diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu index dee993602c313dccf53f71f21d91583da4a6e5de..a531b208902f9e5db458c74893d33809c867edc8 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -472,16 +472,17 @@ Description: information about CPUs heterogeneity. cpu_capacity: capacity of cpu#. What: /sys/devices/system/cpu/vulnerabilities + /sys/devices/system/cpu/vulnerabilities/gather_data_sampling + /sys/devices/system/cpu/vulnerabilities/itlb_multihit + /sys/devices/system/cpu/vulnerabilities/l1tf + /sys/devices/system/cpu/vulnerabilities/mds /sys/devices/system/cpu/vulnerabilities/meltdown + /sys/devices/system/cpu/vulnerabilities/mmio_stale_data + /sys/devices/system/cpu/vulnerabilities/spec_store_bypass /sys/devices/system/cpu/vulnerabilities/spectre_v1 /sys/devices/system/cpu/vulnerabilities/spectre_v2 - /sys/devices/system/cpu/vulnerabilities/spec_store_bypass - /sys/devices/system/cpu/vulnerabilities/l1tf - /sys/devices/system/cpu/vulnerabilities/mds /sys/devices/system/cpu/vulnerabilities/srbds /sys/devices/system/cpu/vulnerabilities/tsx_async_abort - /sys/devices/system/cpu/vulnerabilities/itlb_multihit - /sys/devices/system/cpu/vulnerabilities/mmio_stale_data Date: January 2018 Contact: Linux kernel mailing list Description: Information about CPU vulnerabilities diff --git a/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst b/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst new file mode 100644 index 0000000000000000000000000000000000000000..264bfa937f7de126bdc1622420f459a8170cea86 --- /dev/null +++ b/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst @@ -0,0 +1,109 @@ +.. SPDX-License-Identifier: GPL-2.0 + +GDS - Gather Data Sampling +========================== + +Gather Data Sampling is a hardware vulnerability which allows unprivileged +speculative access to data which was previously stored in vector registers. + +Problem +------- +When a gather instruction performs loads from memory, different data elements +are merged into the destination vector register. However, when a gather +instruction that is transiently executed encounters a fault, stale data from +architectural or internal vector registers may get transiently forwarded to the +destination vector register instead. This will allow a malicious attacker to +infer stale data using typical side channel techniques like cache timing +attacks. GDS is a purely sampling-based attack. + +The attacker uses gather instructions to infer the stale vector register data. +The victim does not need to do anything special other than use the vector +registers. The victim does not need to use gather instructions to be +vulnerable. + +Because the buffers are shared between Hyper-Threads cross Hyper-Thread attacks +are possible. + +Attack scenarios +---------------- +Without mitigation, GDS can infer stale data across virtually all +permission boundaries: + + Non-enclaves can infer SGX enclave data + Userspace can infer kernel data + Guests can infer data from hosts + Guest can infer guest from other guests + Users can infer data from other users + +Because of this, it is important to ensure that the mitigation stays enabled in +lower-privilege contexts like guests and when running outside SGX enclaves. + +The hardware enforces the mitigation for SGX. Likewise, VMMs should ensure +that guests are not allowed to disable the GDS mitigation. If a host erred and +allowed this, a guest could theoretically disable GDS mitigation, mount an +attack, and re-enable it. + +Mitigation mechanism +-------------------- +This issue is mitigated in microcode. The microcode defines the following new +bits: + + ================================ === ============================ + IA32_ARCH_CAPABILITIES[GDS_CTRL] R/O Enumerates GDS vulnerability + and mitigation support. + IA32_ARCH_CAPABILITIES[GDS_NO] R/O Processor is not vulnerable. + IA32_MCU_OPT_CTRL[GDS_MITG_DIS] R/W Disables the mitigation + 0 by default. + IA32_MCU_OPT_CTRL[GDS_MITG_LOCK] R/W Locks GDS_MITG_DIS=0. Writes + to GDS_MITG_DIS are ignored + Can't be cleared once set. + ================================ === ============================ + +GDS can also be mitigated on systems that don't have updated microcode by +disabling AVX. This can be done by setting gather_data_sampling="force" or +"clearcpuid=avx" on the kernel command-line. + +If used, these options will disable AVX use by turning off XSAVE YMM support. +However, the processor will still enumerate AVX support. Userspace that +does not follow proper AVX enumeration to check both AVX *and* XSAVE YMM +support will break. + +Mitigation control on the kernel command line +--------------------------------------------- +The mitigation can be disabled by setting "gather_data_sampling=off" or +"mitigations=off" on the kernel command line. Not specifying either will default +to the mitigation being enabled. Specifying "gather_data_sampling=force" will +use the microcode mitigation when available or disable AVX on affected systems +where the microcode hasn't been updated to include the mitigation. + +GDS System Information +------------------------ +The kernel provides vulnerability status information through sysfs. For +GDS this can be accessed by the following sysfs file: + +/sys/devices/system/cpu/vulnerabilities/gather_data_sampling + +The possible values contained in this file are: + + ============================== ============================================= + Not affected Processor not vulnerable. + Vulnerable Processor vulnerable and mitigation disabled. + Vulnerable: No microcode Processor vulnerable and microcode is missing + mitigation. + Mitigation: AVX disabled, + no microcode Processor is vulnerable and microcode is missing + mitigation. AVX disabled as mitigation. + Mitigation: Microcode Processor is vulnerable and mitigation is in + effect. + Mitigation: Microcode (locked) Processor is vulnerable and mitigation is in + effect and cannot be disabled. + Unknown: Dependent on + hypervisor status Running on a virtual guest processor that is + affected but with no way to know if host + processor is mitigated or vulnerable. + ============================== ============================================= + +GDS Default mitigation +---------------------- +The updated microcode will enable the mitigation by default. The kernel's +default action is to leave the mitigation enabled. diff --git a/Documentation/admin-guide/hw-vuln/index.rst b/Documentation/admin-guide/hw-vuln/index.rst index 2adec1e6520a68e4d6dd9c52bd86f48158e30957..245468b0f2be8014fd70d286fd7c1b01854879d2 100644 --- a/Documentation/admin-guide/hw-vuln/index.rst +++ b/Documentation/admin-guide/hw-vuln/index.rst @@ -16,3 +16,4 @@ are configurable at compile, boot or run time. multihit.rst special-register-buffer-data-sampling.rst processor_mmio_stale_data.rst + gather_data_sampling.rst diff --git a/Documentation/admin-guide/hw-vuln/spectre.rst b/Documentation/admin-guide/hw-vuln/spectre.rst index 7e061ed449aaab9ebfbb4aff73640021aa55e848..0fba3758d0da89273376b126717f8e031cf18630 100644 --- a/Documentation/admin-guide/hw-vuln/spectre.rst +++ b/Documentation/admin-guide/hw-vuln/spectre.rst @@ -479,8 +479,16 @@ Spectre variant 2 On Intel Skylake-era systems the mitigation covers most, but not all, cases. See :ref:`[3] ` for more details. - On CPUs with hardware mitigation for Spectre variant 2 (e.g. Enhanced - IBRS on x86), retpoline is automatically disabled at run time. + On CPUs with hardware mitigation for Spectre variant 2 (e.g. IBRS + or enhanced IBRS on x86), retpoline is automatically disabled at run time. + + Systems which support enhanced IBRS (eIBRS) enable IBRS protection once at + boot, by setting the IBRS bit, and they're automatically protected against + Spectre v2 variant attacks, including cross-thread branch target injections + on SMT systems (STIBP). In other words, eIBRS enables STIBP too. + + Legacy IBRS systems clear the IBRS bit on exit to userspace and + therefore explicitly enable STIBP for that The retpoline mitigation is turned on by default on vulnerable CPUs. It can be forced on or off by the administrator @@ -504,9 +512,12 @@ Spectre variant 2 For Spectre variant 2 mitigation, individual user programs can be compiled with return trampolines for indirect branches. This protects them from consuming poisoned entries in the branch - target buffer left by malicious software. Alternatively, the - programs can disable their indirect branch speculation via prctl() - (See :ref:`Documentation/userspace-api/spec_ctrl.rst `). + target buffer left by malicious software. + + On legacy IBRS systems, at return to userspace, implicit STIBP is disabled + because the kernel clears the IBRS bit. In this case, the userspace programs + can disable indirect branch speculation via prctl() (See + :ref:`Documentation/userspace-api/spec_ctrl.rst `). On x86, this will turn on STIBP to guard against attacks from the sibling thread when the user program is running, and use IBPB to flush the branch target buffer when switching to/from the program. diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 66d09b102bdb0af44512ee0d70c1ef44a27d7871..a4f122cb3c4b994181e9eea1c6a1a031f8313441 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -823,10 +823,6 @@ debugpat [X86] Enable PAT debugging - decnet.addr= [HW,NET] - Format: [,] - See also Documentation/networking/decnet.txt. - default_hugepagesz= [same as hugepagesz=] The size of the default HugeTLB page size. This is the size represented by @@ -1310,6 +1306,26 @@ Format: off | on default: on + gather_data_sampling= + [X86,INTEL] Control the Gather Data Sampling (GDS) + mitigation. + + Gather Data Sampling is a hardware vulnerability which + allows unprivileged speculative access to data which was + previously stored in vector registers. + + This issue is mitigated by default in updated microcode. + The mitigation may have a performance impact but can be + disabled. On systems without the microcode mitigation + disabling AVX serves as a mitigation. + + force: Disable AVX to mitigate systems without + microcode mitigation. No effect if the microcode + mitigation is present. Known to cause crashes in + userspace with buggy AVX enumeration. + + off: Disable GDS mitigation. + gcov_persist= [GCOV] When non-zero (default), profiling data for kernel modules is saved and remains accessible via debugfs, even when the module is unloaded/reloaded. @@ -2584,22 +2600,23 @@ Disable all optional CPU mitigations. This improves system performance, but it may also expose users to several CPU vulnerabilities. - Equivalent to: nopti [X86,PPC] + Equivalent to: gather_data_sampling=off [X86] kpti=0 [ARM64] - nospectre_v1 [PPC] + kvm.nx_huge_pages=off [X86] + l1tf=off [X86] + mds=off [X86] + mmio_stale_data=off [X86] + no_entry_flush [PPC] + no_uaccess_flush [PPC] nobp=0 [S390] + nopti [X86,PPC] + nospectre_v1 [PPC] nospectre_v1 [X86] nospectre_v2 [X86,PPC,S390,ARM64] - spectre_v2_user=off [X86] spec_store_bypass_disable=off [X86,PPC] + spectre_v2_user=off [X86] ssbd=force-off [ARM64] - l1tf=off [X86] - mds=off [X86] tsx_async_abort=off [X86] - kvm.nx_huge_pages=off [X86] - no_entry_flush [PPC] - no_uaccess_flush [PPC] - mmio_stale_data=off [X86] Exceptions: This does not have any effect on diff --git a/Documentation/admin-guide/security-bugs.rst b/Documentation/admin-guide/security-bugs.rst index 30187d49dc2c7d38869c4073e60093d315c3fc4e..67161e1b0f0bde00fa68755ec96b9a23f7592dd3 100644 --- a/Documentation/admin-guide/security-bugs.rst +++ b/Documentation/admin-guide/security-bugs.rst @@ -56,31 +56,28 @@ information submitted to the security list and any followup discussions of the report are treated confidentially even after the embargo has been lifted, in perpetuity. -Coordination ------------- - -Fixes for sensitive bugs, such as those that might lead to privilege -escalations, may need to be coordinated with the private - mailing list so that distribution vendors -are well prepared to issue a fixed kernel upon public disclosure of the -upstream fix. Distros will need some time to test the proposed patch and -will generally request at least a few days of embargo, and vendor update -publication prefers to happen Tuesday through Thursday. When appropriate, -the security team can assist with this coordination, or the reporter can -include linux-distros from the start. In this case, remember to prefix -the email Subject line with "[vs]" as described in the linux-distros wiki: - +Coordination with other groups +------------------------------ + +The kernel security team strongly recommends that reporters of potential +security issues NEVER contact the "linux-distros" mailing list until +AFTER discussing it with the kernel security team. Do not Cc: both +lists at once. You may contact the linux-distros mailing list after a +fix has been agreed on and you fully understand the requirements that +doing so will impose on you and the kernel community. + +The different lists have different goals and the linux-distros rules do +not contribute to actually fixing any potential security problems. CVE assignment -------------- -The security team does not normally assign CVEs, nor do we require them -for reports or fixes, as this can needlessly complicate the process and -may delay the bug handling. If a reporter wishes to have a CVE identifier -assigned ahead of public disclosure, they will need to contact the private -linux-distros list, described above. When such a CVE identifier is known -before a patch is provided, it is desirable to mention it in the commit -message if the reporter agrees. +The security team does not assign CVEs, nor do we require them for +reports or fixes, as this can needlessly complicate the process and may +delay the bug handling. If a reporter wishes to have a CVE identifier +assigned, they should find one by themselves, for example by contacting +MITRE directly. However under no circumstances will a patch inclusion +be delayed to wait for a CVE identifier to arrive. Non-disclosure agreements ------------------------- diff --git a/Documentation/dev-tools/gdb-kernel-debugging.rst b/Documentation/dev-tools/gdb-kernel-debugging.rst index 19df79286f000cac9ef12e1241b496dcce96dbe6..afe4bc206486c9054988a6f834baf9d0ec2f47a2 100644 --- a/Documentation/dev-tools/gdb-kernel-debugging.rst +++ b/Documentation/dev-tools/gdb-kernel-debugging.rst @@ -39,6 +39,10 @@ Setup this mode. In this case, you should build the kernel with CONFIG_RANDOMIZE_BASE disabled if the architecture supports KASLR. +- Build the gdb scripts (required on kernels v5.1 and above):: + + make scripts_gdb + - Enable the gdb stub of QEMU/KVM, either - at VM startup time by appending "-s" to the QEMU command line diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt index 13a7c999c04ab761f81b0e84663b8f38e7bec622..7ab4d71ec83de4339e3950d6a517c7f269430f6d 100644 --- a/Documentation/ioctl/ioctl-number.txt +++ b/Documentation/ioctl/ioctl-number.txt @@ -290,7 +290,6 @@ Code Seq#(hex) Include File Comments 0x89 00-06 arch/x86/include/asm/sockios.h 0x89 0B-DF linux/sockios.h 0x89 E0-EF linux/sockios.h SIOCPROTOPRIVATE range -0x89 E0-EF linux/dn.h PROTOPRIVATE range 0x89 F0-FF linux/sockios.h SIOCDEVPRIVATE range 0x8B all linux/wireless.h 0x8C 00-3F WiNRADiO driver diff --git a/Documentation/media/uapi/v4l/subdev-formats.rst b/Documentation/media/uapi/v4l/subdev-formats.rst index 8e73fcfc690004d8c65c4c7aa9941781ab3655ff..cc2ad8af51ea012c3fe446592781edcaf6c6d553 100644 --- a/Documentation/media/uapi/v4l/subdev-formats.rst +++ b/Documentation/media/uapi/v4l/subdev-formats.rst @@ -7565,3 +7565,30 @@ formats. - 0x5001 - Interleaved raw UYVY and JPEG image format with embedded meta-data used by Samsung S3C73MX camera sensors. + +.. _v4l2-mbus-metadata-fmts: + +Metadata Formats +^^^^^^^^^^^^^^^^ + +This section lists all metadata formats. + +The following table lists the existing metadata formats. + +.. tabularcolumns:: |p{8.0cm}|p{1.4cm}|p{7.7cm}| + +.. flat-table:: Metadata formats + :header-rows: 1 + :stub-columns: 0 + + * - Identifier + - Code + - Comments + * .. _MEDIA-BUS-FMT-METADATA-FIXED: + + - MEDIA_BUS_FMT_METADATA_FIXED + - 0x7001 + - This format should be used when the same driver handles + both sides of the link and the bus format is a fixed + metadata format that is not configurable from userspace. + Width and height will be set to 0 for this format. diff --git a/Documentation/networking/00-INDEX b/Documentation/networking/00-INDEX index 02a323c432612c6a4cb8101390d38f471da09a91..2a9dbac38b4e9382d0b2d9feb62f00ff546cc2ed 100644 --- a/Documentation/networking/00-INDEX +++ b/Documentation/networking/00-INDEX @@ -94,8 +94,8 @@ gianfar.txt - Gianfar Ethernet Driver. i40e.txt - README for the Intel Ethernet Controller XL710 Driver (i40e). -i40evf.txt - - Short note on the Driver for the Intel(R) XL710 X710 Virtual Function +iavf.txt + - README for the Intel Ethernet Adaptive Virtual Function Driver (iavf). ieee802154.txt - Linux IEEE 802.15.4 implementation, API and drivers igb.txt diff --git a/Documentation/networking/decnet.txt b/Documentation/networking/decnet.txt deleted file mode 100644 index e12a4900cf72cb00b1ade4c0257a23c93d2d8f21..0000000000000000000000000000000000000000 --- a/Documentation/networking/decnet.txt +++ /dev/null @@ -1,232 +0,0 @@ - Linux DECnet Networking Layer Information - =========================================== - -1) Other documentation.... - - o Project Home Pages - http://www.chygwyn.com/ - Kernel info - http://linux-decnet.sourceforge.net/ - Userland tools - http://www.sourceforge.net/projects/linux-decnet/ - Status page - -2) Configuring the kernel - -Be sure to turn on the following options: - - CONFIG_DECNET (obviously) - CONFIG_PROC_FS (to see what's going on) - CONFIG_SYSCTL (for easy configuration) - -if you want to try out router support (not properly debugged yet) -you'll need the following options as well... - - CONFIG_DECNET_ROUTER (to be able to add/delete routes) - CONFIG_NETFILTER (will be required for the DECnet routing daemon) - - CONFIG_DECNET_ROUTE_FWMARK is optional - -Don't turn on SIOCGIFCONF support for DECnet unless you are really sure -that you need it, in general you won't and it can cause ifconfig to -malfunction. - -Run time configuration has changed slightly from the 2.4 system. If you -want to configure an endnode, then the simplified procedure is as follows: - - o Set the MAC address on your ethernet card before starting _any_ other - network protocols. - -As soon as your network card is brought into the UP state, DECnet should -start working. If you need something more complicated or are unsure how -to set the MAC address, see the next section. Also all configurations which -worked with 2.4 will work under 2.5 with no change. - -3) Command line options - -You can set a DECnet address on the kernel command line for compatibility -with the 2.4 configuration procedure, but in general it's not needed any more. -If you do st a DECnet address on the command line, it has only one purpose -which is that its added to the addresses on the loopback device. - -With 2.4 kernels, DECnet would only recognise addresses as local if they -were added to the loopback device. In 2.5, any local interface address -can be used to loop back to the local machine. Of course this does not -prevent you adding further addresses to the loopback device if you -want to. - -N.B. Since the address list of an interface determines the addresses for -which "hello" messages are sent, if you don't set an address on the loopback -interface then you won't see any entries in /proc/net/neigh for the local -host until such time as you start a connection. This doesn't affect the -operation of the local communications in any other way though. - -The kernel command line takes options looking like the following: - - decnet.addr=1,2 - -the two numbers are the node address 1,2 = 1.2 For 2.2.xx kernels -and early 2.3.xx kernels, you must use a comma when specifying the -DECnet address like this. For more recent 2.3.xx kernels, you may -use almost any character except space, although a `.` would be the most -obvious choice :-) - -There used to be a third number specifying the node type. This option -has gone away in favour of a per interface node type. This is now set -using /proc/sys/net/decnet/conf//forwarding. This file can be -set with a single digit, 0=EndNode, 1=L1 Router and 2=L2 Router. - -There are also equivalent options for modules. The node address can -also be set through the /proc/sys/net/decnet/ files, as can other system -parameters. - -Currently the only supported devices are ethernet and ip_gre. The -ethernet address of your ethernet card has to be set according to the DECnet -address of the node in order for it to be autoconfigured (and then appear in -/proc/net/decnet_dev). There is a utility available at the above -FTP sites called dn2ethaddr which can compute the correct ethernet -address to use. The address can be set by ifconfig either before or -at the time the device is brought up. If you are using RedHat you can -add the line: - - MACADDR=AA:00:04:00:03:04 - -or something similar, to /etc/sysconfig/network-scripts/ifcfg-eth0 or -wherever your network card's configuration lives. Setting the MAC address -of your ethernet card to an address starting with "hi-ord" will cause a -DECnet address which matches to be added to the interface (which you can -verify with iproute2). - -The default device for routing can be set through the /proc filesystem -by setting /proc/sys/net/decnet/default_device to the -device you want DECnet to route packets out of when no specific route -is available. Usually this will be eth0, for example: - - echo -n "eth0" >/proc/sys/net/decnet/default_device - -If you don't set the default device, then it will default to the first -ethernet card which has been autoconfigured as described above. You can -confirm that by looking in the default_device file of course. - -There is a list of what the other files under /proc/sys/net/decnet/ do -on the kernel patch web site (shown above). - -4) Run time kernel configuration - -This is either done through the sysctl/proc interface (see the kernel web -pages for details on what the various options do) or through the iproute2 -package in the same way as IPv4/6 configuration is performed. - -Documentation for iproute2 is included with the package, although there is -as yet no specific section on DECnet, most of the features apply to both -IP and DECnet, albeit with DECnet addresses instead of IP addresses and -a reduced functionality. - -If you want to configure a DECnet router you'll need the iproute2 package -since its the _only_ way to add and delete routes currently. Eventually -there will be a routing daemon to send and receive routing messages for -each interface and update the kernel routing tables accordingly. The -routing daemon will use netfilter to listen to routing packets, and -rtnetlink to update the kernels routing tables. - -The DECnet raw socket layer has been removed since it was there purely -for use by the routing daemon which will now use netfilter (a much cleaner -and more generic solution) instead. - -5) How can I tell if its working ? - -Here is a quick guide of what to look for in order to know if your DECnet -kernel subsystem is working. - - - Is the node address set (see /proc/sys/net/decnet/node_address) - - Is the node of the correct type - (see /proc/sys/net/decnet/conf//forwarding) - - Is the Ethernet MAC address of each Ethernet card set to match - the DECnet address. If in doubt use the dn2ethaddr utility available - at the ftp archive. - - If the previous two steps are satisfied, and the Ethernet card is up, - you should find that it is listed in /proc/net/decnet_dev and also - that it appears as a directory in /proc/sys/net/decnet/conf/. The - loopback device (lo) should also appear and is required to communicate - within a node. - - If you have any DECnet routers on your network, they should appear - in /proc/net/decnet_neigh, otherwise this file will only contain the - entry for the node itself (if it doesn't check to see if lo is up). - - If you want to send to any node which is not listed in the - /proc/net/decnet_neigh file, you'll need to set the default device - to point to an Ethernet card with connection to a router. This is - again done with the /proc/sys/net/decnet/default_device file. - - Try starting a simple server and client, like the dnping/dnmirror - over the loopback interface. With luck they should communicate. - For this step and those after, you'll need the DECnet library - which can be obtained from the above ftp sites as well as the - actual utilities themselves. - - If this seems to work, then try talking to a node on your local - network, and see if you can obtain the same results. - - At this point you are on your own... :-) - -6) How to send a bug report - -If you've found a bug and want to report it, then there are several things -you can do to help me work out exactly what it is that is wrong. Useful -information (_most_ of which _is_ _essential_) includes: - - - What kernel version are you running ? - - What version of the patch are you running ? - - How far though the above set of tests can you get ? - - What is in the /proc/decnet* files and /proc/sys/net/decnet/* files ? - - Which services are you running ? - - Which client caused the problem ? - - How much data was being transferred ? - - Was the network congested ? - - How can the problem be reproduced ? - - Can you use tcpdump to get a trace ? (N.B. Most (all?) versions of - tcpdump don't understand how to dump DECnet properly, so including - the hex listing of the packet contents is _essential_, usually the -x flag. - You may also need to increase the length grabbed with the -s flag. The - -e flag also provides very useful information (ethernet MAC addresses)) - -7) MAC FAQ - -A quick FAQ on ethernet MAC addresses to explain how Linux and DECnet -interact and how to get the best performance from your hardware. - -Ethernet cards are designed to normally only pass received network frames -to a host computer when they are addressed to it, or to the broadcast address. - -Linux has an interface which allows the setting of extra addresses for -an ethernet card to listen to. If the ethernet card supports it, the -filtering operation will be done in hardware, if not the extra unwanted packets -received will be discarded by the host computer. In the latter case, -significant processor time and bus bandwidth can be used up on a busy -network (see the NAPI documentation for a longer explanation of these -effects). - -DECnet makes use of this interface to allow running DECnet on an ethernet -card which has already been configured using TCP/IP (presumably using the -built in MAC address of the card, as usual) and/or to allow multiple DECnet -addresses on each physical interface. If you do this, be aware that if your -ethernet card doesn't support perfect hashing in its MAC address filter -then your computer will be doing more work than required. Some cards -will simply set themselves into promiscuous mode in order to receive -packets from the DECnet specified addresses. So if you have one of these -cards its better to set the MAC address of the card as described above -to gain the best efficiency. Better still is to use a card which supports -NAPI as well. - - -8) Mailing list - -If you are keen to get involved in development, or want to ask questions -about configuration, or even just report bugs, then there is a mailing -list that you can join, details are at: - -http://sourceforge.net/mail/?group_id=4993 - -9) Legal Info - -The Linux DECnet project team have placed their code under the GPL. The -software is provided "as is" and without warranty express or implied. -DECnet is a trademark of Compaq. This software is not a product of -Compaq. We acknowledge the help of people at Compaq in providing extra -documentation above and beyond what was previously publicly available. - -Steve Whitehouse - diff --git a/Documentation/networking/i40evf.txt b/Documentation/networking/iavf.txt similarity index 72% rename from Documentation/networking/i40evf.txt rename to Documentation/networking/iavf.txt index e9b3035b95d05bdbf6213b78317402606c1530ac..cc902a2369d69a1ecf3d9bfb26e6537a1a18f8d1 100644 --- a/Documentation/networking/i40evf.txt +++ b/Documentation/networking/iavf.txt @@ -2,7 +2,7 @@ Linux* Base Driver for Intel(R) Network Connection ================================================== Intel Ethernet Adaptive Virtual Function Linux driver. -Copyright(c) 2013-2017 Intel Corporation. +Copyright(c) 2013-2018 Intel Corporation. Contents ======== @@ -11,20 +11,21 @@ Contents - Known Issues/Troubleshooting - Support -This file describes the i40evf Linux* Base Driver. +This file describes the iavf Linux* Base Driver. This driver +was formerly called i40evf. -The i40evf driver supports the below mentioned virtual function +The iavf driver supports the below mentioned virtual function devices and can only be activated on kernels running the i40e or newer Physical Function (PF) driver compiled with CONFIG_PCI_IOV. -The i40evf driver requires CONFIG_PCI_MSI to be enabled. +The iavf driver requires CONFIG_PCI_MSI to be enabled. -The guest OS loading the i40evf driver must support MSI-X interrupts. +The guest OS loading the iavf driver must support MSI-X interrupts. Supported Hardware ================== Intel XL710 X710 Virtual Function -Intel Ethernet Adaptive Virtual Function Intel X722 Virtual Function +Intel Ethernet Adaptive Virtual Function Identifying Your Adapter ======================== @@ -32,7 +33,8 @@ Identifying Your Adapter For more information on how to identify your adapter, go to the Adapter & Driver ID Guide at: - http://support.intel.com/support/go/network/adapter/idguide.htm + https://www.intel.com/content/www/us/en/support/articles/000005584/network-and-i-o/ethernet-products.html + Known Issues/Troubleshooting ============================ diff --git a/Documentation/sound/hd-audio/models.rst b/Documentation/sound/hd-audio/models.rst index 8c0de54b5649b7f6d6e804ea40e4b23f185c4121..5aa24f7b78ed90f974d5bbc65bd97233c1fb319f 100644 --- a/Documentation/sound/hd-audio/models.rst +++ b/Documentation/sound/hd-audio/models.rst @@ -691,7 +691,7 @@ ref no-jd BIOS setup but without jack-detection intel - Intel DG45* mobos + Intel D*45* mobos dell-m6-amic Dell desktops/laptops with analog mics dell-m6-dmic diff --git a/Documentation/sysctl/net.txt b/Documentation/sysctl/net.txt index 2793d4eac55fd7e12993b3045657fd4156499d06..57e08f16b4e3860dd1ba240dd46535ce109cc756 100644 --- a/Documentation/sysctl/net.txt +++ b/Documentation/sysctl/net.txt @@ -25,7 +25,6 @@ Table : Subdirectories in /proc/sys/net ethernet Ethernet protocol rose X.25 PLP layer ipv4 IP version 4 x25 X.25 protocol ipx IPX token-ring IBM token ring - bridge Bridging decnet DEC net ipv6 IP version 6 tipc TIPC .............................................................................. diff --git a/MAINTAINERS b/MAINTAINERS index 22885645793e1b66f5812aa5dd2ba7d1d9830708..75aec8d6f154db8fbd953ff397cb12349f084df2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -182,7 +182,7 @@ F: drivers/net/hamradio/6pack.c M: Realtek linux nic maintainers L: netdev@vger.kernel.org S: Maintained -F: drivers/net/ethernet/realtek/r8169.c +F: drivers/net/ethernet/realtek/r8169* 8250/16?50 (AND CLONE UARTS) SERIAL DRIVER M: Greg Kroah-Hartman @@ -1186,7 +1186,7 @@ N: owl F: arch/arm/mach-actions/ F: arch/arm/boot/dts/owl-* F: arch/arm64/boot/dts/actions/ -F: drivers/clocksource/owl-* +F: drivers/clocksource/timer-owl* F: drivers/pinctrl/actions/* F: drivers/soc/actions/ F: include/dt-bindings/power/owl-* @@ -1609,7 +1609,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/boot/dts/lpc43* F: drivers/clk/nxp/clk-lpc18xx* -F: drivers/clocksource/time-lpc32xx.c +F: drivers/clocksource/timer-lpc32xx.c F: drivers/i2c/busses/i2c-lpc2k.c F: drivers/memory/pl172.c F: drivers/mtd/spi-nor/nxp-spifi.c @@ -2225,7 +2225,7 @@ F: arch/arm/mach-vexpress/ F: */*/vexpress* F: */*/*/vexpress* F: drivers/clk/versatile/clk-vexpress-osc.c -F: drivers/clocksource/versatile.c +F: drivers/clocksource/timer-versatile.c N: mps2 ARM/VFP SUPPORT @@ -2247,7 +2247,7 @@ M: Tony Prisk L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-vt8500/ -F: drivers/clocksource/vt8500_timer.c +F: drivers/clocksource/timer-vt8500.c F: drivers/i2c/busses/i2c-wmt.c F: drivers/mmc/host/wmt-sdmmc.c F: drivers/pwm/pwm-vt8500.c @@ -2312,7 +2312,7 @@ F: drivers/cpuidle/cpuidle-zynq.c F: drivers/block/xsysace.c N: zynq N: xilinx -F: drivers/clocksource/cadence_ttc_timer.c +F: drivers/clocksource/timer-cadence-ttc.c F: drivers/i2c/busses/i2c-cadence.c F: drivers/mmc/host/sdhci-of-arasan.c F: drivers/edac/synopsys_edac.c @@ -4159,13 +4159,6 @@ F: include/uapi/linux/dccp.h F: include/linux/tfrc.h F: net/dccp/ -DECnet NETWORK LAYER -W: http://linux-decnet.sourceforge.net -L: linux-decnet-user@lists.sourceforge.net -S: Orphan -F: Documentation/networking/decnet.txt -F: net/decnet/ - DECSTATION PLATFORM SUPPORT M: "Maciej W. Rozycki" L: linux-mips@linux-mips.org @@ -7411,7 +7404,7 @@ F: Documentation/networking/ixgb.txt F: Documentation/networking/ixgbe.txt F: Documentation/networking/ixgbevf.txt F: Documentation/networking/i40e.txt -F: Documentation/networking/i40evf.txt +F: Documentation/networking/iavf.txt F: Documentation/networking/ice.txt F: drivers/net/ethernet/intel/ F: drivers/net/ethernet/intel/*/ diff --git a/Makefile b/Makefile index 88fc3f98f098d7c4b35a614261eaf5f8594b9dff..276f6ecc3ed8a2909538ec716c9e8a378b1036a7 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 275 +SUBLEVEL = 300 EXTRAVERSION = NAME = "People's Front" @@ -88,10 +88,17 @@ endif # If the user is running make -s (silent mode), suppress echoing of # commands +# make-4.0 (and later) keep single letter options in the 1st word of MAKEFLAGS. -ifneq ($(findstring s,$(filter-out --%,$(MAKEFLAGS))),) - quiet=silent_ - tools_silent=s +ifeq ($(filter 3.%,$(MAKE_VERSION)),) +silence:=$(findstring s,$(firstword -$(MAKEFLAGS))) +else +silence:=$(findstring s,$(filter-out --%,$(MAKEFLAGS))) +endif + +ifeq ($(silence),s) +quiet=silent_ +tools_silent=s endif export quiet Q KBUILD_VERBOSE @@ -772,6 +779,10 @@ else KBUILD_CFLAGS += -O2 endif +ifdef CONFIG_CC_WERROR +KBUILD_CFLAGS += -Werror +endif + # Tell gcc to never replace conditional load with a non-conditional one KBUILD_CFLAGS += $(call cc-option,--param=allow-store-data-races=0) KBUILD_CFLAGS += $(call cc-option,-fno-allow-store-data-races) @@ -840,6 +851,10 @@ endif KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable) KBUILD_CFLAGS += $(call cc-disable-warning, unused-const-variable) + +# These result in bogus false positives +KBUILD_CFLAGS += $(call cc-disable-warning, dangling-pointer) + ifdef CONFIG_FRAME_POINTER KBUILD_CFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls else diff --git a/android/abi_gki_aarch64.xml b/android/abi_gki_aarch64.xml index 4c410fd1a030629e3a7bff558510a623c2b09b64..20921dd6c6f611632dcaf1294130100930c8ad13 100644 --- a/android/abi_gki_aarch64.xml +++ b/android/abi_gki_aarch64.xml @@ -1357,6 +1357,7 @@ + @@ -2903,7 +2904,7 @@ - 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+ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -132757,45 +132771,45 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -132820,15 +132834,15 @@ - + - + - + - + @@ -132836,23 +132850,23 @@ - + - + - + - + - + - + - + @@ -132861,90 +132875,90 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -132956,174 +132970,174 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -133134,287 +133148,287 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -133425,285 +133439,285 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -133712,12 +133726,12 @@ - + - + - + @@ -133729,68 +133743,68 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -133799,99 +133813,99 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -133902,15 +133916,15 @@ - + - + - + - + @@ -133921,26 +133935,26 @@ - + - + - + - + - + - + - + - + @@ -133948,145 +133962,145 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -134097,46 +134111,46 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -134144,18 +134158,18 @@ - + - + - + - + - + @@ -134370,7 +134384,7 @@ - + @@ -135459,21 +135473,21 @@ - + - + - + - + - + - + @@ -135612,7 +135626,7 @@ - + @@ -135626,33 +135640,33 @@ - + - + - + - + - + - + - + - + - + - + @@ -136088,50 +136102,50 @@ - - - + + + - - - + + + - - - - - - - - + + + + + + + + - - - - - - - - - - - + + + + + + + + + + + - - - - - - + + + + + + - - - + + + @@ -136151,56 +136165,56 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -136210,53 +136224,53 @@ - + - + - + - + - + - + - + - + - + - - - - + + + + - - - - + + + + - - - - - - - + + + + + + + @@ -136295,11 +136309,11 @@ - - - - - + + + + + @@ -136345,37 +136359,37 @@ - - - + + + - - - + + + - - - + + + - - - + + + - - - - - + + + + + - - - - + + + + @@ -136416,7 +136430,7 @@ - + @@ -142423,31 +142437,31 @@ - - - + + + - - - + + + - - - + + + - - - + + + - - - - - + + + + + @@ -143055,7 +143069,7 @@ - + diff --git a/android/abi_gki_aarch64_qcom b/android/abi_gki_aarch64_qcom index 9d864fd5d672bb8438419d56edb9c77c87c94010..e8b40355894b6664b2f935ce9b0859cd6dad9573 100644 --- a/android/abi_gki_aarch64_qcom +++ b/android/abi_gki_aarch64_qcom @@ -1426,6 +1426,7 @@ kernel_read kernel_write kern_path + kill_anon_super kobject_add kobject_init kobj_sysfs_ops diff --git a/arch/Kconfig b/arch/Kconfig index b892d0781c4e2303f41109a53e8c0b3d4b53483c..4f3b10cff567344c7860ad6e80c1ab5a78e755d9 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -249,6 +249,9 @@ config ARCH_HAS_FORTIFY_SOURCE config ARCH_HAS_SET_MEMORY bool +config ARCH_HAS_CPU_FINALIZE_INIT + bool + # Select if arch init_task must go in the __init_task_data section config ARCH_TASK_STRUCT_ON_STACK bool diff --git a/arch/alpha/include/asm/bugs.h b/arch/alpha/include/asm/bugs.h deleted file mode 100644 index 78030d1c7e7e0210520a57200ecbde11a76c21e5..0000000000000000000000000000000000000000 --- a/arch/alpha/include/asm/bugs.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * include/asm-alpha/bugs.h - * - * Copyright (C) 1994 Linus Torvalds - */ - -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ - -/* - * I don't know of any alpha bugs yet.. Nice chip - */ - -static void check_bugs(void) -{ -} diff --git a/arch/alpha/kernel/module.c b/arch/alpha/kernel/module.c index 47632fa8c24e02418cdbac8d5c139f101aa51945..b169dc9a9ac17e34595ff735f07ab52ac0a2ddf3 100644 --- a/arch/alpha/kernel/module.c +++ b/arch/alpha/kernel/module.c @@ -158,10 +158,8 @@ apply_relocate_add(Elf64_Shdr *sechdrs, const char *strtab, base = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr; symtab = (Elf64_Sym *)sechdrs[symindex].sh_addr; - /* The small sections were sorted to the end of the segment. - The following should definitely cover them. */ - gp = (u64)me->core_layout.base + me->core_layout.size - 0x8000; got = sechdrs[me->arch.gotsecindex].sh_addr; + gp = got + 0x8000; for (i = 0; i < n; i++) { unsigned long r_sym = ELF64_R_SYM (rela[i].r_info); diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c index 5576f7646fb6b4b8e736e39f96b7ef1fa7c3d4bc..60f7e45d3aa8952d905b8a807863dd1da8f3cac9 100644 --- a/arch/alpha/kernel/setup.c +++ b/arch/alpha/kernel/setup.c @@ -469,8 +469,7 @@ setup_memory(void *kernel_end) extern void setup_memory(void *); #endif /* !CONFIG_DISCONTIGMEM */ -int __init -page_is_ram(unsigned long pfn) +int page_is_ram(unsigned long pfn) { struct memclust_struct * cluster; struct memdesc_struct * memdesc; diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c index 22f5c27b96b7cbb152fe826d0c75763b3a1ee080..e2c96f309881cd53c2826f1097f844b12a432c18 100644 --- a/arch/alpha/kernel/traps.c +++ b/arch/alpha/kernel/traps.c @@ -235,7 +235,21 @@ do_entIF(unsigned long type, struct pt_regs *regs) { int signo, code; - if ((regs->ps & ~IPL_MAX) == 0) { + if (type == 3) { /* FEN fault */ + /* Irritating users can call PAL_clrfen to disable the + FPU for the process. The kernel will then trap in + do_switch_stack and undo_switch_stack when we try + to save and restore the FP registers. + + Given that GCC by default generates code that uses the + FP registers, PAL_clrfen is not useful except for DoS + attacks. So turn the bleeding FPU back on and be done + with it. */ + current_thread_info()->pcb.flags |= 1; + __reload_thread(¤t_thread_info()->pcb); + return; + } + if (!user_mode(regs)) { if (type == 1) { const unsigned int *data = (const unsigned int *) regs->pc; @@ -368,20 +382,6 @@ do_entIF(unsigned long type, struct pt_regs *regs) } break; - case 3: /* FEN fault */ - /* Irritating users can call PAL_clrfen to disable the - FPU for the process. The kernel will then trap in - do_switch_stack and undo_switch_stack when we try - to save and restore the FP registers. - - Given that GCC by default generates code that uses the - FP registers, PAL_clrfen is not useful except for DoS - attacks. So turn the bleeding FPU back on and be done - with it. */ - current_thread_info()->pcb.flags |= 1; - __reload_thread(¤t_thread_info()->pcb); - return; - case 5: /* illoc */ default: /* unexpected instruction-fault type */ ; diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h index 225e7df2d8ed8f71932ea5abccaa3390a624c16d..0733752ce7fe88b9044038b76decd9e411e0565b 100644 --- a/arch/arc/include/asm/entry-arcv2.h +++ b/arch/arc/include/asm/entry-arcv2.h @@ -7,232 +7,252 @@ #include #include /* For THREAD_SIZE */ +/* + * Interrupt/Exception stack layout (pt_regs) for ARCv2 + * (End of struct aligned to end of page [unless nested]) + * + * INTERRUPT EXCEPTION + * + * manual --------------------- manual + * | orig_r0 | + * | event/ECR | + * | bta | + * | user_r25 | + * | gp | + * | fp | + * | sp | + * | r12 | + * | r30 | + * | r58 | + * | r59 | + * hw autosave --------------------- + * optional | r0 | + * | r1 | + * ~ ~ + * | r9 | + * | r10 | + * | r11 | + * | blink | + * | lpe | + * | lps | + * | lpc | + * | ei base | + * | ldi base | + * | jli base | + * --------------------- + * hw autosave | pc / eret | + * mandatory | stat32 / erstatus | + * --------------------- + */ + /*------------------------------------------------------------------------*/ -.macro INTERRUPT_PROLOGUE called_from +.macro INTERRUPT_PROLOGUE - ; Before jumping to Interrupt Vector, hardware micro-ops did following: + ; (A) Before jumping to Interrupt Vector, hardware micro-ops did following: ; 1. SP auto-switched to kernel mode stack - ; 2. STATUS32.Z flag set to U mode at time of interrupt (U:1, K:0) - ; 3. Auto saved: r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI, PC, STAT32 + ; 2. STATUS32.Z flag set if in U mode at time of interrupt (U:1,K:0) + ; 3. Auto save: (mandatory) Push PC and STAT32 on stack + ; hardware does even if CONFIG_ARC_IRQ_NO_AUTOSAVE + ; 4. Auto save: (optional) r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI ; - ; Now manually save: r12, sp, fp, gp, r25 + ; (B) Manually saved some regs: r12,r25,r30, sp,fp,gp, ACCL pair #ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE -.ifnc \called_from, exception - st.as r9, [sp, -10] ; save r9 in it's final stack slot - sub sp, sp, 12 ; skip JLI, LDI, EI - - PUSH lp_count - PUSHAX lp_start - PUSHAX lp_end - PUSH blink - - PUSH r11 - PUSH r10 - - sub sp, sp, 4 ; skip r9 - - PUSH r8 - PUSH r7 - PUSH r6 - PUSH r5 - PUSH r4 - PUSH r3 - PUSH r2 - PUSH r1 - PUSH r0 -.endif -#endif + ; carve pt_regs on stack (case #3), PC/STAT32 already on stack + sub sp, sp, SZ_PT_REGS - 8 -#ifdef CONFIG_ARC_HAS_ACCL_REGS - PUSH r59 - PUSH r58 + __SAVE_REGFILE_HARD +#else + ; carve pt_regs on stack (case #4), which grew partially already + sub sp, sp, PT_r0 #endif - PUSH r30 - PUSH r12 + __SAVE_REGFILE_SOFT +.endm + +/*------------------------------------------------------------------------*/ +.macro EXCEPTION_PROLOGUE + + ; (A) Before jumping to Exception Vector, hardware micro-ops did following: + ; 1. SP auto-switched to kernel mode stack + ; 2. STATUS32.Z flag set if in U mode at time of exception (U:1,K:0) + ; + ; (B) Manually save the complete reg file below + + sub sp, sp, SZ_PT_REGS ; carve pt_regs + + ; _HARD saves r10 clobbered by _SOFT as scratch hence comes first + + __SAVE_REGFILE_HARD + __SAVE_REGFILE_SOFT + + st r0, [sp] ; orig_r0 + + lr r10, [eret] + lr r11, [erstatus] + ST2 r10, r11, PT_ret + + lr r10, [ecr] + lr r11, [erbta] + ST2 r10, r11, PT_event + mov r9, r10 + + ; OUTPUT: r9 has ECR +.endm + +/*------------------------------------------------------------------------ + * This macro saves the registers manually which would normally be autosaved + * by hardware on taken interrupts. It is used by + * - exception handlers (which don't have autosave) + * - interrupt autosave disabled due to CONFIG_ARC_IRQ_NO_AUTOSAVE + */ +.macro __SAVE_REGFILE_HARD + + ST2 r0, r1, PT_r0 + ST2 r2, r3, PT_r2 + ST2 r4, r5, PT_r4 + ST2 r6, r7, PT_r6 + ST2 r8, r9, PT_r8 + ST2 r10, r11, PT_r10 + + st blink, [sp, PT_blink] + + lr r10, [lp_end] + lr r11, [lp_start] + ST2 r10, r11, PT_lpe + + st lp_count, [sp, PT_lpc] + + ; skip JLI, LDI, EI for now +.endm + +/*------------------------------------------------------------------------ + * This macros saves a bunch of other registers which can't be autosaved for + * various reasons: + * - r12: the last caller saved scratch reg since hardware saves in pairs so r0-r11 + * - r30: free reg, used by gcc as scratch + * - ACCL/ACCH pair when they exist + */ +.macro __SAVE_REGFILE_SOFT + + ST2 gp, fp, PT_r26 ; gp (r26), fp (r27) + + st r12, [sp, PT_sp + 4] + st r30, [sp, PT_sp + 8] ; Saving pt_regs->sp correctly requires some extra work due to the way ; Auto stack switch works ; - U mode: retrieve it from AUX_USER_SP ; - K mode: add the offset from current SP where H/w starts auto push ; - ; Utilize the fact that Z bit is set if Intr taken in U mode - mov.nz r9, sp - add.nz r9, r9, SZ_PT_REGS - PT_sp - 4 - bnz 1f + ; 1. Utilize the fact that Z bit is set if Intr taken in U mode + ; 2. Upon entry SP is always saved (for any inspection, unwinding etc), + ; but on return, restored only if U mode - lr r9, [AUX_USER_SP] -1: - PUSH r9 ; SP + lr r10, [AUX_USER_SP] ; U mode SP + + ; ISA requires ADD.nz to have same dest and src reg operands + mov.nz r10, sp + add.nz r10, r10, SZ_PT_REGS ; K mode SP - PUSH fp - PUSH gp + st r10, [sp, PT_sp] ; SP (pt_regs->sp) #ifdef CONFIG_ARC_CURR_IN_REG - PUSH r25 ; user_r25 + st r25, [sp, PT_user_r25] GET_CURR_TASK_ON_CPU r25 -#else - sub sp, sp, 4 #endif -.ifnc \called_from, exception - sub sp, sp, 12 ; BTA/ECR/orig_r0 placeholder per pt_regs -.endif +#ifdef CONFIG_ARC_HAS_ACCL_REGS + ST2 r58, r59, PT_sp + 12 +#endif .endm /*------------------------------------------------------------------------*/ -.macro INTERRUPT_EPILOGUE called_from +.macro __RESTORE_REGFILE_SOFT -.ifnc \called_from, exception - add sp, sp, 12 ; skip BTA/ECR/orig_r0 placeholderss -.endif + LD2 gp, fp, PT_r26 ; gp (r26), fp (r27) -#ifdef CONFIG_ARC_CURR_IN_REG - POP r25 -#else - add sp, sp, 4 -#endif + ld r12, [sp, PT_sp + 4] + ld r30, [sp, PT_sp + 8] - POP gp - POP fp - - ; Don't touch AUX_USER_SP if returning to K mode (Z bit set) - ; (Z bit set on K mode is inverse of INTERRUPT_PROLOGUE) - add.z sp, sp, 4 + ; Restore SP (into AUX_USER_SP) only if returning to U mode + ; - for K mode, it will be implicitly restored as stack is unwound + ; - Z flag set on K is inverse of what hardware does on interrupt entry + ; but that doesn't really matter bz 1f - POPAX AUX_USER_SP + ld r10, [sp, PT_sp] ; SP (pt_regs->sp) + sr r10, [AUX_USER_SP] 1: - POP r12 - POP r30 -#ifdef CONFIG_ARC_HAS_ACCL_REGS - POP r58 - POP r59 +#ifdef CONFIG_ARC_CURR_IN_REG + ld r25, [sp, PT_user_r25] #endif -#ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE -.ifnc \called_from, exception - POP r0 - POP r1 - POP r2 - POP r3 - POP r4 - POP r5 - POP r6 - POP r7 - POP r8 - POP r9 - POP r10 - POP r11 - - POP blink - POPAX lp_end - POPAX lp_start - - POP r9 - mov lp_count, r9 - - add sp, sp, 12 ; skip JLI, LDI, EI - ld.as r9, [sp, -10] ; reload r9 which got clobbered -.endif +#ifdef CONFIG_ARC_HAS_ACCL_REGS + LD2 r58, r59, PT_sp + 12 #endif +.endm +/*------------------------------------------------------------------------*/ +.macro __RESTORE_REGFILE_HARD + + ld blink, [sp, PT_blink] + + LD2 r10, r11, PT_lpe + sr r10, [lp_end] + sr r11, [lp_start] + + ld r10, [sp, PT_lpc] ; lp_count can't be target of LD + mov lp_count, r10 + + LD2 r0, r1, PT_r0 + LD2 r2, r3, PT_r2 + LD2 r4, r5, PT_r4 + LD2 r6, r7, PT_r6 + LD2 r8, r9, PT_r8 + LD2 r10, r11, PT_r10 .endm + /*------------------------------------------------------------------------*/ -.macro EXCEPTION_PROLOGUE +.macro INTERRUPT_EPILOGUE - ; Before jumping to Exception Vector, hardware micro-ops did following: - ; 1. SP auto-switched to kernel mode stack - ; 2. STATUS32.Z flag set to U mode at time of interrupt (U:1,K:0) - ; - ; Now manually save the complete reg file - - PUSH r9 ; freeup a register: slot of erstatus - - PUSHAX eret - sub sp, sp, 12 ; skip JLI, LDI, EI - PUSH lp_count - PUSHAX lp_start - PUSHAX lp_end - PUSH blink - - PUSH r11 - PUSH r10 - - ld.as r9, [sp, 10] ; load stashed r9 (status32 stack slot) - lr r10, [erstatus] - st.as r10, [sp, 10] ; save status32 at it's right stack slot - - PUSH r9 - PUSH r8 - PUSH r7 - PUSH r6 - PUSH r5 - PUSH r4 - PUSH r3 - PUSH r2 - PUSH r1 - PUSH r0 - - ; -- for interrupts, regs above are auto-saved by h/w in that order -- - ; Now do what ISR prologue does (manually save r12, sp, fp, gp, r25) - ; - ; Set Z flag if this was from U mode (expected by INTERRUPT_PROLOGUE) - ; Although H/w exception micro-ops do set Z flag for U mode (just like - ; for interrupts), it could get clobbered in case we soft land here from - ; a TLB Miss exception handler (tlbex.S) + ; INPUT: r0 has STAT32 of calling context + ; INPUT: Z flag set if returning to K mode - and r10, r10, STATUS_U_MASK - xor.f 0, r10, STATUS_U_MASK + ; _SOFT clobbers r10 restored by _HARD hence the order - INTERRUPT_PROLOGUE exception + __RESTORE_REGFILE_SOFT - PUSHAX erbta - PUSHAX ecr ; r9 contains ECR, expected by EV_Trap +#ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE + __RESTORE_REGFILE_HARD + add sp, sp, SZ_PT_REGS - 8 +#else + add sp, sp, PT_r0 +#endif - PUSH r0 ; orig_r0 .endm /*------------------------------------------------------------------------*/ .macro EXCEPTION_EPILOGUE - ; Assumes r0 has PT_status32 - btst r0, STATUS_U_BIT ; Z flag set if K, used in INTERRUPT_EPILOGUE - - add sp, sp, 8 ; orig_r0/ECR don't need restoring - POPAX erbta - - INTERRUPT_EPILOGUE exception + ; INPUT: r0 has STAT32 of calling context - POP r0 - POP r1 - POP r2 - POP r3 - POP r4 - POP r5 - POP r6 - POP r7 - POP r8 - POP r9 - POP r10 - POP r11 + btst r0, STATUS_U_BIT ; Z flag set if K, used in restoring SP - POP blink - POPAX lp_end - POPAX lp_start + ld r10, [sp, PT_event + 4] + sr r10, [erbta] - POP r9 - mov lp_count, r9 + LD2 r10, r11, PT_ret + sr r10, [eret] + sr r11, [erstatus] - add sp, sp, 12 ; skip JLI, LDI, EI - POPAX eret - POPAX erstatus + __RESTORE_REGFILE_SOFT + __RESTORE_REGFILE_HARD - ld.as r9, [sp, -12] ; reload r9 which got clobbered + add sp, sp, SZ_PT_REGS .endm .macro FAKE_RET_FROM_EXCPN diff --git a/arch/arc/include/asm/linkage.h b/arch/arc/include/asm/linkage.h index 07c8e1a6c56e25dd40463107809e40491baac77c..b89ca8b4d597552283fa38c346c32b704f74d9b0 100644 --- a/arch/arc/include/asm/linkage.h +++ b/arch/arc/include/asm/linkage.h @@ -11,12 +11,30 @@ #include -#ifdef __ASSEMBLY__ - #define ASM_NL ` /* use '`' to mark new line in macro */ #define __ALIGN .align 4 #define __ALIGN_STR __stringify(__ALIGN) +#ifdef __ASSEMBLY__ + +.macro ST2 e, o, off +#ifdef CONFIG_ARC_HAS_LL64 + std \e, [sp, \off] +#else + st \e, [sp, \off] + st \o, [sp, \off+4] +#endif +.endm + +.macro LD2 e, o, off +#ifdef CONFIG_ARC_HAS_LL64 + ldd \e, [sp, \off] +#else + ld \e, [sp, \off] + ld \o, [sp, \off+4] +#endif +.endm + /* annotation for data we want in DCCM - if enabled in .config */ .macro ARCFP_DATA nm #ifdef CONFIG_ARC_HAS_DCCM diff --git a/arch/arc/kernel/asm-offsets.c b/arch/arc/kernel/asm-offsets.c index ecaf34e9235c20dba4729d79321bef0d3b462a37..e90dccecfd833d91254dcd9918d3b298ab271a50 100644 --- a/arch/arc/kernel/asm-offsets.c +++ b/arch/arc/kernel/asm-offsets.c @@ -58,7 +58,14 @@ int main(void) DEFINE(PT_r5, offsetof(struct pt_regs, r5)); DEFINE(PT_r6, offsetof(struct pt_regs, r6)); DEFINE(PT_r7, offsetof(struct pt_regs, r7)); + DEFINE(PT_r8, offsetof(struct pt_regs, r8)); + DEFINE(PT_r10, offsetof(struct pt_regs, r10)); + DEFINE(PT_r26, offsetof(struct pt_regs, r26)); DEFINE(PT_ret, offsetof(struct pt_regs, ret)); + DEFINE(PT_blink, offsetof(struct pt_regs, blink)); + DEFINE(PT_lpe, offsetof(struct pt_regs, lp_end)); + DEFINE(PT_lpc, offsetof(struct pt_regs, lp_count)); + DEFINE(PT_user_r25, offsetof(struct pt_regs, user_r25)); DEFINE(SZ_CALLEE_REGS, sizeof(struct callee_regs)); DEFINE(SZ_PT_REGS, sizeof(struct pt_regs)); diff --git a/arch/arc/kernel/entry-arcv2.S b/arch/arc/kernel/entry-arcv2.S index 562089d62d9d68cf6fd0be3e9c1e607dfb1decc5..6cbf0ee8a20a7da730d71e4a87549498f42b45e8 100644 --- a/arch/arc/kernel/entry-arcv2.S +++ b/arch/arc/kernel/entry-arcv2.S @@ -70,7 +70,7 @@ reserved: ENTRY(handle_interrupt) - INTERRUPT_PROLOGUE irq + INTERRUPT_PROLOGUE # irq control APIs local_irq_save/restore/disable/enable fiddle with # global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio) @@ -226,7 +226,7 @@ debug_marker_l1: bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U sr r11, [AUX_IRQ_ACT] - INTERRUPT_EPILOGUE irq + INTERRUPT_EPILOGUE rtie ;####### Return from Exception / pure kernel mode ####### diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index 0e1e47a67c73617232c4ed62ca96c2ac74286975..e50cac799a51889e8e582c6e450d94da1158cf3f 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -396,6 +396,17 @@ EV_TLBMissD_fast_ret: ; additional label for VDK OS-kit instrumentation ;-------- Common routine to call Linux Page Fault Handler ----------- do_slow_path_pf: +#ifdef CONFIG_ISA_ARCV2 + ; Set Z flag if exception in U mode. Hardware micro-ops do this on any + ; taken interrupt/exception, and thus is already the case at the entry + ; above, but ensuing code would have already clobbered. + ; EXCEPTION_PROLOGUE called in slow path, relies on correct Z flag set + + lr r2, [erstatus] + and r2, r2, STATUS_U_MASK + bxor.f 0, r2, STATUS_U_BIT +#endif + ; Restore the 4-scratch regs saved by fast path miss handler TLBMISS_RESTORE_REGS diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8d2b2c9ad134c128007eec07b416e9228517b0e4..ed7281da847355bb5aaf9f3c834d5c8fb3f32ed9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -4,6 +4,7 @@ config ARM default y select ARCH_CLOCKSOURCE_DATA select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC + select ARCH_HAS_CPU_FINALIZE_INIT if MMU select ARCH_HAS_DEBUG_VIRTUAL if MMU select ARCH_HAS_DEVMEM_IS_ALLOWED select ARCH_HAS_ELF_RANDOMIZE diff --git a/arch/arm/boot/bootp/init.S b/arch/arm/boot/bootp/init.S index 78b508075161fd4967bdbb3821eab162aa9dd5bc..868eeeaaa46e2646ce602b79ec2866767ae4f4d8 100644 --- a/arch/arm/boot/bootp/init.S +++ b/arch/arm/boot/bootp/init.S @@ -16,7 +16,7 @@ * size immediately following the kernel, we could build this into * a binary blob, and concatenate the zImage using the cat command. */ - .section .start,#alloc,#execinstr + .section .start, "ax" .type _start, #function .globl _start diff --git a/arch/arm/boot/compressed/big-endian.S b/arch/arm/boot/compressed/big-endian.S index 88e2a88d324b2535a6610c1a914e81ef3a010b8b..0e092c36da2f2791d564b5c4aa4aa6dccb859dc7 100644 --- a/arch/arm/boot/compressed/big-endian.S +++ b/arch/arm/boot/compressed/big-endian.S @@ -6,7 +6,7 @@ * Author: Nicolas Pitre */ - .section ".start", #alloc, #execinstr + .section ".start", "ax" mrc p15, 0, r0, c1, c0, 0 @ read control reg orr r0, r0, #(1 << 7) @ enable big endian mode diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index b83eb053320f5223eb0fc67f147b24186b7eb947..39c85df1a41fa6465c0987ebd701483a29d37d3a 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -121,7 +121,7 @@ #endif .endm - .section ".start", #alloc, #execinstr + .section ".start", "ax" /* * sort out different calling conventions */ diff --git a/arch/arm/boot/compressed/piggy.S b/arch/arm/boot/compressed/piggy.S index 0284f84dcf38049f643c144d4f86dd76df88fabe..27577644ee721a861b87e2f68e48ebb3aaff2cf3 100644 --- a/arch/arm/boot/compressed/piggy.S +++ b/arch/arm/boot/compressed/piggy.S @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ - .section .piggydata,#alloc + .section .piggydata, "a" .globl input_data input_data: .incbin "arch/arm/boot/compressed/piggy_data" diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts index 74c83b0ca54e0c1937fe446ae487c0b4a6661ead..bb7dc00a71e060ce5ed42ee71bc845846bc341b1 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts @@ -48,3 +48,16 @@ }; }; }; + +&gmac0 { + phy-mode = "rgmii"; + phy-handle = <&bcm54210e>; + + mdio { + /delete-node/ switch@1e; + + bcm54210e: ethernet-phy@0 { + reg = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts index 214df18f3a754c5c088126df547854d88c479952..6561e3b81b6060684663ddf37f19a1f12091af89 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts @@ -85,3 +85,16 @@ }; }; }; + +&gmac0 { + phy-mode = "rgmii"; + phy-handle = <&bcm54210e>; + + mdio { + /delete-node/ switch@1e; + + bcm54210e: ethernet-phy@0 { + reg = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 6edc4bd1e7eaf1587b2436eb79812dae5463c580..c331217ce21b32e106b30fdfcf6476a7c397eda0 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -260,7 +260,7 @@ interrupt-parent = <&gic>; - ehci: ehci@21000 { + ehci: usb@21000 { #usb-cells = <0>; compatible = "generic-ehci"; @@ -282,7 +282,7 @@ }; }; - ohci: ohci@22000 { + ohci: usb@22000 { #usb-cells = <0>; compatible = "generic-ohci"; @@ -468,7 +468,6 @@ "spi_lr_session_done", "spi_lr_overread"; clocks = <&iprocmed>; - clock-names = "iprocmed"; num-cs = <2>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index 453a2a37dabd3ccbe04d5668cc762aa52213f568..e44694800052d8123c1289017651b31d52373745 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -127,6 +127,9 @@ pcie0: pcie@2000 { reg = <0x00002000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; }; usb2: usb2@4000 { @@ -135,7 +138,7 @@ #address-cells = <1>; #size-cells = <1>; - ehci: ehci@4000 { + ehci: usb@4000 { compatible = "generic-ehci"; reg = <0x4000 0x1000>; interrupt-parent = <&gic>; @@ -155,9 +158,7 @@ }; }; - ohci: ohci@d000 { - #usb-cells = <0>; - + ohci: usb@d000 { compatible = "generic-ohci"; reg = <0xd000 0x1000>; interrupt-parent = <&gic>; @@ -180,6 +181,24 @@ gmac0: ethernet@5000 { reg = <0x5000 0x1000>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch: switch@1e { + compatible = "brcm,bcm53125"; + reg = <0x1e>; + + status = "disabled"; + + /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; gmac1: ethernet@b000 { diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts index ef263412fea513068a67a11ef80dff18d863802a..02c916bedd281d176e1f36d44c0c09ec89d3c640 100644 --- a/arch/arm/boot/dts/bcm947189acdbmr.dts +++ b/arch/arm/boot/dts/bcm947189acdbmr.dts @@ -61,9 +61,9 @@ spi { compatible = "spi-gpio"; num-chipselects = <1>; - gpio-sck = <&chipcommon 21 0>; - gpio-miso = <&chipcommon 22 0>; - gpio-mosi = <&chipcommon 23 0>; + sck-gpios = <&chipcommon 21 0>; + miso-gpios = <&chipcommon 22 0>; + mosi-gpios = <&chipcommon 23 0>; cs-gpios = <&chipcommon 24 0>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 29df4cfa9165f2b9f346b55310c0b1493b66942c..e398604b2ce0f6d4021cd16b87177aadc462a28f 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -237,7 +237,7 @@ i80-if-timings { cs-setup = <0>; wr-setup = <0>; - wr-act = <1>; + wr-active = <1>; wr-hold = <0>; }; }; diff --git a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi b/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi index 021d9fc1b49235c75342ba8d1d949f5f77fc4f25..27a1a895266559190e4708321d9c896cf89f9aee 100644 --- a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi +++ b/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi @@ -10,7 +10,7 @@ / { thermal-zones { cpu_thermal: cpu-thermal { - thermal-sensors = <&tmu 0>; + thermal-sensors = <&tmu>; polling-delay-passive = <0>; polling-delay = <0>; trips { diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 6085e92ac2d73925796e5d28e9a2b5832afd8729..3f7488833745dfaef0497f5186cffc6b0159e95f 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -611,7 +611,7 @@ status = "disabled"; hdmi_i2c_phy: hdmiphy@38 { - compatible = "exynos4210-hdmiphy"; + compatible = "samsung,exynos4210-hdmiphy"; reg = <0x38>; }; }; diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts index 0dedeba89b5f46d9c3637e90413441adc2139ae1..d2350561b05104452866208c5b1f569ec7046f1e 100644 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -184,7 +184,7 @@ compatible = "wlf,wm8960"; reg = <0x1a>; clocks = <&pmu_system_controller 0>; - clock-names = "MCLK1"; + clock-names = "mclk"; wlf,shared-lrclk; #sound-dai-cells = <0>; }; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 840a854ee8385f2791d6b277ab7c57f1b8537ffa..8a7c98f8d4eb6398d093a1449081750fbc11fd27 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -113,7 +113,6 @@ }; &cpu0_thermal { - thermal-sensors = <&tmu_cpu0 0>; polling-delay-passive = <0>; polling-delay = <0>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index aaff1588076136728926c96c6c07e749b6d7064c..99e2e0b0b9cd46082d1a80aaf09a2834dc0b1459 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -530,7 +530,7 @@ }; mipi_phy: mipi-video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; + compatible = "samsung,exynos5420-mipi-video-phy"; syscon = <&pmu_system_controller>; #phy-cells = <1>; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index d91cc532d0e2cefdd7d10939269d8c92397eff15..fcd7e4dc949a11170768d908ce339e1ac404f0b4 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -46,6 +46,10 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg; + usb1 = &usbh1; + usb2 = &usbh2; + usb3 = &usbh3; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index afde0ed6d71afb07f0cce1329e6eb69609fa8f0d..b00f791471c66fff933a9cb15400befc752c7857 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -32,6 +32,9 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index d7d092a5522a3f9dd859955f4950396ff0f00c3f..9f0c82d79a361ce212efc612b548802dcd0437f0 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -36,6 +36,8 @@ spi1 = &ecspi2; spi3 = &ecspi3; spi4 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; @@ -49,20 +51,18 @@ device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; - operating-points = < + operating-points = /* kHz uV */ - 996000 1275000 - 792000 1175000 - 396000 1075000 - 198000 975000 - >; - fsl,soc-operating-points = < + <996000 1275000>, + <792000 1175000>, + <396000 1075000>, + <198000 975000>; + fsl,soc-operating-points = /* ARM kHz SOC-PU uV */ - 996000 1175000 - 792000 1175000 - 396000 1175000 - 198000 1175000 - >; + <996000 1175000>, + <792000 1175000>, + <396000 1175000>, + <198000 1175000>; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX6SLL_CLK_ARM>, <&clks IMX6SLL_CLK_PLL2_PFD2>, @@ -271,7 +271,7 @@ status = "disabled"; }; - ssi1: ssi-controller@2028000 { + ssi1: ssi@2028000 { compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; interrupts = ; @@ -284,7 +284,7 @@ status = "disabled"; }; - ssi2: ssi-controller@202c000 { + ssi2: ssi@202c000 { compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; interrupts = ; @@ -297,7 +297,7 @@ status = "disabled"; }; - ssi3: ssi-controller@2030000 { + ssi3: ssi@2030000 { compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; interrupts = ; @@ -518,7 +518,7 @@ reg = <0x020ca000 0x1000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USBPHY2>; - phy-reg_3p0-supply = <®_3p0>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index b9ab1118be30b4257a96d63e337e2e663d3bb054..a0c0e631ebbe6d107b67fc6864533dec440fc01b 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -49,6 +49,9 @@ spi2 = &ecspi3; spi3 = &ecspi4; spi4 = &ecspi5; + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 334638ff507501c4f70a21ebc0662829c6575d63..dcb187995f7606f27139731d1a2a0617f3c3d46a 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -47,6 +47,8 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 7234e8330a576d8a53e7658d394e50211bbe2450..34904f7eeb133b46080c0d9da8981aa998f06c20 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -7,6 +7,12 @@ #include / { + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; + }; + cpus { cpu0: cpu@0 { clock-frequency = <996000000>; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 7eaf96b425bed4dc48fd647a598a0ce3923c9906..8a6d698e253d29e84781a6d2684bc3885862da30 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -46,6 +46,8 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbh; }; cpus { diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 67d77eee9433c655e0bd8f0c1dbf7c25aba3ecce..91c8a05ab67ae5a198d856fcdf140e3324fbf3a0 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -647,12 +647,12 @@ /* Configure pwm clock source for timers 8 & 9 */ &timer8 { assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin_ck>; + assigned-clock-parents = <&sys_32k_ck>; }; &timer9 { assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin_ck>; + assigned-clock-parents = <&sys_32k_ck>; }; /* @@ -669,6 +669,7 @@ &uart3 { interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core 0x17c>; + overrun-throttle-ms = <500>; }; &uart4 { diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 59527bb1225a9f755b6edd86a6f14e58bb521c56..cb90e7645d08c3b8b0f90b789ff111dc10f89cb1 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -387,8 +387,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>, - <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>; + ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, + <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; interrupts = ; interrupt-names = "msi"; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index c852b69229c977281a6f7e7192d88c3275e80817..26d49f35331b83f10efdf40aa667c291e6b940ac 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -82,14 +82,12 @@ }; }; - regulators { - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; }; soc: soc { diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 402b5e0fd616c2c04f946a6fc6cc9b7e742e34a5..4de88ded6d9a18e20c4898e76b1fbd8634a27fa9 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -924,7 +924,7 @@ status = "disabled"; }; - spdif: sound@ff88b0000 { + spdif: sound@ff8b0000 { compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; reg = <0x0 0xff8b0000 0x0 0x10000>; #sound-dai-cells = <0>; diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index 1aeac33b0d341bea18c0dddf46d6feca5f1c8b5d..0b07b3c319604188c1c768d7a41c5b56c2b24773 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -28,29 +28,21 @@ bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; + fin_pll: oscillator-0 { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; + xusbxti: oscillator-1 { + compatible = "fixed-clock"; + clock-output-names = "xusbxti"; + clock-frequency = <48000000>; + #clock-cells = <0>; }; - srom-cs1@18000000 { + srom-cs1-bus@18000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -59,7 +51,7 @@ ethernet@18000000 { compatible = "davicom,dm9000"; - reg = <0x18000000 0x2 0x18000004 0x2>; + reg = <0x18000000 0x2>, <0x18000004 0x2>; interrupt-parent = <&gpn>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; davicom,no-eeprom; @@ -201,12 +193,12 @@ }; &pinctrl0 { - gpio_leds: gpio-leds { + gpio_leds: gpio-leds-pins { samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; samsung,pin-pud = ; }; - gpio_keys: gpio-keys { + gpio_keys: gpio-keys-pins { samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", "gpn-4", "gpn-5", "gpl-11", "gpl-12"; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi index 8e9594d64b579d7b018835e029fe36217aa958ef..0a3186d57cb564d76e35b2e3b1036cfc752c64f4 100644 --- a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi @@ -16,111 +16,111 @@ * Pin banks */ - gpa: gpa { + gpa: gpa-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpc: gpc { + gpc: gpc-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpd: gpd { + gpd: gpd-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpe: gpe { + gpe: gpe-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpf: gpf { + gpf: gpf-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpg: gpg { + gpg: gpg-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gph: gph { + gph: gph-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpi: gpi { + gpi: gpi-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpj: gpj { + gpj: gpj-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpk: gpk { + gpk: gpk-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpl: gpl { + gpl: gpl-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpm: gpm { + gpm: gpm-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpn: gpn { + gpn: gpn-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpo: gpo { + gpo: gpo-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpp: gpp { + gpp: gpp-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpq: gpq { + gpq: gpq-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -131,225 +131,225 @@ * Pin groups */ - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa-0", "gpa-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa-2", "gpa-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa-4", "gpa-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa-6", "gpa-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - ext_dma_0: ext-dma-0 { + ext_dma_0: ext-dma-0-pins { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - ext_dma_1: ext-dma-1 { + ext_dma_1: ext-dma-1-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - irda_data_0: irda-data-0 { + irda_data_0: irda-data-0-pins { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - irda_data_1: irda-data-1 { + irda_data_1: irda-data-1-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - irda_sdbw: irda-sdbw { + irda_sdbw: irda-sdbw-pins { samsung,pins = "gpb-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpb-5", "gpb-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { /* S3C6410-only */ samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpc-0", "gpc-1", "gpc-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - spi0_cs: spi0-cs { + spi0_cs: spi0-cs-pins { samsung,pins = "gpc-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpc-4", "gpc-5", "gpc-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - spi1_cs: spi1-cs { + spi1_cs: spi1-cs-pins { samsung,pins = "gpc-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpg-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpg-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_bus1: sd0-bus1 { + sd0_bus1: sd0-bus1-pins { samsung,pins = "gpg-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_bus4: sd0-bus4 { + sd0_bus4: sd0-bus4-pins { samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpg-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gph-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gph-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_bus1: sd1-bus1 { + sd1_bus1: sd1-bus1-pins { samsung,pins = "gph-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_bus4: sd1-bus4 { + sd1_bus4: sd1-bus4-pins { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_bus8: sd1-bus8 { + sd1_bus8: sd1-bus8-pins { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", "gph-6", "gph-7", "gph-8", "gph-9"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpg-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpc-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpc-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_bus1: sd2-bus1 { + sd2_bus1: sd2-bus1-pins { samsung,pins = "gph-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_bus4: sd2-bus4 { + sd2_bus4: sd2-bus4-pins { samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s0_cdclk: i2s0-cdclk { + i2s0_cdclk: i2s0-cdclk-pins { samsung,pins = "gpd-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s1_cdclk: i2s1-cdclk { + i2s1_cdclk: i2s1-cdclk-pins { samsung,pins = "gpe-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { /* S3C6410-only */ samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", "gph-8", "gph-9"; @@ -357,50 +357,50 @@ samsung,pin-pud = ; }; - i2s2_cdclk: i2s2-cdclk { + i2s2_cdclk: i2s2-cdclk-pins { /* S3C6410-only */ samsung,pins = "gph-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - pcm0_bus: pcm0-bus { + pcm0_bus: pcm0-bus-pins { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - pcm0_extclk: pcm0-extclk { + pcm0_extclk: pcm0-extclk-pins { samsung,pins = "gpd-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - pcm1_extclk: pcm1-extclk { + pcm1_extclk: pcm1-extclk-pins { samsung,pins = "gpe-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - ac97_bus_0: ac97-bus-0 { + ac97_bus_0: ac97-bus-0-pins { samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - ac97_bus_1: ac97-bus-1 { + ac97_bus_1: ac97-bus-1-pins { samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - cam_port: cam-port { + cam_port: cam-port-pins { samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", "gpf-5", "gpf-6", "gpf-7", "gpf-8", "gpf-9", "gpf-10", "gpf-11", "gpf-12"; @@ -408,242 +408,242 @@ samsung,pin-pud = ; }; - cam_rst: cam-rst { + cam_rst: cam-rst-pins { samsung,pins = "gpf-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - cam_field: cam-field { + cam_field: cam-field-pins { /* S3C6410-only */ samsung,pins = "gpb-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - pwm_extclk: pwm-extclk { + pwm_extclk: pwm-extclk-pins { samsung,pins = "gpf-13"; samsung,pin-function = ; samsung,pin-pud = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpf-14"; samsung,pin-function = ; samsung,pin-pud = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpf-15"; samsung,pin-function = ; samsung,pin-pud = ; }; - clkout0: clkout-0 { + clkout0: clkout-0-pins { samsung,pins = "gpf-14"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col0_0: keypad-col0-0 { + keypad_col0_0: keypad-col0-0-pins { samsung,pins = "gph-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col1_0: keypad-col1-0 { + keypad_col1_0: keypad-col1-0-pins { samsung,pins = "gph-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col2_0: keypad-col2-0 { + keypad_col2_0: keypad-col2-0-pins { samsung,pins = "gph-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col3_0: keypad-col3-0 { + keypad_col3_0: keypad-col3-0-pins { samsung,pins = "gph-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col4_0: keypad-col4-0 { + keypad_col4_0: keypad-col4-0-pins { samsung,pins = "gph-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col5_0: keypad-col5-0 { + keypad_col5_0: keypad-col5-0-pins { samsung,pins = "gph-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col6_0: keypad-col6-0 { + keypad_col6_0: keypad-col6-0-pins { samsung,pins = "gph-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col7_0: keypad-col7-0 { + keypad_col7_0: keypad-col7-0-pins { samsung,pins = "gph-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col0_1: keypad-col0-1 { + keypad_col0_1: keypad-col0-1-pins { samsung,pins = "gpl-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col1_1: keypad-col1-1 { + keypad_col1_1: keypad-col1-1-pins { samsung,pins = "gpl-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col2_1: keypad-col2-1 { + keypad_col2_1: keypad-col2-1-pins { samsung,pins = "gpl-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col3_1: keypad-col3-1 { + keypad_col3_1: keypad-col3-1-pins { samsung,pins = "gpl-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col4_1: keypad-col4-1 { + keypad_col4_1: keypad-col4-1-pins { samsung,pins = "gpl-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col5_1: keypad-col5-1 { + keypad_col5_1: keypad-col5-1-pins { samsung,pins = "gpl-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col6_1: keypad-col6-1 { + keypad_col6_1: keypad-col6-1-pins { samsung,pins = "gpl-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col7_1: keypad-col7-1 { + keypad_col7_1: keypad-col7-1-pins { samsung,pins = "gpl-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row0_0: keypad-row0-0 { + keypad_row0_0: keypad-row0-0-pins { samsung,pins = "gpk-8"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row1_0: keypad-row1-0 { + keypad_row1_0: keypad-row1-0-pins { samsung,pins = "gpk-9"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row2_0: keypad-row2-0 { + keypad_row2_0: keypad-row2-0-pins { samsung,pins = "gpk-10"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row3_0: keypad-row3-0 { + keypad_row3_0: keypad-row3-0-pins { samsung,pins = "gpk-11"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row4_0: keypad-row4-0 { + keypad_row4_0: keypad-row4-0-pins { samsung,pins = "gpk-12"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row5_0: keypad-row5-0 { + keypad_row5_0: keypad-row5-0-pins { samsung,pins = "gpk-13"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row6_0: keypad-row6-0 { + keypad_row6_0: keypad-row6-0-pins { samsung,pins = "gpk-14"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row7_0: keypad-row7-0 { + keypad_row7_0: keypad-row7-0-pins { samsung,pins = "gpk-15"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row0_1: keypad-row0-1 { + keypad_row0_1: keypad-row0-1-pins { samsung,pins = "gpn-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row1_1: keypad-row1-1 { + keypad_row1_1: keypad-row1-1-pins { samsung,pins = "gpn-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row2_1: keypad-row2-1 { + keypad_row2_1: keypad-row2-1-pins { samsung,pins = "gpn-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row3_1: keypad-row3-1 { + keypad_row3_1: keypad-row3-1-pins { samsung,pins = "gpn-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row4_1: keypad-row4-1 { + keypad_row4_1: keypad-row4-1-pins { samsung,pins = "gpn-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row5_1: keypad-row5-1 { + keypad_row5_1: keypad-row5-1-pins { samsung,pins = "gpn-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row6_1: keypad-row6-1 { + keypad_row6_1: keypad-row6-1-pins { samsung,pins = "gpn-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row7_1: keypad-row7-1 { + keypad_row7_1: keypad-row7-1-pins { samsung,pins = "gpn-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - lcd_ctrl: lcd-ctrl { + lcd_ctrl: lcd-ctrl-pins { samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; samsung,pin-function = ; samsung,pin-pud = ; }; - lcd_data16: lcd-data-width16 { + lcd_data16: lcd-data-width16-pins { samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6", "gpi-7", "gpi-10", "gpi-11", "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-3", @@ -652,7 +652,7 @@ samsung,pin-pud = ; }; - lcd_data18: lcd-data-width18 { + lcd_data18: lcd-data-width18-pins { samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5", "gpi-6", "gpi-7", "gpi-10", "gpi-11", "gpi-12", "gpi-13", "gpi-14", "gpi-15", @@ -662,7 +662,7 @@ samsung,pin-pud = ; }; - lcd_data24: lcd-data-width24 { + lcd_data24: lcd-data-width24-pins { samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", "gpi-4", "gpi-5", "gpi-6", "gpi-7", "gpi-8", "gpi-9", "gpi-10", "gpi-11", @@ -673,7 +673,7 @@ samsung,pin-pud = ; }; - hsi_bus: hsi-bus { + hsi_bus: hsi-bus-pins { samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", "gpk-4", "gpk-5", "gpk-6", "gpk-7"; samsung,pin-function = ; diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 84b38f18519917b916248e1695803225910e0fc2..53a841ecf7a448eb526e04089ef69f6e59891b33 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -15,6 +15,7 @@ */ /dts-v1/; +#include #include #include "s5pv210.dtsi" @@ -31,11 +32,18 @@ reg = <0x20000000 0x40000000>; }; - ethernet@18000000 { + pmic_ap_clk: clock-0 { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + ethernet@a8000000 { compatible = "davicom,dm9000"; - reg = <0xA8000000 0x2 0xA8000002 0x2>; + reg = <0xa8000000 0x2>, <0xa8000002 0x2>; interrupt-parent = <&gph1>; - interrupts = <1 4>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; local-mac-address = [00 00 de ad be ef]; davicom,no-eeprom; }; @@ -47,6 +55,14 @@ default-brightness-level = <6>; pinctrl-names = "default"; pinctrl-0 = <&pwm3_out>; + power-supply = <&dc5v_reg>; + }; + + dc5v_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "DC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; }; }; @@ -147,6 +163,8 @@ &rtc { status = "okay"; + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; }; &sdhci0 { diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 020a864623ff4e611531d94de5696af71432e9c0..781ddfdc5f873b6c3c044647281a39b8a04d238e 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -560,7 +560,7 @@ interrupts = <29>; clocks = <&clocks CLK_CSIS>, <&clocks SCLK_CSIS>; - clock-names = "clk_csis", + clock-names = "csis", "sclk_csis"; bus-width = <4>; status = "disabled"; diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/spear320-hmi.dts index 0d0da1f65f0e68a23d038a11a91054f8f25022e0..1e54748799a6ba576056736dbcdd28ac03f29436 100644 --- a/arch/arm/boot/dts/spear320-hmi.dts +++ b/arch/arm/boot/dts/spear320-hmi.dts @@ -248,7 +248,7 @@ irq-trigger = <0x1>; stmpegpio: stmpe-gpio { - compatible = "stmpe,gpio"; + compatible = "st,stmpe-gpio"; reg = <0>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi index 9314128df185919a737b7b74eb45322bd97284c1..639a6b65749f23415a79526baaeb90934a12a713 100644 --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi @@ -284,6 +284,88 @@ slew-rate = <2>; }; }; + + can1_pins_a: can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can1_pins_b: can1-1 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can1_pins_c: can1-2 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + + }; + }; + + can1_pins_d: can1-3 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + + }; + }; + + can2_pins_a: can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can2_pins_b: can2-1 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can3_pins_a: can3-0 { + pins1 { + pinmux = ; /* CAN3_TX */ + }; + pins2 { + pinmux = ; /* CAN3_RX */ + bias-pull-up; + }; + }; + + can3_pins_b: can3-1 { + pins1 { + pinmux = ; /* CAN3_TX */ + }; + pins2 { + pinmux = ; /* CAN3_RX */ + bias-pull-up; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts index e5b4a7570a010e0562eac1b3a6e05627c2c7b0e3..13a75a87d571beb13576051f31d232ab370b5d2a 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts @@ -118,6 +118,7 @@ reg = <0x2c0f0000 0x1000>; interrupts = <0 84 4>; cache-level = <2>; + cache-unified; }; pmu { diff --git a/arch/arm/include/asm/bugs.h b/arch/arm/include/asm/bugs.h index 73a99c72a930a98498a94423fe484c28aab0f583..21b6f742b3baabcbe32b27c83ede6284dddeb68e 100644 --- a/arch/arm/include/asm/bugs.h +++ b/arch/arm/include/asm/bugs.h @@ -1,6 +1,4 @@ /* - * arch/arm/include/asm/bugs.h - * * Copyright (C) 1995-2003 Russell King * * This program is free software; you can redistribute it and/or modify @@ -13,10 +11,8 @@ extern void check_writebuffer_bugs(void); #ifdef CONFIG_MMU -extern void check_bugs(void); extern void check_other_bugs(void); #else -#define check_bugs() do { } while (0) #define check_other_bugs() do { } while (0) #endif diff --git a/arch/arm/include/asm/exception.h b/arch/arm/include/asm/exception.h index 58e039a851af03400dcbf23efe49cc2f0deb67ef..3c82975d46db3531cf68704aa9a61cdcc5126b90 100644 --- a/arch/arm/include/asm/exception.h +++ b/arch/arm/include/asm/exception.h @@ -10,10 +10,6 @@ #include -#ifdef CONFIG_FUNCTION_GRAPH_TRACER #define __exception_irq_entry __irq_entry -#else -#define __exception_irq_entry -#endif #endif /* __ASM_ARM_EXCEPTION_H */ diff --git a/arch/arm/kernel/bugs.c b/arch/arm/kernel/bugs.c index d41d3598e5e541115c08f9b81b26fd187a7fe7af..e9fc25350784e2d3bb1696a72c769d81aecfd7c3 100644 --- a/arch/arm/kernel/bugs.c +++ b/arch/arm/kernel/bugs.c @@ -1,5 +1,6 @@ // SPDX-Identifier: GPL-2.0 #include +#include #include #include @@ -11,7 +12,7 @@ void check_other_bugs(void) #endif } -void __init check_bugs(void) +void __init arch_cpu_finalize_init(void) { check_writebuffer_bugs(); check_other_bugs(); diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 2ee5b7f5e7ad01a9fdf75e562f7fd22f6847d12a..c71ecd06131cadf9158e5efc589b849acd5bc3da 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -631,7 +631,7 @@ int hw_breakpoint_arch_parse(struct perf_event *bp, hw->address &= ~alignment_mask; hw->ctrl.len <<= offset; - if (is_default_overflow_handler(bp)) { + if (uses_default_overflow_handler(bp)) { /* * Mismatch breakpoints are required for single-stepping * breakpoints. @@ -803,7 +803,7 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr, * Otherwise, insert a temporary mismatch breakpoint so that * we can single-step over the watchpoint trigger. */ - if (!is_default_overflow_handler(wp)) + if (!uses_default_overflow_handler(wp)) continue; step: enable_single_step(wp, instruction_pointer(regs)); @@ -816,7 +816,7 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr, info->trigger = addr; pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); perf_bp_event(wp, regs); - if (is_default_overflow_handler(wp)) + if (uses_default_overflow_handler(wp)) enable_single_step(wp, instruction_pointer(regs)); } @@ -891,7 +891,7 @@ static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) info->trigger = addr; pr_debug("breakpoint fired: address = 0x%x\n", addr); perf_bp_event(bp, regs); - if (is_default_overflow_handler(bp)) + if (uses_default_overflow_handler(bp)) enable_single_step(bp, addr); goto unlock; } diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c index 314cfb232a6353165dc899f35e5747a27a7ef617..f2bb090373c674fec71d70f7f23bd764aa599ca3 100644 --- a/arch/arm/kernel/unwind.c +++ b/arch/arm/kernel/unwind.c @@ -313,6 +313,29 @@ static int unwind_exec_pop_subset_r0_to_r3(struct unwind_ctrl_block *ctrl, return URC_OK; } +static unsigned long unwind_decode_uleb128(struct unwind_ctrl_block *ctrl) +{ + unsigned long bytes = 0; + unsigned long insn; + unsigned long result = 0; + + /* + * unwind_get_byte() will advance `ctrl` one instruction at a time, so + * loop until we get an instruction byte where bit 7 is not set. + * + * Note: This decodes a maximum of 4 bytes to output 28 bits data where + * max is 0xfffffff: that will cover a vsp increment of 1073742336, hence + * it is sufficient for unwinding the stack. + */ + do { + insn = unwind_get_byte(ctrl); + result |= (insn & 0x7f) << (bytes * 7); + bytes++; + } while (!!(insn & 0x80) && (bytes != sizeof(result))); + + return result; +} + /* * Execute the current unwind instruction. */ @@ -366,7 +389,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) if (ret) goto error; } else if (insn == 0xb2) { - unsigned long uleb128 = unwind_get_byte(ctrl); + unsigned long uleb128 = unwind_decode_uleb128(ctrl); ctrl->vrs[SP] += 0x204 + (uleb128 << 2); } else { diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index ed6d35d9cdb5a6288f70d116e6914f803455006e..a68688f3f3b3d84449b663323709444bbca0764d 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -19,6 +19,7 @@ ENTRY(mmioset) ENTRY(memset) UNWIND( .fnstart ) + and r1, r1, #255 @ cast to unsigned char ands r3, r0, #3 @ 1 unaligned? mov ip, r0 @ preserve r0 as return value bne 6f @ 1 diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c index 14be73ca107a5e3010d5f5ce8a23a17cfcb61b55..965a41572283e275b0247b519281823e1d81b753 100644 --- a/arch/arm/mach-imx/mmdc.c +++ b/arch/arm/mach-imx/mmdc.c @@ -105,6 +105,7 @@ struct mmdc_pmu { cpumask_t cpu; struct hrtimer hrtimer; unsigned int active_events; + int id; struct device *dev; struct perf_event *mmdc_events[MMDC_NUM_COUNTERS]; struct hlist_node node; @@ -445,8 +446,6 @@ static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer) static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc, void __iomem *mmdc_base, struct device *dev) { - int mmdc_num; - *pmu_mmdc = (struct mmdc_pmu) { .pmu = (struct pmu) { .task_ctx_nr = perf_invalid_context, @@ -463,15 +462,16 @@ static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc, .active_events = 0, }; - mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL); + pmu_mmdc->id = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL); - return mmdc_num; + return pmu_mmdc->id; } static int imx_mmdc_remove(struct platform_device *pdev) { struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev); + ida_simple_remove(&mmdc_ida, pmu_mmdc->id); cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); perf_pmu_unregister(&pmu_mmdc->pmu); iounmap(pmu_mmdc->mmdc_base); @@ -485,7 +485,6 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b { struct mmdc_pmu *pmu_mmdc; char *name; - int mmdc_num; int ret; const struct of_device_id *of_id = of_match_device(imx_mmdc_dt_ids, &pdev->dev); @@ -508,14 +507,14 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b cpuhp_mmdc_state = ret; } - mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev); - pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk; - if (mmdc_num == 0) - name = "mmdc"; - else - name = devm_kasprintf(&pdev->dev, - GFP_KERNEL, "mmdc%d", mmdc_num); + ret = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev); + if (ret < 0) + goto pmu_free; + name = devm_kasprintf(&pdev->dev, + GFP_KERNEL, "mmdc%d", ret); + + pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk; pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data; hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC, @@ -536,6 +535,7 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b pmu_register_err: pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret); + ida_simple_remove(&mmdc_ida, pmu_mmdc->id); cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); hrtimer_cancel(&pmu_mmdc->hrtimer); pmu_free: diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index 4447210c9b0d841a0dc79c4afdb9909eeff7b245..291bc376d30e83148fa1ef81c99416d61453665e 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -165,7 +165,7 @@ static int __init omap1_dm_timer_init(void) kfree(pdata); err_free_pdev: - platform_device_unregister(pdev); + platform_device_put(pdev); return ret; } diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 1a0f69c0a37638ce10985aea2f027a11bb371ba8..27c652eaa17550c02ccdc43acc9d2fc381114104 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -177,7 +177,7 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) break; case PWRDM_STATE_PREV: prev = pwrdm_read_prev_pwrst(pwrdm); - if (pwrdm->state != prev) + if (prev >= 0 && pwrdm->state != prev) pwrdm->state_counter[prev]++; if (prev == PWRDM_POWER_RET) _update_logic_membank_counters(pwrdm); diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index f24858d5ac693065f55afd8d73cbde7ef9bd0a17..754fd99bb43c15169e626b1ff901f6ad439f8e75 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -650,6 +650,7 @@ static void __init realtime_counter_init(void) } rate = clk_get_rate(sys_clk); + clk_put(sys_clk); if (soc_is_dra7xx()) { /* diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index 3d36f1d951964667b111ebe5f75bcad5465d775e..3f651df3a71cf6860f8b214e686b2cc86bcdd71d 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -63,6 +63,9 @@ static void __init orion5x_dt_init(void) if (of_machine_is_compatible("maxtor,shared-storage-2")) mss2_init(); + if (of_machine_is_compatible("lacie,d2-network")) + d2net_init(); + of_platform_default_populate(NULL, orion5x_auxdata_lookup, NULL); } diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index eb96009e21c4ce3fcf07d93b61b7fe354882444f..b9cfdb4564568b717aeedb5778c400ea870b548c 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -75,6 +75,12 @@ extern void mss2_init(void); static inline void mss2_init(void) {} #endif +#ifdef CONFIG_MACH_D2NET_DT +void d2net_init(void); +#else +static inline void d2net_init(void) {} +#endif + /***************************************************************************** * Helpers to access Orion registers ****************************************************************************/ diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index ef9fd9b759cbd0172229cf550301623574a18d4f..34dc870857245c2a6997e87ccf48489a6600a872 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -224,8 +224,6 @@ void sharpsl_battery_kick(void) { schedule_delayed_work(&sharpsl_bat, msecs_to_jiffies(125)); } -EXPORT_SYMBOL(sharpsl_battery_kick); - static void sharpsl_battery_thread(struct work_struct *private_) { diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 5d50025492b7f2a435f1fc3cc60e88a4e015f49f..af35a0ba2dca3e2a6f56ba9eadafb85839d971f6 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -13,7 +13,6 @@ */ #include -#include /* symbol_get ; symbol_put */ #include #include #include @@ -517,17 +516,6 @@ static struct pxa2xx_spi_chip spitz_ads7846_chip = { .gpio_cs = SPITZ_GPIO_ADS7846_CS, }; -static void spitz_bl_kick_battery(void) -{ - void (*kick_batt)(void); - - kick_batt = symbol_get(sharpsl_battery_kick); - if (kick_batt) { - kick_batt(); - symbol_put(sharpsl_battery_kick); - } -} - static struct corgi_lcd_platform_data spitz_lcdcon_info = { .init_mode = CORGI_LCD_MODE_VGA, .max_intensity = 0x2f, @@ -535,7 +523,7 @@ static struct corgi_lcd_platform_data spitz_lcdcon_info = { .limit_mask = 0x0b, .gpio_backlight_cont = SPITZ_GPIO_BACKLIGHT_CONT, .gpio_backlight_on = SPITZ_GPIO_BACKLIGHT_ON, - .kick_battery = spitz_bl_kick_battery, + .kick_battery = sharpsl_battery_kick, }; static struct pxa2xx_spi_chip spitz_lcdcon_chip = { diff --git a/arch/arm/mach-qcom/board-qm215.c b/arch/arm/mach-qcom/board-qm215.c index 3cdeab98a7fc569854cd58875d186a3b079f846a..884aa7101ddbc254fbf4c78cea4a9a608557b8ba 100644 --- a/arch/arm/mach-qcom/board-qm215.c +++ b/arch/arm/mach-qcom/board-qm215.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -10,6 +11,7 @@ static const char *qm215_dt_match[] __initconst = { "qcom,qm215", + "qcom,qcm2150", NULL }; diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index 575ec085cffaf78cac62c3f38f21f147037c0e46..73bedccedb5818aec42fd2be889b85ece40dfbdb 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -570,7 +570,7 @@ static void __init map_sa1100_gpio_regs( void ) */ static void __init get_assabet_scr(void) { - unsigned long uninitialized_var(scr), i; + unsigned long scr, i; GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */ GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */ diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index f0292a30e6f696058114ac64d54c5f8720447b70..6b75ef7be3fda856cfc92eb672b845cea3669391 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -222,6 +222,7 @@ int __init zynq_early_slcr_init(void) zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); if (IS_ERR(zynq_slcr_regmap)) { pr_err("%s: failed to find zynq-slcr\n", __func__); + of_node_put(np); return -ENODEV; } diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 774ef1323554bd54ad74a5caa14155921906560d..4773490177c96e69a93db2bbd20b9bfcace0f6ee 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -505,7 +505,7 @@ cpu_arm1020_name: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm1020_proc_info,#object __arm1020_proc_info: diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index ae3c27b71594d7d57cb40965efe9aecb07c82b9f..928e8ca58f4091b6f5bfa8a946ccf97a6c7d1d9c 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -463,7 +463,7 @@ arm1020e_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm1020e_proc_info,#object __arm1020e_proc_info: diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index dbb2413fe04dbd5babcd7dad8f41820448d518dc..385584c3d22252a7aba35c92286285f8ae0c3cfa 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -448,7 +448,7 @@ arm1022_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm1022_proc_info,#object __arm1022_proc_info: diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 0b37b2cef9d32849b0162787ef06c7215814acb2..29cc81857373498947ff85ad9a64fc6e5de9d108 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -442,7 +442,7 @@ arm1026_crval: string cpu_arm1026_name, "ARM1026EJ-S" .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm1026_proc_info,#object __arm1026_proc_info: diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index 3651cd70e4181c6584259b3b19a50729d38dea19..c08cd1b0a1d0e131b0ef19fc8f1ceb269b0898bf 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S @@ -186,7 +186,7 @@ arm720_crval: * See for a definition of this structure. */ - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req .type __\name\()_proc_info,#object diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S index 024fb7732407d6c25701e4698843e8b27fb66da1..6eed87103b95b4256fc3a38ee65f0146f16cfb0f 100644 --- a/arch/arm/mm/proc-arm740.S +++ b/arch/arm/mm/proc-arm740.S @@ -132,7 +132,7 @@ __arm740_setup: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm740_proc_info,#object __arm740_proc_info: .long 0x41807400 diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S index 25472d94426d2c8a5f6d56456632b4f2406b9eab..beb64a7ccb38d72675680366577e2d80f5d2d698 100644 --- a/arch/arm/mm/proc-arm7tdmi.S +++ b/arch/arm/mm/proc-arm7tdmi.S @@ -76,7 +76,7 @@ __arm7tdmi_setup: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro arm7tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \ extra_hwcaps=0 diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 7a14bd4414c9ca5fdce13b3eedc458ef1fa6f377..5d43197083622be2468d7beb9e892411a15ed3b0 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -448,7 +448,7 @@ arm920_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm920_proc_info,#object __arm920_proc_info: diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index edccfcdcd551fe9e9970172d0467d5ddd3324bba..7e22ca780b3694f52f175d96b7ff956d1b4d81a3 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -426,7 +426,7 @@ arm922_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm922_proc_info,#object __arm922_proc_info: diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 32a47cc19076c1eaef60ff4a523c89da81094455..d343e77b845674666fa51f067545391797167cc6 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -491,7 +491,7 @@ arm925_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache .type __\name\()_proc_info,#object diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index fb827c633693c430b718dcb457f6850d8126d3e6..8cf78c608c4227af629d48a576e6f1a3709bf5a3 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -474,7 +474,7 @@ arm926_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm926_proc_info,#object __arm926_proc_info: diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index ee5b66f847c44939f0a68374ba5d58ecf89591b2..631ae64eeccd86c75b111d69548c6fa4ca0d4493 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S @@ -344,7 +344,7 @@ __arm940_setup: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm940_proc_info,#object __arm940_proc_info: diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index 7361837edc312810a5fb9e5c9d3390ae094f4131..033ad7402d67c4b16d6af6c89d98f08bd9a44145 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S @@ -399,7 +399,7 @@ __arm946_setup: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm946_proc_info,#object __arm946_proc_info: .long 0x41009460 diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S index 7fac8c6121349e03e96bd00694e379c499326e5b..2195468ccd76dc6ad359af50673252d006f60744 100644 --- a/arch/arm/mm/proc-arm9tdmi.S +++ b/arch/arm/mm/proc-arm9tdmi.S @@ -70,7 +70,7 @@ __arm9tdmi_setup: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro arm9tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req .type __\name\()_proc_info, #object diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S index 4001b73af4ee15cc722bf929573196cd4aeb4033..fd3e5dd94e59e9cbf8164fcf3bed61db7d4883fd 100644 --- a/arch/arm/mm/proc-fa526.S +++ b/arch/arm/mm/proc-fa526.S @@ -190,7 +190,7 @@ fa526_cr1_set: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __fa526_proc_info,#object __fa526_proc_info: diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 92e08bf37aad940b8f7da40644ef88bcbf56aa31..685d324a74d389eddcb0d6a73ebb1cd4deea3c10 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -584,7 +584,7 @@ feroceon_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro feroceon_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache:req .type __\name\()_proc_info,#object diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index 6f07d2ef4ff262c64bb814824e48725353a6ca30..9182321a586afb8d1a4e9488657d69b760872936 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -429,7 +429,7 @@ mohawk_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __88sv331x_proc_info,#object __88sv331x_proc_info: diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index ee2ce496239f57f14f3638e133a8fbd14e7d2bfa..093ad2ceff284439ae680e1ec896aa82a31432e0 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S @@ -199,7 +199,7 @@ sa110_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __sa110_proc_info,#object __sa110_proc_info: diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 222d5836f6664467fb5a5c6d18bc6240ba700593..12b8fcab4b59eb8295f1169616e08150ccd1689c 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -242,7 +242,7 @@ sa1100_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req .type __\name\()_proc_info,#object diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 06d890a2342b1600e2eae6e350994ad59f5c3a08..32f4df0915ef118ed2fb92ef8513935479d73a9a 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -264,7 +264,7 @@ v6_crval: string cpu_elf_name, "v6" .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" /* * Match any ARMv6 processor core. diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 587e2eb61a36ac1b70431bd32ca6ae111bf948ed..f318370b71afac51242ad5f0a83821710b719426 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -638,7 +638,7 @@ __v7_setup_stack: string cpu_elf_name, "v7" .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" /* * Standard v7 proc info content diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S index 9c2978c128d97cf24ba3f5aff70dc14179ae17b3..0be14b64879c8ed81b4fb604e90beaef1352f0ce 100644 --- a/arch/arm/mm/proc-v7m.S +++ b/arch/arm/mm/proc-v7m.S @@ -96,7 +96,7 @@ ENTRY(cpu_cm7_proc_fin) ret lr ENDPROC(cpu_cm7_proc_fin) - .section ".init.text", #alloc, #execinstr + .section ".init.text", "ax" __v7m_cm7_setup: mov r8, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC| V7M_SCB_CCR_BP) @@ -180,7 +180,7 @@ ENDPROC(__v7m_setup) string cpu_elf_name "v7m" string cpu_v7m_name "ARMv7-M" - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0, proc_fns = v7m_processor_functions .long 0 /* proc_info_list.__cpu_mm_mmu_flags */ diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 293dcc2c441f305f7b28d67dbf27a2276fdf2c25..da96e4de13537403ab006a0afd22cbfc224bce3b 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -499,7 +499,7 @@ xsc3_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro xsc3_proc_info name:req, cpu_val:req, cpu_mask:req .type __\name\()_proc_info,#object diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 3d75b7972fd13500baee28f30c48817428f286e9..c7800c69921b224564d8c5c38f4cec1d364e54ac 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -613,7 +613,7 @@ xscale_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro xscale_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache .type __\name\()_proc_info,#object diff --git a/arch/arm/probes/kprobes/checkers-common.c b/arch/arm/probes/kprobes/checkers-common.c index 971119c2947413696d9295f1446a57ce040e97cd..aa10e5e46ebb259155e07755c6545d858cd93993 100644 --- a/arch/arm/probes/kprobes/checkers-common.c +++ b/arch/arm/probes/kprobes/checkers-common.c @@ -48,7 +48,7 @@ enum probes_insn checker_stack_use_imm_0xx(probes_opcode_t insn, * Different from other insn uses imm8, the real addressing offset of * STRD in T32 encoding should be imm8 * 4. See ARMARM description. */ -enum probes_insn checker_stack_use_t32strd(probes_opcode_t insn, +static enum probes_insn checker_stack_use_t32strd(probes_opcode_t insn, struct arch_probes_insn *asi, const struct decode_header *h) { diff --git a/arch/arm/probes/kprobes/core.c b/arch/arm/probes/kprobes/core.c index 62da8e2211e4b04b0abda127ad0a69b5d69047a1..0a7090a65bcade879095963e7da83a7c0bb9450c 100644 --- a/arch/arm/probes/kprobes/core.c +++ b/arch/arm/probes/kprobes/core.c @@ -239,7 +239,7 @@ singlestep(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb) * kprobe, and that level is reserved for user kprobe handlers, so we can't * risk encountering a new kprobe in an interrupt handler. */ -void __kprobes kprobe_handler(struct pt_regs *regs) +static void __kprobes kprobe_handler(struct pt_regs *regs) { struct kprobe *p, *cur; struct kprobe_ctlblk *kcb; diff --git a/arch/arm/probes/kprobes/opt-arm.c b/arch/arm/probes/kprobes/opt-arm.c index cf08cb72676707e9aee81d5e915707836b651796..1516c340a0766979ed7dfc100bf0f4d409caa8d9 100644 --- a/arch/arm/probes/kprobes/opt-arm.c +++ b/arch/arm/probes/kprobes/opt-arm.c @@ -158,8 +158,6 @@ __arch_remove_optimized_kprobe(struct optimized_kprobe *op, int dirty) } } -extern void kprobe_handler(struct pt_regs *regs); - static void optimized_callback(struct optimized_kprobe *op, struct pt_regs *regs) { diff --git a/arch/arm/probes/kprobes/test-core.c b/arch/arm/probes/kprobes/test-core.c index cc237fa9b90fbd176faf9d6f04a5a74b42a9a234..1c86c5d980c5b22a0cd275429f3fc7b964cfc50d 100644 --- a/arch/arm/probes/kprobes/test-core.c +++ b/arch/arm/probes/kprobes/test-core.c @@ -723,7 +723,7 @@ static const char coverage_register_lookup[16] = { [REG_TYPE_NOSPPCX] = COVERAGE_ANY_REG | COVERAGE_SP, }; -unsigned coverage_start_registers(const struct decode_header *h) +static unsigned coverage_start_registers(const struct decode_header *h) { unsigned regs = 0; int i; diff --git a/arch/arm/probes/kprobes/test-core.h b/arch/arm/probes/kprobes/test-core.h index 94285203e9f74421153defc83a92ba65eedab9ea..459ebda077139d4a002c96e8b5093947f50a8065 100644 --- a/arch/arm/probes/kprobes/test-core.h +++ b/arch/arm/probes/kprobes/test-core.h @@ -456,3 +456,7 @@ void kprobe_thumb32_test_cases(void); #else void kprobe_arm_test_cases(void); #endif + +void __kprobes_test_case_start(void); +void __kprobes_test_case_end_16(void); +void __kprobes_test_case_end_32(void); diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 636bab51de38d4e5b9348db84be5e11ec4187657..40a54b55ababd059e26ed894048fc445916fe96f 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -125,7 +125,7 @@ status = "okay"; clock-frequency = <100000>; i2c-sda-falling-time-ns = <890>; /* hcnt */ - i2c-sdl-falling-time-ns = <890>; /* lcnt */ + i2c-scl-falling-time-ns = <890>; /* lcnt */ adc@14 { compatible = "lltc,ltc2497"; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 90e9cbcc891f2f3d6df4e2cfdcd78ca86fcf7b58..d5f2f7593c67e2db8cd7a1af7ac20ab92bceb336 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -47,6 +47,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu1: cpu@1 { @@ -55,6 +56,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu2: cpu@2 { @@ -63,6 +65,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu3: cpu@3 { @@ -71,6 +74,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; l2: l2-cache0 { @@ -151,6 +155,28 @@ #clock-cells = <0>; }; + scpi { + compatible = "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + scpi_clocks: clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: clocks-0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index a127657526c7fc0cdd117e32afff08f32dabcec3..c167023ca1db7467da51a81217790bd88f5c2e2c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -150,7 +150,7 @@ reg = <0x14 0x10>; }; - eth_mac: eth_mac@34 { + eth_mac: eth-mac@34 { reg = <0x34 0x10>; }; @@ -167,7 +167,7 @@ scpi_clocks: clocks { compatible = "arm,scpi-clocks"; - scpi_dvfs: scpi_clocks@0 { + scpi_dvfs: clocks-0 { compatible = "arm,scpi-dvfs-clocks"; #clock-cells = <1>; clock-indices = <0>; @@ -423,7 +423,7 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; - hwrng: rng { + hwrng: rng@0 { compatible = "amlogic,meson-rng"; reg = <0x0 0x0 0x0 0x4>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 5d7724b3a612371fb52270123573710b79796b23..f999a92d174b778a19714b4cd818bed8ce5ac261 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -636,7 +636,7 @@ }; }; - eth-phy-mux { + eth-phy-mux@55c { compatible = "mdio-mux-mmioreg", "mdio-mux"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 2bcee994898a2e60214772e8dd4981ac9575864a..5cb0470ede723c5fbd0bb54e49e8ac38aedb8cff 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -380,6 +380,7 @@ pwm: pwm@11006000 { compatible = "mediatek,mt7622-pwm"; reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; interrupts = ; clocks = <&topckgen CLK_TOP_PWM_SEL>, <&pericfg CLK_PERI_PWM_PD>, diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 3e7baabf64507c5ec9985ee8fb31c7181b9c1e9e..4ee32583dc7c516d748a5c52b831a7d4b28336c3 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -382,6 +382,8 @@ reg = <0x4a9000 0x1000>, /* TM */ <0x4a8000 0x1000>; /* SROT */ #qcom,sensors = <13>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; @@ -390,6 +392,8 @@ reg = <0x4ad000 0x1000>, /* TM */ <0x4ac000 0x1000>; /* SROT */ #qcom,sensors = <8>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; @@ -899,6 +903,9 @@ #size-cells = <1>; ranges; + interrupts = ; + interrupt-names = "hs_phy_irq"; + clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, <&gcc GCC_USB20_MASTER_CLK>, <&gcc GCC_USB20_MOCK_UTMI_CLK>, diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 8bf3091a899c81ce9234ab05cfcb8aa9542700d7..5abffdaf4077e2dab48fbdde862509f059127c41 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -165,7 +165,7 @@ }; scif1_pins: scif1 { - groups = "scif1_data_b", "scif1_ctrl"; + groups = "scif1_data_b"; function = "scif1"; }; @@ -178,7 +178,6 @@ &scif1 { pinctrl-0 = <&scif1_pins>; pinctrl-names = "default"; - uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm64/configs/vendor/bengal-perf_defconfig b/arch/arm64/configs/vendor/bengal-perf_defconfig index 619093792cb94471be13e3cad23ebc11057eda82..04514a4eb146e84243dd2a470549d30203989aed 100644 --- a/arch/arm64/configs/vendor/bengal-perf_defconfig +++ b/arch/arm64/configs/vendor/bengal-perf_defconfig @@ -74,6 +74,7 @@ CONFIG_ENERGY_MODEL=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_TIMES=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y @@ -669,6 +670,7 @@ CONFIG_SCHEDSTATS=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_LIST=y CONFIG_IPC_LOGGING=y +CONFIG_CC_WERROR=y CONFIG_CORESIGHT=y CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y diff --git a/arch/arm64/configs/vendor/bengal_defconfig b/arch/arm64/configs/vendor/bengal_defconfig index c06a3ba2bb4559e0039f42613d8c6c423c6b41f8..1ff3e05be01076bfc1e7871f91651645871cbaf7 100644 --- a/arch/arm64/configs/vendor/bengal_defconfig +++ b/arch/arm64/configs/vendor/bengal_defconfig @@ -630,6 +630,7 @@ CONFIG_IIO=y CONFIG_QCOM_SPMI_ADC5=y CONFIG_PWM=y CONFIG_PWM_QTI_LPG=y +CONFIG_PWM_QCOM=y CONFIG_ARM_GIC_V3_ACL=y CONFIG_QCOM_MPM=y CONFIG_PHY_XGENE=y diff --git a/arch/arm64/configs/vendor/debugfs.config b/arch/arm64/configs/vendor/debugfs.config index 059013b6a88ad5f04baff671ae526dcf03bf7547..9841b7c9a4eb700348b4c597a5573829de5a99eb 100644 --- a/arch/arm64/configs/vendor/debugfs.config +++ b/arch/arm64/configs/vendor/debugfs.config @@ -1,2 +1,4 @@ +CONFIG_MSM_IDLE_STATS=n +CONFIG_PAGE_EXTENSION=n CONFIG_PAGE_OWNER=n CONFIG_DEBUG_FS=n diff --git a/arch/arm64/configs/vendor/kona-perf_defconfig b/arch/arm64/configs/vendor/kona-perf_defconfig index 63470d973613919e34b3ee76d35a9cddc84794ea..0265101aa300af090ef6a6dd76cb8693f9c7c9ed 100644 --- a/arch/arm64/configs/vendor/kona-perf_defconfig +++ b/arch/arm64/configs/vendor/kona-perf_defconfig @@ -76,6 +76,7 @@ CONFIG_ENERGY_MODEL=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_TIMES=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y @@ -554,8 +555,6 @@ CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_NINTENDO=y CONFIG_HID_PLANTRONICS=y -CONFIG_HID_PLAYSTATION=y -CONFIG_PLAYSTATION_FF=y CONFIG_HID_SONY=y CONFIG_SONY_FF=y CONFIG_HID_QVR=y @@ -827,6 +826,7 @@ CONFIG_SCHEDSTATS=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_LIST=y CONFIG_IPC_LOGGING=y +CONFIG_CC_WERROR=y CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_CORESIGHT=y CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y diff --git a/arch/arm64/configs/vendor/kona_defconfig b/arch/arm64/configs/vendor/kona_defconfig index e7fcc97c226fc88b075fe250d083fa0b10e46d76..6bd49ed6622332257c60cd9d7cb4c2c3abcace20 100644 --- a/arch/arm64/configs/vendor/kona_defconfig +++ b/arch/arm64/configs/vendor/kona_defconfig @@ -567,8 +567,6 @@ CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_NINTENDO=y CONFIG_HID_PLANTRONICS=y -CONFIG_HID_PLAYSTATION=y -CONFIG_PLAYSTATION_FF=y CONFIG_HID_SONY=y CONFIG_SONY_FF=y CONFIG_HID_QVR=y diff --git a/arch/arm64/configs/vendor/lito-perf_defconfig b/arch/arm64/configs/vendor/lito-perf_defconfig index cb9c0785fce8c35ab8b8248b3dccd6e2a9a4f5c5..a55e6e2687b53158a80250956419656a4d21e8c1 100644 --- a/arch/arm64/configs/vendor/lito-perf_defconfig +++ b/arch/arm64/configs/vendor/lito-perf_defconfig @@ -76,6 +76,7 @@ CONFIG_ENERGY_MODEL=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_TIMES=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y @@ -786,6 +787,7 @@ CONFIG_SCHEDSTATS=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_LIST=y CONFIG_IPC_LOGGING=y +CONFIG_CC_WERROR=y #CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_ARM64_STRICT_BREAK_BEFORE_MAKE=y #CONFIG_CORESIGHT=y diff --git a/arch/arm64/configs/vendor/sdm660_defconfig b/arch/arm64/configs/vendor/sdm660_defconfig index 10f0c960b2661ae36b89210ffd08146e29b08178..a4dd6c93618d8016b6bcfa21811dc6b524f1a6bc 100644 --- a/arch/arm64/configs/vendor/sdm660_defconfig +++ b/arch/arm64/configs/vendor/sdm660_defconfig @@ -623,7 +623,6 @@ CONFIG_MSM_PIL=y CONFIG_MSM_SYSMON_QMI_COMM=y CONFIG_MSM_PIL_SSR_GENERIC=y CONFIG_MSM_BOOT_STATS=y -CONFIG_QCOM_DCC_V2=y CONFIG_QCOM_EUD=y CONFIG_QCOM_MINIDUMP=y CONFIG_MSM_CORE_HANG_DETECT=y @@ -644,6 +643,7 @@ CONFIG_QCOM_SMCINVOKE=y CONFIG_MSM_EVENT_TIMER=y CONFIG_MSM_PM=y CONFIG_QTI_L2_REUSE=y +CONFIG_QCOM_DCC=y CONFIG_QTI_RPM_STATS_LOG=y CONFIG_QTEE_SHM_BRIDGE=y CONFIG_MEM_SHARE_QMI_SERVICE=y diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/asm/debug-monitors.h index 6bd2ab9746f8f6860865c3241c2c028004d82cc2..7236a0507ec4f79a647041a8a57de85b34052ab2 100644 --- a/arch/arm64/include/asm/debug-monitors.h +++ b/arch/arm64/include/asm/debug-monitors.h @@ -126,6 +126,7 @@ void user_regs_reset_single_step(struct user_pt_regs *regs, void kernel_enable_single_step(struct pt_regs *regs); void kernel_disable_single_step(void); int kernel_active_single_step(void); +void kernel_rewind_single_step(struct pt_regs *regs); #ifdef CONFIG_HAVE_HW_BREAKPOINT int reinstall_suspended_bps(struct pt_regs *regs); diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h index f52a2968a3b696270bc73adbb7adfdca1ce01744..590717af0a830b8a1249d2c2f95882e5ec4fd0ff 100644 --- a/arch/arm64/include/asm/efi.h +++ b/arch/arm64/include/asm/efi.h @@ -25,6 +25,7 @@ int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md); ({ \ efi_virtmap_load(); \ __efi_fpsimd_begin(); \ + spin_lock(&efi_rt_lock); \ }) #define arch_efi_call_virt(p, f, args...) \ @@ -36,10 +37,12 @@ int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md); #define arch_efi_call_virt_teardown() \ ({ \ + spin_unlock(&efi_rt_lock); \ __efi_fpsimd_end(); \ efi_virtmap_unload(); \ }) +extern spinlock_t efi_rt_lock; efi_status_t __efi_rt_asm_wrapper(void *, const char *, ...); #define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index bed5f1e4e53b3ec1fefa6c7a244e5d12081669df..904fa051758c27161e83f371f3eca950fad0904c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -108,8 +108,14 @@ #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) +#define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4) +#define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6) #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) +#define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4) +#define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6) #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) +#define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4) +#define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6) #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) diff --git a/arch/arm64/kernel/armv8_deprecated.c b/arch/arm64/kernel/armv8_deprecated.c index 7c69a203cdf8e88c7d72ed81b154ab8999c66114..b8d481c3e26dda6590852a6b47c0735b83417957 100644 --- a/arch/arm64/kernel/armv8_deprecated.c +++ b/arch/arm64/kernel/armv8_deprecated.c @@ -211,10 +211,12 @@ static int emulation_proc_handler(struct ctl_table *table, int write, loff_t *ppos) { int ret = 0; - struct insn_emulation *insn = container_of(table->data, struct insn_emulation, current_mode); - enum insn_emulation_mode prev_mode = insn->current_mode; + struct insn_emulation *insn; + enum insn_emulation_mode prev_mode; mutex_lock(&insn_emulation_mutex); + insn = container_of(table->data, struct insn_emulation, current_mode); + prev_mode = insn->current_mode; ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); if (ret || !write || prev_mode == insn->current_mode) diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c index 501e835c65007899d1ddd9edbea3981a0a54b286..f5837937cd93285be74c63bd691b41c760065a4c 100644 --- a/arch/arm64/kernel/debug-monitors.c +++ b/arch/arm64/kernel/debug-monitors.c @@ -437,6 +437,11 @@ int kernel_active_single_step(void) } NOKPROBE_SYMBOL(kernel_active_single_step); +void kernel_rewind_single_step(struct pt_regs *regs) +{ + set_regs_spsr_ss(regs); +} + /* ptrace API */ void user_enable_single_step(struct task_struct *task) { diff --git a/arch/arm64/kernel/efi-rt-wrapper.S b/arch/arm64/kernel/efi-rt-wrapper.S index f5cea7b0f1aa6d9aa53f58e28cfc5fe6d02db2bb..92b1f6490b7f15f2ebbb6e0492225e2d3a83ed60 100644 --- a/arch/arm64/kernel/efi-rt-wrapper.S +++ b/arch/arm64/kernel/efi-rt-wrapper.S @@ -7,6 +7,7 @@ */ #include +#include ENTRY(__efi_rt_asm_wrapper) stp x29, x30, [sp, #-32]! @@ -19,6 +20,12 @@ ENTRY(__efi_rt_asm_wrapper) */ stp x1, x18, [sp, #16] + ldr_l x16, efi_rt_stack_top + mov sp, x16 +#ifdef CONFIG_SHADOW_CALL_STACK + str x18, [sp, #-16]! +#endif + /* * We are lucky enough that no EFI runtime services take more than * 5 arguments, so all are passed in registers rather than via the @@ -32,19 +39,22 @@ ENTRY(__efi_rt_asm_wrapper) mov x4, x6 blr x8 + mov sp, x29 ldp x1, x2, [sp, #16] cmp x2, x18 ldp x29, x30, [sp], #32 b.ne 0f ret 0: -#ifdef CONFIG_SHADOW_CALL_STACK /* * Restore x18 before returning to instrumented code. This is * safe because the wrapper is called with preemption disabled and * a separate shadow stack is used for interrupts. */ - mov x18, x2 +#ifdef CONFIG_SHADOW_CALL_STACK + ldr_l x18, efi_rt_stack_top + ldr x18, [x18, #-16] #endif + b efi_handle_corrupted_x18 // tail call ENDPROC(__efi_rt_asm_wrapper) diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c index 5b425ed9cd8231b8336fbcddeceafa21b7d9d075..e2dd21489b0bdad5dff8040eadd10d10bfe5e1b2 100644 --- a/arch/arm64/kernel/efi.c +++ b/arch/arm64/kernel/efi.c @@ -148,3 +148,31 @@ asmlinkage efi_status_t efi_handle_corrupted_x18(efi_status_t s, const char *f) pr_err_ratelimited(FW_BUG "register x18 corrupted by EFI %s\n", f); return s; } + +DEFINE_SPINLOCK(efi_rt_lock); + +asmlinkage u64 *efi_rt_stack_top __ro_after_init; + +/* EFI requires 8 KiB of stack space for runtime services */ +static_assert(THREAD_SIZE >= SZ_8K); + +static int __init arm64_efi_rt_init(void) +{ + void *p; + + if (!efi_enabled(EFI_RUNTIME_SERVICES)) + return 0; + + p = __vmalloc_node_range(THREAD_SIZE, THREAD_ALIGN, VMALLOC_START, + VMALLOC_END, GFP_KERNEL, PAGE_KERNEL, 0, + NUMA_NO_NODE, &&l); +l: if (!p) { + pr_warn("Failed to allocate EFI runtime stack\n"); + clear_bit(EFI_RUNTIME_SERVICES, &efi.flags); + return -ENOMEM; + } + + efi_rt_stack_top = p + THREAD_SIZE; + return 0; +} +core_initcall(arm64_efi_rt_init); diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c index b4efae4925639706b30d8b25d729089fc3f7089a..4554adb136421d8eaf9d85ca0f6fca96bfa1f5cf 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -661,7 +661,7 @@ static int breakpoint_handler(unsigned long unused, unsigned int esr, perf_bp_event(bp, regs); /* Do we need to handle the stepping? */ - if (is_default_overflow_handler(bp)) + if (uses_default_overflow_handler(bp)) step = 1; unlock: rcu_read_unlock(); @@ -740,7 +740,7 @@ static u64 get_distance_from_watchpoint(unsigned long addr, u64 val, static int watchpoint_report(struct perf_event *wp, unsigned long addr, struct pt_regs *regs) { - int step = is_default_overflow_handler(wp); + int step = uses_default_overflow_handler(wp); struct arch_hw_breakpoint *info = counter_arch_bp(wp); info->trigger = addr; diff --git a/arch/arm64/kernel/kgdb.c b/arch/arm64/kernel/kgdb.c index 8815b5457dd0b4e70416a329df6937416bd875cc..d7847ef10e9d34c7bdab7d6d7c51173b64bbcd74 100644 --- a/arch/arm64/kernel/kgdb.c +++ b/arch/arm64/kernel/kgdb.c @@ -234,6 +234,8 @@ int kgdb_arch_handle_exception(int exception_vector, int signo, */ if (!kernel_active_single_step()) kernel_enable_single_step(linux_regs); + else + kernel_rewind_single_step(linux_regs); err = 0; break; default: diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 870e594f95edda61e785de85b92148080febd03c..b509afa0547014dd0b41131551a452119105ddb1 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -57,9 +57,8 @@ static u64 core_reg_offset_from_id(u64 id) return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE); } -static int validate_core_offset(const struct kvm_one_reg *reg) +static int core_reg_size_from_offset(u64 off) { - u64 off = core_reg_offset_from_id(reg->id); int size; switch (off) { @@ -89,11 +88,24 @@ static int validate_core_offset(const struct kvm_one_reg *reg) return -EINVAL; } - if (KVM_REG_SIZE(reg->id) == size && - IS_ALIGNED(off, size / sizeof(__u32))) - return 0; + if (!IS_ALIGNED(off, size / sizeof(__u32))) + return -EINVAL; - return -EINVAL; + return size; +} + +static int validate_core_offset(const struct kvm_one_reg *reg) +{ + u64 off = core_reg_offset_from_id(reg->id); + int size = core_reg_size_from_offset(off); + + if (size < 0) + return -EINVAL; + + if (KVM_REG_SIZE(reg->id) != size) + return -EINVAL; + + return 0; } static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) @@ -200,9 +212,51 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) return -EINVAL; } +static int kvm_arm_copy_core_reg_indices(u64 __user *uindices) +{ + unsigned int i; + int n = 0; + + for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) { + u64 reg = KVM_REG_ARM64 | KVM_REG_ARM_CORE | i; + int size = core_reg_size_from_offset(i); + + if (size < 0) + continue; + + switch (size) { + case sizeof(__u32): + reg |= KVM_REG_SIZE_U32; + break; + + case sizeof(__u64): + reg |= KVM_REG_SIZE_U64; + break; + + case sizeof(__uint128_t): + reg |= KVM_REG_SIZE_U128; + break; + + default: + WARN_ON(1); + continue; + } + + if (uindices) { + if (put_user(reg, uindices)) + return -EFAULT; + uindices++; + } + + n++; + } + + return n; +} + static unsigned long num_core_regs(void) { - return sizeof(struct kvm_regs) / sizeof(__u32); + return kvm_arm_copy_core_reg_indices(NULL); } /** @@ -276,23 +330,20 @@ unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu) */ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) { - unsigned int i; - const u64 core_reg = KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE; int ret; - for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) { - if (put_user(core_reg | i, uindices)) - return -EFAULT; - uindices++; - } + ret = kvm_arm_copy_core_reg_indices(uindices); + if (ret < 0) + return ret; + uindices += ret; ret = kvm_arm_copy_fw_reg_indices(vcpu, uindices); - if (ret) + if (ret < 0) return ret; uindices += kvm_arm_get_fw_num_regs(vcpu); ret = copy_timer_indices(vcpu, uindices); - if (ret) + if (ret < 0) return ret; uindices += NUM_TIMER_REGS; diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 656cd5c1c287b80d4ec906f71e3b550ed79b26d1..fab8b2f4ac70e1f62cbd359c550542398f492a5c 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -393,8 +393,8 @@ static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *re } } -#define VM_FAULT_BADMAP 0x010000 -#define VM_FAULT_BADACCESS 0x020000 +#define VM_FAULT_BADMAP ((__force vm_fault_t)0x010000) +#define VM_FAULT_BADACCESS ((__force vm_fault_t)0x020000) static int __do_page_fault(struct vm_area_struct *vma, unsigned long addr, unsigned int mm_flags, unsigned long vm_flags, diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 0d56b19b7511ac0bd924fc0124bbd628776db767..58f63446c6570e7ed13ef1d71af6f2448438effc 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -8,6 +8,7 @@ menu "Processor type and features" config IA64 bool + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_MIGHT_HAVE_PC_SERIO select PCI if (!IA64_HP_SIM) diff --git a/arch/ia64/include/asm/bugs.h b/arch/ia64/include/asm/bugs.h deleted file mode 100644 index 0d6b9bded56c6ba2d9c1e381fd05496cf25f86ff..0000000000000000000000000000000000000000 --- a/arch/ia64/include/asm/bugs.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - * - * Based on . - * - * Modified 1998, 1999, 2003 - * David Mosberger-Tang , Hewlett-Packard Co. - */ -#ifndef _ASM_IA64_BUGS_H -#define _ASM_IA64_BUGS_H - -#include - -extern void check_bugs (void); - -#endif /* _ASM_IA64_BUGS_H */ diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c index 968b5f33e725e738a72510883bf693bab6c3c617..1a8e20652e7ce844020c7b9700ce715fa0bac079 100644 --- a/arch/ia64/kernel/process.c +++ b/arch/ia64/kernel/process.c @@ -444,7 +444,7 @@ static void do_copy_task_regs (struct task_struct *task, struct unw_frame_info *info, void *arg) { unsigned long mask, sp, nat_bits = 0, ar_rnat, urbs_end, cfm; - unsigned long uninitialized_var(ip); /* GCC be quiet */ + unsigned long ip; elf_greg_t *dst = arg; struct pt_regs *pt; char nat; diff --git a/arch/ia64/kernel/salinfo.c b/arch/ia64/kernel/salinfo.c index aba1f463a8dd43375cd0e6e204bb972cf73f2635..b889db4492c8d4b5f919420e1530565eb9e6bb27 100644 --- a/arch/ia64/kernel/salinfo.c +++ b/arch/ia64/kernel/salinfo.c @@ -580,7 +580,7 @@ static int salinfo_cpu_pre_down(unsigned int cpu) * 'data' contains an integer that corresponds to the feature we're * testing */ -static int proc_salinfo_show(struct seq_file *m, void *v) +static int __maybe_unused proc_salinfo_show(struct seq_file *m, void *v) { unsigned long data = (unsigned long)v; seq_puts(m, (sal_platform_features & data) ? "1\n" : "0\n"); diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c index 0e6c2d9fb49876b6e7147151eec5cbb458c4231b..41af687bc1dc6084bdaaa750d3fe0c8b2c7631aa 100644 --- a/arch/ia64/kernel/setup.c +++ b/arch/ia64/kernel/setup.c @@ -1050,8 +1050,7 @@ cpu_init (void) platform_cpu_init(); } -void __init -check_bugs (void) +void __init arch_cpu_finalize_init(void) { ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, (unsigned long) __end___mckinley_e9_bundles); diff --git a/arch/ia64/mm/contig.c b/arch/ia64/mm/contig.c index e2e40bbd391c6a3207dc8d5cd1215abad84371c5..18a2b105f7f307964ea6547d9604bb644a774532 100644 --- a/arch/ia64/mm/contig.c +++ b/arch/ia64/mm/contig.c @@ -82,7 +82,7 @@ void *per_cpu_init(void) return __per_cpu_start + __per_cpu_offset[smp_processor_id()]; } -static inline void +static inline __init void alloc_per_cpu_data(void) { cpu_data = __alloc_bootmem(PERCPU_PAGE_SIZE * num_possible_cpus(), diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c index db3104c9fac53a5ab53a9d10e9cd1ceb7635b629..33f68be018a22627d42a4c5044d8c74228798bc6 100644 --- a/arch/ia64/mm/discontig.c +++ b/arch/ia64/mm/discontig.c @@ -181,7 +181,7 @@ static void *per_cpu_node_setup(void *cpu_data, int node) void __init setup_per_cpu_areas(void) { struct pcpu_alloc_info *ai; - struct pcpu_group_info *uninitialized_var(gi); + struct pcpu_group_info *gi; unsigned int *cpu_map; void *base; unsigned long base_offset; diff --git a/arch/ia64/mm/tlb.c b/arch/ia64/mm/tlb.c index acf10eb9da15c13252411746fe603785a61bffd7..02470929fb3938aebf951304a26817d4e5723c35 100644 --- a/arch/ia64/mm/tlb.c +++ b/arch/ia64/mm/tlb.c @@ -339,7 +339,7 @@ EXPORT_SYMBOL(flush_tlb_range); void ia64_tlb_init(void) { - ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */ + ia64_ptce_info_t ptce_info; u64 tr_pgbits; long status; pal_vm_info_1_u_t vm_info_1; diff --git a/arch/m68k/68000/entry.S b/arch/m68k/68000/entry.S index 259b3661b614168ff8ab377587c66b1478222218..94abf3d8afc52588806f7e7007ddd6ee896b399a 100644 --- a/arch/m68k/68000/entry.S +++ b/arch/m68k/68000/entry.S @@ -47,6 +47,8 @@ do_trace: jbsr syscall_trace_enter RESTORE_SWITCH_STACK addql #4,%sp + addql #1,%d0 + jeq ret_from_exception movel %sp@(PT_OFF_ORIG_D0),%d1 movel #-ENOSYS,%d0 cmpl #NR_syscalls,%d1 diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 070553791e9774e035f7add07c782c2d3b89f0d1..05b7e4cbb16e0970f238a05027a1db0cf1dcc198 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -2,6 +2,7 @@ config M68K bool default y + select ARCH_HAS_CPU_FINALIZE_INIT if MMU select ARCH_HAS_SYNC_DMA_FOR_DEVICE if HAS_DMA select ARCH_MIGHT_HAVE_PC_PARPORT if ISA select ARCH_NO_COHERENT_DMA_MMAP if !MMU diff --git a/arch/m68k/Kconfig.devices b/arch/m68k/Kconfig.devices index 3e9b0b826f8a17d22d06c4823b105f409ef563d5..6fb693bb0771cb06713b98f31265912cdb3035fa 100644 --- a/arch/m68k/Kconfig.devices +++ b/arch/m68k/Kconfig.devices @@ -19,6 +19,7 @@ config HEARTBEAT # We have a dedicated heartbeat LED. :-) config PROC_HARDWARE bool "/proc/hardware support" + depends on PROC_FS help Say Y here to support the /proc/hardware file, which gives you access to information about the machine you're running on, diff --git a/arch/m68k/coldfire/entry.S b/arch/m68k/coldfire/entry.S index 52d312d5b4d4f68337aa8f9b711f50b1a1ad9eda..fb3b06567745972cbceb9ae5ad9395432c7cea99 100644 --- a/arch/m68k/coldfire/entry.S +++ b/arch/m68k/coldfire/entry.S @@ -92,6 +92,8 @@ ENTRY(system_call) jbsr syscall_trace_enter RESTORE_SWITCH_STACK addql #4,%sp + addql #1,%d0 + jeq ret_from_exception movel %d3,%a0 jbsr %a0@ movel %d0,%sp@(PT_OFF_D0) /* save the return value */ diff --git a/arch/m68k/fpsp040/skeleton.S b/arch/m68k/fpsp040/skeleton.S index a8f41615d94a7283db6638117c59eb91b41f8df8..31a9c634c81ed2a0db75274b6360e6aa0d6e3ede 100644 --- a/arch/m68k/fpsp040/skeleton.S +++ b/arch/m68k/fpsp040/skeleton.S @@ -499,12 +499,12 @@ in_ea: dbf %d0,morein rts - .section .fixup,#alloc,#execinstr + .section .fixup,"ax" .even 1: jbra fpsp040_die - .section __ex_table,#alloc + .section __ex_table,"a" .align 4 .long in_ea,1b diff --git a/arch/m68k/ifpsp060/os.S b/arch/m68k/ifpsp060/os.S index 7a0d6e42806656a59f7b5da80f019aed1d1626c6..89e2ec224ab6c7674b19f29c10892987ae575ff4 100644 --- a/arch/m68k/ifpsp060/os.S +++ b/arch/m68k/ifpsp060/os.S @@ -379,11 +379,11 @@ _060_real_access: | Execption handling for movs access to illegal memory - .section .fixup,#alloc,#execinstr + .section .fixup,"ax" .even 1: moveq #-1,%d1 rts -.section __ex_table,#alloc +.section __ex_table,"a" .align 4 .long dmrbuae,1b .long dmrwuae,1b diff --git a/arch/m68k/include/asm/bugs.h b/arch/m68k/include/asm/bugs.h deleted file mode 100644 index 745530651e0bfd39a6b1c06c464eb8e4cbdd66ee..0000000000000000000000000000000000000000 --- a/arch/m68k/include/asm/bugs.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/asm-m68k/bugs.h - * - * Copyright (C) 1994 Linus Torvalds - */ - -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ - -#ifdef CONFIG_MMU -extern void check_bugs(void); /* in arch/m68k/kernel/setup.c */ -#else -static void check_bugs(void) -{ -} -#endif diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S index 97cd3ea5f10b837949b124024951912d6973e8f6..9a66657773beb3613087d8319742830646a4eae1 100644 --- a/arch/m68k/kernel/entry.S +++ b/arch/m68k/kernel/entry.S @@ -160,9 +160,12 @@ do_trace_entry: jbsr syscall_trace RESTORE_SWITCH_STACK addql #4,%sp + addql #1,%d0 | optimization for cmpil #-1,%d0 + jeq ret_from_syscall movel %sp@(PT_OFF_ORIG_D0),%d0 cmpl #NR_syscalls,%d0 jcs syscall + jra ret_from_syscall badsys: movel #-ENOSYS,%sp@(PT_OFF_D0) jra ret_from_syscall diff --git a/arch/m68k/kernel/relocate_kernel.S b/arch/m68k/kernel/relocate_kernel.S index ab0f1e7d465353b87ffb243cf798a6d04bff4b19..f7667079e08e997a5611880fa34b2d772d2403be 100644 --- a/arch/m68k/kernel/relocate_kernel.S +++ b/arch/m68k/kernel/relocate_kernel.S @@ -26,7 +26,7 @@ ENTRY(relocate_new_kernel) lea %pc@(.Lcopy),%a4 2: addl #0x00000000,%a4 /* virt_to_phys() */ - .section ".m68k_fixup","aw" + .section .m68k_fixup,"aw" .long M68K_FIXUP_MEMOFFSET, 2b+2 .previous @@ -49,7 +49,7 @@ ENTRY(relocate_new_kernel) lea %pc@(.Lcont040),%a4 5: addl #0x00000000,%a4 /* virt_to_phys() */ - .section ".m68k_fixup","aw" + .section .m68k_fixup,"aw" .long M68K_FIXUP_MEMOFFSET, 5b+2 .previous diff --git a/arch/m68k/kernel/setup_mm.c b/arch/m68k/kernel/setup_mm.c index de44899c0e6172957a8d88d7ac6df9aee5c439cb..461e14f46cfe5bbfb2376117f2e3b7ad767b6d56 100644 --- a/arch/m68k/kernel/setup_mm.c +++ b/arch/m68k/kernel/setup_mm.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -526,7 +527,7 @@ static int __init proc_hardware_init(void) module_init(proc_hardware_init); #endif -void check_bugs(void) +void __init arch_cpu_finalize_init(void) { #if defined(CONFIG_FPU) && !defined(CONFIG_M68KFPU_EMU) if (m68k_fputype == 0) { diff --git a/arch/m68k/kernel/signal.c b/arch/m68k/kernel/signal.c index c67a68b6b69d1c689d394c3b2f8f24c5e752be98..d08c771b59c1cecddb29d55c96a51f017e9e013e 100644 --- a/arch/m68k/kernel/signal.c +++ b/arch/m68k/kernel/signal.c @@ -882,11 +882,17 @@ static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs * } static inline void __user * -get_sigframe(struct ksignal *ksig, size_t frame_size) +get_sigframe(struct ksignal *ksig, struct pt_regs *tregs, size_t frame_size) { unsigned long usp = sigsp(rdusp(), ksig); + unsigned long gap = 0; - return (void __user *)((usp - frame_size) & -8UL); + if (CPU_IS_020_OR_030 && tregs->format == 0xb) { + /* USP is unreliable so use worst-case value */ + gap = 256; + } + + return (void __user *)((usp - gap - frame_size) & -8UL); } static int setup_frame(struct ksignal *ksig, sigset_t *set, @@ -904,7 +910,7 @@ static int setup_frame(struct ksignal *ksig, sigset_t *set, return -EFAULT; } - frame = get_sigframe(ksig, sizeof(*frame) + fsize); + frame = get_sigframe(ksig, tregs, sizeof(*frame) + fsize); if (fsize) err |= copy_to_user (frame + 1, regs + 1, fsize); @@ -975,7 +981,7 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, return -EFAULT; } - frame = get_sigframe(ksig, sizeof(*frame)); + frame = get_sigframe(ksig, tregs, sizeof(*frame)); if (fsize) err |= copy_to_user (&frame->uc.uc_extra, regs + 1, fsize); diff --git a/arch/m68k/kernel/traps.c b/arch/m68k/kernel/traps.c index 9b70a7f5e7058f9c52441f44fedb5ef224894aa4..35f706d836c501d1eaba0b20a50154742e8e1099 100644 --- a/arch/m68k/kernel/traps.c +++ b/arch/m68k/kernel/traps.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -550,7 +551,8 @@ static inline void bus_error030 (struct frame *fp) errorcode |= 2; if (mmusr & (MMU_I | MMU_WP)) { - if (ssw & 4) { + /* We might have an exception table for this PC */ + if (ssw & 4 && !search_exception_tables(fp->ptregs.pc)) { pr_err("Data %s fault at %#010lx in %s (pc=%#lx)\n", ssw & RW ? "read" : "write", fp->un.fmtb.daddr, diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 59130653b242144aefb1ea6474dfb9dae4345eea..d67714802e7986239218066b6566e3bf70810250 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,6 +4,7 @@ config MIPS default y select ARCH_BINFMT_ELF_STATE select ARCH_CLOCKSOURCE_DATA + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_DISCARD_MEMBLOCK select ARCH_HAS_ELF_RANDOMIZE select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c index 13e3c84859fe760c0a4c109211be06f52135c58f..548bd4db0f9760fa90b6b187cf202ef3bf992b61 100644 --- a/arch/mips/alchemy/devboards/db1000.c +++ b/arch/mips/alchemy/devboards/db1000.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -174,14 +173,10 @@ static struct platform_device db1x00_audio_dev = { /******************************************************************************/ +#ifdef CONFIG_MMC_AU1X static irqreturn_t db1100_mmc_cd(int irq, void *ptr) { - void (*mmc_cd)(struct mmc_host *, unsigned long); - /* link against CONFIG_MMC=m */ - mmc_cd = symbol_get(mmc_detect_change); - mmc_cd(ptr, msecs_to_jiffies(500)); - symbol_put(mmc_detect_change); - + mmc_detect_change(ptr, msecs_to_jiffies(500)); return IRQ_HANDLED; } @@ -386,6 +381,7 @@ static struct platform_device db1100_mmc1_dev = { .num_resources = ARRAY_SIZE(au1100_mmc1_res), .resource = au1100_mmc1_res, }; +#endif /* CONFIG_MMC_AU1X */ /******************************************************************************/ @@ -503,9 +499,11 @@ static struct platform_device *db1000_devs[] = { static struct platform_device *db1100_devs[] = { &au1100_lcd_device, +#ifdef CONFIG_MMC_AU1X &db1100_mmc0_dev, &db1100_mmc1_dev, &db1000_irda_dev, +#endif }; int __init db1000_dev_setup(void) diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c index da76637704253e3610f4f15b69a42e75af99d516..48840e48e79a0e6a5daddc23308bff5be3e9e448 100644 --- a/arch/mips/alchemy/devboards/db1200.c +++ b/arch/mips/alchemy/devboards/db1200.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -342,6 +341,7 @@ static struct platform_device db1200_ide_dev = { /**********************************************************************/ +#ifdef CONFIG_MMC_AU1X /* SD carddetects: they're supposed to be edge-triggered, but ack * doesn't seem to work (CPLD Rev 2). Instead, the screaming one * is disabled and its counterpart enabled. The 200ms timeout is @@ -355,14 +355,7 @@ static irqreturn_t db1200_mmc_cd(int irq, void *ptr) static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr) { - void (*mmc_cd)(struct mmc_host *, unsigned long); - - /* link against CONFIG_MMC=m */ - mmc_cd = symbol_get(mmc_detect_change); - if (mmc_cd) { - mmc_cd(ptr, msecs_to_jiffies(200)); - symbol_put(mmc_detect_change); - } + mmc_detect_change(ptr, msecs_to_jiffies(200)); msleep(100); /* debounce */ if (irq == DB1200_SD0_INSERT_INT) @@ -446,14 +439,7 @@ static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr) static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr) { - void (*mmc_cd)(struct mmc_host *, unsigned long); - - /* link against CONFIG_MMC=m */ - mmc_cd = symbol_get(mmc_detect_change); - if (mmc_cd) { - mmc_cd(ptr, msecs_to_jiffies(200)); - symbol_put(mmc_detect_change); - } + mmc_detect_change(ptr, msecs_to_jiffies(200)); msleep(100); /* debounce */ if (irq == PB1200_SD1_INSERT_INT) @@ -616,6 +602,7 @@ static struct platform_device pb1200_mmc1_dev = { .num_resources = ARRAY_SIZE(au1200_mmc1_res), .resource = au1200_mmc1_res, }; +#endif /* CONFIG_MMC_AU1X */ /**********************************************************************/ @@ -783,7 +770,9 @@ static struct platform_device db1200_audiodma_dev = { static struct platform_device *db1200_devs[] __initdata = { NULL, /* PSC0, selected by S6.8 */ &db1200_ide_dev, +#ifdef CONFIG_MMC_AU1X &db1200_mmc0_dev, +#endif &au1200_lcd_dev, &db1200_eth_dev, &db1200_nand_dev, @@ -794,7 +783,9 @@ static struct platform_device *db1200_devs[] __initdata = { }; static struct platform_device *pb1200_devs[] __initdata = { +#ifdef CONFIG_MMC_AU1X &pb1200_mmc1_dev, +#endif }; /* Some peripheral base addresses differ on the PB1200 */ diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c index efb318e03e0a3d53163307d84c0d850c6a747869..664a5a783d2c5118605654811625a4e3b4d45dd5 100644 --- a/arch/mips/alchemy/devboards/db1300.c +++ b/arch/mips/alchemy/devboards/db1300.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -449,6 +448,7 @@ static struct platform_device db1300_ide_dev = { /**********************************************************************/ +#ifdef CONFIG_MMC_AU1X static irqreturn_t db1300_mmc_cd(int irq, void *ptr) { disable_irq_nosync(irq); @@ -457,14 +457,7 @@ static irqreturn_t db1300_mmc_cd(int irq, void *ptr) static irqreturn_t db1300_mmc_cdfn(int irq, void *ptr) { - void (*mmc_cd)(struct mmc_host *, unsigned long); - - /* link against CONFIG_MMC=m. We can only be called once MMC core has - * initialized the controller, so symbol_get() should always succeed. - */ - mmc_cd = symbol_get(mmc_detect_change); - mmc_cd(ptr, msecs_to_jiffies(200)); - symbol_put(mmc_detect_change); + mmc_detect_change(ptr, msecs_to_jiffies(200)); msleep(100); /* debounce */ if (irq == DB1300_SD1_INSERT_INT) @@ -634,6 +627,7 @@ static struct platform_device db1300_sd0_dev = { .resource = au1300_sd0_res, .num_resources = ARRAY_SIZE(au1300_sd0_res), }; +#endif /* CONFIG_MMC_AU1X */ /**********************************************************************/ @@ -764,8 +758,10 @@ static struct platform_device *db1300_dev[] __initdata = { &db1300_5waysw_dev, &db1300_nand_dev, &db1300_ide_dev, +#ifdef CONFIG_MMC_AU1X &db1300_sd0_dev, &db1300_sd1_dev, +#endif &db1300_lcd_dev, &db1300_ac97_dev, &db1300_i2s_dev, diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig index 55438fc9991ec53715b392f074dbb3d864dc197c..e5976b2972fb08d9966bb235f17ed17c3ca60486 100644 --- a/arch/mips/configs/gpr_defconfig +++ b/arch/mips/configs/gpr_defconfig @@ -73,7 +73,6 @@ CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -104,7 +103,6 @@ CONFIG_ATM_MPOA=m CONFIG_ATM_BR2684=m CONFIG_BRIDGE=m CONFIG_VLAN_8021Q=m -CONFIG_DECNET=m CONFIG_LLC2=m CONFIG_IPX=m CONFIG_ATALK=m diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig index aa101c27ed258cc44851a556e7285b480d3e9cb8..67620b1a0c64e0cd7498134b4550d87611e0bbb5 100644 --- a/arch/mips/configs/jazz_defconfig +++ b/arch/mips/configs/jazz_defconfig @@ -120,7 +120,6 @@ CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -142,7 +141,6 @@ CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_ULOG=m CONFIG_BRIDGE=m -CONFIG_DECNET=m CONFIG_NET_SCHED=y CONFIG_NET_SCH_CBQ=m CONFIG_NET_SCH_HTB=m diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index 6895430b5b2c47beb99a33de6c39a34ae7d94f28..87c0b7a349290914fa55698f9b0970894fb699c5 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -108,7 +108,6 @@ CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -139,7 +138,6 @@ CONFIG_ATM_MPOA=m CONFIG_ATM_BR2684=m CONFIG_BRIDGE=m CONFIG_VLAN_8021Q=m -CONFIG_DECNET=m CONFIG_LLC2=m CONFIG_IPX=m CONFIG_ATALK=m diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig index e8e1dd8e0e99cd525dff3e5b2f9bd8de413461a4..8a13ae190245cd0827f3bd194d8927de1c9acef6 100644 --- a/arch/mips/configs/nlm_xlp_defconfig +++ b/arch/mips/configs/nlm_xlp_defconfig @@ -217,7 +217,6 @@ CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m CONFIG_IP6_NF_SECURITY=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -252,7 +251,6 @@ CONFIG_ATM_BR2684=m CONFIG_BRIDGE=m CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y -CONFIG_DECNET=m CONFIG_LLC2=m CONFIG_IPX=m CONFIG_ATALK=m diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig index c4477a4d40c119b5ad053cdca84de40a9996fc32..be1927e157a6e87c7e375e790379f87349cff22b 100644 --- a/arch/mips/configs/nlm_xlr_defconfig +++ b/arch/mips/configs/nlm_xlr_defconfig @@ -198,7 +198,6 @@ CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m CONFIG_IP6_NF_SECURITY=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -233,7 +232,6 @@ CONFIG_ATM_BR2684=m CONFIG_BRIDGE=m CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y -CONFIG_DECNET=m CONFIG_LLC2=m CONFIG_IPX=m CONFIG_ATALK=m diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index 194df200daadac51f1cef5c6069622f25aee8ad7..0004080a11c33d4f62521cf81cac2d6de0784b69 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -129,7 +129,6 @@ CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -151,7 +150,6 @@ CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_ULOG=m CONFIG_BRIDGE=m -CONFIG_DECNET=m CONFIG_NET_SCHED=y CONFIG_NET_SCH_CBQ=m CONFIG_NET_SCH_HTB=m diff --git a/arch/mips/fw/lib/cmdline.c b/arch/mips/fw/lib/cmdline.c index 6ecda64ad18423f5e27e22cf9ccf8786a5062cac..ed88abc40513be1575379d5a78bae66ac037a2a2 100644 --- a/arch/mips/fw/lib/cmdline.c +++ b/arch/mips/fw/lib/cmdline.c @@ -51,7 +51,7 @@ char *fw_getenv(char *envname) { char *result = NULL; - if (_fw_envp != NULL) { + if (_fw_envp != NULL && fw_envp(0) != NULL) { /* * Return a pointer to the given environment variable. * YAMON uses "name", "value" pairs, while U-Boot uses diff --git a/arch/mips/include/asm/bugs.h b/arch/mips/include/asm/bugs.h index d8ab8b7129b53ccd6e0f11bdcb08f2506d3c1887..6d04d7d3a8f2d4b02794dac831dba3b0f4dae00e 100644 --- a/arch/mips/include/asm/bugs.h +++ b/arch/mips/include/asm/bugs.h @@ -1,17 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This is included by init/main.c to check for architecture-dependent bugs. - * * Copyright (C) 2007 Maciej W. Rozycki - * - * Needs: - * void check_bugs(void); */ #ifndef _ASM_BUGS_H #define _ASM_BUGS_H #include -#include #include #include @@ -31,17 +25,6 @@ static inline void check_bugs_early(void) #endif } -static inline void check_bugs(void) -{ - unsigned int cpu = smp_processor_id(); - - cpu_data[cpu].udelay_val = loops_per_jiffy; - check_bugs32(); -#ifdef CONFIG_64BIT - check_bugs64(); -#endif -} - static inline int r4k_daddiu_bug(void) { #ifdef CONFIG_64BIT diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 4e2ee743088fd4deedadfa4f780595b6ce4d0729..51faee420745441b94934ac0c6fbb468f63b5b00 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -111,7 +111,24 @@ #define cpu_has_tx39_cache __opt(MIPS_CPU_TX39_CACHE) #endif #ifndef cpu_has_octeon_cache -#define cpu_has_octeon_cache 0 +#define cpu_has_octeon_cache \ +({ \ + int __res; \ + \ + switch (boot_cpu_type()) { \ + case CPU_CAVIUM_OCTEON: \ + case CPU_CAVIUM_OCTEON_PLUS: \ + case CPU_CAVIUM_OCTEON2: \ + case CPU_CAVIUM_OCTEON3: \ + __res = 1; \ + break; \ + \ + default: \ + __res = 0; \ + } \ + \ + __res; \ +}) #endif /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ #ifndef cpu_has_fpu @@ -332,7 +349,7 @@ ({ \ int __res; \ \ - switch (current_cpu_type()) { \ + switch (boot_cpu_type()) { \ case CPU_M14KC: \ case CPU_74K: \ case CPU_1074K: \ diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h index 09538ff5e92457f08ac944f00c8dc8c06588666e..6f0405ba27d6df386d0d50e296ba6b2e86b9e21d 100644 --- a/arch/mips/include/asm/dec/prom.h +++ b/arch/mips/include/asm/dec/prom.h @@ -74,7 +74,7 @@ static inline bool prom_is_rex(u32 magic) */ typedef struct { int pagesize; - unsigned char bitmap[0]; + unsigned char bitmap[]; } memmap; diff --git a/arch/mips/include/asm/mach-rc32434/pci.h b/arch/mips/include/asm/mach-rc32434/pci.h index 6f40d1515580b0eff73f1b5169393eb0d244bcf8..1ff8a987025c8ee726d5434cfb87a9090f130fa5 100644 --- a/arch/mips/include/asm/mach-rc32434/pci.h +++ b/arch/mips/include/asm/mach-rc32434/pci.h @@ -377,7 +377,7 @@ struct pci_msu { PCI_CFG04_STAT_SSE | \ PCI_CFG04_STAT_PE) -#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD) +#define KORINA_CNFG1 (KORINA_STAT | KORINA_CMD) #define KORINA_REVID 0 #define KORINA_CLASS_CODE 0 diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h index 6cf8ffb5367ec3fb725aac26c701d0ae5d81923c..94d8c945ea8ebf9e49f7d681f90d867acd066488 100644 --- a/arch/mips/include/asm/syscall.h +++ b/arch/mips/include/asm/syscall.h @@ -38,7 +38,7 @@ static inline bool mips_syscall_is_indirect(struct task_struct *task, static inline long syscall_get_nr(struct task_struct *task, struct pt_regs *regs) { - return current_thread_info()->syscall; + return task_thread_info(task)->syscall; } static inline void mips_syscall_update_nr(struct task_struct *task, diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h index 80e70dbd1f6417aaecf22871e8e82fefc130f8bf..012731546cf607f999b8a5dacf29dce164815be2 100644 --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@ -104,7 +104,6 @@ struct vpe_control { struct list_head tc_list; /* Thread contexts */ }; -extern unsigned long physical_memsize; extern struct vpe_control vpecontrol; extern const struct file_operations vpe_fops; diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 2c2480be3f365a796554e37bf878bc25b8064e19..b424f5e844871070fafd485916f6065544ab4e35 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -11,6 +11,8 @@ * Copyright (C) 2000, 2001, 2002, 2007 Maciej W. Rozycki */ #include +#include +#include #include #include #include @@ -265,10 +267,6 @@ static unsigned long __init init_initrd(void) pr_err("initrd start must be page aligned\n"); goto disable; } - if (initrd_start < PAGE_OFFSET) { - pr_err("initrd start < PAGE_OFFSET\n"); - goto disable; - } /* * Sanitize initrd addresses. For example firmware @@ -281,6 +279,11 @@ static unsigned long __init init_initrd(void) initrd_end = (unsigned long)__va(end); initrd_start = (unsigned long)__va(__pa(initrd_start)); + if (initrd_start < PAGE_OFFSET) { + pr_err("initrd start < PAGE_OFFSET\n"); + goto disable; + } + ROOT_DEV = Root_RAM0; return PFN_UP(end); disable: @@ -1107,3 +1110,14 @@ static int __init setnocoherentio(char *str) } early_param("nocoherentio", setnocoherentio); #endif + +void __init arch_cpu_finalize_init(void) +{ + unsigned int cpu = smp_processor_id(); + + cpu_data[cpu].udelay_val = loops_per_jiffy; + check_bugs32(); + + if (IS_ENABLED(CONFIG_CPU_R4X00_BUGS64)) + check_bugs64(); +} diff --git a/arch/mips/kernel/vpe-mt.c b/arch/mips/kernel/vpe-mt.c index 9fd7cd48ea1d2f61265146af00999f2d57393547..496ed8f362f62fda5d4f7f042118688dec95b7f8 100644 --- a/arch/mips/kernel/vpe-mt.c +++ b/arch/mips/kernel/vpe-mt.c @@ -92,12 +92,11 @@ int vpe_run(struct vpe *v) write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H); /* - * The sde-kit passes 'memsize' to __start in $a3, so set something - * here... Or set $a3 to zero and define DFLT_STACK_SIZE and - * DFLT_HEAP_SIZE when you compile your program + * We don't pass the memsize here, so VPE programs need to be + * compiled with DFLT_STACK_SIZE and DFLT_HEAP_SIZE defined. */ + mttgpr(7, 0); mttgpr(6, v->ntcs); - mttgpr(7, physical_memsize); /* set up VPE1 */ /* diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index dceab67e481a8bf40354d57e8058e47429c3c5ac..02cf9b27b7859769868a9db4de95acabd1afdc4a 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -24,12 +24,6 @@ DEFINE_SPINLOCK(ebu_lock); EXPORT_SYMBOL_GPL(ebu_lock); -/* - * This is needed by the VPE loader code, just set it to 0 and assume - * that the firmware hardcodes this value to something useful. - */ -unsigned long physical_memsize = 0L; - /* * this struct is filled by the soc specific detection code and holds * information about the specific soc type, revision and name diff --git a/arch/nios2/boot/dts/10m50_devboard.dts b/arch/nios2/boot/dts/10m50_devboard.dts index 4bb4dc1b52e92c0cea2a1c33103e3418841381aa..d0831daa42c253713bce4d64316562d78d8c01ed 100644 --- a/arch/nios2/boot/dts/10m50_devboard.dts +++ b/arch/nios2/boot/dts/10m50_devboard.dts @@ -108,7 +108,7 @@ rx-fifo-depth = <8192>; tx-fifo-depth = <8192>; address-bits = <48>; - max-frame-size = <1518>; + max-frame-size = <1500>; local-mac-address = [00 00 00 00 00 00]; altr,has-supplementary-unicast; altr,enable-sup-addr = <1>; diff --git a/arch/nios2/boot/dts/3c120_devboard.dts b/arch/nios2/boot/dts/3c120_devboard.dts index 56f4b5df6d6506cb175ae2291c57bc4b0829d43c..b0b4e45c1a4c77767bb30feb5a60ad8e9f86c12a 100644 --- a/arch/nios2/boot/dts/3c120_devboard.dts +++ b/arch/nios2/boot/dts/3c120_devboard.dts @@ -118,7 +118,7 @@ interrupt-names = "rx_irq", "tx_irq"; rx-fifo-depth = <8192>; tx-fifo-depth = <8192>; - max-frame-size = <1518>; + max-frame-size = <1500>; local-mac-address = [ 00 00 00 00 00 00 ]; phy-mode = "rgmii-id"; phy-handle = <&phy0>; diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S index c2c3ce8a0f84e215f4b007b0ac58e19ae398c025..7b408d67f11e19dcaa87ced73811c844cb866b79 100644 --- a/arch/openrisc/kernel/entry.S +++ b/arch/openrisc/kernel/entry.S @@ -177,7 +177,6 @@ handler: ;\ l.sw PT_GPR28(r1),r28 ;\ l.sw PT_GPR29(r1),r29 ;\ /* r30 already save */ ;\ -/* l.sw PT_GPR30(r1),r30*/ ;\ l.sw PT_GPR31(r1),r31 ;\ TRACE_IRQS_OFF_ENTRY ;\ /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\ @@ -215,9 +214,8 @@ handler: ;\ l.sw PT_GPR27(r1),r27 ;\ l.sw PT_GPR28(r1),r28 ;\ l.sw PT_GPR29(r1),r29 ;\ - /* r31 already saved */ ;\ - l.sw PT_GPR30(r1),r30 ;\ -/* l.sw PT_GPR31(r1),r31 */ ;\ + /* r30 already saved */ ;\ + l.sw PT_GPR31(r1),r31 ;\ /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\ l.addi r30,r0,-1 ;\ l.sw PT_ORIG_GPR11(r1),r30 ;\ diff --git a/arch/parisc/include/asm/bugs.h b/arch/parisc/include/asm/bugs.h deleted file mode 100644 index 0a7f9db6bd1c7c0b93e5e12f0aa25a2dc7162b4e..0000000000000000000000000000000000000000 --- a/arch/parisc/include/asm/bugs.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/asm-parisc/bugs.h - * - * Copyright (C) 1999 Mike Shaver - */ - -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ - -#include - -static inline void check_bugs(void) -{ -// identify_cpu(&boot_cpu_data); -} diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h index 0c83644bfa5cbb3624b7d33b3fc70cf5d78f4a00..b4076ac51005e58b1509fc168d05e5504417cca9 100644 --- a/arch/parisc/include/asm/cacheflush.h +++ b/arch/parisc/include/asm/cacheflush.h @@ -57,6 +57,11 @@ extern void flush_dcache_page(struct page *page); #define flush_dcache_mmap_lock(mapping) xa_lock_irq(&mapping->i_pages) #define flush_dcache_mmap_unlock(mapping) xa_unlock_irq(&mapping->i_pages) +#define flush_dcache_mmap_lock_irqsave(mapping, flags) \ + xa_lock_irqsave(&mapping->i_pages, flags) +#define flush_dcache_mmap_unlock_irqrestore(mapping, flags) \ + xa_unlock_irqrestore(&mapping->i_pages, flags) + #define flush_icache_page(vma,page) do { \ flush_kernel_dcache_page(page); \ diff --git a/arch/parisc/include/asm/ldcw.h b/arch/parisc/include/asm/ldcw.h index 3eb4bfc1fb365478f11c9c87bfb3b3124fab567a..5ed52819e956a415527750a8f84c07805f10d55d 100644 --- a/arch/parisc/include/asm/ldcw.h +++ b/arch/parisc/include/asm/ldcw.h @@ -2,14 +2,28 @@ #ifndef __PARISC_LDCW_H #define __PARISC_LDCW_H -#ifndef CONFIG_PA20 /* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data, and GCC only guarantees 8-byte alignment for stack locals, we can't be assured of 16-byte alignment for atomic lock data even if we specify "__attribute ((aligned(16)))" in the type declaration. So, we use a struct containing an array of four ints for the atomic lock type and dynamically select the 16-byte aligned int from the array - for the semaphore. */ + for the semaphore. */ + +/* From: "Jim Hull" + I've attached a summary of the change, but basically, for PA 2.0, as + long as the ",CO" (coherent operation) completer is implemented, then the + 16-byte alignment requirement for ldcw and ldcd is relaxed, and instead + they only require "natural" alignment (4-byte for ldcw, 8-byte for + ldcd). + + Although the cache control hint is accepted by all PA 2.0 processors, + it is only implemented on PA8800/PA8900 CPUs. Prior PA8X00 CPUs still + require 16-byte alignment. If the address is unaligned, the operation + of the instruction is undefined. The ldcw instruction does not generate + unaligned data reference traps so misaligned accesses are not detected. + This hid the problem for years. So, restore the 16-byte alignment dropped + by Kyle McMartin in "Remove __ldcw_align for PA-RISC 2.0 processors". */ #define __PA_LDCW_ALIGNMENT 16 #define __PA_LDCW_ALIGN_ORDER 4 @@ -19,22 +33,12 @@ & ~(__PA_LDCW_ALIGNMENT - 1); \ (volatile unsigned int *) __ret; \ }) -#define __LDCW "ldcw" -#else /*CONFIG_PA20*/ -/* From: "Jim Hull" - I've attached a summary of the change, but basically, for PA 2.0, as - long as the ",CO" (coherent operation) completer is specified, then the - 16-byte alignment requirement for ldcw and ldcd is relaxed, and instead - they only require "natural" alignment (4-byte for ldcw, 8-byte for - ldcd). */ - -#define __PA_LDCW_ALIGNMENT 4 -#define __PA_LDCW_ALIGN_ORDER 2 -#define __ldcw_align(a) (&(a)->slock) +#ifdef CONFIG_PA20 #define __LDCW "ldcw,co" - -#endif /*!CONFIG_PA20*/ +#else +#define __LDCW "ldcw" +#endif /* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. We don't explicitly expose that "*a" may be written as reload diff --git a/arch/parisc/include/asm/led.h b/arch/parisc/include/asm/led.h index 6de13d08a3886b4dbef50cb5a9e5367715fc816a..b70b9094fb7cd2a314dabef5597a8d31fdf939b2 100644 --- a/arch/parisc/include/asm/led.h +++ b/arch/parisc/include/asm/led.h @@ -11,8 +11,8 @@ #define LED1 0x02 #define LED0 0x01 /* bottom (or furthest left) LED */ -#define LED_LAN_TX LED0 /* for LAN transmit activity */ -#define LED_LAN_RCV LED1 /* for LAN receive activity */ +#define LED_LAN_RCV LED0 /* for LAN receive activity */ +#define LED_LAN_TX LED1 /* for LAN transmit activity */ #define LED_DISK_IO LED2 /* for disk activity */ #define LED_HEARTBEAT LED3 /* heartbeat */ diff --git a/arch/parisc/include/asm/processor.h b/arch/parisc/include/asm/processor.h index 2bd5e695bdadd9d12ebf903a18ed56637e58ecb6..0e6cac0ece5cd272b3c875816c1440cbbe27a248 100644 --- a/arch/parisc/include/asm/processor.h +++ b/arch/parisc/include/asm/processor.h @@ -108,7 +108,6 @@ struct cpuinfo_parisc { unsigned long cpu_loc; /* CPU location from PAT firmware */ unsigned int state; struct parisc_device *dev; - unsigned long loops_per_jiffy; }; extern struct system_cpuinfo_parisc boot_cpu_data; diff --git a/arch/parisc/include/asm/ropes.h b/arch/parisc/include/asm/ropes.h index 8e51c775c80a6f9a8cfd55b12575956082bc9470..62399c7ea94a1cf58906607139fcb9c9cd196fd4 100644 --- a/arch/parisc/include/asm/ropes.h +++ b/arch/parisc/include/asm/ropes.h @@ -86,6 +86,9 @@ struct sba_device { struct ioc ioc[MAX_IOC]; }; +/* list of SBA's in system, see drivers/parisc/sba_iommu.c */ +extern struct sba_device *sba_list; + #define ASTRO_RUNWAY_PORT 0x582 #define IKE_MERCED_PORT 0x803 #define REO_MERCED_PORT 0x804 diff --git a/arch/parisc/include/asm/spinlock_types.h b/arch/parisc/include/asm/spinlock_types.h index 42979c5704dc64a455b35fdd80a22b2c346abfa9..82d2384c3f2227a9e85ddc442d8eeccc0ca3801f 100644 --- a/arch/parisc/include/asm/spinlock_types.h +++ b/arch/parisc/include/asm/spinlock_types.h @@ -3,13 +3,8 @@ #define __ASM_SPINLOCK_TYPES_H typedef struct { -#ifdef CONFIG_PA20 - volatile unsigned int slock; -# define __ARCH_SPIN_LOCK_UNLOCKED { 1 } -#else volatile unsigned int lock[4]; # define __ARCH_SPIN_LOCK_UNLOCKED { { 1, 1, 1, 1 } } -#endif } arch_spinlock_t; typedef struct { diff --git a/arch/parisc/include/uapi/asm/pdc.h b/arch/parisc/include/uapi/asm/pdc.h index 593eeb573138709aafa855343730a1f7e393a874..786c65954ec4d3d5c3759dc25f84bc0e25c89062 100644 --- a/arch/parisc/include/uapi/asm/pdc.h +++ b/arch/parisc/include/uapi/asm/pdc.h @@ -443,6 +443,7 @@ struct pdc_model { /* for PDC_MODEL */ unsigned long arch_rev; unsigned long pot_key; unsigned long curr_key; + unsigned long width; /* default of PSW_W bit (1=enabled) */ }; struct pdc_cache_cf { /* for PDC_CACHE (I/D-caches) */ diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c index bddd2acebdcc85dc4dd86765eaa43352c67143f4..d03a5df7589f1329bd07752d292788aceb4603d8 100644 --- a/arch/parisc/kernel/cache.c +++ b/arch/parisc/kernel/cache.c @@ -309,6 +309,7 @@ void flush_dcache_page(struct page *page) struct vm_area_struct *mpnt; unsigned long offset; unsigned long addr, old_addr = 0; + unsigned long flags; pgoff_t pgoff; if (mapping && !mapping_mapped(mapping)) { @@ -328,7 +329,7 @@ void flush_dcache_page(struct page *page) * declared as MAP_PRIVATE or MAP_SHARED), so we only need * to flush one address here for them all to become coherent */ - flush_dcache_mmap_lock(mapping); + flush_dcache_mmap_lock_irqsave(mapping, flags); vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) { offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; addr = mpnt->vm_start + offset; @@ -351,7 +352,7 @@ void flush_dcache_page(struct page *page) old_addr = addr; } } - flush_dcache_mmap_unlock(mapping); + flush_dcache_mmap_unlock_irqrestore(mapping, flags); } EXPORT_SYMBOL(flush_dcache_page); diff --git a/arch/parisc/kernel/drivers.c b/arch/parisc/kernel/drivers.c index 01a2ed59d2f2ac35025af0903e8fb43606a3f671..94037c8512f782ab9604202970fb5db1f01e808d 100644 --- a/arch/parisc/kernel/drivers.c +++ b/arch/parisc/kernel/drivers.c @@ -903,9 +903,9 @@ static __init void qemu_header(void) pr_info("#define PARISC_MODEL \"%s\"\n\n", boot_cpu_data.pdc.sys_model_name); + #define p ((unsigned long *)&boot_cpu_data.pdc.model) pr_info("#define PARISC_PDC_MODEL 0x%lx, 0x%lx, 0x%lx, " "0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx\n\n", - #define p ((unsigned long *)&boot_cpu_data.pdc.model) p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]); #undef p diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index e8b503cd54f57ada2fd0438eb555c14594b39e58..a0c251c4f3026e5499965ee51ffec043ec2e1376 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -522,13 +522,13 @@ * to a CPU TLB 4k PFN (4k => 12 bits to shift) */ #define PAGE_ADD_SHIFT (PAGE_SHIFT-12) #define PAGE_ADD_HUGE_SHIFT (REAL_HPAGE_SHIFT-12) + #define PFN_START_BIT (63-ASM_PFN_PTE_SHIFT+(63-58)-PAGE_ADD_SHIFT) /* Drop prot bits and convert to page addr for iitlbt and idtlbt */ .macro convert_for_tlb_insert20 pte,tmp #ifdef CONFIG_HUGETLB_PAGE copy \pte,\tmp - extrd,u \tmp,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\ - 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte + extrd,u \tmp,PFN_START_BIT,PFN_START_BIT+1,\pte depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\ (63-58)+PAGE_ADD_SHIFT,\pte @@ -536,8 +536,7 @@ depdi _HUGE_PAGE_SIZE_ENCODING_DEFAULT,63,\ (63-58)+PAGE_ADD_HUGE_SHIFT,\pte #else /* Huge pages disabled */ - extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\ - 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte + extrd,u \pte,PFN_START_BIT,PFN_START_BIT+1,\pte depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\ (63-58)+PAGE_ADD_SHIFT,\pte #endif diff --git a/arch/parisc/kernel/head.S b/arch/parisc/kernel/head.S index 92bc2fa7e6929b946d0909eb1e79e112a4e1dd0e..efa078b3aa45fbf765d11f2c61851dbb080dcfe0 100644 --- a/arch/parisc/kernel/head.S +++ b/arch/parisc/kernel/head.S @@ -69,9 +69,8 @@ $bss_loop: stw,ma %arg2,4(%r1) stw,ma %arg3,4(%r1) -#if !defined(CONFIG_64BIT) && defined(CONFIG_PA20) - /* This 32-bit kernel was compiled for PA2.0 CPUs. Check current CPU - * and halt kernel if we detect a PA1.x CPU. */ +#if defined(CONFIG_PA20) + /* check for 64-bit capable CPU as required by current kernel */ ldi 32,%r10 mtctl %r10,%cr11 .level 2.0 diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c index c152c30c2d06d0a5670f334f7542279ffe0419e8..11c1505775f87416026a50fdb7002c18710d0555 100644 --- a/arch/parisc/kernel/irq.c +++ b/arch/parisc/kernel/irq.c @@ -392,7 +392,7 @@ union irq_stack_union { volatile unsigned int lock[1]; }; -DEFINE_PER_CPU(union irq_stack_union, irq_stack_union) = { +static DEFINE_PER_CPU(union irq_stack_union, irq_stack_union) = { .slock = { 1,1,1,1 }, }; #endif diff --git a/arch/parisc/kernel/pci-dma.c b/arch/parisc/kernel/pci-dma.c index 04c48f1ef3fbddcbc63ba8d52cbbe9683441cc5d..20084336704fc4a2f10efd59565f1a4323d7563d 100644 --- a/arch/parisc/kernel/pci-dma.c +++ b/arch/parisc/kernel/pci-dma.c @@ -464,13 +464,29 @@ void arch_dma_free(struct device *dev, size_t size, void *vaddr, void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr, size_t size, enum dma_data_direction dir) { + /* + * fdc: The data cache line is written back to memory, if and only if + * it is dirty, and then invalidated from the data cache. + */ flush_kernel_dcache_range((unsigned long)phys_to_virt(paddr), size); } void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr, size_t size, enum dma_data_direction dir) { - flush_kernel_dcache_range((unsigned long)phys_to_virt(paddr), size); + unsigned long addr = (unsigned long) phys_to_virt(paddr); + + switch (dir) { + case DMA_TO_DEVICE: + case DMA_BIDIRECTIONAL: + flush_kernel_dcache_range(addr, size); + return; + case DMA_FROM_DEVICE: + purge_kernel_dcache_range_asm(addr, addr + size); + return; + default: + BUG(); + } } void arch_dma_cache_sync(struct device *dev, void *vaddr, size_t size, diff --git a/arch/parisc/kernel/process.c b/arch/parisc/kernel/process.c index 97c206734e24f372175c8592703033084d81d0ae..80592603caaa73def983f60c761d4f9c48a929b8 100644 --- a/arch/parisc/kernel/process.c +++ b/arch/parisc/kernel/process.c @@ -138,13 +138,18 @@ void machine_power_off(void) /* It seems we have no way to power the system off via * software. The user has to press the button himself. */ - printk(KERN_EMERG "System shut down completed.\n" - "Please power this system off now."); + printk("Power off or press RETURN to reboot.\n"); /* prevent soft lockup/stalled CPU messages for endless loop. */ rcu_sysrq_start(); lockup_detector_soft_poweroff(); - for (;;); + while (1) { + /* reboot if user presses RETURN key */ + if (pdc_iodc_getc() == 13) { + printk("Rebooting...\n"); + machine_restart(NULL); + } + } } void (*pm_power_off)(void); diff --git a/arch/parisc/kernel/processor.c b/arch/parisc/kernel/processor.c index 0b0194150b6829318fc3b3dec04c10875e93d0ca..be3618b2c67b36cdf43e6b1b1e4459875b92068b 100644 --- a/arch/parisc/kernel/processor.c +++ b/arch/parisc/kernel/processor.c @@ -177,7 +177,6 @@ static int __init processor_probe(struct parisc_device *dev) if (cpuid) memset(p, 0, sizeof(struct cpuinfo_parisc)); - p->loops_per_jiffy = loops_per_jiffy; p->dev = dev; /* Save IODC data in case we need it */ p->hpa = dev->hpa.start; /* save CPU hpa */ p->cpuid = cpuid; /* save CPU id */ @@ -377,10 +376,18 @@ int show_cpuinfo (struct seq_file *m, void *v) { unsigned long cpu; + char cpu_name[60], *p; + + /* strip PA path from CPU name to not confuse lscpu */ + strlcpy(cpu_name, per_cpu(cpu_data, 0).dev->name, sizeof(cpu_name)); + p = strrchr(cpu_name, '['); + if (p) + *(--p) = 0; for_each_online_cpu(cpu) { - const struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); #ifdef CONFIG_SMP + const struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); + if (0 == cpuinfo->hpa) continue; #endif @@ -425,8 +432,7 @@ show_cpuinfo (struct seq_file *m, void *v) seq_printf(m, "model\t\t: %s - %s\n", boot_cpu_data.pdc.sys_model_name, - cpuinfo->dev ? - cpuinfo->dev->name : "Unknown"); + cpu_name); seq_printf(m, "hversion\t: 0x%08x\n" "sversion\t: 0x%08x\n", @@ -437,8 +443,8 @@ show_cpuinfo (struct seq_file *m, void *v) show_cache_info(m); seq_printf(m, "bogomips\t: %lu.%02lu\n", - cpuinfo->loops_per_jiffy / (500000 / HZ), - (cpuinfo->loops_per_jiffy / (5000 / HZ)) % 100); + loops_per_jiffy / (500000 / HZ), + loops_per_jiffy / (5000 / HZ) % 100); seq_printf(m, "software id\t: %ld\n\n", boot_cpu_data.pdc.model.sw_id); diff --git a/arch/parisc/kernel/real2.S b/arch/parisc/kernel/real2.S index 2b16d8d6598f1d6015795a4455a24a4c039d0108..c37010a1358655100fb53164490833ffca5fbcc2 100644 --- a/arch/parisc/kernel/real2.S +++ b/arch/parisc/kernel/real2.S @@ -248,9 +248,6 @@ ENTRY_CFI(real64_call_asm) /* save fn */ copy %arg2, %r31 - /* set up the new ap */ - ldo 64(%arg1), %r29 - /* load up the arg registers from the saved arg area */ /* 32-bit calling convention passes first 4 args in registers */ ldd 0*REG_SZ(%arg1), %arg0 /* note overwriting arg0 */ @@ -262,7 +259,9 @@ ENTRY_CFI(real64_call_asm) ldd 7*REG_SZ(%arg1), %r19 ldd 1*REG_SZ(%arg1), %arg1 /* do this one last! */ + /* set up real-mode stack and real-mode ap */ tophys_r1 %sp + ldo -16(%sp), %r29 /* Reference param save area */ b,l rfi_virt2real,%r2 nop diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index f0e09d5f0bedd2374340b022256d9284f5edc78c..3be56d857d57f59a867463cd0adb51b7cfef56a0 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -181,6 +181,7 @@ config PPC select HAVE_ARCH_SECCOMP_FILTER select HAVE_ARCH_TRACEHOOK select HAVE_CBPF_JIT if !PPC64 + select HAVE_STACKPROTECTOR if $(cc-option,-mstack-protector-guard=tls) && PPC32 select HAVE_CONTEXT_TRACKING if PPC64 select HAVE_DEBUG_KMEMLEAK select HAVE_DEBUG_STACKOVERFLOW diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug index ffe0cf0f0bea279268ec98662d633e5180c08237..1f54bb93b5cc79f5f6e386c70181e4053bddf148 100644 --- a/arch/powerpc/Kconfig.debug +++ b/arch/powerpc/Kconfig.debug @@ -232,7 +232,7 @@ config PPC_EARLY_DEBUG_40x config PPC_EARLY_DEBUG_CPM bool "Early serial debugging for Freescale CPM-based serial ports" - depends on SERIAL_CPM + depends on SERIAL_CPM=y help Select this to enable early debugging for Freescale chips using a CPM-based serial port. This assumes that the bootwrapper @@ -368,10 +368,6 @@ config PPC_PTDUMP If you are unsure, say N. -config PPC_HTDUMP - def_bool y - depends on PPC_PTDUMP && PPC_BOOK3S_64 - config PPC_FAST_ENDIAN_SWITCH bool "Deprecated fast endian-switch syscall" depends on DEBUG_KERNEL && PPC_BOOK3S_64 diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 5987ae0d8fbbb5a7bb5cb2eb75981ef178992f7b..daddada1a390238d40a9836ff28013ff81fc5d0c 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -30,11 +30,10 @@ endif endif endif -ifeq ($(CROSS_COMPILE),) -KBUILD_DEFCONFIG := $(shell uname -m)_defconfig -else -KBUILD_DEFCONFIG := ppc64_defconfig -endif +# If we're on a ppc/ppc64/ppc64le machine use that defconfig, otherwise just use +# ppc64_defconfig because we have nothing better to go on. +uname := $(shell uname -m) +KBUILD_DEFCONFIG := $(if $(filter ppc%,$(uname)),$(uname),ppc64)_defconfig ifdef CONFIG_PPC64 new_nm := $(shell if $(NM) --help 2>&1 | grep -- '--synthetic' > /dev/null; then echo y; else echo n; fi) @@ -109,11 +108,14 @@ aflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -mlittle-endian ifeq ($(HAS_BIARCH),y) KBUILD_CFLAGS += -m$(BITS) -KBUILD_AFLAGS += -m$(BITS) -Wl,-a$(BITS) +KBUILD_AFLAGS += -m$(BITS) KBUILD_LDFLAGS += -m elf$(BITS)$(LDEMULATION) KBUILD_ARFLAGS += --target=elf$(BITS)-$(GNUTARGET) endif +cflags-$(CONFIG_STACKPROTECTOR) += -mstack-protector-guard=tls +cflags-$(CONFIG_STACKPROTECTOR) += -mstack-protector-guard-reg=r2 + LDFLAGS_vmlinux-y := -Bstatic LDFLAGS_vmlinux-$(CONFIG_RELOCATABLE) := -pie LDFLAGS_vmlinux := $(LDFLAGS_vmlinux-y) @@ -420,9 +422,12 @@ archclean: archprepare: checkbin -# Use the file '.tmp_gas_check' for binutils tests, as gas won't output -# to stdout and these checks are run even on install targets. -TOUT := .tmp_gas_check +ifdef CONFIG_STACKPROTECTOR +prepare: stack_protector_prepare + +stack_protector_prepare: prepare0 + $(eval KBUILD_CFLAGS += -mstack-protector-guard-offset=$(shell awk '{if ($$2 == "TASK_CANARY") print $$3;}' include/generated/asm-offsets.h)) +endif # Check toolchain versions: # - gcc-4.6 is the minimum kernel-wide version so nothing required. @@ -434,7 +439,11 @@ checkbin: echo -n '*** Please use a different binutils version.' ; \ false ; \ fi - - -CLEAN_FILES += $(TOUT) - + @if test "x${CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT}" = "xy" -a \ + "x${CONFIG_LD_IS_BFD}" = "xy" -a \ + "${CONFIG_LD_VERSION}" = "23700" ; then \ + echo -n '*** binutils 2.37 drops unused section symbols, which recordmcount ' ; \ + echo 'is unable to handle.' ; \ + echo '*** Please use a different binutils version.' ; \ + false ; \ + fi diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig index e30af76f47537ee2572bca18b616b1dfd7644989..673935824928a82bb28916a53cc415483ac8b0e2 100644 --- a/arch/powerpc/configs/ppc6xx_defconfig +++ b/arch/powerpc/configs/ppc6xx_defconfig @@ -253,8 +253,6 @@ CONFIG_ATM_LANE=m CONFIG_ATM_BR2684=m CONFIG_BRIDGE=m CONFIG_VLAN_8021Q=m -CONFIG_DECNET=m -CONFIG_DECNET_ROUTER=y CONFIG_IPX=m CONFIG_ATALK=m CONFIG_DEV_APPLETALK=m diff --git a/arch/powerpc/include/asm/book3s/32/mmu-hash.h b/arch/powerpc/include/asm/book3s/32/mmu-hash.h index e38c91388c40f9cfd160641a20be4581710b115c..958b18cecc96ae02cd9a8a7e7a8c38c278843495 100644 --- a/arch/powerpc/include/asm/book3s/32/mmu-hash.h +++ b/arch/powerpc/include/asm/book3s/32/mmu-hash.h @@ -34,14 +34,20 @@ #define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \ ((x & 0x0000000e00000000ULL) >> 24) | \ ((x & 0x0000000100000000ULL) >> 30))) +#define PHYS_BAT_ADDR(x) (((u64)(x) & 0x00000000fffe0000ULL) | \ + (((u64)(x) << 24) & 0x0000000e00000000ULL) | \ + (((u64)(x) << 30) & 0x0000000100000000ULL)) #else #define BAT_PHYS_ADDR(x) (x) +#define PHYS_BAT_ADDR(x) ((x) & 0xfffe0000) #endif struct ppc_bat { u32 batu; u32 batl; }; + +typedef struct page *pgtable_t; #endif /* !__ASSEMBLY__ */ /* diff --git a/arch/powerpc/include/asm/book3s/64/mmu.h b/arch/powerpc/include/asm/book3s/64/mmu.h index 9c8c669a6b6a3e0dd52ad6f4e2de2c62a8965720..488e7ed07e967c9bede5f0559a24c8129e1a49ae 100644 --- a/arch/powerpc/include/asm/book3s/64/mmu.h +++ b/arch/powerpc/include/asm/book3s/64/mmu.h @@ -2,6 +2,8 @@ #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_ #define _ASM_POWERPC_BOOK3S_64_MMU_H_ +#include + #ifndef __ASSEMBLY__ /* * Page size definition @@ -24,6 +26,13 @@ struct mmu_psize_def { }; extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; +/* + * For BOOK3s 64 with 4k and 64K linux page size + * we want to use pointers, because the page table + * actually store pfn + */ +typedef pte_t *pgtable_t; + #endif /* __ASSEMBLY__ */ /* 64-bit classic hash table MMU */ diff --git a/arch/powerpc/include/asm/bugs.h b/arch/powerpc/include/asm/bugs.h deleted file mode 100644 index 42fdb73e3068557061afa3064d0fa5e049e7615f..0000000000000000000000000000000000000000 --- a/arch/powerpc/include/asm/bugs.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _ASM_POWERPC_BUGS_H -#define _ASM_POWERPC_BUGS_H - -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/* - * This file is included by 'init/main.c' to check for - * architecture-dependent bugs. - */ - -static inline void check_bugs(void) { } - -#endif /* _ASM_POWERPC_BUGS_H */ diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 13ea441ac5319e27e1466362fde8f700d0b8f231..2b396de45e9ec281856b45662d546f6f8605c8b2 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -326,18 +326,8 @@ static inline void mmu_early_init_devtree(void) { } #if defined(CONFIG_PPC_STD_MMU_32) /* 32-bit classic hash table MMU */ #include -#elif defined(CONFIG_40x) -/* 40x-style software loaded TLB */ -# include -#elif defined(CONFIG_44x) -/* 44x-style software loaded TLB */ -# include -#elif defined(CONFIG_PPC_BOOK3E_MMU) -/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ -# include -#elif defined (CONFIG_PPC_8xx) -/* Motorola/Freescale 8xx software loaded TLB */ -# include +#elif defined(CONFIG_PPC_MMU_NOHASH) +#include #endif #endif /* __KERNEL__ */ diff --git a/arch/powerpc/include/asm/mmu-40x.h b/arch/powerpc/include/asm/nohash/32/mmu-40x.h similarity index 100% rename from arch/powerpc/include/asm/mmu-40x.h rename to arch/powerpc/include/asm/nohash/32/mmu-40x.h diff --git a/arch/powerpc/include/asm/mmu-44x.h b/arch/powerpc/include/asm/nohash/32/mmu-44x.h similarity index 100% rename from arch/powerpc/include/asm/mmu-44x.h rename to arch/powerpc/include/asm/nohash/32/mmu-44x.h diff --git a/arch/powerpc/include/asm/mmu-8xx.h b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h similarity index 100% rename from arch/powerpc/include/asm/mmu-8xx.h rename to arch/powerpc/include/asm/nohash/32/mmu-8xx.h diff --git a/arch/powerpc/include/asm/nohash/32/mmu.h b/arch/powerpc/include/asm/nohash/32/mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..f61f933a4cd8cb4ccc9bb5dce7056f705bac2a06 --- /dev/null +++ b/arch/powerpc/include/asm/nohash/32/mmu.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_POWERPC_NOHASH_32_MMU_H_ +#define _ASM_POWERPC_NOHASH_32_MMU_H_ + +#if defined(CONFIG_40x) +/* 40x-style software loaded TLB */ +#include +#elif defined(CONFIG_44x) +/* 44x-style software loaded TLB */ +#include +#elif defined(CONFIG_PPC_BOOK3E_MMU) +/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ +#include +#elif defined (CONFIG_PPC_8xx) +/* Motorola/Freescale 8xx software loaded TLB */ +#include +#endif + +#ifndef __ASSEMBLY__ +typedef struct page *pgtable_t; +#endif + +#endif /* _ASM_POWERPC_NOHASH_32_MMU_H_ */ diff --git a/arch/powerpc/include/asm/nohash/64/mmu.h b/arch/powerpc/include/asm/nohash/64/mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..e6585480dfc4001002b129a6f5b558bc432c7ad5 --- /dev/null +++ b/arch/powerpc/include/asm/nohash/64/mmu.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_POWERPC_NOHASH_64_MMU_H_ +#define _ASM_POWERPC_NOHASH_64_MMU_H_ + +/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ +#include + +#ifndef __ASSEMBLY__ +typedef struct page *pgtable_t; +#endif + +#endif /* _ASM_POWERPC_NOHASH_64_MMU_H_ */ diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h index 7cd6809f4d332321e5f7eb806693e94fd5915b48..30fcffc02caad75018adab9e5c359c323ba32be3 100644 --- a/arch/powerpc/include/asm/nohash/64/pgtable.h +++ b/arch/powerpc/include/asm/nohash/64/pgtable.h @@ -215,7 +215,7 @@ static inline int __ptep_test_and_clear_young(struct mm_struct *mm, { unsigned long old; - if (pte_young(*ptep)) + if (!pte_young(*ptep)) return 0; old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); return (old & _PAGE_ACCESSED) != 0; diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/nohash/mmu-book3e.h similarity index 100% rename from arch/powerpc/include/asm/mmu-book3e.h rename to arch/powerpc/include/asm/nohash/mmu-book3e.h diff --git a/arch/powerpc/include/asm/nohash/mmu.h b/arch/powerpc/include/asm/nohash/mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..a037cb1efb57ee7f07fef81934ceee2b3178eefb --- /dev/null +++ b/arch/powerpc/include/asm/nohash/mmu.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_POWERPC_NOHASH_MMU_H_ +#define _ASM_POWERPC_NOHASH_MMU_H_ + +#ifdef CONFIG_PPC64 +#include +#else +#include +#endif + +#endif /* _ASM_POWERPC_NOHASH_MMU_H_ */ diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h index f6a1265face297f6b2cfe9d563dc04fbad93dcc3..ddfb4b965e5bd843d06a9a58648ed57e12d69e20 100644 --- a/arch/powerpc/include/asm/page.h +++ b/arch/powerpc/include/asm/page.h @@ -335,20 +335,6 @@ void arch_free_page(struct page *page, int order); #endif struct vm_area_struct; -#ifdef CONFIG_PPC_BOOK3S_64 -/* - * For BOOK3s 64 with 4k and 64K linux page size - * we want to use pointers, because the page table - * actually store pfn - */ -typedef pte_t *pgtable_t; -#else -#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC64) -typedef pte_t *pgtable_t; -#else -typedef struct page *pgtable_t; -#endif -#endif #include #endif /* __ASSEMBLY__ */ diff --git a/arch/powerpc/include/asm/stackprotector.h b/arch/powerpc/include/asm/stackprotector.h new file mode 100644 index 0000000000000000000000000000000000000000..d05d969c98c213041542f23e4953abf2ed984b9c --- /dev/null +++ b/arch/powerpc/include/asm/stackprotector.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * GCC stack protector support. + * + */ + +#ifndef _ASM_STACKPROTECTOR_H +#define _ASM_STACKPROTECTOR_H + +#include +#include +#include +#include + +/* + * Initialize the stackprotector canary value. + * + * NOTE: this must only be called from functions that never return, + * and it must always be inlined. + */ +static __always_inline void boot_init_stack_canary(void) +{ + unsigned long canary; + + /* Try to get a semi random initial value. */ + canary = get_random_canary(); + canary ^= mftb(); + canary ^= LINUX_VERSION_CODE; + canary &= CANARY_MASK; + + current->stack_canary = canary; +} + +#endif /* _ASM_STACKPROTECTOR_H */ diff --git a/arch/powerpc/include/asm/word-at-a-time.h b/arch/powerpc/include/asm/word-at-a-time.h index f3f4710d4ff522d562cc62085d814944d8b17639..99129b0cd8b8a4c33b857af24267d4231e3a4575 100644 --- a/arch/powerpc/include/asm/word-at-a-time.h +++ b/arch/powerpc/include/asm/word-at-a-time.h @@ -34,7 +34,7 @@ static inline long find_zero(unsigned long mask) return leading_zero_bits >> 3; } -static inline bool has_zero(unsigned long val, unsigned long *data, const struct word_at_a_time *c) +static inline unsigned long has_zero(unsigned long val, unsigned long *data, const struct word_at_a_time *c) { unsigned long rhs = val | c->low_bits; *data = rhs; diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index bf19c5514d6c2660a400e29278017cae941b92dc..cccea292af683b9e100fc9f9584b9db9ce23458e 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -21,6 +21,8 @@ CFLAGS_prom_init.o += $(DISABLE_LATENT_ENTROPY_PLUGIN) CFLAGS_btext.o += $(DISABLE_LATENT_ENTROPY_PLUGIN) CFLAGS_prom.o += $(DISABLE_LATENT_ENTROPY_PLUGIN) +CFLAGS_prom_init.o += $(call cc-option, -fno-stack-protector) + ifdef CONFIG_FUNCTION_TRACER # Do not trace early boot code CFLAGS_REMOVE_cputable.o = $(CC_FLAGS_FTRACE) diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index 50400f213bbf2a57ea60ba3330cf3beee5fd9da4..c2288c73d56d1a5177ce93a91cee99421b74b7e1 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -79,6 +79,9 @@ int main(void) { OFFSET(THREAD, task_struct, thread); OFFSET(MM, task_struct, mm); +#ifdef CONFIG_STACKPROTECTOR + OFFSET(TASK_CANARY, task_struct, stack_canary); +#endif OFFSET(MMCONTEXTID, mm_struct, context.id); #ifdef CONFIG_PPC64 DEFINE(SIGSEGV, SIGSEGV); diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 8d142e5d84cd037babf06bf2b90823d024493a41..5fbc890d109434acdb003f30524d101691710135 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index 61ca27929355a0eea397d22bff1792dc1d5f0c59..53a379da17e97aa4d5f8a1ac110adf0cc30caa75 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -987,7 +987,7 @@ start_here: */ lis r5, abatron_pteptrs@h ori r5, r5, abatron_pteptrs@l - stw r5, 0xf0(r0) /* This much match your Abatron config */ + stw r5, 0xf0(0) /* This much match your Abatron config */ lis r6, swapper_pg_dir@h ori r6, r6, swapper_pg_dir@l tophys(r5, r5) diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c index c3d2d5cd7c10cea3c5765a21c769fc8835ae1aa1..af1a2bf758c5c14aa2ad6162657593a8ab67ac5e 100644 --- a/arch/powerpc/kernel/iommu.c +++ b/arch/powerpc/kernel/iommu.c @@ -145,17 +145,28 @@ static int fail_iommu_bus_notify(struct notifier_block *nb, return 0; } -static struct notifier_block fail_iommu_bus_notifier = { +/* + * PCI and VIO buses need separate notifier_block structs, since they're linked + * list nodes. Sharing a notifier_block would mean that any notifiers later + * registered for PCI buses would also get called by VIO buses and vice versa. + */ +static struct notifier_block fail_iommu_pci_bus_notifier = { .notifier_call = fail_iommu_bus_notify }; +#ifdef CONFIG_IBMVIO +static struct notifier_block fail_iommu_vio_bus_notifier = { + .notifier_call = fail_iommu_bus_notify +}; +#endif + static int __init fail_iommu_setup(void) { #ifdef CONFIG_PCI - bus_register_notifier(&pci_bus_type, &fail_iommu_bus_notifier); + bus_register_notifier(&pci_bus_type, &fail_iommu_pci_bus_notifier); #endif #ifdef CONFIG_IBMVIO - bus_register_notifier(&vio_bus_type, &fail_iommu_bus_notifier); + bus_register_notifier(&vio_bus_type, &fail_iommu_vio_bus_notifier); #endif return 0; diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c index a3f08a380c992b745a2922640495d1bf0c6d72fb..2646dd54eb0bb73be2857b5b40454f1f4e248663 100644 --- a/arch/powerpc/kernel/rtas.c +++ b/arch/powerpc/kernel/rtas.c @@ -54,10 +54,10 @@ struct rtas_t rtas = { EXPORT_SYMBOL(rtas); DEFINE_SPINLOCK(rtas_data_buf_lock); -EXPORT_SYMBOL(rtas_data_buf_lock); +EXPORT_SYMBOL_GPL(rtas_data_buf_lock); -char rtas_data_buf[RTAS_DATA_BUF_SIZE] __cacheline_aligned; -EXPORT_SYMBOL(rtas_data_buf); +char rtas_data_buf[RTAS_DATA_BUF_SIZE] __aligned(SZ_4K); +EXPORT_SYMBOL_GPL(rtas_data_buf); unsigned long rtas_rmo_buf; @@ -66,7 +66,7 @@ unsigned long rtas_rmo_buf; * This is done like this so rtas_flash can be a module. */ void (*rtas_flash_term_hook)(int); -EXPORT_SYMBOL(rtas_flash_term_hook); +EXPORT_SYMBOL_GPL(rtas_flash_term_hook); /* RTAS use home made raw locking instead of spin_lock_irqsave * because those can be called from within really nasty contexts @@ -314,7 +314,7 @@ void rtas_progress(char *s, unsigned short hex) spin_unlock(&progress_lock); } -EXPORT_SYMBOL(rtas_progress); /* needed by rtas_flash module */ +EXPORT_SYMBOL_GPL(rtas_progress); /* needed by rtas_flash module */ int rtas_token(const char *service) { @@ -324,7 +324,7 @@ int rtas_token(const char *service) tokp = of_get_property(rtas.dev, service, NULL); return tokp ? be32_to_cpu(*tokp) : RTAS_UNKNOWN_SERVICE; } -EXPORT_SYMBOL(rtas_token); +EXPORT_SYMBOL_GPL(rtas_token); int rtas_service_present(const char *service) { @@ -401,7 +401,7 @@ static char *__fetch_rtas_last_error(char *altbuf) buf = kmalloc(RTAS_ERROR_LOG_MAX, GFP_ATOMIC); } if (buf) - memcpy(buf, rtas_err_buf, RTAS_ERROR_LOG_MAX); + memmove(buf, rtas_err_buf, RTAS_ERROR_LOG_MAX); } return buf; @@ -484,7 +484,7 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...) } return ret; } -EXPORT_SYMBOL(rtas_call); +EXPORT_SYMBOL_GPL(rtas_call); /* For RTAS_BUSY (-2), delay for 1 millisecond. For an extended busy status * code of 990n, perform the hinted delay of 10^n (last digit) milliseconds. @@ -519,7 +519,7 @@ unsigned int rtas_busy_delay(int status) return ms; } -EXPORT_SYMBOL(rtas_busy_delay); +EXPORT_SYMBOL_GPL(rtas_busy_delay); static int rtas_error_rc(int rtas_rc) { @@ -565,7 +565,7 @@ int rtas_get_power_level(int powerdomain, int *level) return rtas_error_rc(rc); return rc; } -EXPORT_SYMBOL(rtas_get_power_level); +EXPORT_SYMBOL_GPL(rtas_get_power_level); int rtas_set_power_level(int powerdomain, int level, int *setlevel) { @@ -583,7 +583,7 @@ int rtas_set_power_level(int powerdomain, int level, int *setlevel) return rtas_error_rc(rc); return rc; } -EXPORT_SYMBOL(rtas_set_power_level); +EXPORT_SYMBOL_GPL(rtas_set_power_level); int rtas_get_sensor(int sensor, int index, int *state) { @@ -601,7 +601,7 @@ int rtas_get_sensor(int sensor, int index, int *state) return rtas_error_rc(rc); return rc; } -EXPORT_SYMBOL(rtas_get_sensor); +EXPORT_SYMBOL_GPL(rtas_get_sensor); int rtas_get_sensor_fast(int sensor, int index, int *state) { @@ -662,7 +662,7 @@ int rtas_set_indicator(int indicator, int index, int new_value) return rtas_error_rc(rc); return rc; } -EXPORT_SYMBOL(rtas_set_indicator); +EXPORT_SYMBOL_GPL(rtas_set_indicator); /* * Ignoring RTAS extended delay diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c index 10fabae2574d5910b3cbf5ada83d912879d71351..ddab3488cadbfe297696e52816df4085231c7d7d 100644 --- a/arch/powerpc/kernel/rtas_flash.c +++ b/arch/powerpc/kernel/rtas_flash.c @@ -714,9 +714,9 @@ static int __init rtas_flash_init(void) if (!rtas_validate_flash_data.buf) return -ENOMEM; - flash_block_cache = kmem_cache_create("rtas_flash_cache", - RTAS_BLK_SIZE, RTAS_BLK_SIZE, 0, - NULL); + flash_block_cache = kmem_cache_create_usercopy("rtas_flash_cache", + RTAS_BLK_SIZE, RTAS_BLK_SIZE, + 0, 0, RTAS_BLK_SIZE, NULL); if (!flash_block_cache) { printk(KERN_ERR "%s: failed to create block cache\n", __func__); diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S index 9b346f3d2814cde487b10015ae71cc0f84f36eca..737a4698bd5e7b4820ea33b1c8935df07e0b3271 100644 --- a/arch/powerpc/kernel/vmlinux.lds.S +++ b/arch/powerpc/kernel/vmlinux.lds.S @@ -328,6 +328,7 @@ SECTIONS *(.sdata2) *(.got.plt) *(.got) *(.plt) + *(.branch_lt) } #else .data : AT(ADDR(.data) - LOAD_OFFSET) { diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h index 94f04fcb373e15654e243e073134f9eec8e3f4af..962ee90a0dfea0a6072b36b2d62563f96d6419c8 100644 --- a/arch/powerpc/kvm/e500.h +++ b/arch/powerpc/kvm/e500.h @@ -20,7 +20,7 @@ #define KVM_E500_H #include -#include +#include #include #include diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile index 3c844bdd16c4ee4e59656cf89f34364543fb9a82..d4648a1e6e6c16122793b914d699f962af2c409b 100644 --- a/arch/powerpc/mm/Makefile +++ b/arch/powerpc/mm/Makefile @@ -42,13 +42,5 @@ obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_PPC_COPRO_BASE) += copro_fault.o obj-$(CONFIG_SPAPR_TCE_IOMMU) += mmu_context_iommu.o -obj-$(CONFIG_PPC_PTDUMP) += dump_linuxpagetables.o -ifdef CONFIG_PPC_PTDUMP -obj-$(CONFIG_4xx) += dump_linuxpagetables-generic.o -obj-$(CONFIG_PPC_8xx) += dump_linuxpagetables-8xx.o -obj-$(CONFIG_PPC_BOOK3E_MMU) += dump_linuxpagetables-generic.o -obj-$(CONFIG_PPC_BOOK3S_32) += dump_linuxpagetables-generic.o -obj-$(CONFIG_PPC_BOOK3S_64) += dump_linuxpagetables-book3s64.o -endif -obj-$(CONFIG_PPC_HTDUMP) += dump_hashpagetable.o +obj-$(CONFIG_PPC_PTDUMP) += ptdump/ obj-$(CONFIG_PPC_MEM_KEYS) += pkeys.o diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c index a5091c03474753111f77df8de2910152ee38abb8..aff86679af9616e64a3e3969c645cf56a31aa342 100644 --- a/arch/powerpc/mm/init_64.c +++ b/arch/powerpc/mm/init_64.c @@ -266,8 +266,7 @@ void __ref vmemmap_free(unsigned long start, unsigned long end, start = _ALIGN_DOWN(start, page_size); if (altmap) { alt_start = altmap->base_pfn; - alt_end = altmap->base_pfn + altmap->reserve + - altmap->free + altmap->alloc + altmap->align; + alt_end = altmap->base_pfn + altmap->reserve + altmap->free; } pr_debug("vmemmap_free %lx...%lx\n", start, end); diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c index 9ee235fca4278139b8f6095049403760ab9f55e3..75cbedaac5d264a2253e741f388fa1231d4e89be 100644 --- a/arch/powerpc/mm/pgtable-radix.c +++ b/arch/powerpc/mm/pgtable-radix.c @@ -1041,8 +1041,8 @@ void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep, pte_t entry, unsigned long address, int psize) { struct mm_struct *mm = vma->vm_mm; - unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED | - _PAGE_RW | _PAGE_EXEC); + unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_SOFT_DIRTY | + _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); unsigned long change = pte_val(entry) ^ pte_val(*ptep); /* diff --git a/arch/powerpc/mm/dump_linuxpagetables-8xx.c b/arch/powerpc/mm/ptdump/8xx.c similarity index 97% rename from arch/powerpc/mm/dump_linuxpagetables-8xx.c rename to arch/powerpc/mm/ptdump/8xx.c index 33f52a97975b42a5a1566400832abf8c7d090bd6..80b4f73f7fdc2443c06f9fc701acbce7c447d00d 100644 --- a/arch/powerpc/mm/dump_linuxpagetables-8xx.c +++ b/arch/powerpc/mm/ptdump/8xx.c @@ -7,7 +7,7 @@ #include #include -#include "dump_linuxpagetables.h" +#include "ptdump.h" static const struct flag_info flag_array[] = { { diff --git a/arch/powerpc/mm/ptdump/Makefile b/arch/powerpc/mm/ptdump/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..712762be3cb11cc75aa8a686319cd865bef1aed7 --- /dev/null +++ b/arch/powerpc/mm/ptdump/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += ptdump.o + +obj-$(CONFIG_4xx) += shared.o +obj-$(CONFIG_PPC_8xx) += 8xx.o +obj-$(CONFIG_PPC_BOOK3E_MMU) += shared.o +obj-$(CONFIG_PPC_BOOK3S_32) += shared.o bats.o segment_regs.o +obj-$(CONFIG_PPC_BOOK3S_64) += book3s64.o hashpagetable.o diff --git a/arch/powerpc/mm/ptdump/bats.c b/arch/powerpc/mm/ptdump/bats.c new file mode 100644 index 0000000000000000000000000000000000000000..a0d23e96e841a801fc824481aaa01fa1aa203557 --- /dev/null +++ b/arch/powerpc/mm/ptdump/bats.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018, Christophe Leroy CS S.I. + * + * + * This dumps the content of BATS + */ + +#include +#include +#include + +static char *pp_601(int k, int pp) +{ + if (pp == 0) + return k ? "NA" : "RWX"; + if (pp == 1) + return k ? "ROX" : "RWX"; + if (pp == 2) + return k ? "RWX" : "RWX"; + return k ? "ROX" : "ROX"; +} + +static void bat_show_601(struct seq_file *m, int idx, u32 lower, u32 upper) +{ + u32 blpi = upper & 0xfffe0000; + u32 k = (upper >> 2) & 3; + u32 pp = upper & 3; + phys_addr_t pbn = PHYS_BAT_ADDR(lower); + u32 bsm = lower & 0x3ff; + u32 size = (bsm + 1) << 17; + + seq_printf(m, "%d: ", idx); + if (!(lower & 0x40)) { + seq_puts(m, " -\n"); + return; + } + + seq_printf(m, "0x%08x-0x%08x ", blpi, blpi + size - 1); +#ifdef CONFIG_PHYS_64BIT + seq_printf(m, "0x%016llx ", pbn); +#else + seq_printf(m, "0x%08x ", pbn); +#endif + + seq_printf(m, "Kernel %s User %s", pp_601(k & 2, pp), pp_601(k & 1, pp)); + + if (lower & _PAGE_WRITETHRU) + seq_puts(m, "write through "); + if (lower & _PAGE_NO_CACHE) + seq_puts(m, "no cache "); + if (lower & _PAGE_COHERENT) + seq_puts(m, "coherent "); + seq_puts(m, "\n"); +} + +#define BAT_SHOW_601(_m, _n, _l, _u) bat_show_601(_m, _n, mfspr(_l), mfspr(_u)) + +static int bats_show_601(struct seq_file *m, void *v) +{ + seq_puts(m, "---[ Block Address Translation ]---\n"); + + BAT_SHOW_601(m, 0, SPRN_IBAT0L, SPRN_IBAT0U); + BAT_SHOW_601(m, 1, SPRN_IBAT1L, SPRN_IBAT1U); + BAT_SHOW_601(m, 2, SPRN_IBAT2L, SPRN_IBAT2U); + BAT_SHOW_601(m, 3, SPRN_IBAT3L, SPRN_IBAT3U); + + return 0; +} + +static void bat_show_603(struct seq_file *m, int idx, u32 lower, u32 upper, bool is_d) +{ + u32 bepi = upper & 0xfffe0000; + u32 bl = (upper >> 2) & 0x7ff; + u32 k = upper & 3; + phys_addr_t brpn = PHYS_BAT_ADDR(lower); + u32 size = (bl + 1) << 17; + + seq_printf(m, "%d: ", idx); + if (k == 0) { + seq_puts(m, " -\n"); + return; + } + + seq_printf(m, "0x%08x-0x%08x ", bepi, bepi + size - 1); +#ifdef CONFIG_PHYS_64BIT + seq_printf(m, "0x%016llx ", brpn); +#else + seq_printf(m, "0x%08x ", brpn); +#endif + + if (k == 1) + seq_puts(m, "User "); + else if (k == 2) + seq_puts(m, "Kernel "); + else + seq_puts(m, "Kernel/User "); + + if (lower & BPP_RX) + seq_puts(m, is_d ? "RO " : "EXEC "); + else if (lower & BPP_RW) + seq_puts(m, is_d ? "RW " : "EXEC "); + else + seq_puts(m, is_d ? "NA " : "NX "); + + if (lower & _PAGE_WRITETHRU) + seq_puts(m, "write through "); + if (lower & _PAGE_NO_CACHE) + seq_puts(m, "no cache "); + if (lower & _PAGE_COHERENT) + seq_puts(m, "coherent "); + if (lower & _PAGE_GUARDED) + seq_puts(m, "guarded "); + seq_puts(m, "\n"); +} + +#define BAT_SHOW_603(_m, _n, _l, _u, _d) bat_show_603(_m, _n, mfspr(_l), mfspr(_u), _d) + +static int bats_show_603(struct seq_file *m, void *v) +{ + seq_puts(m, "---[ Instruction Block Address Translation ]---\n"); + + BAT_SHOW_603(m, 0, SPRN_IBAT0L, SPRN_IBAT0U, false); + BAT_SHOW_603(m, 1, SPRN_IBAT1L, SPRN_IBAT1U, false); + BAT_SHOW_603(m, 2, SPRN_IBAT2L, SPRN_IBAT2U, false); + BAT_SHOW_603(m, 3, SPRN_IBAT3L, SPRN_IBAT3U, false); + if (mmu_has_feature(MMU_FTR_USE_HIGH_BATS)) { + BAT_SHOW_603(m, 4, SPRN_IBAT4L, SPRN_IBAT4U, false); + BAT_SHOW_603(m, 5, SPRN_IBAT5L, SPRN_IBAT5U, false); + BAT_SHOW_603(m, 6, SPRN_IBAT6L, SPRN_IBAT6U, false); + BAT_SHOW_603(m, 7, SPRN_IBAT7L, SPRN_IBAT7U, false); + } + + seq_puts(m, "\n---[ Data Block Address Translation ]---\n"); + + BAT_SHOW_603(m, 0, SPRN_DBAT0L, SPRN_DBAT0U, true); + BAT_SHOW_603(m, 1, SPRN_DBAT1L, SPRN_DBAT1U, true); + BAT_SHOW_603(m, 2, SPRN_DBAT2L, SPRN_DBAT2U, true); + BAT_SHOW_603(m, 3, SPRN_DBAT3L, SPRN_DBAT3U, true); + if (mmu_has_feature(MMU_FTR_USE_HIGH_BATS)) { + BAT_SHOW_603(m, 4, SPRN_DBAT4L, SPRN_DBAT4U, true); + BAT_SHOW_603(m, 5, SPRN_DBAT5L, SPRN_DBAT5U, true); + BAT_SHOW_603(m, 6, SPRN_DBAT6L, SPRN_DBAT6U, true); + BAT_SHOW_603(m, 7, SPRN_DBAT7L, SPRN_DBAT7U, true); + } + + return 0; +} + +static int bats_open(struct inode *inode, struct file *file) +{ + if (cpu_has_feature(CPU_FTR_601)) + return single_open(file, bats_show_601, NULL); + + return single_open(file, bats_show_603, NULL); +} + +static const struct file_operations bats_fops = { + .open = bats_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init bats_init(void) +{ + struct dentry *debugfs_file; + + debugfs_file = debugfs_create_file("block_address_translation", 0400, + powerpc_debugfs_root, NULL, &bats_fops); + return debugfs_file ? 0 : -ENOMEM; +} +device_initcall(bats_init); diff --git a/arch/powerpc/mm/dump_linuxpagetables-book3s64.c b/arch/powerpc/mm/ptdump/book3s64.c similarity index 98% rename from arch/powerpc/mm/dump_linuxpagetables-book3s64.c rename to arch/powerpc/mm/ptdump/book3s64.c index a637e612b2055d0a8f3d205cad45b2a75f565f01..0bce5b85d01129eb8788e3740f2d3557ac02564e 100644 --- a/arch/powerpc/mm/dump_linuxpagetables-book3s64.c +++ b/arch/powerpc/mm/ptdump/book3s64.c @@ -7,7 +7,7 @@ #include #include -#include "dump_linuxpagetables.h" +#include "ptdump.h" static const struct flag_info flag_array[] = { { diff --git a/arch/powerpc/mm/dump_hashpagetable.c b/arch/powerpc/mm/ptdump/hashpagetable.c similarity index 100% rename from arch/powerpc/mm/dump_hashpagetable.c rename to arch/powerpc/mm/ptdump/hashpagetable.c diff --git a/arch/powerpc/mm/dump_linuxpagetables.c b/arch/powerpc/mm/ptdump/ptdump.c similarity index 99% rename from arch/powerpc/mm/dump_linuxpagetables.c rename to arch/powerpc/mm/ptdump/ptdump.c index 6aa41669ac1aec6b0db81da31d45b47bbade30c1..76be98988578d0a43fbff60488b9fb3b3dec9f51 100644 --- a/arch/powerpc/mm/dump_linuxpagetables.c +++ b/arch/powerpc/mm/ptdump/ptdump.c @@ -28,7 +28,7 @@ #include #include -#include "dump_linuxpagetables.h" +#include "ptdump.h" #ifdef CONFIG_PPC32 #define KERN_VIRT_START 0 diff --git a/arch/powerpc/mm/dump_linuxpagetables.h b/arch/powerpc/mm/ptdump/ptdump.h similarity index 100% rename from arch/powerpc/mm/dump_linuxpagetables.h rename to arch/powerpc/mm/ptdump/ptdump.h diff --git a/arch/powerpc/mm/ptdump/segment_regs.c b/arch/powerpc/mm/ptdump/segment_regs.c new file mode 100644 index 0000000000000000000000000000000000000000..501843664bb91bd52db8b7f7554750a265533814 --- /dev/null +++ b/arch/powerpc/mm/ptdump/segment_regs.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018, Christophe Leroy CS S.I. + * + * + * This dumps the content of Segment Registers + */ + +#include + +static void seg_show(struct seq_file *m, int i) +{ + u32 val = mfsrin(i << 28); + + seq_printf(m, "0x%01x0000000-0x%01xfffffff ", i, i); + seq_printf(m, "Kern key %d ", (val >> 30) & 1); + seq_printf(m, "User key %d ", (val >> 29) & 1); + if (val & 0x80000000) { + seq_printf(m, "Device 0x%03x", (val >> 20) & 0x1ff); + seq_printf(m, "-0x%05x", val & 0xfffff); + } else { + if (val & 0x10000000) + seq_puts(m, "No Exec "); + seq_printf(m, "VSID 0x%06x", val & 0xffffff); + } + seq_puts(m, "\n"); +} + +static int sr_show(struct seq_file *m, void *v) +{ + int i; + + seq_puts(m, "---[ User Segments ]---\n"); + for (i = 0; i < TASK_SIZE >> 28; i++) + seg_show(m, i); + + seq_puts(m, "\n---[ Kernel Segments ]---\n"); + for (; i < 16; i++) + seg_show(m, i); + + return 0; +} + +static int sr_open(struct inode *inode, struct file *file) +{ + return single_open(file, sr_show, NULL); +} + +static const struct file_operations sr_fops = { + .open = sr_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init sr_init(void) +{ + struct dentry *debugfs_file; + + debugfs_file = debugfs_create_file("segment_registers", 0400, + powerpc_debugfs_root, NULL, &sr_fops); + return debugfs_file ? 0 : -ENOMEM; +} +device_initcall(sr_init); diff --git a/arch/powerpc/mm/dump_linuxpagetables-generic.c b/arch/powerpc/mm/ptdump/shared.c similarity index 97% rename from arch/powerpc/mm/dump_linuxpagetables-generic.c rename to arch/powerpc/mm/ptdump/shared.c index fed6923bcb46e67b69b96849aecbc7f415c37cde..1cda3d91c6c26f7adf541f5f0d8afab3f17928b9 100644 --- a/arch/powerpc/mm/dump_linuxpagetables-generic.c +++ b/arch/powerpc/mm/ptdump/shared.c @@ -7,7 +7,7 @@ #include #include -#include "dump_linuxpagetables.h" +#include "ptdump.h" static const struct flag_info flag_array[] = { { diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c index 2bb798918483dc9029b59e2b0d33fa34d24925b3..e6eb2b4cf97eaaf89fc79d73dd4510133501d557 100644 --- a/arch/powerpc/perf/hv-24x7.c +++ b/arch/powerpc/perf/hv-24x7.c @@ -1326,7 +1326,7 @@ static int h_24x7_event_init(struct perf_event *event) } domain = event_get_domain(event); - if (domain >= HV_PERF_DOMAIN_MAX) { + if (domain == 0 || domain >= HV_PERF_DOMAIN_MAX) { pr_devel("invalid domain %d\n", domain); return -EINVAL; } diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c index b3097fe6441b9571095a696b7ee357c995b88dbb..1019d78e44bb45d2766ddadbc21549c3b6d7b917 100644 --- a/arch/powerpc/platforms/512x/clock-commonclk.c +++ b/arch/powerpc/platforms/512x/clock-commonclk.c @@ -985,7 +985,7 @@ static void mpc5121_clk_provide_migration_support(void) #define NODE_PREP do { \ of_address_to_resource(np, 0, &res); \ - snprintf(devname, sizeof(devname), "%08x.%s", res.start, np->name); \ + snprintf(devname, sizeof(devname), "%pa.%s", &res.start, np->name); \ } while (0) #define NODE_CHK(clkname, clkitem, regnode, regflag) do { \ diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c index fc98912f42cf6edbf079a4f9f9bf4da436a159f3..76a8102bdb987588b95120a387f757499045d160 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c @@ -340,7 +340,7 @@ static int mpc52xx_irqhost_map(struct irq_domain *h, unsigned int virq, { int l1irq; int l2irq; - struct irq_chip *uninitialized_var(irqchip); + struct irq_chip *irqchip; void *hndlr; int type; u32 reg; diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c index db0be007fd063b349c51b83d0afe4ba376496fd9..bfca4d42b00d3b32ae4754e8df32eb5233a8e910 100644 --- a/arch/powerpc/platforms/embedded6xx/flipper-pic.c +++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c @@ -149,7 +149,7 @@ static struct irq_domain * __init flipper_pic_init(struct device_node *np) } io_base = ioremap(res.start, resource_size(&res)); - pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base); + pr_info("controller at 0x%pa mapped to 0x%p\n", &res.start, io_base); __flipper_quiesce(io_base); diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c index 7b4edf1cb2c8dad4b71101641648a593bdaa08d0..bdc7e1a80366fb73ec0232dafa858721b6907256 100644 --- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c +++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c @@ -178,7 +178,7 @@ static struct irq_domain *hlwd_pic_init(struct device_node *np) return NULL; } - pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base); + pr_info("controller at 0x%pa mapped to 0x%p\n", &res.start, io_base); __hlwd_quiesce(io_base); diff --git a/arch/powerpc/platforms/embedded6xx/wii.c b/arch/powerpc/platforms/embedded6xx/wii.c index 343bffd20fcaf2ceb378a06dd597fd4e4367b268..768231005fb5aad9711d61307a18388fea6e8466 100644 --- a/arch/powerpc/platforms/embedded6xx/wii.c +++ b/arch/powerpc/platforms/embedded6xx/wii.c @@ -122,8 +122,8 @@ static void __iomem *wii_ioremap_hw_regs(char *name, char *compatible) hw_regs = ioremap(res.start, resource_size(&res)); if (hw_regs) { - pr_info("%s at 0x%08x mapped to 0x%p\n", name, - res.start, hw_regs); + pr_info("%s at 0x%pa mapped to 0x%p\n", name, + &res.start, hw_regs); } out_put: diff --git a/arch/powerpc/platforms/powermac/Makefile b/arch/powerpc/platforms/powermac/Makefile index 561a67d65e4d46b1d069839f66a0e6b3da8b9578..923bfb34043336c044ea9d127ccf0567f7b55ad2 100644 --- a/arch/powerpc/platforms/powermac/Makefile +++ b/arch/powerpc/platforms/powermac/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 CFLAGS_bootx_init.o += -fPIC +CFLAGS_bootx_init.o += $(call cc-option, -fno-stack-protector) ifdef CONFIG_FUNCTION_TRACER # Do not trace early boot code diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index ecd211c5f24a58b2a668d18b630be76dcd305b10..cd3e5ed7d77c535bdc0a1e7fc764b5a107924e0f 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -3123,7 +3123,8 @@ static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, int index; int64_t rc; - if (!res || !res->flags || res->start > res->end) + if (!res || !res->flags || res->start > res->end || + res->flags & IORESOURCE_UNSET) return; if (res->flags & IORESOURCE_IO) { diff --git a/arch/powerpc/platforms/pseries/ibmebus.c b/arch/powerpc/platforms/pseries/ibmebus.c index c7c1140c13b6cb8707c4204c9266e2bd217022d3..3fce7508a4fc6db11595e77d413a0942960d6800 100644 --- a/arch/powerpc/platforms/pseries/ibmebus.c +++ b/arch/powerpc/platforms/pseries/ibmebus.c @@ -452,6 +452,7 @@ static int __init ibmebus_bus_init(void) if (err) { printk(KERN_WARNING "%s: device_register returned %i\n", __func__, err); + put_device(&ibmebus_bus_device); bus_unregister(&ibmebus_bus_type); return err; diff --git a/arch/powerpc/platforms/pseries/lparcfg.c b/arch/powerpc/platforms/pseries/lparcfg.c index 7c872dc01bdb0aa4389302b89eec898b710c0462..d1b338b7dbdedc96431b23ec3df951cbffbad9d8 100644 --- a/arch/powerpc/platforms/pseries/lparcfg.c +++ b/arch/powerpc/platforms/pseries/lparcfg.c @@ -291,6 +291,7 @@ static void parse_mpp_x_data(struct seq_file *m) */ static void parse_system_parameter_string(struct seq_file *m) { + const s32 token = rtas_token("ibm,get-system-parameter"); int call_status; unsigned char *local_buffer = kmalloc(SPLPAR_MAXLENGTH, GFP_KERNEL); @@ -300,16 +301,15 @@ static void parse_system_parameter_string(struct seq_file *m) return; } - spin_lock(&rtas_data_buf_lock); - memset(rtas_data_buf, 0, SPLPAR_MAXLENGTH); - call_status = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1, - NULL, - SPLPAR_CHARACTERISTICS_TOKEN, - __pa(rtas_data_buf), - RTAS_DATA_BUF_SIZE); - memcpy(local_buffer, rtas_data_buf, SPLPAR_MAXLENGTH); - local_buffer[SPLPAR_MAXLENGTH - 1] = '\0'; - spin_unlock(&rtas_data_buf_lock); + do { + spin_lock(&rtas_data_buf_lock); + memset(rtas_data_buf, 0, SPLPAR_MAXLENGTH); + call_status = rtas_call(token, 3, 1, NULL, SPLPAR_CHARACTERISTICS_TOKEN, + __pa(rtas_data_buf), RTAS_DATA_BUF_SIZE); + memcpy(local_buffer, rtas_data_buf, SPLPAR_MAXLENGTH); + local_buffer[SPLPAR_MAXLENGTH - 1] = '\0'; + spin_unlock(&rtas_data_buf_lock); + } while (rtas_busy_delay(call_status)); if (call_status != 0) { printk(KERN_INFO diff --git a/arch/powerpc/purgatory/Makefile b/arch/powerpc/purgatory/Makefile index 4314ba5baf435c70d3a78006adabba34367acaf9..f6a976e7c877785ca14b112148e5bd54566a0c92 100644 --- a/arch/powerpc/purgatory/Makefile +++ b/arch/powerpc/purgatory/Makefile @@ -1,6 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 targets += trampoline.o purgatory.ro kexec-purgatory.c +# When profile-guided optimization is enabled, llvm emits two different +# overlapping text sections, which is not supported by kexec. Remove profile +# optimization flags. +KBUILD_CFLAGS := $(filter-out -fprofile-sample-use=% -fprofile-use=%,$(KBUILD_CFLAGS)) + LDFLAGS_purgatory.ro := -e purgatory_start -r --no-undefined $(obj)/purgatory.ro: $(obj)/trampoline.o FORCE diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c index 28ff1f53cefc1d1101695f5c280578cf516403c2..6bd50c690006fcc09f231710d5ac923c3cf46d40 100644 --- a/arch/powerpc/sysdev/tsi108_pci.c +++ b/arch/powerpc/sysdev/tsi108_pci.c @@ -229,9 +229,8 @@ int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary) (hose)->ops = &tsi108_direct_pci_ops; - printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. " - "Firmware bus number: %d->%d\n", - rsrc.start, hose->first_busno, hose->last_busno); + pr_info("Found tsi108 PCI host bridge at 0x%pa. Firmware bus number: %d->%d\n", + &rsrc.start, hose->first_busno, hose->last_busno); /* Interpret the "ranges" property */ /* This also maps the I/O region and sets isa_io/mem_base */ diff --git a/arch/riscv/include/uapi/asm/setup.h b/arch/riscv/include/uapi/asm/setup.h new file mode 100644 index 0000000000000000000000000000000000000000..66b13a5228808dcbf79a03bac165788bc439af18 --- /dev/null +++ b/arch/riscv/include/uapi/asm/setup.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ + +#ifndef _UAPI_ASM_RISCV_SETUP_H +#define _UAPI_ASM_RISCV_SETUP_H + +#define COMMAND_LINE_SIZE 1024 + +#endif /* _UAPI_ASM_RISCV_SETUP_H */ diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c index 15f4ab40e2221d93db9387b32e724d6b599fba46..50bb7e0d44ba3fa18261e077cb22f88d723a77e5 100644 --- a/arch/riscv/kernel/time.c +++ b/arch/riscv/kernel/time.c @@ -13,6 +13,7 @@ */ #include +#include #include #include #include @@ -33,4 +34,6 @@ void __init time_init(void) of_clk_init(NULL); timer_probe(); + + tick_setup_hrtimer_broadcast(); } diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c index 7c0a095e9c5f6f3d483ceff698f7d7ffd06e614b..b52ca21be3674a719ff8f2c2fe3eaef4875694d0 100644 --- a/arch/s390/kernel/kprobes.c +++ b/arch/s390/kernel/kprobes.c @@ -254,6 +254,7 @@ static void pop_kprobe(struct kprobe_ctlblk *kcb) { __this_cpu_write(current_kprobe, kcb->prev_kprobe.kp); kcb->kprobe_status = kcb->prev_kprobe.status; + kcb->prev_kprobe.kp = NULL; } NOKPROBE_SYMBOL(pop_kprobe); @@ -508,12 +509,11 @@ static int post_kprobe_handler(struct pt_regs *regs) if (!p) return 0; + resume_execution(p, regs); if (kcb->kprobe_status != KPROBE_REENTER && p->post_handler) { kcb->kprobe_status = KPROBE_HIT_SSDONE; p->post_handler(p, regs, 0); } - - resume_execution(p, regs); pop_kprobe(kcb); preempt_enable_no_resched(); diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c index 3ffa2847c110bcbfac536e73113d92869a8e02f4..c36289a3ad500ec18de36ef0ab774793c5843c12 100644 --- a/arch/s390/kernel/ptrace.c +++ b/arch/s390/kernel/ptrace.c @@ -503,9 +503,7 @@ long arch_ptrace(struct task_struct *child, long request, } return 0; case PTRACE_GET_LAST_BREAK: - put_user(child->thread.last_break, - (unsigned long __user *) data); - return 0; + return put_user(child->thread.last_break, (unsigned long __user *)data); case PTRACE_ENABLE_TE: if (!MACHINE_HAS_TE) return -EIO; @@ -857,9 +855,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, } return 0; case PTRACE_GET_LAST_BREAK: - put_user(child->thread.last_break, - (unsigned int __user *) data); - return 0; + return put_user(child->thread.last_break, (unsigned int __user *)data); } return compat_ptrace_request(child, request, addr, data); } diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index bce678c7179c8fcbad6933659970a56512d13cea..f272b662301e4d3d0af354b0db4a791f69964c74 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -145,7 +145,7 @@ static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) static inline int pcpu_stopped(struct pcpu *pcpu) { - u32 uninitialized_var(status); + u32 status; if (__pcpu_sigp(pcpu->address, SIGP_SENSE, 0, &status) != SIGP_CC_STATUS_STORED) diff --git a/arch/s390/kernel/sthyi.c b/arch/s390/kernel/sthyi.c index 888cc2f166db726d8e5c967c4082e781cc6137f4..ce6084e28d904802ef809a197b14d60609794068 100644 --- a/arch/s390/kernel/sthyi.c +++ b/arch/s390/kernel/sthyi.c @@ -460,9 +460,9 @@ static int sthyi_update_cache(u64 *rc) * * Fills the destination with system information returned by the STHYI * instruction. The data is generated by emulation or execution of STHYI, - * if available. The return value is the condition code that would be - * returned, the rc parameter is the return code which is passed in - * register R2 + 1. + * if available. The return value is either a negative error value or + * the condition code that would be returned, the rc parameter is the + * return code which is passed in register R2 + 1. */ int sthyi_fill(void *dst, u64 *rc) { diff --git a/arch/s390/kernel/vmlinux.lds.S b/arch/s390/kernel/vmlinux.lds.S index 160a05c6ce8816d76addc7ec2263a10c82176001..04c3e56da0f2b0a26bf1c00a0aa34b14ac562ee6 100644 --- a/arch/s390/kernel/vmlinux.lds.S +++ b/arch/s390/kernel/vmlinux.lds.S @@ -153,5 +153,6 @@ SECTIONS DISCARDS /DISCARD/ : { *(.eh_frame) + *(.interp) } } diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index a389fa85cca2d4bcb2ff6f715ffd5ffe682eb965..5450d43d26ea5c4606a72a656aed884b33892a19 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -360,8 +360,8 @@ static int handle_partial_execution(struct kvm_vcpu *vcpu) */ int handle_sthyi(struct kvm_vcpu *vcpu) { - int reg1, reg2, r = 0; - u64 code, addr, cc = 0, rc = 0; + int reg1, reg2, cc = 0, r = 0; + u64 code, addr, rc = 0; struct sthyi_sctns *sctns = NULL; if (!test_kvm_facility(vcpu->kvm, 74)) @@ -392,7 +392,10 @@ int handle_sthyi(struct kvm_vcpu *vcpu) return -ENOMEM; cc = sthyi_fill(sctns, &rc); - + if (cc < 0) { + free_page((unsigned long)sctns); + return cc; + } out: if (!cc) { r = write_guest(vcpu, addr, reg2, sctns, PAGE_SIZE); diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index 3aade928c18dd069c798de9a352ed99b5fa492e3..92041d442d2e6d7beb0814f23ba41fc85216e425 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -1716,6 +1716,10 @@ static unsigned long kvm_s390_next_dirty_cmma(struct kvm_memslots *slots, ms = slots->memslots + slotidx; ofs = 0; } + + if (cur_gfn < ms->base_gfn) + ofs = 0; + ofs = find_next_bit(kvm_second_dirty_bitmap(ms), ms->npages, ofs); while ((slotidx > 0) && (ofs >= ms->npages)) { slotidx--; diff --git a/arch/s390/lib/uaccess.c b/arch/s390/lib/uaccess.c index 0267405ab7c69fec93f73df3ed35f381b03c7f38..fcfd78f99cb4b7390f450b4cca651679e230bf55 100644 --- a/arch/s390/lib/uaccess.c +++ b/arch/s390/lib/uaccess.c @@ -339,7 +339,7 @@ static inline unsigned long clear_user_mvcos(void __user *to, unsigned long size "4: slgr %0,%0\n" "5:\n" EX_TABLE(0b,2b) EX_TABLE(3b,5b) - : "+a" (size), "+a" (to), "+a" (tmp1), "=a" (tmp2) + : "+&a" (size), "+&a" (to), "+a" (tmp1), "=&a" (tmp2) : "a" (empty_zero_page), "d" (reg0) : "cc", "memory"); return size; } diff --git a/arch/s390/mm/maccess.c b/arch/s390/mm/maccess.c index 7be06475809b875fd513173c617fe6683fb1f37d..a40739ea3805e423327bbb200e4aa1f9852e816c 100644 --- a/arch/s390/mm/maccess.c +++ b/arch/s390/mm/maccess.c @@ -58,13 +58,19 @@ static notrace long s390_kernel_write_odd(void *dst, const void *src, size_t siz */ void notrace s390_kernel_write(void *dst, const void *src, size_t size) { + unsigned long flags; long copied; - while (size) { - copied = s390_kernel_write_odd(dst, src, size); - dst += copied; - src += copied; - size -= copied; + flags = arch_local_save_flags(); + if (!(flags & PSW_MASK_DAT)) { + memcpy(dst, src, size); + } else { + while (size) { + copied = s390_kernel_write_odd(dst, src, size); + dst += copied; + src += copied; + size -= copied; + } } } diff --git a/arch/s390/pci/pci_dma.c b/arch/s390/pci/pci_dma.c index d387a0fbdd7e4d6d2cb3f3e646bbdad6c42ff2a3..76d27a5947d541a8f33a3b5262aac765e2c03119 100644 --- a/arch/s390/pci/pci_dma.c +++ b/arch/s390/pci/pci_dma.c @@ -545,6 +545,17 @@ static void s390_dma_unmap_sg(struct device *dev, struct scatterlist *sg, s->dma_length = 0; } } + +static unsigned long *bitmap_vzalloc(size_t bits, gfp_t flags) +{ + size_t n = BITS_TO_LONGS(bits); + size_t bytes; + + if (unlikely(check_mul_overflow(n, sizeof(unsigned long), &bytes))) + return NULL; + + return vzalloc(bytes); +} static int s390_mapping_error(struct device *dev, dma_addr_t dma_addr) { @@ -586,13 +597,13 @@ int zpci_dma_init_device(struct zpci_dev *zdev) zdev->end_dma - zdev->start_dma + 1); zdev->end_dma = zdev->start_dma + zdev->iommu_size - 1; zdev->iommu_pages = zdev->iommu_size >> PAGE_SHIFT; - zdev->iommu_bitmap = vzalloc(zdev->iommu_pages / 8); + zdev->iommu_bitmap = bitmap_vzalloc(zdev->iommu_pages, GFP_KERNEL); if (!zdev->iommu_bitmap) { rc = -ENOMEM; goto free_dma_table; } if (!s390_iommu_strict) { - zdev->lazy_bitmap = vzalloc(zdev->iommu_pages / 8); + zdev->lazy_bitmap = bitmap_vzalloc(zdev->iommu_pages, GFP_KERNEL); if (!zdev->lazy_bitmap) { rc = -ENOMEM; goto free_bitmap; diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 1fb7b6d72bafcdae6c10cdc5b4174ae6c45a1db9..63e00320eb3cef49abec7a45bdc35b2d7d6ea942 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 config SUPERH def_bool y + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_MIGHT_HAVE_PC_PARPORT diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug index 71acd3d9b9e8342e106318d68eed2fe82532cd00..dfc784f8979721aef9034a5d3903acc8c48399a5 100644 --- a/arch/sh/Kconfig.debug +++ b/arch/sh/Kconfig.debug @@ -26,6 +26,17 @@ config STACK_DEBUG every function call and will therefore incur a major performance hit. Most users should say N. +config EARLY_PRINTK + bool "Early printk" + depends on SH_STANDARD_BIOS + help + Say Y here to redirect kernel printk messages to the serial port + used by the SH-IPL bootloader, starting very early in the boot + process and ending when the kernel's serial console is initialised. + This option is only useful while porting the kernel to a new machine, + when the kernel may crash or hang before the serial console is + initialised. If unsure, say N. + config 4KSTACKS bool "Use 4Kb for kernel stacks instead of 8Kb" depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c index afde2a7d3eb35859270fe4a3bbdf20d742b8b35a..e0679d8a9b34ba21154aa24cd3743b6df65c2258 100644 --- a/arch/sh/drivers/dma/dma-sh.c +++ b/arch/sh/drivers/dma/dma-sh.c @@ -21,6 +21,18 @@ #include #include +/* + * Some of the SoCs feature two DMAC modules. In such a case, the channels are + * distributed equally among them. + */ +#ifdef SH_DMAC_BASE1 +#define SH_DMAC_NR_MD_CH (CONFIG_NR_ONCHIP_DMA_CHANNELS / 2) +#else +#define SH_DMAC_NR_MD_CH CONFIG_NR_ONCHIP_DMA_CHANNELS +#endif + +#define SH_DMAC_CH_SZ 0x10 + /* * Define the default configuration for dual address memory-memory transfer. * The 0x400 value represents auto-request, external->external. @@ -32,7 +44,7 @@ static unsigned long dma_find_base(unsigned int chan) unsigned long base = SH_DMAC_BASE0; #ifdef SH_DMAC_BASE1 - if (chan >= 6) + if (chan >= SH_DMAC_NR_MD_CH) base = SH_DMAC_BASE1; #endif @@ -43,13 +55,13 @@ static unsigned long dma_base_addr(unsigned int chan) { unsigned long base = dma_find_base(chan); - /* Normalize offset calculation */ - if (chan >= 9) - chan -= 6; - if (chan >= 4) - base += 0x10; + chan = (chan % SH_DMAC_NR_MD_CH) * SH_DMAC_CH_SZ; + + /* DMAOR is placed inside the channel register space. Step over it. */ + if (chan >= DMAOR) + base += SH_DMAC_CH_SZ; - return base + (chan * 0x10); + return base + chan; } #ifdef CONFIG_SH_DMA_IRQ_MULTI @@ -253,12 +265,11 @@ static int sh_dmac_get_dma_residue(struct dma_channel *chan) #define NR_DMAOR 1 #endif -/* - * DMAOR bases are broken out amongst channel groups. DMAOR0 manages - * channels 0 - 5, DMAOR1 6 - 11 (optional). - */ -#define dmaor_read_reg(n) __raw_readw(dma_find_base((n)*6)) -#define dmaor_write_reg(n, data) __raw_writew(data, dma_find_base(n)*6) +#define dmaor_read_reg(n) __raw_readw(dma_find_base((n) * \ + SH_DMAC_NR_MD_CH) + DMAOR) +#define dmaor_write_reg(n, data) __raw_writew(data, \ + dma_find_base((n) * \ + SH_DMAC_NR_MD_CH) + DMAOR) static inline int dmaor_reset(int no) { diff --git a/arch/sh/include/asm/bugs.h b/arch/sh/include/asm/bugs.h deleted file mode 100644 index 030df56bfdb20f2b8a648c3a82e44a3684cb3e5d..0000000000000000000000000000000000000000 --- a/arch/sh/include/asm/bugs.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_SH_BUGS_H -#define __ASM_SH_BUGS_H - -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ - -/* - * I don't know of any Super-H bugs yet. - */ - -#include - -extern void select_idle_routine(void); - -static void __init check_bugs(void) -{ - extern unsigned long loops_per_jiffy; - char *p = &init_utsname()->machine[2]; /* "sh" */ - - select_idle_routine(); - - current_cpu_data.loops_per_jiffy = loops_per_jiffy; - - switch (current_cpu_data.family) { - case CPU_FAMILY_SH2: - *p++ = '2'; - break; - case CPU_FAMILY_SH2A: - *p++ = '2'; - *p++ = 'a'; - break; - case CPU_FAMILY_SH3: - *p++ = '3'; - break; - case CPU_FAMILY_SH4: - *p++ = '4'; - break; - case CPU_FAMILY_SH4A: - *p++ = '4'; - *p++ = 'a'; - break; - case CPU_FAMILY_SH4AL_DSP: - *p++ = '4'; - *p++ = 'a'; - *p++ = 'l'; - *p++ = '-'; - *p++ = 'd'; - *p++ = 's'; - *p++ = 'p'; - break; - case CPU_FAMILY_SH5: - *p++ = '6'; - *p++ = '4'; - break; - case CPU_FAMILY_UNKNOWN: - /* - * Specifically use CPU_FAMILY_UNKNOWN rather than - * default:, so we're able to have the compiler whine - * about unhandled enumerations. - */ - break; - } - - printk("CPU: %s\n", get_cpu_subtype(¤t_cpu_data)); - -#ifndef __LITTLE_ENDIAN__ - /* 'eb' means 'Endian Big' */ - *p++ = 'e'; - *p++ = 'b'; -#endif - *p = '\0'; -} -#endif /* __ASM_SH_BUGS_H */ diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index 6fbf8c80e4981d1fa3cd78fd28e3224552247a3b..386786b1594ab06127bfbcfde86904200f084317 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -173,6 +173,8 @@ extern unsigned int instruction_size(unsigned int insn); #define instruction_size(insn) (4) #endif +void select_idle_routine(void); + #endif /* __ASSEMBLY__ */ #ifdef CONFIG_SUPERH32 diff --git a/arch/sh/include/asm/processor_32.h b/arch/sh/include/asm/processor_32.h index 95100d8a0b7b485427cf615990543b71f6d19083..fc94603724b8695446d6352c63e6942bbd52bbab 100644 --- a/arch/sh/include/asm/processor_32.h +++ b/arch/sh/include/asm/processor_32.h @@ -57,6 +57,7 @@ #define SR_FD 0x00008000 #define SR_MD 0x40000000 +#define SR_USER_MASK 0x00000303 // M, Q, S, T bits /* * DSP structure and data */ diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c index a5bd03642678906a21e1d5fc8f853b4264bfd2e8..75dcb1d6bc62f8a0e92ca1bb7a7116603028d6e9 100644 --- a/arch/sh/kernel/cpu/sh2/probe.c +++ b/arch/sh/kernel/cpu/sh2/probe.c @@ -24,7 +24,7 @@ static int __init scan_cache(unsigned long node, const char *uname, if (!of_flat_dt_is_compatible(node, "jcore,cache")) return 0; - j2_ccr_base = (u32 __iomem *)of_flat_dt_translate_address(node); + j2_ccr_base = ioremap(of_flat_dt_translate_address(node), 4); return 1; } diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c index 4ca78ed71ad2c8ff33707fb8a472d55b553de36e..c218bae8fe208355deabccb9a2aec6eb99bf3f2c 100644 --- a/arch/sh/kernel/cpu/sh4/sq.c +++ b/arch/sh/kernel/cpu/sh4/sq.c @@ -383,7 +383,7 @@ static int __init sq_api_init(void) if (unlikely(!sq_cache)) return ret; - sq_bitmap = kzalloc(size, GFP_KERNEL); + sq_bitmap = kcalloc(size, sizeof(long), GFP_KERNEL); if (unlikely(!sq_bitmap)) goto out; diff --git a/arch/sh/kernel/head_32.S b/arch/sh/kernel/head_32.S index 4e352c3f79e6b79f1338e5a90d7f4cfa39d304c4..fb505cda25fc84db5d28cbd1a868f319731f521e 100644 --- a/arch/sh/kernel/head_32.S +++ b/arch/sh/kernel/head_32.S @@ -67,7 +67,7 @@ ENTRY(_stext) ldc r0, r6_bank #endif -#ifdef CONFIG_OF_FLATTREE +#ifdef CONFIG_OF_EARLY_FLATTREE mov r4, r12 ! Store device tree blob pointer in r12 #endif @@ -318,7 +318,7 @@ ENTRY(_stext) 10: #endif -#ifdef CONFIG_OF_FLATTREE +#ifdef CONFIG_OF_EARLY_FLATTREE mov.l 8f, r0 ! Make flat device tree available early. jsr @r0 mov r12, r4 @@ -349,7 +349,7 @@ ENTRY(stack_start) 5: .long start_kernel 6: .long cpu_init 7: .long init_thread_union -#if defined(CONFIG_OF_FLATTREE) +#if defined(CONFIG_OF_EARLY_FLATTREE) 8: .long sh_fdt_init #endif diff --git a/arch/sh/kernel/idle.c b/arch/sh/kernel/idle.c index be616ee0cf8799a6c7deeb058a7a92da6a8f213c..5169309fdf98c23d062ead7f4429935c7d9c216f 100644 --- a/arch/sh/kernel/idle.c +++ b/arch/sh/kernel/idle.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include diff --git a/arch/sh/kernel/nmi_debug.c b/arch/sh/kernel/nmi_debug.c index 730d928f0d12428af6a888af4aab7b156eb52ce5..d37b54f9cec6f7afd3a62c6eab42ac1f69ed24ad 100644 --- a/arch/sh/kernel/nmi_debug.c +++ b/arch/sh/kernel/nmi_debug.c @@ -52,7 +52,7 @@ static int __init nmi_debug_setup(char *str) register_die_notifier(&nmi_debug_nb); if (*str != '=') - return 0; + return 1; for (p = str + 1; *p; p = sep + 1) { sep = strchr(p, ','); @@ -73,6 +73,6 @@ static int __init nmi_debug_setup(char *str) break; } - return 0; + return 1; } __setup("nmi_debug", nmi_debug_setup); diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index c286cf5da6e770f5b7cbadcb4f815f986822e443..8ef497062350c4197b44ac378a5d4fb5fba8042a 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -42,6 +42,7 @@ #include #include #include +#include #include /* @@ -242,7 +243,7 @@ void __init __weak plat_early_device_setup(void) { } -#ifdef CONFIG_OF_FLATTREE +#ifdef CONFIG_OF_EARLY_FLATTREE void __ref sh_fdt_init(phys_addr_t dt_phys) { static int done = 0; @@ -329,7 +330,7 @@ void __init setup_arch(char **cmdline_p) /* Let earlyprintk output early console messages */ early_platform_driver_probe("earlyprintk", 1, 1); -#ifdef CONFIG_OF_FLATTREE +#ifdef CONFIG_OF_EARLY_FLATTREE #ifdef CONFIG_USE_BUILTIN_DTB unflatten_and_copy_device_tree(); #else @@ -361,3 +362,57 @@ int test_mode_pin(int pin) { return sh_mv.mv_mode_pins() & pin; } + +void __init arch_cpu_finalize_init(void) +{ + char *p = &init_utsname()->machine[2]; /* "sh" */ + + select_idle_routine(); + + current_cpu_data.loops_per_jiffy = loops_per_jiffy; + + switch (current_cpu_data.family) { + case CPU_FAMILY_SH2: + *p++ = '2'; + break; + case CPU_FAMILY_SH2A: + *p++ = '2'; + *p++ = 'a'; + break; + case CPU_FAMILY_SH3: + *p++ = '3'; + break; + case CPU_FAMILY_SH4: + *p++ = '4'; + break; + case CPU_FAMILY_SH4A: + *p++ = '4'; + *p++ = 'a'; + break; + case CPU_FAMILY_SH4AL_DSP: + *p++ = '4'; + *p++ = 'a'; + *p++ = 'l'; + *p++ = '-'; + *p++ = 'd'; + *p++ = 's'; + *p++ = 'p'; + break; + case CPU_FAMILY_UNKNOWN: + /* + * Specifically use CPU_FAMILY_UNKNOWN rather than + * default:, so we're able to have the compiler whine + * about unhandled enumerations. + */ + break; + } + + pr_info("CPU: %s\n", get_cpu_subtype(¤t_cpu_data)); + +#ifndef __LITTLE_ENDIAN__ + /* 'eb' means 'Endian Big' */ + *p++ = 'e'; + *p++ = 'b'; +#endif + *p = '\0'; +} diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c index c46c0020ff55edf0fdfda120ed90cd3fa7b65d17..ce93ae78c3002a55ffe3ed8893383adf14c4dcd4 100644 --- a/arch/sh/kernel/signal_32.c +++ b/arch/sh/kernel/signal_32.c @@ -116,6 +116,7 @@ static int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *r0_p) { unsigned int err = 0; + unsigned int sr = regs->sr & ~SR_USER_MASK; #define COPY(x) err |= __get_user(regs->x, &sc->sc_##x) COPY(regs[1]); @@ -131,6 +132,8 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *r0_p COPY(sr); COPY(pc); #undef COPY + regs->sr = (regs->sr & SR_USER_MASK) | sr; + #ifdef CONFIG_SH_FPU if (boot_cpu_data.flags & CPU_HAS_FPU) { int owned_fp; diff --git a/arch/sh/math-emu/sfp-util.h b/arch/sh/math-emu/sfp-util.h index 784f541344f36d0bba7749dd413160e8317f7c11..bda50762b3d3358ce64946ff2da67467ac5b6468 100644 --- a/arch/sh/math-emu/sfp-util.h +++ b/arch/sh/math-emu/sfp-util.h @@ -67,7 +67,3 @@ } while (0) #define abort() return 0 - -#define __BYTE_ORDER __LITTLE_ENDIAN - - diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 1f1a7583fa9056a0d800ee2d618b4bf129480cc8..8a0bb7c48e9a552d2cc58ecb55af955f35582e9f 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -50,6 +50,7 @@ config SPARC config SPARC32 def_bool !64BIT + select ARCH_HAS_CPU_FINALIZE_INIT if !SMP select ARCH_HAS_SYNC_DMA_FOR_CPU select DMA_NONCOHERENT_OPS select GENERIC_ATOMIC64 @@ -329,7 +330,7 @@ config FORCE_MAX_ZONEORDER This config option is actually maximum order plus one. For example, a value of 13 means that the largest free memory block is 2^12 pages. -if SPARC64 +if SPARC64 || COMPILE_TEST source "kernel/power/Kconfig" endif diff --git a/arch/sparc/include/asm/bugs.h b/arch/sparc/include/asm/bugs.h deleted file mode 100644 index 02fa369b9c21f440c9a792055cd76ddc1eaa53df..0000000000000000000000000000000000000000 --- a/arch/sparc/include/asm/bugs.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* include/asm/bugs.h: Sparc probes for various bugs. - * - * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net) - */ - -#ifdef CONFIG_SPARC32 -#include -#endif - -extern unsigned long loops_per_jiffy; - -static void __init check_bugs(void) -{ -#if defined(CONFIG_SPARC32) && !defined(CONFIG_SMP) - cpu_data(0).udelay_val = loops_per_jiffy; -#endif -} diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c index 13664c377196441096f3a09b6de1d6eac9f410ec..3ee6609e6eb531ff966de820a80a6cd1a5eb3ef9 100644 --- a/arch/sparc/kernel/setup_32.c +++ b/arch/sparc/kernel/setup_32.c @@ -422,3 +422,10 @@ static int __init topology_init(void) } subsys_initcall(topology_init); + +#if defined(CONFIG_SPARC32) && !defined(CONFIG_SMP) +void __init arch_cpu_finalize_init(void) +{ + cpu_data(0).udelay_val = loops_per_jiffy; +} +#endif diff --git a/arch/um/Kconfig b/arch/um/Kconfig index 6b9938919f0bab07e46fefbe97b45c4cab663a8c..8f0cb28099392ea8975a34730ee0705c4d53c5c3 100644 --- a/arch/um/Kconfig +++ b/arch/um/Kconfig @@ -5,6 +5,7 @@ menu "UML-specific options" config UML bool default y + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_KCOV select ARCH_NO_PREEMPT select HAVE_ARCH_AUDITSYSCALL diff --git a/arch/um/configs/i386_defconfig b/arch/um/configs/i386_defconfig index 8f114e3b0a7a36143f79e9af98553ab09784f0bd..8d06b799a0e4efd7f1b343ce107fd29cd6ce0244 100644 --- a/arch/um/configs/i386_defconfig +++ b/arch/um/configs/i386_defconfig @@ -35,6 +35,7 @@ CONFIG_TTY_CHAN=y CONFIG_XTERM_CHAN=y CONFIG_CON_CHAN="pts" CONFIG_SSL_CHAN="pts" +CONFIG_SOUND=m CONFIG_UML_SOUND=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y diff --git a/arch/um/configs/x86_64_defconfig b/arch/um/configs/x86_64_defconfig index 4974b9d0ca8a366ac4ec899904c809e7262280b7..c3859f1f0d926778a6a6d38762e90555a4a8561d 100644 --- a/arch/um/configs/x86_64_defconfig +++ b/arch/um/configs/x86_64_defconfig @@ -33,6 +33,7 @@ CONFIG_TTY_CHAN=y CONFIG_XTERM_CHAN=y CONFIG_CON_CHAN="pts" CONFIG_SSL_CHAN="pts" +CONFIG_SOUND=m CONFIG_UML_SOUND=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y diff --git a/arch/um/drivers/Kconfig b/arch/um/drivers/Kconfig index 2b1aaf7755aac11a27e68fc0d08b7eab62e80fef..494f7c27056e32888a71e75161c7a955d42065b2 100644 --- a/arch/um/drivers/Kconfig +++ b/arch/um/drivers/Kconfig @@ -11,58 +11,58 @@ config STDERR_CONSOLE config SSL bool "Virtual serial line" help - The User-Mode Linux environment allows you to create virtual serial - lines on the UML that are usually made to show up on the host as - ttys or ptys. + The User-Mode Linux environment allows you to create virtual serial + lines on the UML that are usually made to show up on the host as + ttys or ptys. - See for more - information and command line examples of how to use this facility. + See for more + information and command line examples of how to use this facility. - Unless you have a specific reason for disabling this, say Y. + Unless you have a specific reason for disabling this, say Y. config NULL_CHAN bool "null channel support" help - This option enables support for attaching UML consoles and serial - lines to a device similar to /dev/null. Data written to it disappears - and there is never any data to be read. + This option enables support for attaching UML consoles and serial + lines to a device similar to /dev/null. Data written to it disappears + and there is never any data to be read. config PORT_CHAN bool "port channel support" help - This option enables support for attaching UML consoles and serial - lines to host portals. They may be accessed with 'telnet - '. Any number of consoles and serial lines may be - attached to a single portal, although what UML device you get when - you telnet to that portal will be unpredictable. - It is safe to say 'Y' here. + This option enables support for attaching UML consoles and serial + lines to host portals. They may be accessed with 'telnet + '. Any number of consoles and serial lines may be + attached to a single portal, although what UML device you get when + you telnet to that portal will be unpredictable. + It is safe to say 'Y' here. config PTY_CHAN bool "pty channel support" help - This option enables support for attaching UML consoles and serial - lines to host pseudo-terminals. Access to both traditional - pseudo-terminals (/dev/pty*) and pts pseudo-terminals are controlled - with this option. The assignment of UML devices to host devices - will be announced in the kernel message log. - It is safe to say 'Y' here. + This option enables support for attaching UML consoles and serial + lines to host pseudo-terminals. Access to both traditional + pseudo-terminals (/dev/pty*) and pts pseudo-terminals are controlled + with this option. The assignment of UML devices to host devices + will be announced in the kernel message log. + It is safe to say 'Y' here. config TTY_CHAN bool "tty channel support" help - This option enables support for attaching UML consoles and serial - lines to host terminals. Access to both virtual consoles - (/dev/tty*) and the slave side of pseudo-terminals (/dev/ttyp* and - /dev/pts/*) are controlled by this option. - It is safe to say 'Y' here. + This option enables support for attaching UML consoles and serial + lines to host terminals. Access to both virtual consoles + (/dev/tty*) and the slave side of pseudo-terminals (/dev/ttyp* and + /dev/pts/*) are controlled by this option. + It is safe to say 'Y' here. config XTERM_CHAN bool "xterm channel support" help - This option enables support for attaching UML consoles and serial - lines to xterms. Each UML device so assigned will be brought up in - its own xterm. - It is safe to say 'Y' here. + This option enables support for attaching UML consoles and serial + lines to xterms. Each UML device so assigned will be brought up in + its own xterm. + It is safe to say 'Y' here. config NOCONFIG_CHAN bool @@ -72,55 +72,45 @@ config CON_ZERO_CHAN string "Default main console channel initialization" default "fd:0,fd:1" help - This is the string describing the channel to which the main console - will be attached by default. This value can be overridden from the - command line. The default value is "fd:0,fd:1", which attaches the - main console to stdin and stdout. - It is safe to leave this unchanged. + This is the string describing the channel to which the main console + will be attached by default. This value can be overridden from the + command line. The default value is "fd:0,fd:1", which attaches the + main console to stdin and stdout. + It is safe to leave this unchanged. config CON_CHAN string "Default console channel initialization" default "xterm" help - This is the string describing the channel to which all consoles - except the main console will be attached by default. This value can - be overridden from the command line. The default value is "xterm", - which brings them up in xterms. - It is safe to leave this unchanged, although you may wish to change - this if you expect the UML that you build to be run in environments - which don't have X or xterm available. + This is the string describing the channel to which all consoles + except the main console will be attached by default. This value can + be overridden from the command line. The default value is "xterm", + which brings them up in xterms. + It is safe to leave this unchanged, although you may wish to change + this if you expect the UML that you build to be run in environments + which don't have X or xterm available. config SSL_CHAN string "Default serial line channel initialization" default "pty" help - This is the string describing the channel to which the serial lines - will be attached by default. This value can be overridden from the - command line. The default value is "pty", which attaches them to - traditional pseudo-terminals. - It is safe to leave this unchanged, although you may wish to change - this if you expect the UML that you build to be run in environments - which don't have a set of /dev/pty* devices. + This is the string describing the channel to which the serial lines + will be attached by default. This value can be overridden from the + command line. The default value is "pty", which attaches them to + traditional pseudo-terminals. + It is safe to leave this unchanged, although you may wish to change + this if you expect the UML that you build to be run in environments + which don't have a set of /dev/pty* devices. config UML_SOUND tristate "Sound support" + depends on SOUND + select SOUND_OSS_CORE help - This option enables UML sound support. If enabled, it will pull in - soundcore and the UML hostaudio relay, which acts as a intermediary - between the host's dsp and mixer devices and the UML sound system. - It is safe to say 'Y' here. - -config SOUND - tristate - default UML_SOUND - -config SOUND_OSS_CORE - bool - default UML_SOUND - -config HOSTAUDIO - tristate - default UML_SOUND + This option enables UML sound support. If enabled, it will pull in + the UML hostaudio relay, which acts as a intermediary + between the host's dsp and mixer devices and the UML sound system. + It is safe to say 'Y' here. endmenu @@ -131,107 +121,107 @@ menu "UML Network Devices" config UML_NET bool "Virtual network device" help - While the User-Mode port cannot directly talk to any physical - hardware devices, this choice and the following transport options - provide one or more virtual network devices through which the UML - kernels can talk to each other, the host, and with the host's help, - machines on the outside world. + While the User-Mode port cannot directly talk to any physical + hardware devices, this choice and the following transport options + provide one or more virtual network devices through which the UML + kernels can talk to each other, the host, and with the host's help, + machines on the outside world. - For more information, including explanations of the networking and - sample configurations, see - . + For more information, including explanations of the networking and + sample configurations, see + . - If you'd like to be able to enable networking in the User-Mode - linux environment, say Y; otherwise say N. Note that you must - enable at least one of the following transport options to actually - make use of UML networking. + If you'd like to be able to enable networking in the User-Mode + linux environment, say Y; otherwise say N. Note that you must + enable at least one of the following transport options to actually + make use of UML networking. config UML_NET_ETHERTAP bool "Ethertap transport" depends on UML_NET help - The Ethertap User-Mode Linux network transport allows a single - running UML to exchange packets with its host over one of the - host's Ethertap devices, such as /dev/tap0. Additional running - UMLs can use additional Ethertap devices, one per running UML. - While the UML believes it's on a (multi-device, broadcast) virtual - Ethernet network, it's in fact communicating over a point-to-point - link with the host. - - To use this, your host kernel must have support for Ethertap - devices. Also, if your host kernel is 2.4.x, it must have - CONFIG_NETLINK_DEV configured as Y or M. - - For more information, see - That site - has examples of the UML command line to use to enable Ethertap - networking. - - If you'd like to set up an IP network with the host and/or the - outside world, say Y to this, the Daemon Transport and/or the - Slip Transport. You'll need at least one of them, but may choose - more than one without conflict. If you don't need UML networking, - say N. + The Ethertap User-Mode Linux network transport allows a single + running UML to exchange packets with its host over one of the + host's Ethertap devices, such as /dev/tap0. Additional running + UMLs can use additional Ethertap devices, one per running UML. + While the UML believes it's on a (multi-device, broadcast) virtual + Ethernet network, it's in fact communicating over a point-to-point + link with the host. + + To use this, your host kernel must have support for Ethertap + devices. Also, if your host kernel is 2.4.x, it must have + CONFIG_NETLINK_DEV configured as Y or M. + + For more information, see + That site + has examples of the UML command line to use to enable Ethertap + networking. + + If you'd like to set up an IP network with the host and/or the + outside world, say Y to this, the Daemon Transport and/or the + Slip Transport. You'll need at least one of them, but may choose + more than one without conflict. If you don't need UML networking, + say N. config UML_NET_TUNTAP bool "TUN/TAP transport" depends on UML_NET help - The UML TUN/TAP network transport allows a UML instance to exchange - packets with the host over a TUN/TAP device. This option will only - work with a 2.4 host, unless you've applied the TUN/TAP patch to - your 2.2 host kernel. + The UML TUN/TAP network transport allows a UML instance to exchange + packets with the host over a TUN/TAP device. This option will only + work with a 2.4 host, unless you've applied the TUN/TAP patch to + your 2.2 host kernel. - To use this transport, your host kernel must have support for TUN/TAP - devices, either built-in or as a module. + To use this transport, your host kernel must have support for TUN/TAP + devices, either built-in or as a module. config UML_NET_SLIP bool "SLIP transport" depends on UML_NET help - The slip User-Mode Linux network transport allows a running UML to - network with its host over a point-to-point link. Unlike Ethertap, - which can carry any Ethernet frame (and hence even non-IP packets), - the slip transport can only carry IP packets. - - To use this, your host must support slip devices. - - For more information, see - . - has examples of the UML command line to use to enable slip - networking, and details of a few quirks with it. - - The Ethertap Transport is preferred over slip because of its - limitations. If you prefer slip, however, say Y here. Otherwise - choose the Multicast transport (to network multiple UMLs on - multiple hosts), Ethertap (to network with the host and the - outside world), and/or the Daemon transport (to network multiple - UMLs on a single host). You may choose more than one without - conflict. If you don't need UML networking, say N. + The slip User-Mode Linux network transport allows a running UML to + network with its host over a point-to-point link. Unlike Ethertap, + which can carry any Ethernet frame (and hence even non-IP packets), + the slip transport can only carry IP packets. + + To use this, your host must support slip devices. + + For more information, see + . + has examples of the UML command line to use to enable slip + networking, and details of a few quirks with it. + + The Ethertap Transport is preferred over slip because of its + limitations. If you prefer slip, however, say Y here. Otherwise + choose the Multicast transport (to network multiple UMLs on + multiple hosts), Ethertap (to network with the host and the + outside world), and/or the Daemon transport (to network multiple + UMLs on a single host). You may choose more than one without + conflict. If you don't need UML networking, say N. config UML_NET_DAEMON bool "Daemon transport" depends on UML_NET help - This User-Mode Linux network transport allows one or more running - UMLs on a single host to communicate with each other, but not to - the host. - - To use this form of networking, you'll need to run the UML - networking daemon on the host. - - For more information, see - That site - has examples of the UML command line to use to enable Daemon - networking. - - If you'd like to set up a network with other UMLs on a single host, - say Y. If you need a network between UMLs on multiple physical - hosts, choose the Multicast Transport. To set up a network with - the host and/or other IP machines, say Y to the Ethertap or Slip - transports. You'll need at least one of them, but may choose - more than one without conflict. If you don't need UML networking, - say N. + This User-Mode Linux network transport allows one or more running + UMLs on a single host to communicate with each other, but not to + the host. + + To use this form of networking, you'll need to run the UML + networking daemon on the host. + + For more information, see + That site + has examples of the UML command line to use to enable Daemon + networking. + + If you'd like to set up a network with other UMLs on a single host, + say Y. If you need a network between UMLs on multiple physical + hosts, choose the Multicast Transport. To set up a network with + the host and/or other IP machines, say Y to the Ethertap or Slip + transports. You'll need at least one of them, but may choose + more than one without conflict. If you don't need UML networking, + say N. config UML_NET_VECTOR bool "Vector I/O high performance network devices" @@ -270,26 +260,26 @@ config UML_NET_MCAST bool "Multicast transport" depends on UML_NET help - This Multicast User-Mode Linux network transport allows multiple - UMLs (even ones running on different host machines!) to talk to - each other over a virtual ethernet network. However, it requires - at least one UML with one of the other transports to act as a - bridge if any of them need to be able to talk to their hosts or any - other IP machines. - - To use this, your host kernel(s) must support IP Multicasting. - - For more information, see - That site - has examples of the UML command line to use to enable Multicast - networking, and notes about the security of this approach. - - If you need UMLs on multiple physical hosts to communicate as if - they shared an Ethernet network, say Y. If you need to communicate - with other IP machines, make sure you select one of the other - transports (possibly in addition to Multicast; they're not - exclusive). If you don't need to network UMLs say N to each of - the transports. + This Multicast User-Mode Linux network transport allows multiple + UMLs (even ones running on different host machines!) to talk to + each other over a virtual ethernet network. However, it requires + at least one UML with one of the other transports to act as a + bridge if any of them need to be able to talk to their hosts or any + other IP machines. + + To use this, your host kernel(s) must support IP Multicasting. + + For more information, see + That site + has examples of the UML command line to use to enable Multicast + networking, and notes about the security of this approach. + + If you need UMLs on multiple physical hosts to communicate as if + they shared an Ethernet network, say Y. If you need to communicate + with other IP machines, make sure you select one of the other + transports (possibly in addition to Multicast; they're not + exclusive). If you don't need to network UMLs say N to each of + the transports. config UML_NET_PCAP bool "pcap transport" @@ -300,9 +290,9 @@ config UML_NET_PCAP UML act as a network monitor for the host. You must have libcap installed in order to build the pcap transport into UML. - For more information, see - That site - has examples of the UML command line to use to enable this option. + For more information, see + That site + has examples of the UML command line to use to enable this option. If you intend to use UML as a network monitor for the host, say Y here. Otherwise, say N. @@ -311,27 +301,27 @@ config UML_NET_SLIRP bool "SLiRP transport" depends on UML_NET help - The SLiRP User-Mode Linux network transport allows a running UML - to network by invoking a program that can handle SLIP encapsulated - packets. This is commonly (but not limited to) the application - known as SLiRP, a program that can re-socket IP packets back onto - the host on which it is run. Only IP packets are supported, - unlike other network transports that can handle all Ethernet - frames. In general, slirp allows the UML the same IP connectivity - to the outside world that the host user is permitted, and unlike - other transports, SLiRP works without the need of root level - privleges, setuid binaries, or SLIP devices on the host. This - also means not every type of connection is possible, but most - situations can be accommodated with carefully crafted slirp - commands that can be passed along as part of the network device's - setup string. The effect of this transport on the UML is similar - that of a host behind a firewall that masquerades all network - connections passing through it (but is less secure). - - To use this you should first have slirp compiled somewhere - accessible on the host, and have read its documentation. If you - don't need UML networking, say N. - - Startup example: "eth0=slirp,FE:FD:01:02:03:04,/usr/local/bin/slirp" + The SLiRP User-Mode Linux network transport allows a running UML + to network by invoking a program that can handle SLIP encapsulated + packets. This is commonly (but not limited to) the application + known as SLiRP, a program that can re-socket IP packets back onto + he host on which it is run. Only IP packets are supported, + unlike other network transports that can handle all Ethernet + frames. In general, slirp allows the UML the same IP connectivity + to the outside world that the host user is permitted, and unlike + other transports, SLiRP works without the need of root level + privleges, setuid binaries, or SLIP devices on the host. This + also means not every type of connection is possible, but most + situations can be accommodated with carefully crafted slirp + commands that can be passed along as part of the network device's + setup string. The effect of this transport on the UML is similar + that of a host behind a firewall that masquerades all network + connections passing through it (but is less secure). + + To use this you should first have slirp compiled somewhere + accessible on the host, and have read its documentation. If you + don't need UML networking, say N. + + Startup example: "eth0=slirp,FE:FD:01:02:03:04,/usr/local/bin/slirp" endmenu diff --git a/arch/um/drivers/Makefile b/arch/um/drivers/Makefile index 693319839f69ec93083b03d3f267d92c85f7c4fb..d945abf90c3190bfd775f2161a7e5bad916fa657 100644 --- a/arch/um/drivers/Makefile +++ b/arch/um/drivers/Makefile @@ -52,7 +52,7 @@ obj-$(CONFIG_UML_NET) += net.o obj-$(CONFIG_MCONSOLE) += mconsole.o obj-$(CONFIG_MMAPPER) += mmapper_kern.o obj-$(CONFIG_BLK_DEV_UBD) += ubd.o -obj-$(CONFIG_HOSTAUDIO) += hostaudio.o +obj-$(CONFIG_UML_SOUND) += hostaudio.o obj-$(CONFIG_NULL_CHAN) += null.o obj-$(CONFIG_PORT_CHAN) += port.o obj-$(CONFIG_PTY_CHAN) += pty.o diff --git a/arch/um/drivers/vector_kern.c b/arch/um/drivers/vector_kern.c index 50ee3bb5a63a9eb950d76baeba475bcf7f0700b8..b0b124025b48604d11cd98f018bee83dd817f087 100644 --- a/arch/um/drivers/vector_kern.c +++ b/arch/um/drivers/vector_kern.c @@ -741,6 +741,7 @@ static int vector_config(char *str, char **error_out) if (parsed == NULL) { *error_out = "vector_config failed to parse parameters"; + kfree(params); return -EINVAL; } diff --git a/arch/um/include/asm/bugs.h b/arch/um/include/asm/bugs.h deleted file mode 100644 index 4473942a083973d85d590174900fd69250799e27..0000000000000000000000000000000000000000 --- a/arch/um/include/asm/bugs.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __UM_BUGS_H -#define __UM_BUGS_H - -void check_bugs(void); - -#endif diff --git a/arch/um/kernel/um_arch.c b/arch/um/kernel/um_arch.c index c23f8857a798b2df92f7fd20366c581a5155218f..66390c3211553672fd785484effe585f1da4faba 100644 --- a/arch/um/kernel/um_arch.c +++ b/arch/um/kernel/um_arch.c @@ -3,6 +3,7 @@ * Licensed under the GPL */ +#include #include #include #include @@ -352,7 +353,7 @@ void __init setup_arch(char **cmdline_p) setup_hostinfo(host_info, sizeof host_info); } -void __init check_bugs(void) +void __init arch_cpu_finalize_init(void) { arch_check_bugs(); os_check_bugs(); diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a12dc211399f440b866cbb9fcd2128a8167a6522..a51962df7bb14b1eca4c47a135eebae44428d4df 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -50,6 +50,7 @@ config X86 select ARCH_CLOCKSOURCE_DATA select ARCH_DISCARD_MEMBLOCK select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_DEBUG_VIRTUAL select ARCH_HAS_DEVMEM_IS_ALLOWED select ARCH_HAS_ELF_RANDOMIZE @@ -2440,6 +2441,25 @@ config ARCH_ENABLE_SPLIT_PMD_PTLOCK def_bool y depends on X86_64 || X86_PAE +config GDS_FORCE_MITIGATION + bool "Force GDS Mitigation" + depends on CPU_SUP_INTEL + default n + help + Gather Data Sampling (GDS) is a hardware vulnerability which allows + unprivileged speculative access to data which was previously stored in + vector registers. + + This option is equivalent to setting gather_data_sampling=force on the + command line. The microcode mitigation is used if present, otherwise + AVX is disabled as a mitigation. On affected systems that are missing + the microcode any userspace code that unconditionally uses AVX will + break with this option set. + + Setting this option on systems not vulnerable to GDS has no effect. + + If in doubt, say N. + config ARCH_ENABLE_HUGEPAGE_MIGRATION def_bool y depends on X86_64 && HUGETLB_PAGE && MIGRATION diff --git a/arch/x86/boot/boot.h b/arch/x86/boot/boot.h index ef5a9cc66fb82e296139b1b39559cc8adbb5b14b..a4c5fb92b1cba036a2da66b94a0d0526dfb7d990 100644 --- a/arch/x86/boot/boot.h +++ b/arch/x86/boot/boot.h @@ -114,66 +114,78 @@ typedef unsigned int addr_t; static inline u8 rdfs8(addr_t addr) { + u8 *ptr = (u8 *)absolute_pointer(addr); u8 v; - asm volatile("movb %%fs:%1,%0" : "=q" (v) : "m" (*(u8 *)addr)); + asm volatile("movb %%fs:%1,%0" : "=q" (v) : "m" (*ptr)); return v; } static inline u16 rdfs16(addr_t addr) { + u16 *ptr = (u16 *)absolute_pointer(addr); u16 v; - asm volatile("movw %%fs:%1,%0" : "=r" (v) : "m" (*(u16 *)addr)); + asm volatile("movw %%fs:%1,%0" : "=r" (v) : "m" (*ptr)); return v; } static inline u32 rdfs32(addr_t addr) { + u32 *ptr = (u32 *)absolute_pointer(addr); u32 v; - asm volatile("movl %%fs:%1,%0" : "=r" (v) : "m" (*(u32 *)addr)); + asm volatile("movl %%fs:%1,%0" : "=r" (v) : "m" (*ptr)); return v; } static inline void wrfs8(u8 v, addr_t addr) { - asm volatile("movb %1,%%fs:%0" : "+m" (*(u8 *)addr) : "qi" (v)); + u8 *ptr = (u8 *)absolute_pointer(addr); + asm volatile("movb %1,%%fs:%0" : "+m" (*ptr) : "qi" (v)); } static inline void wrfs16(u16 v, addr_t addr) { - asm volatile("movw %1,%%fs:%0" : "+m" (*(u16 *)addr) : "ri" (v)); + u16 *ptr = (u16 *)absolute_pointer(addr); + asm volatile("movw %1,%%fs:%0" : "+m" (*ptr) : "ri" (v)); } static inline void wrfs32(u32 v, addr_t addr) { - asm volatile("movl %1,%%fs:%0" : "+m" (*(u32 *)addr) : "ri" (v)); + u32 *ptr = (u32 *)absolute_pointer(addr); + asm volatile("movl %1,%%fs:%0" : "+m" (*ptr) : "ri" (v)); } static inline u8 rdgs8(addr_t addr) { + u8 *ptr = (u8 *)absolute_pointer(addr); u8 v; - asm volatile("movb %%gs:%1,%0" : "=q" (v) : "m" (*(u8 *)addr)); + asm volatile("movb %%gs:%1,%0" : "=q" (v) : "m" (*ptr)); return v; } static inline u16 rdgs16(addr_t addr) { + u16 *ptr = (u16 *)absolute_pointer(addr); u16 v; - asm volatile("movw %%gs:%1,%0" : "=r" (v) : "m" (*(u16 *)addr)); + asm volatile("movw %%gs:%1,%0" : "=r" (v) : "m" (*ptr)); return v; } static inline u32 rdgs32(addr_t addr) { + u32 *ptr = (u32 *)absolute_pointer(addr); u32 v; - asm volatile("movl %%gs:%1,%0" : "=r" (v) : "m" (*(u32 *)addr)); + asm volatile("movl %%gs:%1,%0" : "=r" (v) : "m" (*ptr)); return v; } static inline void wrgs8(u8 v, addr_t addr) { - asm volatile("movb %1,%%gs:%0" : "+m" (*(u8 *)addr) : "qi" (v)); + u8 *ptr = (u8 *)absolute_pointer(addr); + asm volatile("movb %1,%%gs:%0" : "+m" (*ptr) : "qi" (v)); } static inline void wrgs16(u16 v, addr_t addr) { - asm volatile("movw %1,%%gs:%0" : "+m" (*(u16 *)addr) : "ri" (v)); + u16 *ptr = (u16 *)absolute_pointer(addr); + asm volatile("movw %1,%%gs:%0" : "+m" (*ptr) : "ri" (v)); } static inline void wrgs32(u32 v, addr_t addr) { - asm volatile("movl %1,%%gs:%0" : "+m" (*(u32 *)addr) : "ri" (v)); + u32 *ptr = (u32 *)absolute_pointer(addr); + asm volatile("movl %1,%%gs:%0" : "+m" (*ptr) : "ri" (v)); } /* Note: these only return true/false, not a signed return value! */ diff --git a/arch/x86/boot/main.c b/arch/x86/boot/main.c index 9bcea386db65e3bbce1db97a8b7254249fd89ed7..98b4ff1c51f350e942a2e2b271769073f78046a9 100644 --- a/arch/x86/boot/main.c +++ b/arch/x86/boot/main.c @@ -34,7 +34,7 @@ static void copy_boot_params(void) u16 cl_offset; }; const struct old_cmdline * const oldcmd = - (const struct old_cmdline *)OLD_CL_ADDRESS; + absolute_pointer(OLD_CL_ADDRESS); BUILD_BUG_ON(sizeof boot_params != 4096); memcpy(&boot_params.hdr, &hdr, sizeof hdr); diff --git a/arch/x86/entry/vdso/vma.c b/arch/x86/entry/vdso/vma.c index 47817937fd6e66f57c5b2303caa711d80244a0c8..a6ff2ebc8aca3cf26674ddce61bbf10a2a410ca6 100644 --- a/arch/x86/entry/vdso/vma.c +++ b/arch/x86/entry/vdso/vma.c @@ -228,8 +228,8 @@ static unsigned long vdso_addr(unsigned long start, unsigned len) /* Round the lowest possible end address up to a PMD boundary. */ end = (start + len + PMD_SIZE - 1) & PMD_MASK; - if (end >= TASK_SIZE_MAX) - end = TASK_SIZE_MAX; + if (end >= DEFAULT_MAP_WINDOW) + end = DEFAULT_MAP_WINDOW; end -= len; if (end > start) { diff --git a/arch/x86/include/asm/bugs.h b/arch/x86/include/asm/bugs.h index 542509b53e0f5f1f0d6b8d65fc5b82dd5305fb32..dd8ff1ca2aef416573a853b76a871b046e70b46b 100644 --- a/arch/x86/include/asm/bugs.h +++ b/arch/x86/include/asm/bugs.h @@ -4,8 +4,6 @@ #include -extern void check_bugs(void); - #if defined(CONFIG_CPU_SUP_INTEL) void check_mpx_erratum(struct cpuinfo_x86 *c); #else diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index bd4374f56651b535e31f8180098b34704a83ab38..5cf8dca571cfda75b7111c30f36c86ac8b37fcaa 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -409,5 +409,6 @@ #define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */ #define X86_BUG_RETBLEED X86_BUG(27) /* CPU is affected by RETBleed */ #define X86_BUG_EIBRS_PBRSB X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */ +#define X86_BUG_GDS X86_BUG(29) /* CPU is affected by Gather Data Sampling */ #endif /* _ASM_X86_CPUFEATURES_H */ diff --git a/arch/x86/include/asm/fpu/internal.h b/arch/x86/include/asm/fpu/internal.h index 4f274d8519865bc09d7fdaaee2737664015961d7..51dc8201b51eb3ffdc9ae5f5f150d7a9d5cda53f 100644 --- a/arch/x86/include/asm/fpu/internal.h +++ b/arch/x86/include/asm/fpu/internal.h @@ -42,7 +42,7 @@ extern int dump_fpu(struct pt_regs *ptregs, struct user_i387_struct *fpstate); extern void fpu__init_cpu(void); extern void fpu__init_system_xstate(void); extern void fpu__init_cpu_xstate(void); -extern void fpu__init_system(struct cpuinfo_x86 *c); +extern void fpu__init_system(void); extern void fpu__init_check_bugs(void); extern void fpu__resume_cpu(void); extern u64 fpu__get_supported_xfeatures_mask(void); diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h index 89789e8c80f66a97db08ffad891ed26e5025219e..e16574c16e9332f2613cfd8ae02a01d73a657fba 100644 --- a/arch/x86/include/asm/i8259.h +++ b/arch/x86/include/asm/i8259.h @@ -67,6 +67,8 @@ struct legacy_pic { void (*make_irq)(unsigned int irq); }; +void legacy_pic_pcat_compat(void); + extern struct legacy_pic *legacy_pic; extern struct legacy_pic null_legacy_pic; diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 1f2f52a340868893454fa2848ce35b4dbf4d72ac..ccf07426a84dfa2315512fc35f56bd9ac8655a38 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -74,6 +74,11 @@ #define INTEL_FAM6_LAKEFIELD 0x8A #define INTEL_FAM6_ALDERLAKE 0x97 #define INTEL_FAM6_ALDERLAKE_L 0x9A +#define INTEL_FAM6_ALDERLAKE_N 0xBE + +#define INTEL_FAM6_RAPTORLAKE 0xB7 +#define INTEL_FAM6_RAPTORLAKE_P 0xBA +#define INTEL_FAM6_RAPTORLAKE_S 0xBF /* "Small Core" Processors (Atom) */ diff --git a/arch/x86/include/asm/mem_encrypt.h b/arch/x86/include/asm/mem_encrypt.h index 616f8e637bc32c2bd48dfc9964c6e94cb6cbc2cb..b51ac6eed904edb659bfd76f1a6aae4ca05085a0 100644 --- a/arch/x86/include/asm/mem_encrypt.h +++ b/arch/x86/include/asm/mem_encrypt.h @@ -80,6 +80,8 @@ early_set_memory_decrypted(unsigned long vaddr, unsigned long size) { return 0; static inline int __init early_set_memory_encrypted(unsigned long vaddr, unsigned long size) { return 0; } +static inline void mem_encrypt_init(void) { } + #define __bss_decrypted #endif /* CONFIG_AMD_MEM_ENCRYPT */ diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index 91a06cef50c1b85bd3628b93fe13ef54db06ff73..b675db12a8ab4e9443f7e783a84311fa72cf5d49 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -5,6 +5,7 @@ #include #include #include +#include struct ucode_patch { struct list_head plist; @@ -130,7 +131,7 @@ static inline unsigned int x86_cpuid_family(void) int __init microcode_init(void); extern void __init load_ucode_bsp(void); extern void load_ucode_ap(void); -void reload_early_microcode(void); +void reload_early_microcode(unsigned int cpu); extern bool get_builtin_firmware(struct cpio_data *cd, const char *name); extern bool initrd_gone; void microcode_bsp_resume(void); @@ -138,7 +139,7 @@ void microcode_bsp_resume(void); static inline int __init microcode_init(void) { return 0; }; static inline void __init load_ucode_bsp(void) { } static inline void load_ucode_ap(void) { } -static inline void reload_early_microcode(void) { } +static inline void reload_early_microcode(unsigned int cpu) { } static inline void microcode_bsp_resume(void) { } static inline bool get_builtin_firmware(struct cpio_data *cd, const char *name) { return false; } diff --git a/arch/x86/include/asm/microcode_amd.h b/arch/x86/include/asm/microcode_amd.h index 5c524d4f71cd7b2a99b7037f7962e334f227a94c..403a8e76b310c619d92db56226788a4d3237d258 100644 --- a/arch/x86/include/asm/microcode_amd.h +++ b/arch/x86/include/asm/microcode_amd.h @@ -47,12 +47,14 @@ struct microcode_amd { extern void __init load_ucode_amd_bsp(unsigned int family); extern void load_ucode_amd_ap(unsigned int family); extern int __init save_microcode_in_initrd_amd(unsigned int family); -void reload_ucode_amd(void); +void reload_ucode_amd(unsigned int cpu); +extern void amd_check_microcode(void); #else static inline void __init load_ucode_amd_bsp(unsigned int family) {} static inline void load_ucode_amd_ap(unsigned int family) {} static inline int __init save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; } -void reload_ucode_amd(void) {} +static inline void reload_ucode_amd(unsigned int cpu) {} +static inline void amd_check_microcode(void) {} #endif #endif /* _ASM_X86_MICROCODE_AMD_H */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 0bd07699dba38ea076b46af7eeb2998d75802669..4be36bfb2477caac9e6902ef5a3533fef1a97685 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -50,6 +50,10 @@ #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) +/* A mask for bits which the kernel toggles when controlling mitigations */ +#define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ + | SPEC_CTRL_RRSBA_DIS_S) + #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ @@ -134,6 +138,15 @@ * Not susceptible to Post-Barrier * Return Stack Buffer Predictions. */ +#define ARCH_CAP_GDS_CTRL BIT(25) /* + * CPU is vulnerable to Gather + * Data Sampling (GDS) and + * has controls for mitigation. + */ +#define ARCH_CAP_GDS_NO BIT(26) /* + * CPU is not vulnerable to Gather + * Data Sampling (GDS). + */ #define MSR_IA32_FLUSH_CMD 0x0000010b #define L1D_FLUSH BIT(0) /* @@ -152,6 +165,8 @@ #define MSR_IA32_MCU_OPT_CTRL 0x00000123 #define RNGDS_MITG_DIS BIT(0) #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ +#define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */ +#define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */ #define MSR_IA32_SYSENTER_CS 0x00000174 #define MSR_IA32_SYSENTER_ESP 0x00000175 @@ -399,10 +414,12 @@ #define MSR_AMD64_OSVW_STATUS 0xc0010141 #define MSR_AMD64_LS_CFG 0xc0011020 #define MSR_AMD64_DC_CFG 0xc0011022 +#define MSR_AMD64_TW_CFG 0xc0011023 #define MSR_AMD64_DE_CFG 0xc0011029 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) +#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9 #define MSR_AMD64_BU_CFG2 0xc001102a #define MSR_AMD64_IBSFETCHCTL 0xc0011030 @@ -430,6 +447,10 @@ #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f +/* Zen4 */ +#define MSR_ZEN4_BP_CFG 0xc001102e +#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 + /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9 diff --git a/arch/x86/include/asm/numa.h b/arch/x86/include/asm/numa.h index bbfde3d2662f4f2254a4604e9eac5efdd11e95f3..4bcd9d0c7bee72303d5b5645c3366a7df67af698 100644 --- a/arch/x86/include/asm/numa.h +++ b/arch/x86/include/asm/numa.h @@ -11,13 +11,6 @@ #define NR_NODE_MEMBLKS (MAX_NUMNODES*2) -/* - * Too small node sizes may confuse the VM badly. Usually they - * result from BIOS bugs. So dont recognize nodes as standalone - * NUMA entities that have less than this amount of RAM listed: - */ -#define NODE_MIN_SIZE (4*1024*1024) - extern int numa_off; /* diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index aa26fe007e15c87927e7f4de1743a2b27291d0e7..a8babad935ecb366daa475a487a5410a5a479b2e 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -991,4 +991,6 @@ enum taa_mitigations { TAA_MITIGATION_TSX_DISABLED, }; +extern bool gds_ucode_mitigated(void); + #endif /* _ASM_X86_PROCESSOR_H */ diff --git a/arch/x86/include/asm/reboot.h b/arch/x86/include/asm/reboot.h index a671a1145906db8b0d18e24d608c53afc395a1ef..9177b4354c3f50b2c1ff7f5f454abcace0a98a60 100644 --- a/arch/x86/include/asm/reboot.h +++ b/arch/x86/include/asm/reboot.h @@ -25,6 +25,8 @@ void __noreturn machine_real_restart(unsigned int type); #define MRR_BIOS 0 #define MRR_APM 1 +void cpu_emergency_disable_virtualization(void); + typedef void (*nmi_shootdown_cb)(int, struct pt_regs*); void nmi_shootdown_cpus(nmi_shootdown_cb callback); void run_crash_ipi_callback(struct pt_regs *regs); diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h index 9490cb15a275ac1ee539cb73e60e6e8d9a7d3c4b..8dd2a5ec5231317e4b95608d012f1c566893fddf 100644 --- a/arch/x86/include/asm/setup.h +++ b/arch/x86/include/asm/setup.h @@ -91,27 +91,16 @@ extern unsigned long _brk_end; void *extend_brk(size_t size, size_t align); /* - * Reserve space in the brk section. The name must be unique within - * the file, and somewhat descriptive. The size is in bytes. Must be - * used at file scope. + * Reserve space in the .brk section, which is a block of memory from which the + * caller is allowed to allocate very early (before even memblock is available) + * by calling extend_brk(). All allocated memory will be eventually converted + * to memblock. Any leftover unallocated memory will be freed. * - * (This uses a temp function to wrap the asm so we can pass it the - * size parameter; otherwise we wouldn't be able to. We can't use a - * "section" attribute on a normal variable because it always ends up - * being @progbits, which ends up allocating space in the vmlinux - * executable.) + * The size is in bytes. */ -#define RESERVE_BRK(name,sz) \ - static void __section(.discard.text) __used notrace \ - __brk_reservation_fn_##name##__(void) { \ - asm volatile ( \ - ".pushsection .brk_reservation,\"aw\",@nobits;" \ - ".brk." #name ":" \ - " 1:.skip %c0;" \ - " .size .brk." #name ", . - 1b;" \ - " .popsection" \ - : : "i" (sz)); \ - } +#define RESERVE_BRK(name, size) \ + __section(.bss..brk) __aligned(1) __used \ + static char __brk_##name[size] /* Helper for reserving space for arrays of things */ #define RESERVE_BRK_ARRAY(type, name, entries) \ @@ -129,12 +118,19 @@ asmlinkage void __init x86_64_start_reservations(char *real_mode_data); #endif /* __i386__ */ #endif /* _SETUP */ -#else -#define RESERVE_BRK(name,sz) \ - .pushsection .brk_reservation,"aw",@nobits; \ -.brk.name: \ -1: .skip sz; \ - .size .brk.name,.-1b; \ + +#else /* __ASSEMBLY */ + +.macro __RESERVE_BRK name, size + .pushsection .bss..brk, "aw" +GLOBAL(__brk_\name) + .skip \size +END(__brk_\name) .popsection +.endm + +#define RESERVE_BRK(name, size) __RESERVE_BRK name, size + #endif /* __ASSEMBLY__ */ + #endif /* _ASM_X86_SETUP_H */ diff --git a/arch/x86/include/asm/virtext.h b/arch/x86/include/asm/virtext.h index 0116b2ee9e64f34ebf612a0380410af39b4dd2e5..62810550024d358a33061f3705ee2ddc2ecf081f 100644 --- a/arch/x86/include/asm/virtext.h +++ b/arch/x86/include/asm/virtext.h @@ -89,12 +89,6 @@ static inline int cpu_has_svm(const char **msg) return 0; } - if (boot_cpu_data.extended_cpuid_level < SVM_CPUID_FUNC) { - if (msg) - *msg = "can't execute cpuid_8000000a"; - return 0; - } - if (!boot_cpu_has(X86_FEATURE_SVM)) { if (msg) *msg = "svm not available"; @@ -114,7 +108,21 @@ static inline void cpu_svm_disable(void) wrmsrl(MSR_VM_HSAVE_PA, 0); rdmsrl(MSR_EFER, efer); - wrmsrl(MSR_EFER, efer & ~EFER_SVME); + if (efer & EFER_SVME) { + /* + * Force GIF=1 prior to disabling SVM to ensure INIT and NMI + * aren't blocked, e.g. if a fatal error occurred between CLGI + * and STGI. Note, STGI may #UD if SVM is disabled from NMI + * context between reading EFER and executing STGI. In that + * case, GIF must already be set, otherwise the NMI would have + * been blocked, so just eat the fault. + */ + asm_volatile_goto("1: stgi\n\t" + _ASM_EXTABLE(1b, %l[fault]) + ::: "memory" : fault); +fault: + wrmsrl(MSR_EFER, efer & ~EFER_SVME); + } } /** Makes sure SVM is disabled, if it is supported on the CPU diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 8b1aa1206d9804e9710ec558627c4d932ce3653d..2f0fa294d6176712d478abcb190f4d6a8bf9e3f8 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -156,6 +156,9 @@ static int __init acpi_parse_madt(struct acpi_table_header *table) madt->address); } + if (madt->flags & ACPI_MADT_PCAT_COMPAT) + legacy_pic_pcat_compat(); + default_acpi_madt_oem_check(madt->header.oem_id, madt->header.oem_table_id); diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index 918a23704c0c5b487050da26801e26aef55e01a5..dee94961a667ab85940f8861cdb6cf1d5c45fb0d 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c @@ -366,6 +366,17 @@ void __init_or_module noinline apply_alternatives(struct alt_instr *start, u8 insnbuf[MAX_PATCH_LEN]; DPRINTK("alt table %px, -> %px", start, end); + + /* + * In the case CONFIG_X86_5LEVEL=y, KASAN_SHADOW_START is defined using + * cpu_feature_enabled(X86_FEATURE_LA57) and is therefore patched here. + * During the process, KASAN becomes confused seeing partial LA57 + * conversion and triggers a false-positive out-of-bound report. + * + * Disable KASAN until the patching is complete. + */ + kasan_disable_current(); + /* * The scan order should be from start to end. A later scanned * alternative code can overwrite previously scanned alternative code. @@ -426,6 +437,8 @@ void __init_or_module noinline apply_alternatives(struct alt_instr *start, text_poke_early(instr, insnbuf, insnbuf_sz); } + + kasan_enable_current(); } #ifdef CONFIG_SMP diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 926939978c1c3cbb50e534192b14afd99181b2c0..9318fe7d850e3970a4ec64171be215a524c44bdf 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -403,10 +403,9 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new) if (vector && !eilvt_entry_is_changeable(vector, new)) /* may not change if vectors are different */ return rsvd; - rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); - } while (rsvd != new); + } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new)); - rsvd &= ~APIC_EILVT_MASKED; + rsvd = new & ~APIC_EILVT_MASKED; if (rsvd && rsvd != vector) pr_info("LVT offset %d assigned for vector 0x%02x\n", offset, rsvd); diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 677508baf95a06e686538d8220e7533ceecf1124..af59aa9c55233cb530f3bfa559653f261b22a8ff 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -2449,17 +2449,21 @@ static int io_apic_get_redir_entries(int ioapic) unsigned int arch_dynirq_lower_bound(unsigned int from) { + unsigned int ret; + /* * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use * gsi_top if ioapic_dynirq_base hasn't been initialized yet. */ - if (!ioapic_initialized) - return gsi_top; + ret = ioapic_dynirq_base ? : gsi_top; + /* - * For DT enabled machines ioapic_dynirq_base is irrelevant and not - * updated. So simply return @from if ioapic_dynirq_base == 0. + * For DT enabled machines ioapic_dynirq_base is irrelevant and + * always 0. gsi_top can be 0 if there is no IO/APIC registered. + * 0 is an invalid interrupt number for dynamic allocations. Return + * @from instead. */ - return ioapic_dynirq_base ? : from; + return ret ? : from; } #ifdef CONFIG_X86_32 diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c index 8e70c2ba21b3d273d1ce60e6de469229b3e8120d..fb17767552ef4977bbed01d5d68ad0fa107a382d 100644 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -102,7 +102,10 @@ static void init_x2apic_ldr(void) static int x2apic_phys_probe(void) { - if (x2apic_mode && (x2apic_phys || x2apic_fadt_phys())) + if (!x2apic_mode) + return 0; + + if (x2apic_phys || x2apic_fadt_phys()) return 1; return apic == &apic_x2apic_phys; diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c index f7151cd03cb08145a5c596d28c676abaf8e1f1bf..3d7a8049f63761d24e0d4373f2d1be5dd493a849 100644 --- a/arch/x86/kernel/apm_32.c +++ b/arch/x86/kernel/apm_32.c @@ -246,12 +246,6 @@ extern int (*console_blank_hook)(int); #endif -/* - * The apm_bios device is one of the misc char devices. - * This is its minor number. - */ -#define APM_MINOR_DEV 134 - /* * Various options can be changed at boot time as follows: * (We allow underscores for compatibility with the modules code) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index e017f64e09d60fdb083fd8ed50d605180563e384..dc41d4d7836e337191d508a01559161f8fbbaa05 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -23,11 +23,6 @@ #include "cpu.h" -static const int amd_erratum_383[]; -static const int amd_erratum_400[]; -static const int amd_erratum_1054[]; -static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); - /* * nodes_per_socket: Stores the number of nodes per socket. * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX @@ -35,6 +30,83 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); */ static u32 nodes_per_socket = 1; +/* + * AMD errata checking + * + * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or + * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that + * have an OSVW id assigned, which it takes as first argument. Both take a + * variable number of family-specific model-stepping ranges created by + * AMD_MODEL_RANGE(). + * + * Example: + * + * const int amd_erratum_319[] = + * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), + * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), + * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); + */ + +#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } +#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } +#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ + ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) +#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) +#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) +#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) + +static const int amd_erratum_400[] = + AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), + AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); + +static const int amd_erratum_383[] = + AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); + +/* #1054: Instructions Retired Performance Counter May Be Inaccurate */ +static const int amd_erratum_1054[] = + AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf)); + +static const int amd_zenbleed[] = + AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf), + AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf), + AMD_MODEL_RANGE(0x17, 0x90, 0x0, 0x91, 0xf), + AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf)); + +static const int amd_erratum_1485[] = + AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf), + AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf)); + +static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) +{ + int osvw_id = *erratum++; + u32 range; + u32 ms; + + if (osvw_id >= 0 && osvw_id < 65536 && + cpu_has(cpu, X86_FEATURE_OSVW)) { + u64 osvw_len; + + rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); + if (osvw_id < osvw_len) { + u64 osvw_bits; + + rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), + osvw_bits); + return osvw_bits & (1ULL << (osvw_id & 0x3f)); + } + } + + /* OSVW unavailable or ID unknown, match family-model-stepping range */ + ms = (cpu->x86_model << 4) | cpu->x86_stepping; + while ((range = *erratum++)) + if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && + (ms >= AMD_MODEL_RANGE_START(range)) && + (ms <= AMD_MODEL_RANGE_END(range))) + return true; + + return false; +} + static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) { u32 gprs[8] = { 0 }; @@ -199,6 +271,15 @@ static void init_amd_k6(struct cpuinfo_x86 *c) return; } #endif + /* + * Work around Erratum 1386. The XSAVES instruction malfunctions in + * certain circumstances on Zen1/2 uarch, and not all parts have had + * updated microcode at the time of writing (March 2023). + * + * Affected parts all have no supervisor XSAVE states, meaning that + * the XSAVEC instruction (which works fine) is equivalent. + */ + clear_cpu_cap(c, X86_FEATURE_XSAVES); } static void init_amd_k7(struct cpuinfo_x86 *c) @@ -900,6 +981,47 @@ static void init_amd_zn(struct cpuinfo_x86 *c) } } +static bool cpu_has_zenbleed_microcode(void) +{ + u32 good_rev = 0; + + switch (boot_cpu_data.x86_model) { + case 0x30 ... 0x3f: good_rev = 0x0830107a; break; + case 0x60 ... 0x67: good_rev = 0x0860010b; break; + case 0x68 ... 0x6f: good_rev = 0x08608105; break; + case 0x70 ... 0x7f: good_rev = 0x08701032; break; + case 0xa0 ... 0xaf: good_rev = 0x08a00008; break; + + default: + return false; + break; + } + + if (boot_cpu_data.microcode < good_rev) + return false; + + return true; +} + +static void zenbleed_check(struct cpuinfo_x86 *c) +{ + if (!cpu_has_amd_erratum(c, amd_zenbleed)) + return; + + if (cpu_has(c, X86_FEATURE_HYPERVISOR)) + return; + + if (!cpu_has(c, X86_FEATURE_AVX)) + return; + + if (!cpu_has_zenbleed_microcode()) { + pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n"); + msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); + } else { + msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); + } +} + static void init_amd(struct cpuinfo_x86 *c) { early_init_amd(c); @@ -1002,6 +1124,12 @@ static void init_amd(struct cpuinfo_x86 *c) msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); check_null_seg_clears_base(c); + + zenbleed_check(c); + + if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && + cpu_has_amd_erratum(c, amd_erratum_1485)) + msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT); } #ifdef CONFIG_X86_32 @@ -1097,73 +1225,6 @@ static const struct cpu_dev amd_cpu_dev = { cpu_dev_register(amd_cpu_dev); -/* - * AMD errata checking - * - * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or - * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that - * have an OSVW id assigned, which it takes as first argument. Both take a - * variable number of family-specific model-stepping ranges created by - * AMD_MODEL_RANGE(). - * - * Example: - * - * const int amd_erratum_319[] = - * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), - * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), - * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); - */ - -#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } -#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } -#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ - ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) -#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) -#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) -#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) - -static const int amd_erratum_400[] = - AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), - AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); - -static const int amd_erratum_383[] = - AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); - -/* #1054: Instructions Retired Performance Counter May Be Inaccurate */ -static const int amd_erratum_1054[] = - AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf)); - -static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) -{ - int osvw_id = *erratum++; - u32 range; - u32 ms; - - if (osvw_id >= 0 && osvw_id < 65536 && - cpu_has(cpu, X86_FEATURE_OSVW)) { - u64 osvw_len; - - rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); - if (osvw_id < osvw_len) { - u64 osvw_bits; - - rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), - osvw_bits); - return osvw_bits & (1ULL << (osvw_id & 0x3f)); - } - } - - /* OSVW unavailable or ID unknown, match family-model-stepping range */ - ms = (cpu->x86_model << 4) | cpu->x86_stepping; - while ((range = *erratum++)) - if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && - (ms >= AMD_MODEL_RANGE_START(range)) && - (ms <= AMD_MODEL_RANGE_END(range))) - return true; - - return false; -} - void set_dr_addr_mask(unsigned long mask, int dr) { if (!boot_cpu_has(X86_FEATURE_BPEXT)) @@ -1182,3 +1243,15 @@ void set_dr_addr_mask(unsigned long mask, int dr) break; } } + +static void zenbleed_check_cpu(void *unused) +{ + struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); + + zenbleed_check(c); +} + +void amd_check_microcode(void) +{ + on_each_cpu(zenbleed_check_cpu, NULL, 1); +} diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index e298ec9d5d53655419f52633ec3cf0c505ee915f..6e1acbdd27a50901225895f4bb6a8c3d38ae5a00 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -9,7 +9,6 @@ * - Andrew D. Balsa (code cleanup). */ #include -#include #include #include #include @@ -25,9 +24,7 @@ #include #include #include -#include #include -#include #include #include #include @@ -47,6 +44,7 @@ static void __init md_clear_select_mitigation(void); static void __init taa_select_mitigation(void); static void __init mmio_select_mitigation(void); static void __init srbds_select_mitigation(void); +static void __init gds_select_mitigation(void); /* The base value of the SPEC_CTRL MSR without task-specific bits set */ u64 x86_spec_ctrl_base; @@ -115,29 +113,24 @@ EXPORT_SYMBOL_GPL(mds_idle_clear); DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear); EXPORT_SYMBOL_GPL(mmio_stale_data_clear); -void __init check_bugs(void) +void __init cpu_select_mitigations(void) { - identify_boot_cpu(); - - /* - * identify_boot_cpu() initialized SMT support information, let the - * core code know. - */ - cpu_smt_check_topology(); - - if (!IS_ENABLED(CONFIG_SMP)) { - pr_info("CPU: "); - print_cpu_info(&boot_cpu_data); - } - /* * Read the SPEC_CTRL MSR to account for reserved bits which may * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD * init code as it is not enumerated and depends on the family. */ - if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) + if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) { rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); + /* + * Previously running kernel (kexec), may have some controls + * turned ON. Clear them and let the mitigations setup below + * rediscover them based on configuration. + */ + x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK; + } + /* Select the proper CPU mitigations before patching alternatives: */ spectre_v1_select_mitigation(); spectre_v2_select_mitigation(); @@ -157,39 +150,7 @@ void __init check_bugs(void) l1tf_select_mitigation(); md_clear_select_mitigation(); srbds_select_mitigation(); - - arch_smt_update(); - -#ifdef CONFIG_X86_32 - /* - * Check whether we are able to run this kernel safely on SMP. - * - * - i386 is no longer supported. - * - In order to run on anything without a TSC, we need to be - * compiled for a i486. - */ - if (boot_cpu_data.x86 < 4) - panic("Kernel requires i486+ for 'invlpg' and other features"); - - init_utsname()->machine[1] = - '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); - alternative_instructions(); - - fpu__init_check_bugs(); -#else /* CONFIG_X86_64 */ - alternative_instructions(); - - /* - * Make sure the first 2MB area is not mapped by huge pages - * There are typically fixed size MTRRs in there and overlapping - * MTRRs into large pages causes slow downs. - * - * Right now we don't do that with gbpages because there seems - * very little benefit for that case. - */ - if (!direct_gbpages) - set_memory_4k((unsigned long)__va(0), 1); -#endif + gds_select_mitigation(); } /* @@ -640,6 +601,149 @@ static int __init srbds_parse_cmdline(char *str) } early_param("srbds", srbds_parse_cmdline); +#undef pr_fmt +#define pr_fmt(fmt) "GDS: " fmt + +enum gds_mitigations { + GDS_MITIGATION_OFF, + GDS_MITIGATION_UCODE_NEEDED, + GDS_MITIGATION_FORCE, + GDS_MITIGATION_FULL, + GDS_MITIGATION_FULL_LOCKED, + GDS_MITIGATION_HYPERVISOR, +}; + +#if IS_ENABLED(CONFIG_GDS_FORCE_MITIGATION) +static enum gds_mitigations gds_mitigation __ro_after_init = GDS_MITIGATION_FORCE; +#else +static enum gds_mitigations gds_mitigation __ro_after_init = GDS_MITIGATION_FULL; +#endif + +static const char * const gds_strings[] = { + [GDS_MITIGATION_OFF] = "Vulnerable", + [GDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", + [GDS_MITIGATION_FORCE] = "Mitigation: AVX disabled, no microcode", + [GDS_MITIGATION_FULL] = "Mitigation: Microcode", + [GDS_MITIGATION_FULL_LOCKED] = "Mitigation: Microcode (locked)", + [GDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status", +}; + +bool gds_ucode_mitigated(void) +{ + return (gds_mitigation == GDS_MITIGATION_FULL || + gds_mitigation == GDS_MITIGATION_FULL_LOCKED); +} +EXPORT_SYMBOL_GPL(gds_ucode_mitigated); + +void update_gds_msr(void) +{ + u64 mcu_ctrl_after; + u64 mcu_ctrl; + + switch (gds_mitigation) { + case GDS_MITIGATION_OFF: + rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); + mcu_ctrl |= GDS_MITG_DIS; + break; + case GDS_MITIGATION_FULL_LOCKED: + /* + * The LOCKED state comes from the boot CPU. APs might not have + * the same state. Make sure the mitigation is enabled on all + * CPUs. + */ + case GDS_MITIGATION_FULL: + rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); + mcu_ctrl &= ~GDS_MITG_DIS; + break; + case GDS_MITIGATION_FORCE: + case GDS_MITIGATION_UCODE_NEEDED: + case GDS_MITIGATION_HYPERVISOR: + return; + }; + + wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); + + /* + * Check to make sure that the WRMSR value was not ignored. Writes to + * GDS_MITG_DIS will be ignored if this processor is locked but the boot + * processor was not. + */ + rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl_after); + WARN_ON_ONCE(mcu_ctrl != mcu_ctrl_after); +} + +static void __init gds_select_mitigation(void) +{ + u64 mcu_ctrl; + + if (!boot_cpu_has_bug(X86_BUG_GDS)) + return; + + if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { + gds_mitigation = GDS_MITIGATION_HYPERVISOR; + goto out; + } + + if (cpu_mitigations_off()) + gds_mitigation = GDS_MITIGATION_OFF; + /* Will verify below that mitigation _can_ be disabled */ + + /* No microcode */ + if (!(x86_read_arch_cap_msr() & ARCH_CAP_GDS_CTRL)) { + if (gds_mitigation == GDS_MITIGATION_FORCE) { + /* + * This only needs to be done on the boot CPU so do it + * here rather than in update_gds_msr() + */ + setup_clear_cpu_cap(X86_FEATURE_AVX); + pr_warn("Microcode update needed! Disabling AVX as mitigation.\n"); + } else { + gds_mitigation = GDS_MITIGATION_UCODE_NEEDED; + } + goto out; + } + + /* Microcode has mitigation, use it */ + if (gds_mitigation == GDS_MITIGATION_FORCE) + gds_mitigation = GDS_MITIGATION_FULL; + + rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); + if (mcu_ctrl & GDS_MITG_LOCKED) { + if (gds_mitigation == GDS_MITIGATION_OFF) + pr_warn("Mitigation locked. Disable failed.\n"); + + /* + * The mitigation is selected from the boot CPU. All other CPUs + * _should_ have the same state. If the boot CPU isn't locked + * but others are then update_gds_msr() will WARN() of the state + * mismatch. If the boot CPU is locked update_gds_msr() will + * ensure the other CPUs have the mitigation enabled. + */ + gds_mitigation = GDS_MITIGATION_FULL_LOCKED; + } + + update_gds_msr(); +out: + pr_info("%s\n", gds_strings[gds_mitigation]); +} + +static int __init gds_parse_cmdline(char *str) +{ + if (!str) + return -EINVAL; + + if (!boot_cpu_has_bug(X86_BUG_GDS)) + return 0; + + if (!strcmp(str, "off")) + gds_mitigation = GDS_MITIGATION_OFF; + else if (!strcmp(str, "force")) + gds_mitigation = GDS_MITIGATION_FORCE; + + return 0; +} +early_param("gather_data_sampling", gds_parse_cmdline); + #undef pr_fmt #define pr_fmt(fmt) "Spectre V1 : " fmt @@ -975,14 +1079,18 @@ spectre_v2_parse_user_cmdline(void) return SPECTRE_V2_USER_CMD_AUTO; } -static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode) +static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode) { - return mode == SPECTRE_V2_IBRS || - mode == SPECTRE_V2_EIBRS || + return mode == SPECTRE_V2_EIBRS || mode == SPECTRE_V2_EIBRS_RETPOLINE || mode == SPECTRE_V2_EIBRS_LFENCE; } +static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode) +{ + return spectre_v2_in_eibrs_mode(mode) || mode == SPECTRE_V2_IBRS; +} + static void __init spectre_v2_user_select_mitigation(void) { @@ -1045,12 +1153,19 @@ spectre_v2_user_select_mitigation(void) } /* - * If no STIBP, IBRS or enhanced IBRS is enabled, or SMT impossible, - * STIBP is not required. + * If no STIBP, enhanced IBRS is enabled, or SMT impossible, STIBP + * is not required. + * + * Enhanced IBRS also protects against cross-thread branch target + * injection in user-mode as the IBRS bit remains always set which + * implicitly enables cross-thread protections. However, in legacy IBRS + * mode, the IBRS bit is set only on kernel entry and cleared on return + * to userspace. This disables the implicit cross-thread protection, + * so allow for STIBP to be selected in that case. */ if (!boot_cpu_has(X86_FEATURE_STIBP) || !smt_possible || - spectre_v2_in_ibrs_mode(spectre_v2_enabled)) + spectre_v2_in_eibrs_mode(spectre_v2_enabled)) return; /* @@ -2102,7 +2217,7 @@ static ssize_t mmio_stale_data_show_state(char *buf) static char *stibp_state(void) { - if (spectre_v2_in_ibrs_mode(spectre_v2_enabled)) + if (spectre_v2_in_eibrs_mode(spectre_v2_enabled)) return ""; switch (spectre_v2_user_stibp) { @@ -2177,6 +2292,11 @@ static ssize_t retbleed_show_state(char *buf) return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]); } +static ssize_t gds_show_state(char *buf) +{ + return sysfs_emit(buf, "%s\n", gds_strings[gds_mitigation]); +} + static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, char *buf, unsigned int bug) { @@ -2226,6 +2346,9 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr case X86_BUG_RETBLEED: return retbleed_show_state(buf); + case X86_BUG_GDS: + return gds_show_state(buf); + default: break; } @@ -2290,4 +2413,9 @@ ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, cha { return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED); } + +ssize_t cpu_show_gds(struct device *dev, struct device_attribute *attr, char *buf) +{ + return cpu_show_common(dev, attr, buf, X86_BUG_GDS); +} #endif diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9f0ac012be5a970b0bb838c428d536e8929b5cce..9d96d6a0166543a50b232be0e1ae31ea27853d38 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -13,14 +13,20 @@ #include #include #include +#include #include #include #include +#include #include +#include #include #include #include +#include + +#include #include #include #include @@ -56,6 +62,7 @@ #ifdef CONFIG_X86_LOCAL_APIC #include #endif +#include #include "cpu.h" @@ -1040,6 +1047,12 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { #define MMIO_SBDS BIT(2) /* CPU is affected by RETbleed, speculating where you would not expect it */ #define RETBLEED BIT(3) +/* CPU is affected by SMT (cross-thread) return predictions */ +#define SMT_RSB BIT(4) +/* CPU is affected by SRSO */ +#define SRSO BIT(5) +/* CPU is affected by GDS */ +#define GDS BIT(6) static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), @@ -1052,18 +1065,20 @@ static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO), VULNBL_INTEL_STEPPINGS(BROADWELL_CORE, X86_STEPPING_ANY, SRBDS), VULNBL_INTEL_STEPPINGS(SKYLAKE_MOBILE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), - VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED), + VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), VULNBL_INTEL_STEPPINGS(SKYLAKE_DESKTOP, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), - VULNBL_INTEL_STEPPINGS(KABYLAKE_MOBILE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), - VULNBL_INTEL_STEPPINGS(KABYLAKE_DESKTOP,X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), + VULNBL_INTEL_STEPPINGS(KABYLAKE_MOBILE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(KABYLAKE_DESKTOP,X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED | GDS), VULNBL_INTEL_STEPPINGS(CANNONLAKE_MOBILE,X86_STEPPING_ANY, RETBLEED), - VULNBL_INTEL_STEPPINGS(ICELAKE_MOBILE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), - VULNBL_INTEL_STEPPINGS(ICELAKE_XEON_D, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), - VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), + VULNBL_INTEL_STEPPINGS(ICELAKE_MOBILE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(ICELAKE_XEON_D, X86_STEPPING_ANY, MMIO | GDS), + VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS), + VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(TIGERLAKE_L, X86_STEPPING_ANY, GDS), + VULNBL_INTEL_STEPPINGS(TIGERLAKE, X86_STEPPING_ANY, GDS), VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), - VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED), + VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS), VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_X, X86_STEPPING_ANY, MMIO), VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS), @@ -1186,6 +1201,16 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) !(ia32_cap & ARCH_CAP_PBRSB_NO)) setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); + /* + * Check if CPU is vulnerable to GDS. If running in a virtual machine on + * an affected processor, the VMM may have disabled the use of GATHER by + * disabling AVX2. The only way to do this in HW is to clear XCR0[2], + * which means that AVX will be disabled. + */ + if (cpu_matches(cpu_vuln_blacklist, GDS) && !(ia32_cap & ARCH_CAP_GDS_NO) && + boot_cpu_has(X86_FEATURE_AVX)) + setup_force_cpu_bug(X86_BUG_GDS); + if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) return; @@ -1271,8 +1296,6 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) cpu_set_bug_bits(c); - fpu__init_system(c); - #ifdef CONFIG_X86_32 /* * Regardless of whether PCID is enumerated, the SDM says @@ -1661,6 +1684,8 @@ void identify_secondary_cpu(struct cpuinfo_x86 *c) validate_apic_and_package_id(c); x86_spec_ctrl_setup_ap(); update_srbds_msr(); + if (boot_cpu_has_bug(X86_BUG_GDS)) + update_gds_msr(); } static __init int setup_noclflush(char *arg) @@ -2002,8 +2027,6 @@ void cpu_init(void) clear_all_debug_regs(); dbg_restore_debug_regs(); - fpu__init_cpu(); - if (is_uv_system()) uv_cpu_init(); @@ -2067,8 +2090,6 @@ void cpu_init(void) clear_all_debug_regs(); dbg_restore_debug_regs(); - fpu__init_cpu(); - load_fixmap_gdt(cpu); } #endif @@ -2101,6 +2122,8 @@ void microcode_check(void) perf_check_microcode(); + amd_check_microcode(); + /* Reload CPUID max function as it might've changed. */ info.cpuid_level = cpuid_eax(0); @@ -2119,3 +2142,69 @@ void microcode_check(void) pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); } + +void __init arch_cpu_finalize_init(void) +{ + identify_boot_cpu(); + + /* + * identify_boot_cpu() initialized SMT support information, let the + * core code know. + */ + cpu_smt_check_topology(); + + if (!IS_ENABLED(CONFIG_SMP)) { + pr_info("CPU: "); + print_cpu_info(&boot_cpu_data); + } + + cpu_select_mitigations(); + + arch_smt_update(); + + if (IS_ENABLED(CONFIG_X86_32)) { + /* + * Check whether this is a real i386 which is not longer + * supported and fixup the utsname. + */ + if (boot_cpu_data.x86 < 4) + panic("Kernel requires i486+ for 'invlpg' and other features"); + + init_utsname()->machine[1] = + '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); + } + + /* + * Must be before alternatives because it might set or clear + * feature bits. + */ + fpu__init_system(); + fpu__init_cpu(); + + alternative_instructions(); + + if (IS_ENABLED(CONFIG_X86_64)) { + /* + * Make sure the first 2MB area is not mapped by huge pages + * There are typically fixed size MTRRs in there and overlapping + * MTRRs into large pages causes slow downs. + * + * Right now we don't do that with gbpages because there seems + * very little benefit for that case. + */ + if (!direct_gbpages) + set_memory_4k((unsigned long)__va(0), 1); + } else { + fpu__init_check_bugs(); + } + + /* + * This needs to be called before any devices perform DMA + * operations that might use the SWIOTLB bounce buffers. It will + * mark the bounce buffers as decrypted so that their usage will + * not cause "plain-text" data to be decrypted when accessed. It + * must be called after late_time_init() so that Hyper-V x86/x64 + * hypercalls work when the SWIOTLB bounce buffers are decrypted. + */ + mem_encrypt_init(); +} diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h index 4eb9bf68b1227e6158d9d95a17fbc01a7300db8f..ca1b8bf380a2dc25980bffb57561c00b318ac910 100644 --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -79,9 +79,11 @@ extern void detect_ht(struct cpuinfo_x86 *c); extern void check_null_seg_clears_base(struct cpuinfo_x86 *c); unsigned int aperfmperf_get_khz(int cpu); +void cpu_select_mitigations(void); extern void x86_spec_ctrl_setup_ap(void); extern void update_srbds_msr(void); +extern void update_gds_msr(void); extern u64 x86_read_arch_cap_msr(void); diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index 8396c77e93230367255da72f5178d2b2e4973e72..5698e04803b59c441909e50ffbdbd0e887185c01 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -54,7 +54,9 @@ struct cont_desc { }; static u32 ucode_new_rev; -static u8 amd_ucode_patch[PATCH_MAX_SIZE]; + +/* One blob per node. */ +static u8 amd_ucode_patch[MAX_NUMNODES][PATCH_MAX_SIZE]; /* * Microcode patch container file is prepended to the initrd in cpio @@ -210,7 +212,7 @@ apply_microcode_early_amd(u32 cpuid_1_eax, void *ucode, size_t size, bool save_p patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch); #else new_rev = &ucode_new_rev; - patch = &amd_ucode_patch; + patch = &amd_ucode_patch[0]; #endif desc.cpuid_1_eax = cpuid_1_eax; @@ -329,8 +331,7 @@ void load_ucode_amd_ap(unsigned int cpuid_1_eax) apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, false); } -static enum ucode_state -load_microcode_amd(bool save, u8 family, const u8 *data, size_t size); +static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size); int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax) { @@ -348,19 +349,19 @@ int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax) if (!desc.mc) return -EINVAL; - ret = load_microcode_amd(true, x86_family(cpuid_1_eax), desc.data, desc.size); + ret = load_microcode_amd(x86_family(cpuid_1_eax), desc.data, desc.size); if (ret > UCODE_UPDATED) return -EINVAL; return 0; } -void reload_ucode_amd(void) +void reload_ucode_amd(unsigned int cpu) { - struct microcode_amd *mc; u32 rev, dummy; + struct microcode_amd *mc; - mc = (struct microcode_amd *)amd_ucode_patch; + mc = (struct microcode_amd *)amd_ucode_patch[cpu_to_node(cpu)]; rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); @@ -531,7 +532,7 @@ static enum ucode_state apply_microcode_amd(int cpu) rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); /* need to apply patch? */ - if (rev >= mc_amd->hdr.patch_id) { + if (rev > mc_amd->hdr.patch_id) { ret = UCODE_OK; goto out; } @@ -698,9 +699,10 @@ static enum ucode_state __load_microcode_amd(u8 family, const u8 *data, return UCODE_OK; } -static enum ucode_state -load_microcode_amd(bool save, u8 family, const u8 *data, size_t size) +static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size) { + struct cpuinfo_x86 *c; + unsigned int nid, cpu; struct ucode_patch *p; enum ucode_state ret; @@ -713,22 +715,22 @@ load_microcode_amd(bool save, u8 family, const u8 *data, size_t size) return ret; } - p = find_patch(0); - if (!p) { - return ret; - } else { - if (boot_cpu_data.microcode >= p->patch_id) - return ret; + for_each_node(nid) { + cpu = cpumask_first(cpumask_of_node(nid)); + c = &cpu_data(cpu); - ret = UCODE_NEW; - } + p = find_patch(cpu); + if (!p) + continue; - /* save BSP's matching patch for early load */ - if (!save) - return ret; + if (c->microcode >= p->patch_id) + continue; - memset(amd_ucode_patch, 0, PATCH_MAX_SIZE); - memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE)); + ret = UCODE_NEW; + + memset(&amd_ucode_patch[nid], 0, PATCH_MAX_SIZE); + memcpy(&amd_ucode_patch[nid], p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE)); + } return ret; } @@ -754,12 +756,11 @@ static enum ucode_state request_microcode_amd(int cpu, struct device *device, { char fw_name[36] = "amd-ucode/microcode_amd.bin"; struct cpuinfo_x86 *c = &cpu_data(cpu); - bool bsp = c->cpu_index == boot_cpu_data.cpu_index; enum ucode_state ret = UCODE_NFOUND; const struct firmware *fw; /* reload ucode container only on the boot cpu */ - if (!refresh_fw || !bsp) + if (!refresh_fw) return UCODE_OK; if (c->x86 >= 0x15) @@ -776,7 +777,7 @@ static enum ucode_state request_microcode_amd(int cpu, struct device *device, goto fw_release; } - ret = load_microcode_amd(bsp, c->x86, fw->data, fw->size); + ret = load_microcode_amd(c->x86, fw->data, fw->size); fw_release: release_firmware(fw); diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 985ef98c8ba23a91034f71ca7d4d3ad67eb0c76f..963b989710f98ecb015abd99c6b86ef2306da9bd 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -326,7 +326,7 @@ struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa) #endif } -void reload_early_microcode(void) +void reload_early_microcode(unsigned int cpu) { int vendor, family; @@ -340,7 +340,7 @@ void reload_early_microcode(void) break; case X86_VENDOR_AMD: if (family >= 0x10) - reload_ucode_amd(); + reload_ucode_amd(cpu); break; default: break; @@ -783,7 +783,7 @@ void microcode_bsp_resume(void) if (uci->valid && uci->mc) microcode_ops->apply_microcode(cpu); else if (!uci->mc) - reload_early_microcode(); + reload_early_microcode(cpu); } static struct syscore_ops mc_syscore_ops = { diff --git a/arch/x86/kernel/cpu/topology.c b/arch/x86/kernel/cpu/topology.c index 71ca064e379488f072468f0d3bc57a37beec7855..31fe56a90cbf82a07367cbe3d20dc89eaec02a9a 100644 --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -44,7 +44,7 @@ int detect_extended_topology_early(struct cpuinfo_x86 *c) * initial apic id, which also represents 32-bit extended x2apic id. */ c->initial_apicid = edx; - smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx); + smp_num_siblings = max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)); #endif return 0; } @@ -68,7 +68,8 @@ int detect_extended_topology(struct cpuinfo_x86 *c) * Populate HT related information from sub-leaf level 0. */ cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); - core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx); + core_level_siblings = LEVEL_MAX_SIBLINGS(ebx); + smp_num_siblings = max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)); core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax); sub_index = 1; diff --git a/arch/x86/kernel/crash.c b/arch/x86/kernel/crash.c index 91b3483e5085f3317703e77903522554e351d548..e40bb50c5c4f5951a2dfc805551b7da5b34acfd6 100644 --- a/arch/x86/kernel/crash.c +++ b/arch/x86/kernel/crash.c @@ -35,7 +35,6 @@ #include #include #include -#include #include /* Used while preparing memory map entries for second kernel */ @@ -86,15 +85,6 @@ static void kdump_nmi_callback(int cpu, struct pt_regs *regs) */ cpu_crash_vmclear_loaded_vmcss(); - /* Disable VMX or SVM if needed. - * - * We need to disable virtualization on all CPUs. - * Having VMX or SVM enabled on any CPU may break rebooting - * after the kdump kernel has finished its task. - */ - cpu_emergency_vmxoff(); - cpu_emergency_svm_disable(); - /* * Disable Intel PT to stop its logging */ @@ -153,12 +143,7 @@ void native_machine_crash_shutdown(struct pt_regs *regs) */ cpu_crash_vmclear_loaded_vmcss(); - /* Booting kdump kernel with VMX or SVM enabled won't work, - * because (among other limitations) we can't disable paging - * with the virt flags. - */ - cpu_emergency_vmxoff(); - cpu_emergency_svm_disable(); + cpu_emergency_disable_virtualization(); /* * Disable Intel PT to stop its logging diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index 2b17a5cec0997c01afa6b778a6a4713c5284d34c..7e698c45760cf1c1e440a22ebba246de6e8da8e7 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -171,7 +171,6 @@ void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs, printk("%sCall Trace:\n", log_lvl); unwind_start(&state, task, regs, stack); - stack = stack ? : get_stack_pointer(task, regs); regs = unwind_get_entry_regs(&state, &partial); /* @@ -190,9 +189,13 @@ void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs, * - hardirq stack * - entry stack */ - for ( ; stack; stack = PTR_ALIGN(stack_info.next_sp, sizeof(long))) { + for (stack = stack ?: get_stack_pointer(task, regs); + stack; + stack = stack_info.next_sp) { const char *stack_name; + stack = PTR_ALIGN(stack, sizeof(long)); + if (get_stack_info(stack, task, &stack_info, &visit_mask)) { /* * We weren't on a valid stack. It's possible that diff --git a/arch/x86/kernel/fpu/init.c b/arch/x86/kernel/fpu/init.c index 9692ccc583bb34460f34a0f9c19627a06878d997..644372a10c89590735406d131d4a9f9fc6d18ae7 100644 --- a/arch/x86/kernel/fpu/init.c +++ b/arch/x86/kernel/fpu/init.c @@ -49,7 +49,7 @@ void fpu__init_cpu(void) fpu__init_cpu_xstate(); } -static bool fpu__probe_without_cpuid(void) +static bool __init fpu__probe_without_cpuid(void) { unsigned long cr0; u16 fsw, fcw; @@ -67,7 +67,7 @@ static bool fpu__probe_without_cpuid(void) return fsw == 0 && (fcw & 0x103f) == 0x003f; } -static void fpu__init_system_early_generic(struct cpuinfo_x86 *c) +static void __init fpu__init_system_early_generic(void) { if (!boot_cpu_has(X86_FEATURE_CPUID) && !test_bit(X86_FEATURE_FPU, (unsigned long *)cpu_caps_cleared)) { @@ -297,10 +297,10 @@ static void __init fpu__init_parse_early_param(void) * Called on the boot CPU once per system bootup, to set up the initial * FPU state that is later cloned into all processes: */ -void __init fpu__init_system(struct cpuinfo_x86 *c) +void __init fpu__init_system(void) { fpu__init_parse_early_param(); - fpu__init_system_early_generic(c); + fpu__init_system_early_generic(); /* * The FPU has to be operational for some of the diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 7d372db8bee1186f8a211f5839d6baae7962c5a4..e33b732ad33764eb7b995a826de417abc94d3dce 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -811,6 +811,14 @@ void __init fpu__init_system_xstate(void) fpu__init_prepare_fx_sw_frame(); setup_init_fpu_buf(); setup_xstate_comp(); + + /* + * CPU capabilities initialization runs before FPU init. So + * X86_FEATURE_OSXSAVE is not set. Now that XSAVE is completely + * functional, set the feature bit so depending code works. + */ + setup_force_cpu_cap(X86_FEATURE_OSXSAVE); + print_xstate_offset_size(); pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is %d bytes, using '%s' format.\n", diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c index 8821d0ab0a08c3d0db72078cc7d82f7ebfbee368..82753622f4890484e32ae2891f02422444a56f0c 100644 --- a/arch/x86/kernel/i8259.c +++ b/arch/x86/kernel/i8259.c @@ -32,6 +32,7 @@ */ static void init_8259A(int auto_eoi); +static bool pcat_compat __ro_after_init; static int i8259A_auto_eoi; DEFINE_RAW_SPINLOCK(i8259A_lock); @@ -301,15 +302,32 @@ static void unmask_8259A(void) static int probe_8259A(void) { + unsigned char new_val, probe_val = ~(1 << PIC_CASCADE_IR); unsigned long flags; - unsigned char probe_val = ~(1 << PIC_CASCADE_IR); - unsigned char new_val; + + /* + * If MADT has the PCAT_COMPAT flag set, then do not bother probing + * for the PIC. Some BIOSes leave the PIC uninitialized and probing + * fails. + * + * Right now this causes problems as quite some code depends on + * nr_legacy_irqs() > 0 or has_legacy_pic() == true. This is silly + * when the system has an IO/APIC because then PIC is not required + * at all, except for really old machines where the timer interrupt + * must be routed through the PIC. So just pretend that the PIC is + * there and let legacy_pic->init() initialize it for nothing. + * + * Alternatively this could just try to initialize the PIC and + * repeat the probe, but for cases where there is no PIC that's + * just pointless. + */ + if (pcat_compat) + return nr_legacy_irqs(); + /* - * Check to see if we have a PIC. - * Mask all except the cascade and read - * back the value we just wrote. If we don't - * have a PIC, we will read 0xff as opposed to the - * value we wrote. + * Check to see if we have a PIC. Mask all except the cascade and + * read back the value we just wrote. If we don't have a PIC, we + * will read 0xff as opposed to the value we wrote. */ raw_spin_lock_irqsave(&i8259A_lock, flags); @@ -431,5 +449,9 @@ static int __init i8259A_init_ops(void) return 0; } - device_initcall(i8259A_init_ops); + +void __init legacy_pic_pcat_compat(void) +{ + pcat_compat = true; +} diff --git a/arch/x86/kernel/kprobes/opt.c b/arch/x86/kernel/kprobes/opt.c index 544bd41a514c618f037c8b12a5324aab0debf90b..36b5a493e5b4511ed6fc908a6b2904df143e9cee 100644 --- a/arch/x86/kernel/kprobes/opt.c +++ b/arch/x86/kernel/kprobes/opt.c @@ -56,8 +56,8 @@ unsigned long __recover_optprobed_insn(kprobe_opcode_t *buf, unsigned long addr) /* This function only handles jump-optimized kprobe */ if (kp && kprobe_optimized(kp)) { op = container_of(kp, struct optimized_kprobe, kp); - /* If op->list is not empty, op is under optimizing */ - if (list_empty(&op->list)) + /* If op is optimized or under unoptimizing */ + if (list_empty(&op->list) || optprobe_queued_unopt(op)) goto found; } } @@ -328,7 +328,7 @@ int arch_check_optimized_kprobe(struct optimized_kprobe *op) for (i = 1; i < op->optinsn.size; i++) { p = get_kprobe(op->kp.addr + i); - if (p && !kprobe_disabled(p)) + if (p && !kprobe_disarmed(p)) return -EEXIST; } diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c index 736348ead4218a0007b715efbc1d56bd1bb73e65..2ecf1dcc86b20d7c2f4b79059672b1455d3c3176 100644 --- a/arch/x86/kernel/quirks.c +++ b/arch/x86/kernel/quirks.c @@ -96,7 +96,7 @@ static void ich_force_hpet_resume(void) static void ich_force_enable_hpet(struct pci_dev *dev) { u32 val; - u32 uninitialized_var(rcba); + u32 rcba; int err = 0; if (hpet_address || force_hpet_address) @@ -186,7 +186,7 @@ static void hpet_print_force_info(void) static void old_ich_force_hpet_resume(void) { u32 val; - u32 uninitialized_var(gen_cntl); + u32 gen_cntl; if (!force_hpet_address || !cached_dev) return; @@ -208,7 +208,7 @@ static void old_ich_force_hpet_resume(void) static void old_ich_force_enable_hpet(struct pci_dev *dev) { u32 val; - u32 uninitialized_var(gen_cntl); + u32 gen_cntl; if (hpet_address || force_hpet_address) return; @@ -299,7 +299,7 @@ static void vt8237_force_hpet_resume(void) static void vt8237_force_enable_hpet(struct pci_dev *dev) { - u32 uninitialized_var(val); + u32 val; if (hpet_address || force_hpet_address) return; @@ -430,7 +430,7 @@ static void nvidia_force_hpet_resume(void) static void nvidia_force_enable_hpet(struct pci_dev *dev) { - u32 uninitialized_var(val); + u32 val; if (hpet_address || force_hpet_address) return; diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index b0f3a996df15f6b6fb5d17ff6b57cc9b1db45547..444b8a691c14be4f74637bd444ec2c85329395a2 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -536,33 +536,29 @@ static inline void kb_wait(void) } } -static void vmxoff_nmi(int cpu, struct pt_regs *regs) -{ - cpu_emergency_vmxoff(); -} +static inline void nmi_shootdown_cpus_on_restart(void); -/* Use NMIs as IPIs to tell all CPUs to disable virtualization */ -static void emergency_vmx_disable_all(void) +static void emergency_reboot_disable_virtualization(void) { /* Just make sure we won't change CPUs while doing this */ local_irq_disable(); /* - * Disable VMX on all CPUs before rebooting, otherwise we risk hanging - * the machine, because the CPU blocks INIT when it's in VMX root. + * Disable virtualization on all CPUs before rebooting to avoid hanging + * the system, as VMX and SVM block INIT when running in the host. * * We can't take any locks and we may be on an inconsistent state, so - * use NMIs as IPIs to tell the other CPUs to exit VMX root and halt. + * use NMIs as IPIs to tell the other CPUs to disable VMX/SVM and halt. * - * Do the NMI shootdown even if VMX if off on _this_ CPU, as that - * doesn't prevent a different CPU from being in VMX root operation. + * Do the NMI shootdown even if virtualization is off on _this_ CPU, as + * other CPUs may have virtualization enabled. */ - if (cpu_has_vmx()) { - /* Safely force _this_ CPU out of VMX root operation. */ - __cpu_emergency_vmxoff(); + if (cpu_has_vmx() || cpu_has_svm(NULL)) { + /* Safely force _this_ CPU out of VMX/SVM operation. */ + cpu_emergency_disable_virtualization(); - /* Halt and exit VMX root operation on the other CPUs. */ - nmi_shootdown_cpus(vmxoff_nmi); + /* Disable VMX/SVM and halt on other CPUs. */ + nmi_shootdown_cpus_on_restart(); } } @@ -599,7 +595,7 @@ static void native_machine_emergency_restart(void) unsigned short mode; if (reboot_emergency) - emergency_vmx_disable_all(); + emergency_reboot_disable_virtualization(); tboot_shutdown(TB_SHUTDOWN_REBOOT); @@ -804,6 +800,17 @@ void machine_crash_shutdown(struct pt_regs *regs) /* This is the CPU performing the emergency shutdown work. */ int crashing_cpu = -1; +/* + * Disable virtualization, i.e. VMX or SVM, to ensure INIT is recognized during + * reboot. VMX blocks INIT if the CPU is post-VMXON, and SVM blocks INIT if + * GIF=0, i.e. if the crash occurred between CLGI and STGI. + */ +void cpu_emergency_disable_virtualization(void) +{ + cpu_emergency_vmxoff(); + cpu_emergency_svm_disable(); +} + #if defined(CONFIG_SMP) static nmi_shootdown_cb shootdown_callback; @@ -826,7 +833,14 @@ static int crash_nmi_callback(unsigned int val, struct pt_regs *regs) return NMI_HANDLED; local_irq_disable(); - shootdown_callback(cpu, regs); + if (shootdown_callback) + shootdown_callback(cpu, regs); + + /* + * Prepare the CPU for reboot _after_ invoking the callback so that the + * callback can safely use virtualization instructions, e.g. VMCLEAR. + */ + cpu_emergency_disable_virtualization(); atomic_dec(&waiting_for_crash_ipi); /* Assume hlt works */ @@ -842,18 +856,32 @@ static void smp_send_nmi_allbutself(void) apic->send_IPI_allbutself(NMI_VECTOR); } -/* - * Halt all other CPUs, calling the specified function on each of them +/** + * nmi_shootdown_cpus - Stop other CPUs via NMI + * @callback: Optional callback to be invoked from the NMI handler + * + * The NMI handler on the remote CPUs invokes @callback, if not + * NULL, first and then disables virtualization to ensure that + * INIT is recognized during reboot. * - * This function can be used to halt all other CPUs on crash - * or emergency reboot time. The function passed as parameter - * will be called inside a NMI handler on all CPUs. + * nmi_shootdown_cpus() can only be invoked once. After the first + * invocation all other CPUs are stuck in crash_nmi_callback() and + * cannot respond to a second NMI. */ void nmi_shootdown_cpus(nmi_shootdown_cb callback) { unsigned long msecs; + local_irq_disable(); + /* + * Avoid certain doom if a shootdown already occurred; re-registering + * the NMI handler will cause list corruption, modifying the callback + * will do who knows what, etc... + */ + if (WARN_ON_ONCE(crash_ipi_issued)) + return; + /* Make a note of crashing cpu. Will be used in NMI callback. */ crashing_cpu = safe_smp_processor_id(); @@ -881,7 +909,17 @@ void nmi_shootdown_cpus(nmi_shootdown_cb callback) msecs--; } - /* Leave the nmi callback set */ + /* + * Leave the nmi callback set, shootdown is a one-time thing. Clearing + * the callback could result in a NULL pointer dereference if a CPU + * (finally) responds after the timeout expires. + */ +} + +static inline void nmi_shootdown_cpus_on_restart(void) +{ + if (!crash_ipi_issued) + nmi_shootdown_cpus(NULL); } /* @@ -911,6 +949,8 @@ void nmi_shootdown_cpus(nmi_shootdown_cb callback) /* No other CPUs to shoot down */ } +static inline void nmi_shootdown_cpus_on_restart(void) { } + void run_crash_ipi_callback(struct pt_regs *regs) { } diff --git a/arch/x86/kernel/smp.c b/arch/x86/kernel/smp.c index b2b87b91f3361dc4ec2806685d8bc7b21052ba6e..c94ed0b37bcd46ce4bd605c9098da7d651518ed5 100644 --- a/arch/x86/kernel/smp.c +++ b/arch/x86/kernel/smp.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include /* * Some notes on x86 processor bugs affecting SMP operation: @@ -163,7 +163,7 @@ static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs) if (raw_smp_processor_id() == atomic_read(&stopping_cpu)) return NMI_HANDLED; - cpu_emergency_vmxoff(); + cpu_emergency_disable_virtualization(); stop_this_cpu(NULL); return NMI_HANDLED; @@ -176,7 +176,7 @@ static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs) asmlinkage __visible void smp_reboot_interrupt(void) { ipi_entering_ack_irq(); - cpu_emergency_vmxoff(); + cpu_emergency_disable_virtualization(); stop_this_cpu(NULL); irq_exit(); } diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 8783d065f927634e1e3a9d6ca34194716d9cedcc..2e4f6a1ebca569354a055275437bd861e6f77c7a 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -96,6 +96,17 @@ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); EXPORT_PER_CPU_SYMBOL(cpu_info); +struct mwait_cpu_dead { + unsigned int control; + unsigned int status; +}; + +/* + * Cache line aligned data for mwait_play_dead(). Separate on purpose so + * that it's unlikely to be touched by other CPUs. + */ +static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); + /* Logical package management. We might want to allocate that dynamically */ unsigned int __max_logical_packages __read_mostly; EXPORT_SYMBOL(__max_logical_packages); @@ -231,6 +242,7 @@ static void notrace start_secondary(void *unused) #endif load_current_idt(); cpu_init(); + fpu__init_cpu(); x86_cpuinit.early_percpu_clock_init(); preempt_disable(); smp_callin(); @@ -1594,10 +1606,10 @@ static bool wakeup_cpu0(void) */ static inline void mwait_play_dead(void) { + struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); unsigned int eax, ebx, ecx, edx; unsigned int highest_cstate = 0; unsigned int highest_subcstate = 0; - void *mwait_ptr; int i; if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) @@ -1631,13 +1643,6 @@ static inline void mwait_play_dead(void) (highest_subcstate - 1); } - /* - * This should be a memory location in a cache line which is - * unlikely to be touched by other processors. The actual - * content is immaterial as it is not actually modified in any way. - */ - mwait_ptr = ¤t_thread_info()->flags; - wbinvd(); while (1) { @@ -1649,9 +1654,9 @@ static inline void mwait_play_dead(void) * case where we return around the loop. */ mb(); - clflush(mwait_ptr); + clflush(md); mb(); - __monitor(mwait_ptr, 0, 0); + __monitor(md, 0, 0); mb(); __mwait(eax, 0); /* diff --git a/arch/x86/kernel/sysfb_efi.c b/arch/x86/kernel/sysfb_efi.c index 897da526e40e66027a34b9657c73aea3bdf78c51..5bc0fedb33420b944fdb5a0ce72eee215d894e7a 100644 --- a/arch/x86/kernel/sysfb_efi.c +++ b/arch/x86/kernel/sysfb_efi.c @@ -265,6 +265,22 @@ static const struct dmi_system_id efifb_dmi_swap_width_height[] __initconst = { "Lenovo ideapad D330-10IGM"), }, }, + { + /* Lenovo IdeaPad Duet 3 10IGL5 with 1200x1920 portrait screen */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, + "IdeaPad Duet 3 10IGL5"), + }, + }, + { + /* Lenovo Yoga Book X91F / X91L */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), + /* Non exact match to match F + L versions */ + DMI_MATCH(DMI_PRODUCT_NAME, "Lenovo YB1-X91"), + }, + }, {}, }; diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S index 9c26cbca48af7e9dbaff186e31394e0d43b8ff96..251acce831030b24aba979efb257d43c02fe34bf 100644 --- a/arch/x86/kernel/vmlinux.lds.S +++ b/arch/x86/kernel/vmlinux.lds.S @@ -389,7 +389,7 @@ SECTIONS .brk : AT(ADDR(.brk) - LOAD_OFFSET) { __brk_base = .; . += 64 * 1024; /* 64k alignment slop space */ - *(.brk_reservation) /* areas brk users have reserved */ + *(.bss..brk) /* areas brk users have reserved */ __brk_limit = .; } diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 027941e3df682e6d97544fca66ce9ee949493cf3..256b00f456e6c81c8404edd7c13f2c88472d528c 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2201,13 +2201,17 @@ int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) { u32 reg = kvm_lapic_get_reg(apic, lvt_type); int vector, mode, trig_mode; + int r; if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { vector = reg & APIC_VECTOR_MASK; mode = reg & APIC_MODE_MASK; trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; - return __apic_accept_irq(apic, mode, vector, 1, trig_mode, - NULL); + + r = __apic_accept_irq(apic, mode, vector, 1, trig_mode, NULL); + if (r && lvt_type == APIC_LVTPC) + kvm_lapic_set_reg(apic, APIC_LVTPC, reg | APIC_LVT_MASKED); + return r; } return 0; } diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index ec821a5d131a0190f6477a5af1a8e3b4c0be18dd..55e52064c4ec9be1776b6ea51e491b0657ddd95f 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -12752,7 +12752,7 @@ static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu, static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, u32 *exit_qual) { - bool ia32e; + bool ia32e = !!(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE); *exit_qual = ENTRY_FAIL_DEFAULT; @@ -12765,6 +12765,13 @@ static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, return 1; } + if ((vmcs12->guest_cr0 & (X86_CR0_PG | X86_CR0_PE)) == X86_CR0_PG) + return 1; + + if ((ia32e && !(vmcs12->guest_cr4 & X86_CR4_PAE)) || + (ia32e && !(vmcs12->guest_cr0 & X86_CR0_PG))) + return 1; + /* * If the load IA32_EFER VM-entry control is 1, the following checks * are performed on the field for the IA32_EFER MSR: @@ -12776,7 +12783,6 @@ static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, */ if (to_vmx(vcpu)->nested.nested_run_pending && (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) { - ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || ((vmcs12->guest_cr0 & X86_CR0_PG) && @@ -13872,6 +13878,21 @@ static int vmx_check_intercept(struct kvm_vcpu *vcpu, /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ break; + case x86_intercept_pause: + /* + * PAUSE is a single-byte NOP with a REPE prefix, i.e. collides + * with vanilla NOPs in the emulator. Apply the interception + * check only to actual PAUSE instructions. Don't check + * PAUSE-loop-exiting, software can't expect a given PAUSE to + * exit, i.e. KVM is within its rights to allow L2 to execute + * the PAUSE. + */ + if ((info->rep_prefix != REPE_PREFIX) || + !nested_cpu_has2(vmcs12, CPU_BASED_PAUSE_EXITING)) + return X86EMUL_CONTINUE; + + break; + /* TODO: check more intercepts... */ default: break; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index ff7ec9b507e33306e26e7e84495c70425c82b3bb..0548ae57826ff8d8a5d80b6599c07145e8ec50c0 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1224,6 +1224,9 @@ u64 kvm_get_arch_capabilities(void) /* Guests don't need to know "Fill buffer clear control" exists */ data &= ~ARCH_CAP_FB_CLEAR_CTRL; + if (!boot_cpu_has_bug(X86_BUG_GDS) || gds_ucode_mitigated()) + data |= ARCH_CAP_GDS_NO; + return data; } @@ -2457,6 +2460,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_AMD64_PATCH_LOADER: case MSR_AMD64_BU_CFG2: case MSR_AMD64_DC_CFG: + case MSR_AMD64_TW_CFG: case MSR_F15H_EX_CFG: break; @@ -2760,6 +2764,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_AMD64_BU_CFG2: case MSR_IA32_PERF_CTL: case MSR_AMD64_DC_CFG: + case MSR_AMD64_TW_CFG: case MSR_F15H_EX_CFG: msr_info->data = 0; break; diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index b1dba0987565eb8c0822a02a7b47298f3d0d5420..2c84c5595cf461d93e71dcba8eecd1bf6a9d424a 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -207,6 +208,24 @@ static void __init probe_page_size_mask(void) } } +#define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \ + .family = 6, \ + .model = _model, \ + } +/* + * INVLPG may not properly flush Global entries + * on these CPUs when PCIDs are enabled. + */ +static const struct x86_cpu_id invlpg_miss_ids[] = { + INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), + {} +}; + static void setup_pcid(void) { if (!IS_ENABLED(CONFIG_X86_64)) @@ -215,6 +234,12 @@ static void setup_pcid(void) if (!boot_cpu_has(X86_FEATURE_PCID)) return; + if (x86_match_cpu(invlpg_miss_ids)) { + pr_info("Incomplete global flushes, disabling PCID"); + setup_clear_cpu_cap(X86_FEATURE_PCID); + return; + } + if (boot_cpu_has(X86_FEATURE_PGE)) { /* * This can't be cr4_set_bits_and_update_boot() -- the diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_identity.c index 650d5a6cafc707aae9f0d1525f7748d3343dd029..832c899b7b73b3570e7c46c3d4d6530f7c07849b 100644 --- a/arch/x86/mm/mem_encrypt_identity.c +++ b/arch/x86/mm/mem_encrypt_identity.c @@ -563,7 +563,8 @@ void __init sme_enable(struct boot_params *bp) cmdline_ptr = (const char *)((u64)bp->hdr.cmd_line_ptr | ((u64)bp->ext_cmd_line_ptr << 32)); - cmdline_find_option(cmdline_ptr, cmdline_arg, buffer, sizeof(buffer)); + if (cmdline_find_option(cmdline_ptr, cmdline_arg, buffer, sizeof(buffer)) < 0) + return; if (!strncmp(buffer, cmdline_on, sizeof(buffer))) sme_me_mask = me_mask; diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c index b4ff063a43712ec0b731b86ca0bf378979eb3505..a830d49341ecc747fc446511804eb8786ddb97fb 100644 --- a/arch/x86/mm/numa.c +++ b/arch/x86/mm/numa.c @@ -585,13 +585,6 @@ static int __init numa_register_memblks(struct numa_meminfo *mi) if (start >= end) continue; - /* - * Don't confuse VM with a node that doesn't have the - * minimum amount of memory: - */ - if (end && (end - start) < NODE_MIN_SIZE) - continue; - alloc_node_data(nid); } diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index 76959a7d88c82f3608041a3fd76c74343780d9db..94291e0ddcb7a42a82d8e17d27107d1a289b92b6 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -824,3 +825,23 @@ static void rs690_fix_64bit_dma(struct pci_dev *pdev) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma); #endif + +#ifdef CONFIG_AMD_NB + +#define AMD_15B8_RCC_DEV2_EPF0_STRAP2 0x10136008 +#define AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK 0x00000080L + +static void quirk_clear_strap_no_soft_reset_dev2_f0(struct pci_dev *dev) +{ + u32 data; + + if (!amd_smn_read(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, &data)) { + data &= ~AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK; + if (amd_smn_write(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, data)) + pci_err(dev, "Failed to write data 0x%x\n", data); + } else { + pci_err(dev, "Failed to read data\n"); + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0); +#endif diff --git a/arch/x86/purgatory/Makefile b/arch/x86/purgatory/Makefile index 2cfa0caef1336e99868cedbd1e1adbcd578b36f1..00f104e341e5763b432215a5a6f22ddc72b625ab 100644 --- a/arch/x86/purgatory/Makefile +++ b/arch/x86/purgatory/Makefile @@ -12,6 +12,11 @@ $(obj)/string.o: $(srctree)/arch/x86/boot/compressed/string.c FORCE $(obj)/sha256.o: $(srctree)/lib/sha256.c FORCE $(call if_changed_rule,cc_o_c) +# When profile-guided optimization is enabled, llvm emits two different +# overlapping text sections, which is not supported by kexec. Remove profile +# optimization flags. +KBUILD_CFLAGS := $(filter-out -fprofile-sample-use=% -fprofile-use=%,$(KBUILD_CFLAGS)) + LDFLAGS_purgatory.ro := -e purgatory_start -r --no-undefined -nostdlib -z nodefaultlib targets += purgatory.ro @@ -25,7 +30,7 @@ KCOV_INSTRUMENT := n # make up the standalone purgatory.ro PURGATORY_CFLAGS_REMOVE := -mcmodel=kernel -PURGATORY_CFLAGS := -mcmodel=large -ffreestanding -fno-zero-initialized-in-bss +PURGATORY_CFLAGS := -mcmodel=large -ffreestanding -fno-zero-initialized-in-bss -g0 PURGATORY_CFLAGS += $(DISABLE_STACKLEAK_PLUGIN) -DDISABLE_BRANCH_PROFILING # Default KBUILD_CFLAGS can have -pg option set when FTRACE is enabled. That @@ -56,6 +61,9 @@ CFLAGS_sha256.o += $(PURGATORY_CFLAGS) CFLAGS_REMOVE_string.o += $(PURGATORY_CFLAGS_REMOVE) CFLAGS_string.o += $(PURGATORY_CFLAGS) +AFLAGS_REMOVE_setup-x86_$(BITS).o += -g -Wa,-gdwarf-2 +AFLAGS_REMOVE_entry64.o += -g -Wa,-gdwarf-2 + $(obj)/purgatory.ro: $(PURGATORY_OBJS) FORCE $(call if_changed,ld) diff --git a/arch/x86/um/vdso/um_vdso.c b/arch/x86/um/vdso/um_vdso.c index 7c441b59d3752e43623d56fb4508a710d8a93d3e..be99ff25c5039074c51608eb9940ccd9d82711f0 100644 --- a/arch/x86/um/vdso/um_vdso.c +++ b/arch/x86/um/vdso/um_vdso.c @@ -20,8 +20,10 @@ int __vdso_clock_gettime(clockid_t clock, struct timespec *ts) { long ret; - asm("syscall" : "=a" (ret) : - "0" (__NR_clock_gettime), "D" (clock), "S" (ts) : "memory"); + asm("syscall" + : "=a" (ret) + : "0" (__NR_clock_gettime), "D" (clock), "S" (ts) + : "rcx", "r11", "memory"); return ret; } @@ -32,8 +34,10 @@ int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz) { long ret; - asm("syscall" : "=a" (ret) : - "0" (__NR_gettimeofday), "D" (tv), "S" (tz) : "memory"); + asm("syscall" + : "=a" (ret) + : "0" (__NR_gettimeofday), "D" (tv), "S" (tz) + : "rcx", "r11", "memory"); return ret; } diff --git a/arch/x86/xen/smp_pv.c b/arch/x86/xen/smp_pv.c index 75807c2a1e175cebb67375ecc22fe4c7f055c31f..66f83562d3295bec315b4e1fa36bf2315e443161 100644 --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -58,6 +59,7 @@ static void cpu_bringup(void) int cpu; cpu_init(); + fpu__init_cpu(); touch_softlockup_watchdog(); preempt_disable(); diff --git a/arch/xtensa/include/asm/bugs.h b/arch/xtensa/include/asm/bugs.h deleted file mode 100644 index 69b29d19824946e051dab0e55a1b49513f601a74..0000000000000000000000000000000000000000 --- a/arch/xtensa/include/asm/bugs.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * include/asm-xtensa/bugs.h - * - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Xtensa processors don't have any bugs. :) - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file "COPYING" in the main directory of - * this archive for more details. - */ - -#ifndef _XTENSA_BUGS_H -#define _XTENSA_BUGS_H - -static void check_bugs(void) { } - -#endif /* _XTENSA_BUGS_H */ diff --git a/arch/xtensa/platforms/iss/network.c b/arch/xtensa/platforms/iss/network.c index d027dddc41cadd6de0bca5b84b5c371d1eadb67e..f49329aabec809ceeab13adf66e6cfba27a434c6 100644 --- a/arch/xtensa/platforms/iss/network.c +++ b/arch/xtensa/platforms/iss/network.c @@ -236,7 +236,7 @@ static int tuntap_probe(struct iss_net_private *lp, int index, char *init) init += sizeof(TRANSPORT_TUNTAP_NAME) - 1; if (*init == ',') { - rem = split_if_spec(init + 1, &mac_str, &dev_name); + rem = split_if_spec(init + 1, &mac_str, &dev_name, NULL); if (rem != NULL) { pr_err("%s: extra garbage on specification : '%s'\n", dev->name, rem); diff --git a/block/bio-integrity.c b/block/bio-integrity.c index 2e22a3f7466a86b75c542dd55e6b23d0b4e73c58..469e30a6d3cdec1cac2889770e0f7c0e126737a9 100644 --- a/block/bio-integrity.c +++ b/block/bio-integrity.c @@ -444,6 +444,7 @@ int bio_integrity_clone(struct bio *bio, struct bio *bio_src, bip->bip_vcnt = bip_src->bip_vcnt; bip->bip_iter = bip_src->bip_iter; + bip->bip_flags = bip_src->bip_flags & ~BIP_BLOCK_INTEGRITY; return 0; } diff --git a/block/blk-core.c b/block/blk-core.c index e9b3a6f5a6cb880735ef2028725ecc8e48c7dfbd..83eda8819c1b7f380c28069e82fe66c903dff61d 100644 --- a/block/blk-core.c +++ b/block/blk-core.c @@ -2159,11 +2159,11 @@ static void handle_bad_sector(struct bio *bio, sector_t maxsector) { char b[BDEVNAME_SIZE]; - printk(KERN_INFO "attempt to access beyond end of device\n"); - printk(KERN_INFO "%s: rw=%d, want=%Lu, limit=%Lu\n", - bio_devname(bio, b), bio->bi_opf, - (unsigned long long)bio_end_sector(bio), - (long long)maxsector); + pr_info_ratelimited("attempt to access beyond end of device\n" + "%s: rw=%d, want=%Lu, limit=%Lu\n", + bio_devname(bio, b), bio->bi_opf, + (unsigned long long)bio_end_sector(bio), + (long long)maxsector); } #ifdef CONFIG_FAIL_MAKE_REQUEST diff --git a/block/blk-mq-sched.c b/block/blk-mq-sched.c index d89a757cbde0f9cbbb4c449f5f515f6c6bb34c65..dfa0a21a1fe460fc87ff6e0e28a55c133cf63b42 100644 --- a/block/blk-mq-sched.c +++ b/block/blk-mq-sched.c @@ -51,8 +51,7 @@ void blk_mq_sched_assign_ioc(struct request *rq, struct bio *bio) } /* - * Mark a hardware queue as needing a restart. For shared queues, maintain - * a count of how many hardware queues are marked for restart. + * Mark a hardware queue as needing a restart. */ void blk_mq_sched_mark_restart_hctx(struct blk_mq_hw_ctx *hctx) { diff --git a/block/blk-mq-tag.c b/block/blk-mq-tag.c index 41317c50a44628e9ef4930e9f17ad6d8297c9190..fe5ef6df5b809425ccd2406c82370cf523c64401 100644 --- a/block/blk-mq-tag.c +++ b/block/blk-mq-tag.c @@ -377,18 +377,21 @@ struct blk_mq_tags *blk_mq_init_tags(unsigned int total_tags, int node, int alloc_policy) { struct blk_mq_tags *tags; + struct ext_blk_mq_tags *etags; if (total_tags > BLK_MQ_TAG_MAX) { pr_err("blk-mq: tag depth too large\n"); return NULL; } - tags = kzalloc_node(sizeof(*tags), GFP_KERNEL, node); - if (!tags) + etags = kzalloc_node(sizeof(*etags), GFP_KERNEL, node); + if (!etags) return NULL; + tags = &etags->tags; tags->nr_tags = total_tags; tags->nr_reserved_tags = reserved_tags; + spin_lock_init(&etags->lock); return blk_mq_init_bitmap_tags(tags, node, alloc_policy); } diff --git a/block/blk-mq-tag.h b/block/blk-mq-tag.h index 61deab0b5a5a565c1214ad305cac52f0dde7fb3d..df345118cb533bc0fa9ce4c0f81bdbe029016533 100644 --- a/block/blk-mq-tag.h +++ b/block/blk-mq-tag.h @@ -21,6 +21,21 @@ struct blk_mq_tags { struct list_head page_list; }; +/* + * Extended tag address space map. This was needed + * to add a spinlock to blk_mq_tags in a KMI compliant + * way (no changes could be made to struct blk_mq_tags). + */ +struct ext_blk_mq_tags { + struct blk_mq_tags tags; + + /* + * used to clear request reference in rqs[] before freeing one + * request pool + */ + spinlock_t lock; +}; + extern struct blk_mq_tags *blk_mq_init_tags(unsigned int nr_tags, unsigned int reserved_tags, int node, int alloc_policy); extern void blk_mq_free_tags(struct blk_mq_tags *tags); diff --git a/block/blk-mq.c b/block/blk-mq.c index 6c1e973a8c1193e6a0434892a5436dda22ae4131..859f2633f72972318cbce3b44cfb97aa7207ed06 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -1841,6 +1841,47 @@ void blk_mq_try_issue_list_directly(struct blk_mq_hw_ctx *hctx, } } +static size_t order_to_size(unsigned int order) +{ + return (size_t)PAGE_SIZE << order; +} + +/* called before freeing request pool in @tags */ +static void blk_mq_clear_rq_mapping(struct blk_mq_tag_set *set, + struct blk_mq_tags *tags, unsigned int hctx_idx) +{ + struct blk_mq_tags *drv_tags = set->tags[hctx_idx]; + struct ext_blk_mq_tags *drv_etags; + struct page *page; + unsigned long flags; + + list_for_each_entry(page, &tags->page_list, lru) { + unsigned long start = (unsigned long)page_address(page); + unsigned long end = start + order_to_size(page->private); + int i; + + for (i = 0; i < set->queue_depth; i++) { + struct request *rq = drv_tags->rqs[i]; + unsigned long rq_addr = (unsigned long)rq; + + if (rq_addr >= start && rq_addr < end) { + WARN_ON_ONCE(refcount_read(&rq->ref) != 0); + cmpxchg(&drv_tags->rqs[i], rq, NULL); + } + } + } + + /* + * Wait until all pending iteration is done. + * + * Request reference is cleared and it is guaranteed to be observed + * after the ->lock is released. + */ + drv_etags = container_of(drv_tags, struct ext_blk_mq_tags, tags); + spin_lock_irqsave(&drv_etags->lock, flags); + spin_unlock_irqrestore(&drv_etags->lock, flags); +} + static blk_qc_t blk_mq_make_request(struct request_queue *q, struct bio *bio) { const int is_sync = op_is_sync(bio->bi_opf); @@ -1973,6 +2014,8 @@ void blk_mq_free_rqs(struct blk_mq_tag_set *set, struct blk_mq_tags *tags, } } + blk_mq_clear_rq_mapping(set, tags, hctx_idx); + while (!list_empty(&tags->page_list)) { page = list_first_entry(&tags->page_list, struct page, lru); list_del_init(&page->lru); @@ -2032,11 +2075,6 @@ struct blk_mq_tags *blk_mq_alloc_rq_map(struct blk_mq_tag_set *set, return tags; } -static size_t order_to_size(unsigned int order) -{ - return (size_t)PAGE_SIZE << order; -} - static int blk_mq_init_request(struct blk_mq_tag_set *set, struct request *rq, unsigned int hctx_idx, int node) { diff --git a/block/partitions/amiga.c b/block/partitions/amiga.c index 560936617d9c146b84d980de6137a3d241da2986..4a4160221183b201dcfb3d21bae8dfda42666316 100644 --- a/block/partitions/amiga.c +++ b/block/partitions/amiga.c @@ -32,7 +32,8 @@ int amiga_partition(struct parsed_partitions *state) unsigned char *data; struct RigidDiskBlock *rdb; struct PartitionBlock *pb; - int start_sect, nr_sects, blk, part, res = 0; + sector_t start_sect, nr_sects; + int blk, part, res = 0; int blksize = 1; /* Multiplier for disk block size */ int slot = 1; char b[BDEVNAME_SIZE]; @@ -100,14 +101,14 @@ int amiga_partition(struct parsed_partitions *state) /* Tell Kernel about it */ - nr_sects = (be32_to_cpu(pb->pb_Environment[10]) + 1 - - be32_to_cpu(pb->pb_Environment[9])) * + nr_sects = ((sector_t)be32_to_cpu(pb->pb_Environment[10]) + 1 - + be32_to_cpu(pb->pb_Environment[9])) * be32_to_cpu(pb->pb_Environment[3]) * be32_to_cpu(pb->pb_Environment[5]) * blksize; if (!nr_sects) continue; - start_sect = be32_to_cpu(pb->pb_Environment[9]) * + start_sect = (sector_t)be32_to_cpu(pb->pb_Environment[9]) * be32_to_cpu(pb->pb_Environment[3]) * be32_to_cpu(pb->pb_Environment[5]) * blksize; diff --git a/crypto/asymmetric_keys/verify_pefile.c b/crypto/asymmetric_keys/verify_pefile.c index d178650fd524cfe8bc390c883505f4cbc31d60f2..411977947adbe9ccdad50ee23fade7a48cb3f14e 100644 --- a/crypto/asymmetric_keys/verify_pefile.c +++ b/crypto/asymmetric_keys/verify_pefile.c @@ -139,11 +139,15 @@ static int pefile_strip_sig_wrapper(const void *pebuf, pr_debug("sig wrapper = { %x, %x, %x }\n", wrapper.length, wrapper.revision, wrapper.cert_type); - /* Both pesign and sbsign round up the length of certificate table - * (in optional header data directories) to 8 byte alignment. + /* sbsign rounds up the length of certificate table (in optional + * header data directories) to 8 byte alignment. However, the PE + * specification states that while entries are 8-byte aligned, this is + * not included in their length, and as a result, pesign has not + * rounded up since 0.110. */ - if (round_up(wrapper.length, 8) != ctx->sig_len) { - pr_debug("Signature wrapper len wrong\n"); + if (wrapper.length > ctx->sig_len) { + pr_debug("Signature wrapper bigger than sig len (%x > %x)\n", + ctx->sig_len, wrapper.length); return -ELIBBAD; } if (wrapper.revision != WIN_CERT_REVISION_2_0) { diff --git a/crypto/asymmetric_keys/x509_public_key.c b/crypto/asymmetric_keys/x509_public_key.c index 9338b4558cdc52b70a86c820ef2d39186bf1e3c3..1d25ba3775da7dad19ac06cdda0fe57aade36025 100644 --- a/crypto/asymmetric_keys/x509_public_key.c +++ b/crypto/asymmetric_keys/x509_public_key.c @@ -134,6 +134,11 @@ int x509_check_for_self_signed(struct x509_certificate *cert) if (strcmp(cert->pub->pkey_algo, cert->sig->pkey_algo) != 0) goto out; + if (cert->unsupported_sig) { + ret = 0; + goto out; + } + ret = public_key_verify_signature(cert->pub, cert->sig); if (ret < 0) { if (ret == -ENOPKG) { diff --git a/crypto/drbg.c b/crypto/drbg.c index c8c56763dfdedd9a654d32f2009a0bdcf54de495..0df8cc9bb563713c4c9ef867a986a4f6efbb0725 100644 --- a/crypto/drbg.c +++ b/crypto/drbg.c @@ -1512,6 +1512,14 @@ static int drbg_prepare_hrng(struct drbg_state *drbg) return 0; drbg->jent = crypto_alloc_rng("jitterentropy_rng", 0, 0); + if (IS_ERR(drbg->jent)) { + const int err = PTR_ERR(drbg->jent); + + drbg->jent = NULL; + if (fips_enabled) + return err; + pr_info("DRBG: Continuing without Jitter RNG\n"); + } return 0; } @@ -1567,14 +1575,6 @@ static int drbg_instantiate(struct drbg_state *drbg, struct drbg_string *pers, if (ret) goto free_everything; - if (IS_ERR(drbg->jent)) { - ret = PTR_ERR(drbg->jent); - drbg->jent = NULL; - if (fips_enabled || ret != -ENOENT) - goto free_everything; - pr_info("DRBG: Continuing without Jitter RNG\n"); - } - reseed = false; } diff --git a/crypto/pcrypt.c b/crypto/pcrypt.c index 62e11835f220edf4c72fc77ffc08c10ab60b0ef7..1e9de81ef84fa5c9f28ff6496217c283d1829606 100644 --- a/crypto/pcrypt.c +++ b/crypto/pcrypt.c @@ -174,6 +174,8 @@ static int pcrypt_aead_encrypt(struct aead_request *req) err = pcrypt_do_parallel(padata, &ctx->cb_cpu, &pencrypt); if (!err) return -EINPROGRESS; + if (err == -EBUSY) + return -EAGAIN; return err; } @@ -218,6 +220,8 @@ static int pcrypt_aead_decrypt(struct aead_request *req) err = pcrypt_do_parallel(padata, &ctx->cb_cpu, &pdecrypt); if (!err) return -EINPROGRESS; + if (err == -EBUSY) + return -EAGAIN; return err; } diff --git a/crypto/rsa-pkcs1pad.c b/crypto/rsa-pkcs1pad.c index 812476e4682138225fd46fd2745062d5e1d55105..444a3c630924d0733392dda54d8fc40302df0105 100644 --- a/crypto/rsa-pkcs1pad.c +++ b/crypto/rsa-pkcs1pad.c @@ -216,16 +216,14 @@ static void pkcs1pad_encrypt_sign_complete_cb( struct crypto_async_request *child_async_req, int err) { struct akcipher_request *req = child_async_req->data; - struct crypto_async_request async_req; if (err == -EINPROGRESS) - return; + goto out; + + err = pkcs1pad_encrypt_sign_complete(req, err); - async_req.data = req->base.data; - async_req.tfm = crypto_akcipher_tfm(crypto_akcipher_reqtfm(req)); - async_req.flags = child_async_req->flags; - req->base.complete(&async_req, - pkcs1pad_encrypt_sign_complete(req, err)); +out: + akcipher_request_complete(req, err); } static int pkcs1pad_encrypt(struct akcipher_request *req) @@ -334,15 +332,14 @@ static void pkcs1pad_decrypt_complete_cb( struct crypto_async_request *child_async_req, int err) { struct akcipher_request *req = child_async_req->data; - struct crypto_async_request async_req; if (err == -EINPROGRESS) - return; + goto out; + + err = pkcs1pad_decrypt_complete(req, err); - async_req.data = req->base.data; - async_req.tfm = crypto_akcipher_tfm(crypto_akcipher_reqtfm(req)); - async_req.flags = child_async_req->flags; - req->base.complete(&async_req, pkcs1pad_decrypt_complete(req, err)); +out: + akcipher_request_complete(req, err); } static int pkcs1pad_decrypt(struct akcipher_request *req) @@ -500,15 +497,14 @@ static void pkcs1pad_verify_complete_cb( struct crypto_async_request *child_async_req, int err) { struct akcipher_request *req = child_async_req->data; - struct crypto_async_request async_req; if (err == -EINPROGRESS) - return; + goto out; - async_req.data = req->base.data; - async_req.tfm = crypto_akcipher_tfm(crypto_akcipher_reqtfm(req)); - async_req.flags = child_async_req->flags; - req->base.complete(&async_req, pkcs1pad_verify_complete(req, err)); + err = pkcs1pad_verify_complete(req, err); + +out: + akcipher_request_complete(req, err); } /* diff --git a/crypto/seqiv.c b/crypto/seqiv.c index 64a412be255e10fb6741e144a291313c7b4b308c..039ebc724f5e76b1efad70a370e8e443d3d3a7cd 100644 --- a/crypto/seqiv.c +++ b/crypto/seqiv.c @@ -30,7 +30,7 @@ static void seqiv_aead_encrypt_complete2(struct aead_request *req, int err) struct aead_request *subreq = aead_request_ctx(req); struct crypto_aead *geniv; - if (err == -EINPROGRESS) + if (err == -EINPROGRESS || err == -EBUSY) return; if (err) diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c index 552c1f725b6cf5ab8d4a86ba556c37a053d91b1d..40188632958cdcc8a9ed880e00ae2fd02c303b0d 100644 --- a/drivers/acpi/acpi_pad.c +++ b/drivers/acpi/acpi_pad.c @@ -95,7 +95,7 @@ static void round_robin_cpu(unsigned int tsk_index) cpumask_var_t tmp; int cpu; unsigned long min_weight = -1; - unsigned long uninitialized_var(preferred_cpu); + unsigned long preferred_cpu; if (!alloc_cpumask_var(&tmp, GFP_KERNEL)) return; diff --git a/drivers/acpi/acpica/Makefile b/drivers/acpi/acpica/Makefile index 71f6f2624debca2c3909307c30ec17fc04409ea4..8ce51f0f40ce559232ca1a2521365eefac9e6633 100644 --- a/drivers/acpi/acpica/Makefile +++ b/drivers/acpi/acpica/Makefile @@ -3,7 +3,7 @@ # Makefile for ACPICA Core interpreter # -ccflags-y := -Os -D_LINUX -DBUILDING_ACPICA +ccflags-y := -D_LINUX -DBUILDING_ACPICA ccflags-$(CONFIG_ACPI_DEBUG) += -DACPI_DEBUG_OUTPUT # use acpi.o to put all files here into acpi.o modparam namespace diff --git a/drivers/acpi/acpica/dbnames.c b/drivers/acpi/acpica/dbnames.c index 992bd7b92540d6afff1083164e0f0e237a2f2a08..49afba8c916a71eaad08d201acf73ba5bdfa164c 100644 --- a/drivers/acpi/acpica/dbnames.c +++ b/drivers/acpi/acpica/dbnames.c @@ -571,6 +571,9 @@ acpi_status acpi_db_display_objects(char *obj_type_arg, char *display_count_arg) object_info = ACPI_ALLOCATE_ZEROED(sizeof(struct acpi_object_info)); + if (!object_info) + return (AE_NO_MEMORY); + /* Walk the namespace from the root */ (void)acpi_walk_namespace(ACPI_TYPE_ANY, ACPI_ROOT_OBJECT, diff --git a/drivers/acpi/acpica/dswstate.c b/drivers/acpi/acpica/dswstate.c index c879380e5ce1720b33a99cffa01e06332650376b..ddafbf44158c8142f5ce8c7353c0c8235b08b0df 100644 --- a/drivers/acpi/acpica/dswstate.c +++ b/drivers/acpi/acpica/dswstate.c @@ -576,9 +576,14 @@ acpi_ds_init_aml_walk(struct acpi_walk_state *walk_state, ACPI_FUNCTION_TRACE(ds_init_aml_walk); walk_state->parser_state.aml = - walk_state->parser_state.aml_start = aml_start; - walk_state->parser_state.aml_end = - walk_state->parser_state.pkg_end = aml_start + aml_length; + walk_state->parser_state.aml_start = + walk_state->parser_state.aml_end = + walk_state->parser_state.pkg_end = aml_start; + /* Avoid undefined behavior: applying zero offset to null pointer */ + if (aml_length != 0) { + walk_state->parser_state.aml_end += aml_length; + walk_state->parser_state.pkg_end += aml_length; + } /* The next_op of the next_walk will be the beginning of the method */ diff --git a/drivers/acpi/acpica/hwvalid.c b/drivers/acpi/acpica/hwvalid.c index 24f9b61aa40492b09f84a45745fe7d40d1645e68..b081177c421aa3e96d29c172fca7231ef23ee476 100644 --- a/drivers/acpi/acpica/hwvalid.c +++ b/drivers/acpi/acpica/hwvalid.c @@ -23,8 +23,8 @@ acpi_hw_validate_io_request(acpi_io_address address, u32 bit_width); * * The table is used to implement the Microsoft port access rules that * first appeared in Windows XP. Some ports are always illegal, and some - * ports are only illegal if the BIOS calls _OSI with a win_XP string or - * later (meaning that the BIOS itelf is post-XP.) + * ports are only illegal if the BIOS calls _OSI with nothing newer than + * the specific _OSI strings. * * This provides ACPICA with the desired port protections and * Microsoft compatibility. @@ -145,7 +145,8 @@ acpi_hw_validate_io_request(acpi_io_address address, u32 bit_width) /* Port illegality may depend on the _OSI calls made by the BIOS */ - if (acpi_gbl_osi_data >= port_info->osi_dependency) { + if (port_info->osi_dependency == ACPI_ALWAYS_ILLEGAL || + acpi_gbl_osi_data == port_info->osi_dependency) { ACPI_DEBUG_PRINT((ACPI_DB_VALUES, "Denied AML access to port 0x%8.8X%8.8X/%X (%s 0x%.4X-0x%.4X)\n", ACPI_FORMAT_UINT64(address), diff --git a/drivers/acpi/acpica/nsrepair.c b/drivers/acpi/acpica/nsrepair.c index ff2ab8fbec3841a13e8e7ca815aa0d23e99068f2..8de80bf7802b4a4ee21617743db3fc2c328e36dd 100644 --- a/drivers/acpi/acpica/nsrepair.c +++ b/drivers/acpi/acpica/nsrepair.c @@ -181,8 +181,9 @@ acpi_ns_simple_repair(struct acpi_evaluate_info *info, * Try to fix if there was no return object. Warning if failed to fix. */ if (!return_object) { - if (expected_btypes && (!(expected_btypes & ACPI_RTYPE_NONE))) { - if (package_index != ACPI_NOT_PACKAGE_ELEMENT) { + if (expected_btypes) { + if (!(expected_btypes & ACPI_RTYPE_NONE) && + package_index != ACPI_NOT_PACKAGE_ELEMENT) { ACPI_WARN_PREDEFINED((AE_INFO, info->full_pathname, ACPI_WARN_ALWAYS, @@ -196,14 +197,15 @@ acpi_ns_simple_repair(struct acpi_evaluate_info *info, if (ACPI_SUCCESS(status)) { return (AE_OK); /* Repair was successful */ } - } else { + } + + if (expected_btypes != ACPI_RTYPE_NONE) { ACPI_WARN_PREDEFINED((AE_INFO, info->full_pathname, ACPI_WARN_ALWAYS, "Missing expected return value")); + return (AE_AML_NO_RETURN_VALUE); } - - return (AE_AML_NO_RETURN_VALUE); } } diff --git a/drivers/acpi/acpica/psopcode.c b/drivers/acpi/acpica/psopcode.c index 8d7dc98bad17b50d9224e4802ab8f90046250641..ca01e02af9cba241fa0d7d39aa904c7b2a84a47d 100644 --- a/drivers/acpi/acpica/psopcode.c +++ b/drivers/acpi/acpica/psopcode.c @@ -603,7 +603,7 @@ const struct acpi_opcode_info acpi_gbl_aml_op_info[AML_NUM_OPCODES] = { /* 7E */ ACPI_OP("Timer", ARGP_TIMER_OP, ARGI_TIMER_OP, ACPI_TYPE_ANY, AML_CLASS_EXECUTE, AML_TYPE_EXEC_0A_0T_1R, - AML_FLAGS_EXEC_0A_0T_1R), + AML_FLAGS_EXEC_0A_0T_1R | AML_NO_OPERAND_RESOLVE), /* ACPI 5.0 opcodes */ diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c index c0c533206e02dbfd2b935d235fbb45b6d7131978..88f4040d6c1f212cc997e334430628936985d888 100644 --- a/drivers/acpi/battery.c +++ b/drivers/acpi/battery.c @@ -478,7 +478,7 @@ static int extract_package(struct acpi_battery *battery, u8 *ptr = (u8 *)battery + offsets[i].offset; if (element->type == ACPI_TYPE_STRING || element->type == ACPI_TYPE_BUFFER) - strncpy(ptr, element->string.pointer, 32); + strscpy(ptr, element->string.pointer, 32); else if (element->type == ACPI_TYPE_INTEGER) { strncpy(ptr, (u8 *)&element->integer.value, sizeof(u64)); diff --git a/drivers/acpi/device_sysfs.c b/drivers/acpi/device_sysfs.c index f792b149a5745d3d50be283d61b2937a50a2e543..146be9cdeca5a0baa520f1df75f8fa87d4908b5e 100644 --- a/drivers/acpi/device_sysfs.c +++ b/drivers/acpi/device_sysfs.c @@ -164,8 +164,8 @@ static int create_pnp_modalias(struct acpi_device *acpi_dev, char *modalias, return 0; len = snprintf(modalias, size, "acpi:"); - if (len <= 0) - return len; + if (len >= size) + return -ENOMEM; size -= len; @@ -218,8 +218,10 @@ static int create_of_modalias(struct acpi_device *acpi_dev, char *modalias, len = snprintf(modalias, size, "of:N%sT", (char *)buf.pointer); ACPI_FREE(buf.pointer); - if (len <= 0) - return len; + if (len >= size) + return -ENOMEM; + + size -= len; of_compatible = acpi_dev->data.of_compatible; if (of_compatible->type == ACPI_TYPE_PACKAGE) { diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c index 3394ec64fe95d20d2b154b1109677e2fd12f974e..d2fde87e4d0d4710c65dd07296526fb37707b3e7 100644 --- a/drivers/acpi/ec.c +++ b/drivers/acpi/ec.c @@ -1153,6 +1153,7 @@ static void acpi_ec_remove_query_handlers(struct acpi_ec *ec, void acpi_ec_remove_query_handler(struct acpi_ec *ec, u8 query_bit) { acpi_ec_remove_query_handlers(ec, false, query_bit); + flush_workqueue(ec_query_wq); } EXPORT_SYMBOL_GPL(acpi_ec_remove_query_handler); diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c index 7c352cba052893bb59f135b597f797a345974cd4..8ac01375fe8fdd47452b67c09cadfaa15cafe714 100644 --- a/drivers/acpi/irq.c +++ b/drivers/acpi/irq.c @@ -55,6 +55,7 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity) { struct irq_fwspec fwspec; + unsigned int irq; if (WARN_ON(!acpi_gsi_domain_id)) { pr_warn("GSI: No registered irqchip, giving up\n"); @@ -66,7 +67,11 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity); fwspec.param_count = 2; - return irq_create_fwspec_mapping(&fwspec); + irq = irq_create_fwspec_mapping(&fwspec); + if (!irq) + return -EINVAL; + + return irq; } EXPORT_SYMBOL_GPL(acpi_register_gsi); diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c index 3bdab6eb33bf3b81fa7c1c403aad3e0bcc0b5c58..cceb5ca357dee20f4e3133d418c1f699aaa8e91d 100644 --- a/drivers/acpi/thermal.c +++ b/drivers/acpi/thermal.c @@ -1172,8 +1172,6 @@ static int acpi_thermal_resume(struct device *dev) return -EINVAL; for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE; i++) { - if (!(&tz->trips.active[i])) - break; if (!tz->trips.active[i].flags.valid) break; tz->trips.active[i].flags.enabled = 1; diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c index 0ec74ab2a3995fb1e172b70ab197d67232be5a99..866bc20c823970802c1527460add83709c323298 100644 --- a/drivers/acpi/video_detect.c +++ b/drivers/acpi/video_detect.c @@ -294,13 +294,22 @@ static const struct dmi_system_id video_detect_dmi_table[] = { DMI_MATCH(DMI_BOARD_NAME, "Lenovo IdeaPad S405"), }, }, + { + /* https://bugzilla.suse.com/show_bug.cgi?id=1208724 */ + .callback = video_detect_force_native, + /* Lenovo Ideapad Z470 */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_MATCH(DMI_PRODUCT_VERSION, "IdeaPad Z470"), + }, + }, { /* https://bugzilla.redhat.com/show_bug.cgi?id=1187004 */ .callback = video_detect_force_native, .ident = "Lenovo Ideapad Z570", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), - DMI_MATCH(DMI_PRODUCT_NAME, "102434U"), + DMI_MATCH(DMI_PRODUCT_VERSION, "Ideapad Z570"), }, }, { diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index e1992f361c9a6288b8409e9601cced0c33163634..2aaec96f83849266a14270117eb2957732cfe8a6 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -349,6 +349,7 @@ static void amba_device_release(struct device *dev) { struct amba_device *d = to_amba_device(dev); + of_node_put(d->dev.of_node); if (d->res.parent) release_resource(&d->res); kfree(d); diff --git a/drivers/android/binder.c b/drivers/android/binder.c index ca272fe52842cf8dc2ba382652fe5caed482bf6c..ba47344e1d04bde55b3b5c653b422302c0d10c1b 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -6548,6 +6548,7 @@ static int __init binder_init(void) err_alloc_device_names_failed: debugfs_remove_recursive(binder_debugfs_dir_entry_root); + binder_alloc_shrinker_exit(); return ret; } diff --git a/drivers/android/binder_alloc.c b/drivers/android/binder_alloc.c index 34340f9c3f96934f358604e61b781b7cb806c2aa..3ea6bcc08f89334788e70968ba2dd04a5bc89479 100644 --- a/drivers/android/binder_alloc.c +++ b/drivers/android/binder_alloc.c @@ -1074,6 +1074,12 @@ static struct shrinker binder_shrinker = { .seeks = DEFAULT_SEEKS, }; +void binder_alloc_shrinker_exit(void) +{ + unregister_shrinker(&binder_shrinker); + list_lru_destroy(&binder_alloc_lru); +} + /** * binder_alloc_init() - called by binder_open() for per-proc initialization * @alloc: binder_alloc for this proc diff --git a/drivers/android/binder_alloc.h b/drivers/android/binder_alloc.h index 3daa3e21126778cbdb6f119096cc4a6e1b15234f..09031dbcb1f96b4ea4a2ddc4c94deeda825a406a 100644 --- a/drivers/android/binder_alloc.h +++ b/drivers/android/binder_alloc.h @@ -132,6 +132,7 @@ extern struct binder_buffer *binder_alloc_new_buf(struct binder_alloc *alloc, int pid); extern void binder_alloc_init(struct binder_alloc *alloc); extern int binder_alloc_shrinker_init(void); +extern void binder_alloc_shrinker_exit(void); extern void binder_alloc_vma_close(struct binder_alloc *alloc); extern struct binder_buffer * binder_alloc_prepare_to_free(struct binder_alloc *alloc, diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 13fb983b3413e50ae6488dc54f8cadf7fb67b43c..ab3ea47ecce3a8dedab513be15ea622f22bbec35 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -694,7 +694,7 @@ static void ahci_pci_init_controller(struct ata_host *host) /* clear port IRQ */ tmp = readl(port_mmio + PORT_IRQ_STAT); - VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); + dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp); if (tmp) writel(tmp, port_mmio + PORT_IRQ_STAT); } @@ -1504,7 +1504,6 @@ static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) u32 irq_stat, irq_masked; unsigned int handled = 1; - VPRINTK("ENTER\n"); hpriv = host->private_data; mmio = hpriv->mmio; irq_stat = readl(mmio + HOST_IRQ_STAT); @@ -1521,7 +1520,6 @@ static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) irq_stat = readl(mmio + HOST_IRQ_STAT); spin_unlock(&host->lock); } while (irq_stat); - VPRINTK("EXIT\n"); return IRQ_RETVAL(handled); } @@ -1866,6 +1864,15 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) else dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); + if (!(hpriv->cap & HOST_CAP_PART)) + host->flags |= ATA_HOST_NO_PART; + + if (!(hpriv->cap & HOST_CAP_SSC)) + host->flags |= ATA_HOST_NO_SSC; + + if (!(hpriv->cap2 & HOST_CAP2_SDS)) + host->flags |= ATA_HOST_NO_DEVSLP; + if (pi.flags & ATA_FLAG_EM) ahci_reset_em(host); diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index d5b9f96898776b8b72ffc76bab0a7075e58f7285..8cc6cb14767b0423355675732bb58b07f4ae7147 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -40,6 +40,7 @@ #include #include #include +#include /* Enclosure Management Control */ #define EM_CTRL_MSG_TYPE 0x000f0000 @@ -70,12 +71,12 @@ enum { AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + (AHCI_RX_FIS_SZ * 16), - AHCI_IRQ_ON_SG = (1 << 31), - AHCI_CMD_ATAPI = (1 << 5), - AHCI_CMD_WRITE = (1 << 6), - AHCI_CMD_PREFETCH = (1 << 7), - AHCI_CMD_RESET = (1 << 8), - AHCI_CMD_CLR_BUSY = (1 << 10), + AHCI_IRQ_ON_SG = BIT(31), + AHCI_CMD_ATAPI = BIT(5), + AHCI_CMD_WRITE = BIT(6), + AHCI_CMD_PREFETCH = BIT(7), + AHCI_CMD_RESET = BIT(8), + AHCI_CMD_CLR_BUSY = BIT(10), RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */ RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ @@ -93,37 +94,37 @@ enum { HOST_CAP2 = 0x24, /* host capabilities, extended */ /* HOST_CTL bits */ - HOST_RESET = (1 << 0), /* reset controller; self-clear */ - HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ - HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */ - HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ + HOST_RESET = BIT(0), /* reset controller; self-clear */ + HOST_IRQ_EN = BIT(1), /* global IRQ enable */ + HOST_MRSM = BIT(2), /* MSI Revert to Single Message */ + HOST_AHCI_EN = BIT(31), /* AHCI enabled */ /* HOST_CAP bits */ - HOST_CAP_SXS = (1 << 5), /* Supports External SATA */ - HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ - HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */ - HOST_CAP_PART = (1 << 13), /* Partial state capable */ - HOST_CAP_SSC = (1 << 14), /* Slumber state capable */ - HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */ - HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */ - HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ - HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */ - HOST_CAP_CLO = (1 << 24), /* Command List Override support */ - HOST_CAP_LED = (1 << 25), /* Supports activity LED */ - HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ - HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ - HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */ - HOST_CAP_SNTF = (1 << 29), /* SNotification register */ - HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ - HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ + HOST_CAP_SXS = BIT(5), /* Supports External SATA */ + HOST_CAP_EMS = BIT(6), /* Enclosure Management support */ + HOST_CAP_CCC = BIT(7), /* Command Completion Coalescing */ + HOST_CAP_PART = BIT(13), /* Partial state capable */ + HOST_CAP_SSC = BIT(14), /* Slumber state capable */ + HOST_CAP_PIO_MULTI = BIT(15), /* PIO multiple DRQ support */ + HOST_CAP_FBS = BIT(16), /* FIS-based switching support */ + HOST_CAP_PMP = BIT(17), /* Port Multiplier support */ + HOST_CAP_ONLY = BIT(18), /* Supports AHCI mode only */ + HOST_CAP_CLO = BIT(24), /* Command List Override support */ + HOST_CAP_LED = BIT(25), /* Supports activity LED */ + HOST_CAP_ALPM = BIT(26), /* Aggressive Link PM support */ + HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */ + HOST_CAP_MPS = BIT(28), /* Mechanical presence switch */ + HOST_CAP_SNTF = BIT(29), /* SNotification register */ + HOST_CAP_NCQ = BIT(30), /* Native Command Queueing */ + HOST_CAP_64 = BIT(31), /* PCI DAC (64-bit DMA) support */ /* HOST_CAP2 bits */ - HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */ - HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */ - HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */ - HOST_CAP2_SDS = (1 << 3), /* Support device sleep */ - HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */ - HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */ + HOST_CAP2_BOH = BIT(0), /* BIOS/OS handoff supported */ + HOST_CAP2_NVMHCI = BIT(1), /* NVMHCI supported */ + HOST_CAP2_APST = BIT(2), /* Automatic partial to slumber */ + HOST_CAP2_SDS = BIT(3), /* Support device sleep */ + HOST_CAP2_SADM = BIT(4), /* Support aggressive DevSlp */ + HOST_CAP2_DESO = BIT(5), /* DevSlp from slumber only */ /* registers for each SATA port */ PORT_LST_ADDR = 0x00, /* command list DMA addr */ @@ -145,24 +146,25 @@ enum { PORT_DEVSLP = 0x44, /* device sleep */ /* PORT_IRQ_{STAT,MASK} bits */ - PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ - PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ - PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ - PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ - PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ - PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ - PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ - PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ - - PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ - PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ - PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ - PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ - PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ - PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ - PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ - PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ - PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ + PORT_IRQ_COLD_PRES = BIT(31), /* cold presence detect */ + PORT_IRQ_TF_ERR = BIT(30), /* task file error */ + PORT_IRQ_HBUS_ERR = BIT(29), /* host bus fatal error */ + PORT_IRQ_HBUS_DATA_ERR = BIT(28), /* host bus data error */ + PORT_IRQ_IF_ERR = BIT(27), /* interface fatal error */ + PORT_IRQ_IF_NONFATAL = BIT(26), /* interface non-fatal error */ + PORT_IRQ_OVERFLOW = BIT(24), /* xfer exhausted available S/G */ + PORT_IRQ_BAD_PMP = BIT(23), /* incorrect port multiplier */ + + PORT_IRQ_PHYRDY = BIT(22), /* PhyRdy changed */ + PORT_IRQ_DEV_ILCK = BIT(7), /* device interlock */ + PORT_IRQ_DMPS = BIT(7), /* mechanical presence status */ + PORT_IRQ_CONNECT = BIT(6), /* port connect change status */ + PORT_IRQ_SG_DONE = BIT(5), /* descriptor processed */ + PORT_IRQ_UNK_FIS = BIT(4), /* unknown FIS rx'd */ + PORT_IRQ_SDB_FIS = BIT(3), /* Set Device Bits FIS rx'd */ + PORT_IRQ_DMAS_FIS = BIT(2), /* DMA Setup FIS rx'd */ + PORT_IRQ_PIOS_FIS = BIT(1), /* PIO Setup FIS rx'd */ + PORT_IRQ_D2H_REG_FIS = BIT(0), /* D2H Register FIS rx'd */ PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | @@ -178,34 +180,34 @@ enum { PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, /* PORT_CMD bits */ - PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ - PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ - PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ - PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ - PORT_CMD_ESP = (1 << 21), /* External Sata Port */ - PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */ - PORT_CMD_PMP = (1 << 17), /* PMP attached */ - PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ - PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ - PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ - PORT_CMD_CLO = (1 << 3), /* Command list override */ - PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ - PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ - PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ - - PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ - PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ - PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ - PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ + PORT_CMD_ASP = BIT(27), /* Aggressive Slumber/Partial */ + PORT_CMD_ALPE = BIT(26), /* Aggressive Link PM enable */ + PORT_CMD_ATAPI = BIT(24), /* Device is ATAPI */ + PORT_CMD_FBSCP = BIT(22), /* FBS Capable Port */ + PORT_CMD_ESP = BIT(21), /* External Sata Port */ + PORT_CMD_HPCP = BIT(18), /* HotPlug Capable Port */ + PORT_CMD_PMP = BIT(17), /* PMP attached */ + PORT_CMD_LIST_ON = BIT(15), /* cmd list DMA engine running */ + PORT_CMD_FIS_ON = BIT(14), /* FIS DMA engine running */ + PORT_CMD_FIS_RX = BIT(4), /* Enable FIS receive DMA engine */ + PORT_CMD_CLO = BIT(3), /* Command list override */ + PORT_CMD_POWER_ON = BIT(2), /* Power up device */ + PORT_CMD_SPIN_UP = BIT(1), /* Spin up device */ + PORT_CMD_START = BIT(0), /* Enable port DMA engine */ + + PORT_CMD_ICC_MASK = (0xfu << 28), /* i/f ICC state mask */ + PORT_CMD_ICC_ACTIVE = (0x1u << 28), /* Put i/f in active state */ + PORT_CMD_ICC_PARTIAL = (0x2u << 28), /* Put i/f in partial state */ + PORT_CMD_ICC_SLUMBER = (0x6u << 28), /* Put i/f in slumber state */ /* PORT_FBS bits */ PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */ PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */ PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */ PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */ - PORT_FBS_SDE = (1 << 2), /* FBS single device error */ - PORT_FBS_DEC = (1 << 1), /* FBS device error clear */ - PORT_FBS_EN = (1 << 0), /* Enable FBS */ + PORT_FBS_SDE = BIT(2), /* FBS single device error */ + PORT_FBS_DEC = BIT(1), /* FBS device error clear */ + PORT_FBS_EN = BIT(0), /* Enable FBS */ /* PORT_DEVSLP bits */ PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */ @@ -213,45 +215,45 @@ enum { PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */ PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */ PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */ - PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */ - PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */ + PORT_DEVSLP_DSP = BIT(1), /* DevSlp present */ + PORT_DEVSLP_ADSE = BIT(0), /* Aggressive DevSlp enable */ /* hpriv->flags bits */ #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) - AHCI_HFLAG_NO_NCQ = (1 << 0), - AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ - AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ - AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ - AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ - AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ - AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ - AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ - AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ - AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ - AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as - link offline */ - AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */ - AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */ - AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */ - AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on - port start (wait until - error-handling stage) */ - AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */ - AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */ + AHCI_HFLAG_NO_NCQ = BIT(0), + AHCI_HFLAG_IGN_IRQ_IF_ERR = BIT(1), /* ignore IRQ_IF_ERR */ + AHCI_HFLAG_IGN_SERR_INTERNAL = BIT(2), /* ignore SERR_INTERNAL */ + AHCI_HFLAG_32BIT_ONLY = BIT(3), /* force 32bit */ + AHCI_HFLAG_MV_PATA = BIT(4), /* PATA port */ + AHCI_HFLAG_NO_MSI = BIT(5), /* no PCI MSI */ + AHCI_HFLAG_NO_PMP = BIT(6), /* no PMP */ + AHCI_HFLAG_SECT255 = BIT(8), /* max 255 sectors */ + AHCI_HFLAG_YES_NCQ = BIT(9), /* force NCQ cap on */ + AHCI_HFLAG_NO_SUSPEND = BIT(10), /* don't suspend */ + AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = BIT(11), /* treat SRST timeout as + link offline */ + AHCI_HFLAG_NO_SNTF = BIT(12), /* no sntf */ + AHCI_HFLAG_NO_FPDMA_AA = BIT(13), /* no FPDMA AA */ + AHCI_HFLAG_YES_FBS = BIT(14), /* force FBS cap on */ + AHCI_HFLAG_DELAY_ENGINE = BIT(15), /* do not start engine on + port start (wait until + error-handling stage) */ + AHCI_HFLAG_NO_DEVSLP = BIT(17), /* no device sleep */ + AHCI_HFLAG_NO_FBS = BIT(18), /* no FBS */ #ifdef CONFIG_PCI_MSI - AHCI_HFLAG_MULTI_MSI = (1 << 20), /* per-port MSI(-X) */ + AHCI_HFLAG_MULTI_MSI = BIT(20), /* per-port MSI(-X) */ #else /* compile out MSI infrastructure */ AHCI_HFLAG_MULTI_MSI = 0, #endif - AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */ - AHCI_HFLAG_YES_ALPM = (1 << 23), /* force ALPM cap on */ - AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read - only registers */ - AHCI_HFLAG_IS_MOBILE = (1 << 25), /* mobile chipset, use + AHCI_HFLAG_WAKE_BEFORE_STOP = BIT(22), /* wake before DMA stop */ + AHCI_HFLAG_YES_ALPM = BIT(23), /* force ALPM cap on */ + AHCI_HFLAG_NO_WRITE_TO_RO = BIT(24), /* don't write to read + only registers */ + AHCI_HFLAG_IS_MOBILE = BIT(25), /* mobile chipset, use SATA_MOBILE_LPM_POLICY as default lpm_policy */ @@ -269,22 +271,22 @@ enum { EM_MAX_RETRY = 5, /* em_ctl bits */ - EM_CTL_RST = (1 << 9), /* Reset */ - EM_CTL_TM = (1 << 8), /* Transmit Message */ - EM_CTL_MR = (1 << 0), /* Message Received */ - EM_CTL_ALHD = (1 << 26), /* Activity LED */ - EM_CTL_XMT = (1 << 25), /* Transmit Only */ - EM_CTL_SMB = (1 << 24), /* Single Message Buffer */ - EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */ - EM_CTL_SES = (1 << 18), /* SES-2 messages supported */ - EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */ - EM_CTL_LED = (1 << 16), /* LED messages supported */ + EM_CTL_RST = BIT(9), /* Reset */ + EM_CTL_TM = BIT(8), /* Transmit Message */ + EM_CTL_MR = BIT(0), /* Message Received */ + EM_CTL_ALHD = BIT(26), /* Activity LED */ + EM_CTL_XMT = BIT(25), /* Transmit Only */ + EM_CTL_SMB = BIT(24), /* Single Message Buffer */ + EM_CTL_SGPIO = BIT(19), /* SGPIO messages supported */ + EM_CTL_SES = BIT(18), /* SES-2 messages supported */ + EM_CTL_SAFTE = BIT(17), /* SAF-TE messages supported */ + EM_CTL_LED = BIT(16), /* LED messages supported */ /* em message type */ - EM_MSG_TYPE_LED = (1 << 0), /* LED */ - EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */ - EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */ - EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */ + EM_MSG_TYPE_LED = BIT(0), /* LED */ + EM_MSG_TYPE_SAFTE = BIT(1), /* SAF-TE */ + EM_MSG_TYPE_SES2 = BIT(2), /* SES-2 */ + EM_MSG_TYPE_SGPIO = BIT(3), /* SGPIO */ }; struct ahci_cmd_hdr { diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c index 7e157e1bf65e47f160a10b9e8a6a335bbaaa8d5c..04ad6a2250145f1e39e850927f3f5653c4eff7c2 100644 --- a/drivers/ata/ahci_xgene.c +++ b/drivers/ata/ahci_xgene.c @@ -601,8 +601,6 @@ static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance) void __iomem *mmio; u32 irq_stat, irq_masked; - VPRINTK("ENTER\n"); - hpriv = host->private_data; mmio = hpriv->mmio; @@ -625,8 +623,6 @@ static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance) spin_unlock(&host->lock); - VPRINTK("EXIT\n"); - return IRQ_RETVAL(rc); } diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c index f1153e7ba3b3a2abc3769bf38fe5304ee25b7c0b..b93fad6939dac9aabf54f1544bfa2df56947f4ea 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c @@ -1210,6 +1210,26 @@ static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) return sprintf(buf, "%d\n", emp->blink_policy); } +static void ahci_port_clear_pending_irq(struct ata_port *ap) +{ + struct ahci_host_priv *hpriv = ap->host->private_data; + void __iomem *port_mmio = ahci_port_base(ap); + u32 tmp; + + /* clear SError */ + tmp = readl(port_mmio + PORT_SCR_ERR); + dev_dbg(ap->host->dev, "PORT_SCR_ERR 0x%x\n", tmp); + writel(tmp, port_mmio + PORT_SCR_ERR); + + /* clear port IRQ */ + tmp = readl(port_mmio + PORT_IRQ_STAT); + dev_dbg(ap->host->dev, "PORT_IRQ_STAT 0x%x\n", tmp); + if (tmp) + writel(tmp, port_mmio + PORT_IRQ_STAT); + + writel(1 << ap->port_no, hpriv->mmio + HOST_IRQ_STAT); +} + static void ahci_port_init(struct device *dev, struct ata_port *ap, int port_no, void __iomem *mmio, void __iomem *port_mmio) @@ -1224,18 +1244,7 @@ static void ahci_port_init(struct device *dev, struct ata_port *ap, if (rc) dev_warn(dev, "%s (%d)\n", emsg, rc); - /* clear SError */ - tmp = readl(port_mmio + PORT_SCR_ERR); - VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); - writel(tmp, port_mmio + PORT_SCR_ERR); - - /* clear port IRQ */ - tmp = readl(port_mmio + PORT_IRQ_STAT); - VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); - if (tmp) - writel(tmp, port_mmio + PORT_IRQ_STAT); - - writel(1 << port_no, mmio + HOST_IRQ_STAT); + ahci_port_clear_pending_irq(ap); /* mark esata ports */ tmp = readl(port_mmio + PORT_CMD); @@ -1262,10 +1271,10 @@ void ahci_init_controller(struct ata_host *host) } tmp = readl(mmio + HOST_CTL); - VPRINTK("HOST_CTL 0x%x\n", tmp); + dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp); writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); tmp = readl(mmio + HOST_CTL); - VPRINTK("HOST_CTL 0x%x\n", tmp); + dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp); } EXPORT_SYMBOL_GPL(ahci_init_controller); @@ -1565,6 +1574,8 @@ int ahci_do_hardreset(struct ata_link *link, unsigned int *class, tf.command = ATA_BUSY; ata_tf_to_fis(&tf, 0, 0, d2h_fis); + ahci_port_clear_pending_irq(ap); + rc = sata_link_hardreset(link, timing, deadline, online, ahci_check_ready); @@ -1916,8 +1927,6 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) void __iomem *port_mmio = ahci_port_base(ap); u32 status; - VPRINTK("ENTER\n"); - status = readl(port_mmio + PORT_IRQ_STAT); writel(status, port_mmio + PORT_IRQ_STAT); @@ -1925,8 +1934,6 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) ahci_handle_port_interrupt(ap, port_mmio, status); spin_unlock(ap->lock); - VPRINTK("EXIT\n"); - return IRQ_HANDLED; } @@ -1943,9 +1950,7 @@ u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) ap = host->ports[i]; if (ap) { ahci_port_intr(ap); - VPRINTK("port %u\n", i); } else { - VPRINTK("port %u (no irq)\n", i); if (ata_ratelimit()) dev_warn(host->dev, "interrupt on disabled port %u\n", i); @@ -1966,8 +1971,6 @@ static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) void __iomem *mmio; u32 irq_stat, irq_masked; - VPRINTK("ENTER\n"); - hpriv = host->private_data; mmio = hpriv->mmio; @@ -1995,8 +1998,6 @@ static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) spin_unlock(&host->lock); - VPRINTK("EXIT\n"); - return IRQ_RETVAL(rc); } diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 4a7da8f744e03eb0ab8b581df4c713418f876dbe..2b9f6769f80d714af909d297ee714aa69b707ce5 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -3997,10 +3997,23 @@ int sata_link_scr_lpm(struct ata_link *link, enum ata_lpm_policy policy, case ATA_LPM_MED_POWER_WITH_DIPM: case ATA_LPM_MIN_POWER_WITH_PARTIAL: case ATA_LPM_MIN_POWER: - if (ata_link_nr_enabled(link) > 0) - /* no restrictions on LPM transitions */ + if (ata_link_nr_enabled(link) > 0) { + /* assume no restrictions on LPM transitions */ scontrol &= ~(0x7 << 8); - else { + + /* + * If the controller does not support partial, slumber, + * or devsleep, then disallow these transitions. + */ + if (link->ap->host->flags & ATA_HOST_NO_PART) + scontrol |= (0x1 << 8); + + if (link->ap->host->flags & ATA_HOST_NO_SSC) + scontrol |= (0x2 << 8); + + if (link->ap->host->flags & ATA_HOST_NO_DEVSLP) + scontrol |= (0x4 << 8); + } else { /* empty port, power off */ scontrol &= ~0xf; scontrol |= (0x1 << 2); @@ -5756,17 +5769,19 @@ static void ata_port_request_pm(struct ata_port *ap, pm_message_t mesg, struct ata_link *link; unsigned long flags; - /* Previous resume operation might still be in - * progress. Wait for PM_PENDING to clear. + spin_lock_irqsave(ap->lock, flags); + + /* + * A previous PM operation might still be in progress. Wait for + * ATA_PFLAG_PM_PENDING to clear. */ if (ap->pflags & ATA_PFLAG_PM_PENDING) { + spin_unlock_irqrestore(ap->lock, flags); ata_port_wait_eh(ap); - WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING); + spin_lock_irqsave(ap->lock, flags); } - /* request PM ops to EH */ - spin_lock_irqsave(ap->lock, flags); - + /* Request PM operation to EH */ ap->pm_mesg = mesg; ap->pflags |= ATA_PFLAG_PM_PENDING; ata_for_each_link(link, ap, HOST_FIRST) { @@ -5778,10 +5793,8 @@ static void ata_port_request_pm(struct ata_port *ap, pm_message_t mesg, spin_unlock_irqrestore(ap->lock, flags); - if (!async) { + if (!async) ata_port_wait_eh(ap); - WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING); - } } /* @@ -5947,7 +5960,7 @@ void ata_host_resume(struct ata_host *host) #endif const struct device_type ata_port_type = { - .name = "ata_port", + .name = ATA_PORT_TYPE_NAME, #ifdef CONFIG_PM .pm = &ata_port_pm_ops, #endif @@ -6750,11 +6763,30 @@ static void ata_port_detach(struct ata_port *ap) if (!ap->ops->error_handler) goto skip_eh; - /* tell EH we're leaving & flush EH */ + /* Wait for any ongoing EH */ + ata_port_wait_eh(ap); + + mutex_lock(&ap->scsi_scan_mutex); spin_lock_irqsave(ap->lock, flags); + + /* Remove scsi devices */ + ata_for_each_link(link, ap, HOST_FIRST) { + ata_for_each_dev(dev, link, ALL) { + if (dev->sdev) { + spin_unlock_irqrestore(ap->lock, flags); + scsi_remove_device(dev->sdev); + spin_lock_irqsave(ap->lock, flags); + dev->sdev = NULL; + } + } + } + + /* Tell EH to disable all devices */ ap->pflags |= ATA_PFLAG_UNLOADING; ata_port_schedule_eh(ap); + spin_unlock_irqrestore(ap->lock, flags); + mutex_unlock(&ap->scsi_scan_mutex); /* wait till EH commits suicide */ ata_port_wait_eh(ap); diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c index fcc3d7985762a3a7066ecdff550a81e5ca970009..63423d9e1457c6fa6e34b79bb9c695638c5a7804 100644 --- a/drivers/ata/libata-eh.c +++ b/drivers/ata/libata-eh.c @@ -2443,7 +2443,7 @@ static void ata_eh_link_report(struct ata_link *link) struct ata_eh_context *ehc = &link->eh_context; struct ata_queued_cmd *qc; const char *frozen, *desc; - char tries_buf[6] = ""; + char tries_buf[16] = ""; int tag, nr_failed = 0; if (ehc->i.flags & ATA_EHI_QUIET) @@ -2922,18 +2922,11 @@ int ata_eh_reset(struct ata_link *link, int classify, postreset(slave, classes); } - /* - * Some controllers can't be frozen very well and may set spurious - * error conditions during reset. Clear accumulated error - * information and re-thaw the port if frozen. As reset is the - * final recovery action and we cross check link onlineness against - * device classification later, no hotplug event is lost by this. - */ + /* clear cached SError */ spin_lock_irqsave(link->ap->lock, flags); - memset(&link->eh_info, 0, sizeof(link->eh_info)); + link->eh_info.serror = 0; if (slave) - memset(&slave->eh_info, 0, sizeof(link->eh_info)); - ap->pflags &= ~ATA_PFLAG_EH_PENDING; + slave->eh_info.serror = 0; spin_unlock_irqrestore(link->ap->lock, flags); if (ap->pflags & ATA_PFLAG_FROZEN) diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c index 0950d6fda89cf6e7315359742671e4941900dca8..dc52239812709dbccfb9394622dcc18778f4b9bf 100644 --- a/drivers/ata/libata-scsi.c +++ b/drivers/ata/libata-scsi.c @@ -178,7 +178,7 @@ static ssize_t ata_scsi_park_show(struct device *device, struct ata_link *link; struct ata_device *dev; unsigned long now; - unsigned int uninitialized_var(msecs); + unsigned int msecs; int rc = 0; ap = ata_shost_to_port(sdev->host); @@ -3053,18 +3053,36 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc) return 0; } -static struct ata_device *ata_find_dev(struct ata_port *ap, int devno) +static struct ata_device *ata_find_dev(struct ata_port *ap, unsigned int devno) { - if (!sata_pmp_attached(ap)) { - if (likely(devno >= 0 && - devno < ata_link_max_devices(&ap->link))) + /* + * For the non-PMP case, ata_link_max_devices() returns 1 (SATA case), + * or 2 (IDE master + slave case). However, the former case includes + * libsas hosted devices which are numbered per scsi host, leading + * to devno potentially being larger than 0 but with each struct + * ata_device having its own struct ata_port and struct ata_link. + * To accommodate these, ignore devno and always use device number 0. + */ + if (likely(!sata_pmp_attached(ap))) { + int link_max_devices = ata_link_max_devices(&ap->link); + + if (link_max_devices == 1) + return &ap->link.device[0]; + + if (devno < link_max_devices) return &ap->link.device[devno]; - } else { - if (likely(devno >= 0 && - devno < ap->nr_pmp_links)) - return &ap->pmp_link[devno].device[0]; + + return NULL; } + /* + * For PMP-attached devices, the device number corresponds to C + * (channel) of SCSI [H:C:I:L], indicating the port pmp link + * for the device. + */ + if (devno < ap->nr_pmp_links) + return &ap->pmp_link[devno].device[0]; + return NULL; } @@ -4543,7 +4561,7 @@ void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd) break; case MAINTENANCE_IN: - if (scsicmd[1] == MI_REPORT_SUPPORTED_OPERATION_CODES) + if ((scsicmd[1] & 0x1f) == MI_REPORT_SUPPORTED_OPERATION_CODES) ata_scsi_rbuf_fill(&args, ata_scsiop_maint_in); else ata_scsi_set_invalid_field(dev, cmd, 1, 0xff); diff --git a/drivers/ata/libata-transport.c b/drivers/ata/libata-transport.c index f04f4f977400da0f179b0c9d03646c7fb8e8f503..5eae76d8b65509aeda849ade5ec1a71a26f92645 100644 --- a/drivers/ata/libata-transport.c +++ b/drivers/ata/libata-transport.c @@ -266,6 +266,10 @@ void ata_tport_delete(struct ata_port *ap) put_device(dev); } +static const struct device_type ata_port_sas_type = { + .name = ATA_PORT_TYPE_NAME, +}; + /** ata_tport_add - initialize a transport ATA port structure * * @parent: parent device @@ -283,7 +287,10 @@ int ata_tport_add(struct device *parent, struct device *dev = &ap->tdev; device_initialize(dev); - dev->type = &ata_port_type; + if (ap->flags & ATA_FLAG_SAS_HOST) + dev->type = &ata_port_sas_type; + else + dev->type = &ata_port_type; dev->parent = parent; ata_host_get(ap->host); diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h index f953cb4bb1ba8fe015167d522e08c11b17fa91c7..b568d6b9350a6e00075277194542f5245920f778 100644 --- a/drivers/ata/libata.h +++ b/drivers/ata/libata.h @@ -46,6 +46,8 @@ enum { ATA_DNXFER_QUIET = (1 << 31), }; +#define ATA_PORT_TYPE_NAME "ata_port" + extern atomic_t ata_print_id; extern int atapi_passthru16; extern int libata_fua; diff --git a/drivers/ata/pata_ftide010.c b/drivers/ata/pata_ftide010.c index 569a4a662dcd4deb9d9edb0dbca4001f798bcab5..9da2e14a01080fd4a9753fd7125098b5999e830d 100644 --- a/drivers/ata/pata_ftide010.c +++ b/drivers/ata/pata_ftide010.c @@ -569,6 +569,7 @@ static struct platform_driver pata_ftide010_driver = { }; module_platform_driver(pata_ftide010_driver); +MODULE_DESCRIPTION("low level driver for Faraday Technology FTIDE010"); MODULE_AUTHOR("Linus Walleij "); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:" DRV_NAME); diff --git a/drivers/ata/pata_ns87415.c b/drivers/ata/pata_ns87415.c index 84c6b225b56e941a3f000e7d083700bae9dacf62..9ee4aefca86751aadabe2bcfedf8cd24f98df00f 100644 --- a/drivers/ata/pata_ns87415.c +++ b/drivers/ata/pata_ns87415.c @@ -260,7 +260,7 @@ static u8 ns87560_check_status(struct ata_port *ap) * LOCKING: * Inherited from caller. */ -void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf) +static void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf) { struct ata_ioports *ioaddr = &ap->ioaddr; diff --git a/drivers/ata/sata_gemini.c b/drivers/ata/sata_gemini.c index 46950e0267e0d281dc3aec3429e15be88b93d5a9..64b43943f6502ad680b003298e3b85001ad38951 100644 --- a/drivers/ata/sata_gemini.c +++ b/drivers/ata/sata_gemini.c @@ -434,6 +434,7 @@ static struct platform_driver gemini_sata_driver = { }; module_platform_driver(gemini_sata_driver); +MODULE_DESCRIPTION("low level driver for Cortina Systems Gemini SATA bridge"); MODULE_AUTHOR("Linus Walleij "); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:" DRV_NAME); diff --git a/drivers/atm/idt77252.c b/drivers/atm/idt77252.c index bc06f5919839ca2d3b3521c73d23cce8327e3e0f..3380322df98e0af93f9d3ae939c57ebd01faef73 100644 --- a/drivers/atm/idt77252.c +++ b/drivers/atm/idt77252.c @@ -2915,6 +2915,7 @@ close_card_oam(struct idt77252_dev *card) recycle_rx_pool_skb(card, &vc->rcv.rx_pool); } + kfree(vc); } } } @@ -2958,6 +2959,15 @@ open_card_ubr0(struct idt77252_dev *card) return 0; } +static void +close_card_ubr0(struct idt77252_dev *card) +{ + struct vc_map *vc = card->vcs[0]; + + free_scq(card, vc->scq); + kfree(vc); +} + static int idt77252_dev_open(struct idt77252_dev *card) { @@ -3007,6 +3017,7 @@ static void idt77252_dev_close(struct atm_dev *dev) struct idt77252_dev *card = dev->dev_data; u32 conf; + close_card_ubr0(card); close_card_oam(card); conf = SAR_CFG_RXPTH | /* enable receive path */ diff --git a/drivers/atm/iphase.c b/drivers/atm/iphase.c index 827c6d5e6177422e6d1880274c295f9e4a439c64..b6d8c2660e4a0d0b335f3a98b15aa8eb842a4a6c 100644 --- a/drivers/atm/iphase.c +++ b/drivers/atm/iphase.c @@ -2290,19 +2290,21 @@ static int get_esi(struct atm_dev *dev) static int reset_sar(struct atm_dev *dev) { IADEV *iadev; - int i, error = 1; + int i, error; unsigned int pci[64]; iadev = INPH_IA_DEV(dev); - for(i=0; i<64; i++) - if ((error = pci_read_config_dword(iadev->pci, - i*4, &pci[i])) != PCIBIOS_SUCCESSFUL) - return error; + for (i = 0; i < 64; i++) { + error = pci_read_config_dword(iadev->pci, i * 4, &pci[i]); + if (error != PCIBIOS_SUCCESSFUL) + return error; + } writel(0, iadev->reg+IPHASE5575_EXT_RESET); - for(i=0; i<64; i++) - if ((error = pci_write_config_dword(iadev->pci, - i*4, pci[i])) != PCIBIOS_SUCCESSFUL) - return error; + for (i = 0; i < 64; i++) { + error = pci_write_config_dword(iadev->pci, i * 4, pci[i]); + if (error != PCIBIOS_SUCCESSFUL) + return error; + } udelay(5); return 0; } diff --git a/drivers/atm/zatm.c b/drivers/atm/zatm.c index d5c76b50d3575b753cb8e9f69de6031e145494f4..88f810745fd89def1d50fc030e9f2c4b1ff77407 100644 --- a/drivers/atm/zatm.c +++ b/drivers/atm/zatm.c @@ -939,7 +939,7 @@ static int open_tx_first(struct atm_vcc *vcc) vcc->qos.txtp.max_pcr >= ATM_OC3_PCR); if (unlimited && zatm_dev->ubr != -1) zatm_vcc->shaper = zatm_dev->ubr; else { - int uninitialized_var(pcr); + int pcr; if (unlimited) vcc->qos.txtp.max_sdu = ATM_MAX_AAL5_PDU; if ((zatm_vcc->shaper = alloc_shaper(vcc->dev,&pcr, diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig index df1089f03414233a63b6e329080f3275213047a0..588db5302646b73fbf8042c49fb039d7da251789 100644 --- a/drivers/base/Kconfig +++ b/drivers/base/Kconfig @@ -90,11 +90,6 @@ config PREVENT_FIRMWARE_BUILD source "drivers/base/firmware_loader/Kconfig" -config FW_CACHE - bool "Enable firmware caching during suspend" - depends on PM_SLEEP - default n - config WANT_DEV_COREDUMP bool help diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c index 494147994c5d75d46cc85375bf94c9b6c6b1992a..b9b249843e076baf602bc0df63559762c84cd778 100644 --- a/drivers/base/cpu.c +++ b/drivers/base/cpu.c @@ -586,7 +586,8 @@ static const struct attribute_group *cpu_root_attr_groups[] = { bool cpu_is_hotpluggable(unsigned cpu) { struct device *dev = get_cpu_device(cpu); - return dev && container_of(dev, struct cpu, dev)->hotpluggable; + return dev && container_of(dev, struct cpu, dev)->hotpluggable + && tick_nohz_cpu_hotpluggable(cpu); } EXPORT_SYMBOL_GPL(cpu_is_hotpluggable); @@ -675,6 +676,12 @@ ssize_t __weak cpu_show_retbleed(struct device *dev, return sysfs_emit(buf, "Not affected\n"); } +ssize_t __weak cpu_show_gds(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "Not affected\n"); +} + static DEVICE_ATTR(meltdown, 0444, cpu_show_meltdown, NULL); static DEVICE_ATTR(spectre_v1, 0444, cpu_show_spectre_v1, NULL); static DEVICE_ATTR(spectre_v2, 0444, cpu_show_spectre_v2, NULL); @@ -686,6 +693,7 @@ static DEVICE_ATTR(itlb_multihit, 0444, cpu_show_itlb_multihit, NULL); static DEVICE_ATTR(srbds, 0444, cpu_show_srbds, NULL); static DEVICE_ATTR(mmio_stale_data, 0444, cpu_show_mmio_stale_data, NULL); static DEVICE_ATTR(retbleed, 0444, cpu_show_retbleed, NULL); +static DEVICE_ATTR(gather_data_sampling, 0444, cpu_show_gds, NULL); static struct attribute *cpu_root_vulnerabilities_attrs[] = { &dev_attr_meltdown.attr, @@ -699,6 +707,7 @@ static struct attribute *cpu_root_vulnerabilities_attrs[] = { &dev_attr_srbds.attr, &dev_attr_mmio_stale_data.attr, &dev_attr_retbleed.attr, + &dev_attr_gather_data_sampling.attr, NULL }; diff --git a/drivers/base/driver.c b/drivers/base/driver.c index 857c8f1b876e565a5f7d1130a10351880b8ecd51..668c6c8c22f1f2a3d6b2522e02850f47c99f8b2f 100644 --- a/drivers/base/driver.c +++ b/drivers/base/driver.c @@ -29,6 +29,75 @@ static struct device *next_device(struct klist_iter *i) return dev; } +/** + * driver_set_override() - Helper to set or clear driver override. + * @dev: Device to change + * @override: Address of string to change (e.g. &device->driver_override); + * The contents will be freed and hold newly allocated override. + * @s: NUL-terminated string, new driver name to force a match, pass empty + * string to clear it ("" or "\n", where the latter is only for sysfs + * interface). + * @len: length of @s + * + * Helper to set or clear driver override in a device, intended for the cases + * when the driver_override field is allocated by driver/bus code. + * + * Returns: 0 on success or a negative error code on failure. + */ +int driver_set_override(struct device *dev, const char **override, + const char *s, size_t len) +{ + const char *new, *old; + char *cp; + + if (!override || !s) + return -EINVAL; + + /* + * The stored value will be used in sysfs show callback (sysfs_emit()), + * which has a length limit of PAGE_SIZE and adds a trailing newline. + * Thus we can store one character less to avoid truncation during sysfs + * show. + */ + if (len >= (PAGE_SIZE - 1)) + return -EINVAL; + + if (!len) { + /* Empty string passed - clear override */ + device_lock(dev); + old = *override; + *override = NULL; + device_unlock(dev); + kfree(old); + + return 0; + } + + cp = strnchr(s, len, '\n'); + if (cp) + len = cp - s; + + new = kstrndup(s, len, GFP_KERNEL); + if (!new) + return -ENOMEM; + + device_lock(dev); + old = *override; + if (cp != s) { + *override = new; + } else { + /* "\n" passed - clear override */ + kfree(new); + *override = NULL; + } + device_unlock(dev); + + kfree(old); + + return 0; +} +EXPORT_SYMBOL_GPL(driver_set_override); + /** * driver_for_each_device - Iterator for devices bound to a driver. * @drv: Driver we're iterating. diff --git a/drivers/base/node.c b/drivers/base/node.c index d5dfcfbcd018d33398580c0acd321a991f55a725..2d49e972537a45091e1233bc638baa45911bf5a8 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -72,7 +72,7 @@ static ssize_t node_read_meminfo(struct device *dev, si_meminfo_node(&i, nid); sreclaimable = node_page_state(pgdat, NR_SLAB_RECLAIMABLE); sunreclaimable = node_page_state(pgdat, NR_SLAB_UNRECLAIMABLE); - n = sprintf(buf, + n = sysfs_emit(buf, "Node %d MemTotal: %8lu kB\n" "Node %d MemFree: %8lu kB\n" "Node %d MemUsed: %8lu kB\n" diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 349c2754eed78711ab14b44a081ef3b72ed43d8d..e3b3caf17a618db7718cdcab2cfdfce5b6b6be32 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -80,6 +80,26 @@ struct resource *platform_get_resource(struct platform_device *dev, } EXPORT_SYMBOL_GPL(platform_get_resource); +/** + * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform + * device + * + * @pdev: platform device to use both for memory resource lookup as well as + * resource managemend + * @index: resource index + */ +#ifdef CONFIG_HAS_IOMEM +void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev, + unsigned int index) +{ + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, index); + return devm_ioremap_resource(&pdev->dev, res); +} +EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource); +#endif /* CONFIG_HAS_IOMEM */ + /** * platform_get_irq - get an IRQ for a device * @dev: platform device @@ -871,31 +891,11 @@ static ssize_t driver_override_store(struct device *dev, const char *buf, size_t count) { struct platform_device *pdev = to_platform_device(dev); - char *driver_override, *old, *cp; - - /* We need to keep extra room for a newline */ - if (count >= (PAGE_SIZE - 1)) - return -EINVAL; - - driver_override = kstrndup(buf, count, GFP_KERNEL); - if (!driver_override) - return -ENOMEM; - - cp = strchr(driver_override, '\n'); - if (cp) - *cp = '\0'; - - device_lock(dev); - old = pdev->driver_override; - if (strlen(driver_override)) { - pdev->driver_override = driver_override; - } else { - kfree(driver_override); - pdev->driver_override = NULL; - } - device_unlock(dev); + int ret; - kfree(old); + ret = driver_set_override(dev, (const char **)&pdev->driver_override, buf, count); + if (ret) + return ret; return count; } diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c index e865aa4b250475ad02709d3bfc796b46938b60b7..b32d3cf4f670d8a967fe36ce3ec870d3b9e4828d 100644 --- a/drivers/base/power/domain.c +++ b/drivers/base/power/domain.c @@ -2433,10 +2433,10 @@ static int genpd_parse_state(struct genpd_power_state *genpd_state, err = of_property_read_u32(state_node, "min-residency-us", &residency); if (!err) - genpd_state->residency_ns = 1000 * residency; + genpd_state->residency_ns = 1000LL * residency; - genpd_state->power_on_latency_ns = 1000 * exit_latency; - genpd_state->power_off_latency_ns = 1000 * entry_latency; + genpd_state->power_on_latency_ns = 1000LL * exit_latency; + genpd_state->power_off_latency_ns = 1000LL * entry_latency; genpd_state->fwnode = &state_node->fwnode; return 0; diff --git a/drivers/base/power/power.h b/drivers/base/power/power.h index d5008fee9667d6aac474e02b4bb7cbf356efc2fe..a004e216c0b247f6117be8bc4252d804b98fdf54 100644 --- a/drivers/base/power/power.h +++ b/drivers/base/power/power.h @@ -24,8 +24,11 @@ extern void pm_runtime_remove(struct device *dev); #define WAKE_IRQ_DEDICATED_ALLOCATED BIT(0) #define WAKE_IRQ_DEDICATED_MANAGED BIT(1) +#define WAKE_IRQ_DEDICATED_REVERSE BIT(2) #define WAKE_IRQ_DEDICATED_MASK (WAKE_IRQ_DEDICATED_ALLOCATED | \ - WAKE_IRQ_DEDICATED_MANAGED) + WAKE_IRQ_DEDICATED_MANAGED | \ + WAKE_IRQ_DEDICATED_REVERSE) +#define WAKE_IRQ_DEDICATED_ENABLED BIT(3) struct wake_irq { struct device *dev; @@ -38,7 +41,8 @@ extern void dev_pm_arm_wake_irq(struct wake_irq *wirq); extern void dev_pm_disarm_wake_irq(struct wake_irq *wirq); extern void dev_pm_enable_wake_irq_check(struct device *dev, bool can_change_status); -extern void dev_pm_disable_wake_irq_check(struct device *dev); +extern void dev_pm_disable_wake_irq_check(struct device *dev, bool cond_disable); +extern void dev_pm_enable_wake_irq_complete(struct device *dev); #ifdef CONFIG_PM_SLEEP diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c index 911bb8a4bf6df233f13267901edf64e97338cf2e..ab0898c33880af19f769c435805a7e96e2fc8935 100644 --- a/drivers/base/power/runtime.c +++ b/drivers/base/power/runtime.c @@ -606,6 +606,8 @@ static int rpm_suspend(struct device *dev, int rpmflags) if (retval) goto fail; + dev_pm_enable_wake_irq_complete(dev); + no_callback: __update_runtime_status(dev, RPM_SUSPENDED); pm_runtime_deactivate_timer(dev); @@ -640,7 +642,7 @@ static int rpm_suspend(struct device *dev, int rpmflags) return retval; fail: - dev_pm_disable_wake_irq_check(dev); + dev_pm_disable_wake_irq_check(dev, true); __update_runtime_status(dev, RPM_ACTIVE); dev->power.deferred_resume = false; wake_up_all(&dev->power.wait_queue); @@ -823,7 +825,7 @@ static int rpm_resume(struct device *dev, int rpmflags) callback = RPM_GET_CALLBACK(dev, runtime_resume); - dev_pm_disable_wake_irq_check(dev); + dev_pm_disable_wake_irq_check(dev, false); retval = rpm_callback(callback, dev); if (retval) { __update_runtime_status(dev, RPM_SUSPENDED); diff --git a/drivers/base/power/wakeirq.c b/drivers/base/power/wakeirq.c index b8fa5c0f2d1325ba9238f219f7613e0751abef6b..e7ba5149991631311af9824446af24033abe3318 100644 --- a/drivers/base/power/wakeirq.c +++ b/drivers/base/power/wakeirq.c @@ -156,24 +156,7 @@ static irqreturn_t handle_threaded_wake_irq(int irq, void *_wirq) return IRQ_HANDLED; } -/** - * dev_pm_set_dedicated_wake_irq - Request a dedicated wake-up interrupt - * @dev: Device entry - * @irq: Device wake-up interrupt - * - * Unless your hardware has separate wake-up interrupts in addition - * to the device IO interrupts, you don't need this. - * - * Sets up a threaded interrupt handler for a device that has - * a dedicated wake-up interrupt in addition to the device IO - * interrupt. - * - * The interrupt starts disabled, and needs to be managed for - * the device by the bus code or the device driver using - * dev_pm_enable_wake_irq() and dev_pm_disable_wake_irq() - * functions. - */ -int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq) +static int __dev_pm_set_dedicated_wake_irq(struct device *dev, int irq, unsigned int flag) { struct wake_irq *wirq; int err; @@ -211,7 +194,7 @@ int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq) if (err) goto err_free_irq; - wirq->status = WAKE_IRQ_DEDICATED_ALLOCATED; + wirq->status = WAKE_IRQ_DEDICATED_ALLOCATED | flag; return err; @@ -224,8 +207,57 @@ int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq) return err; } + + +/** + * dev_pm_set_dedicated_wake_irq - Request a dedicated wake-up interrupt + * @dev: Device entry + * @irq: Device wake-up interrupt + * + * Unless your hardware has separate wake-up interrupts in addition + * to the device IO interrupts, you don't need this. + * + * Sets up a threaded interrupt handler for a device that has + * a dedicated wake-up interrupt in addition to the device IO + * interrupt. + * + * The interrupt starts disabled, and needs to be managed for + * the device by the bus code or the device driver using + * dev_pm_enable_wake_irq*() and dev_pm_disable_wake_irq*() + * functions. + */ +int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq) +{ + return __dev_pm_set_dedicated_wake_irq(dev, irq, 0); +} EXPORT_SYMBOL_GPL(dev_pm_set_dedicated_wake_irq); +/** + * dev_pm_set_dedicated_wake_irq_reverse - Request a dedicated wake-up interrupt + * with reverse enable ordering + * @dev: Device entry + * @irq: Device wake-up interrupt + * + * Unless your hardware has separate wake-up interrupts in addition + * to the device IO interrupts, you don't need this. + * + * Sets up a threaded interrupt handler for a device that has a dedicated + * wake-up interrupt in addition to the device IO interrupt. It sets + * the status of WAKE_IRQ_DEDICATED_REVERSE to tell rpm_suspend() + * to enable dedicated wake-up interrupt after running the runtime suspend + * callback for @dev. + * + * The interrupt starts disabled, and needs to be managed for + * the device by the bus code or the device driver using + * dev_pm_enable_wake_irq*() and dev_pm_disable_wake_irq*() + * functions. + */ +int dev_pm_set_dedicated_wake_irq_reverse(struct device *dev, int irq) +{ + return __dev_pm_set_dedicated_wake_irq(dev, irq, WAKE_IRQ_DEDICATED_REVERSE); +} +EXPORT_SYMBOL_GPL(dev_pm_set_dedicated_wake_irq_reverse); + /** * dev_pm_enable_wake_irq - Enable device wake-up interrupt * @dev: Device @@ -296,25 +328,56 @@ void dev_pm_enable_wake_irq_check(struct device *dev, return; enable: - enable_irq(wirq->irq); + if (!can_change_status || !(wirq->status & WAKE_IRQ_DEDICATED_REVERSE)) { + enable_irq(wirq->irq); + wirq->status |= WAKE_IRQ_DEDICATED_ENABLED; + } } /** * dev_pm_disable_wake_irq_check - Checks and disables wake-up interrupt * @dev: Device + * @cond_disable: if set, also check WAKE_IRQ_DEDICATED_REVERSE * * Disables wake-up interrupt conditionally based on status. * Should be only called from rpm_suspend() and rpm_resume() path. */ -void dev_pm_disable_wake_irq_check(struct device *dev) +void dev_pm_disable_wake_irq_check(struct device *dev, bool cond_disable) { struct wake_irq *wirq = dev->power.wakeirq; if (!wirq || !((wirq->status & WAKE_IRQ_DEDICATED_MASK))) return; - if (wirq->status & WAKE_IRQ_DEDICATED_MANAGED) + if (cond_disable && (wirq->status & WAKE_IRQ_DEDICATED_REVERSE)) + return; + + if (wirq->status & WAKE_IRQ_DEDICATED_MANAGED) { + wirq->status &= ~WAKE_IRQ_DEDICATED_ENABLED; disable_irq_nosync(wirq->irq); + } +} + +/** + * dev_pm_enable_wake_irq_complete - enable wake IRQ not enabled before + * @dev: Device using the wake IRQ + * + * Enable wake IRQ conditionally based on status, mainly used if want to + * enable wake IRQ after running ->runtime_suspend() which depends on + * WAKE_IRQ_DEDICATED_REVERSE. + * + * Should be only called from rpm_suspend() path. + */ +void dev_pm_enable_wake_irq_complete(struct device *dev) +{ + struct wake_irq *wirq = dev->power.wakeirq; + + if (!wirq || !(wirq->status & WAKE_IRQ_DEDICATED_MASK)) + return; + + if (wirq->status & WAKE_IRQ_DEDICATED_MANAGED && + wirq->status & WAKE_IRQ_DEDICATED_REVERSE) + enable_irq(wirq->irq); } /** @@ -331,7 +394,7 @@ void dev_pm_arm_wake_irq(struct wake_irq *wirq) if (device_may_wakeup(wirq->dev)) { if (wirq->status & WAKE_IRQ_DEDICATED_ALLOCATED && - !pm_runtime_status_suspended(wirq->dev)) + !(wirq->status & WAKE_IRQ_DEDICATED_ENABLED)) enable_irq(wirq->irq); enable_irq_wake(wirq->irq); @@ -354,7 +417,7 @@ void dev_pm_disarm_wake_irq(struct wake_irq *wirq) disable_irq_wake(wirq->irq); if (wirq->status & WAKE_IRQ_DEDICATED_ALLOCATED && - !pm_runtime_status_suspended(wirq->dev)) + !(wirq->status & WAKE_IRQ_DEDICATED_ENABLED)) disable_irq_nosync(wirq->irq); } } diff --git a/drivers/base/regmap/regcache-rbtree.c b/drivers/base/regmap/regcache-rbtree.c index e9b7ce8c272c6cc39af3687a1ed0119e5a5a4be5..b6f8f4059e255407d40a54a1d534835e4e8225ea 100644 --- a/drivers/base/regmap/regcache-rbtree.c +++ b/drivers/base/regmap/regcache-rbtree.c @@ -291,7 +291,7 @@ static int regcache_rbtree_insert_to_block(struct regmap *map, blk = krealloc(rbnode->block, blklen * map->cache_word_size, - GFP_KERNEL); + map->alloc_flags); if (!blk) return -ENOMEM; @@ -300,7 +300,7 @@ static int regcache_rbtree_insert_to_block(struct regmap *map, if (BITS_TO_LONGS(blklen) > BITS_TO_LONGS(rbnode->blklen)) { present = krealloc(rbnode->cache_present, BITS_TO_LONGS(blklen) * sizeof(*present), - GFP_KERNEL); + map->alloc_flags); if (!present) return -ENOMEM; @@ -334,7 +334,7 @@ regcache_rbtree_node_alloc(struct regmap *map, unsigned int reg) const struct regmap_range *range; int i; - rbnode = kzalloc(sizeof(*rbnode), GFP_KERNEL); + rbnode = kzalloc(sizeof(*rbnode), map->alloc_flags); if (!rbnode) return NULL; @@ -360,13 +360,13 @@ regcache_rbtree_node_alloc(struct regmap *map, unsigned int reg) } rbnode->block = kmalloc_array(rbnode->blklen, map->cache_word_size, - GFP_KERNEL); + map->alloc_flags); if (!rbnode->block) goto err_free; rbnode->cache_present = kcalloc(BITS_TO_LONGS(rbnode->blklen), sizeof(*rbnode->cache_present), - GFP_KERNEL); + map->alloc_flags); if (!rbnode->cache_present) goto err_free_block; @@ -467,7 +467,8 @@ static int regcache_rbtree_write(struct regmap *map, unsigned int reg, if (!rbnode) return -ENOMEM; regcache_rbtree_set_register(map, rbnode, - reg - rbnode->base_reg, value); + (reg - rbnode->base_reg) / map->reg_stride, + value); regcache_rbtree_insert(map, &rbtree_ctx->root, rbnode); rbtree_ctx->cached_rbnode = rbnode; } diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c index 773560348337fed60b363ee8f40e341fcc2044b7..b78e4b6e2c9dac25cbd29137ef466a1040b80707 100644 --- a/drivers/base/regmap/regcache.c +++ b/drivers/base/regmap/regcache.c @@ -347,6 +347,9 @@ int regcache_sync(struct regmap *map) const char *name; bool bypass; + if (WARN_ON(map->cache_type == REGCACHE_NONE)) + return -EINVAL; + BUG_ON(!map->cache_ops); map->lock(map->lock_arg); @@ -416,6 +419,9 @@ int regcache_sync_region(struct regmap *map, unsigned int min, const char *name; bool bypass; + if (WARN_ON(map->cache_type == REGCACHE_NONE)) + return -EINVAL; + BUG_ON(!map->cache_ops); map->lock(map->lock_arg); diff --git a/drivers/base/regmap/regmap-debugfs.c b/drivers/base/regmap/regmap-debugfs.c index 639b7e8f911334d039293a350a469a24e4f3ebf1..ac6aaf9464ff09f14ab809045007d2cbe53d251c 100644 --- a/drivers/base/regmap/regmap-debugfs.c +++ b/drivers/base/regmap/regmap-debugfs.c @@ -53,7 +53,7 @@ static ssize_t regmap_name_read_file(struct file *file, name = map->dev->driver->name; ret = snprintf(buf, PAGE_SIZE, "%s\n", name); - if (ret < 0) { + if (ret >= PAGE_SIZE) { kfree(buf); return ret; } diff --git a/drivers/base/regmap/regmap-i2c.c b/drivers/base/regmap/regmap-i2c.c index 056acde5e7d34221ab43923719676f7e66a7ceb0..4b9d68af090b27146b2f6a338115538701a84b24 100644 --- a/drivers/base/regmap/regmap-i2c.c +++ b/drivers/base/regmap/regmap-i2c.c @@ -246,8 +246,8 @@ static int regmap_i2c_smbus_i2c_read(void *context, const void *reg, static struct regmap_bus regmap_i2c_smbus_i2c_block = { .write = regmap_i2c_smbus_i2c_write, .read = regmap_i2c_smbus_i2c_read, - .max_raw_read = I2C_SMBUS_BLOCK_MAX, - .max_raw_write = I2C_SMBUS_BLOCK_MAX, + .max_raw_read = I2C_SMBUS_BLOCK_MAX - 1, + .max_raw_write = I2C_SMBUS_BLOCK_MAX - 1, }; static const struct regmap_bus *regmap_get_i2c_bus(struct i2c_client *i2c, diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index 330ab9c85d1b88eb56a628ae8c2a5c9ea07a91b3..5e03735374ae23fe1f77fb0214c18ac69870194f 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -1343,7 +1343,7 @@ static int dev_get_regmap_match(struct device *dev, void *res, void *data) /* If the user didn't specify a name match any */ if (data) - return !strcmp((*r)->name, data); + return (*r)->name && !strcmp((*r)->name, data); else return 1; } @@ -1825,6 +1825,8 @@ int _regmap_raw_write(struct regmap *map, unsigned int reg, size_t val_count = val_len / val_bytes; size_t chunk_count, chunk_bytes; size_t chunk_regs = val_count; + size_t max_data = map->max_raw_write - map->format.reg_bytes - + map->format.pad_bytes; int ret, i; if (!val_count) @@ -1832,8 +1834,8 @@ int _regmap_raw_write(struct regmap *map, unsigned int reg, if (map->use_single_write) chunk_regs = 1; - else if (map->max_raw_write && val_len > map->max_raw_write) - chunk_regs = map->max_raw_write / val_bytes; + else if (map->max_raw_write && val_len > max_data) + chunk_regs = max_data / val_bytes; chunk_count = val_count / chunk_regs; chunk_bytes = chunk_regs * val_bytes; diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index e21e6f0314af8780849c29ecdd20bffcdc369572..b19cb945baf15320861492eed46e037a11749472 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -311,15 +311,6 @@ config BLK_DEV_SKD Use device /dev/skd$N amd /dev/skd$Np$M. -config BLK_DEV_SX8 - tristate "Promise SATA SX8 support" - depends on PCI - ---help--- - Saying Y or M here will enable support for the - Promise SATA SX8 controllers. - - Use devices /dev/sx8/$N and /dev/sx8/$Np$M. - config BLK_DEV_RAM tristate "RAM block device support" ---help--- diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 28a563a592a0ed4fb6102e7c8f2e21cdf6705e25..0f31580378102e05744a8961ac74030099157520 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -27,8 +27,6 @@ obj-$(CONFIG_BLK_DEV_NBD) += nbd.o obj-$(CONFIG_BLK_DEV_CRYPTOLOOP) += cryptoloop.o obj-$(CONFIG_VIRTIO_BLK) += virtio_blk.o -obj-$(CONFIG_BLK_DEV_SX8) += sx8.o - obj-$(CONFIG_XEN_BLKDEV_FRONTEND) += xen-blkfront.o obj-$(CONFIG_XEN_BLKDEV_BACKEND) += xen-blkback/ obj-$(CONFIG_BLK_DEV_DRBD) += drbd/ diff --git a/drivers/block/drbd/drbd_nl.c b/drivers/block/drbd/drbd_nl.c index 639c76c7c97ae5aa6440f958e7fb888c10704bd2..10b6bcd8829c269cadb46ad0afe6c27e5812a2b6 100644 --- a/drivers/block/drbd/drbd_nl.c +++ b/drivers/block/drbd/drbd_nl.c @@ -3379,7 +3379,7 @@ int drbd_adm_dump_devices(struct sk_buff *skb, struct netlink_callback *cb) { struct nlattr *resource_filter; struct drbd_resource *resource; - struct drbd_device *uninitialized_var(device); + struct drbd_device *device; int minor, err, retcode; struct drbd_genlmsghdr *dh; struct device_info device_info; @@ -3468,7 +3468,7 @@ int drbd_adm_dump_connections(struct sk_buff *skb, struct netlink_callback *cb) { struct nlattr *resource_filter; struct drbd_resource *resource = NULL, *next_resource; - struct drbd_connection *uninitialized_var(connection); + struct drbd_connection *connection; int err = 0, retcode; struct drbd_genlmsghdr *dh; struct connection_info connection_info; @@ -3630,7 +3630,7 @@ int drbd_adm_dump_peer_devices(struct sk_buff *skb, struct netlink_callback *cb) { struct nlattr *resource_filter; struct drbd_resource *resource; - struct drbd_device *uninitialized_var(device); + struct drbd_device *device; struct drbd_peer_device *peer_device = NULL; int minor, err, retcode; struct drbd_genlmsghdr *dh; diff --git a/drivers/block/drbd/drbd_receiver.c b/drivers/block/drbd/drbd_receiver.c index 2bd488bca3eb7e834edb712cda01ebeb847a7669..477d360c262c36e762d12a53afdbc65cb7d564b4 100644 --- a/drivers/block/drbd/drbd_receiver.c +++ b/drivers/block/drbd/drbd_receiver.c @@ -1310,7 +1310,7 @@ static void submit_one_flush(struct drbd_device *device, struct issue_flush_cont bio_set_dev(bio, device->ldev->backing_bdev); bio->bi_private = octx; bio->bi_end_io = one_flush_endio; - bio->bi_opf = REQ_OP_FLUSH | REQ_PREFLUSH; + bio->bi_opf = REQ_OP_WRITE | REQ_PREFLUSH; device->flush_jif = jiffies; set_bit(FLUSH_PENDING, &device->flags); diff --git a/drivers/block/loop.c b/drivers/block/loop.c index 10871408096433728b45bd2b59f0a799d931d7a7..473eb7019589f6f2f1df09ff74fd89636ee9bc52 100644 --- a/drivers/block/loop.c +++ b/drivers/block/loop.c @@ -2078,7 +2078,8 @@ static int loop_add(struct loop_device **l, int i) lo->tag_set.queue_depth = 128; lo->tag_set.numa_node = NUMA_NO_NODE; lo->tag_set.cmd_size = sizeof(struct loop_cmd); - lo->tag_set.flags = BLK_MQ_F_SHOULD_MERGE | BLK_MQ_F_SG_MERGE; + lo->tag_set.flags = BLK_MQ_F_SHOULD_MERGE | BLK_MQ_F_SG_MERGE | + BLK_MQ_F_NO_SCHED; lo->tag_set.driver_data = lo; err = blk_mq_alloc_tag_set(&lo->tag_set); diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c index cc66983e8b6ab317df8e3c846dba259407e1fcd9..5a07964a1e67617b522977315357dd2b3e0abe20 100644 --- a/drivers/block/nbd.c +++ b/drivers/block/nbd.c @@ -1547,7 +1547,7 @@ static int nbd_dev_dbg_init(struct nbd_device *nbd) return -EIO; dir = debugfs_create_dir(nbd_name(nbd), nbd_dbg_dir); - if (!dir) { + if (IS_ERR(dir)) { dev_err(nbd_to_dev(nbd), "Failed to create debugfs dir for '%s'\n", nbd_name(nbd)); return -EIO; @@ -1573,7 +1573,7 @@ static int nbd_dbg_init(void) struct dentry *dbg_dir; dbg_dir = debugfs_create_dir("nbd", NULL); - if (!dbg_dir) + if (IS_ERR(dbg_dir)) return -EIO; nbd_dbg_dir = dbg_dir; @@ -1646,7 +1646,8 @@ static int nbd_dev_add(int index) if (err == -ENOSPC) err = -EEXIST; } else { - err = idr_alloc(&nbd_index_idr, nbd, 0, 0, GFP_KERNEL); + err = idr_alloc(&nbd_index_idr, nbd, 0, + (MINORMASK >> part_shift) + 1, GFP_KERNEL); if (err >= 0) index = err; } diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c index 9f1265ce2e36507641c8a20daeb553733673d2d4..6edd642b7ab62a64c50d2a762e935f6e9cda86dd 100644 --- a/drivers/block/rbd.c +++ b/drivers/block/rbd.c @@ -4381,8 +4381,7 @@ static void rbd_dev_release(struct device *dev) module_put(THIS_MODULE); } -static struct rbd_device *__rbd_dev_create(struct rbd_client *rbdc, - struct rbd_spec *spec) +static struct rbd_device *__rbd_dev_create(struct rbd_spec *spec) { struct rbd_device *rbd_dev; @@ -4421,9 +4420,6 @@ static struct rbd_device *__rbd_dev_create(struct rbd_client *rbdc, rbd_dev->dev.parent = &rbd_root_dev; device_initialize(&rbd_dev->dev); - rbd_dev->rbd_client = rbdc; - rbd_dev->spec = spec; - return rbd_dev; } @@ -4436,12 +4432,10 @@ static struct rbd_device *rbd_dev_create(struct rbd_client *rbdc, { struct rbd_device *rbd_dev; - rbd_dev = __rbd_dev_create(rbdc, spec); + rbd_dev = __rbd_dev_create(spec); if (!rbd_dev) return NULL; - rbd_dev->opts = opts; - /* get an id and fill in device name */ rbd_dev->dev_id = ida_simple_get(&rbd_dev_id_ida, 0, minor_to_rbd_dev_id(1 << MINORBITS), @@ -4458,6 +4452,10 @@ static struct rbd_device *rbd_dev_create(struct rbd_client *rbdc, /* we have a ref from do_rbd_add() */ __module_get(THIS_MODULE); + rbd_dev->rbd_client = rbdc; + rbd_dev->spec = spec; + rbd_dev->opts = opts; + dout("%s rbd_dev %p dev_id %d\n", __func__, rbd_dev, rbd_dev->dev_id); return rbd_dev; @@ -5618,7 +5616,7 @@ static int rbd_dev_probe_parent(struct rbd_device *rbd_dev, int depth) goto out_err; } - parent = __rbd_dev_create(rbd_dev->rbd_client, rbd_dev->parent_spec); + parent = __rbd_dev_create(rbd_dev->parent_spec); if (!parent) { ret = -ENOMEM; goto out_err; @@ -5628,8 +5626,8 @@ static int rbd_dev_probe_parent(struct rbd_device *rbd_dev, int depth) * Images related by parent/child relationships always share * rbd_client and spec/parent_spec, so bump their refcounts. */ - __rbd_get_client(rbd_dev->rbd_client); - rbd_spec_get(rbd_dev->parent_spec); + parent->rbd_client = __rbd_get_client(rbd_dev->rbd_client); + parent->spec = rbd_spec_get(rbd_dev->parent_spec); ret = rbd_dev_image_probe(parent, depth); if (ret < 0) diff --git a/drivers/block/sunvdc.c b/drivers/block/sunvdc.c index 5d7024057540aa154854686c3b48337d4226db5b..47cd3ea7b660004dda213a15aa96678d74f91b7d 100644 --- a/drivers/block/sunvdc.c +++ b/drivers/block/sunvdc.c @@ -947,6 +947,8 @@ static int vdc_port_probe(struct vio_dev *vdev, const struct vio_device_id *id) print_version(); hp = mdesc_grab(); + if (!hp) + return -ENODEV; err = -ENODEV; if ((vdev->dev_no << PARTITION_SHIFT) & ~(u64)MINORMASK) { diff --git a/drivers/block/sx8.c b/drivers/block/sx8.c deleted file mode 100644 index 4d90e5eba2f5e27d9f217696c5ec0c0f5e5f7be3..0000000000000000000000000000000000000000 --- a/drivers/block/sx8.c +++ /dev/null @@ -1,1746 +0,0 @@ -/* - * sx8.c: Driver for Promise SATA SX8 looks-like-I2O hardware - * - * Copyright 2004-2005 Red Hat, Inc. - * - * Author/maintainer: Jeff Garzik - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if 0 -#define CARM_DEBUG -#define CARM_VERBOSE_DEBUG -#else -#undef CARM_DEBUG -#undef CARM_VERBOSE_DEBUG -#endif -#undef CARM_NDEBUG - -#define DRV_NAME "sx8" -#define DRV_VERSION "1.0" -#define PFX DRV_NAME ": " - -MODULE_AUTHOR("Jeff Garzik"); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("Promise SATA SX8 block driver"); -MODULE_VERSION(DRV_VERSION); - -/* - * SX8 hardware has a single message queue for all ATA ports. - * When this driver was written, the hardware (firmware?) would - * corrupt data eventually, if more than one request was outstanding. - * As one can imagine, having 8 ports bottlenecking on a single - * command hurts performance. - * - * Based on user reports, later versions of the hardware (firmware?) - * seem to be able to survive with more than one command queued. - * - * Therefore, we default to the safe option -- 1 command -- but - * allow the user to increase this. - * - * SX8 should be able to support up to ~60 queued commands (CARM_MAX_REQ), - * but problems seem to occur when you exceed ~30, even on newer hardware. - */ -static int max_queue = 1; -module_param(max_queue, int, 0444); -MODULE_PARM_DESC(max_queue, "Maximum number of queued commands. (min==1, max==30, safe==1)"); - - -#define NEXT_RESP(idx) ((idx + 1) % RMSG_Q_LEN) - -/* 0xf is just arbitrary, non-zero noise; this is sorta like poisoning */ -#define TAG_ENCODE(tag) (((tag) << 16) | 0xf) -#define TAG_DECODE(tag) (((tag) >> 16) & 0x1f) -#define TAG_VALID(tag) ((((tag) & 0xf) == 0xf) && (TAG_DECODE(tag) < 32)) - -/* note: prints function name for you */ -#ifdef CARM_DEBUG -#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) -#ifdef CARM_VERBOSE_DEBUG -#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) -#else -#define VPRINTK(fmt, args...) -#endif /* CARM_VERBOSE_DEBUG */ -#else -#define DPRINTK(fmt, args...) -#define VPRINTK(fmt, args...) -#endif /* CARM_DEBUG */ - -#ifdef CARM_NDEBUG -#define assert(expr) -#else -#define assert(expr) \ - if(unlikely(!(expr))) { \ - printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \ - #expr, __FILE__, __func__, __LINE__); \ - } -#endif - -/* defines only for the constants which don't work well as enums */ -struct carm_host; - -enum { - /* adapter-wide limits */ - CARM_MAX_PORTS = 8, - CARM_SHM_SIZE = (4096 << 7), - CARM_MINORS_PER_MAJOR = 256 / CARM_MAX_PORTS, - CARM_MAX_WAIT_Q = CARM_MAX_PORTS + 1, - - /* command message queue limits */ - CARM_MAX_REQ = 64, /* max command msgs per host */ - CARM_MSG_LOW_WATER = (CARM_MAX_REQ / 4), /* refill mark */ - - /* S/G limits, host-wide and per-request */ - CARM_MAX_REQ_SG = 32, /* max s/g entries per request */ - CARM_MAX_HOST_SG = 600, /* max s/g entries per host */ - CARM_SG_LOW_WATER = (CARM_MAX_HOST_SG / 4), /* re-fill mark */ - - /* hardware registers */ - CARM_IHQP = 0x1c, - CARM_INT_STAT = 0x10, /* interrupt status */ - CARM_INT_MASK = 0x14, /* interrupt mask */ - CARM_HMUC = 0x18, /* host message unit control */ - RBUF_ADDR_LO = 0x20, /* response msg DMA buf low 32 bits */ - RBUF_ADDR_HI = 0x24, /* response msg DMA buf high 32 bits */ - RBUF_BYTE_SZ = 0x28, - CARM_RESP_IDX = 0x2c, - CARM_CMS0 = 0x30, /* command message size reg 0 */ - CARM_LMUC = 0x48, - CARM_HMPHA = 0x6c, - CARM_INITC = 0xb5, - - /* bits in CARM_INT_{STAT,MASK} */ - INT_RESERVED = 0xfffffff0, - INT_WATCHDOG = (1 << 3), /* watchdog timer */ - INT_Q_OVERFLOW = (1 << 2), /* cmd msg q overflow */ - INT_Q_AVAILABLE = (1 << 1), /* cmd msg q has free space */ - INT_RESPONSE = (1 << 0), /* response msg available */ - INT_ACK_MASK = INT_WATCHDOG | INT_Q_OVERFLOW, - INT_DEF_MASK = INT_RESERVED | INT_Q_OVERFLOW | - INT_RESPONSE, - - /* command messages, and related register bits */ - CARM_HAVE_RESP = 0x01, - CARM_MSG_READ = 1, - CARM_MSG_WRITE = 2, - CARM_MSG_VERIFY = 3, - CARM_MSG_GET_CAPACITY = 4, - CARM_MSG_FLUSH = 5, - CARM_MSG_IOCTL = 6, - CARM_MSG_ARRAY = 8, - CARM_MSG_MISC = 9, - CARM_CME = (1 << 2), - CARM_RME = (1 << 1), - CARM_WZBC = (1 << 0), - CARM_RMI = (1 << 0), - CARM_Q_FULL = (1 << 3), - CARM_MSG_SIZE = 288, - CARM_Q_LEN = 48, - - /* CARM_MSG_IOCTL messages */ - CARM_IOC_SCAN_CHAN = 5, /* scan channels for devices */ - CARM_IOC_GET_TCQ = 13, /* get tcq/ncq depth */ - CARM_IOC_SET_TCQ = 14, /* set tcq/ncq depth */ - - IOC_SCAN_CHAN_NODEV = 0x1f, - IOC_SCAN_CHAN_OFFSET = 0x40, - - /* CARM_MSG_ARRAY messages */ - CARM_ARRAY_INFO = 0, - - ARRAY_NO_EXIST = (1 << 31), - - /* response messages */ - RMSG_SZ = 8, /* sizeof(struct carm_response) */ - RMSG_Q_LEN = 48, /* resp. msg list length */ - RMSG_OK = 1, /* bit indicating msg was successful */ - /* length of entire resp. msg buffer */ - RBUF_LEN = RMSG_SZ * RMSG_Q_LEN, - - PDC_SHM_SIZE = (4096 << 7), /* length of entire h/w buffer */ - - /* CARM_MSG_MISC messages */ - MISC_GET_FW_VER = 2, - MISC_ALLOC_MEM = 3, - MISC_SET_TIME = 5, - - /* MISC_GET_FW_VER feature bits */ - FW_VER_4PORT = (1 << 2), /* 1=4 ports, 0=8 ports */ - FW_VER_NON_RAID = (1 << 1), /* 1=non-RAID firmware, 0=RAID */ - FW_VER_ZCR = (1 << 0), /* zero channel RAID (whatever that is) */ - - /* carm_host flags */ - FL_NON_RAID = FW_VER_NON_RAID, - FL_4PORT = FW_VER_4PORT, - FL_FW_VER_MASK = (FW_VER_NON_RAID | FW_VER_4PORT), - FL_DAC = (1 << 16), - FL_DYN_MAJOR = (1 << 17), -}; - -enum { - CARM_SG_BOUNDARY = 0xffffUL, /* s/g segment boundary */ -}; - -enum scatter_gather_types { - SGT_32BIT = 0, - SGT_64BIT = 1, -}; - -enum host_states { - HST_INVALID, /* invalid state; never used */ - HST_ALLOC_BUF, /* setting up master SHM area */ - HST_ERROR, /* we never leave here */ - HST_PORT_SCAN, /* start dev scan */ - HST_DEV_SCAN_START, /* start per-device probe */ - HST_DEV_SCAN, /* continue per-device probe */ - HST_DEV_ACTIVATE, /* activate devices we found */ - HST_PROBE_FINISHED, /* probe is complete */ - HST_PROBE_START, /* initiate probe */ - HST_SYNC_TIME, /* tell firmware what time it is */ - HST_GET_FW_VER, /* get firmware version, adapter port cnt */ -}; - -#ifdef CARM_DEBUG -static const char *state_name[] = { - "HST_INVALID", - "HST_ALLOC_BUF", - "HST_ERROR", - "HST_PORT_SCAN", - "HST_DEV_SCAN_START", - "HST_DEV_SCAN", - "HST_DEV_ACTIVATE", - "HST_PROBE_FINISHED", - "HST_PROBE_START", - "HST_SYNC_TIME", - "HST_GET_FW_VER", -}; -#endif - -struct carm_port { - unsigned int port_no; - struct gendisk *disk; - struct carm_host *host; - - /* attached device characteristics */ - u64 capacity; - char name[41]; - u16 dev_geom_head; - u16 dev_geom_sect; - u16 dev_geom_cyl; -}; - -struct carm_request { - unsigned int tag; - int n_elem; - unsigned int msg_type; - unsigned int msg_subtype; - unsigned int msg_bucket; - struct request *rq; - struct carm_port *port; - struct scatterlist sg[CARM_MAX_REQ_SG]; -}; - -struct carm_host { - unsigned long flags; - void __iomem *mmio; - void *shm; - dma_addr_t shm_dma; - - int major; - int id; - char name[32]; - - spinlock_t lock; - struct pci_dev *pdev; - unsigned int state; - u32 fw_ver; - - struct request_queue *oob_q; - unsigned int n_oob; - - unsigned int hw_sg_used; - - unsigned int resp_idx; - - unsigned int wait_q_prod; - unsigned int wait_q_cons; - struct request_queue *wait_q[CARM_MAX_WAIT_Q]; - - unsigned int n_msgs; - u64 msg_alloc; - struct carm_request req[CARM_MAX_REQ]; - void *msg_base; - dma_addr_t msg_dma; - - int cur_scan_dev; - unsigned long dev_active; - unsigned long dev_present; - struct carm_port port[CARM_MAX_PORTS]; - - struct work_struct fsm_task; - - struct completion probe_comp; -}; - -struct carm_response { - __le32 ret_handle; - __le32 status; -} __attribute__((packed)); - -struct carm_msg_sg { - __le32 start; - __le32 len; -} __attribute__((packed)); - -struct carm_msg_rw { - u8 type; - u8 id; - u8 sg_count; - u8 sg_type; - __le32 handle; - __le32 lba; - __le16 lba_count; - __le16 lba_high; - struct carm_msg_sg sg[32]; -} __attribute__((packed)); - -struct carm_msg_allocbuf { - u8 type; - u8 subtype; - u8 n_sg; - u8 sg_type; - __le32 handle; - __le32 addr; - __le32 len; - __le32 evt_pool; - __le32 n_evt; - __le32 rbuf_pool; - __le32 n_rbuf; - __le32 msg_pool; - __le32 n_msg; - struct carm_msg_sg sg[8]; -} __attribute__((packed)); - -struct carm_msg_ioctl { - u8 type; - u8 subtype; - u8 array_id; - u8 reserved1; - __le32 handle; - __le32 data_addr; - u32 reserved2; -} __attribute__((packed)); - -struct carm_msg_sync_time { - u8 type; - u8 subtype; - u16 reserved1; - __le32 handle; - u32 reserved2; - __le32 timestamp; -} __attribute__((packed)); - -struct carm_msg_get_fw_ver { - u8 type; - u8 subtype; - u16 reserved1; - __le32 handle; - __le32 data_addr; - u32 reserved2; -} __attribute__((packed)); - -struct carm_fw_ver { - __le32 version; - u8 features; - u8 reserved1; - u16 reserved2; -} __attribute__((packed)); - -struct carm_array_info { - __le32 size; - - __le16 size_hi; - __le16 stripe_size; - - __le32 mode; - - __le16 stripe_blk_sz; - __le16 reserved1; - - __le16 cyl; - __le16 head; - - __le16 sect; - u8 array_id; - u8 reserved2; - - char name[40]; - - __le32 array_status; - - /* device list continues beyond this point? */ -} __attribute__((packed)); - -static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); -static void carm_remove_one (struct pci_dev *pdev); -static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo); - -static const struct pci_device_id carm_pci_tbl[] = { - { PCI_VENDOR_ID_PROMISE, 0x8000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, - { PCI_VENDOR_ID_PROMISE, 0x8002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, - { } /* terminate list */ -}; -MODULE_DEVICE_TABLE(pci, carm_pci_tbl); - -static struct pci_driver carm_driver = { - .name = DRV_NAME, - .id_table = carm_pci_tbl, - .probe = carm_init_one, - .remove = carm_remove_one, -}; - -static const struct block_device_operations carm_bd_ops = { - .owner = THIS_MODULE, - .getgeo = carm_bdev_getgeo, -}; - -static unsigned int carm_host_id; -static unsigned long carm_major_alloc; - - - -static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo) -{ - struct carm_port *port = bdev->bd_disk->private_data; - - geo->heads = (u8) port->dev_geom_head; - geo->sectors = (u8) port->dev_geom_sect; - geo->cylinders = port->dev_geom_cyl; - return 0; -} - -static const u32 msg_sizes[] = { 32, 64, 128, CARM_MSG_SIZE }; - -static inline int carm_lookup_bucket(u32 msg_size) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(msg_sizes); i++) - if (msg_size <= msg_sizes[i]) - return i; - - return -ENOENT; -} - -static void carm_init_buckets(void __iomem *mmio) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(msg_sizes); i++) - writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i)); -} - -static inline void *carm_ref_msg(struct carm_host *host, - unsigned int msg_idx) -{ - return host->msg_base + (msg_idx * CARM_MSG_SIZE); -} - -static inline dma_addr_t carm_ref_msg_dma(struct carm_host *host, - unsigned int msg_idx) -{ - return host->msg_dma + (msg_idx * CARM_MSG_SIZE); -} - -static int carm_send_msg(struct carm_host *host, - struct carm_request *crq) -{ - void __iomem *mmio = host->mmio; - u32 msg = (u32) carm_ref_msg_dma(host, crq->tag); - u32 cm_bucket = crq->msg_bucket; - u32 tmp; - int rc = 0; - - VPRINTK("ENTER\n"); - - tmp = readl(mmio + CARM_HMUC); - if (tmp & CARM_Q_FULL) { -#if 0 - tmp = readl(mmio + CARM_INT_MASK); - tmp |= INT_Q_AVAILABLE; - writel(tmp, mmio + CARM_INT_MASK); - readl(mmio + CARM_INT_MASK); /* flush */ -#endif - DPRINTK("host msg queue full\n"); - rc = -EBUSY; - } else { - writel(msg | (cm_bucket << 1), mmio + CARM_IHQP); - readl(mmio + CARM_IHQP); /* flush */ - } - - return rc; -} - -static struct carm_request *carm_get_request(struct carm_host *host) -{ - unsigned int i; - - /* obey global hardware limit on S/G entries */ - if (host->hw_sg_used >= (CARM_MAX_HOST_SG - CARM_MAX_REQ_SG)) - return NULL; - - for (i = 0; i < max_queue; i++) - if ((host->msg_alloc & (1ULL << i)) == 0) { - struct carm_request *crq = &host->req[i]; - crq->port = NULL; - crq->n_elem = 0; - - host->msg_alloc |= (1ULL << i); - host->n_msgs++; - - assert(host->n_msgs <= CARM_MAX_REQ); - sg_init_table(crq->sg, CARM_MAX_REQ_SG); - return crq; - } - - DPRINTK("no request available, returning NULL\n"); - return NULL; -} - -static int carm_put_request(struct carm_host *host, struct carm_request *crq) -{ - assert(crq->tag < max_queue); - - if (unlikely((host->msg_alloc & (1ULL << crq->tag)) == 0)) - return -EINVAL; /* tried to clear a tag that was not active */ - - assert(host->hw_sg_used >= crq->n_elem); - - host->msg_alloc &= ~(1ULL << crq->tag); - host->hw_sg_used -= crq->n_elem; - host->n_msgs--; - - return 0; -} - -static struct carm_request *carm_get_special(struct carm_host *host) -{ - unsigned long flags; - struct carm_request *crq = NULL; - struct request *rq; - int tries = 5000; - - while (tries-- > 0) { - spin_lock_irqsave(&host->lock, flags); - crq = carm_get_request(host); - spin_unlock_irqrestore(&host->lock, flags); - - if (crq) - break; - msleep(10); - } - - if (!crq) - return NULL; - - rq = blk_get_request(host->oob_q, REQ_OP_DRV_OUT, 0); - if (IS_ERR(rq)) { - spin_lock_irqsave(&host->lock, flags); - carm_put_request(host, crq); - spin_unlock_irqrestore(&host->lock, flags); - return NULL; - } - - crq->rq = rq; - return crq; -} - -static int carm_array_info (struct carm_host *host, unsigned int array_idx) -{ - struct carm_msg_ioctl *ioc; - unsigned int idx; - u32 msg_data; - dma_addr_t msg_dma; - struct carm_request *crq; - int rc; - - crq = carm_get_special(host); - if (!crq) { - rc = -ENOMEM; - goto err_out; - } - - idx = crq->tag; - - ioc = carm_ref_msg(host, idx); - msg_dma = carm_ref_msg_dma(host, idx); - msg_data = (u32) (msg_dma + sizeof(struct carm_array_info)); - - crq->msg_type = CARM_MSG_ARRAY; - crq->msg_subtype = CARM_ARRAY_INFO; - rc = carm_lookup_bucket(sizeof(struct carm_msg_ioctl) + - sizeof(struct carm_array_info)); - BUG_ON(rc < 0); - crq->msg_bucket = (u32) rc; - - memset(ioc, 0, sizeof(*ioc)); - ioc->type = CARM_MSG_ARRAY; - ioc->subtype = CARM_ARRAY_INFO; - ioc->array_id = (u8) array_idx; - ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); - ioc->data_addr = cpu_to_le32(msg_data); - - spin_lock_irq(&host->lock); - assert(host->state == HST_DEV_SCAN_START || - host->state == HST_DEV_SCAN); - spin_unlock_irq(&host->lock); - - DPRINTK("blk_execute_rq_nowait, tag == %u\n", idx); - crq->rq->special = crq; - blk_execute_rq_nowait(host->oob_q, NULL, crq->rq, true, NULL); - - return 0; - -err_out: - spin_lock_irq(&host->lock); - host->state = HST_ERROR; - spin_unlock_irq(&host->lock); - return rc; -} - -typedef unsigned int (*carm_sspc_t)(struct carm_host *, unsigned int, void *); - -static int carm_send_special (struct carm_host *host, carm_sspc_t func) -{ - struct carm_request *crq; - struct carm_msg_ioctl *ioc; - void *mem; - unsigned int idx, msg_size; - int rc; - - crq = carm_get_special(host); - if (!crq) - return -ENOMEM; - - idx = crq->tag; - - mem = carm_ref_msg(host, idx); - - msg_size = func(host, idx, mem); - - ioc = mem; - crq->msg_type = ioc->type; - crq->msg_subtype = ioc->subtype; - rc = carm_lookup_bucket(msg_size); - BUG_ON(rc < 0); - crq->msg_bucket = (u32) rc; - - DPRINTK("blk_execute_rq_nowait, tag == %u\n", idx); - crq->rq->special = crq; - blk_execute_rq_nowait(host->oob_q, NULL, crq->rq, true, NULL); - - return 0; -} - -static unsigned int carm_fill_sync_time(struct carm_host *host, - unsigned int idx, void *mem) -{ - struct carm_msg_sync_time *st = mem; - - time64_t tv = ktime_get_real_seconds(); - - memset(st, 0, sizeof(*st)); - st->type = CARM_MSG_MISC; - st->subtype = MISC_SET_TIME; - st->handle = cpu_to_le32(TAG_ENCODE(idx)); - st->timestamp = cpu_to_le32(tv); - - return sizeof(struct carm_msg_sync_time); -} - -static unsigned int carm_fill_alloc_buf(struct carm_host *host, - unsigned int idx, void *mem) -{ - struct carm_msg_allocbuf *ab = mem; - - memset(ab, 0, sizeof(*ab)); - ab->type = CARM_MSG_MISC; - ab->subtype = MISC_ALLOC_MEM; - ab->handle = cpu_to_le32(TAG_ENCODE(idx)); - ab->n_sg = 1; - ab->sg_type = SGT_32BIT; - ab->addr = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1)); - ab->len = cpu_to_le32(PDC_SHM_SIZE >> 1); - ab->evt_pool = cpu_to_le32(host->shm_dma + (16 * 1024)); - ab->n_evt = cpu_to_le32(1024); - ab->rbuf_pool = cpu_to_le32(host->shm_dma); - ab->n_rbuf = cpu_to_le32(RMSG_Q_LEN); - ab->msg_pool = cpu_to_le32(host->shm_dma + RBUF_LEN); - ab->n_msg = cpu_to_le32(CARM_Q_LEN); - ab->sg[0].start = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1)); - ab->sg[0].len = cpu_to_le32(65536); - - return sizeof(struct carm_msg_allocbuf); -} - -static unsigned int carm_fill_scan_channels(struct carm_host *host, - unsigned int idx, void *mem) -{ - struct carm_msg_ioctl *ioc = mem; - u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + - IOC_SCAN_CHAN_OFFSET); - - memset(ioc, 0, sizeof(*ioc)); - ioc->type = CARM_MSG_IOCTL; - ioc->subtype = CARM_IOC_SCAN_CHAN; - ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); - ioc->data_addr = cpu_to_le32(msg_data); - - /* fill output data area with "no device" default values */ - mem += IOC_SCAN_CHAN_OFFSET; - memset(mem, IOC_SCAN_CHAN_NODEV, CARM_MAX_PORTS); - - return IOC_SCAN_CHAN_OFFSET + CARM_MAX_PORTS; -} - -static unsigned int carm_fill_get_fw_ver(struct carm_host *host, - unsigned int idx, void *mem) -{ - struct carm_msg_get_fw_ver *ioc = mem; - u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + sizeof(*ioc)); - - memset(ioc, 0, sizeof(*ioc)); - ioc->type = CARM_MSG_MISC; - ioc->subtype = MISC_GET_FW_VER; - ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); - ioc->data_addr = cpu_to_le32(msg_data); - - return sizeof(struct carm_msg_get_fw_ver) + - sizeof(struct carm_fw_ver); -} - -static inline void carm_end_request_queued(struct carm_host *host, - struct carm_request *crq, - blk_status_t error) -{ - struct request *req = crq->rq; - int rc; - - __blk_end_request_all(req, error); - - rc = carm_put_request(host, crq); - assert(rc == 0); -} - -static inline void carm_push_q (struct carm_host *host, struct request_queue *q) -{ - unsigned int idx = host->wait_q_prod % CARM_MAX_WAIT_Q; - - blk_stop_queue(q); - VPRINTK("STOPPED QUEUE %p\n", q); - - host->wait_q[idx] = q; - host->wait_q_prod++; - BUG_ON(host->wait_q_prod == host->wait_q_cons); /* overrun */ -} - -static inline struct request_queue *carm_pop_q(struct carm_host *host) -{ - unsigned int idx; - - if (host->wait_q_prod == host->wait_q_cons) - return NULL; - - idx = host->wait_q_cons % CARM_MAX_WAIT_Q; - host->wait_q_cons++; - - return host->wait_q[idx]; -} - -static inline void carm_round_robin(struct carm_host *host) -{ - struct request_queue *q = carm_pop_q(host); - if (q) { - blk_start_queue(q); - VPRINTK("STARTED QUEUE %p\n", q); - } -} - -static inline void carm_end_rq(struct carm_host *host, struct carm_request *crq, - blk_status_t error) -{ - carm_end_request_queued(host, crq, error); - if (max_queue == 1) - carm_round_robin(host); - else if ((host->n_msgs <= CARM_MSG_LOW_WATER) && - (host->hw_sg_used <= CARM_SG_LOW_WATER)) { - carm_round_robin(host); - } -} - -static void carm_oob_rq_fn(struct request_queue *q) -{ - struct carm_host *host = q->queuedata; - struct carm_request *crq; - struct request *rq; - int rc; - - while (1) { - DPRINTK("get req\n"); - rq = blk_fetch_request(q); - if (!rq) - break; - - crq = rq->special; - assert(crq != NULL); - assert(crq->rq == rq); - - crq->n_elem = 0; - - DPRINTK("send req\n"); - rc = carm_send_msg(host, crq); - if (rc) { - blk_requeue_request(q, rq); - carm_push_q(host, q); - return; /* call us again later, eventually */ - } - } -} - -static void carm_rq_fn(struct request_queue *q) -{ - struct carm_port *port = q->queuedata; - struct carm_host *host = port->host; - struct carm_msg_rw *msg; - struct carm_request *crq; - struct request *rq; - struct scatterlist *sg; - int writing = 0, pci_dir, i, n_elem, rc; - u32 tmp; - unsigned int msg_size; - -queue_one_request: - VPRINTK("get req\n"); - rq = blk_peek_request(q); - if (!rq) - return; - - crq = carm_get_request(host); - if (!crq) { - carm_push_q(host, q); - return; /* call us again later, eventually */ - } - crq->rq = rq; - - blk_start_request(rq); - - if (rq_data_dir(rq) == WRITE) { - writing = 1; - pci_dir = PCI_DMA_TODEVICE; - } else { - pci_dir = PCI_DMA_FROMDEVICE; - } - - /* get scatterlist from block layer */ - sg = &crq->sg[0]; - n_elem = blk_rq_map_sg(q, rq, sg); - if (n_elem <= 0) { - carm_end_rq(host, crq, BLK_STS_IOERR); - return; /* request with no s/g entries? */ - } - - /* map scatterlist to PCI bus addresses */ - n_elem = pci_map_sg(host->pdev, sg, n_elem, pci_dir); - if (n_elem <= 0) { - carm_end_rq(host, crq, BLK_STS_IOERR); - return; /* request with no s/g entries? */ - } - crq->n_elem = n_elem; - crq->port = port; - host->hw_sg_used += n_elem; - - /* - * build read/write message - */ - - VPRINTK("build msg\n"); - msg = (struct carm_msg_rw *) carm_ref_msg(host, crq->tag); - - if (writing) { - msg->type = CARM_MSG_WRITE; - crq->msg_type = CARM_MSG_WRITE; - } else { - msg->type = CARM_MSG_READ; - crq->msg_type = CARM_MSG_READ; - } - - msg->id = port->port_no; - msg->sg_count = n_elem; - msg->sg_type = SGT_32BIT; - msg->handle = cpu_to_le32(TAG_ENCODE(crq->tag)); - msg->lba = cpu_to_le32(blk_rq_pos(rq) & 0xffffffff); - tmp = (blk_rq_pos(rq) >> 16) >> 16; - msg->lba_high = cpu_to_le16( (u16) tmp ); - msg->lba_count = cpu_to_le16(blk_rq_sectors(rq)); - - msg_size = sizeof(struct carm_msg_rw) - sizeof(msg->sg); - for (i = 0; i < n_elem; i++) { - struct carm_msg_sg *carm_sg = &msg->sg[i]; - carm_sg->start = cpu_to_le32(sg_dma_address(&crq->sg[i])); - carm_sg->len = cpu_to_le32(sg_dma_len(&crq->sg[i])); - msg_size += sizeof(struct carm_msg_sg); - } - - rc = carm_lookup_bucket(msg_size); - BUG_ON(rc < 0); - crq->msg_bucket = (u32) rc; - - /* - * queue read/write message to hardware - */ - - VPRINTK("send msg, tag == %u\n", crq->tag); - rc = carm_send_msg(host, crq); - if (rc) { - carm_put_request(host, crq); - blk_requeue_request(q, rq); - carm_push_q(host, q); - return; /* call us again later, eventually */ - } - - goto queue_one_request; -} - -static void carm_handle_array_info(struct carm_host *host, - struct carm_request *crq, u8 *mem, - blk_status_t error) -{ - struct carm_port *port; - u8 *msg_data = mem + sizeof(struct carm_array_info); - struct carm_array_info *desc = (struct carm_array_info *) msg_data; - u64 lo, hi; - int cur_port; - size_t slen; - - DPRINTK("ENTER\n"); - - carm_end_rq(host, crq, error); - - if (error) - goto out; - if (le32_to_cpu(desc->array_status) & ARRAY_NO_EXIST) - goto out; - - cur_port = host->cur_scan_dev; - - /* should never occur */ - if ((cur_port < 0) || (cur_port >= CARM_MAX_PORTS)) { - printk(KERN_ERR PFX "BUG: cur_scan_dev==%d, array_id==%d\n", - cur_port, (int) desc->array_id); - goto out; - } - - port = &host->port[cur_port]; - - lo = (u64) le32_to_cpu(desc->size); - hi = (u64) le16_to_cpu(desc->size_hi); - - port->capacity = lo | (hi << 32); - port->dev_geom_head = le16_to_cpu(desc->head); - port->dev_geom_sect = le16_to_cpu(desc->sect); - port->dev_geom_cyl = le16_to_cpu(desc->cyl); - - host->dev_active |= (1 << cur_port); - - strncpy(port->name, desc->name, sizeof(port->name)); - port->name[sizeof(port->name) - 1] = 0; - slen = strlen(port->name); - while (slen && (port->name[slen - 1] == ' ')) { - port->name[slen - 1] = 0; - slen--; - } - - printk(KERN_INFO DRV_NAME "(%s): port %u device %Lu sectors\n", - pci_name(host->pdev), port->port_no, - (unsigned long long) port->capacity); - printk(KERN_INFO DRV_NAME "(%s): port %u device \"%s\"\n", - pci_name(host->pdev), port->port_no, port->name); - -out: - assert(host->state == HST_DEV_SCAN); - schedule_work(&host->fsm_task); -} - -static void carm_handle_scan_chan(struct carm_host *host, - struct carm_request *crq, u8 *mem, - blk_status_t error) -{ - u8 *msg_data = mem + IOC_SCAN_CHAN_OFFSET; - unsigned int i, dev_count = 0; - int new_state = HST_DEV_SCAN_START; - - DPRINTK("ENTER\n"); - - carm_end_rq(host, crq, error); - - if (error) { - new_state = HST_ERROR; - goto out; - } - - /* TODO: scan and support non-disk devices */ - for (i = 0; i < 8; i++) - if (msg_data[i] == 0) { /* direct-access device (disk) */ - host->dev_present |= (1 << i); - dev_count++; - } - - printk(KERN_INFO DRV_NAME "(%s): found %u interesting devices\n", - pci_name(host->pdev), dev_count); - -out: - assert(host->state == HST_PORT_SCAN); - host->state = new_state; - schedule_work(&host->fsm_task); -} - -static void carm_handle_generic(struct carm_host *host, - struct carm_request *crq, blk_status_t error, - int cur_state, int next_state) -{ - DPRINTK("ENTER\n"); - - carm_end_rq(host, crq, error); - - assert(host->state == cur_state); - if (error) - host->state = HST_ERROR; - else - host->state = next_state; - schedule_work(&host->fsm_task); -} - -static inline void carm_handle_rw(struct carm_host *host, - struct carm_request *crq, blk_status_t error) -{ - int pci_dir; - - VPRINTK("ENTER\n"); - - if (rq_data_dir(crq->rq) == WRITE) - pci_dir = PCI_DMA_TODEVICE; - else - pci_dir = PCI_DMA_FROMDEVICE; - - pci_unmap_sg(host->pdev, &crq->sg[0], crq->n_elem, pci_dir); - - carm_end_rq(host, crq, error); -} - -static inline void carm_handle_resp(struct carm_host *host, - __le32 ret_handle_le, u32 status) -{ - u32 handle = le32_to_cpu(ret_handle_le); - unsigned int msg_idx; - struct carm_request *crq; - blk_status_t error = (status == RMSG_OK) ? 0 : BLK_STS_IOERR; - u8 *mem; - - VPRINTK("ENTER, handle == 0x%x\n", handle); - - if (unlikely(!TAG_VALID(handle))) { - printk(KERN_ERR DRV_NAME "(%s): BUG: invalid tag 0x%x\n", - pci_name(host->pdev), handle); - return; - } - - msg_idx = TAG_DECODE(handle); - VPRINTK("tag == %u\n", msg_idx); - - crq = &host->req[msg_idx]; - - /* fast path */ - if (likely(crq->msg_type == CARM_MSG_READ || - crq->msg_type == CARM_MSG_WRITE)) { - carm_handle_rw(host, crq, error); - return; - } - - mem = carm_ref_msg(host, msg_idx); - - switch (crq->msg_type) { - case CARM_MSG_IOCTL: { - switch (crq->msg_subtype) { - case CARM_IOC_SCAN_CHAN: - carm_handle_scan_chan(host, crq, mem, error); - break; - default: - /* unknown / invalid response */ - goto err_out; - } - break; - } - - case CARM_MSG_MISC: { - switch (crq->msg_subtype) { - case MISC_ALLOC_MEM: - carm_handle_generic(host, crq, error, - HST_ALLOC_BUF, HST_SYNC_TIME); - break; - case MISC_SET_TIME: - carm_handle_generic(host, crq, error, - HST_SYNC_TIME, HST_GET_FW_VER); - break; - case MISC_GET_FW_VER: { - struct carm_fw_ver *ver = (struct carm_fw_ver *) - (mem + sizeof(struct carm_msg_get_fw_ver)); - if (!error) { - host->fw_ver = le32_to_cpu(ver->version); - host->flags |= (ver->features & FL_FW_VER_MASK); - } - carm_handle_generic(host, crq, error, - HST_GET_FW_VER, HST_PORT_SCAN); - break; - } - default: - /* unknown / invalid response */ - goto err_out; - } - break; - } - - case CARM_MSG_ARRAY: { - switch (crq->msg_subtype) { - case CARM_ARRAY_INFO: - carm_handle_array_info(host, crq, mem, error); - break; - default: - /* unknown / invalid response */ - goto err_out; - } - break; - } - - default: - /* unknown / invalid response */ - goto err_out; - } - - return; - -err_out: - printk(KERN_WARNING DRV_NAME "(%s): BUG: unhandled message type %d/%d\n", - pci_name(host->pdev), crq->msg_type, crq->msg_subtype); - carm_end_rq(host, crq, BLK_STS_IOERR); -} - -static inline void carm_handle_responses(struct carm_host *host) -{ - void __iomem *mmio = host->mmio; - struct carm_response *resp = (struct carm_response *) host->shm; - unsigned int work = 0; - unsigned int idx = host->resp_idx % RMSG_Q_LEN; - - while (1) { - u32 status = le32_to_cpu(resp[idx].status); - - if (status == 0xffffffff) { - VPRINTK("ending response on index %u\n", idx); - writel(idx << 3, mmio + CARM_RESP_IDX); - break; - } - - /* response to a message we sent */ - else if ((status & (1 << 31)) == 0) { - VPRINTK("handling msg response on index %u\n", idx); - carm_handle_resp(host, resp[idx].ret_handle, status); - resp[idx].status = cpu_to_le32(0xffffffff); - } - - /* asynchronous events the hardware throws our way */ - else if ((status & 0xff000000) == (1 << 31)) { - u8 *evt_type_ptr = (u8 *) &resp[idx]; - u8 evt_type = *evt_type_ptr; - printk(KERN_WARNING DRV_NAME "(%s): unhandled event type %d\n", - pci_name(host->pdev), (int) evt_type); - resp[idx].status = cpu_to_le32(0xffffffff); - } - - idx = NEXT_RESP(idx); - work++; - } - - VPRINTK("EXIT, work==%u\n", work); - host->resp_idx += work; -} - -static irqreturn_t carm_interrupt(int irq, void *__host) -{ - struct carm_host *host = __host; - void __iomem *mmio; - u32 mask; - int handled = 0; - unsigned long flags; - - if (!host) { - VPRINTK("no host\n"); - return IRQ_NONE; - } - - spin_lock_irqsave(&host->lock, flags); - - mmio = host->mmio; - - /* reading should also clear interrupts */ - mask = readl(mmio + CARM_INT_STAT); - - if (mask == 0 || mask == 0xffffffff) { - VPRINTK("no work, mask == 0x%x\n", mask); - goto out; - } - - if (mask & INT_ACK_MASK) - writel(mask, mmio + CARM_INT_STAT); - - if (unlikely(host->state == HST_INVALID)) { - VPRINTK("not initialized yet, mask = 0x%x\n", mask); - goto out; - } - - if (mask & CARM_HAVE_RESP) { - handled = 1; - carm_handle_responses(host); - } - -out: - spin_unlock_irqrestore(&host->lock, flags); - VPRINTK("EXIT\n"); - return IRQ_RETVAL(handled); -} - -static void carm_fsm_task (struct work_struct *work) -{ - struct carm_host *host = - container_of(work, struct carm_host, fsm_task); - unsigned long flags; - unsigned int state; - int rc, i, next_dev; - int reschedule = 0; - int new_state = HST_INVALID; - - spin_lock_irqsave(&host->lock, flags); - state = host->state; - spin_unlock_irqrestore(&host->lock, flags); - - DPRINTK("ENTER, state == %s\n", state_name[state]); - - switch (state) { - case HST_PROBE_START: - new_state = HST_ALLOC_BUF; - reschedule = 1; - break; - - case HST_ALLOC_BUF: - rc = carm_send_special(host, carm_fill_alloc_buf); - if (rc) { - new_state = HST_ERROR; - reschedule = 1; - } - break; - - case HST_SYNC_TIME: - rc = carm_send_special(host, carm_fill_sync_time); - if (rc) { - new_state = HST_ERROR; - reschedule = 1; - } - break; - - case HST_GET_FW_VER: - rc = carm_send_special(host, carm_fill_get_fw_ver); - if (rc) { - new_state = HST_ERROR; - reschedule = 1; - } - break; - - case HST_PORT_SCAN: - rc = carm_send_special(host, carm_fill_scan_channels); - if (rc) { - new_state = HST_ERROR; - reschedule = 1; - } - break; - - case HST_DEV_SCAN_START: - host->cur_scan_dev = -1; - new_state = HST_DEV_SCAN; - reschedule = 1; - break; - - case HST_DEV_SCAN: - next_dev = -1; - for (i = host->cur_scan_dev + 1; i < CARM_MAX_PORTS; i++) - if (host->dev_present & (1 << i)) { - next_dev = i; - break; - } - - if (next_dev >= 0) { - host->cur_scan_dev = next_dev; - rc = carm_array_info(host, next_dev); - if (rc) { - new_state = HST_ERROR; - reschedule = 1; - } - } else { - new_state = HST_DEV_ACTIVATE; - reschedule = 1; - } - break; - - case HST_DEV_ACTIVATE: { - int activated = 0; - for (i = 0; i < CARM_MAX_PORTS; i++) - if (host->dev_active & (1 << i)) { - struct carm_port *port = &host->port[i]; - struct gendisk *disk = port->disk; - - set_capacity(disk, port->capacity); - add_disk(disk); - activated++; - } - - printk(KERN_INFO DRV_NAME "(%s): %d ports activated\n", - pci_name(host->pdev), activated); - - new_state = HST_PROBE_FINISHED; - reschedule = 1; - break; - } - - case HST_PROBE_FINISHED: - complete(&host->probe_comp); - break; - - case HST_ERROR: - /* FIXME: TODO */ - break; - - default: - /* should never occur */ - printk(KERN_ERR PFX "BUG: unknown state %d\n", state); - assert(0); - break; - } - - if (new_state != HST_INVALID) { - spin_lock_irqsave(&host->lock, flags); - host->state = new_state; - spin_unlock_irqrestore(&host->lock, flags); - } - if (reschedule) - schedule_work(&host->fsm_task); -} - -static int carm_init_wait(void __iomem *mmio, u32 bits, unsigned int test_bit) -{ - unsigned int i; - - for (i = 0; i < 50000; i++) { - u32 tmp = readl(mmio + CARM_LMUC); - udelay(100); - - if (test_bit) { - if ((tmp & bits) == bits) - return 0; - } else { - if ((tmp & bits) == 0) - return 0; - } - - cond_resched(); - } - - printk(KERN_ERR PFX "carm_init_wait timeout, bits == 0x%x, test_bit == %s\n", - bits, test_bit ? "yes" : "no"); - return -EBUSY; -} - -static void carm_init_responses(struct carm_host *host) -{ - void __iomem *mmio = host->mmio; - unsigned int i; - struct carm_response *resp = (struct carm_response *) host->shm; - - for (i = 0; i < RMSG_Q_LEN; i++) - resp[i].status = cpu_to_le32(0xffffffff); - - writel(0, mmio + CARM_RESP_IDX); -} - -static int carm_init_host(struct carm_host *host) -{ - void __iomem *mmio = host->mmio; - u32 tmp; - u8 tmp8; - int rc; - - DPRINTK("ENTER\n"); - - writel(0, mmio + CARM_INT_MASK); - - tmp8 = readb(mmio + CARM_INITC); - if (tmp8 & 0x01) { - tmp8 &= ~0x01; - writeb(tmp8, mmio + CARM_INITC); - readb(mmio + CARM_INITC); /* flush */ - - DPRINTK("snooze...\n"); - msleep(5000); - } - - tmp = readl(mmio + CARM_HMUC); - if (tmp & CARM_CME) { - DPRINTK("CME bit present, waiting\n"); - rc = carm_init_wait(mmio, CARM_CME, 1); - if (rc) { - DPRINTK("EXIT, carm_init_wait 1 failed\n"); - return rc; - } - } - if (tmp & CARM_RME) { - DPRINTK("RME bit present, waiting\n"); - rc = carm_init_wait(mmio, CARM_RME, 1); - if (rc) { - DPRINTK("EXIT, carm_init_wait 2 failed\n"); - return rc; - } - } - - tmp &= ~(CARM_RME | CARM_CME); - writel(tmp, mmio + CARM_HMUC); - readl(mmio + CARM_HMUC); /* flush */ - - rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 0); - if (rc) { - DPRINTK("EXIT, carm_init_wait 3 failed\n"); - return rc; - } - - carm_init_buckets(mmio); - - writel(host->shm_dma & 0xffffffff, mmio + RBUF_ADDR_LO); - writel((host->shm_dma >> 16) >> 16, mmio + RBUF_ADDR_HI); - writel(RBUF_LEN, mmio + RBUF_BYTE_SZ); - - tmp = readl(mmio + CARM_HMUC); - tmp |= (CARM_RME | CARM_CME | CARM_WZBC); - writel(tmp, mmio + CARM_HMUC); - readl(mmio + CARM_HMUC); /* flush */ - - rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 1); - if (rc) { - DPRINTK("EXIT, carm_init_wait 4 failed\n"); - return rc; - } - - writel(0, mmio + CARM_HMPHA); - writel(INT_DEF_MASK, mmio + CARM_INT_MASK); - - carm_init_responses(host); - - /* start initialization, probing state machine */ - spin_lock_irq(&host->lock); - assert(host->state == HST_INVALID); - host->state = HST_PROBE_START; - spin_unlock_irq(&host->lock); - schedule_work(&host->fsm_task); - - DPRINTK("EXIT\n"); - return 0; -} - -static int carm_init_disks(struct carm_host *host) -{ - unsigned int i; - int rc = 0; - - for (i = 0; i < CARM_MAX_PORTS; i++) { - struct gendisk *disk; - struct request_queue *q; - struct carm_port *port; - - port = &host->port[i]; - port->host = host; - port->port_no = i; - - disk = alloc_disk(CARM_MINORS_PER_MAJOR); - if (!disk) { - rc = -ENOMEM; - break; - } - - port->disk = disk; - sprintf(disk->disk_name, DRV_NAME "/%u", - (unsigned int) (host->id * CARM_MAX_PORTS) + i); - disk->major = host->major; - disk->first_minor = i * CARM_MINORS_PER_MAJOR; - disk->fops = &carm_bd_ops; - disk->private_data = port; - - q = blk_init_queue(carm_rq_fn, &host->lock); - if (!q) { - rc = -ENOMEM; - break; - } - disk->queue = q; - blk_queue_max_segments(q, CARM_MAX_REQ_SG); - blk_queue_segment_boundary(q, CARM_SG_BOUNDARY); - - q->queuedata = port; - } - - return rc; -} - -static void carm_free_disks(struct carm_host *host) -{ - unsigned int i; - - for (i = 0; i < CARM_MAX_PORTS; i++) { - struct gendisk *disk = host->port[i].disk; - if (disk) { - struct request_queue *q = disk->queue; - - if (disk->flags & GENHD_FL_UP) - del_gendisk(disk); - if (q) - blk_cleanup_queue(q); - put_disk(disk); - } - } -} - -static int carm_init_shm(struct carm_host *host) -{ - host->shm = pci_alloc_consistent(host->pdev, CARM_SHM_SIZE, - &host->shm_dma); - if (!host->shm) - return -ENOMEM; - - host->msg_base = host->shm + RBUF_LEN; - host->msg_dma = host->shm_dma + RBUF_LEN; - - memset(host->shm, 0xff, RBUF_LEN); - memset(host->msg_base, 0, PDC_SHM_SIZE - RBUF_LEN); - - return 0; -} - -static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) -{ - struct carm_host *host; - unsigned int pci_dac; - int rc; - struct request_queue *q; - unsigned int i; - - printk_once(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); - - rc = pci_enable_device(pdev); - if (rc) - return rc; - - rc = pci_request_regions(pdev, DRV_NAME); - if (rc) - goto err_out; - -#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); - if (!rc) { - rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); - if (rc) { - printk(KERN_ERR DRV_NAME "(%s): consistent DMA mask failure\n", - pci_name(pdev)); - goto err_out_regions; - } - pci_dac = 1; - } else { -#endif - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); - if (rc) { - printk(KERN_ERR DRV_NAME "(%s): DMA mask failure\n", - pci_name(pdev)); - goto err_out_regions; - } - pci_dac = 0; -#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ - } -#endif - - host = kzalloc(sizeof(*host), GFP_KERNEL); - if (!host) { - printk(KERN_ERR DRV_NAME "(%s): memory alloc failure\n", - pci_name(pdev)); - rc = -ENOMEM; - goto err_out_regions; - } - - host->pdev = pdev; - host->flags = pci_dac ? FL_DAC : 0; - spin_lock_init(&host->lock); - INIT_WORK(&host->fsm_task, carm_fsm_task); - init_completion(&host->probe_comp); - - for (i = 0; i < ARRAY_SIZE(host->req); i++) - host->req[i].tag = i; - - host->mmio = ioremap(pci_resource_start(pdev, 0), - pci_resource_len(pdev, 0)); - if (!host->mmio) { - printk(KERN_ERR DRV_NAME "(%s): MMIO alloc failure\n", - pci_name(pdev)); - rc = -ENOMEM; - goto err_out_kfree; - } - - rc = carm_init_shm(host); - if (rc) { - printk(KERN_ERR DRV_NAME "(%s): DMA SHM alloc failure\n", - pci_name(pdev)); - goto err_out_iounmap; - } - - q = blk_init_queue(carm_oob_rq_fn, &host->lock); - if (!q) { - printk(KERN_ERR DRV_NAME "(%s): OOB queue alloc failure\n", - pci_name(pdev)); - rc = -ENOMEM; - goto err_out_pci_free; - } - host->oob_q = q; - q->queuedata = host; - - /* - * Figure out which major to use: 160, 161, or dynamic - */ - if (!test_and_set_bit(0, &carm_major_alloc)) - host->major = 160; - else if (!test_and_set_bit(1, &carm_major_alloc)) - host->major = 161; - else - host->flags |= FL_DYN_MAJOR; - - host->id = carm_host_id; - sprintf(host->name, DRV_NAME "%d", carm_host_id); - - rc = register_blkdev(host->major, host->name); - if (rc < 0) - goto err_out_free_majors; - if (host->flags & FL_DYN_MAJOR) - host->major = rc; - - rc = carm_init_disks(host); - if (rc) - goto err_out_blkdev_disks; - - pci_set_master(pdev); - - rc = request_irq(pdev->irq, carm_interrupt, IRQF_SHARED, DRV_NAME, host); - if (rc) { - printk(KERN_ERR DRV_NAME "(%s): irq alloc failure\n", - pci_name(pdev)); - goto err_out_blkdev_disks; - } - - rc = carm_init_host(host); - if (rc) - goto err_out_free_irq; - - DPRINTK("waiting for probe_comp\n"); - wait_for_completion(&host->probe_comp); - - printk(KERN_INFO "%s: pci %s, ports %d, io %llx, irq %u, major %d\n", - host->name, pci_name(pdev), (int) CARM_MAX_PORTS, - (unsigned long long)pci_resource_start(pdev, 0), - pdev->irq, host->major); - - carm_host_id++; - pci_set_drvdata(pdev, host); - return 0; - -err_out_free_irq: - free_irq(pdev->irq, host); -err_out_blkdev_disks: - carm_free_disks(host); - unregister_blkdev(host->major, host->name); -err_out_free_majors: - if (host->major == 160) - clear_bit(0, &carm_major_alloc); - else if (host->major == 161) - clear_bit(1, &carm_major_alloc); - blk_cleanup_queue(host->oob_q); -err_out_pci_free: - pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma); -err_out_iounmap: - iounmap(host->mmio); -err_out_kfree: - kfree(host); -err_out_regions: - pci_release_regions(pdev); -err_out: - pci_disable_device(pdev); - return rc; -} - -static void carm_remove_one (struct pci_dev *pdev) -{ - struct carm_host *host = pci_get_drvdata(pdev); - - if (!host) { - printk(KERN_ERR PFX "BUG: no host data for PCI(%s)\n", - pci_name(pdev)); - return; - } - - free_irq(pdev->irq, host); - carm_free_disks(host); - unregister_blkdev(host->major, host->name); - if (host->major == 160) - clear_bit(0, &carm_major_alloc); - else if (host->major == 161) - clear_bit(1, &carm_major_alloc); - blk_cleanup_queue(host->oob_q); - pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma); - iounmap(host->mmio); - kfree(host); - pci_release_regions(pdev); - pci_disable_device(pdev); -} - -module_pci_driver(carm_driver); diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c index 737d0747e9cdb1472045fad6901f2ca6e4f7edac..69201a3eb3100e50c912cd1c5eaeddcfdaeceabd 100644 --- a/drivers/block/xen-blkfront.c +++ b/drivers/block/xen-blkfront.c @@ -779,7 +779,8 @@ static int blkif_queue_rw_req(struct request *req, struct blkfront_ring_info *ri ring_req->u.rw.handle = info->handle; ring_req->operation = rq_data_dir(req) ? BLKIF_OP_WRITE : BLKIF_OP_READ; - if (req_op(req) == REQ_OP_FLUSH || req->cmd_flags & REQ_FUA) { + if (req_op(req) == REQ_OP_FLUSH || + (req_op(req) == REQ_OP_WRITE && (req->cmd_flags & REQ_FUA))) { /* * Ideally we can do an unordered flush-to-disk. * In case the backend onlysupports barriers, use that. diff --git a/drivers/bluetooth/btfm_slim_slave.c b/drivers/bluetooth/btfm_slim_slave.c index f02e31950093de54961bedee34d09769204b4482..25f2774b65b73300959799c845dee0e004821bf3 100644 --- a/drivers/bluetooth/btfm_slim_slave.c +++ b/drivers/bluetooth/btfm_slim_slave.c @@ -81,14 +81,12 @@ int btfm_slim_slave_enable_port(struct btfmslim *btfmslim, uint8_t port_num, uint8_t reg_val = 0, en; uint8_t rxport_num = 0; uint16_t reg; + uint8_t prev_reg_val = 0; BTFMSLIM_DBG("port(%d) enable(%d)", port_num, enable); if (rxport) { BTFMSLIM_DBG("sample rate is %d", btfmslim->sample_rate); - if (enable && - btfmslim->sample_rate != 44100 && - btfmslim->sample_rate != 88200) { - BTFMSLIM_DBG("setting multichannel bit"); + if (enable) { /* For SCO Rx, A2DP Rx other than 44.1 and 88.2Khz */ if (port_num < 24) { rxport_num = port_num - 16; @@ -102,6 +100,21 @@ int btfm_slim_slave_enable_port(struct btfmslim *btfmslim, uint8_t port_num, rxport_num); } + if (btfmslim->sample_rate == 44100 || + btfmslim->sample_rate == 88200) { + BTFMSLIM_DBG("unsetting multichannel bit"); + ret = btfm_slim_read(btfmslim, reg, 1, + &prev_reg_val, IFD); + if (ret < 0) { + BTFMSLIM_ERR("error %d reading", ret); + prev_reg_val = 0; + } + BTFMSLIM_DBG("prev_reg_val (%d) from reg(%x)", + prev_reg_val, reg); + reg_val = prev_reg_val & ~reg_val; + } else + BTFMSLIM_DBG("setting multichannel bit"); + BTFMSLIM_DBG("writing reg_val (%d) to reg(%x)", reg_val, reg); ret = btfm_slim_write(btfmslim, reg, 1, ®_val, IFD); diff --git a/drivers/bluetooth/btqcomsmd.c b/drivers/bluetooth/btqcomsmd.c index 874172aa8e417b7ef0f45bf2db165ea164685c16..a698b1f6394b2af40f8c2c6163684c1a85b9750c 100644 --- a/drivers/bluetooth/btqcomsmd.c +++ b/drivers/bluetooth/btqcomsmd.c @@ -146,6 +146,21 @@ static int btqcomsmd_setup(struct hci_dev *hdev) return 0; } +static int btqcomsmd_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr) +{ + int ret; + + ret = qca_set_bdaddr_rome(hdev, bdaddr); + if (ret) + return ret; + + /* The firmware stops responding for a while after setting the bdaddr, + * causing timeouts for subsequent commands. Sleep a bit to avoid this. + */ + usleep_range(1000, 10000); + return 0; +} + static int btqcomsmd_probe(struct platform_device *pdev) { struct btqcomsmd *btq; @@ -195,7 +210,7 @@ static int btqcomsmd_probe(struct platform_device *pdev) hdev->close = btqcomsmd_close; hdev->send = btqcomsmd_send; hdev->setup = btqcomsmd_setup; - hdev->set_bdaddr = qca_set_bdaddr_rome; + hdev->set_bdaddr = btqcomsmd_set_bdaddr; ret = hci_register_dev(hdev); if (ret < 0) diff --git a/drivers/bluetooth/btsdio.c b/drivers/bluetooth/btsdio.c index 20142bc77554c0f3400da0506a6158e94722f54b..1325b1df4a8ed51ab78d8d8663c4b008302a053e 100644 --- a/drivers/bluetooth/btsdio.c +++ b/drivers/bluetooth/btsdio.c @@ -356,6 +356,7 @@ static void btsdio_remove(struct sdio_func *func) if (!data) return; + cancel_work_sync(&data->work); hdev = data->hdev; sdio_set_drvdata(func, NULL); diff --git a/drivers/bluetooth/hci_nokia.c b/drivers/bluetooth/hci_nokia.c index 2dc33e65d2d0c957199f1e3c1bf8028d4e09ca88..5f6c6930b5bdfb753adee9bf97e9fdf486031626 100644 --- a/drivers/bluetooth/hci_nokia.c +++ b/drivers/bluetooth/hci_nokia.c @@ -743,7 +743,11 @@ static int nokia_bluetooth_serdev_probe(struct serdev_device *serdev) return err; } - clk_prepare_enable(sysclk); + err = clk_prepare_enable(sysclk); + if (err) { + dev_err(dev, "could not enable sysclk: %d", err); + return err; + } btdev->sysclk_speed = clk_get_rate(sysclk); clk_disable_unprepare(sysclk); diff --git a/drivers/bluetooth/hci_vhci.c b/drivers/bluetooth/hci_vhci.c index 22f9145a426fdd962a17ea9816be43c86a922b8d..29d8b5896d6e424239ddf50a54944271dcb60b2e 100644 --- a/drivers/bluetooth/hci_vhci.c +++ b/drivers/bluetooth/hci_vhci.c @@ -82,7 +82,10 @@ static int vhci_send_frame(struct hci_dev *hdev, struct sk_buff *skb) struct vhci_data *data = hci_get_drvdata(hdev); memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); + + mutex_lock(&data->open_mutex); skb_queue_tail(&data->readq, skb); + mutex_unlock(&data->open_mutex); wake_up_interruptible(&data->read_wait); return 0; diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c index 6a94aa6a22c27ce90ab996277bbc3d5c2da50781..1a0f977904b68df297587d38b32e1c4faddda822 100644 --- a/drivers/bus/imx-weim.c +++ b/drivers/bus/imx-weim.c @@ -146,8 +146,8 @@ static int __init weim_parse_dt(struct platform_device *pdev, const struct of_device_id *of_id = of_match_device(weim_id_table, &pdev->dev); const struct imx_weim_devtype *devtype = of_id->data; + int ret = 0, have_child = 0; struct device_node *child; - int ret, have_child = 0; if (devtype == &imx50_weim_devtype) { ret = imx_weim_gpr_setup(pdev); diff --git a/drivers/bus/mhi/core/mhi_internal.h b/drivers/bus/mhi/core/mhi_internal.h index f078adc92207ece2034ab9e6eef97bcaed744f71..001a944d7f6ccf55fd1f6fbd68a848fc7f393a4c 100644 --- a/drivers/bus/mhi/core/mhi_internal.h +++ b/drivers/bus/mhi/core/mhi_internal.h @@ -808,6 +808,12 @@ static inline void mhi_trigger_resume(struct mhi_controller *mhi_cntrl) pm_wakeup_hard_event(&mhi_cntrl->mhi_dev->dev); } +static inline bool is_valid_ring_ptr(struct mhi_ring *ring, dma_addr_t addr) +{ + return ((addr >= ring->iommu_base && + addr < ring->iommu_base + ring->len) && (addr % 16 == 0)); +} + /* queue transfer buffer */ int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, void *buf, void *cb, size_t buf_len, enum MHI_FLAGS flags); diff --git a/drivers/bus/mhi/core/mhi_main.c b/drivers/bus/mhi/core/mhi_main.c index 3098f3892fd4a2a1f54312f3b2cd70aa256371bc..e4d8943d317e31f5e5de8eb30c80be2c14763ee3 100644 --- a/drivers/bus/mhi/core/mhi_main.c +++ b/drivers/bus/mhi/core/mhi_main.c @@ -1385,6 +1385,13 @@ int mhi_process_tsync_ev_ring(struct mhi_controller *mhi_cntrl, int ret = 0; spin_lock_bh(&mhi_event->lock); + if (!is_valid_ring_ptr(ev_ring, er_ctxt->rp)) { + MHI_ERR( + "Event ring rp points outside of the event ring or unalign rp %llx\n", + er_ctxt->rp); + spin_unlock_bh(&mhi_event->lock); + return 0; + } dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); if (ev_ring->rp == dev_rp) { spin_unlock_bh(&mhi_event->lock); @@ -1477,8 +1484,15 @@ int mhi_process_bw_scale_ev_ring(struct mhi_controller *mhi_cntrl, int result, ret = 0; spin_lock_bh(&mhi_event->lock); - dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); + if (!is_valid_ring_ptr(ev_ring, er_ctxt->rp)) { + MHI_ERR( + "Event ring rp points outside of the event ring or unalign rp %llx\n", + er_ctxt->rp); + spin_unlock_bh(&mhi_event->lock); + return 0; + } + dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); if (ev_ring->rp == dev_rp) { spin_unlock_bh(&mhi_event->lock); goto exit_bw_scale_process; diff --git a/drivers/bus/mhi/devices/mhi_satellite.c b/drivers/bus/mhi/devices/mhi_satellite.c index 24621475a26867ea68a6e04c369740a050bbae94..2f226093157faa99d570ed96dc27f001a05a9521 100644 --- a/drivers/bus/mhi/devices/mhi_satellite.c +++ b/drivers/bus/mhi/devices/mhi_satellite.c @@ -358,7 +358,7 @@ static struct mhi_sat_device *find_sat_dev_by_id( static bool mhi_sat_isvalid_header(struct sat_header *hdr, int len) { /* validate payload size */ - if (len >= sizeof(*hdr) && (len != hdr->payload_size + sizeof(*hdr))) + if (len < sizeof(*hdr) || len != hdr->payload_size + sizeof(*hdr)) return false; /* validate SAT IPC version */ diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index 785c6f3419ccee4c0cc454b33366d0202ecfbb27..9dc44e5144eea116517073b842ef5754302cf4c5 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -144,6 +144,13 @@ #define INIT_MEMLEN_MAX (8*1024*1024) #define MAX_CACHE_BUF_SIZE (8*1024*1024) +/* FastRPC remote subsystem state*/ +enum fastrpc_remote_subsys_state { + SUBSYSTEM_RESTARTING = 0, + SUBSYSTEM_DOWN, + SUBSYSTEM_UP, +}; + #define PERF_END (void)0 #define PERF(enb, cnt, ff) \ @@ -349,7 +356,7 @@ struct fastrpc_channel_ctx { uint64_t ssrcount; void *handle; uint64_t prevssrcount; - int issubsystemup; + int subsystemstate; int vmid; struct secure_vm rhvm; int ramdumpenabled; @@ -415,8 +422,8 @@ struct fastrpc_mmap { int uncached; int secure; uintptr_t attr; - bool is_filemap; - /* flag to indicate map used in process init */ + bool is_filemap; /* flag to indicate map used in process init */ + unsigned int ctx_refs; /* Indicates reference count for context map */ }; enum fastrpc_perfkeys { @@ -849,7 +856,7 @@ static int fastrpc_mmap_remove(struct fastrpc_file *fl, uintptr_t va, hlist_for_each_entry_safe(map, n, &me->maps, hn) { if (map->refs == 1 && map->raddr == va && map->raddr + map->len == va + len && - /* Remove map if not used in process initialization*/ + /* Remove map if not used in process initialization */ !map->is_filemap) { match = map; hlist_del_init(&map->hn); @@ -862,9 +869,10 @@ static int fastrpc_mmap_remove(struct fastrpc_file *fl, uintptr_t va, return 0; } hlist_for_each_entry_safe(map, n, &fl->maps, hn) { - if (map->refs == 1 && map->raddr == va && - map->raddr + map->len == va + len && - /* Remove map if not used in process initialization*/ + /* Remove if only one reference map and no context map */ + if (map->refs == 1 && !map->ctx_refs && + map->raddr == va && map->raddr + map->len == va + len && + /* Remove map if not used in process initialization */ !map->is_filemap) { match = map; hlist_del_init(&map->hn); @@ -903,14 +911,14 @@ static void fastrpc_mmap_free(struct fastrpc_mmap *map, uint32_t flags) map->flags == ADSP_MMAP_REMOTE_HEAP_ADDR) { spin_lock(&me->hlock); map->refs--; - if (!map->refs) + if (!map->refs && !map->ctx_refs) hlist_del_init(&map->hn); spin_unlock(&me->hlock); if (map->refs > 0) return; } else { map->refs--; - if (!map->refs) + if (!map->refs && !map->ctx_refs) hlist_del_init(&map->hn); if (map->refs > 0 && !flags) return; @@ -1009,6 +1017,7 @@ static int fastrpc_mmap_create(struct fastrpc_file *fl, int fd, map->is_filemap = false; map->attr = attr; map->is_filemap = false; + map->ctx_refs = 0; if (mflags == ADSP_MMAP_HEAP_ADDR || mflags == ADSP_MMAP_REMOTE_HEAP_ADDR) { map->apps = me; @@ -1534,8 +1543,11 @@ static void context_free(struct smq_invoke_ctx *ctx) spin_unlock(&ctx->fl->hlock); mutex_lock(&ctx->fl->map_mutex); - for (i = 0; i < nbufs; ++i) + for (i = 0; i < nbufs; ++i) { + if (ctx->maps[i] && ctx->maps[i]->ctx_refs) + ctx->maps[i]->ctx_refs--; fastrpc_mmap_free(ctx->maps[i], 0); + } mutex_unlock(&ctx->fl->map_mutex); fastrpc_buf_free(ctx->buf, 1); @@ -1758,6 +1770,8 @@ static int get_args(uint32_t kernel, struct smq_invoke_ctx *ctx) err = fastrpc_mmap_create(ctx->fl, ctx->fds[i], ctx->attrs[i], buf, len, mflags, &ctx->maps[i]); + if (ctx->maps[i]) + ctx->maps[i]->ctx_refs++; mutex_unlock(&ctx->fl->map_mutex); if (err) goto bail; @@ -1775,9 +1789,14 @@ static int get_args(uint32_t kernel, struct smq_invoke_ctx *ctx) err = fastrpc_mmap_create(ctx->fl, ctx->fds[i], FASTRPC_ATTR_NOVA, 0, 0, dmaflags, &ctx->maps[i]); + if (!err && ctx->maps[i]) + ctx->maps[i]->ctx_refs++; if (err) { - for (j = bufs; j < i; j++) + for (j = bufs; j < i; j++) { + if (ctx->maps[j] && ctx->maps[j]->ctx_refs) + ctx->maps[j]->ctx_refs--; fastrpc_mmap_free(ctx->maps[j], 0); + } mutex_unlock(&ctx->fl->map_mutex); goto bail; } @@ -2060,6 +2079,8 @@ static int put_args(uint32_t kernel, struct smq_invoke_ctx *ctx, goto bail; } else { mutex_lock(&ctx->fl->map_mutex); + if (ctx->maps[i]->ctx_refs) + ctx->maps[i]->ctx_refs--; fastrpc_mmap_free(ctx->maps[i], 0); mutex_unlock(&ctx->fl->map_mutex); ctx->maps[i] = NULL; @@ -2071,8 +2092,11 @@ static int put_args(uint32_t kernel, struct smq_invoke_ctx *ctx, if (!fdlist[i]) break; if (!fastrpc_mmap_find(ctx->fl, (int)fdlist[i], 0, 0, - 0, 0, &mmap)) + 0, 0, &mmap)) { + if (mmap && mmap->ctx_refs) + mmap->ctx_refs--; fastrpc_mmap_free(mmap, 0); + } } } mutex_unlock(&ctx->fl->map_mutex); @@ -2923,7 +2947,7 @@ static int fastrpc_get_info_from_dsp(struct fastrpc_file *fl, case ADSP_DOMAIN_ID: case SDSP_DOMAIN_ID: case CDSP_DOMAIN_ID: - if (me->channel[domain].issubsystemup) + if (me->channel[domain].subsystemstate == SUBSYSTEM_UP) dsp_support = 1; break; case MDSP_DOMAIN_ID: @@ -3047,7 +3071,8 @@ static int fastrpc_release_current_dsp_process(struct fastrpc_file *fl) VERIFY(err, fl->apps->channel[cid].rpdev != NULL); if (err) goto bail; - VERIFY(err, fl->apps->channel[cid].issubsystemup == 1); + VERIFY(err, fl->apps->channel[cid].subsystemstate != + SUBSYSTEM_RESTARTING); if (err) { wait_for_completion(&fl->shutdown); goto bail; @@ -3863,7 +3888,6 @@ static int fastrpc_file_free(struct fastrpc_file *fl) mutex_unlock(&fl->perf_mutex); mutex_destroy(&fl->perf_mutex); mutex_destroy(&fl->map_mutex); - mutex_destroy(&fl->pm_qos_mutex); mutex_destroy(&fl->internal_map_mutex); mutex_destroy(&fl->pm_qos_mutex); kfree(fl); @@ -3914,8 +3938,8 @@ static ssize_t fastrpc_debugfs_read(struct file *filp, char __user *buffer, len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, "\n%s %s %s\n", title, " CHANNEL INFO ", title); len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, - "%-7s|%-10s|%-14s|%-9s|%-13s\n", - "subsys", "sesscount", "issubsystemup", + "%-7s|%-10s|%-15s|%-9s|%-13s\n", + "subsys", "sesscount", "subsystemstate", "ssrcount", "session_used"); len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, "-%s%s%s%s-\n", single_line, single_line, @@ -3929,8 +3953,8 @@ static ssize_t fastrpc_debugfs_read(struct file *filp, char __user *buffer, DEBUGFS_SIZE - len, "|%-10u", chan->sesscount); len += scnprintf(fileinfo + len, - DEBUGFS_SIZE - len, "|%-14d", - chan->issubsystemup); + DEBUGFS_SIZE - len, "|%-15d", + chan->subsystemstate); len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, "|%-9u", chan->ssrcount); @@ -4151,7 +4175,7 @@ static int fastrpc_channel_open(struct fastrpc_file *fl) mutex_lock(&me->channel[cid].smd_mutex); if (me->channel[cid].ssrcount != me->channel[cid].prevssrcount) { - if (!me->channel[cid].issubsystemup) { + if (me->channel[cid].subsystemstate != SUBSYSTEM_UP) { err = -ENOTCONN; mutex_unlock(&me->channel[cid].smd_mutex); goto bail; @@ -4766,7 +4790,7 @@ static int fastrpc_restart_notifier_cb(struct notifier_block *nb, __func__, gcinfo[cid].subsys); mutex_lock(&me->channel[cid].smd_mutex); ctx->ssrcount++; - ctx->issubsystemup = 0; + ctx->subsystemstate = SUBSYSTEM_RESTARTING; mutex_unlock(&me->channel[cid].smd_mutex); } else if (code == SUBSYS_AFTER_SHUTDOWN) { pr_info("adsprpc: %s: %s subsystem is down\n", @@ -4778,6 +4802,7 @@ static int fastrpc_restart_notifier_cb(struct notifier_block *nb, complete(&fl->shutdown); } spin_unlock(&me->hlock); + ctx->subsystemstate = SUBSYSTEM_DOWN; } else if (code == SUBSYS_RAMDUMP_NOTIFICATION) { if (cid == RH_CID) { if (me->ramdump_handle) @@ -4796,7 +4821,7 @@ static int fastrpc_restart_notifier_cb(struct notifier_block *nb, } else if (code == SUBSYS_AFTER_POWERUP) { pr_info("adsprpc: %s: %s subsystem is up\n", __func__, gcinfo[cid].subsys); - ctx->issubsystemup = 1; + ctx->subsystemstate = SUBSYSTEM_UP; } return NOTIFY_DONE; } @@ -5469,7 +5494,7 @@ static int __init fastrpc_device_init(void) me->channel[i].dev = dev; me->channel[i].ssrcount = 0; me->channel[i].prevssrcount = 0; - me->channel[i].issubsystemup = 1; + me->channel[i].subsystemstate = SUBSYSTEM_UP; me->channel[i].ramdumpenabled = 0; me->channel[i].rh_dump_dev = NULL; me->channel[i].nb.notifier_call = fastrpc_restart_notifier_cb; diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c index 1d5510cb6db4e7fe0cad57946d2485c401944d1c..1962ff624b7c5ec6dc62827c25c4a91498f32845 100644 --- a/drivers/char/agp/parisc-agp.c +++ b/drivers/char/agp/parisc-agp.c @@ -385,8 +385,6 @@ find_quicksilver(struct device *dev, void *data) static int __init parisc_agp_init(void) { - extern struct sba_device *sba_list; - int err = -1; struct parisc_device *sba = NULL, *lba = NULL; struct lba_device *lbadev = NULL; diff --git a/drivers/char/hw_random/geode-rng.c b/drivers/char/hw_random/geode-rng.c index 207272979f233fe3ea5940c2627a3da9ca58feae..2f8289865ec815611bdc65c95094fe9f5fb4f5c4 100644 --- a/drivers/char/hw_random/geode-rng.c +++ b/drivers/char/hw_random/geode-rng.c @@ -58,7 +58,8 @@ struct amd_geode_priv { static int geode_rng_data_read(struct hwrng *rng, u32 *data) { - void __iomem *mem = (void __iomem *)rng->priv; + struct amd_geode_priv *priv = (struct amd_geode_priv *)rng->priv; + void __iomem *mem = priv->membase; *data = readl(mem + GEODE_RNG_DATA_REG); @@ -67,7 +68,8 @@ static int geode_rng_data_read(struct hwrng *rng, u32 *data) static int geode_rng_data_present(struct hwrng *rng, int wait) { - void __iomem *mem = (void __iomem *)rng->priv; + struct amd_geode_priv *priv = (struct amd_geode_priv *)rng->priv; + void __iomem *mem = priv->membase; int data, i; for (i = 0; i < 20; i++) { diff --git a/drivers/char/hw_random/imx-rngc.c b/drivers/char/hw_random/imx-rngc.c index dc9b8f377907f0e32298bb4686bfc4fe57501f3c..084f7e4254eba12936c55794625b8eeda134f929 100644 --- a/drivers/char/hw_random/imx-rngc.c +++ b/drivers/char/hw_random/imx-rngc.c @@ -105,7 +105,7 @@ static int imx_rngc_self_test(struct imx_rngc *rngc) cmd = readl(rngc->base + RNGC_COMMAND); writel(cmd | RNGC_CMD_SELF_TEST, rngc->base + RNGC_COMMAND); - ret = wait_for_completion_timeout(&rngc->rng_op_done, RNGC_TIMEOUT); + ret = wait_for_completion_timeout(&rngc->rng_op_done, msecs_to_jiffies(RNGC_TIMEOUT)); if (!ret) { imx_rngc_irq_mask_clear(rngc); return -ETIMEDOUT; @@ -188,9 +188,7 @@ static int imx_rngc_init(struct hwrng *rng) cmd = readl(rngc->base + RNGC_COMMAND); writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND); - ret = wait_for_completion_timeout(&rngc->rng_op_done, - RNGC_TIMEOUT); - + ret = wait_for_completion_timeout(&rngc->rng_op_done, msecs_to_jiffies(RNGC_TIMEOUT)); if (!ret) { imx_rngc_irq_mask_clear(rngc); return -ETIMEDOUT; diff --git a/drivers/char/hw_random/virtio-rng.c b/drivers/char/hw_random/virtio-rng.c index 7abd604e938c278825ba6efdf7c65190f3c0b5c2..58884d8752011ef0a671218edf13a3c428185316 100644 --- a/drivers/char/hw_random/virtio-rng.c +++ b/drivers/char/hw_random/virtio-rng.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -30,71 +31,111 @@ static DEFINE_IDA(rng_index_ida); struct virtrng_info { struct hwrng hwrng; struct virtqueue *vq; - struct completion have_data; char name[25]; - unsigned int data_avail; int index; - bool busy; bool hwrng_register_done; bool hwrng_removed; + /* data transfer */ + struct completion have_data; + unsigned int data_avail; + unsigned int data_idx; + /* minimal size returned by rng_buffer_size() */ +#if SMP_CACHE_BYTES < 32 + u8 data[32]; +#else + u8 data[SMP_CACHE_BYTES]; +#endif }; static void random_recv_done(struct virtqueue *vq) { struct virtrng_info *vi = vq->vdev->priv; + unsigned int len; /* We can get spurious callbacks, e.g. shared IRQs + virtio_pci. */ - if (!virtqueue_get_buf(vi->vq, &vi->data_avail)) + if (!virtqueue_get_buf(vi->vq, &len)) return; + smp_store_release(&vi->data_avail, len); complete(&vi->have_data); } -/* The host will fill any buffer we give it with sweet, sweet randomness. */ -static void register_buffer(struct virtrng_info *vi, u8 *buf, size_t size) +static void request_entropy(struct virtrng_info *vi) { struct scatterlist sg; - sg_init_one(&sg, buf, size); + reinit_completion(&vi->have_data); + vi->data_idx = 0; + + sg_init_one(&sg, vi->data, sizeof(vi->data)); /* There should always be room for one buffer. */ - virtqueue_add_inbuf(vi->vq, &sg, 1, buf, GFP_KERNEL); + virtqueue_add_inbuf(vi->vq, &sg, 1, vi->data, GFP_KERNEL); virtqueue_kick(vi->vq); } +static unsigned int copy_data(struct virtrng_info *vi, void *buf, + unsigned int size) +{ + size = min_t(unsigned int, size, vi->data_avail); + memcpy(buf, vi->data + vi->data_idx, size); + vi->data_idx += size; + vi->data_avail -= size; + if (vi->data_avail == 0) + request_entropy(vi); + return size; +} + static int virtio_read(struct hwrng *rng, void *buf, size_t size, bool wait) { int ret; struct virtrng_info *vi = (struct virtrng_info *)rng->priv; + unsigned int chunk; + size_t read; if (vi->hwrng_removed) return -ENODEV; - if (!vi->busy) { - vi->busy = true; - reinit_completion(&vi->have_data); - register_buffer(vi, buf, size); + read = 0; + + /* copy available data */ + if (smp_load_acquire(&vi->data_avail)) { + chunk = copy_data(vi, buf, size); + size -= chunk; + read += chunk; } if (!wait) - return 0; - - ret = wait_for_completion_killable(&vi->have_data); - if (ret < 0) - return ret; + return read; + + /* We have already copied available entropy, + * so either size is 0 or data_avail is 0 + */ + while (size != 0) { + /* data_avail is 0 but a request is pending */ + ret = wait_for_completion_killable(&vi->have_data); + if (ret < 0) + return ret; + /* if vi->data_avail is 0, we have been interrupted + * by a cleanup, but buffer stays in the queue + */ + if (vi->data_avail == 0) + return read; - vi->busy = false; + chunk = copy_data(vi, buf + read, size); + size -= chunk; + read += chunk; + } - return vi->data_avail; + return read; } static void virtio_cleanup(struct hwrng *rng) { struct virtrng_info *vi = (struct virtrng_info *)rng->priv; - if (vi->busy) - wait_for_completion(&vi->have_data); + complete(&vi->have_data); } static int probe_common(struct virtio_device *vdev) @@ -130,6 +171,9 @@ static int probe_common(struct virtio_device *vdev) goto err_find; } + /* we always have a pending entropy request */ + request_entropy(vi); + return 0; err_find: @@ -145,9 +189,9 @@ static void remove_common(struct virtio_device *vdev) vi->hwrng_removed = true; vi->data_avail = 0; + vi->data_idx = 0; complete(&vi->have_data); vdev->config->reset(vdev); - vi->busy = false; if (vi->hwrng_register_done) hwrng_unregister(&vi->hwrng); vdev->config->del_vqs(vdev); diff --git a/drivers/char/ipmi/ipmi_msghandler.c b/drivers/char/ipmi/ipmi_msghandler.c index 4265e8d3e71c5879d1ffcfecaf307d3ed49df40c..988d0e37f87fd43e454c1beda96d2899b8aeb128 100644 --- a/drivers/char/ipmi/ipmi_msghandler.c +++ b/drivers/char/ipmi/ipmi_msghandler.c @@ -536,9 +536,27 @@ struct ipmi_smi { unsigned int waiting_events_count; /* How many events in queue? */ char delivering_events; char event_msg_printed; + + /* How many users are waiting for events? */ atomic_t event_waiters; unsigned int ticks_to_req_ev; - int last_needs_timer; + + spinlock_t watch_lock; /* For dealing with watch stuff below. */ + + /* How many users are waiting for commands? */ + unsigned int command_waiters; + + /* How many users are waiting for watchdogs? */ + unsigned int watchdog_waiters; + + /* How many users are waiting for message responses? */ + unsigned int response_waiters; + + /* + * Tells what the lower layer has last been asked to watch for, + * messages and/or watchdogs. Protected by watch_lock. + */ + unsigned int last_watch_mask; /* * The event receiver for my BMC, only really used at panic @@ -932,6 +950,64 @@ static void deliver_err_response(struct ipmi_smi *intf, deliver_local_response(intf, msg); } +static void smi_add_watch(struct ipmi_smi *intf, unsigned int flags) +{ + unsigned long iflags; + + if (!intf->handlers->set_need_watch) + return; + + spin_lock_irqsave(&intf->watch_lock, iflags); + if (flags & IPMI_WATCH_MASK_CHECK_MESSAGES) + intf->response_waiters++; + + if (flags & IPMI_WATCH_MASK_CHECK_WATCHDOG) + intf->watchdog_waiters++; + + if (flags & IPMI_WATCH_MASK_CHECK_COMMANDS) + intf->command_waiters++; + + if ((intf->last_watch_mask & flags) != flags) { + intf->last_watch_mask |= flags; + intf->handlers->set_need_watch(intf->send_info, + intf->last_watch_mask); + } + spin_unlock_irqrestore(&intf->watch_lock, iflags); +} + +static void smi_remove_watch(struct ipmi_smi *intf, unsigned int flags) +{ + unsigned long iflags; + + if (!intf->handlers->set_need_watch) + return; + + spin_lock_irqsave(&intf->watch_lock, iflags); + if (flags & IPMI_WATCH_MASK_CHECK_MESSAGES) + intf->response_waiters--; + + if (flags & IPMI_WATCH_MASK_CHECK_WATCHDOG) + intf->watchdog_waiters--; + + if (flags & IPMI_WATCH_MASK_CHECK_COMMANDS) + intf->command_waiters--; + + flags = 0; + if (intf->response_waiters) + flags |= IPMI_WATCH_MASK_CHECK_MESSAGES; + if (intf->watchdog_waiters) + flags |= IPMI_WATCH_MASK_CHECK_WATCHDOG; + if (intf->command_waiters) + flags |= IPMI_WATCH_MASK_CHECK_COMMANDS; + + if (intf->last_watch_mask != flags) { + intf->last_watch_mask = flags; + intf->handlers->set_need_watch(intf->send_info, + intf->last_watch_mask); + } + spin_unlock_irqrestore(&intf->watch_lock, iflags); +} + /* * Find the next sequence number not being used and add the given * message with the given timeout to the sequence table. This must be @@ -975,6 +1051,7 @@ static int intf_next_seq(struct ipmi_smi *intf, *seq = i; *seqid = intf->seq_table[i].seqid; intf->curr_seq = (i+1)%IPMI_IPMB_NUM_SEQ; + smi_add_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES); need_waiter(intf); } else { rv = -EAGAIN; @@ -1013,6 +1090,7 @@ static int intf_find_seq(struct ipmi_smi *intf, && (ipmi_addr_equal(addr, &msg->addr))) { *recv_msg = msg; intf->seq_table[seq].inuse = 0; + smi_remove_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES); rv = 0; } } @@ -1074,6 +1152,7 @@ static int intf_err_seq(struct ipmi_smi *intf, struct seq_table *ent = &intf->seq_table[seq]; ent->inuse = 0; + smi_remove_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES); msg = ent->recv_msg; rv = 0; } @@ -1085,7 +1164,6 @@ static int intf_err_seq(struct ipmi_smi *intf, return rv; } - static void free_user_work(struct work_struct *work) { struct ipmi_user *user = container_of(work, struct ipmi_user, @@ -1162,11 +1240,9 @@ int ipmi_create_user(unsigned int if_num, spin_lock_irqsave(&intf->seq_lock, flags); list_add_rcu(&new_user->link, &intf->users); spin_unlock_irqrestore(&intf->seq_lock, flags); - if (handler->ipmi_watchdog_pretimeout) { + if (handler->ipmi_watchdog_pretimeout) /* User wants pretimeouts, so make sure to watch for them. */ - if (atomic_inc_return(&intf->event_waiters) == 1) - need_waiter(intf); - } + smi_add_watch(intf, IPMI_WATCH_MASK_CHECK_WATCHDOG); srcu_read_unlock(&ipmi_interfaces_srcu, index); *user = new_user; return 0; @@ -1239,7 +1315,7 @@ static void _ipmi_destroy_user(struct ipmi_user *user) user->handler->shutdown(user->handler_data); if (user->handler->ipmi_watchdog_pretimeout) - atomic_dec(&intf->event_waiters); + smi_remove_watch(intf, IPMI_WATCH_MASK_CHECK_WATCHDOG); if (user->gets_events) atomic_dec(&intf->event_waiters); @@ -1252,6 +1328,7 @@ static void _ipmi_destroy_user(struct ipmi_user *user) if (intf->seq_table[i].inuse && (intf->seq_table[i].recv_msg->user == user)) { intf->seq_table[i].inuse = 0; + smi_remove_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES); ipmi_free_recv_msg(intf->seq_table[i].recv_msg); } } @@ -1597,8 +1674,7 @@ int ipmi_register_for_cmd(struct ipmi_user *user, goto out_unlock; } - if (atomic_inc_return(&intf->event_waiters) == 1) - need_waiter(intf); + smi_add_watch(intf, IPMI_WATCH_MASK_CHECK_COMMANDS); list_add_rcu(&rcvr->link, &intf->cmd_rcvrs); @@ -1648,7 +1724,7 @@ int ipmi_unregister_for_cmd(struct ipmi_user *user, synchronize_rcu(); release_ipmi_user(user, index); while (rcvrs) { - atomic_dec(&intf->event_waiters); + smi_remove_watch(intf, IPMI_WATCH_MASK_CHECK_COMMANDS); rcvr = rcvrs; rcvrs = rcvr->next; kfree(rcvr); @@ -1765,22 +1841,19 @@ static struct ipmi_smi_msg *smi_add_send_msg(struct ipmi_smi *intf, return smi_msg; } - static void smi_send(struct ipmi_smi *intf, const struct ipmi_smi_handlers *handlers, struct ipmi_smi_msg *smi_msg, int priority) { int run_to_completion = intf->run_to_completion; + unsigned long flags = 0; - if (run_to_completion) { - smi_msg = smi_add_send_msg(intf, smi_msg, priority); - } else { - unsigned long flags; - + if (!run_to_completion) spin_lock_irqsave(&intf->xmit_msgs_lock, flags); - smi_msg = smi_add_send_msg(intf, smi_msg, priority); + smi_msg = smi_add_send_msg(intf, smi_msg, priority); + + if (!run_to_completion) spin_unlock_irqrestore(&intf->xmit_msgs_lock, flags); - } if (smi_msg) handlers->sender(intf->send_info, smi_msg); @@ -3385,6 +3458,7 @@ int ipmi_add_smi(struct module *owner, INIT_LIST_HEAD(&intf->xmit_msgs); INIT_LIST_HEAD(&intf->hp_xmit_msgs); spin_lock_init(&intf->events_lock); + spin_lock_init(&intf->watch_lock); atomic_set(&intf->event_waiters, 0); intf->ticks_to_req_ev = IPMI_REQUEST_EV_TIME; INIT_LIST_HEAD(&intf->waiting_events); @@ -4165,7 +4239,53 @@ static int handle_one_recv_msg(struct ipmi_smi *intf, int chan; ipmi_debug_msg("Recv:", msg->rsp, msg->rsp_size); - if (msg->rsp_size < 2) { + + if ((msg->data_size >= 2) + && (msg->data[0] == (IPMI_NETFN_APP_REQUEST << 2)) + && (msg->data[1] == IPMI_SEND_MSG_CMD) + && (msg->user_data == NULL)) { + + if (intf->in_shutdown) + goto free_msg; + + /* + * This is the local response to a command send, start + * the timer for these. The user_data will not be + * NULL if this is a response send, and we will let + * response sends just go through. + */ + + /* + * Check for errors, if we get certain errors (ones + * that mean basically we can try again later), we + * ignore them and start the timer. Otherwise we + * report the error immediately. + */ + if ((msg->rsp_size >= 3) && (msg->rsp[2] != 0) + && (msg->rsp[2] != IPMI_NODE_BUSY_ERR) + && (msg->rsp[2] != IPMI_LOST_ARBITRATION_ERR) + && (msg->rsp[2] != IPMI_BUS_ERR) + && (msg->rsp[2] != IPMI_NAK_ON_WRITE_ERR)) { + int ch = msg->rsp[3] & 0xf; + struct ipmi_channel *chans; + + /* Got an error sending the message, handle it. */ + + chans = READ_ONCE(intf->channel_list)->c; + if ((chans[ch].medium == IPMI_CHANNEL_MEDIUM_8023LAN) + || (chans[ch].medium == IPMI_CHANNEL_MEDIUM_ASYNC)) + ipmi_inc_stat(intf, sent_lan_command_errs); + else + ipmi_inc_stat(intf, sent_ipmb_command_errs); + intf_err_seq(intf, msg->msgid, msg->rsp[2]); + } else + /* The message was sent, start the timer. */ + intf_start_seq_timer(intf, msg->msgid); +free_msg: + requeue = 0; + goto out; + + } else if (msg->rsp_size < 2) { /* Message is too small to be correct. */ dev_warn(intf->si_dev, PFX "BMC returned to small a message for netfn %x cmd %x, got %d bytes\n", @@ -4404,6 +4524,7 @@ static void smi_recv_tasklet(unsigned long val) intf->curr_msg = newmsg; } } + if (!run_to_completion) spin_unlock_irqrestore(&intf->xmit_msgs_lock, flags); if (newmsg) @@ -4421,62 +4542,16 @@ void ipmi_smi_msg_received(struct ipmi_smi *intf, unsigned long flags = 0; /* keep us warning-free. */ int run_to_completion = intf->run_to_completion; - if ((msg->data_size >= 2) - && (msg->data[0] == (IPMI_NETFN_APP_REQUEST << 2)) - && (msg->data[1] == IPMI_SEND_MSG_CMD) - && (msg->user_data == NULL)) { - - if (intf->in_shutdown) - goto free_msg; - - /* - * This is the local response to a command send, start - * the timer for these. The user_data will not be - * NULL if this is a response send, and we will let - * response sends just go through. - */ - - /* - * Check for errors, if we get certain errors (ones - * that mean basically we can try again later), we - * ignore them and start the timer. Otherwise we - * report the error immediately. - */ - if ((msg->rsp_size >= 3) && (msg->rsp[2] != 0) - && (msg->rsp[2] != IPMI_NODE_BUSY_ERR) - && (msg->rsp[2] != IPMI_LOST_ARBITRATION_ERR) - && (msg->rsp[2] != IPMI_BUS_ERR) - && (msg->rsp[2] != IPMI_NAK_ON_WRITE_ERR)) { - int ch = msg->rsp[3] & 0xf; - struct ipmi_channel *chans; - - /* Got an error sending the message, handle it. */ - - chans = READ_ONCE(intf->channel_list)->c; - if ((chans[ch].medium == IPMI_CHANNEL_MEDIUM_8023LAN) - || (chans[ch].medium == IPMI_CHANNEL_MEDIUM_ASYNC)) - ipmi_inc_stat(intf, sent_lan_command_errs); - else - ipmi_inc_stat(intf, sent_ipmb_command_errs); - intf_err_seq(intf, msg->msgid, msg->rsp[2]); - } else - /* The message was sent, start the timer. */ - intf_start_seq_timer(intf, msg->msgid); - -free_msg: - ipmi_free_smi_msg(msg); - } else { - /* - * To preserve message order, we keep a queue and deliver from - * a tasklet. - */ - if (!run_to_completion) - spin_lock_irqsave(&intf->waiting_rcv_msgs_lock, flags); - list_add_tail(&msg->link, &intf->waiting_rcv_msgs); - if (!run_to_completion) - spin_unlock_irqrestore(&intf->waiting_rcv_msgs_lock, - flags); - } + /* + * To preserve message order, we keep a queue and deliver from + * a tasklet. + */ + if (!run_to_completion) + spin_lock_irqsave(&intf->waiting_rcv_msgs_lock, flags); + list_add_tail(&msg->link, &intf->waiting_rcv_msgs); + if (!run_to_completion) + spin_unlock_irqrestore(&intf->waiting_rcv_msgs_lock, + flags); if (!run_to_completion) spin_lock_irqsave(&intf->xmit_msgs_lock, flags); @@ -4531,7 +4606,7 @@ static void check_msg_timeout(struct ipmi_smi *intf, struct seq_table *ent, struct list_head *timeouts, unsigned long timeout_period, int slot, unsigned long *flags, - unsigned int *waiting_msgs) + bool *need_timer) { struct ipmi_recv_msg *msg; @@ -4543,13 +4618,14 @@ static void check_msg_timeout(struct ipmi_smi *intf, struct seq_table *ent, if (timeout_period < ent->timeout) { ent->timeout -= timeout_period; - (*waiting_msgs)++; + *need_timer = true; return; } if (ent->retries_left == 0) { /* The message has used all its retries. */ ent->inuse = 0; + smi_remove_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES); msg = ent->recv_msg; list_add_tail(&msg->link, timeouts); if (ent->broadcast) @@ -4562,7 +4638,7 @@ static void check_msg_timeout(struct ipmi_smi *intf, struct seq_table *ent, struct ipmi_smi_msg *smi_msg; /* More retries, send again. */ - (*waiting_msgs)++; + *need_timer = true; /* * Start with the max timer, set to normal timer after @@ -4607,20 +4683,20 @@ static void check_msg_timeout(struct ipmi_smi *intf, struct seq_table *ent, } } -static unsigned int ipmi_timeout_handler(struct ipmi_smi *intf, - unsigned long timeout_period) +static bool ipmi_timeout_handler(struct ipmi_smi *intf, + unsigned long timeout_period) { struct list_head timeouts; struct ipmi_recv_msg *msg, *msg2; unsigned long flags; int i; - unsigned int waiting_msgs = 0; + bool need_timer = false; if (!intf->bmc_registered) { kref_get(&intf->refcount); if (!schedule_work(&intf->bmc_reg_work)) { kref_put(&intf->refcount, intf_free); - waiting_msgs++; + need_timer = true; } } @@ -4640,7 +4716,7 @@ static unsigned int ipmi_timeout_handler(struct ipmi_smi *intf, for (i = 0; i < IPMI_IPMB_NUM_SEQ; i++) check_msg_timeout(intf, &intf->seq_table[i], &timeouts, timeout_period, i, - &flags, &waiting_msgs); + &flags, &need_timer); spin_unlock_irqrestore(&intf->seq_lock, flags); list_for_each_entry_safe(msg, msg2, &timeouts, link) @@ -4671,7 +4747,7 @@ static unsigned int ipmi_timeout_handler(struct ipmi_smi *intf, tasklet_schedule(&intf->recv_tasklet); - return waiting_msgs; + return need_timer; } static void ipmi_request_event(struct ipmi_smi *intf) @@ -4691,37 +4767,28 @@ static atomic_t stop_operation; static void ipmi_timeout(struct timer_list *unused) { struct ipmi_smi *intf; - int nt = 0, index; + bool need_timer = false; + int index; if (atomic_read(&stop_operation)) return; index = srcu_read_lock(&ipmi_interfaces_srcu); list_for_each_entry_rcu(intf, &ipmi_interfaces, link) { - int lnt = 0; - if (atomic_read(&intf->event_waiters)) { intf->ticks_to_req_ev--; if (intf->ticks_to_req_ev == 0) { ipmi_request_event(intf); intf->ticks_to_req_ev = IPMI_REQUEST_EV_TIME; } - lnt++; + need_timer = true; } - lnt += ipmi_timeout_handler(intf, IPMI_TIMEOUT_TIME); - - lnt = !!lnt; - if (lnt != intf->last_needs_timer && - intf->handlers->set_need_watch) - intf->handlers->set_need_watch(intf->send_info, lnt); - intf->last_needs_timer = lnt; - - nt += lnt; + need_timer |= ipmi_timeout_handler(intf, IPMI_TIMEOUT_TIME); } srcu_read_unlock(&ipmi_interfaces_srcu, index); - if (nt) + if (need_timer) mod_timer(&ipmi_timer, jiffies + IPMI_TIMEOUT_JIFFIES); } diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c index a5e1dce042e8edcdc4f8374386bb008469d80dc0..3eb22694094887b7ed628143fc81bc9aadb195d4 100644 --- a/drivers/char/ipmi/ipmi_si_intf.c +++ b/drivers/char/ipmi/ipmi_si_intf.c @@ -1073,10 +1073,13 @@ static void request_events(void *send_info) atomic_set(&smi_info->req_events, 1); } -static void set_need_watch(void *send_info, bool enable) +static void set_need_watch(void *send_info, unsigned int watch_mask) { struct smi_info *smi_info = send_info; unsigned long flags; + int enable; + + enable = !!watch_mask; atomic_set(&smi_info->need_watch, enable); spin_lock_irqsave(&smi_info->si_lock, flags); @@ -2116,6 +2119,11 @@ static int try_smi_init(struct smi_info *new_smi) new_smi->io.io_cleanup = NULL; } + if (rv && new_smi->si_sm) { + kfree(new_smi->si_sm); + new_smi->si_sm = NULL; + } + kfree(init_name); return rv; } diff --git a/drivers/char/ipmi/ipmi_ssif.c b/drivers/char/ipmi/ipmi_ssif.c index fd1a487443f02473bd334a5c8942e9fa3294d95f..fc4a96014161b0733fc6f49c8e6e0f5c9089e813 100644 --- a/drivers/char/ipmi/ipmi_ssif.c +++ b/drivers/char/ipmi/ipmi_ssif.c @@ -88,8 +88,14 @@ #define SSIF_MSG_JIFFIES ((SSIF_MSG_USEC * 1000) / TICK_NSEC) #define SSIF_MSG_PART_JIFFIES ((SSIF_MSG_PART_USEC * 1000) / TICK_NSEC) +/* + * Timeout for the watch, only used for get flag timer. + */ +#define SSIF_WATCH_MSG_TIMEOUT msecs_to_jiffies(10) +#define SSIF_WATCH_WATCHDOG_TIMEOUT msecs_to_jiffies(250) + enum ssif_intf_state { - SSIF_NORMAL, + SSIF_IDLE, SSIF_GETTING_FLAGS, SSIF_GETTING_EVENTS, SSIF_CLEARING_FLAGS, @@ -97,8 +103,8 @@ enum ssif_intf_state { /* FIXME - add watchdog stuff. */ }; -#define SSIF_IDLE(ssif) ((ssif)->ssif_state == SSIF_NORMAL \ - && (ssif)->curr_msg == NULL) +#define IS_SSIF_IDLE(ssif) ((ssif)->ssif_state == SSIF_IDLE \ + && (ssif)->curr_msg == NULL) /* * Indexes into stats[] in ssif_info below. @@ -268,6 +274,9 @@ struct ssif_info { struct timer_list retry_timer; int retries_left; + long watch_timeout; /* Timeout for flags check, 0 if off. */ + struct timer_list watch_timer; /* Flag fetch timer. */ + /* Info from SSIF cmd */ unsigned char max_xmit_msg_size; unsigned char max_recv_msg_size; @@ -340,9 +349,9 @@ static void return_hosed_msg(struct ssif_info *ssif_info, /* * Must be called with the message lock held. This will release the - * message lock. Note that the caller will check SSIF_IDLE and start a - * new operation, so there is no need to check for new messages to - * start in here. + * message lock. Note that the caller will check IS_SSIF_IDLE and + * start a new operation, so there is no need to check for new + * messages to start in here. */ static void start_clear_flags(struct ssif_info *ssif_info, unsigned long *flags) { @@ -359,7 +368,7 @@ static void start_clear_flags(struct ssif_info *ssif_info, unsigned long *flags) if (start_send(ssif_info, msg, 3) != 0) { /* Error, just go to normal state. */ - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; } } @@ -374,7 +383,7 @@ static void start_flag_fetch(struct ssif_info *ssif_info, unsigned long *flags) mb[0] = (IPMI_NETFN_APP_REQUEST << 2); mb[1] = IPMI_GET_MSG_FLAGS_CMD; if (start_send(ssif_info, mb, 2) != 0) - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; } static void check_start_send(struct ssif_info *ssif_info, unsigned long *flags, @@ -385,7 +394,7 @@ static void check_start_send(struct ssif_info *ssif_info, unsigned long *flags, flags = ipmi_ssif_lock_cond(ssif_info, &oflags); ssif_info->curr_msg = NULL; - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); ipmi_free_smi_msg(msg); } @@ -399,7 +408,7 @@ static void start_event_fetch(struct ssif_info *ssif_info, unsigned long *flags) msg = ipmi_alloc_smi_msg(); if (!msg) { - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); return; } @@ -422,7 +431,7 @@ static void start_recv_msg_fetch(struct ssif_info *ssif_info, msg = ipmi_alloc_smi_msg(); if (!msg) { - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); return; } @@ -440,9 +449,9 @@ static void start_recv_msg_fetch(struct ssif_info *ssif_info, /* * Must be called with the message lock held. This will release the - * message lock. Note that the caller will check SSIF_IDLE and start a - * new operation, so there is no need to check for new messages to - * start in here. + * message lock. Note that the caller will check IS_SSIF_IDLE and + * start a new operation, so there is no need to check for new + * messages to start in here. */ static void handle_flags(struct ssif_info *ssif_info, unsigned long *flags) { @@ -458,7 +467,7 @@ static void handle_flags(struct ssif_info *ssif_info, unsigned long *flags) /* Events available. */ start_event_fetch(ssif_info, flags); else { - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); } } @@ -558,6 +567,26 @@ static void retry_timeout(struct timer_list *t) start_get(ssif_info); } +static void watch_timeout(struct timer_list *t) +{ + struct ssif_info *ssif_info = from_timer(ssif_info, t, watch_timer); + unsigned long oflags, *flags; + + if (ssif_info->stopping) + return; + + flags = ipmi_ssif_lock_cond(ssif_info, &oflags); + if (ssif_info->watch_timeout) { + mod_timer(&ssif_info->watch_timer, + jiffies + ssif_info->watch_timeout); + if (IS_SSIF_IDLE(ssif_info)) { + start_flag_fetch(ssif_info, flags); /* Releases lock */ + return; + } + ssif_info->req_flags = true; + } + ipmi_ssif_unlock_cond(ssif_info, flags); +} static void ssif_alert(struct i2c_client *client, enum i2c_alert_protocol type, unsigned int data) @@ -747,7 +776,7 @@ static void msg_done_handler(struct ssif_info *ssif_info, int result, } switch (ssif_info->ssif_state) { - case SSIF_NORMAL: + case SSIF_IDLE: ipmi_ssif_unlock_cond(ssif_info, flags); if (!msg) break; @@ -765,16 +794,16 @@ static void msg_done_handler(struct ssif_info *ssif_info, int result, * Error fetching flags, or invalid length, * just give up for now. */ - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); pr_warn(PFX "Error getting flags: %d %d, %x\n", result, len, (len >= 3) ? data[2] : 0); } else if (data[0] != (IPMI_NETFN_APP_REQUEST | 1) << 2 || data[1] != IPMI_GET_MSG_FLAGS_CMD) { /* - * Don't abort here, maybe it was a queued - * response to a previous command. + * Recv error response, give up. */ + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); pr_warn(PFX "Invalid response getting flags: %x %x\n", data[0], data[1]); @@ -796,7 +825,7 @@ static void msg_done_handler(struct ssif_info *ssif_info, int result, pr_warn(PFX "Invalid response clearing flags: %x %x\n", data[0], data[1]); } - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); break; @@ -872,7 +901,7 @@ static void msg_done_handler(struct ssif_info *ssif_info, int result, } flags = ipmi_ssif_lock_cond(ssif_info, &oflags); - if (SSIF_IDLE(ssif_info) && !ssif_info->stopping) { + if (IS_SSIF_IDLE(ssif_info) && !ssif_info->stopping) { if (ssif_info->req_events) start_event_fetch(ssif_info, flags); else if (ssif_info->req_flags) @@ -1041,7 +1070,7 @@ static void start_next_msg(struct ssif_info *ssif_info, unsigned long *flags) unsigned long oflags; restart: - if (!SSIF_IDLE(ssif_info)) { + if (!IS_SSIF_IDLE(ssif_info)) { ipmi_ssif_unlock_cond(ssif_info, flags); return; } @@ -1103,8 +1132,7 @@ static int get_smi_info(void *send_info, struct ipmi_smi_info *data) } /* - * Instead of having our own timer to periodically check the message - * flags, we let the message handler drive us. + * Upper layer wants us to request events. */ static void request_events(void *send_info) { @@ -1115,18 +1143,33 @@ static void request_events(void *send_info) return; flags = ipmi_ssif_lock_cond(ssif_info, &oflags); - /* - * Request flags first, not events, because the lower layer - * doesn't have a way to send an attention. But make sure - * event checking still happens. - */ ssif_info->req_events = true; - if (SSIF_IDLE(ssif_info)) - start_flag_fetch(ssif_info, flags); - else { - ssif_info->req_flags = true; - ipmi_ssif_unlock_cond(ssif_info, flags); + ipmi_ssif_unlock_cond(ssif_info, flags); +} + +/* + * Upper layer is changing the flag saying whether we need to request + * flags periodically or not. + */ +static void ssif_set_need_watch(void *send_info, unsigned int watch_mask) +{ + struct ssif_info *ssif_info = (struct ssif_info *) send_info; + unsigned long oflags, *flags; + long timeout = 0; + + if (watch_mask & IPMI_WATCH_MASK_CHECK_MESSAGES) + timeout = SSIF_WATCH_MSG_TIMEOUT; + else if (watch_mask) + timeout = SSIF_WATCH_WATCHDOG_TIMEOUT; + + flags = ipmi_ssif_lock_cond(ssif_info, &oflags); + if (timeout != ssif_info->watch_timeout) { + ssif_info->watch_timeout = timeout; + if (ssif_info->watch_timeout) + mod_timer(&ssif_info->watch_timer, + jiffies + ssif_info->watch_timeout); } + ipmi_ssif_unlock_cond(ssif_info, flags); } static int ssif_start_processing(void *send_info, @@ -1249,10 +1292,11 @@ static void shutdown_ssif(void *send_info) dev_set_drvdata(&ssif_info->client->dev, NULL); /* make sure the driver is not looking for flags any more. */ - while (ssif_info->ssif_state != SSIF_NORMAL) + while (ssif_info->ssif_state != SSIF_IDLE) schedule_timeout(1); ssif_info->stopping = true; + del_timer_sync(&ssif_info->watch_timer); del_timer_sync(&ssif_info->retry_timer); if (ssif_info->thread) { complete(&ssif_info->wake_thread); @@ -1630,8 +1674,9 @@ static int ssif_probe(struct i2c_client *client, const struct i2c_device_id *id) } spin_lock_init(&ssif_info->lock); - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; timer_setup(&ssif_info->retry_timer, retry_timeout, 0); + timer_setup(&ssif_info->watch_timer, watch_timeout, 0); for (i = 0; i < SSIF_NUM_STATS; i++) atomic_set(&ssif_info->stats[i], 0); @@ -1645,6 +1690,7 @@ static int ssif_probe(struct i2c_client *client, const struct i2c_device_id *id) ssif_info->handlers.get_smi_info = get_smi_info; ssif_info->handlers.sender = sender; ssif_info->handlers.request_events = request_events; + ssif_info->handlers.set_need_watch = ssif_set_need_watch; { unsigned int thread_num; diff --git a/drivers/char/tpm/tpm_tis.c b/drivers/char/tpm/tpm_tis.c index 939dc25a78336d245960e5c8e86e69eaa59c027b..3abb4af80be68dbb7213ac5c79345ff589d73aac 100644 --- a/drivers/char/tpm/tpm_tis.c +++ b/drivers/char/tpm/tpm_tis.c @@ -87,6 +87,22 @@ static const struct dmi_system_id tpm_tis_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T490s"), }, }, + { + .callback = tpm_tis_disable_irq, + .ident = "ThinkStation P360 Tiny", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkStation P360 Tiny"), + }, + }, + { + .callback = tpm_tis_disable_irq, + .ident = "ThinkPad L490", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L490"), + }, + }, {} }; diff --git a/drivers/char/tpm/tpm_tis_core.c b/drivers/char/tpm/tpm_tis_core.c index c95ce9323d77ae3e5465d43fec51407d182328ab..d1869b9a2ffd33ddbee2bcf70f97cc320ed95d7a 100644 --- a/drivers/char/tpm/tpm_tis_core.c +++ b/drivers/char/tpm/tpm_tis_core.c @@ -270,6 +270,7 @@ static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count) int size = 0; int status; u32 expected; + int rc; if (count < TPM_HEADER_SIZE) { size = -EIO; @@ -289,8 +290,13 @@ static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count) goto out; } - size += recv_data(chip, &buf[TPM_HEADER_SIZE], - expected - TPM_HEADER_SIZE); + rc = recv_data(chip, &buf[TPM_HEADER_SIZE], + expected - TPM_HEADER_SIZE); + if (rc < 0) { + size = rc; + goto out; + } + size += rc; if (size < expected) { dev_err(&chip->dev, "Unable to read remainder of result\n"); size = -ETIME; @@ -419,10 +425,17 @@ static int tpm_tis_send_main(struct tpm_chip *chip, const u8 *buf, size_t len) int rc; u32 ordinal; unsigned long dur; - - rc = tpm_tis_send_data(chip, buf, len); - if (rc < 0) - return rc; + unsigned int try; + + for (try = 0; try < TPM_RETRY; try++) { + rc = tpm_tis_send_data(chip, buf, len); + if (rc >= 0) + /* Data transfer done successfully */ + break; + else if (rc != -EIO) + /* Data transfer failed, not recoverable */ + return rc; + } /* go and do it */ rc = tpm_tis_write8(priv, TPM_STS(priv->locality), TPM_STS_GO); diff --git a/drivers/char/tpm/tpm_vtpm_proxy.c b/drivers/char/tpm/tpm_vtpm_proxy.c index ecbb63f8d2318241134b5d515103a4012b5a50ef..05c77812b65016bf6725fd25abf0797fd5c095b7 100644 --- a/drivers/char/tpm/tpm_vtpm_proxy.c +++ b/drivers/char/tpm/tpm_vtpm_proxy.c @@ -700,37 +700,21 @@ static struct miscdevice vtpmx_miscdev = { .fops = &vtpmx_fops, }; -static int vtpmx_init(void) -{ - return misc_register(&vtpmx_miscdev); -} - -static void vtpmx_cleanup(void) -{ - misc_deregister(&vtpmx_miscdev); -} - static int __init vtpm_module_init(void) { int rc; - rc = vtpmx_init(); - if (rc) { - pr_err("couldn't create vtpmx device\n"); - return rc; - } - workqueue = create_workqueue("tpm-vtpm"); if (!workqueue) { pr_err("couldn't create workqueue\n"); - rc = -ENOMEM; - goto err_vtpmx_cleanup; + return -ENOMEM; } - return 0; - -err_vtpmx_cleanup: - vtpmx_cleanup(); + rc = misc_register(&vtpmx_miscdev); + if (rc) { + pr_err("couldn't create vtpmx device\n"); + destroy_workqueue(workqueue); + } return rc; } @@ -738,7 +722,7 @@ static int __init vtpm_module_init(void) static void __exit vtpm_module_exit(void) { destroy_workqueue(workqueue); - vtpmx_cleanup(); + misc_deregister(&vtpmx_miscdev); } module_init(vtpm_module_init); diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 292056bbb30e91a39d6e0f2d27b41e4f0e907c8c..ffe81449ce24644e9a74f104f35f1d24ed64eb12 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -63,7 +63,7 @@ config COMMON_CLK_RK808 config COMMON_CLK_HI655X tristate "Clock driver for Hi655x" if EXPERT depends on (MFD_HI655X_PMIC || COMPILE_TEST) - depends on REGMAP + select REGMAP default MFD_HI655X_PMIC ---help--- This driver supports the hi655x PMIC clock. This diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c index 49819b546134bfa4794d513ce0d6fb5d2e6e609d..5c6760e45a16eeb3b97ab11e57a6d6514a5fb8e7 100644 --- a/drivers/clk/clk-conf.c +++ b/drivers/clk/clk-conf.c @@ -36,9 +36,12 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) else return rc; } - if (clkspec.np == node && !clk_supplier) + if (clkspec.np == node && !clk_supplier) { + of_node_put(clkspec.np); return 0; + } pclk = of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); if (IS_ERR(pclk)) { if (PTR_ERR(pclk) != -EPROBE_DEFER) pr_warn("clk: couldn't get parent clock %d for %pOF\n", @@ -51,10 +54,12 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) if (rc < 0) goto err; if (clkspec.np == node && !clk_supplier) { + of_node_put(clkspec.np); rc = 0; goto err; } clk = of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); if (IS_ERR(clk)) { if (PTR_ERR(clk) != -EPROBE_DEFER) pr_warn("clk: couldn't get assigned clock %d for %pOF\n", @@ -96,10 +101,13 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier) else return rc; } - if (clkspec.np == node && !clk_supplier) + if (clkspec.np == node && !clk_supplier) { + of_node_put(clkspec.np); return 0; + } clk = of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); if (IS_ERR(clk)) { if (PTR_ERR(clk) != -EPROBE_DEFER) pr_warn("clk: couldn't get clock %d for %pOF\n", diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 91124f5524bd526cf908636af57ffbef95fa6f34..72f4aba8e43ccea4f72df7a7671e9f4f0fab2cb5 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -43,7 +43,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) { struct clk_gate *gate = to_clk_gate(hw); int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; - unsigned long uninitialized_var(flags); + unsigned long flags; u32 reg; set ^= enable; diff --git a/drivers/clk/clk-npcm7xx.c b/drivers/clk/clk-npcm7xx.c index d8687584c022e3224385260f2221fb3b5db7ab73..ebf7c500b15e3bfd0e5ab8218c0b9cf88ae886ad 100644 --- a/drivers/clk/clk-npcm7xx.c +++ b/drivers/clk/clk-npcm7xx.c @@ -647,7 +647,7 @@ static void __init npcm7xx_clk_init(struct device_node *clk_np) return; npcm7xx_init_fail: - kfree(npcm7xx_clk_data->hws); + kfree(npcm7xx_clk_data); npcm7xx_init_np_err: iounmap(clk_base); npcm7xx_init_error: diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c index c65d30bba700540611066123a86f74d4564ea05a..9d9eed597617becf0d4a025f16409d6c968f5d8f 100644 --- a/drivers/clk/clk-scmi.c +++ b/drivers/clk/clk-scmi.c @@ -170,6 +170,7 @@ static int scmi_clocks_probe(struct scmi_device *sdev) sclk->info = handle->clk_ops->info_get(handle, idx); if (!sclk->info) { dev_dbg(dev, "invalid clock info for idx %d\n", idx); + devm_kfree(dev, sclk); continue; } diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 474e9769e29bcfb1a9ab73a9016012d0426732a2..759979171b39aaa2a2144260304ac4243a6df0a9 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -276,6 +276,17 @@ static bool clk_core_is_enabled(struct clk_core *core) } } + /* + * This could be called with the enable lock held, or from atomic + * context. If the parent isn't enabled already, we can't do + * anything here. We can also assume this clock isn't enabled. + */ + if ((core->flags & CLK_OPS_PARENT_ENABLE) && core->parent) + if (!clk_core_is_enabled(core->parent)) { + ret = false; + goto done; + } + ret = core->ops->is_enabled(core->hw); done: if (core->rpm_enabled) diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c index 6ec8f279af2cb673282ecb2ceb72cc89a3e81753..f50abfad84aa74455b041df77142e065b7ad1f9d 100644 --- a/drivers/clk/keystone/pll.c +++ b/drivers/clk/keystone/pll.c @@ -213,7 +213,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) } clk = clk_register_pll(NULL, node->name, parent_name, pll_data); - if (clk) { + if (!IS_ERR_OR_NULL(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); return; } @@ -285,12 +285,13 @@ static void __init of_pll_div_clk_init(struct device_node *node) clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift, mask, 0, NULL); - if (clk) { - of_clk_add_provider(node, of_clk_src_simple_get, clk); - } else { + if (IS_ERR(clk)) { pr_err("%s: error registering divider %s\n", __func__, clk_name); iounmap(reg); + return; } + + of_clk_add_provider(node, of_clk_src_simple_get, clk); } CLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init); @@ -332,9 +333,11 @@ static void __init of_pll_mux_clk_init(struct device_node *node) clk = clk_register_mux(NULL, clk_name, (const char **)&parents, ARRAY_SIZE(parents) , 0, reg, shift, mask, 0, NULL); - if (clk) - of_clk_add_provider(node, of_clk_src_simple_get, clk); - else + if (IS_ERR(clk)) { pr_err("%s: error registering mux %s\n", __func__, clk_name); + return; + } + + of_clk_add_provider(node, of_clk_src_simple_get, clk); } CLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init); diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 4dda8988b2f091a665860ae5b2f5dc4cc0492a23..00e52a94e34fd90eb6d914e3476ad2714815ff6f 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -688,6 +688,8 @@ static int mtk_topckgen_init(struct platform_device *pdev) return PTR_ERR(base); clk_data = mtk_alloc_clk_data(CLK_TOP_NR); + if (!clk_data) + return -ENOMEM; mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), clk_data); @@ -755,6 +757,8 @@ static void __init mtk_infrasys_init_early(struct device_node *node) if (!infra_clk_data) { infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); + if (!infra_clk_data) + return; for (i = 0; i < CLK_INFRA_NR; i++) infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); @@ -781,6 +785,8 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (!infra_clk_data) { infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); + if (!infra_clk_data) + return -ENOMEM; } else { for (i = 0; i < CLK_INFRA_NR; i++) { if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) @@ -909,6 +915,8 @@ static int mtk_pericfg_init(struct platform_device *pdev) return PTR_ERR(base); clk_data = mtk_alloc_clk_data(CLK_PERI_NR); + if (!clk_data) + return -ENOMEM; mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), clk_data); diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c index 5702bc974ed9904756fd069509416034d6bbeaf9..1ee45f32c1d4eeadbfbb0035155e82d6f94aee9d 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -396,6 +396,8 @@ static int mtk_topckgen_init(struct platform_device *pdev) return PTR_ERR(base); clk_data = mtk_alloc_clk_data(CLK_TOP_NR); + if (!clk_data) + return -ENOMEM; mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), clk_data); @@ -554,6 +556,8 @@ static void mtk_infrasys_init_early(struct device_node *node) if (!infra_clk_data) { infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); + if (!infra_clk_data) + return; for (i = 0; i < CLK_INFRA_NR; i++) infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); @@ -578,6 +582,8 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (!infra_clk_data) { infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); + if (!infra_clk_data) + return -ENOMEM; } else { for (i = 0; i < CLK_INFRA_NR; i++) { if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) diff --git a/drivers/clk/qcom/clk-debug.c b/drivers/clk/qcom/clk-debug.c index aa785559643035061f29a6b56a818171b2e341d7..87e60ae9430f48fef761a4be3744c20c7e5274f5 100644 --- a/drivers/clk/qcom/clk-debug.c +++ b/drivers/clk/qcom/clk-debug.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2016, 2019-2021 The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -11,6 +12,10 @@ #include #include #include +#include + +#define CREATE_TRACE_POINTS +#include "trace.h" #include "clk-regmap.h" #include "clk-debug.h" @@ -273,6 +278,8 @@ static int clk_debug_measure_get(void *data, u64 *val) /* recursively calculate actual freq */ *val *= get_mux_divs(measure); + /* enable ftrace support */ + trace_clk_measure(clk_hw_get_name(hw), *val); disable_debug_clks(measure); exit: if (meas->bus_cl_id) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index e59069eb23128a739c40265ca02272d8875626e8..dd77d6cc2590babab62730345906e19562f108cb 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -239,19 +239,13 @@ static void disable_unprepare_rcg_srcs(struct clk *curr, struct clk *new) static unsigned long calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) { - u64 tmp = rate; + if (hid_div) + rate = mult_frac(rate, 2, hid_div + 1); - if (hid_div) { - tmp *= 2; - do_div(tmp, hid_div + 1); - } - - if (mode) { - tmp *= m; - do_div(tmp, n); - } + if (mode) + rate = mult_frac(rate, m, n); - return tmp; + return rate; } static unsigned long diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index ee41aec106ac61879eb0cfe52adf72e86207ec1d..eff38d22738c462fcadccd180f4c3936ca09f30e 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -431,7 +431,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -478,7 +477,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -511,7 +509,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -545,7 +542,6 @@ static struct clk_alpha_pll_postdiv gpll6 = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -559,7 +555,6 @@ static struct clk_fixed_factor gpll6_out_main_div2 = { }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -624,7 +619,6 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index 849046fbed6d40963c2100e267e048ab6a5bb981..3df830cdfd01091186304fb7cc675e78a3b6dd84 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -66,7 +66,7 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_names = (const char *[]){ "pll0" }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, diff --git a/drivers/clk/qcom/gcc-scuba.c b/drivers/clk/qcom/gcc-scuba.c index 5efd53034b7bab190114845b575d7a81c069a2c5..a026659f62078636a3ff6a1cec188e23d99bf256 100644 --- a/drivers/clk/qcom/gcc-scuba.c +++ b/drivers/clk/qcom/gcc-scuba.c @@ -2246,6 +2246,19 @@ static struct clk_regmap_div gcc_disp_gpll0_clk_src = { }, }; +static struct clk_regmap_div gcc_pwm0_xo512_div_clk_src = { + .reg = 0x20030, + .shift = 0, + .width = 9, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pwm0_xo512_div_clk_src", + .parent_names = + (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + static struct clk_branch gcc_disp_gpll0_div_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -2522,6 +2535,11 @@ static struct clk_branch gcc_pwm0_xo512_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pwm0_xo512_clk", + .parent_names = (const char *[]){ + "gcc_pwm0_xo512_div_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -3178,6 +3196,7 @@ static struct clk_regmap *gcc_scuba_clocks[] = { [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, + [GCC_PWM0_XO512_DIV_CLK_SRC] = &gcc_pwm0_xo512_div_clk_src.clkr, [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, diff --git a/drivers/clk/qcom/trace.h b/drivers/clk/qcom/trace.h new file mode 100644 index 0000000000000000000000000000000000000000..93ed76187352d22855fdb07024e1d967f4098b96 --- /dev/null +++ b/drivers/clk/qcom/trace.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM clk_qcom + +#if !defined(_TRACE_CLOCK_QCOM_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_CLOCK_QCOM + +#include + +DECLARE_EVENT_CLASS(clk_measure_support, + + TP_PROTO(const char *name, unsigned long rate), + + TP_ARGS(name, rate), + + TP_STRUCT__entry( + __string(name, name) + __field(unsigned long, rate) + ), + + TP_fast_assign( + __assign_str(name, name); + __entry->rate = rate; + ), + + TP_printk("%s rate: %lu", + __get_str(name), (unsigned long)__entry->rate) +); + +DEFINE_EVENT(clk_measure_support, clk_measure, + + TP_PROTO(const char *name, unsigned long rate), + + TP_ARGS(name, rate) +); + +#endif /* _TRACE_CLOCK_QCOM */ + +/* This part must be outside protection */ + +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . + +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE trace + +#include diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 5a628148f3f02a641970962dfc864bf8859bf33a..ec9850db5bf9d6a6da3978d8f96f9bf2414b0df4 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -1267,7 +1267,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, RK3399_CLKGATE_CON(10), 7, GFLAGS), - COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0, + COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS), /* gic */ diff --git a/drivers/clk/sunxi-ng/ccu_mmc_timing.c b/drivers/clk/sunxi-ng/ccu_mmc_timing.c index f9869f7353c01473656c3521ac2601d7060319aa..9356dc1571561cef282f6897b24e424b3adc3a55 100644 --- a/drivers/clk/sunxi-ng/ccu_mmc_timing.c +++ b/drivers/clk/sunxi-ng/ccu_mmc_timing.c @@ -50,7 +50,7 @@ int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode) EXPORT_SYMBOL_GPL(sunxi_ccu_set_mmc_timing_mode); /** - * sunxi_ccu_set_mmc_timing_mode: Get the current MMC clock timing mode + * sunxi_ccu_get_mmc_timing_mode: Get the current MMC clock timing mode * @clk: clock to query * * Returns 0 if the clock is in old timing mode, > 0 if it is in diff --git a/drivers/clk/tegra/clk-bpmp.c b/drivers/clk/tegra/clk-bpmp.c index 5847241022074b4eec2d35fac920169ffff7a840..f1b9721a035842c5b21255654592b747f3857ba8 100644 --- a/drivers/clk/tegra/clk-bpmp.c +++ b/drivers/clk/tegra/clk-bpmp.c @@ -162,7 +162,7 @@ static unsigned long tegra_bpmp_clk_recalc_rate(struct clk_hw *hw, err = tegra_bpmp_clk_transfer(clk->bpmp, &msg); if (err < 0) - return err; + return 0; return response.rate; } diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 5859b8ee14781f16741f7310e7b7b6fc05a590a3..3d39a6dc238132c81f54ec19a2d9524f78b0df5b 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -29,24 +29,24 @@ #define MISC_CLK_ENB 0x48 #define OSC_CTRL 0x50 -#define OSC_CTRL_OSC_FREQ_MASK (3<<30) -#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) -#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) -#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) -#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) -#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) - -#define OSC_CTRL_PLL_REF_DIV_MASK (3<<28) -#define OSC_CTRL_PLL_REF_DIV_1 (0<<28) -#define OSC_CTRL_PLL_REF_DIV_2 (1<<28) -#define OSC_CTRL_PLL_REF_DIV_4 (2<<28) +#define OSC_CTRL_OSC_FREQ_MASK (3u<<30) +#define OSC_CTRL_OSC_FREQ_13MHZ (0u<<30) +#define OSC_CTRL_OSC_FREQ_19_2MHZ (1u<<30) +#define OSC_CTRL_OSC_FREQ_12MHZ (2u<<30) +#define OSC_CTRL_OSC_FREQ_26MHZ (3u<<30) +#define OSC_CTRL_MASK (0x3f2u | OSC_CTRL_OSC_FREQ_MASK) + +#define OSC_CTRL_PLL_REF_DIV_MASK (3u<<28) +#define OSC_CTRL_PLL_REF_DIV_1 (0u<<28) +#define OSC_CTRL_PLL_REF_DIV_2 (1u<<28) +#define OSC_CTRL_PLL_REF_DIV_4 (2u<<28) #define OSC_FREQ_DET 0x58 -#define OSC_FREQ_DET_TRIG (1<<31) +#define OSC_FREQ_DET_TRIG (1u<<31) #define OSC_FREQ_DET_STATUS 0x5c -#define OSC_FREQ_DET_BUSY (1<<31) -#define OSC_FREQ_DET_CNT_MASK 0xFFFF +#define OSC_FREQ_DET_BUSYu (1<<31) +#define OSC_FREQ_DET_CNT_MASK 0xFFFFu #define TEGRA20_CLK_PERIPH_BANKS 3 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index db51b2427e8a64e9bfe20bbb41a9363069b101f4..e33b21d3f9d8b360305e309ba729457e025b25c2 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -23,8 +23,8 @@ obj-$(CONFIG_FTTMR010_TIMER) += timer-fttmr010.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o -obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o -obj-$(CONFIG_ORION_TIMER) += time-orion.o +obj-$(CONFIG_ARMADA_370_XP_TIMER) += timer-armada-370-xp.o +obj-$(CONFIG_ORION_TIMER) += timer-orion.o obj-$(CONFIG_BCM2835_TIMER) += bcm2835_timer.o obj-$(CONFIG_CLPS711X_TIMER) += clps711x-timer.o obj-$(CONFIG_ATLAS7_TIMER) += timer-atlas7.o @@ -36,25 +36,25 @@ obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += meson6_timer.o obj-$(CONFIG_TEGRA_TIMER) += tegra20_timer.o -obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o -obj-$(CONFIG_NSPIRE_TIMER) += zevio-timer.o +obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o +obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o -obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o -obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o +obj-$(CONFIG_CADENCE_TTC_TIMER) += timer-cadence-ttc.o +obj-$(CONFIG_CLKSRC_EFM32) += timer-efm32.o obj-$(CONFIG_CLKSRC_STM32) += timer-stm32.o obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o -obj-$(CONFIG_CLKSRC_LPC32XX) += time-lpc32xx.o +obj-$(CONFIG_CLKSRC_LPC32XX) += timer-lpc32xx.o obj-$(CONFIG_CLKSRC_MPS2) += mps2-timer.o obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o -obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o -obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o -obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o +obj-$(CONFIG_FSL_FTM_TIMER) += timer-fsl-ftm.o +obj-$(CONFIG_VF_PIT_TIMER) += timer-vf-pit.o +obj-$(CONFIG_CLKSRC_QCOM) += timer-qcom.o obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o -obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o +obj-$(CONFIG_CLKSRC_PISTACHIO) += timer-pistachio.o obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o -obj-$(CONFIG_OWL_TIMER) += owl-timer.o +obj-$(CONFIG_OWL_TIMER) += timer-owl.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o @@ -66,7 +66,7 @@ obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp804.o obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o obj-$(CONFIG_KEYSTONE_TIMER) += timer-keystone.o obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o -obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o +obj-$(CONFIG_CLKSRC_VERSATILE) += timer-versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c index 43f4d5c4d6fa4fdb8f4581d71010e4b54ecd18da..998d9115add6badfe7f89d64ba4d9e0e7685e8bb 100644 --- a/drivers/clocksource/tcb_clksrc.c +++ b/drivers/clocksource/tcb_clksrc.c @@ -294,6 +294,7 @@ static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx) writel(mck_divisor_idx /* likely divide-by-8 */ | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP /* free-run */ + | ATMEL_TC_ASWTRG_SET /* TIOA0 rises at software trigger */ | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */ | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */ tcaddr + ATMEL_TC_REG(0, CMR)); diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/timer-armada-370-xp.c similarity index 100% rename from drivers/clocksource/time-armada-370-xp.c rename to drivers/clocksource/timer-armada-370-xp.c diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/timer-cadence-ttc.c similarity index 94% rename from drivers/clocksource/cadence_ttc_timer.c rename to drivers/clocksource/timer-cadence-ttc.c index a7eb858a84a0f75961165881361fc5468b54fb2e..16b9bfb257564d40a1f072eec8a90ebb1465dd0e 100644 --- a/drivers/clocksource/cadence_ttc_timer.c +++ b/drivers/clocksource/timer-cadence-ttc.c @@ -23,6 +23,8 @@ #include #include #include +#include +#include /* * This driver configures the 2 16/32-bit count-up timers as follows: @@ -472,13 +474,7 @@ static int __init ttc_setup_clockevent(struct clk *clk, return err; } -/** - * ttc_timer_init - Initialize the timer - * - * Initializes the timer hardware and register the clock source and clock event - * timers with Linux kernal timer framework - */ -static int __init ttc_timer_init(struct device_node *timer) +static int __init ttc_timer_probe(struct platform_device *pdev) { unsigned int irq; void __iomem *timer_baseaddr; @@ -486,6 +482,7 @@ static int __init ttc_timer_init(struct device_node *timer) static int initialized; int clksel, ret; u32 timer_width = 16; + struct device_node *timer = pdev->dev.of_node; if (initialized) return 0; @@ -497,10 +494,10 @@ static int __init ttc_timer_init(struct device_node *timer) * and use it. Note that the event timer uses the interrupt and it's the * 2nd TTC hence the irq_of_parse_and_map(,1) */ - timer_baseaddr = of_iomap(timer, 0); - if (!timer_baseaddr) { + timer_baseaddr = devm_of_iomap(&pdev->dev, timer, 0, NULL); + if (IS_ERR(timer_baseaddr)) { pr_err("ERROR: invalid timer base address\n"); - return -ENXIO; + return PTR_ERR(timer_baseaddr); } irq = irq_of_parse_and_map(timer, 1); @@ -524,20 +521,40 @@ static int __init ttc_timer_init(struct device_node *timer) clk_ce = of_clk_get(timer, clksel); if (IS_ERR(clk_ce)) { pr_err("ERROR: timer input clock not found\n"); - return PTR_ERR(clk_ce); + ret = PTR_ERR(clk_ce); + goto put_clk_cs; } ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width); if (ret) - return ret; + goto put_clk_ce; ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq); if (ret) - return ret; + goto put_clk_ce; pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); return 0; + +put_clk_ce: + clk_put(clk_ce); +put_clk_cs: + clk_put(clk_cs); + return ret; } -TIMER_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); +static const struct of_device_id ttc_timer_of_match[] = { + {.compatible = "cdns,ttc"}, + {}, +}; + +MODULE_DEVICE_TABLE(of, ttc_timer_of_match); + +static struct platform_driver ttc_timer_driver = { + .driver = { + .name = "cdns_ttc_timer", + .of_match_table = ttc_timer_of_match, + }, +}; +builtin_platform_driver_probe(ttc_timer_driver, ttc_timer_probe); diff --git a/drivers/clocksource/time-efm32.c b/drivers/clocksource/timer-efm32.c similarity index 100% rename from drivers/clocksource/time-efm32.c rename to drivers/clocksource/timer-efm32.c diff --git a/drivers/clocksource/fsl_ftm_timer.c b/drivers/clocksource/timer-fsl-ftm.c similarity index 100% rename from drivers/clocksource/fsl_ftm_timer.c rename to drivers/clocksource/timer-fsl-ftm.c diff --git a/drivers/clocksource/timer-imx-gpt.c b/drivers/clocksource/timer-imx-gpt.c index 165fbbb1c9a049335456cc197392d197c54e93a6..0e67026d782fede56f437aba87706ec6946b7046 100644 --- a/drivers/clocksource/timer-imx-gpt.c +++ b/drivers/clocksource/timer-imx-gpt.c @@ -473,12 +473,16 @@ static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type t return -ENOMEM; imxtm->base = of_iomap(np, 0); - if (!imxtm->base) - return -ENXIO; + if (!imxtm->base) { + ret = -ENXIO; + goto err_kfree; + } imxtm->irq = irq_of_parse_and_map(np, 0); - if (imxtm->irq <= 0) - return -EINVAL; + if (imxtm->irq <= 0) { + ret = -EINVAL; + goto err_kfree; + } imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); @@ -491,11 +495,15 @@ static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type t ret = _mxc_timer_init(imxtm); if (ret) - return ret; + goto err_kfree; initialized = 1; return 0; + +err_kfree: + kfree(imxtm); + return ret; } static int __init imx1_timer_init_dt(struct device_node *np) diff --git a/drivers/clocksource/time-lpc32xx.c b/drivers/clocksource/timer-lpc32xx.c similarity index 100% rename from drivers/clocksource/time-lpc32xx.c rename to drivers/clocksource/timer-lpc32xx.c diff --git a/drivers/clocksource/time-orion.c b/drivers/clocksource/timer-orion.c similarity index 100% rename from drivers/clocksource/time-orion.c rename to drivers/clocksource/timer-orion.c diff --git a/drivers/clocksource/owl-timer.c b/drivers/clocksource/timer-owl.c similarity index 100% rename from drivers/clocksource/owl-timer.c rename to drivers/clocksource/timer-owl.c diff --git a/drivers/clocksource/time-pistachio.c b/drivers/clocksource/timer-pistachio.c similarity index 100% rename from drivers/clocksource/time-pistachio.c rename to drivers/clocksource/timer-pistachio.c diff --git a/drivers/clocksource/qcom-timer.c b/drivers/clocksource/timer-qcom.c similarity index 100% rename from drivers/clocksource/qcom-timer.c rename to drivers/clocksource/timer-qcom.c diff --git a/drivers/clocksource/versatile.c b/drivers/clocksource/timer-versatile.c similarity index 100% rename from drivers/clocksource/versatile.c rename to drivers/clocksource/timer-versatile.c diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/timer-vf-pit.c similarity index 100% rename from drivers/clocksource/vf_pit_timer.c rename to drivers/clocksource/timer-vf-pit.c diff --git a/drivers/clocksource/vt8500_timer.c b/drivers/clocksource/timer-vt8500.c similarity index 100% rename from drivers/clocksource/vt8500_timer.c rename to drivers/clocksource/timer-vt8500.c diff --git a/drivers/clocksource/zevio-timer.c b/drivers/clocksource/timer-zevio.c similarity index 100% rename from drivers/clocksource/zevio-timer.c rename to drivers/clocksource/timer-zevio.c diff --git a/drivers/cpufreq/brcmstb-avs-cpufreq.c b/drivers/cpufreq/brcmstb-avs-cpufreq.c index a3c82f530d6089a333f480163df1234f571f4ecd..541486217984b06835fd535dc344c29735d3d91d 100644 --- a/drivers/cpufreq/brcmstb-avs-cpufreq.c +++ b/drivers/cpufreq/brcmstb-avs-cpufreq.c @@ -410,7 +410,11 @@ brcm_avs_get_freq_table(struct device *dev, struct private_data *priv) if (ret) return ERR_PTR(ret); - table = devm_kcalloc(dev, AVS_PSTATE_MAX + 1, sizeof(*table), + /* + * We allocate space for the 5 different P-STATES AVS, + * plus extra space for a terminating element. + */ + table = devm_kcalloc(dev, AVS_PSTATE_MAX + 1 + 1, sizeof(*table), GFP_KERNEL); if (!table) return ERR_PTR(-ENOMEM); diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c index 818f92798fb9b0dc394c5c7c18854356c33d41aa..55743d78016b02e3ba9f7c3687cbd8a424e823bb 100644 --- a/drivers/cpufreq/powernow-k8.c +++ b/drivers/cpufreq/powernow-k8.c @@ -1104,7 +1104,8 @@ static int powernowk8_cpu_exit(struct cpufreq_policy *pol) kfree(data->powernow_table); kfree(data); - for_each_cpu(cpu, pol->cpus) + /* pol->cpus will be empty here, use related_cpus instead. */ + for_each_cpu(cpu, pol->related_cpus) per_cpu(powernow_data, cpu) = NULL; return 0; diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c index 219704cd87ebf1b36f133fa67dd91cbcf8856e62..3b71fe130337865649796dd03f1245f4dc332174 100644 --- a/drivers/cpuidle/cpuidle.c +++ b/drivers/cpuidle/cpuidle.c @@ -142,13 +142,14 @@ static void enter_s2idle_proper(struct cpuidle_driver *drv, * executing it contains RCU usage regarded as invalid in the idle * context, so tell RCU about that. */ - RCU_NONIDLE(tick_freeze()); + tick_freeze(); /* * The state used here cannot be a "coupled" one, because the "coupled" * cpuidle mechanism enables interrupts and doing that with timekeeping * suspended is generally unsafe. */ stop_critical_timings(); + rcu_idle_enter(); drv->states[index].enter_s2idle(dev, drv, index); if (WARN_ON_ONCE(!irqs_disabled())) local_irq_disable(); @@ -157,7 +158,8 @@ static void enter_s2idle_proper(struct cpuidle_driver *drv, * first CPU executing it calls functions containing RCU read-side * critical sections, so tell RCU about that. */ - RCU_NONIDLE(tick_unfreeze()); + rcu_idle_exit(); + tick_unfreeze(); start_critical_timings(); time_end = ns_to_ktime(local_clock()); @@ -226,16 +228,18 @@ int cpuidle_enter_state(struct cpuidle_device *dev, struct cpuidle_driver *drv, /* Take note of the planned idle state. */ sched_idle_set_state(target_state, index); - trace_cpu_idle_rcuidle(index, dev->cpu); + trace_cpu_idle(index, dev->cpu); time_start = ns_to_ktime(local_clock()); stop_critical_timings(); + rcu_idle_enter(); entered_state = target_state->enter(dev, drv, index); + rcu_idle_exit(); start_critical_timings(); sched_clock_idle_wakeup_event(); time_end = ns_to_ktime(local_clock()); - trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, dev->cpu); + trace_cpu_idle(PWR_EVENT_EXIT, dev->cpu); /* The cpu is no longer idle or about to enter idle. */ sched_idle_set_state(NULL, -1); diff --git a/drivers/crypto/amcc/crypto4xx_core.c b/drivers/crypto/amcc/crypto4xx_core.c index cd00afb5786e86e394e4620cbbe3d3656d78a4a4..2c70a64cc8317ff362323cb71775ad6100cc2209 100644 --- a/drivers/crypto/amcc/crypto4xx_core.c +++ b/drivers/crypto/amcc/crypto4xx_core.c @@ -529,7 +529,6 @@ static void crypto4xx_cipher_done(struct crypto4xx_device *dev, { struct skcipher_request *req; struct scatterlist *dst; - dma_addr_t addr; req = skcipher_request_cast(pd_uinfo->async_req); @@ -538,8 +537,8 @@ static void crypto4xx_cipher_done(struct crypto4xx_device *dev, req->cryptlen, req->dst); } else { dst = pd_uinfo->dest_va; - addr = dma_map_page(dev->core_dev->device, sg_page(dst), - dst->offset, dst->length, DMA_FROM_DEVICE); + dma_unmap_page(dev->core_dev->device, pd->dest, dst->length, + DMA_FROM_DEVICE); } if (pd_uinfo->sa_va->sa_command_0.bf.save_iv == SA_SAVE_IV) { @@ -564,10 +563,9 @@ static void crypto4xx_ahash_done(struct crypto4xx_device *dev, struct ahash_request *ahash_req; ahash_req = ahash_request_cast(pd_uinfo->async_req); - ctx = crypto_tfm_ctx(ahash_req->base.tfm); + ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(ahash_req)); - crypto4xx_copy_digest_to_dst(ahash_req->result, pd_uinfo, - crypto_tfm_ctx(ahash_req->base.tfm)); + crypto4xx_copy_digest_to_dst(ahash_req->result, pd_uinfo, ctx); crypto4xx_ret_sg_desc(dev, pd_uinfo); if (pd_uinfo->state & PD_ENTRY_BUSY) diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c index f26d62e5533a7a5a622d6e2f0661dcb3d0ebdc40..701e4ad8077b41eb8511f74fb1d83bccfea4be88 100644 --- a/drivers/crypto/caam/caampkc.c +++ b/drivers/crypto/caam/caampkc.c @@ -194,7 +194,9 @@ static int caam_rsa_count_leading_zeros(struct scatterlist *sgl, if (len && *buff) break; - sg_miter_next(&miter); + if (!sg_miter_next(&miter)) + break; + buff = miter.addr; len = miter.length; diff --git a/drivers/crypto/chelsio/chtls/chtls_cm.c b/drivers/crypto/chelsio/chtls/chtls_cm.c index 08ed3ff8b255fab4edf578af941a997d70aa6d26..360e1533917091c69c48d5f962246cbeb991c4f7 100644 --- a/drivers/crypto/chelsio/chtls/chtls_cm.c +++ b/drivers/crypto/chelsio/chtls/chtls_cm.c @@ -2071,7 +2071,7 @@ static void chtls_rx_ack(struct sock *sk, struct sk_buff *skb) if (tp->snd_una != snd_una) { tp->snd_una = snd_una; - tp->rcv_tstamp = tcp_time_stamp(tp); + tp->rcv_tstamp = tcp_jiffies32; if (tp->snd_una == tp->snd_nxt && !csk_flag_nochk(csk, CSK_TX_FAILOVER)) csk_reset_flag(csk, CSK_TX_WAIT_IDLE); diff --git a/drivers/crypto/msm/qcedev.c b/drivers/crypto/msm/qcedev.c index 22979101d9c6a45dae75e124f75dc6787e53c7b1..dfef41ed23805242c623e190de192f83c07721cd 100644 --- a/drivers/crypto/msm/qcedev.c +++ b/drivers/crypto/msm/qcedev.c @@ -2283,8 +2283,11 @@ static int qcedev_remove(struct platform_device *pdev) podev = platform_get_drvdata(pdev); if (!podev) return 0; + + qcedev_ce_high_bw_req(podev, true); if (podev->qce) qce_close(podev->qce); + qcedev_ce_high_bw_req(podev, false); if (podev->platform_support.bus_scale_table != NULL) msm_bus_scale_unregister_client(podev->bus_scale_handle); diff --git a/drivers/crypto/nx/Makefile b/drivers/crypto/nx/Makefile index 015155da59c29f4e0d425f4cd68099efeac4a3e5..76139865d7fa167f8def67cb19b0e9b34304514f 100644 --- a/drivers/crypto/nx/Makefile +++ b/drivers/crypto/nx/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CRYPTO_DEV_NX_ENCRYPT) += nx-crypto.o nx-crypto-objs := nx.o \ - nx_debugfs.o \ nx-aes-cbc.o \ nx-aes-ecb.o \ nx-aes-gcm.o \ @@ -11,6 +10,7 @@ nx-crypto-objs := nx.o \ nx-sha256.o \ nx-sha512.o +nx-crypto-$(CONFIG_DEBUG_FS) += nx_debugfs.o obj-$(CONFIG_CRYPTO_DEV_NX_COMPRESS_PSERIES) += nx-compress-pseries.o nx-compress.o obj-$(CONFIG_CRYPTO_DEV_NX_COMPRESS_POWERNV) += nx-compress-powernv.o nx-compress.o nx-compress-objs := nx-842.o diff --git a/drivers/crypto/nx/nx.h b/drivers/crypto/nx/nx.h index c3e54af18645c930220ae2801525ff490c89704b..ebad937a9545c64a4d864a4e217390c8c0aef1d8 100644 --- a/drivers/crypto/nx/nx.h +++ b/drivers/crypto/nx/nx.h @@ -180,8 +180,8 @@ struct nx_sg *nx_walk_and_build(struct nx_sg *, unsigned int, int nx_debugfs_init(struct nx_crypto_driver *); void nx_debugfs_fini(struct nx_crypto_driver *); #else -#define NX_DEBUGFS_INIT(drv) (0) -#define NX_DEBUGFS_FINI(drv) (0) +#define NX_DEBUGFS_INIT(drv) do {} while (0) +#define NX_DEBUGFS_FINI(drv) do {} while (0) #endif #define NX_PAGE_NUM(x) ((u64)(x) & 0xfffffffffffff000ULL) diff --git a/drivers/crypto/stm32/stm32-hash.c b/drivers/crypto/stm32/stm32-hash.c index 641b11077f479df05544e35dacc482ffe56e79ca..015f349bf66bbdca516dae2e4d0c9f74f3beb250 100644 --- a/drivers/crypto/stm32/stm32-hash.c +++ b/drivers/crypto/stm32/stm32-hash.c @@ -578,9 +578,9 @@ static int stm32_hash_dma_send(struct stm32_hash_dev *hdev) } for_each_sg(rctx->sg, tsg, rctx->nents, i) { + sg[0] = *tsg; len = sg->length; - sg[0] = *tsg; if (sg_is_last(sg)) { if (hdev->dma_mode == 1) { len = (ALIGN(sg->length, 16) - 16); diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index 1b76beecf0e27242457174673c5ded6b85d041cf..080205cdb498d0fc4322f5d0a2682669981b599d 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -581,6 +581,7 @@ static void devfreq_dev_release(struct device *dev) mutex_destroy(&devfreq->lock); mutex_destroy(&devfreq->event_lock); + srcu_cleanup_notifier_head(&devfreq->transition_notifier_list); kfree(devfreq); } diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c index 81ba4eb34890952468b877fa2107363adcdc42bb..09d369306ee36fdb54f76cb175ed1dd8315d3938 100644 --- a/drivers/dma-buf/sw_sync.c +++ b/drivers/dma-buf/sw_sync.c @@ -200,6 +200,7 @@ static const struct dma_fence_ops timeline_fence_ops = { */ static void sync_timeline_signal(struct sync_timeline *obj, unsigned int inc) { + LIST_HEAD(signalled); struct sync_pt *pt, *next; trace_sync_timeline(obj); @@ -212,21 +213,20 @@ static void sync_timeline_signal(struct sync_timeline *obj, unsigned int inc) if (!timeline_fence_signaled(&pt->base)) break; - list_del_init(&pt->link); + dma_fence_get(&pt->base); + + list_move_tail(&pt->link, &signalled); rb_erase(&pt->node, &obj->pt_tree); - /* - * A signal callback may release the last reference to this - * fence, causing it to be freed. That operation has to be - * last to avoid a use after free inside this loop, and must - * be after we remove the fence from the timeline in order to - * prevent deadlocking on timeline->lock inside - * timeline_fence_release(). - */ dma_fence_signal_locked(&pt->base); } spin_unlock_irq(&obj->lock); + + list_for_each_entry_safe(pt, next, &signalled, link) { + list_del_init(&pt->link); + dma_fence_put(&pt->base); + } } /** diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 5f459adc5ec3ec9fb8a903a85e85efad2434202f..b1ec5e0c28d3a9c81c6ebd6a1e6840c2bced396e 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -212,6 +212,7 @@ config FSL_DMA config FSL_EDMA tristate "Freescale eDMA engine support" depends on OF + depends on HAS_IOMEM select DMA_ENGINE select DMA_VIRTUAL_CHANNELS help @@ -258,6 +259,7 @@ config IMX_SDMA config INTEL_IDMA64 tristate "Intel integrated DMA 64-bit support" + depends on HAS_IOMEM select DMA_ENGINE select DMA_VIRTUAL_CHANNELS help diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index a451ecae1669276f5b7873740f1a78163d265561..33ea7abd8cc973f5eca4ba63611beb7b1ab1fca2 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -223,6 +223,7 @@ struct at_xdmac { int irq; struct clk *clk; u32 save_gim; + u32 save_gs; struct dma_pool *at_xdmac_desc_pool; struct at_xdmac_chan chan[0]; }; @@ -1878,6 +1879,7 @@ static int atmel_xdmac_suspend(struct device *dev) } } atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM); + atxdmac->save_gs = at_xdmac_read(atxdmac, AT_XDMAC_GS); at_xdmac_off(atxdmac); clk_disable_unprepare(atxdmac->clk); @@ -1914,7 +1916,8 @@ static int atmel_xdmac_resume(struct device *dev) at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc); at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim); wmb(); - at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); + if (atxdmac->save_gs & atchan->mask) + at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); } } return 0; diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c index 9cb1c4228205156e0f6406e7125426e84edc52e2..1bba1fa3a809628018e0c173f3a55fc8fc8c0196 100644 --- a/drivers/dma/pl330.c +++ b/drivers/dma/pl330.c @@ -404,6 +404,12 @@ enum desc_status { * of a channel can be BUSY at any time. */ BUSY, + /* + * Pause was called while descriptor was BUSY. Due to hardware + * limitations, only termination is possible for descriptors + * that have been paused. + */ + PAUSED, /* * Sitting on the channel work_list but xfer done * by PL330 core @@ -1042,7 +1048,7 @@ static bool _trigger(struct pl330_thread *thrd) return true; } -static bool _start(struct pl330_thread *thrd) +static bool pl330_start_thread(struct pl330_thread *thrd) { switch (_state(thrd)) { case PL330_STATE_FAULT_COMPLETING: @@ -1690,7 +1696,7 @@ static int pl330_update(struct pl330_dmac *pl330) thrd->req_running = -1; /* Get going again ASAP */ - _start(thrd); + pl330_start_thread(thrd); /* For now, just make a list of callbacks to be done */ list_add_tail(&descdone->rqd, &pl330->req_done); @@ -2028,7 +2034,7 @@ static inline void fill_queue(struct dma_pl330_chan *pch) list_for_each_entry(desc, &pch->work_list, node) { /* If already submitted */ - if (desc->status == BUSY) + if (desc->status == BUSY || desc->status == PAUSED) continue; ret = pl330_submit_req(pch->thread, desc); @@ -2076,7 +2082,7 @@ static void pl330_tasklet(unsigned long data) } else { /* Make sure the PL330 Channel thread is active */ spin_lock(&pch->thread->dmac->lock); - _start(pch->thread); + pl330_start_thread(pch->thread); spin_unlock(&pch->thread->dmac->lock); } @@ -2094,7 +2100,7 @@ static void pl330_tasklet(unsigned long data) if (power_down) { pch->active = true; spin_lock(&pch->thread->dmac->lock); - _start(pch->thread); + pl330_start_thread(pch->thread); spin_unlock(&pch->thread->dmac->lock); power_down = false; } @@ -2305,6 +2311,7 @@ static int pl330_pause(struct dma_chan *chan) { struct dma_pl330_chan *pch = to_pchan(chan); struct pl330_dmac *pl330 = pch->dmac; + struct dma_pl330_desc *desc; unsigned long flags; pm_runtime_get_sync(pl330->ddma.dev); @@ -2314,6 +2321,10 @@ static int pl330_pause(struct dma_chan *chan) _stop(pch->thread); spin_unlock(&pl330->lock); + list_for_each_entry(desc, &pch->work_list, node) { + if (desc->status == BUSY) + desc->status = PAUSED; + } spin_unlock_irqrestore(&pch->lock, flags); pm_runtime_mark_last_busy(pl330->ddma.dev); pm_runtime_put_autosuspend(pl330->ddma.dev); @@ -2404,7 +2415,7 @@ pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, else if (running && desc == running) transferred = pl330_get_current_xferred_count(pch, desc); - else if (desc->status == BUSY) + else if (desc->status == BUSY || desc->status == PAUSED) /* * Busy but not running means either just enqueued, * or finished and not yet marked done @@ -2421,6 +2432,9 @@ pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, case DONE: ret = DMA_COMPLETE; break; + case PAUSED: + ret = DMA_PAUSED; + break; case PREP: case BUSY: ret = DMA_IN_PROGRESS; diff --git a/drivers/dma/pxa_dma.c b/drivers/dma/pxa_dma.c index c54986902b9d28f8378ccc65fe6b01ee5937e6ae..6dfd08dadb12d8e7eb128e7d497c60791941e9a0 100644 --- a/drivers/dma/pxa_dma.c +++ b/drivers/dma/pxa_dma.c @@ -772,7 +772,6 @@ static void pxad_free_desc(struct virt_dma_desc *vd) dma_addr_t dma; struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd); - BUG_ON(sw_desc->nb_desc == 0); for (i = sw_desc->nb_desc - 1; i >= 0; i--) { if (i > 0) dma = sw_desc->hw_desc[i - 1]->ddadr; diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index e588dc5daaa801f9184fba66829118c234bf80a6..d7d3bf7920ead150e08c350536c4844115976b1a 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -3584,6 +3584,10 @@ static int __init d40_probe(struct platform_device *pdev) spin_lock_init(&base->lcla_pool.lock); base->irq = platform_get_irq(pdev, 0); + if (base->irq < 0) { + ret = base->irq; + goto destroy_cache; + } ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); if (ret) { @@ -3681,6 +3685,7 @@ static int __init d40_probe(struct platform_device *pdev) regulator_disable(base->lcpa_regulator); regulator_put(base->lcpa_regulator); } + pm_runtime_disable(base->dev); kfree(base->lcla_pool.alloc_map); kfree(base->lookup_log_chans); diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c index 3259c450544ca0111ed02e4d072ecf7ec5321ef2..e18090f83bec509bcc25585cf02d24878fc7e58b 100644 --- a/drivers/dma/stm32-mdma.c +++ b/drivers/dma/stm32-mdma.c @@ -520,7 +520,7 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan, src_maxburst = chan->dma_config.src_maxburst; dst_maxburst = chan->dma_config.dst_maxburst; - ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)); + ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN; ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)); ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)); @@ -948,7 +948,7 @@ stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src, if (!desc) return NULL; - ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)); + ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN; ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)); ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)); cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id)); @@ -1217,6 +1217,10 @@ static int stm32_mdma_resume(struct dma_chan *c) unsigned long flags; u32 status, reg; + /* Transfer can be terminated */ + if (!chan->desc || (stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & STM32_MDMA_CCR_EN)) + return -EPERM; + hwdesc = chan->desc->node[chan->curr_hwdesc].hwdesc; spin_lock_irqsave(&chan->vchan.lock, flags); diff --git a/drivers/dma/ti/edma.c b/drivers/dma/ti/edma.c index 44158fa859737c64d43ca2ca3c2fdd691fdcd6f9..3a1b37971bef8d7b47dee22fd8c2462073a0b673 100644 --- a/drivers/dma/ti/edma.c +++ b/drivers/dma/ti/edma.c @@ -2303,7 +2303,7 @@ static int edma_probe(struct platform_device *pdev) if (irq < 0 && node) irq = irq_of_parse_and_map(node, 0); - if (irq >= 0) { + if (irq > 0) { irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint", dev_name(dev)); ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name, @@ -2319,7 +2319,7 @@ static int edma_probe(struct platform_device *pdev) if (irq < 0 && node) irq = irq_of_parse_and_map(node, 2); - if (irq >= 0) { + if (irq > 0) { irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint", dev_name(dev)); ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name, diff --git a/drivers/edac/skx_edac.c b/drivers/edac/skx_edac.c index dd209e0dd9abb2ca72c0c2b45a5548088852d5c9..38a82a3f451677204b0c2653c871246756e5a6bb 100644 --- a/drivers/edac/skx_edac.c +++ b/drivers/edac/skx_edac.c @@ -825,13 +825,13 @@ static bool skx_rir_decode(struct decoded_addr *res) } static u8 skx_close_row[] = { - 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33 + 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33, 34 }; static u8 skx_close_column[] = { 3, 4, 5, 14, 19, 23, 24, 25, 26, 27 }; static u8 skx_open_row[] = { - 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33 + 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33, 34 }; static u8 skx_open_column[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 @@ -896,12 +896,11 @@ static bool skx_decode(struct decoded_addr *res) #ifdef CONFIG_EDAC_DEBUG /* - * Debug feature. Make /sys/kernel/debug/skx_edac_test/addr. - * Write an address to this file to exercise the address decode - * logic in this driver. + * Debug feature. + * Exercise the address decode logic by writing an address to + * /sys/kernel/debug/edac/skx_test/addr. */ static struct dentry *skx_test; -static u64 skx_fake_addr; static int debugfs_u64_set(void *data, u64 val) { @@ -912,19 +911,19 @@ static int debugfs_u64_set(void *data, u64 val) return 0; } - DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n"); -static struct dentry *mydebugfs_create(const char *name, umode_t mode, - struct dentry *parent, u64 *value) -{ - return debugfs_create_file(name, mode, parent, value, &fops_u64_wo); -} - static void setup_skx_debug(void) { - skx_test = debugfs_create_dir("skx_edac_test", NULL); - mydebugfs_create("addr", S_IWUSR, skx_test, &skx_fake_addr); + skx_test = edac_debugfs_create_dir("skx_test"); + if (!skx_test) + return; + + if (!edac_debugfs_create_file("addr", 0200, skx_test, + NULL, &fops_u64_wo)) { + debugfs_remove(skx_test); + skx_test = NULL; + } } static void teardown_skx_debug(void) diff --git a/drivers/extcon/extcon.c b/drivers/extcon/extcon.c index 17ec0d3dbba58147f14b8062459778728c64d2c5..5747d9bfcf2ec98df9a49aeefa71a70778310e40 100644 --- a/drivers/extcon/extcon.c +++ b/drivers/extcon/extcon.c @@ -204,6 +204,14 @@ static const struct __extcon_info { * @attr_name: "name" sysfs entry * @attr_state: "state" sysfs entry * @attrs: the array pointing to attr_name and attr_state for attr_g + * @usb_propval: the array of USB connector properties + * @chg_propval: the array of charger connector properties + * @jack_propval: the array of jack connector properties + * @disp_propval: the array of display connector properties + * @usb_bits: the bit array of the USB connector property capabilities + * @chg_bits: the bit array of the charger connector property capabilities + * @jack_bits: the bit array of the jack connector property capabilities + * @disp_bits: the bit array of the display connector property capabilities */ struct extcon_cable { struct extcon_dev *edev; diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c index 45c048751f3bd8a9527631d26673cc7f603fe85e..9e7abc86de8c2fd0bb04cb7c6eebe01ca38c3938 100644 --- a/drivers/firewire/ohci.c +++ b/drivers/firewire/ohci.c @@ -1112,7 +1112,7 @@ static void context_tasklet(unsigned long data) static int context_add_buffer(struct context *ctx) { struct descriptor_buffer *desc; - dma_addr_t uninitialized_var(bus_addr); + dma_addr_t bus_addr; int offset; /* @@ -1302,7 +1302,7 @@ static int at_context_queue_packet(struct context *ctx, struct fw_packet *packet) { struct fw_ohci *ohci = ctx->ohci; - dma_addr_t d_bus, uninitialized_var(payload_bus); + dma_addr_t d_bus, payload_bus; struct driver_data *driver_data; struct descriptor *d, *last; __le32 *header; @@ -2458,7 +2458,7 @@ static int ohci_set_config_rom(struct fw_card *card, { struct fw_ohci *ohci; __be32 *next_config_rom; - dma_addr_t uninitialized_var(next_config_rom_bus); + dma_addr_t next_config_rom_bus; ohci = fw_ohci(card); @@ -2947,10 +2947,10 @@ static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, int type, int channel, size_t header_size) { struct fw_ohci *ohci = fw_ohci(card); - struct iso_context *uninitialized_var(ctx); - descriptor_callback_t uninitialized_var(callback); - u64 *uninitialized_var(channels); - u32 *uninitialized_var(mask), uninitialized_var(regs); + struct iso_context *ctx; + descriptor_callback_t callback; + u64 *channels; + u32 *mask, regs; int index, ret = -EBUSY; spin_lock_irq(&ohci->lock); diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index e8cd66705ad7a76933804152e83ce740e7cbdde2..5ccbbb3eb68e14768abc5872908c31b33943160b 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -705,6 +705,39 @@ static int scmi_remove(struct platform_device *pdev) return ret; } +static int scmi_mailbox_chan_validate(struct device *cdev) +{ + int num_mb, num_sh, ret = 0; + struct device_node *np = cdev->of_node; + + num_mb = of_count_phandle_with_args(np, "mboxes", "#mbox-cells"); + num_sh = of_count_phandle_with_args(np, "shmem", NULL); + /* Bail out if mboxes and shmem descriptors are inconsistent */ + if (num_mb <= 0 || num_sh > 2 || num_mb != num_sh) { + dev_warn(cdev, "Invalid channel descriptor for '%s'\n", + of_node_full_name(np)); + return -EINVAL; + } + + if (num_sh > 1) { + struct device_node *np_tx, *np_rx; + + np_tx = of_parse_phandle(np, "shmem", 0); + np_rx = of_parse_phandle(np, "shmem", 1); + /* SCMI Tx and Rx shared mem areas have to be distinct */ + if (!np_tx || !np_rx || np_tx == np_rx) { + dev_warn(cdev, "Invalid shmem descriptor for '%s'\n", + of_node_full_name(np)); + ret = -EINVAL; + } + + of_node_put(np_tx); + of_node_put(np_rx); + } + + return ret; +} + static inline int scmi_mbox_chan_setup(struct scmi_info *info, struct device *dev, int prot_id) { @@ -720,6 +753,10 @@ scmi_mbox_chan_setup(struct scmi_info *info, struct device *dev, int prot_id) goto idr_alloc; } + ret = scmi_mailbox_chan_validate(dev); + if (ret) + return ret; + cinfo = devm_kzalloc(info->dev, sizeof(*cinfo), GFP_KERNEL); if (!cinfo) return -ENOMEM; diff --git a/drivers/firmware/arm_sdei.c b/drivers/firmware/arm_sdei.c index e809f4d9a9e93433712947d6a221ef9a50d82a90..ea2c2bdcf4f7f348d1e0b9865225dde96645e26e 100644 --- a/drivers/firmware/arm_sdei.c +++ b/drivers/firmware/arm_sdei.c @@ -43,6 +43,8 @@ static asmlinkage void (*sdei_firmware_call)(unsigned long function_id, /* entry point from firmware to arch asm code */ static unsigned long sdei_entry_point; +static int sdei_hp_state; + struct sdei_event { /* These three are protected by the sdei_list_lock */ struct list_head list; @@ -303,8 +305,6 @@ int sdei_mask_local_cpu(void) { int err; - WARN_ON_ONCE(preemptible()); - err = invoke_sdei_fn(SDEI_1_0_FN_SDEI_PE_MASK, 0, 0, 0, 0, 0, NULL); if (err && err != -EIO) { pr_warn_once("failed to mask CPU[%u]: %d\n", @@ -317,6 +317,7 @@ int sdei_mask_local_cpu(void) static void _ipi_mask_cpu(void *ignored) { + WARN_ON_ONCE(preemptible()); sdei_mask_local_cpu(); } @@ -324,8 +325,6 @@ int sdei_unmask_local_cpu(void) { int err; - WARN_ON_ONCE(preemptible()); - err = invoke_sdei_fn(SDEI_1_0_FN_SDEI_PE_UNMASK, 0, 0, 0, 0, 0, NULL); if (err && err != -EIO) { pr_warn_once("failed to unmask CPU[%u]: %d\n", @@ -338,6 +337,7 @@ int sdei_unmask_local_cpu(void) static void _ipi_unmask_cpu(void *ignored) { + WARN_ON_ONCE(preemptible()); sdei_unmask_local_cpu(); } @@ -345,6 +345,8 @@ static void _ipi_private_reset(void *ignored) { int err; + WARN_ON_ONCE(preemptible()); + err = invoke_sdei_fn(SDEI_1_0_FN_SDEI_PRIVATE_RESET, 0, 0, 0, 0, 0, NULL); if (err && err != -EIO) @@ -391,8 +393,6 @@ static void _local_event_enable(void *data) int err; struct sdei_crosscall_args *arg = data; - WARN_ON_ONCE(preemptible()); - err = sdei_api_event_enable(arg->event->event_num); sdei_cross_call_return(arg, err); @@ -483,8 +483,6 @@ static void _local_event_unregister(void *data) int err; struct sdei_crosscall_args *arg = data; - WARN_ON_ONCE(preemptible()); - err = sdei_api_event_unregister(arg->event->event_num); sdei_cross_call_return(arg, err); @@ -573,8 +571,6 @@ static void _local_event_register(void *data) struct sdei_registered_event *reg; struct sdei_crosscall_args *arg = data; - WARN_ON(preemptible()); - reg = per_cpu_ptr(arg->event->private_registered, smp_processor_id()); err = sdei_api_event_register(arg->event->event_num, sdei_entry_point, reg, 0, 0); @@ -754,6 +750,8 @@ static int sdei_pm_notifier(struct notifier_block *nb, unsigned long action, { int rv; + WARN_ON_ONCE(preemptible()); + switch (action) { case CPU_PM_ENTER: rv = sdei_mask_local_cpu(); @@ -802,7 +800,7 @@ static int sdei_device_freeze(struct device *dev) int err; /* unregister private events */ - cpuhp_remove_state(CPUHP_AP_ARM_SDEI_STARTING); + cpuhp_remove_state(sdei_entry_point); err = sdei_unregister_shared(); if (err) @@ -823,12 +821,15 @@ static int sdei_device_thaw(struct device *dev) return err; } - err = cpuhp_setup_state(CPUHP_AP_ARM_SDEI_STARTING, "SDEI", + err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "SDEI", &sdei_cpuhp_up, &sdei_cpuhp_down); - if (err) + if (err < 0) { pr_warn("Failed to re-register CPU hotplug notifier...\n"); + return err; + } - return err; + sdei_hp_state = err; + return 0; } static int sdei_device_restore(struct device *dev) @@ -860,7 +861,7 @@ static int sdei_reboot_notifier(struct notifier_block *nb, unsigned long action, * We are going to reset the interface, after this there is no point * doing work when we take CPUs offline. */ - cpuhp_remove_state(CPUHP_AP_ARM_SDEI_STARTING); + cpuhp_remove_state(sdei_hp_state); sdei_platform_reset(); @@ -973,13 +974,15 @@ static int sdei_probe(struct platform_device *pdev) goto remove_cpupm; } - err = cpuhp_setup_state(CPUHP_AP_ARM_SDEI_STARTING, "SDEI", + err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "SDEI", &sdei_cpuhp_up, &sdei_cpuhp_down); - if (err) { + if (err < 0) { pr_warn("Failed to register CPU hotplug notifier...\n"); goto remove_reboot; } + sdei_hp_state = err; + return 0; remove_reboot: diff --git a/drivers/firmware/google/framebuffer-coreboot.c b/drivers/firmware/google/framebuffer-coreboot.c index b8b49c06715740de845593db86f6229ad7b805e5..58b1dae60c1930be206675450b4b087f00dd9360 100644 --- a/drivers/firmware/google/framebuffer-coreboot.c +++ b/drivers/firmware/google/framebuffer-coreboot.c @@ -51,9 +51,7 @@ static int framebuffer_probe(struct coreboot_device *dev) fb->green_mask_pos == formats[i].green.offset && fb->green_mask_size == formats[i].green.length && fb->blue_mask_pos == formats[i].blue.offset && - fb->blue_mask_size == formats[i].blue.length && - fb->reserved_mask_pos == formats[i].transp.offset && - fb->reserved_mask_size == formats[i].transp.length) + fb->blue_mask_size == formats[i].blue.length) pdata.format = formats[i].name; } if (!pdata.format) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 513908a0c2622de1b06565dda9db72bb08ac0e65..e795bd9c8038e397d37d3db286bd53a1b9c502d4 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -586,8 +586,7 @@ static int qcom_scm_probe(struct platform_device *pdev) static void qcom_scm_shutdown(struct platform_device *pdev) { /* Clean shutdown, disable download mode to allow normal restart */ - if (download_mode) - qcom_scm_set_download_mode(false); + qcom_scm_set_download_mode(false); } static const struct of_device_id qcom_scm_dt_match[] = { diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 5e35a66ed0ae974b3133899e813442838250d155..46acc6440b9a880b988798ed9dc5ee67c30ec9c9 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -205,19 +205,6 @@ static int ti_sci_debugfs_create(struct platform_device *pdev, return 0; } -/** - * ti_sci_debugfs_destroy() - clean up log debug file - * @pdev: platform device pointer - * @info: Pointer to SCI entity information - */ -static void ti_sci_debugfs_destroy(struct platform_device *pdev, - struct ti_sci_info *info) -{ - if (IS_ERR(info->debug_region)) - return; - - debugfs_remove(info->d); -} #else /* CONFIG_DEBUG_FS */ static inline int ti_sci_debugfs_create(struct platform_device *dev, struct ti_sci_info *info) @@ -1937,43 +1924,12 @@ static int ti_sci_probe(struct platform_device *pdev) return ret; } -static int ti_sci_remove(struct platform_device *pdev) -{ - struct ti_sci_info *info; - struct device *dev = &pdev->dev; - int ret = 0; - - of_platform_depopulate(dev); - - info = platform_get_drvdata(pdev); - - if (info->nb.notifier_call) - unregister_restart_handler(&info->nb); - - mutex_lock(&ti_sci_list_mutex); - if (info->users) - ret = -EBUSY; - else - list_del(&info->node); - mutex_unlock(&ti_sci_list_mutex); - - if (!ret) { - ti_sci_debugfs_destroy(pdev, info); - - /* Safe to free channels since no more users */ - mbox_free_channel(info->chan_tx); - mbox_free_channel(info->chan_rx); - } - - return ret; -} - static struct platform_driver ti_sci_driver = { .probe = ti_sci_probe, - .remove = ti_sci_remove, .driver = { .name = "ti-sci", .of_match_table = of_match_ptr(ti_sci_of_match), + .suppress_bind_attrs = true, }, }; module_platform_driver(ti_sci_driver); diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c index c983dac97501b910e020996d53ec04609d99a265..c7db12192facd4eee5aa2cdb5890110143c6c8c7 100644 --- a/drivers/fpga/fpga-bridge.c +++ b/drivers/fpga/fpga-bridge.c @@ -121,7 +121,7 @@ static int fpga_bridge_dev_match(struct device *dev, const void *data) /** * fpga_bridge_get - get an exclusive reference to a fpga bridge * @dev: parent device that fpga bridge was registered with - * @info: fpga manager info + * @info: fpga image specific information * * Given a device, get an exclusive reference to a fpga bridge. * diff --git a/drivers/fsi/fsi-master-ast-cf.c b/drivers/fsi/fsi-master-ast-cf.c index 04d10ea8d343bcd44d4508dd02083e838041df53..a7fc04bf6550a6076f3e6c3c5b3dcf5ed2619196 100644 --- a/drivers/fsi/fsi-master-ast-cf.c +++ b/drivers/fsi/fsi-master-ast-cf.c @@ -1438,3 +1438,4 @@ static struct platform_driver fsi_master_acf = { module_platform_driver(fsi_master_acf); MODULE_LICENSE("GPL"); +MODULE_FIRMWARE(FW_FILE_NAME); diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index e627e0e9001ae2e0dd5ccecec849e900038c046a..ba1cd971d50b68911a4d03c764892d8b2bc7405d 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -999,7 +999,7 @@ static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, else if (param == PIN_CONFIG_BIAS_DISABLE || param == PIN_CONFIG_BIAS_PULL_DOWN || param == PIN_CONFIG_DRIVE_STRENGTH) - return pinctrl_gpio_set_config(offset, config); + return pinctrl_gpio_set_config(chip->base + offset, config); else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN || param == PIN_CONFIG_DRIVE_OPEN_SOURCE) /* Return -ENOTSUPP to trigger emulation, as per datasheet */ diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index abb332d15a1317a4e962b9152e4f7caf6356ef44..ead75c1062fbcaecbb95430078ca0907a075c23c 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -327,7 +327,7 @@ static struct irq_chip gpio_irqchip = { .irq_enable = gpio_irq_enable, .irq_disable = gpio_irq_disable, .irq_set_type = gpio_irq_type, - .flags = IRQCHIP_SET_TYPE_MASKED, + .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE, }; static void gpio_irq_handler(struct irq_desc *desc) diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c index 29e044ff4b17d0c607a6fbe1388aac18d527b5a6..7697cb96bf36f3e1073249ed08731e2dafbd9f04 100644 --- a/drivers/gpio/gpio-pmic-eic-sprd.c +++ b/drivers/gpio/gpio-pmic-eic-sprd.c @@ -341,6 +341,7 @@ static int sprd_pmic_eic_probe(struct platform_device *pdev) pmic_eic->chip.set_config = sprd_pmic_eic_set_config; pmic_eic->chip.set = sprd_pmic_eic_set; pmic_eic->chip.get = sprd_pmic_eic_get; + pmic_eic->chip.can_sleep = true; pmic_eic->intc.name = dev_name(&pdev->dev); pmic_eic->intc.irq_mask = sprd_pmic_eic_irq_mask; diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index bcc6be4a5cb2ed38c000c6e15a99e91692c81c2c..61df316e0d17a42c7679273c4b1cfe4e85374d05 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c @@ -246,6 +246,7 @@ static bool pxa_gpio_has_pinctrl(void) switch (gpio_type) { case PXA3XX_GPIO: case MMP2_GPIO: + case MMP_GPIO: return false; default: diff --git a/drivers/gpio/gpio-tb10x.c b/drivers/gpio/gpio-tb10x.c index a12cd0b5c9721d487583c09b58fddebeaa8ab136..1d80bae86ec96c6c79f7f39087c05022136cea86 100644 --- a/drivers/gpio/gpio-tb10x.c +++ b/drivers/gpio/gpio-tb10x.c @@ -246,7 +246,7 @@ static int tb10x_gpio_probe(struct platform_device *pdev) handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE, IRQ_GC_INIT_MASK_CACHE); if (ret) - return ret; + goto err_remove_domain; gc = tb10x_gpio->domain->gc->gc[0]; gc->reg_base = tb10x_gpio->base; @@ -260,6 +260,10 @@ static int tb10x_gpio_probe(struct platform_device *pdev) } return 0; + +err_remove_domain: + irq_domain_remove(tb10x_gpio->domain); + return ret; } static int tb10x_gpio_remove(struct platform_device *pdev) diff --git a/drivers/gpio/gpio-timberdale.c b/drivers/gpio/gpio-timberdale.c index 314e300d6ba33ac0724eb41510caa08a697aff1d..1e6925c27ae2911e790763e1d59028e968e54faa 100644 --- a/drivers/gpio/gpio-timberdale.c +++ b/drivers/gpio/gpio-timberdale.c @@ -55,9 +55,10 @@ static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index, unsigned offset, bool enabled) { struct timbgpio *tgpio = gpiochip_get_data(gpio); + unsigned long flags; u32 reg; - spin_lock(&tgpio->lock); + spin_lock_irqsave(&tgpio->lock, flags); reg = ioread32(tgpio->membase + offset); if (enabled) @@ -66,7 +67,7 @@ static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index, reg &= ~(1 << index); iowrite32(reg, tgpio->membase + offset); - spin_unlock(&tgpio->lock); + spin_unlock_irqrestore(&tgpio->lock, flags); return 0; } diff --git a/drivers/gpio/gpio-tps68470.c b/drivers/gpio/gpio-tps68470.c index aff6e504c6668f80feca4dc2e7cd38dc4238374e..9704cff9b4aa3a07e08c46e99d0e479a1ad1bbaa 100644 --- a/drivers/gpio/gpio-tps68470.c +++ b/drivers/gpio/gpio-tps68470.c @@ -91,13 +91,13 @@ static int tps68470_gpio_output(struct gpio_chip *gc, unsigned int offset, struct tps68470_gpio_data *tps68470_gpio = gpiochip_get_data(gc); struct regmap *regmap = tps68470_gpio->tps68470_regmap; + /* Set the initial value */ + tps68470_gpio_set(gc, offset, value); + /* rest are always outputs */ if (offset >= TPS68470_N_REGULAR_GPIO) return 0; - /* Set the initial value */ - tps68470_gpio_set(gc, offset, value); - return regmap_update_bits(regmap, TPS68470_GPIO_CTL_REG_A(offset), TPS68470_GPIO_MODE_MASK, TPS68470_GPIO_MODE_OUT_CMOS); diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c index f7692999df475a183be2c32c235e0f279d0e9738..df400d14ed17a114bc17885730e8ec0bd08a101d 100644 --- a/drivers/gpio/gpio-vf610.c +++ b/drivers/gpio/gpio-vf610.c @@ -137,14 +137,14 @@ static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, unsigned long mask = BIT(gpio); u32 val; + vf610_gpio_set(chip, gpio, value); + if (port->sdata && port->sdata->have_paddr) { val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); val |= mask; vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); } - vf610_gpio_set(chip, gpio, value); - return pinctrl_gpio_direction_output(chip->base + gpio); } @@ -279,7 +279,7 @@ static int vf610_gpio_probe(struct platform_device *pdev) gc = &port->gc; gc->of_node = np; gc->parent = dev; - gc->label = "vf610-gpio"; + gc->label = dev_name(dev); gc->ngpio = VF610_GPIO_PER_PORT; gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index acbd33fcb73d357f682aabf11d77af77068cd3a7..45e6dfa330adc429a9afd26c8482850a15da7784 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -950,6 +950,12 @@ struct amdgpu_gfx { /* NGG */ struct amdgpu_ngg ngg; + /* gfx off */ + bool gfx_off_state; /* true: enabled, false: disabled */ + struct mutex gfx_off_mutex; + uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ + struct delayed_work gfx_off_delay_work; + /* pipe reservation */ struct mutex pipe_reserve_mutex; DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); @@ -1776,6 +1782,7 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, const u32 array_size); bool amdgpu_device_is_px(struct drm_device *dev); +void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); /* atpx handler */ #if defined(CONFIG_VGA_SWITCHEROO) void amdgpu_register_atpx_handler(void); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index fda8d68a87fd6087d9490e339effc6ab809eb4b1..b9a94c431f09186f3008d363457961bf945820f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -168,6 +168,7 @@ int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id, } rcu_read_unlock(); + *result = NULL; return -ENOENT; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index e667bcf64bc7f296edbee70a373d350fc952a5ba..70e446c2acf823dd0142b1592032e454d86c76a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1502,15 +1502,15 @@ static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev, continue; r = dma_fence_wait_timeout(fence, true, timeout); + if (r > 0 && fence->error) + r = fence->error; + dma_fence_put(fence); if (r < 0) return r; if (r == 0) break; - - if (fence->error) - return fence->error; } memset(wait, 0, sizeof(*wait)); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index ee4a0b7cb452fd7ee6175c5c6b38361a772ccf45..41a9cc9e0f9db2c04fc961c27be30f6bf3c090c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -391,6 +391,9 @@ static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, ssize_t result = 0; int r; + if (!adev->smc_rreg) + return -EPERM; + if (size & 0x3 || *pos & 0x3) return -EINVAL; @@ -430,6 +433,9 @@ static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user * ssize_t result = 0; int r; + if (!adev->smc_wreg) + return -EPERM; + if (size & 0x3 || *pos & 0x3) return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 102b05b8f0c2bf9b4bda5f283c670c1a77b49ea1..c84f475d4f136959712eb7810d661ddb14d772da 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -735,6 +735,9 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) u16 cmd; int r; + if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) + return 0; + /* Bypass for VF */ if (amdgpu_sriov_vf(adev)) return 0; @@ -1927,6 +1930,19 @@ static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work) DRM_ERROR("ib ring test failed (%d).\n", r); } +static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) +{ + struct amdgpu_device *adev = + container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); + + mutex_lock(&adev->gfx.gfx_off_mutex); + if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { + if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) + adev->gfx.gfx_off_state = true; + } + mutex_unlock(&adev->gfx.gfx_off_mutex); +} + /** * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) * @@ -2369,6 +2385,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->gfx.gpu_clock_mutex); mutex_init(&adev->srbm_mutex); mutex_init(&adev->gfx.pipe_reserve_mutex); + mutex_init(&adev->gfx.gfx_off_mutex); mutex_init(&adev->grbm_idx_mutex); mutex_init(&adev->mn_lock); mutex_init(&adev->virt.vf_errors.lock); @@ -2395,7 +2412,10 @@ int amdgpu_device_init(struct amdgpu_device *adev, INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_device_ip_late_init_func_handler); + INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, + amdgpu_device_delay_enable_gfx_off); + adev->gfx.gfx_off_req_count = 1; adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false; /* Registers mapping */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index eeaa2e825858b1d64aa5c15401e9745e48f4ae77..af42c2464a5989b112c79c830ace82c8a28775f4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -26,6 +26,9 @@ #include "amdgpu.h" #include "amdgpu_gfx.h" +/* 0.5 second timeout */ +#define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(500) + /* * GPU scratch registers helpers function. */ @@ -340,3 +343,40 @@ void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev) &ring->mqd_gpu_addr, &ring->mqd_ptr); } + +/* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable + * + * @adev: amdgpu_device pointer + * @bool enable true: enable gfx off feature, false: disable gfx off feature + * + * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled. + * 2. other client can send request to disable gfx off feature, the request should be honored. + * 3. other client can cancel their request of disable gfx off feature + * 4. other client should not send request to enable gfx off feature before disable gfx off feature. + */ + +void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) +{ + if (!(adev->powerplay.pp_feature & PP_GFXOFF_MASK)) + return; + + if (!adev->powerplay.pp_funcs->set_powergating_by_smu) + return; + + + mutex_lock(&adev->gfx.gfx_off_mutex); + + if (!enable) + adev->gfx.gfx_off_req_count++; + else if (adev->gfx.gfx_off_req_count > 0) + adev->gfx.gfx_off_req_count--; + + if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { + schedule_delayed_work(&adev->gfx.gfx_off_delay_work, GFX_OFF_DELAY_ENABLE); + } else if (!enable && adev->gfx.gfx_off_state) { + if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) + adev->gfx.gfx_off_state = false; + } + + mutex_unlock(&adev->gfx.gfx_off_mutex); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c index 0b70410488b66cb270da578c7b1f82916f1bb23f..018f06f154b88b00fbafe3f313786ddcb6fe8167 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c @@ -55,6 +55,7 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev, { struct file *filp = fget(fd); struct amdgpu_fpriv *fpriv; + struct amdgpu_ctx_mgr *mgr; struct amdgpu_ctx *ctx; uint32_t id; int r; @@ -68,14 +69,50 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev, return r; } - idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id) + mgr = &fpriv->ctx_mgr; + mutex_lock(&mgr->lock); + idr_for_each_entry(&mgr->ctx_handles, ctx, id) amdgpu_ctx_priority_override(ctx, priority); + mutex_unlock(&mgr->lock); fput(filp); return 0; } +static int amdgpu_sched_context_priority_override(struct amdgpu_device *adev, + int fd, + unsigned ctx_id, + enum drm_sched_priority priority) +{ + struct file *filp = fget(fd); + struct amdgpu_fpriv *fpriv; + struct amdgpu_ctx *ctx; + int r; + + if (!filp) + return -EINVAL; + + r = amdgpu_file_to_fpriv(filp, &fpriv); + if (r) { + fput(filp); + return r; + } + + ctx = amdgpu_ctx_get(fpriv, ctx_id); + + if (!ctx) { + fput(filp); + return -EINVAL; + } + + amdgpu_ctx_priority_override(ctx, priority); + amdgpu_ctx_put(ctx); + fput(filp); + + return 0; +} + int amdgpu_sched_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { @@ -85,7 +122,7 @@ int amdgpu_sched_ioctl(struct drm_device *dev, void *data, int r; priority = amdgpu_to_sched_priority(args->in.priority); - if (args->in.flags || priority == DRM_SCHED_PRIORITY_INVALID) + if (priority == DRM_SCHED_PRIORITY_INVALID) return -EINVAL; switch (args->in.op) { @@ -94,6 +131,12 @@ int amdgpu_sched_ioctl(struct drm_device *dev, void *data, args->in.fd, priority); break; + case AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE: + r = amdgpu_sched_context_priority_override(adev, + args->in.fd, + args->in.ctx_id, + priority); + break; default: DRM_ERROR("Invalid sched op specified: %d\n", args->in.op); r = -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 6a1f5df4bc07ed59c86d29b253ca734f4862dfef..cdcf9e697c3987d2d7ad01cad1627bdb2ad9bd2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2989,6 +2989,10 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) struct amdgpu_fpriv *fpriv = filp->driver_priv; int r; + /* No valid flags defined yet */ + if (args->in.flags) + return -EINVAL; + switch (args->in.op) { case AMDGPU_VM_OP_RESERVE_VMID: /* current, we only have requirement to reserve vmid from gfxhub */ diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 78ab939ae5d864f54b88eda53847e0fbf5dca7ca..7ff16edcda2665643f8276eddde84f9e7d2996d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1377,7 +1377,6 @@ static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) static void cik_pcie_gen3_enable(struct amdgpu_device *adev) { struct pci_dev *root = adev->pdev->bus->self; - int bridge_pos, gpu_pos; u32 speed_cntl, current_data_rate; int i; u16 tmp16; @@ -1412,12 +1411,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); } - bridge_pos = pci_pcie_cap(root); - if (!bridge_pos) - return; - - gpu_pos = pci_pcie_cap(adev->pdev); - if (!gpu_pos) + if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) return; if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { @@ -1427,14 +1421,8 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); - - tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); - - tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); + pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> @@ -1458,15 +1446,23 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) for (i = 0; i < 10; i++) { /* check status */ - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); + pcie_capability_read_word(adev->pdev, + PCI_EXP_DEVSTA, + &tmp16); if (tmp16 & PCI_EXP_DEVSTA_TRPND) break; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &bridge_cfg); + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL, + &gpu_cfg); - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &bridge_cfg2); + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL2, + &gpu_cfg2); tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; @@ -1479,26 +1475,38 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) msleep(100); /* linkctl */ - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); - - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + bridge_cfg & + PCI_EXP_LNKCTL_HAWD); + pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + gpu_cfg & + PCI_EXP_LNKCTL_HAWD); /* linkctl2 */ - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); - - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &tmp16); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (bridge_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); + pcie_capability_write_word(root, + PCI_EXP_LNKCTL2, + tmp16); + + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL2, + &tmp16); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (gpu_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); + pcie_capability_write_word(adev->pdev, + PCI_EXP_LNKCTL2, + tmp16); tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; @@ -1513,15 +1521,16 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK; WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~0xf; + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16); + tmp16 &= ~PCI_EXP_LNKCTL2_TLS; + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) - tmp16 |= 3; /* gen3 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) - tmp16 |= 2; /* gen2 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ else - tmp16 |= 1; /* gen1 */ - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16); speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 77c9f4d8668adf96e2042240206c90d606ec1b7c..580d74f26b69f1c6211ce95b95b5440309e22434 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1558,7 +1558,6 @@ static void si_init_golden_registers(struct amdgpu_device *adev) static void si_pcie_gen3_enable(struct amdgpu_device *adev) { struct pci_dev *root = adev->pdev->bus->self; - int bridge_pos, gpu_pos; u32 speed_cntl, current_data_rate; int i; u16 tmp16; @@ -1593,12 +1592,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); } - bridge_pos = pci_pcie_cap(root); - if (!bridge_pos) - return; - - gpu_pos = pci_pcie_cap(adev->pdev); - if (!gpu_pos) + if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) return; if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { @@ -1607,14 +1601,8 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); - - tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); - - tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); + pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); tmp = RREG32_PCIE(PCIE_LC_STATUS1); max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; @@ -1631,15 +1619,23 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) } for (i = 0; i < 10; i++) { - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); + pcie_capability_read_word(adev->pdev, + PCI_EXP_DEVSTA, + &tmp16); if (tmp16 & PCI_EXP_DEVSTA_TRPND) break; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &bridge_cfg); + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL, + &gpu_cfg); - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &bridge_cfg2); + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL2, + &gpu_cfg2); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp |= LC_SET_QUIESCE; @@ -1651,25 +1647,37 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) mdelay(100); - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); - - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); - - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); - - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + bridge_cfg & + PCI_EXP_LNKCTL_HAWD); + pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + gpu_cfg & + PCI_EXP_LNKCTL_HAWD); + + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &tmp16); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (bridge_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); + pcie_capability_write_word(root, + PCI_EXP_LNKCTL2, + tmp16); + + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL2, + &tmp16); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (gpu_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); + pcie_capability_write_word(adev->pdev, + PCI_EXP_LNKCTL2, + tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp &= ~LC_SET_QUIESCE; @@ -1682,15 +1690,16 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~0xf; + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16); + tmp16 &= ~PCI_EXP_LNKCTL2_TLS; + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) - tmp16 |= 3; + tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) - tmp16 |= 2; + tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ else - tmp16 |= 1; - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 88b57a5e94892ddb4d41916aa9f38b08536090b5..e8272d4c1fc3a34cda8394285d1b8c14b79c3eba 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -328,8 +328,15 @@ static u32 vi_get_xclk(struct amdgpu_device *adev) u32 reference_clock = adev->clock.spll.reference_freq; u32 tmp; - if (adev->flags & AMD_IS_APU) - return reference_clock; + if (adev->flags & AMD_IS_APU) { + switch (adev->asic_type) { + case CHIP_STONEY: + /* vbios says 48Mhz, but the actual freq is 100Mhz */ + return 10000; + default: + return reference_clock; + } + } tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 892077377339ab1f6f857694174c09e45f84fbed..8f23192b6709597f70b9fbea1c27a053b4a8d4cf 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -529,16 +529,13 @@ static struct kfd_event_waiter *alloc_event_waiters(uint32_t num_events) struct kfd_event_waiter *event_waiters; uint32_t i; - event_waiters = kmalloc_array(num_events, - sizeof(struct kfd_event_waiter), - GFP_KERNEL); + event_waiters = kcalloc(num_events, sizeof(struct kfd_event_waiter), + GFP_KERNEL); if (!event_waiters) return NULL; - for (i = 0; (event_waiters) && (i < num_events) ; i++) { + for (i = 0; i < num_events; i++) init_wait(&event_waiters[i].wait); - event_waiters[i].activated = false; - } return event_waiters; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 57678e6dcdc4c6656244f39cee7eccc08a4755e1..98d51bc2041727fe0d679e0e7ce01f368ed18895 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -773,12 +773,14 @@ static int dm_resume(void *handle) list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { aconnector = to_amdgpu_dm_connector(connector); + if (!aconnector->dc_link) + continue; + /* * this is the case when traversing through already created * MST connectors, should be skipped */ - if (aconnector->dc_link && - aconnector->dc_link->type == dc_connection_mst_branch) + if (aconnector->dc_link->type == dc_connection_mst_branch) continue; mutex_lock(&aconnector->hpd_lock); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index fdcc8ab19bf3f3eb979ab643f7b1d217551f6900..25b8a8f933821def07f12e551835d18c2c188e90 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -281,7 +281,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) for (i = 0; i < MAX_PIPES; i++) { struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; - if (res_ctx->pipe_ctx[i].stream != stream) + if (res_ctx->pipe_ctx[i].stream != stream || !tg) continue; return tg->funcs->get_frame_count(tg); @@ -305,7 +305,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, for (i = 0; i < MAX_PIPES; i++) { struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; - if (res_ctx->pipe_ctx[i].stream != stream) + if (res_ctx->pipe_ctx[i].stream != stream || !tg) continue; tg->funcs->get_scanoutpos(tg, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index 6fd57cfb112f5b15180e5ad5488ab6d17245265c..96fdc18ecb3bfecd08c507036855215b9ff51e70 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -778,7 +778,7 @@ static void dce_transform_set_pixel_storage_depth( color_depth = COLOR_DEPTH_101010; pixel_depth = 0; expan_mode = 1; - BREAK_TO_DEBUGGER(); + DC_LOG_DC("The pixel depth %d is not valid, set COLOR_DEPTH_101010 instead.", depth); break; } @@ -792,8 +792,7 @@ static void dce_transform_set_pixel_storage_depth( if (!(xfm_dce->lb_pixel_depth_supported & depth)) { /*we should use unsupported capabilities * unless it is required by w/a*/ - DC_LOG_WARNING("%s: Capability not supported", - __func__); + DC_LOG_DC("%s: Capability not supported", __func__); } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index ead221ccb93e0aa78f84c5152a1716c13ca85983..ddec675ba690ab707c1c6f6360d9f27fcbcebd60 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2529,7 +2529,9 @@ static void dcn10_wait_for_mpcc_disconnect( if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); - res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); + if (pipe_ctx->stream_res.tg && + pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) + res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; hubp->funcs->set_blank(hubp, true); /*DC_LOG_ERROR(dc->ctx->logger, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index 958994edf2c49de84428848bd25abe15e466a036..12d043521c070323a3a78f8a6350d7d6386f6c10 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -193,8 +193,9 @@ struct mpcc *mpc1_insert_plane( /* check insert_above_mpcc exist in tree->opp_list */ struct mpcc *temp_mpcc = tree->opp_list; - while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) - temp_mpcc = temp_mpcc->mpcc_bot; + if (temp_mpcc != insert_above_mpcc) + while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) + temp_mpcc = temp_mpcc->mpcc_bot; if (temp_mpcc == NULL) return NULL; } diff --git a/drivers/gpu/drm/amd/include/pptable.h b/drivers/gpu/drm/amd/include/pptable.h index 0b6a057e0a4c487d553bab851c80185b8b4eee33..5aac8d545bdc6d45ef4719011307c308579f730e 100644 --- a/drivers/gpu/drm/amd/include/pptable.h +++ b/drivers/gpu/drm/amd/include/pptable.h @@ -78,7 +78,7 @@ typedef struct _ATOM_PPLIB_THERMALCONTROLLER typedef struct _ATOM_PPLIB_STATE { UCHAR ucNonClockStateIndex; - UCHAR ucClockStateIndices[1]; // variable-sized + UCHAR ucClockStateIndices[]; // variable-sized } ATOM_PPLIB_STATE; @@ -473,7 +473,7 @@ typedef struct _ATOM_PPLIB_STATE_V2 /** * Driver will read the first ucNumDPMLevels in this array */ - UCHAR clockInfoIndex[1]; + UCHAR clockInfoIndex[]; } ATOM_PPLIB_STATE_V2; typedef struct _StateArray{ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h index 1e870f58dd12ababe9887083624b10b5d2deedf9..0c61e2bc14cdef8c2b97f34f27400d848a64b311 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h @@ -164,7 +164,7 @@ typedef struct _ATOM_Tonga_State { typedef struct _ATOM_Tonga_State_Array { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_State entries[1]; /* Dynamically allocate entries. */ + ATOM_Tonga_State entries[]; /* Dynamically allocate entries. */ } ATOM_Tonga_State_Array; typedef struct _ATOM_Tonga_MCLK_Dependency_Record { @@ -179,7 +179,7 @@ typedef struct _ATOM_Tonga_MCLK_Dependency_Record { typedef struct _ATOM_Tonga_MCLK_Dependency_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_MCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Tonga_MCLK_Dependency_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Tonga_MCLK_Dependency_Table; typedef struct _ATOM_Tonga_SCLK_Dependency_Record { @@ -194,7 +194,7 @@ typedef struct _ATOM_Tonga_SCLK_Dependency_Record { typedef struct _ATOM_Tonga_SCLK_Dependency_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_SCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Tonga_SCLK_Dependency_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Tonga_SCLK_Dependency_Table; typedef struct _ATOM_Polaris_SCLK_Dependency_Record { @@ -210,7 +210,7 @@ typedef struct _ATOM_Polaris_SCLK_Dependency_Record { typedef struct _ATOM_Polaris_SCLK_Dependency_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Polaris_SCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Polaris_SCLK_Dependency_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Polaris_SCLK_Dependency_Table; typedef struct _ATOM_Tonga_PCIE_Record { @@ -222,7 +222,7 @@ typedef struct _ATOM_Tonga_PCIE_Record { typedef struct _ATOM_Tonga_PCIE_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_PCIE_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Tonga_PCIE_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Tonga_PCIE_Table; typedef struct _ATOM_Polaris10_PCIE_Record { @@ -235,7 +235,7 @@ typedef struct _ATOM_Polaris10_PCIE_Record { typedef struct _ATOM_Polaris10_PCIE_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Polaris10_PCIE_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Polaris10_PCIE_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Polaris10_PCIE_Table; @@ -252,7 +252,7 @@ typedef struct _ATOM_Tonga_MM_Dependency_Record { typedef struct _ATOM_Tonga_MM_Dependency_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_MM_Dependency_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Tonga_MM_Dependency_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Tonga_MM_Dependency_Table; typedef struct _ATOM_Tonga_Voltage_Lookup_Record { @@ -265,7 +265,7 @@ typedef struct _ATOM_Tonga_Voltage_Lookup_Record { typedef struct _ATOM_Tonga_Voltage_Lookup_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_Voltage_Lookup_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Tonga_Voltage_Lookup_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Tonga_Voltage_Lookup_Table; typedef struct _ATOM_Tonga_Fan_Table { diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c index c1d1ac51d1c207c0cb0b2f08825aa19ca7761bde..1f09cb9691f8bed6b3f28490c8a76c78f560ad67 100644 --- a/drivers/gpu/drm/ast/ast_post.c +++ b/drivers/gpu/drm/ast/ast_post.c @@ -291,7 +291,7 @@ static void ast_init_dram_reg(struct drm_device *dev) ; } while (ast_read32(ast, 0x10100) != 0xa8); } else {/* AST2100/1100 */ - if (ast->chip == AST2100 || ast->chip == 2200) + if (ast->chip == AST2100 || ast->chip == AST2200) dram_reg_info = ast2100_dram_table_data; else dram_reg_info = ast1100_dram_table_data; diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c index 31b75d3ca6e90f0f257244a2bf56bf1911f6827f..85aba4c38dc00cf1096f04632f57698c151fdbac 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c @@ -756,8 +756,13 @@ static void adv7511_mode_set(struct adv7511 *adv7511, else low_refresh_rate = ADV7511_LOW_REFRESH_RATE_NONE; - regmap_update_bits(adv7511->regmap, 0xfb, - 0x6, low_refresh_rate << 1); + if (adv7511->type == ADV7511) + regmap_update_bits(adv7511->regmap, 0xfb, + 0x6, low_refresh_rate << 1); + else + regmap_update_bits(adv7511->regmap, 0x4a, + 0xc, low_refresh_rate << 2); + regmap_update_bits(adv7511->regmap, 0x17, 0x60, (vsync_polarity << 6) | (hsync_polarity << 5)); diff --git a/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c b/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c index 07e3a8aaa0e4b379a8b76abb228ee095da192a7c..dfc0ada99b5c5e6eed2eb66dabdc9d40cd7ff08e 100644 --- a/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c +++ b/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c @@ -437,7 +437,11 @@ static int __init stdpxxxx_ge_b850v3_init(void) if (ret) return ret; - return i2c_add_driver(&stdp2690_ge_b850v3_fw_driver); + ret = i2c_add_driver(&stdp2690_ge_b850v3_fw_driver); + if (ret) + i2c_del_driver(&stdp4028_ge_b850v3_fw_driver); + + return ret; } module_init(stdpxxxx_ge_b850v3_init); diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c index c72092319a5333d4e5356e6af99b3ac6cf42547f..214cd2028cd57112e6962c8975dd46a82efaea66 100644 --- a/drivers/gpu/drm/bridge/sil-sii8620.c +++ b/drivers/gpu/drm/bridge/sil-sii8620.c @@ -988,7 +988,7 @@ static void sii8620_set_auto_zone(struct sii8620 *ctx) static void sii8620_stop_video(struct sii8620 *ctx) { - u8 uninitialized_var(val); + u8 val; sii8620_write_seq_static(ctx, REG_TPI_INTR_EN, 0, diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index cb3cc5a2d2ef37a065cf31190ac2929dd76bc108..98f7ac8ca7ac725ea0b0e2225107a44bb5d11f50 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -91,6 +91,12 @@ drm_atomic_state_init(struct drm_device *dev, struct drm_atomic_state *state) if (!state->planes) goto fail; + /* + * Because drm_atomic_state can be committed asynchronously we need our + * own reference and cannot rely on the on implied by drm_file in the + * ioctl call. + */ + drm_dev_get(dev); state->dev = dev; DRM_DEBUG_ATOMIC("Allocated atomic state %p\n", state); @@ -250,7 +256,8 @@ EXPORT_SYMBOL(drm_atomic_state_clear); void __drm_atomic_state_free(struct kref *ref) { struct drm_atomic_state *state = container_of(ref, typeof(*state), ref); - struct drm_mode_config *config = &state->dev->mode_config; + struct drm_device *dev = state->dev; + struct drm_mode_config *config = &dev->mode_config; drm_atomic_state_clear(state); @@ -262,6 +269,8 @@ void __drm_atomic_state_free(struct kref *ref) drm_atomic_state_default_release(state); kfree(state); } + + drm_dev_put(dev); } EXPORT_SYMBOL(__drm_atomic_state_free); diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 31d8906a855df08e316d80e436a364d3bb0689ea..c8d8c4d7f7fbd60704e2a5e3c641023bd6658562 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -1331,14 +1331,14 @@ static struct drm_dp_mst_branch *get_mst_branch_device_by_guid_helper( struct drm_dp_mst_branch *found_mstb; struct drm_dp_mst_port *port; + if (!mstb) + return NULL; + if (memcmp(mstb->guid, guid, 16) == 0) return mstb; list_for_each_entry(port, &mstb->ports, next) { - if (!port->mstb) - continue; - found_mstb = get_mst_branch_device_by_guid_helper(port->mstb, guid); if (found_mstb) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index fa2d9392bbcc96dc2cc3e8158fa91567d21596f3..b1b59570b28f6effaad5aafdaef8783548d47586 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -2793,7 +2793,7 @@ static int drm_cvt_modes(struct drm_connector *connector, const u8 empty[3] = { 0, 0, 0 }; for (i = 0; i < 4; i++) { - int uninitialized_var(width), height; + int width, height; cvt = &(timing->data.other_data.data.cvt[i]); if (!memcmp(cvt->code, empty, 3)) @@ -2801,6 +2801,8 @@ static int drm_cvt_modes(struct drm_connector *connector, height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; switch (cvt->code[1] & 0x0c) { + /* default - because compiler doesn't see that we've enumerated all cases */ + default: case 0x00: width = height * 4 / 3; break; diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index fbe9156c9e7c19e1178bde4bda2e548f31075a7b..ee6801fa36ad1b3cb893942b3e07c18c572abbb9 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -2233,6 +2233,9 @@ static bool drm_target_cloned(struct drm_fb_helper *fb_helper, can_clone = true; dmt_mode = drm_mode_find_dmt(fb_helper->dev, 1024, 768, 60, false); + if (!dmt_mode) + goto fail; + drm_fb_helper_for_each_connector(fb_helper, i) { if (!enabled[i]) continue; @@ -2249,11 +2252,13 @@ static bool drm_target_cloned(struct drm_fb_helper *fb_helper, if (!modes[i]) can_clone = false; } + kfree(dmt_mode); if (can_clone) { DRM_DEBUG_KMS("can clone using 1024x768\n"); return true; } +fail: DRM_INFO("kms: can't enable cloning when we probably wanted to.\n"); return false; } diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index a63eaedec0943e8bce91396260f7e090e997046f..5500789b06a79a1d46c04e79e783930b687bd8a2 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -1101,6 +1101,58 @@ int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi, } EXPORT_SYMBOL(mipi_dsi_dcs_get_display_brightness); +/** + * mipi_dsi_dcs_set_display_brightness_large() - sets the 16-bit brightness value + * of the display + * @dsi: DSI peripheral device + * @brightness: brightness value + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_set_display_brightness_large(struct mipi_dsi_device *dsi, + u16 brightness) +{ + u8 payload[2] = { brightness >> 8, brightness & 0xff }; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, + payload, sizeof(payload)); + if (err < 0) + return err; + + return 0; +} +EXPORT_SYMBOL(mipi_dsi_dcs_set_display_brightness_large); + +/** + * mipi_dsi_dcs_get_display_brightness_large() - gets the current 16-bit + * brightness value of the display + * @dsi: DSI peripheral device + * @brightness: brightness value + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_get_display_brightness_large(struct mipi_dsi_device *dsi, + u16 *brightness) +{ + u8 brightness_be[2]; + ssize_t err; + + err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_BRIGHTNESS, + brightness_be, sizeof(brightness_be)); + if (err <= 0) { + if (err == 0) + err = -ENODATA; + + return err; + } + + *brightness = (brightness_be[0] << 8) | brightness_be[1]; + + return 0; +} +EXPORT_SYMBOL(mipi_dsi_dcs_get_display_brightness_large); + static int mipi_dsi_drv_probe(struct device *dev) { struct mipi_dsi_driver *drv = to_mipi_dsi_driver(dev->driver); diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c index 7a2a148b8ec628351ebef75c140e872546cc59f0..597db0acef95a8110bf2ed0ae5b1ae66fdf9b620 100644 --- a/drivers/gpu/drm/drm_panel_orientation_quirks.c +++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c @@ -44,6 +44,14 @@ static const struct drm_dmi_panel_orientation_data gpd_micropc = { .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, }; +static const struct drm_dmi_panel_orientation_data gpd_onemix2s = { + .width = 1200, + .height = 1920, + .bios_dates = (const char * const []){ "05/21/2018", "10/26/2018", + "03/04/2019", NULL }, + .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, +}; + static const struct drm_dmi_panel_orientation_data gpd_pocket = { .width = 1200, .height = 1920, @@ -219,6 +227,14 @@ static const struct dmi_system_id orientation_data[] = { DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "LTH17"), }, .driver_data = (void *)&lcd800x1280_rightside_up, + }, { /* One Mix 2S (generic strings, also match on bios date) */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Default string"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"), + DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"), + DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"), + }, + .driver_data = (void *)&gpd_onemix2s, }, {} }; diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c index c0b26135dbd5b52f7dd1aa64e49dbce003a7238a..f9e0594ee7024041ba89fb2e8d88e101cf408eb9 100644 --- a/drivers/gpu/drm/drm_probe_helper.c +++ b/drivers/gpu/drm/drm_probe_helper.c @@ -459,8 +459,9 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, */ dev->mode_config.delayed_event = true; if (dev->mode_config.poll_enabled) - schedule_delayed_work(&dev->mode_config.output_poll_work, - 0); + mod_delayed_work(system_wq, + &dev->mode_config.output_poll_work, + 0); } /* Re-enable polling in case the global poll config changed. */ diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c index f21529e635e3d8d9ae16ffd440a425ae5a93abf0..3f9ff6bc7644288a82a88b3f68db82c3db0fe6c1 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c @@ -91,7 +91,15 @@ static void *etnaviv_gem_prime_vmap_impl(struct etnaviv_gem_object *etnaviv_obj) static int etnaviv_gem_prime_mmap_obj(struct etnaviv_gem_object *etnaviv_obj, struct vm_area_struct *vma) { - return dma_buf_mmap(etnaviv_obj->base.dma_buf, vma, 0); + int ret; + + ret = dma_buf_mmap(etnaviv_obj->base.dma_buf, vma, 0); + if (!ret) { + /* Drop the reference acquired by drm_gem_mmap_obj(). */ + drm_gem_object_put_unlocked(&etnaviv_obj->base); + } + + return ret; } static const struct etnaviv_gem_ops etnaviv_gem_prime_ops = { diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index 2696289ecc78f204fb504f24c4f897694acb41df..b3e23ace5869cbf61a6cd0cf2d3801167ef14a29 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -43,13 +43,12 @@ static void exynos_drm_crtc_atomic_disable(struct drm_crtc *crtc, if (exynos_crtc->ops->disable) exynos_crtc->ops->disable(exynos_crtc); + spin_lock_irq(&crtc->dev->event_lock); if (crtc->state->event && !crtc->state->active) { - spin_lock_irq(&crtc->dev->event_lock); drm_crtc_send_vblank_event(crtc, crtc->state->event); - spin_unlock_irq(&crtc->dev->event_lock); - crtc->state->event = NULL; } + spin_unlock_irq(&crtc->dev->event_lock); } static int exynos_crtc_atomic_check(struct drm_crtc *crtc, diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 8d776070913da19f6b690cf6c812ae9343b445f3..8610589299fc65e6a1ad50bf15ff7367b0445734 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -544,9 +544,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, unsigned long best_freq = 0; u32 min_delta = 0xffffffff; u8 p_min, p_max; - u8 _p, uninitialized_var(best_p); - u16 _m, uninitialized_var(best_m); - u8 _s, uninitialized_var(best_s); + u8 _p, best_p; + u16 _m, best_m; + u8 _s, best_s; p_min = DIV_ROUND_UP(fin, (12 * MHZ)); p_max = fin / (6 * MHZ); diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c index f2481a2014bb3c91ac1c8d60711a5fea89f43636..2b7ecc02b2774b6521c6adbaca529acb9ea4f869 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c +++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c @@ -1327,7 +1327,7 @@ int exynos_g2d_exec_ioctl(struct drm_device *drm_dev, void *data, /* Let the runqueue know that there is work to do. */ queue_work(g2d->g2d_workq, &g2d->runqueue_work); - if (runqueue_node->async) + if (req->async) goto out; wait_for_completion(&runqueue_node->complete); diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.h b/drivers/gpu/drm/exynos/exynos_drm_g2d.h index 287b2ed8f1782104e8acf3b71ca3e93c691f71ab..60e420cd4caaa0e72594c9a2aad2c34c5d8b35e8 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_g2d.h +++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.h @@ -37,11 +37,11 @@ static inline int exynos_g2d_exec_ioctl(struct drm_device *dev, void *data, return -ENODEV; } -int g2d_open(struct drm_device *drm_dev, struct drm_file *file) +static inline int g2d_open(struct drm_device *drm_dev, struct drm_file *file) { return 0; } -void g2d_close(struct drm_device *drm_dev, struct drm_file *file) +static inline void g2d_close(struct drm_device *drm_dev, struct drm_file *file) { } #endif diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index 19697c1362d8facf536a55485c45b2b2aaae6a85..947c9627c565a3333b0128d232ca9deaf52ecdc0 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -480,8 +480,6 @@ static int vidi_remove(struct platform_device *pdev) if (ctx->raw_edid != (struct edid *)fake_edid_info) { kfree(ctx->raw_edid); ctx->raw_edid = NULL; - - return -EINVAL; } component_del(&pdev->dev, &vidi_component_ops); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 3b8218dd9bb1463cafb975b8e87afc4723ad9598..16eec72f0fedede521552ba3caaa172444472d0f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1083,7 +1083,7 @@ int intel_ring_pin(struct intel_ring *ring, if (unlikely(ret)) return ret; - if (i915_vma_is_map_and_fenceable(vma)) + if (i915_vma_is_map_and_fenceable(vma) && !HAS_LLC(vma->vm->i915)) addr = (void __force *)i915_vma_pin_iomap(vma); else addr = i915_gem_object_pin_map(vma->obj, map); @@ -1118,7 +1118,7 @@ void intel_ring_unpin(struct intel_ring *ring) /* Discard any unused bytes beyond that submitted to hw. */ intel_ring_reset(ring, ring->tail); - if (i915_vma_is_map_and_fenceable(ring->vma)) + if (i915_vma_is_map_and_fenceable(ring->vma) && !HAS_LLC(ring->vma->vm->i915)) i915_vma_unpin_iomap(ring->vma); else i915_gem_object_unpin_map(ring->vma->obj); @@ -1132,10 +1132,11 @@ static struct i915_vma * intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) { struct i915_address_space *vm = &dev_priv->ggtt.vm; - struct drm_i915_gem_object *obj; + struct drm_i915_gem_object *obj = NULL; struct i915_vma *vma; - obj = i915_gem_object_create_stolen(dev_priv, size); + if (!HAS_LLC(dev_priv)) + obj = i915_gem_object_create_stolen(dev_priv, size); if (!obj) obj = i915_gem_object_create_internal(dev_priv, size); if (IS_ERR(obj)) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index d1432176360714af5c434adc0fd0fd02e499920d..eeb1277794dbf6f375c44f1642fb0b47a7462e5f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -425,6 +425,7 @@ static int mtk_drm_bind(struct device *dev) err_deinit: mtk_drm_kms_deinit(drm); err_free: + private->drm = NULL; drm_dev_put(drm); return ret; } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_gem.c b/drivers/gpu/drm/mediatek/mtk_drm_gem.c index 259b7b0de1d22d7beb052c19e2ef06e4859afcff..b09a37a38e0ae0bb76bad25830599752a84390ab 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_gem.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_gem.c @@ -148,8 +148,6 @@ static int mtk_drm_gem_object_mmap(struct drm_gem_object *obj, ret = dma_mmap_attrs(priv->dma_dev, vma, mtk_gem->cookie, mtk_gem->dma_addr, obj->size, mtk_gem->dma_attrs); - if (ret) - drm_gem_vm_close(vma); return ret; } diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index ba513018534e303697a6a1d450c607f347804bc5..1bdba8cc25d3ed165ef61e2ee15096bc3d8d0d6c 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -173,7 +173,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit * since we've already mapped it once in * submit_reloc() */ - if (WARN_ON(!ptr)) + if (WARN_ON(IS_ERR_OR_NULL(ptr))) return; for (i = 0; i < dwords; i++) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 7d3e9a129ac741d57564f1f680f18438b7e10683..7acb53a907e5c5ace7fa78e7bfda5ca5e46894a6 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -190,8 +190,11 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev) if (ret) return NULL; - /* Make sure pm runtime is active and reset any previous errors */ - pm_runtime_set_active(&pdev->dev); + /* + * Now that we have firmware loaded, and are ready to begin + * booting the gpu, go ahead and enable runpm: + */ + pm_runtime_enable(&pdev->dev); ret = pm_runtime_get_sync(&pdev->dev); if (ret < 0) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index c9f831604558f2fa3a9439a64aae4a6157f68492..6da144c39409740823c2a7e13b918636fb1c3007 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -725,7 +725,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, pm_runtime_set_autosuspend_delay(&pdev->dev, adreno_gpu->info->inactive_period); pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_enable(&pdev->dev); return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, adreno_gpu->info->name, &adreno_gpu_config); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 3c3b7f7013e874de268996cfcbac1605e7f006bc..2efdc3c9f291654be739dc5c4cb130fa2391e448 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1477,6 +1477,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL); + if (!pstates) + return -ENOMEM; dpu_crtc = to_dpu_crtc(crtc); cstate = to_dpu_crtc_state(state); diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c index 501d7989b9a5f86eff25ece9df8d97bc9a33249c..cd5b9ee22a5bba2aafa6dca80f441e8e5bc77a9f 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c @@ -185,7 +185,7 @@ static void mdp5_plane_reset(struct drm_plane *plane) struct mdp5_plane_state *mdp5_state; if (plane->state && plane->state->fb) - drm_framebuffer_unreference(plane->state->fb); + drm_framebuffer_put(plane->state->fb); kfree(to_mdp5_plane_state(plane->state)); plane->state = NULL; @@ -230,8 +230,7 @@ static void mdp5_plane_destroy_state(struct drm_plane *plane, { struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); - if (state->fb) - drm_framebuffer_unreference(state->fb); + __drm_atomic_helper_plane_destroy_state(state); kfree(pstate); } diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 56cfa0a03fd5b6d260f5d13cc6a26407033890b0..5f4dd3659bf967ad5e333551c41a71aa96319093 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1059,9 +1059,21 @@ static void dsi_wait4video_done(struct msm_dsi_host *msm_host) static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) { + u32 data; + if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) return; + data = dsi_read(msm_host, REG_DSI_STATUS0); + + /* if video mode engine is not busy, its because + * either timing engine was not turned on or the + * DSI controller has finished transmitting the video + * data already, so no need to wait in those cases + */ + if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) + return; + if (msm_host->power_on && msm_host->enabled) { dsi_wait4video_done(msm_host); /* delay 4 ms to skip BLLP */ @@ -1883,6 +1895,9 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) /* setup workqueue */ msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); + if (!msm_host->workqueue) + return -ENOMEM; + INIT_WORK(&msm_host->err_work, dsi_err_worker); INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index e03f08757b252dbbc2458a36678d78066acfec01..b75067854b4d7fa17af6a7e5a0be85b047ee00f0 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -254,6 +254,10 @@ static struct hdmi *msm_hdmi_init(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); hdmi->workq = alloc_ordered_workqueue("msm_hdmi", 0); + if (!hdmi->workq) { + ret = -ENOMEM; + goto fail; + } hdmi->i2c = msm_hdmi_i2c_init(hdmi); if (IS_ERR(hdmi->i2c)) { diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/msm/msm_fence.c index 6c11be79574e57bf3a8ae235d5e8ebaae3673f33..ef79c3661acb43644b677c968ba205fe99aaed78 100644 --- a/drivers/gpu/drm/msm/msm_fence.c +++ b/drivers/gpu/drm/msm/msm_fence.c @@ -31,7 +31,7 @@ msm_fence_context_alloc(struct drm_device *dev, const char *name) return ERR_PTR(-ENOMEM); fctx->dev = dev; - strncpy(fctx->name, name, sizeof(fctx->name)); + strscpy(fctx->name, name, sizeof(fctx->name)); fctx->context = dma_fence_context_alloc(1); init_waitqueue_head(&fctx->event); spin_lock_init(&fctx->spinlock); diff --git a/drivers/gpu/drm/mxsfb/Kconfig b/drivers/gpu/drm/mxsfb/Kconfig index 3ed6849d63cbadca28755b9200ae6536283d3b4e..1a2805c7a0eb783baeceecef81077556fac47f2c 100644 --- a/drivers/gpu/drm/mxsfb/Kconfig +++ b/drivers/gpu/drm/mxsfb/Kconfig @@ -7,6 +7,7 @@ config DRM_MXSFB tristate "i.MX23/i.MX28/i.MX6SX MXSFB LCD controller" depends on DRM && OF depends on COMMON_CLK + depends on ARCH_MXS || ARCH_MXC || COMPILE_TEST select DRM_MXS select DRM_KMS_HELPER select DRM_KMS_CMA_HELPER diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index b71afde8f115a944340816b1e07a0808205567aa..6e6568101963be1e3bd44051c0e4f6c5a216d9c9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -521,6 +521,19 @@ nouveau_connector_set_encoder(struct drm_connector *connector, } } +static void +nouveau_connector_set_edid(struct nouveau_connector *nv_connector, + struct edid *edid) +{ + if (nv_connector->edid != edid) { + struct edid *old_edid = nv_connector->edid; + + drm_connector_update_edid_property(&nv_connector->base, edid); + kfree(old_edid); + nv_connector->edid = edid; + } +} + static enum drm_connector_status nouveau_connector_detect(struct drm_connector *connector, bool force) { @@ -534,13 +547,6 @@ nouveau_connector_detect(struct drm_connector *connector, bool force) int ret; enum drm_connector_status conn_status = connector_status_disconnected; - /* Cleanup the previous EDID block. */ - if (nv_connector->edid) { - drm_connector_update_edid_property(connector, NULL); - kfree(nv_connector->edid); - nv_connector->edid = NULL; - } - /* Outputs are only polled while runtime active, so resuming the * device here is unnecessary (and would deadlock upon runtime suspend * because it waits for polling to finish). We do however, want to @@ -553,22 +559,23 @@ nouveau_connector_detect(struct drm_connector *connector, bool force) ret = pm_runtime_get_sync(dev->dev); if (ret < 0 && ret != -EACCES) { pm_runtime_put_autosuspend(dev->dev); + nouveau_connector_set_edid(nv_connector, NULL); return conn_status; } } nv_encoder = nouveau_connector_ddc_detect(connector); if (nv_encoder && (i2c = nv_encoder->i2c) != NULL) { + struct edid *new_edid; + if ((vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) && nv_connector->type == DCB_CONNECTOR_LVDS) - nv_connector->edid = drm_get_edid_switcheroo(connector, - i2c); + new_edid = drm_get_edid_switcheroo(connector, i2c); else - nv_connector->edid = drm_get_edid(connector, i2c); + new_edid = drm_get_edid(connector, i2c); - drm_connector_update_edid_property(connector, - nv_connector->edid); + nouveau_connector_set_edid(nv_connector, new_edid); if (!nv_connector->edid) { NV_ERROR(drm, "DDC responded, but no EDID for %s\n", connector->name); @@ -601,6 +608,8 @@ nouveau_connector_detect(struct drm_connector *connector, bool force) nouveau_connector_set_encoder(connector, nv_encoder); conn_status = connector_status_connected; goto out; + } else { + nouveau_connector_set_edid(nv_connector, NULL); } nv_encoder = nouveau_connector_of_detect(connector); @@ -643,24 +652,20 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force) struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_connector *nv_connector = nouveau_connector(connector); struct nouveau_encoder *nv_encoder = NULL; + struct edid *edid = NULL; enum drm_connector_status status = connector_status_disconnected; - /* Cleanup the previous EDID block. */ - if (nv_connector->edid) { - drm_connector_update_edid_property(connector, NULL); - kfree(nv_connector->edid); - nv_connector->edid = NULL; - } - nv_encoder = find_encoder(connector, DCB_OUTPUT_LVDS); if (!nv_encoder) - return connector_status_disconnected; + goto out; /* Try retrieving EDID via DDC */ if (!drm->vbios.fp_no_ddc) { status = nouveau_connector_detect(connector, force); - if (status == connector_status_connected) + if (status == connector_status_connected) { + edid = nv_connector->edid; goto out; + } } /* On some laptops (Sony, i'm looking at you) there appears to @@ -673,7 +678,8 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force) * valid - it's not (rh#613284) */ if (nv_encoder->dcb->lvdsconf.use_acpi_for_edid) { - if ((nv_connector->edid = nouveau_acpi_edid(dev, connector))) { + edid = nouveau_acpi_edid(dev, connector); + if (edid) { status = connector_status_connected; goto out; } @@ -693,12 +699,10 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force) * stored for the panel stored in them. */ if (!drm->vbios.fp_no_ddc) { - struct edid *edid = - (struct edid *)nouveau_bios_embedded_edid(dev); + edid = (struct edid *)nouveau_bios_embedded_edid(dev); if (edid) { - nv_connector->edid = - kmemdup(edid, EDID_LENGTH, GFP_KERNEL); - if (nv_connector->edid) + edid = kmemdup(edid, EDID_LENGTH, GFP_KERNEL); + if (edid) status = connector_status_connected; } } @@ -711,8 +715,9 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force) status = connector_status_unknown; #endif - drm_connector_update_edid_property(connector, nv_connector->edid); - nouveau_connector_set_encoder(connector, nv_encoder); + nouveau_connector_set_edid(nv_connector, edid); + if (nv_encoder) + nouveau_connector_set_encoder(connector, nv_encoder); return status; } @@ -937,7 +942,7 @@ nouveau_connector_get_modes(struct drm_connector *connector) * "native" mode as some VBIOS tables require us to use the * pixel clock as part of the lookup... */ - if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) + if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS && nv_connector->native_mode) nouveau_connector_detect_depth(connector); if (nv_encoder->dcb->type == DCB_OUTPUT_TV) diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 81999bed1e4a58f362779f18e30e0714e731e4ed..352660120fcc68dc178e49806a8b985a7a6705a0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -120,10 +120,16 @@ nouveau_name(struct drm_device *dev) static inline bool nouveau_cli_work_ready(struct dma_fence *fence) { - if (!dma_fence_is_signaled(fence)) - return false; - dma_fence_put(fence); - return true; + bool ret = true; + + spin_lock_irq(fence->lock); + if (!dma_fence_is_signaled_locked(fence)) + ret = false; + spin_unlock_irq(fence->lock); + + if (ret == true) + dma_fence_put(fence); + return ret; } static void diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h index 33e932bd73b167559744b9f323e5ca7e35b16c32..378635e6e87a86c09dd1ba51543a76a3a6310e7b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h @@ -121,6 +121,7 @@ void gk104_grctx_generate_r418800(struct gf100_gr *); extern const struct gf100_grctx_func gk110_grctx; void gk110_grctx_generate_r419eb0(struct gf100_gr *); +void gk110_grctx_generate_r419f78(struct gf100_gr *); extern const struct gf100_grctx_func gk110b_grctx; extern const struct gf100_grctx_func gk208_grctx; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c index 304e9d268bad42e8a8be6831bb80cc78f5f6caad..f894f82548242fa97f085b7d12b42ca446372a91 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c @@ -916,7 +916,9 @@ static void gk104_grctx_generate_r419f78(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; - nvkm_mask(device, 0x419f78, 0x00000001, 0x00000000); + + /* bit 3 set disables loads in fp helper invocations, we need it enabled */ + nvkm_mask(device, 0x419f78, 0x00000009, 0x00000000); } void diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c index 86547cfc38dce6583efd79205c543fae6385096b..e88740d4e54d446ef3f2b978cead12d05733c890 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c @@ -820,6 +820,15 @@ gk110_grctx_generate_r419eb0(struct gf100_gr *gr) nvkm_mask(device, 0x419eb0, 0x00001000, 0x00001000); } +void +gk110_grctx_generate_r419f78(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + + /* bit 3 set disables loads in fp helper invocations, we need it enabled */ + nvkm_mask(device, 0x419f78, 0x00000008, 0x00000000); +} + const struct gf100_grctx_func gk110_grctx = { .main = gf100_grctx_generate_main, @@ -852,4 +861,5 @@ gk110_grctx = { .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r418800 = gk104_grctx_generate_r418800, .r419eb0 = gk110_grctx_generate_r419eb0, + .r419f78 = gk110_grctx_generate_r419f78, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c index ebb947bd1446bfda0c9574ef98f40fd0cc483a2c..086e4d49e11211653ff2011ecd8f77671da1bc20 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c @@ -101,4 +101,5 @@ gk110b_grctx = { .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r418800 = gk104_grctx_generate_r418800, .r419eb0 = gk110_grctx_generate_r419eb0, + .r419f78 = gk110_grctx_generate_r419f78, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c index 4d40512b5c998588b532f14c708210640e0e1eda..0bf438c3f7cbc9fe2cde323c44ae6a162d6081cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c @@ -566,4 +566,5 @@ gk208_grctx = { .dist_skip_table = gf117_grctx_generate_dist_skip_table, .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r418800 = gk104_grctx_generate_r418800, + .r419f78 = gk110_grctx_generate_r419f78, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c index 0b3964e6b36e2b773e715f33ffd4cb5272161e63..acdf0932a99e187adbb0863f9acfb0b795255987 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c @@ -991,4 +991,5 @@ gm107_grctx = { .r406500 = gm107_grctx_generate_r406500, .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r419e00 = gm107_grctx_generate_r419e00, + .r419f78 = gk110_grctx_generate_r419f78, }; diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c index 58ccf648b70fbde9cbed5241e99ab8119a9af416..e88a7d95a00ced8c69a8ef632ecccc2e8565b99d 100644 --- a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c +++ b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c @@ -454,7 +454,7 @@ static int otm8009a_probe(struct mipi_dsi_device *dsi) ctx->panel.funcs = &otm8009a_drm_funcs; ctx->bl_dev = devm_backlight_device_register(dev, dev_name(dev), - dsi->host->dev, ctx, + dev, ctx, &otm8009a_backlight_ops, NULL); if (IS_ERR(ctx->bl_dev)) { diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index a424afdcc77a122f502edf13d91cdb29bedd5deb..35771e0e69fa6a686e5ac15dd7ffdffc66a47fee 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -405,8 +405,8 @@ static const struct panel_desc ampire_am_480272h3tmqw_t01h = { .num_modes = 1, .bpc = 8, .size = { - .width = 105, - .height = 67, + .width = 99, + .height = 58, }, .bus_format = MEDIA_BUS_FMT_RGB888_1X24, }; diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index 79aef5c063fae2cea412c26d6fc6842ea494122c..5f1b503def551d2b73e7ad0da19237919df95e92 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c @@ -2188,11 +2188,12 @@ int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx) /* * On DCE32 any encoder can drive any block so usually just use crtc id, - * but Apple thinks different at least on iMac10,1, so there use linkb, + * but Apple thinks different at least on iMac10,1 and iMac11,2, so there use linkb, * otherwise the internal eDP panel will stay dark. */ if (ASIC_IS_DCE32(rdev)) { - if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1")) + if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1") || + dmi_match(DMI_PRODUCT_NAME, "iMac11,2")) enc_idx = (dig->linkb) ? 1 : 0; else enc_idx = radeon_crtc->crtc_id; diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index 90c1afe498beaf6c545e7b9d5ecca30ac21f599f..ce8b14592b69b000cc50d44cc53df16ca9c2e043 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c @@ -5552,6 +5552,7 @@ static int ci_parse_power_table(struct radeon_device *rdev) u8 frev, crev; u8 *power_state_offset; struct ci_ps *ps; + int ret; if (!atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset)) @@ -5581,11 +5582,15 @@ static int ci_parse_power_table(struct radeon_device *rdev) non_clock_array_index = power_state->v2.nonClockInfoIndex; non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) &non_clock_info_array->nonClockInfo[non_clock_array_index]; - if (!rdev->pm.power_state[i].clock_info) - return -EINVAL; + if (!rdev->pm.power_state[i].clock_info) { + ret = -EINVAL; + goto err_free_ps; + } ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL); - if (ps == NULL) - return -ENOMEM; + if (ps == NULL) { + ret = -ENOMEM; + goto err_free_ps; + } rdev->pm.dpm.ps[i].ps_priv = ps; ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], non_clock_info, @@ -5625,6 +5630,12 @@ static int ci_parse_power_table(struct radeon_device *rdev) } return 0; + +err_free_ps: + for (i = 0; i < rdev->pm.dpm.num_ps; i++) + kfree(rdev->pm.dpm.ps[i].ps_priv); + kfree(rdev->pm.dpm.ps); + return ret; } static int ci_get_vbios_boot_values(struct radeon_device *rdev, @@ -5713,25 +5724,26 @@ int ci_dpm_init(struct radeon_device *rdev) ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); if (ret) { - ci_dpm_fini(rdev); + kfree(rdev->pm.dpm.priv); return ret; } ret = r600_get_platform_caps(rdev); if (ret) { - ci_dpm_fini(rdev); + kfree(rdev->pm.dpm.priv); return ret; } ret = r600_parse_extended_power_table(rdev); if (ret) { - ci_dpm_fini(rdev); + kfree(rdev->pm.dpm.priv); return ret; } ret = ci_parse_power_table(rdev); if (ret) { - ci_dpm_fini(rdev); + kfree(rdev->pm.dpm.priv); + r600_free_extended_power_table(rdev); return ret; } diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 827d551962d98e0a125fa96246e70cbe98be0c80..643f74c231c5daac5d2cf76cda13b2a8dca24d1e 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -9500,7 +9500,6 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) { struct pci_dev *root = rdev->pdev->bus->self; enum pci_bus_speed speed_cap; - int bridge_pos, gpu_pos; u32 speed_cntl, current_data_rate; int i; u16 tmp16; @@ -9542,12 +9541,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); } - bridge_pos = pci_pcie_cap(root); - if (!bridge_pos) - return; - - gpu_pos = pci_pcie_cap(rdev->pdev); - if (!gpu_pos) + if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev)) return; if (speed_cap == PCIE_SPEED_8_0GT) { @@ -9557,14 +9551,8 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); - - tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); - - tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); + pcie_capability_set_word(rdev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1); max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; @@ -9582,15 +9570,23 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) for (i = 0; i < 10; i++) { /* check status */ - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_DEVSTA, + &tmp16); if (tmp16 & PCI_EXP_DEVSTA_TRPND) break; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &bridge_cfg); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL, + &gpu_cfg); - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &bridge_cfg2); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL2, + &gpu_cfg2); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp |= LC_SET_QUIESCE; @@ -9603,26 +9599,38 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) mdelay(100); /* linkctl */ - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); - - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + bridge_cfg & + PCI_EXP_LNKCTL_HAWD); + pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + gpu_cfg & + PCI_EXP_LNKCTL_HAWD); /* linkctl2 */ - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); - - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &tmp16); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (bridge_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); + pcie_capability_write_word(root, + PCI_EXP_LNKCTL2, + tmp16); + + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL2, + &tmp16); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (gpu_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); + pcie_capability_write_word(rdev->pdev, + PCI_EXP_LNKCTL2, + tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp &= ~LC_SET_QUIESCE; @@ -9636,15 +9644,15 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~0xf; + pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16); + tmp16 &= ~PCI_EXP_LNKCTL2_TLS; if (speed_cap == PCIE_SPEED_8_0GT) - tmp16 |= 3; /* gen3 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ else if (speed_cap == PCIE_SPEED_5_0GT) - tmp16 |= 2; /* gen2 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ else - tmp16 |= 1; /* gen1 */ - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ + pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/cypress_dpm.c index 3eb7899a4035ba070408fb620acbf80e15ffb208..2c637e04dfebc6ee5ff5399c8b6c62e6a0fbfd68 100644 --- a/drivers/gpu/drm/radeon/cypress_dpm.c +++ b/drivers/gpu/drm/radeon/cypress_dpm.c @@ -558,8 +558,12 @@ static int cypress_populate_mclk_value(struct radeon_device *rdev, ASIC_INTERNAL_MEMORY_SS, vco_freq)) { u32 reference_clock = rdev->clock.mpll.reference_freq; u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); - u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); - u32 clk_v = ss.percentage * + u32 clk_s, clk_v; + + if (!decoded_ref) + return -EINVAL; + clk_s = reference_clock * 5 / (decoded_ref * ss.rate); + clk_v = ss.percentage * (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625); mpll_ss1 &= ~CLKV_MASK; diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 5712d63dca2070c43fc3b85f9b6f214e9db3e1c9..da728f7fc42bec71a7fbc9398da4833dcf844d57 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -4815,14 +4815,15 @@ int evergreen_irq_process(struct radeon_device *rdev) break; case 44: /* hdmi */ afmt_idx = src_data; - if (!(afmt_status[afmt_idx] & AFMT_AZ_FORMAT_WTRIG)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - if (afmt_idx > 5) { DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); break; } + + if (!(afmt_status[afmt_idx] & AFMT_AZ_FORMAT_WTRIG)) + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); + afmt_status[afmt_idx] &= ~AFMT_AZ_FORMAT_WTRIG; queue_hdmi = true; DRM_DEBUG("IH: HDMI%d\n", afmt_idx + 1); diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c index a7273c01de34b09239ec22d4584e91dfb529ff05..2a9d415400f79c7c7d4512ac39bf3d4dc75579ad 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.c +++ b/drivers/gpu/drm/radeon/ni_dpm.c @@ -2239,8 +2239,12 @@ static int ni_populate_mclk_value(struct radeon_device *rdev, ASIC_INTERNAL_MEMORY_SS, vco_freq)) { u32 reference_clock = rdev->clock.mpll.reference_freq; u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); - u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); - u32 clk_v = ss.percentage * + u32 clk_s, clk_v; + + if (!decoded_ref) + return -EINVAL; + clk_s = reference_clock * 5 / (decoded_ref * ss.rate); + clk_v = ss.percentage * (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625); mpll_ss1 &= ~CLKV_MASK; diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index 1ae31dbc61c64a2fbf30ede3a84fa0ea315fe8b5..5e61abb3dce5c8b9bec6eaac9f248a68557c5b0c 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -265,7 +265,8 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) { struct drm_radeon_cs *cs = data; uint64_t *chunk_array_ptr; - unsigned size, i; + u64 size; + unsigned i; u32 ring = RADEON_CS_RING_GFX; s32 priority = 0; diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index cc1c07963116c3a60ad920c1cd41fd41b8e4f91e..bcca0dd67fd15b827e0e519018ce94f8c62ab4ba 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -1015,6 +1015,7 @@ void radeon_atombios_fini(struct radeon_device *rdev) { if (rdev->mode_info.atom_context) { kfree(rdev->mode_info.atom_context->scratch); + kfree(rdev->mode_info.atom_context->iio); } kfree(rdev->mode_info.atom_context); rdev->mode_info.atom_context = NULL; diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index 8572caf8588b6fd323c8feab933466485c2fb74c..4efbc230c3f384bf07d43bb1c5934dc7b254fb2d 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -379,7 +379,6 @@ int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, struct radeon_device *rdev = dev->dev_private; struct drm_radeon_gem_set_domain *args = data; struct drm_gem_object *gobj; - struct radeon_bo *robj; int r; /* for now if someone requests domain CPU - @@ -392,13 +391,12 @@ int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, up_read(&rdev->exclusive_lock); return -ENOENT; } - robj = gem_to_radeon_bo(gobj); r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain); drm_gem_object_put_unlocked(gobj); up_read(&rdev->exclusive_lock); - r = radeon_gem_handle_lockup(robj->rdev, r); + r = radeon_gem_handle_lockup(rdev, r); return r; } diff --git a/drivers/gpu/drm/radeon/rv740_dpm.c b/drivers/gpu/drm/radeon/rv740_dpm.c index afd597ec50858691e2e75fa025b96a0f9c251cd9..50290e93c79dc9c0134b558ed119f88553c2a29e 100644 --- a/drivers/gpu/drm/radeon/rv740_dpm.c +++ b/drivers/gpu/drm/radeon/rv740_dpm.c @@ -251,8 +251,12 @@ int rv740_populate_mclk_value(struct radeon_device *rdev, ASIC_INTERNAL_MEMORY_SS, vco_freq)) { u32 reference_clock = rdev->clock.mpll.reference_freq; u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); - u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); - u32 clk_v = 0x40000 * ss.percentage * + u32 clk_s, clk_v; + + if (!decoded_ref) + return -EINVAL; + clk_s = reference_clock * 5 / (decoded_ref * ss.rate); + clk_v = 0x40000 * ss.percentage * (dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000); mpll_ss1 &= ~CLKV_MASK; diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 639f0698f961cdb9903cf90ab18bffc6cb9eea8e..644ddd8d65ad5235cadb43a738492645b3919025 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -3253,7 +3253,7 @@ static void si_gpu_init(struct radeon_device *rdev) /* XXX what about 12? */ rdev->config.si.tile_config |= (3 << 0); break; - } + } switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { case 0: /* four banks */ rdev->config.si.tile_config |= 0 << 4; @@ -7083,7 +7083,6 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) { struct pci_dev *root = rdev->pdev->bus->self; enum pci_bus_speed speed_cap; - int bridge_pos, gpu_pos; u32 speed_cntl, current_data_rate; int i; u16 tmp16; @@ -7125,12 +7124,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); } - bridge_pos = pci_pcie_cap(root); - if (!bridge_pos) - return; - - gpu_pos = pci_pcie_cap(rdev->pdev); - if (!gpu_pos) + if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev)) return; if (speed_cap == PCIE_SPEED_8_0GT) { @@ -7140,14 +7134,8 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); - - tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); - - tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); + pcie_capability_set_word(rdev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); tmp = RREG32_PCIE(PCIE_LC_STATUS1); max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; @@ -7165,15 +7153,23 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) for (i = 0; i < 10; i++) { /* check status */ - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_DEVSTA, + &tmp16); if (tmp16 & PCI_EXP_DEVSTA_TRPND) break; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &bridge_cfg); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL, + &gpu_cfg); - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &bridge_cfg2); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL2, + &gpu_cfg2); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp |= LC_SET_QUIESCE; @@ -7186,26 +7182,38 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) mdelay(100); /* linkctl */ - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); - - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + bridge_cfg & + PCI_EXP_LNKCTL_HAWD); + pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + gpu_cfg & + PCI_EXP_LNKCTL_HAWD); /* linkctl2 */ - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); - - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &tmp16); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (bridge_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); + pcie_capability_write_word(root, + PCI_EXP_LNKCTL2, + tmp16); + + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL2, + &tmp16); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (gpu_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); + pcie_capability_write_word(rdev->pdev, + PCI_EXP_LNKCTL2, + tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp &= ~LC_SET_QUIESCE; @@ -7219,15 +7227,15 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~0xf; + pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16); + tmp16 &= ~PCI_EXP_LNKCTL2_TLS; if (speed_cap == PCIE_SPEED_8_0GT) - tmp16 |= 3; /* gen3 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ else if (speed_cap == PCIE_SPEED_5_0GT) - tmp16 |= 2; /* gen2 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ else - tmp16 |= 1; /* gen1 */ - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ + pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c index 3f992e5a75c97b2124a26f0995d7093061cf8324..579652f8b42b3dbdfd9c2618a8ed15ab10a2e4be 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c @@ -1156,6 +1156,7 @@ static int cdn_dp_probe(struct platform_device *pdev) struct cdn_dp_device *dp; struct extcon_dev *extcon; struct phy *phy; + int ret; int i; dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); @@ -1196,9 +1197,19 @@ static int cdn_dp_probe(struct platform_device *pdev) mutex_init(&dp->lock); dev_set_drvdata(dev, dp); - cdn_dp_audio_codec_init(dp, dev); + ret = cdn_dp_audio_codec_init(dp, dev); + if (ret) + return ret; + + ret = component_add(dev, &cdn_dp_component_ops); + if (ret) + goto err_audio_deinit; - return component_add(dev, &cdn_dp_component_ops); + return 0; + +err_audio_deinit: + platform_device_unregister(dp->audio_pdev); + return ret; } static int cdn_dp_remove(struct platform_device *pdev) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c index a8db758d523e94780584090b191625ffdcd28a16..94242fa9e25d17e04ba27031796587247c5fcfb1 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c @@ -270,9 +270,6 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj, else ret = rockchip_drm_gem_object_mmap_dma(obj, vma); - if (ret) - drm_gem_vm_close(vma); - return ret; } diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 69eb0de9973fb7d22ff8738fa63d7d063bd14d4b..ea692046be6149ea8dd13e59899746e698c5820f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -1091,7 +1091,8 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) if (WARN_ON(!crtc->state)) return NULL; - rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); + rockchip_state = kmemdup(to_rockchip_crtc_state(crtc->state), + sizeof(*rockchip_state), GFP_KERNEL); if (!rockchip_state) return NULL; diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index d84e81ff36ad0d906b1002650093748d728ec95b..7d9be2f56ab1e31c39343e626978da83a917146f 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -449,10 +449,8 @@ static int tegra_dpaux_probe(struct platform_device *pdev) return PTR_ERR(dpaux->regs); dpaux->irq = platform_get_irq(pdev, 0); - if (dpaux->irq < 0) { - dev_err(&pdev->dev, "failed to get IRQ\n"); - return -ENXIO; - } + if (dpaux->irq < 0) + return dpaux->irq; if (!pdev->dev.pm_domain) { dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 83108e2430501d51988049de19be69ac99756ad1..adc191ec26a99e57dce4b20228344d71de9d0c2e 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -829,7 +829,7 @@ static int tegra_sor_compute_config(struct tegra_sor *sor, struct drm_dp_link *link) { const u64 f = 100000, link_rate = link->rate * 1000; - const u64 pclk = mode->clock * 1000; + const u64 pclk = (u64)mode->clock * 1000; u64 input, output, watermark, num; struct tegra_sor_params params; u32 num_syms_per_line; diff --git a/drivers/gpu/drm/vc4/vc4_dpi.c b/drivers/gpu/drm/vc4/vc4_dpi.c index f185812970da7a44aa7b82d6ae88942ae673ec9a..0a0c239ed5c814feef0f935b90f2fce58e864d7b 100644 --- a/drivers/gpu/drm/vc4/vc4_dpi.c +++ b/drivers/gpu/drm/vc4/vc4_dpi.c @@ -186,35 +186,45 @@ static void vc4_dpi_encoder_enable(struct drm_encoder *encoder) } drm_connector_list_iter_end(&conn_iter); - if (connector && connector->display_info.num_bus_formats) { - u32 bus_format = connector->display_info.bus_formats[0]; - - switch (bus_format) { - case MEDIA_BUS_FMT_RGB888_1X24: - dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, - DPI_FORMAT); - break; - case MEDIA_BUS_FMT_BGR888_1X24: - dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, - DPI_FORMAT); - dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER); - break; - case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: - dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, - DPI_FORMAT); - break; - case MEDIA_BUS_FMT_RGB666_1X18: - dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, - DPI_FORMAT); - break; - case MEDIA_BUS_FMT_RGB565_1X16: - dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3, - DPI_FORMAT); - break; - default: - DRM_ERROR("Unknown media bus format %d\n", bus_format); - break; + if (connector) { + if (connector->display_info.num_bus_formats) { + u32 bus_format = connector->display_info.bus_formats[0]; + + switch (bus_format) { + case MEDIA_BUS_FMT_RGB888_1X24: + dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, + DPI_FORMAT); + break; + case MEDIA_BUS_FMT_BGR888_1X24: + dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, + DPI_FORMAT); + dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, + DPI_ORDER); + break; + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: + dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, + DPI_FORMAT); + break; + case MEDIA_BUS_FMT_RGB666_1X18: + dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, + DPI_FORMAT); + break; + case MEDIA_BUS_FMT_RGB565_1X16: + dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_1, + DPI_FORMAT); + break; + default: + DRM_ERROR("Unknown media bus format %d\n", + bus_format); + break; + } } + + if (connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) + dpi_c |= DPI_PIXEL_CLK_INVERT; + + if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW) + dpi_c |= DPI_OUTPUT_ENABLE_INVERT; } else { /* Default to 24bit if no connector found. */ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT); diff --git a/drivers/gpu/drm/vgem/vgem_fence.c b/drivers/gpu/drm/vgem/vgem_fence.c index b28876c222b46c6f9b314354d29fb3fd406a979b..04527d8f36236db6893e23ae293180fc607599ca 100644 --- a/drivers/gpu/drm/vgem/vgem_fence.c +++ b/drivers/gpu/drm/vgem/vgem_fence.c @@ -280,4 +280,5 @@ void vgem_fence_close(struct vgem_file *vfile) { idr_for_each(&vfile->fence_idr, __vgem_fence_idr_fini, vfile); idr_destroy(&vfile->fence_idr); + mutex_destroy(&vfile->fence_mutex); } diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c index e65554f5a89d509b9c722adf398d2b4e25d44d35..2480afa466f2b17fff11c84918d651659ebfe7f2 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c @@ -1834,7 +1834,7 @@ static int vmw_cmd_tex_state(struct vmw_private *dev_priv, } *cmd; SVGA3dTextureState *last_state = (SVGA3dTextureState *) - ((unsigned long) header + header->size + sizeof(header)); + ((unsigned long) header + header->size + sizeof(*header)); SVGA3dTextureState *cur_state = (SVGA3dTextureState *) ((unsigned long) header + sizeof(struct vmw_tex_state_cmd)); struct vmw_resource_val_node *ctx_node; diff --git a/drivers/gpu/host1x/hw/syncpt_hw.c b/drivers/gpu/host1x/hw/syncpt_hw.c index a23bb3352d029303a4c3a750532a5e3a73053c0a..b40a537884dde9697117bd876da542fa397adcff 100644 --- a/drivers/gpu/host1x/hw/syncpt_hw.c +++ b/drivers/gpu/host1x/hw/syncpt_hw.c @@ -113,9 +113,6 @@ static void syncpt_assign_to_channel(struct host1x_syncpt *sp, #if HOST1X_HW >= 6 struct host1x *host = sp->host; - if (!host->hv_regs) - return; - host1x_sync_writel(host, HOST1X_SYNC_SYNCPT_CH_APP_CH(ch ? ch->id : 0xff), HOST1X_SYNC_SYNCPT_CH_APP(sp->id)); diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c index 0a7d4395d427bacf0e27cb5251ab74bb6e816ac1..f6e74ff7ef75d4a1a4a77dbbeb7e4fad5d1b7d9c 100644 --- a/drivers/gpu/ipu-v3/ipu-common.c +++ b/drivers/gpu/ipu-v3/ipu-common.c @@ -1238,6 +1238,7 @@ static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) pdev = platform_device_alloc(reg->name, id++); if (!pdev) { ret = -ENOMEM; + of_node_put(of_node); goto err_register; } diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index d051f1dcf6dd113df2452ae614fd4a338e2a0cdd..906ba577b0d28e803ec57c309dfc9e1033bc1f74 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __ADRENO_H #define __ADRENO_H @@ -16,9 +16,6 @@ #define DEVICE_3D_NAME "kgsl-3d" #define DEVICE_3D0_NAME "kgsl-3d0" -/* Index to preemption scratch buffer to store KMD postamble */ -#define KMD_POSTAMBLE_IDX 100 - /* ADRENO_DEVICE - Given a kgsl_device return the adreno device struct */ #define ADRENO_DEVICE(device) \ container_of(device, struct adreno_device, dev) diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index 157a0682c7b87670c24fe61eed0834c33cee5883..2682a11e538494aaf75f2c9252e8d5447823e186 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ /* soc/qcom/cmd-db.h needs types.h */ @@ -388,19 +389,11 @@ static int a6xx_gmu_start(struct kgsl_device *device) gmu_core_regwrite(device, A6XX_GMU_CM3_SYSRESET, 0); /* Make sure the request completes before continuing */ wmb(); + if (timed_poll_check(device, A6XX_GMU_CM3_FW_INIT_RESULT, val, GMU_START_TIMEOUT, mask)) { - u32 val; - - /* - * The breadcrumb is written to a gmu virtual mapping - * which points to dtcm byte offset 0x3fdc. - */ - gmu_core_regread(device, - A6XX_GMU_CM3_DTCM_START + (0x3fdc >> 2), &val); - dev_err(&gmu->pdev->dev, "GMU doesn't boot: 0x%x\n", val); - + dev_err(&gmu->pdev->dev, "GMU doesn't boot\n"); return -ETIMEDOUT; } diff --git a/drivers/gpu/msm/adreno_a6xx_preempt.c b/drivers/gpu/msm/adreno_a6xx_preempt.c index b03b9b26b33e8f91ff1a6d99d18b05c9595a8e94..4d172d23a99726e09cbcc79095d4be3b9bbb5deb 100644 --- a/drivers/gpu/msm/adreno_a6xx_preempt.c +++ b/drivers/gpu/msm/adreno_a6xx_preempt.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include "adreno.h" @@ -558,8 +558,8 @@ unsigned int a6xx_preemption_pre_ibsubmit( * preemption */ if (!adreno_dev->perfcounter) { - u64 kmd_postamble_addr = - PREEMPT_SCRATCH_ADDR(adreno_dev, KMD_POSTAMBLE_IDX); + u64 kmd_postamble_addr = SCRATCH_POSTAMBLE_ADDR + (KGSL_DEVICE(adreno_dev)); *cmds++ = cp_type7_packet(CP_SET_AMBLE, 3); *cmds++ = lower_32_bits(kmd_postamble_addr); @@ -763,6 +763,8 @@ void a6xx_preemption_close(struct adreno_device *adreno_dev) int a6xx_preemption_init(struct adreno_device *adreno_dev) { + u32 flags = ADRENO_FEATURE(adreno_dev, ADRENO_APRIV) ? + KGSL_MEMDESC_PRIVILEGED : 0; struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct adreno_preemption *preempt = &adreno_dev->preempt; struct adreno_ringbuffer *rb; @@ -777,8 +779,8 @@ int a6xx_preemption_init(struct adreno_device *adreno_dev) timer_setup(&preempt->timer, _a6xx_preemption_timer, 0); - ret = kgsl_allocate_global(device, &preempt->scratch, PAGE_SIZE, 0, 0, - "preemption_scratch"); + ret = kgsl_allocate_global(device, &preempt->scratch, PAGE_SIZE, 0, + flags, "preemption_scratch"); /* Allocate mem for storing preemption switch record */ FOR_EACH_RINGBUFFER(adreno_dev, rb, i) { @@ -788,14 +790,15 @@ int a6xx_preemption_init(struct adreno_device *adreno_dev) } /* - * First 8 dwords of the preemption scratch buffer is used to store the - * address for CP to save/restore VPC data. Reserve 11 dwords in the - * preemption scratch buffer from index KMD_POSTAMBLE_IDX for KMD - * postamble pm4 packets + * First 28 dwords of the device scratch buffer are used to store + * shadow rb data. Reserve 11 dwords in the device scratch buffer + * from SCRATCH_POSTAMBLE_OFFSET for KMD postamble pm4 packets. + * This should be in *device->scratch* so that userspace cannot + * access it. */ if (!adreno_dev->perfcounter) { - u32 *postamble = preempt->scratch.hostptr + - (KMD_POSTAMBLE_IDX * sizeof(u64)); + u32 *postamble = device->scratch.hostptr + + SCRATCH_POSTAMBLE_OFFSET; u32 count = 0; postamble[count++] = cp_type7_packet(CP_REG_RMW, 3); diff --git a/drivers/gpu/msm/adreno_snapshot.c b/drivers/gpu/msm/adreno_snapshot.c index 8529084eaaf04cffcbed16f8a028e4ca242fa7e8..96a54bce331811db2f03122032e403abac453c9c 100644 --- a/drivers/gpu/msm/adreno_snapshot.c +++ b/drivers/gpu/msm/adreno_snapshot.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -502,28 +503,15 @@ struct mem_entry { unsigned int type; } __packed; -static int _save_mem_entries(int id, void *ptr, void *data) -{ - struct kgsl_mem_entry *entry = ptr; - struct mem_entry *m = (struct mem_entry *) data; - unsigned int index = id - 1; - - m[index].gpuaddr = entry->memdesc.gpuaddr; - m[index].size = entry->memdesc.size; - m[index].type = kgsl_memdesc_get_memtype(&entry->memdesc); - - return 0; -} - static size_t snapshot_capture_mem_list(struct kgsl_device *device, u8 *buf, size_t remain, void *priv) { struct kgsl_snapshot_mem_list_v2 *header = (struct kgsl_snapshot_mem_list_v2 *)buf; - int num_mem = 0; - int ret = 0; - unsigned int *data = (unsigned int *)(buf + sizeof(*header)); + int id, index = 0, ret = 0, num_mem = 0; struct kgsl_process_private *process = priv; + struct mem_entry *m = (struct mem_entry *)(buf + sizeof(*header)); + struct kgsl_mem_entry *entry; /* we need a process to search! */ if (process == NULL) @@ -550,7 +538,12 @@ static size_t snapshot_capture_mem_list(struct kgsl_device *device, * Walk through the memory list and store the * tuples(gpuaddr, size, memtype) in snapshot */ - idr_for_each(&process->mem_idr, _save_mem_entries, data); + idr_for_each_entry(&process->mem_idr, entry, id) { + m[index].gpuaddr = entry->memdesc.gpuaddr; + m[index].size = entry->memdesc.size; + m[index].type = kgsl_memdesc_get_memtype(&entry->memdesc); + index++; + } ret = sizeof(*header) + (num_mem * sizeof(struct mem_entry)); out: diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index 1d71dcef6218b33e4ba4573479e9bfdb8df8ca04..8e4616da2f1abb4cd4ad59655d44101b23cd04ef 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2133,6 +2133,10 @@ long kgsl_ioctl_gpu_aux_command(struct kgsl_device_private *dev_priv, if (!(param->flags & KGSL_GPU_AUX_COMMAND_TIMELINE)) return -EINVAL; + if ((param->flags & KGSL_GPU_AUX_COMMAND_SYNC) && + (param->numsyncs > KGSL_MAX_SYNCPOINTS)) + return -EINVAL; + context = kgsl_context_get_owner(dev_priv, param->context_id); if (!context) return -EINVAL; @@ -2681,6 +2685,15 @@ static int kgsl_setup_anon_useraddr(struct kgsl_pagetable *pagetable, } #ifdef CONFIG_DMA_SHARED_BUFFER +static int match_file(const void *p, struct file *file, unsigned int fd) +{ + /* + * We must return fd + 1 because iterate_fd stops searching on + * non-zero return, but 0 is a valid fd. + */ + return (p == file) ? (fd + 1) : 0; +} + static void _setup_cache_mode(struct kgsl_mem_entry *entry, struct vm_area_struct *vma) { @@ -2718,6 +2731,8 @@ static int kgsl_setup_dmabuf_useraddr(struct kgsl_device *device, vma = find_vma(current->mm, hostptr); if (vma && vma->vm_file) { + int fd; + ret = check_vma_flags(vma, entry->memdesc.flags); if (ret) { up_read(¤t->mm->mmap_sem); @@ -2733,13 +2748,27 @@ static int kgsl_setup_dmabuf_useraddr(struct kgsl_device *device, return -EFAULT; } - /* - * Take a refcount because dma_buf_put() decrements the - * refcount - */ - get_file(vma->vm_file); - - dmabuf = vma->vm_file->private_data; + /* Look for the fd that matches this vma file */ + fd = iterate_fd(current->files, 0, match_file, vma->vm_file); + if (fd) { + dmabuf = dma_buf_get(fd - 1); + if (IS_ERR(dmabuf)) { + up_read(¤t->mm->mmap_sem); + return PTR_ERR(dmabuf); + } + /* + * It is possible that the fd obtained from iterate_fd + * was closed before passing the fd to dma_buf_get(). + * Hence dmabuf returned by dma_buf_get() could be + * different from vma->vm_file->private_data. Return + * failure if this happens. + */ + if (dmabuf != vma->vm_file->private_data) { + dma_buf_put(dmabuf); + up_read(¤t->mm->mmap_sem); + return -EBADF; + } + } } if (IS_ERR_OR_NULL(dmabuf)) { diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h index 62ad5304171e5c046901a718a3ee239bae69c32a..f3691b6e165b73b14edcb573ea9bb9e9ee7c0bfd 100644 --- a/drivers/gpu/msm/kgsl.h +++ b/drivers/gpu/msm/kgsl.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __KGSL_H #define __KGSL_H @@ -69,6 +70,11 @@ #define SCRATCH_RPTR_GPU_ADDR(dev, id) \ ((dev)->scratch.gpuaddr + SCRATCH_RPTR_OFFSET(id)) +/* OFFSET to KMD postamble packets in scratch buffer */ +#define SCRATCH_POSTAMBLE_OFFSET (100 * sizeof(u64)) +#define SCRATCH_POSTAMBLE_ADDR(dev) \ + ((dev)->scratch.gpuaddr + SCRATCH_POSTAMBLE_OFFSET) + /* Timestamp window used to detect rollovers (half of integer range) */ #define KGSL_TIMESTAMP_WINDOW 0x80000000 diff --git a/drivers/gpu/msm/kgsl_drawobj.c b/drivers/gpu/msm/kgsl_drawobj.c index fc531766617caac3fb7bdda6c616020681a99fdf..63fefc5b98f3fa470f9340f65f239de8b2b0b363 100644 --- a/drivers/gpu/msm/kgsl_drawobj.c +++ b/drivers/gpu/msm/kgsl_drawobj.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ /* @@ -283,7 +283,7 @@ static void drawobj_destroy_sparse(struct kgsl_drawobj *drawobj) } } -static void drawobj_sync_timeline_fence_work(struct irq_work *work) +static void drawobj_sync_timeline_fence_work(struct work_struct *work) { struct kgsl_drawobj_sync_event *event = container_of(work, struct kgsl_drawobj_sync_event, work); @@ -303,7 +303,7 @@ static void drawobj_sync_timeline_fence_callback(struct dma_fence *f, * removing the fence */ if (drawobj_sync_expire(event->device, event)) - irq_work_queue(&event->work); + queue_work(kgsl_driver.mem_workqueue, &event->work); } static void syncobj_destroy(struct kgsl_drawobj *drawobj) @@ -497,7 +497,7 @@ static int drawobj_add_sync_timeline(struct kgsl_device *device, event->device = device; event->context = NULL; event->fence = fence; - init_irq_work(&event->work, drawobj_sync_timeline_fence_work); + INIT_WORK(&event->work, drawobj_sync_timeline_fence_work); INIT_LIST_HEAD(&event->cb.node); diff --git a/drivers/gpu/msm/kgsl_drawobj.h b/drivers/gpu/msm/kgsl_drawobj.h index f61c5d6842c697f1d27d9926f70c2f7a4e8f7a49..cd905a6c110249d3ac96f61e2b031ba6526e6de0 100644 --- a/drivers/gpu/msm/kgsl_drawobj.h +++ b/drivers/gpu/msm/kgsl_drawobj.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __KGSL_DRAWOBJ_H @@ -169,8 +170,8 @@ struct kgsl_drawobj_sync_event { struct dma_fence *fence; /** @cb: Callback struct for KGSL_CMD_SYNCPOINT_TYPE_TIMELINE */ struct dma_fence_cb cb; - /** @work : irq worker for KGSL_CMD_SYNCPOINT_TYPE_TIMELINE */ - struct irq_work work; + /** @work : work_struct for KGSL_CMD_SYNCPOINT_TYPE_TIMELINE */ + struct work_struct work; }; /** diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c index 3897793e189d4ad8416b06bb38fb6e185baf50e6..5fb00ba43abd4d231cec5176f8eef0e1fd284093 100644 --- a/drivers/gpu/msm/kgsl_iommu.c +++ b/drivers/gpu/msm/kgsl_iommu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2440,14 +2440,18 @@ static uint64_t kgsl_iommu_find_svm_region(struct kgsl_pagetable *pagetable, static bool iommu_addr_in_svm_ranges(struct kgsl_iommu_pt *pt, u64 gpuaddr, u64 size) { + u64 end = gpuaddr + size; + + /* Make sure size is not zero and we don't wrap around */ + if (end <= gpuaddr) + return false; + if ((gpuaddr >= pt->compat_va_start && gpuaddr < pt->compat_va_end) && - ((gpuaddr + size) > pt->compat_va_start && - (gpuaddr + size) <= pt->compat_va_end)) + (end > pt->compat_va_start && end <= pt->compat_va_end)) return true; if ((gpuaddr >= pt->svm_start && gpuaddr < pt->svm_end) && - ((gpuaddr + size) > pt->svm_start && - (gpuaddr + size) <= pt->svm_end)) + (end > pt->svm_start && end <= pt->svm_end)) return true; return false; diff --git a/drivers/gpu/msm/kgsl_pool.c b/drivers/gpu/msm/kgsl_pool.c index 14970659c10b8d8827c16487756a7229b3bc3c95..0654f36bc3052dc6a6f306570298e98f57d4c47f 100644 --- a/drivers/gpu/msm/kgsl_pool.c +++ b/drivers/gpu/msm/kgsl_pool.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -61,6 +62,15 @@ _kgsl_get_pool_from_order(unsigned int order) static void _kgsl_pool_add_page(struct kgsl_page_pool *pool, struct page *p) { + /* + * Sanity check to make sure we don't re-pool a page that + * somebody else has a reference to. + */ + if (WARN_ON_ONCE(unlikely(page_count(p) > 1))) { + __free_pages(p, pool->pool_order); + return; + } + kgsl_zero_page(p, pool->pool_order); spin_lock(&pool->list_lock); diff --git a/drivers/gpu/msm/kgsl_reclaim.c b/drivers/gpu/msm/kgsl_reclaim.c index f0bee68705be5fa048f61afe45a20f3bcb8daee5..845ae23af1fad27d0affe76e907af4ec4e3097b5 100644 --- a/drivers/gpu/msm/kgsl_reclaim.c +++ b/drivers/gpu/msm/kgsl_reclaim.c @@ -5,7 +5,9 @@ #include #include +#include #include +#include #include "kgsl_reclaim.h" #include "kgsl_sharedmem.h" @@ -193,6 +195,12 @@ ssize_t kgsl_proc_max_reclaim_limit_show(struct device *dev, return scnprintf(buf, PAGE_SIZE, "%d\n", kgsl_reclaim_max_page_limit); } +static void kgsl_release_page_vec(struct pagevec *pvec) +{ + check_move_unevictable_pages(pvec->pages, pvec->nr); + __pagevec_release(pvec); +} + static int kgsl_reclaim_callback(struct notifier_block *nb, unsigned long pid, void *data) { @@ -266,20 +274,39 @@ static int kgsl_reclaim_callback(struct notifier_block *nb, if (!kgsl_mmu_unmap(memdesc->pagetable, memdesc)) { int i; - + struct pagevec pvec; + + /* + * Pages that are first allocated are by default added + * to unevictable list. To reclaim them, we first clear + * the AS_UNEVICTABLE flag of the shmem file address + * space thus check_move_unevictable_pages() places + * them on the evictable list. + * + * Once reclaim is done, hint that further shmem + * allocations will have to be on the unevictable list. + */ + mapping_clear_unevictable( + memdesc->shmem_filp->f_mapping); + pagevec_init(&pvec); for (i = 0; i < memdesc->page_count; i++) { set_page_dirty_lock(memdesc->pages[i]); spin_lock(&memdesc->lock); - put_page(memdesc->pages[i]); + pagevec_add(&pvec, memdesc->pages[i]); memdesc->pages[i] = NULL; spin_unlock(&memdesc->lock); + if (pagevec_count(&pvec) == PAGEVEC_SIZE) + kgsl_release_page_vec(&pvec); } + if (pagevec_count(&pvec)) + kgsl_release_page_vec(&pvec); memdesc->priv |= KGSL_MEMDESC_RECLAIMED; ret = reclaim_address_space (memdesc->shmem_filp->f_mapping, data); + mapping_set_unevictable(memdesc->shmem_filp->f_mapping); memdesc->reclaimed_page_count += memdesc->page_count; atomic_add(memdesc->page_count, &process->reclaimed_page_count); diff --git a/drivers/gpu/msm/kgsl_sharedmem.c b/drivers/gpu/msm/kgsl_sharedmem.c index 6a2fce9417f14dcafdb08ab1bdd1ccdbd02277b4..045c1fa1af6ea3cc7712500739f099bba785ff53 100644 --- a/drivers/gpu/msm/kgsl_sharedmem.c +++ b/drivers/gpu/msm/kgsl_sharedmem.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved. */ @@ -981,6 +982,7 @@ static int kgsl_memdesc_file_setup(struct kgsl_memdesc *memdesc, uint64_t size) memdesc->shmem_filp = NULL; return ret; } + mapping_set_unevictable(memdesc->shmem_filp->f_mapping); } return 0; diff --git a/drivers/hid/hid-asus.c b/drivers/hid/hid-asus.c index 800b2364e29eaf8ed4de8b78546135ae42253a5a..4dddf3ce32d73a1e75f24226dfa97401c1fff8a7 100644 --- a/drivers/hid/hid-asus.c +++ b/drivers/hid/hid-asus.c @@ -84,6 +84,7 @@ struct asus_kbd_leds { struct hid_device *hdev; struct work_struct work; unsigned int brightness; + spinlock_t lock; bool removed; }; @@ -313,24 +314,42 @@ static int asus_kbd_get_functions(struct hid_device *hdev, return ret; } +static void asus_schedule_work(struct asus_kbd_leds *led) +{ + unsigned long flags; + + spin_lock_irqsave(&led->lock, flags); + if (!led->removed) + schedule_work(&led->work); + spin_unlock_irqrestore(&led->lock, flags); +} + static void asus_kbd_backlight_set(struct led_classdev *led_cdev, enum led_brightness brightness) { struct asus_kbd_leds *led = container_of(led_cdev, struct asus_kbd_leds, cdev); - if (led->brightness == brightness) - return; + unsigned long flags; + spin_lock_irqsave(&led->lock, flags); led->brightness = brightness; - schedule_work(&led->work); + spin_unlock_irqrestore(&led->lock, flags); + + asus_schedule_work(led); } static enum led_brightness asus_kbd_backlight_get(struct led_classdev *led_cdev) { struct asus_kbd_leds *led = container_of(led_cdev, struct asus_kbd_leds, cdev); + enum led_brightness brightness; + unsigned long flags; + + spin_lock_irqsave(&led->lock, flags); + brightness = led->brightness; + spin_unlock_irqrestore(&led->lock, flags); - return led->brightness; + return brightness; } static void asus_kbd_backlight_work(struct work_struct *work) @@ -338,11 +357,11 @@ static void asus_kbd_backlight_work(struct work_struct *work) struct asus_kbd_leds *led = container_of(work, struct asus_kbd_leds, work); u8 buf[] = { FEATURE_KBD_REPORT_ID, 0xba, 0xc5, 0xc4, 0x00 }; int ret; + unsigned long flags; - if (led->removed) - return; - + spin_lock_irqsave(&led->lock, flags); buf[4] = led->brightness; + spin_unlock_irqrestore(&led->lock, flags); ret = asus_kbd_set_report(led->hdev, buf, sizeof(buf)); if (ret < 0) @@ -383,6 +402,7 @@ static int asus_kbd_register_leds(struct hid_device *hdev) drvdata->kbd_backlight->cdev.brightness_set = asus_kbd_backlight_set; drvdata->kbd_backlight->cdev.brightness_get = asus_kbd_backlight_get; INIT_WORK(&drvdata->kbd_backlight->work, asus_kbd_backlight_work); + spin_lock_init(&drvdata->kbd_backlight->lock); ret = devm_led_classdev_register(&hdev->dev, &drvdata->kbd_backlight->cdev); if (ret < 0) { @@ -692,9 +712,13 @@ static int asus_probe(struct hid_device *hdev, const struct hid_device_id *id) static void asus_remove(struct hid_device *hdev) { struct asus_drvdata *drvdata = hid_get_drvdata(hdev); + unsigned long flags; if (drvdata->kbd_backlight) { + spin_lock_irqsave(&drvdata->kbd_backlight->lock, flags); drvdata->kbd_backlight->removed = true; + spin_unlock_irqrestore(&drvdata->kbd_backlight->lock, flags); + cancel_work_sync(&drvdata->kbd_backlight->work); } diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c index 41498375885f04f20f3d28e15f1df5cbf2e851bd..98cda2b738618f00b2fc99b9830a550eba39f7fe 100644 --- a/drivers/hid/hid-core.c +++ b/drivers/hid/hid-core.c @@ -258,6 +258,7 @@ static int hid_add_field(struct hid_parser *parser, unsigned report_type, unsign { struct hid_report *report; struct hid_field *field; + unsigned int max_buffer_size = HID_MAX_BUFFER_SIZE; unsigned int usages; unsigned int offset; unsigned int i; @@ -288,8 +289,11 @@ static int hid_add_field(struct hid_parser *parser, unsigned report_type, unsign offset = report->size; report->size += parser->global.report_size * parser->global.report_count; + if (parser->device->ll_driver->max_buffer_size) + max_buffer_size = parser->device->ll_driver->max_buffer_size; + /* Total size check: Allow for possible report index byte */ - if (report->size > (HID_MAX_BUFFER_SIZE - 1) << 3) { + if (report->size > (max_buffer_size - 1) << 3) { hid_err(parser->device, "report is too long\n"); return -1; } @@ -1576,6 +1580,7 @@ int hid_report_raw_event(struct hid_device *hid, int type, u8 *data, u32 size, struct hid_report_enum *report_enum = hid->report_enum + type; struct hid_report *report; struct hid_driver *hdrv; + int max_buffer_size = HID_MAX_BUFFER_SIZE; unsigned int a; u32 rsize, csize = size; u8 *cdata = data; @@ -1592,10 +1597,13 @@ int hid_report_raw_event(struct hid_device *hid, int type, u8 *data, u32 size, rsize = hid_compute_report_size(report); - if (report_enum->numbered && rsize >= HID_MAX_BUFFER_SIZE) - rsize = HID_MAX_BUFFER_SIZE - 1; - else if (rsize > HID_MAX_BUFFER_SIZE) - rsize = HID_MAX_BUFFER_SIZE; + if (hid->ll_driver->max_buffer_size) + max_buffer_size = hid->ll_driver->max_buffer_size; + + if (report_enum->numbered && rsize >= max_buffer_size) + rsize = max_buffer_size - 1; + else if (rsize > max_buffer_size) + rsize = max_buffer_size; if (csize < rsize) { dbg_hid("report %d is too short, (%d < %d)\n", report->id, diff --git a/drivers/hid/hid-cp2112.c b/drivers/hid/hid-cp2112.c index 637a7ce281c612d11f68984343e664d561ee7470..6dc9ee8adb65f068724bfe0c79e209404eaf25e4 100644 --- a/drivers/hid/hid-cp2112.c +++ b/drivers/hid/hid-cp2112.c @@ -1163,8 +1163,6 @@ static unsigned int cp2112_gpio_irq_startup(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct cp2112_device *dev = gpiochip_get_data(gc); - INIT_DELAYED_WORK(&dev->gpio_poll_worker, cp2112_gpio_poll_callback); - if (!dev->gpio_poll) { dev->gpio_poll = true; schedule_delayed_work(&dev->gpio_poll_worker, 0); @@ -1245,6 +1243,7 @@ static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id) struct cp2112_device *dev; u8 buf[3]; struct cp2112_smbus_config_report config; + struct gpio_irq_chip *girq; int ret; dev = devm_kzalloc(&hdev->dev, sizeof(*dev), GFP_KERNEL); @@ -1348,6 +1347,17 @@ static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id) dev->gc.can_sleep = 1; dev->gc.parent = &hdev->dev; + girq = &dev->gc.irq; + girq->chip = &cp2112_gpio_irqchip; + /* The event comes from the outside so no parent handler */ + girq->parent_handler = NULL; + girq->num_parents = 0; + girq->parents = NULL; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + + INIT_DELAYED_WORK(&dev->gpio_poll_worker, cp2112_gpio_poll_callback); + ret = gpiochip_add_data(&dev->gc, dev); if (ret < 0) { hid_err(hdev, "error registering gpio chip\n"); @@ -1363,17 +1373,8 @@ static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id) chmod_sysfs_attrs(hdev); hid_hw_power(hdev, PM_HINT_NORMAL); - ret = gpiochip_irqchip_add(&dev->gc, &cp2112_gpio_irqchip, 0, - handle_simple_irq, IRQ_TYPE_NONE); - if (ret) { - dev_err(dev->gc.parent, "failed to add IRQ chip\n"); - goto err_sysfs_remove; - } - return ret; -err_sysfs_remove: - sysfs_remove_group(&hdev->dev.kobj, &cp2112_attr_group); err_gpiochip_remove: gpiochip_remove(&dev->gc); err_free_i2c: diff --git a/drivers/hid/hid-google-hammer.c b/drivers/hid/hid-google-hammer.c index 51a827470157b097b9a4660d76dc0e76d3f07884..b36bcc26bbfe3f3613a70ef4a9af5a629a26213d 100644 --- a/drivers/hid/hid-google-hammer.c +++ b/drivers/hid/hid-google-hammer.c @@ -124,6 +124,8 @@ static const struct hid_device_id hammer_devices[] = { USB_VENDOR_ID_GOOGLE, USB_DEVICE_ID_GOOGLE_EEL) }, { HID_DEVICE(BUS_USB, HID_GROUP_GENERIC, USB_VENDOR_ID_GOOGLE, USB_DEVICE_ID_GOOGLE_HAMMER) }, + { HID_DEVICE(BUS_USB, HID_GROUP_GENERIC, + USB_VENDOR_ID_GOOGLE, USB_DEVICE_ID_GOOGLE_JEWEL) }, { HID_DEVICE(BUS_USB, HID_GROUP_GENERIC, USB_VENDOR_ID_GOOGLE, USB_DEVICE_ID_GOOGLE_MAGNEMITE) }, { HID_DEVICE(BUS_USB, HID_GROUP_GENERIC, diff --git a/drivers/hid/hid-holtek-kbd.c b/drivers/hid/hid-holtek-kbd.c index 2f8eb663974445f88d18e56e3d07a61b9a5385bb..72788ca260e08643a2f7ace47820da3faded4ff2 100644 --- a/drivers/hid/hid-holtek-kbd.c +++ b/drivers/hid/hid-holtek-kbd.c @@ -133,6 +133,10 @@ static int holtek_kbd_input_event(struct input_dev *dev, unsigned int type, return -ENODEV; boot_hid = usb_get_intfdata(boot_interface); + if (list_empty(&boot_hid->inputs)) { + hid_err(hid, "no inputs found\n"); + return -ENODEV; + } boot_hid_input = list_first_entry(&boot_hid->inputs, struct hid_input, list); diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index 230e9d1559be04f71c5bd6605eccf1ae3ab36737..36b0d49f5890f63b41dc20625701583a68bb76d4 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -343,6 +343,7 @@ #define USB_VENDOR_ID_DELL 0x413c #define USB_DEVICE_ID_DELL_PIXART_USB_OPTICAL_MOUSE 0x301a +#define USB_DEVICE_ID_DELL_PRO_WIRELESS_KM5221W 0x4503 #define USB_VENDOR_ID_DELORME 0x1163 #define USB_DEVICE_ID_DELORME_EARTHMATE 0x0100 @@ -480,6 +481,7 @@ #define USB_DEVICE_ID_GOOGLE_MOONBALL 0x5044 #define USB_DEVICE_ID_GOOGLE_DON 0x5050 #define USB_DEVICE_ID_GOOGLE_EEL 0x5057 +#define USB_DEVICE_ID_GOOGLE_JEWEL 0x5061 #define USB_VENDOR_ID_GOTOP 0x08f2 #define USB_DEVICE_ID_SUPER_Q2 0x007f @@ -570,6 +572,7 @@ #define USB_DEVICE_ID_UGCI_FIGHTING 0x0030 #define USB_VENDOR_ID_HP 0x03f0 +#define USB_PRODUCT_ID_HP_ELITE_PRESENTER_MOUSE_464A 0x464a #define USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0A4A 0x0a4a #define USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A 0x0b4a #define USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE 0x134a diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c index 504e8917b06f32c316327ac2c4b26cac2c753288..f2982784c4fea619b670f905e0144719978d32ec 100644 --- a/drivers/hid/hid-logitech-hidpp.c +++ b/drivers/hid/hid-logitech-hidpp.c @@ -675,8 +675,7 @@ static int hidpp_unifying_init(struct hidpp_device *hidpp) if (ret) return ret; - snprintf(hdev->uniq, sizeof(hdev->uniq), "%04x-%4phD", - hdev->product, &serial); + snprintf(hdev->uniq, sizeof(hdev->uniq), "%4phD", &serial); dbg_hid("HID++ Unifying: Got serial: %s\n", hdev->uniq); name = hidpp_unifying_get_name(hidpp); @@ -777,6 +776,54 @@ static bool hidpp_is_connected(struct hidpp_device *hidpp) return ret == 0; } +/* -------------------------------------------------------------------------- */ +/* 0x0003: Device Information */ +/* -------------------------------------------------------------------------- */ + +#define HIDPP_PAGE_DEVICE_INFORMATION 0x0003 + +#define CMD_GET_DEVICE_INFO 0x00 + +static int hidpp_get_serial(struct hidpp_device *hidpp, u32 *serial) +{ + struct hidpp_report response; + u8 feature_type; + u8 feature_index; + int ret; + + ret = hidpp_root_get_feature(hidpp, HIDPP_PAGE_DEVICE_INFORMATION, + &feature_index, + &feature_type); + if (ret) + return ret; + + ret = hidpp_send_fap_command_sync(hidpp, feature_index, + CMD_GET_DEVICE_INFO, + NULL, 0, &response); + if (ret) + return ret; + + /* See hidpp_unifying_get_serial() */ + *serial = *((u32 *)&response.rap.params[1]); + return 0; +} + +static int hidpp_serial_init(struct hidpp_device *hidpp) +{ + struct hid_device *hdev = hidpp->hid_dev; + u32 serial; + int ret; + + ret = hidpp_get_serial(hidpp, &serial); + if (ret) + return ret; + + snprintf(hdev->uniq, sizeof(hdev->uniq), "%4phD", &serial); + dbg_hid("HID++ DeviceInformation: Got serial: %s\n", hdev->uniq); + + return 0; +} + /* -------------------------------------------------------------------------- */ /* 0x0005: GetDeviceNameType */ /* -------------------------------------------------------------------------- */ @@ -3040,6 +3087,8 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) if (hidpp->quirks & HIDPP_QUIRK_UNIFYING) hidpp_unifying_init(hidpp); + else if (hid_is_usb(hidpp->hid_dev)) + hidpp_serial_init(hidpp); connected = hidpp_is_connected(hidpp); atomic_set(&hidpp->connected, connected); @@ -3080,7 +3129,8 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) /* Allow incoming packets */ hid_device_io_start(hdev); - hidpp_connect_event(hidpp); + schedule_work(&hidpp->work); + flush_work(&hidpp->work); return ret; diff --git a/drivers/hid/hid-multitouch.c b/drivers/hid/hid-multitouch.c index 4b1c223be993350e80a36d33fd49800d41795fb5..6411ee12c7a30df40cb4629b2991893ffff98562 100644 --- a/drivers/hid/hid-multitouch.c +++ b/drivers/hid/hid-multitouch.c @@ -1540,7 +1540,6 @@ static void mt_post_parse(struct mt_device *td, struct mt_application *app) static int mt_input_configured(struct hid_device *hdev, struct hid_input *hi) { struct mt_device *td = hid_get_drvdata(hdev); - char *name; const char *suffix = NULL; struct mt_report_data *rdata; struct mt_application *mt_application = NULL; @@ -1594,15 +1593,9 @@ static int mt_input_configured(struct hid_device *hdev, struct hid_input *hi) break; } - if (suffix) { - name = devm_kzalloc(&hi->input->dev, - strlen(hdev->name) + strlen(suffix) + 2, - GFP_KERNEL); - if (name) { - sprintf(name, "%s %s", hdev->name, suffix); - hi->input->name = name; - } - } + if (suffix) + hi->input->name = devm_kasprintf(&hdev->dev, GFP_KERNEL, + "%s %s", hdev->name, suffix); return 0; } diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c index aa33ba159e0e2223c035dcde1a70bb68ad14c1f6..51434936346138ea791ad4ef9651833eaabec15d 100644 --- a/drivers/hid/hid-quirks.c +++ b/drivers/hid/hid-quirks.c @@ -68,6 +68,7 @@ static const struct hid_device_id hid_quirks[] = { { HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_STRAFE), HID_QUIRK_NO_INIT_REPORTS | HID_QUIRK_ALWAYS_POLL }, { HID_USB_DEVICE(USB_VENDOR_ID_CREATIVELABS, USB_DEVICE_ID_CREATIVE_SB_OMNI_SURROUND_51), HID_QUIRK_NOGET }, { HID_USB_DEVICE(USB_VENDOR_ID_DELL, USB_DEVICE_ID_DELL_PIXART_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL }, + { HID_USB_DEVICE(USB_VENDOR_ID_DELL, USB_DEVICE_ID_DELL_PRO_WIRELESS_KM5221W), HID_QUIRK_ALWAYS_POLL }, { HID_USB_DEVICE(USB_VENDOR_ID_DMI, USB_DEVICE_ID_DMI_ENC), HID_QUIRK_NOGET }, { HID_USB_DEVICE(USB_VENDOR_ID_DRACAL_RAPHNET, USB_DEVICE_ID_RAPHNET_2NES2SNES), HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_DRACAL_RAPHNET, USB_DEVICE_ID_RAPHNET_4NES4SNES), HID_QUIRK_MULTI_INPUT }, @@ -98,6 +99,7 @@ static const struct hid_device_id hid_quirks[] = { { HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_KEYBOARD_A096), HID_QUIRK_NO_INIT_REPORTS }, { HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_KEYBOARD_A293), HID_QUIRK_ALWAYS_POLL }, { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0A4A), HID_QUIRK_ALWAYS_POLL }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_ELITE_PRESENTER_MOUSE_464A), HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A), HID_QUIRK_ALWAYS_POLL }, { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL }, { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_094A), HID_QUIRK_ALWAYS_POLL }, diff --git a/drivers/hid/uhid.c b/drivers/hid/uhid.c index e128b9ce156df96699431d3596808c72f77658e5..44df81d56d9cada7eb841cfaab17451afb92c527 100644 --- a/drivers/hid/uhid.c +++ b/drivers/hid/uhid.c @@ -398,6 +398,7 @@ struct hid_ll_driver uhid_hid_driver = { .parse = uhid_hid_parse, .raw_request = uhid_hid_raw_request, .output_report = uhid_hid_output_report, + .max_buffer_size = UHID_DATA_MAX, }; EXPORT_SYMBOL_GPL(uhid_hid_driver); diff --git a/drivers/hid/wacom.h b/drivers/hid/wacom.h index 9c0900c35b236b71b9b89ab5d33a922f2f15c7b9..0ee71ce94360749dc27754384fc4699f9471f9d2 100644 --- a/drivers/hid/wacom.h +++ b/drivers/hid/wacom.h @@ -94,6 +94,7 @@ #include #include #include +#include #include /* @@ -155,6 +156,7 @@ struct wacom_remote { struct input_dev *input; bool registered; struct wacom_battery battery; + ktime_t active_time; } remotes[WACOM_MAX_REMOTES]; }; @@ -170,6 +172,7 @@ struct wacom { struct delayed_work init_work; struct wacom_remote *remote; struct work_struct mode_change_work; + struct timer_list idleprox_timer; bool generic_has_leds; struct wacom_leds { struct wacom_group_leds *groups; @@ -242,4 +245,5 @@ struct wacom_led *wacom_led_find(struct wacom *wacom, unsigned int group, struct wacom_led *wacom_led_next(struct wacom *wacom, struct wacom_led *cur); int wacom_equivalent_usage(int usage); int wacom_initialize_leds(struct wacom *wacom); +void wacom_idleprox_timeout(struct timer_list *list); #endif diff --git a/drivers/hid/wacom_sys.c b/drivers/hid/wacom_sys.c index 8e32415e0a9099cabb44ad0e57275f50d2960a36..8255010b03d096bf86007613b8743345cf889a78 100644 --- a/drivers/hid/wacom_sys.c +++ b/drivers/hid/wacom_sys.c @@ -2390,8 +2390,13 @@ static int wacom_parse_and_register(struct wacom *wacom, bool wireless) goto fail_quirks; } - if (features->device_type & WACOM_DEVICETYPE_WL_MONITOR) + if (features->device_type & WACOM_DEVICETYPE_WL_MONITOR) { error = hid_hw_open(hdev); + if (error) { + hid_err(hdev, "hw open failed\n"); + goto fail_quirks; + } + } wacom_set_shared_values(wacom_wac); devres_close_group(&hdev->dev, wacom); @@ -2495,6 +2500,18 @@ static void wacom_wireless_work(struct work_struct *work) return; } +static void wacom_remote_destroy_battery(struct wacom *wacom, int index) +{ + struct wacom_remote *remote = wacom->remote; + + if (remote->remotes[index].battery.battery) { + devres_release_group(&wacom->hdev->dev, + &remote->remotes[index].battery.bat_desc); + remote->remotes[index].battery.battery = NULL; + remote->remotes[index].active_time = 0; + } +} + static void wacom_remote_destroy_one(struct wacom *wacom, unsigned int index) { struct wacom_remote *remote = wacom->remote; @@ -2509,9 +2526,7 @@ static void wacom_remote_destroy_one(struct wacom *wacom, unsigned int index) remote->remotes[i].registered = false; spin_unlock_irqrestore(&remote->remote_lock, flags); - if (remote->remotes[i].battery.battery) - devres_release_group(&wacom->hdev->dev, - &remote->remotes[i].battery.bat_desc); + wacom_remote_destroy_battery(wacom, i); if (remote->remotes[i].group.name) devres_release_group(&wacom->hdev->dev, @@ -2519,7 +2534,6 @@ static void wacom_remote_destroy_one(struct wacom *wacom, unsigned int index) remote->remotes[i].serial = 0; remote->remotes[i].group.name = NULL; - remote->remotes[i].battery.battery = NULL; wacom->led.groups[i].select = WACOM_STATUS_UNKNOWN; } } @@ -2604,6 +2618,9 @@ static int wacom_remote_attach_battery(struct wacom *wacom, int index) if (remote->remotes[index].battery.battery) return 0; + if (!remote->remotes[index].active_time) + return 0; + if (wacom->led.groups[index].select == WACOM_STATUS_UNKNOWN) return 0; @@ -2619,6 +2636,7 @@ static void wacom_remote_work(struct work_struct *work) { struct wacom *wacom = container_of(work, struct wacom, remote_work); struct wacom_remote *remote = wacom->remote; + ktime_t kt = ktime_get(); struct wacom_remote_data data; unsigned long flags; unsigned int count; @@ -2645,6 +2663,10 @@ static void wacom_remote_work(struct work_struct *work) serial = data.remote[i].serial; if (data.remote[i].connected) { + if (kt - remote->remotes[i].active_time > WACOM_REMOTE_BATTERY_TIMEOUT + && remote->remotes[i].active_time != 0) + wacom_remote_destroy_battery(wacom, i); + if (remote->remotes[i].serial == serial) { wacom_remote_attach_battery(wacom, i); continue; @@ -2754,6 +2776,7 @@ static int wacom_probe(struct hid_device *hdev, INIT_WORK(&wacom->battery_work, wacom_battery_work); INIT_WORK(&wacom->remote_work, wacom_remote_work); INIT_WORK(&wacom->mode_change_work, wacom_mode_change_work); + timer_setup(&wacom->idleprox_timer, &wacom_idleprox_timeout, TIMER_DEFERRABLE); /* ask for the report descriptor to be loaded by HID */ error = hid_parse(hdev); @@ -2802,6 +2825,7 @@ static void wacom_remove(struct hid_device *hdev) cancel_work_sync(&wacom->battery_work); cancel_work_sync(&wacom->remote_work); cancel_work_sync(&wacom->mode_change_work); + del_timer_sync(&wacom->idleprox_timer); if (hdev->bus == BUS_BLUETOOTH) device_remove_file(&hdev->dev, &dev_attr_speed); diff --git a/drivers/hid/wacom_wac.c b/drivers/hid/wacom_wac.c index bc4d6474d8f5488a60d5af8c11825bc7f5ea470d..eb5f52e6f19dd2b3f8c2f087ca56b219ac2a7e9b 100644 --- a/drivers/hid/wacom_wac.c +++ b/drivers/hid/wacom_wac.c @@ -15,6 +15,7 @@ #include "wacom_wac.h" #include "wacom.h" #include +#include /* resolution for penabled devices */ #define WACOM_PL_RES 20 @@ -45,6 +46,43 @@ static int wacom_numbered_button_to_key(int n); static void wacom_update_led(struct wacom *wacom, int button_count, int mask, int group); + +static void wacom_force_proxout(struct wacom_wac *wacom_wac) +{ + struct input_dev *input = wacom_wac->pen_input; + + wacom_wac->shared->stylus_in_proximity = 0; + + input_report_key(input, BTN_TOUCH, 0); + input_report_key(input, BTN_STYLUS, 0); + input_report_key(input, BTN_STYLUS2, 0); + input_report_key(input, BTN_STYLUS3, 0); + input_report_key(input, wacom_wac->tool[0], 0); + if (wacom_wac->serial[0]) { + input_report_abs(input, ABS_MISC, 0); + } + input_report_abs(input, ABS_PRESSURE, 0); + + wacom_wac->tool[0] = 0; + wacom_wac->id[0] = 0; + wacom_wac->serial[0] = 0; + + input_sync(input); +} + +void wacom_idleprox_timeout(struct timer_list *list) +{ + struct wacom *wacom = from_timer(wacom, list, idleprox_timer); + struct wacom_wac *wacom_wac = &wacom->wacom_wac; + + if (!wacom_wac->hid_data.sense_state) { + return; + } + + hid_warn(wacom->hdev, "%s: tool appears to be hung in-prox. forcing it out.\n", __func__); + wacom_force_proxout(wacom_wac); +} + /* * Percent of battery capacity for Graphire. * 8th value means AC online and show 100% capacity. @@ -743,7 +781,7 @@ static int wacom_intuos_inout(struct wacom_wac *wacom) /* Enter report */ if ((data[1] & 0xfc) == 0xc0) { /* serial number of the tool */ - wacom->serial[idx] = ((data[3] & 0x0f) << 28) + + wacom->serial[idx] = ((__u64)(data[3] & 0x0f) << 28) + (data[4] << 20) + (data[5] << 12) + (data[6] << 4) + (data[7] >> 4); @@ -1039,6 +1077,7 @@ static int wacom_remote_irq(struct wacom_wac *wacom_wac, size_t len) if (index < 0 || !remote->remotes[index].registered) goto out; + remote->remotes[i].active_time = ktime_get(); input = remote->remotes[index].input; input_report_key(input, BTN_0, (data[9] & 0x01)); @@ -1791,6 +1830,7 @@ static void wacom_map_usage(struct input_dev *input, struct hid_usage *usage, int fmax = field->logical_maximum; unsigned int equivalent_usage = wacom_equivalent_usage(usage->hid); int resolution_code = code; + int resolution = hidinput_calc_abs_res(field, resolution_code); if (equivalent_usage == HID_DG_TWIST) { resolution_code = ABS_RZ; @@ -1813,8 +1853,15 @@ static void wacom_map_usage(struct input_dev *input, struct hid_usage *usage, switch (type) { case EV_ABS: input_set_abs_params(input, code, fmin, fmax, fuzz, 0); - input_abs_set_res(input, code, - hidinput_calc_abs_res(field, resolution_code)); + + /* older tablet may miss physical usage */ + if ((code == ABS_X || code == ABS_Y) && !resolution) { + resolution = WACOM_INTUOS_RES; + hid_warn(input, + "Wacom usage (%d) missing resolution \n", + code); + } + input_abs_set_res(input, code, resolution); break; case EV_KEY: input_set_capability(input, EV_KEY, code); @@ -1831,18 +1878,7 @@ static void wacom_map_usage(struct input_dev *input, struct hid_usage *usage, static void wacom_wac_battery_usage_mapping(struct hid_device *hdev, struct hid_field *field, struct hid_usage *usage) { - struct wacom *wacom = hid_get_drvdata(hdev); - struct wacom_wac *wacom_wac = &wacom->wacom_wac; - struct wacom_features *features = &wacom_wac->features; - unsigned equivalent_usage = wacom_equivalent_usage(usage->hid); - - switch (equivalent_usage) { - case HID_DG_BATTERYSTRENGTH: - case WACOM_HID_WD_BATTERY_LEVEL: - case WACOM_HID_WD_BATTERY_CHARGING: - features->quirks |= WACOM_QUIRK_BATTERY; - break; - } + return; } static void wacom_wac_battery_event(struct hid_device *hdev, struct hid_field *field, @@ -1863,18 +1899,21 @@ static void wacom_wac_battery_event(struct hid_device *hdev, struct hid_field *f wacom_wac->hid_data.bat_connected = 1; wacom_wac->hid_data.bat_status = WACOM_POWER_SUPPLY_STATUS_AUTO; } + wacom_wac->features.quirks |= WACOM_QUIRK_BATTERY; break; case WACOM_HID_WD_BATTERY_LEVEL: value = value * 100 / (field->logical_maximum - field->logical_minimum); wacom_wac->hid_data.battery_capacity = value; wacom_wac->hid_data.bat_connected = 1; wacom_wac->hid_data.bat_status = WACOM_POWER_SUPPLY_STATUS_AUTO; + wacom_wac->features.quirks |= WACOM_QUIRK_BATTERY; break; case WACOM_HID_WD_BATTERY_CHARGING: wacom_wac->hid_data.bat_charging = value; wacom_wac->hid_data.ps_connected = value; wacom_wac->hid_data.bat_connected = 1; wacom_wac->hid_data.bat_status = WACOM_POWER_SUPPLY_STATUS_AUTO; + wacom_wac->features.quirks |= WACOM_QUIRK_BATTERY; break; } } @@ -1890,18 +1929,15 @@ static void wacom_wac_battery_report(struct hid_device *hdev, { struct wacom *wacom = hid_get_drvdata(hdev); struct wacom_wac *wacom_wac = &wacom->wacom_wac; - struct wacom_features *features = &wacom_wac->features; - if (features->quirks & WACOM_QUIRK_BATTERY) { - int status = wacom_wac->hid_data.bat_status; - int capacity = wacom_wac->hid_data.battery_capacity; - bool charging = wacom_wac->hid_data.bat_charging; - bool connected = wacom_wac->hid_data.bat_connected; - bool powered = wacom_wac->hid_data.ps_connected; + int status = wacom_wac->hid_data.bat_status; + int capacity = wacom_wac->hid_data.battery_capacity; + bool charging = wacom_wac->hid_data.bat_charging; + bool connected = wacom_wac->hid_data.bat_connected; + bool powered = wacom_wac->hid_data.ps_connected; - wacom_notify_battery(wacom_wac, status, capacity, charging, - connected, powered); - } + wacom_notify_battery(wacom_wac, status, capacity, charging, + connected, powered); } static void wacom_wac_pad_usage_mapping(struct hid_device *hdev, @@ -2258,6 +2294,7 @@ static void wacom_wac_pen_event(struct hid_device *hdev, struct hid_field *field value = field->logical_maximum - value; break; case HID_DG_INRANGE: + mod_timer(&wacom->idleprox_timer, jiffies + msecs_to_jiffies(100)); wacom_wac->hid_data.inrange_state = value; if (!(features->quirks & WACOM_QUIRK_SENSE)) wacom_wac->hid_data.sense_state = value; diff --git a/drivers/hid/wacom_wac.h b/drivers/hid/wacom_wac.h index fbdbb74f9f1fd413f1ff9612c070d7f4c3c115bf..8ff5e4de60f4cbe359d7fc9eb75d1f9043679ef6 100644 --- a/drivers/hid/wacom_wac.h +++ b/drivers/hid/wacom_wac.h @@ -19,6 +19,7 @@ #define WACOM_NAME_MAX 64 #define WACOM_MAX_REMOTES 5 #define WACOM_STATUS_UNKNOWN 255 +#define WACOM_REMOTE_BATTERY_TIMEOUT 21000000000ll /* packet length for individual models */ #define WACOM_PKGLEN_BBFUN 9 diff --git a/drivers/hv/channel_mgmt.c b/drivers/hv/channel_mgmt.c index ccfa5ceb43c0cf70ac636c63e92b653659916da1..f79346de7f889675e9d20b301c510290bf0940fd 100644 --- a/drivers/hv/channel_mgmt.c +++ b/drivers/hv/channel_mgmt.c @@ -813,11 +813,22 @@ static void vmbus_wait_for_unload(void) if (completion_done(&vmbus_connection.unload_event)) goto completed; - for_each_online_cpu(cpu) { + for_each_present_cpu(cpu) { struct hv_per_cpu_context *hv_cpu = per_cpu_ptr(hv_context.cpu_context, cpu); + /* + * In a CoCo VM the synic_message_page is not allocated + * in hv_synic_alloc(). Instead it is set/cleared in + * hv_synic_enable_regs() and hv_synic_disable_regs() + * such that it is set only when the CPU is online. If + * not all present CPUs are online, the message page + * might be NULL, so skip such CPUs. + */ page_addr = hv_cpu->synic_message_page; + if (!page_addr) + continue; + msg = (struct hv_message *)page_addr + VMBUS_MESSAGE_SINT; @@ -851,11 +862,14 @@ static void vmbus_wait_for_unload(void) * maybe-pending messages on all CPUs to be able to receive new * messages after we reconnect. */ - for_each_online_cpu(cpu) { + for_each_present_cpu(cpu) { struct hv_per_cpu_context *hv_cpu = per_cpu_ptr(hv_context.cpu_context, cpu); page_addr = hv_cpu->synic_message_page; + if (!page_addr) + continue; + msg = (struct hv_message *)page_addr + VMBUS_MESSAGE_SINT; msg->header.message_type = HVMSG_NONE; } diff --git a/drivers/hwmon/adt7475.c b/drivers/hwmon/adt7475.c index 0a87c5b5128623de65065452695f29ede095a0a9..2db2665dcd4dc754c61879bf7f13754c64600e6c 100644 --- a/drivers/hwmon/adt7475.c +++ b/drivers/hwmon/adt7475.c @@ -485,10 +485,10 @@ static ssize_t set_temp(struct device *dev, struct device_attribute *attr, val = (temp - val) / 1000; if (sattr->index != 1) { - data->temp[HYSTERSIS][sattr->index] &= 0xF0; + data->temp[HYSTERSIS][sattr->index] &= 0x0F; data->temp[HYSTERSIS][sattr->index] |= (val & 0xF) << 4; } else { - data->temp[HYSTERSIS][sattr->index] &= 0x0F; + data->temp[HYSTERSIS][sattr->index] &= 0xF0; data->temp[HYSTERSIS][sattr->index] |= (val & 0xF); } @@ -554,11 +554,11 @@ static ssize_t show_temp_st(struct device *dev, struct device_attribute *attr, val = data->enh_acoustics[0] & 0xf; break; case 1: - val = (data->enh_acoustics[1] >> 4) & 0xf; + val = data->enh_acoustics[1] & 0xf; break; case 2: default: - val = data->enh_acoustics[1] & 0xf; + val = (data->enh_acoustics[1] >> 4) & 0xf; break; } diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 1b2f750577dad79540e590f5f0245740a2a0159d..33371f7a4c0f90418d156775e5867808d0403840 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -54,7 +54,7 @@ MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius"); #define PKG_SYSFS_ATTR_NO 1 /* Sysfs attribute for package temp */ #define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */ #define NUM_REAL_CORES 128 /* Number of Real cores per cpu */ -#define CORETEMP_NAME_LENGTH 19 /* String Length of attrs */ +#define CORETEMP_NAME_LENGTH 28 /* String Length of attrs */ #define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */ #define TOTAL_ATTRS (MAX_CORE_ATTRS + 1) #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO) diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index f8499cb95fec851139c4d680e03e80378ee828aa..4e4e151760db2c9a7bb8d745df8b985a7de20b8d 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -495,6 +495,8 @@ static const struct it87_devices it87_devices[] = { #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2) #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP) #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V) +#define has_scaling(data) ((data)->features & (FEAT_12MV_ADC | \ + FEAT_10_9MV_ADC)) struct it87_sio_data { int sioaddr; @@ -3107,7 +3109,7 @@ static int it87_probe(struct platform_device *pdev) "Detected broken BIOS defaults, disabling PWM interface\n"); /* Starting with IT8721F, we handle scaling of internal voltages */ - if (has_12mv_adc(data)) { + if (has_scaling(data)) { if (sio_data->internal & BIT(0)) data->in_scaled |= BIT(3); /* in3 is AVCC */ if (sio_data->internal & BIT(1)) diff --git a/drivers/hwmon/ltc2945.c b/drivers/hwmon/ltc2945.c index 1b92e4f6e23492c1c0c1eb83493ead63501a8137..efabe514ec56001cdc0c7a2b1a75a6ae7bfa00cc 100644 --- a/drivers/hwmon/ltc2945.c +++ b/drivers/hwmon/ltc2945.c @@ -257,6 +257,8 @@ static ssize_t ltc2945_set_value(struct device *dev, /* convert to register value, then clamp and write result */ regval = ltc2945_val_to_reg(dev, reg, val); + if (regval < 0) + return regval; if (is_power_reg(reg)) { regval = clamp_val(regval, 0, 0xffffff); regbuf[0] = regval >> 16; diff --git a/drivers/hwmon/mlxreg-fan.c b/drivers/hwmon/mlxreg-fan.c index e57b0c5119ce440320d3389dde1f0ad867e971ee..ec68dace3cf93c340db27a970edec7428d87d0be 100644 --- a/drivers/hwmon/mlxreg-fan.c +++ b/drivers/hwmon/mlxreg-fan.c @@ -125,6 +125,12 @@ mlxreg_fan_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, if (err) return err; + if (MLXREG_FAN_GET_FAULT(regval, tacho->mask)) { + /* FAN is broken - return zero for FAN speed. */ + *val = 0; + return 0; + } + *val = MLXREG_FAN_GET_RPM(regval, fan->divider, fan->samples); break; diff --git a/drivers/hwmon/nct7802.c b/drivers/hwmon/nct7802.c index 779ec8fdfae082b640046bc36f4b2eb416e3b128..56dd2d6ba9e49f00c938fca911c0dcb0470d5ef3 100644 --- a/drivers/hwmon/nct7802.c +++ b/drivers/hwmon/nct7802.c @@ -698,7 +698,7 @@ static umode_t nct7802_temp_is_visible(struct kobject *kobj, if (index >= 38 && index < 46 && !(reg & 0x01)) /* PECI 0 */ return 0; - if (index >= 0x46 && (!(reg & 0x02))) /* PECI 1 */ + if (index >= 46 && !(reg & 0x02)) /* PECI 1 */ return 0; return attr->mode; diff --git a/drivers/hwmon/scmi-hwmon.c b/drivers/hwmon/scmi-hwmon.c index 91bfecdb3f5ba62b730dd4b62a0e00683ac6c62f..84880c0ff7ab857f48e6e0f336e9e62fc7ab40e8 100644 --- a/drivers/hwmon/scmi-hwmon.c +++ b/drivers/hwmon/scmi-hwmon.c @@ -56,7 +56,7 @@ scmi_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type, const struct scmi_sensors *scmi_sensors = drvdata; sensor = *(scmi_sensors->info[type] + channel); - if (sensor && sensor->name) + if (sensor) return S_IRUGO; return 0; diff --git a/drivers/hwmon/xgene-hwmon.c b/drivers/hwmon/xgene-hwmon.c index a3cd91f232679afd21c9ebbd206be377f5394333..2dd19a42030520c1b1835e7e8cac9cee07470158 100644 --- a/drivers/hwmon/xgene-hwmon.c +++ b/drivers/hwmon/xgene-hwmon.c @@ -780,6 +780,7 @@ static int xgene_hwmon_remove(struct platform_device *pdev) { struct xgene_hwmon_dev *ctx = platform_get_drvdata(pdev); + cancel_work_sync(&ctx->workq); hwmon_device_unregister(ctx->hwmon_dev); kfifo_free(&ctx->async_msg_fifo); if (acpi_disabled) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 72d11d75aab2ea448592ad82989992621c38f6ed..e7ff8d0910e8edec0ce4d961cfd9b6886bfad505 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -173,7 +173,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) writel_relaxed(config->ss_pe_cmp[i], drvdata->base + TRCSSPCICRn(i)); } - for (i = 0; i < drvdata->nr_addr_cmp; i++) { + for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { writeq_relaxed(config->addr_val[i], drvdata->base + TRCACVRn(i)); writeq_relaxed(config->addr_acc[i], diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 1ed9ca6efa71b13118c167e1bf47f59befcef7d9..e0405173a2965bc22c499e6e90fd7e48690a79c6 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -926,7 +926,7 @@ tmc_etr_buf_insert_barrier_packet(struct etr_buf *etr_buf, u64 offset) len = tmc_etr_buf_get_data(etr_buf, offset, CORESIGHT_BARRIER_PKT_SIZE, &bufp); - if (WARN_ON(len < CORESIGHT_BARRIER_PKT_SIZE)) + if (WARN_ON(len < 0 || len < CORESIGHT_BARRIER_PKT_SIZE)) return -EINVAL; coresight_insert_barrier_packet(bufp); return offset + CORESIGHT_BARRIER_PKT_SIZE; diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c index fb0ddaad87d2e8854f14af0c24f6fad98fc2bcb5..c18b899e510ec7f1fa930d1d889a2a4b5a05e04c 100644 --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c @@ -712,15 +712,11 @@ static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, return i801_check_post(priv, status); } - for (i = 1; i <= len; i++) { - if (i == len && read_write == I2C_SMBUS_READ) - smbcmd |= SMBHSTCNT_LAST_BYTE; - outb_p(smbcmd, SMBHSTCNT(priv)); - - if (i == 1) - outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, - SMBHSTCNT(priv)); + if (len == 1 && read_write == I2C_SMBUS_READ) + smbcmd |= SMBHSTCNT_LAST_BYTE; + outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv)); + for (i = 1; i <= len; i++) { status = i801_wait_byte_done(priv); if (status) goto exit; @@ -743,9 +739,12 @@ static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, data->block[0] = len; } - /* Retrieve/store value in SMBBLKDAT */ - if (read_write == I2C_SMBUS_READ) + if (read_write == I2C_SMBUS_READ) { data->block[i] = inb_p(SMBBLKDAT(priv)); + if (i == len - 1) + outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv)); + } + if (read_write == I2C_SMBUS_WRITE && i+1 <= len) outb_p(data->block[i+1], SMBBLKDAT(priv)); @@ -1679,6 +1678,7 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) "SMBus I801 adapter at %04lx", priv->smba); err = i2c_add_adapter(&priv->adapter); if (err) { + platform_device_unregister(priv->tco_pdev); i801_acpi_remove(priv); return err; } diff --git a/drivers/i2c/busses/i2c-imx-lpi2c.c b/drivers/i2c/busses/i2c-imx-lpi2c.c index 06c4c767af322aa2704d5ae51a59e5c103579fc5..a4f90796032b319097d9a75515c4247f4d045e24 100644 --- a/drivers/i2c/busses/i2c-imx-lpi2c.c +++ b/drivers/i2c/busses/i2c-imx-lpi2c.c @@ -206,8 +206,8 @@ static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx) /* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */ static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx) { - u8 prescale, filt, sethold, clkhi, clklo, datavd; - unsigned int clk_rate, clk_cycle; + u8 prescale, filt, sethold, datavd; + unsigned int clk_rate, clk_cycle, clkhi, clklo; enum lpi2c_imx_pincfg pincfg; unsigned int temp; @@ -468,6 +468,8 @@ static int lpi2c_imx_xfer(struct i2c_adapter *adapter, if (num == 1 && msgs[0].len == 0) goto stop; + lpi2c_imx->rx_buf = NULL; + lpi2c_imx->tx_buf = NULL; lpi2c_imx->delivered = 0; lpi2c_imx->msglen = msgs[i].len; init_completion(&lpi2c_imx->complete); @@ -508,10 +510,14 @@ static int lpi2c_imx_xfer(struct i2c_adapter *adapter, static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id) { struct lpi2c_imx_struct *lpi2c_imx = dev_id; + unsigned int enabled; unsigned int temp; + enabled = readl(lpi2c_imx->base + LPI2C_MIER); + lpi2c_imx_intctrl(lpi2c_imx, 0); temp = readl(lpi2c_imx->base + LPI2C_MSR); + temp &= enabled; if (temp & MSR_RDF) lpi2c_imx_read_rxfifo(lpi2c_imx); diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index cd9c65f3d404ff92f0eef87d4d99236b370e82cc..11321ad482a3a4396e0161d6773d74f3e22fbb4b 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -1027,7 +1027,7 @@ omap_i2c_isr(int irq, void *dev_id) u16 stat; stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); - mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); + mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG) & ~OMAP_I2C_STAT_NACK; if (stat & mask) ret = IRQ_WAKE_THREAD; diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c index 61ab462fd94cf4c24302ea93d5b79622a2c261a3..fe7642b916cfc774025e2660f0ebcb2bc8605f04 100644 --- a/drivers/i2c/busses/i2c-rk3x.c +++ b/drivers/i2c/busses/i2c-rk3x.c @@ -421,7 +421,7 @@ static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd) { unsigned int i; unsigned int len = i2c->msg->len - i2c->processed; - u32 uninitialized_var(val); + u32 val; u8 byte; /* we only care for MBRF here. */ diff --git a/drivers/i2c/busses/i2c-sprd.c b/drivers/i2c/busses/i2c-sprd.c index bb1478e781c42ecc1c87dcb3a8bb337b33137712..6c95b809abdc4e36b1b67fea569b65c418670d98 100644 --- a/drivers/i2c/busses/i2c-sprd.c +++ b/drivers/i2c/busses/i2c-sprd.c @@ -581,10 +581,12 @@ static int sprd_i2c_remove(struct platform_device *pdev) ret = pm_runtime_get_sync(i2c_dev->dev); if (ret < 0) - return ret; + dev_err(&pdev->dev, "Failed to resume device (%pe)\n", ERR_PTR(ret)); i2c_del_adapter(&i2c_dev->adap); - clk_disable_unprepare(i2c_dev->clk); + + if (ret >= 0) + clk_disable_unprepare(i2c_dev->clk); pm_runtime_put_noidle(i2c_dev->dev); pm_runtime_disable(i2c_dev->dev); diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c index e352c16087bb3c5388f616b31e519b82c3c91b6a..cbffe303fbc32c98590c28ea3aebc2b936a5aedf 100644 --- a/drivers/i2c/busses/i2c-stm32f7.c +++ b/drivers/i2c/busses/i2c-stm32f7.c @@ -959,9 +959,10 @@ static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, /* Configure PEC */ if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { cr1 |= STM32F7_I2C_CR1_PECEN; - cr2 |= STM32F7_I2C_CR2_PECBYTE; - if (!f7_msg->read_write) + if (!f7_msg->read_write) { + cr2 |= STM32F7_I2C_CR2_PECBYTE; f7_msg->count++; + } } else { cr1 &= ~STM32F7_I2C_CR1_PECEN; cr2 &= ~STM32F7_I2C_CR2_PECBYTE; @@ -1049,8 +1050,10 @@ static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev) f7_msg->stop = true; /* Add one byte for PEC if needed */ - if (cr1 & STM32F7_I2C_CR1_PECEN) + if (cr1 & STM32F7_I2C_CR1_PECEN) { + cr2 |= STM32F7_I2C_CR2_PECBYTE; f7_msg->count++; + } /* Set number of bytes to be transferred */ cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK); diff --git a/drivers/i2c/busses/i2c-sun6i-p2wi.c b/drivers/i2c/busses/i2c-sun6i-p2wi.c index 7c07ce116e38458b00cd93be490cc378f4131f7c..540c33f4e35001a11288e27d68f6910bcdab9e23 100644 --- a/drivers/i2c/busses/i2c-sun6i-p2wi.c +++ b/drivers/i2c/busses/i2c-sun6i-p2wi.c @@ -202,6 +202,11 @@ static int p2wi_probe(struct platform_device *pdev) return -EINVAL; } + if (clk_freq == 0) { + dev_err(dev, "clock-frequency is set to 0 in DT\n"); + return -EINVAL; + } + if (of_get_child_count(np) > 1) { dev_err(dev, "P2WI only supports one slave device\n"); return -EINVAL; diff --git a/drivers/i2c/busses/i2c-xgene-slimpro.c b/drivers/i2c/busses/i2c-xgene-slimpro.c index a7ac746018ad0c098d51eb56c1d5d8981d34c78c..7a746f41353514a7586626c913d77510452de35e 100644 --- a/drivers/i2c/busses/i2c-xgene-slimpro.c +++ b/drivers/i2c/busses/i2c-xgene-slimpro.c @@ -321,6 +321,9 @@ static int slimpro_i2c_blkwr(struct slimpro_i2c_dev *ctx, u32 chip, u32 msg[3]; int rc; + if (writelen > I2C_SMBUS_BLOCK_MAX) + return -EINVAL; + memcpy(ctx->dma_buffer, data, writelen); paddr = dma_map_single(ctx->dev, ctx->dma_buffer, writelen, DMA_TO_DEVICE); diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 03ce9b7d6456ad7dc444bdd7084507dc66c5fc42..c1f85114ab812d7d5af881a76621cfb204427667 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -362,6 +362,9 @@ static irqreturn_t xiic_process(int irq, void *dev_id) struct xiic_i2c *i2c = dev_id; u32 pend, isr, ier; u32 clr = 0; + int xfer_more = 0; + int wakeup_req = 0; + int wakeup_code = 0; /* Get the interrupt Status from the IPIF. There is no clearing of * interrupts in the IPIF. Interrupts must be cleared at the source. @@ -398,10 +401,16 @@ static irqreturn_t xiic_process(int irq, void *dev_id) */ xiic_reinit(i2c); - if (i2c->rx_msg) - xiic_wakeup(i2c, STATE_ERROR); - if (i2c->tx_msg) - xiic_wakeup(i2c, STATE_ERROR); + if (i2c->rx_msg) { + wakeup_req = 1; + wakeup_code = STATE_ERROR; + } + if (i2c->tx_msg) { + wakeup_req = 1; + wakeup_code = STATE_ERROR; + } + /* don't try to handle other events */ + goto out; } if (pend & XIIC_INTR_RX_FULL_MASK) { /* Receive register/FIFO is full */ @@ -435,8 +444,7 @@ static irqreturn_t xiic_process(int irq, void *dev_id) i2c->tx_msg++; dev_dbg(i2c->adap.dev.parent, "%s will start next...\n", __func__); - - __xiic_start_xfer(i2c); + xfer_more = 1; } } } @@ -450,11 +458,13 @@ static irqreturn_t xiic_process(int irq, void *dev_id) if (!i2c->tx_msg) goto out; - if ((i2c->nmsgs == 1) && !i2c->rx_msg && - xiic_tx_space(i2c) == 0) - xiic_wakeup(i2c, STATE_DONE); + wakeup_req = 1; + + if (i2c->nmsgs == 1 && !i2c->rx_msg && + xiic_tx_space(i2c) == 0) + wakeup_code = STATE_DONE; else - xiic_wakeup(i2c, STATE_ERROR); + wakeup_code = STATE_ERROR; } if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { /* Transmit register/FIFO is empty or ½ empty */ @@ -478,7 +488,7 @@ static irqreturn_t xiic_process(int irq, void *dev_id) if (i2c->nmsgs > 1) { i2c->nmsgs--; i2c->tx_msg++; - __xiic_start_xfer(i2c); + xfer_more = 1; } else { xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); @@ -496,6 +506,13 @@ static irqreturn_t xiic_process(int irq, void *dev_id) dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); + if (xfer_more) + __xiic_start_xfer(i2c); + if (wakeup_req) + xiic_wakeup(i2c, wakeup_code); + + WARN_ON(xfer_more && wakeup_req); + mutex_unlock(&i2c->lock); return IRQ_HANDLED; } diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c index f330690b41253ff75e352b321575cc008fcf0353..83a79bcb71ea5aa60e2fc845f7eedff19050072d 100644 --- a/drivers/i2c/i2c-mux.c +++ b/drivers/i2c/i2c-mux.c @@ -334,7 +334,7 @@ int i2c_mux_add_adapter(struct i2c_mux_core *muxc, priv->adap.lock_ops = &i2c_parent_lock_ops; /* Sanity check on class */ - if (i2c_mux_parent_classes(parent) & class) + if (i2c_mux_parent_classes(parent) & class & ~I2C_CLASS_DEPRECATED) dev_err(&parent->dev, "Segment %d behind mux can't share classes with ancestors\n", chan_id); diff --git a/drivers/i2c/muxes/i2c-demux-pinctrl.c b/drivers/i2c/muxes/i2c-demux-pinctrl.c index 1b99d0b928a0dcca16eeb7243694e0633d30f2d4..b62b93ecacefd2ce08fda5b5707c973d399610f3 100644 --- a/drivers/i2c/muxes/i2c-demux-pinctrl.c +++ b/drivers/i2c/muxes/i2c-demux-pinctrl.c @@ -64,7 +64,7 @@ static int i2c_demux_activate_master(struct i2c_demux_pinctrl_priv *priv, u32 ne if (ret) goto err; - adap = of_find_i2c_adapter_by_node(priv->chan[new_chan].parent_np); + adap = of_get_i2c_adapter_by_node(priv->chan[new_chan].parent_np); if (!adap) { ret = -ENODEV; goto err_with_revert; @@ -244,6 +244,10 @@ static int i2c_demux_pinctrl_probe(struct platform_device *pdev) props[i].name = devm_kstrdup(&pdev->dev, "status", GFP_KERNEL); props[i].value = devm_kstrdup(&pdev->dev, "ok", GFP_KERNEL); + if (!props[i].name || !props[i].value) { + err = -ENOMEM; + goto err_rollback; + } props[i].length = 3; of_changeset_init(&priv->chan[i].chgset); diff --git a/drivers/i2c/muxes/i2c-mux-gpmux.c b/drivers/i2c/muxes/i2c-mux-gpmux.c index 5053f1675a294ecaeed7aff55fc2c3d6e14d7a87..04133c973c15f64f0a144225e79e7a50b4595ccb 100644 --- a/drivers/i2c/muxes/i2c-mux-gpmux.c +++ b/drivers/i2c/muxes/i2c-mux-gpmux.c @@ -55,7 +55,7 @@ static struct i2c_adapter *mux_parent_adapter(struct device *dev) dev_err(dev, "Cannot parse i2c-parent\n"); return ERR_PTR(-ENODEV); } - parent = of_find_i2c_adapter_by_node(parent_np); + parent = of_get_i2c_adapter_by_node(parent_np); of_node_put(parent_np); if (!parent) return ERR_PTR(-EPROBE_DEFER); diff --git a/drivers/i2c/muxes/i2c-mux-pinctrl.c b/drivers/i2c/muxes/i2c-mux-pinctrl.c index cc6818aabab515ba2b68badc030c2b6417cc6b94..821e5cd497579d98731a5033180f5a6fd2288de7 100644 --- a/drivers/i2c/muxes/i2c-mux-pinctrl.c +++ b/drivers/i2c/muxes/i2c-mux-pinctrl.c @@ -73,7 +73,7 @@ static struct i2c_adapter *i2c_mux_pinctrl_parent_adapter(struct device *dev) dev_err(dev, "Cannot parse i2c-parent\n"); return ERR_PTR(-ENODEV); } - parent = of_find_i2c_adapter_by_node(parent_np); + parent = of_get_i2c_adapter_by_node(parent_np); of_node_put(parent_np); if (!parent) return ERR_PTR(-EPROBE_DEFER); diff --git a/drivers/ide/ide-acpi.c b/drivers/ide/ide-acpi.c index 7d4e5c08f133ef74b101b86184a22deb6340ebe5..05e18d65814164c637f1cf39caeca648831f312a 100644 --- a/drivers/ide/ide-acpi.c +++ b/drivers/ide/ide-acpi.c @@ -180,7 +180,7 @@ static int ide_get_dev_handle(struct device *dev, acpi_handle *handle, static acpi_handle ide_acpi_hwif_get_handle(ide_hwif_t *hwif) { struct device *dev = hwif->gendev.parent; - acpi_handle uninitialized_var(dev_handle); + acpi_handle dev_handle; u64 pcidevfn; acpi_handle chan_handle; int err; diff --git a/drivers/ide/ide-atapi.c b/drivers/ide/ide-atapi.c index 4224c4dd8963507ccc6f16c97b66774ac6471b91..9a4c094c897c35252c2b6d9ce1b0a0e1e9c43983 100644 --- a/drivers/ide/ide-atapi.c +++ b/drivers/ide/ide-atapi.c @@ -591,7 +591,7 @@ static int ide_delayed_transfer_pc(ide_drive_t *drive) static ide_startstop_t ide_transfer_pc(ide_drive_t *drive) { - struct ide_atapi_pc *uninitialized_var(pc); + struct ide_atapi_pc *pc; ide_hwif_t *hwif = drive->hwif; struct request *rq = hwif->rq; ide_expiry_t *expiry; diff --git a/drivers/ide/ide-io-std.c b/drivers/ide/ide-io-std.c index 19763977568c5d6fd7ecc87c3f4e7bc47fc0d85e..508f98ca3fe872a51b7eb18c7a04723aa7e196ac 100644 --- a/drivers/ide/ide-io-std.c +++ b/drivers/ide/ide-io-std.c @@ -172,7 +172,7 @@ void ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd, void *buf, u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; if (io_32bit) { - unsigned long uninitialized_var(flags); + unsigned long flags; if ((io_32bit & 2) && !mmio) { local_irq_save(flags); @@ -216,7 +216,7 @@ void ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd, void *buf, u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; if (io_32bit) { - unsigned long uninitialized_var(flags); + unsigned long flags; if ((io_32bit & 2) && !mmio) { local_irq_save(flags); diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c index 43817608461090af74981e79f1aef8604f1f086a..a01cc012444223d392e885e33e48c19911a52570 100644 --- a/drivers/ide/ide-io.c +++ b/drivers/ide/ide-io.c @@ -605,12 +605,12 @@ static int drive_is_ready(ide_drive_t *drive) void ide_timer_expiry (struct timer_list *t) { ide_hwif_t *hwif = from_timer(hwif, t, timer); - ide_drive_t *uninitialized_var(drive); + ide_drive_t *drive; ide_handler_t *handler; unsigned long flags; int wait = -1; int plug_device = 0; - struct request *uninitialized_var(rq_in_flight); + struct request *rq_in_flight; spin_lock_irqsave(&hwif->lock, flags); @@ -763,13 +763,13 @@ irqreturn_t ide_intr (int irq, void *dev_id) { ide_hwif_t *hwif = (ide_hwif_t *)dev_id; struct ide_host *host = hwif->host; - ide_drive_t *uninitialized_var(drive); + ide_drive_t *drive; ide_handler_t *handler; unsigned long flags; ide_startstop_t startstop; irqreturn_t irq_ret = IRQ_NONE; int plug_device = 0; - struct request *uninitialized_var(rq_in_flight); + struct request *rq_in_flight; if (host->host_flags & IDE_HFLAG_SERIALIZE) { if (hwif != host->cur_port) diff --git a/drivers/ide/ide-sysfs.c b/drivers/ide/ide-sysfs.c index b9dfeb2e8bd6603c20dc9e02554adc0eff6ed72c..c08a8a0916e220853bfcfcc10c31e1e88d4bcda0 100644 --- a/drivers/ide/ide-sysfs.c +++ b/drivers/ide/ide-sysfs.c @@ -131,7 +131,7 @@ static struct device_attribute *ide_port_attrs[] = { int ide_sysfs_register_port(ide_hwif_t *hwif) { - int i, uninitialized_var(rc); + int i, rc; for (i = 0; ide_port_attrs[i]; i++) { rc = device_create_file(hwif->portdev, ide_port_attrs[i]); diff --git a/drivers/ide/umc8672.c b/drivers/ide/umc8672.c index 3aa0fea0f3d9c779048f1c07ab9422646eb8068d..1414caa97b401e9ccc6edac2cd38855eaf244207 100644 --- a/drivers/ide/umc8672.c +++ b/drivers/ide/umc8672.c @@ -107,7 +107,7 @@ static void umc_set_speeds(u8 speeds[]) static void umc_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { ide_hwif_t *mate = hwif->mate; - unsigned long uninitialized_var(flags); + unsigned long flags; const u8 pio = drive->pio_mode - XFER_PIO_0; printk("%s: setting umc8672 to PIO mode%d (speed %d)\n", diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig index 1dec0fecb6efa940175074fd04223b48fa6be1f5..959b2b69e5c0a10d5a50de18e987a94b525082b5 100644 --- a/drivers/iio/Kconfig +++ b/drivers/iio/Kconfig @@ -69,6 +69,7 @@ config IIO_TRIGGERED_EVENT source "drivers/iio/accel/Kconfig" source "drivers/iio/adc/Kconfig" +source "drivers/iio/addac/Kconfig" source "drivers/iio/afe/Kconfig" source "drivers/iio/amplifiers/Kconfig" source "drivers/iio/chemical/Kconfig" diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile index cb5993251381ea804a0fb7869da3c08b4832b1bd..a60d0cbfe4cd2be0e145619a3806367f1675d1d3 100644 --- a/drivers/iio/Makefile +++ b/drivers/iio/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_IIO_TRIGGERED_EVENT) += industrialio-triggered-event.o obj-y += accel/ obj-y += adc/ +obj-y += addac/ obj-y += afe/ obj-y += amplifiers/ obj-y += buffer/ diff --git a/drivers/iio/accel/mma9551_core.c b/drivers/iio/accel/mma9551_core.c index c34c5ce8123b0938f14c255a21c636dc09e4c513..19b4fbc682e63faeb200dbce1003c5ddd3b695d7 100644 --- a/drivers/iio/accel/mma9551_core.c +++ b/drivers/iio/accel/mma9551_core.c @@ -304,9 +304,12 @@ int mma9551_read_config_word(struct i2c_client *client, u8 app_id, ret = mma9551_transfer(client, app_id, MMA9551_CMD_READ_CONFIG, reg, NULL, 0, (u8 *)&v, 2); + if (ret < 0) + return ret; + *val = be16_to_cpu(v); - return ret; + return 0; } EXPORT_SYMBOL(mma9551_read_config_word); @@ -362,9 +365,12 @@ int mma9551_read_status_word(struct i2c_client *client, u8 app_id, ret = mma9551_transfer(client, app_id, MMA9551_CMD_READ_STATUS, reg, NULL, 0, (u8 *)&v, 2); + if (ret < 0) + return ret; + *val = be16_to_cpu(v); - return ret; + return 0; } EXPORT_SYMBOL(mma9551_read_status_word); diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index b355899f54cc9b2031a63fddf2ef4dae6166f783..41afb9b8696d25f856346085329c3ada563f5045 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -989,7 +989,7 @@ static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio, trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name, indio->id, trigger_name); if (!trig) - return NULL; + return ERR_PTR(-ENOMEM); trig->dev.parent = indio->dev.parent; iio_trigger_set_drvdata(trig, indio); diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c index 1ca2c4d39f87851dac86f3bf4724c3c2d7be9510..7c5ea4ed5332f9d70e876c4bf237d4be113f39f0 100644 --- a/drivers/iio/adc/exynos_adc.c +++ b/drivers/iio/adc/exynos_adc.c @@ -817,6 +817,12 @@ static int exynos_adc_probe(struct platform_device *pdev) } } + /* leave out any TS related code if unreachable */ + if (IS_REACHABLE(CONFIG_INPUT)) { + has_ts = of_property_read_bool(pdev->dev.of_node, + "has-touchscreen") || pdata; + } + irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "no irq resource?\n"); @@ -824,11 +830,15 @@ static int exynos_adc_probe(struct platform_device *pdev) } info->irq = irq; - irq = platform_get_irq(pdev, 1); - if (irq == -EPROBE_DEFER) - return irq; + if (has_ts) { + irq = platform_get_irq(pdev, 1); + if (irq == -EPROBE_DEFER) + return irq; - info->tsirq = irq; + info->tsirq = irq; + } else { + info->tsirq = -1; + } info->dev = &pdev->dev; @@ -895,12 +905,6 @@ static int exynos_adc_probe(struct platform_device *pdev) if (info->data->init_hw) info->data->init_hw(info); - /* leave out any TS related code if unreachable */ - if (IS_REACHABLE(CONFIG_INPUT)) { - has_ts = of_property_read_bool(pdev->dev.of_node, - "has-touchscreen") || pdata; - } - if (pdata) info->delay = pdata->delay; else diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 6e0ef9bb2497f93c42ee6107a23533908ed10f74..c4487693575019f1e27f88d57d7b73a58ba04131 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -75,7 +75,7 @@ #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18) #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16) #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10 - #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5 + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8) #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0) diff --git a/drivers/iio/adc/mxs-lradc-adc.c b/drivers/iio/adc/mxs-lradc-adc.c index fc8b70d8d64c9d798b640bd480d249155ee255d7..10df0b26913a8a742634176f33818a803f5526b9 100644 --- a/drivers/iio/adc/mxs-lradc-adc.c +++ b/drivers/iio/adc/mxs-lradc-adc.c @@ -767,13 +767,13 @@ static int mxs_lradc_adc_probe(struct platform_device *pdev) ret = mxs_lradc_adc_trigger_init(iio); if (ret) - goto err_trig; + return ret; ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time, &mxs_lradc_adc_trigger_handler, &mxs_lradc_adc_buffer_ops); if (ret) - return ret; + goto err_trig; adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc]; @@ -811,9 +811,9 @@ static int mxs_lradc_adc_probe(struct platform_device *pdev) err_dev: mxs_lradc_adc_hw_stop(adc); - mxs_lradc_adc_trigger_remove(iio); -err_trig: iio_triggered_buffer_cleanup(iio); +err_trig: + mxs_lradc_adc_trigger_remove(iio); return ret; } @@ -824,8 +824,8 @@ static int mxs_lradc_adc_remove(struct platform_device *pdev) iio_device_unregister(iio); mxs_lradc_adc_hw_stop(adc); - mxs_lradc_adc_trigger_remove(iio); iio_triggered_buffer_cleanup(iio); + mxs_lradc_adc_trigger_remove(iio); return 0; } diff --git a/drivers/iio/adc/palmas_gpadc.c b/drivers/iio/adc/palmas_gpadc.c index 7dcd4213d38a00f421cd14e659a36dbf3d6e3243..6b76622b4fbfa1390bcde8fa9a00af8fc94891bc 100644 --- a/drivers/iio/adc/palmas_gpadc.c +++ b/drivers/iio/adc/palmas_gpadc.c @@ -633,7 +633,7 @@ static int palmas_gpadc_probe(struct platform_device *pdev) static int palmas_gpadc_remove(struct platform_device *pdev) { - struct iio_dev *indio_dev = dev_to_iio_dev(&pdev->dev); + struct iio_dev *indio_dev = dev_get_drvdata(&pdev->dev); struct palmas_gpadc *adc = iio_priv(indio_dev); if (adc->wakeup1_enable || adc->wakeup2_enable) diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c index 0662ca199eb0be1883a193f28d6c165fb5880f98..49aeb76212fd0801c363b54b83af930179a36928 100644 --- a/drivers/iio/adc/stx104.c +++ b/drivers/iio/adc/stx104.c @@ -23,7 +23,9 @@ #include #include #include +#include #include +#include #define STX104_OUT_CHAN(chan) { \ .type = IIO_VOLTAGE, \ @@ -52,14 +54,38 @@ static unsigned int num_stx104; module_param_hw_array(base, uint, ioport, &num_stx104, 0); MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses"); +/** + * struct stx104_reg - device register structure + * @ssr_ad: Software Strobe Register and ADC Data + * @achan: ADC Channel + * @dio: Digital I/O + * @dac: DAC Channels + * @cir_asr: Clear Interrupts and ADC Status + * @acr: ADC Control + * @pccr_fsh: Pacer Clock Control and FIFO Status MSB + * @acfg: ADC Configuration + */ +struct stx104_reg { + u16 ssr_ad; + u8 achan; + u8 dio; + u16 dac[2]; + u8 cir_asr; + u8 acr; + u8 pccr_fsh; + u8 acfg; +}; + /** * struct stx104_iio - IIO device private data structure + * @lock: synchronization lock to prevent I/O race conditions * @chan_out_states: channels' output states - * @base: base port address of the IIO device + * @reg: I/O address offset for the device registers */ struct stx104_iio { + struct mutex lock; unsigned int chan_out_states[STX104_NUM_OUT_CHAN]; - unsigned int base; + struct stx104_reg __iomem *reg; }; /** @@ -72,7 +98,7 @@ struct stx104_iio { struct stx104_gpio { struct gpio_chip chip; spinlock_t lock; - unsigned int base; + u8 __iomem *base; unsigned int out_state; }; @@ -80,6 +106,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { struct stx104_iio *const priv = iio_priv(indio_dev); + struct stx104_reg __iomem *const reg = priv->reg; unsigned int adc_config; int adbu; int gain; @@ -87,7 +114,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_HARDWAREGAIN: /* get gain configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(®->acfg); gain = adc_config & 0x3; *val = 1 << gain; @@ -98,25 +125,31 @@ static int stx104_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; } + mutex_lock(&priv->lock); + /* select ADC channel */ - outb(chan->channel | (chan->channel << 4), priv->base + 2); + iowrite8(chan->channel | (chan->channel << 4), ®->achan); + + /* trigger ADC sample capture by writing to the 8-bit + * Software Strobe Register and wait for completion + */ + iowrite8(0, ®->ssr_ad); + while (ioread8(®->cir_asr) & BIT(7)); - /* trigger ADC sample capture and wait for completion */ - outb(0, priv->base); - while (inb(priv->base + 8) & BIT(7)); + *val = ioread16(®->ssr_ad); - *val = inw(priv->base); + mutex_unlock(&priv->lock); return IIO_VAL_INT; case IIO_CHAN_INFO_OFFSET: /* get ADC bipolar/unipolar configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(®->acfg); adbu = !(adc_config & BIT(2)); *val = -32768 * adbu; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: /* get ADC bipolar/unipolar and gain configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(®->acfg); adbu = !(adc_config & BIT(2)); gain = adc_config & 0x3; @@ -138,16 +171,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev, /* Only four gain states (x1, x2, x4, x8) */ switch (val) { case 1: - outb(0, priv->base + 11); + iowrite8(0, &priv->reg->acfg); break; case 2: - outb(1, priv->base + 11); + iowrite8(1, &priv->reg->acfg); break; case 4: - outb(2, priv->base + 11); + iowrite8(2, &priv->reg->acfg); break; case 8: - outb(3, priv->base + 11); + iowrite8(3, &priv->reg->acfg); break; default: return -EINVAL; @@ -160,9 +193,12 @@ static int stx104_write_raw(struct iio_dev *indio_dev, if ((unsigned int)val > 65535) return -EINVAL; + mutex_lock(&priv->lock); + priv->chan_out_states[chan->channel] = val; - outw(val, priv->base + 4 + 2 * chan->channel); + iowrite16(val, &priv->reg->dac[chan->channel]); + mutex_unlock(&priv->lock); return 0; } return -EINVAL; @@ -230,7 +266,7 @@ static int stx104_gpio_get(struct gpio_chip *chip, unsigned int offset) if (offset >= 4) return -EINVAL; - return !!(inb(stx104gpio->base) & BIT(offset)); + return !!(ioread8(stx104gpio->base) & BIT(offset)); } static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, @@ -238,7 +274,7 @@ static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, { struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip); - *bits = inb(stx104gpio->base); + *bits = ioread8(stx104gpio->base); return 0; } @@ -260,7 +296,7 @@ static void stx104_gpio_set(struct gpio_chip *chip, unsigned int offset, else stx104gpio->out_state &= ~mask; - outb(stx104gpio->out_state, stx104gpio->base); + iowrite8(stx104gpio->out_state, stx104gpio->base); spin_unlock_irqrestore(&stx104gpio->lock, flags); } @@ -287,7 +323,7 @@ static void stx104_gpio_set_multiple(struct gpio_chip *chip, stx104gpio->out_state &= ~*mask; stx104gpio->out_state |= *mask & *bits; - outb(stx104gpio->out_state, stx104gpio->base); + iowrite8(stx104gpio->out_state, stx104gpio->base); spin_unlock_irqrestore(&stx104gpio->lock, flags); } @@ -314,11 +350,16 @@ static int stx104_probe(struct device *dev, unsigned int id) return -EBUSY; } + priv = iio_priv(indio_dev); + priv->reg = devm_ioport_map(dev, base[id], STX104_EXTENT); + if (!priv->reg) + return -ENOMEM; + indio_dev->info = &stx104_info; indio_dev->modes = INDIO_DIRECT_MODE; /* determine if differential inputs */ - if (inb(base[id] + 8) & BIT(5)) { + if (ioread8(&priv->reg->cir_asr) & BIT(5)) { indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff); indio_dev->channels = stx104_channels_diff; } else { @@ -329,18 +370,17 @@ static int stx104_probe(struct device *dev, unsigned int id) indio_dev->name = dev_name(dev); indio_dev->dev.parent = dev; - priv = iio_priv(indio_dev); - priv->base = base[id]; + mutex_init(&priv->lock); /* configure device for software trigger operation */ - outb(0, base[id] + 9); + iowrite8(0, &priv->reg->acr); /* initialize gain setting to x1 */ - outb(0, base[id] + 11); + iowrite8(0, &priv->reg->acfg); /* initialize DAC output to 0V */ - outw(0, base[id] + 4); - outw(0, base[id] + 6); + iowrite16(0, &priv->reg->dac[0]); + iowrite16(0, &priv->reg->dac[1]); stx104gpio->chip.label = dev_name(dev); stx104gpio->chip.parent = dev; @@ -355,7 +395,7 @@ static int stx104_probe(struct device *dev, unsigned int id) stx104gpio->chip.get_multiple = stx104_gpio_get_multiple; stx104gpio->chip.set = stx104_gpio_set; stx104gpio->chip.set_multiple = stx104_gpio_set_multiple; - stx104gpio->base = base[id] + 3; + stx104gpio->base = &priv->reg->dio; stx104gpio->out_state = 0x0; spin_lock_init(&stx104gpio->lock); diff --git a/drivers/iio/addac/Kconfig b/drivers/iio/addac/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..2e64d7755d5ea3b99305226b692bdbb7cfb3450a --- /dev/null +++ b/drivers/iio/addac/Kconfig @@ -0,0 +1,8 @@ +# +# ADC DAC drivers +# +# When adding new entries keep the list in alphabetical order + +menu "Analog to digital and digital to analog converters" + +endmenu diff --git a/drivers/iio/addac/Makefile b/drivers/iio/addac/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..b888b9ee12da0c03fe1026f2ba1609b32f0f19b7 --- /dev/null +++ b/drivers/iio/addac/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for industrial I/O ADDAC drivers +# + +# When adding new entries keep the list in alphabetical order diff --git a/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c b/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c index 414cc43c287ebd6bf2974f2ae1bdec0cacbe17f6..66991fd4b10a0be0ee9a68e31cd9c04f38a92d31 100644 --- a/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c +++ b/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c @@ -46,7 +46,7 @@ int cros_ec_sensors_core_init(struct platform_device *pdev, platform_set_drvdata(pdev, indio_dev); state->ec = ec->ec_dev; - state->msg = devm_kzalloc(&pdev->dev, + state->msg = devm_kzalloc(&pdev->dev, sizeof(*state->msg) + max((u16)sizeof(struct ec_params_motion_sense), state->ec->max_response), GFP_KERNEL); if (!state->msg) diff --git a/drivers/iio/counter/104-quad-8.c b/drivers/iio/counter/104-quad-8.c index 92be8d0f7735fa0f7c3496b0550de4f9e721d791..92e68cada844c1ad6452c23ef79938d7e0175d1c 100644 --- a/drivers/iio/counter/104-quad-8.c +++ b/drivers/iio/counter/104-quad-8.c @@ -61,10 +61,6 @@ struct quad8_iio { #define QUAD8_REG_CHAN_OP 0x11 #define QUAD8_REG_INDEX_INPUT_LEVELS 0x16 -/* Borrow Toggle flip-flop */ -#define QUAD8_FLAG_BT BIT(0) -/* Carry Toggle flip-flop */ -#define QUAD8_FLAG_CT BIT(1) /* Error flag */ #define QUAD8_FLAG_E BIT(4) /* Up/Down flag */ @@ -97,9 +93,6 @@ static int quad8_read_raw(struct iio_dev *indio_dev, { struct quad8_iio *const priv = iio_priv(indio_dev); const int base_offset = priv->base + 2 * chan->channel; - unsigned int flags; - unsigned int borrow; - unsigned int carry; int i; switch (mask) { @@ -110,12 +103,7 @@ static int quad8_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; } - flags = inb(base_offset + 1); - borrow = flags & QUAD8_FLAG_BT; - carry = !!(flags & QUAD8_FLAG_CT); - - /* Borrow XOR Carry effectively doubles count range */ - *val = (borrow ^ carry) << 24; + *val = 0; /* Reset Byte Pointer; transfer Counter to Output Latch */ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile index a1b37cf9944165fcaef0db42d85149aaab88a233..e859f2d97456531afa63748896bf88ebc41f4098 100644 --- a/drivers/iio/dac/Makefile +++ b/drivers/iio/dac/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_AD5592R_BASE) += ad5592r-base.o obj-$(CONFIG_AD5592R) += ad5592r.o obj-$(CONFIG_AD5593R) += ad5593r.o obj-$(CONFIG_AD5755) += ad5755.o -obj-$(CONFIG_AD5755) += ad5758.o +obj-$(CONFIG_AD5758) += ad5758.o obj-$(CONFIG_AD5761) += ad5761.o obj-$(CONFIG_AD5764) += ad5764.o obj-$(CONFIG_AD5791) += ad5791.o diff --git a/drivers/iio/dac/cio-dac.c b/drivers/iio/dac/cio-dac.c index 6898b0c79013aec42019e289a57d1ecb7015c5aa..901350697390404180ff56fc8fb0e16dc916c44a 100644 --- a/drivers/iio/dac/cio-dac.c +++ b/drivers/iio/dac/cio-dac.c @@ -74,8 +74,8 @@ static int cio_dac_write_raw(struct iio_dev *indio_dev, if (mask != IIO_CHAN_INFO_RAW) return -EINVAL; - /* DAC can only accept up to a 16-bit value */ - if ((unsigned int)val > 65535) + /* DAC can only accept up to a 12-bit value */ + if ((unsigned int)val > 4095) return -EINVAL; priv->chan_out_states[chan->channel] = val; diff --git a/drivers/iio/dac/mcp4725.c b/drivers/iio/dac/mcp4725.c index 30dc2775cbfbd5c1d09e98d0e27930deaa1f78b5..f6e2e467638593f15414b4e9bad07f83441dbfde 100644 --- a/drivers/iio/dac/mcp4725.c +++ b/drivers/iio/dac/mcp4725.c @@ -50,12 +50,18 @@ static int mcp4725_suspend(struct device *dev) struct mcp4725_data *data = iio_priv(i2c_get_clientdata( to_i2c_client(dev))); u8 outbuf[2]; + int ret; outbuf[0] = (data->powerdown_mode + 1) << 4; outbuf[1] = 0; data->powerdown = true; - return i2c_master_send(data->client, outbuf, 2); + ret = i2c_master_send(data->client, outbuf, 2); + if (ret < 0) + return ret; + else if (ret != 2) + return -EIO; + return 0; } static int mcp4725_resume(struct device *dev) @@ -63,13 +69,19 @@ static int mcp4725_resume(struct device *dev) struct mcp4725_data *data = iio_priv(i2c_get_clientdata( to_i2c_client(dev))); u8 outbuf[2]; + int ret; /* restore previous DAC value */ outbuf[0] = (data->dac_value >> 8) & 0xf; outbuf[1] = data->dac_value & 0xff; data->powerdown = false; - return i2c_master_send(data->client, outbuf, 2); + ret = i2c_master_send(data->client, outbuf, 2); + if (ret < 0) + return ret; + else if (ret != 2) + return -EIO; + return 0; } #ifdef CONFIG_PM_SLEEP diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 49d4b4f1a4574771f63e6db6e2f2815d6f9a70f2..ad9bd2001fbd275152a1939e4a00934a72d5ca32 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -323,7 +323,7 @@ static ssize_t iio_debugfs_write_reg(struct file *file, char buf[80]; int ret; - count = min_t(size_t, count, (sizeof(buf)-1)); + count = min(count, sizeof(buf) - 1); if (copy_from_user(buf, userbuf, count)) return -EFAULT; diff --git a/drivers/iio/pressure/bmp280-core.c b/drivers/iio/pressure/bmp280-core.c index 074f6f865008c5c096b7f3d8419f03e2098643ce..5efc50d93d1c5158a118560dc41bbf13887d1861 100644 --- a/drivers/iio/pressure/bmp280-core.c +++ b/drivers/iio/pressure/bmp280-core.c @@ -1110,7 +1110,7 @@ int bmp280_common_probe(struct device *dev, * however as it happens, the BMP085 shares the chip ID of BMP180 * so we look for an IRQ if we have that. */ - if (irq > 0 || (chip_id == BMP180_CHIP_ID)) { + if (irq > 0 && (chip_id == BMP180_CHIP_ID)) { ret = bmp085_fetch_eoc_irq(dev, name, irq, data); if (ret) goto out_disable_vdda; diff --git a/drivers/iio/pressure/ms5611_core.c b/drivers/iio/pressure/ms5611_core.c index 5c7a734ede54c4f9fc37e3873855fe3301cf3499..9980c6f3335e2db6cfda50ce5cd3d49ff498364b 100644 --- a/drivers/iio/pressure/ms5611_core.c +++ b/drivers/iio/pressure/ms5611_core.c @@ -79,7 +79,7 @@ static bool ms5611_prom_is_valid(u16 *prom, size_t len) crc = (crc >> 12) & 0x000F; - return crc_orig != 0x0000 && crc == crc_orig; + return crc == crc_orig; } static int ms5611_read_prom(struct iio_dev *indio_dev) diff --git a/drivers/infiniband/core/cma_configfs.c b/drivers/infiniband/core/cma_configfs.c index ce183d054785269fa41dcda6e071702e3073749d..f9b0303b3a01b6227a6757b413b94f7e7e236808 100644 --- a/drivers/infiniband/core/cma_configfs.c +++ b/drivers/infiniband/core/cma_configfs.c @@ -215,7 +215,7 @@ static int make_cma_ports(struct cma_dev_group *cma_dev_group, } for (i = 0; i < ports_num; i++) { - char port_str[10]; + char port_str[11]; ports[i].port_num = i + 1; snprintf(port_str, sizeof(port_str), "%u", i + 1); diff --git a/drivers/infiniband/core/uverbs_cmd.c b/drivers/infiniband/core/uverbs_cmd.c index 5e10a40fd26d33cc183e78a21ee33da6fb6f6bce..3b287a51cd626848642303dc2eefb86d24c166bf 100644 --- a/drivers/infiniband/core/uverbs_cmd.c +++ b/drivers/infiniband/core/uverbs_cmd.c @@ -1726,7 +1726,7 @@ ssize_t ib_uverbs_open_qp(struct ib_uverbs_file *file, struct ib_udata udata; struct ib_uqp_object *obj; struct ib_xrcd *xrcd; - struct ib_uobject *uninitialized_var(xrcd_uobj); + struct ib_uobject *xrcd_uobj; struct ib_qp *qp; struct ib_qp_open_attr attr; int ret; @@ -2041,8 +2041,13 @@ static int modify_qp(struct ib_uverbs_file *file, attr->path_mtu = cmd->base.path_mtu; if (cmd->base.attr_mask & IB_QP_PATH_MIG_STATE) attr->path_mig_state = cmd->base.path_mig_state; - if (cmd->base.attr_mask & IB_QP_QKEY) + if (cmd->base.attr_mask & IB_QP_QKEY) { + if (cmd->base.qkey & IB_QP_SET_QKEY && !capable(CAP_NET_RAW)) { + ret = -EPERM; + goto release_qp; + } attr->qkey = cmd->base.qkey; + } if (cmd->base.attr_mask & IB_QP_RQ_PSN) attr->rq_psn = cmd->base.rq_psn; if (cmd->base.attr_mask & IB_QP_SQ_PSN) @@ -3689,7 +3694,7 @@ static int __uverbs_create_xsrq(struct ib_uverbs_file *file, struct ib_usrq_object *obj; struct ib_pd *pd; struct ib_srq *srq; - struct ib_uobject *uninitialized_var(xrcd_uobj); + struct ib_uobject *xrcd_uobj; struct ib_srq_init_attr attr; int ret; struct ib_device *ib_dev; diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c index fc4b46258c756ceb23ac7e5560030d2fe090a984..6d8925432d6a7072e7acc1632d8be42504b1435f 100644 --- a/drivers/infiniband/core/uverbs_main.c +++ b/drivers/infiniband/core/uverbs_main.c @@ -283,8 +283,12 @@ static ssize_t ib_uverbs_event_read(struct ib_uverbs_event_queue *ev_queue, spin_lock_irq(&ev_queue->lock); while (list_empty(&ev_queue->event_list)) { - spin_unlock_irq(&ev_queue->lock); + if (ev_queue->is_closed) { + spin_unlock_irq(&ev_queue->lock); + return -EIO; + } + spin_unlock_irq(&ev_queue->lock); if (filp->f_flags & O_NONBLOCK) return -EAGAIN; @@ -294,12 +298,6 @@ static ssize_t ib_uverbs_event_read(struct ib_uverbs_event_queue *ev_queue, return -ERESTARTSYS; spin_lock_irq(&ev_queue->lock); - - /* If device was disassociated and no event exists set an error */ - if (list_empty(&ev_queue->event_list) && ev_queue->is_closed) { - spin_unlock_irq(&ev_queue->lock); - return -EIO; - } } event = list_entry(ev_queue->event_list.next, struct ib_uverbs_event, list); diff --git a/drivers/infiniband/core/uverbs_std_types_counters.c b/drivers/infiniband/core/uverbs_std_types_counters.c index a0ffdcf9a51cd130b8bee57d9a46e3983d4cf27f..bb3a03cdc9742fe3c29fb201d0943a1b1f8713f0 100644 --- a/drivers/infiniband/core/uverbs_std_types_counters.c +++ b/drivers/infiniband/core/uverbs_std_types_counters.c @@ -103,6 +103,8 @@ static int UVERBS_HANDLER(UVERBS_METHOD_COUNTERS_READ)( return ret; uattr = uverbs_attr_get(attrs, UVERBS_ATTR_READ_COUNTERS_BUFF); + if (IS_ERR(uattr)) + return PTR_ERR(uattr); read_attr.ncounters = uattr->ptr_attr.len / sizeof(u64); read_attr.counters_buff = uverbs_zalloc( attrs, array_size(read_attr.ncounters, sizeof(u64))); diff --git a/drivers/infiniband/hw/cxgb4/cm.c b/drivers/infiniband/hw/cxgb4/cm.c index 6c1a093b164e08190b30acce904bac3834470d6d..e8d2135df22db5bae18d94973acfd5f2f676d4f3 100644 --- a/drivers/infiniband/hw/cxgb4/cm.c +++ b/drivers/infiniband/hw/cxgb4/cm.c @@ -1922,6 +1922,9 @@ static int send_fw_act_open_req(struct c4iw_ep *ep, unsigned int atid) int win; skb = get_skb(NULL, sizeof(*req), GFP_KERNEL); + if (!skb) + return -ENOMEM; + req = __skb_put_zero(skb, sizeof(*req)); req->op_compl = htonl(WR_OP_V(FW_OFLD_CONNECTION_WR)); req->len16_pkd = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*req), 16))); @@ -3195,7 +3198,7 @@ static int get_lladdr(struct net_device *dev, struct in6_addr *addr, static int pick_local_ip6addrs(struct c4iw_dev *dev, struct iw_cm_id *cm_id) { - struct in6_addr uninitialized_var(addr); + struct in6_addr addr; struct sockaddr_in6 *la6 = (struct sockaddr_in6 *)&cm_id->m_local_addr; struct sockaddr_in6 *ra6 = (struct sockaddr_in6 *)&cm_id->m_remote_addr; diff --git a/drivers/infiniband/hw/cxgb4/cq.c b/drivers/infiniband/hw/cxgb4/cq.c index 43c611aa068c72088a3b7bb3323760d6c59365ae..8f30d477ab7692cd0cee1cce7b845d0d45031e8f 100644 --- a/drivers/infiniband/hw/cxgb4/cq.c +++ b/drivers/infiniband/hw/cxgb4/cq.c @@ -755,7 +755,7 @@ static int poll_cq(struct t4_wq *wq, struct t4_cq *cq, struct t4_cqe *cqe, static int __c4iw_poll_cq_one(struct c4iw_cq *chp, struct c4iw_qp *qhp, struct ib_wc *wc, struct c4iw_srq *srq) { - struct t4_cqe uninitialized_var(cqe); + struct t4_cqe cqe; struct t4_wq *wq = qhp ? &qhp->wq : NULL; u32 credit = 0; u8 cqe_flushed; diff --git a/drivers/infiniband/hw/hfi1/chip.c b/drivers/infiniband/hw/hfi1/chip.c index 1221faea75a68d69be30103ab0259514f22264d7..54a65db2443e7470a6017f94d2efe63118f51aea 100644 --- a/drivers/infiniband/hw/hfi1/chip.c +++ b/drivers/infiniband/hw/hfi1/chip.c @@ -12178,6 +12178,7 @@ static void free_cntrs(struct hfi1_devdata *dd) if (dd->synth_stats_timer.function) del_timer_sync(&dd->synth_stats_timer); + cancel_work_sync(&dd->update_cntr_work); ppd = (struct hfi1_pportdata *)(dd + 1); for (i = 0; i < dd->num_pports; i++, ppd++) { kfree(ppd->cntrs); diff --git a/drivers/infiniband/hw/hfi1/efivar.c b/drivers/infiniband/hw/hfi1/efivar.c index d106d23016ba0c4c15b56e3bdb33c31bab7f6408..75e39e403a58139b4c4e738c12b9d985c16bd95f 100644 --- a/drivers/infiniband/hw/hfi1/efivar.c +++ b/drivers/infiniband/hw/hfi1/efivar.c @@ -152,7 +152,7 @@ int read_hfi1_efi_var(struct hfi1_devdata *dd, const char *kind, unsigned long *size, void **return_data) { char prefix_name[64]; - char name[64]; + char name[128]; int result; int i; diff --git a/drivers/infiniband/hw/hfi1/mmu_rb.c b/drivers/infiniband/hw/hfi1/mmu_rb.c index e1c7996c018efe688dbe081cc0928f05c5f0bbdd..513a297b4ff0e3e08bcb22cdff02cbdf8a10a53a 100644 --- a/drivers/infiniband/hw/hfi1/mmu_rb.c +++ b/drivers/infiniband/hw/hfi1/mmu_rb.c @@ -175,7 +175,7 @@ int hfi1_mmu_rb_insert(struct mmu_rb_handler *handler, goto unlock; } __mmu_int_rb_insert(mnode, &handler->root); - list_add(&mnode->list, &handler->lru_list); + list_add_tail(&mnode->list, &handler->lru_list); ret = handler->ops->insert(handler->ops_arg, mnode); if (ret) { @@ -222,8 +222,10 @@ bool hfi1_mmu_rb_remove_unless_exact(struct mmu_rb_handler *handler, spin_lock_irqsave(&handler->lock, flags); node = __mmu_rb_search(handler, addr, len); if (node) { - if (node->addr == addr && node->len == len) + if (node->addr == addr && node->len == len) { + list_move_tail(&node->list, &handler->lru_list); goto unlock; + } __mmu_int_rb_remove(node, &handler->root); list_del(&node->list); /* remove from LRU list */ ret = true; @@ -244,8 +246,7 @@ void hfi1_mmu_rb_evict(struct mmu_rb_handler *handler, void *evict_arg) INIT_LIST_HEAD(&del_list); spin_lock_irqsave(&handler->lock, flags); - list_for_each_entry_safe_reverse(rbnode, ptr, &handler->lru_list, - list) { + list_for_each_entry_safe(rbnode, ptr, &handler->lru_list, list) { if (handler->ops->evict(handler->ops_arg, rbnode, evict_arg, &stop)) { __mmu_int_rb_remove(rbnode, &handler->root); @@ -257,9 +258,7 @@ void hfi1_mmu_rb_evict(struct mmu_rb_handler *handler, void *evict_arg) } spin_unlock_irqrestore(&handler->lock, flags); - while (!list_empty(&del_list)) { - rbnode = list_first_entry(&del_list, struct mmu_rb_node, list); - list_del(&rbnode->list); + list_for_each_entry_safe(rbnode, ptr, &del_list, list) { handler->ops->remove(handler->ops_arg, rbnode); } } diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c index a8dd12e525f8126d65d93023d8bbac9f52723efb..e1b6da777558495690f6ecdb030a3f489614affc 100644 --- a/drivers/infiniband/hw/hfi1/pcie.c +++ b/drivers/infiniband/hw/hfi1/pcie.c @@ -45,6 +45,7 @@ * */ +#include #include #include #include @@ -273,12 +274,6 @@ static u32 extract_speed(u16 linkstat) return speed; } -/* return the PCIe link speed from the given link status */ -static u32 extract_width(u16 linkstat) -{ - return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; -} - /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ static void update_lbus_info(struct hfi1_devdata *dd) { @@ -291,7 +286,7 @@ static void update_lbus_info(struct hfi1_devdata *dd) return; } - dd->lbus_width = extract_width(linkstat); + dd->lbus_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, linkstat); dd->lbus_speed = extract_speed(linkstat); snprintf(dd->lbus_info, sizeof(dd->lbus_info), "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); diff --git a/drivers/infiniband/hw/hfi1/sdma.c b/drivers/infiniband/hw/hfi1/sdma.c index 33ff9eca28f69ba9d7992fdf0ad6d1bc42caa5c6..245f9505a9acae30c950c494dd0c8ee40d4607e6 100644 --- a/drivers/infiniband/hw/hfi1/sdma.c +++ b/drivers/infiniband/hw/hfi1/sdma.c @@ -3202,8 +3202,7 @@ int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx) { int rval = 0; - tx->num_desc++; - if ((unlikely(tx->num_desc == tx->desc_limit))) { + if ((unlikely(tx->num_desc + 1 == tx->desc_limit))) { rval = _extend_sdma_tx_descs(dd, tx); if (rval) { __sdma_txclean(dd, tx); @@ -3216,6 +3215,7 @@ int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx) SDMA_MAP_NONE, dd->sdma_pad_phys, sizeof(u32) - (tx->packet_len & (sizeof(u32) - 1))); + tx->num_desc++; _sdma_close_tx(dd, tx); return rval; } diff --git a/drivers/infiniband/hw/hfi1/sdma.h b/drivers/infiniband/hw/hfi1/sdma.h index 46c775f255d14fb5ccb046f45356bc97c7e50434..a3dd2f3d56cca61849f0e8abf2d6a320eb21246f 100644 --- a/drivers/infiniband/hw/hfi1/sdma.h +++ b/drivers/infiniband/hw/hfi1/sdma.h @@ -680,14 +680,13 @@ static inline void sdma_txclean(struct hfi1_devdata *dd, struct sdma_txreq *tx) static inline void _sdma_close_tx(struct hfi1_devdata *dd, struct sdma_txreq *tx) { - tx->descp[tx->num_desc].qw[0] |= - SDMA_DESC0_LAST_DESC_FLAG; - tx->descp[tx->num_desc].qw[1] |= - dd->default_desc1; + u16 last_desc = tx->num_desc - 1; + + tx->descp[last_desc].qw[0] |= SDMA_DESC0_LAST_DESC_FLAG; + tx->descp[last_desc].qw[1] |= dd->default_desc1; if (tx->flags & SDMA_TXREQ_F_URGENT) - tx->descp[tx->num_desc].qw[1] |= - (SDMA_DESC1_HEAD_TO_HOST_FLAG | - SDMA_DESC1_INT_REQ_FLAG); + tx->descp[last_desc].qw[1] |= (SDMA_DESC1_HEAD_TO_HOST_FLAG | + SDMA_DESC1_INT_REQ_FLAG); } static inline int _sdma_txadd_daddr( @@ -704,6 +703,7 @@ static inline int _sdma_txadd_daddr( type, addr, len); WARN_ON(len > tx->tlen); + tx->num_desc++; tx->tlen -= len; /* special cases for last */ if (!tx->tlen) { @@ -715,7 +715,6 @@ static inline int _sdma_txadd_daddr( _sdma_close_tx(dd, tx); } } - tx->num_desc++; return rval; } diff --git a/drivers/infiniband/hw/i40iw/i40iw.h b/drivers/infiniband/hw/i40iw/i40iw.h index 2f2b4426ded77569f563da934f9bce10fc67194b..c38381c71f772c381107f8c0e081c78220f6135c 100644 --- a/drivers/infiniband/hw/i40iw/i40iw.h +++ b/drivers/infiniband/hw/i40iw/i40iw.h @@ -411,9 +411,8 @@ void i40iw_manage_arp_cache(struct i40iw_device *iwdev, bool ipv4, u32 action); -int i40iw_manage_apbvt(struct i40iw_device *iwdev, - u16 accel_local_port, - bool add_port); +enum i40iw_status_code i40iw_manage_apbvt(struct i40iw_device *iwdev, + u16 accel_local_port, bool add_port); struct i40iw_cqp_request *i40iw_get_cqp_request(struct i40iw_cqp *cqp, bool wait); void i40iw_free_cqp_request(struct i40iw_cqp *cqp, struct i40iw_cqp_request *cqp_request); diff --git a/drivers/infiniband/hw/mlx4/qp.c b/drivers/infiniband/hw/mlx4/qp.c index 7209b8a9b0dd24179a5871340787437b855ad822..b48596e174d6559cd30d95ccbee6c69d69dd14a8 100644 --- a/drivers/infiniband/hw/mlx4/qp.c +++ b/drivers/infiniband/hw/mlx4/qp.c @@ -436,9 +436,13 @@ static int set_user_sq_size(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, struct mlx4_ib_create_qp *ucmd) { + u32 cnt; + /* Sanity check SQ size before proceeding */ - if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || - ucmd->log_sq_stride > + if (check_shl_overflow(1, ucmd->log_sq_bb_count, &cnt) || + cnt > dev->dev->caps.max_wqes) + return -EINVAL; + if (ucmd->log_sq_stride > ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) return -EINVAL; @@ -550,15 +554,15 @@ static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx, return (-EOPNOTSUPP); } - if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 | - MLX4_IB_RX_HASH_DST_IPV4 | - MLX4_IB_RX_HASH_SRC_IPV6 | - MLX4_IB_RX_HASH_DST_IPV6 | - MLX4_IB_RX_HASH_SRC_PORT_TCP | - MLX4_IB_RX_HASH_DST_PORT_TCP | - MLX4_IB_RX_HASH_SRC_PORT_UDP | - MLX4_IB_RX_HASH_DST_PORT_UDP | - MLX4_IB_RX_HASH_INNER)) { + if (ucmd->rx_hash_fields_mask & ~(u64)(MLX4_IB_RX_HASH_SRC_IPV4 | + MLX4_IB_RX_HASH_DST_IPV4 | + MLX4_IB_RX_HASH_SRC_IPV6 | + MLX4_IB_RX_HASH_DST_IPV6 | + MLX4_IB_RX_HASH_SRC_PORT_TCP | + MLX4_IB_RX_HASH_DST_PORT_TCP | + MLX4_IB_RX_HASH_SRC_PORT_UDP | + MLX4_IB_RX_HASH_DST_PORT_UDP | + MLX4_IB_RX_HASH_INNER)) { pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n", ucmd->rx_hash_fields_mask); return (-EOPNOTSUPP); @@ -3459,11 +3463,11 @@ static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, int nreq; int err = 0; unsigned ind; - int uninitialized_var(size); - unsigned uninitialized_var(seglen); + int size; + unsigned seglen; __be32 dummy; __be32 *lso_wqe; - __be32 uninitialized_var(lso_hdr_sz); + __be32 lso_hdr_sz; __be32 blh; int i; struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); diff --git a/drivers/infiniband/hw/mlx4/sysfs.c b/drivers/infiniband/hw/mlx4/sysfs.c index d2da28d613f2cc41397de8f2a9d7af99510aaa54..eb95292d12dcb7644e4a489e9e46e276c3f75659 100644 --- a/drivers/infiniband/hw/mlx4/sysfs.c +++ b/drivers/infiniband/hw/mlx4/sysfs.c @@ -221,7 +221,7 @@ void del_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num, static int add_port_entries(struct mlx4_ib_dev *device, int port_num) { int i; - char buff[11]; + char buff[12]; struct mlx4_ib_iov_port *port = NULL; int ret = 0 ; struct ib_port_attr attr; diff --git a/drivers/infiniband/hw/mlx5/cq.c b/drivers/infiniband/hw/mlx5/cq.c index 872985e4eebec98546d91f7e103f221aaa58de7a..c5d3fe256182f5ad907c4518b42dd9b2f969b274 100644 --- a/drivers/infiniband/hw/mlx5/cq.c +++ b/drivers/infiniband/hw/mlx5/cq.c @@ -1333,7 +1333,7 @@ int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) __be64 *pas; int page_shift; int inlen; - int uninitialized_var(cqe_size); + int cqe_size; unsigned long flags; if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) { diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c index 1688c06d5c3c79410fc7230f246a675aa8971dfa..f7df27c7c634493f8dd9fe919a93136d346854d3 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c @@ -2005,7 +2005,7 @@ static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) case MLX5_IB_MMAP_DEVICE_MEM: return "Device Memory"; default: - return NULL; + return "Unknown"; } } diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c index 1520a3098f7dc26a85d4d64339f7642f9e2527d6..0455abfba41c234cbe316f4d47be22ae5eda824c 100644 --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c @@ -3350,7 +3350,7 @@ static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, return -EINVAL; if (attr->port_num == 0 || - attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { + attr->port_num > dev->num_ports) { mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", attr->port_num, dev->num_ports); return -EINVAL; diff --git a/drivers/infiniband/hw/mthca/mthca_qp.c b/drivers/infiniband/hw/mthca/mthca_qp.c index 3d37f2373d63a2a3f4ef1792087ce11cb7df3ea9..a336f69c2653a2e16c6ce9de31bcf6ff3b4e61d9 100644 --- a/drivers/infiniband/hw/mthca/mthca_qp.c +++ b/drivers/infiniband/hw/mthca/mthca_qp.c @@ -1630,8 +1630,8 @@ int mthca_tavor_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, * without initializing f0 and size0, and they are in fact * never used uninitialized. */ - int uninitialized_var(size0); - u32 uninitialized_var(f0); + int size0; + u32 f0; int ind; u8 op0 = 0; @@ -1831,7 +1831,7 @@ int mthca_tavor_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr, * without initializing size0, and it is in fact never used * uninitialized. */ - int uninitialized_var(size0); + int size0; int ind; void *wqe; void *prev_wqe; @@ -1945,8 +1945,8 @@ int mthca_arbel_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, * without initializing f0 and size0, and they are in fact * never used uninitialized. */ - int uninitialized_var(size0); - u32 uninitialized_var(f0); + int size0; + u32 f0; int ind; u8 op0 = 0; diff --git a/drivers/infiniband/sw/rdmavt/qp.c b/drivers/infiniband/sw/rdmavt/qp.c index fbc316775669c47e839ac9f158aea27cb3fa30f1..c12fc2eace1611be95bc991f76400853675e207e 100644 --- a/drivers/infiniband/sw/rdmavt/qp.c +++ b/drivers/infiniband/sw/rdmavt/qp.c @@ -321,8 +321,6 @@ void rvt_qp_exit(struct rvt_dev_info *rdi) if (qps_inuse) rvt_pr_err(rdi, "QP memory leak! %u still in use\n", qps_inuse); - if (!rdi->qp_dev) - return; kfree(rdi->qp_dev->qp_table); free_qpn_table(&rdi->qp_dev->qpn_table); diff --git a/drivers/infiniband/sw/rxe/rxe_qp.c b/drivers/infiniband/sw/rxe/rxe_qp.c index 2cae62ae6c64a1e70612abcbb09cfcd653e00a6c..73009bf8a9c0bbe781a9d4b098774d8f0447122e 100644 --- a/drivers/infiniband/sw/rxe/rxe_qp.c +++ b/drivers/infiniband/sw/rxe/rxe_qp.c @@ -218,6 +218,9 @@ static void rxe_qp_init_misc(struct rxe_dev *rxe, struct rxe_qp *qp, spin_lock_init(&qp->rq.producer_lock); spin_lock_init(&qp->rq.consumer_lock); + skb_queue_head_init(&qp->req_pkts); + skb_queue_head_init(&qp->resp_pkts); + atomic_set(&qp->ssn, 0); atomic_set(&qp->skb_out, 0); } @@ -266,12 +269,8 @@ static int rxe_qp_init_req(struct rxe_dev *rxe, struct rxe_qp *qp, qp->req.opcode = -1; qp->comp.opcode = -1; - skb_queue_head_init(&qp->req_pkts); - - rxe_init_task(rxe, &qp->req.task, qp, - rxe_requester, "req"); - rxe_init_task(rxe, &qp->comp.task, qp, - rxe_completer, "comp"); + rxe_init_task(&qp->req.task, qp, rxe_requester); + rxe_init_task(&qp->comp.task, qp, rxe_completer); qp->qp_timeout_jiffies = 0; /* Can't be set for UD/UC in modify_qp */ if (init->qp_type == IB_QPT_RC) { @@ -315,10 +314,7 @@ static int rxe_qp_init_resp(struct rxe_dev *rxe, struct rxe_qp *qp, } } - skb_queue_head_init(&qp->resp_pkts); - - rxe_init_task(rxe, &qp->resp.task, qp, - rxe_responder, "resp"); + rxe_init_task(&qp->resp.task, qp, rxe_responder); qp->resp.opcode = OPCODE_NONE; qp->resp.msn = 0; diff --git a/drivers/infiniband/sw/rxe/rxe_task.c b/drivers/infiniband/sw/rxe/rxe_task.c index 08f05ac5f5d526f94d48f5b68ae9512463c4bd15..39b3adda16550e850ba890e81312ae4682c2be28 100644 --- a/drivers/infiniband/sw/rxe/rxe_task.c +++ b/drivers/infiniband/sw/rxe/rxe_task.c @@ -114,13 +114,10 @@ void rxe_do_task(unsigned long data) task->ret = ret; } -int rxe_init_task(void *obj, struct rxe_task *task, - void *arg, int (*func)(void *), char *name) +int rxe_init_task(struct rxe_task *task, void *arg, int (*func)(void *)) { - task->obj = obj; task->arg = arg; task->func = func; - snprintf(task->name, sizeof(task->name), "%s", name); task->destroyed = false; tasklet_init(&task->tasklet, rxe_do_task, (unsigned long)task); diff --git a/drivers/infiniband/sw/rxe/rxe_task.h b/drivers/infiniband/sw/rxe/rxe_task.h index 08ff42d451c621f98ba60595b1c8566effe0334f..ecd81b1d1a8cbf0b56661cfffdc08d8a83d2ae70 100644 --- a/drivers/infiniband/sw/rxe/rxe_task.h +++ b/drivers/infiniband/sw/rxe/rxe_task.h @@ -46,14 +46,12 @@ enum { * called again. */ struct rxe_task { - void *obj; struct tasklet_struct tasklet; int state; spinlock_t state_lock; /* spinlock for task state */ void *arg; int (*func)(void *arg); int ret; - char name[16]; bool destroyed; }; @@ -62,8 +60,7 @@ struct rxe_task { * arg => parameter to pass to fcn * fcn => function to call until it returns != 0 */ -int rxe_init_task(void *obj, struct rxe_task *task, - void *arg, int (*func)(void *), char *name); +int rxe_init_task(struct rxe_task *task, void *arg, int (*func)(void *)); /* cleanup task */ void rxe_cleanup_task(struct rxe_task *task); diff --git a/drivers/infiniband/ulp/isert/ib_isert.c b/drivers/infiniband/ulp/isert/ib_isert.c index f39670c5c25c57de945b6e5d454707800374b385..60594dad55455cb93d430d3fe41f8205ed12c639 100644 --- a/drivers/infiniband/ulp/isert/ib_isert.c +++ b/drivers/infiniband/ulp/isert/ib_isert.c @@ -742,9 +742,13 @@ static int isert_connect_error(struct rdma_cm_id *cma_id) { struct isert_conn *isert_conn = cma_id->qp->qp_context; + struct isert_np *isert_np = cma_id->context; ib_drain_qp(isert_conn->qp); + + mutex_lock(&isert_np->mutex); list_del_init(&isert_conn->node); + mutex_unlock(&isert_np->mutex); isert_conn->cm_id = NULL; isert_put_conn(isert_conn); @@ -2515,6 +2519,7 @@ isert_free_np(struct iscsi_np *np) { struct isert_np *isert_np = np->np_context; struct isert_conn *isert_conn, *n; + LIST_HEAD(drop_conn_list); if (isert_np->cm_id) rdma_destroy_id(isert_np->cm_id); @@ -2534,7 +2539,7 @@ isert_free_np(struct iscsi_np *np) node) { isert_info("cleaning isert_conn %p state (%d)\n", isert_conn, isert_conn->state); - isert_connect_release(isert_conn); + list_move_tail(&isert_conn->node, &drop_conn_list); } } @@ -2545,11 +2550,16 @@ isert_free_np(struct iscsi_np *np) node) { isert_info("cleaning isert_conn %p state (%d)\n", isert_conn, isert_conn->state); - isert_connect_release(isert_conn); + list_move_tail(&isert_conn->node, &drop_conn_list); } } mutex_unlock(&isert_np->mutex); + list_for_each_entry_safe(isert_conn, n, &drop_conn_list, node) { + list_del_init(&isert_conn->node); + isert_connect_release(isert_conn); + } + np->np_context = NULL; kfree(isert_np); } diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c index c125cd42faee73590b3a6d42071f2b4fc26c8357..4591f60dd6e2dda25e66d9c9953ac31dde68dae9 100644 --- a/drivers/input/joystick/xpad.c +++ b/drivers/input/joystick/xpad.c @@ -266,6 +266,7 @@ static const struct xpad_device { { 0x1038, 0x1430, "SteelSeries Stratus Duo", 0, XTYPE_XBOX360 }, { 0x1038, 0x1431, "SteelSeries Stratus Duo", 0, XTYPE_XBOX360 }, { 0x11c9, 0x55f0, "Nacon GC-100XF", 0, XTYPE_XBOX360 }, + { 0x11ff, 0x0511, "PXN V900", 0, XTYPE_XBOX360 }, { 0x1209, 0x2882, "Ardwiino Controller", 0, XTYPE_XBOX360 }, { 0x12ab, 0x0004, "Honey Bee Xbox360 dancepad", MAP_DPAD_TO_BUTTONS, XTYPE_XBOX360 }, { 0x12ab, 0x0301, "PDP AFTERGLOW AX.1", 0, XTYPE_XBOX360 }, @@ -276,7 +277,6 @@ static const struct xpad_device { { 0x1430, 0xf801, "RedOctane Controller", 0, XTYPE_XBOX360 }, { 0x146b, 0x0601, "BigBen Interactive XBOX 360 Controller", 0, XTYPE_XBOX360 }, { 0x146b, 0x0604, "Bigben Interactive DAIJA Arcade Stick", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX360 }, - { 0x1532, 0x0037, "Razer Sabertooth", 0, XTYPE_XBOX360 }, { 0x1532, 0x0a00, "Razer Atrox Arcade Stick", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOXONE }, { 0x1532, 0x0a03, "Razer Wildcat", 0, XTYPE_XBOXONE }, { 0x15e4, 0x3f00, "Power A Mini Pro Elite", 0, XTYPE_XBOX360 }, @@ -461,6 +461,7 @@ static const struct usb_device_id xpad_table[] = { XPAD_XBOXONE_VENDOR(0x0f0d), /* Hori Controllers */ XPAD_XBOX360_VENDOR(0x1038), /* SteelSeries Controllers */ XPAD_XBOX360_VENDOR(0x11c9), /* Nacon GC100XF */ + XPAD_XBOX360_VENDOR(0x11ff), /* PXN V900 */ XPAD_XBOX360_VENDOR(0x1209), /* Ardwiino Controllers */ XPAD_XBOX360_VENDOR(0x12ab), /* X-Box 360 dance pads */ XPAD_XBOX360_VENDOR(0x1430), /* RedOctane X-Box 360 controllers */ @@ -503,6 +504,9 @@ struct xboxone_init_packet { } +#define GIP_WIRED_INTF_DATA 0 +#define GIP_WIRED_INTF_AUDIO 1 + /* * This packet is required for all Xbox One pads with 2015 * or later firmware installed (or present from the factory). @@ -1827,7 +1831,7 @@ static int xpad_probe(struct usb_interface *intf, const struct usb_device_id *id } if (xpad->xtype == XTYPE_XBOXONE && - intf->cur_altsetting->desc.bInterfaceNumber != 0) { + intf->cur_altsetting->desc.bInterfaceNumber != GIP_WIRED_INTF_DATA) { /* * The Xbox One controller lists three interfaces all with the * same interface class, subclass and protocol. Differentiate by diff --git a/drivers/input/misc/adxl34x.c b/drivers/input/misc/adxl34x.c index 3695dd7dbb9b4c7d158ea3b6ab943b4ae093274b..ec0c91ec52277d2a16f3a58e86a70933c4e1a742 100644 --- a/drivers/input/misc/adxl34x.c +++ b/drivers/input/misc/adxl34x.c @@ -811,8 +811,7 @@ struct adxl34x *adxl34x_probe(struct device *dev, int irq, AC_WRITE(ac, POWER_CTL, 0); err = request_threaded_irq(ac->irq, NULL, adxl34x_irq, - IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - dev_name(dev), ac); + IRQF_ONESHOT, dev_name(dev), ac); if (err) { dev_err(dev, "irq %d busy?\n", ac->irq); goto err_free_mem; diff --git a/drivers/input/misc/drv260x.c b/drivers/input/misc/drv260x.c index 17eb84ab4c0b7813dcfe394023d16cc218c18953..fe3fbde989be281a8f85cdb09976a8193b6aceb7 100644 --- a/drivers/input/misc/drv260x.c +++ b/drivers/input/misc/drv260x.c @@ -443,6 +443,7 @@ static int drv260x_init(struct drv260x_data *haptics) } do { + usleep_range(15000, 15500); error = regmap_read(haptics->regmap, DRV260X_GO, &cal_buf); if (error) { dev_err(&haptics->client->dev, diff --git a/drivers/input/misc/powermate.c b/drivers/input/misc/powermate.c index e8de3aaf9f6330a276c99387fab80573a5bf6dd6..14f48e10f589e81b8d5f38314cb0d6f6708589bb 100644 --- a/drivers/input/misc/powermate.c +++ b/drivers/input/misc/powermate.c @@ -424,6 +424,7 @@ static void powermate_disconnect(struct usb_interface *intf) pm->requires_update = 0; usb_kill_urb(pm->irq); input_unregister_device(pm->input); + usb_kill_urb(pm->config); usb_free_urb(pm->irq); usb_free_urb(pm->config); powermate_free_buffers(interface_to_usbdev(intf), pm); diff --git a/drivers/input/mouse/alps.c b/drivers/input/mouse/alps.c index dd80ff6cc4273079fa8f75806d89df97e914fa01..b53da63602352a8a17134823f8cf621f785fa8d9 100644 --- a/drivers/input/mouse/alps.c +++ b/drivers/input/mouse/alps.c @@ -855,8 +855,8 @@ static void alps_process_packet_v6(struct psmouse *psmouse) x = y = z = 0; /* Divide 4 since trackpoint's speed is too fast */ - input_report_rel(dev2, REL_X, (char)x / 4); - input_report_rel(dev2, REL_Y, -((char)y / 4)); + input_report_rel(dev2, REL_X, (s8)x / 4); + input_report_rel(dev2, REL_Y, -((s8)y / 4)); psmouse_report_standard_buttons(dev2, packet[3]); @@ -1107,8 +1107,8 @@ static void alps_process_trackstick_packet_v7(struct psmouse *psmouse) ((packet[3] & 0x20) << 1); z = (packet[5] & 0x3f) | ((packet[3] & 0x80) >> 1); - input_report_rel(dev2, REL_X, (char)x); - input_report_rel(dev2, REL_Y, -((char)y)); + input_report_rel(dev2, REL_X, (s8)x); + input_report_rel(dev2, REL_Y, -((s8)y)); input_report_abs(dev2, ABS_PRESSURE, z); psmouse_report_standard_buttons(dev2, packet[1]); @@ -2297,20 +2297,20 @@ static int alps_get_v3_v7_resolution(struct psmouse *psmouse, int reg_pitch) if (reg < 0) return reg; - x_pitch = (char)(reg << 4) >> 4; /* sign extend lower 4 bits */ + x_pitch = (s8)(reg << 4) >> 4; /* sign extend lower 4 bits */ x_pitch = 50 + 2 * x_pitch; /* In 0.1 mm units */ - y_pitch = (char)reg >> 4; /* sign extend upper 4 bits */ + y_pitch = (s8)reg >> 4; /* sign extend upper 4 bits */ y_pitch = 36 + 2 * y_pitch; /* In 0.1 mm units */ reg = alps_command_mode_read_reg(psmouse, reg_pitch + 1); if (reg < 0) return reg; - x_electrode = (char)(reg << 4) >> 4; /* sign extend lower 4 bits */ + x_electrode = (s8)(reg << 4) >> 4; /* sign extend lower 4 bits */ x_electrode = 17 + x_electrode; - y_electrode = (char)reg >> 4; /* sign extend upper 4 bits */ + y_electrode = (s8)reg >> 4; /* sign extend upper 4 bits */ y_electrode = 13 + y_electrode; x_phys = x_pitch * (x_electrode - 1); /* In 0.1 mm units */ diff --git a/drivers/input/mouse/elantech.c b/drivers/input/mouse/elantech.c index a18d17f7ef386268207f615fc9b50d7e452c52d2..6759cab82a7239ecd737e8059540b62156bbbfc0 100644 --- a/drivers/input/mouse/elantech.c +++ b/drivers/input/mouse/elantech.c @@ -590,10 +590,11 @@ static void process_packet_head_v4(struct psmouse *psmouse) struct input_dev *dev = psmouse->dev; struct elantech_data *etd = psmouse->private; unsigned char *packet = psmouse->packet; - int id = ((packet[3] & 0xe0) >> 5) - 1; + int id; int pres, traces; - if (id < 0) + id = ((packet[3] & 0xe0) >> 5) - 1; + if (id < 0 || id >= ETP_MAX_FINGERS) return; etd->mt[id].x = ((packet[1] & 0x0f) << 8) | packet[2]; @@ -623,7 +624,7 @@ static void process_packet_motion_v4(struct psmouse *psmouse) int id, sid; id = ((packet[0] & 0xe0) >> 5) - 1; - if (id < 0) + if (id < 0 || id >= ETP_MAX_FINGERS) return; sid = ((packet[3] & 0xe0) >> 5) - 1; @@ -644,7 +645,7 @@ static void process_packet_motion_v4(struct psmouse *psmouse) input_report_abs(dev, ABS_MT_POSITION_X, etd->mt[id].x); input_report_abs(dev, ABS_MT_POSITION_Y, etd->mt[id].y); - if (sid >= 0) { + if (sid >= 0 && sid < ETP_MAX_FINGERS) { etd->mt[sid].x += delta_x2 * weight; etd->mt[sid].y -= delta_y2 * weight; input_mt_slot(dev, sid); @@ -1995,6 +1996,7 @@ static int elantech_setup_ps2(struct psmouse *psmouse, psmouse->protocol_handler = elantech_process_byte; psmouse->disconnect = elantech_disconnect; psmouse->reconnect = elantech_reconnect; + psmouse->fast_reconnect = NULL; psmouse->pktsize = info->hw_version > 1 ? 6 : 4; return 0; diff --git a/drivers/input/mouse/focaltech.c b/drivers/input/mouse/focaltech.c index a7d39689bbfb6fc7df84f6a01a8b78bdc0cc6a99..4bd48b81ed9806a88366337fd292b9cf1df60f72 100644 --- a/drivers/input/mouse/focaltech.c +++ b/drivers/input/mouse/focaltech.c @@ -206,8 +206,8 @@ static void focaltech_process_rel_packet(struct psmouse *psmouse, state->pressed = packet[0] >> 7; finger1 = ((packet[0] >> 4) & 0x7) - 1; if (finger1 < FOC_MAX_FINGERS) { - state->fingers[finger1].x += (char)packet[1]; - state->fingers[finger1].y += (char)packet[2]; + state->fingers[finger1].x += (s8)packet[1]; + state->fingers[finger1].y += (s8)packet[2]; } else { psmouse_err(psmouse, "First finger in rel packet invalid: %d\n", finger1); @@ -222,8 +222,8 @@ static void focaltech_process_rel_packet(struct psmouse *psmouse, */ finger2 = ((packet[3] >> 4) & 0x7) - 1; if (finger2 < FOC_MAX_FINGERS) { - state->fingers[finger2].x += (char)packet[4]; - state->fingers[finger2].y += (char)packet[5]; + state->fingers[finger2].x += (s8)packet[4]; + state->fingers[finger2].y += (s8)packet[5]; } } diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c index c6d393114502d45c545ac3db019813eeca786f30..833c54af42c33d9fe00dec0454d6d90a63faa3dc 100644 --- a/drivers/input/mouse/synaptics.c +++ b/drivers/input/mouse/synaptics.c @@ -1620,6 +1620,7 @@ static int synaptics_init_ps2(struct psmouse *psmouse, psmouse->set_rate = synaptics_set_rate; psmouse->disconnect = synaptics_disconnect; psmouse->reconnect = synaptics_reconnect; + psmouse->fast_reconnect = NULL; psmouse->cleanup = synaptics_reset; /* Synaptics can usually stay in sync without extra help */ psmouse->resync_time = 0; @@ -1749,6 +1750,7 @@ static int synaptics_create_intertouch(struct psmouse *psmouse, psmouse_matches_pnp_id(psmouse, topbuttonpad_pnp_ids) && !SYN_CAP_EXT_BUTTONS_STICK(info->ext_cap_10); const struct rmi_device_platform_data pdata = { + .reset_delay_ms = 30, .sensor_pdata = { .sensor_type = rmi_sensor_touchpad, .axis_align.flip_y = true, diff --git a/drivers/input/rmi4/rmi_bus.c b/drivers/input/rmi4/rmi_bus.c index bd0d5ff01b08f9c88920b03f56dbb4a3eed21af3..02408487b442364e1e69dc3bb543f6a0a8d40e66 100644 --- a/drivers/input/rmi4/rmi_bus.c +++ b/drivers/input/rmi4/rmi_bus.c @@ -279,11 +279,11 @@ void rmi_unregister_function(struct rmi_function *fn) device_del(&fn->dev); of_node_put(fn->dev.of_node); - put_device(&fn->dev); for (i = 0; i < fn->num_of_irqs; i++) irq_dispose_mapping(fn->irq[i]); + put_device(&fn->dev); } /** diff --git a/drivers/input/rmi4/rmi_smbus.c b/drivers/input/rmi4/rmi_smbus.c index b6ccf39c6a7bb46bc67bf086952a799e27f4f930..e5b0109a4d155a82e9dd9259aa365763a714306c 100644 --- a/drivers/input/rmi4/rmi_smbus.c +++ b/drivers/input/rmi4/rmi_smbus.c @@ -238,12 +238,29 @@ static void rmi_smb_clear_state(struct rmi_smb_xport *rmi_smb) static int rmi_smb_enable_smbus_mode(struct rmi_smb_xport *rmi_smb) { - int retval; + struct i2c_client *client = rmi_smb->client; + int smbus_version; + + /* + * psmouse driver resets the controller, we only need to wait + * to give the firmware chance to fully reinitialize. + */ + if (rmi_smb->xport.pdata.reset_delay_ms) + msleep(rmi_smb->xport.pdata.reset_delay_ms); /* we need to get the smbus version to activate the touchpad */ - retval = rmi_smb_get_version(rmi_smb); - if (retval < 0) - return retval; + smbus_version = rmi_smb_get_version(rmi_smb); + if (smbus_version < 0) + return smbus_version; + + rmi_dbg(RMI_DEBUG_XPORT, &client->dev, "Smbus version is %d", + smbus_version); + + if (smbus_version != 2 && smbus_version != 3) { + dev_err(&client->dev, "Unrecognized SMB version %d\n", + smbus_version); + return -ENODEV; + } return 0; } @@ -256,11 +273,10 @@ static int rmi_smb_reset(struct rmi_transport_dev *xport, u16 reset_addr) rmi_smb_clear_state(rmi_smb); /* - * we do not call the actual reset command, it has to be handled in - * PS/2 or there will be races between PS/2 and SMBus. - * PS/2 should ensure that a psmouse_reset is called before - * intializing the device and after it has been removed to be in a known - * state. + * We do not call the actual reset command, it has to be handled in + * PS/2 or there will be races between PS/2 and SMBus. PS/2 should + * ensure that a psmouse_reset is called before initializing the + * device and after it has been removed to be in a known state. */ return rmi_smb_enable_smbus_mode(rmi_smb); } @@ -276,7 +292,6 @@ static int rmi_smb_probe(struct i2c_client *client, { struct rmi_device_platform_data *pdata = dev_get_platdata(&client->dev); struct rmi_smb_xport *rmi_smb; - int smbus_version; int error; if (!pdata) { @@ -315,18 +330,9 @@ static int rmi_smb_probe(struct i2c_client *client, rmi_smb->xport.proto_name = "smb"; rmi_smb->xport.ops = &rmi_smb_ops; - smbus_version = rmi_smb_get_version(rmi_smb); - if (smbus_version < 0) - return smbus_version; - - rmi_dbg(RMI_DEBUG_XPORT, &client->dev, "Smbus version is %d", - smbus_version); - - if (smbus_version != 2 && smbus_version != 3) { - dev_err(&client->dev, "Unrecognized SMB version %d\n", - smbus_version); - return -ENODEV; - } + error = rmi_smb_enable_smbus_mode(rmi_smb); + if (error) + return error; i2c_set_clientdata(client, rmi_smb); diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h index b2ab20c16cc77751d410058b7e09a169ca38dbb0..2d4df82d65afe760358f2840f118bf3f6e15e733 100644 --- a/drivers/input/serio/i8042-x86ia64io.h +++ b/drivers/input/serio/i8042-x86ia64io.h @@ -605,6 +605,22 @@ static const struct dmi_system_id i8042_dmi_quirk_table[] __initconst = { }, .driver_data = (void *)(SERIO_QUIRK_NOMUX) }, + { + /* Fujitsu Lifebook A574/H */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), + DMI_MATCH(DMI_PRODUCT_NAME, "FMVA0501PZ"), + }, + .driver_data = (void *)(SERIO_QUIRK_NOMUX) + }, + { + /* Fujitsu Lifebook E5411 */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU CLIENT COMPUTING LIMITED"), + DMI_MATCH(DMI_PRODUCT_NAME, "LIFEBOOK E5411"), + }, + .driver_data = (void *)(SERIO_QUIRK_NOAUX) + }, { /* Gigabyte M912 */ .matches = { @@ -1180,6 +1196,13 @@ static const struct dmi_system_id i8042_dmi_quirk_table[] __initconst = { .driver_data = (void *)(SERIO_QUIRK_NOMUX | SERIO_QUIRK_RESET_ALWAYS | SERIO_QUIRK_NOLOOP | SERIO_QUIRK_NOPNP) }, + /* See comment on TUXEDO InfinityBook S17 Gen6 / Clevo NS70MU above */ + { + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "PD5x_7xPNP_PNR_PNN_PNT"), + }, + .driver_data = (void *)(SERIO_QUIRK_NOAUX) + }, { .matches = { DMI_MATCH(DMI_BOARD_NAME, "X170SM"), diff --git a/drivers/input/serio/serio_raw.c b/drivers/input/serio/serio_raw.c index 17b7fbecd9fe7134c86823c2d9c88c5a24dc6ddb..d25059672323d9ff6f1e933eb6d8e561c827fe91 100644 --- a/drivers/input/serio/serio_raw.c +++ b/drivers/input/serio/serio_raw.c @@ -162,7 +162,7 @@ static ssize_t serio_raw_read(struct file *file, char __user *buffer, { struct serio_raw_client *client = file->private_data; struct serio_raw *serio_raw = client->serio_raw; - char uninitialized_var(c); + char c; ssize_t read = 0; int error; diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c index a2f45aefce08a166749e6fd89067dafaced7eaa2..46d87657e6a987779586021d75c819e93f7f148d 100644 --- a/drivers/input/touchscreen/ads7846.c +++ b/drivers/input/touchscreen/ads7846.c @@ -773,14 +773,8 @@ static void ads7846_report_state(struct ads7846 *ts) if (x == MAX_12BIT) x = 0; - if (ts->model == 7843) { + if (ts->model == 7843 || ts->model == 7845) { Rt = ts->pressure_max / 2; - } else if (ts->model == 7845) { - if (get_pendown_state(ts)) - Rt = ts->pressure_max / 2; - else - Rt = 0; - dev_vdbg(&ts->spi->dev, "x/y: %d/%d, PD %d\n", x, y, Rt); } else if (likely(x && z1)) { /* compute touch pressure resistance using equation #2 */ Rt = z2; @@ -1364,8 +1358,9 @@ static int ads7846_probe(struct spi_device *spi) pdata->y_min ? : 0, pdata->y_max ? : MAX_12BIT, 0, 0); - input_set_abs_params(input_dev, ABS_PRESSURE, - pdata->pressure_min, pdata->pressure_max, 0, 0); + if (ts->model != 7845) + input_set_abs_params(input_dev, ABS_PRESSURE, + pdata->pressure_min, pdata->pressure_max, 0, 0); ads7846_setup_spi_msg(ts, pdata); diff --git a/drivers/input/touchscreen/st/fts_lib/ftsIO.c b/drivers/input/touchscreen/st/fts_lib/ftsIO.c index d45b54fc84cfb2b41e2cb7272120314867343525..47fb5fe84ad585a65bf1d7d1efc287ad22207c0b 100644 --- a/drivers/input/touchscreen/st/fts_lib/ftsIO.c +++ b/drivers/input/touchscreen/st/fts_lib/ftsIO.c @@ -82,7 +82,7 @@ int openChannel(struct i2c_client *clt) return OK; } -struct device *getDev() +struct device *getDev(void) { if (client != NULL) return &(client->dev); @@ -90,7 +90,7 @@ struct device *getDev() return NULL; } -struct i2c_client *getClient() +struct i2c_client *getClient(void) { if (client != NULL) return client; diff --git a/drivers/input/touchscreen/st/fts_lib/ftsTime.c b/drivers/input/touchscreen/st/fts_lib/ftsTime.c index 07d1bf5dba8bb8e81379ebe19ddec7069c532cf5..6d21fc857057fc66201696dc6fb3a6eb52abf72f 100644 --- a/drivers/input/touchscreen/st/fts_lib/ftsTime.c +++ b/drivers/input/touchscreen/st/fts_lib/ftsTime.c @@ -92,7 +92,7 @@ int elapsedNanosecond(struct StopWatch *w) return result; } -char *timestamp() +char *timestamp(void) { char *result = NULL; diff --git a/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_core.c b/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_core.c index 70cfa215ca597acb6986c4b549eaebd60465483a..7fea63c0b0d902da2ce36cfdb2c6f85bf6de9fc9 100644 --- a/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_core.c +++ b/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_core.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index bb2d9ebaf6cd2afb3e52e64efe9995e0150e6540..2b6483a632033a9211999722f283de6855aadffa 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -672,9 +672,11 @@ static int arm_lpae_map_sg(struct io_pgtable_ops *ops, unsigned long iova, arm_lpae_iopte *ptep = ms.pgtable + ARM_LPAE_LVL_IDX(iova, MAP_STATE_LVL, data); - arm_lpae_init_pte( + ret = arm_lpae_init_pte( data, iova, phys, prot, MAP_STATE_LVL, ptep, ms.prev_pgtable, false); + if (ret) + goto out_err; ms.num_pte++; } else { ret = __arm_lpae_map(data, iova, phys, pgsize, diff --git a/drivers/irqchip/irq-alpine-msi.c b/drivers/irqchip/irq-alpine-msi.c index ede02dc2bcd0b9cdb811a9c679aa412568a6eba6..1819bb1d27230a6d4a09ccba7f6d07c6a2e7c9a9 100644 --- a/drivers/irqchip/irq-alpine-msi.c +++ b/drivers/irqchip/irq-alpine-msi.c @@ -199,6 +199,7 @@ static int alpine_msix_init_domains(struct alpine_msix_data *priv, } gic_domain = irq_find_host(gic_node); + of_node_put(gic_node); if (!gic_domain) { pr_err("Failed to find the GIC domain\n"); return -ENXIO; diff --git a/drivers/irqchip/irq-bcm6345-l1.c b/drivers/irqchip/irq-bcm6345-l1.c index 31ea6332ecb835a4c989583f69b910dddd9fb410..60dc64b4ac6d2e397949c1dade46e0f03ab1f646 100644 --- a/drivers/irqchip/irq-bcm6345-l1.c +++ b/drivers/irqchip/irq-bcm6345-l1.c @@ -85,6 +85,7 @@ struct bcm6345_l1_chip { }; struct bcm6345_l1_cpu { + struct bcm6345_l1_chip *intc; void __iomem *map_base; unsigned int parent_irq; u32 enable_cache[]; @@ -118,17 +119,11 @@ static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc, static void bcm6345_l1_irq_handle(struct irq_desc *desc) { - struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc); - struct bcm6345_l1_cpu *cpu; + struct bcm6345_l1_cpu *cpu = irq_desc_get_handler_data(desc); + struct bcm6345_l1_chip *intc = cpu->intc; struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int idx; -#ifdef CONFIG_SMP - cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; -#else - cpu = intc->cpus[0]; -#endif - chained_irq_enter(chip, desc); for (idx = 0; idx < intc->n_words; idx++) { @@ -260,6 +255,7 @@ static int __init bcm6345_l1_init_one(struct device_node *dn, if (!cpu) return -ENOMEM; + cpu->intc = intc; cpu->map_base = ioremap(res.start, sz); if (!cpu->map_base) return -ENOMEM; @@ -275,7 +271,7 @@ static int __init bcm6345_l1_init_one(struct device_node *dn, return -EINVAL; } irq_set_chained_handler_and_data(cpu->parent_irq, - bcm6345_l1_irq_handle, intc); + bcm6345_l1_irq_handle, cpu); return 0; } diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c index 8968e5e93fcb8e3bf478329b765c149a47153cd0..fefafe1af1167159afebd60177020bcfcef68cd1 100644 --- a/drivers/irqchip/irq-bcm7120-l2.c +++ b/drivers/irqchip/irq-bcm7120-l2.c @@ -271,7 +271,8 @@ static int __init bcm7120_l2_intc_probe(struct device_node *dn, flags |= IRQ_GC_BE_IO; ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1, - dn->full_name, handle_level_irq, clr, 0, flags); + dn->full_name, handle_level_irq, clr, + IRQ_LEVEL, flags); if (ret) { pr_err("failed to allocate generic irq chip\n"); goto out_free_domain; diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c index 83364fedbf0ab57962a7b325663ab910d6173a0a..3f1ae63233cb4159e51c339698739b0cf68be2b8 100644 --- a/drivers/irqchip/irq-brcmstb-l2.c +++ b/drivers/irqchip/irq-brcmstb-l2.c @@ -169,6 +169,7 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np, *init_params) { unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + unsigned int set = 0; struct brcmstb_l2_intc_data *data; struct irq_chip_type *ct; int ret; @@ -216,9 +217,12 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np, if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) flags |= IRQ_GC_BE_IO; + if (init_params->handler == handle_level_irq) + set |= IRQ_LEVEL; + /* Allocate a single Generic IRQ chip for this node */ ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, - np->full_name, init_params->handler, clr, 0, flags); + np->full_name, init_params->handler, clr, set, flags); if (ret) { pr_err("failed to allocate generic irq chip\n"); goto out_free_domain; diff --git a/drivers/irqchip/irq-jcore-aic.c b/drivers/irqchip/irq-jcore-aic.c index 033bccb41455c46c32d5473fa46940c2770973e9..b9dcc8e78c75017582f44d3615c7db92465f4465 100644 --- a/drivers/irqchip/irq-jcore-aic.c +++ b/drivers/irqchip/irq-jcore-aic.c @@ -68,6 +68,7 @@ static int __init aic_irq_of_init(struct device_node *node, unsigned min_irq = JCORE_AIC2_MIN_HWIRQ; unsigned dom_sz = JCORE_AIC_MAX_HWIRQ+1; struct irq_domain *domain; + int ret; pr_info("Initializing J-Core AIC\n"); @@ -100,11 +101,17 @@ static int __init aic_irq_of_init(struct device_node *node, jcore_aic.irq_unmask = noop; jcore_aic.name = "AIC"; - domain = irq_domain_add_linear(node, dom_sz, &jcore_aic_irqdomain_ops, + ret = irq_alloc_descs(-1, min_irq, dom_sz - min_irq, + of_node_to_nid(node)); + + if (ret < 0) + return ret; + + domain = irq_domain_add_legacy(node, dom_sz - min_irq, min_irq, min_irq, + &jcore_aic_irqdomain_ops, &jcore_aic); if (!domain) return -ENOMEM; - irq_create_strict_mappings(domain, min_irq, min_irq, dom_sz - min_irq); return 0; } diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c index 7599b10ecf09d153e8b2b563f2ce515f19eb3358..dcb22f2539effe4efa0b8150c5614ec11dd28efb 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -67,7 +67,7 @@ static const struct meson_gpio_irq_params axg_params = { .nr_hwirq = 100, }; -static const struct of_device_id meson_irq_gpio_matches[] = { +static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = { { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params }, { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params }, { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params }, diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index f3985469c2211c7fea4b40469a47c1e27711a510..caebafed49bb4f1a7ee8ba7be347f736c793c135 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -48,7 +48,7 @@ void __iomem *mips_gic_base; DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks); -static DEFINE_SPINLOCK(gic_lock); +static DEFINE_RAW_SPINLOCK(gic_lock); static struct irq_domain *gic_irq_domain; static struct irq_domain *gic_ipi_domain; static int gic_shared_intrs; @@ -207,7 +207,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) irq = GIC_HWIRQ_TO_SHARED(d->hwirq); - spin_lock_irqsave(&gic_lock, flags); + raw_spin_lock_irqsave(&gic_lock, flags); switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_FALLING: pol = GIC_POL_FALLING_EDGE; @@ -247,7 +247,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) else irq_set_chip_handler_name_locked(d, &gic_level_irq_controller, handle_level_irq, NULL); - spin_unlock_irqrestore(&gic_lock, flags); + raw_spin_unlock_irqrestore(&gic_lock, flags); return 0; } @@ -265,7 +265,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, return -EINVAL; /* Assumption : cpumask refers to a single CPU */ - spin_lock_irqsave(&gic_lock, flags); + raw_spin_lock_irqsave(&gic_lock, flags); /* Re-route this IRQ */ write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); @@ -276,7 +276,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); irq_data_update_effective_affinity(d, cpumask_of(cpu)); - spin_unlock_irqrestore(&gic_lock, flags); + raw_spin_unlock_irqrestore(&gic_lock, flags); return IRQ_SET_MASK_OK; } @@ -354,12 +354,12 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d) cd = irq_data_get_irq_chip_data(d); cd->mask = false; - spin_lock_irqsave(&gic_lock, flags); + raw_spin_lock_irqsave(&gic_lock, flags); for_each_online_cpu(cpu) { write_gic_vl_other(mips_cm_vp_id(cpu)); write_gic_vo_rmask(BIT(intr)); } - spin_unlock_irqrestore(&gic_lock, flags); + raw_spin_unlock_irqrestore(&gic_lock, flags); } static void gic_unmask_local_irq_all_vpes(struct irq_data *d) @@ -372,32 +372,45 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d) cd = irq_data_get_irq_chip_data(d); cd->mask = true; - spin_lock_irqsave(&gic_lock, flags); + raw_spin_lock_irqsave(&gic_lock, flags); for_each_online_cpu(cpu) { write_gic_vl_other(mips_cm_vp_id(cpu)); write_gic_vo_smask(BIT(intr)); } - spin_unlock_irqrestore(&gic_lock, flags); + raw_spin_unlock_irqrestore(&gic_lock, flags); } -static void gic_all_vpes_irq_cpu_online(struct irq_data *d) +static void gic_all_vpes_irq_cpu_online(void) { - struct gic_all_vpes_chip_data *cd; - unsigned int intr; + static const unsigned int local_intrs[] = { + GIC_LOCAL_INT_TIMER, + GIC_LOCAL_INT_PERFCTR, + GIC_LOCAL_INT_FDC, + }; + unsigned long flags; + int i; - intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); - cd = irq_data_get_irq_chip_data(d); + raw_spin_lock_irqsave(&gic_lock, flags); - write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map); - if (cd->mask) - write_gic_vl_smask(BIT(intr)); + for (i = 0; i < ARRAY_SIZE(local_intrs); i++) { + unsigned int intr = local_intrs[i]; + struct gic_all_vpes_chip_data *cd; + + if (!gic_local_irq_is_routable(intr)) + continue; + cd = &gic_all_vpes_chip_data[intr]; + write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map); + if (cd->mask) + write_gic_vl_smask(BIT(intr)); + } + + raw_spin_unlock_irqrestore(&gic_lock, flags); } static struct irq_chip gic_all_vpes_local_irq_controller = { .name = "MIPS GIC Local", .irq_mask = gic_mask_local_irq_all_vpes, .irq_unmask = gic_unmask_local_irq_all_vpes, - .irq_cpu_online = gic_all_vpes_irq_cpu_online, }; static void __gic_irq_dispatch(void) @@ -421,11 +434,11 @@ static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, data = irq_get_irq_data(virq); - spin_lock_irqsave(&gic_lock, flags); + raw_spin_lock_irqsave(&gic_lock, flags); write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); irq_data_update_effective_affinity(data, cpumask_of(cpu)); - spin_unlock_irqrestore(&gic_lock, flags); + raw_spin_unlock_irqrestore(&gic_lock, flags); return 0; } @@ -476,6 +489,10 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, intr = GIC_HWIRQ_TO_LOCAL(hwirq); map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin; + /* + * If adding support for more per-cpu interrupts, keep the the + * array in gic_all_vpes_irq_cpu_online() in sync. + */ switch (intr) { case GIC_LOCAL_INT_TIMER: /* CONFIG_MIPS_CMP workaround (see __gic_init) */ @@ -514,12 +531,12 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, if (!gic_local_irq_is_routable(intr)) return -EPERM; - spin_lock_irqsave(&gic_lock, flags); + raw_spin_lock_irqsave(&gic_lock, flags); for_each_online_cpu(cpu) { write_gic_vl_other(mips_cm_vp_id(cpu)); write_gic_vo_map(mips_gic_vx_map_reg(intr), map); } - spin_unlock_irqrestore(&gic_lock, flags); + raw_spin_unlock_irqrestore(&gic_lock, flags); return 0; } @@ -662,8 +679,8 @@ static int gic_cpu_startup(unsigned int cpu) /* Clear all local IRQ masks (ie. disable all local interrupts) */ write_gic_vl_rmask(~0); - /* Invoke irq_cpu_online callbacks to enable desired interrupts */ - irq_cpu_online(); + /* Enable desired interrupts */ + gic_all_vpes_irq_cpu_online(); return 0; } diff --git a/drivers/irqchip/irq-mvebu-gicp.c b/drivers/irqchip/irq-mvebu-gicp.c index 3be5c5dba1dab0a503b07dd3274d9eebbeabf5aa..5caec411059f53d4318e3d4b1523d54cd34c1efb 100644 --- a/drivers/irqchip/irq-mvebu-gicp.c +++ b/drivers/irqchip/irq-mvebu-gicp.c @@ -223,6 +223,7 @@ static int mvebu_gicp_probe(struct platform_device *pdev) } parent_domain = irq_find_host(irq_parent_dn); + of_node_put(irq_parent_dn); if (!parent_domain) { dev_err(&pdev->dev, "failed to find parent IRQ domain\n"); return -ENODEV; diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c index f605470855f193e0cfc23d04b53dde86c1db4e21..ed7346fb687bfeb1a65c90d9862533a64b177dd6 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -365,6 +365,7 @@ static const struct irq_domain_ops irq_exti_domain_ops = { .map = irq_map_generic_chip, .alloc = stm32_exti_alloc, .free = stm32_exti_free, + .xlate = irq_domain_xlate_twocell, }; static void stm32_irq_ack(struct irq_data *d) diff --git a/drivers/isdn/mISDN/dsp.h b/drivers/isdn/mISDN/dsp.h index fa09d511a8eda23cfc65ac42c1a998659584d559..baf31258f5c900654565da9f9659bee9e900a412 100644 --- a/drivers/isdn/mISDN/dsp.h +++ b/drivers/isdn/mISDN/dsp.h @@ -247,7 +247,7 @@ extern void dsp_cmx_hardware(struct dsp_conf *conf, struct dsp *dsp); extern int dsp_cmx_conf(struct dsp *dsp, u32 conf_id); extern void dsp_cmx_receive(struct dsp *dsp, struct sk_buff *skb); extern void dsp_cmx_hdlc(struct dsp *dsp, struct sk_buff *skb); -extern void dsp_cmx_send(void *arg); +extern void dsp_cmx_send(struct timer_list *arg); extern void dsp_cmx_transmit(struct dsp *dsp, struct sk_buff *skb); extern int dsp_cmx_del_conf_member(struct dsp *dsp); extern int dsp_cmx_del_conf(struct dsp_conf *conf); diff --git a/drivers/isdn/mISDN/dsp_cmx.c b/drivers/isdn/mISDN/dsp_cmx.c index d4b6f01a3f0eac4103b7961033a35d0273612ce7..23a8e93d26c0322fc46acd57fe04741b929f0985 100644 --- a/drivers/isdn/mISDN/dsp_cmx.c +++ b/drivers/isdn/mISDN/dsp_cmx.c @@ -1625,7 +1625,7 @@ static u16 dsp_count; /* last sample count */ static int dsp_count_valid; /* if we have last sample count */ void -dsp_cmx_send(void *arg) +dsp_cmx_send(struct timer_list *arg) { struct dsp_conf *conf; struct dsp_conf_member *member; diff --git a/drivers/isdn/mISDN/dsp_core.c b/drivers/isdn/mISDN/dsp_core.c index cd036e87335a6ada9537eb08a842a5a1f3ca6d57..c3f8bf82f78ebc96deda7c541b4ed86ca2aaba48 100644 --- a/drivers/isdn/mISDN/dsp_core.c +++ b/drivers/isdn/mISDN/dsp_core.c @@ -1202,7 +1202,7 @@ static int __init dsp_init(void) } /* set sample timer */ - timer_setup(&dsp_spl_tl, (void *)dsp_cmx_send, 0); + timer_setup(&dsp_spl_tl, dsp_cmx_send, 0); dsp_spl_tl.expires = jiffies + dsp_tics; dsp_spl_jiffies = dsp_spl_tl.expires; add_timer(&dsp_spl_tl); diff --git a/drivers/leds/leds-pwm.c b/drivers/leds/leds-pwm.c index 807070a33252399c46b4c6107f54426e02248c31..6016b676e11622a3dab7d818905784ec05773d93 100644 --- a/drivers/leds/leds-pwm.c +++ b/drivers/leds/leds-pwm.c @@ -41,9 +41,8 @@ struct led_pwm_data { struct pwm_device *pwm; struct pwm_setting pwm_setting; struct led_setting led_setting; + struct pwm_state pwmstate; unsigned int active_low; - unsigned int period; - int duty; bool blinking; }; @@ -156,38 +155,23 @@ static int led_pwm_blink_set(struct led_classdev *led_cdev, return rc; } -static void __led_pwm_set(struct led_pwm_data *led_data) -{ - int new_duty = led_data->duty; - - pwm_config(led_data->pwm, new_duty, led_data->period); - - if (new_duty == 0) - pwm_disable(led_data->pwm); - else - pwm_enable(led_data->pwm); -} - static int led_pwm_set(struct led_classdev *led_cdev, enum led_brightness brightness) { struct led_pwm_data *led_data = container_of(led_cdev, struct led_pwm_data, cdev); unsigned int max = led_data->cdev.max_brightness; - unsigned long long duty = led_data->period; + unsigned long long duty = led_data->pwmstate.period; duty *= brightness; do_div(duty, max); if (led_data->active_low) - duty = led_data->period - duty; - - led_data->duty = duty; - led_data->blinking = false; - - __led_pwm_set(led_data); + duty = led_data->pwmstate.period - duty; - return 0; + led_data->pwmstate.duty_cycle = duty; + led_data->pwmstate.enabled = true; + return pwm_apply_state(led_data->pwm, &led_data->pwmstate); } static inline size_t sizeof_pwm_leds_priv(int num_leds) @@ -206,7 +190,6 @@ static int led_pwm_add(struct device *dev, struct led_pwm_priv *priv, struct led_pwm *led, struct device_node *child) { struct led_pwm_data *led_data = &priv->leds[priv->num_leds]; - struct pwm_args pargs; int ret; led_data->active_low = led->active_low; @@ -232,17 +215,10 @@ static int led_pwm_add(struct device *dev, struct led_pwm_priv *priv, led_data->cdev.brightness_set_blocking = led_pwm_set; led_data->cdev.blink_set = led_pwm_blink_set; - /* - * FIXME: pwm_apply_args() should be removed when switching to the - * atomic PWM API. - */ - pwm_apply_args(led_data->pwm); - - pwm_get_args(led_data->pwm, &pargs); + pwm_init_state(led_data->pwm, &led_data->pwmstate); - led_data->period = pargs.period; - if (!led_data->period && (led->pwm_period_ns > 0)) - led_data->period = led->pwm_period_ns; + if (!led_data->pwmstate.period) + led_data->pwmstate.period = led->pwm_period_ns; ret = led_classdev_register(dev, &led_data->cdev); if (ret == 0) { diff --git a/drivers/leds/trigger/ledtrig-cpu.c b/drivers/leds/trigger/ledtrig-cpu.c index 66a6260919367b741c76430b9d3695406fa8fce0..19e068cadedfb2ca84f338ce5b131a0b183aedef 100644 --- a/drivers/leds/trigger/ledtrig-cpu.c +++ b/drivers/leds/trigger/ledtrig-cpu.c @@ -1,14 +1,18 @@ /* * ledtrig-cpu.c - LED trigger based on CPU activity * - * This LED trigger will be registered for each possible CPU and named as - * cpu0, cpu1, cpu2, cpu3, etc. + * This LED trigger will be registered for first 8 CPUs and named + * as cpu0..cpu7. There's additional trigger called cpu that + * is on when any CPU is active. + * + * If you want support for arbitrary number of CPUs, make it one trigger, + * with additional sysfs file selecting which CPU to watch. * * It can be bound to any LED just like other triggers using either a * board file or via sysfs interface. * * An API named ledtrig_cpu is exported for any user, who want to add CPU - * activity indication in their code + * activity indication in their code. * * Copyright 2011 Linus Walleij * Copyright 2011 - 2012 Bryan Wu @@ -130,7 +134,7 @@ static int ledtrig_prepare_down_cpu(unsigned int cpu) static int __init ledtrig_cpu_init(void) { - int cpu; + unsigned int cpu; int ret; /* Supports up to 9999 cpu cores */ @@ -149,7 +153,10 @@ static int __init ledtrig_cpu_init(void) for_each_possible_cpu(cpu) { struct led_trigger_cpu *trig = &per_cpu(cpu_trig, cpu); - snprintf(trig->name, MAX_NAME_LEN, "cpu%d", cpu); + if (cpu >= 8) + continue; + + snprintf(trig->name, MAX_NAME_LEN, "cpu%u", cpu); led_trigger_register_simple(trig->name, &trig->_trig); } diff --git a/drivers/macintosh/Kconfig b/drivers/macintosh/Kconfig index a316624742f68f6863ba970c6fce45867aab03c9..c3d421c7b0cf1c5d0c7c4d444c028d2ceb2645bc 100644 --- a/drivers/macintosh/Kconfig +++ b/drivers/macintosh/Kconfig @@ -83,6 +83,7 @@ config ADB_PMU_LED config ADB_PMU_LED_DISK bool "Use front LED as DISK LED by default" + depends on ATA depends on ADB_PMU_LED depends on LEDS_CLASS select LEDS_TRIGGERS diff --git a/drivers/macintosh/windfarm_lm75_sensor.c b/drivers/macintosh/windfarm_lm75_sensor.c index f48ad2445ed609ef3dbf63159fece5984ffa1f2e..f5b1ac8347db787e2826b49dae8bf56289e2f91c 100644 --- a/drivers/macintosh/windfarm_lm75_sensor.c +++ b/drivers/macintosh/windfarm_lm75_sensor.c @@ -35,8 +35,8 @@ #endif struct wf_lm75_sensor { - int ds1775 : 1; - int inited : 1; + unsigned int ds1775 : 1; + unsigned int inited : 1; struct i2c_client *i2c; struct wf_sensor sens; }; diff --git a/drivers/macintosh/windfarm_smu_sat.c b/drivers/macintosh/windfarm_smu_sat.c index 51ef77de4174456e3ec2af7a075d167eb5c776c5..3d4b8c33640a88459ca24c01d8c669e28a8e1031 100644 --- a/drivers/macintosh/windfarm_smu_sat.c +++ b/drivers/macintosh/windfarm_smu_sat.c @@ -172,6 +172,7 @@ static void wf_sat_release(struct kref *ref) if (sat->nr >= 0) sats[sat->nr] = NULL; + of_node_put(sat->node); kfree(sat); } diff --git a/drivers/macintosh/windfarm_smu_sensors.c b/drivers/macintosh/windfarm_smu_sensors.c index 172fd267dcf6071cf892a558f118e47d1646f34c..0f4017a8189e52397ebba8443873a6813ec25cc6 100644 --- a/drivers/macintosh/windfarm_smu_sensors.c +++ b/drivers/macintosh/windfarm_smu_sensors.c @@ -275,8 +275,8 @@ struct smu_cpu_power_sensor { struct list_head link; struct wf_sensor *volts; struct wf_sensor *amps; - int fake_volts : 1; - int quadratic : 1; + unsigned int fake_volts : 1; + unsigned int quadratic : 1; struct wf_sensor sens; }; #define to_smu_cpu_power(c) container_of(c, struct smu_cpu_power_sensor, sens) diff --git a/drivers/mailbox/mailbox-test.c b/drivers/mailbox/mailbox-test.c index 129b3656c453a68eb295b859baac6a26eac86a65..39236030079e074fc99078d97c13b557eda1e6c8 100644 --- a/drivers/mailbox/mailbox-test.c +++ b/drivers/mailbox/mailbox-test.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -43,6 +44,7 @@ struct mbox_test_device { char *signal; char *message; spinlock_t lock; + struct mutex mutex; wait_queue_head_t waitq; struct fasync_struct *async_queue; }; @@ -99,6 +101,7 @@ static ssize_t mbox_test_message_write(struct file *filp, size_t count, loff_t *ppos) { struct mbox_test_device *tdev = filp->private_data; + char *message; void *data; int ret; @@ -114,10 +117,13 @@ static ssize_t mbox_test_message_write(struct file *filp, return -EINVAL; } - tdev->message = kzalloc(MBOX_MAX_MSG_LEN, GFP_KERNEL); - if (!tdev->message) + message = kzalloc(MBOX_MAX_MSG_LEN, GFP_KERNEL); + if (!message) return -ENOMEM; + mutex_lock(&tdev->mutex); + + tdev->message = message; ret = copy_from_user(tdev->message, userbuf, count); if (ret) { ret = -EFAULT; @@ -148,6 +154,8 @@ static ssize_t mbox_test_message_write(struct file *filp, kfree(tdev->message); tdev->signal = NULL; + mutex_unlock(&tdev->mutex); + return ret < 0 ? ret : count; } @@ -396,6 +404,7 @@ static int mbox_test_probe(struct platform_device *pdev) platform_set_drvdata(pdev, tdev); spin_lock_init(&tdev->lock); + mutex_init(&tdev->mutex); if (tdev->rx_channel) { tdev->rx_buffer = devm_kzalloc(&pdev->dev, diff --git a/drivers/mailbox/ti-msgmgr.c b/drivers/mailbox/ti-msgmgr.c index 01e9e462512b78cb06f85a2fdb4816ffa558841b..eb1e9771037f2a558ff84311295f717ebe7b997a 100644 --- a/drivers/mailbox/ti-msgmgr.c +++ b/drivers/mailbox/ti-msgmgr.c @@ -385,14 +385,20 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data) /* Ensure all unused data is 0 */ data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes)); writel(data_trail, data_reg); - data_reg++; + data_reg += sizeof(u32); } + /* * 'data_reg' indicates next register to write. If we did not already * write on tx complete reg(last reg), we must do so for transmit + * In addition, we also need to make sure all intermediate data + * registers(if any required), are reset to 0 for TISCI backward + * compatibility to be maintained. */ - if (data_reg <= qinst->queue_buff_end) - writel(0, qinst->queue_buff_end); + while (data_reg <= qinst->queue_buff_end) { + writel(0, data_reg); + data_reg += sizeof(u32); + } return 0; } diff --git a/drivers/mcb/mcb-core.c b/drivers/mcb/mcb-core.c index 7fd32b0183dc106e556d927ffed5d8addbfc99d0..c8c6d217aaa94080e5495f08b0ca84bedb0fcc48 100644 --- a/drivers/mcb/mcb-core.c +++ b/drivers/mcb/mcb-core.c @@ -251,6 +251,7 @@ int mcb_device_register(struct mcb_bus *bus, struct mcb_device *dev) return 0; out: + put_device(&dev->dev); return ret; } @@ -392,17 +393,13 @@ EXPORT_SYMBOL_GPL(mcb_free_dev); static int __mcb_bus_add_devices(struct device *dev, void *data) { - struct mcb_device *mdev = to_mcb_device(dev); int retval; - if (mdev->is_added) - return 0; - retval = device_attach(dev); - if (retval < 0) + if (retval < 0) { dev_err(dev, "Error adding device (%d)\n", retval); - - mdev->is_added = true; + return retval; + } return 0; } diff --git a/drivers/mcb/mcb-lpc.c b/drivers/mcb/mcb-lpc.c index 945091a8835465c1aa2313890fcbd32d2ec4b6f4..7d292acbba53953eff42341dad5223de51c7e16d 100644 --- a/drivers/mcb/mcb-lpc.c +++ b/drivers/mcb/mcb-lpc.c @@ -26,7 +26,7 @@ static int mcb_lpc_probe(struct platform_device *pdev) { struct resource *res; struct priv *priv; - int ret = 0; + int ret = 0, table_size; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -61,16 +61,43 @@ static int mcb_lpc_probe(struct platform_device *pdev) ret = chameleon_parse_cells(priv->bus, priv->mem->start, priv->base); if (ret < 0) { - mcb_release_bus(priv->bus); - return ret; + goto out_mcb_bus; } - dev_dbg(&pdev->dev, "Found %d cells\n", ret); + table_size = ret; + + if (table_size < CHAM_HEADER_SIZE) { + /* Release the previous resources */ + devm_iounmap(&pdev->dev, priv->base); + devm_release_mem_region(&pdev->dev, priv->mem->start, resource_size(priv->mem)); + + /* Then, allocate it again with the actual chameleon table size */ + res = devm_request_mem_region(&pdev->dev, priv->mem->start, + table_size, + KBUILD_MODNAME); + if (!res) { + dev_err(&pdev->dev, "Failed to request PCI memory\n"); + ret = -EBUSY; + goto out_mcb_bus; + } + + priv->base = devm_ioremap(&pdev->dev, priv->mem->start, table_size); + if (!priv->base) { + dev_err(&pdev->dev, "Cannot ioremap\n"); + ret = -ENOMEM; + goto out_mcb_bus; + } + + platform_set_drvdata(pdev, priv); + } mcb_bus_add_devices(priv->bus); return 0; +out_mcb_bus: + mcb_release_bus(priv->bus); + return ret; } static int mcb_lpc_remove(struct platform_device *pdev) diff --git a/drivers/mcb/mcb-parse.c b/drivers/mcb/mcb-parse.c index 3636349648b4f0e15cfbec120575c9428472ca3f..6bb6be4bb40ab58f24030c0769b77dd5ff5c0792 100644 --- a/drivers/mcb/mcb-parse.c +++ b/drivers/mcb/mcb-parse.c @@ -98,8 +98,6 @@ static int chameleon_parse_gdd(struct mcb_bus *bus, mdev->mem.end = mdev->mem.start + size - 1; mdev->mem.flags = IORESOURCE_MEM; - mdev->is_added = false; - ret = mcb_device_register(bus, mdev); if (ret < 0) goto err; @@ -107,7 +105,7 @@ static int chameleon_parse_gdd(struct mcb_bus *bus, return 0; err: - put_device(&mdev->dev); + mcb_free_dev(mdev); return ret; } @@ -129,7 +127,7 @@ static void chameleon_parse_bar(void __iomem *base, } } -static int chameleon_get_bar(char __iomem **base, phys_addr_t mapbase, +static int chameleon_get_bar(void __iomem **base, phys_addr_t mapbase, struct chameleon_bar **cb) { struct chameleon_bar *c; @@ -178,12 +176,13 @@ int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase, { struct chameleon_fpga_header *header; struct chameleon_bar *cb; - char __iomem *p = base; + void __iomem *p = base; int num_cells = 0; uint32_t dtype; int bar_count; int ret; u32 hsize; + u32 table_size; hsize = sizeof(struct chameleon_fpga_header); @@ -238,12 +237,16 @@ int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase, num_cells++; } - if (num_cells == 0) - num_cells = -EINVAL; + if (num_cells == 0) { + ret = -EINVAL; + goto free_bar; + } + table_size = p - base; + pr_debug("%d cell(s) found. Chameleon table size: 0x%04x bytes\n", num_cells, table_size); kfree(cb); kfree(header); - return num_cells; + return table_size; free_bar: kfree(cb); diff --git a/drivers/mcb/mcb-pci.c b/drivers/mcb/mcb-pci.c index c2d69e33bf2bfc1d16780f90802bf4695f699013..63879d89c8c4935efcc7427d49fa4724e7411851 100644 --- a/drivers/mcb/mcb-pci.c +++ b/drivers/mcb/mcb-pci.c @@ -34,7 +34,7 @@ static int mcb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct resource *res; struct priv *priv; - int ret; + int ret, table_size; unsigned long flags; priv = devm_kzalloc(&pdev->dev, sizeof(struct priv), GFP_KERNEL); @@ -93,7 +93,30 @@ static int mcb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (ret < 0) goto out_mcb_bus; - dev_dbg(&pdev->dev, "Found %d cells\n", ret); + table_size = ret; + + if (table_size < CHAM_HEADER_SIZE) { + /* Release the previous resources */ + devm_iounmap(&pdev->dev, priv->base); + devm_release_mem_region(&pdev->dev, priv->mapbase, CHAM_HEADER_SIZE); + + /* Then, allocate it again with the actual chameleon table size */ + res = devm_request_mem_region(&pdev->dev, priv->mapbase, + table_size, + KBUILD_MODNAME); + if (!res) { + dev_err(&pdev->dev, "Failed to request PCI memory\n"); + ret = -EBUSY; + goto out_mcb_bus; + } + + priv->base = devm_ioremap(&pdev->dev, priv->mapbase, table_size); + if (!priv->base) { + dev_err(&pdev->dev, "Cannot ioremap\n"); + ret = -ENOMEM; + goto out_mcb_bus; + } + } mcb_bus_add_devices(priv->bus); diff --git a/drivers/md/bcache/alloc.c b/drivers/md/bcache/alloc.c index 46794cac167e7e32eb40cf7c9a158fbbe59993df..5310e1f4a2826b9a69d6ce534e5760b160dcd1df 100644 --- a/drivers/md/bcache/alloc.c +++ b/drivers/md/bcache/alloc.c @@ -49,7 +49,7 @@ * * bch_bucket_alloc() allocates a single bucket from a specific cache. * - * bch_bucket_alloc_set() allocates one or more buckets from different caches + * bch_bucket_alloc_set() allocates one bucket from different caches * out of a cache set. * * free_some_buckets() drives all the processes described above. It's called @@ -488,34 +488,29 @@ void bch_bucket_free(struct cache_set *c, struct bkey *k) } int __bch_bucket_alloc_set(struct cache_set *c, unsigned int reserve, - struct bkey *k, int n, bool wait) + struct bkey *k, bool wait) { - int i; + struct cache *ca; + long b; /* No allocation if CACHE_SET_IO_DISABLE bit is set */ if (unlikely(test_bit(CACHE_SET_IO_DISABLE, &c->flags))) return -1; lockdep_assert_held(&c->bucket_lock); - BUG_ON(!n || n > c->caches_loaded || n > 8); bkey_init(k); - /* sort by free space/prio of oldest data in caches */ - - for (i = 0; i < n; i++) { - struct cache *ca = c->cache_by_alloc[i]; - long b = bch_bucket_alloc(ca, reserve, wait); + ca = c->cache_by_alloc[0]; + b = bch_bucket_alloc(ca, reserve, wait); + if (b == -1) + goto err; - if (b == -1) - goto err; + k->ptr[0] = MAKE_PTR(ca->buckets[b].gen, + bucket_to_sector(c, b), + ca->sb.nr_this_dev); - k->ptr[i] = MAKE_PTR(ca->buckets[b].gen, - bucket_to_sector(c, b), - ca->sb.nr_this_dev); - - SET_KEY_PTRS(k, i + 1); - } + SET_KEY_PTRS(k, 1); return 0; err: @@ -525,12 +520,12 @@ int __bch_bucket_alloc_set(struct cache_set *c, unsigned int reserve, } int bch_bucket_alloc_set(struct cache_set *c, unsigned int reserve, - struct bkey *k, int n, bool wait) + struct bkey *k, bool wait) { int ret; mutex_lock(&c->bucket_lock); - ret = __bch_bucket_alloc_set(c, reserve, k, n, wait); + ret = __bch_bucket_alloc_set(c, reserve, k, wait); mutex_unlock(&c->bucket_lock); return ret; } @@ -638,7 +633,7 @@ bool bch_alloc_sectors(struct cache_set *c, spin_unlock(&c->data_bucket_lock); - if (bch_bucket_alloc_set(c, watermark, &alloc.key, 1, wait)) + if (bch_bucket_alloc_set(c, watermark, &alloc.key, wait)) return false; spin_lock(&c->data_bucket_lock); diff --git a/drivers/md/bcache/bcache.h b/drivers/md/bcache/bcache.h index 6a380ed4919a09c9815519326b3010374e173640..e81d7831098470ae1de628591a67124530b2f470 100644 --- a/drivers/md/bcache/bcache.h +++ b/drivers/md/bcache/bcache.h @@ -952,9 +952,9 @@ void bch_bucket_free(struct cache_set *c, struct bkey *k); long bch_bucket_alloc(struct cache *ca, unsigned int reserve, bool wait); int __bch_bucket_alloc_set(struct cache_set *c, unsigned int reserve, - struct bkey *k, int n, bool wait); + struct bkey *k, bool wait); int bch_bucket_alloc_set(struct cache_set *c, unsigned int reserve, - struct bkey *k, int n, bool wait); + struct bkey *k, bool wait); bool bch_alloc_sectors(struct cache_set *c, struct bkey *k, unsigned int sectors, unsigned int write_point, unsigned int write_prio, bool wait); diff --git a/drivers/md/bcache/btree.c b/drivers/md/bcache/btree.c index e388e7bb7b5db8679428e1a55f924f16271cc4f3..71d670934a07e876d1f1bac4fe0c6f11a8134b62 100644 --- a/drivers/md/bcache/btree.c +++ b/drivers/md/bcache/btree.c @@ -1125,11 +1125,13 @@ struct btree *__bch_btree_node_alloc(struct cache_set *c, struct btree_op *op, struct btree *parent) { BKEY_PADDED(key) k; - struct btree *b = ERR_PTR(-EAGAIN); + struct btree *b; mutex_lock(&c->bucket_lock); retry: - if (__bch_bucket_alloc_set(c, RESERVE_BTREE, &k.key, 1, wait)) + /* return ERR_PTR(-EAGAIN) when it fails */ + b = ERR_PTR(-EAGAIN); + if (__bch_bucket_alloc_set(c, RESERVE_BTREE, &k.key, wait)) goto err; bkey_put(c, &k.key); @@ -1174,7 +1176,7 @@ static struct btree *btree_node_alloc_replacement(struct btree *b, { struct btree *n = bch_btree_node_alloc(b->c, op, b->level, b->parent); - if (!IS_ERR_OR_NULL(n)) { + if (!IS_ERR(n)) { mutex_lock(&n->write_lock); bch_btree_sort_into(&b->keys, &n->keys, &b->c->sort); bkey_copy_key(&n->key, &b->key); @@ -1377,7 +1379,7 @@ static int btree_gc_coalesce(struct btree *b, struct btree_op *op, memset(new_nodes, 0, sizeof(new_nodes)); closure_init_stack(&cl); - while (nodes < GC_MERGE_NODES && !IS_ERR_OR_NULL(r[nodes].b)) + while (nodes < GC_MERGE_NODES && !IS_ERR(r[nodes].b)) keys += r[nodes++].keys; blocks = btree_default_blocks(b->c) * 2 / 3; @@ -1389,7 +1391,7 @@ static int btree_gc_coalesce(struct btree *b, struct btree_op *op, for (i = 0; i < nodes; i++) { new_nodes[i] = btree_node_alloc_replacement(r[i].b, NULL); - if (IS_ERR_OR_NULL(new_nodes[i])) + if (IS_ERR(new_nodes[i])) goto out_nocoalesce; } @@ -1524,7 +1526,7 @@ static int btree_gc_coalesce(struct btree *b, struct btree_op *op, atomic_dec(&b->c->prio_blocked); for (i = 0; i < nodes; i++) - if (!IS_ERR_OR_NULL(new_nodes[i])) { + if (!IS_ERR(new_nodes[i])) { btree_node_free(new_nodes[i]); rw_unlock(true, new_nodes[i]); } @@ -1706,7 +1708,7 @@ static int bch_btree_gc_root(struct btree *b, struct btree_op *op, if (should_rewrite) { n = btree_node_alloc_replacement(b, NULL); - if (!IS_ERR_OR_NULL(n)) { + if (!IS_ERR(n)) { bch_btree_node_write_sync(n); bch_btree_set_root(n); diff --git a/drivers/md/bcache/super.c b/drivers/md/bcache/super.c index 2df75db52e917576dfc448b0f7fae424f11f8c41..4b076f7f184be493a6c95cbe96449692626c211e 100644 --- a/drivers/md/bcache/super.c +++ b/drivers/md/bcache/super.c @@ -423,7 +423,7 @@ static int __uuid_write(struct cache_set *c) closure_init_stack(&cl); lockdep_assert_held(&bch_register_lock); - if (bch_bucket_alloc_set(c, RESERVE_BTREE, &k.key, 1, true)) + if (bch_bucket_alloc_set(c, RESERVE_BTREE, &k.key, true)) return 1; SET_KEY_SIZE(&k.key, c->sb.bucket_size); @@ -1576,7 +1576,7 @@ static void cache_set_flush(struct closure *cl) if (!IS_ERR_OR_NULL(c->gc_thread)) kthread_stop(c->gc_thread); - if (!IS_ERR_OR_NULL(c->root)) + if (!IS_ERR(c->root)) list_add(&c->root->list, &c->btree_cache); /* Should skip this if we're unregistering because of an error */ @@ -1921,7 +1921,7 @@ static int run_cache_set(struct cache_set *c) err = "cannot allocate new btree root"; c->root = __bch_btree_node_alloc(c, NULL, 0, true, NULL); - if (IS_ERR_OR_NULL(c->root)) + if (IS_ERR(c->root)) goto err; mutex_lock(&c->root->write_lock); diff --git a/drivers/md/dm-cache-policy-smq.c b/drivers/md/dm-cache-policy-smq.c index 1b5b9ad9e492f30357990cf60878e76d03d51066..6030193b216ebeb6c9fb4a11e33189579b473b59 100644 --- a/drivers/md/dm-cache-policy-smq.c +++ b/drivers/md/dm-cache-policy-smq.c @@ -854,7 +854,13 @@ struct smq_policy { struct background_tracker *bg_work; - bool migrations_allowed; + bool migrations_allowed:1; + + /* + * If this is set the policy will try and clean the whole cache + * even if the device is not idle. + */ + bool cleaner:1; }; /*----------------------------------------------------------------*/ @@ -1133,7 +1139,7 @@ static bool clean_target_met(struct smq_policy *mq, bool idle) * Cache entries may not be populated. So we cannot rely on the * size of the clean queue. */ - if (idle) { + if (idle || mq->cleaner) { /* * We'd like to clean everything. */ @@ -1716,11 +1722,9 @@ static void calc_hotspot_params(sector_t origin_size, *hotspot_block_size /= 2u; } -static struct dm_cache_policy *__smq_create(dm_cblock_t cache_size, - sector_t origin_size, - sector_t cache_block_size, - bool mimic_mq, - bool migrations_allowed) +static struct dm_cache_policy * +__smq_create(dm_cblock_t cache_size, sector_t origin_size, sector_t cache_block_size, + bool mimic_mq, bool migrations_allowed, bool cleaner) { unsigned i; unsigned nr_sentinels_per_queue = 2u * NR_CACHE_LEVELS; @@ -1807,6 +1811,7 @@ static struct dm_cache_policy *__smq_create(dm_cblock_t cache_size, goto bad_btracker; mq->migrations_allowed = migrations_allowed; + mq->cleaner = cleaner; return &mq->policy; @@ -1830,21 +1835,24 @@ static struct dm_cache_policy *smq_create(dm_cblock_t cache_size, sector_t origin_size, sector_t cache_block_size) { - return __smq_create(cache_size, origin_size, cache_block_size, false, true); + return __smq_create(cache_size, origin_size, cache_block_size, + false, true, false); } static struct dm_cache_policy *mq_create(dm_cblock_t cache_size, sector_t origin_size, sector_t cache_block_size) { - return __smq_create(cache_size, origin_size, cache_block_size, true, true); + return __smq_create(cache_size, origin_size, cache_block_size, + true, true, false); } static struct dm_cache_policy *cleaner_create(dm_cblock_t cache_size, sector_t origin_size, sector_t cache_block_size) { - return __smq_create(cache_size, origin_size, cache_block_size, false, false); + return __smq_create(cache_size, origin_size, cache_block_size, + false, false, true); } /*----------------------------------------------------------------*/ diff --git a/drivers/md/dm-cache-target.c b/drivers/md/dm-cache-target.c index df7bc45bc0cedee831b296b1d02a84f6c606724d..b3371812a215841a22ea07e3ce09d4f40f5a18ea 100644 --- a/drivers/md/dm-cache-target.c +++ b/drivers/md/dm-cache-target.c @@ -1905,6 +1905,7 @@ static void process_deferred_bios(struct work_struct *ws) else commit_needed = process_bio(cache, bio) || commit_needed; + cond_resched(); } if (commit_needed) @@ -1927,6 +1928,7 @@ static void requeue_deferred_bios(struct cache *cache) while ((bio = bio_list_pop(&bios))) { bio->bi_status = BLK_STS_DM_REQUEUE; bio_endio(bio); + cond_resched(); } } @@ -1967,6 +1969,8 @@ static void check_migrations(struct work_struct *ws) r = mg_start(cache, op, NULL); if (r) break; + + cond_resched(); } } diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c index 4b6a74db1d85656f8f2d7d48afe84df0485f6466..a8bbfd46cc624a6cd806117113a287db12dc1754 100644 --- a/drivers/md/dm-crypt.c +++ b/drivers/md/dm-crypt.c @@ -1661,6 +1661,7 @@ static int dmcrypt_write(void *data) io = crypt_io_from_node(rb_first(&write_tree)); rb_erase(&io->rb_node, &write_tree); kcryptd_io_write(io); + cond_resched(); } while (!RB_EMPTY_ROOT(&write_tree)); blk_finish_plug(&plug); } diff --git a/drivers/md/dm-flakey.c b/drivers/md/dm-flakey.c index 2fcf62fb2844f467326c653ae20f59caf4b9d8b8..5116856ea81dd8e81f684b1b6f659bd90f2d93da 100644 --- a/drivers/md/dm-flakey.c +++ b/drivers/md/dm-flakey.c @@ -124,9 +124,9 @@ static int parse_features(struct dm_arg_set *as, struct flakey_c *fc, * Direction r or w? */ arg_name = dm_shift_arg(as); - if (!strcasecmp(arg_name, "w")) + if (arg_name && !strcasecmp(arg_name, "w")) fc->corrupt_bio_rw = WRITE; - else if (!strcasecmp(arg_name, "r")) + else if (arg_name && !strcasecmp(arg_name, "r")) fc->corrupt_bio_rw = READ; else { ti->error = "Invalid corrupt bio direction (r or w)"; @@ -301,8 +301,11 @@ static void corrupt_bio_data(struct bio *bio, struct flakey_c *fc) */ bio_for_each_segment(bvec, bio, iter) { if (bio_iter_len(bio, iter) > corrupt_bio_byte) { - char *segment = (page_address(bio_iter_page(bio, iter)) - + bio_iter_offset(bio, iter)); + char *segment; + struct page *page = bio_iter_page(bio, iter); + if (unlikely(page == ZERO_PAGE(0))) + break; + segment = (page_address(page) + bio_iter_offset(bio, iter)); segment[corrupt_bio_byte] = fc->corrupt_bio_value; DMDEBUG("Corrupting data bio=%p by writing %u to byte %u " "(rw=%c bi_opf=%u bi_sector=%llu size=%u)\n", @@ -364,9 +367,11 @@ static int flakey_map(struct dm_target *ti, struct bio *bio) /* * Corrupt matching writes. */ - if (fc->corrupt_bio_byte && (fc->corrupt_bio_rw == WRITE)) { - if (all_corrupt_bio_flags_match(bio, fc)) - corrupt_bio_data(bio, fc); + if (fc->corrupt_bio_byte) { + if (fc->corrupt_bio_rw == WRITE) { + if (all_corrupt_bio_flags_match(bio, fc)) + corrupt_bio_data(bio, fc); + } goto map_bio; } @@ -397,13 +402,14 @@ static int flakey_end_io(struct dm_target *ti, struct bio *bio, } if (!*error && pb->bio_submitted && (bio_data_dir(bio) == READ)) { - if (fc->corrupt_bio_byte && (fc->corrupt_bio_rw == READ) && - all_corrupt_bio_flags_match(bio, fc)) { - /* - * Corrupt successful matching READs while in down state. - */ - corrupt_bio_data(bio, fc); - + if (fc->corrupt_bio_byte) { + if ((fc->corrupt_bio_rw == READ) && + all_corrupt_bio_flags_match(bio, fc)) { + /* + * Corrupt successful matching READs while in down state. + */ + corrupt_bio_data(bio, fc); + } } else if (!test_bit(DROP_WRITES, &fc->flags) && !test_bit(ERROR_WRITES, &fc->flags)) { /* diff --git a/drivers/md/dm-integrity.c b/drivers/md/dm-integrity.c index 37b91226a35ec14b04c1f9e9ab4be1b3ba630837..03c212bfd5951572313de006070db362c105ab08 100644 --- a/drivers/md/dm-integrity.c +++ b/drivers/md/dm-integrity.c @@ -29,11 +29,11 @@ #define DEFAULT_BUFFER_SECTORS 128 #define DEFAULT_JOURNAL_WATERMARK 50 #define DEFAULT_SYNC_MSEC 10000 -#define DEFAULT_MAX_JOURNAL_SECTORS 131072 +#define DEFAULT_MAX_JOURNAL_SECTORS (IS_ENABLED(CONFIG_64BIT) ? 131072 : 8192) #define MIN_LOG2_INTERLEAVE_SECTORS 3 #define MAX_LOG2_INTERLEAVE_SECTORS 31 #define METADATA_WORKQUEUE_MAX_ACTIVE 16 -#define RECALC_SECTORS 8192 +#define RECALC_SECTORS (IS_ENABLED(CONFIG_64BIT) ? 32768 : 2048) #define RECALC_WRITE_SUPER 16 /* @@ -3700,11 +3700,13 @@ int __init dm_integrity_init(void) } r = dm_register_target(&integrity_target); - - if (r < 0) + if (r < 0) { DMERR("register failed %d", r); + kmem_cache_destroy(journal_io_cache); + return r; + } - return r; + return 0; } void dm_integrity_exit(void) diff --git a/drivers/md/dm-io.c b/drivers/md/dm-io.c index 81ffc59d05c90e7843747a0d9cd2c33fa0bba41d..4312007d2d34b8307059dd0c33c98ceab5e1d86d 100644 --- a/drivers/md/dm-io.c +++ b/drivers/md/dm-io.c @@ -306,7 +306,7 @@ static void do_region(int op, int op_flags, unsigned region, struct request_queue *q = bdev_get_queue(where->bdev); unsigned short logical_block_size = queue_logical_block_size(q); sector_t num_sectors; - unsigned int uninitialized_var(special_cmd_max_sectors); + unsigned int special_cmd_max_sectors; /* * Reject unsupported discard and write same requests. diff --git a/drivers/md/dm-ioctl.c b/drivers/md/dm-ioctl.c index e61f5d95f6859bed850254c939b356838144a212..ec4e33edc2b897612857ee29a9ce0c7cc68de9a1 100644 --- a/drivers/md/dm-ioctl.c +++ b/drivers/md/dm-ioctl.c @@ -1410,11 +1410,12 @@ static int table_clear(struct file *filp, struct dm_ioctl *param, size_t param_s hc->new_map = NULL; } - param->flags &= ~DM_INACTIVE_PRESENT_FLAG; - - __dev_status(hc->md, param); md = hc->md; up_write(&_hash_lock); + + param->flags &= ~DM_INACTIVE_PRESENT_FLAG; + __dev_status(md, param); + if (old_map) { dm_sync_table(md); dm_table_destroy(old_map); @@ -1821,7 +1822,7 @@ static int ctl_ioctl(struct file *file, uint command, struct dm_ioctl __user *us int ioctl_flags; int param_flags; unsigned int cmd; - struct dm_ioctl *uninitialized_var(param); + struct dm_ioctl *param; ioctl_fn fn = NULL; size_t input_param_size; struct dm_ioctl param_kernel; diff --git a/drivers/md/dm-raid.c b/drivers/md/dm-raid.c index 5c45100f6d53ecc7fc5e2018a08c2dea95e0799a..72aa5097b68ff61933342864966ce3a6a8ace720 100644 --- a/drivers/md/dm-raid.c +++ b/drivers/md/dm-raid.c @@ -3289,15 +3289,19 @@ static int raid_ctr(struct dm_target *ti, unsigned int argc, char **argv) /* Try to adjust the raid4/5/6 stripe cache size to the stripe size */ if (rs_is_raid456(rs)) { r = rs_set_raid456_stripe_cache(rs); - if (r) + if (r) { + mddev_unlock(&rs->md); goto bad_stripe_cache; + } } /* Now do an early reshape check */ if (test_bit(RT_FLAG_RESHAPE_RS, &rs->runtime_flags)) { r = rs_check_reshape(rs); - if (r) + if (r) { + mddev_unlock(&rs->md); goto bad_check_reshape; + } /* Restore new, ctr requested layout to perform check */ rs_config_restore(rs, &rs_layout); @@ -3306,6 +3310,7 @@ static int raid_ctr(struct dm_target *ti, unsigned int argc, char **argv) r = rs->md.pers->check_reshape(&rs->md); if (r) { ti->error = "Reshape check failed"; + mddev_unlock(&rs->md); goto bad_check_reshape; } } diff --git a/drivers/md/dm-snap-persistent.c b/drivers/md/dm-snap-persistent.c index 963d3774c93e287432966b658088914b67f10da3..247089c2be256b54341d08ff9e8c2339be9ecadc 100644 --- a/drivers/md/dm-snap-persistent.c +++ b/drivers/md/dm-snap-persistent.c @@ -613,7 +613,7 @@ static int persistent_read_metadata(struct dm_exception_store *store, chunk_t old, chunk_t new), void *callback_context) { - int r, uninitialized_var(new_snapshot); + int r, new_snapshot; struct pstore *ps = get_info(store); /* diff --git a/drivers/md/dm-stats.c b/drivers/md/dm-stats.c index 3d59f3e208c503ae2bc1914536075b2d6b812ce4..0eb48e739f7ea234e601e8f2f7260bbaa794c192 100644 --- a/drivers/md/dm-stats.c +++ b/drivers/md/dm-stats.c @@ -188,7 +188,7 @@ static int dm_stat_in_flight(struct dm_stat_shared *shared) atomic_read(&shared->in_flight[WRITE]); } -void dm_stats_init(struct dm_stats *stats) +int dm_stats_init(struct dm_stats *stats) { int cpu; struct dm_stats_last_position *last; @@ -196,11 +196,16 @@ void dm_stats_init(struct dm_stats *stats) mutex_init(&stats->mutex); INIT_LIST_HEAD(&stats->list); stats->last = alloc_percpu(struct dm_stats_last_position); + if (!stats->last) + return -ENOMEM; + for_each_possible_cpu(cpu) { last = per_cpu_ptr(stats->last, cpu); last->last_sector = (sector_t)ULLONG_MAX; last->last_rw = UINT_MAX; } + + return 0; } void dm_stats_cleanup(struct dm_stats *stats) diff --git a/drivers/md/dm-stats.h b/drivers/md/dm-stats.h index 2ddfae678f320f84776c772f1107da8eab485385..dcac11fce03bba613da83b35c22db732b19ed8af 100644 --- a/drivers/md/dm-stats.h +++ b/drivers/md/dm-stats.h @@ -22,7 +22,7 @@ struct dm_stats_aux { unsigned long long duration_ns; }; -void dm_stats_init(struct dm_stats *st); +int dm_stats_init(struct dm_stats *st); void dm_stats_cleanup(struct dm_stats *st); struct mapped_device; diff --git a/drivers/md/dm-table.c b/drivers/md/dm-table.c index 15c3a9db1ee0cafdc82dd806247bef08dd2df9ca..497c74f870b66179842303ab63293c6987f32abd 100644 --- a/drivers/md/dm-table.c +++ b/drivers/md/dm-table.c @@ -674,7 +674,7 @@ static int validate_hardware_logical_block_alignment(struct dm_table *table, */ unsigned short remaining = 0; - struct dm_target *uninitialized_var(ti); + struct dm_target *ti; struct queue_limits ti_limits; unsigned i; diff --git a/drivers/md/dm-thin.c b/drivers/md/dm-thin.c index 386cb33953783c09ca315d1b30c2cd080911cf77..969ea013c74e41c0e2b2ca5904d79d8e0c66dd6b 100644 --- a/drivers/md/dm-thin.c +++ b/drivers/md/dm-thin.c @@ -2222,6 +2222,7 @@ static void process_thin_deferred_bios(struct thin_c *tc) throttle_work_update(&pool->throttle); dm_pool_issue_prefetches(pool->pmd); } + cond_resched(); } blk_finish_plug(&plug); } @@ -2305,6 +2306,7 @@ static void process_thin_deferred_cells(struct thin_c *tc) else pool->process_cell(tc, cell); } + cond_resched(); } while (!list_empty(&cells)); } diff --git a/drivers/md/dm-verity-target.c b/drivers/md/dm-verity-target.c index 5b19a9a89ec2295df4c781cb63297099ac62ba59..e8aeeb6bc242a99efb01aaa52e8777eedbe23f83 100644 --- a/drivers/md/dm-verity-target.c +++ b/drivers/md/dm-verity-target.c @@ -487,7 +487,7 @@ static int verity_verify_io(struct dm_verity_io *io) sector_t cur_block = io->block + b; struct ahash_request *req = verity_io_hash_req(v, io); - if (v->validated_blocks && + if (v->validated_blocks && bio->bi_status == BLK_STS_OK && likely(test_bit(cur_block, v->validated_blocks))) { verity_bv_skip_block(v, io, &io->iter); continue; @@ -543,7 +543,7 @@ static int verity_verify_io(struct dm_verity_io *io) return -EIO; } if (verity_handle_err(v, DM_VERITY_BLOCK_TYPE_DATA, - cur_block)) + cur_block)) return -EIO; } } diff --git a/drivers/md/dm.c b/drivers/md/dm.c index 4409b8fb945541621f2aa8b35aba420301a2d04f..64ca9c9b19cd96a6d194f7c0a329f186d59bf780 100644 --- a/drivers/md/dm.c +++ b/drivers/md/dm.c @@ -271,7 +271,6 @@ static int __init local_init(void) static void local_exit(void) { - flush_scheduled_work(); destroy_workqueue(deferred_remove_workqueue); kmem_cache_destroy(_rq_cache); @@ -1972,7 +1971,9 @@ static struct mapped_device *alloc_dev(int minor) bio_set_dev(&md->flush_bio, md->bdev); md->flush_bio.bi_opf = REQ_OP_WRITE | REQ_PREFLUSH | REQ_SYNC; - dm_stats_init(&md->stats); + r = dm_stats_init(&md->stats); + if (r < 0) + goto bad; /* Populate the mapping, nobody knows we exist yet */ spin_lock(&_minor_lock); diff --git a/drivers/md/md-bitmap.c b/drivers/md/md-bitmap.c index 1c4c462787198a1c1d303954924eb614af14d35b..7ca81e917aef45b4a29ed8efccacbd5eb1fbfa13 100644 --- a/drivers/md/md-bitmap.c +++ b/drivers/md/md-bitmap.c @@ -53,14 +53,7 @@ __acquires(bitmap->lock) { unsigned char *mappage; - if (page >= bitmap->pages) { - /* This can happen if bitmap_start_sync goes beyond - * End-of-device while looking for a whole page. - * It is harmless. - */ - return -EINVAL; - } - + WARN_ON_ONCE(page >= bitmap->pages); if (bitmap->bp[page].hijacked) /* it's hijacked, don't try to alloc */ return 0; @@ -1368,6 +1361,14 @@ __acquires(bitmap->lock) sector_t csize; int err; + if (page >= bitmap->pages) { + /* + * This can happen if bitmap_start_sync goes beyond + * End-of-device while looking for a whole page or + * user set a huge number to sysfs bitmap_set_bits. + */ + return NULL; + } err = md_bitmap_checkpage(bitmap, page, create, 0); if (bitmap->bp[page].hijacked || diff --git a/drivers/md/md.c b/drivers/md/md.c index 89d4dcc5253e523ada57b1ee27617482d72d8573..6b074c2202d5a220b156b64265b9f583f503cb34 100644 --- a/drivers/md/md.c +++ b/drivers/md/md.c @@ -2991,6 +2991,9 @@ slot_store(struct md_rdev *rdev, const char *buf, size_t len) err = kstrtouint(buf, 10, (unsigned int *)&slot); if (err < 0) return err; + if (slot < 0) + /* overflow */ + return -ENOSPC; } if (rdev->mddev->pers && slot == -1) { /* Setting 'slot' on an active array requires also @@ -3668,8 +3671,9 @@ int strict_strtoul_scaled(const char *cp, unsigned long *res, int scale) static ssize_t safe_delay_show(struct mddev *mddev, char *page) { - int msec = (mddev->safemode_delay*1000)/HZ; - return sprintf(page, "%d.%03d\n", msec/1000, msec%1000); + unsigned int msec = ((unsigned long)mddev->safemode_delay*1000)/HZ; + + return sprintf(page, "%u.%03u\n", msec/1000, msec%1000); } static ssize_t safe_delay_store(struct mddev *mddev, const char *cbuf, size_t len) @@ -3681,7 +3685,7 @@ safe_delay_store(struct mddev *mddev, const char *cbuf, size_t len) return -EINVAL; } - if (strict_strtoul_scaled(cbuf, &msec, 3) < 0) + if (strict_strtoul_scaled(cbuf, &msec, 3) < 0 || msec > UINT_MAX / HZ) return -EINVAL; if (msec == 0) mddev->safemode_delay = 0; @@ -4333,6 +4337,8 @@ max_corrected_read_errors_store(struct mddev *mddev, const char *buf, size_t len rv = kstrtouint(buf, 10, &n); if (rv < 0) return rv; + if (n > INT_MAX) + return -EINVAL; atomic_set(&mddev->max_corr_read_errors, n); return len; } @@ -4633,11 +4639,21 @@ action_store(struct mddev *mddev, const char *page, size_t len) return -EINVAL; err = mddev_lock(mddev); if (!err) { - if (test_bit(MD_RECOVERY_RUNNING, &mddev->recovery)) + if (test_bit(MD_RECOVERY_RUNNING, &mddev->recovery)) { err = -EBUSY; - else { + } else if (mddev->reshape_position == MaxSector || + mddev->pers->check_reshape == NULL || + mddev->pers->check_reshape(mddev)) { clear_bit(MD_RECOVERY_FROZEN, &mddev->recovery); err = mddev->pers->start_reshape(mddev); + } else { + /* + * If reshape is still in progress, and + * md_check_recovery() can continue to reshape, + * don't restart reshape because data can be + * corrupted for raid456. + */ + clear_bit(MD_RECOVERY_FROZEN, &mddev->recovery); } mddev_unlock(mddev); } diff --git a/drivers/md/raid0.c b/drivers/md/raid0.c index 252ef0eab41cb448a15fe61401a2a6029eeaefea..6f5710e833c1b5641649bb47e3fab81d1b08b5a9 100644 --- a/drivers/md/raid0.c +++ b/drivers/md/raid0.c @@ -296,6 +296,18 @@ static int create_strip_zones(struct mddev *mddev, struct r0conf **private_conf) goto abort; } + if (conf->layout == RAID0_ORIG_LAYOUT) { + for (i = 1; i < conf->nr_strip_zones; i++) { + sector_t first_sector = conf->strip_zone[i-1].zone_end; + + sector_div(first_sector, mddev->chunk_sectors); + zone = conf->strip_zone + i; + /* disk_shift is first disk index used in the zone */ + zone->disk_shift = sector_div(first_sector, + zone->nb_dev); + } + } + pr_debug("md/raid0:%s: done.\n", mdname(mddev)); *private_conf = conf; @@ -482,6 +494,20 @@ static inline int is_io_in_chunk_boundary(struct mddev *mddev, } } +/* + * Convert disk_index to the disk order in which it is read/written. + * For example, if we have 4 disks, they are numbered 0,1,2,3. If we + * write the disks starting at disk 3, then the read/write order would + * be disk 3, then 0, then 1, and then disk 2 and we want map_disk_shift() + * to map the disks as follows 0,1,2,3 => 1,2,3,0. So disk 0 would map + * to 1, 1 to 2, 2 to 3, and 3 to 0. That way we can compare disks in + * that 'output' space to understand the read/write disk ordering. + */ +static int map_disk_shift(int disk_index, int num_disks, int disk_shift) +{ + return ((disk_index + num_disks - disk_shift) % num_disks); +} + static void raid0_handle_discard(struct mddev *mddev, struct bio *bio) { struct r0conf *conf = mddev->private; @@ -495,7 +521,9 @@ static void raid0_handle_discard(struct mddev *mddev, struct bio *bio) sector_t end_disk_offset; unsigned int end_disk_index; unsigned int disk; + sector_t orig_start, orig_end; + orig_start = start; zone = find_zone(conf, &start); if (bio_end_sector(bio) > zone->zone_end) { @@ -509,6 +537,7 @@ static void raid0_handle_discard(struct mddev *mddev, struct bio *bio) } else end = bio_end_sector(bio); + orig_end = end; if (zone != conf->strip_zone) end = end - zone[-1].zone_end; @@ -520,13 +549,26 @@ static void raid0_handle_discard(struct mddev *mddev, struct bio *bio) last_stripe_index = end; sector_div(last_stripe_index, stripe_size); - start_disk_index = (int)(start - first_stripe_index * stripe_size) / - mddev->chunk_sectors; + /* In the first zone the original and alternate layouts are the same */ + if ((conf->layout == RAID0_ORIG_LAYOUT) && (zone != conf->strip_zone)) { + sector_div(orig_start, mddev->chunk_sectors); + start_disk_index = sector_div(orig_start, zone->nb_dev); + start_disk_index = map_disk_shift(start_disk_index, + zone->nb_dev, + zone->disk_shift); + sector_div(orig_end, mddev->chunk_sectors); + end_disk_index = sector_div(orig_end, zone->nb_dev); + end_disk_index = map_disk_shift(end_disk_index, + zone->nb_dev, zone->disk_shift); + } else { + start_disk_index = (int)(start - first_stripe_index * stripe_size) / + mddev->chunk_sectors; + end_disk_index = (int)(end - last_stripe_index * stripe_size) / + mddev->chunk_sectors; + } start_disk_offset = ((int)(start - first_stripe_index * stripe_size) % mddev->chunk_sectors) + first_stripe_index * mddev->chunk_sectors; - end_disk_index = (int)(end - last_stripe_index * stripe_size) / - mddev->chunk_sectors; end_disk_offset = ((int)(end - last_stripe_index * stripe_size) % mddev->chunk_sectors) + last_stripe_index * mddev->chunk_sectors; @@ -535,18 +577,22 @@ static void raid0_handle_discard(struct mddev *mddev, struct bio *bio) sector_t dev_start, dev_end; struct bio *discard_bio = NULL; struct md_rdev *rdev; + int compare_disk; + + compare_disk = map_disk_shift(disk, zone->nb_dev, + zone->disk_shift); - if (disk < start_disk_index) + if (compare_disk < start_disk_index) dev_start = (first_stripe_index + 1) * mddev->chunk_sectors; - else if (disk > start_disk_index) + else if (compare_disk > start_disk_index) dev_start = first_stripe_index * mddev->chunk_sectors; else dev_start = start_disk_offset; - if (disk < end_disk_index) + if (compare_disk < end_disk_index) dev_end = (last_stripe_index + 1) * mddev->chunk_sectors; - else if (disk > end_disk_index) + else if (compare_disk > end_disk_index) dev_end = last_stripe_index * mddev->chunk_sectors; else dev_end = end_disk_offset; diff --git a/drivers/md/raid0.h b/drivers/md/raid0.h index 3816e5477db1e743afeaf707c1971f1dbdce1901..8cc761ca7423002d3d1d1e4c84ac5df9a3dcc70f 100644 --- a/drivers/md/raid0.h +++ b/drivers/md/raid0.h @@ -6,6 +6,7 @@ struct strip_zone { sector_t zone_end; /* Start of the next zone (in sectors) */ sector_t dev_start; /* Zone offset in real dev (in sectors) */ int nb_dev; /* # of devices attached to the zone */ + int disk_shift; /* start disk for the original layout */ }; /* Linux 3.14 (20d0189b101) made an unintended change to diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c index 0f8b1fb3d05178a3537af4b8718073108367f0b7..5ff06fbcfabf5d8c9f3dd2cdcb843c2f2b896e6b 100644 --- a/drivers/md/raid1.c +++ b/drivers/md/raid1.c @@ -1785,6 +1785,9 @@ static int raid1_remove_disk(struct mddev *mddev, struct md_rdev *rdev) int number = rdev->raid_disk; struct raid1_info *p = conf->mirrors + number; + if (unlikely(number >= conf->raid_disks)) + goto abort; + if (rdev != p->rdev) p = conf->mirrors + conf->raid_disks + number; diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c index 9f9cd2fadc1e7a5ce5c42afd467a642787e4a53f..bee694be201323dfc2ab6ecd78ddbbf691164a0f 100644 --- a/drivers/md/raid10.c +++ b/drivers/md/raid10.c @@ -781,8 +781,16 @@ static struct md_rdev *read_balance(struct r10conf *conf, disk = r10_bio->devs[slot].devnum; rdev = rcu_dereference(conf->mirrors[disk].replacement); if (rdev == NULL || test_bit(Faulty, &rdev->flags) || - r10_bio->devs[slot].addr + sectors > rdev->recovery_offset) + r10_bio->devs[slot].addr + sectors > + rdev->recovery_offset) { + /* + * Read replacement first to prevent reading both rdev + * and replacement as NULL during replacement replace + * rdev. + */ + smp_mb(); rdev = rcu_dereference(conf->mirrors[disk].rdev); + } if (rdev == NULL || test_bit(Faulty, &rdev->flags)) continue; @@ -934,6 +942,7 @@ static void flush_pending_writes(struct r10conf *conf) else generic_make_request(bio); bio = next; + cond_resched(); } blk_finish_plug(&plug); } else @@ -1119,6 +1128,7 @@ static void raid10_unplug(struct blk_plug_cb *cb, bool from_schedule) else generic_make_request(bio); bio = next; + cond_resched(); } kfree(plug); } @@ -1400,9 +1410,15 @@ static void raid10_write_request(struct mddev *mddev, struct bio *bio, for (i = 0; i < conf->copies; i++) { int d = r10_bio->devs[i].devnum; - struct md_rdev *rdev = rcu_dereference(conf->mirrors[d].rdev); - struct md_rdev *rrdev = rcu_dereference( - conf->mirrors[d].replacement); + struct md_rdev *rdev, *rrdev; + + rrdev = rcu_dereference(conf->mirrors[d].replacement); + /* + * Read replacement first to prevent reading both rdev and + * replacement as NULL during replacement replace rdev. + */ + smp_mb(); + rdev = rcu_dereference(conf->mirrors[d].rdev); if (rdev == rrdev) rrdev = NULL; if (rdev && unlikely(test_bit(Blocked, &rdev->flags))) { @@ -2266,11 +2282,22 @@ static void recovery_request_write(struct mddev *mddev, struct r10bio *r10_bio) { struct r10conf *conf = mddev->private; int d; - struct bio *wbio, *wbio2; + struct bio *wbio = r10_bio->devs[1].bio; + struct bio *wbio2 = r10_bio->devs[1].repl_bio; + + /* Need to test wbio2->bi_end_io before we call + * generic_make_request as if the former is NULL, + * the latter is free to free wbio2. + */ + if (wbio2 && !wbio2->bi_end_io) + wbio2 = NULL; if (!test_bit(R10BIO_Uptodate, &r10_bio->state)) { fix_recovery_read_error(r10_bio); - end_sync_request(r10_bio); + if (wbio->bi_end_io) + end_sync_request(r10_bio); + if (wbio2) + end_sync_request(r10_bio); return; } @@ -2279,14 +2306,6 @@ static void recovery_request_write(struct mddev *mddev, struct r10bio *r10_bio) * and submit the write request */ d = r10_bio->devs[1].devnum; - wbio = r10_bio->devs[1].bio; - wbio2 = r10_bio->devs[1].repl_bio; - /* Need to test wbio2->bi_end_io before we call - * generic_make_request as if the former is NULL, - * the latter is free to free wbio2. - */ - if (wbio2 && !wbio2->bi_end_io) - wbio2 = NULL; if (wbio->bi_end_io) { atomic_inc(&conf->mirrors[d].rdev->nr_pending); md_sync_acct(conf->mirrors[d].rdev->bdev, bio_sectors(wbio)); @@ -2954,10 +2973,6 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr, sector_t chunk_mask = conf->geo.chunk_mask; int page_idx = 0; - if (!mempool_initialized(&conf->r10buf_pool)) - if (init_resync(conf)) - return 0; - /* * Allow skipping a full rebuild for incremental assembly * of a clean array, like RAID1 does. @@ -2973,6 +2988,10 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr, return mddev->dev_sectors - sector_nr; } + if (!mempool_initialized(&conf->r10buf_pool)) + if (init_resync(conf)) + return 0; + skipped: max_sector = mddev->dev_sectors; if (test_bit(MD_RECOVERY_SYNC, &mddev->recovery) || @@ -3668,6 +3687,20 @@ static int setup_geo(struct geom *geo, struct mddev *mddev, enum geo_type new) return nc*fc; } +static void raid10_free_conf(struct r10conf *conf) +{ + if (!conf) + return; + + mempool_exit(&conf->r10bio_pool); + kfree(conf->mirrors); + kfree(conf->mirrors_old); + kfree(conf->mirrors_new); + safe_put_page(conf->tmppage); + bioset_exit(&conf->bio_split); + kfree(conf); +} + static struct r10conf *setup_conf(struct mddev *mddev) { struct r10conf *conf = NULL; @@ -3750,20 +3783,24 @@ static struct r10conf *setup_conf(struct mddev *mddev) return conf; out: - if (conf) { - mempool_exit(&conf->r10bio_pool); - kfree(conf->mirrors); - safe_put_page(conf->tmppage); - bioset_exit(&conf->bio_split); - kfree(conf); - } + raid10_free_conf(conf); return ERR_PTR(err); } +static void raid10_set_io_opt(struct r10conf *conf) +{ + int raid_disks = conf->geo.raid_disks; + + if (!(conf->geo.raid_disks % conf->geo.near_copies)) + raid_disks /= conf->geo.near_copies; + blk_queue_io_opt(conf->mddev->queue, (conf->mddev->chunk_sectors << 9) * + raid_disks); +} + static int raid10_run(struct mddev *mddev) { struct r10conf *conf; - int i, disk_idx, chunk_size; + int i, disk_idx; struct raid10_info *disk; struct md_rdev *rdev; sector_t size; @@ -3784,6 +3821,9 @@ static int raid10_run(struct mddev *mddev) if (!conf) goto out; + mddev->thread = conf->thread; + conf->thread = NULL; + if (mddev_is_clustered(conf->mddev)) { int fc, fo; @@ -3796,21 +3836,13 @@ static int raid10_run(struct mddev *mddev) } } - mddev->thread = conf->thread; - conf->thread = NULL; - - chunk_size = mddev->chunk_sectors << 9; if (mddev->queue) { blk_queue_max_discard_sectors(mddev->queue, mddev->chunk_sectors); blk_queue_max_write_same_sectors(mddev->queue, 0); blk_queue_max_write_zeroes_sectors(mddev->queue, 0); - blk_queue_io_min(mddev->queue, chunk_size); - if (conf->geo.raid_disks % conf->geo.near_copies) - blk_queue_io_opt(mddev->queue, chunk_size * conf->geo.raid_disks); - else - blk_queue_io_opt(mddev->queue, chunk_size * - (conf->geo.raid_disks / conf->geo.near_copies)); + blk_queue_io_min(mddev->queue, mddev->chunk_sectors << 9); + raid10_set_io_opt(conf); } rdev_for_each(rdev, mddev) { @@ -3970,10 +4002,7 @@ static int raid10_run(struct mddev *mddev) out_free_conf: md_unregister_thread(&mddev->thread); - mempool_exit(&conf->r10bio_pool); - safe_put_page(conf->tmppage); - kfree(conf->mirrors); - kfree(conf); + raid10_free_conf(conf); mddev->private = NULL; out: return -EIO; @@ -3981,15 +4010,7 @@ static int raid10_run(struct mddev *mddev) static void raid10_free(struct mddev *mddev, void *priv) { - struct r10conf *conf = priv; - - mempool_exit(&conf->r10bio_pool); - safe_put_page(conf->tmppage); - kfree(conf->mirrors); - kfree(conf->mirrors_old); - kfree(conf->mirrors_new); - bioset_exit(&conf->bio_split); - kfree(conf); + raid10_free_conf(priv); } static void raid10_quiesce(struct mddev *mddev, int quiesce) @@ -4724,6 +4745,7 @@ static void end_reshape(struct r10conf *conf) stripe /= conf->geo.near_copies; if (conf->mddev->queue->backing_dev_info->ra_pages < 2 * stripe) conf->mddev->queue->backing_dev_info->ra_pages = 2 * stripe; + raid10_set_io_opt(conf); } conf->fullsync = 0; } diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 7fe0619c487ae16a3faea2d0bc0627d1b1cc7b57..b98abe927d06bfbc9268302fbb332e6f3c4a92ee 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -2603,7 +2603,7 @@ static void raid5_end_write_request(struct bio *bi) struct stripe_head *sh = bi->bi_private; struct r5conf *conf = sh->raid_conf; int disks = sh->disks, i; - struct md_rdev *uninitialized_var(rdev); + struct md_rdev *rdev; sector_t first_bad; int bad_sectors; int replacement = 0; @@ -7153,6 +7153,12 @@ static int only_parity(int raid_disk, int algo, int raid_disks, int max_degraded return 0; } +static void raid5_set_io_opt(struct r5conf *conf) +{ + blk_queue_io_opt(conf->mddev->queue, (conf->chunk_sectors << 9) * + (conf->raid_disks - conf->max_degraded)); +} + static int raid5_run(struct mddev *mddev) { struct r5conf *conf; @@ -7442,8 +7448,7 @@ static int raid5_run(struct mddev *mddev) chunk_size = mddev->chunk_sectors << 9; blk_queue_io_min(mddev->queue, chunk_size); - blk_queue_io_opt(mddev->queue, chunk_size * - (conf->raid_disks - conf->max_degraded)); + raid5_set_io_opt(conf); mddev->queue->limits.raid_partial_stripes_expensive = 1; /* * We can only discard a whole stripe. It doesn't make sense to @@ -8037,6 +8042,7 @@ static void end_reshape(struct r5conf *conf) / PAGE_SIZE); if (conf->mddev->queue->backing_dev_info->ra_pages < 2 * stripe) conf->mddev->queue->backing_dev_info->ra_pages = 2 * stripe; + raid5_set_io_opt(conf); } } } diff --git a/drivers/media/cec/cec-adap.c b/drivers/media/cec/cec-adap.c index a42043379d676fcbd306dd5167613258d5c83d8d..2f49c4db49b3534256e493dafa1e34068865d9e2 100644 --- a/drivers/media/cec/cec-adap.c +++ b/drivers/media/cec/cec-adap.c @@ -1032,7 +1032,8 @@ void cec_received_msg_ts(struct cec_adapter *adap, mutex_lock(&adap->lock); dprintk(2, "%s: %*ph\n", __func__, msg->len, msg->msg); - adap->last_initiator = 0xff; + if (!adap->transmit_in_progress) + adap->last_initiator = 0xff; /* Check if this message was for us (directed or broadcast). */ if (!cec_msg_is_broadcast(msg)) diff --git a/drivers/media/dvb-core/dvb_ca_en50221.c b/drivers/media/dvb-core/dvb_ca_en50221.c index 36afcea709a7512bd6e076e1ad33a689339a9f54..3647196c2f519012d6f06ce10e71da50863c0527 100644 --- a/drivers/media/dvb-core/dvb_ca_en50221.c +++ b/drivers/media/dvb-core/dvb_ca_en50221.c @@ -162,6 +162,12 @@ struct dvb_ca_private { /* mutex serializing ioctls */ struct mutex ioctl_mutex; + + /* A mutex used when a device is disconnected */ + struct mutex remove_mutex; + + /* Whether the device is disconnected */ + int exit; }; static void dvb_ca_private_free(struct dvb_ca_private *ca) @@ -198,7 +204,7 @@ static void dvb_ca_en50221_thread_wakeup(struct dvb_ca_private *ca); static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot, u8 *ebuf, int ecount); static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, - u8 *ebuf, int ecount); + u8 *ebuf, int ecount, int size_write_flag); /** * Safely find needle in haystack. @@ -381,7 +387,7 @@ static int dvb_ca_en50221_link_init(struct dvb_ca_private *ca, int slot) ret = dvb_ca_en50221_wait_if_status(ca, slot, STATUSREG_FR, HZ / 10); if (ret) return ret; - ret = dvb_ca_en50221_write_data(ca, slot, buf, 2); + ret = dvb_ca_en50221_write_data(ca, slot, buf, 2, CMDREG_SW); if (ret != 2) return -EIO; ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN); @@ -789,11 +795,13 @@ static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot, * @buf: The data in this buffer is treated as a complete link-level packet to * be written. * @bytes_write: Size of ebuf. + * @size_write_flag: A flag on Command Register which says whether the link size + * information will be writen or not. * * return: Number of bytes written, or < 0 on error. */ static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, - u8 *buf, int bytes_write) + u8 *buf, int bytes_write, int size_write_flag) { struct dvb_ca_slot *sl = &ca->slot_info[slot]; int status; @@ -828,7 +836,7 @@ static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, /* OK, set HC bit */ status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, - IRQEN | CMDREG_HC); + IRQEN | CMDREG_HC | size_write_flag); if (status) goto exit; @@ -1516,7 +1524,7 @@ static ssize_t dvb_ca_en50221_io_write(struct file *file, mutex_lock(&sl->slot_lock); status = dvb_ca_en50221_write_data(ca, slot, fragbuf, - fraglen + 2); + fraglen + 2, 0); mutex_unlock(&sl->slot_lock); if (status == (fraglen + 2)) { written = 1; @@ -1717,12 +1725,22 @@ static int dvb_ca_en50221_io_open(struct inode *inode, struct file *file) dprintk("%s\n", __func__); - if (!try_module_get(ca->pub->owner)) + mutex_lock(&ca->remove_mutex); + + if (ca->exit) { + mutex_unlock(&ca->remove_mutex); + return -ENODEV; + } + + if (!try_module_get(ca->pub->owner)) { + mutex_unlock(&ca->remove_mutex); return -EIO; + } err = dvb_generic_open(inode, file); if (err < 0) { module_put(ca->pub->owner); + mutex_unlock(&ca->remove_mutex); return err; } @@ -1747,6 +1765,7 @@ static int dvb_ca_en50221_io_open(struct inode *inode, struct file *file) dvb_ca_private_get(ca); + mutex_unlock(&ca->remove_mutex); return 0; } @@ -1766,6 +1785,8 @@ static int dvb_ca_en50221_io_release(struct inode *inode, struct file *file) dprintk("%s\n", __func__); + mutex_lock(&ca->remove_mutex); + /* mark the CA device as closed */ ca->open = 0; dvb_ca_en50221_thread_update_delay(ca); @@ -1776,6 +1797,13 @@ static int dvb_ca_en50221_io_release(struct inode *inode, struct file *file) dvb_ca_private_put(ca); + if (dvbdev->users == 1 && ca->exit == 1) { + mutex_unlock(&ca->remove_mutex); + wake_up(&dvbdev->wait_queue); + } else { + mutex_unlock(&ca->remove_mutex); + } + return err; } @@ -1900,6 +1928,7 @@ int dvb_ca_en50221_init(struct dvb_adapter *dvb_adapter, } mutex_init(&ca->ioctl_mutex); + mutex_init(&ca->remove_mutex); if (signal_pending(current)) { ret = -EINTR; @@ -1942,6 +1971,14 @@ void dvb_ca_en50221_release(struct dvb_ca_en50221 *pubca) dprintk("%s\n", __func__); + mutex_lock(&ca->remove_mutex); + ca->exit = 1; + mutex_unlock(&ca->remove_mutex); + + if (ca->dvbdev->users < 1) + wait_event(ca->dvbdev->wait_queue, + ca->dvbdev->users == 1); + /* shutdown the thread if there was one */ kthread_stop(ca->thread); diff --git a/drivers/media/dvb-core/dvb_demux.c b/drivers/media/dvb-core/dvb_demux.c index a0cfe74b9523c13eefae025e01bf9cd1cc76c61a..6aeeddad151d7f1a90385e31bfb21b5ebe865249 100644 --- a/drivers/media/dvb-core/dvb_demux.c +++ b/drivers/media/dvb-core/dvb_demux.c @@ -771,7 +771,6 @@ static int dvb_dmx_swfilter_section_one_packet(struct dvb_demux_feed *feed, return -EINVAL; feed->first_cc = 0; - feed->cc = cc; if (buf[3] & 0x20) { /* adaption field present, check for discontinuity_indicator */ @@ -797,6 +796,7 @@ static int dvb_dmx_swfilter_section_one_packet(struct dvb_demux_feed *feed, feed->pusi_seen = 0; dvb_dmx_swfilter_section_new(feed); } + feed->cc = cc; if (buf[1] & 0x40) { /* PUSI=1 (is set), section boundary is here */ diff --git a/drivers/media/dvb-core/dvb_frontend.c b/drivers/media/dvb-core/dvb_frontend.c index e0650bc2df613d6841b22c5fad29146cd00a6817..90acf52cc253c2b59fb9eb1b05b72326aee201da 100644 --- a/drivers/media/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb-core/dvb_frontend.c @@ -304,14 +304,22 @@ static int dvb_frontend_get_event(struct dvb_frontend *fe, } if (events->eventw == events->eventr) { - int ret; + struct wait_queue_entry wait; + int ret = 0; if (flags & O_NONBLOCK) return -EWOULDBLOCK; - ret = wait_event_interruptible(events->wait_queue, - dvb_frontend_test_event(fepriv, events)); - + init_waitqueue_entry(&wait, current); + add_wait_queue(&events->wait_queue, &wait); + while (!dvb_frontend_test_event(fepriv, events)) { + wait_woken(&wait, TASK_INTERRUPTIBLE, 0); + if (signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + } + remove_wait_queue(&events->wait_queue, &wait); if (ret < 0) return ret; } diff --git a/drivers/media/dvb-core/dvb_net.c b/drivers/media/dvb-core/dvb_net.c index 660891275527628c29de4dba207f6613e3307fca..a95bcbde079a00531b4a53a94c2692579ce40d8c 100644 --- a/drivers/media/dvb-core/dvb_net.c +++ b/drivers/media/dvb-core/dvb_net.c @@ -1576,15 +1576,43 @@ static long dvb_net_ioctl(struct file *file, return dvb_usercopy(file, cmd, arg, dvb_net_do_ioctl); } +static int locked_dvb_net_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_net *dvbnet = dvbdev->priv; + int ret; + + if (mutex_lock_interruptible(&dvbnet->remove_mutex)) + return -ERESTARTSYS; + + if (dvbnet->exit) { + mutex_unlock(&dvbnet->remove_mutex); + return -ENODEV; + } + + ret = dvb_generic_open(inode, file); + + mutex_unlock(&dvbnet->remove_mutex); + + return ret; +} + static int dvb_net_close(struct inode *inode, struct file *file) { struct dvb_device *dvbdev = file->private_data; struct dvb_net *dvbnet = dvbdev->priv; + mutex_lock(&dvbnet->remove_mutex); + dvb_generic_release(inode, file); - if(dvbdev->users == 1 && dvbnet->exit == 1) + if (dvbdev->users == 1 && dvbnet->exit == 1) { + mutex_unlock(&dvbnet->remove_mutex); wake_up(&dvbdev->wait_queue); + } else { + mutex_unlock(&dvbnet->remove_mutex); + } + return 0; } @@ -1592,7 +1620,7 @@ static int dvb_net_close(struct inode *inode, struct file *file) static const struct file_operations dvb_net_fops = { .owner = THIS_MODULE, .unlocked_ioctl = dvb_net_ioctl, - .open = dvb_generic_open, + .open = locked_dvb_net_open, .release = dvb_net_close, .llseek = noop_llseek, }; @@ -1611,10 +1639,13 @@ void dvb_net_release (struct dvb_net *dvbnet) { int i; + mutex_lock(&dvbnet->remove_mutex); dvbnet->exit = 1; + mutex_unlock(&dvbnet->remove_mutex); + if (dvbnet->dvbdev->users < 1) wait_event(dvbnet->dvbdev->wait_queue, - dvbnet->dvbdev->users==1); + dvbnet->dvbdev->users == 1); dvb_unregister_device(dvbnet->dvbdev); @@ -1633,6 +1664,7 @@ int dvb_net_init (struct dvb_adapter *adap, struct dvb_net *dvbnet, int i; mutex_init(&dvbnet->ioctl_mutex); + mutex_init(&dvbnet->remove_mutex); dvbnet->demux = dmx; for (i=0; ii2c_address, priv->i2c); return fe; } -EXPORT_SYMBOL(ascot2e_attach); +EXPORT_SYMBOL_GPL(ascot2e_attach); MODULE_DESCRIPTION("Sony ASCOT2E terr/cab tuner driver"); MODULE_AUTHOR("info@netup.ru"); diff --git a/drivers/media/dvb-frontends/atbm8830.c b/drivers/media/dvb-frontends/atbm8830.c index cbcc65dc9d540f2b7cd75c36483c900fde54b0b7..af5ada9f8f455e2778b2547fba2e279be7174efd 100644 --- a/drivers/media/dvb-frontends/atbm8830.c +++ b/drivers/media/dvb-frontends/atbm8830.c @@ -498,7 +498,7 @@ struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config, return NULL; } -EXPORT_SYMBOL(atbm8830_attach); +EXPORT_SYMBOL_GPL(atbm8830_attach); MODULE_DESCRIPTION("AltoBeam ATBM8830/8831 GB20600 demodulator driver"); MODULE_AUTHOR("David T. L. Wong "); diff --git a/drivers/media/dvb-frontends/au8522_dig.c b/drivers/media/dvb-frontends/au8522_dig.c index 076f737aa8c067063cfe8a9b39bdabb3ab76ca14..ee9bacc4811214405c2f988901a4bdc6489bb0f4 100644 --- a/drivers/media/dvb-frontends/au8522_dig.c +++ b/drivers/media/dvb-frontends/au8522_dig.c @@ -891,7 +891,7 @@ struct dvb_frontend *au8522_attach(const struct au8522_config *config, au8522_release_state(state); return NULL; } -EXPORT_SYMBOL(au8522_attach); +EXPORT_SYMBOL_GPL(au8522_attach); static const struct dvb_frontend_ops au8522_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/bcm3510.c b/drivers/media/dvb-frontends/bcm3510.c index 6457b0912d14d7cb1b876696baf2b7bc06f715bb..bc4cc8c24e1a26a2a0da8dc9cccffd48e586af5f 100644 --- a/drivers/media/dvb-frontends/bcm3510.c +++ b/drivers/media/dvb-frontends/bcm3510.c @@ -835,7 +835,7 @@ struct dvb_frontend* bcm3510_attach(const struct bcm3510_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(bcm3510_attach); +EXPORT_SYMBOL_GPL(bcm3510_attach); static const struct dvb_frontend_ops bcm3510_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/cx22700.c b/drivers/media/dvb-frontends/cx22700.c index 961380162cddaabb1a2e8de0410b7029eba896df..43968d02a664146de11bb57cb6320e9e8d2b77a4 100644 --- a/drivers/media/dvb-frontends/cx22700.c +++ b/drivers/media/dvb-frontends/cx22700.c @@ -444,4 +444,4 @@ MODULE_DESCRIPTION("Conexant CX22700 DVB-T Demodulator driver"); MODULE_AUTHOR("Holger Waechtler"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(cx22700_attach); +EXPORT_SYMBOL_GPL(cx22700_attach); diff --git a/drivers/media/dvb-frontends/cx22702.c b/drivers/media/dvb-frontends/cx22702.c index ab9b2924bcca321ceab1cf91a351495112b55ad1..0954e646836c0a1dabe9b72187d8bd5d3ae4adb1 100644 --- a/drivers/media/dvb-frontends/cx22702.c +++ b/drivers/media/dvb-frontends/cx22702.c @@ -616,7 +616,7 @@ struct dvb_frontend *cx22702_attach(const struct cx22702_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(cx22702_attach); +EXPORT_SYMBOL_GPL(cx22702_attach); static const struct dvb_frontend_ops cx22702_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/cx24110.c b/drivers/media/dvb-frontends/cx24110.c index 9441bdc73097cb090b41660a8f25042e6a91a997..ad3291d6aafb860ea6368a0df1353369831d4aa3 100644 --- a/drivers/media/dvb-frontends/cx24110.c +++ b/drivers/media/dvb-frontends/cx24110.c @@ -666,4 +666,4 @@ MODULE_DESCRIPTION("Conexant CX24110 DVB-S Demodulator driver"); MODULE_AUTHOR("Peter Hettkamp"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(cx24110_attach); +EXPORT_SYMBOL_GPL(cx24110_attach); diff --git a/drivers/media/dvb-frontends/cx24113.c b/drivers/media/dvb-frontends/cx24113.c index 91a5033b6bd75b42bbfd47e4254489f2bae28a9e..6e486a0d4d2072eef76b552967ab6b4d008f8a1a 100644 --- a/drivers/media/dvb-frontends/cx24113.c +++ b/drivers/media/dvb-frontends/cx24113.c @@ -600,7 +600,7 @@ struct dvb_frontend *cx24113_attach(struct dvb_frontend *fe, return NULL; } -EXPORT_SYMBOL(cx24113_attach); +EXPORT_SYMBOL_GPL(cx24113_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); diff --git a/drivers/media/dvb-frontends/cx24116.c b/drivers/media/dvb-frontends/cx24116.c index 220f2666364726428650417b2800de9cce853d1d..cb82998619c8269b7b7dca861a482d556544aa72 100644 --- a/drivers/media/dvb-frontends/cx24116.c +++ b/drivers/media/dvb-frontends/cx24116.c @@ -1145,7 +1145,7 @@ struct dvb_frontend *cx24116_attach(const struct cx24116_config *config, state->frontend.demodulator_priv = state; return &state->frontend; } -EXPORT_SYMBOL(cx24116_attach); +EXPORT_SYMBOL_GPL(cx24116_attach); /* * Initialise or wake up device diff --git a/drivers/media/dvb-frontends/cx24120.c b/drivers/media/dvb-frontends/cx24120.c index dd3ec316e7c2a99d87430fa17f64a8176c8f274e..a6cf5a02ce5b1729473d2ae289ee74506c743066 100644 --- a/drivers/media/dvb-frontends/cx24120.c +++ b/drivers/media/dvb-frontends/cx24120.c @@ -313,7 +313,7 @@ struct dvb_frontend *cx24120_attach(const struct cx24120_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(cx24120_attach); +EXPORT_SYMBOL_GPL(cx24120_attach); static int cx24120_test_rom(struct cx24120_state *state) { @@ -980,7 +980,9 @@ static void cx24120_set_clock_ratios(struct dvb_frontend *fe) cmd.arg[8] = (clock_ratios_table[idx].rate >> 8) & 0xff; cmd.arg[9] = (clock_ratios_table[idx].rate >> 0) & 0xff; - cx24120_message_send(state, &cmd); + ret = cx24120_message_send(state, &cmd); + if (ret != 0) + return; /* Calculate ber window rates for stat work */ cx24120_calculate_ber_window(state, clock_ratios_table[idx].rate); diff --git a/drivers/media/dvb-frontends/cx24123.c b/drivers/media/dvb-frontends/cx24123.c index e49215020a9372bb092e7acd6eb8b895c7dbee61..faf1c7e5f2e8bb89ed903b39fcde26f52c37f7ef 100644 --- a/drivers/media/dvb-frontends/cx24123.c +++ b/drivers/media/dvb-frontends/cx24123.c @@ -1105,7 +1105,7 @@ struct dvb_frontend *cx24123_attach(const struct cx24123_config *config, return NULL; } -EXPORT_SYMBOL(cx24123_attach); +EXPORT_SYMBOL_GPL(cx24123_attach); static const struct dvb_frontend_ops cx24123_ops = { .delsys = { SYS_DVBS }, diff --git a/drivers/media/dvb-frontends/cxd2820r_core.c b/drivers/media/dvb-frontends/cxd2820r_core.c index 3e0d8cbd76da36e680f40661edd9a57de344a60b..9b81f1651ad0dd0501c28d613b80c355300bfcce 100644 --- a/drivers/media/dvb-frontends/cxd2820r_core.c +++ b/drivers/media/dvb-frontends/cxd2820r_core.c @@ -549,7 +549,7 @@ struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *config, return pdata.get_dvb_frontend(client); } -EXPORT_SYMBOL(cxd2820r_attach); +EXPORT_SYMBOL_GPL(cxd2820r_attach); static struct dvb_frontend *cxd2820r_get_dvb_frontend(struct i2c_client *client) { diff --git a/drivers/media/dvb-frontends/cxd2841er.c b/drivers/media/dvb-frontends/cxd2841er.c index c98093ed3dd76653fcc0f247ae534157c0e0109e..f7cb0012881044bfc70030093c91b2d9e3d95c8b 100644 --- a/drivers/media/dvb-frontends/cxd2841er.c +++ b/drivers/media/dvb-frontends/cxd2841er.c @@ -3929,14 +3929,14 @@ struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg, { return cxd2841er_attach(cfg, i2c, SYS_DVBS); } -EXPORT_SYMBOL(cxd2841er_attach_s); +EXPORT_SYMBOL_GPL(cxd2841er_attach_s); struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg, struct i2c_adapter *i2c) { return cxd2841er_attach(cfg, i2c, 0); } -EXPORT_SYMBOL(cxd2841er_attach_t_c); +EXPORT_SYMBOL_GPL(cxd2841er_attach_t_c); static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = { .delsys = { SYS_DVBS, SYS_DVBS2 }, diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c b/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c index f87e27481ea7b9dd7737c764dd91583c34801c8a..ea1bc9a35618eb37786725e31491a06d4a21e2ff 100644 --- a/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c +++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c @@ -1950,7 +1950,7 @@ struct dvb_frontend *cxd2880_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(cxd2880_attach); +EXPORT_SYMBOL_GPL(cxd2880_attach); MODULE_DESCRIPTION("Sony CXD2880 DVB-T2/T tuner + demod driver"); MODULE_AUTHOR("Sony Semiconductor Solutions Corporation"); diff --git a/drivers/media/dvb-frontends/dib0070.c b/drivers/media/dvb-frontends/dib0070.c index 37ebd5af8fd46898e58398ce97447523f48b0228..81e041ff3dd56174b6631927160af9b71e19154f 100644 --- a/drivers/media/dvb-frontends/dib0070.c +++ b/drivers/media/dvb-frontends/dib0070.c @@ -767,7 +767,7 @@ struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter fe->tuner_priv = NULL; return NULL; } -EXPORT_SYMBOL(dib0070_attach); +EXPORT_SYMBOL_GPL(dib0070_attach); MODULE_AUTHOR("Patrick Boettcher "); MODULE_DESCRIPTION("Driver for the DiBcom 0070 base-band RF Tuner"); diff --git a/drivers/media/dvb-frontends/dib0090.c b/drivers/media/dvb-frontends/dib0090.c index 44a074261e698571149faa67e07fb5deae63d7f1..c1942d24e0901ad3955f7061dc707347c03adfe0 100644 --- a/drivers/media/dvb-frontends/dib0090.c +++ b/drivers/media/dvb-frontends/dib0090.c @@ -2643,7 +2643,7 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte return NULL; } -EXPORT_SYMBOL(dib0090_register); +EXPORT_SYMBOL_GPL(dib0090_register); struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config) { @@ -2669,7 +2669,7 @@ struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_ada fe->tuner_priv = NULL; return NULL; } -EXPORT_SYMBOL(dib0090_fw_register); +EXPORT_SYMBOL_GPL(dib0090_fw_register); MODULE_AUTHOR("Patrick Boettcher "); MODULE_AUTHOR("Olivier Grenie "); diff --git a/drivers/media/dvb-frontends/dib3000mb.c b/drivers/media/dvb-frontends/dib3000mb.c index bbbd5328047742919c4aa0ef034f00fd814fc217..8df51730d87031ca48ead74e6742e1868ebec63d 100644 --- a/drivers/media/dvb-frontends/dib3000mb.c +++ b/drivers/media/dvb-frontends/dib3000mb.c @@ -819,4 +819,4 @@ MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(dib3000mb_attach); +EXPORT_SYMBOL_GPL(dib3000mb_attach); diff --git a/drivers/media/dvb-frontends/dib3000mc.c b/drivers/media/dvb-frontends/dib3000mc.c index c9e1db2517232e31d487162326331029de478794..040602e8ad7436e6749ccae9bc9bd4a33f296e97 100644 --- a/drivers/media/dvb-frontends/dib3000mc.c +++ b/drivers/media/dvb-frontends/dib3000mc.c @@ -938,7 +938,7 @@ struct dvb_frontend * dib3000mc_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr kfree(st); return NULL; } -EXPORT_SYMBOL(dib3000mc_attach); +EXPORT_SYMBOL_GPL(dib3000mc_attach); static const struct dvb_frontend_ops dib3000mc_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/dib7000m.c b/drivers/media/dvb-frontends/dib7000m.c index b79358d09de68aa4ec1d606fc77c750daf44f405..9684559fc670028a88c14b92c3fcdfce5c98e11b 100644 --- a/drivers/media/dvb-frontends/dib7000m.c +++ b/drivers/media/dvb-frontends/dib7000m.c @@ -1437,7 +1437,7 @@ struct dvb_frontend * dib7000m_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, kfree(st); return NULL; } -EXPORT_SYMBOL(dib7000m_attach); +EXPORT_SYMBOL_GPL(dib7000m_attach); static const struct dvb_frontend_ops dib7000m_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/dib7000p.c b/drivers/media/dvb-frontends/dib7000p.c index 58387860b62dcd90f203cffc62b1f0ea7877e9d6..6399cbc968c47ed7a28afb5d3ccbeab72d46687e 100644 --- a/drivers/media/dvb-frontends/dib7000p.c +++ b/drivers/media/dvb-frontends/dib7000p.c @@ -500,7 +500,7 @@ static int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth prediv = reg_1856 & 0x3f; loopdiv = (reg_1856 >> 6) & 0x3f; - if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) { + if (loopdiv && bw && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) { dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio); reg_1856 &= 0xf000; reg_1857 = dib7000p_read_word(state, 1857); @@ -2818,7 +2818,7 @@ void *dib7000p_attach(struct dib7000p_ops *ops) return ops; } -EXPORT_SYMBOL(dib7000p_attach); +EXPORT_SYMBOL_GPL(dib7000p_attach); static const struct dvb_frontend_ops dib7000p_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/dib8000.c b/drivers/media/dvb-frontends/dib8000.c index 4b9e4afa4c61f30983ce1e8255cc48e43ede8a1a..ca3c219df3c5edcf11823a4f0b5b57e78aaeda1f 100644 --- a/drivers/media/dvb-frontends/dib8000.c +++ b/drivers/media/dvb-frontends/dib8000.c @@ -4530,7 +4530,7 @@ void *dib8000_attach(struct dib8000_ops *ops) return ops; } -EXPORT_SYMBOL(dib8000_attach); +EXPORT_SYMBOL_GPL(dib8000_attach); MODULE_AUTHOR("Olivier Grenie "); MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator"); diff --git a/drivers/media/dvb-frontends/dib9000.c b/drivers/media/dvb-frontends/dib9000.c index 0183fb1346efc5384a5054640cc7ee50904ffb58..ebe693bf9256764304fa12ab61d743d2edb17780 100644 --- a/drivers/media/dvb-frontends/dib9000.c +++ b/drivers/media/dvb-frontends/dib9000.c @@ -2547,7 +2547,7 @@ struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, c kfree(st); return NULL; } -EXPORT_SYMBOL(dib9000_attach); +EXPORT_SYMBOL_GPL(dib9000_attach); static const struct dvb_frontend_ops dib9000_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 9628d4067fe19c8ea64bd0f616ddd410c9e47e41..9670bc98b45a9a6c5d81fb318821cfa2840a8e71 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -12367,7 +12367,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) return NULL; } -EXPORT_SYMBOL(drx39xxj_attach); +EXPORT_SYMBOL_GPL(drx39xxj_attach); static const struct dvb_frontend_ops drx39xxj_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/drxd_hard.c b/drivers/media/dvb-frontends/drxd_hard.c index 684d428efb0dc2741dbe043728805ec08253f9bd..f9038c495ece31a087bbc5b41941bb395c96078d 100644 --- a/drivers/media/dvb-frontends/drxd_hard.c +++ b/drivers/media/dvb-frontends/drxd_hard.c @@ -2972,7 +2972,7 @@ struct dvb_frontend *drxd_attach(const struct drxd_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(drxd_attach); +EXPORT_SYMBOL_GPL(drxd_attach); MODULE_DESCRIPTION("DRXD driver"); MODULE_AUTHOR("Micronas"); diff --git a/drivers/media/dvb-frontends/drxk_hard.c b/drivers/media/dvb-frontends/drxk_hard.c index 100a3a0b2db3763af8e8ff91842ec890d2187674..ad18c8ba1da03f629c79d77520e388b54f33da58 100644 --- a/drivers/media/dvb-frontends/drxk_hard.c +++ b/drivers/media/dvb-frontends/drxk_hard.c @@ -6867,7 +6867,7 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(drxk_attach); +EXPORT_SYMBOL_GPL(drxk_attach); MODULE_DESCRIPTION("DRX-K driver"); MODULE_AUTHOR("Ralph Metzler"); diff --git a/drivers/media/dvb-frontends/ds3000.c b/drivers/media/dvb-frontends/ds3000.c index 46a55146cb0756b340ae384c9a6bba2b075bb9ce..adc00f291921a9e88fceaa740f83bb1a0b9849c5 100644 --- a/drivers/media/dvb-frontends/ds3000.c +++ b/drivers/media/dvb-frontends/ds3000.c @@ -871,7 +871,7 @@ struct dvb_frontend *ds3000_attach(const struct ds3000_config *config, ds3000_set_voltage(&state->frontend, SEC_VOLTAGE_OFF); return &state->frontend; } -EXPORT_SYMBOL(ds3000_attach); +EXPORT_SYMBOL_GPL(ds3000_attach); static int ds3000_set_carrier_offset(struct dvb_frontend *fe, s32 carrier_offset_khz) diff --git a/drivers/media/dvb-frontends/dvb-pll.c b/drivers/media/dvb-frontends/dvb-pll.c index ee830c76e4b30b69361b5fbdc4d2708cc71463e3..bd7576e6338800feef831aa78465ebae4bcdcb9c 100644 --- a/drivers/media/dvb-frontends/dvb-pll.c +++ b/drivers/media/dvb-frontends/dvb-pll.c @@ -875,7 +875,7 @@ struct dvb_frontend *dvb_pll_attach(struct dvb_frontend *fe, int pll_addr, return NULL; } -EXPORT_SYMBOL(dvb_pll_attach); +EXPORT_SYMBOL_GPL(dvb_pll_attach); static int diff --git a/drivers/media/dvb-frontends/ec100.c b/drivers/media/dvb-frontends/ec100.c index c2575fdcc81132e8a288e4f0394ee379f0b64ba2..121699e414750a9537cf2efdca1aea82721f9c8e 100644 --- a/drivers/media/dvb-frontends/ec100.c +++ b/drivers/media/dvb-frontends/ec100.c @@ -309,7 +309,7 @@ struct dvb_frontend *ec100_attach(const struct ec100_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(ec100_attach); +EXPORT_SYMBOL_GPL(ec100_attach); static const struct dvb_frontend_ops ec100_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/helene.c b/drivers/media/dvb-frontends/helene.c index d7790cb98a0c76269a3995de17eaf80e3333ac73..2945124cb7ae160ab0df8a1fe6856bb4bdc6dae5 100644 --- a/drivers/media/dvb-frontends/helene.c +++ b/drivers/media/dvb-frontends/helene.c @@ -1034,7 +1034,7 @@ struct dvb_frontend *helene_attach_s(struct dvb_frontend *fe, priv->i2c_address, priv->i2c); return fe; } -EXPORT_SYMBOL(helene_attach_s); +EXPORT_SYMBOL_GPL(helene_attach_s); struct dvb_frontend *helene_attach(struct dvb_frontend *fe, const struct helene_config *config, @@ -1070,7 +1070,7 @@ struct dvb_frontend *helene_attach(struct dvb_frontend *fe, priv->i2c_address, priv->i2c); return fe; } -EXPORT_SYMBOL(helene_attach); +EXPORT_SYMBOL_GPL(helene_attach); static int helene_probe(struct i2c_client *client, const struct i2c_device_id *id) diff --git a/drivers/media/dvb-frontends/horus3a.c b/drivers/media/dvb-frontends/horus3a.c index 02bc0808197177438b009383efb8a5d6ce676e34..b748b351e161dc429d132691205029b95fea9a93 100644 --- a/drivers/media/dvb-frontends/horus3a.c +++ b/drivers/media/dvb-frontends/horus3a.c @@ -404,7 +404,7 @@ struct dvb_frontend *horus3a_attach(struct dvb_frontend *fe, priv->i2c_address, priv->i2c); return fe; } -EXPORT_SYMBOL(horus3a_attach); +EXPORT_SYMBOL_GPL(horus3a_attach); MODULE_DESCRIPTION("Sony HORUS3A satellite tuner driver"); MODULE_AUTHOR("Sergey Kozlov "); diff --git a/drivers/media/dvb-frontends/isl6405.c b/drivers/media/dvb-frontends/isl6405.c index 3bc78f8ffc00e36be87bdddb2fb141c14441d5fb..9ca4a354a3926cbccc8f2f93e2ec72f4f4ac3fb5 100644 --- a/drivers/media/dvb-frontends/isl6405.c +++ b/drivers/media/dvb-frontends/isl6405.c @@ -155,7 +155,7 @@ struct dvb_frontend *isl6405_attach(struct dvb_frontend *fe, struct i2c_adapter return fe; } -EXPORT_SYMBOL(isl6405_attach); +EXPORT_SYMBOL_GPL(isl6405_attach); MODULE_DESCRIPTION("Driver for lnb supply and control ic isl6405"); MODULE_AUTHOR("Hartmut Hackmann & Oliver Endriss"); diff --git a/drivers/media/dvb-frontends/isl6421.c b/drivers/media/dvb-frontends/isl6421.c index ae8ec59b665cc8c58318ba4d98d1e449a8135f5c..a3515dbf1017dee3f94eb5cca2ab879d3b16788e 100644 --- a/drivers/media/dvb-frontends/isl6421.c +++ b/drivers/media/dvb-frontends/isl6421.c @@ -227,7 +227,7 @@ struct dvb_frontend *isl6421_attach(struct dvb_frontend *fe, struct i2c_adapter return fe; } -EXPORT_SYMBOL(isl6421_attach); +EXPORT_SYMBOL_GPL(isl6421_attach); MODULE_DESCRIPTION("Driver for lnb supply and control ic isl6421"); MODULE_AUTHOR("Andrew de Quincey & Oliver Endriss"); diff --git a/drivers/media/dvb-frontends/isl6423.c b/drivers/media/dvb-frontends/isl6423.c index 3dd2465d17cf61ba35aeeb56f1d1174fd5d1e038..ea029df731cc5d68a3d107c8552380e16eb0bf95 100644 --- a/drivers/media/dvb-frontends/isl6423.c +++ b/drivers/media/dvb-frontends/isl6423.c @@ -301,7 +301,7 @@ struct dvb_frontend *isl6423_attach(struct dvb_frontend *fe, fe->sec_priv = NULL; return NULL; } -EXPORT_SYMBOL(isl6423_attach); +EXPORT_SYMBOL_GPL(isl6423_attach); MODULE_DESCRIPTION("ISL6423 SEC"); MODULE_AUTHOR("Manu Abraham"); diff --git a/drivers/media/dvb-frontends/itd1000.c b/drivers/media/dvb-frontends/itd1000.c index c3a6e81ae87f86682abf169d305474e5d800d9bc..9d87ef92f60a786429efe583c0d5f6a196d1d6d0 100644 --- a/drivers/media/dvb-frontends/itd1000.c +++ b/drivers/media/dvb-frontends/itd1000.c @@ -399,7 +399,7 @@ struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter return fe; } -EXPORT_SYMBOL(itd1000_attach); +EXPORT_SYMBOL_GPL(itd1000_attach); MODULE_AUTHOR("Patrick Boettcher "); MODULE_DESCRIPTION("Integrant ITD1000 driver"); diff --git a/drivers/media/dvb-frontends/ix2505v.c b/drivers/media/dvb-frontends/ix2505v.c index a30707b61b1fbfff0c6dba3451285224f0cbf7c2..577491354c5fd583ce2ba2a070f040f4d38dfee8 100644 --- a/drivers/media/dvb-frontends/ix2505v.c +++ b/drivers/media/dvb-frontends/ix2505v.c @@ -311,7 +311,7 @@ struct dvb_frontend *ix2505v_attach(struct dvb_frontend *fe, kfree(state); return NULL; } -EXPORT_SYMBOL(ix2505v_attach); +EXPORT_SYMBOL_GPL(ix2505v_attach); module_param_named(debug, ix2505v_debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/l64781.c b/drivers/media/dvb-frontends/l64781.c index 9afb5bf6424bfe5aafb2a62a17f1175eeb81e11d..6a19d4d0d4ade7a2294e7f3cd515cb3784c356a7 100644 --- a/drivers/media/dvb-frontends/l64781.c +++ b/drivers/media/dvb-frontends/l64781.c @@ -605,4 +605,4 @@ MODULE_DESCRIPTION("LSI L64781 DVB-T Demodulator driver"); MODULE_AUTHOR("Holger Waechtler, Marko Kohtala"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(l64781_attach); +EXPORT_SYMBOL_GPL(l64781_attach); diff --git a/drivers/media/dvb-frontends/lg2160.c b/drivers/media/dvb-frontends/lg2160.c index 408151e33fa7f45c604cbd7affe951f1828e1e94..96b271a8247dbfd26921554fb8dbd077ab7afc1c 100644 --- a/drivers/media/dvb-frontends/lg2160.c +++ b/drivers/media/dvb-frontends/lg2160.c @@ -1436,7 +1436,7 @@ struct dvb_frontend *lg2160_attach(const struct lg2160_config *config, return &state->frontend; } -EXPORT_SYMBOL(lg2160_attach); +EXPORT_SYMBOL_GPL(lg2160_attach); MODULE_DESCRIPTION("LG Electronics LG216x ATSC/MH Demodulator Driver"); MODULE_AUTHOR("Michael Krufky "); diff --git a/drivers/media/dvb-frontends/lgdt3305.c b/drivers/media/dvb-frontends/lgdt3305.c index 857e9b4d69b443de0ff0292d387694feba14dc42..7592e9e75bfbb3b30dc3188f4aa9dfbc7c1bfa93 100644 --- a/drivers/media/dvb-frontends/lgdt3305.c +++ b/drivers/media/dvb-frontends/lgdt3305.c @@ -1158,7 +1158,7 @@ struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(lgdt3305_attach); +EXPORT_SYMBOL_GPL(lgdt3305_attach); static const struct dvb_frontend_ops lgdt3304_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/lgdt3306a.c b/drivers/media/dvb-frontends/lgdt3306a.c index 0e1f5daaf20cdfc39e4203ae3661718790655827..567bf0dc92063c880435e0f0ee0024aa2f48d4c9 100644 --- a/drivers/media/dvb-frontends/lgdt3306a.c +++ b/drivers/media/dvb-frontends/lgdt3306a.c @@ -1887,7 +1887,7 @@ struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(lgdt3306a_attach); +EXPORT_SYMBOL_GPL(lgdt3306a_attach); #ifdef DBG_DUMP diff --git a/drivers/media/dvb-frontends/lgdt330x.c b/drivers/media/dvb-frontends/lgdt330x.c index 9ee1c1360ab8435a3c5a6044eee612d3730482f3..b9ae8c838501715b401f11caa067cee563758cfa 100644 --- a/drivers/media/dvb-frontends/lgdt330x.c +++ b/drivers/media/dvb-frontends/lgdt330x.c @@ -938,7 +938,7 @@ struct dvb_frontend *lgdt330x_attach(const struct lgdt330x_config *_config, return lgdt330x_get_dvb_frontend(client); } -EXPORT_SYMBOL(lgdt330x_attach); +EXPORT_SYMBOL_GPL(lgdt330x_attach); static const struct dvb_frontend_ops lgdt3302_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/lgs8gxx.c b/drivers/media/dvb-frontends/lgs8gxx.c index a6bcf1571d10f1d43be8e7361213eb4e49def5c1..f9c1493e80e88c531e51aa9a384e4c06f364c650 100644 --- a/drivers/media/dvb-frontends/lgs8gxx.c +++ b/drivers/media/dvb-frontends/lgs8gxx.c @@ -1053,7 +1053,7 @@ struct dvb_frontend *lgs8gxx_attach(const struct lgs8gxx_config *config, return NULL; } -EXPORT_SYMBOL(lgs8gxx_attach); +EXPORT_SYMBOL_GPL(lgs8gxx_attach); MODULE_DESCRIPTION("Legend Silicon LGS8913/LGS8GXX DMB-TH demodulator driver"); MODULE_AUTHOR("David T. L. Wong "); diff --git a/drivers/media/dvb-frontends/lnbh25.c b/drivers/media/dvb-frontends/lnbh25.c index 0b388502c29807e661b3257e4769de429176e84b..bf1c961a64d0094ecf697c82d43d136bfe637618 100644 --- a/drivers/media/dvb-frontends/lnbh25.c +++ b/drivers/media/dvb-frontends/lnbh25.c @@ -182,7 +182,7 @@ struct dvb_frontend *lnbh25_attach(struct dvb_frontend *fe, __func__, priv->i2c_address); return fe; } -EXPORT_SYMBOL(lnbh25_attach); +EXPORT_SYMBOL_GPL(lnbh25_attach); MODULE_DESCRIPTION("ST LNBH25 driver"); MODULE_AUTHOR("info@netup.ru"); diff --git a/drivers/media/dvb-frontends/lnbp21.c b/drivers/media/dvb-frontends/lnbp21.c index d9966a338a724a847dd0c2465d1d6f99331d6deb..84067d27a8719d7fb9bd3e7e2358f003e177691b 100644 --- a/drivers/media/dvb-frontends/lnbp21.c +++ b/drivers/media/dvb-frontends/lnbp21.c @@ -169,7 +169,7 @@ struct dvb_frontend *lnbh24_attach(struct dvb_frontend *fe, return lnbx2x_attach(fe, i2c, override_set, override_clear, i2c_addr, LNBH24_TTX); } -EXPORT_SYMBOL(lnbh24_attach); +EXPORT_SYMBOL_GPL(lnbh24_attach); struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, u8 override_set, @@ -178,7 +178,7 @@ struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe, return lnbx2x_attach(fe, i2c, override_set, override_clear, 0x08, LNBP21_ISEL); } -EXPORT_SYMBOL(lnbp21_attach); +EXPORT_SYMBOL_GPL(lnbp21_attach); MODULE_DESCRIPTION("Driver for lnb supply and control ic lnbp21, lnbh24"); MODULE_AUTHOR("Oliver Endriss, Igor M. Liplianin"); diff --git a/drivers/media/dvb-frontends/lnbp22.c b/drivers/media/dvb-frontends/lnbp22.c index a62e82bf46f5b4e2722d17b13a896f2add6b4c6c..a4257e07eb7b5e894bb646e25c3683ae2133a2ef 100644 --- a/drivers/media/dvb-frontends/lnbp22.c +++ b/drivers/media/dvb-frontends/lnbp22.c @@ -139,7 +139,7 @@ struct dvb_frontend *lnbp22_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(lnbp22_attach); +EXPORT_SYMBOL_GPL(lnbp22_attach); MODULE_DESCRIPTION("Driver for lnb supply and control ic lnbp22"); MODULE_AUTHOR("Dominik Kuhlen"); diff --git a/drivers/media/dvb-frontends/m88ds3103.c b/drivers/media/dvb-frontends/m88ds3103.c index c25c9279740890a6b08760dfd0d541f9f74cf336..ed4076f1c6e0eeaa5716a37a82bdc37be4ead1d3 100644 --- a/drivers/media/dvb-frontends/m88ds3103.c +++ b/drivers/media/dvb-frontends/m88ds3103.c @@ -1293,7 +1293,7 @@ struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg, *tuner_i2c_adapter = pdata.get_i2c_adapter(client); return pdata.get_dvb_frontend(client); } -EXPORT_SYMBOL(m88ds3103_attach); +EXPORT_SYMBOL_GPL(m88ds3103_attach); static const struct dvb_frontend_ops m88ds3103_ops = { .delsys = {SYS_DVBS, SYS_DVBS2}, diff --git a/drivers/media/dvb-frontends/m88rs2000.c b/drivers/media/dvb-frontends/m88rs2000.c index d5bc85501f9ec196c7ded85a5dfc32abe532bbd6..6338b64e6adb4b2b8bed68687646d4b9908f40af 100644 --- a/drivers/media/dvb-frontends/m88rs2000.c +++ b/drivers/media/dvb-frontends/m88rs2000.c @@ -819,7 +819,7 @@ struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config, return NULL; } -EXPORT_SYMBOL(m88rs2000_attach); +EXPORT_SYMBOL_GPL(m88rs2000_attach); MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver"); MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com"); diff --git a/drivers/media/dvb-frontends/mb86a16.c b/drivers/media/dvb-frontends/mb86a16.c index da505a5d035f3abd5e0808b1b4a48eea610db9ac..ece2c121557617ca8ec0fc3f579496ff7a70c10b 100644 --- a/drivers/media/dvb-frontends/mb86a16.c +++ b/drivers/media/dvb-frontends/mb86a16.c @@ -1863,6 +1863,6 @@ struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(mb86a16_attach); +EXPORT_SYMBOL_GPL(mb86a16_attach); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Manu Abraham"); diff --git a/drivers/media/dvb-frontends/mb86a20s.c b/drivers/media/dvb-frontends/mb86a20s.c index 66fc77db0e75940f5efa82e935dfb4ee31b2414b..84f7e9d043986dcf134a7571e50e494072e7cc8f 100644 --- a/drivers/media/dvb-frontends/mb86a20s.c +++ b/drivers/media/dvb-frontends/mb86a20s.c @@ -2097,7 +2097,7 @@ struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config, dev_info(&i2c->dev, "Detected a Fujitsu mb86a20s frontend\n"); return &state->frontend; } -EXPORT_SYMBOL(mb86a20s_attach); +EXPORT_SYMBOL_GPL(mb86a20s_attach); static const struct dvb_frontend_ops mb86a20s_ops = { .delsys = { SYS_ISDBT }, diff --git a/drivers/media/dvb-frontends/mn88443x.c b/drivers/media/dvb-frontends/mn88443x.c index 53981ff9422e074bff4afa684816c7dab582e2f7..2b6732d40b917eaa0de81c7889cf7fdbf126f5ff 100644 --- a/drivers/media/dvb-frontends/mn88443x.c +++ b/drivers/media/dvb-frontends/mn88443x.c @@ -800,7 +800,7 @@ MODULE_DEVICE_TABLE(i2c, mn88443x_i2c_id); static struct i2c_driver mn88443x_driver = { .driver = { .name = "mn88443x", - .of_match_table = of_match_ptr(mn88443x_of_match), + .of_match_table = mn88443x_of_match, }, .probe = mn88443x_probe, .remove = mn88443x_remove, diff --git a/drivers/media/dvb-frontends/mt312.c b/drivers/media/dvb-frontends/mt312.c index aad07adda37dff25c605e3f1aeb1011c83b17843..208f5d0c083a0390ce51ed2fe27f10e170c97af3 100644 --- a/drivers/media/dvb-frontends/mt312.c +++ b/drivers/media/dvb-frontends/mt312.c @@ -840,7 +840,7 @@ struct dvb_frontend *mt312_attach(const struct mt312_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(mt312_attach); +EXPORT_SYMBOL_GPL(mt312_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/mt352.c b/drivers/media/dvb-frontends/mt352.c index da3e466d50e2e0d98d0e15674a1d24d659df9dc2..2d3c6a5ef4930e5a1c45d859036dabb300edfba8 100644 --- a/drivers/media/dvb-frontends/mt352.c +++ b/drivers/media/dvb-frontends/mt352.c @@ -603,4 +603,4 @@ MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver"); MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(mt352_attach); +EXPORT_SYMBOL_GPL(mt352_attach); diff --git a/drivers/media/dvb-frontends/nxt200x.c b/drivers/media/dvb-frontends/nxt200x.c index 0961e686ff68929c504bd50ca5977da19f9a25ff..01d517922e7b27c6d8ca19d4cc6939cc93d74266 100644 --- a/drivers/media/dvb-frontends/nxt200x.c +++ b/drivers/media/dvb-frontends/nxt200x.c @@ -1242,5 +1242,5 @@ MODULE_DESCRIPTION("NXT200X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulat MODULE_AUTHOR("Kirk Lapray, Michael Krufky, Jean-Francois Thibert, and Taylor Jacob"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(nxt200x_attach); +EXPORT_SYMBOL_GPL(nxt200x_attach); diff --git a/drivers/media/dvb-frontends/nxt6000.c b/drivers/media/dvb-frontends/nxt6000.c index 72e447e8ba649cb37b43e928824583b1b08b497b..4fc817f64be43ee899ffe4d9e662115b69a3aa42 100644 --- a/drivers/media/dvb-frontends/nxt6000.c +++ b/drivers/media/dvb-frontends/nxt6000.c @@ -633,4 +633,4 @@ MODULE_DESCRIPTION("NxtWave NXT6000 DVB-T demodulator driver"); MODULE_AUTHOR("Florian Schirmer"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(nxt6000_attach); +EXPORT_SYMBOL_GPL(nxt6000_attach); diff --git a/drivers/media/dvb-frontends/or51132.c b/drivers/media/dvb-frontends/or51132.c index fc35f37eb3c075c773ee655d2ad2a51f34ac5cf2..fee54db955322b30dc3dc9de254cfa2dcb8c841c 100644 --- a/drivers/media/dvb-frontends/or51132.c +++ b/drivers/media/dvb-frontends/or51132.c @@ -616,4 +616,4 @@ MODULE_AUTHOR("Kirk Lapray"); MODULE_AUTHOR("Trent Piepho"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(or51132_attach); +EXPORT_SYMBOL_GPL(or51132_attach); diff --git a/drivers/media/dvb-frontends/or51211.c b/drivers/media/dvb-frontends/or51211.c index a39bbd8ff1f0dd4477d41d87987b880181dcdc14..fbf2ccf60de66717eaef524f5b7cd5d53f823db4 100644 --- a/drivers/media/dvb-frontends/or51211.c +++ b/drivers/media/dvb-frontends/or51211.c @@ -561,5 +561,5 @@ MODULE_DESCRIPTION("Oren OR51211 VSB [pcHDTV HD-2000] Demodulator Driver"); MODULE_AUTHOR("Kirk Lapray"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(or51211_attach); +EXPORT_SYMBOL_GPL(or51211_attach); diff --git a/drivers/media/dvb-frontends/rtl2832.c b/drivers/media/dvb-frontends/rtl2832.c index 2f1f5cbaf03c46bb312d9962d6a792d9b13acd76..7cad4e985315abb681027334a5abb83bf300dcb0 100644 --- a/drivers/media/dvb-frontends/rtl2832.c +++ b/drivers/media/dvb-frontends/rtl2832.c @@ -653,7 +653,7 @@ static int rtl2832_read_status(struct dvb_frontend *fe, enum fe_status *status) struct i2c_client *client = dev->client; struct dtv_frontend_properties *c = &fe->dtv_property_cache; int ret; - u32 uninitialized_var(tmp); + u32 tmp; u8 u8tmp, buf[2]; u16 u16tmp; diff --git a/drivers/media/dvb-frontends/s5h1409.c b/drivers/media/dvb-frontends/s5h1409.c index ceeb0c3551ceeb7e4facbef865f385648a2d9c5e..47e388faac4a5a65d07c073748e357fa5e6fe229 100644 --- a/drivers/media/dvb-frontends/s5h1409.c +++ b/drivers/media/dvb-frontends/s5h1409.c @@ -993,7 +993,7 @@ struct dvb_frontend *s5h1409_attach(const struct s5h1409_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(s5h1409_attach); +EXPORT_SYMBOL_GPL(s5h1409_attach); static const struct dvb_frontend_ops s5h1409_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/s5h1411.c b/drivers/media/dvb-frontends/s5h1411.c index 98aeed1d2284d1f754bd72a15673903313dc773e..d900874044b2e5e0f64835d02a2a73d998ca63b3 100644 --- a/drivers/media/dvb-frontends/s5h1411.c +++ b/drivers/media/dvb-frontends/s5h1411.c @@ -912,7 +912,7 @@ struct dvb_frontend *s5h1411_attach(const struct s5h1411_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(s5h1411_attach); +EXPORT_SYMBOL_GPL(s5h1411_attach); static const struct dvb_frontend_ops s5h1411_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/s5h1420.c b/drivers/media/dvb-frontends/s5h1420.c index a65cdf8e8cd9a22950543d4749eb17c38d3cfac9..085f08427a6d59735790195da3582ad773a6a09c 100644 --- a/drivers/media/dvb-frontends/s5h1420.c +++ b/drivers/media/dvb-frontends/s5h1420.c @@ -928,7 +928,7 @@ struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(s5h1420_attach); +EXPORT_SYMBOL_GPL(s5h1420_attach); static const struct dvb_frontend_ops s5h1420_ops = { .delsys = { SYS_DVBS }, diff --git a/drivers/media/dvb-frontends/s5h1432.c b/drivers/media/dvb-frontends/s5h1432.c index 4dc3febc0e12ca47bf2036cd37668dd64041a900..f4d6304ed2cefea9153f68dfbb1a1b3a19b0fd60 100644 --- a/drivers/media/dvb-frontends/s5h1432.c +++ b/drivers/media/dvb-frontends/s5h1432.c @@ -364,7 +364,7 @@ struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config, return &state->frontend; } -EXPORT_SYMBOL(s5h1432_attach); +EXPORT_SYMBOL_GPL(s5h1432_attach); static const struct dvb_frontend_ops s5h1432_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/s921.c b/drivers/media/dvb-frontends/s921.c index 79276871112a7524c09ef428109e26d3904dd565..4a492445efd79f392db14d875e4462d3bf1556a4 100644 --- a/drivers/media/dvb-frontends/s921.c +++ b/drivers/media/dvb-frontends/s921.c @@ -503,7 +503,7 @@ struct dvb_frontend *s921_attach(const struct s921_config *config, return &state->frontend; } -EXPORT_SYMBOL(s921_attach); +EXPORT_SYMBOL_GPL(s921_attach); static const struct dvb_frontend_ops s921_ops = { .delsys = { SYS_ISDBT }, diff --git a/drivers/media/dvb-frontends/si21xx.c b/drivers/media/dvb-frontends/si21xx.c index 8546a236d4521f34be068999e068521c12b901c8..fe0b94d3c8b1055113f4b71aeb3336ff697f6e91 100644 --- a/drivers/media/dvb-frontends/si21xx.c +++ b/drivers/media/dvb-frontends/si21xx.c @@ -943,7 +943,7 @@ struct dvb_frontend *si21xx_attach(const struct si21xx_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(si21xx_attach); +EXPORT_SYMBOL_GPL(si21xx_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/sp8870.c b/drivers/media/dvb-frontends/sp8870.c index 3a577788041d5091ad29e39532c602838ba0f1c5..c55bcd809458c8ab918eff31ee816b1f6739a9a4 100644 --- a/drivers/media/dvb-frontends/sp8870.c +++ b/drivers/media/dvb-frontends/sp8870.c @@ -619,4 +619,4 @@ MODULE_DESCRIPTION("Spase SP8870 DVB-T Demodulator driver"); MODULE_AUTHOR("Juergen Peitz"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(sp8870_attach); +EXPORT_SYMBOL_GPL(sp8870_attach); diff --git a/drivers/media/dvb-frontends/sp887x.c b/drivers/media/dvb-frontends/sp887x.c index c02f50995df4da86cf4b0e97e34776fe5bdca349..070c74b67ec6a53e246ebee7e35752a26c014572 100644 --- a/drivers/media/dvb-frontends/sp887x.c +++ b/drivers/media/dvb-frontends/sp887x.c @@ -625,4 +625,4 @@ MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); MODULE_DESCRIPTION("Spase sp887x DVB-T demodulator driver"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(sp887x_attach); +EXPORT_SYMBOL_GPL(sp887x_attach); diff --git a/drivers/media/dvb-frontends/stb0899_drv.c b/drivers/media/dvb-frontends/stb0899_drv.c index 874e9c9125d62fbeef438112d68a5b343b3c1634..6dbc9d890d9c56795fdf37574a0e41349999ecdc 100644 --- a/drivers/media/dvb-frontends/stb0899_drv.c +++ b/drivers/media/dvb-frontends/stb0899_drv.c @@ -1650,7 +1650,7 @@ struct dvb_frontend *stb0899_attach(struct stb0899_config *config, struct i2c_ad kfree(state); return NULL; } -EXPORT_SYMBOL(stb0899_attach); +EXPORT_SYMBOL_GPL(stb0899_attach); MODULE_PARM_DESC(verbose, "Set Verbosity level"); MODULE_AUTHOR("Manu Abraham"); MODULE_DESCRIPTION("STB0899 Multi-Std frontend"); diff --git a/drivers/media/dvb-frontends/stb6000.c b/drivers/media/dvb-frontends/stb6000.c index 786b9eccde0097dea36016f9da607a69912600ef..c5e6ddb0ae88f90513f42aa9c75d61f8636be742 100644 --- a/drivers/media/dvb-frontends/stb6000.c +++ b/drivers/media/dvb-frontends/stb6000.c @@ -245,7 +245,7 @@ struct dvb_frontend *stb6000_attach(struct dvb_frontend *fe, int addr, return fe; } -EXPORT_SYMBOL(stb6000_attach); +EXPORT_SYMBOL_GPL(stb6000_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/stb6100.c b/drivers/media/dvb-frontends/stb6100.c index 30ac584dfab33bf13d2b138e33bab58aac5f68bd..3ea6da8d847d09f1eae950d17db27139eabf8d24 100644 --- a/drivers/media/dvb-frontends/stb6100.c +++ b/drivers/media/dvb-frontends/stb6100.c @@ -569,7 +569,7 @@ static void stb6100_release(struct dvb_frontend *fe) kfree(state); } -EXPORT_SYMBOL(stb6100_attach); +EXPORT_SYMBOL_GPL(stb6100_attach); MODULE_PARM_DESC(verbose, "Set Verbosity level"); MODULE_AUTHOR("Manu Abraham"); diff --git a/drivers/media/dvb-frontends/stv0288.c b/drivers/media/dvb-frontends/stv0288.c index ca5d8e41c114ff967abaecaa4ba2775454a333a6..b2b01fcbbfc813b45c3e9e4434875e7bbb953482 100644 --- a/drivers/media/dvb-frontends/stv0288.c +++ b/drivers/media/dvb-frontends/stv0288.c @@ -602,7 +602,7 @@ struct dvb_frontend *stv0288_attach(const struct stv0288_config *config, return NULL; } -EXPORT_SYMBOL(stv0288_attach); +EXPORT_SYMBOL_GPL(stv0288_attach); module_param(debug_legacy_dish_switch, int, 0444); MODULE_PARM_DESC(debug_legacy_dish_switch, diff --git a/drivers/media/dvb-frontends/stv0297.c b/drivers/media/dvb-frontends/stv0297.c index 3ef31a3a27ffb6863196211bbf219ebdceef6508..f90f97b9216f3fa7d2aff17d761eb8be9e962f3d 100644 --- a/drivers/media/dvb-frontends/stv0297.c +++ b/drivers/media/dvb-frontends/stv0297.c @@ -722,4 +722,4 @@ MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver"); MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(stv0297_attach); +EXPORT_SYMBOL_GPL(stv0297_attach); diff --git a/drivers/media/dvb-frontends/stv0299.c b/drivers/media/dvb-frontends/stv0299.c index 4f466394a16c07ad68d906cb1ab8ee938f3f3aeb..822d9add1ecc91383c8b92fe186ab5e8bf8e45d4 100644 --- a/drivers/media/dvb-frontends/stv0299.c +++ b/drivers/media/dvb-frontends/stv0299.c @@ -763,4 +763,4 @@ MODULE_DESCRIPTION("ST STV0299 DVB Demodulator driver"); MODULE_AUTHOR("Ralph Metzler, Holger Waechtler, Peter Schildmann, Felix Domke, Andreas Oberritter, Andrew de Quincey, Kenneth Aafly"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(stv0299_attach); +EXPORT_SYMBOL_GPL(stv0299_attach); diff --git a/drivers/media/dvb-frontends/stv0367.c b/drivers/media/dvb-frontends/stv0367.c index 5b91e740e13581b05c08fc092da920f5043e3022..49f4472f09fa8369604ff8fb845bf2a86d542320 100644 --- a/drivers/media/dvb-frontends/stv0367.c +++ b/drivers/media/dvb-frontends/stv0367.c @@ -1760,7 +1760,7 @@ struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(stv0367ter_attach); +EXPORT_SYMBOL_GPL(stv0367ter_attach); static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable) { @@ -2933,7 +2933,7 @@ struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(stv0367cab_attach); +EXPORT_SYMBOL_GPL(stv0367cab_attach); /* * Functions for operation on Digital Devices hardware @@ -3354,7 +3354,7 @@ struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(stv0367ddb_attach); +EXPORT_SYMBOL_GPL(stv0367ddb_attach); MODULE_PARM_DESC(debug, "Set debug"); MODULE_PARM_DESC(i2c_debug, "Set i2c debug"); diff --git a/drivers/media/dvb-frontends/stv0900_core.c b/drivers/media/dvb-frontends/stv0900_core.c index 254618a06140a2abcaf2c21298fb55ee3e6a122b..272a408dadc646ab5114269f4c6e36cd5b97088c 100644 --- a/drivers/media/dvb-frontends/stv0900_core.c +++ b/drivers/media/dvb-frontends/stv0900_core.c @@ -1967,7 +1967,7 @@ struct dvb_frontend *stv0900_attach(const struct stv0900_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(stv0900_attach); +EXPORT_SYMBOL_GPL(stv0900_attach); MODULE_PARM_DESC(debug, "Set debug"); diff --git a/drivers/media/dvb-frontends/stv6110.c b/drivers/media/dvb-frontends/stv6110.c index 7db9a5bceccc5e1f0e405e436c9533f856a1d50c..adb881c77acb4be8899c0c6a76b0d56d64c7aee9 100644 --- a/drivers/media/dvb-frontends/stv6110.c +++ b/drivers/media/dvb-frontends/stv6110.c @@ -437,7 +437,7 @@ struct dvb_frontend *stv6110_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(stv6110_attach); +EXPORT_SYMBOL_GPL(stv6110_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/stv6110x.c b/drivers/media/dvb-frontends/stv6110x.c index 82c002d3833a919b066eab75dc8269ba12bba4f1..6d87e271ff58f366fe09442f89f4b3093ea79829 100644 --- a/drivers/media/dvb-frontends/stv6110x.c +++ b/drivers/media/dvb-frontends/stv6110x.c @@ -408,7 +408,7 @@ const struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe, printk(KERN_INFO "%s: Attaching STV6110x\n", __func__); return stv6110x->devctl; } -EXPORT_SYMBOL(stv6110x_attach); +EXPORT_SYMBOL_GPL(stv6110x_attach); MODULE_AUTHOR("Manu Abraham"); MODULE_DESCRIPTION("STV6110x Silicon tuner"); diff --git a/drivers/media/dvb-frontends/tda10021.c b/drivers/media/dvb-frontends/tda10021.c index 5cd885d4ea04f2243f48e86a3344832245dba872..d765b72928ef93a4ee2b8cde6a3b64838b44010b 100644 --- a/drivers/media/dvb-frontends/tda10021.c +++ b/drivers/media/dvb-frontends/tda10021.c @@ -525,4 +525,4 @@ MODULE_DESCRIPTION("Philips TDA10021 DVB-C demodulator driver"); MODULE_AUTHOR("Ralph Metzler, Holger Waechtler, Markus Schulz"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(tda10021_attach); +EXPORT_SYMBOL_GPL(tda10021_attach); diff --git a/drivers/media/dvb-frontends/tda10023.c b/drivers/media/dvb-frontends/tda10023.c index 0a9a54563ebefb694575d4d45f69d47fd83765cd..c3d0e5057336378474b64ce09ad456ef945a54ae 100644 --- a/drivers/media/dvb-frontends/tda10023.c +++ b/drivers/media/dvb-frontends/tda10023.c @@ -606,4 +606,4 @@ MODULE_DESCRIPTION("Philips TDA10023 DVB-C demodulator driver"); MODULE_AUTHOR("Georg Acher, Hartmut Birr"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(tda10023_attach); +EXPORT_SYMBOL_GPL(tda10023_attach); diff --git a/drivers/media/dvb-frontends/tda10048.c b/drivers/media/dvb-frontends/tda10048.c index c01d60a88af295d72cbd44f094311e465b76e000..6ca1b25542c5c0ca0189034caffa1b3b94707195 100644 --- a/drivers/media/dvb-frontends/tda10048.c +++ b/drivers/media/dvb-frontends/tda10048.c @@ -1150,7 +1150,7 @@ struct dvb_frontend *tda10048_attach(const struct tda10048_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(tda10048_attach); +EXPORT_SYMBOL_GPL(tda10048_attach); static const struct dvb_frontend_ops tda10048_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/tda1004x.c b/drivers/media/dvb-frontends/tda1004x.c index e506f66657bbfeba72b15c6e7cd29fb4e66d00c4..57bb83e4d4c71f70610dcf9b06908f59409f4084 100644 --- a/drivers/media/dvb-frontends/tda1004x.c +++ b/drivers/media/dvb-frontends/tda1004x.c @@ -1391,5 +1391,5 @@ MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator"); MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(tda10045_attach); -EXPORT_SYMBOL(tda10046_attach); +EXPORT_SYMBOL_GPL(tda10045_attach); +EXPORT_SYMBOL_GPL(tda10046_attach); diff --git a/drivers/media/dvb-frontends/tda10086.c b/drivers/media/dvb-frontends/tda10086.c index 8323e4e53d661b86bef6ec0052eb4e67c376f513..a3457a915dc8f5a1a3bd7afaea0d5d0efda3757a 100644 --- a/drivers/media/dvb-frontends/tda10086.c +++ b/drivers/media/dvb-frontends/tda10086.c @@ -777,4 +777,4 @@ MODULE_DESCRIPTION("Philips TDA10086 DVB-S Demodulator"); MODULE_AUTHOR("Andrew de Quincey"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(tda10086_attach); +EXPORT_SYMBOL_GPL(tda10086_attach); diff --git a/drivers/media/dvb-frontends/tda665x.c b/drivers/media/dvb-frontends/tda665x.c index 8766c9ff6680a22c152c328ab7d6d976cde233c1..d1ccdf19a146eb7c069f0874cbb39c5a55a8c80e 100644 --- a/drivers/media/dvb-frontends/tda665x.c +++ b/drivers/media/dvb-frontends/tda665x.c @@ -239,7 +239,7 @@ struct dvb_frontend *tda665x_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(tda665x_attach); +EXPORT_SYMBOL_GPL(tda665x_attach); MODULE_DESCRIPTION("TDA665x driver"); MODULE_AUTHOR("Manu Abraham"); diff --git a/drivers/media/dvb-frontends/tda8083.c b/drivers/media/dvb-frontends/tda8083.c index 53b26060db7e2d291f6c13fff26d736f0fcf4191..721513ecdbe88297722c845d18cad0e4e6958db3 100644 --- a/drivers/media/dvb-frontends/tda8083.c +++ b/drivers/media/dvb-frontends/tda8083.c @@ -493,4 +493,4 @@ MODULE_DESCRIPTION("Philips TDA8083 DVB-S Demodulator"); MODULE_AUTHOR("Ralph Metzler, Holger Waechtler"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(tda8083_attach); +EXPORT_SYMBOL_GPL(tda8083_attach); diff --git a/drivers/media/dvb-frontends/tda8261.c b/drivers/media/dvb-frontends/tda8261.c index 500f50b81b668e00a07cd65c2794c8d86293e18a..50e25ded308496661a465cb66ce989306097a534 100644 --- a/drivers/media/dvb-frontends/tda8261.c +++ b/drivers/media/dvb-frontends/tda8261.c @@ -200,7 +200,7 @@ struct dvb_frontend *tda8261_attach(struct dvb_frontend *fe, return NULL; } -EXPORT_SYMBOL(tda8261_attach); +EXPORT_SYMBOL_GPL(tda8261_attach); MODULE_AUTHOR("Manu Abraham"); MODULE_DESCRIPTION("TDA8261 8PSK/QPSK Tuner"); diff --git a/drivers/media/dvb-frontends/tda826x.c b/drivers/media/dvb-frontends/tda826x.c index 100da5d5fdc5c1c62386e9b57eda4aed11025795..c5dd1e6a358d38d15900d60147f900d083404d6e 100644 --- a/drivers/media/dvb-frontends/tda826x.c +++ b/drivers/media/dvb-frontends/tda826x.c @@ -177,7 +177,7 @@ struct dvb_frontend *tda826x_attach(struct dvb_frontend *fe, int addr, struct i2 return fe; } -EXPORT_SYMBOL(tda826x_attach); +EXPORT_SYMBOL_GPL(tda826x_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/ts2020.c b/drivers/media/dvb-frontends/ts2020.c index 3e3e408786332f7554cfddaed447d5a61268210b..1bcf822078ebe832b51d313a26a1c33d5c3e5ea2 100644 --- a/drivers/media/dvb-frontends/ts2020.c +++ b/drivers/media/dvb-frontends/ts2020.c @@ -534,7 +534,7 @@ struct dvb_frontend *ts2020_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(ts2020_attach); +EXPORT_SYMBOL_GPL(ts2020_attach); /* * We implement own regmap locking due to legacy DVB attach which uses frontend diff --git a/drivers/media/dvb-frontends/tua6100.c b/drivers/media/dvb-frontends/tua6100.c index e6aaf4973aef47bdf8e84628bf5aa471734b2b96..647182eb5fa4f2d0c81e544ae116940d05c7d600 100644 --- a/drivers/media/dvb-frontends/tua6100.c +++ b/drivers/media/dvb-frontends/tua6100.c @@ -194,7 +194,7 @@ struct dvb_frontend *tua6100_attach(struct dvb_frontend *fe, int addr, struct i2 fe->tuner_priv = priv; return fe; } -EXPORT_SYMBOL(tua6100_attach); +EXPORT_SYMBOL_GPL(tua6100_attach); MODULE_DESCRIPTION("DVB tua6100 driver"); MODULE_AUTHOR("Andrew de Quincey"); diff --git a/drivers/media/dvb-frontends/ves1820.c b/drivers/media/dvb-frontends/ves1820.c index eb1249d81310a8139a9ca200e2b0bf42bee18c74..56e71e780fdd997ec318fd3f9cfeca5d2303ebb1 100644 --- a/drivers/media/dvb-frontends/ves1820.c +++ b/drivers/media/dvb-frontends/ves1820.c @@ -446,4 +446,4 @@ MODULE_DESCRIPTION("VLSI VES1820 DVB-C Demodulator driver"); MODULE_AUTHOR("Ralph Metzler, Holger Waechtler"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(ves1820_attach); +EXPORT_SYMBOL_GPL(ves1820_attach); diff --git a/drivers/media/dvb-frontends/ves1x93.c b/drivers/media/dvb-frontends/ves1x93.c index ddc5bfd84cd58c3186b11b33e4e0e1ae25f96338..071c59057e6dd06d9a43208d673f566b057214e2 100644 --- a/drivers/media/dvb-frontends/ves1x93.c +++ b/drivers/media/dvb-frontends/ves1x93.c @@ -553,4 +553,4 @@ MODULE_DESCRIPTION("VLSI VES1x93 DVB-S Demodulator driver"); MODULE_AUTHOR("Ralph Metzler"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(ves1x93_attach); +EXPORT_SYMBOL_GPL(ves1x93_attach); diff --git a/drivers/media/dvb-frontends/zl10036.c b/drivers/media/dvb-frontends/zl10036.c index f1c92338015d1dde90b272f217fdd3e53c205cfa..cd1156c18a8bf3d66af84d1733bf7f8a10806890 100644 --- a/drivers/media/dvb-frontends/zl10036.c +++ b/drivers/media/dvb-frontends/zl10036.c @@ -504,7 +504,7 @@ struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe, kfree(state); return NULL; } -EXPORT_SYMBOL(zl10036_attach); +EXPORT_SYMBOL_GPL(zl10036_attach); module_param_named(debug, zl10036_debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/zl10039.c b/drivers/media/dvb-frontends/zl10039.c index 6293bd920fa613aae8f7f629688a71283ca299d2..b3a76c00fe88609558bf88f9245a0bcaa2c65d6a 100644 --- a/drivers/media/dvb-frontends/zl10039.c +++ b/drivers/media/dvb-frontends/zl10039.c @@ -304,7 +304,7 @@ struct dvb_frontend *zl10039_attach(struct dvb_frontend *fe, kfree(state); return NULL; } -EXPORT_SYMBOL(zl10039_attach); +EXPORT_SYMBOL_GPL(zl10039_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/zl10353.c b/drivers/media/dvb-frontends/zl10353.c index 42e63a3fa121c05e55dc9d36190b32fc6e51d8ff..e2a5dfe93732499285226ce9ea27a2e2e50184a9 100644 --- a/drivers/media/dvb-frontends/zl10353.c +++ b/drivers/media/dvb-frontends/zl10353.c @@ -675,4 +675,4 @@ MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver"); MODULE_AUTHOR("Chris Pascoe"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(zl10353_attach); +EXPORT_SYMBOL_GPL(zl10353_attach); diff --git a/drivers/media/i2c/m5mols/m5mols_core.c b/drivers/media/i2c/m5mols/m5mols_core.c index d9a96443060965bb84fad28be502dc318f83ff9e..9e6827dedab30001c694a0129677e68730994875 100644 --- a/drivers/media/i2c/m5mols/m5mols_core.c +++ b/drivers/media/i2c/m5mols/m5mols_core.c @@ -492,7 +492,7 @@ static enum m5mols_restype __find_restype(u32 code) do { if (code == m5mols_default_ffmt[type].code) return type; - } while (type++ != SIZE_DEFAULT_FFMT); + } while (++type != SIZE_DEFAULT_FFMT); return 0; } diff --git a/drivers/media/i2c/ov2680.c b/drivers/media/i2c/ov2680.c index d8798fb714ba8a6d3cbf44769ecd61c440aff2a0..40d583a972a41e8ad3ba0d509f189d80e99f43ec 100644 --- a/drivers/media/i2c/ov2680.c +++ b/drivers/media/i2c/ov2680.c @@ -85,15 +85,8 @@ struct ov2680_mode_info { struct ov2680_ctrls { struct v4l2_ctrl_handler handler; - struct { - struct v4l2_ctrl *auto_exp; - struct v4l2_ctrl *exposure; - }; - struct { - struct v4l2_ctrl *auto_gain; - struct v4l2_ctrl *gain; - }; - + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *gain; struct v4l2_ctrl *hflip; struct v4l2_ctrl *vflip; struct v4l2_ctrl *test_pattern; @@ -143,6 +136,7 @@ static const struct reg_value ov2680_setting_30fps_QUXGA_800_600[] = { {0x380e, 0x02}, {0x380f, 0x84}, {0x3811, 0x04}, {0x3813, 0x04}, {0x3814, 0x31}, {0x3815, 0x31}, {0x3820, 0xc0}, {0x4008, 0x00}, {0x4009, 0x03}, {0x4837, 0x1e}, {0x3501, 0x4e}, {0x3502, 0xe0}, + {0x3503, 0x03}, }; static const struct reg_value ov2680_setting_30fps_720P_1280_720[] = { @@ -321,70 +315,49 @@ static void ov2680_power_down(struct ov2680_dev *sensor) usleep_range(5000, 10000); } -static int ov2680_bayer_order(struct ov2680_dev *sensor) +static void ov2680_set_bayer_order(struct ov2680_dev *sensor) { - u32 format1; - u32 format2; - u32 hv_flip; - int ret; - - ret = ov2680_read_reg(sensor, OV2680_REG_FORMAT1, &format1); - if (ret < 0) - return ret; + int hv_flip = 0; - ret = ov2680_read_reg(sensor, OV2680_REG_FORMAT2, &format2); - if (ret < 0) - return ret; + if (sensor->ctrls.vflip && sensor->ctrls.vflip->val) + hv_flip += 1; - hv_flip = (format2 & BIT(2) << 1) | (format1 & BIT(2)); + if (sensor->ctrls.hflip && sensor->ctrls.hflip->val) + hv_flip += 2; sensor->fmt.code = ov2680_hv_flip_bayer_order[hv_flip]; - - return 0; } -static int ov2680_vflip_enable(struct ov2680_dev *sensor) +static int ov2680_set_vflip(struct ov2680_dev *sensor, s32 val) { int ret; - ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT1, BIT(2), BIT(2)); - if (ret < 0) - return ret; - - return ov2680_bayer_order(sensor); -} - -static int ov2680_vflip_disable(struct ov2680_dev *sensor) -{ - int ret; + if (sensor->is_streaming) + return -EBUSY; - ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT1, BIT(2), BIT(0)); + ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT1, + BIT(2), val ? BIT(2) : 0); if (ret < 0) return ret; - return ov2680_bayer_order(sensor); + ov2680_set_bayer_order(sensor); + return 0; } -static int ov2680_hflip_enable(struct ov2680_dev *sensor) +static int ov2680_set_hflip(struct ov2680_dev *sensor, s32 val) { int ret; - ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT2, BIT(2), BIT(2)); - if (ret < 0) - return ret; - - return ov2680_bayer_order(sensor); -} - -static int ov2680_hflip_disable(struct ov2680_dev *sensor) -{ - int ret; + if (sensor->is_streaming) + return -EBUSY; - ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT2, BIT(2), BIT(0)); + ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT2, + BIT(2), val ? BIT(2) : 0); if (ret < 0) return ret; - return ov2680_bayer_order(sensor); + ov2680_set_bayer_order(sensor); + return 0; } static int ov2680_test_pattern_set(struct ov2680_dev *sensor, int value) @@ -405,69 +378,15 @@ static int ov2680_test_pattern_set(struct ov2680_dev *sensor, int value) return 0; } -static int ov2680_gain_set(struct ov2680_dev *sensor, bool auto_gain) +static int ov2680_gain_set(struct ov2680_dev *sensor, u32 gain) { - struct ov2680_ctrls *ctrls = &sensor->ctrls; - u32 gain; - int ret; - - ret = ov2680_mod_reg(sensor, OV2680_REG_R_MANUAL, BIT(1), - auto_gain ? 0 : BIT(1)); - if (ret < 0) - return ret; - - if (auto_gain || !ctrls->gain->is_new) - return 0; - - gain = ctrls->gain->val; - - ret = ov2680_write_reg16(sensor, OV2680_REG_GAIN_PK, gain); - - return 0; + return ov2680_write_reg16(sensor, OV2680_REG_GAIN_PK, gain); } -static int ov2680_gain_get(struct ov2680_dev *sensor) +static int ov2680_exposure_set(struct ov2680_dev *sensor, u32 exp) { - u32 gain; - int ret; - - ret = ov2680_read_reg16(sensor, OV2680_REG_GAIN_PK, &gain); - if (ret) - return ret; - - return gain; -} - -static int ov2680_exposure_set(struct ov2680_dev *sensor, bool auto_exp) -{ - struct ov2680_ctrls *ctrls = &sensor->ctrls; - u32 exp; - int ret; - - ret = ov2680_mod_reg(sensor, OV2680_REG_R_MANUAL, BIT(0), - auto_exp ? 0 : BIT(0)); - if (ret < 0) - return ret; - - if (auto_exp || !ctrls->exposure->is_new) - return 0; - - exp = (u32)ctrls->exposure->val; - exp <<= 4; - - return ov2680_write_reg24(sensor, OV2680_REG_EXPOSURE_PK_HIGH, exp); -} - -static int ov2680_exposure_get(struct ov2680_dev *sensor) -{ - int ret; - u32 exp; - - ret = ov2680_read_reg24(sensor, OV2680_REG_EXPOSURE_PK_HIGH, &exp); - if (ret) - return ret; - - return exp >> 4; + return ov2680_write_reg24(sensor, OV2680_REG_EXPOSURE_PK_HIGH, + exp << 4); } static int ov2680_stream_enable(struct ov2680_dev *sensor) @@ -482,33 +401,17 @@ static int ov2680_stream_disable(struct ov2680_dev *sensor) static int ov2680_mode_set(struct ov2680_dev *sensor) { - struct ov2680_ctrls *ctrls = &sensor->ctrls; int ret; - ret = ov2680_gain_set(sensor, false); + ret = ov2680_load_regs(sensor, sensor->current_mode); if (ret < 0) return ret; - ret = ov2680_exposure_set(sensor, false); + /* Restore value of all ctrls */ + ret = __v4l2_ctrl_handler_setup(&sensor->ctrls.handler); if (ret < 0) return ret; - ret = ov2680_load_regs(sensor, sensor->current_mode); - if (ret < 0) - return ret; - - if (ctrls->auto_gain->val) { - ret = ov2680_gain_set(sensor, true); - if (ret < 0) - return ret; - } - - if (ctrls->auto_exp->val == V4L2_EXPOSURE_AUTO) { - ret = ov2680_exposure_set(sensor, true); - if (ret < 0) - return ret; - } - sensor->mode_pending_changes = false; return 0; @@ -556,7 +459,7 @@ static int ov2680_power_on(struct ov2680_dev *sensor) ret = ov2680_write_reg(sensor, OV2680_REG_SOFT_RESET, 0x01); if (ret != 0) { dev_err(dev, "sensor soft reset failed\n"); - return ret; + goto err_disable_regulators; } usleep_range(1000, 2000); } else { @@ -566,7 +469,7 @@ static int ov2680_power_on(struct ov2680_dev *sensor) ret = clk_prepare_enable(sensor->xvclk); if (ret < 0) - return ret; + goto err_disable_regulators; sensor->is_enabled = true; @@ -576,6 +479,10 @@ static int ov2680_power_on(struct ov2680_dev *sensor) ov2680_stream_disable(sensor); return 0; + +err_disable_regulators: + regulator_bulk_disable(OV2680_NUM_SUPPLIES, sensor->supplies); + return ret; } static int ov2680_s_power(struct v4l2_subdev *sd, int on) @@ -590,15 +497,10 @@ static int ov2680_s_power(struct v4l2_subdev *sd, int on) else ret = ov2680_power_off(sensor); - mutex_unlock(&sensor->lock); - - if (on && ret == 0) { - ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler); - if (ret < 0) - return ret; - + if (on && ret == 0) ret = ov2680_mode_restore(sensor); - } + + mutex_unlock(&sensor->lock); return ret; } @@ -796,66 +698,23 @@ static int ov2680_enum_frame_interval(struct v4l2_subdev *sd, return 0; } -static int ov2680_g_volatile_ctrl(struct v4l2_ctrl *ctrl) -{ - struct v4l2_subdev *sd = ctrl_to_sd(ctrl); - struct ov2680_dev *sensor = to_ov2680_dev(sd); - struct ov2680_ctrls *ctrls = &sensor->ctrls; - int val; - - if (!sensor->is_enabled) - return 0; - - switch (ctrl->id) { - case V4L2_CID_GAIN: - val = ov2680_gain_get(sensor); - if (val < 0) - return val; - ctrls->gain->val = val; - break; - case V4L2_CID_EXPOSURE: - val = ov2680_exposure_get(sensor); - if (val < 0) - return val; - ctrls->exposure->val = val; - break; - } - - return 0; -} - static int ov2680_s_ctrl(struct v4l2_ctrl *ctrl) { struct v4l2_subdev *sd = ctrl_to_sd(ctrl); struct ov2680_dev *sensor = to_ov2680_dev(sd); - struct ov2680_ctrls *ctrls = &sensor->ctrls; if (!sensor->is_enabled) return 0; switch (ctrl->id) { - case V4L2_CID_AUTOGAIN: - return ov2680_gain_set(sensor, !!ctrl->val); case V4L2_CID_GAIN: - return ov2680_gain_set(sensor, !!ctrls->auto_gain->val); - case V4L2_CID_EXPOSURE_AUTO: - return ov2680_exposure_set(sensor, !!ctrl->val); + return ov2680_gain_set(sensor, ctrl->val); case V4L2_CID_EXPOSURE: - return ov2680_exposure_set(sensor, !!ctrls->auto_exp->val); + return ov2680_exposure_set(sensor, ctrl->val); case V4L2_CID_VFLIP: - if (sensor->is_streaming) - return -EBUSY; - if (ctrl->val) - return ov2680_vflip_enable(sensor); - else - return ov2680_vflip_disable(sensor); + return ov2680_set_vflip(sensor, ctrl->val); case V4L2_CID_HFLIP: - if (sensor->is_streaming) - return -EBUSY; - if (ctrl->val) - return ov2680_hflip_enable(sensor); - else - return ov2680_hflip_disable(sensor); + return ov2680_set_hflip(sensor, ctrl->val); case V4L2_CID_TEST_PATTERN: return ov2680_test_pattern_set(sensor, ctrl->val); default: @@ -866,7 +725,6 @@ static int ov2680_s_ctrl(struct v4l2_ctrl *ctrl) } static const struct v4l2_ctrl_ops ov2680_ctrl_ops = { - .g_volatile_ctrl = ov2680_g_volatile_ctrl, .s_ctrl = ov2680_s_ctrl, }; @@ -938,7 +796,7 @@ static int ov2680_v4l2_init(struct ov2680_dev *sensor) if (ret < 0) return ret; - v4l2_ctrl_handler_init(hdl, 7); + v4l2_ctrl_handler_init(hdl, 5); hdl->lock = &sensor->lock; @@ -950,16 +808,9 @@ static int ov2680_v4l2_init(struct ov2680_dev *sensor) ARRAY_SIZE(test_pattern_menu) - 1, 0, 0, test_pattern_menu); - ctrls->auto_exp = v4l2_ctrl_new_std_menu(hdl, ops, - V4L2_CID_EXPOSURE_AUTO, - V4L2_EXPOSURE_MANUAL, 0, - V4L2_EXPOSURE_AUTO); - ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE, 0, 32767, 1, 0); - ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTOGAIN, - 0, 1, 1, 1); ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, 0, 2047, 1, 0); if (hdl->error) { @@ -967,11 +818,8 @@ static int ov2680_v4l2_init(struct ov2680_dev *sensor) goto cleanup_entity; } - ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE; - ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE; - - v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true); - v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true); + ctrls->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; + ctrls->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; sensor->sd.ctrl_handler = hdl; diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c index aa9c0b7ee7a22c25a5726650272c78968ff489b7..31b26b18e525176862bbca2cfee7642b8bde6d85 100644 --- a/drivers/media/i2c/ov5640.c +++ b/drivers/media/i2c/ov5640.c @@ -2447,7 +2447,7 @@ static int ov5640_init_controls(struct ov5640_dev *sensor) /* Auto/manual gain */ ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTOGAIN, 0, 1, 1, 1); - ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, + ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN, 0, 1023, 1, 0); ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, diff --git a/drivers/media/i2c/ov7670.c b/drivers/media/i2c/ov7670.c index 1f71c14c8aab48fde55b1dbe1d1524608f253f73..4f906d25ce5ca223bfa1723e426d4e8f68c44d86 100644 --- a/drivers/media/i2c/ov7670.c +++ b/drivers/media/i2c/ov7670.c @@ -1750,7 +1750,7 @@ static int ov7670_parse_dt(struct device *dev, if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) { dev_err(dev, "Unsupported media bus type\n"); - return ret; + return -EINVAL; } info->mbus_config = bus_cfg.bus.parallel.flags; diff --git a/drivers/media/i2c/ov772x.c b/drivers/media/i2c/ov772x.c index 4eae5f2f7d3183d22cca5c42377b935d8aaf4a78..11deaec9afbfbd289db3e0f772d3e65a00c20ef8 100644 --- a/drivers/media/i2c/ov772x.c +++ b/drivers/media/i2c/ov772x.c @@ -1424,7 +1424,7 @@ static int ov772x_probe(struct i2c_client *client, priv->subdev.ctrl_handler = &priv->hdl; if (priv->hdl.error) { ret = priv->hdl.error; - goto error_mutex_destroy; + goto error_ctrl_free; } priv->clk = clk_get(&client->dev, NULL); @@ -1473,7 +1473,6 @@ static int ov772x_probe(struct i2c_client *client, clk_put(priv->clk); error_ctrl_free: v4l2_ctrl_handler_free(&priv->hdl); -error_mutex_destroy: mutex_destroy(&priv->lock); return ret; diff --git a/drivers/media/pci/bt8xx/bttv-driver.c b/drivers/media/pci/bt8xx/bttv-driver.c index 4c042ba6de9187714524453349928e313a96d6e4..2f75f52777b9d34c2448351639996199ea2c43bd 100644 --- a/drivers/media/pci/bt8xx/bttv-driver.c +++ b/drivers/media/pci/bt8xx/bttv-driver.c @@ -4300,6 +4300,7 @@ static void bttv_remove(struct pci_dev *pci_dev) /* free resources */ free_irq(btv->c.pci->irq,btv); + del_timer_sync(&btv->timeout); iounmap(btv->bt848_mmio); release_mem_region(pci_resource_start(btv->c.pci,0), pci_resource_len(btv->c.pci,0)); diff --git a/drivers/media/pci/bt8xx/dst.c b/drivers/media/pci/bt8xx/dst.c index b98de2a22f78abfb9adeb5972c4bd8b6b6a48afd..0e52a8be03eb318af46d5028eeb247845fb2f4ce 100644 --- a/drivers/media/pci/bt8xx/dst.c +++ b/drivers/media/pci/bt8xx/dst.c @@ -1733,7 +1733,7 @@ struct dst_state *dst_attach(struct dst_state *state, struct dvb_adapter *dvb_ad return state; /* Manu (DST is a card not a frontend) */ } -EXPORT_SYMBOL(dst_attach); +EXPORT_SYMBOL_GPL(dst_attach); static const struct dvb_frontend_ops dst_dvbt_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/pci/bt8xx/dst_ca.c b/drivers/media/pci/bt8xx/dst_ca.c index 0a7623c0fc8ef2f55f62b8857b9669a350610542..d4c5fe2c186ba0e97a195c38a876d9da427fde30 100644 --- a/drivers/media/pci/bt8xx/dst_ca.c +++ b/drivers/media/pci/bt8xx/dst_ca.c @@ -680,7 +680,7 @@ struct dvb_device *dst_ca_attach(struct dst_state *dst, struct dvb_adapter *dvb_ return NULL; } -EXPORT_SYMBOL(dst_ca_attach); +EXPORT_SYMBOL_GPL(dst_ca_attach); MODULE_DESCRIPTION("DST DVB-S/T/C Combo CA driver"); MODULE_AUTHOR("Manu Abraham"); diff --git a/drivers/media/pci/cx23885/cx23885-video.c b/drivers/media/pci/cx23885/cx23885-video.c index 2a20c7165e1e8c71ebf3ef3814c9688e6a0a39fe..16564899f114105e2c24a4bc877d660760fad8a3 100644 --- a/drivers/media/pci/cx23885/cx23885-video.c +++ b/drivers/media/pci/cx23885/cx23885-video.c @@ -420,7 +420,7 @@ static int buffer_prepare(struct vb2_buffer *vb) dev->height >> 1); break; default: - BUG(); + return -EINVAL; /* should not happen */ } dprintk(2, "[%p/%d] buffer_init - %dx%d %dbpp \"%s\" - dma=0x%08lx\n", buf, buf->vb.vb2_buf.index, diff --git a/drivers/media/pci/dm1105/dm1105.c b/drivers/media/pci/dm1105/dm1105.c index 1ddb0576fb7b1af37d8c681d925df6260bc2ff4a..dc3fc69e448062d09844bec5ced2e8b8d053f3f4 100644 --- a/drivers/media/pci/dm1105/dm1105.c +++ b/drivers/media/pci/dm1105/dm1105.c @@ -1188,6 +1188,7 @@ static void dm1105_remove(struct pci_dev *pdev) struct dvb_demux *dvbdemux = &dev->demux; struct dmx_demux *dmx = &dvbdemux->dmx; + cancel_work_sync(&dev->ir.work); dm1105_ir_exit(dev); dmx->close(dmx); dvb_net_release(&dev->dvbnet); diff --git a/drivers/media/pci/intel/ipu3/ipu3-cio2.c b/drivers/media/pci/intel/ipu3/ipu3-cio2.c index cdf4d07343a71d5b5ede4b387160205d97cd7a41..2c037538c7d8fecc31a2ea0863b419b9a8c8ab27 100644 --- a/drivers/media/pci/intel/ipu3/ipu3-cio2.c +++ b/drivers/media/pci/intel/ipu3/ipu3-cio2.c @@ -361,7 +361,7 @@ static int cio2_hw_init(struct cio2_device *cio2, struct cio2_queue *q) void __iomem *const base = cio2->base; u8 lanes, csi2bus = q->csi2.port; u8 sensor_vc = SENSOR_VIR_CH_DFLT; - struct cio2_csi2_timing timing; + struct cio2_csi2_timing timing = { 0 }; int i, r; fmt = cio2_find_format(NULL, &q->subdev_fmt.code); @@ -1860,6 +1860,9 @@ static void cio2_pci_remove(struct pci_dev *pci_dev) v4l2_device_unregister(&cio2->v4l2_dev); media_device_cleanup(&cio2->media_dev); mutex_destroy(&cio2->lock); + + pm_runtime_forbid(&pci_dev->dev); + pm_runtime_get_noresume(&pci_dev->dev); } static int __maybe_unused cio2_runtime_suspend(struct device *dev) diff --git a/drivers/media/pci/netup_unidvb/netup_unidvb_core.c b/drivers/media/pci/netup_unidvb/netup_unidvb_core.c index de3fc62810e6ca5e8bc72de84721496d3ed7c3bf..28381698f2e16715e7a3a596677c8ba4fd88861e 100644 --- a/drivers/media/pci/netup_unidvb/netup_unidvb_core.c +++ b/drivers/media/pci/netup_unidvb/netup_unidvb_core.c @@ -706,7 +706,7 @@ static void netup_unidvb_dma_fini(struct netup_unidvb_dev *ndev, int num) netup_unidvb_dma_enable(dma, 0); msleep(50); cancel_work_sync(&dma->work); - del_timer(&dma->timeout); + del_timer_sync(&dma->timeout); } static int netup_unidvb_dma_setup(struct netup_unidvb_dev *ndev) @@ -896,12 +896,7 @@ static int netup_unidvb_initdev(struct pci_dev *pci_dev, ndev->lmmio0, (u32)pci_resource_len(pci_dev, 0), ndev->lmmio1, (u32)pci_resource_len(pci_dev, 1), pci_dev->irq); - if (request_irq(pci_dev->irq, netup_unidvb_isr, IRQF_SHARED, - "netup_unidvb", pci_dev) < 0) { - dev_err(&pci_dev->dev, - "%s(): can't get IRQ %d\n", __func__, pci_dev->irq); - goto irq_request_err; - } + ndev->dma_size = 2 * 188 * NETUP_DMA_BLOCKS_COUNT * NETUP_DMA_PACKETS_COUNT; ndev->dma_virt = dma_alloc_coherent(&pci_dev->dev, @@ -942,6 +937,14 @@ static int netup_unidvb_initdev(struct pci_dev *pci_dev, dev_err(&pci_dev->dev, "netup_unidvb: DMA setup failed\n"); goto dma_setup_err; } + + if (request_irq(pci_dev->irq, netup_unidvb_isr, IRQF_SHARED, + "netup_unidvb", pci_dev) < 0) { + dev_err(&pci_dev->dev, + "%s(): can't get IRQ %d\n", __func__, pci_dev->irq); + goto dma_setup_err; + } + dev_info(&pci_dev->dev, "netup_unidvb: device has been initialized\n"); return 0; @@ -960,8 +963,6 @@ static int netup_unidvb_initdev(struct pci_dev *pci_dev, dma_free_coherent(&pci_dev->dev, ndev->dma_size, ndev->dma_virt, ndev->dma_phys); dma_alloc_err: - free_irq(pci_dev->irq, pci_dev); -irq_request_err: iounmap(ndev->lmmio1); pci_bar1_error: iounmap(ndev->lmmio0); diff --git a/drivers/media/pci/saa7134/saa7134-ts.c b/drivers/media/pci/saa7134/saa7134-ts.c index 2be703617e29434cc06d0210287ef503fd4903f8..e7adcd4f99623d79648340a29567263541f2a9db 100644 --- a/drivers/media/pci/saa7134/saa7134-ts.c +++ b/drivers/media/pci/saa7134/saa7134-ts.c @@ -309,6 +309,7 @@ int saa7134_ts_start(struct saa7134_dev *dev) int saa7134_ts_fini(struct saa7134_dev *dev) { + del_timer_sync(&dev->ts_q.timeout); saa7134_pgtable_free(dev->pci, &dev->ts_q.pt); return 0; } diff --git a/drivers/media/pci/saa7134/saa7134-vbi.c b/drivers/media/pci/saa7134/saa7134-vbi.c index 57bea543c39ba38ba1c722099e226e8366ce0d0b..559db500b19ce6581b8365e9e8819716715713cb 100644 --- a/drivers/media/pci/saa7134/saa7134-vbi.c +++ b/drivers/media/pci/saa7134/saa7134-vbi.c @@ -194,6 +194,7 @@ int saa7134_vbi_init1(struct saa7134_dev *dev) int saa7134_vbi_fini(struct saa7134_dev *dev) { /* nothing */ + del_timer_sync(&dev->vbi_q.timeout); return 0; } diff --git a/drivers/media/pci/saa7134/saa7134-video.c b/drivers/media/pci/saa7134/saa7134-video.c index 1a50ec9d084f3d6e78fb50ae818b9330071e4ba2..103cbc8c1345a0c503d0efea0686fafed5488e03 100644 --- a/drivers/media/pci/saa7134/saa7134-video.c +++ b/drivers/media/pci/saa7134/saa7134-video.c @@ -2213,6 +2213,7 @@ int saa7134_video_init1(struct saa7134_dev *dev) void saa7134_video_fini(struct saa7134_dev *dev) { + del_timer_sync(&dev->video_q.timeout); /* free stuff */ vb2_queue_release(&dev->video_vbq); saa7134_pgtable_free(dev->pci, &dev->video_q.pt); diff --git a/drivers/media/pci/ttpci/av7110_av.c b/drivers/media/pci/ttpci/av7110_av.c index ef1bc17cdc4d37a8549b86d7085a8fdfd76abca3..03d1d1fba8bc8779c76cfba0a495584b42b58422 100644 --- a/drivers/media/pci/ttpci/av7110_av.c +++ b/drivers/media/pci/ttpci/av7110_av.c @@ -836,10 +836,10 @@ static int write_ts_to_decoder(struct av7110 *av7110, int type, const u8 *buf, s av7110_ipack_flush(ipack); if (buf[3] & ADAPT_FIELD) { + if (buf[4] > len - 1 - 4) + return 0; len -= buf[4] + 1; buf += buf[4] + 1; - if (!len) - return 0; } av7110_ipack_instant_repack(buf + 4, len - 4, ipack); diff --git a/drivers/media/platform/exynos4-is/media-dev.c b/drivers/media/platform/exynos4-is/media-dev.c index 03171f2cf2968c081a2ce54cdfe1742dad175c95..5f50ea283a04f41ee5e8b781adee0b0b0dc8168a 100644 --- a/drivers/media/platform/exynos4-is/media-dev.c +++ b/drivers/media/platform/exynos4-is/media-dev.c @@ -445,7 +445,7 @@ static int fimc_md_parse_port_node(struct fimc_md *fmd, */ np = of_get_parent(rem); - if (np && !of_node_cmp(np->name, "i2c-isp")) + if (of_node_name_eq(np, "i2c-isp")) pd->fimc_bus_type = FIMC_BUS_TYPE_ISP_WRITEBACK; else pd->fimc_bus_type = pd->sensor_bus_type; @@ -492,7 +492,7 @@ static int fimc_md_register_sensor_entities(struct fimc_md *fmd) for_each_available_child_of_node(parent, node) { struct device_node *port; - if (of_node_cmp(node->name, "csis")) + if (!of_node_name_eq(node, "csis")) continue; /* The csis node can have only port subnode. */ port = of_get_next_child(node, NULL); @@ -713,13 +713,13 @@ static int fimc_md_register_platform_entities(struct fimc_md *fmd, continue; /* If driver of any entity isn't ready try all again later. */ - if (!strcmp(node->name, CSIS_OF_NODE_NAME)) + if (of_node_name_eq(node, CSIS_OF_NODE_NAME)) plat_entity = IDX_CSIS; - else if (!strcmp(node->name, FIMC_IS_OF_NODE_NAME)) + else if (of_node_name_eq(node, FIMC_IS_OF_NODE_NAME)) plat_entity = IDX_IS_ISP; - else if (!strcmp(node->name, FIMC_LITE_OF_NODE_NAME)) + else if (of_node_name_eq(node, FIMC_LITE_OF_NODE_NAME)) plat_entity = IDX_FLITE; - else if (!strcmp(node->name, FIMC_OF_NODE_NAME) && + else if (of_node_name_eq(node, FIMC_OF_NODE_NAME) && !of_property_read_bool(node, "samsung,lcd-wb")) plat_entity = IDX_FIMC; diff --git a/drivers/media/platform/msm/npu/npu_mgr.c b/drivers/media/platform/msm/npu/npu_mgr.c index af31981d8431aa01c42d4806ad1949bfa9d0df8a..768a431e4a0ba5e7c13386f51772556309a3f868 100644 --- a/drivers/media/platform/msm/npu/npu_mgr.c +++ b/drivers/media/platform/msm/npu/npu_mgr.c @@ -2574,6 +2574,13 @@ int32_t npu_host_unload_network(struct npu_client *client, return -EINVAL; } + if (network->is_unloading) { + NPU_ERR("network is unloading\n"); + network_put(network); + mutex_unlock(&host_ctx->lock); + return -EINVAL; + } + if (!network->is_active) { NPU_ERR("network is not active\n"); network_put(network); @@ -2591,6 +2598,8 @@ int32_t npu_host_unload_network(struct npu_client *client, goto free_network; } + network->is_unloading = true; + NPU_DBG("Unload network %lld\n", network->id); /* prepare IPC packet for UNLOAD */ unload_packet.header.cmd_type = NPU_IPC_CMD_UNLOAD; @@ -2724,6 +2733,12 @@ int32_t npu_host_exec_network_v2(struct npu_client *client, if (atomic_inc_return(&host_ctx->network_execute_cnt) == 1) npu_notify_cdsprm_cxlimit_activity(npu_dev, true); + if (network->is_unloading) { + NPU_ERR("network is unloading\n"); + ret = -EINVAL; + goto exec_v2_done; + } + if (!network->is_active) { NPU_ERR("network is not active\n"); ret = -EINVAL; diff --git a/drivers/media/platform/msm/npu/npu_mgr.h b/drivers/media/platform/msm/npu/npu_mgr.h index 414901e71a6ba13720618c8f746b44c8a5cd9693..69e9bbcad251d4e36b2105d236e611cbac773f67 100644 --- a/drivers/media/platform/msm/npu/npu_mgr.h +++ b/drivers/media/platform/msm/npu/npu_mgr.h @@ -84,6 +84,7 @@ struct npu_network { atomic_t ref_cnt; bool is_valid; bool is_active; + bool is_unloading; bool fw_error; struct npu_client *client; struct list_head cmd_list; diff --git a/drivers/media/platform/msm/vidc_3x/msm_vidc_common.c b/drivers/media/platform/msm/vidc_3x/msm_vidc_common.c index bae2b39a088f8cf990d0258723a3884bfe4037c4..4ccdca2ac80ba9c1935c0d9374af844a6c03dcf7 100644 --- a/drivers/media/platform/msm/vidc_3x/msm_vidc_common.c +++ b/drivers/media/platform/msm/vidc_3x/msm_vidc_common.c @@ -5030,7 +5030,37 @@ static int msm_vidc_load_supported(struct msm_vidc_inst *inst) } return 0; } +static int msm_vidc_check_mbpf_supported(struct msm_vidc_inst *inst) +{ + u32 mbpf = 0; + struct msm_vidc_core *core; + struct msm_vidc_inst *temp; + struct msm_vidc_capability *capability; + + if (!inst || !inst->core) + return -EINVAL; + core = inst->core; + capability = &inst->capability; + mutex_lock(&core->lock); + list_for_each_entry(temp, &core->instances, list) { + /* ignore invalid and completed session */ + if (temp->state == MSM_VIDC_CORE_INVALID || + temp->state >= MSM_VIDC_STOP_DONE) + continue; + /* ignore thumbnail session */ + if (is_thumbnail_session(temp)) + continue; + mbpf += msm_comm_get_mbs_per_frame(inst); + } + mutex_unlock(&core->lock); + if (mbpf > 2*capability->mbs_per_frame.max) { + msm_vidc_print_running_insts(inst->core); + return -ENOMEM; + } + + return 0; +} int msm_vidc_check_scaling_supported(struct msm_vidc_inst *inst) { u32 x_min, x_max, y_min, y_max; @@ -5128,6 +5158,9 @@ int msm_vidc_check_session_supported(struct msm_vidc_inst *inst) "%s: Hardware is overloaded\n", __func__); return rc; } + rc = msm_vidc_check_mbpf_supported(inst); + if (rc) + return rc; if (!is_thermal_permissible(core)) { dprintk(VIDC_WARN, diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c index 6ad408514a9984b999e0e0f99d9d439311716157..193a1f800a223253957ba66ee09abf566b905a67 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c @@ -766,6 +766,8 @@ static int vb2ops_venc_queue_setup(struct vb2_queue *vq, return -EINVAL; if (*nplanes) { + if (*nplanes != q_data->fmt->num_planes) + return -EINVAL; for (i = 0; i < *nplanes; i++) if (sizes[i] < q_data->sizeimage[i]) return -EINVAL; diff --git a/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c b/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c index bc8349bc2e80c5c4fc72a6253246fa0e1c4b9b10..2c0d89a46410ad62edcbb97cf3d8fe66273b2c8e 100644 --- a/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c @@ -230,10 +230,11 @@ static struct vdec_fb *vp9_rm_from_fb_use_list(struct vdec_vp9_inst if (fb->base_y.va == addr) { list_move_tail(&node->list, &inst->available_fb_node_list); - break; + return fb; } } - return fb; + + return NULL; } static void vp9_add_to_fb_free_list(struct vdec_vp9_inst *inst, diff --git a/drivers/media/platform/mtk-vpu/mtk_vpu.c b/drivers/media/platform/mtk-vpu/mtk_vpu.c index 9b57fb2857285ff77def21f1d064786f4bdd1deb..46ec1f2699aa77fa6dc9cec7038696d320ea212c 100644 --- a/drivers/media/platform/mtk-vpu/mtk_vpu.c +++ b/drivers/media/platform/mtk-vpu/mtk_vpu.c @@ -537,16 +537,18 @@ static int load_requested_vpu(struct mtk_vpu *vpu, int vpu_load_firmware(struct platform_device *pdev) { struct mtk_vpu *vpu; - struct device *dev = &pdev->dev; + struct device *dev; struct vpu_run *run; const struct firmware *vpu_fw = NULL; int ret; if (!pdev) { - dev_err(dev, "VPU platform device is invalid\n"); + pr_err("VPU platform device is invalid\n"); return -EINVAL; } + dev = &pdev->dev; + vpu = platform_get_drvdata(pdev); run = &vpu->run; diff --git a/drivers/media/platform/omap3isp/isp.c b/drivers/media/platform/omap3isp/isp.c index 00e52f0b8251bea790d9e658b7296b4c0b285b6b..b559cc179d708d03016fad1e3822aab814f6634c 100644 --- a/drivers/media/platform/omap3isp/isp.c +++ b/drivers/media/platform/omap3isp/isp.c @@ -2247,7 +2247,16 @@ static int isp_probe(struct platform_device *pdev) /* Regulators */ isp->isp_csiphy1.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy1"); + if (IS_ERR(isp->isp_csiphy1.vdd)) { + ret = PTR_ERR(isp->isp_csiphy1.vdd); + goto error; + } + isp->isp_csiphy2.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy2"); + if (IS_ERR(isp->isp_csiphy2.vdd)) { + ret = PTR_ERR(isp->isp_csiphy2.vdd); + goto error; + } /* Clocks * diff --git a/drivers/media/platform/qcom/venus/hfi_msgs.c b/drivers/media/platform/qcom/venus/hfi_msgs.c index 0ecdaa15c296971f0a2968f81af97ec1c1101d25..24a6e4ecf77d2950bd17e40ba99ddbd09227d4f9 100644 --- a/drivers/media/platform/qcom/venus/hfi_msgs.c +++ b/drivers/media/platform/qcom/venus/hfi_msgs.c @@ -359,7 +359,7 @@ session_get_prop_buf_req(struct hfi_msg_session_property_info_pkt *pkt, memcpy(&bufreq[idx], buf_req, sizeof(*bufreq)); idx++; - if (idx > HFI_BUFFER_TYPE_MAX) + if (idx >= HFI_BUFFER_TYPE_MAX) return HFI_ERR_SESSION_INVALID_PARAMETER; req_bytes -= sizeof(struct hfi_buffer_requirements); diff --git a/drivers/media/platform/qcom/venus/hfi_parser.c b/drivers/media/platform/qcom/venus/hfi_parser.c index 7f515a4b9bd1257152f87c3b17ec1cb046540aed..ad22b51765d46a01ffd5ec69c98de15ca44beace 100644 --- a/drivers/media/platform/qcom/venus/hfi_parser.c +++ b/drivers/media/platform/qcom/venus/hfi_parser.c @@ -19,6 +19,9 @@ static void init_codecs(struct venus_core *core) struct venus_caps *caps = core->caps, *cap; unsigned long bit; + if (hweight_long(core->dec_codecs) + hweight_long(core->enc_codecs) > MAX_CODEC_NUM) + return; + for_each_set_bit(bit, &core->dec_codecs, MAX_CODEC_NUM) { cap = &caps[core->codecs_count++]; cap->codec = BIT(bit); @@ -86,6 +89,9 @@ static void fill_profile_level(struct venus_caps *cap, const void *data, { const struct hfi_profile_level *pl = data; + if (cap->num_pl + num >= HFI_MAX_PROFILE_COUNT) + return; + memcpy(&cap->pl[cap->num_pl], pl, num * sizeof(*pl)); cap->num_pl += num; } @@ -111,6 +117,9 @@ fill_caps(struct venus_caps *cap, const void *data, unsigned int num) { const struct hfi_capability *caps = data; + if (cap->num_caps + num >= MAX_CAP_ENTRIES) + return; + memcpy(&cap->caps[cap->num_caps], caps, num * sizeof(*caps)); cap->num_caps += num; } @@ -137,6 +146,9 @@ static void fill_raw_fmts(struct venus_caps *cap, const void *fmts, { const struct raw_formats *formats = fmts; + if (cap->num_fmts + num_fmts >= MAX_FMT_ENTRIES) + return; + memcpy(&cap->fmts[cap->num_fmts], formats, num_fmts * sizeof(*formats)); cap->num_fmts += num_fmts; } @@ -159,6 +171,9 @@ parse_raw_formats(struct venus_core *core, u32 codecs, u32 domain, void *data) rawfmts[i].buftype = fmt->buffer_type; i++; + if (i >= MAX_FMT_ENTRIES) + return; + if (pinfo->num_planes > MAX_PLANES) break; diff --git a/drivers/media/platform/qcom/venus/hfi_venus.c b/drivers/media/platform/qcom/venus/hfi_venus.c index fbcc67c10993fc25b69847437e6b37684cf6e94f..b1bca3bf9dc917aacb58d4c75eedaccf47f2a1e5 100644 --- a/drivers/media/platform/qcom/venus/hfi_venus.c +++ b/drivers/media/platform/qcom/venus/hfi_venus.c @@ -220,6 +220,11 @@ static int venus_write_queue(struct venus_hfi_device *hdev, new_wr_idx = wr_idx + dwords; wr_ptr = (u32 *)(queue->qmem.kva + (wr_idx << 2)); + + if (wr_ptr < (u32 *)queue->qmem.kva || + wr_ptr > (u32 *)(queue->qmem.kva + queue->qmem.size - sizeof(*wr_ptr))) + return -EINVAL; + if (new_wr_idx < qsize) { memcpy(wr_ptr, packet, dwords << 2); } else { @@ -287,6 +292,11 @@ static int venus_read_queue(struct venus_hfi_device *hdev, } rd_ptr = (u32 *)(queue->qmem.kva + (rd_idx << 2)); + + if (rd_ptr < (u32 *)queue->qmem.kva || + rd_ptr > (u32 *)(queue->qmem.kva + queue->qmem.size - sizeof(*rd_ptr))) + return -EINVAL; + dwords = *rd_ptr >> 2; if (!dwords) return -EINVAL; diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c index 70a8cc433a03f246c012e191bec78dc52a4ef48b..cc28e2cb23f11a77b6168da363e3f6438ff22e2c 100644 --- a/drivers/media/platform/rcar-vin/rcar-dma.c +++ b/drivers/media/platform/rcar-vin/rcar-dma.c @@ -633,6 +633,7 @@ static int rvin_setup(struct rvin_dev *vin) vnmc = VNMC_IM_FULL | VNMC_FOC; break; case V4L2_FIELD_NONE: + case V4L2_FIELD_ALTERNATE: vnmc = VNMC_IM_ODD_EVEN; progressive = true; break; diff --git a/drivers/media/platform/rcar_fdp1.c b/drivers/media/platform/rcar_fdp1.c index 2bd5898a62044e1ff250285557a84592572e4235..605d8188ac8c1cbeb312176b26f41c34ad72972c 100644 --- a/drivers/media/platform/rcar_fdp1.c +++ b/drivers/media/platform/rcar_fdp1.c @@ -2287,11 +2287,10 @@ static int fdp1_probe(struct platform_device *pdev) return PTR_ERR(fdp1->regs); /* Interrupt service routine registration */ - fdp1->irq = ret = platform_get_irq(pdev, 0); - if (ret < 0) { - dev_err(&pdev->dev, "cannot find IRQ\n"); + ret = platform_get_irq(pdev, 0); + if (ret < 0) return ret; - } + fdp1->irq = ret; ret = devm_request_irq(&pdev->dev, fdp1->irq, fdp1_irq_handler, 0, dev_name(&pdev->dev), fdp1); @@ -2314,8 +2313,10 @@ static int fdp1_probe(struct platform_device *pdev) /* Determine our clock rate */ clk = clk_get(&pdev->dev, NULL); - if (IS_ERR(clk)) - return PTR_ERR(clk); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto put_dev; + } fdp1->clk_rate = clk_get_rate(clk); clk_put(clk); @@ -2324,7 +2325,7 @@ static int fdp1_probe(struct platform_device *pdev) ret = v4l2_device_register(&pdev->dev, &fdp1->v4l2_dev); if (ret) { v4l2_err(&fdp1->v4l2_dev, "Failed to register video device\n"); - return ret; + goto put_dev; } /* M2M registration */ @@ -2389,6 +2390,8 @@ static int fdp1_probe(struct platform_device *pdev) unreg_dev: v4l2_device_unregister(&fdp1->v4l2_dev); +put_dev: + rcar_fcp_put(fdp1->fcp); return ret; } @@ -2400,6 +2403,7 @@ static int fdp1_remove(struct platform_device *pdev) video_unregister_device(&fdp1->vfd); v4l2_device_unregister(&fdp1->v4l2_dev); pm_runtime_disable(&pdev->dev); + rcar_fcp_put(fdp1->fcp); return 0; } diff --git a/drivers/media/platform/s3c-camif/camif-capture.c b/drivers/media/platform/s3c-camif/camif-capture.c index c02dce8b4c6c788ba5dd025fc35b1378a9c466e9..6e150fc64e0a017b8cbb95d44052060a60fe18b2 100644 --- a/drivers/media/platform/s3c-camif/camif-capture.c +++ b/drivers/media/platform/s3c-camif/camif-capture.c @@ -1142,12 +1142,12 @@ int s3c_camif_register_video_node(struct camif_dev *camif, int idx) ret = vb2_queue_init(q); if (ret) - goto err_vd_rel; + return ret; vp->pad.flags = MEDIA_PAD_FL_SINK; ret = media_entity_pads_init(&vfd->entity, 1, &vp->pad); if (ret) - goto err_vd_rel; + return ret; video_set_drvdata(vfd, vp); @@ -1179,8 +1179,6 @@ int s3c_camif_register_video_node(struct camif_dev *camif, int idx) v4l2_ctrl_handler_free(&vp->ctrl_handler); err_me_cleanup: media_entity_cleanup(&vfd->entity); -err_vd_rel: - video_device_release(vfd); return ret; } diff --git a/drivers/media/platform/sti/bdisp/bdisp-v4l2.c b/drivers/media/platform/sti/bdisp/bdisp-v4l2.c index 00f6e3f06dac58661982978eb85323af2c09f73c..7a7271f9d875a7d0c8c820e1eed881236d455ec3 100644 --- a/drivers/media/platform/sti/bdisp/bdisp-v4l2.c +++ b/drivers/media/platform/sti/bdisp/bdisp-v4l2.c @@ -1312,6 +1312,8 @@ static int bdisp_probe(struct platform_device *pdev) init_waitqueue_head(&bdisp->irq_queue); INIT_DELAYED_WORK(&bdisp->timeout_work, bdisp_irq_timeout); bdisp->work_queue = create_workqueue(BDISP_NAME); + if (!bdisp->work_queue) + return -ENOMEM; spin_lock_init(&bdisp->slock); mutex_init(&bdisp->lock); diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index d945323fc437d3b7d73f42639bc960e1b4805994..f9488e01a36f01276fe89645ce0a47262d508c1b 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -1618,7 +1618,7 @@ of_get_next_port(const struct device_node *parent, return NULL; } prev = port; - } while (of_node_cmp(port->name, "port") != 0); + } while (!of_node_name_eq(port, "port")); } return port; @@ -1638,7 +1638,7 @@ of_get_next_endpoint(const struct device_node *parent, if (!ep) return NULL; prev = ep; - } while (of_node_cmp(ep->name, "endpoint") != 0); + } while (!of_node_name_eq(ep, "endpoint")); return ep; } diff --git a/drivers/media/platform/vivid/vivid-rds-gen.c b/drivers/media/platform/vivid/vivid-rds-gen.c index 39ca9a56448c0e79bdaa54e0e5cf862687b7f62c..9f6009ac5e2554241f6e566c9ac5889c195ce530 100644 --- a/drivers/media/platform/vivid/vivid-rds-gen.c +++ b/drivers/media/platform/vivid/vivid-rds-gen.c @@ -145,7 +145,7 @@ void vivid_rds_gen_fill(struct vivid_rds_gen *rds, unsigned freq, rds->ta = alt; rds->ms = true; snprintf(rds->psname, sizeof(rds->psname), "%6d.%1d", - freq / 16, ((freq & 0xf) * 10) / 16); + (freq / 16) % 1000000, (((freq & 0xf) * 10) / 16) % 10); if (alt) strlcpy(rds->radiotext, " The Radio Data System can switch between different Radio Texts ", diff --git a/drivers/media/platform/xilinx/xilinx-tpg.c b/drivers/media/platform/xilinx/xilinx-tpg.c index 9c49d1d10bee572066e14d35151595a878f124d9..06d25e5fafbf2551ed2f659c7f139917672a8035 100644 --- a/drivers/media/platform/xilinx/xilinx-tpg.c +++ b/drivers/media/platform/xilinx/xilinx-tpg.c @@ -725,7 +725,7 @@ static int xtpg_parse_of(struct xtpg_device *xtpg) const struct xvip_video_format *format; struct device_node *endpoint; - if (!port->name || of_node_cmp(port->name, "port")) + if (!of_node_name_eq(port, "port")) continue; format = xvip_of_get_format(port); diff --git a/drivers/media/radio/radio-shark.c b/drivers/media/radio/radio-shark.c index 22f3466af2b187d1779c1bd81515ae5e85d3f9ad..5275180aed0b782680ec49d5686f1a2bb7cea720 100644 --- a/drivers/media/radio/radio-shark.c +++ b/drivers/media/radio/radio-shark.c @@ -316,6 +316,16 @@ static int usb_shark_probe(struct usb_interface *intf, { struct shark_device *shark; int retval = -ENOMEM; + static const u8 ep_addresses[] = { + SHARK_IN_EP | USB_DIR_IN, + SHARK_OUT_EP | USB_DIR_OUT, + 0}; + + /* Are the expected endpoints present? */ + if (!usb_check_int_endpoints(intf, ep_addresses)) { + dev_err(&intf->dev, "Invalid radioSHARK device\n"); + return -EINVAL; + } shark = kzalloc(sizeof(struct shark_device), GFP_KERNEL); if (!shark) diff --git a/drivers/media/radio/radio-shark2.c b/drivers/media/radio/radio-shark2.c index 4d1a4b3d669cf5fcdcde0d2b3a882d059baa0acd..5356941f54aefad8709cd21fd2e7deead8e544a2 100644 --- a/drivers/media/radio/radio-shark2.c +++ b/drivers/media/radio/radio-shark2.c @@ -282,6 +282,16 @@ static int usb_shark_probe(struct usb_interface *intf, { struct shark_device *shark; int retval = -ENOMEM; + static const u8 ep_addresses[] = { + SHARK_IN_EP | USB_DIR_IN, + SHARK_OUT_EP | USB_DIR_OUT, + 0}; + + /* Are the expected endpoints present? */ + if (!usb_check_int_endpoints(intf, ep_addresses)) { + dev_err(&intf->dev, "Invalid radioSHARK2 device\n"); + return -EINVAL; + } shark = kzalloc(sizeof(struct shark_device), GFP_KERNEL); if (!shark) diff --git a/drivers/media/rc/ene_ir.c b/drivers/media/rc/ene_ir.c index 71b8c9bbf6c409b954471d6e4cf20884fdea35ee..8cf2a5c0575ab09f33f4601f4ba53af3a0cfaea2 100644 --- a/drivers/media/rc/ene_ir.c +++ b/drivers/media/rc/ene_ir.c @@ -1116,6 +1116,8 @@ static void ene_remove(struct pnp_dev *pnp_dev) struct ene_device *dev = pnp_get_drvdata(pnp_dev); unsigned long flags; + rc_unregister_device(dev->rdev); + del_timer_sync(&dev->tx_sim_timer); spin_lock_irqsave(&dev->hw_lock, flags); ene_rx_disable(dev); ene_rx_restore_hw_buffer(dev); @@ -1123,7 +1125,6 @@ static void ene_remove(struct pnp_dev *pnp_dev) free_irq(dev->irq, dev); release_region(dev->hw_io, ENE_IO_SIZE); - rc_unregister_device(dev->rdev); kfree(dev); } diff --git a/drivers/media/rc/gpio-ir-recv.c b/drivers/media/rc/gpio-ir-recv.c index 3d99b51384ac9f3329eccd50efe67049e7237e0c..ed5cfde4d9e79b5eb121499315cdf298d6e7310d 100644 --- a/drivers/media/rc/gpio-ir-recv.c +++ b/drivers/media/rc/gpio-ir-recv.c @@ -91,6 +91,8 @@ static int gpio_ir_recv_probe(struct platform_device *pdev) rcdev->map_name = RC_MAP_EMPTY; gpio_dev->rcdev = rcdev; + if (of_property_read_bool(np, "wakeup-source")) + device_init_wakeup(dev, true); rc = devm_rc_register_device(dev, rcdev); if (rc < 0) { diff --git a/drivers/media/rc/ir-sharp-decoder.c b/drivers/media/rc/ir-sharp-decoder.c index f96e0c992eed3ee287af6d800a6ebb131de9bdfd..dbddf987df973210f0f86ea7856a9706b1ff83f1 100644 --- a/drivers/media/rc/ir-sharp-decoder.c +++ b/drivers/media/rc/ir-sharp-decoder.c @@ -23,7 +23,9 @@ #define SHARP_UNIT 40000 /* ns */ #define SHARP_BIT_PULSE (8 * SHARP_UNIT) /* 320us */ #define SHARP_BIT_0_PERIOD (25 * SHARP_UNIT) /* 1ms (680us space) */ -#define SHARP_BIT_1_PERIOD (50 * SHARP_UNIT) /* 2ms (1680ms space) */ +#define SHARP_BIT_1_PERIOD (50 * SHARP_UNIT) /* 2ms (1680us space) */ +#define SHARP_BIT_0_SPACE (17 * SHARP_UNIT) /* 680us space */ +#define SHARP_BIT_1_SPACE (42 * SHARP_UNIT) /* 1680us space */ #define SHARP_ECHO_SPACE (1000 * SHARP_UNIT) /* 40 ms */ #define SHARP_TRAILER_SPACE (125 * SHARP_UNIT) /* 5 ms (even longer) */ @@ -176,8 +178,8 @@ static const struct ir_raw_timings_pd ir_sharp_timings = { .header_pulse = 0, .header_space = 0, .bit_pulse = SHARP_BIT_PULSE, - .bit_space[0] = SHARP_BIT_0_PERIOD, - .bit_space[1] = SHARP_BIT_1_PERIOD, + .bit_space[0] = SHARP_BIT_0_SPACE, + .bit_space[1] = SHARP_BIT_1_SPACE, .trailer_pulse = SHARP_BIT_PULSE, .trailer_space = SHARP_ECHO_SPACE, .msb_first = 1, diff --git a/drivers/media/rc/lirc_dev.c b/drivers/media/rc/lirc_dev.c index d6f5f5b3f75f247897acee52446003713854f3da..b71792f491171ab07dbc3a46a34a19e37f534a4b 100644 --- a/drivers/media/rc/lirc_dev.c +++ b/drivers/media/rc/lirc_dev.c @@ -302,7 +302,11 @@ static ssize_t ir_lirc_transmit_ir(struct file *file, const char __user *buf, if (ret < 0) goto out_kfree_raw; - count = ret; + /* drop trailing space */ + if (!(ret % 2)) + count = ret - 1; + else + count = ret; txbuf = kmalloc_array(count, sizeof(unsigned int), GFP_KERNEL); if (!txbuf) { diff --git a/drivers/media/tuners/fc0011.c b/drivers/media/tuners/fc0011.c index a983899c6b0bee325164a5fbbec6cc259d06f1ea..b407e1965f8ade1dd2b7996735061e00d1486428 100644 --- a/drivers/media/tuners/fc0011.c +++ b/drivers/media/tuners/fc0011.c @@ -508,7 +508,7 @@ struct dvb_frontend *fc0011_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(fc0011_attach); +EXPORT_SYMBOL_GPL(fc0011_attach); MODULE_DESCRIPTION("Fitipower FC0011 silicon tuner driver"); MODULE_AUTHOR("Michael Buesch "); diff --git a/drivers/media/tuners/fc0012.c b/drivers/media/tuners/fc0012.c index e992b98ae5bcc010ccc560ebc64fd18dbbd2ad0c..6789a85b618b5340dff47f835cc81b1f869bbe4b 100644 --- a/drivers/media/tuners/fc0012.c +++ b/drivers/media/tuners/fc0012.c @@ -504,7 +504,7 @@ struct dvb_frontend *fc0012_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(fc0012_attach); +EXPORT_SYMBOL_GPL(fc0012_attach); MODULE_DESCRIPTION("Fitipower FC0012 silicon tuner driver"); MODULE_AUTHOR("Hans-Frieder Vogt "); diff --git a/drivers/media/tuners/fc0013.c b/drivers/media/tuners/fc0013.c index fc62afb1450d0c8556b41b49d282cbd35c0f4c1e..0b7ff74a7936abe5cc4fe187356d78ee2c093e23 100644 --- a/drivers/media/tuners/fc0013.c +++ b/drivers/media/tuners/fc0013.c @@ -618,7 +618,7 @@ struct dvb_frontend *fc0013_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(fc0013_attach); +EXPORT_SYMBOL_GPL(fc0013_attach); MODULE_DESCRIPTION("Fitipower FC0013 silicon tuner driver"); MODULE_AUTHOR("Hans-Frieder Vogt "); diff --git a/drivers/media/tuners/max2165.c b/drivers/media/tuners/max2165.c index 721d8f722efb44b9b0813f4d91c48f57ebe8f911..9600989eea5f7f5a38fbb4af9d770c623af34a60 100644 --- a/drivers/media/tuners/max2165.c +++ b/drivers/media/tuners/max2165.c @@ -420,7 +420,7 @@ struct dvb_frontend *max2165_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(max2165_attach); +EXPORT_SYMBOL_GPL(max2165_attach); MODULE_AUTHOR("David T. L. Wong "); MODULE_DESCRIPTION("Maxim MAX2165 silicon tuner driver"); diff --git a/drivers/media/tuners/mc44s803.c b/drivers/media/tuners/mc44s803.c index 2023e081d9adc78d7c7dabe7ee4845fd9f9b80de..7f6d54910f2269a8c0ee7b355eae461f89e3bfe3 100644 --- a/drivers/media/tuners/mc44s803.c +++ b/drivers/media/tuners/mc44s803.c @@ -366,7 +366,7 @@ struct dvb_frontend *mc44s803_attach(struct dvb_frontend *fe, kfree(priv); return NULL; } -EXPORT_SYMBOL(mc44s803_attach); +EXPORT_SYMBOL_GPL(mc44s803_attach); MODULE_AUTHOR("Jochen Friedrich"); MODULE_DESCRIPTION("Freescale MC44S803 silicon tuner driver"); diff --git a/drivers/media/tuners/mt2060.c b/drivers/media/tuners/mt2060.c index 4ace77cfe2857bfce97dc6054155a63b0d4f1f6e..a7fbd4ab2298d83ceedb42b5dd15a716e19ba92a 100644 --- a/drivers/media/tuners/mt2060.c +++ b/drivers/media/tuners/mt2060.c @@ -450,7 +450,7 @@ struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter return fe; } -EXPORT_SYMBOL(mt2060_attach); +EXPORT_SYMBOL_GPL(mt2060_attach); static int mt2060_probe(struct i2c_client *client, const struct i2c_device_id *id) diff --git a/drivers/media/tuners/mt2131.c b/drivers/media/tuners/mt2131.c index 086a7b7cf6348fe45a44a18b41a0894df62f045d..8db33cf31c405b6a6a024d4c841e9cc512e2f8b7 100644 --- a/drivers/media/tuners/mt2131.c +++ b/drivers/media/tuners/mt2131.c @@ -284,7 +284,7 @@ struct dvb_frontend * mt2131_attach(struct dvb_frontend *fe, fe->tuner_priv = priv; return fe; } -EXPORT_SYMBOL(mt2131_attach); +EXPORT_SYMBOL_GPL(mt2131_attach); MODULE_AUTHOR("Steven Toth"); MODULE_DESCRIPTION("Microtune MT2131 silicon tuner driver"); diff --git a/drivers/media/tuners/mt2266.c b/drivers/media/tuners/mt2266.c index e6cc78720de4d7d7f849588d51a9d0f898fc7a91..5300f71b8fe5e2dfa4b6995b4fe805126fa24f36 100644 --- a/drivers/media/tuners/mt2266.c +++ b/drivers/media/tuners/mt2266.c @@ -345,7 +345,7 @@ struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter mt2266_calibrate(priv); return fe; } -EXPORT_SYMBOL(mt2266_attach); +EXPORT_SYMBOL_GPL(mt2266_attach); MODULE_AUTHOR("Olivier DANET"); MODULE_DESCRIPTION("Microtune MT2266 silicon tuner driver"); diff --git a/drivers/media/tuners/mxl5005s.c b/drivers/media/tuners/mxl5005s.c index ec584316c812d30a982c8aef5da0081a6e6a14f0..2c540653e12e1fea77aec4b68b038ac8a35d899e 100644 --- a/drivers/media/tuners/mxl5005s.c +++ b/drivers/media/tuners/mxl5005s.c @@ -4114,7 +4114,7 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, fe->tuner_priv = state; return fe; } -EXPORT_SYMBOL(mxl5005s_attach); +EXPORT_SYMBOL_GPL(mxl5005s_attach); MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); MODULE_AUTHOR("Steven Toth"); diff --git a/drivers/media/tuners/qt1010.c b/drivers/media/tuners/qt1010.c index 4565c06b161763711c12dffa5492224d7f7da58b..3236e2277ab33659615baa1753782a5f032d6082 100644 --- a/drivers/media/tuners/qt1010.c +++ b/drivers/media/tuners/qt1010.c @@ -224,7 +224,7 @@ static int qt1010_set_params(struct dvb_frontend *fe) static int qt1010_init_meas1(struct qt1010_priv *priv, u8 oper, u8 reg, u8 reg_init_val, u8 *retval) { - u8 i, val1, uninitialized_var(val2); + u8 i, val1, val2; int err; qt1010_i2c_oper_t i2c_data[] = { @@ -259,7 +259,7 @@ static int qt1010_init_meas1(struct qt1010_priv *priv, static int qt1010_init_meas2(struct qt1010_priv *priv, u8 reg_init_val, u8 *retval) { - u8 i, uninitialized_var(val); + u8 i, val; int err; qt1010_i2c_oper_t i2c_data[] = { { QT1010_WR, 0x07, reg_init_val }, @@ -351,11 +351,12 @@ static int qt1010_init(struct dvb_frontend *fe) else valptr = &tmpval; - BUG_ON(i >= ARRAY_SIZE(i2c_data) - 1); - - err = qt1010_init_meas1(priv, i2c_data[i+1].reg, - i2c_data[i].reg, - i2c_data[i].val, valptr); + if (i >= ARRAY_SIZE(i2c_data) - 1) + err = -EIO; + else + err = qt1010_init_meas1(priv, i2c_data[i + 1].reg, + i2c_data[i].reg, + i2c_data[i].val, valptr); i++; break; } @@ -446,7 +447,7 @@ struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe, fe->tuner_priv = priv; return fe; } -EXPORT_SYMBOL(qt1010_attach); +EXPORT_SYMBOL_GPL(qt1010_attach); MODULE_DESCRIPTION("Quantek QT1010 silicon tuner driver"); MODULE_AUTHOR("Antti Palosaari "); diff --git a/drivers/media/tuners/tda18218.c b/drivers/media/tuners/tda18218.c index cbbd4d5e15da7c060eb5084977c60913310b8100..16716b557ade2bf0142f14729de2f8f3bc169521 100644 --- a/drivers/media/tuners/tda18218.c +++ b/drivers/media/tuners/tda18218.c @@ -345,7 +345,7 @@ struct dvb_frontend *tda18218_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(tda18218_attach); +EXPORT_SYMBOL_GPL(tda18218_attach); MODULE_DESCRIPTION("NXP TDA18218HN silicon tuner driver"); MODULE_AUTHOR("Antti Palosaari "); diff --git a/drivers/media/tuners/tuner-xc2028.c b/drivers/media/tuners/tuner-xc2028.c index aa6861dcd3fd78fd0df75c358b1149564564371a..802a4d77f26bf8410832c5bf384597829e6b9ca4 100644 --- a/drivers/media/tuners/tuner-xc2028.c +++ b/drivers/media/tuners/tuner-xc2028.c @@ -1513,7 +1513,7 @@ struct dvb_frontend *xc2028_attach(struct dvb_frontend *fe, return NULL; } -EXPORT_SYMBOL(xc2028_attach); +EXPORT_SYMBOL_GPL(xc2028_attach); MODULE_DESCRIPTION("Xceive xc2028/xc3028 tuner driver"); MODULE_AUTHOR("Michel Ludwig "); diff --git a/drivers/media/tuners/xc4000.c b/drivers/media/tuners/xc4000.c index eb6d65dae74868cce98e12de25c8315f1dcdaf24..0ef8f054a7950c61b012a5b1ec7ca3d64864c9ab 100644 --- a/drivers/media/tuners/xc4000.c +++ b/drivers/media/tuners/xc4000.c @@ -1754,7 +1754,7 @@ struct dvb_frontend *xc4000_attach(struct dvb_frontend *fe, xc4000_release(fe); return NULL; } -EXPORT_SYMBOL(xc4000_attach); +EXPORT_SYMBOL_GPL(xc4000_attach); MODULE_AUTHOR("Steven Toth, Davide Ferri"); MODULE_DESCRIPTION("Xceive xc4000 silicon tuner driver"); diff --git a/drivers/media/tuners/xc5000.c b/drivers/media/tuners/xc5000.c index 9388435bc13d98fa77bc0b0d48e955881e425527..fcc18058b01a46e8203b8ab1bd471c0369181aee 100644 --- a/drivers/media/tuners/xc5000.c +++ b/drivers/media/tuners/xc5000.c @@ -1470,7 +1470,7 @@ struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe, xc5000_release(fe); return NULL; } -EXPORT_SYMBOL(xc5000_attach); +EXPORT_SYMBOL_GPL(xc5000_attach); MODULE_AUTHOR("Steven Toth"); MODULE_DESCRIPTION("Xceive xc5000 silicon tuner driver"); diff --git a/drivers/media/usb/dvb-usb-v2/af9035.c b/drivers/media/usb/dvb-usb-v2/af9035.c index 1f6c1eefe38920c9f1e08d1f99158db7e715c838..2ed29a99fee1e962b0f293e5b38a34066445d2ce 100644 --- a/drivers/media/usb/dvb-usb-v2/af9035.c +++ b/drivers/media/usb/dvb-usb-v2/af9035.c @@ -284,6 +284,7 @@ static int af9035_i2c_master_xfer(struct i2c_adapter *adap, struct dvb_usb_device *d = i2c_get_adapdata(adap); struct state *state = d_to_priv(d); int ret; + u32 reg; if (mutex_lock_interruptible(&d->i2c_mutex) < 0) return -EAGAIN; @@ -336,8 +337,12 @@ static int af9035_i2c_master_xfer(struct i2c_adapter *adap, ret = -EOPNOTSUPP; } else if ((msg[0].addr == state->af9033_i2c_addr[0]) || (msg[0].addr == state->af9033_i2c_addr[1])) { + if (msg[0].len < 3 || msg[1].len < 1) { + ret = -EOPNOTSUPP; + goto unlock; + } /* demod access via firmware interface */ - u32 reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | + reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | msg[0].buf[2]; if (msg[0].addr == state->af9033_i2c_addr[1]) @@ -395,17 +400,18 @@ static int af9035_i2c_master_xfer(struct i2c_adapter *adap, ret = -EOPNOTSUPP; } else if ((msg[0].addr == state->af9033_i2c_addr[0]) || (msg[0].addr == state->af9033_i2c_addr[1])) { + if (msg[0].len < 3) { + ret = -EOPNOTSUPP; + goto unlock; + } /* demod access via firmware interface */ - u32 reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | + reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | msg[0].buf[2]; if (msg[0].addr == state->af9033_i2c_addr[1]) reg |= 0x100000; - ret = (msg[0].len >= 3) ? af9035_wr_regs(d, reg, - &msg[0].buf[3], - msg[0].len - 3) - : -EOPNOTSUPP; + ret = af9035_wr_regs(d, reg, &msg[0].buf[3], msg[0].len - 3); } else { /* I2C write */ u8 buf[MAX_XFER_SIZE]; @@ -472,6 +478,7 @@ static int af9035_i2c_master_xfer(struct i2c_adapter *adap, ret = -EOPNOTSUPP; } +unlock: mutex_unlock(&d->i2c_mutex); if (ret < 0) diff --git a/drivers/media/usb/dvb-usb-v2/anysee.c b/drivers/media/usb/dvb-usb-v2/anysee.c index 20ee7eea2a91ef238d19d73fc622addf1529005b..83af86505363b18bd86967703c24c7c42f253e1a 100644 --- a/drivers/media/usb/dvb-usb-v2/anysee.c +++ b/drivers/media/usb/dvb-usb-v2/anysee.c @@ -211,7 +211,7 @@ static int anysee_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, while (i < num) { if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) { - if (msg[i].len > 2 || msg[i+1].len > 60) { + if (msg[i].len != 2 || msg[i + 1].len > 60) { ret = -EOPNOTSUPP; break; } diff --git a/drivers/media/usb/dvb-usb-v2/az6007.c b/drivers/media/usb/dvb-usb-v2/az6007.c index 746926364535d4b64b6446b756b92cd3e8ed5195..2f40eb6bdbb83e6aeefe063142a2f596703fbd0c 100644 --- a/drivers/media/usb/dvb-usb-v2/az6007.c +++ b/drivers/media/usb/dvb-usb-v2/az6007.c @@ -210,7 +210,8 @@ static int az6007_rc_query(struct dvb_usb_device *d) unsigned code; enum rc_proto proto; - az6007_read(d, AZ6007_READ_IR, 0, 0, st->data, 10); + if (az6007_read(d, AZ6007_READ_IR, 0, 0, st->data, 10) < 0) + return -EIO; if (st->data[1] == 0x44) return 0; @@ -795,6 +796,10 @@ static int az6007_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], if (az6007_xfer_debug) printk(KERN_DEBUG "az6007: I2C W addr=0x%x len=%d\n", addr, msgs[i].len); + if (msgs[i].len < 1) { + ret = -EIO; + goto err; + } req = AZ6007_I2C_WR; index = msgs[i].buf[0]; value = addr | (1 << 8); @@ -809,6 +814,10 @@ static int az6007_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], if (az6007_xfer_debug) printk(KERN_DEBUG "az6007: I2C R addr=0x%x len=%d\n", addr, msgs[i].len); + if (msgs[i].len < 1) { + ret = -EIO; + goto err; + } req = AZ6007_I2C_RD; index = msgs[i].buf[0]; value = addr; diff --git a/drivers/media/usb/dvb-usb-v2/ce6230.c b/drivers/media/usb/dvb-usb-v2/ce6230.c index e596031a708d06d69b20af0c2de0a60183b334c2..80a07aab3b4b0c8b62a211ac07d1c1041d4126c6 100644 --- a/drivers/media/usb/dvb-usb-v2/ce6230.c +++ b/drivers/media/usb/dvb-usb-v2/ce6230.c @@ -111,6 +111,10 @@ static int ce6230_i2c_master_xfer(struct i2c_adapter *adap, if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) { if (msg[i].addr == ce6230_zl10353_config.demod_address) { + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } req.cmd = DEMOD_READ; req.value = msg[i].addr >> 1; req.index = msg[i].buf[0]; @@ -127,6 +131,10 @@ static int ce6230_i2c_master_xfer(struct i2c_adapter *adap, } else { if (msg[i].addr == ce6230_zl10353_config.demod_address) { + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } req.cmd = DEMOD_WRITE; req.value = msg[i].addr >> 1; req.index = msg[i].buf[0]; diff --git a/drivers/media/usb/dvb-usb-v2/ec168.c b/drivers/media/usb/dvb-usb-v2/ec168.c index 1db8aeef36553d67d63ca04fd6013fce883e9471..19605958501e1f6129d79e01a82549c5e143a99b 100644 --- a/drivers/media/usb/dvb-usb-v2/ec168.c +++ b/drivers/media/usb/dvb-usb-v2/ec168.c @@ -125,6 +125,10 @@ static int ec168_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], while (i < num) { if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) { if (msg[i].addr == ec168_ec100_config.demod_address) { + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } req.cmd = READ_DEMOD; req.value = 0; req.index = 0xff00 + msg[i].buf[0]; /* reg */ @@ -141,6 +145,10 @@ static int ec168_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], } } else { if (msg[i].addr == ec168_ec100_config.demod_address) { + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } req.cmd = WRITE_DEMOD; req.value = msg[i].buf[1]; /* val */ req.index = 0xff00 + msg[i].buf[0]; /* reg */ @@ -149,6 +157,10 @@ static int ec168_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], ret = ec168_ctrl_msg(d, &req); i += 1; } else { + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } req.cmd = WRITE_I2C; req.value = msg[i].buf[0]; /* val */ req.index = 0x0100 + msg[i].addr; /* I2C addr */ diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index 857ef9edbc123f2e6f318203d710384fbf0aba22..195b1977b6a686053e34c7227e9c650d4d622487 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -189,6 +189,10 @@ static int rtl28xxu_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], ret = -EOPNOTSUPP; goto err_mutex_unlock; } else if (msg[0].addr == 0x10) { + if (msg[0].len < 1 || msg[1].len < 1) { + ret = -EOPNOTSUPP; + goto err_mutex_unlock; + } /* method 1 - integrated demod */ if (msg[0].buf[0] == 0x00) { /* return demod page from driver cache */ @@ -202,6 +206,10 @@ static int rtl28xxu_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], ret = rtl28xxu_ctrl_msg(d, &req); } } else if (msg[0].len < 2) { + if (msg[0].len < 1) { + ret = -EOPNOTSUPP; + goto err_mutex_unlock; + } /* method 2 - old I2C */ req.value = (msg[0].buf[0] << 8) | (msg[0].addr << 1); req.index = CMD_I2C_RD; @@ -230,8 +238,16 @@ static int rtl28xxu_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], ret = -EOPNOTSUPP; goto err_mutex_unlock; } else if (msg[0].addr == 0x10) { + if (msg[0].len < 1) { + ret = -EOPNOTSUPP; + goto err_mutex_unlock; + } /* method 1 - integrated demod */ if (msg[0].buf[0] == 0x00) { + if (msg[0].len < 2) { + ret = -EOPNOTSUPP; + goto err_mutex_unlock; + } /* save demod page for later demod access */ dev->page = msg[0].buf[1]; ret = 0; @@ -244,6 +260,10 @@ static int rtl28xxu_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], ret = rtl28xxu_ctrl_msg(d, &req); } } else if ((msg[0].len < 23) && (!dev->new_i2c_write)) { + if (msg[0].len < 1) { + ret = -EOPNOTSUPP; + goto err_mutex_unlock; + } /* method 2 - old I2C */ req.value = (msg[0].buf[0] << 8) | (msg[0].addr << 1); req.index = CMD_I2C_WR; diff --git a/drivers/media/usb/dvb-usb/af9005.c b/drivers/media/usb/dvb-usb/af9005.c index d2737460c9d3b5ad72328909d8d4790c37b5e44d..60acaaf8b892f450de1f783e961eb94ca4405cb5 100644 --- a/drivers/media/usb/dvb-usb/af9005.c +++ b/drivers/media/usb/dvb-usb/af9005.c @@ -431,6 +431,10 @@ static int af9005_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], if (ret == 0) ret = 2; } else { + if (msg[0].len < 2) { + ret = -EOPNOTSUPP; + goto unlock; + } /* write one or more registers */ reg = msg[0].buf[0]; addr = msg[0].addr; @@ -440,6 +444,7 @@ static int af9005_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], ret = 1; } +unlock: mutex_unlock(&d->i2c_mutex); return ret; } diff --git a/drivers/media/usb/dvb-usb/az6027.c b/drivers/media/usb/dvb-usb/az6027.c index 7d71ac7811ebdc0b4e3bac9961b4dd1323ff6771..fdd57d84cfa42ec4fa037dc465655279443e7bf7 100644 --- a/drivers/media/usb/dvb-usb/az6027.c +++ b/drivers/media/usb/dvb-usb/az6027.c @@ -991,6 +991,10 @@ static int az6027_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], int n /* write/read request */ if (i + 1 < num && (msg[i + 1].flags & I2C_M_RD)) { req = 0xB9; + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } index = (((msg[i].buf[0] << 8) & 0xff00) | (msg[i].buf[1] & 0x00ff)); value = msg[i].addr + (msg[i].len << 8); length = msg[i + 1].len + 6; @@ -1004,6 +1008,10 @@ static int az6027_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], int n /* demod 16bit addr */ req = 0xBD; + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } index = (((msg[i].buf[0] << 8) & 0xff00) | (msg[i].buf[1] & 0x00ff)); value = msg[i].addr + (2 << 8); length = msg[i].len - 2; @@ -1029,6 +1037,10 @@ static int az6027_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], int n } else { req = 0xBD; + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } index = msg[i].buf[0] & 0x00FF; value = msg[i].addr + (1 << 8); length = msg[i].len - 1; diff --git a/drivers/media/usb/dvb-usb/digitv.c b/drivers/media/usb/dvb-usb/digitv.c index e66df4fd1a296d22ed3a1a0307c8403c0cc001c3..6e556a2a74103e76521762ad1c6a640d87d18e02 100644 --- a/drivers/media/usb/dvb-usb/digitv.c +++ b/drivers/media/usb/dvb-usb/digitv.c @@ -66,6 +66,10 @@ static int digitv_i2c_xfer(struct i2c_adapter *adap,struct i2c_msg msg[],int num warn("more than 2 i2c messages at a time is not handled yet. TODO."); for (i = 0; i < num; i++) { + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } /* write/read request */ if (i+1 < num && (msg[i+1].flags & I2C_M_RD)) { if (digitv_ctrl_msg(d, USB_READ_COFDM, msg[i].buf[0], NULL, 0, diff --git a/drivers/media/usb/dvb-usb/dw2102.c b/drivers/media/usb/dvb-usb/dw2102.c index ebb0c982a6f21604b4681b08e131cfd760547bee..a3c5261f9aa41391384b059896b917cd2a4258eb 100644 --- a/drivers/media/usb/dvb-usb/dw2102.c +++ b/drivers/media/usb/dvb-usb/dw2102.c @@ -131,6 +131,10 @@ static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], switch (num) { case 2: + if (msg[0].len < 1) { + num = -EOPNOTSUPP; + break; + } /* read stv0299 register */ value = msg[0].buf[0];/* register */ for (i = 0; i < msg[1].len; i++) { @@ -142,6 +146,10 @@ static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], case 1: switch (msg[0].addr) { case 0x68: + if (msg[0].len < 2) { + num = -EOPNOTSUPP; + break; + } /* write to stv0299 register */ buf6[0] = 0x2a; buf6[1] = msg[0].buf[0]; @@ -151,6 +159,10 @@ static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], break; case 0x60: if (msg[0].flags == 0) { + if (msg[0].len < 4) { + num = -EOPNOTSUPP; + break; + } /* write to tuner pll */ buf6[0] = 0x2c; buf6[1] = 5; @@ -162,6 +174,10 @@ static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], dw210x_op_rw(d->udev, 0xb2, 0, 0, buf6, 7, DW210X_WRITE_MSG); } else { + if (msg[0].len < 1) { + num = -EOPNOTSUPP; + break; + } /* read from tuner */ dw210x_op_rw(d->udev, 0xb5, 0, 0, buf6, 1, DW210X_READ_MSG); @@ -169,12 +185,20 @@ static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], } break; case (DW2102_RC_QUERY): + if (msg[0].len < 2) { + num = -EOPNOTSUPP; + break; + } dw210x_op_rw(d->udev, 0xb8, 0, 0, buf6, 2, DW210X_READ_MSG); msg[0].buf[0] = buf6[0]; msg[0].buf[1] = buf6[1]; break; case (DW2102_VOLTAGE_CTRL): + if (msg[0].len < 1) { + num = -EOPNOTSUPP; + break; + } buf6[0] = 0x30; buf6[1] = msg[0].buf[0]; dw210x_op_rw(d->udev, 0xb2, 0, 0, @@ -949,7 +973,7 @@ static int su3000_read_mac_address(struct dvb_usb_device *d, u8 mac[6]) for (i = 0; i < 6; i++) { obuf[1] = 0xf0 + i; if (i2c_transfer(&d->i2c_adap, msg, 2) != 2) - break; + return -1; else mac[i] = ibuf[0]; } diff --git a/drivers/media/usb/dvb-usb/m920x.c b/drivers/media/usb/dvb-usb/m920x.c index 3b2a0f36fc38e11924f50b26ed845ee3c91e9b4a..e5491b9b8825c062ef755b5af2cbd856f36e05e7 100644 --- a/drivers/media/usb/dvb-usb/m920x.c +++ b/drivers/media/usb/dvb-usb/m920x.c @@ -280,7 +280,6 @@ static int m920x_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], int nu char *read = kmalloc(1, GFP_KERNEL); if (!read) { ret = -ENOMEM; - kfree(read); goto unlock; } @@ -291,8 +290,10 @@ static int m920x_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], int nu if ((ret = m920x_read(d->udev, M9206_I2C, 0x0, 0x20 | stop, - read, 1)) != 0) + read, 1)) != 0) { + kfree(read); goto unlock; + } msg[i].buf[j] = read[0]; } diff --git a/drivers/media/usb/go7007/go7007-i2c.c b/drivers/media/usb/go7007/go7007-i2c.c index c084bf794b56772fdec9f85b8a3200d8ad963a2d..64f25d4e52b20a602febbc9587875504da0ab859 100644 --- a/drivers/media/usb/go7007/go7007-i2c.c +++ b/drivers/media/usb/go7007/go7007-i2c.c @@ -173,8 +173,6 @@ static int go7007_i2c_master_xfer(struct i2c_adapter *adapter, } else if (msgs[i].len == 3) { if (msgs[i].flags & I2C_M_RD) return -EIO; - if (msgs[i].len != 3) - return -EIO; if (go7007_i2c_xfer(go, msgs[i].addr, 0, (msgs[i].buf[0] << 8) | msgs[i].buf[1], 0x01, &msgs[i].buf[2]) < 0) diff --git a/drivers/media/usb/gspca/cpia1.c b/drivers/media/usb/gspca/cpia1.c index 2b09af8865f40f5fc91cc943205e42cf921f9462..5e785343528cc03f2b6f71264b830aae56f1e158 100644 --- a/drivers/media/usb/gspca/cpia1.c +++ b/drivers/media/usb/gspca/cpia1.c @@ -28,6 +28,7 @@ #include #include +#include #include "gspca.h" @@ -1033,6 +1034,8 @@ static int set_flicker(struct gspca_dev *gspca_dev, int on, int apply) sd->params.exposure.expMode = 2; sd->exposure_status = EXPOSURE_NORMAL; } + if (sd->params.exposure.gain >= BITS_PER_TYPE(currentexp)) + return -EINVAL; currentexp = currentexp << sd->params.exposure.gain; sd->params.exposure.gain = 0; /* round down current exposure to nearest value */ diff --git a/drivers/media/usb/gspca/vicam.c b/drivers/media/usb/gspca/vicam.c index 8562bda0ef88609da08da0e93da49733a2bcaa6b..624fdcfdc85a6e8210a7096da3c66ec216de1e32 100644 --- a/drivers/media/usb/gspca/vicam.c +++ b/drivers/media/usb/gspca/vicam.c @@ -234,7 +234,7 @@ static int sd_init(struct gspca_dev *gspca_dev) { int ret; const struct ihex_binrec *rec; - const struct firmware *uninitialized_var(fw); + const struct firmware *fw; u8 *firmware_buf; ret = request_ihex_firmware(&fw, VICAM_FIRMWARE, diff --git a/drivers/media/usb/siano/smsusb.c b/drivers/media/usb/siano/smsusb.c index 3071d9bc77f48827e4c1fda351808da1c3886307..62e4fecc57d9cd7282408f3e6a2c1e4306650f52 100644 --- a/drivers/media/usb/siano/smsusb.c +++ b/drivers/media/usb/siano/smsusb.c @@ -190,6 +190,8 @@ static void smsusb_stop_streaming(struct smsusb_device_t *dev) for (i = 0; i < MAX_URBS; i++) { usb_kill_urb(&dev->surbs[i].urb); + if (dev->surbs[i].wq.func) + cancel_work_sync(&dev->surbs[i].wq); if (dev->surbs[i].cb) { smscore_putbuffer(dev->coredev, dev->surbs[i].cb); @@ -465,12 +467,7 @@ static int smsusb_init_device(struct usb_interface *intf, int board_id) rc = smscore_register_device(¶ms, &dev->coredev, 0, mdev); if (rc < 0) { pr_err("smscore_register_device(...) failed, rc %d\n", rc); - smsusb_term_device(intf); -#ifdef CONFIG_MEDIA_CONTROLLER_DVB - media_device_unregister(mdev); -#endif - kfree(mdev); - return rc; + goto err_unregister_device; } smscore_set_board_id(dev->coredev, board_id); @@ -487,8 +484,7 @@ static int smsusb_init_device(struct usb_interface *intf, int board_id) rc = smsusb_start_streaming(dev); if (rc < 0) { pr_err("smsusb_start_streaming(...) failed\n"); - smsusb_term_device(intf); - return rc; + goto err_unregister_device; } dev->state = SMSUSB_ACTIVE; @@ -496,13 +492,20 @@ static int smsusb_init_device(struct usb_interface *intf, int board_id) rc = smscore_start_device(dev->coredev); if (rc < 0) { pr_err("smscore_start_device(...) failed\n"); - smsusb_term_device(intf); - return rc; + goto err_unregister_device; } pr_debug("device 0x%p created\n", dev); return rc; + +err_unregister_device: + smsusb_term_device(intf); +#ifdef CONFIG_MEDIA_CONTROLLER_DVB + media_device_unregister(mdev); +#endif + kfree(mdev); + return rc; } static int smsusb_probe(struct usb_interface *intf, diff --git a/drivers/media/usb/ttusb-dec/ttusb_dec.c b/drivers/media/usb/ttusb-dec/ttusb_dec.c index f34efa7c61b40c9dd71c7bc6be2d519374664a07..c915e555897ba336748e04656daef1516878da58 100644 --- a/drivers/media/usb/ttusb-dec/ttusb_dec.c +++ b/drivers/media/usb/ttusb-dec/ttusb_dec.c @@ -1561,8 +1561,7 @@ static void ttusb_dec_exit_dvb(struct ttusb_dec *dec) dvb_dmx_release(&dec->demux); if (dec->fe) { dvb_unregister_frontend(dec->fe); - if (dec->fe->ops.release) - dec->fe->ops.release(dec->fe); + dvb_frontend_detach(dec->fe); } dvb_unregister_adapter(&dec->adapter); } diff --git a/drivers/media/usb/uvc/uvc_ctrl.c b/drivers/media/usb/uvc/uvc_ctrl.c index 9192037238631304c65ef36a5bfc3cfcc978d0fa..138bdfa359b7a77a0b7bf76c16d23cdf8f1aec5d 100644 --- a/drivers/media/usb/uvc/uvc_ctrl.c +++ b/drivers/media/usb/uvc/uvc_ctrl.c @@ -11,6 +11,7 @@ * */ +#include #include #include #include @@ -1280,17 +1281,12 @@ static void uvc_ctrl_send_slave_event(struct uvc_video_chain *chain, uvc_ctrl_send_event(chain, handle, ctrl, mapping, val, changes); } -static void uvc_ctrl_status_event_work(struct work_struct *work) +void uvc_ctrl_status_event(struct uvc_video_chain *chain, + struct uvc_control *ctrl, const u8 *data) { - struct uvc_device *dev = container_of(work, struct uvc_device, - async_ctrl.work); - struct uvc_ctrl_work *w = &dev->async_ctrl; - struct uvc_video_chain *chain = w->chain; struct uvc_control_mapping *mapping; - struct uvc_control *ctrl = w->ctrl; struct uvc_fh *handle; unsigned int i; - int ret; mutex_lock(&chain->ctrl_mutex); @@ -1298,7 +1294,7 @@ static void uvc_ctrl_status_event_work(struct work_struct *work) ctrl->handle = NULL; list_for_each_entry(mapping, &ctrl->info.mappings, list) { - s32 value = __uvc_ctrl_get_value(mapping, w->data); + s32 value = __uvc_ctrl_get_value(mapping, data); /* * handle may be NULL here if the device sends auto-update @@ -1317,6 +1313,20 @@ static void uvc_ctrl_status_event_work(struct work_struct *work) } mutex_unlock(&chain->ctrl_mutex); +} + +static void uvc_ctrl_status_event_work(struct work_struct *work) +{ + struct uvc_device *dev = container_of(work, struct uvc_device, + async_ctrl.work); + struct uvc_ctrl_work *w = &dev->async_ctrl; + int ret; + + uvc_ctrl_status_event(w->chain, w->ctrl, w->data); + + /* The barrier is needed to synchronize with uvc_status_stop(). */ + if (smp_load_acquire(&dev->flush_status)) + return; /* Resubmit the URB. */ w->urb->interval = dev->int_ep->desc.bInterval; @@ -1326,8 +1336,8 @@ static void uvc_ctrl_status_event_work(struct work_struct *work) ret); } -bool uvc_ctrl_status_event(struct urb *urb, struct uvc_video_chain *chain, - struct uvc_control *ctrl, const u8 *data) +bool uvc_ctrl_status_event_async(struct urb *urb, struct uvc_video_chain *chain, + struct uvc_control *ctrl, const u8 *data) { struct uvc_device *dev = chain->dev; struct uvc_ctrl_work *w = &dev->async_ctrl; diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c index 70801893cba0dfc481e6a99d85164cfc9027a19d..62d43ae7a1b759f8b374ec78f8c6a36dc55e535b 100644 --- a/drivers/media/usb/uvc/uvc_driver.c +++ b/drivers/media/usb/uvc/uvc_driver.c @@ -1033,10 +1033,8 @@ static int uvc_parse_vendor_control(struct uvc_device *dev, + n; memcpy(unit->extension.bmControls, &buffer[23+p], 2*n); - if (buffer[24+p+2*n] != 0) - usb_string(udev, buffer[24+p+2*n], unit->name, - sizeof(unit->name)); - else + if (buffer[24+p+2*n] == 0 || + usb_string(udev, buffer[24+p+2*n], unit->name, sizeof(unit->name)) < 0) sprintf(unit->name, "Extension %u", buffer[3]); list_add_tail(&unit->list, &dev->entities); @@ -1161,15 +1159,15 @@ static int uvc_parse_standard_control(struct uvc_device *dev, memcpy(term->media.bmTransportModes, &buffer[10+n], p); } - if (buffer[7] != 0) - usb_string(udev, buffer[7], term->name, - sizeof(term->name)); - else if (UVC_ENTITY_TYPE(term) == UVC_ITT_CAMERA) - sprintf(term->name, "Camera %u", buffer[3]); - else if (UVC_ENTITY_TYPE(term) == UVC_ITT_MEDIA_TRANSPORT_INPUT) - sprintf(term->name, "Media %u", buffer[3]); - else - sprintf(term->name, "Input %u", buffer[3]); + if (buffer[7] == 0 || + usb_string(udev, buffer[7], term->name, sizeof(term->name)) < 0) { + if (UVC_ENTITY_TYPE(term) == UVC_ITT_CAMERA) + sprintf(term->name, "Camera %u", buffer[3]); + if (UVC_ENTITY_TYPE(term) == UVC_ITT_MEDIA_TRANSPORT_INPUT) + sprintf(term->name, "Media %u", buffer[3]); + else + sprintf(term->name, "Input %u", buffer[3]); + } list_add_tail(&term->list, &dev->entities); break; @@ -1201,10 +1199,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, memcpy(term->baSourceID, &buffer[7], 1); - if (buffer[8] != 0) - usb_string(udev, buffer[8], term->name, - sizeof(term->name)); - else + if (buffer[8] == 0 || + usb_string(udev, buffer[8], term->name, sizeof(term->name)) < 0) sprintf(term->name, "Output %u", buffer[3]); list_add_tail(&term->list, &dev->entities); @@ -1226,10 +1222,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, memcpy(unit->baSourceID, &buffer[5], p); - if (buffer[5+p] != 0) - usb_string(udev, buffer[5+p], unit->name, - sizeof(unit->name)); - else + if (buffer[5+p] == 0 || + usb_string(udev, buffer[5+p], unit->name, sizeof(unit->name)) < 0) sprintf(unit->name, "Selector %u", buffer[3]); list_add_tail(&unit->list, &dev->entities); @@ -1259,10 +1253,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, if (dev->uvc_version >= 0x0110) unit->processing.bmVideoStandards = buffer[9+n]; - if (buffer[8+n] != 0) - usb_string(udev, buffer[8+n], unit->name, - sizeof(unit->name)); - else + if (buffer[8+n] == 0 || + usb_string(udev, buffer[8+n], unit->name, sizeof(unit->name)) < 0) sprintf(unit->name, "Processing %u", buffer[3]); list_add_tail(&unit->list, &dev->entities); @@ -1290,10 +1282,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, unit->extension.bmControls = (u8 *)unit + sizeof(*unit); memcpy(unit->extension.bmControls, &buffer[23+p], n); - if (buffer[23+p+n] != 0) - usb_string(udev, buffer[23+p+n], unit->name, - sizeof(unit->name)); - else + if (buffer[23+p+n] == 0 || + usb_string(udev, buffer[23+p+n], unit->name, sizeof(unit->name)) < 0) sprintf(unit->name, "Extension %u", buffer[3]); list_add_tail(&unit->list, &dev->entities); diff --git a/drivers/media/usb/uvc/uvc_entity.c b/drivers/media/usb/uvc/uvc_entity.c index f2457953f27c60454b95c72d460214988f27b50b..0d5aaaa7e2d96d22e32006c7ba417287017a024b 100644 --- a/drivers/media/usb/uvc/uvc_entity.c +++ b/drivers/media/usb/uvc/uvc_entity.c @@ -42,7 +42,7 @@ static int uvc_mc_create_links(struct uvc_video_chain *chain, continue; remote = uvc_entity_by_id(chain->dev, entity->baSourceID[i]); - if (remote == NULL) + if (remote == NULL || remote->num_pads == 0) return -EINVAL; source = (UVC_ENTITY_TYPE(remote) == UVC_TT_STREAMING) diff --git a/drivers/media/usb/uvc/uvc_status.c b/drivers/media/usb/uvc/uvc_status.c index 883e4cab45e79b1d3e1d0636963acfac73aa420b..141ac1ffb42ee96b7e96c07e7802d61645dcb55a 100644 --- a/drivers/media/usb/uvc/uvc_status.c +++ b/drivers/media/usb/uvc/uvc_status.c @@ -11,6 +11,7 @@ * */ +#include #include #include #include @@ -184,7 +185,8 @@ static bool uvc_event_control(struct urb *urb, switch (status->bAttribute) { case UVC_CTRL_VALUE_CHANGE: - return uvc_ctrl_status_event(urb, chain, ctrl, status->bValue); + return uvc_ctrl_status_event_async(urb, chain, ctrl, + status->bValue); case UVC_CTRL_INFO_CHANGE: case UVC_CTRL_FAILURE_CHANGE: @@ -314,5 +316,41 @@ int uvc_status_start(struct uvc_device *dev, gfp_t flags) void uvc_status_stop(struct uvc_device *dev) { + struct uvc_ctrl_work *w = &dev->async_ctrl; + + /* + * Prevent the asynchronous control handler from requeing the URB. The + * barrier is needed so the flush_status change is visible to other + * CPUs running the asynchronous handler before usb_kill_urb() is + * called below. + */ + smp_store_release(&dev->flush_status, true); + + /* + * Cancel any pending asynchronous work. If any status event was queued, + * process it synchronously. + */ + if (cancel_work_sync(&w->work)) + uvc_ctrl_status_event(w->chain, w->ctrl, w->data); + + /* Kill the urb. */ usb_kill_urb(dev->int_urb); + + /* + * The URB completion handler may have queued asynchronous work. This + * won't resubmit the URB as flush_status is set, but it needs to be + * cancelled before returning or it could then race with a future + * uvc_status_start() call. + */ + if (cancel_work_sync(&w->work)) + uvc_ctrl_status_event(w->chain, w->ctrl, w->data); + + /* + * From this point, there are no events on the queue and the status URB + * is dead. No events will be queued until uvc_status_start() is called. + * The barrier is needed to make sure that flush_status is visible to + * uvc_ctrl_status_event_work() when uvc_status_start() will be called + * again. + */ + smp_store_release(&dev->flush_status, false); } diff --git a/drivers/media/usb/uvc/uvc_video.c b/drivers/media/usb/uvc/uvc_video.c index b1b514b735c07ab72d24ec00d84f183a86169337..020d6272eae3c0a76c85a13edc624ba6a0ae1116 100644 --- a/drivers/media/usb/uvc/uvc_video.c +++ b/drivers/media/usb/uvc/uvc_video.c @@ -804,9 +804,9 @@ static void uvc_video_stats_decode(struct uvc_streaming *stream, unsigned int header_size; bool has_pts = false; bool has_scr = false; - u16 uninitialized_var(scr_sof); - u32 uninitialized_var(scr_stc); - u32 uninitialized_var(pts); + u16 scr_sof; + u32 scr_stc; + u32 pts; if (stream->stats.stream.nb_frames == 0 && stream->stats.frame.nb_packets == 0) @@ -1280,7 +1280,9 @@ static void uvc_video_decode_meta(struct uvc_streaming *stream, if (has_scr) memcpy(stream->clock.last_scr, scr, 6); - memcpy(&meta->length, mem, length); + meta->length = mem[0]; + meta->flags = mem[1]; + memcpy(meta->buf, &mem[2], length - 2); meta_buf->bytesused += length + sizeof(meta->ns) + sizeof(meta->sof); uvc_trace(UVC_TRACE_FRAME, @@ -1813,7 +1815,7 @@ static int uvc_init_video(struct uvc_streaming *stream, gfp_t gfp_flags) struct usb_host_endpoint *best_ep = NULL; unsigned int best_psize = UINT_MAX; unsigned int bandwidth; - unsigned int uninitialized_var(altsetting); + unsigned int altsetting; int intfnum = stream->intfnum; /* Isochronous endpoint, select the alternate setting. */ diff --git a/drivers/media/usb/uvc/uvcvideo.h b/drivers/media/usb/uvc/uvcvideo.h index a89f8ed9c5a9e0e4c0f79d1743dbd1ff807d4cb6..f335249c93da60c98d18e94b285d06792b9776aa 100644 --- a/drivers/media/usb/uvc/uvcvideo.h +++ b/drivers/media/usb/uvc/uvcvideo.h @@ -612,6 +612,7 @@ struct uvc_device { /* Status Interrupt Endpoint */ struct usb_host_endpoint *int_ep; struct urb *int_urb; + bool flush_status; u8 *status; struct input_dev *input; char input_phys[64]; @@ -777,7 +778,9 @@ int uvc_ctrl_add_mapping(struct uvc_video_chain *chain, int uvc_ctrl_init_device(struct uvc_device *dev); void uvc_ctrl_cleanup_device(struct uvc_device *dev); int uvc_ctrl_restore_values(struct uvc_device *dev); -bool uvc_ctrl_status_event(struct urb *urb, struct uvc_video_chain *chain, +bool uvc_ctrl_status_event_async(struct urb *urb, struct uvc_video_chain *chain, + struct uvc_control *ctrl, const u8 *data); +void uvc_ctrl_status_event(struct uvc_video_chain *chain, struct uvc_control *ctrl, const u8 *data); int uvc_ctrl_begin(struct uvc_video_chain *chain); diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c index 169bdbb1f61a51305257a04882dfc87db4b19117..95079229a772b105843dea309bb52e1a4e9ba0cc 100644 --- a/drivers/media/v4l2-core/v4l2-fwnode.c +++ b/drivers/media/v4l2-core/v4l2-fwnode.c @@ -279,37 +279,38 @@ struct v4l2_fwnode_endpoint *v4l2_fwnode_endpoint_alloc_parse( } EXPORT_SYMBOL_GPL(v4l2_fwnode_endpoint_alloc_parse); -int v4l2_fwnode_parse_link(struct fwnode_handle *__fwnode, +int v4l2_fwnode_parse_link(struct fwnode_handle *fwnode, struct v4l2_fwnode_link *link) { - const char *port_prop = is_of_node(__fwnode) ? "reg" : "port"; - struct fwnode_handle *fwnode; + struct fwnode_endpoint fwep; memset(link, 0, sizeof(*link)); - fwnode = fwnode_get_parent(__fwnode); - fwnode_property_read_u32(fwnode, port_prop, &link->local_port); - fwnode = fwnode_get_next_parent(fwnode); - if (is_of_node(fwnode) && - of_node_cmp(to_of_node(fwnode)->name, "ports") == 0) - fwnode = fwnode_get_next_parent(fwnode); - link->local_node = fwnode; - - fwnode = fwnode_graph_get_remote_endpoint(__fwnode); - if (!fwnode) { - fwnode_handle_put(fwnode); + fwnode_graph_parse_endpoint(fwnode, &fwep); + link->local_port = fwep.port; + link->local_node = fwnode_graph_get_port_parent(fwnode); + if (!link->local_node) return -ENOLINK; - } - fwnode = fwnode_get_parent(fwnode); - fwnode_property_read_u32(fwnode, port_prop, &link->remote_port); - fwnode = fwnode_get_next_parent(fwnode); - if (is_of_node(fwnode) && - of_node_cmp(to_of_node(fwnode)->name, "ports") == 0) - fwnode = fwnode_get_next_parent(fwnode); - link->remote_node = fwnode; + fwnode = fwnode_graph_get_remote_endpoint(fwnode); + if (!fwnode) + goto err_put_local_node; + + fwnode_graph_parse_endpoint(fwnode, &fwep); + link->remote_port = fwep.port; + link->remote_node = fwnode_graph_get_port_parent(fwnode); + if (!link->remote_node) + goto err_put_remote_endpoint; return 0; + +err_put_remote_endpoint: + fwnode_handle_put(fwnode); + +err_put_local_node: + fwnode_handle_put(link->local_node); + + return -ENOLINK; } EXPORT_SYMBOL_GPL(v4l2_fwnode_parse_link); diff --git a/drivers/memstick/core/memstick.c b/drivers/memstick/core/memstick.c index 20ae8652adf4484f6ff2b4e71320332705225694..0849f4d76ff209336c3554f94b66707d854dc79c 100644 --- a/drivers/memstick/core/memstick.c +++ b/drivers/memstick/core/memstick.c @@ -416,6 +416,7 @@ static struct memstick_dev *memstick_alloc_card(struct memstick_host *host) return card; err_out: host->card = old_card; + kfree_const(card->dev.kobj.name); kfree(card); return NULL; } @@ -471,8 +472,10 @@ static void memstick_check(struct work_struct *work) put_device(&card->dev); host->card = NULL; } - } else + } else { + kfree_const(card->dev.kobj.name); kfree(card); + } } out_power_off: diff --git a/drivers/memstick/host/jmb38x_ms.c b/drivers/memstick/host/jmb38x_ms.c index 0610d3c9f131891feae5b6d4d435a79b112955f5..9f65db9a69b3d5e90b6abf77fb3ffb3470fa51a0 100644 --- a/drivers/memstick/host/jmb38x_ms.c +++ b/drivers/memstick/host/jmb38x_ms.c @@ -316,7 +316,7 @@ static int jmb38x_ms_transfer_data(struct jmb38x_ms_host *host) } while (length) { - unsigned int uninitialized_var(p_off); + unsigned int p_off; if (host->req->long_data) { pg = nth_page(sg_page(&host->req->sg), diff --git a/drivers/memstick/host/r592.c b/drivers/memstick/host/r592.c index 4728a42d54b884fce8535c75bf1427c4e4964317..6360f5c6d3958596545f8889674a9da57a694508 100644 --- a/drivers/memstick/host/r592.c +++ b/drivers/memstick/host/r592.c @@ -47,12 +47,10 @@ static const char *tpc_names[] = { * memstick_debug_get_tpc_name - debug helper that returns string for * a TPC number */ -const char *memstick_debug_get_tpc_name(int tpc) +static __maybe_unused const char *memstick_debug_get_tpc_name(int tpc) { return tpc_names[tpc-1]; } -EXPORT_SYMBOL(memstick_debug_get_tpc_name); - /* Read a register*/ static inline u32 r592_read_reg(struct r592_device *dev, int address) @@ -831,7 +829,7 @@ static void r592_remove(struct pci_dev *pdev) /* Stop the processing thread. That ensures that we won't take any more requests */ kthread_stop(dev->io_thread); - + del_timer_sync(&dev->detect_timer); r592_enable_device(dev, false); while (!error && dev->req) { diff --git a/drivers/memstick/host/tifm_ms.c b/drivers/memstick/host/tifm_ms.c index bed205849d027020e260dfa4b68ac3fba8aaa9ed..ecd8d71f8a398524c95d916f70e336aec5cad5d9 100644 --- a/drivers/memstick/host/tifm_ms.c +++ b/drivers/memstick/host/tifm_ms.c @@ -200,7 +200,7 @@ static unsigned int tifm_ms_transfer_data(struct tifm_ms *host) host->block_pos); while (length) { - unsigned int uninitialized_var(p_off); + unsigned int p_off; if (host->req->long_data) { pg = nth_page(sg_page(&host->req->sg), diff --git a/drivers/message/fusion/mptlan.c b/drivers/message/fusion/mptlan.c index ebc00d47abf5243dee30ec4266e0726836b88883..624803a887d8f394eda1d6afe8af43f7cbcd9016 100644 --- a/drivers/message/fusion/mptlan.c +++ b/drivers/message/fusion/mptlan.c @@ -1430,7 +1430,9 @@ mptlan_remove(struct pci_dev *pdev) { MPT_ADAPTER *ioc = pci_get_drvdata(pdev); struct net_device *dev = ioc->netdev; + struct mpt_lan_priv *priv = netdev_priv(dev); + cancel_delayed_work_sync(&priv->post_buckets_task); if(dev != NULL) { unregister_netdev(dev); free_netdev(dev); diff --git a/drivers/mfd/intel-lpss-acpi.c b/drivers/mfd/intel-lpss-acpi.c index fc44fb7c595bca0ae94266071c49e06881e186a8..281ef5f52eb555cacc8d5bb7fd5a9f7d0190fdd6 100644 --- a/drivers/mfd/intel-lpss-acpi.c +++ b/drivers/mfd/intel-lpss-acpi.c @@ -92,6 +92,9 @@ static int intel_lpss_acpi_probe(struct platform_device *pdev) return -ENOMEM; info->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!info->mem) + return -ENODEV; + info->irq = platform_get_irq(pdev, 0); ret = intel_lpss_probe(&pdev->dev, info); diff --git a/drivers/mfd/pcf50633-adc.c b/drivers/mfd/pcf50633-adc.c index c1984b0d1b65273d64651f73e7f9c92fc0ef4e35..a4a765055ee6b38cdcac2955f76b54d6f0adf258 100644 --- a/drivers/mfd/pcf50633-adc.c +++ b/drivers/mfd/pcf50633-adc.c @@ -140,6 +140,7 @@ int pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg, void *callback_param) { struct pcf50633_adc_request *req; + int ret; /* req is freed when the result is ready, in interrupt handler */ req = kmalloc(sizeof(*req), GFP_KERNEL); @@ -151,7 +152,11 @@ int pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg, req->callback = callback; req->callback_param = callback_param; - return adc_enqueue_request(pcf, req); + ret = adc_enqueue_request(pcf, req); + if (ret) + kfree(req); + + return ret; } EXPORT_SYMBOL_GPL(pcf50633_adc_async_read); diff --git a/drivers/mfd/qcom-spmi-pmic.c b/drivers/mfd/qcom-spmi-pmic.c index 43af70a8a81b0d887546a11f5b892ae0bae2b320..49891ff3bf34b86e3c3233ca8e1e396fcc09be77 100644 --- a/drivers/mfd/qcom-spmi-pmic.c +++ b/drivers/mfd/qcom-spmi-pmic.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2014-2015, 2017-2019, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -143,8 +144,11 @@ static int pmic_spmi_probe(struct spmi_device *sdev) MODULE_DEVICE_TABLE(of, pmic_spmi_id_table); +static void pmic_spmi_remove(struct spmi_device *sdev) {} + static struct spmi_driver pmic_spmi_driver = { .probe = pmic_spmi_probe, + .remove = pmic_spmi_remove, .driver = { .name = "pmic-spmi", .of_match_table = pmic_spmi_id_table, diff --git a/drivers/mfd/rt5033.c b/drivers/mfd/rt5033.c index 9bd089c563753b6cb85a7de43ebbdcedcf86738f..94cdad91c06578bddf8a09f8f4c1aac2934def59 100644 --- a/drivers/mfd/rt5033.c +++ b/drivers/mfd/rt5033.c @@ -44,9 +44,6 @@ static const struct mfd_cell rt5033_devs[] = { { .name = "rt5033-charger", .of_compatible = "richtek,rt5033-charger", - }, { - .name = "rt5033-battery", - .of_compatible = "richtek,rt5033-battery", }, { .name = "rt5033-led", .of_compatible = "richtek,rt5033-led", diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c index 722ad2c368a56bce6f9bde915bcf72a787b053c9..d752c56d60e42dffc54d7f122624e562a5afaadf 100644 --- a/drivers/mfd/stmpe.c +++ b/drivers/mfd/stmpe.c @@ -1428,9 +1428,9 @@ int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum) int stmpe_remove(struct stmpe *stmpe) { - if (!IS_ERR(stmpe->vio)) + if (!IS_ERR(stmpe->vio) && regulator_is_enabled(stmpe->vio)) regulator_disable(stmpe->vio); - if (!IS_ERR(stmpe->vcc)) + if (!IS_ERR(stmpe->vcc) && regulator_is_enabled(stmpe->vcc)) regulator_disable(stmpe->vcc); mfd_remove_devices(stmpe->dev); diff --git a/drivers/misc/kxrctrl/aphost.c b/drivers/misc/kxrctrl/aphost.c index bc6ceebd85ee82c164f91bc48ecf43922d047e15..ce8254139d913d730ea3898bef28fa0ba19e8250 100644 --- a/drivers/misc/kxrctrl/aphost.c +++ b/drivers/misc/kxrctrl/aphost.c @@ -6,7 +6,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "aphost.h" @@ -226,6 +226,10 @@ static ssize_t jsrequest_show(struct device *dev, } else { size = scnprintf(buf, PAGE_SIZE, "no need to ack\n"); } + pinctrl_select_state( + gspi_client->pinctrl_info.pinctrl, + gspi_client->pinctrl_info.active); + gspi_client->js_ledl_state = 0; mutex_unlock(&gspi_client->js_mutex); return size; @@ -238,12 +242,36 @@ static ssize_t jsrequest_store(struct device *dev, request_t request; int vibState = 0; int err = 0; - +#ifdef COMPATIBLE_NOT_SUPPORT_DFU + unsigned int getNorVersion = 0; +#endif if (gspi_client == NULL) { pr_err("invalid gspi_client\n"); return size; } +#ifdef COMPATIBLE_NOT_SUPPORT_DFU + getNorVersion = (unsigned int) + atomic_read(&gspi_client->probeGetNordicVersion); + if (getNorVersion <= 0x81000101 && getNorVersion > 0) { + pr_debug("%s DFU not supported version number:%d.%d\n", + __func__, (getNorVersion >> 8) & 0xff, + getNorVersion & 0xff); + } else { + pinctrl_select_state( + gspi_client->pinctrl_info.pinctrl, + gspi_client->pinctrl_info.suspend); + gspi_client->js_ledl_state = 1; + pr_debug("%s DFU supported version number:%d.%d\n", + __func__, (getNorVersion >> 8) & 0xff, + getNorVersion & 0xff); + } +#else + pinctrl_select_state( + gspi_client->pinctrl_info.pinctrl, + gspi_client->pinctrl_info.suspend); + gspi_client->js_ledl_state = 1; +#endif mutex_lock(&gspi_client->js_mutex); err = kstrtouint(buf, 16, &input); if (err) { @@ -252,9 +280,21 @@ static ssize_t jsrequest_store(struct device *dev, memset(&request, 0, sizeof(request_t)); request.requestHead.requestType = ((input & 0x7f000000) >> 24); - request.requestData[0] = (input & 0x000000ff); - request.requestData[1] = (input & 0x0000ff00); - request.requestData[2] = (input & 0x00ff0000); + if (request.requestHead.requestType == 0xc) { + request.requestData[0] = + (input & 0x000000ff); + request.requestData[1] = + ((input & 0x0000ff00) >> 8); + request.requestData[2] = + ((input & 0x00ff0000) >> 16); + } else { + request.requestData[0] = + (input & 0x000000ff); + request.requestData[1] = + (input & 0x0000ff00); + request.requestData[2] = + (input & 0x00ff0000); + } switch (request.requestHead.requestType) { case setVibStateRequest: @@ -285,6 +325,7 @@ static ssize_t jsrequest_store(struct device *dev, case getRightJoyStickProductNameRequest: case getLeftJoyStickFwVersionRequest: case getRightJoyStickFwVersionRequest: + case setControllerSleepMode: atomic_set(&gspi_client->userRequest, input); atomic_inc(&gspi_client->dataflag); @@ -466,6 +507,12 @@ static int js_thread(void *data) spi_client->txbuffer[2] = (currentRequest.requestData[0]&0x01); break; + case setControllerSleepMode: + spi_client->txbuffer[2] = + currentRequest.requestData[0]; + spi_client->txbuffer[3] = + currentRequest.requestData[1]; + break; default: break; } @@ -501,6 +548,18 @@ static int js_thread(void *data) | spi_client->rxbuffer[1]); atomic_set(&spi_client->nordicAcknowledge, input); +#ifdef COMPATIBLE_NOT_SUPPORT_DFU + if ((unsigned int) + atomic_read( + &gspi_client->probeGetNordicVersionFlag)) { + atomic_set( + &spi_client->probeGetNordicVersion, + input); + atomic_set( + &spi_client->probeGetNordicVersionFlag, + 0); + } +#endif } memset(&lastRequest, 0, sizeof(lastRequest)); } @@ -714,6 +773,59 @@ static int js_io_init(struct js_spi_client *spi_client) return ret; } +#ifdef COMPATIBLE_NOT_SUPPORT_DFU +static int probe_get_nordic_version(void) +{ + unsigned int getNorVersion = 0; + + atomic_set(&gspi_client->probeGetNordicVersionFlag, 1); + atomic_set(&gspi_client->userRequest, 0x81000000); + atomic_inc(&gspi_client->dataflag); + wake_up_interruptible(&gspi_client->wait_queue); + pinctrl_select_state( + gspi_client->pinctrl_info.pinctrl, + gspi_client->pinctrl_info.suspend); + gspi_client->js_ledl_state = 1; + while (1) { + if (!((unsigned int) + atomic_read(&gspi_client->probeGetNordicVersionFlag))) { + pr_debug("nordic version flag %d userRequest 0x%x\n", + (unsigned int)atomic_read( + &gspi_client->probeGetNordicVersionFlag), + (unsigned int)atomic_read( + &gspi_client->userRequest)); + getNorVersion = (unsigned int)atomic_read( + &gspi_client->probeGetNordicVersion); + pr_debug("nordic version %d.%d getNorVersion 0x%x\n", + (getNorVersion >> 8) & 0xff, + getNorVersion & 0xff, getNorVersion); + pinctrl_select_state( + gspi_client->pinctrl_info.pinctrl, + gspi_client->pinctrl_info.suspend); + gspi_client->js_ledl_state = 0; + } else { + atomic_set(&gspi_client->probeGetNordicVersionFlag, 1); + atomic_set(&gspi_client->userRequest, 0x81000000); + atomic_inc(&gspi_client->dataflag); + wake_up_interruptible(&gspi_client->wait_queue); + pinctrl_select_state( + gspi_client->pinctrl_info.pinctrl, + gspi_client->pinctrl_info.suspend); + gspi_client->js_ledl_state = 1; + + pr_err("Failed to get version flag %d userRequest 0x%x\n", + (unsigned int)atomic_read( + &gspi_client->probeGetNordicVersionFlag), + (unsigned int)atomic_read( + &gspi_client->userRequest)); + + } + break; + } + + return 0; +} +#endif static int js_spi_setup(struct spi_device *spi) { struct js_spi_client *spi_client; @@ -777,6 +889,10 @@ static int js_spi_setup(struct spi_device *spi) js_io_init(spi_client); js_set_power(1); +#ifdef COMPATIBLE_NOT_SUPPORT_DFU + msleep(5000); + probe_get_nordic_version(); +#endif return rc; spi_free: diff --git a/drivers/misc/kxrctrl/aphost.h b/drivers/misc/kxrctrl/aphost.h index 2d7612fc73f89a328ab20d10c349726bdd683265..e9812a4cc2ad55571a26801b305b291da5461dba 100644 --- a/drivers/misc/kxrctrl/aphost.h +++ b/drivers/misc/kxrctrl/aphost.h @@ -6,7 +6,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __APHOST_H__ @@ -70,12 +70,13 @@ #include #include #include - +#include #include #define MAX_PACK_SIZE 100 #define MAX_DATA_SIZE 32 //#define MANUL_CONTROL_JOYSTICK_RLED +#define COMPATIBLE_NOT_SUPPORT_DFU #define XFR_SIZE 190 /* Protocol commands to interact with firmware */ @@ -109,6 +110,7 @@ typedef enum _requestType_t getRightJoyStickProductNameRequest, getLeftJoyStickFwVersionRequest, getRightJoyStickFwVersionRequest, + setControllerSleepMode = 12, invalidRequest, } requestType_t; @@ -153,6 +155,12 @@ struct js_spi_client { atomic_t dataflag; atomic_t userRequest; /* request from userspace */ atomic_t nordicAcknowledge; /* ack from nordic52832 master */ + +#ifdef COMPATIBLE_NOT_SUPPORT_DFU + atomic_t probeGetNordicVersion; /* ack from nordic52832 master */ + atomic_t probeGetNordicVersionFlag; +#endif + unsigned char JoyStickBondState; /* 1:left JoyStick 2:right JoyStick */ bool suspend; wait_queue_head_t wait_queue; diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index 198e030e5b3d543ab2d225776b41adce3017b791..14f3e05643fc358fd6606e5fa857158e8885e123 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -174,7 +174,7 @@ static int mei_fwver(struct mei_cl_device *cldev) ret = __mei_cl_send(cldev->cl, buf, sizeof(struct mkhi_msg_hdr), MEI_CL_IO_TX_BLOCKING); if (ret < 0) { - dev_err(&cldev->dev, "Could not send ReqFWVersion cmd\n"); + dev_err(&cldev->dev, "Could not send ReqFWVersion cmd ret = %d\n", ret); return ret; } @@ -186,7 +186,7 @@ static int mei_fwver(struct mei_cl_device *cldev) * Should be at least one version block, * error out if nothing found */ - dev_err(&cldev->dev, "Could not read FW version\n"); + dev_err(&cldev->dev, "Could not read FW version ret = %d\n", bytes_recv); return -EIO; } @@ -335,7 +335,7 @@ static int mei_nfc_if_version(struct mei_cl *cl, ret = __mei_cl_send(cl, (u8 *)&cmd, sizeof(struct mei_nfc_cmd), MEI_CL_IO_TX_BLOCKING); if (ret < 0) { - dev_err(bus->dev, "Could not send IF version cmd\n"); + dev_err(bus->dev, "Could not send IF version cmd ret = %d\n", ret); return ret; } @@ -350,7 +350,7 @@ static int mei_nfc_if_version(struct mei_cl *cl, ret = 0; bytes_recv = __mei_cl_recv(cl, (u8 *)reply, if_version_length, 0, 0); if (bytes_recv < 0 || (size_t)bytes_recv < if_version_length) { - dev_err(bus->dev, "Could not read IF version\n"); + dev_err(bus->dev, "Could not read IF version ret = %d\n", bytes_recv); ret = -EIO; goto err; } diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 7d166f57f624227a90db4e5d18eeecb012d095bc..e5b05e11675b4ff494be3ef65a13a1822cfa6e82 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -601,6 +601,10 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, struct pci_dev *pdev = test->pdev; mutex_lock(&test->mutex); + + reinit_completion(&test->irq_raised); + test->last_irq = -ENODATA; + switch (cmd) { case PCITEST_BAR: bar = arg; @@ -785,6 +789,9 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev) if (id < 0) return; + pci_endpoint_test_release_irq(test); + pci_endpoint_test_free_irq_vectors(test); + misc_deregister(&test->miscdev); kfree(misc_device->name); ida_simple_remove(&pci_endpoint_test_ida, id); @@ -793,9 +800,6 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev) pci_iounmap(pdev, test->bar[bar]); } - pci_endpoint_test_release_irq(test); - pci_endpoint_test_free_irq_vectors(test); - pci_release_regions(pdev); pci_disable_device(pdev); } diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c index f0976209d6bafc7d12c622e3dc5142a3ce35f57f..e631c55ac124c8dc7b7f98b8f21d2fcaf203b581 100644 --- a/drivers/misc/qseecom.c +++ b/drivers/misc/qseecom.c @@ -3,7 +3,7 @@ * QTI Secure Execution Environment Communicator (QSEECOM) driver * * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #define pr_fmt(fmt) "QSEECOM: %s: " fmt, __func__ @@ -375,7 +375,7 @@ struct qseecom_client_handle { struct qseecom_listener_handle { u32 id; - bool unregister_pending; + bool register_pending; bool release_called; }; @@ -1525,6 +1525,11 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data, struct qseecom_registered_listener_list *new_entry; struct qseecom_registered_listener_list *ptr_svc; + if (data->listener.register_pending) { + pr_err("Already a listner registration is in process on this FD\n"); + return -EINVAL; + } + ret = copy_from_user(&rcvd_lstnr, argp, sizeof(rcvd_lstnr)); if (ret) { pr_err("copy_from_user failed\n"); @@ -1534,6 +1539,13 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data, rcvd_lstnr.sb_size)) return -EFAULT; + ptr_svc = __qseecom_find_svc(data->listener.id); + if (ptr_svc) { + pr_err("Already a listener registered on this data: lid=%d\n", + data->listener.id); + return -EINVAL; + } + ptr_svc = __qseecom_find_svc(rcvd_lstnr.listener_id); if (ptr_svc) { if (!ptr_svc->unregister_pending) { @@ -1577,13 +1589,16 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data, new_entry->svc.listener_id = rcvd_lstnr.listener_id; new_entry->sb_length = rcvd_lstnr.sb_size; new_entry->user_virt_sb_base = rcvd_lstnr.virt_sb_base; + data->listener.register_pending = true; if (__qseecom_set_sb_memory(new_entry, data, &rcvd_lstnr)) { pr_err("qseecom_set_sb_memory failed for listener %d, size %d\n", rcvd_lstnr.listener_id, rcvd_lstnr.sb_size); __qseecom_free_tzbuf(&new_entry->sglistinfo_shm); kzfree(new_entry); + data->listener.register_pending = false; return -ENOMEM; } + data->listener.register_pending = false; init_waitqueue_head(&new_entry->rcv_req_wq); init_waitqueue_head(&new_entry->listener_block_app_wq); @@ -3153,6 +3168,30 @@ static int qseecom_prepare_unload_app(struct qseecom_dev_handle *data) pr_debug("prepare to unload app(%d)(%s), pending %d\n", data->client.app_id, data->client.app_name, data->client.unload_pending); + + /* For keymaster we are not going to unload so no need to add it in + * unload app pending list as soon as we identify release ion buffer + * and return . + */ + if (!memcmp(data->client.app_name, "keymaste", strlen("keymaste"))) { + if (data->client.dmabuf) { + /* Each client will get same KM TA loaded handle but + * will allocate separate shared buffer during + * loading of TA, as client can't unload KM TA so we + * will only free out shared buffer and return early + * to avoid any ion buffer leak. + */ + qseecom_vaddr_unmap(data->client.sb_virt, + data->client.sgt, data->client.attach, + data->client.dmabuf); + MAKE_NULL(data->client.sgt, + data->client.attach, data->client.dmabuf); + } + __qseecom_free_tzbuf(&data->sglistinfo_shm); + data->released = true; + return 0; + } + if (data->client.unload_pending) return 0; entry = kzalloc(sizeof(*entry), GFP_KERNEL); diff --git a/drivers/misc/ti-st/st_core.c b/drivers/misc/ti-st/st_core.c index eda8d407be2878776bea8b6d57fb8c461f416724..e5fbd61f69c8e8007ccb33ff763f54146068faae 100644 --- a/drivers/misc/ti-st/st_core.c +++ b/drivers/misc/ti-st/st_core.c @@ -28,6 +28,7 @@ #include #include +#include extern void st_kim_recv(void *, const unsigned char *, long); void st_int_recv(void *, const unsigned char *, long); @@ -436,7 +437,7 @@ static void st_int_enqueue(struct st_data_s *st_gdata, struct sk_buff *skb) case ST_LL_AWAKE_TO_ASLEEP: pr_err("ST LL is illegal state(%ld)," "purging received skb.", st_ll_getstate(st_gdata)); - kfree_skb(skb); + dev_kfree_skb_irq(skb); break; case ST_LL_ASLEEP: skb_queue_tail(&st_gdata->tx_waitq, skb); @@ -445,7 +446,7 @@ static void st_int_enqueue(struct st_data_s *st_gdata, struct sk_buff *skb) default: pr_err("ST LL is illegal state(%ld)," "purging received skb.", st_ll_getstate(st_gdata)); - kfree_skb(skb); + dev_kfree_skb_irq(skb); break; } @@ -499,7 +500,7 @@ void st_tx_wakeup(struct st_data_s *st_data) spin_unlock_irqrestore(&st_data->lock, flags); break; } - kfree_skb(skb); + dev_kfree_skb_irq(skb); spin_unlock_irqrestore(&st_data->lock, flags); } /* if wake-up is set in another context- restart sending */ diff --git a/drivers/misc/vmw_vmci/vmci_host.c b/drivers/misc/vmw_vmci/vmci_host.c index 83e0c95d20a47e4cfc7ad792882ceb66df481a7e..5acbf384ffa6495d9b7f3c8d63800df101067038 100644 --- a/drivers/misc/vmw_vmci/vmci_host.c +++ b/drivers/misc/vmw_vmci/vmci_host.c @@ -169,10 +169,16 @@ static int vmci_host_close(struct inode *inode, struct file *filp) static __poll_t vmci_host_poll(struct file *filp, poll_table *wait) { struct vmci_host_dev *vmci_host_dev = filp->private_data; - struct vmci_ctx *context = vmci_host_dev->context; + struct vmci_ctx *context; __poll_t mask = 0; if (vmci_host_dev->ct_type == VMCIOBJ_CONTEXT) { + /* + * Read context only if ct_type == VMCIOBJ_CONTEXT to make + * sure that context is initialized + */ + context = vmci_host_dev->context; + /* Check for VMCI calls to this VM context. */ if (wait) poll_wait(filp, &context->host_context.wait_queue, diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c index 97d724c898703b384c418105d658b19ddd5b5d72..9db6532cbb1faec0e83145999b90b85ae28c152d 100644 --- a/drivers/mmc/core/block.c +++ b/drivers/mmc/core/block.c @@ -258,6 +258,7 @@ static ssize_t power_ro_lock_store(struct device *dev, goto out_put; } req_to_mmc_queue_req(req)->drv_op = MMC_DRV_OP_BOOT_WP; + req_to_mmc_queue_req(req)->drv_op_result = -EIO; blk_execute_rq(mq->queue, NULL, req, 0); ret = req_to_mmc_queue_req(req)->drv_op_result; blk_put_request(req); @@ -706,6 +707,7 @@ static int mmc_blk_ioctl_cmd(struct mmc_blk_data *md, idatas[0] = idata; req_to_mmc_queue_req(req)->drv_op = rpmb ? MMC_DRV_OP_IOCTL_RPMB : MMC_DRV_OP_IOCTL; + req_to_mmc_queue_req(req)->drv_op_result = -EIO; req_to_mmc_queue_req(req)->drv_op_data = idatas; req_to_mmc_queue_req(req)->ioc_count = 1; blk_execute_rq(mq->queue, NULL, req, 0); @@ -775,6 +777,7 @@ static int mmc_blk_ioctl_multi_cmd(struct mmc_blk_data *md, } req_to_mmc_queue_req(req)->drv_op = rpmb ? MMC_DRV_OP_IOCTL_RPMB : MMC_DRV_OP_IOCTL; + req_to_mmc_queue_req(req)->drv_op_result = -EIO; req_to_mmc_queue_req(req)->drv_op_data = idata; req_to_mmc_queue_req(req)->ioc_count = num_of_cmds; blk_execute_rq(mq->queue, NULL, req, 0); @@ -2035,16 +2038,17 @@ static void mmc_blk_mq_poll_completion(struct mmc_queue *mq, mmc_blk_urgent_bkops(mq, mqrq); } -static void mmc_blk_mq_dec_in_flight(struct mmc_queue *mq, struct request *req) +static void mmc_blk_mq_dec_in_flight(struct mmc_queue *mq, + struct request_queue *q, + enum mmc_issue_type issue_type) { - struct request_queue *q = req->q; struct mmc_host *host = mq->card->host; unsigned long flags; bool put_card; spin_lock_irqsave(q->queue_lock, flags); - mq->in_flight[mmc_issue_type(mq, req)] -= 1; + mq->in_flight[issue_type] -= 1; atomic_dec(&host->active_reqs); put_card = (mmc_tot_in_flight(mq) == 0); @@ -2057,9 +2061,11 @@ static void mmc_blk_mq_dec_in_flight(struct mmc_queue *mq, struct request *req) static void mmc_blk_mq_post_req(struct mmc_queue *mq, struct request *req) { + enum mmc_issue_type issue_type = mmc_issue_type(mq, req); struct mmc_queue_req *mqrq = req_to_mmc_queue_req(req); struct mmc_request *mrq = &mqrq->brq.mrq; struct mmc_host *host = mq->card->host; + struct request_queue *q = req->q; mmc_post_req(host, mrq, 0); @@ -2072,7 +2078,7 @@ static void mmc_blk_mq_post_req(struct mmc_queue *mq, struct request *req) else blk_mq_complete_request(req); - mmc_blk_mq_dec_in_flight(mq, req); + mmc_blk_mq_dec_in_flight(mq, q, issue_type); } void mmc_blk_mq_recovery(struct mmc_queue *mq) @@ -2828,6 +2834,7 @@ static int mmc_dbg_card_status_get(void *data, u64 *val) if (IS_ERR(req)) return PTR_ERR(req); req_to_mmc_queue_req(req)->drv_op = MMC_DRV_OP_GET_CARD_STATUS; + req_to_mmc_queue_req(req)->drv_op_result = -EIO; blk_execute_rq(mq->queue, NULL, req, 0); ret = req_to_mmc_queue_req(req)->drv_op_result; if (ret >= 0) { @@ -2866,6 +2873,7 @@ static int mmc_ext_csd_open(struct inode *inode, struct file *filp) goto out_free; } req_to_mmc_queue_req(req)->drv_op = MMC_DRV_OP_GET_EXT_CSD; + req_to_mmc_queue_req(req)->drv_op_result = -EIO; req_to_mmc_queue_req(req)->drv_op_data = &ext_csd; blk_execute_rq(mq->queue, NULL, req, 0); err = req_to_mmc_queue_req(req)->drv_op_result; diff --git a/drivers/mmc/core/quirks.h b/drivers/mmc/core/quirks.h index b54480bbea639dd8385cc03e44f801c9941116a6..4efcfea49090e2f3ce4fa3b9406570ade6506468 100644 --- a/drivers/mmc/core/quirks.h +++ b/drivers/mmc/core/quirks.h @@ -104,6 +104,20 @@ static const struct mmc_fixup mmc_blk_fixups[] = { MMC_FIXUP("VZL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc, MMC_QUIRK_SEC_ERASE_TRIM_BROKEN), + /* + * Kingston EMMC04G-M627 advertises TRIM but it does not seems to + * support being used to offload WRITE_ZEROES. + */ + MMC_FIXUP("M62704", CID_MANFID_KINGSTON, 0x0100, add_quirk_mmc, + MMC_QUIRK_TRIM_BROKEN), + + /* + * Micron MTFC4GACAJCN-1M advertises TRIM but it does not seems to + * support being used to offload WRITE_ZEROES. + */ + MMC_FIXUP("Q2J54A", CID_MANFID_MICRON, 0x014e, add_quirk_mmc, + MMC_QUIRK_TRIM_BROKEN), + /* * On Some Kingston eMMCs, performing trim can result in * unrecoverable data conrruption occasionally due to a firmware bug. diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index 13720051ffca0e4494843156ea28df23d5ebd476..1783f3805eecc023a502e3369e52c5cfa5bede2a 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -1044,7 +1044,11 @@ static int mmc_sdio_resume(struct mmc_host *host) mmc_claim_host(host); mmc_log_string(host, "Enter\n"); - /* Restore power if needed */ + /* + * Restore power and reinitialize the card when needed. Note that a + * removable card is checked from a detect work later on in the resume + * process. + */ if (!mmc_card_keep_power(host)) { mmc_power_up(host, host->card->ocr); /* @@ -1058,13 +1062,14 @@ static int mmc_sdio_resume(struct mmc_host *host) pm_runtime_set_active(&host->card->dev); pm_runtime_enable(&host->card->dev); } - } - - /* No need to reinitialize powered-resumed nonremovable cards */ - if (mmc_card_is_removable(host) || !mmc_card_keep_power(host)) { - err = mmc_sdio_reinit_card(host, mmc_card_keep_power(host)); - } else if (mmc_card_keep_power(host) && mmc_card_wake_sdio_irq(host)) { - /* We may have switched to 1-bit mode during suspend */ + err = mmc_sdio_reinit_card(host, 0); + } else if (mmc_card_wake_sdio_irq(host)) { + /* + * We may have switched to 1-bit mode during suspend, + * need to hold retuning, because tuning only supprt + * 4-bit mode or 8 bit mode. + */ + mmc_retune_hold_now(host); err = sdio_enable_4bit_bus(host->card); if (err > 0) { if (host->caps & MMC_CAP_8_BIT_DATA) @@ -1073,6 +1078,7 @@ static int mmc_sdio_resume(struct mmc_host *host) mmc_set_bus_width(host, MMC_BUS_WIDTH_4); err = 0; } + mmc_retune_release(host); } if (err) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 23f4f9b8046361cede6a0a18319a7f93bd812ebc..7d6c423e17eef9dbad0e746e75050c1091ab81f7 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -433,11 +433,12 @@ config MMC_WBSD If unsure, say N. config MMC_AU1X - tristate "Alchemy AU1XX0 MMC Card Interface support" + bool "Alchemy AU1XX0 MMC Card Interface support" depends on MIPS_ALCHEMY + depends on MMC=y help This selects the AMD Alchemy(R) Multimedia card interface. - If you have a Alchemy platform with a MMC slot, say Y or M here. + If you have a Alchemy platform with a MMC slot, say Y here. If unsure, say N. diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c index d40bab3d9f4af22c579c5f44226b50bc510a8c0d..fb435a8d372132d7de958153d03d3b7bba00708f 100644 --- a/drivers/mmc/host/atmel-mci.c +++ b/drivers/mmc/host/atmel-mci.c @@ -1857,7 +1857,6 @@ static void atmci_tasklet_func(unsigned long priv) atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); state = STATE_WAITING_NOTBUSY; } else if (host->mrq->stop) { - atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); atmci_send_stop_cmd(host, data); state = STATE_SENDING_STOP; } else { @@ -1890,8 +1889,6 @@ static void atmci_tasklet_func(unsigned long priv) * command to send. */ if (host->mrq->stop) { - atmci_writel(host, ATMCI_IER, - ATMCI_CMDRDY); atmci_send_stop_cmd(host, data); state = STATE_SENDING_STOP; } else { diff --git a/drivers/mmc/host/bcm2835.c b/drivers/mmc/host/bcm2835.c index 5301302fb53108641c16a5c7691f96efaa1b28f1..2b3ff4be7ae07b405d79980e8a6e84a63b036ed3 100644 --- a/drivers/mmc/host/bcm2835.c +++ b/drivers/mmc/host/bcm2835.c @@ -1417,9 +1417,8 @@ static int bcm2835_probe(struct platform_device *pdev) host->max_clk = clk_get_rate(clk); host->irq = platform_get_irq(pdev, 0); - if (host->irq <= 0) { - dev_err(dev, "get IRQ failed\n"); - ret = -EINVAL; + if (host->irq < 0) { + ret = host->irq; goto err; } diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c index 864338e308e2b04ef026af950461959b20e37a9d..b8fb518c6db016d57fee6c60ff4f16813ac27866 100644 --- a/drivers/mmc/host/jz4740_mmc.c +++ b/drivers/mmc/host/jz4740_mmc.c @@ -1060,7 +1060,6 @@ static int jz4740_mmc_probe(struct platform_device* pdev) host->irq = platform_get_irq(pdev, 0); if (host->irq < 0) { ret = host->irq; - dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); goto err_free_host; } diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index dba98c2886f26c590eac2d556a4d24f2fcc990b9..12441faa28086cd689a0fec38a2d2cce71da96b8 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -159,7 +158,6 @@ struct meson_host { struct mmc_host *mmc; struct mmc_command *cmd; - spinlock_t lock; void __iomem *regs; struct clk *core_clk; struct clk *mmc_clk; @@ -933,7 +931,6 @@ static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ - cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */ meson_mmc_set_response_bits(cmd, &cmd_cfg); @@ -1042,8 +1039,6 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) if (WARN_ON(!host) || WARN_ON(!host->cmd)) return IRQ_NONE; - spin_lock(&host->lock); - cmd = host->cmd; data = cmd->data; cmd->error = 0; @@ -1071,11 +1066,8 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { if (data && !cmd->error) data->bytes_xfered = data->blksz * data->blocks; - if (meson_mmc_bounce_buf_read(data) || - meson_mmc_get_next_command(cmd)) - ret = IRQ_WAKE_THREAD; - else - ret = IRQ_HANDLED; + + return IRQ_WAKE_THREAD; } out: @@ -1090,10 +1082,6 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) writel(start, host->regs + SD_EMMC_START); } - if (ret == IRQ_HANDLED) - meson_mmc_request_done(host->mmc, cmd->mrq); - - spin_unlock(&host->lock); return ret; } @@ -1246,8 +1234,6 @@ static int meson_mmc_probe(struct platform_device *pdev) host->dev = &pdev->dev; dev_set_drvdata(&pdev->dev, host); - spin_lock_init(&host->lock); - /* Get regulators and the supported OCR mask */ host->vqmmc_enabled = false; ret = mmc_regulator_get_supply(mmc); @@ -1285,7 +1271,6 @@ static int meson_mmc_probe(struct platform_device *pdev) host->irq = platform_get_irq(pdev, 0); if (host->irq <= 0) { - dev_err(&pdev->dev, "failed to get interrupt resource.\n"); ret = -EINVAL; goto free_host; } diff --git a/drivers/mmc/host/moxart-mmc.c b/drivers/mmc/host/moxart-mmc.c index 52307dce08ba840869f1c6779010923ee93a67be..0c392b41a858a602d6a6129c6709d24e3279487b 100644 --- a/drivers/mmc/host/moxart-mmc.c +++ b/drivers/mmc/host/moxart-mmc.c @@ -339,13 +339,7 @@ static void moxart_transfer_pio(struct moxart_host *host) return; } for (len = 0; len < remain && len < host->fifo_width;) { - /* SCR data must be read in big endian. */ - if (data->mrq->cmd->opcode == SD_APP_SEND_SCR) - *sgp = ioread32be(host->base + - REG_DATA_WINDOW); - else - *sgp = ioread32(host->base + - REG_DATA_WINDOW); + *sgp = ioread32(host->base + REG_DATA_WINDOW); sgp++; len += 4; } diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 967e47770af6790481386c136e8f52adc279615b..d42c5da1a22607148541df9e53f001bcf7c643bc 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -1912,7 +1912,7 @@ static int msdc_drv_probe(struct platform_device *pdev) host->irq = platform_get_irq(pdev, 0); if (host->irq < 0) { - ret = -EINVAL; + ret = host->irq; goto host_free; } diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c index e22bbff89c8d24c62d075327de4b65935a345162..fff9980a3ef28fa801569fd1f8f48d803bda9f90 100644 --- a/drivers/mmc/host/mvsdio.c +++ b/drivers/mmc/host/mvsdio.c @@ -699,17 +699,15 @@ static int mvsd_probe(struct platform_device *pdev) struct mmc_host *mmc = NULL; struct mvsd_host *host = NULL; const struct mbus_dram_target_info *dram; - struct resource *r; int ret, irq; if (!np) { dev_err(&pdev->dev, "no DT node\n"); return -ENODEV; } - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_irq(pdev, 0); - if (!r || irq < 0) - return -ENXIO; + if (irq < 0) + return irq; mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev); if (!mmc) { @@ -761,7 +759,7 @@ static int mvsd_probe(struct platform_device *pdev) spin_lock_init(&host->lock); - host->base = devm_ioremap_resource(&pdev->dev, r); + host->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(host->base)) { ret = PTR_ERR(host->base); goto out; diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c index 6215feb976e32485e8e2c787c198becc7ba03985..a0e8ac9124455db36d6dfbb097d87ed5da0cf571 100644 --- a/drivers/mmc/host/mxcmmc.c +++ b/drivers/mmc/host/mxcmmc.c @@ -1017,10 +1017,8 @@ static int mxcmci_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq); + if (irq < 0) return irq; - } mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); if (!mmc) diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c index b2873a2432b69fd374daa049729348c5af042ed6..345b35483cee75546b1f96ce3eb9f6a876e9b5e7 100644 --- a/drivers/mmc/host/omap.c +++ b/drivers/mmc/host/omap.c @@ -1347,7 +1347,7 @@ static int mmc_omap_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); if (irq < 0) - return -ENXIO; + return irq; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); host->virt_base = devm_ioremap_resource(&pdev->dev, res); diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 0135693afa158420587976796dde940f0872fd65..881d1de4a5635dfb65ee1e2e51105e31a9c9dcd0 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -2006,9 +2006,11 @@ static int omap_hsmmc_probe(struct platform_device *pdev) } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - irq = platform_get_irq(pdev, 0); - if (res == NULL || irq < 0) + if (!res) return -ENXIO; + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(base)) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index eabfcb5bbafff5710b71c291ffa2a2a68c4c07c6..a2c44cc8e2e7cd73e6ed592f7f117aa6d4cc4f45 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -155,6 +155,66 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, return ret == 0 ? best_freq : clk_get_rate(priv->clk); } +static void renesas_sdhi_clk_start(struct tmio_mmc_host *host) +{ + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + /* HW engineers overrode docs: no sleep needed on R-Car2+ */ + if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) + usleep_range(10000, 11000); +} + +static void renesas_sdhi_clk_stop(struct tmio_mmc_host *host) +{ + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + /* HW engineers overrode docs: no sleep needed on R-Car2+ */ + if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) + usleep_range(10000, 11000); +} + +static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, + unsigned int new_clock) +{ + u32 clk = 0, clock; + + if (new_clock == 0) { + renesas_sdhi_clk_stop(host); + return; + } + /* + * Both HS400 and HS200/SD104 set 200MHz, but some devices need to + * set 400MHz to distinguish the CPG settings in HS400. + */ + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && + host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 && + new_clock == 200000000) + new_clock = 400000000; + + clock = renesas_sdhi_clk_update(host, new_clock) / 512; + + for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) + clock <<= 1; + + /* 1/1 clock is option */ + if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { + if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) + clk |= 0xff; + else + clk &= ~0xff; + } + + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); + if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) + usleep_range(10000, 11000); + + renesas_sdhi_clk_start(host); +} + static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) { struct renesas_sdhi *priv = host_to_priv(host); @@ -621,8 +681,8 @@ int renesas_sdhi_probe(struct platform_device *pdev, host->write16_hook = renesas_sdhi_write16_hook; host->clk_enable = renesas_sdhi_clk_enable; - host->clk_update = renesas_sdhi_clk_update; host->clk_disable = renesas_sdhi_clk_disable; + host->set_clock = renesas_sdhi_set_clock; host->multi_io_quirk = renesas_sdhi_multi_io_quirk; host->dma_ops = dma_ops; diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c index f77493604312941d8b7985c756d7a94f93af1bc6..ca2239ea6d96da43302c1e5a0c45cd9909903e01 100644 --- a/drivers/mmc/host/s3cmci.c +++ b/drivers/mmc/host/s3cmci.c @@ -1661,7 +1661,6 @@ static int s3cmci_probe(struct platform_device *pdev) host->irq = platform_get_irq(pdev, 0); if (host->irq <= 0) { - dev_err(&pdev->dev, "failed to get interrupt resource.\n"); ret = -EINVAL; goto probe_iounmap; } diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c index 6cc187ce3a329bf0fd8f817de79505ba944cab05..069b9a07aca5dc806ffe9fda05b4afce5c8dcc03 100644 --- a/drivers/mmc/host/sdhci-acpi.c +++ b/drivers/mmc/host/sdhci-acpi.c @@ -721,7 +721,7 @@ static int sdhci_acpi_probe(struct platform_device *pdev) host->ops = &sdhci_acpi_ops_dflt; host->irq = platform_get_irq(pdev, 0); if (host->irq < 0) { - err = -EINVAL; + err = host->irq; goto err_free; } diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 5bd590fcc12772bd293e9105a7433a2dd4f536be..8e711d8412f4e222d2308001222a4a8a2294354b 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -5657,8 +5657,6 @@ static int sdhci_msm_probe(struct platform_device *pdev) /* Setup PWRCTL irq */ msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); if (msm_host->pwr_irq < 0) { - dev_err(&pdev->dev, "Failed to get pwr_irq by name (%d)\n", - msm_host->pwr_irq); goto vreg_deinit; } ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c index 4409a98f19bd1ab09f56d6472b26c4d5505fc3ff..88f6aae2aae6ee37239698a3a1ffe4a81f0d824d 100644 --- a/drivers/mmc/host/sdhci-pltfm.c +++ b/drivers/mmc/host/sdhci-pltfm.c @@ -132,7 +132,6 @@ struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev, irq = platform_get_irq(pdev, 0); if (irq < 0) { - dev_err(&pdev->dev, "failed to get IRQ number\n"); ret = irq; goto err; } diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c index 9ef89d00970e1abf2c0cf27cfe0aa9e23bd0bdf6..936d88a33a675f1df53e084cf4d29363952e87b0 100644 --- a/drivers/mmc/host/sdhci-s3c.c +++ b/drivers/mmc/host/sdhci-s3c.c @@ -493,10 +493,8 @@ static int sdhci_s3c_probe(struct platform_device *pdev) } irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(dev, "no irq specified\n"); + if (irq < 0) return irq; - } host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); if (IS_ERR(host)) { diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index b5760a71b30a471c0d61165e5837cf916a13c997..536ec4c0a7a76d22b40b085498441d236d469492 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -465,7 +465,7 @@ static void sdhci_read_block_pio(struct sdhci_host *host) { unsigned long flags; size_t blksize, len, chunk; - u32 uninitialized_var(scratch); + u32 scratch; u8 *buf; DBG("PIO reading\n"); diff --git a/drivers/mmc/host/sdhci_f_sdh30.c b/drivers/mmc/host/sdhci_f_sdh30.c index ca9e05440da1d10fdebd14cf163790f24ac9491a..ee8160d6015eac110561bd48dd1e63868e933704 100644 --- a/drivers/mmc/host/sdhci_f_sdh30.c +++ b/drivers/mmc/host/sdhci_f_sdh30.c @@ -122,10 +122,8 @@ static int sdhci_f_sdh30_probe(struct platform_device *pdev) u32 reg = 0; irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(dev, "%s: no irq specified\n", __func__); + if (irq < 0) return irq; - } host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv)); if (IS_ERR(host)) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index 757eb175611fbe820177772cd6f01baec659ad04..bc3f8a1df10cc03f309e1ae19de5d6000b552d0d 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -1308,8 +1308,8 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, return ret; host->irq = platform_get_irq(pdev, 0); - if (host->irq <= 0) { - ret = -EINVAL; + if (host->irq < 0) { + ret = host->irq; goto error_disable_mmc; } diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c index 43a2ea5cff24f335c481b7ad8c6f5abff1712d36..b031a776c12e0850619f125225a39e9627948e72 100644 --- a/drivers/mmc/host/tmio_mmc.c +++ b/drivers/mmc/host/tmio_mmc.c @@ -13,6 +13,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -23,6 +24,52 @@ #include "tmio_mmc.h" +static void tmio_mmc_clk_start(struct tmio_mmc_host *host) +{ + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + usleep_range(10000, 11000); + sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100); + usleep_range(10000, 11000); +} + +static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) +{ + sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000); + usleep_range(10000, 11000); + + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + usleep_range(10000, 11000); +} + +static void tmio_mmc_set_clock(struct tmio_mmc_host *host, + unsigned int new_clock) +{ + u32 clk = 0, clock; + + if (new_clock == 0) { + tmio_mmc_clk_stop(host); + return; + } + + clock = host->mmc->f_min; + + for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) + clock <<= 1; + + host->pdata->set_clk_div(host->pdev, (clk >> 22) & 1); + + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); + usleep_range(10000, 11000); + + tmio_mmc_clk_start(host); +} + #ifdef CONFIG_PM_SLEEP static int tmio_mmc_suspend(struct device *dev) { @@ -100,6 +147,7 @@ static int tmio_mmc_probe(struct platform_device *pdev) /* SD control register space size is 0x200, 0x400 for bus_shift=1 */ host->bus_shift = resource_size(res) >> 10; + host->set_clock = tmio_mmc_set_clock; host->mmc->f_max = pdata->hclk; host->mmc->f_min = pdata->hclk / 512; diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h index 7c40a7e1fea1c48757efb3639f7d5cecc7fe60e1..358aa258cb159500bb41a5889718b869229fb3a9 100644 --- a/drivers/mmc/host/tmio_mmc.h +++ b/drivers/mmc/host/tmio_mmc.h @@ -133,7 +133,6 @@ struct tmio_mmc_host { /* Callbacks for clock / power control */ void (*set_pwr)(struct platform_device *host, int state); - void (*set_clk_div)(struct platform_device *host, int state); /* pio related stuff */ struct scatterlist *sg_ptr; @@ -170,10 +169,9 @@ struct tmio_mmc_host { /* Mandatory callback */ int (*clk_enable)(struct tmio_mmc_host *host); + void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock); /* Optional callbacks */ - unsigned int (*clk_update)(struct tmio_mmc_host *host, - unsigned int new_clock); void (*clk_disable)(struct tmio_mmc_host *host); int (*multi_io_quirk)(struct mmc_card *card, unsigned int direction, int blk_size); diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c index 33c9ca8f14a97373afc9aec2b35ccd346aca06b7..f819757e125e0d075536798015d3b29c16bb77e3 100644 --- a/drivers/mmc/host/tmio_mmc_core.c +++ b/drivers/mmc/host/tmio_mmc_core.c @@ -161,83 +161,6 @@ static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) } } -static void tmio_mmc_clk_start(struct tmio_mmc_host *host) -{ - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - - /* HW engineers overrode docs: no sleep needed on R-Car2+ */ - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) - usleep_range(10000, 11000); - - if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) { - sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100); - usleep_range(10000, 11000); - } -} - -static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) -{ - if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) { - sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000); - usleep_range(10000, 11000); - } - - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - - /* HW engineers overrode docs: no sleep needed on R-Car2+ */ - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) - usleep_range(10000, 11000); -} - -static void tmio_mmc_set_clock(struct tmio_mmc_host *host, - unsigned int new_clock) -{ - u32 clk = 0, clock; - - if (new_clock == 0) { - tmio_mmc_clk_stop(host); - return; - } - /* - * Both HS400 and HS200/SD104 set 200MHz, but some devices need to - * set 400MHz to distinguish the CPG settings in HS400. - */ - if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && - host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 && - new_clock == 200000000) - new_clock = 400000000; - - if (host->clk_update) - clock = host->clk_update(host, new_clock) / 512; - else - clock = host->mmc->f_min; - - for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) - clock <<= 1; - - /* 1/1 clock is option */ - if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && - ((clk >> 22) & 0x1)) { - if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) - clk |= 0xff; - else - clk &= ~0xff; - } - - if (host->set_clk_div) - host->set_clk_div(host->pdev, (clk >> 22) & 1); - - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) - usleep_range(10000, 11000); - - tmio_mmc_clk_start(host); -} - static void tmio_mmc_reset(struct tmio_mmc_host *host) { /* FIXME - should we set stop clock reg here */ @@ -1051,15 +974,15 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) switch (ios->power_mode) { case MMC_POWER_OFF: tmio_mmc_power_off(host); - tmio_mmc_clk_stop(host); + host->set_clock(host, 0); break; case MMC_POWER_UP: tmio_mmc_power_on(host, ios->vdd); - tmio_mmc_set_clock(host, ios->clock); + host->set_clock(host, ios->clock); tmio_mmc_set_bus_width(host, ios->bus_width); break; case MMC_POWER_ON: - tmio_mmc_set_clock(host, ios->clock); + host->set_clock(host, ios->clock); tmio_mmc_set_bus_width(host, ios->bus_width); break; } @@ -1245,7 +1168,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host) int ret; /* - * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from + * Check the sanity of mmc->f_min to prevent host->set_clock() from * looping forever... */ if (mmc->f_min == 0) @@ -1255,7 +1178,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host) _host->write16_hook = NULL; _host->set_pwr = pdata->set_pwr; - _host->set_clk_div = pdata->set_clk_div; ret = tmio_mmc_init_ocr(_host); if (ret < 0) @@ -1318,7 +1240,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host) if (pdata->flags & TMIO_MMC_SDIO_IRQ) _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL; - tmio_mmc_clk_stop(_host); + _host->set_clock(_host, 0); tmio_mmc_reset(_host); _host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK); @@ -1402,7 +1324,7 @@ int tmio_mmc_host_runtime_suspend(struct device *dev) tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL); if (host->clk_cache) - tmio_mmc_clk_stop(host); + host->set_clock(host, 0); tmio_mmc_clk_disable(host); @@ -1423,7 +1345,7 @@ int tmio_mmc_host_runtime_resume(struct device *dev) tmio_mmc_clk_enable(host); if (host->clk_cache) - tmio_mmc_set_clock(host, host->clk_cache); + host->set_clock(host, host->clk_cache); if (host->native_hotplug) tmio_mmc_enable_mmc_irqs(host, diff --git a/drivers/mmc/host/usdhi6rol0.c b/drivers/mmc/host/usdhi6rol0.c index b88728b686e8a5f8b5afed8972aee039f41c8bbf..e436f7e7a3ee0e9f82748edd4e3d34b0cbabb1b3 100644 --- a/drivers/mmc/host/usdhi6rol0.c +++ b/drivers/mmc/host/usdhi6rol0.c @@ -1749,8 +1749,10 @@ static int usdhi6_probe(struct platform_device *pdev) irq_cd = platform_get_irq_byname(pdev, "card detect"); irq_sd = platform_get_irq_byname(pdev, "data"); irq_sdio = platform_get_irq_byname(pdev, "SDIO"); - if (irq_sd < 0 || irq_sdio < 0) - return -ENODEV; + if (irq_sd < 0) + return irq_sd; + if (irq_sdio < 0) + return irq_sdio; mmc = mmc_alloc_host(sizeof(struct usdhi6_host), dev); if (!mmc) diff --git a/drivers/mmc/host/vub300.c b/drivers/mmc/host/vub300.c index e74ab79c99cd9176021461d211fbb2e273d4a0cd..1d08318bd707a662765c45c7d649c5c61f3e4734 100644 --- a/drivers/mmc/host/vub300.c +++ b/drivers/mmc/host/vub300.c @@ -1718,6 +1718,9 @@ static void construct_request_response(struct vub300_mmc_host *vub300, int bytes = 3 & less_cmd; int words = less_cmd >> 2; u8 *r = vub300->resp.response.command_response; + + if (!resp_len) + return; if (bytes == 3) { cmd->resp[words] = (r[1 + (words << 2)] << 24) | (r[2 + (words << 2)] << 16) @@ -2318,6 +2321,7 @@ static int vub300_probe(struct usb_interface *interface, vub300->read_only = (0x0010 & vub300->system_port_status.port_flags) ? 1 : 0; } else { + retval = -EINVAL; goto error5; } usb_set_intfdata(interface, vub300); diff --git a/drivers/mmc/host/wbsd.c b/drivers/mmc/host/wbsd.c index 9b15431d961ce5d7644724214e37686cb56f1370..1df3ea9e5d6f1be08fcb8a0d4b97e39b76b7a317 100644 --- a/drivers/mmc/host/wbsd.c +++ b/drivers/mmc/host/wbsd.c @@ -1713,8 +1713,6 @@ static int wbsd_init(struct device *dev, int base, int irq, int dma, wbsd_release_resources(host); wbsd_free_mmc(dev); - - mmc_free_host(mmc); return ret; } diff --git a/drivers/mtd/mtdblock.c b/drivers/mtd/mtdblock.c index a5b1933c0490946d3c328f13074865af10718f19..17b3495fe3563027ae34d8ab61ad582b4a45de62 100644 --- a/drivers/mtd/mtdblock.c +++ b/drivers/mtd/mtdblock.c @@ -164,7 +164,7 @@ static int do_cached_write (struct mtdblk_dev *mtdblk, unsigned long pos, mtdblk->cache_state = STATE_EMPTY; ret = mtd_read(mtd, sect_start, sect_size, &retlen, mtdblk->cache_data); - if (ret) + if (ret && !mtd_is_bitflip(ret)) return ret; if (retlen != sect_size) return -EIO; @@ -199,8 +199,12 @@ static int do_cached_read (struct mtdblk_dev *mtdblk, unsigned long pos, pr_debug("mtdblock: read on \"%s\" at 0x%lx, size 0x%x\n", mtd->name, pos, len); - if (!sect_size) - return mtd_read(mtd, pos, len, &retlen, buf); + if (!sect_size) { + ret = mtd_read(mtd, pos, len, &retlen, buf); + if (ret && !mtd_is_bitflip(ret)) + return ret; + return 0; + } while (len > 0) { unsigned long sect_start = (pos/sect_size)*sect_size; @@ -220,7 +224,7 @@ static int do_cached_read (struct mtdblk_dev *mtdblk, unsigned long pos, memcpy (buf, mtdblk->cache_data + offset, size); } else { ret = mtd_read(mtd, pos, size, &retlen, buf); - if (ret) + if (ret && !mtd_is_bitflip(ret)) return ret; if (retlen != size) return -EIO; diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 27bafb8fc35af192d9832fd44be6e04463940295..0e14892ff92669924152de5145b2f10fb94506ed 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -152,6 +152,7 @@ struct brcmnand_controller { unsigned int max_page_size; const unsigned int *page_sizes; unsigned int max_oob; + u32 ecc_level_shift; u32 features; /* for low-power standby/resume only */ @@ -441,6 +442,34 @@ enum { INTFC_CTLR_READY = BIT(31), }; +/*********************************************************************** + * NAND ACC CONTROL bitfield + * + * Some bits have remained constant throughout hardware revision, while + * others have shifted around. + ***********************************************************************/ + +/* Constant for all versions (where supported) */ +enum { + /* See BRCMNAND_HAS_CACHE_MODE */ + ACC_CONTROL_CACHE_MODE = BIT(22), + + /* See BRCMNAND_HAS_PREFETCH */ + ACC_CONTROL_PREFETCH = BIT(23), + + ACC_CONTROL_PAGE_HIT = BIT(24), + ACC_CONTROL_WR_PREEMPT = BIT(25), + ACC_CONTROL_PARTIAL_PAGE = BIT(26), + ACC_CONTROL_RD_ERASED = BIT(27), + ACC_CONTROL_FAST_PGM_RDIN = BIT(28), + ACC_CONTROL_WR_ECC = BIT(30), + ACC_CONTROL_RD_ECC = BIT(31), +}; + +#define ACC_CONTROL_ECC_SHIFT 16 +/* Only for v7.2 */ +#define ACC_CONTROL_ECC_EXT_SHIFT 13 + static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) { return brcmnand_readl(ctrl->nand_base + offs); @@ -544,6 +573,12 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl) else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) ctrl->features |= BRCMNAND_HAS_WP; + /* v7.2 has different ecc level shift in the acc register */ + if (ctrl->nand_version == 0x0702) + ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT; + else + ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT; + return 0; } @@ -697,30 +732,6 @@ static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) return 0; } -/*********************************************************************** - * NAND ACC CONTROL bitfield - * - * Some bits have remained constant throughout hardware revision, while - * others have shifted around. - ***********************************************************************/ - -/* Constant for all versions (where supported) */ -enum { - /* See BRCMNAND_HAS_CACHE_MODE */ - ACC_CONTROL_CACHE_MODE = BIT(22), - - /* See BRCMNAND_HAS_PREFETCH */ - ACC_CONTROL_PREFETCH = BIT(23), - - ACC_CONTROL_PAGE_HIT = BIT(24), - ACC_CONTROL_WR_PREEMPT = BIT(25), - ACC_CONTROL_PARTIAL_PAGE = BIT(26), - ACC_CONTROL_RD_ERASED = BIT(27), - ACC_CONTROL_FAST_PGM_RDIN = BIT(28), - ACC_CONTROL_WR_ECC = BIT(30), - ACC_CONTROL_RD_ECC = BIT(31), -}; - static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) { if (ctrl->nand_version >= 0x0702) @@ -731,18 +742,15 @@ static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) return GENMASK(5, 0); } -#define NAND_ACC_CONTROL_ECC_SHIFT 16 -#define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13 - static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) { u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; - mask <<= NAND_ACC_CONTROL_ECC_SHIFT; + mask <<= ACC_CONTROL_ECC_SHIFT; /* v7.2 includes additional ECC levels */ - if (ctrl->nand_version >= 0x0702) - mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT; + if (ctrl->nand_version == 0x0702) + mask |= 0x7 << ACC_CONTROL_ECC_EXT_SHIFT; return mask; } @@ -756,8 +764,8 @@ static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en) if (en) { acc_control |= ecc_flags; /* enable RD/WR ECC */ - acc_control |= host->hwcfg.ecc_level - << NAND_ACC_CONTROL_ECC_SHIFT; + acc_control &= ~brcmnand_ecc_level_mask(ctrl); + acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift; } else { acc_control &= ~ecc_flags; /* disable RD/WR ECC */ acc_control &= ~brcmnand_ecc_level_mask(ctrl); @@ -836,6 +844,14 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, cpu_relax(); } while (time_after(limit, jiffies)); + /* + * do a final check after time out in case the CPU was busy and the driver + * did not get enough time to perform the polling to avoid false alarms + */ + val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); + if ((val & mask) == expected_val) + return 0; + dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", expected_val, val & mask); @@ -1213,19 +1229,33 @@ static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, const u8 *oob, int sas, int sector_1k) { int tbytes = sas << sector_1k; - int j; + int j, k = 0; + u32 last = 0xffffffff; + u8 *plast = (u8 *)&last; /* Adjust OOB values for 1K sector size */ if (sector_1k && (i & 0x01)) tbytes = max(0, tbytes - (int)ctrl->max_oob); tbytes = min_t(int, tbytes, ctrl->max_oob); - for (j = 0; j < tbytes; j += 4) + /* + * tbytes may not be multiple of words. Make sure we don't read out of + * the boundary and stop at last word. + */ + for (j = 0; (j + 3) < tbytes; j += 4) oob_reg_write(ctrl, j, (oob[j + 0] << 24) | (oob[j + 1] << 16) | (oob[j + 2] << 8) | (oob[j + 3] << 0)); + + /* handle the remaing bytes */ + while (j < tbytes) + plast[k++] = oob[j++]; + + if (tbytes & 0x3) + oob_reg_write(ctrl, (tbytes & ~0x3), (__force u32)cpu_to_be32(last)); + return tbytes; } @@ -1271,7 +1301,17 @@ static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd) dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); - BUG_ON(ctrl->cmd_pending != 0); + /* + * If we came here through _panic_write and there is a pending + * command, try to wait for it. If it times out, rather than + * hitting BUG_ON, just return so we don't crash while crashing. + */ + if (oops_in_progress) { + if (ctrl->cmd_pending && + bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0)) + return; + } else + BUG_ON(ctrl->cmd_pending != 0); ctrl->cmd_pending = cmd; ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); @@ -2071,9 +2111,10 @@ static int brcmnand_set_cfg(struct brcmnand_host *host, tmp = nand_readreg(ctrl, acc_control_offs); tmp &= ~brcmnand_ecc_level_mask(ctrl); - tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; + tmp |= cfg->ecc_level << ctrl->ecc_level_shift; tmp &= ~brcmnand_spare_area_mask(ctrl); tmp |= cfg->spare_area_size; + nand_writereg(ctrl, acc_control_offs, tmp); brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); diff --git a/drivers/mtd/nand/raw/nand_ecc.c b/drivers/mtd/nand/raw/nand_ecc.c index 8e132edbc5ce96c7f1e1e90658db450a830145e8..d1066f635e4c8c904ac8f22e1acbed6bf661da81 100644 --- a/drivers/mtd/nand/raw/nand_ecc.c +++ b/drivers/mtd/nand/raw/nand_ecc.c @@ -144,7 +144,7 @@ void __nand_calculate_ecc(const unsigned char *buf, unsigned int eccsize, /* rp0..rp15..rp17 are the various accumulated parities (per byte) */ uint32_t rp0, rp1, rp2, rp3, rp4, rp5, rp6, rp7; uint32_t rp8, rp9, rp10, rp11, rp12, rp13, rp14, rp15, rp16; - uint32_t uninitialized_var(rp17); /* to make compiler happy */ + uint32_t rp17; uint32_t par; /* the cumulative parity for all data */ uint32_t tmppar; /* the cumulative parity for this iteration; for rp12, rp14 and rp16 at the end of the diff --git a/drivers/mtd/nand/raw/omap_elm.c b/drivers/mtd/nand/raw/omap_elm.c index 6736777a4156794593454fffda69277047ee6bc6..02d1740383120c2e21d6c5058cf1a83a9515d695 100644 --- a/drivers/mtd/nand/raw/omap_elm.c +++ b/drivers/mtd/nand/raw/omap_elm.c @@ -184,17 +184,17 @@ static void elm_load_syndrome(struct elm_info *info, switch (info->bch_type) { case BCH8_ECC: /* syndrome fragment 0 = ecc[9-12B] */ - val = cpu_to_be32(*(u32 *) &ecc[9]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[9]); elm_write_reg(info, offset, val); /* syndrome fragment 1 = ecc[5-8B] */ offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[5]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[5]); elm_write_reg(info, offset, val); /* syndrome fragment 2 = ecc[1-4B] */ offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[1]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[1]); elm_write_reg(info, offset, val); /* syndrome fragment 3 = ecc[0B] */ @@ -204,35 +204,35 @@ static void elm_load_syndrome(struct elm_info *info, break; case BCH4_ECC: /* syndrome fragment 0 = ecc[20-52b] bits */ - val = (cpu_to_be32(*(u32 *) &ecc[3]) >> 4) | + val = ((__force u32)cpu_to_be32(*(u32 *)&ecc[3]) >> 4) | ((ecc[2] & 0xf) << 28); elm_write_reg(info, offset, val); /* syndrome fragment 1 = ecc[0-20b] bits */ offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[0]) >> 12; + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[0]) >> 12; elm_write_reg(info, offset, val); break; case BCH16_ECC: - val = cpu_to_be32(*(u32 *) &ecc[22]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[22]); elm_write_reg(info, offset, val); offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[18]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[18]); elm_write_reg(info, offset, val); offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[14]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[14]); elm_write_reg(info, offset, val); offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[10]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[10]); elm_write_reg(info, offset, val); offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[6]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[6]); elm_write_reg(info, offset, val); offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[2]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[2]); elm_write_reg(info, offset, val); offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[0]) >> 16; + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[0]) >> 16; elm_write_reg(info, offset, val); break; default: diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index c64b408f080a9ca637e2fcde27b8fa4b10839ff8..783cdc8728cb59bd5871288f2d1e19ed0f4c0e1d 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2987,7 +2987,7 @@ static int qcom_nandc_probe(struct platform_device *pdev) err_aon_clk: clk_disable_unprepare(nandc->core_clk); err_core_clk: - dma_unmap_resource(dev, res->start, resource_size(res), + dma_unmap_resource(dev, nandc->base_dma, resource_size(res), DMA_BIDIRECTIONAL, 0); return ret; } diff --git a/drivers/mtd/nand/raw/s3c2410.c b/drivers/mtd/nand/raw/s3c2410.c index cf045813c160a2c776e95da850a2cca5fbadeffa..83d3e3cb77dedbb676824f3d065e57794ca53500 100644 --- a/drivers/mtd/nand/raw/s3c2410.c +++ b/drivers/mtd/nand/raw/s3c2410.c @@ -304,7 +304,7 @@ static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; int tacls, twrph0, twrph1; unsigned long clkrate = clk_get_rate(info->clk); - unsigned long uninitialized_var(set), cfg, uninitialized_var(mask); + unsigned long set, cfg, mask; unsigned long flags; /* calculate the timing information for the controller */ diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index 88075e420f907c01712f5d5a016837cc858ca016..fe7bfcdf7c69c9b22a15ee446a61d0c5e4668895 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -1670,7 +1670,7 @@ static int sunxi_nand_ooblayout_free(struct mtd_info *mtd, int section, if (section < ecc->steps) oobregion->length = 4; else - oobregion->offset = mtd->oobsize - oobregion->offset; + oobregion->length = mtd->oobsize - oobregion->offset; return 0; } diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index 9c4381d6847b34d225514a990ce1ff6cc5a82b39..fabca2c3632169e2b095db3520244941c4205773 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -12,7 +12,7 @@ #define SPINAND_MFR_MICRON 0x2c -#define MICRON_STATUS_ECC_MASK GENMASK(7, 4) +#define MICRON_STATUS_ECC_MASK GENMASK(6, 4) #define MICRON_STATUS_ECC_NO_BITFLIPS (0 << 4) #define MICRON_STATUS_ECC_1TO3_BITFLIPS (1 << 4) #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index a92f531ad23a3e09c2cd5b09642bd37641c51e62..d5c6b91fd11393d29ce02e621472b9d481e08ff4 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -80,9 +80,6 @@ struct cqspi_st { dma_addr_t mmap_phys_base; int current_cs; - int current_page_size; - int current_erase_size; - int current_addr_width; unsigned long master_ref_clk_hz; bool is_decoded_cs; u32 fifo_depth; @@ -734,32 +731,6 @@ static void cqspi_chipselect(struct spi_nor *nor) writel(reg, reg_base + CQSPI_REG_CONFIG); } -static void cqspi_configure_cs_and_sizes(struct spi_nor *nor) -{ - struct cqspi_flash_pdata *f_pdata = nor->priv; - struct cqspi_st *cqspi = f_pdata->cqspi; - void __iomem *iobase = cqspi->iobase; - unsigned int reg; - - /* configure page size and block size. */ - reg = readl(iobase + CQSPI_REG_SIZE); - reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); - reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); - reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; - reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB); - reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB); - reg |= (nor->addr_width - 1); - writel(reg, iobase + CQSPI_REG_SIZE); - - /* configure the chip select */ - cqspi_chipselect(nor); - - /* Store the new configuration of the controller */ - cqspi->current_page_size = nor->page_size; - cqspi->current_erase_size = nor->mtd.erasesize; - cqspi->current_addr_width = nor->addr_width; -} - static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, const unsigned int ns_val) { @@ -865,18 +836,13 @@ static void cqspi_configure(struct spi_nor *nor) int switch_cs = (cqspi->current_cs != f_pdata->cs); int switch_ck = (cqspi->sclk != sclk); - if ((cqspi->current_page_size != nor->page_size) || - (cqspi->current_erase_size != nor->mtd.erasesize) || - (cqspi->current_addr_width != nor->addr_width)) - switch_cs = 1; - if (switch_cs || switch_ck) cqspi_controller_enable(cqspi, 0); /* Switch chip select. */ if (switch_cs) { cqspi->current_cs = f_pdata->cs; - cqspi_configure_cs_and_sizes(nor); + cqspi_chipselect(nor); } /* Setup baudrate divisor and delays */ @@ -1196,7 +1162,7 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) cqspi_controller_enable(cqspi, 1); } -static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) +static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) { dma_cap_mask_t mask; @@ -1205,10 +1171,16 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) cqspi->rx_chan = dma_request_chan_by_mask(&mask); if (IS_ERR(cqspi->rx_chan)) { - dev_err(&cqspi->pdev->dev, "No Rx DMA available\n"); + int ret = PTR_ERR(cqspi->rx_chan); + + if (ret != -EPROBE_DEFER) + dev_err(&cqspi->pdev->dev, "No Rx DMA available\n"); cqspi->rx_chan = NULL; + return ret; } init_completion(&cqspi->rx_dma_complete); + + return 0; } static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) @@ -1289,8 +1261,11 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) dev_dbg(nor->dev, "using direct mode for %s\n", mtd->name); - if (!cqspi->rx_chan) - cqspi_request_mmap_dma(cqspi); + if (!cqspi->rx_chan) { + ret = cqspi_request_mmap_dma(cqspi); + if (ret == -EPROBE_DEFER) + goto err; + } } } @@ -1437,17 +1412,30 @@ static int cqspi_remove(struct platform_device *pdev) static int cqspi_suspend(struct device *dev) { struct cqspi_st *cqspi = dev_get_drvdata(dev); + struct spi_master *master = dev_get_drvdata(dev); + int ret; + ret = spi_master_suspend(master); cqspi_controller_enable(cqspi, 0); - return 0; + + clk_disable_unprepare(cqspi->clk); + + return ret; } static int cqspi_resume(struct device *dev) { struct cqspi_st *cqspi = dev_get_drvdata(dev); + struct spi_master *master = dev_get_drvdata(dev); - cqspi_controller_enable(cqspi, 1); - return 0; + clk_prepare_enable(cqspi->clk); + cqspi_wait_idle(cqspi); + cqspi_controller_init(cqspi); + + cqspi->current_cs = -1; + cqspi->sclk = 0; + + return spi_master_resume(master); } static const struct dev_pm_ops cqspi__dev_pm_ops = { diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 1ea3a4977c618f325d16388b623aa5864fc887b0..3e7e5b51eafd00abd7f51fbd019b256b094ec262 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -480,6 +480,7 @@ static int uif_init(struct ubi_device *ubi) err = ubi_add_volume(ubi, ubi->volumes[i]); if (err) { ubi_err(ubi, "cannot add volume %d", i); + ubi->volumes[i] = NULL; goto out_volumes; } } @@ -673,6 +674,21 @@ static int io_init(struct ubi_device *ubi, int max_beb_per1024) ubi->vid_hdr_aloffset; } + /* + * Memory allocation for VID header is ubi->vid_hdr_alsize + * which is described in comments in io.c. + * Make sure VID header shift + UBI_VID_HDR_SIZE not exceeds + * ubi->vid_hdr_alsize, so that all vid header operations + * won't access memory out of bounds. + */ + if ((ubi->vid_hdr_shift + UBI_VID_HDR_SIZE) > ubi->vid_hdr_alsize) { + ubi_err(ubi, "Invalid VID header offset %d, VID header shift(%d)" + " + VID header size(%zu) > VID header aligned size(%d).", + ubi->vid_hdr_offset, ubi->vid_hdr_shift, + UBI_VID_HDR_SIZE, ubi->vid_hdr_alsize); + return -EINVAL; + } + /* Similar for the data offset */ ubi->leb_start = ubi->vid_hdr_offset + UBI_VID_HDR_SIZE; ubi->leb_start = ALIGN(ubi->leb_start, ubi->min_io_size); @@ -862,6 +878,13 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, return -EINVAL; } + /* UBI cannot work on flashes with zero erasesize. */ + if (!mtd->erasesize) { + pr_err("ubi: refuse attaching mtd%d - zero erasesize flash is not supported\n", + mtd->index); + return -EINVAL; + } + if (ubi_num == UBI_DEV_NUM_AUTO) { /* Search for an empty slot in the @ubi_devices array */ for (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++) diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c index b98481b69314d94d3a1f205ba804491d3235638c..fa6ff75459c6e3093cb3d871a81e530568309dc8 100644 --- a/drivers/mtd/ubi/eba.c +++ b/drivers/mtd/ubi/eba.c @@ -612,7 +612,7 @@ int ubi_eba_read_leb(struct ubi_device *ubi, struct ubi_volume *vol, int lnum, int err, pnum, scrub = 0, vol_id = vol->vol_id; struct ubi_vid_io_buf *vidb; struct ubi_vid_hdr *vid_hdr; - uint32_t uninitialized_var(crc); + uint32_t crc; err = leb_read_lock(ubi, vol_id, lnum); if (err) @@ -960,7 +960,7 @@ static int try_write_vid_and_data(struct ubi_volume *vol, int lnum, int offset, int len) { struct ubi_device *ubi = vol->ubi; - int pnum, opnum, err, vol_id = vol->vol_id; + int pnum, opnum, err, err2, vol_id = vol->vol_id; pnum = ubi_wl_get_peb(ubi); if (pnum < 0) { @@ -995,10 +995,19 @@ static int try_write_vid_and_data(struct ubi_volume *vol, int lnum, out_put: up_read(&ubi->fm_eba_sem); - if (err && pnum >= 0) - err = ubi_wl_put_peb(ubi, vol_id, lnum, pnum, 1); - else if (!err && opnum >= 0) - err = ubi_wl_put_peb(ubi, vol_id, lnum, opnum, 0); + if (err && pnum >= 0) { + err2 = ubi_wl_put_peb(ubi, vol_id, lnum, pnum, 1); + if (err2) { + ubi_warn(ubi, "failed to return physical eraseblock %d, error %d", + pnum, err2); + } + } else if (!err && opnum >= 0) { + err2 = ubi_wl_put_peb(ubi, vol_id, lnum, opnum, 0); + if (err2) { + ubi_warn(ubi, "failed to return physical eraseblock %d, error %d", + opnum, err2); + } + } return err; } diff --git a/drivers/mtd/ubi/vmt.c b/drivers/mtd/ubi/vmt.c index 9f6ffd340a3efe16daa259e2d2cab23464a8ef8a..c5dec58846ce8ee7ecb8a535d4fbf9a555c383bc 100644 --- a/drivers/mtd/ubi/vmt.c +++ b/drivers/mtd/ubi/vmt.c @@ -477,7 +477,7 @@ int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs) for (i = 0; i < -pebs; i++) { err = ubi_eba_unmap_leb(ubi, vol, reserved_pebs + i); if (err) - goto out_acc; + goto out_free; } spin_lock(&ubi->volumes_lock); ubi->rsvd_pebs += pebs; @@ -525,8 +525,10 @@ int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs) ubi->avail_pebs += pebs; spin_unlock(&ubi->volumes_lock); } + return err; + out_free: - kfree(new_eba_tbl); + ubi_eba_destroy_table(new_eba_tbl); return err; } @@ -593,6 +595,7 @@ int ubi_add_volume(struct ubi_device *ubi, struct ubi_volume *vol) if (err) { ubi_err(ubi, "cannot add character device for volume %d, error %d", vol_id, err); + vol_release(&vol->dev); return err; } @@ -603,15 +606,14 @@ int ubi_add_volume(struct ubi_device *ubi, struct ubi_volume *vol) vol->dev.groups = volume_dev_groups; dev_set_name(&vol->dev, "%s_%d", ubi->ubi_name, vol->vol_id); err = device_register(&vol->dev); - if (err) - goto out_cdev; + if (err) { + cdev_del(&vol->cdev); + put_device(&vol->dev); + return err; + } self_check_volumes(ubi); return err; - -out_cdev: - cdev_del(&vol->cdev); - return err; } /** diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index ac336164f6253560659bda444ac65ce365283457..83c460f7a8837d00ee668799044aa9bed7755128 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -568,6 +568,7 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk, * @vol_id: the volume ID that last used this PEB * @lnum: the last used logical eraseblock number for the PEB * @torture: if the physical eraseblock has to be tortured + * @nested: denotes whether the work_sem is already held * * This function returns zero in case of success and a %-ENOMEM in case of * failure. @@ -865,8 +866,11 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk, err = do_sync_erase(ubi, e1, vol_id, lnum, 0); if (err) { - if (e2) + if (e2) { + spin_lock(&ubi->wl_lock); wl_entry_destroy(ubi, e2); + spin_unlock(&ubi->wl_lock); + } goto out_ro; } @@ -948,11 +952,11 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk, spin_lock(&ubi->wl_lock); ubi->move_from = ubi->move_to = NULL; ubi->move_to_put = ubi->wl_scheduled = 0; + wl_entry_destroy(ubi, e1); + wl_entry_destroy(ubi, e2); spin_unlock(&ubi->wl_lock); ubi_free_vid_buf(vidb); - wl_entry_destroy(ubi, e1); - wl_entry_destroy(ubi, e2); out_ro: ubi_ro_mode(ubi); @@ -1043,8 +1047,6 @@ static int ensure_wear_leveling(struct ubi_device *ubi, int nested) * __erase_worker - physical eraseblock erase worker function. * @ubi: UBI device description object * @wl_wrk: the work object - * @shutdown: non-zero if the worker has to free memory and exit - * because the WL sub-system is shutting down * * This function erases a physical eraseblock and perform torture testing if * needed. It also takes care about marking the physical eraseblock bad if @@ -1094,16 +1096,20 @@ static int __erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk) int err1; /* Re-schedule the LEB for erasure */ - err1 = schedule_erase(ubi, e, vol_id, lnum, 0, false); + err1 = schedule_erase(ubi, e, vol_id, lnum, 0, true); if (err1) { + spin_lock(&ubi->wl_lock); wl_entry_destroy(ubi, e); + spin_unlock(&ubi->wl_lock); err = err1; goto out_ro; } return err; } + spin_lock(&ubi->wl_lock); wl_entry_destroy(ubi, e); + spin_unlock(&ubi->wl_lock); if (err != -EIO) /* * If this is not %-EIO, we have no idea what to do. Scheduling @@ -1219,6 +1225,18 @@ int ubi_wl_put_peb(struct ubi_device *ubi, int vol_id, int lnum, retry: spin_lock(&ubi->wl_lock); e = ubi->lookuptbl[pnum]; + if (!e) { + /* + * This wl entry has been removed for some errors by other + * process (eg. wear leveling worker), corresponding process + * (except __erase_worker, which cannot concurrent with + * ubi_wl_put_peb) will set ubi ro_mode at the same time, + * just ignore this wl entry. + */ + spin_unlock(&ubi->wl_lock); + up_read(&ubi->fm_protect); + return 0; + } if (e == ubi->move_from) { /* * User is putting the physical eraseblock which was selected to diff --git a/drivers/net/arcnet/arcnet.c b/drivers/net/arcnet/arcnet.c index 553776cc1d29ddceb9f4855d93e5d97366dd5a8f..2b112d3d854099176f3e9a1f15e621e9b81dca3d 100644 --- a/drivers/net/arcnet/arcnet.c +++ b/drivers/net/arcnet/arcnet.c @@ -434,7 +434,7 @@ static void arcnet_reply_tasklet(unsigned long data) ret = sock_queue_err_skb(sk, ackskb); if (ret) - kfree_skb(ackskb); + dev_kfree_skb_irq(ackskb); local_irq_enable(); }; diff --git a/drivers/net/bonding/bond_alb.c b/drivers/net/bonding/bond_alb.c index 3fc439d924451288150a8bc1754e438109bf5332..e03f4883858ac866fbb155b8700920f177cf6f8e 100644 --- a/drivers/net/bonding/bond_alb.c +++ b/drivers/net/bonding/bond_alb.c @@ -671,10 +671,10 @@ static struct slave *rlb_arp_xmit(struct sk_buff *skb, struct bonding *bond) return NULL; arp = (struct arp_pkt *)skb_network_header(skb); - /* Don't modify or load balance ARPs that do not originate locally - * (e.g.,arrive via a bridge). + /* Don't modify or load balance ARPs that do not originate + * from the bond itself or a VLAN directly above the bond. */ - if (!bond_slave_has_mac_rx(bond, arp->mac_src)) + if (!bond_slave_has_mac_rcu(bond, arp->mac_src)) return NULL; if (arp->op_code == htons(ARPOP_REPLY)) { diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index 4e4adacb5c2c17a785c834765026dcc347dc8d6b..79b36f1c50aec27187db65ad1cc31feb74d4e04b 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c @@ -1128,6 +1128,11 @@ static void bond_setup_by_slave(struct net_device *bond_dev, memcpy(bond_dev->broadcast, slave_dev->broadcast, slave_dev->addr_len); + + if (slave_dev->flags & IFF_POINTOPOINT) { + bond_dev->flags &= ~(IFF_BROADCAST | IFF_MULTICAST); + bond_dev->flags |= (IFF_POINTOPOINT | IFF_NOARP); + } } /* On bonding slaves other than the currently active slave, suppress @@ -4390,7 +4395,9 @@ void bond_setup(struct net_device *bond_dev) bond_dev->hw_features = BOND_VLAN_FEATURES | NETIF_F_HW_VLAN_CTAG_RX | - NETIF_F_HW_VLAN_CTAG_FILTER; + NETIF_F_HW_VLAN_CTAG_FILTER | + NETIF_F_HW_VLAN_STAG_RX | + NETIF_F_HW_VLAN_STAG_FILTER; bond_dev->hw_features |= NETIF_F_GSO_ENCAP_ALL | NETIF_F_GSO_UDP_L4; bond_dev->features |= bond_dev->hw_features; diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile index 44922bf29b6a0653ea1eda6ad96c30b3a645fbaa..93e11f1fee5c60865e6ad8cfd343a46fb46fc466 100644 --- a/drivers/net/can/Makefile +++ b/drivers/net/can/Makefile @@ -7,12 +7,7 @@ obj-$(CONFIG_CAN_VCAN) += vcan.o obj-$(CONFIG_CAN_VXCAN) += vxcan.o obj-$(CONFIG_CAN_SLCAN) += slcan.o -obj-$(CONFIG_CAN_DEV) += can-dev.o -can-dev-y += dev.o -can-dev-y += rx-offload.o - -can-dev-$(CONFIG_CAN_LEDS) += led.o - +obj-y += dev/ obj-y += rcar/ obj-y += spi/ obj-y += usb/ diff --git a/drivers/net/can/dev/Makefile b/drivers/net/can/dev/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..cba92e6bcf6f58a68006e5115ae74a5402e9e691 --- /dev/null +++ b/drivers/net/can/dev/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_CAN_DEV) += can-dev.o +can-dev-y += dev.o +can-dev-y += rx-offload.o + +can-dev-$(CONFIG_CAN_LEDS) += led.o diff --git a/drivers/net/can/dev.c b/drivers/net/can/dev/dev.c similarity index 99% rename from drivers/net/can/dev.c rename to drivers/net/can/dev/dev.c index 1bd181b33c24f349234c3b0268637a37787e4c26..d9d3e4a0d0d9c764f73411ced03839a0284aebbb 100644 --- a/drivers/net/can/dev.c +++ b/drivers/net/can/dev/dev.c @@ -563,7 +563,8 @@ static void can_restart(struct net_device *dev) struct can_frame *cf; int err; - BUG_ON(netif_carrier_ok(dev)); + if (netif_carrier_ok(dev)) + netdev_err(dev, "Attempt to restart for bus-off recovery, but carrier is OK?\n"); /* * No synchronization needed because the device is bus-off and @@ -589,11 +590,12 @@ static void can_restart(struct net_device *dev) priv->can_stats.restarts++; /* Now restart the device */ - err = priv->do_set_mode(dev, CAN_MODE_START); - netif_carrier_on(dev); - if (err) + err = priv->do_set_mode(dev, CAN_MODE_START); + if (err) { netdev_err(dev, "Error %d during restart", err); + netif_carrier_off(dev); + } } static void can_restart_work(struct work_struct *work) diff --git a/drivers/net/can/rx-offload.c b/drivers/net/can/dev/rx-offload.c similarity index 100% rename from drivers/net/can/rx-offload.c rename to drivers/net/can/dev/rx-offload.c diff --git a/drivers/net/can/janz-ican3.c b/drivers/net/can/janz-ican3.c index 02042cb09bd29f2d680623d21be2a823f111b587..0e939a4cd9998c7a29de4323e234c109bae87310 100644 --- a/drivers/net/can/janz-ican3.c +++ b/drivers/net/can/janz-ican3.c @@ -1455,7 +1455,7 @@ static int ican3_napi(struct napi_struct *napi, int budget) /* process all communication messages */ while (true) { - struct ican3_msg uninitialized_var(msg); + struct ican3_msg msg; ret = ican3_recv_msg(mod, &msg); if (ret) break; diff --git a/drivers/net/can/usb/esd_usb2.c b/drivers/net/can/usb/esd_usb2.c index ffdee5aeb8a937ea080c55c4778536fff79679ba..d46599871919d9a1251e11267a9e899b9947faa1 100644 --- a/drivers/net/can/usb/esd_usb2.c +++ b/drivers/net/can/usb/esd_usb2.c @@ -290,7 +290,6 @@ static void esd_usb2_rx_event(struct esd_usb2_net_priv *priv, cf->data[2] |= CAN_ERR_PROT_STUFF; break; default: - cf->data[3] = ecc & SJA1000_ECC_SEG; break; } @@ -298,6 +297,9 @@ static void esd_usb2_rx_event(struct esd_usb2_net_priv *priv, if (!(ecc & SJA1000_ECC_DIR)) cf->data[2] |= CAN_ERR_PROT_TX; + /* Bit stream position in CAN frame as the error was detected */ + cf->data[3] = ecc & SJA1000_ECC_SEG; + if (priv->can.state == CAN_STATE_ERROR_WARNING || priv->can.state == CAN_STATE_ERROR_PASSIVE) { cf->data[1] = (txerr > rxerr) ? diff --git a/drivers/net/can/usb/gs_usb.c b/drivers/net/can/usb/gs_usb.c index 62ca4964a863aba6c334d314d6057d0a85752e40..fd80af775ec750246ab7ee52ddf347c80c6dfd6f 100644 --- a/drivers/net/can/usb/gs_usb.c +++ b/drivers/net/can/usb/gs_usb.c @@ -389,6 +389,9 @@ static void gs_usb_receive_bulk_callback(struct urb *urb) } if (hf->flags & GS_CAN_FLAG_OVERFLOW) { + stats->rx_over_errors++; + stats->rx_errors++; + skb = alloc_can_err_skb(netdev, &cf); if (!skb) goto resubmit_urb; @@ -396,8 +399,6 @@ static void gs_usb_receive_bulk_callback(struct urb *urb) cf->can_id |= CAN_ERR_CRTL; cf->can_dlc = CAN_ERR_DLC; cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; - stats->rx_over_errors++; - stats->rx_errors++; netif_rx(skb); } @@ -740,6 +741,8 @@ static int gs_can_close(struct net_device *netdev) usb_kill_anchored_urbs(&dev->tx_submitted); atomic_set(&dev->active_tx_urbs, 0); + dev->can.state = CAN_STATE_STOPPED; + /* reset the device */ rc = gs_cmd_reset(dev); if (rc < 0) diff --git a/drivers/net/dsa/b53/b53_mmap.c b/drivers/net/dsa/b53/b53_mmap.c index c628d0980c0b1ffda5cb1f1dfb94a0797f533ef6..1d52cb3e46d523791a9f8ff7b119bb932d26d3af 100644 --- a/drivers/net/dsa/b53/b53_mmap.c +++ b/drivers/net/dsa/b53/b53_mmap.c @@ -215,6 +215,18 @@ static int b53_mmap_write64(struct b53_device *dev, u8 page, u8 reg, return 0; } +static int b53_mmap_phy_read16(struct b53_device *dev, int addr, int reg, + u16 *value) +{ + return -EIO; +} + +static int b53_mmap_phy_write16(struct b53_device *dev, int addr, int reg, + u16 value) +{ + return -EIO; +} + static const struct b53_io_ops b53_mmap_ops = { .read8 = b53_mmap_read8, .read16 = b53_mmap_read16, @@ -226,6 +238,8 @@ static const struct b53_io_ops b53_mmap_ops = { .write32 = b53_mmap_write32, .write48 = b53_mmap_write48, .write64 = b53_mmap_write64, + .phy_read16 = b53_mmap_phy_read16, + .phy_write16 = b53_mmap_phy_write16, }; static int b53_mmap_probe(struct platform_device *pdev) diff --git a/drivers/net/dsa/lan9303-core.c b/drivers/net/dsa/lan9303-core.c index f976b3d64593a33f691269bcebca62b14fb731ef..80ac5efb0a7a91ce26c752e8a49b693e5f8409f9 100644 --- a/drivers/net/dsa/lan9303-core.c +++ b/drivers/net/dsa/lan9303-core.c @@ -1191,8 +1191,6 @@ static int lan9303_port_fdb_add(struct dsa_switch *ds, int port, struct lan9303 *chip = ds->priv; dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); - if (vid) - return -EOPNOTSUPP; return lan9303_alr_add_port(chip, addr, port, false); } @@ -1204,8 +1202,6 @@ static int lan9303_port_fdb_del(struct dsa_switch *ds, int port, struct lan9303 *chip = ds->priv; dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); - if (vid) - return -EOPNOTSUPP; lan9303_alr_del_port(chip, addr, port); return 0; diff --git a/drivers/net/dsa/lan9303_mdio.c b/drivers/net/dsa/lan9303_mdio.c index cc9c2ea1c4fe0209e1423ae35c960a1712fe9099..d2c463ae00411260c07c05aacc403b2f946e460d 100644 --- a/drivers/net/dsa/lan9303_mdio.c +++ b/drivers/net/dsa/lan9303_mdio.c @@ -41,7 +41,7 @@ static int lan9303_mdio_write(void *ctx, uint32_t reg, uint32_t val) struct lan9303_mdio *sw_dev = (struct lan9303_mdio *)ctx; reg <<= 2; /* reg num to offset */ - mutex_lock(&sw_dev->device->bus->mdio_lock); + mutex_lock_nested(&sw_dev->device->bus->mdio_lock, MDIO_MUTEX_NESTED); lan9303_mdio_real_write(sw_dev->device, reg, val & 0xffff); lan9303_mdio_real_write(sw_dev->device, reg + 2, (val >> 16) & 0xffff); mutex_unlock(&sw_dev->device->bus->mdio_lock); @@ -59,7 +59,7 @@ static int lan9303_mdio_read(void *ctx, uint32_t reg, uint32_t *val) struct lan9303_mdio *sw_dev = (struct lan9303_mdio *)ctx; reg <<= 2; /* reg num to offset */ - mutex_lock(&sw_dev->device->bus->mdio_lock); + mutex_lock_nested(&sw_dev->device->bus->mdio_lock, MDIO_MUTEX_NESTED); *val = lan9303_mdio_real_read(sw_dev->device, reg); *val |= (lan9303_mdio_real_read(sw_dev->device, reg + 2) << 16); mutex_unlock(&sw_dev->device->bus->mdio_lock); diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index be064bcfd70a679d7f6943981dd7208480800fa2..792073a768ac0484f338289aa3a8ee08f9874ce8 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2237,9 +2237,14 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) * If this is the upstream port for this switch, enable * forwarding of unknown unicasts and multicasts. */ - reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | - MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | + reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | MV88E6XXX_PORT_CTL0_STATE_FORWARDING; + /* Forward any IPv4 IGMP or IPv6 MLD frames received + * by a USER port to the CPU port to allow snooping. + */ + if (dsa_is_user_port(ds, port)) + reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; + err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); if (err) return err; @@ -3596,6 +3601,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops = { .stats_get_stats = mv88e6320_stats_get_stats, .set_cpu_port = mv88e6095_g1_set_cpu_port, .set_egress_port = mv88e6095_g1_set_egress_port, + .watchdog_ops = &mv88e6390_watchdog_ops, .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, .pot_clear = mv88e6xxx_g2_pot_clear, .reset = mv88e6352_g1_reset, @@ -3638,6 +3644,8 @@ static const struct mv88e6xxx_ops mv88e6321_ops = { .stats_get_stats = mv88e6320_stats_get_stats, .set_cpu_port = mv88e6095_g1_set_cpu_port, .set_egress_port = mv88e6095_g1_set_egress_port, + .watchdog_ops = &mv88e6390_watchdog_ops, + .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, .reset = mv88e6352_g1_reset, .vtu_getnext = mv88e6185_g1_vtu_getnext, .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, @@ -4832,7 +4840,7 @@ static int mv88e6xxx_probe(struct mdio_device *mdiodev) goto out; } if (chip->reset) - usleep_range(1000, 2000); + usleep_range(10000, 20000); err = mv88e6xxx_detect(chip); if (err) diff --git a/drivers/net/ethernet/3com/3c589_cs.c b/drivers/net/ethernet/3com/3c589_cs.c index 2b2695311bda9b6b518bf1cfea8db42b73604be0..aab26dbe76ff92c7ebe90dc2059c9584a77ea3e6 100644 --- a/drivers/net/ethernet/3com/3c589_cs.c +++ b/drivers/net/ethernet/3com/3c589_cs.c @@ -196,6 +196,7 @@ static int tc589_probe(struct pcmcia_device *link) { struct el3_private *lp; struct net_device *dev; + int ret; dev_dbg(&link->dev, "3c589_attach()\n"); @@ -219,7 +220,15 @@ static int tc589_probe(struct pcmcia_device *link) dev->ethtool_ops = &netdev_ethtool_ops; - return tc589_config(link); + ret = tc589_config(link); + if (ret) + goto err_free_netdev; + + return 0; + +err_free_netdev: + free_netdev(dev); + return ret; } static void tc589_detach(struct pcmcia_device *link) diff --git a/drivers/net/ethernet/amd/nmclan_cs.c b/drivers/net/ethernet/amd/nmclan_cs.c index 9c152d85840d79add7dc32bd1ee47579208ced25..c9d2a6f150624e93dadd28f34743df6e9260537b 100644 --- a/drivers/net/ethernet/amd/nmclan_cs.c +++ b/drivers/net/ethernet/amd/nmclan_cs.c @@ -652,7 +652,7 @@ static int nmclan_config(struct pcmcia_device *link) } else { pr_notice("mace id not found: %x %x should be 0x40 0x?9\n", sig[0], sig[1]); - return -ENODEV; + goto failed; } } diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c index 7840eb4cdb8da2b69a084aa93a93844bff27888b..d291976d8b7610347b1754f89d786ebfc50d2fc5 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c @@ -1312,7 +1312,7 @@ static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata) return pdata->phy_if.phy_impl.an_outcome(pdata); } -static void xgbe_phy_status_result(struct xgbe_prv_data *pdata) +static bool xgbe_phy_status_result(struct xgbe_prv_data *pdata) { struct ethtool_link_ksettings *lks = &pdata->phy.lks; enum xgbe_mode mode; @@ -1347,8 +1347,13 @@ static void xgbe_phy_status_result(struct xgbe_prv_data *pdata) pdata->phy.duplex = DUPLEX_FULL; - if (xgbe_set_mode(pdata, mode) && pdata->an_again) + if (!xgbe_set_mode(pdata, mode)) + return false; + + if (pdata->an_again) xgbe_phy_reconfig_aneg(pdata); + + return true; } static void xgbe_phy_status(struct xgbe_prv_data *pdata) @@ -1378,7 +1383,8 @@ static void xgbe_phy_status(struct xgbe_prv_data *pdata) return; } - xgbe_phy_status_result(pdata); + if (xgbe_phy_status_result(pdata)) + return; if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) clear_bit(XGBE_LINK_INIT, &pdata->dev_state); diff --git a/drivers/net/ethernet/atheros/alx/ethtool.c b/drivers/net/ethernet/atheros/alx/ethtool.c index 2f4eabf652e800ff9a2722a43acac174f8ddc427..51e5aa2c74b3410d9e155533a71d0f52f1223149 100644 --- a/drivers/net/ethernet/atheros/alx/ethtool.c +++ b/drivers/net/ethernet/atheros/alx/ethtool.c @@ -281,9 +281,8 @@ static void alx_get_ethtool_stats(struct net_device *netdev, spin_lock(&alx->stats_lock); alx_update_hw_stats(hw); - BUILD_BUG_ON(sizeof(hw->stats) - offsetof(struct alx_hw_stats, rx_ok) < - ALX_NUM_STATS * sizeof(u64)); - memcpy(data, &hw->stats.rx_ok, ALX_NUM_STATS * sizeof(u64)); + BUILD_BUG_ON(sizeof(hw->stats) != ALX_NUM_STATS * sizeof(u64)); + memcpy(data, &hw->stats, sizeof(hw->stats)); spin_unlock(&alx->stats_lock); } diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c index 7087b88550db5fbbbfb909aee8c5a999db5bad57..98cc2bd5adc45df893ac4156573964afb7c8a51b 100644 --- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c +++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c @@ -2002,8 +2002,11 @@ static int atl1c_tso_csum(struct atl1c_adapter *adapter, real_len = (((unsigned char *)ip_hdr(skb) - skb->data) + ntohs(ip_hdr(skb)->tot_len)); - if (real_len < skb->len) - pskb_trim(skb, real_len); + if (real_len < skb->len) { + err = pskb_trim(skb, real_len); + if (err) + return err; + } hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb)); if (unlikely(skb->len == hdr_len)) { diff --git a/drivers/net/ethernet/atheros/atl1e/atl1e_main.c b/drivers/net/ethernet/atheros/atl1e/atl1e_main.c index 3164aad29bcf879aa0841a912d6bbeaa757caad6..e4d58c7aeaf82c1c682c620cc1bd8841adcc1c9a 100644 --- a/drivers/net/ethernet/atheros/atl1e/atl1e_main.c +++ b/drivers/net/ethernet/atheros/atl1e/atl1e_main.c @@ -1651,8 +1651,11 @@ static int atl1e_tso_csum(struct atl1e_adapter *adapter, real_len = (((unsigned char *)ip_hdr(skb) - skb->data) + ntohs(ip_hdr(skb)->tot_len)); - if (real_len < skb->len) - pskb_trim(skb, real_len); + if (real_len < skb->len) { + err = pskb_trim(skb, real_len); + if (err) + return err; + } hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb)); if (unlikely(skb->len == hdr_len)) { diff --git a/drivers/net/ethernet/broadcom/bnx2.c b/drivers/net/ethernet/broadcom/bnx2.c index 9993f1162ac687a90b11c80a815150be78223105..c69700088082dd5975760abf7db97d59c34f0ab6 100644 --- a/drivers/net/ethernet/broadcom/bnx2.c +++ b/drivers/net/ethernet/broadcom/bnx2.c @@ -1461,7 +1461,7 @@ bnx2_test_and_disable_2g5(struct bnx2 *bp) static void bnx2_enable_forced_2g5(struct bnx2 *bp) { - u32 uninitialized_var(bmcr); + u32 bmcr; int err; if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) @@ -1505,7 +1505,7 @@ bnx2_enable_forced_2g5(struct bnx2 *bp) static void bnx2_disable_forced_2g5(struct bnx2 *bp) { - u32 uninitialized_var(bmcr); + u32 bmcr; int err; if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h index 46ee2c01f4c5167209c23f3e1440b82630327cea..d16b1eddbecf2108da76ca1059d3bd44bbc6bc86 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h @@ -296,7 +296,6 @@ static inline void bnx2x_dcb_config_qm(struct bnx2x *bp, enum cos_mode mode, * possible, the driver should only write the valid vnics into the internal * ram according to the appropriate port mode. */ -#define BITS_TO_BYTES(x) ((x)/8) /* CMNG constants, as derived from system spec calculations */ diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c index 91ddde4d647c666174b7fc18927a7cadea45d7d6..d21b22ed0b60ac909c0c04674209b51a7b7e4c82 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c @@ -14464,11 +14464,16 @@ static void bnx2x_io_resume(struct pci_dev *pdev) bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & DRV_MSG_SEQ_NUMBER_MASK; - if (netif_running(dev)) - bnx2x_nic_load(bp, LOAD_NORMAL); + if (netif_running(dev)) { + if (bnx2x_nic_load(bp, LOAD_NORMAL)) { + netdev_err(bp->dev, "Error during driver initialization, try unloading/reloading the driver\n"); + goto done; + } + } netif_device_attach(dev); +done: rtnl_unlock(); } diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c b/drivers/net/ethernet/broadcom/genet/bcmgenet.c index 96ef2dd46c78cac619143790ad87572c73906815..d51857731314539c1313c854a5ceedb6d17e337c 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c @@ -1825,6 +1825,14 @@ static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, __func__, p_index, ring->c_index, ring->read_ptr, dma_length_status); + if (unlikely(len > RX_BUF_LENGTH)) { + netif_err(priv, rx_status, dev, "oversized packet\n"); + dev->stats.rx_length_errors++; + dev->stats.rx_errors++; + dev_kfree_skb_any(skb); + goto next; + } + if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { netif_err(priv, rx_status, dev, "dropping fragmented packet!\n"); @@ -2972,7 +2980,7 @@ static int bcmgenet_open(struct net_device *dev) return ret; } -static void bcmgenet_netif_stop(struct net_device *dev) +static void bcmgenet_netif_stop(struct net_device *dev, bool stop_phy) { struct bcmgenet_priv *priv = netdev_priv(dev); @@ -2987,7 +2995,8 @@ static void bcmgenet_netif_stop(struct net_device *dev) /* Disable MAC transmit. TX DMA disabled must be done before this */ umac_enable_set(priv, CMD_TX_EN, false); - phy_stop(dev->phydev); + if (stop_phy) + phy_stop(dev->phydev); bcmgenet_disable_rx_napi(priv); bcmgenet_intr_disable(priv); @@ -3013,7 +3022,7 @@ static int bcmgenet_close(struct net_device *dev) netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); - bcmgenet_netif_stop(dev); + bcmgenet_netif_stop(dev, false); /* Really kill the PHY state machine and disconnect from it */ phy_disconnect(dev->phydev); @@ -3713,7 +3722,7 @@ static int bcmgenet_suspend(struct device *d) netif_device_detach(dev); - bcmgenet_netif_stop(dev); + bcmgenet_netif_stop(dev, true); if (!device_may_wakeup(d)) phy_suspend(dev->phydev); diff --git a/drivers/net/ethernet/broadcom/genet/bcmmii.c b/drivers/net/ethernet/broadcom/genet/bcmmii.c index 494601c39b847f99c8416f891de21475e425b946..9041a422dd15afebad1c4cc9d8cb8cfea21d00ff 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmmii.c +++ b/drivers/net/ethernet/broadcom/genet/bcmmii.c @@ -620,5 +620,7 @@ void bcmgenet_mii_exit(struct net_device *dev) if (of_phy_is_fixed_link(dn)) of_phy_deregister_fixed_link(dn); of_node_put(priv->phy_dn); + clk_prepare_enable(priv->clk); platform_device_unregister(priv->mii_pdev); + clk_disable_unprepare(priv->clk); } diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 2cf144bbef3ee8977f4d181d11de6ff679ca2754..f0b5c8a4d29f51d51c9d0e3a0a763daa3c0ac8ce 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c @@ -235,6 +235,7 @@ MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_MODULE_VERSION); MODULE_FIRMWARE(FIRMWARE_TG3); +MODULE_FIRMWARE(FIRMWARE_TG357766); MODULE_FIRMWARE(FIRMWARE_TG3TSO); MODULE_FIRMWARE(FIRMWARE_TG3TSO5); @@ -18216,7 +18217,8 @@ static void tg3_shutdown(struct pci_dev *pdev) if (netif_running(dev)) dev_close(dev); - tg3_power_down(tp); + if (system_state == SYSTEM_POWER_OFF) + tg3_power_down(tp); rtnl_unlock(); diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 324d81516832c14ebda0bc66482197777b2e427e..d58f5bbb879560cf3f980acd8b3536d77a067369 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -707,6 +707,10 @@ static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc) } #endif addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr)); +#ifdef CONFIG_MACB_USE_HWSTAMP + if (bp->hw_dma_cap & HW_DMA_CAP_PTP) + addr &= ~GEM_BIT(DMA_RXVALID); +#endif return addr; } diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c index 812f4b743d97e38c2b49dd95eb87608bc44c9d93..0e8aa2d803ebd41ff3b82cade2538230d7beb95a 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c @@ -3850,6 +3850,8 @@ int t4_load_phy_fw(struct adapter *adap, FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD)); ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val, 30000); + if (ret) + return ret; /* If we have version number support, then check to see that the new * firmware got loaded properly. diff --git a/drivers/net/ethernet/cortina/gemini.c b/drivers/net/ethernet/cortina/gemini.c index f8a3d1fecb0a5d4585e02aa001885e4bf9aafd9d..b7ebe5eb46f5af090b8fb57e6a549fcfa50600db 100644 --- a/drivers/net/ethernet/cortina/gemini.c +++ b/drivers/net/ethernet/cortina/gemini.c @@ -433,8 +433,8 @@ static const struct gmac_max_framelen gmac_maxlens[] = { .val = CONFIG0_MAXLEN_1536, }, { - .max_l3_len = 1542, - .val = CONFIG0_MAXLEN_1542, + .max_l3_len = 1548, + .val = CONFIG0_MAXLEN_1548, }, { .max_l3_len = 9212, @@ -1153,6 +1153,7 @@ static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb, dma_addr_t mapping; unsigned short mtu; void *buffer; + int ret; mtu = ETH_HLEN; mtu += netdev->mtu; @@ -1167,9 +1168,30 @@ static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb, word3 |= mtu; } - if (skb->ip_summed != CHECKSUM_NONE) { + if (skb->len >= ETH_FRAME_LEN) { + /* Hardware offloaded checksumming isn't working on frames + * bigger than 1514 bytes. A hypothesis about this is that the + * checksum buffer is only 1518 bytes, so when the frames get + * bigger they get truncated, or the last few bytes get + * overwritten by the FCS. + * + * Just use software checksumming and bypass on bigger frames. + */ + if (skb->ip_summed == CHECKSUM_PARTIAL) { + ret = skb_checksum_help(skb); + if (ret) + return ret; + } + word1 |= TSS_BYPASS_BIT; + } else if (skb->ip_summed == CHECKSUM_PARTIAL) { int tcp = 0; + /* We do not switch off the checksumming on non TCP/UDP + * frames: as is shown from tests, the checksumming engine + * is smart enough to see that a frame is not actually TCP + * or UDP and then just pass it through without any changes + * to the frame. + */ if (skb->protocol == htons(ETH_P_IP)) { word1 |= TSS_IP_CHKSUM_BIT; tcp = ip_hdr(skb)->protocol == IPPROTO_TCP; @@ -1997,15 +2019,6 @@ static int gmac_change_mtu(struct net_device *netdev, int new_mtu) return 0; } -static netdev_features_t gmac_fix_features(struct net_device *netdev, - netdev_features_t features) -{ - if (netdev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK) - features &= ~GMAC_OFFLOAD_FEATURES; - - return features; -} - static int gmac_set_features(struct net_device *netdev, netdev_features_t features) { @@ -2226,7 +2239,6 @@ static const struct net_device_ops gmac_351x_ops = { .ndo_set_mac_address = gmac_set_mac_address, .ndo_get_stats64 = gmac_get_stats64, .ndo_change_mtu = gmac_change_mtu, - .ndo_fix_features = gmac_fix_features, .ndo_set_features = gmac_set_features, }; @@ -2482,11 +2494,12 @@ static int gemini_ethernet_port_probe(struct platform_device *pdev) netdev->hw_features = GMAC_OFFLOAD_FEATURES; netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO; - /* We can handle jumbo frames up to 10236 bytes so, let's accept - * payloads of 10236 bytes minus VLAN and ethernet header + /* We can receive jumbo frames up to 10236 bytes but only + * transmit 2047 bytes so, let's accept payloads of 2047 + * bytes minus VLAN and ethernet header */ netdev->min_mtu = ETH_MIN_MTU; - netdev->max_mtu = 10236 - VLAN_ETH_HLEN; + netdev->max_mtu = MTU_SIZE_BIT_MASK - VLAN_ETH_HLEN; port->freeq_refill = 0; netif_napi_add(netdev, &port->napi, gmac_napi_poll, diff --git a/drivers/net/ethernet/cortina/gemini.h b/drivers/net/ethernet/cortina/gemini.h index 0b12f89bf89a313f574f8e8a7295dbc112bcdeab..ad913f15e89ba9fa0e666ebf575b0eb1c9234484 100644 --- a/drivers/net/ethernet/cortina/gemini.h +++ b/drivers/net/ethernet/cortina/gemini.h @@ -502,7 +502,7 @@ union gmac_txdesc_3 { #define SOF_BIT 0x80000000 #define EOF_BIT 0x40000000 #define EOFIE_BIT BIT(29) -#define MTU_SIZE_BIT_MASK 0x1fff +#define MTU_SIZE_BIT_MASK 0x7ff /* Max MTU 2047 bytes */ /* GMAC Tx Descriptor */ struct gmac_txdesc { @@ -787,7 +787,7 @@ union gmac_config0 { #define CONFIG0_MAXLEN_1536 0 #define CONFIG0_MAXLEN_1518 1 #define CONFIG0_MAXLEN_1522 2 -#define CONFIG0_MAXLEN_1542 3 +#define CONFIG0_MAXLEN_1548 3 #define CONFIG0_MAXLEN_9k 4 /* 9212 */ #define CONFIG0_MAXLEN_10k 5 /* 10236 */ #define CONFIG0_MAXLEN_1518__6 6 diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c index 05cb2f7cc35c372c5d34d22c5cd3ab2aa81ff3fb..d0d9a420f557eb7ea6a9d3ee32773722ba70cd34 100644 --- a/drivers/net/ethernet/emulex/benet/be_main.c +++ b/drivers/net/ethernet/emulex/benet/be_main.c @@ -1136,10 +1136,11 @@ static struct sk_buff *be_lancer_xmit_workarounds(struct be_adapter *adapter, eth_hdr_len = ntohs(skb->protocol) == ETH_P_8021Q ? VLAN_ETH_HLEN : ETH_HLEN; if (skb->len <= 60 && - (lancer_chip(adapter) || skb_vlan_tag_present(skb)) && - is_ipv4_pkt(skb)) { + (lancer_chip(adapter) || BE3_chip(adapter) || + skb_vlan_tag_present(skb)) && is_ipv4_pkt(skb)) { ip = (struct iphdr *)ip_hdr(skb); - pskb_trim(skb, eth_hdr_len + ntohs(ip->tot_len)); + if (unlikely(pskb_trim(skb, eth_hdr_len + ntohs(ip->tot_len)))) + goto tx_drop; } /* If vlan tag is already inlined in the packet, skip HW VLAN diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index e97ab9545a792c1aa7ce4a405d40cc9e1a5e22c9..e4162c2271e3f556b173dd740c50da700e689c95 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -3721,7 +3721,9 @@ fec_drv_remove(struct platform_device *pdev) ret = pm_runtime_get_sync(&pdev->dev); if (ret < 0) - return ret; + dev_err(&pdev->dev, + "Failed to resume device in remove callback (%pe)\n", + ERR_PTR(ret)); cancel_work_sync(&fep->tx_timeout_work); fec_ptp_stop(pdev); @@ -3734,8 +3736,13 @@ fec_drv_remove(struct platform_device *pdev) of_phy_deregister_fixed_link(np); of_node_put(fep->phy_node); - clk_disable_unprepare(fep->clk_ahb); - clk_disable_unprepare(fep->clk_ipg); + /* After pm_runtime_get_sync() failed, the clks are still off, so skip + * disabling them again. + */ + if (ret >= 0) { + clk_disable_unprepare(fep->clk_ahb); + clk_disable_unprepare(fep->clk_ipg); + } pm_runtime_put_noidle(&pdev->dev); pm_runtime_disable(&pdev->dev); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index 2c334b56fd42c081cfd0ad8cd757735110dfcab3..d668d25ae7e76dc0d4e605730c7404fb68ff335f 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -2517,8 +2517,13 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, u32 regclr) { +#define HCLGE_IMP_RESET_DELAY 5 + switch (event_type) { case HCLGE_VECTOR0_EVENT_RST: + if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) + mdelay(HCLGE_IMP_RESET_DELAY); + hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); break; case HCLGE_VECTOR0_EVENT_MBX: diff --git a/drivers/net/ethernet/ibm/ibmveth.c b/drivers/net/ethernet/ibm/ibmveth.c index 75a1915d95aa87b347263d8bee3d45da67c55eb7..23997f1c2619f81f4ad76e6ed21760eddc766b08 100644 --- a/drivers/net/ethernet/ibm/ibmveth.c +++ b/drivers/net/ethernet/ibm/ibmveth.c @@ -209,7 +209,7 @@ static inline void ibmveth_flush_buffer(void *addr, unsigned long length) unsigned long offset; for (offset = 0; offset < length; offset += SMP_CACHE_BYTES) - asm("dcbfl %0,%1" :: "b" (addr), "r" (offset)); + asm("dcbf %0,%1,1" :: "b" (addr), "r" (offset)); } /* replenish the buffers for a pool. note that we don't need to diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c index 1463cf4321a8365ce052e62b803736b9be2b8a6c..646f14a9bd9618e7c904b24b9f63d29fa5291972 100644 --- a/drivers/net/ethernet/ibm/ibmvnic.c +++ b/drivers/net/ethernet/ibm/ibmvnic.c @@ -884,12 +884,22 @@ static int ibmvnic_login(struct net_device *netdev) static void release_login_buffer(struct ibmvnic_adapter *adapter) { + if (!adapter->login_buf) + return; + + dma_unmap_single(&adapter->vdev->dev, adapter->login_buf_token, + adapter->login_buf_sz, DMA_TO_DEVICE); kfree(adapter->login_buf); adapter->login_buf = NULL; } static void release_login_rsp_buffer(struct ibmvnic_adapter *adapter) { + if (!adapter->login_rsp_buf) + return; + + dma_unmap_single(&adapter->vdev->dev, adapter->login_rsp_buf_token, + adapter->login_rsp_buf_sz, DMA_FROM_DEVICE); kfree(adapter->login_rsp_buf); adapter->login_rsp_buf = NULL; } @@ -4061,11 +4071,6 @@ static int handle_login_rsp(union ibmvnic_crq *login_rsp_crq, struct ibmvnic_login_buffer *login = adapter->login_buf; int i; - dma_unmap_single(dev, adapter->login_buf_token, adapter->login_buf_sz, - DMA_TO_DEVICE); - dma_unmap_single(dev, adapter->login_rsp_buf_token, - adapter->login_rsp_buf_sz, DMA_FROM_DEVICE); - /* If the number of queues requested can't be allocated by the * server, the login response will return with code 1. We will need * to resend the login buffer with fewer queues requested. diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig index 1ab613eb5796420c217d66287f72592c5875a55d..b542aba6f0e86c1ad694bd82cd1267100c5b9575 100644 --- a/drivers/net/ethernet/intel/Kconfig +++ b/drivers/net/ethernet/intel/Kconfig @@ -235,20 +235,27 @@ config I40E_DCB If unsure, say N. +# this is here to allow seamless migration from I40EVF --> IAVF name +# so that CONFIG_IAVF symbol will always mirror the state of CONFIG_I40EVF +config IAVF + tristate config I40EVF tristate "Intel(R) Ethernet Adaptive Virtual Function support" + select IAVF depends on PCI_MSI ---help--- This driver supports virtual functions for Intel XL710, - X710, X722, and all devices advertising support for Intel - Ethernet Adaptive Virtual Function devices. For more + X710, X722, XXV710, and all devices advertising support for + Intel Ethernet Adaptive Virtual Function devices. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: - + + + This driver was formerly named i40evf. To compile this driver as a module, choose M here. The module - will be called i40evf. MSI-X interrupt support is required + will be called iavf. MSI-X interrupt support is required for this driver to work correctly. config ICE diff --git a/drivers/net/ethernet/intel/Makefile b/drivers/net/ethernet/intel/Makefile index 807a4f8c7e4ef70e828585a500ebd67bc16fbe7d..b91153df6ee8db53faa6a61e208a94a52bcec909 100644 --- a/drivers/net/ethernet/intel/Makefile +++ b/drivers/net/ethernet/intel/Makefile @@ -12,6 +12,6 @@ obj-$(CONFIG_IXGBE) += ixgbe/ obj-$(CONFIG_IXGBEVF) += ixgbevf/ obj-$(CONFIG_I40E) += i40e/ obj-$(CONFIG_IXGB) += ixgb/ -obj-$(CONFIG_I40EVF) += i40evf/ +obj-$(CONFIG_IAVF) += iavf/ obj-$(CONFIG_FM10K) += fm10k/ obj-$(CONFIG_ICE) += ice/ diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c index 0629f87a20be7259c5ff60570e1dd078fdbbdd00..202f734f8733bf9e0866530ff38fbc5055ec9bec 100644 --- a/drivers/net/ethernet/intel/e1000e/netdev.c +++ b/drivers/net/ethernet/intel/e1000e/netdev.c @@ -5230,31 +5230,6 @@ static void e1000_watchdog_task(struct work_struct *work) ew32(TARC(0), tarc0); } - /* disable TSO for pcie and 10/100 speeds, to avoid - * some hardware issues - */ - if (!(adapter->flags & FLAG_TSO_FORCE)) { - switch (adapter->link_speed) { - case SPEED_10: - case SPEED_100: - e_info("10/100 speed: disabling TSO\n"); - netdev->features &= ~NETIF_F_TSO; - netdev->features &= ~NETIF_F_TSO6; - break; - case SPEED_1000: - netdev->features |= NETIF_F_TSO; - netdev->features |= NETIF_F_TSO6; - break; - default: - /* oops */ - break; - } - if (hw->mac.type == e1000_pch_spt) { - netdev->features &= ~NETIF_F_TSO; - netdev->features &= ~NETIF_F_TSO6; - } - } - /* enable transmits in the hardware, need to do this * after setting TARC(0) */ @@ -7191,6 +7166,32 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) NETIF_F_RXCSUM | NETIF_F_HW_CSUM); + /* disable TSO for pcie and 10/100 speeds to avoid + * some hardware issues and for i219 to fix transfer + * speed being capped at 60% + */ + if (!(adapter->flags & FLAG_TSO_FORCE)) { + switch (adapter->link_speed) { + case SPEED_10: + case SPEED_100: + e_info("10/100 speed: disabling TSO\n"); + netdev->features &= ~NETIF_F_TSO; + netdev->features &= ~NETIF_F_TSO6; + break; + case SPEED_1000: + netdev->features |= NETIF_F_TSO; + netdev->features |= NETIF_F_TSO6; + break; + default: + /* oops */ + break; + } + if (hw->mac.type == e1000_pch_spt) { + netdev->features &= ~NETIF_F_TSO; + netdev->features &= ~NETIF_F_TSO6; + } + } + /* Set user-changeable features (subset of all device features) */ netdev->hw_features = netdev->features; netdev->hw_features |= NETIF_F_RXFCS; diff --git a/drivers/net/ethernet/intel/i40e/i40e_alloc.h b/drivers/net/ethernet/intel/i40e/i40e_alloc.h index cb8689222c8b77c957be573b6fad8e6d75bcaa4d..55ba6b690ab6ced84c22e382cdde3b4da308540a 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_alloc.h +++ b/drivers/net/ethernet/intel/i40e/i40e_alloc.h @@ -20,16 +20,11 @@ enum i40e_memory_type { }; /* prototype for functions used for dynamic memory allocation */ -i40e_status i40e_allocate_dma_mem(struct i40e_hw *hw, - struct i40e_dma_mem *mem, - enum i40e_memory_type type, - u64 size, u32 alignment); -i40e_status i40e_free_dma_mem(struct i40e_hw *hw, - struct i40e_dma_mem *mem); -i40e_status i40e_allocate_virt_mem(struct i40e_hw *hw, - struct i40e_virt_mem *mem, - u32 size); -i40e_status i40e_free_virt_mem(struct i40e_hw *hw, - struct i40e_virt_mem *mem); +int i40e_allocate_dma_mem(struct i40e_hw *hw, struct i40e_dma_mem *mem, + enum i40e_memory_type type, u64 size, u32 alignment); +int i40e_free_dma_mem(struct i40e_hw *hw, struct i40e_dma_mem *mem); +int i40e_allocate_virt_mem(struct i40e_hw *hw, struct i40e_virt_mem *mem, + u32 size); +int i40e_free_virt_mem(struct i40e_hw *hw, struct i40e_virt_mem *mem); #endif /* _I40E_ALLOC_H_ */ diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c index e75b4c4872c0947e0b0df93eec1d13d51171b24b..95cd3c35b0034430df810a797121b19aab317965 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_common.c +++ b/drivers/net/ethernet/intel/i40e/i40e_common.c @@ -1332,7 +1332,7 @@ void i40e_clear_hw(struct i40e_hw *hw) I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> I40E_PFLAN_QALLOC_LASTQ_SHIFT; - if (val & I40E_PFLAN_QALLOC_VALID_MASK) + if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue) num_queues = (j - base_queue) + 1; else num_queues = 0; @@ -1342,7 +1342,7 @@ void i40e_clear_hw(struct i40e_hw *hw) I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> I40E_PF_VT_PFALLOC_LASTVF_SHIFT; - if (val & I40E_PF_VT_PFALLOC_VALID_MASK) + if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i) num_vfs = (j - i) + 1; else num_vfs = 0; diff --git a/drivers/net/ethernet/intel/i40e/i40e_debugfs.c b/drivers/net/ethernet/intel/i40e/i40e_debugfs.c index a66492b9403c4d4a218fe1df334e8c6776a0fd34..5b82c89330e300603bb81283a0226f3487ab51ed 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_debugfs.c +++ b/drivers/net/ethernet/intel/i40e/i40e_debugfs.c @@ -1798,7 +1798,7 @@ void i40e_dbg_pf_exit(struct i40e_pf *pf) void i40e_dbg_init(void) { i40e_dbg_root = debugfs_create_dir(i40e_driver_name, NULL); - if (!i40e_dbg_root) + if (IS_ERR(i40e_dbg_root)) pr_info("init of debugfs failed\n"); } diff --git a/drivers/net/ethernet/intel/i40e/i40e_diag.c b/drivers/net/ethernet/intel/i40e/i40e_diag.c index ef4d3762bf371191c75dba65a53ea784136803ed..ca229b0efeb65d38326c0a8d5c29a9b3a8c08169 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_diag.c +++ b/drivers/net/ethernet/intel/i40e/i40e_diag.c @@ -44,7 +44,7 @@ static i40e_status i40e_diag_reg_pattern_test(struct i40e_hw *hw, return 0; } -struct i40e_diag_reg_test_info i40e_reg_list[] = { +const struct i40e_diag_reg_test_info i40e_reg_list[] = { /* offset mask elements stride */ {I40E_QTX_CTL(0), 0x0000FFBF, 1, I40E_QTX_CTL(1) - I40E_QTX_CTL(0)}, @@ -78,27 +78,28 @@ i40e_status i40e_diag_reg_test(struct i40e_hw *hw) { i40e_status ret_code = 0; u32 reg, mask; + u32 elements; u32 i, j; for (i = 0; i40e_reg_list[i].offset != 0 && !ret_code; i++) { + elements = i40e_reg_list[i].elements; /* set actual reg range for dynamically allocated resources */ if (i40e_reg_list[i].offset == I40E_QTX_CTL(0) && hw->func_caps.num_tx_qp != 0) - i40e_reg_list[i].elements = hw->func_caps.num_tx_qp; + elements = hw->func_caps.num_tx_qp; if ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) || i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) || i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) || i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) || i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) && hw->func_caps.num_msix_vectors != 0) - i40e_reg_list[i].elements = - hw->func_caps.num_msix_vectors - 1; + elements = hw->func_caps.num_msix_vectors - 1; /* test register access */ mask = i40e_reg_list[i].mask; - for (j = 0; j < i40e_reg_list[i].elements && !ret_code; j++) { + for (j = 0; j < elements && !ret_code; j++) { reg = i40e_reg_list[i].offset + (j * i40e_reg_list[i].stride); ret_code = i40e_diag_reg_pattern_test(hw, reg, mask); diff --git a/drivers/net/ethernet/intel/i40e/i40e_diag.h b/drivers/net/ethernet/intel/i40e/i40e_diag.h index c3340f320a18c56dd602c4dc910bc922782c0a72..1db7c6d572311d30fe097f6b451a84b2aee45576 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_diag.h +++ b/drivers/net/ethernet/intel/i40e/i40e_diag.h @@ -20,7 +20,7 @@ struct i40e_diag_reg_test_info { u32 stride; /* bytes between each element */ }; -extern struct i40e_diag_reg_test_info i40e_reg_list[]; +extern const struct i40e_diag_reg_test_info i40e_reg_list[]; i40e_status i40e_diag_reg_test(struct i40e_hw *hw); i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw); diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c index 795f8fe2570e452806a22c71253980aebd2e9967..75a553f4e26f630a56a75b413f155d2b0f44fae8 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c @@ -9702,8 +9702,11 @@ static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired) pf->hw.aq.asq_last_status)); } /* reinit the misc interrupt */ - if (pf->flags & I40E_FLAG_MSIX_ENABLED) + if (pf->flags & I40E_FLAG_MSIX_ENABLED) { ret = i40e_setup_misc_vector(pf); + if (ret) + goto end_unlock; + } /* Add a filter to drop all Flow control frames from any VSI from being * transmitted. By doing so we stop a malicious VF from sending out @@ -12484,15 +12487,15 @@ static int i40e_add_vsi(struct i40e_vsi *vsi) vsi->id = ctxt.vsi_number; } - vsi->active_filters = 0; - clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); spin_lock_bh(&vsi->mac_filter_hash_lock); + vsi->active_filters = 0; /* If macvlan filters already exist, force them to get loaded */ hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { f->state = I40E_FILTER_NEW; f_count++; } spin_unlock_bh(&vsi->mac_filter_hash_lock); + clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); if (f_count) { vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; @@ -14308,11 +14311,15 @@ static void i40e_remove(struct pci_dev *pdev) i40e_switch_branch_release(pf->veb[i]); } - /* Now we can shutdown the PF's VSI, just before we kill + /* Now we can shutdown the PF's VSIs, just before we kill * adminq and hmc. */ - if (pf->vsi[pf->lan_vsi]) - i40e_vsi_release(pf->vsi[pf->lan_vsi]); + for (i = pf->num_alloc_vsi; i--;) + if (pf->vsi[i]) { + i40e_vsi_close(pf->vsi[i]); + i40e_vsi_release(pf->vsi[i]); + pf->vsi[i] = NULL; + } i40e_cloud_filter_exit(pf); diff --git a/drivers/net/ethernet/intel/i40e/i40e_nvm.c b/drivers/net/ethernet/intel/i40e/i40e_nvm.c index 0299e5bbb9022a457fa398ca7a401bc73bc6c1b8..10e9e60f6cf779cb9783c5f78ddc540af0009263 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_nvm.c +++ b/drivers/net/ethernet/intel/i40e/i40e_nvm.c @@ -210,11 +210,11 @@ static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset, * @hw: pointer to the HW structure. * @module_pointer: module pointer location in words from the NVM beginning * @offset: offset in words from module start - * @words: number of words to write - * @data: buffer with words to write to the Shadow RAM + * @words: number of words to read + * @data: buffer with words to read to the Shadow RAM * @last_command: tells the AdminQ that this is the last command * - * Writes a 16 bit words buffer to the Shadow RAM using the admin command. + * Reads a 16 bit words buffer to the Shadow RAM using the admin command. **/ static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer, u32 offset, @@ -234,18 +234,18 @@ static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, */ if ((offset + words) > hw->nvm.sr_size) i40e_debug(hw, I40E_DEBUG_NVM, - "NVM write error: offset %d beyond Shadow RAM limit %d\n", + "NVM read error: offset %d beyond Shadow RAM limit %d\n", (offset + words), hw->nvm.sr_size); else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) - /* We can write only up to 4KB (one sector), in one AQ write */ + /* We can read only up to 4KB (one sector), in one AQ write */ i40e_debug(hw, I40E_DEBUG_NVM, - "NVM write fail error: tried to write %d words, limit is %d.\n", + "NVM read fail error: tried to read %d words, limit is %d.\n", words, I40E_SR_SECTOR_SIZE_IN_WORDS); else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) - /* A single write cannot spread over two sectors */ + /* A single read cannot spread over two sectors */ i40e_debug(hw, I40E_DEBUG_NVM, - "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", + "NVM read error: cannot spread over two sectors in a single read offset=%d words=%d\n", offset, words); else ret_code = i40e_aq_read_nvm(hw, module_pointer, diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c index 9ccbcd88bf1e6b286db54e4f9dafa1f58b3449fa..dfce967a066a4de7cd2976caa5fb791aef8b179f 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c +++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c @@ -2642,7 +2642,7 @@ int i40e_napi_poll(struct napi_struct *napi, int budget) return budget; } - if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) + if (q_vector->tx.ring[0].flags & I40E_TXR_FLAGS_WB_ON_ITR) q_vector->arm_wb_state = false; /* Work is done so exit the polling mode and re-enable the interrupt */ diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c index 240083201dbf4b29bdd92b348a552fee0129831e..1527c67b487b2bb6d9a46192cfb7e6e2a91979bf 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c +++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c @@ -2595,7 +2595,7 @@ static inline int i40e_check_vf_permission(struct i40e_vf *vf, !is_multicast_ether_addr(addr) && vf->pf_set_mac && !ether_addr_equal(addr, vf->default_lan_addr.addr)) { dev_err(&pf->pdev->dev, - "VF attempting to override administratively set MAC address, reload the VF driver to resume normal operation\n"); + "VF attempting to override administratively set MAC address, bring down and up the VF interface to resume normal operation\n"); return -EPERM; } } @@ -4019,9 +4019,11 @@ int i40e_ndo_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) mac, vf_id); } - /* Force the VF driver stop so it has to reload with new MAC address */ + /* Force the VF interface down so it has to bring up with new MAC + * address + */ i40e_vc_disable_vf(vf); - dev_info(&pf->pdev->dev, "Reload the VF driver to make this change effective.\n"); + dev_info(&pf->pdev->dev, "Bring down and up the VF interface to make this change effective.\n"); error_param: return ret; diff --git a/drivers/net/ethernet/intel/i40evf/Makefile b/drivers/net/ethernet/intel/i40evf/Makefile deleted file mode 100644 index 3c5c6e9622805c3f890c683b3a87aa37f10b241e..0000000000000000000000000000000000000000 --- a/drivers/net/ethernet/intel/i40evf/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# Copyright(c) 2013 - 2018 Intel Corporation. - -# -## Makefile for the Intel(R) 40GbE VF driver -# -# - -ccflags-y += -I$(src) -subdir-ccflags-y += -I$(src) - -obj-$(CONFIG_I40EVF) += i40evf.o - -i40evf-objs := i40evf_main.o i40evf_ethtool.o i40evf_virtchnl.o \ - i40e_txrx.o i40e_common.o i40e_adminq.o i40evf_client.o - diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h deleted file mode 100644 index 5fd8529465d48db0ee9b5ac27835253fbcf9beea..0000000000000000000000000000000000000000 --- a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h +++ /dev/null @@ -1,2717 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright(c) 2013 - 2018 Intel Corporation. */ - -#ifndef _I40E_ADMINQ_CMD_H_ -#define _I40E_ADMINQ_CMD_H_ - -/* This header file defines the i40e Admin Queue commands and is shared between - * i40e Firmware and Software. - * - * This file needs to comply with the Linux Kernel coding style. - */ - -#define I40E_FW_API_VERSION_MAJOR 0x0001 -#define I40E_FW_API_VERSION_MINOR_X722 0x0005 -#define I40E_FW_API_VERSION_MINOR_X710 0x0007 - -#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ - I40E_FW_API_VERSION_MINOR_X710 : \ - I40E_FW_API_VERSION_MINOR_X722) - -/* API version 1.7 implements additional link and PHY-specific APIs */ -#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 - -struct i40e_aq_desc { - __le16 flags; - __le16 opcode; - __le16 datalen; - __le16 retval; - __le32 cookie_high; - __le32 cookie_low; - union { - struct { - __le32 param0; - __le32 param1; - __le32 param2; - __le32 param3; - } internal; - struct { - __le32 param0; - __le32 param1; - __le32 addr_high; - __le32 addr_low; - } external; - u8 raw[16]; - } params; -}; - -/* Flags sub-structure - * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | - * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | - */ - -/* command flags and offsets*/ -#define I40E_AQ_FLAG_DD_SHIFT 0 -#define I40E_AQ_FLAG_CMP_SHIFT 1 -#define I40E_AQ_FLAG_ERR_SHIFT 2 -#define I40E_AQ_FLAG_VFE_SHIFT 3 -#define I40E_AQ_FLAG_LB_SHIFT 9 -#define I40E_AQ_FLAG_RD_SHIFT 10 -#define I40E_AQ_FLAG_VFC_SHIFT 11 -#define I40E_AQ_FLAG_BUF_SHIFT 12 -#define I40E_AQ_FLAG_SI_SHIFT 13 -#define I40E_AQ_FLAG_EI_SHIFT 14 -#define I40E_AQ_FLAG_FE_SHIFT 15 - -#define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ -#define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ -#define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ -#define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ -#define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ -#define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ -#define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ -#define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ -#define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ -#define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ -#define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ - -/* error codes */ -enum i40e_admin_queue_err { - I40E_AQ_RC_OK = 0, /* success */ - I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ - I40E_AQ_RC_ENOENT = 2, /* No such element */ - I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ - I40E_AQ_RC_EINTR = 4, /* operation interrupted */ - I40E_AQ_RC_EIO = 5, /* I/O error */ - I40E_AQ_RC_ENXIO = 6, /* No such resource */ - I40E_AQ_RC_E2BIG = 7, /* Arg too long */ - I40E_AQ_RC_EAGAIN = 8, /* Try again */ - I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ - I40E_AQ_RC_EACCES = 10, /* Permission denied */ - I40E_AQ_RC_EFAULT = 11, /* Bad address */ - I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ - I40E_AQ_RC_EEXIST = 13, /* object already exists */ - I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ - I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ - I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ - I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ - I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ - I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ - I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ - I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ - I40E_AQ_RC_EFBIG = 22, /* File too large */ -}; - -/* Admin Queue command opcodes */ -enum i40e_admin_queue_opc { - /* aq commands */ - i40e_aqc_opc_get_version = 0x0001, - i40e_aqc_opc_driver_version = 0x0002, - i40e_aqc_opc_queue_shutdown = 0x0003, - i40e_aqc_opc_set_pf_context = 0x0004, - - /* resource ownership */ - i40e_aqc_opc_request_resource = 0x0008, - i40e_aqc_opc_release_resource = 0x0009, - - i40e_aqc_opc_list_func_capabilities = 0x000A, - i40e_aqc_opc_list_dev_capabilities = 0x000B, - - /* Proxy commands */ - i40e_aqc_opc_set_proxy_config = 0x0104, - i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, - - /* LAA */ - i40e_aqc_opc_mac_address_read = 0x0107, - i40e_aqc_opc_mac_address_write = 0x0108, - - /* PXE */ - i40e_aqc_opc_clear_pxe_mode = 0x0110, - - /* WoL commands */ - i40e_aqc_opc_set_wol_filter = 0x0120, - i40e_aqc_opc_get_wake_reason = 0x0121, - - /* internal switch commands */ - i40e_aqc_opc_get_switch_config = 0x0200, - i40e_aqc_opc_add_statistics = 0x0201, - i40e_aqc_opc_remove_statistics = 0x0202, - i40e_aqc_opc_set_port_parameters = 0x0203, - i40e_aqc_opc_get_switch_resource_alloc = 0x0204, - i40e_aqc_opc_set_switch_config = 0x0205, - i40e_aqc_opc_rx_ctl_reg_read = 0x0206, - i40e_aqc_opc_rx_ctl_reg_write = 0x0207, - - i40e_aqc_opc_add_vsi = 0x0210, - i40e_aqc_opc_update_vsi_parameters = 0x0211, - i40e_aqc_opc_get_vsi_parameters = 0x0212, - - i40e_aqc_opc_add_pv = 0x0220, - i40e_aqc_opc_update_pv_parameters = 0x0221, - i40e_aqc_opc_get_pv_parameters = 0x0222, - - i40e_aqc_opc_add_veb = 0x0230, - i40e_aqc_opc_update_veb_parameters = 0x0231, - i40e_aqc_opc_get_veb_parameters = 0x0232, - - i40e_aqc_opc_delete_element = 0x0243, - - i40e_aqc_opc_add_macvlan = 0x0250, - i40e_aqc_opc_remove_macvlan = 0x0251, - i40e_aqc_opc_add_vlan = 0x0252, - i40e_aqc_opc_remove_vlan = 0x0253, - i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, - i40e_aqc_opc_add_tag = 0x0255, - i40e_aqc_opc_remove_tag = 0x0256, - i40e_aqc_opc_add_multicast_etag = 0x0257, - i40e_aqc_opc_remove_multicast_etag = 0x0258, - i40e_aqc_opc_update_tag = 0x0259, - i40e_aqc_opc_add_control_packet_filter = 0x025A, - i40e_aqc_opc_remove_control_packet_filter = 0x025B, - i40e_aqc_opc_add_cloud_filters = 0x025C, - i40e_aqc_opc_remove_cloud_filters = 0x025D, - i40e_aqc_opc_clear_wol_switch_filters = 0x025E, - - i40e_aqc_opc_add_mirror_rule = 0x0260, - i40e_aqc_opc_delete_mirror_rule = 0x0261, - - /* Dynamic Device Personalization */ - i40e_aqc_opc_write_personalization_profile = 0x0270, - i40e_aqc_opc_get_personalization_profile_list = 0x0271, - - /* DCB commands */ - i40e_aqc_opc_dcb_ignore_pfc = 0x0301, - i40e_aqc_opc_dcb_updated = 0x0302, - i40e_aqc_opc_set_dcb_parameters = 0x0303, - - /* TX scheduler */ - i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, - i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, - i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, - i40e_aqc_opc_query_vsi_bw_config = 0x0408, - i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, - i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, - - i40e_aqc_opc_enable_switching_comp_ets = 0x0413, - i40e_aqc_opc_modify_switching_comp_ets = 0x0414, - i40e_aqc_opc_disable_switching_comp_ets = 0x0415, - i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, - i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, - i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, - i40e_aqc_opc_query_port_ets_config = 0x0419, - i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, - i40e_aqc_opc_suspend_port_tx = 0x041B, - i40e_aqc_opc_resume_port_tx = 0x041C, - i40e_aqc_opc_configure_partition_bw = 0x041D, - /* hmc */ - i40e_aqc_opc_query_hmc_resource_profile = 0x0500, - i40e_aqc_opc_set_hmc_resource_profile = 0x0501, - - /* phy commands*/ - i40e_aqc_opc_get_phy_abilities = 0x0600, - i40e_aqc_opc_set_phy_config = 0x0601, - i40e_aqc_opc_set_mac_config = 0x0603, - i40e_aqc_opc_set_link_restart_an = 0x0605, - i40e_aqc_opc_get_link_status = 0x0607, - i40e_aqc_opc_set_phy_int_mask = 0x0613, - i40e_aqc_opc_get_local_advt_reg = 0x0614, - i40e_aqc_opc_set_local_advt_reg = 0x0615, - i40e_aqc_opc_get_partner_advt = 0x0616, - i40e_aqc_opc_set_lb_modes = 0x0618, - i40e_aqc_opc_get_phy_wol_caps = 0x0621, - i40e_aqc_opc_set_phy_debug = 0x0622, - i40e_aqc_opc_upload_ext_phy_fm = 0x0625, - i40e_aqc_opc_run_phy_activity = 0x0626, - i40e_aqc_opc_set_phy_register = 0x0628, - i40e_aqc_opc_get_phy_register = 0x0629, - - /* NVM commands */ - i40e_aqc_opc_nvm_read = 0x0701, - i40e_aqc_opc_nvm_erase = 0x0702, - i40e_aqc_opc_nvm_update = 0x0703, - i40e_aqc_opc_nvm_config_read = 0x0704, - i40e_aqc_opc_nvm_config_write = 0x0705, - i40e_aqc_opc_oem_post_update = 0x0720, - i40e_aqc_opc_thermal_sensor = 0x0721, - - /* virtualization commands */ - i40e_aqc_opc_send_msg_to_pf = 0x0801, - i40e_aqc_opc_send_msg_to_vf = 0x0802, - i40e_aqc_opc_send_msg_to_peer = 0x0803, - - /* alternate structure */ - i40e_aqc_opc_alternate_write = 0x0900, - i40e_aqc_opc_alternate_write_indirect = 0x0901, - i40e_aqc_opc_alternate_read = 0x0902, - i40e_aqc_opc_alternate_read_indirect = 0x0903, - i40e_aqc_opc_alternate_write_done = 0x0904, - i40e_aqc_opc_alternate_set_mode = 0x0905, - i40e_aqc_opc_alternate_clear_port = 0x0906, - - /* LLDP commands */ - i40e_aqc_opc_lldp_get_mib = 0x0A00, - i40e_aqc_opc_lldp_update_mib = 0x0A01, - i40e_aqc_opc_lldp_add_tlv = 0x0A02, - i40e_aqc_opc_lldp_update_tlv = 0x0A03, - i40e_aqc_opc_lldp_delete_tlv = 0x0A04, - i40e_aqc_opc_lldp_stop = 0x0A05, - i40e_aqc_opc_lldp_start = 0x0A06, - - /* Tunnel commands */ - i40e_aqc_opc_add_udp_tunnel = 0x0B00, - i40e_aqc_opc_del_udp_tunnel = 0x0B01, - i40e_aqc_opc_set_rss_key = 0x0B02, - i40e_aqc_opc_set_rss_lut = 0x0B03, - i40e_aqc_opc_get_rss_key = 0x0B04, - i40e_aqc_opc_get_rss_lut = 0x0B05, - - /* Async Events */ - i40e_aqc_opc_event_lan_overflow = 0x1001, - - /* OEM commands */ - i40e_aqc_opc_oem_parameter_change = 0xFE00, - i40e_aqc_opc_oem_device_status_change = 0xFE01, - i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, - i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, - - /* debug commands */ - i40e_aqc_opc_debug_read_reg = 0xFF03, - i40e_aqc_opc_debug_write_reg = 0xFF04, - i40e_aqc_opc_debug_modify_reg = 0xFF07, - i40e_aqc_opc_debug_dump_internals = 0xFF08, -}; - -/* command structures and indirect data structures */ - -/* Structure naming conventions: - * - no suffix for direct command descriptor structures - * - _data for indirect sent data - * - _resp for indirect return data (data which is both will use _data) - * - _completion for direct return data - * - _element_ for repeated elements (may also be _data or _resp) - * - * Command structures are expected to overlay the params.raw member of the basic - * descriptor, and as such cannot exceed 16 bytes in length. - */ - -/* This macro is used to generate a compilation error if a structure - * is not exactly the correct length. It gives a divide by zero error if the - * structure is not of the correct size, otherwise it creates an enum that is - * never used. - */ -#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ - { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } - -/* This macro is used extensively to ensure that command structures are 16 - * bytes in length as they have to map to the raw array of that size. - */ -#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) - -/* internal (0x00XX) commands */ - -/* Get version (direct 0x0001) */ -struct i40e_aqc_get_version { - __le32 rom_ver; - __le32 fw_build; - __le16 fw_major; - __le16 fw_minor; - __le16 api_major; - __le16 api_minor; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); - -/* Send driver version (indirect 0x0002) */ -struct i40e_aqc_driver_version { - u8 driver_major_ver; - u8 driver_minor_ver; - u8 driver_build_ver; - u8 driver_subbuild_ver; - u8 reserved[4]; - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); - -/* Queue Shutdown (direct 0x0003) */ -struct i40e_aqc_queue_shutdown { - __le32 driver_unloading; -#define I40E_AQ_DRIVER_UNLOADING 0x1 - u8 reserved[12]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); - -/* Set PF context (0x0004, direct) */ -struct i40e_aqc_set_pf_context { - u8 pf_id; - u8 reserved[15]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); - -/* Request resource ownership (direct 0x0008) - * Release resource ownership (direct 0x0009) - */ -#define I40E_AQ_RESOURCE_NVM 1 -#define I40E_AQ_RESOURCE_SDP 2 -#define I40E_AQ_RESOURCE_ACCESS_READ 1 -#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 -#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 -#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 - -struct i40e_aqc_request_resource { - __le16 resource_id; - __le16 access_type; - __le32 timeout; - __le32 resource_number; - u8 reserved[4]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); - -/* Get function capabilities (indirect 0x000A) - * Get device capabilities (indirect 0x000B) - */ -struct i40e_aqc_list_capabilites { - u8 command_flags; -#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 - u8 pf_index; - u8 reserved[2]; - __le32 count; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); - -struct i40e_aqc_list_capabilities_element_resp { - __le16 id; - u8 major_rev; - u8 minor_rev; - __le32 number; - __le32 logical_id; - __le32 phys_id; - u8 reserved[16]; -}; - -/* list of caps */ - -#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 -#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 -#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 -#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 -#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 -#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 -#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 -#define I40E_AQ_CAP_ID_SRIOV 0x0012 -#define I40E_AQ_CAP_ID_VF 0x0013 -#define I40E_AQ_CAP_ID_VMDQ 0x0014 -#define I40E_AQ_CAP_ID_8021QBG 0x0015 -#define I40E_AQ_CAP_ID_8021QBR 0x0016 -#define I40E_AQ_CAP_ID_VSI 0x0017 -#define I40E_AQ_CAP_ID_DCB 0x0018 -#define I40E_AQ_CAP_ID_FCOE 0x0021 -#define I40E_AQ_CAP_ID_ISCSI 0x0022 -#define I40E_AQ_CAP_ID_RSS 0x0040 -#define I40E_AQ_CAP_ID_RXQ 0x0041 -#define I40E_AQ_CAP_ID_TXQ 0x0042 -#define I40E_AQ_CAP_ID_MSIX 0x0043 -#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 -#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 -#define I40E_AQ_CAP_ID_1588 0x0046 -#define I40E_AQ_CAP_ID_IWARP 0x0051 -#define I40E_AQ_CAP_ID_LED 0x0061 -#define I40E_AQ_CAP_ID_SDP 0x0062 -#define I40E_AQ_CAP_ID_MDIO 0x0063 -#define I40E_AQ_CAP_ID_WSR_PROT 0x0064 -#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 -#define I40E_AQ_CAP_ID_FLEX10 0x00F1 -#define I40E_AQ_CAP_ID_CEM 0x00F2 - -/* Set CPPM Configuration (direct 0x0103) */ -struct i40e_aqc_cppm_configuration { - __le16 command_flags; -#define I40E_AQ_CPPM_EN_LTRC 0x0800 -#define I40E_AQ_CPPM_EN_DMCTH 0x1000 -#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 -#define I40E_AQ_CPPM_EN_HPTC 0x4000 -#define I40E_AQ_CPPM_EN_DMARC 0x8000 - __le16 ttlx; - __le32 dmacr; - __le16 dmcth; - u8 hptc; - u8 reserved; - __le32 pfltrc; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); - -/* Set ARP Proxy command / response (indirect 0x0104) */ -struct i40e_aqc_arp_proxy_data { - __le16 command_flags; -#define I40E_AQ_ARP_INIT_IPV4 0x0800 -#define I40E_AQ_ARP_UNSUP_CTL 0x1000 -#define I40E_AQ_ARP_ENA 0x2000 -#define I40E_AQ_ARP_ADD_IPV4 0x4000 -#define I40E_AQ_ARP_DEL_IPV4 0x8000 - __le16 table_id; - __le32 enabled_offloads; -#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 -#define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 - __le32 ip_addr; - u8 mac_addr[6]; - u8 reserved[2]; -}; - -I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); - -/* Set NS Proxy Table Entry Command (indirect 0x0105) */ -struct i40e_aqc_ns_proxy_data { - __le16 table_idx_mac_addr_0; - __le16 table_idx_mac_addr_1; - __le16 table_idx_ipv6_0; - __le16 table_idx_ipv6_1; - __le16 control; -#define I40E_AQ_NS_PROXY_ADD_0 0x0001 -#define I40E_AQ_NS_PROXY_DEL_0 0x0002 -#define I40E_AQ_NS_PROXY_ADD_1 0x0004 -#define I40E_AQ_NS_PROXY_DEL_1 0x0008 -#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 -#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 -#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 -#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 -#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 -#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 -#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 -#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 -#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 - u8 mac_addr_0[6]; - u8 mac_addr_1[6]; - u8 local_mac_addr[6]; - u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ - u8 ipv6_addr_1[16]; -}; - -I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); - -/* Manage LAA Command (0x0106) - obsolete */ -struct i40e_aqc_mng_laa { - __le16 command_flags; -#define I40E_AQ_LAA_FLAG_WR 0x8000 - u8 reserved[2]; - __le32 sal; - __le16 sah; - u8 reserved2[6]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); - -/* Manage MAC Address Read Command (indirect 0x0107) */ -struct i40e_aqc_mac_address_read { - __le16 command_flags; -#define I40E_AQC_LAN_ADDR_VALID 0x10 -#define I40E_AQC_SAN_ADDR_VALID 0x20 -#define I40E_AQC_PORT_ADDR_VALID 0x40 -#define I40E_AQC_WOL_ADDR_VALID 0x80 -#define I40E_AQC_MC_MAG_EN_VALID 0x100 -#define I40E_AQC_ADDR_VALID_MASK 0x3F0 - u8 reserved[6]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); - -struct i40e_aqc_mac_address_read_data { - u8 pf_lan_mac[6]; - u8 pf_san_mac[6]; - u8 port_mac[6]; - u8 pf_wol_mac[6]; -}; - -I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); - -/* Manage MAC Address Write Command (0x0108) */ -struct i40e_aqc_mac_address_write { - __le16 command_flags; -#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 -#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 -#define I40E_AQC_WRITE_TYPE_PORT 0x8000 -#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 -#define I40E_AQC_WRITE_TYPE_MASK 0xC000 - - __le16 mac_sah; - __le32 mac_sal; - u8 reserved[8]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); - -/* PXE commands (0x011x) */ - -/* Clear PXE Command and response (direct 0x0110) */ -struct i40e_aqc_clear_pxe { - u8 rx_cnt; - u8 reserved[15]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); - -/* Set WoL Filter (0x0120) */ - -struct i40e_aqc_set_wol_filter { - __le16 filter_index; -#define I40E_AQC_MAX_NUM_WOL_FILTERS 8 -#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 -#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ - I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) - -#define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 -#define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ - I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) - __le16 cmd_flags; -#define I40E_AQC_SET_WOL_FILTER 0x8000 -#define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 -#define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 -#define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 -#define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 - __le16 valid_flags; -#define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 -#define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 - u8 reserved[2]; - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); - -struct i40e_aqc_set_wol_filter_data { - u8 filter[128]; - u8 mask[16]; -}; - -I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); - -/* Get Wake Reason (0x0121) */ - -struct i40e_aqc_get_wake_reason_completion { - u8 reserved_1[2]; - __le16 wake_reason; -#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 -#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ - I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) -#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 -#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ - I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) - u8 reserved_2[12]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); - -/* Switch configuration commands (0x02xx) */ - -/* Used by many indirect commands that only pass an seid and a buffer in the - * command - */ -struct i40e_aqc_switch_seid { - __le16 seid; - u8 reserved[6]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); - -/* Get Switch Configuration command (indirect 0x0200) - * uses i40e_aqc_switch_seid for the descriptor - */ -struct i40e_aqc_get_switch_config_header_resp { - __le16 num_reported; - __le16 num_total; - u8 reserved[12]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); - -struct i40e_aqc_switch_config_element_resp { - u8 element_type; -#define I40E_AQ_SW_ELEM_TYPE_MAC 1 -#define I40E_AQ_SW_ELEM_TYPE_PF 2 -#define I40E_AQ_SW_ELEM_TYPE_VF 3 -#define I40E_AQ_SW_ELEM_TYPE_EMP 4 -#define I40E_AQ_SW_ELEM_TYPE_BMC 5 -#define I40E_AQ_SW_ELEM_TYPE_PV 16 -#define I40E_AQ_SW_ELEM_TYPE_VEB 17 -#define I40E_AQ_SW_ELEM_TYPE_PA 18 -#define I40E_AQ_SW_ELEM_TYPE_VSI 19 - u8 revision; -#define I40E_AQ_SW_ELEM_REV_1 1 - __le16 seid; - __le16 uplink_seid; - __le16 downlink_seid; - u8 reserved[3]; - u8 connection_type; -#define I40E_AQ_CONN_TYPE_REGULAR 0x1 -#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 -#define I40E_AQ_CONN_TYPE_CASCADED 0x3 - __le16 scheduler_id; - __le16 element_info; -}; - -I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); - -/* Get Switch Configuration (indirect 0x0200) - * an array of elements are returned in the response buffer - * the first in the array is the header, remainder are elements - */ -struct i40e_aqc_get_switch_config_resp { - struct i40e_aqc_get_switch_config_header_resp header; - struct i40e_aqc_switch_config_element_resp element[1]; -}; - -I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); - -/* Add Statistics (direct 0x0201) - * Remove Statistics (direct 0x0202) - */ -struct i40e_aqc_add_remove_statistics { - __le16 seid; - __le16 vlan; - __le16 stat_index; - u8 reserved[10]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); - -/* Set Port Parameters command (direct 0x0203) */ -struct i40e_aqc_set_port_parameters { - __le16 command_flags; -#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 -#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ -#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 - __le16 bad_frame_vsi; -#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 -#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF - __le16 default_seid; /* reserved for command */ - u8 reserved[10]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); - -/* Get Switch Resource Allocation (indirect 0x0204) */ -struct i40e_aqc_get_switch_resource_alloc { - u8 num_entries; /* reserved for command */ - u8 reserved[7]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); - -/* expect an array of these structs in the response buffer */ -struct i40e_aqc_switch_resource_alloc_element_resp { - u8 resource_type; -#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 -#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 -#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 -#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 -#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 -#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 -#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 -#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 -#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 -#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 -#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA -#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB -#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC -#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD -#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF -#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 -#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 -#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 -#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 - u8 reserved1; - __le16 guaranteed; - __le16 total; - __le16 used; - __le16 total_unalloced; - u8 reserved2[6]; -}; - -I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); - -/* Set Switch Configuration (direct 0x0205) */ -struct i40e_aqc_set_switch_config { - __le16 flags; -/* flags used for both fields below */ -#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 -#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 - __le16 valid_flags; - /* The ethertype in switch_tag is dropped on ingress and used - * internally by the switch. Set this to zero for the default - * of 0x88a8 (802.1ad). Should be zero for firmware API - * versions lower than 1.7. - */ - __le16 switch_tag; - /* The ethertypes in first_tag and second_tag are used to - * match the outer and inner VLAN tags (respectively) when HW - * double VLAN tagging is enabled via the set port parameters - * AQ command. Otherwise these are both ignored. Set them to - * zero for their defaults of 0x8100 (802.1Q). Should be zero - * for firmware API versions lower than 1.7. - */ - __le16 first_tag; - __le16 second_tag; - u8 reserved[6]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); - -/* Read Receive control registers (direct 0x0206) - * Write Receive control registers (direct 0x0207) - * used for accessing Rx control registers that can be - * slow and need special handling when under high Rx load - */ -struct i40e_aqc_rx_ctl_reg_read_write { - __le32 reserved1; - __le32 address; - __le32 reserved2; - __le32 value; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); - -/* Add VSI (indirect 0x0210) - * this indirect command uses struct i40e_aqc_vsi_properties_data - * as the indirect buffer (128 bytes) - * - * Update VSI (indirect 0x211) - * uses the same data structure as Add VSI - * - * Get VSI (indirect 0x0212) - * uses the same completion and data structure as Add VSI - */ -struct i40e_aqc_add_get_update_vsi { - __le16 uplink_seid; - u8 connection_type; -#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 -#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 -#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 - u8 reserved1; - u8 vf_id; - u8 reserved2; - __le16 vsi_flags; -#define I40E_AQ_VSI_TYPE_SHIFT 0x0 -#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) -#define I40E_AQ_VSI_TYPE_VF 0x0 -#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 -#define I40E_AQ_VSI_TYPE_PF 0x2 -#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 -#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); - -struct i40e_aqc_add_get_update_vsi_completion { - __le16 seid; - __le16 vsi_number; - __le16 vsi_used; - __le16 vsi_free; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); - -struct i40e_aqc_vsi_properties_data { - /* first 96 byte are written by SW */ - __le16 valid_sections; -#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 -#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 -#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 -#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 -#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 -#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 -#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 -#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 -#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 -#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 - /* switch section */ - __le16 switch_id; /* 12bit id combined with flags below */ -#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 -#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) -#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 -#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 -#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 - u8 sw_reserved[2]; - /* security section */ - u8 sec_flags; -#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 -#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 -#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 - u8 sec_reserved; - /* VLAN section */ - __le16 pvid; /* VLANS include priority bits */ - __le16 fcoe_pvid; - u8 port_vlan_flags; -#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 -#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ - I40E_AQ_VSI_PVLAN_MODE_SHIFT) -#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 -#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 -#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 -#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 -#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 -#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ - I40E_AQ_VSI_PVLAN_EMOD_SHIFT) -#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 -#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 -#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 -#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 - u8 pvlan_reserved[3]; - /* ingress egress up sections */ - __le32 ingress_table; /* bitmap, 3 bits per up */ -#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 -#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ - I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) -#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 -#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ - I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) -#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 -#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ - I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) -#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 -#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ - I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) -#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 -#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ - I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) -#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 -#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ - I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) -#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 -#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ - I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) -#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 -#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ - I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) - __le32 egress_table; /* same defines as for ingress table */ - /* cascaded PV section */ - __le16 cas_pv_tag; - u8 cas_pv_flags; -#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 -#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ - I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) -#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 -#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 -#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 -#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 -#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 -#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 - u8 cas_pv_reserved; - /* queue mapping section */ - __le16 mapping_flags; -#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 -#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 - __le16 queue_mapping[16]; -#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 -#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) - __le16 tc_mapping[8]; -#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 -#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ - I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) -#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 -#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ - I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) - /* queueing option section */ - u8 queueing_opt_flags; -#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 -#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 -#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 -#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 -#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 -#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 - u8 queueing_opt_reserved[3]; - /* scheduler section */ - u8 up_enable_bits; - u8 sched_reserved; - /* outer up section */ - __le32 outer_up_table; /* same structure and defines as ingress tbl */ - u8 cmd_reserved[8]; - /* last 32 bytes are written by FW */ - __le16 qs_handle[8]; -#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF - __le16 stat_counter_idx; - __le16 sched_id; - u8 resp_reserved[12]; -}; - -I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); - -/* Add Port Virtualizer (direct 0x0220) - * also used for update PV (direct 0x0221) but only flags are used - * (IS_CTRL_PORT only works on add PV) - */ -struct i40e_aqc_add_update_pv { - __le16 command_flags; -#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 -#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 -#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 -#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 - __le16 uplink_seid; - __le16 connected_seid; - u8 reserved[10]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); - -struct i40e_aqc_add_update_pv_completion { - /* reserved for update; for add also encodes error if rc == ENOSPC */ - __le16 pv_seid; -#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 -#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 -#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 -#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 - u8 reserved[14]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); - -/* Get PV Params (direct 0x0222) - * uses i40e_aqc_switch_seid for the descriptor - */ - -struct i40e_aqc_get_pv_params_completion { - __le16 seid; - __le16 default_stag; - __le16 pv_flags; /* same flags as add_pv */ -#define I40E_AQC_GET_PV_PV_TYPE 0x1 -#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 -#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 - u8 reserved[8]; - __le16 default_port_seid; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); - -/* Add VEB (direct 0x0230) */ -struct i40e_aqc_add_veb { - __le16 uplink_seid; - __le16 downlink_seid; - __le16 veb_flags; -#define I40E_AQC_ADD_VEB_FLOATING 0x1 -#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 -#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ - I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) -#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 -#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 -#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ -#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 - u8 enable_tcs; - u8 reserved[9]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); - -struct i40e_aqc_add_veb_completion { - u8 reserved[6]; - __le16 switch_seid; - /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ - __le16 veb_seid; -#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 -#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 -#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 -#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 - __le16 statistic_index; - __le16 vebs_used; - __le16 vebs_free; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); - -/* Get VEB Parameters (direct 0x0232) - * uses i40e_aqc_switch_seid for the descriptor - */ -struct i40e_aqc_get_veb_parameters_completion { - __le16 seid; - __le16 switch_id; - __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ - __le16 statistic_index; - __le16 vebs_used; - __le16 vebs_free; - u8 reserved[4]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); - -/* Delete Element (direct 0x0243) - * uses the generic i40e_aqc_switch_seid - */ - -/* Add MAC-VLAN (indirect 0x0250) */ - -/* used for the command for most vlan commands */ -struct i40e_aqc_macvlan { - __le16 num_addresses; - __le16 seid[3]; -#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 -#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ - I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) -#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); - -/* indirect data for command and response */ -struct i40e_aqc_add_macvlan_element_data { - u8 mac_addr[6]; - __le16 vlan_tag; - __le16 flags; -#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 -#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 -#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 -#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 -#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 - __le16 queue_number; -#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 -#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ - I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) - /* response section */ - u8 match_method; -#define I40E_AQC_MM_PERFECT_MATCH 0x01 -#define I40E_AQC_MM_HASH_MATCH 0x02 -#define I40E_AQC_MM_ERR_NO_RES 0xFF - u8 reserved1[3]; -}; - -struct i40e_aqc_add_remove_macvlan_completion { - __le16 perfect_mac_used; - __le16 perfect_mac_free; - __le16 unicast_hash_free; - __le16 multicast_hash_free; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); - -/* Remove MAC-VLAN (indirect 0x0251) - * uses i40e_aqc_macvlan for the descriptor - * data points to an array of num_addresses of elements - */ - -struct i40e_aqc_remove_macvlan_element_data { - u8 mac_addr[6]; - __le16 vlan_tag; - u8 flags; -#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 -#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 -#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 -#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 - u8 reserved[3]; - /* reply section */ - u8 error_code; -#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 -#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF - u8 reply_reserved[3]; -}; - -/* Add VLAN (indirect 0x0252) - * Remove VLAN (indirect 0x0253) - * use the generic i40e_aqc_macvlan for the command - */ -struct i40e_aqc_add_remove_vlan_element_data { - __le16 vlan_tag; - u8 vlan_flags; -/* flags for add VLAN */ -#define I40E_AQC_ADD_VLAN_LOCAL 0x1 -#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 -#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) -#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 -#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 -#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 -#define I40E_AQC_VLAN_PTYPE_SHIFT 3 -#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) -#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 -#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 -#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 -#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 -/* flags for remove VLAN */ -#define I40E_AQC_REMOVE_VLAN_ALL 0x1 - u8 reserved; - u8 result; -/* flags for add VLAN */ -#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 -#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE -#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF -/* flags for remove VLAN */ -#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 -#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF - u8 reserved1[3]; -}; - -struct i40e_aqc_add_remove_vlan_completion { - u8 reserved[4]; - __le16 vlans_used; - __le16 vlans_free; - __le32 addr_high; - __le32 addr_low; -}; - -/* Set VSI Promiscuous Modes (direct 0x0254) */ -struct i40e_aqc_set_vsi_promiscuous_modes { - __le16 promiscuous_flags; - __le16 valid_flags; -/* flags used for both fields above */ -#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 -#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 -#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 -#define I40E_AQC_SET_VSI_DEFAULT 0x08 -#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 -#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 - __le16 seid; -#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF - __le16 vlan_tag; -#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF -#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 - u8 reserved[8]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); - -/* Add S/E-tag command (direct 0x0255) - * Uses generic i40e_aqc_add_remove_tag_completion for completion - */ -struct i40e_aqc_add_tag { - __le16 flags; -#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 - __le16 seid; -#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 -#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ - I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) - __le16 tag; - __le16 queue_number; - u8 reserved[8]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); - -struct i40e_aqc_add_remove_tag_completion { - u8 reserved[12]; - __le16 tags_used; - __le16 tags_free; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); - -/* Remove S/E-tag command (direct 0x0256) - * Uses generic i40e_aqc_add_remove_tag_completion for completion - */ -struct i40e_aqc_remove_tag { - __le16 seid; -#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 -#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ - I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) - __le16 tag; - u8 reserved[12]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); - -/* Add multicast E-Tag (direct 0x0257) - * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields - * and no external data - */ -struct i40e_aqc_add_remove_mcast_etag { - __le16 pv_seid; - __le16 etag; - u8 num_unicast_etags; - u8 reserved[3]; - __le32 addr_high; /* address of array of 2-byte s-tags */ - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); - -struct i40e_aqc_add_remove_mcast_etag_completion { - u8 reserved[4]; - __le16 mcast_etags_used; - __le16 mcast_etags_free; - __le32 addr_high; - __le32 addr_low; - -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); - -/* Update S/E-Tag (direct 0x0259) */ -struct i40e_aqc_update_tag { - __le16 seid; -#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 -#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ - I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) - __le16 old_tag; - __le16 new_tag; - u8 reserved[10]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); - -struct i40e_aqc_update_tag_completion { - u8 reserved[12]; - __le16 tags_used; - __le16 tags_free; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); - -/* Add Control Packet filter (direct 0x025A) - * Remove Control Packet filter (direct 0x025B) - * uses the i40e_aqc_add_oveb_cloud, - * and the generic direct completion structure - */ -struct i40e_aqc_add_remove_control_packet_filter { - u8 mac[6]; - __le16 etype; - __le16 flags; -#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 -#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 -#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 -#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 -#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 - __le16 seid; -#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 -#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ - I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) - __le16 queue; - u8 reserved[2]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); - -struct i40e_aqc_add_remove_control_packet_filter_completion { - __le16 mac_etype_used; - __le16 etype_used; - __le16 mac_etype_free; - __le16 etype_free; - u8 reserved[8]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); - -/* Add Cloud filters (indirect 0x025C) - * Remove Cloud filters (indirect 0x025D) - * uses the i40e_aqc_add_remove_cloud_filters, - * and the generic indirect completion structure - */ -struct i40e_aqc_add_remove_cloud_filters { - u8 num_filters; - u8 reserved; - __le16 seid; -#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 -#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ - I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) - u8 big_buffer_flag; -#define I40E_AQC_ADD_CLOUD_CMD_BB 1 - u8 reserved2[3]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); - -struct i40e_aqc_cloud_filters_element_data { - u8 outer_mac[6]; - u8 inner_mac[6]; - __le16 inner_vlan; - union { - struct { - u8 reserved[12]; - u8 data[4]; - } v4; - struct { - u8 data[16]; - } v6; - struct { - __le16 data[8]; - } raw_v6; - } ipaddr; - __le16 flags; -#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 -#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ - I40E_AQC_ADD_CLOUD_FILTER_SHIFT) -/* 0x0000 reserved */ -#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 -/* 0x0002 reserved */ -#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 -#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 -/* 0x0005 reserved */ -#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 -/* 0x0007 reserved */ -/* 0x0008 reserved */ -#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 -#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A -#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B -#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C -/* 0x0010 to 0x0017 is for custom filters */ -#define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ -#define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ -#define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ - -#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 -#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 -#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 -#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 -#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 - -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 - -#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 -#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 -#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 - - __le32 tenant_id; - u8 reserved[4]; - __le16 queue_number; -#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 -#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ - I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) - u8 reserved2[14]; - /* response section */ - u8 allocation_result; -#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 -#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF - u8 response_reserved[7]; -}; - -I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); - -/* i40e_aqc_cloud_filters_element_bb is used when - * I40E_AQC_ADD_CLOUD_CMD_BB flag is set. - */ -struct i40e_aqc_cloud_filters_element_bb { - struct i40e_aqc_cloud_filters_element_data element; - u16 general_fields[32]; -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 -}; - -I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); - -struct i40e_aqc_remove_cloud_filters_completion { - __le16 perfect_ovlan_used; - __le16 perfect_ovlan_free; - __le16 vlan_used; - __le16 vlan_free; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); - -/* Replace filter Command 0x025F - * uses the i40e_aqc_replace_cloud_filters, - * and the generic indirect completion structure - */ -struct i40e_filter_data { - u8 filter_type; - u8 input[3]; -}; - -I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); - -struct i40e_aqc_replace_cloud_filters_cmd { - u8 valid_flags; -#define I40E_AQC_REPLACE_L1_FILTER 0x0 -#define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 -#define I40E_AQC_GET_CLOUD_FILTERS 0x2 -#define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 -#define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 - u8 old_filter_type; - u8 new_filter_type; - u8 tr_bit; - u8 reserved[4]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); - -struct i40e_aqc_replace_cloud_filters_cmd_buf { - u8 data[32]; -/* Filter type INPUT codes*/ -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED BIT(7) - -/* Field Vector offsets */ -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 -/* big FLU */ -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 -/* big FLU */ -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 - -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 - struct i40e_filter_data filters[8]; -}; - -I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); - -/* Add Mirror Rule (indirect or direct 0x0260) - * Delete Mirror Rule (indirect or direct 0x0261) - * note: some rule types (4,5) do not use an external buffer. - * take care to set the flags correctly. - */ -struct i40e_aqc_add_delete_mirror_rule { - __le16 seid; - __le16 rule_type; -#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 -#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ - I40E_AQC_MIRROR_RULE_TYPE_SHIFT) -#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 -#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 -#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 -#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 -#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 - __le16 num_entries; - __le16 destination; /* VSI for add, rule id for delete */ - __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); - -struct i40e_aqc_add_delete_mirror_rule_completion { - u8 reserved[2]; - __le16 rule_id; /* only used on add */ - __le16 mirror_rules_used; - __le16 mirror_rules_free; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); - -/* Dynamic Device Personalization */ -struct i40e_aqc_write_personalization_profile { - u8 flags; - u8 reserved[3]; - __le32 profile_track_id; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); - -struct i40e_aqc_write_ddp_resp { - __le32 error_offset; - __le32 error_info; - __le32 addr_high; - __le32 addr_low; -}; - -struct i40e_aqc_get_applied_profiles { - u8 flags; -#define I40E_AQC_GET_DDP_GET_CONF 0x1 -#define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2 - u8 rsv[3]; - __le32 reserved; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); - -/* DCB 0x03xx*/ - -/* PFC Ignore (direct 0x0301) - * the command and response use the same descriptor structure - */ -struct i40e_aqc_pfc_ignore { - u8 tc_bitmap; - u8 command_flags; /* unused on response */ -#define I40E_AQC_PFC_IGNORE_SET 0x80 -#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 - u8 reserved[14]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); - -/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure - * with no parameters - */ - -/* TX scheduler 0x04xx */ - -/* Almost all the indirect commands use - * this generic struct to pass the SEID in param0 - */ -struct i40e_aqc_tx_sched_ind { - __le16 vsi_seid; - u8 reserved[6]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); - -/* Several commands respond with a set of queue set handles */ -struct i40e_aqc_qs_handles_resp { - __le16 qs_handles[8]; -}; - -/* Configure VSI BW limits (direct 0x0400) */ -struct i40e_aqc_configure_vsi_bw_limit { - __le16 vsi_seid; - u8 reserved[2]; - __le16 credit; - u8 reserved1[2]; - u8 max_credit; /* 0-3, limit = 2^max */ - u8 reserved2[7]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); - -/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) - * responds with i40e_aqc_qs_handles_resp - */ -struct i40e_aqc_configure_vsi_ets_sla_bw_data { - u8 tc_valid_bits; - u8 reserved[15]; - __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ - - /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ - __le16 tc_bw_max[2]; - u8 reserved1[28]; -}; - -I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); - -/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) - * responds with i40e_aqc_qs_handles_resp - */ -struct i40e_aqc_configure_vsi_tc_bw_data { - u8 tc_valid_bits; - u8 reserved[3]; - u8 tc_bw_credits[8]; - u8 reserved1[4]; - __le16 qs_handles[8]; -}; - -I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); - -/* Query vsi bw configuration (indirect 0x0408) */ -struct i40e_aqc_query_vsi_bw_config_resp { - u8 tc_valid_bits; - u8 tc_suspended_bits; - u8 reserved[14]; - __le16 qs_handles[8]; - u8 reserved1[4]; - __le16 port_bw_limit; - u8 reserved2[2]; - u8 max_bw; /* 0-3, limit = 2^max */ - u8 reserved3[23]; -}; - -I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); - -/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ -struct i40e_aqc_query_vsi_ets_sla_config_resp { - u8 tc_valid_bits; - u8 reserved[3]; - u8 share_credits[8]; - __le16 credits[8]; - - /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ - __le16 tc_bw_max[2]; -}; - -I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); - -/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ -struct i40e_aqc_configure_switching_comp_bw_limit { - __le16 seid; - u8 reserved[2]; - __le16 credit; - u8 reserved1[2]; - u8 max_bw; /* 0-3, limit = 2^max */ - u8 reserved2[7]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); - -/* Enable Physical Port ETS (indirect 0x0413) - * Modify Physical Port ETS (indirect 0x0414) - * Disable Physical Port ETS (indirect 0x0415) - */ -struct i40e_aqc_configure_switching_comp_ets_data { - u8 reserved[4]; - u8 tc_valid_bits; - u8 seepage; -#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 - u8 tc_strict_priority_flags; - u8 reserved1[17]; - u8 tc_bw_share_credits[8]; - u8 reserved2[96]; -}; - -I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); - -/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ -struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { - u8 tc_valid_bits; - u8 reserved[15]; - __le16 tc_bw_credit[8]; - - /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ - __le16 tc_bw_max[2]; - u8 reserved1[28]; -}; - -I40E_CHECK_STRUCT_LEN(0x40, - i40e_aqc_configure_switching_comp_ets_bw_limit_data); - -/* Configure Switching Component Bandwidth Allocation per Tc - * (indirect 0x0417) - */ -struct i40e_aqc_configure_switching_comp_bw_config_data { - u8 tc_valid_bits; - u8 reserved[2]; - u8 absolute_credits; /* bool */ - u8 tc_bw_share_credits[8]; - u8 reserved1[20]; -}; - -I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); - -/* Query Switching Component Configuration (indirect 0x0418) */ -struct i40e_aqc_query_switching_comp_ets_config_resp { - u8 tc_valid_bits; - u8 reserved[35]; - __le16 port_bw_limit; - u8 reserved1[2]; - u8 tc_bw_max; /* 0-3, limit = 2^max */ - u8 reserved2[23]; -}; - -I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); - -/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ -struct i40e_aqc_query_port_ets_config_resp { - u8 reserved[4]; - u8 tc_valid_bits; - u8 reserved1; - u8 tc_strict_priority_bits; - u8 reserved2; - u8 tc_bw_share_credits[8]; - __le16 tc_bw_limits[8]; - - /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ - __le16 tc_bw_max[2]; - u8 reserved3[32]; -}; - -I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); - -/* Query Switching Component Bandwidth Allocation per Traffic Type - * (indirect 0x041A) - */ -struct i40e_aqc_query_switching_comp_bw_config_resp { - u8 tc_valid_bits; - u8 reserved[2]; - u8 absolute_credits_enable; /* bool */ - u8 tc_bw_share_credits[8]; - __le16 tc_bw_limits[8]; - - /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ - __le16 tc_bw_max[2]; -}; - -I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); - -/* Suspend/resume port TX traffic - * (direct 0x041B and 0x041C) uses the generic SEID struct - */ - -/* Configure partition BW - * (indirect 0x041D) - */ -struct i40e_aqc_configure_partition_bw_data { - __le16 pf_valid_bits; - u8 min_bw[16]; /* guaranteed bandwidth */ - u8 max_bw[16]; /* bandwidth limit */ -}; - -I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); - -/* Get and set the active HMC resource profile and status. - * (direct 0x0500) and (direct 0x0501) - */ -struct i40e_aq_get_set_hmc_resource_profile { - u8 pm_profile; - u8 pe_vf_enabled; - u8 reserved[14]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); - -enum i40e_aq_hmc_profile { - /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ - I40E_HMC_PROFILE_DEFAULT = 1, - I40E_HMC_PROFILE_FAVOR_VF = 2, - I40E_HMC_PROFILE_EQUAL = 3, -}; - -/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ - -/* set in param0 for get phy abilities to report qualified modules */ -#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 -#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 - -enum i40e_aq_phy_type { - I40E_PHY_TYPE_SGMII = 0x0, - I40E_PHY_TYPE_1000BASE_KX = 0x1, - I40E_PHY_TYPE_10GBASE_KX4 = 0x2, - I40E_PHY_TYPE_10GBASE_KR = 0x3, - I40E_PHY_TYPE_40GBASE_KR4 = 0x4, - I40E_PHY_TYPE_XAUI = 0x5, - I40E_PHY_TYPE_XFI = 0x6, - I40E_PHY_TYPE_SFI = 0x7, - I40E_PHY_TYPE_XLAUI = 0x8, - I40E_PHY_TYPE_XLPPI = 0x9, - I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, - I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, - I40E_PHY_TYPE_10GBASE_AOC = 0xC, - I40E_PHY_TYPE_40GBASE_AOC = 0xD, - I40E_PHY_TYPE_UNRECOGNIZED = 0xE, - I40E_PHY_TYPE_UNSUPPORTED = 0xF, - I40E_PHY_TYPE_100BASE_TX = 0x11, - I40E_PHY_TYPE_1000BASE_T = 0x12, - I40E_PHY_TYPE_10GBASE_T = 0x13, - I40E_PHY_TYPE_10GBASE_SR = 0x14, - I40E_PHY_TYPE_10GBASE_LR = 0x15, - I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, - I40E_PHY_TYPE_10GBASE_CR1 = 0x17, - I40E_PHY_TYPE_40GBASE_CR4 = 0x18, - I40E_PHY_TYPE_40GBASE_SR4 = 0x19, - I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, - I40E_PHY_TYPE_1000BASE_SX = 0x1B, - I40E_PHY_TYPE_1000BASE_LX = 0x1C, - I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, - I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, - I40E_PHY_TYPE_25GBASE_KR = 0x1F, - I40E_PHY_TYPE_25GBASE_CR = 0x20, - I40E_PHY_TYPE_25GBASE_SR = 0x21, - I40E_PHY_TYPE_25GBASE_LR = 0x22, - I40E_PHY_TYPE_25GBASE_AOC = 0x23, - I40E_PHY_TYPE_25GBASE_ACC = 0x24, - I40E_PHY_TYPE_MAX, - I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, - I40E_PHY_TYPE_EMPTY = 0xFE, - I40E_PHY_TYPE_DEFAULT = 0xFF, -}; - -#define I40E_LINK_SPEED_100MB_SHIFT 0x1 -#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 -#define I40E_LINK_SPEED_10GB_SHIFT 0x3 -#define I40E_LINK_SPEED_40GB_SHIFT 0x4 -#define I40E_LINK_SPEED_20GB_SHIFT 0x5 -#define I40E_LINK_SPEED_25GB_SHIFT 0x6 - -enum i40e_aq_link_speed { - I40E_LINK_SPEED_UNKNOWN = 0, - I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), - I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), - I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), - I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), - I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), - I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), -}; - -struct i40e_aqc_module_desc { - u8 oui[3]; - u8 reserved1; - u8 part_number[16]; - u8 revision[4]; - u8 reserved2[8]; -}; - -I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); - -struct i40e_aq_get_phy_abilities_resp { - __le32 phy_type; /* bitmap using the above enum for offsets */ - u8 link_speed; /* bitmap using the above enum bit patterns */ - u8 abilities; -#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 -#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 -#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 -#define I40E_AQ_PHY_LINK_ENABLED 0x08 -#define I40E_AQ_PHY_AN_ENABLED 0x10 -#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 -#define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 -#define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 - __le16 eee_capability; -#define I40E_AQ_EEE_100BASE_TX 0x0002 -#define I40E_AQ_EEE_1000BASE_T 0x0004 -#define I40E_AQ_EEE_10GBASE_T 0x0008 -#define I40E_AQ_EEE_1000BASE_KX 0x0010 -#define I40E_AQ_EEE_10GBASE_KX4 0x0020 -#define I40E_AQ_EEE_10GBASE_KR 0x0040 - __le32 eeer_val; - u8 d3_lpan; -#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 - u8 phy_type_ext; -#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 -#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 -#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 -#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 -#define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 -#define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 - u8 fec_cfg_curr_mod_ext_info; -#define I40E_AQ_ENABLE_FEC_KR 0x01 -#define I40E_AQ_ENABLE_FEC_RS 0x02 -#define I40E_AQ_REQUEST_FEC_KR 0x04 -#define I40E_AQ_REQUEST_FEC_RS 0x08 -#define I40E_AQ_ENABLE_FEC_AUTO 0x10 -#define I40E_AQ_FEC -#define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 -#define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 - - u8 ext_comp_code; - u8 phy_id[4]; - u8 module_type[3]; - u8 qualified_module_count; -#define I40E_AQ_PHY_MAX_QMS 16 - struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; -}; - -I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); - -/* Set PHY Config (direct 0x0601) */ -struct i40e_aq_set_phy_config { /* same bits as above in all */ - __le32 phy_type; - u8 link_speed; - u8 abilities; -/* bits 0-2 use the values from get_phy_abilities_resp */ -#define I40E_AQ_PHY_ENABLE_LINK 0x08 -#define I40E_AQ_PHY_ENABLE_AN 0x10 -#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 - __le16 eee_capability; - __le32 eeer; - u8 low_power_ctrl; - u8 phy_type_ext; -#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 -#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 -#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 -#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 - u8 fec_config; -#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) -#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) -#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) -#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) -#define I40E_AQ_SET_FEC_AUTO BIT(4) -#define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 -#define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) - u8 reserved; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); - -/* Set MAC Config command data structure (direct 0x0603) */ -struct i40e_aq_set_mac_config { - __le16 max_frame_size; - u8 params; -#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 -#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 -#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 -#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 -#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF -#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 -#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 -#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 -#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 -#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 -#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 -#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 -#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 -#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 - u8 tx_timer_priority; /* bitmap */ - __le16 tx_timer_value; - __le16 fc_refresh_threshold; - u8 reserved[8]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); - -/* Restart Auto-Negotiation (direct 0x605) */ -struct i40e_aqc_set_link_restart_an { - u8 command; -#define I40E_AQ_PHY_RESTART_AN 0x02 -#define I40E_AQ_PHY_LINK_ENABLE 0x04 - u8 reserved[15]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); - -/* Get Link Status cmd & response data structure (direct 0x0607) */ -struct i40e_aqc_get_link_status { - __le16 command_flags; /* only field set on command */ -#define I40E_AQ_LSE_MASK 0x3 -#define I40E_AQ_LSE_NOP 0x0 -#define I40E_AQ_LSE_DISABLE 0x2 -#define I40E_AQ_LSE_ENABLE 0x3 -/* only response uses this flag */ -#define I40E_AQ_LSE_IS_ENABLED 0x1 - u8 phy_type; /* i40e_aq_phy_type */ - u8 link_speed; /* i40e_aq_link_speed */ - u8 link_info; -#define I40E_AQ_LINK_UP 0x01 /* obsolete */ -#define I40E_AQ_LINK_UP_FUNCTION 0x01 -#define I40E_AQ_LINK_FAULT 0x02 -#define I40E_AQ_LINK_FAULT_TX 0x04 -#define I40E_AQ_LINK_FAULT_RX 0x08 -#define I40E_AQ_LINK_FAULT_REMOTE 0x10 -#define I40E_AQ_LINK_UP_PORT 0x20 -#define I40E_AQ_MEDIA_AVAILABLE 0x40 -#define I40E_AQ_SIGNAL_DETECT 0x80 - u8 an_info; -#define I40E_AQ_AN_COMPLETED 0x01 -#define I40E_AQ_LP_AN_ABILITY 0x02 -#define I40E_AQ_PD_FAULT 0x04 -#define I40E_AQ_FEC_EN 0x08 -#define I40E_AQ_PHY_LOW_POWER 0x10 -#define I40E_AQ_LINK_PAUSE_TX 0x20 -#define I40E_AQ_LINK_PAUSE_RX 0x40 -#define I40E_AQ_QUALIFIED_MODULE 0x80 - u8 ext_info; -#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 -#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 -#define I40E_AQ_LINK_TX_SHIFT 0x02 -#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) -#define I40E_AQ_LINK_TX_ACTIVE 0x00 -#define I40E_AQ_LINK_TX_DRAINED 0x01 -#define I40E_AQ_LINK_TX_FLUSHED 0x03 -#define I40E_AQ_LINK_FORCED_40G 0x10 -/* 25G Error Codes */ -#define I40E_AQ_25G_NO_ERR 0X00 -#define I40E_AQ_25G_NOT_PRESENT 0X01 -#define I40E_AQ_25G_NVM_CRC_ERR 0X02 -#define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 -#define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 -#define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 - u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ -/* Since firmware API 1.7 loopback field keeps power class info as well */ -#define I40E_AQ_LOOPBACK_MASK 0x07 -#define I40E_AQ_PWR_CLASS_SHIFT_LB 6 -#define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) - __le16 max_frame_size; - u8 config; -#define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 -#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 -#define I40E_AQ_CONFIG_CRC_ENA 0x04 -#define I40E_AQ_CONFIG_PACING_MASK 0x78 - union { - struct { - u8 power_desc; -#define I40E_AQ_LINK_POWER_CLASS_1 0x00 -#define I40E_AQ_LINK_POWER_CLASS_2 0x01 -#define I40E_AQ_LINK_POWER_CLASS_3 0x02 -#define I40E_AQ_LINK_POWER_CLASS_4 0x03 -#define I40E_AQ_PWR_CLASS_MASK 0x03 - u8 reserved[4]; - }; - struct { - u8 link_type[4]; - u8 link_type_ext; - }; - }; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); - -/* Set event mask command (direct 0x613) */ -struct i40e_aqc_set_phy_int_mask { - u8 reserved[8]; - __le16 event_mask; -#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 -#define I40E_AQ_EVENT_MEDIA_NA 0x0004 -#define I40E_AQ_EVENT_LINK_FAULT 0x0008 -#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 -#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 -#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 -#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 -#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 -#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 - u8 reserved1[6]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); - -/* Get Local AN advt register (direct 0x0614) - * Set Local AN advt register (direct 0x0615) - * Get Link Partner AN advt register (direct 0x0616) - */ -struct i40e_aqc_an_advt_reg { - __le32 local_an_reg0; - __le16 local_an_reg1; - u8 reserved[10]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); - -/* Set Loopback mode (0x0618) */ -struct i40e_aqc_set_lb_mode { - __le16 lb_mode; -#define I40E_AQ_LB_PHY_LOCAL 0x01 -#define I40E_AQ_LB_PHY_REMOTE 0x02 -#define I40E_AQ_LB_MAC_LOCAL 0x04 - u8 reserved[14]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); - -/* Set PHY Debug command (0x0622) */ -struct i40e_aqc_set_phy_debug { - u8 command_flags; -#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 -#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 -#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ - I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) -#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 -#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 -#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 -#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 - u8 reserved[15]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); - -enum i40e_aq_phy_reg_type { - I40E_AQC_PHY_REG_INTERNAL = 0x1, - I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, - I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 -}; - -/* Run PHY Activity (0x0626) */ -struct i40e_aqc_run_phy_activity { - __le16 activity_id; - u8 flags; - u8 reserved1; - __le32 control; - __le32 data; - u8 reserved2[4]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); - -/* Set PHY Register command (0x0628) */ -/* Get PHY Register command (0x0629) */ -struct i40e_aqc_phy_register_access { - u8 phy_interface; -#define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 -#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 -#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 - u8 dev_address; - u8 reserved1[2]; - __le32 reg_address; - __le32 reg_value; - u8 reserved2[4]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); - -/* NVM Read command (indirect 0x0701) - * NVM Erase commands (direct 0x0702) - * NVM Update commands (indirect 0x0703) - */ -struct i40e_aqc_nvm_update { - u8 command_flags; -#define I40E_AQ_NVM_LAST_CMD 0x01 -#define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 -#define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 -#define I40E_AQ_NVM_FLASH_ONLY 0x80 -#define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 -#define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 -#define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 -#define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 - u8 module_pointer; - __le16 length; - __le32 offset; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); - -/* NVM Config Read (indirect 0x0704) */ -struct i40e_aqc_nvm_config_read { - __le16 cmd_flags; -#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 -#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 -#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 - __le16 element_count; - __le16 element_id; /* Feature/field ID */ - __le16 element_id_msw; /* MSWord of field ID */ - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); - -/* NVM Config Write (indirect 0x0705) */ -struct i40e_aqc_nvm_config_write { - __le16 cmd_flags; - __le16 element_count; - u8 reserved[4]; - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); - -/* Used for 0x0704 as well as for 0x0705 commands */ -#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 -#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ - BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) -#define I40E_AQ_ANVM_FEATURE 0 -#define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) -struct i40e_aqc_nvm_config_data_feature { - __le16 feature_id; -#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 -#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 -#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 - __le16 feature_options; - __le16 feature_selection; -}; - -I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); - -struct i40e_aqc_nvm_config_data_immediate_field { - __le32 field_id; - __le32 field_value; - __le16 field_options; - __le16 reserved; -}; - -I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); - -/* OEM Post Update (indirect 0x0720) - * no command data struct used - */ - struct i40e_aqc_nvm_oem_post_update { -#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 - u8 sel_data; - u8 reserved[7]; -}; - -I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); - -struct i40e_aqc_nvm_oem_post_update_buffer { - u8 str_len; - u8 dev_addr; - __le16 eeprom_addr; - u8 data[36]; -}; - -I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); - -/* Thermal Sensor (indirect 0x0721) - * read or set thermal sensor configs and values - * takes a sensor and command specific data buffer, not detailed here - */ -struct i40e_aqc_thermal_sensor { - u8 sensor_action; -#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 -#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 -#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 - u8 reserved[7]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); - -/* Send to PF command (indirect 0x0801) id is only used by PF - * Send to VF command (indirect 0x0802) id is only used by PF - * Send to Peer PF command (indirect 0x0803) - */ -struct i40e_aqc_pf_vf_message { - __le32 id; - u8 reserved[4]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); - -/* Alternate structure */ - -/* Direct write (direct 0x0900) - * Direct read (direct 0x0902) - */ -struct i40e_aqc_alternate_write { - __le32 address0; - __le32 data0; - __le32 address1; - __le32 data1; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); - -/* Indirect write (indirect 0x0901) - * Indirect read (indirect 0x0903) - */ - -struct i40e_aqc_alternate_ind_write { - __le32 address; - __le32 length; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); - -/* Done alternate write (direct 0x0904) - * uses i40e_aq_desc - */ -struct i40e_aqc_alternate_write_done { - __le16 cmd_flags; -#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 -#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 -#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 -#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 - u8 reserved[14]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); - -/* Set OEM mode (direct 0x0905) */ -struct i40e_aqc_alternate_set_mode { - __le32 mode; -#define I40E_AQ_ALTERNATE_MODE_NONE 0 -#define I40E_AQ_ALTERNATE_MODE_OEM 1 - u8 reserved[12]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); - -/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ - -/* async events 0x10xx */ - -/* Lan Queue Overflow Event (direct, 0x1001) */ -struct i40e_aqc_lan_overflow { - __le32 prtdcb_rupto; - __le32 otx_ctl; - u8 reserved[8]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); - -/* Get LLDP MIB (indirect 0x0A00) */ -struct i40e_aqc_lldp_get_mib { - u8 type; - u8 reserved1; -#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 -#define I40E_AQ_LLDP_MIB_LOCAL 0x0 -#define I40E_AQ_LLDP_MIB_REMOTE 0x1 -#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 -#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC -#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 -#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 -#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 -#define I40E_AQ_LLDP_TX_SHIFT 0x4 -#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) -/* TX pause flags use I40E_AQ_LINK_TX_* above */ - __le16 local_len; - __le16 remote_len; - u8 reserved2[2]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); - -/* Configure LLDP MIB Change Event (direct 0x0A01) - * also used for the event (with type in the command field) - */ -struct i40e_aqc_lldp_update_mib { - u8 command; -#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 -#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 - u8 reserved[7]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); - -/* Add LLDP TLV (indirect 0x0A02) - * Delete LLDP TLV (indirect 0x0A04) - */ -struct i40e_aqc_lldp_add_tlv { - u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ - u8 reserved1[1]; - __le16 len; - u8 reserved2[4]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); - -/* Update LLDP TLV (indirect 0x0A03) */ -struct i40e_aqc_lldp_update_tlv { - u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ - u8 reserved; - __le16 old_len; - __le16 new_offset; - __le16 new_len; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); - -/* Stop LLDP (direct 0x0A05) */ -struct i40e_aqc_lldp_stop { - u8 command; -#define I40E_AQ_LLDP_AGENT_STOP 0x0 -#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 - u8 reserved[15]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); - -/* Start LLDP (direct 0x0A06) */ - -struct i40e_aqc_lldp_start { - u8 command; -#define I40E_AQ_LLDP_AGENT_START 0x1 - u8 reserved[15]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); - -/* Set DCB (direct 0x0303) */ -struct i40e_aqc_set_dcb_parameters { - u8 command; -#define I40E_AQ_DCB_SET_AGENT 0x1 -#define I40E_DCB_VALID 0x1 - u8 valid_flags; - u8 reserved[14]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); - -/* Apply MIB changes (0x0A07) - * uses the generic struc as it contains no data - */ - -/* Add Udp Tunnel command and completion (direct 0x0B00) */ -struct i40e_aqc_add_udp_tunnel { - __le16 udp_port; - u8 reserved0[3]; - u8 protocol_type; -#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 -#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 -#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 -#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 - u8 reserved1[10]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); - -struct i40e_aqc_add_udp_tunnel_completion { - __le16 udp_port; - u8 filter_entry_index; - u8 multiple_pfs; -#define I40E_AQC_SINGLE_PF 0x0 -#define I40E_AQC_MULTIPLE_PFS 0x1 - u8 total_filters; - u8 reserved[11]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); - -/* remove UDP Tunnel command (0x0B01) */ -struct i40e_aqc_remove_udp_tunnel { - u8 reserved[2]; - u8 index; /* 0 to 15 */ - u8 reserved2[13]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); - -struct i40e_aqc_del_udp_tunnel_completion { - __le16 udp_port; - u8 index; /* 0 to 15 */ - u8 multiple_pfs; - u8 total_filters_used; - u8 reserved1[11]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); - -struct i40e_aqc_get_set_rss_key { -#define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) -#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 -#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ - I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) - __le16 vsi_id; - u8 reserved[6]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); - -struct i40e_aqc_get_set_rss_key_data { - u8 standard_rss_key[0x28]; - u8 extended_hash_key[0xc]; -}; - -I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); - -struct i40e_aqc_get_set_rss_lut { -#define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) -#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 -#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ - I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) - __le16 vsi_id; -#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 -#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \ - BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) - -#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 -#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 - __le16 flags; - u8 reserved[4]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); - -/* tunnel key structure 0x0B10 */ - -struct i40e_aqc_tunnel_key_structure_A0 { - __le16 key1_off; - __le16 key1_len; - __le16 key2_off; - __le16 key2_len; - __le16 flags; -#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 -/* response flags */ -#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 -#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 -#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 - u8 resreved[6]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0); - -struct i40e_aqc_tunnel_key_structure { - u8 key1_off; - u8 key2_off; - u8 key1_len; /* 0 to 15 */ - u8 key2_len; /* 0 to 15 */ - u8 flags; -#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 -/* response flags */ -#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 -#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 -#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 - u8 network_key_index; -#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 -#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 -#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 -#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 - u8 reserved[10]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); - -/* OEM mode commands (direct 0xFE0x) */ -struct i40e_aqc_oem_param_change { - __le32 param_type; -#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 -#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 -#define I40E_AQ_OEM_PARAM_MAC 2 - __le32 param_value1; - __le16 param_value2; - u8 reserved[6]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); - -struct i40e_aqc_oem_state_change { - __le32 state; -#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 -#define I40E_AQ_OEM_STATE_LINK_UP 0x1 - u8 reserved[12]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); - -/* Initialize OCSD (0xFE02, direct) */ -struct i40e_aqc_opc_oem_ocsd_initialize { - u8 type_status; - u8 reserved1[3]; - __le32 ocsd_memory_block_addr_high; - __le32 ocsd_memory_block_addr_low; - __le32 requested_update_interval; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); - -/* Initialize OCBB (0xFE03, direct) */ -struct i40e_aqc_opc_oem_ocbb_initialize { - u8 type_status; - u8 reserved1[3]; - __le32 ocbb_memory_block_addr_high; - __le32 ocbb_memory_block_addr_low; - u8 reserved2[4]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); - -/* debug commands */ - -/* get device id (0xFF00) uses the generic structure */ - -/* set test more (0xFF01, internal) */ - -struct i40e_acq_set_test_mode { - u8 mode; -#define I40E_AQ_TEST_PARTIAL 0 -#define I40E_AQ_TEST_FULL 1 -#define I40E_AQ_TEST_NVM 2 - u8 reserved[3]; - u8 command; -#define I40E_AQ_TEST_OPEN 0 -#define I40E_AQ_TEST_CLOSE 1 -#define I40E_AQ_TEST_INC 2 - u8 reserved2[3]; - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); - -/* Debug Read Register command (0xFF03) - * Debug Write Register command (0xFF04) - */ -struct i40e_aqc_debug_reg_read_write { - __le32 reserved; - __le32 address; - __le32 value_high; - __le32 value_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); - -/* Scatter/gather Reg Read (indirect 0xFF05) - * Scatter/gather Reg Write (indirect 0xFF06) - */ - -/* i40e_aq_desc is used for the command */ -struct i40e_aqc_debug_reg_sg_element_data { - __le32 address; - __le32 value; -}; - -/* Debug Modify register (direct 0xFF07) */ -struct i40e_aqc_debug_modify_reg { - __le32 address; - __le32 value; - __le32 clear_mask; - __le32 set_mask; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); - -/* dump internal data (0xFF08, indirect) */ - -#define I40E_AQ_CLUSTER_ID_AUX 0 -#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 -#define I40E_AQ_CLUSTER_ID_TXSCHED 2 -#define I40E_AQ_CLUSTER_ID_HMC 3 -#define I40E_AQ_CLUSTER_ID_MAC0 4 -#define I40E_AQ_CLUSTER_ID_MAC1 5 -#define I40E_AQ_CLUSTER_ID_MAC2 6 -#define I40E_AQ_CLUSTER_ID_MAC3 7 -#define I40E_AQ_CLUSTER_ID_DCB 8 -#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 -#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 -#define I40E_AQ_CLUSTER_ID_ALTRAM 11 - -struct i40e_aqc_debug_dump_internals { - u8 cluster_id; - u8 table_id; - __le16 data_size; - __le32 idx; - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); - -struct i40e_aqc_debug_modify_internals { - u8 cluster_id; - u8 cluster_specific_params[7]; - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); - -#endif /* _I40E_ADMINQ_CMD_H_ */ diff --git a/drivers/net/ethernet/intel/i40evf/i40e_hmc.h b/drivers/net/ethernet/intel/i40evf/i40e_hmc.h deleted file mode 100644 index 1c78de838857be788669cc6873984d0ac1cd49d5..0000000000000000000000000000000000000000 --- a/drivers/net/ethernet/intel/i40evf/i40e_hmc.h +++ /dev/null @@ -1,215 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright(c) 2013 - 2018 Intel Corporation. */ - -#ifndef _I40E_HMC_H_ -#define _I40E_HMC_H_ - -#define I40E_HMC_MAX_BP_COUNT 512 - -/* forward-declare the HW struct for the compiler */ -struct i40e_hw; - -#define I40E_HMC_INFO_SIGNATURE 0x484D5347 /* HMSG */ -#define I40E_HMC_PD_CNT_IN_SD 512 -#define I40E_HMC_DIRECT_BP_SIZE 0x200000 /* 2M */ -#define I40E_HMC_PAGED_BP_SIZE 4096 -#define I40E_HMC_PD_BP_BUF_ALIGNMENT 4096 -#define I40E_FIRST_VF_FPM_ID 16 - -struct i40e_hmc_obj_info { - u64 base; /* base addr in FPM */ - u32 max_cnt; /* max count available for this hmc func */ - u32 cnt; /* count of objects driver actually wants to create */ - u64 size; /* size in bytes of one object */ -}; - -enum i40e_sd_entry_type { - I40E_SD_TYPE_INVALID = 0, - I40E_SD_TYPE_PAGED = 1, - I40E_SD_TYPE_DIRECT = 2 -}; - -struct i40e_hmc_bp { - enum i40e_sd_entry_type entry_type; - struct i40e_dma_mem addr; /* populate to be used by hw */ - u32 sd_pd_index; - u32 ref_cnt; -}; - -struct i40e_hmc_pd_entry { - struct i40e_hmc_bp bp; - u32 sd_index; - bool rsrc_pg; - bool valid; -}; - -struct i40e_hmc_pd_table { - struct i40e_dma_mem pd_page_addr; /* populate to be used by hw */ - struct i40e_hmc_pd_entry *pd_entry; /* [512] for sw book keeping */ - struct i40e_virt_mem pd_entry_virt_mem; /* virt mem for pd_entry */ - - u32 ref_cnt; - u32 sd_index; -}; - -struct i40e_hmc_sd_entry { - enum i40e_sd_entry_type entry_type; - bool valid; - - union { - struct i40e_hmc_pd_table pd_table; - struct i40e_hmc_bp bp; - } u; -}; - -struct i40e_hmc_sd_table { - struct i40e_virt_mem addr; /* used to track sd_entry allocations */ - u32 sd_cnt; - u32 ref_cnt; - struct i40e_hmc_sd_entry *sd_entry; /* (sd_cnt*512) entries max */ -}; - -struct i40e_hmc_info { - u32 signature; - /* equals to pci func num for PF and dynamically allocated for VFs */ - u8 hmc_fn_id; - u16 first_sd_index; /* index of the first available SD */ - - /* hmc objects */ - struct i40e_hmc_obj_info *hmc_obj; - struct i40e_virt_mem hmc_obj_virt_mem; - struct i40e_hmc_sd_table sd_table; -}; - -#define I40E_INC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt++) -#define I40E_INC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt++) -#define I40E_INC_BP_REFCNT(bp) ((bp)->ref_cnt++) - -#define I40E_DEC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt--) -#define I40E_DEC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt--) -#define I40E_DEC_BP_REFCNT(bp) ((bp)->ref_cnt--) - -/** - * I40E_SET_PF_SD_ENTRY - marks the sd entry as valid in the hardware - * @hw: pointer to our hw struct - * @pa: pointer to physical address - * @sd_index: segment descriptor index - * @type: if sd entry is direct or paged - **/ -#define I40E_SET_PF_SD_ENTRY(hw, pa, sd_index, type) \ -{ \ - u32 val1, val2, val3; \ - val1 = (u32)(upper_32_bits(pa)); \ - val2 = (u32)(pa) | (I40E_HMC_MAX_BP_COUNT << \ - I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \ - ((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \ - I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) | \ - BIT(I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \ - val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \ - wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \ - wr32((hw), I40E_PFHMC_SDDATALOW, val2); \ - wr32((hw), I40E_PFHMC_SDCMD, val3); \ -} - -/** - * I40E_CLEAR_PF_SD_ENTRY - marks the sd entry as invalid in the hardware - * @hw: pointer to our hw struct - * @sd_index: segment descriptor index - * @type: if sd entry is direct or paged - **/ -#define I40E_CLEAR_PF_SD_ENTRY(hw, sd_index, type) \ -{ \ - u32 val2, val3; \ - val2 = (I40E_HMC_MAX_BP_COUNT << \ - I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \ - ((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \ - I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT); \ - val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \ - wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \ - wr32((hw), I40E_PFHMC_SDDATALOW, val2); \ - wr32((hw), I40E_PFHMC_SDCMD, val3); \ -} - -/** - * I40E_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware - * @hw: pointer to our hw struct - * @sd_idx: segment descriptor index - * @pd_idx: page descriptor index - **/ -#define I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx) \ - wr32((hw), I40E_PFHMC_PDINV, \ - (((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) | \ - ((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT))) - -/** - * I40E_FIND_SD_INDEX_LIMIT - finds segment descriptor index limit - * @hmc_info: pointer to the HMC configuration information structure - * @type: type of HMC resources we're searching - * @index: starting index for the object - * @cnt: number of objects we're trying to create - * @sd_idx: pointer to return index of the segment descriptor in question - * @sd_limit: pointer to return the maximum number of segment descriptors - * - * This function calculates the segment descriptor index and index limit - * for the resource defined by i40e_hmc_rsrc_type. - **/ -#define I40E_FIND_SD_INDEX_LIMIT(hmc_info, type, index, cnt, sd_idx, sd_limit)\ -{ \ - u64 fpm_addr, fpm_limit; \ - fpm_addr = (hmc_info)->hmc_obj[(type)].base + \ - (hmc_info)->hmc_obj[(type)].size * (index); \ - fpm_limit = fpm_addr + (hmc_info)->hmc_obj[(type)].size * (cnt);\ - *(sd_idx) = (u32)(fpm_addr / I40E_HMC_DIRECT_BP_SIZE); \ - *(sd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_DIRECT_BP_SIZE); \ - /* add one more to the limit to correct our range */ \ - *(sd_limit) += 1; \ -} - -/** - * I40E_FIND_PD_INDEX_LIMIT - finds page descriptor index limit - * @hmc_info: pointer to the HMC configuration information struct - * @type: HMC resource type we're examining - * @idx: starting index for the object - * @cnt: number of objects we're trying to create - * @pd_index: pointer to return page descriptor index - * @pd_limit: pointer to return page descriptor index limit - * - * Calculates the page descriptor index and index limit for the resource - * defined by i40e_hmc_rsrc_type. - **/ -#define I40E_FIND_PD_INDEX_LIMIT(hmc_info, type, idx, cnt, pd_index, pd_limit)\ -{ \ - u64 fpm_adr, fpm_limit; \ - fpm_adr = (hmc_info)->hmc_obj[(type)].base + \ - (hmc_info)->hmc_obj[(type)].size * (idx); \ - fpm_limit = fpm_adr + (hmc_info)->hmc_obj[(type)].size * (cnt); \ - *(pd_index) = (u32)(fpm_adr / I40E_HMC_PAGED_BP_SIZE); \ - *(pd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_PAGED_BP_SIZE); \ - /* add one more to the limit to correct our range */ \ - *(pd_limit) += 1; \ -} -i40e_status i40e_add_sd_table_entry(struct i40e_hw *hw, - struct i40e_hmc_info *hmc_info, - u32 sd_index, - enum i40e_sd_entry_type type, - u64 direct_mode_sz); - -i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw, - struct i40e_hmc_info *hmc_info, - u32 pd_index, - struct i40e_dma_mem *rsrc_pg); -i40e_status i40e_remove_pd_bp(struct i40e_hw *hw, - struct i40e_hmc_info *hmc_info, - u32 idx); -i40e_status i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info, - u32 idx); -i40e_status i40e_remove_sd_bp_new(struct i40e_hw *hw, - struct i40e_hmc_info *hmc_info, - u32 idx, bool is_pf); -i40e_status i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info, - u32 idx); -i40e_status i40e_remove_pd_page_new(struct i40e_hw *hw, - struct i40e_hmc_info *hmc_info, - u32 idx, bool is_pf); - -#endif /* _I40E_HMC_H_ */ diff --git a/drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h b/drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h deleted file mode 100644 index 82b00f70a6320a1dd9d957db006e08410cebf050..0000000000000000000000000000000000000000 --- a/drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright(c) 2013 - 2018 Intel Corporation. */ - -#ifndef _I40E_LAN_HMC_H_ -#define _I40E_LAN_HMC_H_ - -/* forward-declare the HW struct for the compiler */ -struct i40e_hw; - -/* HMC element context information */ - -/* Rx queue context data - * - * The sizes of the variables may be larger than needed due to crossing byte - * boundaries. If we do not have the width of the variable set to the correct - * size then we could end up shifting bits off the top of the variable when the - * variable is at the top of a byte and crosses over into the next byte. - */ -struct i40e_hmc_obj_rxq { - u16 head; - u16 cpuid; /* bigger than needed, see above for reason */ - u64 base; - u16 qlen; -#define I40E_RXQ_CTX_DBUFF_SHIFT 7 - u16 dbuff; /* bigger than needed, see above for reason */ -#define I40E_RXQ_CTX_HBUFF_SHIFT 6 - u16 hbuff; /* bigger than needed, see above for reason */ - u8 dtype; - u8 dsize; - u8 crcstrip; - u8 fc_ena; - u8 l2tsel; - u8 hsplit_0; - u8 hsplit_1; - u8 showiv; - u32 rxmax; /* bigger than needed, see above for reason */ - u8 tphrdesc_ena; - u8 tphwdesc_ena; - u8 tphdata_ena; - u8 tphhead_ena; - u16 lrxqthresh; /* bigger than needed, see above for reason */ - u8 prefena; /* NOTE: normally must be set to 1 at init */ -}; - -/* Tx queue context data -* -* The sizes of the variables may be larger than needed due to crossing byte -* boundaries. If we do not have the width of the variable set to the correct -* size then we could end up shifting bits off the top of the variable when the -* variable is at the top of a byte and crosses over into the next byte. -*/ -struct i40e_hmc_obj_txq { - u16 head; - u8 new_context; - u64 base; - u8 fc_ena; - u8 timesync_ena; - u8 fd_ena; - u8 alt_vlan_ena; - u16 thead_wb; - u8 cpuid; - u8 head_wb_ena; - u16 qlen; - u8 tphrdesc_ena; - u8 tphrpacket_ena; - u8 tphwdesc_ena; - u64 head_wb_addr; - u32 crc; - u16 rdylist; - u8 rdylist_act; -}; - -/* for hsplit_0 field of Rx HMC context */ -enum i40e_hmc_obj_rx_hsplit_0 { - I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT = 0, - I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 = 1, - I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP = 2, - I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4, - I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP = 8, -}; - -/* fcoe_cntx and fcoe_filt are for debugging purpose only */ -struct i40e_hmc_obj_fcoe_cntx { - u32 rsv[32]; -}; - -struct i40e_hmc_obj_fcoe_filt { - u32 rsv[8]; -}; - -/* Context sizes for LAN objects */ -enum i40e_hmc_lan_object_size { - I40E_HMC_LAN_OBJ_SZ_8 = 0x3, - I40E_HMC_LAN_OBJ_SZ_16 = 0x4, - I40E_HMC_LAN_OBJ_SZ_32 = 0x5, - I40E_HMC_LAN_OBJ_SZ_64 = 0x6, - I40E_HMC_LAN_OBJ_SZ_128 = 0x7, - I40E_HMC_LAN_OBJ_SZ_256 = 0x8, - I40E_HMC_LAN_OBJ_SZ_512 = 0x9, -}; - -#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512 -#define I40E_HMC_OBJ_SIZE_TXQ 128 -#define I40E_HMC_OBJ_SIZE_RXQ 32 -#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 128 -#define I40E_HMC_OBJ_SIZE_FCOE_FILT 64 - -enum i40e_hmc_lan_rsrc_type { - I40E_HMC_LAN_FULL = 0, - I40E_HMC_LAN_TX = 1, - I40E_HMC_LAN_RX = 2, - I40E_HMC_FCOE_CTX = 3, - I40E_HMC_FCOE_FILT = 4, - I40E_HMC_LAN_MAX = 5 -}; - -enum i40e_hmc_model { - I40E_HMC_MODEL_DIRECT_PREFERRED = 0, - I40E_HMC_MODEL_DIRECT_ONLY = 1, - I40E_HMC_MODEL_PAGED_ONLY = 2, - I40E_HMC_MODEL_UNKNOWN, -}; - -struct i40e_hmc_lan_create_obj_info { - struct i40e_hmc_info *hmc_info; - u32 rsrc_type; - u32 start_idx; - u32 count; - enum i40e_sd_entry_type entry_type; - u64 direct_mode_sz; -}; - -struct i40e_hmc_lan_delete_obj_info { - struct i40e_hmc_info *hmc_info; - u32 rsrc_type; - u32 start_idx; - u32 count; -}; - -i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num, - u32 rxq_num, u32 fcoe_cntx_num, - u32 fcoe_filt_num); -i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw, - enum i40e_hmc_model model); -i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw); - -i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw, - u16 queue); -i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw, - u16 queue, - struct i40e_hmc_obj_txq *s); -i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw, - u16 queue); -i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw, - u16 queue, - struct i40e_hmc_obj_rxq *s); - -#endif /* _I40E_LAN_HMC_H_ */ diff --git a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h b/drivers/net/ethernet/intel/i40evf/i40e_prototype.h deleted file mode 100644 index a358f4b9d5aa639cc6c5b927f38551cad2b0fc05..0000000000000000000000000000000000000000 --- a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright(c) 2013 - 2018 Intel Corporation. */ - -#ifndef _I40E_PROTOTYPE_H_ -#define _I40E_PROTOTYPE_H_ - -#include "i40e_type.h" -#include "i40e_alloc.h" -#include - -/* Prototypes for shared code functions that are not in - * the standard function pointer structures. These are - * mostly because they are needed even before the init - * has happened and will assist in the early SW and FW - * setup. - */ - -/* adminq functions */ -i40e_status i40evf_init_adminq(struct i40e_hw *hw); -i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw); -void i40e_adminq_init_ring_data(struct i40e_hw *hw); -i40e_status i40evf_clean_arq_element(struct i40e_hw *hw, - struct i40e_arq_event_info *e, - u16 *events_pending); -i40e_status i40evf_asq_send_command(struct i40e_hw *hw, - struct i40e_aq_desc *desc, - void *buff, /* can be NULL */ - u16 buff_size, - struct i40e_asq_cmd_details *cmd_details); -bool i40evf_asq_done(struct i40e_hw *hw); - -/* debug function for adminq */ -void i40evf_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, - void *desc, void *buffer, u16 buf_len); - -void i40e_idle_aq(struct i40e_hw *hw); -void i40evf_resume_aq(struct i40e_hw *hw); -bool i40evf_check_asq_alive(struct i40e_hw *hw); -i40e_status i40evf_aq_queue_shutdown(struct i40e_hw *hw, bool unloading); -const char *i40evf_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err); -const char *i40evf_stat_str(struct i40e_hw *hw, i40e_status stat_err); - -i40e_status i40evf_aq_get_rss_lut(struct i40e_hw *hw, u16 seid, - bool pf_lut, u8 *lut, u16 lut_size); -i40e_status i40evf_aq_set_rss_lut(struct i40e_hw *hw, u16 seid, - bool pf_lut, u8 *lut, u16 lut_size); -i40e_status i40evf_aq_get_rss_key(struct i40e_hw *hw, - u16 seid, - struct i40e_aqc_get_set_rss_key_data *key); -i40e_status i40evf_aq_set_rss_key(struct i40e_hw *hw, - u16 seid, - struct i40e_aqc_get_set_rss_key_data *key); - -i40e_status i40e_set_mac_type(struct i40e_hw *hw); - -extern struct i40e_rx_ptype_decoded i40evf_ptype_lookup[]; - -static inline struct i40e_rx_ptype_decoded decode_rx_desc_ptype(u8 ptype) -{ - return i40evf_ptype_lookup[ptype]; -} - -/* prototype for functions used for SW locks */ - -/* i40e_common for VF drivers*/ -void i40e_vf_parse_hw_config(struct i40e_hw *hw, - struct virtchnl_vf_resource *msg); -i40e_status i40e_vf_reset(struct i40e_hw *hw); -i40e_status i40e_aq_send_msg_to_pf(struct i40e_hw *hw, - enum virtchnl_ops v_opcode, - i40e_status v_retval, - u8 *msg, u16 msglen, - struct i40e_asq_cmd_details *cmd_details); -i40e_status i40e_set_filter_control(struct i40e_hw *hw, - struct i40e_filter_control_settings *settings); -i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, - u8 *mac_addr, u16 ethtype, u16 flags, - u16 vsi_seid, u16 queue, bool is_add, - struct i40e_control_filter_stats *stats, - struct i40e_asq_cmd_details *cmd_details); -void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, - u16 vsi_seid); -i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw, - u32 reg_addr, u32 *reg_val, - struct i40e_asq_cmd_details *cmd_details); -u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr); -i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw, - u32 reg_addr, u32 reg_val, - struct i40e_asq_cmd_details *cmd_details); -void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val); -i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw, - u8 phy_select, u8 dev_addr, - u32 reg_addr, u32 reg_val, - struct i40e_asq_cmd_details *cmd_details); -i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw, - u8 phy_select, u8 dev_addr, - u32 reg_addr, u32 *reg_val, - struct i40e_asq_cmd_details *cmd_details); - -i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page, - u16 reg, u8 phy_addr, u16 *value); -i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page, - u16 reg, u8 phy_addr, u16 value); -i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page, u16 reg, - u8 phy_addr, u16 *value); -i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page, u16 reg, - u8 phy_addr, u16 value); -u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num); -i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, - u32 time, u32 interval); -i40e_status i40evf_aq_write_ddp(struct i40e_hw *hw, void *buff, - u16 buff_size, u32 track_id, - u32 *error_offset, u32 *error_info, - struct i40e_asq_cmd_details * - cmd_details); -i40e_status i40evf_aq_get_ddp_list(struct i40e_hw *hw, void *buff, - u16 buff_size, u8 flags, - struct i40e_asq_cmd_details * - cmd_details); -struct i40e_generic_seg_header * -i40evf_find_segment_in_package(u32 segment_type, - struct i40e_package_header *pkg_header); -enum i40e_status_code -i40evf_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *i40e_seg, - u32 track_id); -enum i40e_status_code -i40evf_add_pinfo_to_list(struct i40e_hw *hw, - struct i40e_profile_segment *profile, - u8 *profile_info_sec, u32 track_id); -#endif /* _I40E_PROTOTYPE_H_ */ diff --git a/drivers/net/ethernet/intel/i40evf/i40e_register.h b/drivers/net/ethernet/intel/i40evf/i40e_register.h deleted file mode 100644 index 49e1f57d99cc6703a97ecc5cb7a580a9138113ef..0000000000000000000000000000000000000000 --- a/drivers/net/ethernet/intel/i40evf/i40e_register.h +++ /dev/null @@ -1,313 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright(c) 2013 - 2018 Intel Corporation. */ - -#ifndef _I40E_REGISTER_H_ -#define _I40E_REGISTER_H_ - -#define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */ -#define I40E_VFMSIX_PBA1_MAX_INDEX 19 -#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0 -#define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT) -#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TADD1_MAX_INDEX 639 -#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0 -#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT) -#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2 -#define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT) -#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TMSG1_MAX_INDEX 639 -#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0 -#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT) -#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TUADD1_MAX_INDEX 639 -#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0 -#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT) -#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639 -#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0 -#define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT) -#define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */ -#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0 -#define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT) -#define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */ -#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0 -#define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT) -#define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */ -#define I40E_VF_ARQH1_ARQH_SHIFT 0 -#define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT) -#define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */ -#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0 -#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT) -#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 -#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT) -#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 -#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT) -#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30 -#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT) -#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 -#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT) -#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ -#define I40E_VF_ARQT1_ARQT_SHIFT 0 -#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT) -#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ -#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0 -#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT) -#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ -#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0 -#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT) -#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */ -#define I40E_VF_ATQH1_ATQH_SHIFT 0 -#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT) -#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */ -#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0 -#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT) -#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 -#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT) -#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 -#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT) -#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30 -#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT) -#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 -#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT) -#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ -#define I40E_VF_ATQT1_ATQT_SHIFT 0 -#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT) -#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ -#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 -#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) -#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ -#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 -#define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT) -#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1 -#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT) -#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2 -#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT) -#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3 -#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) -#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5 -#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT) -#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24 -#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT) -#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25 -#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT) -#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31 -#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT) -#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */ -#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15 -#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0 -#define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT) -#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1 -#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT) -#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2 -#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT) -#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3 -#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) -#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5 -#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT) -#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24 -#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT) -#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25 -#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT) -#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31 -#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT) -#define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */ -#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25 -#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT) -#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30 -#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT) -#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31 -#define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT) -#define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */ -#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0 -#define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT) -#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1 -#define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_0_SHIFT) -#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2 -#define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_1_SHIFT) -#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3 -#define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_2_SHIFT) -#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4 -#define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_3_SHIFT) -#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25 -#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT) -#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30 -#define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT) -#define I40E_VFINT_ICR01_SWINT_SHIFT 31 -#define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT) -#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ -#define I40E_VFINT_ITR01_MAX_INDEX 2 -#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0 -#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT) -#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */ -#define I40E_VFINT_ITRN1_MAX_INDEX 2 -#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0 -#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT) -#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */ -#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 -#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT) -#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */ -#define I40E_QRX_TAIL1_MAX_INDEX 15 -#define I40E_QRX_TAIL1_TAIL_SHIFT 0 -#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT) -#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */ -#define I40E_QTX_TAIL1_MAX_INDEX 15 -#define I40E_QTX_TAIL1_TAIL_SHIFT 0 -#define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT) -#define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */ -#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0 -#define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT) -#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TADD_MAX_INDEX 16 -#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0 -#define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT) -#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2 -#define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT) -#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TMSG_MAX_INDEX 16 -#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0 -#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT) -#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TUADD_MAX_INDEX 16 -#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0 -#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT) -#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16 -#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0 -#define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT) -#define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */ -#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0 -#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT) -#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4 -#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT) -#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8 -#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT) -#define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */ -#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0 -#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT) -#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4 -#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT) -#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8 -#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT) -#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16 -#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT) -#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24 -#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT) -#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ -#define I40E_VFQF_HENA_MAX_INDEX 1 -#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0 -#define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT) -#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ -#define I40E_VFQF_HKEY_MAX_INDEX 12 -#define I40E_VFQF_HKEY_KEY_0_SHIFT 0 -#define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT) -#define I40E_VFQF_HKEY_KEY_1_SHIFT 8 -#define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT) -#define I40E_VFQF_HKEY_KEY_2_SHIFT 16 -#define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT) -#define I40E_VFQF_HKEY_KEY_3_SHIFT 24 -#define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT) -#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ -#define I40E_VFQF_HLUT_MAX_INDEX 15 -#define I40E_VFQF_HLUT_LUT0_SHIFT 0 -#define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT) -#define I40E_VFQF_HLUT_LUT1_SHIFT 8 -#define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT) -#define I40E_VFQF_HLUT_LUT2_SHIFT 16 -#define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT) -#define I40E_VFQF_HLUT_LUT3_SHIFT 24 -#define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT) -#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */ -#define I40E_VFQF_HREGION_MAX_INDEX 7 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT) -#define I40E_VFQF_HREGION_REGION_0_SHIFT 1 -#define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT) -#define I40E_VFQF_HREGION_REGION_1_SHIFT 5 -#define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT) -#define I40E_VFQF_HREGION_REGION_2_SHIFT 9 -#define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT) -#define I40E_VFQF_HREGION_REGION_3_SHIFT 13 -#define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT) -#define I40E_VFQF_HREGION_REGION_4_SHIFT 17 -#define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT) -#define I40E_VFQF_HREGION_REGION_5_SHIFT 21 -#define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT) -#define I40E_VFQF_HREGION_REGION_6_SHIFT 25 -#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT) -#define I40E_VFQF_HREGION_REGION_7_SHIFT 29 -#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT) -#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30 -#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT) -#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30 -#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT) -#define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */ -#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0 -#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT) -#define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */ -#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0 -#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT) -#define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */ -#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0 -#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT) -#define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */ -#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0 -#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT) -#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4 -#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT) -#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16 -#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT) -#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31 -#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT) -#define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */ -#define I40E_VFPE_CQACK1_PECQID_SHIFT 0 -#define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT) -#define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */ -#define I40E_VFPE_CQARM1_PECQID_SHIFT 0 -#define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT) -#define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */ -#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0 -#define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT) -#define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */ -#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0 -#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT) -#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16 -#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT) -#define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */ -#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0 -#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT) -#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31 -#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT) -#define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */ -#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0 -#define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT) -#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16 -#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT) -#define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */ -#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0 -#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT) -#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */ -#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0 -#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT) -#define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */ -#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0 -#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT) -#define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */ -#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0 -#define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT) -#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20 -#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT) -#endif /* _I40E_REGISTER_H_ */ diff --git a/drivers/net/ethernet/intel/i40evf/i40e_type.h b/drivers/net/ethernet/intel/i40evf/i40e_type.h deleted file mode 100644 index 094387db3c110a707d21db6b525b984fc54c5165..0000000000000000000000000000000000000000 --- a/drivers/net/ethernet/intel/i40evf/i40e_type.h +++ /dev/null @@ -1,1496 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright(c) 2013 - 2018 Intel Corporation. */ - -#ifndef _I40E_TYPE_H_ -#define _I40E_TYPE_H_ - -#include "i40e_status.h" -#include "i40e_osdep.h" -#include "i40e_register.h" -#include "i40e_adminq.h" -#include "i40e_hmc.h" -#include "i40e_lan_hmc.h" -#include "i40e_devids.h" - -/* I40E_MASK is a macro used on 32 bit registers */ -#define I40E_MASK(mask, shift) ((u32)(mask) << (shift)) - -#define I40E_MAX_VSI_QP 16 -#define I40E_MAX_VF_VSI 3 -#define I40E_MAX_CHAINED_RX_BUFFERS 5 -#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 - -/* Max default timeout in ms, */ -#define I40E_MAX_NVM_TIMEOUT 18000 - -/* Max timeout in ms for the phy to respond */ -#define I40E_MAX_PHY_TIMEOUT 500 - -/* Switch from ms to the 1usec global time (this is the GTIME resolution) */ -#define I40E_MS_TO_GTIME(time) ((time) * 1000) - -/* forward declaration */ -struct i40e_hw; -typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); - -/* Data type manipulation macros. */ - -#define I40E_DESC_UNUSED(R) \ - ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ - (R)->next_to_clean - (R)->next_to_use - 1) - -/* bitfields for Tx queue mapping in QTX_CTL */ -#define I40E_QTX_CTL_VF_QUEUE 0x0 -#define I40E_QTX_CTL_VM_QUEUE 0x1 -#define I40E_QTX_CTL_PF_QUEUE 0x2 - -/* debug masks - set these bits in hw->debug_mask to control output */ -enum i40e_debug_mask { - I40E_DEBUG_INIT = 0x00000001, - I40E_DEBUG_RELEASE = 0x00000002, - - I40E_DEBUG_LINK = 0x00000010, - I40E_DEBUG_PHY = 0x00000020, - I40E_DEBUG_HMC = 0x00000040, - I40E_DEBUG_NVM = 0x00000080, - I40E_DEBUG_LAN = 0x00000100, - I40E_DEBUG_FLOW = 0x00000200, - I40E_DEBUG_DCB = 0x00000400, - I40E_DEBUG_DIAG = 0x00000800, - I40E_DEBUG_FD = 0x00001000, - I40E_DEBUG_PACKAGE = 0x00002000, - - I40E_DEBUG_AQ_MESSAGE = 0x01000000, - I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000, - I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000, - I40E_DEBUG_AQ_COMMAND = 0x06000000, - I40E_DEBUG_AQ = 0x0F000000, - - I40E_DEBUG_USER = 0xF0000000, - - I40E_DEBUG_ALL = 0xFFFFFFFF -}; - -/* These are structs for managing the hardware information and the operations. - * The structures of function pointers are filled out at init time when we - * know for sure exactly which hardware we're working with. This gives us the - * flexibility of using the same main driver code but adapting to slightly - * different hardware needs as new parts are developed. For this architecture, - * the Firmware and AdminQ are intended to insulate the driver from most of the - * future changes, but these structures will also do part of the job. - */ -enum i40e_mac_type { - I40E_MAC_UNKNOWN = 0, - I40E_MAC_XL710, - I40E_MAC_VF, - I40E_MAC_X722, - I40E_MAC_X722_VF, - I40E_MAC_GENERIC, -}; - -enum i40e_media_type { - I40E_MEDIA_TYPE_UNKNOWN = 0, - I40E_MEDIA_TYPE_FIBER, - I40E_MEDIA_TYPE_BASET, - I40E_MEDIA_TYPE_BACKPLANE, - I40E_MEDIA_TYPE_CX4, - I40E_MEDIA_TYPE_DA, - I40E_MEDIA_TYPE_VIRTUAL -}; - -enum i40e_fc_mode { - I40E_FC_NONE = 0, - I40E_FC_RX_PAUSE, - I40E_FC_TX_PAUSE, - I40E_FC_FULL, - I40E_FC_PFC, - I40E_FC_DEFAULT -}; - -enum i40e_set_fc_aq_failures { - I40E_SET_FC_AQ_FAIL_NONE = 0, - I40E_SET_FC_AQ_FAIL_GET = 1, - I40E_SET_FC_AQ_FAIL_SET = 2, - I40E_SET_FC_AQ_FAIL_UPDATE = 4, - I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 -}; - -enum i40e_vsi_type { - I40E_VSI_MAIN = 0, - I40E_VSI_VMDQ1 = 1, - I40E_VSI_VMDQ2 = 2, - I40E_VSI_CTRL = 3, - I40E_VSI_FCOE = 4, - I40E_VSI_MIRROR = 5, - I40E_VSI_SRIOV = 6, - I40E_VSI_FDIR = 7, - I40E_VSI_TYPE_UNKNOWN -}; - -enum i40e_queue_type { - I40E_QUEUE_TYPE_RX = 0, - I40E_QUEUE_TYPE_TX, - I40E_QUEUE_TYPE_PE_CEQ, - I40E_QUEUE_TYPE_UNKNOWN -}; - -struct i40e_link_status { - enum i40e_aq_phy_type phy_type; - enum i40e_aq_link_speed link_speed; - u8 link_info; - u8 an_info; - u8 req_fec_info; - u8 fec_info; - u8 ext_info; - u8 loopback; - /* is Link Status Event notification to SW enabled */ - bool lse_enable; - u16 max_frame_size; - bool crc_enable; - u8 pacing; - u8 requested_speeds; - u8 module_type[3]; - /* 1st byte: module identifier */ -#define I40E_MODULE_TYPE_SFP 0x03 -#define I40E_MODULE_TYPE_QSFP 0x0D - /* 2nd byte: ethernet compliance codes for 10/40G */ -#define I40E_MODULE_TYPE_40G_ACTIVE 0x01 -#define I40E_MODULE_TYPE_40G_LR4 0x02 -#define I40E_MODULE_TYPE_40G_SR4 0x04 -#define I40E_MODULE_TYPE_40G_CR4 0x08 -#define I40E_MODULE_TYPE_10G_BASE_SR 0x10 -#define I40E_MODULE_TYPE_10G_BASE_LR 0x20 -#define I40E_MODULE_TYPE_10G_BASE_LRM 0x40 -#define I40E_MODULE_TYPE_10G_BASE_ER 0x80 - /* 3rd byte: ethernet compliance codes for 1G */ -#define I40E_MODULE_TYPE_1000BASE_SX 0x01 -#define I40E_MODULE_TYPE_1000BASE_LX 0x02 -#define I40E_MODULE_TYPE_1000BASE_CX 0x04 -#define I40E_MODULE_TYPE_1000BASE_T 0x08 -}; - -struct i40e_phy_info { - struct i40e_link_status link_info; - struct i40e_link_status link_info_old; - bool get_link_info; - enum i40e_media_type media_type; - /* all the phy types the NVM is capable of */ - u64 phy_types; -}; - -#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII) -#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) -#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) -#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) -#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) -#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI) -#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI) -#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI) -#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI) -#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI) -#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) -#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) -#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) -#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) -#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX) -#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T) -#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T) -#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) -#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) -#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) -#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) -#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) -#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) -#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) -#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) -#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) -#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \ - BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) -#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) -/* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some - * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit - * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So, - * a shift is needed to adjust for this with values larger than 31. The - * only affected values are I40E_PHY_TYPE_25GBASE_*. - */ -#define I40E_PHY_TYPE_OFFSET 1 -#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \ - I40E_PHY_TYPE_OFFSET) -#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \ - I40E_PHY_TYPE_OFFSET) -#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ - I40E_PHY_TYPE_OFFSET) -#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ - I40E_PHY_TYPE_OFFSET) -#define I40E_HW_CAP_MAX_GPIO 30 -/* Capabilities of a PF or a VF or the whole device */ -struct i40e_hw_capabilities { - u32 switch_mode; -#define I40E_NVM_IMAGE_TYPE_EVB 0x0 -#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 -#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 - - u32 management_mode; - u32 mng_protocols_over_mctp; -#define I40E_MNG_PROTOCOL_PLDM 0x2 -#define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4 -#define I40E_MNG_PROTOCOL_NCSI 0x8 - u32 npar_enable; - u32 os2bmc; - u32 valid_functions; - bool sr_iov_1_1; - bool vmdq; - bool evb_802_1_qbg; /* Edge Virtual Bridging */ - bool evb_802_1_qbh; /* Bridge Port Extension */ - bool dcb; - bool fcoe; - bool iscsi; /* Indicates iSCSI enabled */ - bool flex10_enable; - bool flex10_capable; - u32 flex10_mode; -#define I40E_FLEX10_MODE_UNKNOWN 0x0 -#define I40E_FLEX10_MODE_DCC 0x1 -#define I40E_FLEX10_MODE_DCI 0x2 - - u32 flex10_status; -#define I40E_FLEX10_STATUS_DCC_ERROR 0x1 -#define I40E_FLEX10_STATUS_VC_MODE 0x2 - - bool sec_rev_disabled; - bool update_disabled; -#define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1 -#define I40E_NVM_MGMT_UPDATE_DISABLED 0x2 - - bool mgmt_cem; - bool ieee_1588; - bool iwarp; - bool fd; - u32 fd_filters_guaranteed; - u32 fd_filters_best_effort; - bool rss; - u32 rss_table_size; - u32 rss_table_entry_width; - bool led[I40E_HW_CAP_MAX_GPIO]; - bool sdp[I40E_HW_CAP_MAX_GPIO]; - u32 nvm_image_type; - u32 num_flow_director_filters; - u32 num_vfs; - u32 vf_base_id; - u32 num_vsis; - u32 num_rx_qp; - u32 num_tx_qp; - u32 base_queue; - u32 num_msix_vectors; - u32 num_msix_vectors_vf; - u32 led_pin_num; - u32 sdp_pin_num; - u32 mdio_port_num; - u32 mdio_port_mode; - u8 rx_buf_chain_len; - u32 enabled_tcmap; - u32 maxtc; - u64 wr_csr_prot; -}; - -struct i40e_mac_info { - enum i40e_mac_type type; - u8 addr[ETH_ALEN]; - u8 perm_addr[ETH_ALEN]; - u8 san_addr[ETH_ALEN]; - u16 max_fcoeq; -}; - -enum i40e_aq_resources_ids { - I40E_NVM_RESOURCE_ID = 1 -}; - -enum i40e_aq_resource_access_type { - I40E_RESOURCE_READ = 1, - I40E_RESOURCE_WRITE -}; - -struct i40e_nvm_info { - u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */ - u32 timeout; /* [ms] */ - u16 sr_size; /* Shadow RAM size in words */ - bool blank_nvm_mode; /* is NVM empty (no FW present)*/ - u16 version; /* NVM package version */ - u32 eetrack; /* NVM data version */ - u32 oem_ver; /* OEM version info */ -}; - -/* definitions used in NVM update support */ - -enum i40e_nvmupd_cmd { - I40E_NVMUPD_INVALID, - I40E_NVMUPD_READ_CON, - I40E_NVMUPD_READ_SNT, - I40E_NVMUPD_READ_LCB, - I40E_NVMUPD_READ_SA, - I40E_NVMUPD_WRITE_ERA, - I40E_NVMUPD_WRITE_CON, - I40E_NVMUPD_WRITE_SNT, - I40E_NVMUPD_WRITE_LCB, - I40E_NVMUPD_WRITE_SA, - I40E_NVMUPD_CSUM_CON, - I40E_NVMUPD_CSUM_SA, - I40E_NVMUPD_CSUM_LCB, - I40E_NVMUPD_STATUS, - I40E_NVMUPD_EXEC_AQ, - I40E_NVMUPD_GET_AQ_RESULT, - I40E_NVMUPD_GET_AQ_EVENT, -}; - -enum i40e_nvmupd_state { - I40E_NVMUPD_STATE_INIT, - I40E_NVMUPD_STATE_READING, - I40E_NVMUPD_STATE_WRITING, - I40E_NVMUPD_STATE_INIT_WAIT, - I40E_NVMUPD_STATE_WRITE_WAIT, - I40E_NVMUPD_STATE_ERROR -}; - -/* nvm_access definition and its masks/shifts need to be accessible to - * application, core driver, and shared code. Where is the right file? - */ -#define I40E_NVM_READ 0xB -#define I40E_NVM_WRITE 0xC - -#define I40E_NVM_MOD_PNT_MASK 0xFF - -#define I40E_NVM_TRANS_SHIFT 8 -#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) -#define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12 -#define I40E_NVM_PRESERVATION_FLAGS_MASK \ - (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT) -#define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01 -#define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02 -#define I40E_NVM_CON 0x0 -#define I40E_NVM_SNT 0x1 -#define I40E_NVM_LCB 0x2 -#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) -#define I40E_NVM_ERA 0x4 -#define I40E_NVM_CSUM 0x8 -#define I40E_NVM_AQE 0xe -#define I40E_NVM_EXEC 0xf - -#define I40E_NVM_ADAPT_SHIFT 16 -#define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT) - -#define I40E_NVMUPD_MAX_DATA 4096 -#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ - -struct i40e_nvm_access { - u32 command; - u32 config; - u32 offset; /* in bytes */ - u32 data_size; /* in bytes */ - u8 data[1]; -}; - -/* (Q)SFP module access definitions */ -#define I40E_I2C_EEPROM_DEV_ADDR 0xA0 -#define I40E_I2C_EEPROM_DEV_ADDR2 0xA2 -#define I40E_MODULE_TYPE_ADDR 0x00 -#define I40E_MODULE_REVISION_ADDR 0x01 -#define I40E_MODULE_SFF_8472_COMP 0x5E -#define I40E_MODULE_SFF_8472_SWAP 0x5C -#define I40E_MODULE_SFF_ADDR_MODE 0x04 -#define I40E_MODULE_TYPE_QSFP_PLUS 0x0D -#define I40E_MODULE_TYPE_QSFP28 0x11 -#define I40E_MODULE_QSFP_MAX_LEN 640 - -/* PCI bus types */ -enum i40e_bus_type { - i40e_bus_type_unknown = 0, - i40e_bus_type_pci, - i40e_bus_type_pcix, - i40e_bus_type_pci_express, - i40e_bus_type_reserved -}; - -/* PCI bus speeds */ -enum i40e_bus_speed { - i40e_bus_speed_unknown = 0, - i40e_bus_speed_33 = 33, - i40e_bus_speed_66 = 66, - i40e_bus_speed_100 = 100, - i40e_bus_speed_120 = 120, - i40e_bus_speed_133 = 133, - i40e_bus_speed_2500 = 2500, - i40e_bus_speed_5000 = 5000, - i40e_bus_speed_8000 = 8000, - i40e_bus_speed_reserved -}; - -/* PCI bus widths */ -enum i40e_bus_width { - i40e_bus_width_unknown = 0, - i40e_bus_width_pcie_x1 = 1, - i40e_bus_width_pcie_x2 = 2, - i40e_bus_width_pcie_x4 = 4, - i40e_bus_width_pcie_x8 = 8, - i40e_bus_width_32 = 32, - i40e_bus_width_64 = 64, - i40e_bus_width_reserved -}; - -/* Bus parameters */ -struct i40e_bus_info { - enum i40e_bus_speed speed; - enum i40e_bus_width width; - enum i40e_bus_type type; - - u16 func; - u16 device; - u16 lan_id; - u16 bus_id; -}; - -/* Flow control (FC) parameters */ -struct i40e_fc_info { - enum i40e_fc_mode current_mode; /* FC mode in effect */ - enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ -}; - -#define I40E_MAX_TRAFFIC_CLASS 8 -#define I40E_MAX_USER_PRIORITY 8 -#define I40E_DCBX_MAX_APPS 32 -#define I40E_LLDPDU_SIZE 1500 - -/* IEEE 802.1Qaz ETS Configuration data */ -struct i40e_ieee_ets_config { - u8 willing; - u8 cbs; - u8 maxtcs; - u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; - u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; - u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; -}; - -/* IEEE 802.1Qaz ETS Recommendation data */ -struct i40e_ieee_ets_recommend { - u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; - u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; - u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; -}; - -/* IEEE 802.1Qaz PFC Configuration data */ -struct i40e_ieee_pfc_config { - u8 willing; - u8 mbc; - u8 pfccap; - u8 pfcenable; -}; - -/* IEEE 802.1Qaz Application Priority data */ -struct i40e_ieee_app_priority_table { - u8 priority; - u8 selector; - u16 protocolid; -}; - -struct i40e_dcbx_config { - u32 numapps; - u32 tlv_status; /* CEE mode TLV status */ - struct i40e_ieee_ets_config etscfg; - struct i40e_ieee_ets_recommend etsrec; - struct i40e_ieee_pfc_config pfc; - struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS]; -}; - -/* Port hardware description */ -struct i40e_hw { - u8 __iomem *hw_addr; - void *back; - - /* subsystem structs */ - struct i40e_phy_info phy; - struct i40e_mac_info mac; - struct i40e_bus_info bus; - struct i40e_nvm_info nvm; - struct i40e_fc_info fc; - - /* pci info */ - u16 device_id; - u16 vendor_id; - u16 subsystem_device_id; - u16 subsystem_vendor_id; - u8 revision_id; - u8 port; - bool adapter_stopped; - - /* capabilities for entire device and PCI func */ - struct i40e_hw_capabilities dev_caps; - struct i40e_hw_capabilities func_caps; - - /* Flow Director shared filter space */ - u16 fdir_shared_filter_count; - - /* device profile info */ - u8 pf_id; - u16 main_vsi_seid; - - /* for multi-function MACs */ - u16 partition_id; - u16 num_partitions; - u16 num_ports; - - /* Closest numa node to the device */ - u16 numa_node; - - /* Admin Queue info */ - struct i40e_adminq_info aq; - - /* state of nvm update process */ - enum i40e_nvmupd_state nvmupd_state; - struct i40e_aq_desc nvm_wb_desc; - struct i40e_aq_desc nvm_aq_event_desc; - struct i40e_virt_mem nvm_buff; - bool nvm_release_on_done; - u16 nvm_wait_opcode; - - /* HMC info */ - struct i40e_hmc_info hmc; /* HMC info struct */ - - /* LLDP/DCBX Status */ - u16 dcbx_status; - -#define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) -#define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) - - /* DCBX info */ - struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */ - struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ - struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ - - /* Used in set switch config AQ command */ - u16 switch_tag; - u16 first_tag; - u16 second_tag; - - /* debug mask */ - u32 debug_mask; - char err_str[16]; -}; - -static inline bool i40e_is_vf(struct i40e_hw *hw) -{ - return (hw->mac.type == I40E_MAC_VF || - hw->mac.type == I40E_MAC_X722_VF); -} - -struct i40e_driver_version { - u8 major_version; - u8 minor_version; - u8 build_version; - u8 subbuild_version; - u8 driver_string[32]; -}; - -/* RX Descriptors */ -union i40e_16byte_rx_desc { - struct { - __le64 pkt_addr; /* Packet buffer address */ - __le64 hdr_addr; /* Header buffer address */ - } read; - struct { - struct { - struct { - union { - __le16 mirroring_status; - __le16 fcoe_ctx_id; - } mirr_fcoe; - __le16 l2tag1; - } lo_dword; - union { - __le32 rss; /* RSS Hash */ - __le32 fd_id; /* Flow director filter id */ - __le32 fcoe_param; /* FCoE DDP Context id */ - } hi_dword; - } qword0; - struct { - /* ext status/error/pktype/length */ - __le64 status_error_len; - } qword1; - } wb; /* writeback */ -}; - -union i40e_32byte_rx_desc { - struct { - __le64 pkt_addr; /* Packet buffer address */ - __le64 hdr_addr; /* Header buffer address */ - /* bit 0 of hdr_buffer_addr is DD bit */ - __le64 rsvd1; - __le64 rsvd2; - } read; - struct { - struct { - struct { - union { - __le16 mirroring_status; - __le16 fcoe_ctx_id; - } mirr_fcoe; - __le16 l2tag1; - } lo_dword; - union { - __le32 rss; /* RSS Hash */ - __le32 fcoe_param; /* FCoE DDP Context id */ - /* Flow director filter id in case of - * Programming status desc WB - */ - __le32 fd_id; - } hi_dword; - } qword0; - struct { - /* status/error/pktype/length */ - __le64 status_error_len; - } qword1; - struct { - __le16 ext_status; /* extended status */ - __le16 rsvd; - __le16 l2tag2_1; - __le16 l2tag2_2; - } qword2; - struct { - union { - __le32 flex_bytes_lo; - __le32 pe_status; - } lo_dword; - union { - __le32 flex_bytes_hi; - __le32 fd_id; - } hi_dword; - } qword3; - } wb; /* writeback */ -}; - -enum i40e_rx_desc_status_bits { - /* Note: These are predefined bit offsets */ - I40E_RX_DESC_STATUS_DD_SHIFT = 0, - I40E_RX_DESC_STATUS_EOF_SHIFT = 1, - I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, - I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, - I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, - I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ - I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, - /* Note: Bit 8 is reserved in X710 and XL710 */ - I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8, - I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ - I40E_RX_DESC_STATUS_FLM_SHIFT = 11, - I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ - I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, - I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, - I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */ - /* Note: For non-tunnel packets INT_UDP_0 is the right status for - * UDP header - */ - I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18, - I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ -}; - -#define I40E_RXD_QW1_STATUS_SHIFT 0 -#define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \ - << I40E_RXD_QW1_STATUS_SHIFT) - -#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT -#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ - I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT) - -#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT -#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \ - BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT) - -enum i40e_rx_desc_fltstat_values { - I40E_RX_DESC_FLTSTAT_NO_DATA = 0, - I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ - I40E_RX_DESC_FLTSTAT_RSV = 2, - I40E_RX_DESC_FLTSTAT_RSS_HASH = 3, -}; - -#define I40E_RXD_QW1_ERROR_SHIFT 19 -#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT) - -enum i40e_rx_desc_error_bits { - /* Note: These are predefined bit offsets */ - I40E_RX_DESC_ERROR_RXE_SHIFT = 0, - I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1, - I40E_RX_DESC_ERROR_HBO_SHIFT = 2, - I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ - I40E_RX_DESC_ERROR_IPE_SHIFT = 3, - I40E_RX_DESC_ERROR_L4E_SHIFT = 4, - I40E_RX_DESC_ERROR_EIPE_SHIFT = 5, - I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, - I40E_RX_DESC_ERROR_PPRS_SHIFT = 7 -}; - -enum i40e_rx_desc_error_l3l4e_fcoe_masks { - I40E_RX_DESC_ERROR_L3L4E_NONE = 0, - I40E_RX_DESC_ERROR_L3L4E_PROT = 1, - I40E_RX_DESC_ERROR_L3L4E_FC = 2, - I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, - I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 -}; - -#define I40E_RXD_QW1_PTYPE_SHIFT 30 -#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT) - -/* Packet type non-ip values */ -enum i40e_rx_l2_ptype { - I40E_RX_PTYPE_L2_RESERVED = 0, - I40E_RX_PTYPE_L2_MAC_PAY2 = 1, - I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, - I40E_RX_PTYPE_L2_FIP_PAY2 = 3, - I40E_RX_PTYPE_L2_OUI_PAY2 = 4, - I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, - I40E_RX_PTYPE_L2_LLDP_PAY2 = 6, - I40E_RX_PTYPE_L2_ECP_PAY2 = 7, - I40E_RX_PTYPE_L2_EVB_PAY2 = 8, - I40E_RX_PTYPE_L2_QCN_PAY2 = 9, - I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10, - I40E_RX_PTYPE_L2_ARP = 11, - I40E_RX_PTYPE_L2_FCOE_PAY3 = 12, - I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, - I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, - I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, - I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, - I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, - I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, - I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, - I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, - I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, - I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, - I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, - I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, - I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153 -}; - -struct i40e_rx_ptype_decoded { - u32 ptype:8; - u32 known:1; - u32 outer_ip:1; - u32 outer_ip_ver:1; - u32 outer_frag:1; - u32 tunnel_type:3; - u32 tunnel_end_prot:2; - u32 tunnel_end_frag:1; - u32 inner_prot:4; - u32 payload_layer:3; -}; - -enum i40e_rx_ptype_outer_ip { - I40E_RX_PTYPE_OUTER_L2 = 0, - I40E_RX_PTYPE_OUTER_IP = 1 -}; - -enum i40e_rx_ptype_outer_ip_ver { - I40E_RX_PTYPE_OUTER_NONE = 0, - I40E_RX_PTYPE_OUTER_IPV4 = 0, - I40E_RX_PTYPE_OUTER_IPV6 = 1 -}; - -enum i40e_rx_ptype_outer_fragmented { - I40E_RX_PTYPE_NOT_FRAG = 0, - I40E_RX_PTYPE_FRAG = 1 -}; - -enum i40e_rx_ptype_tunnel_type { - I40E_RX_PTYPE_TUNNEL_NONE = 0, - I40E_RX_PTYPE_TUNNEL_IP_IP = 1, - I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2, - I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, - I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, -}; - -enum i40e_rx_ptype_tunnel_end_prot { - I40E_RX_PTYPE_TUNNEL_END_NONE = 0, - I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1, - I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2, -}; - -enum i40e_rx_ptype_inner_prot { - I40E_RX_PTYPE_INNER_PROT_NONE = 0, - I40E_RX_PTYPE_INNER_PROT_UDP = 1, - I40E_RX_PTYPE_INNER_PROT_TCP = 2, - I40E_RX_PTYPE_INNER_PROT_SCTP = 3, - I40E_RX_PTYPE_INNER_PROT_ICMP = 4, - I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5 -}; - -enum i40e_rx_ptype_payload_layer { - I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, - I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, - I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, - I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, -}; - -#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38 -#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ - I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - -#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52 -#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ - I40E_RXD_QW1_LENGTH_HBUF_SHIFT) - -#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 -#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT) - -enum i40e_rx_desc_ext_status_bits { - /* Note: These are predefined bit offsets */ - I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, - I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, - I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ - I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ - I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, - I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, - I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, -}; - -enum i40e_rx_desc_pe_status_bits { - /* Note: These are predefined bit offsets */ - I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ - I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ - I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ - I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, - I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, - I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, - I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27, - I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, - I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 -}; - -#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 -#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 - -#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 -#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ - I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) - -#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 -#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ - I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) - -enum i40e_rx_prog_status_desc_status_bits { - /* Note: These are predefined bit offsets */ - I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0, - I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ -}; - -enum i40e_rx_prog_status_desc_prog_id_masks { - I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, - I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, - I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, -}; - -enum i40e_rx_prog_status_desc_error_bits { - /* Note: These are predefined bit offsets */ - I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, - I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, - I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, - I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 -}; - -/* TX Descriptor */ -struct i40e_tx_desc { - __le64 buffer_addr; /* Address of descriptor's data buf */ - __le64 cmd_type_offset_bsz; -}; - -#define I40E_TXD_QW1_DTYPE_SHIFT 0 -#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT) - -enum i40e_tx_desc_dtype_value { - I40E_TX_DESC_DTYPE_DATA = 0x0, - I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ - I40E_TX_DESC_DTYPE_CONTEXT = 0x1, - I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2, - I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8, - I40E_TX_DESC_DTYPE_DDP_CTX = 0x9, - I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB, - I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, - I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, - I40E_TX_DESC_DTYPE_DESC_DONE = 0xF -}; - -#define I40E_TXD_QW1_CMD_SHIFT 4 -#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT) - -enum i40e_tx_desc_cmd_bits { - I40E_TX_DESC_CMD_EOP = 0x0001, - I40E_TX_DESC_CMD_RS = 0x0002, - I40E_TX_DESC_CMD_ICRC = 0x0004, - I40E_TX_DESC_CMD_IL2TAG1 = 0x0008, - I40E_TX_DESC_CMD_DUMMY = 0x0010, - I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ - I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ - I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ - I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ - I40E_TX_DESC_CMD_FCOET = 0x0080, - I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ - I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ - I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ - I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ - I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ - I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ - I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ - I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ -}; - -#define I40E_TXD_QW1_OFFSET_SHIFT 16 -#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ - I40E_TXD_QW1_OFFSET_SHIFT) - -enum i40e_tx_desc_length_fields { - /* Note: These are predefined bit offsets */ - I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ - I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ - I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ -}; - -#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 -#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ - I40E_TXD_QW1_TX_BUF_SZ_SHIFT) - -#define I40E_TXD_QW1_L2TAG1_SHIFT 48 -#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT) - -/* Context descriptors */ -struct i40e_tx_context_desc { - __le32 tunneling_params; - __le16 l2tag2; - __le16 rsvd; - __le64 type_cmd_tso_mss; -}; - -#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0 -#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT) - -#define I40E_TXD_CTX_QW1_CMD_SHIFT 4 -#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) - -enum i40e_tx_ctx_desc_cmd_bits { - I40E_TX_CTX_DESC_TSO = 0x01, - I40E_TX_CTX_DESC_TSYN = 0x02, - I40E_TX_CTX_DESC_IL2TAG2 = 0x04, - I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, - I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00, - I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10, - I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20, - I40E_TX_CTX_DESC_SWTCH_VSI = 0x30, - I40E_TX_CTX_DESC_SWPE = 0x40 -}; - -#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 -#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ - I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) - -#define I40E_TXD_CTX_QW1_MSS_SHIFT 50 -#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ - I40E_TXD_CTX_QW1_MSS_SHIFT) - -#define I40E_TXD_CTX_QW1_VSI_SHIFT 50 -#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT) - -#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0 -#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ - I40E_TXD_CTX_QW0_EXT_IP_SHIFT) - -enum i40e_tx_ctx_desc_eipt_offload { - I40E_TX_CTX_EXT_IP_NONE = 0x0, - I40E_TX_CTX_EXT_IP_IPV6 = 0x1, - I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, - I40E_TX_CTX_EXT_IP_IPV4 = 0x3 -}; - -#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 -#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ - I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT) - -#define I40E_TXD_CTX_QW0_NATT_SHIFT 9 -#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) - -#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT) -#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) - -#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 -#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \ - BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT) - -#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK - -#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 -#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ - I40E_TXD_CTX_QW0_NATLEN_SHIFT) - -#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19 -#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ - I40E_TXD_CTX_QW0_DECTTL_SHIFT) - -#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23 -#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT) -struct i40e_filter_program_desc { - __le32 qindex_flex_ptype_vsi; - __le32 rsvd; - __le32 dtype_cmd_cntindex; - __le32 fd_id; -}; -#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 -#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ - I40E_TXD_FLTR_QW0_QINDEX_SHIFT) -#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 -#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ - I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) -#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 -#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ - I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) - -/* Packet Classifier Types for filters */ -enum i40e_filter_pctype { - /* Note: Values 0-28 are reserved for future use. - * Value 29, 30, 32 are not supported on XL710 and X710. - */ - I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, - I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, - I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, - I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, - I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, - I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, - I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, - I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, - /* Note: Values 37-38 are reserved for future use. - * Value 39, 40, 42 are not supported on XL710 and X710. - */ - I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, - I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, - I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, - I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, - I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, - I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, - I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, - I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, - /* Note: Value 47 is reserved for future use */ - I40E_FILTER_PCTYPE_FCOE_OX = 48, - I40E_FILTER_PCTYPE_FCOE_RX = 49, - I40E_FILTER_PCTYPE_FCOE_OTHER = 50, - /* Note: Values 51-62 are reserved for future use */ - I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, -}; - -enum i40e_filter_program_desc_dest { - I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, - I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, - I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, -}; - -enum i40e_filter_program_desc_fd_status { - I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, - I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, - I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, - I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, -}; - -#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 -#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \ - I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) - -#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 -#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ - I40E_TXD_FLTR_QW1_CMD_SHIFT) - -#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) -#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT) - -enum i40e_filter_program_desc_pcmd { - I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, - I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, -}; - -#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) -#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) - -#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) -#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) - -#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ - I40E_TXD_FLTR_QW1_CMD_SHIFT) -#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ - I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) - -#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 -#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ - I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) - -enum i40e_filter_type { - I40E_FLOW_DIRECTOR_FLTR = 0, - I40E_PE_QUAD_HASH_FLTR = 1, - I40E_ETHERTYPE_FLTR, - I40E_FCOE_CTX_FLTR, - I40E_MAC_VLAN_FLTR, - I40E_HASH_FLTR -}; - -struct i40e_vsi_context { - u16 seid; - u16 uplink_seid; - u16 vsi_number; - u16 vsis_allocated; - u16 vsis_unallocated; - u16 flags; - u8 pf_num; - u8 vf_num; - u8 connection_type; - struct i40e_aqc_vsi_properties_data info; -}; - -struct i40e_veb_context { - u16 seid; - u16 uplink_seid; - u16 veb_number; - u16 vebs_allocated; - u16 vebs_unallocated; - u16 flags; - struct i40e_aqc_get_veb_parameters_completion info; -}; - -/* Statistics collected by each port, VSI, VEB, and S-channel */ -struct i40e_eth_stats { - u64 rx_bytes; /* gorc */ - u64 rx_unicast; /* uprc */ - u64 rx_multicast; /* mprc */ - u64 rx_broadcast; /* bprc */ - u64 rx_discards; /* rdpc */ - u64 rx_unknown_protocol; /* rupp */ - u64 tx_bytes; /* gotc */ - u64 tx_unicast; /* uptc */ - u64 tx_multicast; /* mptc */ - u64 tx_broadcast; /* bptc */ - u64 tx_discards; /* tdpc */ - u64 tx_errors; /* tepc */ -}; - -/* Statistics collected per VEB per TC */ -struct i40e_veb_tc_stats { - u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS]; - u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS]; - u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS]; - u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS]; -}; - -/* Statistics collected by the MAC */ -struct i40e_hw_port_stats { - /* eth stats collected by the port */ - struct i40e_eth_stats eth; - - /* additional port specific stats */ - u64 tx_dropped_link_down; /* tdold */ - u64 crc_errors; /* crcerrs */ - u64 illegal_bytes; /* illerrc */ - u64 error_bytes; /* errbc */ - u64 mac_local_faults; /* mlfc */ - u64 mac_remote_faults; /* mrfc */ - u64 rx_length_errors; /* rlec */ - u64 link_xon_rx; /* lxonrxc */ - u64 link_xoff_rx; /* lxoffrxc */ - u64 priority_xon_rx[8]; /* pxonrxc[8] */ - u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ - u64 link_xon_tx; /* lxontxc */ - u64 link_xoff_tx; /* lxofftxc */ - u64 priority_xon_tx[8]; /* pxontxc[8] */ - u64 priority_xoff_tx[8]; /* pxofftxc[8] */ - u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ - u64 rx_size_64; /* prc64 */ - u64 rx_size_127; /* prc127 */ - u64 rx_size_255; /* prc255 */ - u64 rx_size_511; /* prc511 */ - u64 rx_size_1023; /* prc1023 */ - u64 rx_size_1522; /* prc1522 */ - u64 rx_size_big; /* prc9522 */ - u64 rx_undersize; /* ruc */ - u64 rx_fragments; /* rfc */ - u64 rx_oversize; /* roc */ - u64 rx_jabber; /* rjc */ - u64 tx_size_64; /* ptc64 */ - u64 tx_size_127; /* ptc127 */ - u64 tx_size_255; /* ptc255 */ - u64 tx_size_511; /* ptc511 */ - u64 tx_size_1023; /* ptc1023 */ - u64 tx_size_1522; /* ptc1522 */ - u64 tx_size_big; /* ptc9522 */ - u64 mac_short_packet_dropped; /* mspdc */ - u64 checksum_error; /* xec */ - /* flow director stats */ - u64 fd_atr_match; - u64 fd_sb_match; - u64 fd_atr_tunnel_match; - u32 fd_atr_status; - u32 fd_sb_status; - /* EEE LPI */ - u32 tx_lpi_status; - u32 rx_lpi_status; - u64 tx_lpi_count; /* etlpic */ - u64 rx_lpi_count; /* erlpic */ -}; - -/* Checksum and Shadow RAM pointers */ -#define I40E_SR_NVM_CONTROL_WORD 0x00 -#define I40E_EMP_MODULE_PTR 0x0F -#define I40E_SR_EMP_MODULE_PTR 0x48 -#define I40E_NVM_OEM_VER_OFF 0x83 -#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 -#define I40E_SR_NVM_WAKE_ON_LAN 0x19 -#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 -#define I40E_SR_NVM_EETRACK_LO 0x2D -#define I40E_SR_NVM_EETRACK_HI 0x2E -#define I40E_SR_VPD_PTR 0x2F -#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E -#define I40E_SR_SW_CHECKSUM_WORD 0x3F - -/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ -#define I40E_SR_VPD_MODULE_MAX_SIZE 1024 -#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 -#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 -#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) -#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) -#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) -#define I40E_PTR_TYPE BIT(15) - -/* Shadow RAM related */ -#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 -#define I40E_SR_WORDS_IN_1KB 512 -/* Checksum should be calculated such that after adding all the words, - * including the checksum word itself, the sum should be 0xBABA. - */ -#define I40E_SR_SW_CHECKSUM_BASE 0xBABA - -#define I40E_SRRD_SRCTL_ATTEMPTS 100000 - -enum i40e_switch_element_types { - I40E_SWITCH_ELEMENT_TYPE_MAC = 1, - I40E_SWITCH_ELEMENT_TYPE_PF = 2, - I40E_SWITCH_ELEMENT_TYPE_VF = 3, - I40E_SWITCH_ELEMENT_TYPE_EMP = 4, - I40E_SWITCH_ELEMENT_TYPE_BMC = 6, - I40E_SWITCH_ELEMENT_TYPE_PE = 16, - I40E_SWITCH_ELEMENT_TYPE_VEB = 17, - I40E_SWITCH_ELEMENT_TYPE_PA = 18, - I40E_SWITCH_ELEMENT_TYPE_VSI = 19, -}; - -/* Supported EtherType filters */ -enum i40e_ether_type_index { - I40E_ETHER_TYPE_1588 = 0, - I40E_ETHER_TYPE_FIP = 1, - I40E_ETHER_TYPE_OUI_EXTENDED = 2, - I40E_ETHER_TYPE_MAC_CONTROL = 3, - I40E_ETHER_TYPE_LLDP = 4, - I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, - I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, - I40E_ETHER_TYPE_QCN_CNM = 7, - I40E_ETHER_TYPE_8021X = 8, - I40E_ETHER_TYPE_ARP = 9, - I40E_ETHER_TYPE_RSV1 = 10, - I40E_ETHER_TYPE_RSV2 = 11, -}; - -/* Filter context base size is 1K */ -#define I40E_HASH_FILTER_BASE_SIZE 1024 -/* Supported Hash filter values */ -enum i40e_hash_filter_size { - I40E_HASH_FILTER_SIZE_1K = 0, - I40E_HASH_FILTER_SIZE_2K = 1, - I40E_HASH_FILTER_SIZE_4K = 2, - I40E_HASH_FILTER_SIZE_8K = 3, - I40E_HASH_FILTER_SIZE_16K = 4, - I40E_HASH_FILTER_SIZE_32K = 5, - I40E_HASH_FILTER_SIZE_64K = 6, - I40E_HASH_FILTER_SIZE_128K = 7, - I40E_HASH_FILTER_SIZE_256K = 8, - I40E_HASH_FILTER_SIZE_512K = 9, - I40E_HASH_FILTER_SIZE_1M = 10, -}; - -/* DMA context base size is 0.5K */ -#define I40E_DMA_CNTX_BASE_SIZE 512 -/* Supported DMA context values */ -enum i40e_dma_cntx_size { - I40E_DMA_CNTX_SIZE_512 = 0, - I40E_DMA_CNTX_SIZE_1K = 1, - I40E_DMA_CNTX_SIZE_2K = 2, - I40E_DMA_CNTX_SIZE_4K = 3, - I40E_DMA_CNTX_SIZE_8K = 4, - I40E_DMA_CNTX_SIZE_16K = 5, - I40E_DMA_CNTX_SIZE_32K = 6, - I40E_DMA_CNTX_SIZE_64K = 7, - I40E_DMA_CNTX_SIZE_128K = 8, - I40E_DMA_CNTX_SIZE_256K = 9, -}; - -/* Supported Hash look up table (LUT) sizes */ -enum i40e_hash_lut_size { - I40E_HASH_LUT_SIZE_128 = 0, - I40E_HASH_LUT_SIZE_512 = 1, -}; - -/* Structure to hold a per PF filter control settings */ -struct i40e_filter_control_settings { - /* number of PE Quad Hash filter buckets */ - enum i40e_hash_filter_size pe_filt_num; - /* number of PE Quad Hash contexts */ - enum i40e_dma_cntx_size pe_cntx_num; - /* number of FCoE filter buckets */ - enum i40e_hash_filter_size fcoe_filt_num; - /* number of FCoE DDP contexts */ - enum i40e_dma_cntx_size fcoe_cntx_num; - /* size of the Hash LUT */ - enum i40e_hash_lut_size hash_lut_size; - /* enable FDIR filters for PF and its VFs */ - bool enable_fdir; - /* enable Ethertype filters for PF and its VFs */ - bool enable_ethtype; - /* enable MAC/VLAN filters for PF and its VFs */ - bool enable_macvlan; -}; - -/* Structure to hold device level control filter counts */ -struct i40e_control_filter_stats { - u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ - u16 etype_used; /* Used perfect EtherType filters */ - u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ - u16 etype_free; /* Un-used perfect EtherType filters */ -}; - -enum i40e_reset_type { - I40E_RESET_POR = 0, - I40E_RESET_CORER = 1, - I40E_RESET_GLOBR = 2, - I40E_RESET_EMPR = 3, -}; - -/* IEEE 802.1AB LLDP Agent Variables from NVM */ -#define I40E_NVM_LLDP_CFG_PTR 0x06 -#define I40E_SR_LLDP_CFG_PTR 0x31 - -/* RSS Hash Table Size */ -#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 - -/* INPUT SET MASK for RSS, flow director and flexible payload */ -#define I40E_FD_INSET_L3_SRC_SHIFT 47 -#define I40E_FD_INSET_L3_SRC_WORD_MASK (0x3ULL << \ - I40E_FD_INSET_L3_SRC_SHIFT) -#define I40E_FD_INSET_L3_DST_SHIFT 35 -#define I40E_FD_INSET_L3_DST_WORD_MASK (0x3ULL << \ - I40E_FD_INSET_L3_DST_SHIFT) -#define I40E_FD_INSET_L4_SRC_SHIFT 34 -#define I40E_FD_INSET_L4_SRC_WORD_MASK (0x1ULL << \ - I40E_FD_INSET_L4_SRC_SHIFT) -#define I40E_FD_INSET_L4_DST_SHIFT 33 -#define I40E_FD_INSET_L4_DST_WORD_MASK (0x1ULL << \ - I40E_FD_INSET_L4_DST_SHIFT) -#define I40E_FD_INSET_VERIFY_TAG_SHIFT 31 -#define I40E_FD_INSET_VERIFY_TAG_WORD_MASK (0x3ULL << \ - I40E_FD_INSET_VERIFY_TAG_SHIFT) - -#define I40E_FD_INSET_FLEX_WORD50_SHIFT 17 -#define I40E_FD_INSET_FLEX_WORD50_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD50_SHIFT) -#define I40E_FD_INSET_FLEX_WORD51_SHIFT 16 -#define I40E_FD_INSET_FLEX_WORD51_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD51_SHIFT) -#define I40E_FD_INSET_FLEX_WORD52_SHIFT 15 -#define I40E_FD_INSET_FLEX_WORD52_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD52_SHIFT) -#define I40E_FD_INSET_FLEX_WORD53_SHIFT 14 -#define I40E_FD_INSET_FLEX_WORD53_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD53_SHIFT) -#define I40E_FD_INSET_FLEX_WORD54_SHIFT 13 -#define I40E_FD_INSET_FLEX_WORD54_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD54_SHIFT) -#define I40E_FD_INSET_FLEX_WORD55_SHIFT 12 -#define I40E_FD_INSET_FLEX_WORD55_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD55_SHIFT) -#define I40E_FD_INSET_FLEX_WORD56_SHIFT 11 -#define I40E_FD_INSET_FLEX_WORD56_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD56_SHIFT) -#define I40E_FD_INSET_FLEX_WORD57_SHIFT 10 -#define I40E_FD_INSET_FLEX_WORD57_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD57_SHIFT) - -/* Version format for Dynamic Device Personalization(DDP) */ -struct i40e_ddp_version { - u8 major; - u8 minor; - u8 update; - u8 draft; -}; - -#define I40E_DDP_NAME_SIZE 32 - -/* Package header */ -struct i40e_package_header { - struct i40e_ddp_version version; - u32 segment_count; - u32 segment_offset[1]; -}; - -/* Generic segment header */ -struct i40e_generic_seg_header { -#define SEGMENT_TYPE_METADATA 0x00000001 -#define SEGMENT_TYPE_NOTES 0x00000002 -#define SEGMENT_TYPE_I40E 0x00000011 -#define SEGMENT_TYPE_X722 0x00000012 - u32 type; - struct i40e_ddp_version version; - u32 size; - char name[I40E_DDP_NAME_SIZE]; -}; - -struct i40e_metadata_segment { - struct i40e_generic_seg_header header; - struct i40e_ddp_version version; - u32 track_id; - char name[I40E_DDP_NAME_SIZE]; -}; - -struct i40e_device_id_entry { - u32 vendor_dev_id; - u32 sub_vendor_dev_id; -}; - -struct i40e_profile_segment { - struct i40e_generic_seg_header header; - struct i40e_ddp_version version; - char name[I40E_DDP_NAME_SIZE]; - u32 device_table_count; - struct i40e_device_id_entry device_table[1]; -}; - -struct i40e_section_table { - u32 section_count; - u32 section_offset[1]; -}; - -struct i40e_profile_section_header { - u16 tbl_size; - u16 data_end; - struct { -#define SECTION_TYPE_INFO 0x00000010 -#define SECTION_TYPE_MMIO 0x00000800 -#define SECTION_TYPE_AQ 0x00000801 -#define SECTION_TYPE_NOTE 0x80000000 -#define SECTION_TYPE_NAME 0x80000001 - u32 type; - u32 offset; - u32 size; - } section; -}; - -struct i40e_profile_info { - u32 track_id; - struct i40e_ddp_version version; - u8 op; -#define I40E_DDP_ADD_TRACKID 0x01 -#define I40E_DDP_REMOVE_TRACKID 0x02 - u8 reserved[7]; - u8 name[I40E_DDP_NAME_SIZE]; -}; -#endif /* _I40E_TYPE_H_ */ diff --git a/drivers/net/ethernet/intel/iavf/Makefile b/drivers/net/ethernet/intel/iavf/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..1b050d9d5f493f023300dac3796c160645dd8a6f --- /dev/null +++ b/drivers/net/ethernet/intel/iavf/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright(c) 2013 - 2018 Intel Corporation. +# +# Makefile for the Intel(R) Ethernet Adaptive Virtual Function (iavf) +# driver +# +# + +ccflags-y += -I$(src) +subdir-ccflags-y += -I$(src) + +obj-$(CONFIG_IAVF) += iavf.o + +iavf-objs := i40evf_main.o i40evf_ethtool.o i40evf_virtchnl.o \ + i40e_txrx.o i40e_common.o i40e_adminq.o i40evf_client.o diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c b/drivers/net/ethernet/intel/iavf/i40e_adminq.c similarity index 97% rename from drivers/net/ethernet/intel/i40evf/i40e_adminq.c rename to drivers/net/ethernet/intel/iavf/i40e_adminq.c index 21a0dbf6ccf613dd2b9a5d79b81ebb34bf346a14..32e0e2d9cdc53dcc65ff957a0e0c9ef29221c2fe 100644 --- a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c +++ b/drivers/net/ethernet/intel/iavf/i40e_adminq.c @@ -7,16 +7,6 @@ #include "i40e_adminq.h" #include "i40e_prototype.h" -/** - * i40e_is_nvm_update_op - return true if this is an NVM update operation - * @desc: API request descriptor - **/ -static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc) -{ - return (desc->opcode == i40e_aqc_opc_nvm_erase) || - (desc->opcode == i40e_aqc_opc_nvm_update); -} - /** * i40e_adminq_init_regs - Initialize AdminQ registers * @hw: pointer to the hardware structure @@ -569,9 +559,6 @@ i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw) i40e_shutdown_asq(hw); i40e_shutdown_arq(hw); - if (hw->nvm_buff.va) - i40e_free_virt_mem(hw, &hw->nvm_buff); - return ret_code; } @@ -951,17 +938,3 @@ i40e_status i40evf_clean_arq_element(struct i40e_hw *hw, return ret_code; } - -void i40evf_resume_aq(struct i40e_hw *hw) -{ - /* Registers are reset after PF reset */ - hw->aq.asq.next_to_use = 0; - hw->aq.asq.next_to_clean = 0; - - i40e_config_asq_regs(hw); - - hw->aq.arq.next_to_use = 0; - hw->aq.arq.next_to_clean = 0; - - i40e_config_arq_regs(hw); -} diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq.h b/drivers/net/ethernet/intel/iavf/i40e_adminq.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_adminq.h rename to drivers/net/ethernet/intel/iavf/i40e_adminq.h diff --git a/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h new file mode 100644 index 0000000000000000000000000000000000000000..493bdc5331f7bc17a845fbd32a6ff056888f0889 --- /dev/null +++ b/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h @@ -0,0 +1,528 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2013 - 2018 Intel Corporation. */ + +#ifndef _I40E_ADMINQ_CMD_H_ +#define _I40E_ADMINQ_CMD_H_ + +/* This header file defines the i40e Admin Queue commands and is shared between + * i40e Firmware and Software. + * + * This file needs to comply with the Linux Kernel coding style. + */ + +#define I40E_FW_API_VERSION_MAJOR 0x0001 +#define I40E_FW_API_VERSION_MINOR_X722 0x0005 +#define I40E_FW_API_VERSION_MINOR_X710 0x0007 + +#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ + I40E_FW_API_VERSION_MINOR_X710 : \ + I40E_FW_API_VERSION_MINOR_X722) + +/* API version 1.7 implements additional link and PHY-specific APIs */ +#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 + +struct i40e_aq_desc { + __le16 flags; + __le16 opcode; + __le16 datalen; + __le16 retval; + __le32 cookie_high; + __le32 cookie_low; + union { + struct { + __le32 param0; + __le32 param1; + __le32 param2; + __le32 param3; + } internal; + struct { + __le32 param0; + __le32 param1; + __le32 addr_high; + __le32 addr_low; + } external; + u8 raw[16]; + } params; +}; + +/* Flags sub-structure + * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | + * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | + */ + +/* command flags and offsets*/ +#define I40E_AQ_FLAG_DD_SHIFT 0 +#define I40E_AQ_FLAG_CMP_SHIFT 1 +#define I40E_AQ_FLAG_ERR_SHIFT 2 +#define I40E_AQ_FLAG_VFE_SHIFT 3 +#define I40E_AQ_FLAG_LB_SHIFT 9 +#define I40E_AQ_FLAG_RD_SHIFT 10 +#define I40E_AQ_FLAG_VFC_SHIFT 11 +#define I40E_AQ_FLAG_BUF_SHIFT 12 +#define I40E_AQ_FLAG_SI_SHIFT 13 +#define I40E_AQ_FLAG_EI_SHIFT 14 +#define I40E_AQ_FLAG_FE_SHIFT 15 + +#define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ +#define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ +#define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ +#define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ +#define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ +#define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ +#define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ +#define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ +#define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ +#define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ +#define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ + +/* error codes */ +enum i40e_admin_queue_err { + I40E_AQ_RC_OK = 0, /* success */ + I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ + I40E_AQ_RC_ENOENT = 2, /* No such element */ + I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ + I40E_AQ_RC_EINTR = 4, /* operation interrupted */ + I40E_AQ_RC_EIO = 5, /* I/O error */ + I40E_AQ_RC_ENXIO = 6, /* No such resource */ + I40E_AQ_RC_E2BIG = 7, /* Arg too long */ + I40E_AQ_RC_EAGAIN = 8, /* Try again */ + I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ + I40E_AQ_RC_EACCES = 10, /* Permission denied */ + I40E_AQ_RC_EFAULT = 11, /* Bad address */ + I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ + I40E_AQ_RC_EEXIST = 13, /* object already exists */ + I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ + I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ + I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ + I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ + I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ + I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ + I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ + I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ + I40E_AQ_RC_EFBIG = 22, /* File too large */ +}; + +/* Admin Queue command opcodes */ +enum i40e_admin_queue_opc { + /* aq commands */ + i40e_aqc_opc_get_version = 0x0001, + i40e_aqc_opc_driver_version = 0x0002, + i40e_aqc_opc_queue_shutdown = 0x0003, + i40e_aqc_opc_set_pf_context = 0x0004, + + /* resource ownership */ + i40e_aqc_opc_request_resource = 0x0008, + i40e_aqc_opc_release_resource = 0x0009, + + i40e_aqc_opc_list_func_capabilities = 0x000A, + i40e_aqc_opc_list_dev_capabilities = 0x000B, + + /* Proxy commands */ + i40e_aqc_opc_set_proxy_config = 0x0104, + i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, + + /* LAA */ + i40e_aqc_opc_mac_address_read = 0x0107, + i40e_aqc_opc_mac_address_write = 0x0108, + + /* PXE */ + i40e_aqc_opc_clear_pxe_mode = 0x0110, + + /* WoL commands */ + i40e_aqc_opc_set_wol_filter = 0x0120, + i40e_aqc_opc_get_wake_reason = 0x0121, + + /* internal switch commands */ + i40e_aqc_opc_get_switch_config = 0x0200, + i40e_aqc_opc_add_statistics = 0x0201, + i40e_aqc_opc_remove_statistics = 0x0202, + i40e_aqc_opc_set_port_parameters = 0x0203, + i40e_aqc_opc_get_switch_resource_alloc = 0x0204, + i40e_aqc_opc_set_switch_config = 0x0205, + i40e_aqc_opc_rx_ctl_reg_read = 0x0206, + i40e_aqc_opc_rx_ctl_reg_write = 0x0207, + + i40e_aqc_opc_add_vsi = 0x0210, + i40e_aqc_opc_update_vsi_parameters = 0x0211, + i40e_aqc_opc_get_vsi_parameters = 0x0212, + + i40e_aqc_opc_add_pv = 0x0220, + i40e_aqc_opc_update_pv_parameters = 0x0221, + i40e_aqc_opc_get_pv_parameters = 0x0222, + + i40e_aqc_opc_add_veb = 0x0230, + i40e_aqc_opc_update_veb_parameters = 0x0231, + i40e_aqc_opc_get_veb_parameters = 0x0232, + + i40e_aqc_opc_delete_element = 0x0243, + + i40e_aqc_opc_add_macvlan = 0x0250, + i40e_aqc_opc_remove_macvlan = 0x0251, + i40e_aqc_opc_add_vlan = 0x0252, + i40e_aqc_opc_remove_vlan = 0x0253, + i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, + i40e_aqc_opc_add_tag = 0x0255, + i40e_aqc_opc_remove_tag = 0x0256, + i40e_aqc_opc_add_multicast_etag = 0x0257, + i40e_aqc_opc_remove_multicast_etag = 0x0258, + i40e_aqc_opc_update_tag = 0x0259, + i40e_aqc_opc_add_control_packet_filter = 0x025A, + i40e_aqc_opc_remove_control_packet_filter = 0x025B, + i40e_aqc_opc_add_cloud_filters = 0x025C, + i40e_aqc_opc_remove_cloud_filters = 0x025D, + i40e_aqc_opc_clear_wol_switch_filters = 0x025E, + + i40e_aqc_opc_add_mirror_rule = 0x0260, + i40e_aqc_opc_delete_mirror_rule = 0x0261, + + /* Dynamic Device Personalization */ + i40e_aqc_opc_write_personalization_profile = 0x0270, + i40e_aqc_opc_get_personalization_profile_list = 0x0271, + + /* DCB commands */ + i40e_aqc_opc_dcb_ignore_pfc = 0x0301, + i40e_aqc_opc_dcb_updated = 0x0302, + i40e_aqc_opc_set_dcb_parameters = 0x0303, + + /* TX scheduler */ + i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, + i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, + i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, + i40e_aqc_opc_query_vsi_bw_config = 0x0408, + i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, + i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, + + i40e_aqc_opc_enable_switching_comp_ets = 0x0413, + i40e_aqc_opc_modify_switching_comp_ets = 0x0414, + i40e_aqc_opc_disable_switching_comp_ets = 0x0415, + i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, + i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, + i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, + i40e_aqc_opc_query_port_ets_config = 0x0419, + i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, + i40e_aqc_opc_suspend_port_tx = 0x041B, + i40e_aqc_opc_resume_port_tx = 0x041C, + i40e_aqc_opc_configure_partition_bw = 0x041D, + /* hmc */ + i40e_aqc_opc_query_hmc_resource_profile = 0x0500, + i40e_aqc_opc_set_hmc_resource_profile = 0x0501, + + /* phy commands*/ + i40e_aqc_opc_get_phy_abilities = 0x0600, + i40e_aqc_opc_set_phy_config = 0x0601, + i40e_aqc_opc_set_mac_config = 0x0603, + i40e_aqc_opc_set_link_restart_an = 0x0605, + i40e_aqc_opc_get_link_status = 0x0607, + i40e_aqc_opc_set_phy_int_mask = 0x0613, + i40e_aqc_opc_get_local_advt_reg = 0x0614, + i40e_aqc_opc_set_local_advt_reg = 0x0615, + i40e_aqc_opc_get_partner_advt = 0x0616, + i40e_aqc_opc_set_lb_modes = 0x0618, + i40e_aqc_opc_get_phy_wol_caps = 0x0621, + i40e_aqc_opc_set_phy_debug = 0x0622, + i40e_aqc_opc_upload_ext_phy_fm = 0x0625, + i40e_aqc_opc_run_phy_activity = 0x0626, + i40e_aqc_opc_set_phy_register = 0x0628, + i40e_aqc_opc_get_phy_register = 0x0629, + + /* NVM commands */ + i40e_aqc_opc_nvm_read = 0x0701, + i40e_aqc_opc_nvm_erase = 0x0702, + i40e_aqc_opc_nvm_update = 0x0703, + i40e_aqc_opc_nvm_config_read = 0x0704, + i40e_aqc_opc_nvm_config_write = 0x0705, + i40e_aqc_opc_oem_post_update = 0x0720, + i40e_aqc_opc_thermal_sensor = 0x0721, + + /* virtualization commands */ + i40e_aqc_opc_send_msg_to_pf = 0x0801, + i40e_aqc_opc_send_msg_to_vf = 0x0802, + i40e_aqc_opc_send_msg_to_peer = 0x0803, + + /* alternate structure */ + i40e_aqc_opc_alternate_write = 0x0900, + i40e_aqc_opc_alternate_write_indirect = 0x0901, + i40e_aqc_opc_alternate_read = 0x0902, + i40e_aqc_opc_alternate_read_indirect = 0x0903, + i40e_aqc_opc_alternate_write_done = 0x0904, + i40e_aqc_opc_alternate_set_mode = 0x0905, + i40e_aqc_opc_alternate_clear_port = 0x0906, + + /* LLDP commands */ + i40e_aqc_opc_lldp_get_mib = 0x0A00, + i40e_aqc_opc_lldp_update_mib = 0x0A01, + i40e_aqc_opc_lldp_add_tlv = 0x0A02, + i40e_aqc_opc_lldp_update_tlv = 0x0A03, + i40e_aqc_opc_lldp_delete_tlv = 0x0A04, + i40e_aqc_opc_lldp_stop = 0x0A05, + i40e_aqc_opc_lldp_start = 0x0A06, + + /* Tunnel commands */ + i40e_aqc_opc_add_udp_tunnel = 0x0B00, + i40e_aqc_opc_del_udp_tunnel = 0x0B01, + i40e_aqc_opc_set_rss_key = 0x0B02, + i40e_aqc_opc_set_rss_lut = 0x0B03, + i40e_aqc_opc_get_rss_key = 0x0B04, + i40e_aqc_opc_get_rss_lut = 0x0B05, + + /* Async Events */ + i40e_aqc_opc_event_lan_overflow = 0x1001, + + /* OEM commands */ + i40e_aqc_opc_oem_parameter_change = 0xFE00, + i40e_aqc_opc_oem_device_status_change = 0xFE01, + i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, + i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, + + /* debug commands */ + i40e_aqc_opc_debug_read_reg = 0xFF03, + i40e_aqc_opc_debug_write_reg = 0xFF04, + i40e_aqc_opc_debug_modify_reg = 0xFF07, + i40e_aqc_opc_debug_dump_internals = 0xFF08, +}; + +/* command structures and indirect data structures */ + +/* Structure naming conventions: + * - no suffix for direct command descriptor structures + * - _data for indirect sent data + * - _resp for indirect return data (data which is both will use _data) + * - _completion for direct return data + * - _element_ for repeated elements (may also be _data or _resp) + * + * Command structures are expected to overlay the params.raw member of the basic + * descriptor, and as such cannot exceed 16 bytes in length. + */ + +/* This macro is used to generate a compilation error if a structure + * is not exactly the correct length. It gives a divide by zero error if the + * structure is not of the correct size, otherwise it creates an enum that is + * never used. + */ +#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ + { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } + +/* This macro is used extensively to ensure that command structures are 16 + * bytes in length as they have to map to the raw array of that size. + */ +#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) + +/* Queue Shutdown (direct 0x0003) */ +struct i40e_aqc_queue_shutdown { + __le32 driver_unloading; +#define I40E_AQ_DRIVER_UNLOADING 0x1 + u8 reserved[12]; +}; + +I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); + +struct i40e_aqc_vsi_properties_data { + /* first 96 byte are written by SW */ + __le16 valid_sections; +#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 +#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 +#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 +#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 +#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 +#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 +#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 +#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 +#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 +#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 + /* switch section */ + __le16 switch_id; /* 12bit id combined with flags below */ +#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 +#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) +#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 +#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 +#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 + u8 sw_reserved[2]; + /* security section */ + u8 sec_flags; +#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 +#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 +#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 + u8 sec_reserved; + /* VLAN section */ + __le16 pvid; /* VLANS include priority bits */ + __le16 fcoe_pvid; + u8 port_vlan_flags; +#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 +#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ + I40E_AQ_VSI_PVLAN_MODE_SHIFT) +#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 +#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 +#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 +#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 +#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 +#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ + I40E_AQ_VSI_PVLAN_EMOD_SHIFT) +#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 +#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 +#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 +#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 + u8 pvlan_reserved[3]; + /* ingress egress up sections */ + __le32 ingress_table; /* bitmap, 3 bits per up */ +#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 +#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ + I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) +#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 +#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ + I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) +#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 +#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ + I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) +#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 +#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ + I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) +#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 +#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ + I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) +#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 +#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ + I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) +#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 +#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ + I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) +#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 +#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ + I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) + __le32 egress_table; /* same defines as for ingress table */ + /* cascaded PV section */ + __le16 cas_pv_tag; + u8 cas_pv_flags; +#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 +#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ + I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) +#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 +#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 +#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 +#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 +#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 +#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 + u8 cas_pv_reserved; + /* queue mapping section */ + __le16 mapping_flags; +#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 +#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 + __le16 queue_mapping[16]; +#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 +#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) + __le16 tc_mapping[8]; +#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 +#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ + I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) +#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 +#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ + I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) + /* queueing option section */ + u8 queueing_opt_flags; +#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 +#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 +#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 +#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 +#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 +#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 + u8 queueing_opt_reserved[3]; + /* scheduler section */ + u8 up_enable_bits; + u8 sched_reserved; + /* outer up section */ + __le32 outer_up_table; /* same structure and defines as ingress tbl */ + u8 cmd_reserved[8]; + /* last 32 bytes are written by FW */ + __le16 qs_handle[8]; +#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF + __le16 stat_counter_idx; + __le16 sched_id; + u8 resp_reserved[12]; +}; + +I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); + +/* Get VEB Parameters (direct 0x0232) + * uses i40e_aqc_switch_seid for the descriptor + */ +struct i40e_aqc_get_veb_parameters_completion { + __le16 seid; + __le16 switch_id; + __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ + __le16 statistic_index; + __le16 vebs_used; + __le16 vebs_free; + u8 reserved[4]; +}; + +I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); + +#define I40E_LINK_SPEED_100MB_SHIFT 0x1 +#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 +#define I40E_LINK_SPEED_10GB_SHIFT 0x3 +#define I40E_LINK_SPEED_40GB_SHIFT 0x4 +#define I40E_LINK_SPEED_20GB_SHIFT 0x5 +#define I40E_LINK_SPEED_25GB_SHIFT 0x6 + +enum i40e_aq_link_speed { + I40E_LINK_SPEED_UNKNOWN = 0, + I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), + I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), + I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), + I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), + I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), + I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), +}; + +/* Send to PF command (indirect 0x0801) id is only used by PF + * Send to VF command (indirect 0x0802) id is only used by PF + * Send to Peer PF command (indirect 0x0803) + */ +struct i40e_aqc_pf_vf_message { + __le32 id; + u8 reserved[4]; + __le32 addr_high; + __le32 addr_low; +}; + +I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); + +struct i40e_aqc_get_set_rss_key { +#define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) +#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 +#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ + I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) + __le16 vsi_id; + u8 reserved[6]; + __le32 addr_high; + __le32 addr_low; +}; + +I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); + +struct i40e_aqc_get_set_rss_key_data { + u8 standard_rss_key[0x28]; + u8 extended_hash_key[0xc]; +}; + +I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); + +struct i40e_aqc_get_set_rss_lut { +#define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) +#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 +#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ + I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) + __le16 vsi_id; +#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 +#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \ + BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) + +#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 +#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 + __le16 flags; + u8 reserved[4]; + __le32 addr_high; + __le32 addr_low; +}; + +I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); +#endif /* _I40E_ADMINQ_CMD_H_ */ diff --git a/drivers/net/ethernet/intel/i40evf/i40e_alloc.h b/drivers/net/ethernet/intel/iavf/i40e_alloc.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_alloc.h rename to drivers/net/ethernet/intel/iavf/i40e_alloc.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_common.c b/drivers/net/ethernet/intel/iavf/i40e_common.c similarity index 77% rename from drivers/net/ethernet/intel/i40evf/i40e_common.c rename to drivers/net/ethernet/intel/iavf/i40e_common.c index eea280ba411ee116c763bed063b75fef46763776..f34091d96f490d6a5741e19f1e21d3845bcf504e 100644 --- a/drivers/net/ethernet/intel/i40evf/i40e_common.c +++ b/drivers/net/ethernet/intel/iavf/i40e_common.c @@ -525,7 +525,6 @@ i40e_status i40evf_aq_set_rss_key(struct i40e_hw *hw, return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); } - /* The i40evf_ptype_lookup table is used to convert from the 8-bit ptype in the * hardware to a bit-field that can be used by SW to more easily determine the * packet type. @@ -891,135 +890,6 @@ struct i40e_rx_ptype_decoded i40evf_ptype_lookup[] = { I40E_PTT_UNUSED_ENTRY(255) }; -/** - * i40evf_aq_rx_ctl_read_register - use FW to read from an Rx control register - * @hw: pointer to the hw struct - * @reg_addr: register address - * @reg_val: ptr to register value - * @cmd_details: pointer to command details structure or NULL - * - * Use the firmware to read the Rx control register, - * especially useful if the Rx unit is under heavy pressure - **/ -i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw, - u32 reg_addr, u32 *reg_val, - struct i40e_asq_cmd_details *cmd_details) -{ - struct i40e_aq_desc desc; - struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = - (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; - i40e_status status; - - if (!reg_val) - return I40E_ERR_PARAM; - - i40evf_fill_default_direct_cmd_desc(&desc, - i40e_aqc_opc_rx_ctl_reg_read); - - cmd_resp->address = cpu_to_le32(reg_addr); - - status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details); - - if (status == 0) - *reg_val = le32_to_cpu(cmd_resp->value); - - return status; -} - -/** - * i40evf_read_rx_ctl - read from an Rx control register - * @hw: pointer to the hw struct - * @reg_addr: register address - **/ -u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) -{ - i40e_status status = 0; - bool use_register; - int retry = 5; - u32 val = 0; - - use_register = (((hw->aq.api_maj_ver == 1) && - (hw->aq.api_min_ver < 5)) || - (hw->mac.type == I40E_MAC_X722)); - if (!use_register) { -do_retry: - status = i40evf_aq_rx_ctl_read_register(hw, reg_addr, - &val, NULL); - if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { - usleep_range(1000, 2000); - retry--; - goto do_retry; - } - } - - /* if the AQ access failed, try the old-fashioned way */ - if (status || use_register) - val = rd32(hw, reg_addr); - - return val; -} - -/** - * i40evf_aq_rx_ctl_write_register - * @hw: pointer to the hw struct - * @reg_addr: register address - * @reg_val: register value - * @cmd_details: pointer to command details structure or NULL - * - * Use the firmware to write to an Rx control register, - * especially useful if the Rx unit is under heavy pressure - **/ -i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw, - u32 reg_addr, u32 reg_val, - struct i40e_asq_cmd_details *cmd_details) -{ - struct i40e_aq_desc desc; - struct i40e_aqc_rx_ctl_reg_read_write *cmd = - (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; - i40e_status status; - - i40evf_fill_default_direct_cmd_desc(&desc, - i40e_aqc_opc_rx_ctl_reg_write); - - cmd->address = cpu_to_le32(reg_addr); - cmd->value = cpu_to_le32(reg_val); - - status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details); - - return status; -} - -/** - * i40evf_write_rx_ctl - write to an Rx control register - * @hw: pointer to the hw struct - * @reg_addr: register address - * @reg_val: register value - **/ -void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) -{ - i40e_status status = 0; - bool use_register; - int retry = 5; - - use_register = (((hw->aq.api_maj_ver == 1) && - (hw->aq.api_min_ver < 5)) || - (hw->mac.type == I40E_MAC_X722)); - if (!use_register) { -do_retry: - status = i40evf_aq_rx_ctl_write_register(hw, reg_addr, - reg_val, NULL); - if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { - usleep_range(1000, 2000); - retry--; - goto do_retry; - } - } - - /* if the AQ access failed, try the old-fashioned way */ - if (status || use_register) - wr32(hw, reg_addr, reg_val); -} - /** * i40e_aq_send_msg_to_pf * @hw: pointer to the hardware structure @@ -1110,211 +980,3 @@ i40e_status i40e_vf_reset(struct i40e_hw *hw) return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF, 0, NULL, 0, NULL); } - -/** - * i40evf_aq_write_ddp - Write dynamic device personalization (ddp) - * @hw: pointer to the hw struct - * @buff: command buffer (size in bytes = buff_size) - * @buff_size: buffer size in bytes - * @track_id: package tracking id - * @error_offset: returns error offset - * @error_info: returns error information - * @cmd_details: pointer to command details structure or NULL - **/ -enum -i40e_status_code i40evf_aq_write_ddp(struct i40e_hw *hw, void *buff, - u16 buff_size, u32 track_id, - u32 *error_offset, u32 *error_info, - struct i40e_asq_cmd_details *cmd_details) -{ - struct i40e_aq_desc desc; - struct i40e_aqc_write_personalization_profile *cmd = - (struct i40e_aqc_write_personalization_profile *) - &desc.params.raw; - struct i40e_aqc_write_ddp_resp *resp; - i40e_status status; - - i40evf_fill_default_direct_cmd_desc(&desc, - i40e_aqc_opc_write_personalization_profile); - - desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); - if (buff_size > I40E_AQ_LARGE_BUF) - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); - - desc.datalen = cpu_to_le16(buff_size); - - cmd->profile_track_id = cpu_to_le32(track_id); - - status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details); - if (!status) { - resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; - if (error_offset) - *error_offset = le32_to_cpu(resp->error_offset); - if (error_info) - *error_info = le32_to_cpu(resp->error_info); - } - - return status; -} - -/** - * i40evf_aq_get_ddp_list - Read dynamic device personalization (ddp) - * @hw: pointer to the hw struct - * @buff: command buffer (size in bytes = buff_size) - * @buff_size: buffer size in bytes - * @flags: AdminQ command flags - * @cmd_details: pointer to command details structure or NULL - **/ -enum -i40e_status_code i40evf_aq_get_ddp_list(struct i40e_hw *hw, void *buff, - u16 buff_size, u8 flags, - struct i40e_asq_cmd_details *cmd_details) -{ - struct i40e_aq_desc desc; - struct i40e_aqc_get_applied_profiles *cmd = - (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; - i40e_status status; - - i40evf_fill_default_direct_cmd_desc(&desc, - i40e_aqc_opc_get_personalization_profile_list); - - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); - if (buff_size > I40E_AQ_LARGE_BUF) - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); - desc.datalen = cpu_to_le16(buff_size); - - cmd->flags = flags; - - status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details); - - return status; -} - -/** - * i40evf_find_segment_in_package - * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) - * @pkg_hdr: pointer to the package header to be searched - * - * This function searches a package file for a particular segment type. On - * success it returns a pointer to the segment header, otherwise it will - * return NULL. - **/ -struct i40e_generic_seg_header * -i40evf_find_segment_in_package(u32 segment_type, - struct i40e_package_header *pkg_hdr) -{ - struct i40e_generic_seg_header *segment; - u32 i; - - /* Search all package segments for the requested segment type */ - for (i = 0; i < pkg_hdr->segment_count; i++) { - segment = - (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + - pkg_hdr->segment_offset[i]); - - if (segment->type == segment_type) - return segment; - } - - return NULL; -} - -/** - * i40evf_write_profile - * @hw: pointer to the hardware structure - * @profile: pointer to the profile segment of the package to be downloaded - * @track_id: package tracking id - * - * Handles the download of a complete package. - */ -enum i40e_status_code -i40evf_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, - u32 track_id) -{ - i40e_status status = 0; - struct i40e_section_table *sec_tbl; - struct i40e_profile_section_header *sec = NULL; - u32 dev_cnt; - u32 vendor_dev_id; - u32 *nvm; - u32 section_size = 0; - u32 offset = 0, info = 0; - u32 i; - - dev_cnt = profile->device_table_count; - - for (i = 0; i < dev_cnt; i++) { - vendor_dev_id = profile->device_table[i].vendor_dev_id; - if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL) - if (hw->device_id == (vendor_dev_id & 0xFFFF)) - break; - } - if (i == dev_cnt) { - i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP"); - return I40E_ERR_DEVICE_NOT_SUPPORTED; - } - - nvm = (u32 *)&profile->device_table[dev_cnt]; - sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; - - for (i = 0; i < sec_tbl->section_count; i++) { - sec = (struct i40e_profile_section_header *)((u8 *)profile + - sec_tbl->section_offset[i]); - - /* Skip 'AQ', 'note' and 'name' sections */ - if (sec->section.type != SECTION_TYPE_MMIO) - continue; - - section_size = sec->section.size + - sizeof(struct i40e_profile_section_header); - - /* Write profile */ - status = i40evf_aq_write_ddp(hw, (void *)sec, (u16)section_size, - track_id, &offset, &info, NULL); - if (status) { - i40e_debug(hw, I40E_DEBUG_PACKAGE, - "Failed to write profile: offset %d, info %d", - offset, info); - break; - } - } - return status; -} - -/** - * i40evf_add_pinfo_to_list - * @hw: pointer to the hardware structure - * @profile: pointer to the profile segment of the package - * @profile_info_sec: buffer for information section - * @track_id: package tracking id - * - * Register a profile to the list of loaded profiles. - */ -enum i40e_status_code -i40evf_add_pinfo_to_list(struct i40e_hw *hw, - struct i40e_profile_segment *profile, - u8 *profile_info_sec, u32 track_id) -{ - i40e_status status = 0; - struct i40e_profile_section_header *sec = NULL; - struct i40e_profile_info *pinfo; - u32 offset = 0, info = 0; - - sec = (struct i40e_profile_section_header *)profile_info_sec; - sec->tbl_size = 1; - sec->data_end = sizeof(struct i40e_profile_section_header) + - sizeof(struct i40e_profile_info); - sec->section.type = SECTION_TYPE_INFO; - sec->section.offset = sizeof(struct i40e_profile_section_header); - sec->section.size = sizeof(struct i40e_profile_info); - pinfo = (struct i40e_profile_info *)(profile_info_sec + - sec->section.offset); - pinfo->track_id = track_id; - pinfo->version = profile->version; - pinfo->op = I40E_DDP_ADD_TRACKID; - memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE); - - status = i40evf_aq_write_ddp(hw, (void *)sec, sec->data_end, - track_id, &offset, &info, NULL); - return status; -} diff --git a/drivers/net/ethernet/intel/i40evf/i40e_devids.h b/drivers/net/ethernet/intel/iavf/i40e_devids.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_devids.h rename to drivers/net/ethernet/intel/iavf/i40e_devids.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_osdep.h b/drivers/net/ethernet/intel/iavf/i40e_osdep.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_osdep.h rename to drivers/net/ethernet/intel/iavf/i40e_osdep.h diff --git a/drivers/net/ethernet/intel/iavf/i40e_prototype.h b/drivers/net/ethernet/intel/iavf/i40e_prototype.h new file mode 100644 index 0000000000000000000000000000000000000000..ef7f74489bfc0ada28997811e04201b7899604cb --- /dev/null +++ b/drivers/net/ethernet/intel/iavf/i40e_prototype.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2013 - 2018 Intel Corporation. */ + +#ifndef _I40E_PROTOTYPE_H_ +#define _I40E_PROTOTYPE_H_ + +#include "i40e_type.h" +#include "i40e_alloc.h" +#include + +/* Prototypes for shared code functions that are not in + * the standard function pointer structures. These are + * mostly because they are needed even before the init + * has happened and will assist in the early SW and FW + * setup. + */ + +/* adminq functions */ +i40e_status i40evf_init_adminq(struct i40e_hw *hw); +i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw); +void i40e_adminq_init_ring_data(struct i40e_hw *hw); +i40e_status i40evf_clean_arq_element(struct i40e_hw *hw, + struct i40e_arq_event_info *e, + u16 *events_pending); +i40e_status i40evf_asq_send_command(struct i40e_hw *hw, + struct i40e_aq_desc *desc, + void *buff, /* can be NULL */ + u16 buff_size, + struct i40e_asq_cmd_details *cmd_details); +bool i40evf_asq_done(struct i40e_hw *hw); + +/* debug function for adminq */ +void i40evf_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, + void *desc, void *buffer, u16 buf_len); + +void i40e_idle_aq(struct i40e_hw *hw); +void i40evf_resume_aq(struct i40e_hw *hw); +bool i40evf_check_asq_alive(struct i40e_hw *hw); +i40e_status i40evf_aq_queue_shutdown(struct i40e_hw *hw, bool unloading); +const char *i40evf_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err); +const char *i40evf_stat_str(struct i40e_hw *hw, i40e_status stat_err); + +i40e_status i40evf_aq_get_rss_lut(struct i40e_hw *hw, u16 seid, + bool pf_lut, u8 *lut, u16 lut_size); +i40e_status i40evf_aq_set_rss_lut(struct i40e_hw *hw, u16 seid, + bool pf_lut, u8 *lut, u16 lut_size); +i40e_status i40evf_aq_get_rss_key(struct i40e_hw *hw, + u16 seid, + struct i40e_aqc_get_set_rss_key_data *key); +i40e_status i40evf_aq_set_rss_key(struct i40e_hw *hw, + u16 seid, + struct i40e_aqc_get_set_rss_key_data *key); + +i40e_status i40e_set_mac_type(struct i40e_hw *hw); + +extern struct i40e_rx_ptype_decoded i40evf_ptype_lookup[]; + +static inline struct i40e_rx_ptype_decoded decode_rx_desc_ptype(u8 ptype) +{ + return i40evf_ptype_lookup[ptype]; +} + +/* i40e_common for VF drivers*/ +void i40e_vf_parse_hw_config(struct i40e_hw *hw, + struct virtchnl_vf_resource *msg); +i40e_status i40e_vf_reset(struct i40e_hw *hw); +i40e_status i40e_aq_send_msg_to_pf(struct i40e_hw *hw, + enum virtchnl_ops v_opcode, + i40e_status v_retval, u8 *msg, u16 msglen, + struct i40e_asq_cmd_details *cmd_details); +#endif /* _I40E_PROTOTYPE_H_ */ diff --git a/drivers/net/ethernet/intel/iavf/i40e_register.h b/drivers/net/ethernet/intel/iavf/i40e_register.h new file mode 100644 index 0000000000000000000000000000000000000000..20b464ac154203d607a164b14d1c375e16c7ad9e --- /dev/null +++ b/drivers/net/ethernet/intel/iavf/i40e_register.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2013 - 2018 Intel Corporation. */ + +#ifndef _I40E_REGISTER_H_ +#define _I40E_REGISTER_H_ + +#define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */ +#define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */ +#define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */ +#define I40E_VF_ARQH1_ARQH_SHIFT 0 +#define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT) +#define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */ +#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 +#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT) +#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 +#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT) +#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30 +#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT) +#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 +#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT) +#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ +#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ +#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ +#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */ +#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */ +#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 +#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT) +#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 +#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT) +#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30 +#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT) +#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 +#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT) +#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ +#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ +#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 +#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) +#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ +#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 +#define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT) +#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3 +#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) +#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */ +#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0 +#define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT) +#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2 +#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT) +#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3 +#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) +#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5 +#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24 +#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT) +#define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */ +#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30 +#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT) +#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31 +#define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */ +#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */ +#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */ +#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */ +#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ +#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ +#define I40E_VFQF_HKEY_MAX_INDEX 12 +#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ +#define I40E_VFQF_HLUT_MAX_INDEX 15 +#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30 +#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT) +#endif /* _I40E_REGISTER_H_ */ diff --git a/drivers/net/ethernet/intel/i40evf/i40e_status.h b/drivers/net/ethernet/intel/iavf/i40e_status.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_status.h rename to drivers/net/ethernet/intel/iavf/i40e_status.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_trace.h b/drivers/net/ethernet/intel/iavf/i40e_trace.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_trace.h rename to drivers/net/ethernet/intel/iavf/i40e_trace.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/iavf/i40e_txrx.c similarity index 99% rename from drivers/net/ethernet/intel/i40evf/i40e_txrx.c rename to drivers/net/ethernet/intel/iavf/i40e_txrx.c index 1bf9734ae9cf0428d1ee6b14f716649357a9a49b..d4bd06adc14532ea59c525fb2387c16705325001 100644 --- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c +++ b/drivers/net/ethernet/intel/iavf/i40e_txrx.c @@ -1062,7 +1062,7 @@ static inline void i40e_rx_hash(struct i40e_ring *ring, cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); - if (ring->netdev->features & NETIF_F_RXHASH) + if (!(ring->netdev->features & NETIF_F_RXHASH)) return; if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h b/drivers/net/ethernet/intel/iavf/i40e_txrx.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_txrx.h rename to drivers/net/ethernet/intel/iavf/i40e_txrx.h diff --git a/drivers/net/ethernet/intel/iavf/i40e_type.h b/drivers/net/ethernet/intel/iavf/i40e_type.h new file mode 100644 index 0000000000000000000000000000000000000000..8f1344094bc93f2295fd9d53d5fd76f036393996 --- /dev/null +++ b/drivers/net/ethernet/intel/iavf/i40e_type.h @@ -0,0 +1,719 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2013 - 2018 Intel Corporation. */ + +#ifndef _I40E_TYPE_H_ +#define _I40E_TYPE_H_ + +#include "i40e_status.h" +#include "i40e_osdep.h" +#include "i40e_register.h" +#include "i40e_adminq.h" +#include "i40e_devids.h" + +#define I40E_RXQ_CTX_DBUFF_SHIFT 7 + +/* I40E_MASK is a macro used on 32 bit registers */ +#define I40E_MASK(mask, shift) ((u32)(mask) << (shift)) + +#define I40E_MAX_VSI_QP 16 +#define I40E_MAX_VF_VSI 3 +#define I40E_MAX_CHAINED_RX_BUFFERS 5 + +/* forward declaration */ +struct i40e_hw; +typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); + +/* Data type manipulation macros. */ + +#define I40E_DESC_UNUSED(R) \ + ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ + (R)->next_to_clean - (R)->next_to_use - 1) + +/* bitfields for Tx queue mapping in QTX_CTL */ +#define I40E_QTX_CTL_VF_QUEUE 0x0 +#define I40E_QTX_CTL_VM_QUEUE 0x1 +#define I40E_QTX_CTL_PF_QUEUE 0x2 + +/* debug masks - set these bits in hw->debug_mask to control output */ +enum i40e_debug_mask { + I40E_DEBUG_INIT = 0x00000001, + I40E_DEBUG_RELEASE = 0x00000002, + + I40E_DEBUG_LINK = 0x00000010, + I40E_DEBUG_PHY = 0x00000020, + I40E_DEBUG_HMC = 0x00000040, + I40E_DEBUG_NVM = 0x00000080, + I40E_DEBUG_LAN = 0x00000100, + I40E_DEBUG_FLOW = 0x00000200, + I40E_DEBUG_DCB = 0x00000400, + I40E_DEBUG_DIAG = 0x00000800, + I40E_DEBUG_FD = 0x00001000, + I40E_DEBUG_PACKAGE = 0x00002000, + + I40E_DEBUG_AQ_MESSAGE = 0x01000000, + I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000, + I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000, + I40E_DEBUG_AQ_COMMAND = 0x06000000, + I40E_DEBUG_AQ = 0x0F000000, + + I40E_DEBUG_USER = 0xF0000000, + + I40E_DEBUG_ALL = 0xFFFFFFFF +}; + +/* These are structs for managing the hardware information and the operations. + * The structures of function pointers are filled out at init time when we + * know for sure exactly which hardware we're working with. This gives us the + * flexibility of using the same main driver code but adapting to slightly + * different hardware needs as new parts are developed. For this architecture, + * the Firmware and AdminQ are intended to insulate the driver from most of the + * future changes, but these structures will also do part of the job. + */ +enum i40e_mac_type { + I40E_MAC_UNKNOWN = 0, + I40E_MAC_XL710, + I40E_MAC_VF, + I40E_MAC_X722, + I40E_MAC_X722_VF, + I40E_MAC_GENERIC, +}; + +enum i40e_vsi_type { + I40E_VSI_MAIN = 0, + I40E_VSI_VMDQ1 = 1, + I40E_VSI_VMDQ2 = 2, + I40E_VSI_CTRL = 3, + I40E_VSI_FCOE = 4, + I40E_VSI_MIRROR = 5, + I40E_VSI_SRIOV = 6, + I40E_VSI_FDIR = 7, + I40E_VSI_TYPE_UNKNOWN +}; + +enum i40e_queue_type { + I40E_QUEUE_TYPE_RX = 0, + I40E_QUEUE_TYPE_TX, + I40E_QUEUE_TYPE_PE_CEQ, + I40E_QUEUE_TYPE_UNKNOWN +}; + +#define I40E_HW_CAP_MAX_GPIO 30 +/* Capabilities of a PF or a VF or the whole device */ +struct i40e_hw_capabilities { + bool dcb; + bool fcoe; + u32 num_vsis; + u32 num_rx_qp; + u32 num_tx_qp; + u32 base_queue; + u32 num_msix_vectors_vf; +}; + +struct i40e_mac_info { + enum i40e_mac_type type; + u8 addr[ETH_ALEN]; + u8 perm_addr[ETH_ALEN]; + u8 san_addr[ETH_ALEN]; + u16 max_fcoeq; +}; + +/* PCI bus types */ +enum i40e_bus_type { + i40e_bus_type_unknown = 0, + i40e_bus_type_pci, + i40e_bus_type_pcix, + i40e_bus_type_pci_express, + i40e_bus_type_reserved +}; + +/* PCI bus speeds */ +enum i40e_bus_speed { + i40e_bus_speed_unknown = 0, + i40e_bus_speed_33 = 33, + i40e_bus_speed_66 = 66, + i40e_bus_speed_100 = 100, + i40e_bus_speed_120 = 120, + i40e_bus_speed_133 = 133, + i40e_bus_speed_2500 = 2500, + i40e_bus_speed_5000 = 5000, + i40e_bus_speed_8000 = 8000, + i40e_bus_speed_reserved +}; + +/* PCI bus widths */ +enum i40e_bus_width { + i40e_bus_width_unknown = 0, + i40e_bus_width_pcie_x1 = 1, + i40e_bus_width_pcie_x2 = 2, + i40e_bus_width_pcie_x4 = 4, + i40e_bus_width_pcie_x8 = 8, + i40e_bus_width_32 = 32, + i40e_bus_width_64 = 64, + i40e_bus_width_reserved +}; + +/* Bus parameters */ +struct i40e_bus_info { + enum i40e_bus_speed speed; + enum i40e_bus_width width; + enum i40e_bus_type type; + + u16 func; + u16 device; + u16 lan_id; + u16 bus_id; +}; + +#define I40E_MAX_TRAFFIC_CLASS 8 +#define I40E_MAX_USER_PRIORITY 8 +/* Port hardware description */ +struct i40e_hw { + u8 __iomem *hw_addr; + void *back; + + /* subsystem structs */ + struct i40e_mac_info mac; + struct i40e_bus_info bus; + + /* pci info */ + u16 device_id; + u16 vendor_id; + u16 subsystem_device_id; + u16 subsystem_vendor_id; + u8 revision_id; + + /* capabilities for entire device and PCI func */ + struct i40e_hw_capabilities dev_caps; + + /* Admin Queue info */ + struct i40e_adminq_info aq; + + /* debug mask */ + u32 debug_mask; + char err_str[16]; +}; + +static inline bool i40e_is_vf(struct i40e_hw *hw) +{ + return (hw->mac.type == I40E_MAC_VF || + hw->mac.type == I40E_MAC_X722_VF); +} + +struct i40e_driver_version { + u8 major_version; + u8 minor_version; + u8 build_version; + u8 subbuild_version; + u8 driver_string[32]; +}; + +/* RX Descriptors */ +union i40e_16byte_rx_desc { + struct { + __le64 pkt_addr; /* Packet buffer address */ + __le64 hdr_addr; /* Header buffer address */ + } read; + struct { + struct { + struct { + union { + __le16 mirroring_status; + __le16 fcoe_ctx_id; + } mirr_fcoe; + __le16 l2tag1; + } lo_dword; + union { + __le32 rss; /* RSS Hash */ + __le32 fd_id; /* Flow director filter id */ + __le32 fcoe_param; /* FCoE DDP Context id */ + } hi_dword; + } qword0; + struct { + /* ext status/error/pktype/length */ + __le64 status_error_len; + } qword1; + } wb; /* writeback */ +}; + +union i40e_32byte_rx_desc { + struct { + __le64 pkt_addr; /* Packet buffer address */ + __le64 hdr_addr; /* Header buffer address */ + /* bit 0 of hdr_buffer_addr is DD bit */ + __le64 rsvd1; + __le64 rsvd2; + } read; + struct { + struct { + struct { + union { + __le16 mirroring_status; + __le16 fcoe_ctx_id; + } mirr_fcoe; + __le16 l2tag1; + } lo_dword; + union { + __le32 rss; /* RSS Hash */ + __le32 fcoe_param; /* FCoE DDP Context id */ + /* Flow director filter id in case of + * Programming status desc WB + */ + __le32 fd_id; + } hi_dword; + } qword0; + struct { + /* status/error/pktype/length */ + __le64 status_error_len; + } qword1; + struct { + __le16 ext_status; /* extended status */ + __le16 rsvd; + __le16 l2tag2_1; + __le16 l2tag2_2; + } qword2; + struct { + union { + __le32 flex_bytes_lo; + __le32 pe_status; + } lo_dword; + union { + __le32 flex_bytes_hi; + __le32 fd_id; + } hi_dword; + } qword3; + } wb; /* writeback */ +}; + +enum i40e_rx_desc_status_bits { + /* Note: These are predefined bit offsets */ + I40E_RX_DESC_STATUS_DD_SHIFT = 0, + I40E_RX_DESC_STATUS_EOF_SHIFT = 1, + I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, + I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, + I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, + I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ + I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, + /* Note: Bit 8 is reserved in X710 and XL710 */ + I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8, + I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ + I40E_RX_DESC_STATUS_FLM_SHIFT = 11, + I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ + I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, + I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, + I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */ + /* Note: For non-tunnel packets INT_UDP_0 is the right status for + * UDP header + */ + I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18, + I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ +}; + +#define I40E_RXD_QW1_STATUS_SHIFT 0 +#define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \ + << I40E_RXD_QW1_STATUS_SHIFT) + +#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT +#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ + I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT) + +#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT +#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \ + BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT) + +enum i40e_rx_desc_fltstat_values { + I40E_RX_DESC_FLTSTAT_NO_DATA = 0, + I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ + I40E_RX_DESC_FLTSTAT_RSV = 2, + I40E_RX_DESC_FLTSTAT_RSS_HASH = 3, +}; + +#define I40E_RXD_QW1_ERROR_SHIFT 19 +#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT) + +enum i40e_rx_desc_error_bits { + /* Note: These are predefined bit offsets */ + I40E_RX_DESC_ERROR_RXE_SHIFT = 0, + I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1, + I40E_RX_DESC_ERROR_HBO_SHIFT = 2, + I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ + I40E_RX_DESC_ERROR_IPE_SHIFT = 3, + I40E_RX_DESC_ERROR_L4E_SHIFT = 4, + I40E_RX_DESC_ERROR_EIPE_SHIFT = 5, + I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, + I40E_RX_DESC_ERROR_PPRS_SHIFT = 7 +}; + +enum i40e_rx_desc_error_l3l4e_fcoe_masks { + I40E_RX_DESC_ERROR_L3L4E_NONE = 0, + I40E_RX_DESC_ERROR_L3L4E_PROT = 1, + I40E_RX_DESC_ERROR_L3L4E_FC = 2, + I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, + I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 +}; + +#define I40E_RXD_QW1_PTYPE_SHIFT 30 +#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT) + +/* Packet type non-ip values */ +enum i40e_rx_l2_ptype { + I40E_RX_PTYPE_L2_RESERVED = 0, + I40E_RX_PTYPE_L2_MAC_PAY2 = 1, + I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, + I40E_RX_PTYPE_L2_FIP_PAY2 = 3, + I40E_RX_PTYPE_L2_OUI_PAY2 = 4, + I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, + I40E_RX_PTYPE_L2_LLDP_PAY2 = 6, + I40E_RX_PTYPE_L2_ECP_PAY2 = 7, + I40E_RX_PTYPE_L2_EVB_PAY2 = 8, + I40E_RX_PTYPE_L2_QCN_PAY2 = 9, + I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10, + I40E_RX_PTYPE_L2_ARP = 11, + I40E_RX_PTYPE_L2_FCOE_PAY3 = 12, + I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, + I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, + I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, + I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, + I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, + I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, + I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, + I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, + I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, + I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, + I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, + I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, + I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153 +}; + +struct i40e_rx_ptype_decoded { + u32 ptype:8; + u32 known:1; + u32 outer_ip:1; + u32 outer_ip_ver:1; + u32 outer_frag:1; + u32 tunnel_type:3; + u32 tunnel_end_prot:2; + u32 tunnel_end_frag:1; + u32 inner_prot:4; + u32 payload_layer:3; +}; + +enum i40e_rx_ptype_outer_ip { + I40E_RX_PTYPE_OUTER_L2 = 0, + I40E_RX_PTYPE_OUTER_IP = 1 +}; + +enum i40e_rx_ptype_outer_ip_ver { + I40E_RX_PTYPE_OUTER_NONE = 0, + I40E_RX_PTYPE_OUTER_IPV4 = 0, + I40E_RX_PTYPE_OUTER_IPV6 = 1 +}; + +enum i40e_rx_ptype_outer_fragmented { + I40E_RX_PTYPE_NOT_FRAG = 0, + I40E_RX_PTYPE_FRAG = 1 +}; + +enum i40e_rx_ptype_tunnel_type { + I40E_RX_PTYPE_TUNNEL_NONE = 0, + I40E_RX_PTYPE_TUNNEL_IP_IP = 1, + I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2, + I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, + I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, +}; + +enum i40e_rx_ptype_tunnel_end_prot { + I40E_RX_PTYPE_TUNNEL_END_NONE = 0, + I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1, + I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2, +}; + +enum i40e_rx_ptype_inner_prot { + I40E_RX_PTYPE_INNER_PROT_NONE = 0, + I40E_RX_PTYPE_INNER_PROT_UDP = 1, + I40E_RX_PTYPE_INNER_PROT_TCP = 2, + I40E_RX_PTYPE_INNER_PROT_SCTP = 3, + I40E_RX_PTYPE_INNER_PROT_ICMP = 4, + I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5 +}; + +enum i40e_rx_ptype_payload_layer { + I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, + I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, + I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, + I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, +}; + +#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38 +#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ + I40E_RXD_QW1_LENGTH_PBUF_SHIFT) + +#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52 +#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ + I40E_RXD_QW1_LENGTH_HBUF_SHIFT) + +#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 +#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT) + +enum i40e_rx_desc_ext_status_bits { + /* Note: These are predefined bit offsets */ + I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, + I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, + I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ + I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ + I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, + I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, + I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, +}; + +enum i40e_rx_desc_pe_status_bits { + /* Note: These are predefined bit offsets */ + I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ + I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ + I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ + I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, + I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, + I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, + I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27, + I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, + I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 +}; + +#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 +#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 + +#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 +#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ + I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) + +#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 +#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ + I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) + +enum i40e_rx_prog_status_desc_status_bits { + /* Note: These are predefined bit offsets */ + I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0, + I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ +}; + +enum i40e_rx_prog_status_desc_prog_id_masks { + I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, + I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, + I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, +}; + +enum i40e_rx_prog_status_desc_error_bits { + /* Note: These are predefined bit offsets */ + I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, + I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, + I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, + I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 +}; + +/* TX Descriptor */ +struct i40e_tx_desc { + __le64 buffer_addr; /* Address of descriptor's data buf */ + __le64 cmd_type_offset_bsz; +}; + +#define I40E_TXD_QW1_DTYPE_SHIFT 0 +#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT) + +enum i40e_tx_desc_dtype_value { + I40E_TX_DESC_DTYPE_DATA = 0x0, + I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ + I40E_TX_DESC_DTYPE_CONTEXT = 0x1, + I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2, + I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8, + I40E_TX_DESC_DTYPE_DDP_CTX = 0x9, + I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB, + I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, + I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, + I40E_TX_DESC_DTYPE_DESC_DONE = 0xF +}; + +#define I40E_TXD_QW1_CMD_SHIFT 4 +#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT) + +enum i40e_tx_desc_cmd_bits { + I40E_TX_DESC_CMD_EOP = 0x0001, + I40E_TX_DESC_CMD_RS = 0x0002, + I40E_TX_DESC_CMD_ICRC = 0x0004, + I40E_TX_DESC_CMD_IL2TAG1 = 0x0008, + I40E_TX_DESC_CMD_DUMMY = 0x0010, + I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ + I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ + I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ + I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ + I40E_TX_DESC_CMD_FCOET = 0x0080, + I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ + I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ + I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ + I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ + I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ + I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ + I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ + I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ +}; + +#define I40E_TXD_QW1_OFFSET_SHIFT 16 +#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ + I40E_TXD_QW1_OFFSET_SHIFT) + +enum i40e_tx_desc_length_fields { + /* Note: These are predefined bit offsets */ + I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ + I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ + I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ +}; + +#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 +#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ + I40E_TXD_QW1_TX_BUF_SZ_SHIFT) + +#define I40E_TXD_QW1_L2TAG1_SHIFT 48 +#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT) + +/* Context descriptors */ +struct i40e_tx_context_desc { + __le32 tunneling_params; + __le16 l2tag2; + __le16 rsvd; + __le64 type_cmd_tso_mss; +}; + +#define I40E_TXD_CTX_QW1_CMD_SHIFT 4 +#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) + +enum i40e_tx_ctx_desc_cmd_bits { + I40E_TX_CTX_DESC_TSO = 0x01, + I40E_TX_CTX_DESC_TSYN = 0x02, + I40E_TX_CTX_DESC_IL2TAG2 = 0x04, + I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, + I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00, + I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10, + I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20, + I40E_TX_CTX_DESC_SWTCH_VSI = 0x30, + I40E_TX_CTX_DESC_SWPE = 0x40 +}; + +#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 +#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ + I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) + +#define I40E_TXD_CTX_QW1_MSS_SHIFT 50 +#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ + I40E_TXD_CTX_QW1_MSS_SHIFT) + +#define I40E_TXD_CTX_QW1_VSI_SHIFT 50 +#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT) + +#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0 +#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ + I40E_TXD_CTX_QW0_EXT_IP_SHIFT) + +enum i40e_tx_ctx_desc_eipt_offload { + I40E_TX_CTX_EXT_IP_NONE = 0x0, + I40E_TX_CTX_EXT_IP_IPV6 = 0x1, + I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, + I40E_TX_CTX_EXT_IP_IPV4 = 0x3 +}; + +#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 +#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ + I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT) + +#define I40E_TXD_CTX_QW0_NATT_SHIFT 9 +#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) + +#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT) +#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) + +#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 +#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \ + BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT) + +#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK + +#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 +#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ + I40E_TXD_CTX_QW0_NATLEN_SHIFT) + +#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19 +#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ + I40E_TXD_CTX_QW0_DECTTL_SHIFT) + +#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23 +#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT) + +/* Packet Classifier Types for filters */ +enum i40e_filter_pctype { + /* Note: Values 0-28 are reserved for future use. + * Value 29, 30, 32 are not supported on XL710 and X710. + */ + I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, + I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, + I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, + I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, + I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, + I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, + I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, + I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, + /* Note: Values 37-38 are reserved for future use. + * Value 39, 40, 42 are not supported on XL710 and X710. + */ + I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, + I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, + I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, + I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, + I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, + I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, + I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, + I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, + /* Note: Value 47 is reserved for future use */ + I40E_FILTER_PCTYPE_FCOE_OX = 48, + I40E_FILTER_PCTYPE_FCOE_RX = 49, + I40E_FILTER_PCTYPE_FCOE_OTHER = 50, + /* Note: Values 51-62 are reserved for future use */ + I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, +}; + + +struct i40e_vsi_context { + u16 seid; + u16 uplink_seid; + u16 vsi_number; + u16 vsis_allocated; + u16 vsis_unallocated; + u16 flags; + u8 pf_num; + u8 vf_num; + u8 connection_type; + struct i40e_aqc_vsi_properties_data info; +}; + +struct i40e_veb_context { + u16 seid; + u16 uplink_seid; + u16 veb_number; + u16 vebs_allocated; + u16 vebs_unallocated; + u16 flags; + struct i40e_aqc_get_veb_parameters_completion info; +}; + +/* Statistics collected by each port, VSI, VEB, and S-channel */ +struct i40e_eth_stats { + u64 rx_bytes; /* gorc */ + u64 rx_unicast; /* uprc */ + u64 rx_multicast; /* mprc */ + u64 rx_broadcast; /* bprc */ + u64 rx_discards; /* rdpc */ + u64 rx_unknown_protocol; /* rupp */ + u64 tx_bytes; /* gotc */ + u64 tx_unicast; /* uptc */ + u64 tx_multicast; /* mptc */ + u64 tx_broadcast; /* bptc */ + u64 tx_discards; /* tdpc */ + u64 tx_errors; /* tepc */ +}; +#endif /* _I40E_TYPE_H_ */ diff --git a/drivers/net/ethernet/intel/i40evf/i40evf.h b/drivers/net/ethernet/intel/iavf/i40evf.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40evf.h rename to drivers/net/ethernet/intel/iavf/i40evf.h diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_client.c b/drivers/net/ethernet/intel/iavf/i40evf_client.c similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40evf_client.c rename to drivers/net/ethernet/intel/iavf/i40evf_client.c diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_client.h b/drivers/net/ethernet/intel/iavf/i40evf_client.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40evf_client.h rename to drivers/net/ethernet/intel/iavf/i40evf_client.h diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c b/drivers/net/ethernet/intel/iavf/i40evf_ethtool.c similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c rename to drivers/net/ethernet/intel/iavf/i40evf_ethtool.c diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_main.c b/drivers/net/ethernet/intel/iavf/i40evf_main.c similarity index 99% rename from drivers/net/ethernet/intel/i40evf/i40evf_main.c rename to drivers/net/ethernet/intel/iavf/i40evf_main.c index 5a6e579e9e6535d0e20a88e04b9060442a255793..60c2e5df58272033561e0a1286d64ac19f31e840 100644 --- a/drivers/net/ethernet/intel/i40evf/i40evf_main.c +++ b/drivers/net/ethernet/intel/iavf/i40evf_main.c @@ -17,20 +17,20 @@ static int i40evf_close(struct net_device *netdev); char i40evf_driver_name[] = "i40evf"; static const char i40evf_driver_string[] = - "Intel(R) 40-10 Gigabit Virtual Function Network Driver"; + "Intel(R) Ethernet Adaptive Virtual Function Network Driver"; #define DRV_KERN "-k" #define DRV_VERSION_MAJOR 3 #define DRV_VERSION_MINOR 2 -#define DRV_VERSION_BUILD 2 +#define DRV_VERSION_BUILD 3 #define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \ __stringify(DRV_VERSION_MINOR) "." \ __stringify(DRV_VERSION_BUILD) \ DRV_KERN const char i40evf_driver_version[] = DRV_VERSION; static const char i40evf_copyright[] = - "Copyright (c) 2013 - 2015 Intel Corporation."; + "Copyright (c) 2013 - 2018 Intel Corporation."; /* i40evf_pci_tbl - PCI Device ID Table * @@ -51,6 +51,7 @@ static const struct pci_device_id i40evf_pci_tbl[] = { MODULE_DEVICE_TABLE(pci, i40evf_pci_tbl); +MODULE_ALIAS("i40evf"); MODULE_AUTHOR("Intel Corporation, "); MODULE_DESCRIPTION("Intel(R) XL710 X710 Virtual Function Network Driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c b/drivers/net/ethernet/intel/iavf/i40evf_virtchnl.c similarity index 99% rename from drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c rename to drivers/net/ethernet/intel/iavf/i40evf_virtchnl.c index 94dabc9d89f731f436c90ed7bf56eebd56297e63..6579dabab78cf0a921c1b5212d8c1a2771e7f07d 100644 --- a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c +++ b/drivers/net/ethernet/intel/iavf/i40evf_virtchnl.c @@ -1362,8 +1362,15 @@ void i40evf_virtchnl_completion(struct i40evf_adapter *adapter, memcpy(adapter->vf_res, msg, min(msglen, len)); i40evf_validate_num_queues(adapter); i40e_vf_parse_hw_config(&adapter->hw, adapter->vf_res); - /* restore current mac address */ - ether_addr_copy(adapter->hw.mac.addr, netdev->dev_addr); + if (is_zero_ether_addr(adapter->hw.mac.addr)) { + /* restore current mac address */ + ether_addr_copy(adapter->hw.mac.addr, netdev->dev_addr); + } else { + /* refresh current mac address if changed */ + ether_addr_copy(netdev->dev_addr, adapter->hw.mac.addr); + ether_addr_copy(netdev->perm_addr, + adapter->hw.mac.addr); + } i40evf_process_config(adapter); } break; diff --git a/drivers/net/ethernet/intel/igb/e1000_mac.c b/drivers/net/ethernet/intel/igb/e1000_mac.c index 79ee0a7472608ec823e29d576a40a29b05237fe1..4e69cb2c025fd3459b6574229948e15ac35785b7 100644 --- a/drivers/net/ethernet/intel/igb/e1000_mac.c +++ b/drivers/net/ethernet/intel/igb/e1000_mac.c @@ -425,7 +425,7 @@ void igb_mta_set(struct e1000_hw *hw, u32 hash_value) static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) { u32 hash_value, hash_mask; - u8 bit_shift = 0; + u8 bit_shift = 1; /* Register count multiplied by bits per register */ hash_mask = (hw->mac.mta_reg_count * 32) - 1; @@ -433,7 +433,7 @@ static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) /* For a mc_filter_type of 0, bit_shift is the number of left-shifts * where 0xFF would still fall within the hash mask. */ - while (hash_mask >> bit_shift != 0xFF) + while (hash_mask >> bit_shift != 0xFF && bit_shift < 4) bit_shift++; /* The portion of the address that is used for the hash table diff --git a/drivers/net/ethernet/intel/igb/igb.h b/drivers/net/ethernet/intel/igb/igb.h index 33cbe4f70d590bb34a3e7a9c58b7fdb491beecd2..e6d99759d95a1fddc7645a84134c7830c525f016 100644 --- a/drivers/net/ethernet/intel/igb/igb.h +++ b/drivers/net/ethernet/intel/igb/igb.h @@ -32,11 +32,11 @@ struct igb_adapter; /* TX/RX descriptor defines */ #define IGB_DEFAULT_TXD 256 #define IGB_DEFAULT_TX_WORK 128 -#define IGB_MIN_TXD 80 +#define IGB_MIN_TXD 64 #define IGB_MAX_TXD 4096 #define IGB_DEFAULT_RXD 256 -#define IGB_MIN_RXD 80 +#define IGB_MIN_RXD 64 #define IGB_MAX_RXD 4096 #define IGB_DEFAULT_ITR 3 /* dynamic */ diff --git a/drivers/net/ethernet/intel/igb/igb_ethtool.c b/drivers/net/ethernet/intel/igb/igb_ethtool.c index d0f5b92bead7364d367a4f5b1db62aaf9f9ce0e2..f714c85c36c5062e84d578c50d14bb7b2fa476cf 100644 --- a/drivers/net/ethernet/intel/igb/igb_ethtool.c +++ b/drivers/net/ethernet/intel/igb/igb_ethtool.c @@ -811,6 +811,8 @@ static int igb_set_eeprom(struct net_device *netdev, */ ret_val = hw->nvm.ops.read(hw, last_word, 1, &eeprom_buff[last_word - first_word]); + if (ret_val) + goto out; } /* Device's eeprom is always little-endian, word addressable */ @@ -830,6 +832,7 @@ static int igb_set_eeprom(struct net_device *netdev, hw->nvm.ops.update(hw); igb_set_fw_version(adapter); +out: kfree(eeprom_buff); return ret_val; } @@ -2991,11 +2994,15 @@ static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter, if (err) goto err_out_w_lock; - igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx); + err = igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx); + if (err) + goto err_out_input_filter; spin_unlock(&adapter->nfc_lock); return 0; +err_out_input_filter: + igb_erase_filter(adapter, input); err_out_w_lock: spin_unlock(&adapter->nfc_lock); err_out: diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c index 87f98170ac937cf9c230d82cc7a94905a1b38a87..00d8f1e8177e7bb7759c016a58cbb28c248bb311 100644 --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c @@ -3700,9 +3700,7 @@ static void igb_remove(struct pci_dev *pdev) igb_release_hw_control(adapter); #ifdef CONFIG_PCI_IOV - rtnl_lock(); igb_disable_sriov(pdev); - rtnl_unlock(); #endif unregister_netdev(netdev); @@ -3738,8 +3736,9 @@ static void igb_probe_vfs(struct igb_adapter *adapter) struct pci_dev *pdev = adapter->pdev; struct e1000_hw *hw = &adapter->hw; - /* Virtualization features not supported on i210 family. */ - if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) + /* Virtualization features not supported on i210 and 82580 family. */ + if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) || + (hw->mac.type == e1000_82580)) return; /* Of the below we really only want the effect of getting @@ -4581,6 +4580,10 @@ void igb_configure_rx_ring(struct igb_adapter *adapter, static void igb_set_rx_buffer_len(struct igb_adapter *adapter, struct igb_ring *rx_ring) { +#if (PAGE_SIZE < 8192) + struct e1000_hw *hw = &adapter->hw; +#endif + /* set build_skb and buffer size flags */ clear_ring_build_skb_enabled(rx_ring); clear_ring_uses_large_buffer(rx_ring); @@ -4591,10 +4594,9 @@ static void igb_set_rx_buffer_len(struct igb_adapter *adapter, set_ring_build_skb_enabled(rx_ring); #if (PAGE_SIZE < 8192) - if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) - return; - - set_ring_uses_large_buffer(rx_ring); + if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB || + rd32(E1000_RCTL) & E1000_RCTL_SBP) + set_ring_uses_large_buffer(rx_ring); #endif } @@ -9061,6 +9063,11 @@ static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, struct net_device *netdev = pci_get_drvdata(pdev); struct igb_adapter *adapter = netdev_priv(netdev); + if (state == pci_channel_io_normal) { + dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n"); + return PCI_ERS_RESULT_CAN_RECOVER; + } + netif_device_detach(netdev); if (state == pci_channel_io_perm_failure) diff --git a/drivers/net/ethernet/intel/igb/igb_ptp.c b/drivers/net/ethernet/intel/igb/igb_ptp.c index 29ced6b74d364632113e9674f8d005257e548411..be2e743e65de9436e3eafba7e4dc914ff79072ee 100644 --- a/drivers/net/ethernet/intel/igb/igb_ptp.c +++ b/drivers/net/ethernet/intel/igb/igb_ptp.c @@ -1181,18 +1181,6 @@ void igb_ptp_init(struct igb_adapter *adapter) return; } - spin_lock_init(&adapter->tmreg_lock); - INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); - - if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) - INIT_DELAYED_WORK(&adapter->ptp_overflow_work, - igb_ptp_overflow_check); - - adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; - adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; - - igb_ptp_reset(adapter); - adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, &adapter->pdev->dev); if (IS_ERR(adapter->ptp_clock)) { @@ -1202,6 +1190,18 @@ void igb_ptp_init(struct igb_adapter *adapter) dev_info(&adapter->pdev->dev, "added PHC on %s\n", adapter->netdev->name); adapter->ptp_flags |= IGB_PTP_ENABLED; + + spin_lock_init(&adapter->tmreg_lock); + INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); + + if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) + INIT_DELAYED_WORK(&adapter->ptp_overflow_work, + igb_ptp_overflow_check); + + adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; + adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; + + igb_ptp_reset(adapter); } } diff --git a/drivers/net/ethernet/intel/igbvf/igbvf.h b/drivers/net/ethernet/intel/igbvf/igbvf.h index eee26a3be90ba8aad04baa961f01badb0d889565..52545cb25d058738cd895329a2c02e9c14ef2052 100644 --- a/drivers/net/ethernet/intel/igbvf/igbvf.h +++ b/drivers/net/ethernet/intel/igbvf/igbvf.h @@ -39,11 +39,11 @@ enum latency_range { /* Tx/Rx descriptor defines */ #define IGBVF_DEFAULT_TXD 256 #define IGBVF_MAX_TXD 4096 -#define IGBVF_MIN_TXD 80 +#define IGBVF_MIN_TXD 64 #define IGBVF_DEFAULT_RXD 256 #define IGBVF_MAX_RXD 4096 -#define IGBVF_MIN_RXD 80 +#define IGBVF_MIN_RXD 64 #define IGBVF_MIN_ITR_USECS 10 /* 100000 irq/sec */ #define IGBVF_MAX_ITR_USECS 10000 /* 100 irq/sec */ diff --git a/drivers/net/ethernet/intel/igbvf/netdev.c b/drivers/net/ethernet/intel/igbvf/netdev.c index df827c2541628ab82caa11691efa44d448e9bd96..70f5f28bfd9ed924e14187d3a49baefd6d639eb3 100644 --- a/drivers/net/ethernet/intel/igbvf/netdev.c +++ b/drivers/net/ethernet/intel/igbvf/netdev.c @@ -1070,7 +1070,7 @@ static int igbvf_request_msix(struct igbvf_adapter *adapter) igbvf_intr_msix_rx, 0, adapter->rx_ring->name, netdev); if (err) - goto out; + goto free_irq_tx; adapter->rx_ring->itr_register = E1000_EITR(vector); adapter->rx_ring->itr_val = adapter->current_itr; @@ -1079,10 +1079,14 @@ static int igbvf_request_msix(struct igbvf_adapter *adapter) err = request_irq(adapter->msix_entries[vector].vector, igbvf_msix_other, 0, netdev->name, netdev); if (err) - goto out; + goto free_irq_rx; igbvf_configure_msix(adapter); return 0; +free_irq_rx: + free_irq(adapter->msix_entries[--vector].vector, netdev); +free_irq_tx: + free_irq(adapter->msix_entries[--vector].vector, netdev); out: return err; } diff --git a/drivers/net/ethernet/intel/igbvf/vf.c b/drivers/net/ethernet/intel/igbvf/vf.c index b8ba3f94c363229b230d3c8dbe1a882149e6e265..a47a2e3e548cf3f2e5241ca3180e816f7ebb626a 100644 --- a/drivers/net/ethernet/intel/igbvf/vf.c +++ b/drivers/net/ethernet/intel/igbvf/vf.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright(c) 2009 - 2018 Intel Corporation. */ +#include + #include "vf.h" static s32 e1000_check_for_link_vf(struct e1000_hw *hw); @@ -131,11 +133,16 @@ static s32 e1000_reset_hw_vf(struct e1000_hw *hw) /* set our "perm_addr" based on info provided by PF */ ret_val = mbx->ops.read_posted(hw, msgbuf, 3); if (!ret_val) { - if (msgbuf[0] == (E1000_VF_RESET | - E1000_VT_MSGTYPE_ACK)) + switch (msgbuf[0]) { + case E1000_VF_RESET | E1000_VT_MSGTYPE_ACK: memcpy(hw->mac.perm_addr, addr, ETH_ALEN); - else + break; + case E1000_VF_RESET | E1000_VT_MSGTYPE_NACK: + eth_zero_addr(hw->mac.perm_addr); + break; + default: ret_val = -E1000_ERR_MAC_INIT; + } } } diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c index 8829bd95d0d36557acf0e669f77f6680e45485c5..3d361557a63a37b488f3a7cfe3c2b4ee7cce20f1 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c @@ -2539,6 +2539,14 @@ static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter, return 0; } +static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter) +{ + if (adapter->hw.mac.type < ixgbe_mac_X550) + return 16; + else + return 64; +} + static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, u32 *rule_locs) { @@ -2547,7 +2555,8 @@ static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, switch (cmd->cmd) { case ETHTOOL_GRXRINGS: - cmd->data = adapter->num_rx_queues; + cmd->data = min_t(int, adapter->num_rx_queues, + ixgbe_rss_indir_tbl_max(adapter)); ret = 0; break; case ETHTOOL_GRXCLSRLCNT: @@ -2949,14 +2958,6 @@ static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) return ret; } -static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter) -{ - if (adapter->hw.mac.type < ixgbe_mac_X550) - return 16; - else - return 64; -} - static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev) { return IXGBE_RSS_KEY_SIZE; @@ -3005,8 +3006,8 @@ static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir, int i; u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); - if (hfunc) - return -EINVAL; + if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP) + return -EOPNOTSUPP; /* Fill out the redirection table */ if (indir) { diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c index eec68cc9288c8dd1cd69672afa3bf63a57f9c381..9c0e0ccbbe3cf433ffd2711857817dd1100b4c15 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c @@ -844,6 +844,7 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED; u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED; u32 tsync_rx_mtrl = PTP_EV_PORT << 16; + u32 aflags = adapter->flags; bool is_l2 = false; u32 regval; @@ -864,20 +865,20 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, case HWTSTAMP_FILTER_NONE: tsync_rx_ctl = 0; tsync_rx_mtrl = 0; - adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | - IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); + aflags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | + IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); break; case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG; - adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | - IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); + aflags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | + IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); break; case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG; - adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | - IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); + aflags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | + IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); break; case HWTSTAMP_FILTER_PTP_V2_EVENT: case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: @@ -891,8 +892,8 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2; is_l2 = true; config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; - adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | - IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); + aflags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | + IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); break; case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: case HWTSTAMP_FILTER_NTP_ALL: @@ -903,7 +904,7 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, if (hw->mac.type >= ixgbe_mac_X550) { tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_ALL; config->rx_filter = HWTSTAMP_FILTER_ALL; - adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED; + aflags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED; break; } /* fall through */ @@ -914,8 +915,6 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, * Delay_Req messages and hardware does not support * timestamping all packets => return error */ - adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | - IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); config->rx_filter = HWTSTAMP_FILTER_NONE; return -ERANGE; } @@ -947,8 +946,8 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, IXGBE_TSYNCRXCTL_TYPE_ALL | IXGBE_TSYNCRXCTL_TSIP_UT_EN; config->rx_filter = HWTSTAMP_FILTER_ALL; - adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED; - adapter->flags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER; + aflags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED; + aflags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER; is_l2 = true; break; default: @@ -981,6 +980,9 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, IXGBE_WRITE_FLUSH(hw); + /* configure adapter flags only when HW is actually configured */ + adapter->flags = aflags; + /* clear TX/RX time stamp registers, just to be sure */ ixgbe_ptp_clear_tx_timestamp(adapter); IXGBE_READ_REG(hw, IXGBE_RXSTMPH); diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c index 6055a4917ff6942924d39c3716ae08ead0ef7eed..9b463ef62be5589ff973d75e59c598555699b68e 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c @@ -28,6 +28,9 @@ static inline void ixgbe_alloc_vf_macvlans(struct ixgbe_adapter *adapter, struct vf_macvlans *mv_list; int num_vf_macvlans, i; + /* Initialize list of VF macvlans */ + INIT_LIST_HEAD(&adapter->vf_mvs.l); + num_vf_macvlans = hw->mac.num_rar_entries - (IXGBE_MAX_PF_MACVLANS + 1 + num_vfs); if (!num_vf_macvlans) @@ -36,8 +39,6 @@ static inline void ixgbe_alloc_vf_macvlans(struct ixgbe_adapter *adapter, mv_list = kcalloc(num_vf_macvlans, sizeof(struct vf_macvlans), GFP_KERNEL); if (mv_list) { - /* Initialize list of VF macvlans */ - INIT_LIST_HEAD(&adapter->vf_mvs.l); for (i = 0; i < num_vf_macvlans; i++) { mv_list[i].vf = -1; mv_list[i].free = true; diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index fd13116812006a3dbebe50cc558a3abbe6076402..512f9cd68070a870f6ea4db0487a1cb5eadde52e 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -542,6 +542,20 @@ struct mvneta_rx_desc { }; #endif +enum mvneta_tx_buf_type { + MVNETA_TYPE_SKB, + MVNETA_TYPE_XDP_TX, + MVNETA_TYPE_XDP_NDO, +}; + +struct mvneta_tx_buf { + enum mvneta_tx_buf_type type; + union { + struct xdp_frame *xdpf; + struct sk_buff *skb; + }; +}; + struct mvneta_tx_queue { /* Number of this TX queue, in the range 0-7 */ u8 id; @@ -557,8 +571,8 @@ struct mvneta_tx_queue { int tx_stop_threshold; int tx_wake_threshold; - /* Array of transmitted skb */ - struct sk_buff **tx_skb; + /* Array of transmitted buffers */ + struct mvneta_tx_buf *buf; /* Index of last TX DMA descriptor that was inserted */ int txq_put_index; @@ -1401,7 +1415,7 @@ static void mvneta_defaults_set(struct mvneta_port *pp) */ if (txq_number == 1) txq_map = (cpu == pp->rxq_def) ? - MVNETA_CPU_TXQ_ACCESS(1) : 0; + MVNETA_CPU_TXQ_ACCESS(0) : 0; } else { txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; @@ -1767,14 +1781,9 @@ static void mvneta_txq_bufs_free(struct mvneta_port *pp, int i; for (i = 0; i < num; i++) { + struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; struct mvneta_tx_desc *tx_desc = txq->descs + txq->txq_get_index; - struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; - - if (skb) { - bytes_compl += skb->len; - pkts_compl++; - } mvneta_txq_inc_get(txq); @@ -1782,9 +1791,12 @@ static void mvneta_txq_bufs_free(struct mvneta_port *pp, dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr, tx_desc->data_size, DMA_TO_DEVICE); - if (!skb) + if (!buf->skb) continue; - dev_kfree_skb_any(skb); + + bytes_compl += buf->skb->len; + pkts_compl++; + dev_kfree_skb_any(buf->skb); } netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); @@ -2238,16 +2250,19 @@ static inline void mvneta_tso_put_hdr(struct sk_buff *skb, struct mvneta_port *pp, struct mvneta_tx_queue *txq) { - struct mvneta_tx_desc *tx_desc; int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); + struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; + struct mvneta_tx_desc *tx_desc; - txq->tx_skb[txq->txq_put_index] = NULL; tx_desc = mvneta_txq_next_desc_get(txq); tx_desc->data_size = hdr_len; tx_desc->command = mvneta_skb_tx_csum(pp, skb); tx_desc->command |= MVNETA_TXD_F_DESC; tx_desc->buf_phys_addr = txq->tso_hdrs_phys + txq->txq_put_index * TSO_HEADER_SIZE; + buf->type = MVNETA_TYPE_SKB; + buf->skb = NULL; + mvneta_txq_inc_put(txq); } @@ -2256,6 +2271,7 @@ mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, struct sk_buff *skb, char *data, int size, bool last_tcp, bool is_last) { + struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; struct mvneta_tx_desc *tx_desc; tx_desc = mvneta_txq_next_desc_get(txq); @@ -2269,7 +2285,8 @@ mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, } tx_desc->command = 0; - txq->tx_skb[txq->txq_put_index] = NULL; + buf->type = MVNETA_TYPE_SKB; + buf->skb = NULL; if (last_tcp) { /* last descriptor in the TCP packet */ @@ -2277,7 +2294,7 @@ mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, /* last descriptor in SKB */ if (is_last) - txq->tx_skb[txq->txq_put_index] = skb; + buf->skb = skb; } mvneta_txq_inc_put(txq); return 0; @@ -2362,6 +2379,7 @@ static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, int i, nr_frags = skb_shinfo(skb)->nr_frags; for (i = 0; i < nr_frags; i++) { + struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; void *addr = page_address(frag->page.p) + frag->page_offset; @@ -2381,12 +2399,13 @@ static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, if (i == nr_frags - 1) { /* Last descriptor */ tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; - txq->tx_skb[txq->txq_put_index] = skb; + buf->skb = skb; } else { /* Descriptor in the middle: Not First, Not Last */ tx_desc->command = 0; - txq->tx_skb[txq->txq_put_index] = NULL; + buf->skb = NULL; } + buf->type = MVNETA_TYPE_SKB; mvneta_txq_inc_put(txq); } @@ -2414,6 +2433,7 @@ static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) struct mvneta_port *pp = netdev_priv(dev); u16 txq_id = skb_get_queue_mapping(skb); struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; + struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; struct mvneta_tx_desc *tx_desc; int len = skb->len; int frags = 0; @@ -2446,16 +2466,17 @@ static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) goto out; } + buf->type = MVNETA_TYPE_SKB; if (frags == 1) { /* First and Last descriptor */ tx_cmd |= MVNETA_TXD_FLZ_DESC; tx_desc->command = tx_cmd; - txq->tx_skb[txq->txq_put_index] = skb; + buf->skb = skb; mvneta_txq_inc_put(txq); } else { /* First but not Last */ tx_cmd |= MVNETA_TXD_F_DESC; - txq->tx_skb[txq->txq_put_index] = NULL; + buf->skb = NULL; mvneta_txq_inc_put(txq); tx_desc->command = tx_cmd; /* Continue with other skb fragments */ @@ -3000,9 +3021,8 @@ static int mvneta_txq_sw_init(struct mvneta_port *pp, txq->last_desc = txq->size - 1; - txq->tx_skb = kmalloc_array(txq->size, sizeof(*txq->tx_skb), - GFP_KERNEL); - if (!txq->tx_skb) { + txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); + if (!txq->buf) { dma_free_coherent(pp->dev->dev.parent, txq->size * MVNETA_DESC_ALIGNED_SIZE, txq->descs, txq->descs_phys); @@ -3014,7 +3034,7 @@ static int mvneta_txq_sw_init(struct mvneta_port *pp, txq->size * TSO_HEADER_SIZE, &txq->tso_hdrs_phys, GFP_KERNEL); if (!txq->tso_hdrs) { - kfree(txq->tx_skb); + kfree(txq->buf); dma_free_coherent(pp->dev->dev.parent, txq->size * MVNETA_DESC_ALIGNED_SIZE, txq->descs, txq->descs_phys); @@ -3069,7 +3089,7 @@ static void mvneta_txq_sw_deinit(struct mvneta_port *pp, { struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); - kfree(txq->tx_skb); + kfree(txq->buf); if (txq->tso_hdrs) dma_free_coherent(pp->dev->dev.parent, @@ -3645,7 +3665,7 @@ static void mvneta_percpu_elect(struct mvneta_port *pp) */ if (txq_number == 1) txq_map = (cpu == elected_cpu) ? - MVNETA_CPU_TXQ_ACCESS(1) : 0; + MVNETA_CPU_TXQ_ACCESS(0) : 0; else txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & MVNETA_CPU_TXQ_ACCESS_ALL_MASK; diff --git a/drivers/net/ethernet/marvell/sky2.h b/drivers/net/ethernet/marvell/sky2.h index b02b6523083ce988f743bac543c595d776fe908e..99451585a45f2d1052bcc5ec43bda76a6d858139 100644 --- a/drivers/net/ethernet/marvell/sky2.h +++ b/drivers/net/ethernet/marvell/sky2.h @@ -2201,7 +2201,7 @@ struct rx_ring_info { struct sk_buff *skb; dma_addr_t data_addr; DEFINE_DMA_UNMAP_LEN(data_size); - dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT]; + dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT ?: 1]; }; enum flow_control { diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 53cff913abf0b49edf07a5bfffeb15cf6da8eca7..1a4f96894cd708adcc091d9c7686b683a49e546a 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -1621,6 +1621,9 @@ static int mtk_hwlro_get_fdir_all(struct net_device *dev, int i; for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { + if (cnt == cmd->rule_cnt) + return -EMSGSIZE; + if (mac->hwlro_ip[i]) { rule_locs[cnt] = i; cnt++; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c b/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c index ef9f932f02263f62b9af2876e43a2ccb33b7f556..97e6b06b1bff3154e931decb9be31716d91d9100 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c @@ -466,7 +466,7 @@ static void poll_trace(struct mlx5_fw_tracer *tracer, (u64)timestamp_low; break; default: - if (tracer_event->event_id >= tracer->str_db.first_string_trace || + if (tracer_event->event_id >= tracer->str_db.first_string_trace && tracer_event->event_id <= tracer->str_db.first_string_trace + tracer->str_db.num_string_trace) { tracer_event->type = TRACER_EVENT_TYPE_STRING; @@ -564,7 +564,7 @@ static int mlx5_tracer_handle_string_trace(struct mlx5_fw_tracer *tracer, } else { cur_string = mlx5_tracer_message_get(tracer, tracer_event); if (!cur_string) { - pr_debug("%s Got string event for unknown string tdsm: %d\n", + pr_debug("%s Got string event for unknown string tmsn: %d\n", __func__, tracer_event->string_event.tmsn); return -1; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c index 128a82b1dbfc66147c1df824613f5d1e807a6e40..ad9db70eb879e64c4b52b4a9182a5ccdf558c2b8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c @@ -121,7 +121,9 @@ static int mlx5e_ipsec_remove_trailer(struct sk_buff *skb, struct xfrm_state *x) trailer_len = alen + plen + 2; - pskb_trim(skb, skb->len - trailer_len); + ret = pskb_trim(skb, skb->len - trailer_len); + if (unlikely(ret)) + return ret; if (skb->protocol == htons(ETH_P_IP)) { ipv4hdr->tot_len = htons(ntohs(ipv4hdr->tot_len) - trailer_len); ip_send_check(ipv4hdr); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c b/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c index 722998d685646ebd2502dd25479a5d51127ac35c..6f1f53f91ed8c590cb2b7fc3093ebbcef5d7568d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c @@ -109,12 +109,14 @@ static int mlx5e_dcbnl_ieee_getets(struct net_device *netdev, if (!MLX5_CAP_GEN(priv->mdev, ets)) return -EOPNOTSUPP; - ets->ets_cap = mlx5_max_tc(priv->mdev) + 1; - for (i = 0; i < ets->ets_cap; i++) { + for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { err = mlx5_query_port_prio_tc(mdev, i, &ets->prio_tc[i]); if (err) return err; + } + ets->ets_cap = mlx5_max_tc(priv->mdev) + 1; + for (i = 0; i < ets->ets_cap; i++) { err = mlx5_query_port_tc_group(mdev, i, &tc_group[i]); if (err) return err; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c b/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c index 9c3653e06886a679eca755f00f6459b2b4068e8a..c9ba97b400fa1242747f19cfeeea468e865ccb59 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c @@ -164,7 +164,8 @@ static int alloc_4k(struct mlx5_core_dev *dev, u64 *addr) fp = list_entry(dev->priv.free_list.next, struct fw_page, list); n = find_first_bit(&fp->bitmask, 8 * sizeof(fp->bitmask)); if (n >= MLX5_NUM_4K_IN_PAGE) { - mlx5_core_warn(dev, "alloc 4k bug\n"); + mlx5_core_warn(dev, "alloc 4k bug: fw page = 0x%llx, n = %u, bitmask: %lu, max num of 4K pages: %d\n", + fp->addr, n, fp->bitmask, MLX5_NUM_4K_IN_PAGE); return -ENOENT; } clear_bit(n, &fp->bitmask); @@ -470,8 +471,8 @@ void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot) { - u16 uninitialized_var(func_id); - s32 uninitialized_var(npages); + u16 func_id; + s32 npages; int err; err = mlx5_cmd_query_pages(dev, &func_id, &npages, boot); diff --git a/drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2_tlv_multi.c b/drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2_tlv_multi.c index 0094b92a233ba5d635f66e3a92ff12baee56c3fb..31c0d6ee81b1655cc716fcedc3fdd2a098b13c1e 100644 --- a/drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2_tlv_multi.c +++ b/drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2_tlv_multi.c @@ -62,6 +62,8 @@ mlxfw_mfa2_tlv_next(const struct mlxfw_mfa2_file *mfa2_file, if (tlv->type == MLXFW_MFA2_TLV_MULTI_PART) { multi = mlxfw_mfa2_tlv_multi_get(mfa2_file, tlv); + if (!multi) + return NULL; tlv_len = NLA_ALIGN(tlv_len + be16_to_cpu(multi->total_len)); } diff --git a/drivers/net/ethernet/microchip/lan743x_main.c b/drivers/net/ethernet/microchip/lan743x_main.c index e734bc5e3ceb47973c31212a5b3ee368f2ad22cd..112d374e716636b6213ad2334825541b4542674a 100644 --- a/drivers/net/ethernet/microchip/lan743x_main.c +++ b/drivers/net/ethernet/microchip/lan743x_main.c @@ -80,6 +80,18 @@ static int lan743x_csr_light_reset(struct lan743x_adapter *adapter) !(data & HW_CFG_LRST_), 100000, 10000000); } +static int lan743x_csr_wait_for_bit_atomic(struct lan743x_adapter *adapter, + int offset, u32 bit_mask, + int target_value, int udelay_min, + int udelay_max, int count) +{ + u32 data; + + return readx_poll_timeout_atomic(LAN743X_CSR_READ_OP, offset, data, + target_value == !!(data & bit_mask), + udelay_max, udelay_min * count); +} + static int lan743x_csr_wait_for_bit(struct lan743x_adapter *adapter, int offset, u32 bit_mask, int target_value, int usleep_min, @@ -675,8 +687,8 @@ static int lan743x_dp_write(struct lan743x_adapter *adapter, u32 dp_sel; int i; - if (lan743x_csr_wait_for_bit(adapter, DP_SEL, DP_SEL_DPRDY_, - 1, 40, 100, 100)) + if (lan743x_csr_wait_for_bit_atomic(adapter, DP_SEL, DP_SEL_DPRDY_, + 1, 40, 100, 100)) return -EIO; dp_sel = lan743x_csr_read(adapter, DP_SEL); dp_sel &= ~DP_SEL_MASK_; @@ -687,8 +699,9 @@ static int lan743x_dp_write(struct lan743x_adapter *adapter, lan743x_csr_write(adapter, DP_ADDR, addr + i); lan743x_csr_write(adapter, DP_DATA_0, buf[i]); lan743x_csr_write(adapter, DP_CMD, DP_CMD_WRITE_); - if (lan743x_csr_wait_for_bit(adapter, DP_SEL, DP_SEL_DPRDY_, - 1, 40, 100, 100)) + if (lan743x_csr_wait_for_bit_atomic(adapter, DP_SEL, + DP_SEL_DPRDY_, + 1, 40, 100, 100)) return -EIO; } diff --git a/drivers/net/ethernet/natsemi/sonic.c b/drivers/net/ethernet/natsemi/sonic.c index 69282f31d519e81ee02a86ad106c6040479c0912..fe54bcab705f8af5afd14f990952b54ddb92afbd 100644 --- a/drivers/net/ethernet/natsemi/sonic.c +++ b/drivers/net/ethernet/natsemi/sonic.c @@ -255,7 +255,7 @@ static int sonic_send_packet(struct sk_buff *skb, struct net_device *dev) */ laddr = dma_map_single(lp->device, skb->data, length, DMA_TO_DEVICE); - if (!laddr) { + if (dma_mapping_error(lp->device, laddr)) { pr_err_ratelimited("%s: failed to map tx DMA buffer.\n", dev->name); dev_kfree_skb_any(skb); return NETDEV_TX_OK; @@ -473,7 +473,7 @@ static bool sonic_alloc_rb(struct net_device *dev, struct sonic_local *lp, *new_addr = dma_map_single(lp->device, skb_put(*new_skb, SONIC_RBSIZE), SONIC_RBSIZE, DMA_FROM_DEVICE); - if (!*new_addr) { + if (dma_mapping_error(lp->device, *new_addr)) { dev_kfree_skb(*new_skb); *new_skb = NULL; return false; diff --git a/drivers/net/ethernet/neterion/s2io.c b/drivers/net/ethernet/neterion/s2io.c index b42f81d0c6f0543fce583876964b3cecffbd091f..f5272d2fcc7e494f292cefe3b4b06176bcd6e61c 100644 --- a/drivers/net/ethernet/neterion/s2io.c +++ b/drivers/net/ethernet/neterion/s2io.c @@ -7291,7 +7291,7 @@ static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp) int ring_no = ring_data->ring_no; u16 l3_csum, l4_csum; unsigned long long err = rxdp->Control_1 & RXD_T_CODE; - struct lro *uninitialized_var(lro); + struct lro *lro; u8 err_mask; struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; diff --git a/drivers/net/ethernet/nvidia/forcedeth.c b/drivers/net/ethernet/nvidia/forcedeth.c index 1d9b0d44ddb693fbc4816b055581ffc0aa7e88cf..45be26dbdd11ccf811a0c35289eb5dec5c0005c4 100644 --- a/drivers/net/ethernet/nvidia/forcedeth.c +++ b/drivers/net/ethernet/nvidia/forcedeth.c @@ -6061,6 +6061,7 @@ static int nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) return 0; out_error: + nv_mgmt_release_sema(dev); if (phystate_orig) writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); out_freering: diff --git a/drivers/net/ethernet/pasemi/pasemi_mac.c b/drivers/net/ethernet/pasemi/pasemi_mac.c index e2c280913fbbbf7ec810a58a0af4a50df7c04691..8238a701615994619fa13fc1dca14b2cdbea70a9 100644 --- a/drivers/net/ethernet/pasemi/pasemi_mac.c +++ b/drivers/net/ethernet/pasemi/pasemi_mac.c @@ -1435,7 +1435,7 @@ static void pasemi_mac_queue_csdesc(const struct sk_buff *skb, write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2); } -static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) +static netdev_tx_t pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) { struct pasemi_mac * const mac = netdev_priv(dev); struct pasemi_mac_txring * const txring = tx_ring(mac); diff --git a/drivers/net/ethernet/qlogic/qed/qed_dev.c b/drivers/net/ethernet/qlogic/qed/qed_dev.c index e50fc8f714dcf6cb3f46e92d5c551532459000a4..7e5beb4136014f2531a803b0266b21d404d1b300 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_dev.c +++ b/drivers/net/ethernet/qlogic/qed/qed_dev.c @@ -4062,6 +4062,11 @@ static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, num_vports = p_hwfn->qm_info.num_vports; + if (num_vports < 2) { + DP_NOTICE(p_hwfn, "Unexpected num_vports: %d\n", num_vports); + return -EINVAL; + } + /* Accounting for the vports which are configured for WFQ explicitly */ for (i = 0; i < num_vports; i++) { u32 tmp_speed; diff --git a/drivers/net/ethernet/qlogic/qed/qed_ll2.h b/drivers/net/ethernet/qlogic/qed/qed_ll2.h index f65817012e9722e5a47458d30a47ef79209075a7..785899d3511cb9df3f0208d96222618bbc5fa797 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_ll2.h +++ b/drivers/net/ethernet/qlogic/qed/qed_ll2.h @@ -122,9 +122,9 @@ struct qed_ll2_info { enum core_tx_dest tx_dest; u8 tx_stats_en; bool main_func_queue; + struct qed_ll2_cbs cbs; struct qed_ll2_rx_queue rx_queue; struct qed_ll2_tx_queue tx_queue; - struct qed_ll2_cbs cbs; }; /** diff --git a/drivers/net/ethernet/qlogic/qed/qed_sriov.c b/drivers/net/ethernet/qlogic/qed/qed_sriov.c index 402c1c3d84ce293bf2589d497a3fdabe5a474be6..5c8eaded6b30df7b4402e8d00d08b7cb17f8adec 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_sriov.c +++ b/drivers/net/ethernet/qlogic/qed/qed_sriov.c @@ -4403,6 +4403,9 @@ qed_iov_configure_min_tx_rate(struct qed_dev *cdev, int vfid, u32 rate) } vf = qed_iov_get_vf_info(QED_LEADING_HWFN(cdev), (u16)vfid, true); + if (!vf) + return -EINVAL; + vport_id = vf->vport_id; return qed_configure_vport_wfq(cdev, vport_id, rate); @@ -5142,7 +5145,7 @@ static void qed_iov_handle_trust_change(struct qed_hwfn *hwfn) /* Validate that the VF has a configured vport */ vf = qed_iov_get_vf_info(hwfn, i, true); - if (!vf->vport_instance) + if (!vf || !vf->vport_instance) continue; memset(¶ms, 0, sizeof(params)); diff --git a/drivers/net/ethernet/qlogic/qla3xxx.c b/drivers/net/ethernet/qlogic/qla3xxx.c index 7a65a1534e41ab2167eea3d8c1a3101f75a1a28c..d545593354c63c15b77716471ce149d915d9a6df 100644 --- a/drivers/net/ethernet/qlogic/qla3xxx.c +++ b/drivers/net/ethernet/qlogic/qla3xxx.c @@ -3771,7 +3771,7 @@ static int ql3xxx_probe(struct pci_dev *pdev, struct net_device *ndev = NULL; struct ql3_adapter *qdev = NULL; static int cards_found; - int uninitialized_var(pci_using_dac), err; + int pci_using_dac, err; err = pci_enable_device(pdev); if (err) { diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c index d344e9d438321873fa8e4dedf745a74aeeb3db52..d3030bd967d5aacad6c19af44b60a111432446d4 100644 --- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c +++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c @@ -629,7 +629,13 @@ int qlcnic_fw_create_ctx(struct qlcnic_adapter *dev) int i, err, ring; if (dev->flags & QLCNIC_NEED_FLR) { - pci_reset_function(dev->pdev); + err = pci_reset_function(dev->pdev); + if (err) { + dev_err(&dev->pdev->dev, + "Adapter reset failed (%d). Please reboot\n", + err); + return err; + } dev->flags &= ~QLCNIC_NEED_FLR; } diff --git a/drivers/net/ethernet/qualcomm/emac/emac.c b/drivers/net/ethernet/qualcomm/emac/emac.c index 76a9b37c8680f4d59015ec5307e83ff14cb760b6..3c764c28d5dbcee137d106f61655d838f7ba3e14 100644 --- a/drivers/net/ethernet/qualcomm/emac/emac.c +++ b/drivers/net/ethernet/qualcomm/emac/emac.c @@ -752,9 +752,15 @@ static int emac_remove(struct platform_device *pdev) struct net_device *netdev = dev_get_drvdata(&pdev->dev); struct emac_adapter *adpt = netdev_priv(netdev); + netif_carrier_off(netdev); + netif_tx_disable(netdev); + unregister_netdev(netdev); netif_napi_del(&adpt->rx_q.napi); + free_irq(adpt->irq.irq, &adpt->irq); + cancel_work_sync(&adpt->work_thread); + emac_clks_teardown(adpt); put_device(&adpt->phydev->mdio.dev); diff --git a/drivers/net/ethernet/qualcomm/qca_spi.c b/drivers/net/ethernet/qualcomm/qca_spi.c index afd49c7fd87fe33999a23e56cc52580072011eb4..3e6095f0cb5f59bc234b6f26d52f2d9a41e8a95e 100644 --- a/drivers/net/ethernet/qualcomm/qca_spi.c +++ b/drivers/net/ethernet/qualcomm/qca_spi.c @@ -553,8 +553,7 @@ qcaspi_spi_thread(void *data) while (!kthread_should_stop()) { set_current_state(TASK_INTERRUPTIBLE); if ((qca->intr_req == qca->intr_svc) && - (qca->txr.skb[qca->txr.head] == NULL) && - (qca->sync == QCASPI_SYNC_READY)) + !qca->txr.skb[qca->txr.head]) schedule(); set_current_state(TASK_RUNNING); diff --git a/drivers/net/ethernet/realtek/Makefile b/drivers/net/ethernet/realtek/Makefile index 71b1da30ecb5b380cab2cfb0baf6b372b4a75fc0..7f68be4b9f51fc50ac7c0118cbd0f1727b66635d 100644 --- a/drivers/net/ethernet/realtek/Makefile +++ b/drivers/net/ethernet/realtek/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_8139CP) += 8139cp.o obj-$(CONFIG_8139TOO) += 8139too.o obj-$(CONFIG_ATP) += atp.o +r8169-objs += r8169_main.o obj-$(CONFIG_R8169) += r8169.o diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169_main.c similarity index 99% rename from drivers/net/ethernet/realtek/r8169.c rename to drivers/net/ethernet/realtek/r8169_main.c index 523626f2ffbeb970b82e2007e3d5783f470832c2..ecdf628e3bb89fe6a94ebb0af75370e00c544440 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -66,7 +66,7 @@ /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). The RTL chips use a 64 element hash table based on the Ethernet CRC. */ -static const int multicast_filter_limit = 32; +#define MC_FILTER_LIMIT 32 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ @@ -4614,54 +4614,48 @@ static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_versi static void rtl_set_rx_mode(struct net_device *dev) { + u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; + /* Multicast hash filter */ + u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; struct rtl8169_private *tp = netdev_priv(dev); - u32 mc_filter[2]; /* Multicast hash filter */ - int rx_mode; - u32 tmp = 0; + u32 tmp; if (dev->flags & IFF_PROMISC) { /* Unconditionally log net taps. */ netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); - rx_mode = - AcceptBroadcast | AcceptMulticast | AcceptMyPhys | - AcceptAllPhys; - mc_filter[1] = mc_filter[0] = 0xffffffff; - } else if ((netdev_mc_count(dev) > multicast_filter_limit) || - (dev->flags & IFF_ALLMULTI)) { - /* Too many to filter perfectly -- accept all multicasts. */ - rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; - mc_filter[1] = mc_filter[0] = 0xffffffff; + rx_mode |= AcceptAllPhys; + } else if (!(dev->flags & IFF_MULTICAST)) { + rx_mode &= ~AcceptMulticast; + } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || + dev->flags & IFF_ALLMULTI || + tp->mac_version == RTL_GIGA_MAC_VER_35) { + /* accept all multicasts */ + } else if (netdev_mc_empty(dev)) { + rx_mode &= ~AcceptMulticast; } else { struct netdev_hw_addr *ha; - rx_mode = AcceptBroadcast | AcceptMyPhys; mc_filter[1] = mc_filter[0] = 0; netdev_for_each_mc_addr(ha, dev) { - int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; - mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); - rx_mode |= AcceptMulticast; + u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; + mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); + } + + if (tp->mac_version > RTL_GIGA_MAC_VER_06) { + tmp = mc_filter[0]; + mc_filter[0] = swab32(mc_filter[1]); + mc_filter[1] = swab32(tmp); } } if (dev->features & NETIF_F_RXALL) rx_mode |= (AcceptErr | AcceptRunt); - tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; - - if (tp->mac_version > RTL_GIGA_MAC_VER_06) { - u32 data = mc_filter[0]; - - mc_filter[0] = swab32(mc_filter[1]); - mc_filter[1] = swab32(data); - } - - if (tp->mac_version == RTL_GIGA_MAC_VER_35) - mc_filter[1] = mc_filter[0] = 0xffffffff; - RTL_W32(tp, MAR0 + 4, mc_filter[1]); RTL_W32(tp, MAR0 + 0, mc_filter[0]); - RTL_W32(tp, RxConfig, tmp); + tmp = RTL_R32(tp, RxConfig); + RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode); } static void rtl_hw_start(struct rtl8169_private *tp) @@ -6445,7 +6439,7 @@ static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp) struct ring_info *tx_skb = tp->tx_skb + entry; u32 status; - status = le32_to_cpu(tp->TxDescArray[entry].opts1); + status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); if (status & DescOwn) break; @@ -6541,7 +6535,7 @@ static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget struct RxDesc *desc = tp->RxDescArray + entry; u32 status; - status = le32_to_cpu(desc->opts1); + status = le32_to_cpu(READ_ONCE(desc->opts1)); if (status & DescOwn) break; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 7e2e79dedebf2c23ae93fef4dd9cc651701feaf0..df7fc6b675a53e56a742f1ddade8a2ec343b0f32 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -57,6 +57,7 @@ struct stm32_ops { int (*parse_data)(struct stm32_dwmac *dwmac, struct device *dev); u32 syscfg_eth_mask; + bool clk_rx_enable_in_suspend; }; static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat) @@ -74,7 +75,8 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat) if (ret) return ret; - if (!dwmac->dev->power.is_suspended) { + if (!dwmac->ops->clk_rx_enable_in_suspend || + !dwmac->dev->power.is_suspended) { ret = clk_prepare_enable(dwmac->clk_rx); if (ret) { clk_disable_unprepare(dwmac->clk_tx); @@ -413,7 +415,8 @@ static struct stm32_ops stm32mp1_dwmac_data = { .suspend = stm32mp1_suspend, .resume = stm32mp1_resume, .parse_data = stm32mp1_parse_data, - .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK + .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK, + .clk_rx_enable_in_suspend = true }; static const struct of_device_id stm32_dwmac_match[] = { diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 0a4d093adfc9394826ebb0790dc6613a91cc2292..3e35cdf0d2b7690889c5d2ead6c38059b15c2268 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -114,6 +114,7 @@ MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); static irqreturn_t stmmac_interrupt(int irq, void *dev_id); #ifdef CONFIG_DEBUG_FS +static const struct net_device_ops stmmac_netdev_ops; static int stmmac_init_fs(struct net_device *dev); static void stmmac_exit_fs(struct net_device *dev); #endif @@ -4034,6 +4035,34 @@ static const struct file_operations stmmac_dma_cap_fops = { .release = single_release, }; +/* Use network device events to rename debugfs file entries. + */ +static int stmmac_device_event(struct notifier_block *unused, + unsigned long event, void *ptr) +{ + struct net_device *dev = netdev_notifier_info_to_dev(ptr); + struct stmmac_priv *priv = netdev_priv(dev); + + if (dev->netdev_ops != &stmmac_netdev_ops) + goto done; + + switch (event) { + case NETDEV_CHANGENAME: + if (priv->dbgfs_dir) + priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, + priv->dbgfs_dir, + stmmac_fs_dir, + dev->name); + break; + } +done: + return NOTIFY_DONE; +} + +static struct notifier_block stmmac_notifier = { + .notifier_call = stmmac_device_event, +}; + static int stmmac_init_fs(struct net_device *dev) { struct stmmac_priv *priv = netdev_priv(dev); @@ -4072,6 +4101,8 @@ static int stmmac_init_fs(struct net_device *dev) return -ENOMEM; } + register_netdevice_notifier(&stmmac_notifier); + return 0; } @@ -4079,6 +4110,7 @@ static void stmmac_exit_fs(struct net_device *dev) { struct stmmac_priv *priv = netdev_priv(dev); + unregister_netdevice_notifier(&stmmac_notifier); debugfs_remove_recursive(priv->dbgfs_dir); } #endif /* CONFIG_DEBUG_FS */ diff --git a/drivers/net/ethernet/sun/cassini.c b/drivers/net/ethernet/sun/cassini.c index d323dd9daccb00d424eda9b4578974196cc92663..861d1f6d7508f044d00171cb6f88790b54a85c12 100644 --- a/drivers/net/ethernet/sun/cassini.c +++ b/drivers/net/ethernet/sun/cassini.c @@ -1337,7 +1337,7 @@ static void cas_init_rx_dma(struct cas *cp) writel(val, cp->regs + REG_RX_PAGE_SIZE); /* enable the header parser if desired */ - if (CAS_HP_FIRMWARE == cas_prog_null) + if (&CAS_HP_FIRMWARE[0] == &cas_prog_null[0]) return; val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS); @@ -2291,7 +2291,7 @@ static int cas_rx_ringN(struct cas *cp, int ring, int budget) drops = 0; while (1) { struct cas_rx_comp *rxc = rxcs + entry; - struct sk_buff *uninitialized_var(skb); + struct sk_buff *skb; int type, len; u64 words[4]; int i, dring; @@ -3807,7 +3807,7 @@ static void cas_reset(struct cas *cp, int blkflag) /* program header parser */ if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) || - (CAS_HP_ALT_FIRMWARE == cas_prog_null)) { + (&CAS_HP_ALT_FIRMWARE[0] == &cas_prog_null[0])) { cas_load_firmware(cp, CAS_HP_FIRMWARE); } else { cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE); @@ -5138,6 +5138,8 @@ static int cas_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) cas_shutdown(cp); mutex_unlock(&cp->pm_mutex); + vfree(cp->fw_data); + pci_iounmap(pdev, cp->regs); diff --git a/drivers/net/ethernet/sun/ldmvsw.c b/drivers/net/ethernet/sun/ldmvsw.c index 644e42c181ee6030dee0222479daf314a290a1f5..1c9522ad31787abcdf2ab52ec038895cd822d567 100644 --- a/drivers/net/ethernet/sun/ldmvsw.c +++ b/drivers/net/ethernet/sun/ldmvsw.c @@ -291,6 +291,9 @@ static int vsw_port_probe(struct vio_dev *vdev, const struct vio_device_id *id) hp = mdesc_grab(); + if (!hp) + return -ENODEV; + rmac = mdesc_get_property(hp, vdev->mp, remote_macaddr_prop, &len); err = -ENODEV; if (!rmac) { diff --git a/drivers/net/ethernet/sun/niu.c b/drivers/net/ethernet/sun/niu.c index 605c4d15b88c17572d6318260c54c293a44094cb..1c13c08c4f96550abdf0236ce8bdcdf0c7fa65c2 100644 --- a/drivers/net/ethernet/sun/niu.c +++ b/drivers/net/ethernet/sun/niu.c @@ -429,7 +429,7 @@ static int serdes_init_niu_1g_serdes(struct niu *np) struct niu_link_config *lp = &np->link_config; u16 pll_cfg, pll_sts; int max_retry = 100; - u64 uninitialized_var(sig), mask, val; + u64 sig, mask, val; u32 tx_cfg, rx_cfg; unsigned long i; int err; @@ -526,7 +526,7 @@ static int serdes_init_niu_10g_serdes(struct niu *np) struct niu_link_config *lp = &np->link_config; u32 tx_cfg, rx_cfg, pll_cfg, pll_sts; int max_retry = 100; - u64 uninitialized_var(sig), mask, val; + u64 sig, mask, val; unsigned long i; int err; @@ -714,7 +714,7 @@ static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val) static int esr_reset(struct niu *np) { - u32 uninitialized_var(reset); + u32 reset; int err; err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, @@ -4505,7 +4505,7 @@ static int niu_alloc_channels(struct niu *np) err = niu_rbr_fill(np, rp, GFP_KERNEL); if (err) - return err; + goto out_err; } tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info), diff --git a/drivers/net/ethernet/sun/sunvnet.c b/drivers/net/ethernet/sun/sunvnet.c index 590172818b922f069a82765ff5042cd852093c27..3a1f0653cfb76ee7ac5abf19c28f3a9c7794015c 100644 --- a/drivers/net/ethernet/sun/sunvnet.c +++ b/drivers/net/ethernet/sun/sunvnet.c @@ -432,6 +432,9 @@ static int vnet_port_probe(struct vio_dev *vdev, const struct vio_device_id *id) hp = mdesc_grab(); + if (!hp) + return -ENODEV; + vp = vnet_find_parent(hp, vdev->mp, vdev); if (IS_ERR(vp)) { pr_err("Cannot find port parent vnet\n"); diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index c245629a38c7675ae273139abb968beb786fbc90..6cb98760bc84ea48cfcfcb9e41a182f1d1c46b13 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -67,23 +67,37 @@ static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) { - int idx; + int idx, idx2; + u32 hi_val = 0; idx = start / 32; + idx2 = (start + bits - 1) / 32; + /* Check if bits to be fetched exceed a word */ + if (idx != idx2) { + idx2 = 2 - idx2; /* flip */ + hi_val = ale_entry[idx2] << ((idx2 * 32) - start); + } start -= idx * 32; idx = 2 - idx; /* flip */ - return (ale_entry[idx] >> start) & BITMASK(bits); + return (hi_val + (ale_entry[idx] >> start)) & BITMASK(bits); } static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, u32 value) { - int idx; + int idx, idx2; value &= BITMASK(bits); - idx = start / 32; + idx = start / 32; + idx2 = (start + bits - 1) / 32; + /* Check if bits to be set exceed a word */ + if (idx != idx2) { + idx2 = 2 - idx2; /* flip */ + ale_entry[idx2] &= ~(BITMASK(bits + start - (idx2 * 32))); + ale_entry[idx2] |= (value >> ((idx2 * 32) - start)); + } start -= idx * 32; - idx = 2 - idx; /* flip */ + idx = 2 - idx; /* flip */ ale_entry[idx] &= ~(BITMASK(bits) << start); ale_entry[idx] |= (value << start); } diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_net.c b/drivers/net/ethernet/toshiba/ps3_gelic_net.c index 75237c81c63d65dda6951137bcd69ce43b5d65cd..572294678faf023b2d1ca38675d4e3505a310062 100644 --- a/drivers/net/ethernet/toshiba/ps3_gelic_net.c +++ b/drivers/net/ethernet/toshiba/ps3_gelic_net.c @@ -330,15 +330,17 @@ static int gelic_card_init_chain(struct gelic_card *card, /* set up the hardware pointers in each descriptor */ for (i = 0; i < no; i++, descr++) { + dma_addr_t cpu_addr; + gelic_descr_set_status(descr, GELIC_DESCR_DMA_NOT_IN_USE); - descr->bus_addr = - dma_map_single(ctodev(card), descr, - GELIC_DESCR_SIZE, - DMA_BIDIRECTIONAL); - if (!descr->bus_addr) + cpu_addr = dma_map_single(ctodev(card), descr, + GELIC_DESCR_SIZE, DMA_BIDIRECTIONAL); + + if (dma_mapping_error(ctodev(card), cpu_addr)) goto iommu_error; + descr->bus_addr = cpu_to_be32(cpu_addr); descr->next = descr + 1; descr->prev = descr - 1; } @@ -378,28 +380,30 @@ static int gelic_card_init_chain(struct gelic_card *card, * * allocates a new rx skb, iommu-maps it and attaches it to the descriptor. * Activate the descriptor state-wise + * + * Gelic RX sk_buffs must be aligned to GELIC_NET_RXBUF_ALIGN and the length + * must be a multiple of GELIC_NET_RXBUF_ALIGN. */ static int gelic_descr_prepare_rx(struct gelic_card *card, struct gelic_descr *descr) { + static const unsigned int rx_skb_size = + ALIGN(GELIC_NET_MAX_FRAME, GELIC_NET_RXBUF_ALIGN) + + GELIC_NET_RXBUF_ALIGN - 1; + dma_addr_t cpu_addr; int offset; - unsigned int bufsize; if (gelic_descr_get_status(descr) != GELIC_DESCR_DMA_NOT_IN_USE) dev_info(ctodev(card), "%s: ERROR status\n", __func__); - /* we need to round up the buffer size to a multiple of 128 */ - bufsize = ALIGN(GELIC_NET_MAX_MTU, GELIC_NET_RXBUF_ALIGN); - /* and we need to have it 128 byte aligned, therefore we allocate a - * bit more */ - descr->skb = dev_alloc_skb(bufsize + GELIC_NET_RXBUF_ALIGN - 1); + descr->skb = netdev_alloc_skb(*card->netdev, rx_skb_size); if (!descr->skb) { descr->buf_addr = 0; /* tell DMAC don't touch memory */ dev_info(ctodev(card), "%s:allocate skb failed !!\n", __func__); return -ENOMEM; } - descr->buf_size = cpu_to_be32(bufsize); + descr->buf_size = cpu_to_be32(rx_skb_size); descr->dmac_cmd_status = 0; descr->result_size = 0; descr->valid_size = 0; @@ -410,11 +414,10 @@ static int gelic_descr_prepare_rx(struct gelic_card *card, if (offset) skb_reserve(descr->skb, GELIC_NET_RXBUF_ALIGN - offset); /* io-mmu-map the skb */ - descr->buf_addr = cpu_to_be32(dma_map_single(ctodev(card), - descr->skb->data, - GELIC_NET_MAX_MTU, - DMA_FROM_DEVICE)); - if (!descr->buf_addr) { + cpu_addr = dma_map_single(ctodev(card), descr->skb->data, + GELIC_NET_MAX_FRAME, DMA_FROM_DEVICE); + descr->buf_addr = cpu_to_be32(cpu_addr); + if (dma_mapping_error(ctodev(card), cpu_addr)) { dev_kfree_skb_any(descr->skb); descr->skb = NULL; dev_info(ctodev(card), @@ -794,7 +797,7 @@ static int gelic_descr_prepare_tx(struct gelic_card *card, buf = dma_map_single(ctodev(card), skb->data, skb->len, DMA_TO_DEVICE); - if (!buf) { + if (dma_mapping_error(ctodev(card), buf)) { dev_err(ctodev(card), "dma map 2 failed (%p, %i). Dropping packet\n", skb->data, skb->len); @@ -930,7 +933,7 @@ static void gelic_net_pass_skb_up(struct gelic_descr *descr, data_error = be32_to_cpu(descr->data_error); /* unmap skb buffer */ dma_unmap_single(ctodev(card), be32_to_cpu(descr->buf_addr), - GELIC_NET_MAX_MTU, + GELIC_NET_MAX_FRAME, DMA_FROM_DEVICE); skb_put(skb, be32_to_cpu(descr->valid_size)? diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_net.h b/drivers/net/ethernet/toshiba/ps3_gelic_net.h index fbbf9b54b173bfc3d14c61253e83e51d3f4088db..0e592fc19f6c54c2590b872916111cf8027bbd46 100644 --- a/drivers/net/ethernet/toshiba/ps3_gelic_net.h +++ b/drivers/net/ethernet/toshiba/ps3_gelic_net.h @@ -32,8 +32,9 @@ #define GELIC_NET_RX_DESCRIPTORS 128 /* num of descriptors */ #define GELIC_NET_TX_DESCRIPTORS 128 /* num of descriptors */ -#define GELIC_NET_MAX_MTU VLAN_ETH_FRAME_LEN -#define GELIC_NET_MIN_MTU VLAN_ETH_ZLEN +#define GELIC_NET_MAX_FRAME 2312 +#define GELIC_NET_MAX_MTU 2294 +#define GELIC_NET_MIN_MTU 64 #define GELIC_NET_RXBUF_ALIGN 128 #define GELIC_CARD_RX_CSUM_DEFAULT 1 /* hw chksum */ #define GELIC_NET_WATCHDOG_TIMEOUT 5*HZ diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_wireless.c b/drivers/net/ethernet/toshiba/ps3_gelic_wireless.c index 302079e22b06c7c9992d2f7e2b01b817cccf5906..186f35b2b182b4e2406f34715c93839fcc613c31 100644 --- a/drivers/net/ethernet/toshiba/ps3_gelic_wireless.c +++ b/drivers/net/ethernet/toshiba/ps3_gelic_wireless.c @@ -1232,7 +1232,7 @@ static int gelic_wl_set_encodeext(struct net_device *netdev, key_index = wl->current_key; if (!enc->length && (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY)) { - /* reques to change default key index */ + /* request to change default key index */ pr_debug("%s: request to change default key to %d\n", __func__, key_index); wl->current_key = key_index; diff --git a/drivers/net/ethernet/xircom/xirc2ps_cs.c b/drivers/net/ethernet/xircom/xirc2ps_cs.c index fd5288ff53b5303271f20137dda57f125d879901..e3438cef5f9c66a68434461ae8bfe5edef443300 100644 --- a/drivers/net/ethernet/xircom/xirc2ps_cs.c +++ b/drivers/net/ethernet/xircom/xirc2ps_cs.c @@ -503,6 +503,11 @@ static void xirc2ps_detach(struct pcmcia_device *link) { struct net_device *dev = link->priv; + struct local_info *local = netdev_priv(dev); + + netif_carrier_off(dev); + netif_tx_disable(dev); + cancel_work_sync(&local->tx_timeout_task); dev_dbg(&link->dev, "detach\n"); diff --git a/drivers/net/gtp.c b/drivers/net/gtp.c index e18d06cb2173cb938e4821563f1dd8728374f210..615edcb880372cd9354dd69fa30eac6e0172ff36 100644 --- a/drivers/net/gtp.c +++ b/drivers/net/gtp.c @@ -301,7 +301,9 @@ static void __gtp_encap_destroy(struct sock *sk) gtp->sk1u = NULL; udp_sk(sk)->encap_type = 0; rcu_assign_sk_user_data(sk, NULL); + release_sock(sk); sock_put(sk); + return; } release_sock(sk); } @@ -546,8 +548,9 @@ static int gtp_build_skb_ip4(struct sk_buff *skb, struct net_device *dev, rt->dst.ops->update_pmtu(&rt->dst, NULL, skb, mtu, false); - if (!skb_is_gso(skb) && (iph->frag_off & htons(IP_DF)) && - mtu < ntohs(iph->tot_len)) { + if (iph->frag_off & htons(IP_DF) && + ((!skb_is_gso(skb) && skb->len > mtu) || + (skb_is_gso(skb) && !skb_gso_validate_network_len(skb, mtu)))) { netdev_dbg(dev, "packet too big, fragmentation needed\n"); icmp_ndo_send(skb, ICMP_DEST_UNREACH, ICMP_FRAG_NEEDED, htonl(mtu)); diff --git a/drivers/net/ieee802154/ca8210.c b/drivers/net/ieee802154/ca8210.c index 917edb3d04b7844cacd72c2af341d0fd4365f63e..525f92e896699abdc5a6dfa9967d4adb8096013b 100644 --- a/drivers/net/ieee802154/ca8210.c +++ b/drivers/net/ieee802154/ca8210.c @@ -1943,10 +1943,9 @@ static int ca8210_skb_tx( struct ca8210_priv *priv ) { - int status; struct ieee802154_hdr header = { }; struct secspec secspec; - unsigned int mac_len; + int mac_len, status; dev_dbg(&priv->spi->dev, "%s called\n", __func__); @@ -1954,6 +1953,8 @@ static int ca8210_skb_tx( * packet */ mac_len = ieee802154_hdr_peek_addrs(skb, &header); + if (mac_len < 0) + return mac_len; secspec.security_level = header.sec.level; secspec.key_id_mode = header.sec.key_id_mode; @@ -2780,7 +2781,6 @@ static int ca8210_register_ext_clock(struct spi_device *spi) struct device_node *np = spi->dev.of_node; struct ca8210_priv *priv = spi_get_drvdata(spi); struct ca8210_platform_data *pdata = spi->dev.platform_data; - int ret = 0; if (!np) return -EFAULT; @@ -2797,18 +2797,8 @@ static int ca8210_register_ext_clock(struct spi_device *spi) dev_crit(&spi->dev, "Failed to register external clk\n"); return PTR_ERR(priv->clk); } - ret = of_clk_add_provider(np, of_clk_src_simple_get, priv->clk); - if (ret) { - clk_unregister(priv->clk); - dev_crit( - &spi->dev, - "Failed to register external clock as clock provider\n" - ); - } else { - dev_info(&spi->dev, "External clock set as clock provider\n"); - } - return ret; + return of_clk_add_provider(np, of_clk_src_simple_get, priv->clk); } /** @@ -2820,8 +2810,8 @@ static void ca8210_unregister_ext_clock(struct spi_device *spi) { struct ca8210_priv *priv = spi_get_drvdata(spi); - if (!priv->clk) - return + if (IS_ERR_OR_NULL(priv->clk)) + return; of_clk_del_provider(spi->dev.of_node); clk_unregister(priv->clk); diff --git a/drivers/net/ieee802154/mac802154_hwsim.c b/drivers/net/ieee802154/mac802154_hwsim.c index d07e5571e07ae58af98d3c995328d8ed94ffb18b..1ac600d186886c705cb05a87c76ebd5f5a1615a2 100644 --- a/drivers/net/ieee802154/mac802154_hwsim.c +++ b/drivers/net/ieee802154/mac802154_hwsim.c @@ -540,7 +540,7 @@ static int hwsim_del_edge_nl(struct sk_buff *msg, struct genl_info *info) static int hwsim_set_edge_lqi(struct sk_buff *msg, struct genl_info *info) { struct nlattr *edge_attrs[MAC802154_HWSIM_EDGE_ATTR_MAX + 1]; - struct hwsim_edge_info *einfo; + struct hwsim_edge_info *einfo, *einfo_old; struct hwsim_phy *phy_v0; struct hwsim_edge *e; u32 v0, v1; @@ -580,8 +580,10 @@ static int hwsim_set_edge_lqi(struct sk_buff *msg, struct genl_info *info) list_for_each_entry_rcu(e, &phy_v0->edges, list) { if (e->endpoint->idx == v1) { einfo->lqi = lqi; - rcu_assign_pointer(e->info, einfo); + einfo_old = rcu_replace_pointer(e->info, einfo, + lockdep_is_held(&hwsim_phys_lock)); rcu_read_unlock(); + kfree_rcu(einfo_old, rcu); mutex_unlock(&hwsim_phys_lock); return 0; } diff --git a/drivers/net/ipvlan/ipvlan_core.c b/drivers/net/ipvlan/ipvlan_core.c index 63f0226b0a70ca8148db5a56cca36a3578f855c7..2f6518f53cf881b88208b9f6b088657fa5c0072d 100644 --- a/drivers/net/ipvlan/ipvlan_core.c +++ b/drivers/net/ipvlan/ipvlan_core.c @@ -418,7 +418,7 @@ static struct ipvl_addr *ipvlan_addr_lookup(struct ipvl_port *port, return addr; } -static int ipvlan_process_v4_outbound(struct sk_buff *skb) +static noinline_for_stack int ipvlan_process_v4_outbound(struct sk_buff *skb) { const struct iphdr *ip4h = ip_hdr(skb); struct net_device *dev = skb->dev; @@ -443,6 +443,9 @@ static int ipvlan_process_v4_outbound(struct sk_buff *skb) goto err; } skb_dst_set(skb, &rt->dst); + + memset(IPCB(skb), 0, sizeof(*IPCB(skb))); + err = ip_local_out(net, skb->sk, skb); if (unlikely(net_xmit_eval(err))) dev->stats.tx_errors++; @@ -457,13 +460,11 @@ static int ipvlan_process_v4_outbound(struct sk_buff *skb) } #if IS_ENABLED(CONFIG_IPV6) -static int ipvlan_process_v6_outbound(struct sk_buff *skb) + +static noinline_for_stack int +ipvlan_route_v6_outbound(struct net_device *dev, struct sk_buff *skb) { const struct ipv6hdr *ip6h = ipv6_hdr(skb); - struct net_device *dev = skb->dev; - struct net *net = dev_net(dev); - struct dst_entry *dst; - int err, ret = NET_XMIT_DROP; struct flowi6 fl6 = { .flowi6_oif = dev->ifindex, .daddr = ip6h->daddr, @@ -473,24 +474,38 @@ static int ipvlan_process_v6_outbound(struct sk_buff *skb) .flowi6_mark = skb->mark, .flowi6_proto = ip6h->nexthdr, }; + struct dst_entry *dst; + int err; - dst = ip6_route_output(net, NULL, &fl6); - if (dst->error) { - ret = dst->error; + dst = ip6_route_output(dev_net(dev), NULL, &fl6); + err = dst->error; + if (err) { dst_release(dst); - goto err; + return err; } skb_dst_set(skb, dst); - err = ip6_local_out(net, skb->sk, skb); + return 0; +} + +static int ipvlan_process_v6_outbound(struct sk_buff *skb) +{ + struct net_device *dev = skb->dev; + int err, ret = NET_XMIT_DROP; + + err = ipvlan_route_v6_outbound(dev, skb); + if (unlikely(err)) { + dev->stats.tx_errors++; + kfree_skb(skb); + return err; + } + + memset(IP6CB(skb), 0, sizeof(*IP6CB(skb))); + + err = ip6_local_out(dev_net(dev), skb->sk, skb); if (unlikely(net_xmit_eval(err))) dev->stats.tx_errors++; else ret = NET_XMIT_SUCCESS; - goto out; -err: - dev->stats.tx_errors++; - kfree_skb(skb); -out: return ret; } #else @@ -586,7 +601,8 @@ static int ipvlan_xmit_mode_l3(struct sk_buff *skb, struct net_device *dev) consume_skb(skb); return NET_XMIT_DROP; } - return ipvlan_rcv_frame(addr, &skb, true); + ipvlan_rcv_frame(addr, &skb, true); + return NET_XMIT_SUCCESS; } } out: @@ -612,7 +628,8 @@ static int ipvlan_xmit_mode_l2(struct sk_buff *skb, struct net_device *dev) consume_skb(skb); return NET_XMIT_DROP; } - return ipvlan_rcv_frame(addr, &skb, true); + ipvlan_rcv_frame(addr, &skb, true); + return NET_XMIT_SUCCESS; } } skb = skb_share_check(skb, GFP_ATOMIC); @@ -624,7 +641,8 @@ static int ipvlan_xmit_mode_l2(struct sk_buff *skb, struct net_device *dev) * the skb for the main-dev. At the RX side we just return * RX_PASS for it to be processed further on the stack. */ - return dev_forward_skb(ipvlan->phy_dev, skb); + dev_forward_skb(ipvlan->phy_dev, skb); + return NET_XMIT_SUCCESS; } else if (is_multicast_ether_addr(eth->h_dest)) { skb_reset_mac_header(skb); diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c index 6c0f80bea81614e73216f9eb8897a65bdffd0c32..73b1be3450f14906ebd1bd7946a193f446c404f0 100644 --- a/drivers/net/macsec.c +++ b/drivers/net/macsec.c @@ -322,6 +322,19 @@ static struct macsec_rx_sa *macsec_rxsa_get(struct macsec_rx_sa __rcu *ptr) return sa; } +static struct macsec_rx_sa *macsec_active_rxsa_get(struct macsec_rx_sc *rx_sc) +{ + struct macsec_rx_sa *sa = NULL; + int an; + + for (an = 0; an < MACSEC_NUM_AN; an++) { + sa = macsec_rxsa_get(rx_sc->sa[an]); + if (sa) + break; + } + return sa; +} + static void free_rx_sc_rcu(struct rcu_head *head) { struct macsec_rx_sc *rx_sc = container_of(head, struct macsec_rx_sc, rcu_head); @@ -566,18 +579,28 @@ static void macsec_encrypt_finish(struct sk_buff *skb, struct net_device *dev) skb->protocol = eth_hdr(skb)->h_proto; } +static unsigned int macsec_msdu_len(struct sk_buff *skb) +{ + struct macsec_dev *macsec = macsec_priv(skb->dev); + struct macsec_secy *secy = &macsec->secy; + bool sci_present = macsec_skb_cb(skb)->has_sci; + + return skb->len - macsec_hdr_len(sci_present) - secy->icv_len; +} + static void macsec_count_tx(struct sk_buff *skb, struct macsec_tx_sc *tx_sc, struct macsec_tx_sa *tx_sa) { + unsigned int msdu_len = macsec_msdu_len(skb); struct pcpu_tx_sc_stats *txsc_stats = this_cpu_ptr(tx_sc->stats); u64_stats_update_begin(&txsc_stats->syncp); if (tx_sc->encrypt) { - txsc_stats->stats.OutOctetsEncrypted += skb->len; + txsc_stats->stats.OutOctetsEncrypted += msdu_len; txsc_stats->stats.OutPktsEncrypted++; this_cpu_inc(tx_sa->stats->OutPktsEncrypted); } else { - txsc_stats->stats.OutOctetsProtected += skb->len; + txsc_stats->stats.OutOctetsProtected += msdu_len; txsc_stats->stats.OutPktsProtected++; this_cpu_inc(tx_sa->stats->OutPktsProtected); } @@ -607,9 +630,10 @@ static void macsec_encrypt_done(struct crypto_async_request *base, int err) aead_request_free(macsec_skb_cb(skb)->req); rcu_read_lock_bh(); - macsec_encrypt_finish(skb, dev); macsec_count_tx(skb, &macsec->secy.tx_sc, macsec_skb_cb(skb)->tx_sa); - len = skb->len; + /* packet is encrypted/protected so tx_bytes must be calculated */ + len = macsec_msdu_len(skb) + 2 * ETH_ALEN; + macsec_encrypt_finish(skb, dev); ret = dev_queue_xmit(skb); count_tx(dev, ret, len); rcu_read_unlock_bh(); @@ -765,6 +789,7 @@ static struct sk_buff *macsec_encrypt(struct sk_buff *skb, macsec_skb_cb(skb)->req = req; macsec_skb_cb(skb)->tx_sa = tx_sa; + macsec_skb_cb(skb)->has_sci = sci_present; aead_request_set_callback(req, 0, macsec_encrypt_done, skb); dev_hold(skb->dev); @@ -805,15 +830,17 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsLate++; u64_stats_update_end(&rxsc_stats->syncp); + secy->netdev->stats.rx_dropped++; return false; } if (secy->validate_frames != MACSEC_VALIDATE_DISABLED) { + unsigned int msdu_len = macsec_msdu_len(skb); u64_stats_update_begin(&rxsc_stats->syncp); if (hdr->tci_an & MACSEC_TCI_E) - rxsc_stats->stats.InOctetsDecrypted += skb->len; + rxsc_stats->stats.InOctetsDecrypted += msdu_len; else - rxsc_stats->stats.InOctetsValidated += skb->len; + rxsc_stats->stats.InOctetsValidated += msdu_len; u64_stats_update_end(&rxsc_stats->syncp); } @@ -826,6 +853,8 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsNotValid++; u64_stats_update_end(&rxsc_stats->syncp); + this_cpu_inc(rx_sa->stats->InPktsNotValid); + secy->netdev->stats.rx_errors++; return false; } @@ -911,9 +940,9 @@ static void macsec_decrypt_done(struct crypto_async_request *base, int err) macsec_finalize_skb(skb, macsec->secy.icv_len, macsec_extra_len(macsec_skb_cb(skb)->has_sci)); + len = skb->len; macsec_reset_skb(skb, macsec->secy.netdev); - len = skb->len; if (gro_cells_receive(&macsec->gro_cells, skb) == NET_RX_SUCCESS) count_rx(dev, len); @@ -1055,6 +1084,7 @@ static void handle_not_macsec(struct sk_buff *skb) u64_stats_update_begin(&secy_stats->syncp); secy_stats->stats.InPktsNoTag++; u64_stats_update_end(&secy_stats->syncp); + macsec->secy.netdev->stats.rx_dropped++; continue; } @@ -1165,6 +1195,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&secy_stats->syncp); secy_stats->stats.InPktsBadTag++; u64_stats_update_end(&secy_stats->syncp); + secy->netdev->stats.rx_errors++; goto drop_nosa; } @@ -1175,11 +1206,15 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) /* If validateFrames is Strict or the C bit in the * SecTAG is set, discard */ + struct macsec_rx_sa *active_rx_sa = macsec_active_rxsa_get(rx_sc); if (hdr->tci_an & MACSEC_TCI_C || secy->validate_frames == MACSEC_VALIDATE_STRICT) { u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsNotUsingSA++; u64_stats_update_end(&rxsc_stats->syncp); + secy->netdev->stats.rx_errors++; + if (active_rx_sa) + this_cpu_inc(active_rx_sa->stats->InPktsNotUsingSA); goto drop_nosa; } @@ -1189,6 +1224,8 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsUnusedSA++; u64_stats_update_end(&rxsc_stats->syncp); + if (active_rx_sa) + this_cpu_inc(active_rx_sa->stats->InPktsUnusedSA); goto deliver; } @@ -1206,6 +1243,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsLate++; u64_stats_update_end(&rxsc_stats->syncp); + macsec->secy.netdev->stats.rx_dropped++; goto drop; } } @@ -1234,6 +1272,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) deliver: macsec_finalize_skb(skb, secy->icv_len, macsec_extra_len(macsec_skb_cb(skb)->has_sci)); + len = skb->len; macsec_reset_skb(skb, secy->netdev); if (rx_sa) @@ -1241,7 +1280,6 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) macsec_rxsc_put(rx_sc); skb_orphan(skb); - len = skb->len; ret = gro_cells_receive(&macsec->gro_cells, skb); if (ret == NET_RX_SUCCESS) count_rx(dev, len); @@ -1283,6 +1321,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&secy_stats->syncp); secy_stats->stats.InPktsNoSCI++; u64_stats_update_end(&secy_stats->syncp); + macsec->secy.netdev->stats.rx_errors++; continue; } @@ -1315,8 +1354,7 @@ static struct crypto_aead *macsec_alloc_tfm(char *key, int key_len, int icv_len) struct crypto_aead *tfm; int ret; - /* Pick a sync gcm(aes) cipher to ensure order is preserved. */ - tfm = crypto_alloc_aead("gcm(aes)", 0, CRYPTO_ALG_ASYNC); + tfm = crypto_alloc_aead("gcm(aes)", 0, 0); if (IS_ERR(tfm)) return tfm; @@ -2738,6 +2776,7 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb, return NETDEV_TX_OK; } + len = skb->len; skb = macsec_encrypt(skb, dev); if (IS_ERR(skb)) { if (PTR_ERR(skb) != -EINPROGRESS) @@ -2748,7 +2787,6 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb, macsec_count_tx(skb, &macsec->secy.tx_sc, macsec_skb_cb(skb)->tx_sa); macsec_encrypt_finish(skb, dev); - len = skb->len; ret = dev_queue_xmit(skb); count_tx(dev, ret, len); return ret; @@ -2963,6 +3001,7 @@ static void macsec_get_stats64(struct net_device *dev, s->rx_dropped = dev->stats.rx_dropped; s->tx_dropped = dev->stats.tx_dropped; + s->rx_errors = dev->stats.rx_errors; } static int macsec_get_iflink(const struct net_device *dev) diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c index e1f95fd08d7213f3490214c8583ce9c9ef526530..29d5fd46c09a07d15db44bb2308a5f65b514a019 100644 --- a/drivers/net/macvlan.c +++ b/drivers/net/macvlan.c @@ -769,7 +769,7 @@ static void macvlan_change_rx_flags(struct net_device *dev, int change) if (dev->flags & IFF_UP) { if (change & IFF_ALLMULTI) dev_set_allmulti(lowerdev, dev->flags & IFF_ALLMULTI ? 1 : -1); - if (change & IFF_PROMISC) + if (!macvlan_passthru(vlan->port) && change & IFF_PROMISC) dev_set_promiscuity(lowerdev, dev->flags & IFF_PROMISC ? 1 : -1); diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index 94622d119abcea5b493393becb1b94a56ccc3778..49fb62d02a76d7efd861a8a7188b2232687fd45a 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -421,6 +421,17 @@ static int bcm5482_read_status(struct phy_device *phydev) return err; } +static int bcm54810_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) +{ + return -EOPNOTSUPP; +} + +static int bcm54810_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, + u16 val) +{ + return -EOPNOTSUPP; +} + static int bcm5481_config_aneg(struct phy_device *phydev) { struct device_node *np = phydev->mdio.dev.of_node; @@ -684,6 +695,8 @@ static struct phy_driver broadcom_drivers[] = { .name = "Broadcom BCM54810", .features = PHY_GBIT_FEATURES, .flags = PHY_HAS_INTERRUPT, + .read_mmd = bcm54810_read_mmd, + .write_mmd = bcm54810_write_mmd, .config_init = bcm54xx_config_init, .config_aneg = bcm5481_config_aneg, .ack_interrupt = bcm_phy_ack_intr, diff --git a/drivers/net/phy/mdio-thunder.c b/drivers/net/phy/mdio-thunder.c index c0c922eff760c0225da62446a7b10e15722ab580..959bf342133a7021727377ad3b74df5fd093b3c8 100644 --- a/drivers/net/phy/mdio-thunder.c +++ b/drivers/net/phy/mdio-thunder.c @@ -107,6 +107,7 @@ static int thunder_mdiobus_pci_probe(struct pci_dev *pdev, if (i >= ARRAY_SIZE(nexus->buses)) break; } + fwnode_handle_put(fwn); return 0; err_release_regions: diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c index c328208388da7eafda9bf87219469bf75733fce4..fd7c9f5ff99eb22e15a100233abf67ffd01b0d2e 100644 --- a/drivers/net/phy/smsc.c +++ b/drivers/net/phy/smsc.c @@ -112,8 +112,11 @@ static int lan911x_config_init(struct phy_device *phydev) static int lan87xx_read_status(struct phy_device *phydev) { struct smsc_phy_priv *priv = phydev->priv; + int err; - int err = genphy_read_status(phydev); + err = genphy_read_status(phydev); + if (err) + return err; if (!phydev->link && priv->energy_enable) { int i; diff --git a/drivers/net/ppp/ppp_synctty.c b/drivers/net/ppp/ppp_synctty.c index d02ba2494d9371096abb072e2dbd6e47007dc15d..5758c0ed9a9675c6a3d9f933f43517ff860b2b08 100644 --- a/drivers/net/ppp/ppp_synctty.c +++ b/drivers/net/ppp/ppp_synctty.c @@ -467,6 +467,10 @@ ppp_sync_ioctl(struct ppp_channel *chan, unsigned int cmd, unsigned long arg) case PPPIOCSMRU: if (get_user(val, (int __user *) argp)) break; + if (val > U16_MAX) { + err = -EINVAL; + break; + } if (val < PPP_MRU) val = PPP_MRU; ap->mru = val; @@ -702,7 +706,7 @@ ppp_sync_input(struct syncppp *ap, const unsigned char *buf, /* strip address/control field if present */ p = skb->data; - if (p[0] == PPP_ALLSTATIONS && p[1] == PPP_UI) { + if (skb->len >= 2 && p[0] == PPP_ALLSTATIONS && p[1] == PPP_UI) { /* chop off address/control */ if (skb->len < 3) goto err; diff --git a/drivers/net/tap.c b/drivers/net/tap.c index f0f7cd9776671fb6d3f3dd6498611afe593b41c3..43012a195b71ca914347558e939721ec3ded3b43 100644 --- a/drivers/net/tap.c +++ b/drivers/net/tap.c @@ -525,7 +525,7 @@ static int tap_open(struct inode *inode, struct file *file) q->sock.state = SS_CONNECTED; q->sock.file = file; q->sock.ops = &tap_socket_ops; - sock_init_data(&q->sock, &q->sk); + sock_init_data_uid(&q->sock, &q->sk, inode->i_uid); q->sk.sk_write_space = tap_sock_write_space; q->sk.sk_destruct = tap_sock_destruct; q->flags = IFF_VNET_HDR | IFF_NO_PI | IFF_TAP; diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c index 2410f08e2bb5cdb42ed73cfa3c6ad18adf83a5fc..08f9530fd5b1573cb92ec75e32391a2133a0eddc 100644 --- a/drivers/net/team/team.c +++ b/drivers/net/team/team.c @@ -2095,7 +2095,12 @@ static const struct ethtool_ops team_ethtool_ops = { static void team_setup_by_port(struct net_device *dev, struct net_device *port_dev) { - dev->header_ops = port_dev->header_ops; + struct team *team = netdev_priv(dev); + + if (port_dev->type == ARPHRD_ETHER) + dev->header_ops = team->header_ops_cache; + else + dev->header_ops = port_dev->header_ops; dev->type = port_dev->type; dev->hard_header_len = port_dev->hard_header_len; dev->needed_headroom = port_dev->needed_headroom; @@ -2103,6 +2108,15 @@ static void team_setup_by_port(struct net_device *dev, dev->mtu = port_dev->mtu; memcpy(dev->broadcast, port_dev->broadcast, port_dev->addr_len); eth_hw_addr_inherit(dev, port_dev); + + if (port_dev->flags & IFF_POINTOPOINT) { + dev->flags &= ~(IFF_BROADCAST | IFF_MULTICAST); + dev->flags |= (IFF_POINTOPOINT | IFF_NOARP); + } else if ((port_dev->flags & (IFF_BROADCAST | IFF_MULTICAST)) == + (IFF_BROADCAST | IFF_MULTICAST)) { + dev->flags |= (IFF_BROADCAST | IFF_MULTICAST); + dev->flags &= ~(IFF_POINTOPOINT | IFF_NOARP); + } } static int team_dev_type_check_change(struct net_device *dev, @@ -2133,8 +2147,11 @@ static int team_dev_type_check_change(struct net_device *dev, static void team_setup(struct net_device *dev) { + struct team *team = netdev_priv(dev); + ether_setup(dev); dev->max_mtu = ETH_MAX_MTU; + team->header_ops_cache = dev->header_ops; dev->netdev_ops = &team_netdev_ops; dev->ethtool_ops = &team_ethtool_ops; @@ -2159,7 +2176,9 @@ static void team_setup(struct net_device *dev) dev->hw_features = TEAM_VLAN_FEATURES | NETIF_F_HW_VLAN_CTAG_RX | - NETIF_F_HW_VLAN_CTAG_FILTER; + NETIF_F_HW_VLAN_CTAG_FILTER | + NETIF_F_HW_VLAN_STAG_RX | + NETIF_F_HW_VLAN_STAG_FILTER; dev->hw_features |= NETIF_F_GSO_ENCAP_ALL | NETIF_F_GSO_UDP_L4; dev->features |= dev->hw_features; diff --git a/drivers/net/thunderbolt.c b/drivers/net/thunderbolt.c index 51b5442fbc668eef0cdbe1a0b35dc71c65eb336c..e0b4c54e6c08f6f3c48da69cbe53307266e2efd4 100644 --- a/drivers/net/thunderbolt.c +++ b/drivers/net/thunderbolt.c @@ -961,12 +961,11 @@ static bool tbnet_xmit_csum_and_map(struct tbnet *net, struct sk_buff *skb, *tucso = ~csum_tcpudp_magic(ip_hdr(skb)->saddr, ip_hdr(skb)->daddr, 0, ip_hdr(skb)->protocol, 0); - } else if (skb_is_gso_v6(skb)) { + } else if (skb_is_gso(skb) && skb_is_gso_v6(skb)) { tucso = dest + ((void *)&(tcp_hdr(skb)->check) - data); *tucso = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); - return false; } else if (protocol == htons(ETH_P_IPV6)) { tucso = dest + skb_checksum_start_offset(skb) + skb->csum_offset; *tucso = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, diff --git a/drivers/net/tun.c b/drivers/net/tun.c index 346bd687067b7ab9a2b7a261ce63e4214eb454ab..b47b5189f9581c0c2be0a6dc52eb597f3dd1367a 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -256,6 +256,9 @@ struct tun_struct { struct tun_prog __rcu *steering_prog; struct tun_prog __rcu *filter_prog; struct ethtool_link_ksettings link_ksettings; + /* init args */ + struct file *file; + struct ifreq *ifr; }; struct veth { @@ -281,6 +284,9 @@ void *tun_ptr_to_xdp(void *ptr) } EXPORT_SYMBOL(tun_ptr_to_xdp); +static void tun_flow_init(struct tun_struct *tun); +static void tun_flow_uninit(struct tun_struct *tun); + static int tun_napi_receive(struct napi_struct *napi, int budget) { struct tun_file *tfile = container_of(napi, struct tun_file, napi); @@ -1038,6 +1044,49 @@ static int check_filter(struct tap_filter *filter, const struct sk_buff *skb) static const struct ethtool_ops tun_ethtool_ops; +static int tun_net_init(struct net_device *dev) +{ + struct tun_struct *tun = netdev_priv(dev); + struct ifreq *ifr = tun->ifr; + int err; + + tun->pcpu_stats = netdev_alloc_pcpu_stats(struct tun_pcpu_stats); + if (!tun->pcpu_stats) + return -ENOMEM; + + spin_lock_init(&tun->lock); + + err = security_tun_dev_alloc_security(&tun->security); + if (err < 0) { + free_percpu(tun->pcpu_stats); + return err; + } + + tun_flow_init(tun); + + dev->hw_features = NETIF_F_SG | NETIF_F_FRAGLIST | + TUN_USER_FEATURES | NETIF_F_HW_VLAN_CTAG_TX | + NETIF_F_HW_VLAN_STAG_TX; + dev->features = dev->hw_features | NETIF_F_LLTX; + dev->vlan_features = dev->features & + ~(NETIF_F_HW_VLAN_CTAG_TX | + NETIF_F_HW_VLAN_STAG_TX); + + tun->flags = (tun->flags & ~TUN_FEATURES) | + (ifr->ifr_flags & TUN_FEATURES); + + INIT_LIST_HEAD(&tun->disabled); + err = tun_attach(tun, tun->file, false, ifr->ifr_flags & IFF_NAPI, + ifr->ifr_flags & IFF_NAPI_FRAGS, false); + if (err < 0) { + tun_flow_uninit(tun); + security_tun_dev_free_security(tun->security); + free_percpu(tun->pcpu_stats); + return err; + } + return 0; +} + /* Net device detach from fd. */ static void tun_net_uninit(struct net_device *dev) { @@ -1268,6 +1317,7 @@ static int tun_xdp(struct net_device *dev, struct netdev_bpf *xdp) } static const struct net_device_ops tun_netdev_ops = { + .ndo_init = tun_net_init, .ndo_uninit = tun_net_uninit, .ndo_open = tun_net_open, .ndo_stop = tun_net_close, @@ -1347,6 +1397,7 @@ static int tun_xdp_tx(struct net_device *dev, struct xdp_buff *xdp) } static const struct net_device_ops tap_netdev_ops = { + .ndo_init = tun_net_init, .ndo_uninit = tun_net_uninit, .ndo_open = tun_net_open, .ndo_stop = tun_net_close, @@ -1386,7 +1437,7 @@ static void tun_flow_uninit(struct tun_struct *tun) #define MAX_MTU 65535 /* Initialize net device. */ -static void tun_net_init(struct net_device *dev) +static void tun_net_initialize(struct net_device *dev) { struct tun_struct *tun = netdev_priv(dev); @@ -1603,7 +1654,7 @@ static bool tun_can_build_skb(struct tun_struct *tun, struct tun_file *tfile, if (zerocopy) return false; - if (SKB_DATA_ALIGN(len + TUN_RX_PAD) + + if (SKB_DATA_ALIGN(len + TUN_RX_PAD + XDP_PACKET_HEADROOM) + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) > PAGE_SIZE) return false; @@ -2662,9 +2713,6 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr) if (!dev) return -ENOMEM; - err = dev_get_valid_name(net, dev, name); - if (err < 0) - goto err_free_dev; dev_net_set(dev, net); dev->rtnl_link_ops = &tun_link_ops; @@ -2683,41 +2731,16 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr) tun->rx_batched = 0; RCU_INIT_POINTER(tun->steering_prog, NULL); - tun->pcpu_stats = netdev_alloc_pcpu_stats(struct tun_pcpu_stats); - if (!tun->pcpu_stats) { - err = -ENOMEM; - goto err_free_dev; - } - - spin_lock_init(&tun->lock); - - err = security_tun_dev_alloc_security(&tun->security); - if (err < 0) - goto err_free_stat; - - tun_net_init(dev); - tun_flow_init(tun); - - dev->hw_features = NETIF_F_SG | NETIF_F_FRAGLIST | - TUN_USER_FEATURES | NETIF_F_HW_VLAN_CTAG_TX | - NETIF_F_HW_VLAN_STAG_TX; - dev->features = dev->hw_features | NETIF_F_LLTX; - dev->vlan_features = dev->features & - ~(NETIF_F_HW_VLAN_CTAG_TX | - NETIF_F_HW_VLAN_STAG_TX); + tun->ifr = ifr; + tun->file = file; - tun->flags = (tun->flags & ~TUN_FEATURES) | - (ifr->ifr_flags & TUN_FEATURES); - - INIT_LIST_HEAD(&tun->disabled); - err = tun_attach(tun, file, false, ifr->ifr_flags & IFF_NAPI, - ifr->ifr_flags & IFF_NAPI_FRAGS, false); - if (err < 0) - goto err_free_flow; + tun_net_initialize(dev); err = register_netdevice(tun->dev); - if (err < 0) - goto err_detach; + if (err < 0) { + free_netdev(dev); + return err; + } /* free_netdev() won't check refcnt, to aovid race * with dev_put() we need publish tun after registration. */ @@ -2736,20 +2759,6 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr) strcpy(ifr->ifr_name, tun->dev->name); return 0; - -err_detach: - tun_detach_all(dev); - /* register_netdevice() already called tun_free_netdev() */ - goto err_free_dev; - -err_free_flow: - tun_flow_uninit(tun); - security_tun_dev_free_security(tun->security); -err_free_stat: - free_percpu(tun->pcpu_stats); -err_free_dev: - free_netdev(dev); - return err; } static void tun_get_iff(struct net *net, struct tun_struct *tun, @@ -3340,7 +3349,7 @@ static int tun_chr_open(struct inode *inode, struct file * file) tfile->socket.file = file; tfile->socket.ops = &tun_socket_ops; - sock_init_data(&tfile->socket, &tfile->sk); + sock_init_data_uid(&tfile->socket, &tfile->sk, inode->i_uid); tfile->sk.sk_write_space = tun_sock_write_space; tfile->sk.sk_sndbuf = INT_MAX; diff --git a/drivers/net/usb/cdc_ether.c b/drivers/net/usb/cdc_ether.c index 17b932505be0cfc068fb391639e840ac3b5faf5d..e2ce3c5541baa396a7791d6bff69cd49d0b586cc 100644 --- a/drivers/net/usb/cdc_ether.c +++ b/drivers/net/usb/cdc_ether.c @@ -618,9 +618,23 @@ static const struct usb_device_id products[] = { .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | USB_DEVICE_ID_MATCH_DEVICE, .idVendor = 0x04DD, + .idProduct = 0x8005, /* A-300 */ + ZAURUS_FAKE_INTERFACE, + .driver_info = 0, +}, { + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO + | USB_DEVICE_ID_MATCH_DEVICE, + .idVendor = 0x04DD, .idProduct = 0x8006, /* B-500/SL-5600 */ ZAURUS_MASTER_INTERFACE, .driver_info = 0, +}, { + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO + | USB_DEVICE_ID_MATCH_DEVICE, + .idVendor = 0x04DD, + .idProduct = 0x8006, /* B-500/SL-5600 */ + ZAURUS_FAKE_INTERFACE, + .driver_info = 0, }, { .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | USB_DEVICE_ID_MATCH_DEVICE, @@ -628,6 +642,13 @@ static const struct usb_device_id products[] = { .idProduct = 0x8007, /* C-700 */ ZAURUS_MASTER_INTERFACE, .driver_info = 0, +}, { + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO + | USB_DEVICE_ID_MATCH_DEVICE, + .idVendor = 0x04DD, + .idProduct = 0x8007, /* C-700 */ + ZAURUS_FAKE_INTERFACE, + .driver_info = 0, }, { .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | USB_DEVICE_ID_MATCH_DEVICE, diff --git a/drivers/net/usb/cdc_mbim.c b/drivers/net/usb/cdc_mbim.c index 41bac861ca99d46e3c7241834553ebc8cef61b8d..72a93dc2df8687c06d828d0b55072c69d8784cf0 100644 --- a/drivers/net/usb/cdc_mbim.c +++ b/drivers/net/usb/cdc_mbim.c @@ -665,6 +665,11 @@ static const struct usb_device_id mbim_devs[] = { .driver_info = (unsigned long)&cdc_mbim_info_avoid_altsetting_toggle, }, + /* Telit FE990 */ + { USB_DEVICE_AND_INTERFACE_INFO(0x1bc7, 0x1081, USB_CLASS_COMM, USB_CDC_SUBCLASS_MBIM, USB_CDC_PROTO_NONE), + .driver_info = (unsigned long)&cdc_mbim_info_avoid_altsetting_toggle, + }, + /* default entry */ { USB_INTERFACE_INFO(USB_CLASS_COMM, USB_CDC_SUBCLASS_MBIM, USB_CDC_PROTO_NONE), .driver_info = (unsigned long)&cdc_mbim_info_zlp, diff --git a/drivers/net/usb/cdc_ncm.c b/drivers/net/usb/cdc_ncm.c index 0e1306ded31ea769651fe911a264d4b2d77c3fee..65dac36d8d4ffebab0c24e5a8d18771bbeab7429 100644 --- a/drivers/net/usb/cdc_ncm.c +++ b/drivers/net/usb/cdc_ncm.c @@ -175,10 +175,17 @@ static u32 cdc_ncm_check_tx_max(struct usbnet *dev, u32 new_tx) u32 val, max, min; /* clamp new_tx to sane values */ - min = ctx->max_datagram_size + ctx->max_ndp_size + sizeof(struct usb_cdc_ncm_nth16); - max = min_t(u32, CDC_NCM_NTB_MAX_SIZE_TX, le32_to_cpu(ctx->ncm_parm.dwNtbOutMaxSize)); - if (max == 0) + if (ctx->is_ndp16) + min = ctx->max_datagram_size + ctx->max_ndp_size + sizeof(struct usb_cdc_ncm_nth16); + else + min = ctx->max_datagram_size + ctx->max_ndp_size + sizeof(struct usb_cdc_ncm_nth32); + + if (le32_to_cpu(ctx->ncm_parm.dwNtbOutMaxSize) == 0) max = CDC_NCM_NTB_MAX_SIZE_TX; /* dwNtbOutMaxSize not set */ + else + max = clamp_t(u32, le32_to_cpu(ctx->ncm_parm.dwNtbOutMaxSize), + USB_CDC_NCM_NTB_MIN_OUT_SIZE, + CDC_NCM_NTB_MAX_SIZE_TX); /* some devices set dwNtbOutMaxSize too low for the above default */ min = min(min, max); @@ -309,10 +316,17 @@ static ssize_t ndp_to_end_store(struct device *d, struct device_attribute *attr if (enable == (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) return len; - if (enable && !ctx->delayed_ndp16) { - ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); - if (!ctx->delayed_ndp16) - return -ENOMEM; + if (enable) { + if (ctx->is_ndp16 && !ctx->delayed_ndp16) { + ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); + if (!ctx->delayed_ndp16) + return -ENOMEM; + } + if (!ctx->is_ndp16 && !ctx->delayed_ndp32) { + ctx->delayed_ndp32 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); + if (!ctx->delayed_ndp32) + return -ENOMEM; + } } /* flush pending data before changing flag */ @@ -514,6 +528,9 @@ static int cdc_ncm_init(struct usbnet *dev) dev_err(&dev->intf->dev, "SET_CRC_MODE failed\n"); } + /* use ndp16 by default */ + ctx->is_ndp16 = 1; + /* set NTB format, if both formats are supported. * * "The host shall only send this command while the NCM Data @@ -521,14 +538,27 @@ static int cdc_ncm_init(struct usbnet *dev) */ if (le16_to_cpu(ctx->ncm_parm.bmNtbFormatsSupported) & USB_CDC_NCM_NTB32_SUPPORTED) { - dev_dbg(&dev->intf->dev, "Setting NTB format to 16-bit\n"); - err = usbnet_write_cmd(dev, USB_CDC_SET_NTB_FORMAT, - USB_TYPE_CLASS | USB_DIR_OUT - | USB_RECIP_INTERFACE, - USB_CDC_NCM_NTB16_FORMAT, - iface_no, NULL, 0); - if (err < 0) + if (ctx->drvflags & CDC_NCM_FLAG_PREFER_NTB32) { + ctx->is_ndp16 = 0; + dev_dbg(&dev->intf->dev, "Setting NTB format to 32-bit\n"); + err = usbnet_write_cmd(dev, USB_CDC_SET_NTB_FORMAT, + USB_TYPE_CLASS | USB_DIR_OUT + | USB_RECIP_INTERFACE, + USB_CDC_NCM_NTB32_FORMAT, + iface_no, NULL, 0); + } else { + ctx->is_ndp16 = 1; + dev_dbg(&dev->intf->dev, "Setting NTB format to 16-bit\n"); + err = usbnet_write_cmd(dev, USB_CDC_SET_NTB_FORMAT, + USB_TYPE_CLASS | USB_DIR_OUT + | USB_RECIP_INTERFACE, + USB_CDC_NCM_NTB16_FORMAT, + iface_no, NULL, 0); + } + if (err < 0) { + ctx->is_ndp16 = 1; dev_err(&dev->intf->dev, "SET_NTB_FORMAT failed\n"); + } } /* set initial device values */ @@ -551,7 +581,10 @@ static int cdc_ncm_init(struct usbnet *dev) ctx->tx_max_datagrams = CDC_NCM_DPT_DATAGRAMS_MAX; /* set up maximum NDP size */ - ctx->max_ndp_size = sizeof(struct usb_cdc_ncm_ndp16) + (ctx->tx_max_datagrams + 1) * sizeof(struct usb_cdc_ncm_dpe16); + if (ctx->is_ndp16) + ctx->max_ndp_size = sizeof(struct usb_cdc_ncm_ndp16) + (ctx->tx_max_datagrams + 1) * sizeof(struct usb_cdc_ncm_dpe16); + else + ctx->max_ndp_size = sizeof(struct usb_cdc_ncm_ndp32) + (ctx->tx_max_datagrams + 1) * sizeof(struct usb_cdc_ncm_dpe32); /* initial coalescing timer interval */ ctx->timer_interval = CDC_NCM_TIMER_INTERVAL_USEC * NSEC_PER_USEC; @@ -736,7 +769,10 @@ static void cdc_ncm_free(struct cdc_ncm_ctx *ctx) ctx->tx_curr_skb = NULL; } - kfree(ctx->delayed_ndp16); + if (ctx->is_ndp16) + kfree(ctx->delayed_ndp16); + else + kfree(ctx->delayed_ndp32); kfree(ctx); } @@ -774,10 +810,8 @@ int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_ u8 *buf; int len; int temp; - int err; u8 iface_no; struct usb_cdc_parsed_header hdr; - __le16 curr_ntb_format; ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); if (!ctx) @@ -882,32 +916,6 @@ int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_ goto error2; } - /* - * Some Huawei devices have been observed to come out of reset in NDP32 mode. - * Let's check if this is the case, and set the device to NDP16 mode again if - * needed. - */ - if (ctx->drvflags & CDC_NCM_FLAG_RESET_NTB16) { - err = usbnet_read_cmd(dev, USB_CDC_GET_NTB_FORMAT, - USB_TYPE_CLASS | USB_DIR_IN | USB_RECIP_INTERFACE, - 0, iface_no, &curr_ntb_format, 2); - if (err < 0) { - goto error2; - } - - if (curr_ntb_format == cpu_to_le16(USB_CDC_NCM_NTB32_FORMAT)) { - dev_info(&intf->dev, "resetting NTB format to 16-bit"); - err = usbnet_write_cmd(dev, USB_CDC_SET_NTB_FORMAT, - USB_TYPE_CLASS | USB_DIR_OUT - | USB_RECIP_INTERFACE, - USB_CDC_NCM_NTB16_FORMAT, - iface_no, NULL, 0); - - if (err < 0) - goto error2; - } - } - cdc_ncm_find_endpoints(dev, ctx->data); cdc_ncm_find_endpoints(dev, ctx->control); if (!dev->in || !dev->out || !dev->status) { @@ -932,9 +940,15 @@ int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_ /* Allocate the delayed NDP if needed. */ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { - ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); - if (!ctx->delayed_ndp16) - goto error2; + if (ctx->is_ndp16) { + ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); + if (!ctx->delayed_ndp16) + goto error2; + } else { + ctx->delayed_ndp32 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); + if (!ctx->delayed_ndp32) + goto error2; + } dev_info(&intf->dev, "NDP will be placed at end of frame for this device."); } @@ -1058,7 +1072,7 @@ static void cdc_ncm_align_tail(struct sk_buff *skb, size_t modulus, size_t remai /* return a pointer to a valid struct usb_cdc_ncm_ndp16 of type sign, possibly * allocating a new one within skb */ -static struct usb_cdc_ncm_ndp16 *cdc_ncm_ndp(struct cdc_ncm_ctx *ctx, struct sk_buff *skb, __le32 sign, size_t reserve) +static struct usb_cdc_ncm_ndp16 *cdc_ncm_ndp16(struct cdc_ncm_ctx *ctx, struct sk_buff *skb, __le32 sign, size_t reserve) { struct usb_cdc_ncm_ndp16 *ndp16 = NULL; struct usb_cdc_ncm_nth16 *nth16 = (void *)skb->data; @@ -1113,12 +1127,73 @@ static struct usb_cdc_ncm_ndp16 *cdc_ncm_ndp(struct cdc_ncm_ctx *ctx, struct sk_ return ndp16; } +static struct usb_cdc_ncm_ndp32 *cdc_ncm_ndp32(struct cdc_ncm_ctx *ctx, struct sk_buff *skb, __le32 sign, size_t reserve) +{ + struct usb_cdc_ncm_ndp32 *ndp32 = NULL; + struct usb_cdc_ncm_nth32 *nth32 = (void *)skb->data; + size_t ndpoffset = le32_to_cpu(nth32->dwNdpIndex); + + /* If NDP should be moved to the end of the NCM package, we can't follow the + * NTH32 header as we would normally do. NDP isn't written to the SKB yet, and + * the wNdpIndex field in the header is actually not consistent with reality. It will be later. + */ + if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { + if (ctx->delayed_ndp32->dwSignature == sign) + return ctx->delayed_ndp32; + + /* We can only push a single NDP to the end. Return + * NULL to send what we've already got and queue this + * skb for later. + */ + else if (ctx->delayed_ndp32->dwSignature) + return NULL; + } + + /* follow the chain of NDPs, looking for a match */ + while (ndpoffset) { + ndp32 = (struct usb_cdc_ncm_ndp32 *)(skb->data + ndpoffset); + if (ndp32->dwSignature == sign) + return ndp32; + ndpoffset = le32_to_cpu(ndp32->dwNextNdpIndex); + } + + /* align new NDP */ + if (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) + cdc_ncm_align_tail(skb, ctx->tx_ndp_modulus, 0, ctx->tx_curr_size); + + /* verify that there is room for the NDP and the datagram (reserve) */ + if ((ctx->tx_curr_size - skb->len - reserve) < ctx->max_ndp_size) + return NULL; + + /* link to it */ + if (ndp32) + ndp32->dwNextNdpIndex = cpu_to_le32(skb->len); + else + nth32->dwNdpIndex = cpu_to_le32(skb->len); + + /* push a new empty NDP */ + if (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) + ndp32 = skb_put_zero(skb, ctx->max_ndp_size); + else + ndp32 = ctx->delayed_ndp32; + + ndp32->dwSignature = sign; + ndp32->wLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_ndp32) + sizeof(struct usb_cdc_ncm_dpe32)); + return ndp32; +} + struct sk_buff * cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) { struct cdc_ncm_ctx *ctx = (struct cdc_ncm_ctx *)dev->data[0]; - struct usb_cdc_ncm_nth16 *nth16; - struct usb_cdc_ncm_ndp16 *ndp16; + union { + struct usb_cdc_ncm_nth16 *nth16; + struct usb_cdc_ncm_nth32 *nth32; + } nth; + union { + struct usb_cdc_ncm_ndp16 *ndp16; + struct usb_cdc_ncm_ndp32 *ndp32; + } ndp; struct sk_buff *skb_out; u16 n = 0, index, ndplen; u8 ready2send = 0; @@ -1158,6 +1233,9 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) * further. */ if (skb_out == NULL) { + /* If even the smallest allocation fails, abort. */ + if (ctx->tx_curr_size == USB_CDC_NCM_NTB_MIN_OUT_SIZE) + goto alloc_failed; ctx->tx_low_mem_max_cnt = min(ctx->tx_low_mem_max_cnt + 1, (unsigned)CDC_NCM_LOW_MEM_MAX_CNT); ctx->tx_low_mem_val = ctx->tx_low_mem_max_cnt; @@ -1176,20 +1254,23 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) skb_out = alloc_skb(ctx->tx_curr_size, GFP_ATOMIC); /* No allocation possible so we will abort */ - if (skb_out == NULL) { - if (skb != NULL) { - dev_kfree_skb_any(skb); - dev->net->stats.tx_dropped++; - } - goto exit_no_skb; - } + if (!skb_out) + goto alloc_failed; ctx->tx_low_mem_val--; } - /* fill out the initial 16-bit NTB header */ - nth16 = skb_put_zero(skb_out, sizeof(struct usb_cdc_ncm_nth16)); - nth16->dwSignature = cpu_to_le32(USB_CDC_NCM_NTH16_SIGN); - nth16->wHeaderLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_nth16)); - nth16->wSequence = cpu_to_le16(ctx->tx_seq++); + if (ctx->is_ndp16) { + /* fill out the initial 16-bit NTB header */ + nth.nth16 = skb_put_zero(skb_out, sizeof(struct usb_cdc_ncm_nth16)); + nth.nth16->dwSignature = cpu_to_le32(USB_CDC_NCM_NTH16_SIGN); + nth.nth16->wHeaderLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_nth16)); + nth.nth16->wSequence = cpu_to_le16(ctx->tx_seq++); + } else { + /* fill out the initial 32-bit NTB header */ + nth.nth32 = skb_put_zero(skb_out, sizeof(struct usb_cdc_ncm_nth32)); + nth.nth32->dwSignature = cpu_to_le32(USB_CDC_NCM_NTH32_SIGN); + nth.nth32->wHeaderLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_nth32)); + nth.nth32->wSequence = cpu_to_le16(ctx->tx_seq++); + } /* count total number of frames in this NTB */ ctx->tx_curr_frame_num = 0; @@ -1211,13 +1292,17 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) } /* get the appropriate NDP for this skb */ - ndp16 = cdc_ncm_ndp(ctx, skb_out, sign, skb->len + ctx->tx_modulus + ctx->tx_remainder); + if (ctx->is_ndp16) + ndp.ndp16 = cdc_ncm_ndp16(ctx, skb_out, sign, skb->len + ctx->tx_modulus + ctx->tx_remainder); + else + ndp.ndp32 = cdc_ncm_ndp32(ctx, skb_out, sign, skb->len + ctx->tx_modulus + ctx->tx_remainder); /* align beginning of next frame */ cdc_ncm_align_tail(skb_out, ctx->tx_modulus, ctx->tx_remainder, ctx->tx_curr_size); /* check if we had enough room left for both NDP and frame */ - if (!ndp16 || skb_out->len + skb->len + delayed_ndp_size > ctx->tx_curr_size) { + if ((ctx->is_ndp16 && !ndp.ndp16) || (!ctx->is_ndp16 && !ndp.ndp32) || + skb_out->len + skb->len + delayed_ndp_size > ctx->tx_curr_size) { if (n == 0) { /* won't fit, MTU problem? */ dev_kfree_skb_any(skb); @@ -1239,13 +1324,22 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) } /* calculate frame number withing this NDP */ - ndplen = le16_to_cpu(ndp16->wLength); - index = (ndplen - sizeof(struct usb_cdc_ncm_ndp16)) / sizeof(struct usb_cdc_ncm_dpe16) - 1; + if (ctx->is_ndp16) { + ndplen = le16_to_cpu(ndp.ndp16->wLength); + index = (ndplen - sizeof(struct usb_cdc_ncm_ndp16)) / sizeof(struct usb_cdc_ncm_dpe16) - 1; + + /* OK, add this skb */ + ndp.ndp16->dpe16[index].wDatagramLength = cpu_to_le16(skb->len); + ndp.ndp16->dpe16[index].wDatagramIndex = cpu_to_le16(skb_out->len); + ndp.ndp16->wLength = cpu_to_le16(ndplen + sizeof(struct usb_cdc_ncm_dpe16)); + } else { + ndplen = le16_to_cpu(ndp.ndp32->wLength); + index = (ndplen - sizeof(struct usb_cdc_ncm_ndp32)) / sizeof(struct usb_cdc_ncm_dpe32) - 1; - /* OK, add this skb */ - ndp16->dpe16[index].wDatagramLength = cpu_to_le16(skb->len); - ndp16->dpe16[index].wDatagramIndex = cpu_to_le16(skb_out->len); - ndp16->wLength = cpu_to_le16(ndplen + sizeof(struct usb_cdc_ncm_dpe16)); + ndp.ndp32->dpe32[index].dwDatagramLength = cpu_to_le32(skb->len); + ndp.ndp32->dpe32[index].dwDatagramIndex = cpu_to_le32(skb_out->len); + ndp.ndp32->wLength = cpu_to_le16(ndplen + sizeof(struct usb_cdc_ncm_dpe32)); + } skb_put_data(skb_out, skb->data, skb->len); ctx->tx_curr_frame_payload += skb->len; /* count real tx payload data */ dev_kfree_skb_any(skb); @@ -1292,13 +1386,22 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) /* If requested, put NDP at end of frame. */ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { - nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; - cdc_ncm_align_tail(skb_out, ctx->tx_ndp_modulus, 0, ctx->tx_curr_size - ctx->max_ndp_size); - nth16->wNdpIndex = cpu_to_le16(skb_out->len); - skb_put_data(skb_out, ctx->delayed_ndp16, ctx->max_ndp_size); + if (ctx->is_ndp16) { + nth.nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; + cdc_ncm_align_tail(skb_out, ctx->tx_ndp_modulus, 0, ctx->tx_curr_size - ctx->max_ndp_size); + nth.nth16->wNdpIndex = cpu_to_le16(skb_out->len); + skb_put_data(skb_out, ctx->delayed_ndp16, ctx->max_ndp_size); + + /* Zero out delayed NDP - signature checking will naturally fail. */ + ndp.ndp16 = memset(ctx->delayed_ndp16, 0, ctx->max_ndp_size); + } else { + nth.nth32 = (struct usb_cdc_ncm_nth32 *)skb_out->data; + cdc_ncm_align_tail(skb_out, ctx->tx_ndp_modulus, 0, ctx->tx_curr_size - ctx->max_ndp_size); + nth.nth32->dwNdpIndex = cpu_to_le32(skb_out->len); + skb_put_data(skb_out, ctx->delayed_ndp32, ctx->max_ndp_size); - /* Zero out delayed NDP - signature checking will naturally fail. */ - ndp16 = memset(ctx->delayed_ndp16, 0, ctx->max_ndp_size); + ndp.ndp32 = memset(ctx->delayed_ndp32, 0, ctx->max_ndp_size); + } } /* If collected data size is less or equal ctx->min_tx_pkt @@ -1321,8 +1424,13 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) } /* set final frame length */ - nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; - nth16->wBlockLength = cpu_to_le16(skb_out->len); + if (ctx->is_ndp16) { + nth.nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; + nth.nth16->wBlockLength = cpu_to_le16(skb_out->len); + } else { + nth.nth32 = (struct usb_cdc_ncm_nth32 *)skb_out->data; + nth.nth32->dwBlockLength = cpu_to_le32(skb_out->len); + } /* return skb */ ctx->tx_curr_skb = NULL; @@ -1340,6 +1448,11 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) return skb_out; +alloc_failed: + if (skb) { + dev_kfree_skb_any(skb); + dev->net->stats.tx_dropped++; + } exit_no_skb: /* Start timer, if there is a remaining non-empty skb */ if (ctx->tx_curr_skb != NULL && n > 0) @@ -1405,7 +1518,12 @@ cdc_ncm_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags) goto error; spin_lock_bh(&ctx->mtx); - skb_out = cdc_ncm_fill_tx_frame(dev, skb, cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN)); + + if (ctx->is_ndp16) + skb_out = cdc_ncm_fill_tx_frame(dev, skb, cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN)); + else + skb_out = cdc_ncm_fill_tx_frame(dev, skb, cpu_to_le32(USB_CDC_NCM_NDP32_NOCRC_SIGN)); + spin_unlock_bh(&ctx->mtx); return skb_out; @@ -1466,6 +1584,54 @@ int cdc_ncm_rx_verify_nth16(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in) } EXPORT_SYMBOL_GPL(cdc_ncm_rx_verify_nth16); +int cdc_ncm_rx_verify_nth32(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in) +{ + struct usbnet *dev = netdev_priv(skb_in->dev); + struct usb_cdc_ncm_nth32 *nth32; + int len; + int ret = -EINVAL; + + if (ctx == NULL) + goto error; + + if (skb_in->len < (sizeof(struct usb_cdc_ncm_nth32) + + sizeof(struct usb_cdc_ncm_ndp32))) { + netif_dbg(dev, rx_err, dev->net, "frame too short\n"); + goto error; + } + + nth32 = (struct usb_cdc_ncm_nth32 *)skb_in->data; + + if (nth32->dwSignature != cpu_to_le32(USB_CDC_NCM_NTH32_SIGN)) { + netif_dbg(dev, rx_err, dev->net, + "invalid NTH32 signature <%#010x>\n", + le32_to_cpu(nth32->dwSignature)); + goto error; + } + + len = le32_to_cpu(nth32->dwBlockLength); + if (len > ctx->rx_max) { + netif_dbg(dev, rx_err, dev->net, + "unsupported NTB block length %u/%u\n", len, + ctx->rx_max); + goto error; + } + + if ((ctx->rx_seq + 1) != le16_to_cpu(nth32->wSequence) && + (ctx->rx_seq || le16_to_cpu(nth32->wSequence)) && + !((ctx->rx_seq == 0xffff) && !le16_to_cpu(nth32->wSequence))) { + netif_dbg(dev, rx_err, dev->net, + "sequence number glitch prev=%d curr=%d\n", + ctx->rx_seq, le16_to_cpu(nth32->wSequence)); + } + ctx->rx_seq = le16_to_cpu(nth32->wSequence); + + ret = le32_to_cpu(nth32->dwNdpIndex); +error: + return ret; +} +EXPORT_SYMBOL_GPL(cdc_ncm_rx_verify_nth32); + /* verify NDP header and return number of datagrams, or negative error */ int cdc_ncm_rx_verify_ndp16(struct sk_buff *skb_in, int ndpoffset) { @@ -1502,6 +1668,42 @@ int cdc_ncm_rx_verify_ndp16(struct sk_buff *skb_in, int ndpoffset) } EXPORT_SYMBOL_GPL(cdc_ncm_rx_verify_ndp16); +/* verify NDP header and return number of datagrams, or negative error */ +int cdc_ncm_rx_verify_ndp32(struct sk_buff *skb_in, int ndpoffset) +{ + struct usbnet *dev = netdev_priv(skb_in->dev); + struct usb_cdc_ncm_ndp32 *ndp32; + int ret = -EINVAL; + + if ((ndpoffset + sizeof(struct usb_cdc_ncm_ndp32)) > skb_in->len) { + netif_dbg(dev, rx_err, dev->net, "invalid NDP offset <%u>\n", + ndpoffset); + goto error; + } + ndp32 = (struct usb_cdc_ncm_ndp32 *)(skb_in->data + ndpoffset); + + if (le16_to_cpu(ndp32->wLength) < USB_CDC_NCM_NDP32_LENGTH_MIN) { + netif_dbg(dev, rx_err, dev->net, "invalid DPT32 length <%u>\n", + le16_to_cpu(ndp32->wLength)); + goto error; + } + + ret = ((le16_to_cpu(ndp32->wLength) - + sizeof(struct usb_cdc_ncm_ndp32)) / + sizeof(struct usb_cdc_ncm_dpe32)); + ret--; /* we process NDP entries except for the last one */ + + if ((sizeof(struct usb_cdc_ncm_ndp32) + + ret * (sizeof(struct usb_cdc_ncm_dpe32))) > skb_in->len) { + netif_dbg(dev, rx_err, dev->net, "Invalid nframes = %d\n", ret); + ret = -EINVAL; + } + +error: + return ret; +} +EXPORT_SYMBOL_GPL(cdc_ncm_rx_verify_ndp32); + int cdc_ncm_rx_fixup(struct usbnet *dev, struct sk_buff *skb_in) { struct sk_buff *skb; @@ -1510,34 +1712,66 @@ int cdc_ncm_rx_fixup(struct usbnet *dev, struct sk_buff *skb_in) int nframes; int x; int offset; - struct usb_cdc_ncm_ndp16 *ndp16; - struct usb_cdc_ncm_dpe16 *dpe16; + union { + struct usb_cdc_ncm_ndp16 *ndp16; + struct usb_cdc_ncm_ndp32 *ndp32; + } ndp; + union { + struct usb_cdc_ncm_dpe16 *dpe16; + struct usb_cdc_ncm_dpe32 *dpe32; + } dpe; + int ndpoffset; int loopcount = 50; /* arbitrary max preventing infinite loop */ u32 payload = 0; - ndpoffset = cdc_ncm_rx_verify_nth16(ctx, skb_in); + if (ctx->is_ndp16) + ndpoffset = cdc_ncm_rx_verify_nth16(ctx, skb_in); + else + ndpoffset = cdc_ncm_rx_verify_nth32(ctx, skb_in); + if (ndpoffset < 0) goto error; next_ndp: - nframes = cdc_ncm_rx_verify_ndp16(skb_in, ndpoffset); - if (nframes < 0) - goto error; + if (ctx->is_ndp16) { + nframes = cdc_ncm_rx_verify_ndp16(skb_in, ndpoffset); + if (nframes < 0) + goto error; - ndp16 = (struct usb_cdc_ncm_ndp16 *)(skb_in->data + ndpoffset); + ndp.ndp16 = (struct usb_cdc_ncm_ndp16 *)(skb_in->data + ndpoffset); - if (ndp16->dwSignature != cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN)) { - netif_dbg(dev, rx_err, dev->net, - "invalid DPT16 signature <%#010x>\n", - le32_to_cpu(ndp16->dwSignature)); - goto err_ndp; + if (ndp.ndp16->dwSignature != cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN)) { + netif_dbg(dev, rx_err, dev->net, + "invalid DPT16 signature <%#010x>\n", + le32_to_cpu(ndp.ndp16->dwSignature)); + goto err_ndp; + } + dpe.dpe16 = ndp.ndp16->dpe16; + } else { + nframes = cdc_ncm_rx_verify_ndp32(skb_in, ndpoffset); + if (nframes < 0) + goto error; + + ndp.ndp32 = (struct usb_cdc_ncm_ndp32 *)(skb_in->data + ndpoffset); + + if (ndp.ndp32->dwSignature != cpu_to_le32(USB_CDC_NCM_NDP32_NOCRC_SIGN)) { + netif_dbg(dev, rx_err, dev->net, + "invalid DPT32 signature <%#010x>\n", + le32_to_cpu(ndp.ndp32->dwSignature)); + goto err_ndp; + } + dpe.dpe32 = ndp.ndp32->dpe32; } - dpe16 = ndp16->dpe16; - for (x = 0; x < nframes; x++, dpe16++) { - offset = le16_to_cpu(dpe16->wDatagramIndex); - len = le16_to_cpu(dpe16->wDatagramLength); + for (x = 0; x < nframes; x++) { + if (ctx->is_ndp16) { + offset = le16_to_cpu(dpe.dpe16->wDatagramIndex); + len = le16_to_cpu(dpe.dpe16->wDatagramLength); + } else { + offset = le32_to_cpu(dpe.dpe32->dwDatagramIndex); + len = le32_to_cpu(dpe.dpe32->dwDatagramLength); + } /* * CDC NCM ch. 3.7 @@ -1568,10 +1802,19 @@ int cdc_ncm_rx_fixup(struct usbnet *dev, struct sk_buff *skb_in) usbnet_skb_return(dev, skb); payload += len; /* count payload bytes in this NTB */ } + + if (ctx->is_ndp16) + dpe.dpe16++; + else + dpe.dpe32++; } err_ndp: /* are there more NDPs to process? */ - ndpoffset = le16_to_cpu(ndp16->wNextNdpIndex); + if (ctx->is_ndp16) + ndpoffset = le16_to_cpu(ndp.ndp16->wNextNdpIndex); + else + ndpoffset = le32_to_cpu(ndp.ndp32->dwNextNdpIndex); + if (ndpoffset && loopcount--) goto next_ndp; diff --git a/drivers/net/usb/dm9601.c b/drivers/net/usb/dm9601.c index 915ac75b55fc7c43f55db19b379983216b93de5f..5aad26600b03eb0a94446b4509375e5f6d40e042 100644 --- a/drivers/net/usb/dm9601.c +++ b/drivers/net/usb/dm9601.c @@ -221,13 +221,18 @@ static int dm9601_mdio_read(struct net_device *netdev, int phy_id, int loc) struct usbnet *dev = netdev_priv(netdev); __le16 res; + int err; if (phy_id) { netdev_dbg(dev->net, "Only internal phy supported\n"); return 0; } - dm_read_shared_word(dev, 1, loc, &res); + err = dm_read_shared_word(dev, 1, loc, &res); + if (err < 0) { + netdev_err(dev->net, "MDIO read error: %d\n", err); + return err; + } netdev_dbg(dev->net, "dm9601_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n", diff --git a/drivers/net/usb/huawei_cdc_ncm.c b/drivers/net/usb/huawei_cdc_ncm.c index 63f28908afda78e05dcbcdd27e0a1a037f8b6fcb..ac86fb0efb2596d1bd26f16def202cbabf3e35f9 100644 --- a/drivers/net/usb/huawei_cdc_ncm.c +++ b/drivers/net/usb/huawei_cdc_ncm.c @@ -81,11 +81,11 @@ static int huawei_cdc_ncm_bind(struct usbnet *usbnet_dev, */ drvflags |= CDC_NCM_FLAG_NDP_TO_END; - /* Additionally, it has been reported that some Huawei E3372H devices, with - * firmware version 21.318.01.00.541, come out of reset in NTB32 format mode, hence - * needing to be set to the NTB16 one again. + /* For many Huawei devices the NTB32 mode is the default and the best mode + * they work with. Huawei E5785 and E5885 devices refuse to work in NTB16 mode at all. */ - drvflags |= CDC_NCM_FLAG_RESET_NTB16; + drvflags |= CDC_NCM_FLAG_PREFER_NTB32; + ret = cdc_ncm_bind_common(usbnet_dev, intf, 1, drvflags); if (ret) goto err; diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c index 24ce49b311c4c152f18f9e5e12d6e6811b11c946..aefa57e72695438aa5fff06b74068240c901a0d5 100644 --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c @@ -1181,7 +1181,9 @@ static const struct usb_device_id products[] = { {QMI_FIXED_INTF(0x05c6, 0x9080, 8)}, {QMI_FIXED_INTF(0x05c6, 0x9083, 3)}, {QMI_FIXED_INTF(0x05c6, 0x9084, 4)}, + {QMI_QUIRK_SET_DTR(0x05c6, 0x9091, 2)}, /* Compal RXM-G1 */ {QMI_FIXED_INTF(0x05c6, 0x90b2, 3)}, /* ublox R410M */ + {QMI_QUIRK_SET_DTR(0x05c6, 0x90db, 2)}, /* Compal RXM-G1 */ {QMI_FIXED_INTF(0x05c6, 0x920d, 0)}, {QMI_FIXED_INTF(0x05c6, 0x920d, 5)}, {QMI_QUIRK_SET_DTR(0x05c6, 0x9625, 4)}, /* YUGA CLM920-NC5 */ @@ -1285,7 +1287,7 @@ static const struct usb_device_id products[] = { {QMI_FIXED_INTF(0x2001, 0x7e3d, 4)}, /* D-Link DWM-222 A2 */ {QMI_FIXED_INTF(0x2020, 0x2031, 4)}, /* Olicard 600 */ {QMI_FIXED_INTF(0x2020, 0x2033, 4)}, /* BroadMobi BM806U */ - {QMI_FIXED_INTF(0x2020, 0x2060, 4)}, /* BroadMobi BM818 */ + {QMI_QUIRK_SET_DTR(0x2020, 0x2060, 4)}, /* BroadMobi BM818 */ {QMI_FIXED_INTF(0x0f3d, 0x68a2, 8)}, /* Sierra Wireless MC7700 */ {QMI_FIXED_INTF(0x114f, 0x68a2, 8)}, /* Sierra Wireless MC7750 */ {QMI_FIXED_INTF(0x1199, 0x68a2, 8)}, /* Sierra Wireless MC7710 in QMI mode */ @@ -1322,6 +1324,7 @@ static const struct usb_device_id products[] = { {QMI_QUIRK_SET_DTR(0x1bc7, 0x1050, 2)}, /* Telit FN980 */ {QMI_QUIRK_SET_DTR(0x1bc7, 0x1060, 2)}, /* Telit LN920 */ {QMI_QUIRK_SET_DTR(0x1bc7, 0x1070, 2)}, /* Telit FN990 */ + {QMI_QUIRK_SET_DTR(0x1bc7, 0x1080, 2)}, /* Telit FE990 */ {QMI_FIXED_INTF(0x1bc7, 0x1100, 3)}, /* Telit ME910 */ {QMI_FIXED_INTF(0x1bc7, 0x1101, 3)}, /* Telit ME910 dual modem */ {QMI_FIXED_INTF(0x1bc7, 0x1200, 5)}, /* Telit LE920 */ @@ -1373,6 +1376,7 @@ static const struct usb_device_id products[] = { {QMI_QUIRK_SET_DTR(0x2c7c, 0x0191, 4)}, /* Quectel EG91 */ {QMI_QUIRK_SET_DTR(0x2c7c, 0x0195, 4)}, /* Quectel EG95 */ {QMI_FIXED_INTF(0x2c7c, 0x0296, 4)}, /* Quectel BG96 */ + {QMI_QUIRK_SET_DTR(0x2c7c, 0x030e, 4)}, /* Quectel EM05GV2 */ {QMI_QUIRK_SET_DTR(0x2cb7, 0x0104, 4)}, /* Fibocom NL678 series */ {QMI_FIXED_INTF(0x0489, 0xe0b4, 0)}, /* Foxconn T77W968 LTE */ {QMI_FIXED_INTF(0x0489, 0xe0b5, 0)}, /* Foxconn T77W968 LTE with eSIM support*/ diff --git a/drivers/net/usb/smsc75xx.c b/drivers/net/usb/smsc75xx.c index 8b9fd4e071f3d08ccec554460401ab70396633d3..573d7ad2e7082f88775fe7326f57783cf56cbb9c 100644 --- a/drivers/net/usb/smsc75xx.c +++ b/drivers/net/usb/smsc75xx.c @@ -102,7 +102,9 @@ static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index, ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 0, index, &buf, 4); - if (unlikely(ret < 0)) { + if (unlikely(ret < 4)) { + ret = ret < 0 ? ret : -ENODATA; + netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n", index, ret); return ret; @@ -2213,6 +2215,13 @@ static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING; align_count = (4 - ((size + RXW_PADDING) % 4)) % 4; + if (unlikely(size > skb->len)) { + netif_dbg(dev, rx_err, dev->net, + "size err rx_cmd_a=0x%08x\n", + rx_cmd_a); + return 0; + } + if (unlikely(rx_cmd_a & RX_CMD_A_RED)) { netif_dbg(dev, rx_err, dev->net, "Error rx_cmd_a=0x%08x\n", rx_cmd_a); diff --git a/drivers/net/usb/smsc95xx.c b/drivers/net/usb/smsc95xx.c index 4f29010e1aeff09ddac6fdbe258cb5f38cb2e788..37547ac72840fd067a156f1f58ba22ab7d9ec3d3 100644 --- a/drivers/net/usb/smsc95xx.c +++ b/drivers/net/usb/smsc95xx.c @@ -1054,7 +1054,7 @@ static int smsc95xx_reset(struct usbnet *dev) if (timeout >= 100) { netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n"); - return ret; + return -ETIMEDOUT; } ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_); @@ -1950,6 +1950,12 @@ static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) size = (u16)((header & RX_STS_FL_) >> 16); align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4; + if (unlikely(size > skb->len)) { + netif_dbg(dev, rx_err, dev->net, + "size err header=0x%08x\n", header); + return 0; + } + if (unlikely(header & RX_STS_ES_)) { netif_dbg(dev, rx_err, dev->net, "Error header=0x%08x\n", header); diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c index 594b62e38613015e72b887eb889c5c8faa3ce4f7..b5136302710641ea6d58119c5e1314543b94bd63 100644 --- a/drivers/net/usb/usbnet.c +++ b/drivers/net/usb/usbnet.c @@ -1774,6 +1774,10 @@ usbnet_probe (struct usb_interface *udev, const struct usb_device_id *prod) } else if (!info->in || !info->out) status = usbnet_get_endpoints (dev, udev); else { + u8 ep_addrs[3] = { + info->in + USB_DIR_IN, info->out + USB_DIR_OUT, 0 + }; + dev->in = usb_rcvbulkpipe (xdev, info->in); dev->out = usb_sndbulkpipe (xdev, info->out); if (!(info->flags & FLAG_NO_SETINT)) @@ -1783,6 +1787,8 @@ usbnet_probe (struct usb_interface *udev, const struct usb_device_id *prod) else status = 0; + if (status == 0 && !usb_check_bulk_endpoints(udev, ep_addrs)) + status = -EINVAL; } if (status >= 0 && dev->status) status = init_status (dev, udev); diff --git a/drivers/net/usb/zaurus.c b/drivers/net/usb/zaurus.c index 1f19fc5e6117e3d23a2b45b7cf11d32df975155f..9a6ab75752e1696b2f291ef18e11aaa2f57fd54c 100644 --- a/drivers/net/usb/zaurus.c +++ b/drivers/net/usb/zaurus.c @@ -301,9 +301,23 @@ static const struct usb_device_id products [] = { .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | USB_DEVICE_ID_MATCH_DEVICE, .idVendor = 0x04DD, + .idProduct = 0x8005, /* A-300 */ + ZAURUS_FAKE_INTERFACE, + .driver_info = (unsigned long)&bogus_mdlm_info, +}, { + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO + | USB_DEVICE_ID_MATCH_DEVICE, + .idVendor = 0x04DD, .idProduct = 0x8006, /* B-500/SL-5600 */ ZAURUS_MASTER_INTERFACE, .driver_info = ZAURUS_PXA_INFO, +}, { + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO + | USB_DEVICE_ID_MATCH_DEVICE, + .idVendor = 0x04DD, + .idProduct = 0x8006, /* B-500/SL-5600 */ + ZAURUS_FAKE_INTERFACE, + .driver_info = (unsigned long)&bogus_mdlm_info, }, { .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | USB_DEVICE_ID_MATCH_DEVICE, @@ -311,6 +325,13 @@ static const struct usb_device_id products [] = { .idProduct = 0x8007, /* C-700 */ ZAURUS_MASTER_INTERFACE, .driver_info = ZAURUS_PXA_INFO, +}, { + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO + | USB_DEVICE_ID_MATCH_DEVICE, + .idVendor = 0x04DD, + .idProduct = 0x8007, /* C-700 */ + ZAURUS_FAKE_INTERFACE, + .driver_info = (unsigned long)&bogus_mdlm_info, }, { .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | USB_DEVICE_ID_MATCH_DEVICE, diff --git a/drivers/net/veth.c b/drivers/net/veth.c index ea999a663933023e2d9df741ba986becea597cda..8006a7716168fc7b8cd271f92f35d889360324ac 100644 --- a/drivers/net/veth.c +++ b/drivers/net/veth.c @@ -181,6 +181,7 @@ static netdev_tx_t veth_xmit(struct sk_buff *skb, struct net_device *dev) { struct veth_priv *rcv_priv, *priv = netdev_priv(dev); struct veth_rq *rq = NULL; + int ret = NETDEV_TX_OK; struct net_device *rcv; int length = skb->len; bool rcv_xdp = false; @@ -210,6 +211,7 @@ static netdev_tx_t veth_xmit(struct sk_buff *skb, struct net_device *dev) } else { drop: atomic64_inc(&priv->dropped); + ret = NET_XMIT_DROP; } if (rcv_xdp) @@ -217,7 +219,7 @@ static netdev_tx_t veth_xmit(struct sk_buff *skb, struct net_device *dev) rcu_read_unlock(); - return NETDEV_TX_OK; + return ret; } static u64 veth_stats_one(struct pcpu_vstats *result, struct net_device *dev) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 406ef4cc636d456c834733dc47e4914378b961b0..331d74f9281b6d660ae4bb9e82a2c16962820f32 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -600,8 +600,13 @@ static struct page *xdp_linearize_page(struct receive_queue *rq, int page_off, unsigned int *len) { - struct page *page = alloc_page(GFP_ATOMIC); + int tailroom = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); + struct page *page; + if (page_off + *len + tailroom > PAGE_SIZE) + return NULL; + + page = alloc_page(GFP_ATOMIC); if (!page) return NULL; @@ -609,7 +614,6 @@ static struct page *xdp_linearize_page(struct receive_queue *rq, page_off += *len; while (--*num_buf) { - int tailroom = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); unsigned int buflen; void *buf; int off; @@ -2651,6 +2655,27 @@ static void free_receive_page_frags(struct virtnet_info *vi) put_page(vi->rq[i].alloc_frag.page); } +static void virtnet_sq_free_unused_buf(struct virtqueue *vq, void *buf) +{ + if (!is_xdp_frame(buf)) + dev_kfree_skb(buf); + else + xdp_return_frame(ptr_to_xdp(buf)); +} + +static void virtnet_rq_free_unused_buf(struct virtqueue *vq, void *buf) +{ + struct virtnet_info *vi = vq->vdev->priv; + int i = vq2rxq(vq); + + if (vi->mergeable_rx_bufs) + put_page(virt_to_head_page(buf)); + else if (vi->big_packets) + give_pages(&vi->rq[i], buf); + else + put_page(virt_to_head_page(buf)); +} + static void free_unused_bufs(struct virtnet_info *vi) { void *buf; @@ -2658,26 +2683,16 @@ static void free_unused_bufs(struct virtnet_info *vi) for (i = 0; i < vi->max_queue_pairs; i++) { struct virtqueue *vq = vi->sq[i].vq; - while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) { - if (!is_xdp_frame(buf)) - dev_kfree_skb(buf); - else - xdp_return_frame(ptr_to_xdp(buf)); - } + while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) + virtnet_sq_free_unused_buf(vq, buf); + cond_resched(); } for (i = 0; i < vi->max_queue_pairs; i++) { struct virtqueue *vq = vi->rq[i].vq; - - while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) { - if (vi->mergeable_rx_bufs) { - put_page(virt_to_head_page(buf)); - } else if (vi->big_packets) { - give_pages(&vi->rq[i], buf); - } else { - put_page(virt_to_head_page(buf)); - } - } + while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) + virtnet_rq_free_unused_buf(vq, buf); + cond_resched(); } } @@ -3117,6 +3132,8 @@ static int virtnet_probe(struct virtio_device *vdev) virtio_device_ready(vdev); + _virtnet_set_queues(vi, vi->curr_queue_pairs); + rtnl_unlock(); err = virtnet_cpu_notif_add(vi); @@ -3125,8 +3142,6 @@ static int virtnet_probe(struct virtio_device *vdev) goto free_unregister_netdev; } - virtnet_set_queues(vi, vi->curr_queue_pairs); - /* Assume link up if device can't report link status, otherwise get link status from config. */ netif_carrier_off(dev); diff --git a/drivers/net/vxlan.c b/drivers/net/vxlan.c index 1b98a888a168ea4e629eac52aad3d8c5e859769c..d5c8d0d54b33df00e87589134566381bd17e6991 100644 --- a/drivers/net/vxlan.c +++ b/drivers/net/vxlan.c @@ -542,6 +542,32 @@ static int vxlan_fdb_append(struct vxlan_fdb *f, return 1; } +static bool vxlan_parse_gpe_proto(struct vxlanhdr *hdr, __be16 *protocol) +{ + struct vxlanhdr_gpe *gpe = (struct vxlanhdr_gpe *)hdr; + + /* Need to have Next Protocol set for interfaces in GPE mode. */ + if (!gpe->np_applied) + return false; + /* "The initial version is 0. If a receiver does not support the + * version indicated it MUST drop the packet. + */ + if (gpe->version != 0) + return false; + /* "When the O bit is set to 1, the packet is an OAM packet and OAM + * processing MUST occur." However, we don't implement OAM + * processing, thus drop the packet. + */ + if (gpe->oam_flag) + return false; + + *protocol = tun_p_to_eth_p(gpe->next_protocol); + if (!*protocol) + return false; + + return true; +} + static struct vxlanhdr *vxlan_gro_remcsum(struct sk_buff *skb, unsigned int off, struct vxlanhdr *vh, size_t hdrlen, @@ -1279,35 +1305,6 @@ static void vxlan_parse_gbp_hdr(struct vxlanhdr *unparsed, unparsed->vx_flags &= ~VXLAN_GBP_USED_BITS; } -static bool vxlan_parse_gpe_hdr(struct vxlanhdr *unparsed, - __be16 *protocol, - struct sk_buff *skb, u32 vxflags) -{ - struct vxlanhdr_gpe *gpe = (struct vxlanhdr_gpe *)unparsed; - - /* Need to have Next Protocol set for interfaces in GPE mode. */ - if (!gpe->np_applied) - return false; - /* "The initial version is 0. If a receiver does not support the - * version indicated it MUST drop the packet. - */ - if (gpe->version != 0) - return false; - /* "When the O bit is set to 1, the packet is an OAM packet and OAM - * processing MUST occur." However, we don't implement OAM - * processing, thus drop the packet. - */ - if (gpe->oam_flag) - return false; - - *protocol = tun_p_to_eth_p(gpe->next_protocol); - if (!*protocol) - return false; - - unparsed->vx_flags &= ~VXLAN_GPE_USED_BITS; - return true; -} - static bool vxlan_set_mac(struct vxlan_dev *vxlan, struct vxlan_sock *vs, struct sk_buff *skb, __be32 vni) @@ -1409,8 +1406,9 @@ static int vxlan_rcv(struct sock *sk, struct sk_buff *skb) * used by VXLAN extensions if explicitly requested. */ if (vs->flags & VXLAN_F_GPE) { - if (!vxlan_parse_gpe_hdr(&unparsed, &protocol, skb, vs->flags)) + if (!vxlan_parse_gpe_proto(&unparsed, &protocol)) goto drop; + unparsed.vx_flags &= ~VXLAN_GPE_USED_BITS; raw_proto = true; } diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c index 5df6e85e7ccb7884590ec635f2748c1ba3760da2..c8cff000a931f969958771c7b0ae48a1f0f6966f 100644 --- a/drivers/net/wan/fsl_ucc_hdlc.c +++ b/drivers/net/wan/fsl_ucc_hdlc.c @@ -37,6 +37,8 @@ #define TDM_PPPOHT_SLIC_MAXIN +static int uhdlc_close(struct net_device *dev); + static struct ucc_tdm_info utdm_primary_info = { .uf_info = { .tsa = 0, @@ -661,6 +663,7 @@ static int uhdlc_open(struct net_device *dev) hdlc_device *hdlc = dev_to_hdlc(dev); struct ucc_hdlc_private *priv = hdlc->priv; struct ucc_tdm *utdm = priv->utdm; + int rc = 0; if (priv->hdlc_busy != 1) { if (request_irq(priv->ut_info->uf_info.irq, @@ -683,10 +686,13 @@ static int uhdlc_open(struct net_device *dev) netif_device_attach(priv->ndev); napi_enable(&priv->napi); netif_start_queue(dev); - hdlc_open(dev); + + rc = hdlc_open(dev); + if (rc) + uhdlc_close(dev); } - return 0; + return rc; } static void uhdlc_memclean(struct ucc_hdlc_private *priv) @@ -775,6 +781,8 @@ static int uhdlc_close(struct net_device *dev) netif_stop_queue(dev); priv->hdlc_busy = 0; + hdlc_close(dev); + return 0; } diff --git a/drivers/net/wan/lapbether.c b/drivers/net/wan/lapbether.c index 6233805fc032c40b50db7d59eb2d6795e23d11a5..b2ede9acb4bcf4013609d9b92efcc18753cf69b8 100644 --- a/drivers/net/wan/lapbether.c +++ b/drivers/net/wan/lapbether.c @@ -344,6 +344,9 @@ static int lapbeth_new_device(struct net_device *dev) ASSERT_RTNL(); + if (dev->type != ARPHRD_ETHER) + return -EINVAL; + ndev = alloc_netdev(sizeof(*lapbeth), "lapb%d", NET_NAME_UNKNOWN, lapbeth_setup); if (!ndev) diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index deea41e96f0183e7d6d1b10ee029e1aa0f50c523..96025d42b0eea351f6578e26a643640c9eec58cc 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -705,7 +705,7 @@ EXPORT_SYMBOL(z8530_nop); irqreturn_t z8530_interrupt(int irq, void *dev_id) { struct z8530_dev *dev=dev_id; - u8 uninitialized_var(intr); + u8 intr; static volatile int locker=0; int work=0; struct z8530_irqhandler *irqs; diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c index 436eac342b62276aa7e39eaefa6a29521ef4f2f4..7e43d449131ddcdf567448205d91dacd98f677d9 100644 --- a/drivers/net/wireless/ath/ath10k/core.c +++ b/drivers/net/wireless/ath/ath10k/core.c @@ -1891,7 +1891,7 @@ static int ath10k_init_uart(struct ath10k *ar) static int ath10k_init_hw_params(struct ath10k *ar) { - const struct ath10k_hw_params *uninitialized_var(hw_params); + const struct ath10k_hw_params *hw_params; int i; for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { diff --git a/drivers/net/wireless/ath/ath10k/debug.c b/drivers/net/wireless/ath/ath10k/debug.c index 4e980e78ba95c3d955ec922b9da48a58e85e871c..9586deab5c004afa7e277392e731f36be8fcb974 100644 --- a/drivers/net/wireless/ath/ath10k/debug.c +++ b/drivers/net/wireless/ath/ath10k/debug.c @@ -1146,7 +1146,7 @@ void ath10k_debug_get_et_strings(struct ieee80211_hw *hw, u32 sset, u8 *data) { if (sset == ETH_SS_STATS) - memcpy(data, *ath10k_gstrings_stats, + memcpy(data, ath10k_gstrings_stats, sizeof(ath10k_gstrings_stats)); } diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c index 92757495c73b6fef3c234ec0a7be86e27bc892b3..c929a62c722ad3972e29643e268856079615a19e 100644 --- a/drivers/net/wireless/ath/ath10k/pci.c +++ b/drivers/net/wireless/ath/ath10k/pci.c @@ -1957,8 +1957,9 @@ static int ath10k_pci_hif_start(struct ath10k *ar) ath10k_pci_irq_enable(ar); ath10k_pci_rx_post(ar); - pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, - ar_pci->link_ctl); + pcie_capability_clear_and_set_word(ar_pci->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC, + ar_pci->link_ctl & PCI_EXP_LNKCTL_ASPMC); return 0; } @@ -2813,8 +2814,8 @@ static int ath10k_pci_hif_power_up(struct ath10k *ar) pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, &ar_pci->link_ctl); - pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, - ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); + pcie_capability_clear_word(ar_pci->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC); /* * Bring the target up cleanly. diff --git a/drivers/net/wireless/ath/ath5k/eeprom.c b/drivers/net/wireless/ath/ath5k/eeprom.c index 01163b3339451b151cb79ca0c584e24cd7d85e80..92f5c8e8309012573d598dbb7663f9f170f38527 100644 --- a/drivers/net/wireless/ath/ath5k/eeprom.c +++ b/drivers/net/wireless/ath/ath5k/eeprom.c @@ -529,7 +529,7 @@ ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max, ee->ee_n_piers[mode]++; freq2 = (val >> 8) & 0xff; - if (!freq2) + if (!freq2 || i >= max) break; pc[i++].freq = ath5k_eeprom_bin2freq(ee, diff --git a/drivers/net/wireless/ath/ath6kl/bmi.c b/drivers/net/wireless/ath/ath6kl/bmi.c index bde5a10d470c8e74e169e3f4479d9f2487542c34..af98e871199d317f3807dc1e333920cd3b003b7a 100644 --- a/drivers/net/wireless/ath/ath6kl/bmi.c +++ b/drivers/net/wireless/ath/ath6kl/bmi.c @@ -246,7 +246,7 @@ int ath6kl_bmi_execute(struct ath6kl *ar, u32 addr, u32 *param) return -EACCES; } - size = sizeof(cid) + sizeof(addr) + sizeof(param); + size = sizeof(cid) + sizeof(addr) + sizeof(*param); if (size > ar->bmi.max_cmd_size) { WARN_ON(1); return -EINVAL; diff --git a/drivers/net/wireless/ath/ath6kl/htc_pipe.c b/drivers/net/wireless/ath/ath6kl/htc_pipe.c index 434b6682964662fa3b9e723fcead47745e5dd622..73bf4af1f3c7c84d724e7e0e52d0e6a9c0d0dc36 100644 --- a/drivers/net/wireless/ath/ath6kl/htc_pipe.c +++ b/drivers/net/wireless/ath/ath6kl/htc_pipe.c @@ -963,8 +963,8 @@ static int ath6kl_htc_pipe_rx_complete(struct ath6kl *ar, struct sk_buff *skb, * Thus the possibility of ar->htc_target being NULL * via ath6kl_recv_complete -> ath6kl_usb_io_comp_work. */ - if (WARN_ON_ONCE(!target)) { - ath6kl_err("Target not yet initialized\n"); + if (!target) { + ath6kl_dbg(ATH6KL_DBG_HTC, "Target not yet initialized\n"); status = -EINVAL; goto free_skb; } diff --git a/drivers/net/wireless/ath/ath6kl/init.c b/drivers/net/wireless/ath/ath6kl/init.c index 58fb227a849f68e3aaa918b80ba2a0e1596bbfc3..49b93a5b7a72a192f035ad914a271d0d2ee32616 100644 --- a/drivers/net/wireless/ath/ath6kl/init.c +++ b/drivers/net/wireless/ath/ath6kl/init.c @@ -1575,7 +1575,7 @@ static int ath6kl_init_upload(struct ath6kl *ar) int ath6kl_init_hw_params(struct ath6kl *ar) { - const struct ath6kl_hw *uninitialized_var(hw); + const struct ath6kl_hw *hw; int i; for (i = 0; i < ARRAY_SIZE(hw_list); i++) { diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c index 63019c3de034d4771974b8d5aa01d73bae2dc74a..26023e3b4b9df7736255d9cb92df01859dc9c562 100644 --- a/drivers/net/wireless/ath/ath9k/ahb.c +++ b/drivers/net/wireless/ath/ath9k/ahb.c @@ -136,8 +136,8 @@ static int ath_ahb_probe(struct platform_device *pdev) ah = sc->sc_ah; ath9k_hw_name(ah, hw_name, sizeof(hw_name)); - wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", - hw_name, (unsigned long)mem, irq); + wiphy_info(hw->wiphy, "%s mem=0x%p, irq=%d\n", + hw_name, mem, irq); return 0; diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c index 2fe12b0de5b4f2a47af17caf7417d0ce48793728..dea8a998fb6229e8a76951dd22b1b2e2f49c912c 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c @@ -1099,17 +1099,22 @@ static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue) { u32 dma_dbg_chain, dma_dbg_complete; u8 dcu_chain_state, dcu_complete_state; + unsigned int dbg_reg, reg_offset; int i; - for (i = 0; i < NUM_STATUS_READS; i++) { - if (queue < 6) - dma_dbg_chain = REG_READ(ah, AR_DMADBG_4); - else - dma_dbg_chain = REG_READ(ah, AR_DMADBG_5); + if (queue < 6) { + dbg_reg = AR_DMADBG_4; + reg_offset = queue * 5; + } else { + dbg_reg = AR_DMADBG_5; + reg_offset = (queue - 6) * 5; + } + for (i = 0; i < NUM_STATUS_READS; i++) { + dma_dbg_chain = REG_READ(ah, dbg_reg); dma_dbg_complete = REG_READ(ah, AR_DMADBG_6); - dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f; + dcu_chain_state = (dma_dbg_chain >> reg_offset) & 0x1f; dcu_complete_state = dma_dbg_complete & 0x3; if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1)) @@ -1128,6 +1133,7 @@ static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah) u8 dcu_chain_state, dcu_complete_state; bool dcu_wait_frdone = false; unsigned long chk_dcu = 0; + unsigned int reg_offset; unsigned int i = 0; dma_dbg_4 = REG_READ(ah, AR_DMADBG_4); @@ -1139,12 +1145,15 @@ static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah) goto exit; for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { - if (i < 6) + if (i < 6) { chk_dbg = dma_dbg_4; - else + reg_offset = i * 5; + } else { chk_dbg = dma_dbg_5; + reg_offset = (i - 6) * 5; + } - dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f; + dcu_chain_state = (chk_dbg >> reg_offset) & 0x1f; if (dcu_chain_state == 0x6) { dcu_wait_frdone = true; chk_dcu |= BIT(i); diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c index 84fe686709496a273d2c66d2697000807ab32ea2..e0a4e3fa8730536ed99c30fde54fb6e2b51acad8 100644 --- a/drivers/net/wireless/ath/ath9k/debug.c +++ b/drivers/net/wireless/ath/ath9k/debug.c @@ -1297,7 +1297,7 @@ void ath9k_get_et_strings(struct ieee80211_hw *hw, u32 sset, u8 *data) { if (sset == ETH_SS_STATS) - memcpy(data, *ath9k_gstrings_stats, + memcpy(data, ath9k_gstrings_stats, sizeof(ath9k_gstrings_stats)); } diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c index 8a18a33b5b59f22463f01595d58867772768f86a..3aa915d2155455b27ac0c5e3f3c5566bfc56edec 100644 --- a/drivers/net/wireless/ath/ath9k/hif_usb.c +++ b/drivers/net/wireless/ath/ath9k/hif_usb.c @@ -244,11 +244,11 @@ static inline void ath9k_skb_queue_complete(struct hif_device_usb *hif_dev, ath9k_htc_txcompletion_cb(hif_dev->htc_handle, skb, txok); if (txok) { - TX_STAT_INC(skb_success); - TX_STAT_ADD(skb_success_bytes, ln); + TX_STAT_INC(hif_dev, skb_success); + TX_STAT_ADD(hif_dev, skb_success_bytes, ln); } else - TX_STAT_INC(skb_failed); + TX_STAT_INC(hif_dev, skb_failed); } } @@ -302,7 +302,7 @@ static void hif_usb_tx_cb(struct urb *urb) hif_dev->tx.tx_buf_cnt++; if (!(hif_dev->tx.flags & HIF_USB_TX_STOP)) __hif_usb_tx(hif_dev); /* Check for pending SKBs */ - TX_STAT_INC(buf_completed); + TX_STAT_INC(hif_dev, buf_completed); spin_unlock(&hif_dev->tx.tx_lock); } @@ -353,7 +353,7 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev) tx_buf->len += tx_buf->offset; __skb_queue_tail(&tx_buf->skb_queue, nskb); - TX_STAT_INC(skb_queued); + TX_STAT_INC(hif_dev, skb_queued); } usb_fill_bulk_urb(tx_buf->urb, hif_dev->udev, @@ -368,11 +368,10 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev) __skb_queue_head_init(&tx_buf->skb_queue); list_move_tail(&tx_buf->list, &hif_dev->tx.tx_buf); hif_dev->tx.tx_buf_cnt++; + } else { + TX_STAT_INC(hif_dev, buf_queued); } - if (!ret) - TX_STAT_INC(buf_queued); - return ret; } @@ -515,7 +514,7 @@ static void hif_usb_sta_drain(void *hif_handle, u8 idx) ath9k_htc_txcompletion_cb(hif_dev->htc_handle, skb, false); hif_dev->tx.tx_skb_cnt--; - TX_STAT_INC(skb_failed); + TX_STAT_INC(hif_dev, skb_failed); } } @@ -535,6 +534,24 @@ static struct ath9k_htc_hif hif_usb = { .send = hif_usb_send, }; +/* Need to free remain_skb allocated in ath9k_hif_usb_rx_stream + * in case ath9k_hif_usb_rx_stream wasn't called next time to + * process the buffer and subsequently free it. + */ +static void ath9k_hif_usb_free_rx_remain_skb(struct hif_device_usb *hif_dev) +{ + unsigned long flags; + + spin_lock_irqsave(&hif_dev->rx_lock, flags); + if (hif_dev->remain_skb) { + dev_kfree_skb_any(hif_dev->remain_skb); + hif_dev->remain_skb = NULL; + hif_dev->rx_remain_len = 0; + RX_STAT_INC(hif_dev, skb_dropped); + } + spin_unlock_irqrestore(&hif_dev->rx_lock, flags); +} + static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, struct sk_buff *skb) { @@ -562,11 +579,11 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, memcpy(ptr, skb->data, rx_remain_len); rx_pkt_len += rx_remain_len; - hif_dev->rx_remain_len = 0; skb_put(remain_skb, rx_pkt_len); skb_pool[pool_index++] = remain_skb; - + hif_dev->remain_skb = NULL; + hif_dev->rx_remain_len = 0; } else { index = rx_remain_len; } @@ -585,16 +602,21 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, pkt_len = get_unaligned_le16(ptr + index); pkt_tag = get_unaligned_le16(ptr + index + 2); + /* It is supposed that if we have an invalid pkt_tag or + * pkt_len then the whole input SKB is considered invalid + * and dropped; the associated packets already in skb_pool + * are dropped, too. + */ if (pkt_tag != ATH_USB_RX_STREAM_MODE_TAG) { - RX_STAT_INC(skb_dropped); - return; + RX_STAT_INC(hif_dev, skb_dropped); + goto invalid_pkt; } if (pkt_len > 2 * MAX_RX_BUF_SIZE) { dev_err(&hif_dev->udev->dev, "ath9k_htc: invalid pkt_len (%x)\n", pkt_len); - RX_STAT_INC(skb_dropped); - return; + RX_STAT_INC(hif_dev, skb_dropped); + goto invalid_pkt; } pad_len = 4 - (pkt_len & 0x3); @@ -606,11 +628,6 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, if (index > MAX_RX_BUF_SIZE) { spin_lock(&hif_dev->rx_lock); - hif_dev->rx_remain_len = index - MAX_RX_BUF_SIZE; - hif_dev->rx_transfer_len = - MAX_RX_BUF_SIZE - chk_idx - 4; - hif_dev->rx_pad_len = pad_len; - nskb = __dev_alloc_skb(pkt_len + 32, GFP_ATOMIC); if (!nskb) { dev_err(&hif_dev->udev->dev, @@ -618,8 +635,14 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, spin_unlock(&hif_dev->rx_lock); goto err; } + + hif_dev->rx_remain_len = index - MAX_RX_BUF_SIZE; + hif_dev->rx_transfer_len = + MAX_RX_BUF_SIZE - chk_idx - 4; + hif_dev->rx_pad_len = pad_len; + skb_reserve(nskb, 32); - RX_STAT_INC(skb_allocated); + RX_STAT_INC(hif_dev, skb_allocated); memcpy(nskb->data, &(skb->data[chk_idx+4]), hif_dev->rx_transfer_len); @@ -640,7 +663,7 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, goto err; } skb_reserve(nskb, 32); - RX_STAT_INC(skb_allocated); + RX_STAT_INC(hif_dev, skb_allocated); memcpy(nskb->data, &(skb->data[chk_idx+4]), pkt_len); skb_put(nskb, pkt_len); @@ -650,11 +673,18 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, err: for (i = 0; i < pool_index; i++) { - RX_STAT_ADD(skb_completed_bytes, skb_pool[i]->len); + RX_STAT_ADD(hif_dev, skb_completed_bytes, skb_pool[i]->len); ath9k_htc_rx_msg(hif_dev->htc_handle, skb_pool[i], skb_pool[i]->len, USB_WLAN_RX_PIPE); - RX_STAT_INC(skb_completed); + RX_STAT_INC(hif_dev, skb_completed); } + return; +invalid_pkt: + for (i = 0; i < pool_index; i++) { + dev_kfree_skb_any(skb_pool[i]); + RX_STAT_INC(hif_dev, skb_dropped); + } + return; } static void ath9k_hif_usb_rx_cb(struct urb *urb) @@ -856,6 +886,7 @@ static int ath9k_hif_usb_alloc_tx_urbs(struct hif_device_usb *hif_dev) static void ath9k_hif_usb_dealloc_rx_urbs(struct hif_device_usb *hif_dev) { usb_kill_anchored_urbs(&hif_dev->rx_submitted); + ath9k_hif_usb_free_rx_remain_skb(hif_dev); } static int ath9k_hif_usb_alloc_rx_urbs(struct hif_device_usb *hif_dev) diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h index 81107100e36827ab8b46863fb35079af105a821b..232e93dfbc83125a9279d580f3c68587096b9a4b 100644 --- a/drivers/net/wireless/ath/ath9k/htc.h +++ b/drivers/net/wireless/ath/ath9k/htc.h @@ -325,14 +325,18 @@ static inline struct ath9k_htc_tx_ctl *HTC_SKB_CB(struct sk_buff *skb) } #ifdef CONFIG_ATH9K_HTC_DEBUGFS -#define __STAT_SAFE(expr) (hif_dev->htc_handle->drv_priv ? (expr) : 0) -#define TX_STAT_INC(c) __STAT_SAFE(hif_dev->htc_handle->drv_priv->debug.tx_stats.c++) -#define TX_STAT_ADD(c, a) __STAT_SAFE(hif_dev->htc_handle->drv_priv->debug.tx_stats.c += a) -#define RX_STAT_INC(c) __STAT_SAFE(hif_dev->htc_handle->drv_priv->debug.skbrx_stats.c++) -#define RX_STAT_ADD(c, a) __STAT_SAFE(hif_dev->htc_handle->drv_priv->debug.skbrx_stats.c += a) -#define CAB_STAT_INC priv->debug.tx_stats.cab_queued++ - -#define TX_QSTAT_INC(q) (priv->debug.tx_stats.queue_stats[q]++) +#define __STAT_SAFE(hif_dev, expr) do { ((hif_dev)->htc_handle->drv_priv ? (expr) : 0); } while (0) +#define CAB_STAT_INC(priv) do { ((priv)->debug.tx_stats.cab_queued++); } while (0) +#define TX_QSTAT_INC(priv, q) do { ((priv)->debug.tx_stats.queue_stats[q]++); } while (0) + +#define TX_STAT_INC(hif_dev, c) \ + __STAT_SAFE((hif_dev), (hif_dev)->htc_handle->drv_priv->debug.tx_stats.c++) +#define TX_STAT_ADD(hif_dev, c, a) \ + __STAT_SAFE((hif_dev), (hif_dev)->htc_handle->drv_priv->debug.tx_stats.c += a) +#define RX_STAT_INC(hif_dev, c) \ + __STAT_SAFE((hif_dev), (hif_dev)->htc_handle->drv_priv->debug.skbrx_stats.c++) +#define RX_STAT_ADD(hif_dev, c, a) \ + __STAT_SAFE((hif_dev), (hif_dev)->htc_handle->drv_priv->debug.skbrx_stats.c += a) void ath9k_htc_err_stat_rx(struct ath9k_htc_priv *priv, struct ath_rx_status *rs); @@ -372,13 +376,13 @@ void ath9k_htc_get_et_stats(struct ieee80211_hw *hw, struct ethtool_stats *stats, u64 *data); #else -#define TX_STAT_INC(c) do { } while (0) -#define TX_STAT_ADD(c, a) do { } while (0) -#define RX_STAT_INC(c) do { } while (0) -#define RX_STAT_ADD(c, a) do { } while (0) -#define CAB_STAT_INC do { } while (0) +#define TX_STAT_INC(hif_dev, c) do { } while (0) +#define TX_STAT_ADD(hif_dev, c, a) do { } while (0) +#define RX_STAT_INC(hif_dev, c) do { } while (0) +#define RX_STAT_ADD(hif_dev, c, a) do { } while (0) -#define TX_QSTAT_INC(c) do { } while (0) +#define CAB_STAT_INC(priv) +#define TX_QSTAT_INC(priv, c) static inline void ath9k_htc_err_stat_rx(struct ath9k_htc_priv *priv, struct ath_rx_status *rs) diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c index b3ed65e5c4da81f62bb6f4519ed2015fa0c62459..e79bbcd3279aff7cb24bf45de5d1b63d6e6e3cf4 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c @@ -428,7 +428,7 @@ void ath9k_htc_get_et_strings(struct ieee80211_hw *hw, u32 sset, u8 *data) { if (sset == ETH_SS_STATS) - memcpy(data, *ath9k_htc_gstrings_stats, + memcpy(data, ath9k_htc_gstrings_stats, sizeof(ath9k_htc_gstrings_stats)); } @@ -491,7 +491,7 @@ int ath9k_htc_init_debug(struct ath_hw *ah) priv->debug.debugfs_phy = debugfs_create_dir(KBUILD_MODNAME, priv->hw->wiphy->debugfsdir); - if (!priv->debug.debugfs_phy) + if (IS_ERR(priv->debug.debugfs_phy)) return -ENOMEM; ath9k_cmn_spectral_init_debug(&priv->spec_priv, priv->debug.debugfs_phy); diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c index 3cd3f3ca1000da5ff357a899089b0d9a9e25668f..979ac31a77a07d03cd0c95128cacaa4112a179e6 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c @@ -106,20 +106,20 @@ static inline enum htc_endpoint_id get_htc_epid(struct ath9k_htc_priv *priv, switch (qnum) { case 0: - TX_QSTAT_INC(IEEE80211_AC_VO); + TX_QSTAT_INC(priv, IEEE80211_AC_VO); epid = priv->data_vo_ep; break; case 1: - TX_QSTAT_INC(IEEE80211_AC_VI); + TX_QSTAT_INC(priv, IEEE80211_AC_VI); epid = priv->data_vi_ep; break; case 2: - TX_QSTAT_INC(IEEE80211_AC_BE); + TX_QSTAT_INC(priv, IEEE80211_AC_BE); epid = priv->data_be_ep; break; case 3: default: - TX_QSTAT_INC(IEEE80211_AC_BK); + TX_QSTAT_INC(priv, IEEE80211_AC_BK); epid = priv->data_bk_ep; break; } @@ -323,7 +323,7 @@ static void ath9k_htc_tx_data(struct ath9k_htc_priv *priv, memcpy(tx_fhdr, (u8 *) &tx_hdr, sizeof(tx_hdr)); if (is_cab) { - CAB_STAT_INC; + CAB_STAT_INC(priv); tx_ctl->epid = priv->cab_ep; return; } diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.c b/drivers/net/wireless/ath/ath9k/htc_hst.c index 6d69cf69fd86e1beaaee72a707d2e248c1b6efab..d5e5f9cf4ca86824ceecaaf9326af99b56ff9a9c 100644 --- a/drivers/net/wireless/ath/ath9k/htc_hst.c +++ b/drivers/net/wireless/ath/ath9k/htc_hst.c @@ -114,7 +114,13 @@ static void htc_process_conn_rsp(struct htc_target *target, if (svc_rspmsg->status == HTC_SERVICE_SUCCESS) { epid = svc_rspmsg->endpoint_id; - if (epid < 0 || epid >= ENDPOINT_MAX) + + /* Check that the received epid for the endpoint to attach + * a new service is valid. ENDPOINT0 can't be used here as it + * is already reserved for HTC_CTRL_RSVD_SVC service and thus + * should not be modified. + */ + if (epid <= ENDPOINT0 || epid >= ENDPOINT_MAX) return; service_id = be16_to_cpu(svc_rspmsg->service_id); @@ -394,7 +400,7 @@ static void ath9k_htc_fw_panic_report(struct htc_target *htc_handle, * HTC Messages are handled directly here and the obtained SKB * is freed. * - * Service messages (Data, WMI) passed to the corresponding + * Service messages (Data, WMI) are passed to the corresponding * endpoint RX handlers, which have to free the SKB. */ void ath9k_htc_rx_msg(struct htc_target *htc_handle, @@ -481,6 +487,8 @@ void ath9k_htc_rx_msg(struct htc_target *htc_handle, if (endpoint->ep_callbacks.rx) endpoint->ep_callbacks.rx(endpoint->ep_callbacks.priv, skb, epid); + else + goto invalid; } } diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c index fae572b384169cb27598a271056d418669e4c2b3..922a3f208837e8ad6095c819919ee6020828cf3b 100644 --- a/drivers/net/wireless/ath/ath9k/init.c +++ b/drivers/net/wireless/ath/ath9k/init.c @@ -230,7 +230,7 @@ static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 cl struct ath_hw *ah = hw_priv; struct ath_common *common = ath9k_hw_common(ah); struct ath_softc *sc = (struct ath_softc *) common->priv; - unsigned long uninitialized_var(flags); + unsigned long flags; u32 val; if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c index ee1b9c39bad7a0e036b19edddccb518062683e85..2fdf9858a73d95990f0afc9972d7273f7fb539e4 100644 --- a/drivers/net/wireless/ath/ath9k/main.c +++ b/drivers/net/wireless/ath/ath9k/main.c @@ -200,7 +200,7 @@ void ath_cancel_work(struct ath_softc *sc) void ath_restart_work(struct ath_softc *sc) { ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work, - ATH_HW_CHECK_POLL_INT); + msecs_to_jiffies(ATH_HW_CHECK_POLL_INT)); if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, @@ -847,7 +847,7 @@ static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix) static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix) { struct ath_hw *ah = sc->sc_ah; - int i; + int i, j; struct ath_txq *txq; bool key_in_use = false; @@ -865,8 +865,9 @@ static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix) if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { int idx = txq->txq_tailidx; - while (!key_in_use && - !list_empty(&txq->txq_fifo[idx])) { + for (j = 0; !key_in_use && + !list_empty(&txq->txq_fifo[idx]) && + j < ATH_TXFIFO_DEPTH; j++) { key_in_use = ath9k_txq_list_has_key( &txq->txq_fifo[idx], keyix); INCR(idx, ATH_TXFIFO_DEPTH); @@ -2227,7 +2228,7 @@ void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop, } ieee80211_queue_delayed_work(hw, &sc->hw_check_work, - ATH_HW_CHECK_POLL_INT); + msecs_to_jiffies(ATH_HW_CHECK_POLL_INT)); } static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c index 92b2dd396436adb8db52ff74dd9c966f7262c590..cb3318bd3cad24b08ee7869e29cc0eca368b7fa1 100644 --- a/drivers/net/wireless/ath/ath9k/pci.c +++ b/drivers/net/wireless/ath/ath9k/pci.c @@ -993,8 +993,8 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) sc->sc_ah->msi_reg = 0; ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name)); - wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", - hw_name, (unsigned long)sc->mem, pdev->irq); + wiphy_info(hw->wiphy, "%s mem=0x%p, irq=%d\n", + hw_name, sc->mem, pdev->irq); return 0; diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c index 066677bb83eb008f0bfdd542c645b78106581241..78ce349a48f7e8d67e4f2376780506a4532976fc 100644 --- a/drivers/net/wireless/ath/ath9k/wmi.c +++ b/drivers/net/wireless/ath/ath9k/wmi.c @@ -218,6 +218,10 @@ static void ath9k_wmi_ctrl_rx(void *priv, struct sk_buff *skb, if (unlikely(wmi->stopped)) goto free_skb; + /* Validate the obtained SKB. */ + if (unlikely(skb->len < sizeof(struct wmi_cmd_hdr))) + goto free_skb; + hdr = (struct wmi_cmd_hdr *) skb->data; cmd_id = be16_to_cpu(hdr->command_id); @@ -235,10 +239,10 @@ static void ath9k_wmi_ctrl_rx(void *priv, struct sk_buff *skb, spin_unlock_irqrestore(&wmi->wmi_lock, flags); goto free_skb; } - spin_unlock_irqrestore(&wmi->wmi_lock, flags); /* WMI command response */ ath9k_wmi_rsp_callback(wmi, skb); + spin_unlock_irqrestore(&wmi->wmi_lock, flags); free_skb: kfree_skb(skb); @@ -276,7 +280,8 @@ int ath9k_wmi_connect(struct htc_target *htc, struct wmi *wmi, static int ath9k_wmi_cmd_issue(struct wmi *wmi, struct sk_buff *skb, - enum wmi_cmd_id cmd, u16 len) + enum wmi_cmd_id cmd, u16 len, + u8 *rsp_buf, u32 rsp_len) { struct wmi_cmd_hdr *hdr; unsigned long flags; @@ -286,6 +291,11 @@ static int ath9k_wmi_cmd_issue(struct wmi *wmi, hdr->seq_no = cpu_to_be16(++wmi->tx_seq_id); spin_lock_irqsave(&wmi->wmi_lock, flags); + + /* record the rsp buffer and length */ + wmi->cmd_rsp_buf = rsp_buf; + wmi->cmd_rsp_len = rsp_len; + wmi->last_seq_id = wmi->tx_seq_id; spin_unlock_irqrestore(&wmi->wmi_lock, flags); @@ -301,8 +311,8 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, struct ath_common *common = ath9k_hw_common(ah); u16 headroom = sizeof(struct htc_frame_hdr) + sizeof(struct wmi_cmd_hdr); + unsigned long time_left, flags; struct sk_buff *skb; - unsigned long time_left; int ret = 0; if (ah->ah_flags & AH_UNPLUGGED) @@ -326,11 +336,7 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, goto out; } - /* record the rsp buffer and length */ - wmi->cmd_rsp_buf = rsp_buf; - wmi->cmd_rsp_len = rsp_len; - - ret = ath9k_wmi_cmd_issue(wmi, skb, cmd_id, cmd_len); + ret = ath9k_wmi_cmd_issue(wmi, skb, cmd_id, cmd_len, rsp_buf, rsp_len); if (ret) goto out; @@ -338,6 +344,9 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, if (!time_left) { ath_dbg(common, WMI, "Timeout waiting for WMI command: %s\n", wmi_cmd_to_name(cmd_id)); + spin_lock_irqsave(&wmi->wmi_lock, flags); + wmi->last_seq_id = 0; + spin_unlock_irqrestore(&wmi->wmi_lock, flags); mutex_unlock(&wmi->op_mutex); kfree_skb(skb); return -ETIMEDOUT; diff --git a/drivers/net/wireless/atmel/atmel_cs.c b/drivers/net/wireless/atmel/atmel_cs.c index 7afc9c5329fb1b307a83773cf19e3d9d1b2b3cba..f5fa1a95b0c15589a4693e638355629a51743259 100644 --- a/drivers/net/wireless/atmel/atmel_cs.c +++ b/drivers/net/wireless/atmel/atmel_cs.c @@ -73,6 +73,7 @@ struct local_info { static int atmel_probe(struct pcmcia_device *p_dev) { struct local_info *local; + int ret; dev_dbg(&p_dev->dev, "atmel_attach()\n"); @@ -83,8 +84,16 @@ static int atmel_probe(struct pcmcia_device *p_dev) p_dev->priv = local; - return atmel_config(p_dev); -} /* atmel_attach */ + ret = atmel_config(p_dev); + if (ret) + goto err_free_priv; + + return 0; + +err_free_priv: + kfree(p_dev->priv); + return ret; +} static void atmel_detach(struct pcmcia_device *link) { diff --git a/drivers/net/wireless/broadcom/b43/b43.h b/drivers/net/wireless/broadcom/b43/b43.h index b77d1a904f7e68f29fc73f34ef8defdf4fb71c56..a449561fccf2871ec8e7c18ed212ecce7a8f8d87 100644 --- a/drivers/net/wireless/broadcom/b43/b43.h +++ b/drivers/net/wireless/broadcom/b43/b43.h @@ -651,7 +651,7 @@ struct b43_iv { union { __be16 d16; __be32 d32; - } data __packed; + } __packed data; } __packed; diff --git a/drivers/net/wireless/broadcom/b43/debugfs.c b/drivers/net/wireless/broadcom/b43/debugfs.c index 77046384dd8004c60493012d94fe5d82ba9ab667..70b02d6641709c5770b7a90213c8c06db32d5e4b 100644 --- a/drivers/net/wireless/broadcom/b43/debugfs.c +++ b/drivers/net/wireless/broadcom/b43/debugfs.c @@ -506,7 +506,7 @@ static ssize_t b43_debugfs_read(struct file *file, char __user *userbuf, struct b43_wldev *dev; struct b43_debugfs_fops *dfops; struct b43_dfs_file *dfile; - ssize_t uninitialized_var(ret); + ssize_t ret; char *buf; const size_t bufsize = 1024 * 16; /* 16 kiB buffer */ const size_t buforder = get_order(bufsize); diff --git a/drivers/net/wireless/broadcom/b43/dma.c b/drivers/net/wireless/broadcom/b43/dma.c index d46d57b989aec0d1fa869128b62022b7be401892..06139835055fa3fcf84b6fe51f761fd301b1be9c 100644 --- a/drivers/net/wireless/broadcom/b43/dma.c +++ b/drivers/net/wireless/broadcom/b43/dma.c @@ -50,7 +50,7 @@ static u32 b43_dma_address(struct b43_dma *dma, dma_addr_t dmaaddr, enum b43_addrtype addrtype) { - u32 uninitialized_var(addr); + u32 addr; switch (addrtype) { case B43_DMA_ADDR_LOW: diff --git a/drivers/net/wireless/broadcom/b43/lo.c b/drivers/net/wireless/broadcom/b43/lo.c index a335f94c72ff7019c3017afadc7946ec26283cc3..10cc0c0d70c3ac2937c398bce316b5f9b3ee23a1 100644 --- a/drivers/net/wireless/broadcom/b43/lo.c +++ b/drivers/net/wireless/broadcom/b43/lo.c @@ -742,7 +742,7 @@ struct b43_lo_calib *b43_calibrate_lo_setting(struct b43_wldev *dev, }; int max_rx_gain; struct b43_lo_calib *cal; - struct lo_g_saved_values uninitialized_var(saved_regs); + struct lo_g_saved_values saved_regs; /* Values from the "TXCTL Register and Value Table" */ u16 txctl_reg; u16 txctl_value; diff --git a/drivers/net/wireless/broadcom/b43/phy_n.c b/drivers/net/wireless/broadcom/b43/phy_n.c index 3508a78226193a62785555632a973887c98d95de..3a74e82c9fb68cab6da5bdbe040a472b74e5d5e6 100644 --- a/drivers/net/wireless/broadcom/b43/phy_n.c +++ b/drivers/net/wireless/broadcom/b43/phy_n.c @@ -5655,7 +5655,7 @@ static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, u8 rfctl[2]; u8 afectl_core; u16 tmp[6]; - u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna; + u16 cur_hpf1, cur_hpf2, cur_lna; u32 real, imag; enum nl80211_band band; diff --git a/drivers/net/wireless/broadcom/b43/xmit.c b/drivers/net/wireless/broadcom/b43/xmit.c index 1b9c191e2a2290e8030c095e96aafeb245e64cd5..c123e220466370e8f139f011598194cc672e297e 100644 --- a/drivers/net/wireless/broadcom/b43/xmit.c +++ b/drivers/net/wireless/broadcom/b43/xmit.c @@ -435,10 +435,10 @@ int b43_generate_txhdr(struct b43_wldev *dev, if ((rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) { unsigned int len; - struct ieee80211_hdr *uninitialized_var(hdr); + struct ieee80211_hdr *hdr; int rts_rate, rts_rate_fb; int rts_rate_ofdm, rts_rate_fb_ofdm; - struct b43_plcp_hdr6 *uninitialized_var(plcp); + struct b43_plcp_hdr6 *plcp; struct ieee80211_rate *rts_cts_rate; rts_cts_rate = ieee80211_get_rts_cts_rate(dev->wl->hw, info); @@ -449,7 +449,7 @@ int b43_generate_txhdr(struct b43_wldev *dev, rts_rate_fb_ofdm = b43_is_ofdm_rate(rts_rate_fb); if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { - struct ieee80211_cts *uninitialized_var(cts); + struct ieee80211_cts *cts; switch (dev->fw.hdr_format) { case B43_FW_HDR_598: @@ -471,7 +471,7 @@ int b43_generate_txhdr(struct b43_wldev *dev, mac_ctl |= B43_TXH_MAC_SENDCTS; len = sizeof(struct ieee80211_cts); } else { - struct ieee80211_rts *uninitialized_var(rts); + struct ieee80211_rts *rts; switch (dev->fw.hdr_format) { case B43_FW_HDR_598: @@ -663,8 +663,8 @@ void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr) const struct b43_rxhdr_fw4 *rxhdr = _rxhdr; __le16 fctl; u16 phystat0, phystat3; - u16 uninitialized_var(chanstat), uninitialized_var(mactime); - u32 uninitialized_var(macstat); + u16 chanstat, mactime; + u32 macstat; u16 chanid; int padding, rate_idx; diff --git a/drivers/net/wireless/broadcom/b43legacy/b43legacy.h b/drivers/net/wireless/broadcom/b43legacy/b43legacy.h index 6b0cec467938fc555f23f0d464086afec69181d9..f49365d14619f39d05535e0b82b4e7f2228fbfa5 100644 --- a/drivers/net/wireless/broadcom/b43legacy/b43legacy.h +++ b/drivers/net/wireless/broadcom/b43legacy/b43legacy.h @@ -379,7 +379,7 @@ struct b43legacy_iv { union { __be16 d16; __be32 d32; - } data __packed; + } __packed data; } __packed; #define B43legacy_PHYMODE(phytype) (1 << (phytype)) diff --git a/drivers/net/wireless/broadcom/b43legacy/debugfs.c b/drivers/net/wireless/broadcom/b43legacy/debugfs.c index 82ef56ed7ca1ba70e5e94c0586b1a96dad305854..d3c9a916b44c5851330b3305e2bafc9612e2f5c1 100644 --- a/drivers/net/wireless/broadcom/b43legacy/debugfs.c +++ b/drivers/net/wireless/broadcom/b43legacy/debugfs.c @@ -203,7 +203,7 @@ static ssize_t b43legacy_debugfs_read(struct file *file, char __user *userbuf, struct b43legacy_wldev *dev; struct b43legacy_debugfs_fops *dfops; struct b43legacy_dfs_file *dfile; - ssize_t uninitialized_var(ret); + ssize_t ret; char *buf; const size_t bufsize = 1024 * 16; /* 16 KiB buffer */ const size_t buforder = get_order(bufsize); diff --git a/drivers/net/wireless/broadcom/b43legacy/main.c b/drivers/net/wireless/broadcom/b43legacy/main.c index ef1f1b5d63b10ac0609cd4971604385d3c5688d8..a147c93583b262350f23e6c26cb3143ae7f0a33b 100644 --- a/drivers/net/wireless/broadcom/b43legacy/main.c +++ b/drivers/net/wireless/broadcom/b43legacy/main.c @@ -2612,7 +2612,7 @@ static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev) static int b43legacy_switch_phymode(struct b43legacy_wl *wl, unsigned int new_mode) { - struct b43legacy_wldev *uninitialized_var(up_dev); + struct b43legacy_wldev *up_dev; struct b43legacy_wldev *down_dev; int err; bool gmode = false; diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c index 75790b13c96210df7874926f9ebf9e82f1ad5616..1827be85f115f69a3c13f97877676053684c1cd6 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c @@ -1238,13 +1238,14 @@ static u16 brcmf_map_fw_linkdown_reason(const struct brcmf_event_msg *e) static int brcmf_set_pmk(struct brcmf_if *ifp, const u8 *pmk_data, u16 pmk_len) { struct brcmf_wsec_pmk_le pmk; - int i, err; + int err; + + memset(&pmk, 0, sizeof(pmk)); - /* convert to firmware key format */ - pmk.key_len = cpu_to_le16(pmk_len << 1); - pmk.flags = cpu_to_le16(BRCMF_WSEC_PASSPHRASE); - for (i = 0; i < pmk_len; i++) - snprintf(&pmk.key[2 * i], 3, "%02x", pmk_data[i]); + /* pass pmk directly */ + pmk.key_len = cpu_to_le16(pmk_len); + pmk.flags = cpu_to_le16(0); + memcpy(pmk.key, pmk_data, pmk_len); /* store psk in firmware */ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_WSEC_PMK, @@ -5362,6 +5363,11 @@ static s32 brcmf_get_assoc_ies(struct brcmf_cfg80211_info *cfg, (struct brcmf_cfg80211_assoc_ielen_le *)cfg->extra_buf; req_len = le32_to_cpu(assoc_info->req_len); resp_len = le32_to_cpu(assoc_info->resp_len); + if (req_len > WL_EXTRA_BUF_MAX || resp_len > WL_EXTRA_BUF_MAX) { + brcmf_err("invalid lengths in assoc info: req %u resp %u\n", + req_len, resp_len); + return -EINVAL; + } if (req_len) { err = brcmf_fil_iovar_data_get(ifp, "assoc_req_ies", cfg->extra_buf, diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c index 8510d207ee87d1f5b2f65dfae112a19201d6ba5e..3626ea9be92af5fcd6ccf72ec52ce3a6902c3a2b 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c @@ -273,6 +273,7 @@ int brcmf_c_preinit_dcmds(struct brcmf_if *ifp) err); goto done; } + buf[sizeof(buf) - 1] = '\0'; ptr = (char *)buf; strsep(&ptr, "\n"); @@ -289,15 +290,17 @@ int brcmf_c_preinit_dcmds(struct brcmf_if *ifp) if (err) { brcmf_dbg(TRACE, "retrieving clmver failed, %d\n", err); } else { + buf[sizeof(buf) - 1] = '\0'; clmver = (char *)buf; - /* store CLM version for adding it to revinfo debugfs file */ - memcpy(ifp->drvr->clmver, clmver, sizeof(ifp->drvr->clmver)); /* Replace all newline/linefeed characters with space * character */ strreplace(clmver, '\n', ' '); + /* store CLM version for adding it to revinfo debugfs file */ + memcpy(ifp->drvr->clmver, clmver, sizeof(ifp->drvr->clmver)); + brcmf_dbg(INFO, "CLM version = %s\n", clmver); } diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c index 31bf2eb47b49f6fc05163e9336761ec04bdeb85b..6fd155187263fd94037ac417a41504372e47ad58 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c @@ -313,6 +313,7 @@ static netdev_tx_t brcmf_netdev_start_xmit(struct sk_buff *skb, brcmf_err("%s: failed to expand headroom\n", brcmf_ifname(ifp)); atomic_inc(&drvr->bus_if->stats.pktcow_failed); + dev_kfree_skb(skb); goto done; } } diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/msgbuf.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/msgbuf.c index 768a99c15c08b4b7dd3dff2d25a78127788caf71..e81e892ddacc5e9ab2841049caa9a63f9ce498f4 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/msgbuf.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/msgbuf.c @@ -339,8 +339,11 @@ brcmf_msgbuf_alloc_pktid(struct device *dev, count++; } while (count < pktids->array_size); - if (count == pktids->array_size) + if (count == pktids->array_size) { + dma_unmap_single(dev, *physaddr, skb->len - data_offset, + pktids->direction); return -ENOMEM; + } array[*idx].data_offset = data_offset; array[*idx].physaddr = *physaddr; diff --git a/drivers/net/wireless/cisco/airo.c b/drivers/net/wireless/cisco/airo.c index 5a6ee0b014da0fead684d88003bf4282030567e3..a01b42c7c07ac076e9ac2c1db552db1d970bdbe2 100644 --- a/drivers/net/wireless/cisco/airo.c +++ b/drivers/net/wireless/cisco/airo.c @@ -6100,8 +6100,11 @@ static int airo_get_rate(struct net_device *dev, { struct airo_info *local = dev->ml_priv; StatusRid status_rid; /* Card status info */ + int ret; - readStatusRid(local, &status_rid, 1); + ret = readStatusRid(local, &status_rid, 1); + if (ret) + return -EBUSY; vwrq->value = le16_to_cpu(status_rid.currentXmitRate) * 500000; /* If more than one rate, set auto */ diff --git a/drivers/net/wireless/intel/ipw2x00/ipw2100.c b/drivers/net/wireless/intel/ipw2x00/ipw2100.c index a3a470976a5c7a05d41f9cd722665d1d8228fc42..68c4ce352b006175e5048770efe4acd601476c40 100644 --- a/drivers/net/wireless/intel/ipw2x00/ipw2100.c +++ b/drivers/net/wireless/intel/ipw2x00/ipw2100.c @@ -2308,10 +2308,11 @@ static int ipw2100_alloc_skb(struct ipw2100_priv *priv, return -ENOMEM; packet->rxp = (struct ipw2100_rx *)packet->skb->data; - packet->dma_addr = pci_map_single(priv->pci_dev, packet->skb->data, + packet->dma_addr = dma_map_single(&priv->pci_dev->dev, + packet->skb->data, sizeof(struct ipw2100_rx), - PCI_DMA_FROMDEVICE); - if (pci_dma_mapping_error(priv->pci_dev, packet->dma_addr)) { + DMA_FROM_DEVICE); + if (dma_mapping_error(&priv->pci_dev->dev, packet->dma_addr)) { dev_kfree_skb(packet->skb); return -ENOMEM; } @@ -2492,9 +2493,8 @@ static void isr_rx(struct ipw2100_priv *priv, int i, return; } - pci_unmap_single(priv->pci_dev, - packet->dma_addr, - sizeof(struct ipw2100_rx), PCI_DMA_FROMDEVICE); + dma_unmap_single(&priv->pci_dev->dev, packet->dma_addr, + sizeof(struct ipw2100_rx), DMA_FROM_DEVICE); skb_put(packet->skb, status->frame_size); @@ -2576,8 +2576,8 @@ static void isr_rx_monitor(struct ipw2100_priv *priv, int i, return; } - pci_unmap_single(priv->pci_dev, packet->dma_addr, - sizeof(struct ipw2100_rx), PCI_DMA_FROMDEVICE); + dma_unmap_single(&priv->pci_dev->dev, packet->dma_addr, + sizeof(struct ipw2100_rx), DMA_FROM_DEVICE); memmove(packet->skb->data + sizeof(struct ipw_rt_hdr), packet->skb->data, status->frame_size); @@ -2702,9 +2702,9 @@ static void __ipw2100_rx_process(struct ipw2100_priv *priv) /* Sync the DMA for the RX buffer so CPU is sure to get * the correct values */ - pci_dma_sync_single_for_cpu(priv->pci_dev, packet->dma_addr, - sizeof(struct ipw2100_rx), - PCI_DMA_FROMDEVICE); + dma_sync_single_for_cpu(&priv->pci_dev->dev, packet->dma_addr, + sizeof(struct ipw2100_rx), + DMA_FROM_DEVICE); if (unlikely(ipw2100_corruption_check(priv, i))) { ipw2100_corruption_detected(priv, i); @@ -2936,9 +2936,8 @@ static int __ipw2100_tx_process(struct ipw2100_priv *priv) (packet->index + 1 + i) % txq->entries, tbd->host_addr, tbd->buf_length); - pci_unmap_single(priv->pci_dev, - tbd->host_addr, - tbd->buf_length, PCI_DMA_TODEVICE); + dma_unmap_single(&priv->pci_dev->dev, tbd->host_addr, + tbd->buf_length, DMA_TO_DEVICE); } libipw_txb_free(packet->info.d_struct.txb); @@ -3178,15 +3177,13 @@ static void ipw2100_tx_send_data(struct ipw2100_priv *priv) tbd->buf_length = packet->info.d_struct.txb-> fragments[i]->len - LIBIPW_3ADDR_LEN; - tbd->host_addr = pci_map_single(priv->pci_dev, + tbd->host_addr = dma_map_single(&priv->pci_dev->dev, packet->info.d_struct. - txb->fragments[i]-> - data + + txb->fragments[i]->data + LIBIPW_3ADDR_LEN, tbd->buf_length, - PCI_DMA_TODEVICE); - if (pci_dma_mapping_error(priv->pci_dev, - tbd->host_addr)) { + DMA_TO_DEVICE); + if (dma_mapping_error(&priv->pci_dev->dev, tbd->host_addr)) { IPW_DEBUG_TX("dma mapping error\n"); break; } @@ -3195,10 +3192,10 @@ static void ipw2100_tx_send_data(struct ipw2100_priv *priv) txq->next, tbd->host_addr, tbd->buf_length); - pci_dma_sync_single_for_device(priv->pci_dev, - tbd->host_addr, - tbd->buf_length, - PCI_DMA_TODEVICE); + dma_sync_single_for_device(&priv->pci_dev->dev, + tbd->host_addr, + tbd->buf_length, + DMA_TO_DEVICE); txq->next++; txq->next %= txq->entries; @@ -3453,9 +3450,9 @@ static int ipw2100_msg_allocate(struct ipw2100_priv *priv) return -ENOMEM; for (i = 0; i < IPW_COMMAND_POOL_SIZE; i++) { - v = pci_zalloc_consistent(priv->pci_dev, - sizeof(struct ipw2100_cmd_header), - &p); + v = dma_alloc_coherent(&priv->pci_dev->dev, + sizeof(struct ipw2100_cmd_header), &p, + GFP_KERNEL); if (!v) { printk(KERN_ERR DRV_NAME ": " "%s: PCI alloc failed for msg " @@ -3474,11 +3471,10 @@ static int ipw2100_msg_allocate(struct ipw2100_priv *priv) return 0; for (j = 0; j < i; j++) { - pci_free_consistent(priv->pci_dev, - sizeof(struct ipw2100_cmd_header), - priv->msg_buffers[j].info.c_struct.cmd, - priv->msg_buffers[j].info.c_struct. - cmd_phys); + dma_free_coherent(&priv->pci_dev->dev, + sizeof(struct ipw2100_cmd_header), + priv->msg_buffers[j].info.c_struct.cmd, + priv->msg_buffers[j].info.c_struct.cmd_phys); } kfree(priv->msg_buffers); @@ -3509,11 +3505,10 @@ static void ipw2100_msg_free(struct ipw2100_priv *priv) return; for (i = 0; i < IPW_COMMAND_POOL_SIZE; i++) { - pci_free_consistent(priv->pci_dev, - sizeof(struct ipw2100_cmd_header), - priv->msg_buffers[i].info.c_struct.cmd, - priv->msg_buffers[i].info.c_struct. - cmd_phys); + dma_free_coherent(&priv->pci_dev->dev, + sizeof(struct ipw2100_cmd_header), + priv->msg_buffers[i].info.c_struct.cmd, + priv->msg_buffers[i].info.c_struct.cmd_phys); } kfree(priv->msg_buffers); @@ -4336,7 +4331,8 @@ static int status_queue_allocate(struct ipw2100_priv *priv, int entries) IPW_DEBUG_INFO("enter\n"); q->size = entries * sizeof(struct ipw2100_status); - q->drv = pci_zalloc_consistent(priv->pci_dev, q->size, &q->nic); + q->drv = dma_alloc_coherent(&priv->pci_dev->dev, q->size, &q->nic, + GFP_KERNEL); if (!q->drv) { IPW_DEBUG_WARNING("Can not allocate status queue.\n"); return -ENOMEM; @@ -4352,9 +4348,10 @@ static void status_queue_free(struct ipw2100_priv *priv) IPW_DEBUG_INFO("enter\n"); if (priv->status_queue.drv) { - pci_free_consistent(priv->pci_dev, priv->status_queue.size, - priv->status_queue.drv, - priv->status_queue.nic); + dma_free_coherent(&priv->pci_dev->dev, + priv->status_queue.size, + priv->status_queue.drv, + priv->status_queue.nic); priv->status_queue.drv = NULL; } @@ -4370,7 +4367,8 @@ static int bd_queue_allocate(struct ipw2100_priv *priv, q->entries = entries; q->size = entries * sizeof(struct ipw2100_bd); - q->drv = pci_zalloc_consistent(priv->pci_dev, q->size, &q->nic); + q->drv = dma_alloc_coherent(&priv->pci_dev->dev, q->size, &q->nic, + GFP_KERNEL); if (!q->drv) { IPW_DEBUG_INFO ("can't allocate shared memory for buffer descriptors\n"); @@ -4390,7 +4388,8 @@ static void bd_queue_free(struct ipw2100_priv *priv, struct ipw2100_bd_queue *q) return; if (q->drv) { - pci_free_consistent(priv->pci_dev, q->size, q->drv, q->nic); + dma_free_coherent(&priv->pci_dev->dev, q->size, q->drv, + q->nic); q->drv = NULL; } @@ -4450,9 +4449,9 @@ static int ipw2100_tx_allocate(struct ipw2100_priv *priv) } for (i = 0; i < TX_PENDED_QUEUE_LENGTH; i++) { - v = pci_alloc_consistent(priv->pci_dev, - sizeof(struct ipw2100_data_header), - &p); + v = dma_alloc_coherent(&priv->pci_dev->dev, + sizeof(struct ipw2100_data_header), &p, + GFP_KERNEL); if (!v) { printk(KERN_ERR DRV_NAME ": %s: PCI alloc failed for tx " "buffers.\n", @@ -4472,11 +4471,10 @@ static int ipw2100_tx_allocate(struct ipw2100_priv *priv) return 0; for (j = 0; j < i; j++) { - pci_free_consistent(priv->pci_dev, - sizeof(struct ipw2100_data_header), - priv->tx_buffers[j].info.d_struct.data, - priv->tx_buffers[j].info.d_struct. - data_phys); + dma_free_coherent(&priv->pci_dev->dev, + sizeof(struct ipw2100_data_header), + priv->tx_buffers[j].info.d_struct.data, + priv->tx_buffers[j].info.d_struct.data_phys); } kfree(priv->tx_buffers); @@ -4553,12 +4551,10 @@ static void ipw2100_tx_free(struct ipw2100_priv *priv) priv->tx_buffers[i].info.d_struct.txb = NULL; } if (priv->tx_buffers[i].info.d_struct.data) - pci_free_consistent(priv->pci_dev, - sizeof(struct ipw2100_data_header), - priv->tx_buffers[i].info.d_struct. - data, - priv->tx_buffers[i].info.d_struct. - data_phys); + dma_free_coherent(&priv->pci_dev->dev, + sizeof(struct ipw2100_data_header), + priv->tx_buffers[i].info.d_struct.data, + priv->tx_buffers[i].info.d_struct.data_phys); } kfree(priv->tx_buffers); @@ -4621,9 +4617,10 @@ static int ipw2100_rx_allocate(struct ipw2100_priv *priv) return 0; for (j = 0; j < i; j++) { - pci_unmap_single(priv->pci_dev, priv->rx_buffers[j].dma_addr, + dma_unmap_single(&priv->pci_dev->dev, + priv->rx_buffers[j].dma_addr, sizeof(struct ipw2100_rx_packet), - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); dev_kfree_skb(priv->rx_buffers[j].skb); } @@ -4675,10 +4672,10 @@ static void ipw2100_rx_free(struct ipw2100_priv *priv) for (i = 0; i < RX_QUEUE_LENGTH; i++) { if (priv->rx_buffers[i].rxp) { - pci_unmap_single(priv->pci_dev, + dma_unmap_single(&priv->pci_dev->dev, priv->rx_buffers[i].dma_addr, sizeof(struct ipw2100_rx), - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); dev_kfree_skb(priv->rx_buffers[i].skb); } } @@ -6214,7 +6211,7 @@ static int ipw2100_pci_init_one(struct pci_dev *pci_dev, pci_set_master(pci_dev); pci_set_drvdata(pci_dev, priv); - err = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32)); + err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32)); if (err) { printk(KERN_WARNING DRV_NAME "Error calling pci_set_dma_mask.\n"); diff --git a/drivers/net/wireless/intel/ipw2x00/ipw2200.c b/drivers/net/wireless/intel/ipw2x00/ipw2200.c index 04aee2fdba3756f7ffa63b997f27cf44bb149c39..c6f2cc3083aef57120fb8817c7a9627b008dd470 100644 --- a/drivers/net/wireless/intel/ipw2x00/ipw2200.c +++ b/drivers/net/wireless/intel/ipw2x00/ipw2200.c @@ -3456,9 +3456,10 @@ static void ipw_rx_queue_reset(struct ipw_priv *priv, /* In the reset function, these buffers may have been allocated * to an SKB, so we need to unmap and free potential storage */ if (rxq->pool[i].skb != NULL) { - pci_unmap_single(priv->pci_dev, rxq->pool[i].dma_addr, - IPW_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); - dev_kfree_skb(rxq->pool[i].skb); + dma_unmap_single(&priv->pci_dev->dev, + rxq->pool[i].dma_addr, + IPW_RX_BUF_SIZE, DMA_FROM_DEVICE); + dev_kfree_skb_irq(rxq->pool[i].skb); rxq->pool[i].skb = NULL; } list_add_tail(&rxq->pool[i].list, &rxq->rx_used); @@ -3790,7 +3791,8 @@ static int ipw_queue_tx_init(struct ipw_priv *priv, } q->bd = - pci_alloc_consistent(dev, sizeof(q->bd[0]) * count, &q->q.dma_addr); + dma_alloc_coherent(&dev->dev, sizeof(q->bd[0]) * count, + &q->q.dma_addr, GFP_KERNEL); if (!q->bd) { IPW_ERROR("pci_alloc_consistent(%zd) failed\n", sizeof(q->bd[0]) * count); @@ -3832,9 +3834,10 @@ static void ipw_queue_tx_free_tfd(struct ipw_priv *priv, /* unmap chunks if any */ for (i = 0; i < le32_to_cpu(bd->u.data.num_chunks); i++) { - pci_unmap_single(dev, le32_to_cpu(bd->u.data.chunk_ptr[i]), + dma_unmap_single(&dev->dev, + le32_to_cpu(bd->u.data.chunk_ptr[i]), le16_to_cpu(bd->u.data.chunk_len[i]), - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); if (txq->txb[txq->q.last_used]) { libipw_txb_free(txq->txb[txq->q.last_used]); txq->txb[txq->q.last_used] = NULL; @@ -3866,8 +3869,8 @@ static void ipw_queue_tx_free(struct ipw_priv *priv, struct clx2_tx_queue *txq) } /* free buffers belonging to queue itself */ - pci_free_consistent(dev, sizeof(txq->bd[0]) * q->n_bd, txq->bd, - q->dma_addr); + dma_free_coherent(&dev->dev, sizeof(txq->bd[0]) * q->n_bd, txq->bd, + q->dma_addr); kfree(txq->txb); /* 0 fill whole structure */ @@ -5212,8 +5215,8 @@ static void ipw_rx_queue_replenish(void *data) list_del(element); rxb->dma_addr = - pci_map_single(priv->pci_dev, rxb->skb->data, - IPW_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); + dma_map_single(&priv->pci_dev->dev, rxb->skb->data, + IPW_RX_BUF_SIZE, DMA_FROM_DEVICE); list_add_tail(&rxb->list, &rxq->rx_free); rxq->free_count++; @@ -5246,8 +5249,9 @@ static void ipw_rx_queue_free(struct ipw_priv *priv, struct ipw_rx_queue *rxq) for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { if (rxq->pool[i].skb != NULL) { - pci_unmap_single(priv->pci_dev, rxq->pool[i].dma_addr, - IPW_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); + dma_unmap_single(&priv->pci_dev->dev, + rxq->pool[i].dma_addr, + IPW_RX_BUF_SIZE, DMA_FROM_DEVICE); dev_kfree_skb(rxq->pool[i].skb); } } @@ -8285,9 +8289,8 @@ static void ipw_rx(struct ipw_priv *priv) } priv->rxq->queue[i] = NULL; - pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr, - IPW_RX_BUF_SIZE, - PCI_DMA_FROMDEVICE); + dma_sync_single_for_cpu(&priv->pci_dev->dev, rxb->dma_addr, + IPW_RX_BUF_SIZE, DMA_FROM_DEVICE); pkt = (struct ipw_rx_packet *)rxb->skb->data; IPW_DEBUG_RX("Packet: type=%02X seq=%02X bits=%02X\n", @@ -8439,8 +8442,8 @@ static void ipw_rx(struct ipw_priv *priv) rxb->skb = NULL; } - pci_unmap_single(priv->pci_dev, rxb->dma_addr, - IPW_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); + dma_unmap_single(&priv->pci_dev->dev, rxb->dma_addr, + IPW_RX_BUF_SIZE, DMA_FROM_DEVICE); list_add_tail(&rxb->list, &priv->rxq->rx_used); i = (i + 1) % RX_QUEUE_SIZE; @@ -10239,11 +10242,10 @@ static int ipw_tx_skb(struct ipw_priv *priv, struct libipw_txb *txb, txb->fragments[i]->len - hdr_len); tfd->u.data.chunk_ptr[i] = - cpu_to_le32(pci_map_single - (priv->pci_dev, - txb->fragments[i]->data + hdr_len, - txb->fragments[i]->len - hdr_len, - PCI_DMA_TODEVICE)); + cpu_to_le32(dma_map_single(&priv->pci_dev->dev, + txb->fragments[i]->data + hdr_len, + txb->fragments[i]->len - hdr_len, + DMA_TO_DEVICE)); tfd->u.data.chunk_len[i] = cpu_to_le16(txb->fragments[i]->len - hdr_len); } @@ -10273,10 +10275,10 @@ static int ipw_tx_skb(struct ipw_priv *priv, struct libipw_txb *txb, dev_kfree_skb_any(txb->fragments[i]); txb->fragments[i] = skb; tfd->u.data.chunk_ptr[i] = - cpu_to_le32(pci_map_single - (priv->pci_dev, skb->data, - remaining_bytes, - PCI_DMA_TODEVICE)); + cpu_to_le32(dma_map_single(&priv->pci_dev->dev, + skb->data, + remaining_bytes, + DMA_TO_DEVICE)); le32_add_cpu(&tfd->u.data.num_chunks, 1); } @@ -11429,9 +11431,14 @@ static int ipw_wdev_init(struct net_device *dev) set_wiphy_dev(wdev->wiphy, &priv->pci_dev->dev); /* With that information in place, we can now register the wiphy... */ - if (wiphy_register(wdev->wiphy)) - rc = -EIO; + rc = wiphy_register(wdev->wiphy); + if (rc) + goto out; + + return 0; out: + kfree(priv->ieee->a_band.channels); + kfree(priv->ieee->bg_band.channels); return rc; } @@ -11649,9 +11656,9 @@ static int ipw_pci_probe(struct pci_dev *pdev, pci_set_master(pdev); - err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); if (!err) - err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); if (err) { printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n"); goto out_pci_disable_device; diff --git a/drivers/net/wireless/intel/iwlegacy/3945-mac.c b/drivers/net/wireless/intel/iwlegacy/3945-mac.c index b536ec20eaccb189da2d7db667099ef87756e261..d51a23815e18603f9cba9cf7b5d275081c1941ac 100644 --- a/drivers/net/wireless/intel/iwlegacy/3945-mac.c +++ b/drivers/net/wireless/intel/iwlegacy/3945-mac.c @@ -3400,10 +3400,12 @@ static DEVICE_ATTR(dump_errors, 0200, NULL, il3945_dump_error_log); * *****************************************************************************/ -static void +static int il3945_setup_deferred_work(struct il_priv *il) { il->workqueue = create_singlethread_workqueue(DRV_NAME); + if (!il->workqueue) + return -ENOMEM; init_waitqueue_head(&il->wait_command_queue); @@ -3422,6 +3424,8 @@ il3945_setup_deferred_work(struct il_priv *il) tasklet_init(&il->irq_tasklet, il3945_irq_tasklet, (unsigned long)il); + + return 0; } static void @@ -3743,7 +3747,10 @@ il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) } il_set_rxon_channel(il, &il->bands[NL80211_BAND_2GHZ].channels[5]); - il3945_setup_deferred_work(il); + err = il3945_setup_deferred_work(il); + if (err) + goto out_remove_sysfs; + il3945_setup_handlers(il); il_power_initialize(il); @@ -3755,7 +3762,7 @@ il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) err = il3945_setup_mac(il); if (err) - goto out_remove_sysfs; + goto out_destroy_workqueue; err = il_dbgfs_register(il, DRV_NAME); if (err) @@ -3767,9 +3774,10 @@ il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) return 0; -out_remove_sysfs: +out_destroy_workqueue: destroy_workqueue(il->workqueue); il->workqueue = NULL; +out_remove_sysfs: sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group); out_release_irq: free_irq(il->pci_dev->irq, il); diff --git a/drivers/net/wireless/intel/iwlegacy/3945.c b/drivers/net/wireless/intel/iwlegacy/3945.c index 3e568ce2fb20838f090b9aa4716495a9cb51c52f..6703ce95e640e2964bed3c848faed54c57a345b1 100644 --- a/drivers/net/wireless/intel/iwlegacy/3945.c +++ b/drivers/net/wireless/intel/iwlegacy/3945.c @@ -2115,7 +2115,7 @@ il3945_txpower_set_from_eeprom(struct il_priv *il) /* set tx power value for all OFDM rates */ for (rate_idx = 0; rate_idx < IL_OFDM_RATES; rate_idx++) { - s32 uninitialized_var(power_idx); + s32 power_idx; int rc; /* use channel group's clip-power table, diff --git a/drivers/net/wireless/intel/iwlegacy/4965-mac.c b/drivers/net/wireless/intel/iwlegacy/4965-mac.c index 6fc51c74cdb86f9dad7d1575973fd2d462121212..2b60473e7bf9ccb0f4d5556f3e5a8dcf98c43f10 100644 --- a/drivers/net/wireless/intel/iwlegacy/4965-mac.c +++ b/drivers/net/wireless/intel/iwlegacy/4965-mac.c @@ -2784,7 +2784,7 @@ il4965_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb) struct ieee80211_tx_info *info; struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; u32 status = le32_to_cpu(tx_resp->u.status); - int uninitialized_var(tid); + int tid; int sta_id; int freed; u8 *qc = NULL; @@ -6236,10 +6236,12 @@ il4965_bg_txpower_work(struct work_struct *work) mutex_unlock(&il->mutex); } -static void +static int il4965_setup_deferred_work(struct il_priv *il) { il->workqueue = create_singlethread_workqueue(DRV_NAME); + if (!il->workqueue) + return -ENOMEM; init_waitqueue_head(&il->wait_command_queue); @@ -6260,6 +6262,8 @@ il4965_setup_deferred_work(struct il_priv *il) tasklet_init(&il->irq_tasklet, il4965_irq_tasklet, (unsigned long)il); + + return 0; } static void @@ -6649,7 +6653,10 @@ il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) goto out_disable_msi; } - il4965_setup_deferred_work(il); + err = il4965_setup_deferred_work(il); + if (err) + goto out_free_irq; + il4965_setup_handlers(il); /********************************************* @@ -6687,6 +6694,7 @@ il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) out_destroy_workqueue: destroy_workqueue(il->workqueue); il->workqueue = NULL; +out_free_irq: free_irq(il->pci_dev->irq, il); out_disable_msi: pci_disable_msi(il->pci_dev); diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/sta.c b/drivers/net/wireless/intel/iwlwifi/dvm/sta.c index de6ec9b7ace4587f778c2658dc5f7696debd8a4d..f30bac02d32ce921dfae8e30b47fbc2632ad69b2 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/sta.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/sta.c @@ -1101,6 +1101,7 @@ static int iwlagn_send_sta_key(struct iwl_priv *priv, { __le16 key_flags; struct iwl_addsta_cmd sta_cmd; + size_t to_copy; int i; spin_lock_bh(&priv->sta_lock); @@ -1120,7 +1121,9 @@ static int iwlagn_send_sta_key(struct iwl_priv *priv, sta_cmd.key.tkip_rx_tsc_byte2 = tkip_iv32; for (i = 0; i < 5; i++) sta_cmd.key.tkip_rx_ttak[i] = cpu_to_le16(tkip_p1k[i]); - memcpy(sta_cmd.key.key, keyconf->key, keyconf->keylen); + /* keyconf may contain MIC rx/tx keys which iwl does not use */ + to_copy = min_t(size_t, sizeof(sta_cmd.key.key), keyconf->keylen); + memcpy(sta_cmd.key.key, keyconf->key, to_copy); break; case WLAN_CIPHER_SUITE_WEP104: key_flags |= STA_KEY_FLG_KEY_SIZE_MSK; diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c index 05b77419953ce6250f77f573b173b92660d5bc33..9540c874fc38039ce710a3ea49b3dd8af137b569 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c @@ -1835,6 +1835,11 @@ static ssize_t iwl_dbgfs_mem_read(struct file *file, char __user *user_buf, if (ret < 0) return ret; + if (iwl_rx_packet_payload_len(hcmd.resp_pkt) < sizeof(*rsp)) { + ret = -EIO; + goto out; + } + rsp = (void *)hcmd.resp_pkt->data; if (le32_to_cpu(rsp->status) != DEBUG_MEM_STATUS_SUCCESS) { ret = -ENXIO; @@ -1912,6 +1917,11 @@ static ssize_t iwl_dbgfs_mem_write(struct file *file, if (ret < 0) return ret; + if (iwl_rx_packet_payload_len(hcmd.resp_pkt) < sizeof(*rsp)) { + ret = -EIO; + goto out; + } + rsp = (void *)hcmd.resp_pkt->data; if (rsp->status != DEBUG_MEM_STATUS_SUCCESS) { ret = -ENXIO; diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/sta.c b/drivers/net/wireless/intel/iwlwifi/mvm/sta.c index 373ace38edab7bbbd467287b0d6556698e5fe434..83883ce7f55dc1873485d0df41594da9b6c6851a 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/sta.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/sta.c @@ -2237,7 +2237,7 @@ int iwl_mvm_sta_rx_agg(struct iwl_mvm *mvm, struct ieee80211_sta *sta, } if (iwl_mvm_has_new_rx_api(mvm) && start) { - u16 reorder_buf_size = buf_size * sizeof(baid_data->entries[0]); + u32 reorder_buf_size = buf_size * sizeof(baid_data->entries[0]); /* sparse doesn't like the __align() so don't check */ #ifndef __CHECKER__ diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c index 2d2afc1758304f947dd0e75566b8facf35e04140..c69c13e762bbe6dd12e85f4b01780e851fbf4dd8 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c @@ -666,7 +666,6 @@ static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) { int ret; - int t = 0; int iter; IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); @@ -681,6 +680,8 @@ int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) usleep_range(1000, 2000); for (iter = 0; iter < 10; iter++) { + int t = 0; + /* If HW is not ready, prepare the conditions to check again */ iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE); diff --git a/drivers/net/wireless/intersil/orinoco/hw.c b/drivers/net/wireless/intersil/orinoco/hw.c index 61af5a28f269fd562ffceb1eea1a01122a080b73..af49aa421e47f00b66fba554ba4c0b4e0f6dcec9 100644 --- a/drivers/net/wireless/intersil/orinoco/hw.c +++ b/drivers/net/wireless/intersil/orinoco/hw.c @@ -931,6 +931,8 @@ int __orinoco_hw_setup_enc(struct orinoco_private *priv) err = hermes_write_wordrec(hw, USER_BAP, HERMES_RID_CNFAUTHENTICATION_AGERE, auth_flag); + if (err) + return err; } err = hermes_write_wordrec(hw, USER_BAP, HERMES_RID_CNFWEPENABLED_AGERE, diff --git a/drivers/net/wireless/intersil/orinoco/orinoco_cs.c b/drivers/net/wireless/intersil/orinoco/orinoco_cs.c index a956f965a1e5ec77e19c03e86ec87dc810461315..03bfd2482656c09143249928c3bf74a7edca5a1e 100644 --- a/drivers/net/wireless/intersil/orinoco/orinoco_cs.c +++ b/drivers/net/wireless/intersil/orinoco/orinoco_cs.c @@ -96,6 +96,7 @@ orinoco_cs_probe(struct pcmcia_device *link) { struct orinoco_private *priv; struct orinoco_pccard *card; + int ret; priv = alloc_orinocodev(sizeof(*card), &link->dev, orinoco_cs_hard_reset, NULL); @@ -107,8 +108,16 @@ orinoco_cs_probe(struct pcmcia_device *link) card->p_dev = link; link->priv = priv; - return orinoco_cs_config(link); -} /* orinoco_cs_attach */ + ret = orinoco_cs_config(link); + if (ret) + goto err_free_orinocodev; + + return 0; + +err_free_orinocodev: + free_orinocodev(priv); + return ret; +} static void orinoco_cs_detach(struct pcmcia_device *link) { diff --git a/drivers/net/wireless/intersil/orinoco/spectrum_cs.c b/drivers/net/wireless/intersil/orinoco/spectrum_cs.c index b60048c95e0a852863f3e2f541bc283fd263f9ab..011c86e55923e6d4c805cf893e45f42118dc6213 100644 --- a/drivers/net/wireless/intersil/orinoco/spectrum_cs.c +++ b/drivers/net/wireless/intersil/orinoco/spectrum_cs.c @@ -157,6 +157,7 @@ spectrum_cs_probe(struct pcmcia_device *link) { struct orinoco_private *priv; struct orinoco_pccard *card; + int ret; priv = alloc_orinocodev(sizeof(*card), &link->dev, spectrum_cs_hard_reset, @@ -169,8 +170,16 @@ spectrum_cs_probe(struct pcmcia_device *link) card->p_dev = link; link->priv = priv; - return spectrum_cs_config(link); -} /* spectrum_cs_attach */ + ret = spectrum_cs_config(link); + if (ret) + goto err_free_orinocodev; + + return 0; + +err_free_orinocodev: + free_orinocodev(priv); + return ret; +} static void spectrum_cs_detach(struct pcmcia_device *link) { diff --git a/drivers/net/wireless/marvell/libertas/cmdresp.c b/drivers/net/wireless/marvell/libertas/cmdresp.c index b73d083813985a36d9858106e9d690d52177fa4c..5908f07d62ed745bd91158d388adb95d0670d2fd 100644 --- a/drivers/net/wireless/marvell/libertas/cmdresp.c +++ b/drivers/net/wireless/marvell/libertas/cmdresp.c @@ -48,7 +48,7 @@ void lbs_mac_event_disconnected(struct lbs_private *priv, /* Free Tx and Rx packets */ spin_lock_irqsave(&priv->driver_lock, flags); - kfree_skb(priv->currenttxskb); + dev_kfree_skb_irq(priv->currenttxskb); priv->currenttxskb = NULL; priv->tx_pending_len = 0; spin_unlock_irqrestore(&priv->driver_lock, flags); diff --git a/drivers/net/wireless/marvell/libertas/if_usb.c b/drivers/net/wireless/marvell/libertas/if_usb.c index d75763410cdc18aa838a5c7b6850b582a649d01a..885abbd665e6e7f36000409e5cdda46bda1fa491 100644 --- a/drivers/net/wireless/marvell/libertas/if_usb.c +++ b/drivers/net/wireless/marvell/libertas/if_usb.c @@ -633,7 +633,7 @@ static inline void process_cmdrequest(int recvlength, uint8_t *recvbuff, priv->resp_len[i] = (recvlength - MESSAGE_HEADER_LEN); memcpy(priv->resp_buf[i], recvbuff + MESSAGE_HEADER_LEN, priv->resp_len[i]); - kfree_skb(skb); + dev_kfree_skb_irq(skb); lbs_notify_command_response(priv, i); spin_unlock_irqrestore(&priv->driver_lock, flags); diff --git a/drivers/net/wireless/marvell/libertas/main.c b/drivers/net/wireless/marvell/libertas/main.c index f22e1c220cba13cb5f0968bf2552d3a7dcf72e25..997c246b971e76b5b038a58ab9d10f5837fdefcb 100644 --- a/drivers/net/wireless/marvell/libertas/main.c +++ b/drivers/net/wireless/marvell/libertas/main.c @@ -216,7 +216,7 @@ int lbs_stop_iface(struct lbs_private *priv) spin_lock_irqsave(&priv->driver_lock, flags); priv->iface_running = false; - kfree_skb(priv->currenttxskb); + dev_kfree_skb_irq(priv->currenttxskb); priv->currenttxskb = NULL; priv->tx_pending_len = 0; spin_unlock_irqrestore(&priv->driver_lock, flags); @@ -869,6 +869,7 @@ static int lbs_init_adapter(struct lbs_private *priv) ret = kfifo_alloc(&priv->event_fifo, sizeof(u32) * 16, GFP_KERNEL); if (ret) { pr_err("Out of memory allocating event FIFO buffer\n"); + lbs_free_cmd_buffer(priv); goto out; } diff --git a/drivers/net/wireless/marvell/libertas_tf/if_usb.c b/drivers/net/wireless/marvell/libertas_tf/if_usb.c index 60941c319b4219e5c56fe4ab7e3778aaa70321ab..5e7edc0309751ed6bb191776d47d7bdccbf52b77 100644 --- a/drivers/net/wireless/marvell/libertas_tf/if_usb.c +++ b/drivers/net/wireless/marvell/libertas_tf/if_usb.c @@ -616,7 +616,7 @@ static inline void process_cmdrequest(int recvlength, uint8_t *recvbuff, spin_lock_irqsave(&priv->driver_lock, flags); memcpy(priv->cmd_resp_buff, recvbuff + MESSAGE_HEADER_LEN, recvlength - MESSAGE_HEADER_LEN); - kfree_skb(skb); + dev_kfree_skb_irq(skb); lbtf_cmd_response_rx(priv); spin_unlock_irqrestore(&priv->driver_lock, flags); } diff --git a/drivers/net/wireless/marvell/mwifiex/11n.c b/drivers/net/wireless/marvell/mwifiex/11n.c index 5dcc305cc812710b892eb429b6468ca08181c072..452ac56cdc923755096cfe5ee379450a1d0804b0 100644 --- a/drivers/net/wireless/marvell/mwifiex/11n.c +++ b/drivers/net/wireless/marvell/mwifiex/11n.c @@ -901,7 +901,7 @@ mwifiex_send_delba_txbastream_tbl(struct mwifiex_private *priv, u8 tid) */ void mwifiex_update_ampdu_txwinsize(struct mwifiex_adapter *adapter) { - u8 i; + u8 i, j; u32 tx_win_size; struct mwifiex_private *priv; @@ -932,8 +932,8 @@ void mwifiex_update_ampdu_txwinsize(struct mwifiex_adapter *adapter) if (tx_win_size != priv->add_ba_param.tx_win_size) { if (!priv->media_connected) continue; - for (i = 0; i < MAX_NUM_TID; i++) - mwifiex_send_delba_txbastream_tbl(priv, i); + for (j = 0; j < MAX_NUM_TID; j++) + mwifiex_send_delba_txbastream_tbl(priv, j); } } } diff --git a/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c b/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c index 5380fba652cc49ff2a2aef2528b35e674b8f1a4a..1aa0bcdab8ef4a12fd55681583482aaf54b66aa1 100644 --- a/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c +++ b/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c @@ -986,8 +986,8 @@ void mwifiex_11n_rxba_sync_event(struct mwifiex_private *priv, } } - tlv_buf_left -= (sizeof(*tlv_rxba) + tlv_len); - tmp = (u8 *)tlv_rxba + tlv_len + sizeof(*tlv_rxba); + tlv_buf_left -= (sizeof(tlv_rxba->header) + tlv_len); + tmp = (u8 *)tlv_rxba + sizeof(tlv_rxba->header) + tlv_len; tlv_rxba = (struct mwifiex_ie_types_rxba_sync *)tmp; } } diff --git a/drivers/net/wireless/marvell/mwifiex/debugfs.c b/drivers/net/wireless/marvell/mwifiex/debugfs.c index cbe4493b32664cba530fc97d744e560dc1934224..0f62da50e11a201d47e91d3acda78a3822704fba 100644 --- a/drivers/net/wireless/marvell/mwifiex/debugfs.c +++ b/drivers/net/wireless/marvell/mwifiex/debugfs.c @@ -265,8 +265,11 @@ mwifiex_histogram_read(struct file *file, char __user *ubuf, if (!p) return -ENOMEM; - if (!priv || !priv->hist_data) - return -EFAULT; + if (!priv || !priv->hist_data) { + ret = -EFAULT; + goto free_and_exit; + } + phist_data = priv->hist_data; p += sprintf(p, "\n" @@ -321,6 +324,8 @@ mwifiex_histogram_read(struct file *file, char __user *ubuf, ret = simple_read_from_buffer(ubuf, count, ppos, (char *)page, (unsigned long)p - page); +free_and_exit: + free_page(page); return ret; } diff --git a/drivers/net/wireless/marvell/mwifiex/pcie.c b/drivers/net/wireless/marvell/mwifiex/pcie.c index aea79fd54c3112203564e7e417f7b058f70ea6f6..7e9111965b233ab4610c5999bafe7cbb83ec333d 100644 --- a/drivers/net/wireless/marvell/mwifiex/pcie.c +++ b/drivers/net/wireless/marvell/mwifiex/pcie.c @@ -50,6 +50,8 @@ static int mwifiex_pcie_probe_of(struct device *dev) } static void mwifiex_pcie_work(struct work_struct *work); +static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter); +static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter); static int mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb, @@ -58,8 +60,8 @@ mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb, struct pcie_service_card *card = adapter->card; struct mwifiex_dma_mapping mapping; - mapping.addr = pci_map_single(card->dev, skb->data, size, flags); - if (pci_dma_mapping_error(card->dev, mapping.addr)) { + mapping.addr = dma_map_single(&card->dev->dev, skb->data, size, flags); + if (dma_mapping_error(&card->dev->dev, mapping.addr)) { mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n"); return -1; } @@ -75,7 +77,7 @@ static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter, struct mwifiex_dma_mapping mapping; mwifiex_get_mapping(skb, &mapping); - pci_unmap_single(card->dev, mapping.addr, mapping.len, flags); + dma_unmap_single(&card->dev->dev, mapping.addr, mapping.len, flags); } /* @@ -469,10 +471,9 @@ static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter, struct sk_buff *cmdrsp = card->cmdrsp_buf; for (count = 0; count < max_delay_loop_cnt; count++) { - pci_dma_sync_single_for_cpu(card->dev, - MWIFIEX_SKB_DMA_ADDR(cmdrsp), - sizeof(sleep_cookie), - PCI_DMA_FROMDEVICE); + dma_sync_single_for_cpu(&card->dev->dev, + MWIFIEX_SKB_DMA_ADDR(cmdrsp), + sizeof(sleep_cookie), DMA_FROM_DEVICE); buffer = cmdrsp->data; sleep_cookie = get_unaligned_le32(buffer); @@ -481,10 +482,10 @@ static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter, "sleep cookie found at count %d\n", count); break; } - pci_dma_sync_single_for_device(card->dev, - MWIFIEX_SKB_DMA_ADDR(cmdrsp), - sizeof(sleep_cookie), - PCI_DMA_FROMDEVICE); + dma_sync_single_for_device(&card->dev->dev, + MWIFIEX_SKB_DMA_ADDR(cmdrsp), + sizeof(sleep_cookie), + DMA_FROM_DEVICE); usleep_range(20, 30); } @@ -632,14 +633,15 @@ static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter) if (!skb) { mwifiex_dbg(adapter, ERROR, "Unable to allocate skb for RX ring.\n"); - kfree(card->rxbd_ring_vbase); return -ENOMEM; } if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_RX_DATA_BUF_SIZE, - PCI_DMA_FROMDEVICE)) - return -1; + DMA_FROM_DEVICE)) { + kfree_skb(skb); + return -ENOMEM; + } buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); @@ -689,16 +691,14 @@ static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter) if (!skb) { mwifiex_dbg(adapter, ERROR, "Unable to allocate skb for EVENT buf.\n"); - kfree(card->evtbd_ring_vbase); return -ENOMEM; } skb_put(skb, MAX_EVENT_SIZE); if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE, - PCI_DMA_FROMDEVICE)) { + DMA_FROM_DEVICE)) { kfree_skb(skb); - kfree(card->evtbd_ring_vbase); - return -1; + return -ENOMEM; } buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); @@ -738,7 +738,7 @@ static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter) if (card->tx_buf_list[i]) { skb = card->tx_buf_list[i]; mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); dev_kfree_skb_any(skb); } memset(desc2, 0, sizeof(*desc2)); @@ -747,7 +747,7 @@ static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter) if (card->tx_buf_list[i]) { skb = card->tx_buf_list[i]; mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); dev_kfree_skb_any(skb); } memset(desc, 0, sizeof(*desc)); @@ -777,7 +777,7 @@ static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter) if (card->rx_buf_list[i]) { skb = card->rx_buf_list[i]; mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); dev_kfree_skb_any(skb); } memset(desc2, 0, sizeof(*desc2)); @@ -786,7 +786,7 @@ static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter) if (card->rx_buf_list[i]) { skb = card->rx_buf_list[i]; mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); dev_kfree_skb_any(skb); } memset(desc, 0, sizeof(*desc)); @@ -812,7 +812,7 @@ static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter) if (card->evt_buf_list[i]) { skb = card->evt_buf_list[i]; mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); dev_kfree_skb_any(skb); } card->evt_buf_list[i] = NULL; @@ -853,9 +853,10 @@ static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter) mwifiex_dbg(adapter, INFO, "info: txbd_ring: Allocating %d bytes\n", card->txbd_ring_size); - card->txbd_ring_vbase = pci_alloc_consistent(card->dev, - card->txbd_ring_size, - &card->txbd_ring_pbase); + card->txbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, + card->txbd_ring_size, + &card->txbd_ring_pbase, + GFP_KERNEL); if (!card->txbd_ring_vbase) { mwifiex_dbg(adapter, ERROR, "allocate consistent memory (%d bytes) failed!\n", @@ -879,9 +880,9 @@ static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter) mwifiex_cleanup_txq_ring(adapter); if (card->txbd_ring_vbase) - pci_free_consistent(card->dev, card->txbd_ring_size, - card->txbd_ring_vbase, - card->txbd_ring_pbase); + dma_free_coherent(&card->dev->dev, card->txbd_ring_size, + card->txbd_ring_vbase, + card->txbd_ring_pbase); card->txbd_ring_size = 0; card->txbd_wrptr = 0; card->txbd_rdptr = 0 | reg->tx_rollover_ind; @@ -896,6 +897,7 @@ static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter) */ static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter) { + int ret; struct pcie_service_card *card = adapter->card; const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; @@ -917,9 +919,10 @@ static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter) mwifiex_dbg(adapter, INFO, "info: rxbd_ring: Allocating %d bytes\n", card->rxbd_ring_size); - card->rxbd_ring_vbase = pci_alloc_consistent(card->dev, - card->rxbd_ring_size, - &card->rxbd_ring_pbase); + card->rxbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, + card->rxbd_ring_size, + &card->rxbd_ring_pbase, + GFP_KERNEL); if (!card->rxbd_ring_vbase) { mwifiex_dbg(adapter, ERROR, "allocate consistent memory (%d bytes) failed!\n", @@ -933,7 +936,10 @@ static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter) (u32)((u64)card->rxbd_ring_pbase >> 32), card->rxbd_ring_size); - return mwifiex_init_rxq_ring(adapter); + ret = mwifiex_init_rxq_ring(adapter); + if (ret) + mwifiex_pcie_delete_rxbd_ring(adapter); + return ret; } /* @@ -947,9 +953,9 @@ static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter) mwifiex_cleanup_rxq_ring(adapter); if (card->rxbd_ring_vbase) - pci_free_consistent(card->dev, card->rxbd_ring_size, - card->rxbd_ring_vbase, - card->rxbd_ring_pbase); + dma_free_coherent(&card->dev->dev, card->rxbd_ring_size, + card->rxbd_ring_vbase, + card->rxbd_ring_pbase); card->rxbd_ring_size = 0; card->rxbd_wrptr = 0; card->rxbd_rdptr = 0 | reg->rx_rollover_ind; @@ -964,6 +970,7 @@ static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter) */ static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter) { + int ret; struct pcie_service_card *card = adapter->card; const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; @@ -981,9 +988,10 @@ static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter) mwifiex_dbg(adapter, INFO, "info: evtbd_ring: Allocating %d bytes\n", card->evtbd_ring_size); - card->evtbd_ring_vbase = pci_alloc_consistent(card->dev, - card->evtbd_ring_size, - &card->evtbd_ring_pbase); + card->evtbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, + card->evtbd_ring_size, + &card->evtbd_ring_pbase, + GFP_KERNEL); if (!card->evtbd_ring_vbase) { mwifiex_dbg(adapter, ERROR, "allocate consistent memory (%d bytes) failed!\n", @@ -997,7 +1005,10 @@ static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter) (u32)((u64)card->evtbd_ring_pbase >> 32), card->evtbd_ring_size); - return mwifiex_pcie_init_evt_ring(adapter); + ret = mwifiex_pcie_init_evt_ring(adapter); + if (ret) + mwifiex_pcie_delete_evtbd_ring(adapter); + return ret; } /* @@ -1011,9 +1022,9 @@ static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter) mwifiex_cleanup_evt_ring(adapter); if (card->evtbd_ring_vbase) - pci_free_consistent(card->dev, card->evtbd_ring_size, - card->evtbd_ring_vbase, - card->evtbd_ring_pbase); + dma_free_coherent(&card->dev->dev, card->evtbd_ring_size, + card->evtbd_ring_vbase, + card->evtbd_ring_pbase); card->evtbd_wrptr = 0; card->evtbd_rdptr = 0 | reg->evt_rollover_ind; card->evtbd_ring_size = 0; @@ -1040,7 +1051,7 @@ static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter) } skb_put(skb, MWIFIEX_UPLD_SIZE); if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, - PCI_DMA_FROMDEVICE)) { + DMA_FROM_DEVICE)) { kfree_skb(skb); return -1; } @@ -1064,14 +1075,14 @@ static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter) if (card && card->cmdrsp_buf) { mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); dev_kfree_skb_any(card->cmdrsp_buf); card->cmdrsp_buf = NULL; } if (card && card->cmd_buf) { mwifiex_unmap_pci_memory(adapter, card->cmd_buf, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); dev_kfree_skb_any(card->cmd_buf); card->cmd_buf = NULL; } @@ -1086,8 +1097,10 @@ static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter) struct pcie_service_card *card = adapter->card; u32 *cookie; - card->sleep_cookie_vbase = pci_alloc_consistent(card->dev, sizeof(u32), - &card->sleep_cookie_pbase); + card->sleep_cookie_vbase = dma_alloc_coherent(&card->dev->dev, + sizeof(u32), + &card->sleep_cookie_pbase, + GFP_KERNEL); if (!card->sleep_cookie_vbase) { mwifiex_dbg(adapter, ERROR, "pci_alloc_consistent failed!\n"); @@ -1115,9 +1128,9 @@ static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter) card = adapter->card; if (card && card->sleep_cookie_vbase) { - pci_free_consistent(card->dev, sizeof(u32), - card->sleep_cookie_vbase, - card->sleep_cookie_pbase); + dma_free_coherent(&card->dev->dev, sizeof(u32), + card->sleep_cookie_vbase, + card->sleep_cookie_pbase); card->sleep_cookie_vbase = NULL; } @@ -1189,7 +1202,7 @@ static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter) "SEND COMP: Detach skb %p at txbd_rdidx=%d\n", skb, wrdoneidx); mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); unmap_count++; @@ -1282,7 +1295,7 @@ mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb, put_unaligned_le16(MWIFIEX_TYPE_DATA, payload + 2); if (mwifiex_map_pci_memory(adapter, skb, skb->len, - PCI_DMA_TODEVICE)) + DMA_TO_DEVICE)) return -1; wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr; @@ -1372,7 +1385,7 @@ mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb, return -EINPROGRESS; done_unmap: - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); card->tx_buf_list[wrindx] = NULL; atomic_dec(&adapter->tx_hw_pending); if (reg->pfu_enabled) @@ -1426,7 +1439,7 @@ static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter) if (!skb_data) return -ENOMEM; - mwifiex_unmap_pci_memory(adapter, skb_data, PCI_DMA_FROMDEVICE); + mwifiex_unmap_pci_memory(adapter, skb_data, DMA_FROM_DEVICE); card->rx_buf_list[rd_index] = NULL; /* Get data length from interface header - @@ -1464,7 +1477,7 @@ static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter) if (mwifiex_map_pci_memory(adapter, skb_tmp, MWIFIEX_RX_DATA_BUF_SIZE, - PCI_DMA_FROMDEVICE)) + DMA_FROM_DEVICE)) return -1; buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp); @@ -1541,7 +1554,7 @@ mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) return -1; } - if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE)) + if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE)) return -1; buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); @@ -1553,7 +1566,7 @@ mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) mwifiex_dbg(adapter, ERROR, "%s: failed to write download command to boot code.\n", __func__); - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); return -1; } @@ -1565,7 +1578,7 @@ mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) mwifiex_dbg(adapter, ERROR, "%s: failed to write download command to boot code.\n", __func__); - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); return -1; } @@ -1574,7 +1587,7 @@ mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) mwifiex_dbg(adapter, ERROR, "%s: failed to write command len to cmd_size scratch reg\n", __func__); - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); return -1; } @@ -1583,7 +1596,7 @@ mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) CPU_INTR_DOOR_BELL)) { mwifiex_dbg(adapter, ERROR, "%s: failed to assert door-bell intr\n", __func__); - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); return -1; } @@ -1642,7 +1655,7 @@ mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) put_unaligned_le16((u16)skb->len, &payload[0]); put_unaligned_le16(MWIFIEX_TYPE_CMD, &payload[2]); - if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE)) + if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE)) return -1; card->cmd_buf = skb; @@ -1742,17 +1755,16 @@ static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) "info: Rx CMD Response\n"); if (adapter->curr_cmd) - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_FROMDEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_FROM_DEVICE); else - pci_dma_sync_single_for_cpu(card->dev, - MWIFIEX_SKB_DMA_ADDR(skb), - MWIFIEX_UPLD_SIZE, - PCI_DMA_FROMDEVICE); + dma_sync_single_for_cpu(&card->dev->dev, + MWIFIEX_SKB_DMA_ADDR(skb), + MWIFIEX_UPLD_SIZE, DMA_FROM_DEVICE); /* Unmap the command as a response has been received. */ if (card->cmd_buf) { mwifiex_unmap_pci_memory(adapter, card->cmd_buf, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); dev_kfree_skb_any(card->cmd_buf); card->cmd_buf = NULL; } @@ -1763,10 +1775,10 @@ static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) if (!adapter->curr_cmd) { if (adapter->ps_state == PS_STATE_SLEEP_CFM) { - pci_dma_sync_single_for_device(card->dev, - MWIFIEX_SKB_DMA_ADDR(skb), - MWIFIEX_SLEEP_COOKIE_SIZE, - PCI_DMA_FROMDEVICE); + dma_sync_single_for_device(&card->dev->dev, + MWIFIEX_SKB_DMA_ADDR(skb), + MWIFIEX_SLEEP_COOKIE_SIZE, + DMA_FROM_DEVICE); if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, CPU_INTR_SLEEP_CFM_DONE)) { @@ -1777,7 +1789,7 @@ static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) mwifiex_delay_for_sleep_cookie(adapter, MWIFIEX_MAX_DELAY_COUNT); mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); skb_pull(skb, adapter->intf_hdr_len); while (reg->sleep_cookie && (count++ < 10) && mwifiex_pcie_ok_to_access_hw(adapter)) @@ -1793,7 +1805,7 @@ static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len)); skb_push(skb, adapter->intf_hdr_len); if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, - PCI_DMA_FROMDEVICE)) + DMA_FROM_DEVICE)) return -1; } else if (mwifiex_pcie_ok_to_access_hw(adapter)) { skb_pull(skb, adapter->intf_hdr_len); @@ -1835,7 +1847,7 @@ static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter, card->cmdrsp_buf = skb; skb_push(card->cmdrsp_buf, adapter->intf_hdr_len); if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, - PCI_DMA_FROMDEVICE)) + DMA_FROM_DEVICE)) return -1; } @@ -1890,7 +1902,7 @@ static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter) mwifiex_dbg(adapter, INFO, "info: Read Index: %d\n", rdptr); skb_cmd = card->evt_buf_list[rdptr]; - mwifiex_unmap_pci_memory(adapter, skb_cmd, PCI_DMA_FROMDEVICE); + mwifiex_unmap_pci_memory(adapter, skb_cmd, DMA_FROM_DEVICE); /* Take the pointer and set it to event pointer in adapter and will return back after event handling callback */ @@ -1970,7 +1982,7 @@ static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter, skb_put(skb, MAX_EVENT_SIZE - skb->len); if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE, - PCI_DMA_FROMDEVICE)) + DMA_FROM_DEVICE)) return -1; card->evt_buf_list[rdptr] = skb; desc = card->evtbd_ring[rdptr]; @@ -2252,7 +2264,7 @@ static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter, "interrupt status during fw dnld.\n", __func__); mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); ret = -1; goto done; } @@ -2264,12 +2276,12 @@ static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter, mwifiex_dbg(adapter, ERROR, "%s: Card failed to ACK download\n", __func__); mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); ret = -1; goto done; } - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); offset += txlen; } while (true); @@ -2939,14 +2951,13 @@ static int mwifiex_init_pcie(struct mwifiex_adapter *adapter) pci_set_master(pdev); - pr_notice("try set_consistent_dma_mask(32)\n"); - ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); if (ret) { - pr_err("set_dma_mask(32) failed\n"); + pr_err("set_dma_mask(32) failed: %d\n", ret); goto err_set_dma_mask; } - ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); if (ret) { pr_err("set_consistent_dma_mask(64) failed\n"); goto err_set_dma_mask; diff --git a/drivers/net/wireless/marvell/mwifiex/scan.c b/drivers/net/wireless/marvell/mwifiex/scan.c index c9f6cd2919699ac19f05da1a2d4dc91340b47c82..4f0e78ae3dbd0c8ae3352f293c9dd7aecec79342 100644 --- a/drivers/net/wireless/marvell/mwifiex/scan.c +++ b/drivers/net/wireless/marvell/mwifiex/scan.c @@ -2208,9 +2208,9 @@ int mwifiex_ret_802_11_scan(struct mwifiex_private *priv, if (nd_config) { adapter->nd_info = - kzalloc(sizeof(struct cfg80211_wowlan_nd_match) + - sizeof(struct cfg80211_wowlan_nd_match *) * - scan_rsp->number_of_sets, GFP_ATOMIC); + kzalloc(struct_size(adapter->nd_info, matches, + scan_rsp->number_of_sets), + GFP_ATOMIC); if (adapter->nd_info) adapter->nd_info->n_matches = scan_rsp->number_of_sets; diff --git a/drivers/net/wireless/marvell/mwifiex/sta_rx.c b/drivers/net/wireless/marvell/mwifiex/sta_rx.c index 00fcbda09349e76533b9faa6b2cde3c246bea6f6..346e91b9f2ad7bfe4d7bebbb427b956a973cf133 100644 --- a/drivers/net/wireless/marvell/mwifiex/sta_rx.c +++ b/drivers/net/wireless/marvell/mwifiex/sta_rx.c @@ -98,12 +98,23 @@ int mwifiex_process_rx_packet(struct mwifiex_private *priv, rx_pkt_len = le16_to_cpu(local_rx_pd->rx_pkt_length); rx_pkt_hdr = (void *)local_rx_pd + rx_pkt_off; - if ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header, - sizeof(bridge_tunnel_header))) || - (!memcmp(&rx_pkt_hdr->rfc1042_hdr, rfc1042_header, - sizeof(rfc1042_header)) && - ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_AARP && - ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_IPX)) { + if (sizeof(rx_pkt_hdr->eth803_hdr) + sizeof(rfc1042_header) + + rx_pkt_off > skb->len) { + mwifiex_dbg(priv->adapter, ERROR, + "wrong rx packet offset: len=%d, rx_pkt_off=%d\n", + skb->len, rx_pkt_off); + priv->stats.rx_dropped++; + dev_kfree_skb_any(skb); + return -1; + } + + if (sizeof(*rx_pkt_hdr) + rx_pkt_off <= skb->len && + ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header, + sizeof(bridge_tunnel_header))) || + (!memcmp(&rx_pkt_hdr->rfc1042_hdr, rfc1042_header, + sizeof(rfc1042_header)) && + ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_AARP && + ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_IPX))) { /* * Replace the 803 header and rfc1042 header (llc/snap) with an * EthernetII header, keep the src/dst and snap_type @@ -203,7 +214,8 @@ int mwifiex_process_sta_rx_packet(struct mwifiex_private *priv, rx_pkt_hdr = (void *)local_rx_pd + rx_pkt_offset; - if ((rx_pkt_offset + rx_pkt_length) > (u16) skb->len) { + if ((rx_pkt_offset + rx_pkt_length) > skb->len || + sizeof(rx_pkt_hdr->eth803_hdr) + rx_pkt_offset > skb->len) { mwifiex_dbg(adapter, ERROR, "wrong rx packet: len=%d, rx_pkt_offset=%d, rx_pkt_length=%d\n", skb->len, rx_pkt_offset, rx_pkt_length); diff --git a/drivers/net/wireless/marvell/mwifiex/tdls.c b/drivers/net/wireless/marvell/mwifiex/tdls.c index b6b7bbe168ebcb15fb8fda8032e65474dd033818..12cfc95f0259873d7cb11d6dc255bcf70d55df14 100644 --- a/drivers/net/wireless/marvell/mwifiex/tdls.c +++ b/drivers/net/wireless/marvell/mwifiex/tdls.c @@ -737,6 +737,7 @@ mwifiex_construct_tdls_action_frame(struct mwifiex_private *priv, int ret; u16 capab; struct ieee80211_ht_cap *ht_cap; + unsigned int extra; u8 radio, *pos; capab = priv->curr_bss_params.bss_descriptor.cap_info_bitmap; @@ -755,7 +756,10 @@ mwifiex_construct_tdls_action_frame(struct mwifiex_private *priv, switch (action_code) { case WLAN_PUB_ACTION_TDLS_DISCOVER_RES: - skb_put(skb, sizeof(mgmt->u.action.u.tdls_discover_resp) + 1); + /* See the layout of 'struct ieee80211_mgmt'. */ + extra = sizeof(mgmt->u.action.u.tdls_discover_resp) + + sizeof(mgmt->u.action.category); + skb_put(skb, extra); mgmt->u.action.category = WLAN_CATEGORY_PUBLIC; mgmt->u.action.u.tdls_discover_resp.action_code = WLAN_PUB_ACTION_TDLS_DISCOVER_RES; @@ -764,8 +768,7 @@ mwifiex_construct_tdls_action_frame(struct mwifiex_private *priv, mgmt->u.action.u.tdls_discover_resp.capability = cpu_to_le16(capab); /* move back for addr4 */ - memmove(pos + ETH_ALEN, &mgmt->u.action.category, - sizeof(mgmt->u.action.u.tdls_discover_resp)); + memmove(pos + ETH_ALEN, &mgmt->u.action, extra); /* init address 4 */ memcpy(pos, bc_addr, ETH_ALEN); diff --git a/drivers/net/wireless/marvell/mwifiex/uap_txrx.c b/drivers/net/wireless/marvell/mwifiex/uap_txrx.c index 5ce85d5727e4b882ebc37372f03bb49003d1a0c9..987057af00fb30804fcdbc8986edfc29662d0bba 100644 --- a/drivers/net/wireless/marvell/mwifiex/uap_txrx.c +++ b/drivers/net/wireless/marvell/mwifiex/uap_txrx.c @@ -116,6 +116,16 @@ static void mwifiex_uap_queue_bridged_pkt(struct mwifiex_private *priv, return; } + if (sizeof(*rx_pkt_hdr) + + le16_to_cpu(uap_rx_pd->rx_pkt_offset) > skb->len) { + mwifiex_dbg(adapter, ERROR, + "wrong rx packet offset: len=%d,rx_pkt_offset=%d\n", + skb->len, le16_to_cpu(uap_rx_pd->rx_pkt_offset)); + priv->stats.rx_dropped++; + dev_kfree_skb_any(skb); + return; + } + if ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header, sizeof(bridge_tunnel_header))) || (!memcmp(&rx_pkt_hdr->rfc1042_hdr, rfc1042_header, @@ -256,7 +266,15 @@ int mwifiex_handle_uap_rx_forward(struct mwifiex_private *priv, if (is_multicast_ether_addr(ra)) { skb_uap = skb_copy(skb, GFP_ATOMIC); - mwifiex_uap_queue_bridged_pkt(priv, skb_uap); + if (likely(skb_uap)) { + mwifiex_uap_queue_bridged_pkt(priv, skb_uap); + } else { + mwifiex_dbg(adapter, ERROR, + "failed to copy skb for uAP\n"); + priv->stats.rx_dropped++; + dev_kfree_skb_any(skb); + return -1; + } } else { if (mwifiex_get_sta_entry(priv, ra)) { /* Requeue Intra-BSS packet */ @@ -385,6 +403,16 @@ int mwifiex_process_uap_rx_packet(struct mwifiex_private *priv, rx_pkt_type = le16_to_cpu(uap_rx_pd->rx_pkt_type); rx_pkt_hdr = (void *)uap_rx_pd + le16_to_cpu(uap_rx_pd->rx_pkt_offset); + if (le16_to_cpu(uap_rx_pd->rx_pkt_offset) + + sizeof(rx_pkt_hdr->eth803_hdr) > skb->len) { + mwifiex_dbg(adapter, ERROR, + "wrong rx packet for struct ethhdr: len=%d, offset=%d\n", + skb->len, le16_to_cpu(uap_rx_pd->rx_pkt_offset)); + priv->stats.rx_dropped++; + dev_kfree_skb_any(skb); + return 0; + } + ether_addr_copy(ta, rx_pkt_hdr->eth803_hdr.h_source); if ((le16_to_cpu(uap_rx_pd->rx_pkt_offset) + diff --git a/drivers/net/wireless/marvell/mwifiex/util.c b/drivers/net/wireless/marvell/mwifiex/util.c index f9b71539d33e684963ed2cdc65d14c9feee9b8c8..c45f72779d08a1b8dd6d84348244407ad07ee5be 100644 --- a/drivers/net/wireless/marvell/mwifiex/util.c +++ b/drivers/net/wireless/marvell/mwifiex/util.c @@ -405,11 +405,15 @@ mwifiex_process_mgmt_packet(struct mwifiex_private *priv, } rx_pd = (struct rxpd *)skb->data; + pkt_len = le16_to_cpu(rx_pd->rx_pkt_length); + if (pkt_len < sizeof(struct ieee80211_hdr) + sizeof(pkt_len)) { + mwifiex_dbg(priv->adapter, ERROR, "invalid rx_pkt_length"); + return -1; + } skb_pull(skb, le16_to_cpu(rx_pd->rx_pkt_offset)); skb_pull(skb, sizeof(pkt_len)); - - pkt_len = le16_to_cpu(rx_pd->rx_pkt_length); + pkt_len -= sizeof(pkt_len); ieee_hdr = (void *)skb->data; if (ieee80211_is_mgmt(ieee_hdr->frame_control)) { @@ -422,7 +426,7 @@ mwifiex_process_mgmt_packet(struct mwifiex_private *priv, skb->data + sizeof(struct ieee80211_hdr), pkt_len - sizeof(struct ieee80211_hdr)); - pkt_len -= ETH_ALEN + sizeof(pkt_len); + pkt_len -= ETH_ALEN; rx_pd->rx_pkt_length = cpu_to_le16(pkt_len); cfg80211_rx_mgmt(&priv->wdev, priv->roc_cfg.chan.center_freq, diff --git a/drivers/net/wireless/ray_cs.c b/drivers/net/wireless/ray_cs.c index 8704bae39e1bf941e87a7cceca1b21946cfa558a..edc990d09978940f4e418232ce0697c134096568 100644 --- a/drivers/net/wireless/ray_cs.c +++ b/drivers/net/wireless/ray_cs.c @@ -282,13 +282,14 @@ static int ray_probe(struct pcmcia_device *p_dev) { ray_dev_t *local; struct net_device *dev; + int ret; dev_dbg(&p_dev->dev, "ray_attach()\n"); /* Allocate space for private device-specific data */ dev = alloc_etherdev(sizeof(ray_dev_t)); if (!dev) - goto fail_alloc_dev; + return -ENOMEM; local = netdev_priv(dev); local->finder = p_dev; @@ -325,11 +326,16 @@ static int ray_probe(struct pcmcia_device *p_dev) timer_setup(&local->timer, NULL, 0); this_device = p_dev; - return ray_config(p_dev); + ret = ray_config(p_dev); + if (ret) + goto err_free_dev; + + return 0; -fail_alloc_dev: - return -ENOMEM; -} /* ray_attach */ +err_free_dev: + free_netdev(dev); + return ret; +} static void ray_detach(struct pcmcia_device *link) { @@ -1651,38 +1657,34 @@ static void authenticate_timeout(struct timer_list *t) /*===========================================================================*/ static int parse_addr(char *in_str, UCHAR *out) { + int i, k; int len; - int i, j, k; - int status; if (in_str == NULL) return 0; - if ((len = strlen(in_str)) < 2) + len = strnlen(in_str, ADDRLEN * 2 + 1) - 1; + if (len < 1) return 0; memset(out, 0, ADDRLEN); - status = 1; - j = len - 1; - if (j > 12) - j = 12; i = 5; - while (j > 0) { - if ((k = hex_to_bin(in_str[j--])) != -1) + while (len > 0) { + if ((k = hex_to_bin(in_str[len--])) != -1) out[i] = k; else return 0; - if (j == 0) + if (len == 0) break; - if ((k = hex_to_bin(in_str[j--])) != -1) + if ((k = hex_to_bin(in_str[len--])) != -1) out[i] += k << 4; else return 0; if (!i--) break; } - return status; + return 1; } /*===========================================================================*/ diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h index 921a226b18f8525a02b6e6946d0aaa71dbdb8f5c..08ccb49c9a2e39617296de5413e4c4ce3c842f31 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h @@ -1272,6 +1272,7 @@ struct rtl8xxxu_priv { u32 rege9c; u32 regeb4; u32 regebc; + u32 regrcr; int next_mbox; int nr_out_eps; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c index 837a1b9d189dfd82fed8292b27f17f6baffa7b19..f936ad6c57284fbb4f1a6ee7e2914b9e4e269682 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c @@ -1679,6 +1679,11 @@ static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv) val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); val8 &= ~BIT(0); rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); + + /* + * Fix transmission failure of rtl8192e. + */ + rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); } struct rtl8xxxu_fileops rtl8192eu_fops = { @@ -1705,6 +1710,7 @@ struct rtl8xxxu_fileops rtl8192eu_fops = { .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), .has_s0s1 = 0, .gen2_thermal_meter = 1, + .needs_full_init = 1, .adda_1t_init = 0x0fc01616, .adda_1t_path_on = 0x0fc01616, .adda_2t_path_on_a = 0x0fc01616, diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c index e5aac9694ade2011f555c161712d20a0b320a0ec..780dab27682975856f6d449e8ceae26bf5c3ffb6 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c @@ -4051,6 +4051,7 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; rtl8xxxu_write32(priv, REG_RCR, val32); + priv->regrcr = val32; /* * Accept all multicast @@ -5101,7 +5102,7 @@ static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, pending = priv->rx_urb_pending_count; } else { skb = (struct sk_buff *)rx_urb->urb.context; - dev_kfree_skb(skb); + dev_kfree_skb_irq(skb); usb_free_urb(&rx_urb->urb); } @@ -5500,7 +5501,6 @@ static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) { struct rtl8xxxu_priv *priv = hw->priv; struct device *dev = &priv->udev->dev; - u16 val16; int ret = 0, channel; bool ht40; @@ -5510,14 +5510,6 @@ static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) __func__, hw->conf.chandef.chan->hw_value, changed, hw->conf.chandef.width); - if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) { - val16 = ((hw->conf.long_frame_max_tx_count << - RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) | - ((hw->conf.short_frame_max_tx_count << - RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK); - rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); - } - if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { switch (hw->conf.chandef.width) { case NL80211_CHAN_WIDTH_20_NOHT: @@ -5600,7 +5592,7 @@ static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, unsigned int *total_flags, u64 multicast) { struct rtl8xxxu_priv *priv = hw->priv; - u32 rcr = rtl8xxxu_read32(priv, REG_RCR); + u32 rcr = priv->regrcr; dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", __func__, changed_flags, *total_flags); @@ -5646,6 +5638,7 @@ static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, */ rtl8xxxu_write32(priv, REG_RCR, rcr); + priv->regrcr = rcr; *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | diff --git a/drivers/net/wireless/realtek/rtlwifi/base.c b/drivers/net/wireless/realtek/rtlwifi/base.c index 6d1b6a4a81502b2423ce2ec53eb8ed911c943d49..7644d7cbcb5af402072e846197045e58435b2251 100644 --- a/drivers/net/wireless/realtek/rtlwifi/base.c +++ b/drivers/net/wireless/realtek/rtlwifi/base.c @@ -217,8 +217,8 @@ static void _rtl_init_hw_ht_capab(struct ieee80211_hw *hw, } else { if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_2T2R) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "1T2R or 2T2R\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "1T2R or 2T2R\n"); ht_cap->mcs.rx_mask[0] = 0xFF; ht_cap->mcs.rx_mask[1] = 0xFF; ht_cap->mcs.rx_mask[4] = 0x01; @@ -226,7 +226,7 @@ static void _rtl_init_hw_ht_capab(struct ieee80211_hw *hw, ht_cap->mcs.rx_highest = cpu_to_le16(MAX_BIT_RATE_40MHZ_MCS15); } else if (get_rf_type(rtlphy) == RF_1T1R) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "1T1R\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "1T1R\n"); ht_cap->mcs.rx_mask[0] = 0xFF; ht_cap->mcs.rx_mask[1] = 0x00; @@ -1344,7 +1344,7 @@ bool rtl_tx_mgmt_proc(struct ieee80211_hw *hw, struct sk_buff *skb) rtlpriv->cfg->ops->chk_switch_dmdp(hw); } if (ieee80211_is_auth(fc)) { - RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n"); + rtl_dbg(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n"); mac->link_state = MAC80211_LINKING; /* Dul mac */ @@ -1405,7 +1405,7 @@ bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx) if (mac->act_scanning) return false; - RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, + rtl_dbg(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, "%s ACT_ADDBAREQ From :%pM\n", is_tx ? "Tx" : "Rx", hdr->addr2); RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "req\n", @@ -1420,8 +1420,8 @@ bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx) rcu_read_lock(); sta = rtl_find_sta(hw, hdr->addr3); if (sta == NULL) { - RT_TRACE(rtlpriv, COMP_SEND | COMP_RECV, - DBG_DMESG, "sta is NULL\n"); + rtl_dbg(rtlpriv, COMP_SEND | COMP_RECV, + DBG_DMESG, "sta is NULL\n"); rcu_read_unlock(); return true; } @@ -1448,13 +1448,13 @@ bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx) } break; case ACT_ADDBARSP: - RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, - "%s ACT_ADDBARSP From :%pM\n", - is_tx ? "Tx" : "Rx", hdr->addr2); + rtl_dbg(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, + "%s ACT_ADDBARSP From :%pM\n", + is_tx ? "Tx" : "Rx", hdr->addr2); break; case ACT_DELBA: - RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, - "ACT_ADDBADEL From :%pM\n", hdr->addr2); + rtl_dbg(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, + "ACT_ADDBADEL From :%pM\n", hdr->addr2); break; } break; @@ -1539,9 +1539,9 @@ u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx, /* 68 : UDP BOOTP client * 67 : UDP BOOTP server */ - RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), - DBG_DMESG, "dhcp %s !!\n", - (is_tx) ? "Tx" : "Rx"); + rtl_dbg(rtlpriv, (COMP_SEND | COMP_RECV), + DBG_DMESG, "dhcp %s !!\n", + (is_tx) ? "Tx" : "Rx"); if (is_tx) setup_special_tx(rtlpriv, ppsc, @@ -1560,8 +1560,8 @@ u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx, rtlpriv->btcoexist.btc_info.in_4way = true; rtlpriv->btcoexist.btc_info.in_4way_ts = jiffies; - RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, - "802.1X %s EAPOL pkt!!\n", (is_tx) ? "Tx" : "Rx"); + rtl_dbg(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, + "802.1X %s EAPOL pkt!!\n", (is_tx) ? "Tx" : "Rx"); if (is_tx) { rtlpriv->ra.is_special_data = true; @@ -1603,12 +1603,12 @@ static void rtl_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, info = IEEE80211_SKB_CB(skb); ieee80211_tx_info_clear_status(info); if (ack) { - RT_TRACE(rtlpriv, COMP_TX_REPORT, DBG_LOUD, - "tx report: ack\n"); + rtl_dbg(rtlpriv, COMP_TX_REPORT, DBG_LOUD, + "tx report: ack\n"); info->flags |= IEEE80211_TX_STAT_ACK; } else { - RT_TRACE(rtlpriv, COMP_TX_REPORT, DBG_LOUD, - "tx report: not ack\n"); + rtl_dbg(rtlpriv, COMP_TX_REPORT, DBG_LOUD, + "tx report: not ack\n"); info->flags &= ~IEEE80211_TX_STAT_ACK; } ieee80211_tx_status_irqsafe(hw, skb); @@ -1646,8 +1646,8 @@ static u16 rtl_get_tx_report_sn(struct ieee80211_hw *hw, tx_report->last_sent_time = jiffies; tx_info->sn = sn; tx_info->send_time = tx_report->last_sent_time; - RT_TRACE(rtlpriv, COMP_TX_REPORT, DBG_DMESG, - "Send TX-Report sn=0x%X\n", sn); + rtl_dbg(rtlpriv, COMP_TX_REPORT, DBG_DMESG, + "Send TX-Report sn=0x%X\n", sn); return sn; } @@ -1694,9 +1694,9 @@ void rtl_tx_report_handler(struct ieee80211_hw *hw, u8 *tmp_buf, u8 c2h_cmd_len) break; } } - RT_TRACE(rtlpriv, COMP_TX_REPORT, DBG_DMESG, - "Recv TX-Report st=0x%02X sn=0x%X retry=0x%X\n", - st, sn, retry); + rtl_dbg(rtlpriv, COMP_TX_REPORT, DBG_DMESG, + "Recv TX-Report st=0x%02X sn=0x%X retry=0x%X\n", + st, sn, retry); } EXPORT_SYMBOL_GPL(rtl_tx_report_handler); @@ -1709,9 +1709,9 @@ bool rtl_check_tx_report_acked(struct ieee80211_hw *hw) return true; if (time_before(tx_report->last_sent_time + 3 * HZ, jiffies)) { - RT_TRACE(rtlpriv, COMP_TX_REPORT, DBG_WARNING, - "Check TX-Report timeout!! s_sn=0x%X r_sn=0x%X\n", - tx_report->last_sent_sn, tx_report->last_recv_sn); + rtl_dbg(rtlpriv, COMP_TX_REPORT, DBG_WARNING, + "Check TX-Report timeout!! s_sn=0x%X r_sn=0x%X\n", + tx_report->last_sent_sn, tx_report->last_recv_sn); return true; /* 3 sec. (timeout) seen as acked */ } @@ -1727,8 +1727,8 @@ void rtl_wait_tx_report_acked(struct ieee80211_hw *hw, u32 wait_ms) if (rtl_check_tx_report_acked(hw)) break; usleep_range(1000, 2000); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "Wait 1ms (%d/%d) to disable key.\n", i, wait_ms); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "Wait 1ms (%d/%d) to disable key.\n", i, wait_ms); } } @@ -1790,9 +1790,9 @@ int rtl_tx_agg_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif, return -ENXIO; tid_data = &sta_entry->tids[tid]; - RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, - "on ra = %pM tid = %d seq:%d\n", sta->addr, tid, - *ssn); + rtl_dbg(rtlpriv, COMP_SEND, DBG_DMESG, + "on ra = %pM tid = %d seq:%d\n", sta->addr, tid, + *ssn); tid_data->agg.agg_state = RTL_AGG_START; @@ -1809,8 +1809,8 @@ int rtl_tx_agg_stop(struct ieee80211_hw *hw, struct ieee80211_vif *vif, if (sta == NULL) return -EINVAL; - RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, - "on ra = %pM tid = %d\n", sta->addr, tid); + rtl_dbg(rtlpriv, COMP_SEND, DBG_DMESG, + "on ra = %pM tid = %d\n", sta->addr, tid); if (unlikely(tid >= MAX_TID_COUNT)) return -EINVAL; @@ -1849,8 +1849,8 @@ int rtl_rx_agg_start(struct ieee80211_hw *hw, return -ENXIO; tid_data = &sta_entry->tids[tid]; - RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG, - "on ra = %pM tid = %d\n", sta->addr, tid); + rtl_dbg(rtlpriv, COMP_RECV, DBG_DMESG, + "on ra = %pM tid = %d\n", sta->addr, tid); tid_data->agg.rx_agg_state = RTL_RX_AGG_START; return 0; @@ -1865,8 +1865,8 @@ int rtl_rx_agg_stop(struct ieee80211_hw *hw, if (sta == NULL) return -EINVAL; - RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, - "on ra = %pM tid = %d\n", sta->addr, tid); + rtl_dbg(rtlpriv, COMP_SEND, DBG_DMESG, + "on ra = %pM tid = %d\n", sta->addr, tid); if (unlikely(tid >= MAX_TID_COUNT)) return -EINVAL; @@ -1885,8 +1885,8 @@ int rtl_tx_agg_oper(struct ieee80211_hw *hw, if (sta == NULL) return -EINVAL; - RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, - "on ra = %pM tid = %d\n", sta->addr, tid); + rtl_dbg(rtlpriv, COMP_SEND, DBG_DMESG, + "on ra = %pM tid = %d\n", sta->addr, tid); if (unlikely(tid >= MAX_TID_COUNT)) return -EINVAL; @@ -1906,9 +1906,9 @@ void rtl_rx_ampdu_apply(struct rtl_priv *rtlpriv) btc_ops->btc_get_ampdu_cfg(rtlpriv, &reject_agg, &ctrl_agg_size, &agg_size); - RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, - "Set RX AMPDU: coex - reject=%d, ctrl_agg_size=%d, size=%d", - reject_agg, ctrl_agg_size, agg_size); + rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, + "Set RX AMPDU: coex - reject=%d, ctrl_agg_size=%d, size=%d", + reject_agg, ctrl_agg_size, agg_size); rtlpriv->hw->max_rx_aggregation_subframes = (ctrl_agg_size ? agg_size : IEEE80211_MAX_AMPDU_BUF_HT); @@ -1996,9 +1996,9 @@ void rtl_scan_list_expire(struct ieee80211_hw *hw) list_del(&entry->list); rtlpriv->scan_list.num--; - RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, - "BSSID=%pM is expire in scan list (total=%d)\n", - entry->bssid, rtlpriv->scan_list.num); + rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, + "BSSID=%pM is expire in scan list (total=%d)\n", + entry->bssid, rtlpriv->scan_list.num); kfree(entry); } @@ -2032,9 +2032,9 @@ void rtl_collect_scan_list(struct ieee80211_hw *hw, struct sk_buff *skb) if (memcmp(entry->bssid, hdr->addr3, ETH_ALEN) == 0) { list_del_init(&entry->list); entry_found = true; - RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, - "Update BSSID=%pM to scan list (total=%d)\n", - hdr->addr3, rtlpriv->scan_list.num); + rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, + "Update BSSID=%pM to scan list (total=%d)\n", + hdr->addr3, rtlpriv->scan_list.num); break; } } @@ -2048,9 +2048,9 @@ void rtl_collect_scan_list(struct ieee80211_hw *hw, struct sk_buff *skb) memcpy(entry->bssid, hdr->addr3, ETH_ALEN); rtlpriv->scan_list.num++; - RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, - "Add BSSID=%pM to scan list (total=%d)\n", - hdr->addr3, rtlpriv->scan_list.num); + rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, + "Add BSSID=%pM to scan list (total=%d)\n", + hdr->addr3, rtlpriv->scan_list.num); } entry->age = jiffies; @@ -2213,8 +2213,8 @@ void rtl_watchdog_wq_callback(void *data) if ((rtlpriv->link_info.bcn_rx_inperiod + rtlpriv->link_info.num_rx_inperiod) == 0) { rtlpriv->link_info.roam_times++; - RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, - "AP off for %d s\n", + rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, + "AP off for %d s\n", (rtlpriv->link_info.roam_times * 2)); /* if we can't recv beacon for 10s, @@ -2325,11 +2325,11 @@ static void rtl_c2h_content_parsing(struct ieee80211_hw *hw, switch (cmd_id) { case C2H_DBG: - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "[C2H], C2H_DBG!!\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, "[C2H], C2H_DBG!!\n"); break; case C2H_TXBF: - RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, - "[C2H], C2H_TXBF!!\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, + "[C2H], C2H_TXBF!!\n"); break; case C2H_TX_REPORT: rtl_tx_report_handler(hw, cmd_buf, cmd_len); @@ -2339,20 +2339,20 @@ static void rtl_c2h_content_parsing(struct ieee80211_hw *hw, hal_ops->c2h_ra_report_handler(hw, cmd_buf, cmd_len); break; case C2H_BT_INFO: - RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, - "[C2H], C2H_BT_INFO!!\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, + "[C2H], C2H_BT_INFO!!\n"); if (rtlpriv->cfg->ops->get_btc_status()) btc_ops->btc_btinfo_notify(rtlpriv, cmd_buf, cmd_len); break; case C2H_BT_MP: - RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, - "[C2H], C2H_BT_MP!!\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, + "[C2H], C2H_BT_MP!!\n"); if (rtlpriv->cfg->ops->get_btc_status()) btc_ops->btc_btmpinfo_notify(rtlpriv, cmd_buf, cmd_len); break; default: - RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, - "[C2H], Unknown packet!! cmd_id(%#X)!\n", cmd_id); + rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, + "[C2H], Unknown packet!! cmd_id(%#X)!\n", cmd_id); break; } } @@ -2376,8 +2376,8 @@ void rtl_c2hcmd_launcher(struct ieee80211_hw *hw, int exec) if (!skb) break; - RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG, "C2H rx_desc_shift=%d\n", - *((u8 *)skb->cb)); + rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, "C2H rx_desc_shift=%d\n", + *((u8 *)skb->cb)); RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_DMESG, "C2H data: ", skb->data, skb->len); @@ -2721,29 +2721,29 @@ void rtl_recognize_peer(struct ieee80211_hw *hw, u8 *data, unsigned int len) (memcmp(mac->bssid, ap5_6, 3) == 0) || vendor == PEER_ATH) { vendor = PEER_ATH; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>ath find\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>ath find\n"); } else if ((memcmp(mac->bssid, ap4_4, 3) == 0) || (memcmp(mac->bssid, ap4_5, 3) == 0) || (memcmp(mac->bssid, ap4_1, 3) == 0) || (memcmp(mac->bssid, ap4_2, 3) == 0) || (memcmp(mac->bssid, ap4_3, 3) == 0) || vendor == PEER_RAL) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>ral find\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>ral find\n"); vendor = PEER_RAL; } else if (memcmp(mac->bssid, ap6_1, 3) == 0 || vendor == PEER_CISCO) { vendor = PEER_CISCO; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>cisco find\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>cisco find\n"); } else if ((memcmp(mac->bssid, ap3_1, 3) == 0) || (memcmp(mac->bssid, ap3_2, 3) == 0) || (memcmp(mac->bssid, ap3_3, 3) == 0) || vendor == PEER_BROAD) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>broad find\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>broad find\n"); vendor = PEER_BROAD; } else if (memcmp(mac->bssid, ap7_1, 3) == 0 || vendor == PEER_MARV) { vendor = PEER_MARV; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>marv find\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>marv find\n"); } mac->vendor = vendor; diff --git a/drivers/net/wireless/realtek/rtlwifi/cam.c b/drivers/net/wireless/realtek/rtlwifi/cam.c index f7a7dcbf945ef67e5a1f2b991906c1c598de0eab..c63129525875270f070e8d830768958c92d5fb54 100644 --- a/drivers/net/wireless/realtek/rtlwifi/cam.c +++ b/drivers/net/wireless/realtek/rtlwifi/cam.c @@ -64,14 +64,14 @@ static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no, rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], target_command); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "WRITE %x: %x\n", - rtlpriv->cfg->maps[WCAMI], target_content); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "The Key ID is %d\n", entry_no); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "WRITE %x: %x\n", - rtlpriv->cfg->maps[RWCAM], target_command); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "WRITE %x: %x\n", + rtlpriv->cfg->maps[WCAMI], target_content); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "The Key ID is %d\n", entry_no); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "WRITE %x: %x\n", + rtlpriv->cfg->maps[RWCAM], target_command); } else if (entry_i == 1) { @@ -85,10 +85,10 @@ static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no, rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], target_command); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "WRITE A4: %x\n", target_content); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "WRITE A0: %x\n", target_command); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "WRITE A4: %x\n", target_content); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "WRITE A0: %x\n", target_command); } else { @@ -104,15 +104,15 @@ static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no, rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], target_command); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "WRITE A4: %x\n", target_content); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "WRITE A0: %x\n", target_command); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "WRITE A4: %x\n", target_content); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "WRITE A0: %x\n", target_command); } } - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "after set key, usconfig:%x\n", us_config); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "after set key, usconfig:%x\n", us_config); } u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr, @@ -122,14 +122,14 @@ u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr, u32 us_config; struct rtl_priv *rtlpriv = rtl_priv(hw); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, ulUseDK=%x MacAddr %pM\n", - ul_entry_idx, ul_key_id, ul_enc_alg, - ul_default_key, mac_addr); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, ulUseDK=%x MacAddr %pM\n", + ul_entry_idx, ul_key_id, ul_enc_alg, + ul_default_key, mac_addr); if (ul_key_id == TOTAL_CAM_ENTRY) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "ulKeyId exceed!\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "ulKeyId exceed!\n"); return 0; } @@ -141,7 +141,7 @@ u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr, rtl_cam_program_entry(hw, ul_entry_idx, mac_addr, (u8 *)key_content, us_config); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "end\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "end\n"); return 1; @@ -154,7 +154,7 @@ int rtl_cam_delete_one_entry(struct ieee80211_hw *hw, u32 ul_command; struct rtl_priv *rtlpriv = rtl_priv(hw); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "key_idx:%d\n", ul_key_id); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "key_idx:%d\n", ul_key_id); ul_command = ul_key_id * CAM_CONTENT_COUNT; ul_command = ul_command | BIT(31) | BIT(16); @@ -162,10 +162,10 @@ int rtl_cam_delete_one_entry(struct ieee80211_hw *hw, rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], 0); rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "rtl_cam_delete_one_entry(): WRITE A4: %x\n", 0); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "rtl_cam_delete_one_entry(): WRITE A0: %x\n", ul_command); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "%s: WRITE A4: %x\n", __func__, 0); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "%s: WRITE A0: %x\n", __func__, ul_command); return 0; @@ -216,10 +216,10 @@ void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index) rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content); rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "rtl_cam_mark_invalid(): WRITE A4: %x\n", ul_content); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "rtl_cam_mark_invalid(): WRITE A0: %x\n", ul_command); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "%s: WRITE A4: %x\n", __func__, ul_content); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "%s: WRITE A0: %x\n", __func__, ul_command); } EXPORT_SYMBOL(rtl_cam_mark_invalid); @@ -266,12 +266,10 @@ void rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index) rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content); rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "rtl_cam_empty_entry(): WRITE A4: %x\n", - ul_content); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "rtl_cam_empty_entry(): WRITE A0: %x\n", - ul_command); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "%s: WRITE A4: %x\n", __func__, ul_content); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "%s: WRITE A0: %x\n", __func__, ul_command); } } @@ -334,8 +332,8 @@ void rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr) /* Remove from HW Security CAM */ eth_zero_addr(rtlpriv->sec.hwsec_cam_sta_addr[i]); rtlpriv->sec.hwsec_cam_bitmap &= ~(BIT(0) << i); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "&&&&&&&&&del entry %d\n", i); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "&&&&&&&&&del entry %d\n", i); } } return; diff --git a/drivers/net/wireless/realtek/rtlwifi/core.c b/drivers/net/wireless/realtek/rtlwifi/core.c index 4bf7967590ca7be3b9b452d0b0ec65d98b829599..0ad4e0f099f95bb9e6f389dbdbdec5be8b830d42 100644 --- a/drivers/net/wireless/realtek/rtlwifi/core.c +++ b/drivers/net/wireless/realtek/rtlwifi/core.c @@ -98,8 +98,8 @@ static void rtl_fw_do_work(const struct firmware *firmware, void *context, struct rtl_priv *rtlpriv = rtl_priv(hw); int err; - RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, - "Firmware callback routine entered!\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, + "Firmware callback routine entered!\n"); complete(&rtlpriv->firmware_loading_complete); if (!firmware) { if (rtlpriv->cfg->alt_fw_name) { @@ -235,8 +235,8 @@ static int rtl_op_add_interface(struct ieee80211_hw *hw, u8 retry_limit = 0x30; if (mac->vif) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "vif has been set!! mac->vif = 0x%p\n", mac->vif); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "vif has been set!! mac->vif = 0x%p\n", mac->vif); return -EOPNOTSUPP; } @@ -251,16 +251,16 @@ static int rtl_op_add_interface(struct ieee80211_hw *hw, /*fall through*/ case NL80211_IFTYPE_STATION: if (mac->beacon_enabled == 1) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "NL80211_IFTYPE_STATION\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "NL80211_IFTYPE_STATION\n"); mac->beacon_enabled = 0; rtlpriv->cfg->ops->update_interrupt_mask(hw, 0, rtlpriv->cfg->maps[RTL_IBSS_INT_MASKS]); } break; case NL80211_IFTYPE_ADHOC: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "NL80211_IFTYPE_ADHOC\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "NL80211_IFTYPE_ADHOC\n"); mac->link_state = MAC80211_LINKED; rtlpriv->cfg->ops->set_bcn_reg(hw); @@ -277,8 +277,8 @@ static int rtl_op_add_interface(struct ieee80211_hw *hw, mac->p2p = P2P_ROLE_GO; /*fall through*/ case NL80211_IFTYPE_AP: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "NL80211_IFTYPE_AP\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "NL80211_IFTYPE_AP\n"); mac->link_state = MAC80211_LINKED; rtlpriv->cfg->ops->set_bcn_reg(hw); @@ -292,8 +292,8 @@ static int rtl_op_add_interface(struct ieee80211_hw *hw, retry_limit = 0x07; break; case NL80211_IFTYPE_MESH_POINT: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "NL80211_IFTYPE_MESH_POINT\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "NL80211_IFTYPE_MESH_POINT\n"); mac->link_state = MAC80211_LINKED; rtlpriv->cfg->ops->set_bcn_reg(hw); @@ -314,8 +314,8 @@ static int rtl_op_add_interface(struct ieee80211_hw *hw, } if (mac->p2p) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "p2p role %x\n", vif->type); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "p2p role %x\n", vif->type); mac->basic_rates = 0xff0;/*disable cck rate for p2p*/ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE, (u8 *)(&mac->basic_rates)); @@ -379,8 +379,8 @@ static int rtl_op_change_interface(struct ieee80211_hw *hw, vif->type = new_type; vif->p2p = p2p; ret = rtl_op_add_interface(hw, vif); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "p2p %x\n", p2p); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "p2p %x\n", p2p); return ret; } @@ -454,8 +454,8 @@ static void _rtl_add_wowlan_patterns(struct ieee80211_hw *hw, memset(mask, 0, MAX_WOL_BIT_MASK_SIZE); if (patterns[i].pattern_len < 0 || patterns[i].pattern_len > MAX_WOL_PATTERN_SIZE) { - RT_TRACE(rtlpriv, COMP_POWER, DBG_WARNING, - "Pattern[%d] is too long\n", i); + rtl_dbg(rtlpriv, COMP_POWER, DBG_WARNING, + "Pattern[%d] is too long\n", i); continue; } pattern_os = patterns[i].pattern; @@ -534,8 +534,8 @@ static void _rtl_add_wowlan_patterns(struct ieee80211_hw *hw, "pattern to hw\n", content, len); /* 3. calculate crc */ rtl_pattern.crc = _calculate_wol_pattern_crc(content, len); - RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, - "CRC_Remainder = 0x%x\n", rtl_pattern.crc); + rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, + "CRC_Remainder = 0x%x\n", rtl_pattern.crc); /* 4. write crc & mask_for_hw to hw */ rtlpriv->cfg->ops->add_wowlan_pattern(hw, &rtl_pattern, i); @@ -550,7 +550,7 @@ static int rtl_op_suspend(struct ieee80211_hw *hw, struct rtl_hal *rtlhal = rtl_hal(rtlpriv); struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); - RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, "\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, "\n"); if (WARN_ON(!wow)) return -EINVAL; @@ -576,7 +576,7 @@ static int rtl_op_resume(struct ieee80211_hw *hw) struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); time64_t now; - RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, "\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, "\n"); rtlhal->driver_is_goingto_unload = false; rtlhal->enter_pnp_sleep = false; rtlhal->wake_from_pnp_sleep = true; @@ -607,8 +607,8 @@ static int rtl_op_config(struct ieee80211_hw *hw, u32 changed) mutex_lock(&rtlpriv->locks.conf_mutex); if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL) { /* BIT(2)*/ - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "IEEE80211_CONF_CHANGE_LISTEN_INTERVAL\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "IEEE80211_CONF_CHANGE_LISTEN_INTERVAL\n"); } /*For IPS */ @@ -651,9 +651,9 @@ static int rtl_op_config(struct ieee80211_hw *hw, u32 changed) } if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "IEEE80211_CONF_CHANGE_RETRY_LIMITS %x\n", - hw->conf.long_frame_max_tx_count); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "IEEE80211_CONF_CHANGE_RETRY_LIMITS %x\n", + hw->conf.long_frame_max_tx_count); /* brought up everything changes (changed == ~0) indicates first * open, so use our default value instead of that of wiphy. */ @@ -828,13 +828,13 @@ static void rtl_op_configure_filter(struct ieee80211_hw *hw, if (*new_flags & FIF_ALLMULTI) { mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_AM] | rtlpriv->cfg->maps[MAC_RCR_AB]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Enable receive multicast frame\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Enable receive multicast frame\n"); } else { mac->rx_conf &= ~(rtlpriv->cfg->maps[MAC_RCR_AM] | rtlpriv->cfg->maps[MAC_RCR_AB]); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Disable receive multicast frame\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Disable receive multicast frame\n"); } update_rcr = true; } @@ -842,12 +842,12 @@ static void rtl_op_configure_filter(struct ieee80211_hw *hw, if (changed_flags & FIF_FCSFAIL) { if (*new_flags & FIF_FCSFAIL) { mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_ACRC32]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Enable receive FCS error frame\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Enable receive FCS error frame\n"); } else { mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_ACRC32]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Disable receive FCS error frame\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Disable receive FCS error frame\n"); } if (!update_rcr) update_rcr = true; @@ -874,12 +874,12 @@ static void rtl_op_configure_filter(struct ieee80211_hw *hw, if (*new_flags & FIF_CONTROL) { mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_ACF]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Enable receive control frame.\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Enable receive control frame.\n"); } else { mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_ACF]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Disable receive control frame.\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Disable receive control frame.\n"); } if (!update_rcr) update_rcr = true; @@ -888,12 +888,12 @@ static void rtl_op_configure_filter(struct ieee80211_hw *hw, if (changed_flags & FIF_OTHER_BSS) { if (*new_flags & FIF_OTHER_BSS) { mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_AAP]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Enable receive other BSS's frame.\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Enable receive other BSS's frame.\n"); } else { mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_AAP]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Disable receive other BSS's frame.\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Disable receive other BSS's frame.\n"); } if (!update_rcr) update_rcr = true; @@ -941,7 +941,7 @@ static int rtl_op_sta_add(struct ieee80211_hw *hw, sta->supp_rates[0] &= 0xfffffff0; memcpy(sta_entry->mac_addr, sta->addr, ETH_ALEN); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, "Add sta addr is %pM\n", sta->addr); rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 0, true); } @@ -956,8 +956,8 @@ static int rtl_op_sta_remove(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_sta_info *sta_entry; if (sta) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "Remove sta addr is %pM\n", sta->addr); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "Remove sta addr is %pM\n", sta->addr); sta_entry = (struct rtl_sta_info *)sta->drv_priv; sta_entry->wireless_mode = 0; sta_entry->ratr_index = 0; @@ -1004,8 +1004,8 @@ static int rtl_op_conf_tx(struct ieee80211_hw *hw, int aci; if (queue >= AC_MAX) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "queue number %d is incorrect!\n", queue); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "queue number %d is incorrect!\n", queue); return -EINVAL; } @@ -1050,8 +1050,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, (changed & BSS_CHANGED_BEACON_ENABLED && bss_conf->enable_beacon)) { if (mac->beacon_enabled == 0) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "BSS_CHANGED_BEACON_ENABLED\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "BSS_CHANGED_BEACON_ENABLED\n"); /*start hw beacon interrupt. */ /*rtlpriv->cfg->ops->set_bcn_reg(hw); */ @@ -1068,8 +1068,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, if ((changed & BSS_CHANGED_BEACON_ENABLED && !bss_conf->enable_beacon)) { if (mac->beacon_enabled == 1) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "ADHOC DISABLE BEACON\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "ADHOC DISABLE BEACON\n"); mac->beacon_enabled = 0; rtlpriv->cfg->ops->update_interrupt_mask(hw, 0, @@ -1078,8 +1078,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, } } if (changed & BSS_CHANGED_BEACON_INT) { - RT_TRACE(rtlpriv, COMP_BEACON, DBG_TRACE, - "BSS_CHANGED_BEACON_INT\n"); + rtl_dbg(rtlpriv, COMP_BEACON, DBG_TRACE, + "BSS_CHANGED_BEACON_INT\n"); mac->beacon_interval = bss_conf->beacon_int; rtlpriv->cfg->ops->set_bcn_intv(hw); } @@ -1117,8 +1117,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, rcu_read_unlock(); goto out; } - RT_TRACE(rtlpriv, COMP_EASY_CONCURRENT, DBG_LOUD, - "send PS STATIC frame\n"); + rtl_dbg(rtlpriv, COMP_EASY_CONCURRENT, DBG_LOUD, + "send PS STATIC frame\n"); if (rtlpriv->dm.supp_phymode_switch) { if (sta->ht_cap.ht_supported) rtl_send_smps_action(hw, sta, @@ -1158,8 +1158,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, HW_VAR_KEEP_ALIVE, (u8 *)(&keep_alive)); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "BSS_CHANGED_ASSOC\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "BSS_CHANGED_ASSOC\n"); } else { struct cfg80211_bss *bss = NULL; @@ -1176,14 +1176,14 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, IEEE80211_BSS_TYPE_ESS, IEEE80211_PRIVACY_OFF); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "bssid = %pMF\n", mac->bssid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "bssid = %pMF\n", mac->bssid); if (bss) { cfg80211_unlink_bss(hw->wiphy, bss); cfg80211_put_bss(hw->wiphy, bss); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "cfg80211_unlink !!\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "cfg80211_unlink !!\n"); } eth_zero_addr(mac->bssid); @@ -1194,8 +1194,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, if (rtlpriv->cfg->ops->chk_switch_dmdp) rtlpriv->cfg->ops->chk_switch_dmdp(hw); } - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "BSS_CHANGED_UN_ASSOC\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "BSS_CHANGED_UN_ASSOC\n"); } rtlpriv->cfg->ops->set_network_type(hw, vif->type); /* For FW LPS: @@ -1213,14 +1213,14 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, } if (changed & BSS_CHANGED_ERP_CTS_PROT) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "BSS_CHANGED_ERP_CTS_PROT\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "BSS_CHANGED_ERP_CTS_PROT\n"); mac->use_cts_protect = bss_conf->use_cts_prot; } if (changed & BSS_CHANGED_ERP_PREAMBLE) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "BSS_CHANGED_ERP_PREAMBLE use short preamble:%x\n", + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "BSS_CHANGED_ERP_PREAMBLE use short preamble:%x\n", bss_conf->use_short_preamble); mac->short_preamble = bss_conf->use_short_preamble; @@ -1229,8 +1229,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, } if (changed & BSS_CHANGED_ERP_SLOT) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "BSS_CHANGED_ERP_SLOT\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "BSS_CHANGED_ERP_SLOT\n"); if (bss_conf->use_short_slot) mac->slot_time = RTL_SLOT_TIME_9; @@ -1244,8 +1244,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, if (changed & BSS_CHANGED_HT) { struct ieee80211_sta *sta = NULL; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "BSS_CHANGED_HT\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "BSS_CHANGED_HT\n"); rcu_read_lock(); sta = ieee80211_find_sta(vif, (u8 *)bss_conf->bssid); @@ -1276,8 +1276,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BSSID, (u8 *)bss_conf->bssid); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "bssid: %pM\n", bss_conf->bssid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "bssid: %pM\n", bss_conf->bssid); mac->vendor = PEER_UNKNOWN; memcpy(mac->bssid, bss_conf->bssid, ETH_ALEN); @@ -1407,27 +1407,27 @@ static int rtl_op_ampdu_action(struct ieee80211_hw *hw, switch (action) { case IEEE80211_AMPDU_TX_START: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "IEEE80211_AMPDU_TX_START: TID:%d\n", tid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "IEEE80211_AMPDU_TX_START: TID:%d\n", tid); return rtl_tx_agg_start(hw, vif, sta, tid, ssn); case IEEE80211_AMPDU_TX_STOP_CONT: case IEEE80211_AMPDU_TX_STOP_FLUSH: case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "IEEE80211_AMPDU_TX_STOP: TID:%d\n", tid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "IEEE80211_AMPDU_TX_STOP: TID:%d\n", tid); return rtl_tx_agg_stop(hw, vif, sta, tid); case IEEE80211_AMPDU_TX_OPERATIONAL: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "IEEE80211_AMPDU_TX_OPERATIONAL:TID:%d\n", tid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "IEEE80211_AMPDU_TX_OPERATIONAL:TID:%d\n", tid); rtl_tx_agg_oper(hw, sta, tid); break; case IEEE80211_AMPDU_RX_START: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "IEEE80211_AMPDU_RX_START:TID:%d\n", tid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "IEEE80211_AMPDU_RX_START:TID:%d\n", tid); return rtl_rx_agg_start(hw, sta, tid); case IEEE80211_AMPDU_RX_STOP: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "IEEE80211_AMPDU_RX_STOP:TID:%d\n", tid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "IEEE80211_AMPDU_RX_STOP:TID:%d\n", tid); return rtl_rx_agg_stop(hw, sta, tid); default: pr_err("IEEE80211_AMPDU_ERR!!!!:\n"); @@ -1443,7 +1443,7 @@ static void rtl_op_sw_scan_start(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "\n"); mac->act_scanning = true; if (rtlpriv->link_info.higher_busytraffic) { mac->skip_scan = true; @@ -1481,7 +1481,7 @@ static void rtl_op_sw_scan_complete(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "\n"); mac->act_scanning = false; mac->skip_scan = false; @@ -1531,8 +1531,8 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, rtlpriv->btcoexist.btc_info.in_4way = false; if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "not open hw encryption\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "not open hw encryption\n"); return -ENOSPC; /*User disabled HW-crypto */ } /* To support IBSS, use sw-crypto for GTK */ @@ -1540,10 +1540,10 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, vif->type == NL80211_IFTYPE_MESH_POINT) && !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) return -ENOSPC; - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "%s hardware based encryption for keyidx: %d, mac: %pM\n", - cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, - sta ? sta->addr : bcast_addr); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "%s hardware based encryption for keyidx: %d, mac: %pM\n", + cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, + sta ? sta->addr : bcast_addr); rtlpriv->sec.being_setkey = true; rtl_ips_nic_on(hw); mutex_lock(&rtlpriv->locks.conf_mutex); @@ -1552,28 +1552,28 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, switch (key->cipher) { case WLAN_CIPHER_SUITE_WEP40: key_type = WEP40_ENCRYPTION; - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:WEP40\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "alg:WEP40\n"); break; case WLAN_CIPHER_SUITE_WEP104: - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:WEP104\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "alg:WEP104\n"); key_type = WEP104_ENCRYPTION; break; case WLAN_CIPHER_SUITE_TKIP: key_type = TKIP_ENCRYPTION; - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:TKIP\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "alg:TKIP\n"); break; case WLAN_CIPHER_SUITE_CCMP: key_type = AESCCMP_ENCRYPTION; - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:CCMP\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "alg:CCMP\n"); break; case WLAN_CIPHER_SUITE_AES_CMAC: /* HW don't support CMAC encryption, * use software CMAC encryption */ key_type = AESCMAC_ENCRYPTION; - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:CMAC\n"); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "HW don't support CMAC encryption, use software CMAC encryption\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "alg:CMAC\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "HW don't support CMAC encryption, use software CMAC encryption\n"); err = -EOPNOTSUPP; goto out_unlock; default: @@ -1619,9 +1619,9 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, key_type == WEP104_ENCRYPTION)) wep_only = true; rtlpriv->sec.pairwise_enc_algorithm = key_type; - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "set enable_hw_sec, key_type:%x(OPEN:0 WEP40:1 TKIP:2 AES:4 WEP104:5)\n", - key_type); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "set enable_hw_sec, key_type:%x(OPEN:0 WEP40:1 TKIP:2 AES:4 WEP104:5)\n", + key_type); rtlpriv->cfg->ops->enable_hw_sec(hw); } } @@ -1629,8 +1629,8 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, switch (cmd) { case SET_KEY: if (wep_only) { - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "set WEP(group/pairwise) key\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "set WEP(group/pairwise) key\n"); /* Pairwise key with an assigned MAC address. */ rtlpriv->sec.pairwise_enc_algorithm = key_type; rtlpriv->sec.group_enc_algorithm = key_type; @@ -1640,8 +1640,8 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, rtlpriv->sec.key_len[key_idx] = key->keylen; eth_zero_addr(mac_addr); } else if (group_key) { /* group key */ - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "set group key\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "set group key\n"); /* group key */ rtlpriv->sec.group_enc_algorithm = key_type; /*set local buf about group key. */ @@ -1650,8 +1650,8 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, rtlpriv->sec.key_len[key_idx] = key->keylen; memcpy(mac_addr, bcast_addr, ETH_ALEN); } else { /* pairwise key */ - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "set pairwise key\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "set pairwise key\n"); if (!sta) { WARN_ONCE(true, "rtlwifi: pairwise key without mac_addr\n"); @@ -1683,8 +1683,8 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; break; case DISABLE_KEY: - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "disable key delete one entry\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "disable key delete one entry\n"); /*set local buf about wep key. */ if (vif->type == NL80211_IFTYPE_AP || vif->type == NL80211_IFTYPE_MESH_POINT) { @@ -1732,9 +1732,9 @@ static void rtl_op_rfkill_poll(struct ieee80211_hw *hw) if (unlikely(radio_state != rtlpriv->rfkill.rfkill_state)) { rtlpriv->rfkill.rfkill_state = radio_state; - RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, - "wireless radio switch turned %s\n", - radio_state ? "on" : "off"); + rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, + "wireless radio switch turned %s\n", + radio_state ? "on" : "off"); blocked = (rtlpriv->rfkill.rfkill_state == 1) ? 0 : 1; wiphy_rfkill_set_hw_state(hw->wiphy, blocked); @@ -1779,26 +1779,27 @@ bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version, do { cfg_cmd = pwrcfgcmd[ary_idx]; - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, - "rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), famsk(%#x), interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n", - GET_PWR_CFG_OFFSET(cfg_cmd), - GET_PWR_CFG_CUT_MASK(cfg_cmd), - GET_PWR_CFG_FAB_MASK(cfg_cmd), - GET_PWR_CFG_INTF_MASK(cfg_cmd), - GET_PWR_CFG_BASE(cfg_cmd), GET_PWR_CFG_CMD(cfg_cmd), - GET_PWR_CFG_MASK(cfg_cmd), GET_PWR_CFG_VALUE(cfg_cmd)); + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, + "%s: offset(%#x),cut_msk(%#x), famsk(%#x), interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n", + __func__, + GET_PWR_CFG_OFFSET(cfg_cmd), + GET_PWR_CFG_CUT_MASK(cfg_cmd), + GET_PWR_CFG_FAB_MASK(cfg_cmd), + GET_PWR_CFG_INTF_MASK(cfg_cmd), + GET_PWR_CFG_BASE(cfg_cmd), GET_PWR_CFG_CMD(cfg_cmd), + GET_PWR_CFG_MASK(cfg_cmd), GET_PWR_CFG_VALUE(cfg_cmd)); if ((GET_PWR_CFG_FAB_MASK(cfg_cmd)&faversion) && (GET_PWR_CFG_CUT_MASK(cfg_cmd)&cut_version) && (GET_PWR_CFG_INTF_MASK(cfg_cmd)&interface_type)) { switch (GET_PWR_CFG_CMD(cfg_cmd)) { case PWR_CMD_READ: - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n"); break; case PWR_CMD_WRITE: - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, - "%s(): PWR_CMD_WRITE\n", __func__); + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, + "%s(): PWR_CMD_WRITE\n", __func__); offset = GET_PWR_CFG_OFFSET(cfg_cmd); /*Read the value from system register*/ @@ -1811,7 +1812,7 @@ bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version, rtl_write_byte(rtlpriv, offset, value); break; case PWR_CMD_POLLING: - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n"); polling_bit = false; offset = GET_PWR_CFG_OFFSET(cfg_cmd); @@ -1832,8 +1833,8 @@ bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version, } while (!polling_bit); break; case PWR_CMD_DELAY: - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, - "rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, + "%s: PWR_CMD_DELAY\n", __func__); if (GET_PWR_CFG_VALUE(cfg_cmd) == PWRSEQ_DELAY_US) udelay(GET_PWR_CFG_OFFSET(cfg_cmd)); @@ -1841,8 +1842,8 @@ bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version, mdelay(GET_PWR_CFG_OFFSET(cfg_cmd)); break; case PWR_CMD_END: - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, - "rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, + "%s: PWR_CMD_END\n", __func__); return true; default: WARN_ONCE(true, diff --git a/drivers/net/wireless/realtek/rtlwifi/debug.c b/drivers/net/wireless/realtek/rtlwifi/debug.c index 474439fc2da1f25fd33d37a0df83ed341f4c27bc..6a0dfc6d4905ed64c67fe88afa2a55770f2d4c2b 100644 --- a/drivers/net/wireless/realtek/rtlwifi/debug.c +++ b/drivers/net/wireless/realtek/rtlwifi/debug.c @@ -319,8 +319,8 @@ static ssize_t rtl_debugfs_set_write_reg(struct file *filp, tmp_len = (count > sizeof(tmp) - 1 ? sizeof(tmp) - 1 : count); - if (!buffer || copy_from_user(tmp, buffer, tmp_len)) - return count; + if (copy_from_user(tmp, buffer, tmp_len)) + return -EFAULT; tmp[tmp_len] = '\0'; @@ -328,7 +328,7 @@ static ssize_t rtl_debugfs_set_write_reg(struct file *filp, num = sscanf(tmp, "%x %x %x", &addr, &val, &len); if (num != 3) - return count; + return -EINVAL; switch (len) { case 1: @@ -416,8 +416,8 @@ static ssize_t rtl_debugfs_set_write_rfreg(struct file *filp, tmp_len = (count > sizeof(tmp) - 1 ? sizeof(tmp) - 1 : count); - if (!buffer || copy_from_user(tmp, buffer, tmp_len)) - return count; + if (copy_from_user(tmp, buffer, tmp_len)) + return -EFAULT; tmp[tmp_len] = '\0'; @@ -425,9 +425,9 @@ static ssize_t rtl_debugfs_set_write_rfreg(struct file *filp, &path, &addr, &bitmask, &data); if (num != 4) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, - "Format is \n"); - return count; + rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, + "Format is \n"); + return -EINVAL; } rtl_set_rfreg(hw, path, addr, bitmask, data); diff --git a/drivers/net/wireless/realtek/rtlwifi/debug.h b/drivers/net/wireless/realtek/rtlwifi/debug.h index ad6834af618b47bcfafdd4ecdff5f7e6e5eea9ca..14f822afc89ac6ebebdf19ec6b0f3012de81d517 100644 --- a/drivers/net/wireless/realtek/rtlwifi/debug.h +++ b/drivers/net/wireless/realtek/rtlwifi/debug.h @@ -181,6 +181,10 @@ void _rtl_dbg_print_data(struct rtl_priv *rtlpriv, u64 comp, int level, const char *titlestring, const void *hexdata, int hexdatalen); +#define rtl_dbg(rtlpriv, comp, level, fmt, ...) \ + _rtl_dbg_trace(rtlpriv, comp, level, \ + fmt, ##__VA_ARGS__) + #define RT_TRACE(rtlpriv, comp, level, fmt, ...) \ _rtl_dbg_trace(rtlpriv, comp, level, \ fmt, ##__VA_ARGS__) @@ -197,6 +201,13 @@ void _rtl_dbg_print_data(struct rtl_priv *rtlpriv, u64 comp, int level, struct rtl_priv; +__printf(4, 5) +static inline void rtl_dbg(struct rtl_priv *rtlpriv, + u64 comp, int level, + const char *fmt, ...) +{ +} + __printf(4, 5) static inline void RT_TRACE(struct rtl_priv *rtlpriv, u64 comp, int level, diff --git a/drivers/net/wireless/realtek/rtlwifi/efuse.c b/drivers/net/wireless/realtek/rtlwifi/efuse.c index 9729e51fce381232d2bb18b4aa3f6b32a0daa610..5d8995097ee79d30893b416d7fc51e7ecac64339 100644 --- a/drivers/net/wireless/realtek/rtlwifi/efuse.c +++ b/drivers/net/wireless/realtek/rtlwifi/efuse.c @@ -160,8 +160,8 @@ void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value) const u32 efuse_len = rtlpriv->cfg->maps[EFUSE_REAL_CONTENT_SIZE]; - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, "Addr=%x Data =%x\n", - address, value); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, "Addr=%x Data =%x\n", + address, value); if (address < efuse_len) { rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL], value); @@ -251,9 +251,9 @@ void read_efuse(struct ieee80211_hw *hw, u16 _offset, u16 _size_byte, u8 *pbuf) u8 efuse_usage; if ((_offset + _size_byte) > rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]) { - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, - "read_efuse(): Invalid offset(%#x) with read bytes(%#x)!!\n", - _offset, _size_byte); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, + "%s: Invalid offset(%#x) with read bytes(%#x)!!\n", + __func__, _offset, _size_byte); return; } @@ -416,9 +416,9 @@ bool efuse_shadow_update_chk(struct ieee80211_hw *hw) (EFUSE_MAX_SIZE - rtlpriv->cfg->maps[EFUSE_OOB_PROTECT_BYTES_LEN])) result = false; - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, - "efuse_shadow_update_chk(): totalbytes(%#x), hdr_num(%#x), words_need(%#x), efuse_used(%d)\n", - totalbytes, hdr_num, words_need, efuse_used); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, + "%s: totalbytes(%#x), hdr_num(%#x), words_need(%#x), efuse_used(%d)\n", + __func__, totalbytes, hdr_num, words_need, efuse_used); return result; } @@ -456,7 +456,7 @@ bool efuse_shadow_update(struct ieee80211_hw *hw) u8 word_en = 0x0F; u8 first_pg = false; - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, "\n"); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, "\n"); if (!efuse_shadow_update_chk(hw)) { efuse_read_all_map(hw, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0]); @@ -464,8 +464,8 @@ bool efuse_shadow_update(struct ieee80211_hw *hw) &rtlefuse->efuse_map[EFUSE_INIT_MAP][0], rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]); - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, - "efuse out of capacity!!\n"); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, + "efuse out of capacity!!\n"); return false; } efuse_power_switch(hw, true, true); @@ -503,8 +503,8 @@ bool efuse_shadow_update(struct ieee80211_hw *hw) if (!efuse_pg_packet_write(hw, (u8) offset, word_en, tmpdata)) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "PG section(%#x) fail!!\n", offset); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "PG section(%#x) fail!!\n", offset); break; } } @@ -518,7 +518,7 @@ bool efuse_shadow_update(struct ieee80211_hw *hw) &rtlefuse->efuse_map[EFUSE_INIT_MAP][0], rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]); - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, "\n"); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, "\n"); return true; } @@ -656,8 +656,8 @@ static int efuse_one_byte_write(struct ieee80211_hw *hw, u16 addr, u8 data) struct rtl_priv *rtlpriv = rtl_priv(hw); u8 tmpidx = 0; - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, - "Addr = %x Data=%x\n", addr, data); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, + "Addr = %x Data=%x\n", addr, data); rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1, (u8) (addr & 0xff)); @@ -1036,8 +1036,8 @@ static int efuse_pg_packet_write(struct ieee80211_hw *hw, if (efuse_addr >= (EFUSE_MAX_SIZE - rtlpriv->cfg->maps[EFUSE_OOB_PROTECT_BYTES_LEN])) { - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, - "efuse_addr(%#x) Out of size!!\n", efuse_addr); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, + "efuse_addr(%#x) Out of size!!\n", efuse_addr); } return true; @@ -1077,8 +1077,8 @@ static u8 enable_efuse_data_write(struct ieee80211_hw *hw, u8 tmpdata[8]; memset(tmpdata, 0xff, PGPKT_DATA_SIZE); - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, - "word_en = %x efuse_addr=%x\n", word_en, efuse_addr); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, + "word_en = %x efuse_addr=%x\n", word_en, efuse_addr); if (!(word_en & BIT(0))) { tmpaddr = start_addr; @@ -1281,11 +1281,11 @@ int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv, eeprom_id = *((u16 *)&hwinfo[0]); if (eeprom_id != params[0]) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "EEPROM ID(%#x) is invalid!!\n", eeprom_id); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "EEPROM ID(%#x) is invalid!!\n", eeprom_id); rtlefuse->autoload_failflag = true; } else { - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); rtlefuse->autoload_failflag = false; } @@ -1296,30 +1296,30 @@ int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv, rtlefuse->eeprom_did = *(u16 *)&hwinfo[params[2]]; rtlefuse->eeprom_svid = *(u16 *)&hwinfo[params[3]]; rtlefuse->eeprom_smid = *(u16 *)&hwinfo[params[4]]; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "EEPROMId = 0x%4x\n", eeprom_id); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "EEPROMId = 0x%4x\n", eeprom_id); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid); for (i = 0; i < 6; i += 2) { usvalue = *(u16 *)&hwinfo[params[5] + i]; *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue; } - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); rtlefuse->eeprom_channelplan = *&hwinfo[params[6]]; rtlefuse->eeprom_version = *(u16 *)&hwinfo[params[7]]; rtlefuse->txpwr_fromeprom = true; rtlefuse->eeprom_oemid = *&hwinfo[params[8]]; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid); /* set channel plan to world wide 13 */ rtlefuse->channel_plan = params[9]; diff --git a/drivers/net/wireless/realtek/rtlwifi/pci.c b/drivers/net/wireless/realtek/rtlwifi/pci.c index 83749578fa8b38266ec14057ee88260b929c8d30..0d22bd300f0496f90bd40fb3394f62e0d142c94b 100644 --- a/drivers/net/wireless/realtek/rtlwifi/pci.c +++ b/drivers/net/wireless/realtek/rtlwifi/pci.c @@ -226,8 +226,8 @@ static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) return; if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { - RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, - "PCI(Bridge) UNKNOWN\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, + "PCI(Bridge) UNKNOWN\n"); return; } @@ -276,8 +276,8 @@ static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) return; if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { - RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, - "PCI(Bridge) UNKNOWN\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, + "PCI(Bridge) UNKNOWN\n"); return; } @@ -293,10 +293,10 @@ static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), u_pcibridge_aspmsetting); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "PlatformEnableASPM(): Write reg[%x] = %x\n", - (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), - u_pcibridge_aspmsetting); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "PlatformEnableASPM(): Write reg[%x] = %x\n", + (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), + u_pcibridge_aspmsetting); udelay(50); @@ -353,11 +353,11 @@ static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list, list) { tpcipriv = (struct rtl_pci_priv *)tpriv->priv; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "pcipriv->ndis_adapter.funcnumber %x\n", + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "pcipriv->ndis_adapter.funcnumber %x\n", pcipriv->ndis_adapter.funcnumber); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "tpcipriv->ndis_adapter.funcnumber %x\n", + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "tpcipriv->ndis_adapter.funcnumber %x\n", tpcipriv->ndis_adapter.funcnumber); if (pcipriv->ndis_adapter.busnumber == @@ -372,8 +372,8 @@ static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, } } - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "find_buddy_priv %d\n", find_buddy_priv); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "find_buddy_priv %d\n", find_buddy_priv); if (find_buddy_priv) *buddy_priv = tpriv; @@ -410,8 +410,8 @@ static void rtl_pci_parse_configuration(struct pci_dev *pdev, pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", - pcipriv->ndis_adapter.linkctrl_reg); + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", + pcipriv->ndis_adapter.linkctrl_reg); pci_read_config_byte(pdev, 0x98, &tmp); tmp |= BIT(4); @@ -579,11 +579,11 @@ static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) if (rtlpriv->rtlhal.earlymode_enable) skb_pull(skb, EM_HDR_LEN); - RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, - "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", - ring->idx, - skb_queue_len(&ring->queue), - *(u16 *)(skb->data + 22)); + rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, + "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", + ring->idx, + skb_queue_len(&ring->queue), + *(u16 *)(skb->data + 22)); if (prio == TXCMD_QUEUE) { dev_kfree_skb(skb); @@ -630,10 +630,10 @@ static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) } if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, - "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", - prio, ring->idx, - skb_queue_len(&ring->queue)); + rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, + "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", + prio, ring->idx, + skb_queue_len(&ring->queue)); ieee80211_wake_queue(hw, skb_get_queue_mapping(skb)); } @@ -823,9 +823,9 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift); } else { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "skb->end - skb->tail = %d, len is %d\n", - skb->end - skb->tail, len); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "skb->end - skb->tail = %d, len is %d\n", + skb->end - skb->tail, len); dev_kfree_skb_any(skb); goto new_trx_end; } @@ -946,67 +946,67 @@ static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) /*<1> beacon related */ if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "beacon ok interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "beacon ok interrupt!\n"); if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "beacon err interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "beacon err interrupt!\n"); if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "prepare beacon for interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "prepare beacon for interrupt!\n"); tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); } /*<2> Tx related */ if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "Manage ok interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "Manage ok interrupt!\n"); _rtl_pci_tx_isr(hw, MGNT_QUEUE); } if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "HIGH_QUEUE ok interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "HIGH_QUEUE ok interrupt!\n"); _rtl_pci_tx_isr(hw, HIGH_QUEUE); } if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { rtlpriv->link_info.num_tx_inperiod++; - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "BK Tx OK interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "BK Tx OK interrupt!\n"); _rtl_pci_tx_isr(hw, BK_QUEUE); } if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { rtlpriv->link_info.num_tx_inperiod++; - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "BE TX OK interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "BE TX OK interrupt!\n"); _rtl_pci_tx_isr(hw, BE_QUEUE); } if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { rtlpriv->link_info.num_tx_inperiod++; - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "VI TX OK interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "VI TX OK interrupt!\n"); _rtl_pci_tx_isr(hw, VI_QUEUE); } if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { rtlpriv->link_info.num_tx_inperiod++; - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "Vo TX OK interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "Vo TX OK interrupt!\n"); _rtl_pci_tx_isr(hw, VO_QUEUE); } @@ -1014,8 +1014,8 @@ static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) { rtlpriv->link_info.num_tx_inperiod++; - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "H2C TX OK interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "H2C TX OK interrupt!\n"); _rtl_pci_tx_isr(hw, H2C_QUEUE); } } @@ -1024,34 +1024,34 @@ static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { rtlpriv->link_info.num_tx_inperiod++; - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "CMD TX OK interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "CMD TX OK interrupt!\n"); _rtl_pci_tx_isr(hw, TXCMD_QUEUE); } } /*<3> Rx related */ if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); _rtl_pci_rx_interrupt(hw); } if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "rx descriptor unavailable!\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "rx descriptor unavailable!\n"); _rtl_pci_rx_interrupt(hw); } if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); _rtl_pci_rx_interrupt(hw); } /*<4> fw related*/ if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "firmware interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "firmware interrupt!\n"); queue_delayed_work(rtlpriv->works.rtl_wq, &rtlpriv->works.fwevt_wq, 0); } @@ -1067,8 +1067,8 @@ static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "hsisr interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "hsisr interrupt!\n"); _rtl_pci_hs_interrupt(hw); } } @@ -1272,8 +1272,8 @@ static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, rtlpci->tx_ring[prio].entries = entries; skb_queue_head_init(&rtlpci->tx_ring[prio].queue); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", - prio, desc); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", + prio, desc); /* init every desc in this ring */ if (!rtlpriv->use_new_trx_flow) { @@ -1670,10 +1670,10 @@ static int rtl_pci_tx(struct ieee80211_hw *hw, true, HW_DESC_OWN); if (own == 1 && hw_queue != BEACON_QUEUE) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", - hw_queue, ring->idx, idx, - skb_queue_len(&ring->queue)); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", + hw_queue, ring->idx, idx, + skb_queue_len(&ring->queue)); spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); @@ -1683,8 +1683,8 @@ static int rtl_pci_tx(struct ieee80211_hw *hw, if (rtlpriv->cfg->ops->get_available_desc && rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "get_available_desc fail\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "get_available_desc fail\n"); spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); return skb->len; } @@ -1707,8 +1707,8 @@ static int rtl_pci_tx(struct ieee80211_hw *hw, if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && hw_queue != BEACON_QUEUE) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, - "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", + rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, + "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", hw_queue, ring->idx, idx, skb_queue_len(&ring->queue)); @@ -1815,15 +1815,17 @@ static int rtl_pci_start(struct ieee80211_hw *hw) err = rtlpriv->cfg->ops->hw_init(hw); if (err) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "Failed to config hardware!\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "Failed to config hardware!\n"); + kfree(rtlpriv->btcoexist.btc_context); + kfree(rtlpriv->btcoexist.wifi_only_context); return err; } rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, &rtlmac->retry_long); rtlpriv->cfg->ops->enable_interrupt(hw); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); rtl_init_rx_config(hw); @@ -1834,7 +1836,7 @@ static int rtl_pci_start(struct ieee80211_hw *hw) rtlpci->up_first_time = false; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__); return 0; } @@ -1928,71 +1930,71 @@ static bool _rtl_pci_find_adapter(struct pci_dev *pdev, deviceid == RTL_PCI_8171_DID) { switch (revisionid) { case RTL_PCI_REVISION_ID_8192PCIE: - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "8192 PCI-E is found - vid/did=%x/%x\n", - venderid, deviceid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "8192 PCI-E is found - vid/did=%x/%x\n", + venderid, deviceid); rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; return false; case RTL_PCI_REVISION_ID_8192SE: - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "8192SE is found - vid/did=%x/%x\n", - venderid, deviceid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "8192SE is found - vid/did=%x/%x\n", + venderid, deviceid); rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; break; default: - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "Err: Unknown device - vid/did=%x/%x\n", - venderid, deviceid); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "Err: Unknown device - vid/did=%x/%x\n", + venderid, deviceid); rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; break; } } else if (deviceid == RTL_PCI_8723AE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "8723AE PCI-E is found - vid/did=%x/%x\n", - venderid, deviceid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "8723AE PCI-E is found - vid/did=%x/%x\n", + venderid, deviceid); } else if (deviceid == RTL_PCI_8192CET_DID || deviceid == RTL_PCI_8192CE_DID || deviceid == RTL_PCI_8191CE_DID || deviceid == RTL_PCI_8188CE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "8192C PCI-E is found - vid/did=%x/%x\n", - venderid, deviceid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "8192C PCI-E is found - vid/did=%x/%x\n", + venderid, deviceid); } else if (deviceid == RTL_PCI_8192DE_DID || deviceid == RTL_PCI_8192DE_DID2) { rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "8192D PCI-E is found - vid/did=%x/%x\n", - venderid, deviceid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "8192D PCI-E is found - vid/did=%x/%x\n", + venderid, deviceid); } else if (deviceid == RTL_PCI_8188EE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find adapter, Hardware type is 8188EE\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find adapter, Hardware type is 8188EE\n"); } else if (deviceid == RTL_PCI_8723BE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find adapter, Hardware type is 8723BE\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find adapter, Hardware type is 8723BE\n"); } else if (deviceid == RTL_PCI_8192EE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find adapter, Hardware type is 8192EE\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find adapter, Hardware type is 8192EE\n"); } else if (deviceid == RTL_PCI_8821AE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find adapter, Hardware type is 8821AE\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find adapter, Hardware type is 8821AE\n"); } else if (deviceid == RTL_PCI_8812AE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find adapter, Hardware type is 8812AE\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find adapter, Hardware type is 8812AE\n"); } else if (deviceid == RTL_PCI_8822BE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE; rtlhal->bandset = BAND_ON_BOTH; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find adapter, Hardware type is 8822BE\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find adapter, Hardware type is 8822BE\n"); } else { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "Err: Unknown device - vid/did=%x/%x\n", + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "Err: Unknown device - vid/did=%x/%x\n", venderid, deviceid); rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; @@ -2001,17 +2003,17 @@ static bool _rtl_pci_find_adapter(struct pci_dev *pdev, if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { if (revisionid == 0 || revisionid == 1) { if (revisionid == 0) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find 92DE MAC0\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find 92DE MAC0\n"); rtlhal->interfaceindex = 0; } else if (revisionid == 1) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find 92DE MAC1\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find 92DE MAC1\n"); rtlhal->interfaceindex = 1; } } else { - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", venderid, deviceid, revisionid); rtlhal->interfaceindex = 0; } @@ -2045,9 +2047,9 @@ static bool _rtl_pci_find_adapter(struct pci_dev *pdev, for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { pcipriv->ndis_adapter.pcibridge_vendor = tmp; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "Pci Bridge Vendor is found index: %d\n", - tmp); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "Pci Bridge Vendor is found index: %d\n", + tmp); break; } } @@ -2075,22 +2077,22 @@ static bool _rtl_pci_find_adapter(struct pci_dev *pdev, } } - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", - pcipriv->ndis_adapter.busnumber, - pcipriv->ndis_adapter.devnumber, - pcipriv->ndis_adapter.funcnumber, - pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", + pcipriv->ndis_adapter.busnumber, + pcipriv->ndis_adapter.devnumber, + pcipriv->ndis_adapter.funcnumber, + pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", - pcipriv->ndis_adapter.pcibridge_busnum, - pcipriv->ndis_adapter.pcibridge_devnum, - pcipriv->ndis_adapter.pcibridge_funcnum, - pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], - pcipriv->ndis_adapter.pcibridge_pciehdr_offset, - pcipriv->ndis_adapter.pcibridge_linkctrlreg, - pcipriv->ndis_adapter.amd_l1_patch); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", + pcipriv->ndis_adapter.pcibridge_busnum, + pcipriv->ndis_adapter.pcibridge_devnum, + pcipriv->ndis_adapter.pcibridge_funcnum, + pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], + pcipriv->ndis_adapter.pcibridge_pciehdr_offset, + pcipriv->ndis_adapter.pcibridge_linkctrlreg, + pcipriv->ndis_adapter.amd_l1_patch); rtl_pci_parse_configuration(pdev, hw); list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list); @@ -2118,8 +2120,8 @@ static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) rtlpci->using_msi = true; - RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, - "MSI Interrupt Mode!\n"); + rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, + "MSI Interrupt Mode!\n"); return 0; } @@ -2136,8 +2138,8 @@ static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) return ret; rtlpci->using_msi = false; - RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, - "Pin-based Interrupt Mode!\n"); + rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, + "Pin-based Interrupt Mode!\n"); return 0; } @@ -2264,10 +2266,10 @@ int rtl_pci_probe(struct pci_dev *pdev, goto fail2; } - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", - pmem_start, pmem_len, pmem_flags, - rtlpriv->io.pci_mem_start); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", + pmem_start, pmem_len, pmem_flags, + rtlpriv->io.pci_mem_start); /* Disable Clk Request */ pci_write_config_byte(pdev, 0x81, 0); @@ -2329,9 +2331,9 @@ int rtl_pci_probe(struct pci_dev *pdev, rtlpci = rtl_pcidev(pcipriv); err = rtl_pci_intr_mode_decide(hw); if (err) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "%s: failed to register IRQ handler\n", - wiphy_name(hw->wiphy)); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "%s: failed to register IRQ handler\n", + wiphy_name(hw->wiphy)); goto fail3; } rtlpci->irq_alloc = 1; diff --git a/drivers/net/wireless/realtek/rtlwifi/ps.c b/drivers/net/wireless/realtek/rtlwifi/ps.c index 5f998ea2d5a67db2fb74d0216a3d0100c49ccc61..102f0d0e1cd010d6f8132d7bdfd0de27a3210dca 100644 --- a/drivers/net/wireless/realtek/rtlwifi/ps.c +++ b/drivers/net/wireless/realtek/rtlwifi/ps.c @@ -41,8 +41,8 @@ bool rtl_ps_enable_nic(struct ieee80211_hw *hw) rtlpriv->intf_ops->reset_trx_ring(hw); if (is_hal_stop(rtlhal)) - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "Driver is already down!\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "Driver is already down!\n"); /*<2> Enable Adapter */ if (rtlpriv->cfg->ops->hw_init(hw)) @@ -103,9 +103,9 @@ static bool rtl_ps_set_rf_state(struct ieee80211_hw *hw, if (ppsc->rfchange_inprogress) { spin_unlock(&rtlpriv->locks.rf_ps_lock); - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "RF Change in progress! Wait to set..state_toset(%d).\n", - state_toset); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "RF Change in progress! Wait to set..state_toset(%d).\n", + state_toset); /* Set RF after the previous action is done. */ while (ppsc->rfchange_inprogress) { @@ -217,8 +217,8 @@ void rtl_ips_nic_off_wq_callback(void *data) enum rf_pwrstate rtstate; if (mac->opmode != NL80211_IFTYPE_STATION) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "not station return\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "not station return\n"); return; } @@ -254,8 +254,8 @@ void rtl_ips_nic_off_wq_callback(void *data) !ppsc->swrf_processing && (mac->link_state == MAC80211_NOLINK) && !mac->act_scanning) { - RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, - "IPSEnter(): Turn off RF\n"); + rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, + "IPSEnter(): Turn off RF\n"); ppsc->inactive_pwrstate = ERFOFF; ppsc->in_powersavemode = true; @@ -333,8 +333,8 @@ static bool rtl_get_fwlps_doze(struct ieee80211_hw *hw) ppsc->last_delaylps_stamp_jiffies); if (ps_timediff < 2000) { - RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, - "Delay enter Fw LPS for DHCP, ARP, or EAPOL exchanging state\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, + "Delay enter Fw LPS for DHCP, ARP, or EAPOL exchanging state\n"); return false; } @@ -379,9 +379,9 @@ void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode) if ((ppsc->fwctrl_lps) && ppsc->report_linked) { if (ppsc->dot11_psmode == EACTIVE) { - RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, - "FW LPS leave ps_mode:%x\n", - FW_PS_ACTIVE_MODE); + rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, + "FW LPS leave ps_mode:%x\n", + FW_PS_ACTIVE_MODE); enter_fwlps = false; ppsc->pwr_mode = FW_PS_ACTIVE_MODE; ppsc->smart_ps = 0; @@ -394,9 +394,9 @@ void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode) rtlpriv->btcoexist.btc_ops->btc_lps_notify(rtlpriv, rt_psmode); } else { if (rtl_get_fwlps_doze(hw)) { - RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, - "FW LPS enter ps_mode:%x\n", - ppsc->fwctrl_psmode); + rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, + "FW LPS enter ps_mode:%x\n", + ppsc->fwctrl_psmode); if (rtlpriv->cfg->ops->get_btc_status()) rtlpriv->btcoexist.btc_ops->btc_lps_notify(rtlpriv, rt_psmode); enter_fwlps = true; @@ -446,8 +446,8 @@ static void rtl_lps_enter_core(struct ieee80211_hw *hw) * bt_ccoexist may ask to enter lps. * In normal case, this constraint move to rtl_lps_set_psmode(). */ - RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, - "Enter 802.11 power save mode...\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, + "Enter 802.11 power save mode...\n"); rtl_lps_set_psmode(hw, EAUTOPS); mutex_unlock(&rtlpriv->locks.lps_mutex); @@ -475,8 +475,8 @@ static void rtl_lps_leave_core(struct ieee80211_hw *hw) RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM); } - RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, - "Busy Traffic,Leave 802.11 power save..\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, + "Busy Traffic,Leave 802.11 power save..\n"); rtl_lps_set_psmode(hw, EACTIVE); } @@ -560,8 +560,8 @@ void rtl_swlps_beacon(struct ieee80211_hw *hw, void *data, unsigned int len) queue_delayed_work(rtlpriv->works.rtl_wq, &rtlpriv->works.ps_work, MSECS(5)); } else { - RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, - "u_bufferd: %x, m_buffered: %x\n", u_buffed, m_buffed); + rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, + "u_bufferd: %x, m_buffered: %x\n", u_buffed, m_buffed); } } EXPORT_SYMBOL_GPL(rtl_swlps_beacon); @@ -656,9 +656,9 @@ void rtl_swlps_rf_sleep(struct ieee80211_hw *hw) /* this print should always be dtim_conter = 0 & * sleep = dtim_period, that meaons, we should * awake before every dtim */ - RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, - "dtim_counter:%x will sleep :%d beacon_intv\n", - rtlpriv->psc.dtim_counter, sleep_intv); + rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, + "dtim_counter:%x will sleep :%d beacon_intv\n", + rtlpriv->psc.dtim_counter, sleep_intv); /* we tested that 40ms is enough for sw & hw sw delay */ queue_delayed_work(rtlpriv->works.rtl_wq, &rtlpriv->works.ps_rfon_wq, @@ -769,9 +769,9 @@ static void rtl_p2p_noa_ie(struct ieee80211_hw *hw, void *data, if (ie[0] == 12) { find_p2p_ps_ie = true; if ((noa_len - 2) % 13 != 0) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "P2P notice of absence: invalid length.%d\n", - noa_len); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "P2P notice of absence: invalid length.%d\n", + noa_len); return; } else { noa_num = (noa_len - 2) / 13; @@ -782,8 +782,8 @@ static void rtl_p2p_noa_ie(struct ieee80211_hw *hw, void *data, noa_index = ie[3]; if (rtlpriv->psc.p2p_ps_info.p2p_ps_mode == P2P_PS_NONE || noa_index != p2pinfo->noa_index) { - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, - "update NOA ie.\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, + "update NOA ie.\n"); p2pinfo->noa_index = noa_index; p2pinfo->opp_ps = (ie[4] >> 7); p2pinfo->ctwindow = ie[4] & 0x7F; @@ -854,7 +854,7 @@ static void rtl_p2p_action_ie(struct ieee80211_hw *hw, void *data, if (ie == NULL) return; - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "action frame find P2P IE.\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, "action frame find P2P IE.\n"); /*to find noa ie*/ while (ie + 1 < end) { noa_len = READEF2BYTE((__le16 *)&ie[1]); @@ -862,13 +862,13 @@ static void rtl_p2p_action_ie(struct ieee80211_hw *hw, void *data, return; if (ie[0] == 12) { - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "find NOA IE.\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, "find NOA IE.\n"); RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_LOUD, "noa ie ", ie, noa_len); if ((noa_len - 2) % 13 != 0) { - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, - "P2P notice of absence: invalid length.%d\n", - noa_len); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, + "P2P notice of absence: invalid length.%d\n", + noa_len); return; } else { noa_num = (noa_len - 2) / 13; @@ -926,7 +926,7 @@ void rtl_p2p_ps_cmd(struct ieee80211_hw *hw , u8 p2p_ps_state) struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw)); struct rtl_p2p_ps_info *p2pinfo = &(rtlpriv->psc.p2p_ps_info); - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, " p2p state %x\n" , p2p_ps_state); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, " p2p state %x\n", p2p_ps_state); switch (p2p_ps_state) { case P2P_PS_DISABLE: p2pinfo->p2p_ps_state = p2p_ps_state; @@ -978,18 +978,18 @@ void rtl_p2p_ps_cmd(struct ieee80211_hw *hw , u8 p2p_ps_state) default: break; } - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, - "ctwindow %x oppps %x\n", - p2pinfo->ctwindow , p2pinfo->opp_ps); - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, - "count %x duration %x index %x interval %x start time %x noa num %x\n", - p2pinfo->noa_count_type[0], - p2pinfo->noa_duration[0], - p2pinfo->noa_index, - p2pinfo->noa_interval[0], - p2pinfo->noa_start_time[0], - p2pinfo->noa_num); - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "end\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, + "ctwindow %x oppps %x\n", + p2pinfo->ctwindow, p2pinfo->opp_ps); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, + "count %x duration %x index %x interval %x start time %x noa num %x\n", + p2pinfo->noa_count_type[0], + p2pinfo->noa_duration[0], + p2pinfo->noa_index, + p2pinfo->noa_interval[0], + p2pinfo->noa_start_time[0], + p2pinfo->noa_num); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, "end\n"); } void rtl_p2p_info(struct ieee80211_hw *hw, void *data, unsigned int len) diff --git a/drivers/net/wireless/realtek/rtlwifi/regd.c b/drivers/net/wireless/realtek/rtlwifi/regd.c index 72ca370331fb46ab927467a3fcde6cf495d9b8f5..f89f60ddfebe03ac8505c628fee0033e5a14369f 100644 --- a/drivers/net/wireless/realtek/rtlwifi/regd.c +++ b/drivers/net/wireless/realtek/rtlwifi/regd.c @@ -434,13 +434,13 @@ int rtl_regd_init(struct ieee80211_hw *hw, rtlpriv->regd.country_code = channel_plan_to_country_code(rtlpriv->efuse.channel_plan); - RT_TRACE(rtlpriv, COMP_REGD, DBG_DMESG, - "rtl: EEPROM regdomain: 0x%0x country code: %d\n", - rtlpriv->efuse.channel_plan, rtlpriv->regd.country_code); + rtl_dbg(rtlpriv, COMP_REGD, DBG_DMESG, + "rtl: EEPROM regdomain: 0x%0x country code: %d\n", + rtlpriv->efuse.channel_plan, rtlpriv->regd.country_code); if (rtlpriv->regd.country_code >= COUNTRY_CODE_MAX) { - RT_TRACE(rtlpriv, COMP_REGD, DBG_DMESG, - "rtl: EEPROM indicates invalid country code, world wide 13 should be used\n"); + rtl_dbg(rtlpriv, COMP_REGD, DBG_DMESG, + "rtl: EEPROM indicates invalid country code, world wide 13 should be used\n"); rtlpriv->regd.country_code = COUNTRY_CODE_WORLD_WIDE_13; } @@ -455,9 +455,9 @@ int rtl_regd_init(struct ieee80211_hw *hw, rtlpriv->regd.alpha2[1] = '0'; } - RT_TRACE(rtlpriv, COMP_REGD, DBG_TRACE, - "rtl: Country alpha2 being used: %c%c\n", - rtlpriv->regd.alpha2[0], rtlpriv->regd.alpha2[1]); + rtl_dbg(rtlpriv, COMP_REGD, DBG_TRACE, + "rtl: Country alpha2 being used: %c%c\n", + rtlpriv->regd.alpha2[0], rtlpriv->regd.alpha2[1]); _rtl_regd_init_wiphy(&rtlpriv->regd, wiphy, reg_notifier); @@ -469,7 +469,7 @@ void rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); struct rtl_priv *rtlpriv = rtl_priv(hw); - RT_TRACE(rtlpriv, COMP_REGD, DBG_LOUD, "\n"); + rtl_dbg(rtlpriv, COMP_REGD, DBG_LOUD, "\n"); _rtl_reg_notifier_apply(wiphy, request, &rtlpriv->regd); } diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c index e05af7d6083096588cc5e6c6b66f9f343aeabe28..d54ecbe717e7a6adf94dda7dc4ca797456d2e18b 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c @@ -827,7 +827,7 @@ static void rtl88e_dm_check_edca_turbo(struct ieee80211_hw *hw) } if (rtlpriv->btcoexist.bt_edca_dl != 0) { - edca_be_ul = rtlpriv->btcoexist.bt_edca_dl; + edca_be_dl = rtlpriv->btcoexist.bt_edca_dl; bt_change_edca = true; } diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c index 0b5a06ffa482660cba47c3e9b32bcdd15e47da7c..ed3ef78e5394ed12dacc2c0cb2352e3a5afc1997 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c @@ -663,7 +663,7 @@ static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw) } if (rtlpriv->btcoexist.bt_edca_dl != 0) { - edca_be_ul = rtlpriv->btcoexist.bt_edca_dl; + edca_be_dl = rtlpriv->btcoexist.bt_edca_dl; bt_change_edca = true; } diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c index de98d88199d6ec19b5a11fc6837eaf79436feb61..53734250479c507def03d803f8bf73a452f9e94a 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c @@ -2414,14 +2414,10 @@ void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "Just Read IQK Matrix reg for channel:%d....\n", channel); - if ((rtlphy->iqk_matrix[indexforchannel]. - value[0] != NULL) - /*&&(regea4 != 0) */) + if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0) _rtl92d_phy_patha_fill_iqk_matrix(hw, true, - rtlphy->iqk_matrix[ - indexforchannel].value, 0, - (rtlphy->iqk_matrix[ - indexforchannel].value[0][2] == 0)); + rtlphy->iqk_matrix[indexforchannel].value, 0, + rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0); if (IS_92D_SINGLEPHY(rtlhal->version)) { if ((rtlphy->iqk_matrix[ indexforchannel].value[0][4] != 0) diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c index 42a6fba90ba9144bbcd60764c1fb7283034633cc..fedde63d9bc5b48ba9be61bd5bc0539749d1041c 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c @@ -592,7 +592,7 @@ static void rtl8723e_dm_check_edca_turbo(struct ieee80211_hw *hw) } if (rtlpriv->btcoexist.bt_edca_dl != 0) { - edca_be_ul = rtlpriv->btcoexist.bt_edca_dl; + edca_be_dl = rtlpriv->btcoexist.bt_edca_dl; bt_change_edca = true; } diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c index 176deb2b5386823dc7f3ce7c85cfe4d79c3bbe5e..502ac10cf251b9a0c75cb4b311dfe12e946f657b 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c @@ -1608,7 +1608,7 @@ static void _rtl8821ae_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw } /* string is in decimal */ -static bool _rtl8812ae_get_integer_from_string(char *str, u8 *pint) +static bool _rtl8812ae_get_integer_from_string(const char *str, u8 *pint) { u16 i = 0; *pint = 0; @@ -1626,18 +1626,6 @@ static bool _rtl8812ae_get_integer_from_string(char *str, u8 *pint) return true; } -static bool _rtl8812ae_eq_n_byte(u8 *str1, u8 *str2, u32 num) -{ - if (num == 0) - return false; - while (num > 0) { - num--; - if (str1[num] != str2[num]) - return false; - } - return true; -} - static s8 _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw *hw, u8 band, u8 channel) { @@ -1664,10 +1652,11 @@ static s8 _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw *hw, return channel_index; } -static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregulation, - u8 *pband, u8 *pbandwidth, - u8 *prate_section, u8 *prf_path, - u8 *pchannel, u8 *ppower_limit) +static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, + const char *pregulation, + const char *pband, const char *pbandwidth, + const char *prate_section, const char *prf_path, + const char *pchannel, const char *ppower_limit) { struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_phy *rtlphy = &rtlpriv->phy; @@ -1675,8 +1664,8 @@ static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregul u8 channel_index; s8 power_limit = 0, prev_power_limit, ret; - if (!_rtl8812ae_get_integer_from_string((char *)pchannel, &channel) || - !_rtl8812ae_get_integer_from_string((char *)ppower_limit, + if (!_rtl8812ae_get_integer_from_string(pchannel, &channel) || + !_rtl8812ae_get_integer_from_string(ppower_limit, &power_limit)) { RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Illegal index of pwr_lmt table [chnl %d][val %d]\n", @@ -1686,42 +1675,42 @@ static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregul power_limit = power_limit > MAX_POWER_INDEX ? MAX_POWER_INDEX : power_limit; - if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("FCC"), 3)) + if (strcmp(pregulation, "FCC") == 0) regulation = 0; - else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("MKK"), 3)) + else if (strcmp(pregulation, "MKK") == 0) regulation = 1; - else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("ETSI"), 4)) + else if (strcmp(pregulation, "ETSI") == 0) regulation = 2; - else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("WW13"), 4)) + else if (strcmp(pregulation, "WW13") == 0) regulation = 3; - if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("CCK"), 3)) + if (strcmp(prate_section, "CCK") == 0) rate_section = 0; - else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("OFDM"), 4)) + else if (strcmp(prate_section, "OFDM") == 0) rate_section = 1; - else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("HT"), 2) && - _rtl8812ae_eq_n_byte(prf_path, (u8 *)("1T"), 2)) + else if (strcmp(prate_section, "HT") == 0 && + strcmp(prf_path, "1T") == 0) rate_section = 2; - else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("HT"), 2) && - _rtl8812ae_eq_n_byte(prf_path, (u8 *)("2T"), 2)) + else if (strcmp(prate_section, "HT") == 0 && + strcmp(prf_path, "2T") == 0) rate_section = 3; - else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("VHT"), 3) && - _rtl8812ae_eq_n_byte(prf_path, (u8 *)("1T"), 2)) + else if (strcmp(prate_section, "VHT") == 0 && + strcmp(prf_path, "1T") == 0) rate_section = 4; - else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("VHT"), 3) && - _rtl8812ae_eq_n_byte(prf_path, (u8 *)("2T"), 2)) + else if (strcmp(prate_section, "VHT") == 0 && + strcmp(prf_path, "2T") == 0) rate_section = 5; - if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("20M"), 3)) + if (strcmp(pbandwidth, "20M") == 0) bandwidth = 0; - else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("40M"), 3)) + else if (strcmp(pbandwidth, "40M") == 0) bandwidth = 1; - else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("80M"), 3)) + else if (strcmp(pbandwidth, "80M") == 0) bandwidth = 2; - else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("160M"), 4)) + else if (strcmp(pbandwidth, "160M") == 0) bandwidth = 3; - if (_rtl8812ae_eq_n_byte(pband, (u8 *)("2.4G"), 4)) { + if (strcmp(pband, "2.4G") == 0) { ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, BAND_ON_2_4G, channel); @@ -1745,7 +1734,7 @@ static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregul regulation, bandwidth, rate_section, channel_index, rtlphy->txpwr_limit_2_4g[regulation][bandwidth] [rate_section][channel_index][RF90_PATH_A]); - } else if (_rtl8812ae_eq_n_byte(pband, (u8 *)("5G"), 2)) { + } else if (strcmp(pband, "5G") == 0) { ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, BAND_ON_5G, channel); @@ -1776,10 +1765,10 @@ static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregul } static void _rtl8812ae_phy_config_bb_txpwr_lmt(struct ieee80211_hw *hw, - u8 *regulation, u8 *band, - u8 *bandwidth, u8 *rate_section, - u8 *rf_path, u8 *channel, - u8 *power_limit) + const char *regulation, const char *band, + const char *bandwidth, const char *rate_section, + const char *rf_path, const char *channel, + const char *power_limit) { _rtl8812ae_phy_set_txpower_limit(hw, regulation, band, bandwidth, rate_section, rf_path, channel, @@ -1792,7 +1781,7 @@ static void _rtl8821ae_phy_read_and_config_txpwr_lmt(struct ieee80211_hw *hw) struct rtl_hal *rtlhal = rtl_hal(rtlpriv); u32 i = 0; u32 array_len; - u8 **array; + const char **array; if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { array_len = RTL8812AE_TXPWR_LMT_ARRAY_LEN; @@ -1806,13 +1795,13 @@ static void _rtl8821ae_phy_read_and_config_txpwr_lmt(struct ieee80211_hw *hw) "\n"); for (i = 0; i < array_len; i += 7) { - u8 *regulation = array[i]; - u8 *band = array[i+1]; - u8 *bandwidth = array[i+2]; - u8 *rate = array[i+3]; - u8 *rf_path = array[i+4]; - u8 *chnl = array[i+5]; - u8 *val = array[i+6]; + const char *regulation = array[i]; + const char *band = array[i+1]; + const char *bandwidth = array[i+2]; + const char *rate = array[i+3]; + const char *rf_path = array[i+4]; + const char *chnl = array[i+5]; + const char *val = array[i+6]; _rtl8812ae_phy_config_bb_txpwr_lmt(hw, regulation, band, bandwidth, rate, rf_path, diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.c b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.c index ac44fd5d059773f257978d37b56906df7dbcbb8f..e1e7fa990132aec2ab33ffb251be8dc98720147b 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.c @@ -2917,7 +2917,7 @@ u32 RTL8821AE_AGC_TAB_1TARRAYLEN = ARRAY_SIZE(RTL8821AE_AGC_TAB_ARRAY); * TXPWR_LMT.TXT ******************************************************************************/ -u8 *RTL8812AE_TXPWR_LMT[] = { +const char *RTL8812AE_TXPWR_LMT[] = { "FCC", "2.4G", "20M", "CCK", "1T", "01", "36", "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", @@ -3486,7 +3486,7 @@ u8 *RTL8812AE_TXPWR_LMT[] = { u32 RTL8812AE_TXPWR_LMT_ARRAY_LEN = ARRAY_SIZE(RTL8812AE_TXPWR_LMT); -u8 *RTL8821AE_TXPWR_LMT[] = { +const char *RTL8821AE_TXPWR_LMT[] = { "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.h b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.h index 36c2388b60bca303e3df7405996952a32ca3dcd7..f8550a0122e80b1995f57b28ad2fb0b2acad3e47 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.h +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.h @@ -52,7 +52,7 @@ extern u32 RTL8821AE_AGC_TAB_ARRAY[]; extern u32 RTL8812AE_AGC_TAB_1TARRAYLEN; extern u32 RTL8812AE_AGC_TAB_ARRAY[]; extern u32 RTL8812AE_TXPWR_LMT_ARRAY_LEN; -extern u8 *RTL8812AE_TXPWR_LMT[]; +extern const char *RTL8812AE_TXPWR_LMT[]; extern u32 RTL8821AE_TXPWR_LMT_ARRAY_LEN; -extern u8 *RTL8821AE_TXPWR_LMT[]; +extern const char *RTL8821AE_TXPWR_LMT[]; #endif diff --git a/drivers/net/wireless/realtek/rtlwifi/usb.c b/drivers/net/wireless/realtek/rtlwifi/usb.c index 395671383ca93ad0bf882059e1b43001ec45777d..35ebbd8ca9caf7772d5c99507db1413dffc85600 100644 --- a/drivers/net/wireless/realtek/rtlwifi/usb.c +++ b/drivers/net/wireless/realtek/rtlwifi/usb.c @@ -282,14 +282,14 @@ static int _rtl_usb_init_tx(struct ieee80211_hw *hw) ? USB_HIGH_SPEED_BULK_SIZE : USB_FULL_SPEED_BULK_SIZE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "USB Max Bulk-out Size=%d\n", - rtlusb->max_bulk_out_size); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "USB Max Bulk-out Size=%d\n", + rtlusb->max_bulk_out_size); for (i = 0; i < __RTL_TXQ_NUM; i++) { u32 ep_num = rtlusb->ep_map.ep_mapping[i]; if (!ep_num) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "Invalid endpoint map setting!\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "Invalid endpoint map setting!\n"); return -EINVAL; } } @@ -358,10 +358,10 @@ static int _rtl_usb_init(struct ieee80211_hw *hw) else if (usb_endpoint_dir_out(pep_desc)) rtlusb->out_ep_nums++; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "USB EP(0x%02x), MaxPacketSize=%d, Interval=%d\n", - pep_desc->bEndpointAddress, pep_desc->wMaxPacketSize, - pep_desc->bInterval); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "USB EP(0x%02x), MaxPacketSize=%d, Interval=%d\n", + pep_desc->bEndpointAddress, pep_desc->wMaxPacketSize, + pep_desc->bInterval); } if (rtlusb->in_ep_nums < rtlpriv->cfg->usb_interface_cfg->in_ep_num) { pr_err("Too few input end points found\n"); @@ -960,7 +960,7 @@ static void _rtl_usb_tx_preprocess(struct ieee80211_hw *hw, memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); if (ieee80211_is_auth(fc)) { - RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n"); + rtl_dbg(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n"); } if (rtlpriv->psc.sw_ps_enabled) { diff --git a/drivers/net/wireless/rsi/rsi_91x_coex.c b/drivers/net/wireless/rsi/rsi_91x_coex.c index c8ba148f8c6cf03054385c2ef5077cec18a26e1c..acf4d8cb4b4797abf5c800ee711a9056f442870f 100644 --- a/drivers/net/wireless/rsi/rsi_91x_coex.c +++ b/drivers/net/wireless/rsi/rsi_91x_coex.c @@ -160,6 +160,7 @@ int rsi_coex_attach(struct rsi_common *common) rsi_coex_scheduler_thread, "Coex-Tx-Thread")) { rsi_dbg(ERR_ZONE, "%s: Unable to init tx thrd\n", __func__); + kfree(coex_cb); return -EINVAL; } return 0; diff --git a/drivers/net/wireless/rsi/rsi_91x_mac80211.c b/drivers/net/wireless/rsi/rsi_91x_mac80211.c index 69cd2c2c30ef90deee2c4b548fb8633532c79ecb..4445a53e9f0b8a4b3249fc9d2c23a6e87e53b2ac 100644 --- a/drivers/net/wireless/rsi/rsi_91x_mac80211.c +++ b/drivers/net/wireless/rsi/rsi_91x_mac80211.c @@ -924,7 +924,7 @@ static int rsi_hal_key_config(struct ieee80211_hw *hw, if (status) return status; - if (vif->type == NL80211_IFTYPE_STATION && key->key && + if (vif->type == NL80211_IFTYPE_STATION && (key->cipher == WLAN_CIPHER_SUITE_WEP104 || key->cipher == WLAN_CIPHER_SUITE_WEP40)) { if (!rsi_send_block_unblock_frame(adapter->priv, false)) diff --git a/drivers/net/wireless/rsi/rsi_91x_sdio.c b/drivers/net/wireless/rsi/rsi_91x_sdio.c index 48efe83c58d89cac44e14711253e70c46ec88036..409a3e8305763c10a167604ec378029a2c3c385b 100644 --- a/drivers/net/wireless/rsi/rsi_91x_sdio.c +++ b/drivers/net/wireless/rsi/rsi_91x_sdio.c @@ -1368,9 +1368,6 @@ static void rsi_shutdown(struct device *dev) if (sdev->write_fail) rsi_dbg(INFO_ZONE, "###### Device is not ready #######\n"); - if (rsi_set_sdio_pm_caps(adapter)) - rsi_dbg(INFO_ZONE, "Setting power management caps failed\n"); - rsi_dbg(INFO_ZONE, "***** RSI module shut down *****\n"); } diff --git a/drivers/net/wireless/wl3501_cs.c b/drivers/net/wireless/wl3501_cs.c index f33ece937047381002ac59edc8478b4d187809df..4380c5d8fdd27c865fb9075d144a48e158763872 100644 --- a/drivers/net/wireless/wl3501_cs.c +++ b/drivers/net/wireless/wl3501_cs.c @@ -133,8 +133,8 @@ static const struct { /** * iw_valid_channel - validate channel in regulatory domain - * @reg_comain - regulatory domain - * @channel - channel to validate + * @reg_domain: regulatory domain + * @channel: channel to validate * * Returns 0 if invalid in the specified regulatory domain, non-zero if valid. */ @@ -153,7 +153,7 @@ static int iw_valid_channel(int reg_domain, int channel) /** * iw_default_channel - get default channel for a regulatory domain - * @reg_comain - regulatory domain + * @reg_domain: regulatory domain * * Returns the default channel for a regulatory domain */ @@ -236,6 +236,7 @@ static int wl3501_get_flash_mac_addr(struct wl3501_card *this) /** * wl3501_set_to_wla - Move 'size' bytes from PC to card + * @this: Card * @dest: Card addressing space * @src: PC addressing space * @size: Bytes to move @@ -258,6 +259,7 @@ static void wl3501_set_to_wla(struct wl3501_card *this, u16 dest, void *src, /** * wl3501_get_from_wla - Move 'size' bytes from card to PC + * @this: Card * @src: Card addressing space * @dest: PC addressing space * @size: Bytes to move @@ -454,12 +456,10 @@ static int wl3501_pwr_mgmt(struct wl3501_card *this, int suspend) /** * wl3501_send_pkt - Send a packet. - * @this - card - * - * Send a packet. - * - * data = Ethernet raw frame. (e.g. data[0] - data[5] is Dest MAC Addr, + * @this: Card + * @data: Ethernet raw frame. (e.g. data[0] - data[5] is Dest MAC Addr, * data[6] - data[11] is Src MAC Addr) + * @len: Packet length * Ref: IEEE 802.11 */ static int wl3501_send_pkt(struct wl3501_card *this, u8 *data, u16 len) @@ -722,7 +722,7 @@ static void wl3501_mgmt_scan_confirm(struct wl3501_card *this, u16 addr) /** * wl3501_block_interrupt - Mask interrupt from SUTRO - * @this - card + * @this: Card * * Mask interrupt from SUTRO. (i.e. SUTRO cannot interrupt the HOST) * Return: 1 if interrupt is originally enabled @@ -739,7 +739,7 @@ static int wl3501_block_interrupt(struct wl3501_card *this) /** * wl3501_unblock_interrupt - Enable interrupt from SUTRO - * @this - card + * @this: Card * * Enable interrupt from SUTRO. (i.e. SUTRO can interrupt the HOST) * Return: 1 if interrupt is originally enabled @@ -1113,8 +1113,8 @@ static inline void wl3501_ack_interrupt(struct wl3501_card *this) /** * wl3501_interrupt - Hardware interrupt from card. - * @irq - Interrupt number - * @dev_id - net_device + * @irq: Interrupt number + * @dev_id: net_device * * We must acknowledge the interrupt as soon as possible, and block the * interrupt from the same card immediately to prevent re-entry. @@ -1252,7 +1252,7 @@ static int wl3501_close(struct net_device *dev) /** * wl3501_reset - Reset the SUTRO. - * @dev - network device + * @dev: network device * * It is almost the same as wl3501_open(). In fact, we may just wl3501_close() * and wl3501_open() again, but I wouldn't like to free_irq() when the driver @@ -1329,7 +1329,7 @@ static netdev_tx_t wl3501_hard_start_xmit(struct sk_buff *skb, } else { ++dev->stats.tx_packets; dev->stats.tx_bytes += skb->len; - kfree_skb(skb); + dev_kfree_skb_irq(skb); if (this->tx_buffer_cnt < 2) netif_stop_queue(dev); @@ -1415,7 +1415,7 @@ static struct iw_statistics *wl3501_get_wireless_stats(struct net_device *dev) /** * wl3501_detach - deletes a driver "instance" - * @link - FILL_IN + * @link: FILL_IN * * This deletes a driver "instance". The device is de-registered with Card * Services. If it has been released, all local data structures are freed. @@ -1436,9 +1436,7 @@ static void wl3501_detach(struct pcmcia_device *link) wl3501_release(link); unregister_netdev(dev); - - if (link->priv) - free_netdev(link->priv); + free_netdev(dev); } static int wl3501_get_name(struct net_device *dev, struct iw_request_info *info, @@ -1865,6 +1863,7 @@ static int wl3501_probe(struct pcmcia_device *p_dev) { struct net_device *dev; struct wl3501_card *this; + int ret; /* The io structure describes IO port mapping */ p_dev->resource[0]->end = 16; @@ -1876,8 +1875,7 @@ static int wl3501_probe(struct pcmcia_device *p_dev) dev = alloc_etherdev(sizeof(struct wl3501_card)); if (!dev) - goto out_link; - + return -ENOMEM; dev->netdev_ops = &wl3501_netdev_ops; dev->watchdog_timeo = 5 * HZ; @@ -1890,9 +1888,15 @@ static int wl3501_probe(struct pcmcia_device *p_dev) netif_stop_queue(dev); p_dev->priv = dev; - return wl3501_config(p_dev); -out_link: - return -ENOMEM; + ret = wl3501_config(p_dev); + if (ret) + goto out_free_etherdev; + + return 0; + +out_free_etherdev: + free_netdev(dev); + return ret; } static int wl3501_config(struct pcmcia_device *link) @@ -1948,8 +1952,7 @@ static int wl3501_config(struct pcmcia_device *link) goto failed; } - for (i = 0; i < 6; i++) - dev->dev_addr[i] = ((char *)&this->mac_addr)[i]; + eth_hw_addr_set(dev, this->mac_addr); /* print probe information */ printk(KERN_INFO "%s: wl3501 @ 0x%3.3x, IRQ %d, " diff --git a/drivers/net/xen-netback/common.h b/drivers/net/xen-netback/common.h index 92d30ebdb1112722ad204257882a2ab2343342c0..2b984c5bae24fb4b4bb1702a380102e33412d6ac 100644 --- a/drivers/net/xen-netback/common.h +++ b/drivers/net/xen-netback/common.h @@ -166,7 +166,7 @@ struct xenvif_queue { /* Per-queue data for xenvif */ struct pending_tx_info pending_tx_info[MAX_PENDING_REQS]; grant_handle_t grant_tx_handle[MAX_PENDING_REQS]; - struct gnttab_copy tx_copy_ops[MAX_PENDING_REQS]; + struct gnttab_copy tx_copy_ops[2 * MAX_PENDING_REQS]; struct gnttab_map_grant_ref tx_map_ops[MAX_PENDING_REQS]; struct gnttab_unmap_grant_ref tx_unmap_ops[MAX_PENDING_REQS]; /* passed to gnttab_[un]map_refs with pages under (un)mapping */ diff --git a/drivers/net/xen-netback/interface.c b/drivers/net/xen-netback/interface.c index df20270827631069f53232d2c120f57d84575e9f..fadbde1d21add4a7a34ce9fd0990bf3d5a1c6a42 100644 --- a/drivers/net/xen-netback/interface.c +++ b/drivers/net/xen-netback/interface.c @@ -41,7 +41,6 @@ #include #include -#define XENVIF_QUEUE_LENGTH 32 #define XENVIF_NAPI_WEIGHT 64 /* Number of bytes allowed on the internal guest Rx queue. */ @@ -526,8 +525,6 @@ struct xenvif *xenvif_alloc(struct device *parent, domid_t domid, dev->features = dev->hw_features | NETIF_F_RXCSUM; dev->ethtool_ops = &xenvif_ethtool_ops; - dev->tx_queue_len = XENVIF_QUEUE_LENGTH; - dev->min_mtu = ETH_MIN_MTU; dev->max_mtu = ETH_MAX_MTU - VLAN_ETH_HLEN; diff --git a/drivers/net/xen-netback/netback.c b/drivers/net/xen-netback/netback.c index fc389f2bba7aa48a380fe71c042c71f36dcb7f1b..6faf36bfdeafc6fd0591244a6caa10c88c811e1f 100644 --- a/drivers/net/xen-netback/netback.c +++ b/drivers/net/xen-netback/netback.c @@ -327,6 +327,7 @@ static int xenvif_count_requests(struct xenvif_queue *queue, struct xenvif_tx_cb { u16 copy_pending_idx[XEN_NETBK_LEGACY_SLOTS_MAX + 1]; u8 copy_count; + u32 split_mask; }; #define XENVIF_TX_CB(skb) ((struct xenvif_tx_cb *)(skb)->cb) @@ -354,6 +355,8 @@ static inline struct sk_buff *xenvif_alloc_skb(unsigned int size) struct sk_buff *skb = alloc_skb(size + NET_SKB_PAD + NET_IP_ALIGN, GFP_ATOMIC | __GFP_NOWARN); + + BUILD_BUG_ON(sizeof(*XENVIF_TX_CB(skb)) > sizeof(skb->cb)); if (unlikely(skb == NULL)) return NULL; @@ -386,14 +389,16 @@ static void xenvif_get_requests(struct xenvif_queue *queue, struct gnttab_map_grant_ref *gop = queue->tx_map_ops + *map_ops; struct xen_netif_tx_request *txp = first; - nr_slots = shinfo->nr_frags + 1; + nr_slots = shinfo->nr_frags + frag_overflow + 1; copy_count(skb) = 0; + XENVIF_TX_CB(skb)->split_mask = 0; /* Create copy ops for exactly data_len bytes into the skb head. */ __skb_put(skb, data_len); while (data_len > 0) { int amount = data_len > txp->size ? txp->size : data_len; + bool split = false; cop->source.u.ref = txp->gref; cop->source.domid = queue->vif->domid; @@ -406,6 +411,13 @@ static void xenvif_get_requests(struct xenvif_queue *queue, cop->dest.u.gmfn = virt_to_gfn(skb->data + skb_headlen(skb) - data_len); + /* Don't cross local page boundary! */ + if (cop->dest.offset + amount > XEN_PAGE_SIZE) { + amount = XEN_PAGE_SIZE - cop->dest.offset; + XENVIF_TX_CB(skb)->split_mask |= 1U << copy_count(skb); + split = true; + } + cop->len = amount; cop->flags = GNTCOPY_source_gref; @@ -413,7 +425,8 @@ static void xenvif_get_requests(struct xenvif_queue *queue, pending_idx = queue->pending_ring[index]; callback_param(queue, pending_idx).ctx = NULL; copy_pending_idx(skb, copy_count(skb)) = pending_idx; - copy_count(skb)++; + if (!split) + copy_count(skb)++; cop++; data_len -= amount; @@ -434,15 +447,16 @@ static void xenvif_get_requests(struct xenvif_queue *queue, nr_slots--; } else { /* The copy op partially covered the tx_request. - * The remainder will be mapped. + * The remainder will be mapped or copied in the next + * iteration. */ txp->offset += amount; txp->size -= amount; } } - for (shinfo->nr_frags = 0; shinfo->nr_frags < nr_slots; - shinfo->nr_frags++, gop++) { + for (shinfo->nr_frags = 0; nr_slots > 0 && shinfo->nr_frags < MAX_SKB_FRAGS; + shinfo->nr_frags++, gop++, nr_slots--) { index = pending_index(queue->pending_cons++); pending_idx = queue->pending_ring[index]; xenvif_tx_create_map_op(queue, pending_idx, txp, @@ -455,12 +469,12 @@ static void xenvif_get_requests(struct xenvif_queue *queue, txp++; } - if (frag_overflow) { + if (nr_slots > 0) { shinfo = skb_shinfo(nskb); frags = shinfo->frags; - for (shinfo->nr_frags = 0; shinfo->nr_frags < frag_overflow; + for (shinfo->nr_frags = 0; shinfo->nr_frags < nr_slots; shinfo->nr_frags++, txp++, gop++) { index = pending_index(queue->pending_cons++); pending_idx = queue->pending_ring[index]; @@ -471,6 +485,11 @@ static void xenvif_get_requests(struct xenvif_queue *queue, } skb_shinfo(skb)->frag_list = nskb; + } else if (nskb) { + /* A frag_list skb was allocated but it is no longer needed + * because enough slots were converted to copy ops above. + */ + kfree_skb(nskb); } (*copy_ops) = cop - queue->tx_copy_ops; @@ -532,6 +551,13 @@ static int xenvif_tx_check_gop(struct xenvif_queue *queue, pending_idx = copy_pending_idx(skb, i); newerr = (*gopp_copy)->status; + + /* Split copies need to be handled together. */ + if (XENVIF_TX_CB(skb)->split_mask & (1U << i)) { + (*gopp_copy)++; + if (!newerr) + newerr = (*gopp_copy)->status; + } if (likely(!newerr)) { /* The first frag might still have this slot mapped */ if (i < copy_count(skb) - 1 || !sharedslot) @@ -968,10 +994,8 @@ static void xenvif_tx_build_gops(struct xenvif_queue *queue, /* No crossing a page as the payload mustn't fragment. */ if (unlikely((txreq.offset + txreq.size) > XEN_PAGE_SIZE)) { - netdev_err(queue->vif->dev, - "txreq.offset: %u, size: %u, end: %lu\n", - txreq.offset, txreq.size, - (unsigned long)(txreq.offset&~XEN_PAGE_MASK) + txreq.size); + netdev_err(queue->vif->dev, "Cross page boundary, txreq.offset: %u, size: %u\n", + txreq.offset, txreq.size); xenvif_fatal_tx_err(queue->vif); break; } diff --git a/drivers/nfc/fdp/i2c.c b/drivers/nfc/fdp/i2c.c index 159dc9ed0bad9389568b9d04b71547913c744aba..6c15005b2540a676ab0a5cfb0a0192e0011cdc37 100644 --- a/drivers/nfc/fdp/i2c.c +++ b/drivers/nfc/fdp/i2c.c @@ -273,6 +273,9 @@ static void fdp_nci_i2c_read_device_properties(struct device *dev, len, sizeof(**fw_vsc_cfg), GFP_KERNEL); + if (!*fw_vsc_cfg) + goto alloc_err; + r = device_property_read_u8_array(dev, FDP_DP_FW_VSC_CFG_NAME, *fw_vsc_cfg, len); @@ -286,6 +289,7 @@ static void fdp_nci_i2c_read_device_properties(struct device *dev, *fw_vsc_cfg = NULL; } +alloc_err: dev_dbg(dev, "Clock type: %d, clock frequency: %d, VSC: %s", *clock_type, *clock_freq, *fw_vsc_cfg != NULL ? "yes" : "no"); } diff --git a/drivers/nfc/nfcsim.c b/drivers/nfc/nfcsim.c index 533e3aa6275cddd892555d56a2288642be5e69cd..cf07b366500e9b50b65c5a37bd6d400012288561 100644 --- a/drivers/nfc/nfcsim.c +++ b/drivers/nfc/nfcsim.c @@ -345,10 +345,6 @@ static struct dentry *nfcsim_debugfs_root; static void nfcsim_debugfs_init(void) { nfcsim_debugfs_root = debugfs_create_dir("nfcsim", NULL); - - if (!nfcsim_debugfs_root) - pr_err("Could not create debugfs entry\n"); - } static void nfcsim_debugfs_remove(void) diff --git a/drivers/nfc/pn533/usb.c b/drivers/nfc/pn533/usb.c index c7da364b63584dd6fe963c62a1aad9d87bbc7182..a2d61d82402468218626ca9fb911922bdfb4fb7b 100644 --- a/drivers/nfc/pn533/usb.c +++ b/drivers/nfc/pn533/usb.c @@ -187,6 +187,7 @@ static int pn533_usb_send_frame(struct pn533 *dev, print_hex_dump_debug("PN533 TX: ", DUMP_PREFIX_NONE, 16, 1, out->data, out->len, false); + arg.phy = phy; init_completion(&arg.done); cntx = phy->out_urb->context; phy->out_urb->context = &arg; diff --git a/drivers/nfc/st-nci/ndlc.c b/drivers/nfc/st-nci/ndlc.c index f26d938d240f03dbb27889fc101d552511ea9d92..12d73f9dbe9f37e3ef208971b16dee783d362312 100644 --- a/drivers/nfc/st-nci/ndlc.c +++ b/drivers/nfc/st-nci/ndlc.c @@ -297,13 +297,15 @@ EXPORT_SYMBOL(ndlc_probe); void ndlc_remove(struct llt_ndlc *ndlc) { - st_nci_remove(ndlc->ndev); - /* cancel timers */ del_timer_sync(&ndlc->t1_timer); del_timer_sync(&ndlc->t2_timer); ndlc->t2_active = false; ndlc->t1_active = false; + /* cancel work */ + cancel_work_sync(&ndlc->sm_work); + + st_nci_remove(ndlc->ndev); skb_queue_purge(&ndlc->rcv_q); skb_queue_purge(&ndlc->send_q); diff --git a/drivers/nfc/st-nci/se.c b/drivers/nfc/st-nci/se.c index cdf9e915c974b5414da1e31319196dcfc49f7f2e..f702aa9c7cf5bd589f0c3271928aca132096a0d2 100644 --- a/drivers/nfc/st-nci/se.c +++ b/drivers/nfc/st-nci/se.c @@ -676,6 +676,12 @@ int st_nci_se_io(struct nci_dev *ndev, u32 se_idx, ST_NCI_EVT_TRANSMIT_DATA, apdu, apdu_length); default: + /* Need to free cb_context here as at the moment we can't + * clearly indicate to the caller if the callback function + * would be called (and free it) or not. In both cases a + * negative value may be returned to the caller. + */ + kfree(cb_context); return -ENODEV; } } diff --git a/drivers/nfc/st21nfca/se.c b/drivers/nfc/st21nfca/se.c index 1754197c58f49c554c7326654f4e6e72144ab27c..8b12bfb97d053c31169c62f0db6b01a53a79e289 100644 --- a/drivers/nfc/st21nfca/se.c +++ b/drivers/nfc/st21nfca/se.c @@ -247,6 +247,12 @@ int st21nfca_hci_se_io(struct nfc_hci_dev *hdev, u32 se_idx, ST21NFCA_EVT_TRANSMIT_DATA, apdu, apdu_length); default: + /* Need to free cb_context here as at the moment we can't + * clearly indicate to the caller if the callback function + * would be called (and free it) or not. In both cases a + * negative value may be returned to the caller. + */ + kfree(cb_context); return -ENODEV; } } diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_amd.c index 0b1fbb5dba9b6387094c2338db59d2ccfd15863a..7de761680393504456b466c6b546b3aa07b7e683 100644 --- a/drivers/ntb/hw/amd/ntb_hw_amd.c +++ b/drivers/ntb/hw/amd/ntb_hw_amd.c @@ -1139,12 +1139,17 @@ static struct pci_driver amd_ntb_pci_driver = { static int __init amd_ntb_pci_driver_init(void) { + int ret; pr_info("%s %s\n", NTB_DESC, NTB_VER); if (debugfs_initialized()) debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL); - return pci_register_driver(&amd_ntb_pci_driver); + ret = pci_register_driver(&amd_ntb_pci_driver); + if (ret) + debugfs_remove_recursive(debugfs_dir); + + return ret; } module_init(amd_ntb_pci_driver_init); diff --git a/drivers/ntb/hw/idt/ntb_hw_idt.c b/drivers/ntb/hw/idt/ntb_hw_idt.c index a67ef23e81bca70127edb92afcb78662ad3dc0e3..82e08f583980b4af7b891b7181905a7819a80931 100644 --- a/drivers/ntb/hw/idt/ntb_hw_idt.c +++ b/drivers/ntb/hw/idt/ntb_hw_idt.c @@ -2692,6 +2692,7 @@ static struct pci_driver idt_pci_driver = { static int __init idt_pci_driver_init(void) { + int ret; pr_info("%s %s\n", NTB_DESC, NTB_VER); /* Create the top DebugFS directory if the FS is initialized */ @@ -2699,7 +2700,11 @@ static int __init idt_pci_driver_init(void) dbgfs_topdir = debugfs_create_dir(KBUILD_MODNAME, NULL); /* Register the NTB hardware driver to handle the PCI device */ - return pci_register_driver(&idt_pci_driver); + ret = pci_register_driver(&idt_pci_driver); + if (ret) + debugfs_remove_recursive(dbgfs_topdir); + + return ret; } module_init(idt_pci_driver_init); diff --git a/drivers/ntb/hw/intel/ntb_hw_gen1.c b/drivers/ntb/hw/intel/ntb_hw_gen1.c index 2ad263f708da7ab68b12c9767058df9505501013..084bd1d1ac1dc44c7378d8606131495239d4a089 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen1.c +++ b/drivers/ntb/hw/intel/ntb_hw_gen1.c @@ -2052,12 +2052,17 @@ static struct pci_driver intel_ntb_pci_driver = { static int __init intel_ntb_pci_driver_init(void) { + int ret; pr_info("%s %s\n", NTB_DESC, NTB_VER); if (debugfs_initialized()) debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL); - return pci_register_driver(&intel_ntb_pci_driver); + ret = pci_register_driver(&intel_ntb_pci_driver); + if (ret) + debugfs_remove_recursive(debugfs_dir); + + return ret; } module_init(intel_ntb_pci_driver_init); diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index 9398959664769b5f6cd3c79e4914199d1cf35f0d..9ac97d560c1c35fd00d92122132fe2e20cba3adb 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -393,7 +393,7 @@ int ntb_transport_register_client_dev(char *device_name) rc = device_register(dev); if (rc) { - kfree(client_dev); + put_device(dev); goto err; } @@ -746,7 +746,7 @@ static int ntb_set_mw(struct ntb_transport_ctx *nt, int num_mw, return 0; } -static void ntb_qp_link_down_reset(struct ntb_transport_qp *qp) +static void ntb_qp_link_context_reset(struct ntb_transport_qp *qp) { qp->link_is_up = false; qp->active = false; @@ -769,6 +769,13 @@ static void ntb_qp_link_down_reset(struct ntb_transport_qp *qp) qp->tx_async = 0; } +static void ntb_qp_link_down_reset(struct ntb_transport_qp *qp) +{ + ntb_qp_link_context_reset(qp); + if (qp->remote_rx_info) + qp->remote_rx_info->entry = qp->rx_max_entry - 1; +} + static void ntb_qp_link_cleanup(struct ntb_transport_qp *qp) { struct ntb_transport_ctx *nt = qp->transport; @@ -993,7 +1000,7 @@ static int ntb_transport_init_queue(struct ntb_transport_ctx *nt, qp->ndev = nt->ndev; qp->client_ready = false; qp->event_handler = NULL; - ntb_qp_link_down_reset(qp); + ntb_qp_link_context_reset(qp); if (mw_num < qp_count % mw_count) num_qps_mw = qp_count / mw_count + 1; @@ -2046,9 +2053,13 @@ int ntb_transport_tx_enqueue(struct ntb_transport_qp *qp, void *cb, void *data, struct ntb_queue_entry *entry; int rc; - if (!qp || !qp->link_is_up || !len) + if (!qp || !len) return -EINVAL; + /* If the qp link is down already, just ignore. */ + if (!qp->link_is_up) + return 0; + entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q); if (!entry) { qp->tx_err_no_buf++; @@ -2188,7 +2199,7 @@ unsigned int ntb_transport_tx_free_entry(struct ntb_transport_qp *qp) unsigned int head = qp->tx_index; unsigned int tail = qp->remote_rx_info->entry; - return tail > head ? tail - head : qp->tx_max_entry + tail - head; + return tail >= head ? tail - head : qp->tx_max_entry + tail - head; } EXPORT_SYMBOL_GPL(ntb_transport_tx_free_entry); diff --git a/drivers/ntb/test/ntb_tool.c b/drivers/ntb/test/ntb_tool.c index 6301aa413c3b8a7d955518a8781eed8f7b87f711..1f641465462212b1c7d844d58564d894fd89ecc7 100644 --- a/drivers/ntb/test/ntb_tool.c +++ b/drivers/ntb/test/ntb_tool.c @@ -998,6 +998,8 @@ static int tool_init_mws(struct tool_ctx *tc) tc->peers[pidx].outmws = devm_kcalloc(&tc->ntb->dev, tc->peers[pidx].outmw_cnt, sizeof(*tc->peers[pidx].outmws), GFP_KERNEL); + if (tc->peers[pidx].outmws == NULL) + return -ENOMEM; for (widx = 0; widx < tc->peers[pidx].outmw_cnt; widx++) { tc->peers[pidx].outmws[widx].pidx = pidx; diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c index e76b3eb5faf3e4b45ff1a7019d4fa84d19373069..d7ad43007cea7d7909ea3194b89a15bc4885da09 100644 --- a/drivers/nvdimm/region_devs.c +++ b/drivers/nvdimm/region_devs.c @@ -949,7 +949,8 @@ unsigned int nd_region_acquire_lane(struct nd_region *nd_region) { unsigned int cpu, lane; - cpu = get_cpu(); + migrate_disable(); + cpu = smp_processor_id(); if (nd_region->num_lanes < nr_cpu_ids) { struct nd_percpu_lane *ndl_lock, *ndl_count; @@ -968,16 +969,15 @@ EXPORT_SYMBOL(nd_region_acquire_lane); void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane) { if (nd_region->num_lanes < nr_cpu_ids) { - unsigned int cpu = get_cpu(); + unsigned int cpu = smp_processor_id(); struct nd_percpu_lane *ndl_lock, *ndl_count; ndl_count = per_cpu_ptr(nd_region->lane, cpu); ndl_lock = per_cpu_ptr(nd_region->lane, lane); if (--ndl_count->count == 0) spin_unlock(&ndl_lock->lock); - put_cpu(); } - put_cpu(); + migrate_enable(); } EXPORT_SYMBOL(nd_region_release_lane); diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index b06d2b6bd3febc5417372d134df245be989c6d95..163497ef48fd7dc06d07655ea7a5bad51c08dd0c 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -2501,8 +2501,6 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) size_t alloc_size; node = dev_to_node(&pdev->dev); - if (node == NUMA_NO_NODE) - set_dev_node(&pdev->dev, first_memory_node); dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); if (!dev) diff --git a/drivers/nvme/target/core.c b/drivers/nvme/target/core.c index 80b5aae1bdc9b0b6005b7f326e5083fbda1f3efe..aff18a3f002f9f97eb2c331d614b42539a0443f5 100644 --- a/drivers/nvme/target/core.c +++ b/drivers/nvme/target/core.c @@ -528,8 +528,10 @@ static void __nvmet_req_complete(struct nvmet_req *req, u16 status) void nvmet_req_complete(struct nvmet_req *req, u16 status) { + struct nvmet_sq *sq = req->sq; + __nvmet_req_complete(req, status); - percpu_ref_put(&req->sq->ref); + percpu_ref_put(&sq->ref); } EXPORT_SYMBOL_GPL(nvmet_req_complete); diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index 09281aca86c29e181fa35d570869b11c9051b196..74397381e7d7a1dd29ffd1d5bcd9c3631969f46d 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -439,7 +439,7 @@ static const struct ocotp_params imx6sl_params = { }; static const struct ocotp_params imx6sll_params = { - .nregs = 128, + .nregs = 80, .bank_address_words = 0, .set_timing = imx_ocotp_set_imx6_timing, }; @@ -451,7 +451,7 @@ static const struct ocotp_params imx6sx_params = { }; static const struct ocotp_params imx6ul_params = { - .nregs = 128, + .nregs = 144, .bank_address_words = 0, .set_timing = imx_ocotp_set_imx6_timing, }; diff --git a/drivers/of/device.c b/drivers/of/device.c index 258742830e366215c5f26506a0afe1e79a007952..566d8af05157d461fd37676e746bd20d36a8c2e2 100644 --- a/drivers/of/device.c +++ b/drivers/of/device.c @@ -258,12 +258,15 @@ int of_device_request_module(struct device *dev) if (size < 0) return size; - str = kmalloc(size + 1, GFP_KERNEL); + /* Reserve an additional byte for the trailing '\0' */ + size++; + + str = kmalloc(size, GFP_KERNEL); if (!str) return -ENOMEM; of_device_get_modalias(dev, str, size); - str[size] = '\0'; + str[size - 1] = '\0'; ret = request_module(str); kfree(str); diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c index 29f17c3449aa44a62c5af58562bd7075a3ef777d..2515ce39300592cf94faa745db0b5f370f168863 100644 --- a/drivers/of/unittest.c +++ b/drivers/of/unittest.c @@ -52,7 +52,7 @@ static void __init of_unittest_find_node_by_name(void) np = of_find_node_by_path("/testcase-data"); name = kasprintf(GFP_KERNEL, "%pOF", np); - unittest(np && !strcmp("/testcase-data", name), + unittest(np && name && !strcmp("/testcase-data", name), "find /testcase-data failed\n"); of_node_put(np); kfree(name); @@ -63,14 +63,14 @@ static void __init of_unittest_find_node_by_name(void) np = of_find_node_by_path("/testcase-data/phandle-tests/consumer-a"); name = kasprintf(GFP_KERNEL, "%pOF", np); - unittest(np && !strcmp("/testcase-data/phandle-tests/consumer-a", name), + unittest(np && name && !strcmp("/testcase-data/phandle-tests/consumer-a", name), "find /testcase-data/phandle-tests/consumer-a failed\n"); of_node_put(np); kfree(name); np = of_find_node_by_path("testcase-alias"); name = kasprintf(GFP_KERNEL, "%pOF", np); - unittest(np && !strcmp("/testcase-data", name), + unittest(np && name && !strcmp("/testcase-data", name), "find testcase-alias failed\n"); of_node_put(np); kfree(name); @@ -81,7 +81,7 @@ static void __init of_unittest_find_node_by_name(void) np = of_find_node_by_path("testcase-alias/phandle-tests/consumer-a"); name = kasprintf(GFP_KERNEL, "%pOF", np); - unittest(np && !strcmp("/testcase-data/phandle-tests/consumer-a", name), + unittest(np && name && !strcmp("/testcase-data/phandle-tests/consumer-a", name), "find testcase-alias/phandle-tests/consumer-a failed\n"); of_node_put(np); kfree(name); @@ -1138,6 +1138,8 @@ static void attach_node_and_children(struct device_node *np) const char *full_name; full_name = kasprintf(GFP_KERNEL, "%pOF", np); + if (!full_name) + return; if (!strcmp(full_name, "/__local_fixups__") || !strcmp(full_name, "/__fixups__")) { @@ -1571,7 +1573,7 @@ static int __init of_unittest_apply_revert_overlay_check(int overlay_nr, } /* unittest device must be again in before state */ - if (of_unittest_device_exists(unittest_nr, PDEV_OVERLAY) != before) { + if (of_unittest_device_exists(unittest_nr, ovtype) != before) { unittest(0, "%s with device @\"%s\" %s\n", overlay_name_from_nr(overlay_nr), unittest_path(unittest_nr, ovtype), diff --git a/drivers/parisc/iosapic.c b/drivers/parisc/iosapic.c index eb9137faccf74e09f98731014b4d19d0570387bc..4cc08d13b82fae284837ed44ffd271fbfa213126 100644 --- a/drivers/parisc/iosapic.c +++ b/drivers/parisc/iosapic.c @@ -216,9 +216,9 @@ static inline void iosapic_write(void __iomem *iosapic, unsigned int reg, u32 va static DEFINE_SPINLOCK(iosapic_lock); -static inline void iosapic_eoi(void __iomem *addr, unsigned int data) +static inline void iosapic_eoi(__le32 __iomem *addr, __le32 data) { - __raw_writel(data, addr); + __raw_writel((__force u32)data, addr); } /* diff --git a/drivers/parisc/iosapic_private.h b/drivers/parisc/iosapic_private.h index 6e05e30a2450a052c9d1f4d0d460826a10514b52..7a928c03d5201d6284cba250cbda20a1c1e1df40 100644 --- a/drivers/parisc/iosapic_private.h +++ b/drivers/parisc/iosapic_private.h @@ -132,8 +132,8 @@ struct iosapic_irt { struct vector_info { struct iosapic_info *iosapic; /* I/O SAPIC this vector is on */ struct irt_entry *irte; /* IRT entry */ - u32 __iomem *eoi_addr; /* precalculate EOI reg address */ - u32 eoi_data; /* IA64: ? PA: swapped txn_data */ + __le32 __iomem *eoi_addr; /* precalculate EOI reg address */ + __le32 eoi_data; /* IA64: ? PA: swapped txn_data */ int txn_irq; /* virtual IRQ number for processor */ ulong txn_addr; /* IA64: id_eid PA: partial HPA */ u32 txn_data; /* CPU interrupt bit */ diff --git a/drivers/parisc/led.c b/drivers/parisc/led.c index 6a0833f5923c1d8476975bd58a58853d6ce113a1..8a5a73d7540069065bb8506b74e742360da2f5ca 100644 --- a/drivers/parisc/led.c +++ b/drivers/parisc/led.c @@ -60,8 +60,8 @@ static int led_type __read_mostly = -1; static unsigned char lastleds; /* LED state from most recent update */ static unsigned int led_heartbeat __read_mostly = 1; -static unsigned int led_diskio __read_mostly = 1; -static unsigned int led_lanrxtx __read_mostly = 1; +static unsigned int led_diskio __read_mostly; +static unsigned int led_lanrxtx __read_mostly; static char lcd_text[32] __read_mostly; static char lcd_text_default[32] __read_mostly; static int lcd_no_led_support __read_mostly = 0; /* KittyHawk doesn't support LED on its LCD */ diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index 5b78f3b1b918a7f5600c4222b89288481ed985c2..420cd0a578d079371227a1d2f0d13ad89b39ceeb 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -368,6 +368,36 @@ int pci_pasid_features(struct pci_dev *pdev) } EXPORT_SYMBOL_GPL(pci_pasid_features); +/** + * pci_prg_resp_pasid_required - Return PRG Response PASID Required bit + * status. + * @pdev: PCI device structure + * + * Returns 1 if PASID is required in PRG Response Message, 0 otherwise. + * + * Even though the PRG response PASID status is read from PRI Status + * Register, since this API will mainly be used by PASID users, this + * function is defined within #ifdef CONFIG_PCI_PASID instead of + * CONFIG_PCI_PRI. + */ +int pci_prg_resp_pasid_required(struct pci_dev *pdev) +{ + u16 status; + int pos; + + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); + if (!pos) + return 0; + + pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); + + if (status & PCI_PRI_STATUS_PASID) + return 1; + + return 0; +} +EXPORT_SYMBOL_GPL(pci_prg_resp_pasid_required); + #define PASID_NUMBER_SHIFT 8 #define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT) /** diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 765357b87ff695624e9feff0c4b47953fcf0ecb9..5fa7c0f09fa526362e50351b6f91bce1e7aade46 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -376,7 +376,7 @@ static const struct dw_pcie_ops dw_pcie_ops = { .link_up = ks_dw_pcie_link_up, }; -static int __exit ks_pcie_remove(struct platform_device *pdev) +static int ks_pcie_remove(struct platform_device *pdev) { struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); @@ -385,7 +385,7 @@ static int __exit ks_pcie_remove(struct platform_device *pdev) return 0; } -static int __init ks_pcie_probe(struct platform_device *pdev) +static int ks_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct dw_pcie *pci; @@ -452,9 +452,9 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return ret; } -static struct platform_driver ks_pcie_driver __refdata = { +static struct platform_driver ks_pcie_driver = { .probe = ks_pcie_probe, - .remove = __exit_p(ks_pcie_remove), + .remove = ks_pcie_remove, .driver = { .name = "keystone-pcie", .of_match_table = of_match_ptr(ks_pcie_of_match), diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller/pci-hyperv.c index 63c79e140f1a8b286946cacb9d790e9a2f1f0d1d..f5f201bfc814d7b9e53f660b231897b6f36ba686 100644 --- a/drivers/pci/controller/pci-hyperv.c +++ b/drivers/pci/controller/pci-hyperv.c @@ -2445,6 +2445,24 @@ static int hv_pci_query_relations(struct hv_device *hdev) if (!ret) ret = wait_for_response(hdev, &comp); + /* + * In the case of fast device addition/removal, it's possible that + * vmbus_sendpacket() or wait_for_response() returns -ENODEV but we + * already got a PCI_BUS_RELATIONS* message from the host and the + * channel callback already scheduled a work to hbus->wq, which can be + * running pci_devices_present_work() -> survey_child_resources() -> + * complete(&hbus->survey_event), even after hv_pci_query_relations() + * exits and the stack variable 'comp' is no longer valid; as a result, + * a hang or a page fault may happen when the complete() calls + * raw_spin_lock_irqsave(). Flush hbus->wq before we exit from + * hv_pci_query_relations() to avoid the issues. Note: if 'ret' is + * -ENODEV, there can't be any more work item scheduled to hbus->wq + * after the flush_workqueue(): see vmbus_onoffer_rescind() -> + * vmbus_reset_channel_cb(), vmbus_rescind_cleanup() -> + * channel->rescind = true. + */ + flush_workqueue(hbus->wq); + return ret; } diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index 06dd2ab73b6eeafd455e04286f7c210a4d7291d0..4d3a589af1296b37d6e283b0008fdbac1313f0e6 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -124,6 +124,7 @@ static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, struct pci_epf_header *hdr) { + u32 reg; struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; @@ -136,8 +137,9 @@ static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, PCIE_CORE_CONFIG_VENDOR); } - rockchip_pcie_write(rockchip, hdr->deviceid << 16, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID); + reg = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID); + reg = (reg & 0xFFFF) | (hdr->deviceid << 16); + rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID); rockchip_pcie_write(rockchip, hdr->revid | @@ -311,15 +313,15 @@ static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, { struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; - u16 flags; + u32 flags; flags = rockchip_pcie_read(rockchip, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK; flags |= - ((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | - PCI_MSI_FLAGS_64BIT; + (multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | + (PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET); flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP; rockchip_pcie_write(rockchip, flags, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + @@ -331,7 +333,7 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) { struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; - u16 flags; + u32 flags; flags = rockchip_pcie_read(rockchip, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + @@ -344,48 +346,25 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) } static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn, - u8 intx, bool is_asserted) + u8 intx, bool do_assert) { struct rockchip_pcie *rockchip = &ep->rockchip; - u32 r = ep->max_regions - 1; - u32 offset; - u32 status; - u8 msg_code; - - if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR || - ep->irq_pci_fn != fn)) { - rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r, - AXI_WRAPPER_NOR_MSG, - ep->irq_phys_addr, 0, 0); - ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR; - ep->irq_pci_fn = fn; - } intx &= 3; - if (is_asserted) { + + if (do_assert) { ep->irq_pending |= BIT(intx); - msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx; + rockchip_pcie_write(rockchip, + PCIE_CLIENT_INT_IN_ASSERT | + PCIE_CLIENT_INT_PEND_ST_PEND, + PCIE_CLIENT_LEGACY_INT_CTRL); } else { ep->irq_pending &= ~BIT(intx); - msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx; + rockchip_pcie_write(rockchip, + PCIE_CLIENT_INT_IN_DEASSERT | + PCIE_CLIENT_INT_PEND_ST_NORMAL, + PCIE_CLIENT_LEGACY_INT_CTRL); } - - status = rockchip_pcie_read(rockchip, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + - ROCKCHIP_PCIE_EP_CMD_STATUS); - status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; - - if ((status != 0) ^ (ep->irq_pending != 0)) { - status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; - rockchip_pcie_write(rockchip, status, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + - ROCKCHIP_PCIE_EP_CMD_STATUS); - } - - offset = - ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) | - ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA; - writel(0, ep->irq_cpu_addr + offset); } static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn, @@ -415,7 +394,7 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, u8 interrupt_num) { struct rockchip_pcie *rockchip = &ep->rockchip; - u16 flags, mme, data, data_mask; + u32 flags, mme, data, data_mask; u8 msi_count; u64 pci_addr, pci_addr_mask = 0xff; @@ -620,6 +599,9 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; + rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE, + PCIE_CLIENT_CONFIG); + return 0; err_epc_mem_exit: pci_epc_mem_exit(epc); diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index c53d1322a3d6cf873eafc4ba4a5c9d93c56c662c..b047437605cb20123cdde458c9e0df4adf1e8c09 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -154,6 +155,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) } EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt); +#define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr) +/* 100 ms max wait time for PHY PLLs to lock */ +#define RK_PHY_PLL_LOCK_TIMEOUT_US 100000 +/* Sleep should be less than 20ms */ +#define RK_PHY_PLL_LOCK_SLEEP_US 1000 + int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) { struct device *dev = rockchip->dev; @@ -255,6 +262,16 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) } } + err = readx_poll_timeout(rockchip_pcie_read_addr, + PCIE_CLIENT_SIDE_BAND_STATUS, + regs, !(regs & PCIE_CLIENT_PHY_ST), + RK_PHY_PLL_LOCK_SLEEP_US, + RK_PHY_PLL_LOCK_TIMEOUT_US); + if (err) { + dev_err(dev, "PHY PLLs could not lock, %d\n", err); + goto err_power_off_phy; + } + /* * Please don't reorder the deassert sequence of the following * four reset pins. diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 8e87a059ce73d3921350f100315afbec0dda1f1d..1c45b3c32151c68110fa4e2dbbe7f4ccbcaa55aa 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -37,6 +37,13 @@ #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) +#define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c) +#define PCIE_CLIENT_INT_IN_ASSERT HIWORD_UPDATE_BIT(0x0002) +#define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0) +#define PCIE_CLIENT_INT_PEND_ST_PEND HIWORD_UPDATE_BIT(0x0001) +#define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0) +#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20) +#define PCIE_CLIENT_PHY_ST BIT(12) #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) #define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0) #define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18 @@ -132,6 +139,8 @@ #define PCIE_RC_RP_ATS_BASE 0x400000 #define PCIE_RC_CONFIG_NORMAL_BASE 0x800000 #define PCIE_RC_CONFIG_BASE 0xa00000 +#define PCIE_EP_CONFIG_BASE 0xa00000 +#define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00) #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) #define PCIE_RC_CONFIG_SCC_SHIFT 16 #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) @@ -223,6 +232,7 @@ #define ROCKCHIP_PCIE_EP_CMD_STATUS 0x4 #define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19) #define ROCKCHIP_PCIE_EP_MSI_CTRL_REG 0x90 +#define ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET 16 #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET 17 #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17) #define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET 20 @@ -230,7 +240,6 @@ #define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(16) #define ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP BIT(24) #define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1 -#define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3 #define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) #define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ (PCIE_RC_RP_ATS_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c index 3d8844e7090a880c24578c04599888586f4acd9d..72a289d73dfc88062442d08bcbbc0b6a7a26ccb5 100644 --- a/drivers/pci/hotplug/acpiphp_glue.c +++ b/drivers/pci/hotplug/acpiphp_glue.c @@ -510,12 +510,15 @@ static void enable_slot(struct acpiphp_slot *slot, bool bridge) if (pass && dev->subordinate) { check_hotplug_bridge(slot, dev); pcibios_resource_survey_bus(dev->subordinate); - __pci_bus_size_bridges(dev->subordinate, - &add_list); + if (pci_is_root_bus(bus)) + __pci_bus_size_bridges(dev->subordinate, &add_list); } } } - __pci_bus_assign_resources(bus, &add_list, NULL); + if (pci_is_root_bus(bus)) + __pci_bus_assign_resources(bus, &add_list, NULL); + else + pci_assign_unassigned_bridge_resources(bus->self); } acpiphp_sanitize_bus(bus); diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h index ef60718070728c227ffd954f2d3777292e5ffd53..522719ca1c2b07058d3c2fc92325170c864bee6b 100644 --- a/drivers/pci/hotplug/pciehp.h +++ b/drivers/pci/hotplug/pciehp.h @@ -84,6 +84,8 @@ struct slot { * @reset_lock: prevents access to the Data Link Layer Link Active bit in the * Link Status register and to the Presence Detect State bit in the Slot * Status register during a slot reset which may cause them to flap + * @depth: Number of additional hotplug ports in the path to the root bus, + * used as lock subclass for @reset_lock * @slot: pointer to the controller's slot structure * @queue: wait queue to wake up on reception of a Command Completed event, * used for synchronous writes to the Slot Control register @@ -115,6 +117,7 @@ struct controller { struct mutex ctrl_lock; struct pcie_device *pcie; struct rw_semaphore reset_lock; + unsigned int depth; struct slot *slot; wait_queue_head_t queue; u32 slot_cap; diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c index 518c46f8e63b7348a81eae21b8c1a8fb0b08adaf..5ebfff9356c7f8473f5c2beac1114f5325d8b208 100644 --- a/drivers/pci/hotplug/pciehp_core.c +++ b/drivers/pci/hotplug/pciehp_core.c @@ -215,7 +215,7 @@ static void pciehp_check_presence(struct controller *ctrl) struct slot *slot = ctrl->slot; u8 occupied; - down_read(&ctrl->reset_lock); + down_read_nested(&ctrl->reset_lock, ctrl->depth); mutex_lock(&slot->lock); pciehp_get_adapter_status(slot, &occupied); diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 2795445233b3b9117d44f35a12cea41628f3fc64..04630106269af13cd0590f0770e033e0387ee4ad 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -298,17 +298,11 @@ int pciehp_check_link_status(struct controller *ctrl) static int __pciehp_link_set(struct controller *ctrl, bool enable) { struct pci_dev *pdev = ctrl_dev(ctrl); - u16 lnk_ctrl; - pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); + pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_LD, + enable ? 0 : PCI_EXP_LNKCTL_LD); - if (enable) - lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; - else - lnk_ctrl |= PCI_EXP_LNKCTL_LD; - - pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); - ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); return 0; } @@ -674,7 +668,7 @@ static irqreturn_t pciehp_ist(int irq, void *dev_id) * Disable requests have higher priority than Presence Detect Changed * or Data Link Layer State Changed events. */ - down_read(&ctrl->reset_lock); + down_read_nested(&ctrl->reset_lock, ctrl->depth); if (events & DISABLE_SLOT) pciehp_handle_disable_request(slot); else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC)) @@ -785,7 +779,7 @@ int pciehp_reset_slot(struct slot *slot, int probe) if (probe) return 0; - down_write(&ctrl->reset_lock); + down_write_nested(&ctrl->reset_lock, ctrl->depth); if (!ATTN_BUTTN(ctrl)) { ctrl_mask |= PCI_EXP_SLTCTL_PDCE; @@ -872,6 +866,20 @@ static inline void dbg_ctrl(struct controller *ctrl) #define FLAG(x, y) (((x) & (y)) ? '+' : '-') +static inline int pcie_hotplug_depth(struct pci_dev *dev) +{ + struct pci_bus *bus = dev->bus; + int depth = 0; + + while (bus->parent) { + bus = bus->parent; + if (bus->self && bus->self->is_hotplug_bridge) + depth++; + } + + return depth; +} + struct controller *pcie_init(struct pcie_device *dev) { struct controller *ctrl; @@ -884,6 +892,7 @@ struct controller *pcie_init(struct pcie_device *dev) goto abort; ctrl->pcie = dev; + ctrl->depth = pcie_hotplug_depth(dev->port); pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); if (pdev->hotplug_user_indicators) diff --git a/drivers/pci/hotplug/pciehp_pci.c b/drivers/pci/hotplug/pciehp_pci.c index 5c58c22e0c084145115662855c6efadc0dea6268..a32023afa25bcc4a2e8cbdb70f299cd5d2cb499c 100644 --- a/drivers/pci/hotplug/pciehp_pci.c +++ b/drivers/pci/hotplug/pciehp_pci.c @@ -55,7 +55,14 @@ int pciehp_configure_device(struct slot *p_slot) pci_assign_unassigned_bridge_resources(bridge); pcie_bus_configure_settings(parent); + + /* + * Release reset_lock during driver binding + * to avoid AB-BA deadlock with device_lock. + */ + up_read(&ctrl->reset_lock); pci_bus_add_devices(parent); + down_read_nested(&ctrl->reset_lock, ctrl->depth); out: pci_unlock_rescan_remove(); @@ -91,7 +98,15 @@ void pciehp_unconfigure_device(struct slot *p_slot) pci_walk_bus(dev->subordinate, pci_dev_set_disconnected, NULL); } + + /* + * Release reset_lock during driver unbinding + * to avoid AB-BA deadlock with device_lock. + */ + up_read(&ctrl->reset_lock); pci_stop_and_remove_bus_device(dev); + down_read_nested(&ctrl->reset_lock, ctrl->depth); + /* * Ensure that no new Requests will be generated from * the device. diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 2c46f7dcd2f5dad5cb129a3ec17104e26bee10e8..2777c459706a9debeeab940e0f71ccb3c6a4da7d 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -496,7 +496,7 @@ static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) { int acpi_state, d_max; - if (pdev->no_d3cold) + if (pdev->no_d3cold || !pdev->d3cold_allowed) d_max = ACPI_STATE_D3_HOT; else d_max = ACPI_STATE_D3_COLD; diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 34a7b3c137bb03a870d10479aee03e1389953410..f68798763af8dcaaa494747e1f77ea781f24f62a 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -182,6 +182,9 @@ static ssize_t current_link_speed_show(struct device *dev, return -EINVAL; switch (linkstat & PCI_EXP_LNKSTA_CLS) { + case PCI_EXP_LNKSTA_CLS_32_0GB: + speed = "32 GT/s"; + break; case PCI_EXP_LNKSTA_CLS_16_0GB: speed = "16 GT/s"; break; @@ -516,10 +519,7 @@ static ssize_t d3cold_allowed_store(struct device *dev, return -EINVAL; pdev->d3cold_allowed = !!val; - if (pdev->d3cold_allowed) - pci_d3cold_enable(pdev); - else - pci_d3cold_disable(pdev); + pci_bridge_d3_update(pdev); pm_runtime_resume(dev); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 8c0c5e84b708ffbda27f76385371b2a489af39f7..df2aefc583f0c83f3ea95ff9a47b9040d75d0706 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2521,13 +2521,13 @@ static const struct dmi_system_id bridge_d3_blacklist[] = { { /* * Downstream device is not accessible after putting a root port - * into D3cold and back into D0 on Elo i2. + * into D3cold and back into D0 on Elo Continental Z2 board */ - .ident = "Elo i2", + .ident = "Elo Continental Z2", .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Elo Touch Solutions"), - DMI_MATCH(DMI_PRODUCT_NAME, "Elo i2"), - DMI_MATCH(DMI_PRODUCT_VERSION, "RevB"), + DMI_MATCH(DMI_BOARD_VENDOR, "Elo Touch Solutions"), + DMI_MATCH(DMI_BOARD_NAME, "Geminilake"), + DMI_MATCH(DMI_BOARD_VERSION, "Continental Z2"), }, }, #endif @@ -5576,7 +5576,9 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) */ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); if (lnkcap2) { /* PCIe r3.0-compliant */ - if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) + if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) + return PCIE_SPEED_32_0GT; + else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) return PCIE_SPEED_16_0GT; else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) return PCIE_SPEED_8_0GT; diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 279f9f0197b0191f450a125ce3c7de72d4dd1a17..118c91586798d56b35e1b71f0201597a2ca7c97e 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -203,12 +203,39 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) link->clkpm_disable = blacklist ? 1 : 0; } -static bool pcie_retrain_link(struct pcie_link_state *link) +static int pcie_wait_for_retrain(struct pci_dev *pdev) +{ + unsigned long end_jiffies; + u16 reg16; + + /* Wait for Link Training to be cleared by hardware */ + end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; + do { + pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, ®16); + if (!(reg16 & PCI_EXP_LNKSTA_LT)) + return 0; + msleep(1); + } while (time_before(jiffies, end_jiffies)); + + return -ETIMEDOUT; +} + +static int pcie_retrain_link(struct pcie_link_state *link) { struct pci_dev *parent = link->pdev; - unsigned long start_jiffies; + int rc; u16 reg16; + /* + * Ensure the updated LNKCTL parameters are used during link + * training by checking that there is no ongoing link training to + * avoid LTSSM race as recommended in Implementation Note at the + * end of PCIe r6.0.1 sec 7.5.3.7. + */ + rc = pcie_wait_for_retrain(parent); + if (rc) + return rc; + pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); reg16 |= PCI_EXP_LNKCTL_RL; pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); @@ -222,17 +249,7 @@ static bool pcie_retrain_link(struct pcie_link_state *link) pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); } - /* Wait for link training end. Break out after waiting for timeout */ - start_jiffies = jiffies; - for (;;) { - pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_LT)) - break; - if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) - break; - msleep(1); - } - return !(reg16 & PCI_EXP_LNKSTA_LT); + return pcie_wait_for_retrain(parent); } /* @@ -243,7 +260,7 @@ static bool pcie_retrain_link(struct pcie_link_state *link) static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) { int same_clock = 1; - u16 reg16, parent_reg, child_reg[8]; + u16 reg16, ccc, parent_old_ccc, child_old_ccc[8]; struct pci_dev *child, *parent = link->pdev; struct pci_bus *linkbus = parent->subordinate; /* @@ -265,6 +282,7 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) /* Port might be already in common clock mode */ pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); + parent_old_ccc = reg16 & PCI_EXP_LNKCTL_CCC; if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) { bool consistent = true; @@ -281,35 +299,30 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) pci_warn(parent, "ASPM: current common clock configuration is broken, reconfiguring\n"); } + ccc = same_clock ? PCI_EXP_LNKCTL_CCC : 0; /* Configure downstream component, all functions */ list_for_each_entry(child, &linkbus->devices, bus_list) { pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); - child_reg[PCI_FUNC(child->devfn)] = reg16; - if (same_clock) - reg16 |= PCI_EXP_LNKCTL_CCC; - else - reg16 &= ~PCI_EXP_LNKCTL_CCC; - pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16); + child_old_ccc[PCI_FUNC(child->devfn)] = reg16 & PCI_EXP_LNKCTL_CCC; + pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_CCC, ccc); } /* Configure upstream component */ - pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); - parent_reg = reg16; - if (same_clock) - reg16 |= PCI_EXP_LNKCTL_CCC; - else - reg16 &= ~PCI_EXP_LNKCTL_CCC; - pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); + pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_CCC, ccc); - if (pcie_retrain_link(link)) - return; + if (pcie_retrain_link(link)) { - /* Training failed. Restore common clock configurations */ - pci_err(parent, "ASPM: Could not configure common clock\n"); - list_for_each_entry(child, &linkbus->devices, bus_list) - pcie_capability_write_word(child, PCI_EXP_LNKCTL, - child_reg[PCI_FUNC(child->devfn)]); - pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg); + /* Training failed. Restore common clock configurations */ + pci_err(parent, "ASPM: Could not configure common clock\n"); + list_for_each_entry(child, &linkbus->devices, bus_list) + pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_CCC, + child_old_ccc[PCI_FUNC(child->devfn)]); + pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_CCC, parent_old_ccc); + } } /* Convert L0s latency encoding to ns */ diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 4853bdbaa90260fe45ff669040fb76e98c1e95b5..f9134118ae63edaec5c186c446c8515fa9648388 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -616,7 +616,7 @@ const unsigned char pcie_link_speed[] = { PCIE_SPEED_5_0GT, /* 2 */ PCIE_SPEED_8_0GT, /* 3 */ PCIE_SPEED_16_0GT, /* 4 */ - PCI_SPEED_UNKNOWN, /* 5 */ + PCIE_SPEED_32_0GT, /* 5 */ PCI_SPEED_UNKNOWN, /* 6 */ PCI_SPEED_UNKNOWN, /* 7 */ PCI_SPEED_UNKNOWN, /* 8 */ diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index f494e76faaa0127c332bae4c6527cd80659d2e90..3a165710fbb8696eab88229eb74ba5d2b4ff144f 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -599,7 +599,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_ /* * In the AMD NL platform, this device ([1022:7912]) has a class code of * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will - * claim it. + * claim it. The same applies on the VanGogh platform device ([1022:163a]). * * But the dwc3 driver is a more specific driver for this device, and we'd * prefer to use it instead of xhci. To prevent xhci from claiming the @@ -607,7 +607,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_ * defines as "USB device (not host controller)". The dwc3 driver can then * claim it based on its Vendor and Device ID. */ -static void quirk_amd_nl_class(struct pci_dev *pdev) +static void quirk_amd_dwc_class(struct pci_dev *pdev) { u32 class = pdev->class; @@ -617,7 +617,9 @@ static void quirk_amd_nl_class(struct pci_dev *pdev) class, pdev->class); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, - quirk_amd_nl_class); + quirk_amd_dwc_class); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, + quirk_amd_dwc_class); /* * Let's make the southbridge information explicit instead of having to @@ -4074,6 +4076,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, quirk_dma_func1_alias); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, + quirk_dma_func1_alias); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, quirk_dma_func1_alias); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, @@ -5153,6 +5157,7 @@ static void quirk_no_flr(struct pci_dev *dev) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c index dfbe9cbf292c09350f4e02520e53142c0bf53936..d575583e49c2cb790f51773f24d7ee708c7182f6 100644 --- a/drivers/pci/slot.c +++ b/drivers/pci/slot.c @@ -75,6 +75,7 @@ static const char *pci_bus_speed_strings[] = { "5.0 GT/s PCIe", /* 0x15 */ "8.0 GT/s PCIe", /* 0x16 */ "16.0 GT/s PCIe", /* 0x17 */ + "32.0 GT/s PCIe", /* 0x18 */ }; static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf) diff --git a/drivers/pcmcia/cs.c b/drivers/pcmcia/cs.c index 182e5ef4ab83db481965d3efb54ce01f0db4334b..e99ef7b745aeb4327c7721aad793f7740df227b3 100644 --- a/drivers/pcmcia/cs.c +++ b/drivers/pcmcia/cs.c @@ -608,6 +608,7 @@ static int pccardd(void *__skt) dev_warn(&skt->dev, "PCMCIA: unable to register socket\n"); skt->thread = NULL; complete(&skt->thread_done); + put_device(&skt->dev); return 0; } ret = pccard_sysfs_add_socket(&skt->dev); diff --git a/drivers/pcmcia/ds.c b/drivers/pcmcia/ds.c index a9258f641ceed7a077aa08af4219bc2e1a25e6f9..3701887be32e88a2e2c3e9a3e8c231f8f23d5315 100644 --- a/drivers/pcmcia/ds.c +++ b/drivers/pcmcia/ds.c @@ -521,9 +521,6 @@ static struct pcmcia_device *pcmcia_device_add(struct pcmcia_socket *s, /* by default don't allow DMA */ p_dev->dma_mask = DMA_MASK_NONE; p_dev->dev.dma_mask = &p_dev->dma_mask; - dev_set_name(&p_dev->dev, "%d.%d", p_dev->socket->sock, p_dev->device_no); - if (!dev_name(&p_dev->dev)) - goto err_free; p_dev->devname = kasprintf(GFP_KERNEL, "pcmcia%s", dev_name(&p_dev->dev)); if (!p_dev->devname) goto err_free; @@ -581,8 +578,15 @@ static struct pcmcia_device *pcmcia_device_add(struct pcmcia_socket *s, pcmcia_device_query(p_dev); - if (device_register(&p_dev->dev)) - goto err_unreg; + dev_set_name(&p_dev->dev, "%d.%d", p_dev->socket->sock, p_dev->device_no); + if (device_register(&p_dev->dev)) { + mutex_lock(&s->ops_mutex); + list_del(&p_dev->socket_device_list); + s->device_count--; + mutex_unlock(&s->ops_mutex); + put_device(&p_dev->dev); + return NULL; + } return p_dev; diff --git a/drivers/pcmcia/rsrc_nonstatic.c b/drivers/pcmcia/rsrc_nonstatic.c index 123420cac6b5444b9f91b8f9ddc49c0aafefb48a..b75b12c2c702d21404548e2b5d030577c57d661f 100644 --- a/drivers/pcmcia/rsrc_nonstatic.c +++ b/drivers/pcmcia/rsrc_nonstatic.c @@ -1056,6 +1056,8 @@ static void nonstatic_release_resource_db(struct pcmcia_socket *s) q = p->next; kfree(p); } + + kfree(data); } diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c index 524381249a2b80ad857369b691a29195232a29f0..b51e19402ab0c3d7403acae0a4b99c18068d0864 100644 --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c @@ -167,7 +167,7 @@ static int hisi_inno_phy_probe(struct platform_device *pdev) phy_set_drvdata(phy, &priv->ports[i]); i++; - if (i > INNO_PHY_PORT_NUM) { + if (i >= INNO_PHY_PORT_NUM) { dev_warn(dev, "Support %d ports in maximum\n", i); break; } diff --git a/drivers/phy/motorola/phy-mapphone-mdm6600.c b/drivers/phy/motorola/phy-mapphone-mdm6600.c index 77518010adc88353002561543c3ebf3b66de3ceb..44ad15ca881ee248fd546c1c02d127c8c8ccc20f 100644 --- a/drivers/phy/motorola/phy-mapphone-mdm6600.c +++ b/drivers/phy/motorola/phy-mapphone-mdm6600.c @@ -612,6 +612,7 @@ static int phy_mdm6600_remove(struct platform_device *pdev) struct phy_mdm6600 *ddata = platform_get_drvdata(pdev); struct gpio_desc *reset_gpio = ddata->ctrl_gpios[PHY_MDM6600_RESET]; + pm_runtime_get_noresume(ddata->dev); pm_runtime_dont_use_autosuspend(ddata->dev); pm_runtime_put_sync(ddata->dev); pm_runtime_disable(ddata->dev); diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 76a4b58ec77172873e53e50abc3a6a02efeb1a9c..ca4b80d0d8b783ecd080884f0ec88d442c826299 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -817,9 +817,8 @@ static int tcphy_get_mode(struct rockchip_typec_phy *tcphy) struct extcon_dev *edev = tcphy->extcon; union extcon_property_value property; unsigned int id; - bool ufp, dp; u8 mode; - int ret; + int ret, ufp, dp; if (!edev) return MODE_DFP_USB; diff --git a/drivers/phy/st/phy-miphy28lp.c b/drivers/phy/st/phy-miphy28lp.c index 213e2e15339c44dff742b2394455d7138e0d524e..fe23432e5b1a60657f74e304f841ac56e52c6a4b 100644 --- a/drivers/phy/st/phy-miphy28lp.c +++ b/drivers/phy/st/phy-miphy28lp.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -488,19 +489,11 @@ static inline void miphy28lp_pcie_config_gen(struct miphy28lp_phy *miphy_phy) static inline int miphy28lp_wait_compensation(struct miphy28lp_phy *miphy_phy) { - unsigned long finish = jiffies + 5 * HZ; u8 val; /* Waiting for Compensation to complete */ - do { - val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6); - - if (time_after_eq(jiffies, finish)) - return -EBUSY; - cpu_relax(); - } while (!(val & COMP_DONE)); - - return 0; + return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_COMP_FSM_6, + val, val & COMP_DONE, 1, 5 * USEC_PER_SEC); } @@ -809,7 +802,6 @@ static inline void miphy28lp_configure_usb3(struct miphy28lp_phy *miphy_phy) static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy) { - unsigned long finish = jiffies + 5 * HZ; u8 mask = HFC_PLL | HFC_RDY; u8 val; @@ -820,21 +812,14 @@ static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy) if (miphy_phy->type == PHY_TYPE_SATA) mask |= PHY_RDY; - do { - val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1); - if ((val & mask) != mask) - cpu_relax(); - else - return 0; - } while (!time_after_eq(jiffies, finish)); - - return -EBUSY; + return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_STATUS_1, + val, (val & mask) == mask, 1, + 5 * USEC_PER_SEC); } static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy) { struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; - unsigned long finish = jiffies + 5 * HZ; u32 val; if (!miphy_phy->osc_rdy) @@ -843,17 +828,10 @@ static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy) if (!miphy_phy->syscfg_reg[SYSCFG_STATUS]) return -EINVAL; - do { - regmap_read(miphy_dev->regmap, - miphy_phy->syscfg_reg[SYSCFG_STATUS], &val); - - if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY) - cpu_relax(); - else - return 0; - } while (!time_after_eq(jiffies, finish)); - - return -EBUSY; + return regmap_read_poll_timeout(miphy_dev->regmap, + miphy_phy->syscfg_reg[SYSCFG_STATUS], + val, val & MIPHY_OSC_RDY, 1, + 5 * USEC_PER_SEC); } static int miphy28lp_get_resource_byname(struct device_node *child, diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index 39c01ef57d83cf9c88b23ee0b9bdd955f1e3c9b8..17211b31e1ed44b05923271163e4e281ef9b8b8d 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -583,6 +583,7 @@ static int tegra_xusb_add_usb2_port(struct tegra_xusb_padctl *padctl, usb2->base.lane = usb2->base.ops->map(&usb2->base); if (IS_ERR(usb2->base.lane)) { err = PTR_ERR(usb2->base.lane); + tegra_xusb_port_unregister(&usb2->base); goto out; } @@ -635,6 +636,7 @@ static int tegra_xusb_add_ulpi_port(struct tegra_xusb_padctl *padctl, ulpi->base.lane = ulpi->base.ops->map(&ulpi->base); if (IS_ERR(ulpi->base.lane)) { err = PTR_ERR(ulpi->base.lane); + tegra_xusb_port_unregister(&ulpi->base); goto out; } diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 25932d2a71547dbcb2b170ecc885e5c6876b988d..ef8eb42e4d38323c4f5e0e89053fd67e08e39f8b 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1032,11 +1032,6 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, break; - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - if (!(ctrl1 & CHV_PADCTRL1_ODEN)) - return -EINVAL; - break; - case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { u32 cfg; @@ -1046,6 +1041,16 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, return -EINVAL; break; + + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (ctrl1 & CHV_PADCTRL1_ODEN) + return -EINVAL; + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!(ctrl1 & CHV_PADCTRL1_ODEN)) + return -EINVAL; + break; } default: diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c index ad502eda4afa46ec2b31a62f6204335c64424b7e..89ce65e5309f221c269814821e46179da1b54ff4 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c @@ -400,6 +400,7 @@ static struct meson_pmx_group meson_axg_periphs_groups[] = { GPIO_GROUP(GPIOA_15), GPIO_GROUP(GPIOA_16), GPIO_GROUP(GPIOA_17), + GPIO_GROUP(GPIOA_18), GPIO_GROUP(GPIOA_19), GPIO_GROUP(GPIOA_20), diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 66b9c5826ec0316c53497d97ad284a10b1881ca1..ee25edecc2e1d141848ade68fb714ffc18e97736 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -127,6 +127,14 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, struct amd_gpio *gpio_dev = gpiochip_get_data(gc); raw_spin_lock_irqsave(&gpio_dev->lock, flags); + + /* Use special handling for Pin0 debounce */ + if (offset == 0) { + pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); + if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) + debounce = 0; + } + pin_reg = readl(gpio_dev->base + offset * 4); if (debounce) { @@ -182,18 +190,6 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, return ret; } -static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, - unsigned long config) -{ - u32 debounce; - - if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) - return -ENOTSUPP; - - debounce = pinconf_to_config_argument(config); - return amd_gpio_set_debounce(gc, offset, debounce); -} - #ifdef CONFIG_DEBUG_FS static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) { @@ -216,6 +212,7 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) char *output_value; char *output_enable; + seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG)); for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { seq_printf(s, "GPIO bank%d\t", bank); @@ -666,7 +663,7 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev, break; default: - dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", + dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; } @@ -677,7 +674,7 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev, } static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *configs, unsigned num_configs) + unsigned long *configs, unsigned int num_configs) { int i; u32 arg; @@ -719,7 +716,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, break; default: - dev_err(&gpio_dev->pdev->dev, + dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", param); ret = -ENOTSUPP; } @@ -767,6 +764,20 @@ static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, return 0; } +static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin, + unsigned long config) +{ + struct amd_gpio *gpio_dev = gpiochip_get_data(gc); + + if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) { + u32 debounce = pinconf_to_config_argument(config); + + return amd_gpio_set_debounce(gc, pin, debounce); + } + + return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1); +} + static const struct pinconf_ops amd_pinconf_ops = { .pin_config_get = amd_pinconf_get, .pin_config_set = amd_pinconf_set, @@ -774,6 +785,34 @@ static const struct pinconf_ops amd_pinconf_ops = { .pin_config_group_set = amd_pinconf_group_set, }; +static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) +{ + struct pinctrl_desc *desc = gpio_dev->pctrl->desc; + unsigned long flags; + u32 pin_reg, mask; + int i; + + mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | + BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | + BIT(WAKE_CNTRL_OFF_S4); + + for (i = 0; i < desc->npins; i++) { + int pin = desc->pins[i].number; + const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); + + if (!pd) + continue; + + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + + pin_reg = readl(gpio_dev->base + pin * 4); + pin_reg &= ~mask; + writel(pin_reg, gpio_dev->base + pin * 4); + + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); + } +} + #ifdef CONFIG_PM_SLEEP static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) { @@ -858,6 +897,7 @@ static int amd_gpio_probe(struct platform_device *pdev) int irq_base; struct resource *res; struct amd_gpio *gpio_dev; + struct gpio_irq_chip *girq; gpio_dev = devm_kzalloc(&pdev->dev, sizeof(struct amd_gpio), GFP_KERNEL); @@ -921,6 +961,18 @@ static int amd_gpio_probe(struct platform_device *pdev) return PTR_ERR(gpio_dev->pctrl); } + /* Disable and mask interrupts */ + amd_gpio_irq_init(gpio_dev); + + girq = &gpio_dev->gc.irq; + girq->chip = &amd_gpio_irqchip; + /* This will let us handle the parent IRQ in the driver */ + girq->parent_handler = NULL; + girq->num_parents = 0; + girq->parents = NULL; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); if (ret) return ret; @@ -932,19 +984,8 @@ static int amd_gpio_probe(struct platform_device *pdev) goto out2; } - ret = gpiochip_irqchip_add(&gpio_dev->gc, - &amd_gpio_irqchip, - 0, - handle_simple_irq, - IRQ_TYPE_NONE); - if (ret) { - dev_err(&pdev->dev, "could not add irqchip\n"); - ret = -ENODEV; - goto out2; - } - - ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0, - KBUILD_MODNAME, gpio_dev); + ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, + IRQF_SHARED, KBUILD_MODNAME, gpio_dev); if (ret) goto out2; diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index 91da7527f0020328b628e1ecb5992f28ab212879..0f7c02bc9044a1d179ccd3dd39b6512b89a3d9ea 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -21,6 +21,7 @@ #define AMD_GPIO_PINS_BANK3 32 #define WAKE_INT_MASTER_REG 0xfc +#define INTERNAL_GPIO0_DEBOUNCE (1 << 15) #define EOI_MASK (1 << 29) #define WAKE_INT_STATUS_REG0 0x2f8 diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 9e2f3738bf3ecdec3314be32863b4fcc89b46739..cbbda24bf6a80b232e98b7ab4c26e7d5712dacc6 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -1022,8 +1022,10 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) pin_desc[i].number = i; /* Pin naming convention: P(bank_name)(bank_pin_number). */ - pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d", - bank + 'A', line); + pin_desc[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "P%c%d", + bank + 'A', line); + if (!pin_desc[i].name) + return -ENOMEM; group->name = group_names[i] = pin_desc[i].name; group->pin = pin_desc[i].number; @@ -1080,7 +1082,6 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) dev_err(dev, "can't add the irq domain\n"); return -ENODEV; } - atmel_pioctrl->irq_domain->name = "atmel gpio"; for (i = 0; i < atmel_pioctrl->npins; i++) { int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i); diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index fad0e132ead84b187e8d9294f98d29b0068f577d..ad01cc57982328c442f121c3ebee3a0f24797dff 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1782,7 +1782,7 @@ static int at91_gpio_probe(struct platform_device *pdev) } for (i = 0; i < chip->ngpio; i++) - names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); + names[i] = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); chip->names = (const char *const *)names; diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index dc405d7aa1b78f1150a58591ec69baaf9cb64c54..fb7f2282635e80586b6db043900fda4c7a0c4803 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -70,7 +70,7 @@ enum rockchip_pinctrl_type { RK3399, }; -/** +/* * Encode variants of iomux registers into a type variable */ #define IOMUX_GPIO_ONLY BIT(0) @@ -80,6 +80,7 @@ enum rockchip_pinctrl_type { #define IOMUX_WIDTH_3BIT BIT(4) /** + * struct rockchip_iomux * @type: iomux variant using IOMUX_* constants * @offset: if initialized to -1 it will be autocalculated, by specifying * an initial offset value the relevant source offset can be reset @@ -90,7 +91,7 @@ struct rockchip_iomux { int offset; }; -/** +/* * enum type index corresponding to rockchip_perpin_drv_list arrays index. */ enum rockchip_pin_drv_type { @@ -102,7 +103,7 @@ enum rockchip_pin_drv_type { DRV_TYPE_MAX }; -/** +/* * enum type index corresponding to rockchip_pull_list arrays index. */ enum rockchip_pin_pull_type { @@ -112,6 +113,7 @@ enum rockchip_pin_pull_type { }; /** + * struct rockchip_drv * @drv_type: drive strength variant using rockchip_perpin_drv_type * @offset: if initialized to -1 it will be autocalculated, by specifying * an initial offset value the relevant source offset can be reset @@ -125,8 +127,9 @@ struct rockchip_drv { }; /** + * struct rockchip_pin_bank * @reg_base: register base of the gpio bank - * @reg_pull: optional separate register for additional pull settings + * @regmap_pull: optional separate register for additional pull settings * @clk: clock of the gpio bank * @irq: interrupt of the gpio bank * @saved_masks: Saved content of GPIO_INTEN at suspend time. @@ -144,6 +147,8 @@ struct rockchip_drv { * @gpio_chip: gpiolib chip * @grange: gpio range * @slock: spinlock for the gpio bank + * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode + * @recalced_mask: bit mask to indicate a need to recalulate the mask * @route_mask: bits describing the routing pins of per bank */ struct rockchip_pin_bank { @@ -312,6 +317,7 @@ struct rockchip_mux_recalced_data { * @bank_num: bank number. * @pin: index at register or used to calc index. * @func: the min pin. + * @route_location: the mux route location (same, pmu, grf). * @route_offset: the max pin. * @route_val: the register offset. */ @@ -323,8 +329,6 @@ struct rockchip_mux_route_data { u32 route_val; }; -/** - */ struct rockchip_pin_ctrl { struct rockchip_pin_bank *pin_banks; u32 nr_banks; @@ -362,9 +366,7 @@ struct rockchip_pin_config { * @name: name of the pin group, used to lookup the group. * @pins: the pins included in this group. * @npins: number of pins included in this group. - * @func: the mux function number to be programmed when selected. - * @configs: the config values to be set for each pin - * @nconfigs: number of configs for each pin + * @data: local pin configuration */ struct rockchip_pin_group { const char *name; @@ -377,7 +379,7 @@ struct rockchip_pin_group { * struct rockchip_pmx_func: represent a pin function. * @name: name of the pin function, used to lookup the function. * @groups: one or more names of pin groups that provide this function. - * @num_groups: number of groups included in @groups. + * @ngroups: number of groups included in @groups. */ struct rockchip_pmx_func { const char *name; @@ -2502,6 +2504,7 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np, np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); ret = pinconf_generic_parse_dt_config(np_config, NULL, &grp->data[j].configs, &grp->data[j].nconfigs); + of_node_put(np_config); if (ret) return ret; } diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c index 14699e988a040418ee6fc9815294a17803a8de2b..fa6fa393fc23b716bc89c48afbf2e7fd04e85f7e 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c @@ -6238,7 +6238,7 @@ void ipa3_counter_remove_hdl(int hdl) offset = counter->hw_counter.start_id - 1; if (offset >= 0 && (offset + counter->hw_counter.num_counters) < IPA_FLT_RT_HW_COUNTER) { - memset(&ipa3_ctx->flt_rt_counters.used_hw + offset, + memset(&ipa3_ctx->flt_rt_counters.used_hw[offset], 0, counter->hw_counter.num_counters * sizeof(bool)); } else { IPAERR_RL("unexpected hdl %d\n", hdl); @@ -6247,7 +6247,7 @@ void ipa3_counter_remove_hdl(int hdl) offset = counter->sw_counter.start_id - 1 - IPA_FLT_RT_HW_COUNTER; if (offset >= 0 && (offset + counter->sw_counter.num_counters) < IPA_FLT_RT_SW_COUNTER) { - memset(&ipa3_ctx->flt_rt_counters.used_sw + offset, + memset(&ipa3_ctx->flt_rt_counters.used_sw[offset], 0, counter->sw_counter.num_counters * sizeof(bool)); } else { IPAERR_RL("unexpected hdl %d\n", hdl); diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h index 283786236a070baac8bbe5e665fec3c4623a99b6..0200541c27647977278a7923f44000d9bb9395d2 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h @@ -44,7 +44,7 @@ enum ipa_fltrt_equations { #define IPA3_0_HW_TBL_ADDR_MASK (127) #define IPA3_0_HW_RULE_BUF_SIZE (256) #define IPA3_0_HW_RULE_START_ALIGNMENT (7) -#define IPA3_0_HW_RULE_PREFETCH_BUF_SIZE (128) +#define IPA3_0_HW_RULE_PREFETCH_BUF_SIZE (256) /* diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c index a0284deed24f9c23edcb9476d1944a8714f9ab65..8101cb777e75727aa982d005b2ffc934fbcf836c 100644 --- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c @@ -489,8 +489,8 @@ static void ipa3_copy_qmi_flt_rule_ex( */ flt_spec_ptr = (struct ipa_filter_spec_ex_type_v01 *) flt_spec_ptr_void; - q6_ul_flt_rule_ptr->ip = flt_spec_ptr->ip_type; - q6_ul_flt_rule_ptr->action = flt_spec_ptr->filter_action; + q6_ul_flt_rule_ptr->ip = (enum ipa_ip_type)flt_spec_ptr->ip_type; + q6_ul_flt_rule_ptr->action = (enum ipa_flt_action)flt_spec_ptr->filter_action; if (flt_spec_ptr->is_routing_table_index_valid == true) q6_ul_flt_rule_ptr->rt_tbl_idx = flt_spec_ptr->route_table_index; diff --git a/drivers/platform/x86/asus-wmi.h b/drivers/platform/x86/asus-wmi.h index 57a79bddb28611c4b5603553f4a68911f4a526a7..95612878a841f3a1ef4dae3bbc9a6f6d5ff73bce 100644 --- a/drivers/platform/x86/asus-wmi.h +++ b/drivers/platform/x86/asus-wmi.h @@ -31,7 +31,7 @@ #include #define ASUS_WMI_KEY_IGNORE (-1) -#define ASUS_WMI_BRN_DOWN 0x20 +#define ASUS_WMI_BRN_DOWN 0x2e #define ASUS_WMI_BRN_UP 0x2f struct module; diff --git a/drivers/platform/x86/hdaps.c b/drivers/platform/x86/hdaps.c index c26baf77938eaba1657f9cda929f13aadf777822..96cc87d123292530ff03aaeb9fc873bebe1980c0 100644 --- a/drivers/platform/x86/hdaps.c +++ b/drivers/platform/x86/hdaps.c @@ -378,7 +378,7 @@ static ssize_t hdaps_variance_show(struct device *dev, static ssize_t hdaps_temp1_show(struct device *dev, struct device_attribute *attr, char *buf) { - u8 uninitialized_var(temp); + u8 temp; int ret; ret = hdaps_readb_one(HDAPS_PORT_TEMP1, &temp); @@ -391,7 +391,7 @@ static ssize_t hdaps_temp1_show(struct device *dev, static ssize_t hdaps_temp2_show(struct device *dev, struct device_attribute *attr, char *buf) { - u8 uninitialized_var(temp); + u8 temp; int ret; ret = hdaps_readb_one(HDAPS_PORT_TEMP2, &temp); diff --git a/drivers/platform/x86/intel-hid.c b/drivers/platform/x86/intel-hid.c index fa3cda69cec96135a570945ebd2e7e47ac79d732..159284bfdd7f201f409cf11dde49a5c3ce041c71 100644 --- a/drivers/platform/x86/intel-hid.c +++ b/drivers/platform/x86/intel-hid.c @@ -449,7 +449,7 @@ static bool button_array_present(struct platform_device *device) static int intel_hid_probe(struct platform_device *device) { acpi_handle handle = ACPI_HANDLE(&device->dev); - unsigned long long mode; + unsigned long long mode, dummy; struct intel_hid_priv *priv; acpi_status status; int err; @@ -501,18 +501,15 @@ static int intel_hid_probe(struct platform_device *device) if (err) goto err_remove_notify; - if (priv->array) { - unsigned long long dummy; + intel_button_array_enable(&device->dev, true); - intel_button_array_enable(&device->dev, true); - - /* Call button load method to enable HID power button */ - if (!intel_hid_evaluate_method(handle, INTEL_HID_DSM_BTNL_FN, - &dummy)) { - dev_warn(&device->dev, - "failed to enable HID power button\n"); - } - } + /* + * Call button load method to enable HID power button + * Always do this since it activates events on some devices without + * a button array too. + */ + if (!intel_hid_evaluate_method(handle, INTEL_HID_DSM_BTNL_FN, &dummy)) + dev_warn(&device->dev, "failed to enable HID power button\n"); device_init_wakeup(&device->dev, true); return 0; diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c index 42b31c549db00a336a960bf702864670fd93ed43..1781e67781a55952307da224225c260c1bc66ed8 100644 --- a/drivers/platform/x86/msi-laptop.c +++ b/drivers/platform/x86/msi-laptop.c @@ -223,7 +223,7 @@ static ssize_t set_device_state(const char *buf, size_t count, u8 mask) return -EINVAL; if (quirks->ec_read_only) - return -EOPNOTSUPP; + return 0; /* read current device state */ result = ec_read(MSI_STANDARD_EC_COMMAND_ADDRESS, &rdata); @@ -854,15 +854,15 @@ static bool msi_laptop_i8042_filter(unsigned char data, unsigned char str, static void msi_init_rfkill(struct work_struct *ignored) { if (rfk_wlan) { - rfkill_set_sw_state(rfk_wlan, !wlan_s); + msi_rfkill_set_state(rfk_wlan, !wlan_s); rfkill_wlan_set(NULL, !wlan_s); } if (rfk_bluetooth) { - rfkill_set_sw_state(rfk_bluetooth, !bluetooth_s); + msi_rfkill_set_state(rfk_bluetooth, !bluetooth_s); rfkill_bluetooth_set(NULL, !bluetooth_s); } if (rfk_threeg) { - rfkill_set_sw_state(rfk_threeg, !threeg_s); + msi_rfkill_set_state(rfk_threeg, !threeg_s); rfkill_threeg_set(NULL, !threeg_s); } } diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c index 912ce5cb2f084321762d091832edda8867280f79..1036ec368ddacc6de545f820c3e7b7dd584d5f53 100644 --- a/drivers/platform/x86/thinkpad_acpi.c +++ b/drivers/platform/x86/thinkpad_acpi.c @@ -9699,6 +9699,7 @@ static const struct tpacpi_quirk battery_quirk_table[] __initconst = { * Individual addressing is broken on models that expose the * primary battery as BAT1. */ + TPACPI_Q_LNV('8', 'F', true), /* Thinkpad X120e */ TPACPI_Q_LNV('J', '7', true), /* B5400 */ TPACPI_Q_LNV('J', 'I', true), /* Thinkpad 11e */ TPACPI_Q_LNV3('R', '0', 'B', true), /* Thinkpad 11e gen 3 */ diff --git a/drivers/platform/x86/touchscreen_dmi.c b/drivers/platform/x86/touchscreen_dmi.c index f122a0263a1ba525760c06209e5fb4b5d0f7a5b4..e26e2279ba6c324678af38479f5b0a38f2277b29 100644 --- a/drivers/platform/x86/touchscreen_dmi.c +++ b/drivers/platform/x86/touchscreen_dmi.c @@ -147,6 +147,22 @@ static const struct ts_dmi_data dexp_ursus_7w_data = { .properties = dexp_ursus_7w_props, }; +static const struct property_entry dexp_ursus_kx210i_props[] = { + PROPERTY_ENTRY_U32("touchscreen-min-x", 5), + PROPERTY_ENTRY_U32("touchscreen-min-y", 2), + PROPERTY_ENTRY_U32("touchscreen-size-x", 1720), + PROPERTY_ENTRY_U32("touchscreen-size-y", 1137), + PROPERTY_ENTRY_STRING("firmware-name", "gsl1680-dexp-ursus-kx210i.fw"), + PROPERTY_ENTRY_U32("silead,max-fingers", 10), + PROPERTY_ENTRY_BOOL("silead,home-button"), + { } +}; + +static const struct ts_dmi_data dexp_ursus_kx210i_data = { + .acpi_name = "MSSL1680:00", + .properties = dexp_ursus_kx210i_props, +}; + static const struct property_entry digma_citi_e200_props[] = { PROPERTY_ENTRY_U32("touchscreen-size-x", 1980), PROPERTY_ENTRY_U32("touchscreen-size-y", 1500), @@ -502,6 +518,14 @@ static const struct dmi_system_id touchscreen_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "7W"), }, }, + { + /* DEXP Ursus KX210i */ + .driver_data = (void *)&dexp_ursus_kx210i_data, + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "INSYDE Corp."), + DMI_MATCH(DMI_PRODUCT_NAME, "S107I"), + }, + }, { /* Digma Citi E200 */ .driver_data = (void *)&digma_citi_e200_data, diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c index 387358af685c5ba6c2f8725af450f27c64258b19..136347a195ece3556f51cae4eea5c72ea53b30cb 100644 --- a/drivers/platform/x86/wmi.c +++ b/drivers/platform/x86/wmi.c @@ -172,7 +172,7 @@ static int get_subobj_info(acpi_handle handle, const char *pathname, static acpi_status wmi_method_enable(struct wmi_block *wblock, int enable) { - struct guid_block *block = NULL; + struct guid_block *block; char method[5]; acpi_status status; acpi_handle handle; @@ -246,8 +246,8 @@ EXPORT_SYMBOL_GPL(wmi_evaluate_method); acpi_status wmidev_evaluate_method(struct wmi_device *wdev, u8 instance, u32 method_id, const struct acpi_buffer *in, struct acpi_buffer *out) { - struct guid_block *block = NULL; - struct wmi_block *wblock = NULL; + struct guid_block *block; + struct wmi_block *wblock; acpi_handle handle; acpi_status status; struct acpi_object_list input; @@ -294,7 +294,7 @@ EXPORT_SYMBOL_GPL(wmidev_evaluate_method); static acpi_status __query_block(struct wmi_block *wblock, u8 instance, struct acpi_buffer *out) { - struct guid_block *block = NULL; + struct guid_block *block; acpi_handle handle; acpi_status status, wc_status = AE_ERROR; struct acpi_object_list input; @@ -409,8 +409,8 @@ EXPORT_SYMBOL_GPL(wmidev_block_query); acpi_status wmi_set_block(const char *guid_string, u8 instance, const struct acpi_buffer *in) { - struct guid_block *block = NULL; struct wmi_block *wblock = NULL; + struct guid_block *block; acpi_handle handle; struct acpi_object_list input; union acpi_object params[2]; @@ -793,21 +793,13 @@ static int wmi_dev_match(struct device *dev, struct device_driver *driver) } static int wmi_char_open(struct inode *inode, struct file *filp) { - const char *driver_name = filp->f_path.dentry->d_iname; - struct wmi_block *wblock = NULL; - struct wmi_block *next = NULL; - - list_for_each_entry_safe(wblock, next, &wmi_block_list, list) { - if (!wblock->dev.dev.driver) - continue; - if (strcmp(driver_name, wblock->dev.dev.driver->name) == 0) { - filp->private_data = wblock; - break; - } - } + /* + * The miscdevice already stores a pointer to itself + * inside filp->private_data + */ + struct wmi_block *wblock = container_of(filp->private_data, struct wmi_block, char_dev); - if (!filp->private_data) - return -ENODEV; + filp->private_data = wblock; return nonseekable_open(inode, filp); } @@ -827,8 +819,8 @@ static long wmi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) struct wmi_ioctl_buffer __user *input = (struct wmi_ioctl_buffer __user *) arg; struct wmi_block *wblock = filp->private_data; - struct wmi_ioctl_buffer *buf = NULL; - struct wmi_driver *wdriver = NULL; + struct wmi_ioctl_buffer *buf; + struct wmi_driver *wdriver; int ret; if (_IOC_TYPE(cmd) != WMI_IOC) @@ -1131,8 +1123,8 @@ static int parse_wdg(struct device *wmi_bus_dev, struct acpi_device *device) struct wmi_block *wblock, *next; union acpi_object *obj; acpi_status status; - int retval = 0; u32 i, total; + int retval; status = acpi_evaluate_object(device->handle, "_WDG", NULL, &out); if (ACPI_FAILURE(status)) @@ -1143,8 +1135,8 @@ static int parse_wdg(struct device *wmi_bus_dev, struct acpi_device *device) return -ENXIO; if (obj->type != ACPI_TYPE_BUFFER) { - retval = -ENXIO; - goto out_free_pointer; + kfree(obj); + return -ENXIO; } gblock = (const struct guid_block *)obj->buffer.pointer; @@ -1165,8 +1157,8 @@ static int parse_wdg(struct device *wmi_bus_dev, struct acpi_device *device) wblock = kzalloc(sizeof(struct wmi_block), GFP_KERNEL); if (!wblock) { - retval = -ENOMEM; - break; + dev_err(wmi_bus_dev, "Failed to allocate %pUL\n", &gblock[i].guid); + continue; } wblock->acpi_device = device; @@ -1205,9 +1197,9 @@ static int parse_wdg(struct device *wmi_bus_dev, struct acpi_device *device) } } -out_free_pointer: - kfree(out.pointer); - return retval; + kfree(obj); + + return 0; } /* diff --git a/drivers/power/supply/ab8500_btemp.c b/drivers/power/supply/ab8500_btemp.c index 0fd24577112eb9c6430e175c73059a40ed689af7..0bec8b90667c873145fa6b9874babebf855c271b 100644 --- a/drivers/power/supply/ab8500_btemp.c +++ b/drivers/power/supply/ab8500_btemp.c @@ -919,10 +919,8 @@ static int ab8500_btemp_get_ext_psy_data(struct device *dev, void *data) */ static void ab8500_btemp_external_power_changed(struct power_supply *psy) { - struct ab8500_btemp *di = power_supply_get_drvdata(psy); - - class_for_each_device(power_supply_class, NULL, - di->btemp_psy, ab8500_btemp_get_ext_psy_data); + class_for_each_device(power_supply_class, NULL, psy, + ab8500_btemp_get_ext_psy_data); } /* ab8500 btemp driver interrupts and their respective isr */ diff --git a/drivers/power/supply/ab8500_fg.c b/drivers/power/supply/ab8500_fg.c index 675f9d0e8471e5d80ae1682cb4763271923ec446..d0cbd7189a622eec720195d527e87b6bad8da493 100644 --- a/drivers/power/supply/ab8500_fg.c +++ b/drivers/power/supply/ab8500_fg.c @@ -2380,10 +2380,8 @@ static int ab8500_fg_init_hw_registers(struct ab8500_fg *di) */ static void ab8500_fg_external_power_changed(struct power_supply *psy) { - struct ab8500_fg *di = power_supply_get_drvdata(psy); - - class_for_each_device(power_supply_class, NULL, - di->fg_psy, ab8500_fg_get_ext_psy_data); + class_for_each_device(power_supply_class, NULL, psy, + ab8500_fg_get_ext_psy_data); } /** diff --git a/drivers/power/supply/bq24190_charger.c b/drivers/power/supply/bq24190_charger.c index c830343be61e5c4cf10dc3f476e3c5a54c64773b..1a3624141c4119c2c67f9b00a45c62fd00a1b5dc 100644 --- a/drivers/power/supply/bq24190_charger.c +++ b/drivers/power/supply/bq24190_charger.c @@ -1228,8 +1228,19 @@ static void bq24190_input_current_limit_work(struct work_struct *work) struct bq24190_dev_info *bdi = container_of(work, struct bq24190_dev_info, input_current_limit_work.work); + union power_supply_propval val; + int ret; - power_supply_set_input_current_limit_from_supplier(bdi->charger); + ret = power_supply_get_property_from_supplier(bdi->charger, + POWER_SUPPLY_PROP_CURRENT_MAX, + &val); + if (ret) + return; + + bq24190_charger_set_property(bdi->charger, + POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, + &val); + power_supply_changed(bdi->charger); } /* Sync the input-current-limit with our parent supply (if we have one) */ diff --git a/drivers/power/supply/bq27xxx_battery.c b/drivers/power/supply/bq27xxx_battery.c index b7dc881268666e92c76bd655e142df67ffdb0c72..f665553b26a2ddc32a2b5b9418266becc45d32de 100644 --- a/drivers/power/supply/bq27xxx_battery.c +++ b/drivers/power/supply/bq27xxx_battery.c @@ -877,10 +877,8 @@ static int poll_interval_param_set(const char *val, const struct kernel_param *k return ret; mutex_lock(&bq27xxx_list_lock); - list_for_each_entry(di, &bq27xxx_battery_devices, list) { - cancel_delayed_work_sync(&di->work); - schedule_delayed_work(&di->work, 0); - } + list_for_each_entry(di, &bq27xxx_battery_devices, list) + mod_delayed_work(system_wq, &di->work, 0); mutex_unlock(&bq27xxx_list_lock); return ret; @@ -1551,7 +1549,7 @@ static int bq27xxx_battery_read_health(struct bq27xxx_device_info *di) return POWER_SUPPLY_HEALTH_GOOD; } -void bq27xxx_battery_update(struct bq27xxx_device_info *di) +static void bq27xxx_battery_update_unlocked(struct bq27xxx_device_info *di) { struct bq27xxx_reg_cache cache = {0, }; bool has_ci_flag = di->opts & BQ27XXX_O_ZERO; @@ -1599,6 +1597,16 @@ void bq27xxx_battery_update(struct bq27xxx_device_info *di) di->cache = cache; di->last_update = jiffies; + + if (!di->removed && poll_interval > 0) + mod_delayed_work(system_wq, &di->work, poll_interval * HZ); +} + +void bq27xxx_battery_update(struct bq27xxx_device_info *di) +{ + mutex_lock(&di->lock); + bq27xxx_battery_update_unlocked(di); + mutex_unlock(&di->lock); } EXPORT_SYMBOL_GPL(bq27xxx_battery_update); @@ -1609,9 +1617,6 @@ static void bq27xxx_battery_poll(struct work_struct *work) work.work); bq27xxx_battery_update(di); - - if (poll_interval > 0) - schedule_delayed_work(&di->work, poll_interval * HZ); } /* @@ -1772,10 +1777,8 @@ static int bq27xxx_battery_get_property(struct power_supply *psy, struct bq27xxx_device_info *di = power_supply_get_drvdata(psy); mutex_lock(&di->lock); - if (time_is_before_jiffies(di->last_update + 5 * HZ)) { - cancel_delayed_work_sync(&di->work); - bq27xxx_battery_poll(&di->work.work); - } + if (time_is_before_jiffies(di->last_update + 5 * HZ)) + bq27xxx_battery_update_unlocked(di); mutex_unlock(&di->lock); if (psp != POWER_SUPPLY_PROP_PRESENT && di->cache.flags < 0) @@ -1859,8 +1862,8 @@ static void bq27xxx_external_power_changed(struct power_supply *psy) { struct bq27xxx_device_info *di = power_supply_get_drvdata(psy); - cancel_delayed_work_sync(&di->work); - schedule_delayed_work(&di->work, 0); + /* After charger plug in/out wait 0.5s for things to stabilize */ + mod_delayed_work(system_wq, &di->work, HZ / 2); } int bq27xxx_battery_setup(struct bq27xxx_device_info *di) @@ -1912,22 +1915,18 @@ EXPORT_SYMBOL_GPL(bq27xxx_battery_setup); void bq27xxx_battery_teardown(struct bq27xxx_device_info *di) { - /* - * power_supply_unregister call bq27xxx_battery_get_property which - * call bq27xxx_battery_poll. - * Make sure that bq27xxx_battery_poll will not call - * schedule_delayed_work again after unregister (which cause OOPS). - */ - poll_interval = 0; - - cancel_delayed_work_sync(&di->work); - - power_supply_unregister(di->bat); - mutex_lock(&bq27xxx_list_lock); list_del(&di->list); mutex_unlock(&bq27xxx_list_lock); + /* Set removed to avoid bq27xxx_battery_update() re-queuing the work */ + mutex_lock(&di->lock); + di->removed = true; + mutex_unlock(&di->lock); + + cancel_delayed_work_sync(&di->work); + + power_supply_unregister(di->bat); mutex_destroy(&di->lock); } EXPORT_SYMBOL_GPL(bq27xxx_battery_teardown); diff --git a/drivers/power/supply/bq27xxx_battery_i2c.c b/drivers/power/supply/bq27xxx_battery_i2c.c index 06dd5077104cc7e017b8fa33be49f0ccd22dcac3..0fbc221ee50ef7a1fbc69630e156302f7f5145eb 100644 --- a/drivers/power/supply/bq27xxx_battery_i2c.c +++ b/drivers/power/supply/bq27xxx_battery_i2c.c @@ -187,7 +187,7 @@ static int bq27xxx_battery_i2c_probe(struct i2c_client *client, i2c_set_clientdata(client, di); if (client->irq) { - ret = devm_request_threaded_irq(&client->dev, client->irq, + ret = request_threaded_irq(client->irq, NULL, bq27xxx_battery_irq_handler_thread, IRQF_ONESHOT, di->name, di); @@ -217,6 +217,7 @@ static int bq27xxx_battery_i2c_remove(struct i2c_client *client) { struct bq27xxx_device_info *di = i2c_get_clientdata(client); + free_irq(client->irq, di); bq27xxx_battery_teardown(di); mutex_lock(&battery_mutex); diff --git a/drivers/power/supply/cros_usbpd-charger.c b/drivers/power/supply/cros_usbpd-charger.c index 688a16bacfbbd509e053358cb6f59b5715f49864..74b5914abbf7e83bf1d2de96f6d298fe852eda6f 100644 --- a/drivers/power/supply/cros_usbpd-charger.c +++ b/drivers/power/supply/cros_usbpd-charger.c @@ -242,7 +242,7 @@ static int cros_usbpd_charger_get_power_info(struct port_data *port) port->psy_current_max = 0; break; default: - dev_err(dev, "Port %d: default case!\n", port->port_number); + dev_dbg(dev, "Port %d: default case!\n", port->port_number); port->psy_usb_type = POWER_SUPPLY_USB_TYPE_SDP; } diff --git a/drivers/power/supply/da9150-charger.c b/drivers/power/supply/da9150-charger.c index 60099815296e75d86cfcde6a18d14c428214f987..b2d38eb32288a78d873e0e423010a0f74b46240c 100644 --- a/drivers/power/supply/da9150-charger.c +++ b/drivers/power/supply/da9150-charger.c @@ -666,6 +666,7 @@ static int da9150_charger_remove(struct platform_device *pdev) if (!IS_ERR_OR_NULL(charger->usb_phy)) usb_unregister_notifier(charger->usb_phy, &charger->otg_nb); + cancel_work_sync(&charger->otg_work); power_supply_unregister(charger->battery); power_supply_unregister(charger->usb); diff --git a/drivers/power/supply/generic-adc-battery.c b/drivers/power/supply/generic-adc-battery.c index 97b0e873e87d2e0aea2b787a4cd8daeae6de14cb..c2d6378bb897d6612119868d423de13c7ba0389b 100644 --- a/drivers/power/supply/generic-adc-battery.c +++ b/drivers/power/supply/generic-adc-battery.c @@ -138,6 +138,9 @@ static int read_channel(struct gab *adc_bat, enum power_supply_property psp, result); if (ret < 0) pr_err("read channel error\n"); + else + *result *= 1000; + return ret; } diff --git a/drivers/power/supply/power_supply_core.c b/drivers/power/supply/power_supply_core.c index 4954c8772b6f2a9af2c583d38f61ba6a4fd90c49..84e10b27bab080d1ff134d9bffb6a718866c535e 100644 --- a/drivers/power/supply/power_supply_core.c +++ b/drivers/power/supply/power_supply_core.c @@ -354,6 +354,10 @@ static int __power_supply_is_system_supplied(struct device *dev, void *data) struct power_supply *psy = dev_get_drvdata(dev); unsigned int *count = data; + if (!psy->desc->get_property(psy, POWER_SUPPLY_PROP_SCOPE, &ret)) + if (ret.intval == POWER_SUPPLY_SCOPE_DEVICE) + return 0; + (*count)++; if (psy->desc->type != POWER_SUPPLY_TYPE_BATTERY) if (!psy->desc->get_property(psy, POWER_SUPPLY_PROP_ONLINE, @@ -372,8 +376,8 @@ int power_supply_is_system_supplied(void) __power_supply_is_system_supplied); /* - * If no power class device was found at all, most probably we are - * running on a desktop system, so assume we are on mains power. + * If no system scope power class device was found at all, most probably we + * are running on a desktop system, so assume we are on mains power. */ if (count == 0) return 1; @@ -382,46 +386,49 @@ int power_supply_is_system_supplied(void) } EXPORT_SYMBOL_GPL(power_supply_is_system_supplied); -static int __power_supply_get_supplier_max_current(struct device *dev, - void *data) +struct psy_get_supplier_prop_data { + struct power_supply *psy; + enum power_supply_property psp; + union power_supply_propval *val; +}; + +static int __power_supply_get_supplier_property(struct device *dev, void *_data) { - union power_supply_propval ret = {0,}; struct power_supply *epsy = dev_get_drvdata(dev); - struct power_supply *psy = data; + struct psy_get_supplier_prop_data *data = _data; - if (__power_supply_is_supplied_by(epsy, psy)) - if (!epsy->desc->get_property(epsy, - POWER_SUPPLY_PROP_CURRENT_MAX, - &ret)) - return ret.intval; + if (__power_supply_is_supplied_by(epsy, data->psy)) + if (!epsy->desc->get_property(epsy, data->psp, data->val)) + return 1; /* Success */ - return 0; + return 0; /* Continue iterating */ } -int power_supply_set_input_current_limit_from_supplier(struct power_supply *psy) +int power_supply_get_property_from_supplier(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) { - union power_supply_propval val = {0,}; - int curr; - - if (!psy->desc->set_property) - return -EINVAL; + struct psy_get_supplier_prop_data data = { + .psy = psy, + .psp = psp, + .val = val, + }; + int ret; /* * This function is not intended for use with a supply with multiple - * suppliers, we simply pick the first supply to report a non 0 - * max-current. + * suppliers, we simply pick the first supply to report the psp. */ - curr = class_for_each_device(power_supply_class, NULL, psy, - __power_supply_get_supplier_max_current); - if (curr <= 0) - return (curr == 0) ? -ENODEV : curr; - - val.intval = curr; + ret = class_for_each_device(power_supply_class, NULL, &data, + __power_supply_get_supplier_property); + if (ret < 0) + return ret; + if (ret == 0) + return -ENODEV; - return psy->desc->set_property(psy, - POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val); + return 0; } -EXPORT_SYMBOL_GPL(power_supply_set_input_current_limit_from_supplier); +EXPORT_SYMBOL_GPL(power_supply_get_property_from_supplier); int power_supply_set_battery_charged(struct power_supply *psy) { diff --git a/drivers/power/supply/power_supply_leds.c b/drivers/power/supply/power_supply_leds.c index 2277ad9c2f6825da0a96e77e087c4999d0f4f74e..9188b7ccdd4c72b41fa498838b60ab7066c4331f 100644 --- a/drivers/power/supply/power_supply_leds.c +++ b/drivers/power/supply/power_supply_leds.c @@ -35,8 +35,9 @@ static void power_supply_update_bat_leds(struct power_supply *psy) led_trigger_event(psy->charging_full_trig, LED_FULL); led_trigger_event(psy->charging_trig, LED_OFF); led_trigger_event(psy->full_trig, LED_FULL); - led_trigger_event(psy->charging_blink_full_solid_trig, - LED_FULL); + /* Going from blink to LED on requires a LED_OFF event to stop blink */ + led_trigger_event(psy->charging_blink_full_solid_trig, LED_OFF); + led_trigger_event(psy->charging_blink_full_solid_trig, LED_FULL); break; case POWER_SUPPLY_STATUS_CHARGING: led_trigger_event(psy->charging_full_trig, LED_FULL); diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supply/power_supply_sysfs.c index 947cc1b26a5249dbc46515f1c97f1e6e2843134f..9b7ced43aa6ba87ec9b28351f72489f85710df33 100644 --- a/drivers/power/supply/power_supply_sysfs.c +++ b/drivers/power/supply/power_supply_sysfs.c @@ -148,7 +148,8 @@ static ssize_t power_supply_show_property(struct device *dev, if (ret < 0) { if (ret == -ENODATA) - dev_dbg(dev, "driver has no data for `%s' property\n", + dev_dbg_ratelimited(dev, + "driver has no data for `%s' property\n", attr->attr.name); else if (ret != -ENODEV && ret != -EAGAIN) dev_err_ratelimited(dev, diff --git a/drivers/power/supply/sbs-charger.c b/drivers/power/supply/sbs-charger.c index 15947dbb511e320dfd80d8e9968f313d4c54550a..0f9cc82d81618f1d0a21bf0fc0345241442a7eb2 100644 --- a/drivers/power/supply/sbs-charger.c +++ b/drivers/power/supply/sbs-charger.c @@ -29,7 +29,7 @@ #define SBS_CHARGER_REG_STATUS 0x13 #define SBS_CHARGER_REG_ALARM_WARNING 0x16 -#define SBS_CHARGER_STATUS_CHARGE_INHIBITED BIT(1) +#define SBS_CHARGER_STATUS_CHARGE_INHIBITED BIT(0) #define SBS_CHARGER_STATUS_RES_COLD BIT(9) #define SBS_CHARGER_STATUS_RES_HOT BIT(10) #define SBS_CHARGER_STATUS_BATTERY_PRESENT BIT(14) diff --git a/drivers/powercap/powercap_sys.c b/drivers/powercap/powercap_sys.c index 60c8375c3c816cad88f34c1b46aa0674a9a906d8..0a63fac54fd93d2d797ff49454ffc74387192668 100644 --- a/drivers/powercap/powercap_sys.c +++ b/drivers/powercap/powercap_sys.c @@ -542,9 +542,6 @@ struct powercap_zone *powercap_register_zone( power_zone->name = kstrdup(name, GFP_KERNEL); if (!power_zone->name) goto err_name_alloc; - dev_set_name(&power_zone->dev, "%s:%x", - dev_name(power_zone->dev.parent), - power_zone->id); power_zone->constraints = kcalloc(nr_constraints, sizeof(*power_zone->constraints), GFP_KERNEL); @@ -567,9 +564,16 @@ struct powercap_zone *powercap_register_zone( power_zone->dev_attr_groups[0] = &power_zone->dev_zone_attr_group; power_zone->dev_attr_groups[1] = NULL; power_zone->dev.groups = power_zone->dev_attr_groups; + dev_set_name(&power_zone->dev, "%s:%x", + dev_name(power_zone->dev.parent), + power_zone->id); result = device_register(&power_zone->dev); - if (result) - goto err_dev_ret; + if (result) { + put_device(&power_zone->dev); + mutex_unlock(&control_type->lock); + + return ERR_PTR(result); + } control_type->nr_zones++; mutex_unlock(&control_type->lock); diff --git a/drivers/ptp/ptp_chardev.c b/drivers/ptp/ptp_chardev.c index 796eeffdf93b1240af7be112ed4356881773b525..8ff2dd5c52e647c3f4706005cfa4f0f51e612a03 100644 --- a/drivers/ptp/ptp_chardev.c +++ b/drivers/ptp/ptp_chardev.c @@ -346,7 +346,8 @@ ssize_t ptp_read(struct posix_clock *pc, for (i = 0; i < cnt; i++) { event[i] = queue->buf[queue->head]; - queue->head = (queue->head + 1) % PTP_MAX_TIMESTAMPS; + /* Paired with READ_ONCE() in queue_cnt() */ + WRITE_ONCE(queue->head, (queue->head + 1) % PTP_MAX_TIMESTAMPS); } spin_unlock_irqrestore(&queue->lock, flags); diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c index 89632cc9c28fc5a5eb6e01d7576ad9c629e6518e..1e92bd897aa45cdc36d3d8b19b74ba264dc28be2 100644 --- a/drivers/ptp/ptp_clock.c +++ b/drivers/ptp/ptp_clock.c @@ -68,10 +68,11 @@ static void enqueue_external_timestamp(struct timestamp_event_queue *queue, dst->t.sec = seconds; dst->t.nsec = remainder; + /* Both WRITE_ONCE() are paired with READ_ONCE() in queue_cnt() */ if (!queue_free(queue)) - queue->head = (queue->head + 1) % PTP_MAX_TIMESTAMPS; + WRITE_ONCE(queue->head, (queue->head + 1) % PTP_MAX_TIMESTAMPS); - queue->tail = (queue->tail + 1) % PTP_MAX_TIMESTAMPS; + WRITE_ONCE(queue->tail, (queue->tail + 1) % PTP_MAX_TIMESTAMPS); spin_unlock_irqrestore(&queue->lock, flags); } diff --git a/drivers/ptp/ptp_private.h b/drivers/ptp/ptp_private.h index 05f6b6a9bbd580192679b184d5e2ccdc50ce3b12..1e02b5ae6127b0e3702bc171969336f8319c28ef 100644 --- a/drivers/ptp/ptp_private.h +++ b/drivers/ptp/ptp_private.h @@ -68,9 +68,13 @@ struct ptp_clock { * that a writer might concurrently increment the tail does not * matter, since the queue remains nonempty nonetheless. */ -static inline int queue_cnt(struct timestamp_event_queue *q) +static inline int queue_cnt(const struct timestamp_event_queue *q) { - int cnt = q->tail - q->head; + /* + * Paired with WRITE_ONCE() in enqueue_external_timestamp(), + * ptp_read(), extts_fifo_show(). + */ + int cnt = READ_ONCE(q->tail) - READ_ONCE(q->head); return cnt < 0 ? PTP_MAX_TIMESTAMPS + cnt : cnt; } diff --git a/drivers/ptp/ptp_sysfs.c b/drivers/ptp/ptp_sysfs.c index f97a5eefa2e23646834bb0de4482c3661c71cbce..b9e2f089606887451cbf302abd055bf94ede5492 100644 --- a/drivers/ptp/ptp_sysfs.c +++ b/drivers/ptp/ptp_sysfs.c @@ -91,7 +91,8 @@ static ssize_t extts_fifo_show(struct device *dev, qcnt = queue_cnt(queue); if (qcnt) { event = queue->buf[queue->head]; - queue->head = (queue->head + 1) % PTP_MAX_TIMESTAMPS; + /* Paired with READ_ONCE() in queue_cnt() */ + WRITE_ONCE(queue->head, (queue->head + 1) % PTP_MAX_TIMESTAMPS); } spin_unlock_irqrestore(&queue->lock, flags); diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index f2361a68a74a4c42062dc0ad5ad61d3178b84c20..288942dc2b15a75b3fa8de5a1eaeb38df9731498 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -520,4 +520,14 @@ config PWM_ZX To compile this driver as a module, choose M here: the module will be called pwm-zx. +config PWM_QCOM + tristate "Qualcomm Technologies, Inc. PWM support" + depends on ARCH_QCOM + help + Generic PWM framework driver for the PWM controller found on + Qualcomm Technologies Inc. SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-qcom. + endif diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 9014b91b770f0f63c43fb521bf9ed47be1abfdba..46345a2388994b1b45370c6dd488a25a3f595cfe 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o +obj-$(CONFIG_PWM_QCOM) += pwm-qcom.o obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o obj-$(CONFIG_PWM_QTI_LPG) += pwm-qti-lpg.o obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o diff --git a/drivers/pwm/pwm-brcmstb.c b/drivers/pwm/pwm-brcmstb.c index 8063cffa1c96031ef7c24cff02086a99e25b96b3..5d7842a62d59429867770d33d9c66c5d954ae283 100644 --- a/drivers/pwm/pwm-brcmstb.c +++ b/drivers/pwm/pwm-brcmstb.c @@ -307,7 +307,7 @@ static int brcmstb_pwm_suspend(struct device *dev) { struct brcmstb_pwm *p = dev_get_drvdata(dev); - clk_disable(p->clk); + clk_disable_unprepare(p->clk); return 0; } @@ -316,7 +316,7 @@ static int brcmstb_pwm_resume(struct device *dev) { struct brcmstb_pwm *p = dev_get_drvdata(dev); - clk_enable(p->clk); + clk_prepare_enable(p->clk); return 0; } diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c index 98f6ac6cf6ab4f9fcda159ae51e5017c519ed042..bedf6298acfbbb810d5e2dc751195a6e1e2d8851 100644 --- a/drivers/pwm/pwm-cros-ec.c +++ b/drivers/pwm/pwm-cros-ec.c @@ -125,6 +125,7 @@ static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, state->enabled = (ret > 0); state->period = EC_PWM_MAX_DUTY; + state->polarity = PWM_POLARITY_NORMAL; /* Note that "disabled" and "duty cycle == 0" are treated the same */ state->duty_cycle = ret; diff --git a/drivers/pwm/pwm-lpc32xx.c b/drivers/pwm/pwm-lpc32xx.c index ed8e9406b4af2568591b84962c5ef653c96717d9..b5f8b86b328af5b5ad35a665f5b00912b63f3d29 100644 --- a/drivers/pwm/pwm-lpc32xx.c +++ b/drivers/pwm/pwm-lpc32xx.c @@ -55,10 +55,10 @@ static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, if (duty_cycles > 255) duty_cycles = 255; - val = readl(lpc32xx->base + (pwm->hwpwm << 2)); + val = readl(lpc32xx->base); val &= ~0xFFFF; val |= (period_cycles << 8) | duty_cycles; - writel(val, lpc32xx->base + (pwm->hwpwm << 2)); + writel(val, lpc32xx->base); return 0; } @@ -73,9 +73,9 @@ static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) if (ret) return ret; - val = readl(lpc32xx->base + (pwm->hwpwm << 2)); + val = readl(lpc32xx->base); val |= PWM_ENABLE; - writel(val, lpc32xx->base + (pwm->hwpwm << 2)); + writel(val, lpc32xx->base); return 0; } @@ -85,9 +85,9 @@ static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); u32 val; - val = readl(lpc32xx->base + (pwm->hwpwm << 2)); + val = readl(lpc32xx->base); val &= ~PWM_ENABLE; - writel(val, lpc32xx->base + (pwm->hwpwm << 2)); + writel(val, lpc32xx->base); clk_disable_unprepare(lpc32xx->clk); } @@ -125,9 +125,9 @@ static int lpc32xx_pwm_probe(struct platform_device *pdev) lpc32xx->chip.base = -1; /* If PWM is disabled, configure the output to the default value */ - val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); + val = readl(lpc32xx->base); val &= ~PWM_PIN_LEVEL; - writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); + writel(val, lpc32xx->base); ret = pwmchip_add(&lpc32xx->chip); if (ret < 0) { diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index e247ab632530bac5d07c22f816b68681ac866578..90aba3091b2367fc3623493ef16ff1961abf0f50 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -425,7 +425,7 @@ static const struct meson_pwm_data pwm_axg_ee_data = { }; static const char * const pwm_axg_ao_parent_names[] = { - "aoclk81", "xtal", "fclk_div4", "fclk_div5" + "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" }; static const struct meson_pwm_data pwm_axg_ao_data = { diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index 893940d45f0d0859d5aaeaa6cd70ff67bb5dd34b..c49b1e696b8c4430e657b355625179cf0481f68a 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -82,6 +82,19 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, u64 div, rate; int err; + err = clk_prepare_enable(mdp->clk_main); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); + return err; + } + + err = clk_prepare_enable(mdp->clk_mm); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); + clk_disable_unprepare(mdp->clk_main); + return err; + } + /* * Find period, high_width and clk_div to suit duty_ns and period_ns. * Calculate proper div value to keep period value in the bound. @@ -95,8 +108,11 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, rate = clk_get_rate(mdp->clk_main); clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >> PWM_PERIOD_BIT_WIDTH; - if (clk_div > PWM_CLKDIV_MAX) + if (clk_div > PWM_CLKDIV_MAX) { + clk_disable_unprepare(mdp->clk_mm); + clk_disable_unprepare(mdp->clk_main); return -EINVAL; + } div = NSEC_PER_SEC * (clk_div + 1); period = div64_u64(rate * period_ns, div); @@ -106,14 +122,17 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, high_width = div64_u64(rate * duty_ns, div); value = period | (high_width << PWM_HIGH_WIDTH_SHIFT); - err = clk_enable(mdp->clk_main); - if (err < 0) - return err; - - err = clk_enable(mdp->clk_mm); - if (err < 0) { - clk_disable(mdp->clk_main); - return err; + if (mdp->data->bls_debug && !mdp->data->has_commit) { + /* + * For MT2701, disable double buffer before writing register + * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH. + */ + mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, + mdp->data->bls_debug_mask, + mdp->data->bls_debug_mask); + mtk_disp_pwm_update_bits(mdp, mdp->data->con0, + mdp->data->con0_sel, + mdp->data->con0_sel); } mtk_disp_pwm_update_bits(mdp, mdp->data->con0, @@ -132,8 +151,8 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 0x0); } - clk_disable(mdp->clk_mm); - clk_disable(mdp->clk_main); + clk_disable_unprepare(mdp->clk_mm); + clk_disable_unprepare(mdp->clk_main); return 0; } @@ -143,13 +162,16 @@ static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); int err; - err = clk_enable(mdp->clk_main); - if (err < 0) + err = clk_prepare_enable(mdp->clk_main); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); return err; + } - err = clk_enable(mdp->clk_mm); + err = clk_prepare_enable(mdp->clk_mm); if (err < 0) { - clk_disable(mdp->clk_main); + dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); + clk_disable_unprepare(mdp->clk_main); return err; } @@ -166,8 +188,8 @@ static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, 0x0); - clk_disable(mdp->clk_mm); - clk_disable(mdp->clk_main); + clk_disable_unprepare(mdp->clk_mm); + clk_disable_unprepare(mdp->clk_main); } static const struct pwm_ops mtk_disp_pwm_ops = { @@ -202,14 +224,6 @@ static int mtk_disp_pwm_probe(struct platform_device *pdev) if (IS_ERR(mdp->clk_mm)) return PTR_ERR(mdp->clk_mm); - ret = clk_prepare(mdp->clk_main); - if (ret < 0) - return ret; - - ret = clk_prepare(mdp->clk_mm); - if (ret < 0) - goto disable_clk_main; - mdp->chip.dev = &pdev->dev; mdp->chip.ops = &mtk_disp_pwm_ops; mdp->chip.base = -1; @@ -217,44 +231,22 @@ static int mtk_disp_pwm_probe(struct platform_device *pdev) ret = pwmchip_add(&mdp->chip); if (ret < 0) { - dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); - goto disable_clk_mm; + dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret)); + return ret; } platform_set_drvdata(pdev, mdp); - /* - * For MT2701, disable double buffer before writing register - * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH. - */ - if (!mdp->data->has_commit) { - mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, - mdp->data->bls_debug_mask, - mdp->data->bls_debug_mask); - mtk_disp_pwm_update_bits(mdp, mdp->data->con0, - mdp->data->con0_sel, - mdp->data->con0_sel); - } - return 0; - -disable_clk_mm: - clk_unprepare(mdp->clk_mm); -disable_clk_main: - clk_unprepare(mdp->clk_main); - return ret; } static int mtk_disp_pwm_remove(struct platform_device *pdev) { struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev); - int ret; - ret = pwmchip_remove(&mdp->chip); - clk_unprepare(mdp->clk_mm); - clk_unprepare(mdp->clk_main); + pwmchip_remove(&mdp->chip); - return ret; + return 0; } static const struct mtk_pwm_data mt2701_pwm_data = { diff --git a/drivers/pwm/pwm-qcom.c b/drivers/pwm/pwm-qcom.c new file mode 100644 index 0000000000000000000000000000000000000000..7ab90dd995746fbee095b856a4e0a4ab62632e95 --- /dev/null +++ b/drivers/pwm/pwm-qcom.c @@ -0,0 +1,667 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PERIOD_TO_HZ(period_ns) ((1 * 1000000000UL) / period_ns) +#define FRAME_NUM_MAX_LEN 9 + +/* Offsets */ +#define PWM_TOPCTL0 0x0 + +/* offsets per frame */ +#define PWM_CTL0 0x0 +#define PWM_CTL1 0x4 +#define PWM_CTL2 0x8 +#define PWM_CYC_CFG 0xC +#define PWM_UPDATE 0x10 +#define PWM_PERIOD_CNT 0x14 + +enum { + ENABLE_STATUS0, + ENABLE_STATUS1, + + ENABLE_STATUS_REG_SIZE, +}; + +struct pdm_pwm_priv_data { + unsigned int max_channels; + const u16 *status_reg_offsets; +}; + +/* + *struct pdm_pwm_frames - Information regarding per pdm frame + * @frame_id: Id number associated with each frame. + * @reg_offset: offset of each frame from base pdm. + * @current_period_ns: Current period of the particular frame. + * @current_duty_ns: Current duty cycle of the particular frame. + * @current_freq: Current frequency of frame. + * @freq_set: This bool flag is responsible for setting period once per frame. + * @mutex: mutex lock per frame. + */ +struct pdm_pwm_frames { + u32 frame_id; + u32 reg_offset; + u64 current_period_ns; + u64 current_duty_ns; + unsigned long current_freq; + bool is_enabled; + bool freq_set; + struct mutex frame_lock; /* PWM per frame lock */ + struct pdm_pwm_chip *pwm_chip; +}; + +/* + *struct pdm_pwm_chip - Information regarding per pdm + * @pwm_chip: information per pdm. + * @regmap: regmap of each pdm. + * @device: pdm device. + * @pdm_pwm_frames: structure for all frames of each pdm. + * @pdm_ahb_clk: pdm clock for enabling pdm block + * @pwm_core_clk: pwm clock for enabling each pwm. + * @mutex: mutex lock per frame. + * @pwm_core_rate: core rate of pwm_core__clk. + * @num_frames: number of frames in each pdm. + */ +struct pdm_pwm_chip { + struct pwm_chip pwm_chip; + struct regmap *regmap; + struct device *dev; + struct pdm_pwm_frames *frames; + struct clk *pdm_ahb_clk; + struct clk *pwm_core_clk; + struct pdm_pwm_priv_data *priv_data; + /* This lock to be used for Enable/Disable as it is per PWM channel */ + struct mutex lock; + unsigned long pwm_core_rate; + u32 num_frames; +}; + +static int __pdm_pwm_calc_pwm_frequency(struct pdm_pwm_chip *chip, + int period_ns, u32 hw_idx) +{ + unsigned long cyc_cfg, freq; + int ret; + + /* PWM client could set the period only once, due to HW limitation. */ + if (chip->frames[hw_idx].freq_set) + return 0; + + freq = PERIOD_TO_HZ(period_ns); + if (!freq) { + pr_err("Frequency cannot be Zero\n"); + return -EINVAL; + } + if (freq > (chip->pwm_core_rate >> 1) || + freq <= (chip->pwm_core_rate >> 16)) { + pr_debug("Freq %ld is not in range Max=%ld Min=%ld\n", freq, + (chip->pwm_core_rate >> 1), (chip->pwm_core_rate >> 16) + 1); + return -ERANGE; + } + cyc_cfg = DIV_ROUND_CLOSEST(chip->pwm_core_rate, freq) - 1; + + ret = regmap_update_bits(chip->regmap, + chip->frames[hw_idx].reg_offset + PWM_CYC_CFG, + GENMASK(15, 0), cyc_cfg); + if (ret) + return ret; + + chip->frames[hw_idx].current_freq = freq; + chip->frames[hw_idx].freq_set = true; + chip->frames[hw_idx].current_period_ns = period_ns; + + return 0; +} + +static void pdm_pwm_get_state(struct pwm_chip *pwm_chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct pdm_pwm_chip *chip = container_of(pwm_chip, + struct pdm_pwm_chip, pwm_chip); + + state->enabled = chip->frames[pwm->hwpwm].is_enabled; + state->period = chip->frames[pwm->hwpwm].current_period_ns; + state->duty_cycle = chip->frames[pwm->hwpwm].current_duty_ns; + +} + +static int pdm_pwm_config(struct pdm_pwm_chip *chip, u32 hw_idx, + int duty_ns, int period_ns) +{ + unsigned long ctl1; + int current_period = period_ns, ret; + u32 cyc_cfg; + + /* + * 1. Enable GCC_PDM_AHB_CBCR clock for PDM block Access + * 2. pwm_core_rate = clk_get_rate(pwm_core_clk); for now it is + * 19.2MHz. + * 3. min_freq = pwm_core_rate/2 ^ 16; + * 4. max_freq = pwm_core_rate/2; + * 5. calculate the frequency based on the period_ns and compare. + */ + ret = clk_prepare_enable(chip->pdm_ahb_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(chip->pwm_core_clk); + if (ret) + goto fail; + + mutex_lock(&chip->frames[hw_idx].frame_lock); + + ret = __pdm_pwm_calc_pwm_frequency(chip, current_period, hw_idx); + if (ret) + goto out; + + if (chip->frames[hw_idx].current_period_ns != period_ns) { + pr_err("Period cannot be updated, calculating dutycycle on old period\n"); + current_period = chip->frames[hw_idx].current_period_ns; + } + + ctl1 = DIV_ROUND_CLOSEST(chip->pwm_core_rate, + chip->frames[hw_idx].current_freq); + + ctl1 = DIV_ROUND_CLOSEST(ctl1 * (DIV_ROUND_CLOSEST((duty_ns * 100), + current_period)), 100); + + regmap_read(chip->regmap, chip->frames[hw_idx].reg_offset + + PWM_CYC_CFG, &cyc_cfg); + if ((ctl1 > cyc_cfg || ctl1 <= 0) && duty_ns != 0) { + pr_err("Duty cycle cannot be set at and beyond/below this limit\n"); + goto out; + } + + ret = regmap_update_bits(chip->regmap, chip->frames[hw_idx].reg_offset + + PWM_CTL2, GENMASK(15, 0), 0); + if (ret) + goto out; + + ret = regmap_update_bits(chip->regmap, chip->frames[hw_idx].reg_offset + + PWM_CTL1, GENMASK(15, 0), ctl1); + if (ret) + goto out; + + ret = regmap_update_bits(chip->regmap, chip->frames[hw_idx].reg_offset + + PWM_UPDATE, BIT(0), 1); + if (ret) + goto out; + + chip->frames[hw_idx].current_duty_ns = duty_ns; +out: + mutex_unlock(&chip->frames[hw_idx].frame_lock); + + clk_disable_unprepare(chip->pwm_core_clk); +fail: + clk_disable_unprepare(chip->pdm_ahb_clk); + + return ret; +} + +static void pdm_pwm_free(struct pwm_chip *pwm_chip, struct pwm_device *pwm) +{ + struct pdm_pwm_chip *chip = container_of(pwm_chip, + struct pdm_pwm_chip, pwm_chip); + u32 hw_idx = pwm->hwpwm; + + mutex_lock(&chip->lock); + + chip->frames[hw_idx].freq_set = false; + chip->frames[hw_idx].current_period_ns = 0; + chip->frames[hw_idx].current_duty_ns = 0; + + mutex_unlock(&chip->lock); +} + +static int pdm_pwm_enable(struct pdm_pwm_chip *chip, struct pwm_device *pwm) +{ + u32 ret, val; + u32 hw_idx = pwm->hwpwm; + + ret = clk_prepare_enable(chip->pdm_ahb_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(chip->pwm_core_clk); + if (ret) { + clk_disable_unprepare(chip->pdm_ahb_clk); + return ret; + } + + mutex_lock(&chip->lock); + + /* Check the channel in Chip channel and enable the BIT in PWM_TOP */ + pr_debug("%s: PWM device Label %s, HW index %u, PWM index %u\n", + __func__, pwm->label, hw_idx, pwm->pwm); + pr_debug("%s: PWM frame-index %d, frame-offset 0x%x\n", __func__, + chip->frames[hw_idx].frame_id, + chip->frames[hw_idx].reg_offset); + + val = BIT(chip->frames[hw_idx].frame_id); + ret = regmap_update_bits(chip->regmap, PWM_TOPCTL0, val, val); + + mutex_unlock(&chip->lock); + + if (ret) + return ret; + chip->frames[hw_idx].is_enabled = true; + + return 0; +} + +static int pdm_pwm_disable(struct pdm_pwm_chip *chip, struct pwm_device *pwm) +{ + u32 val, hw_idx = pwm->hwpwm; + int ret; + + mutex_lock(&chip->lock); + + /* Check the channel in the chip and disable the BIT in PWM_TOP */ + pr_debug("%s:PWM device Label %s\n", __func__, pwm->label); + + val = BIT(chip->frames[hw_idx].frame_id); + ret = regmap_update_bits(chip->regmap, PWM_TOPCTL0, val, 0); + + mutex_unlock(&chip->lock); + + if (ret) + return ret; + chip->frames[hw_idx].is_enabled = false; + + clk_disable_unprepare(chip->pwm_core_clk); + clk_disable_unprepare(chip->pdm_ahb_clk); + + return 0; +} + +static int pdm_pwm_apply(struct pwm_chip *pwm_chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct pdm_pwm_chip *chip = container_of(pwm_chip, + struct pdm_pwm_chip, pwm_chip); + struct pwm_state curr_state; + int ret; + + pwm_get_state(pwm, &curr_state); + + if (state->period < curr_state.period) + return -EINVAL; + + if (state->period != curr_state.period || + state->duty_cycle != curr_state.duty_cycle) { + ret = pdm_pwm_config(chip, pwm->hwpwm, state->duty_cycle, + state->period); + if (ret) { + pr_err("%s: Failed to update PWM configuration\n", + __func__); + return ret; + } + } + + if (state->enabled != curr_state.enabled) { + if (state->enabled) + return pdm_pwm_enable(chip, pwm); + + ret = pdm_pwm_disable(chip, pwm); + if (ret) + return ret; + } + + return 0; +} + +static const struct pwm_ops pdm_pwm_ops = { + .apply = pdm_pwm_apply, + .free = pdm_pwm_free, + .get_state = pdm_pwm_get_state, +}; + +static const struct regmap_config pwm_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + +static int pdm_pwm_parse_dt(struct platform_device *pdev, + struct pdm_pwm_chip *chip) +{ + struct resource *res; + struct device_node *np = pdev->dev.of_node; + struct device_node *frame_node; + void __iomem *base; + int count, ret; + + chip->pdm_ahb_clk = devm_clk_get(chip->dev, "pdm_ahb_clk"); + if (IS_ERR(chip->pdm_ahb_clk)) { + if (PTR_ERR(chip->pdm_ahb_clk) != -EPROBE_DEFER) + dev_err(chip->dev, "Unable to get ahb clock handle\n"); + return PTR_ERR(chip->pdm_ahb_clk); + } + + chip->pwm_core_clk = devm_clk_get(chip->dev, "pwm_core_clk"); + if (IS_ERR(chip->pwm_core_clk)) { + if (PTR_ERR(chip->pwm_core_clk) != -EPROBE_DEFER) + dev_err(chip->dev, "Unable to get core clock handle\n"); + return PTR_ERR(chip->pwm_core_clk); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(chip->dev, "Failed to get reg base resource\n"); + return -EINVAL; + } + + base = devm_ioremap(chip->dev, res->start, resource_size(res)); + if (!base) + return -ENOMEM; + + chip->regmap = devm_regmap_init_mmio(chip->dev, base, + &pwm_regmap_config); + if (!chip->regmap) { + dev_err(chip->dev, "Couldn't get regmap\n"); + return -EINVAL; + } + + if (!of_find_property(np, "assigned-clocks", NULL)) { + dev_err(chip->dev, "missing parent clock handle\n"); + return -ENODEV; + } + + if (!of_find_property(np, "assigned-clock-rates", NULL)) { + dev_err(chip->dev, "missing parent clock rate\n"); + return -ENODEV; + } + + chip->pwm_core_rate = clk_get_rate(chip->pwm_core_clk); + + chip->num_frames = of_get_child_count(np); + if (!chip->num_frames || + chip->num_frames > chip->priv_data->max_channels) { + dev_err(chip->dev, "PWM frames 0-%u are supported.\n", + chip->priv_data->max_channels); + return -EINVAL; + } + + chip->frames = devm_kcalloc(chip->dev, chip->num_frames, + sizeof(*chip->frames), GFP_KERNEL); + if (!chip->frames) + return -ENOMEM; + + count = 0; + for_each_available_child_of_node(np, frame_node) { + u32 n, off; + + if (of_property_read_u32(frame_node, "frame-index", &n)) { + pr_err(FW_BUG "Missing frame-index.\n"); + of_node_put(frame_node); + return -EINVAL; + } + chip->frames[count].frame_id = n; + + if (of_property_read_u32(frame_node, "frame-offset", &off)) { + pr_err(FW_BUG "Missing frame-offset.\n"); + of_node_put(frame_node); + return -EINVAL; + } + chip->frames[count].reg_offset = off; + + /* Holding a reference to the pdm chip for debug operations. */ + chip->frames[count].pwm_chip = chip; + + mutex_init(&chip->frames[count].frame_lock); + count++; + } + + ret = clk_prepare_enable(chip->pdm_ahb_clk); + if (ret) + return ret; + + ret = regmap_update_bits(chip->regmap, PWM_TOPCTL0, + GENMASK(chip->num_frames, 0), 0); + if (ret) + return ret; + + clk_disable_unprepare(chip->pdm_ahb_clk); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS + +static int duty_get(void *data, u64 *val) +{ + struct pdm_pwm_frames *frame = data; + + *val = DIV_ROUND_CLOSEST((frame->current_duty_ns * 100), + frame->current_period_ns); + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(pwm_duty_fops, duty_get, NULL, "%lld\n"); + +static int enabled(void *data, u64 *val) +{ + struct pdm_pwm_frames *frame = data; + struct pdm_pwm_chip *chip = frame->pwm_chip; + u32 temp, reg_offset; + + *val = 0; + reg_offset = chip->priv_data->status_reg_offsets[ENABLE_STATUS0]; + + if (chip->priv_data->status_reg_offsets[ENABLE_STATUS1] && + frame->frame_id > 10) + reg_offset = + chip->priv_data->status_reg_offsets[ENABLE_STATUS1]; + + regmap_read(chip->regmap, reg_offset, &temp); + if (BIT((frame->frame_id % 10) + BIT(0)) & temp) + *val = 1; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(pwm_enable_fops, enabled, NULL, "%lld\n"); + +static int print_hw_show(struct seq_file *m, void *unused) +{ + struct pdm_pwm_frames *frame = m->private; + u32 ctl1, ctl2, cyc_cfg, period_cnt; + + regmap_read(frame->pwm_chip->regmap, frame->reg_offset + PWM_CTL1, + &ctl1); + regmap_read(frame->pwm_chip->regmap, frame->reg_offset + PWM_CTL2, + &ctl2); + regmap_read(frame->pwm_chip->regmap, frame->reg_offset + PWM_CYC_CFG, + &cyc_cfg); + regmap_read(frame->pwm_chip->regmap, frame->reg_offset + PWM_PERIOD_CNT, + &period_cnt); + + seq_printf(m, "PWM_CTL1 : 0x%x\nPWM_CTL2 : 0x%x\n", ctl1, ctl2); + seq_printf(m, "PWM_CYC_CFG : 0x%x\nPWM_PERIOD_CNT : 0x%x\n", cyc_cfg, + period_cnt); + + return 0; +} + +static int print_hw_open(struct inode *inode, struct file *file) +{ + return single_open(file, print_hw_show, inode->i_private); +} + +static const struct file_operations pwm_list_regs_fops = { + .open = print_hw_open, + .read = seq_read, +}; + +static int freq_get(void *data, u64 *val) +{ + struct pdm_pwm_frames *frame = data; + + *val = PERIOD_TO_HZ(frame->current_period_ns); + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(pwm_freq_fops, freq_get, NULL, "%lld\n"); + +static int period_ns_get(void *data, u64 *val) +{ + struct pdm_pwm_frames *frame = data; + + *val = frame->current_period_ns; + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(pwm_period_ns_fops, period_ns_get, NULL, "%lld\n"); + +static int duty_ns_get(void *data, u64 *val) +{ + struct pdm_pwm_frames *frame = data; + + *val = frame->current_duty_ns; + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(pwm_duty_ns_fops, duty_ns_get, NULL, "%lld\n"); + +static void pdm_dwm_debug_init(struct pwm_chip *pwm_chip) +{ + struct pdm_pwm_chip *chip = container_of(pwm_chip, + struct pdm_pwm_chip, pwm_chip); + struct pwm_device *pwm; + static struct dentry *debugfs_base, *debugfs_frame_base; + int i, hw_idx; + char frame[FRAME_NUM_MAX_LEN]; + + debugfs_base = debugfs_create_dir(chip->dev->of_node->name, NULL); + if (IS_ERR_OR_NULL(debugfs_base)) { + pr_err("Failed in creating debugfs directory.\n"); + return; + } + for (i = 0; i < pwm_chip->npwm; i++) { + pwm = &pwm_chip->pwms[i]; + hw_idx = pwm->hwpwm; + + snprintf(frame, FRAME_NUM_MAX_LEN, "frame_%d", + chip->frames[hw_idx].frame_id); + debugfs_frame_base = debugfs_create_dir(frame, debugfs_base); + + debugfs_create_file("enabled", 0444, debugfs_frame_base, + &chip->frames[hw_idx], &pwm_enable_fops); + + debugfs_create_file("current_duty", 0444, debugfs_frame_base, + &chip->frames[hw_idx], &pwm_duty_fops); + + debugfs_create_file("pwm_print_regs", 0444, debugfs_frame_base, + &chip->frames[hw_idx], &pwm_list_regs_fops); + + debugfs_create_file("current_frequency_hz", 0444, + debugfs_frame_base, + &chip->frames[hw_idx], &pwm_freq_fops); + + debugfs_create_file("current_period_ns", 0444, + debugfs_frame_base, + &chip->frames[hw_idx], &pwm_period_ns_fops); + + debugfs_create_file("current_duty_cycle_ns", 0444, + debugfs_frame_base, + &chip->frames[hw_idx], &pwm_duty_ns_fops); + } +} + +#endif + +static int pdm_pwm_probe(struct platform_device *pdev) +{ + struct pdm_pwm_chip *chip; + int rc; + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->priv_data = (struct pdm_pwm_priv_data *) + of_device_get_match_data(&pdev->dev); + if (IS_ERR_OR_NULL(chip->priv_data)) + return -EINVAL; + + chip->dev = &pdev->dev; + mutex_init(&chip->lock); + rc = pdm_pwm_parse_dt(pdev, chip); + if (rc < 0) { + dev_err(chip->dev, + "Devicetree properties parsing failed, rc=%d\n", rc); + goto err_out; + } + + dev_set_drvdata(chip->dev, chip); + chip->pwm_chip.dev = chip->dev; + chip->pwm_chip.base = -1; + chip->pwm_chip.npwm = chip->num_frames; + chip->pwm_chip.ops = &pdm_pwm_ops; + + rc = pwmchip_add(&chip->pwm_chip); + if (rc < 0) { + dev_err(chip->dev, "Add pwmchip failed, rc=%d\n", rc); + goto err_out; + } + +#ifdef CONFIG_DEBUG_FS + pdm_dwm_debug_init(&chip->pwm_chip); +#endif + dev_info(chip->dev, "pwmchip driver success.\n"); + return rc; +err_out: + mutex_destroy(&chip->lock); + return rc; +} + +static int pdm_pwm_remove(struct platform_device *pdev) +{ + struct pdm_pwm_chip *chip = dev_get_drvdata(&pdev->dev); + int rc; + + rc = pwmchip_remove(&chip->pwm_chip); + if (rc < 0) + dev_err(chip->dev, "Remove pwmchip failed, rc=%d\n", rc); + + mutex_destroy(&chip->lock); + + dev_set_drvdata(chip->dev, NULL); + + return rc; +} + +static struct pdm_pwm_priv_data pdm_pwm_reg_offsets = { + .max_channels = 10, + .status_reg_offsets = (u16 [ENABLE_STATUS_REG_SIZE]) { + [ENABLE_STATUS0] = 0xc, + }, +}; + +static const struct of_device_id pdm_pwm_of_match[] = { + { .compatible = "qcom,pdm-pwm", .data = &pdm_pwm_reg_offsets }, + { }, +}; + +static struct platform_driver pdm_pwm_driver = { + .driver = { + .name = "pdm-pwm", + .of_match_table = pdm_pwm_of_match, + }, + .probe = pdm_pwm_probe, + .remove = pdm_pwm_remove, +}; +module_platform_driver(pdm_pwm_driver); + +MODULE_DESCRIPTION("QTI PDM PWM driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("pwm:pdm-pwm"); diff --git a/drivers/pwm/pwm-sti.c b/drivers/pwm/pwm-sti.c index ca67401f3575353cb35f6f0694017739246f6233..d75c7488fe2a3d01bbeacdc8811ab9d4322b021b 100644 --- a/drivers/pwm/pwm-sti.c +++ b/drivers/pwm/pwm-sti.c @@ -83,6 +83,7 @@ struct sti_pwm_compat_data { unsigned int cpt_num_devs; unsigned int max_pwm_cnt; unsigned int max_prescale; + struct sti_cpt_ddata *ddata; }; struct sti_pwm_chip { @@ -318,7 +319,7 @@ static int sti_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, { struct sti_pwm_chip *pc = to_sti_pwmchip(chip); struct sti_pwm_compat_data *cdata = pc->cdata; - struct sti_cpt_ddata *ddata = pwm_get_chip_data(pwm); + struct sti_cpt_ddata *ddata = &cdata->ddata[pwm->hwpwm]; struct device *dev = pc->dev; unsigned int effective_ticks; unsigned long long high, low; @@ -422,7 +423,7 @@ static irqreturn_t sti_pwm_interrupt(int irq, void *data) while (cpt_int_stat) { devicenum = ffs(cpt_int_stat) - 1; - ddata = pwm_get_chip_data(&pc->chip.pwms[devicenum]); + ddata = &pc->cdata->ddata[devicenum]; /* * Capture input: @@ -600,61 +601,55 @@ static int sti_pwm_probe(struct platform_device *pdev) if (ret) return ret; - if (!cdata->pwm_num_devs) - goto skip_pwm; - - pc->pwm_clk = of_clk_get_by_name(dev->of_node, "pwm"); - if (IS_ERR(pc->pwm_clk)) { - dev_err(dev, "failed to get PWM clock\n"); - return PTR_ERR(pc->pwm_clk); - } + if (cdata->pwm_num_devs) { + pc->pwm_clk = of_clk_get_by_name(dev->of_node, "pwm"); + if (IS_ERR(pc->pwm_clk)) { + dev_err(dev, "failed to get PWM clock\n"); + return PTR_ERR(pc->pwm_clk); + } - ret = clk_prepare(pc->pwm_clk); - if (ret) { - dev_err(dev, "failed to prepare clock\n"); - return ret; + ret = clk_prepare(pc->pwm_clk); + if (ret) { + dev_err(dev, "failed to prepare clock\n"); + return ret; + } } -skip_pwm: - if (!cdata->cpt_num_devs) - goto skip_cpt; + if (cdata->cpt_num_devs) { + pc->cpt_clk = of_clk_get_by_name(dev->of_node, "capture"); + if (IS_ERR(pc->cpt_clk)) { + dev_err(dev, "failed to get PWM capture clock\n"); + return PTR_ERR(pc->cpt_clk); + } - pc->cpt_clk = of_clk_get_by_name(dev->of_node, "capture"); - if (IS_ERR(pc->cpt_clk)) { - dev_err(dev, "failed to get PWM capture clock\n"); - return PTR_ERR(pc->cpt_clk); - } + ret = clk_prepare(pc->cpt_clk); + if (ret) { + dev_err(dev, "failed to prepare clock\n"); + return ret; + } - ret = clk_prepare(pc->cpt_clk); - if (ret) { - dev_err(dev, "failed to prepare clock\n"); - return ret; + cdata->ddata = devm_kzalloc(dev, cdata->cpt_num_devs * sizeof(*cdata->ddata), GFP_KERNEL); + if (!cdata->ddata) + return -ENOMEM; } -skip_cpt: pc->chip.dev = dev; pc->chip.ops = &sti_pwm_ops; pc->chip.base = -1; pc->chip.npwm = pc->cdata->pwm_num_devs; - ret = pwmchip_add(&pc->chip); - if (ret < 0) { - clk_unprepare(pc->pwm_clk); - clk_unprepare(pc->cpt_clk); - return ret; - } - for (i = 0; i < cdata->cpt_num_devs; i++) { - struct sti_cpt_ddata *ddata; - - ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); - if (!ddata) - return -ENOMEM; + struct sti_cpt_ddata *ddata = &cdata->ddata[i]; init_waitqueue_head(&ddata->wait); mutex_init(&ddata->lock); + } - pwm_set_chip_data(&pc->chip.pwms[i], ddata); + ret = pwmchip_add(&pc->chip); + if (ret < 0) { + clk_unprepare(pc->pwm_clk); + clk_unprepare(pc->cpt_clk); + return ret; } platform_set_drvdata(pdev, pc); diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c index e92a140074221e4b686307b872406a126631b3eb..7c8c2bb8f6a2841b1e74f2ea3837fbe24aaa3ece 100644 --- a/drivers/pwm/pwm-stm32-lp.c +++ b/drivers/pwm/pwm-stm32-lp.c @@ -126,7 +126,7 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, /* ensure CMP & ARR registers are properly written */ ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, - (val & STM32_LPTIM_CMPOK_ARROK), + (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK, 100, 1000); if (ret) { dev_err(priv->chip.dev, "ARR/CMP registers write issue\n"); diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 968b90cbcab98deee297ac944cba646192de8c1e..bc167451a977982e9529280ee52ee8564c735268 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -4546,7 +4546,7 @@ static void rdev_init_debugfs(struct regulator_dev *rdev) } rdev->debugfs = debugfs_create_dir(rname, debugfs_root); - if (!rdev->debugfs) { + if (IS_ERR(rdev->debugfs)) { rdev_warn(rdev, "Failed to create debugfs directory\n"); return; } @@ -5353,7 +5353,7 @@ static int __init regulator_init(void) ret = class_register(®ulator_class); debugfs_root = debugfs_create_dir("regulator", NULL); - if (!debugfs_root) + if (IS_ERR(debugfs_root)) pr_warn("regulator: Failed to create debugfs directory\n"); debugfs_create_file("supply_map", 0444, debugfs_root, NULL, diff --git a/drivers/regulator/da9052-regulator.c b/drivers/regulator/da9052-regulator.c index bd91c95f73e0e0caf4d7c984f3b3fbda24e43128..99713d0e9f0cfe0d375b74d384817d75b1fe77d8 100644 --- a/drivers/regulator/da9052-regulator.c +++ b/drivers/regulator/da9052-regulator.c @@ -421,7 +421,7 @@ static int da9052_regulator_probe(struct platform_device *pdev) config.dev = &pdev->dev; config.driver_data = regulator; config.regmap = da9052->regmap; - if (pdata && pdata->regulators) { + if (pdata) { config.init_data = pdata->regulators[cell->id]; } else { #ifdef CONFIG_OF diff --git a/drivers/regulator/da9055-regulator.c b/drivers/regulator/da9055-regulator.c index f40c3b8644ae524e2dbb76fb1c4a4af6d0d9fcd2..588c3d2445cf364c91cdcbb2c6376aaa095750ee 100644 --- a/drivers/regulator/da9055-regulator.c +++ b/drivers/regulator/da9055-regulator.c @@ -612,7 +612,7 @@ static int da9055_regulator_probe(struct platform_device *pdev) config.driver_data = regulator; config.regmap = da9055->regmap; - if (pdata && pdata->regulators) { + if (pdata) { config.init_data = pdata->regulators[pdev->id]; } else { ret = da9055_regulator_dt_init(pdev, regulator, &config, diff --git a/drivers/regulator/max77802-regulator.c b/drivers/regulator/max77802-regulator.c index c30cf5c9f2de33470273784e8491ed155c196b63..ef314de7c2c01bc9090b991c8fc0c8c426d6d323 100644 --- a/drivers/regulator/max77802-regulator.c +++ b/drivers/regulator/max77802-regulator.c @@ -97,9 +97,11 @@ static int max77802_set_suspend_disable(struct regulator_dev *rdev) { unsigned int val = MAX77802_OFF_PWRREQ; struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev); - int id = rdev_get_id(rdev); + unsigned int id = rdev_get_id(rdev); int shift = max77802_get_opmode_shift(id); + if (WARN_ON_ONCE(id >= ARRAY_SIZE(max77802->opmode))) + return -EINVAL; max77802->opmode[id] = val; return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, rdev->desc->enable_mask, val << shift); @@ -113,7 +115,7 @@ static int max77802_set_suspend_disable(struct regulator_dev *rdev) static int max77802_set_mode(struct regulator_dev *rdev, unsigned int mode) { struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev); - int id = rdev_get_id(rdev); + unsigned int id = rdev_get_id(rdev); unsigned int val; int shift = max77802_get_opmode_shift(id); @@ -130,6 +132,9 @@ static int max77802_set_mode(struct regulator_dev *rdev, unsigned int mode) return -EINVAL; } + if (WARN_ON_ONCE(id >= ARRAY_SIZE(max77802->opmode))) + return -EINVAL; + max77802->opmode[id] = val; return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, rdev->desc->enable_mask, val << shift); @@ -138,8 +143,10 @@ static int max77802_set_mode(struct regulator_dev *rdev, unsigned int mode) static unsigned max77802_get_mode(struct regulator_dev *rdev) { struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev); - int id = rdev_get_id(rdev); + unsigned int id = rdev_get_id(rdev); + if (WARN_ON_ONCE(id >= ARRAY_SIZE(max77802->opmode))) + return -EINVAL; return max77802_map_mode(max77802->opmode[id]); } @@ -163,10 +170,13 @@ static int max77802_set_suspend_mode(struct regulator_dev *rdev, unsigned int mode) { struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev); - int id = rdev_get_id(rdev); + unsigned int id = rdev_get_id(rdev); unsigned int val; int shift = max77802_get_opmode_shift(id); + if (WARN_ON_ONCE(id >= ARRAY_SIZE(max77802->opmode))) + return -EINVAL; + /* * If the regulator has been disabled for suspend * then is invalid to try setting a suspend mode. @@ -212,9 +222,11 @@ static int max77802_set_suspend_mode(struct regulator_dev *rdev, static int max77802_enable(struct regulator_dev *rdev) { struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev); - int id = rdev_get_id(rdev); + unsigned int id = rdev_get_id(rdev); int shift = max77802_get_opmode_shift(id); + if (WARN_ON_ONCE(id >= ARRAY_SIZE(max77802->opmode))) + return -EINVAL; if (max77802->opmode[id] == MAX77802_OFF_PWRREQ) max77802->opmode[id] = MAX77802_OPMODE_NORMAL; @@ -543,7 +555,7 @@ static int max77802_pmic_probe(struct platform_device *pdev) for (i = 0; i < MAX77802_REG_MAX; i++) { struct regulator_dev *rdev; - int id = regulators[i].id; + unsigned int id = regulators[i].id; int shift = max77802_get_opmode_shift(id); int ret; @@ -561,10 +573,12 @@ static int max77802_pmic_probe(struct platform_device *pdev) * the hardware reports OFF as the regulator operating mode. * Default to operating mode NORMAL in that case. */ - if (val == MAX77802_STATUS_OFF) - max77802->opmode[id] = MAX77802_OPMODE_NORMAL; - else - max77802->opmode[id] = val; + if (id < ARRAY_SIZE(max77802->opmode)) { + if (val == MAX77802_STATUS_OFF) + max77802->opmode[id] = MAX77802_OPMODE_NORMAL; + else + max77802->opmode[id] = val; + } rdev = devm_regulator_register(&pdev->dev, ®ulators[i], &config); diff --git a/drivers/regulator/rpm-smd-regulator.c b/drivers/regulator/rpm-smd-regulator.c index 7a1b961015e99c638f27611f38b249eef7f36123..c7078883e4001f421bf01dc426bb053b32ce5f7b 100644 --- a/drivers/regulator/rpm-smd-regulator.c +++ b/drivers/regulator/rpm-smd-regulator.c @@ -2042,7 +2042,6 @@ int __init rpm_smd_regulator_driver_init(void) return platform_driver_register(&rpm_vreg_resource_driver); } -EXPORT_SYMBOL(rpm_smd_regulator_driver_init); static void __exit rpm_vreg_exit(void) { diff --git a/drivers/regulator/s5m8767.c b/drivers/regulator/s5m8767.c index 4818df3f8ec91e91cf926181d18ef8f1f1a5f4e8..24c0c82b08a5d7d6e39cc5746ddb54c048931fef 100644 --- a/drivers/regulator/s5m8767.c +++ b/drivers/regulator/s5m8767.c @@ -922,10 +922,14 @@ static int s5m8767_pmic_probe(struct platform_device *pdev) for (i = 0; i < pdata->num_regulators; i++) { const struct sec_voltage_desc *desc; - int id = pdata->regulators[i].id; + unsigned int id = pdata->regulators[i].id; int enable_reg, enable_val; struct regulator_dev *rdev; + BUILD_BUG_ON(ARRAY_SIZE(regulators) != ARRAY_SIZE(reg_voltage_map)); + if (WARN_ON_ONCE(id >= ARRAY_SIZE(regulators))) + continue; + desc = reg_voltage_map[id]; if (desc) { regulators[id].n_voltages = diff --git a/drivers/rpmsg/qcom_glink_native.c b/drivers/rpmsg/qcom_glink_native.c index d6e2e85da84c02290f87763634effe8425e117d7..bdd2d5570579043abcac9407cac86c94a5e9ff90 100644 --- a/drivers/rpmsg/qcom_glink_native.c +++ b/drivers/rpmsg/qcom_glink_native.c @@ -281,6 +281,10 @@ static struct glink_channel *qcom_glink_alloc_channel(struct qcom_glink *glink, channel->glink = glink; channel->name = kstrdup(name, GFP_KERNEL); + if (!channel->name) { + kfree(channel); + return ERR_PTR(-ENOMEM); + } init_completion(&channel->open_req); init_completion(&channel->open_ack); @@ -1118,6 +1122,7 @@ static void qcom_glink_handle_intent(struct qcom_glink *glink, spin_unlock_irqrestore(&glink->idr_lock, flags); if (!channel) { dev_err(glink->dev, "intents for non-existing channel\n"); + qcom_glink_rx_advance(glink, ALIGN(msglen, 8)); return; } @@ -1713,6 +1718,7 @@ static void qcom_glink_rpdev_release(struct device *dev) { struct rpmsg_device *rpdev = to_rpmsg_device(dev); + kfree(rpdev->driver_override); kfree(rpdev); } diff --git a/drivers/rpmsg/rpmsg_core.c b/drivers/rpmsg/rpmsg_core.c index e95029130ca2ae456e7c2d49cd6a4c20189f3ef6..ed992684e05cfc56efc498f9614de60e8836d78c 100644 --- a/drivers/rpmsg/rpmsg_core.c +++ b/drivers/rpmsg/rpmsg_core.c @@ -369,7 +369,8 @@ field##_store(struct device *dev, struct device_attribute *attr, \ const char *buf, size_t sz) \ { \ struct rpmsg_device *rpdev = to_rpmsg_device(dev); \ - char *new, *old; \ + const char *old; \ + char *new; \ \ new = kstrndup(buf, sz, GFP_KERNEL); \ if (!new) \ @@ -565,24 +566,52 @@ static struct bus_type rpmsg_bus = { .remove = rpmsg_dev_remove, }; -int rpmsg_register_device(struct rpmsg_device *rpdev) +/* + * A helper for registering rpmsg device with driver override and name. + * Drivers should not be using it, but instead rpmsg_register_device(). + */ +int rpmsg_register_device_override(struct rpmsg_device *rpdev, + const char *driver_override) { struct device *dev = &rpdev->dev; int ret; + if (driver_override) + strcpy(rpdev->id.name, driver_override); + dev_set_name(&rpdev->dev, "%s.%s.%d.%d", dev_name(dev->parent), rpdev->id.name, rpdev->src, rpdev->dst); rpdev->dev.bus = &rpmsg_bus; - ret = device_register(&rpdev->dev); + device_initialize(dev); + if (driver_override) { + ret = driver_set_override(dev, &rpdev->driver_override, + driver_override, + strlen(driver_override)); + if (ret) { + dev_err(dev, "device_set_override failed: %d\n", ret); + put_device(dev); + return ret; + } + } + + ret = device_add(dev); if (ret) { - dev_err(dev, "device_register failed: %d\n", ret); + dev_err(dev, "device_add failed: %d\n", ret); + kfree(rpdev->driver_override); + rpdev->driver_override = NULL; put_device(&rpdev->dev); } return ret; } +EXPORT_SYMBOL(rpmsg_register_device_override); + +int rpmsg_register_device(struct rpmsg_device *rpdev) +{ + return rpmsg_register_device_override(rpdev, NULL); +} EXPORT_SYMBOL(rpmsg_register_device); /* diff --git a/drivers/rpmsg/rpmsg_internal.h b/drivers/rpmsg/rpmsg_internal.h index 195c3c55a0b1f30338a31e9965cf0ff41c1cd46c..a65da77fdd5dd032d3dfcee2c953307fd6250b66 100644 --- a/drivers/rpmsg/rpmsg_internal.h +++ b/drivers/rpmsg/rpmsg_internal.h @@ -88,10 +88,7 @@ struct device *rpmsg_find_device(struct device *parent, */ static inline int rpmsg_chrdev_register_device(struct rpmsg_device *rpdev) { - strcpy(rpdev->id.name, "rpmsg_chrdev"); - rpdev->driver_override = "rpmsg_chrdev"; - - return rpmsg_register_device(rpdev); + return rpmsg_register_device_override(rpdev, "rpmsg_ctrl"); } #endif diff --git a/drivers/rtc/rtc-ds1685.c b/drivers/rtc/rtc-ds1685.c index 6f39f683a98c6385f208473459b705bfe91e1f74..83926cd4753bd83e3b46b3018bc5bc5d0852d6b8 100644 --- a/drivers/rtc/rtc-ds1685.c +++ b/drivers/rtc/rtc-ds1685.c @@ -1630,7 +1630,7 @@ ds1685_rtc_poweroff(struct platform_device *pdev) unreachable(); } } -EXPORT_SYMBOL(ds1685_rtc_poweroff); +EXPORT_SYMBOL_GPL(ds1685_rtc_poweroff); /* ----------------------------------------------------------------------- */ diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c index 67bc979f14bb0e3918c18a75b2f7c8fecc7232e2..75fffca030bdede95023686238ad630339f8e9d7 100644 --- a/drivers/rtc/rtc-pm8xxx.c +++ b/drivers/rtc/rtc-pm8xxx.c @@ -229,7 +229,6 @@ static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) { int rc, i; u8 value[NUM_8_BIT_RTC_REGS]; - unsigned int ctrl_reg; unsigned long secs, irq_flags; struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; @@ -241,6 +240,11 @@ static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) secs >>= 8; } + rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl, + regs->alarm_en, 0); + if (rc) + return rc; + spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value, @@ -250,19 +254,11 @@ static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) goto rtc_rw_fail; } - rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); - if (rc) - goto rtc_rw_fail; - - if (alarm->enabled) - ctrl_reg |= regs->alarm_en; - else - ctrl_reg &= ~regs->alarm_en; - - rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); - if (rc) { - dev_err(dev, "Write to RTC alarm control register failed\n"); - goto rtc_rw_fail; + if (alarm->enabled) { + rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl, + regs->alarm_en, regs->alarm_en); + if (rc) + goto rtc_rw_fail; } dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n", diff --git a/drivers/rtc/rtc-st-lpc.c b/drivers/rtc/rtc-st-lpc.c index e66439b6247a4e8a7afe938d445713a98e270c32..e8a8ca3545f00a6d2d5f7ac9292189d3347049ad 100644 --- a/drivers/rtc/rtc-st-lpc.c +++ b/drivers/rtc/rtc-st-lpc.c @@ -239,7 +239,7 @@ static int st_rtc_probe(struct platform_device *pdev) enable_irq_wake(rtc->irq); disable_irq(rtc->irq); - rtc->clk = clk_get(&pdev->dev, NULL); + rtc->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(rtc->clk)) { dev_err(&pdev->dev, "Unable to request clock\n"); return PTR_ERR(rtc->clk); diff --git a/drivers/s390/block/dasd.c b/drivers/s390/block/dasd.c index 7beda20cf1221f307a9213e1275363af723cc221..c0eee7b00442ec14a2369ee3d566deefa2d9f520 100644 --- a/drivers/s390/block/dasd.c +++ b/drivers/s390/block/dasd.c @@ -2826,41 +2826,32 @@ static void _dasd_wake_block_flush_cb(struct dasd_ccw_req *cqr, void *data) * Requeue a request back to the block request queue * only works for block requests */ -static int _dasd_requeue_request(struct dasd_ccw_req *cqr) +static void _dasd_requeue_request(struct dasd_ccw_req *cqr) { - struct dasd_block *block = cqr->block; struct request *req; - if (!block) - return -EINVAL; /* * If the request is an ERP request there is nothing to requeue. * This will be done with the remaining original request. */ if (cqr->refers) - return 0; + return; spin_lock_irq(&cqr->dq->lock); req = (struct request *) cqr->callback_data; - blk_mq_requeue_request(req, false); + blk_mq_requeue_request(req, true); spin_unlock_irq(&cqr->dq->lock); - return 0; + return; } -/* - * Go through all request on the dasd_block request queue, cancel them - * on the respective dasd_device, and return them to the generic - * block layer. - */ -static int dasd_flush_block_queue(struct dasd_block *block) +static int _dasd_requests_to_flushqueue(struct dasd_block *block, + struct list_head *flush_queue) { struct dasd_ccw_req *cqr, *n; - int rc, i; - struct list_head flush_queue; unsigned long flags; + int rc, i; - INIT_LIST_HEAD(&flush_queue); - spin_lock_bh(&block->queue_lock); + spin_lock_irqsave(&block->queue_lock, flags); rc = 0; restart: list_for_each_entry_safe(cqr, n, &block->ccw_queue, blocklist) { @@ -2875,13 +2866,32 @@ static int dasd_flush_block_queue(struct dasd_block *block) * is returned from the dasd_device layer. */ cqr->callback = _dasd_wake_block_flush_cb; - for (i = 0; cqr != NULL; cqr = cqr->refers, i++) - list_move_tail(&cqr->blocklist, &flush_queue); + for (i = 0; cqr; cqr = cqr->refers, i++) + list_move_tail(&cqr->blocklist, flush_queue); if (i > 1) /* moved more than one request - need to restart */ goto restart; } - spin_unlock_bh(&block->queue_lock); + spin_unlock_irqrestore(&block->queue_lock, flags); + + return rc; +} + +/* + * Go through all request on the dasd_block request queue, cancel them + * on the respective dasd_device, and return them to the generic + * block layer. + */ +static int dasd_flush_block_queue(struct dasd_block *block) +{ + struct dasd_ccw_req *cqr, *n; + struct list_head flush_queue; + unsigned long flags; + int rc; + + INIT_LIST_HEAD(&flush_queue); + rc = _dasd_requests_to_flushqueue(block, &flush_queue); + /* Now call the callback function of flushed requests */ restart_cb: list_for_each_entry_safe(cqr, n, &flush_queue, blocklist) { @@ -3832,75 +3842,36 @@ EXPORT_SYMBOL_GPL(dasd_generic_verify_path); */ static int dasd_generic_requeue_all_requests(struct dasd_device *device) { + struct dasd_block *block = device->block; struct list_head requeue_queue; struct dasd_ccw_req *cqr, *n; - struct dasd_ccw_req *refers; int rc; - INIT_LIST_HEAD(&requeue_queue); - spin_lock_irq(get_ccwdev_lock(device->cdev)); - rc = 0; - list_for_each_entry_safe(cqr, n, &device->ccw_queue, devlist) { - /* Check status and move request to flush_queue */ - if (cqr->status == DASD_CQR_IN_IO) { - rc = device->discipline->term_IO(cqr); - if (rc) { - /* unable to terminate requeust */ - dev_err(&device->cdev->dev, - "Unable to terminate request %p " - "on suspend\n", cqr); - spin_unlock_irq(get_ccwdev_lock(device->cdev)); - dasd_put_device(device); - return rc; - } - } - list_move_tail(&cqr->devlist, &requeue_queue); - } - spin_unlock_irq(get_ccwdev_lock(device->cdev)); - - list_for_each_entry_safe(cqr, n, &requeue_queue, devlist) { - wait_event(dasd_flush_wq, - (cqr->status != DASD_CQR_CLEAR_PENDING)); + if (!block) + return 0; - /* - * requeue requests to blocklayer will only work - * for block device requests - */ - if (_dasd_requeue_request(cqr)) - continue; + INIT_LIST_HEAD(&requeue_queue); + rc = _dasd_requests_to_flushqueue(block, &requeue_queue); - /* remove requests from device and block queue */ - list_del_init(&cqr->devlist); - while (cqr->refers != NULL) { - refers = cqr->refers; - /* remove the request from the block queue */ - list_del(&cqr->blocklist); - /* free the finished erp request */ - dasd_free_erp_request(cqr, cqr->memdev); - cqr = refers; + /* Now call the callback function of flushed requests */ +restart_cb: + list_for_each_entry_safe(cqr, n, &requeue_queue, blocklist) { + wait_event(dasd_flush_wq, (cqr->status < DASD_CQR_QUEUED)); + /* Process finished ERP request. */ + if (cqr->refers) { + spin_lock_bh(&block->queue_lock); + __dasd_process_erp(block->base, cqr); + spin_unlock_bh(&block->queue_lock); + /* restart list_for_xx loop since dasd_process_erp + * might remove multiple elements + */ + goto restart_cb; } - - /* - * _dasd_requeue_request already checked for a valid - * blockdevice, no need to check again - * all erp requests (cqr->refers) have a cqr->block - * pointer copy from the original cqr - */ + _dasd_requeue_request(cqr); list_del_init(&cqr->blocklist); cqr->block->base->discipline->free_cp( cqr, (struct request *) cqr->callback_data); } - - /* - * if requests remain then they are internal request - * and go back to the device queue - */ - if (!list_empty(&requeue_queue)) { - /* move freeze_queue to start of the ccw_queue */ - spin_lock_irq(get_ccwdev_lock(device->cdev)); - list_splice_tail(&requeue_queue, &device->ccw_queue); - spin_unlock_irq(get_ccwdev_lock(device->cdev)); - } dasd_schedule_device_bh(device); return rc; } diff --git a/drivers/s390/block/dasd_3990_erp.c b/drivers/s390/block/dasd_3990_erp.c index ee73b0607e47c7c6fc108aa6c7ffa05924ee3d74..8598c792ded30ae2d9cec81542dec018f19dc6bf 100644 --- a/drivers/s390/block/dasd_3990_erp.c +++ b/drivers/s390/block/dasd_3990_erp.c @@ -2436,7 +2436,7 @@ static struct dasd_ccw_req *dasd_3990_erp_add_erp(struct dasd_ccw_req *cqr) erp->block = cqr->block; erp->magic = cqr->magic; erp->expires = cqr->expires; - erp->retries = 256; + erp->retries = device->default_retries; erp->buildclk = get_tod_clock(); erp->status = DASD_CQR_FILLED; diff --git a/drivers/s390/block/dasd_ioctl.c b/drivers/s390/block/dasd_ioctl.c index 2016e0ed5865726011742227de740053d492b337..9f3f483137598cbd73577fc7911254708048cd9e 100644 --- a/drivers/s390/block/dasd_ioctl.c +++ b/drivers/s390/block/dasd_ioctl.c @@ -137,6 +137,7 @@ static int dasd_ioctl_resume(struct dasd_block *block) spin_unlock_irqrestore(get_ccwdev_lock(base->cdev), flags); dasd_schedule_block_bh(block); + dasd_schedule_device_bh(base); return 0; } diff --git a/drivers/s390/cio/device.c b/drivers/s390/cio/device.c index c9bc9a6bd73b7a5b237fdaeb79afe27a3bbd8dc3..ee4338158ae2ea1580e38dd45d984343e3f6c247 100644 --- a/drivers/s390/cio/device.c +++ b/drivers/s390/cio/device.c @@ -1353,6 +1353,7 @@ void ccw_device_set_notoper(struct ccw_device *cdev) enum io_sch_action { IO_SCH_UNREG, IO_SCH_ORPH_UNREG, + IO_SCH_UNREG_CDEV, IO_SCH_ATTACH, IO_SCH_UNREG_ATTACH, IO_SCH_ORPH_ATTACH, @@ -1385,7 +1386,7 @@ static enum io_sch_action sch_get_action(struct subchannel *sch) } if ((sch->schib.pmcw.pam & sch->opm) == 0) { if (ccw_device_notify(cdev, CIO_NO_PATH) != NOTIFY_OK) - return IO_SCH_UNREG; + return IO_SCH_UNREG_CDEV; return IO_SCH_DISC; } if (device_is_disconnected(cdev)) @@ -1447,6 +1448,7 @@ static int io_subchannel_sch_event(struct subchannel *sch, int process) case IO_SCH_ORPH_ATTACH: ccw_device_set_disconnected(cdev); break; + case IO_SCH_UNREG_CDEV: case IO_SCH_UNREG_ATTACH: case IO_SCH_UNREG: if (!cdev) @@ -1480,6 +1482,7 @@ static int io_subchannel_sch_event(struct subchannel *sch, int process) if (rc) goto out; break; + case IO_SCH_UNREG_CDEV: case IO_SCH_UNREG_ATTACH: spin_lock_irqsave(sch->lock, flags); if (cdev->private->flags.resuming) { diff --git a/drivers/s390/cio/qdio.h b/drivers/s390/cio/qdio.h index ed60b8d4efe6859023f6f8dee786b0cda8f3efa5..f98dc3a8e3c7149f4bd6f4a300178f09807e9001 100644 --- a/drivers/s390/cio/qdio.h +++ b/drivers/s390/cio/qdio.h @@ -88,15 +88,15 @@ enum qdio_irq_states { static inline int do_sqbs(u64 token, unsigned char state, int queue, int *start, int *count) { - register unsigned long _ccq asm ("0") = *count; - register unsigned long _token asm ("1") = token; unsigned long _queuestart = ((unsigned long)queue << 32) | *start; + unsigned long _ccq = *count; asm volatile( - " .insn rsy,0xeb000000008A,%1,0,0(%2)" - : "+d" (_ccq), "+d" (_queuestart) - : "d" ((unsigned long)state), "d" (_token) - : "memory", "cc"); + " lgr 1,%[token]\n" + " .insn rsy,0xeb000000008a,%[qs],%[ccq],0(%[state])" + : [ccq] "+&d" (_ccq), [qs] "+&d" (_queuestart) + : [state] "a" ((unsigned long)state), [token] "d" (token) + : "memory", "cc", "1"); *count = _ccq & 0xff; *start = _queuestart & 0xff; @@ -106,16 +106,17 @@ static inline int do_sqbs(u64 token, unsigned char state, int queue, static inline int do_eqbs(u64 token, unsigned char *state, int queue, int *start, int *count, int ack) { - register unsigned long _ccq asm ("0") = *count; - register unsigned long _token asm ("1") = token; unsigned long _queuestart = ((unsigned long)queue << 32) | *start; unsigned long _state = (unsigned long)ack << 63; + unsigned long _ccq = *count; asm volatile( - " .insn rrf,0xB99c0000,%1,%2,0,0" - : "+d" (_ccq), "+d" (_queuestart), "+d" (_state) - : "d" (_token) - : "memory", "cc"); + " lgr 1,%[token]\n" + " .insn rrf,0xb99c0000,%[qs],%[state],%[ccq],0" + : [ccq] "+&d" (_ccq), [qs] "+&d" (_queuestart), + [state] "+&d" (_state) + : [token] "d" (token) + : "memory", "cc", "1"); *count = _ccq & 0xff; *start = _queuestart & 0xff; *state = _state & 0xff; diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index 4b7cc8d425b1c64c6b27e4f3308d4152362a0e21..6100cf4df54b6eef9ca1670a47292173d0ebe3cd 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -31,38 +31,41 @@ MODULE_DESCRIPTION("QDIO base support"); MODULE_LICENSE("GPL"); static inline int do_siga_sync(unsigned long schid, - unsigned int out_mask, unsigned int in_mask, + unsigned long out_mask, unsigned long in_mask, unsigned int fc) { - register unsigned long __fc asm ("0") = fc; - register unsigned long __schid asm ("1") = schid; - register unsigned long out asm ("2") = out_mask; - register unsigned long in asm ("3") = in_mask; int cc; asm volatile( + " lgr 0,%[fc]\n" + " lgr 1,%[schid]\n" + " lgr 2,%[out]\n" + " lgr 3,%[in]\n" " siga 0\n" - " ipm %0\n" - " srl %0,28\n" - : "=d" (cc) - : "d" (__fc), "d" (__schid), "d" (out), "d" (in) : "cc"); + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "=&d" (cc) + : [fc] "d" (fc), [schid] "d" (schid), + [out] "d" (out_mask), [in] "d" (in_mask) + : "cc", "0", "1", "2", "3"); return cc; } -static inline int do_siga_input(unsigned long schid, unsigned int mask, - unsigned int fc) +static inline int do_siga_input(unsigned long schid, unsigned long mask, + unsigned long fc) { - register unsigned long __fc asm ("0") = fc; - register unsigned long __schid asm ("1") = schid; - register unsigned long __mask asm ("2") = mask; int cc; asm volatile( + " lgr 0,%[fc]\n" + " lgr 1,%[schid]\n" + " lgr 2,%[mask]\n" " siga 0\n" - " ipm %0\n" - " srl %0,28\n" - : "=d" (cc) - : "d" (__fc), "d" (__schid), "d" (__mask) : "cc"); + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "=&d" (cc) + : [fc] "d" (fc), [schid] "d" (schid), [mask] "d" (mask) + : "cc", "0", "1", "2"); return cc; } @@ -78,23 +81,24 @@ static inline int do_siga_input(unsigned long schid, unsigned int mask, * Note: For IQDC unicast queues only the highest priority queue is processed. */ static inline int do_siga_output(unsigned long schid, unsigned long mask, - unsigned int *bb, unsigned int fc, + unsigned int *bb, unsigned long fc, unsigned long aob) { - register unsigned long __fc asm("0") = fc; - register unsigned long __schid asm("1") = schid; - register unsigned long __mask asm("2") = mask; - register unsigned long __aob asm("3") = aob; int cc; asm volatile( + " lgr 0,%[fc]\n" + " lgr 1,%[schid]\n" + " lgr 2,%[mask]\n" + " lgr 3,%[aob]\n" " siga 0\n" - " ipm %0\n" - " srl %0,28\n" - : "=d" (cc), "+d" (__fc), "+d" (__aob) - : "d" (__schid), "d" (__mask) - : "cc"); - *bb = __fc >> 31; + " lgr %[fc],0\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "=&d" (cc), [fc] "+&d" (fc) + : [schid] "d" (schid), [mask] "d" (mask), [aob] "d" (aob) + : "cc", "0", "1", "2", "3"); + *bb = fc >> 31; return cc; } diff --git a/drivers/s390/scsi/zfcp_aux.c b/drivers/s390/scsi/zfcp_aux.c index d1b531fe9ada1d72403a8181ccaae2270b866a07..e5697ae9b4a3fc2d01200f59c4117ba03b0537e3 100644 --- a/drivers/s390/scsi/zfcp_aux.c +++ b/drivers/s390/scsi/zfcp_aux.c @@ -493,12 +493,12 @@ struct zfcp_port *zfcp_port_enqueue(struct zfcp_adapter *adapter, u64 wwpn, if (port) { put_device(&port->dev); retval = -EEXIST; - goto err_out; + goto err_put; } port = kzalloc(sizeof(struct zfcp_port), GFP_KERNEL); if (!port) - goto err_out; + goto err_put; rwlock_init(&port->unit_list_lock); INIT_LIST_HEAD(&port->unit_list); @@ -521,7 +521,7 @@ struct zfcp_port *zfcp_port_enqueue(struct zfcp_adapter *adapter, u64 wwpn, if (dev_set_name(&port->dev, "0x%016llx", (unsigned long long)wwpn)) { kfree(port); - goto err_out; + goto err_put; } retval = -EINVAL; @@ -538,8 +538,9 @@ struct zfcp_port *zfcp_port_enqueue(struct zfcp_adapter *adapter, u64 wwpn, return port; -err_out: +err_put: zfcp_ccw_adapter_put(adapter); +err_out: return ERR_PTR(retval); } diff --git a/drivers/s390/scsi/zfcp_fc.c b/drivers/s390/scsi/zfcp_fc.c index dc87a6b84d73978da48781cc2951f18e67db0d5e..72e9e2945ee09499243ed552455eb819e4271041 100644 --- a/drivers/s390/scsi/zfcp_fc.c +++ b/drivers/s390/scsi/zfcp_fc.c @@ -534,8 +534,7 @@ static void zfcp_fc_adisc_handler(void *data) /* re-init to undo drop from zfcp_fc_adisc() */ port->d_id = ntoh24(adisc_resp->adisc_port_id); - /* port is good, unblock rport without going through erp */ - zfcp_scsi_schedule_rport_register(port); + /* port is still good, nothing to do */ out: atomic_andnot(ZFCP_STATUS_PORT_LINK_TEST, &port->status); put_device(&port->dev); @@ -595,9 +594,6 @@ void zfcp_fc_link_test_work(struct work_struct *work) int retval; set_worker_desc("zadisc%16llx", port->wwpn); /* < WORKER_DESC_LEN=24 */ - get_device(&port->dev); - port->rport_task = RPORT_DEL; - zfcp_scsi_rport_work(&port->rport_work); /* only issue one test command at one time per port */ if (atomic_read(&port->status) & ZFCP_STATUS_PORT_LINK_TEST) diff --git a/drivers/scsi/3w-xxxx.c b/drivers/scsi/3w-xxxx.c index 471366945bd4fc8b3d92ede8247f8a4d5706d508..8a61e832607eb2285d083359e4fe4eb77b1781e5 100644 --- a/drivers/scsi/3w-xxxx.c +++ b/drivers/scsi/3w-xxxx.c @@ -2303,8 +2303,10 @@ static int tw_probe(struct pci_dev *pdev, const struct pci_device_id *dev_id) TW_DISABLE_INTERRUPTS(tw_dev); /* Initialize the card */ - if (tw_reset_sequence(tw_dev)) + if (tw_reset_sequence(tw_dev)) { + retval = -EINVAL; goto out_release_mem_region; + } /* Set host specific parameters */ host->max_id = TW_MAX_UNITS; diff --git a/drivers/scsi/53c700.c b/drivers/scsi/53c700.c index ac79f2088b3167d1024de7205f6bcff6c96e636e..480fc9bb4c9034b6a6327eb87e0b368fd3dbe684 100644 --- a/drivers/scsi/53c700.c +++ b/drivers/scsi/53c700.c @@ -1594,7 +1594,7 @@ NCR_700_intr(int irq, void *dev_id) printk("scsi%d (%d:%d) PHASE MISMATCH IN SEND MESSAGE %d remain, return %p[%04x], phase %s\n", host->host_no, pun, lun, count, (void *)temp, temp - hostdata->pScript, sbcl_to_string(NCR_700_readb(host, SBCL_REG))); #endif resume_offset = hostdata->pScript + Ent_SendMessagePhaseMismatch; - } else if(dsp >= to32bit(&slot->pSG[0].ins) && + } else if (slot && dsp >= to32bit(&slot->pSG[0].ins) && dsp <= to32bit(&slot->pSG[NCR_700_SG_SEGMENTS].ins)) { int data_transfer = NCR_700_readl(host, DBC_REG) & 0xffffff; int SGcount = (dsp - to32bit(&slot->pSG[0].ins))/sizeof(struct NCR_700_SG_List); diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index b5431d351f84635b1a492a9099c6af9fcce5744e..098b835e1bb6d69d4711158fe48bcfabdc7ff9f6 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -473,7 +473,7 @@ config SCSI_MVUMI config SCSI_DPT_I2O tristate "Adaptec I2O RAID support " - depends on SCSI && PCI && VIRT_TO_BUS + depends on SCSI && PCI help This driver supports all of Adaptec's I2O based RAID controllers as well as the DPT SmartRaid V cards. This is an Adaptec maintained diff --git a/drivers/scsi/aic94xx/aic94xx_task.c b/drivers/scsi/aic94xx/aic94xx_task.c index cdd4ab683be980d4af077129434137b9910c7bbd..4de4bbca1f9257cef1dc374056af9af50d1921ea 100644 --- a/drivers/scsi/aic94xx/aic94xx_task.c +++ b/drivers/scsi/aic94xx/aic94xx_task.c @@ -68,6 +68,9 @@ static int asd_map_scatterlist(struct sas_task *task, dma_addr_t dma = pci_map_single(asd_ha->pcidev, p, task->total_xfer_len, task->data_dir); + if (dma_mapping_error(&asd_ha->pcidev->dev, dma)) + return -ENOMEM; + sg_arr[0].bus_addr = cpu_to_le64((u64)dma); sg_arr[0].size = cpu_to_le32(task->total_xfer_len); sg_arr[0].flags |= ASD_SG_EL_LIST_EOL; diff --git a/drivers/scsi/be2iscsi/be_iscsi.c b/drivers/scsi/be2iscsi/be_iscsi.c index c8f0a2144b4439cdce74e413ed40e870b89bdb27..818a690771e05ac6680ba938770b8322fd1e49c7 100644 --- a/drivers/scsi/be2iscsi/be_iscsi.c +++ b/drivers/scsi/be2iscsi/be_iscsi.c @@ -445,6 +445,10 @@ int beiscsi_iface_set_param(struct Scsi_Host *shost, } nla_for_each_attr(attrib, data, dt_len, rm_len) { + /* ignore nla_type as it is never used */ + if (nla_len(attrib) < sizeof(*iface_param)) + return -EINVAL; + iface_param = nla_data(attrib); if (iface_param->param_type != ISCSI_NET_PARAM) diff --git a/drivers/scsi/dc395x.c b/drivers/scsi/dc395x.c index 8b5a07503d5f000bb986bec8f5748d4050c8ad6c..fdfa88e0d1d070c02661e33e9842affc19d772bb 100644 --- a/drivers/scsi/dc395x.c +++ b/drivers/scsi/dc395x.c @@ -4275,7 +4275,7 @@ static int adapter_sg_tables_alloc(struct AdapterCtlBlk *acb) const unsigned srbs_per_page = PAGE_SIZE/SEGMENTX_LEN; int srb_idx = 0; unsigned i = 0; - struct SGentry *uninitialized_var(ptr); + struct SGentry *ptr; for (i = 0; i < DC395x_MAX_SRB_CNT; i++) acb->srb_array[i].segment_x = NULL; diff --git a/drivers/scsi/device_handler/scsi_dh_alua.c b/drivers/scsi/device_handler/scsi_dh_alua.c index 4cf7c3348bffe10b538b199d26f9c8bcaee731ee..9be913c19a6e0174b5e8a3b50b1c7e1775d3af79 100644 --- a/drivers/scsi/device_handler/scsi_dh_alua.c +++ b/drivers/scsi/device_handler/scsi_dh_alua.c @@ -1050,10 +1050,12 @@ static int alua_activate(struct scsi_device *sdev, rcu_read_unlock(); mutex_unlock(&h->init_mutex); - if (alua_rtpg_queue(pg, sdev, qdata, true)) + if (alua_rtpg_queue(pg, sdev, qdata, true)) { fn = NULL; - else + } else { + kfree(qdata); err = SCSI_DH_DEV_OFFLINED; + } kref_put(&pg->kref, release_port_group); out: if (fn) diff --git a/drivers/scsi/dpt_i2o.c b/drivers/scsi/dpt_i2o.c index 37de8fb186d7b61dbbd7db97a18ca6bcfa26f977..3f8d1c17e93810f6ea3946e98cac89001fde23b4 100644 --- a/drivers/scsi/dpt_i2o.c +++ b/drivers/scsi/dpt_i2o.c @@ -59,7 +59,7 @@ MODULE_DESCRIPTION("Adaptec I2O RAID Driver"); #include /* for boot_cpu_data */ #include -#include /* for virt_to_bus, etc. */ +#include #include #include @@ -628,51 +628,6 @@ static struct scsi_cmnd * return NULL; } -/* - * Turn a pointer to ioctl reply data into an u32 'context' - */ -static u32 adpt_ioctl_to_context(adpt_hba * pHba, void *reply) -{ -#if BITS_PER_LONG == 32 - return (u32)(unsigned long)reply; -#else - ulong flags = 0; - u32 nr, i; - - spin_lock_irqsave(pHba->host->host_lock, flags); - nr = ARRAY_SIZE(pHba->ioctl_reply_context); - for (i = 0; i < nr; i++) { - if (pHba->ioctl_reply_context[i] == NULL) { - pHba->ioctl_reply_context[i] = reply; - break; - } - } - spin_unlock_irqrestore(pHba->host->host_lock, flags); - if (i >= nr) { - printk(KERN_WARNING"%s: Too many outstanding " - "ioctl commands\n", pHba->name); - return (u32)-1; - } - - return i; -#endif -} - -/* - * Go from an u32 'context' to a pointer to ioctl reply data. - */ -static void *adpt_ioctl_from_context(adpt_hba *pHba, u32 context) -{ -#if BITS_PER_LONG == 32 - return (void *)(unsigned long)context; -#else - void *p = pHba->ioctl_reply_context[context]; - pHba->ioctl_reply_context[context] = NULL; - - return p; -#endif -} - /*=========================================================================== * Error Handling routines *=========================================================================== @@ -1697,208 +1652,6 @@ static int adpt_close(struct inode *inode, struct file *file) return 0; } - -static int adpt_i2o_passthru(adpt_hba* pHba, u32 __user *arg) -{ - u32 msg[MAX_MESSAGE_SIZE]; - u32* reply = NULL; - u32 size = 0; - u32 reply_size = 0; - u32 __user *user_msg = arg; - u32 __user * user_reply = NULL; - void **sg_list = NULL; - u32 sg_offset = 0; - u32 sg_count = 0; - int sg_index = 0; - u32 i = 0; - u32 rcode = 0; - void *p = NULL; - dma_addr_t addr; - ulong flags = 0; - - memset(&msg, 0, MAX_MESSAGE_SIZE*4); - // get user msg size in u32s - if(get_user(size, &user_msg[0])){ - return -EFAULT; - } - size = size>>16; - - user_reply = &user_msg[size]; - if(size > MAX_MESSAGE_SIZE){ - return -EFAULT; - } - size *= 4; // Convert to bytes - - /* Copy in the user's I2O command */ - if(copy_from_user(msg, user_msg, size)) { - return -EFAULT; - } - get_user(reply_size, &user_reply[0]); - reply_size = reply_size>>16; - if(reply_size > REPLY_FRAME_SIZE){ - reply_size = REPLY_FRAME_SIZE; - } - reply_size *= 4; - reply = kzalloc(REPLY_FRAME_SIZE*4, GFP_KERNEL); - if(reply == NULL) { - printk(KERN_WARNING"%s: Could not allocate reply buffer\n",pHba->name); - return -ENOMEM; - } - sg_offset = (msg[0]>>4)&0xf; - msg[2] = 0x40000000; // IOCTL context - msg[3] = adpt_ioctl_to_context(pHba, reply); - if (msg[3] == (u32)-1) { - rcode = -EBUSY; - goto free; - } - - sg_list = kcalloc(pHba->sg_tablesize, sizeof(*sg_list), GFP_KERNEL); - if (!sg_list) { - rcode = -ENOMEM; - goto free; - } - if(sg_offset) { - // TODO add 64 bit API - struct sg_simple_element *sg = (struct sg_simple_element*) (msg+sg_offset); - sg_count = (size - sg_offset*4) / sizeof(struct sg_simple_element); - if (sg_count > pHba->sg_tablesize){ - printk(KERN_DEBUG"%s:IOCTL SG List too large (%u)\n", pHba->name,sg_count); - rcode = -EINVAL; - goto free; - } - - for(i = 0; i < sg_count; i++) { - int sg_size; - - if (!(sg[i].flag_count & 0x10000000 /*I2O_SGL_FLAGS_SIMPLE_ADDRESS_ELEMENT*/)) { - printk(KERN_DEBUG"%s:Bad SG element %d - not simple (%x)\n",pHba->name,i, sg[i].flag_count); - rcode = -EINVAL; - goto cleanup; - } - sg_size = sg[i].flag_count & 0xffffff; - /* Allocate memory for the transfer */ - p = dma_alloc_coherent(&pHba->pDev->dev, sg_size, &addr, GFP_KERNEL); - if(!p) { - printk(KERN_DEBUG"%s: Could not allocate SG buffer - size = %d buffer number %d of %d\n", - pHba->name,sg_size,i,sg_count); - rcode = -ENOMEM; - goto cleanup; - } - sg_list[sg_index++] = p; // sglist indexed with input frame, not our internal frame. - /* Copy in the user's SG buffer if necessary */ - if(sg[i].flag_count & 0x04000000 /*I2O_SGL_FLAGS_DIR*/) { - // sg_simple_element API is 32 bit - if (copy_from_user(p,(void __user *)(ulong)sg[i].addr_bus, sg_size)) { - printk(KERN_DEBUG"%s: Could not copy SG buf %d FROM user\n",pHba->name,i); - rcode = -EFAULT; - goto cleanup; - } - } - /* sg_simple_element API is 32 bit, but addr < 4GB */ - sg[i].addr_bus = addr; - } - } - - do { - /* - * Stop any new commands from enterring the - * controller while processing the ioctl - */ - if (pHba->host) { - scsi_block_requests(pHba->host); - spin_lock_irqsave(pHba->host->host_lock, flags); - } - rcode = adpt_i2o_post_wait(pHba, msg, size, FOREVER); - if (rcode != 0) - printk("adpt_i2o_passthru: post wait failed %d %p\n", - rcode, reply); - if (pHba->host) { - spin_unlock_irqrestore(pHba->host->host_lock, flags); - scsi_unblock_requests(pHba->host); - } - } while (rcode == -ETIMEDOUT); - - if(rcode){ - goto cleanup; - } - - if(sg_offset) { - /* Copy back the Scatter Gather buffers back to user space */ - u32 j; - // TODO add 64 bit API - struct sg_simple_element* sg; - int sg_size; - - // re-acquire the original message to handle correctly the sg copy operation - memset(&msg, 0, MAX_MESSAGE_SIZE*4); - // get user msg size in u32s - if(get_user(size, &user_msg[0])){ - rcode = -EFAULT; - goto cleanup; - } - size = size>>16; - size *= 4; - if (size > MAX_MESSAGE_SIZE) { - rcode = -EINVAL; - goto cleanup; - } - /* Copy in the user's I2O command */ - if (copy_from_user (msg, user_msg, size)) { - rcode = -EFAULT; - goto cleanup; - } - sg_count = (size - sg_offset*4) / sizeof(struct sg_simple_element); - - // TODO add 64 bit API - sg = (struct sg_simple_element*)(msg + sg_offset); - for (j = 0; j < sg_count; j++) { - /* Copy out the SG list to user's buffer if necessary */ - if(! (sg[j].flag_count & 0x4000000 /*I2O_SGL_FLAGS_DIR*/)) { - sg_size = sg[j].flag_count & 0xffffff; - // sg_simple_element API is 32 bit - if (copy_to_user((void __user *)(ulong)sg[j].addr_bus,sg_list[j], sg_size)) { - printk(KERN_WARNING"%s: Could not copy %p TO user %x\n",pHba->name, sg_list[j], sg[j].addr_bus); - rcode = -EFAULT; - goto cleanup; - } - } - } - } - - /* Copy back the reply to user space */ - if (reply_size) { - // we wrote our own values for context - now restore the user supplied ones - if(copy_from_user(reply+2, user_msg+2, sizeof(u32)*2)) { - printk(KERN_WARNING"%s: Could not copy message context FROM user\n",pHba->name); - rcode = -EFAULT; - } - if(copy_to_user(user_reply, reply, reply_size)) { - printk(KERN_WARNING"%s: Could not copy reply TO user\n",pHba->name); - rcode = -EFAULT; - } - } - - -cleanup: - if (rcode != -ETIME && rcode != -EINTR) { - struct sg_simple_element *sg = - (struct sg_simple_element*) (msg +sg_offset); - while(sg_index) { - if(sg_list[--sg_index]) { - dma_free_coherent(&pHba->pDev->dev, - sg[sg_index].flag_count & 0xffffff, - sg_list[sg_index], - sg[sg_index].addr_bus); - } - } - } - -free: - kfree(sg_list); - kfree(reply); - return rcode; -} - #if defined __ia64__ static void adpt_ia64_info(sysInfo_S* si) { @@ -2025,8 +1778,6 @@ static int adpt_ioctl(struct inode *inode, struct file *file, uint cmd, ulong ar return -EFAULT; } break; - case I2OUSRCMD: - return adpt_i2o_passthru(pHba, argp); case DPT_CTRLINFO:{ drvrHBAinfo_S HbaInfo; @@ -2163,7 +1914,7 @@ static irqreturn_t adpt_isr(int irq, void *dev_id) } else { /* Ick, we should *never* be here */ printk(KERN_ERR "dpti: reply frame not from pool\n"); - reply = (u8 *)bus_to_virt(m); + continue; } if (readl(reply) & MSG_FAIL) { @@ -2183,13 +1934,6 @@ static irqreturn_t adpt_isr(int irq, void *dev_id) adpt_send_nop(pHba, old_m); } context = readl(reply+8); - if(context & 0x40000000){ // IOCTL - void *p = adpt_ioctl_from_context(pHba, readl(reply+12)); - if( p != NULL) { - memcpy_fromio(p, reply, REPLY_FRAME_SIZE * 4); - } - // All IOCTLs will also be post wait - } if(context & 0x80000000){ // Post wait message status = readl(reply+16); if(status >> 24){ @@ -2197,12 +1941,9 @@ static irqreturn_t adpt_isr(int irq, void *dev_id) } else { status = I2O_POST_WAIT_OK; } - if(!(context & 0x40000000)) { - cmd = adpt_cmd_from_context(pHba, - readl(reply+12)); - if(cmd != NULL) { - printk(KERN_WARNING"%s: Apparent SCSI cmd in Post Wait Context - cmd=%p context=%x\n", pHba->name, cmd, context); - } + cmd = adpt_cmd_from_context(pHba, readl(reply+12)); + if(cmd != NULL) { + printk(KERN_WARNING"%s: Apparent SCSI cmd in Post Wait Context - cmd=%p context=%x\n", pHba->name, cmd, context); } adpt_i2o_post_wait_complete(context, status); } else { // SCSI message diff --git a/drivers/scsi/dpti.h b/drivers/scsi/dpti.h index dfc8d2eaa09e4b2ac3f178aeb634bc91884856af..9a313883788a2b328749fe43a61fdfff98d94d64 100644 --- a/drivers/scsi/dpti.h +++ b/drivers/scsi/dpti.h @@ -251,7 +251,6 @@ typedef struct _adpt_hba { void __iomem *FwDebugBLEDflag_P;// Virtual Addr Of FW Debug BLED void __iomem *FwDebugBLEDvalue_P;// Virtual Addr Of FW Debug BLED u32 FwDebugFlags; - u32 *ioctl_reply_context[4]; } adpt_hba; struct sg_simple_element { diff --git a/drivers/scsi/fcoe/fcoe_ctlr.c b/drivers/scsi/fcoe/fcoe_ctlr.c index 1e087a206f48ed3c85eb1b76e9569128a0890f86..c49986eba47b6835c8275ff6d3fcbcc1221e688b 100644 --- a/drivers/scsi/fcoe/fcoe_ctlr.c +++ b/drivers/scsi/fcoe/fcoe_ctlr.c @@ -330,16 +330,17 @@ static void fcoe_ctlr_announce(struct fcoe_ctlr *fip) { struct fcoe_fcf *sel; struct fcoe_fcf *fcf; + unsigned long flags; mutex_lock(&fip->ctlr_mutex); - spin_lock_bh(&fip->ctlr_lock); + spin_lock_irqsave(&fip->ctlr_lock, flags); kfree_skb(fip->flogi_req); fip->flogi_req = NULL; list_for_each_entry(fcf, &fip->fcfs, list) fcf->flogi_sent = 0; - spin_unlock_bh(&fip->ctlr_lock); + spin_unlock_irqrestore(&fip->ctlr_lock, flags); sel = fip->sel_fcf; if (sel && ether_addr_equal(sel->fcf_mac, fip->dest_addr)) @@ -709,6 +710,7 @@ int fcoe_ctlr_els_send(struct fcoe_ctlr *fip, struct fc_lport *lport, { struct fc_frame *fp; struct fc_frame_header *fh; + unsigned long flags; u16 old_xid; u8 op; u8 mac[ETH_ALEN]; @@ -742,11 +744,11 @@ int fcoe_ctlr_els_send(struct fcoe_ctlr *fip, struct fc_lport *lport, op = FIP_DT_FLOGI; if (fip->mode == FIP_MODE_VN2VN) break; - spin_lock_bh(&fip->ctlr_lock); + spin_lock_irqsave(&fip->ctlr_lock, flags); kfree_skb(fip->flogi_req); fip->flogi_req = skb; fip->flogi_req_send = 1; - spin_unlock_bh(&fip->ctlr_lock); + spin_unlock_irqrestore(&fip->ctlr_lock, flags); schedule_work(&fip->timer_work); return -EINPROGRESS; case ELS_FDISC: @@ -1723,10 +1725,11 @@ static int fcoe_ctlr_flogi_send_locked(struct fcoe_ctlr *fip) static int fcoe_ctlr_flogi_retry(struct fcoe_ctlr *fip) { struct fcoe_fcf *fcf; + unsigned long flags; int error; mutex_lock(&fip->ctlr_mutex); - spin_lock_bh(&fip->ctlr_lock); + spin_lock_irqsave(&fip->ctlr_lock, flags); LIBFCOE_FIP_DBG(fip, "re-sending FLOGI - reselect\n"); fcf = fcoe_ctlr_select(fip); if (!fcf || fcf->flogi_sent) { @@ -1737,7 +1740,7 @@ static int fcoe_ctlr_flogi_retry(struct fcoe_ctlr *fip) fcoe_ctlr_solicit(fip, NULL); error = fcoe_ctlr_flogi_send_locked(fip); } - spin_unlock_bh(&fip->ctlr_lock); + spin_unlock_irqrestore(&fip->ctlr_lock, flags); mutex_unlock(&fip->ctlr_mutex); return error; } @@ -1754,8 +1757,9 @@ static int fcoe_ctlr_flogi_retry(struct fcoe_ctlr *fip) static void fcoe_ctlr_flogi_send(struct fcoe_ctlr *fip) { struct fcoe_fcf *fcf; + unsigned long flags; - spin_lock_bh(&fip->ctlr_lock); + spin_lock_irqsave(&fip->ctlr_lock, flags); fcf = fip->sel_fcf; if (!fcf || !fip->flogi_req_send) goto unlock; @@ -1782,7 +1786,7 @@ static void fcoe_ctlr_flogi_send(struct fcoe_ctlr *fip) } else /* XXX */ LIBFCOE_FIP_DBG(fip, "No FCF selected - defer send\n"); unlock: - spin_unlock_bh(&fip->ctlr_lock); + spin_unlock_irqrestore(&fip->ctlr_lock, flags); } /** diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c index b3d6ea92b4f7c066c9940ce9c8c6513d58374b85..c5a0ef6f67c0f4064d0da222a88d31949b991d99 100644 --- a/drivers/scsi/hosts.c +++ b/drivers/scsi/hosts.c @@ -178,6 +178,7 @@ void scsi_remove_host(struct Scsi_Host *shost) scsi_forget_host(shost); mutex_unlock(&shost->scan_mutex); scsi_proc_host_rm(shost); + scsi_proc_hostdir_rm(shost->hostt); spin_lock_irqsave(shost->host_lock, flags); if (scsi_host_set_state(shost, SHOST_DEL)) @@ -329,6 +330,7 @@ static void scsi_host_dev_release(struct device *dev) struct Scsi_Host *shost = dev_to_shost(dev); struct device *parent = dev->parent; + /* In case scsi_remove_host() has not been called. */ scsi_proc_hostdir_rm(shost->hostt); /* Wait for functions invoked through call_rcu(&shost->rcu, ...) */ @@ -530,7 +532,7 @@ EXPORT_SYMBOL(scsi_host_alloc); static int __scsi_host_match(struct device *dev, const void *data) { struct Scsi_Host *p; - const unsigned short *hostnum = data; + const unsigned int *hostnum = data; p = class_to_shost(dev); return p->host_no == *hostnum; @@ -547,7 +549,7 @@ static int __scsi_host_match(struct device *dev, const void *data) * that scsi_host_get() took. The put_device() below dropped * the reference from class_find_device(). **/ -struct Scsi_Host *scsi_host_lookup(unsigned short hostnum) +struct Scsi_Host *scsi_host_lookup(unsigned int hostnum) { struct device *cdev; struct Scsi_Host *shost = NULL; diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index 5989c868bfe08747cf26c528f775482623596293..921ecaf33c9b42dc3efb57a8c7cbfb6a940c08f8 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -1531,23 +1531,22 @@ static void ipr_process_ccn(struct ipr_cmnd *ipr_cmd) } /** - * strip_and_pad_whitespace - Strip and pad trailing whitespace. - * @i: index into buffer - * @buf: string to modify + * strip_whitespace - Strip and pad trailing whitespace. + * @i: size of buffer + * @buf: string to modify * - * This function will strip all trailing whitespace, pad the end - * of the string with a single space, and NULL terminate the string. + * This function will strip all trailing whitespace and + * NUL terminate the string. * - * Return value: - * new length of string **/ -static int strip_and_pad_whitespace(int i, char *buf) +static void strip_whitespace(int i, char *buf) { + if (i < 1) + return; + i--; while (i && buf[i] == ' ') i--; - buf[i+1] = ' '; - buf[i+2] = '\0'; - return i + 2; + buf[i+1] = '\0'; } /** @@ -1562,19 +1561,21 @@ static int strip_and_pad_whitespace(int i, char *buf) static void ipr_log_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb, struct ipr_vpd *vpd) { - char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN + IPR_SERIAL_NUM_LEN + 3]; - int i = 0; + char vendor_id[IPR_VENDOR_ID_LEN + 1]; + char product_id[IPR_PROD_ID_LEN + 1]; + char sn[IPR_SERIAL_NUM_LEN + 1]; - memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN); - i = strip_and_pad_whitespace(IPR_VENDOR_ID_LEN - 1, buffer); + memcpy(vendor_id, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN); + strip_whitespace(IPR_VENDOR_ID_LEN, vendor_id); - memcpy(&buffer[i], vpd->vpids.product_id, IPR_PROD_ID_LEN); - i = strip_and_pad_whitespace(i + IPR_PROD_ID_LEN - 1, buffer); + memcpy(product_id, vpd->vpids.product_id, IPR_PROD_ID_LEN); + strip_whitespace(IPR_PROD_ID_LEN, product_id); - memcpy(&buffer[i], vpd->sn, IPR_SERIAL_NUM_LEN); - buffer[IPR_SERIAL_NUM_LEN + i] = '\0'; + memcpy(sn, vpd->sn, IPR_SERIAL_NUM_LEN); + strip_whitespace(IPR_SERIAL_NUM_LEN, sn); - ipr_hcam_err(hostrcb, "%s VPID/SN: %s\n", prefix, buffer); + ipr_hcam_err(hostrcb, "%s VPID/SN: %s %s %s\n", prefix, + vendor_id, product_id, sn); } /** diff --git a/drivers/scsi/libfc/fc_lport.c b/drivers/scsi/libfc/fc_lport.c index f653109d56af0e84f8c12a62f18dcb70819056bf..f84c8a9846abb60ffca6f71d37bb8cff286013ff 100644 --- a/drivers/scsi/libfc/fc_lport.c +++ b/drivers/scsi/libfc/fc_lport.c @@ -250,6 +250,12 @@ static void fc_lport_ptp_setup(struct fc_lport *lport, } mutex_lock(&lport->disc.disc_mutex); lport->ptp_rdata = fc_rport_create(lport, remote_fid); + if (!lport->ptp_rdata) { + printk(KERN_WARNING "libfc: Failed to setup lport 0x%x\n", + lport->port_id); + mutex_unlock(&lport->disc.disc_mutex); + return; + } kref_get(&lport->ptp_rdata->kref); lport->ptp_rdata->ids.port_name = remote_wwpn; lport->ptp_rdata->ids.node_name = remote_wwnn; diff --git a/drivers/scsi/megaraid.c b/drivers/scsi/megaraid.c index 7352d46ebb0930056bfe708d00cf77ed9034f3f7..44d648baabd87e4a4a12f432700b641659edf8b0 100644 --- a/drivers/scsi/megaraid.c +++ b/drivers/scsi/megaraid.c @@ -1444,6 +1444,7 @@ mega_cmd_done(adapter_t *adapter, u8 completed[], int nstatus, int status) */ if (cmdid == CMDID_INT_CMDS) { scb = &adapter->int_scb; + cmd = scb->cmd; list_del_init(&scb->list); scb->state = SCB_FREE; diff --git a/drivers/scsi/megaraid/megaraid_sas.h b/drivers/scsi/megaraid/megaraid_sas.h index 67d356d84717631eb7f1c85726a6eff334e2da7f..0d7cca9365aacd4837226ed2a4df177cbad848ce 100644 --- a/drivers/scsi/megaraid/megaraid_sas.h +++ b/drivers/scsi/megaraid/megaraid_sas.h @@ -2193,7 +2193,8 @@ struct megasas_instance { u32 secure_jbod_support; u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */ bool use_seqnum_jbod_fp; /* Added for PD sequence */ - spinlock_t crashdump_lock; + bool smp_affinity_enable; + struct mutex crashdump_lock; struct megasas_register_set __iomem *reg_set; u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; @@ -2210,6 +2211,7 @@ struct megasas_instance { u16 ldio_threshold; u16 cur_can_queue; u32 max_sectors_per_req; + bool msix_load_balance; struct megasas_aen_event *ev; struct megasas_cmd **cmd_list; @@ -2246,6 +2248,7 @@ struct megasas_instance { atomic_t sge_holes_type1; atomic_t sge_holes_type2; atomic_t sge_holes_type3; + atomic64_t total_io_count; struct megasas_instance_template *instancet; struct tasklet_struct isr_tasklet; diff --git a/drivers/scsi/megaraid/megaraid_sas_base.c b/drivers/scsi/megaraid/megaraid_sas_base.c index 8877a21102f1dd486446aa36d72557d71787bfcc..ac4800fb1a7fb40fc780f6b636eead0cb745fdbd 100644 --- a/drivers/scsi/megaraid/megaraid_sas_base.c +++ b/drivers/scsi/megaraid/megaraid_sas_base.c @@ -3004,14 +3004,13 @@ megasas_fw_crash_buffer_store(struct device *cdev, struct megasas_instance *instance = (struct megasas_instance *) shost->hostdata; int val = 0; - unsigned long flags; if (kstrtoint(buf, 0, &val) != 0) return -EINVAL; - spin_lock_irqsave(&instance->crashdump_lock, flags); + mutex_lock(&instance->crashdump_lock); instance->fw_crash_buffer_offset = val; - spin_unlock_irqrestore(&instance->crashdump_lock, flags); + mutex_unlock(&instance->crashdump_lock); return strlen(buf); } @@ -3027,17 +3026,16 @@ megasas_fw_crash_buffer_show(struct device *cdev, unsigned long dmachunk = CRASH_DMA_BUF_SIZE; unsigned long chunk_left_bytes; unsigned long src_addr; - unsigned long flags; u32 buff_offset; - spin_lock_irqsave(&instance->crashdump_lock, flags); + mutex_lock(&instance->crashdump_lock); buff_offset = instance->fw_crash_buffer_offset; - if (!instance->crash_dump_buf && + if (!instance->crash_dump_buf || !((instance->fw_crash_state == AVAILABLE) || (instance->fw_crash_state == COPYING))) { dev_err(&instance->pdev->dev, "Firmware crash dump is not available\n"); - spin_unlock_irqrestore(&instance->crashdump_lock, flags); + mutex_unlock(&instance->crashdump_lock); return -EINVAL; } @@ -3046,7 +3044,7 @@ megasas_fw_crash_buffer_show(struct device *cdev, if (buff_offset > (instance->fw_crash_buffer_size * dmachunk)) { dev_err(&instance->pdev->dev, "Firmware crash dump offset is out of range\n"); - spin_unlock_irqrestore(&instance->crashdump_lock, flags); + mutex_unlock(&instance->crashdump_lock); return 0; } @@ -3058,7 +3056,7 @@ megasas_fw_crash_buffer_show(struct device *cdev, src_addr = (unsigned long)instance->crash_buf[buff_offset / dmachunk] + (buff_offset % dmachunk); memcpy(buf, (void *)src_addr, size); - spin_unlock_irqrestore(&instance->crashdump_lock, flags); + mutex_unlock(&instance->crashdump_lock); return size; } @@ -3083,7 +3081,6 @@ megasas_fw_crash_state_store(struct device *cdev, struct megasas_instance *instance = (struct megasas_instance *) shost->hostdata; int val = 0; - unsigned long flags; if (kstrtoint(buf, 0, &val) != 0) return -EINVAL; @@ -3097,9 +3094,9 @@ megasas_fw_crash_state_store(struct device *cdev, instance->fw_crash_state = val; if ((val == COPIED) || (val == COPY_ERROR)) { - spin_lock_irqsave(&instance->crashdump_lock, flags); + mutex_lock(&instance->crashdump_lock); megasas_free_host_crash_buffer(instance); - spin_unlock_irqrestore(&instance->crashdump_lock, flags); + mutex_unlock(&instance->crashdump_lock); if (val == COPY_ERROR) dev_info(&instance->pdev->dev, "application failed to " "copy Firmware crash dump\n"); @@ -5101,6 +5098,7 @@ megasas_setup_irqs_msix(struct megasas_instance *instance, u8 is_probe) &instance->irq_context[j]); /* Retry irq register for IO_APIC*/ instance->msix_vectors = 0; + instance->msix_load_balance = false; if (is_probe) { pci_free_irq_vectors(instance->pdev); return megasas_setup_irqs_ioapic(instance); @@ -5109,6 +5107,7 @@ megasas_setup_irqs_msix(struct megasas_instance *instance, u8 is_probe) } } } + return 0; } @@ -5364,6 +5363,13 @@ static int megasas_init_fw(struct megasas_instance *instance) if (rdpq_enable) instance->is_rdpq = (scratch_pad_2 & MR_RDPQ_MODE_OFFSET) ? 1 : 0; + + if (instance->adapter_type >= INVADER_SERIES && + !instance->msix_combined) { + instance->msix_load_balance = true; + instance->smp_affinity_enable = false; + } + fw_msix_count = instance->msix_vectors; /* Save 1-15 reply post index address to local memory * Index 0 is already saved from reg offset @@ -5382,17 +5388,20 @@ static int megasas_init_fw(struct megasas_instance *instance) instance->msix_vectors); } else /* MFI adapters */ instance->msix_vectors = 1; + /* Don't bother allocating more MSI-X vectors than cpus */ instance->msix_vectors = min(instance->msix_vectors, (unsigned int)num_online_cpus()); - if (smp_affinity_enable) + if (instance->smp_affinity_enable) irq_flags |= PCI_IRQ_AFFINITY; i = pci_alloc_irq_vectors(instance->pdev, 1, instance->msix_vectors, irq_flags); - if (i > 0) + if (i > 0) { instance->msix_vectors = i; - else + } else { instance->msix_vectors = 0; + instance->msix_load_balance = false; + } } /* * MSI-X host index 0 is common for all adapter. @@ -6447,11 +6456,12 @@ static inline void megasas_init_ctrl_params(struct megasas_instance *instance) INIT_LIST_HEAD(&instance->internal_reset_pending_q); atomic_set(&instance->fw_outstanding, 0); + atomic64_set(&instance->total_io_count, 0); init_waitqueue_head(&instance->int_cmd_wait_q); init_waitqueue_head(&instance->abort_cmd_wait_q); - spin_lock_init(&instance->crashdump_lock); + mutex_init(&instance->crashdump_lock); spin_lock_init(&instance->mfi_pool_lock); spin_lock_init(&instance->hba_lock); spin_lock_init(&instance->stream_lock); @@ -6469,6 +6479,8 @@ static inline void megasas_init_ctrl_params(struct megasas_instance *instance) instance->last_time = 0; instance->disableOnlineCtrlReset = 1; instance->UnevenSpanSupport = 0; + instance->smp_affinity_enable = smp_affinity_enable ? true : false; + instance->msix_load_balance = false; if (instance->adapter_type != MFI_SERIES) { INIT_WORK(&instance->work_init, megasas_fusion_ocr_wq); @@ -6818,7 +6830,7 @@ megasas_resume(struct pci_dev *pdev) /* Now re-enable MSI-X */ if (instance->msix_vectors) { irq_flags = PCI_IRQ_MSIX; - if (smp_affinity_enable) + if (instance->smp_affinity_enable) irq_flags |= PCI_IRQ_AFFINITY; } rval = pci_alloc_irq_vectors(instance->pdev, 1, diff --git a/drivers/scsi/megaraid/megaraid_sas_fusion.c b/drivers/scsi/megaraid/megaraid_sas_fusion.c index bdb12bf0d5c753f33a38f46b3ed500f939ef99d7..294e1a3a6adfa70d2dea243e75214678d6531bf2 100644 --- a/drivers/scsi/megaraid/megaraid_sas_fusion.c +++ b/drivers/scsi/megaraid/megaraid_sas_fusion.c @@ -2641,8 +2641,13 @@ megasas_build_ldio_fusion(struct megasas_instance *instance, fp_possible = (io_info.fpOkForIo > 0) ? true : false; } - cmd->request_desc->SCSIIO.MSIxIndex = - instance->reply_map[raw_smp_processor_id()]; + if (instance->msix_load_balance) + cmd->request_desc->SCSIIO.MSIxIndex = + (mega_mod64(atomic64_add_return(1, &instance->total_io_count), + instance->msix_vectors)); + else + cmd->request_desc->SCSIIO.MSIxIndex = + instance->reply_map[raw_smp_processor_id()]; praid_context = &io_request->RaidContext; @@ -2969,8 +2974,13 @@ megasas_build_syspd_fusion(struct megasas_instance *instance, cmd->request_desc->SCSIIO.DevHandle = io_request->DevHandle; - cmd->request_desc->SCSIIO.MSIxIndex = - instance->reply_map[raw_smp_processor_id()]; + if (instance->msix_load_balance) + cmd->request_desc->SCSIIO.MSIxIndex = + (mega_mod64(atomic64_add_return(1, &instance->total_io_count), + instance->msix_vectors)); + else + cmd->request_desc->SCSIIO.MSIxIndex = + instance->reply_map[raw_smp_processor_id()]; if (!fp_possible) { /* system pd firmware path */ @@ -4367,7 +4377,7 @@ int megasas_task_abort_fusion(struct scsi_cmnd *scmd) devhandle = megasas_get_tm_devhandle(scmd->device); if (devhandle == (u16)ULONG_MAX) { - ret = SUCCESS; + ret = FAILED; sdev_printk(KERN_INFO, scmd->device, "task abort issued for invalid devhandle\n"); mutex_unlock(&instance->reset_mutex); @@ -4440,7 +4450,7 @@ int megasas_reset_target_fusion(struct scsi_cmnd *scmd) devhandle = megasas_get_tm_devhandle(scmd->device); if (devhandle == (u16)ULONG_MAX) { - ret = SUCCESS; + ret = FAILED; sdev_printk(KERN_INFO, scmd->device, "target reset issued for invalid devhandle\n"); mutex_unlock(&instance->reset_mutex); diff --git a/drivers/scsi/mpt3sas/mpt3sas_scsih.c b/drivers/scsi/mpt3sas/mpt3sas_scsih.c index c8d97dc2ca63d7539d5d945c4d2c3e630261443c..bf659bc466dcceaba3a270ce9a80780ce34ebc5f 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_scsih.c +++ b/drivers/scsi/mpt3sas/mpt3sas_scsih.c @@ -11182,8 +11182,10 @@ _mpt3sas_init(void) mpt3sas_ctl_init(hbas_to_enumerate); error = pci_register_driver(&mpt3sas_driver); - if (error) + if (error) { + mpt3sas_ctl_exit(hbas_to_enumerate); scsih_exit(); + } return error; } diff --git a/drivers/scsi/pm8001/pm8001_hwi.c b/drivers/scsi/pm8001/pm8001_hwi.c index d532230c62f3e1ef457dbb89d8e973f5455d1380..69695bb99925bb78c740af32e60a5d3d260f26d2 100644 --- a/drivers/scsi/pm8001/pm8001_hwi.c +++ b/drivers/scsi/pm8001/pm8001_hwi.c @@ -4174,7 +4174,7 @@ static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) { struct outbound_queue_table *circularQ; void *pMsg1 = NULL; - u8 uninitialized_var(bc); + u8 bc; u32 ret = MPI_IO_STATUS_FAIL; unsigned long flags; diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c index d655f72db51d549c4a77b492b33b23a6d7a60d58..067be417e251bf5392a9b4de7c9694d8929a8219 100644 --- a/drivers/scsi/pm8001/pm80xx_hwi.c +++ b/drivers/scsi/pm8001/pm80xx_hwi.c @@ -3811,7 +3811,7 @@ static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) { struct outbound_queue_table *circularQ; void *pMsg1 = NULL; - u8 uninitialized_var(bc); + u8 bc; u32 ret = MPI_IO_STATUS_FAIL; unsigned long flags; u32 regval; diff --git a/drivers/scsi/qedf/qedf_dbg.h b/drivers/scsi/qedf/qedf_dbg.h index dd0109653aa32d18ade66046947efbed5dc93265..9c7f7b444daa7dc4b0edea11b1370b117e03832d 100644 --- a/drivers/scsi/qedf/qedf_dbg.h +++ b/drivers/scsi/qedf/qedf_dbg.h @@ -63,6 +63,8 @@ extern uint qedf_debug; #define QEDF_LOG_NOTICE 0x40000000 /* Notice logs */ #define QEDF_LOG_WARN 0x80000000 /* Warning logs */ +#define QEDF_DEBUGFS_LOG_LEN (2 * PAGE_SIZE) + /* Debug context structure */ struct qedf_dbg_ctx { unsigned int host_no; diff --git a/drivers/scsi/qedf/qedf_debugfs.c b/drivers/scsi/qedf/qedf_debugfs.c index c29c162a494ff13a0631def00d6156ca039e7fa2..84f1ddcfbb2180a4ac9e273995a69a0c509a75b8 100644 --- a/drivers/scsi/qedf/qedf_debugfs.c +++ b/drivers/scsi/qedf/qedf_debugfs.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "qedf.h" #include "qedf_dbg.h" @@ -117,7 +118,9 @@ static ssize_t qedf_dbg_fp_int_cmd_read(struct file *filp, char __user *buffer, size_t count, loff_t *ppos) { + ssize_t ret; size_t cnt = 0; + char *cbuf; int id; struct qedf_fastpath *fp = NULL; struct qedf_dbg_ctx *qedf_dbg = @@ -127,19 +130,25 @@ qedf_dbg_fp_int_cmd_read(struct file *filp, char __user *buffer, size_t count, QEDF_INFO(qedf_dbg, QEDF_LOG_DEBUGFS, "entered\n"); - cnt = sprintf(buffer, "\nFastpath I/O completions\n\n"); + cbuf = vmalloc(QEDF_DEBUGFS_LOG_LEN); + if (!cbuf) + return 0; + + cnt += scnprintf(cbuf + cnt, QEDF_DEBUGFS_LOG_LEN - cnt, "\nFastpath I/O completions\n\n"); for (id = 0; id < qedf->num_queues; id++) { fp = &(qedf->fp_array[id]); if (fp->sb_id == QEDF_SB_ID_NULL) continue; - cnt += sprintf((buffer + cnt), "#%d: %lu\n", id, - fp->completions); + cnt += scnprintf(cbuf + cnt, QEDF_DEBUGFS_LOG_LEN - cnt, + "#%d: %lu\n", id, fp->completions); } - cnt = min_t(int, count, cnt - *ppos); - *ppos += cnt; - return cnt; + ret = simple_read_from_buffer(buffer, count, ppos, cbuf, cnt); + + vfree(cbuf); + + return ret; } static ssize_t @@ -204,18 +213,17 @@ qedf_dbg_stop_io_on_error_cmd_read(struct file *filp, char __user *buffer, size_t count, loff_t *ppos) { int cnt; + char cbuf[7]; struct qedf_dbg_ctx *qedf_dbg = (struct qedf_dbg_ctx *)filp->private_data; struct qedf_ctx *qedf = container_of(qedf_dbg, struct qedf_ctx, dbg_ctx); QEDF_INFO(qedf_dbg, QEDF_LOG_DEBUGFS, "entered\n"); - cnt = sprintf(buffer, "%s\n", + cnt = scnprintf(cbuf, sizeof(cbuf), "%s\n", qedf->stop_io_on_error ? "true" : "false"); - cnt = min_t(int, count, cnt - *ppos); - *ppos += cnt; - return cnt; + return simple_read_from_buffer(buffer, count, ppos, cbuf, cnt); } static ssize_t diff --git a/drivers/scsi/qedi/qedi_main.c b/drivers/scsi/qedi/qedi_main.c index ab66e1f0fdfa380cef80f695701845225bdf10fe..7a179cfc01ed265075bbd50e067e0867cde8f61f 100644 --- a/drivers/scsi/qedi/qedi_main.c +++ b/drivers/scsi/qedi/qedi_main.c @@ -1864,8 +1864,9 @@ static int qedi_cpu_offline(unsigned int cpu) struct qedi_percpu_s *p = this_cpu_ptr(&qedi_percpu); struct qedi_work *work, *tmp; struct task_struct *thread; + unsigned long flags; - spin_lock_bh(&p->p_work_lock); + spin_lock_irqsave(&p->p_work_lock, flags); thread = p->iothread; p->iothread = NULL; @@ -1876,7 +1877,7 @@ static int qedi_cpu_offline(unsigned int cpu) kfree(work); } - spin_unlock_bh(&p->p_work_lock); + spin_unlock_irqrestore(&p->p_work_lock, flags); if (thread) kthread_stop(thread); return 0; diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c index d46a10d24ed4b8c4c35f657ceb8f8e5033b3acae..9a25e92ef1abeb43199e06a4937e41177d71fdd9 100644 --- a/drivers/scsi/qla2xxx/qla_attr.c +++ b/drivers/scsi/qla2xxx/qla_attr.c @@ -1800,6 +1800,7 @@ static void qla2x00_terminate_rport_io(struct fc_rport *rport) { fc_port_t *fcport = *(fc_port_t **)rport->dd_data; + scsi_qla_host_t *vha; if (!fcport) return; @@ -1809,9 +1810,12 @@ qla2x00_terminate_rport_io(struct fc_rport *rport) if (test_bit(ABORT_ISP_ACTIVE, &fcport->vha->dpc_flags)) return; + vha = fcport->vha; if (unlikely(pci_channel_offline(fcport->vha->hw->pdev))) { qla2x00_abort_all_cmds(fcport->vha, DID_NO_CONNECT << 16); + qla2x00_eh_wait_for_pending_commands(fcport->vha, fcport->d_id.b24, + 0, WAIT_TARGET); return; } /* @@ -1826,6 +1830,15 @@ qla2x00_terminate_rport_io(struct fc_rport *rport) else qla2x00_port_logout(fcport->vha, fcport); } + + /* check for any straggling io left behind */ + if (qla2x00_eh_wait_for_pending_commands(fcport->vha, fcport->d_id.b24, 0, WAIT_TARGET)) { + ql_log(ql_log_warn, vha, 0x300b, + "IO not return. Resetting. \n"); + set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); + qla2xxx_wake_dpc(vha); + qla2x00_wait_for_chip_reset(vha); + } } static int @@ -2075,8 +2088,6 @@ qla24xx_vport_create(struct fc_vport *fc_vport, bool disable) vha->flags.difdix_supported = 1; ql_dbg(ql_dbg_user, vha, 0x7082, "Registered for DIF/DIX type 1 and 3 protection.\n"); - if (ql2xenabledif == 1) - prot = SHOST_DIX_TYPE0_PROTECTION; scsi_host_set_prot(vha->host, prot | SHOST_DIF_TYPE1_PROTECTION | SHOST_DIF_TYPE2_PROTECTION diff --git a/drivers/scsi/qla2xxx/qla_bsg.c b/drivers/scsi/qla2xxx/qla_bsg.c index eae16657296436874fdfbd73dd82ec9ec7375d44..430dfe3d5416a9d047d4974522ffa7ae6d5ba230 100644 --- a/drivers/scsi/qla2xxx/qla_bsg.c +++ b/drivers/scsi/qla2xxx/qla_bsg.c @@ -264,6 +264,10 @@ qla2x00_process_els(struct bsg_job *bsg_job) if (bsg_request->msgcode == FC_BSG_RPT_ELS) { rport = fc_bsg_to_rport(bsg_job); + if (!rport) { + rval = -ENOMEM; + goto done; + } fcport = *(fc_port_t **) rport->dd_data; host = rport_to_shost(rport); vha = shost_priv(host); @@ -2484,6 +2488,8 @@ qla24xx_bsg_request(struct bsg_job *bsg_job) if (bsg_request->msgcode == FC_BSG_RPT_ELS) { rport = fc_bsg_to_rport(bsg_job); + if (!rport) + return ret; host = rport_to_shost(rport); vha = shost_priv(host); } else { diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c index 36871760a5d372da9b63109a2be5fa8d4edb22ec..fcbadd41856c20a3fee6850095ca17b69c716a09 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.c +++ b/drivers/scsi/qla2xxx/qla_dbg.c @@ -22,7 +22,7 @@ * | Queue Command and IO tracing | 0x3074 | 0x300b | * | | | 0x3027-0x3028 | * | | | 0x303d-0x3041 | - * | | | 0x302d,0x3033 | + * | | | 0x302e,0x3033 | * | | | 0x3036,0x3038 | * | | | 0x303a | * | DPC Thread | 0x4023 | 0x4002,0x4013 | diff --git a/drivers/scsi/qla2xxx/qla_iocb.c b/drivers/scsi/qla2xxx/qla_iocb.c index 7e47321e003c81cde1decb57818689a0883729de..23cd9ff82478960a37dfa2737c66a789314c2338 100644 --- a/drivers/scsi/qla2xxx/qla_iocb.c +++ b/drivers/scsi/qla2xxx/qla_iocb.c @@ -603,7 +603,8 @@ qla24xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt, *((uint32_t *)(&cmd_pkt->entry_type)) = cpu_to_le32(COMMAND_TYPE_6); /* No data transfer */ - if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) { + if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE || + tot_dsds == 0) { cmd_pkt->byte_count = cpu_to_le32(0); return 0; } diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c index 9c7af5e1dfb07befb2350548711eee6e28b66f99..ca2bc3f36ff6a39916af8ba27736cfd33a70211f 100644 --- a/drivers/scsi/qla2xxx/qla_isr.c +++ b/drivers/scsi/qla2xxx/qla_isr.c @@ -2673,7 +2673,6 @@ qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt) case CS_PORT_BUSY: case CS_INCOMPLETE: case CS_PORT_UNAVAILABLE: - case CS_TIMEOUT: case CS_RESET: /* diff --git a/drivers/scsi/qla2xxx/qla_nvme.c b/drivers/scsi/qla2xxx/qla_nvme.c index dcd0f058f23e085797977dfd7362ca02f4ce7751..35762d29b04baffa3f3826f0ff7adbead191dcd6 100644 --- a/drivers/scsi/qla2xxx/qla_nvme.c +++ b/drivers/scsi/qla2xxx/qla_nvme.c @@ -518,7 +518,7 @@ static int qla_nvme_post_cmd(struct nvme_fc_local_port *lport, rval = qla2x00_start_nvme_mq(sp); if (rval != QLA_SUCCESS) { - ql_log(ql_log_warn, vha, 0x212d, + ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x212d, "qla2x00_start_nvme_mq failed = %d\n", rval); atomic_dec(&sp->ref_count); wake_up(&sp->nvme_ls_waitq); diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index 207af1d5ed292d8fe12a29164fcb8289f0a967c4..36dca08166f295d9447fb72cf209366ed968f3ff 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c @@ -277,6 +277,20 @@ MODULE_PARM_DESC(qla2xuseresexchforels, "Reserve 1/2 of emergency exchanges for ELS.\n" " 0 (default): disabled"); +int ql2xprotmask; +module_param(ql2xprotmask, int, 0644); +MODULE_PARM_DESC(ql2xprotmask, + "Override DIF/DIX protection capabilities mask\n" + "Default is 0 which sets protection mask based on " + "capabilities reported by HBA firmware.\n"); + +int ql2xprotguard; +module_param(ql2xprotguard, int, 0644); +MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" + " 0 -- Let HBA firmware decide\n" + " 1 -- Force T10 CRC\n" + " 2 -- Force IP checksum\n"); + /* * SCSI host template entry points */ @@ -3055,6 +3069,13 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) host->max_id = ha->max_fibre_devices; host->cmd_per_lun = 3; host->unique_id = host->host_no; + + if (ql2xenabledif && ql2xenabledif != 2) { + ql_log(ql_log_warn, base_vha, 0x302d, + "Invalid value for ql2xenabledif, resetting it to default (2)\n"); + ql2xenabledif = 2; + } + if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) host->max_cmd_len = 32; else @@ -3291,15 +3312,16 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) base_vha->flags.difdix_supported = 1; ql_dbg(ql_dbg_init, base_vha, 0x00f1, "Registering for DIF/DIX type 1 and 3 protection.\n"); - if (ql2xenabledif == 1) - prot = SHOST_DIX_TYPE0_PROTECTION; - scsi_host_set_prot(host, - prot | SHOST_DIF_TYPE1_PROTECTION - | SHOST_DIF_TYPE2_PROTECTION - | SHOST_DIF_TYPE3_PROTECTION - | SHOST_DIX_TYPE1_PROTECTION - | SHOST_DIX_TYPE2_PROTECTION - | SHOST_DIX_TYPE3_PROTECTION); + if (ql2xprotmask) + scsi_host_set_prot(host, ql2xprotmask); + else + scsi_host_set_prot(host, + prot | SHOST_DIF_TYPE1_PROTECTION + | SHOST_DIF_TYPE2_PROTECTION + | SHOST_DIF_TYPE3_PROTECTION + | SHOST_DIX_TYPE1_PROTECTION + | SHOST_DIX_TYPE2_PROTECTION + | SHOST_DIX_TYPE3_PROTECTION); guard = SHOST_DIX_GUARD_CRC; @@ -3307,7 +3329,10 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) guard |= SHOST_DIX_GUARD_IP; - scsi_host_set_guard(host, guard); + if (ql2xprotguard) + scsi_host_set_guard(host, ql2xprotguard); + else + scsi_host_set_guard(host, guard); } else base_vha->flags.difdix_supported = 0; } @@ -4604,7 +4629,8 @@ struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, } INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); - sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); + snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu", + QLA2XXX_DRIVER_NAME, vha->host_no); ql_dbg(ql_dbg_init, vha, 0x0041, "Allocated the host=%p hw=%p vha=%p dev_name=%s", vha->host, vha->hw, vha, @@ -4735,7 +4761,7 @@ qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) switch (code) { case QLA_UEVENT_CODE_FW_DUMP: - snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", + snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", vha->host_no); break; default: @@ -6149,9 +6175,12 @@ qla2x00_do_dpc(void *data) } } loop_resync_check: - if (test_and_clear_bit(LOOP_RESYNC_NEEDED, + if (!qla2x00_reset_active(base_vha) && + test_and_clear_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags)) { - + /* + * Allow abort_isp to complete before moving on to scanning. + */ ql_dbg(ql_dbg_dpc, base_vha, 0x400f, "Loop resync scheduled.\n"); @@ -6384,7 +6413,7 @@ qla2x00_timer(struct timer_list *t) /* if the loop has been down for 4 minutes, reinit adapter */ if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { - if (!(vha->device_flags & DFLG_NO_CABLE)) { + if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) { ql_log(ql_log_warn, vha, 0x6009, "Loop down - aborting ISP.\n"); diff --git a/drivers/scsi/qla4xxx/ql4_os.c b/drivers/scsi/qla4xxx/ql4_os.c index 4ba9f46fcf748c5e518eeae7cba34f3dd0c6d69e..21cc9e2797a287d710bd3c1e350d462008f10954 100644 --- a/drivers/scsi/qla4xxx/ql4_os.c +++ b/drivers/scsi/qla4xxx/ql4_os.c @@ -940,6 +940,11 @@ static int qla4xxx_set_chap_entry(struct Scsi_Host *shost, void *data, int len) memset(&chap_rec, 0, sizeof(chap_rec)); nla_for_each_attr(attr, data, len, rem) { + if (nla_len(attr) < sizeof(*param_info)) { + rc = -EINVAL; + goto exit_set_chap; + } + param_info = nla_data(attr); switch (param_info->param) { @@ -2724,6 +2729,11 @@ qla4xxx_iface_set_param(struct Scsi_Host *shost, void *data, uint32_t len) } nla_for_each_attr(attr, data, len, rem) { + if (nla_len(attr) < sizeof(*iface_param)) { + rval = -EINVAL; + goto exit_init_fw_cb; + } + iface_param = nla_data(attr); if (iface_param->param_type == ISCSI_NET_PARAM) { @@ -8098,6 +8108,11 @@ qla4xxx_sysfs_ddb_set_param(struct iscsi_bus_flash_session *fnode_sess, memset((void *)&chap_tbl, 0, sizeof(chap_tbl)); nla_for_each_attr(attr, data, len, rem) { + if (nla_len(attr) < sizeof(*fnode_param)) { + rc = -EINVAL; + goto exit_set_param; + } + fnode_param = nla_data(attr); switch (fnode_param->param) { diff --git a/drivers/scsi/raid_class.c b/drivers/scsi/raid_class.c index 5c3d6e1e0145e61fbeccd99a389485160615f6c3..cd7912e34dcd6e36e22bb69b8b8a69a2d90b5b6f 100644 --- a/drivers/scsi/raid_class.c +++ b/drivers/scsi/raid_class.c @@ -210,53 +210,6 @@ raid_attr_ro_state(level); raid_attr_ro_fn(resync); raid_attr_ro_state_fn(state); -static void raid_component_release(struct device *dev) -{ - struct raid_component *rc = - container_of(dev, struct raid_component, dev); - dev_printk(KERN_ERR, rc->dev.parent, "COMPONENT RELEASE\n"); - put_device(rc->dev.parent); - kfree(rc); -} - -int raid_component_add(struct raid_template *r,struct device *raid_dev, - struct device *component_dev) -{ - struct device *cdev = - attribute_container_find_class_device(&r->raid_attrs.ac, - raid_dev); - struct raid_component *rc; - struct raid_data *rd = dev_get_drvdata(cdev); - int err; - - rc = kzalloc(sizeof(*rc), GFP_KERNEL); - if (!rc) - return -ENOMEM; - - INIT_LIST_HEAD(&rc->node); - device_initialize(&rc->dev); - rc->dev.release = raid_component_release; - rc->dev.parent = get_device(component_dev); - rc->num = rd->component_count++; - - dev_set_name(&rc->dev, "component-%d", rc->num); - list_add_tail(&rc->node, &rd->component_list); - rc->dev.class = &raid_class.class; - err = device_add(&rc->dev); - if (err) - goto err_out; - - return 0; - -err_out: - list_del(&rc->node); - rd->component_count--; - put_device(component_dev); - kfree(rc); - return err; -} -EXPORT_SYMBOL(raid_component_add); - struct raid_template * raid_class_attach(struct raid_function_template *ft) { diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index febe29a9b8b0611d035a37749b6eef1c4fc6b9a7..acd118da88bfb50fc69917cb36bbcf863d1e5be1 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -351,11 +351,18 @@ static int scsi_vpd_inquiry(struct scsi_device *sdev, unsigned char *buffer, if (result) return -EIO; - /* Sanity check that we got the page back that we asked for */ + /* + * Sanity check that we got the page back that we asked for and that + * the page size is not 0. + */ if (buffer[1] != page) return -EIO; - return get_unaligned_be16(&buffer[2]) + 4; + result = get_unaligned_be16(&buffer[2]); + if (!result) + return -EIO; + + return result + 4; } /** diff --git a/drivers/scsi/scsi_devinfo.c b/drivers/scsi/scsi_devinfo.c index 6a2a413cc97e0e75f249b754e0b08f336a59f0eb..d8557a00e1ecfb7a67d4f5873731cdcee133d669 100644 --- a/drivers/scsi/scsi_devinfo.c +++ b/drivers/scsi/scsi_devinfo.c @@ -232,6 +232,7 @@ static struct { {"SGI", "RAID5", "*", BLIST_SPARSELUN}, {"SGI", "TP9100", "*", BLIST_REPORTLUN2}, {"SGI", "Universal Xport", "*", BLIST_NO_ULD_ATTACH}, + {"SKhynix", "H28U74301AMR", NULL, BLIST_SKIP_VPD_PAGES}, {"IBM", "Universal Xport", "*", BLIST_NO_ULD_ATTACH}, {"SUN", "Universal Xport", "*", BLIST_NO_ULD_ATTACH}, {"DELL", "Universal Xport", "*", BLIST_NO_ULD_ATTACH}, diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c index 0aada12d6f93072f0e5afcd8da189645b2021c56..2656d6ace8ffbdf39d24021c13f831d4fc949130 100644 --- a/drivers/scsi/scsi_lib.c +++ b/drivers/scsi/scsi_lib.c @@ -1808,6 +1808,7 @@ static int scsi_dispatch_cmd(struct scsi_cmnd *cmd) */ SCSI_LOG_MLQUEUE(3, scmd_printk(KERN_INFO, cmd, "queuecommand : device blocked\n")); + atomic_dec(&cmd->device->iorequest_cnt); return SCSI_MLQUEUE_DEVICE_BUSY; } @@ -1840,6 +1841,7 @@ static int scsi_dispatch_cmd(struct scsi_cmnd *cmd) trace_scsi_dispatch_cmd_start(cmd); rtn = host->hostt->queuecommand(host, cmd); if (rtn) { + atomic_dec(&cmd->device->iorequest_cnt); trace_scsi_dispatch_cmd_error(cmd, rtn); if (rtn != SCSI_MLQUEUE_DEVICE_BUSY && rtn != SCSI_MLQUEUE_TARGET_BUSY) diff --git a/drivers/scsi/scsi_proc.c b/drivers/scsi/scsi_proc.c index 7f0ceb65c3f39dcc89ac21a10f36de6391b5bcee..99f472bb9f7e5f43eb84856a38bc9f9cd2329372 100644 --- a/drivers/scsi/scsi_proc.c +++ b/drivers/scsi/scsi_proc.c @@ -311,7 +311,7 @@ static ssize_t proc_scsi_write(struct file *file, const char __user *buf, size_t length, loff_t *ppos) { int host, channel, id, lun; - char *buffer, *p; + char *buffer, *end, *p; int err; if (!buf || length > PAGE_SIZE) @@ -326,10 +326,14 @@ static ssize_t proc_scsi_write(struct file *file, const char __user *buf, goto out; err = -EINVAL; - if (length < PAGE_SIZE) - buffer[length] = '\0'; - else if (buffer[PAGE_SIZE-1]) - goto out; + if (length < PAGE_SIZE) { + end = buffer + length; + *end = '\0'; + } else { + end = buffer + PAGE_SIZE - 1; + if (*end) + goto out; + } /* * Usage: echo "scsi add-single-device 0 1 2 3" >/proc/scsi/scsi @@ -338,10 +342,10 @@ static ssize_t proc_scsi_write(struct file *file, const char __user *buf, if (!strncmp("scsi add-single-device", buffer, 22)) { p = buffer + 23; - host = simple_strtoul(p, &p, 0); - channel = simple_strtoul(p + 1, &p, 0); - id = simple_strtoul(p + 1, &p, 0); - lun = simple_strtoul(p + 1, &p, 0); + host = (p < end) ? simple_strtoul(p, &p, 0) : 0; + channel = (p + 1 < end) ? simple_strtoul(p + 1, &p, 0) : 0; + id = (p + 1 < end) ? simple_strtoul(p + 1, &p, 0) : 0; + lun = (p + 1 < end) ? simple_strtoul(p + 1, &p, 0) : 0; err = scsi_add_single_device(host, channel, id, lun); @@ -352,10 +356,10 @@ static ssize_t proc_scsi_write(struct file *file, const char __user *buf, } else if (!strncmp("scsi remove-single-device", buffer, 25)) { p = buffer + 26; - host = simple_strtoul(p, &p, 0); - channel = simple_strtoul(p + 1, &p, 0); - id = simple_strtoul(p + 1, &p, 0); - lun = simple_strtoul(p + 1, &p, 0); + host = (p < end) ? simple_strtoul(p, &p, 0) : 0; + channel = (p + 1 < end) ? simple_strtoul(p + 1, &p, 0) : 0; + id = (p + 1 < end) ? simple_strtoul(p + 1, &p, 0) : 0; + lun = (p + 1 < end) ? simple_strtoul(p + 1, &p, 0) : 0; err = scsi_remove_single_device(host, channel, id, lun); } diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c index 79581771e6f6114a1c93dfd1732bd280d0e2c568..b13d1be1b0f105316dee0c6318a14b842007b2dd 100644 --- a/drivers/scsi/scsi_transport_iscsi.c +++ b/drivers/scsi/scsi_transport_iscsi.c @@ -2765,6 +2765,10 @@ iscsi_set_param(struct iscsi_transport *transport, struct iscsi_uevent *ev) if (!conn || !session) return -EINVAL; + /* data will be regarded as NULL-ended string, do length check */ + if (strlen(data) > ev->u.set_param.len) + return -EINVAL; + switch (ev->u.set_param.param) { case ISCSI_PARAM_SESS_RECOVERY_TMO: sscanf(data, "%d", &value); @@ -2917,6 +2921,10 @@ iscsi_set_host_param(struct iscsi_transport *transport, return -ENODEV; } + /* see similar check in iscsi_if_set_param() */ + if (strlen(data) > ev->u.set_host_param.len) + return -EINVAL; + err = transport->set_host_param(shost, ev->u.set_host_param.param, data, ev->u.set_host_param.len); scsi_host_put(shost); diff --git a/drivers/scsi/ses.c b/drivers/scsi/ses.c index e79d9f60a52824f5786ca7744c50628e0812f08e..f2ab113d66337b05b878afb055cd3c7a3e62a86f 100644 --- a/drivers/scsi/ses.c +++ b/drivers/scsi/ses.c @@ -449,8 +449,8 @@ int ses_match_host(struct enclosure_device *edev, void *data) } #endif /* 0 */ -static void ses_process_descriptor(struct enclosure_component *ecomp, - unsigned char *desc) +static int ses_process_descriptor(struct enclosure_component *ecomp, + unsigned char *desc, int max_desc_len) { int eip = desc[0] & 0x10; int invalid = desc[0] & 0x80; @@ -461,22 +461,32 @@ static void ses_process_descriptor(struct enclosure_component *ecomp, unsigned char *d; if (invalid) - return; + return 0; switch (proto) { case SCSI_PROTOCOL_FCP: if (eip) { + if (max_desc_len <= 7) + return 1; d = desc + 4; slot = d[3]; } break; case SCSI_PROTOCOL_SAS: + if (eip) { + if (max_desc_len <= 27) + return 1; d = desc + 4; slot = d[3]; d = desc + 8; - } else + } else { + if (max_desc_len <= 23) + return 1; d = desc + 4; + } + + /* only take the phy0 addr */ addr = (u64)d[12] << 56 | (u64)d[13] << 48 | @@ -493,6 +503,8 @@ static void ses_process_descriptor(struct enclosure_component *ecomp, } ecomp->slot = slot; scomp->addr = addr; + + return 0; } struct efd { @@ -507,9 +519,6 @@ static int ses_enclosure_find_by_addr(struct enclosure_device *edev, int i; struct ses_component *scomp; - if (!edev->component[0].scratch) - return 0; - for (i = 0; i < edev->components; i++) { scomp = edev->component[i].scratch; if (scomp->addr != efd->addr) @@ -565,7 +574,7 @@ static void ses_enclosure_data_process(struct enclosure_device *edev, /* skip past overall descriptor */ desc_ptr += len + 4; } - if (ses_dev->page10) + if (ses_dev->page10 && ses_dev->page10_len > 9) addl_desc_ptr = ses_dev->page10 + 8; type_ptr = ses_dev->page1_types; components = 0; @@ -573,17 +582,22 @@ static void ses_enclosure_data_process(struct enclosure_device *edev, for (j = 0; j < type_ptr[1]; j++) { char *name = NULL; struct enclosure_component *ecomp; + int max_desc_len; if (desc_ptr) { - if (desc_ptr >= buf + page7_len) { + if (desc_ptr + 3 >= buf + page7_len) { desc_ptr = NULL; } else { len = (desc_ptr[2] << 8) + desc_ptr[3]; desc_ptr += 4; - /* Add trailing zero - pushes into - * reserved space */ - desc_ptr[len] = '\0'; - name = desc_ptr; + if (desc_ptr + len > buf + page7_len) + desc_ptr = NULL; + else { + /* Add trailing zero - pushes into + * reserved space */ + desc_ptr[len] = '\0'; + name = desc_ptr; + } } } if (type_ptr[0] == ENCLOSURE_COMPONENT_DEVICE || @@ -595,14 +609,20 @@ static void ses_enclosure_data_process(struct enclosure_device *edev, components++, type_ptr[0], name); - else + else if (components < edev->components) ecomp = &edev->component[components++]; + else + ecomp = ERR_PTR(-EINVAL); if (!IS_ERR(ecomp)) { - if (addl_desc_ptr) - ses_process_descriptor( - ecomp, - addl_desc_ptr); + if (addl_desc_ptr) { + max_desc_len = ses_dev->page10_len - + (addl_desc_ptr - ses_dev->page10); + if (ses_process_descriptor(ecomp, + addl_desc_ptr, + max_desc_len)) + addl_desc_ptr = NULL; + } if (create) enclosure_component_register( ecomp); @@ -619,9 +639,11 @@ static void ses_enclosure_data_process(struct enclosure_device *edev, /* these elements are optional */ type_ptr[0] == ENCLOSURE_COMPONENT_SCSI_TARGET_PORT || type_ptr[0] == ENCLOSURE_COMPONENT_SCSI_INITIATOR_PORT || - type_ptr[0] == ENCLOSURE_COMPONENT_CONTROLLER_ELECTRONICS)) + type_ptr[0] == ENCLOSURE_COMPONENT_CONTROLLER_ELECTRONICS)) { addl_desc_ptr += addl_desc_ptr[1] + 2; - + if (addl_desc_ptr + 1 >= ses_dev->page10 + ses_dev->page10_len) + addl_desc_ptr = NULL; + } } } kfree(buf); @@ -720,6 +742,7 @@ static int ses_intf_add(struct device *cdev, type_ptr[0] == ENCLOSURE_COMPONENT_ARRAY_DEVICE) components += type_ptr[1]; } + ses_dev->page1 = buf; ses_dev->page1_len = len; buf = NULL; @@ -761,9 +784,11 @@ static int ses_intf_add(struct device *cdev, buf = NULL; } page2_not_supported: - scomp = kcalloc(components, sizeof(struct ses_component), GFP_KERNEL); - if (!scomp) - goto err_free; + if (components > 0) { + scomp = kcalloc(components, sizeof(struct ses_component), GFP_KERNEL); + if (!scomp) + goto err_free; + } edev = enclosure_register(cdev->parent, dev_name(&sdev->sdev_gendev), components, &ses_enclosure_callbacks); @@ -843,7 +868,8 @@ static void ses_intf_remove_enclosure(struct scsi_device *sdev) kfree(ses_dev->page2); kfree(ses_dev); - kfree(edev->component[0].scratch); + if (edev->components) + kfree(edev->component[0].scratch); put_device(&edev->edev); enclosure_unregister(edev); diff --git a/drivers/scsi/snic/snic_disc.c b/drivers/scsi/snic/snic_disc.c index 69c5e26a9d5b381a5f216c1bfbdbb55a8d30522c..02b80291c1360b8285c58a2fcb782cfddd220a95 100644 --- a/drivers/scsi/snic/snic_disc.c +++ b/drivers/scsi/snic/snic_disc.c @@ -320,7 +320,7 @@ snic_tgt_create(struct snic *snic, struct snic_tgt_id *tgtid) spin_lock_irqsave(snic->shost->host_lock, flags); list_del(&tgt->list); spin_unlock_irqrestore(snic->shost->host_lock, flags); - kfree(tgt); + put_device(&tgt->dev); tgt = NULL; return tgt; diff --git a/drivers/scsi/stex.c b/drivers/scsi/stex.c index 124a5d0ec05cad5bb5c907a01315837e6d7d6f95..b02f254ce40b74aa35ff0a9a5e81e813b46e580a 100644 --- a/drivers/scsi/stex.c +++ b/drivers/scsi/stex.c @@ -114,7 +114,9 @@ enum { TASK_ATTRIBUTE_HEADOFQUEUE = 0x1, TASK_ATTRIBUTE_ORDERED = 0x2, TASK_ATTRIBUTE_ACA = 0x4, +}; +enum { SS_STS_NORMAL = 0x80000000, SS_STS_DONE = 0x40000000, SS_STS_HANDSHAKE = 0x20000000, @@ -126,7 +128,9 @@ enum { SS_I2H_REQUEST_RESET = 0x2000, SS_MU_OPERATIONAL = 0x80000000, +}; +enum { STEX_CDB_LENGTH = 16, STATUS_VAR_LEN = 128, diff --git a/drivers/scsi/storvsc_drv.c b/drivers/scsi/storvsc_drv.c index f3701b4e374b6e1d3c24eacd362b61aa681ab045..a28eb91dc2f3a4c7ce214aa7c8664fe817838e4d 100644 --- a/drivers/scsi/storvsc_drv.c +++ b/drivers/scsi/storvsc_drv.c @@ -1540,10 +1540,6 @@ static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd) */ static enum blk_eh_timer_return storvsc_eh_timed_out(struct scsi_cmnd *scmnd) { -#if IS_ENABLED(CONFIG_SCSI_FC_ATTRS) - if (scmnd->device->host->transportt == fc_transport_template) - return fc_eh_timed_out(scmnd); -#endif return BLK_EH_RESET_TIMER; } diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index b1b3eb1bd60b5a838bc98a08fe01a935d619b189..b749e69408614155f97719dce77b873329bf8ad5 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -11256,5 +11256,6 @@ EXPORT_SYMBOL_GPL(ufshcd_init); MODULE_AUTHOR("Santosh Yaragnavi "); MODULE_AUTHOR("Vinayak Holikatti "); MODULE_DESCRIPTION("Generic UFS host controller driver Core"); +MODULE_SOFTDEP("pre: governor_simpleondemand"); MODULE_LICENSE("GPL"); MODULE_VERSION(UFSHCD_DRIVER_VERSION); diff --git a/drivers/scsi/virtio_scsi.c b/drivers/scsi/virtio_scsi.c index 50e87823baab4b7c5dd7b9dcb76f4941bac0d21c..0b45424e7ca58ad8c28cba810bad2987e41e7c15 100644 --- a/drivers/scsi/virtio_scsi.c +++ b/drivers/scsi/virtio_scsi.c @@ -853,6 +853,7 @@ static int virtscsi_probe(struct virtio_device *vdev) /* We need to know how many queues before we allocate. */ num_queues = virtscsi_config_get(vdev, num_queues) ? : 1; + num_queues = min_t(unsigned int, nr_cpu_ids, num_queues); num_targets = virtscsi_config_get(vdev, max_target) + 1; diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig index fabba17e9d65b6976c1ad17de08406288d4e5df2..7ec158e2acf91ff659d7d5e621814b1e366bce7e 100644 --- a/drivers/soc/fsl/qe/Kconfig +++ b/drivers/soc/fsl/qe/Kconfig @@ -37,6 +37,7 @@ config QE_TDM config QE_USB bool + depends on QUICC_ENGINE default y if USB_FSL_QE help QE USB Controller support diff --git a/drivers/soc/qcom/glink_probe.c b/drivers/soc/qcom/glink_probe.c index 1d0e7a1c143ac702ed43d0deaf3653435d45c29f..dca4339eb2c0238f14052e350acbf3466063cb74 100644 --- a/drivers/soc/qcom/glink_probe.c +++ b/drivers/soc/qcom/glink_probe.c @@ -128,7 +128,7 @@ static int glink_ssr_ssr_cb(struct notifier_block *this, if (!dev || !ssr->ept) goto out; - if (code == SUBSYS_AFTER_SHUTDOWN) { + if (code == SUBSYS_AFTER_SHUTDOWN || code == SUBSYS_POWERUP_FAILURE) { ssr->seq_num++; reinit_completion(&ssr->completion); diff --git a/drivers/soc/qcom/msm_minidump.c b/drivers/soc/qcom/msm_minidump.c index a2de6fc57d71a441e32b93f431ca181e902a7934..ae8ddada405639d2e97fd83c30ba6061d2a4adde 100644 --- a/drivers/soc/qcom/msm_minidump.c +++ b/drivers/soc/qcom/msm_minidump.c @@ -542,7 +542,7 @@ static int __init msm_minidump_init(void) } /*Check global minidump support initialization */ - if (!md_global_toc->md_toc_init) { + if (size < sizeof(*md_global_toc) || !md_global_toc->md_toc_init) { pr_err("System Minidump TOC not initialized\n"); return -ENODEV; } diff --git a/drivers/soc/qcom/qsee_ipc_irq_bridge.c b/drivers/soc/qcom/qsee_ipc_irq_bridge.c index cdd28554dcc4901a4f54c7ad6cad7ed68f99e936..d5ac4efa9ce5e32c40d10d5bc025c17fd6cdcb0d 100644 --- a/drivers/soc/qcom/qsee_ipc_irq_bridge.c +++ b/drivers/soc/qcom/qsee_ipc_irq_bridge.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -125,7 +126,6 @@ static int qiib_driver_data_init(void) */ static void qiib_driver_data_deinit(void) { - qiib_cleanup(); if (!qiib_info->log_ctx) ipc_log_context_destroy(qiib_info->log_ctx); kfree(qiib_info); @@ -433,8 +433,10 @@ static void qiib_cleanup(void) } mutex_unlock(&qiib_info->list_lock); - if (!IS_ERR_OR_NULL(qiib_info->classp)) + if (!IS_ERR_OR_NULL(qiib_info->classp)) { class_destroy(qiib_info->classp); + qiib_info->classp = NULL; + } unregister_chrdev_region(MAJOR(qiib_info->dev_num), qiib_info->nports); } diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 3e1498dfc977a30c088d1cb949d7d4170e316a50..df62c4cf74b889caf6d4540b2a85e31489c2b358 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2009-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #define pr_fmt(fmt) "%s: " fmt, __func__ @@ -211,6 +212,14 @@ struct socinfo_v0_15 { uint32_t nmodem_supported; }; +struct socinfo_v0_16 { + struct socinfo_v0_15 v0_15; + __le32 feature_code; + __le32 pcode; + __le32 npartnamemap_offset; + __le32 nnum_partname_mapping; +}; + static union { struct socinfo_v0_1 v0_1; struct socinfo_v0_2 v0_2; @@ -227,10 +236,43 @@ static union { struct socinfo_v0_13 v0_13; struct socinfo_v0_14 v0_14; struct socinfo_v0_15 v0_15; + struct socinfo_v0_16 v0_16; } *socinfo; +#define PART_NAME_MAX 32 +struct socinfo_partinfo { + __le32 part_type; + char part_name[PART_NAME_MAX]; + __le32 part_name_len; +}; +struct socinfo_partinfo partinfo[SOCINFO_PART_MAX_PARTTYPE]; + /* max socinfo format version supported */ -#define MAX_SOCINFO_FORMAT SOCINFO_VERSION(0, 15) +#define MAX_SOCINFO_FORMAT SOCINFO_VERSION(0, 16) + +static const char * const hw_platform_feature_code[] = { + [SOCINFO_FC_UNKNOWN] = "Unknown", + [SOCINFO_FC_AA] = "AA", + [SOCINFO_FC_AB] = "AB", + [SOCINFO_FC_AC] = "AC", + [SOCINFO_FC_AD] = "AD", + [SOCINFO_FC_AE] = "AE", + [SOCINFO_FC_AF] = "AF", + [SOCINFO_FC_AG] = "AG", + [SOCINFO_FC_AH] = "AH", +}; + +#define SOCINFO_FC_INT_MASK 0x0f +static const char * const hw_platform_ifeature_code[] = { + [SOCINFO_FC_Y0 - SOCINFO_FC_Y0] = "Y0", + [SOCINFO_FC_Y1 - SOCINFO_FC_Y0] = "Y1", + [SOCINFO_FC_Y2 - SOCINFO_FC_Y0] = "Y2", + [SOCINFO_FC_Y3 - SOCINFO_FC_Y0] = "Y3", + [SOCINFO_FC_Y4 - SOCINFO_FC_Y0] = "Y4", + [SOCINFO_FC_Y5 - SOCINFO_FC_Y0] = "Y5", + [SOCINFO_FC_Y6 - SOCINFO_FC_Y0] = "Y6", + [SOCINFO_FC_Y7 - SOCINFO_FC_Y0] = "Y7", +}; #ifdef OPLUS_ARCH_EXTENDS static char *fake_cpu_id = "SM8150"; @@ -409,6 +451,9 @@ static struct msm_soc_info cpu_of_id[] = { /* QM215 ID */ [386] = {MSM_CPU_QM215, "QM215"}, + /* QCM2150 ID */ + [436] = {MSM_CPU_QCM2150, "QCM2150"}, + /* 8953 ID */ [293] = {MSM_CPU_8953, "MSM8953"}, [304] = {MSM_CPU_8953, "APQ8053"}, @@ -454,6 +499,7 @@ static struct msm_soc_info cpu_of_id_2065c = { static enum msm_cpu cur_cpu; static int current_image; static uint32_t socinfo_format; +static const char *sku; static struct socinfo_v0_1 dummy_socinfo = { .format = SOCINFO_VERSION(0, 1), @@ -750,6 +796,117 @@ static uint32_t socinfo_get_nmodem_supported(void) : 0; } +static uint32_t socinfo_get_feature_code_id(void) +{ + uint32_t fc_id; + + if (!socinfo || socinfo_format < SOCINFO_VERSION(0, 16)) + return SOCINFO_FC_UNKNOWN; + + fc_id = le32_to_cpu(socinfo->v0_16.feature_code); + if (fc_id <= SOCINFO_FC_UNKNOWN || fc_id >= SOCINFO_FC_INT_RESERVE) + return SOCINFO_FC_UNKNOWN; + + return fc_id; +} + +static const char *socinfo_get_feature_code_mapping(void) +{ + uint32_t id = socinfo_get_feature_code_id(); + + if (id > SOCINFO_FC_UNKNOWN && id < SOCINFO_FC_EXT_RESERVE) + return hw_platform_feature_code[id]; + else if (id >= SOCINFO_FC_Y0 && id < SOCINFO_FC_INT_RESERVE) + return hw_platform_ifeature_code[id & SOCINFO_FC_INT_MASK]; + + return NULL; +} + +static uint32_t socinfo_get_pcode_id(void) +{ + uint32_t pcode; + + if (!socinfo || socinfo_format < SOCINFO_VERSION(0, 16)) + return SOCINFO_PCODE_RESERVE; + + pcode = le32_to_cpu(socinfo->v0_16.pcode); + if (pcode <= SOCINFO_PCODE_UNKNOWN || pcode >= SOCINFO_PCODE_RESERVE) + return SOCINFO_PCODE_UNKNOWN; + + return pcode; +} + +int socinfo_get_feature_code(void) +{ + if (socinfo_format < SOCINFO_VERSION(0, 16)) { + pr_warn("socinfo: Feature code is not supported by bootloaders\n"); + return -EINVAL; + } + + return socinfo_get_feature_code_id(); +} +EXPORT_SYMBOL(socinfo_get_feature_code); + +int socinfo_get_pcode(void) +{ + if (socinfo_format < SOCINFO_VERSION(0, 16)) { + pr_warn("socinfo: pcode is not supported by bootloaders\n"); + return -EINVAL; + } + + return socinfo_get_pcode_id(); +} +EXPORT_SYMBOL(socinfo_get_pcode); + +char *socinfo_get_partinfo_details(unsigned int part_id) +{ + if (socinfo_format < SOCINFO_VERSION(0, 16) || + part_id > SOCINFO_PART_MAX_PARTTYPE) + return NULL; + + return partinfo[part_id].part_name; +} +EXPORT_SYMBOL(socinfo_get_partinfo_details); + +void socinfo_enumerate_partinfo_details(void) +{ + unsigned int partinfo_array_offset; + unsigned int nnum_partname_mapping; + void *ptr = socinfo; + int i, part_type, part_name_len; + + if (socinfo_format < SOCINFO_VERSION(0, 16)) + return; + + partinfo_array_offset = + le32_to_cpu(socinfo->v0_16.npartnamemap_offset); + nnum_partname_mapping = + le32_to_cpu(socinfo->v0_16.nnum_partname_mapping); + + if (nnum_partname_mapping > SOCINFO_PART_MAX_PARTTYPE) { + pr_warn("socinfo: Mismatch between bootloaders and hlos\n"); + return; + } + + ptr += partinfo_array_offset; + for (i = 0; i < nnum_partname_mapping; i++) { + part_type = get_unaligned_le32(ptr); + if (part_type > SOCINFO_PART_MAX_PARTTYPE) + pr_warn("socinfo: part type mismatch\n"); + + partinfo[part_type].part_type = part_type; + ptr += sizeof(u32); + strscpy(partinfo[part_type].part_name, ptr, PART_NAME_MAX); + part_name_len = strlen(partinfo[part_type].part_name); + ptr += PART_NAME_MAX; + if (part_name_len != get_unaligned_le32(ptr)) + pr_warn("socinfo: part info string length mismatch\n"); + + partinfo[part_type].part_name_len = part_name_len; + ptr += sizeof(u32); + } +} + enum pmic_model socinfo_get_pmic_model(void) { return socinfo ? @@ -1081,6 +1238,34 @@ msm_get_nmodem_supported(struct device *dev, socinfo_get_nmodem_supported()); } +static ssize_t +msm_get_sku(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%s\n", + sku ? sku : "Unknown"); +} + +static ssize_t +msm_get_pcode(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "0x%x\n", socinfo_get_pcode_id()); +} + +static ssize_t +msm_get_feature_code(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + const char *feature_code = socinfo_get_feature_code_mapping(); + + return scnprintf(buf, PAGE_SIZE, "%s\n", + feature_code ? feature_code : "Unknown"); +} + static ssize_t msm_get_pmic_model(struct device *dev, struct device_attribute *attr, @@ -1396,6 +1581,15 @@ static struct device_attribute msm_soc_attr_nmodem_supported = __ATTR(nmodem_supported, 0444, msm_get_nmodem_supported, NULL); +static struct device_attribute msm_soc_attr_sku = + __ATTR(sku, 0444, msm_get_sku, NULL); + +static struct device_attribute msm_soc_attr_feature_code = + __ATTR(feature_code, 0444, msm_get_feature_code, NULL); + +static struct device_attribute msm_soc_attr_pcode = + __ATTR(pcode, 0444, msm_get_pcode, NULL); + static struct device_attribute msm_soc_attr_pmic_model = __ATTR(pmic_model, 0444, msm_get_pmic_model, NULL); @@ -1553,6 +1747,10 @@ static void * __init setup_dummy_socinfo(void) dummy_socinfo.id = 386; strlcpy(dummy_socinfo.build_id, "qm215 - ", sizeof(dummy_socinfo.build_id)); + } else if (early_machine_is_qcm2150()) { + dummy_socinfo.id = 436; + strlcpy(dummy_socinfo.build_id, "qcm2150 - ", + sizeof(dummy_socinfo.build_id)); } else if (early_machine_is_msm8953()) { dummy_socinfo.id = 293; strlcpy(dummy_socinfo.build_id, "msm8953 - ", @@ -1582,6 +1780,13 @@ static void __init populate_soc_sysfs_files(struct device *msm_soc_device) device_create_file(msm_soc_device, &images); switch (socinfo_format) { + case SOCINFO_VERSION(0, 16): + device_create_file(msm_soc_device, + &msm_soc_attr_sku); + device_create_file(msm_soc_device, + &msm_soc_attr_feature_code); + device_create_file(msm_soc_device, + &msm_soc_attr_pcode); case SOCINFO_VERSION(0, 15): device_create_file(msm_soc_device, &msm_soc_attr_nmodem_supported); @@ -1880,6 +2085,33 @@ static void socinfo_print(void) socinfo->v0_15.nmodem_supported); break; + case SOCINFO_VERSION(0, 16): + pr_info("v%u.%u, id=%u, ver=%u.%u, raw_id=%u, raw_ver=%u, hw_plat=%u, hw_plat_ver=%u\n accessory_chip=%u, hw_plat_subtype=%u, pmic_model=%u, pmic_die_revision=%u foundry_id=%u serial_number=%u num_pmics=%u chip_family=0x%x raw_device_family=0x%x raw_device_number=0x%x nproduct_id=0x%x num_clusters=0x%x ncluster_array_offset=0x%x num_subset_parts=0x%x nsubset_parts_array_offset=0x%x nmodem_supported=0x%x feature_code=0x%x pcode=0x%x sku=%s\n", + f_maj, f_min, socinfo->v0_1.id, v_maj, v_min, + socinfo->v0_2.raw_id, socinfo->v0_2.raw_version, + socinfo->v0_3.hw_platform, + socinfo->v0_4.platform_version, + socinfo->v0_5.accessory_chip, + socinfo->v0_6.hw_platform_subtype, + socinfo->v0_7.pmic_model, + socinfo->v0_7.pmic_die_revision, + socinfo->v0_9.foundry_id, + socinfo->v0_10.serial_number, + socinfo->v0_11.num_pmics, + socinfo->v0_12.chip_family, + socinfo->v0_12.raw_device_family, + socinfo->v0_12.raw_device_number, + socinfo->v0_13.nproduct_id, + socinfo->v0_14.num_clusters, + socinfo->v0_14.ncluster_array_offset, + socinfo->v0_14.num_subset_parts, + socinfo->v0_14.nsubset_parts_array_offset, + socinfo->v0_15.nmodem_supported, + socinfo->v0_16.feature_code, + socinfo->v0_16.pcode, + sku ? sku : "Unknown"); + break; + default: pr_err("Unknown format found: v%u.%u\n", f_maj, f_min); break; @@ -1912,6 +2144,7 @@ int __init socinfo_init(void) static bool socinfo_init_done; size_t size; uint32_t soc_info_id; + const char *machine, *fc; if (socinfo_init_done) return 0; @@ -1931,6 +2164,14 @@ int __init socinfo_init(void) (!cpu_of_id[soc_info_id].soc_id_string)) pr_warn("New IDs added! ID => CPU mapping needs an update.\n"); + if (socinfo_format >= SOCINFO_VERSION(0, 16)) { + socinfo_enumerate_partinfo_details(); + machine = socinfo_get_id_string(); + fc = socinfo_get_feature_code_mapping(); + sku = kasprintf(GFP_KERNEL, "%s-%u-%s", + machine, socinfo_get_pcode(), fc); + } + cur_cpu = cpu_of_id[socinfo->v0_1.id].generic_soc_type; #ifdef OPLUS_ARCH_EXTENDS if (is_confidential()) { diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index 3f291db7b39a084ea6ab10ec23f812f618c0ad97..e3c69b623770841c438960724ca4a6699f453ee6 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -1255,13 +1255,9 @@ int bcm_qspi_probe(struct platform_device *pdev, res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mspi"); - if (res) { - qspi->base[MSPI] = devm_ioremap_resource(dev, res); - if (IS_ERR(qspi->base[MSPI])) - return PTR_ERR(qspi->base[MSPI]); - } else { - return 0; - } + qspi->base[MSPI] = devm_ioremap_resource(dev, res); + if (IS_ERR(qspi->base[MSPI])) + return PTR_ERR(qspi->base[MSPI]); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi"); if (res) { diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index 2ad7b3f3666be98b3495bc377e5223595e1189de..d4692f54492f43e4c252111c767e53ba87bec722 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #define HSSPI_GLOBAL_CTRL_REG 0x0 #define GLOBAL_CTRL_CS_POLARITY_SHIFT 0 @@ -161,6 +163,7 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) int step_size = HSSPI_BUFFER_LEN; const u8 *tx = t->tx_buf; u8 *rx = t->rx_buf; + u32 val = 0; bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); bcm63xx_hsspi_set_cs(bs, spi->chip_select, true); @@ -176,11 +179,16 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) step_size -= HSSPI_OPCODE_LEN; if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) || - (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) + (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) { opcode |= HSSPI_OP_MULTIBIT; - __raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT | - 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff, + if (t->rx_nbits == SPI_NBITS_DUAL) + val |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT; + if (t->tx_nbits == SPI_NBITS_DUAL) + val |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT; + } + + __raw_writel(val | 0xff, bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select)); while (pending > 0) { @@ -432,13 +440,17 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) if (ret) goto out_put_master; + pm_runtime_enable(&pdev->dev); + /* register and we are done */ ret = devm_spi_register_master(dev, master); if (ret) - goto out_put_master; + goto out_pm_disable; return 0; +out_pm_disable: + pm_runtime_disable(&pdev->dev); out_put_master: spi_master_put(master); out_disable_pll_clk: diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c index bfe5754768f9738c7e96d27ea8795685f17d7be8..cc6ec3fb5bfdf75b477893858407a4dfa02bad1f 100644 --- a/drivers/spi/spi-bcm63xx.c +++ b/drivers/spi/spi-bcm63xx.c @@ -134,7 +134,7 @@ enum bcm63xx_regs_spi { SPI_MSG_DATA_SIZE, }; -#define BCM63XX_SPI_MAX_PREPEND 15 +#define BCM63XX_SPI_MAX_PREPEND 7 #define BCM63XX_SPI_MAX_CS 8 #define BCM63XX_SPI_BUS_NUM 0 diff --git a/drivers/spi/spi-fsl-cpm.c b/drivers/spi/spi-fsl-cpm.c index 8f7b26ec181e2782c2e8fd0cbb4de7e4b3c89f89..0485593dc2f5b1fe4e9b8e451e34d5a57e1d46f6 100644 --- a/drivers/spi/spi-fsl-cpm.c +++ b/drivers/spi/spi-fsl-cpm.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "spi-fsl-cpm.h" #include "spi-fsl-lib.h" @@ -124,6 +125,21 @@ int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi, mspi->rx_dma = mspi->dma_dummy_rx; mspi->map_rx_dma = 0; } + if (t->bits_per_word == 16 && t->tx_buf) { + const u16 *src = t->tx_buf; + u16 *dst; + int i; + + dst = kmalloc(t->len, GFP_KERNEL); + if (!dst) + return -ENOMEM; + + for (i = 0; i < t->len >> 1; i++) + dst[i] = cpu_to_le16p(src + i); + + mspi->tx = dst; + mspi->map_tx_dma = 1; + } if (mspi->map_tx_dma) { void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */ @@ -177,6 +193,13 @@ void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi) if (mspi->map_rx_dma) dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE); mspi->xfer_in_progress = NULL; + + if (t->bits_per_word == 16 && t->rx_buf) { + int i; + + for (i = 0; i < t->len; i += 2) + le16_to_cpus(t->rx_buf + i); + } } EXPORT_SYMBOL_GPL(fsl_spi_cpm_bufs_complete); diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c index cd784552de7f15048537ddcd78cf43f8822bb12d..fd15b030b381515b97bfc7f148e3c0b7ea9857df 100644 --- a/drivers/spi/spi-fsl-spi.c +++ b/drivers/spi/spi-fsl-spi.c @@ -201,24 +201,6 @@ static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, return bits_per_word; } -static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, - struct spi_device *spi, - int bits_per_word) -{ - /* QE uses Little Endian for words > 8 - * so transform all words > 8 into 8 bits - * Unfortnatly that doesn't work for LSB so - * reject these for now */ - /* Note: 32 bits word, LSB works iff - * tfcr/rfcr is set to CPMFCR_GBL */ - if (spi->mode & SPI_LSB_FIRST && - bits_per_word > 8) - return -EINVAL; - if (bits_per_word > 8) - return 8; /* pretend its 8 bits */ - return bits_per_word; -} - static int fsl_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) { @@ -246,9 +228,6 @@ static int fsl_spi_setup_transfer(struct spi_device *spi, bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, mpc8xxx_spi, bits_per_word); - else if (mpc8xxx_spi->flags & SPI_QE) - bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, - bits_per_word); if (bits_per_word < 0) return bits_per_word; @@ -355,33 +334,66 @@ static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, static int fsl_spi_do_one_msg(struct spi_master *master, struct spi_message *m) { + struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); struct spi_device *spi = m->spi; struct spi_transfer *t, *first; unsigned int cs_change; const int nsecs = 50; - int status; + int status, last_bpw; + + /* + * In CPU mode, optimize large byte transfers to use larger + * bits_per_word values to reduce number of interrupts taken. + */ + list_for_each_entry(t, &m->transfers, transfer_list) { + if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { + if (t->len < 256 || t->bits_per_word != 8) + continue; + if ((t->len & 3) == 0) + t->bits_per_word = 32; + else if ((t->len & 1) == 0) + t->bits_per_word = 16; + } else { + /* + * CPM/QE uses Little Endian for words > 8 + * so transform 16 and 32 bits words into 8 bits + * Unfortnatly that doesn't work for LSB so + * reject these for now + * Note: 32 bits word, LSB works iff + * tfcr/rfcr is set to CPMFCR_GBL + */ + if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8) + return -EINVAL; + if (t->bits_per_word == 16 || t->bits_per_word == 32) + t->bits_per_word = 8; /* pretend its 8 bits */ + if (t->bits_per_word == 8 && t->len >= 256 && + (mpc8xxx_spi->flags & SPI_CPM1)) + t->bits_per_word = 16; + } + } /* Don't allow changes if CS is active */ - first = list_first_entry(&m->transfers, struct spi_transfer, - transfer_list); + cs_change = 1; list_for_each_entry(t, &m->transfers, transfer_list) { - if ((first->bits_per_word != t->bits_per_word) || - (first->speed_hz != t->speed_hz)) { + if (cs_change) + first = t; + cs_change = t->cs_change; + if (first->speed_hz != t->speed_hz) { dev_err(&spi->dev, - "bits_per_word/speed_hz should be same for the same SPI transfer\n"); + "speed_hz cannot change while CS is active\n"); return -EINVAL; } } + last_bpw = -1; cs_change = 1; status = -EINVAL; list_for_each_entry(t, &m->transfers, transfer_list) { - if (t->bits_per_word || t->speed_hz) { - if (cs_change) - status = fsl_spi_setup_transfer(spi, t); - if (status < 0) - break; - } + if (cs_change || last_bpw != t->bits_per_word) + status = fsl_spi_setup_transfer(spi, t); + if (status < 0) + break; + last_bpw = t->bits_per_word; if (cs_change) { fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); @@ -640,8 +652,14 @@ static struct spi_master * fsl_spi_probe(struct device *dev, if (mpc8xxx_spi->type == TYPE_GRLIB) fsl_spi_grlib_probe(dev); - master->bits_per_word_mask = - (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) & + if (mpc8xxx_spi->flags & SPI_CPM_MODE) + master->bits_per_word_mask = + (SPI_BPW_RANGE_MASK(4, 8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32)); + else + master->bits_per_word_mask = + (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)); + + master->bits_per_word_mask &= SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index ec2296a4c44ddc00fecc22bfda69458e6a9328b0..1ad4b69292ad8754605842c930b2b96d5e43419c 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -237,6 +237,18 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, return true; } +/* + * Note the number of natively supported chip selects for MX51 is 4. Some + * devices may have less actual SS pins but the register map supports 4. When + * using gpio chip selects the cs values passed into the macros below can go + * outside the range 0 - 3. We therefore need to limit the cs value to avoid + * corrupting bits outside the allocated locations. + * + * The simplest way to do this is to just mask the cs bits to 2 bits. This + * still allows all 4 native chip selects to work as well as gpio chip selects + * (which can use any of the 4 chip select configurations). + */ + #define MX51_ECSPI_CTRL 0x08 #define MX51_ECSPI_CTRL_ENABLE (1 << 0) #define MX51_ECSPI_CTRL_XCH (1 << 2) @@ -245,16 +257,16 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 -#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) +#define MX51_ECSPI_CTRL_CS(cs) ((cs & 3) << 18) #define MX51_ECSPI_CTRL_BL_OFFSET 20 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) #define MX51_ECSPI_CONFIG 0x0c -#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) -#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) -#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) -#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) -#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) +#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs & 3) + 0)) +#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs & 3) + 4)) +#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs & 3) + 8)) +#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs & 3) + 12)) +#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs & 3) + 20)) #define MX51_ECSPI_INT 0x10 #define MX51_ECSPI_INT_TEEN (1 << 0) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 1ca678bcb5279a62226fecb589ee936e6b8e9e77..1518a8bf49be13bc8ab00097513f022a52fc9b97 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -1003,23 +1003,8 @@ static int spi_qup_probe(struct platform_device *pdev) return -ENXIO; } - ret = clk_prepare_enable(cclk); - if (ret) { - dev_err(dev, "cannot enable core clock\n"); - return ret; - } - - ret = clk_prepare_enable(iclk); - if (ret) { - clk_disable_unprepare(cclk); - dev_err(dev, "cannot enable iface clock\n"); - return ret; - } - master = spi_alloc_master(dev, sizeof(struct spi_qup)); if (!master) { - clk_disable_unprepare(cclk); - clk_disable_unprepare(iclk); dev_err(dev, "cannot allocate master\n"); return -ENOMEM; } @@ -1065,6 +1050,19 @@ static int spi_qup_probe(struct platform_device *pdev) spin_lock_init(&controller->lock); init_completion(&controller->done); + ret = clk_prepare_enable(cclk); + if (ret) { + dev_err(dev, "cannot enable core clock\n"); + goto error_dma; + } + + ret = clk_prepare_enable(iclk); + if (ret) { + clk_disable_unprepare(cclk); + dev_err(dev, "cannot enable iface clock\n"); + goto error_dma; + } + iomode = readl_relaxed(base + QUP_IO_M_MODES); size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode); @@ -1094,7 +1092,7 @@ static int spi_qup_probe(struct platform_device *pdev) ret = spi_qup_set_state(controller, QUP_STATE_RESET); if (ret) { dev_err(dev, "cannot set RESET state\n"); - goto error_dma; + goto error_clk; } writel_relaxed(0, base + QUP_OPERATIONAL); @@ -1118,7 +1116,7 @@ static int spi_qup_probe(struct platform_device *pdev) ret = devm_request_irq(dev, irq, spi_qup_qup_irq, IRQF_TRIGGER_HIGH, pdev->name, controller); if (ret) - goto error_dma; + goto error_clk; pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); pm_runtime_use_autosuspend(dev); @@ -1133,11 +1131,12 @@ static int spi_qup_probe(struct platform_device *pdev) disable_pm: pm_runtime_disable(&pdev->dev); +error_clk: + clk_disable_unprepare(cclk); + clk_disable_unprepare(iclk); error_dma: spi_qup_release_dma(master); error: - clk_disable_unprepare(cclk); - clk_disable_unprepare(iclk); spi_master_put(master); return ret; } @@ -1250,17 +1249,21 @@ static int spi_qup_remove(struct platform_device *pdev) int ret; ret = pm_runtime_get_sync(&pdev->dev); - if (ret < 0) - return ret; - ret = spi_qup_set_state(controller, QUP_STATE_RESET); - if (ret) - return ret; + if (ret >= 0) { + ret = spi_qup_set_state(controller, QUP_STATE_RESET); + if (ret) + dev_warn(&pdev->dev, "failed to reset controller (%pe)\n", + ERR_PTR(ret)); - spi_qup_release_dma(master); + clk_disable_unprepare(controller->cclk); + clk_disable_unprepare(controller->iclk); + } else { + dev_warn(&pdev->dev, "failed to resume, skip hw disable (%pe)\n", + ERR_PTR(ret)); + } - clk_disable_unprepare(controller->cclk); - clk_disable_unprepare(controller->iclk); + spi_qup_release_dma(master); pm_runtime_put_noidle(&pdev->dev); pm_runtime_disable(&pdev->dev); diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c index 749288310c36c9b8d3fc25b6172335829ebe4d87..2989795272a163b55c27c6a13bc023f922df8c82 100644 --- a/drivers/spi/spi-tegra20-sflash.c +++ b/drivers/spi/spi-tegra20-sflash.c @@ -469,7 +469,11 @@ static int tegra_sflash_probe(struct platform_device *pdev) goto exit_free_master; } - tsd->irq = platform_get_irq(pdev, 0); + ret = platform_get_irq(pdev, 0); + if (ret < 0) + goto exit_free_master; + tsd->irq = ret; + ret = request_irq(tsd->irq, tegra_sflash_isr, 0, dev_name(&pdev->dev), tsd); if (ret < 0) { diff --git a/drivers/spmi/spmi.c b/drivers/spmi/spmi.c index ba12b9cfe4a01b8afbc8123765fe99a0c249a111..8cfb6535da9a76acf658d91ab9bd7fb8b037a2b8 100644 --- a/drivers/spmi/spmi.c +++ b/drivers/spmi/spmi.c @@ -347,7 +347,8 @@ static int spmi_drv_remove(struct device *dev) const struct spmi_driver *sdrv = to_spmi_driver(dev->driver); pm_runtime_get_sync(dev); - sdrv->remove(to_spmi_device(dev)); + if (sdrv->remove) + sdrv->remove(to_spmi_device(dev)); pm_runtime_put_noidle(dev); pm_runtime_disable(dev); diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c index 99a4656d113d5dc67233e3dfd24dc608638da257..832ee69f45f52202f8cb2a6a618f2ce1d4256ba8 100644 --- a/drivers/ssb/driver_chipcommon.c +++ b/drivers/ssb/driver_chipcommon.c @@ -119,7 +119,7 @@ void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc) { struct ssb_bus *bus = cc->dev->bus; - u32 uninitialized_var(tmp); + u32 tmp; if (cc->dev->id.revision < 6) { if (bus->bustype == SSB_BUSTYPE_SSB || @@ -149,7 +149,7 @@ static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc) /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */ static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max) { - int uninitialized_var(limit); + int limit; enum ssb_clksrc clocksrc; int divisor = 1; u32 tmp; diff --git a/drivers/staging/erofs/unzip_vle.c b/drivers/staging/erofs/unzip_vle.c index 83e4d9384bd2d5c523cf230735ef49e6a9fca3c5..7ccc4a18a900626942f76e43d9fd9230428eda35 100644 --- a/drivers/staging/erofs/unzip_vle.c +++ b/drivers/staging/erofs/unzip_vle.c @@ -675,6 +675,8 @@ static int z_erofs_do_read_page(struct z_erofs_vle_frontend *fe, cur = end - min_t(unsigned, offset + end - map->m_la, end); if (unlikely(!(map->m_flags & EROFS_MAP_MAPPED))) { zero_user_segment(page, cur, end); + ++spiltted; + tight = false; goto next_part; } diff --git a/drivers/staging/fw-api/fw/htc.h b/drivers/staging/fw-api/fw/htc.h index 348c719a72318debe3d139dfea26975e63f4be0c..8e7f13dc8b42e889f43880cbf890084f7ed4fe97 100644 --- a/drivers/staging/fw-api/fw/htc.h +++ b/drivers/staging/fw-api/fw/htc.h @@ -165,13 +165,17 @@ typedef PREPACK struct _HTC_FRAME_HDR{ /* base message ID header */ typedef PREPACK struct { - A_UINT32 MessageID : 16, - reserved : 16; + A_UINT32 MessageID: 16, + MetaData: 8, + reserved: 8; } POSTPACK HTC_UNKNOWN_MSG; #define HTC_UNKNOWN_MSG_MESSAGEID_LSB 0 #define HTC_UNKNOWN_MSG_MESSAGEID_MASK 0x0000ffff #define HTC_UNKNOWN_MSG_MESSAGEID_OFFSET 0x00000000 +#define HTC_UNKNOWN_MSG_METADATA_LSB 16 +#define HTC_UNKNOWN_MSG_METADATA_MASK 0X00ff0000 +#define HTC_UNKNOWN_MSG_METADATA_OFFSET 0x00000000 /* HTC ready message * direction : target-to-host */ diff --git a/drivers/staging/fw-api/fw/htc_services.h b/drivers/staging/fw-api/fw/htc_services.h index ce2fcf85a2ff253d3bae71fa9e9eea33bf4ee6db..50d57596a0b0cea194a0e7cf80b40ab48b1d5223 100644 --- a/drivers/staging/fw-api/fw/htc_services.h +++ b/drivers/staging/fw-api/fw/htc_services.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012, 2014-2017, 2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -61,7 +61,10 @@ typedef enum { #define WMI_CONTROL_SVC_WMAC2 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,6) #define WMI_CONTROL_DIAG_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,7) #define WMI_CONTROL_DBR_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,8) -#define WMI_MAX_SERVICES 9 +/* WMI_CONTROL_SVC_WMAC3,4: WMI service for MACs 3 and 4 (where applicable) */ +#define WMI_CONTROL_SVC_WMAC3 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,9) +#define WMI_CONTROL_SVC_WMAC4 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,10) +#define WMI_MAX_SERVICES 11 #define NMI_CONTROL_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,0) #define NMI_DATA_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,1) diff --git a/drivers/staging/fw-api/fw/htt.h b/drivers/staging/fw-api/fw/htt.h index 3c36a13fb893fcd91d29cf913f345c2a4f45fc96..0b6c085ad6236f1a15a6cb4661a5afc7e2518558 100644 --- a/drivers/staging/fw-api/fw/htt.h +++ b/drivers/staging/fw-api/fw/htt.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -239,9 +239,25 @@ * 3.112 Add logical_link_id field in rx_peer_metadata_v1. * 3.113 Add add rx msdu,mpdu,ppdu fields in rx_ring_selection_cfg_t * 3.114 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET def. + * 3.115 Add HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP and + * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE msg defs. + * 3.116 Add HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE flag. + * 3.117 Add HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND def. + * 3.118 Add HTT_T2H_MSG_TYPE_RX_DATA_IND and _SOFT_UMAC_TX_COMPL_IND defs. + * 3.119 Add RX_PEER_META_DATA V1A and V1B defs. + * 3.120 Add HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND, _RESP defs. + * 3.121 Add HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND def. + * 3.122 Add is_umac_hang flag in H2T UMAC_HANG_RECOVERY_SOC_START_PRE_RESET msg + * 3.123 Add HTT_OPTION_TLV_TCL_METADATA_V21 def. + * 3.124 Add HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT def. + * 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2. + * 3.126 Add HTT_RXDATA_ERR_INVALID_PEER def. + * 3.127 Add transmit_count fields in htt_tx_wbm_completion_vX structs. + * 3.128 Add H2T TX_LATENCY_STATS_CFG + T2H TX_LATENCY_STATS_PERIODIC_IND + * msg defs */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 114 +#define HTT_CURRENT_VERSION_MINOR 128 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -554,10 +570,21 @@ PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t { * supported by the host. If the target doesn't provide a * HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the VERSION_CONF message, it * is implicitly understood that the V1 TCL metadata shall be used. + * + * Feb 2023: Added version HTT_OPTION_TLV_TCL_METADATA_V21 = 21 + * read as version 2.1. We added support for Dynamic AST Index Allocation + * for Alder+Pine in version 2.1. For HTT_OPTION_TLV_TCL_METADATA_V2 = 2 + * we will retain older behavior of making sure the AST Index for SAWF + * in Pine is allocated using wifitool ath2 setUnitTestCmd 0x48 2 536 1 + * and the FW will crash in wal_tx_de_fast.c. For version 2.1 and + * above we will use htt_tx_tcl_svc_class_id_metadata.ast_index + * in TCLV2 command and do the dynamic AST allocations. */ enum HTT_OPTION_TLV_TCL_METADATA_VER_VALUES { HTT_OPTION_TLV_TCL_METADATA_V1 = 1, HTT_OPTION_TLV_TCL_METADATA_V2 = 2, + /* values 3-20 reserved */ + HTT_OPTION_TLV_TCL_METADATA_V21 = 21, }; PREPACK struct htt_option_tlv_tcl_metadata_ver_t { @@ -771,6 +798,21 @@ typedef enum { HTT_STATS_PEER_AX_OFDMA_STATS_TAG = 174, /* htt_peer_ax_ofdma_stats_tlv */ HTT_STATS_TX_PDEV_MU_EDCA_PARAMS_STATS_TAG = 175, /* htt_tx_pdev_mu_edca_params_stats_tlv_v */ HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, /* htt_pdev_mbssid_ctrl_frame_stats_tlv */ + HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */ + HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG = 178, /* htt_tx_pdev_stats_mlo_txop_abort_tlv_v */ + HTT_STATS_UMAC_SSR_TAG = 179, /* htt_umac_ssr_stats_tlv */ + HTT_STATS_PEER_BE_OFDMA_STATS_TAG = 180, /* htt_peer_be_ofdma_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_TRIGGER_TAG = 181, /* htt_mlo_umac_ssr_trigger_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_CMN_TAG = 182, /* htt_mlo_umac_ssr_common_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_KPI_TSTMP_TAG = 183, /* htt_mlo_umac_ssr_kpi_tstamp_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_DBG_TAG = 184, /* htt_mlo_umac_ssr_dbg_tlv */ + HTT_STATS_MLO_UMAC_SSR_HANDSHAKE_TAG = 185, /* htt_mlo_umac_htt_handshake_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_MLO_TAG = 186, /* htt_mlo_umac_ssr_mlo_stats_tlv */ + HTT_STATS_PDEV_TDMA_TAG = 187, /* htt_pdev_tdma_stats_tlv */ + HTT_STATS_CODEL_SVC_CLASS_TAG = 188, /* htt_codel_svc_class_stats_tlv */ + HTT_STATS_CODEL_MSDUQ_TAG = 189, /* htt_codel_msduq_stats_tlv */ + HTT_STATS_MLO_SCHED_STATS_TAG = 190, /* htt_mlo_sched_stats_tlv */ + HTT_STATS_PDEV_MLO_IPC_STATS_TAG = 191, /* htt_pdev_mlo_ipc_stats_tlv */ HTT_STATS_MAX_TAG, @@ -841,6 +883,9 @@ enum htt_h2t_msg_type { HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ = 0x20, HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21, HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22, + HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23, + HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24, + HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG = 0x25, /* keep this last */ HTT_H2T_NUM_MSGS @@ -2556,7 +2601,8 @@ typedef struct { type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ svc_class_id: 8, - rsvd: 5, + ast_index: 3, /* Indicates to firmware the AST index to be used for Pine for AST Override */ + rsvd: 2, padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ } htt_tx_tcl_svc_class_id_metadata; @@ -2837,7 +2883,8 @@ PREPACK struct htt_tx_wbm_completion_v2 { tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */ reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ exception_frame: 1, - rsvd0: 12, /* For future use */ + transmit_count: 7, /* Refer to struct wbm_release_ring */ + rsvd0: 5, /* For future use */ used_by_hw4: 1, /* wbm_internal_error bit being used by HW */ rsvd1: 1; /* For future use */ A_UINT32 @@ -2863,6 +2910,8 @@ PREPACK struct htt_tx_wbm_completion_v2 { #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S 13 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_M 0x00020000 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S 17 +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M 0x01FC0000 +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S 18 /* DWORD 3 */ #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(_var) \ @@ -2895,6 +2944,16 @@ PREPACK struct htt_tx_wbm_completion_v2 { ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S)); \ } while (0) +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_GET(_var) \ + (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M) >> \ + HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S) + +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT, _val); \ + ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S)); \ + } while (0) + /** * @brief HTT TX WBM Completion from firmware to host (V3) * @details @@ -2920,7 +2979,8 @@ PREPACK struct htt_tx_wbm_completion_v3 { A_UINT32 reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ exception_frame: 1, - rsvd0: 27; /* For future use */ + transmit_count: 7, /* Refer to struct wbm_release_ring */ + rsvd0: 20; /* For future use */ A_UINT32 data0: 32; /* data0,1 and 2 changes based on tx_status type * if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP @@ -2937,13 +2997,17 @@ PREPACK struct htt_tx_wbm_completion_v3 { used_by_hw4: 12; /* Refer to struct wbm_release_ring */ } POSTPACK; - +/* DWORD 3 */ #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M 0x0001E000 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S 13 + +/* DWORD 4 */ #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M 0x0000000F #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S 0 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M 0x00000010 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S 4 +#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M 0x00000FE0 +#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S 5 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(_var) \ @@ -2976,6 +3040,16 @@ PREPACK struct htt_tx_wbm_completion_v3 { ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S)); \ } while (0) +#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_GET(_var) \ + (((_var) & HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M) >> \ + HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S) + +#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT, _val); \ + ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S)); \ + } while (0) + typedef enum { TX_FRAME_TYPE_UNDEFINED = 0, @@ -3016,7 +3090,11 @@ PREPACK struct htt_tx_wbm_transmit_status { * contains valid data. */ frame_type: 4, /* holds htt_tx_wbm_status_frame_type value */ - reserved: 4; + transmit_count_valid: 1, /* If this "transmit_count_valid" is set, the + * transmit_count field in struct + * htt_tx_wbm_completion_vx has valid data. + */ + reserved: 3; A_UINT32 ppdu_start_tsf: 32; /* PPDU Start timestamp added for multicast * packets in the wbm completion path @@ -3040,6 +3118,10 @@ PREPACK struct htt_tx_wbm_transmit_status { #define HTT_TX_WBM_COMPLETION_V2_MCAST_S 22 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M 0x00800000 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S 23 +#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M 0x0F000000 +#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S 24 +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M 0x10000000 +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S 28 /* DWORD 4 */ #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var) \ @@ -3113,6 +3195,26 @@ PREPACK struct htt_tx_wbm_transmit_status { ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S)); \ } while (0) +#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_GET(_var) \ + (((_var) & HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M) >> \ + HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S) + +#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE, _val); \ + ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S)); \ + +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(_var) \ + (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M) >> \ + HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S) + +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \ + ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S)); \ + } while (0) + + /** * @brief HTT TX WBM reinject status from firmware to host * @details @@ -5349,7 +5451,7 @@ enum htt_srng_ring_id { (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M) >> \ HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S) #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_SET(_var, _val) \ - do { \ + do { \ HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP, _val); \ ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S)); \ } while (0) @@ -7136,7 +7238,8 @@ PREPACK struct htt_tx_monitor_cfg_t { filter_in_tx_msdu_end_mgmt: 1, filter_in_tx_msdu_end_ctrl: 1, filter_in_tx_msdu_end_data: 1, - rsvd3: 17; + word_mask_compaction_enable: 1, + rsvd3: 16; A_UINT32 tlv_filter_mask_in0; A_UINT32 tlv_filter_mask_in1; A_UINT32 tlv_filter_mask_in2; @@ -7155,7 +7258,7 @@ PREPACK struct htt_tx_monitor_cfg_t { rsvd4: 10; A_UINT32 tx_queue_ext_v2_word_mask: 12, tx_peer_entry_v2_word_mask: 12, - rsvd5: 10; + rsvd5: 8; A_UINT32 fes_status_end_word_mask: 16, response_end_status_word_mask: 16; A_UINT32 fes_status_prot_word_mask: 11, @@ -7406,6 +7509,18 @@ PREPACK struct htt_tx_monitor_cfg_t { ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S)); \ } while (0) +#define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_M 0x00008000 +#define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S 15 +#define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_GET(_var) \ + (((_var) & HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_M) >> \ + HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S) +#define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE, _val); \ + ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S)); \ + } while (0) + + #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_M 0xffffffff #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S 0 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_GET(_var) \ @@ -8570,8 +8685,8 @@ PREPACK struct htt_h2t_msg_type_fisa_config_t { } fisa_control_bits; struct { A_UINT32 fisa_enable: 1, - fisa_aggr_limit: 4, - reserved: 27; + fisa_aggr_limit: 6, + reserved: 25; } fisa_control_bits_v2; A_UINT32 fisa_control_value; @@ -8791,7 +8906,7 @@ PREPACK struct htt_h2t_msg_type_fisa_config_t { } while (0) /* Dword 1: fisa_control_value fisa_aggr_limit */ -#define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M 0x0000001e +#define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M 0x0000007e #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S 1 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_GET(_var) \ (((_var) & HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M) >> \ @@ -9882,10 +9997,10 @@ PREPACK struct htt_h2t_sawf_def_queues_map_report_req { /** * @brief Format of shared memory between Host and Target - * for UMAC hang recovery feature messaging. + * for UMAC recovery feature messaging. * @details * This is shared memory between Host and Target allocated - * and used in chips where UMAC hang recovery feature is supported. + * and used in chips where UMAC recovery feature is supported. * This shared memory is allocated per SOC level by Host since each * SOC's target Q6FW needs to communicate independently to the Host * through its own shared memory. @@ -9903,11 +10018,12 @@ PREPACK struct htt_h2t_sawf_def_queues_map_report_req { * b'1 - do_post_reset_start * b'2 - do_post_reset_complete * b'3 - initiate_umac_recovery - * b'4:31 - rsvd_t2h + * b'4 - initiate_target_recovery_sync_using_umac + * b'5:31 - rsvd_t2h * dword2 - b'0 - pre_reset_done * b'1 - post_reset_start_done * b'2 - post_reset_complete_done - * b'3 - start_pre_reset + * b'3 - start_pre_reset (deprecated) * b'4:31 - rsvd_h2t */ PREPACK typedef struct { @@ -9918,18 +10034,23 @@ PREPACK typedef struct { * BIT [0] :- T2H msg to do pre-reset * BIT [1] :- T2H msg to do post-reset start * BIT [2] :- T2H msg to do post-reset complete - * BIT [3] :- T2H msg to initiate UMAC recovery sequence. - * This is needed to synchronize UMAC recovery - * across all SOCs. - * BIT [31 : 4] :- reserved + * BIT [3] :- T2H msg to indicate to Host that + * a trigger request for MLO UMAC Recovery + * is received for UMAC hang. + * BIT [4] :- T2H msg to indicate to Host that + * a trigger request for MLO UMAC Recovery + * is received for Mode-1 Target Recovery. + * BIT [31 : 5] :- reserved */ A_UINT32 t2h_msg; struct { - A_UINT32 do_pre_reset : 1, /* BIT [0] */ - do_post_reset_start : 1, /* BIT [1] */ - do_post_reset_complete : 1, /* BIT [2] */ - initiate_umac_recovery : 1, /* BIT [3] */ - rsvd_t2h : 28; /* BIT [31 : 4] */ + A_UINT32 + do_pre_reset: 1, /* BIT [0] */ + do_post_reset_start: 1, /* BIT [1] */ + do_post_reset_complete: 1, /* BIT [2] */ + initiate_umac_recovery: 1, /* BIT [3] */ + initiate_target_recovery_sync_using_umac: 1, /* BIT [4] */ + rsvd_t2h: 27; /* BIT [31:5] */ }; }; @@ -9938,10 +10059,7 @@ PREPACK typedef struct { * BIT [0] :- H2T msg to send pre-reset done * BIT [1] :- H2T msg to send post-reset start done * BIT [2] :- H2T msg to send post-reset complete done - * BIT [3] :- H2T msg to start pre-reset. - * This is expected only after T2H - * initiate_umac_recovery was received by Host - * from one of the SOCs. + * BIT [3] :- H2T msg to start pre-reset. This is deprecated. * BIT [31 : 4] :- reserved */ A_UINT32 h2t_msg; @@ -10000,7 +10118,7 @@ PREPACK typedef struct { #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M 0x00000008 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S 3 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_GET(word1) \ - (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M) >> \ + (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M) >> \ HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S) #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_SET(word1, _val) \ do { \ @@ -10008,6 +10126,18 @@ PREPACK typedef struct { ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S));\ } while (0) +/* dword1 - b'4 - initiate_target_recovery_sync_using_umac */ +#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M 0x00000010 +#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S 4 +#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_GET(word1) \ + (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M) >> \ + HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S) +#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_SET(word1, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC, _val); \ + ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S));\ + } while (0) + /* dword2 - b'0 - pre_reset_done */ #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M 0x00000001 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S 0 @@ -10171,12 +10301,13 @@ PREPACK typedef struct { * and HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP was sent * beforehand. * - * |31 9|8|7 0| + * |31 10|9|8|7 0| * |-----------------------------------------------------------| - * | reserved |I| msg_type | + * | reserved |U|I| msg_type | * |-----------------------------------------------------------| * Where: * I = is_initiator + * U = is_umac_hang * * The message is interpreted as follows: * dword0 - b'0:7 - msg_type @@ -10185,13 +10316,16 @@ PREPACK typedef struct { * execute the UMAC-recovery in context of the Initiator or * Non-Initiator. * The value zero indicates this target is Non-Initiator. - * b'9:31 - reserved. + * b'9 - is_umac_hang: indicates whether MLO UMAC recovery + * executed in context of UMAC hang or Target recovery. + * b'10:31 - reserved. */ PREPACK typedef struct { A_UINT32 msg_type : 8, is_initiator : 1, - reserved : 23; + is_umac_hang : 1, + reserved : 22; } POSTPACK htt_h2t_umac_hang_recovery_start_pre_reset_t; #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES \ @@ -10210,6 +10344,521 @@ PREPACK typedef struct { ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S));\ } while (0) +#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M 0x00000200 +#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S 9 +#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_GET(word0) \ + (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M) >> \ + HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S) +#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG, _val); \ + ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S));\ + } while (0) + + +/* + * @brief host -> target HTT RX_CCE_SUPER_RULE_SETUP message + * + * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP + * + * @details + * Host sends RX_CCE_SUPER_RULE setup message to target, in order to request, + * install or uninstall rx cce super rules to match certain kind of packets + * with specific parameters. Target sets up HW registers based on setup message + * and always confirms back to Host. + * + * The message would appear as follows: + * |31 24|23 16|15 8|7 0| + * |-----------------+-----------------+-----------------+-----------------| + * | reserved | operation | pdev_id | msg_type | + * |-----------------------------------------------------------------------| + * | cce_super_rule_param[0] | + * |-----------------------------------------------------------------------| + * | cce_super_rule_param[1] | + * |-----------------------------------------------------------------------| + * + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type: This will be set to + * 0x23 (HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP) + * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is for + * b'16:23 - operation: Identify operation to be taken, + * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST + * 1: HTT_RX_CCE_SUPER_RULE_INSTALL + * 2: HTT_RX_CCE_SUPER_RULE_RELEASE + * b'24:31 - reserved + * dword1~10 - cce_super_rule_param[0]: + * contains parameters used to setup RX_CCE_SUPER_RULE_0 + * dword11~20 - cce_super_rule_param[1]: + * contains parameters used to setup RX_CCE_SUPER_RULE_1 + * + * Each cce_super_rule_param structure would appear as follows: + * |31 24|23 16|15 8|7 0| + * |-----------------+-----------------+-----------------+-----------------| + * |src_ipv6_addr[3] |src_ipv6_addr[2] |src_ipv6_addr[1] |src_ipv6_addr[0] | + * |/src_ipv4_addr[3]|/src_ipv4_addr[2]|/src_ipv4_addr[1]|/src_ipv4_addr[0]| + * |-----------------------------------------------------------------------| + * |src_ipv6_addr[7] |src_ipv6_addr[6] |src_ipv6_addr[5] |src_ipv6_addr[4] | + * |-----------------------------------------------------------------------| + * |src_ipv6_addr[11]|src_ipv6_addr[10]|src_ipv6_addr[9] |src_ipv6_addr[8] | + * |-----------------------------------------------------------------------| + * |src_ipv6_addr[15]|src_ipv6_addr[14]|src_ipv6_addr[13]|src_ipv6_addr[12]| + * |-----------------------------------------------------------------------| + * |dst_ipv6_addr[3] |dst_ipv6_addr[2] |dst_ipv6_addr[1] |dst_ipv6_addr[0] | + * |/dst_ipv4_addr[3]|/dst_ipv4_addr[2]|/dst_ipv4_addr[1]|/dst_ipv4_addr[0]| + * |-----------------------------------------------------------------------| + * |dst_ipv6_addr[7] |dst_ipv6_addr[6] |dst_ipv6_addr[5] |dst_ipv6_addr[4] | + * |-----------------------------------------------------------------------| + * |dst_ipv6_addr[11]|dst_ipv6_addr[10]|dst_ipv6_addr[9] |dst_ipv6_addr[8] | + * |-----------------------------------------------------------------------| + * |dst_ipv6_addr[15]|dst_ipv6_addr[14]|dst_ipv6_addr[13]|dst_ipv6_addr[12]| + * |-----------------------------------------------------------------------| + * | is_valid | l4_type | l3_type | + * |-----------------------------------------------------------------------| + * | l4_dst_port | l4_src_port | + * |-----------------------------------------------------------------------| + * + * The cce_super_rule_param[0] structure is interpreted as follows: + * dword1 - b'0:7 - src_ipv6_addr[0]: b'120:127 of source ipv6 address + * (or src_ipv4_addr[0]: b'24:31 of source ipv4 address, + * in case of ipv4) + * b'8:15 - src_ipv6_addr[1]: b'112:119 of source ipv6 address + * (or src_ipv4_addr[1]: b'16:23 of source ipv4 address, + * in case of ipv4) + * b'16:23 - src_ipv6_addr[2]: b'104:111 of source ipv6 address + * (or src_ipv4_addr[2]: b'8:15 of source ipv4 address, + * in case of ipv4) + * b'24:31 - src_ipv6_addr[3]: b'96:103 of source ipv6 address + * (or src_ipv4_addr[3]: b'0:7 of source ipv4 address, + * in case of ipv4) + * dword2 - b'0:7 - src_ipv6_addr[4]: b'88:95 of source ipv6 address + * b'8:15 - src_ipv6_addr[5]: b'80:87 of source ipv6 address + * b'16:23 - src_ipv6_addr[6]: b'72:79 of source ipv6 address + * b'24:31 - src_ipv6_addr[7]: b'64:71 of source ipv6 address + * dword3 - b'0:7 - src_ipv6_addr[8]: b'56:63 of source ipv6 address + * b'8:15 - src_ipv6_addr[9]: b'48:55 of source ipv6 address + * b'16:23 - src_ipv6_addr[10]: b'40:47 of source ipv6 address + * b'24:31 - src_ipv6_addr[11]: b'32:39 of source ipv6 address + * dword4 - b'0:7 - src_ipv6_addr[12]: b'24:31 of source ipv6 address + * b'8:15 - src_ipv6_addr[13]: b'16:23 of source ipv6 address + * b'16:23 - src_ipv6_addr[14]: b'8:15 of source ipv6 address + * b'24:31 - src_ipv6_addr[15]: b'0:7 of source ipv6 address + * dword5 - b'0:7 - dst_ipv6_addr[0]: b'120:127 of destination ipv6 address + * (or dst_ipv4_addr[0]: b'24:31 of destination + * ipv4 address, in case of ipv4) + * b'8:15 - dst_ipv6_addr[1]: b'112:119 of destination ipv6 address + * (or dst_ipv4_addr[1]: b'16:23 of destination + * ipv4 address, in case of ipv4) + * b'16:23 - dst_ipv6_addr[2]: b'104:111 of destination ipv6 address + * (or dst_ipv4_addr[2]: b'8:15 of destination + * ipv4 address, in case of ipv4) + * b'24:31 - dst_ipv6_addr[3]: b'96:103 of destination ipv6 address + * (or dst_ipv4_addr[3]: b'0:7 of destination + * ipv4 address, in case of ipv4) + * dword6 - b'0:7 - dst_ipv6_addr[4]: b'88:95 of destination ipv6 address + * b'8:15 - dst_ipv6_addr[5]: b'80:87 of destination ipv6 address + * b'16:23 - dst_ipv6_addr[6]: b'72:79 of destination ipv6 address + * b'24:31 - dst_ipv6_addr[7]: b'64:71 of destination ipv6 address + * dword7 - b'0:7 - dst_ipv6_addr[8]: b'56:63 of destination ipv6 address + * b'8:15 - dst_ipv6_addr[9]: b'48:55 of destination ipv6 address + * b'16:23 - dst_ipv6_addr[10]: b'40:47 of destination ipv6 address + * b'24:31 - dst_ipv6_addr[11]: b'32:39 of destination ipv6 address + * dword8 - b'0:7 - dst_ipv6_addr[12]: b'24:31 of destination ipv6 address + * b'8:15 - dst_ipv6_addr[13]: b'16:23 of destination ipv6 address + * b'16:23 - dst_ipv6_addr[14]: b'8:15 of destination ipv6 address + * b'24:31 - dst_ipv6_addr[15]: b'0:7 of destination ipv6 address + * dword9 - b'0:15 - l3_type: type of L3 protocol, indicating L3 protocol used + * 0x0008: ipv4 + * 0xdd86: ipv6 + * b'16:23 - l4_type: type of L4 protocol, indicating L4 protocol used + * 6: TCP + * 17: UDP + * b'24:31 - is_valid: indicate whether this parameter is valid + * 0: invalid + * 1: valid + * dword10 - b'0:15 - l4_src_port: TCP/UDP source port field + * b'16:31 - l4_dst_port: TCP/UDP destination port field + * + * The cce_super_rule_param[1] structure is similar. + */ +#define HTT_RX_CCE_SUPER_RULE_SETUP_NUM 2 + +enum htt_rx_cce_super_rule_setup_operation { + HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST = 0, + HTT_RX_CCE_SUPER_RULE_INSTALL, + HTT_RX_CCE_SUPER_RULE_RELEASE, + + /* All operation should be before this */ + HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_OPERATION, +}; + +typedef struct { + union { + A_UINT8 src_ipv4_addr[4]; + A_UINT8 src_ipv6_addr[16]; + }; + union { + A_UINT8 dst_ipv4_addr[4]; + A_UINT8 dst_ipv6_addr[16]; + }; + A_UINT32 l3_type: 16, + l4_type: 8, + is_valid: 8; + A_UINT32 l4_src_port: 16, + l4_dst_port: 16; +} htt_rx_cce_super_rule_param_t; + +PREPACK struct htt_rx_cce_super_rule_setup_t { + A_UINT32 msg_type: 8, + pdev_id: 8, + operation: 8, + reserved: 8; + htt_rx_cce_super_rule_param_t + cce_super_rule_param[HTT_RX_CCE_SUPER_RULE_SETUP_NUM]; +} POSTPACK; + +#define HTT_RX_CCE_SUPER_RULE_SETUP_SZ \ + (sizeof(struct htt_rx_cce_super_rule_setup_t)) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M 0x0000ff00 +#define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S 8 +#define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M 0x00ff0000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S 16 +#define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M 0x0000ffff +#define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S 0 +#define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M 0x00ff0000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S 16 +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M 0xff000000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S 24 +#define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M 0x0000ffff +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S 0 +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M 0xffff0000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S 16 +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_GET(_ptr, _array) \ + do { \ + A_MEMCPY(_array, _ptr, 4); \ + } while (0) +#define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_SET(_ptr, _array) \ + do { \ + A_MEMCPY(_ptr, _array, 4); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_GET(_ptr, _array) \ + do { \ + A_MEMCPY(_array, _ptr, 16); \ + } while (0) +#define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_SET(_ptr, _array) \ + do { \ + A_MEMCPY(_ptr, _array, 16); \ + } while (0) + + +/** + * htt_h2t_primary_link_peer_status_type - + * Unique number for each status or reasons + * The status reasons can go up to 255 max + */ +enum htt_h2t_primary_link_peer_status_type { + /* Host Primary Link Peer migration Success */ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_OK = 0, + + + /* keep this last */ + /* Host Primary Link Peer migration Fail */ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_FAIL = 254, + HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_NUM_STATUS = 255 +}; + + +/** + * @brief host -> Primary peer migration completion message from host + * + * MSG_TYPE => HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP + * + * @details + * HTT_H2T_MSG_TYPE_PRIMARY_PEER_MIGRATE_RESP message is sent by host to + * target Confirming that primary link peer migration has completed, + * in response to a HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND + * message from the target. + * + * The message would appear as follows: + * + * |31 25|24|23 16|15 12|11 8|7 0| + * |----------------------------+----------+---------+--------------| + * | vdev ID | pdev ID | chip ID | msg type | + * |----------------------------+----------+---------+--------------| + * | ML peer ID | SW peer ID | + * |------------+--+------------+--------------------+--------------| + * | reserved |SV| src_info | status | + * |------------+--+---------------------------------+--------------| + * Where: + * SV = src_info_valid flag + * + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type: This will be set to 0x24 + * (HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP) + * b'8:11 - chip_id: Indicate which chip has been chosen as primary + * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen + * as primary + * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen + * as primary + * + * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer + * chosen as primary + * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the + * primary peer belongs. + * dword2 - b'0:7 - status: Indicates the status of Rx/TCL migration + * b'8:23 - src_info: Indicates New Virtual port number through + * which Rx Pipe connects to the correct PPE. + * b'24 - src_info_valid: Indicates src_info is valid. + */ + +typedef struct { + A_UINT32 msg_type: 8, /* bits 7:0 */ + chip_id: 4, /* bits 11:8 */ + pdev_id: 4, /* bits 15:12 */ + vdev_id: 16; /* bits 31:16 */ + A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */ + ml_peer_id: 16; /* bits 31:16 */ + A_UINT32 status: 8, /* bits 7:0 */ + src_info: 16, /* bits 23:8 */ + src_info_valid: 1, /* bit 24 */ + reserved: 7; /* bits 31:25 */ +} htt_h2t_primary_link_peer_migrate_resp_t; + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M 0x000000FF +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S 0 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M 0x00FFFF00 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S 8 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M 0x01000000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S 24 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S));\ + } while (0) + + +/** + * @brief host -> tgt msg to configure params for PPDU tx latency stats report + * + * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG + * + * @details + * HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG message is sent by the host to + * configure the parameters needed for FW to report PPDU tx latency stats + * for latency prediction in user space. + * + * The message would appear as follows: + * |31 28|27 12|11|10 8|7 0| + * |-----------+-------------------+--+-------+--------------| + * |granularity| periodic interval | E|vdev ID| msg type | + * |-----------+-------------------+--+-------+--------------| + * Where: E = enable + * + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type: This will be set to 0x25 + * (HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG) + * b'8:10 - vdev_id: Indicate which vdev is configuration is for + * b'11 - enable: Indicate this message is to enable/disable + * PPDU latency report from FW + * b'12:27 - periodic_interval: Indicate the report interval in MS + * b'28:31 - granularity: Indicate the granularity of the latency + * stats report, in ms + */ + +/* HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG */ +PREPACK struct htt_h2t_tx_latency_stats_cfg { + A_UINT32 msg_type :8, + vdev_id :3, + enable :1, + periodic_interval :16, + granularity :4; +} POSTPACK; + +#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M 0x00000700 +#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S 8 +#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_GET(_var) \ + (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M) >> \ + HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S) +#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S)); \ + } while (0) + +#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M 0x00000800 +#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S 11 +#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_GET(_var) \ + (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M) >> \ + HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S) +#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE, _val); \ + ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S)); \ + } while (0) + +#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M 0x0FFFF000 +#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S 12 +#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_GET(_var) \ + (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M) >> \ + HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S) +#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL, _val); \ + ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S)); \ + } while (0) + +#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M 0xF0000000 +#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S 28 +#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_GET(_var) \ + (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M) >> \ + HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S) +#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY, _val); \ + ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S)); \ + } while (0) + + /*=== target -> host messages ===============================================*/ @@ -10273,6 +10922,14 @@ enum htt_t2h_msg_type { HTT_T2H_PPDU_ID_FMT_IND = 0x30, HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN = 0x31, HTT_T2H_MSG_TYPE_RX_DELBA_EXTN = 0x32, + HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE = 0x33, + HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND = 0x34, /* DEPRECATED */ + HTT_T2H_MSG_TYPE_RX_DATA_IND = 0x35, + HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND = 0x36, + HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37, + HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND = 0x38, + HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT = 0x39, + HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND = 0x3a, HTT_T2H_MSG_TYPE_TEST, @@ -13536,6 +14193,132 @@ typedef enum { #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_SET HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_SET #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_GET HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_GET +/** + * @brief target -> host peer extended event for additional information + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT + * + * @details + * The following diagram shows the format of the peer extended message sent + * from the target to the host. This layout assumes the target operates + * as little-endian. + * + * This message always contains a SW peer ID. The main purpose of the + * SW peer ID is to tell the host what peer ID logical link id will be tagged + * with, so that the host can use that peer ID to determine which link + * transmitted the rx/tx frame. + * + * This message also contains MLO logical link id assigned to peer + * with sw_peer_id if it is valid ML link peer. + * + * + * |31 28|27 24|23 20|19|18 16|15 8|7 0| + * |---------------------------------------------------------------------------| + * | VDEV_ID | SW peer ID | msg type | + * |---------------------------------------------------------------------------| + * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | + * |---------------------------------------------------------------------------| + * | Reserved |V | LINK ID | MAC addr 5 | MAC addr 4 | + * |---------------------------------------------------------------------------| + * | Reserved | + * |---------------------------------------------------------------------------| + * | Reserved | + * |---------------------------------------------------------------------------| + * + * Where: + * LINK_ID (LOGICAL) - 3 Bits Bit16,17,18 of 3rd byte + * V (valid) - 1 Bit Bit19 of 3rd byte + * + * The following field definitions describe the format of the rx peer extended + * event messages sent from the target to the host. + * MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as an rx MLO peer extended information message + * Value: 0x39 (HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT) + * - PEER_ID (a.k.a. SW_PEER_ID) + * Bits 8:23 + * Purpose: The peer ID (index) that WAL has allocated + * Value: (rx) peer ID + * - VDEV_ID + * Bits 24:31 + * Purpose: Gives the vdev id of peer with peer_id as above. + * Value: VDEV ID of wal_peer + * + * - MAC_ADDR_L32 + * Bits 31:0 + * Purpose: Identifies which peer node the peer ID is for. + * Value: lower 4 bytes of peer node's MAC address + * + * - MAC_ADDR_U16 + * Bits 15:0 + * Purpose: Identifies which peer node the peer ID is for. + * Value: upper 2 bytes of peer node's MAC address + * Rest all bits are reserved for future expansion + * - LOGICAL_LINK_ID + * Bits 18:16 + * Purpose: Gives the logical link id of peer with peer_id as above. This + * field should be taken alongwith LOGICAL_LINK_ID_VALID + * Value: Logical link id used by wal_peer + * - LOGICAL_LINK_ID_VALID + * Bit 19 + * Purpose: Clarifies whether the logical link id of peer with peer_id as + * is valid or not + * Value: 0/1 indicating LOGICAL_LINK_ID is valid or not + */ +#define HTT_RX_PEER_EXTENDED_PEER_ID_M 0x00ffff00 +#define HTT_RX_PEER_EXTENDED_PEER_ID_S 8 +#define HTT_RX_PEER_EXTENDED_VDEV_ID_M 0xff000000 +#define HTT_RX_PEER_EXTENDED_VDEV_ID_S 24 + +#define HTT_RX_PEER_EXTENDED_MAC_ADDR_L32_M 0xffffffff +#define HTT_RX_PEER_EXTENDED_MAC_ADDR_L32_S 0 + +#define HTT_RX_PEER_EXTENDED_MAC_ADDR_U16_M 0x0000ffff +#define HTT_RX_PEER_EXTENDED_MAC_ADDR_U16_S 0 +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_M 0x00070000 +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S 16 +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_M 0x00080000 +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S 19 + + +#define HTT_RX_PEER_EXTENDED_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_PEER_ID, value); \ + (word) |= (value) << HTT_RX_PEER_EXTENDED_PEER_ID_S; \ + } while (0) +#define HTT_RX_PEER_EXTENDED_PEER_ID_GET(word) \ + (((word) & HTT_RX_PEER_EXTENDED_PEER_ID_M) >> HTT_RX_PEER_EXTENDED_PEER_ID_S) + +#define HTT_RX_PEER_EXTENDED_VDEV_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_VDEV_ID, value); \ + (word) |= (value) << HTT_RX_PEER_EXTENDED_VDEV_ID_S; \ + } while (0) +#define HTT_RX_PEER_EXTENDED_VDEV_ID_GET(word) \ + (((word) & HTT_RX_PEER_EXTENDED_VDEV_ID_M) >> HTT_RX_PEER_EXTENDED_VDEV_ID_S) + +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID, value); \ + (word) |= (value) << HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S; \ + } while (0) +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_GET(word) \ + (((word) & HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S) + +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID, value); \ + (word) |= (value) << HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S; \ + } while (0) +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_GET(word) \ + (((word) & HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_M) >> HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S) + +#define HTT_RX_PEER_EXTENDED_MAC_ADDR_OFFSET 4 /* bytes */ +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_OFFSET 8 /* bytes */ +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_OFFSET 8 /* bytes */ + +#define HTT_RX_PEER_EXTENDED_EVENT_BYTES 20 /* bytes */ + /** * @brief target -> host message specifying security parameters * @@ -14580,46 +15363,784 @@ PREPACK struct htt_tx_compl_ind_append_tx_tsf64 { /** - * @brief target -> host rate-control update indication message + * @brief target -> host software UMAC TX completion indication message * - * DEPRECATED (DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND) + * MSG_TYPE => HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND * * @details - * The following diagram shows the format of the RC Update message - * sent from the target to the host, while processing the tx-completion - * of a transmitted PPDU. + * The following diagram shows the format of the soft UMAC TX completion + * indication sent from the target to the host * - * |31 24|23 16|15 8|7 0| - * |-------------------------------------------------------------| - * | peer ID | vdev ID | msg_type | - * |-------------------------------------------------------------| - * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | - * |-------------------------------------------------------------| - * | reserved | num elems | MAC addr 5 | MAC addr 4 | - * |-------------------------------------------------------------| - * | : | - * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) : - * | : | - * |-------------------------------------------------------------| - * | : | - * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) : - * | : | - * |-------------------------------------------------------------| - * : : - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + * |31 30|29|28|27|26 20|19 17|16|15 12|11|10| 9|8|7 4|3 1|0| + * |-------------------------------------+----------------+------------| + * hdr: | rsvd | msdu_cnt | msg_type | + * pyld: |===================================================================| + * MSDU 0| buf addr low (bits 31:0) | + * |-----------------------------------------------+------+------------| + * | SW buffer cookie | RS | buf addr hi| + * |--------+--+--+-------------+--------+---------+------+------------| + * | rsvd0 | M| V| tx count | TID | SW peer ID | + * |--------+--+--+-------------+--------+----------------------+------| + * | frametype | TQM status number | RELR | + * |-----+-----+-----------------------------------+--+-+-+-----+------| + * |rsvd1| buffer timestamp | A|L|F| ACK RSSI | + * |-----+--+-------------------------+--+------+-----+--+-+-----+---+-| + * | rsvd2 | tones in RU |OF|tx MCS|txSGI|LC|S|PKTYP|BW |I| + * |--------+-------------------------+--+------+-----+--+-+-----+---+-| + * | PPDU transmission TSF | + * |-------------------------------------------------------------------| + * | rsvd3 | + * |===================================================================| + * MSDU 1| buf addr low (bits 31:0) | + * : ... : + * | rsvd3 | + * |===================================================================| + * etc. * + * Where: + * RS = release source + * V = valid + * M = multicast + * RELR = release reason + * F = first MSDU + * L = last MSDU + * A = MSDU is part of A-MSDU + * I = rate info valid + * PKTYP = packet type + * S = STBC + * LC = LDPC + * OF = OFDMA transmission */ +typedef enum { + /* 0 (REASON_FRAME_ACKED): + * Corresponds to tqm_release_reason = ; + * frame is removed because an ACK of BA for it was received. + */ + HTT_TX_MSDU_RELEASE_REASON_FRAME_ACKED, -typedef struct { - A_UINT32 rate_code; /* rate code, bw, chain mask sgi */ - A_UINT32 rate_code_flags; - A_UINT32 flags; /* Encodes information such as excessive - retransmission, aggregate, some info - from .11 frame control, - STBC, LDPC, (SGI and Tx Chain Mask - are encoded in ptx_rc->flags field), - AMPDU truncation (BT/time based etc.), - RTS/CTS attempt */ + /* 1 (REASON_REMOVE_CMD_FW): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command of type "Remove_mpdus" + * initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_FW, + + /* 2 (REASON_REMOVE_CMD_TX): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command of type + * "Remove_transmitted_mpdus" initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_TX, + + /* 3 (REASON_REMOVE_CMD_NOTX): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command of type + * "Remove_untransmitted_mpdus" initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_NOTX, + + /* 4 (REASON_REMOVE_CMD_AGED): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command of type "Remove_aged_mpdus" + * or "Remove_aged_msdus" initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_AGED, + + /* 5 (RELEASE_FW_REASON1): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command where fw indicated that + * remove reason is fw_reason1. + */ + HTT_TX_MSDU_RELEASE_FW_REASON1, + + /* 6 (RELEASE_FW_REASON2): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command where fw indicated that + * remove reason is fw_reason1. + */ + HTT_TX_MSDU_RELEASE_FW_REASON2, + + /* 7 (RELEASE_FW_REASON3): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command where fw indicated that + * remove reason is fw_reason1. + */ + HTT_TX_MSDU_RELEASE_FW_REASON3, + + /* 8 (REASON_REMOVE_CMD_DISABLEQ): + * Corresponds to tqm_release_reason = + * frame is removed because a remove command of type + * "remove_mpdus_and_disable_queue" or "remove_msdus_and_disable_flow" + * initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_DISABLEQ, + + /* 9 (REASON_DROP_MISC): + * Corresponds to sw_release_reason = Packet dropped by FW due to + * any discard reason that is not categorized as MSDU TTL expired. + * Examples: TXDE ENQ layer dropped the packet due to peer delete, + * tid delete, no resource credit available. + */ + HTT_TX_MSDU_RELEASE_REASON_DROP_MISC, + + /* 10 (REASON_DROP_TTL): + * Corresponds to sw_release_reason = Packet dropped by FW due to + * discard reason that frame is not transmitted due to MSDU TTL expired. + */ + HTT_TX_MSDU_RELEASE_REASON_DROP_TTL, + + /* 11 - available for use */ + /* 12 - available for use */ + /* 13 - available for use */ + /* 14 - available for use */ + /* 15 - available for use */ + + HTT_TX_MSDU_RELEASE_REASON_MAX = 16 +} htt_t2h_tx_msdu_release_reason_e; + +typedef enum { + /* 0 (RELEASE_SOURCE_FW): + * MSDU released by FW even before the frame was queued to TQM-L HW. + */ + HTT_TX_MSDU_RELEASE_SOURCE_FW, + + /* 1 (RELEASE_SOURCE_TQM_LITE): + * MSDU released by TQM-L HW. + */ + HTT_TX_MSDU_RELEASE_SOURCE_TQM_LITE, + + HTT_TX_MSDU_RELEASE_SOURCE_MAX = 8 +} htt_t2h_tx_msdu_release_source_e; + +struct htt_t2h_tx_buffer_addr_info { /* 2 words */ + A_UINT32 buffer_addr_31_0 : 32; /* [31:0] */ + A_UINT32 buffer_addr_39_32 : 8, /* [7:0] */ + /* release_source: + * holds a htt_t2h_tx_msdu_release_source_e enum value + */ + release_source : 3, /* [10:8] */ + sw_buffer_cookie : 21; /* [31:11] */ + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +/* member definitions of htt_t2h_tx_buffer_addr_info */ + +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M 0xFFFFFFFF +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S 0 + +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0, value); \ + (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S; \ + } while (0) +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_GET(word) \ + (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S) + +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M 0x000000FF +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S 0 + +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32, value); \ + (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S; \ + } while (0) +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_GET(word) \ + (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S) + +#define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M 0x00000700 +#define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S 8 + +#define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE, value); \ + (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S; \ + } while (0) +#define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_GET(word) \ + (((word) & HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M) >> HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S) + +#define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M 0xFFFFF800 +#define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S 11 + +#define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE, value); \ + (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S; \ + } while (0) +#define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_GET(word) \ + (((word) & HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M) >> HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S) + +struct htt_t2h_tx_rate_stats_info { /* 2 words */ + /* word 0 */ + A_UINT32 + /* tx_rate_stats_info_valid: + * Indicates if the tx rate stats below are valid. + */ + tx_rate_stats_info_valid : 1, /* [0] */ + /* transmit_bw: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Indicates the BW of the upcoming transmission that shall likely + * start in about 3 -4 us on the medium: + * + * + * + * + * + */ + transmit_bw : 3, /* [3:1] */ + /* transmit_pkt_type: + * same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * The packet type + * + * Type: enum Definition Name: PKT_TYPE_ENUM + * enum number enum name Description + * ------------------------------------ + * 0 dot11a 802.11a PPDU type + * 1 dot11b 802.11b PPDU type + * 2 dot11n_mm 802.11n Mixed Mode PPDU type + * 3 dot11ac 802.11ac PPDU type + * 4 dot11ax 802.11ax PPDU type + * 5 dot11ba 802.11ba (WUR) PPDU type + * 6 dot11be 802.11be PPDU type + * 7 dot11az 802.11az (ranging) PPDU type + */ + transmit_pkt_type : 4, /* [7:4] */ + /* transmit_stbc: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * When set, STBC transmission rate was used. + */ + transmit_stbc : 1, /* [8] */ + /* transmit_ldpc: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * When set, use LDPC transmission rates + */ + transmit_ldpc : 1, /* [9] */ + /* transmit_sgi: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * Legacy normal GI. Can also be used for HE + * Legacy short GI. Can also be used for HE + * HE related GI + * HE related GI + * + */ + transmit_sgi : 2, /* [11:10] */ + /* transmit_mcs: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * + * For details, refer to MCS_TYPE description + * + * Pkt_type Related definition of MCS_TYPE + * dot11b This field is the rate: + * 0: CCK 11 Mbps Long + * 1: CCK 5.5 Mbps Long + * 2: CCK 2 Mbps Long + * 3: CCK 1 Mbps Long + * 4: CCK 11 Mbps Short + * 5: CCK 5.5 Mbps Short + * 6: CCK 2 Mbps Short + * NOTE: The numbering here is NOT the same as the as MAC gives + * in the "rate" field in the SIG given to the PHY. + * The MAC will do an internal translation. + * + * Dot11a This field is the rate: + * 0: OFDM 48 Mbps + * 1: OFDM 24 Mbps + * 2: OFDM 12 Mbps + * 3: OFDM 6 Mbps + * 4: OFDM 54 Mbps + * 5: OFDM 36 Mbps + * 6: OFDM 18 Mbps + * 7: OFDM 9 Mbps + * NOTE: The numbering here is NOT the same as the as MAC gives + * in the "rate" field in the SIG given to the PHY. + * The MAC will do an internal translation. + * + * Dot11n_mm (mixed mode) This field represends the MCS. + * 0: HT MCS 0 (BPSK 1/2) + * 1: HT MCS 1 (QPSK 1/2) + * 2: HT MCS 2 (QPSK 3/4) + * 3: HT MCS 3 (16-QAM 1/2) + * 4: HT MCS 4 (16-QAM 3/4) + * 5: HT MCS 5 (64-QAM 2/3) + * 6: HT MCS 6 (64-QAM 3/4) + * 7: HT MCS 7 (64-QAM 5/6) + * NOTE: To get higher MCS's use the nss field to indicate the + * number of spatial streams. + * + * Dot11ac This field represends the MCS. + * 0: VHT MCS 0 (BPSK 1/2) + * 1: VHT MCS 1 (QPSK 1/2) + * 2: VHT MCS 2 (QPSK 3/4) + * 3: VHT MCS 3 (16-QAM 1/2) + * 4: VHT MCS 4 (16-QAM 3/4) + * 5: VHT MCS 5 (64-QAM 2/3) + * 6: VHT MCS 6 (64-QAM 3/4) + * 7: VHT MCS 7 (64-QAM 5/6) + * 8: VHT MCS 8 (256-QAM 3/4) + * 9: VHT MCS 9 (256-QAM 5/6) + * 10: VHT MCS 10 (1024-QAM 3/4) + * 11: VHT MCS 11 (1024-QAM 5/6) + * NOTE: There are several illegal VHT rates due to fractional + * number of bits per symbol. + * Below are the illegal rates for 4 streams and lower: + * 20 MHz, 1 stream, MCS 9 + * 20 MHz, 2 stream, MCS 9 + * 20 MHz, 4 stream, MCS 9 + * 80 MHz, 3 stream, MCS 6 + * 160 MHz, 3 stream, MCS 9 (Unsupported) + * 160 MHz, 4 stream, MCS 7 (Unsupported) + * + * dot11ax This field represends the MCS. + * 0: HE MCS 0 (BPSK 1/2) + * 1: HE MCS 1 (QPSK 1/2) + * 2: HE MCS 2 (QPSK 3/4) + * 3: HE MCS 3 (16-QAM 1/2) + * 4: HE MCS 4 (16-QAM 3/4) + * 5: HE MCS 5 (64-QAM 2/3) + * 6: HE MCS 6 (64-QAM 3/4) + * 7: HE MCS 7 (64-QAM 5/6) + * 8: HE MCS 8 (256-QAM 3/4) + * 9: HE MCS 9 (256-QAM 5/6) + * 10: HE MCS 10 (1024-QAM 3/4) + * 11: HE MCS 11 (1024-QAM 5/6) + * 12: HE MCS 12 (4096-QAM 3/4) + * 13: HE MCS 13 (4096-QAM 5/6) + * + * dot11ba This field is the rate: + * 0: LDR + * 1: HDR + * 2: Exclusive rate + */ + transmit_mcs : 4, /* [15:12] */ + /* ofdma_transmission: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Set when the transmission was an OFDMA transmission (DL or UL). + * + */ + ofdma_transmission : 1, /* [16] */ + /* tones_in_ru: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * The number of tones in the RU used. + * + */ + tones_in_ru : 12, /* [28:17] */ + rsvd2 : 3; /* [31:29] */ + + /* word 1 */ + /* ppdu_transmission_tsf: + * Based on a HWSCH configuration register setting, + * this field either contains: + * Lower 32 bits of the TSF, snapshot of this value when transmission + * of the PPDU containing the frame finished. + * OR + * Lower 32 bits of the TSF, snapshot of this value when transmission + * of the PPDU containing the frame started. + * + */ + A_UINT32 ppdu_transmission_tsf; + + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +/* member definitions of htt_t2h_tx_rate_stats_info */ + +#define HTT_TX_RATE_STATS_INFO_VALID_M 0x00000001 +#define HTT_TX_RATE_STATS_INFO_VALID_S 0 + +#define HTT_TX_RATE_STATS_INFO_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_VALID, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_VALID_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_VALID_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_VALID_M) >> HTT_TX_RATE_STATS_INFO_VALID_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M 0x0000000E +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S 1 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_BW, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M 0x000000F0 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S 4 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M 0x00000100 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S 8 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M 0x00000200 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S 9 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M 0x00000C00 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S 10 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M 0x0000F000 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S 12 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S) + +#define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M 0x00010000 +#define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S 16 + +#define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M) >> HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S) + +#define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M 0x1FFE0000 +#define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S 17 + +#define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TONES_IN_RU, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M) >> HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S) + +#define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M 0xFFFFFFFF +#define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S 0 + +#define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M) >> HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S) + +struct htt_t2h_tx_msdu_info { /* 8 words */ + /* words 0 + 1 */ + struct htt_t2h_tx_buffer_addr_info addr_info; + + /* word 2 */ + A_UINT32 + sw_peer_id : 16, + tid : 4, + transmit_cnt : 7, + valid : 1, + mcast : 1, + rsvd0 : 3; + + /* word 3 */ + A_UINT32 + release_reason : 4, /* Refer to htt_t2h_tx_msdu_release_reason_e */ + tqm_status_number : 24, + frame_type : 4; /* holds htt_tx_wbm_status_frame_type value */ + + /* word 4 */ + A_UINT32 + /* ack_frame_rssi: + * If this frame is removed as the result of the + * reception of an ACK or BA, this field indicates + * the RSSI of the received ACK or BA frame. + * When the frame is removed as result of a direct + * remove command from the SW, this field is set + * to 0x0 (which is never a valid value when real + * RSSI is available). + * Units: dB w.r.t noise floor + */ + ack_frame_rssi : 8, + first_msdu : 1, + last_msdu : 1, + msdu_part_of_amsdu : 1, + buffer_timestamp : 19, /* units = TU = 1024 microseconds */ + rsvd1 : 2; + + /* words 5 + 6 */ + struct htt_t2h_tx_rate_stats_info tx_rate_stats; + + /* word 7 */ + /* rsvd3: + * backup reserved field to add new parameters if [rsvd0, rsvd1, rsvd2] + * is not sufficient + */ + A_UINT32 rsvd3; + + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +/* member definitions of htt_t2h_tx_msdu_info */ + +#define HTT_TX_MSDU_INFO_SW_PEER_ID_M 0x0000FFFF +#define HTT_TX_MSDU_INFO_SW_PEER_ID_S 0 + +#define HTT_TX_MSDU_INFO_SW_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_SW_PEER_ID, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_SW_PEER_ID_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_SW_PEER_ID_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_SW_PEER_ID_M) >> HTT_TX_MSDU_INFO_SW_PEER_ID_S) + +#define HTT_TX_MSDU_INFO_TID_M 0x000F0000 +#define HTT_TX_MSDU_INFO_TID_S 16 + +#define HTT_TX_MSDU_INFO_TID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TID, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_TID_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_TID_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_TID_M) >> HTT_TX_MSDU_INFO_TID_S) + +#define HTT_TX_MSDU_INFO_TRANSMIT_CNT_M 0x07F00000 +#define HTT_TX_MSDU_INFO_TRANSMIT_CNT_S 20 + +#define HTT_TX_MSDU_INFO_TRANSMIT_CNT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TRANSMIT_CNT, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_TRANSMIT_CNT_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_TRANSMIT_CNT_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_TRANSMIT_CNT_M) >> HTT_TX_MSDU_INFO_TRANSMIT_CNT_S) + +#define HTT_TX_MSDU_INFO_VALID_M 0x08000000 +#define HTT_TX_MSDU_INFO_VALID_S 27 + +#define HTT_TX_MSDU_INFO_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_VALID, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_VALID_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_VALID_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_VALID_M) >> HTT_TX_MSDU_INFO_VALID_S) + +#define HTT_TX_MSDU_INFO_MCAST_M 0x10000000 +#define HTT_TX_MSDU_INFO_MCAST_S 28 + +#define HTT_TX_MSDU_INFO_MCAST_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MCAST, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_MCAST_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_MCAST_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_MCAST_M) >> HTT_TX_MSDU_INFO_MCAST_S) + +#define HTT_TX_MSDU_INFO_RELEASE_REASON_M 0x0000000F +#define HTT_TX_MSDU_INFO_RELEASE_REASON_S 0 + +#define HTT_TX_MSDU_INFO_RELEASE_REASON_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_RELEASE_REASON, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_RELEASE_REASON_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_RELEASE_REASON_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_RELEASE_REASON_M) >> HTT_TX_MSDU_INFO_RELEASE_REASON_S) + +#define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M 0x0FFFFFF0 +#define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S 4 + +#define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M) >> HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S) + +#define HTT_TX_MSDU_INFO_FRAME_TYPE_M 0xF0000000 +#define HTT_TX_MSDU_INFO_FRAME_TYPE_S 28 + +#define HTT_TX_MSDU_INFO_FRAME_TYPE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FRAME_TYPE, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_FRAME_TYPE_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_FRAME_TYPE_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_FRAME_TYPE_M) >> HTT_TX_MSDU_INFO_FRAME_TYPE_S) + +#define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M 0x000000FF +#define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S 0 + +#define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_ACK_FRAME_RSSI, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M) >> HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S) + +#define HTT_TX_MSDU_INFO_FIRST_MSDU_M 0x00000100 +#define HTT_TX_MSDU_INFO_FIRST_MSDU_S 8 + +#define HTT_TX_MSDU_INFO_FIRST_MSDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FIRST_MSDU, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_FIRST_MSDU_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_FIRST_MSDU_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_FIRST_MSDU_M) >> HTT_TX_MSDU_INFO_FIRST_MSDU_S) + +#define HTT_TX_MSDU_INFO_LAST_MSDU_M 0x00000200 +#define HTT_TX_MSDU_INFO_LAST_MSDU_S 9 + +#define HTT_TX_MSDU_INFO_LAST_MSDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_LAST_MSDU, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_LAST_MSDU_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_LAST_MSDU_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_LAST_MSDU_M) >> HTT_TX_MSDU_INFO_LAST_MSDU_S) + +#define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M 0x00000400 +#define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S 10 + +#define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M) >> HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S) + +#define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M 0x3FFFF800 +#define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S 11 + +#define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M) >> HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S) + +struct htt_t2h_soft_umac_tx_compl_ind { + A_UINT32 msg_type : 8, /* HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND */ + msdu_cnt : 8, /* min: 0, max: 255 */ + rsvd0 : 16; + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ + /* + * append here: + * struct htt_t2h_tx_msdu_info payload[1(or more)] + * for all the msdu's that are part of this completion. + */ +}; + +/* member definitions of htt_t2h_soft_umac_tx_compl_ind */ + +#define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M 0x0000FF00 +#define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S 8 + +#define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT, value); \ + (word) |= (value) << HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S; \ + } while (0) +#define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_GET(word) \ + (((word) & HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M) >> HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S) + + +/** + * @brief target -> host rate-control update indication message + * + * DEPRECATED (DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND) + * + * @details + * The following diagram shows the format of the RC Update message + * sent from the target to the host, while processing the tx-completion + * of a transmitted PPDU. + * + * |31 24|23 16|15 8|7 0| + * |-------------------------------------------------------------| + * | peer ID | vdev ID | msg_type | + * |-------------------------------------------------------------| + * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | + * |-------------------------------------------------------------| + * | reserved | num elems | MAC addr 5 | MAC addr 4 | + * |-------------------------------------------------------------| + * | : | + * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) : + * | : | + * |-------------------------------------------------------------| + * | : | + * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) : + * | : | + * |-------------------------------------------------------------| + * : : + * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + * + */ + +typedef struct { + A_UINT32 rate_code; /* rate code, bw, chain mask sgi */ + A_UINT32 rate_code_flags; + A_UINT32 flags; /* Encodes information such as excessive + retransmission, aggregate, some info + from .11 frame control, + STBC, LDPC, (SGI and Tx Chain Mask + are encoded in ptx_rc->flags field), + AMPDU truncation (BT/time based etc.), + RTS/CTS attempt */ A_UINT32 num_enqued; /* # of MPDUs (for non-AMPDU 1) for this rate */ A_UINT32 num_retries; /* Total # of transmission attempt for this rate */ @@ -16576,12 +18097,12 @@ enum htt_dbg_ext_stats_status { * to host ppdu stats indication message. * * - * |31 16|15 12|11 10|9 8|7 0 | - * |----------------------------------------------------------------------| + * |31 24|23 16|15 12|11 10|9 8|7 0 | + * |-----------------------------+-------+-------+--------+---------------| * | payload_size | rsvd |pdev_id|mac_id | msg type | - * |----------------------------------------------------------------------| - * | ppdu_id | - * |----------------------------------------------------------------------| + * |-------------+---------------+-------+-------+--------+---------------| + * | tgt_private | ppdu_id | + * |-------------+--------------------------------------------------------| * | Timestamp in us | * |----------------------------------------------------------------------| * | reserved | @@ -16621,8 +18142,9 @@ enum htt_dbg_ext_stats_status { #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_M 0xFFFF0000 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S 16 -#define HTT_T2H_PPDU_STATS_PPDU_ID_M 0xFFFFFFFF +#define HTT_T2H_PPDU_STATS_PPDU_ID_M 0x00FFFFFF #define HTT_T2H_PPDU_STATS_PPDU_ID_S 0 +/* bits 31:24 are used by the target for internal purposes */ #define HTT_T2H_PPDU_STATS_MAC_ID_SET(word, value) \ do { \ @@ -16653,7 +18175,7 @@ enum htt_dbg_ext_stats_status { #define HTT_T2H_PPDU_STATS_PPDU_ID_SET(word, value) \ do { \ - HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PPDU_ID, value); \ + /*HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PPDU_ID, value);*/ \ (word) |= (value) << HTT_T2H_PPDU_STATS_PPDU_ID_S; \ } while (0) #define HTT_T2H_PPDU_STATS_PPDU_ID_GET(word) \ @@ -17832,9 +19354,11 @@ struct htt_ul_ofdma_user_info_v0 { }; #define HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 \ - A_UINT32 w0_fw_rsvd:30; \ + A_UINT32 w0_fw_rsvd:29; \ + A_UINT32 w0_manual_ulofdma_trig:1; \ A_UINT32 w0_valid:1; \ A_UINT32 w0_version:1; + struct htt_ul_ofdma_user_info_v0_bitmap_w0 { HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 }; @@ -17855,9 +19379,9 @@ struct htt_ul_ofdma_user_info_v0_bitmap_w1 { #define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 \ A_UINT32 w0_fw_rsvd:27; \ - A_UINT32 w0_sub_version:3; /* set to a value of “0” on WKK/Beryllium targets (future expansion) */ \ + A_UINT32 w0_sub_version:3; /* set to a value of "0" on WKK/Beryllium targets (future expansion) */ \ A_UINT32 w0_valid:1; /* field aligns with V0 definition */ \ - A_UINT32 w0_version:1; /* set to a value of “1” to indicate picking htt_ul_ofdma_user_info_v1_bitmap (field aligns with V0 definition) */ + A_UINT32 w0_version:1; /* set to a value of "1" to indicate picking htt_ul_ofdma_user_info_v1_bitmap (field aligns with V0 definition) */ struct htt_ul_ofdma_user_info_v1_bitmap_w0 { HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 @@ -17924,6 +19448,9 @@ enum HTT_UL_OFDMA_TRIG_TYPE { #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M 0x0000ffff #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S 0 +#define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_M 0x20000000 +#define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_S 29 + #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M 0x40000000 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S 30 @@ -18567,16 +20094,205 @@ PREPACK struct htt_rx_peer_metadata_v1 { ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_CHIP_ID_S)); \ } while (0) -/* - * In some systems, the host SW wants to specify priorities between - * different MSDU / flow queues within the same peer-TID. - * The below enums are used for the host to identify to the target - * which MSDU queue's priority it wants to adjust. +/** + * @brief target -> RX PEER METADATA V1A format + * Host will know the peer metadata version from the wmi_service_ready_ext2 + * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service, + * and will confirm to the target which peer metadata version to use in the + * wmi_init message. + * + * The following diagram shows the format of the RX PEER METADATA V1A format. + * + * |31 29|28 26|25 22|21 14| 13 |12 0| + * |-------------------------------------------------------------------| + * |Rsvd2|CHIP ID|logical_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| + * |-------------------------------------------------------------------| */ +PREPACK struct htt_rx_peer_metadata_v1a { + A_UINT32 + peer_id: 13, + ml_peer_valid: 1, + vdev_id: 8, + logical_link_id: 4, + chip_id: 3, + reserved2: 3; +} POSTPACK; -/* - * The MSDUQ index describe index of TCL HW, where each index is - * used for queuing particular types of MSDUs. +#define HTT_RX_PEER_META_DATA_V1A_PEER_ID_S 0 +#define HTT_RX_PEER_META_DATA_V1A_PEER_ID_M 0x00001fff +#define HTT_RX_PEER_META_DATA_V1A_PEER_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1A_PEER_ID_S) + +#define HTT_RX_PEER_META_DATA_V1A_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_PEER_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S 13 +#define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M 0x00002000 +#define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S) + +#define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S 14 +#define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M 0x003fc000 +#define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S) + +#define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S 22 +#define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M 0x03C00000 +#define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S) + +#define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S 26 +#define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M 0x1c000000 +#define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S) + +#define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_CHIP_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S)); \ + } while (0) + + +/** + * @brief target -> RX PEER METADATA V1B format + * Host will know the peer metadata version from the wmi_service_ready_ext2 + * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service, + * and will confirm to the target which peer metadata version to use in the + * wmi_init message. + * + * The following diagram shows the format of the RX PEER METADATA V1B format. + * + * |31 29|28 26|25 22|21 14| 13 |12 0| + * |--------------------------------------------------------------| + * |Rsvd2|CHIP ID|hw_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| + * |--------------------------------------------------------------| + */ +PREPACK struct htt_rx_peer_metadata_v1b { + A_UINT32 + peer_id: 13, + ml_peer_valid: 1, + vdev_id: 8, + hw_link_id: 4, + chip_id: 3, + reserved2: 3; +} POSTPACK; + +#define HTT_RX_PEER_META_DATA_V1B_PEER_ID_S 0 +#define HTT_RX_PEER_META_DATA_V1B_PEER_ID_M 0x00001fff +#define HTT_RX_PEER_META_DATA_V1B_PEER_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1B_PEER_ID_S) + +#define HTT_RX_PEER_META_DATA_V1B_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_PEER_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S 13 +#define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M 0x00002000 +#define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S) + +#define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S 14 +#define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M 0x003fc000 +#define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S) + +#define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S 22 +#define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M 0x03C00000 +#define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S) + +#define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S 26 +#define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M 0x1c000000 +#define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S) + +#define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_CHIP_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S)); \ + } while (0) + +/* generic variables for masks and shifts for various fields */ +extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_S; +extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_M; + +extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_S; +extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_M; + +/* generic function pointers to get/set values from rx peer metadata v0/v1/v1a/v1b */ +extern A_UINT32 (*HTT_RX_PEER_META_DATA_PEER_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_PEER_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_VDEV_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_VDEV_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_LMAC_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_LMAC_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_CHIP_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_CHIP_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_HW_LINK_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_HW_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val); + + +/* + * In some systems, the host SW wants to specify priorities between + * different MSDU / flow queues within the same peer-TID. + * The below enums are used for the host to identify to the target + * which MSDU queue's priority it wants to adjust. + */ + +/* + * The MSDUQ index describe index of TCL HW, where each index is + * used for queuing particular types of MSDUs. * The different MSDU queue types are defined in HTT_MSDU_QTYPE. */ enum HTT_MSDUQ_INDEX { @@ -19464,4 +21180,1038 @@ typedef struct { } htt_t2h_ppdu_id_fmt_ind_t; +/** + * @brief target -> host RX_CCE_SUPER_RULE setup done message + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE + * + * @details + * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE message is sent by the target + * when RX_CCE_SUPER_RULE setup is done + * + * This message shows the configuration results after the setup operation. + * It will always be sent to host. + * The message would appear as follows: + * + * |31 24|23 16|15 8|7 0| + * |-----------------+-----------------+----------------+----------------| + * | result | response_type | pdev_id | msg_type | + * |---------------------------------------------------------------------| + * + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type: This will be set to 0x33 + * (HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE) + * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is setup on + * b'16:23 - response_type: Indicate the response type of this setup + * done msg + * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE, + * response to HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST + * 1: HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE, + * response to HTT_RX_CCE_SUPER_RULE_INSTALL + * 2: HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE, + * response to HTT_RX_CCE_SUPER_RULE_RELEASE + * b'24:31 - result: Indicate result of setup operation + * For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE: + * b'24 - is_rule_enough: indicate if there are + * enough free cce rule slots + * 0: not enough + * 1: enough + * b'25:31 - avail_rule_num: indicate the number of + * remaining free cce rule slots, only makes sense + * when is_rule_enough = 0 + * For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE: + * b'24 - cfg_result_0: indicate the config result + * of RX_CCE_SUPER_RULE_0 + * 0: Install/Uninstall fails + * 1: Install/Uninstall succeeds + * b'25 - cfg_result_1: indicate the config result + * of RX_CCE_SUPER_RULE_1 + * 0: Install/Uninstall fails + * 1: Install/Uninstall succeeds + * b'26:31 - reserved + * For HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE: + * b'24 - cfg_result_0: indicate the config result + * of RX_CCE_SUPER_RULE_0 + * 0: Release fails + * 1: Release succeeds + * b'25 - cfg_result_1: indicate the config result + * of RX_CCE_SUPER_RULE_1 + * 0: Release fails + * 1: Release succeeds + * b'26:31 - reserved + */ + +enum htt_rx_cce_super_rule_setup_done_response_type { + HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE = 0, + HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE, + HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE, + + /*All reply type should be before this*/ + HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_RESPONSE, +}; + +PREPACK struct htt_rx_cce_super_rule_setup_done_t { + A_UINT8 msg_type; + A_UINT8 pdev_id; + A_UINT8 response_type; + union { + struct { + /* For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE */ + A_UINT8 is_rule_enough: 1, + avail_rule_num: 7; + }; + struct { + /* + * For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE and + * HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE + */ + A_UINT8 cfg_result_0: 1, + cfg_result_1: 1, + rsvd: 6; + }; + } result; +} POSTPACK; + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_SZ (sizeof(struct htt_rx_cce_super_rule_setup_done_t)) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M 0x0000ff00 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S 8 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M 0x00ff0000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S 16 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M 0xff000000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S 24 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M 0x01000000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S 24 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M 0xFE000000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S 25 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M 0x01000000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S 24 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M 0x02000000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S 25 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S)); \ + } while (0) + +/** + * THE BELOW MESSAGE HAS BEEN DEPRECATED + *====================================== + * @brief target -> host CoDel MSDU queue latencies array configuration + * + * MSG_TYPE => HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND + * + * @details + * The HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND message is used + * by the target to inform the host of the location and size of the DDR array of + * per MSDU queue latency metrics. This array is updated by the host and + * read by the target. The target uses these metric values to determine + * which MSDU queues have latencies exceeding their CoDel latency target. + * + * |31 16|15 8|7 0| + * |-------------------------------------------+----------| + * | number of array elements | reserved | MSG_TYPE | + * |-------------------------------------------+----------| + * | array physical address, low bits | + * |------------------------------------------------------| + * | array physical address, high bits | + * |------------------------------------------------------| + * Header fields: + * - MSG_TYPE + * Bits 7:0 + * Purpose: Identifies this as a CoDel MSDU queue latencies + * array configuration message. + * Value: (HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND) + * - NUM_ELEM + * Bits 31:16 + * Purpose: Inform the host of the length of the MSDU queue latencies array. + * Value: Specifies the number of elements in the MSDU queue latency + * metrics array. This value is the same as the maximum number of + * MSDU queues supported by the target. + * Since each array element is 16 bits, the size in bytes of the + * MSDU queue latency metrics array is twice the number of elements. + * - PADDR_LOW + * Bits 31:0 + * Purpose: Inform the host of the MSDU queue latencies array's location. + * Value: Lower 32 bits of the physical address of the MSDU queue latency + * metrics array. + * - PADDR_HIGH + * Bits 31:0 + * Purpose: Inform the host of the MSDU queue latencies array's location. + * Value: Upper 32 bits of the physical address of the MSDU queue latency + * metrics array. + */ +typedef struct { + A_UINT32 msg_type: 8, /* bits 7:0 */ + reserved: 8, /* bits 15:8 */ + num_elem: 16; /* bits 31:16 */ + A_UINT32 paddr_low; + A_UINT32 paddr_high; +} htt_t2h_codel_msduq_latencies_array_cfg_int_t; /* DEPRECATED */ + +#define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_SIZE 12 /* bytes */ + +#define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_M 0xffff0000 +#define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S 16 + +#define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_GET(_var) \ + (((_var) & HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_M) >> \ + HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S) +#define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL( \ + HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM, _val); \ + ((_var) |= ((_val) << \ + HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S)); \ + } while (0) + +/* + * This CoDel MSDU queue latencies array whose location and number of + * elements are specified by this HTT_T2H message consists of 16-bit elements + * that each specify a statistical summary (min) of a MSDU queue's latency, + * using milliseconds units. + */ +#define HTT_CODEL_MSDUQ_LATENCIES_ARRAY_ELEM_BYTES 2 + + +/** + * @brief target -> host rx completion indication message definition + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DATA_IND + * + * @details + * The following diagram shows the format of the Rx completion indication sent + * from the target to the host + * + * |31|29|28 24|23 12|11 9|8| 7|6|5|4|3|2|1|0| + * |---------------+----------------------------+----------------| + * | vdev_id | peer_id | msg_type | + * hdr: |---------------+--------------------------+-+----------------| + * | rsvd0 |F| msdu_cnt | + * pyld: |==========================================+=+================| + * MSDU 0 | buf addr lo (bits 31:0) | + * |-----+--------------------------------------+----------------| + * |rsvd1| SW buffer cookie | buf addr hi | + * |--+--+-----------------------------+--------+--+-+-+-+-+-+-+-| + * |R2| W| MSDU length | TID |MC|D|S|C|L|F|R|M| + * |-------------------------------------------------+---------+-| + * | rsvd3 | err info|E| + * |=================================================+=========+=| + * MSDU 1 | buf addr lo (bits 31:0) | + * : ... : + * | rsvd3 | err info|E| + * |-------------------------------------------------------------| + * Where: + * F = fragment + * M = MPDU retry bit + * R = raw MPDU frame + * F = first MSDU in MPDU + * L = last MSDU in MPDU + * C = MSDU continuation + * S = Souce Addr is valid + * D = Dest Addr is valid + * MC = Dest Addr is multicast / broadcast + * W = is first MSDU after WoW wakeup + * R2 = rsvd2 + * E = error valid + */ + +/* htt_t2h_rx_data_msdu_err: + * To be filled in "htt_t2h_rx_data_msdu_info.error_info" field + * when FW forwards MSDU to host. + */ +typedef enum htt_t2h_rx_data_msdu_err { + /* ERR_DECRYPT: + * FW sets this when rxdma_error_code = . + * host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_DECRYPT = 0, + + /* ERR_TKIP_MIC: + * FW sets this when rxdma_error_code = . + * Host maintains error stats, recycles buffer, sends notification to + * middleware. + */ + HTT_RXDATA_ERR_TKIP_MIC = 1, + + /* ERR_UNENCRYPTED: + * FW sets this when rxdma_error_code = . + * Host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_UNENCRYPTED = 2, + + /* ERR_MSDU_LIMIT: + * FW sets this when rxdma_error_code = . + * Host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_MSDU_LIMIT = 3, + + /* ERR_FLUSH_REQUEST: + * FW sets this when rxdma_error_code = . + * Host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_FLUSH_REQUEST = 4, + + /* ERR_OOR: + * FW full reorder layer maps this error to . + * Host maintains error stats, recycles buffer mainly for low + * TCP KPI debugging. + */ + HTT_RXDATA_ERR_OOR = 5, + + /* ERR_2K_JUMP: + * FW full reorder layer maps this error to . + * Host maintains error stats, recycles buffer mainly for low + * TCP KPI debugging. + */ + HTT_RXDATA_ERR_2K_JUMP = 6, + + /* ERR_ZERO_LEN_MSDU: + * FW sets this error flag for a 0 length MSDU. + * Host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_ZERO_LEN_MSDU = 7, + + /* ERR_INVALID_PEER: + * FW sets this error flag when MSDU is recived from invalid PEER + * HOST decides to send DEAUTH or not, recyles buffer. + */ + HTT_RXDATA_ERR_INVALID_PEER = 8, + + /* add new error codes here */ + + HTT_RXDATA_ERR_MAX = 32 +} htt_t2h_rx_data_msdu_err_e; + +struct htt_t2h_rx_data_ind_t +{ + A_UINT32 /* word 0 */ + /* msg_type: + * Set to Rx data indication i.e. HTT_T2H_MSG_TYPE_RX_DATA_IND. + */ + msg_type: 8, + peer_id: 16, /* This will provide peer data */ + vdev_id: 8; /* This will provide vdev id info */ + A_UINT32 /* word 1 */ + /* msdu_cnt: + * Total number of MSDUs (htt_t2h_rx_data_msdu_info items) in message. + */ + msdu_cnt: 8, + frag: 1, /* this bit will be set for 802.11 frag MPDU */ + rsvd0: 23; + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +struct htt_t2h_rx_data_msdu_info +{ + A_UINT32 /* word 0 */ + buffer_addr_low : 32; + A_UINT32 /* word 1 */ + buffer_addr_high : 8, + sw_buffer_cookie : 21, + /* fw_offloads_inspected: + * When reo_destination_indication is 6 in reo_entrance_ring + * of the RXDMA2REO MPDU upload, all the MSDUs that are part + * of the MPDU are inspected by FW offloads layer, subsequently + * the MSDUs are qualified to be host interested. + * In such case the fw_offloads_inspected is set to 1, else 0. + * This will assist host to not consider such MSDUs for FISA + * flow addition. + */ + fw_offloads_inspected : 1, + rsvd1 : 2; + A_UINT32 /* word 2 */ + mpdu_retry_bit : 1, /* used for stats maintenance */ + raw_mpdu_frame : 1, /* used for pkt drop and processing */ + first_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */ + last_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */ + msdu_continuation : 1, /* used for MSDU scatter/gather support */ + sa_is_valid : 1, /* used for HW issue check in + * is_sa_da_idx_valid() */ + da_is_valid : 1, /* used for HW issue check and + * intra-BSS forwarding */ + da_is_mcbc : 1, + tid_info : 8, /* used for stats maintenance */ + msdu_length : 14, + is_first_pkt_after_wkp : 1, /* indicates this is the first rx MSDU + * provided by fw after WoW exit */ + rsvd2 : 1; + A_UINT32 /* word 3 */ + error_valid : 1, /* Set if the MSDU has any error */ + error_info : 5, /* If error_valid is TRUE, then refer to + * "htt_t2h_rx_data_msdu_err_e" for + * checking error reason. */ + rsvd3 : 26; + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +/* HTT_RX_DATA_IND_HDR_SIZE: 2 4-byte words + * This is the size of htt_t2h_rx_data_ind_t alone which is fixed overhead + * for every Rx DATA IND sent by FW to host. + */ +#define HTT_RX_DATA_IND_HDR_SIZE (2*4) +/* HTT_RX_DATA_MSDU_INFO_SIZE: 4 4-bytes words + * This is the size of each MSDU detail that will be piggybacked with the + * RX IND header. + */ +#define HTT_RX_DATA_MSDU_INFO_SIZE (4*4) + +/* member definitions of htt_t2h_rx_data_ind_t */ + +#define HTT_RX_DATA_IND_PEER_ID_M 0x00ffff00 +#define HTT_RX_DATA_IND_PEER_ID_S 8 + +#define HTT_RX_DATA_IND_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_PEER_ID, value); \ + (word) |= (value) << HTT_RX_DATA_IND_PEER_ID_S; \ + } while (0) +#define HTT_RX_DATA_IND_PEER_ID_GET(word) \ + (((word) & HTT_RX_DATA_IND_PEER_ID_M) >> HTT_RX_DATA_IND_PEER_ID_S) + +#define HTT_RX_DATA_IND_VDEV_ID_M 0xff000000 +#define HTT_RX_DATA_IND_VDEV_ID_S 24 + +#define HTT_RX_DATA_IND_VDEV_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_VDEV_ID, value); \ + (word) |= (value) << HTT_RX_DATA_IND_VDEV_ID_S; \ + } while (0) +#define HTT_RX_DATA_IND_VDEV_ID_GET(word) \ + (((word) & HTT_RX_DATA_IND_VDEV_ID_M) >> HTT_RX_DATA_IND_VDEV_ID_S) + +#define HTT_RX_DATA_IND_MSDU_CNT_M 0x000000ff +#define HTT_RX_DATA_IND_MSDU_CNT_S 0 + +#define HTT_RX_DATA_IND_MSDU_CNT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_MSDU_CNT, value); \ + (word) |= (value) << HTT_RX_DATA_IND_MSDU_CNT_S; \ + } while (0) +#define HTT_RX_DATA_IND_MSDU_CNT_GET(word) \ + (((word) & HTT_RX_DATA_IND_MSDU_CNT_M) >> HTT_RX_DATA_IND_MSDU_CNT_S) + +#define HTT_RX_DATA_IND_FRAG_M 0x00000100 +#define HTT_RX_DATA_IND_FRAG_S 8 + +#define HTT_RX_DATA_IND_FRAG_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_FRAG, value); \ + (word) |= (value) << HTT_RX_DATA_IND_FRAG_S; \ + } while (0) +#define HTT_RX_DATA_IND_FRAG_GET(word) \ + (((word) & HTT_RX_DATA_IND_FRAG_M) >> HTT_RX_DATA_IND_FRAG_S) + +/* member definitions of htt_t2h_rx_data_msdu_info */ + +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M 0xFFFFFFFF +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S 0 + +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M 0x000000FF +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S 0 + +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S) + +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S) + +#define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M 0x1FFFFF00 +#define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S 8 + +#define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M) >> HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S) + +#define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_M 0x20000000 +#define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S 29 + +#define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_M) >> HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S) + +#define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M 0x00000001 +#define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S 0 + +#define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M) >> HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S) + +#define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M 0x00000002 +#define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S 1 + +#define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M) >> HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S) + +#define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M 0x00000004 +#define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S 2 + +#define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S) + +#define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M 0x00000008 +#define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S 3 + +#define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S) + +#define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M 0x00000010 +#define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S 4 + +#define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S) + +#define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M 0x00000020 +#define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S 5 + +#define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SA_IS_VALID, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S) + +#define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M 0x00000040 +#define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S 6 + +#define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_VALID, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S) + +#define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M 0x00000080 +#define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S 7 + +#define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S) + +#define HTT_RX_DATA_MSDU_INFO_TID_INFO_M 0x0000FF00 +#define HTT_RX_DATA_MSDU_INFO_TID_INFO_S 8 + +#define HTT_RX_DATA_MSDU_INFO_TID_INFO_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_TID_INFO, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_TID_INFO_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_TID_INFO_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_TID_INFO_M) >> HTT_RX_DATA_MSDU_INFO_TID_INFO_S) + +#define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M 0x3FFF0000 +#define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S 16 + +#define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S) + +#define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M 0x40000000 +#define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S 30 + +#define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M) >> HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S) + +#define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M 0x00000001 +#define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S 0 + +#define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_VALID, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S) + +#define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M 0x0000001E +#define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S 1 + +#define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_INFO, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S) + + +/** + * @brief target -> Primary peer migration message to host + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND + * + * @details + * HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND message is sent by target + * to host to flush & set-up the RX rings to new primary peer + * + * The message would appear as follows: + * + * |31 16|15 12|11 8|7 0| + * |-------------------------------+---------+---------+--------------| + * | vdev ID | pdev ID | chip ID | msg type | + * |-------------------------------+---------+---------+--------------| + * | ML peer ID | SW peer ID | + * |-------------------------------+----------------------------------| + * + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type: This will be set to 0x37 + * (HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND) + * b'8:11 - chip_id: Indicate which chip has been chosen as primary + * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen + * as primary + * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen + * as primary + * + * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer + * chosen as primary + * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the + * primary peer belongs. + */ +typedef struct { + A_UINT32 msg_type: 8, /* bits 7:0 */ + chip_id: 4, /* bits 11:8 */ + pdev_id: 4, /* bits 15:12 */ + vdev_id: 16; /* bits 31:16 */ + A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */ + ml_peer_id: 16; /* bits 31:16 */ +} htt_t2h_primary_link_peer_migrate_ind_t; + +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ + } while (0) + +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ + } while (0) + +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ + } while (0) + +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ + } while (0) + +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ + } while (0) + +/** + * @brief target -> host rx peer AST override message defenition + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND + * + * @details + * Format inherits parts of the HTT_T2H_MSG_TYPE_PEER_MAP_V3 published above + * where in the dummy ast index is provided to the host. + * This new message below is sent to the host at run time from the TX_DE + * exception path when a SAWF flow is detected for a peer. + * This is sent up once per SAWF peer. + * This layout assumes the target operates as little-endian. + * + * |31 24|23 16|15 8|7 0| + * |--------------------------------------+-----------------+-----------------| + * | SW peer ID | vdev ID | msg type | + * |-----------------+--------------------+-----------------+-----------------| + * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | + * |-----------------+--------------------+-----------------+-----------------| + * | dummy AST Index #1 | MAC addr 5 | MAC addr 4 | + * |--------------------------------------+-----------------+-----------------| + * | reserved | dummy AST Index #2 | + * |--------------------------------------+-----------------------------------| + * + * The following field definitions describe the format of the peer ast override + * index messages sent from the target to the host. + * - MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as a peer map v3 message + * Value: 0x38 (HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND) + * - VDEV_ID + * Bits 15:8 + * Purpose: Indicates which virtual device the peer is associated with. + * - SW_PEER_ID + * Bits 31:16 + * Purpose: The peer ID (index) that WAL has allocated for this peer. + * - MAC_ADDR_L32 + * Bits 31:0 + * Purpose: Identifies which peer node the peer ID is for. + * Value: lower 4 bytes of peer node's MAC address + * - MAC_ADDR_U16 + * Bits 15:0 + * Purpose: Identifies which peer node the peer ID is for. + * Value: upper 2 bytes of peer node's MAC address + * - AST_INDEX1 + * Bits 31:16 + * Purpose: The 1st extra AST index used to identify user defined MSDUQ + * - AST_INDEX2 + * Bits 15:0 + * Purpose: The 2nd extra AST index used to identify user defined MSDUQ +*/ + +/* dword 0 */ +#define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M 0xffff0000 +#define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S 16 +#define HTT_PEER_AST_OVERRIDE_VDEV_ID_M 0x0000ff00 +#define HTT_PEER_AST_OVERRIDE_VDEV_ID_S 8 +/* dword 1 */ +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M 0xffffffff +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S 0 +/* dword 2 */ +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M 0x0000ffff +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S 0 +#define HTT_PEER_AST_OVERRIDE_AST_INDEX1_M 0xffff0000 +#define HTT_PEER_AST_OVERRIDE_AST_INDEX1_S 16 +/* dword 3 */ +#define HTT_PEER_AST_OVERRIDE_AST_INDEX2_M 0x0000ffff +#define HTT_PEER_AST_OVERRIDE_AST_INDEX2_S 0 + +#define HTT_PEER_AST_OVERRIDE_VDEV_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_VDEV_ID, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_VDEV_ID_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_VDEV_ID_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_VDEV_ID_M) >> HTT_PEER_AST_OVERRIDE_VDEV_ID_S) + +#define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_SW_PEER_ID, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M) >> HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S) + +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S) + +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S) + +#define HTT_PEER_AST_OVERRIDE_AST_INDEX1_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX1, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX1_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_AST_INDEX1_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX1_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX1_S) + + +#define HTT_PEER_AST_OVERRIDE_AST_INDEX2_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX2, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX2_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_AST_INDEX2_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX2_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX2_S) + + +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_WORD_BASE_OFFSET 4 /* bytes */ +#define HTT_PEER_AST_OVERRIDE_DUMMY_AST1_WORD_BASE_OFFSET 8 /* bytes */ +#define HTT_PEER_AST_OVERRIDE_DUMMY_AST2_WORD_BASE_OFFSET 12 /* bytes */ + +#define HTT_PEER_AST_OVERRIDE_INDEX_IND_BYTES 16 + + +/** + * @brief target -> periodic report of tx latency to host + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND + * + * @details + * The message starts with a message header followed by one or more + * htt_t2h_peer_tx_latency_stats structs, one for each peer within the vdev. + * After each upload, these tx latency stats will be reset. + * + * |31 24|23 16|15 14|13 10|9 8|7 0| + * +-------------------------+-----+-----+---+----------| + * hdr | |pyld elem sz| | GR | P | msg type | + *- -|=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| + * pyld | peer ID | + * |----------------------------------------------------| + * | peer_tx_latency[0] | + * |----------------------------------------------------| + * 1st | peer_tx_latency[1] | + * peer |----------------------------------------------------| + * | peer_tx_latency[2] | + * |----------------------------------------------------| + * | peer_tx_latency[3] | + * |----------------------------------------------------| + * | avg latency | + * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| + * | peer ID | + * |----------------------------------------------------| + * | peer_tx_latency[0] | + * |----------------------------------------------------| + * 2nd | peer_tx_latency[1] | + * peer |----------------------------------------------------| + * | peer_tx_latency[2] | + * |----------------------------------------------------| + * | peer_tx_latency[3] | + * |----------------------------------------------------| + * | avg latency | + * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| + * Where: + * P = pdev ID + * GR = granularity + * + * @details + * htt_t2h_tx_latency_stats_periodic_hdr_t: + * - msg_type + * Bits 7:0 + * Purpose: identifies this as a tx latency report message + * Value: 0x3a (HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND) + * - pdev_id + * Bits 9:8 + * Purpose: Indicates which pdev this message is associated with. + * - granularity + * Bits 13:10 + * Purpose: specifies the granulairty of each tx latency bucket in MS. + * There are 4 buckets in total. E.g. if granularity is set to 5 ms, + * then the ranges for the 4 latency histogram buckets will be + * 0-5ms, 5ms-10ms, 10ms-15ms, 15ms-max, respectively. + * - payload_elem_size + * Bits 23:16 + * Purpose: specifies the size of each element within the msg's payload + * In other words, this field specified the value of + * sizeof(htt_t2h_peer_tx_latency_stats) based on the target's + * revision of the htt_t2h_peer_tx_latency_stats definition. + * If the payload_elem_size reported in the message exceeds the + * sizeof(htt_t2h_peer_tx_latency_stats) based on the host's + * revision of the htt_t2h_peer_tx_latency_stats definition, + * the host shall ignore the excess data. + * Conversely, if the payload_elem_size reported in the message is + * less than sizeof(htt_t2h_peer_tx_latency_stats) based on the host's + * revision of the htt_t2h_peer_tx_latency_stats definition, + * the host shall use 0x0 values for the portion of the data not + * provided by the target. + * The host can compare the payload_elem_size to the total size of + * the message minus the size of the message header to determine + * how many peer payload elements are present in the message. + * - sw_peer_id + * Purpose: The peer to which the following stats belong + * - peer_tx_latency + * Purpose: tx latency histogram for this peer, with 4 buckets whose + * size (in milliseconds) is specified by the granularity field + * - avg_latency + * Purpose: average tx latency (in ms) for this peer in this report interval +*/ +typedef struct { + A_UINT32 msg_type: 8, + pdev_id: 2, + granularity: 4, + reserved1: 2, + payload_elem_size: 8, + reserved2: 8; +} htt_t2h_tx_latency_stats_periodic_hdr_t; + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_HDR_SIZE \ + (sizeof(htt_t2h_tx_latency_stats_periodic_hdr_t)) +#define HTT_PEER_TX_LATENCY_REPORT_BINS 4 + +typedef struct _htt_tx_latency_stats { + A_UINT32 peer_id; + A_UINT32 peer_tx_latency[HTT_PEER_TX_LATENCY_REPORT_BINS]; + A_UINT32 avg_latency; +} htt_t2h_peer_tx_latency_stats; + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M 0x00000300 +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S 8 + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_GET(_var) \ + (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S) +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S)); \ + } while (0) + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M 0x00003C00 +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S 10 + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_GET(_var) \ + (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S) +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY, _val); \ + ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)); \ + } while (0) + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M 0x00FF0000 +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S 16 + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_GET(_var) \ + (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S) +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE, _val); \ + ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)); \ + } while (0) + + + #endif diff --git a/drivers/staging/fw-api/fw/htt_ppdu_stats.h b/drivers/staging/fw-api/fw/htt_ppdu_stats.h index d5555a12955db784698647e37912aa906164861a..fed6e2d63975fa4a2bb1db54784c986928426f95 100644 --- a/drivers/staging/fw-api/fw/htt_ppdu_stats.h +++ b/drivers/staging/fw-api/fw/htt_ppdu_stats.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -612,6 +612,58 @@ typedef enum HTT_PPDU_STATS_SPATIAL_REUSE HTT_PPDU_STATS_SPATIAL_REUSE; ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_S)); \ } while (0) +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_M 0x00020000 +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_S 17 + +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_S) + +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_S)); \ + } while (0) + +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_M 0x000c0000 +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_S 18 + +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_S) + +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_AC_VALID, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_S)); \ + } while (0) + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_M 0x00100000 +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_S 20 + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_S) + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_S)); \ + } while (0) + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_M 0x1fe00000 +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_S 21 + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_S) + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_S)); \ + } while (0) + #define HTT_PPDU_STATS_COMMON_TRIG_COOKIE_M 0x0000ffff #define HTT_PPDU_STATS_COMMON_TRIG_COOKIE_S 0 @@ -760,19 +812,36 @@ typedef struct { * by which SRG/Non-SRG based spatial reuse opportunity * was created. * BIT [16:16] - PPDU transmitted using PSR opportunity - * BIT [31:17] - reserved + * BIT [17:17] - backoff_ac_valid + * BIT [19:18] - backoff_ac: WMM ACI Value of the backoff engine used for + * this transmission. Only valid if backoff_ac_valid is set + * to 1. Typically this would match the default tid + * number -> AC mapping. For frames in the middle of a SIFS + * burst, the backoff_ac_valid will be 0. + * BIT [20:20] - num_ul_user_responses_valid + * BIT [21:28] - num_ul_user_responses: The number of user responses + * detected by the MAC layer. This value can be compared with + * the "num_ul_expected_users" field to see whether this frame + * had a complete or partial response failure. Only valid if + * num_ul_user_responses_valid is set to 1. + * BIT [31:29] - reserved */ union { + A_UINT32 reserved__num_ul_user_responses__num_ul_user_responses_valid__backoff_ac__backoff_ac_valid__psr_tx__aborted_obss_rssi__srg_tx__non_srg_tx__bss_color_id; A_UINT32 reserved__psr_tx__aborted_obss_rssi__srg_tx__non_srg_tx___bss_color_id; A_UINT32 reserved__aborted_obss_rssi__srg_tx__non_srg_tx___bss_color_id; A_UINT32 reserved__bss_color_id; struct { - A_UINT32 bss_color_id: 6, - non_srg_tx: 1, - srg_tx: 1, - aborted_obss_rssi: 8, - psr_tx: 1, - reserved2: 15; + A_UINT32 bss_color_id: 6, + non_srg_tx: 1, + srg_tx: 1, + aborted_obss_rssi: 8, + psr_tx: 1, + backoff_ac_valid: 1, + backoff_ac: 2, + num_ul_user_responses_valid: 1, + num_ul_user_responses: 8, + reserved2: 3; }; }; @@ -787,16 +856,18 @@ typedef struct { }; /* - * htt_seq_type field is added for backward compatibility with - * pktlog decoder, host driver or any third party tool interpreting - * ppdu sequence type. If field 'htt_seq_type'is not present or is - * present but set to WAL_PPDU_SEQ_TYPE, decoder should interpret - * the seq type as WAL_TXSEND_PPDU_SEQUENCE. - * If the new field htt_seq_type is present and is set to - * HTT_PPDU_SEQ_TYPE then decoder should interpret the seq type as - * HTT_PPDU_STATS_SEQ_TYPE. htt_seq_type field will be set to - * HTT_PPDU_SEQ_TYPE in firmware versions where this field is - * defined. + * BIT [0 : 0] - htt_seq_type field is added for backward compatibility + * with pktlog decoder, host driver or any third party tool + * interpreting ppdu sequence type. If field 'htt_seq_type' + * is not present or is present but set to WAL_PPDU_SEQ_TYPE, + * decoder should interpret the seq type as + * WAL_TXSEND_PPDU_SEQUENCE. + * If the new field htt_seq_type is present and is set to + * HTT_PPDU_SEQ_TYPE then decoder should interpret the + * seq type as HTT_PPDU_STATS_SEQ_TYPE. + * htt_seq_type field will be set to HTT_PPDU_SEQ_TYPE in + * firmware versions where this field is defined. + * BIT [31: 1] - reserved */ union { A_UINT32 reserved__htt_seq_type; @@ -805,6 +876,16 @@ typedef struct { reserved3: 31; }; }; + /* is_manual_ulofdma_trigger: + * Flag to indicate if a given UL OFDMA trigger is manually triggered + * from the Host + */ + A_UINT32 is_manual_ulofdma_trigger; + /* is_combined_ul_bsrp_trigger: + * Flag to indicate if a given UL BSRP trigger is sent combined as + * part of existing DL/UL data sequence + */ + A_UINT32 is_combined_ul_bsrp_trigger; } htt_ppdu_stats_common_tlv; #define HTT_PPDU_STATS_USER_COMMON_TLV_TID_NUM_M 0x000000ff @@ -976,6 +1057,20 @@ typedef struct { ((_var) |= ((_val) << HTT_PPDU_STATS_USER_COMMON_TLV_CHAIN_ENABLE_BITS_S)); \ } while (0) +#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_M 0x00010000 +#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_S 16 + +#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_GET(_var) \ + (((_var) & HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_M) >> \ + HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_S) + +#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_S)); \ + } while (0) + + #define HTT_PPDU_STATS_USER_COMMON_TLV_TX_PWR_CHAINS_PER_U32 4 #define HTT_PPDU_STATS_USER_COMMON_TLV_TX_PWR_MASK 0x000000ff @@ -1113,10 +1208,15 @@ typedef struct { * Default value: 1 * tx_pwr[0] value is used for all chains if chain_enable_bits field * is set to 1. + * + * is_smart_ulofdma_basic_trig: + * To check if user grouped in UL OFDMA Basic Trigger Frame is + * due to Smart Basic Trigger. */ - A_UINT32 tx_pwr_multiplier : 8, - chain_enable_bits : 8, - reserved2 : 16; + A_UINT32 tx_pwr_multiplier : 8, + chain_enable_bits : 8, + is_smart_ulofdma_basic_trig: 1, + reserved2 : 15; /* * Transmit powers (signed values packed into unsigned bitfields) @@ -1169,6 +1269,19 @@ typedef struct { * value is larger than A_INT8. */ A_UINT32 alt_tx_pwr[HTT_STATS_MAX_CHAINS / HTT_PPDU_STATS_USER_COMMON_TLV_TX_PWR_CHAINS_PER_U32]; + + /* + * A bitmap indicating the MSDUQs that the scheduler is attempting to + * transmit in this PPDU. Note that in some cases, the scheduler's notion + * of what MSDUQs are being transmitted from may not be fully accurate, + * such as when MPDUs are retried, or when some previously generated MPDUs + * that were not attempted OTA yet are tried. + * + * The valid bit indices for this bitmap are defined by the HTT_MSDUQ_INDEX + * enum (in htt.h). For example, (1 << HTT_MSDUQ_INDEX_UDP) would + * correspond to the default UDP msduq. + */ + A_UINT32 msduq_bitmap; } htt_ppdu_stats_user_common_tlv; #define HTT_PPDU_STATS_USER_RATE_TLV_TID_NUM_M 0x000000ff @@ -1712,6 +1825,32 @@ typedef enum HTT_PPDU_STATS_RESP_PPDU_TYPE HTT_PPDU_STATS_RESP_PPDU_TYPE; ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_PUNC_PATTERN_BITMAP_S)); \ } while (0) +#define HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_M 0x00010000 +#define HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_S 16 + +#define HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_GET(_var) \ + (((_var) & HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_M) >> \ + HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_S) + +#define HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_SET (_var , _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_S)); \ + } while (0) + +#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_M 0x00020000 +#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S 17 + +#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_GET(_var) \ + (((_var) & HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_M) >> \ + HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S) + +#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_SET (_var , _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S)); \ + } while (0) + typedef enum HTT_PPDU_STATS_RU_SIZE { HTT_PPDU_STATS_RU_26, HTT_PPDU_STATS_RU_52, @@ -1897,9 +2036,13 @@ typedef struct { /* * BIT [15:0] :- Punctured BW bitmap pattern to indicate which BWs are * punctured. + * BIT 16 :- flag showing whether EHT extra LTF is applied + * for current PPDU */ A_UINT32 punc_pattern_bitmap: 16, - reserved4: 16; + extra_eht_ltf: 1, + is_min_rate: 1, + reserved4: 14; } htt_ppdu_stats_user_rate_tlv; #define HTT_PPDU_STATS_USR_RATE_VALID_M 0x80000000 @@ -2342,7 +2485,7 @@ typedef struct { /* * Max rates configured per BW: - * for BW supported by Smart Antenna - 20MHZ, 40MHZ and 80MHZ and 160MHZ + * for BW supported by Smart Antenna - 20MHZ, 40MHZ, 80MHZ and 160MHZ * (Note: 160 MHz is currently not supported by Smart Antenna) */ A_UINT32 max_rates[HTT_STATS_NUM_SUPPORTED_BW_SMART_ANTENNA]; @@ -2363,6 +2506,17 @@ typedef struct { sw_rts_failure: 1, cts_rcvd_diff_bw: 1, reserved2: 28; + + /* + * Max rates configured per BW: + * for BW supported by Smart Antenna - 320 MHZ + */ + A_UINT32 max_rates_ext; + + /* hw_prot_dur_us: + * hw protection frame's FES duration in micro seconds. + */ + A_UINT32 hw_prot_dur_us; } htt_ppdu_stats_user_cmpltn_common_tlv; #define HTT_PPDU_STATS_USER_CMPLTN_BA_BITMAP_TLV_TID_NUM_M 0x000000ff diff --git a/drivers/staging/fw-api/fw/htt_stats.h b/drivers/staging/fw-api/fw/htt_stats.h index 67dd30f9a5f424f410a44005d333ea56dcf7eb87..c779f6fd16e811ed8d4f25930c4e2467c1fc7c69 100644 --- a/drivers/staging/fw-api/fw/htt_stats.h +++ b/drivers/staging/fw-api/fw/htt_stats.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -148,6 +148,7 @@ enum htt_dbg_ext_stats_type { * 6 bit htt_msdu_flow_stats_tlv * 7 bit htt_peer_sched_stats_tlv * 8 bit htt_peer_ax_ofdma_stats_tlv + * 9 bit htt_peer_be_ofdma_stats_tlv * - config_param2: [Bit31 : Bit0] mac_addr31to0 * - config_param3: [Bit15 : Bit0] mac_addr47to32 * [Bit 16] If this bit is set, reset per peer stats @@ -519,6 +520,85 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_PDEV_MBSSID_CTRL_FRAME_STATS = 54, + /** HTT_DBG_SOC_SSR_STATS + * Used for non-MLO UMAC recovery stats. + * PARAMS: + * - No Params + * RESP MSG: + * - htt_umac_ssr_stats_tlv + */ + HTT_DBG_SOC_SSR_STATS = 55, + + /** HTT_DBG_MLO_UMAC_SSR_STATS + * Used for MLO UMAC recovery stats. + * PARAMS: + * - No Params + * RESP MSG: + * - htt_mlo_umac_ssr_stats_tlv + */ + HTT_DBG_MLO_UMAC_SSR_STATS = 56, + + /** HTT_DBG_PDEV_TDMA_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_pdev_tdma_stats_tlv + */ + HTT_DBG_PDEV_TDMA_STATS = 57, + + /** HTT_DBG_CODEL_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_codel_svc_class_stats_tlv + * - htt_codel_msduq_stats_tlv + */ + HTT_DBG_CODEL_STATS = 58, + + /** HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_tx_pdev_mpdu_stats_tlv + */ + HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS = 59, + + /** HTT_DBG_EXT_STATS_PDEV_UL_TRIGGER + * PARAMS: + * - No Params + * RESP MSG: + * - htt_rx_pdev_be_ul_ofdma_user_stats_tlv + */ + HTT_DBG_ODD_UL_BE_OFDMA_STATS = 60, + + /** HTT_DBG_ODD_BE_TXBF_OFDMA_STATS + */ + HTT_DBG_ODD_BE_TXBF_OFDMA_STATS = 61, + + /** HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_rx_pdev_be_ul_ofdma_user_stats_tlv + */ + HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS = 62, + + /** HTT_DBG_MLO_SCHED_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_pdev_mlo_sched_stats_tlv + */ + HTT_DBG_MLO_SCHED_STATS = 63, + + /** HTT_DBG_PDEV_MLO_IPC_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_pdev_mlo_ipc_stats_tlv + */ + HTT_DBG_PDEV_MLO_IPC_STATS = 64, + /* keep this last */ HTT_DBG_NUM_EXT_STATS = 256, @@ -928,6 +1008,20 @@ typedef struct { A_UINT32 flush_errs[1]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ } htt_tx_pdev_stats_flush_tlv_v; +#define HTT_TX_PDEV_STATS_MLO_ABORT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) +/* NOTE: Variable length TLV, use length spec to infer array size */ +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 mlo_abort_cnt[]; /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ +} htt_tx_pdev_stats_mlo_abort_tlv_v; + +#define HTT_TX_PDEV_STATS_MLO_TXOP_ABORT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) +/* NOTE: Variable length TLV, use length spec to infer array size */ +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 mlo_txop_abort_cnt[]; /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ +} htt_tx_pdev_stats_mlo_txop_abort_tlv_v; + #define HTT_TX_PDEV_STATS_SIFS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { @@ -1467,6 +1561,17 @@ typedef struct _htt_tx_tid_stats_v1_tlv { A_UINT32 mlo_flush_partner_info_high; A_UINT32 mlo_flush_initator_info_low; A_UINT32 mlo_flush_initator_info_high; + /* + * head_msdu_tqm_timestamp_us: + * MSDU enqueue timestamp (TQM reference timestamp) for the MSDU + * at the head of the MPDU queue + * head_msdu_tqm_latency_us: + * The age of the MSDU that is at the head of the MPDU queue, + * i.e. the delta between the current TQM time and the MSDU's + * enqueue timestamp. + */ + A_UINT32 head_msdu_tqm_timestamp_us; + A_UINT32 head_msdu_tqm_latency_us; } htt_tx_tid_stats_v1_tlv; #define HTT_RX_TID_STATS_SW_PEER_ID_M 0x0000ffff @@ -1575,6 +1680,13 @@ typedef struct { #define HTT_PEER_DETAILS_ML_PEER_ID_S 1 #define HTT_PEER_DETAILS_LINK_IDX_M 0x001fe000 #define HTT_PEER_DETAILS_LINK_IDX_S 13 +#define HTT_PEER_DETAILS_USE_PPE_M 0x00200000 +#define HTT_PEER_DETAILS_USE_PPE_S 21 + + +#define HTT_PEER_DETAILS_SRC_INFO_M 0x00000fff +#define HTT_PEER_DETAILS_SRC_INFO_S 0 + #define HTT_PEER_DETAILS_SET(word, httsym, val) \ do { \ @@ -1603,7 +1715,11 @@ typedef struct { A_UINT32 ml_peer_id_valid : 1, /* [0:0] */ ml_peer_id : 12, /* [12:1] */ link_idx : 8, /* [20:13] */ - rsvd : 11; /* [31:21] */ + use_ppe : 1, /* [21:21] */ + rsvd0 : 10; /* [31:22] */ + /* Dword 9 */ + A_UINT32 src_info : 12, /* [11:0] */ + rsvd1 : 20; /* [31:12] */ } htt_peer_details_tlv; typedef struct { @@ -1833,6 +1949,7 @@ typedef enum { HTT_MSDU_FLOW_STATS_TLV = 6, HTT_PEER_SCHED_STATS_TLV = 7, HTT_PEER_AX_OFDMA_STATS_TLV = 8, + HTT_PEER_BE_OFDMA_STATS_TLV = 9, HTT_PEER_STATS_MAX_TLV = 31, } htt_peer_stats_tlv_enum; @@ -1876,8 +1993,20 @@ typedef struct { /* Last updated value of DL and UL queue depths for each peer per AC */ A_UINT32 last_updated_dl_qdepth[HTT_NUM_AC_WMM]; A_UINT32 last_updated_ul_qdepth[HTT_NUM_AC_WMM]; + /* Per peer Manual 11ax UL OFDMA trigger and trigger error counts */ + A_UINT32 ax_manual_ulofdma_trig_count; + A_UINT32 ax_manual_ulofdma_trig_err_count; } htt_peer_ax_ofdma_stats_tlv; +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 peer_id; + /* Per peer Manual 11be UL OFDMA trigger and trigger error counts */ + A_UINT32 be_manual_ulofdma_trig_count; + A_UINT32 be_manual_ulofdma_trig_err_count; +} htt_peer_be_ofdma_stats_tlv; + + /* config_param0 */ #define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_M 0x00000001 @@ -1967,6 +2096,7 @@ typedef struct _htt_peer_stats { htt_tx_tid_stats_v1_tlv tx_tid_stats_v1[1]; htt_peer_sched_stats_tlv peer_sched_stats; htt_peer_ax_ofdma_stats_tlv ax_ofdma_stats; + htt_peer_be_ofdma_stats_tlv be_ofdma_stats; } htt_peer_stats_t; /* =========== ACTIVE PEER LIST ========== */ @@ -2342,6 +2472,8 @@ typedef enum { #define HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \ (HTT_STATS_MAX_MUMIMO_GRP_SZ * HTT_STATS_MAX_INVALID_REASON_CODE) +#define HTT_MAX_NUM_SBT_INTR 4 + typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -2394,6 +2526,19 @@ typedef struct { /** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */ A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM]; /* END DEPRECATED FIELDS */ + /** smart_basic_trig_sch_histogram: + * Count how many times the interval between predictive basic triggers + * sent to a given STA based on analysis of that STA's traffic patterns + * is within a given range: + * + * smart_basic_trig_sch_histogram[0]: SBT interval <= 10 ms + * smart_basic_trig_sch_histogram[1]: 10 ms < SBT interval <= 20 ms + * smart_basic_trig_sch_histogram[2]: 20 ms < SBT interval <= 30 ms + * smart_basic_trig_sch_histogram[3]: 30 ms < SBT interval <= 40 ms + * + * (Smart basic triggers are only used with intervals <= 40 ms.) + */ + A_UINT32 smart_basic_trig_sch_histogram[HTT_MAX_NUM_SBT_INTR]; } htt_tx_selfgen_cmn_stats_tlv; typedef struct { @@ -2485,6 +2630,22 @@ typedef struct { A_UINT32 standalone_ax_bsr_trigger_tried[HTT_NUM_AC_WMM]; /** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */ A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM]; + /** 11AX HE Manual Single-User UL OFDMA Trigger frame sent over the air */ + A_UINT32 manual_ax_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; + /** 11AX HE Manual Single-User UL OFDMA Trigger completed with error(s) */ + A_UINT32 manual_ax_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; + /** 11AX HE Manual Multi-User UL OFDMA Trigger frame sent over the air */ + A_UINT32 manual_ax_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; + /** 11AX HE Manual Multi-User UL OFDMA Trigger completed with error(s) */ + A_UINT32 manual_ax_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; + /** 11AX HE UL OFDMA Basic Trigger frames per AC */ + A_UINT32 ax_basic_trigger_per_ac[HTT_NUM_AC_WMM]; + /** 11AX HE UL OFDMA Basic Trigger frames per AC completed with error(s) */ + A_UINT32 ax_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM]; + /** 11AX HE MU-BAR Trigger frames per AC */ + A_UINT32 ax_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM]; + /** 11AX HE MU-BAR Trigger frames per AC completed with error(s) */ + A_UINT32 ax_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM]; } htt_tx_selfgen_ax_stats_tlv; typedef struct { @@ -2532,6 +2693,22 @@ typedef struct { A_UINT32 standalone_be_bsr_trigger_tried[HTT_NUM_AC_WMM]; /** 11BE EHT MU Standalone Freq. BSRP Trigger completed with error(s) */ A_UINT32 standalone_be_bsr_trigger_err[HTT_NUM_AC_WMM]; + /** 11BE EHT Manual Single-User UL OFDMA Trigger frame sent over the air */ + A_UINT32 manual_be_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; + /** 11BE EHT Manual Single-User UL OFDMA Trigger completed with error(s) */ + A_UINT32 manual_be_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; + /** 11BE EHT Manual Multi-User UL OFDMA Trigger frame sent over the air */ + A_UINT32 manual_be_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; + /** 11BE EHT Manual Multi-User UL OFDMA Trigger completed with error(s) */ + A_UINT32 manual_be_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; + /** 11BE EHT UL OFDMA Basic Trigger frames per AC */ + A_UINT32 be_basic_trigger_per_ac[HTT_NUM_AC_WMM]; + /** 11BE EHT UL OFDMA Basic Trigger frames per AC completed with error(s) */ + A_UINT32 be_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM]; + /** 11BE EHT MU-BAR Trigger frames per AC */ + A_UINT32 be_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM]; + /** 11BE EHT MU-BAR Trigger frames per AC completed with error(s) */ + A_UINT32 be_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM]; } htt_tx_selfgen_be_stats_tlv; typedef struct { /* DEPRECATED */ @@ -3885,6 +4062,7 @@ typedef struct { A_UINT32 total_get_mpdu_head_info_cmds_by_sched_algo_la_query; A_UINT32 total_get_mpdu_head_info_cmds_by_tac; A_UINT32 total_gen_mpdu_cmds_by_sched_algo_la_query; + A_UINT32 high_prio_q_not_empty; } htt_tx_tqm_cmn_stats_tlv; typedef struct { @@ -4965,6 +5143,8 @@ typedef struct { A_UINT32 ax_su_embedded_trigger_data_ppdu_err; /** sta side trigger stats */ A_UINT32 trigger_type_11be[HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES]; + /** Stats for Extra EHT LTF */ + A_UINT32 extra_eht_ltf; } htt_tx_pdev_rate_stats_tlv; typedef struct { @@ -5527,6 +5707,12 @@ typedef struct { * response to basic trigger. Typically a data response is expected. */ A_UINT32 be_ul_ofdma_basic_trigger_rx_qos_null_only; + + /* UL MLO Queue Depth Sharing Stats */ + A_UINT32 ul_mlo_send_qdepth_params_count; + A_UINT32 ul_mlo_proc_qdepth_params_count; + A_UINT32 ul_mlo_proc_accepted_qdepth_params_count; + A_UINT32 ul_mlo_proc_discarded_qdepth_params_count; } htt_rx_pdev_be_ul_trigger_stats_tlv; /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS @@ -6127,6 +6313,7 @@ typedef struct { A_UINT32 med_rx_idle_usec; A_UINT32 med_tx_idle_global_usec; A_UINT32 cca_obss_usec; + A_UINT32 pre_rx_frame_usec; } htt_pdev_stats_cca_counters_tlv; /* NOTE: THIS htt_pdev_cca_stats_hist_tlv STRUCTURE IS DEPRECATED, @@ -6217,9 +6404,12 @@ typedef struct { */ } htt_pdev_cca_stats_hist_v1_tlv; -#define HTT_TWT_SESSION_FLAG_FLOW_ID_M 0x0000ffff +#define HTT_TWT_SESSION_FLAG_FLOW_ID_M 0x0000000f #define HTT_TWT_SESSION_FLAG_FLOW_ID_S 0 +#define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_M 0x0000fff0 +#define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S 4 + #define HTT_TWT_SESSION_FLAG_BCAST_TWT_M 0x00010000 #define HTT_TWT_SESSION_FLAG_BCAST_TWT_S 16 @@ -6239,6 +6429,16 @@ typedef struct { ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_FLOW_ID_S)); \ } while (0) +#define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_GET(_var) \ + (((_var) & HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_M) >> \ + HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S) + +#define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT, _val); \ + ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S)); \ + } while (0) + #define HTT_TWT_SESSION_FLAG_BCAST_TWT_GET(_var) \ (((_var) & HTT_TWT_SESSION_FLAG_BCAST_TWT_M) >> \ HTT_TWT_SESSION_FLAG_BCAST_TWT_S) @@ -6389,12 +6589,15 @@ typedef enum { } htt_txbf_sound_steer_modes; typedef enum { - HTT_TX_AC_SOUNDING_MODE = 0, - HTT_TX_AX_SOUNDING_MODE = 1, - HTT_TX_BE_SOUNDING_MODE = 2, + HTT_TX_AC_SOUNDING_MODE = 0, + HTT_TX_AX_SOUNDING_MODE = 1, + HTT_TX_BE_SOUNDING_MODE = 2, HTT_TX_CMN_SOUNDING_MODE = 3, + HTT_TX_CV_CORR_MODE = 4, } htt_stats_sounding_tx_mode; +#define HTT_TX_CV_CORR_MAX_NUM_COLUMNS 8 + typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */ @@ -6488,14 +6691,84 @@ typedef struct { A_UINT32 cv_buf_received; /** total times CV bufs fed back to the IPC ring */ A_UINT32 cv_buf_fed_back; - /* Total times CV query happened for IBF case */ + /** Total times CV query happened for IBF case */ A_UINT32 cv_total_query_ibf; - /* A valid CV has been found for IBF case */ + /** A valid CV has been found for IBF case */ A_UINT32 cv_found_ibf; - /* A valid CV has not been found for IBF case */ + /** A valid CV has not been found for IBF case */ A_UINT32 cv_not_found_ibf; - /* Expired CV found during query for IBF case */ + /** Expired CV found during query for IBF case */ A_UINT32 cv_expired_during_query_ibf; + /** Total number of times adaptive sounding logic has been queried */ + A_UINT32 adaptive_snd_total_query; + /** + * Total number of times adaptive sounding mcs drop has been computed + * and recorded. + */ + A_UINT32 adaptive_snd_total_mcs_drop[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + /** Total number of times adaptive sounding logic kicked in */ + A_UINT32 adaptive_snd_kicked_in; + /** Total number of times we switched back to normal sounding interval */ + A_UINT32 adaptive_snd_back_to_default; + + /** + * Below are CV correlation feature related stats. + * This feature is used for DL MU MIMO, but is not available + * from certain legacy targets. + */ + + /** number of CV Correlation triggers for online mode */ + A_UINT32 cv_corr_trigger_online_mode; + /** number of CV Correlation triggers for offline mode */ + A_UINT32 cv_corr_trigger_offline_mode; + /** number of CV Correlation triggers for hybrid mode */ + A_UINT32 cv_corr_trigger_hybrid_mode; + /** number of CV Correlation triggers with computation level 0 */ + A_UINT32 cv_corr_trigger_computation_level_0; + /** number of CV Correlation triggers with computation level 1 */ + A_UINT32 cv_corr_trigger_computation_level_1; + /** number of CV Correlation triggers with computation level 2 */ + A_UINT32 cv_corr_trigger_computation_level_2; + /** number of users for which CV Correlation was triggered */ + A_UINT32 cv_corr_trigger_num_users[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; + /** number of streams for which CV Correlation was triggered */ + A_UINT32 cv_corr_trigger_num_streams[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; + /** number of CV Correlation buffers received through IPC tickle */ + A_UINT32 cv_corr_upload_total_buf_received; + /** number of CV Correlation buffers fed back to the IPC ring */ + A_UINT32 cv_corr_upload_total_buf_fed_back; + /** number of CV Correlation buffers for which processing failed */ + A_UINT32 cv_corr_upload_total_processing_failed; + /** + * number of CV Correlation buffers for which processing failed, + * due to no users being present in parsed buffer + */ + A_UINT32 cv_corr_upload_failed_total_users_zero; + /** + * number of CV Correlation buffers for which processing failed, + * due to number of users present in parsed buffer exceeded + * CV_CORR_MAX_NUM_COLUMNS + */ + A_UINT32 cv_corr_upload_failed_total_users_exceeded; + /** + * number of CV Correlation buffers for which processing failed, + * due to peer pointer for parsed peer not available + */ + A_UINT32 cv_corr_upload_failed_peer_not_found; + /** + * number of CV Correlation buffers for which processing encountered, + * Nss of peer exceeding SCHED_ALGO_MAX_SUPPORTED_MUMIMO_NSS + */ + A_UINT32 cv_corr_upload_user_nss_exceeded; + /** + * number of CV Correlation buffers for which processing encountered, + * invalid reverse look up index for fetching CV correlation results + */ + A_UINT32 cv_corr_upload_invalid_lookup_index; + /** number of users present in uploaded CV Correlation results buffer */ + A_UINT32 cv_corr_upload_total_num_users[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; + /** number of streams present in uploaded CV Correlation results buffer */ + A_UINT32 cv_corr_upload_total_num_streams[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; } htt_tx_sounding_stats_tlv; /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SOUNDING_INFO @@ -6944,6 +7217,7 @@ typedef enum { HTT_STATS_RC_MODE_DLMUMIMO = 1, HTT_STATS_RC_MODE_DLOFDMA = 2, HTT_STATS_RC_MODE_ULMUMIMO = 3, + HTT_STATS_RC_MODE_ULOFDMA = 4, } htt_stats_rc_mode; typedef struct { @@ -7360,6 +7634,11 @@ typedef struct { #define HTT_MAX_RX_PKT_CRC_PASS_CNT 8 #define HTT_MAX_PER_BLK_ERR_CNT 20 #define HTT_MAX_RX_OTA_ERR_CNT 14 +#define HTT_MAX_RX_PKT_CNT_EXT 4 +#define HTT_MAX_RX_PKT_CRC_PASS_CNT_EXT 4 +#define HTT_MAX_RX_PKT_MU_CNT 14 +#define HTT_MAX_TX_PKT_CNT 10 +#define HTT_MAX_PHY_TX_ABORT_CNT 10 typedef enum { HTT_STATS_CHANNEL_HALF_RATE = 0x0001, /* Half rate */ @@ -7474,13 +7753,13 @@ typedef struct { /** rx_pkt_cnt - * Received EOP (end-of-packet) count per packet type; * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF - * [6-7]=RSVD + * [6] = EHT; [7]=RSVD; [6] = Applicable only for BE */ A_UINT32 rx_pkt_cnt[HTT_MAX_RX_PKT_CNT]; /** rx_pkt_crc_pass_cnt - * Received EOP (end-of-packet) count per packet type; * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF - * [6-7]=RSVD + * [6] = EHT; [7]=RSVD; [6] = Applicable only for BE */ A_UINT32 rx_pkt_crc_pass_cnt[HTT_MAX_RX_PKT_CRC_PASS_CNT]; /** per_blk_err_cnt - @@ -7500,6 +7779,38 @@ typedef struct { * [9-13]=RSVD */ A_UINT32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT]; + /** rx_pkt_cnt_ext - + * Received EOP (end-of-packet) count per packet type for BE; + * [0] = WUR; [1] = AZ; [2-3]=RVSD + */ + A_UINT32 rx_pkt_cnt_ext[HTT_MAX_RX_PKT_CNT_EXT]; + /** rx_pkt_crc_pass_cnt_ext - + * Received EOP (end-of-packet) count per packet type for BE; + * [0] = WUR; [1] = AZ; [2-3]=RVSD + */ + A_UINT32 rx_pkt_crc_pass_cnt_ext[HTT_MAX_RX_PKT_CRC_PASS_CNT_EXT]; + /** rx_pkt_mu_cnt - + * RX MU MIMO+OFDMA packet count per packet type for BE; + * [0] = 11ax OFDMA; [1] = 11ax OFDMA+MUMIMO; [2] = 11be OFDMA; + * [3] = 11be OFDMA+MUMIMO; [4] = 11ax MIMO; [5] = 11be MIMO; + * [6] = 11ax OFDMA; [7] = 11ax OFDMA+MUMIMO; [8] = 11be OFDMA; + * [9] = 11be OFDMA+MUMIMO; [10] = 11ax MIMO; [11] = 11be MIMO; + * [12-13]=RSVD + */ + A_UINT32 rx_pkt_mu_cnt[HTT_MAX_RX_PKT_MU_CNT]; + /** tx_pkt_cnt - + * num of transfered packet count per packet type; + * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF; + * [6]= EHT; [7] = WUR; [8] = AZ; [9]=RSVD; [6-8] = Applicable only for BE + */ + A_UINT32 tx_pkt_cnt[HTT_MAX_TX_PKT_CNT]; + /** phy_tx_abort_cnt - + * phy tx abort after each tlv; + * [0] = PRE-PHY desc tlv; [1] = PHY desc tlv; [2] = LSIGA tlv; + * [3] = LSIGB tlv; [4] = Per User tlv; [5] = HESIGB tlv; + * [6] = Service tlv; [7] = Tx Packet End tlv; [8-9]=RSVD; + */ + A_UINT32 phy_tx_abort_cnt[HTT_MAX_PHY_TX_ABORT_CNT]; } htt_phy_counters_tlv; typedef struct { @@ -7658,6 +7969,58 @@ typedef struct { /* Considering 320 MHz maximum 16 power levels */ #define HTT_MAX_CH_PWR_INFO_SIZE 16 +#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_M 0x000000ff +#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_S 0 + +#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_GET(_var) \ + (((_var) & HTT_PHY_TPC_STATS_CTL_REGION_GRP_M) >> \ + HTT_PHY_TPC_STATS_CTL_REGION_GRP_S) +#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_REGION_GRP, _val); \ + ((_var) &= ~(HTT_PHY_TPC_STATS_CTL_REGION_GRP_M)); \ + ((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_REGION_GRP_S)); \ + } while (0) + +#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M 0x0000ff00 +#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S 8 + +#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_GET(_var) \ + (((_var) & HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M) >> \ + HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S) +#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_SUB_BAND_INDEX, _val); \ + ((_var) &= ~(HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M)); \ + ((_var) |= ((_val) << HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S)); \ + } while (0) + +#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M 0x00ff0000 +#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S 16 + +#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_GET(_var) \ + (((_var) & HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M) >> \ + HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S) +#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED, _val); \ + ((_var) &= ~(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M)); \ + ((_var) |= ((_val) << HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S)); \ + } while (0) + +#define HTT_PHY_TPC_STATS_CTL_FLAG_M 0xff000000 +#define HTT_PHY_TPC_STATS_CTL_FLAG_S 24 + +#define HTT_PHY_TPC_STATS_CTL_FLAG_GET(_var) \ + (((_var) & HTT_PHY_TPC_STATS_CTL_FLAG_M) >> \ + HTT_PHY_TPC_STATS_CTL_FLAG_S) +#define HTT_PHY_TPC_STATS_CTL_FLAG_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_FLAG, _val); \ + ((_var) &= ~(HTT_PHY_TPC_STATS_CTL_FLAG_M)); \ + ((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_FLAG_S)); \ + } while (0) + typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -7696,6 +8059,33 @@ typedef struct { /** sub-band channels and corresponding Tx-power */ A_UINT32 sub_band_cfreq[HTT_MAX_CH_PWR_INFO_SIZE]; A_UINT32 sub_band_txpower[HTT_MAX_CH_PWR_INFO_SIZE]; + + /** array_gain_cap: + * CTL Array Gain cap, units are dB + * The lower-triangular portion of this square matrix is stored, i.e. + * array element 0 stores matrix element (0,0) + * array element 1 stores matrix element (1,0) + * array element 2 stores matrix element (1,1) + * array element 3 stores matrix element (2,0) + * ... + * array element 35 stores matrix element (7,7) + */ + A_INT32 array_gain_cap[HTT_STATS_MAX_CHAINS * ((HTT_STATS_MAX_CHAINS/2)+1)]; + union { + struct { + A_UINT32 + ctl_region_grp:8, /** Group to which the ctl region belongs */ + sub_band_index:8, /** Frequency subband index */ + /** Array Gain Cap Ext2 feature enablement status */ + array_gain_cap_ext2_enabled:8, + /** ctl_flag: + * 1st bit ULOFDMA supported + * 2nd bit DLOFDMA shared Exception supported + */ + ctl_flag:8; + }; + A_UINT32 ctl_args; + }; } htt_phy_tpc_stats_tlv; /* NOTE: @@ -8558,6 +8948,18 @@ typedef struct _htt_odd_mandatory_muofdma_pdev_stats_tlv { ((_var) |= ((_val) << HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S)); \ } while (0) +typedef enum { + HTT_STATS_SCHED_OFDMA_TXBF = 0, /* 0 */ + HTT_STATS_SCHED_OFDMA_TXBF_IS_SANITY_FAILED, /* 1 */ + HTT_STATS_SCHED_OFDMA_TXBF_IS_EBF_ALLOWED_FAILIED, /* 2 */ + HTT_STATS_SCHED_OFDMA_TXBF_RU_ALLOC_BW_DROP_COUNT, /* 3 */ + HTT_STATS_SCHED_OFDMA_TXBF_INVALID_CV_QUERY_COUNT, /* 4 */ + HTT_STATS_SCHED_OFDMA_TXBF_AVG_TXTIME_LESS_THAN_TXBF_SND_THERHOLD, /* 5 */ + HTT_STATS_SCHED_OFDMA_TXBF_IS_CANDIDATE_KICKED_OUT, /* 6 */ + HTT_STATS_SCHED_OFDMA_TXBF_CV_IMAGE_BUF_INVALID, /* 7 */ + HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX, +} htt_stats_sched_ofdma_txbf_ineligibility_t; + typedef struct { htt_tlv_hdr_t tlv_hdr; /** @@ -8600,6 +9002,7 @@ typedef struct { A_UINT32 dlofdma_disabled_consec_no_mpdus_tried[HTT_NUM_AC_WMM]; /** Num of instances where dl ofdma is disabled because there are consecutive mpdu failure */ A_UINT32 dlofdma_disabled_consec_no_mpdus_success[HTT_NUM_AC_WMM]; + A_UINT32 txbf_ofdma_ineligibility_stat[HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX]; } htt_pdev_sched_algo_ofdma_stats_tlv; typedef struct { @@ -8621,6 +9024,44 @@ typedef struct { A_UINT32 ul_mumimo_trigger_within_bss; } htt_pdev_mbssid_ctrl_frame_stats_tlv; +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /** + * BIT [ 7 : 0] :- mac_id + * Use the HTT_STATS_TDMA_MAC_ID_GET macro to extract + * this bitfield. + * BIT [31 : 8] :- reserved + */ + union { + struct { + A_UINT32 mac_id: 8, + reserved: 24; + }; + A_UINT32 mac_id__word; + }; + + /** Num of Active TDMA schedules */ + A_UINT32 num_tdma_active_schedules; + /** Num of Reserved TDMA schedules */ + A_UINT32 num_tdma_reserved_schedules; + /** Num of Restricted TDMA schedules */ + A_UINT32 num_tdma_restricted_schedules; + /** Num of Unconfigured TDMA schedules */ + A_UINT32 num_tdma_unconfigured_schedules; + /** Num of TDMA slot switches */ + A_UINT32 num_tdma_slot_switches; + /** Num of TDMA EDCA switches */ + A_UINT32 num_tdma_edca_switches; +} htt_pdev_tdma_stats_tlv; + +#define HTT_STATS_TDMA_MAC_ID_M 0x000000ff +#define HTT_STATS_TDMA_MAC_ID_S 0 + +#define HTT_STATS_TDMA_MAC_ID_GET(_var) \ + (((_var) & HTT_STATS_TDMA_MAC_ID_M) >> \ + HTT_STATS_TDMA_MAC_ID_S) + + /*======= Bandwidth Manager stats ====================*/ #define HTT_BW_MGR_STATS_MAC_ID_M 0x000000ff @@ -8756,4 +9197,826 @@ typedef struct { } htt_pdev_bw_mgr_stats_t; +/*============= start MLO UMAC SSR stats ============= { */ + +typedef enum { + HTT_MLO_UMAC_SSR_DBG_POINT_INVALID = 0, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_DISABLE_RXDMA_PREFETCH, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_PMACS_HWMLOS, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_GLOBAL_WSI, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_PMACS_DMAC, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_TCL, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_TQM, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_WBM, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_REO, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_HOST, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_PREREQUISITES, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_PRE_RING_RESET, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_APPLY_SOFT_RESET, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_POST_RING_RESET, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_FW_TQM_CMDQS, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_HOST, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_UMAC_INTERRUPTS, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_WBM, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_REO, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TQM, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_PMACS_DMAC, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TQM_SYNC_CMD, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_GLOBAL_WSI, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_PMACS_HWMLOS, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_ENABLE_RXDMA_PREFETCH, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TCL, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_HOST_ENQ, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_VERIFY_UMAC_RECOVERED, + /* The below debug point values are reserved for future expansion. */ + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED28, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED29, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED30, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED31, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED32, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED33, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED34, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED35, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED36, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED37, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED38, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED39, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED40, + /* + * Due to backwards compatibility requirements, no futher DBG_POINT values + * can be added (but the above reserved values can be repurposed). + */ + HTT_MLO_UMAC_SSR_DBG_POINT_MAX, +} HTT_MLO_UMAC_SSR_DBG_POINTS; + +typedef enum { + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_INVALID = 0, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_PRE_RESET, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_POST_RESET_START, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_POST_RESET_COMPLETE, + /* The below recovery handshake values are reserved for future expansion. */ + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED4, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED5, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED6, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED7, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED8, + /* + * Due to backwards compatibility requirements, no futher + * RECOVERY_HANDSHAKE values can be added (but the above + * reserved values can be repurposed). + */ + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_COUNT, +} HTT_MLO_UMAC_RECOVERY_HANDSHAKES; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 start_ms; + A_UINT32 end_ms; + A_UINT32 delta_ms; + A_UINT32 reserved; + A_UINT32 footprint; /* holds a HTT_MLO_UMAC_SSR_DBG_POINTS value */ + A_UINT32 tqm_hw_tstamp; +} htt_mlo_umac_ssr_dbg_tlv; + +typedef struct { + A_UINT32 last_mlo_htt_handshake_delta_ms; + A_UINT32 max_mlo_htt_handshake_delta_ms; + union { + A_UINT32 umac_recovery_done_mask; + struct { + A_UINT32 pre_reset_disable_rxdma_prefetch : 1, + pre_reset_pmacs_hwmlos : 1, + pre_reset_global_wsi : 1, + pre_reset_pmacs_dmac : 1, + pre_reset_tcl : 1, + pre_reset_tqm : 1, + pre_reset_wbm : 1, + pre_reset_reo : 1, + pre_reset_host : 1, + reset_prerequisites : 1, + reset_pre_ring_reset : 1, + reset_apply_soft_reset : 1, + reset_post_ring_reset : 1, + reset_fw_tqm_cmdqs : 1, + post_reset_host : 1, + post_reset_umac_interrupts : 1, + post_reset_wbm : 1, + post_reset_reo : 1, + post_reset_tqm : 1, + post_reset_pmacs_dmac : 1, + post_reset_tqm_sync_cmd : 1, + post_reset_global_wsi : 1, + post_reset_pmacs_hwmlos : 1, + post_reset_enable_rxdma_prefetch : 1, + post_reset_tcl : 1, + post_reset_host_enq : 1, + post_reset_verify_umac_recovered : 1, + reserved : 5; + } done_mask; + }; +} htt_mlo_umac_ssr_mlo_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + htt_mlo_umac_ssr_mlo_stats_t mlo; +} htt_mlo_umac_ssr_mlo_stats_tlv; + +/* dword0 - b'0 - PRE_RESET_DISABLE_RXDMA_PREFETCH */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M 0x1 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S 0 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S));\ + } while (0) + +/* dword0 - b'1 - PRE_RESET_PMACS_HWMLOS */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_M 0x2 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S 1 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S));\ + } while (0) + +/* dword0 - b'2 - PRE_RESET_GLOBAL_WSI */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_M 0x4 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S 2 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S));\ + } while (0) + +/* dword0 - b'3 - PRE_RESET_PMACS_DMAC */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_M 0x8 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S 3 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S));\ + } while (0) + +/* dword0 - b'4 - PRE_RESET_TCL */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_M 0x10 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S 4 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S));\ + } while (0) + +/* dword0 - b'5 - PRE_RESET_TQM */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_M 0x20 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S 5 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S));\ + } while (0) + +/* dword0 - b'6 - PRE_RESET_WBM */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_M 0x40 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S 6 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S));\ + } while (0) + +/* dword0 - b'7 - PRE_RESET_REO */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_M 0x80 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S 7 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S));\ + } while (0) + +/* dword0 - b'8 - PRE_RESET_HOST */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_M 0x100 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S 8 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S));\ + } while (0) + +/* dword0 - b'9 - RESET_PREREQUISITES */ +#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_M 0x200 +#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S 9 +#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S));\ + } while (0) + +/* dword0 - b'10 - RESET_PRE_RING_RESET */ +#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_M 0x400 +#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S 10 +#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S));\ + } while (0) + +/* dword0 - b'11 - RESET_APPLY_SOFT_RESET */ +#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_M 0x800 +#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S 11 +#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S));\ + } while (0) + +/* dword0 - b'12 - RESET_POST_RING_RESET */ +#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_M 0x1000 +#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S 12 +#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S));\ + } while (0) + +/* dword0 - b'13 - RESET_FW_TQM_CMDQS */ +#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_M 0x2000 +#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S 13 +#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S));\ + } while (0) + +/* dword0 - b'14 - POST_RESET_HOST */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_M 0x4000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S 14 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S));\ + } while (0) + +/* dword0 - b'15 - POST_RESET_UMAC_INTERRUPTS */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_M 0x8000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S 15 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S));\ + } while (0) + +/* dword0 - b'16 - POST_RESET_WBM */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_M 0x10000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S 16 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S));\ + } while (0) + +/* dword0 - b'17 - POST_RESET_REO */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_M 0x20000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S 17 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_REO, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S));\ + } while (0) + +/* dword0 - b'18 - POST_RESET_TQM */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_M 0x40000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S 18 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S));\ + } while (0) + +/* dword0 - b'19 - POST_RESET_PMACS_DMAC */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_M 0x80000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S 19 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S));\ + } while (0) + +/* dword0 - b'20 - POST_RESET_TQM_SYNC_CMD */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_M 0x100000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S 20 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S));\ + } while (0) + +/* dword0 - b'21 - POST_RESET_GLOBAL_WSI */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_M 0x200000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S 21 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S));\ + } while (0) + +/* dword0 - b'22 - POST_RESET_PMACS_HWMLOS */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_M 0x400000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S 22 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S));\ + } while (0) + +/* dword0 - b'23 - POST_RESET_ENABLE_RXDMA_PREFETCH */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_M 0x800000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S 23 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S));\ + } while (0) + +/* dword0 - b'24 - POST_RESET_TCL */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_M 0x1000000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S 24 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S));\ + } while (0) + +/* dword0 - b'25 - POST_RESET_HOST_ENQ */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_M 0x2000000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S 25 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S));\ + } while (0) + +/* dword0 - b'26 - POST_RESET_VERIFY_UMAC_RECOVERED */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_M 0x4000000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S 26 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S));\ + } while (0) + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 last_trigger_request_ms; + A_UINT32 last_start_ms; + A_UINT32 last_start_disengage_umac_ms; + A_UINT32 last_enter_ssr_platform_thread_ms; + A_UINT32 last_exit_ssr_platform_thread_ms; + A_UINT32 last_start_engage_umac_ms; + A_UINT32 last_done_successful_ms; + A_UINT32 post_reset_tqm_sync_cmd_completion_ms; + A_UINT32 htt_sync_mlo_initiate_umac_recovery_ms; + A_UINT32 htt_sync_do_pre_reset_ms; + A_UINT32 htt_sync_do_post_reset_start_ms; + A_UINT32 htt_sync_do_post_reset_complete_ms; +} htt_mlo_umac_ssr_kpi_tstamp_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 htt_sync_start_ms; + A_UINT32 htt_sync_delta_ms; + A_UINT32 post_t2h_start_ms; + A_UINT32 post_t2h_delta_ms; + A_UINT32 post_t2h_msg_read_shmem_ms; + A_UINT32 post_t2h_msg_write_shmem_ms; + A_UINT32 post_t2h_msg_send_msg_to_host_ms; +} htt_mlo_umac_htt_handshake_stats_tlv; + +typedef struct { + /* + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within each element of each of the arrays in + * this struct to determine where the subsequent item resides. + */ + htt_mlo_umac_ssr_dbg_tlv dbg_point[HTT_MLO_UMAC_SSR_DBG_POINT_MAX]; + htt_mlo_umac_htt_handshake_stats_tlv htt_handshakes[HTT_MLO_UMAC_RECOVERY_HANDSHAKE_COUNT]; +} htt_mlo_umac_ssr_kpi_delta_stats_t; + +typedef struct { + /* + * Since each item within htt_mlo_umac_ssr_kpi_delta_stats_t has its own + * TLV header, and since no additional fields are added in this struct + * beyond the htt_mlo_umac_ssr_kpi_delta_stats_t info, no additional + * TLV header is needed. + * + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within each item inside the + * htt_mlo_umac_ssr_kpi_delta_stats_t to determine where the subsequent + * item resides. + */ + htt_mlo_umac_ssr_kpi_delta_stats_t kpi_delta; +} htt_mlo_umac_ssr_kpi_delta_stats_tlv; + +typedef struct { + A_UINT32 last_e2e_delta_ms; + A_UINT32 max_e2e_delta_ms; + A_UINT32 per_handshake_max_allowed_delta_ms; + /* Total done count */ + A_UINT32 total_success_runs_cnt; + A_UINT32 umac_recovery_in_progress; + /* Count of Disengaged in Pre reset */ + A_UINT32 umac_disengaged_count; + /* Count of UMAC Soft/Control Reset */ + A_UINT32 umac_soft_reset_count; + /* Count of Engaged in Post reset */ + A_UINT32 umac_engaged_count; +} htt_mlo_umac_ssr_common_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + htt_mlo_umac_ssr_common_stats_t cmn; +} htt_mlo_umac_ssr_common_stats_tlv; + +typedef struct { + A_UINT32 trigger_requests_count; + A_UINT32 trigger_count_for_umac_hang; + A_UINT32 trigger_count_for_mlo_target_recovery_mode1; + A_UINT32 trigger_count_for_unknown_signature; + A_UINT32 total_trig_dropped; + A_UINT32 trigger_count_for_unit_test_direct_trigger; + A_UINT32 trigger_count_for_tx_de_wdg_dummy_frame_tout; + A_UINT32 trigger_count_for_peer_delete_wdg_dummy_frame_tout; + A_UINT32 trigger_count_for_reo_hang; + A_UINT32 trigger_count_for_tqm_hang; + A_UINT32 trigger_count_for_tcl_hang; + A_UINT32 trigger_count_for_wbm_hang; +} htt_mlo_umac_ssr_trigger_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + htt_mlo_umac_ssr_trigger_stats_t trigger; +} htt_mlo_umac_ssr_trigger_stats_tlv; + +typedef struct { + /* + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within each element to determine where the + * subsequent element resides. + */ + htt_mlo_umac_ssr_kpi_delta_stats_tlv kpi_delta_tlv; + htt_mlo_umac_ssr_kpi_tstamp_stats_tlv kpi_tstamp_tlv; +} htt_mlo_umac_ssr_kpi_stats_t; + +typedef struct { + /* + * Since the embedded sub-struct within htt_mlo_umac_ssr_kpi_stats_tlv + * has its own TLV header, and since no additional fields are added in + * this struct beyond the htt_mlo_umac_ssr_kpi_stats_t info, no additional + * TLV header is needed. + * + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within the htt_mlo_umac_ssr_kpi_stats_t sub-struct + * to determine how much data is present for this struct. + */ + htt_mlo_umac_ssr_kpi_stats_t kpi; +} htt_mlo_umac_ssr_kpi_stats_tlv; + +typedef struct { + /* + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within each element to determine where the + * subsequent element resides. + */ + htt_mlo_umac_ssr_trigger_stats_tlv trigger_tlv; + htt_mlo_umac_ssr_kpi_stats_tlv kpi_tlv; + htt_mlo_umac_ssr_mlo_stats_tlv mlo_tlv; + htt_mlo_umac_ssr_common_stats_tlv cmn_tlv; +} htt_mlo_umac_ssr_stats_tlv; + +/*============= end MLO UMAC SSR stats ============= } */ + +typedef struct { + A_UINT32 total_done; + A_UINT32 trigger_requests_count; + A_UINT32 total_trig_dropped; + A_UINT32 umac_disengaged_count; + A_UINT32 umac_soft_reset_count; + A_UINT32 umac_engaged_count; + A_UINT32 last_trigger_request_ms; + A_UINT32 last_start_ms; + A_UINT32 last_start_disengage_umac_ms; + A_UINT32 last_enter_ssr_platform_thread_ms; + A_UINT32 last_exit_ssr_platform_thread_ms; + A_UINT32 last_start_engage_umac_ms; + A_UINT32 last_done_successful_ms; + A_UINT32 last_e2e_delta_ms; + A_UINT32 max_e2e_delta_ms; + A_UINT32 trigger_count_for_umac_hang; + A_UINT32 trigger_count_for_mlo_quick_ssr; + A_UINT32 trigger_count_for_unknown_signature; + A_UINT32 post_reset_tqm_sync_cmd_completion_ms; + A_UINT32 htt_sync_mlo_initiate_umac_recovery_ms; + A_UINT32 htt_sync_do_pre_reset_ms; + A_UINT32 htt_sync_do_post_reset_start_ms; + A_UINT32 htt_sync_do_post_reset_complete_ms; +} htt_umac_ssr_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + htt_umac_ssr_stats_t stats; +} htt_umac_ssr_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 svc_class_id; + /* codel_drops: + * How many times have MSDU queues belonging to this service class + * dropped their head MSDU due to the queue's latency being above + * the CoDel latency limit specified for the service class throughout + * the full CoDel latency statistics collection window. + */ + A_UINT32 codel_drops; + /* codel_no_drops: + * How many times have MSDU queues belonging to this service class + * completed a CoDel latency statistics collection window and + * concluded that no head MSDU drop is needed, due to the MSDU queue's + * latency being under the limit specified for the service class at + * some point during the window. + */ + A_UINT32 codel_no_drops; +} htt_codel_svc_class_stats_tlv; + +#define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_M 0x0000FFFF +#define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S 0 + +#define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_GET(_var) \ + (((_var) & HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_M) >> \ + HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S) +#define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM, _val); \ + ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S)); \ + } while (0) + +#define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_M 0x00FF0000 +#define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S 16 + +#define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_GET(_var) \ + (((_var) & HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_M) >> \ + HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S) +#define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID, _val); \ + ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S)); \ + } while (0) + +#define HTT_CODEL_MSDUQ_STATS_DROPS_M 0x0000FFFF +#define HTT_CODEL_MSDUQ_STATS_DROPS_S 0 + +#define HTT_CODEL_MSDUQ_STATS_DROPS_GET(_var) \ + (((_var) & HTT_CODEL_MSDUQ_STATS_DROPS_M) >> \ + HTT_CODEL_MSDUQ_STATS_DROPS_S) +#define HTT_CODEL_MSDUQ_STATS_DROPS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_DROPS, _val); \ + ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_DROPS_S)); \ + } while (0) + +#define HTT_CODEL_MSDUQ_STATS_NO_DROPS_M 0xFFFF0000 +#define HTT_CODEL_MSDUQ_STATS_NO_DROPS_S 16 + +#define HTT_CODEL_MSDUQ_STATS_NO_DROPS_GET(_var) \ + (((_var) & HTT_CODEL_MSDUQ_STATS_NO_DROPS_M) >> \ + HTT_CODEL_MSDUQ_STATS_NO_DROPS_S) +#define HTT_CODEL_MSDUQ_STATS_NO_DROPS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_NO_DROPS, _val); \ + ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_NO_DROPS_S)); \ + } while (0) + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + union { + A_UINT32 id__word; + struct { + A_UINT32 tx_flow_num: 16, /* FW's MSDU queue ID */ + svc_class_id: 8, + reserved: 8; + }; + }; + union { + A_UINT32 stats__word; + struct { + A_UINT32 + codel_drops: 16, + codel_no_drops: 16; + }; + }; +} htt_codel_msduq_stats_tlv; + +/*===================== start MLO stats ====================*/ + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 pref_link_num_sec_link_sched; + A_UINT32 pref_link_num_pref_link_timeout; + A_UINT32 pref_link_num_pref_link_sch_delay_ipc; + A_UINT32 pref_link_num_pref_link_timeout_ipc; +} htt_mlo_sched_stats_tlv; + +/* STATS_TYPE : HTT_DBG_MLO_SCHED_STATS + * TLV_TAGS: + * - HTT_STATS_MLO_SCHED_STATS_TAG + */ +/* NOTE: + * This structure is for documentation, and cannot be safely used directly. + * Instead, use the constituent TLV structures to fill/parse. + */ +typedef struct _htt_mlo_sched_stats { + htt_mlo_sched_stats_tlv preferred_link_stats; +} htt_mlo_sched_stats_t; + +#define HTT_STATS_HWMLO_MAX_LINKS 6 +#define HTT_STATS_MLO_MAX_IPC_RINGS 7 + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 mlo_ipc_ring_full_cnt[HTT_STATS_HWMLO_MAX_LINKS][HTT_STATS_MLO_MAX_IPC_RINGS]; +} htt_pdev_mlo_ipc_stats_tlv; + +/* STATS_TYPE : HTT_DBG_MLO_IPC_STATS + * TLV_TAGS: + * - HTT_STATS_PDEV_MLO_IPC_STATS_TAG + */ +/* NOTE: + * This structure is for documentation, and cannot be safely used directly. + * Instead, use the constituent TLV structures to fill/parse. + */ +typedef struct _htt_mlo_ipc_stats { + htt_pdev_mlo_ipc_stats_tlv mlo_ipc_stats; +} htt_pdev_mlo_ipc_stats_t; + +/*===================== end MLO stats ======================*/ + +typedef enum { + HTT_CTRL_PATH_STATS_CAL_TYPE_ADC = 0x0, + HTT_CTRL_PATH_STATS_CAL_TYPE_DAC = 0x1, + HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS = 0x2, + HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR = 0x3, + HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO = 0x4, + HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ = 0x5, + HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO = 0x6, + HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ = 0x7, + HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ = 0x8, + HTT_CTRL_PATH_STATS_CAL_TYPE_IM2 = 0x9, + HTT_CTRL_PATH_STATS_CAL_TYPE_LNA = 0xa, + HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO = 0xb, + HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ = 0xc, + HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS = 0xd, + HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY = 0xe, + HTT_CTRL_PATH_STATS_CAL_TYPE_IBF = 0xf, + HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL = 0x10, + HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ = 0x11, + HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM = 0x12, + HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL = 0x13, + HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ = 0x14, + HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER = 0x15, + HTT_CTRL_PATH_STATS_CAL_TYPE_PEF = 0x16, + HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP = 0x17, + HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC = 0x18, + + /* add new cal types above this line */ + HTT_CTRL_PATH_STATS_CAL_TYPE_INVALID = 0xFF +} htt_ctrl_path_stats_cal_type_ids; + +#define HTT_RETURN_STRING(str) case ((str)): return (A_UINT8 *)(# str); + +#define HTT_GET_BITS(_val, _index, _num_bits) \ + (((_val) >> (_index)) & ((1 << (_num_bits)) - 1)) + +#define HTT_CTRL_PATH_CALIBRATION_STATS_CAL_TYPE_GET(cal_info) \ + HTT_GET_BITS(cal_info, 0, 8) + +/* + * Used by some hosts to print names of cal type, based on + * htt_ctrl_path_cal_type_ids values specified in + * htt_ctrl_path_calibration_stats_struct in ctrl_path_stats event msg. + */ +#ifdef HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS +static INLINE A_UINT8 *htt_ctrl_path_cal_type_id_to_name(A_UINT32 cal_type_id) +{ + switch (cal_type_id) + { + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_ADC); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DAC); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IM2); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_LNA); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IBF); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PEF); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC); + } + + return (A_UINT8 *) "HTT_CTRL_PATH_STATS_CAL_TYPE_UNKNOWN"; +} +#endif /* HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS */ + + #endif /* __HTT_STATS_H__ */ diff --git a/drivers/staging/fw-api/fw/wlan_defs.h b/drivers/staging/fw-api/fw/wlan_defs.h index abb978c19516001273d92ee98e9ec2906b899e27..5024efe702ffd5210a25d34e3ea2fdbfa68eab25 100755 --- a/drivers/staging/fw-api/fw/wlan_defs.h +++ b/drivers/staging/fw-api/fw/wlan_defs.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2016, 2018-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -149,7 +149,7 @@ typedef enum { MODE_11AX_HE80_2G = 23, #endif -#if defined(SUPPORT_11BE) && SUPPORT_11BE +#if (defined(SUPPORT_11BE) && SUPPORT_11BE) || defined(SUPPORT_11BE_ROM) MODE_11BE_EHT20 = 24, MODE_11BE_EHT40 = 25, MODE_11BE_EHT80 = 26, @@ -248,7 +248,7 @@ typedef enum { ((mode) == MODE_11AX_HE80_2G)) #endif /* SUPPORT_11AX */ -#if defined(SUPPORT_11BE) && SUPPORT_11BE +#if (defined(SUPPORT_11BE) && SUPPORT_11BE) || defined(SUPPORT_11BE_ROM) #define IS_MODE_EHT(mode) (((mode) == MODE_11BE_EHT20) || \ ((mode) == MODE_11BE_EHT40) || \ ((mode) == MODE_11BE_EHT80) || \ @@ -458,6 +458,10 @@ typedef struct { A_UINT32 low_5ghz_chan; A_UINT32 high_5ghz_chan; A_UINT32 wireless_modes_ext; /* REGDMN MODE ext */ + A_UINT32 low_2ghz_chan_ext; + A_UINT32 high_2ghz_chan_ext; + A_UINT32 low_5ghz_chan_ext; + A_UINT32 high_5ghz_chan_ext; } HAL_REG_CAPABILITIES; #ifdef NUM_SPATIAL_STREAM @@ -972,8 +976,7 @@ struct wlan_dbg_mem_stats { }; struct wlan_dbg_peer_stats { - - A_INT32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ + A_INT32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ }; /* @@ -1017,7 +1020,7 @@ typedef struct { * TEMPORARY: leave rssi_chain3 in place for AR900B builds until code using * rssi_chain3 has been converted to use wlan_dbg_rx_rate_info_v2_t. */ - A_UINT32 rssi_chain3; + A_UINT32 rssi_chain3; } wlan_dbg_rx_rate_info_v1b_t; #if defined(AR900B) @@ -1744,8 +1747,15 @@ A_COMPILE_TIME_ASSERT(check_mlo_glb_link_info_8byte_size_quantum, typedef enum { MLO_SHMEM_CRASH_PARTNER_CHIPS = 1, + MLO_SHMEM_CRASH_SW_PANIC = 2, + MLO_SHMEM_CRASH_SW_ASSERT = 3, } MLO_SHMEM_CHIP_CRASH_REASON; +typedef enum { + MLO_SHMEM_RECOVERY_CRASH_PARTNER_CHIPS = 1, + MLO_SHMEM_RECOVER_NON_MLO_MODE = 2, +} MLO_SHMEM_CHIP_RECOVERY_MODE; + /* glb link info structures used for scratchpad memory (crash and recovery) */ typedef struct { /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_PER_CHIP_CRASH_INFO */ @@ -1754,17 +1764,29 @@ typedef struct { * crash reason, takes value in enum MLO_SHMEM_CHIP_CRASH_REASON */ A_UINT32 crash_reason; + /** + * crash reason, takes value in enum MLO_SHMEM_CHIP_RECOVERY_MODE + */ + A_UINT32 recovery_mode; + /* reserved: added for padding to A_UINT64 size, available for future use */ + A_UINT32 reserved; } mlo_glb_per_chip_crash_info; A_COMPILE_TIME_ASSERT(check_mlo_glb_per_chip_crash_info, (((sizeof(mlo_glb_per_chip_crash_info) % sizeof(A_UINT64) == 0x0)))); /** Helper macro for params GET/SET of mlo_glb_chip_crash_info */ -#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 0, 2) -#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 0, 2, value) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_GET(chip_info) \ + (MLO_SHMEM_GET_BITS(chip_info, 0, 2) + \ + (MLO_SHMEM_GET_BITS(chip_info, 12, 4) << 2)) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_SET(chip_info, value) \ + do { \ + MLO_SHMEM_SET_BITS(chip_info, 0, 2, ((value) & 0x03)); \ + MLO_SHMEM_SET_BITS(chip_info, 12, 4, ((value) >> 2)); \ +} while (0) -#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 2, 3) -#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 2, 3, value) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 2, 8) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 2, 8, value) typedef struct { /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO */ @@ -1775,7 +1797,18 @@ typedef struct { * * [1:0]: no_of_chips * [4:2]: valid_chip_bmap - * [31:6]: reserved + * For number of chips beyond 3, extension fields are added. + * To maintain backward compatibility, with 3 chip board and + * old host driver, valid chip bmap is extended in continuation from + * existing bit 4 onwards, while extending no_of_chips information + * would overlap with old valid_chip_bmap, hence extended from + * bit 12:15. Now no_of_chip will have two parts, lower 2 bits from 0-1 and + * upper 4 bits from 12-15. SET-GET macros are modified accordingly. + * This helps in no change in respective processing files and don't need + * to maintain two copy of information for backward compatibility. + * [9:5]: valid_chip_bmap_ext + * [15:12]: no_of_chips_ext + * [31:16]: reserved */ A_UINT32 chip_info; /* This TLV is followed by array of mlo_glb_per_chip_crash_info: @@ -1816,5 +1849,12 @@ typedef struct { A_COMPILE_TIME_ASSERT(check_mlo_glb_h_shmem_8byte_size_quantum, (((sizeof(mlo_glb_h_shmem) % sizeof(A_UINT64) == 0x0)))); +/** 2 word representation of MAC addr */ +typedef struct _wmi_mac_addr { + /** upper 4 bytes of MAC address */ + A_UINT32 mac_addr31to0; + /** lower 2 bytes of MAC address */ + A_UINT32 mac_addr47to32; +} wmi_mac_addr; #endif /* __WLANDEFS_H__ */ diff --git a/drivers/staging/fw-api/fw/wlan_module_ids.h b/drivers/staging/fw-api/fw/wlan_module_ids.h index 188b0b0bb6b5fbc8979fd0ea866aebeddc899b7c..b8ebd0e90a91b489cc83557b5e3ef0880ee66e9b 100644 --- a/drivers/staging/fw-api/fw/wlan_module_ids.h +++ b/drivers/staging/fw-api/fw/wlan_module_ids.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -151,6 +152,8 @@ typedef enum { WLAN_MODULE_SCHED_ALGO_SAWF, /* 0x6f */ WLAN_MODULE_BAR, /* 0x70 */ WLAN_MODULE_SMART_TX, /* 0x71 */ + WLAN_MODULE_BRIDGE_PEER, /* 0x72 */ + WLAN_MODULE_AUX_MAC_MGR, /* 0x73 */ WLAN_MODULE_ID_MAX, diff --git a/drivers/staging/fw-api/fw/wmi_services.h b/drivers/staging/fw-api/fw/wmi_services.h index 3f9897ab60b447179037cac50808b5964818aa62..53be26388e6fddf2d000dff0eea1faf373077abe 100644 --- a/drivers/staging/fw-api/fw/wmi_services.h +++ b/drivers/staging/fw-api/fw/wmi_services.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -607,7 +607,41 @@ typedef enum { WMI_SERVICE_RESTRICTED_TWT = 354, /* Support for R-TWT feature */ WMI_SERVICE_SLO_SUPPORTED = 355, /* Support for Single Link 11BE */ WMI_SERVICE_RTT_11AZ_TB_RSTA_SUPPORT = 356, /* FW support for 11AZ trigger based ranging Responder (RSTA) role */ - + WMI_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357, + WMI_SERVICE_DETERMINISTIC_SCHEDULER_LEVEL0 = 358, /* FW supports 12.2 level scheduler mode disable commands and stats */ + WMI_SERVICE_COORDINATED_AP_TDMA = 359, /* Support for Coordinated-AP TDMA feature */ + WMI_SERVICE_HPA_SUPPORT = 360, /* Support for Host Platform Authentication */ + WMI_SERVICE_WMSK_COMPACTION_RX_TLVS = 361, /* Support word mask subscription for rx tlv compaction */ + WMI_SERVICE_PRE_RX_TO = 362, /* Support for Pre RX timeout */ + WMI_SERVICE_TDLS_CONCURRENCY_SUPPORT = 363, /* Support for TDLS concurrency in FW */ + WMI_SERVICE_SELF_MLD_ROAM_BETWEEN_DBS_AND_HBS = 364, /* Suppport roam between DBS(2G+5G/6G) to HBS(5G+6G) with self AP MLD. */ + WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT = 365, /* Support rx peer meta data v1a and v1b */ + WMI_SERVICE_CFR_CAPTURE_PDEV_ID_SOC = 366, /* Host can send PDEV_ID_SOC with CFR capture request and FW can derive pdev_id from TA address */ + WMI_SERVICE_11BE_MLO_TDLS_SUPPORT = 367, /* Indicates FW supports 11be MLO TDLS. Host should enable 11be on TDLS only when FW indicates the support. */ + WMI_SERVICE_MANUAL_ULOFDMA_TRIGGER_SUPPORT = 368, /* Support for Host triggered Manual UL OFDMA trigger frame feature */ + WMI_SERVICE_STANDALONE_SOUND = 369, /* FW supports standalone sounding */ + WMI_SERVICE_AFC_RESP_BINARY_FORMAT_SUPPORTED = 370, /* Service bit to indicate the supported AFC payload response format */ + WMI_SERVICE_CCA_BUSY_INFO_FOREACH_20MHZ = 371, /* FW supports reporting of CCA busy info for each 20Mhz subband of wideband scan channel */ + WMI_SERVICE_MLO_TSF_SYNC = 372, /* FW supports TSF sync across multiple chips */ + WMI_SERVICE_RF_PATH_SEL_INIT_SUPPORT = 373, /* FW supports RF Path selection using WMI Init command field */ + WMI_SERVICE_VDEV_PARAM_CHWIDTH_WITH_NOTIFY_SUPPORT = 374, /* FW supports VDEV param channel width switch with OMN/OMI notification */ + WMI_SERVICE_RESTRICTED_TWT_REQUESTER = 375, /* Indicates FW supports Restricted TWT REQUESTER */ + WMI_SERVICE_RESTRICTED_TWT_RESPONDER = 376, /* Indicates FW supports Restricted TWT RESPONDER */ + WMI_SERVICE_AUX_MAC_SUPPORT = 377, + WMI_SERVICE_NAN_PAIRING_PEER_CREATE_BY_HOST = 378, /* Indicate FW supports creation of PASN Peer by Host for NAN pairing usecase */ + WMI_SERVICE_MLO_TID_TO_LINK_MAPPING_SUPPORT = 379, /* Indicates FW supports TID-TO-LINK mapping */ + WMI_SERVICE_PER_LINK_STATS_SUPPORT = 380, /* Indicates FW supports per link stats for MLO */ + WMI_SERVICE_N_LINK_MLO_SUPPORT = 381, /* Indicate FW supports N MLO link & vdev re-purpose between links */ + WMI_SERVICE_ATF_MAX_CLIENT_512_SUPPORT = 382, /* Indicates FW supports maximum of 512 clients when ATF is enabled */ + WMI_SERVICE_FISA_DYNAMIC_MSDU_AGGR_SIZE_SUPPORT = 383, /* Indicates FW support for FISA aggregation size up to 64 instead of only 16 */ + WMI_SERVICE_BRIDGE_VDEV_SUPPORT = 384, /* Indicated FW supports Bridge VDEV */ + WMI_SERVICE_MLO_MODE1_RECOVERY_SUPPORTED = 385, /* Indicate fw support for mlo mode1 recovery */ + WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT = 386, /* FW support to check tx power stats per PPDU */ + WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT = 387, /* Indicate FW support to disable wds peer map/unmap events */ + WMI_SERVICE_PDEV_WSI_STATS_INFO_SUPPORT = 388, /* Support for WSI Stats Info. */ + WMI_SERVICE_MULTIPLE_RF_PATH_SOC_SUPPORT = 389, /* Indicates FW supports Multiple RF Path on SOC Level */ + WMI_SERVICE_RADAR_FLAGS_SUPPORT = 390, /* Indicates FW supports radar flags, such as full bandwidth need put to NOL */ + WMI_SERVICE_XPAN_SUPPORT = 391, /* Indicate FW support XPAN configuration */ WMI_MAX_EXT2_SERVICE diff --git a/drivers/staging/fw-api/fw/wmi_tlv_defs.h b/drivers/staging/fw-api/fw/wmi_tlv_defs.h index ef475482e80b1593819e25578b3e0e23c72bb81f..21ca4d8b1cb197cfc329bc51e89c97062b2ce6a3 100644 --- a/drivers/staging/fw-api/fw/wmi_tlv_defs.h +++ b/drivers/staging/fw-api/fw/wmi_tlv_defs.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2010-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -1120,11 +1120,23 @@ typedef enum { WMITLV_TAG_STRUC_wmi_twt_nudge_dialog_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_twt_nudge_dialog_complete_event_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_pdev_event_fixed_param = + WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_pdev_cmd_fixed_param = + WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_vdev_event_fixed_param = + WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param, WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_vdev_cmd_fixed_param = + WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_peer_event_fixed_param = + WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param, WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_peer_cmd_fixed_param = + WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_roam_msg_info_tlv_param, WMITLV_TAG_STRUC_wmi_vdev_set_tpc_power_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_vdev_ch_power_info, @@ -1330,8 +1342,68 @@ typedef enum { WMITLV_TAG_STRUC_wmi_ctrl_path_pmlo_stats_struct, WMITLV_TAG_STRUC_wmi_ctrl_path_cfr_stats_struct, WMITLV_TAG_STRUC_WMI_COEX_FIX_CHANNEL_CAPABILITIES, + WMITLV_TAG_STRUC_wmi_peer_sched_mode_disable_fixed_param, + WMITLV_TAG_STRUC_wmi_per_peer_sched_mode_disable, + WMITLV_TAG_STRUC_wmi_esl_egid_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_tdma_schedule_request_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_hpa_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_hpa_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_bulk_set_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_preferred_link_map, + WMITLV_TAG_STRUC_wmi_scan_blanking_params_info, + WMITLV_TAG_STRUC_wmi_peer_list, + WMITLV_TAG_STRUC_wmi_ctrl_path_t2lm_stats_struct, + WMITLV_TAG_STRUC_wmi_mlo_vdev_get_link_info_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info_event_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info, + WMITLV_TAG_STRUC_wmi_vdev_set_manual_su_trig_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_peer_link_control_param, + WMITLV_TAG_STRUC_wmi_dma_buf_release_cv_upload_meta_data, + WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_ctrl_path_blanking_stats_struct, + WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo, + WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_cca_busy_subband_info, + WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ctrl_path_peer_stats_struct, + WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ctrl_path_vdev_stats_struct, + WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_event_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_link_bss_param, + WMITLV_TAG_STRUC_wmi_mlo_set_link_bss_params_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_link_switch_req_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_new_primary_link_peer_info, + WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_compl_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_status, + WMITLV_TAG_STRUC_wmi_atf_group_info_v2, + WMITLV_TAG_STRUC_wmi_atf_peer_info_v2, + WMITLV_TAG_STRUC_wmi_mlo_link_recommendation_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_peer_recommended_links, + WMITLV_TAG_STRUC_wmi_aux_dev_capabilities, + WMITLV_TAG_STRUC_wmi_nan_oem_data_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_nan_oem_data_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_enhanced_aoa_gain_phase_data_hdr, + WMITLV_TAG_STRUC_wmi_ctrl_path_sta_rrm_stats_struct, + WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param, + WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param, + WMITLV_TAG_STRUC_WMI_RADAR_FLAGS, + WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data, + WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_trigger_reason_tlv_param, } WMITLV_TAG_ID; - /* * IMPORTANT: Please add _ALL_ WMI Commands Here. * Otherwise, these WMI TLV Functions will be process them. @@ -1844,6 +1916,29 @@ typedef enum { OP(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID) \ OP(WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID) \ OP(WMI_TAS_POWER_HISTORY_CMDID) \ + OP(WMI_PEER_SCHED_MODE_DISABLE_CMDID) \ + OP(WMI_ESL_EGID_CMDID) \ + OP(WMI_TDMA_SCHEDULE_REQUEST_CMDID) \ + OP(WMI_HPA_CMDID) \ + OP(WMI_PDEV_SET_TGTR2P_TABLE_CMDID) \ + OP(WMI_PEER_BULK_SET_CMDID) \ + OP(WMI_MLO_VDEV_GET_LINK_INFO_CMDID) \ + OP(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID) \ + OP(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID) \ + OP(WMI_VDEV_STANDALONE_SOUND_CMDID) \ + OP(WMI_PDEV_SET_RF_PATH_CMDID) \ + OP(WMI_VDEV_PAUSE_CMDID) \ + OP(WMI_GPIO_STATE_REQ_CMDID) \ + OP(WMI_VENDOR_PDEV_CMDID) \ + OP(WMI_VENDOR_VDEV_CMDID) \ + OP(WMI_VENDOR_PEER_CMDID) \ + OP(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID) \ + OP(WMI_MLO_LINK_RECOMMENDATION_CMDID) \ + OP(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID) \ + OP(WMI_MLO_LINK_SWITCH_CONF_CMDID) \ + OP(WMI_NAN_OEM_DATA_CMDID) \ + OP(WMI_PDEV_WSI_STATS_INFO_CMDID) \ + OP(WMI_CSA_EVENT_STATUS_INDICATION_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -2142,6 +2237,25 @@ typedef enum { OP(WMI_MLO_LINK_REMOVAL_EVENTID) \ OP(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID) \ OP(WMI_TAS_POWER_HISTORY_EVENTID) \ + OP(WMI_HPA_EVENTID) \ + OP(WMI_PDEV_SET_TGTR2P_TABLE_EVENTID) \ + OP(WMI_CSA_IE_RECEIVED_EVENTID) \ + OP(WMI_MLO_VDEV_LINK_INFO_EVENTID) \ + OP(WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID) \ + OP(WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID) \ + OP(WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID) \ + OP(WMI_MLO_LINK_DISABLE_REQUEST_EVENTID) \ + OP(WMI_GPIO_STATE_RES_EVENTID) \ + OP(WMI_VENDOR_PDEV_EVENTID) \ + OP(WMI_VENDOR_VDEV_EVENTID) \ + OP(WMI_VENDOR_PEER_EVENTID) \ + OP(WMI_PDEV_SET_RF_PATH_RESP_EVENTID) \ + OP(WMI_ROAM_SYNCH_KEY_EVENTID) \ + OP(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID) \ + OP(WMI_MLO_LINK_SWITCH_REQUEST_EVENTID) \ + OP(WMI_NAN_OEM_DATA_EVENTID) \ + OP(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID) \ + OP(WMI_MLO_LINK_STATE_SWITCH_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -2977,6 +3091,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_CONFIG_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_output_cmd_fixed_param, wmi_gpio_output_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_OUTPUT_CMDID); +/* GPIO State Req Cmd */ +#define WMITLV_TABLE_WMI_GPIO_STATE_REQ_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param, wmi_gpio_state_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_STATE_REQ_CMDID); + /* Antenna Controller config Cmd */ #define WMITLV_TABLE_WMI_ANT_CONTROLLER_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ant_controller_cmd_fixed_param, wmi_ant_controller_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -3498,7 +3617,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_PEER_UPDATE_CMDID); /* Enable/Disable TDLS Offchannel Cmd */ #define WMITLV_TABLE_WMI_TDLS_SET_OFFCHAN_MODE_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_set_offchan_mode_cmd_fixed_param, \ - wmi_tdls_set_offchan_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + wmi_tdls_set_offchan_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, peer_chan_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_SET_OFFCHAN_MODE_CMDID); @@ -3766,6 +3886,13 @@ WMITLV_CREATE_PARAM_STRUC(WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_host_config_param, host_config, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_CMDID); +/* NAN OEM Data Cmd */ +#define WMITLV_TABLE_WMI_NAN_OEM_DATA_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_oem_data_cmd_fixed_param, wmi_nan_oem_data_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_nan_oem_data_hdr, nan_oem_data_hdr, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_oem_data_buffer, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_NAN_OEM_DATA_CMDID); + /* NAN Data Get Capabilities Cmd */ #define WMITLV_TABLE_WMI_NDI_GET_CAP_REQ_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndi_get_cap_req_fixed_param, wmi_ndi_get_cap_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) @@ -4347,6 +4474,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TX_FILTER_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_pn_mgmt_rx_filter_cmd_fixed_param, wmi_vdev_pn_mgmt_rx_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PN_MGMT_RX_FILTER_CMDID); +#define WMITLV_TABLE_WMI_ESL_EGID_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_esl_egid_cmd_fixed_param, wmi_esl_egid_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_ESL_EGID_CMDID); + /* update a wds (4 address) entry */ #define WMITLV_TABLE_WMI_PEER_UPDATE_WDS_ENTRY_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_update_wds_entry_cmd_fixed_param, wmi_peer_update_wds_entry_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -4388,7 +4519,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_FWTEST_CMDID); /* ATF PEER REQUEST commands. */ #define WMITLV_TABLE_WMI_PEER_ATF_REQUEST_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_atf_request_fixed_param, wmi_peer_atf_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_peer_info, peer_info, WMITLV_SIZE_VAR) +WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_peer_info, peer_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_peer_info_v2, peer_info_v2, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ATF_REQUEST_CMDID); #define WMITLV_TABLE_WMI_VDEV_TID_LATENCY_CONFIG_CMDID(id,op,buf,len) \ @@ -4404,7 +4536,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TID_LATENCY_CONFIG_CMDID); /* ATF Group Request commands */ #define WMITLV_TABLE_WMI_ATF_SSID_GROUPING_REQUEST_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_atf_ssid_grp_request_fixed_param, wmi_atf_ssid_grp_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_group_info, group_info, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_group_info, group_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_group_info_v2, group_info_v2, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ATF_SSID_GROUPING_REQUEST_CMDID); /* ATF Group WMM Request commands */ @@ -4506,7 +4639,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_PEER_STATS_INFO_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_ids, WMITLV_SIZE_VAR)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, mac_addr_list, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, twt_dialog_ids, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_addr_read_args, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_addr_read_args, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, peer_ids, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_CTRL_PATH_STATS_CMDID); /* Request Halphy Stats through Ctrl Path */ @@ -4781,6 +4915,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CFR_CAPTURE_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_chan_width_peer_list, peer_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CHAN_WIDTH_SWITCH_CMDID); +/* BULK Peer Set command */ +#define WMITLV_TABLE_WMI_PEER_BULK_SET_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_bulk_set_cmd_fixed_param, wmi_peer_bulk_set_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_list, peer_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_BULK_SET_CMDID); + /* OBSS_PD Spatial_Reuse Set Default OBSS Thresholds */ #define WMITLV_TABLE_WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param, wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -5013,7 +5153,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ENABLE_DURATION_BASED_TX_MODE_SELECTION_CMDID WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_set_active_cmd_fixed_param, wmi_mlo_link_set_active_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_set_active_link_number_param, link_number_param, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_id_bitmap, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_id_bitmap2, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_id_bitmap2, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap2, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_ACTIVE_CMDID); /* Request DPD Status */ @@ -5050,7 +5192,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_TEARDOWN_CMDID); /** WMI cmd used to setup Tid to Link Mapping for a MLO Peer */ #define WMITLV_TABLE_WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tid_to_link_map_fixed_param, wmi_peer_tid_to_link_map_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tid_to_link_map, tid_to_link_map, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tid_to_link_map, tid_to_link_map, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_preferred_link_map, peer_preferred_link_map, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_peer_link_control_param, mlo_peer_link_control_param, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID); /** WMI cmd used to setup Tid to Link Mapping for a vdev */ @@ -5059,6 +5203,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_ap_vdev_tid_to_link_map_ie_info, mlo_vdev_tid_to_link_map_ie_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID); +/** WMI cmd used to set up Tid to Link Mapping for a vdev */ +#define WMITLV_TABLE_WMI_MLO_LINK_RECOMMENDATION_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_recommendation_fixed_param, wmi_mlo_link_recommendation_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_peer_recommended_links, mlo_peer_recommended_links, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_RECOMMENDATION_CMDID); + /* Mcast ipv4 address filter list cmd */ #define WMITLV_TABLE_WMI_VDEV_IGMP_OFFLOAD_CMDID(id,op,buf,len) \ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_igmp_offload_fixed_param, wmi_igmp_offload_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ @@ -5240,6 +5390,97 @@ WMITLV_CREATE_PARAM_STRUC(WMI_XGAP_ENABLE_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_livedump_id_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ODD_LIVEDUMP_REQUEST_CMDID); +#define WMITLV_TABLE_WMI_PEER_SCHED_MODE_DISABLE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_sched_mode_disable_fixed_param, wmi_peer_sched_mode_disable_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_per_peer_sched_mode_disable, peer_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SCHED_MODE_DISABLE_CMDID); + +#define WMITLV_TABLE_WMI_TDMA_SCHEDULE_REQUEST_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdma_schedule_request_cmd_fixed_param, wmi_tdma_schedule_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_TDMA_SCHEDULE_REQUEST_CMDID); + +/* HPA cmd */ +#define WMITLV_TABLE_WMI_HPA_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hpa_cmd_fixed_param, wmi_hpa_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_HPA_CMDID); + +/* WMI cmd to set target rate to power table */ +#define WMITLV_TABLE_WMI_PDEV_SET_TGTR2P_TABLE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_cmd_fixed_param, wmi_pdev_set_tgtr2p_table_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, r2p_array, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TGTR2P_TABLE_CMDID); + +#define WMITLV_TABLE_WMI_MLO_VDEV_GET_LINK_INFO_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_vdev_get_link_info_cmd_fixed_param, wmi_mlo_vdev_get_link_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_VDEV_GET_LINK_INFO_CMDID); + +/* WMI command to set Manual SU UL OFDMA Trigger params */ +#define WMITLV_TABLE_WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_set_manual_su_trig_cmd_fixed_param, wmi_vdev_set_manual_su_trig_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID); + +/* WMI command to set Manual MU UL OFDMA Trigger params */ +#define WMITLV_TABLE_WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param, wmi_vdev_set_manual_mu_trig_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_macaddr, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID); + +/* Standalone Sound Cmd */ +#define WMITLV_TABLE_WMI_VDEV_STANDALONE_SOUND_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param, wmi_standalone_sounding_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_list, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STANDALONE_SOUND_CMDID); + +/* WMI cmd to set RF path for PHY */ +#define WMITLV_TABLE_WMI_PDEV_SET_RF_PATH_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param, wmi_pdev_set_rf_path_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_RF_PATH_CMDID); + +/* VDEV PAUSE cmd */ +#define WMITLV_TABLE_WMI_VDEV_PAUSE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param, wmi_vdev_pause_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PAUSE_CMDID); + +/* pdev,vdev,peer cmd messages for tunneling vendor-specific contents */ +#define WMITLV_TABLE_WMI_VENDOR_PDEV_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param, wmi_pdev_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, opaque_vendor_var_len_data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PDEV_CMDID); +#define WMITLV_TABLE_WMI_VENDOR_VDEV_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param, wmi_vdev_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, opaque_vendor_var_len_data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_VDEV_CMDID); +#define WMITLV_TABLE_WMI_VENDOR_PEER_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param, wmi_peer_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, opaque_vendor_var_len_data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_CMDID); + +/* SET MLO link BSS param */ +#define WMITLV_TABLE_WMI_MLO_LINK_SET_BSS_PARAMS_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_set_link_bss_params_cmd_fixed_param, wmi_mlo_set_link_bss_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_bss_param, link_bss_params, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID); + +/* MLO link switch confirmation command to inform FW about host side status and reason code */ +#define WMITLV_TABLE_WMI_MLO_LINK_SWITCH_CONF_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, wmi_mlo_link_switch_cnf_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_set_active_cmd_fixed_param, set_link_params, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_set_active_link_number_param, link_number_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap2, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_CONF_CMDID); + +/* WMI CMD used to send WSI stats info. */ +#define WMITLV_TABLE_WMI_PDEV_WSI_STATS_INFO_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param, wmi_pdev_wsi_stats_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_WSI_STATS_INFO_CMDID); + +/* CSA status indication command to inform FW about host accepting or rejecting csa event*/ +#define WMITLV_TABLE_WMI_CSA_EVENT_STATUS_INDICATION_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param , wmi_csa_event_status_ind_fixed_param,fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_CSA_EVENT_STATUS_INDICATION_CMDID); + /************************** TLV definitions of WMI events *******************************/ @@ -5295,7 +5536,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cust_bdf_version_capabilities, cust_bdf_version_capabilities, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_sw_cal_ver_cap, sw_cal_ver_cap, WMITLV_SIZE_VAR) \ WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_INT32, A_INT32, hw_tx_power_signed, WMITLV_SIZE_FIX, WMI_HW_TX_POWER_CAPS_MAX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_COEX_FIX_CHANNEL_CAPABILITIES, coex_fix_channel_caps, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_COEX_FIX_CHANNEL_CAPABILITIES, coex_fix_channel_caps, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_aux_dev_capabilities, aux_dev_caps, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_caps_param, aoa_caps_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_per_band_caps_param, aoa_per_band_caps_param, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID); #define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \ @@ -5420,7 +5664,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_TX_POWER_EVENTID); /* Channel Info Event */ #define WMITLV_TABLE_WMI_CHAN_INFO_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param, wmi_chan_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param, wmi_chan_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_blanking_params_info, scan_blanking_params, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cca_busy_subband_info, cca_busy_subband_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CHAN_INFO_EVENTID); /* RSSI dB to dBm conversion params info event to host */ @@ -5510,7 +5756,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STA_KICKOUT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bpcc_bufp, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_is_my_mgmt_frame, my_frame, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_removal_tbtt_count, link_removal_tbtt_count, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_bcast_t2lm_info, mlo_bcast_t2lm_info, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_bcast_t2lm_info, mlo_bcast_t2lm_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_EVENTID); /* Management Rx FW Consumed Event */ @@ -5582,6 +5829,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_band_to_mac, mac_freq_mapping, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_EVENTID); +/* Roam Synch key Event */ +#define WMITLV_TABLE_WMI_ROAM_SYNCH_KEY_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_ml_key_material_param, ml_key_material, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_KEY_EVENTID); + /* Roam Synch frame Event */ #define WMITLV_TABLE_WMI_ROAM_SYNCH_FRAME_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_synch_frame_event_fixed_param, wmi_roam_synch_frame_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ @@ -5656,9 +5908,20 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MUEDCA_PARAMS_CONFIG_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param, wmi_gpio_input_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_INPUT_EVENTID); +/* GPIO State Res Event */ +#define WMITLV_TABLE_WMI_GPIO_STATE_RES_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param, wmi_gpio_state_res_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_STATE_RES_EVENTID); + +/* RF Path Res Event */ +#define WMITLV_TABLE_WMI_PDEV_SET_RF_PATH_RESP_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_event_fixed_param, wmi_pdev_set_rf_path_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_RF_PATH_RESP_EVENTID); + /* CSA Handling Event */ #define WMITLV_TABLE_WMI_CSA_HANDLING_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, cs_wrap_ie, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CSA_HANDLING_EVENTID); /* Rfkill state change Event */ @@ -6008,7 +6271,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_OPER_MODE_CHANGE_EVENTID); WMITLV_CREATE_PARAM_STRUC(WMI_DFS_RADAR_EVENTID); #define WMITLV_TABLE_WMI_PDEV_DFS_RADAR_DETECTION_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_radar_detection_event_fixed_param, wmi_pdev_dfs_radar_detection_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_radar_detection_event_fixed_param, wmi_pdev_dfs_radar_detection_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_RADAR_FLAGS, radar_flags, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DFS_RADAR_DETECTION_EVENTID); #define WMITLV_TABLE_WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID(id,op,buf,len) \ @@ -6035,6 +6299,13 @@ WMITLV_CREATE_PARAM_STRUC(WMI_OEM_DMA_RING_CFG_RSP_EVENTID) WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_event_info, event_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_EVENTID); +/* NAN OEM Data Event */ +#define WMITLV_TABLE_WMI_NAN_OEM_DATA_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_oem_data_event_fixed_param, wmi_nan_oem_data_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_nan_oem_data_hdr, nan_oem_data_hdr, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_oem_data_buffer, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_NAN_OEM_DATA_EVENTID); + /* NAN discovery interface created event */ #define WMITLV_TABLE_WMI_NAN_DISC_IFACE_CREATED_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_iface_created_event_fixed_param, wmi_nan_disc_iface_created_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) @@ -6674,7 +6945,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_odd_addr_read_struct, ctrl_path_odd_addr_read, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_afc_stats_struct, ctrl_path_afc_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pmlo_stats_struct, ctrl_path_pmlo_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_cfr_stats_struct, ctrl_path_cfr_stats, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_cfr_stats_struct, ctrl_path_cfr_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_t2lm_stats_struct, ctrl_path_t2lm_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_blanking_stats_struct, ctrl_path_blanking_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_peer_stats_struct, ctrl_path_peer_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_vdev_stats_struct, ctrl_path_vdev_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_sta_rrm_stats_struct, ctrl_path_sta_rrm_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID); /* @@ -6749,7 +7025,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_CFG_RSP_EVENTID); #define WMITLV_TABLE_WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dma_buf_release_fixed_param, wmi_dma_buf_release_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_entry, entries, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_spectral_meta_data, meta_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_spectral_meta_data, meta_data, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cv_upload_meta_data, cv_meta_data, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cqi_upload_meta_data, cqi_meta_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID); /* ctl failsafe check event */ @@ -6979,7 +7257,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_TWT_SESSION_STATS_EVENTID); #define WMITLV_TABLE_WMI_MLO_LINK_SET_ACTIVE_RESP_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_set_active_resp_event_fixed_param, wmi_mlo_link_set_active_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_active_vdev_bitmap, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_vdev_bitmap, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_vdev_bitmap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_active_ieee_link_id_bitmap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_ieee_link_id_bitmap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, current_active_ieee_link_id_bitmap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, current_inactive_ieee_link_id_bitmap, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_ACTIVE_RESP_EVENTID); /* Get DPD status Event */ @@ -7112,6 +7394,95 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_REMOVAL_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_ap_vdev_tid_to_link_map_evt_fixed_param, wmi_mlo_ap_vdev_tid_to_link_map_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID); +/* HPA Event */ +#define WMITLV_TABLE_WMI_HPA_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hpa_evt_fixed_param, wmi_hpa_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_HPA_EVENTID); + +/* WMI target rate to power table return status event */ +#define WMITLV_TABLE_WMI_PDEV_SET_TGTR2P_TABLE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_event_fixed_param, wmi_pdev_set_tgtr2p_table_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TGTR2P_TABLE_EVENTID); + +/* CSA IE Received Event */ +#define WMITLV_TABLE_WMI_CSA_IE_RECEIVED_EVENTID(id,op,buf,len)\ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_CSA_IE_RECEIVED_EVENTID); + +#define WMITLV_TABLE_WMI_MLO_VDEV_LINK_INFO_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info_event_fixed_param, wmi_mlo_vdev_link_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_vdev_link_info, mlo_vdev_link_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_VDEV_LINK_INFO_EVENTID); + +/* Manual UL OFDMA Trigger Feedback Event */ +#define WMITLV_TABLE_WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param, wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_macaddr, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID); + +/* WMI standalone sound complete event */ +#define WMITLV_TABLE_WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param, wmi_standalone_sounding_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, snd_failed, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID); + +/* Manual UL OFDMA Trigger RX PPDU Per user info Event */ +#define WMITLV_TABLE_WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_manual_ul_ofdma_trig_rx_peer_userinfo, rx_peer_userinfo, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID); + +/* MLO_LINK_DISABLE_REQUEST Event */ +#define WMITLV_TABLE_WMI_MLO_LINK_DISABLE_REQUEST_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param, wmi_mlo_link_disable_request_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_DISABLE_REQUEST_EVENTID); + +/* pdev,vdev,peer event messages for tunneling vendor-specific contents */ +#define WMITLV_TABLE_WMI_VENDOR_PDEV_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param, wmi_pdev_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, opaque_vendor_var_len_data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PDEV_EVENTID); +#define WMITLV_TABLE_WMI_VENDOR_VDEV_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param, wmi_vdev_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, opaque_vendor_var_len_data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_VDEV_EVENTID); +#define WMITLV_TABLE_WMI_VENDOR_PEER_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param, wmi_peer_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, opaque_vendor_var_len_data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_EVENTID); + +/* link switch event */ +#define WMITLV_TABLE_WMI_MLO_LINK_SWITCH_REQUEST_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_req_evt_fixed_param, wmi_mlo_link_switch_req_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_REQUEST_EVENTID); + +/* MLO Primary Link Peer Migration command */ +#define WMITLV_TABLE_WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_fixed_param, wmi_mlo_primary_link_peer_migration_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_new_primary_link_peer_info, new_primary_link_peer_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID); + +/* MLO Primary Link Peer Migration Event */ +#define WMITLV_TABLE_WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_compl_fixed_param, wmi_mlo_primary_link_peer_migration_compl_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_primary_link_peer_migration_status, primary_link_peer_migration_status, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID); + +/* + * Update AOA Phase delta values for all gain tables event + * Below definition shows TLV packing of AOA Phase delta values for all gain tables event + */ +#define WMITLV_TABLE_WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param, wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_gain_phase_data_hdr, aoa_data_hdr, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, aoa_data_buf, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID); + +/* MLO Link State Switch Event */ +#define WMITLV_TABLE_WMI_MLO_LINK_STATE_SWITCH_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param, wmi_mlo_link_state_switch_req_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_state_switch_trigger_reason, switch_trigger_reason, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_STATE_SWITCH_EVENTID); #ifdef __cplusplus diff --git a/drivers/staging/fw-api/fw/wmi_unified.h b/drivers/staging/fw-api/fw/wmi_unified.h index f03822efa4e70b82c6ca8e984c14faeb35eee0b6..65610e75108eab0808537da8b7c2871ad0dd0ca2 100644 --- a/drivers/staging/fw-api/fw/wmi_unified.h +++ b/drivers/staging/fw-api/fw/wmi_unified.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2010-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -98,6 +98,8 @@ extern "C" { #define WMI_MAX_PN_LEN 8 +#define MAX_NUM_CQI_USERS_IN_STANDALONE_SND 3 + /* * These don't necessarily belong here; but as the MS/SM macros require * ar6000_internal.h to be included, it may not be defined as yet. @@ -198,14 +200,6 @@ static INLINE void wmi_packed_arr_set_bits(A_UINT32 *arr, A_UINT32 entry_index, ((val & (((A_UINT32) 1 << bits_per_entry) - 1)) << start_bit_in_uint); } -/** 2 word representation of MAC addr */ -typedef struct _wmi_mac_addr { - /** upper 4 bytes of MAC address */ - A_UINT32 mac_addr31to0; - /** lower 2 bytes of MAC address */ - A_UINT32 mac_addr47to32; -} wmi_mac_addr; - /** macro to convert MAC address from WMI word format to char array */ #define WMI_MAC_ADDR_TO_CHAR_ARRAY(pwmi_mac_addr,c_macaddr) do { \ (c_macaddr)[0] = (((pwmi_mac_addr)->mac_addr31to0) >> 0) & 0xff; \ @@ -315,6 +309,8 @@ typedef enum { WMI_GRP_SAWF, /* 0x49 SAWF (Service Aware WiFi) */ WMI_GRP_QUIET_OFL, /* 0x4a Quiet offloads */ WMI_GRP_ODD, /* 0x4b ODD */ + WMI_GRP_TDMA, /* 0x4c TDMA */ + WMI_GRP_MANUAL_UL_TRIG /* 0x4d Manual UL OFDMA Trigger */ } WMI_GRP_ID; #define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) @@ -514,6 +510,13 @@ typedef enum { WMI_PDEV_FEATURESET_CMDID, /** tag as Filter Pass category and the filters set for FP mode */ WMI_PDEV_MESH_RX_FILTER_ENABLE_CMDID, + /* WMI cmd to set Target rate to power table */ + WMI_PDEV_SET_TGTR2P_TABLE_CMDID, + /* WMI cmd to set RF path for PHY */ + WMI_PDEV_SET_RF_PATH_CMDID, + /** WSI stats info WMI command */ + WMI_PDEV_WSI_STATS_INFO_CMDID, + /* VDEV (virtual device) specific commands */ /** vdev create */ @@ -621,6 +624,13 @@ typedef enum { /** Enable SR prohibit feature for TIDs of vdev */ WMI_VDEV_PARAM_ENABLE_SR_PROHIBIT_CMDID, + /** pause vdev's Tx, Rx, or both for a specific duration */ + WMI_VDEV_PAUSE_CMDID, + + /** WMI Command to set status of CSA event from HOST */ + WMI_CSA_EVENT_STATUS_INDICATION_CMDID, + + /* peer specific commands */ /** create a peer */ @@ -736,9 +746,14 @@ typedef enum { /* Mac addr based filtering*/ WMI_PEER_TX_FILTER_CMDID, - /** flush specific tid queues of a peer */ + /** flush specific tid queues of a peer */ WMI_PEER_FLUSH_POLICY_CMDID, + /* Set disabled scheduler modes for one or more peers */ + WMI_PEER_SCHED_MODE_DISABLE_CMDID, + + /* Group SET cmd for PEERS */ + WMI_PEER_BULK_SET_CMDID, /* beacon/management specific commands */ @@ -1218,6 +1233,12 @@ typedef enum { /* WMI cmd used to start/stop XGAP (XPAN Green AP) */ WMI_XGAP_ENABLE_CMDID, + /* H2T HPA message */ + WMI_HPA_CMDID, + + /* WMI comamnd for standalone sounding */ + WMI_VDEV_STANDALONE_SOUND_CMDID, + /* Offload 11k related requests */ WMI_11K_OFFLOAD_REPORT_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_11K_OFFLOAD), /* invoke neighbor report from FW */ @@ -1233,6 +1254,8 @@ typedef enum { /* Antenna Controller, connected to wlan debug uart/GPIO. */ WMI_ANT_CONTROLLER_CMDID, + WMI_GPIO_STATE_REQ_CMDID, + /* FWTEST Commands */ WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_FWTEST), /** set NoA descs **/ @@ -1329,6 +1352,8 @@ typedef enum { /** Nan Request */ WMI_NAN_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_NAN), + /** Command to handle OEM's NAN specific opaque data */ + WMI_NAN_OEM_DATA_CMDID, /** Modem power state command */ WMI_MODEM_POWER_STATE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_COEX), @@ -1341,6 +1366,7 @@ typedef enum { /** Dedicated BT Antenna Mode (DBAM) command */ WMI_COEX_DBAM_CMDID, WMI_TAS_POWER_HISTORY_CMDID, + WMI_ESL_EGID_CMDID, /** * OBSS scan offload enable/disable commands @@ -1355,12 +1381,12 @@ typedef enum { WMI_OBSS_SCAN_DISABLE_CMDID, WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID, - /**LPI commands*/ - /**LPI mgmt snooping config command*/ + /** LPI commands */ + /** LPI mgmt snooping config command */ WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_LPI), - /**LPI scan start command*/ + /** LPI scan start command */ WMI_LPI_START_SCAN_CMDID, - /**LPI scan stop command*/ + /** LPI scan stop command */ WMI_LPI_STOP_SCAN_CMDID, /** ExtScan commands */ @@ -1537,6 +1563,16 @@ typedef enum { WMI_MLO_LINK_REMOVAL_CMDID, /** WMI cmd used to setup Tid to Link Mapping for a MLO VAP */ WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID, + /** WMI cmd used to get mlo link information */ + WMI_MLO_VDEV_GET_LINK_INFO_CMDID, + /** WMI cmd used to set link BSS parameters */ + WMI_MLO_LINK_SET_BSS_PARAMS_CMDID, + /** WMI cmd to confirm the status of link switch request handling */ + WMI_MLO_LINK_SWITCH_CONF_CMDID, + /** WMI cmd to migrate the primary link peer */ + WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID, + /** WMI cmd to recommand preferred link */ + WMI_MLO_LINK_RECOMMENDATION_CMDID, /** WMI commands specific to Service Aware WiFi (SAWF) */ /** configure or reconfigure the parameters for a service class */ @@ -1547,6 +1583,15 @@ typedef enum { /* WMI commands specific to ODD */ WMI_ODD_LIVEDUMP_REQUEST_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_ODD), + /* WMI commands specific to TDMA */ + WMI_TDMA_SCHEDULE_REQUEST_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_TDMA), + + /* WMI commands specific to manually-triggered UL */ + /** WMI Command to set Manual SU UL OFDMA trigger parameters */ + WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MANUAL_UL_TRIG), + + /** WMI Command to set Manual MU UL OFDMA trigger parameters */ + WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID, } WMI_CMD_ID; typedef enum { @@ -1705,6 +1750,14 @@ typedef enum { /* Event to indicate Schedule tid queue suspended info */ WMI_PDEV_SCHED_TIDQ_SUSP_INFO_EVENTID, + /* Event to send target rate to power table update status */ + WMI_PDEV_SET_TGTR2P_TABLE_EVENTID, + + /* Event to indicate completion on RF path */ + WMI_PDEV_SET_RF_PATH_RESP_EVENTID, + + /* Event to get AOA phasedelta values for all gain tables from HALPHY */ + WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID, /* VDEV specific events */ /** VDEV started event in response to VDEV_START request */ @@ -1937,6 +1990,8 @@ typedef enum { WMI_ROAM_FRAME_EVENTID, /** Send firmware ini value corresponding to param_id */ WMI_ROAM_GET_VENDOR_CONTROL_PARAM_EVENTID, + /** roam synch key event */ + WMI_ROAM_SYNCH_KEY_EVENTID, /** P2P disc found */ WMI_P2P_DISC_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_P2P), @@ -2054,8 +2109,11 @@ typedef enum { /** GTK offload failed to rekey event */ WMI_GTK_REKEY_FAIL_EVENTID, - /* CSA IE received event */ + + /* CSA handling event */ WMI_CSA_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CSA_OFL), + /* CSA IE received event */ + WMI_CSA_IE_RECEIVED_EVENTID, /*chatter query reply event*/ WMI_CHATTER_PC_QUERY_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CHATTER), @@ -2174,6 +2232,12 @@ typedef enum { /* WMI XGAP enable command response event ID */ WMI_XGAP_ENABLE_COMPLETE_EVENTID, + /* T2H HPA message */ + WMI_HPA_EVENTID, + + /* WMI standalone command complete Event */ + WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID, + /* GPIO Event */ WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO), @@ -2192,6 +2256,8 @@ typedef enum { /* Smart Antenna Controller status */ WMI_SMARTANT_STATE_CHANGE_EVENTID, + WMI_GPIO_STATE_RES_EVENTID, + /* TDLS Event */ WMI_TDLS_PEER_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_TDLS), @@ -2224,6 +2290,8 @@ typedef enum { WMI_NAN_STARTED_CLUSTER_EVENTID, WMI_NAN_JOINED_CLUSTER_EVENTID, WMI_NAN_DMESG_EVENTID, + /** Event to deliver OEM's NAN specific opaque data */ + WMI_NAN_OEM_DATA_EVENTID, /* Coex Event */ WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_COEX), @@ -2342,12 +2410,32 @@ typedef enum { WMI_MLO_LINK_REMOVAL_EVENTID, /* Response event for WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID */ WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID, + /* Response event for WMI_MLO_VDEV_GET_LINK_INFO_CMDID */ + WMI_MLO_VDEV_LINK_INFO_EVENTID, + /** request host to do T2LM neg to the un-disabled link */ + WMI_MLO_LINK_DISABLE_REQUEST_EVENTID, + /** request host to switch to new link for specified vdev */ + WMI_MLO_LINK_SWITCH_REQUEST_EVENTID, + /** Response event for WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID */ + WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID, + /** WMI Event to spcify reason for link state switch */ + WMI_MLO_LINK_STATE_SWITCH_EVENTID, /* WMI event specific to Quiet handling */ WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL), /* ODD events */ WMI_ODD_LIVEDUMP_RESPONSE_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_ODD), + + /** WMI events specific to manually-triggered UL */ + /** + * WMI Event to send Manual UL OFDMA Trigger frame status feedback to Host + */ + WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MANUAL_UL_TRIG), + /** + * WMI Event to send Manual UL OFDMA Trigger frame RX PPDU info to Host + */ + WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID, } WMI_EVT_ID; /* defines for OEM message sub-types */ @@ -3272,6 +3360,11 @@ typedef struct { #define WMI_TARGET_CAP_CONCURRENCE_SUPPORT_SET(target_cap_flags, value) \ WMI_SET_BITS(target_cap_flags, 11, 2, value) +#define WMI_TARGET_CAP_MULTIPASS_SAP_SUPPORT_GET(target_cap_flags) \ + WMI_GET_BITS(target_cap_flags, 13, 1) +#define WMI_TARGET_CAP_MULTIPASS_SAP_SUPPORT_SET(target_cap_flags, value) \ + WMI_SET_BITS(target_cap_flags, 13, 1, value) + /* * wmi_htt_msdu_idx_to_htt_msdu_qtype GET/SET APIs */ @@ -3414,7 +3507,8 @@ typedef struct { * Bits 12:11 concurrence support capability * Bit11 - [ML-STA + SL-STA] 0: not supported; 1:supported * Bit12 - [ML-STA + SL-SAP] 0: not supported; 1:supported - * Bits 31:13 - Reserved + * Bit 13 - Support for multipass SAP + * Bits 31:14 - Reserved */ A_UINT32 target_cap_flags; @@ -3460,6 +3554,21 @@ typedef struct { */ A_UINT32 hw_bd_status; + /* + * max block ack window size FW supports for tx. + */ + A_UINT32 tx_aggr_ba_win_size_max; + + /* + * max block ack window size FW supports for rx. + */ + A_UINT32 rx_aggr_ba_win_size_max; + + /* + * max link number per MLD FW supports. + */ + A_UINT32 num_max_mlo_link_per_ml_bss_supp; + /* Followed by next TLVs: * WMI_DMA_RING_CAPABILITIES dma_ring_caps[]; * wmi_spectral_bin_scaling_params wmi_bin_scaling_params[]; @@ -3470,6 +3579,7 @@ typedef struct { * wmi_htt_msdu_idx_to_htt_msdu_qtype htt_msdu_idx_to_qtype_map[]; * wmi_dbs_or_sbs_cap_ext dbs_or_sbs_cap_ext; * A_INT32 hw_tx_power_signed[WMI_HW_TX_POWER_CAPS_MAX]; + * wmi_aux_dev_capabilities aux_dev_caps[]; */ } wmi_service_ready_ext2_event_fixed_param; @@ -4368,8 +4478,29 @@ typedef struct { * 1 -> disable wds_mec_intrabss offload * Refer to WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_MEC_INTRABSS_OFFLOAD_GET / * SET macros. + * Bit 16 - latency_flowq_support + * Flag to indicate whether host supports latency tolerant queue. + * By default, it is disabled. + * 0 -> disable latency_flowq_support + * 1 -> enable latency_flowq_support + * Refer to WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_GET/SET macros. + * Bit 17 - rf_path_mode + * Flag to indicate overlapping_freq_mode + * By default, it will be primary mode (0) + * 0 - Primary + * 1 - Secondary + * Refer to WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_GET/SET macros. + * Bit 18 - disable_wds_peer_map_unmap_event + * Flag to indicate whether the WDS peer map/unmap event should be + * processed or ignored. + * 0 - leave the WDS peer map/unmap event enabled + * 1 - disable the WDS peer map/unmap event + * This flag shall only be set if the target has set the + * WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT flag. + * Refer to WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_GET + * and _SET macros. * - * Bits 31:16 - Reserved + * Bits 31:19 - Reserved */ A_UINT32 flags2; /** @brief host_service_flags - can be used by Host to indicate @@ -4468,7 +4599,15 @@ typedef struct { * Refer to the below definitions of the * WMI_RSRC_CFG_HOST_SERVICE_FLAG_BANG_RADAR_320M_SUPPORT_GET * and _SET macros. - * Bits 31:14 - Reserved + * Bit 14 + * This bit will be set when host wants to enable/disable + * full BW NOL feature. + * When set to 1: Enable full BW NOL feature. + * When set to 0: Disable the full BW NOL feature. + * Refer to the below definitions of the + * WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_GET + * and _SET macros. + * Bits 31:15 - Reserved */ A_UINT32 host_service_flags; @@ -4559,6 +4698,18 @@ typedef struct { * number of max active virtual devices (VAPs) to support */ A_UINT32 num_max_active_vdevs; + + /** + * @brief num_max_mlo_link_per_ml_bss + * number of max partner links of a ML BSS + */ + A_UINT32 num_max_mlo_link_per_ml_bss; + + /** + * @brief num_max_active_mlo_link_per_ml_bss + * number of max active partner links of a ML BSS + */ + A_UINT32 num_max_active_mlo_link_per_ml_bss; } wmi_resource_config; #define WMI_MSDU_FLOW_AST_ENABLE_GET(msdu_flow_config0, ast_x) \ @@ -4813,6 +4964,21 @@ typedef struct { #define WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_MEC_INTRABSS_OFFLOAD_SET(flags2, value) \ WMI_SET_BITS(flags2, 15, 1, value) +#define WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_GET(flags2) \ + WMI_GET_BITS(flags2, 16, 1) +#define WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_SET(flags2, value) \ + WMI_SET_BITS(flags2, 16, 1, value) + +#define WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_GET(flags2) \ + WMI_GET_BITS(flags2, 17, 1) +#define WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_SET(flags2, value) \ + WMI_SET_BITS(flags2, 17, 1, value) + +#define WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_GET(flags2) \ + WMI_GET_BITS(flags2, 18, 1) +#define WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SET(flags2, value) \ + WMI_SET_BITS(flags2, 18, 1, value) + #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \ WMI_GET_BITS(host_service_flags, 0, 1) @@ -4884,6 +5050,11 @@ typedef struct { #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_BANG_RADAR_320M_SUPPORT_SET(host_service_flags, val) \ WMI_SET_BITS(host_service_flags, 13, 1, val) +#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_GET(host_service_flags) \ + WMI_GET_BITS(host_service_flags, 14, 1) +#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_SET(host_service_flags, val) \ + WMI_SET_BITS(host_service_flags, 14, 1, val) + #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_GET(carrier_config) \ WMI_GET_BITS(carrier_config, 0, 1) @@ -4954,12 +5125,14 @@ typedef enum { WMI_VENDOR1_REQ1_VERSION_3_20 = 2, WMI_VENDOR1_REQ1_VERSION_3_30 = 3, WMI_VENDOR1_REQ1_VERSION_3_40 = 4, + WMI_VENDOR1_REQ1_VERSION_4_00 = 5, } WMI_VENDOR1_REQ1_VERSION; typedef enum { WMI_VENDOR1_REQ2_VERSION_3_00 = 0, WMI_VENDOR1_REQ2_VERSION_3_01 = 1, WMI_VENDOR1_REQ2_VERSION_3_20 = 2, + WMI_VENDOR1_REQ2_VERSION_3_50 = 3, } WMI_VENDOR1_REQ2_VERSION; typedef enum { @@ -5237,6 +5410,11 @@ typedef enum { #define WMI_SET_HOST_BAND_CAP(feature_bitmap, val) \ WMI_SET_BITS_ARRAY_LEN32_BYTES(feature_bitmap, 106, 6, val) +#define WMI_GET_STA_DUMP_SUPPORT(var, feature_bitmap) \ + WMI_GET_BITS_ARRAY_LEN32_BYTES(var, feature_bitmap, 112, 1) +#define WMI_SET_STA_DUMP_SUPPORT(feature_bitmap, val) \ + WMI_SET_BITS_ARRAY_LEN32_BYTES(feature_bitmap, 112, 1, val) + /* * Specify how many A_UINT32 words are needed to hold the feature bitmap flags. * This value may change over time. @@ -5437,6 +5615,9 @@ typedef struct { /* NOTE: This constant cannot be changed without breaking WMI compatibility */ #define WMI_IE_BITMAP_SIZE 8 +#define WMI_SCAN_MLD_PARAM_MLD_ID_GET(mld_param) WMI_GET_BITS(mld_param, 0, 8) +#define WMI_SCAN_MLD_PARAM_MLD_ID_SET(mld_param, val) WMI_SET_BITS(mld_param, 0, 8, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param */ /** Scan ID (lower 16 bits) MSB 4 bits is used to identify scan client based on enum WMI_SCAN_CLIENT_ID */ @@ -5528,6 +5709,11 @@ typedef struct { * dwell time in msec for 6 GHz channel of spectral scan channel list */ A_UINT32 dwell_time_spectral_ch; + /** + * B0-B7: mld id to be inserted in ML probe request + * B8-B31: reserved + */ + A_UINT32 mld_parameter; /** * TLV (tag length value) parameters follow the scan_cmd @@ -5603,6 +5789,12 @@ typedef struct { #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000 #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000 #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000 +/** pause home channel when scan channel is same as home channel */ +#define WMI_SCAN_FLAG_PAUSE_HOME_CHANNEL 0x200000 +/** + * report CCA busy for each possible 20Mhz subbands of the wideband scan channel + */ +#define WMI_SCAN_FLAG_REPORT_CCA_BUSY_FOREACH_20MHZ 0x400000 /** for adaptive scan mode using 3 bits (21 - 23 bits) */ #define WMI_SCAN_DWELL_MODE_MASK 0x00E00000 @@ -5711,6 +5903,11 @@ typedef enum { /* Include MLO IE in Probe req */ #define WMI_SCAN_FLAG_EXT_INCL_MLIE_PRB_REQ 0x00004000 +#define WMI_SCAN_FLAG_EXT_LOW_LATENCY_SCAN 0x00008000 +#define WMI_SCAN_FLAG_EXT_RELIABLE_SCAN 0x00010000 +#define WMI_SCAN_FLAG_EXT_FAST_SCAN 0x00020000 +#define WMI_SCAN_FLAG_EXT_LOW_POWER_SCAN 0x00040000 + /** * new 6 GHz flags per chan (short ssid or bssid) in struct @@ -6093,6 +6290,7 @@ typedef struct { */ A_UINT32 flags; wmi_mac_addr link_addr; /* link address */ + wmi_mac_addr self_link_addr; /* self-link address */ } wmi_roam_ml_setup_links_param; /* @@ -6228,6 +6426,7 @@ typedef struct { typedef enum { WMI_RX_PARAMS_EXT_META_ADDBA = 0x0, + WMI_RX_PARAMS_EXT_META_TWT = 0x1, } wmi_mgmt_rx_params_ext_meta_t; typedef struct { @@ -6252,6 +6451,20 @@ typedef struct { }; A_UINT32 mgmt_rx_params_ext_dword1; }; + union { + struct { + /* WMI_RX_PARAMS_EXT_META_TWT */ + A_UINT32 twt_ie_buf_len; /* IE length */ + /* Following this structure is the TLV byte stream of IE data + * of length twt_ie_buf_len: + * A_UINT8 ie_data[]; <-- length in bytes given by field + * twt_ie_buf_len. + * This ie_data[] would contain only the TWT IE information + * when twt_ie_buf_len is non zero. + */ + }; + A_UINT32 mgmt_rx_params_ext_dword2; + }; } wmi_mgmt_rx_params_ext; typedef struct { @@ -7062,6 +7275,8 @@ typedef struct { /* This TLV is followed by wmi_tx_send_params * wmi_tx_send_params tx_send_params; * wmi_mlo_tx_send_params mlo_tx_send_params[]; + * Note: WMI_MLO_MGMT_TID path validated for specific scenario + * (BTM Usecase). Full support is not available. * wmi_tx_send_params_ext tx_send_params_ext[0 or 1]; */ } wmi_mgmt_tx_send_cmd_fixed_param; @@ -7114,6 +7329,21 @@ typedef struct { A_UINT32 value; } wmi_echo_cmd_fixed_param; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag would be equivalent to WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param */ + /** AP MLD address request to be disabled some set of link */ + wmi_mac_addr mld_addr; + /** Request link id set to disable */ + A_UINT32 linkid_bitmap; +} wmi_mlo_link_disable_request_event_fixed_param; + +typedef enum { + /** + * Projects support to offload regulatory database by default. + * If don`t offload regulatory database, host can set this bit. + */ + WMI_REGDOMAIN_DATABASE_NO_OFFLOAD_BITMASK = 0x00000001, +} WMI_REGDOMAIN_BITMASK; typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_regdomain_cmd_fixed_param */ @@ -7180,6 +7410,9 @@ typedef struct { A_UINT32 conformance_test_limit_6G_subband_UNII6_client[3][2]; A_UINT32 conformance_test_limit_6G_subband_UNII7_client[3][2]; A_UINT32 conformance_test_limit_6G_subband_UNII8_client[3][2]; + + /** reg domain bitmap */ + A_UINT32 regdomain_bitmap; } wmi_pdev_set_regdomain_cmd_fixed_param; typedef struct { @@ -7825,6 +8058,7 @@ typedef enum { WMI_CSWARP_IE_PRESENT = WMI_CSWRAP_IE_PRESENT, /* deprecated: typo */ WMI_QSBW_ISE_PRESENT = 0x00000010, WMI_CSWRAP_IE_EXTENDED_PRESENT = 0x00000020, /* Added bitmask to verify if the additional information is filled in */ + WMI_CSWRAP_IE_EXT_VER_2_PRESENT = 0x00000040 /* Added bitmask to see if additional info is present in CS wrap IE */ } WMI_CSA_EVENT_IES_PRESENT_FLAG; /* wmi CSA receive event from beacon frame */ @@ -7855,6 +8089,31 @@ typedef struct { * the second octet resides in bits 15:8 of cswrap_ie_extended[0] and so on. */ A_UINT32 cswrap_ie_extended[5]; + + /* num_bytes_valid_in_cswrap_ie_ext_ver2: + * This fixed_param TLV can be followed by a VAR length TLV + * variable-length byte-array TLV for CS WRAP IE. + * Since the variable-length byte-array TLVs are always padded, if needed, + * to contain a multiple of 4 bytes, this field shows how many of the bytes + * contain valid data, versus how many are only for alignment padding. + */ + A_UINT32 num_bytes_valid_in_cswrap_ie_ext_ver2; + + /* + * Add link id, mld address and link address + * fields for N link CSA support + */ + A_UINT32 link_id; /* Link id associated with AP */ + wmi_mac_addr mld_mac_address; /* AP mld mac address */ + wmi_mac_addr link_mac_address; /* AP link mac address */ + A_UINT32 mld_mac_address_present :1, + link_mac_address_present :1, + link_id_present :1, + reserved :29; +/* + * This initial fixed_param TLV may be followed by the below TLVs: + * - cs_wrap_ie variable-length byte-array TLV + */ } wmi_csa_event_fixed_param; #define WMI_GET_MLD_MAC_ADDRESS_PRESENT(mld_mac_address_present) \ @@ -7927,6 +8186,21 @@ typedef enum { #define WMI_PDEV_PARAM_IS_HIGHER_MCS_XRETRY_RESTRICTION_SET(word32) WMI_F_MS(word32, WMI_PDEV_PARAM_HIGHER_MCS_XRETRY_RESTRICTION) #define WMI_PDEV_PARAM_GET_XRETRY_THRESHOLD(word32) WMI_F_MS(word32, WMI_PDEV_PARAM_XRETRY_THRESHOLD) +/* + * The WMI_SCHED_MODE_FLAGS enum is used by the following WMI commands: + * + * WMI_VDEV_PARAM_SET_DISABLED_SCHED_MODES + * WMI_PDEV_PARAM_SET_DISABLED_SCHED_MODES + * WMI_PEER_SCHED_MODE_DISABLE_CMDID + * WMI_SAWF_SVC_CLASS_CFG_CMDID + */ +typedef enum { + WMI_SCHED_MODE_DL_MU_MIMO = 0x00000001, + WMI_SCHED_MODE_UL_MU_MIMO = 0x00000002, + WMI_SCHED_MODE_DL_OFDMA = 0x00000004, + WMI_SCHED_MODE_UL_OFDMA = 0x00000008, +} WMI_SCHED_MODE_FLAGS; + typedef enum { /** TX chain mask */ WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, @@ -8932,6 +9206,112 @@ typedef enum { * based ranging. */ WMI_PDEV_PARAM_RTT_11AZ_RSID_RANGE, + + /* + * Disable the indicated DL and UL scheduler for the PDEV. + * + * This command is not supported in STA mode. + * + * A value of 1 in a given bit position disables the corresponding mode, + * and a value of 0 enables the mode. The WMI_SCHED_MODE_FLAGS enum defines + * the bit positions for each mode. + * + * A single 32 bit value is used to store the following configuration + * bitmap. + * + * This command differs from WMI_VDEV_PARAM_SET_HEMU_MODE and + * WMI_VDEV_PARAM_SET_EHT_MU_MODE in that it is intended for use during + * normal AP operation, and will never cause a VAP restart or other + * capability bit modification. It simply controls the scheduler + * behavior. + * + * bit | sched mode + * --------------- + * 0 | DL MU-MIMO + * 1 | UL MU-MIMO + * 2 | DL OFDMA + * 3 | UL OFDMA + * 4..31 | RESERVED + */ + WMI_PDEV_PARAM_SET_DISABLED_SCHED_MODES, + + /* + * Override default FW behavior and explicitly enable / disable + * to allow frames without encryption when no encryption is set. + * + */ + WMI_PDEV_PARAM_BYPASS_ENCRYPTION, + + /* + * Param to Enable/Disable scan blanking feature on the Scan Radio + * Host should ensure to send this param only for Scan Radio + * The WMI_SCAN_BLANKING_MODE enum specifies the possible values for this parameter. + * Based on the received input, the scan blanking feature will be carried out as explained in the enum WMI_SCAN_BLANKING_MODE + */ + WMI_PDEV_PARAM_SET_SCAN_BLANKING_MODE, + + /* + * Parameter to enable/disable Multi-Channel Concurrency low latency mode + * bit | config_mode + * ----------------- + * 0 | 0:disable, 1:enable. + * 1-31 | Reserved. + */ + WMI_PDEV_PARAM_SET_CONC_LOW_LATENCY_MODE, + + /* + * Parameter to enable/disable low power listen mode + * bit | config_mode + * ----------------- + * 0 | 0:disable, 1:enable. + * 1-31 | Reserved. + */ + WMI_PDEV_PARAM_LPL_SETTING, + + /** Set Probe Resp retry limit */ + WMI_PDEV_PARAM_PROBE_RESP_RETRY_LIMIT, + + /* + * Parameter for configure PCIE + * + * 0 - Default Value(FW Control). + * 1 - Force PCIE Gen Speed and Lane Width to maximum supported value. + */ + WMI_PDEV_PARAM_PCIE_CONFIG, + + /** CTS timeout - change wireless packet cts timeout configuration, + * units are microseconds + */ + WMI_PDEV_PARAM_CTS_TIMEOUT, + + /** Slot time - change wireless packet slot time value dynamically, + * units are microseconds + */ + WMI_PDEV_PARAM_SLOT_TIME, + + /** VO dedicated time - + * allocate dedicated time slots for VO access category across all + * ATF groups in a pdev. + * Note : + * 1. Per AC airtime per group is already available through + * ATF WMM WMI commands + * 2. The dedicated time slot is applicable per second + * 3. Units are in milli-seconds + */ + WMI_PDEV_PARAM_ATF_VO_DEDICATED_TIME, + + /** VI dedicated time - + * allocate dedicated time slots for VI access category across all + * ATF groups in a pdev. + * Note : + * 1. Per AC airtime per group is already given through ATF WMM WMI cmds + * 2. The dedicated time slot is applicable per second + * 3. Units are in milli-seconds + */ + WMI_PDEV_PARAM_ATF_VI_DEDICATED_TIME, + + /** Parameter used for enabling/disabling RFA toggle for SAP mode */ + WMI_PDEV_PARAM_SET_SAP_RFA_TOGGLE, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) @@ -9132,6 +9512,7 @@ typedef enum { WMI_HALPHY_TPC_STATS_SUPPORT_AX_EXTRA_MCS, WMI_HALPHY_TPC_STATS_SUPPORT_BE, WMI_HALPHY_TPC_STATS_SUPPORT_BE_PUNC, + WMI_HALPHY_TPC_STATS_SUPPORT_CTL_DESIGN_1, } WMI_HALPHY_TPC_STATS_SUPPORT_BITF; /* support bit fields */ typedef struct { @@ -9182,6 +9563,7 @@ typedef struct { * Refer to enum WMI_HALPHY_TPC_STATS_SUPPORT_BITF. */ A_UINT32 support_bits; + A_UINT32 nss; /* target specific NUM_SPATIAL_STREAM flag */ } wmi_tpc_configs; typedef struct { @@ -10224,7 +10606,7 @@ typedef enum { WMI_CHAN_WIDTH_MAX, } wmi_channel_width; -/*Clear stats*/ +/* Clear stats */ typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_clear_link_stats_cmd_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ @@ -10362,6 +10744,35 @@ typedef struct { #define WMI_VDEV_ID_INFO_GET_VALIDATE(vdev_id_info) WMI_GET_BITS(vdev_id_info, 31, 1) #define WMI_VDEV_ID_INFO_SET_VALIDATE(vdev_id_info, value) WMI_SET_BITS(vdev_id_info, 31, 1, value) +typedef struct { + union { + struct { + A_UINT32 + id: 8, /* the vdev ID */ + /* validate: + * validate bit, the vdev ID (id and link_status) is only valid + * if this bit set as 1. + */ + validate: 1, + /* link_status: + * 0 -> link inactive + * 1 -> link active + */ + link_status: 1, + reserved:22; + }; + A_UINT32 vdev_info_word0; + }; +} wmi_vdev_id_info_v2; + +#define WMI_VDEV_ID_INFO_V2_GET_VDEV_ID(vdev_id_info_v2) WMI_GET_BITS(vdev_id_info_v2, 0, 8) +#define WMI_VDEV_ID_INFO_V2_SET_VDEV_ID(vdev_id_info_v2, value) WMI_SET_BITS(vdev_id_info_v2, 0, 8, value) +#define WMI_VDEV_ID_INFO_V2_GET_VALIDATE(vdev_id_info_v2) WMI_GET_BITS(vdev_id_info_v2, 8, 1) +#define WMI_VDEV_ID_INFO_V2_SET_VALIDATE(vdev_id_info_v2, value) WMI_SET_BITS(vdev_id_info_v2, 8, 1, value) +#define WMI_VDEV_ID_INFO_V2_GET_LINK_STATUS(vdev_id_info_v2) WMI_GET_BITS(vdev_id_info_v2, 9, 1) +#define WMI_VDEV_ID_INFO_V2_SET_LINK_STATUS(vdev_id_info_v2, value) WMI_SET_BITS(vdev_id_info_v2, 9, 1, value) + + /* * Each step represents 0.5 dB. The starting value is 0 dBm. * Thus the TPC levels cover 0 dBm to 31.5 dBm inclusive in 0.5 dB steps. @@ -10643,10 +11054,10 @@ typedef struct { /** time slice duty cycle percentage of this interface */ A_UINT32 time_slice_duty_cycle; /** - * noise floor value report to host + * Current home channel noise floor value report to host * Units are dBm, values 0x0000ffff and 0x0 are invalid. */ - A_INT32 nf_cal_val_per_freq; + A_INT32 nf_cal_val; } wmi_iface_link_stats; typedef enum { @@ -10925,6 +11336,8 @@ typedef struct { A_UINT32 num_mib_extd_stats; /** Indicates the vdev id of the stats for MLO stats query */ wmi_vdev_id_info vdev_id_info; + /** Indicates the vdev id of the stats for MLO stats query v2 */ + wmi_vdev_id_info_v2 vdev_id_info_v2; /* This TLV is followed by another TLV of array of bytes * A_UINT8 data[]; @@ -11599,8 +12012,539 @@ typedef struct { A_UINT32 qos_null_tx_send_compl_over_wmi; /** total event alloc failure count for qos null tx send */ A_UINT32 qos_null_tx_send_event_alloc_failed; + + /** wlan_pdev fields num_macs, vdev_up_count and vdev_active_count + * num_macs_phy_vdev_up_active: + * This word contains the following bitfields: + * number of macs from wlan_pdev + * (WMI_PDEV_STATS_NUM_MACS_SET,GET) + * number of vdev up count + * (WMI_PDEV_STATS_VDEV_UP_CNT_SET,GET) + * number of vdev active count + * (WMI_PDEV_STATS_VDEV_UP_CNT_SET,GET) + */ + A_UINT32 opaque_debug_num_macs_phy_vdev_up_active; + /** refer wlan_pdev ic flags */ + A_UINT32 opaque_debug_ic_flags; + /** vdev_id that are paused per pdev */ + A_UINT32 opaque_debug_paused_ap_vdev_bitmap; + /** opaque_debug_flags: + * refer to WLAN_PS_DESC_BIN_HWM_HIT or WLAN_PS_DESC_BIN_LWM_HIT + */ + A_UINT32 opaque_debug_flags; + /** wlan_pdev fields remote_peer_cnt, max_rf_chains_2G and max_rf_chains_5G + * remote_peer_cnt_max_rf_chains_2G_5G: + * This word contains the following bitfields: + * max chains supported in the 2.4 GHz band + * (WMI_PDEV_STATS_MAX_RF_CHAIN_2G_SET,GET) + * max chains supported in the 5 GHz band, + * (WMI_PDEV_STATS_MAX_RF_CHAIN_5G_SET,GET) + * number of remote peers + * (WMI_PDEV_STATS_REMOTE_PEER_CNT_SET,GET) + */ + A_UINT32 opaque_debug_remote_peer_cnt_max_rf_chains_2G_5G; + /** wlan_pdev max HT Capability info, WMI_HT_CAP defines */ + A_UINT32 opaque_debug_max_ht_cap_info; + /** wlan_pdev max VHT capability info, WMI_VHT_CAP defines */ + A_UINT32 opaque_debug_max_vht_cap_info; + /** opaque_debug_max_vht_supp_mcs: + * wlan_pdev max VHT Supported MCS which is + * vht_supp_mcs_2G or vht_supp_mcs_5G + */ + A_UINT32 opaque_debug_max_vht_supp_mcs; + /** wlan_pdev max HE capability info, WMI_HE_CAP defines */ + A_UINT32 opaque_debug_max_he_cap_info; + A_UINT32 opaque_debug_max_he_cap_info_ext; + /** the nominal chain mask for transmit */ + A_UINT32 opaque_debug_tx_chain_mask; + /** the nominal chain mask for receive */ + A_UINT32 opaque_debug_rx_chain_mask; + /** opaque_debug_ema_flags: + * This word contains the following bitfields: + * ema_flags: ema_max_vap_cnt and ema_max_profile_period from wlan_pdev + * ema_max_vap_cnt- number of maximum EMA Tx vaps (VAPs having both + * VDEV_FLAGS_EMA_MODE and VDEV_FLAGS_TRANSMIT_AP set) + * (WMI_PDEV_STATS_EMA_MAX_VAP_CNT_SET,GET) + * ema_max_profile_period - maximum profile periodicity + * (maximum number of beacons after which VAP profiles repeat) + * for any EMA VAP on any pdev. + * (WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_SET,GET) + */ + A_UINT32 opaque_debug_ema_flags; + /** wlan_pdev - maximum ML peers supported */ + A_UINT32 opaque_debug_num_ml_peer_entries; + /** This word contains the following bitfields: + * wlan_pdev fields - num_max_hw_links, current_chip_id and max_num_chips + * (related to MLO) + * Max number of HW links + * (WMI_PDEV_STATS_NUM_MAX_HW_LINKS_SET,GET) + * Current Chip Id + * (WMI_PDEV_STATS_CURRENT_CHIP_ID_SET,GET) + * Max number of chips + * (WMI_PDEV_STATS_MAX_NUM_CHIPS_SET,GET) + */ + A_UINT32 opaque_debug_mlo_flags; + /** Indicate beacon size in bytes */ + A_UINT32 opaque_debug_large_bcn_size; + /** proposed by the host value of MSDUQs per each LinkView peer's TID */ + A_UINT32 opaque_debug_num_of_linkview_msduqs_per_tid; + /** bcn_filter_context variables */ + A_UINT32 opaque_debug_bcns_dropped; + A_UINT32 opaque_debug_bcns_recvd; + A_UINT32 opaque_debug_bcns_delivered; + /** Tids that are paused/unpaused based on module_id */ + A_UINT32 opaque_debug_vdev_all_tid_pause_bitmap; + /** Tids that are blocked/unblocked based on module_id */ + A_UINT32 opaque_debug_vdev_all_tid_block_bitmap; + /** wal_pdev rx filter, WAL_RX_FILTER_FLAGS defines */ + A_UINT32 opaque_debug_rx_filter; + /** This word contains the following bitfields: + * aggr_nonaggr_retry_th: + * wal_pdev fields - agg_retry_th and non_agg_retry_th + * This value holds max retry threshold up to which a Data packet + * will be retried when ack is not received. + * agg_retry_th - Threshold value used when aggregation is enabled + * (WMI_PDEV_STATS_AGG_RETRY_TH_SET,GET) + * non_agg_retry_th - Threshold value used for non-aggregation. + * (WMI_PDEV_STATS_NON_AGG_RETRY_TH_SET) + */ + A_UINT32 opaque_debug_aggr_nonaggr_retry_th; + /** This word contains the following bitfields: + * num_max_rx_ba_sessions: + * Number of rx BA session establised + * (WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_SET,GET) + * Max number of rx BA session from wal_pdev + * (WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_SET,GET) + */ + A_UINT32 opaque_debug_num_max_rx_ba_sessions; + /** It holds WHAL_CHANNEL_SWITCH_FLAGS values */ + A_UINT32 opaque_debug_chan_switch_flags; + /** reset_cause holds PDEV_RESET_CONSEC_FAILURE or PDEV_RESET_TXQ_TIMEOUT */ + A_UINT32 opaque_debug_consecutive_failure_reset_cause; + /** PPDU duration limit, in us */ + A_UINT32 opaque_debug_mu_ppdu_dur_limit_us; + /** pdev reset in progress */ + A_UINT32 opaque_debug_reset_in_progress; + /** wal_dev - vdev_migrate_state refer to WAL_VDEV_MIGRATE_STATE */ + A_UINT32 opaque_debug_vdev_migrate_state; + /** opaque_debug_rts_rc_flag: + * wal_pdev rts ratecode - this value reflects whatever + * WMI_PDEV_PARAM_RTS_FIXED_RATE value the host has specified for the pdev. + */ + A_UINT32 opaque_debug_rts_rc_flag; + /* Num of peer delete in progress */ + A_UINT32 opaque_debug_num_of_peer_delete_in_progress; + /** wal_pdev total number of active vdev count */ + A_UINT32 opaque_debug_total_active_vdev_cnt; + /** wal_pdev - max number of vdevs per pdev */ + A_UINT32 opaque_debug_max_vdevs; + /* NonOccupancyList(NOL) context */ + A_UINT32 opaque_debug_dfs_nol_count; + /** NOL timeout in seconds */ + A_UINT32 opaque_debug_dfs_nol_timeout; + A_UINT32 opaque_debug_dfs_use_nol; + /** channel availability check mode, refer enum WMI_ADFS_OCAC_MODE */ + A_UINT32 opaque_debug_cac_mode; + A_UINT32 opaque_debug_dyn_ppdu_dur; /* in ms */ + /** This word contains the following bitfields: + * wal_pdev home channel info + * home_chan_mhz_flags: + * primary channel frequency in mhz + * (WMI_PDEV_STATS_HOME_CHAN_MHZ_SET,GET) + * flags to specify other channel attributes + * (WMI_PDEV_STATS_HOME_CHAN_FLAGS_SET, GET) + */ + A_UINT32 opaque_debug_home_chan_mhz_flags; + /** home channel center frequency in MHz */ + A_UINT32 opaque_debug_home_band_center_freq; + /** home channel phy_mode, refer enum WLAN_PHY_MODE */ + A_UINT32 opaque_debug_home_phy_mode; + /** This word contains the following bitfields: + * wal_pdev current channel info + * cur_chan_mhz_flags: + * primary channel frequency in mhz + * (WMI_PDEV_STATS_CUR_CHAN_MHZ_SET,GET) + * flags to specify other channel attributes + * (WMI_PDEV_STATS_CUR_CHAN_FLAGS_SET,GET) + */ + A_UINT32 opaque_debug_cur_chan_mhz_flags; + /** current channel center frequency in MHz */ + A_UINT32 opaque_debug_cur_band_center_freq; + /** current channel phy_mode, refer enum WLAN_PHY_MODE */ + A_UINT32 opaque_debug_cur_phy_mode; + /* Beacon context info */ + A_UINT32 opaque_debug_bcn_q_num_bcns_queued_to_hw; + /** beacon queue AIFS */ + A_UINT32 opaque_debug_aifs; + /** beacon queue cwmin */ + A_UINT32 opaque_debug_cwmin; + /** beacon queue cwmax */ + A_UINT32 opaque_debug_cwmax; + /** FILS discovery period in TU */ + A_UINT32 opaque_debug_fils_period; + /** Beacon interval in TU */ + A_UINT32 opaque_debug_beacon_period; + A_UINT32 opaque_debug_staggered_beacon_intvl; + /** wal_pdev tx context, refer enum WAL_TX_CTXT_FLAGS */ + A_UINT32 opaque_debug_tx_ctxt_flags; + /** opaque_debug_burst_mode_pending_isr + * wal_pdev tx_ctxt fields - burst_mode refer enum WAL_TX_BURST_MODE + * and pending_isr_status count + */ + A_UINT32 opaque_debug_burst_mode_pending_isr; + /** max burst duration from ppdu duration in us */ + A_UINT32 opaque_debug_burst_dur; + /** counter for tx hw stuck */ + A_UINT32 opaque_debug_tx_hw_stuck_cnt; + /** counter for tx consecutive lifetime expiry */ + A_UINT32 opaque_debug_consecutive_lifetime_expiries; + /** wal_pdev rx context, refer enum WAL_RX_CTXT_FLAGS */ + A_UINT32 opaque_debug_rx_ctxt_flags; + /** wal_pdev fields in rx context for rx_suspend or resume count */ + A_UINT32 opaque_debug_rx_suspend_cnt; + A_UINT32 opaque_debug_rx_resume_cnt; + A_UINT32 opaque_debug_rx_pcie_suspend_cnt; + A_UINT32 opaque_debug_rx_pcie_resume_cnt; + /** This word contains the following bitfields: + * wal_pdev fields + * pdev paused - WMI_PDEV_STATS_PAUSED_SET,GET + * pdev suspend - WMI_PDEV_STATS_SUSPENDED_SET,GET + * cac_enabed - MI_PDEV_STATS_CAC_ENABLED_SET,GET + * monitor VAP present - WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_SET,GET + * beacon tx mode - WMI_PDEV_STATS_BCN_TX_MODE_SET,GET + * isTXsuspended - WMI_PDEV_STATS_IS_TXSUSPENDED_SET,GET + * isSCHEDsuspended - WMI_PDEV_STATS_IS_SCHEDSUSPENDED_SET,GET + * sched_algo_resume_needed - + * WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_SET,GET + * abort_reason - WMI_PDEV_STATS_ABORT_REASON_SET,GET + * atf_cfg - WMI_PDEV_STATS_ATF_CONFIG_SET,GET + * Green AP TX chainmask valid - WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_SET,GET + * Green AP RX chainmask valid - WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_SET,GET + * Green AP Phy mode valid - WMI_PDEV_STATS_GAP_PHY_MODE_VALID_SET,GET + * burst_enable - WMI_PDEV_STATS_BURST_ENABLE_SET,GET + */ + A_UINT32 opaque_debug_wal_pdev_bitfield; + /** This word contains the following bitfields: + * gap_phy_mode_freq: + * When GreenAP is enabled, phy_mode (WMI_PDEV_STATS_GAP_PHY_MODE_SET,GET) + * and center freq(MHz) (WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_SET,GET) + * in GAP context is displayed + */ + A_UINT32 opaque_debug_gap_phy_mode_freq; + /** + * The following 5 opaque_debug_reserved_field variables are provided + * purely for debugging by technicians who have outside knowledge of + * what kind of values the target has placed into these fields. + */ + A_UINT32 opaque_debug_reserved_field_1; + A_UINT32 opaque_debug_reserved_field_2; + A_UINT32 opaque_debug_reserved_field_3; + A_UINT32 opaque_debug_reserved_field_4; + A_UINT32 opaque_debug_reserved_field_5; } wmi_ctrl_path_pdev_stats_struct; +#define WMI_PDEV_STATS_NUM_MACS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_NUM_MACS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_NUM_PHY_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_NUM_PHY_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_VDEV_UP_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_VDEV_UP_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_VDEV_ACTIVE_CNT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_VDEV_ACTIVE_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_REMOTE_PEER_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_REMOTE_PEER_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_MAX_RF_CHAIN_2G_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_MAX_RF_CHAIN_2G_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_MAX_RF_CHAIN_5G_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_MAX_RF_CHAIN_5G_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_EMA_MAX_VAP_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8 ) +#define WMI_PDEV_STATS_EMA_MAX_VAP_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8 , val) +#define WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_NUM_SELF_PEERS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_NUM_SELF_PEERS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_MAX_ACTIVE_VDEVS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_MAX_ACTIVE_VDEVS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_NUM_MAX_HW_LINKS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_NUM_MAX_HW_LINKS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_CURRENT_CHIP_ID_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_CURRENT_CHIP_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_MAX_NUM_CHIPS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_MAX_NUM_CHIPS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_NUM_HOME_CHANS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_NUM_HOME_CHANS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_AGG_RETRY_TH_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_AGG_RETRY_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_NON_AGG_RETRY_TH_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_NON_AGG_RETRY_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_MAX_NON_DATA_RETRY_TH_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_MAX_NON_DATA_RETRY_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_NUM_CONSECUTIVE_BCN_TX_FILT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_NUM_CONSECUTIVE_BCN_TX_FILT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_PPDU_DUR_LIMIT_US_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_PPDU_DUR_LIMIT_US_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_MU_PPDU_DUR_LIMIT_US_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_MU_PPDU_DUR_LIMIT_US_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_RTS_RC_FLAGS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_RTS_RC_FLAGS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_RTS_RC_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_RTS_RC_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_GAP_TX_CH_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_GAP_TX_CH_MASK_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_GAP_RX_CH_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_GAP_RX_CH_MASK_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_GAP_PHY_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_GAP_PHY_MODE_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_CONSECUTIVE_FAILURE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_CONSECUTIVE_FAILURE_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_NUM_FILS_DISC_ENQD_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_NUM_FILS_DISC_ENQD_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_RESET_CAUSE_BITMAP_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_RESET_CAUSE_BITMAP_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_SWBA_NUM_OF_VDEVS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_SWBA_NUM_OF_VDEVS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_HOME_CHAN_MHZ_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_HOME_CHAN_MHZ_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_HOME_CHAN_FLAGS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_HOME_CHAN_FLAGS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_1_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_1_SET(flag,val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_2_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_2_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_CUR_CHAN_MHZ_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_CUR_CHAN_MHZ_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_CUR_CHAN_FLAGS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_CUR_CHAN_FLAGS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_1_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_1_SET(flag,val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_2_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_2_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_BURST_MODE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_BURST_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_PENDING_ISR_STATUS_GET(flag) \ + WMI_GET_BITS(flag, 8, 16) +#define WMI_PDEV_STATS_PENDING_ISR_STATUS_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 16, val) +#define WMI_PDEV_STATS_BCN_Q_NUM_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_BCN_Q_NUM_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_NUM_BCNS_QUEUED_TO_HW_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_NUM_BCNS_QUEUED_TO_HW_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_SWFDA_VDEV_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_SWFDA_VDEV_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) + +#define WMI_PDEV_STATS_ABORT_RESULT_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_PDEV_STATS_ABORT_RESULT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_PDEV_STATS_ABORT_REASON_GET(flag) \ + WMI_GET_BITS(flag, 2, 3) +#define WMI_PDEV_STATS_ABORT_REASON_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 3, val) +#define WMI_PDEV_STATS_IS_TXSUSPENDED_GET(flag) \ + WMI_GET_BITS(flag, 5, 1) +#define WMI_PDEV_STATS_IS_TXSUSPENDED_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 1, val) +#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_GET(flag) \ + WMI_GET_BITS(flag, 6, 1) +#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_SET(flag, val) \ + WMI_SET_BITS(flag, 6, 1, val) +#define WMI_PDEV_STATS_IS_TXSUSPENDED_WITH_AFC_GET(flag) \ + WMI_GET_BITS(flag, 7, 1) +#define WMI_PDEV_STATS_IS_TXSUSPENDED_WITH_AFC_SET(flag, val) \ + WMI_SET_BITS(flag, 7, 1, val) +#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_WITH_AFC_GET(flag) \ + WMI_GET_BITS(flag, 8, 1) +#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_WITH_AFC_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 1, val) +#define WMI_PDEV_STATS_SW_RETRY_MPDU_COUNT_TH_GET(flag) \ + WMI_GET_BITS(flag, 9, 1) +#define WMI_PDEV_STATS_SW_RETRY_MPDU_COUNT_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 9, 1, val) +#define WMI_PDEV_STATS_SENDBAR_COMPL_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 10, 1) +#define WMI_PDEV_STATS_SENDBAR_COMPL_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 10, 1, val) +#define WMI_PDEV_STATS_CAC_ENABLED_GET(flag) \ + WMI_GET_BITS(flag, 11, 1) +#define WMI_PDEV_STATS_CAC_ENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 11, 1, val) +#define WMI_PDEV_STATS_PAUSED_GET(flag) \ + WMI_GET_BITS(flag, 12, 1) +#define WMI_PDEV_STATS_PAUSED_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 1, val) +#define WMI_PDEV_STATS_SUSPENDED_GET(flag) \ + WMI_GET_BITS(flag, 13, 1) +#define WMI_PDEV_STATS_SUSPENDED_SET(flag, val) \ + WMI_SET_BITS(flag, 13, 1, val) +#define WMI_PDEV_STATS_MAC_COLD_RESET_GET(flag) \ + WMI_GET_BITS(flag, 14, 1) +#define WMI_PDEV_STATS_MAC_COLD_RESET_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 1, val) +#define WMI_PDEV_STATS_SAFE_TO_ACCESS_HW_GET(flag) \ + WMI_GET_BITS(flag, 15, 1) +#define WMI_PDEV_STATS_SAFE_TO_ACCESS_HW_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 1, val) +#define WMI_PDEV_STATS_STA_PS_STATECHG_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 16, 1) +#define WMI_PDEV_STATS_STA_PS_STATECHG_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 1, val) +#define WMI_PDEV_STATS_WAL_HOST_SCAN_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 17, 1) +#define WMI_PDEV_STATS_WAL_HOST_SCAN_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 17, 1, val) +#define WMI_PDEV_STATS_ATF_CONFIG_GET(flag) \ + WMI_GET_BITS(flag, 18, 1) +#define WMI_PDEV_STATS_ATF_CONFIG_SET(flag, val) \ + WMI_SET_BITS(flag, 18, 1, val) +#define WMI_PDEV_STATS_EAPOL_AC_OVERRIDE_GET(flag) \ + WMI_GET_BITS(flag, 19, 1) +#define WMI_PDEV_STATS_EAPOL_AC_OVERRIDE_SET(flag, val) \ + WMI_SET_BITS(flag, 19, 1, val) +#define WMI_PDEV_STATS_CALC_NEXT_DTIM_CNT_GET(flag) \ + WMI_GET_BITS(flag, 20, 1) +#define WMI_PDEV_STATS_CALC_NEXT_DTIM_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 20, 1, val) +#define WMI_PDEV_STATS_ATF_STRICT_SCH_GET(flag) \ + WMI_GET_BITS(flag, 21, 1) +#define WMI_PDEV_STATS_ATF_STRICT_SCH_SET(flag, val) \ + WMI_SET_BITS(flag, 21, 1, val) +#define WMI_PDEV_STATS_BCN_TX_MODE_GET(flag) \ + WMI_GET_BITS(flag, 22, 2) +#define WMI_PDEV_STATS_BCN_TX_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 2, val) +#define WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_GET(flag) \ + WMI_GET_BITS(flag, 24, 1) +#define WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 1, val) +#define WMI_PDEV_STATS_DYN_BW_GET(flag) \ + WMI_GET_BITS(flag, 25, 1) +#define WMI_PDEV_STATS_DYN_BW_SET(flag, val) \ + WMI_SET_BITS(flag, 25, 1, val) +#define WMI_PDEV_STATS_IS_MLO_SUPPORTED_GET(flag) \ + WMI_GET_BITS(flag, 26, 1) +#define WMI_PDEV_STATS_IS_MLO_SUPPORTED_SET(flag, val) \ + WMI_SET_BITS(flag, 26, 1, val) +#define WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_GET(flag) \ + WMI_GET_BITS(flag, 27, 1) +#define WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 27, 1, val) +#define WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_GET(flag) \ + WMI_GET_BITS(flag, 28, 1) +#define WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 28, 1, val) +#define WMI_PDEV_STATS_GAP_PHY_MODE_VALID_GET(flag) \ + WMI_GET_BITS(flag, 29, 1) +#define WMI_PDEV_STATS_GAP_PHY_MODE_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 29, 1, val) +#define WMI_PDEV_STATS_GAP_CLKGATE_VALID_GET(flag) \ + WMI_GET_BITS(flag, 30, 1) +#define WMI_PDEV_STATS_GAP_CLKGATE_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 30, 1, val) +#define WMI_PDEV_STATS_BURST_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 31, 1) +#define WMI_PDEV_STATS_BURST_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 31, 1, val) + typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_btcoex_stats_struct*/ A_UINT32 tlv_header; @@ -11668,6 +12612,11 @@ typedef enum { WMI_CTRL_PATH_STATS_ARENA_DBG_SRAM_AUX, WMI_CTRL_PATH_STATS_ARENA_SRAM_AUX_OVERFLOW, WMI_CTRL_PATH_STATS_ARENA_AMSS, + WMI_CTRL_PATH_STATS_ARENA_MLO_SHMEM, + WMI_CTRL_PATH_STATS_ARENA_MLO_H_SHMEM, + WMI_CTRL_PATH_STATS_ARENA_MLO_HC_SHMEM, + WMI_CTRL_PATH_STATS_ARENA_RRI_CMD, + WMI_CTRL_PATH_STATS_ARENA_SRAM_CLADE, WMI_CTRL_PATH_STATS_ARENA_MAX, } wmi_ctrl_path_fw_arena_ids; @@ -11700,6 +12649,11 @@ static INLINE A_UINT8 *wmi_ctrl_path_fw_arena_id_to_name(A_UINT32 arena_id) WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_DBG_SRAM_AUX); WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_SRAM_AUX_OVERFLOW); WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_AMSS); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_MLO_SHMEM); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_MLO_H_SHMEM); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_MLO_HC_SHMEM); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_RRI_CMD); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_SRAM_CLADE); } return (A_UINT8 *) "WMI_CTRL_PATH_STATS_ARENA_UNKNOWN"; @@ -12399,6 +13353,924 @@ typedef struct { A_UINT32 cfr_resp_failure_count; } wmi_ctrl_path_cfr_stats_struct; + +#define WMI_MAX_MLO_LINKS 5 +#define WMI_HE_MAP_COUNT 3 +#define WMI_EHT_MAP_COUNT 3 + +typedef struct { + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ctrl_path_peer_stats_struct + */ + A_UINT32 tlv_header; + /* mac address - part of wlan_peer */ + wmi_mac_addr mac_addr; + /* wlan_peer flags - refer to IEEE80211_NODE_* flags in wlan_peer.h */ + A_UINT32 opaque_debug_flags; + /* opaque_debug_vht_caps: + * Negotiated VHT capabilities in the wlan_peer struct + * Refer to ieee80211_defs.h. + */ + A_UINT32 opaque_debug_vht_caps; + /* opaque_debug_flags_ext: + * Extended flags in the wlan_peer struct + * Refer to IEEE80211_NODE_* flags in wlan_peer.h. + */ + A_UINT32 opaque_debug_flags_ext; + /* TID queues marked for TWT flush, present in wlan_peer */ + A_UINT32 opaque_debug_twt_flush_tidmap; + /* Number of TWT SPs to be expired, present in wlan_peer */ + A_UINT32 opaque_debug_n_TWT_SPs_to_expire; + /* opaque_debug_rc_flags: + * Peer rate information, part of struct rate_node + * Refer to whal_rate_api.h for complete RC_FLAGS details. + */ + A_UINT32 opaque_debug_rc_flags; + /* opaque_debug_sm_event_mask_eosp_cnt: + * This word contains the following bitfields: + * - Power save state machine event mask, + * part of wal_ps_buf_peer_handle_t. + * Refer to enum wal_ps_buf_peer_reg_ev_handlers. + * Use WMI_PEER_STATS_SM_MASK_SET,GET macros. + * - End of service period (EOSP) sent retry counter, + * part of wal_ps_buf_peer_handle_t. + * Use WMI_PEER_STATS_EOSP_RETRY_CNT_SET,GET macros. + */ + A_UINT32 opaque_debug_sm_event_mask_eosp_cnt; + /* opaque_debug_ps_buf_peer_flag1: + * Power save related send_n, ps_poll, unscheduled service period + * related fields; + * Part of wal_ps_buf_peer_handle_t. + * Refer to wal_ps_buf_peer_ctx struct definition. + */ + A_UINT32 opaque_debug_ps_buf_peer_flag1; + /* opaque_debug_ps_buf_peer_flag2: + * Power save related trigger/delivery tid related fields. + * part of wal_ps_buf_peer_handle_t. + * Refer to wal_ps_buf_peer_ctx struct definition. + */ + A_UINT32 opaque_debug_ps_buf_peer_flag2; + /* opaque_debug_ps_buf_peer_flag3: + * Power save related last trigger related information, + * part of wal_ps_buf_peer_handle_t. + * Refer to wal_ps_buf_peer_ctx struct definition. + */ + A_UINT32 opaque_debug_ps_buf_peer_flag3; + /* opaque_debug_last_rx_trigger_time: + * Time of the most recently received uplink trigger frame, + * part of wal_ps_buf_peer_handle_t - in microseconds units. + */ + A_UINT32 opaque_debug_last_rx_trigger_time; + /* opaque_debug_last_poll_time: + * TSF of the most recently received uplink PS-Poll, + * part of wal_ps_buf_peer_handle_t - in TU + */ + A_UINT32 opaque_debug_last_poll_time; + /* opaque_debug_oldest_tx_buffered_waiting_ms: + * Enqueue time of most recent MSDU that AP has buffered for + * sleeping station, part of wal_ps_buf_peer_handle_t, in ms units. + */ + A_UINT32 opaque_debug_oldest_tx_buffered_waiting_ms; + /* opaque_debug_last_rxtx_activity: + * The last time when there was a rx or tx traffic from a client, + * part of wal_ps_buf_peer_handle_t, in ms units. + */ + A_UINT32 opaque_debug_last_rxtx_activity; + /* opaque_debug_twt_flush_expiry_timestamp: + * Peer's TWT flush expiry timestamp in us, + * part of peer_twt_flush struct. + */ + A_UINT32 opaque_debug_twt_flush_expiry_timestamp; + /* opaque_debug_hw_link_id: + * Unique link id across SOCs, determined during QMI handshake, + * part of wlan_peer_ml_info_t. + */ + A_UINT32 opaque_debug_hw_link_id; + /* opaque_debug_ml_partner_hw_link_id_bitmap: + * Hardware link id of the of partner links that are to be cleaned up. + * This is filled by host during peer delete cmd. + * It it part of wlan_peer_ml_info_t. + */ + A_UINT32 opaque_debug_ml_partner_hw_link_id_bitmap; + /* opaque_debug_link_flags: + * MLO link flags: related to assoc, anchor, master and primary UMAC links. + * Refer to resmgr_mlo_link_flags. + * Part of wlan_peer_ml_info_t. + */ + A_UINT32 opaque_debug_link_flags; + /* MLO peer id - part of wlan_ml_peer_t */ + A_UINT32 opaque_debug_ml_peer_id; + /* MLD mac address - part of wlan_ml_peer_t */ + wmi_mac_addr opaque_debug_mld_mac_addr; + /* opaque_debug_assoc_id_usage_cnt: + * Part of wlan_peer. + * This word contains the following bitfields: + * - assoc id of the peer + * Use WMI_PEER_STATS_ASSOCIATE_ID_SET,GET macros. + * - peer usage count to track if peer alloc command is sent + * for new or existing peer, + * Use WMI_PEER_STATS_USAGE_CNT_SET,GET macros. + */ + A_UINT32 opaque_debug_assoc_id_usage_cnt; + /* opaque_debug_default_ht_caps: + * Part of wlan_peer. + * This word contains the following bitfields: + * - default peer capabilities of the peer - refer ieee80211_defs.h + * Use WMI_PEER_STATS_DEF_CAPS_SET,GET macros. + * - HT capabilities of the peer - refer ieee80211_defs.h + * Use WMI_PEER_STATS_HT_CAPS_SET,GET macros. + */ + A_UINT32 opaque_debug_default_ht_caps; + /* opaque_debug_inact_gen: + * Part of wlan_peer. + * This word contains the following bitfields: + * - Overall tx/rx inactivity time of the peer in seconds + * Use WMI_PEER_STATS_INACT_GEN_SET,GET macros. + * - Data tx/rx inactivity time of the peer in seconds. + * Use WMI_PEER_STATS_DATA_INACT_GEN_SET,GET macros. + */ + A_UINT32 opaque_debug_inact_gen; + /* opaque_debug_id_type: + * Part of wlan_peer. + * This word contains the following bitfields: + * - Type of peer whether it is bss,self or remote peer. + * Refer to enum wmi_peer_type. + * Use WMI_PEER_STATS_TYPE_SET,GET macros. + * - MAC ID that the peer belongs to + * Use WMI_PEER_STATS_MAC_ID_SET,GET macros. + * - sw peer id of the peer + * Use WMI_PEER_STATS_ID_SET,GET macros. + */ + A_UINT32 opaque_debug_id_type; + /* Deleted tids bitmask within the peer - part of wal_peer */ + A_UINT32 opaque_debug_deleted_tidmask; + /* number of local pending frames for completions - part of wal_peer */ + A_UINT32 opaque_debug_num_of_local_frames_pending; + /* flags part of wal_peer - refer to wal_peer_flags_t */ + A_UINT32 opaque_debug_wal_peer_flags; + /* opaque_debug_keyid0_ast_index: + * The AST index for key id 0 which is always allocated, + * part of wal_peer. + */ + A_UINT32 opaque_debug_keyid0_ast_index; + /* opaque_debug_all_tids_block_module_bitmap: + * Bitmap of block IDs requesting block of all TIDs, + * part of wal_peer. + * Refer to enum WLAN_PAUSE_ID. + * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. + */ + A_UINT32 opaque_debug_all_tids_block_module_bitmap; + /* opaque_debug_all_tids_pause_module_bitmap: + * Bitmap of pause IDs requesting block of all TIDs, + * part of wal_peer. + * Refer to enum WLAN_PAUSE_ID. + * This pause ID can be mapped to a WLAN_MODULE_ID module ID. + */ + A_UINT32 opaque_debug_all_tids_pause_module_bitmap; + /* opaque_debug_data_tids_block_module_bitmap: + * Bitmap of block ids requesting block of data tids, + * part of wal_peer. + * Refer to enum WLAN_PAUSE_ID. + * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. + */ + A_UINT32 opaque_debug_data_tids_block_module_bitmap; + /* opaque_debug_data_tids_pause_module_bitmap: + * Bitmap of pause ids requesting block of data tids, + * part of wal_peer. + * Refer to enum WLAN_PAUSE_ID. + * This pause ID can be mapped to a WLAN_MODULE_ID module ID. + */ + A_UINT32 opaque_debug_data_tids_pause_module_bitmap; + /* The time stamp when first ppdu fails in us, part of wal_peer */ + A_UINT32 opaque_debug_ppdu_fail_time; + /* opaque_debug_rate_params: + * This word contains the following bitfields: + * - Non data rate code of the peer - part of wal_peer + * Use WMI_PEER_STATS_BSS_NON_DATA_RC_SET,GET macros. + * - channel bandwidth supported by the peer, part of wal_peer. + * The mapping is as follows: + * 0 = 20 MHz, 1 = 40 MHz, 2 = 80 MHz, 3 = 160 MHz, 4 = 320 MHz + * Use WMI_PEER_STATS_CH_WIDTH_SET,GET macros. + * - MCS used for the last PPDU received from the peer, part of wal_peer + * Use WMI_PEER_STATS_RX_MCS_SET,GET macros. + */ + A_UINT32 opaque_debug_rate_params; + /* consecutive QOS null frame tx fail count, part of wal_peer */ + A_UINT32 opaque_debug_consecutive_null_failure; + /* peer delete state refer enum PEER_DELETE_SM_STATE, part of wal_peer */ + A_UINT32 opaque_debug_peer_delete_sm_state; + /* opaque_debug_cache_rate_info_low32,_high32: + * Lower/upper 32 bits respectively of cached rate info variable + * updated by the HTT metadata. + * This rate_info is based on the values from struct + * htt_tx_msdu_desc_ext2_t . + * If htt_tx_desc_ext2->update_peer_cache is set to 1 and + * HTT_TX_TCL_METADATA_PEER_ID_GET(tcl_cmd_num) returns valid peer ID + * then rate_info cache of the peer is updated. + * Part of wal_peer. + */ + A_UINT32 opaque_debug_cache_rate_info_low32; + A_UINT32 opaque_debug_cache_rate_info_high32; + /* opaque_debug_peer_delete_rc4_rekey: + * This word contains the following bitfields: + * - Flag that denotes if Peer delete all is in progress or not, + * part of wal_peer. + * Use WMI_PEER_STATS_DELETE_ALL_FLAG_SET,GET macros. + * - RC4 rekey counter, part of wal_peer. + * Use WMI_PEER_STATS_RC4_REKEY_CNT_SET,GET macros. + */ + A_UINT32 opaque_debug_peer_delete_rc4_rekey; + /* opaque_debug_mcbc_tids_pause_bitmap: + * Bitmap containing Multicast and broadcast tids that are paused, + * part of wal_peer. + */ + A_UINT32 opaque_debug_mcbc_tids_pause_bitmap; + /* opaque_debug_next_to_last_pn_low32,_high32: + * Lower/upper 32 bits respectively of last used PN value received, + * part of wal_peer. + */ + A_UINT32 opaque_debug_next_to_last_pn_low32; + A_UINT32 opaque_debug_next_to_last_pn_high32; + /* opaque_debug_last_pn_low32,_high32: + * Lower/upper 32 bits respectively of current PN value received, + * part of wal_peer. + */ + A_UINT32 opaque_debug_last_pn_low32; + A_UINT32 opaque_debug_last_pn_high32; + /* opaque_debug_twt_ap_peer_ctx_flags: + * This word contains the following bitfields: + * - TWT AP peer's context flags, part of twt_ap_peer_handle_t struct. + * Refer twt_ap_twt_session_t definition. + * Use WMI_PEER_STATS_TWT_AP_FLAGS_SET,GET macros. + * - TWT session counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_AP_SESSION_CNT_SET,GET macros. + * - TWT frame retry counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_FRM_RETRY_SET,GET macros. + */ + A_UINT32 opaque_debug_twt_ap_peer_ctx_flags; + /* opaque_debug_twt_ap_counters: + * This word contains the following bitfields: + * - TWT UL trigger counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_UL_TRIGGER_SET,GET macros. + * - TWT Broadcast session counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_BC_SESSION_SET,GET macros. + * - TWT pending report counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_PENDING_REPORT_SET,GET macros. + * - TWT flow IDs, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_FLOW_IDS_SET,GET macros. + */ + A_UINT32 opaque_debug_twt_ap_counters; + /* opaque_debug_tx_state_bmap_low32,_high32: + * Lower/upper 32 bits respectively of list of currently running + * BA Tx states for tids in this peer, part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_tx_state_bmap_low32; + A_UINT32 opaque_debug_tx_state_bmap_high32; + /* opaque_debug_addba_mode: + * This word contains the following bitfields: + * - ADDBA mode whether its automatic or manual, + * WAL_BA_ADDBA_MODE_AUTO = 0 and WAL_BA_ADDBA_MODE_MANUAL = 1 + * Part of wal_ba_peer_handle_t. + * Use WMI_PEER_STATS_ADDBBA_TX_MODE_SET,GET macros. + * - ADDBA request's response code, part of wal_ba_peer_handle_t. + * Use WMI_PEER_STATS_ADDBBA_RESP_MODE_SET,GET macros. + */ + A_UINT32 opaque_debug_addba_mode; + /* opaque_debug_tx_retry_bmap: + * Bitmap of tids and their TX BlockAck retry counters. + * Each TID uses 2 bits for its BA retry counter. + * Part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_tx_retry_bmap; + /* opaque_debug_rx_state_bmap: + * Bitmap of tids and their RX BlockAck retry counters. + * 00 - BA not setup + * 01 - BA in progress + * 10 - reserved + * 11 - BA setup. + * Each TID uses 2 bits for its BA RX state; + * for instance TID 0's BA info occupies bits 1:0 and so on. + * Part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_rx_state_bmap; + /* opaque_debug_tx_pending_delba_tid_bmap: + * TID bitmap containaing information DELBA tx pending, + * part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_tx_pending_delba_tid_bmap; + /* opaque_debug_link_monitor_tid_num: + * link monitor tid num in bss_peer ba_peer_handle, + * part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_link_monitor_tid_num; + /* opaque_debug_rc4_eapol_key_complete: + * Flag that denotes rc4 eapol key exchange is complete, + * part of wal_peer_ext. + */ + A_UINT32 opaque_debug_rc4_eapol_key_complete; + /* qcache peer flags, refer to qpeer_flags_t */ + A_UINT32 opaque_debug_qpeer_flags; + /* bitmap of TIDs requested for flush, part of wal_qcache_peer */ + A_UINT32 opaque_debug_delete_requested_tidmask; + /* bitmap of created TIDs, part of wal_qcache_peer */ + A_UINT32 opaque_debug_tid_created_tidmask; + /* opaque_debug_qpeer_rt_flags0,_flags1,_flags2: + * RT thread related fields in qpeer, refer to _wal_qcache_peer. + */ + A_UINT32 opaque_debug_qpeer_rt_flags0; + A_UINT32 opaque_debug_qpeer_rt_flags1; + A_UINT32 opaque_debug_qpeer_rt_flags2; + /* opaque_debug_qpeer_sa_flags0,_flags1: + * SA thread related fields in qpeer, refer to _wal_qcache_peer. + */ + A_UINT32 opaque_debug_qpeer_sa_flags0; + A_UINT32 opaque_debug_qpeer_sa_flags1; + /* BE thread related fields in qpeer, refer to _wal_qcache_peer */ + A_UINT32 opaque_debug_qpeer_be_flags; + /* qpeer event bitmap, refer to wal_peer_event_type */ + A_UINT32 opaque_debug_event_bitmap; + /* tx fail count for a peer, part of dcache peer */ + A_UINT32 opaque_debug_seq_no_tx_fail_cnt; + /* Last transmission rate in kbps for a peer, part of dcache peer */ + A_UINT32 opaque_debug_last_tx_rate_kbps; + /* opaque_debug_amsdu_size: + * This word contains the following bitfields: + * - MAX AMSDU size of the peer, part of dcache peer. + * Use WMI_PEER_STATS_MAX_AMSDU_SIZE_SET,GET macros. + */ + A_UINT32 opaque_debug_amsdu_size; + /* opaque_debug_fake_sleep_time: + * Time elapsed in ms after entering into fake sleep after xretry failure, + * part of dcache peer. + */ + A_UINT32 opaque_debug_fake_sleep_time; + /* opaque_debug_tx_frame_qos_ctrl: + * This word contains the following bitfields: + * - Tx frame control FC flags in ieee80211_defs.h, part of dcache peer. + * Use WMI_PEER_STATS_TX_FRAME_CTRL_SET,GET macros. + * - Tx QOS control FC flags in ieee80211_defs.h, part of dcache peer. + * Use WMI_PEER_STATS_TX_QOS_CTRL_SET,GET macros. + */ + A_UINT32 opaque_debug_tx_frame_qos_ctrl; + /* opaque_debug_consec_fail_subfrm_sz: + * This word contains the following bitfields: + * - Consecutive tx fail count for the peer, part of dcache peer. + * Use WMI_PEER_STATS_CONSEC_FAIL_SET,GET macros. + * - subframe size configured for the peer, part of dcache peer. + * Use WMI_PEER_STATS_SUBFRAME_SIZE_SET,GET macros. + */ + A_UINT32 opaque_debug_consec_fail_subfrm_sz; + /* opaque_debug_tx_fail_partial_aid: + * This word contains the following bitfields: + * - tx fail count for the peer, part of dcache peer. + * Use WMI_PEER_STATS_TX_FAIL_CNT_SET,GET macros. + * - Partial AID of the peer, part of dcache peer. + * Use WMI_PEER_STATS_TX_PARTIAL_AID_SET,GET macros. + */ + A_UINT32 opaque_debug_tx_fail_partial_aid; + /* opaque_debug_max_nss: + * Part of dcache peer. + * This word contains the following bitfields: + * - Peer NSS value sent by host during WMI_PEER_ASSOC cmd. + * Use WMI_PEER_STATS_MAX_NSS_SET,GET macros. + */ + A_UINT32 opaque_debug_max_nss; + /* opaque_debug_he_cap_info: + * Peer HE capabilities info sent during peer assoc cmd. + * Refer to WMI_HECAP_* macros in wmi_unified.h. + * Part of dcache peer. + */ + A_UINT32 opaque_debug_he_cap_info; + /* opaque_debug_he_cap_info_ext: + * Peer extended HE capabilities info sent during peer assoc cmd. + * Refer to WMI_HECAP_* macros in wmi_unified.h. + * Part of dcache peer. + */ + A_UINT32 opaque_debug_he_cap_info_ext; + /* opaque_debug_eht_cap_info: + * Peer EHT capabilities info. + * Refer to ieee80211_defs.h, part of dcache peer. + */ + A_UINT32 opaque_debug_eht_cap_info; + /* TAC thread related fields in dcache peer refer wal_dcache_peer_t */ + A_UINT32 opaque_debug_dcache_tac_flags; + /* RT thread related fields in dcache peer refer wal_dcache_peer_t */ + A_UINT32 opaque_debug_dcache_rt_flags; + /* Supported RC modes for the peer refer enum RC_MODE, part of dcache */ + A_UINT32 opaque_debug_rc_mode_supported_mask; + /* opaque_debug_wlan_peer_bitfield_mask: + * Part of wlan peer. This word contains the following bitfields: + * - Flag that denotes whether peer delete response is being sent + * to host or not. + * Use WMI_PEER_STATS_DEL_RESP_TO_HOST_SET,GET macros. + * - Flag that denotes if peer delete is in progress or not. + * Use WMI_PEER_STATS_DELETE_IN_PROGRESS_SET,GET macros. + * - Flag that denotes if peer migration is in progress or not. + * Use WMI_PEER_STATS_MIGRATION_IN_PROGRESS_SET,GET macros. + * - Flag that denotes peer's connection/authorized state. + * Refer WAL_PEER_STATE_* macros in wal_peer.h. + * Use WMI_PEER_STATS_CONN_STATE_SET,GET macros. + * - TX chain mask at 160MHz of the peer set during peer assoc command. + * Use WMI_PEER_STATS_TX_CHAIN_MASK_160_SET,GET macros. + * - Tx chain mask set during peer assoc command. + * Use WMI_PEER_STATS_TX_CHAIN_MASK_SET,GET macros. + * - copy of tx chain mask of peer saved for AP MIMO PS. + * Use WMI_PEER_STATS_ASSOC_CHAIN_MASK_SET,GET macros. + */ + A_UINT32 opaque_debug_wlan_peer_bitfield_mask; + /* opaque_debug_wal_peer_bitfields: + * Part of wal_peer. This word contains the following bitfields: + * - Flag that denotes if QOS null is sent over WMI or not. + * Use WMI_PEER_STATS_QOS_NULL_OVER_WMI_SET,GET macros. + * - Flag that denotes whether peer assoc is received + * for the first time or not. + * Use WMI_PEER_STATS_NEW_ASSOC_SET,GET macros. + * - Flag that denotes whether TWT filter is enabled or not. + * Use WMI_PEER_STATS_TWT_FILT_FLAG_SET,GET macros. + * - Flag that denotes whether TWT is registered or not. + * Use WMI_PEER_STATS_TWT_REG_FLAG_SET,GET macros. + * - Flag that denotes whether WMM txQ uplink trigger is disabled or not. + * Use WMI_PEER_STATS_WMM_UL_TRIG_FLAG_SET,GET macros. + * - Number of active TIDs that do not have BA setup. + * Use WMI_PEER_STATS_ACTIVE_NOT_BA_TID_SET,GET macros. + */ + A_UINT32 opaque_debug_wal_peer_bitfields; + /* flags in RT context refer wal_peer_ext_t */ + A_UINT32 opaque_debug_wal_peer_rt_flags; + /* opaque_debug_ml_attributes: + * Part of wal_ml_peer. This word contains the following bitfields: + * - Num of MLO links + * Use WMI_PEER_STATS_NUM_LINKS_SET,GET macros. + * - ML peer id + * Use WMI_PEER_STATS_ML_PEER_ID_SET,GET macros. + * - Primary link ID + * Use WMI_PEER_STATS_PRI_LINK_ID_SET,GET macros. + * - Primary chip ID + * Use WMI_PEER_STATS_PRI_CHIP_ID_SET,GET macros. + * - Initial link count + * Use WMI_PEER_STATS_LINK_INIT_CNT_SET,GET macros. + * - Number of local links + * Use WMI_PEER_STATS_NUM_LOCAL_LINKS_SET,GET macros. + * - Bitmap of participating chips + * Use WMI_PEER_STATS_CHIPS_BITMAP_SET,GET macros. + */ + A_UINT32 opaque_debug_ml_attributes; + /* wal peer MLO flags refer ml_peer_flags_t */ + A_UINT32 opaque_debug_ml_flags; + /* opaque_debug_ml_link_info_flags: + * Part of link_info in wlan_peer_ml_info_t. + * This word contains the following bitfields: + * - flag denoting if MLO-link is valid or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_VALID_SET,GET macros. + * - flag denoting if MLO-link is active or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_ACTIVE_SET,GET macros. + * - flag denoting if MLO-link is primary or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_PRI_SET,GET macros. + * - flag denoting if MLO-link is assoc link or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_ASSOC_LINK_SET,GET macros. + * - Chip ID of the MLO-link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_CHIP_ID_SET,GET macros. + * - IEEE link ID of the MLO-link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_IEEE_LINK_SET,GET macros. + * - HW link ID of the MLO-link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_HW_LINK_SET,GET macros. + * - logical link ID of the MLO-link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_LOGICAL_LINK_SET,GET macros. + * - flag denoting if MLO-link is master link or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_MASTER_LINK_SET,GET macros. + * - flag denoting if MLO-link is anchor link or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_ANCHOR_LINK_SET,GET macros. + * - flag denoting if MLO-link is initialized or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_INIT_SET,GET macros. + */ + A_UINT32 opaque_debug_ml_link_info_flags[WMI_MAX_MLO_LINKS]; + /* opaque_debug_ml_link_info_id: + * Part of link_info in wlan_peer_ml_info_t. + * This word contains the following bitfields: + * - sw_peer_id corresponding to the link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_PEER_ID_SET,GET macros. + * - vdev id corresponding to the link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_VDEV_ID_SET,GET macros. + */ + A_UINT32 opaque_debug_ml_link_info_id[WMI_MAX_MLO_LINKS]; + /* MLO link info primary tid mask, part of link_info in wlan_peer_ml_info_t */ + A_UINT32 opaque_debug_ml_link_info_pri_tidmask[WMI_MAX_MLO_LINKS]; + /* opaque_debug_rc_node_params: + * Part of struct TX_PEER_PARAMS. + * This word contains the following bitfields: + * - NSS of the peer in 160MHZ + * Use WMI_PEER_STATS_NSS_160_SET,GET macros. + * - phymode of the peer - refer enum WLAN_PHY_MODE + * Use WMI_PEER_STATS_RC_PHYMODE_SET,GET macros. + * - legacy rate set for the peer + * Use WMI_PEER_STATS_LEGACY_RATE_SET,GET macros. + */ + A_UINT32 opaque_debug_rc_node_params; + /* opaque_debug_rc_vht_mcs_set: + * Rate node param - negotiated VHT MCS map, + * part of struct TX_PEER_PARAMS + */ + A_UINT32 opaque_debug_rc_vht_mcs_set; + /* opaque_debug_rc_node_params1: + * Part of link_info in wlan_peer_ml_info_t. + * This word contains the following bitfields: + * - Minimum data rate set for the peer in Mbps + * Use WMI_PEER_STATS_MIN_DATA_RATE_SET,GET macros. + * - Max VHT rate set for the peer + * Use WMI_PEER_STATS_VHT_MAX_RATE_SET,GET macros. + * - Max VHT streams set for the peer + * Use WMI_PEER_STATS_VHT_MAX_STREAMS_SET,GET macros. + * - BSS - Channel frequency set for the peer in MHz + * Use WMI_PEER_STATS_RC_CHAN_FREQ_SET,GET macros. + */ + A_UINT32 opaque_debug_rc_node_params1; + /* opaque_debug_he_mcs_nss_set_tx,_rx: + * Rate node param - negotiated HE MCS tx+rx maps, + * part of struct TX_PEER_PARAMS. + * The lower 8 bits (bits 23:16) within the upper 16 bits indicate + * MCS 12/13 enablement for BW <= 80MHz; the upper 8 bits (bits 31:24) + * within the 16 bits indicate MCS 12/13 enablement for BW > 80MHz. + * The 16 bits for the index values are within the upper bits (bits 31:16) + * of a 32-bit word. and WMI_HE_MAP_COUNT is based on HE_MCS_MAP_CNT + * in ieee80211_defs.h. + */ + A_UINT32 opaque_debug_he_mcs_nss_set_tx[WMI_HE_MAP_COUNT]; + A_UINT32 opaque_debug_he_mcs_nss_set_rx[WMI_HE_MAP_COUNT]; + /* opaque_debug_eht_mcs_nss_set_tx,_rx: + * Rate node param - negotiated EHT MCS tx+rx maps, + * part of struct TX_PEER_PARAMS. + * B0-B3 indicates max NSS that supports mcs 0-7 + * B4-B7 indicates max NSS that supports mcs 8-9 + * B8-B11 indicates max NSS that supports mcs 10-11 + * B12-B15 indicates max NSS that supports mcs 12-13 + * B16-B31 reserved. + * WMI_EHT_MAP_COUNT is based on EHT_MCS_MAP_CNT in ieee80211_defs.h. + */ + A_UINT32 opaque_debug_eht_mcs_nss_set_tx[WMI_EHT_MAP_COUNT]; + A_UINT32 opaque_debug_eht_mcs_nss_set_rx[WMI_EHT_MAP_COUNT]; + /* opaque_debug_rc_user_start_mcs_rate: + * Rate node user_start_rate is MCS value set based on phymode. + * For possible values refer "INITIAL_" macros in ratectrl.h. + * Part of struct TX_PEER_PARAMS. + * This is the starting value of MCS that was used by rate control + * for the first transmissions to the peer, until PER information + * from the peer allowed the rate control algorithm to determine + * the suitable MCS. + */ + A_UINT32 opaque_debug_rc_user_start_mcs_rate; + /* + * The following 4 opaque_debug_field variables are provided purely + * for debugging by technicians who have outside knowledge of what + * kind of values the target has placed into these fields. + * They are not to be interpreted by the host driver in any manner. + */ + A_UINT32 opaque_debug_field_1; + A_UINT32 opaque_debug_field_2; + A_UINT32 opaque_debug_field_3; + A_UINT32 opaque_debug_field_4; +} wmi_ctrl_path_peer_stats_struct; + +#define WMI_PEER_STATS_SM_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_SM_MASK_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_EOSP_RETRY_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_EOSP_RETRY_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +/* bits 31:24 unused/reserved */ + +#define WMI_PEER_STATS_ASSOCIATE_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_ASSOCIATE_ID_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_USAGE_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_USAGE_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_DEF_CAPS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_DEF_CAPS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_HT_CAPS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_HT_CAPS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_INACT_GEN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_INACT_GEN_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_DATA_INACT_GEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_DATA_INACT_GEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_PEER_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_PEER_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_MAC_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_MAC_ID_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_PEER_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_PEER_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_BSS_NON_DATA_RC_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_BSS_NON_DATA_RC_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_CH_WIDTH_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_CH_WIDTH_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_RX_MCS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_RX_MCS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +/* bits 31:24 unused/reserved */ + +#define WMI_PEER_STATS_DELETE_ALL_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_DELETE_ALL_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_RC4_REKEY_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_RC4_REKEY_CNT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +/* bits 31:16 unused/reserved */ + +#define WMI_PEER_STATS_TWT_AP_FLAGS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_TWT_AP_FLAGS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_TWT_AP_SESSION_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_TWT_AP_SESSION_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PEER_STATS_TWT_FRM_RETRY_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PEER_STATS_TWT_FRM_RETRY_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_PEER_STATS_TWT_UL_TRIGGER_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_TWT_UL_TRIGGER_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_TWT_BC_SESSION_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_TWT_BC_SESSION_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_TWT_PENDING_REPORT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_TWT_PENDING_REPORT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PEER_STATS_TWT_FLOW_IDS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PEER_STATS_TWT_FLOW_IDS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_PEER_STATS_ADDBBA_TX_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_ADDBBA_TX_MODE_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_ADDBBA_RESP_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_ADDBBA_RESP_MODE_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_MAX_AMSDU_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_MAX_AMSDU_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +/* bits 31:16 unused/reserved */ + +#define WMI_PEER_STATS_TX_FRAME_CTRL_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_TX_FRAME_CTRL_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_TX_QOS_CTRL_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_TX_QOS_CTRL_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_CONSEC_FAIL_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_CONSEC_FAIL_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_SUBFRAME_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_SUBFRAME_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_TX_FAIL_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_TX_FAIL_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_TX_PARTIAL_AID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_TX_PARTIAL_AID_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_MAX_NSS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_MAX_NSS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +/* bits 31:8 unused/reserved */ + +#define WMI_PEER_STATS_DEL_RESP_TO_HOST_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_PEER_STATS_DEL_RESP_TO_HOST_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_PEER_STATS_DELETE_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_PEER_STATS_DELETE_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_PEER_STATS_MIGRATION_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_PEER_STATS_MIGRATION_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_PEER_STATS_CONN_STATE_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 4, val) +#define WMI_PEER_STATS_CONN_STATE_GET(flag) \ + WMI_GET_BITS(flag, 3, 4) +#define WMI_PEER_STATS_TX_CHAIN_MASK_160_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_TX_CHAIN_MASK_160_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_TX_CHAIN_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_TX_CHAIN_MASK_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PEER_STATS_ASSOC_CHAIN_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PEER_STATS_ASSOC_CHAIN_MASK_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_PEER_STATS_QOS_NULL_OVER_WMI_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_PEER_STATS_QOS_NULL_OVER_WMI_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_PEER_STATS_NEW_ASSOC_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_PEER_STATS_NEW_ASSOC_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_PEER_STATS_TWT_FILT_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_PEER_STATS_TWT_FILT_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_PEER_STATS_TWT_REG_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 1, val) +#define WMI_PEER_STATS_TWT_REG_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 3, 1) +#define WMI_PEER_STATS_WMM_UL_TRIG_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 1, val) +#define WMI_PEER_STATS_WMM_UL_TRIG_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 4, 1) +#define WMI_PEER_STATS_ACTIVE_NOT_BA_TID_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 4, val) +#define WMI_PEER_STATS_ACTIVE_NOT_BA_TID_GET(flag) \ + WMI_GET_BITS(flag, 5, 4) +/* bits 31:10 unused/reserved */ + +#define WMI_PEER_STATS_NUM_LINKS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 2, val) +#define WMI_PEER_STATS_NUM_LINKS_GET(flag) \ + WMI_GET_BITS(flag, 0, 2) +#define WMI_PEER_STATS_ML_PEER_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 12, val) +#define WMI_PEER_STATS_ML_PEER_ID_GET(flag) \ + WMI_GET_BITS(flag, 2, 12) +#define WMI_PEER_STATS_PRI_LINK_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 3, val) +#define WMI_PEER_STATS_PRI_LINK_ID_GET(flag) \ + WMI_GET_BITS(flag, 14, 3) +#define WMI_PEER_STATS_PRI_CHIP_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 17, 2, val) +#define WMI_PEER_STATS_PRI_CHIP_ID_GET(flag) \ + WMI_GET_BITS(flag, 17, 2) +#define WMI_PEER_STATS_LINK_INIT_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 19, 3, val) +#define WMI_PEER_STATS_LINK_INIT_CNT_GET(flag) \ + WMI_GET_BITS(flag, 19, 3) +#define WMI_PEER_STATS_NUM_LOCAL_LINKS_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 2, val) +#define WMI_PEER_STATS_NUM_LOCAL_LINKS_GET(flag) \ + WMI_GET_BITS(flag, 22, 2) +#define WMI_PEER_STATS_CHIPS_BITMAP_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PEER_STATS_CHIPS_BITMAP_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VALID_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ACTIVE_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ACTIVE_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PRI_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PRI_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ASSOC_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ASSOC_LINK_GET(flag) \ + WMI_GET_BITS(flag, 3, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_CHIP_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 3, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_CHIP_ID_GET(flag) \ + WMI_GET_BITS(flag, 4, 3) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_IEEE_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 7, 8, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_IEEE_LINK_GET(flag) \ + WMI_GET_BITS(flag, 7, 8) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_HW_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 3, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_HW_LINK_GET(flag) \ + WMI_GET_BITS(flag, 15, 3) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_LOGICAL_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 18, 2, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_LOGICAL_LINK_GET(flag) \ + WMI_GET_BITS(flag, 18, 2) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_MASTER_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 20, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_MASTER_LINK_GET(flag) \ + WMI_GET_BITS(flag, 20, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ANCHOR_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 21, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ANCHOR_LINK_GET(flag) \ + WMI_GET_BITS(flag, 21, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_INIT_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_INIT_GET(flag) \ + WMI_GET_BITS(flag, 22, 1) +/* bits 31:23 unused/reserved */ + +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PEER_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PEER_ID_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VDEV_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VDEV_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +/* bits 31:24 unused/reserved */ + +#define WMI_PEER_STATS_NSS_160_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_NSS_160_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_RC_PHYMODE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_RC_PHYMODE_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_LEGACY_RATE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_LEGACY_RATE_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_MIN_DATA_RATE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_MIN_DATA_RATE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_VHT_MAX_RATE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 4, val) +#define WMI_PEER_STATS_VHT_MAX_RATE_GET(flag) \ + WMI_GET_BITS(flag, 8, 4) +#define WMI_PEER_STATS_VHT_MAX_STREAMS_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 4, val) +#define WMI_PEER_STATS_VHT_MAX_STREAMS_GET(flag) \ + WMI_GET_BITS(flag, 12, 4) +#define WMI_PEER_STATS_RC_CHAN_FREQ_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_RC_CHAN_FREQ_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_cfr_stats_struct */ + A_UINT32 tlv_header; + /* blanking_mode: + * blanking configuration. Refer to WMI_SCAN_BLANKING_MODE + */ + A_UINT32 blanking_mode; + /* is_blanking_enabled: + * current blanking status. 0 = disabled, 1 = enabled + */ + A_UINT32 is_blanking_enabled; + A_UINT32 gate_2g_enabled; /* 2.4GHZ gate pin state */ + A_UINT32 gate_5g_enabled; /* 5GHz gate pin state */ + A_UINT32 gate_6g_enabled; /* 6GHz gate pin state */ + A_UINT32 blanking_count; /* scan radio blanking count */ + A_UINT32 blanking_duration; /* scan radio blanking duration in us */ +} wmi_ctrl_path_blanking_stats_struct; + typedef struct { /** TLV tag and len; tag equals * WMITLV_TAG_STRUC_wmi_ctrl_path_stats_event_fixed_param */ @@ -12644,10 +14516,19 @@ typedef struct { A_UINT32 tx_bcn_outage_cnt; /* Total number of failed beacons */ } wmi_bcn_stats; +#define WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_BIT 0 +#define WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_MASK \ + (1 << WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_BIT) + +#define WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_BIT 1 +#define WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_MASK \ + (1 << WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_BIT) + /** * vdev extension statistics */ typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_vdev_extd_stats */ A_UINT32 tlv_header; /* vdev id */ A_UINT32 vdev_id; @@ -12659,8 +14540,1211 @@ typedef struct { A_UINT32 unsolicited_prb_succ_cnt; /* Total number of unsolicited probe response frames failed */ A_UINT32 unsolicited_prb_fail_cnt; + /* vdev info flags: + * bit 0: WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID, + * 0: the "is link active" flag is not valid + * 1: the "is link active" flag is valid + * bit 1: WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE, + * 1:link_active; 0:link_inactive + * Refer to WMI_VDEV_STATS_FLAGS_ defs. + */ + A_UINT32 flags; + A_INT32 vdev_tx_power; /* dBm units */ } wmi_vdev_extd_stats; +/** + * Vdev debug stats to be used for wmi control path stats. + * This is an extension to vdev_extd_stats, + * vdev_extd_stats display is part of apstats. + */ +typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_vdev_stats_struct */ + A_UINT32 tlv_header; + /* vdev id */ + A_UINT32 vdev_id; + /** opaque_debug_wal_vdev_flags: + * This will contain the value from wal_vdev wal vdev flags for vdev state + */ + A_UINT32 opaque_debug_wal_vdev_flags; + /** control flags for this vdev */ + A_UINT32 opaque_debug_vdev_flags; + /** vdevid of transmitted AP (mbssid case) */ + A_UINT32 opaque_debug_vdevid_trans; + /** opaque_debug_profile_idx: + * the profile index of the connected non-trans ap (mbssid case). + * 0 means invalid. + */ + A_UINT32 opaque_debug_profile_idx; + /** opaque_debug_profile_num: + * the total profile numbers of non-trans aps (mbssid case). + * 0 means legacy AP. + */ + A_UINT32 opaque_debug_profile_num; + /* Contains the value of multi_vdev_restart status */ + A_UINT32 opaque_debug_multi_vdev_restart; + /* Contains the value of created mac_id from wal_vdev */ + A_UINT32 opaque_debug_created_mac_id; + /* Contains the value of consecutive count of the leaky AP */ + A_UINT32 opaque_debug_consec_detect_leaky_ap_cnt; + /* Contains the value of Vdev manager debug flags */ + A_UINT32 opaque_debug_vdev_mgr_dbg_flags; + /* Contains the value of max vdev pause delay in microseconds */ + A_UINT32 opaque_debug_max_pause_delay_us; + /* opaque_debug_sta_offset: + * Contains the value of the offset of vdev TSF with BI (vdev_tsf%BI) + * for STA vdev. + */ + A_UINT32 opaque_debug_sta_offset; + /* Contains the value of vdev pn sequence receive filter */ + A_UINT32 opaque_debug_vdev_pn_rx_filter; + /* Contains the value of config params */ + A_UINT32 opaque_debug_traffic_config; + /* opaque_debug_he_bss_rts_thld_tu: + * Contains Period of time in units for a non-AP STA to reserve the medium. + */ + A_UINT32 opaque_debug_he_bss_rts_thld_tu; + /* opaque_debug_rts_threshold: + * Contains the value of Request to Send (RTS) Threshold of the packet size. + */ + A_UINT32 opaque_debug_rts_threshold; /* dot11RTSThreshold */ + /* Contains the value of Tx failure count threshold */ + A_UINT32 opaque_debug_tx_fail_cnt_thres; + /* Contains the value of ratio = HI_WORD/LO_WORD */ + A_UINT32 opaque_debug_mu_edca_sifs_ratio; + /* opaque_debug_kickout_th: + * Contains the value of kickout threshold that denotes units of + * lost block acks of consecutive tx failure threshold. + */ + A_UINT32 opaque_debug_kickout_th; + /* opaque_debug_rate_dd_bmap: + * Contains the value of per vap config related to VAP aggregation + * of ratectrl drop-down limits. + */ + A_UINT32 opaque_debug_rate_dd_bmap; + /* Contains the value of Maximum Transmission Unit frame size */ + A_UINT32 opaque_debug_mtu_size; + /* Contains the value of vdev event bitmap from wal_vdev */ + A_UINT32 opaque_debug_event_bitmap; + /* Contains the value of peer event bitmap from wal_vdev */ + A_UINT32 opaque_debug_peer_event_bitmap; + /* Contains the value of Sched config of vdev allowed time during ATF */ + A_UINT32 opaque_debug_atf_vdev_allowed_time; + /* opaque_debug_atf_vdev_used_unallocated_time: + * Contains the value of Sched config of vdev used unallocated time + * during ATF. + */ + A_UINT32 opaque_debug_atf_vdev_used_unallocated_time; + /* Contains the value of Sched config of vdev unused time during ATF */ + A_UINT32 opaque_debug_atf_vdev_unused_time; + /* Contains the value of Carrier frequency offset last programmed time */ + A_UINT32 opaque_debug_last_prog_time; + /* Contains the value of Carrier frequency offset last receive time */ + A_UINT32 opaque_debug_last_recv_time; + /* Contains the value of Packet count of received frames on the channel */ + A_UINT32 opaque_debug_rx_pkt_on_channel; + /* Contains the value of Target beacon transmission time offset value */ + A_UINT32 opaque_debug_tbtt_offset; + /* Contains the value of tid pause bitmap of the peer from wal_vdev */ + A_UINT32 opaque_debug_peer_all_tid_pause_bitmap; + /* Contains the value of tid block bitmap of the peer from wal_vdev */ + A_UINT32 opaque_debug_peer_all_tid_block_bitmap; + /* Contains the value of tdls peer kickout threshold */ + A_UINT32 opaque_debug_tdls_peer_kickout_th; + /* opaque_debug_num_of_remote_peers_connected: + * Contains the value of num_of_remote_peers_connected; + * Below field is valid only for AP vap. + */ + A_UINT32 opaque_debug_num_of_remote_peers_connected; + /* Contains the value of num of Multi group key support */ + A_UINT32 opaque_debug_num_group_key_enabled; + /* Contains the value of delete all peer command flags */ + A_UINT32 opaque_debug_delete_all_peer_flags; + /* Contains the value of Keepalive ARP sender address time */ + A_UINT32 opaque_debug_keepalive_arp_sender_ipv4; + /* Contains the value of Keepalive ARP Target address time */ + A_UINT32 opaque_debug_keepalive_arp_target_ipv4; + /* Contains the value of Keepalive interval duration time */ + A_UINT32 opaque_debug_keepalive_interval; + /* Contains the value of Keepalive start timer timestamp */ + A_UINT32 opaque_debug_keepalive_timer_start_timestamp; + /* Contains the value of max idle interval and status of STA */ + A_UINT32 opaque_debug_sta_maxidle_interval; + A_UINT32 opaque_debug_sta_maxidle_method; + /* Contains the value of Timing synchronization function (TSF) time diff */ + A_UINT32 opaque_debug_tsf_curr_time_diff; + /* opaque_debug_sleep_duration_us: + * Contains the value of Time in microsends to detect sleep duration + * of the client. + */ + A_UINT32 opaque_debug_sleep_duration_us; + /* Contains the value of pause start time and to calculate pause delay */ + A_UINT32 opaque_debug_pause_start_time_us; + A_UINT32 opaque_debug_pause_delay_us; + /* Contains the value of number of supported group key */ + A_UINT32 opaque_debug_num_supported_group_key; + /* opaque_debug_avg_data_null_tx_delay: + * Contains the value of Average time taken to calculate data frame + * tx delay. + */ + A_UINT32 opaque_debug_avg_data_null_tx_delay; + /* opaque_debug_avg_rx_leak_window: + * Contains the value of Average time taken to calculate data frame + * in receive window. + */ + A_UINT32 opaque_debug_avg_rx_leak_window; + /* Contains the value of count for number of received deauth frames */ + A_UINT32 opaque_debug_num_recv_deauth; + /* Contains the value of Beacon interval in microseconds */ + A_UINT32 opaque_debug_bcn_intval_us; + /* opaque_debug_fils_period + * Contains the value of us, period configured through + * WMI_ENABLE_FILS_CMDID. + */ + A_UINT32 opaque_debug_fils_period; + /* Contains the value of previous Timing synchronization function (TSF) */ + A_UINT32 opaque_debug_prev_tsf; + /* Contains the value of time taken during client sleep */ + A_UINT32 opaque_debug_sleep_entry_time; + /* Contains the value of Total sleep duration from wal_vdev */ + A_UINT32 opaque_debug_tot_sleep_dur; + /* Contains the value of Vdev pause bitmap from wal_vdev */ + A_UINT32 opaque_debug_pause_bitmap; + /* opaque_debug_last_send_to_host_deauth_tsf: + * Contains the value of Last TSF time last_send_to_host_deauth_tsf + * from wlan_vdev. + */ + A_UINT32 opaque_debug_last_send_to_host_deauth_tsf; + /* Contains the value of debug_short_ssid from wlan_vdev */ + A_UINT32 opaque_debug_short_ssid; + /* Bitfield macro's expansion variables */ + /* opaque_debug_vdev_amsdu_bitfield: + * bit 7:0 - Contains the value of dis_dyn_bw_rts from wlan_vdev, + * 15:8 - max_amsdu, + * 23:16 - def_amsdu, + * 31:24 - he_bss_color + */ + A_UINT32 opaque_debug_vdev_amsdu_bitfield; + /* opaque_debug_vdev_ac_failure_configs: + * bit 7:0 - Contains the value of dhe_def_pe_duratio from wal_vdev, + * 15:8 - minimum_allowed_mcs, + * 23:16 - max_11ac_to_leg_rts_fallback_th, + * 31:24 - max_11ac_rts_consec_failure_th + */ + A_UINT32 opaque_debug_vdev_ac_failure_configs; + /* opaque_debug_vdev_pkt_type_info: + * bit 7:0 - Contains the value of input_pkt_type from wal_vdev, + * 15:8 - recv_pkt_type, + * 23:16 - disable_intra_fwd, + * 31:24 - ps_awake + */ + A_UINT32 opaque_debug_vdev_pkt_type_info; + /* opaque_debug_vdev_ba_param_bitfield: + * bit 7:0 - Contains the value of snr_cal_count from wal_vdev, + * 15:8 - amsdu_auto_enable, + * 23:16 - param_ba_timeout, + * 31:24 - param_ba_buffer_size + */ + A_UINT32 opaque_debug_vdev_ba_param_bitfield; + /* opaque_debug_vdev_aggr_bitfield: + * bit 7:0 - Contains the value of param_amsdu_support from wal_vdev, + * 15:8 - param_ba_retry_max, + * 23:16 - tx_aggr_size, + * 31:24 - rx_aggr_size + */ + A_UINT32 opaque_debug_vdev_aggr_bitfield; + /* opaque_debug_vdev_event_delivery: + * bit 7:0 - Contains the value of tqm_bypass_enabled from wal_vdev, + * 15:8 - wmmac_timer_vote_cnt, + * 23:16 - peer_event_delivery_in_progress, + * 31:24 - vdev_event_delivery_in_progress + */ + A_UINT32 opaque_debug_vdev_event_delivery; + /* opaque_debug_vdev_cap_slot_bitfield: + * bit 7:0 - Contains the value of bcn_max_slot from wal_vdev, + * 15:8 - bcn_curr_slot, + * 23:16 - mgmt_tx_power, + * 31:24 - mbssid_capable_association + */ + A_UINT32 opaque_debug_vdev_cap_slot_bitfield; + /* opaque_debug_vdev_bcn_configs: + * bit 7:0 - Contains the value of mbssid_txbssid_association from + * wal_vdev, + * 15:8 - consec_beacon_skip, + * 23:16 - consec_beacon_skip_cnt, + * 31:24 - max_consec_beacon_skip + */ + A_UINT32 opaque_debug_vdev_bcn_configs; + /* Contains the value of opaque_debug_vdev_cmd_info */ + A_UINT32 opaque_debug_vdev_cmd_info; + /* opaque_debug_vdev_mac_configs: + * bit 7:0 - Contains the value of pause_cnt from wlan_vdev, + * 15:8 - e_mac_id, + * 23:16 - is_transmit_bssid, + * 31:24 - rts_rc_flag + */ + A_UINT32 opaque_debug_vdev_mac_configs; + /* opaque_debug_vdev_mode_configs: + * bit 7:0 - Contains the value of ic_opmode from wlan_vdev, + * 15:8 - ic_subopmode, + * 23:16 - ic_curmode, + * 31:24 - vdev_up_cmd_cnt + */ + A_UINT32 opaque_debug_vdev_mode_configs; + /* opaque_debug_vdev_keepalive_bitfields: + * bit 7:0 - keepalive_method + * 15:8 - keepalive_prohibit_data_mgmt + * 23:16 - resp_type + * 31:24 - ap_detect_out_of_sync_sleeping_sta_time_secs + */ + A_UINT32 opaque_debug_vdev_keepalive_bitfields; + /* opaque_debug_vdev_bcn_drift_info: + * bit 7:0 - bcn_drift_cnt + * 15:8 - bcn_drift_calibration + * 23:16 - rts_cts_default + * 31:24 - vdev_down_cmd_cnt + */ + A_UINT32 opaque_debug_vdev_bcn_drift_info; + /* opaque_debug_vdev_arp_configs: + * bit 7:0 - Contains the value of tbtt_link_type from wlan_vdev, + * 15:8 - is_arp_in_air, + * 23:16 - is_ns_in_air, + * 31:24 - num_of_keepalive_attempts + */ + A_UINT32 opaque_debug_vdev_arp_configs; + /* opaque_debug_vdev_streams_configs: + * bit 7:0 - n_beacons_since_last_rssi_report + * 15:8 - num_ofld_peer_alloced + * 23:16 - preferred_tx_streams + * 31:24 - preferred_rx_streams + */ + A_UINT32 opaque_debug_vdev_streams_configs; + /* opaque_debug_vdev_chains_configs: + * bit 7:0 - Contains the value of preferred_tx_streams_160 from + * wlan_vdev, + * 15:8 - preferred_rx_streams_160, + * 23:16 - tx_chains_num_11b, + * 31:24 - tx_chains_num_11ag + */ + A_UINT32 opaque_debug_vdev_chains_configs; + /* opaque_debug_vdev_power_cap_configs: + * bit 7:0 - Contains the value of supp_op_cls_ie_len from wlan_vdev, + * 15:8 - rm_en_cap_ie_len, + * 23:16 - power_cap_ie_len, + * 31:24 - supp_channel_ie_len + */ + A_UINT32 opaque_debug_vdev_power_cap_configs; + /* opaque_debug_vdev_wmm_mbo_configs: + * bit 7:0 - Contains the value of wmm_tspec_ie_len from wlan_vdev, + * 15:8 - ccx_version_ie_len, + * 23:16 - extn_dh_ie_len, + * 31:24 - mbo_ie_len + */ + A_UINT32 opaque_debug_vdev_wmm_mbo_configs; + /* opaque_debug_vdev_remote_configs: + * bit 7:0 - Contains the value of rsnxe_ie_len from wlan_vdev, + * 15:8 - remote_peer_cnt + * 23:16 - p2p_cli_pause_type + * 31:24 - mu_edca_update_count + */ + A_UINT32 opaque_debug_vdev_remote_configs; + /* opaque_debug_vdev_stats_id_configs: + * bit 7:0 - vdev_stats_id + * 15:8 - vdev_stats_id_valid + * 23:16 - preferred_tx_streams_320 + * 31:24 - preferred_rx_streams_320 + */ + A_UINT32 opaque_debug_vdev_stats_id_configs; + /* opaque_debug_vdev_assoc_peer_configs: + * bit 7:0 - unused / reserved + * 15:8 - group_cipher + * 31:16 - assoc_id + */ + A_UINT32 opaque_debug_vdev_assoc_peer_configs; + /* opaque_debug_vdev_mhz_fils_configs: + * bit 15:0 - Contains the value of bss_channel_mhz from wal_vdev, + * 31:16 - config_fils_period + */ + A_UINT32 opaque_debug_vdev_mhz_fils_configs; + /* opaque_debug_vdev_fils_period: + * bit 15:0 - Contains the value of calc_fils_period from wal_vdev, + * 31:16 - ic_txseqs_cmn + */ + A_UINT32 opaque_debug_vdev_fils_period; + /* opaque_debug_vdev_inactive_time: + * bit 15:0 - Contains the value of + * ap_keepalive_min_idle_inactive_time_secs from wlan_vdev, + * 31:16 - ap_keepalive_max_idle_inactive_time_secs + */ + A_UINT32 opaque_debug_vdev_inactive_time; + /* opaque_debug_vdev_chain_mask_configs: + * bit 15:0 - Contains the value of + * ap_keepalive_max_unresponsive_time_secs from wlan_vdev, + * 31:16 - chain_mask + */ + A_UINT32 opaque_debug_vdev_chain_mask_configs; + /* opaque_debug_vdev_ie_len_configs: + * bit 15:0 - num_mcast_filters + * 31:16 - ext_cap_ie_len + */ + A_UINT32 opaque_debug_vdev_ie_len_configs; + /* opaque_debug_vdev_fils_configs: + * bit 15:0 - Contains the value of fils_channel_guard_time from wlan_vdev, + * 31:16 - fd_tmpl_len + */ + A_UINT32 opaque_debug_vdev_fils_configs; + /* opaque_debug_vdev_chan_configs: + * bit 15:0 - Contains the value of common_rsn_caps from wlan_vdev, + * 31:16 - off_ch_active_dwell_time + */ + A_UINT32 opaque_debug_vdev_chan_configs; + /* opaque_debug_vdev_dwell_configs: + * bit 15:0 - Contains the value of off_ch_passive_dwell_time from + * wlan_vdev, + * 31:16 - current_pause_request_id + */ + A_UINT32 opaque_debug_vdev_dwell_configs; + /* opaque_debug_vdev_wmi_configs: + * bit 0 - Contains the value of hide_ssid_enable from wlan_vdev, + * 1 - b_none_protocol_paused + * 2 - dpd_cal_state + * 4 - req_bcn_q_unpause + * 5 - bt_coex_enable_cts2s + * 6 - dpd_delay_n_beacon + * 8 - b_need_check_first_beacon + * 9 - ap_peer_keepalive_max_idle_time_reached + * 10 - leakyap_cts2s_enable + * 11 - stasapscc_in_mcc + * 12 - stasapscc_in_mcc_cts2s_enable + * 13 - is_vdev_stopping + * 14 - is_wmi_vdev_down + * 15 - is_vdev_down_pending + * 16 - vdev_delete_in_progress + * 17 - cac_enabled + * 18 - is_quaterrate + * 19 - is_halfrate + * 20 - stop_resp_event_blocked + * 21 - use_enhanced_mcast_filter + * 22 - is_start_pending_on_asm + * 23 - no_null_to_ap_for_roaming + * 24 - is_loopback_cal_pending + * 25 - vdev_delete_acked + * 26 - bc_proberesp_enable + * 27 - is_wmm_param + * 28 - is_connect_in_progress + * 29 - is_mu_edca_param + * 30 - send_del_resp_tohost + * 31 - is_restart_different_ch + */ + A_UINT32 opaque_debug_vdev_wmi_configs; + /* opaque_debug_vdev_hu_mu_configs: + * bit 0 - Contains the value of proto_ps_status from wlan_vdev, + * 1 - smps_intolerant + * 2 - is_offload_registered_for_connection + * 3 - is_bss_beacon_offload_registered + * 4 - is_prob_resp_offload_registered + * 5 - is_ibss_beacon_offload_registered + * 6 - is_keepalive_attempts_exhausted + * 7 - is_bcn_tx_ie_changed_log + * 8 - he_su_bfee + * 9 - he_su_bfer + * 10 - he_mu_bfee + * 11 - he_mu_bfer + * 12 - he_dl_ofdma + * 13 - he_ul_ofdma + * 14 - he_ul_mumimo + * 15 - ul_mu_resp + * 23:16 - alt_rssi_non_srg + * 31:24 - alt_rssi_srg + */ + A_UINT32 opaque_debug_vdev_hu_mu_configs; + /* opaque_debug_vdev_sm_chan_configs: + * bit 0 - Contains the value of he_bss_color_en from wlan_vdev, + * 1 - he_txbf_ofdma + * 2 - non_srg_enable + * 3 - srg_enable + * 4 - srp_enable + * 5 - sr_initialized + * 6 - sr_rings_initialized + * 10:7 - per_ac_obss_pd_enable + * 11 - ifup + * 12 - ifactive + * 13 - ifpaused + * 14 - ifoutofsync + * 15 - is_free + * 16 - is_nawds + * 17 - hw_flag + * 18 - ch_req_flag + * 20 - restart_resp + * 21 - first_beacon_recv_wait + * 22 - erpenabled + * 23 - start_responded + * 24 - bcn_sync_crit_req_act + * 25 - recal_notif_registered + * 26 - bcn_tx_paused + * 27 - he_bss_color_en_bypass + * 28 - default_ba_mode + * 29 - ba_256_bitmap_enable + * 30 - ba_256_bitmap_tx_disable + * 31 - is_multi_group_key_enabled + */ + A_UINT32 opaque_debug_vdev_sm_chan_configs; + /* + * The following 4 opaque_debug variables are provided purely for + * debugging by technicians who have outside knowledge of what kind of + * values the target has placed into these fields. + * The host must not interpret the values of these fields, since the + * meaning of the values provided in these fields may change without + * regard for backwards compatibility or interoperability. + */ + A_UINT32 opaque_debug_field_1; + A_UINT32 opaque_debug_field_2; + A_UINT32 opaque_debug_field_3; + A_UINT32 opaque_debug_field_4; +} wmi_ctrl_path_vdev_stats_struct; + + +#define WMI_VDEV_STATS_DIS_DYN_BW_RTS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_DIS_DYN_BW_RTS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_MAX_AMSDU_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_MAX_AMSDU_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_DEF_AMSDU_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_DEF_AMSDU_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_HW_BSS_COLOR_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_HW_BSS_COLOR_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_HE_DEF_PE_DURATION_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_HE_DEF_PE_DURATION_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_MINIMUM_ALLOWED_MCS_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_MINIMUM_ALLOWED_MCS_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_MAX_11AC_TO_LEG_RTS_FALLBACK_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_MAX_11AC_TO_LEG_RTS_FALLBACK_TH_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MAX_11AC_RTS_CONSEC_FAILURE_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MAX_11AC_RTS_CONSEC_FAILURE_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_INPUT_PKT_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_INPUT_PKT_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_RECV_PKT_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_RECV_PKT_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_DISABLE_INTRA_FWD_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_DISABLE_INTRA_FWD_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_PS_AWAKE_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_PS_AWAKE_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_SNR_CAL_COUNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_SNR_CAL_COUNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_AMSDU_AUTO_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_AMSDU_AUTO_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_PARAM_BA_TIMEOUT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_PARAM_BA_TIMEOUT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_PARAM_BA_BUFFER_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_PARAM_BA_BUFFER_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_PARAM_AMSDU_SUPPORT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_PARAM_AMSDU_SUPPORT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_PARAM_BA_RETRY_MAX_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_PARAM_BA_RETRY_MAX_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_TX_AGGR_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_TX_AGGR_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_RX_AGGR_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_RX_AGGR_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_TQM_BYPASS_ENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_TQM_BYPASS_ENABLED_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_WMMAC_TIMER_VOTE_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_WMMAC_TIMER_VOTE_CNT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_PEER_EVENT_DELIVERY_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_PEER_EVENT_DELIVERY_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_VDEV_EVENT_DELIVERY_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_VDEV_EVENT_DELIVERY_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_BCN_MAX_SLOT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_BCN_MAX_SLOT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_BCN_CURR_SLOT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_BCN_CURR_SLOT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_MGMT_TX_POWER_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_MGMT_TX_POWER_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MBSSID_CAPABLE_ASSOCIATION_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MBSSID_CAPABLE_ASSOCIATION_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_MBSSID_TXBSSID_ASSOCIATION_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_MBSSID_TXBSSID_ASSOCIATION_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MAX_CONSEC_BEACON_SKIP_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MAX_CONSEC_BEACON_SKIP_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_BCN_DRIFT_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_BCN_DRIFT_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_PAUSE_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_PAUSE_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_E_MAC_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_E_MAC_ID_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_IS_TRANSMIT_BSSID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_IS_TRANSMIT_BSSID_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_RTS_RC_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_RTS_RC_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_IC_OPMODE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_IC_OPMODE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_IC_SUBOPMODE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_IC_SUBOPMODE_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_IC_CURMODE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_IC_CURMODE_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_VDEV_UP_CMD_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_VDEV_UP_CMD_CNT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_KEEPALIVE_METHOD_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_KEEPALIVE_METHOD_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_KEEPALIVE_PROHIBIT_DATA_MGMT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_KEEPALIVE_PROHIBIT_DATA_MGMT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_RESP_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_RESP_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_BCN_DRIFT_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_BCN_DRIFT_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_TBTT_LINK_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_TBTT_LINK_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_IS_ARP_IN_AIR_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_IS_ARP_IN_AIR_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_IS_NS_IN_AIR_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_IS_NS_IN_AIR_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_NUM_OF_KEEPALIVE_ATTEMPTS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_NUM_OF_KEEPALIVE_ATTEMPTS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_N_BEACONS_SINCE_LAST_RSSI_REPORT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_N_BEACONS_SINCE_LAST_RSSI_REPORT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_NUM_OFLD_PEER_ALLOCED_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_NUM_OFLD_PEER_ALLOCED_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_160_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_160_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_160_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_160_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_TX_CHAINS_NUM_11B_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_TX_CHAINS_NUM_11B_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_TX_CHAINS_NUM_11AG_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_TX_CHAINS_NUM_11AG_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_SUPP_OP_CLS_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_SUPP_OP_CLS_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_RM_EN_CAP_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_RM_EN_CAP_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_POWER_CAP_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_POWER_CAP_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_SUPP_CHANNEL_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_SUPP_CHANNEL_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_WMM_TSPEC_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_WMM_TSPEC_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_CCX_VERSION_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_CCX_VERSION_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_EXTN_DH_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_EXTN_DH_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MBO_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MBO_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_RSNXE_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_RSNXE_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_REMOTE_PEER_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_REMOTE_PEER_CNT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_P2P_CLI_PAUSE_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_P2P_CLI_PAUSE_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MU_EDCA_UPDATE_COUNT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MU_EDCA_UPDATE_COUNT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_ID_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_ID_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_ID_VALID_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_320_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_320_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_320_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_320_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +/* bits 7:0 unused / reserved */ +#define WMI_VDEV_STATS_GROUP_CIPHER_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_GROUP_CIPHER_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_ASSOC_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_ASSOC_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_BSS_CHANNEL_MHZ_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_BSS_CHANNEL_MHZ_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_CONFIG_FILS_PERIOD_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_CONFIG_FILS_PERIOD_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_CALC_FILS_PERIOD_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_CALC_FILS_PERIOD_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_IC_TXSEQS_CMN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_IC_TXSEQS_CMN_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_CHAIN_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_CHAIN_MASK_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_NUM_MCAST_FILTERS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_NUM_MCAST_FILTERS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_EXT_CAP_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_EXT_CAP_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_FILS_CHANNEL_GUARD_TIME_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_FILS_CHANNEL_GUARD_TIME_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_FD_TMPL_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_FD_TMPL_LEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_COMMON_RSN_CAPS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_COMMON_RSN_CAPS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_OFF_CH_ACTIVE_DWELL_TIME_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_OFF_CH_ACTIVE_DWELL_TIME_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_OFF_CH_PASSIVE_DWELL_TIME_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_OFF_CH_PASSIVE_DWELL_TIME_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_CURRENT_PAUSE_REQUEST_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_CURRENT_PAUSE_REQUEST_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_HIDE_SSID_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_VDEV_STATS_HIDE_SSID_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_VDEV_STATS_B_NONE_PROTOCOL_PAUSED_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_VDEV_STATS_B_NONE_PROTOCOL_PAUSED_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_VDEV_STATS_DPD_CAL_STATE_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 2, val) +#define WMI_VDEV_STATS_DPD_CAL_STATE_GET(flag) \ + WMI_GET_BITS(flag, 2, 2) +#define WMI_VDEV_STATS_REQ_BCN_Q_UNPAUSE_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 1, val) +#define WMI_VDEV_STATS_REQ_BCN_Q_UNPAUSE_GET(flag) \ + WMI_GET_BITS(flag, 4, 1) +#define WMI_VDEV_STATS_BT_COEX_ENABLE_CTS2S_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 1, val) +#define WMI_VDEV_STATS_BT_COEX_ENABLE_CTS2S_GET(flag) \ + WMI_GET_BITS(flag, 5, 1) +#define WMI_VDEV_STATS_DPD_DELAY_N_BEACON_SET(flag, val) \ + WMI_SET_BITS(flag, 6, 2, val) +#define WMI_VDEV_STATS_DPD_DELAY_N_BEACON_GET(flag) \ + WMI_GET_BITS(flag, 6, 2) +#define WMI_VDEV_STATS_B_NEED_CHECK_FIRST_BEACON_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 1, val) +#define WMI_VDEV_STATS_B_NEED_CHECK_FIRST_BEACON_GET(flag) \ + WMI_GET_BITS(flag, 8, 1) +#define WMI_VDEV_STATS_AP_PEER_KEEPALIVE_MAX_IDLE_TIME_REACHED_SET(flag, val) \ + WMI_SET_BITS(flag, 9, 1, val) +#define WMI_VDEV_STATS_AP_PEER_KEEPALIVE_MAX_IDLE_TIME_REACHED_GET(flag) \ + WMI_GET_BITS(flag, 9, 1) +#define WMI_VDEV_STATS_LEAKYAP_CTS2S_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 10, 1, val) +#define WMI_VDEV_STATS_LEAKYAP_CTS2S_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 10, 1) +#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_SET(flag, val) \ + WMI_SET_BITS(flag, 11, 1, val) +#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_GET(flag) \ + WMI_GET_BITS(flag, 11, 1) +#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_CTS2S_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 1, val) +#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_CTS2S_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 12, 1) +#define WMI_VDEV_STATS_IS_VDEV_STOPPING_SET(flag, val) \ + WMI_SET_BITS(flag, 13, 1, val) +#define WMI_VDEV_STATS_IS_VDEV_STOPPING_GET(flag) \ + WMI_GET_BITS(flag, 13, 1) +#define WMI_VDEV_STATS_IS_WMI_VDEV_DOWN_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 1, val) +#define WMI_VDEV_STATS_IS_WMI_VDEV_DOWN_GET(flag) \ + WMI_GET_BITS(flag, 14, 1) +#define WMI_VDEV_STATS_IS_VDEV_DOWN_PENDING_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 1, val) +#define WMI_VDEV_STATS_IS_VDEV_DOWN_PENDING_GET(flag) \ + WMI_GET_BITS(flag, 15, 1) +#define WMI_VDEV_STATS_VDEV_DELETE_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 1, val) +#define WMI_VDEV_STATS_VDEV_DELETE_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 16, 1) +#define WMI_VDEV_STATS_CAC_ENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 17, 1, val) +#define WMI_VDEV_STATS_CAC_ENABLED_GET(flag) \ + WMI_GET_BITS(flag, 17, 1) +#define WMI_VDEV_STATS_IS_QUATERRATE_SET(flag, val) \ + WMI_SET_BITS(flag, 18, 1, val) +#define WMI_VDEV_STATS_IS_QUATERRATE_GET(flag) \ + WMI_GET_BITS(flag, 18, 1) +#define WMI_VDEV_STATS_IS_HALFRATE_SET(flag, val) \ + WMI_SET_BITS(flag, 19, 1, val) +#define WMI_VDEV_STATS_IS_HALFRATE_GET(flag) \ + WMI_GET_BITS(flag, 19, 1) +#define WMI_VDEV_STATS_STOP_RESP_EVENT_BLOCKED_SET(flag, val) \ + WMI_SET_BITS(flag, 20, 1, val) +#define WMI_VDEV_STATS_STOP_RESP_EVENT_BLOCKED_GET(flag) \ + WMI_GET_BITS(flag, 20, 1) +#define WMI_VDEV_STATS_USE_ENHANCED_MCAST_FILTER_SET(flag, val) \ + WMI_SET_BITS(flag, 21, 1, val) +#define WMI_VDEV_STATS_USE_ENHANCED_MCAST_FILTER_GET(flag) \ + WMI_GET_BITS(flag, 21, 1) +#define WMI_VDEV_STATS_IS_START_PENDING_ON_ASM_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 1, val) +#define WMI_VDEV_STATS_IS_START_PENDING_ON_ASM_GET(flag) \ + WMI_GET_BITS(flag, 22, 1) +#define WMI_VDEV_STATS_NO_NULL_TO_AP_FOR_ROAMING_SET(flag, val) \ + WMI_SET_BITS(flag, 23, 1, val) +#define WMI_VDEV_STATS_NO_NULL_TO_AP_FOR_ROAMING_GET(flag) \ + WMI_GET_BITS(flag, 23, 1) +#define WMI_VDEV_STATS_IS_LOOPBACK_CAL_PENDING_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 1, val) +#define WMI_VDEV_STATS_IS_LOOPBACK_CAL_PENDING_GET(flag) \ + WMI_GET_BITS(flag, 24, 1) +#define WMI_VDEV_STATS_VDEV_DELETE_ACKED_SET(flag, val) \ + WMI_SET_BITS(flag, 25, 1, val) +#define WMI_VDEV_STATS_VDEV_DELETE_ACKED_GET(flag) \ + WMI_GET_BITS(flag, 25, 1) +#define WMI_VDEV_STATS_BC_PROBERESP_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 26, 1, val) +#define WMI_VDEV_STATS_BC_PROBERESP_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 26, 1) +#define WMI_VDEV_STATS_IS_WMM_PARAM_SET_SET(flag, val) \ + WMI_SET_BITS(flag, 27, 1, val) +#define WMI_VDEV_STATS_IS_WMM_PARAM_SET_GET(flag) \ + WMI_GET_BITS(flag, 27, 1) +#define WMI_VDEV_STATS_IS_CONNECT_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 28, 1, val) +#define WMI_VDEV_STATS_IS_CONNECT_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 28, 1) +#define WMI_VDEV_STATS_IS_MU_EDCA_PARAM_SET_SET(flag, val) \ + WMI_SET_BITS(flag, 29, 1, val) +#define WMI_VDEV_STATS_IS_MU_EDCA_PARAM_SET_GET(flag) \ + WMI_GET_BITS(flag, 29, 1) +#define WMI_VDEV_STATS_SEND_DEL_RESP_TOHOST_SET(flag, val) \ + WMI_SET_BITS(flag, 30, 1, val) +#define WMI_VDEV_STATS_SEND_DEL_RESP_TOHOST_GET(flag) \ + WMI_GET_BITS(flag, 30, 1) +#define WMI_VDEV_STATS_IS_RESTART_DIFFERENT_CH_SET(flag, val) \ + WMI_SET_BITS(flag, 31, 1, val) +#define WMI_VDEV_STATS_IS_RESTART_DIFFERENT_CH_GET(flag) \ + WMI_GET_BITS(flag, 31, 1) + +#define WMI_VDEV_STATS_PROTO_PS_STATUS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_VDEV_STATS_PROTO_PS_STATUS_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_VDEV_STATS_SMPS_INTOLERANT_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_VDEV_STATS_SMPS_INTOLERANT_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_VDEV_STATS_IS_OFFLOAD_REGISTERED_FOR_CONNECTION_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_VDEV_STATS_IS_OFFLOAD_REGISTERED_FOR_CONNECTION_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_VDEV_STATS_IS_BSS_BEACON_OFFLOAD_REGISTERED_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 1, val) +#define WMI_VDEV_STATS_IS_BSS_BEACON_OFFLOAD_REGISTERED_GET(flag) \ + WMI_GET_BITS(flag, 3, 1) +#define WMI_VDEV_STATS_IS_PROB_RESP_OFFLOAD_REGISTERED_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 1, val) +#define WMI_VDEV_STATS_IS_PROB_RESP_OFFLOAD_REGISTERED_GET(flag) \ + WMI_GET_BITS(flag, 4, 1) +#define WMI_VDEV_STATS_IS_IBSS_BEACON_OFFLOAD_REGISTERED_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 1, val) +#define WMI_VDEV_STATS_IS_IBSS_BEACON_OFFLOAD_REGISTERED_GET(flag) \ + WMI_GET_BITS(flag, 5, 1) +#define WMI_VDEV_STATS_IS_KEEPALIVE_ATTEMPTS_EXHAUSTED_SET(flag, val) \ + WMI_SET_BITS(flag, 6, 1, val) +#define WMI_VDEV_STATS_IS_KEEPALIVE_ATTEMPTS_EXHAUSTED_GET(flag) \ + WMI_GET_BITS(flag, 6, 1) +#define WMI_VDEV_STATS_IS_BCN_TX_IE_CHANGED_LOG_SET(flag, val) \ + WMI_SET_BITS(flag, 7, 1, val) +#define WMI_VDEV_STATS_IS_BCN_TX_IE_CHANGED_LOG_GET(flag) \ + WMI_GET_BITS(flag, 7, 1) +#define WMI_VDEV_STATS_HE_SU_BFEE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 1, val) +#define WMI_VDEV_STATS_HE_SU_BFEE_GET(flag) \ + WMI_GET_BITS(flag, 8, 1) +#define WMI_VDEV_STATS_HE_SU_BFER_SET(flag, val) \ + WMI_SET_BITS(flag, 9, 1, val) +#define WMI_VDEV_STATS_HE_SU_BFER_GET(flag) \ + WMI_GET_BITS(flag, 9, 1) +#define WMI_VDEV_STATS_HE_MU_BFEE_SET(flag, val) \ + WMI_SET_BITS(flag, 10, 1, val) +#define WMI_VDEV_STATS_HE_MU_BFEE_GET(flag) \ + WMI_GET_BITS(flag, 10, 1) +#define WMI_VDEV_STATS_HE_MU_BFER_SET(flag, val) \ + WMI_SET_BITS(flag, 11, 1, val) +#define WMI_VDEV_STATS_HE_MU_BFER_GET(flag) \ + WMI_GET_BITS(flag, 11, 1) +#define WMI_VDEV_STATS_HE_DL_OFDMA_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 1, val) +#define WMI_VDEV_STATS_HE_DL_OFDMA_GET(flag) \ + WMI_GET_BITS(flag, 12, 1) +#define WMI_VDEV_STATS_HE_UL_OFDMA_SET(flag, val) \ + WMI_SET_BITS(flag, 13, 1, val) +#define WMI_VDEV_STATS_HE_UL_OFDMA_GET(flag) \ + WMI_GET_BITS(flag, 13, 1) +#define WMI_VDEV_STATS_HE_UL_MUMIMO_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 1, val) +#define WMI_VDEV_STATS_HE_UL_MUMIMO_GET(flag) \ + WMI_GET_BITS(flag, 14, 1) +#define WMI_VDEV_STATS_UL_MU_RESP_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 1, val) +#define WMI_VDEV_STATS_UL_MU_RESP_GET(flag) \ + WMI_GET_BITS(flag, 15, 1) +#define WMI_VDEV_STATS_ALT_RSSI_NON_SRG_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_ALT_RSSI_NON_SRG_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_ALT_RSSI_SRG_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_ALT_RSSI_SRG_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_VDEV_STATS_HE_TXBF_OFDMA_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_VDEV_STATS_HE_TXBF_OFDMA_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_VDEV_STATS_NON_SRG_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_VDEV_STATS_NON_SRG_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_VDEV_STATS_SRG_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 1, val) +#define WMI_VDEV_STATS_SRG_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 3, 1) +#define WMI_VDEV_STATS_SRP_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 1, val) +#define WMI_VDEV_STATS_SRP_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 4, 1) +#define WMI_VDEV_STATS_SR_INITIALIZED_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 1, val) +#define WMI_VDEV_STATS_SR_INITIALIZED_GET(flag) \ + WMI_GET_BITS(flag, 5, 1) +#define WMI_VDEV_STATS_SR_RINGS_INITIALIZED_SET(flag, val) \ + WMI_SET_BITS(flag, 6, 1, val) +#define WMI_VDEV_STATS_SR_RINGS_INITIALIZED_GET(flag) \ + WMI_GET_BITS(flag, 6, 1) +#define WMI_VDEV_STATS_PER_AC_OBSS_PD_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 7, 4, val) +#define WMI_VDEV_STATS_PER_AC_OBSS_PD_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 7, 4) +#define WMI_VDEV_STATS_IFUP_SET(flag, val) \ + WMI_SET_BITS(flag, 11, 1, val) +#define WMI_VDEV_STATS_IFUP_GET(flag) \ + WMI_GET_BITS(flag, 11, 1) +#define WMI_VDEV_STATS_IFACTIVE_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 1, val) +#define WMI_VDEV_STATS_IFACTIVE_GET(flag) \ + WMI_GET_BITS(flag, 12, 1) +#define WMI_VDEV_STATS_IFPAUSED_SET(flag, val) \ + WMI_SET_BITS(flag, 13, 1, val) +#define WMI_VDEV_STATS_IFPAUSED_GET(flag) \ + WMI_GET_BITS(flag, 13, 1) +#define WMI_VDEV_STATS_IFOUTOFSYNC_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 1, val) +#define WMI_VDEV_STATS_IFOUTOFSYNC_GET(flag) \ + WMI_GET_BITS(flag, 14, 1) +#define WMI_VDEV_STATS_IS_FREE_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 1, val) +#define WMI_VDEV_STATS_IS_FREE_GET(flag) \ + WMI_GET_BITS(flag, 15, 1) +#define WMI_VDEV_STATS_IS_NAWDS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 1, val) +#define WMI_VDEV_STATS_IS_NAWDS_GET(flag) \ + WMI_GET_BITS(flag, 16, 1) +#define WMI_VDEV_STATS_HW_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 17, 1, val) +#define WMI_VDEV_STATS_HW_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 17, 1) +#define WMI_VDEV_STATS_CH_REQ_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 18, 2, val) +#define WMI_VDEV_STATS_CH_REQ_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 18, 2) +#define WMI_VDEV_STATS_RESTART_RESP_SET(flag, val) \ + WMI_SET_BITS(flag, 20, 1, val) +#define WMI_VDEV_STATS_RESTART_RESP_GET(flag) \ + WMI_GET_BITS(flag, 20, 1) +#define WMI_VDEV_STATS_FIRST_BEACON_RECV_WAIT_SET(flag, val) \ + WMI_SET_BITS(flag, 21, 1, val) +#define WMI_VDEV_STATS_FIRST_BEACON_RECV_WAIT_GET(flag) \ + WMI_GET_BITS(flag, 21, 1) +#define WMI_VDEV_STATS_ERPENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 1, val) +#define WMI_VDEV_STATS_ERPENABLED_GET(flag) \ + WMI_GET_BITS(flag, 22, 1) +#define WMI_VDEV_STATS_START_RESPONDED_SET(flag, val) \ + WMI_SET_BITS(flag, 23, 1, val) +#define WMI_VDEV_STATS_START_RESPONDED_GET(flag) \ + WMI_GET_BITS(flag, 23, 1) +#define WMI_VDEV_STATS_BCN_SYNC_CRIT_REQ_ACT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 1, val) +#define WMI_VDEV_STATS_BCN_SYNC_CRIT_REQ_ACT_GET(flag) \ + WMI_GET_BITS(flag, 24, 1) +#define WMI_VDEV_STATS_RECAL_NOTIF_REGISTERED_SET(flag, val) \ + WMI_SET_BITS(flag, 25, 1, val) +#define WMI_VDEV_STATS_RECAL_NOTIF_REGISTERED_GET(flag) \ + WMI_GET_BITS(flag, 25, 1) +#define WMI_VDEV_STATS_BCN_TX_PAUSED_SET(flag, val) \ + WMI_SET_BITS(flag, 26, 1, val) +#define WMI_VDEV_STATS_BCN_TX_PAUSED_GET(flag) \ + WMI_GET_BITS(flag, 26, 1) +#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_BYPASS_SET(flag, val) \ + WMI_SET_BITS(flag, 27, 1, val) +#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_BYPASS_GET(flag) \ + WMI_GET_BITS(flag, 27, 1) +#define WMI_VDEV_STATS_DEFAULT_BA_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 28, 1, val) +#define WMI_VDEV_STATS_DEFAULT_BA_MODE_GET(flag) \ + WMI_GET_BITS(flag, 28, 1) +#define WMI_VDEV_STATS_BA_256_BITMAP_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 29, 1, val) +#define WMI_VDEV_STATS_BA_256_BITMAP_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 29, 1) +#define WMI_VDEV_STATS_BA_256_BITMAP_TX_DISABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 30, 1, val) +#define WMI_VDEV_STATS_BA_256_BITMAP_TX_DISABLE_GET(flag) \ + WMI_GET_BITS(flag, 30, 1) +#define WMI_VDEV_STATS_IS_MULTI_GROUP_KEY_ENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 31, 1, val) +#define WMI_VDEV_STATS_IS_MULTI_GROUP_KEY_ENABLED_GET(flag) \ + WMI_GET_BITS(flag, 31, 1) + +typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_sta_rrm_stats_struct */ + A_UINT32 tlv_header; + A_UINT32 dot11GroupTransmittedFrameCount; + A_UINT32 dot11GroupReceivedFrameCount; + A_UINT32 dot11TransmittedFrameCount; + A_UINT32 dot11AckFailureCount; + A_UINT32 dot11FailedCount; + A_UINT32 dot11FCSErrorCount; + A_UINT32 dot11RTSSuccessCount; + A_UINT32 dot11RTSFailureCount; +} wmi_ctrl_path_sta_rrm_stats_struct; + /** * peer statistics. */ @@ -12873,7 +15957,7 @@ typedef struct { A_UINT32 vdev_id; /** VDEV type (AP,STA,IBSS,MONITOR) */ A_UINT32 vdev_type; - /** VDEV subtype (P2PDEV, P2PCLI, P2PGO, BT3.0)*/ + /** VDEV subtype (P2PDEV, P2PCLI, P2PGO, BT3.0, BRIDGE) */ A_UINT32 vdev_subtype; /** VDEV MAC address */ wmi_mac_addr vdev_macaddr; @@ -12956,6 +16040,14 @@ typedef struct { #define WMI_MLO_FLAGS_SET_LINK_ADD(mlo_flags, value) WMI_SET_BITS(mlo_flags, 8, 1, value) #define WMI_MLO_FLAGS_GET_LINK_DEL(mlo_flags) WMI_GET_BITS(mlo_flags, 9, 1) #define WMI_MLO_FLAGS_SET_LINK_DEL(mlo_flags, value) WMI_SET_BITS(mlo_flags, 9, 1, value) +#define WMI_MLO_FLAGS_GET_BRIDGE_PEER(mlo_flags) WMI_GET_BITS(mlo_flags, 10, 1) +#define WMI_MLO_FLAGS_SET_BRIDGE_PEER(mlo_flags, value) WMI_SET_BITS(mlo_flags, 10, 1, value) +#define WMI_MLO_FLAGS_GET_NSTR_BITMAP_PRESENT(mlo_flags) WMI_GET_BITS(mlo_flags, 11, 1) +#define WMI_MLO_FLAGS_SET_NSTR_BITMAP_PRESENT(mlo_flags, value) WMI_SET_BITS(mlo_flags, 11, 1, value) +#define WMI_MLO_FLAGS_GET_NSTR_BITMAP_SIZE(mlo_flags) WMI_GET_BITS(mlo_flags, 12, 1) +#define WMI_MLO_FLAGS_SET_NSTR_BITMAP_SIZE(mlo_flags, value) WMI_SET_BITS(mlo_flags, 12, 1, value) +#define WMI_MLO_FLAGS_GET_MLO_LINK_SWITCH(mlo_flags) WMI_GET_BITS(mlo_flags, 13, 1) +#define WMI_MLO_FLAGS_SET_MLO_LINK_SWITCH(mlo_flags, value) WMI_SET_BITS(mlo_flags, 13, 1, value) /* this structure used for pass mlo flags*/ typedef struct { @@ -12971,7 +16063,17 @@ typedef struct { mlo_force_link_inactive:1, /* indicate this link is forced inactive */ mlo_link_add:1, /* Indicate dynamic link addition in an MLD VAP */ mlo_link_del:1, /* Indicate dynamic link deletion in an MLD VAP */ - unused: 22; + mlo_bridge_peer:1, /* Indicate if this link has bridge_peer */ + nstr_bitmap_present:1, /* Indicate if at least one NSTR link pair is present in the MLD */ + /* nstr_bitmap_size: + * Set to 1 if the length of the corresponding NSTR + * Indication Bitmap subfield is equal to 2 octets. + * Set to 0 if the length of the corresponding NSTR + * Indication Bitmap subfield is equal to 1 octet. + */ + nstr_bitmap_size:1, + mlo_link_switch: 1, /* indicate the command is a part of link switch procedure */ + unused: 18; }; A_UINT32 mlo_flags; }; @@ -13103,6 +16205,14 @@ typedef enum { */ #define WMI_UNIFIED_VDEV_SUBTYPE_SMART_MON 0x7 +/* Subtype to indicate that the VDEV is in Bridge mode. + * Bridge VDEV is dummy VDEV required for 4 chip MLO scenario. + * Bridge Peer will be connected to Bridge VDEV. + * Bridge VDEV/PEER will be required to seamlessly transmit + * to diagonal links in 4 chip MLO. + */ +#define WMI_UNIFIED_VDEV_SUBTYPE_BRIDGE 0x8 + /** values for vdev_start_request flags */ /** Indicates that AP VDEV uses hidden ssid. only valid for * AP/GO */ @@ -13127,6 +16237,12 @@ typedef enum { * If SW encryption is enabled, key plumbing will not happen in FW. */ #define WMI_UNIFIED_VDEV_START_HW_ENCRYPTION_DISABLED (1<<4) +/** Indicates VAP is used for MLO repurpose. + * This Indicates that vap can be brought up as 11ax or 11be and can be + * repurposed based on the above stack on the fly to change from MLO to + * non MLO, currently we support only 11ax and 11be transition. + */ +#define WMI_UNIFIED_VDEV_START_MLO_REPURPOSE_VAP (1<<5) /* BSS color 0-6 */ #define WMI_HEOPS_COLOR_GET_D2(he_ops) WMI_GET_BITS(he_ops, 0, 6) @@ -14953,7 +18069,9 @@ typedef enum { * bit 0: URNM_MFPR in RSNXE * bit 1: MFPC in RSN CAP * bit 2: MFPR in RSN CAP - * bit 31:3 Reserved + * bit 3: URNM_MFPR_X20 in RSNXE + * bit 4: RSTA_EXTCAP_I2R_LMR_FB + * bit 31:5 Reserved */ WMI_VDEV_PARAM_11AZ_SECURITY_CONFIG, /* 0xAB */ @@ -15007,6 +18125,47 @@ typedef enum { */ WMI_VDEV_PARAM_DISABLE_LPI_ANT_OPTIMIZATION, /* 0xB9 */ + /* + * Param to update connected VDEV channel bandwidth. + * Target firmware should take care of notifying associated peers + * (except TDLS) about change in bandwidth, through OMN/OMI notification + * before performing bandwidth update internally. + * Please note incase of STA VDEV only BSS peer gets updated, + * associated TDLS peer bandwidth won't be impacted. + * + * The updated bandwidth is specified with a wmi_channel_width value. + */ + WMI_VDEV_PARAM_CHWIDTH_WITH_NOTIFY, /* 0xBA */ + + /* + * Min time between measurment for 11AZ NTB ranging + * in units of 100 microseconds + */ + WMI_VDEV_PARAM_RTT_11AZ_NTB_MIN_TIME_BW_MEAS, /* 0xBB */ + + /* + * Max time between measurment for 11AZ NTB ranging + * in units of 10 milliseconds + */ + WMI_VDEV_PARAM_RTT_11AZ_NTB_MAX_TIME_BW_MEAS, /* 0xBC */ + + /* + * Max session expiry for 11AZ TB ranging. + * Session expiry value is computed as 2^(Max Session Exp + 8) ms. + */ + WMI_VDEV_PARAM_RTT_11AZ_TB_MAX_SESSION_EXPIRY, /* 0xBD */ + + /* + * WiFi Standard version to be supported. + * Value is from enum WMI_WIFI_STANDARD + */ + WMI_VDEV_PARAM_WIFI_STANDARD_VERSION, /* 0xBE */ + + /* + * Allow to disable TWT on 2G channel + * if corresponding INI is set + */ + WMI_VDEV_PARAM_DISABLE_2G_TWT, /* 0xBF */ /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE === @@ -15116,17 +18275,19 @@ typedef enum { WMI_VDEV_PARAM_MCAST_STEERING, /* 0x800E */ /* - * 0 - XPAN disabled - * 1 - XPAN Lossless audio profile - * 2 - XPAN Gaming profile + * bit 0: 0 - XR SAP profile disabled + * 1 - XR SAP profile enabled + * bit 1: 0 - XPAN profile disabled + * 1 - XPAN profile enabled + * bits 31:2 - reserved */ - WMI_VDEV_PARAM_XPAN_PROFILE, /* 0x800F */ + WMI_VDEV_PARAM_SET_PROFILE, /* 0x800F */ /* * for valid vdev id * for vdev offload stats */ - WMI_VDEV_PARAM_VDEV_STATS_ID_UPDATE, /* 0x8010 */ + WMI_VDEV_PARAM_VDEV_STATS_ID_UPDATE, /* 0x8010 */ /* * Enable or disable Extra LTF capability in Auto rate and @@ -15137,6 +18298,41 @@ typedef enum { */ WMI_VDEV_PARAM_EXTRA_EHT_LTF, /* 0x8011 */ + /* + * Disable the indicated DL and UL scheduler for the VDEV. + * + * This command is not supported in STA mode. + * + * A value of 1 in a given bit position disables the corresponding + * mode, and a value of 0 enables the mode. The WMI_SCHED_MODE_FLAGS + * enum defines the bit positions for each mode. + * + * A single 32 bit value is used to store the following configuration + * bitmap. + * + * This command differs from WMI_VDEV_PARAM_SET_HEMU_MODE and + * WMI_VDEV_PARAM_SET_EHT_MU_MODE in that it is intended for use during + * normal AP operation, and will never cause a VAP restart or other + * capability bit modification. It simply controls the scheduler + * behavior. + * + * bit | sched mode + * --------------- + * 0 | DL MU-MIMO + * 1 | UL MU-MIMO + * 2 | DL OFDMA + * 3 | UL OFDMA + * 4..31 | RESERVED + */ + WMI_VDEV_PARAM_SET_DISABLED_SCHED_MODES, /* 0x8012 */ + + /* + * SAP Power save with TWT vdev param command + * 0 - Disable SAP Power save TWT + * 1 - Enable SAP Power save TWT + */ + WMI_VDEV_PARAM_SET_SAP_PS_WITH_TWT, /* 0x8013 */ + /*=== END VDEV_PARAM_PROTOTYPE SECTION ===*/ } WMI_VDEV_PARAM; @@ -15447,6 +18643,10 @@ typedef struct { A_UINT32 mac_tsf_id; /** ignore mac_tsf_id unless mac_tsf_id_valid is set */ A_UINT32 mac_tsf_id_valid; + /** min_device_tx_pwr_valid = 0 means value is not specified. */ + A_UINT32 min_device_tx_pwr_valid; + /** minimum allowed device Tx power (in dBm) for this connection. */ + A_INT32 min_device_tx_pwr; } wmi_vdev_start_response_event_fixed_param; typedef struct { @@ -15494,6 +18694,7 @@ typedef struct { #define WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN 0x4 /** Invalid regulatory domain in VDEV start */ #define WMI_VDEV_START_RESPONSE_INVALID_BAND 0x5 /** Band unsupported by current hw mode in VDEV start */ #define WMI_VDEV_START_RESPONSE_INVALID_PREFERRED_TX_RX_STREAMS 0x6 /** Invalid preferred tx/rx streams */ +#define WMI_VDEV_START_RESPONSE_INVALID_TX_VAP_CONFIG 0x7 /** Invalid tx_vap config in VDEV start */ /** Beacon processing related command and event structures */ typedef struct { @@ -15585,6 +18786,11 @@ typedef struct { * data is in TLV data[] */ A_UINT32 buf_len; + /** bw: + * Bandwidth to use for the injected frame, of type wmi_channel_width. + * This bw spec shall be ignored unless the bw_valid flag is set. + */ + A_UINT32 bw; /* * The TLVs follows: * A_UINT8 data[]; <-- Variable length data @@ -15953,6 +19159,12 @@ enum wmi_sta_ps_param_uapsd { WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), }; +enum wmi_sta_ps_scheme_cfg { + WMI_STA_PS_OPM_CONSERVATIVE = 0, + WMI_STA_PS_OPM_AGGRESSIVE = 1, + WMI_STA_PS_USER_DEF = 2, +}; + enum wmi_sta_powersave_param { /** * Controls how frames are retrievd from AP while STA is sleeping @@ -15998,9 +19210,10 @@ WMI_STA_PS_PARAM_UAPSD = 4, WMI_STA_PS_PARAM_QPOWER_PSPOLL_COUNT = 5, /** - * Enable QPower + * Enable OPM */ WMI_STA_PS_ENABLE_QPOWER = 6, + WMI_STA_PS_ENABLE_OPM = WMI_STA_PS_ENABLE_QPOWER, /* alias */ /** * Number of TX frames before the entering the Active state @@ -16029,6 +19242,12 @@ WMI_STA_PS_PARAM_MAX_RESET_ITO_COUNT_ON_TIM_NO_TXRX = 10, * in WOW */ WMI_STA_PS_PARAM_ENABLE_PS_OPT_IN_WOW = 11, + +/** + * Speculative interval in ms + */ +WMI_STA_PS_PARAM_SPEC_WAKE_INTERVAL = 12, + }; typedef struct { @@ -16532,6 +19751,7 @@ enum wmi_peer_type { WMI_PEER_TYPE_NAN_DATA = 4, /* Peer is NAN DATA */ WMI_PEER_TYPE_TRANS_BSS = 5, /* For creating BSS peer when connecting with non-transmit AP */ WMI_PEER_TYPE_PASN = 6, /* Peer is used for Pre-Association Security Negotiation */ + WMI_PEER_TYPE_BRIDGE = 7, /* For creating Dummy Peer in case of 4 Link MLO */ WMI_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type is assigned up to 127 */ /* Reserved from 128 - 255 for target internal use.*/ WMI_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */ @@ -17007,7 +20227,8 @@ typedef struct { #define WMI_PEER_CHWIDTH_PUNCTURE_BITMAP_GET_CHWIDTH(value32) WMI_GET_BITS(value32, 0x0, 8) #define WMI_PEER_CHWIDTH_PUNCTURE_BITMAP_GET_PUNCTURE_BMAP(value32) WMI_GET_BITS(value32, 0x8, 16) -/* peer channel bandwidth and puncture_bitmap +/* + * peer channel bandwidth and puncture_bitmap * BIT 0-7 - Peer channel width * This bitfield holds a wmi_channel_width enum value. * BIT 8-23 - Peer Puncture bitmap where each bit indicates whether @@ -17018,6 +20239,12 @@ typedef struct { */ #define WMI_PEER_CHWIDTH_PUNCTURE_20MHZ_BITMAP 0x27 +#define WMI_PEER_SET_TX_POWER 0x28 + +#define WMI_PEER_FT_ROAMING_PEER_UPDATE 0x29 + +#define WMI_PEER_PARAM_DMS_SUPPORT 0x2A + typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ @@ -17229,6 +20456,8 @@ typedef struct { #define WMI_PEER_EXT_320MHZ 0x00000002 /* 320Mhz enabled */ #define WMI_PEER_EXT_DMS_CAPABLE 0x00000004 #define WMI_PEER_EXT_HE_CAPS_6GHZ_VALID 0x00000008 /* param he_caps_6ghz is valid or not */ +#define WMI_PEER_EXT_IS_QUALCOMM_NODE 0x00000010 /* Indicates if the peer connecting is a qualcomm node */ +#define WMI_PEER_EXT_IS_MESH_NODE 0x00000020 /* Indicates if the peer connecting is a mesh node */ #define WMI_PEER_EXT_F_CRIT_PROTO_HINT_ENABLED 0x40000000 /** @@ -17287,8 +20516,14 @@ enum WMI_PEER_STA_TYPE { typedef struct { A_UINT32 tlv_header; /** TLV tag (MITLV_TAG_STRUC_wmi_peer_assoc_mlo_partner_link_params) and len */ - A_UINT32 vdev_id; /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; /** unique id identifying the VDEV, generated by the caller. Set to 0xFFFFFFFF if no vdev is allocated. */ A_UINT32 hw_mld_link_id; /** Unique link id across SOCs, got as part of QMI handshake. */ + wmi_mlo_flags mlo_flags; /** MLO flags */ + A_UINT32 logical_link_index; /** Unique index for links of the mlo. Starts with Zero */ + A_UINT32 ieee_link_id; /*link id in the 802.11 frames*/ + wmi_mac_addr bss_id; + wmi_channel wmi_chan; + wmi_mac_addr self_mac; } wmi_peer_assoc_mlo_partner_link_params; /* This TLV structure used to pass mlo Parameters on peer assoc, only apply for mlo-peers */ @@ -17313,12 +20548,27 @@ typedef struct { A_UINT32 emlsr_trans_delay_us; /** eMLSR padding delay in microseconds */ A_UINT32 emlsr_padding_delay_us; - /** Medium Synchronization Duration in microseconds */ - A_UINT32 msd_dur_us; + union { + /** Medium Synchronization Duration field in units of 32 microseconds */ + A_UINT32 msd_dur_subfield; + /** DEPRECATED - DO NOT USE. + * Medium Synchronization Duration in microseconds */ + A_UINT32 msd_dur_us; + }; /** Medium Synchronization OFDM ED Threshold */ A_UINT32 msd_ofdm_ed_thr; /** Medium Synchronization Max Num of TXOPs */ A_UINT32 msd_max_num_txops; + /** max_num_simultaneous_links: + * The maximum number of affiliated STAs in the non-AP MLD that + * support simultaneous transmission or reception of frames. + */ + A_UINT32 max_num_simultaneous_links; + /** NSTR indication bitmap received in assoc req */ + A_UINT32 nstr_indication_bitmap; + + /** max num of active links recommended by AP or applications */ + A_UINT32 recommended_max_num_simultaneous_links; } wmi_peer_assoc_mlo_params; typedef struct { @@ -17531,6 +20781,8 @@ typedef struct { /* deprecated but maintained as aliases: old names containing typo */ #define WMI_CHAN_InFO_START_RESP WMI_CHAN_INFO_START_RESP #define WMI_CHAN_InFO_END_RESP WMI_CHAN_INFO_END_RESP +/* end deprecated */ +#define WMI_CHAN_INFO_ENTRY_RESP 2 typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_remove_wds_entry_cmd_fixed_param */ @@ -17603,8 +20855,58 @@ typedef struct { * If per_chain_noise_floor value is 0 then it should be ignored. */ A_UINT32 per_chain_noise_floor[WMI_MAX_CHAINS]; + +/** + * Following this structure is the optional TLV: + * struct wmi_scan_blanking_params_info[0/1]; + * struct wmi_cca_busy_subband_info[]; + * Reporting subband CCA busy info in host requested manner. + */ } wmi_chan_info_event_fixed_param; +typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_cca_busy_subband_info */ + A_UINT32 tlv_header; + /** rx clear count */ + A_UINT32 rx_clear_count; +} wmi_cca_busy_subband_info; + +/** + * The below structure contains parameters related to the scan radio + * blanking feature + */ +typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_blanking_params_info */ + A_UINT32 tlv_header; + /* scan_radio_blanking_duration: + * Cumulative scan disabled duration which indicates the total time in + * micro seconds where rx blanking was enabled on the scan radio due to + * simultaneous transmissions on the same band in the serving radio. + */ + A_UINT32 scan_radio_blanking_duration; + /* scan_radio_blanking_count: + * Count of the number of times rx blanking was enabled on the scan radio + * due to simultaneous transmissions on the same band in the serving radio. + */ + A_UINT32 scan_radio_blanking_count; +} wmi_scan_blanking_params_info; + +typedef enum { + /* Blanking feature will be disabled */ + WMI_SCAN_BLANKING_DISABLED = 0, + + /* Blanking enabled only on current operating band */ + WMI_SCAN_BLANKING_ENABLED, + + /* + * Blanking enabled on both 5GHz and 6GHz bands when scan radio + * home channel is on either 5GHz or 6GHz bands + */ + WMI_SCAN_BLANKING_ENABLED_NO_ISOLATION, + + WMI_SCAN_BLANKING_MAX, +} WMI_SCAN_BLANKING_MODE; + /** * The below three structures are the params used for converting RSSI * from dB to dBm units. @@ -18523,6 +21825,17 @@ typedef struct { /* Scoring for security mode */ A_INT32 security_weightage_pcnt; wmi_roam_cnd_security_scoring security_scoring; + /* mlo_etp_weightage_pcnt: + * Give etp weightage to candidate based on MLO support. + * In host INI configuration, it will give boost(+) or reduction(-) + * percentage value and host will deliver actual weighted number + * based on 100. For example: + * If percentage value in INI is 20, then host will give 120 (100 * 1.2) + * as mlo_etp_weightage_pcnt. + * If percentage value in INI is -20, then host will give 80 (100 * 0.8) + * as mlo_etp_weightage_pcnt. + */ + A_UINT32 mlo_etp_weightage_pcnt; } wmi_roam_cnd_scoring_param; typedef struct { @@ -19009,6 +22322,12 @@ typedef struct { A_UINT32 timestamp; /* Original timeout value in milli seconds when AP added to BL */ A_UINT32 original_timeout; + /* + * If disallow_linkid_bitmap is not 0, then means current entity + * is for MLD AP and bssid field is standing for MLD address. + * If all links for MLD AP is disallow, then the value shall be 0xffffffff + */ + A_UINT32 disallow_linkid_bitmap; } wmi_roam_blacklist_with_timeout_tlv_param; /** WMI_ROAM_BLACKLIST_EVENT: generated whenever STA needs to move AP to blacklist for a particluar time @@ -19982,6 +23301,10 @@ typedef enum wake_reason_e { WOW_REASON_SCHED_PM_TERMINATED, /* XGAP entry/exit response */ WOW_REASON_XGAP, + /* COEX channel avoid event */ + WOW_REASON_COEX_CHAVD, + /* vdev repurpose request event */ + WOW_REASON_VDEV_REPURPOSE, /* add new WOW_REASON_ defs before this line */ WOW_REASON_MAX, @@ -20038,6 +23361,48 @@ typedef enum { WMI_WOW_RESUME_FLAG_TX_DATA = 0x00000001, /* TX data pending to be sent in resume */ } WMI_WOW_RESUME_FLAG_ENUM; +/* wow nack reason codes */ +typedef enum { + /* WoW error due to unnkown reason */ + WMI_WOW_NON_ACK_REASON_UNKNOWN = 0, + + /* WoW error due to TX failure */ + WMI_WOW_NON_ACK_REASON_TX = 1, + + /* WoW error due to some data blocked */ + WMI_WOW_NON_ACK_REASON_IS_BLOCK = 2, + + /* WoW error in WFA mode */ + WMI_WOW_NON_ACK_REASON_NOT_ALLOW = 3, + + /* WoW error mac operation fail */ + WMI_WOW_NON_ACK_REASON_HW_FAIL = 4, + + /* WoW error due to timeout */ + WMI_WOW_NON_ACK_REASON_TIMEOUT = 5, + + /* WoW error due to RTT or CFR capture active */ + WMI_WOW_NON_ACK_REASON_RTT_DMA = 6, + + /* WoW error due to roam module holding lock */ + WMI_WOW_NON_ACK_REASON_ROAM = 7, + + /* WoW error remote peer not sleeping */ + WMI_WOW_NON_ACK_REASON_PEER_ACTIVE = 8, + + /* WoW error due to WoW entry defer failed */ + WMI_WOW_NON_ACK_REASON_DEFER_FAILURE = 9, + + /* WoW error due to WoW entry defer timeout */ + WMI_WOW_NON_ACK_REASON_DEFER_TIMEOUT = 10, + + /* WoW error due to FATAL event */ + WMI_WOW_NON_ACK_REASON_FATAL_EVENT = 11, + + /* WoW error if close to TBTT */ + WMI_WOW_NON_ACK_REASON_CLOSE_TO_TBTT = 12, +} WMI_WOW_NACK_STATUS; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wow_hostwakeup_from_sleep_cmd_fixed_param */ /* reserved0: @@ -21340,6 +24705,13 @@ typedef struct { A_UINT32 key_cipher; A_UINT8 pn[WMI_MAX_PN_LEN]; A_UINT8 key_buff[WMI_MAX_KEY_LEN]; + /* + * When link_id is 0xf, this field will be MLD address. + * Otherwise, it will be bssid which specified with link_id. + */ + wmi_mac_addr mac_addr; + A_UINT32 key_len; /* number of valid bytes within key_buff */ + A_UINT32 key_flags; } wmi_roam_ml_key_material_param; typedef struct { @@ -21578,6 +24950,19 @@ typedef enum */ WMI_VENDOR_OUI_ACTION_DISABLE_DYNAMIC_QOS_NULL_TX_RATE = 10, + /* + * Enable CTS2SELF with QoS null frame if specific vendor OUI + * received in beacon. + */ + WMI_VENDOR_OUI_ACTION_ENABLE_CTS2SELF_WITH_QOS_NULL = 11, + + /* + * Send SMPS frame following OMN frame on VHT conncection if specific + * vendor OUI received in beacon. + */ + WMI_VENDOR_OUI_ACTION_SEND_SMPS_FRAME_WITH_OMN = 12, + + /* Add any action before this line */ WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID } wmi_vendor_oui_action_id; @@ -21872,12 +25257,37 @@ typedef struct { A_UINT32 set; /* Set the GPIO pin*/ } wmi_gpio_output_cmd_fixed_param; +/* WMI_GPIO_STATE_REQ_CMDID */ +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param */ + A_UINT32 gpio_num; /* GPIO number to get state */ +} wmi_gpio_state_req_cmd_fixed_param; + /* WMI_GPIO_INPUT_EVENTID */ typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param */ A_UINT32 gpio_num; /* GPIO number which changed state */ } wmi_gpio_input_event_fixed_param; +typedef enum { + /** + * The following wmi_gpio_state_type is mutually exclusive. + * 0: gpio_invalid_state + * 1: gpio_state is LO + * 2: gpio_state is HIGH + */ + WMI_GPIO_STATE_INVALID, /* GPIO state is invalid. */ + WMI_GPIO_STATE_LOW, /* GPIO state is low. */ + WMI_GPIO_STATE_HIGH, /* GPIO state is high. */ +} WMI_GPIO_STATE_TYPE; + +/* WMI_GPIO_STATE_RES_EVENTID */ +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param */ + A_UINT32 gpio_num; /* GPIO number */ + A_UINT32 gpio_state; /* state of GPIO pin defined in WMI_GPIO_STATE_TYPE 0 invalid 1 - LO, 2 -HI*/ +} wmi_gpio_state_res_event_fixed_param; + /* WMI_ANT_CONTROLLER_CMDID */ typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ant_controller_cmd_fixed_param */ @@ -22172,6 +25582,30 @@ typedef struct { A_INT32 sidx; /* segment index (where was the radar within the channel) */ } wmi_pdev_dfs_radar_detection_event_fixed_param; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_RADAR_FLAGS */ + /* + * Bit 0: + * 0 - need check sub channel marking + * 1 - full bandwidth need put to NOL + * Refer to WMI_RADAR_FLAGS_FULL_BW_NOL_GET and _SET macros + * [1:31] reserved + */ + A_UINT32 flags; +} WMI_RADAR_FLAGS; + +#define WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS 0 +#define WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS 1 + +#define WMI_RADAR_FLAGS_FULL_BW_NOL_GET(flag) \ + WMI_GET_BITS(flag, \ + WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \ + WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS) +#define WMI_RADAR_FLAGS_FULL_BW_NOL_SET(flag, val) \ + WMI_GET_BITS(flag, \ + WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \ + WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS, val) + typedef enum { OCAC_COMPLETE = 0, OCAC_ABORT, @@ -22442,7 +25876,8 @@ typedef struct { enum wmi_tdls_offchan_mode { WMI_TDLS_ENABLE_OFFCHANNEL, - WMI_TDLS_DISABLE_OFFCHANNEL + WMI_TDLS_DISABLE_OFFCHANNEL, /* passive offchannel disable */ + WMI_TDLS_ACTIVE_DISABLE_OFFCHANNEL, }; typedef struct { @@ -22464,6 +25899,9 @@ typedef struct { A_UINT32 offchan_oper_class; /* off channel frequency in MHz */ A_UINT32 offchan_freq; +/** This fixed_param TLV is followed by the below additional TLVs: + * - wmi_channel peer_chan_info[]: optional per-peer chan_info + */ } wmi_tdls_set_offchan_mode_cmd_fixed_param; @@ -24318,6 +27756,42 @@ typedef struct { */ } wmi_nan_cmd_param; +typedef enum { + WMI_NAN_VENDOR1_REQ1 = 1, +} WMI_NAN_OEM_DATA_TYPE; + +typedef struct { + /** oem_data_type: + * Indicate what kind of OEM-specific data is present in the + * oem_data_buffer[]. + * Possible values are listed in the enum WMI_NAN_OEM_DATA_TYPE. + */ + A_UINT32 oem_data_type; + /** oem_data_len: + * Actual length in bytes of the OEM-specific data within the + * oem_data_buffer[]. + * Note that it is possible for a single message to contain multiple + * OEM opaque data blobs. In such cases, the oem_data_len field of + * nan_oem_data_hdr[0] not only specifies the size of the first such + * opaque blob, but furthermore specifies the offset in oem_data_buffer[] + * where the second opaque blob begins. + */ + A_UINT32 oem_data_len; +} wmi_nan_oem_data_hdr; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_oem_data_cmd_fixed_param */ + + /* Following this structure are the below TLVs: + * - wmi_nan_oem_data_hdr nan_oem_data_hdr[]; + * This TLV explains the type and size of the one or more OEM NAN + * opaque data blobs carried in this message. + * - A_UINT8 nan_oem_data_buffer[]; + * This TLV holds the contents of the one or more OEM NAN opaque data + * blobs carried in this message. + */ +} wmi_nan_oem_data_cmd_fixed_param; + #define WMI_NAN_GET_RANGING_INITIATOR_ROLE(flag) WMI_GET_BITS(flag, 0, 1) #define WMI_NAN_SET_RANGING_INITIATOR_ROLE(flag, val) WMI_SET_BITS(flag, 0, 1, val) #define WMI_NAN_GET_RANGING_RESPONDER_ROLE(flag) WMI_GET_BITS(flag, 1, 1) @@ -24350,6 +27824,19 @@ typedef struct { */ } wmi_nan_event_hdr; +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_oem_data_event_fixed_param */ + + /* Following this structure are the below TLVs: + * - wmi_nan_oem_data_hdr nan_oem_data_hdr[]; + * This TLV explains the type and size of the one or more OEM NAN + * opaque data blobs carried in this message. + * - A_UINT8 nan_oem_data_buffer[]; + * This TLV holds the contents of the one or more OEM NAN opaque data + * blobs carried in this message. + */ +} wmi_nan_oem_data_event_fixed_param; + typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_event_info */ A_UINT32 mac_id; /* MAC ID associated with NAN primary discovery channel; Valid only for NAN enable resp message identified by NAN_MSG_ID_ENABLE_RSP */ @@ -24430,6 +27917,8 @@ typedef struct { A_UINT32 tlv_header; /** Maximum number of ndp sessions supported by the Firmware */ A_UINT32 max_ndp_sessions; + /** Maximum number of nan pairing sessions supported by the Firmware */ + A_UINT32 max_pairing_sessions; } wmi_nan_capabilities; /** NAN DATA CMD's */ @@ -24534,6 +28023,10 @@ typedef struct { A_UINT32 nan_passphrase_len; /** Actual number of bytes in TLV nan_servicename */ A_UINT32 nan_servicename_len; + /** NAN Cipher Suite Capability field */ + A_UINT32 nan_csid_cap; + /** GTK protection is required for the NDP */ + A_UINT32 nan_gtk_required; /** * TLV (tag length value) parameters follow the ndp_initiator_req * structure. The TLV's are: @@ -24579,6 +28072,10 @@ typedef struct { A_UINT32 nan_passphrase_len; /** Actual number of bytes in TLV nan_servicename */ A_UINT32 nan_servicename_len; + /** NAN Cipher Suite Capability field */ + A_UINT32 nan_csid_cap; + /** GTK protection is required for the NDP */ + A_UINT32 nan_gtk_required; /** * TLV (tag length value) parameters follow the ndp_responder_req * structure. The TLV's are: @@ -24625,6 +28122,10 @@ typedef struct { A_UINT32 tlv_header; /** NDP instance id */ A_UINT32 ndp_instance_id; + /** vdev_id valid flag */ + A_UINT32 vdev_id_valid; + /** vdev id */ + A_UINT32 vdev_id; } wmi_ndp_end_req_PROTOTYPE; #define wmi_ndp_end_req wmi_ndp_end_req_PROTOTYPE @@ -24845,6 +28346,10 @@ typedef struct { wmi_mac_addr self_ndi_mac_addr; /** Number of bytes in TLV service_id */ A_UINT32 service_id_len; + /** NAN Cipher Suite Capability field */ + A_UINT32 nan_csid_cap; + /** GTK protection is required for the NDP */ + A_UINT32 nan_gtk_required; /** * TLV (tag length value) parameters follow the ndp_indication * structure. The TLV's are: @@ -25229,10 +28734,15 @@ typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_key_material_ext */ A_UINT32 tlv_header; /* - * key_buffer contains kck,kck2,kek,kek2,replay counter, in order - * The split between kck vs. kek should be known to host based on akmp. + * key_buffer contains kck,kck2,kek,kek2,replay counter, in order. + * If both the below kck_len and kek_len fields are 0x0, the split + * between kck vs. kek should be inferred based on akmp. */ A_UINT8 key_buffer[GTK_OFFLOAD_KEK_EXTENDED_BYTES+GTK_OFFLOAD_KCK_EXTENDED_BYTES+GTK_REPLAY_COUNTER_BYTES]; + /* length of kck in key_buffer */ + A_UINT32 kck_len; + /* length of kek in key_buffer */ + A_UINT32 kek_len; } wmi_key_material_ext; typedef struct { @@ -25419,12 +28929,24 @@ typedef struct { */ } wmi_stats_ext_event_fixed_param; +typedef enum { + /** Default: no replay required. */ + WMI_PEER_DELETE_NO_REPLAY = 0, + /** + * Replay requested due to UMAC hang during Peer delete. + * Replay done by Host SW after MLO UMAC SSR recovered the UMAC. + */ + WMI_PEER_DELETE_REPLAY_FOR_UMAC, +} WMI_PEER_DELETE_REPLAY_T; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ A_UINT32 vdev_id; /** peer MAC address */ wmi_mac_addr peer_macaddr; + /** WMI_PEER_DELETE_REPLAY_T */ + A_UINT32 replay_type; } wmi_peer_delete_resp_event_fixed_param; typedef struct { @@ -25439,6 +28961,8 @@ typedef struct { * 2 - EFAILED; Delete all peer failed */ A_UINT32 status; + /** WMI_PEER_DELETE_REPLAY_T */ + A_UINT32 replay_type; } wmi_vdev_delete_all_peer_resp_event_fixed_param; typedef struct { @@ -28951,6 +32475,42 @@ typedef struct { A_UINT32 antenna_series; } wmi_peer_smart_ant_set_tx_antenna_series; +#define WMI_PER_VALID_BIT_POS 0 +#define WMI_PER_VALID_NUM_BITS 1 + +#define WMI_GET_PER_VALID(per_threshold) \ + WMI_GET_BITS(per_threshold, WMI_PER_VALID_BIT_POS, WMI_PER_VALID_NUM_BITS) + +#define WMI_PER_VALID_SET(per_threshold, value) \ + WMI_SET_BITS(per_threshold, WMI_PER_VALID_BIT_POS, WMI_PER_VALID_NUM_BITS, value) + +#define WMI_PER_THRESHOLD_BIT_POS 1 +#define WMI_PER_THRESHOLD_NUM_BITS 8 + +#define WMI_GET_PER_THRESHOLD(per_threshold) \ + WMI_GET_BITS(per_threshold, WMI_PER_THRESHOLD_BIT_POS, WMI_PER_THRESHOLD_NUM_BITS) + +#define WMI_PER_THRESHOLD_SET(per_threshold, value) \ + WMI_SET_BITS(per_threshold, WMI_PER_THRESHOLD_BIT_POS, WMI_PER_THRESHOLD_NUM_BITS, value) + +#define WMI_PER_MIN_TX_PKTS_BIT_POS 9 +#define WMI_PER_MIN_TX_PKTS_NUM_BITS 16 + +#define WMI_GET_PER_MIN_TX_PKTS(per_threshold) \ + WMI_GET_BITS(per_threshold, WMI_PER_MIN_TX_PKTS_BIT_POS, WMI_PER_MIN_TX_PKTS_NUM_BITS) + +#define WMI_PER_MIN_TX_PKTS_SET(per_threshold, value) \ + WMI_SET_BITS(per_threshold, WMI_PER_MIN_TX_PKTS_BIT_POS, WMI_PER_MIN_TX_PKTS_NUM_BITS, value) + +#define WMI_RATE_SERIES_320_BIT_POS 0 +#define WMI_RATE_SERIES_320_NUM_BITS 16 + +#define WMI_GET_RATE_SERIES_320(train_rate_series_ext) \ + WMI_GET_BITS(train_rate_series_ext, WMI_RATE_SERIES_320_BIT_POS, WMI_RATE_SERIES_320_NUM_BITS) + +#define WMI_SET_RATE_SERIES_320(train_rate_series_ext) \ + WMI_SET_BITS(train_rate_series_ext, WMI_RATE_SERIES_320_BIT_POS, WMI_RATE_SERIES_320_NUM_BITS, value) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_param */ /* rate array */ @@ -28972,6 +32532,11 @@ typedef struct { A_UINT32 rc_flags; /* rate array -- continued */ A_UINT32 train_rate_series_hi; /* Higher 32 bits of rate array */ + /* train_rate_series_ext: + * 15:0 - 320Mhz rate + * 31:16 - Reserved + */ + A_UINT32 train_rate_series_ext; /* For 320Mhz and Reserved for other */ } wmi_peer_smart_ant_set_train_antenna_param; typedef struct { @@ -28982,10 +32547,19 @@ typedef struct { wmi_mac_addr peer_macaddr; /* num packets; 0-stop training */ A_UINT32 num_pkts; - /* - * Following this structure is the TLV: - * wmi_peer_smart_ant_set_train_antenna_param - */ + /* per_threshold: + * bits | interpretation + * ------+-------------------------- + * 0 | PER Threshold is valid + * 1:8 | Per Threshold + * 9:24 | min_tx_pkts Minimum number of pkts need to be checked + * 25:31 | Reserved + */ + A_UINT32 per_threshold; +/* + * Following this structure is the TLV: + * wmi_peer_smart_ant_set_train_antenna_param + */ } wmi_peer_smart_ant_set_train_antenna_cmd_fixed_param; typedef struct { @@ -29450,12 +33024,100 @@ typedef struct { A_UINT32 pdev_id; } wmi_atf_peer_info; +#define WMI_ATF_PEER_UNITS_BIT_POS 0 +#define WMI_ATF_PEER_UNITS_NUM_BITS 16 + +#define WMI_ATF_GET_PEER_UNITS(atf_peer_info) \ + WMI_GET_BITS(atf_peer_info,WMI_ATF_PEER_UNITS_BIT_POS,WMI_ATF_PEER_UNITS_NUM_BITS) + +#define WMI_ATF_SET_PEER_UNITS(atf_peer_info,val) \ + WMI_SET_BITS(atf_peer_info,WMI_ATF_PEER_UNITS_BIT_POS,WMI_ATF_PEER_UNITS_NUM_BITS, val) + +#define WMI_ATF_GROUP_ID_BIT_POS 16 +#define WMI_ATF_GROUP_ID_NUM_BITS 8 + +#define WMI_ATF_GET_GROUP_ID(atf_peer_info) \ + WMI_GET_BITS(atf_peer_info,WMI_ATF_GROUP_ID_BIT_POS,WMI_ATF_GROUP_ID_NUM_BITS) + +#define WMI_ATF_SET_GROUP_ID(atf_peer_info,val) \ + WMI_SET_BITS(atf_peer_info,WMI_ATF_GROUP_ID_BIT_POS,WMI_ATF_GROUP_ID_NUM_BITS, val) + +#define WMI_ATF_EXPLICIT_PEER_FLAG_BIT_POS 24 +#define WMI_ATF_EXPLICIT_PEER_FLAG_NUM_BITS 1 + +#define WMI_ATF_GET_EXPLICIT_PEER_FLAG(atf_peer_info) \ + WMI_GET_BITS(atf_peer_info,WMI_ATF_EXPLICIT_PEER_FLAG_BIT_POS,WMI_ATF_EXPLICIT_PEER_FLAG_NUM_BITS) + +#define WMI_ATF_SET_EXPLICIT_PEER_FLAG(atf_peer_info,val) \ + WMI_SET_BITS(atf_peer_info,WMI_ATF_EXPLICIT_PEER_FLAG_BIT_POS,WMI_ATF_EXPLICIT_PEER_FLAG_NUM_BITS, val) + +typedef struct { + /* The new structure is an optimized version of wmi_atf_peer_info & wmi_atf_peer_ext_info combined */ + A_UINT32 tlv_header; + wmi_mac_addr peer_macaddr; + /* atf_peer_info + * Bits 0-15 - atf_units (based on 1 part in 1000 (per mille)) + * Bits 16-23 - atf_groupid + * Bit 24 - Configured Peer Indication (0/1), this bit would be set by + * host to indicate that the peer has airtime % configured + * explicitly by user + * Bits 25-31 - Reserved (Shall be zero) + */ + A_UINT32 atf_peer_info; +} wmi_atf_peer_info_v2; + +#define WMI_ATF_PEER_FULL_UPDATE_BIT_POS 0 +#define WMI_ATF_PEER_FULL_UPDATE_NUM_BITS 1 + +#define WMI_ATF_GET_PEER_FULL_UPDATE(atf_flags) \ + WMI_GET_BITS(atf_flags,WMI_ATF_PEER_FULL_UPDATE_BIT_POS,WMI_ATF_PEER_FULL_UPDATE_NUM_BITS) + +#define WMI_ATF_SET_PEER_FULL_UPDATE(atf_flags,val) \ + WMI_SET_BITS(atf_flags,WMI_ATF_PEER_FULL_UPDATE_BIT_POS,WMI_ATF_PEER_FULL_UPDATE_NUM_BITS,val) + +#define WMI_ATF_PEER_PENDING_WMI_CMDS_BIT_POS 1 +#define WMI_ATF_PEER_PENDING_WMI_CMDS_NUM_BITS 1 + +#define WMI_ATF_GET_PEER_PENDING_WMI_CMDS(atf_flags) \ + WMI_GET_BITS(atf_flags,WMI_ATF_PEER_PENDING_WMI_CMDS_BIT_POS, WMI_ATF_PEER_PENDING_WMI_CMDS_NUM_BITS) + +#define WMI_ATF_SET_PEER_PENDING_WMI_CMDS(atf_flags,val) \ + WMI_SET_BITS(atf_flags,WMI_ATF_PEER_PENDING_WMI_CMDS_BIT_POS, WMI_ATF_PEER_PENDING_WMI_CMDS_NUM_BITS, val) + +#define WMI_ATF_PEER_PDEV_ID_VALID_BIT_POS 2 +#define WMI_ATF_PEER_PDEV_ID_VALID_NUM_BITS 1 + +#define WMI_ATF_GET_PEER_PDEV_ID_VALID(atf_flags) \ + WMI_GET_BITS(atf_flags,WMI_ATF_PEER_PDEV_ID_VALID_BIT_POS, WMI_ATF_PEER_PDEV_ID_VALID_NUM_BITS) + +#define WMI_ATF_SET_PEER_PDEV_ID_VALID(atf_flags,val) \ + WMI_SET_BITS(atf_flags,WMI_ATF_PEER_PDEV_ID_VALID_BIT_POS, WMI_ATF_PEER_PDEV_ID_VALID_NUM_BITS, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_atf_request_fixed_param */ A_UINT32 num_peers; - /* - * Following this structure is the TLV: - * struct wmi_atf_peer_info peer_info[num_peers]; + A_UINT32 pdev_id; + /* atf_flags + * Bit 0 - full or partial update; + * full update - + * indicates that this is done for all the connected peers + * partial update - + * indicates update for only the newly connected peers + * (whenever some peers gets connected/disconnected) + * Bit 1 - indicates whether there are more iterations of WMI command + * incoming after the current set of cmds + * Example : If there are 500 peers present and tlv can accomodate + * only 50 peers at a time, then this will be set for all the + * instances of the WMI commands except the last one. + * Bit 2 - indicates if pdev_id is valid or not + * Bits 3-31 - Reserved (Shall be zero) + */ + A_UINT32 atf_flags; + /* + * Following this structure is one of the following TLVs + * (only one of them will have valid data in a particular message) + * - struct wmi_atf_peer_info peer_info[num_peers]; + * - struct wmi_atf_peer_info_v2 peer_info_v2[num_peers]; */ } wmi_peer_atf_request_fixed_param; @@ -29488,12 +33150,69 @@ typedef struct { A_UINT32 atf_group_flags; } wmi_atf_group_info; +#define WMI_ATF_GROUP_NUM_EXPLICIT_PEERS_BIT_POS 0 +#define WMI_ATF_GROUP_NUM_EXPLICIT_PEERS_NUM_BITS 16 + +#define WMI_ATF_GROUP_GET_NUM_EXPLICIT_PEERS(atf_total_num_peers) \ + WMI_GET_BITS(atf_total_num_peers, WMI_ATF_GROUP_NUM_EXPLICIT_PEERS_BIT_POS, WMI_ATF_GROUP_NUM_EXPLICIT_PEERS_NUM_BITS) + +#define WMI_ATF_GROUP_SET_NUM_EXPLICIT_PEERS(atf_total_num_peers, val) \ + WMI_SET_BITS(atf_total_num_peers, WMI_ATF_GROUP_NUM_EXPLICIT_PEERS_BIT_POS, WMI_ATF_GROUP_NUM_EXPLICIT_PEERS_NUM_BITS, val) + +#define WMI_ATF_GROUP_NUM_IMPLICIT_PEERS_BIT_POS 16 +#define WMI_ATF_GROUP_NUM_IMPLICIT_PEERS_NUM_BITS 16 + +#define WMI_ATF_GROUP_GET_NUM_IMPLICIT_PEERS(atf_total_num_peers) \ + WMI_GET_BITS(atf_total_num_peers, WMI_ATF_GROUP_NUM_IMPLICIT_PEERS_BIT_POS, WMI_ATF_GROUP_NUM_IMPLICIT_PEERS_NUM_BITS) + +#define WMI_ATF_GROUP_SET_NUM_IMPLICIT_PEERS(atf_total_num_peers, val) \ + WMI_SET_BITS(atf_total_num_peers, WMI_ATF_GROUP_NUM_IMPLICIT_PEERS_BIT_POS, WMI_ATF_GROUP_NUM_IMPLICIT_PEERS_NUM_BITS, val) + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_atf_group_info_v2 */ + A_UINT32 tlv_header; + A_UINT32 atf_group_id; /* ID of the Air Time Management group */ + /* atf_group_units + * Fraction of air time allowed for the group, in per mille units + * (from 0-1000). + * For example, to indicate that the group can use 12.3% of the air time, + * the atf_group_units setting would be 123. + */ + A_UINT32 atf_group_units; + /* atf_group_flags + * Bits 0-3 - Group Schedule Policy (Fair/Strict/Fair with upper bound) + * Refer to WMI_ATF_SSID_ definitions + * Bit 4-31 - Reserved (Shall be zero) + */ + A_UINT32 atf_group_flags; + /* atf_total_num_peers + * + * Bits 0-15 - total number of explicit peers + * Bits 16-31 - total number of implicit peers + * An explicit peer has an ATF % configured by the user. + * An implicit peer has an ATF % = + * (Group_ATF_percent - Total_Explicit_Peers_ATF_Percent) / + * number of implicit peers + * This computation can be done in FW based on atf_total_num_peers. + */ + A_UINT32 atf_total_num_peers; + /* atf_total_implicit_peer_units + * + * Air time allocated for all the implicit peers + * (from 0-1000, in per mille units) + */ + A_UINT32 atf_total_implicit_peer_units; +} wmi_atf_group_info_v2; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_atf_ssid_grp_request_fixed_param */ A_UINT32 pdev_id; /* - * Following this structure is the TLV: - * struct wmi_atf_group_info group_info[]; + * Following this structure is the one of the following TLVs + * (only one of them will have valid data in a particular message) + * - struct wmi_atf_group_info group_info[]; + * - struct wmi_atf_group_info_v2 group_info[]; */ } wmi_atf_ssid_grp_request_fixed_param; @@ -29695,6 +33414,34 @@ typedef struct { #define WMI_LATENCY_SET_MSDUQ_ID(latency_tid_info,val) \ WMI_SET_BITS(latency_tid_info, WMI_LATENCY_MSDUQ_ID_BIT_POS, WMI_LATENCY_MSDUQ_ID_NUM_BITS, val) +#define WMI_LATENCY_DISABLE_UL_OFDMA_BIT_POS 18 +#define WMI_LATENCY_DISABLE_UL_OFDMA_NUM_BITS 1 + +#define WMI_LATENCY_GET_DISABLE_UL_OFDMA(latency_tid_info) \ + WMI_GET_BITS(latency_tid_info, WMI_LATENCY_DISABLE_UL_OFDMA_BIT_POS, WMI_LATENCY_DISABLE_UL_OFDMA_NUM_BITS) + +#define WMI_LATENCY_SET_DISABLE_UL_OFDMA(latency_tid_info,val) \ + WMI_SET_BITS(latency_tid_info, WMI_LATENCY_DISABLE_UL_OFDMA_BIT_POS, WMI_LATENCY_DISABLE_UL_OFDMA_NUM_BITS, val) + +#define WMI_LATENCY_DISABLE_UL_MU_MIMO_BIT_POS 19 +#define WMI_LATENCY_DISABLE_UL_MU_MIMO_NUM_BITS 1 + +#define WMI_LATENCY_GET_DISABLE_UL_MU_MIMO(latency_tid_info) \ + WMI_GET_BITS(latency_tid_info, WMI_LATENCY_DISABLE_UL_MU_MIMO_BIT_POS, WMI_LATENCY_DISABLE_UL_MU_MIMO_NUM_BITS) + +#define WMI_LATENCY_SET_DISABLE_UL_MU_MIMO(latency_tid_info,val) \ + WMI_SET_BITS(latency_tid_info, WMI_LATENCY_DISABLE_UL_MU_MIMO_BIT_POS, WMI_LATENCY_DISABLE_UL_MU_MIMO_NUM_BITS, val) + +#define WMI_LATENCY_SAWF_UL_PARAMS_FLAG_POS 20 +#define WMI_LATENCY_SAWF_UL_PARAMS_FLAG_NUM_BITS 1 + +#define WMI_LATENCY_GET_SAWF_UL_PARAMS_BIT(latency_tid_info) \ + WMI_GET_BITS(latency_tid_info, WMI_LATENCY_SAWF_UL_PARAMS_FLAG_POS, WMI_LATENCY_SAWF_UL_PARAMS_FLAG_NUM_BITS) + +#define WMI_LATENCY_SET_SAWF_UL_PARAMS_BIT(latency_tid_info, val) \ + WMI_SET_BITS(latency_tid_info, WMI_LATENCY_SAWF_UL_PARAMS_FLAG_POS, WMI_LATENCY_SAWF_UL_PARAMS_FLAG_NUM_BITS, val) + + typedef struct { /** TLV tag and len; tag equals * WMITLV_TAG_STRUC_wmi_tid_latency_info @@ -29738,7 +33485,14 @@ typedef struct { */ A_UINT32 min_tput; /* latency_tid_info - * Bits 18-31 - Reserved (Shall be zero) + * Bits 21-31 - Reserved (Shall be zero) + * Bit 20 - Flag to indicate SAWF UL params (and not mesh latency) + * Bit 19 - Disable UL MU-MIMO. If set, UL MU-MIMO is disabled + * for the specified AC. Note that TID level control is + * not possible for UL MU-MIMO (the granularity is AC). + * Bit 18 - Disable UL OFDMA. If set, UL OFDMA is disabled for + * the specified AC. Note that TID level control is not + * possible for UL OFDMA (the granularity is AC). * Bits 14-17 - MSDU queue flow id within the TID for configuring * latency info per MSDU flow queue * Bit 12-13 - burst size sum. Bit to indicate whether to add or @@ -29899,9 +33653,11 @@ typedef struct { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_mcs_rate_info */ - A_UINT32 ratecode_20; /* Rate code for 20MHz BW */ - A_UINT32 ratecode_40; /* Rate code for 40MHz BW */ - A_UINT32 ratecode_80; /* Rate code for 80MHz BW */ + A_UINT32 ratecode_20; /* Rate code for 20MHz BW */ + A_UINT32 ratecode_40; /* Rate code for 40MHz BW */ + A_UINT32 ratecode_80; /* Rate code for 80MHz BW */ + A_UINT32 ratecode_160; /* Rate code for 160MHz BW */ + A_UINT32 ratecode_320; /* Rate code for 320MHz BW */ } wmi_peer_mcs_rate_info; typedef struct { @@ -29910,6 +33666,7 @@ typedef struct { A_UINT32 ratecount; /* Max Rate count for each mode */ A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ A_UINT32 pdev_id; /* ID of the pdev this peer belongs to */ + A_UINT32 ratecount_ext; /* Max Rate count for 160, 320MHz */ /* * Following this structure are the TLV: * struct wmi_peer_cck_ofdm_rate_info; @@ -30782,6 +34539,26 @@ typedef enum wmi_coex_config_type { * 1 to place more emphasis on WLAN performance */ WMI_COEX_CONFIG_LE_SCAN_POLICY = 48, + /* WMI_COEX_CONFIG_BT_RX_PER_THRESHOLD + * config BT RX PER threshold + */ + WMI_COEX_CONFIG_BT_RX_PER_THRESHOLD = 49, + /* WMI_COEX_SET_TRAFFIC_SHAPING_MODE + * arg1: 0 (WMI_COEX_TRAFFIC_SHAPING_MODE_DISABLED) + * Disable coex policies and set fixed arbitration config. + * 1 (WMI_COEX_TRAFFIC_SHAPING_MODE_ENABLED) + * Enable all coex policies. + */ + WMI_COEX_SET_TRAFFIC_SHAPING_MODE = 50, + /* WMI_COEX_CONFIG_ENABLE_CONT_INFO + * enable contention info log + * arg1: + * 0: disable both cont/sched log + * 1: enable cont log + * 2: enable sched log + * 3: enable both cont and sched log + */ + WMI_COEX_CONFIG_ENABLE_CONT_INFO = 51, } WMI_COEX_CONFIG_TYPE; typedef struct { @@ -30802,6 +34579,11 @@ typedef enum wmi_coex_dbam_mode_type { WMI_COEX_DBAM_FORCED = 2, } WMI_COEX_DBAM_MODE_TYPE; +typedef enum { + WMI_COEX_TRAFFIC_SHAPING_MODE_DISABLED = 0, + WMI_COEX_TRAFFIC_SHAPING_MODE_ENABLED = 1, +} WMI_COEX_TRAFFIC_SHAPING_MODE; + typedef struct { A_UINT32 tlv_header; A_UINT32 vdev_id; @@ -30993,6 +34775,11 @@ typedef enum { WMI_REQUEST_CTRL_PATH_AFC_STAT = 11, WMI_REQUEST_CTRL_PATH_PMLO_STAT = 12, WMI_REQUEST_CTRL_PATH_CFR_STAT = 13, + WMI_REQUEST_CTRL_PATH_T2LM_STAT = 14, + WMI_REQUEST_CTRL_PATH_BLANKING_STAT = 15, + WMI_REQUEST_CTRL_PATH_PEER_STAT = 16, + WMI_REQUEST_CTRL_PATH_VDEV_DEBUG_STAT = 17, + WMI_REQUEST_CTRL_STA_RRM_STAT = 18, } wmi_ctrl_path_stats_id; typedef enum { @@ -31283,6 +35070,16 @@ typedef enum wmi_hw_mode_config_type { * and Tx/Rx trigger on any PHY will switch * from 1x1 to 2x2 on that Phy */ + WMI_HW_MODE_AUX_EMLSR_SINGLE = 9, /* PHYA0 and AUX are active in listen mode + * in 1x1 and Tx/Rx trigger on any. + * PHY will switch from 1x1 to 2x2 + * on that Phy. + */ + WMI_HW_MODE_AUX_EMLSR_SPLIT = 10, /* PHYA1 and AUX are active in listen mode + * in 1x1 and Tx/Rx trigger on any. + * PHY will switch from 1x1 to 2x2 + * on that Phy. + */ } WMI_HW_MODE_CONFIG_TYPE; /* @@ -31462,6 +35259,24 @@ typedef enum wmi_hw_mode_config_type { #define WMI_SUPPORT_AAR_GET(mld_capability) WMI_GET_BITS(mld_capability, 12, 1) #define WMI_SUPPORT_AAR_SET(mld_capability, value) WMI_SET_BITS(mld_capability, 12, 1, value) +/* + * 11BE Ext MLD Capability Set and Get macros + */ +#define WMI_EXT_MLD_OPERATION_PARAMETER_UPDATE_SUPP_GET(ext_mld_capability) WMI_GET_BITS(ext_mld_capability, 0, 1) +#define WMI_EXT_MLD_OPERATION_PARAMETER_UPDATE_SUPP_SET(ext_mld_capability, value) WMI_SET_BITS(ext_mld_capability, 0, 1, value) + +/* + * 11BE MSD Capability Set and Get macros + */ +#define WMI_MEDIUM_SYNC_DURATION_GET(msd_capability) WMI_GET_BITS(msd_capability, 0, 8) +#define WMI_MEDIUM_SYNC_DURATION_SET(msd_capability,value) WMI_SET_BITS(msd_capability, 0, 8, value) + +#define WMI_MEDIUM_SYNC_OFDM_ED_THRESHOLD_GET(msd_capability) WMI_GET_BITS(msd_capability, 8, 4) +#define WMI_MEDIUM_SYNC_OFDM_ED_THRESHOLD_SET(msd_capability, value) WMI_SET_BITS(msd_capability, 8, 4, value) + +#define WMI_MEDIUM_SYNC_MAX_NO_TXOPS_GET(msd_capability) WMI_GET_BITS(msd_capability, 12, 4) +#define WMI_MEDIUM_SYNC_MAX_NO_TXOPS_SET(msd_capability, value) WMI_SET_BITS(msd_capability, 12, 4, value) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES */ /* hw_mode_id - identify a particular set of HW characteristics, as specified @@ -31737,6 +35552,23 @@ typedef struct { }; A_UINT32 mld_capability; }; + union { + struct { + A_UINT32 + op_update_para_support:1, /* Indicates support of operation parameter update negotiation */ + reserved3: 31; + }; + A_UINT32 ext_mld_capability; + }; + union { + struct { + A_UINT32 medium_sync_duration:8, + medium_sync_ofdm_ed_threshold:4, + medium_sync_max_no_txops:4, + reserved4: 16; + }; + A_UINT32 msd_capability; + }; } WMI_MAC_PHY_CAPABILITIES_EXT; typedef struct { @@ -31944,6 +35776,10 @@ typedef struct { A_UINT32 phy_id; /* regdomain value specified in EEPROM */ A_UINT32 wireless_modes_ext; + A_UINT32 low_2ghz_chan_ext; /* freq in MHz */ + A_UINT32 high_2ghz_chan_ext; /* freq in MHz */ + A_UINT32 low_5ghz_chan_ext; /* freq in MHz */ + A_UINT32 high_5ghz_chan_ext; /* freq in MHz */ } WMI_HAL_REG_CAPABILITIES_EXT2; /* @@ -31976,9 +35812,9 @@ typedef struct { * The DFS feature is disabled on this scan radio, since there will not be * much TX traffic. * The Host has to disable CAC timer because DFS feature not supported here. - * In order to know about the scan radio RDP and DFS disabled case, - * the target has to send this information to Host per pdev via - * WMI_SERVICE_READY_EXT2_EVENT. + * In order to know about the scan radio RDP, DFS disabled case and + * SCAN BLANKING support, the target has to send this information to Host + * per pdev via WMI_SERVICE_READY_EXT2_EVENT. * The target is notified of the special scan VAP by the flags variable * in the WMI_CREATE_CMD. */ @@ -31992,7 +35828,11 @@ typedef struct { * Bit 1: * 1 - DFS enabled 0 - DFS disabled * Refer to WMI_SCAN_RADIO_CAP_DFS_FLAG_SET, GET macros - * [2:31] reserved + * Bit 2: + * 1 - SCAN RADIO blanking supported + * 0 - SCAN RADIO blanking not supported + * Refer to WMI_SCAN_RADIO_CAP_BLANKING_SUPPORT_SET, GET macros + * [3:31] reserved */ A_UINT32 flags; } WMI_SCAN_RADIO_CAPABILITIES_EXT2; @@ -32003,6 +35843,9 @@ typedef struct { #define WMI_SCAN_RADIO_CAP_DFS_FLAG_GET(flag) WMI_GET_BITS(flag, 1, 1) #define WMI_SCAN_RADIO_CAP_DFS_FLAG_SET(flag, val) WMI_SET_BITS(flag, 1, 1, val) +#define WMI_SCAN_RADIO_CAP_BLANKING_SUPPORT_GET(flag) WMI_GET_BITS(flag, 2, 1) +#define WMI_SCAN_RADIO_CAP_BLANKING_SUPPORT_SET(flag, val) WMI_SET_BITS(flag, 2, 1, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SOC_HAL_REG_CAPABILITIES */ A_UINT32 num_phy; @@ -32032,10 +35875,22 @@ typedef struct { **************************************************************************/ } WMI_OEM_DMA_RING_CAPABILITIES; +typedef enum { + WMI_SAR_VERSION_0_ORIGINAL = 0x00, + WMI_SAR_VERSION_1_FULL_TABLE = 0x01, + WMI_SAR_VERSION_2_DBS_SAR = 0x02, + WMI_SAR_VERSION_3_SBS_SAR = 0x03, + + WMI_SAR_VERSION_SMART_TX = 0x04, + WMI_SAR_VERSION_TAS = 0x05, + + WMI_SAR_VERSION_INVALID = 0x80 +} wmi_sar_version_t; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SAR_CAPABILITIES*/ /* sar version in bdf */ - A_UINT32 active_version; + A_UINT32 active_version; /* contains a wmi_sar_version_t value */ /************************************************************************** * DON'T ADD ANY FURTHER FIELDS HERE - @@ -33043,9 +36898,26 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_RMC_SET_MANUAL_LEADER_CMDID); WMI_RETURN_STRING(WMI_11D_SCAN_START_CMDID); WMI_RETURN_STRING(WMI_11D_SCAN_STOP_CMDID); + WMI_RETURN_STRING(WMI_VENDOR_PDEV_CMDID); WMI_RETURN_STRING(WMI_VENDOR_VDEV_CMDID); WMI_RETURN_STRING(WMI_VENDOR_PEER_CMDID); WMI_RETURN_STRING(WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID); /* XPAN TWT */ + WMI_RETURN_STRING(WMI_ESL_EGID_CMDID); + WMI_RETURN_STRING(WMI_TDMA_SCHEDULE_REQUEST_CMDID); + WMI_RETURN_STRING(WMI_HPA_CMDID); + WMI_RETURN_STRING(WMI_PDEV_SET_TGTR2P_TABLE_CMDID); /* To set target rate to power table */ + WMI_RETURN_STRING(WMI_MLO_VDEV_GET_LINK_INFO_CMDID); + WMI_RETURN_STRING(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID); + WMI_RETURN_STRING(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID); + WMI_RETURN_STRING(WMI_VDEV_STANDALONE_SOUND_CMDID); + WMI_RETURN_STRING(WMI_PDEV_SET_RF_PATH_CMDID); /* set RF path of PHY */ + WMI_RETURN_STRING(WMI_VDEV_PAUSE_CMDID); + WMI_RETURN_STRING(WMI_GPIO_STATE_REQ_CMDID); + WMI_RETURN_STRING(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID); + WMI_RETURN_STRING(WMI_MLO_LINK_RECOMMENDATION_CMDID); + WMI_RETURN_STRING(WMI_NAN_OEM_DATA_CMDID); + WMI_RETURN_STRING(WMI_PDEV_WSI_STATS_INFO_CMDID); + WMI_RETURN_STRING(WMI_CSA_EVENT_STATUS_INDICATION_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -33316,6 +37188,11 @@ typedef struct { bits 15:1 - reserved bits 31:16 - maximum PSD EIRP (dB/MHz) */ +/* + * NOTE: no further fields can be added into this struct, due to + * message buffer size limitations in certain targets for the + * WMI_REG_CHAN_LIST_CC_EXT_EVENT message. + */ } wmi_regulatory_rule_ext_struct; #define WMI_REG_CHAN_PRIORITY_FREQ_GET(freq_info) WMI_GET_BITS(freq_info, 0, 16) @@ -33330,6 +37207,11 @@ typedef struct { * the frequencies below this value will be de-prioritized. * bits 31:16 = reserved for future */ +/* + * NOTE: no further fields can be added into this struct, due to + * message buffer size limitations in certain targets for the + * WMI_REG_CHAN_LIST_CC_EXT_EVENT message. + */ } wmi_regulatory_chan_priority_struct; #define WMI_REG_FCC_RULE_CHAN_FREQ_GET(freq_info) WMI_GET_BITS(freq_info, 0, 16) @@ -33345,6 +37227,11 @@ typedef struct { * bits 23:16 = u8 FCC_Tx_power (dBm units) * bits 31:24 = u8 reserved for future */ +/* + * NOTE: no further fields can be added into this struct, due to + * message buffer size limitations in certain targets for the + * WMI_REG_CHAN_LIST_CC_EXT_EVENT message. + */ } wmi_regulatory_fcc_rule_struct; typedef enum { @@ -33451,6 +37338,11 @@ typedef struct { A_UINT32 num_6g_reg_rules_client_sp[WMI_REG_CLIENT_MAX]; A_UINT32 num_6g_reg_rules_client_lpi[WMI_REG_CLIENT_MAX]; A_UINT32 num_6g_reg_rules_client_vlp[WMI_REG_CLIENT_MAX]; +/* + * NOTE: no further fields can be added into this struct, due to + * message buffer size limitations in certain targets for the + * WMI_REG_CHAN_LIST_CC_EXT_EVENT message. + */ /* * This fixed_param TLV is followed by the following TLVs: * - wmi_regulatory_rule_ext reg_rule_array[] struct TLV array. @@ -34383,15 +38275,28 @@ typedef struct { * requester and broadcast requester. Same way for RESPONDER. * */ +/* 0: requester; 1: responder */ #define TWT_EN_DIS_FLAGS_GET_REQ_RESP(flag) WMI_GET_BITS(flag, 4, 1) #define TWT_EN_DIS_FLAGS_SET_REQ_RESP(flag, val) WMI_SET_BITS(flag, 4, 1, val) +/* 0: iTWT; 1: bTWT */ #define TWT_EN_DIS_FLAGS_GET_I_B_TWT(flag) WMI_GET_BITS(flag, 5, 1) #define TWT_EN_DIS_FLAGS_SET_I_B_TWT(flag, val) WMI_SET_BITS(flag, 5, 1, val) +/* 0: bTWT; 1: rTWT */ #define TWT_EN_DIS_FLAGS_GET_B_R_TWT(flag) WMI_GET_BITS(flag, 6, 1) #define TWT_EN_DIS_FLAGS_SET_B_R_TWT(flag, val) WMI_SET_BITS(flag, 6, 1, val) +/* + * disable autonomous bTWT session delete feature + * This feature will delete client triggered session when number of clients + * joined decreases to 0. + */ +#define TWT_EN_DIS_FLAGS_GET_DIS_BTWT_AUTO_DELETE(flag) \ + WMI_GET_BITS(flag, 7, 1) +#define TWT_EN_DIS_FLAGS_SET_DIS_BTWT_AUTO_DELETE(flag, val) \ + WMI_SET_BITS(flag, 7, 1, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_enable_cmd_fixed_param */ /** pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0 @@ -34648,6 +38553,10 @@ typedef enum _WMI_ADD_TWT_STATUS_T { WMI_ADD_TWT_STATUS_CHAN_SW_IN_PROGRESS, /* Channel switch in progress */ WMI_ADD_TWT_STATUS_SCAN_IN_PROGRESS, /* Scan in progress */ WMI_ADD_TWT_STATUS_DIALOG_ID_BUSY, /* FW is in the process of handling this dialog */ + WMI_ADD_TWT_STATUS_BTWT_NOT_ENBABLED, /* Broadcast TWT is not enabled */ + WMI_ADD_TWT_STATUS_RTWT_NOT_ENBABLED, /* Restricted TWT is not enabled */ + WMI_ADD_TWT_STATUS_LINK_SWITCH_IN_PROGRESS, /* Link switch is ongoing */ + WMI_ADD_TWT_STATUS_UNSUPPORTED_MODE_MLMR, /* Unsupported in MLMR mode */ } WMI_ADD_TWT_STATUS_T; typedef struct { @@ -34818,6 +38727,9 @@ typedef struct { A_UINT32 vdev_id; /* VDEV identifier */ wmi_mac_addr peer_macaddr; /* peer MAC address */ A_UINT32 dialog_id; /* TWT dialog ID */ + /* parameters required for R-TWT feature */ + A_UINT32 r_twt_dl_tid_bitmap; + A_UINT32 r_twt_ul_tid_bitmap; } wmi_twt_btwt_invite_sta_cmd_fixed_param; /* status code of inviting STA to B-TWT dialog */ @@ -34845,6 +38757,9 @@ typedef struct { A_UINT32 vdev_id; /* VDEV identifier */ wmi_mac_addr peer_macaddr; /* peer MAC address */ A_UINT32 dialog_id; /* TWT dialog ID */ + /* parameters required for R-TWT feature */ + A_UINT32 r_twt_dl_tid_bitmap; + A_UINT32 r_twt_ul_tid_bitmap; } wmi_twt_btwt_remove_sta_cmd_fixed_param; /* status code of removing STA from B-TWT dialog */ @@ -34870,6 +38785,7 @@ typedef struct { typedef enum { WMI_DMA_RING_CONFIG_MODULE_SPECTRAL, WMI_DMA_RING_CONFIG_MODULE_RTT, + WMI_DMA_RING_CONFIG_MODULE_CV_UPLOAD, } WMI_DMA_RING_SUPPORTED_MODULE; typedef struct { @@ -35028,6 +38944,9 @@ typedef struct { /* This TLV is followed by another TLV of array of structs. * wmi_dma_buf_release_entry entries[num_buf_release_entry]; * wmi_dma_buf_release_spectral_meta_data meta_datat[num_meta_data_entry]; + * wmi_dma_buf_release_cv_upload_meta_data cv_meta_data[num_meta_data_entry] + * wmi_dma_buf_release_cqi_upload_meta_data + * cqi_meta_data[num_meta_data_entry] */ } wmi_dma_buf_release_fixed_param; @@ -35379,6 +39298,12 @@ typedef struct { A_UINT32 timestamp; /* Original timeout value in milli seconds when AP added to BL */ A_UINT32 original_timeout; + /* + * If disallow_linkid_bitmap is not 0, then means current entity + * is for MLD AP and bssid field is standing for MLD address. + * If all links for MLD AP is disallow, then the value shall be 0xffffffff + */ + A_UINT32 disallow_linkid_bitmap; } wmi_pdev_bssid_disallow_list_config_param; typedef enum { @@ -35640,9 +39565,9 @@ typedef struct { /* btm_req_dialog_token: dialog token number in BTM request frame */ A_UINT32 btm_req_dialog_token; /* data RSSI in dBm when abort to roam scan */ - A_UINT32 data_rssi; + A_INT32 data_rssi; /* data RSSI threshold in dBm */ - A_UINT32 data_rssi_threshold; + A_INT32 data_rssi_threshold; /* rx linkspeed status, 0:good linkspeed, 1:bad */ A_UINT32 rx_linkspeed_status; } wmi_roam_trigger_reason; @@ -35650,6 +39575,16 @@ typedef struct { #define WMI_GET_BTCONNECT_STATUS(flags) WMI_GET_BITS(flags, 0, 1) #define WMI_SET_BTCONNECT_STATUS(flags, val) WMI_SET_BITS(flags, 0, 1, val) +#define WMI_GET_MLO_BAND(flags) WMI_GET_BITS(flags, 1, 3) +#define WMI_SET_MLO_BAND(flags, val) WMI_SET_BITS(flags, 1, 3, val) + +typedef enum wmi_mlo_band_info { + WMI_MLO_BAND_NO_MLO = 0, + WMI_MLO_BAND_2GHZ_MLO, + WMI_MLO_BAND_5GHZ_MLO, + WMI_MLO_BAND_6GHZ_MLO, +} wmi_mlo_band_info_t; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_info_tlv_param */ /* roam_scan_type: @@ -35673,7 +39608,10 @@ typedef struct { /* * Flags capturing factors involved during roam scan: * Bit 0 : Bluetooth connect status, 0(not connected) or 1(connected). - * Bit 1-31 : reserved for future use. + * Bit 1-3 : Indicates which link triggered roaming in MLD cases. + * The value is one of the wmi_mlo_band_info_t enum constants. + * Refer to WMI_[GET,SET]_MLO_BAND macros. + * Bit 4-31 : reserved for future use. */ A_UINT32 flags; } wmi_roam_scan_info; @@ -35688,6 +39626,9 @@ typedef struct { */ } wmi_roam_scan_channel_info; +#define WMI_GET_AP_INFO_MLO_STATUS(flags) WMI_GET_BITS(flags, 0, 1) +#define WMI_SET_AP_INFO_MLO_STATUS(flags, val) WMI_SET_BITS(flags, 0, 1, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_ap_info_tlv_param */ /* @@ -35723,6 +39664,12 @@ typedef struct { A_UINT32 bl_timestamp; /* Original timeout value in milli seconds when AP added to BL */ A_UINT32 bl_original_timeout; + /* flags: + * bit 0: MLD AP FLAG -> 1: MLD AP, 0: non-MLD AP + * Refer to WMI_[GET,SET]_AP_INFO_MLO_STATUS macros. + * bit 1-31: reserved. + */ + A_UINT32 flags; } wmi_roam_ap_info; typedef enum { @@ -35764,6 +39711,11 @@ typedef enum { WMI_ROAM_FAIL_REASON_SAE_PREAUTH_FAIL, /* WPA3-SAE pre-authentication failed */ WMI_ROAM_FAIL_REASON_UNABLE_TO_START_ROAM_HO, /* Roam HO is not started due to FW internal issue */ + /* Failure reasons to indicate no candidate and final bmiss event sent */ + WMI_ROAM_FAIL_REASON_NO_AP_FOUND_AND_FINAL_BMISS_SENT, /* No roamable APs found during roam scan and final bmiss event sent */ + WMI_ROAM_FAIL_REASON_NO_CAND_AP_FOUND_AND_FINAL_BMISS_SENT, /* No candidate APs found during roam scan and final bmiss event sent */ + WMI_ROAM_FAIL_REASON_CURR_AP_STILL_OK, /* Roam scan not happen due to current network condition is fine */ + WMI_ROAM_FAIL_REASON_UNKNOWN = 255, } WMI_ROAM_FAIL_REASON_ID; @@ -35795,6 +39747,8 @@ typedef struct { #define WMI_ROAM_NEIGHBOR_REPORT_INFO_RESPONSE_TOKEN_SET(detail,val) WMI_SET_BITS(detail, 8, 8, val) #define WMI_ROAM_NEIGHBOR_REPORT_INFO_NUM_OF_NRIE_GET(detail) WMI_GET_BITS(detail, 16, 8) #define WMI_ROAM_NEIGHBOR_REPORT_INFO_NUM_OF_NRIE_SET(detail,val) WMI_SET_BITS(detail, 16, 8, val) +#define WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_GET(detail) WMI_GET_BITS(detail, 24, 3) +#define WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_SET(detail,val) WMI_SET_BITS(detail, 24, 3, val) typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_neighbor_report_info_tlv_param */ @@ -35825,13 +39779,20 @@ typedef struct { * [7:0] : neighbor report request token * [15:8] : neighbor report response token * [23:16] : the number of neighbor report elements in response frame - * [31:24] : reserved + * [26:24] : band on which frame is sent; the value will be one of the + * wmi_mlo_band_info enum constants + * Refer to WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_GET,SET + * macros. + * [31:27] : reserved * Refer to the above WMI_ROAM_NEIGHBOR_REPORT_INFO_*_GET,_SET macros for * reading and writing these bitfields. */ A_UINT32 neighbor_report_detail; } wmi_roam_neighbor_report_info; +#define WMI_ROAM_BTM_RESP_MLO_BAND_INFO_GET(detail) WMI_GET_BITS(detail, 0, 3) +#define WMI_ROAM_BTM_RESP_MLO_BAND_INFO_SET(detail,val) WMI_SET_BITS(detail, 0, 3, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_btm_response_info_tlv_param */ @@ -35865,6 +39826,13 @@ typedef struct { * that the responding STA requests the BSS to delay termination. */ A_UINT32 btm_resp_bss_termination_delay; + /* info: + * Bit[0:2] - band on which frame is sent, band value will be one of the + * wmi_mlo_band_info_t enum constants + * Refer to WMI_ROAM_BTM_RESP_MLO_BAND_INFO_GET,SET macros. + * Bit[3:31] - reserved. + */ + A_UINT32 info; } wmi_roam_btm_response_info; typedef struct { @@ -35881,6 +39849,15 @@ typedef struct { #define WMI_GET_ASSOC_ID(frame_info_ext) WMI_GET_BITS(frame_info_ext, 0, 16) #define WMI_SET_ASSOC_ID(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 0, 16, val) +#define WMI_GET_MLO_BITMAP_BAND_INFO(frame_info_ext) WMI_GET_BITS(frame_info_ext, 16, 5) +#define WMI_SET_MLO_BITMAP_BAND_INFO(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 16, 5, val) + +#define WMI_GET_RX_INDICATE(frame_info_ext) WMI_GET_BITS(frame_info_ext, 21, 1) +#define WMI_SET_RX_INDICATE(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 21, 1, val) + +#define WMI_GET_TX_FAILED_REASON(frame_info_ext) WMI_GET_BITS(frame_info_ext, 22, 4) +#define WMI_SET_TX_FAILED_REASON(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 22, 4, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_frame_info_tlv_param */ /* timestamp is the absolute time w.r.t host timer which is synchronized between the host and target */ @@ -35928,7 +39905,14 @@ typedef struct { * frame_info_ext captures below fields: * Bit 0-15 : (re)assoc id of (re)association response frame, * section 9.4.1.8 AID field. - * Bit 16~31 : reserved for future use. + * Bit 16-20 : MLO bitmap band info, + * bit0: 2GHz, bit1: 5GHz, bit2: 6GHz, bits 3-4: reserved + * Refer to WMI_[GET,SET]_MLO_BITMAP_BAND_INFO macros. + * Bit 21 : indicate whether this frame is rx :0-not rx; 1-rx + * Refer to WMI_[GET,SET]_RX_INDICATE macros. + * Bit 22-25 : opaque tx failure reason + * Refer to WMI_[GET,SET]_TX_FAILED_REASON macros. + * Bit 26-31 : reserved for future use. */ A_UINT32 frame_info_ext; } wmi_roam_frame_info; @@ -36208,6 +40192,7 @@ typedef struct { * Bit 2: 6G band support if 1 */ A_UINT32 support_link_band; /* Configure the band bitmap of mlo connection supports. */ + A_UINT32 max_active_links; /* Max active links supported for STA */ } wmi_roam_mlo_config_cmd_fixed_param; typedef struct { @@ -36375,6 +40360,22 @@ typedef enum { */ WMI_ROAM_PARAM_ROAM_RSSI_BOOST_FOR_6GHZ_CAND_AP = 8, + /* + * Roam param to indicate unsupported Power Type for 6 GHz Candidate AP + * found during Roam Scan. If AP operates on the power type disabled by + * the host, then that candidate should not be selected. + * This unsupported Power Type will be configured based + * on disabled 6GHz Power Types in Regdomain + * + * If below bits in the obtianed Bitmap is set then any AP + * broadcasting these Power Types should not be selected + * BIT 0 - Indoor Access Point + * BIT 1 - Standard Power (SP) Access Point + * BIT 2 - Very Low Power (VLP) Access Point + * BIT 3-7 - Reserved + */ + WMI_ROAM_PARAM_ROAM_UNSUPPORTED_6GHZ_POWERTYPE = 9, + /*=== END ROAM_PARAM_PROTOTYPE SECTION ===*/ } WMI_ROAM_PARAM; @@ -36628,6 +40629,229 @@ typedef struct { A_UINT32 perChainIbfCalVal[WMI_MAX_CHAINS_FOR_AOA_RCC]; } wmi_pdev_aoa_phasedelta_evt_fixed_param; +#define WMI_AOA_MAX_SUPPORTED_CHAINS_GET(chain_data) \ + WMI_GET_BITS(chain_data, 0, 16) +#define WMI_AOA_MAX_SUPPORTED_CHAINS_SET(chain_data, value) \ + WMI_SET_BITS(chain_data, 0, 16, value) + +#define WMI_AOA_SUPPORTED_CHAINMASK_GET(chain_data) \ + WMI_GET_BITS(chain_data, 16, 16) +#define WMI_AOA_SUPPORTED_CHAINMASK_SET(chain_data, value) \ + WMI_SET_BITS(chain_data, 16, 16, value) + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_eventid */ + A_UINT32 tlv_header; + /* Current Operating Channel Frequency in MHz */ + A_UINT32 freq; + /** pdev_id: + * Identify the MAC. + * See macros starting with WMI_PDEV_ID_ for values. + * In non-DBDC case host should set it to 0. + */ + A_UINT32 pdev_id; + /** chain_info: + * B0 -- B15 : Max number of chains supported + * B16 --B31 : Data shared for chainmask - + * indicates the chains to which the data shared. + */ + union { + struct { + A_UINT32 max_supported_chains:16, + data_for_chainmask:16; + }; + A_UINT32 chain_info; + }; + /** XBAR configuration to get RF2BB/BB2RF chain mapping + * Samples of xbar_config, + * If xbar_config is 0xFAC688(hex): + * RF chains 0-7 are connected to BB chains 0-7 + * here, + * bits 0 to 2 = 0, maps BB chain 0 for RF chain 0 + * bits 3 to 5 = 1, maps BB chain 1 for RF chain 1 + * bits 6 to 8 = 2, maps BB chain 2 for RF chain 2 + * bits 9 to 11 = 3, maps BB chain 3 for RF chain 3 + * bits 12 to 14 = 4, maps BB chain 4 for RF chain 4 + * bits 15 to 17 = 5, maps BB chain 5 for RF chain 5 + * bits 18 to 20 = 6, maps BB chain 6 for RF chain 6 + * bits 21 to 23 = 7, maps BB chain 7 for RF chain 7 + * + * If xbar_config is 0x688FAC(hex): + * RF chains 0-3 are connected to BB chains 4-7 + * RF chains 4-7 are connected to BB chains 0-3 + * here, + * bits 0 to 2 = 4, maps BB chain 4 for RF chain 0 + * bits 3 to 5 = 5, maps BB chain 5 for RF chain 1 + * bits 6 to 8 = 6, maps BB chain 6 for RF chain 2 + * bits 9 to 11 = 7, maps BB chain 7 for RF chain 3 + * bits 12 to 14 = 0, maps BB chain 0 for RF chain 4 + * bits 15 to 17 = 1, maps BB chain 1 for RF chain 5 + * bits 18 to 20 = 2, maps BB chain 2 for RF chain 6 + * bits 21 to 23 = 3, maps BB chain 3 for RF chain 7 + */ + A_UINT32 xbar_config; + /** + * IBF cal values: + * Used for final AoA calculation + * [AoAPhase = ( PhaseDeltaValue + IBFcalValue ) % 1024] + */ + A_UINT32 per_chain_ibf_cal_val[WMI_MAX_CHAINS]; + /** + * This TLV is followed by TLV arrays containing + * different types of data header and data buffer TLVs: + * 1. wmi_enhanced_aoa_gain_phase_data_hdr. + * This TLV contains the array of structure fields which indicate + * the type and format of data carried in the following data buffer + * TLV. + * 2. aoa_data_buf[] - Data buffer TLV. + * TLV header contains the total buffer size. + * Data buffer contains the phase_delta_array[Chains][GainEntries] + * in absolute phase values ranging 0-1024 and + * gain_delta_array[Chains][GainEntries] are gain index values. + */ +} wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param; + +#define WMI_AOA_DATA_TYPE_GET(data_info) \ + WMI_GET_BITS(data_info, 0, 8) +#define WMI_AOA_DATA_TYPE_SET(data_info,value) \ + WMI_SET_BITS(data_info, 0, 8, value) + +#define WMI_AOA_NUM_ENTIRES_GET(data_info) \ + WMI_GET_BITS(data_info, 8, 8) +#define WMI_AOA_NUM_DATA_ENTRIES_SET(data_info,value) \ + WMI_SET_BITS(data_info, 8, 8, value) + +typedef enum _WMI_AOA_EVENT_DATA_TYPE { + WMI_PHASE_DELTA_ARRAY = 0x0, + WMI_GAIN_GROUP_STOP_ARRAY = 0x1, + /* add new types here */ + WMI_MAX_DATA_TYPE_ARRAY, +} WMI_AOA_EVENT_DATA_TYPE; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_eventid */ + A_UINT32 tlv_header; + /** data_info: + * Data follows the LSB first and MSB second order in a 32bit word + * bit mapping: + * B0 -- B7 : Data type + * B8 -- B15 : Number of entries to be parsed in terms of 32bit word + * + * If data is Phase delta values - Data type is 0x0 + * group stop gain index values - Data type is 0x1 + * + * num_entries - Total number of data entries in uint32 + */ + union { + struct { + A_UINT32 data_type:8, + num_entries:8, + reserved:16; + }; + A_UINT32 data_info; + }; +} wmi_enhanced_aoa_gain_phase_data_hdr; + +typedef enum _WMI_AGC_GAIN_TABLE_IDX { + WMI_AGC_DG_TABLE_IDX = 0, + WMI_AGC_LG_TABLE_IDX, + WMI_AGC_VLG_TABLE_IDX, + WMI_AGC_MAX_GAIN_TABLE_IDX = 8, +} WMI_AGC_GAIN_TABLE_IDX; + +#define WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD 4 +#define WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD 2 +#define WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM 1 +#define WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM 2 + +/* Number of words required to store max number of gain table elements = ((max number of gain table elements)/(number of gain table elements per word)) */ +/* 2 bytes (at most)used to store each gain table elements */ +#define WMI_AOA_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS (WMI_AGC_MAX_GAIN_TABLE_IDX / WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD) + +/* 1 byte (at most) used to store each gain table elements obtained from BDF */ +#define WMI_AOA_BDF_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS (WMI_AGC_MAX_GAIN_TABLE_IDX / WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD) + +typedef enum { + WMI_AOA_2G = 0, + WMI_AOA_5G, + WMI_AOA_6G, + WMI_AOA_MAX_BAND, +} WMI_AOA_SUPPORTED_BANDS; + +#define WMI_AOA_MAX_AGC_GAIN_GET(pcap_var, tbl_idx, output) \ + do { \ + A_UINT8 word_idx = 0; \ + A_UINT8 bit_index = 0; \ + A_UINT8 nth_byte = 0; \ + word_idx = tbl_idx >> 1; \ + nth_byte = (tbl_idx % WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD); \ + bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM; \ + output = WMI_GET_BITS(*(pcap_var + word_idx), bit_index, 16); \ + } while (0) + +#define WMI_AOA_MAX_AGC_GAIN_SET(pcap_var, tbl_idx, value) \ + do { \ + A_UINT8 word_idx = 0; \ + A_UINT8 bit_index = 0; \ + A_UINT8 nth_byte = 0; \ + word_idx = tbl_idx >> 1; \ + nth_byte = (tbl_idx % WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD); \ + bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM; \ + WMI_SET_BITS(*(pcap_var+word_idx), bit_index, 16, value); \ + } while (0) + +#define WMI_AOA_MAX_BDF_ENTRIES_GET(pcap_var, tbl_idx, output) \ + do { \ + A_UINT8 word_idx = 0; \ + A_UINT8 bit_index = 0; \ + A_UINT8 nth_byte = 0; \ + word_idx = tbl_idx >> 2; \ + nth_byte = (tbl_idx % WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD); \ + bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM; \ + output = WMI_GET_BITS(*(pcap_var+word_idx), bit_index, 8); \ + } while (0) + +#define WMI_AOA_MAX_BDF_ENTRIES_SET(pcap_var, tbl_idx, value) \ + do { \ + A_UINT8 word_idx = 0; \ + A_UINT8 nth_byte = 0; \ + A_UINT8 bit_index = 0; \ + word_idx = tbl_idx >> 2; \ + nth_byte = (tbl_idx % WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD); \ + bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM; \ + WMI_SET_BITS(*(pcap_var+word_idx), bit_index, 8, value); \ + } while (0) + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param */ + A_UINT32 tlv_header; + + /* Maximum number of Rx AGC gain tables supported */ + A_UINT32 max_agc_gain_tbls; + + /* 1 byte is used to store bdf max number of elements in each gain tables */ + A_UINT32 max_bdf_gain_entries[WMI_AOA_BDF_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS]; + + /** This TLV is followed by TLV array - wmi_enhanced_aoa_per_band_caps_param + * containing band specifc agc gain table information. + */ +} wmi_enhanced_aoa_caps_param; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param */ + A_UINT32 tlv_header; + + /* Band information - WMI_AOA_SUPPORTED_BANDS */ + A_UINT32 band_info; + + /* 2 bytes are used to store agc max number of elements in each gain tables */ + A_UINT32 max_agc_gain[WMI_AOA_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS]; +} wmi_enhanced_aoa_per_band_caps_param; + /* WMI_HALPHY_CAL_LIST: * * Below is the list of HALPHY online CAL currently enabled in @@ -36928,6 +41152,36 @@ typedef struct { */ } wmi_peer_chan_width_switch_cmd_fixed_param; +#define WMI_PEER_BULK_SET_VDEV_ID(comp, value) WMI_SET_BITS(comp, 0, 8, value) +#define WMI_PEER_BULK_GET_VDEV_ID(comp) WMI_GET_BITS(comp, 0, 8) +/* bits 30:8 currently unused */ +#define WMI_PEER_BULK_SET_VALID_VDEV_ID(comp) WMI_SET_BITS(comp, 31, 1, 1) +#define WMI_PEER_BULK_GET_VALID_VDEV_ID(comp) WMI_GET_BITS(comp, 31, 1) + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUCT_wmi_peer_list */ + wmi_mac_addr peer_macaddr; + /** parameter id */ + A_UINT32 param_id; + A_UINT32 param_value; +} wmi_peer_list; + +/* WMI_PEER_BULK_SET_CMDID */ +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_bulk_set_cmd_fixed_param */ + /* vdev_var: + * The MSb (bit 31) indicates that the vdev_id is valid. + * The LSB (bits 0-7) is used to infer the actual vdev_id. + * The other bits can be used for future enhancements. + */ + A_UINT32 vdev_var; + + /* + * Following this structure is the TLV array: + * struct wmi_peer_list peer_info[]; + */ +} wmi_peer_bulk_set_cmd_fixed_param; + typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_he_tb_action_frm_cmd_fixed_param */ A_UINT32 tlv_header; @@ -38210,7 +42464,20 @@ typedef struct { #define WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 1, 1) #define WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 1, 1, value) -/* Bits 66-71: reserved */ +/* Bit 66: 20Mhz-only limited capabilities support */ +#define WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 2, 1) +#define WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 2, 1, value) + +/* Bit 67: 20Mhz-only triggered MU beamforming full BW feedback and DL MU-MIMO */ +#define WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 3, 1) +#define WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 3, 1, value) + +/* Bit 68: 20Mhz-only M-RU support */ +#define WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 4, 1) +#define WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 4, 1, value) + + +/* Bits 69-71: reserved */ /****** End of 11BE EHT PHY Capabilities Information field ******/ @@ -38264,7 +42531,15 @@ typedef struct { #define WMI_EHTCAP_MAC_TXOP_RETURN_SUPP_IN_SHARINGMODE2_GET(eht_cap_mac) WMI_GET_BITS(eht_cap_mac[0], 10, 1) #define WMI_EHTCAP_MAC_TXOP_RETURN_SUPP_IN_SHARINGMODE2_SET(eht_cap_mac, value) WMI_SET_BITS(eht_cap_mac[0], 10, 1, value) -/* Bit 11-15: reserved */ +/* Bit 11: two BQRs support */ +#define WMI_EHTCAP_MAC_TWO_BQRS_SUPP_GET(eht_cap_mac) WMI_GET_BITS(eht_cap_mac[0], 11, 1) +#define WMI_EHTCAP_MAC_TWO_BQRS_SUPP_SET(eht_cap_mac, value) WMI_SET_BITS(eht_cap_mac[0], 11, 1, value) + +/* Bit 12-13: EHT link adaptation support */ +#define WMI_EHTCAP_MAC_EHT_LINK_ADAPTATION_SUPP_GET(eht_cap_mac) WMI_GET_BITS(eht_cap_mac[0], 12, 2) +#define WMI_EHTCAP_MAC_EHT_LINK_ADAPTATION_SUPP_SET(eht_cap_mac, value) WMI_SET_BITS(eht_cap_mac[0], 12, 2, value) + +/* Bit 14-15: reserved */ /****** End of 11BE EHT MAC Capabilities Information field ******/ @@ -38916,6 +43191,38 @@ typedef struct { A_UINT32 en_dis_chain; } wmi_set_ocl_cmd_fixed_param; +typedef enum { + /* HPA Handshake Stages */ + WMI_HPA_SMCK_REQUEST = 0, + WMI_HPA_SMCK_RESPONSE = 1, + WMI_HPA_SIGN_REQUEST = 2, + WMI_HPA_SIGN_RESPONSE = 3, + WMI_HPA_HANDSHAKE_STAGE_MAX, +} WMI_HPA_STAGE_TYPE; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_hpa_cmd_fixed_param */ + /* stage: + * HPA Handshake Stage, filled with a WMI_HPA_STAGE_TYPE enum value + */ + A_UINT32 stage; + + /* the base address and length of data on host memory */ + A_UINT32 base_paddr_low; /* bits 31:0 */ + A_UINT32 base_paddr_high; /* bits 63:32 */ + A_UINT32 len; /* units = bytes */ +} wmi_hpa_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_hpa_evt_fixed_param */ + /* stage: + * HPA Handshake Stage, filled with a WMI_HPA_STAGE_TYPE enum value + */ + A_UINT32 stage; + + A_UINT32 nonce; +} wmi_hpa_evt_fixed_param; + typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_audio_sync_qtimer */ A_UINT32 vdev_id; @@ -39946,6 +44253,9 @@ typedef struct { #define WMI_TWT_SESSION_FLAG_TWT_PM_RESPONDER_MODE_GET(_var) WMI_GET_BITS(_var, 22, 1) #define WMI_TWT_SESSION_FLAG_TWT_PM_RESPONDER_MODE_SET(_var, _val) WMI_SET_BITS(_var, 22, 1, _val) +#define WMI_TWT_SESSION_FLAG_RESTRICTED_TWT_GET(_var) WMI_GET_BITS(_var, 23, 1) +#define WMI_TWT_SESSION_FLAG_RESTRICTED_TWT_SET(_var, _val) WMI_SET_BITS(_var, 23, 1, _val) + typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_session_stats_info */ A_UINT32 tlv_hdr; @@ -39989,7 +44299,7 @@ typedef struct { typedef struct wmi_pdev_vendor_event { - /* type is WMI_PDEV_VENDOR_EVENTID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_pdev_event_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -40002,11 +44312,19 @@ typedef struct wmi_pdev_vendor_event * because their offsets within wmi_pdev_vendor_event_fixed_param * would change, causing backwards incompatibilities. */ +/* + * This fixed_param TLV may be followed by the below TLVs: + * - A_UINT32 opaque_vendor_var_len_data[]: + * Variable-length array of opaque data. + * The _fixed_param.sub_type value clarifies how to interpret the + * contents of this opaque data. + */ } wmi_pdev_vendor_event_fixed_param; +typedef wmi_pdev_vendor_event_fixed_param wmi_vendor_pdev_event_fixed_param; typedef struct wmi_vdev_vendor_event { - /* type is WMI_VDEV_VENDOR_EVENTID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_vdev_event_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -40021,11 +44339,19 @@ typedef struct wmi_vdev_vendor_event * because their offsets within wmi_vdev_vendor_event_fixed_param * would change, causing backwards incompatibilities. */ +/* + * This fixed_param TLV may be followed by the below TLVs: + * - A_UINT32 opaque_vendor_var_len_data[]: + * Variable-length array of opaque data. + * The _fixed_param.sub_type value clarifies how to interpret the + * contents of this opaque data. + */ } wmi_vdev_vendor_event_fixed_param; +typedef wmi_vdev_vendor_event_fixed_param wmi_vendor_vdev_event_fixed_param; typedef struct wmi_peer_vendor_event { - /* type is WMI_PEER_VENDOR_EVENTID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_peer_event_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -40042,11 +44368,19 @@ typedef struct wmi_peer_vendor_event * because their offsets within wmi_peer_vendor_event_fixed_param * would change, causing backwards incompatibilities. */ +/* + * This fixed_param TLV may be followed by the below TLVs: + * - A_UINT32 opaque_vendor_var_len_data[]: + * Variable-length array of opaque data. + * The _fixed_param.sub_type value clarifies how to interpret the + * contents of this opaque data. + */ } wmi_peer_vendor_event_fixed_param; +typedef wmi_peer_vendor_event_fixed_param wmi_vendor_peer_event_fixed_param; typedef struct wmi_pdev_vendor_cmd { - /* type is WMI_PDEV_VENDOR_CMDID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_pdev_cmd_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -40059,11 +44393,19 @@ typedef struct wmi_pdev_vendor_cmd * because their offsets within wmi_pdev_vendor_cmd_fixed_param * would change, causing backwards incompatibilities. */ +/* + * This fixed_param TLV may be followed by the below TLVs: + * - A_UINT32 opaque_vendor_var_len_data[]: + * Variable-length array of opaque data. + * The _fixed_param.sub_type value clarifies how to interpret the + * contents of this opaque data. + */ } wmi_pdev_vendor_cmd_fixed_param; +typedef wmi_pdev_vendor_cmd_fixed_param wmi_vendor_pdev_cmd_fixed_param; typedef struct wmi_vdev_vendor_cmd { - /* type is WMI_VDEV_VENDOR_CMDID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_vdev_cmd_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -40078,11 +44420,19 @@ typedef struct wmi_vdev_vendor_cmd * because their offsets within wmi_vdev_vendor_cmd_fixed_param * would change, causing backwards incompatibilities. */ +/* + * This fixed_param TLV may be followed by the below TLVs: + * - A_UINT32 opaque_vendor_var_len_data[]: + * Variable-length array of opaque data. + * The _fixed_param.sub_type value clarifies how to interpret the + * contents of this opaque data. + */ } wmi_vdev_vendor_cmd_fixed_param; +typedef wmi_vdev_vendor_cmd_fixed_param wmi_vendor_vdev_cmd_fixed_param; typedef struct wmi_peer_vendor_cmd { - /* type is WMI_PEER_VENDOR_CMDID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_peer_cmd_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -40099,7 +44449,15 @@ typedef struct wmi_peer_vendor_cmd * because their offsets within wmi_peer_vendor_cmd_fixed_param * would change, causing backwards incompatibilities. */ +/* + * This fixed_param TLV may be followed by the below TLVs: + * - A_UINT32 opaque_vendor_var_len_data[]: + * Variable-length array of opaque data. + * The _fixed_param.sub_type value clarifies how to interpret the + * contents of this opaque data. + */ } wmi_peer_vendor_cmd_fixed_param; +typedef wmi_peer_vendor_cmd_fixed_param wmi_vendor_peer_cmd_fixed_param; typedef enum { WMI_MLO_LINK_FORCE_ACTIVE = 1, /* Force specific links active */ @@ -40114,8 +44472,47 @@ typedef enum { WMI_MLO_LINK_FORCE_REASON_NEW_CONNECT = 1, /* Set force specific links because of new connection */ WMI_MLO_LINK_FORCE_REASON_NEW_DISCONNECT = 2, /* Set force specific links because of new dis-connection */ WMI_MLO_LINK_FORCE_REASON_LINK_REMOVAL = 3, /* Set force specific links because of AP-side link removal */ + WMI_MLO_LINK_FORCE_REASON_TDLS = 4, /* Set force specific links because of 11BE MLO TDLS setup/teardown */ + WMI_MLO_LINK_FORCE_REASON_REVERT_FAILURE = 5, /* Set force specific links for revert previous failed due to host reject */ } WMI_MLO_LINK_FORCE_REASON; +#define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_ACTIVE(mlo_flags) \ + WMI_GET_BITS(control_flags, 0, 1) +#define WMI_MLO_CONTROL_FLAGS_SET_OVERWRITE_FORCE_ACTIVE(mlo_flags, value) \ + WMI_SET_BITS(control_flags, 0, 1, value) +#define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_INACTIVE(mlo_flags) \ + WMI_GET_BITS(control_flags, 1, 1) +#define WMI_MLO_CONTROL_FLAGS_SET_OVERWRITE_FORCE_INACTIVE(mlo_flags, value) \ + WMI_SET_BITS(control_flags, 1, 1, value) +#define WMI_MLO_CONTROL_FLAGS_GET_DYNAMIC_FORCE_LINK_NUM(mlo_flags) \ + WMI_GET_BITS(control_flags, 2, 1) +#define WMI_MLO_CONTROL_FLAGS_SET_DYNAMIC_FORCE_LINK_NUM(mlo_flags, value) \ + WMI_SET_BITS(control_flags, 2, 1, value) + +/* + * This structure is used for passing wmi_mlo_control_flags. + * + * - When force_mode is WMI_MLO_LINK_FORCE_ACTIVE or + * WMI_MLO_LINK_FORCE_INACTIVE host can pass below control flags, + * to indicate if FW need to clear earlier force bitmap config. + * + * - When force mode is WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or + * WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM, host can pass below control flags, + * to indicate if FW need to use force link number instead of force link + * bitmap. + */ +typedef struct { + union { + struct { + A_UINT32 overwrite_force_active_bitmap:1, /* indicate overwrite all earlier force_active bitmaps */ + overwrite_force_inactive_bitmap:1, /* indicate overwrite all earlier force_inactive bitmaps */ + dynamic_force_link_num:1, /* indicate fw to use force link number instead of force link bitmap */ + unused: 29; + }; + A_UINT32 control_flags; + }; +} wmi_mlo_control_flags; + typedef struct wmi_mlo_link_set_active_cmd { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_set_active_cmd_fixed_param; */ @@ -40124,12 +44521,21 @@ typedef struct wmi_mlo_link_set_active_cmd A_UINT32 force_mode; /** reason of force link active / inactive, enum WMI_MLO_LINK_FORCE_REASON */ A_UINT32 reason; + /* indicate use vdev_id bitmap or link_id_bitmap */ + A_UINT32 use_ieee_link_id_bitmap; + + wmi_mac_addr ap_mld_mac_addr; + + wmi_mlo_control_flags ctrl_flags; /* The TLVs follows this structure: * wmi_mlo_set_active_link_number_param link_number_param[]; * Link number parameters, optional TLV. * Present when force type is WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or * WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM. * In other cases the length of array should be 0. + *--- + * If use_ieee_link_id_bitmap equals 0 vdev_id_bitmap[] & vdev_id_bitmap2[] + * are valid. * A_UINT32 vdev_id_bitmap[]; * Optional TLV, present when force type is WMI_MLO_LINK_FORCE_ACTIVE * or WMI_MLO_LINK_FORCE_INACTIVE or WMI_MLO_LINK_NO_FORCE, @@ -40141,6 +44547,18 @@ typedef struct wmi_mlo_link_set_active_cmd * For force mode WMI_MLO_LINK_FORCE_ACTIVE_INACTIVE vdev_id_bitmap2[] * carry the inactive vdev bitmap. * In other cases the length of the array should be 0. + *--- + * If use_ieee_link_id_bitmap equals 1 ieee_link_id_bitmap[] & + * ieee_link_id_bitmap2[] are valid. + * A_UINT32 ieee_link_id_bitmap[]; + * present for WMI_MLO_LINK_FORCE_ACTIVE + * or WMI_MLO_LINK_FORCE_INACTIVE or WMI_MLO_LINK_NO_FORCE + * or WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or + * WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM + * A_UINT32 ieee_link_id_bitmap2[]; + * For force mode WMI_MLO_LINK_FORCE_ACTIVE_INACTIVE ieee_link_id_bitmap2[] + * carry the inactive linkid bitmap. + * In other cases the length of the array should be 0. */ } wmi_mlo_link_set_active_cmd_fixed_param; @@ -40162,6 +44580,11 @@ typedef struct wmi_mlo_set_active_link_number_param } wmi_mlo_set_active_link_number_param; +typedef enum { + WMI_MLO_LINK_SET_ACTIVE_STATUS_SUCCESS = 0, + WMI_MLO_LINK_SET_ACTIVE_STATUS_HOST_REJECT = 1, +} WMI_MLO_LINK_SET_ACTIVE_STATUS; + typedef struct wmi_mlo_link_set_active_resp_event { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_set_active_resp_event_fixed_param; */ @@ -40170,9 +44593,24 @@ typedef struct wmi_mlo_link_set_active_resp_event /** Return status. 0 for success, non-zero otherwise */ A_UINT32 status; + /* indicate use vdev_id bitmap or link_id_bitmap */ + A_UINT32 use_ieee_link_id_bitmap; + + wmi_mac_addr ap_mld_mac_addr; + /* The TLVs follows this structure: + *--- + * If use_ieee_link_id_bitmap equals 0, vdev_bitmap[] are valid. * A_UINT32 force_active_vdev_bitmap[]; <-- current force active vdev. * A_UINT32 force_inactive_vdev_bitmap[]; <-- current force inactive vdevs + *--- + * If use_ieee_link_id_bitmap equals 1, ieee_link_id_bitmap[] are valid. + * A_UINT32 force_active_ieee_link_id_bitmap[]; + * A_UINT32 force_inactive_ieee_link_id_bitmap[]; + *--- + * current active ieee link id bitmap & inactive ieee link id bitmap + * A_UINT32 current_active_ieee_link_id_bitmap[]; + * A_UINT32 current_inactive_ieee_link_id_bitmap[]; */ } wmi_mlo_link_set_active_resp_event_fixed_param; @@ -40196,6 +44634,13 @@ typedef struct { A_UINT32 pdev_id; /** Return status. 0 for success, non-zero otherwise */ A_UINT32 status; + /** max_ml_peer_ids: + * Max number of ml_peerids across the SOC, Derived as + * max_mlo_peer * num chips. + * (Max_mlo_peer and num_chips are provided by Host Platform + * in QMI exchange). + */ + A_UINT32 max_ml_peer_ids; } wmi_mlo_setup_complete_event_fixed_param; typedef struct { @@ -40206,8 +44651,14 @@ typedef struct { } wmi_mlo_ready_cmd_fixed_param; typedef enum wmi_mlo_tear_down_reason_code_type { - WMI_MLO_TEARDOWN_SSR_REASON, - WMI_MLO_TEARDOWN_HOST_INITIATED_REASON, + WMI_MLO_TEARDOWN_REASON_SSR, + /* keep old name as alias for new name */ + WMI_MLO_TEARDOWN_SSR_REASON = WMI_MLO_TEARDOWN_REASON_SSR, + WMI_MLO_TEARDOWN_REASON_HOST_INITIATED, + /* keep old name as alias for new name */ + WMI_MLO_TEARDOWN_HOST_INITIATED_REASON = + WMI_MLO_TEARDOWN_REASON_HOST_INITIATED, + WMI_MLO_TEARDOWN_REASON_STANDBY_DOWN, } WMI_MLO_TEARDOWN_REASON_TYPE; typedef struct { @@ -40217,6 +44668,10 @@ typedef struct { A_UINT32 pdev_id; /** reason_code: of type WMI_TEARDOWN_REASON_TYPE */ A_UINT32 reason_code; + /* trigger_umac_reset : of type A_BOOL to indicate the umac reset for the partner chip. */ + A_UINT32 trigger_umac_reset; + /* erp_standby_mode : of type A_BOOL to indicate the chip is going to be active in ERP */ + A_UINT32 erp_standby_mode; } wmi_mlo_teardown_fixed_param; typedef struct { @@ -40228,6 +44683,27 @@ typedef struct { A_UINT32 status; } wmi_mlo_teardown_complete_fixed_param; +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_peer_recommended_links; */ + A_UINT32 tlv_header; + /** AID (association id) of this station */ + A_UINT32 assoc_id; + /** Request link id set to disable */ + A_UINT32 linkid_bitmap; +} wmi_mlo_peer_recommended_links; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_recommendation_fixed_param */ + A_UINT32 tlv_header; + /* unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* DTIM specified in units of num beacon intervals */ + A_UINT32 dtim_period; + /* The TLVs follows this structure: + * wmi_mlo_peer_recommended_links recommended_links[]; + */ +} wmi_mlo_link_recommendation_fixed_param; + #define WMI_TID_TO_LINK_MAP_TID_NUM_GET(_var) WMI_GET_BITS(_var, 0, 5) #define WMI_TID_TO_LINK_MAP_TID_NUM_SET(_var, _val) WMI_SET_BITS(_var, 0, 5, _val) @@ -40271,6 +44747,91 @@ typedef struct { A_UINT32 tid_to_link_map_info; } wmi_tid_to_link_map; +#define WMI_MAX_NUM_PREFERRED_LINKS 4 + +/* NOTE: + * wmi_peer_preferred_link_map will be deprecated and replaced + * by wmi_mlo_peer_link_control_param. + */ +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_preferred_link_map */ + A_UINT32 tlv_header; + + /* num_preferred_links: + * If it is 0, all links are equally preferred and which link to be used + * in each schedule is decided by FW. + */ + A_UINT32 num_preferred_links; + + /* [0] - highest preferred link, [1] - 2nd preferred link, etc. */ + A_UINT32 preferred_link_order[WMI_MAX_NUM_PREFERRED_LINKS]; + + /* expected_max_latency_ms: + * 0 - Expected Max Latency to be estimated in Firmware + * Non 0 - Firmware should try to achieve given max latency + * in first preferred link. + * If unable to meet in first preferred link, start scheduling + * in next preferred link and so on. + */ + A_UINT32 expected_max_latency_ms[WLAN_MAX_AC]; +} wmi_peer_preferred_link_map; + +#define WMI_MLO_PEER_LINK_CONTROL_PARAM_SET_TX_LINK_TUPLE_CONFIG(comp, value) \ + WMI_SET_BITS(comp, 0, 1, value) +#define WMI_MLO_PEER_LINK_CONTROL_PARAM_GET_TX_LINK_TUPLE_CONFIG(comp) \ + WMI_GET_BITS(comp, 0, 1) + +#define WMI_MLO_PEER_LINK_CONTROL_PARAM_SET_PREFERRED_LINK_CONFIG(comp, value) \ + WMI_SET_BITS(comp, 1, 1, value) +#define WMI_MLO_PEER_LINK_CONTROL_PARAM_GET_PREFERRED_LINK_CONFIG(comp) \ + WMI_GET_BITS(comp, 1, 1) + +#define WMI_MAX_NUM_MLO_LINKS 5 + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_preferred_link_map */ + A_UINT32 tlv_header; + + /** flags: + * Bit0 : tx_link_tuple enable/disable. + * When enabled, f/w picks the links in tx_link_tuple_bitmap + * for TX scheduling. + * Bit1 : preferred_link enable/disable. + * When enabled, f/w schedules the data on preferred link first. + * If it fails to deliver within a timeout, it additionally + * starts attempting TX on non-preferred links. + * Bit2-31 : reserved + */ + A_UINT32 flags; + + /* num_links: number of links present in link_priority_order array below. + * 0 - we dont have sorted list of link priority + * non zero - this should be the max number of links that the peer supports. + */ + A_UINT32 num_links; + + /* link_priority_order: + * [0] - ID of highest priority link, + * [1] - ID of 2nd highest priority link, etc. + */ + A_UINT32 link_priority_order[WMI_MAX_NUM_MLO_LINKS]; + + /* tx_link_tuple_bitmap: + * bitmap of indices within link_priority_order array that needs to be + * selected in the TX link tuple. + * FW will not attempt scheduling on a link if it is not part of the + * tx_link_tuple. + */ + A_UINT32 tx_link_tuple_bitmap; + + /* max_timeout_ms: applicable only when preferred_link is enabled + * 0 - max_timeout_ms to be estimated in Firmware + * Non 0 - value beyond which, firmware should additionally start + * scheduling on non preferred links + */ + A_UINT32 max_timeout_ms[WLAN_MAX_AC]; +} wmi_mlo_peer_link_control_param; + typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_tid_to_link_map_fixed_param */ A_UINT32 tlv_header; @@ -40280,9 +44841,20 @@ typedef struct { /** MLO Peer's current link MAC address */ wmi_mac_addr link_macaddr; + /** mapping_switch_time from the T2LM IE */ + A_UINT32 mapping_switch_time; + + /** expected_duration from the T2LM IE, in units of TUs */ + A_UINT32 expected_duration; + /** * Following this structure is the TLV: - * struct wmi_tid_to_link_map tid_to_link_map[]; + * - struct wmi_tid_to_link_map tid_to_link_map[]; + * - struct wmi_peer_preferred_link_map peer_preferred_link_map[]; + * Note - TLV array of peer_preferred_link_map has either 0 or 1 + * entries, not multiple entries. + * - struct wmi_mlo_peer_link_control_param[]; + * Note: can have 0 or 1 entry. */ } wmi_peer_tid_to_link_map_fixed_param; @@ -40310,6 +44882,22 @@ typedef enum { WMI_EXPECTED_DUR_EXPIRED, } WMI_MLO_TID_TO_LINK_MAP_STATUS; +#define WMI_BCAST_T2LM_MAX 16 /* max number of vdevs covered by T2LM stats */ +typedef struct { + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ctrl_path_t2lm_stats_struct + */ + A_UINT32 tlv_header; + /* + * The below arrays store per-vdev counters, and are indexed by vdev ID. + * The number of valid elements is min(WMI_BCAST_T2LM_MAX, num vdevs). + */ + A_UINT32 bcast_t2lm_wmi_cmd[WMI_BCAST_T2LM_MAX]; + A_UINT32 bcast_t2lm_wmi_evt_map_swt_tme_tsf[WMI_BCAST_T2LM_MAX]; + A_UINT32 bcast_t2lm_wmi_evt_map_swt_tme_exp[WMI_BCAST_T2LM_MAX]; + A_UINT32 bcast_t2lm_wmi_evt_exp_dur_exp[WMI_BCAST_T2LM_MAX]; +} wmi_ctrl_path_t2lm_stats_struct; + typedef struct{ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_ap_vdev_tid_to_link_map_evt_fixed_param */ A_UINT32 tlv_header; @@ -40334,6 +44922,9 @@ typedef struct{ #define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_DUR_TIME_GET(_var) WMI_GET_BITS(_var, 4, 1) #define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_DUR_TIME_SET(_var, _val) WMI_SET_BITS(_var, 4, 1, _val) +#define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_GET(_var) WMI_GET_BITS(_var, 5, 1) +#define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_SET(_var, _val) WMI_SET_BITS(_var, 5, 1, _val) + #define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_GET(_var) WMI_GET_BITS(_var, 8, 8) #define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_SET(_var, _val) WMI_SET_BITS(_var, 8, 8, _val) @@ -40414,7 +45005,12 @@ typedef struct { * // 0 - Expected Duration Field * // not Present * - * reserved:3 + * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_GET + * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_SET + * link_mapping_size:1 // 1 - Link Mapping Size 1 Octets + * // 0 - Link Mapping Size 2 Octets + * + * reserved:2 * * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_GET / * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_SET @@ -40694,6 +45290,13 @@ typedef struct { A_UINT32 vdev_id; /** Average RSSI value of Data Frames */ A_INT32 avg_rssi_data_dbm; + /** rx_vht_sgi: + * Short guard interval state of Data frames obtaining from rx PPDU TLV + * of VHTSIGA buf. + * 0: Default (No sgi set) + * 1: sgi set + */ + A_UINT32 rx_vht_sgi; } wmi_vdev_smart_monitor_event_fixed_param; typedef struct { @@ -40772,6 +45375,15 @@ typedef struct { A_UINT32 cust_bdf_ver_minor; } wmi_cust_bdf_version_capabilities; +enum WMI_CODEL_ENABLE_VALUES { + WMI_CODEL_DISABLED, + WMI_CODEL_ENABLED, + /* WMI_CODEL_DEBUG: + * partly enabled – track interval and check target, but don’t drop + */ + WMI_CODEL_DEBUG, +}; + typedef enum { WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_MIN_THRUPUT = 0, WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_MAX_THRUPUT = 0xffffffff, @@ -40782,8 +45394,15 @@ typedef enum { WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_PRIORITY = 0, WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_TID = 0xffffffff, WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_MSDU_LOSS_RATE = 0, + WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_DISABLED_SCHED_MODE = 0, + WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_CODEL_ENABLED = WMI_CODEL_DISABLED, + WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_CODEL_LATENCY_TARGET_MS = 0xffffffff, + WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_CODEL_INTERVAL_MS = 0xffffffff, } WMI_SAWF_SVC_CLASS_PARAM_DEFAULTS; +#define WMI_CODEL_INTERVAL_MAX_MS 0x0000ffff +#define WMI_CODEL_LATENCY_TARGET_MAX_MS 0x00003fff + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sawf_svc_class_cfg_cmd_fixed_param */ A_UINT32 svc_class_id; /* which service class is being configured */ @@ -40863,6 +45482,44 @@ typedef struct { * since 100 / 1000000 = 1 / 10000. */ A_UINT32 msdu_loss_rate_ppm; + /* + * The disabled DL and UL scheduler modes bitmap. + * + * Each bit in the "disabled_sched_modes" bitmap indicates whether a + * specific scheduler mode may be selected by the fast loop scheduler. A + * "1" bit indicates that mode is disabled, and a "0" bit indicates the + * mode is enabled. + * + * The WMI_SCHED_MODE_FLAGS enum defines the bit positions for each mode. + */ + A_UINT32 disabled_sched_modes; + + A_UINT32 codel_enabled; /* contains a WMI_CODEL_ENABLE_VALUES enum value */ + /* codel_latency_target_ms: + * The codel_latency_target_ms field specifies the latency target for + * MSDU queues belonging to this service class. + * The latency of each such MSDU queue will periodically be checked + * (with the periodicity controlled by the code_interval_ms parameter). + * If the MSDU queue's latency is above this target latency, a MSDU will + * be dropped from the head of the queue, to attempt to get the flow's + * producer to scale down its rate of MSDU production. + * This value should be roughly 10% to 30% of the codel_interval_ms value. + * This value must be <= WMI_CODEL_LATENCY_TARGET_MAX_MS (or must equal + * WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_CODEL_LATENCY_TARGET_MS). + */ + A_UINT32 codel_latency_target_ms; + /* codel_interval_ms: + * The codel_interval_ms field specifies the baseline interval between + * successive checks that a given MSDU queue's latency is under the + * CoDel target latency. + * If in a given interval a MSDU queue has a latency exceeding the target, + * the duration of the subsequent interval for that MSDU queue will be + * reduced. The interval will get reset to the baseline interval when + * the MSDU queue's latency is again under the CoDel target latency. + * This value must be <= WMI_CODEL_INTERVAL_MAX_MS (or must equal + * WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_CODEL_INTERVAL_MS). + */ + A_UINT32 codel_interval_ms; } wmi_sawf_svc_class_cfg_cmd_fixed_param; typedef struct { @@ -40910,6 +45567,40 @@ typedef struct { A_UINT32 pn_rx_filter; } wmi_vdev_pn_mgmt_rx_filter_cmd_fixed_param; /* Filter for Neighbor Rx Packets */ +typedef struct { + A_UINT32 tlv_header; + /* egid_info: + * Identify which ESL group is active and the duty cycle configured + * for each group. + * This is a 128-bit bitmap to represent 16 ESL sets, with each set + * having 8 members. + * For a given set, the 1-values within the 8-bit bitmap identify + * which groups are active. The number of active groups within each + * set of 8 indirectly determines the WLAN/BT duty cycle: + * number of 1-bits | + * within 8-bit bitmap | WLAN / BT duty cycle + * --------------------+---------------- + * 0 | 100 ms WLAN + * 1 | 87.5 ms WLAN, 12.5 ms BT + * 2 | 75 ms WLAN, 25 ms BT + * 3 | 62.5 ms WLAN, 37.5 ms BT + * 4 | 50 ms WLAN, 50 ms BT + * 5 | 37.5 ms WLAN, 62.5 ms BT + * 6 | 25 ms WLAN, 75 ms BT + * 7 | 12.5 ms WLAN, 87.5 ms BT + * 8 | 100 ms BT + * The lowest bits in the bitmap represent the highest ESL groups, + * E.g. bitmap bit 0 corresponds to ESL group 127, bit 1 corresponds + * to ESL group 126, bit 7 corresponds to ESL group 120, bit 8 + * corresponds to ESL group 119, etc. + * + * So for example, if the lowest 8 bits of egid_info are 0x07, this + * indicates that groups 125-127 are active and 120-124 are inactive, + * and that the duty cycle is 62.5 ms WLAN + 37.5 ms BT. + */ + A_UINT32 egid_info[4]; +} wmi_esl_egid_cmd_fixed_param; + #define WMI_RTT_PASN_PEER_CREATE_SECURITY_MODE_GET(flag) WMI_GET_BITS(flag, 0, 2) #define WMI_RTT_PASN_PEER_CREATE_SECURITY_MODE_SET(flag,val) WMI_SET_BITS(flag, 0, 2, val) #define WMI_RTT_PASN_PEER_CREATE_FORCE_SELF_MAC_USE_GET(flag) WMI_GET_BITS(flag, 2, 1) @@ -41167,6 +45858,965 @@ typedef struct { */ } wmi_mlo_link_removal_cmd_fixed_param; +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_per_peer_sched_mode_disable */ + + /* Peer MAC Address */ + wmi_mac_addr peer_macaddr; + + /* + * The disabled DL and UL scheduler modes bitmap. + * + * This command is not supported in STA mode. + * + * A value of 1 in a given bit position disables the corresponding mode, + * and a value of 0 enables the mode. The WMI_SCHED_MODE_FLAGS enum defines + * the bit positions for each mode. + * + * A single 32 bit value is used to store the following configuration + * bitmap. + * + * bit | sched mode + * --------------- + * 0 | DL MU-MIMO + * 1 | UL MU-MIMO + * 2 | DL OFDMA + * 3 | UL OFDMA + * 4..31 | RESERVED + */ + A_UINT32 disabled_sched_modes; +} wmi_per_peer_sched_mode_disable; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_sched_mode_disable_fixed_param */ + A_UINT32 pdev_id; + /* The TLVs for each peer follows: + * wmi_per_peer_sched_mode_disable per_peer_sched_mode_disable[]; + */ +} wmi_peer_sched_mode_disable_fixed_param; + +/** Coordinated-AP TDMA **/ + +#define WMI_TDMA_MAX_ACTIVE_SCHEDULES 10 + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdma_schedule_request_cmd_fixed_param **/ + /** pdev_id + * PDEV ID for identifying the MAC for which this schedule + * is being requested. + */ + A_UINT32 pdev_id; + /** schedule_type + * 0 = Reserved + * 1 = Restricted + * UINT32_MAX = Cancel all TDMA schedules and ignore other parameters below. + */ + A_UINT32 schedule_type; + /** schedule_handle_id + * Unique ID to identify this TDMA schedule + */ + A_UINT32 schedule_handle_id; + /** owner_bssid + * The BSSID this TDMA schedule is reserved for + */ + wmi_mac_addr owner_bssid; + /** start_time_tsf_low + * Lower 32-bits of Synchronized Start time for the first busy slot + * in this TDMA schedule. + * It should be a PMM global FW TSF reference + */ + A_UINT32 start_time_tsf_low; + /** start_time_tsf_high + * Higher 32-bits of Synchronized Start time for the first busy slot + * in this TDMA schedule. + * It should be a PMM global FW TSF reference + */ + A_UINT32 start_time_tsf_high; + /** num_busy_slots + * Number of busy periods in this schedule + */ + A_UINT32 num_busy_slots; + /** busy_slot_dur_ms + * The fixed duration of each busy slot in milliseconds + */ + A_UINT32 busy_slot_dur_ms; + /** busy_slot_intvl_ms + * The fixed interval between the start of two consecutive busy slots + * in milliseconds. + */ + A_UINT32 busy_slot_intvl_ms; + /** edca_params_valid + * Indicates whether the following EDCA fields aifsn, ecwmin, ecwmax + * are valid or not + * 1 = Valid. 0 = Not Valid. + */ + A_UINT32 edca_params_valid; + /** aifsn + * Arbitration inter frame spacing number for this schedule type. + * Range: 2-15. + * For voice, video, best-effort, background ACs + */ + A_UINT32 aifsn[WMI_AC_MAX]; + /** ecwmin + * Exponent form of Contention Window minimum value for this schedule type. + * Range: 2 - 1024. + * For voice, video, best-effort, background ACs + */ + A_UINT32 ecwmin[WMI_AC_MAX]; + /** ecwmax + * Exponent form of Contention Window maximum value for this schedule type. + * Range: 2 - 1024. + * For voice, video, best-effort, background ACs + */ + A_UINT32 ecwmax[WMI_AC_MAX]; +} wmi_tdma_schedule_request_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table _fixed_param */ + A_UINT32 pdev_id; + /* freq_band: + * Indicates the intended FreqBand for updating targetPowerR2PTable. + * 0: 5G + * 1: 2G + * 2: 6G + */ + A_UINT32 freq_band; + /* sub_band: + * Denotes band defined in targetPowerR2PFreqRangexG BDF fields. + * Valid values for each target is listed below + * For 11AX targets, + * 2G - 0 + * 5G/6G - 0/1/2 + * + * For 11BE targets, + * 2G - 0 + * 5G/6G - 0/1 + */ + A_UINT32 sub_band; + /* is_ext: + * Applicable only for 11BE targets + * 0 - Default targetPowerR2PTable + * 1 - To update targetPowerR2PTable in extension fields + * For 11AX targets, value is expected to be 0. + */ + A_UINT32 is_ext; + A_UINT32 target_type; /* 0 - IPQ95xx, 1 - QCN90xx, 0x10 - QCN92xx */ + A_UINT32 r2p_array_len; /* length of targetPowerR2PTable */ + /* end_of_r2ptable_update: + * This field can be used to indicate FW to trigger update of SW structures + * once user has updated for all the sub-bands of the Frequency band. + * This would be used when there are multiple sub-bands. + */ + A_UINT32 end_of_r2ptable_update; +/* + * Following this structure is the TLV containing targetPowerR2PTablexG + * of type INT8 and with a unit of 0.25dBm. + */ +} wmi_pdev_set_tgtr2p_table_cmd_fixed_param; + +typedef enum { + WMI_PDEV_TGTR2P_SUCCESS = 0, + WMI_PDEV_TGTR2P_SUCCESS_WAITING_FOR_END_OF_UPDATE, + WMI_PDEV_TGTR2P_ERROR_INVALID_FREQ_BAND, + WMI_PDEV_TGTR2P_ERROR_INVALID_SUB_BAND, + WMI_PDEV_TGTR2P_ERROR_EXTENSION_FIELDS_NOT_ENABLED_IN_BDF, + WMI_PDEV_TGTR2P_ERROR_INVALID_TARGET_TPYE, + WMI_PDEV_TGTR2P_ERROR_R2P_ARRAY_LEN_MISMATCH, +} wmi_pdev_set_tgtr2p_event_status_type; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_event_fixed_param */ + + /* status: + * enum wmi_pdev_set_tgtr2p_event_status_type to indicate the status + * code/result + */ + A_UINT32 status; + A_UINT32 pdev_id; /* to identify for which pdev the response is received */ +} wmi_pdev_set_tgtr2p_table_event_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_vdev_get_link_info_cmd_fixed_param */ + A_UINT32 vdev_id; + wmi_mac_addr mld_macaddr; /* MLD MAC address */ +} wmi_mlo_vdev_get_link_info_cmd_fixed_param; + +typedef enum { + WMI_LINK_INFO_EVENT_SUCCESS = 0, + + /* reject due to common failure reason */ + WMI_LINK_INFO_EVENT_REJECT_FAILURE, + + /* reject as vdev is not up */ + WMI_LINK_INFO_EVENT_REJECT_VDEV_NOT_UP, + + /* reject as roaming is in progress */ + WMI_LINK_INFO_EVENT_REJECT_ROAMING_IN_PROGRESS, + + /* reject as it's not MLO connection */ + WMI_LINK_INFO_EVENT_REJECT_NON_MLO_CONNECTION, +} wmi_mlo_vdev_link_info_event_status_type; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info_event_fixed_param */ + + /* status: + * enum wmi_mlo_vdev_link_info_event_status_type to indicate the status + */ + A_UINT32 status; + + /* vdev_id: + * unique id identifying the VDEV, generated by the caller + */ + A_UINT32 vdev_id; + + wmi_mac_addr mld_macaddr; /* MLD MAC address */ + + /* hw_mode_index: + * current hardware mode index, see soc_hw_mode_t for values + */ + A_UINT32 hw_mode_index; +} wmi_mlo_vdev_link_info_event_fixed_param; + +#define WMI_MLO_VDEV_LINK_INFO_GET_VDEVID(link_info) WMI_GET_BITS(link_info, 0, 8) +#define WMI_MLO_VDEV_LINK_INFO_SET_VDEVID(link_info, value) WMI_SET_BITS(link_info, 0, 8, value) +#define WMI_MLO_VDEV_LINK_INFO_GET_LINKID(link_info) WMI_GET_BITS(link_info, 8, 8) +#define WMI_MLO_VDEV_LINK_INFO_SET_LINKID(link_info, value) WMI_SET_BITS(link_info, 8, 8, value) +#define WMI_MLO_VDEV_LINK_INFO_GET_LINK_STATUS(link_info) WMI_GET_BITS(link_info, 16, 2) +#define WMI_MLO_VDEV_LINK_INFO_SET_LINK_STATUS(link_info, value) WMI_SET_BITS(link_info, 16, 2, value) + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info */ + union { + struct { + A_UINT32 vdev_id:8, /* vdev id for this link */ + link_id:8, /* link id defined as in 802.11 BE spec. */ + link_status:2, /* link_status - 0: inactive, 1: active */ + reserved:14; + }; + A_UINT32 link_info; + }; + A_UINT32 chan_freq; /* Channel frequency in MHz */ +} wmi_mlo_vdev_link_info; + +/* Manual UL OFDMA trigger frame data structures */ + +typedef enum { + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_NONE, + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_RESP, /* response timeout, mismatch, + * BW mismatch, mimo ctrl mismatch, + * CRC error.. */ + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_FILT, /* blocked by tx filtering */ + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_FIFO, /* fifo, misc errors in HW */ + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_SWABORT, /* software initiated abort + * (TX_ABORT) */ + + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_MAX = 0xff, + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_INVALID = + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_MAX +} wmi_ul_ofdma_manual_trig_txerr_t; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param */ + A_UINT32 tlv_header; + + /* VDEV identifier */ + A_UINT32 vdev_id; + + /* To indicate whether feedback event is for SU (0) or MU trigger (1) */ + A_UINT32 feedback_trig_type; + + /* Feedback Params */ + A_UINT32 curr_su_manual_trig_count; + A_UINT32 remaining_su_manual_trig; + A_UINT32 remaining_mu_trig_peers; + A_UINT32 manual_trig_status; /* holds a wmi_ul_ofdma_manual_trig_txerr_t */ + + /** + * This TLV is followed by TLVs below: + * wmi_mac_addr peer_macaddr[]; + * Array length corresponds to the number of triggered peers + */ +} wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param */ + A_UINT32 tlv_header; + + /* VDEV identifier */ + A_UINT32 vdev_id; + + /* Configurable Parameters for manual UL OFDMA Multi-User Trigger frame */ + A_UINT32 manual_trig_preferred_ac; + /** + * This TLV is followed by TLVs below: + * wmi_mac_addr peer_macaddr[]; + * The array has one element for each peer to be included in the + * manually-triggered UL MU transmission. + */ +} wmi_vdev_set_manual_mu_trig_cmd_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_manual_su_trig_cmd_fixed_param */ + A_UINT32 tlv_header; + + /* VDEV identifier */ + A_UINT32 vdev_id; + + /* Configurable Parameters for manual UL OFDMA Single-User Trigger frame */ + wmi_mac_addr peer_macaddr; + A_UINT32 manual_trig_preferred_ac; + A_UINT32 num_su_manual_trig; + A_UINT32 manual_trig_length; + A_UINT32 manual_trig_mcs; + A_UINT32 manual_trig_nss; + A_INT32 manual_trig_target_rssi; /* units = dBm */ +} wmi_vdev_set_manual_su_trig_cmd_fixed_param; + + +#define CQI_UPLOAD_META_DATA_NC_IDX(idx) \ + (MAX_NUM_CQI_USERS_IN_STANDALONE_SND + (idx * 2)) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_ASNR_LENGTH(asnr_params, value) \ + WMI_SET_BITS(asnr_params, 0, 16, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_ASNR_LENGTH(asnr_params) \ + WMI_GET_BITS(asnr_params, 0, 16) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_ASNR_OFFSET(asnr_params, value) \ + WMI_SET_BITS(asnr_params, 16, 16, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_ASNR_OFFSET(asnr_params) \ + WMI_GET_BITS(asnr_params, 16, 16) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_DSNR_LENGTH(dsnr_params, value) \ + WMI_SET_BITS(dsnr_params, 0, 16, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_DSNR_LENGTH(dsnr_params) \ + WMI_GET_BITS(dsnr_params, 0, 16) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_DSNR_OFFSET(dsnr_params, value) \ + WMI_SET_BITS(dsnr_params, 16, 16, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_DSNR_OFFSET(dsnr_params) \ + WMI_GET_BITS(dsnr_params, 16, 16) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_FB_PARAMS_NC(fb_params, value) \ + WMI_SET_BITS(fb_params, 0, 2, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_FB_PARAMS_NC(fb_params) \ + WMI_GET_BITS(fb_params, 0, 2) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_FB_PARAMS_NSS_NUM(fb_params, value) \ + WMI_SET_BITS(fb_params, 2, 2, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_FB_PARAMS_NSS_NUM(fb_params) \ + WMI_GET_BITS(fb_params, 2, 2) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_DDR_BUF_IDX(ddr_buffer_idx, value) \ + WMI_SET_BITS(ddr_buffer_idx, 4, 2, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_DDR_BUF_IDX(ddr_buffer_idx) \ + WMI_GET_BITS(ddr_buffer_idx, 4, 2) + + +#define WMI_SET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params, value) \ + WMI_SET_BITS(snd_params, 0, 2, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params) \ + WMI_GET_BITS(snd_params, 0, 2) + +#define WMI_SET_STANDALONE_SOUND_PARAMS_NG(snd_params, value) \ + WMI_SET_BITS(snd_params, 2, 2, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_NG(snd_params) \ + WMI_GET_BITS(snd_params, 2, 2) + +#define WMI_SET_STANDALONE_SOUND_PARAMS_CB(snd_params, value) \ + WMI_SET_BITS(snd_params, 4, 1, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_CB(snd_params) \ + WMI_GET_BITS(snd_params, 4, 1) + +#define WMI_SET_STANDALONE_SOUND_PARAMS_BW(snd_params, value) \ + WMI_SET_BITS(snd_params, 5, 3, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_BW(snd_params) \ + WMI_GET_BITS(snd_params, 5, 3) + +#define WMI_SET_STANDALONE_SOUND_PARAMS_CQI_TYPE(snd_params, value) \ + WMI_SET_BITS(snd_params, 8, 1, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_CQI_TYPE(snd_params) \ + WMI_GET_BITS(snd_params, 8, 1) + +#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_SET_FB_PARAMS_IS_VALID(fb_params_cqi, value, idx) \ + WMI_SET_BITS(fb_params_cqi, idx, 1, value) +#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_GET_FB_PARAMS_IS_VALID(fb_params_cqi, idx) \ + WMI_GET_BITS(fb_params_cqi, idx, 1) + +#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_SET_FB_PARAMS_NC(fb_params_cqi, value, idx) \ + WMI_SET_BITS(fb_params_cqi, CQI_UPLOAD_META_DATA_NC_IDX(idx), 2, value) +#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_GET_FB_PARAMS_NC(fb_params_cqi, idx) \ + WMI_GET_BITS(fb_params_cqi, CQI_UPLOAD_META_DATA_NC_IDX(idx), 2) + + +typedef enum _WMI_STANDALONE_SOUND_STATUS_T { + WMI_STANDALONE_SOUND_STATUS_OK, + WMI_STANDALONE_SOUND_STATUS_ERR_NUM_PEERS_EXCEEDED, + WMI_STANDALONE_SOUND_STATUS_ERR_NG_INVALID, + WMI_STANDALONE_SOUND_STATUS_ERR_NUM_REPEAT_EXCEEDED, + WMI_STANDALONE_SOUND_STATUS_ERR_PEER_DOESNOT_SUPPORT_BW, + WMI_STANDALONE_SOUND_STATUS_ERR_INVALID_PEER, + WMI_STANDALONE_SOUND_STATUS_ERR_INVALID_VDEV, + WMI_STANDALONE_SOUND_STATUS_ERR_PEER_DOES_NOT_SUPPORT_MU_FB, + WMI_STANDALONE_SOUND_STATUS_ERR_DMA_NOT_CONFIGURED, + WMI_STANDALONE_SOUND_STATUS_ERR_COMPLETE_FAILURE, +} WMI_STANDALONE_SOUND_STATUS_T; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dma_buf_release_cv_upload_meta_data */ + /** Set if the CV is valid */ + A_UINT32 is_valid; + /** Feedback type */ + A_UINT32 fb_type; + /** + * [15:0] ASNR length + * [31:16] ASNR offset + */ + A_UINT32 asnr_params; + /** + * [15:0] DSNR length + * [31:16] DSNR offset + */ + A_UINT32 dsnr_params; + /** Peer mac address */ + wmi_mac_addr peer_mac_address; + /** fb_params: + * [1:0] Nc + * Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_FB_PARAMS_NC + * [3:2] nss_num + * Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_FB_PARAMS_NSS_NUM + * [5:4] ddr_buffer_idx + * Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_DDR_BUF_IDX + */ + A_UINT32 fb_params; +} wmi_dma_buf_release_cv_upload_meta_data; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data */ + A_UINT32 tlv_header; + + /** + * [15:0] ASNR length + * [31:16] ASNR offset + */ + A_UINT32 asnr_params; + + /** Peer mac address */ + wmi_mac_addr peer_mac_address[MAX_NUM_CQI_USERS_IN_STANDALONE_SND]; + + /** + * [0] is_user0_valid + * [1] is_user1_valid + * [2] is_user2_valid + * [4:3] User0_Nc + * [6:5] User1_Nc + * [8:7] User2_Nc + */ + A_UINT32 fb_params_cqi : 9, + reserved : 23; +} wmi_dma_buf_release_cqi_upload_meta_data; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param */ + /** vdev identifier */ + A_UINT32 vdev_id; + /** sounding_params: + * [1:0] Feedback type + * [3:2] Ng + * [4] Codebook + * [7:5] BW + * 0 = 20 MHz + * 1 = 40 MHz + * 2 = 80 MHz + * 3 = 160 MHz + * 4 = 320 MHz + * [8] Triggered/Non-Triggered CQI + * [31:9] Reserved + */ + A_UINT32 sounding_params; + /** The number of sounding repeats */ + A_UINT32 num_sounding_repeats; + /** + * TLV (tag length value) parameters follow the + * structure. The TLV's are: + * wmi_mac_addr peer_list[num_peers]; + */ +} wmi_standalone_sounding_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param */ + /** vdev identifier */ + A_UINT32 vdev_id; + /** status: + * standalone sounding command status - + * refer to WMI_STANDALONE_SOUND_STATUS_T + */ + A_UINT32 status; + /** number of CV buffers uploaded */ + A_UINT32 buffer_uploaded; + /** TLV (tag length value) parameters follow the + * structure. The TLV's are: + * A_UINT32 snd_failed[num_sounding_repeats]; + * snd_failed[] array's elements hold the number of failures + * for each sounding. + */ +} wmi_standalone_sounding_evt_fixed_param; + +typedef struct { + /* + * TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param + */ + A_UINT32 tlv_header; + /* pdev_id for identifying the MAC */ + A_UINT32 pdev_id; + /* + * rf_path : + * 0 - primary RF path + * 1 - secondary RF path + */ + A_UINT32 rf_path; +} wmi_pdev_set_rf_path_cmd_fixed_param; + +typedef struct { + /* + * TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_event_fixed_param + */ + A_UINT32 tlv_header; + /* pdev_id for identifying the MAC */ + A_UINT32 pdev_id; + /* + * rf_path : + * 0 - primary RF path + * 1 - secondary RF path + */ + A_UINT32 rf_path; + /* + * status : + * TRUE (0) - for recieved and cache the value in FW + * FALSE (1) : + * a. pdev_id for which secondary RF path is not available + * b. caching of the rf_path got failed in FW + */ + A_UINT32 status; +} wmi_pdev_set_rf_path_event_fixed_param; + +#define WMI_SET_RX_PEER_STATS_RESP_TYPE(rx_params, value) \ + WMI_SET_BITS(rx_params, 0, 1, value) +#define WMI_GET_RX_PEER_STATS_RESP_TYPE(rx_params) \ + WMI_GET_BITS(rx_params, 0, 1) + +#define WMI_SET_RX_PEER_STATS_MCS(rx_params, value) \ + WMI_SET_BITS(rx_params, 1, 5, value) +#define WMI_GET_RX_PEER_STATS_MCS(rx_params) \ + WMI_GET_BITS(rx_params, 1, 5) + +#define WMI_SET_RX_PEER_STATS_NSS(rx_params, value) \ + WMI_SET_BITS(rx_params, 6, 4, value) +#define WMI_GET_RX_PEER_STATS_NSS(rx_params) \ + WMI_GET_BITS(rx_params, 6, 4) + +#define WMI_SET_RX_PEER_STATS_GI_LTF_TYPE(rx_params, value) \ + WMI_SET_BITS(rx_params, 10, 4, value) +#define WMI_GET_RX_PEER_STATS_GI_LTF_TYPE(rx_params) \ + WMI_GET_BITS(rx_params, 10, 4) + +typedef enum { + WMI_PEER_RX_RESP_SU = 0, + WMI_PEER_RX_RESP_MIMO = 1, + WMI_PEER_RX_RESP_OFDMA = 2, +} WMI_PEER_RX_RESP_TYPE; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo */ + A_UINT32 tlv_header; + + /* Peer mac address */ + wmi_mac_addr peer_macaddr; + + /* Per peer RX parameters */ + /* [0] - Flag to indicate if peer responded with QoS Data or QoS NULL. + * 0 -> indicates QoS NULL, 1-> indicates QoS Data response + * [5:1] - MCS - Peer response MCS + * [9:6] - NSS - Peer response NSS + * [13:10] - GI LTF Type - Peer response GI/LTF type + * 0 => gi == GI_1600 && ltf == 1x LTF + * 1 => gi == GI_1600 && ltf == 2x LTF + * 2 => gi == GI_3200 && ltf == 4x LTF + * [31:14] - Reserved + */ + A_UINT32 rx_peer_stats; + + /* Peer response per chain RSSI */ + A_INT32 peer_per_chain_rssi[WMI_MAX_CHAINS]; +} wmi_manual_ul_ofdma_trig_rx_peer_userinfo; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param */ + A_UINT32 tlv_header; + + A_UINT32 vdev_id; /* VDEV identifier */ + + /* combined_rssi: + * RX Combined RSSI in dBm + * Value indicates the average RSSI per 20MHz by averaging the total RSSI + * across entire BW for each OFDMA STA + */ + A_INT32 combined_rssi; + + /* rx_ppdu_resp_type: + * RX PPDU Response Type + * Refer WMI_PEER_RX_RESP_TYPE for possible values + */ + A_UINT32 rx_ppdu_resp_type; + + /* rx_resp_bw: + * RX response bandwidth + * 0 = 20 MHz + * 1 = 40 MHz + * 2 = 80 MHz + * 3 = 160 MHz + * 4 = 320 MHz + */ + A_UINT32 rx_resp_bw; + + /** + * This TLV is followed by TLVs below: + * wmi_manual_ul_ofdma_trig_rx_peer_userinfo rx_peer_userinfo[] + * TLV length specified by number of peer responses for manual + * UL OFDMA trigger + */ +} wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param; + +typedef enum _WMI_VDEV_PAUSE_TYPE +{ + WMI_VDEV_PAUSE_TYPE_UNKNOWN = 0, + WMI_VDEV_PAUSE_TYPE_MLO_LINK = 1, + WMI_VDEV_PAUSE_TYPE_TX = 2, +} WMI_VDEV_PAUSE_TYPE; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + /** type of pause, refer to WMI_VDEV_PAUSE_TYPE */ + A_UINT32 pause_type; + /** duration of pause, in unit of ms */ + A_UINT32 pause_dur_ms; +} wmi_vdev_pause_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; + A_UINT32 ieee_link_id; /* key to identify a link */ + wmi_channel wmi_chan; +} wmi_mlo_link_bss_param; + +typedef struct { + A_UINT32 tlv_header; + wmi_mac_addr ap_mld_macaddr; + + /* max num of active links recommended by AP or applications */ + A_UINT32 recommended_max_num_simultaneous_links; + + /* + * The TLVs listed below follow this fixed_param TLV: + * wmi_mlo_link_bss_param link_bss_params[]: + * an array of links to be updated + */ +} wmi_mlo_set_link_bss_params_cmd_fixed_param; + +typedef enum _WMI_LINK_SWITCH_REASON{ + WMI_MLO_LINK_SWITCH_REASON_RSSI_CHANGE = 1, + WMI_MLO_LINK_SWITCH_REASON_LOW_QUALITY = 2, + WMI_MLO_LINK_SWITCH_REASON_C2_CHANGE = 3, + WMI_MLO_LINK_SWITCH_REASON_HOST_FORCE = 4, + WMI_MLO_LINK_SWITCH_REASON_T2LM = 5, + WMI_MLO_LINK_SWITCH_REASON_MAX, +} WMI_LINK_SWITCH_REASON; + +typedef struct { + A_UINT32 tlv_header; + + A_UINT32 vdev_id; /*the vdev id assigned to curr_ieee_link_id*/ + A_UINT32 curr_ieee_link_id; /*current link id on above vdev_id*/ + A_UINT32 new_ieee_link_id; /*new link id on above vdev_id*/ + A_UINT32 new_primary_freq; /*primay_freq for the new link on the vdev, in units of MHZ*/ + A_UINT32 new_phymode; /*phymode for the new link on the vdev, see WLAN_PHY_MODE for definitions*/ + A_UINT32 reason; /*see WMI_LINK_SWITCH_REASON for definition*/ +} wmi_mlo_link_switch_req_evt_fixed_param; + +typedef enum _WMI_LINK_SWITCH_CNF_REASON{ + WMI_MLO_LINK_SWITCH_CNF_REASON_BSS_PARAMS_CHANGED = 1, + WMI_MLO_LINK_SWITCH_CNF_REASON_CONCURRECNY_CONFLICT = 2, + WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_INTERNAL_ERROR = 3, + WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_RESTORE_FORCE = 4, + WMI_MLO_LINK_SWITCH_CNF_REASON_MAX, +} WMI_LINK_SWITCH_CNF_REASON; + +typedef enum _WMI_LINK_SWITCH_CNF_STATUS{ + WMI_MLO_LINK_SWITCH_CNF_STATUS_ACCEPT = 0, + WMI_MLO_LINK_SWITCH_CNF_STATUS_REJECT = 1, +} WMI_LINK_SWITCH_CNF_STATUS; + +typedef struct { + A_UINT32 tlv_header; + + A_UINT32 vdev_id; + A_UINT32 status; /* see definition of WMI_LINK_SWITCH_CNF_STATUS */ + A_UINT32 reason; /* see definition of WMI_LINK_SWITCH_CNF_REASON */ + +/* + * The following optional TLVs may follow this fixed_praam TLV, + * depending on the value of the reason field. + * + * wmi_mlo_link_set_active_cmd_fixed_param set_link_params[]; + * The set_link_params array has one element when reason is + * WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_RESTORE_FORCE and + * use_ieee_link_id_bitmap should always be filled with 1. + * In other cases the length of the set_link_params array shall be 0. + * + * wmi_mlo_set_active_link_number_param link_number_param[]; + * Link number parameters, optional TLV. + * Present when force type is WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or + * WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM. + * In other cases the length of array shall be 0. + * + * A_UINT32 ieee_link_id_bitmap[]; + * present for WMI_MLO_LINK_FORCE_ACTIVE + * or WMI_MLO_LINK_FORCE_INACTIVE or WMI_MLO_LINK_NO_FORCE + * or WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or + * WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM + * In other cases the length of array shall be 0. + * + * A_UINT32 ieee_link_id_bitmap2[]; + * For force mode WMI_MLO_LINK_FORCE_ACTIVE_INACTIVE ieee_link_id_bitmap2[] + * carries the inactive linkid bitmap. + * In other cases the length of the array shall be 0. + */ +} wmi_mlo_link_switch_cnf_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param */ + A_UINT32 link_state_switch_count; /* Number of link state switch event pending, MAX 5 iteration */ +} wmi_mlo_link_state_switch_req_evt_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_trigger_reason_tlv_param */ + A_UINT32 cur_active_ieee_bitmap; /* current active ieee linkbitmap */ + A_UINT32 prev_active_ieee_bitmap; /* previous active iee linkbitmap */ + A_UINT32 host_ref_fw_timestamp_ms; /* fw time stamp on refrence of TIME_STAMP_SYNC_CMD */ + A_UINT32 reason_code; /* reason for link state switch trigger - + * refer to WMI_LINK_STATE_SWITCH_REASON + */ + wmi_mac_addr ml_bssid; /* mac address of mld device */ +} wmi_mlo_link_state_switch_trigger_reason; + +typedef enum _WMI_LINK_STATE_SWITCH_REASON { + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_VDEV_READY = 0, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_ULL_MODE = 1, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_T2LM_ENABLED = 2, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_T2LM_DISABLED = 3, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_FORCE_ENABLED = 4, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_FORCE_DISABLED = 5, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_LINK_QUALITY = 6, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_LINK_CAPACITY = 7, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_RSSI = 8, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_BMISS = 9, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_BT_STATUS = 10, + + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_MAX, +} WMI_LINK_STATE_SWITCH_REASON; + +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_ML_PEER_ID_GET(new_link_info) WMI_GET_BITS(new_link_info, 0, 16) +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_ML_PEER_ID_SET(new_link_info, value) WMI_SET_BITS(new_link_info, 0, 16, value) + +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_HW_LINK_ID_GET(new_link_info) WMI_GET_BITS(new_link_info, 16, 16) +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_HW_LINK_ID_SET(new_link_info, value) WMI_SET_BITS(new_link_info, 16, 16, value) + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_new_primary_link_peer_info */ + A_UINT32 tlv_header; + + union { + A_UINT32 new_link_info; + struct { + A_UINT32 ml_peer_id :16, + hw_link_id :16; + }; + }; +} wmi_mlo_new_primary_link_peer_info; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_fixed_param */ + A_UINT32 tlv_header; + + A_UINT32 vdev_id; + + /** + * Following this structure is + * the array of "wmi_mlo_new_primary_link_peer_info" TLVs. + */ +} wmi_mlo_primary_link_peer_migration_fixed_param; + +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_STATUS_ML_PEER_ID_GET(status_info) WMI_GET_BITS(status_info, 0, 16) +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_STATUS_ML_PEER_ID_SET(status_info, value) WMI_SET_BITS(status_info, 0, 16, value) + +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_STATUS_STATUS_GET(status_info) WMI_GET_BITS(status_info, 16, 8) +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_STATUS_STATUS_SET(status_info, value) WMI_SET_BITS(status_info, 16, 8, value) + +typedef enum { + WMI_PRIMARY_LINK_PEER_MIGRATION_SUCCESS, + WMI_PRIMARY_LINK_PEER_MIGRATION_IN_PROGRESS, + WMI_PRIMARY_LINK_PEER_MIGRATION_DELETE_IN_PROGRESS, + WMI_PRIMARY_LINK_PEER_MIGRATION_DELETED, + WMI_PRIMARY_LINK_PEER_MIGRATION_TX_PIPES_FAILED, + WMI_PRIMARY_LINK_PEER_MIGRATION_RX_PIPES_FAILED, + + /* Add any new status above this line */ + WMI_PRIMARY_LINK_PEER_MIGRATION_FAIL = 255, +} WMI_PRIMARY_LINK_PEER_MIGRATION_STATUS; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_status */ + A_UINT32 tlv_header; + + union { + A_UINT32 status_info; + struct { + A_UINT32 ml_peer_id :16, + status :8, /* WMI_PRIMARY_LINK_PEER_MIGRATION_STATUS */ + reserved :8; + }; + }; +} wmi_mlo_primary_link_peer_migration_status; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_compl_fixed_param */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + + /** + * Following the fixed param is + * the array of TLVs "wmi_mlo_primary_link_peer_migration_status". + */ +} wmi_mlo_primary_link_peer_migration_compl_fixed_param; + +/* WMI_AUX_DEV_CAPS_SUPPORTED_MODE: + * How many bits to shift for each supported mode. + * This works just like Linux file permission bits + * (i.e. user|group|other values for each rwx perms). + */ +typedef enum _WMI_AUX_DEV_CAPS_SUPPORTED_MODE { + WMI_AUX_DEV_SUPPORTED_MODE_SCAN = 0, + WMI_AUX_DEV_SUPPORTED_MODE_LISTEN = 1, + WMI_AUX_DEV_SUPPORTED_MODE_EMLSR = 2, +} WMI_AUX_DEV_CAPS_SUPPORTED_MODE; + +/* wmi_aux_dev_capabilities: + * TLV representing AUX mode capabilities + * A one-dimensional "flattened" array of these structs shall represent + * all AUX capabilities regardless of the actual AUX count. + * + * For example, if 2x AUX are present, then the array is expected to look + * something like this: + * wmi_aux_dev_capabilities caps[] = { + * // 4 elements for AUX_0 - one element for each HW mode: + * AUX_0_single_mac, + * AUX_0_dual_mac, + * AUX_0_single_mac_emlsr, + * AUX_0_split_emlsr, + * // 4 elements for AUX_1: + * AUX_1_single_mac, + * AUX_1_dual_mac, + * AUX_1_single_mac_emlsr, + * AUX_1_split_emlsr, + * }; + * In effect, indexes 0 to 3 (inclusive) represent the first AUX, + * 4 to 7 (inclusive) represent the second, and so on. + * Note that each element explicitly identifies which AUX and HW mode it + * corresponds to, via the aux_index and hw_mode_id fields respectively. + * So the receiver should not assume the ordering will be as shown above + * (AUX0 single, AUX0 dual, AUX0 single emlsr, AUX0 split emlsr, + * AUX1 single, AUX1 dual, AUX1 single emlsr, AUX1 split emlsr) + * but instead should directly check each element's aux_index and hw_mode_id + * fields. + */ +typedef struct { + /* tlv_header -- WMITLV_TAG_STRUC_wmi_aux_dev_capabilities */ + A_UINT32 tlv_header; + + /* aux_index -- Which AUX this TLV applies to. + Ex: aux_index=0 is first AUX, aux_index=1 is second AUX, etc */ + A_UINT32 aux_index; + + /* + * This TLV represents which AUX capabilities are supported by + * which MAC for the given HW mode. + * pdev ID value of 0x0 denotes that the AUX mode is not applicable + * for the given HW mode. + * + * hw_mode_id | Single DBS_OR_SBS AUX eMLSR AUX eMLSR + * | Phy single split + * -------------------------------------------------------------- + * supported_modes | SCAN/ SCAN/ EMLSR EMLSR + * | LISTEN LISTEN + * listen_pdev_id_map | 0x1 0x2 0x0 0x0 + * emlsr_pdev_id_map | 0x0 0x0 0x1 0x2 + */ + + /* hw_mode_id: + * Which HW mode this TLV applies to. + * HW mode values are defined in WMI_HW_MODE_CONFIG_TYPE. + */ + A_UINT32 hw_mode_id; + + /* supported_modes: + * Which mode this AUX supports for the HW mode defined in hw_mode_id. + * Shift amounts are defined in WMI_AUX_DEV_CAPS_SUPPORTED_MODE. + * This works just like user|group|other bits for Linux file permissions: + * 0x1 = SCAN (0 0 1) + * 0x2 = LISTEN (0 1 0) + * 0x3 = SCAN+LISTEN (0 1 1) + * 0x4 = EMLSR (1 0 0) + */ + A_UINT32 supported_modes_bitmap; + + /* listen_pdev_id_map: + * Which AUX MAC can listen/scan for the HW mode described in hw_mode_id. + * 0x0 - AUX cannot be used for listen mode. + * 0x1 - AUX can be attached to MAC-0 in AUX listen mode. + * 0x2 - AUX can be attached to MAC-1 in AUX listen mode. + */ + A_UINT32 listen_pdev_id_map; + + /* emlsr_pdev_id_map: + * Which AUX MAC can perform eMLSR for the HW mode described in hw_mode_id. + * 0x0 - AUX cannot be used for eMLSR mode. + * 0x1 - AUX can be attached to MAC-0 in AUX eMLSR mode. + * 0x2 - AUX can be attached to MAC-1 in AUX eMLSR mode. + */ + A_UINT32 emlsr_pdev_id_map; +} wmi_aux_dev_capabilities; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 pdev_id; /* for identifying the MAC */ + A_UINT32 wsi_ingress_load_info; + A_UINT32 wsi_egress_load_info; +} wmi_pdev_wsi_stats_info_cmd_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 status; /* accept: 1 reject : 0 */ +} wmi_csa_event_status_ind_fixed_param; diff --git a/drivers/staging/fw-api/fw/wmi_version.h b/drivers/staging/fw-api/fw/wmi_version.h index c71c4da1483be0c19449423e7ced2c02ea157035..35aa809e0fc8cdb156a1fed067d5c31e07c02fe3 100644 --- a/drivers/staging/fw-api/fw/wmi_version.h +++ b/drivers/staging/fw-api/fw/wmi_version.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1252 +#define __WMI_REVISION_ 1392 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work diff --git a/drivers/staging/fw-api/hw/kiwi/v2/ack_report.h b/drivers/staging/fw-api/hw/kiwi/v2/ack_report.h new file mode 100644 index 0000000000000000000000000000000000000000..b92cb77fd2a67c344122e89a6c52bfae4e031469 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/ack_report.h @@ -0,0 +1,68 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _ACK_REPORT_H_ +#define _ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_ACK_REPORT 1 + +struct ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t selfgen_response_reason : 4, + ax_trigger_type : 4, + sr_ppdu : 1, + reserved : 7, + frame_control : 16; +#else + uint32_t frame_control : 16, + reserved : 7, + sr_ppdu : 1, + ax_trigger_type : 4, + selfgen_response_reason : 4; +#endif +}; + +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f + +#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 +#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 +#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 + +#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 +#define ACK_REPORT_SR_PPDU_LSB 8 +#define ACK_REPORT_SR_PPDU_MSB 8 +#define ACK_REPORT_SR_PPDU_MASK 0x00000100 + +#define ACK_REPORT_RESERVED_OFFSET 0x00000000 +#define ACK_REPORT_RESERVED_LSB 9 +#define ACK_REPORT_RESERVED_MSB 15 +#define ACK_REPORT_RESERVED_MASK 0x0000fe00 + +#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define ACK_REPORT_FRAME_CONTROL_LSB 16 +#define ACK_REPORT_FRAME_CONTROL_MSB 31 +#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/coex_rx_status.h b/drivers/staging/fw-api/hw/kiwi/v2/coex_rx_status.h new file mode 100644 index 0000000000000000000000000000000000000000..53bbf0053f4821ff9e6e83418ad835dc3f37cd57 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/coex_rx_status.h @@ -0,0 +1,147 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _COEX_RX_STATUS_H_ +#define _COEX_RX_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_RX_STATUS 2 + +#define NUM_OF_QWORDS_COEX_RX_STATUS 1 + +struct coex_rx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_mac_frame_status : 2, + rx_with_tx_response : 1, + rx_rate : 5, + rx_bw : 3, + single_mpdu : 1, + filter_status : 1, + ampdu : 1, + directed : 1, + reserved_0 : 1, + rx_nss : 3, + rx_rssi : 8, + rx_type : 3, + retry_bit_setting : 1, + more_data_bit_setting : 1; + uint32_t remain_rx_packet_time : 16, + rx_remaining_fes_time : 16; +#else + uint32_t more_data_bit_setting : 1, + retry_bit_setting : 1, + rx_type : 3, + rx_rssi : 8, + rx_nss : 3, + reserved_0 : 1, + directed : 1, + ampdu : 1, + filter_status : 1, + single_mpdu : 1, + rx_bw : 3, + rx_rate : 5, + rx_with_tx_response : 1, + rx_mac_frame_status : 2; + uint32_t rx_remaining_fes_time : 16, + remain_rx_packet_time : 16; +#endif +}; + +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 + +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 + +#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_RATE_LSB 3 +#define COEX_RX_STATUS_RX_RATE_MSB 7 +#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 + +#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_BW_LSB 8 +#define COEX_RX_STATUS_RX_BW_MSB 10 +#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 + +#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 + +#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 + +#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_AMPDU_LSB 13 +#define COEX_RX_STATUS_AMPDU_MSB 13 +#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 + +#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_DIRECTED_LSB 14 +#define COEX_RX_STATUS_DIRECTED_MSB 14 +#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 + +#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RESERVED_0_LSB 15 +#define COEX_RX_STATUS_RESERVED_0_MSB 15 +#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 + +#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_NSS_LSB 16 +#define COEX_RX_STATUS_RX_NSS_MSB 18 +#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 + +#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_RSSI_LSB 19 +#define COEX_RX_STATUS_RX_RSSI_MSB 26 +#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 + +#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_TYPE_LSB 27 +#define COEX_RX_STATUS_RX_TYPE_MSB 29 +#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 + +#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 + +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 + +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 + +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/coex_tx_req.h b/drivers/staging/fw-api/hw/kiwi/v2/coex_tx_req.h new file mode 100644 index 0000000000000000000000000000000000000000..e19fefa41385fd68964ddd2019b718837cd7494a --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/coex_tx_req.h @@ -0,0 +1,196 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _COEX_TX_REQ_H_ +#define _COEX_TX_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_TX_REQ 4 + +#define NUM_OF_QWORDS_COEX_TX_REQ 2 + +struct coex_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_pwr : 8, + min_tx_pwr : 8, + nss : 3, + tx_chain_mask : 8, + bw : 3, + reserved_0 : 2; + uint32_t alt_tx_pwr : 8, + alt_min_tx_pwr : 8, + alt_nss : 3, + alt_tx_chain_mask : 8, + alt_bw : 3, + reserved_1 : 2; + uint32_t tx_pwr_1 : 8, + alt_tx_pwr_1 : 8, + wlan_request_duration : 16; + uint32_t wlan_pkt_type : 4, + coex_tx_reason : 2, + response_frame_type : 5, + wlan_low_priority_slicing_allowed : 1, + wlan_high_priority_slicing_allowed : 1, + sch_tx_burst_ongoing : 1, + coex_tx_priority : 4, + reserved_3a : 14; +#else + uint32_t reserved_0 : 2, + bw : 3, + tx_chain_mask : 8, + nss : 3, + min_tx_pwr : 8, + tx_pwr : 8; + uint32_t reserved_1 : 2, + alt_bw : 3, + alt_tx_chain_mask : 8, + alt_nss : 3, + alt_min_tx_pwr : 8, + alt_tx_pwr : 8; + uint32_t wlan_request_duration : 16, + alt_tx_pwr_1 : 8, + tx_pwr_1 : 8; + uint32_t reserved_3a : 14, + coex_tx_priority : 4, + sch_tx_burst_ongoing : 1, + wlan_high_priority_slicing_allowed : 1, + wlan_low_priority_slicing_allowed : 1, + response_frame_type : 5, + coex_tx_reason : 2, + wlan_pkt_type : 4; +#endif +}; + +#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_TX_PWR_LSB 0 +#define COEX_TX_REQ_TX_PWR_MSB 7 +#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff + +#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 +#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 +#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00 + +#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_NSS_LSB 16 +#define COEX_TX_REQ_NSS_MSB 18 +#define COEX_TX_REQ_NSS_MASK 0x0000000000070000 + +#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 +#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 +#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000 + +#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_BW_LSB 27 +#define COEX_TX_REQ_BW_MSB 29 +#define COEX_TX_REQ_BW_MASK 0x0000000038000000 + +#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_RESERVED_0_LSB 30 +#define COEX_TX_REQ_RESERVED_0_MSB 31 +#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000 + +#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_TX_PWR_LSB 32 +#define COEX_TX_REQ_ALT_TX_PWR_MSB 39 +#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_NSS_LSB 48 +#define COEX_TX_REQ_ALT_NSS_MSB 50 +#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000 + +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_BW_LSB 59 +#define COEX_TX_REQ_ALT_BW_MSB 61 +#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000 + +#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_RESERVED_1_LSB 62 +#define COEX_TX_REQ_RESERVED_1_MSB 63 +#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000 + +#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_TX_PWR_1_LSB 0 +#define COEX_TX_REQ_TX_PWR_1_MSB 7 +#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff + +#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 +#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 +#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00 + +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000 + +#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000 + +#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_COEX_TX_REASON_LSB 36 +#define COEX_TX_REQ_COEX_TX_REASON_MSB 37 +#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000 + +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000 + +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000 + +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000 + +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000 + +#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000 + +#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_RESERVED_3A_LSB 50 +#define COEX_TX_REQ_RESERVED_3A_MSB 63 +#define COEX_TX_REQ_RESERVED_3A_MASK 0xfffc000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/coex_tx_status.h b/drivers/staging/fw-api/hw/kiwi/v2/coex_tx_status.h new file mode 100644 index 0000000000000000000000000000000000000000..597c37388879f92fa4e92067ea9fc038a4ff1a24 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/coex_tx_status.h @@ -0,0 +1,133 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _COEX_TX_STATUS_H_ +#define _COEX_TX_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_TX_STATUS 4 + +#define NUM_OF_QWORDS_COEX_TX_STATUS 2 + +struct coex_tx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 7, + tx_bw : 3, + tx_status_reason : 3, + tx_wait_ack : 1, + fes_tx_is_gen_frame : 1, + sch_tx_burst_ongoing : 1, + current_tx_duration : 16; + uint32_t next_rx_active_time : 16, + remaining_fes_time : 16; + uint32_t tx_antenna_mask : 8, + shared_ant_tx_pwr : 8, + other_ant_tx_pwr : 8, + reserved_2 : 8; + uint32_t tlv64_padding : 32; +#else + uint32_t current_tx_duration : 16, + sch_tx_burst_ongoing : 1, + fes_tx_is_gen_frame : 1, + tx_wait_ack : 1, + tx_status_reason : 3, + tx_bw : 3, + reserved_0a : 7; + uint32_t remaining_fes_time : 16, + next_rx_active_time : 16; + uint32_t reserved_2 : 8, + other_ant_tx_pwr : 8, + shared_ant_tx_pwr : 8, + tx_antenna_mask : 8; + uint32_t tlv64_padding : 32; +#endif +}; + +#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_RESERVED_0A_LSB 0 +#define COEX_TX_STATUS_RESERVED_0A_MSB 6 +#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f + +#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_BW_LSB 7 +#define COEX_TX_STATUS_TX_BW_MSB 9 +#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 + +#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 +#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 +#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 + +#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 + +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 + +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 + +#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 + +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 + +#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 + +#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff + +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 + +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 + +#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_RESERVED_2_LSB 24 +#define COEX_TX_STATUS_RESERVED_2_MSB 31 +#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 + +#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_TLV64_PADDING_LSB 32 +#define COEX_TX_STATUS_TLV64_PADDING_MSB 63 +#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h new file mode 100644 index 0000000000000000000000000000000000000000..9ae112a88007a8bcce4f333b4cdac3aca3c112d3 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h @@ -0,0 +1,110 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ +#define _EHT_SIG_USR_MU_MIMO_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 + +struct eht_sig_usr_mu_mimo_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + sta_coding : 1, + sta_spatial_config : 6, + reserved_0a : 1, + rx_integrity_check_passed : 1, + subband80_cc_mask : 8; + uint32_t user_order_subband80_0 : 8, + user_order_subband80_1 : 8, + user_order_subband80_2 : 8, + user_order_subband80_3 : 8; +#else + uint32_t subband80_cc_mask : 8, + rx_integrity_check_passed : 1, + reserved_0a : 1, + sta_spatial_config : 6, + sta_coding : 1, + sta_mcs : 4, + sta_id : 11; + uint32_t user_order_subband80_3 : 8, + user_order_subband80_2 : 8, + user_order_subband80_1 : 8, + user_order_subband80_0 : 8; +#endif +}; + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 + +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 + +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_ofdma_info.h new file mode 100644 index 0000000000000000000000000000000000000000..4700af7c46103c7b42a41067a338f11b500c0752 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_ofdma_info.h @@ -0,0 +1,124 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ +#define _EHT_SIG_USR_OFDMA_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 + +struct eht_sig_usr_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + validate_0a : 1, + nss : 4, + txbf : 1, + sta_coding : 1, + reserved_0b : 1, + rx_integrity_check_passed : 1, + subband80_cc_mask : 8; + uint32_t user_order_subband80_0 : 8, + user_order_subband80_1 : 8, + user_order_subband80_2 : 8, + user_order_subband80_3 : 8; +#else + uint32_t subband80_cc_mask : 8, + rx_integrity_check_passed : 1, + reserved_0b : 1, + sta_coding : 1, + txbf : 1, + nss : 4, + validate_0a : 1, + sta_mcs : 4, + sta_id : 11; + uint32_t user_order_subband80_3 : 8, + user_order_subband80_2 : 8, + user_order_subband80_1 : 8, + user_order_subband80_0 : 8; +#endif +}; + +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 + +#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 + +#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 + +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 + +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 + +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_su_info.h new file mode 100644 index 0000000000000000000000000000000000000000..746d557796f99584cda4e42065c9d2900b2124d2 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_su_info.h @@ -0,0 +1,89 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _EHT_SIG_USR_SU_INFO_H_ +#define _EHT_SIG_USR_SU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 + +struct eht_sig_usr_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + validate_0a : 1, + nss : 4, + txbf : 1, + sta_coding : 1, + reserved_0b : 9, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0b : 9, + sta_coding : 1, + txbf : 1, + nss : 4, + validate_0a : 1, + sta_mcs : 4, + sta_id : 11; +#endif +}; + +#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 + +#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 +#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 +#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 + +#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 + +#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 + +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 + +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/expected_response.h b/drivers/staging/fw-api/hw/kiwi/v2/expected_response.h new file mode 100644 index 0000000000000000000000000000000000000000..e62901b2460415facf6dc1553a6616fb79d4a407 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/expected_response.h @@ -0,0 +1,217 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _EXPECTED_RESPONSE_H_ +#define _EXPECTED_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 + +#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 + +struct expected_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_ad2_31_0 : 32; + uint32_t tx_ad2_47_32 : 16, + expected_response_type : 5, + response_to_response : 3, + su_ba_user_number : 1, + response_info_part2_required : 1, + transmitted_bssid_check_en : 1, + reserved_1 : 5; + uint32_t ndp_sta_partial_aid_2_8_0 : 11, + reserved_2 : 10, + ndp_sta_partial_aid1_8_0 : 11; + uint32_t ast_index : 16, + capture_ack_ba_sounding : 1, + capture_sounding_1str_20mhz : 1, + capture_sounding_1str_40mhz : 1, + capture_sounding_1str_80mhz : 1, + capture_sounding_1str_160mhz : 1, + capture_sounding_1str_240mhz : 1, + capture_sounding_1str_320mhz : 1, + reserved_3a : 9; + uint32_t fcs : 9, + reserved_4a : 1, + crc : 4, + scrambler_seed : 7, + reserved_4b : 11; + uint32_t tlv64_padding : 32; +#else + uint32_t tx_ad2_31_0 : 32; + uint32_t reserved_1 : 5, + transmitted_bssid_check_en : 1, + response_info_part2_required : 1, + su_ba_user_number : 1, + response_to_response : 3, + expected_response_type : 5, + tx_ad2_47_32 : 16; + uint32_t ndp_sta_partial_aid1_8_0 : 11, + reserved_2 : 10, + ndp_sta_partial_aid_2_8_0 : 11; + uint32_t reserved_3a : 9, + capture_sounding_1str_320mhz : 1, + capture_sounding_1str_240mhz : 1, + capture_sounding_1str_160mhz : 1, + capture_sounding_1str_80mhz : 1, + capture_sounding_1str_40mhz : 1, + capture_sounding_1str_20mhz : 1, + capture_ack_ba_sounding : 1, + ast_index : 16; + uint32_t reserved_4b : 11, + scrambler_seed : 7, + crc : 4, + reserved_4a : 1, + fcs : 9; + uint32_t tlv64_padding : 32; +#endif +}; + +#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff + +#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 + +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 + +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 + +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 + +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 + +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 + +#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESERVED_1_LSB 59 +#define EXPECTED_RESPONSE_RESERVED_1_MSB 63 +#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf800000000000000 + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff + +#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 +#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 +#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 + +#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_AST_INDEX_LSB 32 +#define EXPECTED_RESPONSE_AST_INDEX_MSB 47 +#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 + +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 + +#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 +#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 +#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 + +#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_FCS_LSB 0 +#define EXPECTED_RESPONSE_FCS_MSB 8 +#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff + +#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_RESERVED_4A_LSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x0000000000000200 + +#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_CRC_LSB 10 +#define EXPECTED_RESPONSE_CRC_MSB 13 +#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 + +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 + +#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 +#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 + +#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 +#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 +#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_mu_mimo.h new file mode 100644 index 0000000000000000000000000000000000000000..3d3ff5b23ae9c551101a9d9885c853432e9d2cfb --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_mu_mimo.h @@ -0,0 +1,93 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ +#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_mu_mimo_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 + +struct mactx_eht_sig_usr_mu_mimo { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#else + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_ofdma.h new file mode 100644 index 0000000000000000000000000000000000000000..0996ff5b546058ac97904792ed25321bd372a28e --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_ofdma.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ +#define _MACTX_EHT_SIG_USR_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1 + +struct mactx_eht_sig_usr_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#else + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_su.h new file mode 100644 index 0000000000000000000000000000000000000000..6254d13942d87d5f198a528bc6a0e43700d40f7e --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_su.h @@ -0,0 +1,85 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_EHT_SIG_USR_SU_H_ +#define _MACTX_EHT_SIG_USR_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_su_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1 + +struct mactx_eht_sig_usr_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; + uint32_t tlv64_padding : 32; +#else + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_mu_dl.h new file mode 100644 index 0000000000000000000000000000000000000000..fcbbd39d631e9f81da2c38ed71c5b0b586e0ccf6 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_mu_dl.h @@ -0,0 +1,148 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_A_MU_DL_H_ +#define _MACTX_HE_SIG_A_MU_DL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1 + +struct mactx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_mu_ul.h new file mode 100644 index 0000000000000000000000000000000000000000..c150750711b0db7f89a9437fecb6e959cdac4e6b --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_mu_ul.h @@ -0,0 +1,98 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_A_MU_UL_H_ +#define _MACTX_HE_SIG_A_MU_UL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1 + +struct mactx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_su.h new file mode 100644 index 0000000000000000000000000000000000000000..0ae2a026c796a650129b45f7f08052f7ba7f352c --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_su.h @@ -0,0 +1,173 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_A_SU_H_ +#define _MACTX_HE_SIG_A_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1 + +struct mactx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b1_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..de9156081d135d84f9f742effe984b39371b1fca --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b1_mu.h @@ -0,0 +1,60 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_B1_MU_H_ +#define _MACTX_HE_SIG_B1_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 + +struct mactx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; +#else + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b2_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..0204d9a3739d6e7fd589fbad47752202862dc2f3 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b2_mu.h @@ -0,0 +1,93 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_B2_MU_H_ +#define _MACTX_HE_SIG_B2_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1 + +struct mactx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#endif +}; + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b2_ofdma.h new file mode 100644 index 0000000000000000000000000000000000000000..09cde561aebd77f448c0a63a39246ea6d11246ab --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b2_ofdma.h @@ -0,0 +1,93 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ +#define _MACTX_HE_SIG_B2_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1 + +struct mactx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#endif +}; + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_ht_sig.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_ht_sig.h new file mode 100644 index 0000000000000000000000000000000000000000..2bbb61d6f40efecd02a4da99b5468ad75d9309c7 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_ht_sig.h @@ -0,0 +1,118 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HT_SIG_H_ +#define _MACTX_HT_SIG_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_MACTX_HT_SIG 2 + +#define NUM_OF_QWORDS_MACTX_HT_SIG 1 + +struct mactx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info mactx_ht_sig_info_details; +#else + struct ht_sig_info mactx_ht_sig_info_details; +#endif +}; + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_l_sig_a.h new file mode 100644 index 0000000000000000000000000000000000000000..1d7913d53c068c968209596c0258df55bc6705d6 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_l_sig_a.h @@ -0,0 +1,90 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_L_SIG_A_H_ +#define _MACTX_L_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_A 2 + +#define NUM_OF_QWORDS_MACTX_L_SIG_A 1 + +struct mactx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info mactx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; +#else + struct l_sig_a_info mactx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32 +#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63 +#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_l_sig_b.h new file mode 100644 index 0000000000000000000000000000000000000000..397c20f7067b283ebf163a3a8c2bac4f88ca741c --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_l_sig_b.h @@ -0,0 +1,65 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_L_SIG_B_H_ +#define _MACTX_L_SIG_B_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_B 2 + +#define NUM_OF_QWORDS_MACTX_L_SIG_B 1 + +struct mactx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info mactx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; +#else + struct l_sig_b_info mactx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32 +#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63 +#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_phy_desc.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_phy_desc.h new file mode 100644 index 0000000000000000000000000000000000000000..c6f7cdca83fc89b376f084b012f6e5d43332f169 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_phy_desc.h @@ -0,0 +1,371 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_PHY_DESC_H_ +#define _MACTX_PHY_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 + +#define NUM_OF_QWORDS_MACTX_PHY_DESC 2 + +struct mactx_phy_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 16, + bf_type : 2, + wait_sifs : 2, + dot11b_preamble_type : 1, + pkt_type : 4, + su_or_mu : 2, + mu_type : 1, + bandwidth : 3, + channel_capture : 1; + uint32_t mcs : 4, + global_ofdma_mimo_enable : 1, + reserved_1a : 1, + stbc : 1, + dot11ax_su_extended : 1, + dot11ax_trigger_frame_embedded : 1, + tx_pwr_shared : 8, + tx_pwr_unshared : 8, + measure_power : 1, + tpc_glut_self_cal : 1, + back_to_back_transmission_expected : 1, + heavy_clip_nss : 3, + txbf_per_packet_no_csd_no_walsh : 1; + uint32_t ndp : 2, + ul_flag : 1, + triggered : 1, + ap_pkt_bw : 3, + ru_position_start : 8, + pcu_ppdu_setup_start_reason : 3, + tlv_source : 1, + reserved_2a : 2, + nss : 3, + stream_offset : 3, + reserved_2b : 2, + clpc_enable : 1, + mu_ndp : 1, + response_expected : 1; + uint32_t rx_chain_mask : 8, + rx_chain_mask_valid : 1, + ant_sel_valid : 1, + ant_sel : 1, + cp_setting : 2, + he_ppdu_subtype : 2, + active_channel : 3, + generate_phyrx_tx_start_timing : 1, + ltf_size : 2, + ru_size_updated_v2 : 4, + reserved_3c : 1, + u_sig_puncture_pattern_encoding : 6; +#else + uint32_t channel_capture : 1, + bandwidth : 3, + mu_type : 1, + su_or_mu : 2, + pkt_type : 4, + dot11b_preamble_type : 1, + wait_sifs : 2, + bf_type : 2, + reserved_0a : 16; + uint32_t txbf_per_packet_no_csd_no_walsh : 1, + heavy_clip_nss : 3, + back_to_back_transmission_expected : 1, + tpc_glut_self_cal : 1, + measure_power : 1, + tx_pwr_unshared : 8, + tx_pwr_shared : 8, + dot11ax_trigger_frame_embedded : 1, + dot11ax_su_extended : 1, + stbc : 1, + reserved_1a : 1, + global_ofdma_mimo_enable : 1, + mcs : 4; + uint32_t response_expected : 1, + mu_ndp : 1, + clpc_enable : 1, + reserved_2b : 2, + stream_offset : 3, + nss : 3, + reserved_2a : 2, + tlv_source : 1, + pcu_ppdu_setup_start_reason : 3, + ru_position_start : 8, + ap_pkt_bw : 3, + triggered : 1, + ul_flag : 1, + ndp : 2; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_3c : 1, + ru_size_updated_v2 : 4, + ltf_size : 2, + generate_phyrx_tx_start_timing : 1, + active_channel : 3, + he_ppdu_subtype : 2, + cp_setting : 2, + ant_sel : 1, + ant_sel_valid : 1, + rx_chain_mask_valid : 1, + rx_chain_mask : 8; +#endif +}; + +#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 +#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 +#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff + +#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BF_TYPE_LSB 16 +#define MACTX_PHY_DESC_BF_TYPE_MSB 17 +#define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 + +#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 +#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 +#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 + +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 + +#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 +#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 +#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 + +#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 +#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 +#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 + +#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MU_TYPE_LSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 + +#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 +#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 +#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 + +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 + +#define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MCS_LSB 32 +#define MACTX_PHY_DESC_MCS_MSB 35 +#define MACTX_PHY_DESC_MCS_MASK 0x0000000f00000000 + +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 36 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 36 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000001000000000 + +#define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_RESERVED_1A_LSB 37 +#define MACTX_PHY_DESC_RESERVED_1A_MSB 37 +#define MACTX_PHY_DESC_RESERVED_1A_MASK 0x0000002000000000 + +#define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_STBC_LSB 38 +#define MACTX_PHY_DESC_STBC_MSB 38 +#define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 + +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 + +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 + +#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 + +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 + +#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 +#define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 +#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 + +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 + +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 + +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 + +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 + +#define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_NDP_LSB 0 +#define MACTX_PHY_DESC_NDP_MSB 1 +#define MACTX_PHY_DESC_NDP_MASK 0x0000000000000003 + +#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_UL_FLAG_LSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000004 + +#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_TRIGGERED_LSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000008 + +#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 +#define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 +#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x0000000000000070 + +#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 +#define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 +#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x0000000000007f80 + +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000038000 + +#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000040000 + +#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_2A_LSB 19 +#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 +#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000180000 + +#define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_NSS_LSB 21 +#define MACTX_PHY_DESC_NSS_MSB 23 +#define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 + +#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 +#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 +#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 + +#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 +#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 +#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 + +#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 + +#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_MU_NDP_LSB 30 +#define MACTX_PHY_DESC_MU_NDP_MSB 30 +#define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 + +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 + +#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 + +#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ANT_SEL_LSB 42 +#define MACTX_PHY_DESC_ANT_SEL_MSB 42 +#define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 + +#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_CP_SETTING_LSB 43 +#define MACTX_PHY_DESC_CP_SETTING_MSB 44 +#define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 + +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 + +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 + +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 + +#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_LTF_SIZE_LSB 51 +#define MACTX_PHY_DESC_LTF_SIZE_MSB 52 +#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 + +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 + +#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_3C_LSB 57 +#define MACTX_PHY_DESC_RESERVED_3C_MSB 57 +#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 + +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_u_sig_eht_su_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..35f58ab104f6506a6ad46a06fddce8d8a0ba3232 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_u_sig_eht_su_mu.h @@ -0,0 +1,138 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ +#define _MACTX_U_SIG_EHT_SU_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "u_sig_eht_su_mu_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 + +#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1 + +struct mactx_u_sig_eht_su_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#else + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#endif +}; + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_u_sig_eht_tb.h new file mode 100644 index 0000000000000000000000000000000000000000..7318873f1a6a5d4706e3f6ca77f8b54aaed2e66e --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_u_sig_eht_tb.h @@ -0,0 +1,113 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_U_SIG_EHT_TB_H_ +#define _MACTX_U_SIG_EHT_TB_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "u_sig_eht_tb_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 + +#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1 + +struct mactx_u_sig_eht_tb { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#else + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#endif +}; + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_user_desc_common.h new file mode 100644 index 0000000000000000000000000000000000000000..f3d78ce1ee1bea1851dc5b662f6a618416dac385 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_user_desc_common.h @@ -0,0 +1,484 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_USER_DESC_COMMON_H_ +#define _MACTX_USER_DESC_COMMON_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "unallocated_ru_160_info.h" +#include "ru_allocation_160_info.h" +#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 + +#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 + +struct mactx_user_desc_common { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, + reserved_0b : 5, + ltf_size : 2, + reserved_0c : 3, + he_stf_long : 1, + reserved_0d : 7, + num_users_he_sigb_band0 : 8; + uint32_t num_ltf_symbols : 3, + reserved_1a : 5, + num_users_he_sigb_band1 : 8, + reserved_1b : 16; + uint32_t packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + packet_extension : 3, + reserved : 2, + he_sigb_dcm : 1, + reserved_2b : 7, + he_sigb_compression : 1, + reserved_2c : 15; + uint32_t he_sigb_0_mcs : 3, + reserved_3a : 13, + num_he_sigb_sym : 5, + center_ru_0 : 1, + center_ru_1 : 1, + reserved_3b : 1, + ftm_en : 1, + pe_nss : 3, + pe_ltf_size : 2, + pe_content : 1, + pe_chain_csd_en : 1; + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t num_data_symbols : 16, + ndp_ru_tone_set_index : 7, + ndp_feedback_status : 1, + doppler_indication : 1, + reserved_14a : 7; + uint32_t spatial_reuse : 16, + reserved_15a : 16; +#else + uint32_t num_users_he_sigb_band0 : 8, + reserved_0d : 7, + he_stf_long : 1, + reserved_0c : 3, + ltf_size : 2, + reserved_0b : 5, + num_users : 6; + uint32_t reserved_1b : 16, + num_users_he_sigb_band1 : 8, + reserved_1a : 5, + num_ltf_symbols : 3; + uint32_t reserved_2c : 15, + he_sigb_compression : 1, + reserved_2b : 7, + he_sigb_dcm : 1, + reserved : 2, + packet_extension : 3, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2; + uint32_t pe_chain_csd_en : 1, + pe_content : 1, + pe_ltf_size : 2, + pe_nss : 3, + ftm_en : 1, + reserved_3b : 1, + center_ru_1 : 1, + center_ru_0 : 1, + num_he_sigb_sym : 5, + reserved_3a : 13, + he_sigb_0_mcs : 3; + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t reserved_14a : 7, + doppler_indication : 1, + ndp_feedback_status : 1, + ndp_ru_tone_set_index : 7, + num_data_symbols : 16; + uint32_t reserved_15a : 16, + spatial_reuse : 16; +#endif +}; + +#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f + +#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 + +#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 + +#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 + +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 + +#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 + +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 + +#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 +#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 + +#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 + +#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 + +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 + +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 + +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 + +#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 +#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 +#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 + +#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 +#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 +#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 + +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 + +#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 + +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 + +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff + +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 + +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 + +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 + +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 48 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_user_desc_per_user.h new file mode 100644 index 0000000000000000000000000000000000000000..c0cf26c9ecb112711e25e9219e378dc2c54b45c4 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_user_desc_per_user.h @@ -0,0 +1,196 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_USER_DESC_PER_USER_H_ +#define _MACTX_USER_DESC_PER_USER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4 + +#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 2 + +struct mactx_user_desc_per_user { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t psdu_length : 24, + reserved_0a : 8; + uint32_t ru_start_index : 8, + ru_size : 4, + reserved_1b : 4, + ofdma_mu_mimo_enabled : 1, + nss : 3, + stream_offset : 3, + reserved_1c : 1, + mcs : 4, + dcm : 1, + reserved_1d : 3; + uint32_t fec_type : 1, + reserved_2a : 7, + user_bf_type : 2, + reserved_2b : 6, + drop_user_cbf : 1, + reserved_2c : 7, + ldpc_extra_symbol : 1, + force_extra_symbol : 1, + reserved_2d : 6; + uint32_t sw_peer_id : 16, + per_user_subband_mask : 16; +#else + uint32_t reserved_0a : 8, + psdu_length : 24; + uint32_t reserved_1d : 3, + dcm : 1, + mcs : 4, + reserved_1c : 1, + stream_offset : 3, + nss : 3, + ofdma_mu_mimo_enabled : 1, + reserved_1b : 4, + ru_size : 4, + ru_start_index : 8; + uint32_t reserved_2d : 6, + force_extra_symbol : 1, + ldpc_extra_symbol : 1, + reserved_2c : 7, + drop_user_cbf : 1, + reserved_2b : 6, + user_bf_type : 2, + reserved_2a : 7, + fec_type : 1; + uint32_t per_user_subband_mask : 16, + sw_peer_id : 16; +#endif +}; + +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff + +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000 + +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000 + +#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000 + +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000 + +#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_NSS_LSB 49 +#define MACTX_USER_DESC_PER_USER_NSS_MSB 51 +#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000 + +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000 + +#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_MCS_LSB 56 +#define MACTX_USER_DESC_PER_USER_MCS_MSB 59 +#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f00000000000000 + +#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_DCM_LSB 60 +#define MACTX_USER_DESC_PER_USER_DCM_MSB 60 +#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x1000000000000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 61 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe000000000000000 + +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x00000000000000fe + +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x000000000000fc00 + +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x0000000000fe0000 + +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000 + +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000fc000000 + +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_a.h new file mode 100644 index 0000000000000000000000000000000000000000..34eddc4b435c947f97cf2216ccb1c65db1f7f747 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_a.h @@ -0,0 +1,128 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_A_H_ +#define _MACTX_VHT_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1 + +struct mactx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#else + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#endif +}; + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu160.h new file mode 100644 index 0000000000000000000000000000000000000000..52e85cdec2054f151855f0c362f7a491f6104317 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu160.h @@ -0,0 +1,198 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_MU160_H_ +#define _MACTX_VHT_SIG_B_MU160_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4 + +struct mactx_vht_sig_b_mu160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#else + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu20.h new file mode 100644 index 0000000000000000000000000000000000000000..626929b4c767c143ff4d98a76b6a50e11d82534d --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu20.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_MU20_H_ +#define _MACTX_VHT_SIG_B_MU20_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1 + +struct mactx_vht_sig_b_mu20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; + uint32_t tlv64_padding : 32; +#else + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu40.h new file mode 100644 index 0000000000000000000000000000000000000000..bc1e56c46c53079125550d18054cd04dde54df44 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu40.h @@ -0,0 +1,83 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_MU40_H_ +#define _MACTX_VHT_SIG_B_MU40_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1 + +struct mactx_vht_sig_b_mu40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#else + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu80.h new file mode 100644 index 0000000000000000000000000000000000000000..d4499072674df9887f21e26f0737c3bc4c3dc2e8 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu80.h @@ -0,0 +1,118 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_MU80_H_ +#define _MACTX_VHT_SIG_B_MU80_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2 + +struct mactx_vht_sig_b_mu80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#else + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su160.h new file mode 100644 index 0000000000000000000000000000000000000000..aa74f8a27a129127dc9dfbcf0be28013b291ea6f --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su160.h @@ -0,0 +1,238 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_SU160_H_ +#define _MACTX_VHT_SIG_B_SU160_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4 + +struct mactx_vht_sig_b_su160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#else + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su20.h new file mode 100644 index 0000000000000000000000000000000000000000..823052ebfd88915e05d7522c813887793bbdb570 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su20.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_SU20_H_ +#define _MACTX_VHT_SIG_B_SU20_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1 + +struct mactx_vht_sig_b_su20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; + uint32_t tlv64_padding : 32; +#else + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su40.h new file mode 100644 index 0000000000000000000000000000000000000000..610db4be1fcf47c48d9a987ddf07bfde4edb2984 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su40.h @@ -0,0 +1,88 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_SU40_H_ +#define _MACTX_VHT_SIG_B_SU40_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1 + +struct mactx_vht_sig_b_su40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#else + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su80.h new file mode 100644 index 0000000000000000000000000000000000000000..ae448945e01b4b98062e66e9778cd95cad08ff51 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su80.h @@ -0,0 +1,138 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_SU80_H_ +#define _MACTX_VHT_SIG_B_SU80_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2 + +struct mactx_vht_sig_b_su80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#else + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/kiwi/v2/mlo_sta_id_details.h new file mode 100644 index 0000000000000000000000000000000000000000..91bf584790fc6b1564e821a2ed6675324e14dd8a --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mlo_sta_id_details.h @@ -0,0 +1,68 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MLO_STA_ID_DETAILS_H_ +#define _MLO_STA_ID_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 + +struct mlo_sta_id_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t nstr_mlo_sta_id : 10, + block_self_ml_sync : 1, + block_partner_ml_sync : 1, + nstr_mlo_sta_id_valid : 1, + reserved_0a : 3; +#else + uint16_t reserved_0a : 3, + nstr_mlo_sta_id_valid : 1, + block_partner_ml_sync : 1, + block_self_ml_sync : 1, + nstr_mlo_sta_id : 10; +#endif +}; + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mon_buffer_addr.h b/drivers/staging/fw-api/hw/kiwi/v2/mon_buffer_addr.h new file mode 100644 index 0000000000000000000000000000000000000000..afbfb52367c2899fdb84b2b7184c5a98f82dc748 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mon_buffer_addr.h @@ -0,0 +1,91 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MON_BUFFER_ADDR_H_ +#define _MON_BUFFER_ADDR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 + +#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 + +struct mon_buffer_addr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t dma_length : 12, + reserved_2a : 4, + msdu_continuation : 1, + truncated : 1, + reserved_2b : 14; + uint32_t tlv64_padding : 32; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reserved_2b : 14, + truncated : 1, + msdu_continuation : 1, + reserved_2a : 4, + dma_length : 12; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 + +#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 +#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 +#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff + +#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 +#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 +#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 + +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 + +#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 + +#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 +#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 +#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 + +#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 +#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 +#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mon_destination_ring.h b/drivers/staging/fw-api/hw/kiwi/v2/mon_destination_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..c92ec87f4d99870a47f183d7286141e8f67e8613 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mon_destination_ring.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MON_DESTINATION_RING_H_ +#define _MON_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 + +struct mon_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t stat_buf_virt_addr_31_0 : 32; + uint32_t stat_buf_virt_addr_63_32 : 32; + uint32_t ppdu_id : 32; + uint32_t end_offset : 12, + reserved_3a : 4, + end_reason : 2, + initiator : 1, + empty_descriptor : 1, + ring_id : 8, + looping_count : 4; +#else + uint32_t stat_buf_virt_addr_31_0 : 32; + uint32_t stat_buf_virt_addr_63_32 : 32; + uint32_t ppdu_id : 32; + uint32_t looping_count : 4, + ring_id : 8, + empty_descriptor : 1, + initiator : 1, + end_reason : 2, + reserved_3a : 4, + end_offset : 12; +#endif +}; + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff + +#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 +#define MON_DESTINATION_RING_PPDU_ID_LSB 0 +#define MON_DESTINATION_RING_PPDU_ID_MSB 31 +#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff + +#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_OFFSET_LSB 0 +#define MON_DESTINATION_RING_END_OFFSET_MSB 11 +#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff + +#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 +#define MON_DESTINATION_RING_RESERVED_3A_MSB 15 +#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x0000f000 + +#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_REASON_LSB 16 +#define MON_DESTINATION_RING_END_REASON_MSB 17 +#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 + +#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_INITIATOR_LSB 18 +#define MON_DESTINATION_RING_INITIATOR_MSB 18 +#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 + +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 + +#define MON_DESTINATION_RING_RING_ID_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RING_ID_LSB 20 +#define MON_DESTINATION_RING_RING_ID_MSB 27 +#define MON_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + +#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c +#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mon_drop.h b/drivers/staging/fw-api/hw/kiwi/v2/mon_drop.h new file mode 100644 index 0000000000000000000000000000000000000000..f4af1328c76e895d7807a17abf1005af3a9b1613 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mon_drop.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MON_DROP_H_ +#define _MON_DROP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_DROP 2 + +#define NUM_OF_QWORDS_MON_DROP 1 + +struct mon_drop { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_id : 32; + uint32_t ppdu_drop_cnt : 10, + mpdu_drop_cnt : 10, + tlv_drop_cnt : 10, + end_of_ppdu_seen : 1, + reserved_1a : 1; +#else + uint32_t ppdu_id : 32; + uint32_t reserved_1a : 1, + end_of_ppdu_seen : 1, + tlv_drop_cnt : 10, + mpdu_drop_cnt : 10, + ppdu_drop_cnt : 10; +#endif +}; + +#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000 +#define MON_DROP_PPDU_ID_LSB 0 +#define MON_DROP_PPDU_ID_MSB 31 +#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff + +#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_PPDU_DROP_CNT_LSB 32 +#define MON_DROP_PPDU_DROP_CNT_MSB 41 +#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000 + +#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_MPDU_DROP_CNT_LSB 42 +#define MON_DROP_MPDU_DROP_CNT_MSB 51 +#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000 + +#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_TLV_DROP_CNT_LSB 52 +#define MON_DROP_TLV_DROP_CNT_MSB 61 +#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000 + +#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000 +#define MON_DROP_END_OF_PPDU_SEEN_LSB 62 +#define MON_DROP_END_OF_PPDU_SEEN_MSB 62 +#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000 + +#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000 +#define MON_DROP_RESERVED_1A_LSB 63 +#define MON_DROP_RESERVED_1A_MSB 63 +#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mon_ingress_ring.h b/drivers/staging/fw-api/hw/kiwi/v2/mon_ingress_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..5ddfc4f725f5ebfc5c6c23dc3808a7cf1ac9d89f --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mon_ingress_ring.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MON_INGRESS_RING_H_ +#define _MON_INGRESS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_MON_INGRESS_RING 4 + +struct mon_ingress_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; +#else + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; +#endif +}; + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/no_ack_report.h b/drivers/staging/fw-api/hw/kiwi/v2/no_ack_report.h new file mode 100644 index 0000000000000000000000000000000000000000..9e545358e5d36ecca7b7b32b5306d3f4bf03f2ea --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/no_ack_report.h @@ -0,0 +1,124 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _NO_ACK_REPORT_H_ +#define _NO_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_NO_ACK_REPORT 4 + +struct no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_ack_transmit_reason : 4, + macrx_abort_reason : 4, + phyrx_abort_reason : 8, + frame_control : 16; + uint32_t rx_ppdu_duration : 24, + sr_ppdu_during_obss : 1, + selfgen_response_reason_to_sr_ppdu : 4, + reserved_1 : 3; + uint32_t pre_bt_broadcast_status_details : 12, + first_bt_broadcast_status_details : 12, + reserved_2 : 8; + uint32_t second_bt_broadcast_status_details : 12, + reserved_3 : 20; +#else + uint32_t frame_control : 16, + phyrx_abort_reason : 8, + macrx_abort_reason : 4, + no_ack_transmit_reason : 4; + uint32_t reserved_1 : 3, + selfgen_response_reason_to_sr_ppdu : 4, + sr_ppdu_during_obss : 1, + rx_ppdu_duration : 24; + uint32_t reserved_2 : 8, + first_bt_broadcast_status_details : 12, + pre_bt_broadcast_status_details : 12; + uint32_t reserved_3 : 20, + second_bt_broadcast_status_details : 12; +#endif +}; + +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f + +#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 + +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 + +#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 +#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 +#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + +#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 +#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff + +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 + +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 + +#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 +#define NO_ACK_REPORT_RESERVED_1_LSB 29 +#define NO_ACK_REPORT_RESERVED_1_MSB 31 +#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 + +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 + +#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 +#define NO_ACK_REPORT_RESERVED_2_LSB 24 +#define NO_ACK_REPORT_RESERVED_2_MSB 31 +#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 + +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c +#define NO_ACK_REPORT_RESERVED_3_LSB 12 +#define NO_ACK_REPORT_RESERVED_3_MSB 31 +#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/kiwi/v2/ofdma_trigger_details.h new file mode 100644 index 0000000000000000000000000000000000000000..86a807ab89f6edd73f26c942ea0d77a8aa6ab24b --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/ofdma_trigger_details.h @@ -0,0 +1,840 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _OFDMA_TRIGGER_DETAILS_H_ +#define _OFDMA_TRIGGER_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22 + +#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 11 + +struct ofdma_trigger_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ax_trigger_source : 1, + rx_trigger_frame_user_source : 2, + received_bandwidth : 3, + txop_duration_all_ones : 1, + eht_trigger_response : 1, + pre_rssi_comb : 8, + rssi_comb : 8, + rxpcu_pcie_l0_req_duration : 8; + uint32_t he_trigger_ul_ppdu_length : 5, + he_trigger_ru_allocation : 8, + he_trigger_dl_tx_power : 5, + he_trigger_ul_target_rssi : 5, + he_trigger_ul_mcs : 2, + he_trigger_reserved : 1, + bss_color : 6; + uint32_t trigger_type : 4, + lsig_response_length : 12, + cascade_indication : 1, + carrier_sense : 1, + bandwidth : 2, + cp_ltf_size : 2, + mu_mimo_ltf_mode : 1, + number_of_ltfs : 3, + stbc : 1, + ldpc_extra_symbol : 1, + ap_tx_power_lsb_part : 4; + uint32_t ap_tx_power_msb_part : 2, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + spatial_reuse : 16, + doppler : 1, + he_siga_reserved : 9, + reserved_3b : 1; + uint32_t aid12 : 12, + ru_allocation : 9, + mcs : 4, + dcm : 1, + start_spatial_stream : 3, + number_of_spatial_stream : 3; + uint32_t target_rssi : 7, + coding_type : 1, + mpdu_mu_spacing_factor : 2, + tid_aggregation_limit : 3, + reserved_5b : 1, + prefered_ac : 2, + bar_control_ack_policy : 1, + bar_control_multi_tid : 1, + bar_control_compressed_bitmap : 1, + bar_control_reserved : 9, + bar_control_tid_info : 4; + uint32_t nr0_per_tid_info_reserved : 12, + nr0_per_tid_info_tid_value : 4, + nr0_start_seq_ctrl_frag_number : 4, + nr0_start_seq_ctrl_start_seq_number : 12; + uint32_t nr1_per_tid_info_reserved : 12, + nr1_per_tid_info_tid_value : 4, + nr1_start_seq_ctrl_frag_number : 4, + nr1_start_seq_ctrl_start_seq_number : 12; + uint32_t nr2_per_tid_info_reserved : 12, + nr2_per_tid_info_tid_value : 4, + nr2_start_seq_ctrl_frag_number : 4, + nr2_start_seq_ctrl_start_seq_number : 12; + uint32_t nr3_per_tid_info_reserved : 12, + nr3_per_tid_info_tid_value : 4, + nr3_start_seq_ctrl_frag_number : 4, + nr3_start_seq_ctrl_start_seq_number : 12; + uint32_t nr4_per_tid_info_reserved : 12, + nr4_per_tid_info_tid_value : 4, + nr4_start_seq_ctrl_frag_number : 4, + nr4_start_seq_ctrl_start_seq_number : 12; + uint32_t nr5_per_tid_info_reserved : 12, + nr5_per_tid_info_tid_value : 4, + nr5_start_seq_ctrl_frag_number : 4, + nr5_start_seq_ctrl_start_seq_number : 12; + uint32_t nr6_per_tid_info_reserved : 12, + nr6_per_tid_info_tid_value : 4, + nr6_start_seq_ctrl_frag_number : 4, + nr6_start_seq_ctrl_start_seq_number : 12; + uint32_t nr7_per_tid_info_reserved : 12, + nr7_per_tid_info_tid_value : 4, + nr7_start_seq_ctrl_frag_number : 4, + nr7_start_seq_ctrl_start_seq_number : 12; + uint32_t fb_segment_retransmission_bitmap : 8, + reserved_14a : 2, + u_sig_puncture_pattern_encoding : 6, + dot11be_puncture_bitmap : 16; + uint32_t rx_chain_mask : 8, + rx_duration_field : 16, + scrambler_seed : 7, + rx_chain_mask_type : 1; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t sw_peer_id : 16, + response_tx_duration : 16; + uint32_t __reserved_g_0005_trigger_subtype : 4, + tbr_trigger_common_info_79_68 : 12, + tbr_trigger_sound_reserved_20_12 : 9, + i2r_rep : 3, + tbr_trigger_sound_reserved_25_24 : 2, + reserved_18a : 1, + qos_null_only_response_tx : 1; + uint32_t tbr_trigger_sound_sac : 16, + reserved_19a : 8, + u_sig_reserved2 : 5, + reserved_19b : 3; + uint32_t eht_special_aid12 : 12, + phy_version : 3, + bandwidth_ext : 2, + eht_spatial_reuse : 8, + u_sig_reserved1 : 7; + uint32_t eht_trigger_special_user_info_71_40 : 32; +#else + uint32_t rxpcu_pcie_l0_req_duration : 8, + rssi_comb : 8, + pre_rssi_comb : 8, + eht_trigger_response : 1, + txop_duration_all_ones : 1, + received_bandwidth : 3, + rx_trigger_frame_user_source : 2, + ax_trigger_source : 1; + uint32_t bss_color : 6, + he_trigger_reserved : 1, + he_trigger_ul_mcs : 2, + he_trigger_ul_target_rssi : 5, + he_trigger_dl_tx_power : 5, + he_trigger_ru_allocation : 8, + he_trigger_ul_ppdu_length : 5; + uint32_t ap_tx_power_lsb_part : 4, + ldpc_extra_symbol : 1, + stbc : 1, + number_of_ltfs : 3, + mu_mimo_ltf_mode : 1, + cp_ltf_size : 2, + bandwidth : 2, + carrier_sense : 1, + cascade_indication : 1, + lsig_response_length : 12, + trigger_type : 4; + uint32_t reserved_3b : 1, + he_siga_reserved : 9, + doppler : 1, + spatial_reuse : 16, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + ap_tx_power_msb_part : 2; + uint32_t number_of_spatial_stream : 3, + start_spatial_stream : 3, + dcm : 1, + mcs : 4, + ru_allocation : 9, + aid12 : 12; + uint32_t bar_control_tid_info : 4, + bar_control_reserved : 9, + bar_control_compressed_bitmap : 1, + bar_control_multi_tid : 1, + bar_control_ack_policy : 1, + prefered_ac : 2, + reserved_5b : 1, + tid_aggregation_limit : 3, + mpdu_mu_spacing_factor : 2, + coding_type : 1, + target_rssi : 7; + uint32_t nr0_start_seq_ctrl_start_seq_number : 12, + nr0_start_seq_ctrl_frag_number : 4, + nr0_per_tid_info_tid_value : 4, + nr0_per_tid_info_reserved : 12; + uint32_t nr1_start_seq_ctrl_start_seq_number : 12, + nr1_start_seq_ctrl_frag_number : 4, + nr1_per_tid_info_tid_value : 4, + nr1_per_tid_info_reserved : 12; + uint32_t nr2_start_seq_ctrl_start_seq_number : 12, + nr2_start_seq_ctrl_frag_number : 4, + nr2_per_tid_info_tid_value : 4, + nr2_per_tid_info_reserved : 12; + uint32_t nr3_start_seq_ctrl_start_seq_number : 12, + nr3_start_seq_ctrl_frag_number : 4, + nr3_per_tid_info_tid_value : 4, + nr3_per_tid_info_reserved : 12; + uint32_t nr4_start_seq_ctrl_start_seq_number : 12, + nr4_start_seq_ctrl_frag_number : 4, + nr4_per_tid_info_tid_value : 4, + nr4_per_tid_info_reserved : 12; + uint32_t nr5_start_seq_ctrl_start_seq_number : 12, + nr5_start_seq_ctrl_frag_number : 4, + nr5_per_tid_info_tid_value : 4, + nr5_per_tid_info_reserved : 12; + uint32_t nr6_start_seq_ctrl_start_seq_number : 12, + nr6_start_seq_ctrl_frag_number : 4, + nr6_per_tid_info_tid_value : 4, + nr6_per_tid_info_reserved : 12; + uint32_t nr7_start_seq_ctrl_start_seq_number : 12, + nr7_start_seq_ctrl_frag_number : 4, + nr7_per_tid_info_tid_value : 4, + nr7_per_tid_info_reserved : 12; + uint32_t dot11be_puncture_bitmap : 16, + u_sig_puncture_pattern_encoding : 6, + reserved_14a : 2, + fb_segment_retransmission_bitmap : 8; + uint32_t rx_chain_mask_type : 1, + scrambler_seed : 7, + rx_duration_field : 16, + rx_chain_mask : 8; + uint32_t normalized_rssi_comb : 8, + normalized_pre_rssi_comb : 8; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint32_t response_tx_duration : 16, + sw_peer_id : 16; + uint32_t qos_null_only_response_tx : 1, + reserved_18a : 1, + tbr_trigger_sound_reserved_25_24 : 2, + i2r_rep : 3, + tbr_trigger_sound_reserved_20_12 : 9, + tbr_trigger_common_info_79_68 : 12, + __reserved_g_0005_trigger_subtype : 4; + uint32_t reserved_19b : 3, + u_sig_reserved2 : 5, + reserved_19a : 8, + tbr_trigger_sound_sac : 16; + uint32_t u_sig_reserved1 : 7, + eht_spatial_reuse : 8, + bandwidth_ext : 2, + phy_version : 3, + eht_special_aid12 : 12; + uint32_t eht_trigger_special_user_info_71_40 : 32; +#endif +}; + +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001 + +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006 + +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038 + +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040 + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080 + +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00 + +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000 + +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000 + +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000 + +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f + +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0 + +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000 + +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000 + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000 + +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000 + +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000 + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000 + +#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000 + +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000 + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000 + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000 + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000 + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000 + +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000 + +#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000 + +#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000 + +#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 +#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 +#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000 + +#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000 + +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000 + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000 + +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000 + +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000 + +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000 + +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000 + +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff + +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00 + +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000 + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000 + +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000 + +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000 + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 + +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000 + +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000000f + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000 + +#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000 + +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000 + +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000 + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000 + +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000 + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/kiwi/v2/pcu_ppdu_setup_init.h new file mode 100644 index 0000000000000000000000000000000000000000..8ff86d18db242ccbc01ad9a5aeb2d5f873865f5c --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/pcu_ppdu_setup_init.h @@ -0,0 +1,2288 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PCU_PPDU_SETUP_INIT_H_ +#define _PCU_PPDU_SETUP_INIT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 + +#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29 + +struct pcu_ppdu_setup_init { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t medium_prot_type : 3, + response_type : 5, + response_info_part2_required : 1, + response_to_response : 3, + mba_user_order : 2, + expected_mba_size : 11, + required_ul_mu_resp_user_count : 6, + transmitted_bssid_check_en : 1; + uint32_t mprot_required_bw1 : 1, + mprot_required_bw20 : 1, + mprot_required_bw40 : 1, + mprot_required_bw80 : 1, + mprot_required_bw160 : 1, + mprot_required_bw240 : 1, + mprot_required_bw320 : 1, + ppdu_allowed_bw1 : 1, + ppdu_allowed_bw20 : 1, + ppdu_allowed_bw40 : 1, + ppdu_allowed_bw80 : 1, + ppdu_allowed_bw160 : 1, + ppdu_allowed_bw240 : 1, + ppdu_allowed_bw320 : 1, + set_fc_pwr_mgt : 1, + use_cts_duration_for_data_tx : 1, + update_timestamp_64 : 1, + update_timestamp_32_lower : 1, + update_timestamp_32_upper : 1, + reserved_1a : 13; + uint32_t insert_timestamp_offset_0 : 16, + insert_timestamp_offset_1 : 16; + uint32_t max_bw40_try_count : 4, + max_bw80_try_count : 4, + max_bw160_try_count : 4, + max_bw240_try_count : 4, + max_bw320_try_count : 4, + insert_wur_timestamp_offset : 6, + update_wur_timestamp : 1, + wur_embedded_bssid_present : 1, + insert_wur_fcs : 1, + reserved_3b : 3; + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_hw_response_tx_duration : 16, + r2r_rx_duration_field : 16; + uint32_t r2r_group_id : 6, + r2r_response_frame_type : 4, + r2r_sta_partial_aid : 11, + use_address_fields_for_protection : 1, + r2r_set_required_response_time : 1, + reserved_29a : 3, + r2r_bw20_active_channel : 3, + r2r_bw40_active_channel : 3; + uint32_t r2r_bw80_active_channel : 3, + r2r_bw160_active_channel : 3, + r2r_bw240_active_channel : 3, + r2r_bw320_active_channel : 3, + r2r_bw20 : 3, + r2r_bw40 : 3, + r2r_bw80 : 3, + r2r_bw160 : 3, + r2r_bw240 : 3, + r2r_bw320 : 3, + reserved_30a : 2; + uint32_t mu_response_expected_bitmap_31_0 : 32; + uint32_t mu_response_expected_bitmap_36_32 : 5, + mu_expected_response_cbf_count : 6, + mu_expected_response_sta_count : 6, + transmit_includes_multidestination : 1, + insert_prev_tx_start_timing_info : 1, + insert_current_tx_start_timing_info : 1, + tx_start_transmit_time_byte_offset : 12; + uint32_t protection_frame_ad1_31_0 : 32; + uint32_t protection_frame_ad1_47_32 : 16, + protection_frame_ad2_15_0 : 16; + uint32_t protection_frame_ad2_47_16 : 32; + uint32_t dynamic_medium_prot_threshold : 24, + dynamic_medium_prot_type : 1, + reserved_54a : 7; + uint32_t protection_frame_ad3_31_0 : 32; + uint32_t protection_frame_ad3_47_32 : 16, + protection_frame_ad4_15_0 : 16; + uint32_t protection_frame_ad4_47_16 : 32; +#else + uint32_t transmitted_bssid_check_en : 1, + required_ul_mu_resp_user_count : 6, + expected_mba_size : 11, + mba_user_order : 2, + response_to_response : 3, + response_info_part2_required : 1, + response_type : 5, + medium_prot_type : 3; + uint32_t reserved_1a : 13, + update_timestamp_32_upper : 1, + update_timestamp_32_lower : 1, + update_timestamp_64 : 1, + use_cts_duration_for_data_tx : 1, + set_fc_pwr_mgt : 1, + ppdu_allowed_bw320 : 1, + ppdu_allowed_bw240 : 1, + ppdu_allowed_bw160 : 1, + ppdu_allowed_bw80 : 1, + ppdu_allowed_bw40 : 1, + ppdu_allowed_bw20 : 1, + ppdu_allowed_bw1 : 1, + mprot_required_bw320 : 1, + mprot_required_bw240 : 1, + mprot_required_bw160 : 1, + mprot_required_bw80 : 1, + mprot_required_bw40 : 1, + mprot_required_bw20 : 1, + mprot_required_bw1 : 1; + uint32_t insert_timestamp_offset_1 : 16, + insert_timestamp_offset_0 : 16; + uint32_t reserved_3b : 3, + insert_wur_fcs : 1, + wur_embedded_bssid_present : 1, + update_wur_timestamp : 1, + insert_wur_timestamp_offset : 6, + max_bw320_try_count : 4, + max_bw240_try_count : 4, + max_bw160_try_count : 4, + max_bw80_try_count : 4, + max_bw40_try_count : 4; + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_rx_duration_field : 16, + r2r_hw_response_tx_duration : 16; + uint32_t r2r_bw40_active_channel : 3, + r2r_bw20_active_channel : 3, + reserved_29a : 3, + r2r_set_required_response_time : 1, + use_address_fields_for_protection : 1, + r2r_sta_partial_aid : 11, + r2r_response_frame_type : 4, + r2r_group_id : 6; + uint32_t reserved_30a : 2, + r2r_bw320 : 3, + r2r_bw240 : 3, + r2r_bw160 : 3, + r2r_bw80 : 3, + r2r_bw40 : 3, + r2r_bw20 : 3, + r2r_bw320_active_channel : 3, + r2r_bw240_active_channel : 3, + r2r_bw160_active_channel : 3, + r2r_bw80_active_channel : 3; + uint32_t mu_response_expected_bitmap_31_0 : 32; + uint32_t tx_start_transmit_time_byte_offset : 12, + insert_current_tx_start_timing_info : 1, + insert_prev_tx_start_timing_info : 1, + transmit_includes_multidestination : 1, + mu_expected_response_sta_count : 6, + mu_expected_response_cbf_count : 6, + mu_response_expected_bitmap_36_32 : 5; + uint32_t protection_frame_ad1_31_0 : 32; + uint32_t protection_frame_ad2_15_0 : 16, + protection_frame_ad1_47_32 : 16; + uint32_t protection_frame_ad2_47_16 : 32; + uint32_t reserved_54a : 7, + dynamic_medium_prot_type : 1, + dynamic_medium_prot_threshold : 24; + uint32_t protection_frame_ad3_31_0 : 32; + uint32_t protection_frame_ad4_15_0 : 16, + protection_frame_ad3_47_32 : 16; + uint32_t protection_frame_ad4_47_16 : 32; +#endif +}; + +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x0000000000000007 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x00000000000000f8 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0000000000000100 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x0000000000000e00 + +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x0000000000003000 + +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x0000000001ffc000 + +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x000000007e000000 + +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 32 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 32 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 33 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 33 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x0000000200000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 34 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 34 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x0000000400000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 35 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 35 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x0000000800000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 36 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 36 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x0000001000000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 37 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 37 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x0000002000000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 38 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 38 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x0000004000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 39 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 39 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x0000008000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 40 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 40 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x0000010000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 41 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 41 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x0000020000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 42 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 42 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 43 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 43 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x0000080000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 44 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 44 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x0000100000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 45 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 45 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x0000200000000000 + +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 46 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 46 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x0000400000000000 + +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 47 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 47 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x0000800000000000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 48 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 48 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x0001000000000000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 49 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 49 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x0002000000000000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 50 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 50 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x0004000000000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff8000000000000 + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x000000000000ffff + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0x00000000ffff0000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 32 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 35 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 36 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 39 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f000000000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 40 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 43 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f0000000000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 44 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 47 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f00000000000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 48 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 51 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f000000000000 + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 52 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 57 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f0000000000000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 58 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 58 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x0400000000000000 + +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 59 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 59 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x0800000000000000 + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 60 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 60 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x1000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xe000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x000000001e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x0000000020000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x0007000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x3800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x0000000000000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x0000000000000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00003c0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MASK 0x0000c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x0000000000002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0x00000000f8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x0000380000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x2000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x0000000000070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x0000000038000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x0000007000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x0000008000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x0000000000003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MASK 0x000000000000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x0000200000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x0000000000003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x0000000003f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x000000001e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x0000000020000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x0007000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x3800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x0000000000000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x0000000000000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00003c0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MASK 0x0000c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x0000000000002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0x00000000f8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x0000380000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x2000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x0000000000070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x0000000038000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x0000007000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x0000008000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x0000000000003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MASK 0x000000000000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x0000200000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x0000000003f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x000000001e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x0000000020000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x0007000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x3800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x0000000000000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x0000000000000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00003c0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MASK 0x0000c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x0000000000002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0x00000000f8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x2000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x0000000000070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x0000000038000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x0000007000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x0000008000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x0000000000003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MASK 0x000000000000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x0000200000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x0000000003f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x000000000000ffff + +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0x00000000ffff0000 + +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 37 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f00000000 + +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 38 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 41 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 42 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 52 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc0000000000 + +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 53 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 53 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x0020000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 54 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 54 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x0040000000000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 55 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x0380000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 58 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 60 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c00000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 61 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 63 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe000000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x0000000000000007 + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x0000000000000038 + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x00000000000001c0 + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x0000000000000e00 + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x0000000000007000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x0000000000038000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x00000000001c0000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x0000000000e00000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x0000000007000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x0000000038000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MASK 0x00000000c0000000 + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff00000000 + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x000000000000001f + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x00000000000007e0 + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x000000000001f800 + +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x0000000000020000 + +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x0000000000040000 + +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x0000000000080000 + +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0x00000000fff00000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff00000000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x000000000000ffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0x00000000ffff0000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff00000000 + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x0000000000ffffff + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x0000000001000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0x00000000fe000000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff00000000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x000000000000ffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0x00000000ffff0000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/pdg_response.h b/drivers/staging/fw-api/hw/kiwi/v2/pdg_response.h new file mode 100644 index 0000000000000000000000000000000000000000..6dff648021113f90bab8259a7a39a8d3474b7b5b --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/pdg_response.h @@ -0,0 +1,479 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PDG_RESPONSE_H_ +#define _PDG_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PDG_RESPONSE 12 + +#define NUM_OF_QWORDS_PDG_RESPONSE 6 + +struct pdg_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t hw_response_tx_duration : 16, + rx_duration_field : 16; + uint32_t punctured_response_transmission : 1, + cca_subband_channel_bonding_mask : 16, + scrambler_seed_override : 2, + response_density_valid : 1, + response_density : 5, + more_data : 1, + duration_indication : 1, + relayed_frame : 1, + address_indicator : 1, + bandwidth : 3; + uint32_t ack_id : 16, + block_ack_bitmap : 16; + uint32_t response_frame_type : 4, + ack_id_ext : 10, + ftm_en : 1, + group_id : 6, + sta_partial_aid : 11; + uint32_t ndp_ba_start_seq_ctrl : 12, + active_channel : 3, + txop_duration_all_ones : 1, + frame_length : 16; +#else + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t rx_duration_field : 16, + hw_response_tx_duration : 16; + uint32_t bandwidth : 3, + address_indicator : 1, + relayed_frame : 1, + duration_indication : 1, + more_data : 1, + response_density : 5, + response_density_valid : 1, + scrambler_seed_override : 2, + cca_subband_channel_bonding_mask : 16, + punctured_response_transmission : 1; + uint32_t block_ack_bitmap : 16, + ack_id : 16; + uint32_t sta_partial_aid : 11, + group_id : 6, + ftm_en : 1, + ack_id_ext : 10, + response_frame_type : 4; + uint32_t frame_length : 16, + txop_duration_all_ones : 1, + active_channel : 3, + ndp_ba_start_seq_ctrl : 12; +#endif +}; + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x000000000000000f + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff00000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 45 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c0000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 46 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c00000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000 + +#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48 +#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63 +#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000 + +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001 + +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe + +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000 + +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000 + +#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 +#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 +#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000 + +#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_MORE_DATA_LSB 25 +#define PDG_RESPONSE_MORE_DATA_MSB 25 +#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000 + +#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000 + +#define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RELAYED_FRAME_LSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MASK 0x0000000008000000 + +#define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x0000000010000000 + +#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_BANDWIDTH_LSB 29 +#define PDG_RESPONSE_BANDWIDTH_MSB 31 +#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000 + +#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_ACK_ID_LSB 32 +#define PDG_RESPONSE_ACK_ID_MSB 47 +#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000 + +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000 + +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f + +#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 +#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 +#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0 + +#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_FTM_EN_LSB 14 +#define PDG_RESPONSE_FTM_EN_MSB 14 +#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000 + +#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_GROUP_ID_LSB 15 +#define PDG_RESPONSE_GROUP_ID_MSB 20 +#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000 + +#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 +#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 +#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000 + +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000 + +#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000 + +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000 + +#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_FRAME_LENGTH_LSB 48 +#define PDG_RESPONSE_FRAME_LENGTH_MSB 63 +#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/pdg_response_rate_setting.h b/drivers/staging/fw-api/hw/kiwi/v2/pdg_response_rate_setting.h new file mode 100644 index 0000000000000000000000000000000000000000..1749452d580904a18bd4524b6f40cc3bd680bc95 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/pdg_response_rate_setting.h @@ -0,0 +1,418 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PDG_RESPONSE_RATE_SETTING_H_ +#define _PDG_RESPONSE_RATE_SETTING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 + +struct pdg_response_rate_setting { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 1, + tx_antenna_sector_ctrl : 24, + pkt_type : 4, + smoothing : 1, + ldpc : 1, + stbc : 1; + uint32_t alt_tx_pwr : 8, + alt_min_tx_pwr : 8, + alt_nss : 3, + alt_tx_chain_mask : 8, + alt_bw : 3, + stf_ltf_3db_boost : 1, + force_extra_symbol : 1; + uint32_t alt_rate_mcs : 4, + nss : 3, + dpd_enable : 1, + tx_pwr : 8, + min_tx_pwr : 8, + tx_chain_mask : 8; + uint32_t reserved_3a : 8, + sgi : 2, + rate_mcs : 4, + reserved_3b : 2, + tx_pwr_1 : 8, + alt_tx_pwr_1 : 8; + uint32_t aggregation : 1, + dot11ax_bss_color_id : 6, + dot11ax_spatial_reuse : 4, + dot11ax_cp_ltf_size : 2, + dot11ax_dcm : 1, + dot11ax_doppler_indication : 1, + dot11ax_su_extended : 1, + dot11ax_min_packet_extension : 2, + dot11ax_pe_nss : 3, + dot11ax_pe_content : 1, + dot11ax_pe_ltf_size : 2, + dot11ax_chain_csd_en : 1, + dot11ax_pe_chain_csd_en : 1, + dot11ax_dl_ul_flag : 1, + reserved_4a : 5; + uint32_t dot11ax_ext_ru_start_index : 4, + dot11ax_ext_ru_size : 4, + eht_duplicate_mode : 2, + he_sigb_dcm : 1, + he_sigb_0_mcs : 3, + num_he_sigb_sym : 5, + required_response_time_source : 1, + reserved_5a : 6, + u_sig_puncture_pattern_encoding : 6; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t required_response_time : 12, + dot11be_params_placeholder : 4; +#else + uint32_t stbc : 1, + ldpc : 1, + smoothing : 1, + pkt_type : 4, + tx_antenna_sector_ctrl : 24, + reserved_0a : 1; + uint32_t force_extra_symbol : 1, + stf_ltf_3db_boost : 1, + alt_bw : 3, + alt_tx_chain_mask : 8, + alt_nss : 3, + alt_min_tx_pwr : 8, + alt_tx_pwr : 8; + uint32_t tx_chain_mask : 8, + min_tx_pwr : 8, + tx_pwr : 8, + dpd_enable : 1, + nss : 3, + alt_rate_mcs : 4; + uint32_t alt_tx_pwr_1 : 8, + tx_pwr_1 : 8, + reserved_3b : 2, + rate_mcs : 4, + sgi : 2, + reserved_3a : 8; + uint32_t reserved_4a : 5, + dot11ax_dl_ul_flag : 1, + dot11ax_pe_chain_csd_en : 1, + dot11ax_chain_csd_en : 1, + dot11ax_pe_ltf_size : 2, + dot11ax_pe_content : 1, + dot11ax_pe_nss : 3, + dot11ax_min_packet_extension : 2, + dot11ax_su_extended : 1, + dot11ax_doppler_indication : 1, + dot11ax_dcm : 1, + dot11ax_cp_ltf_size : 2, + dot11ax_spatial_reuse : 4, + dot11ax_bss_color_id : 6, + aggregation : 1; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_5a : 6, + required_response_time_source : 1, + num_he_sigb_sym : 5, + he_sigb_0_mcs : 3, + he_sigb_dcm : 1, + eht_duplicate_mode : 2, + dot11ax_ext_ru_size : 4, + dot11ax_ext_ru_start_index : 4; + uint32_t dot11be_params_placeholder : 4, + required_response_time : 12; + struct mlo_sta_id_details mlo_sta_id_details_rx; +#endif +}; + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 + +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 + +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 + +#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 + +#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff + +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 + +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f + +#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 + +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 + +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff + +#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 + +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000 + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 + +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 + +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/pdg_tx_req.h b/drivers/staging/fw-api/hw/kiwi/v2/pdg_tx_req.h new file mode 100644 index 0000000000000000000000000000000000000000..a954537e537ed42488f41da8a3abdff8b8f0f0d8 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/pdg_tx_req.h @@ -0,0 +1,105 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PDG_TX_REQ_H_ +#define _PDG_TX_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PDG_TX_REQ 2 + +#define NUM_OF_QWORDS_PDG_TX_REQ 1 + +struct pdg_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_reason : 2, + use_puncture_pattern : 2, + req_bw : 3, + puncture_pattern_number : 6, + reserved_0b : 1, + req_paprd : 1, + duration_field_boundary_valid : 1, + duration_field_boundary : 16; + uint32_t puncture_subband_mask : 16, + reserved_0c : 16; +#else + uint32_t duration_field_boundary : 16, + duration_field_boundary_valid : 1, + req_paprd : 1, + reserved_0b : 1, + puncture_pattern_number : 6, + req_bw : 3, + use_puncture_pattern : 2, + tx_reason : 2; + uint32_t reserved_0c : 16, + puncture_subband_mask : 16; +#endif +}; + +#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_TX_REASON_LSB 0 +#define PDG_TX_REQ_TX_REASON_MSB 1 +#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003 + +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c + +#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_REQ_BW_LSB 4 +#define PDG_TX_REQ_REQ_BW_MSB 6 +#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070 + +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80 + +#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_RESERVED_0B_LSB 13 +#define PDG_TX_REQ_RESERVED_0B_MSB 13 +#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000 + +#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_REQ_PAPRD_LSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000 + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000 + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000 + +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000 + +#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_RESERVED_0C_LSB 48 +#define PDG_TX_REQ_RESERVED_0C_MSB 63 +#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/phytx_abort_request_info.h b/drivers/staging/fw-api/hw/kiwi/v2/phytx_abort_request_info.h new file mode 100644 index 0000000000000000000000000000000000000000..ec6ad5a04f9c7f96eb580f3edb8eb462f6efe67d --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/phytx_abort_request_info.h @@ -0,0 +1,54 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ +#define _PHYTX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 + +struct phytx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t phytx_abort_reason : 8, + user_number : 6, + reserved : 2; +#else + uint16_t reserved : 2, + user_number : 6, + phytx_abort_reason : 8; +#endif +}; + +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 + +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/phytx_ppdu_header_info_request.h b/drivers/staging/fw-api/hw/kiwi/v2/phytx_ppdu_header_info_request.h new file mode 100644 index 0000000000000000000000000000000000000000..8e6e268b02b17f8a06b903078eeadb5a8c9d3d9c --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/phytx_ppdu_header_info_request.h @@ -0,0 +1,56 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ +#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 + +#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 + +struct phytx_ppdu_header_info_request { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t request_type : 5, + reserved : 11; + uint16_t tlv32_padding : 16; +#else + uint16_t reserved : 11, + request_type : 5; + uint16_t tlv32_padding : 16; +#endif +}; + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_15_8.h b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_15_8.h new file mode 100644 index 0000000000000000000000000000000000000000..df9b22bc137659e79c69872d86d38e50c8968e58 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_15_8.h @@ -0,0 +1,1132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ +#define _RECEIVED_RESPONSE_USER_15_8_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32 + +struct received_response_user_15_8 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#else + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#endif +}; + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_23_16.h b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_23_16.h new file mode 100644 index 0000000000000000000000000000000000000000..3a7f724d76583b64d08d2a7a211fc401c4ac3b09 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_23_16.h @@ -0,0 +1,1132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ +#define _RECEIVED_RESPONSE_USER_23_16_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32 + +struct received_response_user_23_16 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#else + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#endif +}; + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_31_24.h b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_31_24.h new file mode 100644 index 0000000000000000000000000000000000000000..db8fd4fa68a8f442d8aae46e68275b0091e4486c --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_31_24.h @@ -0,0 +1,1132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ +#define _RECEIVED_RESPONSE_USER_31_24_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32 + +struct received_response_user_31_24 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#else + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#endif +}; + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_36_32.h b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_36_32.h new file mode 100644 index 0000000000000000000000000000000000000000..e4748fa8e304982a7dda55d5ffcf966da5605cc6 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_36_32.h @@ -0,0 +1,721 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ +#define _RECEIVED_RESPONSE_USER_36_32_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20 + +struct received_response_user_36_32 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#else + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#endif +}; + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_7_0.h b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_7_0.h new file mode 100644 index 0000000000000000000000000000000000000000..53d81ee64a51c7435bcfc6fd7c39950d08af9c87 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_7_0.h @@ -0,0 +1,1132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ +#define _RECEIVED_RESPONSE_USER_7_0_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32 + +struct received_response_user_7_0 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#else + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#endif +}; + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_info.h b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..500b5c456c16d8b79953b64ad830be7764af072b --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_info.h @@ -0,0 +1,222 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ +#define _RECEIVED_RESPONSE_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 + +struct received_response_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_fcs_pass_count : 12, + mpdu_fcs_fail_count : 12, + qosnull_frame_count : 4, + reserved_0a : 3, + user_info_valid : 1; + uint32_t null_delimiter_count : 22, + reserved_1a : 9, + ht_control_valid : 1; + uint32_t ht_control : 32; + uint32_t qos_control_valid : 16, + eosp : 16; + uint32_t qos_control_15_8_tid_0 : 8, + qos_control_15_8_tid_1 : 8, + qos_control_15_8_tid_2 : 8, + qos_control_15_8_tid_3 : 8; + uint32_t qos_control_15_8_tid_4 : 8, + qos_control_15_8_tid_5 : 8, + qos_control_15_8_tid_6 : 8, + qos_control_15_8_tid_7 : 8; + uint32_t qos_control_15_8_tid_8 : 8, + qos_control_15_8_tid_9 : 8, + qos_control_15_8_tid_10 : 8, + qos_control_15_8_tid_11 : 8; + uint32_t qos_control_15_8_tid_12 : 8, + qos_control_15_8_tid_13 : 8, + qos_control_15_8_tid_14 : 8, + qos_control_15_8_tid_15 : 8; +#else + uint32_t user_info_valid : 1, + reserved_0a : 3, + qosnull_frame_count : 4, + mpdu_fcs_fail_count : 12, + mpdu_fcs_pass_count : 12; + uint32_t ht_control_valid : 1, + reserved_1a : 9, + null_delimiter_count : 22; + uint32_t ht_control : 32; + uint32_t eosp : 16, + qos_control_valid : 16; + uint32_t qos_control_15_8_tid_3 : 8, + qos_control_15_8_tid_2 : 8, + qos_control_15_8_tid_1 : 8, + qos_control_15_8_tid_0 : 8; + uint32_t qos_control_15_8_tid_7 : 8, + qos_control_15_8_tid_6 : 8, + qos_control_15_8_tid_5 : 8, + qos_control_15_8_tid_4 : 8; + uint32_t qos_control_15_8_tid_11 : 8, + qos_control_15_8_tid_10 : 8, + qos_control_15_8_tid_9 : 8, + qos_control_15_8_tid_8 : 8; + uint32_t qos_control_15_8_tid_15 : 8, + qos_control_15_8_tid_14 : 8, + qos_control_15_8_tid_13 : 8, + qos_control_15_8_tid_12 : 8; +#endif +}; + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_trigger_info.h b/drivers/staging/fw-api/hw/kiwi/v2/received_trigger_info.h new file mode 100644 index 0000000000000000000000000000000000000000..047d20f508d1862ab43be0a371a2b1e9c1b050ea --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_trigger_info.h @@ -0,0 +1,130 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_TRIGGER_INFO_H_ +#define _RECEIVED_TRIGGER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_trigger_info_details.h" +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6 + +#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3 + +struct received_trigger_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_trigger_info_details received_trigger_details; + uint32_t tlv64_padding : 32; +#else + struct received_trigger_info_details received_trigger_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000001e000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_LSB 29 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MASK 0x00000000e0000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 60 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0xf000000000000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 48 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xffff000000000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_OFFSET 0x0000000000000010 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_LSB 32 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MSB 63 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_trigger_info_details.h b/drivers/staging/fw-api/hw/kiwi/v2/received_trigger_info_details.h new file mode 100644 index 0000000000000000000000000000000000000000..61e59fa4788c3a3ffd7915d8dab8f9920378f627 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_trigger_info_details.h @@ -0,0 +1,152 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ +#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5 + +struct received_trigger_info_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t trigger_type : 4, + ax_trigger_source : 1, + ax_trigger_type : 4, + trigger_source_sta_full_aid : 13, + frame_control_valid : 1, + qos_control_valid : 1, + he_control_info_valid : 1, + __reserved_g_0005_trigger_subtype : 4, + reserved_0b : 3; + uint32_t phy_ppdu_id : 16, + lsig_response_length : 12, + reserved_1a : 4; + uint32_t frame_control : 16, + qos_control : 16; + uint32_t sw_peer_id : 16, + reserved_3a : 16; + uint32_t he_control : 32; +#else + uint32_t reserved_0b : 3, + __reserved_g_0005_trigger_subtype : 4, + he_control_info_valid : 1, + qos_control_valid : 1, + frame_control_valid : 1, + trigger_source_sta_full_aid : 13, + ax_trigger_type : 4, + ax_trigger_source : 1, + trigger_type : 4; + uint32_t reserved_1a : 4, + lsig_response_length : 12, + phy_ppdu_id : 16; + uint32_t qos_control : 16, + frame_control : 16; + uint32_t reserved_3a : 16, + sw_peer_id : 16; + uint32_t he_control : 32; +#endif +}; + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_LSB 29 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MASK 0xe0000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xffff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/response_end_status.h b/drivers/staging/fw-api/hw/kiwi/v2/response_end_status.h new file mode 100644 index 0000000000000000000000000000000000000000..287618e10f25ea4ec366012d76e4cb6a4cc35669 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/response_end_status.h @@ -0,0 +1,468 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RESPONSE_END_STATUS_H_ +#define _RESPONSE_END_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_RESPONSE_END_STATUS 22 + +#define NUM_OF_QWORDS_RESPONSE_END_STATUS 11 + +struct response_end_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t coex_bt_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_wlan_tx_while_wlan_tx : 1, + global_data_underflow_warning : 1, + response_transmit_status : 4, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + generated_response : 3, + mba_user_count : 7, + mba_fake_bitmap_count : 7, + coex_based_tx_bw : 3, + trig_response_related : 1, + dpdtrain_done : 1; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t cbf_segment_request_mask : 8, + cbf_segment_sent_mask : 8; + uint32_t underflow_mpdu_count : 9, + data_underflow_warning : 2, + phy_tx_gain_setting : 8, + timing_status : 2, + only_null_delim_sent : 1, + brp_info_valid : 1, + reserved_2a : 9; + uint32_t mu_response_bitmap_31_0 : 32; + uint32_t mu_response_bitmap_36_32 : 5, + reserved_4a : 11, + transmit_delay : 16; + uint32_t start_of_frame_timestamp_15_0 : 16, + start_of_frame_timestamp_31_16 : 16; + uint32_t end_of_frame_timestamp_15_0 : 16, + end_of_frame_timestamp_31_16 : 16; + uint32_t tx_group_delay : 12, + reserved_7a : 4, + tpc_dbg_info_cmn_15_0 : 16; + uint32_t tpc_dbg_info_31_16 : 16, + tpc_dbg_info_47_32 : 16; + uint32_t tpc_dbg_info_chn1_15_0 : 16, + tpc_dbg_info_chn1_31_16 : 16; + uint32_t tpc_dbg_info_chn1_47_32 : 16, + tpc_dbg_info_chn1_63_48 : 16; + uint32_t tpc_dbg_info_chn1_79_64 : 16, + tpc_dbg_info_chn2_15_0 : 16; + uint32_t tpc_dbg_info_chn2_31_16 : 16, + tpc_dbg_info_chn2_47_32 : 16; + uint32_t tpc_dbg_info_chn2_63_48 : 16, + tpc_dbg_info_chn2_79_64 : 16; + uint32_t phytx_tx_end_sw_info_15_0 : 16, + phytx_tx_end_sw_info_31_16 : 16; + uint32_t phytx_tx_end_sw_info_47_32 : 16, + phytx_tx_end_sw_info_63_48 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t addr3_47_32 : 16, + __reserved_g_0005 : 1, + secure : 1, + __reserved_g_0005_ftm_frame_sent : 1, + reserved_20a : 13; + uint32_t tlv64_padding : 32; +#else + uint32_t dpdtrain_done : 1, + trig_response_related : 1, + coex_based_tx_bw : 3, + mba_fake_bitmap_count : 7, + mba_user_count : 7, + generated_response : 3, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + response_transmit_status : 4, + global_data_underflow_warning : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_tx : 1; + uint32_t cbf_segment_sent_mask : 8, + cbf_segment_request_mask : 8; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t reserved_2a : 9, + brp_info_valid : 1, + only_null_delim_sent : 1, + timing_status : 2, + phy_tx_gain_setting : 8, + data_underflow_warning : 2, + underflow_mpdu_count : 9; + uint32_t mu_response_bitmap_31_0 : 32; + uint32_t transmit_delay : 16, + reserved_4a : 11, + mu_response_bitmap_36_32 : 5; + uint32_t start_of_frame_timestamp_31_16 : 16, + start_of_frame_timestamp_15_0 : 16; + uint32_t end_of_frame_timestamp_31_16 : 16, + end_of_frame_timestamp_15_0 : 16; + uint32_t tpc_dbg_info_cmn_15_0 : 16, + reserved_7a : 4, + tx_group_delay : 12; + uint32_t tpc_dbg_info_47_32 : 16, + tpc_dbg_info_31_16 : 16; + uint32_t tpc_dbg_info_chn1_31_16 : 16, + tpc_dbg_info_chn1_15_0 : 16; + uint32_t tpc_dbg_info_chn1_63_48 : 16, + tpc_dbg_info_chn1_47_32 : 16; + uint32_t tpc_dbg_info_chn2_15_0 : 16, + tpc_dbg_info_chn1_79_64 : 16; + uint32_t tpc_dbg_info_chn2_47_32 : 16, + tpc_dbg_info_chn2_31_16 : 16; + uint32_t tpc_dbg_info_chn2_79_64 : 16, + tpc_dbg_info_chn2_63_48 : 16; + uint32_t phytx_tx_end_sw_info_31_16 : 16, + phytx_tx_end_sw_info_15_0 : 16; + uint32_t phytx_tx_end_sw_info_63_48 : 16, + phytx_tx_end_sw_info_47_32 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t reserved_20a : 13, + __reserved_g_0005_ftm_frame_sent : 1, + secure : 1, + __reserved_g_0005 : 1, + addr3_47_32 : 16; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 + +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000002 + +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 + +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 + +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 + +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 + +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 + +#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 + +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 + +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 + +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 + +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_LSB 31 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_MSB 31 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_MASK 0x0000000080000000 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 + +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 + +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff + +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 + +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_LSB 11 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MSB 18 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MASK 0x000000000007f800 + +#define RESPONSE_END_STATUS_TIMING_STATUS_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_TIMING_STATUS_LSB 19 +#define RESPONSE_END_STATUS_TIMING_STATUS_MSB 20 +#define RESPONSE_END_STATUS_TIMING_STATUS_MASK 0x0000000000180000 + +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 + +#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 + +#define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_RESERVED_2A_LSB 23 +#define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_2A_MASK 0x00000000ff800000 + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f + +#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 +#define RESPONSE_END_STATUS_RESERVED_4A_MSB 15 +#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x000000000000ffe0 + +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_LSB 16 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_MSB 31 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_LSB 32 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_MSB 43 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_MASK 0x00000fff00000000 + +#define RESPONSE_END_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_RESERVED_7A_LSB 44 +#define RESPONSE_END_STATUS_RESERVED_7A_MSB 47 +#define RESPONSE_END_STATUS_RESERVED_7A_MASK 0x0000f00000000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 +#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0x00000000ffffffff + +#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 32 +#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 47 +#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 48 +#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 63 +#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000048 +#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 +#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 +#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0x00000000ffffffff + +#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000048 +#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 32 +#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 63 +#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff00000000 + +#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 +#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 +#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_SECURE_LSB 17 +#define RESPONSE_END_STATUS_SECURE_MSB 17 +#define RESPONSE_END_STATUS_SECURE_MASK 0x0000000000020000 + +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x0000000000040000 + +#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 +#define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0x00000000fff80000 + +#define RESPONSE_END_STATUS_TLV64_PADDING_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_TLV64_PADDING_LSB 32 +#define RESPONSE_END_STATUS_TLV64_PADDING_MSB 63 +#define RESPONSE_END_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/response_start_status.h b/drivers/staging/fw-api/hw/kiwi/v2/response_start_status.h new file mode 100644 index 0000000000000000000000000000000000000000..4556dcd5a1b41b4675aa7dd7f197520be7408082 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/response_start_status.h @@ -0,0 +1,79 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RESPONSE_START_STATUS_H_ +#define _RESPONSE_START_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 + +#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 + +struct response_start_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t generated_response : 3, + __reserved_g_0012 : 2, + trig_response_related : 1, + response_sta_count : 7, + reserved : 19; + uint32_t phy_ppdu_id : 16, + sw_peer_id : 16; +#else + uint32_t reserved : 19, + response_sta_count : 7, + trig_response_related : 1, + __reserved_g_0012 : 2, + generated_response : 3; + uint32_t sw_peer_id : 16, + phy_ppdu_id : 16; +#endif +}; + +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 + +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 + +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 + +#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_RESERVED_LSB 13 +#define RESPONSE_START_STATUS_RESERVED_MSB 31 +#define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffffe000 + +#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 + +#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 +#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 +#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/ru_allocation_160_info.h b/drivers/staging/fw-api/hw/kiwi/v2/ru_allocation_160_info.h new file mode 100644 index 0000000000000000000000000000000000000000..e622b5dd713eefdb3c7132086c2735d3592973dd --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/ru_allocation_160_info.h @@ -0,0 +1,131 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RU_ALLOCATION_160_INFO_H_ +#define _RU_ALLOCATION_160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 + +struct ru_allocation_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation_band0_0 : 9, + ru_allocation_band0_1 : 9, + reserved_0a : 6, + ru_allocations_01_subband80_mask : 4, + ru_allocations_23_subband80_mask : 4; + uint32_t ru_allocation_band0_2 : 9, + ru_allocation_band0_3 : 9, + reserved_1a : 14; + uint32_t ru_allocation_band1_0 : 9, + ru_allocation_band1_1 : 9, + reserved_2a : 14; + uint32_t ru_allocation_band1_2 : 9, + ru_allocation_band1_3 : 9, + reserved_3a : 14; +#else + uint32_t ru_allocations_23_subband80_mask : 4, + ru_allocations_01_subband80_mask : 4, + reserved_0a : 6, + ru_allocation_band0_1 : 9, + ru_allocation_band0_0 : 9; + uint32_t reserved_1a : 14, + ru_allocation_band0_3 : 9, + ru_allocation_band0_2 : 9; + uint32_t reserved_2a : 14, + ru_allocation_band1_1 : 9, + ru_allocation_band1_0 : 9; + uint32_t reserved_3a : 14, + ru_allocation_band1_3 : 9, + ru_allocation_band1_2 : 9; +#endif +}; + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_1k_bitmap_ack.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_1k_bitmap_ack.h new file mode 100644 index 0000000000000000000000000000000000000000..f58e7f9f03dc81c105a91ccc7280c64b2edc4ef1 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_1k_bitmap_ack.h @@ -0,0 +1,350 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ +#define _RX_FRAME_1K_BITMAP_ACK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 + +#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 + +struct rx_frame_1k_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 5, + ba_bitmap_size : 2, + reserved_0b : 3, + ba_tid : 4, + sta_full_aid : 13, + reserved_0c : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_ctrl : 16, + ba_ts_seq : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t ba_ts_bitmap_287_256 : 32; + uint32_t ba_ts_bitmap_319_288 : 32; + uint32_t ba_ts_bitmap_351_320 : 32; + uint32_t ba_ts_bitmap_383_352 : 32; + uint32_t ba_ts_bitmap_415_384 : 32; + uint32_t ba_ts_bitmap_447_416 : 32; + uint32_t ba_ts_bitmap_479_448 : 32; + uint32_t ba_ts_bitmap_511_480 : 32; + uint32_t ba_ts_bitmap_543_512 : 32; + uint32_t ba_ts_bitmap_575_544 : 32; + uint32_t ba_ts_bitmap_607_576 : 32; + uint32_t ba_ts_bitmap_639_608 : 32; + uint32_t ba_ts_bitmap_671_640 : 32; + uint32_t ba_ts_bitmap_703_672 : 32; + uint32_t ba_ts_bitmap_735_704 : 32; + uint32_t ba_ts_bitmap_767_736 : 32; + uint32_t ba_ts_bitmap_799_768 : 32; + uint32_t ba_ts_bitmap_831_800 : 32; + uint32_t ba_ts_bitmap_863_832 : 32; + uint32_t ba_ts_bitmap_895_864 : 32; + uint32_t ba_ts_bitmap_927_896 : 32; + uint32_t ba_ts_bitmap_959_928 : 32; + uint32_t ba_ts_bitmap_991_960 : 32; + uint32_t ba_ts_bitmap_1023_992 : 32; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0c : 5, + sta_full_aid : 13, + ba_tid : 4, + reserved_0b : 3, + ba_bitmap_size : 2, + reserved_0a : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_seq : 16, + ba_ts_ctrl : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t ba_ts_bitmap_287_256 : 32; + uint32_t ba_ts_bitmap_319_288 : 32; + uint32_t ba_ts_bitmap_351_320 : 32; + uint32_t ba_ts_bitmap_383_352 : 32; + uint32_t ba_ts_bitmap_415_384 : 32; + uint32_t ba_ts_bitmap_447_416 : 32; + uint32_t ba_ts_bitmap_479_448 : 32; + uint32_t ba_ts_bitmap_511_480 : 32; + uint32_t ba_ts_bitmap_543_512 : 32; + uint32_t ba_ts_bitmap_575_544 : 32; + uint32_t ba_ts_bitmap_607_576 : 32; + uint32_t ba_ts_bitmap_639_608 : 32; + uint32_t ba_ts_bitmap_671_640 : 32; + uint32_t ba_ts_bitmap_703_672 : 32; + uint32_t ba_ts_bitmap_735_704 : 32; + uint32_t ba_ts_bitmap_767_736 : 32; + uint32_t ba_ts_bitmap_799_768 : 32; + uint32_t ba_ts_bitmap_831_800 : 32; + uint32_t ba_ts_bitmap_863_832 : 32; + uint32_t ba_ts_bitmap_895_864 : 32; + uint32_t ba_ts_bitmap_927_896 : 32; + uint32_t ba_ts_bitmap_959_928 : 32; + uint32_t ba_ts_bitmap_991_960 : 32; + uint32_t ba_ts_bitmap_1023_992 : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f + +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000380 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 + +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000030 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000038 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000040 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000048 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000050 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000058 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000060 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000068 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000070 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000078 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000080 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000088 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000090 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_bitmap_ack.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_bitmap_ack.h new file mode 100644 index 0000000000000000000000000000000000000000..e0f3b8e931e17378de9775e1695eb2f174bcea34 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_bitmap_ack.h @@ -0,0 +1,196 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_FRAME_BITMAP_ACK_H_ +#define _RX_FRAME_BITMAP_ACK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 + +#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 + +struct rx_frame_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_bitmap_available : 1, + explicit_ack : 1, + explict_ack_type : 3, + ba_bitmap_size : 2, + reserved_0a : 3, + ba_tid : 4, + sta_full_aid : 13, + reserved_0b : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_ctrl : 16, + ba_ts_seq : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0b : 5, + sta_full_aid : 13, + ba_tid : 4, + reserved_0a : 3, + ba_bitmap_size : 2, + explict_ack_type : 3, + explicit_ack : 1, + no_bitmap_available : 1; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_seq : 16, + ba_ts_ctrl : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 + +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 + +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c + +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 + +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000380 + +#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 + +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 + +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 + +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 32 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 63 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff + +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 + +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 32 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 63 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff + +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000030 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_LSB 32 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MSB 63 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_bitmap_req.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_bitmap_req.h new file mode 100644 index 0000000000000000000000000000000000000000..de968d0021a13db19cefb5f6a5092b3e0b28f519 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_bitmap_req.h @@ -0,0 +1,91 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_FRAME_BITMAP_REQ_H_ +#define _RX_FRAME_BITMAP_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2 + +#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1 + +struct rx_frame_bitmap_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t explicit_user_request : 1, + user_request_type : 1, + user_number : 6, + sw_peer_id : 16, + tid_specific_request : 1, + requested_tid : 4, + reserved_0 : 3; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0 : 3, + requested_tid : 4, + tid_specific_request : 1, + sw_peer_id : 16, + user_number : 6, + user_request_type : 1, + explicit_user_request : 1; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x0000000000000001 + +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x0000000000000002 + +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x00000000000000fc + +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x0000000000ffff00 + +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x0000000001000000 + +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x000000001e000000 + +#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0x00000000e0000000 + +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB 32 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB 63 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_ppdu_ack_report.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_ppdu_ack_report.h new file mode 100644 index 0000000000000000000000000000000000000000..3448121a249815c04397f9be268f8aa7c216a926 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_ppdu_ack_report.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_ACK_REPORT_H_ +#define _RX_PPDU_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2 + +#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1 + +struct rx_ppdu_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ack_report ack_report_details; + uint32_t tlv64_padding : 32; +#else + struct ack_report ack_report_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x000000000000000f + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000000f0 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x0000000000000100 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x000000000000fe00 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 + +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB 32 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB 63 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_ppdu_no_ack_report.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_ppdu_no_ack_report.h new file mode 100644 index 0000000000000000000000000000000000000000..3f7778ff5156623b78091491510d52908daa272c --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_ppdu_no_ack_report.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_NO_ACK_REPORT_H_ +#define _RX_PPDU_NO_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "no_ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 + +#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2 + +struct rx_ppdu_no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct no_ack_report no_ack_report_details; +#else + struct no_ack_report no_ack_report_details; +#endif +}; + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x000000000000000f + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000f0 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000000000ff00 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 32 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 55 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff00000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 56 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 56 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x0100000000000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 61 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 63 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe000000000000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0x00000000ff000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 44 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 63 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff00000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_preamble.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_preamble.h new file mode 100644 index 0000000000000000000000000000000000000000..2c60b26ac7759945859107c044e78e64ca7c4c71 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_preamble.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PREAMBLE_H_ +#define _RX_PREAMBLE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_PREAMBLE 2 + +#define NUM_OF_QWORDS_RX_PREAMBLE 1 + +struct rx_preamble { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, + pkt_type : 4, + direction : 1, + reserved_0a : 21; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 21, + direction : 1, + pkt_type : 4, + num_users : 6; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_PREAMBLE_NUM_USERS_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_NUM_USERS_LSB 0 +#define RX_PREAMBLE_NUM_USERS_MSB 5 +#define RX_PREAMBLE_NUM_USERS_MASK 0x000000000000003f + +#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_PKT_TYPE_LSB 6 +#define RX_PREAMBLE_PKT_TYPE_MSB 9 +#define RX_PREAMBLE_PKT_TYPE_MASK 0x00000000000003c0 + +#define RX_PREAMBLE_DIRECTION_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_DIRECTION_LSB 10 +#define RX_PREAMBLE_DIRECTION_MSB 10 +#define RX_PREAMBLE_DIRECTION_MASK 0x0000000000000400 + +#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_RESERVED_0A_LSB 11 +#define RX_PREAMBLE_RESERVED_0A_MSB 31 +#define RX_PREAMBLE_RESERVED_0A_MASK 0x00000000fffff800 + +#define RX_PREAMBLE_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_TLV64_PADDING_LSB 32 +#define RX_PREAMBLE_TLV64_PADDING_MSB 63 +#define RX_PREAMBLE_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_response_required_info.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_response_required_info.h new file mode 100644 index 0000000000000000000000000000000000000000..01c3b946ea6d0fbafdf0c0fd7a99b1ee4cb1b860 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_response_required_info.h @@ -0,0 +1,709 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ +#define _RX_RESPONSE_REQUIRED_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 + +#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 + +struct rx_response_required_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + su_or_uplink_mu_reception : 1, + trigger_frame_received : 1, + __reserved_g_0012 : 2, + tb___reserved_g_0005_response_required : 2, + mac_security : 1, + filter_pass_monitor_ovrd : 1, + ast_search_incomplete : 1, + r2r_end_status_to_follow : 1, + reserved_0a : 2, + three_or_more_type_subtypes : 1, + wait_sifs_config_valid : 1, + wait_sifs : 2; + uint32_t general_frame_control : 16, + second_frame_control : 16; + uint32_t duration : 16, + pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4, + sgi : 2, + stbc : 1, + ldpc : 1, + ampdu : 1, + vht_ack : 1, + rts_ta_grp_bit : 1; + uint32_t ctrl_frame_soliciting_resp : 1, + ast_fail_for_dot11ax_su_ext : 1, + service_dynamic : 1, + m_pkt : 1, + sta_partial_aid : 12, + group_id : 6, + ctrl_resp_pwr_mgmt : 1, + response_indication : 2, + ndp_indication : 1, + ndp_frame_type : 3, + second_frame_control_valid : 1, + reserved_3a : 2; + uint32_t ack_id : 16, + ack_id_ext : 10, + agc_cbw : 3, + service_cbw : 3; + uint32_t response_sta_count : 7, + reserved : 4, + ht_vht_sig_cbw : 3, + cts_cbw : 3, + response_ack_count : 7, + response_assoc_ack_count : 7, + txop_duration_all_ones : 1; + uint32_t response_ba32_count : 7, + response_ba64_count : 7, + response_ba128_count : 7, + response_ba256_count : 7, + multi_tid : 1, + sw_response_tlv_from_crypto : 1, + dot11ax_dl_ul_flag : 1, + reserved_6a : 1; + uint32_t sw_response_frame_length : 16, + response_ba512_count : 7, + response_ba1024_count : 7, + reserved_7a : 2; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t dot11ax_received_format_indication : 1, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_bss_color_id : 6, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_cp_size : 2, + dot11ax_received_ltf_size : 2, + dot11ax_received_coding : 1, + dot11ax_received_dcm : 1, + dot11ax_received_doppler_indication : 1, + dot11ax_received_ext_ru_size : 4, + ftm_fields_valid : 1, + ftm_pe_nss : 3, + ftm_pe_ltf_size : 2, + ftm_pe_content : 1, + ftm_chain_csd_en : 1, + ftm_pe_chain_csd_en : 1; + uint32_t dot11ax_response_rate_source : 8, + dot11ax_ext_response_rate_source : 8, + sw_peer_id : 16; + uint32_t dot11be_puncture_bitmap : 16, + dot11be_response : 1, + punctured_response : 1, + eht_duplicate_mode : 2, + force_extra_symbol : 1, + reserved_13a : 5, + u_sig_puncture_pattern_encoding : 6; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t he_a_control_response_time : 12, + reserved_after_struct16 : 4; + uint32_t tlv64_padding : 32; +#else + uint32_t wait_sifs : 2, + wait_sifs_config_valid : 1, + three_or_more_type_subtypes : 1, + reserved_0a : 2, + r2r_end_status_to_follow : 1, + ast_search_incomplete : 1, + filter_pass_monitor_ovrd : 1, + mac_security : 1, + tb___reserved_g_0005_response_required : 2, + __reserved_g_0012 : 2, + trigger_frame_received : 1, + su_or_uplink_mu_reception : 1, + phy_ppdu_id : 16; + uint32_t second_frame_control : 16, + general_frame_control : 16; + uint32_t rts_ta_grp_bit : 1, + vht_ack : 1, + ampdu : 1, + ldpc : 1, + stbc : 1, + sgi : 2, + rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4, + duration : 16; + uint32_t reserved_3a : 2, + second_frame_control_valid : 1, + ndp_frame_type : 3, + ndp_indication : 1, + response_indication : 2, + ctrl_resp_pwr_mgmt : 1, + group_id : 6, + sta_partial_aid : 12, + m_pkt : 1, + service_dynamic : 1, + ast_fail_for_dot11ax_su_ext : 1, + ctrl_frame_soliciting_resp : 1; + uint32_t service_cbw : 3, + agc_cbw : 3, + ack_id_ext : 10, + ack_id : 16; + uint32_t txop_duration_all_ones : 1, + response_assoc_ack_count : 7, + response_ack_count : 7, + cts_cbw : 3, + ht_vht_sig_cbw : 3, + reserved : 4, + response_sta_count : 7; + uint32_t reserved_6a : 1, + dot11ax_dl_ul_flag : 1, + sw_response_tlv_from_crypto : 1, + multi_tid : 1, + response_ba256_count : 7, + response_ba128_count : 7, + response_ba64_count : 7, + response_ba32_count : 7; + uint32_t reserved_7a : 2, + response_ba1024_count : 7, + response_ba512_count : 7, + sw_response_frame_length : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ftm_pe_chain_csd_en : 1, + ftm_chain_csd_en : 1, + ftm_pe_content : 1, + ftm_pe_ltf_size : 2, + ftm_pe_nss : 3, + ftm_fields_valid : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_received_doppler_indication : 1, + dot11ax_received_dcm : 1, + dot11ax_received_coding : 1, + dot11ax_received_ltf_size : 2, + dot11ax_received_cp_size : 2, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_bss_color_id : 6, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_format_indication : 1; + uint32_t sw_peer_id : 16, + dot11ax_ext_response_rate_source : 8, + dot11ax_response_rate_source : 8; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_13a : 5, + force_extra_symbol : 1, + eht_duplicate_mode : 2, + punctured_response : 1, + dot11be_response : 1, + dot11be_puncture_bitmap : 16; + uint32_t reserved_after_struct16 : 4, + he_a_control_response_time : 12; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff + +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 + +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 + +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000300000 + +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 + +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 + +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 + +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MASK 0x000000000c000000 + +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 + +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff + +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 + +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000001e00000 + +#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x0000000006000000 + +#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000008000000 + +#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000010000000 + +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000020000000 + +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x0000000040000000 + +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 + +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 + +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 + +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 + +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0xc000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x000000000000ffff + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 + +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 39 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000078000000000 + +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 + +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 + +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MASK 0x0000000080000000 + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 + +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 53 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e0000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 + +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_start_param.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_start_param.h new file mode 100644 index 0000000000000000000000000000000000000000..364538c2c017fbeee79887433515c6b3fe44fe87 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_start_param.h @@ -0,0 +1,63 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_START_PARAM_H_ +#define _RX_START_PARAM_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_START_PARAM 2 + +#define NUM_OF_QWORDS_RX_START_PARAM 1 + +struct rx_start_param { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, + reserved_0a : 12, + remaining_rx_time : 16; + uint32_t tlv64_padding : 32; +#else + uint32_t remaining_rx_time : 16, + reserved_0a : 12, + pkt_type : 4; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_START_PARAM_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_START_PARAM_PKT_TYPE_LSB 0 +#define RX_START_PARAM_PKT_TYPE_MSB 3 +#define RX_START_PARAM_PKT_TYPE_MASK 0x000000000000000f + +#define RX_START_PARAM_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_START_PARAM_RESERVED_0A_LSB 4 +#define RX_START_PARAM_RESERVED_0A_MSB 15 +#define RX_START_PARAM_RESERVED_0A_MASK 0x000000000000fff0 + +#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x0000000000000000 +#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 +#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 +#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0x00000000ffff0000 + +#define RX_START_PARAM_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_START_PARAM_TLV64_PADDING_LSB 32 +#define RX_START_PARAM_TLV64_PADDING_MSB 63 +#define RX_START_PARAM_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_trig_info.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_trig_info.h new file mode 100644 index 0000000000000000000000000000000000000000..c246aa15f98608a9c6508f3103bffdeceb88d4e6 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_trig_info.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_TRIG_INFO_H_ +#define _RX_TRIG_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_TRIG_INFO 2 + +#define NUM_OF_QWORDS_RX_TRIG_INFO 1 + +struct rx_trig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_trigger_frame_type : 2, + trigger_resp_type : 3, + reserved_0 : 27; + uint32_t ppdu_duration : 16, + unique_destination_id : 16; +#else + uint32_t reserved_0 : 27, + trigger_resp_type : 3, + rx_trigger_frame_type : 2; + uint32_t unique_destination_id : 16, + ppdu_duration : 16; +#endif +}; + +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003 + +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c + +#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_RESERVED_0_LSB 5 +#define RX_TRIG_INFO_RESERVED_0_MSB 31 +#define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0 + +#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_PPDU_DURATION_LSB 32 +#define RX_TRIG_INFO_PPDU_DURATION_MSB 47 +#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000 + +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rxpcu_early_rx_indication.h b/drivers/staging/fw-api/hw/kiwi/v2/rxpcu_early_rx_indication.h new file mode 100644 index 0000000000000000000000000000000000000000..4761a1dacd3e2974bcf817ab4abd6e2081ddcbd4 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rxpcu_early_rx_indication.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RXPCU_EARLY_RX_INDICATION_H_ +#define _RXPCU_EARLY_RX_INDICATION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2 + +#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1 + +struct rxpcu_early_rx_indication { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4, + dot11ax_received_ext_ru_size : 4, + reserved_0a : 19; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 19, + dot11ax_received_ext_ru_size : 4, + rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x000000000000000f + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x0000000000000010 + +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 8 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x00000000000001e0 + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 9 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 12 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0000000000001e00 + +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 13 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0x00000000ffffe000 + +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB 32 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB 63 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_cbf_info.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_cbf_info.h new file mode 100644 index 0000000000000000000000000000000000000000..c84dac34f70b0be66edbc98c32a155d6db69cc89 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_cbf_info.h @@ -0,0 +1,464 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_CBF_INFO_H_ +#define _TX_CBF_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_CBF_INFO 16 + +#define NUM_OF_QWORDS_TX_CBF_INFO 8 + +struct tx_cbf_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sw_peer_id : 16, + pre_cbf_duration : 16; + uint32_t brpoll_info_valid : 1, + trigger_brpoll_info_valid : 1, + npda_info_11ac_valid : 1, + npda_info_11ax_valid : 1, + dot11ax_su_extended : 1, + bandwidth : 3, + brpoll_info : 8, + cbf_response_table_base_index : 8, + peer_index : 3, + pkt_type : 4, + txop_duration_all_ones : 1; + uint32_t trigger_brpoll_common_info_15_0 : 16, + trigger_brpoll_common_info_31_16 : 16; + uint32_t trigger_brpoll_user_info_15_0 : 16, + trigger_brpoll_user_info_31_16 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t addr3_47_32 : 16, + sta_partial_aid : 11, + reserved_8a : 4, + cbf_resp_pwr_mgmt : 1; + uint32_t group_id : 6, + rssi_comb : 8, + reserved_9a : 2, + vht_ndpa_sta_info : 16; + uint32_t he_eht_sta_info_15_0 : 16, + he_eht_sta_info_31_16 : 16; + uint32_t dot11ax_received_format_indication : 1, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_bss_color_id : 6, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_cp_size : 2, + dot11ax_received_ltf_size : 2, + dot11ax_received_coding : 1, + dot11ax_received_dcm : 1, + dot11ax_received_doppler_indication : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_dl_ul_flag : 1, + reserved_11a : 8; + uint32_t sw_response_frame_length : 16, + sw_response_tlv_from_crypto : 1, + wait_sifs_config_valid : 1, + wait_sifs : 2, + __reserved_g_0005 : 1, + secure : 1, + tb___reserved_g_0005_response_required : 2, + reserved_12a : 2, + u_sig_puncture_pattern_encoding : 6; + uint32_t dot11be_puncture_bitmap : 16, + dot11be_response : 1, + punctured_response : 1, + npda_info_11be_valid : 1, + eht_duplicate_mode : 2, + reserved_13a : 11; + uint32_t eht_sta_info_39_32 : 8, + reserved_14a : 24; + uint32_t tlv64_padding : 32; +#else + uint32_t pre_cbf_duration : 16, + sw_peer_id : 16; + uint32_t txop_duration_all_ones : 1, + pkt_type : 4, + peer_index : 3, + cbf_response_table_base_index : 8, + brpoll_info : 8, + bandwidth : 3, + dot11ax_su_extended : 1, + npda_info_11ax_valid : 1, + npda_info_11ac_valid : 1, + trigger_brpoll_info_valid : 1, + brpoll_info_valid : 1; + uint32_t trigger_brpoll_common_info_31_16 : 16, + trigger_brpoll_common_info_15_0 : 16; + uint32_t trigger_brpoll_user_info_31_16 : 16, + trigger_brpoll_user_info_15_0 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t cbf_resp_pwr_mgmt : 1, + reserved_8a : 4, + sta_partial_aid : 11, + addr3_47_32 : 16; + uint32_t vht_ndpa_sta_info : 16, + reserved_9a : 2, + rssi_comb : 8, + group_id : 6; + uint32_t he_eht_sta_info_31_16 : 16, + he_eht_sta_info_15_0 : 16; + uint32_t reserved_11a : 8, + dot11ax_dl_ul_flag : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_received_doppler_indication : 1, + dot11ax_received_dcm : 1, + dot11ax_received_coding : 1, + dot11ax_received_ltf_size : 2, + dot11ax_received_cp_size : 2, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_bss_color_id : 6, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_format_indication : 1; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_12a : 2, + tb___reserved_g_0005_response_required : 2, + secure : 1, + __reserved_g_0005 : 1, + wait_sifs : 2, + wait_sifs_config_valid : 1, + sw_response_tlv_from_crypto : 1, + sw_response_frame_length : 16; + uint32_t reserved_13a : 11, + eht_duplicate_mode : 2, + npda_info_11be_valid : 1, + punctured_response : 1, + dot11be_response : 1, + dot11be_puncture_bitmap : 16; + uint32_t reserved_14a : 24, + eht_sta_info_39_32 : 8; + uint32_t tlv64_padding : 32; +#endif +}; + +#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_SW_PEER_ID_LSB 0 +#define TX_CBF_INFO_SW_PEER_ID_MSB 15 +#define TX_CBF_INFO_SW_PEER_ID_MASK 0x000000000000ffff + +#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 +#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 +#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0x00000000ffff0000 + +#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 32 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 32 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x0000000100000000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 33 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 33 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x0000000200000000 + +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 34 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 34 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x0000000400000000 + +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 35 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 35 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x0000000800000000 + +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 36 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 36 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000001000000000 + +#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BANDWIDTH_LSB 37 +#define TX_CBF_INFO_BANDWIDTH_MSB 39 +#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e000000000 + +#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BRPOLL_INFO_LSB 40 +#define TX_CBF_INFO_BRPOLL_INFO_MSB 47 +#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff0000000000 + +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 48 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 55 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff000000000000 + +#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PEER_INDEX_LSB 56 +#define TX_CBF_INFO_PEER_INDEX_MSB 58 +#define TX_CBF_INFO_PEER_INDEX_MASK 0x0700000000000000 + +#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PKT_TYPE_LSB 59 +#define TX_CBF_INFO_PKT_TYPE_MSB 62 +#define TX_CBF_INFO_PKT_TYPE_MASK 0x7800000000000000 + +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 63 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 63 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x000000000000ffff + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0x00000000ffff0000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 32 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 47 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff00000000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 48 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 63 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff000000000000 + +#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR1_31_0_LSB 0 +#define TX_CBF_INFO_ADDR1_31_0_MSB 31 +#define TX_CBF_INFO_ADDR1_31_0_MASK 0x00000000ffffffff + +#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR1_47_32_LSB 32 +#define TX_CBF_INFO_ADDR1_47_32_MSB 47 +#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 + +#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR2_15_0_LSB 48 +#define TX_CBF_INFO_ADDR2_15_0_MSB 63 +#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff000000000000 + +#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x0000000000000018 +#define TX_CBF_INFO_ADDR2_47_16_LSB 0 +#define TX_CBF_INFO_ADDR2_47_16_MSB 31 +#define TX_CBF_INFO_ADDR2_47_16_MASK 0x00000000ffffffff + +#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000000000000018 +#define TX_CBF_INFO_ADDR3_31_0_LSB 32 +#define TX_CBF_INFO_ADDR3_31_0_MSB 63 +#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff00000000 + +#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_ADDR3_47_32_LSB 0 +#define TX_CBF_INFO_ADDR3_47_32_MSB 15 +#define TX_CBF_INFO_ADDR3_47_32_MASK 0x000000000000ffff + +#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 +#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 +#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x0000000007ff0000 + +#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RESERVED_8A_LSB 27 +#define TX_CBF_INFO_RESERVED_8A_MSB 30 +#define TX_CBF_INFO_RESERVED_8A_MASK 0x0000000078000000 + +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x0000000080000000 + +#define TX_CBF_INFO_GROUP_ID_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_GROUP_ID_LSB 32 +#define TX_CBF_INFO_GROUP_ID_MSB 37 +#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f00000000 + +#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RSSI_COMB_LSB 38 +#define TX_CBF_INFO_RSSI_COMB_MSB 45 +#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc000000000 + +#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RESERVED_9A_LSB 46 +#define TX_CBF_INFO_RESERVED_9A_MSB 47 +#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c00000000000 + +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 48 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 63 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff000000000000 + +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x000000000000ffff + +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0x00000000ffff0000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 48 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 48 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 49 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 49 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 + +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 55 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 55 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0080000000000000 + +#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_RESERVED_11A_LSB 56 +#define TX_CBF_INFO_RESERVED_11A_MSB 63 +#define TX_CBF_INFO_RESERVED_11A_MASK 0xff00000000000000 + +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x000000000000ffff + +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000000010000 + +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000000020000 + +#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_WAIT_SIFS_LSB 18 +#define TX_CBF_INFO_WAIT_SIFS_MSB 19 +#define TX_CBF_INFO_WAIT_SIFS_MASK 0x00000000000c0000 + +#define TX_CBF_INFO_SECURE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SECURE_LSB 21 +#define TX_CBF_INFO_SECURE_MSB 21 +#define TX_CBF_INFO_SECURE_MASK 0x0000000000200000 + +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 22 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 23 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000c00000 + +#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_RESERVED_12A_LSB 24 +#define TX_CBF_INFO_RESERVED_12A_MSB 25 +#define TX_CBF_INFO_RESERVED_12A_MASK 0x0000000003000000 + +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 + +#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 48 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 48 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 + +#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 49 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 49 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 + +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 50 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 50 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x0004000000000000 + +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 51 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 52 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x0018000000000000 + +#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_RESERVED_13A_LSB 53 +#define TX_CBF_INFO_RESERVED_13A_MSB 63 +#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe0000000000000 + +#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x00000000000000ff + +#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_RESERVED_14A_LSB 8 +#define TX_CBF_INFO_RESERVED_14A_MSB 31 +#define TX_CBF_INFO_RESERVED_14A_MASK 0x00000000ffffff00 + +#define TX_CBF_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_TLV64_PADDING_LSB 32 +#define TX_CBF_INFO_TLV64_PADDING_MSB 63 +#define TX_CBF_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_setup.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_setup.h new file mode 100644 index 0000000000000000000000000000000000000000..3c6ac61fba18a13d003c7e60da656a85f5465dec --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_setup.h @@ -0,0 +1,487 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_SETUP_H_ +#define _TX_FES_SETUP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_SETUP 10 + +#define NUM_OF_QWORDS_TX_FES_SETUP 5 + +struct tx_fes_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; + uint32_t fes_in_11ax_trigger_response_config : 1, + bo_based_tid_aggregation_limit : 4, + __reserved_g_0005 : 1, + expect_i2r_lmr : 1, + transmit_start_reason : 3, + use_alt_power_sr : 1, + static_2_pwr_mode_status : 1, + obss_srg_opport_transmit_status : 1, + srp_based_transmit_status : 1, + obss_pd_based_transmit_status : 1, + puncture_from_all_allowed_modes : 1, + schedule_cmd_ring_id : 5, + fes_control_mode : 2, + number_of_users : 6, + mu_type : 1, + ofdma_triggered_response : 1, + response_to_response_cmd : 1; + uint32_t schedule_try : 4, + ndp_frame : 2, + txbf : 1, + allow_txop_exceed_in_1st_pkt : 1, + ignore_bw_available : 1, + ignore_tbtt : 1, + static_bandwidth : 3, + set_txop_duration_all_ones : 1, + transmission_contains_mu_rts : 1, + bw_restricted_frames_embedded : 1, + ast_index : 16; + uint32_t cv_id : 8, + trigger_resp_txpdu_ppdu_boundary : 2, + rxpcu_setup_complete_present : 1, + rbo_must_have_data_user_limit : 4, + mu_ndp : 1, + bf_type : 2, + cbf_nc_index_mask : 1, + cbf_nc_index : 3, + cbf_nr_index_mask : 1, + cbf_nr_index : 3, + secure___reserved_g_0005_ista : 1, + ndpa : 1, + wait_sifs : 2, + cbf_feedback_type_mask : 1, + cbf_feedback_type : 1; + uint32_t cbf_sounding_token : 6, + cbf_sounding_token_mask : 1, + cbf_bw_mask : 1, + cbf_bw : 3, + use_static_bw : 1, + coex_nack_count : 5, + sch_tx_burst_ongoing : 1, + gen_tqm_update_mpdu_count_tlv : 1, + transmit_vif : 4, + optimal_bw_retry_count : 4, + fes_continuation_ratio_threshold : 5; + uint32_t transmit_cca_bitmap : 32; + uint32_t tb___reserved_g_0005 : 1, + __reserved_g_0005_trigger_subtype : 4, + min_cts2self_count : 4, + max_cts2self_count : 4, + wifi_radar_enable : 1, + reserved_6a : 18; + uint32_t monitor_override_sta_31_0 : 32; + uint32_t monitor_override_sta_36_32 : 5, + reserved_8a : 27; + uint32_t fw2sw_info : 32; +#else + uint32_t schedule_id : 32; + uint32_t response_to_response_cmd : 1, + ofdma_triggered_response : 1, + mu_type : 1, + number_of_users : 6, + fes_control_mode : 2, + schedule_cmd_ring_id : 5, + puncture_from_all_allowed_modes : 1, + obss_pd_based_transmit_status : 1, + srp_based_transmit_status : 1, + obss_srg_opport_transmit_status : 1, + static_2_pwr_mode_status : 1, + use_alt_power_sr : 1, + transmit_start_reason : 3, + expect_i2r_lmr : 1, + __reserved_g_0005 : 1, + bo_based_tid_aggregation_limit : 4, + fes_in_11ax_trigger_response_config : 1; + uint32_t ast_index : 16, + bw_restricted_frames_embedded : 1, + transmission_contains_mu_rts : 1, + set_txop_duration_all_ones : 1, + static_bandwidth : 3, + ignore_tbtt : 1, + ignore_bw_available : 1, + allow_txop_exceed_in_1st_pkt : 1, + txbf : 1, + ndp_frame : 2, + schedule_try : 4; + uint32_t cbf_feedback_type : 1, + cbf_feedback_type_mask : 1, + wait_sifs : 2, + ndpa : 1, + secure___reserved_g_0005_ista : 1, + cbf_nr_index : 3, + cbf_nr_index_mask : 1, + cbf_nc_index : 3, + cbf_nc_index_mask : 1, + bf_type : 2, + mu_ndp : 1, + rbo_must_have_data_user_limit : 4, + rxpcu_setup_complete_present : 1, + trigger_resp_txpdu_ppdu_boundary : 2, + cv_id : 8; + uint32_t fes_continuation_ratio_threshold : 5, + optimal_bw_retry_count : 4, + transmit_vif : 4, + gen_tqm_update_mpdu_count_tlv : 1, + sch_tx_burst_ongoing : 1, + coex_nack_count : 5, + use_static_bw : 1, + cbf_bw : 3, + cbf_bw_mask : 1, + cbf_sounding_token_mask : 1, + cbf_sounding_token : 6; + uint32_t transmit_cca_bitmap : 32; + uint32_t reserved_6a : 18, + wifi_radar_enable : 1, + max_cts2self_count : 4, + min_cts2self_count : 4, + __reserved_g_0005_trigger_subtype : 4, + tb___reserved_g_0005 : 1; + uint32_t monitor_override_sta_31_0 : 32; + uint32_t reserved_8a : 27, + monitor_override_sta_36_32 : 5; + uint32_t fw2sw_info : 32; +#endif +}; + +#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 +#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 +#define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff + +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 + +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 + +#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 + +#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 + +#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 + +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 + +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 + +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 + +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 + +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 + +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 + +#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 +#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 +#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 + +#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 +#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 +#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 + +#define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_MU_TYPE_LSB 61 +#define TX_FES_SETUP_MU_TYPE_MSB 61 +#define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 + +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 + +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 + +#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 +#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 +#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f + +#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_NDP_FRAME_LSB 4 +#define TX_FES_SETUP_NDP_FRAME_MSB 5 +#define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000000030 + +#define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TXBF_LSB 6 +#define TX_FES_SETUP_TXBF_MSB 6 +#define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 + +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 + +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 + +#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 + +#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 + +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 + +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 + +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 + +#define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_AST_INDEX_LSB 16 +#define TX_FES_SETUP_AST_INDEX_MSB 31 +#define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 + +#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CV_ID_LSB 32 +#define TX_FES_SETUP_CV_ID_MSB 39 +#define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 + +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 + +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 + +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 + +#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_MU_NDP_LSB 47 +#define TX_FES_SETUP_MU_NDP_MSB 47 +#define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 + +#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_BF_TYPE_LSB 48 +#define TX_FES_SETUP_BF_TYPE_MSB 49 +#define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 + +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 + +#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 +#define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 + +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 + +#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 +#define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 + +#define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 58 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 58 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x0400000000000000 + +#define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_NDPA_LSB 59 +#define TX_FES_SETUP_NDPA_MSB 59 +#define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 + +#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_WAIT_SIFS_LSB 60 +#define TX_FES_SETUP_WAIT_SIFS_MSB 61 +#define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 + +#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 + +#define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_BW_LSB 8 +#define TX_FES_SETUP_CBF_BW_MSB 10 +#define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 + +#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 + +#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 +#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 +#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 + +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 + +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 + +#define TX_FES_SETUP_TRANSMIT_VIF_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_TRANSMIT_VIF_LSB 19 +#define TX_FES_SETUP_TRANSMIT_VIF_MSB 22 +#define TX_FES_SETUP_TRANSMIT_VIF_MASK 0x0000000000780000 + +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 + +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 + +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 + +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000001e + +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 + +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 + +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 + +#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_RESERVED_6A_LSB 14 +#define TX_FES_SETUP_RESERVED_6A_MSB 31 +#define TX_FES_SETUP_RESERVED_6A_MASK 0x00000000ffffc000 + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f + +#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_RESERVED_8A_LSB 5 +#define TX_FES_SETUP_RESERVED_8A_MSB 31 +#define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000ffffffe0 + +#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_FW2SW_INFO_LSB 32 +#define TX_FES_SETUP_FW2SW_INFO_MSB 63 +#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_1k_ba.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_1k_ba.h new file mode 100644 index 0000000000000000000000000000000000000000..97238a99431ff4c7d1a287bc9324f47bb534e5be --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_1k_ba.h @@ -0,0 +1,329 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_1K_BA_H_ +#define _TX_FES_STATUS_1K_BA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 + +#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 + +struct tx_fes_status_1k_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, + ba_type : 1, + ba_tid : 4, + unexpected_ack_or_ba : 1, + response_timeout : 1, + ack_frame_rssi : 8, + ssn : 12, + reserved_0b : 4; + uint32_t sw_peer_id : 16, + reserved_1a : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; + uint32_t ba_bitmap_287_256 : 32; + uint32_t ba_bitmap_319_288 : 32; + uint32_t ba_bitmap_351_320 : 32; + uint32_t ba_bitmap_383_352 : 32; + uint32_t ba_bitmap_415_384 : 32; + uint32_t ba_bitmap_447_416 : 32; + uint32_t ba_bitmap_479_448 : 32; + uint32_t ba_bitmap_511_480 : 32; + uint32_t ba_bitmap_543_512 : 32; + uint32_t ba_bitmap_575_544 : 32; + uint32_t ba_bitmap_607_576 : 32; + uint32_t ba_bitmap_639_608 : 32; + uint32_t ba_bitmap_671_640 : 32; + uint32_t ba_bitmap_703_672 : 32; + uint32_t ba_bitmap_735_704 : 32; + uint32_t ba_bitmap_767_736 : 32; + uint32_t ba_bitmap_799_768 : 32; + uint32_t ba_bitmap_831_800 : 32; + uint32_t ba_bitmap_863_832 : 32; + uint32_t ba_bitmap_895_864 : 32; + uint32_t ba_bitmap_927_896 : 32; + uint32_t ba_bitmap_959_928 : 32; + uint32_t ba_bitmap_991_960 : 32; + uint32_t ba_bitmap_1023_992 : 32; +#else + uint32_t reserved_0b : 4, + ssn : 12, + ack_frame_rssi : 8, + response_timeout : 1, + unexpected_ack_or_ba : 1, + ba_tid : 4, + ba_type : 1, + ack_ba_status_type : 1; + uint32_t reserved_1a : 16, + sw_peer_id : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; + uint32_t ba_bitmap_287_256 : 32; + uint32_t ba_bitmap_319_288 : 32; + uint32_t ba_bitmap_351_320 : 32; + uint32_t ba_bitmap_383_352 : 32; + uint32_t ba_bitmap_415_384 : 32; + uint32_t ba_bitmap_447_416 : 32; + uint32_t ba_bitmap_479_448 : 32; + uint32_t ba_bitmap_511_480 : 32; + uint32_t ba_bitmap_543_512 : 32; + uint32_t ba_bitmap_575_544 : 32; + uint32_t ba_bitmap_607_576 : 32; + uint32_t ba_bitmap_639_608 : 32; + uint32_t ba_bitmap_671_640 : 32; + uint32_t ba_bitmap_703_672 : 32; + uint32_t ba_bitmap_735_704 : 32; + uint32_t ba_bitmap_767_736 : 32; + uint32_t ba_bitmap_799_768 : 32; + uint32_t ba_bitmap_831_800 : 32; + uint32_t ba_bitmap_863_832 : 32; + uint32_t ba_bitmap_895_864 : 32; + uint32_t ba_bitmap_927_896 : 32; + uint32_t ba_bitmap_959_928 : 32; + uint32_t ba_bitmap_991_960 : 32; + uint32_t ba_bitmap_1023_992 : 32; +#endif +}; + +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 + +#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 + +#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c + +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 + +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 + +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 + +#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_SSN_LSB 16 +#define TX_FES_STATUS_1K_BA_SSN_MSB 27 +#define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 + +#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_ack_or_ba.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_ack_or_ba.h new file mode 100644 index 0000000000000000000000000000000000000000..6ddc78925274ae47973375ebd89164b66d7d28b4 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_ack_or_ba.h @@ -0,0 +1,161 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ +#define _TX_FES_STATUS_ACK_OR_BA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 + +#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5 + +struct tx_fes_status_ack_or_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, + ba_type : 1, + ba_tid : 4, + unexpected_ack_or_ba : 1, + response_timeout : 1, + ack_frame_rssi : 8, + ssn : 12, + reserved_0b : 4; + uint32_t sw_peer_id : 16, + reserved_1a : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; +#else + uint32_t reserved_0b : 4, + ssn : 12, + ack_frame_rssi : 8, + response_timeout : 1, + unexpected_ack_or_ba : 1, + ba_tid : 4, + ba_type : 1, + ack_ba_status_type : 1; + uint32_t reserved_1a : 16, + sw_peer_id : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; +#endif +}; + +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 + +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x0000000000000002 + +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x000000000000003c + +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 + +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 + +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 + +#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x000000000fff0000 + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 47 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 48 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff000000000000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_end.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_end.h new file mode 100644 index 0000000000000000000000000000000000000000..5061be22988ea0034994761135bbc33f2fe18bad --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_end.h @@ -0,0 +1,739 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_END_H_ +#define _TX_FES_STATUS_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_END 22 + +#define NUM_OF_QWORDS_TX_FES_STATUS_END 11 + +struct tx_fes_status_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_coex_bt_tx_while_wlan_tx : 1, + prot_coex_bt_tx_while_wlan_rx : 1, + prot_coex_wan_tx_while_wlan_tx : 1, + prot_coex_wan_tx_while_wlan_rx : 1, + prot_coex_wlan_tx_while_wlan_tx : 1, + prot_coex_wlan_tx_while_wlan_rx : 1, + coex_bt_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_rx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_rx : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wlan_tx_while_wlan_rx : 1, + global_data_underflow_warning : 1, + global_fes_transmit_result : 4, + cbf_bw_received_valid : 1, + cbf_bw_received : 3, + actual_received_ack_type : 4, + sta_response_count : 6, + dpdtrain_done : 1; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 4, + brp_info_valid : 1, + reserved_1a : 6, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + fes_in_11ax_trigger_response_config : 1, + null_delim_inserted_before_mpdus : 1, + only_null_delim_sent : 1; + uint32_t start_of_frame_timestamp_15_0 : 16, + start_of_frame_timestamp_31_16 : 16; + uint32_t end_of_frame_timestamp_15_0 : 16, + end_of_frame_timestamp_31_16 : 16; + uint32_t terminate___reserved_g_0005_sequence : 1, + reserved_4a : 7, + timing_status : 2, + response_type : 5, + r2r_end_status_to_follow : 1, + transmit_delay : 16; + uint32_t tx_group_delay : 12, + reserved_5a : 4, + tpc_dbg_info_cmn_15_0 : 16; + uint32_t tpc_dbg_info_cmn_31_16 : 16, + tpc_dbg_info_47_32 : 16; + uint32_t tpc_dbg_info_chn1_15_0 : 16, + tpc_dbg_info_chn1_31_16 : 16; + uint32_t tpc_dbg_info_chn1_47_32 : 16, + tpc_dbg_info_chn1_63_48 : 16; + uint32_t tpc_dbg_info_chn1_79_64 : 16, + tpc_dbg_info_chn2_15_0 : 16; + uint32_t tpc_dbg_info_chn2_31_16 : 16, + tpc_dbg_info_chn2_47_32 : 16; + uint32_t tpc_dbg_info_chn2_63_48 : 16, + tpc_dbg_info_chn2_79_64 : 16; + uint32_t phytx_tx_end_sw_info_15_0 : 16, + phytx_tx_end_sw_info_31_16 : 16; + uint32_t phytx_tx_end_sw_info_47_32 : 16, + phytx_tx_end_sw_info_63_48 : 16; + uint32_t beamform_masked_user_bitmap_15_0 : 16, + beamform_masked_user_bitmap_31_16 : 16; + uint32_t cbf_segment_request_mask : 8, + cbf_segment_sent_mask : 8, + highest_achieved_data_null_ratio : 5, + use_alt_power_sr : 1, + static_2_pwr_mode_status : 1, + obss_srg_opport_transmit_status : 1, + srp_based_transmit_status : 1, + obss_pd_based_transmit_status : 1, + beamform_masked_user_bitmap_36_32 : 5, + pdg_mpdu_ready : 1; + uint32_t pdg_mpdu_count : 16, + pdg_est_mpdu_tx_count : 16; + uint32_t pdg_overview_length : 24, + txop_duration : 7, + pdg_dropped_mpdu_warning : 1; + uint32_t packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + packet_extension : 3, + fec_type : 1, + stbc : 1, + num_data_symbols : 16, + ru_size : 4, + reserved_17a : 4; + uint32_t num_ltf_symbols : 3, + ltf_size : 2, + cp_setting : 2, + reserved_18a : 5, + dcm : 1, + ldpc_extra_symbol : 1, + force_extra_symbol : 1, + reserved_18b : 1, + tx_pwr_shared : 8, + tx_pwr_unshared : 8; + uint32_t __reserved_g_0005_active_user_map : 16, + __reserved_g_0005_sent_dummy_tx : 1, + __reserved_g_0005_ftm_frame_sent : 1, + reserved_20a : 6, + cv_corr_status : 8; + uint32_t current_tx_duration : 16, + reserved_21a : 16; +#else + uint32_t dpdtrain_done : 1, + sta_response_count : 6, + actual_received_ack_type : 4, + cbf_bw_received : 3, + cbf_bw_received_valid : 1, + global_fes_transmit_result : 4, + global_data_underflow_warning : 1, + coex_wlan_tx_while_wlan_rx : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_rx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_rx : 1, + coex_bt_tx_while_wlan_tx : 1, + prot_coex_wlan_tx_while_wlan_rx : 1, + prot_coex_wlan_tx_while_wlan_tx : 1, + prot_coex_wan_tx_while_wlan_rx : 1, + prot_coex_wan_tx_while_wlan_tx : 1, + prot_coex_bt_tx_while_wlan_rx : 1, + prot_coex_bt_tx_while_wlan_tx : 1; + uint32_t only_null_delim_sent : 1, + null_delim_inserted_before_mpdus : 1, + fes_in_11ax_trigger_response_config : 1, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + reserved_1a : 6, + brp_info_valid : 1, + reserved_after_struct16 : 4; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t start_of_frame_timestamp_31_16 : 16, + start_of_frame_timestamp_15_0 : 16; + uint32_t end_of_frame_timestamp_31_16 : 16, + end_of_frame_timestamp_15_0 : 16; + uint32_t transmit_delay : 16, + r2r_end_status_to_follow : 1, + response_type : 5, + timing_status : 2, + reserved_4a : 7, + terminate___reserved_g_0005_sequence : 1; + uint32_t tpc_dbg_info_cmn_15_0 : 16, + reserved_5a : 4, + tx_group_delay : 12; + uint32_t tpc_dbg_info_47_32 : 16, + tpc_dbg_info_cmn_31_16 : 16; + uint32_t tpc_dbg_info_chn1_31_16 : 16, + tpc_dbg_info_chn1_15_0 : 16; + uint32_t tpc_dbg_info_chn1_63_48 : 16, + tpc_dbg_info_chn1_47_32 : 16; + uint32_t tpc_dbg_info_chn2_15_0 : 16, + tpc_dbg_info_chn1_79_64 : 16; + uint32_t tpc_dbg_info_chn2_47_32 : 16, + tpc_dbg_info_chn2_31_16 : 16; + uint32_t tpc_dbg_info_chn2_79_64 : 16, + tpc_dbg_info_chn2_63_48 : 16; + uint32_t phytx_tx_end_sw_info_31_16 : 16, + phytx_tx_end_sw_info_15_0 : 16; + uint32_t phytx_tx_end_sw_info_63_48 : 16, + phytx_tx_end_sw_info_47_32 : 16; + uint32_t beamform_masked_user_bitmap_31_16 : 16, + beamform_masked_user_bitmap_15_0 : 16; + uint32_t pdg_mpdu_ready : 1, + beamform_masked_user_bitmap_36_32 : 5, + obss_pd_based_transmit_status : 1, + srp_based_transmit_status : 1, + obss_srg_opport_transmit_status : 1, + static_2_pwr_mode_status : 1, + use_alt_power_sr : 1, + highest_achieved_data_null_ratio : 5, + cbf_segment_sent_mask : 8, + cbf_segment_request_mask : 8; + uint32_t pdg_est_mpdu_tx_count : 16, + pdg_mpdu_count : 16; + uint32_t pdg_dropped_mpdu_warning : 1, + txop_duration : 7, + pdg_overview_length : 24; + uint32_t reserved_17a : 4, + ru_size : 4, + num_data_symbols : 16, + stbc : 1, + fec_type : 1, + packet_extension : 3, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2; + uint32_t tx_pwr_unshared : 8, + tx_pwr_shared : 8, + reserved_18b : 1, + force_extra_symbol : 1, + ldpc_extra_symbol : 1, + dcm : 1, + reserved_18a : 5, + cp_setting : 2, + ltf_size : 2, + num_ltf_symbols : 3; + uint32_t cv_corr_status : 8, + reserved_20a : 6, + __reserved_g_0005_ftm_frame_sent : 1, + __reserved_g_0005_sent_dummy_tx : 1, + __reserved_g_0005_active_user_map : 16; + uint32_t reserved_21a : 16, + current_tx_duration : 16; +#endif +}; + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000002 + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000008 + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000010 + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000020 + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000040 + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000080 + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000100 + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000200 + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000400 + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000800 + +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 + +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 + +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 + +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 + +#define TX_FES_STATUS_END_DPDTRAIN_DONE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_LSB 31 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_MSB 31 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_MASK 0x0000000080000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 + +#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 + +#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_RESERVED_1A_LSB 53 +#define TX_FES_STATUS_END_RESERVED_1A_MSB 58 +#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07e0000000000000 + +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 + +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 + +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 + +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 + +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x0000000000000001 + +#define TX_FES_STATUS_END_RESERVED_4A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESERVED_4A_LSB 1 +#define TX_FES_STATUS_END_RESERVED_4A_MSB 7 +#define TX_FES_STATUS_END_RESERVED_4A_MASK 0x00000000000000fe + +#define TX_FES_STATUS_END_TIMING_STATUS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TIMING_STATUS_LSB 8 +#define TX_FES_STATUS_END_TIMING_STATUS_MSB 9 +#define TX_FES_STATUS_END_TIMING_STATUS_MASK 0x0000000000000300 + +#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 10 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 14 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x0000000000007c00 + +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 15 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 15 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000008000 + +#define TX_FES_STATUS_END_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_LSB 16 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_MSB 31 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_TX_GROUP_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_LSB 32 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_MSB 43 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_MASK 0x00000fff00000000 + +#define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESERVED_5A_LSB 44 +#define TX_FES_STATUS_END_RESERVED_5A_MSB 47 +#define TX_FES_STATUS_END_RESERVED_5A_MASK 0x0000f00000000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 32 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 39 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 40 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 47 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff0000000000 + +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 48 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 52 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f000000000000 + +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 53 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 53 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0020000000000000 + +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 54 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 54 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0040000000000000 + +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 55 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 55 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0080000000000000 + +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 56 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 56 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0100000000000000 + +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 57 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 57 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0200000000000000 + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 58 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 62 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c00000000000000 + +#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 63 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 63 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x8000000000000000 + +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 32 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 55 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff00000000 + +#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_TXOP_DURATION_LSB 56 +#define TX_FES_STATUS_END_TXOP_DURATION_MSB 62 +#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f00000000000000 + +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 63 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 63 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x8000000000000000 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000000000000038 + +#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_FEC_TYPE_LSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000000000000040 + +#define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_STBC_LSB 7 +#define TX_FES_STATUS_END_STBC_MSB 7 +#define TX_FES_STATUS_END_STBC_MASK 0x0000000000000080 + +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x0000000000ffff00 + +#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RU_SIZE_LSB 24 +#define TX_FES_STATUS_END_RU_SIZE_MSB 27 +#define TX_FES_STATUS_END_RU_SIZE_MASK 0x000000000f000000 + +#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_17A_LSB 28 +#define TX_FES_STATUS_END_RESERVED_17A_MSB 31 +#define TX_FES_STATUS_END_RESERVED_17A_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 32 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 34 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 + +#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_LTF_SIZE_LSB 35 +#define TX_FES_STATUS_END_LTF_SIZE_MSB 36 +#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000001800000000 + +#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_CP_SETTING_LSB 37 +#define TX_FES_STATUS_END_CP_SETTING_MSB 38 +#define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000006000000000 + +#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_18A_LSB 39 +#define TX_FES_STATUS_END_RESERVED_18A_MSB 43 +#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f8000000000 + +#define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_DCM_LSB 44 +#define TX_FES_STATUS_END_DCM_MSB 44 +#define TX_FES_STATUS_END_DCM_MASK 0x0000100000000000 + +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 45 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 45 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000200000000000 + +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 46 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 46 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000400000000000 + +#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_18B_LSB 47 +#define TX_FES_STATUS_END_RESERVED_18B_MSB 47 +#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000800000000000 + +#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 48 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 55 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff000000000000 + +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 56 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 63 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff00000000000000 + +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x0000000000010000 + +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x0000000000020000 + +#define TX_FES_STATUS_END_RESERVED_20A_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RESERVED_20A_LSB 18 +#define TX_FES_STATUS_END_RESERVED_20A_MSB 23 +#define TX_FES_STATUS_END_RESERVED_20A_MASK 0x0000000000fc0000 + +#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0x00000000ff000000 + +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 32 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 47 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RESERVED_21A_LSB 48 +#define TX_FES_STATUS_END_RESERVED_21A_MSB 63 +#define TX_FES_STATUS_END_RESERVED_21A_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_prot.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_prot.h new file mode 100644 index 0000000000000000000000000000000000000000..fed16b594806cd40c456038e6b5699183d10aae9 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_prot.h @@ -0,0 +1,340 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_PROT_H_ +#define _TX_FES_STATUS_PROT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 14 + +#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 7 + +struct tx_fes_status_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t success : 1, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + reserved_0 : 20, + pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4; + uint32_t frame_type : 2, + frame_subtype : 4, + rx_pwr_mgmt : 1, + status : 1, + duration_field : 16, + reserved_1a : 2, + agc_cbw : 3, + service_cbw : 3; + uint32_t start_of_frame_timestamp_15_0 : 16, + start_of_frame_timestamp_31_16 : 16; + uint32_t end_of_frame_timestamp_15_0 : 16, + end_of_frame_timestamp_31_16 : 16; + uint32_t tx_group_delay : 12, + timing_status : 2, + dpdtrain_done : 1, + reserved_4 : 1, + transmit_delay : 16; + uint32_t tpc_dbg_info_cmn_15_0 : 16, + tpc_dbg_info_cmn_31_16 : 16; + uint32_t tpc_dbg_info_cmn_47_32 : 16, + tpc_dbg_info_chn1_15_0 : 16; + uint32_t tpc_dbg_info_chn1_31_16 : 16, + tpc_dbg_info_chn1_47_32 : 16; + uint32_t tpc_dbg_info_chn1_63_48 : 16, + tpc_dbg_info_chn1_79_64 : 16; + uint32_t tpc_dbg_info_chn2_15_0 : 16, + tpc_dbg_info_chn2_31_16 : 16; + uint32_t tpc_dbg_info_chn2_47_32 : 16, + tpc_dbg_info_chn2_63_48 : 16; + uint32_t tpc_dbg_info_chn2_79_64 : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t phytx_tx_end_sw_info_15_0 : 16, + phytx_tx_end_sw_info_31_16 : 16; + uint32_t phytx_tx_end_sw_info_47_32 : 16, + phytx_tx_end_sw_info_63_48 : 16; +#else + uint32_t rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4, + reserved_0 : 20, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + success : 1; + uint32_t service_cbw : 3, + agc_cbw : 3, + reserved_1a : 2, + duration_field : 16, + status : 1, + rx_pwr_mgmt : 1, + frame_subtype : 4, + frame_type : 2; + uint32_t start_of_frame_timestamp_31_16 : 16, + start_of_frame_timestamp_15_0 : 16; + uint32_t end_of_frame_timestamp_31_16 : 16, + end_of_frame_timestamp_15_0 : 16; + uint32_t transmit_delay : 16, + reserved_4 : 1, + dpdtrain_done : 1, + timing_status : 2, + tx_group_delay : 12; + uint32_t tpc_dbg_info_cmn_31_16 : 16, + tpc_dbg_info_cmn_15_0 : 16; + uint32_t tpc_dbg_info_chn1_15_0 : 16, + tpc_dbg_info_cmn_47_32 : 16; + uint32_t tpc_dbg_info_chn1_47_32 : 16, + tpc_dbg_info_chn1_31_16 : 16; + uint32_t tpc_dbg_info_chn1_79_64 : 16, + tpc_dbg_info_chn1_63_48 : 16; + uint32_t tpc_dbg_info_chn2_31_16 : 16, + tpc_dbg_info_chn2_15_0 : 16; + uint32_t tpc_dbg_info_chn2_63_48 : 16, + tpc_dbg_info_chn2_47_32 : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t tpc_dbg_info_chn2_79_64 : 16; + uint32_t phytx_tx_end_sw_info_31_16 : 16, + phytx_tx_end_sw_info_15_0 : 16; + uint32_t phytx_tx_end_sw_info_63_48 : 16, + phytx_tx_end_sw_info_47_32 : 16; +#endif +}; + +#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 + +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 + +#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 +#define TX_FES_STATUS_PROT_RESERVED_0_MSB 22 +#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000007ffff8 + +#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23 +#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26 +#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000007800000 + +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000008000000 + +#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RATE_MCS_LSB 28 +#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 +#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 + +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 + +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 + +#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_STATUS_LSB 39 +#define TX_FES_STATUS_PROT_STATUS_MSB 39 +#define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 + +#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 + +#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 +#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 +#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 + +#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 +#define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 +#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 + +#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 + +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_LSB 0 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MSB 11 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MASK 0x0000000000000fff + +#define TX_FES_STATUS_PROT_TIMING_STATUS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TIMING_STATUS_LSB 12 +#define TX_FES_STATUS_PROT_TIMING_STATUS_MSB 13 +#define TX_FES_STATUS_PROT_TIMING_STATUS_MASK 0x0000000000003000 + +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_LSB 14 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MSB 14 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MASK 0x0000000000004000 + +#define TX_FES_STATUS_PROT_RESERVED_4_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_RESERVED_4_LSB 15 +#define TX_FES_STATUS_PROT_RESERVED_4_MSB 15 +#define TX_FES_STATUS_PROT_RESERVED_4_MASK 0x0000000000008000 + +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_LSB 16 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MSB 31 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MASK 0xffff000000000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 48 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 55 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00ff000000000000 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 56 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 61 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x3f00000000000000 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 62 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 63 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0xc000000000000000 + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start.h new file mode 100644 index 0000000000000000000000000000000000000000..2b87d6dbe79119d5135f9fce299d499ba423cecb --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start.h @@ -0,0 +1,133 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_START_H_ +#define _TX_FES_STATUS_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START 2 + +struct tx_fes_status_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; + uint32_t reserved_1a : 8, + transmit_start_reason : 3, + disabled_user_bitmap_36_32 : 5, + schedule_cmd_ring_id : 5, + fes_control_mode : 2, + schedule_try : 4, + medium_prot_type : 3, + reserved_1b : 2; + uint32_t optimal_bw_try_count : 4, + number_of_users : 7, + coex_nack_count : 5, + cca_ed0 : 16; + uint32_t disabled_user_bitmap_31_0 : 32; +#else + uint32_t schedule_id : 32; + uint32_t reserved_1b : 2, + medium_prot_type : 3, + schedule_try : 4, + fes_control_mode : 2, + schedule_cmd_ring_id : 5, + disabled_user_bitmap_36_32 : 5, + transmit_start_reason : 3, + reserved_1a : 8; + uint32_t cca_ed0 : 16, + coex_nack_count : 5, + number_of_users : 7, + optimal_bw_try_count : 4; + uint32_t disabled_user_bitmap_31_0 : 32; +#endif +}; + +#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 +#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 +#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_RESERVED_1A_LSB 32 +#define TX_FES_STATUS_START_RESERVED_1A_MSB 39 +#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 40 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 42 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x0000070000000000 + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 43 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 47 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f80000000000 + +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 48 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 52 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 + +#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 53 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 54 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x0060000000000000 + +#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 55 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 58 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x0780000000000000 + +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 59 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 61 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x3800000000000000 + +#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_RESERVED_1B_LSB 62 +#define TX_FES_STATUS_START_RESERVED_1B_MSB 63 +#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc000000000000000 + +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x000000000000000f + +#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x00000000000007f0 + +#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x000000000000f800 + +#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_CCA_ED0_LSB 16 +#define TX_FES_STATUS_START_CCA_ED0_MSB 31 +#define TX_FES_STATUS_START_CCA_ED0_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 32 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 63 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start_ppdu.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start_ppdu.h new file mode 100644 index 0000000000000000000000000000000000000000..d008fc7942248accc1b59e1c88f2251acbc92561 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start_ppdu.h @@ -0,0 +1,175 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_START_PPDU_H_ +#define _TX_FES_STATUS_START_PPDU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 2 + +struct tx_fes_status_start_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_timestamp_lower_32 : 32; + uint32_t ppdu_timestamp_upper_32 : 32; + uint32_t subband_mask : 16, + ndp_frame : 2, + reserved_2b : 2, + coex_based_tx_bw : 3, + coex_based_ant_mask : 8, + reserved_2c : 1; + uint32_t coex_based_tx_pwr_shared_ant : 8, + coex_based_tx_pwr_ant : 8, + concurrent_bt_tx : 1, + concurrent_wlan_tx : 1, + concurrent_wan_tx : 1, + concurrent_wan_rx : 1, + coex_pwr_reduction_bt : 1, + coex_pwr_reduction_wlan : 1, + coex_pwr_reduction_wan : 1, + coex_result_alt_based : 1, + request_packet_bw : 3, + response_type : 5; +#else + uint32_t ppdu_timestamp_lower_32 : 32; + uint32_t ppdu_timestamp_upper_32 : 32; + uint32_t reserved_2c : 1, + coex_based_ant_mask : 8, + coex_based_tx_bw : 3, + reserved_2b : 2, + ndp_frame : 2, + subband_mask : 16; + uint32_t response_type : 5, + request_packet_bw : 3, + coex_result_alt_based : 1, + coex_pwr_reduction_wan : 1, + coex_pwr_reduction_wlan : 1, + coex_pwr_reduction_bt : 1, + concurrent_wan_rx : 1, + concurrent_wan_tx : 1, + concurrent_wlan_tx : 1, + concurrent_bt_tx : 1, + coex_based_tx_pwr_ant : 8, + coex_based_tx_pwr_shared_ant : 8; +#endif +}; + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 32 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 63 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x000000000000ffff + +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 17 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x0000000000030000 + +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 18 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x00000000000c0000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x0000000000700000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 + +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x0000000080000000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 32 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 39 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 40 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 47 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff0000000000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 48 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 48 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x0001000000000000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 49 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 49 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 50 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 50 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x0004000000000000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 51 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 51 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x0008000000000000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 52 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 52 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 53 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 53 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 54 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 54 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 + +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 55 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 55 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x0080000000000000 + +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 56 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 58 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x0700000000000000 + +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 59 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 63 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf800000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start_prot.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start_prot.h new file mode 100644 index 0000000000000000000000000000000000000000..9e7bbe980258c4a31f5dbfbece403d1c88e4507a --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start_prot.h @@ -0,0 +1,168 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_START_PROT_H_ +#define _TX_FES_STATUS_START_PROT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 2 + +struct tx_fes_status_start_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_timestamp_lower_32 : 32; + uint32_t prot_timestamp_upper_32 : 32; + uint32_t subband_mask : 16, + reserved_2b : 4, + prot_coex_based_tx_bw : 3, + prot_coex_based_ant_mask : 8, + prot_coex_result_alt_based : 1; + uint32_t prot_coex_tx_pwr_shared_ant : 8, + prot_coex_tx_pwr_ant : 8, + prot_concurrent_bt_tx : 1, + prot_concurrent_wlan_tx : 1, + prot_concurrent_wan_tx : 1, + prot_concurrent_wan_rx : 1, + prot_coex_pwr_reduction_bt : 1, + prot_coex_pwr_reduction_wlan : 1, + prot_coex_pwr_reduction_wan : 1, + prot_request_packet_bw : 3, + response_type : 5, + reserved_3a : 1; +#else + uint32_t prot_timestamp_lower_32 : 32; + uint32_t prot_timestamp_upper_32 : 32; + uint32_t prot_coex_result_alt_based : 1, + prot_coex_based_ant_mask : 8, + prot_coex_based_tx_bw : 3, + reserved_2b : 4, + subband_mask : 16; + uint32_t reserved_3a : 1, + response_type : 5, + prot_request_packet_bw : 3, + prot_coex_pwr_reduction_wan : 1, + prot_coex_pwr_reduction_wlan : 1, + prot_coex_pwr_reduction_bt : 1, + prot_concurrent_wan_rx : 1, + prot_concurrent_wan_tx : 1, + prot_concurrent_wlan_tx : 1, + prot_concurrent_bt_tx : 1, + prot_coex_tx_pwr_ant : 8, + prot_coex_tx_pwr_shared_ant : 8; +#endif +}; + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 32 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 63 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x000000000000ffff + +#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x00000000000f0000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x0000000000700000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x0000000080000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 32 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 39 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 40 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 47 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff0000000000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 48 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 48 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x0001000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 49 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 49 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 50 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 50 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x0004000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 51 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 51 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x0008000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 52 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 52 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 53 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 53 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 54 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 54 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 55 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 57 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x0380000000000000 + +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 58 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 62 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c00000000000000 + +#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 63 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 63 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_user_ppdu.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_user_ppdu.h new file mode 100644 index 0000000000000000000000000000000000000000..84732390eb1d2a552cbecc559743a86ed0d445d9 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_user_ppdu.h @@ -0,0 +1,210 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_USER_PPDU_H_ +#define _TX_FES_STATUS_USER_PPDU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 + +#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 + +struct tx_fes_status_user_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t underflow_mpdu_count : 9, + data_underflow_warning : 2, + bw_drop_underflow_warning : 1, + qc_eosp_setting : 1, + fc_more_data_setting : 1, + fc_pwr_mgt_setting : 1, + mpdu_tx_count : 9, + user_blocked : 1, + pre_trig_response_delim_count : 7; + uint32_t underflow_byte_count : 16, + coex_abort_mpdu_count_valid : 1, + coex_abort_mpdu_count : 9, + transmitted_tid : 4, + txdma_dropped_mpdu_warning : 1, + reserved_1 : 1; + uint32_t duration : 16, + num_eof_delim_added : 16; + uint32_t psdu_octet : 24, + qos_buf_state : 8; + uint32_t num_null_delim_added : 22, + reserved_4a : 2, + cv_corr_user_valid_in_phy : 1, + nss : 3, + mcs : 4; + uint32_t ht_control : 32; +#else + uint32_t pre_trig_response_delim_count : 7, + user_blocked : 1, + mpdu_tx_count : 9, + fc_pwr_mgt_setting : 1, + fc_more_data_setting : 1, + qc_eosp_setting : 1, + bw_drop_underflow_warning : 1, + data_underflow_warning : 2, + underflow_mpdu_count : 9; + uint32_t reserved_1 : 1, + txdma_dropped_mpdu_warning : 1, + transmitted_tid : 4, + coex_abort_mpdu_count : 9, + coex_abort_mpdu_count_valid : 1, + underflow_byte_count : 16; + uint32_t num_eof_delim_added : 16, + duration : 16; + uint32_t qos_buf_state : 8, + psdu_octet : 24; + uint32_t mcs : 4, + nss : 3, + cv_corr_user_valid_in_phy : 1, + reserved_4a : 2, + num_null_delim_added : 22; + uint32_t ht_control : 32; +#endif +}; + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff + +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 + +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 + +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 + +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000002000 + +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000004000 + +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ff8000 + +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 + +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 + +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 + +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 + +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 63 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 63 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x8000000000000000 + +#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 +#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 +#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff + +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 + +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 + +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff + +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x0000000000c00000 + +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x0000000001000000 + +#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_NSS_LSB 25 +#define TX_FES_STATUS_USER_PPDU_NSS_MSB 27 +#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x000000000e000000 + +#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_MCS_LSB 28 +#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 +#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_user_response.h new file mode 100644 index 0000000000000000000000000000000000000000..da58b669a4506f8208602518ec384676204d281d --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_user_response.h @@ -0,0 +1,74 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ +#define _TX_FES_STATUS_USER_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 + +#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1 + +struct tx_fes_status_user_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fes_transmit_result : 4, + reserved_0 : 28; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 16; +#else + uint32_t reserved_0 : 28, + fes_transmit_result : 4; + uint32_t reserved_after_struct16 : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; +#endif +}; + +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x000000000000000f + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 31 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0x00000000fffffff0 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 48 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 63 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_flush_req.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_flush_req.h new file mode 100644 index 0000000000000000000000000000000000000000..bcb5be4a4e9676a178612d71fee40278d7838156 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_flush_req.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FLUSH_REQ_H_ +#define _TX_FLUSH_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FLUSH_REQ 2 + +#define NUM_OF_QWORDS_TX_FLUSH_REQ 1 + +struct tx_flush_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t flush_req_reason : 8, + phytx_abort_reason : 8, + flush_req_user_number_or_link_id : 6, + mlo_abort_reason : 5, + reserved_0a : 5; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 5, + mlo_abort_reason : 5, + flush_req_user_number_or_link_id : 6, + phytx_abort_reason : 8, + flush_req_reason : 8; + uint32_t tlv64_padding : 32; +#endif +}; + +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff + +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00 + +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000 + +#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000 + +#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 +#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 +#define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000 + +#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_TLV64_PADDING_LSB 32 +#define TX_FLUSH_REQ_TLV64_PADDING_MSB 63 +#define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_mpdu_start.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_mpdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..a7006918117f18d50d99b3b2627f99f85de58070 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_mpdu_start.h @@ -0,0 +1,308 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_MPDU_START_H_ +#define _TX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MPDU_START 10 + +#define NUM_OF_QWORDS_TX_MPDU_START 5 + +struct tx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_length : 14, + frame_not_from_tqm : 1, + vht_control_present : 1, + mpdu_header_length : 8, + retry_count : 7, + wds : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_47_32 : 16, + mpdu_sequence_number : 12, + raw_already_encrypted : 1, + frame_type : 2, + txdma_dropped_mpdu_warning : 1; + uint32_t iv_byte_0 : 8, + iv_byte_1 : 8, + iv_byte_2 : 8, + iv_byte_3 : 8; + uint32_t iv_byte_4 : 8, + iv_byte_5 : 8, + iv_byte_6 : 8, + iv_byte_7 : 8; + uint32_t iv_byte_8 : 8, + iv_byte_9 : 8, + iv_byte_10 : 8, + iv_byte_11 : 8; + uint32_t iv_byte_12 : 8, + iv_byte_13 : 8, + iv_byte_14 : 8, + iv_byte_15 : 8; + uint32_t iv_byte_16 : 8, + iv_byte_17 : 8, + iv_len : 5, + icv_len : 5, + vht_control_offset : 6; + uint32_t mpdu_type : 1, + transmit_bw_restriction : 1, + allowed_transmit_bw : 4, + tx_notify_frame : 3, + reserved_8a : 23; + uint32_t tlv64_padding : 32; +#else + uint32_t wds : 1, + retry_count : 7, + mpdu_header_length : 8, + vht_control_present : 1, + frame_not_from_tqm : 1, + mpdu_length : 14; + uint32_t pn_31_0 : 32; + uint32_t txdma_dropped_mpdu_warning : 1, + frame_type : 2, + raw_already_encrypted : 1, + mpdu_sequence_number : 12, + pn_47_32 : 16; + uint32_t iv_byte_3 : 8, + iv_byte_2 : 8, + iv_byte_1 : 8, + iv_byte_0 : 8; + uint32_t iv_byte_7 : 8, + iv_byte_6 : 8, + iv_byte_5 : 8, + iv_byte_4 : 8; + uint32_t iv_byte_11 : 8, + iv_byte_10 : 8, + iv_byte_9 : 8, + iv_byte_8 : 8; + uint32_t iv_byte_15 : 8, + iv_byte_14 : 8, + iv_byte_13 : 8, + iv_byte_12 : 8; + uint32_t vht_control_offset : 6, + icv_len : 5, + iv_len : 5, + iv_byte_17 : 8, + iv_byte_16 : 8; + uint32_t reserved_8a : 23, + tx_notify_frame : 3, + allowed_transmit_bw : 4, + transmit_bw_restriction : 1, + mpdu_type : 1; + uint32_t tlv64_padding : 32; +#endif +}; + +#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 +#define TX_MPDU_START_MPDU_LENGTH_LSB 0 +#define TX_MPDU_START_MPDU_LENGTH_MSB 13 +#define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff + +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 + +#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 + +#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 + +#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 +#define TX_MPDU_START_RETRY_COUNT_LSB 24 +#define TX_MPDU_START_RETRY_COUNT_MSB 30 +#define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 + +#define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 +#define TX_MPDU_START_WDS_LSB 31 +#define TX_MPDU_START_WDS_MSB 31 +#define TX_MPDU_START_WDS_MASK 0x0000000080000000 + +#define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 +#define TX_MPDU_START_PN_31_0_LSB 32 +#define TX_MPDU_START_PN_31_0_MSB 63 +#define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 + +#define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 +#define TX_MPDU_START_PN_47_32_LSB 0 +#define TX_MPDU_START_PN_47_32_MSB 15 +#define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff + +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 + +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 + +#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 +#define TX_MPDU_START_FRAME_TYPE_LSB 29 +#define TX_MPDU_START_FRAME_TYPE_MSB 30 +#define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 + +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 + +#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_0_LSB 32 +#define TX_MPDU_START_IV_BYTE_0_MSB 39 +#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 + +#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_1_LSB 40 +#define TX_MPDU_START_IV_BYTE_1_MSB 47 +#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 + +#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_2_LSB 48 +#define TX_MPDU_START_IV_BYTE_2_MSB 55 +#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 + +#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_3_LSB 56 +#define TX_MPDU_START_IV_BYTE_3_MSB 63 +#define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 + +#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_4_LSB 0 +#define TX_MPDU_START_IV_BYTE_4_MSB 7 +#define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff + +#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_5_LSB 8 +#define TX_MPDU_START_IV_BYTE_5_MSB 15 +#define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 + +#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_6_LSB 16 +#define TX_MPDU_START_IV_BYTE_6_MSB 23 +#define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 + +#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_7_LSB 24 +#define TX_MPDU_START_IV_BYTE_7_MSB 31 +#define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 + +#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_8_LSB 32 +#define TX_MPDU_START_IV_BYTE_8_MSB 39 +#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 + +#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_9_LSB 40 +#define TX_MPDU_START_IV_BYTE_9_MSB 47 +#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 + +#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_10_LSB 48 +#define TX_MPDU_START_IV_BYTE_10_MSB 55 +#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 + +#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_11_LSB 56 +#define TX_MPDU_START_IV_BYTE_11_MSB 63 +#define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 + +#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_12_LSB 0 +#define TX_MPDU_START_IV_BYTE_12_MSB 7 +#define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff + +#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_13_LSB 8 +#define TX_MPDU_START_IV_BYTE_13_MSB 15 +#define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 + +#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_14_LSB 16 +#define TX_MPDU_START_IV_BYTE_14_MSB 23 +#define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 + +#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_15_LSB 24 +#define TX_MPDU_START_IV_BYTE_15_MSB 31 +#define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 + +#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_16_LSB 32 +#define TX_MPDU_START_IV_BYTE_16_MSB 39 +#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 + +#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_17_LSB 40 +#define TX_MPDU_START_IV_BYTE_17_MSB 47 +#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 + +#define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_LEN_LSB 48 +#define TX_MPDU_START_IV_LEN_MSB 52 +#define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 + +#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 +#define TX_MPDU_START_ICV_LEN_LSB 53 +#define TX_MPDU_START_ICV_LEN_MSB 57 +#define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 + +#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 + +#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 +#define TX_MPDU_START_MPDU_TYPE_LSB 0 +#define TX_MPDU_START_MPDU_TYPE_MSB 0 +#define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 + +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 + +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c + +#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 + +#define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_MPDU_START_RESERVED_8A_LSB 9 +#define TX_MPDU_START_RESERVED_8A_MSB 31 +#define TX_MPDU_START_RESERVED_8A_MASK 0x00000000fffffe00 + +#define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TLV64_PADDING_LSB 32 +#define TX_MPDU_START_TLV64_PADDING_MSB 63 +#define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_msdu_start.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_msdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..04d105db7488f81ec8589bbe0f7506b74b2955f0 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_msdu_start.h @@ -0,0 +1,266 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_MSDU_START_H_ +#define _TX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MSDU_START 8 + +#define NUM_OF_QWORDS_TX_MSDU_START 4 + +struct tx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_len : 14, + first_msdu : 1, + last_msdu : 1, + encap_type : 2, + epd_en : 1, + da_sa_present : 2, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + dummy_msdu_delimitation : 1, + reserved_0a : 5; + uint32_t tso_enable : 1, + reserved_1a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + mesh_enable : 1, + reserved_1b : 6; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + checksum_offset : 13, + partial_checksum_en : 1, + reserved_4 : 2; + uint32_t payload_start_offset : 14, + reserved_5a : 2, + payload_end_offset : 14, + reserved_5b : 2; + uint32_t udp_length : 16, + reserved_6 : 16; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 5, + dummy_msdu_delimitation : 1, + tcp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + ipv4_checksum_en : 1, + da_sa_present : 2, + epd_en : 1, + encap_type : 2, + last_msdu : 1, + first_msdu : 1, + msdu_len : 14; + uint32_t reserved_1b : 6, + mesh_enable : 1, + tcp_flag_mask : 9, + tcp_flag : 9, + reserved_1a : 6, + tso_enable : 1; + uint32_t ip_length : 16, + l2_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t reserved_4 : 2, + partial_checksum_en : 1, + checksum_offset : 13, + ip_identification : 16; + uint32_t reserved_5b : 2, + payload_end_offset : 14, + reserved_5a : 2, + payload_start_offset : 14; + uint32_t reserved_6 : 16, + udp_length : 16; + uint32_t tlv64_padding : 32; +#endif +}; + +#define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_MSDU_LEN_LSB 0 +#define TX_MSDU_START_MSDU_LEN_MSB 13 +#define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff + +#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000 +#define TX_MSDU_START_FIRST_MSDU_LSB 14 +#define TX_MSDU_START_FIRST_MSDU_MSB 14 +#define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000 + +#define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000 +#define TX_MSDU_START_LAST_MSDU_LSB 15 +#define TX_MSDU_START_LAST_MSDU_MSB 15 +#define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000 + +#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_ENCAP_TYPE_LSB 16 +#define TX_MSDU_START_ENCAP_TYPE_MSB 17 +#define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000 + +#define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_EPD_EN_LSB 18 +#define TX_MSDU_START_EPD_EN_MSB 18 +#define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000 + +#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000 +#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 +#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 +#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000 + +#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000 + +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000 + +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000 + +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000 + +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000 + +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000 + +#define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_0A_LSB 27 +#define TX_MSDU_START_RESERVED_0A_MSB 31 +#define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000 + +#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TSO_ENABLE_LSB 32 +#define TX_MSDU_START_TSO_ENABLE_MSB 32 +#define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000 + +#define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_1A_LSB 33 +#define TX_MSDU_START_RESERVED_1A_MSB 38 +#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000 + +#define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_FLAG_LSB 39 +#define TX_MSDU_START_TCP_FLAG_MSB 47 +#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000 + +#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_FLAG_MASK_LSB 48 +#define TX_MSDU_START_TCP_FLAG_MASK_MSB 56 +#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000 + +#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_MESH_ENABLE_LSB 57 +#define TX_MSDU_START_MESH_ENABLE_MSB 57 +#define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000 + +#define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_1B_LSB 58 +#define TX_MSDU_START_RESERVED_1B_MSB 63 +#define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000 + +#define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008 +#define TX_MSDU_START_L2_LENGTH_LSB 0 +#define TX_MSDU_START_L2_LENGTH_MSB 15 +#define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff + +#define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008 +#define TX_MSDU_START_IP_LENGTH_LSB 16 +#define TX_MSDU_START_IP_LENGTH_MSB 31 +#define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000 + +#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008 +#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 + +#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010 +#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff + +#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 +#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 +#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000 + +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000 + +#define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_4_LSB 30 +#define TX_MSDU_START_RESERVED_4_MSB 31 +#define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000 + +#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000 + +#define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_5A_LSB 46 +#define TX_MSDU_START_RESERVED_5A_MSB 47 +#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000 + +#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000 + +#define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_5B_LSB 62 +#define TX_MSDU_START_RESERVED_5B_MSB 63 +#define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000 + +#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018 +#define TX_MSDU_START_UDP_LENGTH_LSB 0 +#define TX_MSDU_START_UDP_LENGTH_MSB 15 +#define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff + +#define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018 +#define TX_MSDU_START_RESERVED_6_LSB 16 +#define TX_MSDU_START_RESERVED_6_MSB 31 +#define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000 + +#define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018 +#define TX_MSDU_START_TLV64_PADDING_LSB 32 +#define TX_MSDU_START_TLV64_PADDING_MSB 63 +#define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_peer_entry.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_peer_entry.h new file mode 100644 index 0000000000000000000000000000000000000000..d9213c4e8813d24ec8ae587cef32f4d8e34ce8f3 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_peer_entry.h @@ -0,0 +1,295 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_PEER_ENTRY_H_ +#define _TX_PEER_ENTRY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_PEER_ENTRY 18 + +#define NUM_OF_QWORDS_TX_PEER_ENTRY 9 + +struct tx_peer_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mac_addr_a_31_0 : 32; + uint32_t mac_addr_a_47_32 : 16, + mac_addr_b_15_0 : 16; + uint32_t mac_addr_b_47_16 : 32; + uint32_t use_ad_b : 1, + strip_insert_vlan_inner : 1, + strip_insert_vlan_outer : 1, + vlan_llc_mode : 1, + key_type : 4, + a_msdu_wds_ad3_ad4 : 3, + ignore_hard_filters : 1, + ignore_soft_filters : 1, + epd_output : 1, + wds : 1, + insert_or_strip : 1, + sw_filter_id : 16; + uint32_t temporal_key_31_0 : 32; + uint32_t temporal_key_63_32 : 32; + uint32_t temporal_key_95_64 : 32; + uint32_t temporal_key_127_96 : 32; + uint32_t temporal_key_159_128 : 32; + uint32_t temporal_key_191_160 : 32; + uint32_t temporal_key_223_192 : 32; + uint32_t temporal_key_255_224 : 32; + uint32_t sta_partial_aid : 11, + transmit_vif : 4, + block_this_user : 1, + mesh_amsdu_mode : 2, + use_qos_alt_mute_mask : 1, + dl_ul_direction : 1, + reserved_12 : 12; + uint32_t insert_vlan_outer_tci : 16, + insert_vlan_inner_tci : 16; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0008 : 16, + __reserved_g_0009 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t multi_link_addr_crypto_enable : 1, + reserved_17a : 15, + sw_peer_id : 16; +#else + uint32_t mac_addr_a_31_0 : 32; + uint32_t mac_addr_b_15_0 : 16, + mac_addr_a_47_32 : 16; + uint32_t mac_addr_b_47_16 : 32; + uint32_t sw_filter_id : 16, + insert_or_strip : 1, + wds : 1, + epd_output : 1, + ignore_soft_filters : 1, + ignore_hard_filters : 1, + a_msdu_wds_ad3_ad4 : 3, + key_type : 4, + vlan_llc_mode : 1, + strip_insert_vlan_outer : 1, + strip_insert_vlan_inner : 1, + use_ad_b : 1; + uint32_t temporal_key_31_0 : 32; + uint32_t temporal_key_63_32 : 32; + uint32_t temporal_key_95_64 : 32; + uint32_t temporal_key_127_96 : 32; + uint32_t temporal_key_159_128 : 32; + uint32_t temporal_key_191_160 : 32; + uint32_t temporal_key_223_192 : 32; + uint32_t temporal_key_255_224 : 32; + uint32_t reserved_12 : 12, + dl_ul_direction : 1, + use_qos_alt_mute_mask : 1, + mesh_amsdu_mode : 2, + block_this_user : 1, + transmit_vif : 4, + sta_partial_aid : 11; + uint32_t insert_vlan_inner_tci : 16, + insert_vlan_outer_tci : 16; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0009 : 16, + __reserved_g_0008 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t sw_peer_id : 16, + reserved_17a : 15, + multi_link_addr_crypto_enable : 1; +#endif +}; + +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 + +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 + +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_USE_AD_B_LSB 32 +#define TX_PEER_ENTRY_USE_AD_B_MSB 32 +#define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 + +#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 + +#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_KEY_TYPE_LSB 36 +#define TX_PEER_ENTRY_KEY_TYPE_MSB 39 +#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 + +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 + +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 + +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 + +#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 +#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 +#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 + +#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_WDS_LSB 46 +#define TX_PEER_ENTRY_WDS_MSB 46 +#define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 + +#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 + +#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 +#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 +#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 + +#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff + +#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 + +#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 + +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 + +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 + +#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 + +#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_RESERVED_12_LSB 20 +#define TX_PEER_ENTRY_RESERVED_12_MSB 31 +#define TX_PEER_ENTRY_RESERVED_12_MASK 0x00000000fff00000 + +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 + +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 + +#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_RESERVED_17A_LSB 33 +#define TX_PEER_ENTRY_RESERVED_17A_MSB 47 +#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe00000000 + +#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 +#define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 +#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_queue_extension.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_queue_extension.h new file mode 100644 index 0000000000000000000000000000000000000000..938e3bcad7b852537a6da43fcf7579256a6c308c --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_queue_extension.h @@ -0,0 +1,322 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_QUEUE_EXTENSION_H_ +#define _TX_QUEUE_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 + +#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 7 + +struct tx_queue_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t frame_ctl : 16, + qos_ctl : 16; + uint32_t ampdu_flag : 1, + tx_notify_no_htc_override : 1, + reserved_1a : 7, + checksum_tso_disable_for_frag : 1, + key_id : 8, + qos_buf_state_overwrite : 1, + buf_state_sta_id : 1, + buf_state_source : 1, + ht_control_overwrite_enable : 1, + ht_control_overwrite_source : 4, + reserved_1b : 6; + uint32_t ul_headroom_insertion_enable : 1, + ul_headroom_offset : 5, + bqrp_insertion_enable : 1, + bqrp_offset : 5, + ul_headroom_rsvd_7_6 : 2, + bqr_rsvd_9_8 : 2, + base_pn_63_48 : 16; + uint32_t base_pn_95_64 : 32; + uint32_t base_pn_127_96 : 32; + uint32_t ht_control_field_bw20 : 32; + uint32_t ht_control_field_bw40 : 32; + uint32_t ht_control_field_bw80 : 32; + uint32_t ht_control_field_bw160 : 32; + uint32_t ht_control_overwrite_mask : 32; + uint32_t cas_control_info : 8, + cas_offset : 5, + cas_insertion_enable : 1, + reserved_10a : 2, + ht_control_overwrite_source_for_srp : 4, + ht_control_overwrite_source_for_bsrp : 4, + reserved_10b : 6, + mpdu_hdr_len_override_en : 1, + bar_ssn_overwrite_enable : 1; + uint32_t bar_ssn_offset : 12, + mpdu_hdr_len_override_val : 9, + reserved_11a : 11; + uint32_t ht_control_field_bw320 : 32; + uint32_t fw2sw_info : 32; +#else + uint32_t qos_ctl : 16, + frame_ctl : 16; + uint32_t reserved_1b : 6, + ht_control_overwrite_source : 4, + ht_control_overwrite_enable : 1, + buf_state_source : 1, + buf_state_sta_id : 1, + qos_buf_state_overwrite : 1, + key_id : 8, + checksum_tso_disable_for_frag : 1, + reserved_1a : 7, + tx_notify_no_htc_override : 1, + ampdu_flag : 1; + uint32_t base_pn_63_48 : 16, + bqr_rsvd_9_8 : 2, + ul_headroom_rsvd_7_6 : 2, + bqrp_offset : 5, + bqrp_insertion_enable : 1, + ul_headroom_offset : 5, + ul_headroom_insertion_enable : 1; + uint32_t base_pn_95_64 : 32; + uint32_t base_pn_127_96 : 32; + uint32_t ht_control_field_bw20 : 32; + uint32_t ht_control_field_bw40 : 32; + uint32_t ht_control_field_bw80 : 32; + uint32_t ht_control_field_bw160 : 32; + uint32_t ht_control_overwrite_mask : 32; + uint32_t bar_ssn_overwrite_enable : 1, + mpdu_hdr_len_override_en : 1, + reserved_10b : 6, + ht_control_overwrite_source_for_bsrp : 4, + ht_control_overwrite_source_for_srp : 4, + reserved_10a : 2, + cas_insertion_enable : 1, + cas_offset : 5, + cas_control_info : 8; + uint32_t reserved_11a : 11, + mpdu_hdr_len_override_val : 9, + bar_ssn_offset : 12; + uint32_t ht_control_field_bw320 : 32; + uint32_t fw2sw_info : 32; +#endif +}; + +#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff + +#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 +#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 +#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 + +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 + +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 + +#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 + +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 + +#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 +#define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 +#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 + +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 + +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 + +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 + +#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e + +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 + +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 + +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 + +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 + +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 + +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x0000000000000010 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff00000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x0000000000000018 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0x00000000ffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000000000000018 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff00000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x0000000000000020 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0x00000000ffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 + +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff + +#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 + +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 + +#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 + +#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003f000000 + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 + +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 + +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 + +#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x0000000000000030 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0x00000000ffffffff + +#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 32 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 63 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_raw_or_native_frame_setup.h new file mode 100644 index 0000000000000000000000000000000000000000..c54443a327210b86c824aadb5fa7ded946d4a8d3 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_raw_or_native_frame_setup.h @@ -0,0 +1,280 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ +#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 + +#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 1 + +struct tx_raw_or_native_frame_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fc_to_ds_mask : 1, + fc_from_ds_mask : 1, + fc_more_frag_mask : 1, + fc_retry_mask : 1, + fc_pwr_mgt_mask : 1, + fc_more_data_mask : 1, + fc_prot_frame_mask : 1, + fc_order_mask : 1, + duration_field_mask : 1, + sequence_control_mask : 1, + qc_tid_mask : 1, + qc_eosp_mask : 1, + qc_ack_policy_mask : 1, + qc_amsdu_mask : 1, + reserved_0a : 1, + qc_15to8_mask : 1, + iv_mask : 1, + fc_to_ds_setting : 1, + fc_from_ds_setting : 1, + fc_more_frag_setting : 1, + fc_retry_setting : 2, + fc_pwr_mgt_setting : 1, + fc_more_data_setting : 2, + fc_prot_frame_setting : 2, + fc_order_setting : 1, + qc_tid_setting : 4; + uint32_t qc_eosp_setting : 2, + qc_ack_policy_setting : 2, + qc_amsdu_setting : 1, + qc_15to8_setting : 8, + mlo_addr_override : 1, + mlo_ignore_addr3_override : 1, + sequence_control_source : 1, + fragment_number : 4, + sequence_number : 12; +#else + uint32_t qc_tid_setting : 4, + fc_order_setting : 1, + fc_prot_frame_setting : 2, + fc_more_data_setting : 2, + fc_pwr_mgt_setting : 1, + fc_retry_setting : 2, + fc_more_frag_setting : 1, + fc_from_ds_setting : 1, + fc_to_ds_setting : 1, + iv_mask : 1, + qc_15to8_mask : 1, + reserved_0a : 1, + qc_amsdu_mask : 1, + qc_ack_policy_mask : 1, + qc_eosp_mask : 1, + qc_tid_mask : 1, + sequence_control_mask : 1, + duration_field_mask : 1, + fc_order_mask : 1, + fc_prot_frame_mask : 1, + fc_more_data_mask : 1, + fc_pwr_mgt_mask : 1, + fc_retry_mask : 1, + fc_more_frag_mask : 1, + fc_from_ds_mask : 1, + fc_to_ds_mask : 1; + uint32_t sequence_number : 12, + fragment_number : 4, + sequence_control_source : 1, + mlo_ignore_addr3_override : 1, + mlo_addr_override : 1, + qc_15to8_setting : 8, + qc_amsdu_setting : 1, + qc_ack_policy_setting : 2, + qc_eosp_setting : 2; +#endif +}; + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x0000000000000001 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x0000000000000002 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x0000000000000004 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x0000000000000008 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x0000000000000010 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x0000000000000020 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x0000000000000040 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x0000000000000080 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x0000000000000100 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x0000000000000200 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x0000000000000400 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x0000000000000800 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x0000000000001000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x0000000000002000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x0000000000004000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x0000000000008000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x0000000000010000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x0000000000020000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x0000000000040000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x0000000000080000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x0000000000300000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x0000000000400000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x0000000001800000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x0000000006000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x0000000008000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0x00000000f0000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 32 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 33 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x0000000300000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 34 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 35 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c00000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 36 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 36 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x0000001000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 37 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 44 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 45 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 45 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x0000200000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 46 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 46 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x0000400000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 47 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 47 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x0000800000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 48 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 51 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f000000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 52 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 63 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff0000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/kiwi/v2/txpcu_buffer_basics.h new file mode 100644 index 0000000000000000000000000000000000000000..6ced947af53d5d71d1601401c99200d2bf0036c1 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/txpcu_buffer_basics.h @@ -0,0 +1,54 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TXPCU_BUFFER_BASICS_H_ +#define _TXPCU_BUFFER_BASICS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 + +struct txpcu_buffer_basics { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t available_memory : 8, + partial_tx_data_tlv_count : 8, + tx_data_tlv_count : 16; +#else + uint32_t tx_data_tlv_count : 16, + partial_tx_data_tlv_count : 8, + available_memory : 8; +#endif +}; + +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff + +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/kiwi/v2/txpcu_buffer_status.h new file mode 100644 index 0000000000000000000000000000000000000000..ce665cbd92fdfb89b2533cb82951b80aedc227ec --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/txpcu_buffer_status.h @@ -0,0 +1,74 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TXPCU_BUFFER_STATUS_H_ +#define _TXPCU_BUFFER_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 + +#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1 + +struct txpcu_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t reserved : 15, + msdu_end : 1, + tx_data_sync_value : 16; +#else + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t tx_data_sync_value : 16, + msdu_end : 1, + reserved : 15; +#endif +}; + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 + +#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_RESERVED_LSB 32 +#define TXPCU_BUFFER_STATUS_RESERVED_MSB 46 +#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000 + +#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47 +#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47 +#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 + +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/kiwi/v2/txpcu_user_buffer_status.h new file mode 100644 index 0000000000000000000000000000000000000000..21dfda17c7a7714c3178011f76df9cb2d838c3f6 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/txpcu_user_buffer_status.h @@ -0,0 +1,81 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TXPCU_USER_BUFFER_STATUS_H_ +#define _TXPCU_USER_BUFFER_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 + +#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1 + +struct txpcu_user_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t stored_word_count_user : 14, + reserved_1a : 1, + msdu_end : 1, + tx_data_sync_value : 16; +#else + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t tx_data_sync_value : 16, + msdu_end : 1, + reserved_1a : 1, + stored_word_count_user : 14; +#endif +}; + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 + +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 32 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 45 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff00000000 + +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 46 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 46 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x0000400000000000 + +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 47 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 47 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 + +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/kiwi/v2/u_sig_eht_su_mu_info.h new file mode 100644 index 0000000000000000000000000000000000000000..38974da9e61240591ab60d141d230b5322e26581 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/u_sig_eht_su_mu_info.h @@ -0,0 +1,173 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _U_SIG_EHT_SU_MU_INFO_H_ +#define _U_SIG_EHT_SU_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 + +struct u_sig_eht_su_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, + transmit_bw : 3, + dl_ul_flag : 1, + bss_color_id : 6, + txop_duration : 7, + disregard_0a : 5, + validate_0b : 1, + reserved_0c : 6; + uint32_t eht_ppdu_sig_cmn_type : 2, + validate_1a : 1, + punctured_channel_information : 5, + validate_1b : 1, + mcs_of_eht_sig : 2, + num_eht_sig_symbols : 5, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + reserved_1d : 3, + rx_ndp : 1, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0c : 6, + validate_0b : 1, + disregard_0a : 5, + txop_duration : 7, + bss_color_id : 6, + dl_ul_flag : 1, + transmit_bw : 3, + phy_version : 3; + uint32_t rx_integrity_check_passed : 1, + rx_ndp : 1, + reserved_1d : 3, + dot11ax_su_extended : 1, + tail : 6, + crc : 4, + num_eht_sig_symbols : 5, + mcs_of_eht_sig : 2, + validate_1b : 1, + punctured_channel_information : 5, + validate_1a : 1, + eht_ppdu_sig_cmn_type : 2; +#endif +}; + +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 + +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 + +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 + +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 + +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 + +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 + +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 + +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 + +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 + +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 + +#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 +#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 + +#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 + +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 + +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 + +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/kiwi/v2/u_sig_eht_tb_info.h new file mode 100644 index 0000000000000000000000000000000000000000..e62ff3dd18aacaaa8c4547a73ee2d6b8b8638c79 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/u_sig_eht_tb_info.h @@ -0,0 +1,138 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _U_SIG_EHT_TB_INFO_H_ +#define _U_SIG_EHT_TB_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 + +struct u_sig_eht_tb_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, + transmit_bw : 3, + dl_ul_flag : 1, + bss_color_id : 6, + txop_duration : 7, + disregard_0a : 6, + reserved_0c : 6; + uint32_t eht_ppdu_sig_cmn_type : 2, + validate_1a : 1, + spatial_reuse : 8, + disregard_1b : 5, + crc : 4, + tail : 6, + reserved_1c : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0c : 6, + disregard_0a : 6, + txop_duration : 7, + bss_color_id : 6, + dl_ul_flag : 1, + transmit_bw : 3, + phy_version : 3; + uint32_t rx_integrity_check_passed : 1, + reserved_1c : 5, + tail : 6, + crc : 4, + disregard_1b : 5, + spatial_reuse : 8, + validate_1a : 1, + eht_ppdu_sig_cmn_type : 2; +#endif +}; + +#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 + +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 + +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 + +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 + +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 + +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 + +#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 + +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 + +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 + +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 + +#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_CRC_LSB 16 +#define U_SIG_EHT_TB_INFO_CRC_MSB 19 +#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 + +#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 +#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 +#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 + +#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 + +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/kiwi/v2/unallocated_ru_160_info.h new file mode 100644 index 0000000000000000000000000000000000000000..23b78179ff68ae33c644c430c3ffc13c5b8fa317 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/unallocated_ru_160_info.h @@ -0,0 +1,61 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNALLOCATED_RU_160_INFO_H_ +#define _UNALLOCATED_RU_160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 + +struct unallocated_ru_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t subband80_0_cc0 : 8, + subband80_0_cc1 : 8, + subband80_1_cc0 : 8, + subband80_1_cc1 : 8; +#else + uint32_t subband80_1_cc1 : 8, + subband80_1_cc0 : 8, + subband80_0_cc1 : 8, + subband80_0_cc0 : 8; +#endif +}; + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu160_info.h new file mode 100644 index 0000000000000000000000000000000000000000..408c0a65e1f21d950b066db5fe9c744a761c1318 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu160_info.h @@ -0,0 +1,257 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_MU160_INFO_H_ +#define _VHT_SIG_B_MU160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 + +struct vht_sig_b_mu160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + mcs : 4, + tail : 6, + reserved_0 : 3; + uint32_t length_copy_a : 19, + mcs_copy_a : 4, + tail_copy_a : 6, + reserved_1 : 3; + uint32_t length_copy_b : 19, + mcs_copy_b : 4, + tail_copy_b : 6, + reserved_2 : 3; + uint32_t length_copy_c : 19, + mcs_copy_c : 4, + tail_copy_c : 6, + reserved_3 : 3; + uint32_t length_copy_d : 19, + mcs_copy_d : 4, + tail_copy_d : 6, + reserved_4 : 3; + uint32_t length_copy_e : 19, + mcs_copy_e : 4, + tail_copy_e : 6, + reserved_5 : 3; + uint32_t length_copy_f : 19, + mcs_copy_f : 4, + tail_copy_f : 6, + mu_user_number : 3; + uint32_t length_copy_g : 19, + mcs_copy_g : 4, + tail_copy_g : 6, + reserved_7 : 3; +#else + uint32_t reserved_0 : 3, + tail : 6, + mcs : 4, + length : 19; + uint32_t reserved_1 : 3, + tail_copy_a : 6, + mcs_copy_a : 4, + length_copy_a : 19; + uint32_t reserved_2 : 3, + tail_copy_b : 6, + mcs_copy_b : 4, + length_copy_b : 19; + uint32_t reserved_3 : 3, + tail_copy_c : 6, + mcs_copy_c : 4, + length_copy_c : 19; + uint32_t reserved_4 : 3, + tail_copy_d : 6, + mcs_copy_d : 4, + length_copy_d : 19; + uint32_t reserved_5 : 3, + tail_copy_e : 6, + mcs_copy_e : 4, + length_copy_e : 19; + uint32_t mu_user_number : 3, + tail_copy_f : 6, + mcs_copy_f : 4, + length_copy_f : 19; + uint32_t reserved_7 : 3, + tail_copy_g : 6, + mcs_copy_g : 4, + length_copy_g : 19; +#endif +}; + +#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu20_info.h new file mode 100644 index 0000000000000000000000000000000000000000..0c45d622217c5d9fe41e8416e9c774783514444e --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu20_info.h @@ -0,0 +1,68 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_MU20_INFO_H_ +#define _VHT_SIG_B_MU20_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 + +struct vht_sig_b_mu20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 16, + mcs : 4, + tail : 6, + mu_user_number : 3, + reserved_0 : 3; +#else + uint32_t reserved_0 : 3, + mu_user_number : 3, + tail : 6, + mcs : 4, + length : 16; +#endif +}; + +#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 +#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff + +#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 +#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 +#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 + +#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 + +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 + +#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu40_info.h new file mode 100644 index 0000000000000000000000000000000000000000..7692f5df62aa7f384561699b70209886b38f5a0d --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu40_info.h @@ -0,0 +1,96 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_MU40_INFO_H_ +#define _VHT_SIG_B_MU40_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 + +struct vht_sig_b_mu40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, + mcs : 4, + tail : 6, + reserved_0 : 2, + mu_user_number : 3; + uint32_t length_copy : 17, + mcs_copy : 4, + tail_copy : 6, + reserved_1 : 5; +#else + uint32_t mu_user_number : 3, + reserved_0 : 2, + tail : 6, + mcs : 4, + length : 17; + uint32_t reserved_1 : 5, + tail_copy : 6, + mcs_copy : 4, + length_copy : 17; +#endif +}; + +#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff + +#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 + +#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 + +#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 + +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff + +#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 + +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 + +#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu80_info.h new file mode 100644 index 0000000000000000000000000000000000000000..0e4d483d4a2e6f37355edf90ae2f301d1852d3ca --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu80_info.h @@ -0,0 +1,145 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_MU80_INFO_H_ +#define _VHT_SIG_B_MU80_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 + +struct vht_sig_b_mu80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + mcs : 4, + tail : 6, + reserved_0 : 3; + uint32_t length_copy_a : 19, + mcs_copy_a : 4, + tail_copy_a : 6, + reserved_1 : 3; + uint32_t length_copy_b : 19, + mcs_copy_b : 4, + tail_copy_b : 6, + mu_user_number : 3; + uint32_t length_copy_c : 19, + mcs_copy_c : 4, + tail_copy_c : 6, + reserved_3 : 3; +#else + uint32_t reserved_0 : 3, + tail : 6, + mcs : 4, + length : 19; + uint32_t reserved_1 : 3, + tail_copy_a : 6, + mcs_copy_a : 4, + length_copy_a : 19; + uint32_t mu_user_number : 3, + tail_copy_b : 6, + mcs_copy_b : 4, + length_copy_b : 19; + uint32_t reserved_3 : 3, + tail_copy_c : 6, + mcs_copy_c : 4, + length_copy_c : 19; +#endif +}; + +#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su160_info.h new file mode 100644 index 0000000000000000000000000000000000000000..73b0f14703747361c7d17d5b345a3b59deee744a --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su160_info.h @@ -0,0 +1,313 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_SU160_INFO_H_ +#define _VHT_SIG_B_SU160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 + +struct vht_sig_b_su160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, + vhtb_reserved : 2, + tail : 6, + reserved_0 : 2, + rx_ndp : 1; + uint32_t length_copy_a : 21, + vhtb_reserved_copy_a : 2, + tail_copy_a : 6, + reserved_1 : 2, + rx_ndp_copy_a : 1; + uint32_t length_copy_b : 21, + vhtb_reserved_copy_b : 2, + tail_copy_b : 6, + reserved_2 : 2, + rx_ndp_copy_b : 1; + uint32_t length_copy_c : 21, + vhtb_reserved_copy_c : 2, + tail_copy_c : 6, + reserved_3 : 2, + rx_ndp_copy_c : 1; + uint32_t length_copy_d : 21, + vhtb_reserved_copy_d : 2, + tail_copy_d : 6, + reserved_4 : 2, + rx_ndp_copy_d : 1; + uint32_t length_copy_e : 21, + vhtb_reserved_copy_e : 2, + tail_copy_e : 6, + reserved_5 : 2, + rx_ndp_copy_e : 1; + uint32_t length_copy_f : 21, + vhtb_reserved_copy_f : 2, + tail_copy_f : 6, + reserved_6 : 2, + rx_ndp_copy_f : 1; + uint32_t length_copy_g : 21, + vhtb_reserved_copy_g : 2, + tail_copy_g : 6, + reserved_7 : 2, + rx_ndp_copy_g : 1; +#else + uint32_t rx_ndp : 1, + reserved_0 : 2, + tail : 6, + vhtb_reserved : 2, + length : 21; + uint32_t rx_ndp_copy_a : 1, + reserved_1 : 2, + tail_copy_a : 6, + vhtb_reserved_copy_a : 2, + length_copy_a : 21; + uint32_t rx_ndp_copy_b : 1, + reserved_2 : 2, + tail_copy_b : 6, + vhtb_reserved_copy_b : 2, + length_copy_b : 21; + uint32_t rx_ndp_copy_c : 1, + reserved_3 : 2, + tail_copy_c : 6, + vhtb_reserved_copy_c : 2, + length_copy_c : 21; + uint32_t rx_ndp_copy_d : 1, + reserved_4 : 2, + tail_copy_d : 6, + vhtb_reserved_copy_d : 2, + length_copy_d : 21; + uint32_t rx_ndp_copy_e : 1, + reserved_5 : 2, + tail_copy_e : 6, + vhtb_reserved_copy_e : 2, + length_copy_e : 21; + uint32_t rx_ndp_copy_f : 1, + reserved_6 : 2, + tail_copy_f : 6, + vhtb_reserved_copy_f : 2, + length_copy_f : 21; + uint32_t rx_ndp_copy_g : 1, + reserved_7 : 2, + tail_copy_g : 6, + vhtb_reserved_copy_g : 2, + length_copy_g : 21; +#endif +}; + +#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su20_info.h new file mode 100644 index 0000000000000000000000000000000000000000..f76a9f0680b89bee8890ad767ac13aa551c406b2 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su20_info.h @@ -0,0 +1,68 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_SU20_INFO_H_ +#define _VHT_SIG_B_SU20_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 + +struct vht_sig_b_su20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, + vhtb_reserved : 3, + tail : 6, + reserved : 5, + rx_ndp : 1; +#else + uint32_t rx_ndp : 1, + reserved : 5, + tail : 6, + vhtb_reserved : 3, + length : 17; +#endif +}; + +#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff + +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 + +#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 + +#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 +#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 + +#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su40_info.h new file mode 100644 index 0000000000000000000000000000000000000000..d3439bf6e8ba34e9d243247257551b21c5fcf05e --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su40_info.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_SU40_INFO_H_ +#define _VHT_SIG_B_SU40_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 + +struct vht_sig_b_su40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + vhtb_reserved : 2, + tail : 6, + reserved : 4, + rx_ndp : 1; + uint32_t length_copy : 19, + vhtb_reserved_copy : 2, + tail_copy : 6, + reserved_copy : 4, + rx_ndp_copy : 1; +#else + uint32_t rx_ndp : 1, + reserved : 4, + tail : 6, + vhtb_reserved : 2, + length : 19; + uint32_t rx_ndp_copy : 1, + reserved_copy : 4, + tail_copy : 6, + vhtb_reserved_copy : 2, + length_copy : 19; +#endif +}; + +#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 + +#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 + +#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 + +#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 + +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 + +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 + +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su80_info.h new file mode 100644 index 0000000000000000000000000000000000000000..1cf37a4864b8b3412ca7e109325be2792bb92ef1 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su80_info.h @@ -0,0 +1,173 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_SU80_INFO_H_ +#define _VHT_SIG_B_SU80_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 + +struct vht_sig_b_su80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, + vhtb_reserved : 2, + tail : 6, + reserved_0 : 2, + rx_ndp : 1; + uint32_t length_copy_a : 21, + vhtb_reserved_copy_a : 2, + tail_copy_a : 6, + reserved_1 : 2, + rx_ndp_copy_a : 1; + uint32_t length_copy_b : 21, + vhtb_reserved_copy_b : 2, + tail_copy_b : 6, + reserved_2 : 2, + rx_ndp_copy_b : 1; + uint32_t length_copy_c : 21, + vhtb_reserved_copy_c : 2, + tail_copy_c : 6, + reserved_3 : 2, + rx_ndp_copy_c : 1; +#else + uint32_t rx_ndp : 1, + reserved_0 : 2, + tail : 6, + vhtb_reserved : 2, + length : 21; + uint32_t rx_ndp_copy_a : 1, + reserved_1 : 2, + tail_copy_a : 6, + vhtb_reserved_copy_a : 2, + length_copy_a : 21; + uint32_t rx_ndp_copy_b : 1, + reserved_2 : 2, + tail_copy_b : 6, + vhtb_reserved_copy_b : 2, + length_copy_b : 21; + uint32_t rx_ndp_copy_c : 1, + reserved_3 : 2, + tail_copy_c : 6, + vhtb_reserved_copy_c : 2, + length_copy_c : 21; +#endif +}; + +#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/kiwi/v2/wcss_seq_hwioreg_umac.h index 7c7ebed4f9014afe1ce4155d9e30f2842f142239..f594c525deedaba32d495f371875580f04d43198 100644 --- a/drivers/staging/fw-api/hw/kiwi/v2/wcss_seq_hwioreg_umac.h +++ b/drivers/staging/fw-api/hw/kiwi/v2/wcss_seq_hwioreg_umac.h @@ -1,6 +1,5 @@ - /* - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -236,6 +235,11 @@ #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x53c) #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x540) #define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x544) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x558) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x55c) #define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0x8a4) #define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 diff --git a/drivers/staging/fw-api/hw/peach/v1/HALcomdef.h b/drivers/staging/fw-api/hw/peach/v1/HALcomdef.h new file mode 100644 index 0000000000000000000000000000000000000000..307eb8d09aa6994a79429dc82efe953c8dcca0e2 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/HALcomdef.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef HAL_COMDEF_H +#define HAL_COMDEF_H + +#ifndef _ARM_ASM_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "com_dtypes.h" + +#ifndef _BOOL32_DEFINED +typedef unsigned long int bool32; +#define _BOOL32_DEFINED +#endif + +#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF + + #define inp(port) (*((volatile byte *) (port))) + #define inpw(port) (*((volatile word *) (port))) + #define inpdw(port) (*((volatile dword *)(port))) + + #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) + #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) + #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + diff --git a/drivers/staging/fw-api/hw/peach/v1/HALhwio.h b/drivers/staging/fw-api/hw/peach/v1/HALhwio.h new file mode 100644 index 0000000000000000000000000000000000000000..1fce6d0729b26783d565d149c72fcb4f6516ca93 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/HALhwio.h @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef HAL_HWIO_H +#define HAL_HWIO_H + +#include "HALcomdef.h" + +#define HWIO_BASE_PTR(base) base##_BASE_PTR + +#ifdef __ARMCC_VERSION + #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) +#else + #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) +#endif + +#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) +#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) +#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) +#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) + +#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) +#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) +#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) +#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) +#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) +#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) +#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) + +#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) +#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) +#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) +#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) +#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) +#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) +#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) + +#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) +#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) +#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) +#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) + +#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) +#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) +#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) +#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) + +#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) +#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) +#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) +#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) +#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) +#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) +#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) + +#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) +#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) +#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) +#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) + +#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) +#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) +#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) +#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) +#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) +#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) +#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) + +#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) +#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) +#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) +#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) +#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) +#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) +#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) + +#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) +#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) +#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) +#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) +#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) +#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) +#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) + +#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) +#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) + +#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN +#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) +#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) +#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) +#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) +#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) +#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) +#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) +#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) +#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) +#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) +#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) +#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) +#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) +#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) +#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) +#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR +#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) +#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) +#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) +#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS +#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) +#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) +#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) +#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) +#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) +#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK +#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) +#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK +#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT +#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT +#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow +#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) +#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL + +#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) +#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) +#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) +#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) +#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) +#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) +#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) +#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) +#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) +#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) +#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) +#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) +#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) +#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ + static unsigned int Readdata, Val_temp, Val;\ + Readdata = HWIO_INX(base, hwiosym); \ + Val_temp = Readdata & ~mask1 & ~mask2; \ + Val = Val_temp | val1 | val2; \ + HWIO_##hwiosym##_OUT(base, Val); \ + } + +#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + static unsigned int Readdata1, Val_temp1, Val1;\ + Readdata1 = HWIO_INX(base, hwiosym); \ + Val_temp1 = Readdata1 & ~mask1 & ~mask2 & ~mask3; \ + Val1 = Val_temp1 | val1 | val2 | val3; \ + HWIO_##hwiosym##_OUT(base, Val1); \ + } + +#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + static unsigned int Readdata2, Val_temp2, Val2;\ + Readdata2 = HWIO_INX(base, hwiosym); \ + Val_temp2 = Readdata2 & ~mask1 & ~mask2 & ~mask3 & ~mask4; \ + Val2 = Val_temp2 | val1 | val2 | val3 | val4; \ + HWIO_##hwiosym##_OUT(base, Val2); \ + } + +#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) +#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) +#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) +#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) +#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) +#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) +#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) +#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) +#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) +#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) +#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) + +#define HWIO_INTLOCK() +#define HWIO_INTFREE() + +#define __inp(port) (*((volatile uint8 *) (port))) +#define __inpw(port) (*((volatile uint16 *) (port))) +#define __inpdw(port) (*((volatile uint32 *) (port))) +#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) +#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) + +#ifdef HAL_HWIO_EXTERNAL + +#undef __inp +#undef __inpw +#undef __inpdw +#undef __outp +#undef __outpw +#undef __outpdw + +#define __inp(port) __inp_extern(port) +#define __inpw(port) __inpw_extern(port) +#define __inpdw(port) __inpdw_extern(port) +#define __outp(port, val) __outp_extern(port, val) +#define __outpw(port, val) __outpw_extern(port, val) +#define __outpdw(port, val) __outpdw_extern(port, val) + +extern uint8 __inp_extern ( uint32 nAddr ); +extern uint16 __inpw_extern ( uint32 nAddr ); +extern uint32 __inpdw_extern ( uint32 nAddr ); +extern void __outp_extern ( uint32 nAddr, uint8 nData ); +extern void __outpw_extern ( uint32 nAddr, uint16 nData ); +extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); + +#endif + +#define in_byte(addr) (__inp(addr)) +#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) +#define out_byte(addr, val) __outp(addr,val) +#define out_byte_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + out_byte( io, shadow); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + HWIO_INTFREE() +#define out_byte_masked_ns(io, mask, val, current_reg_content) \ + out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_word(addr) (__inpw(addr)) +#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) +#define out_word(addr, val) __outpw(addr,val) +#define out_word_masked(io, mask, val, shadow) \ + HWIO_INTLOCK( ); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + out_word( io, shadow); \ + HWIO_INTFREE( ) +#define out_word_masked_ns(io, mask, val, current_reg_content) \ + out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_dword(addr) (__inpdw(addr)) +#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) +#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ + out_dword( io, shadow); \ + HWIO_INTFREE() +#define out_dword_masked_ns(io, mask, val, current_reg_content) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + ((uint32)((val) & (mask)))) ) + +#endif + diff --git a/drivers/staging/fw-api/hw/peach/v1/ack_report.h b/drivers/staging/fw-api/hw/peach/v1/ack_report.h new file mode 100644 index 0000000000000000000000000000000000000000..6b00b2ee99f0c24f36d4607b0b1a537a8ab6125a --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/ack_report.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _ACK_REPORT_H_ +#define _ACK_REPORT_H_ + +#define NUM_OF_DWORDS_ACK_REPORT 1 + +struct ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t selfgen_response_reason : 4, + ax_trigger_type : 4, + sr_ppdu : 1, + reserved : 7, + frame_control : 16; +#else + uint32_t frame_control : 16, + reserved : 7, + sr_ppdu : 1, + ax_trigger_type : 4, + selfgen_response_reason : 4; +#endif +}; + +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f + +#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 +#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 +#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 + +#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 +#define ACK_REPORT_SR_PPDU_LSB 8 +#define ACK_REPORT_SR_PPDU_MSB 8 +#define ACK_REPORT_SR_PPDU_MASK 0x00000100 + +#define ACK_REPORT_RESERVED_OFFSET 0x00000000 +#define ACK_REPORT_RESERVED_LSB 9 +#define ACK_REPORT_RESERVED_MSB 15 +#define ACK_REPORT_RESERVED_MASK 0x0000fe00 + +#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define ACK_REPORT_FRAME_CONTROL_LSB 16 +#define ACK_REPORT_FRAME_CONTROL_MSB 31 +#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/beryllium_top_reg.h b/drivers/staging/fw-api/hw/peach/v1/beryllium_top_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..5477be24828e81c2c59ad4b76df8ce54ed971999 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/beryllium_top_reg.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef BERYLLIUM_TOP_REG_H +#define BERYLLIUM_TOP_REG_H + +#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C) +#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050) + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/buffer_addr_info.h b/drivers/staging/fw-api/hw/peach/v1/buffer_addr_info.h new file mode 100644 index 0000000000000000000000000000000000000000..4a8c064ecd163474f6b09ceb012d276fed827e05 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/buffer_addr_info.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _BUFFER_ADDR_INFO_H_ +#define _BUFFER_ADDR_INFO_H_ + +#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 + +struct buffer_addr_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_addr_31_0 : 32; + uint32_t buffer_addr_39_32 : 8, + return_buffer_manager : 4, + sw_buffer_cookie : 20; +#else + uint32_t buffer_addr_31_0 : 32; + uint32_t sw_buffer_cookie : 20, + return_buffer_manager : 4, + buffer_addr_39_32 : 8; +#endif +}; + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/ce_src_desc.h b/drivers/staging/fw-api/hw/peach/v1/ce_src_desc.h new file mode 100644 index 0000000000000000000000000000000000000000..3aa8b5850feade17e44bf502fa7029f4ee937286 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/ce_src_desc.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _CE_SRC_DESC_H_ +#define _CE_SRC_DESC_H_ + +#define NUM_OF_DWORDS_CE_SRC_DESC 4 + +struct ce_src_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_buffer_low : 32; + uint32_t src_buffer_high : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + ce_res_0 : 1, + barrier_read : 1, + ce_res_1 : 2, + length : 16; + uint32_t fw_metadata : 16, + ce_res_2 : 16; + uint32_t ce_res_3 : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t src_buffer_low : 32; + uint32_t length : 16, + ce_res_1 : 2, + barrier_read : 1, + ce_res_0 : 1, + gather : 1, + dest_swap : 1, + src_swap : 1, + toeplitz_en : 1, + src_buffer_high : 8; + uint32_t ce_res_2 : 16, + fw_metadata : 16; + uint32_t looping_count : 4, + ring_id : 8, + ce_res_3 : 20; +#endif +}; + +#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000 +#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff + +#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff + +#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004 +#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_SWAP_LSB 9 +#define CE_SRC_DESC_SRC_SWAP_MSB 9 +#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200 + +#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_DEST_SWAP_LSB 10 +#define CE_SRC_DESC_DEST_SWAP_MSB 10 +#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400 + +#define CE_SRC_DESC_GATHER_OFFSET 0x00000004 +#define CE_SRC_DESC_GATHER_LSB 11 +#define CE_SRC_DESC_GATHER_MSB 11 +#define CE_SRC_DESC_GATHER_MASK 0x00000800 + +#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_0_LSB 12 +#define CE_SRC_DESC_CE_RES_0_MSB 12 +#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000 + +#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004 +#define CE_SRC_DESC_BARRIER_READ_LSB 13 +#define CE_SRC_DESC_BARRIER_READ_MSB 13 +#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000 + +#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_1_LSB 14 +#define CE_SRC_DESC_CE_RES_1_MSB 15 +#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000 + +#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004 +#define CE_SRC_DESC_LENGTH_LSB 16 +#define CE_SRC_DESC_LENGTH_MSB 31 +#define CE_SRC_DESC_LENGTH_MASK 0xffff0000 + +#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008 +#define CE_SRC_DESC_FW_METADATA_LSB 0 +#define CE_SRC_DESC_FW_METADATA_MSB 15 +#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff + +#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008 +#define CE_SRC_DESC_CE_RES_2_LSB 16 +#define CE_SRC_DESC_CE_RES_2_MSB 31 +#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000 + +#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c +#define CE_SRC_DESC_CE_RES_3_LSB 0 +#define CE_SRC_DESC_CE_RES_3_MSB 19 +#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff + +#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c +#define CE_SRC_DESC_RING_ID_LSB 20 +#define CE_SRC_DESC_RING_ID_MSB 27 +#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000 + +#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_SRC_DESC_LOOPING_COUNT_LSB 28 +#define CE_SRC_DESC_LOOPING_COUNT_MSB 31 +#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/ce_stat_desc.h b/drivers/staging/fw-api/hw/peach/v1/ce_stat_desc.h new file mode 100644 index 0000000000000000000000000000000000000000..199c25775c0c83c9bd036a63da58b834ae2cf6ef --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/ce_stat_desc.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _CE_STAT_DESC_H_ +#define _CE_STAT_DESC_H_ + +#define NUM_OF_DWORDS_CE_STAT_DESC 4 + +struct ce_stat_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ce_res_5 : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + barrier_read : 1, + ce_res_6 : 3, + length : 16; + uint32_t toeplitz_hash_0 : 32; + uint32_t toeplitz_hash_1 : 32; + uint32_t fw_metadata : 16, + ce_res_7 : 4, + ring_id : 8, + looping_count : 4; +#else + uint32_t length : 16, + ce_res_6 : 3, + barrier_read : 1, + gather : 1, + dest_swap : 1, + src_swap : 1, + toeplitz_en : 1, + ce_res_5 : 8; + uint32_t toeplitz_hash_0 : 32; + uint32_t toeplitz_hash_1 : 32; + uint32_t looping_count : 4, + ring_id : 8, + ce_res_7 : 4, + fw_metadata : 16; +#endif +}; + +#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_5_LSB 0 +#define CE_STAT_DESC_CE_RES_5_MSB 7 +#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff + +#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000 +#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_SRC_SWAP_LSB 9 +#define CE_STAT_DESC_SRC_SWAP_MSB 9 +#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200 + +#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_DEST_SWAP_LSB 10 +#define CE_STAT_DESC_DEST_SWAP_MSB 10 +#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400 + +#define CE_STAT_DESC_GATHER_OFFSET 0x00000000 +#define CE_STAT_DESC_GATHER_LSB 11 +#define CE_STAT_DESC_GATHER_MSB 11 +#define CE_STAT_DESC_GATHER_MASK 0x00000800 + +#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000 +#define CE_STAT_DESC_BARRIER_READ_LSB 12 +#define CE_STAT_DESC_BARRIER_READ_MSB 12 +#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000 + +#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_6_LSB 13 +#define CE_STAT_DESC_CE_RES_6_MSB 15 +#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000 + +#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000 +#define CE_STAT_DESC_LENGTH_LSB 16 +#define CE_STAT_DESC_LENGTH_MSB 31 +#define CE_STAT_DESC_LENGTH_MASK 0xffff0000 + +#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff + +#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff + +#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c +#define CE_STAT_DESC_FW_METADATA_LSB 0 +#define CE_STAT_DESC_FW_METADATA_MSB 15 +#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff + +#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c +#define CE_STAT_DESC_CE_RES_7_LSB 16 +#define CE_STAT_DESC_CE_RES_7_MSB 19 +#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000 + +#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c +#define CE_STAT_DESC_RING_ID_LSB 20 +#define CE_STAT_DESC_RING_ID_MSB 27 +#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000 + +#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_STAT_DESC_LOOPING_COUNT_LSB 28 +#define CE_STAT_DESC_LOOPING_COUNT_MSB 31 +#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/coex_rx_status.h b/drivers/staging/fw-api/hw/peach/v1/coex_rx_status.h new file mode 100644 index 0000000000000000000000000000000000000000..86db6aad11162879759cd68c4b85cb7a53faaa1e --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/coex_rx_status.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _COEX_RX_STATUS_H_ +#define _COEX_RX_STATUS_H_ + +#define NUM_OF_DWORDS_COEX_RX_STATUS 2 + +struct coex_rx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_mac_frame_status : 2, + rx_with_tx_response : 1, + rx_rate : 5, + rx_bw : 3, + single_mpdu : 1, + filter_status : 1, + ampdu : 1, + directed : 1, + reserved_0 : 1, + rx_nss : 3, + rx_rssi : 8, + rx_type : 3, + retry_bit_setting : 1, + more_data_bit_setting : 1; + uint32_t remain_rx_packet_time : 16, + rx_remaining_fes_time : 16; +#else + uint32_t more_data_bit_setting : 1, + retry_bit_setting : 1, + rx_type : 3, + rx_rssi : 8, + rx_nss : 3, + reserved_0 : 1, + directed : 1, + ampdu : 1, + filter_status : 1, + single_mpdu : 1, + rx_bw : 3, + rx_rate : 5, + rx_with_tx_response : 1, + rx_mac_frame_status : 2; + uint32_t rx_remaining_fes_time : 16, + remain_rx_packet_time : 16; +#endif +}; + +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x00000003 + +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x00000004 + +#define COEX_RX_STATUS_RX_RATE_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_RATE_LSB 3 +#define COEX_RX_STATUS_RX_RATE_MSB 7 +#define COEX_RX_STATUS_RX_RATE_MASK 0x000000f8 + +#define COEX_RX_STATUS_RX_BW_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_BW_LSB 8 +#define COEX_RX_STATUS_RX_BW_MSB 10 +#define COEX_RX_STATUS_RX_BW_MASK 0x00000700 + +#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x00000000 +#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x00000800 + +#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x00000000 +#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x00001000 + +#define COEX_RX_STATUS_AMPDU_OFFSET 0x00000000 +#define COEX_RX_STATUS_AMPDU_LSB 13 +#define COEX_RX_STATUS_AMPDU_MSB 13 +#define COEX_RX_STATUS_AMPDU_MASK 0x00002000 + +#define COEX_RX_STATUS_DIRECTED_OFFSET 0x00000000 +#define COEX_RX_STATUS_DIRECTED_LSB 14 +#define COEX_RX_STATUS_DIRECTED_MSB 14 +#define COEX_RX_STATUS_DIRECTED_MASK 0x00004000 + +#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x00000000 +#define COEX_RX_STATUS_RESERVED_0_LSB 15 +#define COEX_RX_STATUS_RESERVED_0_MSB 15 +#define COEX_RX_STATUS_RESERVED_0_MASK 0x00008000 + +#define COEX_RX_STATUS_RX_NSS_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_NSS_LSB 16 +#define COEX_RX_STATUS_RX_NSS_MSB 18 +#define COEX_RX_STATUS_RX_NSS_MASK 0x00070000 + +#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_RSSI_LSB 19 +#define COEX_RX_STATUS_RX_RSSI_MSB 26 +#define COEX_RX_STATUS_RX_RSSI_MASK 0x07f80000 + +#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_TYPE_LSB 27 +#define COEX_RX_STATUS_RX_TYPE_MSB 29 +#define COEX_RX_STATUS_RX_TYPE_MASK 0x38000000 + +#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x00000000 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x40000000 + +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x00000000 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x80000000 + +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x00000004 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 0 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 15 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff + +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x00000004 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 16 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 31 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/coex_tx_req.h b/drivers/staging/fw-api/hw/peach/v1/coex_tx_req.h new file mode 100644 index 0000000000000000000000000000000000000000..a116adb2a132a0e8d5f0db0e3a065864adaa5e38 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/coex_tx_req.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _COEX_TX_REQ_H_ +#define _COEX_TX_REQ_H_ + +#define NUM_OF_DWORDS_COEX_TX_REQ 4 + +struct coex_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_pwr : 8, + min_tx_pwr : 8, + nss : 3, + tx_chain_mask : 8, + bw : 3, + reserved_0 : 2; + uint32_t alt_tx_pwr : 8, + alt_min_tx_pwr : 8, + alt_nss : 3, + alt_tx_chain_mask : 8, + alt_bw : 3, + reserved_1 : 2; + uint32_t tx_pwr_1 : 8, + alt_tx_pwr_1 : 8, + wlan_request_duration : 16; + uint32_t wlan_pkt_type : 4, + coex_tx_reason : 2, + response_frame_type : 5, + wlan_low_priority_slicing_allowed : 1, + wlan_high_priority_slicing_allowed : 1, + sch_tx_burst_ongoing : 1, + coex_tx_priority : 4, + reserved_3a : 14; +#else + uint32_t reserved_0 : 2, + bw : 3, + tx_chain_mask : 8, + nss : 3, + min_tx_pwr : 8, + tx_pwr : 8; + uint32_t reserved_1 : 2, + alt_bw : 3, + alt_tx_chain_mask : 8, + alt_nss : 3, + alt_min_tx_pwr : 8, + alt_tx_pwr : 8; + uint32_t wlan_request_duration : 16, + alt_tx_pwr_1 : 8, + tx_pwr_1 : 8; + uint32_t reserved_3a : 14, + coex_tx_priority : 4, + sch_tx_burst_ongoing : 1, + wlan_high_priority_slicing_allowed : 1, + wlan_low_priority_slicing_allowed : 1, + response_frame_type : 5, + coex_tx_reason : 2, + wlan_pkt_type : 4; +#endif +}; + +#define COEX_TX_REQ_TX_PWR_OFFSET 0x00000000 +#define COEX_TX_REQ_TX_PWR_LSB 0 +#define COEX_TX_REQ_TX_PWR_MSB 7 +#define COEX_TX_REQ_TX_PWR_MASK 0x000000ff + +#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x00000000 +#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 +#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 +#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x0000ff00 + +#define COEX_TX_REQ_NSS_OFFSET 0x00000000 +#define COEX_TX_REQ_NSS_LSB 16 +#define COEX_TX_REQ_NSS_MSB 18 +#define COEX_TX_REQ_NSS_MASK 0x00070000 + +#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x00000000 +#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 +#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 +#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x07f80000 + +#define COEX_TX_REQ_BW_OFFSET 0x00000000 +#define COEX_TX_REQ_BW_LSB 27 +#define COEX_TX_REQ_BW_MSB 29 +#define COEX_TX_REQ_BW_MASK 0x38000000 + +#define COEX_TX_REQ_RESERVED_0_OFFSET 0x00000000 +#define COEX_TX_REQ_RESERVED_0_LSB 30 +#define COEX_TX_REQ_RESERVED_0_MSB 31 +#define COEX_TX_REQ_RESERVED_0_MASK 0xc0000000 + +#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_TX_PWR_LSB 0 +#define COEX_TX_REQ_ALT_TX_PWR_MSB 7 +#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff + +#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 8 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 15 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define COEX_TX_REQ_ALT_NSS_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_NSS_LSB 16 +#define COEX_TX_REQ_ALT_NSS_MSB 18 +#define COEX_TX_REQ_ALT_NSS_MASK 0x00070000 + +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 19 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 26 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define COEX_TX_REQ_ALT_BW_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_BW_LSB 27 +#define COEX_TX_REQ_ALT_BW_MSB 29 +#define COEX_TX_REQ_ALT_BW_MASK 0x38000000 + +#define COEX_TX_REQ_RESERVED_1_OFFSET 0x00000004 +#define COEX_TX_REQ_RESERVED_1_LSB 30 +#define COEX_TX_REQ_RESERVED_1_MSB 31 +#define COEX_TX_REQ_RESERVED_1_MASK 0xc0000000 + +#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x00000008 +#define COEX_TX_REQ_TX_PWR_1_LSB 0 +#define COEX_TX_REQ_TX_PWR_1_MSB 7 +#define COEX_TX_REQ_TX_PWR_1_MASK 0x000000ff + +#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x00000008 +#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 +#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 +#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x0000ff00 + +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x00000008 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0xffff0000 + +#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000c +#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 0 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 3 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f + +#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000c +#define COEX_TX_REQ_COEX_TX_REASON_LSB 4 +#define COEX_TX_REQ_COEX_TX_REASON_MSB 5 +#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x00000030 + +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000c +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 6 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 10 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c0 + +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000c +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 11 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 11 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x00000800 + +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000c +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 12 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 12 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x00001000 + +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000c +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 13 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 13 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x00002000 + +#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000c +#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 14 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 17 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c000 + +#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000c +#define COEX_TX_REQ_RESERVED_3A_LSB 18 +#define COEX_TX_REQ_RESERVED_3A_MSB 31 +#define COEX_TX_REQ_RESERVED_3A_MASK 0xfffc0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/coex_tx_status.h b/drivers/staging/fw-api/hw/peach/v1/coex_tx_status.h new file mode 100644 index 0000000000000000000000000000000000000000..7331ea9094b09b1b65e41adbb0da71272c3c8050 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/coex_tx_status.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _COEX_TX_STATUS_H_ +#define _COEX_TX_STATUS_H_ + +#define NUM_OF_DWORDS_COEX_TX_STATUS 3 + +struct coex_tx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 7, + tx_bw : 3, + tx_status_reason : 3, + tx_wait_ack : 1, + fes_tx_is_gen_frame : 1, + sch_tx_burst_ongoing : 1, + current_tx_duration : 16; + uint32_t next_rx_active_time : 16, + remaining_fes_time : 16; + uint32_t tx_antenna_mask : 8, + shared_ant_tx_pwr : 8, + other_ant_tx_pwr : 8, + reserved_2 : 8; +#else + uint32_t current_tx_duration : 16, + sch_tx_burst_ongoing : 1, + fes_tx_is_gen_frame : 1, + tx_wait_ack : 1, + tx_status_reason : 3, + tx_bw : 3, + reserved_0a : 7; + uint32_t remaining_fes_time : 16, + next_rx_active_time : 16; + uint32_t reserved_2 : 8, + other_ant_tx_pwr : 8, + shared_ant_tx_pwr : 8, + tx_antenna_mask : 8; +#endif +}; + +#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x00000000 +#define COEX_TX_STATUS_RESERVED_0A_LSB 0 +#define COEX_TX_STATUS_RESERVED_0A_MSB 6 +#define COEX_TX_STATUS_RESERVED_0A_MASK 0x0000007f + +#define COEX_TX_STATUS_TX_BW_OFFSET 0x00000000 +#define COEX_TX_STATUS_TX_BW_LSB 7 +#define COEX_TX_STATUS_TX_BW_MSB 9 +#define COEX_TX_STATUS_TX_BW_MASK 0x00000380 + +#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x00000000 +#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 +#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 +#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x00001c00 + +#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x00000000 +#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x00002000 + +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x00000000 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x00004000 + +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x00000000 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x00008000 + +#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x00000000 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0xffff0000 + +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x00000004 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 0 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 15 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff + +#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x00000004 +#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 16 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 31 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff0000 + +#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x00000008 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x000000ff + +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x00000008 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x0000ff00 + +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x00000008 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x00ff0000 + +#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x00000008 +#define COEX_TX_STATUS_RESERVED_2_LSB 24 +#define COEX_TX_STATUS_RESERVED_2_MSB 31 +#define COEX_TX_STATUS_RESERVED_2_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/com_dtypes.h b/drivers/staging/fw-api/hw/peach/v1/com_dtypes.h new file mode 100644 index 0000000000000000000000000000000000000000..dc2da8338fcf6b13936a6d86e03172a21764b239 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/com_dtypes.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef COM_DTYPES_H +#define COM_DTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef T_WINNT + #ifndef WIN32 + #define WIN32 + #endif + #include +#endif + +#ifdef TRUE +#undef TRUE +#endif + +#ifdef FALSE +#undef FALSE +#endif + +#define TRUE 1 +#define FALSE 0 + +#define ON 1 +#define OFF 0 + +#ifndef NULL + #define NULL 0 +#endif + +#ifndef _ARM_ASM_ +#ifndef _BOOLEAN_DEFINED + +typedef unsigned char boolean; +#define _BOOLEAN_DEFINED +#endif + +#if defined(DALSTDDEF_H) +#define _BOOLEAN_DEFINED +#define _UINT32_DEFINED +#define _UINT16_DEFINED +#define _UINT8_DEFINED +#define _INT32_DEFINED +#define _INT16_DEFINED +#define _INT8_DEFINED +#define _UINT64_DEFINED +#define _INT64_DEFINED +#define _BYTE_DEFINED +#endif + +#ifndef _UINT32_DEFINED + +typedef unsigned int uint32; +#define _UINT32_DEFINED +#endif + +#ifndef _UINT16_DEFINED + +typedef unsigned short uint16; +#define _UINT16_DEFINED +#endif + +#ifndef _UINT8_DEFINED + +typedef unsigned char uint8; +#define _UINT8_DEFINED +#endif + +#ifndef _INT32_DEFINED + +typedef signed int int32; +#define _INT32_DEFINED +#endif + +#ifndef _INT16_DEFINED + +typedef signed short int16; +#define _INT16_DEFINED +#endif + +#ifndef _INT8_DEFINED + +typedef signed char int8; +#define _INT8_DEFINED +#endif + +#ifndef _BYTE_DEFINED + +typedef unsigned char byte; +#define _BYTE_DEFINED +#endif + +typedef unsigned short word; + +typedef unsigned long dword; + +typedef unsigned char uint1; + +typedef unsigned short uint2; + +typedef unsigned long uint4; + +typedef signed char int1; + +typedef signed short int2; + +typedef long int int4; + +typedef signed long sint31; + +typedef signed short sint15; + +typedef signed char sint7; + +typedef uint16 UWord16 ; +typedef uint32 UWord32 ; +typedef int32 Word32 ; +typedef int16 Word16 ; +typedef uint8 UWord8 ; +typedef int8 Word8 ; +typedef int32 Vect32 ; + +#if (! defined T_WINNT) && (! defined __GNUC__) + + #ifndef _INT64_DEFINED + + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif +#else + + #if (defined __GNUC__) + #ifndef _INT64_DEFINED + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif + #else + typedef __int64 int64; + #ifndef _UINT64_DEFINED + typedef unsigned __int64 uint64; + #define _UINT64_DEFINED + #endif + #endif +#endif + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_mu_mimo_info.h new file mode 100644 index 0000000000000000000000000000000000000000..c83784ae4b62c3c3d639098671c2e685a5d13e71 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_mu_mimo_info.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ +#define _EHT_SIG_USR_MU_MIMO_INFO_H_ + +#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 + +struct eht_sig_usr_mu_mimo_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + sta_coding : 1, + sta_spatial_config : 6, + reserved_0a : 1, + rx_integrity_check_passed : 1, + subband80_cc_mask : 8; + uint32_t user_order_subband80_0 : 8, + user_order_subband80_1 : 8, + user_order_subband80_2 : 8, + user_order_subband80_3 : 8; +#else + uint32_t subband80_cc_mask : 8, + rx_integrity_check_passed : 1, + reserved_0a : 1, + sta_spatial_config : 6, + sta_coding : 1, + sta_mcs : 4, + sta_id : 11; + uint32_t user_order_subband80_3 : 8, + user_order_subband80_2 : 8, + user_order_subband80_1 : 8, + user_order_subband80_0 : 8; +#endif +}; + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 + +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 + +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_ofdma_info.h new file mode 100644 index 0000000000000000000000000000000000000000..8455629f5b273711d960ac7c1e3e5d795eca2668 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_ofdma_info.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ +#define _EHT_SIG_USR_OFDMA_INFO_H_ + +#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 + +struct eht_sig_usr_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + validate_0a : 1, + nss : 4, + txbf : 1, + sta_coding : 1, + reserved_0b : 1, + rx_integrity_check_passed : 1, + subband80_cc_mask : 8; + uint32_t user_order_subband80_0 : 8, + user_order_subband80_1 : 8, + user_order_subband80_2 : 8, + user_order_subband80_3 : 8; +#else + uint32_t subband80_cc_mask : 8, + rx_integrity_check_passed : 1, + reserved_0b : 1, + sta_coding : 1, + txbf : 1, + nss : 4, + validate_0a : 1, + sta_mcs : 4, + sta_id : 11; + uint32_t user_order_subband80_3 : 8, + user_order_subband80_2 : 8, + user_order_subband80_1 : 8, + user_order_subband80_0 : 8; +#endif +}; + +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 + +#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 + +#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 + +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 + +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 + +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_su_info.h new file mode 100644 index 0000000000000000000000000000000000000000..29127112fa5316dfdd4a027f482bc30c3be70291 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_su_info.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _EHT_SIG_USR_SU_INFO_H_ +#define _EHT_SIG_USR_SU_INFO_H_ + +#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 + +struct eht_sig_usr_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + validate_0a : 1, + nss : 4, + txbf : 1, + sta_coding : 1, + reserved_0b : 9, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0b : 9, + sta_coding : 1, + txbf : 1, + nss : 4, + validate_0a : 1, + sta_mcs : 4, + sta_id : 11; +#endif +}; + +#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 + +#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 +#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 +#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 + +#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 + +#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 + +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 + +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/expected_response.h b/drivers/staging/fw-api/hw/peach/v1/expected_response.h new file mode 100644 index 0000000000000000000000000000000000000000..fe18eca09123929d9752b8def91a3fdd7b645bf9 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/expected_response.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _EXPECTED_RESPONSE_H_ +#define _EXPECTED_RESPONSE_H_ + +#define NUM_OF_DWORDS_EXPECTED_RESPONSE 5 + +struct expected_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_ad2_31_0 : 32; + uint32_t tx_ad2_47_32 : 16, + expected_response_type : 5, + response_to_response : 3, + su_ba_user_number : 1, + response_info_part2_required : 1, + transmitted_bssid_check_en : 1, + reserved_1 : 5; + uint32_t ndp_sta_partial_aid_2_8_0 : 11, + reserved_2 : 10, + ndp_sta_partial_aid1_8_0 : 11; + uint32_t ast_index : 16, + capture_ack_ba_sounding : 1, + capture_sounding_1str_20mhz : 1, + capture_sounding_1str_40mhz : 1, + capture_sounding_1str_80mhz : 1, + capture_sounding_1str_160mhz : 1, + capture_sounding_1str_240mhz : 1, + capture_sounding_1str_320mhz : 1, + reserved_3a : 9; + uint32_t fcs : 9, + reserved_4a : 1, + crc : 4, + scrambler_seed : 7, + reserved_4b : 11; +#else + uint32_t tx_ad2_31_0 : 32; + uint32_t reserved_1 : 5, + transmitted_bssid_check_en : 1, + response_info_part2_required : 1, + su_ba_user_number : 1, + response_to_response : 3, + expected_response_type : 5, + tx_ad2_47_32 : 16; + uint32_t ndp_sta_partial_aid1_8_0 : 11, + reserved_2 : 10, + ndp_sta_partial_aid_2_8_0 : 11; + uint32_t reserved_3a : 9, + capture_sounding_1str_320mhz : 1, + capture_sounding_1str_240mhz : 1, + capture_sounding_1str_160mhz : 1, + capture_sounding_1str_80mhz : 1, + capture_sounding_1str_40mhz : 1, + capture_sounding_1str_20mhz : 1, + capture_ack_ba_sounding : 1, + ast_index : 16; + uint32_t reserved_4b : 11, + scrambler_seed : 7, + crc : 4, + reserved_4a : 1, + fcs : 9; +#endif +}; + +#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x00000000 +#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0xffffffff + +#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 0 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 15 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff + +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 16 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 20 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f0000 + +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 21 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 23 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e00000 + +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 24 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 24 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x01000000 + +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 25 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 25 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x02000000 + +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 26 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 26 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x04000000 + +#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_RESERVED_1_LSB 27 +#define EXPECTED_RESPONSE_RESERVED_1_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf8000000 + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x00000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x000007ff + +#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x00000008 +#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 +#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 +#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x001ff800 + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x00000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0xffe00000 + +#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_AST_INDEX_LSB 0 +#define EXPECTED_RESPONSE_AST_INDEX_MSB 15 +#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff + +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 16 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 16 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x00010000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 17 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 17 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x00020000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 18 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 18 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x00040000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 19 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 19 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x00080000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 20 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 20 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x00100000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 21 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 21 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x00200000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 22 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 22 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x00400000 + +#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_RESERVED_3A_LSB 23 +#define EXPECTED_RESPONSE_RESERVED_3A_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff800000 + +#define EXPECTED_RESPONSE_FCS_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_FCS_LSB 0 +#define EXPECTED_RESPONSE_FCS_MSB 8 +#define EXPECTED_RESPONSE_FCS_MASK 0x000001ff + +#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_RESERVED_4A_LSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x00000200 + +#define EXPECTED_RESPONSE_CRC_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_CRC_LSB 10 +#define EXPECTED_RESPONSE_CRC_MSB 13 +#define EXPECTED_RESPONSE_CRC_MASK 0x00003c00 + +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x001fc000 + +#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 +#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0xffe00000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_dl_info.h new file mode 100644 index 0000000000000000000000000000000000000000..6c5c1c293aa52eb97b694e0a2f108e038e5a88a5 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_dl_info.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_A_MU_DL_INFO_H_ +#define _HE_SIG_A_MU_DL_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 + +struct he_sig_a_mu_dl_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t dl_ul_flag : 1, + mcs_of_sig_b : 3, + dcm_of_sig_b : 1, + bss_color_id : 6, + spatial_reuse : 4, + transmit_bw : 3, + num_sig_b_symbols : 4, + comp_mode_sig_b : 1, + cp_ltf_size : 2, + doppler_indication : 1, + reserved_0a : 6; + uint32_t txop_duration : 7, + reserved_1a : 1, + num_ltf_symbols : 3, + ldpc_extra_symbol : 1, + stbc : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + crc : 4, + tail : 6, + reserved_1b : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0a : 6, + doppler_indication : 1, + cp_ltf_size : 2, + comp_mode_sig_b : 1, + num_sig_b_symbols : 4, + transmit_bw : 3, + spatial_reuse : 4, + bss_color_id : 6, + dcm_of_sig_b : 1, + mcs_of_sig_b : 3, + dl_ul_flag : 1; + uint32_t rx_integrity_check_passed : 1, + reserved_1b : 5, + tail : 6, + crc : 4, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + stbc : 1, + ldpc_extra_symbol : 1, + num_ltf_symbols : 3, + reserved_1a : 1, + txop_duration : 7; +#endif +}; + +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 + +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e + +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 + +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 + +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 + +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 + +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 + +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 + +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 + +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 + +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 + +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 +#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 +#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 +#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 +#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 + +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_ul_info.h new file mode 100644 index 0000000000000000000000000000000000000000..947a6f8e2cba46436bb6d5e94c8f7a5a182eab34 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_ul_info.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_A_MU_UL_INFO_H_ +#define _HE_SIG_A_MU_UL_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 + +struct he_sig_a_mu_ul_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t format_indication : 1, + bss_color_id : 6, + spatial_reuse : 16, + reserved_0a : 1, + transmit_bw : 2, + reserved_0b : 6; + uint32_t txop_duration : 7, + reserved_1a : 9, + crc : 4, + tail : 6, + reserved_1b : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0b : 6, + transmit_bw : 2, + reserved_0a : 1, + spatial_reuse : 16, + bss_color_id : 6, + format_indication : 1; + uint32_t rx_integrity_check_passed : 1, + reserved_1b : 5, + tail : 6, + crc : 4, + reserved_1a : 9, + txop_duration : 7; +#endif +}; + +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e + +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 + +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 + +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 + +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 + +#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 +#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 +#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 +#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 +#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 + +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/peach/v1/he_sig_a_su_info.h new file mode 100644 index 0000000000000000000000000000000000000000..c82cc61e966d5b4cfd8a6ea9439986c1583928a2 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/he_sig_a_su_info.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_A_SU_INFO_H_ +#define _HE_SIG_A_SU_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 + +struct he_sig_a_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t format_indication : 1, + beam_change : 1, + dl_ul_flag : 1, + transmit_mcs : 4, + dcm : 1, + bss_color_id : 6, + reserved_0a : 1, + spatial_reuse : 4, + transmit_bw : 2, + cp_ltf_size : 2, + nsts : 3, + reserved_0b : 6; + uint32_t txop_duration : 7, + coding : 1, + ldpc_extra_symbol : 1, + stbc : 1, + txbf : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + reserved_1a : 1, + doppler_indication : 1, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + dot11ax_ext_ru_size : 3, + rx_ndp : 1, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0b : 6, + nsts : 3, + cp_ltf_size : 2, + transmit_bw : 2, + spatial_reuse : 4, + reserved_0a : 1, + bss_color_id : 6, + dcm : 1, + transmit_mcs : 4, + dl_ul_flag : 1, + beam_change : 1, + format_indication : 1; + uint32_t rx_integrity_check_passed : 1, + rx_ndp : 1, + dot11ax_ext_ru_size : 3, + dot11ax_su_extended : 1, + tail : 6, + crc : 4, + doppler_indication : 1, + reserved_1a : 1, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + txbf : 1, + stbc : 1, + ldpc_extra_symbol : 1, + coding : 1, + txop_duration : 7; +#endif +}; + +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002 + +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004 + +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078 + +#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DCM_LSB 7 +#define HE_SIG_A_SU_INFO_DCM_MSB 7 +#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00 + +#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000 + +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000 + +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000 + +#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_NSTS_LSB 23 +#define HE_SIG_A_SU_INFO_NSTS_MSB 25 +#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000 + +#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CODING_LSB 7 +#define HE_SIG_A_SU_INFO_CODING_MSB 7 +#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_STBC_LSB 9 +#define HE_SIG_A_SU_INFO_STBC_MSB 9 +#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200 + +#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXBF_LSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400 + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000 + +#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CRC_LSB 16 +#define HE_SIG_A_SU_INFO_CRC_MSB 19 +#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000 + +#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TAIL_LSB 20 +#define HE_SIG_A_SU_INFO_TAIL_MSB 25 +#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 + +#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000 + +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/peach/v1/he_sig_b1_mu_info.h new file mode 100644 index 0000000000000000000000000000000000000000..2cb4633311a5d26746e5bead98967875576ba498 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/he_sig_b1_mu_info.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_B1_MU_INFO_H_ +#define _HE_SIG_B1_MU_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 + +struct he_sig_b1_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation : 8, + reserved_0 : 23, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0 : 23, + ru_allocation : 8; +#endif +}; + +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff + +#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 + +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/peach/v1/he_sig_b2_mu_info.h new file mode 100644 index 0000000000000000000000000000000000000000..8f198333aa7e6b0a55dc7ce6e8b9578b638e270d --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/he_sig_b2_mu_info.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_B2_MU_INFO_H_ +#define _HE_SIG_B2_MU_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2 + +struct he_sig_b2_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_spatial_config : 4, + sta_mcs : 4, + reserved_set_to_1 : 1, + sta_coding : 1, + reserved_0a : 7, + nsts : 3, + rx_integrity_check_passed : 1; + uint32_t user_order : 8, + cc_mask : 8, + reserved_1a : 16; +#else + uint32_t rx_integrity_check_passed : 1, + nsts : 3, + reserved_0a : 7, + sta_coding : 1, + reserved_set_to_1 : 1, + sta_mcs : 4, + sta_spatial_config : 4, + sta_id : 11; + uint32_t reserved_1a : 16, + cc_mask : 8, + user_order : 8; +#endif +}; + +#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000 + +#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000 + +#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_NSTS_LSB 28 +#define HE_SIG_B2_MU_INFO_NSTS_MSB 30 +#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000 + +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff + +#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00 + +#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/peach/v1/he_sig_b2_ofdma_info.h new file mode 100644 index 0000000000000000000000000000000000000000..9cb9d4228ebf57b1948c4e9943d7924ae669d7de --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/he_sig_b2_ofdma_info.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_B2_OFDMA_INFO_H_ +#define _HE_SIG_B2_OFDMA_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 + +struct he_sig_b2_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + nsts : 3, + txbf : 1, + sta_mcs : 4, + sta_dcm : 1, + sta_coding : 1, + reserved_0 : 10, + rx_integrity_check_passed : 1; + uint32_t user_order : 8, + cc_mask : 8, + reserved_1a : 16; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0 : 10, + sta_coding : 1, + sta_dcm : 1, + sta_mcs : 4, + txbf : 1, + nsts : 3, + sta_id : 11; + uint32_t reserved_1a : 16, + cc_mask : 8, + user_order : 8; +#endif +}; + +#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 + +#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 + +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 + +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 + +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff + +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/ht_sig_info.h b/drivers/staging/fw-api/hw/peach/v1/ht_sig_info.h new file mode 100644 index 0000000000000000000000000000000000000000..faf40148e6f45b0414778950cf97a53ad866c5f3 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/ht_sig_info.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HT_SIG_INFO_H_ +#define _HT_SIG_INFO_H_ + +#define NUM_OF_DWORDS_HT_SIG_INFO 2 + +struct ht_sig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mcs : 7, + cbw : 1, + length : 16, + reserved_0 : 8; + uint32_t smoothing : 1, + not_sounding : 1, + ht_reserved : 1, + aggregation : 1, + stbc : 2, + fec_coding : 1, + short_gi : 1, + num_ext_sp_str : 2, + crc : 8, + signal_tail : 6, + reserved_1 : 7, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0 : 8, + length : 16, + cbw : 1, + mcs : 7; + uint32_t rx_integrity_check_passed : 1, + reserved_1 : 7, + signal_tail : 6, + crc : 8, + num_ext_sp_str : 2, + short_gi : 1, + fec_coding : 1, + stbc : 2, + aggregation : 1, + ht_reserved : 1, + not_sounding : 1, + smoothing : 1; +#endif +}; + +#define HT_SIG_INFO_MCS_OFFSET 0x00000000 +#define HT_SIG_INFO_MCS_LSB 0 +#define HT_SIG_INFO_MCS_MSB 6 +#define HT_SIG_INFO_MCS_MASK 0x0000007f + +#define HT_SIG_INFO_CBW_OFFSET 0x00000000 +#define HT_SIG_INFO_CBW_LSB 7 +#define HT_SIG_INFO_CBW_MSB 7 +#define HT_SIG_INFO_CBW_MASK 0x00000080 + +#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000 +#define HT_SIG_INFO_LENGTH_LSB 8 +#define HT_SIG_INFO_LENGTH_MSB 23 +#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00 + +#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000 +#define HT_SIG_INFO_RESERVED_0_LSB 24 +#define HT_SIG_INFO_RESERVED_0_MSB 31 +#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000 + +#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004 +#define HT_SIG_INFO_SMOOTHING_LSB 0 +#define HT_SIG_INFO_SMOOTHING_MSB 0 +#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001 + +#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004 +#define HT_SIG_INFO_NOT_SOUNDING_LSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002 + +#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004 +#define HT_SIG_INFO_HT_RESERVED_LSB 2 +#define HT_SIG_INFO_HT_RESERVED_MSB 2 +#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004 + +#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004 +#define HT_SIG_INFO_AGGREGATION_LSB 3 +#define HT_SIG_INFO_AGGREGATION_MSB 3 +#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008 + +#define HT_SIG_INFO_STBC_OFFSET 0x00000004 +#define HT_SIG_INFO_STBC_LSB 4 +#define HT_SIG_INFO_STBC_MSB 5 +#define HT_SIG_INFO_STBC_MASK 0x00000030 + +#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004 +#define HT_SIG_INFO_FEC_CODING_LSB 6 +#define HT_SIG_INFO_FEC_CODING_MSB 6 +#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040 + +#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004 +#define HT_SIG_INFO_SHORT_GI_LSB 7 +#define HT_SIG_INFO_SHORT_GI_MSB 7 +#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080 + +#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300 + +#define HT_SIG_INFO_CRC_OFFSET 0x00000004 +#define HT_SIG_INFO_CRC_LSB 10 +#define HT_SIG_INFO_CRC_MSB 17 +#define HT_SIG_INFO_CRC_MASK 0x0003fc00 + +#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004 +#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18 +#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23 +#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000 + +#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004 +#define HT_SIG_INFO_RESERVED_1_LSB 24 +#define HT_SIG_INFO_RESERVED_1_MSB 30 +#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000 + +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/l_sig_a_info.h b/drivers/staging/fw-api/hw/peach/v1/l_sig_a_info.h new file mode 100644 index 0000000000000000000000000000000000000000..f6b1fbff5190ed72fe6216f9169cca3fdfc4fab9 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/l_sig_a_info.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _L_SIG_A_INFO_H_ +#define _L_SIG_A_INFO_H_ + +#define NUM_OF_DWORDS_L_SIG_A_INFO 1 + +struct l_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, + lsig_reserved : 1, + length : 12, + parity : 1, + tail : 6, + pkt_type : 4, + captured_implicit_sounding : 1, + reserved : 2, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved : 2, + captured_implicit_sounding : 1, + pkt_type : 4, + tail : 6, + parity : 1, + length : 12, + lsig_reserved : 1, + rate : 4; +#endif +}; + +#define L_SIG_A_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_A_INFO_RATE_LSB 0 +#define L_SIG_A_INFO_RATE_MSB 3 +#define L_SIG_A_INFO_RATE_MASK 0x0000000f + +#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010 + +#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_A_INFO_LENGTH_LSB 5 +#define L_SIG_A_INFO_LENGTH_MSB 16 +#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0 + +#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000 +#define L_SIG_A_INFO_PARITY_LSB 17 +#define L_SIG_A_INFO_PARITY_MSB 17 +#define L_SIG_A_INFO_PARITY_MASK 0x00020000 + +#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000 +#define L_SIG_A_INFO_TAIL_LSB 18 +#define L_SIG_A_INFO_TAIL_MSB 23 +#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000 + +#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000 +#define L_SIG_A_INFO_PKT_TYPE_LSB 24 +#define L_SIG_A_INFO_PKT_TYPE_MSB 27 +#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000 + +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RESERVED_LSB 29 +#define L_SIG_A_INFO_RESERVED_MSB 30 +#define L_SIG_A_INFO_RESERVED_MASK 0x60000000 + +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/l_sig_b_info.h b/drivers/staging/fw-api/hw/peach/v1/l_sig_b_info.h new file mode 100644 index 0000000000000000000000000000000000000000..c6f0f3a0cadc597bef8fe4c904cf4d96cda96ecd --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/l_sig_b_info.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _L_SIG_B_INFO_H_ +#define _L_SIG_B_INFO_H_ + +#define NUM_OF_DWORDS_L_SIG_B_INFO 1 + +struct l_sig_b_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, + length : 12, + reserved : 15, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved : 15, + length : 12, + rate : 4; +#endif +}; + +#define L_SIG_B_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_B_INFO_RATE_LSB 0 +#define L_SIG_B_INFO_RATE_MSB 3 +#define L_SIG_B_INFO_RATE_MASK 0x0000000f + +#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_B_INFO_LENGTH_LSB 4 +#define L_SIG_B_INFO_LENGTH_MSB 15 +#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0 + +#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RESERVED_LSB 16 +#define L_SIG_B_INFO_RESERVED_MSB 30 +#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000 + +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/peach/v1/macrx_abort_request_info.h new file mode 100644 index 0000000000000000000000000000000000000000..197f4e5d41ee16a6524c4936424f4a774600f71b --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/macrx_abort_request_info.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACRX_ABORT_REQUEST_INFO_H_ +#define _MACRX_ABORT_REQUEST_INFO_H_ + +#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 + +struct macrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t macrx_abort_reason : 8, + reserved_0 : 8; +#else + uint16_t reserved_0 : 8, + macrx_abort_reason : 8; +#endif +}; + +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff + +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h new file mode 100644 index 0000000000000000000000000000000000000000..c9c7f41822f90fda733c92fc671cf70c3ef2a503 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ +#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ + +#include "eht_sig_usr_mu_mimo_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 + +struct mactx_eht_sig_usr_mu_mimo { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#else + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x00007800 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x00008000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x003f0000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x00400000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 0 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 7 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 8 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 16 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 24 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 31 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_ofdma.h new file mode 100644 index 0000000000000000000000000000000000000000..98d98d500a9f020264feff17f615d81b335ecbe2 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_ofdma.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ +#define _MACTX_EHT_SIG_USR_OFDMA_H_ + +#include "eht_sig_usr_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 + +struct mactx_eht_sig_usr_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#else + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00007800 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x00008000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x000f0000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x00100000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00200000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x00400000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 0 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 7 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 8 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 16 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 24 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 31 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_su.h new file mode 100644 index 0000000000000000000000000000000000000000..aaef05617272e69fd5f98ce299f8140ef983c120 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_su.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_EHT_SIG_USR_SU_H_ +#define _MACTX_EHT_SIG_USR_SU_H_ + +#include "eht_sig_usr_su_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 1 + +struct mactx_eht_sig_usr_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; +#else + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x00007800 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x00008000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x000f0000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x00100000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x00200000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x7fc00000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_dl.h new file mode 100644 index 0000000000000000000000000000000000000000..19db380bb47383a0862acbcc92a4ee84ae41959b --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_dl.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_A_MU_DL_H_ +#define _MACTX_HE_SIG_A_MU_DL_H_ + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 + +struct mactx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 7 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 10 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 12 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 14 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 19 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 30 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_ul.h new file mode 100644 index 0000000000000000000000000000000000000000..ddc528393428d51ce6336b89eced98190bad8bf4 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_ul.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_A_MU_UL_H_ +#define _MACTX_HE_SIG_A_MU_UL_H_ + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 + +struct mactx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 15 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 19 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 30 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_su.h new file mode 100644 index 0000000000000000000000000000000000000000..449e9bc875c47c2c48b988877cae579778e5df10 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_su.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_A_SU_H_ +#define _MACTX_HE_SIG_A_SU_H_ + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 + +struct mactx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 9 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 10 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 12 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 19 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 29 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 30 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 30 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x40000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b1_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..177d7666b6414aaad4ae122c165576ba8a086318 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b1_mu.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_B1_MU_H_ +#define _MACTX_HE_SIG_B1_MU_H_ + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 1 + +struct mactx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; +#else + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; +#endif +}; + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x7fffff00 + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..6439af73ecb2e6ec7f947cfd70feb5219fc769ad --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_mu.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_B2_MU_H_ +#define _MACTX_HE_SIG_B2_MU_H_ + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 + +struct mactx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#endif +}; + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x0fe00000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x70000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 0 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 7 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 8 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 15 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff00 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 16 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_ofdma.h new file mode 100644 index 0000000000000000000000000000000000000000..b1563803a0ecaac5c3e0ca678811982a84c39719 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_ofdma.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ +#define _MACTX_HE_SIG_B2_OFDMA_H_ + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 + +struct mactx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#endif +}; + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x7fe00000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 0 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 7 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 8 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 15 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff00 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 16 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_ht_sig.h b/drivers/staging/fw-api/hw/peach/v1/mactx_ht_sig.h new file mode 100644 index 0000000000000000000000000000000000000000..96f653ce831ac2f4512b3738251640012c03e871 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_ht_sig.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HT_SIG_H_ +#define _MACTX_HT_SIG_H_ + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_MACTX_HT_SIG 2 + +struct mactx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info mactx_ht_sig_info_details; +#else + struct ht_sig_info mactx_ht_sig_info_details; +#endif +}; + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 1 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 2 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 3 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 4 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 5 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 9 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 10 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 17 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 23 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 30 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_a.h new file mode 100644 index 0000000000000000000000000000000000000000..5ba28f73ec8c54031ec3763ee1d77bce9e83ffa1 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_a.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_L_SIG_A_H_ +#define _MACTX_L_SIG_A_H_ + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_A 1 + +struct mactx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info mactx_l_sig_a_info_details; +#else + struct l_sig_a_info mactx_l_sig_a_info_details; +#endif +}; + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x60000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_b.h new file mode 100644 index 0000000000000000000000000000000000000000..4e05a7b71b19095acbfe5ac9e7e1d4e66f724884 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_b.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_L_SIG_B_H_ +#define _MACTX_L_SIG_B_H_ + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_B 1 + +struct mactx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info mactx_l_sig_b_info_details; +#else + struct l_sig_b_info mactx_l_sig_b_info_details; +#endif +}; + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0 + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x7fff0000 + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_phy_desc.h b/drivers/staging/fw-api/hw/peach/v1/mactx_phy_desc.h new file mode 100644 index 0000000000000000000000000000000000000000..a7f61e8108d71820026a1838f594da4f0e139fb4 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_phy_desc.h @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_PHY_DESC_H_ +#define _MACTX_PHY_DESC_H_ + +#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 + +struct mactx_phy_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 16, + bf_type : 2, + wait_sifs : 2, + dot11b_preamble_type : 1, + pkt_type : 4, + su_or_mu : 2, + mu_type : 1, + bandwidth : 3, + channel_capture : 1; + uint32_t mcs : 4, + global_ofdma_mimo_enable : 1, + reserved_1a : 1, + stbc : 1, + dot11ax_su_extended : 1, + dot11ax_trigger_frame_embedded : 1, + tx_pwr_shared : 8, + tx_pwr_unshared : 8, + measure_power : 1, + tpc_glut_self_cal : 1, + back_to_back_transmission_expected : 1, + heavy_clip_nss : 3, + txbf_per_packet_no_csd_no_walsh : 1; + uint32_t ndp : 2, + ul_flag : 1, + triggered : 1, + ap_pkt_bw : 3, + ru_position_start : 8, + pcu_ppdu_setup_start_reason : 3, + tlv_source : 1, + reserved_2a : 2, + nss : 3, + stream_offset : 3, + reserved_2b : 2, + clpc_enable : 1, + mu_ndp : 1, + response_expected : 1; + uint32_t rx_chain_mask : 8, + rx_chain_mask_valid : 1, + ant_sel_valid : 1, + ant_sel : 1, + cp_setting : 2, + he_ppdu_subtype : 2, + active_channel : 3, + generate_phyrx_tx_start_timing : 1, + ltf_size : 2, + ru_size_updated_v2 : 4, + reserved_3c : 1, + u_sig_puncture_pattern_encoding : 6; +#else + uint32_t channel_capture : 1, + bandwidth : 3, + mu_type : 1, + su_or_mu : 2, + pkt_type : 4, + dot11b_preamble_type : 1, + wait_sifs : 2, + bf_type : 2, + reserved_0a : 16; + uint32_t txbf_per_packet_no_csd_no_walsh : 1, + heavy_clip_nss : 3, + back_to_back_transmission_expected : 1, + tpc_glut_self_cal : 1, + measure_power : 1, + tx_pwr_unshared : 8, + tx_pwr_shared : 8, + dot11ax_trigger_frame_embedded : 1, + dot11ax_su_extended : 1, + stbc : 1, + reserved_1a : 1, + global_ofdma_mimo_enable : 1, + mcs : 4; + uint32_t response_expected : 1, + mu_ndp : 1, + clpc_enable : 1, + reserved_2b : 2, + stream_offset : 3, + nss : 3, + reserved_2a : 2, + tlv_source : 1, + pcu_ppdu_setup_start_reason : 3, + ru_position_start : 8, + ap_pkt_bw : 3, + triggered : 1, + ul_flag : 1, + ndp : 2; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_3c : 1, + ru_size_updated_v2 : 4, + ltf_size : 2, + generate_phyrx_tx_start_timing : 1, + active_channel : 3, + he_ppdu_subtype : 2, + cp_setting : 2, + ant_sel : 1, + ant_sel_valid : 1, + rx_chain_mask_valid : 1, + rx_chain_mask : 8; +#endif +}; + +#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 +#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 +#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x0000ffff + +#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_BF_TYPE_LSB 16 +#define MACTX_PHY_DESC_BF_TYPE_MSB 17 +#define MACTX_PHY_DESC_BF_TYPE_MASK 0x00030000 + +#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x00000000 +#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 +#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 +#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x000c0000 + +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x00100000 + +#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 +#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 +#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x01e00000 + +#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x00000000 +#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 +#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 +#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x06000000 + +#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_MU_TYPE_LSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MASK 0x08000000 + +#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x00000000 +#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 +#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 +#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x70000000 + +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x80000000 + +#define MACTX_PHY_DESC_MCS_OFFSET 0x00000004 +#define MACTX_PHY_DESC_MCS_LSB 0 +#define MACTX_PHY_DESC_MCS_MSB 3 +#define MACTX_PHY_DESC_MCS_MASK 0x0000000f + +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x00000004 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 4 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 4 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x00000010 + +#define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_PHY_DESC_RESERVED_1A_LSB 5 +#define MACTX_PHY_DESC_RESERVED_1A_MSB 5 +#define MACTX_PHY_DESC_RESERVED_1A_MASK 0x00000020 + +#define MACTX_PHY_DESC_STBC_OFFSET 0x00000004 +#define MACTX_PHY_DESC_STBC_LSB 6 +#define MACTX_PHY_DESC_STBC_MSB 6 +#define MACTX_PHY_DESC_STBC_MASK 0x00000040 + +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 7 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 7 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x00000080 + +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 8 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 8 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x00000100 + +#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 9 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 16 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe00 + +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 17 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 24 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe0000 + +#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x00000004 +#define MACTX_PHY_DESC_MEASURE_POWER_LSB 25 +#define MACTX_PHY_DESC_MEASURE_POWER_MSB 25 +#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x02000000 + +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x00000004 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 26 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 26 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x04000000 + +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 27 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 27 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x08000000 + +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x00000004 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 28 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 30 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x70000000 + +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x00000004 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 31 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 31 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x80000000 + +#define MACTX_PHY_DESC_NDP_OFFSET 0x00000008 +#define MACTX_PHY_DESC_NDP_LSB 0 +#define MACTX_PHY_DESC_NDP_MSB 1 +#define MACTX_PHY_DESC_NDP_MASK 0x00000003 + +#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x00000008 +#define MACTX_PHY_DESC_UL_FLAG_LSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MASK 0x00000004 + +#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x00000008 +#define MACTX_PHY_DESC_TRIGGERED_LSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MASK 0x00000008 + +#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x00000008 +#define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 +#define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 +#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000070 + +#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x00000008 +#define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 +#define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 +#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x00007f80 + +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x00000008 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x00038000 + +#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x00000008 +#define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x00040000 + +#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x00000008 +#define MACTX_PHY_DESC_RESERVED_2A_LSB 19 +#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 +#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x00180000 + +#define MACTX_PHY_DESC_NSS_OFFSET 0x00000008 +#define MACTX_PHY_DESC_NSS_LSB 21 +#define MACTX_PHY_DESC_NSS_MSB 23 +#define MACTX_PHY_DESC_NSS_MASK 0x00e00000 + +#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x00000008 +#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 +#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 +#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x07000000 + +#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x00000008 +#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 +#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 +#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x18000000 + +#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x00000008 +#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x20000000 + +#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x00000008 +#define MACTX_PHY_DESC_MU_NDP_LSB 30 +#define MACTX_PHY_DESC_MU_NDP_MSB 30 +#define MACTX_PHY_DESC_MU_NDP_MASK 0x40000000 + +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x00000008 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x80000000 + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000c +#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 0 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 7 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000c +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 8 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 8 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x00000100 + +#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000c +#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 9 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 9 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x00000200 + +#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000c +#define MACTX_PHY_DESC_ANT_SEL_LSB 10 +#define MACTX_PHY_DESC_ANT_SEL_MSB 10 +#define MACTX_PHY_DESC_ANT_SEL_MASK 0x00000400 + +#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000c +#define MACTX_PHY_DESC_CP_SETTING_LSB 11 +#define MACTX_PHY_DESC_CP_SETTING_MSB 12 +#define MACTX_PHY_DESC_CP_SETTING_MASK 0x00001800 + +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000c +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 13 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 14 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x00006000 + +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000c +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 15 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 17 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x00038000 + +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000c +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 18 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 18 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x00040000 + +#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000c +#define MACTX_PHY_DESC_LTF_SIZE_LSB 19 +#define MACTX_PHY_DESC_LTF_SIZE_MSB 20 +#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x00180000 + +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000c +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 21 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 24 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e00000 + +#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000c +#define MACTX_PHY_DESC_RESERVED_3C_LSB 25 +#define MACTX_PHY_DESC_RESERVED_3C_MSB 25 +#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x02000000 + +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000c +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_su_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..6ccc7d2e25485e250e8af493a0cd86023e7dc3e2 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_su_mu.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ +#define _MACTX_U_SIG_EHT_SU_MU_H_ + +#include "u_sig_eht_su_mu_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 + +struct mactx_u_sig_eht_su_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#else + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#endif +}; + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x00000007 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00000038 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000040 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00001f80 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x000fe000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x01f00000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x02000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0xfc000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 2 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 2 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x00000004 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 3 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 7 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 8 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 8 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x00000100 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 9 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 10 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x00000600 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 11 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 15 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 16 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 19 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 27 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 29 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x38000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 30 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 30 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x40000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_tb.h new file mode 100644 index 0000000000000000000000000000000000000000..a305e5640a0d74209cdcc422b930b6f28d534292 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_tb.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_U_SIG_EHT_TB_H_ +#define _MACTX_U_SIG_EHT_TB_H_ + +#include "u_sig_eht_tb_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 + +struct mactx_u_sig_eht_tb { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#else + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#endif +}; + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x00000007 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x00000038 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000040 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00001f80 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x000fe000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x03f00000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0xfc000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x00000004 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 3 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 10 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f8 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 11 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 15 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f800 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 16 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 19 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 26 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 30 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_common.h new file mode 100644 index 0000000000000000000000000000000000000000..6ccbfc2e57fe305f7d5c3914c2bac5896405f4ca --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_common.h @@ -0,0 +1,478 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_USER_DESC_COMMON_H_ +#define _MACTX_USER_DESC_COMMON_H_ + +#include "unallocated_ru_160_info.h" +#include "ru_allocation_160_info.h" +#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 + +struct mactx_user_desc_common { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, + reserved_0b : 5, + ltf_size : 2, + reserved_0c : 3, + he_stf_long : 1, + reserved_0d : 7, + num_users_he_sigb_band0 : 8; + uint32_t num_ltf_symbols : 3, + reserved_1a : 5, + num_users_he_sigb_band1 : 8, + reserved_1b : 16; + uint32_t packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + packet_extension : 3, + reserved : 2, + he_sigb_dcm : 1, + reserved_2b : 7, + he_sigb_compression : 1, + reserved_2c : 15; + uint32_t he_sigb_0_mcs : 3, + reserved_3a : 13, + num_he_sigb_sym : 5, + center_ru_0 : 1, + center_ru_1 : 1, + reserved_3b : 1, + ftm_en : 1, + pe_nss : 3, + pe_ltf_size : 2, + pe_content : 1, + pe_chain_csd_en : 1; + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t num_data_symbols : 16, + ndp_ru_tone_set_index : 7, + ndp_feedback_status : 1, + doppler_indication : 1, + reserved_14a : 7; + uint32_t spatial_reuse : 16, + reserved_15a : 16; +#else + uint32_t num_users_he_sigb_band0 : 8, + reserved_0d : 7, + he_stf_long : 1, + reserved_0c : 3, + ltf_size : 2, + reserved_0b : 5, + num_users : 6; + uint32_t reserved_1b : 16, + num_users_he_sigb_band1 : 8, + reserved_1a : 5, + num_ltf_symbols : 3; + uint32_t reserved_2c : 15, + he_sigb_compression : 1, + reserved_2b : 7, + he_sigb_dcm : 1, + reserved : 2, + packet_extension : 3, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2; + uint32_t pe_chain_csd_en : 1, + pe_content : 1, + pe_ltf_size : 2, + pe_nss : 3, + ftm_en : 1, + reserved_3b : 1, + center_ru_1 : 1, + center_ru_0 : 1, + num_he_sigb_sym : 5, + reserved_3a : 13, + he_sigb_0_mcs : 3; + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t reserved_14a : 7, + doppler_indication : 1, + ndp_feedback_status : 1, + ndp_ru_tone_set_index : 7, + num_data_symbols : 16; + uint32_t reserved_15a : 16, + spatial_reuse : 16; +#endif +}; + +#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x0000003f + +#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x000007c0 + +#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x00001800 + +#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x0000e000 + +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x00010000 + +#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x00fe0000 + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0xff000000 + +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 2 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x00000007 + +#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 3 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 7 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f8 + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x00000004 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 8 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 15 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff00 + +#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x00000004 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 16 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff0000 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x00000003 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000004 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x00000038 + +#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 +#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x000000c0 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x00000100 + +#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x0000fe00 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x00010000 + +#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0xfffe0000 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 0 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 2 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x00000007 + +#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 3 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff8 + +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 16 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 20 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f0000 + +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 21 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 21 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x00200000 + +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 22 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 22 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x00400000 + +#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x00800000 + +#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 24 +#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 24 +#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x01000000 + +#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 25 +#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 27 +#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e000000 + +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 28 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 29 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x30000000 + +#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 30 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 30 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x40000000 + +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 31 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 31 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x80000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x00fc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000014 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000014 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x00000014 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x00000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000001c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000001c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000001c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x00fc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000024 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000024 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x00000024 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x00000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000002c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000002c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000002c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x00000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x00000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x00000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x00000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0xff000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x00000034 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 7 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x00000034 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 15 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x00000034 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 16 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x00000034 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff000000 + +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x0000ffff + +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x007f0000 + +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x00800000 + +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x01000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0xfe000000 + +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000003c +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 0 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 15 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff + +#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000003c +#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 16 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_per_user.h new file mode 100644 index 0000000000000000000000000000000000000000..7e70429874b080c8e5bb4efa68daa5d23e57e553 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_per_user.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_USER_DESC_PER_USER_H_ +#define _MACTX_USER_DESC_PER_USER_H_ + +#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4 + +struct mactx_user_desc_per_user { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t psdu_length : 24, + reserved_0a : 8; + uint32_t ru_start_index : 8, + ru_size : 4, + reserved_1b : 4, + ofdma_mu_mimo_enabled : 1, + nss : 3, + stream_offset : 3, + reserved_1c : 1, + mcs : 4, + dcm : 1, + reserved_1d : 3; + uint32_t fec_type : 1, + reserved_2a : 7, + user_bf_type : 2, + reserved_2b : 6, + drop_user_cbf : 1, + reserved_2c : 7, + ldpc_extra_symbol : 1, + force_extra_symbol : 1, + reserved_2d : 6; + uint32_t sw_peer_id : 16, + per_user_subband_mask : 16; +#else + uint32_t reserved_0a : 8, + psdu_length : 24; + uint32_t reserved_1d : 3, + dcm : 1, + mcs : 4, + reserved_1c : 1, + stream_offset : 3, + nss : 3, + ofdma_mu_mimo_enabled : 1, + reserved_1b : 4, + ru_size : 4, + ru_start_index : 8; + uint32_t reserved_2d : 6, + force_extra_symbol : 1, + ldpc_extra_symbol : 1, + reserved_2c : 7, + drop_user_cbf : 1, + reserved_2b : 6, + user_bf_type : 2, + reserved_2a : 7, + fec_type : 1; + uint32_t per_user_subband_mask : 16, + sw_peer_id : 16; +#endif +}; + +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x00000000 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x00ffffff + +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0xff000000 + +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 0 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 7 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff + +#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 8 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 11 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f00 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 12 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 15 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f000 + +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 16 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 16 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x00010000 + +#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_NSS_LSB 17 +#define MACTX_USER_DESC_PER_USER_NSS_MSB 19 +#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e0000 + +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 20 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 22 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x00700000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x00800000 + +#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_MCS_LSB 24 +#define MACTX_USER_DESC_PER_USER_MCS_MSB 27 +#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f000000 + +#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_DCM_LSB 28 +#define MACTX_USER_DESC_PER_USER_DCM_MSB 28 +#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x10000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 29 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe0000000 + +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x00000001 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x000000fe + +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x00000300 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x0000fc00 + +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x00010000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x00fe0000 + +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x01000000 + +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x02000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0xfc000000 + +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000c +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 0 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 15 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff + +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000c +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 16 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 31 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_a.h new file mode 100644 index 0000000000000000000000000000000000000000..3252a84ea556520f2563d26e904fbdc7d86adeea --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_a.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_A_H_ +#define _MACTX_VHT_SIG_A_H_ + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 + +struct mactx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#else + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#endif +}; + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 1 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 7 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 8 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 17 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 30 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu160.h new file mode 100644 index 0000000000000000000000000000000000000000..b26ede5f8f3b18b69ae236ac743ebd9009deffec --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu160.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_MU160_H_ +#define _MACTX_VHT_SIG_B_MU160_H_ + +#include "vht_sig_b_mu160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 + +struct mactx_vht_sig_b_mu160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#else + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu20.h new file mode 100644 index 0000000000000000000000000000000000000000..994a1ae4c235bfbf9e885bb1915a9ca035c1ec0e --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu20.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_MU20_H_ +#define _MACTX_VHT_SIG_B_MU20_H_ + +#include "vht_sig_b_mu20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 1 + +struct mactx_vht_sig_b_mu20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; +#else + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x0000ffff + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x000f0000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x1c000000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu40.h new file mode 100644 index 0000000000000000000000000000000000000000..bdbe562d6ad97a53dcf9aae32020e2db6c458610 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu40.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_MU40_H_ +#define _MACTX_VHT_SIG_B_MU40_H_ + +#include "vht_sig_b_mu40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 + +struct mactx_vht_sig_b_mu40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#else + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x0001ffff + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x001e0000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x07e00000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x18000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 0 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 16 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 17 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 20 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e0000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 21 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 26 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e00000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 27 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 31 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf8000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu80.h new file mode 100644 index 0000000000000000000000000000000000000000..e150bf89b643f4f7b720ed531dfc08450e758516 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu80.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_MU80_H_ +#define _MACTX_VHT_SIG_B_MU80_H_ + +#include "vht_sig_b_mu80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 + +struct mactx_vht_sig_b_mu80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#else + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su160.h new file mode 100644 index 0000000000000000000000000000000000000000..edde887c102b008e5f14f89ac05f82e9985bdaaa --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su160.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_SU160_H_ +#define _MACTX_VHT_SIG_B_SU160_H_ + +#include "vht_sig_b_su160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 + +struct mactx_vht_sig_b_su160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#else + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su20.h new file mode 100644 index 0000000000000000000000000000000000000000..3543c7f7057502200dcf80f0db9593771dc3e8f5 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su20.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_SU20_H_ +#define _MACTX_VHT_SIG_B_SU20_H_ + +#include "vht_sig_b_su20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 1 + +struct mactx_vht_sig_b_su20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; +#else + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x0001ffff + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x000e0000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x7c000000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su40.h new file mode 100644 index 0000000000000000000000000000000000000000..f9136e2a6c2168d7766d92ccc8415c81861ef0cf --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su40.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_SU40_H_ +#define _MACTX_VHT_SIG_B_SU40_H_ + +#include "vht_sig_b_su40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 + +struct mactx_vht_sig_b_su40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#else + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x00180000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x07e00000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x78000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 0 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 18 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 19 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 20 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x00180000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 21 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 26 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e00000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 27 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 30 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x78000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su80.h new file mode 100644 index 0000000000000000000000000000000000000000..881918cbb8657aa1f93a82632a7f829147d06deb --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su80.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_SU80_H_ +#define _MACTX_VHT_SIG_B_SU80_H_ + +#include "vht_sig_b_su80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 + +struct mactx_vht_sig_b_su80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#else + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/peach/v1/mlo_sta_id_details.h new file mode 100644 index 0000000000000000000000000000000000000000..50448cc4e075984b568ae4bf06f78a85f6c365a8 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mlo_sta_id_details.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MLO_STA_ID_DETAILS_H_ +#define _MLO_STA_ID_DETAILS_H_ + +#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 + +struct mlo_sta_id_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t nstr_mlo_sta_id : 10, + block_self_ml_sync : 1, + block_partner_ml_sync : 1, + nstr_mlo_sta_id_valid : 1, + reserved_0a : 3; +#else + uint16_t reserved_0a : 3, + nstr_mlo_sta_id_valid : 1, + block_partner_ml_sync : 1, + block_self_ml_sync : 1, + nstr_mlo_sta_id : 10; +#endif +}; + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mon_buffer_addr.h b/drivers/staging/fw-api/hw/peach/v1/mon_buffer_addr.h new file mode 100644 index 0000000000000000000000000000000000000000..7c3c60a57d8f768c61f7f28de0c03b801d78198b --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mon_buffer_addr.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MON_BUFFER_ADDR_H_ +#define _MON_BUFFER_ADDR_H_ + +#define NUM_OF_DWORDS_MON_BUFFER_ADDR 3 + +struct mon_buffer_addr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t dma_length : 12, + reserved_2a : 4, + msdu_continuation : 1, + truncated : 1, + reserved_2b : 14; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reserved_2b : 14, + truncated : 1, + msdu_continuation : 1, + reserved_2a : 4, + dma_length : 12; +#endif +}; + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 +#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 +#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x00000fff + +#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 +#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 +#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x0000f000 + +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x00010000 + +#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x00020000 + +#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 +#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 +#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0xfffc0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mon_destination_ring.h b/drivers/staging/fw-api/hw/peach/v1/mon_destination_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..e1feca4d70fd83b6041eef5ab995a7d381e239b3 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mon_destination_ring.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MON_DESTINATION_RING_H_ +#define _MON_DESTINATION_RING_H_ + +#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 + +struct mon_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t stat_buf_virt_addr_31_0 : 32; + uint32_t stat_buf_virt_addr_63_32 : 32; + uint32_t ppdu_id : 32; + uint32_t end_offset : 12, + reserved_3a : 2, + link_info : 2, + end_reason : 2, + initiator : 1, + empty_descriptor : 1, + ring_id : 8, + looping_count : 4; +#else + uint32_t stat_buf_virt_addr_31_0 : 32; + uint32_t stat_buf_virt_addr_63_32 : 32; + uint32_t ppdu_id : 32; + uint32_t looping_count : 4, + ring_id : 8, + empty_descriptor : 1, + initiator : 1, + end_reason : 2, + link_info : 2, + reserved_3a : 2, + end_offset : 12; +#endif +}; + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff + +#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 +#define MON_DESTINATION_RING_PPDU_ID_LSB 0 +#define MON_DESTINATION_RING_PPDU_ID_MSB 31 +#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff + +#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_OFFSET_LSB 0 +#define MON_DESTINATION_RING_END_OFFSET_MSB 11 +#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff + +#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 +#define MON_DESTINATION_RING_RESERVED_3A_MSB 13 +#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x00003000 + +#define MON_DESTINATION_RING_LINK_INFO_OFFSET 0x0000000c +#define MON_DESTINATION_RING_LINK_INFO_LSB 14 +#define MON_DESTINATION_RING_LINK_INFO_MSB 15 +#define MON_DESTINATION_RING_LINK_INFO_MASK 0x0000c000 + +#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_REASON_LSB 16 +#define MON_DESTINATION_RING_END_REASON_MSB 17 +#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 + +#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_INITIATOR_LSB 18 +#define MON_DESTINATION_RING_INITIATOR_MSB 18 +#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 + +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 + +#define MON_DESTINATION_RING_RING_ID_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RING_ID_LSB 20 +#define MON_DESTINATION_RING_RING_ID_MSB 27 +#define MON_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + +#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c +#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mon_drop.h b/drivers/staging/fw-api/hw/peach/v1/mon_drop.h new file mode 100644 index 0000000000000000000000000000000000000000..99d782f9f5850b6c22cd424dfe9e71d418cb9b59 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mon_drop.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MON_DROP_H_ +#define _MON_DROP_H_ + +#define NUM_OF_DWORDS_MON_DROP 2 + +struct mon_drop { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_id : 32; + uint32_t ppdu_drop_cnt : 10, + mpdu_drop_cnt : 10, + tlv_drop_cnt : 10, + end_of_ppdu_seen : 1, + reserved_1a : 1; +#else + uint32_t ppdu_id : 32; + uint32_t reserved_1a : 1, + end_of_ppdu_seen : 1, + tlv_drop_cnt : 10, + mpdu_drop_cnt : 10, + ppdu_drop_cnt : 10; +#endif +}; + +#define MON_DROP_PPDU_ID_OFFSET 0x00000000 +#define MON_DROP_PPDU_ID_LSB 0 +#define MON_DROP_PPDU_ID_MSB 31 +#define MON_DROP_PPDU_ID_MASK 0xffffffff + +#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x00000004 +#define MON_DROP_PPDU_DROP_CNT_LSB 0 +#define MON_DROP_PPDU_DROP_CNT_MSB 9 +#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff + +#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x00000004 +#define MON_DROP_MPDU_DROP_CNT_LSB 10 +#define MON_DROP_MPDU_DROP_CNT_MSB 19 +#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc00 + +#define MON_DROP_TLV_DROP_CNT_OFFSET 0x00000004 +#define MON_DROP_TLV_DROP_CNT_LSB 20 +#define MON_DROP_TLV_DROP_CNT_MSB 29 +#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff00000 + +#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x00000004 +#define MON_DROP_END_OF_PPDU_SEEN_LSB 30 +#define MON_DROP_END_OF_PPDU_SEEN_MSB 30 +#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x40000000 + +#define MON_DROP_RESERVED_1A_OFFSET 0x00000004 +#define MON_DROP_RESERVED_1A_LSB 31 +#define MON_DROP_RESERVED_1A_MSB 31 +#define MON_DROP_RESERVED_1A_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/mon_ingress_ring.h b/drivers/staging/fw-api/hw/peach/v1/mon_ingress_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..f284a530bb58abccf70bcfc859ce04df9192ce84 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/mon_ingress_ring.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MON_INGRESS_RING_H_ +#define _MON_INGRESS_RING_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_MON_INGRESS_RING 4 + +struct mon_ingress_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; +#else + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; +#endif +}; + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/msmhwiobase.h b/drivers/staging/fw-api/hw/peach/v1/msmhwiobase.h new file mode 100644 index 0000000000000000000000000000000000000000..a251141f304a17491b6d3adf75db22dffe889271 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/msmhwiobase.h @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __MSMHWIOBASE_H__ +#define __MSMHWIOBASE_H__ + +#define WCSS_WCSS_BASE 0x00000000 +#define WCSS_WCSS_BASE_SIZE 0x01000000 +#define WCSS_WCSS_BASE_PHYS 0x00000000 + +#define QDSS_STM_SIZE_BASE 0x00100000 +#define QDSS_STM_SIZE_BASE_SIZE 0x100000000 +#define QDSS_STM_SIZE_BASE_PHYS 0x00100000 + +#define BOOT_ROM_SIZE_BASE 0x00200000 +#define BOOT_ROM_SIZE_BASE_SIZE 0x100000000 +#define BOOT_ROM_SIZE_BASE_PHYS 0x00200000 + +#define SYSTEM_IRAM_SIZE_BASE 0x00400000 +#define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000 +#define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000 + +#define BOOT_ROM_START_ADDRESS_BASE 0x01200000 +#define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000 +#define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x01200000 + +#define BOOT_ROM_END_ADDRESS_BASE 0x013fffff +#define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000 +#define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x013fffff + +#define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000 +#define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000 +#define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000 + +#define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff +#define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000 +#define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff + +#define QDSS_STM_BASE 0x01800000 +#define QDSS_STM_BASE_SIZE 0x100000000 +#define QDSS_STM_BASE_PHYS 0x01800000 + +#define QDSS_STM_END_BASE 0x018fffff +#define QDSS_STM_END_BASE_SIZE 0x100000000 +#define QDSS_STM_END_BASE_PHYS 0x018fffff + +#define TLMM_BASE 0x01900000 +#define TLMM_BASE_SIZE 0x00200000 +#define TLMM_BASE_PHYS 0x01900000 + +#define CORE_TOP_CSR_BASE 0x01b00000 +#define CORE_TOP_CSR_BASE_SIZE 0x00040000 +#define CORE_TOP_CSR_BASE_PHYS 0x01b00000 + +#define BLSP1_BLSP_BASE 0x01b40000 +#define BLSP1_BLSP_BASE_SIZE 0x00040000 +#define BLSP1_BLSP_BASE_PHYS 0x01b40000 + +#define SOC_WFSS_CE_REG_BASE 0x01b80000 +#define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 +#define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 + +#define WL_TLMM_BASE 0x01bc0000 +#define WL_TLMM_BASE_SIZE 0x00020000 +#define WL_TLMM_BASE_PHYS 0x01bc0000 + +#define MEMSS_CSR_BASE 0x01be0000 +#define MEMSS_CSR_BASE_SIZE 0x0000001c +#define MEMSS_CSR_BASE_PHYS 0x01be0000 + +#define TSENS_SROT_BASE 0x01bf0000 +#define TSENS_SROT_BASE_SIZE 0x00001000 +#define TSENS_SROT_BASE_PHYS 0x01bf0000 + +#define TSENS_TM_BASE 0x01bf1000 +#define TSENS_TM_BASE_SIZE 0x00001000 +#define TSENS_TM_BASE_PHYS 0x01bf1000 + +#define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000 +#define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000 +#define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000 + +#define QDSS_WRAPPER_TOP_BASE 0x01c80000 +#define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd +#define QDSS_WRAPPER_TOP_BASE_PHYS 0x01c80000 + +#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01d00000 +#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00100000 +#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01d00000 + +#define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000 +#define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000 +#define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000 + +#define SECURITY_CONTROL_WLAN_BASE 0x01e20000 +#define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000 +#define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000 + +#define EDPD_CAL_ACC_BASE 0x01e28000 +#define EDPD_CAL_ACC_BASE_SIZE 0x00003000 +#define EDPD_CAL_ACC_BASE_PHYS 0x01e28000 + +#define CPR_CX_CPR3_BASE 0x01e30000 +#define CPR_CX_CPR3_BASE_SIZE 0x00004000 +#define CPR_CX_CPR3_BASE_PHYS 0x01e30000 + +#define CPR_MX_CPR3_BASE 0x01e34000 +#define CPR_MX_CPR3_BASE_SIZE 0x00004000 +#define CPR_MX_CPR3_BASE_PHYS 0x01e34000 + +#define GCC_GCC_BASE 0x01e40000 +#define GCC_GCC_BASE_SIZE 0x000003e8 +#define GCC_GCC_BASE_PHYS 0x01e40000 + +#define PRNG_PRNG_TOP_BASE 0x01e50000 +#define PRNG_PRNG_TOP_BASE_SIZE 0x00010000 +#define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000 + +#define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000 +#define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000 + +#define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000 +#define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000 + +#define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000 +#define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000 + +#define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000 +#define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000 + +#define RRI_PREFETCH_REG_BASE 0x01e70000 +#define RRI_PREFETCH_REG_BASE_SIZE 0x00010000 +#define RRI_PREFETCH_REG_BASE_PHYS 0x01e70000 + +#define SYSTEM_NOC_BASE 0x01e80000 +#define SYSTEM_NOC_BASE_SIZE 0x0000a000 +#define SYSTEM_NOC_BASE_PHYS 0x01e80000 + +#define PC_NOC_BASE 0x01f00000 +#define PC_NOC_BASE_SIZE 0x00003880 +#define PC_NOC_BASE_PHYS 0x01f00000 + +#define WLAON_WL_AON_REG_BASE 0x01f80000 +#define WLAON_WL_AON_REG_BASE_SIZE 0x000007c8 +#define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000 + +#define SYSPM_SYSPM_REG_BASE 0x01f82000 +#define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000 +#define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000 + +#define PMU_WLAN_PMU_TOP_BASE 0x01f88000 +#define PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000340 +#define PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000 + +#define PMU_NOC_BASE 0x01f8a000 +#define PMU_NOC_BASE_SIZE 0x00000080 +#define PMU_NOC_BASE_PHYS 0x01f8a000 + +#define PCIE_ATU_REGION_BASE 0x04000000 +#define PCIE_ATU_REGION_BASE_SIZE 0x100000000 +#define PCIE_ATU_REGION_BASE_PHYS 0x04000000 + +#define PCIE_ATU_REGION_SIZE_BASE 0x40000000 +#define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000 +#define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000 + +#define PCIE_ATU_REGION_END_BASE 0x43ffffff +#define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000 +#define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/msmhwioreg.h b/drivers/staging/fw-api/hw/peach/v1/msmhwioreg.h new file mode 100644 index 0000000000000000000000000000000000000000..4953fc29e4827685153d33d9186bb2b61cdb823e --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/msmhwioreg.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __MSMHWIOREG_H__ +#define __MSMHWIOREG_H__ + +#include "msmhwiobase.h" + +#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0xfffffffc +#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 0x2 +#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058) + + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/no_ack_report.h b/drivers/staging/fw-api/hw/peach/v1/no_ack_report.h new file mode 100644 index 0000000000000000000000000000000000000000..c80f32fe47d2c9905ac72fe9dbb417cfaa0828f9 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/no_ack_report.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _NO_ACK_REPORT_H_ +#define _NO_ACK_REPORT_H_ + +#define NUM_OF_DWORDS_NO_ACK_REPORT 4 + +struct no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_ack_transmit_reason : 4, + macrx_abort_reason : 4, + phyrx_abort_reason : 8, + frame_control : 16; + uint32_t rx_ppdu_duration : 24, + sr_ppdu_during_obss : 1, + selfgen_response_reason_to_sr_ppdu : 4, + reserved_1 : 3; + uint32_t pre_bt_broadcast_status_details : 12, + first_bt_broadcast_status_details : 12, + reserved_2 : 8; + uint32_t second_bt_broadcast_status_details : 12, + reserved_3 : 20; +#else + uint32_t frame_control : 16, + phyrx_abort_reason : 8, + macrx_abort_reason : 4, + no_ack_transmit_reason : 4; + uint32_t reserved_1 : 3, + selfgen_response_reason_to_sr_ppdu : 4, + sr_ppdu_during_obss : 1, + rx_ppdu_duration : 24; + uint32_t reserved_2 : 8, + first_bt_broadcast_status_details : 12, + pre_bt_broadcast_status_details : 12; + uint32_t reserved_3 : 20, + second_bt_broadcast_status_details : 12; +#endif +}; + +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f + +#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 + +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 + +#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 +#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 +#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + +#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 +#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff + +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 + +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 + +#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 +#define NO_ACK_REPORT_RESERVED_1_LSB 29 +#define NO_ACK_REPORT_RESERVED_1_MSB 31 +#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 + +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 + +#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 +#define NO_ACK_REPORT_RESERVED_2_LSB 24 +#define NO_ACK_REPORT_RESERVED_2_MSB 31 +#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 + +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c +#define NO_ACK_REPORT_RESERVED_3_LSB 12 +#define NO_ACK_REPORT_RESERVED_3_MSB 31 +#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/peach/v1/ofdma_trigger_details.h new file mode 100644 index 0000000000000000000000000000000000000000..e842d347bb56a31c71e9e199d53fca63dda4eadf --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/ofdma_trigger_details.h @@ -0,0 +1,834 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _OFDMA_TRIGGER_DETAILS_H_ +#define _OFDMA_TRIGGER_DETAILS_H_ + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22 + +struct ofdma_trigger_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ax_trigger_source : 1, + rx_trigger_frame_user_source : 2, + received_bandwidth : 3, + txop_duration_all_ones : 1, + eht_trigger_response : 1, + pre_rssi_comb : 8, + rssi_comb : 8, + rxpcu_pcie_l0_req_duration : 8; + uint32_t he_trigger_ul_ppdu_length : 5, + he_trigger_ru_allocation : 8, + he_trigger_dl_tx_power : 5, + he_trigger_ul_target_rssi : 5, + he_trigger_ul_mcs : 2, + he_trigger_reserved : 1, + bss_color : 6; + uint32_t trigger_type : 4, + lsig_response_length : 12, + cascade_indication : 1, + carrier_sense : 1, + bandwidth : 2, + cp_ltf_size : 2, + mu_mimo_ltf_mode : 1, + number_of_ltfs : 3, + stbc : 1, + ldpc_extra_symbol : 1, + ap_tx_power_lsb_part : 4; + uint32_t ap_tx_power_msb_part : 2, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + spatial_reuse : 16, + doppler : 1, + he_siga_reserved : 9, + reserved_3b : 1; + uint32_t aid12 : 12, + ru_allocation : 9, + mcs : 4, + dcm : 1, + start_spatial_stream : 3, + number_of_spatial_stream : 3; + uint32_t target_rssi : 7, + coding_type : 1, + mpdu_mu_spacing_factor : 2, + tid_aggregation_limit : 3, + reserved_5b : 1, + prefered_ac : 2, + bar_control_ack_policy : 1, + bar_control_multi_tid : 1, + bar_control_compressed_bitmap : 1, + bar_control_reserved : 9, + bar_control_tid_info : 4; + uint32_t nr0_per_tid_info_reserved : 12, + nr0_per_tid_info_tid_value : 4, + nr0_start_seq_ctrl_frag_number : 4, + nr0_start_seq_ctrl_start_seq_number : 12; + uint32_t nr1_per_tid_info_reserved : 12, + nr1_per_tid_info_tid_value : 4, + nr1_start_seq_ctrl_frag_number : 4, + nr1_start_seq_ctrl_start_seq_number : 12; + uint32_t nr2_per_tid_info_reserved : 12, + nr2_per_tid_info_tid_value : 4, + nr2_start_seq_ctrl_frag_number : 4, + nr2_start_seq_ctrl_start_seq_number : 12; + uint32_t nr3_per_tid_info_reserved : 12, + nr3_per_tid_info_tid_value : 4, + nr3_start_seq_ctrl_frag_number : 4, + nr3_start_seq_ctrl_start_seq_number : 12; + uint32_t nr4_per_tid_info_reserved : 12, + nr4_per_tid_info_tid_value : 4, + nr4_start_seq_ctrl_frag_number : 4, + nr4_start_seq_ctrl_start_seq_number : 12; + uint32_t nr5_per_tid_info_reserved : 12, + nr5_per_tid_info_tid_value : 4, + nr5_start_seq_ctrl_frag_number : 4, + nr5_start_seq_ctrl_start_seq_number : 12; + uint32_t nr6_per_tid_info_reserved : 12, + nr6_per_tid_info_tid_value : 4, + nr6_start_seq_ctrl_frag_number : 4, + nr6_start_seq_ctrl_start_seq_number : 12; + uint32_t nr7_per_tid_info_reserved : 12, + nr7_per_tid_info_tid_value : 4, + nr7_start_seq_ctrl_frag_number : 4, + nr7_start_seq_ctrl_start_seq_number : 12; + uint32_t fb_segment_retransmission_bitmap : 8, + reserved_14a : 2, + u_sig_puncture_pattern_encoding : 6, + dot11be_puncture_bitmap : 16; + uint32_t rx_chain_mask : 8, + rx_duration_field : 16, + scrambler_seed : 7, + rx_chain_mask_type : 1; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t sw_peer_id : 16, + response_tx_duration : 16; + uint32_t __reserved_g_0005_trigger_subtype : 4, + tbr_trigger_common_info_79_68 : 12, + tbr_trigger_sound_reserved_20_12 : 9, + i2r_rep : 3, + tbr_trigger_sound_reserved_25_24 : 2, + reserved_18a : 1, + qos_null_only_response_tx : 1; + uint32_t tbr_trigger_sound_sac : 16, + reserved_19a : 8, + u_sig_reserved2 : 5, + reserved_19b : 3; + uint32_t eht_special_aid12 : 12, + phy_version : 3, + bandwidth_ext : 2, + eht_spatial_reuse : 8, + u_sig_reserved1 : 7; + uint32_t eht_trigger_special_user_info_71_40 : 32; +#else + uint32_t rxpcu_pcie_l0_req_duration : 8, + rssi_comb : 8, + pre_rssi_comb : 8, + eht_trigger_response : 1, + txop_duration_all_ones : 1, + received_bandwidth : 3, + rx_trigger_frame_user_source : 2, + ax_trigger_source : 1; + uint32_t bss_color : 6, + he_trigger_reserved : 1, + he_trigger_ul_mcs : 2, + he_trigger_ul_target_rssi : 5, + he_trigger_dl_tx_power : 5, + he_trigger_ru_allocation : 8, + he_trigger_ul_ppdu_length : 5; + uint32_t ap_tx_power_lsb_part : 4, + ldpc_extra_symbol : 1, + stbc : 1, + number_of_ltfs : 3, + mu_mimo_ltf_mode : 1, + cp_ltf_size : 2, + bandwidth : 2, + carrier_sense : 1, + cascade_indication : 1, + lsig_response_length : 12, + trigger_type : 4; + uint32_t reserved_3b : 1, + he_siga_reserved : 9, + doppler : 1, + spatial_reuse : 16, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + ap_tx_power_msb_part : 2; + uint32_t number_of_spatial_stream : 3, + start_spatial_stream : 3, + dcm : 1, + mcs : 4, + ru_allocation : 9, + aid12 : 12; + uint32_t bar_control_tid_info : 4, + bar_control_reserved : 9, + bar_control_compressed_bitmap : 1, + bar_control_multi_tid : 1, + bar_control_ack_policy : 1, + prefered_ac : 2, + reserved_5b : 1, + tid_aggregation_limit : 3, + mpdu_mu_spacing_factor : 2, + coding_type : 1, + target_rssi : 7; + uint32_t nr0_start_seq_ctrl_start_seq_number : 12, + nr0_start_seq_ctrl_frag_number : 4, + nr0_per_tid_info_tid_value : 4, + nr0_per_tid_info_reserved : 12; + uint32_t nr1_start_seq_ctrl_start_seq_number : 12, + nr1_start_seq_ctrl_frag_number : 4, + nr1_per_tid_info_tid_value : 4, + nr1_per_tid_info_reserved : 12; + uint32_t nr2_start_seq_ctrl_start_seq_number : 12, + nr2_start_seq_ctrl_frag_number : 4, + nr2_per_tid_info_tid_value : 4, + nr2_per_tid_info_reserved : 12; + uint32_t nr3_start_seq_ctrl_start_seq_number : 12, + nr3_start_seq_ctrl_frag_number : 4, + nr3_per_tid_info_tid_value : 4, + nr3_per_tid_info_reserved : 12; + uint32_t nr4_start_seq_ctrl_start_seq_number : 12, + nr4_start_seq_ctrl_frag_number : 4, + nr4_per_tid_info_tid_value : 4, + nr4_per_tid_info_reserved : 12; + uint32_t nr5_start_seq_ctrl_start_seq_number : 12, + nr5_start_seq_ctrl_frag_number : 4, + nr5_per_tid_info_tid_value : 4, + nr5_per_tid_info_reserved : 12; + uint32_t nr6_start_seq_ctrl_start_seq_number : 12, + nr6_start_seq_ctrl_frag_number : 4, + nr6_per_tid_info_tid_value : 4, + nr6_per_tid_info_reserved : 12; + uint32_t nr7_start_seq_ctrl_start_seq_number : 12, + nr7_start_seq_ctrl_frag_number : 4, + nr7_per_tid_info_tid_value : 4, + nr7_per_tid_info_reserved : 12; + uint32_t dot11be_puncture_bitmap : 16, + u_sig_puncture_pattern_encoding : 6, + reserved_14a : 2, + fb_segment_retransmission_bitmap : 8; + uint32_t rx_chain_mask_type : 1, + scrambler_seed : 7, + rx_duration_field : 16, + rx_chain_mask : 8; + uint32_t normalized_rssi_comb : 8, + normalized_pre_rssi_comb : 8; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint32_t response_tx_duration : 16, + sw_peer_id : 16; + uint32_t qos_null_only_response_tx : 1, + reserved_18a : 1, + tbr_trigger_sound_reserved_25_24 : 2, + i2r_rep : 3, + tbr_trigger_sound_reserved_20_12 : 9, + tbr_trigger_common_info_79_68 : 12, + __reserved_g_0005_trigger_subtype : 4; + uint32_t reserved_19b : 3, + u_sig_reserved2 : 5, + reserved_19a : 8, + tbr_trigger_sound_sac : 16; + uint32_t u_sig_reserved1 : 7, + eht_spatial_reuse : 8, + bandwidth_ext : 2, + phy_version : 3, + eht_special_aid12 : 12; + uint32_t eht_trigger_special_user_info_71_40 : 32; +#endif +}; + +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000001 + +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x00000006 + +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x00000038 + +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x00000040 + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x00000080 + +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x0000ff00 + +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x00ff0000 + +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0xff000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 0 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 4 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 5 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 12 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe0 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 13 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 17 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 18 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 22 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c0000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 23 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 24 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x01800000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 25 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 25 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x02000000 + +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 26 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 31 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc000000 + +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0000fff0 + +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x00010000 + +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x00020000 + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x000c0000 + +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x00300000 + +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x00400000 + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x03800000 + +#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x04000000 + +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x08000000 + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0xf0000000 + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 1 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x00000003 + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 2 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 3 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 4 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 4 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000010 + +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 5 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 20 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe0 + +#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 21 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 21 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x00200000 + +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 22 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 30 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc00000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 31 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x80000000 + +#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x001ff000 + +#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 +#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 +#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x01e00000 + +#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x02000000 + +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x1c000000 + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0xe0000000 + +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 6 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f + +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 7 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 7 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x00000080 + +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 8 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 9 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x00000300 + +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 10 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 12 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c00 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 13 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 13 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x00002000 + +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 14 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 15 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 16 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 16 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x00010000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 17 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 17 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x00020000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 18 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 18 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x00040000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 19 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 27 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff80000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 28 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 31 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf0000000 + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x00000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x00000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000001c +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000001c +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000001c +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000001c +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x00000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x00000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x00000024 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x00000024 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000024 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000024 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x00000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x00000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000002c +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000002c +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000002c +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000002c +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x00000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x00000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x00000034 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x00000034 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000034 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000034 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x00000038 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x000000ff + +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x00000038 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x00000300 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000038 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000fc00 + +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000038 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0xffff0000 + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000003c +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 0 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 7 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff + +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000003c +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 8 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff00 + +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000003c +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 24 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 30 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f000000 + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000003c +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 31 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x80000000 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000 + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0xff000000 + +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x00000044 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 0 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 15 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff + +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x00000044 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff0000 + +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x0000000f + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x0000fff0 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x01ff0000 + +#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x0e000000 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x30000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x40000000 + +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x80000000 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000004c +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 15 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000004c +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff0000 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000004c +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 24 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 28 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000004c +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 29 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe0000000 + +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x00007000 + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x00018000 + +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x01fe0000 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0xfe000000 + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x00000054 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 0 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 31 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/peach/v1/pcu_ppdu_setup_init.h new file mode 100644 index 0000000000000000000000000000000000000000..90d022543c271434c2db5f19eb4ad6c1e316120a --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/pcu_ppdu_setup_init.h @@ -0,0 +1,2282 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PCU_PPDU_SETUP_INIT_H_ +#define _PCU_PPDU_SETUP_INIT_H_ + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 + +struct pcu_ppdu_setup_init { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t medium_prot_type : 3, + response_type : 5, + response_info_part2_required : 1, + response_to_response : 3, + mba_user_order : 2, + expected_mba_size : 11, + required_ul_mu_resp_user_count : 6, + transmitted_bssid_check_en : 1; + uint32_t mprot_required_bw1 : 1, + mprot_required_bw20 : 1, + mprot_required_bw40 : 1, + mprot_required_bw80 : 1, + mprot_required_bw160 : 1, + mprot_required_bw240 : 1, + mprot_required_bw320 : 1, + ppdu_allowed_bw1 : 1, + ppdu_allowed_bw20 : 1, + ppdu_allowed_bw40 : 1, + ppdu_allowed_bw80 : 1, + ppdu_allowed_bw160 : 1, + ppdu_allowed_bw240 : 1, + ppdu_allowed_bw320 : 1, + set_fc_pwr_mgt : 1, + use_cts_duration_for_data_tx : 1, + update_timestamp_64 : 1, + update_timestamp_32_lower : 1, + update_timestamp_32_upper : 1, + reserved_1a : 13; + uint32_t insert_timestamp_offset_0 : 16, + insert_timestamp_offset_1 : 16; + uint32_t max_bw40_try_count : 4, + max_bw80_try_count : 4, + max_bw160_try_count : 4, + max_bw240_try_count : 4, + max_bw320_try_count : 4, + insert_wur_timestamp_offset : 6, + update_wur_timestamp : 1, + wur_embedded_bssid_present : 1, + insert_wur_fcs : 1, + reserved_3b : 3; + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_hw_response_tx_duration : 16, + r2r_rx_duration_field : 16; + uint32_t r2r_group_id : 6, + r2r_response_frame_type : 4, + r2r_sta_partial_aid : 11, + use_address_fields_for_protection : 1, + r2r_set_required_response_time : 1, + reserved_29a : 3, + r2r_bw20_active_channel : 3, + r2r_bw40_active_channel : 3; + uint32_t r2r_bw80_active_channel : 3, + r2r_bw160_active_channel : 3, + r2r_bw240_active_channel : 3, + r2r_bw320_active_channel : 3, + r2r_bw20 : 3, + r2r_bw40 : 3, + r2r_bw80 : 3, + r2r_bw160 : 3, + r2r_bw240 : 3, + r2r_bw320 : 3, + reserved_30a : 2; + uint32_t mu_response_expected_bitmap_31_0 : 32; + uint32_t mu_response_expected_bitmap_36_32 : 5, + mu_expected_response_cbf_count : 6, + mu_expected_response_sta_count : 6, + transmit_includes_multidestination : 1, + insert_prev_tx_start_timing_info : 1, + insert_current_tx_start_timing_info : 1, + tx_start_transmit_time_byte_offset : 12; + uint32_t protection_frame_ad1_31_0 : 32; + uint32_t protection_frame_ad1_47_32 : 16, + protection_frame_ad2_15_0 : 16; + uint32_t protection_frame_ad2_47_16 : 32; + uint32_t dynamic_medium_prot_threshold : 24, + dynamic_medium_prot_type : 1, + reserved_54a : 7; + uint32_t protection_frame_ad3_31_0 : 32; + uint32_t protection_frame_ad3_47_32 : 16, + protection_frame_ad4_15_0 : 16; + uint32_t protection_frame_ad4_47_16 : 32; +#else + uint32_t transmitted_bssid_check_en : 1, + required_ul_mu_resp_user_count : 6, + expected_mba_size : 11, + mba_user_order : 2, + response_to_response : 3, + response_info_part2_required : 1, + response_type : 5, + medium_prot_type : 3; + uint32_t reserved_1a : 13, + update_timestamp_32_upper : 1, + update_timestamp_32_lower : 1, + update_timestamp_64 : 1, + use_cts_duration_for_data_tx : 1, + set_fc_pwr_mgt : 1, + ppdu_allowed_bw320 : 1, + ppdu_allowed_bw240 : 1, + ppdu_allowed_bw160 : 1, + ppdu_allowed_bw80 : 1, + ppdu_allowed_bw40 : 1, + ppdu_allowed_bw20 : 1, + ppdu_allowed_bw1 : 1, + mprot_required_bw320 : 1, + mprot_required_bw240 : 1, + mprot_required_bw160 : 1, + mprot_required_bw80 : 1, + mprot_required_bw40 : 1, + mprot_required_bw20 : 1, + mprot_required_bw1 : 1; + uint32_t insert_timestamp_offset_1 : 16, + insert_timestamp_offset_0 : 16; + uint32_t reserved_3b : 3, + insert_wur_fcs : 1, + wur_embedded_bssid_present : 1, + update_wur_timestamp : 1, + insert_wur_timestamp_offset : 6, + max_bw320_try_count : 4, + max_bw240_try_count : 4, + max_bw160_try_count : 4, + max_bw80_try_count : 4, + max_bw40_try_count : 4; + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_rx_duration_field : 16, + r2r_hw_response_tx_duration : 16; + uint32_t r2r_bw40_active_channel : 3, + r2r_bw20_active_channel : 3, + reserved_29a : 3, + r2r_set_required_response_time : 1, + use_address_fields_for_protection : 1, + r2r_sta_partial_aid : 11, + r2r_response_frame_type : 4, + r2r_group_id : 6; + uint32_t reserved_30a : 2, + r2r_bw320 : 3, + r2r_bw240 : 3, + r2r_bw160 : 3, + r2r_bw80 : 3, + r2r_bw40 : 3, + r2r_bw20 : 3, + r2r_bw320_active_channel : 3, + r2r_bw240_active_channel : 3, + r2r_bw160_active_channel : 3, + r2r_bw80_active_channel : 3; + uint32_t mu_response_expected_bitmap_31_0 : 32; + uint32_t tx_start_transmit_time_byte_offset : 12, + insert_current_tx_start_timing_info : 1, + insert_prev_tx_start_timing_info : 1, + transmit_includes_multidestination : 1, + mu_expected_response_sta_count : 6, + mu_expected_response_cbf_count : 6, + mu_response_expected_bitmap_36_32 : 5; + uint32_t protection_frame_ad1_31_0 : 32; + uint32_t protection_frame_ad2_15_0 : 16, + protection_frame_ad1_47_32 : 16; + uint32_t protection_frame_ad2_47_16 : 32; + uint32_t reserved_54a : 7, + dynamic_medium_prot_type : 1, + dynamic_medium_prot_threshold : 24; + uint32_t protection_frame_ad3_31_0 : 32; + uint32_t protection_frame_ad4_15_0 : 16, + protection_frame_ad3_47_32 : 16; + uint32_t protection_frame_ad4_47_16 : 32; +#endif +}; + +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x00000007 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x000000f8 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x00000100 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x00000e00 + +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x00003000 + +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x01ffc000 + +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x7e000000 + +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 0 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 0 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 1 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 1 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x00000002 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 2 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 2 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x00000004 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 3 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 3 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x00000008 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 4 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 4 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x00000010 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 5 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 5 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x00000020 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 6 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 6 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x00000040 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 7 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 7 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 8 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 8 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x00000100 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 9 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 9 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x00000200 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 10 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 10 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 11 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 11 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 12 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 12 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 13 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 13 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 14 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 14 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 15 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 15 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 16 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 16 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x00010000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 17 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 17 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x00020000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 18 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 18 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x00040000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff80000 + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x00000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x0000ffff + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x00000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0xffff0000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 0 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 3 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 4 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 7 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 8 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 11 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f00 + +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 12 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 15 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 16 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 19 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f0000 + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 20 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 25 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 26 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 26 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 27 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 27 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x08000000 + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 28 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 28 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x10000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xe0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff + +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0xffff0000 + +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 5 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f + +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 6 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 9 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c0 + +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 10 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 20 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc00 + +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 21 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 21 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 22 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 22 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x00400000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 23 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x03800000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 26 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 28 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 29 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 31 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe0000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x00000007 + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x00000038 + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x000001c0 + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x00000e00 + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x00007000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x00038000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x00e00000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x07000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MASK 0xc0000000 + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x000000c4 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x0000001f + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x000007e0 + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x0001f800 + +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x00020000 + +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x00040000 + +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0xfff00000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x000000cc +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x0000ffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0xffff0000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x000000d4 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x00ffffff + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x000000d8 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0xfe000000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x000000dc +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x0000ffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0xffff0000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x000000e4 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/pdg_response.h b/drivers/staging/fw-api/hw/peach/v1/pdg_response.h new file mode 100644 index 0000000000000000000000000000000000000000..7060494a33e7e6e6e392c13316cfedcbfc6566fb --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/pdg_response.h @@ -0,0 +1,473 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PDG_RESPONSE_H_ +#define _PDG_RESPONSE_H_ + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PDG_RESPONSE 12 + +struct pdg_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t hw_response_tx_duration : 16, + rx_duration_field : 16; + uint32_t punctured_response_transmission : 1, + cca_subband_channel_bonding_mask : 16, + scrambler_seed_override : 2, + response_density_valid : 1, + response_density : 5, + more_data : 1, + duration_indication : 1, + relayed_frame : 1, + address_indicator : 1, + bandwidth : 3; + uint32_t ack_id : 16, + block_ack_bitmap : 16; + uint32_t response_frame_type : 4, + ack_id_ext : 10, + ftm_en : 1, + group_id : 6, + sta_partial_aid : 11; + uint32_t ndp_ba_start_seq_ctrl : 12, + active_channel : 3, + txop_duration_all_ones : 1, + frame_length : 16; +#else + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t rx_duration_field : 16, + hw_response_tx_duration : 16; + uint32_t bandwidth : 3, + address_indicator : 1, + relayed_frame : 1, + duration_indication : 1, + more_data : 1, + response_density : 5, + response_density_valid : 1, + scrambler_seed_override : 2, + cca_subband_channel_bonding_mask : 16, + punctured_response_transmission : 1; + uint32_t block_ack_bitmap : 16, + ack_id : 16; + uint32_t sta_partial_aid : 11, + group_id : 6, + ftm_en : 1, + ack_id_ext : 10, + response_frame_type : 4; + uint32_t frame_length : 16, + txop_duration_all_ones : 1, + active_channel : 3, + ndp_ba_start_seq_ctrl : 12; +#endif +}; + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x00000001 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x1e000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x20000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x40000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x80000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x00070000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 19 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x38000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x0000000f + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x00000070 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x00000080 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x00ff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0xff000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x00000300 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c00 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x00000001 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x00002000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0xf8000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x00000400 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 20 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f00000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000001c +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff + +#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000001c +#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 16 +#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 31 +#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff0000 + +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x00000020 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x00000001 + +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x00000020 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x0001fffe + +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x00000020 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x00060000 + +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x00000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x00080000 + +#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x00000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 +#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 +#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x01f00000 + +#define PDG_RESPONSE_MORE_DATA_OFFSET 0x00000020 +#define PDG_RESPONSE_MORE_DATA_LSB 25 +#define PDG_RESPONSE_MORE_DATA_MSB 25 +#define PDG_RESPONSE_MORE_DATA_MASK 0x02000000 + +#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x00000020 +#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x04000000 + +#define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x00000020 +#define PDG_RESPONSE_RELAYED_FRAME_LSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MASK 0x08000000 + +#define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x00000020 +#define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x10000000 + +#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x00000020 +#define PDG_RESPONSE_BANDWIDTH_LSB 29 +#define PDG_RESPONSE_BANDWIDTH_MSB 31 +#define PDG_RESPONSE_BANDWIDTH_MASK 0xe0000000 + +#define PDG_RESPONSE_ACK_ID_OFFSET 0x00000024 +#define PDG_RESPONSE_ACK_ID_LSB 0 +#define PDG_RESPONSE_ACK_ID_MSB 15 +#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff + +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x00000024 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 16 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 31 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff0000 + +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x00000028 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x0000000f + +#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x00000028 +#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 +#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 +#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x00003ff0 + +#define PDG_RESPONSE_FTM_EN_OFFSET 0x00000028 +#define PDG_RESPONSE_FTM_EN_LSB 14 +#define PDG_RESPONSE_FTM_EN_MSB 14 +#define PDG_RESPONSE_FTM_EN_MASK 0x00004000 + +#define PDG_RESPONSE_GROUP_ID_OFFSET 0x00000028 +#define PDG_RESPONSE_GROUP_ID_LSB 15 +#define PDG_RESPONSE_GROUP_ID_MSB 20 +#define PDG_RESPONSE_GROUP_ID_MASK 0x001f8000 + +#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x00000028 +#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 +#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 +#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0xffe00000 + +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000002c +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 0 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 11 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff + +#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000002c +#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 12 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 14 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x00007000 + +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000002c +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 15 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 15 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x00008000 + +#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000002c +#define PDG_RESPONSE_FRAME_LENGTH_LSB 16 +#define PDG_RESPONSE_FRAME_LENGTH_MSB 31 +#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/pdg_response_rate_setting.h b/drivers/staging/fw-api/hw/peach/v1/pdg_response_rate_setting.h new file mode 100644 index 0000000000000000000000000000000000000000..7a187717bf40b6849059f628f6bb385fd8be5dde --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/pdg_response_rate_setting.h @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PDG_RESPONSE_RATE_SETTING_H_ +#define _PDG_RESPONSE_RATE_SETTING_H_ + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 + +struct pdg_response_rate_setting { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 1, + tx_antenna_sector_ctrl : 24, + pkt_type : 4, + smoothing : 1, + ldpc : 1, + stbc : 1; + uint32_t alt_tx_pwr : 8, + alt_min_tx_pwr : 8, + alt_nss : 3, + alt_tx_chain_mask : 8, + alt_bw : 3, + stf_ltf_3db_boost : 1, + force_extra_symbol : 1; + uint32_t alt_rate_mcs : 4, + nss : 3, + dpd_enable : 1, + tx_pwr : 8, + min_tx_pwr : 8, + tx_chain_mask : 8; + uint32_t reserved_3a : 8, + sgi : 2, + rate_mcs : 4, + reserved_3b : 2, + tx_pwr_1 : 8, + alt_tx_pwr_1 : 8; + uint32_t aggregation : 1, + dot11ax_bss_color_id : 6, + dot11ax_spatial_reuse : 4, + dot11ax_cp_ltf_size : 2, + dot11ax_dcm : 1, + dot11ax_doppler_indication : 1, + dot11ax_su_extended : 1, + dot11ax_min_packet_extension : 2, + dot11ax_pe_nss : 3, + dot11ax_pe_content : 1, + dot11ax_pe_ltf_size : 2, + dot11ax_chain_csd_en : 1, + dot11ax_pe_chain_csd_en : 1, + dot11ax_dl_ul_flag : 1, + reserved_4a : 5; + uint32_t dot11ax_ext_ru_start_index : 4, + dot11ax_ext_ru_size : 4, + eht_duplicate_mode : 2, + he_sigb_dcm : 1, + he_sigb_0_mcs : 3, + num_he_sigb_sym : 5, + required_response_time_source : 1, + reserved_5a : 6, + u_sig_puncture_pattern_encoding : 6; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t required_response_time : 12, + dot11be_params_placeholder : 4; +#else + uint32_t stbc : 1, + ldpc : 1, + smoothing : 1, + pkt_type : 4, + tx_antenna_sector_ctrl : 24, + reserved_0a : 1; + uint32_t force_extra_symbol : 1, + stf_ltf_3db_boost : 1, + alt_bw : 3, + alt_tx_chain_mask : 8, + alt_nss : 3, + alt_min_tx_pwr : 8, + alt_tx_pwr : 8; + uint32_t tx_chain_mask : 8, + min_tx_pwr : 8, + tx_pwr : 8, + dpd_enable : 1, + nss : 3, + alt_rate_mcs : 4; + uint32_t alt_tx_pwr_1 : 8, + tx_pwr_1 : 8, + reserved_3b : 2, + rate_mcs : 4, + sgi : 2, + reserved_3a : 8; + uint32_t reserved_4a : 5, + dot11ax_dl_ul_flag : 1, + dot11ax_pe_chain_csd_en : 1, + dot11ax_chain_csd_en : 1, + dot11ax_pe_ltf_size : 2, + dot11ax_pe_content : 1, + dot11ax_pe_nss : 3, + dot11ax_min_packet_extension : 2, + dot11ax_su_extended : 1, + dot11ax_doppler_indication : 1, + dot11ax_dcm : 1, + dot11ax_cp_ltf_size : 2, + dot11ax_spatial_reuse : 4, + dot11ax_bss_color_id : 6, + aggregation : 1; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_5a : 6, + required_response_time_source : 1, + num_he_sigb_sym : 5, + he_sigb_0_mcs : 3, + he_sigb_dcm : 1, + eht_duplicate_mode : 2, + dot11ax_ext_ru_size : 4, + dot11ax_ext_ru_start_index : 4; + uint32_t dot11be_params_placeholder : 4, + required_response_time : 12; + struct mlo_sta_id_details mlo_sta_id_details_rx; +#endif +}; + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 + +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 + +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 + +#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 + +#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff + +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 + +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f + +#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 + +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 + +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff + +#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 + +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000 + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 + +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 + +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/pdg_tx_req.h b/drivers/staging/fw-api/hw/peach/v1/pdg_tx_req.h new file mode 100644 index 0000000000000000000000000000000000000000..82333c6a21c55573c5f23fae85b4640ab970ce50 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/pdg_tx_req.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PDG_TX_REQ_H_ +#define _PDG_TX_REQ_H_ + +#define NUM_OF_DWORDS_PDG_TX_REQ 2 + +struct pdg_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_reason : 2, + use_puncture_pattern : 2, + req_bw : 3, + puncture_pattern_number : 6, + reserved_0b : 1, + req_paprd : 1, + duration_field_boundary_valid : 1, + duration_field_boundary : 16; + uint32_t puncture_subband_mask : 16, + reserved_0c : 16; +#else + uint32_t duration_field_boundary : 16, + duration_field_boundary_valid : 1, + req_paprd : 1, + reserved_0b : 1, + puncture_pattern_number : 6, + req_bw : 3, + use_puncture_pattern : 2, + tx_reason : 2; + uint32_t reserved_0c : 16, + puncture_subband_mask : 16; +#endif +}; + +#define PDG_TX_REQ_TX_REASON_OFFSET 0x00000000 +#define PDG_TX_REQ_TX_REASON_LSB 0 +#define PDG_TX_REQ_TX_REASON_MSB 1 +#define PDG_TX_REQ_TX_REASON_MASK 0x00000003 + +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x00000000 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x0000000c + +#define PDG_TX_REQ_REQ_BW_OFFSET 0x00000000 +#define PDG_TX_REQ_REQ_BW_LSB 4 +#define PDG_TX_REQ_REQ_BW_MSB 6 +#define PDG_TX_REQ_REQ_BW_MASK 0x00000070 + +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x00000000 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x00001f80 + +#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x00000000 +#define PDG_TX_REQ_RESERVED_0B_LSB 13 +#define PDG_TX_REQ_RESERVED_0B_MSB 13 +#define PDG_TX_REQ_RESERVED_0B_MASK 0x00002000 + +#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x00000000 +#define PDG_TX_REQ_REQ_PAPRD_LSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MASK 0x00004000 + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x00000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x00008000 + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x00000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0xffff0000 + +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x00000004 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 0 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 15 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff + +#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x00000004 +#define PDG_TX_REQ_RESERVED_0C_LSB 16 +#define PDG_TX_REQ_RESERVED_0C_MSB 31 +#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_abort_request_info.h new file mode 100644 index 0000000000000000000000000000000000000000..76d5ef73c2b90ea927f1ed3d0d03577eac0a0214 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_abort_request_info.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ +#define _PHYRX_ABORT_REQUEST_INFO_H_ + +#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 + +struct phyrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phyrx_abort_reason : 8, + phy_enters_nap_state : 1, + phy_enters_defer_state : 1, + gain_change_by_main : 1, + gain_change_by_bt : 1, + main_tx_indication : 1, + bt_tx_indication : 1, + concurrent_mode : 1, + reserved_0 : 1, + receive_duration : 16; +#else + uint32_t receive_duration : 16, + reserved_0 : 1, + concurrent_mode : 1, + bt_tx_indication : 1, + main_tx_indication : 1, + gain_change_by_bt : 1, + gain_change_by_main : 1, + phy_enters_defer_state : 1, + phy_enters_nap_state : 1, + phyrx_abort_reason : 8; +#endif +}; + +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB 10 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB 10 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK 0x00000400 + +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB 11 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB 11 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK 0x00000800 + +#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB 12 +#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB 12 +#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK 0x00001000 + +#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB 13 +#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB 13 +#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK 0x00002000 + +#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB 14 +#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB 14 +#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK 0x00004000 + +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 15 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x00008000 + +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_common_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..eeb21a463ecdc0cca8c72805e3fe920aa049ee97 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_common_user_info.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_COMMON_USER_INFO_H_ +#define _PHYRX_COMMON_USER_INFO_H_ + +#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4 + +struct phyrx_common_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t receive_duration : 16, + reserved_0a : 16; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_1a : 9, + obss_nav_update_enable : 1, + obss_nav_value : 16; + uint32_t eht_ppdu_type : 2, + bss_color_id : 6, + dl_ul_flag : 1, + txop_duration : 7, + cp_setting : 2, + ltf_size : 2, + spatial_reuse : 4, + rx_ndp : 1, + dot11be_su_extended : 1, + reserved_2a : 6; + uint32_t eht_duplicate : 2, + eht_sig_cmn_field_type : 2, + doppler_indication : 1, + sta_id : 11, + puncture_bitmap : 16; +#else + uint32_t reserved_0a : 16, + receive_duration : 16; + uint32_t obss_nav_value : 16, + obss_nav_update_enable : 1, + reserved_1a : 9, + u_sig_puncture_pattern_encoding : 6; + uint32_t reserved_2a : 6, + dot11be_su_extended : 1, + rx_ndp : 1, + spatial_reuse : 4, + ltf_size : 2, + cp_setting : 2, + txop_duration : 7, + dl_ul_flag : 1, + bss_color_id : 6, + eht_ppdu_type : 2; + uint32_t puncture_bitmap : 16, + sta_id : 11, + doppler_indication : 1, + eht_sig_cmn_field_type : 2, + eht_duplicate : 2; +#endif +}; + +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x0000ffff + +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0xffff0000 + +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000004 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 0 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 5 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f + +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 6 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 14 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0x00007fc0 + +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET 0x00000004 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB 15 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB 15 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK 0x00008000 + +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET 0x00000004 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB 16 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB 31 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK 0xffff0000 + +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_LSB 0 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MSB 1 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MASK 0x00000003 + +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x000000fc + +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x00000100 + +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x0000fe00 + +#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x00030000 + +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x000c0000 + +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x00f00000 + +#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24 +#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24 +#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x01000000 + +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_LSB 25 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MSB 25 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MASK 0x02000000 + +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0xfc000000 + +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 0 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 1 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x00000003 + +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_LSB 2 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MSB 3 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MASK 0x0000000c + +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 4 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 4 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x00000010 + +#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 5 +#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 15 +#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe0 + +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 16 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 31 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_dl.h new file mode 100644 index 0000000000000000000000000000000000000000..d1c2b1e1b8e47d87cf1c8ac71a0a116d6a9e2e30 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_dl.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ +#define _PHYRX_HE_SIG_A_MU_DL_H_ + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 + +struct phyrx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#endif +}; + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 7 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 10 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 11 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 12 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 14 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 19 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 30 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_ul.h new file mode 100644 index 0000000000000000000000000000000000000000..fdf4307f5ff7cb0bb68424276ce613fa829c0752 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_ul.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ +#define _PHYRX_HE_SIG_A_MU_UL_H_ + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 + +struct phyrx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +#endif +}; + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 15 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 19 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 25 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 30 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_su.h new file mode 100644 index 0000000000000000000000000000000000000000..387503c0d79d9f13cb10e12ddd3275440393c605 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_su.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_A_SU_H_ +#define _PHYRX_HE_SIG_A_SU_H_ + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 + +struct phyrx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#endif +}; + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 8 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 9 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 10 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 12 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 15 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 19 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 25 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 29 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 30 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 30 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x40000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b1_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..cfe51c2026c0244343c79c84860cbd8bc808a175 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b1_mu.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_B1_MU_H_ +#define _PHYRX_HE_SIG_B1_MU_H_ + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1 + +struct phyrx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; +#else + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; +#endif +}; + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x7fffff00 + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..1fc8f8b0da2246c038050d87b05ac8c82f5df536 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_mu.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_B2_MU_H_ +#define _PHYRX_HE_SIG_B2_MU_H_ + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2 + +struct phyrx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#endif +}; + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x0fe00000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x70000000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 0 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 7 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 8 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 15 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff00 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 16 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_ofdma.h new file mode 100644 index 0000000000000000000000000000000000000000..60f343a1eb1787d513f095aca4fa09c4e418918a --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_ofdma.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ +#define _PHYRX_HE_SIG_B2_OFDMA_H_ + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2 + +struct phyrx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#endif +}; + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x7fe00000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 7 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 8 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff00 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 16 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_ht_sig.h new file mode 100644 index 0000000000000000000000000000000000000000..f9f1e04911a28758bb66c2e4852955d2d5f04e5d --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_ht_sig.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HT_SIG_H_ +#define _PHYRX_HT_SIG_H_ + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 + +struct phyrx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info phyrx_ht_sig_info_details; +#else + struct ht_sig_info phyrx_ht_sig_info_details; +#endif +}; + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 0 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 1 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 2 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 3 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 4 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 5 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 6 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 9 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 17 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 23 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 30 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_a.h new file mode 100644 index 0000000000000000000000000000000000000000..568e3dfc27f12654661399e130026fbfe9c7cc6b --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_a.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_L_SIG_A_H_ +#define _PHYRX_L_SIG_A_H_ + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1 + +struct phyrx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info phyrx_l_sig_a_info_details; +#else + struct l_sig_a_info phyrx_l_sig_a_info_details; +#endif +}; + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x60000000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_b.h new file mode 100644 index 0000000000000000000000000000000000000000..6c472400e61406723327aeec7c18d4987258c65c --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_b.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_L_SIG_B_H_ +#define _PHYRX_L_SIG_B_H_ + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1 + +struct phyrx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info phyrx_l_sig_b_info_details; +#else + struct l_sig_b_info phyrx_l_sig_b_info_details; +#endif +}; + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0 + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x7fff0000 + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_location.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_location.h new file mode 100644 index 0000000000000000000000000000000000000000..1c92be1c6d5fc8fde77110df9a6851de718c6bc9 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_location.h @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_LOCATION_H_ +#define _PHYRX_LOCATION_H_ + +#include "rx_location_info.h" +#define NUM_OF_DWORDS_PHYRX_LOCATION 28 + +struct phyrx_location { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_location_info rx_location_info_details; +#else + struct rx_location_info rx_location_info_details; +#endif +}; + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x00000001 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x00000002 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_LSB 2 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MSB 3 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MASK 0x0000000c + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x000000f0 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x0000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0xff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x00000004 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x00000004 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 19 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 20 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f00000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0xff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000014 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x00000018 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0xffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000001c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x00000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x00000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x00000024 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x00000024 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x00000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x000000ff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x00000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000002c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000002c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x00000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x00000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x00000034 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x00000034 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x00000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x00000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000003c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000003c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x00000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x00000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x00000044 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x00000044 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x00000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x00000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000004c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000004c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x00000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x00000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x00000054 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x00000054 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x00000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x00000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000005c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000005c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x00000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x00000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x00000064 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x00000064 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x00000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x00000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000006c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_other_receive_info_ru_details.h new file mode 100644 index 0000000000000000000000000000000000000000..03f379615ad049b5ccb2fa7e990844485b8ae62a --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_other_receive_info_ru_details.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 3 + +struct phyrx_other_receive_info_ru_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_details_channel_0 : 32; + uint32_t ru_details_channel_1 : 32; + uint32_t spare : 32; +#else + uint32_t ru_details_channel_0 : 32; + uint32_t ru_details_channel_1 : 32; + uint32_t spare : 32; +#endif +}; + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x00000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0xffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x00000004 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x00000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end.h new file mode 100644 index 0000000000000000000000000000000000000000..ab6d45be6a99ce80cfffa1b55ec0eb752d67e44c --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end.h @@ -0,0 +1,432 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_PKT_END_H_ +#define _PHYRX_PKT_END_H_ + +#include "phyrx_pkt_end_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END 24 + +struct phyrx_pkt_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct phyrx_pkt_end_info rx_pkt_end_details; +#else + struct phyrx_pkt_end_info rx_pkt_end_details; +#endif +}; + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x00000002 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x00000004 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x00000008 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x00000010 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x000000c0 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0xffff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xfffff000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x00000058 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000005c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end_info.h new file mode 100644 index 0000000000000000000000000000000000000000..31e6ca16566bd0b79ec6b9fbd41d16825b93bcde --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end_info.h @@ -0,0 +1,457 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_PKT_END_INFO_H_ +#define _PHYRX_PKT_END_INFO_H_ + +#include "receive_rssi_info.h" +#include "rx_timing_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 + +struct phyrx_pkt_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t __reserved_g_0001 : 1, + location_info_valid : 1, + timing_info_valid : 1, + rssi_info_valid : 1, + reserved_0a : 1, + frameless_frame_received : 1, + reserved_0b : 2, + rssi_comb : 8, + reserved_0c : 16; + struct rx_timing_info rx_timing_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; + uint32_t phy_sw_status_63_32 : 32; +#else + uint32_t reserved_0c : 16, + rssi_comb : 8, + reserved_0b : 2, + frameless_frame_received : 1, + reserved_0a : 1, + rssi_info_valid : 1, + timing_info_valid : 1, + location_info_valid : 1, + __reserved_g_0001 : 1; + struct rx_timing_info rx_timing_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; + uint32_t phy_sw_status_63_32 : 32; +#endif +}; + +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 + +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 + +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 + +#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 + +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 + +#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xfffff000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_rssi_legacy.h new file mode 100644 index 0000000000000000000000000000000000000000..61f865a012ce4608bf5068f38170bc1680946225 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_rssi_legacy.h @@ -0,0 +1,811 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_RSSI_LEGACY_H_ +#define _PHYRX_RSSI_LEGACY_H_ + +#include "receive_rssi_info.h" +#include "receive_pkt_start_info.h" +#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 + +struct phyrx_rssi_legacy { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_pkt_start_info rx_pkt_start_details; + uint32_t sw_phy_meta_data : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t pre_rssi_comb : 8, + rssi_comb : 8, + normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t rssi_comb_ppdu : 8, + rssi_db_to_dbm_offset : 8, + rssi_for_spatial_reuse : 8, + rssi_for_trigger_resp : 8; +#else + struct receive_pkt_start_info rx_pkt_start_details; + uint32_t sw_phy_meta_data : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t normalized_rssi_comb : 8, + normalized_pre_rssi_comb : 8, + rssi_comb : 8, + pre_rssi_comb : 8; + uint32_t rssi_for_trigger_resp : 8, + rssi_for_spatial_reuse : 8, + rssi_db_to_dbm_offset : 8, + rssi_comb_ppdu : 8; +#endif +}; + +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_LSB 0 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MSB 3 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MASK 0x0000000f + +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_LSB 4 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MSB 4 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MASK 0x00000010 + +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB 5 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB 7 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK 0x000000e0 + +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_LSB 8 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MSB 15 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_LSB 16 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MSB 31 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MASK 0xffff0000 + +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_LSB 8 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_MSB 8 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_MASK 0x00000100 + +#define PHYRX_RSSI_LEGACY_RESERVED_3A_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_RESERVED_3A_LSB 9 +#define PHYRX_RSSI_LEGACY_RESERVED_3A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_3A_MASK 0xfffffe00 + +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 31 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000094 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000094 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000094 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000094 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000009c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000009c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000009c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000009c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x000000a0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x000000a4 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 7 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x000000a4 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 8 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 15 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x000000a4 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 16 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 23 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x000000a4 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 24 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 31 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_user_info.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..b3b4cb6ced1526424c26b100436c34f42180063c --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_user_info.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_USER_INFO_H_ +#define _PHYRX_USER_INFO_H_ + +#include "receive_user_info.h" +#define NUM_OF_DWORDS_PHYRX_USER_INFO 8 + +struct phyrx_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_user_info receive_user_info_details; +#else + struct receive_user_info receive_user_info_details; +#endif +}; + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 3 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 5 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 7 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 18 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00070000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 19 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f80000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x000000fe + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x00000700 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x00003800 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x00004000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00008000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x000f0000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x00f00000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x0f000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0xf0000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 5 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 6 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 7 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c0 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 8 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 13 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f00 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 14 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 21 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f0000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 22 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c00000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 29 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 30 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc0000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x00000010 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0xffffffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x00000014 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x00000018 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0xffffffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000001c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_vht_sig_a.h new file mode 100644 index 0000000000000000000000000000000000000000..dda1c96b070d010eda88ef2ab34d3a84fa27e6d4 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_vht_sig_a.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_VHT_SIG_A_H_ +#define _PHYRX_VHT_SIG_A_H_ + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 + +struct phyrx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#else + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#endif +}; + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 1 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 7 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 8 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 9 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 17 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 30 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phytx_abort_request_info.h b/drivers/staging/fw-api/hw/peach/v1/phytx_abort_request_info.h new file mode 100644 index 0000000000000000000000000000000000000000..85b70949c5796f4a7afe5577e92f1ebadabfdfdd --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phytx_abort_request_info.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ +#define _PHYTX_ABORT_REQUEST_INFO_H_ + +#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 + +struct phytx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t phytx_abort_reason : 8, + user_number : 6, + reserved : 2; +#else + uint16_t reserved : 2, + user_number : 6, + phytx_abort_reason : 8; +#endif +}; + +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 + +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phytx_pkt_end.h b/drivers/staging/fw-api/hw/peach/v1/phytx_pkt_end.h new file mode 100644 index 0000000000000000000000000000000000000000..d055a48ac3d4bb4ce8cec6f28c7094d4ee2cc210 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phytx_pkt_end.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYTX_PKT_END_H_ +#define _PHYTX_PKT_END_H_ + +#define NUM_OF_WORDS_PHYTX_PKT_END 26 + +#define NUM_OF_DWORDS_PHYTX_PKT_END 13 + +struct phytx_pkt_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t start_of_frame_timestamp_15_0 : 16; + uint16_t start_of_frame_timestamp_31_16 : 16; + uint16_t end_of_frame_timestamp_15_0 : 16; + uint16_t end_of_frame_timestamp_31_16 : 16; + uint16_t tx_group_delay : 12, + timing_status : 2, + phyrx_entered_nap_state : 1, + dpdtrain_done : 1; + uint16_t transmit_delay : 16; + uint16_t tpc_dbg_info_cmn_15_0 : 16; + uint16_t tpc_dbg_info_cmn_31_16 : 16; + uint16_t tpc_dbg_info_cmn_47_32 : 16; + uint16_t tpc_dbg_info_chn1_15_0 : 16; + uint16_t tpc_dbg_info_chn1_31_16 : 16; + uint16_t tpc_dbg_info_chn1_47_32 : 16; + uint16_t tpc_dbg_info_chn1_63_48 : 16; + uint16_t tpc_dbg_info_chn1_79_64 : 16; + uint16_t tpc_dbg_info_chn2_15_0 : 16; + uint16_t tpc_dbg_info_chn2_31_16 : 16; + uint16_t tpc_dbg_info_chn2_47_32 : 16; + uint16_t tpc_dbg_info_chn2_63_48 : 16; + uint16_t tpc_dbg_info_chn2_79_64 : 16; + uint16_t phytx_tx_end_sw_info_15_0 : 16; + uint16_t phytx_tx_end_sw_info_31_16 : 16; + uint16_t phytx_tx_end_sw_info_47_32 : 16; + uint16_t phytx_tx_end_sw_info_63_48 : 16; + uint16_t beamform_masked_user_bitmap_15_0 : 16; + uint16_t beamform_masked_user_bitmap_31_16 : 16; + uint16_t beamform_masked_user_bitmap_36_32 : 5, + reserved_23 : 11; +#else + uint16_t start_of_frame_timestamp_15_0 : 16; + uint16_t start_of_frame_timestamp_31_16 : 16; + uint16_t end_of_frame_timestamp_15_0 : 16; + uint16_t end_of_frame_timestamp_31_16 : 16; + uint16_t dpdtrain_done : 1, + phyrx_entered_nap_state : 1, + timing_status : 2, + tx_group_delay : 12; + uint16_t transmit_delay : 16; + uint16_t tpc_dbg_info_cmn_15_0 : 16; + uint16_t tpc_dbg_info_cmn_31_16 : 16; + uint16_t tpc_dbg_info_cmn_47_32 : 16; + uint16_t tpc_dbg_info_chn1_15_0 : 16; + uint16_t tpc_dbg_info_chn1_31_16 : 16; + uint16_t tpc_dbg_info_chn1_47_32 : 16; + uint16_t tpc_dbg_info_chn1_63_48 : 16; + uint16_t tpc_dbg_info_chn1_79_64 : 16; + uint16_t tpc_dbg_info_chn2_15_0 : 16; + uint16_t tpc_dbg_info_chn2_31_16 : 16; + uint16_t tpc_dbg_info_chn2_47_32 : 16; + uint16_t tpc_dbg_info_chn2_63_48 : 16; + uint16_t tpc_dbg_info_chn2_79_64 : 16; + uint16_t phytx_tx_end_sw_info_15_0 : 16; + uint16_t phytx_tx_end_sw_info_31_16 : 16; + uint16_t phytx_tx_end_sw_info_47_32 : 16; + uint16_t phytx_tx_end_sw_info_63_48 : 16; + uint16_t beamform_masked_user_bitmap_15_0 : 16; + uint16_t beamform_masked_user_bitmap_31_16 : 16; + uint16_t reserved_23 : 11, + beamform_masked_user_bitmap_36_32 : 5; +#endif +}; + +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000000 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000002 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 0 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 15 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000004 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000006 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 0 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 15 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET 0x00000008 +#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB 0 +#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB 11 +#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK 0x00000fff + +#define PHYTX_PKT_END_TIMING_STATUS_OFFSET 0x00000008 +#define PHYTX_PKT_END_TIMING_STATUS_LSB 12 +#define PHYTX_PKT_END_TIMING_STATUS_MSB 13 +#define PHYTX_PKT_END_TIMING_STATUS_MASK 0x00003000 + +#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET 0x00000008 +#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB 14 +#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB 14 +#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK 0x00004000 + +#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET 0x00000008 +#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB 15 +#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB 15 +#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK 0x00008000 + +#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET 0x0000000a +#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB 0 +#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB 15 +#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000c +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000e +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET 0x00000010 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x00000012 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x00000014 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x00000016 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x00000018 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000001a +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000001c +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000001e +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x00000020 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x00000022 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x00000024 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff + +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x00000026 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x00000028 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB 0 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB 15 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000002a +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB 0 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB 15 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff + +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000002c +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB 0 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB 15 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0x0000ffff + +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000002e +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x00000030 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 0 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 15 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000032 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 0 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 4 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x0000001f + +#define PHYTX_PKT_END_RESERVED_23_OFFSET 0x00000032 +#define PHYTX_PKT_END_RESERVED_23_LSB 5 +#define PHYTX_PKT_END_RESERVED_23_MSB 15 +#define PHYTX_PKT_END_RESERVED_23_MASK 0x0000ffe0 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/phytx_ppdu_header_info_request.h b/drivers/staging/fw-api/hw/peach/v1/phytx_ppdu_header_info_request.h new file mode 100644 index 0000000000000000000000000000000000000000..c0d81901da8498b347a6ba6aa2fa99075c0454c3 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/phytx_ppdu_header_info_request.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ +#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ + +#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 + +#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 + +struct phytx_ppdu_header_info_request { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t request_type : 5, + reserved : 11; + uint16_t tlv32_padding : 16; +#else + uint16_t reserved : 11, + request_type : 5; + uint16_t tlv32_padding : 16; +#endif +}; + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/receive_pkt_start_info.h b/drivers/staging/fw-api/hw/peach/v1/receive_pkt_start_info.h new file mode 100644 index 0000000000000000000000000000000000000000..d1c935cc6e728a312bb328f04675be77ebe770ca --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/receive_pkt_start_info.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVE_PKT_START_INFO_H_ +#define _RECEIVE_PKT_START_INFO_H_ + +#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4 + +struct receive_pkt_start_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reception_type : 4, + rx_chain_mask_type : 1, + receive_bandwidth : 3, + rx_chain_mask : 8, + phy_ppdu_id : 16; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t preamble_time_to_rxframe : 8, + standalone_sniffer_mode : 1, + reserved_3a : 23; +#else + uint32_t phy_ppdu_id : 16, + rx_chain_mask : 8, + receive_bandwidth : 3, + rx_chain_mask_type : 1, + reception_type : 4; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t reserved_3a : 23, + standalone_sniffer_mode : 1, + preamble_time_to_rxframe : 8; +#endif +}; + +#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB 0 +#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB 3 +#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK 0x0000000f + +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB 4 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB 4 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK 0x00000010 + +#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB 5 +#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB 7 +#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK 0x000000e0 + +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB 8 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB 15 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK 0x0000ff00 + +#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB 16 +#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB 31 +#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK 0xffff0000 + +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c +#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB 0 +#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB 7 +#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff + +#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c +#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB 8 +#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB 8 +#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK 0x00000100 + +#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB 9 +#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB 31 +#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK 0xfffffe00 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/receive_rssi_info.h b/drivers/staging/fw-api/hw/peach/v1/receive_rssi_info.h new file mode 100644 index 0000000000000000000000000000000000000000..43fd1796f0eb4ba0e96a4066d5e471edc2697a00 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/receive_rssi_info.h @@ -0,0 +1,477 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVE_RSSI_INFO_H_ +#define _RECEIVE_RSSI_INFO_H_ + +#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 + +struct receive_rssi_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_pri20_chain0 : 8, + rssi_ext20_chain0 : 8, + rssi_ext40_low20_chain0 : 8, + rssi_ext40_high20_chain0 : 8; + uint32_t rssi_ext80_low20_chain0 : 8, + rssi_ext80_low_high20_chain0 : 8, + rssi_ext80_high_low20_chain0 : 8, + rssi_ext80_high20_chain0 : 8; + uint32_t rssi_ext160_0_chain0 : 8, + rssi_ext160_1_chain0 : 8, + rssi_ext160_2_chain0 : 8, + rssi_ext160_3_chain0 : 8; + uint32_t rssi_ext160_4_chain0 : 8, + rssi_ext160_5_chain0 : 8, + rssi_ext160_6_chain0 : 8, + rssi_ext160_7_chain0 : 8; + uint32_t rssi_pri20_chain1 : 8, + rssi_ext20_chain1 : 8, + rssi_ext40_low20_chain1 : 8, + rssi_ext40_high20_chain1 : 8; + uint32_t rssi_ext80_low20_chain1 : 8, + rssi_ext80_low_high20_chain1 : 8, + rssi_ext80_high_low20_chain1 : 8, + rssi_ext80_high20_chain1 : 8; + uint32_t rssi_ext160_0_chain1 : 8, + rssi_ext160_1_chain1 : 8, + rssi_ext160_2_chain1 : 8, + rssi_ext160_3_chain1 : 8; + uint32_t rssi_ext160_4_chain1 : 8, + rssi_ext160_5_chain1 : 8, + rssi_ext160_6_chain1 : 8, + rssi_ext160_7_chain1 : 8; + uint32_t rssi_pri20_chain2 : 8, + rssi_ext20_chain2 : 8, + rssi_ext40_low20_chain2 : 8, + rssi_ext40_high20_chain2 : 8; + uint32_t rssi_ext80_low20_chain2 : 8, + rssi_ext80_low_high20_chain2 : 8, + rssi_ext80_high_low20_chain2 : 8, + rssi_ext80_high20_chain2 : 8; + uint32_t rssi_ext160_0_chain2 : 8, + rssi_ext160_1_chain2 : 8, + rssi_ext160_2_chain2 : 8, + rssi_ext160_3_chain2 : 8; + uint32_t rssi_ext160_4_chain2 : 8, + rssi_ext160_5_chain2 : 8, + rssi_ext160_6_chain2 : 8, + rssi_ext160_7_chain2 : 8; + uint32_t rssi_pri20_chain3 : 8, + rssi_ext20_chain3 : 8, + rssi_ext40_low20_chain3 : 8, + rssi_ext40_high20_chain3 : 8; + uint32_t rssi_ext80_low20_chain3 : 8, + rssi_ext80_low_high20_chain3 : 8, + rssi_ext80_high_low20_chain3 : 8, + rssi_ext80_high20_chain3 : 8; + uint32_t rssi_ext160_0_chain3 : 8, + rssi_ext160_1_chain3 : 8, + rssi_ext160_2_chain3 : 8, + rssi_ext160_3_chain3 : 8; + uint32_t rssi_ext160_4_chain3 : 8, + rssi_ext160_5_chain3 : 8, + rssi_ext160_6_chain3 : 8, + rssi_ext160_7_chain3 : 8; +#else + uint32_t rssi_ext40_high20_chain0 : 8, + rssi_ext40_low20_chain0 : 8, + rssi_ext20_chain0 : 8, + rssi_pri20_chain0 : 8; + uint32_t rssi_ext80_high20_chain0 : 8, + rssi_ext80_high_low20_chain0 : 8, + rssi_ext80_low_high20_chain0 : 8, + rssi_ext80_low20_chain0 : 8; + uint32_t rssi_ext160_3_chain0 : 8, + rssi_ext160_2_chain0 : 8, + rssi_ext160_1_chain0 : 8, + rssi_ext160_0_chain0 : 8; + uint32_t rssi_ext160_7_chain0 : 8, + rssi_ext160_6_chain0 : 8, + rssi_ext160_5_chain0 : 8, + rssi_ext160_4_chain0 : 8; + uint32_t rssi_ext40_high20_chain1 : 8, + rssi_ext40_low20_chain1 : 8, + rssi_ext20_chain1 : 8, + rssi_pri20_chain1 : 8; + uint32_t rssi_ext80_high20_chain1 : 8, + rssi_ext80_high_low20_chain1 : 8, + rssi_ext80_low_high20_chain1 : 8, + rssi_ext80_low20_chain1 : 8; + uint32_t rssi_ext160_3_chain1 : 8, + rssi_ext160_2_chain1 : 8, + rssi_ext160_1_chain1 : 8, + rssi_ext160_0_chain1 : 8; + uint32_t rssi_ext160_7_chain1 : 8, + rssi_ext160_6_chain1 : 8, + rssi_ext160_5_chain1 : 8, + rssi_ext160_4_chain1 : 8; + uint32_t rssi_ext40_high20_chain2 : 8, + rssi_ext40_low20_chain2 : 8, + rssi_ext20_chain2 : 8, + rssi_pri20_chain2 : 8; + uint32_t rssi_ext80_high20_chain2 : 8, + rssi_ext80_high_low20_chain2 : 8, + rssi_ext80_low_high20_chain2 : 8, + rssi_ext80_low20_chain2 : 8; + uint32_t rssi_ext160_3_chain2 : 8, + rssi_ext160_2_chain2 : 8, + rssi_ext160_1_chain2 : 8, + rssi_ext160_0_chain2 : 8; + uint32_t rssi_ext160_7_chain2 : 8, + rssi_ext160_6_chain2 : 8, + rssi_ext160_5_chain2 : 8, + rssi_ext160_4_chain2 : 8; + uint32_t rssi_ext40_high20_chain3 : 8, + rssi_ext40_low20_chain3 : 8, + rssi_ext20_chain3 : 8, + rssi_pri20_chain3 : 8; + uint32_t rssi_ext80_high20_chain3 : 8, + rssi_ext80_high_low20_chain3 : 8, + rssi_ext80_low_high20_chain3 : 8, + rssi_ext80_low20_chain3 : 8; + uint32_t rssi_ext160_3_chain3 : 8, + rssi_ext160_2_chain3 : 8, + rssi_ext160_1_chain3 : 8, + rssi_ext160_0_chain3 : 8; + uint32_t rssi_ext160_7_chain3 : 8, + rssi_ext160_6_chain3 : 8, + rssi_ext160_5_chain3 : 8, + rssi_ext160_4_chain3 : 8; +#endif +}; + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/receive_user_info.h b/drivers/staging/fw-api/hw/peach/v1/receive_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..7ecc5e4232c4aa6c89eb77cc3423b8fcbd75a0c9 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/receive_user_info.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVE_USER_INFO_H_ +#define _RECEIVE_USER_INFO_H_ + +#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8 + +struct receive_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + user_rssi : 8, + pkt_type : 4, + stbc : 1, + reception_type : 3; + uint32_t rate_mcs : 4, + sgi : 2, + __reserved_g_0004 : 1, + reserved_1a : 1, + mimo_ss_bitmap : 8, + receive_bandwidth : 3, + reserved_1b : 5, + dl_ofdma_user_index : 8; + uint32_t dl_ofdma_content_channel : 1, + reserved_2a : 7, + nss : 3, + stream_offset : 3, + sta_dcm : 1, + ldpc : 1, + ru_type_80_0 : 4, + ru_type_80_1 : 4, + ru_type_80_2 : 4, + ru_type_80_3 : 4; + uint32_t ru_start_index_80_0 : 6, + reserved_3a : 2, + ru_start_index_80_1 : 6, + reserved_3b : 2, + ru_start_index_80_2 : 6, + reserved_3c : 2, + ru_start_index_80_3 : 6, + reserved_3d : 2; + uint32_t user_fd_rssi_seg0 : 32; + uint32_t user_fd_rssi_seg1 : 32; + uint32_t user_fd_rssi_seg2 : 32; + uint32_t user_fd_rssi_seg3 : 32; +#else + uint32_t reception_type : 3, + stbc : 1, + pkt_type : 4, + user_rssi : 8, + phy_ppdu_id : 16; + uint32_t dl_ofdma_user_index : 8, + reserved_1b : 5, + receive_bandwidth : 3, + mimo_ss_bitmap : 8, + reserved_1a : 1, + __reserved_g_0004 : 1, + sgi : 2, + rate_mcs : 4; + uint32_t ru_type_80_3 : 4, + ru_type_80_2 : 4, + ru_type_80_1 : 4, + ru_type_80_0 : 4, + ldpc : 1, + sta_dcm : 1, + stream_offset : 3, + nss : 3, + reserved_2a : 7, + dl_ofdma_content_channel : 1; + uint32_t reserved_3d : 2, + ru_start_index_80_3 : 6, + reserved_3c : 2, + ru_start_index_80_2 : 6, + reserved_3b : 2, + ru_start_index_80_1 : 6, + reserved_3a : 2, + ru_start_index_80_0 : 6; + uint32_t user_fd_rssi_seg0 : 32; + uint32_t user_fd_rssi_seg1 : 32; + uint32_t user_fd_rssi_seg2 : 32; + uint32_t user_fd_rssi_seg3 : 32; +#endif +}; + +#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_USER_RSSI_LSB 16 +#define RECEIVE_USER_INFO_USER_RSSI_MSB 23 +#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 + +#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 +#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 +#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 + +#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_STBC_LSB 28 +#define RECEIVE_USER_INFO_STBC_MSB 28 +#define RECEIVE_USER_INFO_STBC_MASK 0x10000000 + +#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 + +#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RATE_MCS_LSB 0 +#define RECEIVE_USER_INFO_RATE_MCS_MSB 3 +#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f + +#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_SGI_LSB 4 +#define RECEIVE_USER_INFO_SGI_MSB 5 +#define RECEIVE_USER_INFO_SGI_MASK 0x00000030 + +#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1A_LSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x00000080 + +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 + +#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 +#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 + +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 + +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 + +#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 +#define RECEIVE_USER_INFO_RESERVED_2A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe + +#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_NSS_LSB 8 +#define RECEIVE_USER_INFO_NSS_MSB 10 +#define RECEIVE_USER_INFO_NSS_MASK 0x00000700 + +#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 + +#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STA_DCM_LSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 + +#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_LDPC_LSB 15 +#define RECEIVE_USER_INFO_LDPC_MSB 15 +#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f + +#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 +#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 + +#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 +#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 +#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 + +#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 +#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 + +#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30 +#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 +#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000 + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/received_response_user_15_8.h b/drivers/staging/fw-api/hw/peach/v1/received_response_user_15_8.h new file mode 100644 index 0000000000000000000000000000000000000000..bce76aff2a0036b248ee4656183ec9a6d36ed84c --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/received_response_user_15_8.h @@ -0,0 +1,1126 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ +#define _RECEIVED_RESPONSE_USER_15_8_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 + +struct received_response_user_15_8 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#else + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#endif +}; + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/received_response_user_23_16.h b/drivers/staging/fw-api/hw/peach/v1/received_response_user_23_16.h new file mode 100644 index 0000000000000000000000000000000000000000..ccd2d9191078317c8d053cbb8f5931d1cef4ab61 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/received_response_user_23_16.h @@ -0,0 +1,1126 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ +#define _RECEIVED_RESPONSE_USER_23_16_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 + +struct received_response_user_23_16 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#else + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#endif +}; + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/received_response_user_31_24.h b/drivers/staging/fw-api/hw/peach/v1/received_response_user_31_24.h new file mode 100644 index 0000000000000000000000000000000000000000..81db62baa5daa9a978378908b9cbf76cc9aae283 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/received_response_user_31_24.h @@ -0,0 +1,1126 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ +#define _RECEIVED_RESPONSE_USER_31_24_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 + +struct received_response_user_31_24 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#else + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#endif +}; + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/received_response_user_36_32.h b/drivers/staging/fw-api/hw/peach/v1/received_response_user_36_32.h new file mode 100644 index 0000000000000000000000000000000000000000..9ba8ee5d23e25c399edebc4ef7b28224cd2ca8d8 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/received_response_user_36_32.h @@ -0,0 +1,715 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ +#define _RECEIVED_RESPONSE_USER_36_32_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 + +struct received_response_user_36_32 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#else + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#endif +}; + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/received_response_user_7_0.h b/drivers/staging/fw-api/hw/peach/v1/received_response_user_7_0.h new file mode 100644 index 0000000000000000000000000000000000000000..6b39f5cbea9db18609cadb14fdf12a6c745b6466 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/received_response_user_7_0.h @@ -0,0 +1,1126 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ +#define _RECEIVED_RESPONSE_USER_7_0_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 + +struct received_response_user_7_0 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#else + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#endif +}; + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/received_response_user_info.h b/drivers/staging/fw-api/hw/peach/v1/received_response_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..0f2676619a212057df049383bf77f767893ec513 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/received_response_user_info.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ +#define _RECEIVED_RESPONSE_USER_INFO_H_ + +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 + +struct received_response_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_fcs_pass_count : 12, + mpdu_fcs_fail_count : 12, + qosnull_frame_count : 4, + reserved_0a : 3, + user_info_valid : 1; + uint32_t null_delimiter_count : 22, + reserved_1a : 9, + ht_control_valid : 1; + uint32_t ht_control : 32; + uint32_t qos_control_valid : 16, + eosp : 16; + uint32_t qos_control_15_8_tid_0 : 8, + qos_control_15_8_tid_1 : 8, + qos_control_15_8_tid_2 : 8, + qos_control_15_8_tid_3 : 8; + uint32_t qos_control_15_8_tid_4 : 8, + qos_control_15_8_tid_5 : 8, + qos_control_15_8_tid_6 : 8, + qos_control_15_8_tid_7 : 8; + uint32_t qos_control_15_8_tid_8 : 8, + qos_control_15_8_tid_9 : 8, + qos_control_15_8_tid_10 : 8, + qos_control_15_8_tid_11 : 8; + uint32_t qos_control_15_8_tid_12 : 8, + qos_control_15_8_tid_13 : 8, + qos_control_15_8_tid_14 : 8, + qos_control_15_8_tid_15 : 8; +#else + uint32_t user_info_valid : 1, + reserved_0a : 3, + qosnull_frame_count : 4, + mpdu_fcs_fail_count : 12, + mpdu_fcs_pass_count : 12; + uint32_t ht_control_valid : 1, + reserved_1a : 9, + null_delimiter_count : 22; + uint32_t ht_control : 32; + uint32_t eosp : 16, + qos_control_valid : 16; + uint32_t qos_control_15_8_tid_3 : 8, + qos_control_15_8_tid_2 : 8, + qos_control_15_8_tid_1 : 8, + qos_control_15_8_tid_0 : 8; + uint32_t qos_control_15_8_tid_7 : 8, + qos_control_15_8_tid_6 : 8, + qos_control_15_8_tid_5 : 8, + qos_control_15_8_tid_4 : 8; + uint32_t qos_control_15_8_tid_11 : 8, + qos_control_15_8_tid_10 : 8, + qos_control_15_8_tid_9 : 8, + qos_control_15_8_tid_8 : 8; + uint32_t qos_control_15_8_tid_15 : 8, + qos_control_15_8_tid_14 : 8, + qos_control_15_8_tid_13 : 8, + qos_control_15_8_tid_12 : 8; +#endif +}; + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/received_trigger_info.h b/drivers/staging/fw-api/hw/peach/v1/received_trigger_info.h new file mode 100644 index 0000000000000000000000000000000000000000..965dce76fbc4645bf68402e979f2d367990e4071 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/received_trigger_info.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_TRIGGER_INFO_H_ +#define _RECEIVED_TRIGGER_INFO_H_ + +#include "received_trigger_info_details.h" +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 5 + +struct received_trigger_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_trigger_info_details received_trigger_details; +#else + struct received_trigger_info_details received_trigger_details; +#endif +}; + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB 29 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB 30 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 28 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0xf0000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0xffff0000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 25 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xfe000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x00000010 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/received_trigger_info_details.h b/drivers/staging/fw-api/hw/peach/v1/received_trigger_info_details.h new file mode 100644 index 0000000000000000000000000000000000000000..b162adf0d8bcb7dee8e31ba1f057d9f62d38f7ca --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/received_trigger_info_details.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ +#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ + +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5 + +struct received_trigger_info_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t trigger_type : 4, + ax_trigger_source : 1, + ax_trigger_type : 4, + trigger_source_sta_full_aid : 13, + frame_control_valid : 1, + qos_control_valid : 1, + he_control_info_valid : 1, + __reserved_g_0005_trigger_subtype : 4, + txop_sharing_mode : 2, + tid_aggregation_limit_is_zero : 1; + uint32_t phy_ppdu_id : 16, + lsig_response_length : 12, + reserved_1a : 4; + uint32_t frame_control : 16, + qos_control : 16; + uint32_t sw_peer_id : 16, + txop_sharing_allocation_duration : 9, + reserved_3a : 7; + uint32_t he_control : 32; +#else + uint32_t tid_aggregation_limit_is_zero : 1, + txop_sharing_mode : 2, + __reserved_g_0005_trigger_subtype : 4, + he_control_info_valid : 1, + qos_control_valid : 1, + frame_control_valid : 1, + trigger_source_sta_full_aid : 13, + ax_trigger_type : 4, + ax_trigger_source : 1, + trigger_type : 4; + uint32_t reserved_1a : 4, + lsig_response_length : 12, + phy_ppdu_id : 16; + uint32_t qos_control : 16, + frame_control : 16; + uint32_t reserved_3a : 7, + txop_sharing_allocation_duration : 9, + sw_peer_id : 16; + uint32_t he_control : 32; +#endif +}; + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 25 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xfe000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_descriptor_threshold_reached_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_descriptor_threshold_reached_status.h new file mode 100644 index 0000000000000000000000000000000000000000..6c63c1dc02971493f392fb92a20b16c3958c0aeb --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_descriptor_threshold_reached_status.h @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 27 + +struct reo_descriptor_threshold_reached_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t threshold_index : 2, + reserved_2 : 30; + uint32_t link_descriptor_counter0 : 24, + reserved_3 : 8; + uint32_t link_descriptor_counter1 : 24, + reserved_4 : 8; + uint32_t link_descriptor_counter2 : 24, + reserved_5 : 8; + uint32_t link_descriptor_counter_sum : 26, + reserved_6 : 6; + uint32_t reserved_7 : 32; + uint32_t reserved_8 : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 30, + threshold_index : 2; + uint32_t reserved_3 : 8, + link_descriptor_counter0 : 24; + uint32_t reserved_4 : 8, + link_descriptor_counter1 : 24; + uint32_t reserved_5 : 8, + link_descriptor_counter2 : 24; + uint32_t reserved_6 : 6, + link_descriptor_counter_sum : 26; + uint32_t reserved_7 : 32; + uint32_t reserved_8 : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x00000003 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0xfffffffc + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 23 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 23 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000001c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000001c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0xfc000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x00000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x00000024 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 27 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_destination_ring.h b/drivers/staging/fw-api/hw/peach/v1/reo_destination_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..fd54f690063dec08b3ba96fa481338ff5668813f --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_destination_ring.h @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_DESTINATION_RING_H_ +#define _REO_DESTINATION_RING_H_ + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_REO_DESTINATION_RING 8 + +struct reo_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reo_dest_buffer_type : 1, + reo_push_reason : 2, + reo_error_code : 5, + captured_msdu_data_size : 4, + sw_exception : 1, + src_link_id : 3, + reo_destination_struct_signature : 4, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t looping_count : 4, + ring_id : 8, + reo_destination_struct_signature : 4, + src_link_id : 3, + sw_exception : 1, + captured_msdu_data_size : 4, + reo_error_code : 5, + reo_push_reason : 2, + reo_dest_buffer_type : 1; +#endif +}; + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 + +#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 + +#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 + +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 + +#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 + +#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 +#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 +#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 + +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 + +#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_RING_ID_LSB 20 +#define REO_DESTINATION_RING_RING_ID_MSB 27 +#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + +#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_destination_ring_with_pn.h b/drivers/staging/fw-api/hw/peach/v1/reo_destination_ring_with_pn.h new file mode 100644 index 0000000000000000000000000000000000000000..b8e162a8ab3396baaa07b6dbb79703835aafff1e --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_destination_ring_with_pn.h @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_DESTINATION_RING_WITH_PN_H_ +#define _REO_DESTINATION_RING_WITH_PN_H_ + +#include "rx_msdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8 + +struct reo_destination_ring_with_pn { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_or_link_desc_addr_info; + uint32_t msdu_count : 8, + prev_pn_23_0 : 24; + uint32_t prev_pn_55_24 : 32; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reo_dest_buffer_type : 1, + reo_push_reason : 2, + reo_error_code : 5, + captured_msdu_data_size : 4, + sw_exception : 1, + src_link_id : 3, + reo_destination_struct_signature : 4, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_or_link_desc_addr_info; + uint32_t prev_pn_23_0 : 24, + msdu_count : 8; + uint32_t prev_pn_55_24 : 32; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t looping_count : 4, + ring_id : 8, + reo_destination_struct_signature : 4, + src_link_id : 3, + sw_exception : 1, + captured_msdu_data_size : 4, + reo_error_code : 5, + reo_push_reason : 2, + reo_dest_buffer_type : 1; +#endif +}; + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7 +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff + +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00 + +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_OFFSET 0x0000000c +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0 +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001 + +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1 +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2 +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006 + +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3 +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7 +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8 + +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8 +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11 +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 + +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12 +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12 +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000 + +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13 +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15 +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000 + +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 + +#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20 +#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27 +#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000 + +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_entrance_ring.h b/drivers/staging/fw-api/hw/peach/v1/reo_entrance_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..c9c9df2bd53a88a748cd6e99efe0019e20b41502 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_entrance_ring.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_ENTRANCE_RING_H_ +#define _REO_ENTRANCE_RING_H_ + +#include "rx_mpdu_details.h" +#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 + +struct reo_entrance_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + rounded_mpdu_byte_count : 14, + reo_destination_indication : 5, + frameless_bar : 1, + reserved_5a : 4; + uint32_t rxdma_push_reason : 2, + rxdma_error_code : 5, + mpdu_fragment_number : 4, + sw_exception : 1, + sw_exception_mpdu_delink : 1, + sw_exception_destination_ring_valid : 1, + sw_exception_destination_ring : 5, + mpdu_sequence_number : 12, + reserved_6a : 1; + uint32_t phy_ppdu_id : 16, + src_link_id : 3, + reserved_7a : 1, + ring_id : 8, + looping_count : 4; +#else + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_5a : 4, + frameless_bar : 1, + reo_destination_indication : 5, + rounded_mpdu_byte_count : 14, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t reserved_6a : 1, + mpdu_sequence_number : 12, + sw_exception_destination_ring : 5, + sw_exception_destination_ring_valid : 1, + sw_exception_mpdu_delink : 1, + sw_exception : 1, + mpdu_fragment_number : 4, + rxdma_error_code : 5, + rxdma_push_reason : 2; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 1, + src_link_id : 3, + phy_ppdu_id : 16; +#endif +}; + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 + +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 + +#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 + +#define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RESERVED_5A_LSB 28 +#define REO_ENTRANCE_RING_RESERVED_5A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000 + +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 + +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c + +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 + +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 + +#define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RESERVED_6A_LSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000 + +#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff + +#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 + +#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RESERVED_7A_LSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000 + +#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RING_ID_LSB 20 +#define REO_ENTRANCE_RING_RING_ID_MSB 27 +#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 + +#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_flush_cache.h b/drivers/staging/fw-api/hw/peach/v1/reo_flush_cache.h new file mode 100644 index 0000000000000000000000000000000000000000..1d6e09f51d6f6b8000a5d0137076c80ed9f3ebba --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_flush_cache.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_CACHE_H_ +#define _REO_FLUSH_CACHE_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9 + +struct reo_flush_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; + uint32_t flush_addr_39_32 : 8, + forward_all_mpdus_in_queue : 1, + release_cache_block_index : 1, + cache_block_resource_index : 2, + flush_without_invalidate : 1, + block_cache_usage_after_flush : 1, + flush_entire_cache : 1, + flush_queue_1k_desc : 1, + reserved_2b : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; + uint32_t reserved_2b : 16, + flush_queue_1k_desc : 1, + flush_entire_cache : 1, + block_cache_usage_after_flush : 1, + flush_without_invalidate : 1, + cache_block_resource_index : 2, + release_cache_block_index : 1, + forward_all_mpdus_in_queue : 1, + flush_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 0 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 31 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff + +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x000000ff + +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100 + +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200 + +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00 + +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000 + +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000 + +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x00004000 + +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x00008000 + +#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 +#define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_2B_MASK 0xffff0000 + +#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_3A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_5A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_7A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_flush_cache_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_flush_cache_status.h new file mode 100644 index 0000000000000000000000000000000000000000..6f2716362cd4f3d15a09dc67474ef8a19948c943 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_flush_cache_status.h @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_CACHE_STATUS_H_ +#define _REO_FLUSH_CACHE_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 27 + +struct reo_flush_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + block_error_details : 2, + reserved_2a : 5, + cache_controller_flush_status_hit : 1, + cache_controller_flush_status_desc_type : 3, + cache_controller_flush_status_client_id : 4, + cache_controller_flush_status_error : 2, + cache_controller_flush_count : 8, + flush_queue_1k_desc : 1, + reserved_2b : 5; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2b : 5, + flush_queue_1k_desc : 1, + cache_controller_flush_count : 8, + cache_controller_flush_status_error : 2, + cache_controller_flush_status_client_id : 4, + cache_controller_flush_status_desc_type : 3, + cache_controller_flush_status_hit : 1, + reserved_2a : 5, + block_error_details : 2, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x00000006 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x000000f8 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000 + +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x04000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0xf8000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 27 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 31 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_flush_queue.h b/drivers/staging/fw-api/hw/peach/v1/reo_flush_queue.h new file mode 100644 index 0000000000000000000000000000000000000000..701a8546d33a7a42877f17a608986694d84a956a --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_flush_queue.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_QUEUE_H_ +#define _REO_FLUSH_QUEUE_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9 + +struct reo_flush_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; + uint32_t flush_desc_addr_39_32 : 8, + block_desc_addr_usage_after_flush : 1, + block_resource_index : 2, + reserved_2a : 21; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; + uint32_t reserved_2a : 21, + block_resource_index : 2, + block_desc_addr_usage_after_flush : 1, + flush_desc_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 0 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 31 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100 + +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x00000600 + +#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 +#define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0xfffff800 + +#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_3A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_5A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_7A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_flush_queue_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_flush_queue_status.h new file mode 100644 index 0000000000000000000000000000000000000000..51490730c0588d07249b651a89aaefbac8730696 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_flush_queue_status.h @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_QUEUE_STATUS_H_ +#define _REO_FLUSH_QUEUE_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 27 + +struct reo_flush_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + reserved_2a : 31; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 31, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0xfffffffe + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 27 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_flush_timeout_list.h b/drivers/staging/fw-api/hw/peach/v1/reo_flush_timeout_list.h new file mode 100644 index 0000000000000000000000000000000000000000..02a307a3c18984c20eab208da1c4d01729b1047e --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_flush_timeout_list.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_H_ +#define _REO_FLUSH_TIMEOUT_LIST_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9 + +struct reo_flush_timeout_list { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t ac_timout_list : 2, + reserved_1 : 30; + uint32_t minimum_release_desc_count : 16, + minimum_forward_buf_count : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1 : 30, + ac_timout_list : 2; + uint32_t minimum_forward_buf_count : 16, + minimum_release_desc_count : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB 1 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK 0x00000003 + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK 0xfffffffc + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK 0xffff0000 + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_flush_timeout_list_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_flush_timeout_list_status.h new file mode 100644 index 0000000000000000000000000000000000000000..0bb7d402cd664e648e589a76fb59d734339c09e9 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_flush_timeout_list_status.h @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 27 + +struct reo_flush_timeout_list_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + timout_list_empty : 1, + reserved_2a : 30; + uint32_t release_desc_count : 16, + forward_buf_count : 16; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, + timout_list_empty : 1, + error_detected : 1; + uint32_t forward_buf_count : 16, + release_desc_count : 16; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x00000002 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0xfffffffc + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff0000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 27 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_get_queue_stats.h b/drivers/staging/fw-api/hw/peach/v1/reo_get_queue_stats.h new file mode 100644 index 0000000000000000000000000000000000000000..6fff523c04a5fe85232f40f7fded017e1afaf9f0 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_get_queue_stats.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_GET_QUEUE_STATS_H_ +#define _REO_GET_QUEUE_STATS_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9 + +struct reo_get_queue_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + clear_stats : 1, + reserved_2a : 23; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_2a : 23, + clear_stats : 1, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x00000100 + +#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0xfffffe00 + +#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_get_queue_stats_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_get_queue_stats_status.h new file mode 100644 index 0000000000000000000000000000000000000000..b80815d0d748fbbe002702d00870f5189f912c1a --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_get_queue_stats_status.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_GET_QUEUE_STATS_STATUS_H_ +#define _REO_GET_QUEUE_STATS_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 27 + +struct reo_get_queue_stats_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t ssn : 12, + current_index : 10, + reserved_2 : 10; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t window_jump_2k : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + hole_count : 16, + get_queue_1k_stats_status_to_follow : 1, + reserved_24a : 3; + uint32_t aging_drop_mpdu_count : 16, + aging_drop_interval : 8, + reserved_25a : 4, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 10, + current_index : 10, + ssn : 12; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_msdu_count : 25, + current_mpdu_count : 7; + uint32_t duplicate_count : 16, + forward_due_to_bar_count : 6, + timeout_count : 6, + window_jump_2k : 4; + uint32_t bar_received_count : 8, + frames_in_order_count : 24; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t reserved_24a : 3, + get_queue_1k_stats_status_to_follow : 1, + hole_count : 16, + late_receive_mpdu_count : 12; + uint32_t looping_count : 4, + reserved_25a : 4, + aging_drop_interval : 8, + aging_drop_mpdu_count : 16; +#endif +}; + +#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK 0x00000fff + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB 21 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK 0x003ff000 + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB 22 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK 0xffc00000 + +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET 0x00000028 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET 0x0000002c +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET 0x00000030 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET 0x00000034 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET 0x00000038 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET 0x0000003c +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET 0x00000040 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB 6 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK 0x0000007f + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB 7 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB 3 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK 0x0000000f + +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB 4 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB 9 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK 0x000003f0 + +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB 15 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK 0xffff0000 + +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000054 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB 23 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET 0x00000054 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK 0xff000000 + +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000058 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000064 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET 0x00000064 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK 0x0ffff000 + +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET 0x00000064 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK 0x10000000 + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB 29 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK 0xe0000000 + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_OFFSET 0x00000068 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MSB 15 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_OFFSET 0x00000068 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MSB 23 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MASK 0x00ff0000 + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK 0x0f000000 + +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_unblock_cache.h b/drivers/staging/fw-api/hw/peach/v1/reo_unblock_cache.h new file mode 100644 index 0000000000000000000000000000000000000000..b3dd68876515db4112c36510399aeb0d4caa7054 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_unblock_cache.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_UNBLOCK_CACHE_H_ +#define _REO_UNBLOCK_CACHE_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9 + +struct reo_unblock_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t unblock_type : 1, + cache_block_resource_index : 2, + reserved_1a : 29; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1a : 29, + cache_block_resource_index : 2, + unblock_type : 1; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 0 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 0 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x00000001 + +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 1 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 2 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000006 + +#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 3 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff8 + +#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_unblock_cache_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_unblock_cache_status.h new file mode 100644 index 0000000000000000000000000000000000000000..fe0de6cbb2825689672115fe6307fa5fd0476430 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_unblock_cache_status.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_UNBLOCK_CACHE_STATUS_H_ +#define _REO_UNBLOCK_CACHE_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 27 + +struct reo_unblock_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + unblock_type : 1, + reserved_2a : 30; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, + unblock_type : 1, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x00000001 + +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x00000002 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0xfffffffc + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 27 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_update_rx_reo_queue.h b/drivers/staging/fw-api/hw/peach/v1/reo_update_rx_reo_queue.h new file mode 100644 index 0000000000000000000000000000000000000000..3aefb3f39a92e7ccc2f95c69c4d78ff140846be6 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_update_rx_reo_queue.h @@ -0,0 +1,425 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_H_ +#define _REO_UPDATE_RX_REO_QUEUE_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9 + +struct reo_update_rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + update_receive_queue_number : 1, + update_vld : 1, + update_associated_link_descriptor_counter : 1, + update_disable_duplicate_detection : 1, + update_soft_reorder_enable : 1, + update_ac : 1, + update_bar : 1, + update_rty : 1, + update_chk_2k_mode : 1, + update_oor_mode : 1, + update_ba_window_size : 1, + update_pn_check_needed : 1, + update_pn_shall_be_even : 1, + update_pn_shall_be_uneven : 1, + update_pn_handling_enable : 1, + update_pn_size : 1, + update_ignore_ampdu_flag : 1, + update_svld : 1, + update_ssn : 1, + update_seq_2k_error_detected_flag : 1, + update_pn_error_detected_flag : 1, + update_pn_valid : 1, + update_pn : 1, + clear_stat_counters : 1; + uint32_t receive_queue_number : 16, + vld : 1, + associated_link_descriptor_counter : 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + ignore_ampdu_flag : 1; + uint32_t ba_window_size : 10, + pn_size : 2, + svld : 1, + ssn : 12, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + pn_valid : 1, + flush_from_cache : 1, + reserved_4a : 3; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t clear_stat_counters : 1, + update_pn : 1, + update_pn_valid : 1, + update_pn_error_detected_flag : 1, + update_seq_2k_error_detected_flag : 1, + update_ssn : 1, + update_svld : 1, + update_ignore_ampdu_flag : 1, + update_pn_size : 1, + update_pn_handling_enable : 1, + update_pn_shall_be_uneven : 1, + update_pn_shall_be_even : 1, + update_pn_check_needed : 1, + update_ba_window_size : 1, + update_oor_mode : 1, + update_chk_2k_mode : 1, + update_rty : 1, + update_bar : 1, + update_ac : 1, + update_soft_reorder_enable : 1, + update_disable_duplicate_detection : 1, + update_associated_link_descriptor_counter : 1, + update_vld : 1, + update_receive_queue_number : 1, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t ignore_ampdu_flag : 1, + pn_handling_enable : 1, + pn_shall_be_uneven : 1, + pn_shall_be_even : 1, + pn_check_needed : 1, + oor_mode : 1, + chk_2k_mode : 1, + rty : 1, + bar : 1, + ac : 2, + soft_reorder_enable : 1, + disable_duplicate_detection : 1, + associated_link_descriptor_counter : 2, + vld : 1, + receive_queue_number : 16; + uint32_t reserved_4a : 3, + flush_from_cache : 1, + pn_valid : 1, + pn_error_detected_flag : 1, + seq_2k_error_detected_flag : 1, + ssn : 12, + svld : 1, + pn_size : 2, + ba_window_size : 10; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; +#endif +}; + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x00000100 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x00000200 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x00001000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x00002000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x00004000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x00008000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x00020000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x00040000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x00080000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x00100000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x00200000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x00400000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x20000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x40000000 + +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x80000000 + +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 18 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000 + +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 19 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00080000 + +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 20 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00100000 + +#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_AC_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_AC_MSB 22 +#define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x00600000 + +#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 23 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 29 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x20000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 30 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x40000000 + +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x80000000 + +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x000003ff + +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x00000c00 + +#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x00001000 + +#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x01ffe000 + +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0xe0000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_update_rx_reo_queue_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_update_rx_reo_queue_status.h new file mode 100644 index 0000000000000000000000000000000000000000..9ec7efc6ad3a60be42880f45ff92d79535e5bc62 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/reo_update_rx_reo_queue_status.h @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 27 + +struct reo_update_rx_reo_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/response_end_status.h b/drivers/staging/fw-api/hw/peach/v1/response_end_status.h new file mode 100644 index 0000000000000000000000000000000000000000..600d007ce5727881a1f74b78cea7ca7c12af39db --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/response_end_status.h @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RESPONSE_END_STATUS_H_ +#define _RESPONSE_END_STATUS_H_ + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10 + +struct response_end_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t coex_bt_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_wlan_tx_while_wlan_tx : 1, + global_data_underflow_warning : 1, + response_transmit_status : 4, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + generated_response : 3, + mba_user_count : 7, + mba_fake_bitmap_count : 7, + coex_based_tx_bw : 3, + trig_response_related : 1, + reserved_0a : 1; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t cbf_segment_request_mask : 8, + cbf_segment_sent_mask : 8; + uint32_t underflow_mpdu_count : 9, + data_underflow_warning : 2, + reserved_2b : 10, + only_null_delim_sent : 1, + brp_info_valid : 1, + coex_uwb_tx_while_wlan_tx : 1, + coex_lte_tx_while_wlan_tx : 1, + reserved_2a : 7; + uint32_t mu_response_bitmap_31_0 : 32; + uint32_t mu_response_bitmap_36_32 : 5, + reserved_4a : 27; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t addr3_47_32 : 16, + __reserved_g_0005 : 1, + secure : 1, + __reserved_g_0005_ftm_frame_sent : 1, + reserved_20a : 13; +#else + uint32_t reserved_0a : 1, + trig_response_related : 1, + coex_based_tx_bw : 3, + mba_fake_bitmap_count : 7, + mba_user_count : 7, + generated_response : 3, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + response_transmit_status : 4, + global_data_underflow_warning : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_tx : 1; + uint32_t cbf_segment_sent_mask : 8, + cbf_segment_request_mask : 8; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t reserved_2a : 7, + coex_lte_tx_while_wlan_tx : 1, + coex_uwb_tx_while_wlan_tx : 1, + brp_info_valid : 1, + only_null_delim_sent : 1, + reserved_2b : 10, + data_underflow_warning : 2, + underflow_mpdu_count : 9; + uint32_t mu_response_bitmap_31_0 : 32; + uint32_t reserved_4a : 27, + mu_response_bitmap_36_32 : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t reserved_20a : 13, + __reserved_g_0005_ftm_frame_sent : 1, + secure : 1, + __reserved_g_0005 : 1, + addr3_47_32 : 16; +#endif +}; + +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x00000001 + +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x00000002 + +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x00000004 + +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x00000008 + +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x000000f0 + +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x00000100 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x00000200 + +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x00001c00 + +#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x000fe000 + +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x07f00000 + +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x38000000 + +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x40000000 + +#define RESPONSE_END_STATUS_RESERVED_0A_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_RESERVED_0A_LSB 31 +#define RESPONSE_END_STATUS_RESERVED_0A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_0A_MASK 0x80000000 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000 + +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 16 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 23 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff0000 + +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 24 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 31 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff000000 + +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x000001ff + +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x00000600 + +#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_RESERVED_2B_LSB 11 +#define RESPONSE_END_STATUS_RESERVED_2B_MSB 20 +#define RESPONSE_END_STATUS_RESERVED_2B_MASK 0x001ff800 + +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x00200000 + +#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x00400000 + +#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_LSB 23 +#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_MSB 23 +#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_MASK 0x00800000 + +#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_LSB 24 +#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_MSB 24 +#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_MASK 0x01000000 + +#define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_RESERVED_2A_LSB 25 +#define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_2A_MASK 0xfe000000 + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000c +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 0 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 31 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x00000010 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x0000001f + +#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x00000010 +#define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 +#define RESPONSE_END_STATUS_RESERVED_4A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0xffffffe0 + +#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x00000014 +#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 +#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0xffffffff + +#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x00000018 +#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 0 +#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 15 +#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff + +#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x00000018 +#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 16 +#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff0000 + +#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000001c +#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 +#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 +#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0xffffffff + +#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x00000020 +#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 0 +#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff + +#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x00000024 +#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 +#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 +#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x0000ffff + +#define RESPONSE_END_STATUS_SECURE_OFFSET 0x00000024 +#define RESPONSE_END_STATUS_SECURE_LSB 17 +#define RESPONSE_END_STATUS_SECURE_MSB 17 +#define RESPONSE_END_STATUS_SECURE_MASK 0x00020000 + +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x00000024 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x00040000 + +#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x00000024 +#define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 +#define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0xfff80000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/response_start_status.h b/drivers/staging/fw-api/hw/peach/v1/response_start_status.h new file mode 100644 index 0000000000000000000000000000000000000000..2b54ed1da7abf42d1bc27719f2b6b0c1b0edde61 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/response_start_status.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RESPONSE_START_STATUS_H_ +#define _RESPONSE_START_STATUS_H_ + +#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 + +struct response_start_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t generated_response : 3, + __reserved_g_0012 : 2, + trig_response_related : 1, + response_sta_count : 7, + reserved : 19; + uint32_t phy_ppdu_id : 16, + sw_peer_id : 16; +#else + uint32_t reserved : 19, + response_sta_count : 7, + trig_response_related : 1, + __reserved_g_0012 : 2, + generated_response : 3; + uint32_t sw_peer_id : 16, + phy_ppdu_id : 16; +#endif +}; + +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x00000000 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x00000007 + +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x00000000 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x00000020 + +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x00000000 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x00001fc0 + +#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x00000000 +#define RESPONSE_START_STATUS_RESERVED_LSB 13 +#define RESPONSE_START_STATUS_RESERVED_MSB 31 +#define RESPONSE_START_STATUS_RESERVED_MASK 0xffffe000 + +#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 0 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 15 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x00000004 +#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 16 +#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 31 +#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/ru_allocation_160_info.h b/drivers/staging/fw-api/hw/peach/v1/ru_allocation_160_info.h new file mode 100644 index 0000000000000000000000000000000000000000..3693e4ba64422f0ccecbea53204898979c1c0bf9 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/ru_allocation_160_info.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RU_ALLOCATION_160_INFO_H_ +#define _RU_ALLOCATION_160_INFO_H_ + +#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 + +struct ru_allocation_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation_band0_0 : 9, + ru_allocation_band0_1 : 9, + reserved_0a : 6, + ru_allocations_01_subband80_mask : 4, + ru_allocations_23_subband80_mask : 4; + uint32_t ru_allocation_band0_2 : 9, + ru_allocation_band0_3 : 9, + reserved_1a : 14; + uint32_t ru_allocation_band1_0 : 9, + ru_allocation_band1_1 : 9, + reserved_2a : 14; + uint32_t ru_allocation_band1_2 : 9, + ru_allocation_band1_3 : 9, + reserved_3a : 14; +#else + uint32_t ru_allocations_23_subband80_mask : 4, + ru_allocations_01_subband80_mask : 4, + reserved_0a : 6, + ru_allocation_band0_1 : 9, + ru_allocation_band0_0 : 9; + uint32_t reserved_1a : 14, + ru_allocation_band0_3 : 9, + ru_allocation_band0_2 : 9; + uint32_t reserved_2a : 14, + ru_allocation_band1_1 : 9, + ru_allocation_band1_0 : 9; + uint32_t reserved_3a : 14, + ru_allocation_band1_3 : 9, + ru_allocation_band1_2 : 9; +#endif +}; + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_attention.h b/drivers/staging/fw-api/hw/peach/v1/rx_attention.h new file mode 100644 index 0000000000000000000000000000000000000000..cafa2abe8ea7a5ee785116a4e722fb86003469cf --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_attention.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_ATTENTION_H_ +#define _RX_ATTENTION_H_ + +#define NUM_OF_DWORDS_RX_ATTENTION 3 + +struct rx_attention { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t first_mpdu : 1, + reserved_1a : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + a_msdu_error : 1, + fragment_flag : 1, + order : 1, + cce_match : 1, + overflow_err : 1, + msdu_length_err : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + sa_idx_invalid : 1, + da_idx_invalid : 1, + reserved_1b : 1, + rx_in_tx_decrypt_byp : 1, + encrypt_required : 1, + directed : 1, + buffer_fragment : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + fcs_err : 1; + uint32_t flow_idx_timeout : 1, + flow_idx_invalid : 1, + wifi_parser_error : 1, + amsdu_parser_error : 1, + sa_idx_timeout : 1, + da_idx_timeout : 1, + msdu_limit_error : 1, + da_is_valid : 1, + da_is_mcbc : 1, + sa_is_valid : 1, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_2 : 17, + msdu_done : 1; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t fcs_err : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + buffer_fragment : 1, + directed : 1, + encrypt_required : 1, + rx_in_tx_decrypt_byp : 1, + reserved_1b : 1, + da_idx_invalid : 1, + sa_idx_invalid : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + msdu_length_err : 1, + overflow_err : 1, + cce_match : 1, + order : 1, + fragment_flag : 1, + a_msdu_error : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + reserved_1a : 1, + first_mpdu : 1; + uint32_t msdu_done : 1, + reserved_2 : 17, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + sa_is_valid : 1, + da_is_mcbc : 1, + da_is_valid : 1, + msdu_limit_error : 1, + da_idx_timeout : 1, + sa_idx_timeout : 1, + amsdu_parser_error : 1, + wifi_parser_error : 1, + flow_idx_invalid : 1, + flow_idx_timeout : 1; +#endif +}; + +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_ATTENTION_RESERVED_0_OFFSET 0x00000000 +#define RX_ATTENTION_RESERVED_0_LSB 9 +#define RX_ATTENTION_RESERVED_0_MSB 15 +#define RX_ATTENTION_RESERVED_0_MASK 0x0000fe00 + +#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_ATTENTION_PHY_PPDU_ID_LSB 16 +#define RX_ATTENTION_PHY_PPDU_ID_MSB 31 +#define RX_ATTENTION_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x00000004 +#define RX_ATTENTION_FIRST_MPDU_LSB 0 +#define RX_ATTENTION_FIRST_MPDU_MSB 0 +#define RX_ATTENTION_FIRST_MPDU_MASK 0x00000001 + +#define RX_ATTENTION_RESERVED_1A_OFFSET 0x00000004 +#define RX_ATTENTION_RESERVED_1A_LSB 1 +#define RX_ATTENTION_RESERVED_1A_MSB 1 +#define RX_ATTENTION_RESERVED_1A_MASK 0x00000002 + +#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x00000004 +#define RX_ATTENTION_MCAST_BCAST_LSB 2 +#define RX_ATTENTION_MCAST_BCAST_MSB 2 +#define RX_ATTENTION_MCAST_BCAST_MASK 0x00000004 + +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x00000004 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 3 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x00000008 + +#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x00000004 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 4 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 4 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x00000010 + +#define RX_ATTENTION_POWER_MGMT_OFFSET 0x00000004 +#define RX_ATTENTION_POWER_MGMT_LSB 5 +#define RX_ATTENTION_POWER_MGMT_MSB 5 +#define RX_ATTENTION_POWER_MGMT_MASK 0x00000020 + +#define RX_ATTENTION_NON_QOS_OFFSET 0x00000004 +#define RX_ATTENTION_NON_QOS_LSB 6 +#define RX_ATTENTION_NON_QOS_MSB 6 +#define RX_ATTENTION_NON_QOS_MASK 0x00000040 + +#define RX_ATTENTION_NULL_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_NULL_DATA_LSB 7 +#define RX_ATTENTION_NULL_DATA_MSB 7 +#define RX_ATTENTION_NULL_DATA_MASK 0x00000080 + +#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_MGMT_TYPE_LSB 8 +#define RX_ATTENTION_MGMT_TYPE_MSB 8 +#define RX_ATTENTION_MGMT_TYPE_MASK 0x00000100 + +#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_CTRL_TYPE_LSB 9 +#define RX_ATTENTION_CTRL_TYPE_MSB 9 +#define RX_ATTENTION_CTRL_TYPE_MASK 0x00000200 + +#define RX_ATTENTION_MORE_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_MORE_DATA_LSB 10 +#define RX_ATTENTION_MORE_DATA_MSB 10 +#define RX_ATTENTION_MORE_DATA_MASK 0x00000400 + +#define RX_ATTENTION_EOSP_OFFSET 0x00000004 +#define RX_ATTENTION_EOSP_LSB 11 +#define RX_ATTENTION_EOSP_MSB 11 +#define RX_ATTENTION_EOSP_MASK 0x00000800 + +#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x00000004 +#define RX_ATTENTION_A_MSDU_ERROR_LSB 12 +#define RX_ATTENTION_A_MSDU_ERROR_MSB 12 +#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x00001000 + +#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x00000004 +#define RX_ATTENTION_FRAGMENT_FLAG_LSB 13 +#define RX_ATTENTION_FRAGMENT_FLAG_MSB 13 +#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x00002000 + +#define RX_ATTENTION_ORDER_OFFSET 0x00000004 +#define RX_ATTENTION_ORDER_LSB 14 +#define RX_ATTENTION_ORDER_MSB 14 +#define RX_ATTENTION_ORDER_MASK 0x00004000 + +#define RX_ATTENTION_CCE_MATCH_OFFSET 0x00000004 +#define RX_ATTENTION_CCE_MATCH_LSB 15 +#define RX_ATTENTION_CCE_MATCH_MSB 15 +#define RX_ATTENTION_CCE_MATCH_MASK 0x00008000 + +#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_OVERFLOW_ERR_LSB 16 +#define RX_ATTENTION_OVERFLOW_ERR_MSB 16 +#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x00010000 + +#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 17 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 17 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x00020000 + +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 18 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 + +#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 19 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 19 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x00080000 + +#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_SA_IDX_INVALID_LSB 20 +#define RX_ATTENTION_SA_IDX_INVALID_MSB 20 +#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x00100000 + +#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_DA_IDX_INVALID_LSB 21 +#define RX_ATTENTION_DA_IDX_INVALID_MSB 21 +#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x00200000 + +#define RX_ATTENTION_RESERVED_1B_OFFSET 0x00000004 +#define RX_ATTENTION_RESERVED_1B_LSB 22 +#define RX_ATTENTION_RESERVED_1B_MSB 22 +#define RX_ATTENTION_RESERVED_1B_MASK 0x00400000 + +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 23 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 + +#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x00000004 +#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 24 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 24 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x01000000 + +#define RX_ATTENTION_DIRECTED_OFFSET 0x00000004 +#define RX_ATTENTION_DIRECTED_LSB 25 +#define RX_ATTENTION_DIRECTED_MSB 25 +#define RX_ATTENTION_DIRECTED_MASK 0x02000000 + +#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x00000004 +#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 26 +#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 26 +#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x04000000 + +#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 27 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 27 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x08000000 + +#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_TKIP_MIC_ERR_LSB 28 +#define RX_ATTENTION_TKIP_MIC_ERR_MSB 28 +#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x10000000 + +#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_DECRYPT_ERR_LSB 29 +#define RX_ATTENTION_DECRYPT_ERR_MSB 29 +#define RX_ATTENTION_DECRYPT_ERR_MASK 0x20000000 + +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 30 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 + +#define RX_ATTENTION_FCS_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_FCS_ERR_LSB 31 +#define RX_ATTENTION_FCS_ERR_MSB 31 +#define RX_ATTENTION_FCS_ERR_MASK 0x80000000 + +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x00000001 + +#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x00000008 +#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x00000002 + +#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x00000004 + +#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x00000008 + +#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x00000010 + +#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x00000020 + +#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x00000040 + +#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_DA_IS_VALID_LSB 7 +#define RX_ATTENTION_DA_IS_VALID_MSB 7 +#define RX_ATTENTION_DA_IS_VALID_MASK 0x00000080 + +#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_ATTENTION_DA_IS_MCBC_LSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MASK 0x00000100 + +#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_SA_IS_VALID_LSB 9 +#define RX_ATTENTION_SA_IS_VALID_MSB 9 +#define RX_ATTENTION_SA_IS_VALID_MASK 0x00000200 + +#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x00000008 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x00001c00 + +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 + +#define RX_ATTENTION_RESERVED_2_OFFSET 0x00000008 +#define RX_ATTENTION_RESERVED_2_LSB 14 +#define RX_ATTENTION_RESERVED_2_MSB 30 +#define RX_ATTENTION_RESERVED_2_MASK 0x7fffc000 + +#define RX_ATTENTION_MSDU_DONE_OFFSET 0x00000008 +#define RX_ATTENTION_MSDU_DONE_LSB 31 +#define RX_ATTENTION_MSDU_DONE_MSB 31 +#define RX_ATTENTION_MSDU_DONE_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/peach/v1/rx_flow_search_entry.h new file mode 100644 index 0000000000000000000000000000000000000000..adcae02a8492a04a5e2232955263b240e160a944 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_flow_search_entry.h @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_FLOW_SEARCH_ENTRY_H_ +#define _RX_FLOW_SEARCH_ENTRY_H_ + +#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 + +struct rx_flow_search_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_ip_127_96 : 32; + uint32_t src_ip_95_64 : 32; + uint32_t src_ip_63_32 : 32; + uint32_t src_ip_31_0 : 32; + uint32_t dest_ip_127_96 : 32; + uint32_t dest_ip_95_64 : 32; + uint32_t dest_ip_63_32 : 32; + uint32_t dest_ip_31_0 : 32; + uint32_t src_port : 16, + dest_port : 16; + uint32_t l4_protocol : 8, + valid : 1, + reserved_9 : 4, + service_code : 9, + priority_valid : 1, + use_ppe : 1, + reo_destination_indication : 5, + msdu_drop : 1, + reo_destination_handler : 2; + uint32_t metadata : 32; + uint32_t aggregation_count : 7, + lro_eligible : 1, + msdu_count : 24; + uint32_t msdu_byte_count : 32; + uint32_t timestamp : 32; + uint32_t cumulative_ip_length_pmac1 : 16, + cumulative_ip_length : 16; + uint32_t tcp_sequence_number : 32; +#else + uint32_t src_ip_127_96 : 32; + uint32_t src_ip_95_64 : 32; + uint32_t src_ip_63_32 : 32; + uint32_t src_ip_31_0 : 32; + uint32_t dest_ip_127_96 : 32; + uint32_t dest_ip_95_64 : 32; + uint32_t dest_ip_63_32 : 32; + uint32_t dest_ip_31_0 : 32; + uint32_t dest_port : 16, + src_port : 16; + uint32_t reo_destination_handler : 2, + msdu_drop : 1, + reo_destination_indication : 5, + use_ppe : 1, + priority_valid : 1, + service_code : 9, + reserved_9 : 4, + valid : 1, + l4_protocol : 8; + uint32_t metadata : 32; + uint32_t msdu_count : 24, + lro_eligible : 1, + aggregation_count : 7; + uint32_t msdu_byte_count : 32; + uint32_t timestamp : 32; + uint32_t cumulative_ip_length : 16, + cumulative_ip_length_pmac1 : 16; + uint32_t tcp_sequence_number : 32; +#endif +}; + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff + +#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 + +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 + +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 + +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 + +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 + +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 + +#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 +#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f + +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 + +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 + +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_frame_1k_bitmap_ack.h b/drivers/staging/fw-api/hw/peach/v1/rx_frame_1k_bitmap_ack.h new file mode 100644 index 0000000000000000000000000000000000000000..2698e5b0a5420e5e16b2b10d8450e9ed1a360cdc --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_frame_1k_bitmap_ack.h @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ +#define _RX_FRAME_1K_BITMAP_ACK_H_ + +#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 37 + +struct rx_frame_1k_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 5, + ba_bitmap_size : 2, + reserved_0b : 3, + ba_tid : 4, + sta_full_aid : 13, + reserved_0c : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_ctrl : 16, + ba_ts_seq : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t ba_ts_bitmap_287_256 : 32; + uint32_t ba_ts_bitmap_319_288 : 32; + uint32_t ba_ts_bitmap_351_320 : 32; + uint32_t ba_ts_bitmap_383_352 : 32; + uint32_t ba_ts_bitmap_415_384 : 32; + uint32_t ba_ts_bitmap_447_416 : 32; + uint32_t ba_ts_bitmap_479_448 : 32; + uint32_t ba_ts_bitmap_511_480 : 32; + uint32_t ba_ts_bitmap_543_512 : 32; + uint32_t ba_ts_bitmap_575_544 : 32; + uint32_t ba_ts_bitmap_607_576 : 32; + uint32_t ba_ts_bitmap_639_608 : 32; + uint32_t ba_ts_bitmap_671_640 : 32; + uint32_t ba_ts_bitmap_703_672 : 32; + uint32_t ba_ts_bitmap_735_704 : 32; + uint32_t ba_ts_bitmap_767_736 : 32; + uint32_t ba_ts_bitmap_799_768 : 32; + uint32_t ba_ts_bitmap_831_800 : 32; + uint32_t ba_ts_bitmap_863_832 : 32; + uint32_t ba_ts_bitmap_895_864 : 32; + uint32_t ba_ts_bitmap_927_896 : 32; + uint32_t ba_ts_bitmap_959_928 : 32; + uint32_t ba_ts_bitmap_991_960 : 32; + uint32_t ba_ts_bitmap_1023_992 : 32; +#else + uint32_t reserved_0c : 5, + sta_full_aid : 13, + ba_tid : 4, + reserved_0b : 3, + ba_bitmap_size : 2, + reserved_0a : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_seq : 16, + ba_ts_ctrl : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t ba_ts_bitmap_287_256 : 32; + uint32_t ba_ts_bitmap_319_288 : 32; + uint32_t ba_ts_bitmap_351_320 : 32; + uint32_t ba_ts_bitmap_383_352 : 32; + uint32_t ba_ts_bitmap_415_384 : 32; + uint32_t ba_ts_bitmap_447_416 : 32; + uint32_t ba_ts_bitmap_479_448 : 32; + uint32_t ba_ts_bitmap_511_480 : 32; + uint32_t ba_ts_bitmap_543_512 : 32; + uint32_t ba_ts_bitmap_575_544 : 32; + uint32_t ba_ts_bitmap_607_576 : 32; + uint32_t ba_ts_bitmap_639_608 : 32; + uint32_t ba_ts_bitmap_671_640 : 32; + uint32_t ba_ts_bitmap_703_672 : 32; + uint32_t ba_ts_bitmap_735_704 : 32; + uint32_t ba_ts_bitmap_767_736 : 32; + uint32_t ba_ts_bitmap_799_768 : 32; + uint32_t ba_ts_bitmap_831_800 : 32; + uint32_t ba_ts_bitmap_863_832 : 32; + uint32_t ba_ts_bitmap_895_864 : 32; + uint32_t ba_ts_bitmap_927_896 : 32; + uint32_t ba_ts_bitmap_959_928 : 32; + uint32_t ba_ts_bitmap_991_960 : 32; + uint32_t ba_ts_bitmap_1023_992 : 32; +#endif +}; + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x0000001f + +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x00000060 + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x00000380 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x00003c00 + +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x07ffc000 + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0xf8000000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x00000004 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x00000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x00000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0xffff0000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000c +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x00000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x00000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff0000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x00000014 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x00000018 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000001c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x00000020 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x00000024 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x00000028 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000002c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x00000030 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x00000034 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x00000038 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000003c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x00000040 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x00000044 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x00000048 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000004c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x00000050 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x00000054 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x00000058 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000005c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x00000060 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x00000064 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x00000068 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000006c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x00000070 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x00000074 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x00000078 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000007c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x00000080 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x00000084 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x00000088 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000008c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x00000090 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_frame_bitmap_ack.h b/drivers/staging/fw-api/hw/peach/v1/rx_frame_bitmap_ack.h new file mode 100644 index 0000000000000000000000000000000000000000..c9db51691c319f7ca08d98610d2a0a861742a115 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_frame_bitmap_ack.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_FRAME_BITMAP_ACK_H_ +#define _RX_FRAME_BITMAP_ACK_H_ + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 13 + +struct rx_frame_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_bitmap_available : 1, + explicit_ack : 1, + explict_ack_type : 3, + ba_bitmap_size : 2, + reserved_0a : 3, + ba_tid : 4, + sta_full_aid : 13, + reserved_0b : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_ctrl : 16, + ba_ts_seq : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; +#else + uint32_t reserved_0b : 5, + sta_full_aid : 13, + ba_tid : 4, + reserved_0a : 3, + ba_bitmap_size : 2, + explict_ack_type : 3, + explicit_ack : 1, + no_bitmap_available : 1; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_seq : 16, + ba_ts_ctrl : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; +#endif +}; + +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x00000001 + +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x00000002 + +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x0000001c + +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x00000060 + +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x00000380 + +#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x00003c00 + +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x07ffc000 + +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0xf8000000 + +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x00000004 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x00000008 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff + +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x00000008 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0xffff0000 + +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000c +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x00000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x00000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff0000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x00000014 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x00000018 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000001c +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x00000020 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x00000024 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x00000028 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000002c +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x00000030 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_frame_bitmap_req.h b/drivers/staging/fw-api/hw/peach/v1/rx_frame_bitmap_req.h new file mode 100644 index 0000000000000000000000000000000000000000..160de339bdf63cdba53c52621ac767394f77fba5 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_frame_bitmap_req.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_FRAME_BITMAP_REQ_H_ +#define _RX_FRAME_BITMAP_REQ_H_ + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 1 + +struct rx_frame_bitmap_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t explicit_user_request : 1, + user_request_type : 1, + user_number : 6, + sw_peer_id : 16, + tid_specific_request : 1, + requested_tid : 4, + reserved_0 : 3; +#else + uint32_t reserved_0 : 3, + requested_tid : 4, + tid_specific_request : 1, + sw_peer_id : 16, + user_number : 6, + user_request_type : 1, + explicit_user_request : 1; +#endif +}; + +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x00000001 + +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x00000002 + +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x000000fc + +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x00ffff00 + +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x01000000 + +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x1e000000 + +#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_location_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_location_info.h new file mode 100644 index 0000000000000000000000000000000000000000..77089c7cf312f960e120231fd28878ffccfe6e9d --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_location_info.h @@ -0,0 +1,470 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_LOCATION_INFO_H_ +#define _RX_LOCATION_INFO_H_ + +#define NUM_OF_DWORDS_RX_LOCATION_INFO 28 + +struct rx_location_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_location_info_valid : 1, + rtt_hw_ifft_mode : 1, + rtt_11az_mode : 2, + reserved_0 : 4, + rtt_num_fac : 8, + rtt_rx_chain_mask : 8, + rtt_num_streams : 8; + uint32_t rtt_first_selected_chain : 8, + rtt_second_selected_chain : 8, + rtt_cfr_status : 8, + rtt_cir_status : 8; + uint32_t rtt_che_buffer_pointer_low32 : 32; + uint32_t rtt_che_buffer_pointer_high8 : 8, + reserved_3 : 8, + rtt_pkt_bw_vht : 4, + rtt_pkt_bw_leg : 4, + rtt_mcs_rate : 8; + uint32_t rtt_cfo_measurement : 16, + rtt_preamble_type : 8, + rtt_gi_type : 8; + uint32_t rx_start_ts : 32; + uint32_t rx_start_ts_upper : 32; + uint32_t rx_end_ts : 32; + uint32_t gain_chain0 : 16, + gain_chain1 : 16; + uint32_t gain_chain2 : 16, + gain_chain3 : 16; + uint32_t gain_report_status : 8, + rtt_timing_backoff_sel : 8, + rtt_fac_combined : 16; + uint32_t rtt_fac_0 : 16, + rtt_fac_1 : 16; + uint32_t rtt_fac_2 : 16, + rtt_fac_3 : 16; + uint32_t rtt_fac_4 : 16, + rtt_fac_5 : 16; + uint32_t rtt_fac_6 : 16, + rtt_fac_7 : 16; + uint32_t rtt_fac_8 : 16, + rtt_fac_9 : 16; + uint32_t rtt_fac_10 : 16, + rtt_fac_11 : 16; + uint32_t rtt_fac_12 : 16, + rtt_fac_13 : 16; + uint32_t rtt_fac_14 : 16, + rtt_fac_15 : 16; + uint32_t rtt_fac_16 : 16, + rtt_fac_17 : 16; + uint32_t rtt_fac_18 : 16, + rtt_fac_19 : 16; + uint32_t rtt_fac_20 : 16, + rtt_fac_21 : 16; + uint32_t rtt_fac_22 : 16, + rtt_fac_23 : 16; + uint32_t rtt_fac_24 : 16, + rtt_fac_25 : 16; + uint32_t rtt_fac_26 : 16, + rtt_fac_27 : 16; + uint32_t rtt_fac_28 : 16, + rtt_fac_29 : 16; + uint32_t rtt_fac_30 : 16, + rtt_fac_31 : 16; + uint32_t reserved_27a : 32; +#else + uint32_t rtt_num_streams : 8, + rtt_rx_chain_mask : 8, + rtt_num_fac : 8, + reserved_0 : 4, + rtt_11az_mode : 2, + rtt_hw_ifft_mode : 1, + rx_location_info_valid : 1; + uint32_t rtt_cir_status : 8, + rtt_cfr_status : 8, + rtt_second_selected_chain : 8, + rtt_first_selected_chain : 8; + uint32_t rtt_che_buffer_pointer_low32 : 32; + uint32_t rtt_mcs_rate : 8, + rtt_pkt_bw_leg : 4, + rtt_pkt_bw_vht : 4, + reserved_3 : 8, + rtt_che_buffer_pointer_high8 : 8; + uint32_t rtt_gi_type : 8, + rtt_preamble_type : 8, + rtt_cfo_measurement : 16; + uint32_t rx_start_ts : 32; + uint32_t rx_start_ts_upper : 32; + uint32_t rx_end_ts : 32; + uint32_t gain_chain1 : 16, + gain_chain0 : 16; + uint32_t gain_chain3 : 16, + gain_chain2 : 16; + uint32_t rtt_fac_combined : 16, + rtt_timing_backoff_sel : 8, + gain_report_status : 8; + uint32_t rtt_fac_1 : 16, + rtt_fac_0 : 16; + uint32_t rtt_fac_3 : 16, + rtt_fac_2 : 16; + uint32_t rtt_fac_5 : 16, + rtt_fac_4 : 16; + uint32_t rtt_fac_7 : 16, + rtt_fac_6 : 16; + uint32_t rtt_fac_9 : 16, + rtt_fac_8 : 16; + uint32_t rtt_fac_11 : 16, + rtt_fac_10 : 16; + uint32_t rtt_fac_13 : 16, + rtt_fac_12 : 16; + uint32_t rtt_fac_15 : 16, + rtt_fac_14 : 16; + uint32_t rtt_fac_17 : 16, + rtt_fac_16 : 16; + uint32_t rtt_fac_19 : 16, + rtt_fac_18 : 16; + uint32_t rtt_fac_21 : 16, + rtt_fac_20 : 16; + uint32_t rtt_fac_23 : 16, + rtt_fac_22 : 16; + uint32_t rtt_fac_25 : 16, + rtt_fac_24 : 16; + uint32_t rtt_fac_27 : 16, + rtt_fac_26 : 16; + uint32_t rtt_fac_29 : 16, + rtt_fac_28 : 16; + uint32_t rtt_fac_31 : 16, + rtt_fac_30 : 16; + uint32_t reserved_27a : 32; +#endif +}; + +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001 + +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002 + +#define RX_LOCATION_INFO_RTT_11AZ_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_LSB 2 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MSB 3 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MASK 0x0000000c + +#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RESERVED_0_LSB 4 +#define RX_LOCATION_INFO_RESERVED_0_MSB 7 +#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0 + +#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 + +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000 + +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff + +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000 + +#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000 + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff + +#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RESERVED_3_LSB 8 +#define RX_LOCATION_INFO_RESERVED_3_MSB 15 +#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000 + +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000 + +#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000 + +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 + +#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000 + +#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014 +#define RX_LOCATION_INFO_RX_START_TS_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff + +#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c +#define RX_LOCATION_INFO_RX_END_TS_LSB 0 +#define RX_LOCATION_INFO_RX_END_TS_MSB 31 +#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff + +#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000 + +#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff + +#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000 + +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff + +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_LOCATION_INFO_RESERVED_27A_LSB 0 +#define RX_LOCATION_INFO_RESERVED_27A_MSB 31 +#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_desc_info.h new file mode 100644 index 0000000000000000000000000000000000000000..c88ba6a17199cd5bc1d57512c8cbb0f4bb23e47e --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_desc_info.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_DESC_INFO_H_ +#define _RX_MPDU_DESC_INFO_H_ + +#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 + +struct rx_mpdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_count : 8, + fragment_flag : 1, + mpdu_retry_bit : 1, + ampdu_flag : 1, + bar_frame : 1, + pn_fields_contain_valid_info : 1, + raw_mpdu : 1, + more_fragment_flag : 1, + src_info : 12, + mpdu_qos_control_valid : 1, + tid : 4; + uint32_t peer_meta_data : 32; +#else + uint32_t tid : 4, + mpdu_qos_control_valid : 1, + src_info : 12, + more_fragment_flag : 1, + raw_mpdu : 1, + pn_fields_contain_valid_info : 1, + bar_frame : 1, + ampdu_flag : 1, + mpdu_retry_bit : 1, + fragment_flag : 1, + msdu_count : 8; + uint32_t peer_meta_data : 32; +#endif +}; + +#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 + +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 + +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 + +#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 + +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 + +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 +#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 +#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 + +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_TID_LSB 28 +#define RX_MPDU_DESC_INFO_TID_MSB 31 +#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 + +#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_details.h b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_details.h new file mode 100644 index 0000000000000000000000000000000000000000..9c909a87e2c11ec028182b17899363948d325793 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_details.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_DETAILS_H_ +#define _RX_MPDU_DETAILS_H_ + +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 + +struct rx_mpdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#else + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#endif +}; + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_end.h b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_end.h new file mode 100644 index 0000000000000000000000000000000000000000..26824a03ee3a2df9c53b05c0f9a9dea404852ae5 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_end.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_END_H_ +#define _RX_MPDU_END_H_ + +#define NUM_OF_DWORDS_RX_MPDU_END 4 + +struct rx_mpdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t reserved_1a : 11, + unsup_ktype_short_frame : 1, + rx_in_tx_decrypt_byp : 1, + overflow_err : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + pn_fields_contain_valid_info : 1, + fcs_err : 1, + msdu_length_err : 1, + rxdma0_destination_ring : 3, + rxdma1_destination_ring : 3, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_1b : 1; + uint32_t reserved_2a : 15, + rxpcu_mgmt_sequence_nr_valid : 1, + rxpcu_mgmt_sequence_nr : 16; + uint32_t __reserved_g_0002 : 32; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_1b : 1, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + rxdma1_destination_ring : 3, + rxdma0_destination_ring : 3, + msdu_length_err : 1, + fcs_err : 1, + pn_fields_contain_valid_info : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + overflow_err : 1, + rx_in_tx_decrypt_byp : 1, + unsup_ktype_short_frame : 1, + reserved_1a : 11; + uint32_t rxpcu_mgmt_sequence_nr : 16, + rxpcu_mgmt_sequence_nr_valid : 1, + reserved_2a : 15; + uint32_t __reserved_g_0002 : 32; +#endif +}; + +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_END_RESERVED_0_OFFSET 0x00000000 +#define RX_MPDU_END_RESERVED_0_LSB 9 +#define RX_MPDU_END_RESERVED_0_MSB 15 +#define RX_MPDU_END_RESERVED_0_MASK 0x0000fe00 + +#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MPDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_END_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_END_RESERVED_1A_OFFSET 0x00000004 +#define RX_MPDU_END_RESERVED_1A_LSB 0 +#define RX_MPDU_END_RESERVED_1A_MSB 10 +#define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff + +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 11 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 11 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 + +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 12 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 12 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 + +#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_OVERFLOW_ERR_LSB 13 +#define RX_MPDU_END_OVERFLOW_ERR_MSB 13 +#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x00002000 + +#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 14 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 14 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x00004000 + +#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_TKIP_MIC_ERR_LSB 15 +#define RX_MPDU_END_TKIP_MIC_ERR_MSB 15 +#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x00008000 + +#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_DECRYPT_ERR_LSB 16 +#define RX_MPDU_END_DECRYPT_ERR_MSB 16 +#define RX_MPDU_END_DECRYPT_ERR_MASK 0x00010000 + +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 17 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 17 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 + +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 18 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 + +#define RX_MPDU_END_FCS_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_FCS_ERR_LSB 19 +#define RX_MPDU_END_FCS_ERR_MSB 19 +#define RX_MPDU_END_FCS_ERR_MASK 0x00080000 + +#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 20 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 20 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x00100000 + +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 21 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 23 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e00000 + +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 24 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 26 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x07000000 + +#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x00000004 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 27 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 29 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x38000000 + +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 30 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 30 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x40000000 + +#define RX_MPDU_END_RESERVED_1B_OFFSET 0x00000004 +#define RX_MPDU_END_RESERVED_1B_LSB 31 +#define RX_MPDU_END_RESERVED_1B_MSB 31 +#define RX_MPDU_END_RESERVED_1B_MASK 0x80000000 + +#define RX_MPDU_END_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_END_RESERVED_2A_LSB 0 +#define RX_MPDU_END_RESERVED_2A_MSB 14 +#define RX_MPDU_END_RESERVED_2A_MASK 0x00007fff + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x00000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x00008000 + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x00000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_info.h new file mode 100644 index 0000000000000000000000000000000000000000..2231090a035a0f8056365ab1b2cfe8ff40ff1b15 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_info.h @@ -0,0 +1,835 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_INFO_H_ +#define _RX_MPDU_INFO_H_ + +#include "rxpt_classify_info.h" +#define NUM_OF_DWORDS_RX_MPDU_INFO 30 + +struct rx_mpdu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t epd_en : 1, + all_frames_shall_be_encrypted : 1, + encrypt_type : 4, + wep_key_width_for_variable_key : 2, + __reserved_g_0003 : 2, + bssid_hit : 1, + bssid_number : 4, + tid : 4, + reserved_7a : 13; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + receive_queue_number : 16, + pre_delim_err_warning : 1, + first_delim_err : 1, + reserved_2a : 6; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t mpdu_frame_control_valid : 1, + mpdu_duration_valid : 1, + mac_addr_ad1_valid : 1, + mac_addr_ad2_valid : 1, + mac_addr_ad3_valid : 1, + mac_addr_ad4_valid : 1, + mpdu_sequence_control_valid : 1, + mpdu_qos_control_valid : 1, + mpdu_ht_control_valid : 1, + frame_encryption_info_valid : 1, + mpdu_fragment_number : 4, + more_fragment_flag : 1, + reserved_11a : 1, + fr_ds : 1, + to_ds : 1, + encrypted : 1, + mpdu_retry : 1, + mpdu_sequence_number : 12; + uint32_t peer_meta_data : 32; + uint32_t ast_index : 16, + sw_peer_id : 16; + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + ndp_frame : 1, + phy_err : 1, + phy_err_during_mpdu_header : 1, + protocol_version_err : 1, + ast_based_lookup_valid : 1, + __reserved_g_0005 : 1, + reserved_9a : 1, + phy_ppdu_id : 16; + uint32_t key_id_octet : 8, + new_peer_entry : 1, + decrypt_needed : 1, + decap_type : 2, + rx_insert_vlan_c_tag_padding : 1, + rx_insert_vlan_s_tag_padding : 1, + strip_vlan_c_tag_decap : 1, + strip_vlan_s_tag_decap : 1, + pre_delim_count : 12, + ampdu_flag : 1, + bar_frame : 1, + raw_mpdu : 1, + reserved_12 : 1; + uint32_t mpdu_length : 14, + first_mpdu : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + fragment_flag : 1, + order : 1, + u_apsd_trigger : 1, + encrypt_required : 1, + directed : 1, + amsdu_present : 1, + reserved_13 : 1; + uint32_t mpdu_frame_control_field : 16, + mpdu_duration_field : 16; + uint32_t mac_addr_ad1_31_0 : 32; + uint32_t mac_addr_ad1_47_32 : 16, + mac_addr_ad2_15_0 : 16; + uint32_t mac_addr_ad2_47_16 : 32; + uint32_t mac_addr_ad3_31_0 : 32; + uint32_t mac_addr_ad3_47_32 : 16, + mpdu_sequence_control_field : 16; + uint32_t mac_addr_ad4_31_0 : 32; + uint32_t mac_addr_ad4_47_32 : 16, + mpdu_qos_control_field : 16; + uint32_t mpdu_ht_control_field : 32; + uint32_t vdev_id : 8, + service_code : 9, + priority_valid : 1, + src_info : 12, + reserved_23a : 1, + __reserved_g_0006 : 1; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0008 : 16, + __reserved_g_0009 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t authorized_to_send_wds : 1, + reserved_27a : 31; + uint32_t reserved_28a : 32; + uint32_t reserved_29a : 32; +#else + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t reserved_7a : 13, + tid : 4, + bssid_number : 4, + bssid_hit : 1, + __reserved_g_0003 : 2, + wep_key_width_for_variable_key : 2, + encrypt_type : 4, + all_frames_shall_be_encrypted : 1, + epd_en : 1; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_2a : 6, + first_delim_err : 1, + pre_delim_err_warning : 1, + receive_queue_number : 16, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t mpdu_sequence_number : 12, + mpdu_retry : 1, + encrypted : 1, + to_ds : 1, + fr_ds : 1, + reserved_11a : 1, + more_fragment_flag : 1, + mpdu_fragment_number : 4, + frame_encryption_info_valid : 1, + mpdu_ht_control_valid : 1, + mpdu_qos_control_valid : 1, + mpdu_sequence_control_valid : 1, + mac_addr_ad4_valid : 1, + mac_addr_ad3_valid : 1, + mac_addr_ad2_valid : 1, + mac_addr_ad1_valid : 1, + mpdu_duration_valid : 1, + mpdu_frame_control_valid : 1; + uint32_t peer_meta_data : 32; + uint32_t sw_peer_id : 16, + ast_index : 16; + uint32_t phy_ppdu_id : 16, + reserved_9a : 1, + __reserved_g_0005 : 1, + ast_based_lookup_valid : 1, + protocol_version_err : 1, + phy_err_during_mpdu_header : 1, + phy_err : 1, + ndp_frame : 1, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_12 : 1, + raw_mpdu : 1, + bar_frame : 1, + ampdu_flag : 1, + pre_delim_count : 12, + strip_vlan_s_tag_decap : 1, + strip_vlan_c_tag_decap : 1, + rx_insert_vlan_s_tag_padding : 1, + rx_insert_vlan_c_tag_padding : 1, + decap_type : 2, + decrypt_needed : 1, + new_peer_entry : 1, + key_id_octet : 8; + uint32_t reserved_13 : 1, + amsdu_present : 1, + directed : 1, + encrypt_required : 1, + u_apsd_trigger : 1, + order : 1, + fragment_flag : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + first_mpdu : 1, + mpdu_length : 14; + uint32_t mpdu_duration_field : 16, + mpdu_frame_control_field : 16; + uint32_t mac_addr_ad1_31_0 : 32; + uint32_t mac_addr_ad2_15_0 : 16, + mac_addr_ad1_47_32 : 16; + uint32_t mac_addr_ad2_47_16 : 32; + uint32_t mac_addr_ad3_31_0 : 32; + uint32_t mpdu_sequence_control_field : 16, + mac_addr_ad3_47_32 : 16; + uint32_t mac_addr_ad4_31_0 : 32; + uint32_t mpdu_qos_control_field : 16, + mac_addr_ad4_47_32 : 16; + uint32_t mpdu_ht_control_field : 32; + uint32_t __reserved_g_0006 : 1, + reserved_23a : 1, + src_info : 12, + priority_valid : 1, + service_code : 9, + vdev_id : 8; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0009 : 16, + __reserved_g_0008 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t reserved_27a : 31, + authorized_to_send_wds : 1; + uint32_t reserved_28a : 32; + uint32_t reserved_29a : 32; +#endif +}; + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000 + +#define RX_MPDU_INFO_EPD_EN_OFFSET 0x00000004 +#define RX_MPDU_INFO_EPD_EN_LSB 0 +#define RX_MPDU_INFO_EPD_EN_MSB 0 +#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 + +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x00000004 +#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c + +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x00000004 +#define RX_MPDU_INFO_BSSID_HIT_LSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 + +#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x00000004 +#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 +#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 +#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 + +#define RX_MPDU_INFO_TID_OFFSET 0x00000004 +#define RX_MPDU_INFO_TID_LSB 15 +#define RX_MPDU_INFO_TID_MSB 18 +#define RX_MPDU_INFO_TID_MASK 0x00078000 + +#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x00000004 +#define RX_MPDU_INFO_RESERVED_7A_LSB 19 +#define RX_MPDU_INFO_RESERVED_7A_MSB 31 +#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x0000000c +#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 + +#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x0000000c +#define RX_MPDU_INFO_RESERVED_2A_LSB 26 +#define RX_MPDU_INFO_RESERVED_2A_MSB 31 +#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 + +#define RX_MPDU_INFO_PN_31_0_OFFSET 0x00000010 +#define RX_MPDU_INFO_PN_31_0_LSB 0 +#define RX_MPDU_INFO_PN_31_0_MSB 31 +#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000014 +#define RX_MPDU_INFO_PN_63_32_LSB 0 +#define RX_MPDU_INFO_PN_63_32_MSB 31 +#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff + +#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000018 +#define RX_MPDU_INFO_PN_95_64_LSB 0 +#define RX_MPDU_INFO_PN_95_64_MSB 31 +#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff + +#define RX_MPDU_INFO_PN_127_96_OFFSET 0x0000001c +#define RX_MPDU_INFO_PN_127_96_LSB 0 +#define RX_MPDU_INFO_PN_127_96_MSB 31 +#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 + +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000020 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x00000020 +#define RX_MPDU_INFO_RESERVED_11A_LSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 + +#define RX_MPDU_INFO_FR_DS_OFFSET 0x00000020 +#define RX_MPDU_INFO_FR_DS_LSB 16 +#define RX_MPDU_INFO_FR_DS_MSB 16 +#define RX_MPDU_INFO_FR_DS_MASK 0x00010000 + +#define RX_MPDU_INFO_TO_DS_OFFSET 0x00000020 +#define RX_MPDU_INFO_TO_DS_LSB 17 +#define RX_MPDU_INFO_TO_DS_MSB 17 +#define RX_MPDU_INFO_TO_DS_MASK 0x00020000 + +#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x00000020 +#define RX_MPDU_INFO_ENCRYPTED_LSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 + +#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_RETRY_LSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 + +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000024 +#define RX_MPDU_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff + +#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_INFO_AST_INDEX_LSB 0 +#define RX_MPDU_INFO_AST_INDEX_MSB 15 +#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff + +#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_INFO_SW_PEER_ID_LSB 16 +#define RX_MPDU_INFO_SW_PEER_ID_MSB 31 +#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x0000002c +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x0000002c +#define RX_MPDU_INFO_NDP_FRAME_LSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 + +#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x0000002c +#define RX_MPDU_INFO_PHY_ERR_LSB 10 +#define RX_MPDU_INFO_PHY_ERR_MSB 10 +#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 + +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +#define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x0000002c +#define RX_MPDU_INFO_RESERVED_9A_LSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 + +#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x0000002c +#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 + +#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 + +#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECAP_TYPE_LSB 10 +#define RX_MPDU_INFO_DECAP_TYPE_MSB 11 +#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 + +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 + +#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 + +#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_INFO_BAR_FRAME_LSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 + +#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_INFO_RAW_MPDU_LSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_INFO_RESERVED_12_LSB 31 +#define RX_MPDU_INFO_RESERVED_12_MSB 31 +#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 + +#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 +#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 +#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff + +#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_INFO_FIRST_MPDU_LSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 + +#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_INFO_MCAST_BCAST_LSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 + +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 + +#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_INFO_POWER_MGMT_LSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 + +#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_INFO_NON_QOS_LSB 19 +#define RX_MPDU_INFO_NON_QOS_MSB 19 +#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 + +#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_NULL_DATA_LSB 20 +#define RX_MPDU_INFO_NULL_DATA_MSB 20 +#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 + +#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_MGMT_TYPE_LSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 + +#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_CTRL_TYPE_LSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 + +#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_MORE_DATA_LSB 23 +#define RX_MPDU_INFO_MORE_DATA_MSB 23 +#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 + +#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 +#define RX_MPDU_INFO_EOSP_LSB 24 +#define RX_MPDU_INFO_EOSP_MSB 24 +#define RX_MPDU_INFO_EOSP_MASK 0x01000000 + +#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 + +#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 +#define RX_MPDU_INFO_ORDER_LSB 26 +#define RX_MPDU_INFO_ORDER_MSB 26 +#define RX_MPDU_INFO_ORDER_MASK 0x04000000 + +#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 + +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 + +#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_INFO_DIRECTED_LSB 29 +#define RX_MPDU_INFO_DIRECTED_MSB 29 +#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 + +#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 + +#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_INFO_RESERVED_13_LSB 31 +#define RX_MPDU_INFO_RESERVED_13_MSB 31 +#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + +#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c +#define RX_MPDU_INFO_VDEV_ID_LSB 0 +#define RX_MPDU_INFO_VDEV_ID_MSB 7 +#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff + +#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MPDU_INFO_SERVICE_CODE_LSB 8 +#define RX_MPDU_INFO_SERVICE_CODE_MSB 16 +#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 + +#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 + +#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c +#define RX_MPDU_INFO_SRC_INFO_LSB 18 +#define RX_MPDU_INFO_SRC_INFO_MSB 29 +#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 + +#define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c +#define RX_MPDU_INFO_RESERVED_23A_LSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 + +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 + +#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_MPDU_INFO_RESERVED_27A_LSB 1 +#define RX_MPDU_INFO_RESERVED_27A_MSB 31 +#define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe + +#define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 +#define RX_MPDU_INFO_RESERVED_28A_LSB 0 +#define RX_MPDU_INFO_RESERVED_28A_MSB 31 +#define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff + +#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 +#define RX_MPDU_INFO_RESERVED_29A_LSB 0 +#define RX_MPDU_INFO_RESERVED_29A_MSB 31 +#define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_link_ptr.h new file mode 100644 index 0000000000000000000000000000000000000000..d356550543f4fd81bc669853446acb455cab7266 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_link_ptr.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_LINK_PTR_H_ +#define _RX_MPDU_LINK_PTR_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 + +struct rx_mpdu_link_ptr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info mpdu_link_desc_addr_info; +#else + struct buffer_addr_info mpdu_link_desc_addr_info; +#endif +}; + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_start.h b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..18032824c2f046cd98d27b51ba372c5d925625ec --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_start.h @@ -0,0 +1,617 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_START_H_ +#define _RX_MPDU_START_H_ + +#include "rx_mpdu_info.h" +#define NUM_OF_DWORDS_RX_MPDU_START 30 + +struct rx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_info rx_mpdu_info_details; +#else + struct rx_mpdu_info rx_mpdu_info_details; +#endif +}; + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000400 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00007800 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x00078000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff80000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000014 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000001c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 2 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 3 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 4 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x00008000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000024 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x00008000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x80000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 26 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 26 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 27 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x40000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x80000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x00020000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK 0x40000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000006c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xfffffffe + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_OFFSET 0x00000070 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x00000074 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_desc_info.h new file mode 100644 index 0000000000000000000000000000000000000000..90a3df7973a276172e7ce6c2a736b8bf146568c0 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_desc_info.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_DESC_INFO_H_ +#define _RX_MSDU_DESC_INFO_H_ + +#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 + +struct rx_msdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t first_msdu_in_mpdu_flag : 1, + last_msdu_in_mpdu_flag : 1, + msdu_continuation : 1, + msdu_length : 14, + msdu_drop : 1, + sa_is_valid : 1, + da_is_valid : 1, + da_is_mcbc : 1, + l3_header_padding_msb : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + fr_ds : 1, + to_ds : 1, + intra_bss : 1, + dest_chip_id : 2, + decap_format : 2, + reserved_0a : 1; +#else + uint32_t reserved_0a : 1, + decap_format : 2, + dest_chip_id : 2, + intra_bss : 1, + to_ds : 1, + fr_ds : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + l3_header_padding_msb : 1, + da_is_mcbc : 1, + da_is_valid : 1, + sa_is_valid : 1, + msdu_drop : 1, + msdu_length : 14, + msdu_continuation : 1, + last_msdu_in_mpdu_flag : 1, + first_msdu_in_mpdu_flag : 1; +#endif +}; + +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FR_DS_LSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 + +#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TO_DS_LSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 + +#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_msdu_details.h b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_details.h new file mode 100644 index 0000000000000000000000000000000000000000..39313f38b3aeec5c10e0e49e88f65179bce319bd --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_details.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_DETAILS_H_ +#define _RX_MSDU_DETAILS_H_ + +#include "rx_msdu_desc_info.h" +#include "rx_msdu_ext_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 + +struct rx_msdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#else + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#endif +}; + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_msdu_end.h b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_end.h new file mode 100644 index 0000000000000000000000000000000000000000..15b0aa3f017b82acba0fb6893c31a46b08b27c7a --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_end.h @@ -0,0 +1,1097 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_END_H_ +#define _RX_MSDU_END_H_ + +#define NUM_OF_DWORDS_RX_MSDU_END 32 + +struct rx_msdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t ip_hdr_chksum : 16, + reported_mpdu_length : 14, + reserved_1a : 2; + uint32_t reserved_2a : 8, + cce_super_rule : 6, + cce_classify_not_done_truncate : 1, + cce_classify_not_done_cce_dis : 1, + cumulative_l3_checksum : 16; + uint32_t rule_indication_31_0 : 32; + uint32_t ipv6_options_crc : 32; + uint32_t da_offset : 6, + sa_offset : 6, + da_offset_valid : 1, + sa_offset_valid : 1, + reserved_5a : 2, + l3_type : 16; + uint32_t rule_indication_63_32 : 32; + uint32_t tcp_seq_number : 32; + uint32_t tcp_ack_number : 32; + uint32_t tcp_flag : 9, + lro_eligible : 1, + reserved_9a : 6, + window_size : 16; + uint32_t sa_sw_peer_id : 16, + sa_idx_timeout : 1, + da_idx_timeout : 1, + to_ds : 1, + tid : 4, + sa_is_valid : 1, + da_is_valid : 1, + da_is_mcbc : 1, + l3_header_padding : 2, + first_msdu : 1, + last_msdu : 1, + fr_ds : 1, + ip_chksum_fail_copy : 1; + uint32_t sa_idx : 16, + da_idx_or_sw_peer_id : 16; + uint32_t msdu_drop : 1, + reo_destination_indication : 5, + flow_idx : 20, + use_ppe : 1, + __reserved_g_0003 : 2, + vlan_ctag_stripped : 1, + vlan_stag_stripped : 1, + fragment_flag : 1; + uint32_t fse_metadata : 32; + uint32_t cce_metadata : 16, + tcp_udp_chksum : 16; + uint32_t aggregation_count : 8, + flow_aggregation_continuation : 1, + fisa_timeout : 1, + tcp_udp_chksum_fail_copy : 1, + msdu_limit_error : 1, + flow_idx_timeout : 1, + flow_idx_invalid : 1, + cce_match : 1, + amsdu_parser_error : 1, + cumulative_ip_length : 16; + uint32_t key_id_octet : 8, + reserved_16a : 24; + uint32_t reserved_17a : 6, + service_code : 9, + priority_valid : 1, + intra_bss : 1, + dest_chip_id : 2, + multicast_echo : 1, + wds_learning_event : 1, + wds_roaming_event : 1, + wds_keep_alive_event : 1, + __reserved_g_0015 : 1, + reserved_17b : 8; + uint32_t msdu_length : 14, + stbc : 1, + ipsec_esp : 1, + l3_offset : 7, + ipsec_ah : 1, + l4_offset : 8; + uint32_t msdu_number : 8, + decap_format : 2, + ipv4_proto : 1, + ipv6_proto : 1, + tcp_proto : 1, + udp_proto : 1, + ip_frag : 1, + tcp_only_ack : 1, + da_is_bcast_mcast : 1, + toeplitz_hash_sel : 2, + ip_fixed_header_valid : 1, + ip_extn_header_valid : 1, + tcp_udp_header_valid : 1, + mesh_control_present : 1, + ldpc : 1, + ip4_protocol_ip6_next_header : 8; + uint32_t vlan_ctag_ci : 16, + vlan_stag_ci : 16; + uint32_t peer_meta_data : 32; + uint32_t user_rssi : 8, + pkt_type : 4, + sgi : 2, + rate_mcs : 4, + receive_bandwidth : 3, + reception_type : 3, + mimo_ss_bitmap : 7, + msdu_done_copy : 1; + uint32_t flow_id_toeplitz : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t reserved_28a : 16, + sa_15_0 : 16; + uint32_t sa_47_16 : 32; + uint32_t first_mpdu : 1, + reserved_30a : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + a_msdu_error : 1, + reserved_30b : 1, + order : 1, + wifi_parser_error : 1, + overflow_err : 1, + msdu_length_err : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + sa_idx_invalid : 1, + da_idx_invalid : 1, + amsdu_addr_mismatch : 1, + rx_in_tx_decrypt_byp : 1, + encrypt_required : 1, + directed : 1, + buffer_fragment : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + fcs_err : 1; + uint32_t reserved_31a : 10, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_31b : 17, + msdu_done : 1; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_1a : 2, + reported_mpdu_length : 14, + ip_hdr_chksum : 16; + uint32_t cumulative_l3_checksum : 16, + cce_classify_not_done_cce_dis : 1, + cce_classify_not_done_truncate : 1, + cce_super_rule : 6, + reserved_2a : 8; + uint32_t rule_indication_31_0 : 32; + uint32_t ipv6_options_crc : 32; + uint32_t l3_type : 16, + reserved_5a : 2, + sa_offset_valid : 1, + da_offset_valid : 1, + sa_offset : 6, + da_offset : 6; + uint32_t rule_indication_63_32 : 32; + uint32_t tcp_seq_number : 32; + uint32_t tcp_ack_number : 32; + uint32_t window_size : 16, + reserved_9a : 6, + lro_eligible : 1, + tcp_flag : 9; + uint32_t ip_chksum_fail_copy : 1, + fr_ds : 1, + last_msdu : 1, + first_msdu : 1, + l3_header_padding : 2, + da_is_mcbc : 1, + da_is_valid : 1, + sa_is_valid : 1, + tid : 4, + to_ds : 1, + da_idx_timeout : 1, + sa_idx_timeout : 1, + sa_sw_peer_id : 16; + uint32_t da_idx_or_sw_peer_id : 16, + sa_idx : 16; + uint32_t fragment_flag : 1, + vlan_stag_stripped : 1, + vlan_ctag_stripped : 1, + __reserved_g_0003 : 2, + use_ppe : 1, + flow_idx : 20, + reo_destination_indication : 5, + msdu_drop : 1; + uint32_t fse_metadata : 32; + uint32_t tcp_udp_chksum : 16, + cce_metadata : 16; + uint32_t cumulative_ip_length : 16, + amsdu_parser_error : 1, + cce_match : 1, + flow_idx_invalid : 1, + flow_idx_timeout : 1, + msdu_limit_error : 1, + tcp_udp_chksum_fail_copy : 1, + fisa_timeout : 1, + flow_aggregation_continuation : 1, + aggregation_count : 8; + uint32_t reserved_16a : 24, + key_id_octet : 8; + uint32_t reserved_17b : 8, + __reserved_g_0015 : 1, + wds_keep_alive_event : 1, + wds_roaming_event : 1, + wds_learning_event : 1, + multicast_echo : 1, + dest_chip_id : 2, + intra_bss : 1, + priority_valid : 1, + service_code : 9, + reserved_17a : 6; + uint32_t l4_offset : 8, + ipsec_ah : 1, + l3_offset : 7, + ipsec_esp : 1, + stbc : 1, + msdu_length : 14; + uint32_t ip4_protocol_ip6_next_header : 8, + ldpc : 1, + mesh_control_present : 1, + tcp_udp_header_valid : 1, + ip_extn_header_valid : 1, + ip_fixed_header_valid : 1, + toeplitz_hash_sel : 2, + da_is_bcast_mcast : 1, + tcp_only_ack : 1, + ip_frag : 1, + udp_proto : 1, + tcp_proto : 1, + ipv6_proto : 1, + ipv4_proto : 1, + decap_format : 2, + msdu_number : 8; + uint32_t vlan_stag_ci : 16, + vlan_ctag_ci : 16; + uint32_t peer_meta_data : 32; + uint32_t msdu_done_copy : 1, + mimo_ss_bitmap : 7, + reception_type : 3, + receive_bandwidth : 3, + rate_mcs : 4, + sgi : 2, + pkt_type : 4, + user_rssi : 8; + uint32_t flow_id_toeplitz : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t sa_15_0 : 16, + reserved_28a : 16; + uint32_t sa_47_16 : 32; + uint32_t fcs_err : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + buffer_fragment : 1, + directed : 1, + encrypt_required : 1, + rx_in_tx_decrypt_byp : 1, + amsdu_addr_mismatch : 1, + da_idx_invalid : 1, + sa_idx_invalid : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + msdu_length_err : 1, + overflow_err : 1, + wifi_parser_error : 1, + order : 1, + reserved_30b : 1, + a_msdu_error : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + reserved_30a : 1, + first_mpdu : 1; + uint32_t msdu_done : 1, + reserved_31b : 17, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + reserved_31a : 10; +#endif +}; + +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MSDU_END_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_END_RESERVED_0_LSB 9 +#define RX_MSDU_END_RESERVED_0_MSB 15 +#define RX_MSDU_END_RESERVED_0_MASK 0x0000fe00 + +#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_END_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x00000004 +#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 0 +#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 15 +#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff + +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 16 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 29 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff0000 + +#define RX_MSDU_END_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_END_RESERVED_1A_LSB 30 +#define RX_MSDU_END_RESERVED_1A_MSB 31 +#define RX_MSDU_END_RESERVED_1A_MASK 0xc0000000 + +#define RX_MSDU_END_RESERVED_2A_OFFSET 0x00000008 +#define RX_MSDU_END_RESERVED_2A_LSB 0 +#define RX_MSDU_END_RESERVED_2A_MSB 7 +#define RX_MSDU_END_RESERVED_2A_MASK 0x000000ff + +#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x00000008 +#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 +#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 +#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x00003f00 + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 + +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000 + +#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000c +#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 0 +#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 31 +#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff + +#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x00000010 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0xffffffff + +#define RX_MSDU_END_DA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_DA_OFFSET_LSB 0 +#define RX_MSDU_END_DA_OFFSET_MSB 5 +#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f + +#define RX_MSDU_END_SA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_SA_OFFSET_LSB 6 +#define RX_MSDU_END_SA_OFFSET_MSB 11 +#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc0 + +#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_DA_OFFSET_VALID_LSB 12 +#define RX_MSDU_END_DA_OFFSET_VALID_MSB 12 +#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x00001000 + +#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_SA_OFFSET_VALID_LSB 13 +#define RX_MSDU_END_SA_OFFSET_VALID_MSB 13 +#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x00002000 + +#define RX_MSDU_END_RESERVED_5A_OFFSET 0x00000014 +#define RX_MSDU_END_RESERVED_5A_LSB 14 +#define RX_MSDU_END_RESERVED_5A_MSB 15 +#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c000 + +#define RX_MSDU_END_L3_TYPE_OFFSET 0x00000014 +#define RX_MSDU_END_L3_TYPE_LSB 16 +#define RX_MSDU_END_L3_TYPE_MSB 31 +#define RX_MSDU_END_L3_TYPE_MASK 0xffff0000 + +#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x00000018 +#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 +#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 +#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0xffffffff + +#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000001c +#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 0 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 31 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x00000020 +#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 +#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 +#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0xffffffff + +#define RX_MSDU_END_TCP_FLAG_OFFSET 0x00000024 +#define RX_MSDU_END_TCP_FLAG_LSB 0 +#define RX_MSDU_END_TCP_FLAG_MSB 8 +#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff + +#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x00000024 +#define RX_MSDU_END_LRO_ELIGIBLE_LSB 9 +#define RX_MSDU_END_LRO_ELIGIBLE_MSB 9 +#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x00000200 + +#define RX_MSDU_END_RESERVED_9A_OFFSET 0x00000024 +#define RX_MSDU_END_RESERVED_9A_LSB 10 +#define RX_MSDU_END_RESERVED_9A_MSB 15 +#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc00 + +#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x00000024 +#define RX_MSDU_END_WINDOW_SIZE_LSB 16 +#define RX_MSDU_END_WINDOW_SIZE_MSB 31 +#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff0000 + +#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 +#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 +#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x0000ffff + +#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x00010000 + +#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x00020000 + +#define RX_MSDU_END_TO_DS_OFFSET 0x00000028 +#define RX_MSDU_END_TO_DS_LSB 18 +#define RX_MSDU_END_TO_DS_MSB 18 +#define RX_MSDU_END_TO_DS_MASK 0x00040000 + +#define RX_MSDU_END_TID_OFFSET 0x00000028 +#define RX_MSDU_END_TID_LSB 19 +#define RX_MSDU_END_TID_MSB 22 +#define RX_MSDU_END_TID_MASK 0x00780000 + +#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_SA_IS_VALID_LSB 23 +#define RX_MSDU_END_SA_IS_VALID_MSB 23 +#define RX_MSDU_END_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_DA_IS_VALID_LSB 24 +#define RX_MSDU_END_DA_IS_VALID_MSB 24 +#define RX_MSDU_END_DA_IS_VALID_MASK 0x01000000 + +#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_END_DA_IS_MCBC_LSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MASK 0x02000000 + +#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x00000028 +#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 +#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 +#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x0c000000 + +#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_FIRST_MSDU_LSB 28 +#define RX_MSDU_END_FIRST_MSDU_MSB 28 +#define RX_MSDU_END_FIRST_MSDU_MASK 0x10000000 + +#define RX_MSDU_END_LAST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_LAST_MSDU_LSB 29 +#define RX_MSDU_END_LAST_MSDU_MSB 29 +#define RX_MSDU_END_LAST_MSDU_MASK 0x20000000 + +#define RX_MSDU_END_FR_DS_OFFSET 0x00000028 +#define RX_MSDU_END_FR_DS_LSB 30 +#define RX_MSDU_END_FR_DS_MSB 30 +#define RX_MSDU_END_FR_DS_MASK 0x40000000 + +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x00000028 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x80000000 + +#define RX_MSDU_END_SA_IDX_OFFSET 0x0000002c +#define RX_MSDU_END_SA_IDX_LSB 0 +#define RX_MSDU_END_SA_IDX_MSB 15 +#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff + +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 16 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 31 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MSDU_END_MSDU_DROP_OFFSET 0x00000030 +#define RX_MSDU_END_MSDU_DROP_LSB 0 +#define RX_MSDU_END_MSDU_DROP_MSB 0 +#define RX_MSDU_END_MSDU_DROP_MASK 0x00000001 + +#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x00000030 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x0000003e + +#define RX_MSDU_END_FLOW_IDX_OFFSET 0x00000030 +#define RX_MSDU_END_FLOW_IDX_LSB 6 +#define RX_MSDU_END_FLOW_IDX_MSB 25 +#define RX_MSDU_END_FLOW_IDX_MASK 0x03ffffc0 + +#define RX_MSDU_END_USE_PPE_OFFSET 0x00000030 +#define RX_MSDU_END_USE_PPE_LSB 26 +#define RX_MSDU_END_USE_PPE_MSB 26 +#define RX_MSDU_END_USE_PPE_MASK 0x04000000 + +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x00000030 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x20000000 + +#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x00000030 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x40000000 + +#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x00000030 +#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x80000000 + +#define RX_MSDU_END_FSE_METADATA_OFFSET 0x00000034 +#define RX_MSDU_END_FSE_METADATA_LSB 0 +#define RX_MSDU_END_FSE_METADATA_MSB 31 +#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff + +#define RX_MSDU_END_CCE_METADATA_OFFSET 0x00000038 +#define RX_MSDU_END_CCE_METADATA_LSB 0 +#define RX_MSDU_END_CCE_METADATA_MSB 15 +#define RX_MSDU_END_CCE_METADATA_MASK 0x0000ffff + +#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x00000038 +#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0xffff0000 + +#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000003c +#define RX_MSDU_END_AGGREGATION_COUNT_LSB 0 +#define RX_MSDU_END_AGGREGATION_COUNT_MSB 7 +#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff + +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 8 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 8 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100 + +#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000003c +#define RX_MSDU_END_FISA_TIMEOUT_LSB 9 +#define RX_MSDU_END_FISA_TIMEOUT_MSB 9 +#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x00000200 + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000003c +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 10 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 10 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x00000400 + +#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000003c +#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 11 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 11 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x00000800 + +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000003c +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 12 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 12 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x00001000 + +#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000003c +#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 13 +#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 13 +#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x00002000 + +#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000003c +#define RX_MSDU_END_CCE_MATCH_LSB 14 +#define RX_MSDU_END_CCE_MATCH_MSB 14 +#define RX_MSDU_END_CCE_MATCH_MASK 0x00004000 + +#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000003c +#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 15 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 15 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x00008000 + +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000003c +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 31 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x00000040 +#define RX_MSDU_END_KEY_ID_OCTET_LSB 0 +#define RX_MSDU_END_KEY_ID_OCTET_MSB 7 +#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MSDU_END_RESERVED_16A_OFFSET 0x00000040 +#define RX_MSDU_END_RESERVED_16A_LSB 8 +#define RX_MSDU_END_RESERVED_16A_MSB 31 +#define RX_MSDU_END_RESERVED_16A_MASK 0xffffff00 + +#define RX_MSDU_END_RESERVED_17A_OFFSET 0x00000044 +#define RX_MSDU_END_RESERVED_17A_LSB 0 +#define RX_MSDU_END_RESERVED_17A_MSB 5 +#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f + +#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x00000044 +#define RX_MSDU_END_SERVICE_CODE_LSB 6 +#define RX_MSDU_END_SERVICE_CODE_MSB 14 +#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc0 + +#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x00000044 +#define RX_MSDU_END_PRIORITY_VALID_LSB 15 +#define RX_MSDU_END_PRIORITY_VALID_MSB 15 +#define RX_MSDU_END_PRIORITY_VALID_MASK 0x00008000 + +#define RX_MSDU_END_INTRA_BSS_OFFSET 0x00000044 +#define RX_MSDU_END_INTRA_BSS_LSB 16 +#define RX_MSDU_END_INTRA_BSS_MSB 16 +#define RX_MSDU_END_INTRA_BSS_MASK 0x00010000 + +#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x00000044 +#define RX_MSDU_END_DEST_CHIP_ID_LSB 17 +#define RX_MSDU_END_DEST_CHIP_ID_MSB 18 +#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x00060000 + +#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x00000044 +#define RX_MSDU_END_MULTICAST_ECHO_LSB 19 +#define RX_MSDU_END_MULTICAST_ECHO_MSB 19 +#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x00080000 + +#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x00000044 +#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 20 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 20 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x00100000 + +#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x00000044 +#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 21 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 21 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x00200000 + +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x00000044 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 22 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 22 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x00400000 + +#define RX_MSDU_END_RESERVED_17B_OFFSET 0x00000044 +#define RX_MSDU_END_RESERVED_17B_LSB 24 +#define RX_MSDU_END_RESERVED_17B_MSB 31 +#define RX_MSDU_END_RESERVED_17B_MASK 0xff000000 + +#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_END_MSDU_LENGTH_LSB 0 +#define RX_MSDU_END_MSDU_LENGTH_MSB 13 +#define RX_MSDU_END_MSDU_LENGTH_MASK 0x00003fff + +#define RX_MSDU_END_STBC_OFFSET 0x00000048 +#define RX_MSDU_END_STBC_LSB 14 +#define RX_MSDU_END_STBC_MSB 14 +#define RX_MSDU_END_STBC_MASK 0x00004000 + +#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x00000048 +#define RX_MSDU_END_IPSEC_ESP_LSB 15 +#define RX_MSDU_END_IPSEC_ESP_MSB 15 +#define RX_MSDU_END_IPSEC_ESP_MASK 0x00008000 + +#define RX_MSDU_END_L3_OFFSET_OFFSET 0x00000048 +#define RX_MSDU_END_L3_OFFSET_LSB 16 +#define RX_MSDU_END_L3_OFFSET_MSB 22 +#define RX_MSDU_END_L3_OFFSET_MASK 0x007f0000 + +#define RX_MSDU_END_IPSEC_AH_OFFSET 0x00000048 +#define RX_MSDU_END_IPSEC_AH_LSB 23 +#define RX_MSDU_END_IPSEC_AH_MSB 23 +#define RX_MSDU_END_IPSEC_AH_MASK 0x00800000 + +#define RX_MSDU_END_L4_OFFSET_OFFSET 0x00000048 +#define RX_MSDU_END_L4_OFFSET_LSB 24 +#define RX_MSDU_END_L4_OFFSET_MSB 31 +#define RX_MSDU_END_L4_OFFSET_MASK 0xff000000 + +#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000004c +#define RX_MSDU_END_MSDU_NUMBER_LSB 0 +#define RX_MSDU_END_MSDU_NUMBER_MSB 7 +#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff + +#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000004c +#define RX_MSDU_END_DECAP_FORMAT_LSB 8 +#define RX_MSDU_END_DECAP_FORMAT_MSB 9 +#define RX_MSDU_END_DECAP_FORMAT_MASK 0x00000300 + +#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000004c +#define RX_MSDU_END_IPV4_PROTO_LSB 10 +#define RX_MSDU_END_IPV4_PROTO_MSB 10 +#define RX_MSDU_END_IPV4_PROTO_MASK 0x00000400 + +#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000004c +#define RX_MSDU_END_IPV6_PROTO_LSB 11 +#define RX_MSDU_END_IPV6_PROTO_MSB 11 +#define RX_MSDU_END_IPV6_PROTO_MASK 0x00000800 + +#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000004c +#define RX_MSDU_END_TCP_PROTO_LSB 12 +#define RX_MSDU_END_TCP_PROTO_MSB 12 +#define RX_MSDU_END_TCP_PROTO_MASK 0x00001000 + +#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000004c +#define RX_MSDU_END_UDP_PROTO_LSB 13 +#define RX_MSDU_END_UDP_PROTO_MSB 13 +#define RX_MSDU_END_UDP_PROTO_MASK 0x00002000 + +#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000004c +#define RX_MSDU_END_IP_FRAG_LSB 14 +#define RX_MSDU_END_IP_FRAG_MSB 14 +#define RX_MSDU_END_IP_FRAG_MASK 0x00004000 + +#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000004c +#define RX_MSDU_END_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_END_TCP_ONLY_ACK_MSB 15 +#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x00008000 + +#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000004c +#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 16 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x00010000 + +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000004c +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 18 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x00060000 + +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000004c +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 19 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x00080000 + +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000004c +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 20 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x00100000 + +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000004c +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 21 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x00200000 + +#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000004c +#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 22 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x00400000 + +#define RX_MSDU_END_LDPC_OFFSET 0x0000004c +#define RX_MSDU_END_LDPC_LSB 23 +#define RX_MSDU_END_LDPC_MSB 23 +#define RX_MSDU_END_LDPC_MASK 0x00800000 + +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000004c +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000 + +#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x00000050 +#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 +#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x0000ffff + +#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x00000050 +#define RX_MSDU_END_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_END_VLAN_STAG_CI_MSB 31 +#define RX_MSDU_END_VLAN_STAG_CI_MASK 0xffff0000 + +#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x00000054 +#define RX_MSDU_END_PEER_META_DATA_LSB 0 +#define RX_MSDU_END_PEER_META_DATA_MSB 31 +#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff + +#define RX_MSDU_END_USER_RSSI_OFFSET 0x00000058 +#define RX_MSDU_END_USER_RSSI_LSB 0 +#define RX_MSDU_END_USER_RSSI_MSB 7 +#define RX_MSDU_END_USER_RSSI_MASK 0x000000ff + +#define RX_MSDU_END_PKT_TYPE_OFFSET 0x00000058 +#define RX_MSDU_END_PKT_TYPE_LSB 8 +#define RX_MSDU_END_PKT_TYPE_MSB 11 +#define RX_MSDU_END_PKT_TYPE_MASK 0x00000f00 + +#define RX_MSDU_END_SGI_OFFSET 0x00000058 +#define RX_MSDU_END_SGI_LSB 12 +#define RX_MSDU_END_SGI_MSB 13 +#define RX_MSDU_END_SGI_MASK 0x00003000 + +#define RX_MSDU_END_RATE_MCS_OFFSET 0x00000058 +#define RX_MSDU_END_RATE_MCS_LSB 14 +#define RX_MSDU_END_RATE_MCS_MSB 17 +#define RX_MSDU_END_RATE_MCS_MASK 0x0003c000 + +#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x00000058 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x001c0000 + +#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x00000058 +#define RX_MSDU_END_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_END_RECEPTION_TYPE_MSB 23 +#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x00e00000 + +#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x00000058 +#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 +#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x7f000000 + +#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x00000058 +#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x80000000 + +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000005c +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 31 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000060 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x00000064 +#define RX_MSDU_END_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_END_SW_PHY_META_DATA_MSB 31 +#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000068 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000006c +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 31 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff + +#define RX_MSDU_END_RESERVED_28A_OFFSET 0x00000070 +#define RX_MSDU_END_RESERVED_28A_LSB 0 +#define RX_MSDU_END_RESERVED_28A_MSB 15 +#define RX_MSDU_END_RESERVED_28A_MASK 0x0000ffff + +#define RX_MSDU_END_SA_15_0_OFFSET 0x00000070 +#define RX_MSDU_END_SA_15_0_LSB 16 +#define RX_MSDU_END_SA_15_0_MSB 31 +#define RX_MSDU_END_SA_15_0_MASK 0xffff0000 + +#define RX_MSDU_END_SA_47_16_OFFSET 0x00000074 +#define RX_MSDU_END_SA_47_16_LSB 0 +#define RX_MSDU_END_SA_47_16_MSB 31 +#define RX_MSDU_END_SA_47_16_MASK 0xffffffff + +#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x00000078 +#define RX_MSDU_END_FIRST_MPDU_LSB 0 +#define RX_MSDU_END_FIRST_MPDU_MSB 0 +#define RX_MSDU_END_FIRST_MPDU_MASK 0x00000001 + +#define RX_MSDU_END_RESERVED_30A_OFFSET 0x00000078 +#define RX_MSDU_END_RESERVED_30A_LSB 1 +#define RX_MSDU_END_RESERVED_30A_MSB 1 +#define RX_MSDU_END_RESERVED_30A_MASK 0x00000002 + +#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x00000078 +#define RX_MSDU_END_MCAST_BCAST_LSB 2 +#define RX_MSDU_END_MCAST_BCAST_MSB 2 +#define RX_MSDU_END_MCAST_BCAST_MASK 0x00000004 + +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x00000078 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x00000008 + +#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x00000078 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x00000010 + +#define RX_MSDU_END_POWER_MGMT_OFFSET 0x00000078 +#define RX_MSDU_END_POWER_MGMT_LSB 5 +#define RX_MSDU_END_POWER_MGMT_MSB 5 +#define RX_MSDU_END_POWER_MGMT_MASK 0x00000020 + +#define RX_MSDU_END_NON_QOS_OFFSET 0x00000078 +#define RX_MSDU_END_NON_QOS_LSB 6 +#define RX_MSDU_END_NON_QOS_MSB 6 +#define RX_MSDU_END_NON_QOS_MASK 0x00000040 + +#define RX_MSDU_END_NULL_DATA_OFFSET 0x00000078 +#define RX_MSDU_END_NULL_DATA_LSB 7 +#define RX_MSDU_END_NULL_DATA_MSB 7 +#define RX_MSDU_END_NULL_DATA_MASK 0x00000080 + +#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x00000078 +#define RX_MSDU_END_MGMT_TYPE_LSB 8 +#define RX_MSDU_END_MGMT_TYPE_MSB 8 +#define RX_MSDU_END_MGMT_TYPE_MASK 0x00000100 + +#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x00000078 +#define RX_MSDU_END_CTRL_TYPE_LSB 9 +#define RX_MSDU_END_CTRL_TYPE_MSB 9 +#define RX_MSDU_END_CTRL_TYPE_MASK 0x00000200 + +#define RX_MSDU_END_MORE_DATA_OFFSET 0x00000078 +#define RX_MSDU_END_MORE_DATA_LSB 10 +#define RX_MSDU_END_MORE_DATA_MSB 10 +#define RX_MSDU_END_MORE_DATA_MASK 0x00000400 + +#define RX_MSDU_END_EOSP_OFFSET 0x00000078 +#define RX_MSDU_END_EOSP_LSB 11 +#define RX_MSDU_END_EOSP_MSB 11 +#define RX_MSDU_END_EOSP_MASK 0x00000800 + +#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x00000078 +#define RX_MSDU_END_A_MSDU_ERROR_LSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x00001000 + +#define RX_MSDU_END_RESERVED_30B_OFFSET 0x00000078 +#define RX_MSDU_END_RESERVED_30B_LSB 13 +#define RX_MSDU_END_RESERVED_30B_MSB 13 +#define RX_MSDU_END_RESERVED_30B_MASK 0x00002000 + +#define RX_MSDU_END_ORDER_OFFSET 0x00000078 +#define RX_MSDU_END_ORDER_LSB 14 +#define RX_MSDU_END_ORDER_MSB 14 +#define RX_MSDU_END_ORDER_MASK 0x00004000 + +#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x00000078 +#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x00008000 + +#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_OVERFLOW_ERR_LSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x00010000 + +#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x00020000 + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 + +#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x00080000 + +#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x00000078 +#define RX_MSDU_END_SA_IDX_INVALID_LSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x00100000 + +#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x00000078 +#define RX_MSDU_END_DA_IDX_INVALID_LSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x00200000 + +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x00000078 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x00400000 + +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000078 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 + +#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x00000078 +#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x01000000 + +#define RX_MSDU_END_DIRECTED_OFFSET 0x00000078 +#define RX_MSDU_END_DIRECTED_LSB 25 +#define RX_MSDU_END_DIRECTED_MSB 25 +#define RX_MSDU_END_DIRECTED_MASK 0x02000000 + +#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x00000078 +#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x04000000 + +#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x08000000 + +#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x10000000 + +#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_DECRYPT_ERR_LSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MASK 0x20000000 + +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 + +#define RX_MSDU_END_FCS_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_FCS_ERR_LSB 31 +#define RX_MSDU_END_FCS_ERR_MSB 31 +#define RX_MSDU_END_FCS_ERR_MASK 0x80000000 + +#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000007c +#define RX_MSDU_END_RESERVED_31A_LSB 0 +#define RX_MSDU_END_RESERVED_31A_MSB 9 +#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff + +#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000007c +#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 10 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 12 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c00 + +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000007c +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 13 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 + +#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000007c +#define RX_MSDU_END_RESERVED_31B_LSB 14 +#define RX_MSDU_END_RESERVED_31B_MSB 30 +#define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc000 + +#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000007c +#define RX_MSDU_END_MSDU_DONE_LSB 31 +#define RX_MSDU_END_MSDU_DONE_MSB 31 +#define RX_MSDU_END_MSDU_DONE_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_msdu_ext_desc_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_ext_desc_info.h new file mode 100644 index 0000000000000000000000000000000000000000..3fc24d531259a9036968c22ccb3c253d85f0bfc5 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_ext_desc_info.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_EXT_DESC_INFO_H_ +#define _RX_MSDU_EXT_DESC_INFO_H_ + +#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 + +struct rx_msdu_ext_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, + service_code : 9, + priority_valid : 1, + data_offset : 12, + src_link_id : 3, + reserved_0a : 2; +#else + uint32_t reserved_0a : 2, + src_link_id : 3, + data_offset : 12, + priority_valid : 1, + service_code : 9, + reo_destination_indication : 5; +#endif +}; + +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_msdu_link.h b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_link.h new file mode 100644 index 0000000000000000000000000000000000000000..7506bfd60465a2a55cc7175379f2c29b29529808 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_link.h @@ -0,0 +1,917 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_LINK_H_ +#define _RX_MSDU_LINK_H_ + +#include "uniform_descriptor_header.h" +#include "buffer_addr_info.h" +#include "rx_msdu_details.h" +#define NUM_OF_DWORDS_RX_MSDU_LINK 32 + +struct rx_msdu_link { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t receive_queue_number : 16, + first_rx_msdu_link_struct : 1, + reserved_3a : 15; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#else + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t reserved_3a : 15, + first_rx_msdu_link_struct : 1, + receive_queue_number : 16; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#endif +}; + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 + +#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_LINK_RESERVED_3A_LSB 17 +#define RX_MSDU_LINK_RESERVED_3A_MSB 31 +#define RX_MSDU_LINK_RESERVED_3A_MASK 0xfffe0000 + +#define RX_MSDU_LINK_PN_31_0_OFFSET 0x00000010 +#define RX_MSDU_LINK_PN_31_0_LSB 0 +#define RX_MSDU_LINK_PN_31_0_MSB 31 +#define RX_MSDU_LINK_PN_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_PN_63_32_OFFSET 0x00000014 +#define RX_MSDU_LINK_PN_63_32_LSB 0 +#define RX_MSDU_LINK_PN_63_32_MSB 31 +#define RX_MSDU_LINK_PN_63_32_MASK 0xffffffff + +#define RX_MSDU_LINK_PN_95_64_OFFSET 0x00000018 +#define RX_MSDU_LINK_PN_95_64_LSB 0 +#define RX_MSDU_LINK_PN_95_64_MSB 31 +#define RX_MSDU_LINK_PN_95_64_MASK 0xffffffff + +#define RX_MSDU_LINK_PN_127_96_OFFSET 0x0000001c +#define RX_MSDU_LINK_PN_127_96_LSB 0 +#define RX_MSDU_LINK_PN_127_96_MSB 31 +#define RX_MSDU_LINK_PN_127_96_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_msdu_start.h b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..6dbba779511559334b13ae66949381408ff18842 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_start.h @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_START_H_ +#define _RX_MSDU_START_H_ + +#define NUM_OF_DWORDS_RX_MSDU_START 10 + +struct rx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t msdu_length : 14, + stbc : 1, + ipsec_esp : 1, + l3_offset : 7, + ipsec_ah : 1, + l4_offset : 8; + uint32_t msdu_number : 8, + decap_format : 2, + ipv4_proto : 1, + ipv6_proto : 1, + tcp_proto : 1, + udp_proto : 1, + ip_frag : 1, + tcp_only_ack : 1, + da_is_bcast_mcast : 1, + toeplitz_hash_sel : 2, + ip_fixed_header_valid : 1, + ip_extn_header_valid : 1, + tcp_udp_header_valid : 1, + mesh_control_present : 1, + ldpc : 1, + ip4_protocol_ip6_next_header : 8; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t flow_id_toeplitz : 32; + uint32_t user_rssi : 8, + pkt_type : 4, + sgi : 2, + rate_mcs : 4, + receive_bandwidth : 3, + reception_type : 3, + mimo_ss_bitmap : 8; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t vlan_ctag_ci : 16, + vlan_stag_ci : 16; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t l4_offset : 8, + ipsec_ah : 1, + l3_offset : 7, + ipsec_esp : 1, + stbc : 1, + msdu_length : 14; + uint32_t ip4_protocol_ip6_next_header : 8, + ldpc : 1, + mesh_control_present : 1, + tcp_udp_header_valid : 1, + ip_extn_header_valid : 1, + ip_fixed_header_valid : 1, + toeplitz_hash_sel : 2, + da_is_bcast_mcast : 1, + tcp_only_ack : 1, + ip_frag : 1, + udp_proto : 1, + tcp_proto : 1, + ipv6_proto : 1, + ipv4_proto : 1, + decap_format : 2, + msdu_number : 8; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t flow_id_toeplitz : 32; + uint32_t mimo_ss_bitmap : 8, + reception_type : 3, + receive_bandwidth : 3, + rate_mcs : 4, + sgi : 2, + pkt_type : 4, + user_rssi : 8; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t vlan_stag_ci : 16, + vlan_ctag_ci : 16; +#endif +}; + +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MSDU_START_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_START_RESERVED_0_LSB 9 +#define RX_MSDU_START_RESERVED_0_MSB 15 +#define RX_MSDU_START_RESERVED_0_MASK 0x0000fe00 + +#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_START_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_START_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_START_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_START_MSDU_LENGTH_LSB 0 +#define RX_MSDU_START_MSDU_LENGTH_MSB 13 +#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff + +#define RX_MSDU_START_STBC_OFFSET 0x00000004 +#define RX_MSDU_START_STBC_LSB 14 +#define RX_MSDU_START_STBC_MSB 14 +#define RX_MSDU_START_STBC_MASK 0x00004000 + +#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x00000004 +#define RX_MSDU_START_IPSEC_ESP_LSB 15 +#define RX_MSDU_START_IPSEC_ESP_MSB 15 +#define RX_MSDU_START_IPSEC_ESP_MASK 0x00008000 + +#define RX_MSDU_START_L3_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_L3_OFFSET_LSB 16 +#define RX_MSDU_START_L3_OFFSET_MSB 22 +#define RX_MSDU_START_L3_OFFSET_MASK 0x007f0000 + +#define RX_MSDU_START_IPSEC_AH_OFFSET 0x00000004 +#define RX_MSDU_START_IPSEC_AH_LSB 23 +#define RX_MSDU_START_IPSEC_AH_MSB 23 +#define RX_MSDU_START_IPSEC_AH_MASK 0x00800000 + +#define RX_MSDU_START_L4_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_L4_OFFSET_LSB 24 +#define RX_MSDU_START_L4_OFFSET_MSB 31 +#define RX_MSDU_START_L4_OFFSET_MASK 0xff000000 + +#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x00000008 +#define RX_MSDU_START_MSDU_NUMBER_LSB 0 +#define RX_MSDU_START_MSDU_NUMBER_MSB 7 +#define RX_MSDU_START_MSDU_NUMBER_MASK 0x000000ff + +#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_START_DECAP_FORMAT_LSB 8 +#define RX_MSDU_START_DECAP_FORMAT_MSB 9 +#define RX_MSDU_START_DECAP_FORMAT_MASK 0x00000300 + +#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_IPV4_PROTO_LSB 10 +#define RX_MSDU_START_IPV4_PROTO_MSB 10 +#define RX_MSDU_START_IPV4_PROTO_MASK 0x00000400 + +#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_IPV6_PROTO_LSB 11 +#define RX_MSDU_START_IPV6_PROTO_MSB 11 +#define RX_MSDU_START_IPV6_PROTO_MASK 0x00000800 + +#define RX_MSDU_START_TCP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_TCP_PROTO_LSB 12 +#define RX_MSDU_START_TCP_PROTO_MSB 12 +#define RX_MSDU_START_TCP_PROTO_MASK 0x00001000 + +#define RX_MSDU_START_UDP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_UDP_PROTO_LSB 13 +#define RX_MSDU_START_UDP_PROTO_MSB 13 +#define RX_MSDU_START_UDP_PROTO_MASK 0x00002000 + +#define RX_MSDU_START_IP_FRAG_OFFSET 0x00000008 +#define RX_MSDU_START_IP_FRAG_LSB 14 +#define RX_MSDU_START_IP_FRAG_MSB 14 +#define RX_MSDU_START_IP_FRAG_MASK 0x00004000 + +#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x00000008 +#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x00008000 + +#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x00000008 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x00010000 + +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x00000008 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x00060000 + +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x00080000 + +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x00100000 + +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x00200000 + +#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x00000008 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x00400000 + +#define RX_MSDU_START_LDPC_OFFSET 0x00000008 +#define RX_MSDU_START_LDPC_LSB 23 +#define RX_MSDU_START_LDPC_MSB 23 +#define RX_MSDU_START_LDPC_MASK 0x00800000 + +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x00000008 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000 + +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000c +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 31 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff + +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x00000010 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0xffffffff + +#define RX_MSDU_START_USER_RSSI_OFFSET 0x00000014 +#define RX_MSDU_START_USER_RSSI_LSB 0 +#define RX_MSDU_START_USER_RSSI_MSB 7 +#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff + +#define RX_MSDU_START_PKT_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_PKT_TYPE_LSB 8 +#define RX_MSDU_START_PKT_TYPE_MSB 11 +#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f00 + +#define RX_MSDU_START_SGI_OFFSET 0x00000014 +#define RX_MSDU_START_SGI_LSB 12 +#define RX_MSDU_START_SGI_MSB 13 +#define RX_MSDU_START_SGI_MASK 0x00003000 + +#define RX_MSDU_START_RATE_MCS_OFFSET 0x00000014 +#define RX_MSDU_START_RATE_MCS_LSB 14 +#define RX_MSDU_START_RATE_MCS_MSB 17 +#define RX_MSDU_START_RATE_MCS_MASK 0x0003c000 + +#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x00000014 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 18 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 20 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c0000 + +#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_START_RECEPTION_TYPE_MSB 23 +#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e00000 + +#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x00000014 +#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 31 +#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff000000 + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000018 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000001c +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x00000020 +#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 +#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x00000024 +#define RX_MSDU_START_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_START_VLAN_CTAG_CI_MSB 15 +#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff + +#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x00000024 +#define RX_MSDU_START_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_START_VLAN_STAG_CI_MSB 31 +#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_ack_report.h b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_ack_report.h new file mode 100644 index 0000000000000000000000000000000000000000..91bf124633865a289ef3586ce4b54d6e65767d91 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_ack_report.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_ACK_REPORT_H_ +#define _RX_PPDU_ACK_REPORT_H_ + +#include "ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 1 + +struct rx_ppdu_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ack_report ack_report_details; +#else + struct ack_report ack_report_details; +#endif +}; + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x0000000f + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x000000f0 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x00000100 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x0000fe00 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_end_user_stats.h new file mode 100644 index 0000000000000000000000000000000000000000..e08c0dbe0e0fa3d4a455f668d68b2b7593d49fb7 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_end_user_stats.h @@ -0,0 +1,703 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_END_USER_STATS_H_ +#define _RX_PPDU_END_USER_STATS_H_ + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 + +struct rx_ppdu_end_user_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t sta_full_aid : 13, + mcs : 4, + nss : 3, + expected_response_ack_or_ba : 1, + reserved_1a : 11; + uint32_t sw_peer_id : 16, + mpdu_cnt_fcs_err : 11, + sw2rxdma0_buf_source_used : 1, + fw2rxdma_pmac0_buf_source_used : 1, + sw2rxdma1_buf_source_used : 1, + sw2rxdma_exception_buf_source_used : 1, + fw2rxdma_pmac1_buf_source_used : 1; + uint32_t mpdu_cnt_fcs_ok : 11, + frame_control_info_valid : 1, + qos_control_info_valid : 1, + ht_control_info_valid : 1, + data_sequence_control_info_valid : 1, + ht_control_info_null_valid : 1, + rxdma2fw_pmac1_ring_used : 1, + rxdma2reo_ring_used : 1, + rxdma2fw_pmac0_ring_used : 1, + rxdma2sw_ring_used : 1, + rxdma_release_ring_used : 1, + ht_control_field_pkt_type : 4, + rxdma2reo_remote0_ring_used : 1, + rxdma2reo_remote1_ring_used : 1, + reserved_3b : 5; + uint32_t ast_index : 16, + frame_control_field : 16; + uint32_t first_data_seq_ctrl : 16, + qos_control_field : 16; + uint32_t ht_control_field : 32; + uint32_t fcs_ok_bitmap_31_0 : 32; + uint32_t fcs_ok_bitmap_63_32 : 32; + uint32_t udp_msdu_count : 16, + tcp_msdu_count : 16; + uint32_t other_msdu_count : 16, + tcp_ack_msdu_count : 16; + uint32_t sw_response_reference_ptr : 32; + uint32_t received_qos_data_tid_bitmap : 16, + received_qos_data_tid_eosp_bitmap : 16; + uint32_t qosctrl_15_8_tid0 : 8, + qosctrl_15_8_tid1 : 8, + qosctrl_15_8_tid2 : 8, + qosctrl_15_8_tid3 : 8; + uint32_t qosctrl_15_8_tid4 : 8, + qosctrl_15_8_tid5 : 8, + qosctrl_15_8_tid6 : 8, + qosctrl_15_8_tid7 : 8; + uint32_t qosctrl_15_8_tid8 : 8, + qosctrl_15_8_tid9 : 8, + qosctrl_15_8_tid10 : 8, + qosctrl_15_8_tid11 : 8; + uint32_t qosctrl_15_8_tid12 : 8, + qosctrl_15_8_tid13 : 8, + qosctrl_15_8_tid14 : 8, + qosctrl_15_8_tid15 : 8; + uint32_t mpdu_ok_byte_count : 25, + ampdu_delim_ok_count_6_0 : 7; + uint32_t ampdu_delim_err_count : 25, + ampdu_delim_ok_count_13_7 : 7; + uint32_t mpdu_err_byte_count : 25, + ampdu_delim_ok_count_20_14 : 7; + uint32_t non_consecutive_delimiter_err : 16, + retried_msdu_count : 16; + uint32_t ht_control_null_field : 32; + uint32_t sw_response_reference_ptr_ext : 32; + uint32_t corrupted_due_to_fifo_delay : 1, + frame_control_info_null_valid : 1, + frame_control_field_null : 16, + retried_mpdu_count : 11, + reserved_23a : 3; + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_24a : 4, + frame_control_info_mgmt_ctrl_valid : 1, + mac_addr_ad2_valid : 1, + mcast_bcast : 1, + frame_control_field_mgmt_ctrl : 16; + uint32_t user_ppdu_len : 24, + reserved_25a : 8; + uint32_t mac_addr_ad2_31_0 : 32; + uint32_t mac_addr_ad2_47_32 : 16, + amsdu_msdu_count : 16; + uint32_t non_amsdu_msdu_count : 16, + ucast_msdu_count : 16; + uint32_t bcast_msdu_count : 16, + mcast_bcast_msdu_count : 16; +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t reserved_1a : 11, + expected_response_ack_or_ba : 1, + nss : 3, + mcs : 4, + sta_full_aid : 13; + uint32_t fw2rxdma_pmac1_buf_source_used : 1, + sw2rxdma_exception_buf_source_used : 1, + sw2rxdma1_buf_source_used : 1, + fw2rxdma_pmac0_buf_source_used : 1, + sw2rxdma0_buf_source_used : 1, + mpdu_cnt_fcs_err : 11, + sw_peer_id : 16; + uint32_t reserved_3b : 5, + rxdma2reo_remote1_ring_used : 1, + rxdma2reo_remote0_ring_used : 1, + ht_control_field_pkt_type : 4, + rxdma_release_ring_used : 1, + rxdma2sw_ring_used : 1, + rxdma2fw_pmac0_ring_used : 1, + rxdma2reo_ring_used : 1, + rxdma2fw_pmac1_ring_used : 1, + ht_control_info_null_valid : 1, + data_sequence_control_info_valid : 1, + ht_control_info_valid : 1, + qos_control_info_valid : 1, + frame_control_info_valid : 1, + mpdu_cnt_fcs_ok : 11; + uint32_t frame_control_field : 16, + ast_index : 16; + uint32_t qos_control_field : 16, + first_data_seq_ctrl : 16; + uint32_t ht_control_field : 32; + uint32_t fcs_ok_bitmap_31_0 : 32; + uint32_t fcs_ok_bitmap_63_32 : 32; + uint32_t tcp_msdu_count : 16, + udp_msdu_count : 16; + uint32_t tcp_ack_msdu_count : 16, + other_msdu_count : 16; + uint32_t sw_response_reference_ptr : 32; + uint32_t received_qos_data_tid_eosp_bitmap : 16, + received_qos_data_tid_bitmap : 16; + uint32_t qosctrl_15_8_tid3 : 8, + qosctrl_15_8_tid2 : 8, + qosctrl_15_8_tid1 : 8, + qosctrl_15_8_tid0 : 8; + uint32_t qosctrl_15_8_tid7 : 8, + qosctrl_15_8_tid6 : 8, + qosctrl_15_8_tid5 : 8, + qosctrl_15_8_tid4 : 8; + uint32_t qosctrl_15_8_tid11 : 8, + qosctrl_15_8_tid10 : 8, + qosctrl_15_8_tid9 : 8, + qosctrl_15_8_tid8 : 8; + uint32_t qosctrl_15_8_tid15 : 8, + qosctrl_15_8_tid14 : 8, + qosctrl_15_8_tid13 : 8, + qosctrl_15_8_tid12 : 8; + uint32_t ampdu_delim_ok_count_6_0 : 7, + mpdu_ok_byte_count : 25; + uint32_t ampdu_delim_ok_count_13_7 : 7, + ampdu_delim_err_count : 25; + uint32_t ampdu_delim_ok_count_20_14 : 7, + mpdu_err_byte_count : 25; + uint32_t retried_msdu_count : 16, + non_consecutive_delimiter_err : 16; + uint32_t ht_control_null_field : 32; + uint32_t sw_response_reference_ptr_ext : 32; + uint32_t reserved_23a : 3, + retried_mpdu_count : 11, + frame_control_field_null : 16, + frame_control_info_null_valid : 1, + corrupted_due_to_fifo_delay : 1; + uint32_t frame_control_field_mgmt_ctrl : 16, + mcast_bcast : 1, + mac_addr_ad2_valid : 1, + frame_control_info_mgmt_ctrl_valid : 1, + reserved_24a : 4, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_25a : 8, + user_ppdu_len : 24; + uint32_t mac_addr_ad2_31_0 : 32; + uint32_t amsdu_msdu_count : 16, + mac_addr_ad2_47_32 : 16; + uint32_t ucast_msdu_count : 16, + non_amsdu_msdu_count : 16; + uint32_t mcast_bcast_msdu_count : 16, + bcast_msdu_count : 16; +#endif +}; + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000fe00 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 0 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 12 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff + +#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_MCS_LSB 13 +#define RX_PPDU_END_USER_STATS_MCS_MSB 16 +#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e000 + +#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_NSS_LSB 17 +#define RX_PPDU_END_USER_STATS_NSS_MSB 19 +#define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e0000 + +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 20 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 20 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x00100000 + +#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 21 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 31 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe00000 + +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x07ff0000 + +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x08000000 + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x10000000 + +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x20000000 + +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x40000000 + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x80000000 + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 0 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 10 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 11 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 11 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x00000800 + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 12 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 12 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x00001000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 13 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 13 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x00002000 + +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 14 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 14 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00004000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 15 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 15 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x00008000 + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 16 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 16 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x00010000 + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 17 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 17 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x00020000 + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 18 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 18 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x00040000 + +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 19 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 19 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x00080000 + +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 20 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 20 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x00100000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 21 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 24 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e00000 + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 25 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 25 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x02000000 + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 26 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 26 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x04000000 + +#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 27 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 31 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xf8000000 + +#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 0 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 15 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000001c +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 0 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 31 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x00000020 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000002c +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 31 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 24 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 25 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 31 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 24 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 25 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 31 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x00000054 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x00000058 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 1 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 1 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 2 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 17 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc + +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 18 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 28 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc0000 + +#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 29 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 31 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe0000000 + +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x00001e00 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x00002000 + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x00004000 + +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x00008000 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x00000064 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 0 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 23 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff + +#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x00000064 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 24 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 31 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x00000068 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000006c +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 0 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 15 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000006c +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x00000070 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x00000070 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x00000074 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x00000074 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_end_user_stats_ext.h new file mode 100644 index 0000000000000000000000000000000000000000..8c41ae3057497e93aa638d90824a3d8afeb606b9 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_end_user_stats_ext.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ +#define _RX_PPDU_END_USER_STATS_EXT_H_ + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 + +struct rx_ppdu_end_user_stats_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; + uint32_t fcs_ok_bitmap_127_96 : 32; + uint32_t fcs_ok_bitmap_159_128 : 32; + uint32_t fcs_ok_bitmap_191_160 : 32; + uint32_t fcs_ok_bitmap_223_192 : 32; + uint32_t fcs_ok_bitmap_255_224 : 32; + uint32_t corrupted_due_to_fifo_delay : 1, + reserved_7a : 31; +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; + uint32_t fcs_ok_bitmap_127_96 : 32; + uint32_t fcs_ok_bitmap_159_128 : 32; + uint32_t fcs_ok_bitmap_191_160 : 32; + uint32_t fcs_ok_bitmap_223_192 : 32; + uint32_t fcs_ok_bitmap_255_224 : 32; + uint32_t reserved_7a : 31, + corrupted_due_to_fifo_delay : 1; +#endif +}; + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000fe00 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000001c +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000001c +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_no_ack_report.h b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_no_ack_report.h new file mode 100644 index 0000000000000000000000000000000000000000..c98fd8f9ac8c217667c0a8ac6f212ac2c8e9c81c --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_no_ack_report.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_NO_ACK_REPORT_H_ +#define _RX_PPDU_NO_ACK_REPORT_H_ + +#include "no_ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 + +struct rx_ppdu_no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct no_ack_report no_ack_report_details; +#else + struct no_ack_report no_ack_report_details; +#endif +}; + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x000000f0 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x0000ff00 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x00000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0xffff0000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x00000004 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 23 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x01000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 29 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe0000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x00000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0xff000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 12 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_start.h b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..174b88cda1fab984ca8f1b3a486313f26b32d306 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_start.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_START_H_ +#define _RX_PPDU_START_H_ + +#define NUM_OF_DWORDS_RX_PPDU_START 5 + +struct rx_ppdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + preamble_time_to_rxframe : 8, + reserved_0a : 8; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t rxframe_assert_timestamp : 32; +#else + uint32_t reserved_0a : 8, + preamble_time_to_rxframe : 8, + phy_ppdu_id : 16; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t rxframe_assert_timestamp : 32; +#endif +}; + +#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x00000000 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x00ff0000 + +#define RX_PPDU_START_RESERVED_0A_OFFSET 0x00000000 +#define RX_PPDU_START_RESERVED_0A_LSB 24 +#define RX_PPDU_START_RESERVED_0A_MSB 31 +#define RX_PPDU_START_RESERVED_0A_MASK 0xff000000 + +#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x00000004 +#define RX_PPDU_START_SW_PHY_META_DATA_LSB 0 +#define RX_PPDU_START_SW_PHY_META_DATA_MSB 31 +#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000008 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000c +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x00000010 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_start_user_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_start_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..544532ca7734ae51100d581324513afa58afb892 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_start_user_info.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_START_USER_INFO_H_ +#define _RX_PPDU_START_USER_INFO_H_ + +#include "receive_user_info.h" +#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8 + +struct rx_ppdu_start_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_user_info receive_user_info_details; +#else + struct receive_user_info receive_user_info_details; +#endif +}; + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 3 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 5 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 18 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00070000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 19 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f80000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x000000fe + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x00000700 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x00003800 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x00004000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00008000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x000f0000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x00f00000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x0f000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0xf0000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 5 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 6 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c0 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 8 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 13 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f00 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 21 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f0000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 22 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c00000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 29 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 30 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc0000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x00000010 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0xffffffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x00000014 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x00000018 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0xffffffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000001c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_preamble.h b/drivers/staging/fw-api/hw/peach/v1/rx_preamble.h new file mode 100644 index 0000000000000000000000000000000000000000..75862b6e9a8c1029945d1c67ac7b4af797dc0d8c --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_preamble.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PREAMBLE_H_ +#define _RX_PREAMBLE_H_ + +#define NUM_OF_DWORDS_RX_PREAMBLE 1 + +struct rx_preamble { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, + pkt_type : 4, + direction : 1, + reserved_0a : 21; +#else + uint32_t reserved_0a : 21, + direction : 1, + pkt_type : 4, + num_users : 6; +#endif +}; + +#define RX_PREAMBLE_NUM_USERS_OFFSET 0x00000000 +#define RX_PREAMBLE_NUM_USERS_LSB 0 +#define RX_PREAMBLE_NUM_USERS_MSB 5 +#define RX_PREAMBLE_NUM_USERS_MASK 0x0000003f + +#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x00000000 +#define RX_PREAMBLE_PKT_TYPE_LSB 6 +#define RX_PREAMBLE_PKT_TYPE_MSB 9 +#define RX_PREAMBLE_PKT_TYPE_MASK 0x000003c0 + +#define RX_PREAMBLE_DIRECTION_OFFSET 0x00000000 +#define RX_PREAMBLE_DIRECTION_LSB 10 +#define RX_PREAMBLE_DIRECTION_MSB 10 +#define RX_PREAMBLE_DIRECTION_MASK 0x00000400 + +#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x00000000 +#define RX_PREAMBLE_RESERVED_0A_LSB 11 +#define RX_PREAMBLE_RESERVED_0A_MSB 31 +#define RX_PREAMBLE_RESERVED_0A_MASK 0xfffff800 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue.h b/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue.h new file mode 100644 index 0000000000000000000000000000000000000000..be630859dfd40daa3903ab55196b72c039f66d36 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue.h @@ -0,0 +1,514 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_REO_QUEUE_H_ +#define _RX_REO_QUEUE_H_ + +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE 32 + +struct rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t receive_queue_number : 16, + reserved_1b : 16; + uint32_t vld : 1, + associated_link_descriptor_counter : 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + ba_window_size : 10, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + pn_size : 2, + ignore_ampdu_flag : 1, + reserved_2b : 4; + uint32_t svld : 1, + ssn : 12, + current_index : 10, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + reserved_3a : 6, + pn_valid : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t ptr_to_next_aging_queue_31_0 : 32; + uint32_t ptr_to_next_aging_queue_39_32 : 8, + reserved_11a : 24; + uint32_t ptr_to_previous_aging_queue_31_0 : 32; + uint32_t ptr_to_previous_aging_queue_39_32 : 8, + statistics_counter_index : 6, + reserved_13a : 18; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t last_sn_reg_index : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + window_jump_2k : 4, + hole_count : 16; + uint32_t aging_drop_mpdu_count : 16, + aging_drop_interval : 8, + reserved_30 : 8; + uint32_t reserved_31 : 32; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1b : 16, + receive_queue_number : 16; + uint32_t reserved_2b : 4, + ignore_ampdu_flag : 1, + pn_size : 2, + pn_handling_enable : 1, + pn_shall_be_uneven : 1, + pn_shall_be_even : 1, + pn_check_needed : 1, + ba_window_size : 10, + oor_mode : 1, + chk_2k_mode : 1, + rty : 1, + bar : 1, + ac : 2, + soft_reorder_enable : 1, + disable_duplicate_detection : 1, + associated_link_descriptor_counter : 2, + vld : 1; + uint32_t pn_valid : 1, + reserved_3a : 6, + pn_error_detected_flag : 1, + seq_2k_error_detected_flag : 1, + current_index : 10, + ssn : 12, + svld : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t ptr_to_next_aging_queue_31_0 : 32; + uint32_t reserved_11a : 24, + ptr_to_next_aging_queue_39_32 : 8; + uint32_t ptr_to_previous_aging_queue_31_0 : 32; + uint32_t reserved_13a : 18, + statistics_counter_index : 6, + ptr_to_previous_aging_queue_39_32 : 8; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_msdu_count : 25, + current_mpdu_count : 7; + uint32_t duplicate_count : 16, + forward_due_to_bar_count : 6, + timeout_count : 6, + last_sn_reg_index : 4; + uint32_t bar_received_count : 8, + frames_in_order_count : 24; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t hole_count : 16, + window_jump_2k : 4, + late_receive_mpdu_count : 12; + uint32_t reserved_30 : 8, + aging_drop_interval : 8, + aging_drop_mpdu_count : 16; + uint32_t reserved_31 : 32; +#endif +}; + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 +#define RX_REO_QUEUE_RESERVED_1B_LSB 16 +#define RX_REO_QUEUE_RESERVED_1B_MSB 31 +#define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 + +#define RX_REO_QUEUE_VLD_OFFSET 0x00000008 +#define RX_REO_QUEUE_VLD_LSB 0 +#define RX_REO_QUEUE_VLD_MSB 0 +#define RX_REO_QUEUE_VLD_MASK 0x00000001 + +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 + +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 + +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 + +#define RX_REO_QUEUE_AC_OFFSET 0x00000008 +#define RX_REO_QUEUE_AC_LSB 5 +#define RX_REO_QUEUE_AC_MSB 6 +#define RX_REO_QUEUE_AC_MASK 0x00000060 + +#define RX_REO_QUEUE_BAR_OFFSET 0x00000008 +#define RX_REO_QUEUE_BAR_LSB 7 +#define RX_REO_QUEUE_BAR_MSB 7 +#define RX_REO_QUEUE_BAR_MASK 0x00000080 + +#define RX_REO_QUEUE_RTY_OFFSET 0x00000008 +#define RX_REO_QUEUE_RTY_LSB 8 +#define RX_REO_QUEUE_RTY_MSB 8 +#define RX_REO_QUEUE_RTY_MASK 0x00000100 + +#define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 + +#define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_OOR_MODE_LSB 10 +#define RX_REO_QUEUE_OOR_MODE_MSB 10 +#define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 + +#define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 + +#define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 + +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 + +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 + +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 + +#define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SIZE_LSB 25 +#define RX_REO_QUEUE_PN_SIZE_MSB 26 +#define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 + +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 + +#define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 +#define RX_REO_QUEUE_RESERVED_2B_LSB 28 +#define RX_REO_QUEUE_RESERVED_2B_MSB 31 +#define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 + +#define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c +#define RX_REO_QUEUE_SVLD_LSB 0 +#define RX_REO_QUEUE_SVLD_MSB 0 +#define RX_REO_QUEUE_SVLD_MASK 0x00000001 + +#define RX_REO_QUEUE_SSN_OFFSET 0x0000000c +#define RX_REO_QUEUE_SSN_LSB 1 +#define RX_REO_QUEUE_SSN_MSB 12 +#define RX_REO_QUEUE_SSN_MASK 0x00001ffe + +#define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c +#define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 +#define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 +#define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 + +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 + +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 + +#define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c +#define RX_REO_QUEUE_RESERVED_3A_LSB 25 +#define RX_REO_QUEUE_RESERVED_3A_MSB 30 +#define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 + +#define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_VALID_LSB 31 +#define RX_REO_QUEUE_PN_VALID_MSB 31 +#define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 + +#define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_PN_31_0_LSB 0 +#define RX_REO_QUEUE_PN_31_0_MSB 31 +#define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_PN_63_32_LSB 0 +#define RX_REO_QUEUE_PN_63_32_MSB 31 +#define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 +#define RX_REO_QUEUE_PN_95_64_LSB 0 +#define RX_REO_QUEUE_PN_95_64_MSB 31 +#define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c +#define RX_REO_QUEUE_PN_127_96_LSB 0 +#define RX_REO_QUEUE_PN_127_96_MSB 31 +#define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c +#define RX_REO_QUEUE_RESERVED_11A_LSB 8 +#define RX_REO_QUEUE_RESERVED_11A_MSB 31 +#define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00 + +#define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 +#define RX_REO_QUEUE_RESERVED_13A_LSB 14 +#define RX_REO_QUEUE_RESERVED_13A_MSB 31 +#define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000 + +#define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 +#define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 +#define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 +#define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c +#define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 +#define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 +#define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 +#define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff + +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f + +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f + +#define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 + +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +#define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 + +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +#define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 + +#define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_HOLE_COUNT_LSB 16 +#define RX_REO_QUEUE_HOLE_COUNT_MSB 31 +#define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff + +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000 + +#define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_RESERVED_30_LSB 24 +#define RX_REO_QUEUE_RESERVED_30_MSB 31 +#define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000 + +#define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_RESERVED_31_MSB 31 +#define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue_1k.h b/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue_1k.h new file mode 100644 index 0000000000000000000000000000000000000000..410c1d499c51453a8ff3d043cfe7b717849551ab --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue_1k.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_REO_QUEUE_1K_H_ +#define _RX_REO_QUEUE_1K_H_ + +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32 + +struct rx_reo_queue_1k { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t rx_bitmap_319_288 : 32; + uint32_t rx_bitmap_351_320 : 32; + uint32_t rx_bitmap_383_352 : 32; + uint32_t rx_bitmap_415_384 : 32; + uint32_t rx_bitmap_447_416 : 32; + uint32_t rx_bitmap_479_448 : 32; + uint32_t rx_bitmap_511_480 : 32; + uint32_t rx_bitmap_543_512 : 32; + uint32_t rx_bitmap_575_544 : 32; + uint32_t rx_bitmap_607_576 : 32; + uint32_t rx_bitmap_639_608 : 32; + uint32_t rx_bitmap_671_640 : 32; + uint32_t rx_bitmap_703_672 : 32; + uint32_t rx_bitmap_735_704 : 32; + uint32_t rx_bitmap_767_736 : 32; + uint32_t rx_bitmap_799_768 : 32; + uint32_t rx_bitmap_831_800 : 32; + uint32_t rx_bitmap_863_832 : 32; + uint32_t rx_bitmap_895_864 : 32; + uint32_t rx_bitmap_927_896 : 32; + uint32_t rx_bitmap_959_928 : 32; + uint32_t rx_bitmap_991_960 : 32; + uint32_t rx_bitmap_1023_992 : 32; + uint32_t reserved_24 : 32; + uint32_t reserved_25 : 32; + uint32_t reserved_26 : 32; + uint32_t reserved_27 : 32; + uint32_t reserved_28 : 32; + uint32_t reserved_29 : 32; + uint32_t reserved_30 : 32; + uint32_t reserved_31 : 32; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t rx_bitmap_319_288 : 32; + uint32_t rx_bitmap_351_320 : 32; + uint32_t rx_bitmap_383_352 : 32; + uint32_t rx_bitmap_415_384 : 32; + uint32_t rx_bitmap_447_416 : 32; + uint32_t rx_bitmap_479_448 : 32; + uint32_t rx_bitmap_511_480 : 32; + uint32_t rx_bitmap_543_512 : 32; + uint32_t rx_bitmap_575_544 : 32; + uint32_t rx_bitmap_607_576 : 32; + uint32_t rx_bitmap_639_608 : 32; + uint32_t rx_bitmap_671_640 : 32; + uint32_t rx_bitmap_703_672 : 32; + uint32_t rx_bitmap_735_704 : 32; + uint32_t rx_bitmap_767_736 : 32; + uint32_t rx_bitmap_799_768 : 32; + uint32_t rx_bitmap_831_800 : 32; + uint32_t rx_bitmap_863_832 : 32; + uint32_t rx_bitmap_895_864 : 32; + uint32_t rx_bitmap_927_896 : 32; + uint32_t rx_bitmap_959_928 : 32; + uint32_t rx_bitmap_991_960 : 32; + uint32_t rx_bitmap_1023_992 : 32; + uint32_t reserved_24 : 32; + uint32_t reserved_25 : 32; + uint32_t reserved_26 : 32; + uint32_t reserved_27 : 32; + uint32_t reserved_28 : 32; + uint32_t reserved_29 : 32; + uint32_t reserved_30 : 32; + uint32_t reserved_31 : 32; +#endif +}; + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060 +#define RX_REO_QUEUE_1K_RESERVED_24_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_24_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064 +#define RX_REO_QUEUE_1K_RESERVED_25_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_25_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068 +#define RX_REO_QUEUE_1K_RESERVED_26_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_26_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c +#define RX_REO_QUEUE_1K_RESERVED_27_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_27_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070 +#define RX_REO_QUEUE_1K_RESERVED_28_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_28_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074 +#define RX_REO_QUEUE_1K_RESERVED_29_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_29_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_1K_RESERVED_30_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_30_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_1K_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_31_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue_ext.h b/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue_ext.h new file mode 100644 index 0000000000000000000000000000000000000000..32c25df690d31f1b057b554e892f51238ad14327 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue_ext.h @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_REO_QUEUE_EXT_H_ +#define _RX_REO_QUEUE_EXT_H_ + +#include "rx_mpdu_link_ptr.h" +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 + +struct rx_reo_queue_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#endif +}; + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004 +#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_response_required_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_response_required_info.h new file mode 100644 index 0000000000000000000000000000000000000000..516ea5180df1827d315f3e7af775f1d9a10f21d4 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_response_required_info.h @@ -0,0 +1,700 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ +#define _RX_RESPONSE_REQUIRED_INFO_H_ + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 15 + +struct rx_response_required_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + su_or_uplink_mu_reception : 1, + trigger_frame_received : 1, + __reserved_g_0012 : 2, + tb___reserved_g_0005_response_required : 2, + mac_security : 1, + filter_pass_monitor_ovrd : 1, + ast_search_incomplete : 1, + r2r_end_status_to_follow : 1, + __reserved_g_0016_listen_cca_check_at_phy_desc : 1, + __reserved_g_0016_listen_indication : 1, + three_or_more_type_subtypes : 1, + wait_sifs_config_valid : 1, + wait_sifs : 2; + uint32_t general_frame_control : 16, + second_frame_control : 16; + uint32_t duration : 16, + pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4, + sgi : 2, + stbc : 1, + ldpc : 1, + ampdu : 1, + vht_ack : 1, + rts_ta_grp_bit : 1; + uint32_t ctrl_frame_soliciting_resp : 1, + ast_fail_for_dot11ax_su_ext : 1, + service_dynamic : 1, + m_pkt : 1, + sta_partial_aid : 12, + group_id : 6, + ctrl_resp_pwr_mgmt : 1, + response_indication : 2, + ndp_indication : 1, + ndp_frame_type : 3, + second_frame_control_valid : 1, + ack_ba_resp_more_data : 1, + reserved_3a : 1; + uint32_t ack_id : 16, + ack_id_ext : 10, + agc_cbw : 3, + service_cbw : 3; + uint32_t response_sta_count : 7, + reserved : 4, + ht_vht_sig_cbw : 3, + cts_cbw : 3, + response_ack_count : 7, + response_assoc_ack_count : 7, + txop_duration_all_ones : 1; + uint32_t response_ba32_count : 7, + response_ba64_count : 7, + response_ba128_count : 7, + response_ba256_count : 7, + multi_tid : 1, + sw_response_tlv_from_crypto : 1, + dot11ax_dl_ul_flag : 1, + emlsr_main_tlv_if : 1; + uint32_t sw_response_frame_length : 16, + response_ba512_count : 7, + response_ba1024_count : 7, + reserved_7a : 2; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t dot11ax_received_format_indication : 1, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_bss_color_id : 6, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_cp_size : 2, + dot11ax_received_ltf_size : 2, + dot11ax_received_coding : 1, + dot11ax_received_dcm : 1, + dot11ax_received_doppler_indication : 1, + dot11ax_received_ext_ru_size : 4, + ftm_fields_valid : 1, + ftm_pe_nss : 3, + ftm_pe_ltf_size : 2, + ftm_pe_content : 1, + ftm_chain_csd_en : 1, + ftm_pe_chain_csd_en : 1; + uint32_t dot11ax_response_rate_source : 8, + dot11ax_ext_response_rate_source : 8, + sw_peer_id : 16; + uint32_t dot11be_puncture_bitmap : 16, + dot11be_response : 1, + punctured_response : 1, + eht_duplicate_mode : 2, + force_extra_symbol : 1, + reserved_13a : 5, + u_sig_puncture_pattern_encoding : 6; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t he_a_control_response_time : 12, + reserved_after_struct16 : 4; +#else + uint32_t wait_sifs : 2, + wait_sifs_config_valid : 1, + three_or_more_type_subtypes : 1, + __reserved_g_0016_listen_indication : 1, + __reserved_g_0016_listen_cca_check_at_phy_desc : 1, + r2r_end_status_to_follow : 1, + ast_search_incomplete : 1, + filter_pass_monitor_ovrd : 1, + mac_security : 1, + tb___reserved_g_0005_response_required : 2, + __reserved_g_0012 : 2, + trigger_frame_received : 1, + su_or_uplink_mu_reception : 1, + phy_ppdu_id : 16; + uint32_t second_frame_control : 16, + general_frame_control : 16; + uint32_t rts_ta_grp_bit : 1, + vht_ack : 1, + ampdu : 1, + ldpc : 1, + stbc : 1, + sgi : 2, + rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4, + duration : 16; + uint32_t reserved_3a : 1, + ack_ba_resp_more_data : 1, + second_frame_control_valid : 1, + ndp_frame_type : 3, + ndp_indication : 1, + response_indication : 2, + ctrl_resp_pwr_mgmt : 1, + group_id : 6, + sta_partial_aid : 12, + m_pkt : 1, + service_dynamic : 1, + ast_fail_for_dot11ax_su_ext : 1, + ctrl_frame_soliciting_resp : 1; + uint32_t service_cbw : 3, + agc_cbw : 3, + ack_id_ext : 10, + ack_id : 16; + uint32_t txop_duration_all_ones : 1, + response_assoc_ack_count : 7, + response_ack_count : 7, + cts_cbw : 3, + ht_vht_sig_cbw : 3, + reserved : 4, + response_sta_count : 7; + uint32_t emlsr_main_tlv_if : 1, + dot11ax_dl_ul_flag : 1, + sw_response_tlv_from_crypto : 1, + multi_tid : 1, + response_ba256_count : 7, + response_ba128_count : 7, + response_ba64_count : 7, + response_ba32_count : 7; + uint32_t reserved_7a : 2, + response_ba1024_count : 7, + response_ba512_count : 7, + sw_response_frame_length : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ftm_pe_chain_csd_en : 1, + ftm_chain_csd_en : 1, + ftm_pe_content : 1, + ftm_pe_ltf_size : 2, + ftm_pe_nss : 3, + ftm_fields_valid : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_received_doppler_indication : 1, + dot11ax_received_dcm : 1, + dot11ax_received_coding : 1, + dot11ax_received_ltf_size : 2, + dot11ax_received_cp_size : 2, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_bss_color_id : 6, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_format_indication : 1; + uint32_t sw_peer_id : 16, + dot11ax_ext_response_rate_source : 8, + dot11ax_response_rate_source : 8; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_13a : 5, + force_extra_symbol : 1, + eht_duplicate_mode : 2, + punctured_response : 1, + dot11be_response : 1, + dot11be_puncture_bitmap : 16; + uint32_t reserved_after_struct16 : 4, + he_a_control_response_time : 12; + struct mlo_sta_id_details mlo_sta_id_details_rx; +#endif +}; + +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x00010000 + +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x00020000 + +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x00300000 + +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x00400000 + +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x00800000 + +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x01000000 + +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x02000000 + +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x10000000 + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0xc0000000 + +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x00000004 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x00000004 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff0000 + +#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x000f0000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x00100000 + +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x01e00000 + +#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x06000000 + +#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x08000000 + +#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x10000000 + +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x40000000 + +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 0 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x00000001 + +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 1 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 1 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x00000002 + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 2 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 2 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x00000004 + +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 3 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 3 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x00000008 + +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 4 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff0 + +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 21 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f0000 + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 22 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x00400000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x01800000 + +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x02000000 + +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c000000 + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK 0x40000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x00000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x00000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x03ff0000 + +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x00000010 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x1c000000 + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x00000010 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0xe0000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 6 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 7 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 10 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x00000780 + +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 11 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x00003800 + +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe0000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f000000 + +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x0000007f + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x00003f80 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x001fc000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x0fe00000 + +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x10000000 + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x40000000 + +#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000001c +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000001c +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f0000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000001c +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f800000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc0000000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x00000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0xffffffff + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x00000024 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x00000024 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff0000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x00000028 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0xffffffff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x00000001 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 1 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 1 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x00000002 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 2 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 7 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 8 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 11 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f00 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 12 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x00003000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x00010000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x00020000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 18 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 18 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x00040000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 19 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x00780000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x00800000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 26 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x07000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 27 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x18000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x40000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x00000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x000000ff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x00000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x0000ff00 + +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x00000030 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0xffff0000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x00010000 + +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x00020000 + +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 18 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 19 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c0000 + +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x00100000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e00000 + +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x0fff0000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/peach/v1/rx_rxpcu_classification_overview.h new file mode 100644 index 0000000000000000000000000000000000000000..36bc52b5415cbf78565f4d9c3350cad68ca16202 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_rxpcu_classification_overview.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ + +#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 + +struct rx_rxpcu_classification_overview { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t filter_pass_mpdus : 1, + filter_pass_mpdus_fcs_ok : 1, + monitor_direct_mpdus : 1, + monitor_direct_mpdus_fcs_ok : 1, + monitor_other_mpdus : 1, + monitor_other_mpdus_fcs_ok : 1, + phyrx_abort_received : 1, + filter_pass_monitor_ovrd_mpdus : 1, + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, + reserved_0 : 7, + phy_ppdu_id : 16; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, + filter_pass_monitor_ovrd_mpdus : 1, + phyrx_abort_received : 1, + monitor_other_mpdus_fcs_ok : 1, + monitor_other_mpdus : 1, + monitor_direct_mpdus_fcs_ok : 1, + monitor_direct_mpdus : 1, + filter_pass_mpdus_fcs_ok : 1, + filter_pass_mpdus : 1; +#endif +}; + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_start_param.h b/drivers/staging/fw-api/hw/peach/v1/rx_start_param.h new file mode 100644 index 0000000000000000000000000000000000000000..b10ffb979b3a4a35a71394e2af7310aee5e296ea --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_start_param.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_START_PARAM_H_ +#define _RX_START_PARAM_H_ + +#define NUM_OF_DWORDS_RX_START_PARAM 1 + +struct rx_start_param { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, + reserved_0a : 12, + remaining_rx_time : 16; +#else + uint32_t remaining_rx_time : 16, + reserved_0a : 12, + pkt_type : 4; +#endif +}; + +#define RX_START_PARAM_PKT_TYPE_OFFSET 0x00000000 +#define RX_START_PARAM_PKT_TYPE_LSB 0 +#define RX_START_PARAM_PKT_TYPE_MSB 3 +#define RX_START_PARAM_PKT_TYPE_MASK 0x0000000f + +#define RX_START_PARAM_RESERVED_0A_OFFSET 0x00000000 +#define RX_START_PARAM_RESERVED_0A_LSB 4 +#define RX_START_PARAM_RESERVED_0A_MSB 15 +#define RX_START_PARAM_RESERVED_0A_MASK 0x0000fff0 + +#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x00000000 +#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 +#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 +#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_timing_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_timing_info.h new file mode 100644 index 0000000000000000000000000000000000000000..50c0a41e408c1a091d4a983abe3c1d2fe3ca1e8d --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_timing_info.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_TIMING_INFO_H_ +#define _RX_TIMING_INFO_H_ + +#define NUM_OF_DWORDS_RX_TIMING_INFO 5 + +struct rx_timing_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_timestamp_1_lower_32 : 32; + uint32_t phy_timestamp_1_upper_32 : 32; + uint32_t phy_timestamp_2_lower_32 : 32; + uint32_t phy_timestamp_2_upper_32 : 32; + uint32_t residual_phase_offset : 12, + reserved : 20; +#else + uint32_t phy_timestamp_1_lower_32 : 32; + uint32_t phy_timestamp_1_upper_32 : 32; + uint32_t phy_timestamp_2_lower_32 : 32; + uint32_t phy_timestamp_2_upper_32 : 32; + uint32_t reserved : 20, + residual_phase_offset : 12; +#endif +}; + +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000000 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000004 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x00000008 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000c +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000010 +#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB 0 +#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB 11 +#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define RX_TIMING_INFO_RESERVED_OFFSET 0x00000010 +#define RX_TIMING_INFO_RESERVED_LSB 12 +#define RX_TIMING_INFO_RESERVED_MSB 31 +#define RX_TIMING_INFO_RESERVED_MASK 0xfffff000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_trig_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_trig_info.h new file mode 100644 index 0000000000000000000000000000000000000000..d13b2bed819ba74a2e68e9c11b5467c445e726e0 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rx_trig_info.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_TRIG_INFO_H_ +#define _RX_TRIG_INFO_H_ + +#define NUM_OF_DWORDS_RX_TRIG_INFO 2 + +struct rx_trig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_trigger_frame_type : 2, + trigger_resp_type : 3, + reserved_0 : 27; + uint32_t ppdu_duration : 16, + unique_destination_id : 16; +#else + uint32_t reserved_0 : 27, + trigger_resp_type : 3, + rx_trigger_frame_type : 2; + uint32_t unique_destination_id : 16, + ppdu_duration : 16; +#endif +}; + +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x00000000 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x00000003 + +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x00000000 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x0000001c + +#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x00000000 +#define RX_TRIG_INFO_RESERVED_0_LSB 5 +#define RX_TRIG_INFO_RESERVED_0_MSB 31 +#define RX_TRIG_INFO_RESERVED_0_MASK 0xffffffe0 + +#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x00000004 +#define RX_TRIG_INFO_PPDU_DURATION_LSB 0 +#define RX_TRIG_INFO_PPDU_DURATION_MSB 15 +#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff + +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x00000004 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 16 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 31 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rxpcu_early_rx_indication.h b/drivers/staging/fw-api/hw/peach/v1/rxpcu_early_rx_indication.h new file mode 100644 index 0000000000000000000000000000000000000000..92fcdb29560faca5053e7203b656abf05f6aedf5 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rxpcu_early_rx_indication.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RXPCU_EARLY_RX_INDICATION_H_ +#define _RXPCU_EARLY_RX_INDICATION_H_ + +#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 1 + +struct rxpcu_early_rx_indication { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4, + dot11ax_received_ext_ru_size : 4, + reserved_0a : 19; +#else + uint32_t reserved_0a : 19, + dot11ax_received_ext_ru_size : 4, + rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4; +#endif +}; + +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x0000000f + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x00000010 + +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 8 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x000001e0 + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 9 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 12 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x00001e00 + +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 13 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0xffffe000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/peach/v1/rxpcu_ppdu_end_info.h new file mode 100644 index 0000000000000000000000000000000000000000..3248374744f9e1c06f3e746474b4019b90dc8c28 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rxpcu_ppdu_end_info.h @@ -0,0 +1,861 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RXPCU_PPDU_END_INFO_H_ +#define _RXPCU_PPDU_END_INFO_H_ + +#include "phyrx_abort_request_info.h" +#include "macrx_abort_request_info.h" +#include "rxpcu_ppdu_end_layout_info.h" +#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 31 + +struct rxpcu_ppdu_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t wb_timestamp_lower_32 : 32; + uint32_t wb_timestamp_upper_32 : 32; + uint32_t rx_antenna : 24, + tx_ht_vht_ack : 1, + unsupported_mu_nc : 1, + otp_txbf_disable : 1, + previous_tlv_corrupted : 1, + phyrx_abort_request_info_valid : 1, + macrx_abort_request_info_valid : 1, + reserved : 2; + uint32_t coex_bt_tx_from_start_of_rx : 1, + coex_bt_tx_after_start_of_rx : 1, + coex_wan_tx_from_start_of_rx : 1, + coex_wan_tx_after_start_of_rx : 1, + coex_wlan_tx_from_start_of_rx : 1, + coex_wlan_tx_after_start_of_rx : 1, + mpdu_delimiter_errors_seen : 1, + __reserved_g_0012 : 2, + dialog_token : 8, + follow_up_dialog_token : 8, + bb_captured_channel : 1, + bb_captured_reason : 3, + bb_captured_timeout : 1, + coex_uwb_tx_after_start_of_rx : 1, + coex_uwb_tx_from_start_of_rx : 1; + uint32_t before_mpdu_count_passing_fcs : 10, + before_mpdu_count_failing_fcs : 10, + after_mpdu_count_passing_fcs : 10, + reserved_4 : 2; + uint32_t after_mpdu_count_failing_fcs : 10, + reserved_5 : 22; + uint32_t phy_timestamp_tx_lower_32 : 32; + uint32_t phy_timestamp_tx_upper_32 : 32; + uint32_t bb_length : 16, + bb_data : 1, + reserved_8 : 3, + first_bt_broadcast_status_details : 12; + uint32_t rx_ppdu_duration : 24, + reserved_9 : 8; + uint32_t ast_index : 16, + ast_index_valid : 1, + reserved_10 : 3, + second_bt_broadcast_status_details : 12; + struct phyrx_abort_request_info phyrx_abort_request_info_details; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint16_t pre_bt_broadcast_status_details : 12, + reserved_12a : 4; + uint32_t non_qos_sn_info_valid : 1, + rts_or_trig_protected_ppdu : 1, + rts_or_trig_prot_type : 2, + reserved_13a : 2, + non_qos_sn_highest : 12, + non_qos_sn_highest_retry_setting : 1, + non_qos_sn_lowest : 12, + non_qos_sn_lowest_retry_setting : 1; + uint32_t qos_sn_1_info_valid : 1, + reserved_14a : 1, + qos_sn_1_tid : 4, + qos_sn_1_highest : 12, + qos_sn_1_highest_retry_setting : 1, + qos_sn_1_lowest : 12, + qos_sn_1_lowest_retry_setting : 1; + uint32_t qos_sn_2_info_valid : 1, + reserved_15a : 1, + qos_sn_2_tid : 4, + qos_sn_2_highest : 12, + qos_sn_2_highest_retry_setting : 1, + qos_sn_2_lowest : 12, + qos_sn_2_lowest_retry_setting : 1; + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t corrupted_due_to_fifo_delay : 1, + qos_sn_1_more_frag_state : 1, + qos_sn_1_frag_num_state : 4, + qos_sn_2_more_frag_state : 1, + qos_sn_2_frag_num_state : 4, + rts_or_trig_prot_non_11a : 1, + rts_or_trig_prot_rate_mcs : 4, + rts_or_trig_prot_peer_addr_15_0 : 16; + uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; + uint32_t rts_or_trig_rx_count : 32; + uint32_t cts_or_null_tx_count : 32; + uint32_t rx_ppdu_end_marker : 32; +#else + uint32_t wb_timestamp_lower_32 : 32; + uint32_t wb_timestamp_upper_32 : 32; + uint32_t reserved : 2, + macrx_abort_request_info_valid : 1, + phyrx_abort_request_info_valid : 1, + previous_tlv_corrupted : 1, + otp_txbf_disable : 1, + unsupported_mu_nc : 1, + tx_ht_vht_ack : 1, + rx_antenna : 24; + uint32_t coex_uwb_tx_from_start_of_rx : 1, + coex_uwb_tx_after_start_of_rx : 1, + bb_captured_timeout : 1, + bb_captured_reason : 3, + bb_captured_channel : 1, + follow_up_dialog_token : 8, + dialog_token : 8, + __reserved_g_0012 : 2, + mpdu_delimiter_errors_seen : 1, + coex_wlan_tx_after_start_of_rx : 1, + coex_wlan_tx_from_start_of_rx : 1, + coex_wan_tx_after_start_of_rx : 1, + coex_wan_tx_from_start_of_rx : 1, + coex_bt_tx_after_start_of_rx : 1, + coex_bt_tx_from_start_of_rx : 1; + uint32_t reserved_4 : 2, + after_mpdu_count_passing_fcs : 10, + before_mpdu_count_failing_fcs : 10, + before_mpdu_count_passing_fcs : 10; + uint32_t reserved_5 : 22, + after_mpdu_count_failing_fcs : 10; + uint32_t phy_timestamp_tx_lower_32 : 32; + uint32_t phy_timestamp_tx_upper_32 : 32; + uint32_t first_bt_broadcast_status_details : 12, + reserved_8 : 3, + bb_data : 1, + bb_length : 16; + uint32_t reserved_9 : 8, + rx_ppdu_duration : 24; + uint32_t second_bt_broadcast_status_details : 12, + reserved_10 : 3, + ast_index_valid : 1, + ast_index : 16; + struct phyrx_abort_request_info phyrx_abort_request_info_details; + uint32_t reserved_12a : 4, + pre_bt_broadcast_status_details : 12; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint32_t non_qos_sn_lowest_retry_setting : 1, + non_qos_sn_lowest : 12, + non_qos_sn_highest_retry_setting : 1, + non_qos_sn_highest : 12, + reserved_13a : 2, + rts_or_trig_prot_type : 2, + rts_or_trig_protected_ppdu : 1, + non_qos_sn_info_valid : 1; + uint32_t qos_sn_1_lowest_retry_setting : 1, + qos_sn_1_lowest : 12, + qos_sn_1_highest_retry_setting : 1, + qos_sn_1_highest : 12, + qos_sn_1_tid : 4, + reserved_14a : 1, + qos_sn_1_info_valid : 1; + uint32_t qos_sn_2_lowest_retry_setting : 1, + qos_sn_2_lowest : 12, + qos_sn_2_highest_retry_setting : 1, + qos_sn_2_highest : 12, + qos_sn_2_tid : 4, + reserved_15a : 1, + qos_sn_2_info_valid : 1; + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t rts_or_trig_prot_peer_addr_15_0 : 16, + rts_or_trig_prot_rate_mcs : 4, + rts_or_trig_prot_non_11a : 1, + qos_sn_2_frag_num_state : 4, + qos_sn_2_more_frag_state : 1, + qos_sn_1_frag_num_state : 4, + qos_sn_1_more_frag_state : 1, + corrupted_due_to_fifo_delay : 1; + uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; + uint32_t rts_or_trig_rx_count : 32; + uint32_t cts_or_null_tx_count : 32; + uint32_t rx_ppdu_end_marker : 32; +#endif +}; + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x00ffffff + +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x01000000 + +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x02000000 + +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x04000000 + +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000 + +#define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 0 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 0 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 1 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 1 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 2 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 2 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004 + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 3 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008 + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 4 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010 + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 5 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020 + +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 6 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 6 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040 + +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 9 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 16 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe00 + +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 17 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 24 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000 + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 25 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 25 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x02000000 + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 26 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 28 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c000000 + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 29 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 29 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x20000000 + +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_LSB 30 +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_MSB 30 +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_MASK 0x40000000 + +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_LSB 31 +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_MSB 31 +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00 + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000 + +#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 9 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff + +#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 10 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc00 + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x0000ffff + +#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x00010000 + +#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x000e0000 + +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 0 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 23 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff + +#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 24 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff000000 + +#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x0000ffff + +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x00010000 + +#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x000e0000 + +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 7 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 8 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 9 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 10 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 10 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x00000400 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB 11 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB 11 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x00000800 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 12 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 12 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x00001000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB 13 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB 13 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK 0x00002000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB 14 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB 14 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK 0x00004000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 15 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x00008000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 31 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000 + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0fff0000 + +#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 0 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 0 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB 1 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB 1 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB 2 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB 3 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK 0x0000000c + +#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 4 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 5 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x00000030 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 6 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 17 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc0 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 18 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 18 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x00040000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 19 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 30 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff80000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 31 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 31 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x0000003c + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x0003ffc0 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x00040000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x7ff80000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 17 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc0 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x00040000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 19 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 30 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff80000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x00000003 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x000000fc + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x00003f00 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x000fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x03f00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 5 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 11 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 12 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 17 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 18 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 30 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0xe0000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 25 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x00000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x00000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x00000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0xff000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000005c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000005c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 16 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000005c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x00000060 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x00000064 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x0000003c + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x00000040 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x00000780 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB 11 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB 11 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK 0x00000800 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB 12 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB 15 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK 0x0000f000 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB 16 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB 31 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK 0xffff0000 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET 0x0000006c +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB 0 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB 31 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET 0x00000070 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB 0 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB 31 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET 0x00000074 +#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB 0 +#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB 31 +#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x00000078 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 0 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 31 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rxpcu_ppdu_end_layout_info.h b/drivers/staging/fw-api/hw/peach/v1/rxpcu_ppdu_end_layout_info.h new file mode 100644 index 0000000000000000000000000000000000000000..9f8f00dd9d5bd3f1c2c1012b86b5f01a6cb5648d --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rxpcu_ppdu_end_layout_info.h @@ -0,0 +1,332 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ +#define _RXPCU_PPDU_END_LAYOUT_INFO_H_ + +#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 + +struct rxpcu_ppdu_end_layout_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_legacy_offset : 2, + l_sig_a_offset : 6, + l_sig_b_offset : 6, + ht_sig_offset : 6, + vht_sig_a_offset : 6, + repeat_l_sig_a_offset : 6; + uint32_t he_sig_a_su_offset : 6, + he_sig_a_mu_dl_offset : 6, + he_sig_a_mu_ul_offset : 6, + generic_u_sig_offset : 6, + rssi_ht_offset : 7, + reserved_1a : 1; + uint32_t vht_sig_b_su20_offset : 7, + vht_sig_b_su40_offset : 7, + vht_sig_b_su80_offset : 7, + vht_sig_b_su160_offset : 7, + reserved_2a : 4; + uint32_t vht_sig_b_mu20_offset : 7, + vht_sig_b_mu40_offset : 7, + vht_sig_b_mu80_offset : 7, + vht_sig_b_mu160_offset : 7, + reserved_3a : 4; + uint32_t he_sig_b1_mu_offset : 7, + he_sig_b2_mu_offset : 7, + he_sig_b2_ofdma_offset : 7, + first_generic_eht_sig_offset : 7, + multiple_generic_eht_sig_included : 1, + reserved_4a : 3; + uint32_t common_user_info_offset : 7, + first_debug_info_offset : 8, + multiple_debug_info_included : 1, + first_other_receive_info_offset : 8, + multiple_other_receive_info_included : 1, + reserved_5a : 7; + uint32_t data_done_offset : 8, + generated_cbf_details_offset : 8, + pkt_end_part1_offset : 8, + location_offset : 8; + uint32_t __reserved_g_0011 : 8, + pkt_end_offset : 8, + abort_request_ack_offset : 8, + reserved_7a : 8; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; +#else + uint32_t repeat_l_sig_a_offset : 6, + vht_sig_a_offset : 6, + ht_sig_offset : 6, + l_sig_b_offset : 6, + l_sig_a_offset : 6, + rssi_legacy_offset : 2; + uint32_t reserved_1a : 1, + rssi_ht_offset : 7, + generic_u_sig_offset : 6, + he_sig_a_mu_ul_offset : 6, + he_sig_a_mu_dl_offset : 6, + he_sig_a_su_offset : 6; + uint32_t reserved_2a : 4, + vht_sig_b_su160_offset : 7, + vht_sig_b_su80_offset : 7, + vht_sig_b_su40_offset : 7, + vht_sig_b_su20_offset : 7; + uint32_t reserved_3a : 4, + vht_sig_b_mu160_offset : 7, + vht_sig_b_mu80_offset : 7, + vht_sig_b_mu40_offset : 7, + vht_sig_b_mu20_offset : 7; + uint32_t reserved_4a : 3, + multiple_generic_eht_sig_included : 1, + first_generic_eht_sig_offset : 7, + he_sig_b2_ofdma_offset : 7, + he_sig_b2_mu_offset : 7, + he_sig_b1_mu_offset : 7; + uint32_t reserved_5a : 7, + multiple_other_receive_info_included : 1, + first_other_receive_info_offset : 8, + multiple_debug_info_included : 1, + first_debug_info_offset : 8, + common_user_info_offset : 7; + uint32_t location_offset : 8, + pkt_end_part1_offset : 8, + generated_cbf_details_offset : 8, + data_done_offset : 8; + uint32_t reserved_7a : 8, + abort_request_ack_offset : 8, + pkt_end_offset : 8, + __reserved_g_0011 : 8; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; +#endif +}; + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/rxpt_classify_info.h b/drivers/staging/fw-api/hw/peach/v1/rxpt_classify_info.h new file mode 100644 index 0000000000000000000000000000000000000000..e87054cf2dfb853a84eb134fa945de5b82128e9b --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/rxpt_classify_info.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RXPT_CLASSIFY_INFO_H_ +#define _RXPT_CLASSIFY_INFO_H_ + +#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 + +struct rxpt_classify_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, + lmac_peer_id_msb : 2, + use_flow_id_toeplitz_clfy : 1, + pkt_selection_fp_ucast_data : 1, + pkt_selection_fp_mcast_data : 1, + pkt_selection_fp_1000 : 1, + rxdma0_source_ring_selection : 3, + rxdma0_destination_ring_selection : 3, + mcast_echo_drop_enable : 1, + wds_learning_detect_en : 1, + intrabss_check_en : 1, + use_ppe : 1, + ppe_routing_enable : 1, + cce_source_sel_en : 1, + reserved_0b : 9; +#else + uint32_t reserved_0b : 9, + cce_source_sel_en : 1, + ppe_routing_enable : 1, + use_ppe : 1, + intrabss_check_en : 1, + wds_learning_detect_en : 1, + mcast_echo_drop_enable : 1, + rxdma0_destination_ring_selection : 3, + rxdma0_source_ring_selection : 3, + pkt_selection_fp_1000 : 1, + pkt_selection_fp_mcast_data : 1, + pkt_selection_fp_ucast_data : 1, + use_flow_id_toeplitz_clfy : 1, + lmac_peer_id_msb : 2, + reo_destination_indication : 5; +#endif +}; + +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000 + +#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000 + +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000 + +#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB 22 +#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB 22 +#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK 0x00400000 + +#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 23 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xff800000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/seq_hwio.h b/drivers/staging/fw-api/hw/peach/v1/seq_hwio.h new file mode 100644 index 0000000000000000000000000000000000000000..576abae9ee69e8340f6a058f4e0fbc3f3ae55590 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/seq_hwio.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef __SEQ_H__ +#define __SEQ_H__ + +#include "HALhwio.h" + +#define SEQ_INH(base, regtype, reg) \ + SEQ_##regtype##_INH(base, reg) + +#define SEQ_INMH(base, regtype, reg, mask) \ + SEQ_##regtype##_INMH(base, reg, mask) + +#define SEQ_INFH(base, regtype, reg, fld) \ + (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) + +#define SEQ_OUTH(base, regtype, reg, val) \ + SEQ_##regtype##_OUTH(base, reg, val) + +#define SEQ_OUTMH(base, regtype, reg, mask, val) \ + SEQ_##regtype##_OUTMH(base, reg, mask, val) + +#define SEQ_OUTFH(base, regtype, reg, fld, val) \ + SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) + +typedef enum { + SEC, + MS, + US, + NS +} SEQ_TimeUnit; + +extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); + +extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); + +#endif + diff --git a/drivers/staging/fw-api/hw/peach/v1/tcl_data_cmd.h b/drivers/staging/fw-api/hw/peach/v1/tcl_data_cmd.h new file mode 100644 index 0000000000000000000000000000000000000000..388b6dd7a30187b249c4c8d66db391545daefa6f --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tcl_data_cmd.h @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TCL_DATA_CMD_H_ +#define _TCL_DATA_CMD_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_TCL_DATA_CMD 8 + +struct tcl_data_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; + uint32_t tcl_cmd_type : 1, + buf_or_ext_desc_type : 1, + bank_id : 6, + tx_notify_frame : 3, + header_length_read_sel : 1, + buffer_timestamp : 19, + buffer_timestamp_valid : 1; + uint32_t reserved_3a : 16, + tcl_cmd_number : 16; + uint32_t data_length : 16, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + to_fw : 1, + reserved_4a : 1, + packet_offset : 9; + uint32_t hlos_tid_overwrite : 1, + flow_override_enable : 1, + who_classify_info_sel : 2, + hlos_tid : 4, + flow_override : 1, + pmac_id : 2, + msdu_color : 2, + reserved_5a : 11, + vdev_id : 8; + uint32_t search_index : 20, + cache_set_num : 4, + index_lookup_override : 1, + reserved_6a : 7; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_addr_info; + uint32_t buffer_timestamp_valid : 1, + buffer_timestamp : 19, + header_length_read_sel : 1, + tx_notify_frame : 3, + bank_id : 6, + buf_or_ext_desc_type : 1, + tcl_cmd_type : 1; + uint32_t tcl_cmd_number : 16, + reserved_3a : 16; + uint32_t packet_offset : 9, + reserved_4a : 1, + to_fw : 1, + tcp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + ipv4_checksum_en : 1, + data_length : 16; + uint32_t vdev_id : 8, + reserved_5a : 11, + msdu_color : 2, + pmac_id : 2, + flow_override : 1, + hlos_tid : 4, + who_classify_info_sel : 2, + flow_override_enable : 1, + hlos_tid_overwrite : 1; + uint32_t reserved_6a : 7, + index_lookup_override : 1, + cache_set_num : 4, + search_index : 20; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001 + +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002 + +#define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BANK_ID_LSB 2 +#define TCL_DATA_CMD_BANK_ID_MSB 7 +#define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc + +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700 + +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800 + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000 + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000 + +#define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c +#define TCL_DATA_CMD_RESERVED_3A_LSB 0 +#define TCL_DATA_CMD_RESERVED_3A_MSB 15 +#define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff + +#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c +#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000 + +#define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010 +#define TCL_DATA_CMD_DATA_LENGTH_LSB 0 +#define TCL_DATA_CMD_DATA_LENGTH_MSB 15 +#define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff + +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000 + +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 + +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 + +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 + +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 + +#define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010 +#define TCL_DATA_CMD_TO_FW_LSB 21 +#define TCL_DATA_CMD_TO_FW_MSB 21 +#define TCL_DATA_CMD_TO_FW_MASK 0x00200000 + +#define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010 +#define TCL_DATA_CMD_RESERVED_4A_LSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000 + +#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010 +#define TCL_DATA_CMD_PACKET_OFFSET_LSB 23 +#define TCL_DATA_CMD_PACKET_OFFSET_MSB 31 +#define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000 + +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001 + +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002 + +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c + +#define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_LSB 4 +#define TCL_DATA_CMD_HLOS_TID_MSB 7 +#define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0 + +#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100 + +#define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_PMAC_ID_LSB 9 +#define TCL_DATA_CMD_PMAC_ID_MSB 10 +#define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600 + +#define TCL_DATA_CMD_MSDU_COLOR_OFFSET 0x00000014 +#define TCL_DATA_CMD_MSDU_COLOR_LSB 11 +#define TCL_DATA_CMD_MSDU_COLOR_MSB 12 +#define TCL_DATA_CMD_MSDU_COLOR_MASK 0x00001800 + +#define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_DATA_CMD_RESERVED_5A_LSB 13 +#define TCL_DATA_CMD_RESERVED_5A_MSB 23 +#define TCL_DATA_CMD_RESERVED_5A_MASK 0x00ffe000 + +#define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_VDEV_ID_LSB 24 +#define TCL_DATA_CMD_VDEV_ID_MSB 31 +#define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000 + +#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018 +#define TCL_DATA_CMD_SEARCH_INDEX_LSB 0 +#define TCL_DATA_CMD_SEARCH_INDEX_MSB 19 +#define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff + +#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018 +#define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20 +#define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23 +#define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000 + +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000 + +#define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_DATA_CMD_RESERVED_6A_LSB 25 +#define TCL_DATA_CMD_RESERVED_6A_MSB 31 +#define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000 + +#define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_DATA_CMD_RESERVED_7A_LSB 0 +#define TCL_DATA_CMD_RESERVED_7A_MSB 19 +#define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff + +#define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_DATA_CMD_RING_ID_LSB 20 +#define TCL_DATA_CMD_RING_ID_MSB 27 +#define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000 + +#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_DATA_CMD_LOOPING_COUNT_LSB 28 +#define TCL_DATA_CMD_LOOPING_COUNT_MSB 31 +#define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tcl_gse_cmd.h b/drivers/staging/fw-api/hw/peach/v1/tcl_gse_cmd.h new file mode 100644 index 0000000000000000000000000000000000000000..9ab07f469049f5f59bf9dc0b4cadb98a76352211 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tcl_gse_cmd.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TCL_GSE_CMD_H_ +#define _TCL_GSE_CMD_H_ + +#define NUM_OF_DWORDS_TCL_GSE_CMD 8 + +struct tcl_gse_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t control_buffer_addr_31_0 : 32; + uint32_t control_buffer_addr_39_32 : 8, + gse_ctrl : 4, + gse_sel : 1, + status_destination_ring_id : 1, + swap : 1, + index_search_en : 1, + cache_set_num : 4, + reserved_1a : 12; + uint32_t tcl_cmd_type : 1, + reserved_2a : 31; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t control_buffer_addr_31_0 : 32; + uint32_t reserved_1a : 12, + cache_set_num : 4, + index_search_en : 1, + swap : 1, + status_destination_ring_id : 1, + gse_sel : 1, + gse_ctrl : 4, + control_buffer_addr_39_32 : 8; + uint32_t reserved_2a : 31, + tcl_cmd_type : 1; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_CTRL_LSB 8 +#define TCL_GSE_CMD_GSE_CTRL_MSB 11 +#define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00 + +#define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_SEL_LSB 12 +#define TCL_GSE_CMD_GSE_SEL_MSB 12 +#define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000 + +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000 + +#define TCL_GSE_CMD_SWAP_OFFSET 0x00000004 +#define TCL_GSE_CMD_SWAP_LSB 14 +#define TCL_GSE_CMD_SWAP_MSB 14 +#define TCL_GSE_CMD_SWAP_MASK 0x00004000 + +#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000 + +#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004 +#define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16 +#define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19 +#define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000 + +#define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004 +#define TCL_GSE_CMD_RESERVED_1A_LSB 20 +#define TCL_GSE_CMD_RESERVED_1A_MSB 31 +#define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000 + +#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001 + +#define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008 +#define TCL_GSE_CMD_RESERVED_2A_LSB 1 +#define TCL_GSE_CMD_RESERVED_2A_MSB 31 +#define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe + +#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_GSE_CMD_RESERVED_5A_LSB 0 +#define TCL_GSE_CMD_RESERVED_5A_MSB 31 +#define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff + +#define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_GSE_CMD_RESERVED_6A_LSB 0 +#define TCL_GSE_CMD_RESERVED_6A_MSB 31 +#define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff + +#define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_GSE_CMD_RESERVED_7A_LSB 0 +#define TCL_GSE_CMD_RESERVED_7A_MSB 19 +#define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff + +#define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_GSE_CMD_RING_ID_LSB 20 +#define TCL_GSE_CMD_RING_ID_MSB 27 +#define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000 + +#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_GSE_CMD_LOOPING_COUNT_LSB 28 +#define TCL_GSE_CMD_LOOPING_COUNT_MSB 31 +#define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tcl_status_ring.h b/drivers/staging/fw-api/hw/peach/v1/tcl_status_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..8930533a442e9121dee12821b9ddce01b452eacb --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tcl_status_ring.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TCL_STATUS_RING_H_ +#define _TCL_STATUS_RING_H_ + +#define NUM_OF_DWORDS_TCL_STATUS_RING 8 + +struct tcl_status_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t gse_ctrl : 4, + ase_fse_sel : 1, + cache_op_res : 2, + index_search_en : 1, + msdu_cnt_n : 24; + uint32_t msdu_byte_cnt_n : 32; + uint32_t msdu_timestmp_n : 32; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t hash_indx_val : 20, + cache_set_num : 4, + reserved_5a : 8; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t msdu_cnt_n : 24, + index_search_en : 1, + cache_op_res : 2, + ase_fse_sel : 1, + gse_ctrl : 4; + uint32_t msdu_byte_cnt_n : 32; + uint32_t msdu_timestmp_n : 32; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 8, + cache_set_num : 4, + hash_indx_val : 20; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 +#define TCL_STATUS_RING_GSE_CTRL_LSB 0 +#define TCL_STATUS_RING_GSE_CTRL_MSB 3 +#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f + +#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 +#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 + +#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 +#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 +#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 +#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 + +#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 + +#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 +#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 +#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 + +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff + +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff + +#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 +#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 +#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 +#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff + +#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 +#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 +#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 + +#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 +#define TCL_STATUS_RING_RESERVED_5A_LSB 24 +#define TCL_STATUS_RING_RESERVED_5A_MSB 31 +#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 + +#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 +#define TCL_STATUS_RING_RESERVED_6A_LSB 0 +#define TCL_STATUS_RING_RESERVED_6A_MSB 31 +#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff + +#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c +#define TCL_STATUS_RING_RESERVED_7A_LSB 0 +#define TCL_STATUS_RING_RESERVED_7A_MSB 19 +#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff + +#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c +#define TCL_STATUS_RING_RING_ID_LSB 20 +#define TCL_STATUS_RING_RING_ID_MSB 27 +#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 + +#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 +#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 +#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tlv_hdr.h b/drivers/staging/fw-api/hw/peach/v1/tlv_hdr.h new file mode 100644 index 0000000000000000000000000000000000000000..6d25ff3047dcd4eda89e5583d950a856404ac4c4 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tlv_hdr.h @@ -0,0 +1,416 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TLV_HDR_H_ +#define _TLV_HDR_H_ + +#define _TLV_USERID_WIDTH_ 6 +#define _TLV_DATA_WIDTH_ 32 +#define _TLV_TAG_WIDTH_ 9 + +#define _TLV_MRV_EN_LEN_WIDTH_ 9 +#define _TLV_MRV_DIS_LEN_WIDTH_ 12 + +#define _TLV_16_DATA_WIDTH_ 16 +#define _TLV_16_TAG_WIDTH_ 5 +#define _TLV_16_LEN_WIDTH_ 4 +#define _TLV_CTAG_WIDTH_ 5 +#define _TLV_44_DATA_WIDTH_ 44 +#define _TLV_64_DATA_WIDTH_ 64 +#define _TLV_76_DATA_WIDTH_ 64 +#define _TLV_CDATA_WIDTH_ 32 +#define _TLV_CDATA_76_WIDTH_ 64 + +struct tlv_usr_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint16_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_reserved : 6; +#else + uint16_t tlv_reserved : 6, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_usr_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 6; +#else + uint32_t tlv_reserved : 6, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_usr_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_mac_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; + +struct tlv_mac_usr_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_reserved : 10, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 16, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_usr_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, +#endif + tlv_reserved : 32; + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_mac_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + tlv_reserved : 32; +#endif + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_usr_c_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata : _TLV_CDATA_WIDTH_, + pad_44to64_bit : 20; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_52 : 52; + uint64_t tlv_cdata_upper_12 : 12, + pad_76to128_bit : 52; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + tlv_cdata_middle_32 : 32; + uint64_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12, + pad_96to128_bit : 32; +#endif +}; + +struct tlv_usr_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 6; +#else + uint32_t tlv_reserved : 6, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mlo_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mlo_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_usr_c_44_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_upper_12 : 12, + pad_44to64_bit : 20; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t tlv_cdata_upper_12 : 12, + pad_76to96_bit : 20; + uint32_t pad_96to128_bit : 32; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12; + uint32_t pad_96to128_bit : 32; +#endif +}; + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tlv_tag_def.h b/drivers/staging/fw-api/hw/peach/v1/tlv_tag_def.h new file mode 100644 index 0000000000000000000000000000000000000000..bbbd5f376f446210a625f5572195d2410e1ca4ba --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tlv_tag_def.h @@ -0,0 +1,510 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TLV_TAG_DEF_ +#define _TLV_TAG_DEF_ + +typedef enum tlv_tag_def { + WIFIMACTX_CBF_START_E = 0 , + WIFIPHYRX_DATA_E = 1 , + WIFIPHYRX_CBF_DATA_RESP_E = 2 , + WIFIPHYRX_ABORT_REQUEST_E = 3 , + WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , + WIFIMACTX_DATA_RESP_E = 5 , + WIFIMACTX_CBF_DATA_E = 6 , + WIFIMACTX_CBF_DONE_E = 7 , + WIFIPHYRX_LMR_DATA_RESP_E = 8 , + WIFIRXPCU_TO_UCODE_START_E = 9 , + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , + WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , + WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 , + WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , + WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , + WIFIRXPCU_TO_UCODE_END_E = 16 , + WIFIPHYRX_RSSI_LEGACY_20MHZ_E = 28 , + WIFIPHYRX_NC_ABORT_REQUEST_E = 29 , + WIFIPHYRX_PKT_END_20MHZ_E = 30 , + WIFIPHYRX_NC_DATA_E = 31 , + WIFIMACRX_CBF_READ_REQUEST_E = 32 , + WIFIMACRX_CBF_DATA_REQUEST_E = 33 , + WIFIMACRX_EXPECT_NDP_RECEPTION_E = 34 , + WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 35 , + WIFIMACRX_NDP_TIMEOUT_E = 36 , + WIFIMACRX_ABORT_ACK_E = 37 , + WIFIMACRX_REQ_IMPLICIT_FB_E = 38 , + WIFIMACRX_CHAIN_MASK_E = 39 , + WIFIMACRX_NAP_USER_E = 40 , + WIFIMACRX_ABORT_REQUEST_E = 41 , + WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 42 , + WIFIPHYTX_ABORT_ACK_E = 43 , + WIFIPHYTX_ABORT_REQUEST_E = 44 , + WIFIPHYTX_PKT_END_E = 45 , + WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 46 , + WIFIPHYTX_REQUEST_CTRL_INFO_E = 47 , + WIFIPHYTX_DATA_REQUEST_E = 48 , + WIFIPHYTX_BF_CV_LOADING_DONE_E = 49 , + WIFIPHYTX_NAP_ACK_E = 50 , + WIFIPHYTX_NAP_DONE_E = 51 , + WIFIPHYTX_OFF_ACK_E = 52 , + WIFIPHYTX_ON_ACK_E = 53 , + WIFIPHYTX_SYNTH_OFF_ACK_E = 54 , + WIFIPHYTX_DEBUG16_E = 55 , + WIFIMACTX_ABORT_REQUEST_E = 56 , + WIFIMACTX_ABORT_ACK_E = 57 , + WIFIMACTX_PKT_END_E = 58 , + WIFIMACTX_PRE_PHY_DESC_E = 59 , + WIFIMACTX_BF_PARAMS_COMMON_E = 60 , + WIFIMACTX_BF_PARAMS_PER_USER_E = 61 , + WIFIMACTX_PREFETCH_CV_E = 62 , + WIFIMACTX_USER_DESC_COMMON_E = 63 , + WIFIMACTX_USER_DESC_PER_USER_E = 64 , + WIFIEXAMPLE_USER_TLV_16_E = 65 , + WIFIEXAMPLE_TLV_16_E = 66 , + WIFIMACTX_PHY_OFF_E = 67 , + WIFIMACTX_PHY_ON_E = 68 , + WIFIMACTX_SYNTH_OFF_E = 69 , + WIFIMACTX_EXPECT_CBF_COMMON_E = 70 , + WIFIMACTX_EXPECT_CBF_PER_USER_E = 71 , + WIFIMACTX_PHY_DESC_E = 72 , + WIFIMACTX_L_SIG_A_E = 73 , + WIFIMACTX_L_SIG_B_E = 74 , + WIFIMACTX_HT_SIG_E = 75 , + WIFIMACTX_VHT_SIG_A_E = 76 , + WIFIMACTX_VHT_SIG_B_SU20_E = 77 , + WIFIMACTX_VHT_SIG_B_SU40_E = 78 , + WIFIMACTX_VHT_SIG_B_SU80_E = 79 , + WIFIMACTX_VHT_SIG_B_SU160_E = 80 , + WIFIMACTX_VHT_SIG_B_MU20_E = 81 , + WIFIMACTX_VHT_SIG_B_MU40_E = 82 , + WIFIMACTX_VHT_SIG_B_MU80_E = 83 , + WIFIMACTX_VHT_SIG_B_MU160_E = 84 , + WIFIMACTX_SERVICE_E = 85 , + WIFIMACTX_HE_SIG_A_SU_E = 86 , + WIFIMACTX_HE_SIG_A_MU_DL_E = 87 , + WIFIMACTX_HE_SIG_A_MU_UL_E = 88 , + WIFIMACTX_HE_SIG_B1_MU_E = 89 , + WIFIMACTX_HE_SIG_B2_MU_E = 90 , + WIFIMACTX_HE_SIG_B2_OFDMA_E = 91 , + WIFIMACTX_DELETE_CV_E = 92 , + WIFIMACTX_MU_UPLINK_COMMON_E = 93 , + WIFIMACTX_MU_UPLINK_USER_SETUP_E = 94 , + WIFIMACTX_OTHER_TRANSMIT_INFO_E = 95 , + WIFIMACTX_PHY_NAP_E = 96 , + WIFIMACTX_DEBUG_E = 97 , + WIFIPHYRX_ABORT_ACK_E = 98 , + WIFIPHYRX_GENERATED_CBF_DETAILS_E = 99 , + WIFIPHYRX_RSSI_LEGACY_E = 100 , + WIFIPHYRX_RSSI_HT_E = 101 , + WIFIPHYRX_USER_INFO_E = 102 , + WIFIPHYRX_PKT_END_E = 103 , + WIFIPHYRX_DEBUG_E = 104 , + WIFIPHYRX_CBF_TRANSFER_DONE_E = 105 , + WIFIPHYRX_CBF_TRANSFER_ABORT_E = 106 , + WIFIPHYRX_L_SIG_A_E = 107 , + WIFIPHYRX_L_SIG_B_E = 108 , + WIFIPHYRX_HT_SIG_E = 109 , + WIFIPHYRX_VHT_SIG_A_E = 110 , + WIFIPHYRX_VHT_SIG_B_SU20_E = 111 , + WIFIPHYRX_VHT_SIG_B_SU40_E = 112 , + WIFIPHYRX_VHT_SIG_B_SU80_E = 113 , + WIFIPHYRX_VHT_SIG_B_SU160_E = 114 , + WIFIPHYRX_VHT_SIG_B_MU20_E = 115 , + WIFIPHYRX_VHT_SIG_B_MU40_E = 116 , + WIFIPHYRX_VHT_SIG_B_MU80_E = 117 , + WIFIPHYRX_VHT_SIG_B_MU160_E = 118 , + WIFIPHYRX_HE_SIG_A_SU_E = 119 , + WIFIPHYRX_HE_SIG_A_MU_DL_E = 120 , + WIFIPHYRX_HE_SIG_A_MU_UL_E = 121 , + WIFIPHYRX_HE_SIG_B1_MU_E = 122 , + WIFIPHYRX_HE_SIG_B2_MU_E = 123 , + WIFIPHYRX_HE_SIG_B2_OFDMA_E = 124 , + WIFIPHYRX_OTHER_RECEIVE_INFO_E = 125 , + WIFIPHYRX_COMMON_USER_INFO_E = 126 , + WIFIPHYRX_DATA_DONE_E = 127 , + WIFICOEX_TX_REQ_E = 128 , + WIFIDUMMY_E = 129 , + WIFIEXAMPLE_TLV_32_NAME_E = 130 , + WIFIMPDU_LIMIT_E = 131 , + WIFINA_LENGTH_END_E = 132 , + WIFIOLE_BUF_STATUS_E = 133 , + WIFIPCU_PPDU_SETUP_DONE_E = 134 , + WIFIPCU_PPDU_SETUP_END_E = 135 , + WIFIPCU_PPDU_SETUP_INIT_E = 136 , + WIFIPCU_PPDU_SETUP_START_E = 137 , + WIFIPDG_FES_SETUP_E = 138 , + WIFIPDG_RESPONSE_E = 139 , + WIFIPDG_TX_REQ_E = 140 , + WIFISCH_WAIT_INSTR_E = 141 , + WIFIMACTX_SWITCH_TO_MAIN_E = 142 , + WIFIPHYTX_LINK_STATE_E = 143 , + WIFIAUX_PPDU_END_E = 144 , + WIFITQM_GEN_MPDU_LENGTH_LIST_E = 145 , + WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 146 , + WIFITQM_GEN_MPDUS_E = 147 , + WIFITQM_GEN_MPDUS_STATUS_E = 148 , + WIFITQM_REMOVE_MPDU_E = 149 , + WIFITQM_REMOVE_MPDU_STATUS_E = 150 , + WIFITQM_REMOVE_MSDU_E = 151 , + WIFITQM_REMOVE_MSDU_STATUS_E = 152 , + WIFITQM_UPDATE_TX_MPDU_COUNT_E = 153 , + WIFITQM_WRITE_CMD_E = 154 , + WIFIOFDMA_TRIGGER_DETAILS_E = 155 , + WIFITX_DATA_E = 156 , + WIFITX_FES_SETUP_E = 157 , + WIFIRX_PACKET_E = 158 , + WIFIEXPECTED_RESPONSE_E = 159 , + WIFITX_MPDU_END_E = 160 , + WIFITX_MPDU_START_E = 161 , + WIFITX_MSDU_END_E = 162 , + WIFITX_MSDU_START_E = 163 , + WIFITX_SW_MODE_SETUP_E = 164 , + WIFITXPCU_BUFFER_STATUS_E = 165 , + WIFITXPCU_USER_BUFFER_STATUS_E = 166 , + WIFIDATA_TO_TIME_CONFIG_E = 167 , + WIFIEXAMPLE_USER_TLV_32_E = 168 , + WIFIMPDU_INFO_E = 169 , + WIFIPDG_USER_SETUP_E = 170 , + WIFITX_11AH_SETUP_E = 171 , + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 172 , + WIFITX_PEER_ENTRY_E = 173 , + WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 174 , + WIFIEXAMPLE_USER_TLV_44_E = 175 , + WIFITX_FLUSH_E = 176 , + WIFITX_FLUSH_REQ_E = 177 , + WIFITQM_WRITE_CMD_STATUS_E = 178 , + WIFITQM_GET_MPDU_QUEUE_STATS_E = 179 , + WIFITQM_GET_MSDU_FLOW_STATS_E = 180 , + WIFIEXAMPLE_USER_CTLV_44_E = 181 , + WIFITX_FES_STATUS_START_E = 182 , + WIFITX_FES_STATUS_USER_PPDU_E = 183 , + WIFITX_FES_STATUS_USER_RESPONSE_E = 184 , + WIFITX_FES_STATUS_END_E = 185 , + WIFIRX_TRIG_INFO_E = 186 , + WIFIRXPCU_TX_SETUP_CLEAR_E = 187 , + WIFIRX_FRAME_BITMAP_REQ_E = 188 , + WIFIRX_FRAME_BITMAP_ACK_E = 189 , + WIFICOEX_RX_STATUS_E = 190 , + WIFIRX_START_PARAM_E = 191 , + WIFIRX_PPDU_START_E = 192 , + WIFIRX_PPDU_END_E = 193 , + WIFIRX_MPDU_START_E = 194 , + WIFIRX_MPDU_END_E = 195 , + WIFIRX_MSDU_START_E = 196 , + WIFIRX_MSDU_END_E = 197 , + WIFIRX_ATTENTION_E = 198 , + WIFIRECEIVED_RESPONSE_INFO_E = 199 , + WIFIRX_PHY_SLEEP_E = 200 , + WIFIRX_HEADER_E = 201 , + WIFIRX_PEER_ENTRY_E = 202 , + WIFIRX_FLUSH_E = 203 , + WIFIRX_RESPONSE_REQUIRED_INFO_E = 204 , + WIFIRX_FRAMELESS_BAR_DETAILS_E = 205 , + WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 206 , + WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 207 , + WIFITX_CBF_INFO_E = 208 , + WIFIPCU_PPDU_SETUP_USER_E = 209 , + WIFIRX_MPDU_PCU_START_E = 210 , + WIFIRX_PM_INFO_E = 211 , + WIFIRX_USER_PPDU_END_E = 212 , + WIFIRX_PRE_PPDU_START_E = 213 , + WIFIRX_PREAMBLE_E = 214 , + WIFITX_FES_SETUP_COMPLETE_E = 215 , + WIFITX_LAST_MPDU_FETCHED_E = 216 , + WIFITXDMA_STOP_REQUEST_E = 217 , + WIFIRXPCU_SETUP_E = 218 , + WIFIRXPCU_USER_SETUP_E = 219 , + WIFITX_FES_STATUS_ACK_OR_BA_E = 220 , + WIFITQM_ACKED_MPDU_E = 221 , + WIFICOEX_TX_RESP_E = 222 , + WIFICOEX_TX_STATUS_E = 223 , + WIFIMACTX_COEX_PHY_CTRL_E = 224 , + WIFICOEX_STATUS_BROADCAST_E = 225 , + WIFIRESPONSE_START_STATUS_E = 226 , + WIFIRESPONSE_END_STATUS_E = 227 , + WIFICRYPTO_STATUS_E = 228 , + WIFIRECEIVED_TRIGGER_INFO_E = 229 , + WIFICOEX_TX_STOP_CTRL_E = 230 , + WIFIRX_PPDU_ACK_REPORT_E = 231 , + WIFIRX_PPDU_NO_ACK_REPORT_E = 232 , + WIFISCH_COEX_STATUS_E = 233 , + WIFISCHEDULER_COMMAND_STATUS_E = 234 , + WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 235 , + WIFITX_FES_STATUS_PROT_E = 236 , + WIFITX_FES_STATUS_START_PPDU_E = 237 , + WIFITX_FES_STATUS_START_PROT_E = 238 , + WIFITXPCU_PHYTX_DEBUG32_E = 239 , + WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 240 , + WIFITX_MPDU_COUNT_TRANSFER_END_E = 241 , + WIFIWHO_ANCHOR_OFFSET_E = 242 , + WIFIWHO_ANCHOR_VALUE_E = 243 , + WIFIWHO_CCE_INFO_E = 244 , + WIFIWHO_COMMIT_E = 245 , + WIFIWHO_COMMIT_DONE_E = 246 , + WIFIWHO_FLUSH_E = 247 , + WIFIWHO_L2_LLC_E = 248 , + WIFIWHO_L2_PAYLOAD_E = 249 , + WIFIWHO_L3_CHECKSUM_E = 250 , + WIFIWHO_L3_INFO_E = 251 , + WIFIWHO_L4_CHECKSUM_E = 252 , + WIFIWHO_L4_INFO_E = 253 , + WIFIWHO_MSDU_E = 254 , + WIFIWHO_MSDU_MISC_E = 255 , + WIFIWHO_PACKET_DATA_E = 256 , + WIFIWHO_PACKET_HDR_E = 257 , + WIFIWHO_PPDU_END_E = 258 , + WIFIWHO_PPDU_START_E = 259 , + WIFIWHO_TSO_E = 260 , + WIFIWHO_WMAC_HEADER_PV0_E = 261 , + WIFIWHO_WMAC_HEADER_PV1_E = 262 , + WIFIWHO_WMAC_IV_E = 263 , + WIFIMPDU_INFO_END_E = 264 , + WIFIMPDU_INFO_BITMAP_E = 265 , + WIFITX_QUEUE_EXTENSION_E = 266 , + WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 267 , + WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 268 , + WIFITQM_ACKED_MPDU_STATUS_E = 269 , + WIFITQM_ADD_MSDU_STATUS_E = 270 , + WIFITQM_LIST_GEN_DONE_E = 271 , + WIFIWHO_TERMINATE_E = 272 , + WIFITX_LAST_MPDU_END_E = 273 , + WIFITX_CV_DATA_E = 274 , + WIFIPPDU_TX_END_E = 275 , + WIFIPROT_TX_END_E = 276 , + WIFIMPDU_INFO_GLOBAL_END_E = 277 , + WIFITQM_SCH_INSTR_GLOBAL_END_E = 278 , + WIFIRX_PPDU_END_USER_STATS_E = 279 , + WIFIRX_PPDU_END_USER_STATS_EXT_E = 280 , + WIFIREO_GET_QUEUE_STATS_E = 281 , + WIFIREO_FLUSH_QUEUE_E = 282 , + WIFIREO_FLUSH_CACHE_E = 283 , + WIFIREO_UNBLOCK_CACHE_E = 284 , + WIFIREO_GET_QUEUE_STATS_STATUS_E = 285 , + WIFIREO_FLUSH_QUEUE_STATUS_E = 286 , + WIFIREO_FLUSH_CACHE_STATUS_E = 287 , + WIFIREO_UNBLOCK_CACHE_STATUS_E = 288 , + WIFITQM_FLUSH_CACHE_E = 289 , + WIFITQM_UNBLOCK_CACHE_E = 290 , + WIFITQM_FLUSH_CACHE_STATUS_E = 291 , + WIFITQM_UNBLOCK_CACHE_STATUS_E = 292 , + WIFIRX_PPDU_END_STATUS_DONE_E = 293 , + WIFIRX_STATUS_BUFFER_DONE_E = 294 , + WIFISCHEDULER_MLO_SW_MSG_STATUS_E = 295 , + WIFISCHEDULER_TXOP_DURATION_TRIGGER_E = 296 , + WIFITX_DATA_SYNC_E = 297 , + WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 298 , + WIFITQM_GET_MPDU_HEAD_INFO_E = 299 , + WIFITQM_SYNC_CMD_E = 300 , + WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 301 , + WIFITQM_SYNC_CMD_STATUS_E = 302 , + WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 303 , + WIFIREO_FLUSH_TIMEOUT_LIST_E = 305 , + WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 306 , + WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 307 , + WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 308 , + WIFIEXAMPLE_USER_TLV_32_NAME_E = 309 , + WIFIRX_PPDU_START_USER_INFO_E = 310 , + WIFIRX_RING_MASK_E = 311 , + WIFICOEX_MAC_NAP_E = 312 , + WIFIRXPCU_PPDU_END_INFO_E = 313 , + WIFIWHO_MESH_CONTROL_E = 314 , + WIFIPDG_SW_MODE_BW_START_E = 315 , + WIFIPDG_SW_MODE_BW_END_E = 316 , + WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 317 , + WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 318 , + WIFISCHEDULER_END_E = 319 , + WIFIRX_PPDU_START_DROPPED_E = 320 , + WIFIRX_PPDU_END_DROPPED_E = 321 , + WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 322 , + WIFIRX_MPDU_START_DROPPED_E = 323 , + WIFIRX_MSDU_START_DROPPED_E = 324 , + WIFIRX_MSDU_END_DROPPED_E = 325 , + WIFIRX_MPDU_END_DROPPED_E = 326 , + WIFIRX_ATTENTION_DROPPED_E = 327 , + WIFITXPCU_USER_SETUP_E = 328 , + WIFIRXPCU_USER_SETUP_EXT_E = 329 , + WIFICMD_PART_0_END_E = 330 , + WIFIMACTX_SYNTH_ON_E = 331 , + WIFISCH_CRITICAL_TLV_REFERENCE_E = 332 , + WIFITQM_MPDU_GLOBAL_START_E = 333 , + WIFIEXAMPLE_TLV_32_E = 334 , + WIFITQM_UPDATE_TX_MSDU_FLOW_E = 335 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 336 , + WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 337 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 338 , + WIFIREO_UPDATE_RX_REO_QUEUE_E = 339 , + WIFITQM_2_SCH_MPDU_AVAILABLE_E = 341 , + WIFIPDG_TRIG_RESPONSE_E = 342 , + WIFITRIGGER_RESPONSE_TX_DONE_E = 343 , + WIFIABORT_FROM_PHYRX_DETAILS_E = 344 , + WIFISCH_TQM_CMD_WRAPPER_E = 345 , + WIFIMPDUS_AVAILABLE_E = 346 , + WIFIRECEIVED_RESPONSE_INFO_PART2_E = 347 , + WIFIPHYRX_TX_START_TIMING_E = 348 , + WIFITXPCU_PREAMBLE_DONE_E = 349 , + WIFINDP_PREAMBLE_DONE_E = 350 , + WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 351 , + WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 352 , + WIFIMACTX_CLEAR_PREV_TX_INFO_E = 353 , + WIFITX_PUNCTURE_SETUP_E = 354 , + WIFIR2R_STATUS_END_E = 355 , + WIFIMACTX_PREFETCH_CV_COMMON_E = 356 , + WIFIEND_OF_FLUSH_MARKER_E = 357 , + WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 358 , + WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 359 , + WIFIRECEIVED_RESPONSE_USER_7_0_E = 360 , + WIFIRECEIVED_RESPONSE_USER_15_8_E = 361 , + WIFIRECEIVED_RESPONSE_USER_23_16_E = 362 , + WIFIRECEIVED_RESPONSE_USER_31_24_E = 363 , + WIFIRECEIVED_RESPONSE_USER_36_32_E = 364 , + WIFITX_LOOPBACK_SETUP_E = 365 , + WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 366 , + WIFISCH_WAIT_INSTR_TX_PATH_E = 367 , + WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 368 , + WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 369 , + WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 370 , + WIFITX_WUR_DATA_E = 371 , + WIFIRX_PPDU_END_START_E = 372 , + WIFIRX_PPDU_END_MIDDLE_E = 373 , + WIFIRX_PPDU_END_LAST_E = 374 , + WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 375 , + WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 376 , + WIFISRP_INFO_E = 377 , + WIFIOBSS_SR_INFO_E = 378 , + WIFISCHEDULER_SW_MSG_STATUS_E = 379 , + WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 380 , + WIFIRXPCU_SETUP_COMPLETE_E = 381 , + WIFIMACTX_MCC_SWITCH_E = 382 , + WIFIMACTX_MCC_SWITCH_BACK_E = 383 , + WIFIPHYTX_MCC_SWITCH_ACK_E = 384 , + WIFIPHYTX_MCC_SWITCH_BACK_ACK_E = 385 , + WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E = 386 , + WIFILMR_TX_END_E = 389 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 390 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 391 , + WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 392 , + WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 393 , + WIFISCH_TLV_WRAPPER_E = 394 , + WIFISCHEDULER_STATUS_WRAPPER_E = 395 , + WIFIMPDU_INFO_6X_E = 396 , + WIFIMACTX___RESERVED_G_0013 = 397 , + WIFIMACTX_U_SIG_EHT_SU_MU_E = 398 , + WIFIMACTX_U_SIG_EHT_TB_E = 399 , + WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E = 400 , + WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E = 401 , + WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E = 402 , + WIFIPHYRX_U_SIG_EHT_SU_MU_E = 403 , + WIFIPHYRX_U_SIG_EHT_TB_E = 404 , + WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E = 405 , + WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 406 , + WIFITX_PUNCTURE_6PATTERNS_SETUP_E = 407 , + WIFIMACRX_LMR_READ_REQUEST_E = 408 , + WIFIMACRX_LMR_DATA_REQUEST_E = 409 , + WIFIPHYRX_LMR_TRANSFER_DONE_E = 410 , + WIFIPHYRX_LMR_TRANSFER_ABORT_E = 411 , + WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 412 , + WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 413 , + WIFIPHYRX_USER_INFO_MU_UL_E = 414 , + WIFIMPDU_QUEUE_OVERVIEW_E = 415 , + WIFISCHEDULER_NAV_INFO_E = 416 , + WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 417 , + WIFILMR_PEER_ENTRY_E = 418 , + WIFILMR_MPDU_START_E = 419 , + WIFILMR_DATA_E = 420 , + WIFILMR_MPDU_END_E = 421 , + WIFIREO_GET_QUEUE_1K_STATS_STATUS_E = 422 , + WIFIRX_FRAME_1K_BITMAP_ACK_E = 423 , + WIFITX_FES_STATUS_1K_BA_E = 424 , + WIFITQM_ACKED_1K_MPDU_E = 425 , + WIFIMACRX_INBSS_OBSS_IND_E = 426 , + WIFIPHYRX_LOCATION_E = 427 , + WIFIMLO_TX_NOTIFICATION_SU_E = 428 , + WIFIMLO_TX_NOTIFICATION_MU_E = 429 , + WIFIMLO_TX_REQ_SU_E = 430 , + WIFIMLO_TX_REQ_MU_E = 431 , + WIFIMLO_TX_RESP_E = 432 , + WIFIMLO_RX_NOTIFICATION_E = 433 , + WIFIMLO_BKOFF_TRUNC_REQ_E = 434 , + WIFIMLO_TBTT_NOTIFICATION_E = 435 , + WIFIMLO_MESSAGE_E = 436 , + WIFIMLO_TS_SYNC_MSG_E = 437 , + WIFIMLO_FES_SETUP_E = 438 , + WIFIMLO_PDG_FES_SETUP_SU_E = 439 , + WIFIMLO_PDG_FES_SETUP_MU_E = 440 , + WIFIMPDU_INFO_1K_BITMAP_E = 441 , + WIFIMON_BUFFER_ADDR_E = 442 , + WIFITX_FRAG_STATE_E = 443 , + WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 444 , + WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 445 , + WIFIMACTX_EHT_SIG_USR_OFDMA_E = 446 , + WIFIPHYRX_EHT_SIG_CMN_PUNC_E = 448 , + WIFIPHYRX_EHT_SIG_CMN_OFDMA_E = 450 , + WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 454 , + WIFIPHYRX_PKT_END_PART1_E = 456 , + WIFIMACTX_EXPECT_NDP_RECEPTION_E = 457 , + WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 458 , + WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 460 , + WIFIPHYRX___RESERVED_G_0014 = 461 , + WIFIPHYTX_LOCATION_E = 462 , + WIFIPHYTX___RESERVED_G_0014 = 463 , + WIFIMACTX_EHT_SIG_USR_SU_E = 466 , + WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 467 , + WIFIPHYRX_EHT_SIG_USR_SU_E = 468 , + WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 469 , + WIFIPHYRX_GENERIC_U_SIG_E = 470 , + WIFIPHYRX_GENERIC_EHT_SIG_E = 471 , + WIFIOVERWRITE_RESP_START_E = 472 , + WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 473 , + WIFIOVERWRITE_RESP_FRAME_INFO_E = 474 , + WIFIOVERWRITE_RESP_END_E = 475 , + WIFIRXPCU_EARLY_RX_INDICATION_E = 476 , + WIFIMON_DROP_E = 477 , + WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 478 , + WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 479 , + WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 480 , + WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 481 , + WIFIMACTX_PREFETCH_CV_DMA_E = 482 , + WIFIMACTX_PREFETCH_CV_PER_USER_E = 483 , + WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 484 , + WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 485 , + WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 486 , + WIFIRANGING_USER_DETAILS_E = 487 , + WIFIPHYTX_CV_CORR_STATUS_E = 488 , + WIFIPHYTX_CV_CORR_COMMON_E = 489 , + WIFIPHYTX_CV_CORR_USER_E = 490 , + WIFIMACTX_CV_CORR_COMMON_E = 491 , + WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 492 , + WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 493 , + WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 494 , + WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 495 , + WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 496 , + WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 497 , + WIFIRX_PPDU_END_USER_STATS_EXT2_E = 498 , + WIFIFW2SW_MON_E = 499 , + WIFIWSI_DIRECT_MESSAGE_E = 500 , + WIFIMACTX_EMLSR_PRE_SWITCH_E = 501 , + WIFIMACTX_EMLSR_SWITCH_E = 502 , + WIFIMACTX_EMLSR_SWITCH_BACK_E = 503 , + WIFIPHYTX_EMLSR_SWITCH_ACK_E = 504 , + WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 505 , + WIFISPARE_REUSE_TAG_0_E = 506 , + WIFISPARE_REUSE_TAG_1_E = 507 , + WIFISPARE_REUSE_TAG_2_E = 508 , + WIFISPARE_REUSE_TAG_3_E = 509 +} tlv_tag_def__e; + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_cbf_info.h b/drivers/staging/fw-api/hw/peach/v1/tx_cbf_info.h new file mode 100644 index 0000000000000000000000000000000000000000..704e096b629c63902faa5de702d593a8e8f85422 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_cbf_info.h @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_CBF_INFO_H_ +#define _TX_CBF_INFO_H_ + +#define NUM_OF_DWORDS_TX_CBF_INFO 15 + +struct tx_cbf_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sw_peer_id : 16, + pre_cbf_duration : 16; + uint32_t brpoll_info_valid : 1, + trigger_brpoll_info_valid : 1, + npda_info_11ac_valid : 1, + npda_info_11ax_valid : 1, + dot11ax_su_extended : 1, + bandwidth : 3, + brpoll_info : 8, + cbf_response_table_base_index : 8, + peer_index : 3, + pkt_type : 4, + txop_duration_all_ones : 1; + uint32_t trigger_brpoll_common_info_15_0 : 16, + trigger_brpoll_common_info_31_16 : 16; + uint32_t trigger_brpoll_user_info_15_0 : 16, + trigger_brpoll_user_info_31_16 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t addr3_47_32 : 16, + sta_partial_aid : 11, + reserved_8a : 4, + cbf_resp_pwr_mgmt : 1; + uint32_t group_id : 6, + rssi_comb : 8, + reserved_9a : 2, + vht_ndpa_sta_info : 16; + uint32_t he_eht_sta_info_15_0 : 16, + he_eht_sta_info_31_16 : 16; + uint32_t dot11ax_received_format_indication : 1, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_bss_color_id : 6, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_cp_size : 2, + dot11ax_received_ltf_size : 2, + dot11ax_received_coding : 1, + dot11ax_received_dcm : 1, + dot11ax_received_doppler_indication : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_dl_ul_flag : 1, + reserved_11a : 8; + uint32_t sw_response_frame_length : 16, + sw_response_tlv_from_crypto : 1, + wait_sifs_config_valid : 1, + wait_sifs : 2, + __reserved_g_0005 : 1, + secure : 1, + tb___reserved_g_0005_response_required : 2, + emlsr_main_tlv_if : 1, + reserved_12a : 1, + u_sig_puncture_pattern_encoding : 6; + uint32_t dot11be_puncture_bitmap : 16, + dot11be_response : 1, + punctured_response : 1, + npda_info_11be_valid : 1, + eht_duplicate_mode : 2, + reserved_13a : 11; + uint32_t eht_sta_info_39_32 : 8, + reserved_14a : 24; +#else + uint32_t pre_cbf_duration : 16, + sw_peer_id : 16; + uint32_t txop_duration_all_ones : 1, + pkt_type : 4, + peer_index : 3, + cbf_response_table_base_index : 8, + brpoll_info : 8, + bandwidth : 3, + dot11ax_su_extended : 1, + npda_info_11ax_valid : 1, + npda_info_11ac_valid : 1, + trigger_brpoll_info_valid : 1, + brpoll_info_valid : 1; + uint32_t trigger_brpoll_common_info_31_16 : 16, + trigger_brpoll_common_info_15_0 : 16; + uint32_t trigger_brpoll_user_info_31_16 : 16, + trigger_brpoll_user_info_15_0 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t cbf_resp_pwr_mgmt : 1, + reserved_8a : 4, + sta_partial_aid : 11, + addr3_47_32 : 16; + uint32_t vht_ndpa_sta_info : 16, + reserved_9a : 2, + rssi_comb : 8, + group_id : 6; + uint32_t he_eht_sta_info_31_16 : 16, + he_eht_sta_info_15_0 : 16; + uint32_t reserved_11a : 8, + dot11ax_dl_ul_flag : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_received_doppler_indication : 1, + dot11ax_received_dcm : 1, + dot11ax_received_coding : 1, + dot11ax_received_ltf_size : 2, + dot11ax_received_cp_size : 2, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_bss_color_id : 6, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_format_indication : 1; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_12a : 1, + emlsr_main_tlv_if : 1, + tb___reserved_g_0005_response_required : 2, + secure : 1, + __reserved_g_0005 : 1, + wait_sifs : 2, + wait_sifs_config_valid : 1, + sw_response_tlv_from_crypto : 1, + sw_response_frame_length : 16; + uint32_t reserved_13a : 11, + eht_duplicate_mode : 2, + npda_info_11be_valid : 1, + punctured_response : 1, + dot11be_response : 1, + dot11be_puncture_bitmap : 16; + uint32_t reserved_14a : 24, + eht_sta_info_39_32 : 8; +#endif +}; + +#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x00000000 +#define TX_CBF_INFO_SW_PEER_ID_LSB 0 +#define TX_CBF_INFO_SW_PEER_ID_MSB 15 +#define TX_CBF_INFO_SW_PEER_ID_MASK 0x0000ffff + +#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x00000000 +#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 +#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 +#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0xffff0000 + +#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x00000004 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 0 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 0 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x00000001 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x00000004 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 1 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 1 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x00000002 + +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x00000004 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 2 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 2 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x00000004 + +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x00000004 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 3 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 3 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x00000008 + +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 4 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 4 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x00000010 + +#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x00000004 +#define TX_CBF_INFO_BANDWIDTH_LSB 5 +#define TX_CBF_INFO_BANDWIDTH_MSB 7 +#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e0 + +#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x00000004 +#define TX_CBF_INFO_BRPOLL_INFO_LSB 8 +#define TX_CBF_INFO_BRPOLL_INFO_MSB 15 +#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff00 + +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x00000004 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 16 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 23 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff0000 + +#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x00000004 +#define TX_CBF_INFO_PEER_INDEX_LSB 24 +#define TX_CBF_INFO_PEER_INDEX_MSB 26 +#define TX_CBF_INFO_PEER_INDEX_MASK 0x07000000 + +#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x00000004 +#define TX_CBF_INFO_PKT_TYPE_LSB 27 +#define TX_CBF_INFO_PKT_TYPE_MSB 30 +#define TX_CBF_INFO_PKT_TYPE_MASK 0x78000000 + +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x00000004 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 31 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 31 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x80000000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x00000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x0000ffff + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x00000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0xffff0000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000c +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 0 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 15 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000c +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 16 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 31 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff0000 + +#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x00000010 +#define TX_CBF_INFO_ADDR1_31_0_LSB 0 +#define TX_CBF_INFO_ADDR1_31_0_MSB 31 +#define TX_CBF_INFO_ADDR1_31_0_MASK 0xffffffff + +#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x00000014 +#define TX_CBF_INFO_ADDR1_47_32_LSB 0 +#define TX_CBF_INFO_ADDR1_47_32_MSB 15 +#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff + +#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x00000014 +#define TX_CBF_INFO_ADDR2_15_0_LSB 16 +#define TX_CBF_INFO_ADDR2_15_0_MSB 31 +#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff0000 + +#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x00000018 +#define TX_CBF_INFO_ADDR2_47_16_LSB 0 +#define TX_CBF_INFO_ADDR2_47_16_MSB 31 +#define TX_CBF_INFO_ADDR2_47_16_MASK 0xffffffff + +#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000001c +#define TX_CBF_INFO_ADDR3_31_0_LSB 0 +#define TX_CBF_INFO_ADDR3_31_0_MSB 31 +#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff + +#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x00000020 +#define TX_CBF_INFO_ADDR3_47_32_LSB 0 +#define TX_CBF_INFO_ADDR3_47_32_MSB 15 +#define TX_CBF_INFO_ADDR3_47_32_MASK 0x0000ffff + +#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x00000020 +#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 +#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 +#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x07ff0000 + +#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x00000020 +#define TX_CBF_INFO_RESERVED_8A_LSB 27 +#define TX_CBF_INFO_RESERVED_8A_MSB 30 +#define TX_CBF_INFO_RESERVED_8A_MASK 0x78000000 + +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x00000020 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x80000000 + +#define TX_CBF_INFO_GROUP_ID_OFFSET 0x00000024 +#define TX_CBF_INFO_GROUP_ID_LSB 0 +#define TX_CBF_INFO_GROUP_ID_MSB 5 +#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f + +#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x00000024 +#define TX_CBF_INFO_RSSI_COMB_LSB 6 +#define TX_CBF_INFO_RSSI_COMB_MSB 13 +#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc0 + +#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x00000024 +#define TX_CBF_INFO_RESERVED_9A_LSB 14 +#define TX_CBF_INFO_RESERVED_9A_MSB 15 +#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c000 + +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x00000024 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 16 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 31 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff0000 + +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x00000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x0000ffff + +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x00000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0xffff0000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 0 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 0 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x00000001 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 1 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 1 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x00000002 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 2 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 7 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc + +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 8 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 11 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f00 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 12 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 13 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x00003000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 14 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 15 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 16 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 16 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x00010000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 17 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 17 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x00020000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 18 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 18 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x00040000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 19 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 22 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x00780000 + +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 23 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 23 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x00800000 + +#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000002c +#define TX_CBF_INFO_RESERVED_11A_LSB 24 +#define TX_CBF_INFO_RESERVED_11A_MSB 31 +#define TX_CBF_INFO_RESERVED_11A_MASK 0xff000000 + +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x00000030 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff + +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x00000030 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x00010000 + +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x00000030 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x00020000 + +#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x00000030 +#define TX_CBF_INFO_WAIT_SIFS_LSB 18 +#define TX_CBF_INFO_WAIT_SIFS_MSB 19 +#define TX_CBF_INFO_WAIT_SIFS_MASK 0x000c0000 + +#define TX_CBF_INFO_SECURE_OFFSET 0x00000030 +#define TX_CBF_INFO_SECURE_LSB 21 +#define TX_CBF_INFO_SECURE_MSB 21 +#define TX_CBF_INFO_SECURE_MASK 0x00200000 + +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x00000030 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 22 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 23 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x00c00000 + +#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x00000030 +#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB 24 +#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB 24 +#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK 0x01000000 + +#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x00000030 +#define TX_CBF_INFO_RESERVED_12A_LSB 25 +#define TX_CBF_INFO_RESERVED_12A_MSB 25 +#define TX_CBF_INFO_RESERVED_12A_MASK 0x02000000 + +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000030 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000034 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 0 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 15 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff + +#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x00000034 +#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 16 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 16 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x00010000 + +#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x00000034 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 17 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 17 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x00020000 + +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x00000034 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 18 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 18 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x00040000 + +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000034 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 19 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 20 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x00180000 + +#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x00000034 +#define TX_CBF_INFO_RESERVED_13A_LSB 21 +#define TX_CBF_INFO_RESERVED_13A_MSB 31 +#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe00000 + +#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x00000038 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x000000ff + +#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x00000038 +#define TX_CBF_INFO_RESERVED_14A_LSB 8 +#define TX_CBF_INFO_RESERVED_14A_MSB 31 +#define TX_CBF_INFO_RESERVED_14A_MASK 0xffffff00 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_setup.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_setup.h new file mode 100644 index 0000000000000000000000000000000000000000..c141ea42f74895e3b05a053d35b5a5eb7caa004d --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_setup.h @@ -0,0 +1,511 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_SETUP_H_ +#define _TX_FES_SETUP_H_ + +#define NUM_OF_DWORDS_TX_FES_SETUP 10 + +struct tx_fes_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; + uint32_t fes_in_11ax_trigger_response_config : 1, + bo_based_tid_aggregation_limit : 4, + __reserved_g_0005 : 1, + expect_i2r_lmr : 1, + transmit_start_reason : 3, + use_alt_power_sr : 1, + static_2_pwr_mode_status : 1, + obss_srg_opport_transmit_status : 1, + srp_based_transmit_status : 1, + obss_pd_based_transmit_status : 1, + puncture_from_all_allowed_modes : 1, + schedule_cmd_ring_id : 5, + fes_control_mode : 2, + number_of_users : 6, + mu_type : 1, + ofdma_triggered_response : 1, + response_to_response_cmd : 1; + uint32_t schedule_try : 4, + ndp_frame : 2, + txbf : 1, + allow_txop_exceed_in_1st_pkt : 1, + ignore_bw_available : 1, + ignore_tbtt : 1, + static_bandwidth : 3, + set_txop_duration_all_ones : 1, + transmission_contains_mu_rts : 1, + bw_restricted_frames_embedded : 1, + ast_index : 16; + uint32_t cv_id : 8, + trigger_resp_txpdu_ppdu_boundary : 2, + rxpcu_setup_complete_present : 1, + rbo_must_have_data_user_limit : 4, + mu_ndp : 1, + bf_type : 2, + cbf_nc_index_mask : 1, + cbf_nc_index : 3, + cbf_nr_index_mask : 1, + cbf_nr_index : 3, + secure___reserved_g_0005_ista : 1, + ndpa : 1, + wait_sifs : 2, + cbf_feedback_type_mask : 1, + cbf_feedback_type : 1; + uint32_t cbf_sounding_token : 6, + cbf_sounding_token_mask : 1, + cbf_bw_mask : 1, + cbf_bw : 3, + use_static_bw : 1, + coex_nack_count : 5, + sch_tx_burst_ongoing : 1, + gen_tqm_update_mpdu_count_tlv : 1, + rts_tx_over___reserved_g_0016 : 1, + reserved_4a : 3, + optimal_bw_retry_count : 4, + fes_continuation_ratio_threshold : 5; + uint32_t transmit_cca_bitmap : 32; + uint32_t tb___reserved_g_0005 : 1, + __reserved_g_0005_trigger_subtype : 4, + min_cts2self_count : 4, + max_cts2self_count : 4, + wifi_radar_enable : 1, + reserved_6a : 1, + wait_for_chksum_done : 1, + reserved_6b : 15, + enable_hw_qos_null : 1; + uint32_t monitor_override_sta_31_0 : 32; + uint32_t monitor_override_sta_36_32 : 5, + enable_qos_null_switch_for_eosp : 1, + reserved_8a : 26; + uint32_t fw2sw_info : 32; +#else + uint32_t schedule_id : 32; + uint32_t response_to_response_cmd : 1, + ofdma_triggered_response : 1, + mu_type : 1, + number_of_users : 6, + fes_control_mode : 2, + schedule_cmd_ring_id : 5, + puncture_from_all_allowed_modes : 1, + obss_pd_based_transmit_status : 1, + srp_based_transmit_status : 1, + obss_srg_opport_transmit_status : 1, + static_2_pwr_mode_status : 1, + use_alt_power_sr : 1, + transmit_start_reason : 3, + expect_i2r_lmr : 1, + __reserved_g_0005 : 1, + bo_based_tid_aggregation_limit : 4, + fes_in_11ax_trigger_response_config : 1; + uint32_t ast_index : 16, + bw_restricted_frames_embedded : 1, + transmission_contains_mu_rts : 1, + set_txop_duration_all_ones : 1, + static_bandwidth : 3, + ignore_tbtt : 1, + ignore_bw_available : 1, + allow_txop_exceed_in_1st_pkt : 1, + txbf : 1, + ndp_frame : 2, + schedule_try : 4; + uint32_t cbf_feedback_type : 1, + cbf_feedback_type_mask : 1, + wait_sifs : 2, + ndpa : 1, + secure___reserved_g_0005_ista : 1, + cbf_nr_index : 3, + cbf_nr_index_mask : 1, + cbf_nc_index : 3, + cbf_nc_index_mask : 1, + bf_type : 2, + mu_ndp : 1, + rbo_must_have_data_user_limit : 4, + rxpcu_setup_complete_present : 1, + trigger_resp_txpdu_ppdu_boundary : 2, + cv_id : 8; + uint32_t fes_continuation_ratio_threshold : 5, + optimal_bw_retry_count : 4, + reserved_4a : 3, + rts_tx_over___reserved_g_0016 : 1, + gen_tqm_update_mpdu_count_tlv : 1, + sch_tx_burst_ongoing : 1, + coex_nack_count : 5, + use_static_bw : 1, + cbf_bw : 3, + cbf_bw_mask : 1, + cbf_sounding_token_mask : 1, + cbf_sounding_token : 6; + uint32_t transmit_cca_bitmap : 32; + uint32_t enable_hw_qos_null : 1, + reserved_6b : 15, + wait_for_chksum_done : 1, + reserved_6a : 1, + wifi_radar_enable : 1, + max_cts2self_count : 4, + min_cts2self_count : 4, + __reserved_g_0005_trigger_subtype : 4, + tb___reserved_g_0005 : 1; + uint32_t monitor_override_sta_31_0 : 32; + uint32_t reserved_8a : 26, + enable_qos_null_switch_for_eosp : 1, + monitor_override_sta_36_32 : 5; + uint32_t fw2sw_info : 32; +#endif +}; + +#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x00000000 +#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 +#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 +#define TX_FES_SETUP_SCHEDULE_ID_MASK 0xffffffff + +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x00000004 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 0 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 0 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x00000001 + +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x00000004 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 1 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 4 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e + +#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x00000004 +#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 6 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 6 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x00000040 + +#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x00000004 +#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 7 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 9 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x00000380 + +#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x00000004 +#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 10 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 10 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x00000400 + +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x00000004 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 11 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 11 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x00000800 + +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x00000004 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 12 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 12 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x00001000 + +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x00000004 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 13 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 13 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x00002000 + +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x00000004 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 14 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 14 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x00004000 + +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x00000004 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 15 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 15 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x00008000 + +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x00000004 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 16 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 20 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f0000 + +#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x00000004 +#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 21 +#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 22 +#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x00600000 + +#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x00000004 +#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 23 +#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 28 +#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f800000 + +#define TX_FES_SETUP_MU_TYPE_OFFSET 0x00000004 +#define TX_FES_SETUP_MU_TYPE_LSB 29 +#define TX_FES_SETUP_MU_TYPE_MSB 29 +#define TX_FES_SETUP_MU_TYPE_MASK 0x20000000 + +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x00000004 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 30 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 30 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x40000000 + +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x00000004 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 31 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 31 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x80000000 + +#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x00000008 +#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 +#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 +#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x0000000f + +#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x00000008 +#define TX_FES_SETUP_NDP_FRAME_LSB 4 +#define TX_FES_SETUP_NDP_FRAME_MSB 5 +#define TX_FES_SETUP_NDP_FRAME_MASK 0x00000030 + +#define TX_FES_SETUP_TXBF_OFFSET 0x00000008 +#define TX_FES_SETUP_TXBF_LSB 6 +#define TX_FES_SETUP_TXBF_MSB 6 +#define TX_FES_SETUP_TXBF_MASK 0x00000040 + +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x00000008 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x00000080 + +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x00000008 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x00000100 + +#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x00000008 +#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x00000200 + +#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x00000008 +#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x00001c00 + +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x00000008 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x00002000 + +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x00000008 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x00004000 + +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x00000008 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x00008000 + +#define TX_FES_SETUP_AST_INDEX_OFFSET 0x00000008 +#define TX_FES_SETUP_AST_INDEX_LSB 16 +#define TX_FES_SETUP_AST_INDEX_MSB 31 +#define TX_FES_SETUP_AST_INDEX_MASK 0xffff0000 + +#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000c +#define TX_FES_SETUP_CV_ID_LSB 0 +#define TX_FES_SETUP_CV_ID_MSB 7 +#define TX_FES_SETUP_CV_ID_MASK 0x000000ff + +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000c +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 8 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 9 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x00000300 + +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000c +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 10 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 10 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x00000400 + +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000c +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 11 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 14 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x00007800 + +#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000c +#define TX_FES_SETUP_MU_NDP_LSB 15 +#define TX_FES_SETUP_MU_NDP_MSB 15 +#define TX_FES_SETUP_MU_NDP_MASK 0x00008000 + +#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000c +#define TX_FES_SETUP_BF_TYPE_LSB 16 +#define TX_FES_SETUP_BF_TYPE_MSB 17 +#define TX_FES_SETUP_BF_TYPE_MASK 0x00030000 + +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 18 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 18 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x00040000 + +#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_NC_INDEX_LSB 19 +#define TX_FES_SETUP_CBF_NC_INDEX_MSB 21 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x00380000 + +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 22 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 22 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x00400000 + +#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_NR_INDEX_LSB 23 +#define TX_FES_SETUP_CBF_NR_INDEX_MSB 25 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x03800000 + +#define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000c +#define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 26 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 26 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x04000000 + +#define TX_FES_SETUP_NDPA_OFFSET 0x0000000c +#define TX_FES_SETUP_NDPA_LSB 27 +#define TX_FES_SETUP_NDPA_MSB 27 +#define TX_FES_SETUP_NDPA_MASK 0x08000000 + +#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000c +#define TX_FES_SETUP_WAIT_SIFS_LSB 28 +#define TX_FES_SETUP_WAIT_SIFS_MSB 29 +#define TX_FES_SETUP_WAIT_SIFS_MASK 0x30000000 + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 30 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 30 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x40000000 + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 31 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 31 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x80000000 + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x00000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x0000003f + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x00000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x00000040 + +#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x00000010 +#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x00000080 + +#define TX_FES_SETUP_CBF_BW_OFFSET 0x00000010 +#define TX_FES_SETUP_CBF_BW_LSB 8 +#define TX_FES_SETUP_CBF_BW_MSB 10 +#define TX_FES_SETUP_CBF_BW_MASK 0x00000700 + +#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x00000010 +#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x00000800 + +#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x00000010 +#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 +#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 +#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x0001f000 + +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x00000010 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x00020000 + +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x00000010 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x00040000 + +#define TX_FES_SETUP_RESERVED_4A_OFFSET 0x00000010 +#define TX_FES_SETUP_RESERVED_4A_LSB 20 +#define TX_FES_SETUP_RESERVED_4A_MSB 22 +#define TX_FES_SETUP_RESERVED_4A_MASK 0x00700000 + +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x00000010 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x07800000 + +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x00000010 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0xf8000000 + +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x00000014 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 0 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 31 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff + +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000018 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x0000001e + +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x00000018 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x000001e0 + +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x00000018 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x00001e00 + +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x00000018 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x00002000 + +#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x00000018 +#define TX_FES_SETUP_RESERVED_6A_LSB 14 +#define TX_FES_SETUP_RESERVED_6A_MSB 14 +#define TX_FES_SETUP_RESERVED_6A_MASK 0x00004000 + +#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET 0x00000018 +#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB 15 +#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB 15 +#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK 0x00008000 + +#define TX_FES_SETUP_RESERVED_6B_OFFSET 0x00000018 +#define TX_FES_SETUP_RESERVED_6B_LSB 16 +#define TX_FES_SETUP_RESERVED_6B_MSB 30 +#define TX_FES_SETUP_RESERVED_6B_MASK 0x7fff0000 + +#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET 0x00000018 +#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB 31 +#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB 31 +#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK 0x80000000 + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000001c +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 0 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 31 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x00000020 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x0000001f + +#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET 0x00000020 +#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB 5 +#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB 5 +#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK 0x00000020 + +#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x00000020 +#define TX_FES_SETUP_RESERVED_8A_LSB 6 +#define TX_FES_SETUP_RESERVED_8A_MSB 31 +#define TX_FES_SETUP_RESERVED_8A_MASK 0xffffffc0 + +#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x00000024 +#define TX_FES_SETUP_FW2SW_INFO_LSB 0 +#define TX_FES_SETUP_FW2SW_INFO_MSB 31 +#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_1k_ba.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_1k_ba.h new file mode 100644 index 0000000000000000000000000000000000000000..7b391758e361204fb3f49aecb1ad7af6a9f72b44 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_1k_ba.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_1K_BA_H_ +#define _TX_FES_STATUS_1K_BA_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 + +struct tx_fes_status_1k_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, + ba_type : 1, + ba_tid : 4, + unexpected_ack_or_ba : 1, + response_timeout : 1, + ack_frame_rssi : 8, + ssn : 12, + reserved_0b : 4; + uint32_t sw_peer_id : 16, + reserved_1a : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; + uint32_t ba_bitmap_287_256 : 32; + uint32_t ba_bitmap_319_288 : 32; + uint32_t ba_bitmap_351_320 : 32; + uint32_t ba_bitmap_383_352 : 32; + uint32_t ba_bitmap_415_384 : 32; + uint32_t ba_bitmap_447_416 : 32; + uint32_t ba_bitmap_479_448 : 32; + uint32_t ba_bitmap_511_480 : 32; + uint32_t ba_bitmap_543_512 : 32; + uint32_t ba_bitmap_575_544 : 32; + uint32_t ba_bitmap_607_576 : 32; + uint32_t ba_bitmap_639_608 : 32; + uint32_t ba_bitmap_671_640 : 32; + uint32_t ba_bitmap_703_672 : 32; + uint32_t ba_bitmap_735_704 : 32; + uint32_t ba_bitmap_767_736 : 32; + uint32_t ba_bitmap_799_768 : 32; + uint32_t ba_bitmap_831_800 : 32; + uint32_t ba_bitmap_863_832 : 32; + uint32_t ba_bitmap_895_864 : 32; + uint32_t ba_bitmap_927_896 : 32; + uint32_t ba_bitmap_959_928 : 32; + uint32_t ba_bitmap_991_960 : 32; + uint32_t ba_bitmap_1023_992 : 32; +#else + uint32_t reserved_0b : 4, + ssn : 12, + ack_frame_rssi : 8, + response_timeout : 1, + unexpected_ack_or_ba : 1, + ba_tid : 4, + ba_type : 1, + ack_ba_status_type : 1; + uint32_t reserved_1a : 16, + sw_peer_id : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; + uint32_t ba_bitmap_287_256 : 32; + uint32_t ba_bitmap_319_288 : 32; + uint32_t ba_bitmap_351_320 : 32; + uint32_t ba_bitmap_383_352 : 32; + uint32_t ba_bitmap_415_384 : 32; + uint32_t ba_bitmap_447_416 : 32; + uint32_t ba_bitmap_479_448 : 32; + uint32_t ba_bitmap_511_480 : 32; + uint32_t ba_bitmap_543_512 : 32; + uint32_t ba_bitmap_575_544 : 32; + uint32_t ba_bitmap_607_576 : 32; + uint32_t ba_bitmap_639_608 : 32; + uint32_t ba_bitmap_671_640 : 32; + uint32_t ba_bitmap_703_672 : 32; + uint32_t ba_bitmap_735_704 : 32; + uint32_t ba_bitmap_767_736 : 32; + uint32_t ba_bitmap_799_768 : 32; + uint32_t ba_bitmap_831_800 : 32; + uint32_t ba_bitmap_863_832 : 32; + uint32_t ba_bitmap_895_864 : 32; + uint32_t ba_bitmap_927_896 : 32; + uint32_t ba_bitmap_959_928 : 32; + uint32_t ba_bitmap_991_960 : 32; + uint32_t ba_bitmap_1023_992 : 32; +#endif +}; + +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x00000001 + +#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x00000002 + +#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x0000003c + +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x00000040 + +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x00000080 + +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x0000ff00 + +#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_SSN_LSB 16 +#define TX_FES_STATUS_1K_BA_SSN_MSB 27 +#define TX_FES_STATUS_1K_BA_SSN_MASK 0x0fff0000 + +#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0xf0000000 + +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x00000004 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 0 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 15 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff + +#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 16 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 31 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff0000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x00000008 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x00000010 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x00000014 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x00000018 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000001c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x00000020 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x00000024 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x00000028 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000002c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x00000030 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x00000034 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x00000038 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000003c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x00000040 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x00000044 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x00000048 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000004c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x00000050 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x00000054 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x00000058 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000005c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x00000060 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x00000064 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x00000068 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000006c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x00000070 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x00000074 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x00000078 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000007c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x00000080 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x00000084 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_ack_or_ba.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_ack_or_ba.h new file mode 100644 index 0000000000000000000000000000000000000000..582cc09ba72a1add9055d0775bb52b63a56210ea --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_ack_or_ba.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ +#define _TX_FES_STATUS_ACK_OR_BA_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 + +struct tx_fes_status_ack_or_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, + ba_type : 1, + ba_tid : 4, + unexpected_ack_or_ba : 1, + response_timeout : 1, + ack_frame_rssi : 8, + ssn : 12, + reserved_0b : 4; + uint32_t sw_peer_id : 16, + reserved_1a : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; +#else + uint32_t reserved_0b : 4, + ssn : 12, + ack_frame_rssi : 8, + response_timeout : 1, + unexpected_ack_or_ba : 1, + ba_tid : 4, + ba_type : 1, + ack_ba_status_type : 1; + uint32_t reserved_1a : 16, + sw_peer_id : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; +#endif +}; + +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x00000001 + +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x00000002 + +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x0000003c + +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x00000040 + +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x00000080 + +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x0000ff00 + +#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x0fff0000 + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0xf0000000 + +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x00000004 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 15 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 16 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff0000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x00000008 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000c +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x00000010 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x00000014 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x00000018 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000001c +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x00000020 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x00000024 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_end.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_end.h new file mode 100644 index 0000000000000000000000000000000000000000..eea99f35e3333cae30af3205873b1de9b023bca8 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_end.h @@ -0,0 +1,649 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_END_H_ +#define _TX_FES_STATUS_END_H_ + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_END 11 + +struct tx_fes_status_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_coex_bt_tx_while_wlan_tx : 1, + prot_coex_bt_tx_while_wlan_rx : 1, + prot_coex_wan_tx_while_wlan_tx : 1, + prot_coex_wan_tx_while_wlan_rx : 1, + prot_coex_wlan_tx_while_wlan_tx : 1, + prot_coex_wlan_tx_while_wlan_rx : 1, + coex_bt_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_rx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_rx : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wlan_tx_while_wlan_rx : 1, + global_data_underflow_warning : 1, + global_fes_transmit_result : 4, + cbf_bw_received_valid : 1, + cbf_bw_received : 3, + actual_received_ack_type : 4, + sta_response_count : 6, + more_data_received : 1; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 4, + brp_info_valid : 1, + qos_null_switch_done_for_eosp : 1, + reserved_1a : 5, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + fes_in_11ax_trigger_response_config : 1, + null_delim_inserted_before_mpdus : 1, + only_null_delim_sent : 1; + uint32_t terminate___reserved_g_0005_sequence : 1, + reserved_2b : 5, + response_type : 5, + r2r_end_status_to_follow : 1, + reserved_5a : 3, + prot_coex_lte_tx_while_wlan_tx : 1, + prot_coex_lte_tx_while_wlan_rx : 1, + reserved_2c : 15; + uint32_t beamform_masked_user_bitmap_15_0 : 16, + beamform_masked_user_bitmap_31_16 : 16; + uint32_t cbf_segment_request_mask : 8, + cbf_segment_sent_mask : 8, + highest_achieved_data_null_ratio : 5, + use_alt_power_sr : 1, + static_2_pwr_mode_status : 1, + obss_srg_opport_transmit_status : 1, + srp_based_transmit_status : 1, + obss_pd_based_transmit_status : 1, + beamform_masked_user_bitmap_36_32 : 5, + pdg_mpdu_ready : 1; + uint32_t pdg_mpdu_count : 16, + pdg_est_mpdu_tx_count : 16; + uint32_t pdg_overview_length : 24, + txop_duration : 7, + pdg_dropped_mpdu_warning : 1; + uint32_t packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + packet_extension : 3, + fec_type : 1, + stbc : 1, + num_data_symbols : 16, + ru_size : 4, + reserved_17a : 4; + uint32_t num_ltf_symbols : 3, + ltf_size : 2, + cp_setting : 2, + reserved_18a : 5, + dcm : 1, + ldpc_extra_symbol : 1, + force_extra_symbol : 1, + reserved_18b : 1, + tx_pwr_shared : 8, + tx_pwr_unshared : 8; + uint32_t __reserved_g_0005_active_user_map : 16, + __reserved_g_0005_sent_dummy_tx : 1, + __reserved_g_0005_ftm_frame_sent : 1, + coex_uwb_tx_while_wlan_tx : 1, + coex_uwb_tx_while_wlan_rx : 1, + prot_coex_uwb_tx_while_wlan_tx : 1, + prot_coex_uwb_tx_while_wlan_rx : 1, + coex_lte_tx_while_wlan_tx : 1, + coex_lte_tx_while_wlan_rx : 1, + cv_corr_status : 8; + uint32_t current_tx_duration : 16, + reserved_21a : 4, + hw_qos_null_bitmap : 8, + hw_qos_null_setup_missing : 1, + reserved_21b : 3; +#else + uint32_t more_data_received : 1, + sta_response_count : 6, + actual_received_ack_type : 4, + cbf_bw_received : 3, + cbf_bw_received_valid : 1, + global_fes_transmit_result : 4, + global_data_underflow_warning : 1, + coex_wlan_tx_while_wlan_rx : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_rx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_rx : 1, + coex_bt_tx_while_wlan_tx : 1, + prot_coex_wlan_tx_while_wlan_rx : 1, + prot_coex_wlan_tx_while_wlan_tx : 1, + prot_coex_wan_tx_while_wlan_rx : 1, + prot_coex_wan_tx_while_wlan_tx : 1, + prot_coex_bt_tx_while_wlan_rx : 1, + prot_coex_bt_tx_while_wlan_tx : 1; + uint32_t only_null_delim_sent : 1, + null_delim_inserted_before_mpdus : 1, + fes_in_11ax_trigger_response_config : 1, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + reserved_1a : 5, + qos_null_switch_done_for_eosp : 1, + brp_info_valid : 1, + reserved_after_struct16 : 4; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t reserved_2c : 15, + prot_coex_lte_tx_while_wlan_rx : 1, + prot_coex_lte_tx_while_wlan_tx : 1, + reserved_5a : 3, + r2r_end_status_to_follow : 1, + response_type : 5, + reserved_2b : 5, + terminate___reserved_g_0005_sequence : 1; + uint32_t beamform_masked_user_bitmap_31_16 : 16, + beamform_masked_user_bitmap_15_0 : 16; + uint32_t pdg_mpdu_ready : 1, + beamform_masked_user_bitmap_36_32 : 5, + obss_pd_based_transmit_status : 1, + srp_based_transmit_status : 1, + obss_srg_opport_transmit_status : 1, + static_2_pwr_mode_status : 1, + use_alt_power_sr : 1, + highest_achieved_data_null_ratio : 5, + cbf_segment_sent_mask : 8, + cbf_segment_request_mask : 8; + uint32_t pdg_est_mpdu_tx_count : 16, + pdg_mpdu_count : 16; + uint32_t pdg_dropped_mpdu_warning : 1, + txop_duration : 7, + pdg_overview_length : 24; + uint32_t reserved_17a : 4, + ru_size : 4, + num_data_symbols : 16, + stbc : 1, + fec_type : 1, + packet_extension : 3, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2; + uint32_t tx_pwr_unshared : 8, + tx_pwr_shared : 8, + reserved_18b : 1, + force_extra_symbol : 1, + ldpc_extra_symbol : 1, + dcm : 1, + reserved_18a : 5, + cp_setting : 2, + ltf_size : 2, + num_ltf_symbols : 3; + uint32_t cv_corr_status : 8, + coex_lte_tx_while_wlan_rx : 1, + coex_lte_tx_while_wlan_tx : 1, + prot_coex_uwb_tx_while_wlan_rx : 1, + prot_coex_uwb_tx_while_wlan_tx : 1, + coex_uwb_tx_while_wlan_rx : 1, + coex_uwb_tx_while_wlan_tx : 1, + __reserved_g_0005_ftm_frame_sent : 1, + __reserved_g_0005_sent_dummy_tx : 1, + __reserved_g_0005_active_user_map : 16; + uint32_t reserved_21b : 3, + hw_qos_null_setup_missing : 1, + hw_qos_null_bitmap : 8, + reserved_21a : 4, + current_tx_duration : 16; +#endif +}; + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x00000001 + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x00000002 + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x00000004 + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x00000008 + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x00000010 + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x00000020 + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x00000040 + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x00000080 + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x00000100 + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x00000200 + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x00000400 + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x00000800 + +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x00001000 + +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x00000000 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x0001e000 + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x00000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x00020000 + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x00000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x001c0000 + +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x01e00000 + +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x00000000 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x7e000000 + +#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET 0x00000000 +#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB 31 +#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB 31 +#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK 0x80000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000 + +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x00000004 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 16 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 19 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f0000 + +#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x00000004 +#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 20 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 20 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x00100000 + +#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET 0x00000004 +#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB 21 +#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB 21 +#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK 0x00200000 + +#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_END_RESERVED_1A_LSB 22 +#define TX_FES_STATUS_END_RESERVED_1A_MSB 26 +#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07c00000 + +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 27 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 27 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x08000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 28 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 + +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x00000004 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 29 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 29 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x20000000 + +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x00000004 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 30 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 30 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x40000000 + +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x00000004 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 31 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 31 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x80000000 + +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x00000008 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x00000001 + +#define TX_FES_STATUS_END_RESERVED_2B_OFFSET 0x00000008 +#define TX_FES_STATUS_END_RESERVED_2B_LSB 1 +#define TX_FES_STATUS_END_RESERVED_2B_MSB 5 +#define TX_FES_STATUS_END_RESERVED_2B_MASK 0x0000003e + +#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x00000008 +#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 6 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 10 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x000007c0 + +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x00000008 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 11 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 11 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x00000800 + +#define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x00000008 +#define TX_FES_STATUS_END_RESERVED_5A_LSB 12 +#define TX_FES_STATUS_END_RESERVED_5A_MSB 14 +#define TX_FES_STATUS_END_RESERVED_5A_MASK 0x00007000 + +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET 0x00000008 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_LSB 15 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_MSB 15 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_MASK 0x00008000 + +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_OFFSET 0x00000008 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_LSB 16 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_MSB 16 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_MASK 0x00010000 + +#define TX_FES_STATUS_END_RESERVED_2C_OFFSET 0x00000008 +#define TX_FES_STATUS_END_RESERVED_2C_LSB 17 +#define TX_FES_STATUS_END_RESERVED_2C_MSB 31 +#define TX_FES_STATUS_END_RESERVED_2C_MASK 0xfffe0000 + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000c +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000c +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0xffff0000 + +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x00000010 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 0 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 7 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff + +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x00000010 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 8 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 15 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff00 + +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x00000010 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 16 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 20 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f0000 + +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x00000010 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 21 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 21 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x00200000 + +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x00000010 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 22 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 22 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x00400000 + +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x00000010 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 23 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 23 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x00800000 + +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x00000010 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 24 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 24 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x01000000 + +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x00000010 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 25 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 25 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x02000000 + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000010 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 26 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 30 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c000000 + +#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x00000010 +#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 31 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 31 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x80000000 + +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x00000014 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x0000ffff + +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x00000014 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0xffff0000 + +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x00000018 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 0 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 23 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff + +#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x00000018 +#define TX_FES_STATUS_END_TXOP_DURATION_LSB 24 +#define TX_FES_STATUS_END_TXOP_DURATION_MSB 30 +#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f000000 + +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x00000018 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 31 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 31 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x80000000 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000001c +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x00000003 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000001c +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000004 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000001c +#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x00000038 + +#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000001c +#define TX_FES_STATUS_END_FEC_TYPE_LSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x00000040 + +#define TX_FES_STATUS_END_STBC_OFFSET 0x0000001c +#define TX_FES_STATUS_END_STBC_LSB 7 +#define TX_FES_STATUS_END_STBC_MSB 7 +#define TX_FES_STATUS_END_STBC_MASK 0x00000080 + +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000001c +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x00ffff00 + +#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000001c +#define TX_FES_STATUS_END_RU_SIZE_LSB 24 +#define TX_FES_STATUS_END_RU_SIZE_MSB 27 +#define TX_FES_STATUS_END_RU_SIZE_MASK 0x0f000000 + +#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000001c +#define TX_FES_STATUS_END_RESERVED_17A_LSB 28 +#define TX_FES_STATUS_END_RESERVED_17A_MSB 31 +#define TX_FES_STATUS_END_RESERVED_17A_MASK 0xf0000000 + +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x00000020 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 0 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 2 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x00000007 + +#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x00000020 +#define TX_FES_STATUS_END_LTF_SIZE_LSB 3 +#define TX_FES_STATUS_END_LTF_SIZE_MSB 4 +#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x00000018 + +#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x00000020 +#define TX_FES_STATUS_END_CP_SETTING_LSB 5 +#define TX_FES_STATUS_END_CP_SETTING_MSB 6 +#define TX_FES_STATUS_END_CP_SETTING_MASK 0x00000060 + +#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x00000020 +#define TX_FES_STATUS_END_RESERVED_18A_LSB 7 +#define TX_FES_STATUS_END_RESERVED_18A_MSB 11 +#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f80 + +#define TX_FES_STATUS_END_DCM_OFFSET 0x00000020 +#define TX_FES_STATUS_END_DCM_LSB 12 +#define TX_FES_STATUS_END_DCM_MSB 12 +#define TX_FES_STATUS_END_DCM_MASK 0x00001000 + +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x00000020 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 13 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 13 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x00002000 + +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x00000020 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 14 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 14 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x00004000 + +#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x00000020 +#define TX_FES_STATUS_END_RESERVED_18B_LSB 15 +#define TX_FES_STATUS_END_RESERVED_18B_MSB 15 +#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x00008000 + +#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x00000020 +#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 16 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 23 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff0000 + +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x00000020 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 24 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 31 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff000000 + +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x00000024 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x0000ffff + +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x00010000 + +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x00000024 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x00020000 + +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_LSB 18 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_MSB 18 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_MASK 0x00040000 + +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_LSB 19 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_MSB 19 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_MASK 0x00080000 + +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_LSB 20 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_MSB 20 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_MASK 0x00100000 + +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_LSB 21 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_MSB 21 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_MASK 0x00200000 + +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_LSB 22 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_MSB 22 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_MASK 0x00400000 + +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_LSB 23 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_MSB 23 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_MASK 0x00800000 + +#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x00000024 +#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0xff000000 + +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x00000028 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 0 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 15 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff + +#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x00000028 +#define TX_FES_STATUS_END_RESERVED_21A_LSB 16 +#define TX_FES_STATUS_END_RESERVED_21A_MSB 19 +#define TX_FES_STATUS_END_RESERVED_21A_MASK 0x000f0000 + +#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET 0x00000028 +#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB 20 +#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB 27 +#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK 0x0ff00000 + +#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET 0x00000028 +#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB 28 +#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB 28 +#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK 0x10000000 + +#define TX_FES_STATUS_END_RESERVED_21B_OFFSET 0x00000028 +#define TX_FES_STATUS_END_RESERVED_21B_LSB 29 +#define TX_FES_STATUS_END_RESERVED_21B_MSB 31 +#define TX_FES_STATUS_END_RESERVED_21B_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_prot.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_prot.h new file mode 100644 index 0000000000000000000000000000000000000000..b595140a53bf7d5c95001307b4d441e68f9719c1 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_prot.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_PROT_H_ +#define _TX_FES_STATUS_PROT_H_ + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 3 + +struct tx_fes_status_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t success : 1, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + reserved_0 : 20, + pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4; + uint32_t frame_type : 2, + frame_subtype : 4, + rx_pwr_mgmt : 1, + status : 1, + duration_field : 16, + reserved_1a : 2, + agc_cbw : 3, + service_cbw : 3; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_2a : 16; +#else + uint32_t rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4, + reserved_0 : 20, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + success : 1; + uint32_t service_cbw : 3, + agc_cbw : 3, + reserved_1a : 2, + duration_field : 16, + status : 1, + rx_pwr_mgmt : 1, + frame_subtype : 4, + frame_type : 2; + uint32_t reserved_2a : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; +#endif +}; + +#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x00000001 + +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x00000002 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x00000004 + +#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 +#define TX_FES_STATUS_PROT_RESERVED_0_MSB 22 +#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x007ffff8 + +#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23 +#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26 +#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x07800000 + +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x08000000 + +#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_RATE_MCS_LSB 28 +#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 +#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0xf0000000 + +#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 0 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 1 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x00000003 + +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 2 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 5 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c + +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 6 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 6 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x00000040 + +#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_STATUS_LSB 7 +#define TX_FES_STATUS_PROT_STATUS_MSB 7 +#define TX_FES_STATUS_PROT_STATUS_MASK 0x00000080 + +#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 8 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 23 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff00 + +#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 24 +#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 25 +#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x03000000 + +#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_AGC_CBW_LSB 26 +#define TX_FES_STATUS_PROT_AGC_CBW_MSB 28 +#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c000000 + +#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 29 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 31 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe0000000 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000008 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000008 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000008 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000 + +#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET 0x00000008 +#define TX_FES_STATUS_PROT_RESERVED_2A_LSB 16 +#define TX_FES_STATUS_PROT_RESERVED_2A_MSB 31 +#define TX_FES_STATUS_PROT_RESERVED_2A_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start.h new file mode 100644 index 0000000000000000000000000000000000000000..b8704980b17813ab8a247c7ef6aa1569e23e536b --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_START_H_ +#define _TX_FES_STATUS_START_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 + +struct tx_fes_status_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; + uint32_t reserved_1a : 8, + transmit_start_reason : 3, + disabled_user_bitmap_36_32 : 5, + schedule_cmd_ring_id : 5, + fes_control_mode : 2, + schedule_try : 4, + medium_prot_type : 3, + reserved_1b : 2; + uint32_t optimal_bw_try_count : 4, + number_of_users : 7, + coex_nack_count : 5, + cca_ed0 : 16; + uint32_t disabled_user_bitmap_31_0 : 32; +#else + uint32_t schedule_id : 32; + uint32_t reserved_1b : 2, + medium_prot_type : 3, + schedule_try : 4, + fes_control_mode : 2, + schedule_cmd_ring_id : 5, + disabled_user_bitmap_36_32 : 5, + transmit_start_reason : 3, + reserved_1a : 8; + uint32_t cca_ed0 : 16, + coex_nack_count : 5, + number_of_users : 7, + optimal_bw_try_count : 4; + uint32_t disabled_user_bitmap_31_0 : 32; +#endif +}; + +#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x00000000 +#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 +#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 +#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0xffffffff + +#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_START_RESERVED_1A_LSB 0 +#define TX_FES_STATUS_START_RESERVED_1A_MSB 7 +#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff + +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x00000004 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 8 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 10 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x00000700 + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x00000004 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 11 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 15 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f800 + +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x00000004 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 16 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 20 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f0000 + +#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x00000004 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 21 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 22 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x00600000 + +#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x00000004 +#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 23 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 26 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x07800000 + +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x00000004 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 27 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 29 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x38000000 + +#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x00000004 +#define TX_FES_STATUS_START_RESERVED_1B_LSB 30 +#define TX_FES_STATUS_START_RESERVED_1B_MSB 31 +#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc0000000 + +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x00000008 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x0000000f + +#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x00000008 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x000007f0 + +#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x00000008 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x0000f800 + +#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x00000008 +#define TX_FES_STATUS_START_CCA_ED0_LSB 16 +#define TX_FES_STATUS_START_CCA_ED0_MSB 31 +#define TX_FES_STATUS_START_CCA_ED0_MASK 0xffff0000 + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000c +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start_ppdu.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start_ppdu.h new file mode 100644 index 0000000000000000000000000000000000000000..21fbf64bae9c70c8d8398163e55ae092f9330b54 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start_ppdu.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_START_PPDU_H_ +#define _TX_FES_STATUS_START_PPDU_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 4 + +struct tx_fes_status_start_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_timestamp_lower_32 : 32; + uint32_t ppdu_timestamp_upper_32 : 32; + uint32_t subband_mask : 16, + ndp_frame : 2, + reserved_2b : 2, + coex_based_tx_bw : 3, + coex_based_ant_mask : 8, + reserved_2c : 1; + uint32_t coex_based_tx_pwr_shared_ant : 8, + coex_based_tx_pwr_ant : 8, + concurrent_bt_tx : 1, + concurrent_wlan_tx : 1, + concurrent_wan_tx : 1, + concurrent_wan_rx : 1, + coex_pwr_reduction_bt : 1, + coex_pwr_reduction_wlan : 1, + coex_pwr_reduction_wan : 1, + coex_result_alt_based : 1, + request_packet_bw : 3, + response_type : 5; +#else + uint32_t ppdu_timestamp_lower_32 : 32; + uint32_t ppdu_timestamp_upper_32 : 32; + uint32_t reserved_2c : 1, + coex_based_ant_mask : 8, + coex_based_tx_bw : 3, + reserved_2b : 2, + ndp_frame : 2, + subband_mask : 16; + uint32_t response_type : 5, + request_packet_bw : 3, + coex_result_alt_based : 1, + coex_pwr_reduction_wan : 1, + coex_pwr_reduction_wlan : 1, + coex_pwr_reduction_bt : 1, + concurrent_wan_rx : 1, + concurrent_wan_tx : 1, + concurrent_wlan_tx : 1, + concurrent_bt_tx : 1, + coex_based_tx_pwr_ant : 8, + coex_based_tx_pwr_shared_ant : 8; +#endif +}; + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x00000000 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0xffffffff + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x00000004 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 0 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 31 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff + +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x0000ffff + +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 17 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x00030000 + +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 18 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x000c0000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x00700000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x7f800000 + +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x80000000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 0 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 7 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 8 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 15 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff00 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 16 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 16 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x00010000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 17 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 17 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x00020000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 18 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 18 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x00040000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 19 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 19 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x00080000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x00100000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 21 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 21 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x00200000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x00400000 + +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x00800000 + +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 24 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 26 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x07000000 + +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 27 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 31 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf8000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start_prot.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start_prot.h new file mode 100644 index 0000000000000000000000000000000000000000..4e3bbe0004a5eedef1df5a9dc05d8ddbbfb43a72 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start_prot.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_START_PROT_H_ +#define _TX_FES_STATUS_START_PROT_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 4 + +struct tx_fes_status_start_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_timestamp_lower_32 : 32; + uint32_t prot_timestamp_upper_32 : 32; + uint32_t subband_mask : 16, + reserved_2b : 4, + prot_coex_based_tx_bw : 3, + prot_coex_based_ant_mask : 8, + prot_coex_result_alt_based : 1; + uint32_t prot_coex_tx_pwr_shared_ant : 8, + prot_coex_tx_pwr_ant : 8, + prot_concurrent_bt_tx : 1, + prot_concurrent_wlan_tx : 1, + prot_concurrent_wan_tx : 1, + prot_concurrent_wan_rx : 1, + prot_coex_pwr_reduction_bt : 1, + prot_coex_pwr_reduction_wlan : 1, + prot_coex_pwr_reduction_wan : 1, + prot_request_packet_bw : 3, + response_type : 5, + reserved_3a : 1; +#else + uint32_t prot_timestamp_lower_32 : 32; + uint32_t prot_timestamp_upper_32 : 32; + uint32_t prot_coex_result_alt_based : 1, + prot_coex_based_ant_mask : 8, + prot_coex_based_tx_bw : 3, + reserved_2b : 4, + subband_mask : 16; + uint32_t reserved_3a : 1, + response_type : 5, + prot_request_packet_bw : 3, + prot_coex_pwr_reduction_wan : 1, + prot_coex_pwr_reduction_wlan : 1, + prot_coex_pwr_reduction_bt : 1, + prot_concurrent_wan_rx : 1, + prot_concurrent_wan_tx : 1, + prot_concurrent_wlan_tx : 1, + prot_concurrent_bt_tx : 1, + prot_coex_tx_pwr_ant : 8, + prot_coex_tx_pwr_shared_ant : 8; +#endif +}; + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x00000000 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0xffffffff + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x00000004 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff + +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x0000ffff + +#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x000f0000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x00700000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x7f800000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x80000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 7 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 8 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 15 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff00 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 16 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 16 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x00010000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 17 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 17 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x00020000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 18 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 18 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x00040000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 19 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 19 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x00080000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x00100000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 21 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 21 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x00200000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x00400000 + +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 23 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 25 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x03800000 + +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 26 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 30 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c000000 + +#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 31 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 31 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_user_ppdu.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_user_ppdu.h new file mode 100644 index 0000000000000000000000000000000000000000..a18815551738b0510edaad983001caeb6faa47be --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_user_ppdu.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_USER_PPDU_H_ +#define _TX_FES_STATUS_USER_PPDU_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 + +struct tx_fes_status_user_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t underflow_mpdu_count : 9, + data_underflow_warning : 2, + bw_drop_underflow_warning : 1, + qc_eosp_setting : 1, + fc_more_data_setting : 1, + fc_pwr_mgt_setting : 1, + mpdu_tx_count : 9, + user_blocked : 1, + pre_trig_response_delim_count : 7; + uint32_t underflow_byte_count : 16, + coex_abort_mpdu_count_valid : 1, + coex_abort_mpdu_count : 9, + transmitted_tid : 4, + txdma_dropped_mpdu_warning : 1, + reserved_1 : 1; + uint32_t duration : 16, + num_eof_delim_added : 16; + uint32_t psdu_octet : 24, + qos_buf_state : 8; + uint32_t num_null_delim_added : 22, + reserved_4a : 2, + cv_corr_user_valid_in_phy : 1, + nss : 3, + mcs : 4; + uint32_t ht_control : 32; +#else + uint32_t pre_trig_response_delim_count : 7, + user_blocked : 1, + mpdu_tx_count : 9, + fc_pwr_mgt_setting : 1, + fc_more_data_setting : 1, + qc_eosp_setting : 1, + bw_drop_underflow_warning : 1, + data_underflow_warning : 2, + underflow_mpdu_count : 9; + uint32_t reserved_1 : 1, + txdma_dropped_mpdu_warning : 1, + transmitted_tid : 4, + coex_abort_mpdu_count : 9, + coex_abort_mpdu_count_valid : 1, + underflow_byte_count : 16; + uint32_t num_eof_delim_added : 16, + duration : 16; + uint32_t qos_buf_state : 8, + psdu_octet : 24; + uint32_t mcs : 4, + nss : 3, + cv_corr_user_valid_in_phy : 1, + reserved_4a : 2, + num_null_delim_added : 22; + uint32_t ht_control : 32; +#endif +}; + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x000001ff + +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x00000600 + +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x00000800 + +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x00001000 + +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x00002000 + +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x00004000 + +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x00ff8000 + +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x01000000 + +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0xfe000000 + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 0 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 15 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 16 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 16 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x00010000 + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 17 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 25 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe0000 + +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 26 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 29 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c000000 + +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 30 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 30 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x40000000 + +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 31 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 31 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x80000000 + +#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x00000008 +#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 +#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 +#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x0000ffff + +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x00000008 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0xffff0000 + +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000c +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 0 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 23 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff + +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000c +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 24 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 31 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff000000 + +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x003fffff + +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x00c00000 + +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x01000000 + +#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_NSS_LSB 25 +#define TX_FES_STATUS_USER_PPDU_NSS_MSB 27 +#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x0e000000 + +#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_MCS_LSB 28 +#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 +#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0xf0000000 + +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x00000014 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 0 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 31 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_user_response.h new file mode 100644 index 0000000000000000000000000000000000000000..f1255bdb12b3501abd310fd9b0bbd3a15da637c4 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_user_response.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ +#define _TX_FES_STATUS_USER_RESPONSE_H_ + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 + +struct tx_fes_status_user_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fes_transmit_result : 4, + reserved_0 : 28; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 16; +#else + uint32_t reserved_0 : 28, + fes_transmit_result : 4; + uint32_t reserved_after_struct16 : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; +#endif +}; + +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x0000000f + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 31 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0xfffffff0 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000 + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 16 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 31 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_flush_req.h b/drivers/staging/fw-api/hw/peach/v1/tx_flush_req.h new file mode 100644 index 0000000000000000000000000000000000000000..1ee52b57ad220b97d68cdb7dd4ab9b773582da90 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_flush_req.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FLUSH_REQ_H_ +#define _TX_FLUSH_REQ_H_ + +#define NUM_OF_DWORDS_TX_FLUSH_REQ 1 + +struct tx_flush_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t flush_req_reason : 8, + phytx_abort_reason : 8, + flush_req_user_number_or_link_id : 6, + mlo_abort_reason : 5, + reserved_0a : 5; +#else + uint32_t reserved_0a : 5, + mlo_abort_reason : 5, + flush_req_user_number_or_link_id : 6, + phytx_abort_reason : 8, + flush_req_reason : 8; +#endif +}; + +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x00000000 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x000000ff + +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x00000000 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x0000ff00 + +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x00000000 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x003f0000 + +#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x00000000 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x07c00000 + +#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x00000000 +#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 +#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 +#define TX_FLUSH_REQ_RESERVED_0A_MASK 0xf8000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_mpdu_start.h b/drivers/staging/fw-api/hw/peach/v1/tx_mpdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..aa7bebca07adfdfcc144f1d8a6c2f72aa34bd5b9 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_mpdu_start.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_MPDU_START_H_ +#define _TX_MPDU_START_H_ + +#define NUM_OF_DWORDS_TX_MPDU_START 9 + +struct tx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_length : 14, + frame_not_from_tqm : 1, + vht_control_present : 1, + mpdu_header_length : 8, + retry_count : 7, + wds : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_47_32 : 16, + mpdu_sequence_number : 12, + raw_already_encrypted : 1, + frame_type : 2, + txdma_dropped_mpdu_warning : 1; + uint32_t iv_byte_0 : 8, + iv_byte_1 : 8, + iv_byte_2 : 8, + iv_byte_3 : 8; + uint32_t iv_byte_4 : 8, + iv_byte_5 : 8, + iv_byte_6 : 8, + iv_byte_7 : 8; + uint32_t iv_byte_8 : 8, + iv_byte_9 : 8, + iv_byte_10 : 8, + iv_byte_11 : 8; + uint32_t iv_byte_12 : 8, + iv_byte_13 : 8, + iv_byte_14 : 8, + iv_byte_15 : 8; + uint32_t iv_byte_16 : 8, + iv_byte_17 : 8, + iv_len : 5, + icv_len : 5, + vht_control_offset : 6; + uint32_t mpdu_type : 1, + transmit_bw_restriction : 1, + allowed_transmit_bw : 4, + tx_notify_frame : 3, + reserved_8a : 23; +#else + uint32_t wds : 1, + retry_count : 7, + mpdu_header_length : 8, + vht_control_present : 1, + frame_not_from_tqm : 1, + mpdu_length : 14; + uint32_t pn_31_0 : 32; + uint32_t txdma_dropped_mpdu_warning : 1, + frame_type : 2, + raw_already_encrypted : 1, + mpdu_sequence_number : 12, + pn_47_32 : 16; + uint32_t iv_byte_3 : 8, + iv_byte_2 : 8, + iv_byte_1 : 8, + iv_byte_0 : 8; + uint32_t iv_byte_7 : 8, + iv_byte_6 : 8, + iv_byte_5 : 8, + iv_byte_4 : 8; + uint32_t iv_byte_11 : 8, + iv_byte_10 : 8, + iv_byte_9 : 8, + iv_byte_8 : 8; + uint32_t iv_byte_15 : 8, + iv_byte_14 : 8, + iv_byte_13 : 8, + iv_byte_12 : 8; + uint32_t vht_control_offset : 6, + icv_len : 5, + iv_len : 5, + iv_byte_17 : 8, + iv_byte_16 : 8; + uint32_t reserved_8a : 23, + tx_notify_frame : 3, + allowed_transmit_bw : 4, + transmit_bw_restriction : 1, + mpdu_type : 1; +#endif +}; + +#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x00000000 +#define TX_MPDU_START_MPDU_LENGTH_LSB 0 +#define TX_MPDU_START_MPDU_LENGTH_MSB 13 +#define TX_MPDU_START_MPDU_LENGTH_MASK 0x00003fff + +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x00000000 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x00004000 + +#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x00000000 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x00008000 + +#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x00000000 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x00ff0000 + +#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x00000000 +#define TX_MPDU_START_RETRY_COUNT_LSB 24 +#define TX_MPDU_START_RETRY_COUNT_MSB 30 +#define TX_MPDU_START_RETRY_COUNT_MASK 0x7f000000 + +#define TX_MPDU_START_WDS_OFFSET 0x00000000 +#define TX_MPDU_START_WDS_LSB 31 +#define TX_MPDU_START_WDS_MSB 31 +#define TX_MPDU_START_WDS_MASK 0x80000000 + +#define TX_MPDU_START_PN_31_0_OFFSET 0x00000004 +#define TX_MPDU_START_PN_31_0_LSB 0 +#define TX_MPDU_START_PN_31_0_MSB 31 +#define TX_MPDU_START_PN_31_0_MASK 0xffffffff + +#define TX_MPDU_START_PN_47_32_OFFSET 0x00000008 +#define TX_MPDU_START_PN_47_32_LSB 0 +#define TX_MPDU_START_PN_47_32_MSB 15 +#define TX_MPDU_START_PN_47_32_MASK 0x0000ffff + +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x0fff0000 + +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x00000008 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x10000000 + +#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x00000008 +#define TX_MPDU_START_FRAME_TYPE_LSB 29 +#define TX_MPDU_START_FRAME_TYPE_MSB 30 +#define TX_MPDU_START_FRAME_TYPE_MASK 0x60000000 + +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x00000008 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x80000000 + +#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000c +#define TX_MPDU_START_IV_BYTE_0_LSB 0 +#define TX_MPDU_START_IV_BYTE_0_MSB 7 +#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000c +#define TX_MPDU_START_IV_BYTE_1_LSB 8 +#define TX_MPDU_START_IV_BYTE_1_MSB 15 +#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000c +#define TX_MPDU_START_IV_BYTE_2_LSB 16 +#define TX_MPDU_START_IV_BYTE_2_MSB 23 +#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff0000 + +#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000c +#define TX_MPDU_START_IV_BYTE_3_LSB 24 +#define TX_MPDU_START_IV_BYTE_3_MSB 31 +#define TX_MPDU_START_IV_BYTE_3_MASK 0xff000000 + +#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x00000010 +#define TX_MPDU_START_IV_BYTE_4_LSB 0 +#define TX_MPDU_START_IV_BYTE_4_MSB 7 +#define TX_MPDU_START_IV_BYTE_4_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x00000010 +#define TX_MPDU_START_IV_BYTE_5_LSB 8 +#define TX_MPDU_START_IV_BYTE_5_MSB 15 +#define TX_MPDU_START_IV_BYTE_5_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x00000010 +#define TX_MPDU_START_IV_BYTE_6_LSB 16 +#define TX_MPDU_START_IV_BYTE_6_MSB 23 +#define TX_MPDU_START_IV_BYTE_6_MASK 0x00ff0000 + +#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x00000010 +#define TX_MPDU_START_IV_BYTE_7_LSB 24 +#define TX_MPDU_START_IV_BYTE_7_MSB 31 +#define TX_MPDU_START_IV_BYTE_7_MASK 0xff000000 + +#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x00000014 +#define TX_MPDU_START_IV_BYTE_8_LSB 0 +#define TX_MPDU_START_IV_BYTE_8_MSB 7 +#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x00000014 +#define TX_MPDU_START_IV_BYTE_9_LSB 8 +#define TX_MPDU_START_IV_BYTE_9_MSB 15 +#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x00000014 +#define TX_MPDU_START_IV_BYTE_10_LSB 16 +#define TX_MPDU_START_IV_BYTE_10_MSB 23 +#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff0000 + +#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x00000014 +#define TX_MPDU_START_IV_BYTE_11_LSB 24 +#define TX_MPDU_START_IV_BYTE_11_MSB 31 +#define TX_MPDU_START_IV_BYTE_11_MASK 0xff000000 + +#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x00000018 +#define TX_MPDU_START_IV_BYTE_12_LSB 0 +#define TX_MPDU_START_IV_BYTE_12_MSB 7 +#define TX_MPDU_START_IV_BYTE_12_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x00000018 +#define TX_MPDU_START_IV_BYTE_13_LSB 8 +#define TX_MPDU_START_IV_BYTE_13_MSB 15 +#define TX_MPDU_START_IV_BYTE_13_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x00000018 +#define TX_MPDU_START_IV_BYTE_14_LSB 16 +#define TX_MPDU_START_IV_BYTE_14_MSB 23 +#define TX_MPDU_START_IV_BYTE_14_MASK 0x00ff0000 + +#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x00000018 +#define TX_MPDU_START_IV_BYTE_15_LSB 24 +#define TX_MPDU_START_IV_BYTE_15_MSB 31 +#define TX_MPDU_START_IV_BYTE_15_MASK 0xff000000 + +#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000001c +#define TX_MPDU_START_IV_BYTE_16_LSB 0 +#define TX_MPDU_START_IV_BYTE_16_MSB 7 +#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000001c +#define TX_MPDU_START_IV_BYTE_17_LSB 8 +#define TX_MPDU_START_IV_BYTE_17_MSB 15 +#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_LEN_OFFSET 0x0000001c +#define TX_MPDU_START_IV_LEN_LSB 16 +#define TX_MPDU_START_IV_LEN_MSB 20 +#define TX_MPDU_START_IV_LEN_MASK 0x001f0000 + +#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000001c +#define TX_MPDU_START_ICV_LEN_LSB 21 +#define TX_MPDU_START_ICV_LEN_MSB 25 +#define TX_MPDU_START_ICV_LEN_MASK 0x03e00000 + +#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000001c +#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 26 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 31 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc000000 + +#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x00000020 +#define TX_MPDU_START_MPDU_TYPE_LSB 0 +#define TX_MPDU_START_MPDU_TYPE_MSB 0 +#define TX_MPDU_START_MPDU_TYPE_MASK 0x00000001 + +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x00000020 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x00000002 + +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x00000020 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x0000003c + +#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x00000020 +#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x000001c0 + +#define TX_MPDU_START_RESERVED_8A_OFFSET 0x00000020 +#define TX_MPDU_START_RESERVED_8A_LSB 9 +#define TX_MPDU_START_RESERVED_8A_MSB 31 +#define TX_MPDU_START_RESERVED_8A_MASK 0xfffffe00 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_msdu_extension.h b/drivers/staging/fw-api/hw/peach/v1/tx_msdu_extension.h new file mode 100644 index 0000000000000000000000000000000000000000..6bceb28ed8381d22bd09a9da9d4923808221afd5 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_msdu_extension.h @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_MSDU_EXTENSION_H_ +#define _TX_MSDU_EXTENSION_H_ + +#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 + +struct tx_msdu_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tso_enable : 1, + reserved_0a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + reserved_0b : 7; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + udp_length : 16; + uint32_t checksum_offset : 14, + partial_checksum_en : 1, + reserved_4a : 1, + payload_start_offset : 14, + reserved_4b : 2; + uint32_t payload_end_offset : 14, + reserved_5a : 2, + wds : 1, + reserved_5b : 15; + uint32_t buf0_ptr_31_0 : 32; + uint32_t buf0_ptr_39_32 : 8, + extn_override : 1, + encap_type : 2, + encrypt_type : 4, + tqm_no_drop : 1, + buf0_len : 16; + uint32_t buf1_ptr_31_0 : 32; + uint32_t buf1_ptr_39_32 : 8, + epd : 1, + mesh_enable : 2, + reserved_9a : 5, + buf1_len : 16; + uint32_t buf2_ptr_31_0 : 32; + uint32_t buf2_ptr_39_32 : 8, + dscp_tid_table_num : 6, + reserved_11a : 2, + buf2_len : 16; + uint32_t buf3_ptr_31_0 : 32; + uint32_t buf3_ptr_39_32 : 8, + reserved_13a : 8, + buf3_len : 16; + uint32_t buf4_ptr_31_0 : 32; + uint32_t buf4_ptr_39_32 : 8, + reserved_15a : 8, + buf4_len : 16; + uint32_t buf5_ptr_31_0 : 32; + uint32_t buf5_ptr_39_32 : 8, + reserved_17a : 8, + buf5_len : 16; +#else + uint32_t reserved_0b : 7, + tcp_flag_mask : 9, + tcp_flag : 9, + reserved_0a : 6, + tso_enable : 1; + uint32_t ip_length : 16, + l2_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t udp_length : 16, + ip_identification : 16; + uint32_t reserved_4b : 2, + payload_start_offset : 14, + reserved_4a : 1, + partial_checksum_en : 1, + checksum_offset : 14; + uint32_t reserved_5b : 15, + wds : 1, + reserved_5a : 2, + payload_end_offset : 14; + uint32_t buf0_ptr_31_0 : 32; + uint32_t buf0_len : 16, + tqm_no_drop : 1, + encrypt_type : 4, + encap_type : 2, + extn_override : 1, + buf0_ptr_39_32 : 8; + uint32_t buf1_ptr_31_0 : 32; + uint32_t buf1_len : 16, + reserved_9a : 5, + mesh_enable : 2, + epd : 1, + buf1_ptr_39_32 : 8; + uint32_t buf2_ptr_31_0 : 32; + uint32_t buf2_len : 16, + reserved_11a : 2, + dscp_tid_table_num : 6, + buf2_ptr_39_32 : 8; + uint32_t buf3_ptr_31_0 : 32; + uint32_t buf3_len : 16, + reserved_13a : 8, + buf3_ptr_39_32 : 8; + uint32_t buf4_ptr_31_0 : 32; + uint32_t buf4_len : 16, + reserved_15a : 8, + buf4_ptr_39_32 : 8; + uint32_t buf5_ptr_31_0 : 32; + uint32_t buf5_len : 16, + reserved_17a : 8, + buf5_ptr_39_32 : 8; +#endif +}; + +#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 + +#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 +#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 +#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e + +#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 +#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 + +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 + +#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 +#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 + +#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 +#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 +#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 + +#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 + +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 + +#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 +#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 + +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 + +#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_WDS_LSB 16 +#define TX_MSDU_EXTENSION_WDS_MSB 16 +#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 + +#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 +#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 + +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK 0x00000100 + +#define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB 9 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB 10 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK 0x00000600 + +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB 11 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB 14 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK 0x00007800 + +#define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK 0x00008000 + +#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_EPD_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_EPD_LSB 8 +#define TX_MSDU_EXTENSION_EPD_MSB 8 +#define TX_MSDU_EXTENSION_EPD_MASK 0x00000100 + +#define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_MESH_ENABLE_LSB 9 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MSB 10 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MASK 0x00000600 + +#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 11 +#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000f800 + +#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_LSB 8 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MSB 13 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MASK 0x00003f00 + +#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000c000 + +#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_msdu_start.h b/drivers/staging/fw-api/hw/peach/v1/tx_msdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..3b9e5b1c2c2f27e56b8ae7c1e8eda7a71bbf7195 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_msdu_start.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_MSDU_START_H_ +#define _TX_MSDU_START_H_ + +#define NUM_OF_DWORDS_TX_MSDU_START 7 + +struct tx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_len : 14, + first_msdu : 1, + last_msdu : 1, + encap_type : 2, + epd_en : 1, + da_sa_present : 2, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + dummy_msdu_delimitation : 1, + reserved_0a : 5; + uint32_t tso_enable : 1, + reserved_1a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + mesh_enable : 1, + reserved_1b : 6; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + checksum_offset : 13, + partial_checksum_en : 1, + reserved_4 : 2; + uint32_t payload_start_offset : 14, + reserved_5a : 2, + payload_end_offset : 14, + reserved_5b : 2; + uint32_t udp_length : 16, + reserved_6 : 16; +#else + uint32_t reserved_0a : 5, + dummy_msdu_delimitation : 1, + tcp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + ipv4_checksum_en : 1, + da_sa_present : 2, + epd_en : 1, + encap_type : 2, + last_msdu : 1, + first_msdu : 1, + msdu_len : 14; + uint32_t reserved_1b : 6, + mesh_enable : 1, + tcp_flag_mask : 9, + tcp_flag : 9, + reserved_1a : 6, + tso_enable : 1; + uint32_t ip_length : 16, + l2_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t reserved_4 : 2, + partial_checksum_en : 1, + checksum_offset : 13, + ip_identification : 16; + uint32_t reserved_5b : 2, + payload_end_offset : 14, + reserved_5a : 2, + payload_start_offset : 14; + uint32_t reserved_6 : 16, + udp_length : 16; +#endif +}; + +#define TX_MSDU_START_MSDU_LEN_OFFSET 0x00000000 +#define TX_MSDU_START_MSDU_LEN_LSB 0 +#define TX_MSDU_START_MSDU_LEN_MSB 13 +#define TX_MSDU_START_MSDU_LEN_MASK 0x00003fff + +#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x00000000 +#define TX_MSDU_START_FIRST_MSDU_LSB 14 +#define TX_MSDU_START_FIRST_MSDU_MSB 14 +#define TX_MSDU_START_FIRST_MSDU_MASK 0x00004000 + +#define TX_MSDU_START_LAST_MSDU_OFFSET 0x00000000 +#define TX_MSDU_START_LAST_MSDU_LSB 15 +#define TX_MSDU_START_LAST_MSDU_MSB 15 +#define TX_MSDU_START_LAST_MSDU_MASK 0x00008000 + +#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x00000000 +#define TX_MSDU_START_ENCAP_TYPE_LSB 16 +#define TX_MSDU_START_ENCAP_TYPE_MSB 17 +#define TX_MSDU_START_ENCAP_TYPE_MASK 0x00030000 + +#define TX_MSDU_START_EPD_EN_OFFSET 0x00000000 +#define TX_MSDU_START_EPD_EN_LSB 18 +#define TX_MSDU_START_EPD_EN_MSB 18 +#define TX_MSDU_START_EPD_EN_MASK 0x00040000 + +#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x00000000 +#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 +#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 +#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x00180000 + +#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x00200000 + +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00400000 + +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00800000 + +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x01000000 + +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x02000000 + +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x00000000 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x04000000 + +#define TX_MSDU_START_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_START_RESERVED_0A_LSB 27 +#define TX_MSDU_START_RESERVED_0A_MSB 31 +#define TX_MSDU_START_RESERVED_0A_MASK 0xf8000000 + +#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x00000004 +#define TX_MSDU_START_TSO_ENABLE_LSB 0 +#define TX_MSDU_START_TSO_ENABLE_MSB 0 +#define TX_MSDU_START_TSO_ENABLE_MASK 0x00000001 + +#define TX_MSDU_START_RESERVED_1A_OFFSET 0x00000004 +#define TX_MSDU_START_RESERVED_1A_LSB 1 +#define TX_MSDU_START_RESERVED_1A_MSB 6 +#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e + +#define TX_MSDU_START_TCP_FLAG_OFFSET 0x00000004 +#define TX_MSDU_START_TCP_FLAG_LSB 7 +#define TX_MSDU_START_TCP_FLAG_MSB 15 +#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff80 + +#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x00000004 +#define TX_MSDU_START_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_START_TCP_FLAG_MASK_MSB 24 +#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff0000 + +#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x00000004 +#define TX_MSDU_START_MESH_ENABLE_LSB 25 +#define TX_MSDU_START_MESH_ENABLE_MSB 25 +#define TX_MSDU_START_MESH_ENABLE_MASK 0x02000000 + +#define TX_MSDU_START_RESERVED_1B_OFFSET 0x00000004 +#define TX_MSDU_START_RESERVED_1B_LSB 26 +#define TX_MSDU_START_RESERVED_1B_MSB 31 +#define TX_MSDU_START_RESERVED_1B_MASK 0xfc000000 + +#define TX_MSDU_START_L2_LENGTH_OFFSET 0x00000008 +#define TX_MSDU_START_L2_LENGTH_LSB 0 +#define TX_MSDU_START_L2_LENGTH_MSB 15 +#define TX_MSDU_START_L2_LENGTH_MASK 0x0000ffff + +#define TX_MSDU_START_IP_LENGTH_OFFSET 0x00000008 +#define TX_MSDU_START_IP_LENGTH_LSB 16 +#define TX_MSDU_START_IP_LENGTH_MSB 31 +#define TX_MSDU_START_IP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000c +#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 31 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x00000010 +#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x0000ffff + +#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 +#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 +#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x1fff0000 + +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x20000000 + +#define TX_MSDU_START_RESERVED_4_OFFSET 0x00000010 +#define TX_MSDU_START_RESERVED_4_LSB 30 +#define TX_MSDU_START_RESERVED_4_MSB 31 +#define TX_MSDU_START_RESERVED_4_MASK 0xc0000000 + +#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 0 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 13 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff + +#define TX_MSDU_START_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_START_RESERVED_5A_LSB 14 +#define TX_MSDU_START_RESERVED_5A_MSB 15 +#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c000 + +#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 16 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 29 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff0000 + +#define TX_MSDU_START_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_START_RESERVED_5B_LSB 30 +#define TX_MSDU_START_RESERVED_5B_MSB 31 +#define TX_MSDU_START_RESERVED_5B_MASK 0xc0000000 + +#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x00000018 +#define TX_MSDU_START_UDP_LENGTH_LSB 0 +#define TX_MSDU_START_UDP_LENGTH_MSB 15 +#define TX_MSDU_START_UDP_LENGTH_MASK 0x0000ffff + +#define TX_MSDU_START_RESERVED_6_OFFSET 0x00000018 +#define TX_MSDU_START_RESERVED_6_LSB 16 +#define TX_MSDU_START_RESERVED_6_MSB 31 +#define TX_MSDU_START_RESERVED_6_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_peer_entry.h b/drivers/staging/fw-api/hw/peach/v1/tx_peer_entry.h new file mode 100644 index 0000000000000000000000000000000000000000..4011563b7f7b0bf3300368b48b804a5b9a448079 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_peer_entry.h @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_PEER_ENTRY_H_ +#define _TX_PEER_ENTRY_H_ + +#define NUM_OF_DWORDS_TX_PEER_ENTRY 18 + +struct tx_peer_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mac_addr_a_31_0 : 32; + uint32_t mac_addr_a_47_32 : 16, + mac_addr_b_15_0 : 16; + uint32_t mac_addr_b_47_16 : 32; + uint32_t use_ad_b : 1, + strip_insert_vlan_inner : 1, + strip_insert_vlan_outer : 1, + vlan_llc_mode : 1, + key_type : 4, + a_msdu_wds_ad3_ad4 : 3, + ignore_hard_filters : 1, + ignore_soft_filters : 1, + epd_output : 1, + wds : 1, + insert_or_strip : 1, + sw_filter_id : 16; + uint32_t temporal_key_31_0 : 32; + uint32_t temporal_key_63_32 : 32; + uint32_t temporal_key_95_64 : 32; + uint32_t temporal_key_127_96 : 32; + uint32_t temporal_key_159_128 : 32; + uint32_t temporal_key_191_160 : 32; + uint32_t temporal_key_223_192 : 32; + uint32_t temporal_key_255_224 : 32; + uint32_t sta_partial_aid : 11, + transmit_vif : 4, + block_this_user : 1, + mesh_amsdu_mode : 2, + use_qos_alt_mute_mask : 1, + dl_ul_direction : 1, + reserved_12 : 12; + uint32_t insert_vlan_outer_tci : 16, + insert_vlan_inner_tci : 16; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0008 : 16, + __reserved_g_0009 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t multi_link_addr_crypto_enable : 1, + reserved_17a : 15, + sw_peer_id : 16; +#else + uint32_t mac_addr_a_31_0 : 32; + uint32_t mac_addr_b_15_0 : 16, + mac_addr_a_47_32 : 16; + uint32_t mac_addr_b_47_16 : 32; + uint32_t sw_filter_id : 16, + insert_or_strip : 1, + wds : 1, + epd_output : 1, + ignore_soft_filters : 1, + ignore_hard_filters : 1, + a_msdu_wds_ad3_ad4 : 3, + key_type : 4, + vlan_llc_mode : 1, + strip_insert_vlan_outer : 1, + strip_insert_vlan_inner : 1, + use_ad_b : 1; + uint32_t temporal_key_31_0 : 32; + uint32_t temporal_key_63_32 : 32; + uint32_t temporal_key_95_64 : 32; + uint32_t temporal_key_127_96 : 32; + uint32_t temporal_key_159_128 : 32; + uint32_t temporal_key_191_160 : 32; + uint32_t temporal_key_223_192 : 32; + uint32_t temporal_key_255_224 : 32; + uint32_t reserved_12 : 12, + dl_ul_direction : 1, + use_qos_alt_mute_mask : 1, + mesh_amsdu_mode : 2, + block_this_user : 1, + transmit_vif : 4, + sta_partial_aid : 11; + uint32_t insert_vlan_inner_tci : 16, + insert_vlan_outer_tci : 16; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0009 : 16, + __reserved_g_0008 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t sw_peer_id : 16, + reserved_17a : 15, + multi_link_addr_crypto_enable : 1; +#endif +}; + +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x00000000 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0xffffffff + +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x00000004 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 15 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff + +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x00000004 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 16 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff0000 + +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x00000008 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0xffffffff + +#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000c +#define TX_PEER_ENTRY_USE_AD_B_LSB 0 +#define TX_PEER_ENTRY_USE_AD_B_MSB 0 +#define TX_PEER_ENTRY_USE_AD_B_MASK 0x00000001 + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000c +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 1 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 1 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x00000002 + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000c +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 2 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 2 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x00000004 + +#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000c +#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 3 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 3 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x00000008 + +#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000c +#define TX_PEER_ENTRY_KEY_TYPE_LSB 4 +#define TX_PEER_ENTRY_KEY_TYPE_MSB 7 +#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f0 + +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000c +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 8 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 10 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x00000700 + +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000c +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 11 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 11 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x00000800 + +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000c +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 12 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 12 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x00001000 + +#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000c +#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 13 +#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 13 +#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x00002000 + +#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000c +#define TX_PEER_ENTRY_WDS_LSB 14 +#define TX_PEER_ENTRY_WDS_MSB 14 +#define TX_PEER_ENTRY_WDS_MASK 0x00004000 + +#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000c +#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 15 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 15 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x00008000 + +#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000c +#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 16 +#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 31 +#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff0000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x00000010 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x00000014 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x00000018 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000001c +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x00000020 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x00000024 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x00000028 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000002c +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff + +#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x00000030 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x000007ff + +#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x00000030 +#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x00007800 + +#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x00000030 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x00008000 + +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x00000030 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x00030000 + +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x00000030 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x00040000 + +#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x00000030 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x00080000 + +#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x00000030 +#define TX_PEER_ENTRY_RESERVED_12_LSB 20 +#define TX_PEER_ENTRY_RESERVED_12_MSB 31 +#define TX_PEER_ENTRY_RESERVED_12_MASK 0xfff00000 + +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x00000034 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 0 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 15 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff + +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x00000034 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 16 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 31 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff0000 + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x00000044 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 0 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 0 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x00000001 + +#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x00000044 +#define TX_PEER_ENTRY_RESERVED_17A_LSB 1 +#define TX_PEER_ENTRY_RESERVED_17A_MSB 15 +#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe + +#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x00000044 +#define TX_PEER_ENTRY_SW_PEER_ID_LSB 16 +#define TX_PEER_ENTRY_SW_PEER_ID_MSB 31 +#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_queue_extension.h b/drivers/staging/fw-api/hw/peach/v1/tx_queue_extension.h new file mode 100644 index 0000000000000000000000000000000000000000..7b0d123d544bbd6f8e7b86f80e7b7ceed528b8be --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_queue_extension.h @@ -0,0 +1,316 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_QUEUE_EXTENSION_H_ +#define _TX_QUEUE_EXTENSION_H_ + +#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 + +struct tx_queue_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t frame_ctl : 16, + qos_ctl : 16; + uint32_t ampdu_flag : 1, + tx_notify_no_htc_override : 1, + reserved_1a : 7, + checksum_tso_disable_for_frag : 1, + key_id : 8, + qos_buf_state_overwrite : 1, + buf_state_sta_id : 1, + buf_state_source : 1, + ht_control_overwrite_enable : 1, + ht_control_overwrite_source : 4, + reserved_1b : 6; + uint32_t ul_headroom_insertion_enable : 1, + ul_headroom_offset : 5, + bqrp_insertion_enable : 1, + bqrp_offset : 5, + ul_headroom_rsvd_7_6 : 2, + bqr_rsvd_9_8 : 2, + base_pn_63_48 : 16; + uint32_t base_pn_95_64 : 32; + uint32_t base_pn_127_96 : 32; + uint32_t ht_control_field_bw20 : 32; + uint32_t ht_control_field_bw40 : 32; + uint32_t ht_control_field_bw80 : 32; + uint32_t ht_control_field_bw160 : 32; + uint32_t ht_control_overwrite_mask : 32; + uint32_t cas_control_info : 8, + cas_offset : 5, + cas_insertion_enable : 1, + reserved_10a : 2, + ht_control_overwrite_source_for_srp : 4, + ht_control_overwrite_source_for_bsrp : 4, + reserved_10b : 6, + mpdu_hdr_len_override_en : 1, + bar_ssn_overwrite_enable : 1; + uint32_t bar_ssn_offset : 12, + mpdu_hdr_len_override_val : 9, + reserved_11a : 11; + uint32_t ht_control_field_bw320 : 32; + uint32_t fw2sw_info : 32; +#else + uint32_t qos_ctl : 16, + frame_ctl : 16; + uint32_t reserved_1b : 6, + ht_control_overwrite_source : 4, + ht_control_overwrite_enable : 1, + buf_state_source : 1, + buf_state_sta_id : 1, + qos_buf_state_overwrite : 1, + key_id : 8, + checksum_tso_disable_for_frag : 1, + reserved_1a : 7, + tx_notify_no_htc_override : 1, + ampdu_flag : 1; + uint32_t base_pn_63_48 : 16, + bqr_rsvd_9_8 : 2, + ul_headroom_rsvd_7_6 : 2, + bqrp_offset : 5, + bqrp_insertion_enable : 1, + ul_headroom_offset : 5, + ul_headroom_insertion_enable : 1; + uint32_t base_pn_95_64 : 32; + uint32_t base_pn_127_96 : 32; + uint32_t ht_control_field_bw20 : 32; + uint32_t ht_control_field_bw40 : 32; + uint32_t ht_control_field_bw80 : 32; + uint32_t ht_control_field_bw160 : 32; + uint32_t ht_control_overwrite_mask : 32; + uint32_t bar_ssn_overwrite_enable : 1, + mpdu_hdr_len_override_en : 1, + reserved_10b : 6, + ht_control_overwrite_source_for_bsrp : 4, + ht_control_overwrite_source_for_srp : 4, + reserved_10a : 2, + cas_insertion_enable : 1, + cas_offset : 5, + cas_control_info : 8; + uint32_t reserved_11a : 11, + mpdu_hdr_len_override_val : 9, + bar_ssn_offset : 12; + uint32_t ht_control_field_bw320 : 32; + uint32_t fw2sw_info : 32; +#endif +}; + +#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x00000000 +#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x0000ffff + +#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x00000000 +#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 +#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 +#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0xffff0000 + +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 0 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 0 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x00000001 + +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 1 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 1 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x00000002 + +#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 2 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 8 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc + +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 9 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 9 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x00000200 + +#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_KEY_ID_LSB 10 +#define TX_QUEUE_EXTENSION_KEY_ID_MSB 17 +#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc00 + +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 18 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 18 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x00040000 + +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 19 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 19 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x00080000 + +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 20 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 20 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x00100000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 21 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 21 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x00200000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 22 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 25 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c00000 + +#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 26 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 31 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc000000 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x00000001 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x0000003e + +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x00000040 + +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x00000f80 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x00003000 + +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x0000c000 + +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0xffff0000 + +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000c +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 0 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x00000010 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x00000014 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x00000018 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000001c +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x00000020 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x00000024 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x000000ff + +#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x00001f00 + +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x00002000 + +#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x0000c000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x000f0000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x00f00000 + +#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x3f000000 + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x40000000 + +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x80000000 + +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000002c +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 0 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 11 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000002c +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 12 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 20 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff000 + +#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000002c +#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 21 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 31 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe00000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x00000030 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x00000034 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 0 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 31 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/peach/v1/tx_rate_stats_info.h new file mode 100644 index 0000000000000000000000000000000000000000..4f311a2d6ea9fc6d85c7c1cb4bf467f192af45d5 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_rate_stats_info.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_RATE_STATS_INFO_H_ +#define _TX_RATE_STATS_INFO_H_ + +#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 + +struct tx_rate_stats_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_rate_stats_info_valid : 1, + transmit_bw : 3, + transmit_pkt_type : 4, + transmit_stbc : 1, + transmit_ldpc : 1, + transmit_sgi : 2, + transmit_mcs : 4, + ofdma_transmission : 1, + tones_in_ru : 12, + transmit_nss : 3; + uint32_t ppdu_transmission_tsf : 32; +#else + uint32_t transmit_nss : 3, + tones_in_ru : 12, + ofdma_transmission : 1, + transmit_mcs : 4, + transmit_sgi : 2, + transmit_ldpc : 1, + transmit_stbc : 1, + transmit_pkt_type : 4, + transmit_bw : 3, + tx_rate_stats_info_valid : 1; + uint32_t ppdu_transmission_tsf : 32; +#endif +}; + +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e + +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100 + +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200 + +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00 + +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 15 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0000f000 + +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00010000 + +#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 17 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1ffe0000 + +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB 29 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB 31 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK 0xe0000000 + +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/peach/v1/tx_raw_or_native_frame_setup.h new file mode 100644 index 0000000000000000000000000000000000000000..468ff4919f5a6cc6f985281a08f335ac050900c1 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/tx_raw_or_native_frame_setup.h @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ +#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ + +#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 + +struct tx_raw_or_native_frame_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fc_to_ds_mask : 1, + fc_from_ds_mask : 1, + fc_more_frag_mask : 1, + fc_retry_mask : 1, + fc_pwr_mgt_mask : 1, + fc_more_data_mask : 1, + fc_prot_frame_mask : 1, + fc_order_mask : 1, + duration_field_mask : 1, + sequence_control_mask : 1, + qc_tid_mask : 1, + qc_eosp_mask : 1, + qc_ack_policy_mask : 1, + qc_amsdu_mask : 1, + reserved_0a : 1, + qc_15to8_mask : 1, + iv_mask : 1, + fc_to_ds_setting : 1, + fc_from_ds_setting : 1, + fc_more_frag_setting : 1, + fc_retry_setting : 2, + fc_pwr_mgt_setting : 1, + fc_more_data_setting : 2, + fc_prot_frame_setting : 2, + fc_order_setting : 1, + qc_tid_setting : 4; + uint32_t qc_eosp_setting : 2, + qc_ack_policy_setting : 2, + qc_amsdu_setting : 1, + qc_15to8_setting : 8, + mlo_addr_override : 1, + mlo_ignore_addr3_override : 1, + sequence_control_source : 1, + fragment_number : 4, + sequence_number : 12; +#else + uint32_t qc_tid_setting : 4, + fc_order_setting : 1, + fc_prot_frame_setting : 2, + fc_more_data_setting : 2, + fc_pwr_mgt_setting : 1, + fc_retry_setting : 2, + fc_more_frag_setting : 1, + fc_from_ds_setting : 1, + fc_to_ds_setting : 1, + iv_mask : 1, + qc_15to8_mask : 1, + reserved_0a : 1, + qc_amsdu_mask : 1, + qc_ack_policy_mask : 1, + qc_eosp_mask : 1, + qc_tid_mask : 1, + sequence_control_mask : 1, + duration_field_mask : 1, + fc_order_mask : 1, + fc_prot_frame_mask : 1, + fc_more_data_mask : 1, + fc_pwr_mgt_mask : 1, + fc_retry_mask : 1, + fc_more_frag_mask : 1, + fc_from_ds_mask : 1, + fc_to_ds_mask : 1; + uint32_t sequence_number : 12, + fragment_number : 4, + sequence_control_source : 1, + mlo_ignore_addr3_override : 1, + mlo_addr_override : 1, + qc_15to8_setting : 8, + qc_amsdu_setting : 1, + qc_ack_policy_setting : 2, + qc_eosp_setting : 2; +#endif +}; + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x00000001 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x00000002 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x00000004 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x00000008 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x00000010 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x00000020 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x00000040 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x00000080 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x00000100 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x00000200 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x00000400 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x00000800 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x00001000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x00002000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x00004000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x00008000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x00010000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x00020000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x00040000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x00080000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x00300000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x00400000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x01800000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x06000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x08000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0xf0000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x00000003 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x00000010 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe0 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x00002000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x00004000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x00008000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f0000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 20 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 31 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff00000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/peach/v1/txpcu_buffer_basics.h new file mode 100644 index 0000000000000000000000000000000000000000..236c1b83af92cbba62b3ba5156e2ccf973e68754 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/txpcu_buffer_basics.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TXPCU_BUFFER_BASICS_H_ +#define _TXPCU_BUFFER_BASICS_H_ + +#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 + +struct txpcu_buffer_basics { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t available_memory : 8, + partial_tx_data_tlv_count : 8, + tx_data_tlv_count : 16; +#else + uint32_t tx_data_tlv_count : 16, + partial_tx_data_tlv_count : 8, + available_memory : 8; +#endif +}; + +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff + +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/peach/v1/txpcu_buffer_status.h new file mode 100644 index 0000000000000000000000000000000000000000..f9d49adf23a235a5949accea441744bbc96eb1fc --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/txpcu_buffer_status.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TXPCU_BUFFER_STATUS_H_ +#define _TXPCU_BUFFER_STATUS_H_ + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 + +struct txpcu_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t reserved : 15, + msdu_end : 1, + tx_data_sync_value : 16; +#else + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t tx_data_sync_value : 16, + msdu_end : 1, + reserved : 15; +#endif +}; + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x000000ff + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0xffff0000 + +#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x00000004 +#define TXPCU_BUFFER_STATUS_RESERVED_LSB 0 +#define TXPCU_BUFFER_STATUS_RESERVED_MSB 14 +#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff + +#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x00000004 +#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 15 +#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 15 +#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x00008000 + +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x00000004 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 16 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 31 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/peach/v1/txpcu_user_buffer_status.h new file mode 100644 index 0000000000000000000000000000000000000000..f6d6f049fcc5a89e08eb338897848aa39b2526e4 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/txpcu_user_buffer_status.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TXPCU_USER_BUFFER_STATUS_H_ +#define _TXPCU_USER_BUFFER_STATUS_H_ + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 + +struct txpcu_user_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t stored_word_count_user : 14, + reserved_1a : 1, + msdu_end : 1, + tx_data_sync_value : 16; +#else + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t tx_data_sync_value : 16, + msdu_end : 1, + reserved_1a : 1, + stored_word_count_user : 14; +#endif +}; + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x000000ff + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0xffff0000 + +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x00000004 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 0 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 13 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff + +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x00000004 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 14 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 14 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x00004000 + +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x00000004 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 15 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 15 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x00008000 + +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x00000004 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 16 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 31 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/peach/v1/u_sig_eht_su_mu_info.h new file mode 100644 index 0000000000000000000000000000000000000000..9e2f1616e31fd7c9e4dcb6c2d80aef0c3a95ae61 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/u_sig_eht_su_mu_info.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _U_SIG_EHT_SU_MU_INFO_H_ +#define _U_SIG_EHT_SU_MU_INFO_H_ + +#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 + +struct u_sig_eht_su_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, + transmit_bw : 3, + dl_ul_flag : 1, + bss_color_id : 6, + txop_duration : 7, + disregard_0a : 5, + validate_0b : 1, + reserved_0c : 6; + uint32_t eht_ppdu_sig_cmn_type : 2, + validate_1a : 1, + punctured_channel_information : 5, + validate_1b : 1, + mcs_of_eht_sig : 2, + num_eht_sig_symbols : 5, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + reserved_1d : 3, + rx_ndp : 1, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0c : 6, + validate_0b : 1, + disregard_0a : 5, + txop_duration : 7, + bss_color_id : 6, + dl_ul_flag : 1, + transmit_bw : 3, + phy_version : 3; + uint32_t rx_integrity_check_passed : 1, + rx_ndp : 1, + reserved_1d : 3, + dot11ax_su_extended : 1, + tail : 6, + crc : 4, + num_eht_sig_symbols : 5, + mcs_of_eht_sig : 2, + validate_1b : 1, + punctured_channel_information : 5, + validate_1a : 1, + eht_ppdu_sig_cmn_type : 2; +#endif +}; + +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 + +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 + +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 + +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 + +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 + +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 + +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 + +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 + +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 + +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 + +#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 +#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 + +#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 + +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 + +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 + +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/peach/v1/u_sig_eht_tb_info.h new file mode 100644 index 0000000000000000000000000000000000000000..1240c159f708d2a1f5500820483a5c4b760f48f4 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/u_sig_eht_tb_info.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _U_SIG_EHT_TB_INFO_H_ +#define _U_SIG_EHT_TB_INFO_H_ + +#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 + +struct u_sig_eht_tb_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, + transmit_bw : 3, + dl_ul_flag : 1, + bss_color_id : 6, + txop_duration : 7, + disregard_0a : 6, + reserved_0c : 6; + uint32_t eht_ppdu_sig_cmn_type : 2, + validate_1a : 1, + spatial_reuse : 8, + disregard_1b : 5, + crc : 4, + tail : 6, + reserved_1c : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0c : 6, + disregard_0a : 6, + txop_duration : 7, + bss_color_id : 6, + dl_ul_flag : 1, + transmit_bw : 3, + phy_version : 3; + uint32_t rx_integrity_check_passed : 1, + reserved_1c : 5, + tail : 6, + crc : 4, + disregard_1b : 5, + spatial_reuse : 8, + validate_1a : 1, + eht_ppdu_sig_cmn_type : 2; +#endif +}; + +#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 + +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 + +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 + +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 + +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 + +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 + +#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 + +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 + +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 + +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 + +#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_CRC_LSB 16 +#define U_SIG_EHT_TB_INFO_CRC_MSB 19 +#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 + +#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 +#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 +#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 + +#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 + +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/peach/v1/unallocated_ru_160_info.h new file mode 100644 index 0000000000000000000000000000000000000000..da3c52bfc2170fa110cc7dd02fc866e2e35ed2aa --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/unallocated_ru_160_info.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _UNALLOCATED_RU_160_INFO_H_ +#define _UNALLOCATED_RU_160_INFO_H_ + +#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 + +struct unallocated_ru_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t subband80_0_cc0 : 8, + subband80_0_cc1 : 8, + subband80_1_cc0 : 8, + subband80_1_cc1 : 8; +#else + uint32_t subband80_1_cc1 : 8, + subband80_1_cc0 : 8, + subband80_0_cc1 : 8, + subband80_0_cc0 : 8; +#endif +}; + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/peach/v1/uniform_descriptor_header.h new file mode 100644 index 0000000000000000000000000000000000000000..efe58926b91fcb6716bb43103f6d42e44f2eb12c --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/uniform_descriptor_header.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ +#define _UNIFORM_DESCRIPTOR_HEADER_H_ + +#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 + +struct uniform_descriptor_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t owner : 4, + buffer_type : 4, + tx_mpdu_queue_number : 20, + reserved_0a : 4; +#else + uint32_t reserved_0a : 4, + tx_mpdu_queue_number : 20, + buffer_type : 4, + owner : 4; +#endif +}; + +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +/* RESERVED is overlapping with TX_MPDU_QUEUE_NUMBER + * TX_MPDU_QUEUE_NUMBER valid on in Buffer_type is any of Transmit_MPDU_*_descriptor + * Where as RESERVED is only used for debugging in REO_QUEUE_Descr reo_queue_desc + */ +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/uniform_reo_cmd_header.h b/drivers/staging/fw-api/hw/peach/v1/uniform_reo_cmd_header.h new file mode 100644 index 0000000000000000000000000000000000000000..e9139b54e9b23cb627090e4b350070a3264f39ee --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/uniform_reo_cmd_header.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _UNIFORM_REO_CMD_HEADER_H_ +#define _UNIFORM_REO_CMD_HEADER_H_ + +#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1 + +struct uniform_reo_cmd_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_cmd_number : 16, + reo_status_required : 1, + reserved_0a : 15; +#else + uint32_t reserved_0a : 15, + reo_status_required : 1, + reo_cmd_number : 16; +#endif +}; + +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_LSB 17 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/uniform_reo_status_header.h b/drivers/staging/fw-api/hw/peach/v1/uniform_reo_status_header.h new file mode 100644 index 0000000000000000000000000000000000000000..988ba6e05ec05884d544bbd8a9eb28f236ed86b4 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/uniform_reo_status_header.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _UNIFORM_REO_STATUS_HEADER_H_ +#define _UNIFORM_REO_STATUS_HEADER_H_ + +#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2 + +struct uniform_reo_status_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_status_number : 16, + cmd_execution_time : 10, + reo_cmd_execution_status : 2, + reserved_0a : 4; + uint32_t timestamp : 32; +#else + uint32_t reserved_0a : 4, + reo_cmd_execution_status : 2, + cmd_execution_time : 10, + reo_status_number : 16; + uint32_t timestamp : 32; +#endif +}; + +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_LSB 28 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_a_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_a_info.h new file mode 100644 index 0000000000000000000000000000000000000000..6b20f8f904f831655dd77c975f6c2236b7bc4233 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_a_info.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_A_INFO_H_ +#define _VHT_SIG_A_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 + +struct vht_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t bandwidth : 2, + vhta_reserved_0 : 1, + stbc : 1, + group_id : 6, + n_sts : 12, + txop_ps_not_allowed : 1, + vhta_reserved_0b : 1, + reserved_0 : 8; + uint32_t gi_setting : 2, + su_mu_coding : 1, + ldpc_extra_symbol : 1, + mcs : 4, + beamformed : 1, + vhta_reserved_1 : 1, + crc : 8, + tail : 6, + reserved_1 : 7, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0 : 8, + vhta_reserved_0b : 1, + txop_ps_not_allowed : 1, + n_sts : 12, + group_id : 6, + stbc : 1, + vhta_reserved_0 : 1, + bandwidth : 2; + uint32_t rx_integrity_check_passed : 1, + reserved_1 : 7, + tail : 6, + crc : 8, + vhta_reserved_1 : 1, + beamformed : 1, + mcs : 4, + ldpc_extra_symbol : 1, + su_mu_coding : 1, + gi_setting : 2; +#endif +}; + +#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0 +#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1 +#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003 + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004 + +#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_STBC_LSB 3 +#define VHT_SIG_A_INFO_STBC_MSB 3 +#define VHT_SIG_A_INFO_STBC_MASK 0x00000008 + +#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_GROUP_ID_LSB 4 +#define VHT_SIG_A_INFO_GROUP_ID_MSB 9 +#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0 + +#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_N_STS_LSB 10 +#define VHT_SIG_A_INFO_N_STS_MSB 21 +#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00 + +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000 + +#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_RESERVED_0_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000 + +#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_GI_SETTING_LSB 0 +#define VHT_SIG_A_INFO_GI_SETTING_MSB 1 +#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003 + +#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004 + +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_MCS_LSB 4 +#define VHT_SIG_A_INFO_MCS_MSB 7 +#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0 + +#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100 + +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200 + +#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_CRC_LSB 10 +#define VHT_SIG_A_INFO_CRC_MSB 17 +#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00 + +#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_TAIL_LSB 18 +#define VHT_SIG_A_INFO_TAIL_MSB 23 +#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000 + +#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RESERVED_1_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000 + +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu160_info.h new file mode 100644 index 0000000000000000000000000000000000000000..6709a5e3c87d2a10e48608c664b110389d0b467b --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu160_info.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_MU160_INFO_H_ +#define _VHT_SIG_B_MU160_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 + +struct vht_sig_b_mu160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + mcs : 4, + tail : 6, + reserved_0 : 3; + uint32_t length_copy_a : 19, + mcs_copy_a : 4, + tail_copy_a : 6, + reserved_1 : 3; + uint32_t length_copy_b : 19, + mcs_copy_b : 4, + tail_copy_b : 6, + reserved_2 : 3; + uint32_t length_copy_c : 19, + mcs_copy_c : 4, + tail_copy_c : 6, + reserved_3 : 3; + uint32_t length_copy_d : 19, + mcs_copy_d : 4, + tail_copy_d : 6, + reserved_4 : 3; + uint32_t length_copy_e : 19, + mcs_copy_e : 4, + tail_copy_e : 6, + reserved_5 : 3; + uint32_t length_copy_f : 19, + mcs_copy_f : 4, + tail_copy_f : 6, + mu_user_number : 3; + uint32_t length_copy_g : 19, + mcs_copy_g : 4, + tail_copy_g : 6, + reserved_7 : 3; +#else + uint32_t reserved_0 : 3, + tail : 6, + mcs : 4, + length : 19; + uint32_t reserved_1 : 3, + tail_copy_a : 6, + mcs_copy_a : 4, + length_copy_a : 19; + uint32_t reserved_2 : 3, + tail_copy_b : 6, + mcs_copy_b : 4, + length_copy_b : 19; + uint32_t reserved_3 : 3, + tail_copy_c : 6, + mcs_copy_c : 4, + length_copy_c : 19; + uint32_t reserved_4 : 3, + tail_copy_d : 6, + mcs_copy_d : 4, + length_copy_d : 19; + uint32_t reserved_5 : 3, + tail_copy_e : 6, + mcs_copy_e : 4, + length_copy_e : 19; + uint32_t mu_user_number : 3, + tail_copy_f : 6, + mcs_copy_f : 4, + length_copy_f : 19; + uint32_t reserved_7 : 3, + tail_copy_g : 6, + mcs_copy_g : 4, + length_copy_g : 19; +#endif +}; + +#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu20_info.h new file mode 100644 index 0000000000000000000000000000000000000000..3af2601c4424cf49959f9d4cba44c363a48e3d16 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu20_info.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_MU20_INFO_H_ +#define _VHT_SIG_B_MU20_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 + +struct vht_sig_b_mu20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 16, + mcs : 4, + tail : 6, + mu_user_number : 3, + reserved_0 : 3; +#else + uint32_t reserved_0 : 3, + mu_user_number : 3, + tail : 6, + mcs : 4, + length : 16; +#endif +}; + +#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 +#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff + +#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 +#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 +#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 + +#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 + +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 + +#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu40_info.h new file mode 100644 index 0000000000000000000000000000000000000000..565c9bd78fe09ff6389b65afbe3eda9cfac59f20 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu40_info.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_MU40_INFO_H_ +#define _VHT_SIG_B_MU40_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 + +struct vht_sig_b_mu40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, + mcs : 4, + tail : 6, + reserved_0 : 2, + mu_user_number : 3; + uint32_t length_copy : 17, + mcs_copy : 4, + tail_copy : 6, + reserved_1 : 5; +#else + uint32_t mu_user_number : 3, + reserved_0 : 2, + tail : 6, + mcs : 4, + length : 17; + uint32_t reserved_1 : 5, + tail_copy : 6, + mcs_copy : 4, + length_copy : 17; +#endif +}; + +#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff + +#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 + +#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 + +#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 + +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff + +#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 + +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 + +#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu80_info.h new file mode 100644 index 0000000000000000000000000000000000000000..5ede34ec87a45b24ccdf53b115cacc84a43793c8 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu80_info.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_MU80_INFO_H_ +#define _VHT_SIG_B_MU80_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 + +struct vht_sig_b_mu80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + mcs : 4, + tail : 6, + reserved_0 : 3; + uint32_t length_copy_a : 19, + mcs_copy_a : 4, + tail_copy_a : 6, + reserved_1 : 3; + uint32_t length_copy_b : 19, + mcs_copy_b : 4, + tail_copy_b : 6, + mu_user_number : 3; + uint32_t length_copy_c : 19, + mcs_copy_c : 4, + tail_copy_c : 6, + reserved_3 : 3; +#else + uint32_t reserved_0 : 3, + tail : 6, + mcs : 4, + length : 19; + uint32_t reserved_1 : 3, + tail_copy_a : 6, + mcs_copy_a : 4, + length_copy_a : 19; + uint32_t mu_user_number : 3, + tail_copy_b : 6, + mcs_copy_b : 4, + length_copy_b : 19; + uint32_t reserved_3 : 3, + tail_copy_c : 6, + mcs_copy_c : 4, + length_copy_c : 19; +#endif +}; + +#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su160_info.h new file mode 100644 index 0000000000000000000000000000000000000000..53e8156dc9377795b30e0983ac353b5650624de7 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su160_info.h @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_SU160_INFO_H_ +#define _VHT_SIG_B_SU160_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 + +struct vht_sig_b_su160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, + vhtb_reserved : 2, + tail : 6, + reserved_0 : 2, + rx_ndp : 1; + uint32_t length_copy_a : 21, + vhtb_reserved_copy_a : 2, + tail_copy_a : 6, + reserved_1 : 2, + rx_ndp_copy_a : 1; + uint32_t length_copy_b : 21, + vhtb_reserved_copy_b : 2, + tail_copy_b : 6, + reserved_2 : 2, + rx_ndp_copy_b : 1; + uint32_t length_copy_c : 21, + vhtb_reserved_copy_c : 2, + tail_copy_c : 6, + reserved_3 : 2, + rx_ndp_copy_c : 1; + uint32_t length_copy_d : 21, + vhtb_reserved_copy_d : 2, + tail_copy_d : 6, + reserved_4 : 2, + rx_ndp_copy_d : 1; + uint32_t length_copy_e : 21, + vhtb_reserved_copy_e : 2, + tail_copy_e : 6, + reserved_5 : 2, + rx_ndp_copy_e : 1; + uint32_t length_copy_f : 21, + vhtb_reserved_copy_f : 2, + tail_copy_f : 6, + reserved_6 : 2, + rx_ndp_copy_f : 1; + uint32_t length_copy_g : 21, + vhtb_reserved_copy_g : 2, + tail_copy_g : 6, + reserved_7 : 2, + rx_ndp_copy_g : 1; +#else + uint32_t rx_ndp : 1, + reserved_0 : 2, + tail : 6, + vhtb_reserved : 2, + length : 21; + uint32_t rx_ndp_copy_a : 1, + reserved_1 : 2, + tail_copy_a : 6, + vhtb_reserved_copy_a : 2, + length_copy_a : 21; + uint32_t rx_ndp_copy_b : 1, + reserved_2 : 2, + tail_copy_b : 6, + vhtb_reserved_copy_b : 2, + length_copy_b : 21; + uint32_t rx_ndp_copy_c : 1, + reserved_3 : 2, + tail_copy_c : 6, + vhtb_reserved_copy_c : 2, + length_copy_c : 21; + uint32_t rx_ndp_copy_d : 1, + reserved_4 : 2, + tail_copy_d : 6, + vhtb_reserved_copy_d : 2, + length_copy_d : 21; + uint32_t rx_ndp_copy_e : 1, + reserved_5 : 2, + tail_copy_e : 6, + vhtb_reserved_copy_e : 2, + length_copy_e : 21; + uint32_t rx_ndp_copy_f : 1, + reserved_6 : 2, + tail_copy_f : 6, + vhtb_reserved_copy_f : 2, + length_copy_f : 21; + uint32_t rx_ndp_copy_g : 1, + reserved_7 : 2, + tail_copy_g : 6, + vhtb_reserved_copy_g : 2, + length_copy_g : 21; +#endif +}; + +#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su20_info.h new file mode 100644 index 0000000000000000000000000000000000000000..1343f424b763b19ed639d8fe081540a6bfe23a46 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su20_info.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_SU20_INFO_H_ +#define _VHT_SIG_B_SU20_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 + +struct vht_sig_b_su20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, + vhtb_reserved : 3, + tail : 6, + reserved : 5, + rx_ndp : 1; +#else + uint32_t rx_ndp : 1, + reserved : 5, + tail : 6, + vhtb_reserved : 3, + length : 17; +#endif +}; + +#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff + +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 + +#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 + +#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 +#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 + +#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su40_info.h new file mode 100644 index 0000000000000000000000000000000000000000..1f0049317179977772b94eb4c12c7849a9c9d020 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su40_info.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_SU40_INFO_H_ +#define _VHT_SIG_B_SU40_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 + +struct vht_sig_b_su40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + vhtb_reserved : 2, + tail : 6, + reserved : 4, + rx_ndp : 1; + uint32_t length_copy : 19, + vhtb_reserved_copy : 2, + tail_copy : 6, + reserved_copy : 4, + rx_ndp_copy : 1; +#else + uint32_t rx_ndp : 1, + reserved : 4, + tail : 6, + vhtb_reserved : 2, + length : 19; + uint32_t rx_ndp_copy : 1, + reserved_copy : 4, + tail_copy : 6, + vhtb_reserved_copy : 2, + length_copy : 19; +#endif +}; + +#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 + +#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 + +#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 + +#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 + +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 + +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 + +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su80_info.h new file mode 100644 index 0000000000000000000000000000000000000000..ac47150f808834207476cfd3622563fe550536d7 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su80_info.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_SU80_INFO_H_ +#define _VHT_SIG_B_SU80_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 + +struct vht_sig_b_su80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, + vhtb_reserved : 2, + tail : 6, + reserved_0 : 2, + rx_ndp : 1; + uint32_t length_copy_a : 21, + vhtb_reserved_copy_a : 2, + tail_copy_a : 6, + reserved_1 : 2, + rx_ndp_copy_a : 1; + uint32_t length_copy_b : 21, + vhtb_reserved_copy_b : 2, + tail_copy_b : 6, + reserved_2 : 2, + rx_ndp_copy_b : 1; + uint32_t length_copy_c : 21, + vhtb_reserved_copy_c : 2, + tail_copy_c : 6, + reserved_3 : 2, + rx_ndp_copy_c : 1; +#else + uint32_t rx_ndp : 1, + reserved_0 : 2, + tail : 6, + vhtb_reserved : 2, + length : 21; + uint32_t rx_ndp_copy_a : 1, + reserved_1 : 2, + tail_copy_a : 6, + vhtb_reserved_copy_a : 2, + length_copy_a : 21; + uint32_t rx_ndp_copy_b : 1, + reserved_2 : 2, + tail_copy_b : 6, + vhtb_reserved_copy_b : 2, + length_copy_b : 21; + uint32_t rx_ndp_copy_c : 1, + reserved_3 : 2, + tail_copy_c : 6, + vhtb_reserved_copy_c : 2, + length_copy_c : 21; +#endif +}; + +#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm2sw_completion_ring_rx.h b/drivers/staging/fw-api/hw/peach/v1/wbm2sw_completion_ring_rx.h new file mode 100644 index 0000000000000000000000000000000000000000..f88a753bfbd2bf6140ce9b0de1eb1dbf6ff3fe81 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/wbm2sw_completion_ring_rx.h @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM2SW_COMPLETION_RING_RX_H_ +#define _WBM2SW_COMPLETION_RING_RX_H_ + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 + +struct wbm2sw_completion_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + return_buffer_manager : 4, + reserved_2a : 2, + cache_id : 1, + cookie_conversion_status : 1, + rxdma_push_reason : 2, + rxdma_error_code : 5, + reo_push_reason : 2, + reo_error_code : 5, + wbm_internal_error : 1; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; + uint32_t buffer_phys_addr_39_32 : 8, + sw_buffer_cookie : 20, + looping_count : 4; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t wbm_internal_error : 1, + reo_error_code : 5, + reo_push_reason : 2, + rxdma_error_code : 5, + rxdma_push_reason : 2, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 2, + return_buffer_manager : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; + uint32_t looping_count : 4, + sw_buffer_cookie : 20, + buffer_phys_addr_39_32 : 8; +#endif +}; + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 + +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 + +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff + +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 + +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm2sw_completion_ring_tx.h b/drivers/staging/fw-api/hw/peach/v1/wbm2sw_completion_ring_tx.h new file mode 100644 index 0000000000000000000000000000000000000000..713cd8f04669f8d9caef456ca3210fec84cf256e --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/wbm2sw_completion_ring_tx.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM2SW_COMPLETION_RING_TX_H_ +#define _WBM2SW_COMPLETION_RING_TX_H_ + +#include "tx_rate_stats_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8 + +struct wbm2sw_completion_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t release_source_module : 3, + cache_id : 1, + reserved_2a : 2, + buffer_or_desc_type : 3, + return_buffer_manager : 4, + tqm_release_reason : 4, + rbm_override_valid : 1, + sw_buffer_cookie_11_0 : 12, + cookie_conversion_status : 1, + wbm_internal_error : 1; + uint32_t tqm_status_number : 24, + transmit_count : 7, + sw_release_details_valid : 1; + uint32_t ack_frame_rssi : 8, + first_msdu : 1, + last_msdu : 1, + fw_tx_notify_frame : 3, + buffer_timestamp : 19; + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, + tid : 4, + sw_buffer_cookie_19_12 : 8, + looping_count : 4; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t wbm_internal_error : 1, + cookie_conversion_status : 1, + sw_buffer_cookie_11_0 : 12, + rbm_override_valid : 1, + tqm_release_reason : 4, + return_buffer_manager : 4, + buffer_or_desc_type : 3, + reserved_2a : 2, + cache_id : 1, + release_source_module : 3; + uint32_t sw_release_details_valid : 1, + transmit_count : 7, + tqm_status_number : 24; + uint32_t buffer_timestamp : 19, + fw_tx_notify_frame : 3, + last_msdu : 1, + first_msdu : 1, + ack_frame_rssi : 8; + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, + sw_buffer_cookie_19_12 : 8, + tid : 4, + sw_peer_id : 16; +#endif +}; + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008 + +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030 + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 + +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100 + +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200 + +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff + +#define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_TID_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TID_MSB 19 +#define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000 + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 + +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/peach/v1/wbm_buffer_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..eb472a7841e2ce1fdc6748420a04e7abcd18c7ca --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/wbm_buffer_ring.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_BUFFER_RING_H_ +#define _WBM_BUFFER_RING_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 + +struct wbm_buffer_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; +#else + struct buffer_addr_info buf_addr_info; +#endif +}; + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/peach/v1/wbm_link_descriptor_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..96e225e81c7fb547bfabc8ab1a3070d1c1924ccf --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/wbm_link_descriptor_ring.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ +#define _WBM_LINK_DESCRIPTOR_RING_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 + +struct wbm_link_descriptor_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info desc_addr_info; +#else + struct buffer_addr_info desc_addr_info; +#endif +}; + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring.h b/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..06978a0b66d8d485975a3bbe7e71bc4957982bbf --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_RELEASE_RING_H_ +#define _WBM_RELEASE_RING_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 + +struct wbm_release_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + reserved_2a : 3, + buffer_or_desc_type : 3, + reserved_2b : 22, + wbm_internal_error : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 28, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + reserved_2b : 22, + buffer_or_desc_type : 3, + reserved_2a : 3, + release_source_module : 3; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + reserved_7a : 28; +#endif +}; + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2A_LSB 3 +#define WBM_RELEASE_RING_RESERVED_2A_MSB 5 +#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 + +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2B_LSB 9 +#define WBM_RELEASE_RING_RESERVED_2B_MSB 30 +#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 + +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RESERVED_3A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_3A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RESERVED_4A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_4A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RESERVED_5A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_5A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_7A_MSB 27 +#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff + +#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring_rx.h b/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring_rx.h new file mode 100644 index 0000000000000000000000000000000000000000..dd3c0d39f317ae162010c0bbef7bbcb43b9a5f3a --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring_rx.h @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_RELEASE_RING_RX_H_ +#define _WBM_RELEASE_RING_RX_H_ + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8 + +struct wbm_release_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + first_msdu_index : 4, + reserved_2a : 2, + cache_id : 1, + cookie_conversion_status : 1, + rxdma_push_reason : 2, + rxdma_error_code : 5, + reo_push_reason : 2, + reo_error_code : 5, + wbm_internal_error : 1; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + reo_error_code : 5, + reo_push_reason : 2, + rxdma_error_code : 5, + rxdma_push_reason : 2, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 2, + first_msdu_index : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_RX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_RX_BM_ACTION_MASK 0x00000038 + +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK 0x00001e00 + +#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 13 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 14 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x00006000 + +#define WBM_RELEASE_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_CACHE_ID_LSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MASK 0x00008000 + +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RX_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MSB 19 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MASK 0x000fffff + +#define WBM_RELEASE_RING_RX_RING_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RING_ID_LSB 20 +#define WBM_RELEASE_RING_RX_RING_ID_MSB 27 +#define WBM_RELEASE_RING_RX_RING_ID_MASK 0x0ff00000 + +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring_tx.h b/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring_tx.h new file mode 100644 index 0000000000000000000000000000000000000000..283568ff81a8c3fdc1ae9aee0e8a427b514b1a96 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring_tx.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_RELEASE_RING_TX_H_ +#define _WBM_RELEASE_RING_TX_H_ + +#include "tx_rate_stats_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8 + +struct wbm_release_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + first_msdu_index : 4, + tqm_release_reason : 4, + rbm_override_valid : 1, + rbm_override : 4, + reserved_2a : 7, + cache_id : 1, + cookie_conversion_status : 1, + wbm_internal_error : 1; + uint32_t tqm_status_number : 24, + transmit_count : 7, + sw_release_details_valid : 1; + uint32_t ack_frame_rssi : 8, + first_msdu : 1, + last_msdu : 1, + fw_tx_notify_frame : 3, + buffer_timestamp : 19; + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, + tid : 4, + tqm_status_number_31_24 : 8, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 7, + rbm_override : 4, + rbm_override_valid : 1, + tqm_release_reason : 4, + first_msdu_index : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + uint32_t sw_release_details_valid : 1, + transmit_count : 7, + tqm_status_number : 24; + uint32_t buffer_timestamp : 19, + fw_tx_notify_frame : 3, + last_msdu : 1, + first_msdu : 1, + ack_frame_rssi : 8; + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, + tqm_status_number_31_24 : 8, + tid : 4, + sw_peer_id : 16; +#endif +}; + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_TX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_TX_BM_ACTION_MASK 0x00000038 + +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK 0x00001e00 + +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB 18 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB 21 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK 0x003c0000 + +#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 22 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 28 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0x1fc00000 + +#define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_CACHE_ID_LSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MASK 0x20000000 + +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK 0x00000100 + +#define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_LAST_MSDU_LSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MASK 0x00000200 + +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB 0 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB 15 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK 0x0000ffff + +#define WBM_RELEASE_RING_TX_TID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TID_LSB 16 +#define WBM_RELEASE_RING_TX_TID_MSB 19 +#define WBM_RELEASE_RING_TX_TID_MASK 0x000f0000 + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB 20 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB 27 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK 0x0ff00000 + +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/peach/v1/wcss_seq_hwiobase.h new file mode 100644 index 0000000000000000000000000000000000000000..12ae566501284dd2232f2c607af0c090216083a5 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/wcss_seq_hwiobase.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __WCSS_SEQ_HWIOBASE_H__ +#define __WCSS_SEQ_HWIOBASE_H__ + +#define WCSS_CFGBUS_BASE 0x00008000 +#define WCSS_CFGBUS_BASE_SIZE 0x00008000 +#define WCSS_CFGBUS_BASE_PHYS 0x00008000 + +#define UMAC_NOC_BASE 0x00140000 +#define UMAC_NOC_BASE_SIZE 0x00004400 +#define UMAC_NOC_BASE_PHYS 0x00140000 + +#define PHYA0_BASE 0x00300000 +#define PHYA0_BASE_SIZE 0x00300000 +#define PHYA0_BASE_PHYS 0x00300000 + +#define PHYA1_BASE 0x00600000 +#define PHYA1_BASE_SIZE 0x00300000 +#define PHYA1_BASE_PHYS 0x00600000 + +#define DMAC_BASE 0x00900000 +#define DMAC_BASE_SIZE 0x00080000 +#define DMAC_BASE_PHYS 0x00900000 + +#define UMAC_BASE 0x00a00000 +#define UMAC_BASE_SIZE 0x0004d000 +#define UMAC_BASE_PHYS 0x00a00000 + +#define PMAC0_BASE 0x00a80000 +#define PMAC0_BASE_SIZE 0x00040000 +#define PMAC0_BASE_PHYS 0x00a80000 + +#define PMAC1_BASE 0x00ac0000 +#define PMAC1_BASE_SIZE 0x00040000 +#define PMAC1_BASE_PHYS 0x00ac0000 + +#define WFSS_AMCSS_BASE 0x00b00000 +#define WFSS_AMCSS_BASE_SIZE 0x00040000 +#define WFSS_AMCSS_BASE_PHYS 0x00b00000 + +#define CXC_BASE 0x00b40000 +#define CXC_BASE_SIZE 0x00010000 +#define CXC_BASE_PHYS 0x00b40000 + +#define WFSS_PMM_BASE 0x00b50000 +#define WFSS_PMM_BASE_SIZE 0x00002401 +#define WFSS_PMM_BASE_PHYS 0x00b50000 + +#define WFSS_CC_BASE 0x00b60000 +#define WFSS_CC_BASE_SIZE 0x00008000 +#define WFSS_CC_BASE_PHYS 0x00b60000 + +#define WCMN_CORE_BASE 0x00b68000 +#define WCMN_CORE_BASE_SIZE 0x000008a9 +#define WCMN_CORE_BASE_PHYS 0x00b68000 + +#define WIFI_CFGBUS_APB_TSLV_BASE 0x00b6b000 +#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000 + +#define WFSS_CFGBUS_BASE 0x00b6c000 +#define WFSS_CFGBUS_BASE_SIZE 0x000000a0 +#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000 + +#define WIFI_CFGBUS_AHB_TSLV_BASE 0x00b6d000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000 + +#define UMAC_ACMT_BASE 0x00b6e000 +#define UMAC_ACMT_BASE_SIZE 0x00001000 +#define UMAC_ACMT_BASE_PHYS 0x00b6e000 + +#define WCSS_CC_BASE 0x00b80000 +#define WCSS_CC_BASE_SIZE 0x00010000 +#define WCSS_CC_BASE_PHYS 0x00b80000 + +#define PMM_TOP_BASE 0x00b90000 +#define PMM_TOP_BASE_SIZE 0x00010000 +#define PMM_TOP_BASE_PHYS 0x00b90000 + +#define WCSS_TOP_CMN_BASE 0x00ba0000 +#define WCSS_TOP_CMN_BASE_SIZE 0x00004000 +#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000 + +#define MSIP_BASE 0x00bb0000 +#define MSIP_BASE_SIZE 0x00010000 +#define MSIP_BASE_PHYS 0x00bb0000 + +#define DBG_BASE 0x01000000 +#define DBG_BASE_SIZE 0x00100000 +#define DBG_BASE_PHYS 0x01000000 + +#define Q6SS_WLAN_BASE 0x01100000 +#define Q6SS_WLAN_BASE_SIZE 0x00100000 +#define Q6SS_WLAN_BASE_PHYS 0x01100000 + +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/peach/v1/wcss_seq_hwioreg_umac.h new file mode 100644 index 0000000000000000000000000000000000000000..70f00a5642055bef59e1bf288c831c6bfe349287 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/wcss_seq_hwioreg_umac.h @@ -0,0 +1,2269 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __WCSS_SEQ_HWIOREG_UMAC_H__ +#define __WCSS_SEQ_HWIOREG_UMAC_H__ + +#include "seq_hwio.h" +#include "wcss_seq_hwiobase.h" +#ifdef SCALE_INCLUDES +#include "HALhwio.h" +#else +#include "msmhwio.h" +#endif + +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x) ((x) + 0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x) ((x) + 0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS (0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK 0x7 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK 0x7 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x) ((x) + 0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x) ((x) + 0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS (0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR 0x00001ffe +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK 0x1ffe000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT 13 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK 0x1ffe +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT 1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK 0x1000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT 12 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK 0x800 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT 11 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK 0x400 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT 10 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK 0x200 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT 9 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x) ((x) + 0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x) ((x) + 0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS (0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK 0xff000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT 24 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK 0xff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK 0xff00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK 0xff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n) ((base) + 0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n) ((base) + 0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n) (0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK 0xfff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn 3 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK 0xfff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x) ((x) + 0x1c4) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x) ((x) + 0x1c4) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS (0x1c4) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK 0x3 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK 0x2 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT 1 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT 0 + +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n) (0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn 63 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x40) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x44) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x7c) +#define HWIO_WBM_R0_WBM_CFG_2_ADDR(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_PHYS(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_OFFS (0x90) +#define HWIO_WBM_R0_WBM_CFG_2_RMSK 0x4b +#define HWIO_WBM_R0_WBM_CFG_2_POR 0x00000040 +#define HWIO_WBM_R0_WBM_CFG_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_CFG_2_ATTR 0x3 +#define HWIO_WBM_R0_WBM_CFG_2_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x)) +#define HWIO_WBM_R0_WBM_CFG_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_CFG_2_ADDR(x), m) +#define HWIO_WBM_R0_WBM_CFG_2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),v) +#define HWIO_WBM_R0_WBM_CFG_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),m,v,HWIO_WBM_R0_WBM_CFG_2_IN(x)) +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK 0x40 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_SHFT 6 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_BMSK 0x8 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_SHFT 3 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_SHFT 1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0 + +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x94) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_SHFT 7 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_SHFT 6 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_SHFT 5 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_SHFT 4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_SHFT 3 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_SHFT 2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_SHFT 1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x240) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x244) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x250) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x254) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x260) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x264) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x270) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x274) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x27c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x37c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xd3c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0xd4c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe08) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe80) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x1408) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x1408) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x1408) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x140c) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x140c) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x140c) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x1410) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x1410) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x1410) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x1414) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x1414) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x1414) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1418) +#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1418) +#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS (0x1418) +#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK 0x20 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT 5 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK 0x10 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT 4 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x) ((x) + 0x141c) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x) ((x) + 0x141c) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS (0x141c) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x)) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x)) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK 0xffe00000 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT 21 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK 0x1f0000 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT 16 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK 0xf800 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT 11 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK 0x7c0 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT 6 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT 0 + +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2030) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2030) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2030) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x3ff +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK 0x200 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT 9 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK 0x100 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT 8 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2034 + (0x4*(n))) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2034 + (0x4*(n))) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2034 + (0x4*(n))) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn 255 +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x30b8) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x30c8) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x30d0) +#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) +#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x8 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 3 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x4 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 2 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x) ((x) + 0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x) ((x) + 0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS (0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR 0x76543210 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x) ((x) + 0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x) ((x) + 0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS (0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x66666a98 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x) ((x) + 0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x) ((x) + 0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS (0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x) ((x) + 0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x) ((x) + 0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS (0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x38) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x3c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x) ((x) + 0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x) ((x) + 0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS (0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x) ((x) + 0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x) ((x) + 0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS (0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT 0 + +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x) ((x) + 0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x) ((x) + 0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS (0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK 0x1ffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR 0x00000000 +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR 0x3 +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x) \ + in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v) \ + out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK 0x1ffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT 0 + +#define HWIO_REO_R0_PN_IN_DEST_ADDR(x) ((x) + 0x68) +#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x6c) +#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x70) +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) ((x) + 0x2a8) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x320) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_SW2REO1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x500) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x504) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x508) +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x510) +#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x514) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x518) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x524) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x548) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x54c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x550) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x574) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x554) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x558) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x55c) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x560) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x578) +#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0x8c0) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0xaa0) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_MISC_CFG_ADDR(x) ((x) + 0xb24) +#define HWIO_REO_R0_MISC_CFG_PHYS(x) ((x) + 0xb24) +#define HWIO_REO_R0_MISC_CFG_OFFS (0xb24) +#define HWIO_REO_R0_MISC_CFG_RMSK 0x1 +#define HWIO_REO_R0_MISC_CFG_POR 0x00000000 +#define HWIO_REO_R0_MISC_CFG_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MISC_CFG_ATTR 0x3 +#define HWIO_REO_R0_MISC_CFG_IN(x) \ + in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x)) +#define HWIO_REO_R0_MISC_CFG_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m) +#define HWIO_REO_R0_MISC_CFG_OUT(x, v) \ + out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v) +#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x)) +#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK 0x1 +#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT 0 + +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x) ((x) + 0xb28) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x) ((x) + 0xb28) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS (0xb28) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK 0x1ff +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR 0x0000002d +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR 0x3 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x) \ + in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v) \ + out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK 0x1fe +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT 1 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK 0x1 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0xb2c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0xb30) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0xb34) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0xb38) +#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0xba0) +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xd78) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xd78) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xd78) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd7c) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd7c) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xd7c) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xd80) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xd80) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xd80) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd84) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd84) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xd84) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_REO_R0_CREDIT_ADDR(x) ((x) + 0xd88) +#define HWIO_REO_R0_CREDIT_PHYS(x) ((x) + 0xd88) +#define HWIO_REO_R0_CREDIT_OFFS (0xd88) +#define HWIO_REO_R0_CREDIT_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_POR 0x00000000 +#define HWIO_REO_R0_CREDIT_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_ATTR 0x3 +#define HWIO_REO_R0_CREDIT_IN(x) \ + in_dword(HWIO_REO_R0_CREDIT_ADDR(x)) +#define HWIO_REO_R0_CREDIT_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m) +#define HWIO_REO_R0_CREDIT_OUT(x, v) \ + out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v) +#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x)) +#define HWIO_REO_R0_CREDIT_VAL_BMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_VAL_SHFT 0 + +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x) ((x) + 0xd8c) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x) ((x) + 0xd8c) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS (0xd8c) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK 0x7 +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR 0x00000002 +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR 0x3 +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x) \ + in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x)) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v) \ + out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x)) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK 0x7 +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT 0 + +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x) ((x) + 0xd90) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x) ((x) + 0xd90) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS (0xd90) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR 0x00000000 +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR 0x1 +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x)) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT 0 + +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK 0x2000 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT 13 +#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0xdbc) +#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0xdbc) +#define HWIO_REO_R0_LPM_FW_CTRL_OFFS (0xdbc) +#define HWIO_REO_R0_LPM_FW_CTRL_RMSK 0x7 +#define HWIO_REO_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_REO_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x205c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x205c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x205c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2060) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2060) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2060) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x2064) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x2064) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x2064) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0 + +#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x) ((x) + 0x20c0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x) ((x) + 0x20c0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS (0x20c0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK 0x3f +#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR 0x00000000 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR 0x1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x) \ + in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK 0x20 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT 5 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK 0x10 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT 4 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK 0x8 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT 3 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK 0x4 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT 2 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK 0x2 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT 1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK 0x1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT 0 + +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x) ((x) + 0x20c4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x) ((x) + 0x20c4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS (0x20c4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR 0x00000000 +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR 0x3 +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x) \ + in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v) \ + out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT 0 + +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x20cc) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x20cc) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x20cc) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X20D0 + (0x4*(n))) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X20D0 + (0x4*(n))) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X20D0 + (0x4*(n))) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn 255 +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) ((x) + 0x3020) +#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028) +#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3048) +#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x304c) +#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3050) +#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x3088) +#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) ((x) + 0x30a8) +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK 0x80 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT 7 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK 0x40 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT 6 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK 0x20 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT 5 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK 0x10 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT 4 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK 0x8 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT 3 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x3f4) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x3f4) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x3f4) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x3f8) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x3f8) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x3f8) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x3fc) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x3fc) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x3fc) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x400) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x400) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x400) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK 0x80000000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT 31 +#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK 0x8000 +#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT 15 +#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK 0x4000 +#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT 14 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK 0x2000 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT 13 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK 0x1000 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT 12 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK 0x800 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT 11 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK 0x400 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT 10 +#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x480) +#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x480) +#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS (0x480) +#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK 0xf +#define HWIO_TQM_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x) ((x) + 0x484) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x) ((x) + 0x484) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS (0x484) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK 0x3 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR 0x00000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR 0x3 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x) \ + in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x)) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x)) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK 0x2 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT 1 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK 0x1 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT 0 + +#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK 0x20000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT 29 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x) ((x) + 0x508) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x) ((x) + 0x508) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS (0x508) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x) ((x) + 0x50c) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x) ((x) + 0x50c) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS (0x50c) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x) ((x) + 0x510) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x) ((x) + 0x510) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS (0x510) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT 0 + +#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x) ((x) + 0x51c) +#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x) ((x) + 0x51c) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS (0x51c) +#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK 0xfff +#define HWIO_TQM_R0_WATCHDOG_SRNG_POR 0x00000710 +#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR 0x3 +#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x) \ + in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)) +#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)) +#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK 0xfff +#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x2054) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x2054) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x2054) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2058) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2058) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2058) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x205c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x205c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x205c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0 + +#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x) ((x) + 0x2060) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x) ((x) + 0x2060) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS (0x2060) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK 0x1ffff +#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR 0x00000000 +#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR 0x3 +#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x) \ + in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x)) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v) \ + out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x)) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff +#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 + +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x) ((x) + 0x2064) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x) ((x) + 0x2064) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS (0x2064) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK 0x1ffff +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR 0x00000000 +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR 0x3 +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x) \ + in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x)) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v) \ + out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x)) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT 0 + +#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x) ((x) + 0x2068) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x) ((x) + 0x2068) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS (0x2068) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK 0x1ffff +#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR 0x00000000 +#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR 0x3 +#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x) \ + in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x)) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v) \ + out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x)) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff +#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 + +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x) ((x) + 0x206c) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x) ((x) + 0x206c) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS (0x206c) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK 0xf +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x)) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK 0x8 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT 3 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK 0x4 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT 2 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK 0x2 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT 1 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK 0x1 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT 0 + +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x) ((x) + 0x2070) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x) ((x) + 0x2070) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS (0x2070) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR 0x00000000 +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR 0x1 +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x) \ + in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x)) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT 0 + +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x) ((x) + 0x2074) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x) ((x) + 0x2074) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS (0x2074) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR 0x00000000 +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR 0x1 +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x) \ + in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x)) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT 0 + +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2078) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2078) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2078) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0xff +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2114 + (0x4*(n))) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2114 + (0x4*(n))) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2114 + (0x4*(n))) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn 127 +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK 0x80 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 22 +#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 +#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 22 +#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 +#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK 0x40 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT 6 +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x) ((x) + 0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x) ((x) + 0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS (0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK 0xf +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR 0x0000000a +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR 0x3 +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x) \ + in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK 0xf +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x16c) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x16c) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS (0x16c) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK 0x1f +#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK 0x10 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT 4 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK 0x8 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT 3 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK 0x4 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT 2 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK 0x2 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT 1 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_UMCMN_R0_LINK_ID_ADDR(x) ((x) + 0x170) +#define HWIO_UMCMN_R0_LINK_ID_PHYS(x) ((x) + 0x170) +#define HWIO_UMCMN_R0_LINK_ID_OFFS (0x170) +#define HWIO_UMCMN_R0_LINK_ID_RMSK 0xffff +#define HWIO_UMCMN_R0_LINK_ID_POR 0x000052c8 +#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_LINK_ID_ATTR 0x3 +#define HWIO_UMCMN_R0_LINK_ID_IN(x) \ + in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x)) +#define HWIO_UMCMN_R0_LINK_ID_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m) +#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v) +#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x)) +#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK 0x80 +#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT 7 +#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK 0x40 +#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT 6 +#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK 0x38 +#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT 3 +#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK 0x7 +#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT 0 + +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK 0x4000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT 14 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK 0x2000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT 13 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK 0x1000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT 12 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK 0x800 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT 11 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK 0x400 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT 10 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK 0x200 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT 9 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK 0x100 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT 8 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK 0x80 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT 7 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK 0x40 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT 6 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK 0x20 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT 5 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK 0x10 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT 4 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK 0x8 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT 3 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK 0x4 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT 2 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK 0x2 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT 1 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK 0x1 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT 0 + +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x) ((x) + 0x184) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x) ((x) + 0x184) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS (0x184) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK 0x1 +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR 0x00000000 +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR 0x3 +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x) \ + in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x)) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x)) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK 0x1 +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT 0 + +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x) ((x) + 0x188) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x) ((x) + 0x188) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS (0x188) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK 0x1ffff +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR 0x00000000 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR 0x3 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x) \ + in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x)) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x)) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK 0x1fe00 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT 9 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK 0x1fe +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT 1 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK 0x1 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT 0 + +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2010) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2010) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2010) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x1ff +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK 0x100 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT 8 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK 0x80 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT 7 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK 0x40 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT 6 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK 0x20 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT 5 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n) ((base) + 0X2014 + (0x4*(n))) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n) ((base) + 0X2014 + (0x4*(n))) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n) (0X2014 + (0x4*(n))) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK 0xffffffff +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn 7 +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR 0x00000000 +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR 0x3 +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n) \ + in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val) \ + out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n)) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK 0xffffffff +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT 0 + +#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 +#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK 0x8000000 +#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT 27 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X8C + (0x4*(n))) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT 15 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT 11 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT 10 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT 9 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 + +#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X240 + (0x4*(n))) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff +#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) ((x) + 0x6c0) +#define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0xffffff +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 21 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 18 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 15 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 12 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 9 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 6 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 3 +#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) ((x) + 0x6e8) +#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0xef +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK 0x800000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT 23 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK 0x10 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT 4 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK 0x8 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT 3 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x) ((x) + 0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x) ((x) + 0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS (0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK 0x3 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR 0x00000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR 0x3 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x) \ + in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK 0x2 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT 1 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK 0x1 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT 0 + +#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x914) +#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x914) +#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS (0x914) +#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK 0x7 +#define HWIO_TCL_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x918) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x91c) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x920) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x928) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x934) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x938) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x948) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x94c) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x960) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x964) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x968) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x990) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) ((x) + 0xb70) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) ((x) + 0xd50) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xedc) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xedc) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xedc) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xee0) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xee0) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xee0) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xee4) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xee4) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xee4) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xee8) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xee8) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xee8) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x1000) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x1000) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x1000) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x20000 +#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 17 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x20000 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 17 +#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x1030) +#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x1030) +#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS (0x1030) +#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK 0x1ff +#define HWIO_TCL_R1_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x) \ + in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)) +#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x100 +#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 8 +#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK 0xc0 +#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT 6 +#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK 0x3f +#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT 0 + +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X1034 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X1034 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X1034 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn 511 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x) ((x) + 0x2028) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) ((x) + 0x2048) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_NOPX_BMSK 0x80000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_NOPX_SHFT 19 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWSLVERR_BMSK 0x40000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWSLVERR_SHFT 18 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWDECERR_BMSK 0x20000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWDECERR_SHFT 17 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#endif diff --git a/drivers/staging/fw-api/hw/peach/v1/wcss_version.h b/drivers/staging/fw-api/hw/peach/v1/wcss_version.h new file mode 100644 index 0000000000000000000000000000000000000000..a07cff096e51347421c86b8cbc1ad7ee2b65d897 --- /dev/null +++ b/drivers/staging/fw-api/hw/peach/v1/wcss_version.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#define WCSS_VERSION 2544 diff --git a/drivers/staging/fw-api/hw/qca5332/mon_buffer_addr.h b/drivers/staging/fw-api/hw/qca5332/mon_buffer_addr.h index 8bd6d621e9854396280239fcf074b47908d399bf..95225bed09c1c977bdd84101e28c4a2dbd3164b7 100644 --- a/drivers/staging/fw-api/hw/qca5332/mon_buffer_addr.h +++ b/drivers/staging/fw-api/hw/qca5332/mon_buffer_addr.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -34,7 +34,7 @@ struct mon_buffer_addr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t buffer_virt_addr_31_0 : 32; // [31:0] uint32_t buffer_virt_addr_63_32 : 32; // [31:0] uint32_t dma_length : 12, // [11:0] diff --git a/drivers/staging/fw-api/hw/qca5332/mon_destination_ring.h b/drivers/staging/fw-api/hw/qca5332/mon_destination_ring.h index 385c2eda04f7002009411ac0077808b6653e5f9c..c16810423d633a12851312cf737f97a1cc171a64 100644 --- a/drivers/staging/fw-api/hw/qca5332/mon_destination_ring.h +++ b/drivers/staging/fw-api/hw/qca5332/mon_destination_ring.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -32,7 +32,7 @@ struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t stat_buf_virt_addr_31_0 : 32; // [31:0] uint32_t stat_buf_virt_addr_63_32 : 32; // [31:0] uint32_t ppdu_id : 32; // [31:0] diff --git a/drivers/staging/fw-api/hw/qcn6432/HALcomdef.h b/drivers/staging/fw-api/hw/qcn6432/HALcomdef.h new file mode 100644 index 0000000000000000000000000000000000000000..8a984985292ec070ba735a4868fee1d37e5a8721 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/HALcomdef.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_COMDEF_H +#define HAL_COMDEF_H + +/* + * Assembly wrapper + */ +#ifndef _ARM_ASM_ + +/* + * C++ wrapper + */ +#ifdef __cplusplus +extern "C" { +#endif + +#include "com_dtypes.h" + +/* ----------------------------------------------------------------------- +** Types +** ----------------------------------------------------------------------- */ + +/* + * Standard integer types. + * + * bool32 - boolean, 32 bit (TRUE or FALSE) + */ +#ifndef _BOOL32_DEFINED +typedef unsigned long int bool32; +#define _BOOL32_DEFINED +#endif + +/* + * Macro to allow forcing an enum to 32 bits. The argument should be + * an identifier in the namespace of the enumeration in question, i.e. + * for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx). + */ +#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF + +/*=========================================================================== + +FUNCTION inp, outp, inpw, outpw, inpdw, outpdw + +DESCRIPTION + IN/OUT port macros for byte and word ports, typically inlined by compilers + which support these routines + +PARAMETERS + inp( xx_addr ) + inpw( xx_addr ) + inpdw( xx_addr ) + outp( xx_addr, xx_byte_val ) + outpw( xx_addr, xx_word_val ) + outpdw( xx_addr, xx_dword_val ) + xx_addr - Address of port to read or write (may be memory mapped) + xx_byte_val - 8 bit value to write + xx_word_val - 16 bit value to write + xx_dword_val - 32 bit value to write + +DEPENDENCIES + None + +RETURN VALUE + inp/inpw/inpdw: the byte, word or dword read from the given address + outp/outpw/outpdw: the byte, word or dword written to the given address + +SIDE EFFECTS + None. + +===========================================================================*/ + + /* ARM based targets use memory mapped i/o, so the inp/outp calls are + ** macroized to access memory directly + */ + + #define inp(port) (*((volatile byte *) (port))) + #define inpw(port) (*((volatile word *) (port))) + #define inpdw(port) (*((volatile dword *)(port))) + + #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) + #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) + #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) + +#ifdef __cplusplus +} +#endif + +#endif /* !_ARM_ASM_ */ + +#endif /* HAL_COMDEF_H */ + diff --git a/drivers/staging/fw-api/hw/qcn6432/HALhwio.h b/drivers/staging/fw-api/hw/qcn6432/HALhwio.h new file mode 100644 index 0000000000000000000000000000000000000000..3ccc644f9f42c2bb1ece09ca69c836ddfa6be491 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/HALhwio.h @@ -0,0 +1,488 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef HAL_HWIO_H +#define HAL_HWIO_H + +/* + * Common types. + */ +#include "HALcomdef.h" + + + +/* ----------------------------------------------------------------------- +** Macros +** ----------------------------------------------------------------------- */ + +/** + @addtogroup macros + @{ +*/ + +/** + * Map a base name to the pointer to access the base. + * + * This macro maps a base name to the pointer to access the base. + * This is generally just used internally. + * + */ +#define HWIO_BASE_PTR(base) base##_BASE_PTR + + +/** + * Declare a HWIO base pointer. + * + * This macro will declare a HWIO base pointer data structure. The pointer + * will always be declared as a weak symbol so multiple declarations will + * resolve correctly to the same data at link-time. + */ +#ifdef __ARMCC_VERSION + #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) +#else + #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) +#endif + +/** + @} +*/ + +#ifdef CONFIG_WHAL_MM +#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET +#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET +#endif + + +/** + @addtogroup hwio_macros + @{ +*/ + +/** + * @name Address Macros + * + * Macros for getting register addresses. + * These macros are used for retrieving the address of a register. + * HWIO_ADDR* will return the directly accessible address (virtual or physical based + * on environment), HWIO_PHYS* will always return the physical address. + * The offset from the base region can be retrieved using HWIO_OFFS*. + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * + * @{ + */ +#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) +#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) +#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) +#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) + +#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) +#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) +#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) +#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) +#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) +#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) +#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) + +#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) +#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) +#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) +#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) +#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) +#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) +#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) +/** @} */ + +/** + * @name Input Macros + * + * These macros are used for reading from a named hardware register. Register + * arrays ("indexed") use the macros with the "I" suffix. The "M" suffix + * indicates that the input will be masked with the supplied mask. The HWIO_INF* + * macros take a field name and will do the appropriate masking and shifting + * to return just the value of that field. + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * + * Generally you want to use either HWIO_IN or HWIO_INF (with required indexing). + * + * @{ + */ +#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) +#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) +#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) +#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) + +#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) +#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) +#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) +#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) + +#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) +#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) +#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) +#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) +#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) +#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) +#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) + +#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +/** @} */ + +/** + * @name Output Macros + * + * These macros are used for writing to a named hardware register. Register + * arrays ("indexed") use the macros with the "I" suffix. The "M" suffix + * indicates that the output will be masked with the supplied mask (meaning these + * macros do a read first, mask in the supplied data, then write it back). + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * The HWIO_OUTF* macros take a field name and will do the appropriate masking + * and shifting to output just the value of that field. + * HWIO_OUTV* registers take a named value instead of a numeric value and + * do the same masking/shifting as HWIO_OUTF. + * + * Generally you want to use either HWIO_OUT or HWIO_OUTF (with required indexing). + * + * @{ + */ +#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) +#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) +#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) +#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) + +#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) +#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) +#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) +#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) +#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) +#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) +#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) + +#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) +#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) +#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) +#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) +#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) +#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) +#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) + +#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +/** @} */ + +/** + * @name Shift and Mask Macros + * + * Macros for getting shift and mask values for fields and registers. + * HWIO_RMSK: The mask value for accessing an entire register. For example: + * @code + * HWIO_RMSK(REG) -> 0xFFFFFFFF + * @endcode + * HWIO_RSHFT: The right-shift value for an entire register (rarely necessary).\n + * HWIO_SHFT: The right-shift value for accessing a field in a register. For example: + * @code + * HWIO_SHFT(REG, FLD) -> 8 + * @endcode + * HWIO_FMSK: The mask value for accessing a field in a register. For example: + * @code + * HWIO_FMSK(REG, FLD) -> 0xFF00 + * @endcode + * HWIO_VAL: The value for a field in a register. For example: + * @code + * HWIO_VAL(REG, FLD, ON) -> 0x1 + * @endcode + * HWIO_FVAL: This macro takes a numerical value and will shift and mask it into + * the given field position. For example: + * @code + * HWIO_FVAL(REG, FLD, 0x1) -> 0x100 + * @endcode + * HWIO_FVALV: This macro takes a logical (named) value and will shift and mask it + * into the given field position. For example: + * @code + * HWIO_FVALV(REG, FLD, ON) -> 0x100 + * @endcode + * + * @{ + */ +#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) +#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) +#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) +#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) +#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) +#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) +#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +/** @} */ + +/** + * @name Shadow Register Macros + * + * These macros are used for directly reading the value stored in a + * shadow register. + * Shadow registers are defined for write-only registers. Generally these + * macros should not be necessary as HWIO_OUTM* macros will automatically use + * the shadow values internally. + * + * @{ + */ +#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) +#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) +/** @} */ + +/** + @} +*/ /* end_group */ + + +/** @cond */ + +/* + * Map to final symbols. This remapping is done to allow register + * redefinitions. If we just define HWIO_IN(xreg) as HWIO_##xreg##_IN + * then remappings like "#define xreg xregnew" do not work as expected. + */ +#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN +#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) +#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) +#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) +#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) +#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) +#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) +#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) +#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) +#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) +#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) +#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) +#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) +#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) +#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) +#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) +#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR +#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) +#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) +#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) +#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS +#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) +#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) +#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) +#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) +#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) +#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK +#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) +#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK +#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT +#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT +#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow +#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) +#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL + +#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) +#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) +#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) +#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) +#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) +#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) +#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) +#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) +#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) +#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) +#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) +#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) +#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) +#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + } +#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + } +#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + HWIO_##hwiosym##_OUTM(base, mask4, val4); \ + } + + +#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) +#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) +#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) +#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) +#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) +#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) +#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) +#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) +#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) +#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) +#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) + + +/* + * HWIO_INTLOCK + * + * Macro used by autogenerated code for mutual exclusion around + * read-mask-write operations. This is not supported in HAL + * code but can be overridden by non-HAL code. + */ +#define HWIO_INTLOCK() +#define HWIO_INTFREE() + + +/* + * Input/output port macros for memory mapped IO. + */ +#define __inp(port) (*((volatile uint8 *) (port))) +#define __inpw(port) (*((volatile uint16 *) (port))) +#define __inpdw(port) (*((volatile uint32 *) (port))) +#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) +#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) + + +#ifdef HAL_HWIO_EXTERNAL + +/* + * Replace macros with externally supplied functions. + */ +#undef __inp +#undef __inpw +#undef __inpdw +#undef __outp +#undef __outpw +#undef __outpdw + +#ifdef WCSS_IE_EN +extern uint32 registerRead(unsigned long addr); +extern void registerWrite(unsigned long addr, uint32 value); +#define __inp(port) registerRead(port) +#define __inpw(port) registerRead(port) +#define __inpdw(port) registerRead(port) +#define __outp(port, val) registerWrite(port, val) +#define __outpw(port, val) registerWrite(port, val) +#define __outpdw(port, val) registerWrite(port, val) +#else +#define __inp(port) __inp_extern((uint32) (port)) +#define __inpw(port) __inpw_extern((uint32) (port)) +#define __inpdw(port) __inpdw_extern((uint32) (port)) +#define __outp(port, val) __outp_extern((uint32) (port), val) +#define __outpw(port, val) __outpw_extern((uint32) (port), val) +#define __outpdw(port, val) __outpdw_extern((uint32) (port), val) + +extern uint8 __inp_extern ( uint32 nAddr ); +extern uint16 __inpw_extern ( uint32 nAddr ); +extern uint32 __inpdw_extern ( uint32 nAddr ); +extern void __outp_extern ( uint32 nAddr, uint8 nData ); +extern void __outpw_extern ( uint32 nAddr, uint16 nData ); +extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); +#endif + + +#endif /* HAL_HWIO_EXTERNAL */ + + +/* + * Base 8-bit byte accessing macros. + */ +#define in_byte(addr) (__inp(addr)) +#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) +#define out_byte(addr, val) __outp(addr,val) +#define out_byte_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + out_byte( io, shadow); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + HWIO_INTFREE() +#define out_byte_masked_ns(io, mask, val, current_reg_content) \ + out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + + +/* + * Base 16-bit word accessing macros. + */ +#define in_word(addr) (__inpw(addr)) +#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) +#define out_word(addr, val) __outpw(addr,val) +#define out_word_masked(io, mask, val, shadow) \ + HWIO_INTLOCK( ); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + out_word( io, shadow); \ + HWIO_INTFREE( ) +#define out_word_masked_ns(io, mask, val, current_reg_content) \ + out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + + +/* + * Base 32-bit double-word accessing macros. + */ +#define in_dword(addr) (__inpdw(addr)) +#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) +#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ + out_dword( io, shadow); \ + HWIO_INTFREE() +#define out_dword_masked_ns(io, mask, val, current_reg_content) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + ((uint32)((val) & (mask)))) ) + +/** @endcond */ + +#endif /* HAL_HWIO_H */ + diff --git a/drivers/staging/fw-api/hw/qcn6432/ack_report.h b/drivers/staging/fw-api/hw/qcn6432/ack_report.h new file mode 100644 index 0000000000000000000000000000000000000000..2226be2944c513ec6b284c8d23c888efde9b752b --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/ack_report.h @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _ACK_REPORT_H_ +#define _ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_ACK_REPORT 1 + + +struct ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t selfgen_response_reason : 4, // [3:0] + ax_trigger_type : 4, // [7:4] + sr_ppdu : 1, // [8:8] + reserved : 7, // [15:9] + frame_control : 16; // [31:16] +#else + uint32_t frame_control : 16, // [31:16] + reserved : 7, // [15:9] + sr_ppdu : 1, // [8:8] + ax_trigger_type : 4, // [7:4] + selfgen_response_reason : 4; // [3:0] +#endif +}; + + +/* Description SELFGEN_RESPONSE_REASON + + Field that indicates why the received frame needs a response + in SIFS time. The possible responses are listed in order. + + + + + + Qboost trigger received + PSPOLL trigger received + Unscheduled APSD trigger received + + the CBF frame needs to be send as + a result of NDP or BRPOLL + 11ax trigger received for this + device + 11ax wildcardtrigger has + been received + 11ax wildcard trigger + for unassociated STAs has been received + EHT R1 trigger received for + this device + + + + Ranging NDP + LMR need + to be sent in response to ranging NDPA + NDP + + +*/ + +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f + + +/* Description AX_TRIGGER_TYPE + + Field Only valid when selfgen_response_reason is an 11ax + related trigger + + The 11AX trigger type/ trigger number: + It identifies which trigger was received. + + + + + + + + + + + + + + + + + + +*/ + +#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 +#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 +#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 + + +/* Description SR_PPDU + + Field only valid with SRP Responder support + + Indicates if the received frame was sent using SRP as indicated + by the 'SR PPDU' bit in the 'CAS Control' in the 'HE A-Control' + in one of the MPDUs received + +*/ + +#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 +#define ACK_REPORT_SR_PPDU_LSB 8 +#define ACK_REPORT_SR_PPDU_MSB 8 +#define ACK_REPORT_SR_PPDU_MASK 0x00000100 + + +/* Description RESERVED + + +*/ + +#define ACK_REPORT_RESERVED_OFFSET 0x00000000 +#define ACK_REPORT_RESERVED_LSB 9 +#define ACK_REPORT_RESERVED_MSB 15 +#define ACK_REPORT_RESERVED_MASK 0x0000fe00 + + +/* Description FRAME_CONTROL + + Field not valid when selfgen_response_reason is MU_UL_response_to_response + + + For SU receptions: + frame control field of the received frame + + In 11ah Mode of Operation, for non-NDP frames the BW information + is extracted from Frame Control fields [11:8]. + + Decode is as follows + + Bits[11] - Dynamic/Static + Bits[10:8] - Channel BW +*/ + +#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define ACK_REPORT_FRAME_CONTROL_LSB 16 +#define ACK_REPORT_FRAME_CONTROL_MSB 31 +#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + + + +#endif // ACK_REPORT diff --git a/drivers/staging/fw-api/hw/qcn6432/buffer_addr_info.h b/drivers/staging/fw-api/hw/qcn6432/buffer_addr_info.h new file mode 100644 index 0000000000000000000000000000000000000000..de74fe3d6a4a5cd065ab604b1d649bf129de3c61 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/buffer_addr_info.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _BUFFER_ADDR_INFO_H_ +#define _BUFFER_ADDR_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 + + +struct buffer_addr_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_addr_31_0 : 32; // [31:0] + uint32_t buffer_addr_39_32 : 8, // [7:0] + return_buffer_manager : 4, // [11:8] + sw_buffer_cookie : 20; // [31:12] +#else + uint32_t buffer_addr_31_0 : 32; // [31:0] + uint32_t sw_buffer_cookie : 20, // [31:12] + return_buffer_manager : 4, // [11:8] + buffer_addr_39_32 : 8; // [7:0] +#endif +}; + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif // BUFFER_ADDR_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/ce_src_desc.h b/drivers/staging/fw-api/hw/qcn6432/ce_src_desc.h new file mode 100644 index 0000000000000000000000000000000000000000..b556ac88e08c1e8d9b548b30009cb66559d2d7f7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/ce_src_desc.h @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _CE_SRC_DESC_H_ +#define _CE_SRC_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_SRC_DESC 4 + + +struct ce_src_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_buffer_low : 32; // [31:0] + uint32_t src_buffer_high : 8, // [7:0] + toeplitz_en : 1, // [8:8] + src_swap : 1, // [9:9] + dest_swap : 1, // [10:10] + gather : 1, // [11:11] + ce_res_0 : 1, // [12:12] + barrier_read : 1, // [13:13] + ce_res_1 : 2, // [15:14] + length : 16; // [31:16] + uint32_t fw_metadata : 16, // [15:0] + ce_res_2 : 16; // [31:16] + uint32_t ce_res_3 : 20, // [19:0] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t src_buffer_low : 32; // [31:0] + uint32_t length : 16, // [31:16] + ce_res_1 : 2, // [15:14] + barrier_read : 1, // [13:13] + ce_res_0 : 1, // [12:12] + gather : 1, // [11:11] + dest_swap : 1, // [10:10] + src_swap : 1, // [9:9] + toeplitz_en : 1, // [8:8] + src_buffer_high : 8; // [7:0] + uint32_t ce_res_2 : 16, // [31:16] + fw_metadata : 16; // [15:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + ce_res_3 : 20; // [19:0] +#endif +}; + + +/* Description SRC_BUFFER_LOW + + LSB 32 bits of the 40 Bit Pointer to the source buffer + +*/ + +#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000 +#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff + + +/* Description SRC_BUFFER_HIGH + + Bits [6:0] for 40 Bit Pointer to the source buffer + Bit [7] can be programmed with VC bit. + Note: CE Descriptor has 40-bit address. Only 37 bits are + routed as address to NoC. Remaining bits are user bits. + Bit [7] of SRC_BUFFER_HIGH can be used for VC configuration. + 0 indicate VC0 and 1 indicate VC1. + +*/ + +#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff + + +/* Description TOEPLITZ_EN + + Enable generation of 32-bit Toeplitz-LFSR hash for the data + transfer + In case of gather field in first source ring entry of the + gather copy cycle in taken into account. + +*/ + +#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004 +#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100 + + +/* Description SRC_SWAP + + Treats source memory organization as big-endian. For each + dword read (4 bytes), the byte 0 is swapped with byte 3 + and byte 1 is swapped with byte 2. + In case of gather field in first source ring entry of the + gather copy cycle in taken into account. + +*/ + +#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_SWAP_LSB 9 +#define CE_SRC_DESC_SRC_SWAP_MSB 9 +#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200 + + +/* Description DEST_SWAP + + Treats destination memory organization as big-endian. For + each dword write (4 bytes), the byte 0 is swapped with + byte 3 and byte 1 is swapped with byte 2. + In case of gather field in first source ring entry of the + gather copy cycle in taken into account. + +*/ + +#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_DEST_SWAP_LSB 10 +#define CE_SRC_DESC_DEST_SWAP_MSB 10 +#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400 + + +/* Description GATHER + + Enables gather of multiple copy engine source descriptors + to one destination. + +*/ + +#define CE_SRC_DESC_GATHER_OFFSET 0x00000004 +#define CE_SRC_DESC_GATHER_LSB 11 +#define CE_SRC_DESC_GATHER_MSB 11 +#define CE_SRC_DESC_GATHER_MASK 0x00000800 + + +/* Description CE_RES_0 + + Reserved + +*/ + +#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_0_LSB 12 +#define CE_SRC_DESC_CE_RES_0_MSB 12 +#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000 + + +/* Description BARRIER_READ + + Barrier Read enable + +*/ + +#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004 +#define CE_SRC_DESC_BARRIER_READ_LSB 13 +#define CE_SRC_DESC_BARRIER_READ_MSB 13 +#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000 + + +/* Description CE_RES_1 + + Reserved + +*/ + +#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_1_LSB 14 +#define CE_SRC_DESC_CE_RES_1_MSB 15 +#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000 + + +/* Description LENGTH + + Length of the buffer in units of octets of the current descriptor + + +*/ + +#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004 +#define CE_SRC_DESC_LENGTH_LSB 16 +#define CE_SRC_DESC_LENGTH_MSB 31 +#define CE_SRC_DESC_LENGTH_MASK 0xffff0000 + + +/* Description FW_METADATA + + Meta data used by FW + In case of gather field in first source ring entry of the + gather copy cycle in taken into account. + +*/ + +#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008 +#define CE_SRC_DESC_FW_METADATA_LSB 0 +#define CE_SRC_DESC_FW_METADATA_MSB 15 +#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff + + +/* Description CE_RES_2 + + Reserved + +*/ + +#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008 +#define CE_SRC_DESC_CE_RES_2_LSB 16 +#define CE_SRC_DESC_CE_RES_2_MSB 31 +#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000 + + +/* Description CE_RES_3 + + Reserved + +*/ + +#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c +#define CE_SRC_DESC_CE_RES_3_LSB 0 +#define CE_SRC_DESC_CE_RES_3_MSB 19 +#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff + + +/* Description RING_ID + + The buffer pointer ring ID. + 0 refers to the IDLE ring + 1 - N refers to other rings + + Helps with debugging when dumping ring contents. + +*/ + +#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c +#define CE_SRC_DESC_RING_ID_LSB 20 +#define CE_SRC_DESC_RING_ID_MSB 27 +#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into the Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_SRC_DESC_LOOPING_COUNT_LSB 28 +#define CE_SRC_DESC_LOOPING_COUNT_MSB 31 +#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // CE_SRC_DESC diff --git a/drivers/staging/fw-api/hw/qcn6432/ce_stat_desc.h b/drivers/staging/fw-api/hw/qcn6432/ce_stat_desc.h new file mode 100644 index 0000000000000000000000000000000000000000..a9da436e070994e4e539f6ba51eba9b66ad4c74a --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/ce_stat_desc.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _CE_STAT_DESC_H_ +#define _CE_STAT_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_STAT_DESC 4 + + +struct ce_stat_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ce_res_5 : 8, // [7:0] + toeplitz_en : 1, // [8:8] + src_swap : 1, // [9:9] + dest_swap : 1, // [10:10] + gather : 1, // [11:11] + barrier_read : 1, // [12:12] + ce_res_6 : 3, // [15:13] + length : 16; // [31:16] + uint32_t toeplitz_hash_0 : 32; // [31:0] + uint32_t toeplitz_hash_1 : 32; // [31:0] + uint32_t fw_metadata : 16, // [15:0] + ce_res_7 : 4, // [19:16] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t length : 16, // [31:16] + ce_res_6 : 3, // [15:13] + barrier_read : 1, // [12:12] + gather : 1, // [11:11] + dest_swap : 1, // [10:10] + src_swap : 1, // [9:9] + toeplitz_en : 1, // [8:8] + ce_res_5 : 8; // [7:0] + uint32_t toeplitz_hash_0 : 32; // [31:0] + uint32_t toeplitz_hash_1 : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + ce_res_7 : 4, // [19:16] + fw_metadata : 16; // [15:0] +#endif +}; + + +/* Description CE_RES_5 + + Reserved + +*/ + +#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_5_LSB 0 +#define CE_STAT_DESC_CE_RES_5_MSB 7 +#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff + + +/* Description TOEPLITZ_EN + + 32-bit Toeplitz-LFSR hash for the data transfer, Enabled + + +*/ + +#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000 +#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100 + + +/* Description SRC_SWAP + + Source memory buffer swapped + +*/ + +#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_SRC_SWAP_LSB 9 +#define CE_STAT_DESC_SRC_SWAP_MSB 9 +#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200 + + +/* Description DEST_SWAP + + Destination memory buffer swapped + +*/ + +#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_DEST_SWAP_LSB 10 +#define CE_STAT_DESC_DEST_SWAP_MSB 10 +#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400 + + +/* Description GATHER + + Gather of multiple copy engine source descriptors to one + destination enabled + +*/ + +#define CE_STAT_DESC_GATHER_OFFSET 0x00000000 +#define CE_STAT_DESC_GATHER_LSB 11 +#define CE_STAT_DESC_GATHER_MSB 11 +#define CE_STAT_DESC_GATHER_MASK 0x00000800 + + +/* Description BARRIER_READ + + Barrier read enabled + +*/ + +#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000 +#define CE_STAT_DESC_BARRIER_READ_LSB 12 +#define CE_STAT_DESC_BARRIER_READ_MSB 12 +#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000 + + +/* Description CE_RES_6 + + Reserved + +*/ + +#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_6_LSB 13 +#define CE_STAT_DESC_CE_RES_6_MSB 15 +#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000 + + +/* Description LENGTH + + Sum of all the Lengths of the source descriptor in the gather + chain + +*/ + +#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000 +#define CE_STAT_DESC_LENGTH_LSB 16 +#define CE_STAT_DESC_LENGTH_MSB 31 +#define CE_STAT_DESC_LENGTH_MASK 0xffff0000 + + +/* Description TOEPLITZ_HASH_0 + + 32 LS bits of 64 bit Toeplitz LFSR hash result + +*/ + +#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff + + +/* Description TOEPLITZ_HASH_1 + + 32 MS bits of 64 bit Toeplitz LFSR hash result + +*/ + +#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff + + +/* Description FW_METADATA + + Meta data used by FW + In case of gather field in first source ring entry of the + gather copy cycle in taken into account. + +*/ + +#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c +#define CE_STAT_DESC_FW_METADATA_LSB 0 +#define CE_STAT_DESC_FW_METADATA_MSB 15 +#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff + + +/* Description CE_RES_7 + + Reserved + +*/ + +#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c +#define CE_STAT_DESC_CE_RES_7_LSB 16 +#define CE_STAT_DESC_CE_RES_7_MSB 19 +#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000 + + +/* Description RING_ID + + The buffer pointer ring ID. + 0 refers to the IDLE ring + 1 - N refers to other rings + + Helps with debugging when dumping ring contents. + +*/ + +#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c +#define CE_STAT_DESC_RING_ID_LSB 20 +#define CE_STAT_DESC_RING_ID_MSB 27 +#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into the Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_STAT_DESC_LOOPING_COUNT_LSB 28 +#define CE_STAT_DESC_LOOPING_COUNT_MSB 31 +#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // CE_STAT_DESC diff --git a/drivers/staging/fw-api/hw/qcn6432/coex_rx_status.h b/drivers/staging/fw-api/hw/qcn6432/coex_rx_status.h new file mode 100644 index 0000000000000000000000000000000000000000..2afaf284554d2f11abe85d0f8fd5f296202fd459 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/coex_rx_status.h @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _COEX_RX_STATUS_H_ +#define _COEX_RX_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_RX_STATUS 2 + +#define NUM_OF_QWORDS_COEX_RX_STATUS 1 + + +struct coex_rx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_mac_frame_status : 2, // [1:0] + rx_with_tx_response : 1, // [2:2] + rx_rate : 5, // [7:3] + rx_bw : 3, // [10:8] + single_mpdu : 1, // [11:11] + filter_status : 1, // [12:12] + ampdu : 1, // [13:13] + directed : 1, // [14:14] + reserved_0 : 1, // [15:15] + rx_nss : 3, // [18:16] + rx_rssi : 8, // [26:19] + rx_type : 3, // [29:27] + retry_bit_setting : 1, // [30:30] + more_data_bit_setting : 1; // [31:31] + uint32_t remain_rx_packet_time : 16, // [15:0] + rx_remaining_fes_time : 16; // [31:16] +#else + uint32_t more_data_bit_setting : 1, // [31:31] + retry_bit_setting : 1, // [30:30] + rx_type : 3, // [29:27] + rx_rssi : 8, // [26:19] + rx_nss : 3, // [18:16] + reserved_0 : 1, // [15:15] + directed : 1, // [14:14] + ampdu : 1, // [13:13] + filter_status : 1, // [12:12] + single_mpdu : 1, // [11:11] + rx_bw : 3, // [10:8] + rx_rate : 5, // [7:3] + rx_with_tx_response : 1, // [2:2] + rx_mac_frame_status : 2; // [1:0] + uint32_t rx_remaining_fes_time : 16, // [31:16] + remain_rx_packet_time : 16; // [15:0] +#endif +}; + + +/* Description RX_MAC_FRAME_STATUS + + RXPCU send this bit as 1 when it receives the begin of a + frame from PHY, and it passes the address filter. RXPCUsend + this bit as 0 when the frame ends. (on/off bit) + start of PPDU reception. + For SU: Generated the first time the MPDU header passes + the address filter and is destined to this STA. + For MU: Generated the first time the MPDU header from any + user passes the address filter and is destined to this + STA. + message only sent in case + of A-MPDU reception. + For SU: first time the FCS of an MPDU passes (and frame + is destined to this device) + For MU: first time the FCS of any MPDU passes (and frame + is destined to this device) + + receive of PPDU frame reception has + finished + receive of PPDU frame reception + has finished as it has been aborted due to PHY NAP generation + + +*/ + +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 + + +/* Description RX_WITH_TX_RESPONSE + + Field only valid when rx_mac_frame_status is first_mpdu_FCS_pass + or ppdu_end. + + For SU: RXPCU set this bit to indicate it is expecting the + TX to send a response after the receive. + For MU: RXPCU set this bit to indicate it is expecting that + at least for one of the users a response after the reception + needs to be generated. + + +*/ + +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 + + +/* Description RX_RATE + + For SU: RXPCU send the current receive rate at the beginning + of receive when rate is available from PHY. + For MU: RXPCU to use the current receive rate from the first + USER that triggers this TLV to be generated. + + Field is always valid + + +*/ + +#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_RATE_LSB 3 +#define COEX_RX_STATUS_RX_RATE_MSB 7 +#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 + + +/* Description RX_BW + + Actual RX bandwidth. Not SU or MU dependent. + RXPCU send the current receive rate at the beginning of + receive. This information is from PHY. + Field is always valid + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_BW_LSB 8 +#define COEX_RX_STATUS_RX_BW_MSB 10 +#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 + + +/* Description SINGLE_MPDU + + For SU: Once set the Received frame is a single MPDU. This + can be a non-AMPDU reception or A-MPDU reception but with + an EOF bit set (VHT single AMPDU). + For MU: RXPCU to base this on the first USER that triggers + this TLV to be generated. + +*/ + +#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 + + +/* Description FILTER_STATUS + + 1: LMAC is interested in receiving the full packet and forward + it to downstream modules. 0: LMAC is not interested in + receiving the packet. + + Based on the register bit 'COEX_RX_STATUS_NOFILTERIN,' + Rx PCU will send this TLV for filtered-out packets as well, + with appropriate info in the fields filter_status, AMPDU + and Directed. Otherwise, and in other chips, this TLV is + sent only for packets filtered in, with these fields set + to zero. + +*/ + +#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 + + +/* Description AMPDU + + 1: Indicates received frame is an AMPDU0: indicates received + frames in not an AMPDU + + Based on the register bit 'COEX_RX_STATUS_NOFILTERIN,' + Rx PCU will send this TLV for filtered-out packets as well, + with appropriate info in the fields filter_status, AMPDU + and Directed. Otherwise, and in other chips, this TLV is + sent only for packets filtered in, with these fields set + to zero. + +*/ + +#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_AMPDU_LSB 13 +#define COEX_RX_STATUS_AMPDU_MSB 13 +#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 + + +/* Description DIRECTED + + 1: indicates AD1 matches our Receiver address0: indicates + AD1 does not match our Receiver address + + Based on the register bit 'COEX_RX_STATUS_NOFILTERIN,' + Rx PCU will send this TLV for filtered-out packets as well, + with appropriate info in the fields filter_status, AMPDU + and Directed. Otherwise, and in other chips, this TLV is + sent only for packets filtered in, with these fields set + to zero. + +*/ + +#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_DIRECTED_LSB 14 +#define COEX_RX_STATUS_DIRECTED_MSB 14 +#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 + + +/* Description RESERVED_0 + + +*/ + +#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RESERVED_0_LSB 15 +#define COEX_RX_STATUS_RESERVED_0_MSB 15 +#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 + + +/* Description RX_NSS + + For SU: Number of spatial streams in the reception. Field + is always valid + For MU: RXPCU to base this on the first USER that triggers + this TLV to be generated. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_NSS_LSB 16 +#define COEX_RX_STATUS_RX_NSS_MSB 18 +#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 + + +/* Description RX_RSSI + + RXPCU send the current receive RSSI (from the PHYRX_RSSI_LEGACY + TLV) at the beginning of reception. This is information + is from PHY and is not SU or MU dependent. + Field is always valid + +*/ + +#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_RSSI_LSB 19 +#define COEX_RX_STATUS_RX_RSSI_MSB 26 +#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 + + +/* Description RX_TYPE + + For SU: RXPCU send the current receive packet type. Field + is always valid.This info is from MAC. + For MU: RXPCU to base this on the first USER that triggers + this TLV to be generated. + + + + + For reception of RTS frame + For reception of CTS, ACK + or BA frames + + +*/ + +#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_TYPE_LSB 27 +#define COEX_RX_STATUS_RX_TYPE_MSB 29 +#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 + + +/* Description RETRY_BIT_SETTING + + For SU: Value of the retry bit in the frame control field + of the first MPDU MAC header that passes the RxPCU frame + filter + For MU: RXPCU to base this on the first USER that triggers + this TLV to be generated. + + +*/ + +#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 + + +/* Description MORE_DATA_BIT_SETTING + + For SU: Value of the more data bit in the frame control + field of the first MPDU MAC header that passes the RxPCU + frame filter + For MU: RXPCU to base this on the first USER that triggers + this TLV to be generated. + + +*/ + +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 + + +/* Description REMAIN_RX_PACKET_TIME + + HWSCH sends current remaining rx PPDU frame time. This time + covers the entire rx_frame. This information is not in + the L-SIG and we expect to get it from PHY at the start + of the reception. + This is not SU or MU dependent. + +*/ + +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 + + +/* Description RX_REMAINING_FES_TIME + + RXPCU sends the remaining time FES time the moment a frame + with proper FCS is received. The time indicated is the + remaining rx packet time with the duration field value added. + As long as no frame with valid FCS is received, this field + should be set equal to 'remain_rx_packet_time' + This is not SU or MU dependent. + +*/ + +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 + + + +#endif // COEX_RX_STATUS diff --git a/drivers/staging/fw-api/hw/qcn6432/coex_tx_req.h b/drivers/staging/fw-api/hw/qcn6432/coex_tx_req.h new file mode 100644 index 0000000000000000000000000000000000000000..41c888fde7bc31673a8cd4ac529906adeb520aab --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/coex_tx_req.h @@ -0,0 +1,481 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _COEX_TX_REQ_H_ +#define _COEX_TX_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_TX_REQ 4 + +#define NUM_OF_QWORDS_COEX_TX_REQ 2 + + +struct coex_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_pwr : 8, // [7:0] + min_tx_pwr : 8, // [15:8] + nss : 3, // [18:16] + tx_chain_mask : 8, // [26:19] + bw : 3, // [29:27] + reserved_0 : 2; // [31:30] + uint32_t alt_tx_pwr : 8, // [7:0] + alt_min_tx_pwr : 8, // [15:8] + alt_nss : 3, // [18:16] + alt_tx_chain_mask : 8, // [26:19] + alt_bw : 3, // [29:27] + reserved_1 : 2; // [31:30] + uint32_t tx_pwr_1 : 8, // [7:0] + alt_tx_pwr_1 : 8, // [15:8] + wlan_request_duration : 16; // [31:16] + uint32_t wlan_pkt_type : 4, // [3:0] + coex_tx_reason : 2, // [5:4] + response_frame_type : 5, // [10:6] + wlan_low_priority_slicing_allowed : 1, // [11:11] + wlan_high_priority_slicing_allowed : 1, // [12:12] + sch_tx_burst_ongoing : 1, // [13:13] + coex_tx_priority : 4, // [17:14] + reserved_3a : 14; // [31:18] +#else + uint32_t reserved_0 : 2, // [31:30] + bw : 3, // [29:27] + tx_chain_mask : 8, // [26:19] + nss : 3, // [18:16] + min_tx_pwr : 8, // [15:8] + tx_pwr : 8; // [7:0] + uint32_t reserved_1 : 2, // [31:30] + alt_bw : 3, // [29:27] + alt_tx_chain_mask : 8, // [26:19] + alt_nss : 3, // [18:16] + alt_min_tx_pwr : 8, // [15:8] + alt_tx_pwr : 8; // [7:0] + uint32_t wlan_request_duration : 16, // [31:16] + alt_tx_pwr_1 : 8, // [15:8] + tx_pwr_1 : 8; // [7:0] + uint32_t reserved_3a : 14, // [31:18] + coex_tx_priority : 4, // [17:14] + sch_tx_burst_ongoing : 1, // [13:13] + wlan_high_priority_slicing_allowed : 1, // [12:12] + wlan_low_priority_slicing_allowed : 1, // [11:11] + response_frame_type : 5, // [10:6] + coex_tx_reason : 2, // [5:4] + wlan_pkt_type : 4; // [3:0] +#endif +}; + + +/* Description TX_PWR + + Default (desired) transmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_TX_PWR_LSB 0 +#define COEX_TX_REQ_TX_PWR_MSB 7 +#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff + + +/* Description MIN_TX_PWR + + Default (desired) transmit parameter + + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 +#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 +#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00 + + +/* Description NSS + + Default (desired) transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_NSS_LSB 16 +#define COEX_TX_REQ_NSS_MSB 18 +#define COEX_TX_REQ_NSS_MASK 0x0000000000070000 + + +/* Description TX_CHAIN_MASK + + Default (desired) transmit parameter + + + Chain mask to support up to 8 antennas. + +*/ + +#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 +#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 +#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000 + + +/* Description BW + + Default (desired) transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_BW_LSB 27 +#define COEX_TX_REQ_BW_MSB 29 +#define COEX_TX_REQ_BW_MASK 0x0000000038000000 + + +/* Description RESERVED_0 + + +*/ + +#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_RESERVED_0_LSB 30 +#define COEX_TX_REQ_RESERVED_0_MSB 31 +#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_TX_PWR_LSB 32 +#define COEX_TX_REQ_ALT_TX_PWR_MSB 39 +#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000 + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_NSS_LSB 48 +#define COEX_TX_REQ_ALT_NSS_MSB 50 +#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + + +*/ + +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter. + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_BW_LSB 59 +#define COEX_TX_REQ_ALT_BW_MSB 61 +#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000 + + +/* Description RESERVED_1 + + +*/ + +#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_RESERVED_1_LSB 62 +#define COEX_TX_REQ_RESERVED_1_MSB 63 +#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_TX_PWR_1_LSB 0 +#define COEX_TX_REQ_TX_PWR_1_MSB 7 +#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 +#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 +#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00 + + +/* Description WLAN_REQUEST_DURATION + + The amount of time PDG might use for the upcoming transmission + and corresponding reception if there is one... + +*/ + +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000 + + +/* Description WLAN_PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000 + + +/* Description COEX_TX_REASON + + RTS, CTS2Self or + 11h protection type transmission preceding the regular PPDU + portion of the coming FES. + Regular PPDU transmission + that follows the transmission of medium protection frames:. + + Regular PPDU transmission without + preceding medium protection frame exchanges. + + + HW generated response frame. + Details of the response frame type provided in field: Response_frame_type + + + +*/ + +#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_COEX_TX_REASON_LSB 36 +#define COEX_TX_REQ_COEX_TX_REASON_MSB 37 +#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000 + + +/* Description RESPONSE_FRAME_TYPE + + Coex related field + + + + + + + + + + + + + + + + + + + + + +*/ + +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000 + + +/* Description WLAN_LOW_PRIORITY_SLICING_ALLOWED + + When set, COEX is allowed to invoke 'tx slicing' algorithms + when WLAN tx is low priority when compared to BT activity, + to get to more optimal throughput. Value 0 will disable + this feature + +*/ + +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000 + + +/* Description WLAN_HIGH_PRIORITY_SLICING_ALLOWED + + When set, COEX is allowed to invoke 'tx slicing' algorithms + when WLAN tx is high priority when compared to BT activity, + to get to more optimal throughput. Value 0 will disable + this feature. + +*/ + +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000 + + +/* Description SCH_TX_BURST_ONGOING + + 0: No action + 1: The next scheduling command needs to start at SIFS time + after finishing the frame transmissions in this command. + This allows for SIFS based bursting + +*/ + +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000 + + +/* Description COEX_TX_PRIORITY + + Transmit priority. Used for Coex weight table look up in + case of regular FES transmission. This value is typically + programmed in relationship to the backoff engine. In case + of self_gen tx, the value comes from a programmable register + in the TXPCU. For BA and ACK packets, this is related to + AC of the incoming frame. . + + For a request type of "fes", the field is copied over from + the scheduling command TLV. + +*/ + +#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000 + + +/* Description RESERVED_3A + + +*/ + +#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_RESERVED_3A_LSB 50 +#define COEX_TX_REQ_RESERVED_3A_MSB 63 +#define COEX_TX_REQ_RESERVED_3A_MASK 0xfffc000000000000 + + + +#endif // COEX_TX_REQ diff --git a/drivers/staging/fw-api/hw/qcn6432/coex_tx_status.h b/drivers/staging/fw-api/hw/qcn6432/coex_tx_status.h new file mode 100644 index 0000000000000000000000000000000000000000..252d82a2d146b3d4b8c2d9629bedfad4f039619f --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/coex_tx_status.h @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _COEX_TX_STATUS_H_ +#define _COEX_TX_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_TX_STATUS 4 + +#define NUM_OF_QWORDS_COEX_TX_STATUS 2 + + +struct coex_tx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 7, // [6:0] + tx_bw : 3, // [9:7] + tx_status_reason : 3, // [12:10] + tx_wait_ack : 1, // [13:13] + fes_tx_is_gen_frame : 1, // [14:14] + sch_tx_burst_ongoing : 1, // [15:15] + current_tx_duration : 16; // [31:16] + uint32_t next_rx_active_time : 16, // [15:0] + remaining_fes_time : 16; // [31:16] + uint32_t tx_antenna_mask : 8, // [7:0] + shared_ant_tx_pwr : 8, // [15:8] + other_ant_tx_pwr : 8, // [23:16] + reserved_2 : 8; // [31:24] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t current_tx_duration : 16, // [31:16] + sch_tx_burst_ongoing : 1, // [15:15] + fes_tx_is_gen_frame : 1, // [14:14] + tx_wait_ack : 1, // [13:13] + tx_status_reason : 3, // [12:10] + tx_bw : 3, // [9:7] + reserved_0a : 7; // [6:0] + uint32_t remaining_fes_time : 16, // [31:16] + next_rx_active_time : 16; // [15:0] + uint32_t reserved_2 : 8, // [31:24] + other_ant_tx_pwr : 8, // [23:16] + shared_ant_tx_pwr : 8, // [15:8] + tx_antenna_mask : 8; // [7:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description RESERVED_0A + + +*/ + +#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_RESERVED_0A_LSB 0 +#define COEX_TX_STATUS_RESERVED_0A_MSB 6 +#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f + + +/* Description TX_BW + + The BW of the upcoming transmission. + Note: Coex might have changed this from the original request. + See coex related fields below + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_BW_LSB 7 +#define COEX_TX_STATUS_TX_BW_MSB 9 +#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 + + +/* Description TX_STATUS_REASON + + TXPCU sends this status at the + start of SCH initiated transmission (when the commands + are given to the PHY). This includes the transmission of + RTS and CTS + Note that based on field 'Fes_tx_is_gen_frame' COEX can + derive if this is a protection frame or regular PPDU. + + TXPCU sends this status at the end + of SCH initiated transmission (when PHY TX has confirmed + the transmit over the medium has finished) + + TXPCU sends this status at the end + of of the entire frame exchange sequence. This includes + reception (or lack of..) of the ACK/BA/CTS frame + TXPCU sends this FES after it has sent the TX_FES_STATUS + TLV(s). This also sent in case of 11ax basic trigger response + transmissions, when an ACK/BA is expected, and that got + received. + TXPCU sends this status at + the start of Self gen initiated response transmission (when + the commands are given to the PHY) + TXPCU sends this status at + the end of Self gen initiated response transmission (when + PHY TX has confirmed the transmit over the medium has finished) + + + TXPCU sends this TLV when forced + by SW to do so. It is used to be able to get TXPCU and + coex synchronized again in case of some error handling scenarios + + + +*/ + +#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 +#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 +#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 + + +/* Description TX_WAIT_ACK + + Field can only be set for the 'FES_tx_end' scenario. + TXPCU sets this bit to 1 when it is waiting for an ACK/BA + or CTS Response. +*/ + +#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 + + +/* Description FES_TX_IS_GEN_FRAME + + Field only valid in case tx_status_reason indicates FES_tx_start + or FES_tx_end. + + Field is set to 1 if the frame transmitted is a self generated + frame like RTS, CTS 2 self or NDP +*/ + +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 + + +/* Description SCH_TX_BURST_ONGOING + + The proposed change by HWSCH requires TXPCU to reflect + TX_FES_SETUP.sch_tx_burst_ongoing field intoCOEX_TX_STATUS.sch_tx_burst_ongoing + field, when tx_status_reason is FES_end. + SCH will overwrite this bit (that is set it to 1), when + TXPCU set the tx_status_reason to FES_end, and SCH determines + that this FES is followed by other SIFS bursting based + Scheduler commands. + +*/ + +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 + + +/* Description CURRENT_TX_DURATION + + In case of FES related transmission: + TXPCU sends current transmission time at the beginning of + transmission. This time covers the entire (PPDU) tx_frame. + This field is only valid when 'tx_status_reason' is equal + to FES_tx_start or Response_tx_start. In other scenarios + it is set to 0 + In us units +*/ + +#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 + + +/* Description NEXT_RX_ACTIVE_TIME + + In case of FES transmission: + The expected receive duration for ACK/CTS/BA frame after + current transmission has finished. This field should be + set at both the start and end of the transmission. When + no frame reception is expected, this field is 0 + + In case of Response transmission or Trigger Response transmission: + + The expected receive duration for upcoming reception. This + field has the same value as the transmitted duration field. + + + Note that for this scenario, there might be an other TX + generated during this specified time. It is not known to + this device what the transmitter is planning to do in the + remainder of the TXOP. In other words, this value represents + the best guess, but might not be fully accurate. + + In us units + +*/ + +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 + + +/* Description REMAINING_FES_TIME + + In case of FES transmission: + TXPCU sends the remaining FES time it expects to occupy + the media. + At the 'FES_tx_start', this value is the current_tx_duration + + value of inserted duration field. + At the 'FES_tx_end', this value is equal to the duration + field in the just transmitted frame. + At the 'FES_end', this value is the remaining FES duration + value. Note that this value should only be non zero in + case of SIFS burting type of transmissions. + In case of a FES failure, like reponse frame not received, + this field is set to 0 + + In case of Self Gen response transmission (includes Trigger + response): + At the 'Response_tx_start', this field has the same value + as the Current_tx_duration + inserted duration field + At the 'Response_tx_end', this field has the same value + as the inserted duration field + +*/ + +#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 + + +/* Description TX_ANTENNA_MASK + + The actual used antennas for this transmission + + For debug purpose only. PDG should not have modified the + value given by the Coex. + + +*/ + +#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff + + +/* Description SHARED_ANT_TX_PWR + + Actual tx power on the shared antenna + TXPCU sends at the beginning of transmission when tx_frame + is on. + + For debug purpose only. PDG should not have modified the + value given by the Coex. + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 + + +/* Description OTHER_ANT_TX_PWR + + Actual tx power on the 'unshared' antenna(s) + TXPCU sends at the beginning of transmission when tx_frame + is on. + + For debug purpose only. PDG should not have modified the + value given by the Coex. + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 + + +/* Description RESERVED_2 + + Generator should set to 0, consumer shall ignore +*/ + +#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_RESERVED_2_LSB 24 +#define COEX_TX_STATUS_RESERVED_2_MSB 31 +#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_TLV64_PADDING_LSB 32 +#define COEX_TX_STATUS_TLV64_PADDING_MSB 63 +#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // COEX_TX_STATUS diff --git a/drivers/staging/fw-api/hw/qcn6432/com_dtypes.h b/drivers/staging/fw-api/hw/qcn6432/com_dtypes.h new file mode 100644 index 0000000000000000000000000000000000000000..cfaad463a587079377342be05bf890781cee459d --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/com_dtypes.h @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef COM_DTYPES_H +#define COM_DTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* For NT apps we want to use the Win32 definitions and/or those + supplied by the Win32 compiler for things like NULL, MAX, MIN + abs, labs, etc. +*/ +#ifdef T_WINNT + #ifndef WIN32 + #define WIN32 + #endif + #include +#endif + +/* ------------------------------------------------------------------------ +** Constants +** ------------------------------------------------------------------------ */ + +#ifdef TRUE +#undef TRUE +#endif + +#ifdef FALSE +#undef FALSE +#endif + +/** @addtogroup utils_services +@{ */ + +/** @name Macros for Common Data Types +@{ */ +#define TRUE 1 /**< Boolean TRUE value. */ +#define FALSE 0 /**< Boolean FALSE value. */ + +#define ON 1 /**< ON value. */ +#define OFF 0 /**< OFF value. */ + +#ifndef NULL + #define NULL 0 /**< NULL value. */ +#endif +/** @} */ /* end_name_group Macros for Common Data Types */ + +/* ----------------------------------------------------------------------- +** Standard Types +** ----------------------------------------------------------------------- */ + +/** @} */ /* end_addtogroup utils_services */ + +/* The following definitions are the same across platforms. This first + group are the sanctioned types. +*/ +#ifndef _ARM_ASM_ +#ifndef _BOOLEAN_DEFINED + +/** @addtogroup utils_services +@{ */ +/** Boolean value type. +*/ +typedef unsigned char boolean; +#define _BOOLEAN_DEFINED +#endif + +/** @cond +*/ +#if defined(DALSTDDEF_H) /* guards against a known re-definer */ +#define _BOOLEAN_DEFINED +#define _UINT32_DEFINED +#define _UINT16_DEFINED +#define _UINT8_DEFINED +#define _INT32_DEFINED +#define _INT16_DEFINED +#define _INT8_DEFINED +#define _UINT64_DEFINED +#define _INT64_DEFINED +#define _BYTE_DEFINED +#endif /* #if !defined(DALSTDDEF_H) */ +/** @endcond */ + +#ifndef _UINT32_DEFINED +/** Unsigned 32-bit value. +*/ +typedef unsigned int uint32; +#define _UINT32_DEFINED +#endif + +#ifndef _UINT16_DEFINED +/** Unsigned 16-bit value. +*/ +typedef unsigned short uint16; +#define _UINT16_DEFINED +#endif + +#ifndef _UINT8_DEFINED +/** Unsigned 8-bit value. +*/ +typedef unsigned char uint8; +#define _UINT8_DEFINED +#endif + +#ifndef _INT32_DEFINED +/** Signed 32-bit value. +*/ +typedef signed int int32; +#define _INT32_DEFINED +#endif + +#ifndef _INT16_DEFINED +/** Signed 16-bit value. +*/ +typedef signed short int16; +#define _INT16_DEFINED +#endif + +#ifndef _INT8_DEFINED +/** Signed 8-bit value. +*/ +typedef signed char int8; +#define _INT8_DEFINED +#endif + +/** @cond +*/ +/* This group are the deprecated types. Their use should be +** discontinued and new code should use the types above +*/ +#ifndef _BYTE_DEFINED +/** DEPRECATED: Unsigned 8 bit value type. +*/ +typedef unsigned char byte; +#define _BYTE_DEFINED +#endif + +/** DEPRECATED: Unsinged 16 bit value type. +*/ +typedef unsigned short word; +/** DEPRECATED: Unsigned 32 bit value type. +*/ +typedef unsigned long dword; + +/** DEPRECATED: Unsigned 8 bit value type. +*/ +typedef unsigned char uint1; +/** DEPRECATED: Unsigned 16 bit value type. +*/ +typedef unsigned short uint2; +/** DEPRECATED: Unsigned 32 bit value type. +*/ +typedef unsigned long uint4; + +/** DEPRECATED: Signed 8 bit value type. +*/ +typedef signed char int1; +/** DEPRECATED: Signed 16 bit value type. +*/ +typedef signed short int2; +/** DEPRECATED: Signed 32 bit value type. +*/ +typedef long int int4; + +/** DEPRECATED: Signed 32 bit value. +*/ +typedef signed long sint31; +/** DEPRECATED: Signed 16 bit value. +*/ +typedef signed short sint15; +/** DEPRECATED: Signed 8 bit value. +*/ +typedef signed char sint7; + +typedef uint16 UWord16 ; +typedef uint32 UWord32 ; +typedef int32 Word32 ; +typedef int16 Word16 ; +typedef uint8 UWord8 ; +typedef int8 Word8 ; +typedef int32 Vect32 ; +/** @endcond */ + +#if (! defined T_WINNT) && (! defined __GNUC__) + /* Non WinNT Targets */ + #ifndef _INT64_DEFINED + /** Signed 64-bit value. + */ + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + /** Unsigned 64-bit value. + */ + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif +#else /* T_WINNT || TARGET_OS_SOLARIS || __GNUC__ */ + /* WINNT or SOLARIS based targets */ + #if (defined __GNUC__) + #ifndef _INT64_DEFINED + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif + #else + typedef __int64 int64; /* Signed 64-bit value */ + #ifndef _UINT64_DEFINED + typedef unsigned __int64 uint64; /* Unsigned 64-bit value */ + #define _UINT64_DEFINED + #endif + #endif +#endif /* T_WINNT */ + +#endif /* _ARM_ASM_ */ + +#ifdef __cplusplus +} +#endif + +/** @} */ /* end_addtogroup utils_services */ +#endif /* COM_DTYPES_H */ diff --git a/drivers/staging/fw-api/hw/qcn6432/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/qcn6432/eht_sig_usr_mu_mimo_info.h new file mode 100644 index 0000000000000000000000000000000000000000..0041ac68f9e6c3d78f99eeff8ca6cb4f18c775a2 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/eht_sig_usr_mu_mimo_info.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ +#define _EHT_SIG_USR_MU_MIMO_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 + + +struct eht_sig_usr_mu_mimo_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, // [10:0] + sta_mcs : 4, // [14:11] + sta_coding : 1, // [15:15] + sta_spatial_config : 6, // [21:16] + reserved_0a : 1, // [22:22] + rx_integrity_check_passed : 1, // [23:23] + subband80_cc_mask : 8; // [31:24] + uint32_t user_order_subband80_0 : 8, // [7:0] + user_order_subband80_1 : 8, // [15:8] + user_order_subband80_2 : 8, // [23:16] + user_order_subband80_3 : 8; // [31:24] +#else + uint32_t subband80_cc_mask : 8, // [31:24] + rx_integrity_check_passed : 1, // [23:23] + reserved_0a : 1, // [22:22] + sta_spatial_config : 6, // [21:16] + sta_coding : 1, // [15:15] + sta_mcs : 4, // [14:11] + sta_id : 11; // [10:0] + uint32_t user_order_subband80_3 : 8, // [31:24] + user_order_subband80_2 : 8, // [23:16] + user_order_subband80_1 : 8, // [15:8] + user_order_subband80_0 : 8; // [7:0] +#endif +}; + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff + + +/* Description STA_MCS + + Indicates the data MCS + 0 - 13: MCS 0 - 13 + 14: validate + 15: MCS 0 with DCM + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 + + +/* Description STA_SPATIAL_CONFIG + + Number of assigned spatial streams and their corresponding + index. + Total number of spatial streams assigned for the MU-MIMO + allocation is also signaled. +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 + + +/* Description RESERVED_0A + + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this EHT-SIG user info has passed, + else set to 0 + + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + + +/* Description SUBBAND80_CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channels of what 80 MHz + subbands this User field can go to + Bit 0: lowest 80 MHz content channel 0 + Bit 1: lowest 80 MHz content channel 1 + Bit 2: 2nd lowest 80 MHz content channel 0 + ... + Bit 7: highest 80 MHz content channel 1 + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + + +/* Description USER_ORDER_SUBBAND80_0 + + RX side: Set to 0 + TX side: Ordering index of the User field within the lowest + 80 MHz + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + + +/* Description USER_ORDER_SUBBAND80_1 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + lowest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + + +/* Description USER_ORDER_SUBBAND80_2 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + highest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + + +/* Description USER_ORDER_SUBBAND80_3 + + RX side: Set to 0 + TX side: Ordering index of the User field within the highest + 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + + + +#endif // EHT_SIG_USR_MU_MIMO_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/qcn6432/eht_sig_usr_ofdma_info.h new file mode 100644 index 0000000000000000000000000000000000000000..12fd6565f439dc2580ac6d0fdf7c1d8559553344 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/eht_sig_usr_ofdma_info.h @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ +#define _EHT_SIG_USR_OFDMA_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 + + +struct eht_sig_usr_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, // [10:0] + sta_mcs : 4, // [14:11] + validate_0a : 1, // [15:15] + nss : 4, // [19:16] + txbf : 1, // [20:20] + sta_coding : 1, // [21:21] + reserved_0b : 1, // [22:22] + rx_integrity_check_passed : 1, // [23:23] + subband80_cc_mask : 8; // [31:24] + uint32_t user_order_subband80_0 : 8, // [7:0] + user_order_subband80_1 : 8, // [15:8] + user_order_subband80_2 : 8, // [23:16] + user_order_subband80_3 : 8; // [31:24] +#else + uint32_t subband80_cc_mask : 8, // [31:24] + rx_integrity_check_passed : 1, // [23:23] + reserved_0b : 1, // [22:22] + sta_coding : 1, // [21:21] + txbf : 1, // [20:20] + nss : 4, // [19:16] + validate_0a : 1, // [15:15] + sta_mcs : 4, // [14:11] + sta_id : 11; // [10:0] + uint32_t user_order_subband80_3 : 8, // [31:24] + user_order_subband80_2 : 8, // [23:16] + user_order_subband80_1 : 8, // [15:8] + user_order_subband80_0 : 8; // [7:0] +#endif +}; + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff + + +/* Description STA_MCS + + Indicates the data MCS + 0 - 13: MCS 0 - 13 + 14: validate + 15: MCS 0 with DCM + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 + + +/* Description VALIDATE_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 + + +/* Description NSS + + Number of spatial streams for this user + + The actual number of streams is 1 larger than indicated + in this field. + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 + + +/* Description RESERVED_0B + + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this EHT-SIG user info has passed, + else set to 0 + + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + + +/* Description SUBBAND80_CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channels of what 80 MHz + subbands this User field can go to + Bit 0: lowest 80 MHz content channel 0 + Bit 1: lowest 80 MHz content channel 1 + Bit 2: 2nd lowest 80 MHz content channel 0 + ... + Bit 7: highest 80 MHz content channel 1 + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + + +/* Description USER_ORDER_SUBBAND80_0 + + RX side: Set to 0 + TX side: Ordering index of the User field within the lowest + 80 MHz + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + + +/* Description USER_ORDER_SUBBAND80_1 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + lowest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + + +/* Description USER_ORDER_SUBBAND80_2 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + highest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + + +/* Description USER_ORDER_SUBBAND80_3 + + RX side: Set to 0 + TX side: Ordering index of the User field within the highest + 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + + + +#endif // EHT_SIG_USR_OFDMA_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/qcn6432/eht_sig_usr_su_info.h new file mode 100644 index 0000000000000000000000000000000000000000..3b7ff3985d194abce4c550a1ac73f97749c28387 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/eht_sig_usr_su_info.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _EHT_SIG_USR_SU_INFO_H_ +#define _EHT_SIG_USR_SU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 + + +struct eht_sig_usr_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, // [10:0] + sta_mcs : 4, // [14:11] + validate_0a : 1, // [15:15] + nss : 4, // [19:16] + txbf : 1, // [20:20] + sta_coding : 1, // [21:21] + reserved_0b : 9, // [30:22] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_0b : 9, // [30:22] + sta_coding : 1, // [21:21] + txbf : 1, // [20:20] + nss : 4, // [19:16] + validate_0a : 1, // [15:15] + sta_mcs : 4, // [14:11] + sta_id : 11; // [10:0] +#endif +}; + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff + + +/* Description STA_MCS + + Indicates the data MCS + 0 - 13: MCS 0 - 13 + 14: MCS 0 with DCM and 2x duplicate + 15: MCS 0 with DCM + +*/ + +#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 + + +/* Description VALIDATE_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 + + +/* Description NSS + + Number of spatial streams for this user + + The actual number of streams is 1 larger than indicated + in this field. + +*/ + +#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 +#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 +#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 + + +/* Description RESERVED_0B + + +*/ + +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this EHT-SIG user info has passed, + else set to 0 + + +*/ + +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // EHT_SIG_USR_SU_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/expected_response.h b/drivers/staging/fw-api/hw/qcn6432/expected_response.h new file mode 100644 index 0000000000000000000000000000000000000000..120f329ced2f42917a3e46e7486b2e00e3b9d4ed --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/expected_response.h @@ -0,0 +1,700 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _EXPECTED_RESPONSE_H_ +#define _EXPECTED_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 + +#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 + + +struct expected_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_ad2_31_0 : 32; // [31:0] + uint32_t tx_ad2_47_32 : 16, // [15:0] + expected_response_type : 5, // [20:16] + response_to_response : 3, // [23:21] + su_ba_user_number : 1, // [24:24] + response_info_part2_required : 1, // [25:25] + transmitted_bssid_check_en : 1, // [26:26] + reserved_1 : 5; // [31:27] + uint32_t ndp_sta_partial_aid_2_8_0 : 11, // [10:0] + reserved_2 : 10, // [20:11] + ndp_sta_partial_aid1_8_0 : 11; // [31:21] + uint32_t ast_index : 16, // [15:0] + capture_ack_ba_sounding : 1, // [16:16] + capture_sounding_1str_20mhz : 1, // [17:17] + capture_sounding_1str_40mhz : 1, // [18:18] + capture_sounding_1str_80mhz : 1, // [19:19] + capture_sounding_1str_160mhz : 1, // [20:20] + capture_sounding_1str_240mhz : 1, // [21:21] + capture_sounding_1str_320mhz : 1, // [22:22] + reserved_3a : 9; // [31:23] + uint32_t fcs : 9, // [8:0] + reserved_4a : 1, // [9:9] + crc : 4, // [13:10] + scrambler_seed : 7, // [20:14] + reserved_4b : 11; // [31:21] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t tx_ad2_31_0 : 32; // [31:0] + uint32_t reserved_1 : 5, // [31:27] + transmitted_bssid_check_en : 1, // [26:26] + response_info_part2_required : 1, // [25:25] + su_ba_user_number : 1, // [24:24] + response_to_response : 3, // [23:21] + expected_response_type : 5, // [20:16] + tx_ad2_47_32 : 16; // [15:0] + uint32_t ndp_sta_partial_aid1_8_0 : 11, // [31:21] + reserved_2 : 10, // [20:11] + ndp_sta_partial_aid_2_8_0 : 11; // [10:0] + uint32_t reserved_3a : 9, // [31:23] + capture_sounding_1str_320mhz : 1, // [22:22] + capture_sounding_1str_240mhz : 1, // [21:21] + capture_sounding_1str_160mhz : 1, // [20:20] + capture_sounding_1str_80mhz : 1, // [19:19] + capture_sounding_1str_40mhz : 1, // [18:18] + capture_sounding_1str_20mhz : 1, // [17:17] + capture_ack_ba_sounding : 1, // [16:16] + ast_index : 16; // [15:0] + uint32_t reserved_4b : 11, // [31:21] + scrambler_seed : 7, // [20:14] + crc : 4, // [13:10] + reserved_4a : 1, // [9:9] + fcs : 9; // [8:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description TX_AD2_31_0 + + Lower 32 bits of the transmitter address (AD2) of the last + packet which was transmitted, which is used by RXPCU in + Proxy STA mode. +*/ + +#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff + + +/* Description TX_AD2_47_32 + + Upper 16 bits of the transmitter address (AD2) of the last + packet which was transmitted, which is used by RXPCU in + Proxy STA mode. +*/ + +#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 + + +/* Description EXPECTED_RESPONSE_TYPE + + Provides insight for RXPCU of what type of response is expected + in the medium. + + Mainly used for debugging purposes. + + No matter what RXPCU receives, it shall always report it + to TXPCU. + + Only special scenario where RXPCU will have to generate + a RECEIVED_RESPONSE_INFO TLV , even when no actual MPDU + with passing FCS was received is when the response_type + is set to: frameless_phyrx_response_accepted + + After transmission of this + frame, no response in SIFS time is expected + + When TXPCU sees this setting, it shall not generated the + EXPECTED_RESPONSE TLV. + + RXPCU should never see this setting + An ACK frame is expected as response + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 64 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 256 bitmap is expected. + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending + NDP or BR-Poll. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + PDG uses the size info and assumes + single BA format with ACK and 64 bitmap embedded. + If SW expects more bitmaps in case of multi-TID, is shall + program the 'Extend_duration_value_bw...' field for additional + duration time. + For TXPCU only the fact that an ACK and/or BA is received + is important. Reception of only ACK or BA is also considered + a success. + SW also typically sets this when sending VHT single MPDU. + Some chip vendors might send BA rather than ACK in response + to VHT single MPDU but still we want to accept BA as well. + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after queuing RTS frame + as standalone packet and sending it. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending PS-Poll. + + + For TXPCU either ACK and/or data reception is considered + success. + PDG basis it's response duration calculation on an ACK. + For the data portion, SW shall program the 'Extend_duration_value_bw...' + field + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for + 11ah usage + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO MU_Response_BA_bitmap + if indeed BA was received + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_data_bitmap + and MU_Response_BA_bitmap if indeed BA and data was received + + When selected, CBF frames are expected to be received in + MU reception (uplink OFDMA or uplink MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_cbf_bitmap + if indeed CBF frames were received. + When selected, MPDU frames + are expected in the MU reception (uplink OFDMA or uplink + MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_bitmap + if indeed frames were received. + Any response expected + to be send to this device in SIFS time is acceptable. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any frame in the medium to + this or any other device, is acceptable as response. + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any MU frameless + reception generated by the PHY is acceptable. + + PHY indicates this type of reception explicitly in TLV PHYRX_RSSI_LEGACY, + field Reception_type == reception_is_frameless + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU. + + This can be used for complex MU-MIMO or OFDMA scenarios, + like receiving MU-CTS. + + PDG can not calculate the uplink duration. Therefor SW shall + program the 'Extend_duration_value_bw...' field + SW sets this after + sending ranging NDPA followed by NDP as an ISTA and NDP + and LMR (Action No Ack) are expected as back-to-back reception + in SIFS. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 512 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 1024 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + When selected, CTS2S + frames are expected to be received in MU reception (uplink + OFDMA) + + RXPCU shall check each response for CTS2S and report to + TXPCU. + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed CTS2S + frames were received. + When selected, UL NDP + frames are expected to be received in MU reception (uplink + spatial multiplexing) + + RXPCU shall check each response for NDP and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed NDP + frames were received. + When selected, LMR frames + are expected to be received in MU reception (uplink OFDMA + or uplink MIMO) + + RXPCU shall check each response for LMR and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed LMR + frames were received. +*/ + +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 + + +/* Description RESPONSE_TO_RESPONSE + + Field indicates if after receiving the PPDU response (indicated + in the field above), TXPCU is expected to generate a reponse + to the response + + In case a response to response is expected, RXPCU shall + first acknowledge the proper reception of the received frames, + so that TXPCU can first wrapup that portion of the FES. + + No response after response allowed. + The response after response that TXPCU is + allowed to generate is a single BA. Even if RXPCU is indicating + that multiple users are received, TXPCU shall only send + a BA for 1 STA. Response_to_response rates can be found + in fields 'response_to_response_rate_info_bw...' + The response after response that TXPCU is + allowed to generate is only Multi Destination Multi User + BA. Response_to_response rates can be found in fields 'response_to_response_rate_info_bw...' + + + A response to response + is expected to be generated. In other words, RXPCU will + likely indicate to TXPCU at the end of upcoming reception + that a response is needed. TXPCU is however to ignore this + indication from RXPCU, and assume for a moment that no + response to response is needed, as all the details on how + to handle this is provided in the next scheduling command, + which is marked as a 'response_to_response' type. + + +*/ + +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 + + +/* Description SU_BA_USER_NUMBER + + Field only valid when Response_to_response is SU_BA + + Indicates the user number of which the BA will be send after + receiving the uplink OFDMA. +*/ + +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 + + +/* Description RESPONSE_INFO_PART2_REQUIRED + + Field only valid when Response_type is NOT set to No_response_expected + + + When set to 1, RXPCU shall generate the RECEIVED_RESPONSE_INFO_PART2 + TLV after having received the response frame. TXPCU shall + wait for this TLV before sending the TX_FES_STATUS_END + TLV. + + When NOT set, RXPCU shall NOT generate the above mentioned + TLV. TXPCU shall not wait for this TLV and after having + received RECEIVED_RESPONSE_INFO TLV, it can immediately + generate the TX_FES_STATUS_END TLV. + + +*/ + +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 + + +/* Description TRANSMITTED_BSSID_CHECK_EN + + When set to 1, RXPCU shall assume group addressed frame + with Tx_AD2 equal to TBSSID was sent. RxPCU should properly + handle receive frame(s) from STA(s) which A1 is TBSSID + or any VAPs.When NOT set, RXPCU shall compare received frame's + A1 with Tx_AD2 only. + +*/ + +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 + + +/* Description RESERVED_1 + + +*/ + +#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESERVED_1_LSB 59 +#define EXPECTED_RESPONSE_RESERVED_1_MSB 63 +#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf800000000000000 + + +/* Description NDP_STA_PARTIAL_AID_2_8_0 + + This field is applicable only in 11ah mode of operation. + This field carries the information needed for RxPCU to qualify + valid NDP-CTS + + When an RTS is being transmitted, this field provides the + partial AID of STA/BSSID of the transmitter,so the received + RA/BSSID of the NDP CTS response frame can be compared + to validate it. This value is provided by SW for valiadating + the NDP CTS. + + This filed also carries information for TA of the NDP Modified + ACK when an NDP PS-Poll is transmitted. +*/ + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff + + +/* Description RESERVED_2 + + Reserved: Generator should set to 0, consumer shall ignore + +*/ + +#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 +#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 +#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 + + +/* Description NDP_STA_PARTIAL_AID1_8_0 + + This field is applicable only in 11ah mode of operation. + This field carries the information needed for RxPCU to qualify + valid NDP Modified ACK + + TxPCU provides the partial AID (RA) of the NDP PS-Poll frame. + +*/ + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 + + +/* Description AST_INDEX + + The AST index of the receive Ack/BA. This information is + provided from the TXPCU to the RXPCU for receive Ack/BA. + +*/ + +#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_AST_INDEX_LSB 32 +#define EXPECTED_RESPONSE_AST_INDEX_MSB 47 +#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 + + +/* Description CAPTURE_ACK_BA_SOUNDING + + If set enables capture of 1str and 2str sounding on Ack + or BA as long as the corresponding capture_sounding_1str_##mhz + bits is set. + + If clear the capture of sounding on Ack or BA is disabled + even if the corresponding capture_sounding_1str_##mhz is + set. +*/ + +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 + + +/* Description CAPTURE_SOUNDING_1STR_20MHZ + + Capture sounding for 1 stream 20 MHz receive packets +*/ + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 + + +/* Description CAPTURE_SOUNDING_1STR_40MHZ + + Capture sounding for 1 stream 40 MHz receive packets +*/ + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 + + +/* Description CAPTURE_SOUNDING_1STR_80MHZ + + Capture sounding for 1 stream 80 MHz receive packets +*/ + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 + + +/* Description CAPTURE_SOUNDING_1STR_160MHZ + + Capture sounding for 1 stream 160 MHz receive packets +*/ + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 + + +/* Description CAPTURE_SOUNDING_1STR_240MHZ + + Capture sounding for 1 stream 240 MHz receive packets +*/ + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 + + +/* Description CAPTURE_SOUNDING_1STR_320MHZ + + Capture sounding for 1 stream 320 MHz receive packets +*/ + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 + + +/* Description RESERVED_3A + + Reserved: Generator should set to 0, consumer shall ignore + +*/ + +#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 +#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 +#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 + + +/* Description FCS + + Tx Frame's FCS[31:23] + + TODO: describe what this is used for ... + + For aggregates and NDP frames, this field is reserved and + TxPCU should populate this to Zero. +*/ + +#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_FCS_LSB 0 +#define EXPECTED_RESPONSE_FCS_MSB 8 +#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff + + +/* Description RESERVED_4A + + Reserved: Generator should set to 0, consumer shall ignore + +*/ + +#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_RESERVED_4A_LSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x0000000000000200 + + +/* Description CRC + + TODO: describe what this is used for ... + + Tx SIG's CRC[3:0] +*/ + +#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_CRC_LSB 10 +#define EXPECTED_RESPONSE_CRC_MSB 13 +#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 + + +/* Description SCRAMBLER_SEED + + TODO: describe what this is used for ... + + Tx Frames SERVICE[6:0] +*/ + +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 + + +/* Description RESERVED_4B + + Reserved: Generator should set to 0, consumer shall ignore + +*/ + +#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 +#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 +#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 +#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // EXPECTED_RESPONSE diff --git a/drivers/staging/fw-api/hw/qcn6432/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/qcn6432/he_sig_a_mu_dl_info.h new file mode 100644 index 0000000000000000000000000000000000000000..3a934f425c47c7f423c1f6d6dbf5c5ee3ba67b7e --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/he_sig_a_mu_dl_info.h @@ -0,0 +1,418 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HE_SIG_A_MU_DL_INFO_H_ +#define _HE_SIG_A_MU_DL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 + + +struct he_sig_a_mu_dl_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t dl_ul_flag : 1, // [0:0] + mcs_of_sig_b : 3, // [3:1] + dcm_of_sig_b : 1, // [4:4] + bss_color_id : 6, // [10:5] + spatial_reuse : 4, // [14:11] + transmit_bw : 3, // [17:15] + num_sig_b_symbols : 4, // [21:18] + comp_mode_sig_b : 1, // [22:22] + cp_ltf_size : 2, // [24:23] + doppler_indication : 1, // [25:25] + reserved_0a : 6; // [31:26] + uint32_t txop_duration : 7, // [6:0] + reserved_1a : 1, // [7:7] + num_ltf_symbols : 3, // [10:8] + ldpc_extra_symbol : 1, // [11:11] + stbc : 1, // [12:12] + packet_extension_a_factor : 2, // [14:13] + packet_extension_pe_disambiguity : 1, // [15:15] + crc : 4, // [19:16] + tail : 6, // [25:20] + reserved_1b : 5, // [30:26] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0a : 6, // [31:26] + doppler_indication : 1, // [25:25] + cp_ltf_size : 2, // [24:23] + comp_mode_sig_b : 1, // [22:22] + num_sig_b_symbols : 4, // [21:18] + transmit_bw : 3, // [17:15] + spatial_reuse : 4, // [14:11] + bss_color_id : 6, // [10:5] + dcm_of_sig_b : 1, // [4:4] + mcs_of_sig_b : 3, // [3:1] + dl_ul_flag : 1; // [0:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_1b : 5, // [30:26] + tail : 6, // [25:20] + crc : 4, // [19:16] + packet_extension_pe_disambiguity : 1, // [15:15] + packet_extension_a_factor : 2, // [14:13] + stbc : 1, // [12:12] + ldpc_extra_symbol : 1, // [11:11] + num_ltf_symbols : 3, // [10:8] + reserved_1a : 1, // [7:7] + txop_duration : 7; // [6:0] +#endif +}; + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + NOTE: This is unsupported for "HE MU" format (including "MU_SU") + +*/ + +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 + + +/* Description MCS_OF_SIG_B + + Indicates the MCS of HE-SIG-B + +*/ + +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e + + +/* Description DCM_OF_SIG_B + + Indicates whether dual sub-carrier modulation is applied + to HE-SIG-B + + 0: No DCM for HE_SIG_B + 1: DCM for HE_SIG_B + +*/ + +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field Used by MAC HW + +*/ + +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 + + +/* Description SPATIAL_REUSE + + Spatial reuse + + For 20MHz one SR field corresponding to entire 20MHz (other + 3 fields indicate identical values) + For 40MHz two SR fields for each 20MHz (other 2 fields indicate + identical values) + For 80MHz four SR fields for each 20MHz + For 160MHz four SR fields for each 40MHz + +*/ + +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + 20 Mhz + 40 Mhz + 80 MHz non-preamble puncturing + mode + 160 MHz and 80+80 MHz non-preamble + puncturing mode + for preamble puncturing + in 80 MHz, where in the preamble only the secondary 20 + MHz is punctured + for preamble + puncturing in 80 MHz, where in the preamble only one of + the two 20 MHz sub-channels in secondary 40 MHz is punctured. + + for preamble puncturing + in 160 MHz or 80+80 MHz, where in the primary 80 MHz of + the preamble only the secondary 20 MHz is punctured. + for preamble + puncturing in 160 MHz or 80+80 MHz, where in the primary + 80 MHz of the preamble the primary 40 MHz is present. + + On RX side, Field Used by MAC HW + +*/ + +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 + + +/* Description NUM_SIG_B_SYMBOLS + + Number of symbols + + For OFDMA, the actual number of symbols is 1 larger then + indicated in this field. + + For MU-MIMO this is equal to the number of users - 1: the + following encoding is used: + 1 => 2 users + 2 => 3 users + Etc. + + +*/ + +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + + +/* Description COMP_MODE_SIG_B + + Indicates the compression mode of HE-SIG-B + + 0: Regular [uncomp mode] + 1: compressed mode (full-BW MU-MIMO only) + +*/ + +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 + + +/* Description CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + 4xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + 4x LTF + 3.2 µs CP + + +*/ + +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 + + +/* Description DOPPLER_INDICATION + + 0: No Doppler support + 1: Doppler support + +*/ + +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 + + +/* Description RESERVED_0A + + +*/ + +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field Used by MAC HW + +*/ + +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f + + + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 + + +/* Description NUM_LTF_SYMBOLS + + Indicates the number of HE-LTF symbols + + 0: 1 LTF + 1: 2 LTFs + 2: 4 LTFs + 3: 6 LTFs + 4: 8 LTFs + + +*/ + +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 + + +/* Description LDPC_EXTRA_SYMBOL + + If LDPC, + 0: LDPC extra symbol not present + 1: LDPC extra symbol present + Else + Set to 1 + +*/ + +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + + +/* Description STBC + + Indicates whether STBC is applied + 0: No STBC + 1: STBC + +*/ + +#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + +*/ + +#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 +#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 +#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 + + +/* Description TAIL + + +*/ + +#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 +#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 +#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 + + +/* Description RESERVED_1B + + +*/ + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // HE_SIG_A_MU_DL_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/qcn6432/he_sig_a_mu_ul_info.h new file mode 100644 index 0000000000000000000000000000000000000000..3fcd19e6583e12335a0ae7c79ce62c6b2c41833b --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/he_sig_a_mu_ul_info.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HE_SIG_A_MU_UL_INFO_H_ +#define _HE_SIG_A_MU_UL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 + + +struct he_sig_a_mu_ul_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t format_indication : 1, // [0:0] + bss_color_id : 6, // [6:1] + spatial_reuse : 16, // [22:7] + reserved_0a : 1, // [23:23] + transmit_bw : 2, // [25:24] + reserved_0b : 6; // [31:26] + uint32_t txop_duration : 7, // [6:0] + reserved_1a : 9, // [15:7] + crc : 4, // [19:16] + tail : 6, // [25:20] + reserved_1b : 5, // [30:26] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0b : 6, // [31:26] + transmit_bw : 2, // [25:24] + reserved_0a : 1, // [23:23] + spatial_reuse : 16, // [22:7] + bss_color_id : 6, // [6:1] + format_indication : 1; // [0:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_1b : 5, // [30:26] + tail : 6, // [25:20] + crc : 4, // [19:16] + reserved_1a : 9, // [15:7] + txop_duration : 7; // [6:0] +#endif +}; + + +/* Description FORMAT_INDICATION + + Indicates whether the transmission is SU PPDU or a trigger + based UL MU PDDU + + + +*/ + +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 + + +/* Description BSS_COLOR_ID + + BSS color ID + +*/ + +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e + + +/* Description SPATIAL_REUSE + + Spatial reuse + + +*/ + +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 + + +/* Description RESERVED_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + On RX side, Field Used by MAC HW + +*/ + +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 + + +/* Description RESERVED_0B + + +*/ + +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP +*/ + +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f + + +/* Description RESERVED_1A + + Set to value indicated in the trigger frame + +*/ + +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 + + +/* Description CRC + + CRC for HE-SIG-A contents. + This CRC may also cover some fields of L-SIG (TBD) + +*/ + +#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 +#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 +#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 + + +/* Description TAIL + + BCC encoding (similar to VHT-SIG-A) with 6 tail bits is + used + +*/ + +#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 +#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 +#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 + + +/* Description RESERVED_1B + + +*/ + +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // HE_SIG_A_MU_UL_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/qcn6432/he_sig_a_su_info.h new file mode 100644 index 0000000000000000000000000000000000000000..c3a549e1c785ba1418155d53a80e799b3d98f615 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/he_sig_a_su_info.h @@ -0,0 +1,540 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HE_SIG_A_SU_INFO_H_ +#define _HE_SIG_A_SU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 + + +struct he_sig_a_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t format_indication : 1, // [0:0] + beam_change : 1, // [1:1] + dl_ul_flag : 1, // [2:2] + transmit_mcs : 4, // [6:3] + dcm : 1, // [7:7] + bss_color_id : 6, // [13:8] + reserved_0a : 1, // [14:14] + spatial_reuse : 4, // [18:15] + transmit_bw : 2, // [20:19] + cp_ltf_size : 2, // [22:21] + nsts : 3, // [25:23] + reserved_0b : 6; // [31:26] + uint32_t txop_duration : 7, // [6:0] + coding : 1, // [7:7] + ldpc_extra_symbol : 1, // [8:8] + stbc : 1, // [9:9] + txbf : 1, // [10:10] + packet_extension_a_factor : 2, // [12:11] + packet_extension_pe_disambiguity : 1, // [13:13] + reserved_1a : 1, // [14:14] + doppler_indication : 1, // [15:15] + crc : 4, // [19:16] + tail : 6, // [25:20] + dot11ax_su_extended : 1, // [26:26] + dot11ax_ext_ru_size : 3, // [29:27] + rx_ndp : 1, // [30:30] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0b : 6, // [31:26] + nsts : 3, // [25:23] + cp_ltf_size : 2, // [22:21] + transmit_bw : 2, // [20:19] + spatial_reuse : 4, // [18:15] + reserved_0a : 1, // [14:14] + bss_color_id : 6, // [13:8] + dcm : 1, // [7:7] + transmit_mcs : 4, // [6:3] + dl_ul_flag : 1, // [2:2] + beam_change : 1, // [1:1] + format_indication : 1; // [0:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + rx_ndp : 1, // [30:30] + dot11ax_ext_ru_size : 3, // [29:27] + dot11ax_su_extended : 1, // [26:26] + tail : 6, // [25:20] + crc : 4, // [19:16] + doppler_indication : 1, // [15:15] + reserved_1a : 1, // [14:14] + packet_extension_pe_disambiguity : 1, // [13:13] + packet_extension_a_factor : 2, // [12:11] + txbf : 1, // [10:10] + stbc : 1, // [9:9] + ldpc_extra_symbol : 1, // [8:8] + coding : 1, // [7:7] + txop_duration : 7; // [6:0] +#endif +}; + + +/* Description FORMAT_INDICATION + + + + +*/ + +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001 + + +/* Description BEAM_CHANGE + + Indicates whether spatial mapping is changed between legacy + and HE portion of preamble. If not, channel estimation + can include legacy preamble to improve accuracy + +*/ + +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004 + + +/* Description TRANSMIT_MCS + + Indicates the data MCS + + Field Used by MAC HW + +*/ + +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078 + + +/* Description DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DCM_LSB 7 +#define HE_SIG_A_SU_INFO_DCM_MSB 7 +#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field Used by MAC HW + +*/ + +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00 + + +/* Description RESERVED_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000 + + +/* Description SPATIAL_REUSE + + Spatial reuse + + For 20MHz one SR field corresponding to entire 20MHz (other + 3 fields indicate identical values) + For 40MHz two SR fields for each 20MHz (other 2 fields indicate + identical values) + For 80MHz four SR fields for each 20MHz + For 160MHz four SR fields for each 40MHz + +*/ + +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + For HE SU PPDU + + + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + For HE Extended Range SU PPDU + Set to 0 for 242-tone RU + + Set to 1 for right 106-tone RU within + the primary 20 MHz + + On RX side, Field Used by MAC HW + +*/ + +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000 + + +/* Description CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + NOTE: + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000 + + +/* Description NSTS + + Indicates number of streams used for the SU transmission + + + For HE SU PPDU + + + Set to n for n+1 space time stream, + where n = 0, 1, 2,.....,7. + + + + + For HE Extended Range PPDU + + + Set to 0 for 1 space time stream. + Value 1 is TBD + + + + Values 2 - 7 are reserved + +*/ + +#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_NSTS_LSB 23 +#define HE_SIG_A_SU_INFO_NSTS_MSB 25 +#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000 + + +/* Description RESERVED_0B + + +*/ + +#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field Used by MAC HW + +*/ + +#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f + + +/* Description CODING + + Distinguishes between BCC and LDPC coding. + + 0: BCC + 1: LDPC + +*/ + +#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CODING_LSB 7 +#define HE_SIG_A_SU_INFO_CODING_MSB 7 +#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080 + + +/* Description LDPC_EXTRA_SYMBOL + + If LDPC, + 0: LDPC extra symbol not present + 1: LDPC extra symbol present + Else + Set to 1 + +*/ + +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + + +/* Description STBC + + Indicates whether STBC is applied + 0: No STBC + 1: STBC + +*/ + +#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_STBC_LSB 9 +#define HE_SIG_A_SU_INFO_STBC_MSB 9 +#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXBF_LSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400 + + +/* Description PACKET_EXTENSION_A_FACTOR + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + + +/* Description RESERVED_1A + + Note: per standard, set to 1 + +*/ + +#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000 + + +/* Description DOPPLER_INDICATION + + 0: No Doppler support + 1: Doppler support + +*/ + +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + +*/ + +#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CRC_LSB 16 +#define HE_SIG_A_SU_INFO_CRC_MSB 19 +#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000 + + +/* Description TAIL + + +*/ + +#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TAIL_LSB 20 +#define HE_SIG_A_SU_INFO_TAIL_MSB 25 +#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000 + + +/* Description DOT11AX_SU_EXTENDED + + TX side: + Set to 0 + + RX side: + On RX side, evaluated by MAC HW. This is the only way for + MAC RX to know that this was an HE_SIG_A_SU received in + 'extended' format + + When set, the 11ax frame is of the extended range format + + +*/ + +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + TX side: + Set to 0 + + RX side: + Field only contains valid info when dot11ax_su_extended + is set. + + On RX side, evaluated by MAC HW. This is the only way for + MAC RX to know what the number of based RUs was in this + extended range reception. It is used by the MAC to determine + the RU size for the response... + + + + + +*/ + +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 + + +/* Description RX_NDP + + TX side: + Set to 0 + + RX side:Valid on RX side only, and looked at by MAC HW + + When set, PHY has received (expected) NDP frame + +*/ + +#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // HE_SIG_A_SU_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/qcn6432/he_sig_b1_mu_info.h new file mode 100644 index 0000000000000000000000000000000000000000..127d98ad82180aaebe95230b07973081e1a9d9af --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/he_sig_b1_mu_info.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HE_SIG_B1_MU_INFO_H_ +#define _HE_SIG_B1_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 + + +struct he_sig_b1_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation : 8, // [7:0] + reserved_0 : 23, // [30:8] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_0 : 23, // [30:8] + ru_allocation : 8; // [7:0] +#endif +}; + + +/* Description RU_ALLOCATION + + RU allocation for the user(s) following this common portion + of the SIG + + For details, refer to RU_TYPE description + +*/ + +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff + + +/* Description RESERVED_0 + + +*/ + +#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing the HE-SIG-B common info has passed, + else set to 0 + + +*/ + +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // HE_SIG_B1_MU_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/qcn6432/he_sig_b2_mu_info.h new file mode 100644 index 0000000000000000000000000000000000000000..8833cfba6d86c9e5663c793618f59a3dad540c89 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/he_sig_b2_mu_info.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HE_SIG_B2_MU_INFO_H_ +#define _HE_SIG_B2_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2 + + +struct he_sig_b2_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, // [10:0] + sta_spatial_config : 4, // [14:11] + sta_mcs : 4, // [18:15] + reserved_set_to_1 : 1, // [19:19] + sta_coding : 1, // [20:20] + reserved_0a : 7, // [27:21] + nsts : 3, // [30:28] + rx_integrity_check_passed : 1; // [31:31] + uint32_t user_order : 8, // [7:0] + cc_mask : 8, // [15:8] + reserved_1a : 16; // [31:16] +#else + uint32_t rx_integrity_check_passed : 1, // [31:31] + nsts : 3, // [30:28] + reserved_0a : 7, // [27:21] + sta_coding : 1, // [20:20] + reserved_set_to_1 : 1, // [19:19] + sta_mcs : 4, // [18:15] + sta_spatial_config : 4, // [14:11] + sta_id : 11; // [10:0] + uint32_t reserved_1a : 16, // [31:16] + cc_mask : 8, // [15:8] + user_order : 8; // [7:0] +#endif +}; + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff + + +/* Description STA_SPATIAL_CONFIG + + Number of assigned spatial streams and their corresponding + index. + Total number of spatial streams assigned for the MU-MIMO + allocation is also signaled. +*/ + +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800 + + +/* Description STA_MCS + + Indicates the data MCS +*/ + +#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000 + + + +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000 + + +/* Description RESERVED_0A + + +*/ + +#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000 + + +/* Description NSTS + + MAC RX side usage only: + Needed by RXPCU. Provided by PHY so that RXPCU does not + need to have the RU number decoding logic. + + Number of spatial streams for this user + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_NSTS_LSB 28 +#define HE_SIG_B2_MU_INFO_NSTS_MSB 30 +#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this HE-SIG-B user info has passed, + else set to 0 + + +*/ + +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + +/* Description USER_ORDER + + RX side: Set to 0 + TX side: Ordering index of the User field + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff + + +/* Description CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channel this User field + can go to + Bit 0: content channel 0 + Bit 1: content channel 1 + The other bits are unused, but could repeat the above pattern + for compatibility with 'EHT_SIG_USR_MU_MIMO_INFO.' + +*/ + +#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00 + + +/* Description RESERVED_1A + + +*/ + +#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000 + + + +#endif // HE_SIG_B2_MU_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/qcn6432/he_sig_b2_ofdma_info.h new file mode 100644 index 0000000000000000000000000000000000000000..840068981ad21b501d721a73a299e9a7f14829c6 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/he_sig_b2_ofdma_info.h @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HE_SIG_B2_OFDMA_INFO_H_ +#define _HE_SIG_B2_OFDMA_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 + + +struct he_sig_b2_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, // [10:0] + nsts : 3, // [13:11] + txbf : 1, // [14:14] + sta_mcs : 4, // [18:15] + sta_dcm : 1, // [19:19] + sta_coding : 1, // [20:20] + reserved_0 : 10, // [30:21] + rx_integrity_check_passed : 1; // [31:31] + uint32_t user_order : 8, // [7:0] + cc_mask : 8, // [15:8] + reserved_1a : 16; // [31:16] +#else + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_0 : 10, // [30:21] + sta_coding : 1, // [20:20] + sta_dcm : 1, // [19:19] + sta_mcs : 4, // [18:15] + txbf : 1, // [14:14] + nsts : 3, // [13:11] + sta_id : 11; // [10:0] + uint32_t reserved_1a : 16, // [31:16] + cc_mask : 8, // [15:8] + user_order : 8; // [7:0] +#endif +}; + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff + + +/* Description NSTS + + MAC RX side usage only: + + Number of spatial streams for this user + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 + + +/* Description STA_MCS + + Indicates the data MCS +*/ + +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 + + +/* Description STA_DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 + + +/* Description RESERVED_0 + + +*/ + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this HE-SIG-B user info has passed, + else set to 0 + + +*/ + +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + +/* Description USER_ORDER + + RX side: Set to 0 + TX side: Ordering index of the User field + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff + + +/* Description CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channel this User field + can go to + Bit 0: content channel 0 + Bit 1: content channel 1 + The other bits are unused, but could repeat the above pattern + for compatibility with 'EHT_SIG_USR_OFDMA_INFO.' + +*/ + +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 + + +/* Description RESERVED_1A + + +*/ + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 + + + +#endif // HE_SIG_B2_OFDMA_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/ht_sig_info.h b/drivers/staging/fw-api/hw/qcn6432/ht_sig_info.h new file mode 100644 index 0000000000000000000000000000000000000000..53f607d48530a494d57808fe38ec8c1f8cb27a27 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/ht_sig_info.h @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HT_SIG_INFO_H_ +#define _HT_SIG_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HT_SIG_INFO 2 + + +struct ht_sig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mcs : 7, // [6:0] + cbw : 1, // [7:7] + length : 16, // [23:8] + reserved_0 : 8; // [31:24] + uint32_t smoothing : 1, // [0:0] + not_sounding : 1, // [1:1] + ht_reserved : 1, // [2:2] + aggregation : 1, // [3:3] + stbc : 2, // [5:4] + fec_coding : 1, // [6:6] + short_gi : 1, // [7:7] + num_ext_sp_str : 2, // [9:8] + crc : 8, // [17:10] + signal_tail : 6, // [23:18] + reserved_1 : 7, // [30:24] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0 : 8, // [31:24] + length : 16, // [23:8] + cbw : 1, // [7:7] + mcs : 7; // [6:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_1 : 7, // [30:24] + signal_tail : 6, // [23:18] + crc : 8, // [17:10] + num_ext_sp_str : 2, // [9:8] + short_gi : 1, // [7:7] + fec_coding : 1, // [6:6] + stbc : 2, // [5:4] + aggregation : 1, // [3:3] + ht_reserved : 1, // [2:2] + not_sounding : 1, // [1:1] + smoothing : 1; // [0:0] +#endif +}; + + +/* Description MCS + + Modulation Coding Scheme: + 0-7 are used for single stream + 8-15 are used for 2 streams + 16-23 are used for 3 streams + 24-31 are used for 4 streams + 32 is used for duplicate HT20 (unsupported) + 33-76 is used for unequal modulation (unsupported) + 77-127 is reserved. + +*/ + +#define HT_SIG_INFO_MCS_OFFSET 0x00000000 +#define HT_SIG_INFO_MCS_LSB 0 +#define HT_SIG_INFO_MCS_MSB 6 +#define HT_SIG_INFO_MCS_MASK 0x0000007f + + +/* Description CBW + + Packet bandwidth: + + + +*/ + +#define HT_SIG_INFO_CBW_OFFSET 0x00000000 +#define HT_SIG_INFO_CBW_LSB 7 +#define HT_SIG_INFO_CBW_MSB 7 +#define HT_SIG_INFO_CBW_MASK 0x00000080 + + +/* Description LENGTH + + This is the MPDU or A-MPDU length in octets of the PPDU + +*/ + +#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000 +#define HT_SIG_INFO_LENGTH_LSB 8 +#define HT_SIG_INFO_LENGTH_MSB 23 +#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00 + + +/* Description RESERVED_0 + + This field is not part of HT-SIG + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000 +#define HT_SIG_INFO_RESERVED_0_LSB 24 +#define HT_SIG_INFO_RESERVED_0_MSB 31 +#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000 + + +/* Description SMOOTHING + + Field indicates if smoothing is needed + E_num 0 do_smoothing Unsupported setting: indicates + smoothing is often used for beamforming + Indicates no smoothing is used + + +*/ + +#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004 +#define HT_SIG_INFO_SMOOTHING_LSB 0 +#define HT_SIG_INFO_SMOOTHING_MSB 0 +#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001 + + +/* Description NOT_SOUNDING + + E_num 0 sounding Unsupported setting: indicates sounding + is used + Indicates no sounding is used + +*/ + +#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004 +#define HT_SIG_INFO_NOT_SOUNDING_LSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002 + + +/* Description HT_RESERVED + + Reserved: Should be set to 1 by the MAC and ignored by the + PHY + +*/ + +#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004 +#define HT_SIG_INFO_HT_RESERVED_LSB 2 +#define HT_SIG_INFO_HT_RESERVED_MSB 2 +#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004 + + +/* Description AGGREGATION + + Indicates MPDU format + Indicates A-MPDU format + +*/ + +#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004 +#define HT_SIG_INFO_AGGREGATION_LSB 3 +#define HT_SIG_INFO_AGGREGATION_MSB 3 +#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008 + + +/* Description STBC + + Indicates no STBC + Indicates 1 stream STBC + E_num 2 2_str_stbc Indicates 2 stream STBC (Unsupported) + + +*/ + +#define HT_SIG_INFO_STBC_OFFSET 0x00000004 +#define HT_SIG_INFO_STBC_LSB 4 +#define HT_SIG_INFO_STBC_MSB 5 +#define HT_SIG_INFO_STBC_MASK 0x00000030 + + +/* Description FEC_CODING + + Indicates BCC coding + Indicates LDPC coding + +*/ + +#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004 +#define HT_SIG_INFO_FEC_CODING_LSB 6 +#define HT_SIG_INFO_FEC_CODING_MSB 6 +#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040 + + +/* Description SHORT_GI + + Indicates normal guard interval + + Indicates short guard interval + + +*/ + +#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004 +#define HT_SIG_INFO_SHORT_GI_LSB 7 +#define HT_SIG_INFO_SHORT_GI_MSB 7 +#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080 + + +/* Description NUM_EXT_SP_STR + + Number of extension spatial streams: (Used for TxBF) + No extension spatial streams + E_num 1 1_ext_sp_str Not supported: 1 extension spatial + streams + E_num 2 2_ext_sp_str Not supported: 2 extension spatial + streams + +*/ + +#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300 + + +/* Description CRC + + The CRC protects the HT-SIG (HT-SIG[0][23:0] and HT-SIG[1][9:0]. + The generator polynomial is G(D) = D8 + D2 + D + 1. +*/ + +#define HT_SIG_INFO_CRC_OFFSET 0x00000004 +#define HT_SIG_INFO_CRC_LSB 10 +#define HT_SIG_INFO_CRC_MSB 17 +#define HT_SIG_INFO_CRC_MASK 0x0003fc00 + + +/* Description SIGNAL_TAIL + + The 6 bits of tail is always set to 0 is used to flush the + BCC encoder and decoder. +*/ + +#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004 +#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18 +#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23 +#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000 + + +/* Description RESERVED_1 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY. +*/ + +#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004 +#define HT_SIG_INFO_RESERVED_1_LSB 24 +#define HT_SIG_INFO_RESERVED_1_MSB 30 +#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HT-SIG CRC check + has passed, else set to 0 + + +*/ + +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // HT_SIG_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/l_sig_a_info.h b/drivers/staging/fw-api/hw/qcn6432/l_sig_a_info.h new file mode 100644 index 0000000000000000000000000000000000000000..f39ddc7eef67ec791c5d56d14f64485de25d7d2b --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/l_sig_a_info.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _L_SIG_A_INFO_H_ +#define _L_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_A_INFO 1 + + +struct l_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, // [3:0] + lsig_reserved : 1, // [4:4] + length : 12, // [16:5] + parity : 1, // [17:17] + tail : 6, // [23:18] + pkt_type : 4, // [27:24] + captured_implicit_sounding : 1, // [28:28] + reserved : 2, // [30:29] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved : 2, // [30:29] + captured_implicit_sounding : 1, // [28:28] + pkt_type : 4, // [27:24] + tail : 6, // [23:18] + parity : 1, // [17:17] + length : 12, // [16:5] + lsig_reserved : 1, // [4:4] + rate : 4; // [3:0] +#endif +}; + + +/* Description RATE + + This format is originally defined for OFDM as a 4 bit field + but the 5th bit was added to indicate 11b formatted frames. + In the standard bit [4] is specified as reserved. For + 11b frames this L-SIG is transformed in the PHY into the + 11b preamble format. The following are the rates: + 64-QAM 2/3 (48 Mbps) + 16-QAM 1/2 (24 Mbps) + QPSK 1/2 (12 Mbps) + BPSK 1/2 (6 Mbps) + 64-QAM 3/4 (54 Mbps) + 16-QAM 3/4 (36 Mbps) + QPSK 1/2 (18 Mbps) + BPSK 3/4 (9 Mbps) + +*/ + +#define L_SIG_A_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_A_INFO_RATE_LSB 0 +#define L_SIG_A_INFO_RATE_MSB 3 +#define L_SIG_A_INFO_RATE_MASK 0x0000000f + + +/* Description LSIG_RESERVED + + Reserved: Should be set to 0 by the MAC and ignored by the + PHY + +*/ + +#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010 + + +/* Description LENGTH + + The length indicates the number of octets in this MPDU. + Note that when using mixed mode .11n preamble or .11ac/.11ax/.11ba/.11be + this length provides the spoofed length for the PPDU. + This length provides part of the information (viz. PPDU + duration) to derive the actually PSDU length. For legacy + OFDM and 11B frames the maximum length is 4095. + +*/ + +#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_A_INFO_LENGTH_LSB 5 +#define L_SIG_A_INFO_LENGTH_MSB 16 +#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0 + + +/* Description PARITY + + 11a/n/ac TX: This field provides even parity over the first + 18 bits of the signal field which means that the sum of + 1s in the signal field will always be even on transmission. + The value of the field is computed by the MAC. + 11a/n/ac RX: this field contains the received parity field + from the L-SIG symbol for the current packet. + +*/ + +#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000 +#define L_SIG_A_INFO_PARITY_LSB 17 +#define L_SIG_A_INFO_PARITY_MSB 17 +#define L_SIG_A_INFO_PARITY_MASK 0x00020000 + + +/* Description TAIL + + The 6 bits of tail is always set to 0 is used to flush the + BCC encoder and decoder. +*/ + +#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000 +#define L_SIG_A_INFO_TAIL_LSB 18 +#define L_SIG_A_INFO_TAIL_MSB 23 +#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000 + + +/* Description PKT_TYPE + + Only used on the RX side. + Note: This is not really part of L-SIG + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000 +#define L_SIG_A_INFO_PKT_TYPE_LSB 24 +#define L_SIG_A_INFO_PKT_TYPE_MSB 27 +#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000 + + +/* Description CAPTURED_IMPLICIT_SOUNDING + + Only used on the RX side. + Note: This is not really part of L-SIG + + This indicates that the PHY has captured implicit sounding. + +*/ + +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + + +/* Description RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + +#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RESERVED_LSB 29 +#define L_SIG_A_INFO_RESERVED_MSB 30 +#define L_SIG_A_INFO_RESERVED_MASK 0x60000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the L-SIG integrity + check has passed, else set to 0 + + +*/ + +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // L_SIG_A_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/l_sig_b_info.h b/drivers/staging/fw-api/hw/qcn6432/l_sig_b_info.h new file mode 100644 index 0000000000000000000000000000000000000000..82984b33596957a27ac2b7bbfe9e3f2461f0bd17 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/l_sig_b_info.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _L_SIG_B_INFO_H_ +#define _L_SIG_B_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_B_INFO 1 + + +struct l_sig_b_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, // [3:0] + length : 12, // [15:4] + reserved : 15, // [30:16] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved : 15, // [30:16] + length : 12, // [15:4] + rate : 4; // [3:0] +#endif +}; + + +/* Description RATE + + DSSS 1 Mbps long + DSSS 2 Mbps long + CCK 5.5 Mbps long + CCK 11 Mbps long + DSSS 2 Mbps short + CCK 5.5 Mbps short + CCK 11 Mbps short + +*/ + +#define L_SIG_B_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_B_INFO_RATE_LSB 0 +#define L_SIG_B_INFO_RATE_MSB 3 +#define L_SIG_B_INFO_RATE_MASK 0x0000000f + + +/* Description LENGTH + + The length indicates the number of octets in this MPDU. + +*/ + +#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_B_INFO_LENGTH_LSB 4 +#define L_SIG_B_INFO_LENGTH_MSB 15 +#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0 + + +/* Description RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + +#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RESERVED_LSB 16 +#define L_SIG_B_INFO_RESERVED_MSB 30 +#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the .11b PHY header + CRC check has passed, else set to 0 + + +*/ + +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // L_SIG_B_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/qcn6432/macrx_abort_request_info.h new file mode 100644 index 0000000000000000000000000000000000000000..5665d020f7199a7e420aaf5514a4cae93c6abe6a --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/macrx_abort_request_info.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACRX_ABORT_REQUEST_INFO_H_ +#define _MACRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 + + +struct macrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t macrx_abort_reason : 8, // [7:0] + reserved_0 : 8; // [15:8] +#else + uint16_t reserved_0 : 8, // [15:8] + macrx_abort_reason : 8; // [7:0] +#endif +}; + + +/* Description MACRX_ABORT_REASON + + + Upon receiving this + abort reason, PHY should stop reception of the current frame + and go back into a search mode + + MAC FW + issued an abort for channel switch reasons + MAC FW issued + an abort power save reasons + RXPCU is terminating + the current ongoing reception, as the data that MAC is + receiving seems to be all garbage... The PER is too high, + or in case of MU UL, Likely the trigger frame never got + properly received by any of the targeted MU UL devices. + After the abort, PHYRX can resume a normal search mode. + RXPCU is terminating + the current ongoing UL MU reception, because at the end + of the "early_termination_window," the required number + of users with at least one valid MPDU delimiter was not + reached. Likely the trigger frame never got properly received + by the required number of targeted devices. After the abort, + PHYRX can resume a normal search mode. + + +*/ + +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff + + +/* Description RESERVED_0 + + +*/ + +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00 + + + +#endif // MACRX_ABORT_REQUEST_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/qcn6432/mactx_eht_sig_usr_mu_mimo.h new file mode 100644 index 0000000000000000000000000000000000000000..5007cfacf110896f5deadcc8840b6e7cd00808f7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_eht_sig_usr_mu_mimo.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ +#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_mu_mimo_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 + + +struct mactx_eht_sig_usr_mu_mimo { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#else + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#endif +}; + + +/* Description MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description STA_MCS + + Indicates the data MCS + 0 - 13: MCS 0 - 13 + 14: validate + 15: MCS 0 with DCM + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 + + +/* Description STA_SPATIAL_CONFIG + + Number of assigned spatial streams and their corresponding + index. + Total number of spatial streams assigned for the MU-MIMO + allocation is also signaled. +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this EHT-SIG user info has passed, + else set to 0 + + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 + + +/* Description SUBBAND80_CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channels of what 80 MHz + subbands this User field can go to + Bit 0: lowest 80 MHz content channel 0 + Bit 1: lowest 80 MHz content channel 1 + Bit 2: 2nd lowest 80 MHz content channel 0 + ... + Bit 7: highest 80 MHz content channel 1 + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 + + +/* Description USER_ORDER_SUBBAND80_0 + + RX side: Set to 0 + TX side: Ordering index of the User field within the lowest + 80 MHz + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 + + +/* Description USER_ORDER_SUBBAND80_1 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + lowest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 + + +/* Description USER_ORDER_SUBBAND80_2 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + highest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 + + +/* Description USER_ORDER_SUBBAND80_3 + + RX side: Set to 0 + TX side: Ordering index of the User field within the highest + 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 + + + +#endif // MACTX_EHT_SIG_USR_MU_MIMO diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/qcn6432/mactx_eht_sig_usr_ofdma.h new file mode 100644 index 0000000000000000000000000000000000000000..54a1f902804a3180a5d395e64892a346688cc311 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_eht_sig_usr_ofdma.h @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ +#define _MACTX_EHT_SIG_USR_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1 + + +struct mactx_eht_sig_usr_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#else + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#endif +}; + + +/* Description MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description STA_MCS + + Indicates the data MCS + 0 - 13: MCS 0 - 13 + 14: validate + 15: MCS 0 with DCM + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + + +/* Description VALIDATE_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 + + +/* Description NSS + + Number of spatial streams for this user + + The actual number of streams is 1 larger than indicated + in this field. + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 + + +/* Description RESERVED_0B + + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this EHT-SIG user info has passed, + else set to 0 + + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 + + +/* Description SUBBAND80_CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channels of what 80 MHz + subbands this User field can go to + Bit 0: lowest 80 MHz content channel 0 + Bit 1: lowest 80 MHz content channel 1 + Bit 2: 2nd lowest 80 MHz content channel 0 + ... + Bit 7: highest 80 MHz content channel 1 + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 + + +/* Description USER_ORDER_SUBBAND80_0 + + RX side: Set to 0 + TX side: Ordering index of the User field within the lowest + 80 MHz + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 + + +/* Description USER_ORDER_SUBBAND80_1 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + lowest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 + + +/* Description USER_ORDER_SUBBAND80_2 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + highest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 + + +/* Description USER_ORDER_SUBBAND80_3 + + RX side: Set to 0 + TX side: Ordering index of the User field within the highest + 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 + + + +#endif // MACTX_EHT_SIG_USR_OFDMA diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/qcn6432/mactx_eht_sig_usr_su.h new file mode 100644 index 0000000000000000000000000000000000000000..e1d205fee8632454a445bdb01cd3a84cd4f7f9d1 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_eht_sig_usr_su.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_EHT_SIG_USR_SU_H_ +#define _MACTX_EHT_SIG_USR_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_su_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1 + + +struct mactx_eht_sig_usr_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_EHT_SIG_USR_SU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description STA_MCS + + Indicates the data MCS + 0 - 13: MCS 0 - 13 + 14: MCS 0 with DCM and 2x duplicate + 15: MCS 0 with DCM + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + + +/* Description VALIDATE_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 + + +/* Description NSS + + Number of spatial streams for this user + + The actual number of streams is 1 larger than indicated + in this field. + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 + + +/* Description RESERVED_0B + + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this EHT-SIG user info has passed, + else set to 0 + + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_EHT_SIG_USR_SU diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_a_mu_dl.h new file mode 100644 index 0000000000000000000000000000000000000000..cfa11ba0cf6b7b56a1c5988d6306a51e14beaa88 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_a_mu_dl.h @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HE_SIG_A_MU_DL_H_ +#define _MACTX_HE_SIG_A_MU_DL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1 + + +struct mactx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#endif +}; + + +/* Description MACTX_HE_SIG_A_MU_DL_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + NOTE: This is unsupported for "HE MU" format (including "MU_SU") + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 + + +/* Description MCS_OF_SIG_B + + Indicates the MCS of HE-SIG-B + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e + + +/* Description DCM_OF_SIG_B + + Indicates whether dual sub-carrier modulation is applied + to HE-SIG-B + + 0: No DCM for HE_SIG_B + 1: DCM for HE_SIG_B + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 + + +/* Description SPATIAL_REUSE + + Spatial reuse + + For 20MHz one SR field corresponding to entire 20MHz (other + 3 fields indicate identical values) + For 40MHz two SR fields for each 20MHz (other 2 fields indicate + identical values) + For 80MHz four SR fields for each 20MHz + For 160MHz four SR fields for each 40MHz + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + 20 Mhz + 40 Mhz + 80 MHz non-preamble puncturing + mode + 160 MHz and 80+80 MHz non-preamble + puncturing mode + for preamble puncturing + in 80 MHz, where in the preamble only the secondary 20 + MHz is punctured + for preamble + puncturing in 80 MHz, where in the preamble only one of + the two 20 MHz sub-channels in secondary 40 MHz is punctured. + + for preamble puncturing + in 160 MHz or 80+80 MHz, where in the primary 80 MHz of + the preamble only the secondary 20 MHz is punctured. + for preamble + puncturing in 160 MHz or 80+80 MHz, where in the primary + 80 MHz of the preamble the primary 40 MHz is present. + + On RX side, Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 + + +/* Description NUM_SIG_B_SYMBOLS + + Number of symbols + + For OFDMA, the actual number of symbols is 1 larger then + indicated in this field. + + For MU-MIMO this is equal to the number of users - 1: the + following encoding is used: + 1 => 2 users + 2 => 3 users + Etc. + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 + + +/* Description COMP_MODE_SIG_B + + Indicates the compression mode of HE-SIG-B + + 0: Regular [uncomp mode] + 1: compressed mode (full-BW MU-MIMO only) + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 + + +/* Description CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + 4xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + 4x LTF + 3.2 µs CP + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 + + +/* Description DOPPLER_INDICATION + + 0: No Doppler support + 1: Doppler support + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + +/* Description RESERVED_1A + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + + +/* Description NUM_LTF_SYMBOLS + + Indicates the number of HE-LTF symbols + + 0: 1 LTF + 1: 2 LTFs + 2: 4 LTFs + 3: 6 LTFs + 4: 8 LTFs + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 + + +/* Description LDPC_EXTRA_SYMBOL + + If LDPC, + 0: LDPC extra symbol not present + 1: LDPC extra symbol present + Else + Set to 1 + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 + + +/* Description STBC + + Indicates whether STBC is applied + 0: No STBC + 1: STBC + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_HE_SIG_A_MU_DL diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_a_mu_ul.h new file mode 100644 index 0000000000000000000000000000000000000000..ccbf7b9187a83a2ad2dd6d171dd5e75d32bd6f3a --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_a_mu_ul.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HE_SIG_A_MU_UL_H_ +#define _MACTX_HE_SIG_A_MU_UL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1 + + +struct mactx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#endif +}; + + +/* Description MACTX_HE_SIG_A_MU_UL_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description FORMAT_INDICATION + + Indicates whether the transmission is SU PPDU or a trigger + based UL MU PDDU + + + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + + +/* Description BSS_COLOR_ID + + BSS color ID + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e + + +/* Description SPATIAL_REUSE + + Spatial reuse + + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 + + +/* Description RESERVED_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + On RX side, Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 + + +/* Description RESERVED_0B + + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + +/* Description RESERVED_1A + + Set to value indicated in the trigger frame + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + This CRC may also cover some fields of L-SIG (TBD) + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + BCC encoding (similar to VHT-SIG-A) with 6 tail bits is + used + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_HE_SIG_A_MU_UL diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_a_su.h new file mode 100644 index 0000000000000000000000000000000000000000..91d593c8774f3cd053797aebf15485b780a14e2e --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_a_su.h @@ -0,0 +1,497 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HE_SIG_A_SU_H_ +#define _MACTX_HE_SIG_A_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1 + + +struct mactx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#endif +}; + + +/* Description MACTX_HE_SIG_A_SU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description FORMAT_INDICATION + + + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + + +/* Description BEAM_CHANGE + + Indicates whether spatial mapping is changed between legacy + and HE portion of preamble. If not, channel estimation + can include legacy preamble to improve accuracy + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 + + +/* Description TRANSMIT_MCS + + Indicates the data MCS + + Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 + + +/* Description DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 + + +/* Description RESERVED_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 + + +/* Description SPATIAL_REUSE + + Spatial reuse + + For 20MHz one SR field corresponding to entire 20MHz (other + 3 fields indicate identical values) + For 40MHz two SR fields for each 20MHz (other 2 fields indicate + identical values) + For 80MHz four SR fields for each 20MHz + For 160MHz four SR fields for each 40MHz + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + For HE SU PPDU + + + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + For HE Extended Range SU PPDU + Set to 0 for 242-tone RU + + Set to 1 for right 106-tone RU within + the primary 20 MHz + + On RX side, Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 + + +/* Description CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + NOTE: + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 + + +/* Description NSTS + + Indicates number of streams used for the SU transmission + + + For HE SU PPDU + + + Set to n for n+1 space time stream, + where n = 0, 1, 2,.....,7. + + + + + For HE Extended Range PPDU + + + Set to 0 for 1 space time stream. + Value 1 is TBD + + + + Values 2 - 7 are reserved + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 + + +/* Description RESERVED_0B + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + +/* Description CODING + + Distinguishes between BCC and LDPC coding. + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 + + +/* Description LDPC_EXTRA_SYMBOL + + If LDPC, + 0: LDPC extra symbol not present + 1: LDPC extra symbol present + Else + Set to 1 + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 + + +/* Description STBC + + Indicates whether STBC is applied + 0: No STBC + 1: STBC + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 + + +/* Description RESERVED_1A + + Note: per standard, set to 1 + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 + + +/* Description DOPPLER_INDICATION + + 0: No Doppler support + 1: Doppler support + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description DOT11AX_SU_EXTENDED + + TX side: + Set to 0 + + RX side: + On RX side, evaluated by MAC HW. This is the only way for + MAC RX to know that this was an HE_SIG_A_SU received in + 'extended' format + + When set, the 11ax frame is of the extended range format + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + TX side: + Set to 0 + + RX side: + Field only contains valid info when dot11ax_su_extended + is set. + + On RX side, evaluated by MAC HW. This is the only way for + MAC RX to know what the number of based RUs was in this + extended range reception. It is used by the MAC to determine + the RU size for the response... + + + + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 + + +/* Description RX_NDP + + TX side: + Set to 0 + + RX side:Valid on RX side only, and looked at by MAC HW + + When set, PHY has received (expected) NDP frame + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_HE_SIG_A_SU diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_b1_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..a98584157c907ceaa550aec86660d3dd3926a57b --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_b1_mu.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HE_SIG_B1_MU_H_ +#define _MACTX_HE_SIG_B1_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 + + +struct mactx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_HE_SIG_B1_MU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description RU_ALLOCATION + + RU allocation for the user(s) following this common portion + of the SIG + + For details, refer to RU_TYPE description + +*/ + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff + + +/* Description RESERVED_0 + + +*/ + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing the HE-SIG-B common info has passed, + else set to 0 + + +*/ + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_HE_SIG_B1_MU diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_b2_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..8340eb2cee2dd49290f47197d09a6a72e50349b0 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_b2_mu.h @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HE_SIG_B2_MU_H_ +#define _MACTX_HE_SIG_B2_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1 + + +struct mactx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#endif +}; + + +/* Description MACTX_HE_SIG_B2_MU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description STA_SPATIAL_CONFIG + + Number of assigned spatial streams and their corresponding + index. + Total number of spatial streams assigned for the MU-MIMO + allocation is also signaled. +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 + + +/* Description STA_MCS + + Indicates the data MCS +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + + + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 + + +/* Description NSTS + + MAC RX side usage only: + Needed by RXPCU. Provided by PHY so that RXPCU does not + need to have the RU number decoding logic. + + Number of spatial streams for this user + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this HE-SIG-B user info has passed, + else set to 0 + + +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description USER_ORDER + + RX side: Set to 0 + TX side: Ordering index of the User field + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + + +/* Description CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channel this User field + can go to + Bit 0: content channel 0 + Bit 1: content channel 1 + The other bits are unused, but could repeat the above pattern + for compatibility with 'EHT_SIG_USR_MU_MIMO_INFO.' + +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + + + +#endif // MACTX_HE_SIG_B2_MU diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_b2_ofdma.h new file mode 100644 index 0000000000000000000000000000000000000000..9d45bbd18f52ce3948ea26e2e7db0b3d53413e9d --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_he_sig_b2_ofdma.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ +#define _MACTX_HE_SIG_B2_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1 + + +struct mactx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#endif +}; + + +/* Description MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description NSTS + + MAC RX side usage only: + + Number of spatial streams for this user + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 + + +/* Description STA_MCS + + Indicates the data MCS +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + + +/* Description STA_DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + + +/* Description RESERVED_0 + + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this HE-SIG-B user info has passed, + else set to 0 + + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description USER_ORDER + + RX side: Set to 0 + TX side: Ordering index of the User field + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + + +/* Description CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channel this User field + can go to + Bit 0: content channel 0 + Bit 1: content channel 1 + The other bits are unused, but could repeat the above pattern + for compatibility with 'EHT_SIG_USR_OFDMA_INFO.' + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + + + +#endif // MACTX_HE_SIG_B2_OFDMA diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_ht_sig.h b/drivers/staging/fw-api/hw/qcn6432/mactx_ht_sig.h new file mode 100644 index 0000000000000000000000000000000000000000..6329fdb2ba13e20340d7a9d7bc106578b295ae82 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_ht_sig.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HT_SIG_H_ +#define _MACTX_HT_SIG_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_MACTX_HT_SIG 2 + +#define NUM_OF_QWORDS_MACTX_HT_SIG 1 + + +struct mactx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info mactx_ht_sig_info_details; +#else + struct ht_sig_info mactx_ht_sig_info_details; +#endif +}; + + +/* Description MACTX_HT_SIG_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description MCS + + Modulation Coding Scheme: + 0-7 are used for single stream + 8-15 are used for 2 streams + 16-23 are used for 3 streams + 24-31 are used for 4 streams + 32 is used for duplicate HT20 (unsupported) + 33-76 is used for unequal modulation (unsupported) + 77-127 is reserved. + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f + + +/* Description CBW + + Packet bandwidth: + + + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 + + +/* Description LENGTH + + This is the MPDU or A-MPDU length in octets of the PPDU + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 + + +/* Description RESERVED_0 + + This field is not part of HT-SIG + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + + +/* Description SMOOTHING + + Field indicates if smoothing is needed + E_num 0 do_smoothing Unsupported setting: indicates + smoothing is often used for beamforming + Indicates no smoothing is used + + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 + + +/* Description NOT_SOUNDING + + E_num 0 sounding Unsupported setting: indicates sounding + is used + Indicates no sounding is used + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 + + +/* Description HT_RESERVED + + Reserved: Should be set to 1 by the MAC and ignored by the + PHY + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 + + +/* Description AGGREGATION + + Indicates MPDU format + Indicates A-MPDU format + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 + + +/* Description STBC + + Indicates no STBC + Indicates 1 stream STBC + E_num 2 2_str_stbc Indicates 2 stream STBC (Unsupported) + + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 + + +/* Description FEC_CODING + + Indicates BCC coding + Indicates LDPC coding + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 + + +/* Description SHORT_GI + + Indicates normal guard interval + + Indicates short guard interval + + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 + + +/* Description NUM_EXT_SP_STR + + Number of extension spatial streams: (Used for TxBF) + No extension spatial streams + E_num 1 1_ext_sp_str Not supported: 1 extension spatial + streams + E_num 2 2_ext_sp_str Not supported: 2 extension spatial + streams + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 + + +/* Description CRC + + The CRC protects the HT-SIG (HT-SIG[0][23:0] and HT-SIG[1][9:0]. + The generator polynomial is G(D) = D8 + D2 + D + 1. +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + + +/* Description SIGNAL_TAIL + + The 6 bits of tail is always set to 0 is used to flush the + BCC encoder and decoder. +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 + + +/* Description RESERVED_1 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY. +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HT-SIG CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_HT_SIG diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/qcn6432/mactx_l_sig_a.h new file mode 100644 index 0000000000000000000000000000000000000000..a1ef2681b07b8187b2fea11702a010ac824774a8 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_l_sig_a.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_L_SIG_A_H_ +#define _MACTX_L_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_A 2 + +#define NUM_OF_QWORDS_MACTX_L_SIG_A 1 + + +struct mactx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info mactx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct l_sig_a_info mactx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_L_SIG_A_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description RATE + + This format is originally defined for OFDM as a 4 bit field + but the 5th bit was added to indicate 11b formatted frames. + In the standard bit [4] is specified as reserved. For + 11b frames this L-SIG is transformed in the PHY into the + 11b preamble format. The following are the rates: + 64-QAM 2/3 (48 Mbps) + 16-QAM 1/2 (24 Mbps) + QPSK 1/2 (12 Mbps) + BPSK 1/2 (6 Mbps) + 64-QAM 3/4 (54 Mbps) + 16-QAM 3/4 (36 Mbps) + QPSK 1/2 (18 Mbps) + BPSK 3/4 (9 Mbps) + +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f + + +/* Description LSIG_RESERVED + + Reserved: Should be set to 0 by the MAC and ignored by the + PHY + +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 + + +/* Description LENGTH + + The length indicates the number of octets in this MPDU. + Note that when using mixed mode .11n preamble or .11ac/.11ax/.11ba/.11be + this length provides the spoofed length for the PPDU. + This length provides part of the information (viz. PPDU + duration) to derive the actually PSDU length. For legacy + OFDM and 11B frames the maximum length is 4095. + +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 + + +/* Description PARITY + + 11a/n/ac TX: This field provides even parity over the first + 18 bits of the signal field which means that the sum of + 1s in the signal field will always be even on transmission. + The value of the field is computed by the MAC. + 11a/n/ac RX: this field contains the received parity field + from the L-SIG symbol for the current packet. + +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 + + +/* Description TAIL + + The 6 bits of tail is always set to 0 is used to flush the + BCC encoder and decoder. +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 + + +/* Description PKT_TYPE + + Only used on the RX side. + Note: This is not really part of L-SIG + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + + +/* Description CAPTURED_IMPLICIT_SOUNDING + + Only used on the RX side. + Note: This is not really part of L-SIG + + This indicates that the PHY has captured implicit sounding. + +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 + + +/* Description RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the L-SIG integrity + check has passed, else set to 0 + + +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32 +#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63 +#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_L_SIG_A diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/qcn6432/mactx_l_sig_b.h new file mode 100644 index 0000000000000000000000000000000000000000..6bf3831e1ca83f60578c439c6650d63e9a9e716b --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_l_sig_b.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_L_SIG_B_H_ +#define _MACTX_L_SIG_B_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_B 2 + +#define NUM_OF_QWORDS_MACTX_L_SIG_B 1 + + +struct mactx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info mactx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct l_sig_b_info mactx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_L_SIG_B_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description RATE + + DSSS 1 Mbps long + DSSS 2 Mbps long + CCK 5.5 Mbps long + CCK 11 Mbps long + DSSS 2 Mbps short + CCK 5.5 Mbps short + CCK 11 Mbps short + +*/ + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f + + +/* Description LENGTH + + The length indicates the number of octets in this MPDU. + +*/ + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 + + +/* Description RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the .11b PHY header + CRC check has passed, else set to 0 + + +*/ + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32 +#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63 +#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_L_SIG_B diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_phy_desc.h b/drivers/staging/fw-api/hw/qcn6432/mactx_phy_desc.h new file mode 100644 index 0000000000000000000000000000000000000000..86983de1db17433f8a7d43623e64884e57f20201 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_phy_desc.h @@ -0,0 +1,1079 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_PHY_DESC_H_ +#define _MACTX_PHY_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 + +#define NUM_OF_QWORDS_MACTX_PHY_DESC 2 + + +struct mactx_phy_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 16, // [15:0] + bf_type : 2, // [17:16] + wait_sifs : 2, // [19:18] + dot11b_preamble_type : 1, // [20:20] + pkt_type : 4, // [24:21] + su_or_mu : 2, // [26:25] + mu_type : 1, // [27:27] + bandwidth : 3, // [30:28] + channel_capture : 1; // [31:31] + uint32_t mcs : 4, // [3:0] + global_ofdma_mimo_enable : 1, // [4:4] + reserved_1a : 1, // [5:5] + stbc : 1, // [6:6] + dot11ax_su_extended : 1, // [7:7] + dot11ax_trigger_frame_embedded : 1, // [8:8] + tx_pwr_shared : 8, // [16:9] + tx_pwr_unshared : 8, // [24:17] + measure_power : 1, // [25:25] + tpc_glut_self_cal : 1, // [26:26] + back_to_back_transmission_expected : 1, // [27:27] + heavy_clip_nss : 3, // [30:28] + txbf_per_packet_no_csd_no_walsh : 1; // [31:31] + uint32_t ndp : 2, // [1:0] + ul_flag : 1, // [2:2] + triggered : 1, // [3:3] + ap_pkt_bw : 3, // [6:4] + ru_position_start : 8, // [14:7] + pcu_ppdu_setup_start_reason : 3, // [17:15] + tlv_source : 1, // [18:18] + reserved_2a : 2, // [20:19] + nss : 3, // [23:21] + stream_offset : 3, // [26:24] + reserved_2b : 2, // [28:27] + clpc_enable : 1, // [29:29] + mu_ndp : 1, // [30:30] + response_expected : 1; // [31:31] + uint32_t rx_chain_mask : 8, // [7:0] + rx_chain_mask_valid : 1, // [8:8] + ant_sel_valid : 1, // [9:9] + ant_sel : 1, // [10:10] + cp_setting : 2, // [12:11] + he_ppdu_subtype : 2, // [14:13] + active_channel : 3, // [17:15] + generate_phyrx_tx_start_timing : 1, // [18:18] + ltf_size : 2, // [20:19] + ru_size_updated_v2 : 4, // [24:21] + reserved_3c : 1, // [25:25] + u_sig_puncture_pattern_encoding : 6; // [31:26] +#else + uint32_t channel_capture : 1, // [31:31] + bandwidth : 3, // [30:28] + mu_type : 1, // [27:27] + su_or_mu : 2, // [26:25] + pkt_type : 4, // [24:21] + dot11b_preamble_type : 1, // [20:20] + wait_sifs : 2, // [19:18] + bf_type : 2, // [17:16] + reserved_0a : 16; // [15:0] + uint32_t txbf_per_packet_no_csd_no_walsh : 1, // [31:31] + heavy_clip_nss : 3, // [30:28] + back_to_back_transmission_expected : 1, // [27:27] + tpc_glut_self_cal : 1, // [26:26] + measure_power : 1, // [25:25] + tx_pwr_unshared : 8, // [24:17] + tx_pwr_shared : 8, // [16:9] + dot11ax_trigger_frame_embedded : 1, // [8:8] + dot11ax_su_extended : 1, // [7:7] + stbc : 1, // [6:6] + reserved_1a : 1, // [5:5] + global_ofdma_mimo_enable : 1, // [4:4] + mcs : 4; // [3:0] + uint32_t response_expected : 1, // [31:31] + mu_ndp : 1, // [30:30] + clpc_enable : 1, // [29:29] + reserved_2b : 2, // [28:27] + stream_offset : 3, // [26:24] + nss : 3, // [23:21] + reserved_2a : 2, // [20:19] + tlv_source : 1, // [18:18] + pcu_ppdu_setup_start_reason : 3, // [17:15] + ru_position_start : 8, // [14:7] + ap_pkt_bw : 3, // [6:4] + triggered : 1, // [3:3] + ul_flag : 1, // [2:2] + ndp : 2; // [1:0] + uint32_t u_sig_puncture_pattern_encoding : 6, // [31:26] + reserved_3c : 1, // [25:25] + ru_size_updated_v2 : 4, // [24:21] + ltf_size : 2, // [20:19] + generate_phyrx_tx_start_timing : 1, // [18:18] + active_channel : 3, // [17:15] + he_ppdu_subtype : 2, // [14:13] + cp_setting : 2, // [12:11] + ant_sel : 1, // [10:10] + ant_sel_valid : 1, // [9:9] + rx_chain_mask_valid : 1, // [8:8] + rx_chain_mask : 8; // [7:0] +#endif +}; + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 +#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 +#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff + + +/* Description BF_TYPE + + Transmit a non-beamformed packet. NOTE + that MAC might have send MACTX_BF_PARAMS... related TLVs + to the PHY for this upcoming transmission, but if this + field indicates NO_BF, MAC_TX has for some reason decided + at the last moment that actual beamform transmission shall + not happen anymore... + Transmit a legacy beamformed packet. + This means beamforming starts at the L-STF. The possible + preamble formats are 11a, 11n mixed mode and 11ac. This + is used to support legacy implicit beamforming. + Transmit a single-user beamformed packet + starting at the HT-STF or VHT-STF. + Transmit a multi-user beamformed packet + starting at the VHT-STF. In case of an MU transmission, + where maybe not all users are being transmitted in a 'beamformed' + way, but at least one is, this e_num setting will be used + as well + +*/ + +#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BF_TYPE_LSB 16 +#define MACTX_PHY_DESC_BF_TYPE_MSB 17 +#define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 + + +/* Description WAIT_SIFS + + This bit is evaluated by the PHY TX to determine if this + transmission start on the air needs to be exactly SIFS + aligned compared to the end of the previous reception or + previous transmission. + + This feature is typically required for Triggered UL response + transmissions, where SIFS accuracy is really required. + For RTT this is also usefull, but not absolutely needed. + + + + This field is filled in by TXPCU. + + Transmission shall start with the + normal delay in PHY after receiving this notification + Transmission shall be made + at the SIFS boundary. If shall never start before SIFS boundary, + but if it a little later, it is not ideal and should be + flagged, but transmission shall not be aborted. + Transmission shall be made + at exactly SIFS boundary. If this notification is received + by the PHY after SIFS boundary already passed, the PHY + shall abort the transmission + +*/ + +#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 +#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 +#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 + + +/* Description DOT11B_PREAMBLE_TYPE + + Valid for 802.11b packets only. + + + +*/ + +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 + + +/* Description PKT_TYPE + + Packet type: + + Note: in case of 11ax, see field he_ppdu_subtype for additional + info... + + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 +#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 +#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 + + +/* Description SU_OR_MU + + Type of transmission: + + For 11ax: + + 11ax: + This setting is used for the following preamble type of + transmissions: + 11ax HE_SU PPDU + 11ax HE_EXT_SU PPDU + 11ax HE_TRIG PPDU + Note that the above implies all single user transmissions + + + 11ac and other pkt_types: + Single user transmission + + + 11ax: + This setting is used for the following preamble type of + transmissions: + 11ax HE_MU + Note that this type of transmission implies multiple users + + + For 11ac: + Multi-user transmission + + + 11ax: + This setting is used for the following preamble type of + transmissions: + 11ax HE_MU + Note that this type of transmission implies a SINGLE user, + but using HE_MU preamble type... + + 11ac and other pkt_types: + Reserved + + +*/ + +#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 +#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 +#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 + + +/* Description MU_TYPE + + Field only valid when + SU_or_MU == MU_transmission or + SU_or_MU == MU_SU_transmission + + Note that within the RUs, + there might still be MU-MIMO... + +*/ + +#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MU_TYPE_LSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 + + +/* Description BANDWIDTH + + Packet bandwidth: + + The physical bandwidth that this device will be transmitting + in. + + Note that for 11ax Trigger response transmissions (when + Field triggered == is_triggered), this bandwith is min(AP_pkt_bw, + STA_ch_bw) + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 +#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 +#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 + + +/* Description CHANNEL_CAPTURE + + Indicates that the PHY should be armed to capture the channel + on the next received packet. This channel estimate is passed + to the MAC if the packet is successfully received. + + This field is not applicable for 11ah since implicit beamforming + is not supported +*/ + +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 + + +/* Description MCS + + In case of SU_or_MU == SU_transmission + + Note that this includes trigger response transmission + + The MCS to be used for the upcoming transmission. It must + match the 4-bit MCS value that is sent in the appropriate + signal field for the given packet type, except that EHT + BPSK with DCM and/or duplicate is encoded as '0.' + + In case of .11ba (WUR), this field is filled according to + what is on the MAC side defined as "MCS_TYPE" + + In case of SU_or_MU == MU_transmission + .11ac: highest MCS of all users + .11ax or .11be: highest 4-bit MCS field in all the HE_SIG_B + or EHT_SIG TLVs that MAC S/W informs to MAC H/W. Actual + highest 4-bit MCS to be sent to PHY might be lower after + MAC H/W computation. + + For details, refer to the SIG field, related to this pkt_type. + + (Note that this is slightly different then what is on the + MAC side defined as "MCS_TYPE". For this reason, the 'legal + values' here are NOT defined as MCS_TYPE) + +*/ + +#define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MCS_LSB 32 +#define MACTX_PHY_DESC_MCS_MSB 35 +#define MACTX_PHY_DESC_MCS_MASK 0x0000000f00000000 + + +/* Description GLOBAL_OFDMA_MIMO_ENABLE + + When set, this transmission contains at least 1 user for + which MU-MIMO is enabled in its RU. + After per-BW/puncture pattern user disabling, in case of + pure OFDMA, PDG will clear this bit, but full BW MU-MIMO + is still possible with this bit set. + +*/ + +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 36 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 36 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000001000000000 + + +/* Description RESERVED_1A + +*/ + +#define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_RESERVED_1A_LSB 37 +#define MACTX_PHY_DESC_RESERVED_1A_MSB 37 +#define MACTX_PHY_DESC_RESERVED_1A_MASK 0x0000002000000000 + + +/* Description STBC + + When set, this transmission is based on stbc rates. +*/ + +#define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_STBC_LSB 38 +#define MACTX_PHY_DESC_STBC_MSB 38 +#define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 + + +/* Description DOT11AX_SU_EXTENDED + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be + + When set, the 11ax or 11be transmission is extended range + SU +*/ + +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 + + +/* Description DOT11AX_TRIGGER_FRAME_EMBEDDED + + When set, there is an 11ax trigger frame OR 11be trigger + frame embedded in this transmission. PHY shall latch the + transmit BW of this transmission and use it to select the + 'MACTX_UPLINK_COMMON/USER...' TLVs parameters belonging + to this BW. Note that these 'MACTX_UPLINK_COMMON/USER...' + might already have been received by the PHY, or will come + in later. + +*/ + +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 + + +/* Description TX_PWR_SHARED + + Transmit Power (signed value) in units of 0.25 dBm + +*/ + +#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 + + +/* Description TX_PWR_UNSHARED + + Transmit Power (signed value) in units of 0.25 dBm +*/ + +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 + + +/* Description MEASURE_POWER + + This field enables the TPC to use power measurement for + current packet in CLPC updates. + TPC will not latch power measurement + result for current packet + TPC will latch power measurement + result for current packet + +*/ + +#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 +#define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 +#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 + + +/* Description TPC_GLUT_SELF_CAL + + Setting related to transmit power control calibration. + +*/ + +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 + + +/* Description BACK_TO_BACK_TRANSMISSION_EXPECTED + + When set, the next transmission is expected to follow this + one in SIFS time (without any response reception in between). + + + For example used when transmitting beacons followed by the + broadcast or multicast frames + +*/ + +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 + + +/* Description HEAVY_CLIP_NSS + + Number of active spatial streams in current packet. This + parameter is used by the heavy clip function in the transmitter. + In case of MU PPDU, this is total Nss of all users. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 + + +/* Description TXBF_PER_PACKET_NO_CSD_NO_WALSH + + This is a global switch that is applied to beamformed packets + + + If set, no_csd and no_walsh is applied to steering packet. + +*/ + +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 + + +/* Description NDP + + When not "0", upcoming transmission is one of the indicated + NDP types. + + No NDP transmission + Beamforming NDP + 11az NDP (HE Ranging NDP) + Short TB (HE Feedback NDP) +*/ + +#define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_NDP_LSB 0 +#define MACTX_PHY_DESC_NDP_MSB 1 +#define MACTX_PHY_DESC_NDP_MASK 0x0000000000000003 + + +/* Description UL_FLAG + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be + + + Used for HE_SIGB + + + +*/ + +#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_UL_FLAG_LSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000004 + + +/* Description TRIGGERED + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be + + + Denotes whether it's a triggered uplink transmission + + Must be set for HE-TB NDPs used in Secure Ranging NDPs (11az) + and Short-NDP (HE TB Feedback NDP). + + + + +*/ + +#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_TRIGGERED_LSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000008 + + +/* Description AP_PKT_BW + + Field only valid when triggered == is_triggered + + This indicates the total bandwidth of the UL_TRIG packet + as indicated in the Trigger Frame. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 +#define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 +#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x0000000000000070 + + +/* Description RU_POSITION_START + + Field only valid when triggered == is_triggered + + + This field indicates the start basic (26 tone) RU number + assigned to this user + + RU Numbering is based only on the order in which the RUs + are allocated over the available BW, starting from 0 and + in increasing frequency order and not primary-secondary + order. + + The RU number within 80 MHz is available from the RU allocation + information in the trigger. For 160 MHz transmissions, + the trigger RU allocation only mentions primary/secondary + 80 MHz. PDG needs to convert this to lower/higher 80 MHz. + + + If in 'PCU_PPDU_SETUP_START'/'MACTX_PRE_PHY_DESC,' CCA_Subband_channel_bonding_mask + bit 0 is mapped to any of bits 4 - 7 of Freq_Subband_channel_bonding_mask, + then the primary 80 MHz is the higher 80 MHz and the secondary + 80 MHz is the lower one. + Otherwise (if CCA_Subband_channel_bonding_mask bit 0 is + mapped to any of bits 0 - 3 of Freq_Subband_channel_bonding_mask, + then the primary 80 MHz is the lower 80 MHz and the secondary + 80 MHz is the higher one. + + Note: this type of encoding decouples the formatting of + the trigger from from how info between MAC-PHY is exchanged + + +*/ + +#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 +#define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 +#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x0000000000007f80 + + +/* Description PCU_PPDU_SETUP_START_REASON + + PDG shall fill this with the value it fills in the setup_start_reason + in 'PCU_PPDU_SETUP_START.' It indicates what triggered + the PDG to start Tx setup. + Used for debugging purposes. + + RTS or CTS-to-self transmission + preceding the regular PPDU portion of the coming FES. The + transmit is initiated by PDG_TX_REQ TLV from TXPCU + Regular PPDU transmission + that follows the transmission of medium protection: Either + RTS - CTS exchanges or CTS to self. The transmit is initiated + by PDG_TX_REQ TLV from TXPCU + Regular PPDU transmission without + preceding medium protection frame exchanges. The transmit + is initiated by PDG_TX_REQ TLV from TXPCU + response frame transmission. + The transmit is initiated by PDG_RESPONSE TLV from TXPCU + + 11ax triggered response + frame transmission. The transmit is initiated by PDG_TRIG_RESPONSE + TLV from TXPCU + Regular PPDU transmission + without preceding medium protection frame exchanges, because + the dynamic medium protection constraints were not satisfied. + The transmit is initiated by PDG_TX_REQ TLV from TXPCU. + + +*/ + +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000038000 + + +/* Description TLV_SOURCE + + This MACTX_PHY_DESC TLV is generated + by PDG. + PDG is in bypass mode and this + MACTX_PHY_DESC TLV is queued by firmware. + +*/ + +#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000040000 + + +/* Description RESERVED_2A + + +*/ + +#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_2A_LSB 19 +#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 +#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000180000 + + +/* Description NSS + + Field only valid when triggered == is_triggered + + Number of Spatial Streams occupied by the User + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_NSS_LSB 21 +#define MACTX_PHY_DESC_NSS_MSB 23 +#define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 + + +/* Description STREAM_OFFSET + + Field only valid when triggered == is_triggered + + Specify Stream-offset of the user for HE_TB Ranging NDP + or Short-NDP + + Stream Offset from which the User occupies the Streams +*/ + +#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 +#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 +#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 + + +/* Description RESERVED_2B + + +*/ + +#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 +#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 +#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 + + +/* Description CLPC_ENABLE + + This field enables closed-loop TPC operation by enabling + CLPC adjustment of DAC gain for the next packet. + TPC error update disabled + TPC error will be applied to DAC gain + setting for the next packet + +*/ + +#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 + + +/* Description MU_NDP + + If set indicates that this packet is an NDP used for MU + channel estimation. This bit will be used by the TPC to + signal that the analog gain settings can be updated. The + analog gain settings will not change for subsequent MU + data packets. +*/ + +#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_MU_NDP_LSB 30 +#define MACTX_PHY_DESC_MU_NDP_MSB 30 +#define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 + + +/* Description RESPONSE_EXPECTED + + When set, a response frame in SIFS time is expected after + this transmission. + +*/ + +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 + + +/* Description RX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 + + +/* Description RX_CHAIN_MASK_VALID + + Indicates rx_chain_mask field is valid. + + + +*/ + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 + + +/* Description ANT_SEL_VALID + + Field only valid when ant_sel_valid is set. + + TX Antenna select valid + + + +*/ + +#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 + + +/* Description ANT_SEL + + Field only valid when ant_sel_valid is set. + + Antenna select for TX antenna diversity. + + + +*/ + +#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ANT_SEL_LSB 42 +#define MACTX_PHY_DESC_ANT_SEL_MSB 42 +#define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 + + +/* Description CP_SETTING + + Field only valid when pkt type is HT, VHT or HE. + + Specify the right CP for HE-Ranging NDPs (11az)/Short NDP + + + Legacy normal GI + Legacy short GI + HE related GI + HE related GI + +*/ + +#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_CP_SETTING_LSB 43 +#define MACTX_PHY_DESC_CP_SETTING_MSB 44 +#define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 + + +/* Description HE_PPDU_SUBTYPE + + The subtype of HE transmission: + + Specify as HE-SU for HE-SU Ranging NDP in 11az ; + Specify as HE-TB for HE-TB Ranging NDP in 11az ; + Specify as HE-TB for Short -NDP + Re-use the same for EHT PPDU types also + + + + + + +*/ + +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 + + +/* Description ACTIVE_CHANNEL + + Field only valid when triggered == non_trigerred + In case of a triggered response transmission, this field + will always be set to 0 + + This field indicates the active frequency band when the + packet bandwidth is less than the channel bandwidth. For + non 11ax packets this is same as the primary channel + +*/ + +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 + + +/* Description GENERATE_PHYRX_TX_START_TIMING + + When set, PHY shall generate the PHYRX_TX_START_TIMING TLV + at the earliest opportunity during the preamble transmission + + +*/ + +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 + + +/* Description LTF_SIZE + + Field only valid when pkt type is HE. + + Ltf size + + Specify right LTF-size for HE-Ranging NDPs (11az)/Short-NDP + + + + + + +*/ + +#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_LTF_SIZE_LSB 51 +#define MACTX_PHY_DESC_LTF_SIZE_MSB 52 +#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 + + +/* Description RU_SIZE_UPDATED_V2 + + Field only valid for pkt_type == 11ax or 11be and + SU_or_MU == SU_transmission or + SU_or_MU == MU_SU_transmission + + The RU size of the upcoming transmission. + + PHY uses this info to apply different min/max BO if payload + bandwidth is less than 10MHz + + In case of HE extended range transmission, e-num 2 (10MHz) + or e-num 7 (20MHz) are used. + + In case of trig transmission or OFDMA single user or MU-MIMO + single user transmission, if the ru_size allocated to the + user is the fullBW (with respect to AP_bw) ru size then + the e-num 7 is used. + For all other cases, e-nums corresponding to the ru size + allocated to the user is used. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + Set when the RU occupies the full packet + bandwidth + Note that for an MU-RTS trigger, the response will also + go out in legacy CTS rate... and thus e-num 7 will be used. + + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + + HW will use per-user sub-band-mask + to infer the actual RU-size for Multi-large-RU/SU-Puncturing + + + multi small RU + multi small RU + + + + NOTE: See the table following this TLV definition that explains + the relationship between this field and the RU size allocated + to users. + + +*/ + +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 + + +/* Description RESERVED_3C + + +*/ + +#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_3C_LSB 57 +#define MACTX_PHY_DESC_RESERVED_3C_MSB 57 +#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + Field only valid for pkt_type == 11be + + The 6-bit value to be used in U-SIG and/or EHT-SIG Common + field for the puncture pattern + +*/ + +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + + + +#endif // MACTX_PHY_DESC diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_service.h b/drivers/staging/fw-api/hw/qcn6432/mactx_service.h new file mode 100644 index 0000000000000000000000000000000000000000..ce6ccc53298782775e9faa82a7b6af9b3122af4a --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_service.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_SERVICE_H_ +#define _MACTX_SERVICE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "service_info.h" +#define NUM_OF_DWORDS_MACTX_SERVICE 2 + +#define NUM_OF_QWORDS_MACTX_SERVICE 1 + + +struct mactx_service { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct service_info mactx_service_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct service_info mactx_service_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_SERVICE_INFO_DETAILS + + See detailed description of the STRUCT. + + In case of EHT, instead of 'SERVICE_INFO' the STRUCT 'EHT_SERVICE_INFO' + is used. See detailed description of the STRUCT. +*/ + + +/* Description SCRAMBLER_SEED + + This field provides the 7-bit seed for the data scrambler. + +*/ + +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000000 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SCRAMBLER_SEED_LSB 0 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SCRAMBLER_SEED_MSB 6 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SCRAMBLER_SEED_MASK 0x000000000000007f + + +/* Description RESERVED + + Reserved. Set to 0 by sender and ignored by receiver. +*/ + +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_LSB 7 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_MSB 7 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_MASK 0x0000000000000080 + + +/* Description SIG_B_CRC_USER + + In case of vht transmission: vht_sig_b_crc_user + +*/ + +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SIG_B_CRC_USER_OFFSET 0x0000000000000000 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SIG_B_CRC_USER_LSB 8 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SIG_B_CRC_USER_MSB 15 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SIG_B_CRC_USER_MASK 0x000000000000ff00 + + +/* Description RESERVED_1 + + +*/ + +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_1_LSB 16 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_1_MSB 31 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_1_MASK 0x00000000ffff0000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_SERVICE_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_SERVICE_TLV64_PADDING_LSB 32 +#define MACTX_SERVICE_TLV64_PADDING_MSB 63 +#define MACTX_SERVICE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_SERVICE diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/qcn6432/mactx_u_sig_eht_su_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..a7c38a019f9146769bedfd579bec436da5482510 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_u_sig_eht_su_mu.h @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ +#define _MACTX_U_SIG_EHT_SU_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "u_sig_eht_su_mu_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 + +#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1 + + +struct mactx_u_sig_eht_su_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#else + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#endif +}; + + +/* Description MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description PHY_VERSION + + + Values 1 - 7 are reserved. + 20 MHz + 40 MHz + 80 MHz + 160 MHz + 320 MHz + DO NOT USE + + Microcode remaps 'U_SIG_BW320' based on channelization. + + On RX side, field used by MAC HW + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field used by MAC HW + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field used by MAC HW + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 + + +/* Description DISREGARD_0A + + Note: spec indicates this shall be set to 1s + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000 + + +/* Description VALIDATE_0B + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000 + + +/* Description RESERVED_0C + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 + + +/* Description EHT_PPDU_SIG_CMN_TYPE + + DO NOT USE + Need to look at both + EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO) + + Need to look at both EHT-SIG + content channels + Need to look at only one EHT-SIG + content channel + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 + + +/* Description VALIDATE_1A + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 + + +/* Description PUNCTURED_CHANNEL_INFORMATION + + For OFDMA BW 20 MHz or 40 MHz: + Set to all 1s, i.e. 31 + + For OFDMA of higher BW: + Bit 3 = lowest 20 MHz in the current 80 MHz + Bit 6 = highest 20 MHz in the current 80 MHz + Bit 7 = 1 + + Each bit indicates whether the 20 MHz is modulated or punctured + + 0 = punctured + 1 = modulated + + For non-OFDMA: + Set to a 5-bit value encoding the puncture pattern, a.k.a. 'U_sig_puncture_pattern_encoding' + elsewhere in the data structures + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000 + + +/* Description VALIDATE_1B + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000 + + +/* Description MCS_OF_EHT_SIG + + Indicates the MCS of EHT-SIG + 0 - 1: MCS 0 - 1 + 2: MCS 3 + 3: MCS 0 with DCM + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000 + + +/* Description NUM_EHT_SIG_SYMBOLS + + Number of symbols + + The actual number of symbols is 1 larger than indicated + in this field. + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000 + + +/* Description CRC + + CRC for U-SIG contents + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description DOT11AX_SU_EXTENDED + + TX side: + Set to 0 + + RX side: On RX side, evaluated by MAC HW + + This is the only way for MAC RX to know that this was a + U_SIG_EHT_SU received in extended range format. + + When set, the 11be frame is of the extended range format. + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + + +/* Description RESERVED_1D + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000 + + +/* Description RX_NDP + + TX side: + Set to 0 + + RX side: On RX side, looked at by MAC HW + + When set, PHY has received an (expected) NDP frame + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the U-SIG CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_U_SIG_EHT_SU_MU diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/qcn6432/mactx_u_sig_eht_tb.h new file mode 100644 index 0000000000000000000000000000000000000000..c43f75737aa354b861b29595ce8d6c2336898055 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_u_sig_eht_tb.h @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_U_SIG_EHT_TB_H_ +#define _MACTX_U_SIG_EHT_TB_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "u_sig_eht_tb_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 + +#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1 + + +struct mactx_u_sig_eht_tb { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#else + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#endif +}; + + +/* Description MACTX_U_SIG_EHT_TB_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description PHY_VERSION + + + Values 1 - 7 are reserved. + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU, as indicated in the trigger frame + + + 20 MHz + 40 MHz + 80 MHz + 160 MHz + 320 MHz channelization scheme 1 + 320 MHz channelization scheme 2 + + On RX side, field used by MAC HW + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field used by MAC HW + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field used by MAC HW + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 + + +/* Description DISREGARD_0A + + Set to value indicated in the trigger frame + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000 + + +/* Description RESERVED_0C + + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 + + +/* Description EHT_PPDU_SIG_CMN_TYPE + + DO NOT USE + Need to look at both + EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO) + + Need to look at both EHT-SIG + content channels + Need to look at only one EHT-SIG + content channel + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 + + +/* Description VALIDATE_1A + + Set to value indicated in the trigger frame + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 + + +/* Description SPATIAL_REUSE + + TODO: Placeholder + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000 + + +/* Description DISREGARD_1B + + Set to value indicated in the trigger frame + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000 + + +/* Description CRC + + CRC for U-SIG contents + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description RESERVED_1C + + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the U-SIG CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_U_SIG_EHT_TB diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/qcn6432/mactx_user_desc_common.h new file mode 100644 index 0000000000000000000000000000000000000000..64ebb492fc6b3633be73583804d9e151fd325710 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_user_desc_common.h @@ -0,0 +1,1305 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_USER_DESC_COMMON_H_ +#define _MACTX_USER_DESC_COMMON_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "unallocated_ru_160_info.h" +#include "ru_allocation_160_info.h" +#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 + +#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 + + +struct mactx_user_desc_common { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, // [5:0] + reserved_0b : 5, // [10:6] + ltf_size : 2, // [12:11] + reserved_0c : 3, // [15:13] + he_stf_long : 1, // [16:16] + reserved_0d : 7, // [23:17] + num_users_he_sigb_band0 : 8; // [31:24] + uint32_t num_ltf_symbols : 3, // [2:0] + reserved_1a : 5, // [7:3] + num_users_he_sigb_band1 : 8, // [15:8] + reserved_1b : 16; // [31:16] + uint32_t packet_extension_a_factor : 2, // [1:0] + packet_extension_pe_disambiguity : 1, // [2:2] + packet_extension : 3, // [5:3] + reserved : 2, // [7:6] + he_sigb_dcm : 1, // [8:8] + reserved_2b : 7, // [15:9] + he_sigb_compression : 1, // [16:16] + reserved_2c : 15; // [31:17] + uint32_t he_sigb_0_mcs : 3, // [2:0] + reserved_3a : 13, // [15:3] + num_he_sigb_sym : 5, // [20:16] + center_ru_0 : 1, // [21:21] + center_ru_1 : 1, // [22:22] + reserved_3b : 1, // [23:23] + ftm_en : 1, // [24:24] + pe_nss : 3, // [27:25] + pe_ltf_size : 2, // [29:28] + pe_content : 1, // [30:30] + pe_chain_csd_en : 1; // [31:31] + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t num_data_symbols : 16, // [15:0] + ndp_ru_tone_set_index : 7, // [22:16] + ndp_feedback_status : 1, // [23:23] + doppler_indication : 1, // [24:24] + reserved_14a : 7; // [31:25] + uint32_t spatial_reuse : 16, // [15:0] + reserved_15a : 16; // [31:16] +#else + uint32_t num_users_he_sigb_band0 : 8, // [31:24] + reserved_0d : 7, // [23:17] + he_stf_long : 1, // [16:16] + reserved_0c : 3, // [15:13] + ltf_size : 2, // [12:11] + reserved_0b : 5, // [10:6] + num_users : 6; // [5:0] + uint32_t reserved_1b : 16, // [31:16] + num_users_he_sigb_band1 : 8, // [15:8] + reserved_1a : 5, // [7:3] + num_ltf_symbols : 3; // [2:0] + uint32_t reserved_2c : 15, // [31:17] + he_sigb_compression : 1, // [16:16] + reserved_2b : 7, // [15:9] + he_sigb_dcm : 1, // [8:8] + reserved : 2, // [7:6] + packet_extension : 3, // [5:3] + packet_extension_pe_disambiguity : 1, // [2:2] + packet_extension_a_factor : 2; // [1:0] + uint32_t pe_chain_csd_en : 1, // [31:31] + pe_content : 1, // [30:30] + pe_ltf_size : 2, // [29:28] + pe_nss : 3, // [27:25] + ftm_en : 1, // [24:24] + reserved_3b : 1, // [23:23] + center_ru_1 : 1, // [22:22] + center_ru_0 : 1, // [21:21] + num_he_sigb_sym : 5, // [20:16] + reserved_3a : 13, // [15:3] + he_sigb_0_mcs : 3; // [2:0] + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t reserved_14a : 7, // [31:25] + doppler_indication : 1, // [24:24] + ndp_feedback_status : 1, // [23:23] + ndp_ru_tone_set_index : 7, // [22:16] + num_data_symbols : 16; // [15:0] + uint32_t reserved_15a : 16, // [31:16] + spatial_reuse : 16; // [15:0] +#endif +}; + + +/* Description NUM_USERS + + The number of users in this transmission + + Use this same field for HE-ranging NDP as well. + +*/ + +#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f + + +/* Description RESERVED_0B + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 + + +/* Description LTF_SIZE + + Ltf size + + Specify the right LTF-size for HE-Ranging NDPs (11az)/Short-NDP. + + + + + + +*/ + +#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 + + +/* Description RESERVED_0C + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 + + +/* Description HE_STF_LONG + + 0: Normal HE STF. + 1: Long HE STF + + Specify the right STF-size for HE-Ranging NDPs (11az)/Short-NDP. + + + +*/ + +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 + + +/* Description RESERVED_0D + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 + + +/* Description NUM_USERS_HE_SIGB_BAND0 + + number of users in HE_SIGB_0 or EHT_SIG_0 + + Note for MAC: + directly from pdg_fes_setup, based on BW + +*/ + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 + + +/* Description NUM_LTF_SYMBOLS + + Indicates the number of HE-LTF symbols + + 0: 1 symbol + 1: 2 symbols + 2: 3 symbols + 3: 4 symbols + 4: 5 symbols + 5: 6 symbols + 6: 7 symbols + 7: 8 symbols + + NOTE that this encoding is different from what is in "Num_LTF_symbols" + in the HE_SIG_A_MU_DL. + + NOTE 2: Not used for HE-Ranging NDPs (11az) + +*/ + +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 + + +/* Description RESERVED_1A + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 + + +/* Description NUM_USERS_HE_SIGB_BAND1 + + number of users in HE_SIGB_1 or EHT_SIG_1 + + Note for MAC: + directly from pdg_fes_setup, based on BW + For 20Mhz transmission, this is set to 0 + +*/ + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 + + +/* Description RESERVED_1B + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 + + +/* Description PACKET_EXTENSION + + Packet extension size + + Specify the right packet extension size for HE-Ranging NDPs + (11az)/Short-NDP. + + + + + + + +*/ + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 + + +/* Description RESERVED + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 +#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to HE-SIG-B or EHT-SIG + +*/ + +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 + + +/* Description RESERVED_2B + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 + + +/* Description HE_SIGB_COMPRESSION + + Indicates the compression mode of HE-SIG-B or EHT-SIG + +*/ + +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 + + +/* Description RESERVED_2C + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 + + +/* Description HE_SIGB_0_MCS + + Note: stbc setting is indicated in the MACTX_PHY_DESC. + + Indicates the MCS of HE-SIG-B or EHT-SIG. + + For details, refer to MCS_TYPE description + +*/ + +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 + + +/* Description RESERVED_3A + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 + + +/* Description NUM_HE_SIGB_SYM + + This field is valid only when (MACTX_PHY_DESC.pkt_type==11ax + or MACTX_PHY_DESC.pkt_type == 11be) + + Indicates the number of HE-SIG-B or EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 he_sigb/eht_sig + symbol needs to be transmitted + +*/ + +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 + + +/* Description CENTER_RU_0 + + Field only valid for 11ax transmission with a BW of 80Mhz + or 160 Mhz + + Indicates whether the Center RU is occupied in the lower + 80 MHz band. This is part of HE_SIGB content channel 1 + + 0: center RU is NOT used + 1: center RU is used + + NOTE: EHT is not expected to use the center RU. + + +*/ + +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 + + +/* Description CENTER_RU_1 + + Field only valid for 11ax transmission with a BW of 160 + Mhz (or 80 + 80) + + Indicates whether the Center RU is occupied in the upper + 80 MHz band. This is part of HE_SIGB content channel 1 + + 0: center RU is NOT used + 1: center RU is used + + NOTE: EHT is not expected to use the center RU. + + +*/ + +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 + + +/* Description RESERVED_3B + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 + + +/* Description FTM_EN + + This field is set to 1 if the present packet is either an + FTM_1 or an FTM_2 packet or an HE-Ranging NDP (11az). + + 0: non-FTM frame + 1: FTM or HE-Ranging NDP Frame + +*/ + +#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 +#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 +#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 + + +/* Description PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 +#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 +#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 + + +/* Description PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 + + +/* Description PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 + + +/* Description PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 + + +/* Description RU_ALLOCATION_0123_DETAILS + + See detailed description of the STRUCT. +*/ + + +/* Description RU_ALLOCATION_BAND0_0 + + Field not used for MIMO + + Indicates RU arrangement in frequency domain. RU allocated + for MU-MIMO, and number of users in the MU-MIMO. + 0 - valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 + 1 - valid for HE_80/HE_160 (80+80)/ EHT_80/EHT_160/EHT_240/EHT_320 + + 2 - valid for HE_160 (80+80)/ EHT_160/EHT_240/EHT_320 + 3 - valid for HE_160 (80+80)/ EHT_160/EHT_240/EHT_320 + + The four bands are for HE_SIGB0 & B1 respectively or for + EHT_SIG0, EHT_SIG1, EHT_SIG2 & EHT_SIG3 respectively. + + valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 packets and denotes RU-map of the first + 20MHz band of HE_SIGB0 or EHT_SIG0 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff + + +/* Description RU_ALLOCATION_BAND0_1 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_80/HE_160/ EHT_80/EHT_160/EHT_240/EHT_320 packets + and denotes RU-map of the second 20MHz band of HE_SIGB0 + or EHT_SIG0 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 + + +/* Description RU_ALLOCATIONS_01_SUBBAND80_MASK + + Field not used for HE + + Indicates what 80 MHz subbands 'ru_allocation_band{0, 1}_{0, + 1}' are valid for + Bit 0: lowest 80 MHz + Bit 1: 2nd lowest 80 MHz + Bit 2: 2nd highest 80 MHz + Bit 3: highest 80 MHz + + In other 80 MHz subbands PHY microcode should override these + with 'zero-user RU996.' + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 + + +/* Description RU_ALLOCATIONS_23_SUBBAND80_MASK + + Field not used for HE + + Indicates what 80 MHz subbands 'ru_allocation_band{0, 1}_{2, + 3}' are valid for + Bit 0: lowest 80 MHz + Bit 1: 2nd lowest 80 MHz + Bit 2: 2nd highest 80 MHz + Bit 3: highest 80 MHz + + In other 80 MHz subbands PHY microcode should override these + with 'zero-user RU996.' + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 + + +/* Description RU_ALLOCATION_BAND0_2 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the third 20MHz band of HE_SIGB0 or EHT_SIG0 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 + + +/* Description RU_ALLOCATION_BAND0_3 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the fourth 20MHz band of HE_SIGB0 or EHT_SIG0 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 + + +/* Description RU_ALLOCATION_BAND1_0 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_40/HE_80/HE_160/ EHT_40/EHT_80/EHT_160/ EHT_240/EHT_320 + packets and denotes RU-map of the first 20MHz band of HE_SIGB1 + or EHT_SIG1 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff + + +/* Description RU_ALLOCATION_BAND1_1 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_80/HE_160/ EHT_80/EHT_160/EHT_240/EHT_320 packets + and denotes RU-map of the second 20MHz band of HE_SIGB1 + or EHT_SIG1 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 + + +/* Description RESERVED_2A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 + + +/* Description RU_ALLOCATION_BAND1_2 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the third 20MHz band of HE_SIGB1 or EHT_SIG1 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 + + +/* Description RU_ALLOCATION_BAND1_3 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the fourth 20MHz band of HE_SIGB1 or EHT_SIG1 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 + + +/* Description RESERVED_3A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 + + +/* Description RU_ALLOCATION_4567_DETAILS + + See detailed description of the STRUCT. + + Valid for EHT_240/EHT_320 packets and denotes RU-map of + the fifth/sixth/sevent/eighth 20MHz bands of EHT_SIG0/EHT_SIG1 + +*/ + + +/* Description RU_ALLOCATION_BAND0_0 + + Field not used for MIMO + + Indicates RU arrangement in frequency domain. RU allocated + for MU-MIMO, and number of users in the MU-MIMO. + 0 - valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 + 1 - valid for HE_80/HE_160 (80+80)/ EHT_80/EHT_160/EHT_240/EHT_320 + + 2 - valid for HE_160 (80+80)/ EHT_160/EHT_240/EHT_320 + 3 - valid for HE_160 (80+80)/ EHT_160/EHT_240/EHT_320 + + The four bands are for HE_SIGB0 & B1 respectively or for + EHT_SIG0, EHT_SIG1, EHT_SIG2 & EHT_SIG3 respectively. + + valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 packets and denotes RU-map of the first + 20MHz band of HE_SIGB0 or EHT_SIG0 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff + + +/* Description RU_ALLOCATION_BAND0_1 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_80/HE_160/ EHT_80/EHT_160/EHT_240/EHT_320 packets + and denotes RU-map of the second 20MHz band of HE_SIGB0 + or EHT_SIG0 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 + + +/* Description RU_ALLOCATIONS_01_SUBBAND80_MASK + + Field not used for HE + + Indicates what 80 MHz subbands 'ru_allocation_band{0, 1}_{0, + 1}' are valid for + Bit 0: lowest 80 MHz + Bit 1: 2nd lowest 80 MHz + Bit 2: 2nd highest 80 MHz + Bit 3: highest 80 MHz + + In other 80 MHz subbands PHY microcode should override these + with 'zero-user RU996.' + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 + + +/* Description RU_ALLOCATIONS_23_SUBBAND80_MASK + + Field not used for HE + + Indicates what 80 MHz subbands 'ru_allocation_band{0, 1}_{2, + 3}' are valid for + Bit 0: lowest 80 MHz + Bit 1: 2nd lowest 80 MHz + Bit 2: 2nd highest 80 MHz + Bit 3: highest 80 MHz + + In other 80 MHz subbands PHY microcode should override these + with 'zero-user RU996.' + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 + + +/* Description RU_ALLOCATION_BAND0_2 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the third 20MHz band of HE_SIGB0 or EHT_SIG0 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 + + +/* Description RU_ALLOCATION_BAND0_3 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the fourth 20MHz band of HE_SIGB0 or EHT_SIG0 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 + + +/* Description RU_ALLOCATION_BAND1_0 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_40/HE_80/HE_160/ EHT_40/EHT_80/EHT_160/ EHT_240/EHT_320 + packets and denotes RU-map of the first 20MHz band of HE_SIGB1 + or EHT_SIG1 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff + + +/* Description RU_ALLOCATION_BAND1_1 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_80/HE_160/ EHT_80/EHT_160/EHT_240/EHT_320 packets + and denotes RU-map of the second 20MHz band of HE_SIGB1 + or EHT_SIG1 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 + + +/* Description RESERVED_2A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 + + +/* Description RU_ALLOCATION_BAND1_2 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the third 20MHz band of HE_SIGB1 or EHT_SIG1 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 + + +/* Description RU_ALLOCATION_BAND1_3 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the fourth 20MHz band of HE_SIGB1 or EHT_SIG1 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 + + +/* Description RESERVED_3A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 + + +/* Description RU_ALLOCATION_160_0_DETAILS + + See detailed description of the STRUCT. +*/ + + +/* Description SUBBAND80_0_CC0 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 0 (HE_SIGB0 or EHT_SIG0) + for the lower 80 MHz + + Valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff + + +/* Description SUBBAND80_0_CC1 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 1 (HE_SIGB1 or EHT_SIG1) + for the lower 80 MHz + + Valid for HE_40/HE_80/HE_160 (80+80)/ EHT_40/EHT_80/EHT_160/EHT_240/EHT_320 + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 + + +/* Description SUBBAND80_1_CC0 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 0 (HE_SIGB0 or EHT_SIG0) + for the higher 80 MHz + + Valid for EHT_160/EHT_240/EHT_320 + All 80 MHz subbands are identical for HE_160 (80+80). + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 + + +/* Description SUBBAND80_1_CC1 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 1 (HE_SIGB1 or EHT_SIG1) + for the higher 80 MHz + + Valid for EHT_160/EHT_240/EHT_320 + All 80 MHz subbands are identical for HE_160 (80+80). + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 + + +/* Description RU_ALLOCATION_160_1_DETAILS + + See detailed description of the STRUCT. + + Valid for EHT_240/EHT_320 +*/ + + +/* Description SUBBAND80_0_CC0 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 0 (HE_SIGB0 or EHT_SIG0) + for the lower 80 MHz + + Valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 + + +/* Description SUBBAND80_0_CC1 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 1 (HE_SIGB1 or EHT_SIG1) + for the lower 80 MHz + + Valid for HE_40/HE_80/HE_160 (80+80)/ EHT_40/EHT_80/EHT_160/EHT_240/EHT_320 + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 + + +/* Description SUBBAND80_1_CC0 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 0 (HE_SIGB0 or EHT_SIG0) + for the higher 80 MHz + + Valid for EHT_160/EHT_240/EHT_320 + All 80 MHz subbands are identical for HE_160 (80+80). + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 + + +/* Description SUBBAND80_1_CC1 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 1 (HE_SIGB1 or EHT_SIG1) + for the higher 80 MHz + + Valid for EHT_160/EHT_240/EHT_320 + All 80 MHz subbands are identical for HE_160 (80+80). + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 + + +/* Description NUM_DATA_SYMBOLS + + The number of data symbols in the upcoming transmission. + + + This does not include PE_LTF. Also for STBC packets this + has to be an even number. + +*/ + +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff + + +/* Description NDP_RU_TONE_SET_INDEX + + Determines the RU tone set (1 - 72) to use for Short-NDP + feedback + + Can be set to 0 for frames other than Short-NDP + +*/ + +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 + + +/* Description NDP_FEEDBACK_STATUS + + Determines the feedback value for Short-NDP + +*/ + +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 + + +/* Description DOPPLER_INDICATION + + This field is valid only when (MACTX_PHY_DESC.pkt_type==11ax + or MACTX_PHY_DESC.pkt_type == 11be). + + +*/ + +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 + + +/* Description RESERVED_14A + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 + + +/* Description SPATIAL_REUSE + + This field is valid only when (MACTX_PHY_DESC.pkt_type==11ax + or MACTX_PHY_DESC.pkt_type == 11be) + + For an HE TB PPDU all 16 bits are valid. + For an EHT TB PPDU LSB 8 bits are valid. + For any other HE/EHT PPDU LSB 4 bits are valid. + + +*/ + +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 + + +/* Description RESERVED_15A + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 48 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff000000000000 + + + +#endif // MACTX_USER_DESC_COMMON diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/qcn6432/mactx_user_desc_per_user.h new file mode 100644 index 0000000000000000000000000000000000000000..a75f833f00080762b27d82dc14b21b7b68cd65ef --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_user_desc_per_user.h @@ -0,0 +1,473 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_USER_DESC_PER_USER_H_ +#define _MACTX_USER_DESC_PER_USER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4 + +#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 2 + + +struct mactx_user_desc_per_user { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t psdu_length : 24, // [23:0] + reserved_0a : 8; // [31:24] + uint32_t ru_start_index : 8, // [7:0] + ru_size : 4, // [11:8] + reserved_1b : 4, // [15:12] + ofdma_mu_mimo_enabled : 1, // [16:16] + nss : 3, // [19:17] + stream_offset : 3, // [22:20] + reserved_1c : 1, // [23:23] + mcs : 4, // [27:24] + dcm : 1, // [28:28] + reserved_1d : 3; // [31:29] + uint32_t fec_type : 1, // [0:0] + reserved_2a : 7, // [7:1] + user_bf_type : 2, // [9:8] + reserved_2b : 6, // [15:10] + drop_user_cbf : 1, // [16:16] + reserved_2c : 7, // [23:17] + ldpc_extra_symbol : 1, // [24:24] + force_extra_symbol : 1, // [25:25] + reserved_2d : 6; // [31:26] + uint32_t sw_peer_id : 16, // [15:0] + per_user_subband_mask : 16; // [31:16] +#else + uint32_t reserved_0a : 8, // [31:24] + psdu_length : 24; // [23:0] + uint32_t reserved_1d : 3, // [31:29] + dcm : 1, // [28:28] + mcs : 4, // [27:24] + reserved_1c : 1, // [23:23] + stream_offset : 3, // [22:20] + nss : 3, // [19:17] + ofdma_mu_mimo_enabled : 1, // [16:16] + reserved_1b : 4, // [15:12] + ru_size : 4, // [11:8] + ru_start_index : 8; // [7:0] + uint32_t reserved_2d : 6, // [31:26] + force_extra_symbol : 1, // [25:25] + ldpc_extra_symbol : 1, // [24:24] + reserved_2c : 7, // [23:17] + drop_user_cbf : 1, // [16:16] + reserved_2b : 6, // [15:10] + user_bf_type : 2, // [9:8] + reserved_2a : 7, // [7:1] + fec_type : 1; // [0:0] + uint32_t per_user_subband_mask : 16, // [31:16] + sw_peer_id : 16; // [15:0] +#endif +}; + + +/* Description PSDU_LENGTH + + PSDU Length for the User in octets + NOTE: This also holds good for .11ba packets + +*/ + +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000 + + +/* Description RU_START_INDEX + + Field only valid in case of .11ax or .11be OFDMA transmission + (=> from MACTX_PHY_DESC, field MU_type == OFDMA) + OR + 11ax SU "Narrow band" transmission. + + RU Number to which User is assigned + RU numbering is over the entire BW, starting from 0 and + for the different users in increasing frequency order and + not primary-secondary order. + + For DL OFDMA transmissions, PDG shall fill this as instructed + by SW. + + For UL OFDMA transmissions, the RU number within 80 MHz + is available from the RU allocation information in the trigger. + For 160 MHz UL OFDMA transmissions, the trigger RU allocation + only mentions primary/secondary 80 MHz. PDG needs to convert + this to lower/higher 80 MHz. + + If in 'PCU_PPDU_SETUP_START'/'MACTX_PRE_PHY_DESC,' CCA_Subband_channel_bonding_mask + bit 0 is mapped to any of bits 4 - 7 of Freq_Subband_channel_bonding_mask, + then the primary 80 MHz is the higher 80 MHz and the secondary + 80 MHz is the lower one. + Otherwise (if CCA_Subband_channel_bonding_mask bit 0 is + mapped to any of bits 0 - 3 of Freq_Subband_channel_bonding_mask, + then the primary 80 MHz is the lower 80 MHz and the secondary + 80 MHz is the higher one. + + +*/ + +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000 + + +/* Description RU_SIZE + + The size of the RU for this user + + In case of HE extended range transmission, e-num 2 (10MHz) + or e-num 7 (20MHz) are used. + + In case of trig transmission or OFDMA single user or MU-MIMO + single user transmission, if the RU allocated to the user + is the full BW (with respect to AP_bw) then the e-num 7 + is used. + For all other cases, e-nums corresponding to the RU size + allocated to the user is used. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + HW will use per-user sub-band-mask + to infer the actual RU-size for Multi-large-RU/SU-Puncturing + + multi small RU + multi small RU +*/ + +#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000 + + +/* Description RESERVED_1B + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000 + + +/* Description OFDMA_MU_MIMO_ENABLED + + Field only valid in case of .11ax or .11be OFDMA transmission + (=> from MACTX_PHY_DESC, field MU_type == OFDMA) + + When set, for this user there is MIMO transmission within + the RU + +*/ + +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000 + + +/* Description NSS + + Number of Spatial Streams occupied by the User + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_NSS_LSB 49 +#define MACTX_USER_DESC_PER_USER_NSS_MSB 51 +#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000 + + +/* Description STREAM_OFFSET + + Field only valid in case of MU-MIMO transmission (=> from + MACTX_PHY_DESC, field MU_type == MU-MIMO) + OR + when field Ofdma_mu_mimo_enabled is set + + Stream Offset from which the User occupies the Streams + + Note MAC: + directly from pdg_fes_setup, based on BW + +*/ + +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000 + + +/* Description RESERVED_1C + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000 + + +/* Description MCS + + Modulation Coding Scheme for the User + + The MCS to be used for the upcoming transmission. It must + match the 4-bit MCS value that is sent in the appropriate + signal field for the given packet type, except that EHT + BPSK with DCM and/or duplicate is encoded as '0.' + + + For details, refer to the SIG field, related to this pkt_type. + + (Note that this is slightly different then what is on the + MAC side defined as "MCS_TYPE". For this reason, the 'legal + values' here are NOT defined as MCS_TYPE) + +*/ + +#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_MCS_LSB 56 +#define MACTX_USER_DESC_PER_USER_MCS_MSB 59 +#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f00000000000000 + + +/* Description DCM + + Field only valid in case of 11ax transmission + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_DCM_LSB 60 +#define MACTX_USER_DESC_PER_USER_DCM_MSB 60 +#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x1000000000000000 + + +/* Description RESERVED_1D + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 61 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe000000000000000 + + +/* Description FEC_TYPE + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001 + + +/* Description RESERVED_2A + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x00000000000000fe + + +/* Description USER_BF_TYPE + + This field is valid for all packets using multiple antennas + because it defines whether the user's tones will be beamformed, + spatially spread, both or none of the above. + + Direct mapping from Stream to Chain + + Enable Walsh mapping only + Enable Beamforming only + Enable Walsh and Beamforming + + + NOTE: USER_NO_BF and USER_BF_ONLY are not allowed if the + number of spatial streams (NSS) < the number of Tx chains + (NTx). + +*/ + +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300 + + +/* Description RESERVED_2B + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x000000000000fc00 + + +/* Description DROP_USER_CBF + + This user shall be dropped because of CBF FCS failure or + no CBF reception. + +*/ + +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000 + + +/* Description RESERVED_2C + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x0000000000fe0000 + + +/* Description LDPC_EXTRA_SYMBOL + + Set to 1 if the LDPC PPDU encoding process (if an SU PPDU), + or at least one LDPC user's PPDU encoding process (if an + MU PPDU), results in an extra OFDM symbol (or symbols) + as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 + (Encoding process for MU PPDUs). Set to 0 otherwise. + +*/ + +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if none of the users' PPDU encoding process resuls in an + extra OFDM symbol (or symbols). + +*/ + +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000 + + +/* Description RESERVED_2D + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000fc000000 + + +/* Description SW_PEER_ID + + When set to 0, SW did not populate this field. + + The SW peer ID for this user + +*/ + +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000 + + +/* Description PER_USER_SUBBAND_MASK + + This specifies a per-20 MHz (frequency order) subband mask + per-user to be used in case of either multi-large-RU or + preamble puncturing. + +*/ + +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000 + + + +#endif // MACTX_USER_DESC_PER_USER diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_a.h new file mode 100644 index 0000000000000000000000000000000000000000..40f09e76dd2126af0ce3971d429d70d16184334f --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_a.h @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_A_H_ +#define _MACTX_VHT_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1 + + +struct mactx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#else + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_A_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description BANDWIDTH + + Packet bandwidth + + + + + + + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 + + +/* Description VHTA_RESERVED_0 + + Reserved. Set to 1 by MAC, PHY should ignore + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 + + +/* Description STBC + + Space time block coding: + Indicates STBC is disabled + Indicates STBC is enabled on + all streams + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 + + +/* Description GROUP_ID + + In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed + to an AP or to a mesh STA, the Group ID field is set to + 0, otherwise it is set to 63. In an NDP PPDU the Group + ID is set according to IEEE 802.11ac_D1.0 Section 9.30.6 + (Transmission of a VHT NDP). For a MU-MIMO PPDU the Group + ID is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group + ID). +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 + + +/* Description N_STS + + For MU: + 3 bits/user with maximum of 4 users (user u uses + vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2, + 3) + Set to 0 for 0 space time streams + Set to 1 for 1 space time stream + Set to 2 for 2 space time streams + Set to 3 for 3 space time streams + Set to 4 for 4 space time streams (not supported in Wifi + 3.0) + Values 5-7 are reserved + In this field, references to user "u" should be interpreted + as MU user "u". As described in the previous chapter in + this document (see chapter on User number), the MU user + value for a given client is defined for each MU group that + the client participates in. The MU user number is not related + to the internal user number that is used within the BFer. + + + + For SU: + vht_sig_a[0][12:10] + Set to 0 for 1 space time stream + Set to 1 for 2 space time streams + Set to 2 for 3 space time streams + Set to 3 for 4 space time streams + Set to 4 for 5 space time streams + Set to 5 for 6 space time streams + Set to 6 for 7 space time streams + Set to 7 for 8 space time streams + + vht_sig_a[0][21:13] + Partial AID: + Set to the value of the TXVECTOR parameter PARTIAL_AID. + Partial AID provides an abbreviated indication of the intended + recipient(s) of the frame (see IEEE802.11ac_D1.0 Section + 9.17a (Partial AID in VHT PPDUs)). + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 + + +/* Description TXOP_PS_NOT_ALLOWED + + E_num 0 txop_ps_allowed Not supported: If set to by + VHT AP if it allows non-AP VHT STAs in TXOP power save + mode to enter Doze state during a TXOP + Otherwise + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 + + +/* Description VHTA_RESERVED_0B + + Reserved: Should be set to 1 by the MAC and ignored by the + PHY +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 + + +/* Description RESERVED_0 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + + +/* Description GI_SETTING + + Indicates short guard interval is + not used in the data field + Indicates short guard interval is + used in the data field + Indicates short guard interval + is used in the data field and NSYM mod 10 = 9 + NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3 (TXTIME + and PSDU_LENGTH calculation). + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 + + +/* Description SU_MU_CODING + + For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For an + MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then + B2 indicates the coding used for user 0; set to 0 for BCC + and 1 for LDPC. If the MU[0] NSTS field is 0, then this + field is reserved and set to 1 +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 + + +/* Description LDPC_EXTRA_SYMBOL + + Set to 1 if the LDPC PPDU encoding process (if an SU PPDU), + or at least one LDPC user's PPDU encoding process (if an + MU PPDU), results in an extra OFDM symbol (or symbols) + as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 + (Encoding process for MU PPDUs). Set to 0 otherwise. +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 + + +/* Description MCS + + For SU: + Set to 0 for BPSK 1/2 + Set to 1 for QPSK 1/2 + Set to 2 for QPSK 3/4 + Set to 3 for 16-QAM 1/2 + Set to 4 for 16-QAM 3/4 + Set to 5 for 64-QAM 2/3 + Set to 6 for 64-QAM 3/4 + Set to 7 for 64-QAM 5/6 + Set to 8 for 256-QAM 3/4 + Set to 9 for 256-QAM 5/6 + For MU: + If NSTS for user 1 is non-zero, then vht_sig_a[1][4] indicates + coding for user 1: set to 0 for BCC, 1 for LDPC. + If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is + reserved and set to 1. + If NSTS for user 2 is non-zero, then vht_sig_a[1][5] indicates + coding for user 2: set to 0 for BCC, 1 for LDPC. + If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is + reserved and set to 1. + If NSTS for user 3 is non-zero, then vht_sig_a[1][6] indicates + coding for user 3: set to 0 for BCC, 1 for LDPC. + If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is + reserved and set to 1. + vht_sig_a[1][7] is reserved and set to 1 + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 + + +/* Description BEAMFORMED + + For SU: + Set to 1 if a Beamforming steering matrix is applied to + the waveform in an SU transmission as described in IEEE802.11ac_D1.0 + Section 19.3.11.11.2 (Spatial mapping), set to 0 otherwise. + + For MU: + Reserved and set to 1 + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 + + +/* Description VHTA_RESERVED_1 + + Reserved and set to 1. +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 + + +/* Description CRC + + CRC calculated as in IEEE802.11ac_D1.0 Section 19.3.9.4.4 + (CRC calculation for HTSIG) with C7 in vht_sig_a[1][10], + etc. +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + Set to 0. +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 + + +/* Description RESERVED_1 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the VHT-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_VHT_SIG_A diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_mu160.h new file mode 100644 index 0000000000000000000000000000000000000000..77917cbf0878d44af2732694059d8d0a7bb3f955 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_mu160.h @@ -0,0 +1,437 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_MU160_H_ +#define _MACTX_VHT_SIG_B_MU160_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4 + + +struct mactx_vht_sig_b_mu160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#else + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_B_MU160_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY_A + + Same as "length". This field is not valid for RX packets + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 + + +/* Description MCS_COPY_A + + Same as "mcs". This field is not valid for RX packets +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 + + +/* Description TAIL_COPY_A + + Same as "tail". This field is not valid for RX packets +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + + +/* Description RESERVED_1 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 + + +/* Description LENGTH_COPY_B + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff + + +/* Description MCS_COPY_B + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 + + +/* Description TAIL_COPY_B + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + + +/* Description RESERVED_2 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY_C + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 + + +/* Description MCS_COPY_C + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 + + +/* Description TAIL_COPY_C + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + + +/* Description RESERVED_3 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 + + +/* Description LENGTH_COPY_D + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff + + +/* Description MCS_COPY_D + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000 + + +/* Description TAIL_COPY_D + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 + + +/* Description RESERVED_4 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY_E + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000 + + +/* Description MCS_COPY_E + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000 + + +/* Description TAIL_COPY_E + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 + + +/* Description RESERVED_5 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000 + + +/* Description LENGTH_COPY_F + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff + + +/* Description MCS_COPY_F + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000 + + +/* Description TAIL_COPY_F + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY_G + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000 + + +/* Description MCS_COPY_G + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000 + + +/* Description TAIL_COPY_G + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 + + +/* Description RESERVED_7 + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000 + + + +#endif // MACTX_VHT_SIG_B_MU160 diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_mu20.h new file mode 100644 index 0000000000000000000000000000000000000000..1607f282e09cb76b89166e1fe902e0c3e6e3cf22 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_mu20.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_MU20_H_ +#define _MACTX_VHT_SIG_B_MU20_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1 + + +struct mactx_vht_sig_b_mu20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_VHT_SIG_B_MU20_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + +*/ + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. + +*/ + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000 + + +/* Description RESERVED_0 + + +*/ + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_VHT_SIG_B_MU20 diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_mu40.h new file mode 100644 index 0000000000000000000000000000000000000000..644066e68910e649656b2ab93d7dc4e73fa29734 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_mu40.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_MU40_H_ +#define _MACTX_VHT_SIG_B_MU40_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1 + + +struct mactx_vht_sig_b_mu40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#else + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_B_MU40_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. + +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000 + + +/* Description MCS_COPY + + Same as "mcs". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000 + + +/* Description TAIL_COPY + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 + + +/* Description RESERVED_1 + + +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000 + + + +#endif // MACTX_VHT_SIG_B_MU40 diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_mu80.h new file mode 100644 index 0000000000000000000000000000000000000000..71a324e17ab4381199eff751df3d0ed07ec63b4d --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_mu80.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_MU80_H_ +#define _MACTX_VHT_SIG_B_MU80_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2 + + +struct mactx_vht_sig_b_mu80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#else + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_B_MU80_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY_A + + Same as "length". This field is not valid for RX packets + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 + + +/* Description MCS_COPY_A + + Same as "mcs". This field is not valid for RX packets +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 + + +/* Description TAIL_COPY_A + + Same as "tail". This field is not valid for RX packets +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + + +/* Description RESERVED_1 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 + + +/* Description LENGTH_COPY_B + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff + + +/* Description MCS_COPY_B + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 + + +/* Description TAIL_COPY_B + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY_C + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 + + +/* Description MCS_COPY_C + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 + + +/* Description TAIL_COPY_C + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + + +/* Description RESERVED_3 + + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 + + + +#endif // MACTX_VHT_SIG_B_MU80 diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_su160.h new file mode 100644 index 0000000000000000000000000000000000000000..cf51fa56d90c056f5062d840ca1787c79baf2f57 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_su160.h @@ -0,0 +1,506 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_SU160_H_ +#define _MACTX_VHT_SIG_B_SU160_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4 + + +struct mactx_vht_sig_b_su160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#else + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_B_SU160_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones for non-NDP frames and ignored + on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY_A + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 + + +/* Description VHTB_RESERVED_COPY_A + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 + + +/* Description TAIL_COPY_A + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + + +/* Description RESERVED_1 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 + + +/* Description RX_NDP_COPY_A + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 + + +/* Description LENGTH_COPY_B + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff + + +/* Description VHTB_RESERVED_COPY_B + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 + + +/* Description TAIL_COPY_B + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + + +/* Description RESERVED_2 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 + + +/* Description RX_NDP_COPY_B + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY_C + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 + + +/* Description VHTB_RESERVED_COPY_C + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 + + +/* Description TAIL_COPY_C + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + + +/* Description RESERVED_3 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 + + +/* Description RX_NDP_COPY_C + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 + + +/* Description LENGTH_COPY_D + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff + + +/* Description VHTB_RESERVED_COPY_D + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000 + + +/* Description TAIL_COPY_D + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 + + +/* Description RESERVED_4 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000 + + +/* Description RX_NDP_COPY_D + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY_E + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000 + + +/* Description VHTB_RESERVED_COPY_E + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000 + + +/* Description TAIL_COPY_E + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 + + +/* Description RESERVED_5 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000 + + +/* Description RX_NDP_COPY_E + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000 + + +/* Description LENGTH_COPY_F + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff + + +/* Description VHTB_RESERVED_COPY_F + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000 + + +/* Description TAIL_COPY_F + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 + + +/* Description RESERVED_6 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000 + + +/* Description RX_NDP_COPY_F + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY_G + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000 + + +/* Description VHTB_RESERVED_COPY_G + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000 + + +/* Description TAIL_COPY_G + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 + + +/* Description RESERVED_7 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000 + + +/* Description RX_NDP_COPY_G + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000 + + + +#endif // MACTX_VHT_SIG_B_SU160 diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_su20.h new file mode 100644 index 0000000000000000000000000000000000000000..37f6d276e1b6073a1d16d6abd043f2a6bb307a57 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_su20.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_SU20_H_ +#define _MACTX_VHT_SIG_B_SU20_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1 + + +struct mactx_vht_sig_b_su20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_VHT_SIG_B_SU20_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones for non-NDP frames and ignored + on receive + +*/ + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 + + +/* Description RESERVED + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_VHT_SIG_B_SU20 diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_su40.h new file mode 100644 index 0000000000000000000000000000000000000000..a2addc0befefc6a58445a8cebff1887696f408aa --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_su40.h @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_SU40_H_ +#define _MACTX_VHT_SIG_B_SU40_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1 + + +struct mactx_vht_sig_b_su40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#else + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_B_SU40_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 + + +/* Description RESERVED + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000 + + +/* Description VHTB_RESERVED_COPY + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000 + + +/* Description TAIL_COPY + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 + + +/* Description RESERVED_COPY + + Same as "reserved" +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000 + + +/* Description RX_NDP_COPY + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000 + + + +#endif // MACTX_VHT_SIG_B_SU40 diff --git a/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_su80.h new file mode 100644 index 0000000000000000000000000000000000000000..7ac4ff450811f6b9f44b593b64a59641e70b5d04 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mactx_vht_sig_b_su80.h @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_SU80_H_ +#define _MACTX_VHT_SIG_B_SU80_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2 + + +struct mactx_vht_sig_b_su80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#else + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_B_SU80_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones for non-NDP frames and ignored + on receive +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY_A + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 + + +/* Description VHTB_RESERVED_COPY_A + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 + + +/* Description TAIL_COPY_A + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + + +/* Description RESERVED_1 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 + + +/* Description RX_NDP_COPY_A + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 + + +/* Description LENGTH_COPY_B + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff + + +/* Description VHTB_RESERVED_COPY_B + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 + + +/* Description TAIL_COPY_B + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + + +/* Description RESERVED_2 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 + + +/* Description RX_NDP_COPY_B + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY_C + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 + + +/* Description VHTB_RESERVED_COPY_C + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 + + +/* Description TAIL_COPY_C + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + + +/* Description RESERVED_3 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 + + +/* Description RX_NDP_COPY_C + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 + + + +#endif // MACTX_VHT_SIG_B_SU80 diff --git a/drivers/staging/fw-api/hw/qcn6432/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/qcn6432/mlo_sta_id_details.h new file mode 100644 index 0000000000000000000000000000000000000000..0efc81854431e241ba0af358b2d68e2fa1c0213b --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mlo_sta_id_details.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MLO_STA_ID_DETAILS_H_ +#define _MLO_STA_ID_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 + + +struct mlo_sta_id_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t nstr_mlo_sta_id : 10, // [9:0] + block_self_ml_sync : 1, // [10:10] + block_partner_ml_sync : 1, // [11:11] + nstr_mlo_sta_id_valid : 1, // [12:12] + reserved_0a : 3; // [15:13] +#else + uint16_t reserved_0a : 3, // [15:13] + nstr_mlo_sta_id_valid : 1, // [12:12] + block_partner_ml_sync : 1, // [11:11] + block_self_ml_sync : 1, // [10:10] + nstr_mlo_sta_id : 10; // [9:0] +#endif +}; + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + + +/* Description RESERVED_0A + + +*/ + +#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 + + + +#endif // MLO_STA_ID_DETAILS diff --git a/drivers/staging/fw-api/hw/qcn6432/mon_buffer_addr.h b/drivers/staging/fw-api/hw/qcn6432/mon_buffer_addr.h new file mode 100644 index 0000000000000000000000000000000000000000..f6052babd52153447de847eb2901a98e85084e8c --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mon_buffer_addr.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MON_BUFFER_ADDR_H_ +#define _MON_BUFFER_ADDR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 + +#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 + + +struct mon_buffer_addr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t dma_length : 12, // [11:0] + reserved_2a : 4, // [15:12] + msdu_continuation : 1, // [16:16] + truncated : 1, // [17:17] + reserved_2b : 14; // [31:18] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t reserved_2b : 14, // [31:18] + truncated : 1, // [17:17] + msdu_continuation : 1, // [16:16] + reserved_2a : 4, // [15:12] + dma_length : 12; // [11:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description BUFFER_VIRT_ADDR_31_0 + + Lower 32 bits of the 64-bit virtual address of the packet + buffer + +*/ + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff + + +/* Description BUFFER_VIRT_ADDR_63_32 + + Upper 32 bits of the 64-bit virtual address of the packet + buffer + +*/ + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 + + +/* Description DMA_LENGTH + + The number of bytes DMA'd into the packet buffer MINUS 1. + + + The packet could be truncated in case of a 'TX_FLUSH' or + 'RX_FLUSH,' or in case of drops due to back-pressure. + +*/ + +#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 +#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 +#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff + + +/* Description RESERVED_2A + + +*/ + +#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 +#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 +#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 + + +/* Description MSDU_CONTINUATION + + When set, this packet buffer was not able to hold the entire + MSDU. The next buffer will therefore contain additional + packet bytes. + +*/ + +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 + + +/* Description TRUNCATED + + When set, this TLV belongs to a previously truncated MPDU. + + +*/ + +#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 + + +/* Description RESERVED_2B + + +*/ + +#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 +#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 +#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 +#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 +#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MON_BUFFER_ADDR diff --git a/drivers/staging/fw-api/hw/qcn6432/mon_destination_ring.h b/drivers/staging/fw-api/hw/qcn6432/mon_destination_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..70ad321bed9e774e0c2142aea4f38b241b723231 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mon_destination_ring.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MON_DESTINATION_RING_H_ +#define _MON_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 + + +struct mon_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t stat_buf_virt_addr_31_0 : 32; // [31:0] + uint32_t stat_buf_virt_addr_63_32 : 32; // [31:0] + uint32_t ppdu_id : 32; // [31:0] + uint32_t end_offset : 12, // [11:0] + reserved_3a : 4, // [15:12] + end_reason : 2, // [17:16] + initiator : 1, // [18:18] + empty_descriptor : 1, // [19:19] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t stat_buf_virt_addr_31_0 : 32; // [31:0] + uint32_t stat_buf_virt_addr_63_32 : 32; // [31:0] + uint32_t ppdu_id : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + empty_descriptor : 1, // [19:19] + initiator : 1, // [18:18] + end_reason : 2, // [17:16] + reserved_3a : 4, // [15:12] + end_offset : 12; // [11:0] +#endif +}; + + +/* Description STAT_BUF_VIRT_ADDR_31_0 + + Lower 32 bits of the 64-bit virtual address of the status + buffer + +*/ + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff + + +/* Description STAT_BUF_VIRT_ADDR_63_32 + + Upper 32 bits of the 64-bit virtual address of the status + buffer + +*/ + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff + + +/* Description PPDU_ID + + TXMON fills this with the schedule_id from 'TX_FES_SETUP' + when Initiator = 1. + TXMON fills this with the Phy_ppdu_id from 'RX_RESPONSE_REQUIRED_INFO' + when Initiator = 0. + RXMON fills this with the Phy_ppdu_id from 'RX_PPDU_START.' + + +*/ + +#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 +#define MON_DESTINATION_RING_PPDU_ID_LSB 0 +#define MON_DESTINATION_RING_PPDU_ID_MSB 31 +#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff + + +/* Description END_OFFSET + + The offset (in units of 4 bytes) into the status buffer + where DMA ended, i.e. offset to the last TLV + last TLV + size MINUS 1. + + In case of a 'TX_FLUSH' or 'RX_FLUSH,' this reflects the + offset at which flush occurred. + +*/ + +#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_OFFSET_LSB 0 +#define MON_DESTINATION_RING_END_OFFSET_MSB 11 +#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff + + +/* Description RESERVED_3A + + +*/ + +#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 +#define MON_DESTINATION_RING_RESERVED_3A_MSB 15 +#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x0000f000 + + +/* Description END_REASON + + The status buffer was fully + written. + A 'TX_FLUSH' or 'RX_FLUSH' was + received. This is implicitly the end of the Tx FES or Rx + PPDU. The status buffer data can be discarded by SW. + A 'TX_FES_STATUS_END' or 'RX_PPDU_END' + was received indicating the end of the Tx FES or Rx PPDU. + + The PPDU got truncated due to + a system-level error. + +*/ + +#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_REASON_LSB 16 +#define MON_DESTINATION_RING_END_REASON_MSB 17 +#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 + + +/* Description INITIATOR + + 1: This descriptor belongs to a TX FES (TXOP initiator) + 0: This descriptor belongs to a response TX (TXOP responder) + + +*/ + +#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_INITIATOR_LSB 18 +#define MON_DESTINATION_RING_INITIATOR_MSB 18 +#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 + + +/* Description EMPTY_DESCRIPTOR + + 0: This descriptor is written on a flush or the end of a + PPDU or the end of status buffer + 1: This descriptor is written to indicate drop information + (see 'MON_DESTINATION_RING_WITH_DROP' structure) + +*/ + +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 + + +/* Description RING_ID + + Consumer: SW/REO/DEBUG + Producer: SRNG (of TXMON/RXMON) + + For debugging. + This field is filled in by the SRNG module. + It help to identify the ring that is being looked + +*/ + +#define MON_DESTINATION_RING_RING_ID_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RING_ID_LSB 20 +#define MON_DESTINATION_RING_RING_ID_MSB 27 +#define MON_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: SW/DEBUG + Producer: SRNG (of TXMON/RXMON) + + For debugging. + This field is filled in by the SRNG module. + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c +#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // MON_DESTINATION_RING diff --git a/drivers/staging/fw-api/hw/qcn6432/mon_destination_ring_with_drop.h b/drivers/staging/fw-api/hw/qcn6432/mon_destination_ring_with_drop.h new file mode 100644 index 0000000000000000000000000000000000000000..24f83a7fdba1133ee54fd2af3a10794afd210a32 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mon_destination_ring_with_drop.h @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MON_DESTINATION_RING_WITH_DROP_H_ +#define _MON_DESTINATION_RING_WITH_DROP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_DESTINATION_RING_WITH_DROP 4 + + +struct mon_destination_ring_with_drop { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_drop_cnt : 10, // [9:0] + mpdu_drop_cnt : 10, // [19:10] + tlv_drop_cnt : 10, // [29:20] + end_of_ppdu_seen : 1, // [30:30] + reserved_0a : 1; // [31:31] + uint32_t reserved_1a : 32; // [31:0] + uint32_t ppdu_id : 32; // [31:0] + uint32_t reserved_3a : 18, // [17:0] + initiator : 1, // [18:18] + empty_descriptor : 1, // [19:19] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t reserved_0a : 1, // [31:31] + end_of_ppdu_seen : 1, // [30:30] + tlv_drop_cnt : 10, // [29:20] + mpdu_drop_cnt : 10, // [19:10] + ppdu_drop_cnt : 10; // [9:0] + uint32_t reserved_1a : 32; // [31:0] + uint32_t ppdu_id : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + empty_descriptor : 1, // [19:19] + initiator : 1, // [18:18] + reserved_3a : 18; // [17:0] +#endif +}; + + +/* Description PPDU_DROP_CNT + + The number of PPDUs dropped due to the back-pressure + + Set to 1023 if >1023 PPDUs got dropped + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_PPDU_DROP_CNT_OFFSET 0x00000000 +#define MON_DESTINATION_RING_WITH_DROP_PPDU_DROP_CNT_LSB 0 +#define MON_DESTINATION_RING_WITH_DROP_PPDU_DROP_CNT_MSB 9 +#define MON_DESTINATION_RING_WITH_DROP_PPDU_DROP_CNT_MASK 0x000003ff + + +/* Description MPDU_DROP_CNT + + The number of MPDUs dropped within the first PPDU due to + the back-pressure + + Set to 1023 if >1023 MPDUs got dropped + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_MPDU_DROP_CNT_OFFSET 0x00000000 +#define MON_DESTINATION_RING_WITH_DROP_MPDU_DROP_CNT_LSB 10 +#define MON_DESTINATION_RING_WITH_DROP_MPDU_DROP_CNT_MSB 19 +#define MON_DESTINATION_RING_WITH_DROP_MPDU_DROP_CNT_MASK 0x000ffc00 + + +/* Description TLV_DROP_CNT + + The number of PPDU-level (global or per-user) TLVs dropped + within the first PPDU due to the back-pressure +*/ + +#define MON_DESTINATION_RING_WITH_DROP_TLV_DROP_CNT_OFFSET 0x00000000 +#define MON_DESTINATION_RING_WITH_DROP_TLV_DROP_CNT_LSB 20 +#define MON_DESTINATION_RING_WITH_DROP_TLV_DROP_CNT_MSB 29 +#define MON_DESTINATION_RING_WITH_DROP_TLV_DROP_CNT_MASK 0x3ff00000 + + +/* Description END_OF_PPDU_SEEN + + Field valid only if mpdu_drop_cnt > 0 or tlv_drop_cnt > + 0 + + Set by TXMON if 'TX_FES_STATUS_END' is received for a partially + dropped PPDU when Initiator = 1. + Set by TXMON if 'RESPONSE_END_STATUS' is received for a + partially dropped PPDU when Initiator = 0. + Set by RXMON if 'RX_PPDU_END_STATUS_DONE' is received for + a partially dropped PPDU. +*/ + +#define MON_DESTINATION_RING_WITH_DROP_END_OF_PPDU_SEEN_OFFSET 0x00000000 +#define MON_DESTINATION_RING_WITH_DROP_END_OF_PPDU_SEEN_LSB 30 +#define MON_DESTINATION_RING_WITH_DROP_END_OF_PPDU_SEEN_MSB 30 +#define MON_DESTINATION_RING_WITH_DROP_END_OF_PPDU_SEEN_MASK 0x40000000 + + +/* Description RESERVED_0A + + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_0A_OFFSET 0x00000000 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_0A_LSB 31 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_0A_MSB 31 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_0A_MASK 0x80000000 + + +/* Description RESERVED_1A + + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_1A_OFFSET 0x00000004 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_1A_LSB 0 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_1A_MSB 31 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_1A_MASK 0xffffffff + + +/* Description PPDU_ID + + The ID of the last PPDU which saw the back-pressure on AXI + + + TXMON fills this with the schedule_id from 'TX_FES_SETUP' + when Initiator = 1. + TXMON fills this with the Phy_ppdu_id from 'RX_RESPONSE_REQUIRED_INFO' + when Initiator = 0. + RXMON fills this with the Phy_ppdu_id from 'RX_PPDU_START.' + + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_PPDU_ID_OFFSET 0x00000008 +#define MON_DESTINATION_RING_WITH_DROP_PPDU_ID_LSB 0 +#define MON_DESTINATION_RING_WITH_DROP_PPDU_ID_MSB 31 +#define MON_DESTINATION_RING_WITH_DROP_PPDU_ID_MASK 0xffffffff + + +/* Description RESERVED_3A + + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_3A_OFFSET 0x0000000c +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_3A_LSB 0 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_3A_MSB 17 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_3A_MASK 0x0003ffff + + +/* Description INITIATOR + + 1: This descriptor belongs to a TX FES (TXOP initiator) + 0: This descriptor belongs to a response TX (TXOP responder) + + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_INITIATOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_WITH_DROP_INITIATOR_LSB 18 +#define MON_DESTINATION_RING_WITH_DROP_INITIATOR_MSB 18 +#define MON_DESTINATION_RING_WITH_DROP_INITIATOR_MASK 0x00040000 + + +/* Description EMPTY_DESCRIPTOR + + 0: This descriptor is written on a flush or the end of a + PPDU or the end of status buffer (see 'MON_DESTINATION_RING' + structure) + 1: This descriptor is written to indicate drop information + + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_EMPTY_DESCRIPTOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_WITH_DROP_EMPTY_DESCRIPTOR_LSB 19 +#define MON_DESTINATION_RING_WITH_DROP_EMPTY_DESCRIPTOR_MSB 19 +#define MON_DESTINATION_RING_WITH_DROP_EMPTY_DESCRIPTOR_MASK 0x00080000 + + +/* Description RING_ID + + Consumer: SW/REO/DEBUG + Producer: SRNG (of TXMON/RXMON) + + For debugging. + This field is filled in by the SRNG module. + It help to identify the ring that is being looked + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_RING_ID_OFFSET 0x0000000c +#define MON_DESTINATION_RING_WITH_DROP_RING_ID_LSB 20 +#define MON_DESTINATION_RING_WITH_DROP_RING_ID_MSB 27 +#define MON_DESTINATION_RING_WITH_DROP_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: SW/DEBUG + Producer: SRNG (of TXMON/RXMON) + + For debugging. + This field is filled in by the SRNG module. + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_LOOPING_COUNT_OFFSET 0x0000000c +#define MON_DESTINATION_RING_WITH_DROP_LOOPING_COUNT_LSB 28 +#define MON_DESTINATION_RING_WITH_DROP_LOOPING_COUNT_MSB 31 +#define MON_DESTINATION_RING_WITH_DROP_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // MON_DESTINATION_RING_WITH_DROP diff --git a/drivers/staging/fw-api/hw/qcn6432/mon_drop.h b/drivers/staging/fw-api/hw/qcn6432/mon_drop.h new file mode 100644 index 0000000000000000000000000000000000000000..072eda2ce46446d7ee867ed459c092006299f76b --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mon_drop.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MON_DROP_H_ +#define _MON_DROP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_DROP 2 + +#define NUM_OF_QWORDS_MON_DROP 1 + + +struct mon_drop { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_id : 32; // [31:0] + uint32_t ppdu_drop_cnt : 10, // [9:0] + mpdu_drop_cnt : 10, // [19:10] + tlv_drop_cnt : 10, // [29:20] + end_of_ppdu_seen : 1, // [30:30] + reserved_1a : 1; // [31:31] +#else + uint32_t ppdu_id : 32; // [31:0] + uint32_t reserved_1a : 1, // [31:31] + end_of_ppdu_seen : 1, // [30:30] + tlv_drop_cnt : 10, // [29:20] + mpdu_drop_cnt : 10, // [19:10] + ppdu_drop_cnt : 10; // [9:0] +#endif +}; + + +/* Description PPDU_ID + + The ID of the last PPDU which saw the back-pressure on AXI + + + TXMON fills this with the schedule_id from 'TX_FES_SETUP' + in case of a TX FES (TXOP initiator). + TXMON fills this with the Phy_ppdu_id from 'RX_RESPONSE_REQUIRED_INFO' + in case of a response TX (TXOP responder). + RXMON fills this with the Phy_ppdu_id from 'RX_PPDU_START.' + + +*/ + +#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000 +#define MON_DROP_PPDU_ID_LSB 0 +#define MON_DROP_PPDU_ID_MSB 31 +#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff + + +/* Description PPDU_DROP_CNT + + The number of PPDUs dropped due to the back-pressure + + Set to 1023 if >1023 PPDUs got dropped + +*/ + +#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_PPDU_DROP_CNT_LSB 32 +#define MON_DROP_PPDU_DROP_CNT_MSB 41 +#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000 + + +/* Description MPDU_DROP_CNT + + The number of MPDUs dropped within the first PPDU due to + the back-pressure + + Set to 1023 if >1023 MPDUs got dropped + +*/ + +#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_MPDU_DROP_CNT_LSB 42 +#define MON_DROP_MPDU_DROP_CNT_MSB 51 +#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000 + + +/* Description TLV_DROP_CNT + + The number of PPDU-level (global or per-user) TLVs dropped + within the first PPDU due to the back-pressure +*/ + +#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_TLV_DROP_CNT_LSB 52 +#define MON_DROP_TLV_DROP_CNT_MSB 61 +#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000 + + +/* Description END_OF_PPDU_SEEN + + Field valid only if mpdu_drop_cnt > 0 or tlv_drop_cnt > + 0 + + Set by TXMON if 'TX_FES_STATUS_END' is received but dropped + in case of a TX FES (TXOP initiator). + Set by TXMON if 'RESPONSE_END_STATUS' is received but dropped + in case of a response TX (TXOP responder). + Set by RXMON if 'RX_PPDU_END' is received but dropped +*/ + +#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000 +#define MON_DROP_END_OF_PPDU_SEEN_LSB 62 +#define MON_DROP_END_OF_PPDU_SEEN_MSB 62 +#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000 +#define MON_DROP_RESERVED_1A_LSB 63 +#define MON_DROP_RESERVED_1A_MSB 63 +#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000 + + + +#endif // MON_DROP diff --git a/drivers/staging/fw-api/hw/qcn6432/mon_ingress_ring.h b/drivers/staging/fw-api/hw/qcn6432/mon_ingress_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..ac72e170c9a29e97aaca26ecdf85c67848d3f946 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/mon_ingress_ring.h @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MON_INGRESS_RING_H_ +#define _MON_INGRESS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_MON_INGRESS_RING 4 + + +struct mon_ingress_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] +#else + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] +#endif +}; + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: TXMON/RXMON + Producer: SW + + Details of the physical address of the buffer + + 'Sw_buffer_cookie' and 'Return_buffer_manager' sub-fields + are reserved and unused by TXMON/RXMON. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description BUFFER_VIRT_ADDR_31_0 + + Lower 32 bits of the 64-bit virtual address corresponding + to Buffer_addr_info_details + +*/ + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_VIRT_ADDR_63_32 + + Upper 32 bits of the 64-bit virtual address corresponding + to Buffer_addr_info_details + +*/ + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + + + +#endif // MON_INGRESS_RING diff --git a/drivers/staging/fw-api/hw/qcn6432/no_ack_report.h b/drivers/staging/fw-api/hw/qcn6432/no_ack_report.h new file mode 100644 index 0000000000000000000000000000000000000000..607d72d99760e41bbf0fdb45759198028c3ad35e --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/no_ack_report.h @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _NO_ACK_REPORT_H_ +#define _NO_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_NO_ACK_REPORT 4 + + +struct no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_ack_transmit_reason : 4, // [3:0] + macrx_abort_reason : 4, // [7:4] + phyrx_abort_reason : 8, // [15:8] + frame_control : 16; // [31:16] + uint32_t rx_ppdu_duration : 24, // [23:0] + sr_ppdu_during_obss : 1, // [24:24] + selfgen_response_reason_to_sr_ppdu : 4, // [28:25] + reserved_1 : 3; // [31:29] + uint32_t pre_bt_broadcast_status_details : 12, // [11:0] + first_bt_broadcast_status_details : 12, // [23:12] + reserved_2 : 8; // [31:24] + uint32_t second_bt_broadcast_status_details : 12, // [11:0] + reserved_3 : 20; // [31:12] +#else + uint32_t frame_control : 16, // [31:16] + phyrx_abort_reason : 8, // [15:8] + macrx_abort_reason : 4, // [7:4] + no_ack_transmit_reason : 4; // [3:0] + uint32_t reserved_1 : 3, // [31:29] + selfgen_response_reason_to_sr_ppdu : 4, // [28:25] + sr_ppdu_during_obss : 1, // [24:24] + rx_ppdu_duration : 24; // [23:0] + uint32_t reserved_2 : 8, // [31:24] + first_bt_broadcast_status_details : 12, // [23:12] + pre_bt_broadcast_status_details : 12; // [11:0] + uint32_t reserved_3 : 20, // [31:12] + second_bt_broadcast_status_details : 12; // [11:0] +#endif +}; + + +/* Description NO_ACK_TRANSMIT_REASON + + Field that indicates why the received frame is not needing + any transmit response in SIFS time. + + The possible responses are listed in order. + + All received frames have + FCS errors. + All received + frames did not require a response. + Broadcast frame received + Multicast frame received + Frames received are not directed + to this device (based on addr1) + The AST entry indicated that NO + ACK shall be send + PHY dropped the incoming frame + dur to GID mismatch + PHY dropped the incoming frame + dur to AID mismatch + PHY reported an error during + reception. For details, see the 'phy_error...' fields + The requested BW for the + CTS response frame is not available + An NDPA frame got received + An NDP frame got received + a trigger frame was received, + but due to NAV setting, no response could be generated + A trigger frame was received, + but this device's AID was not in the list + No ACK is needed as + SW asked RXPCU to send a abort_request to the PHYRX + placeholder in case non + of the above properly cover the reasons + + Also see the field SR_PPDU_during_OBSS. + +*/ + +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f + + +/* Description MACRX_ABORT_REASON + + Field only valid when No_ack_transmit_reason is set to NO_ACK_MAC_ABORT_REQ + + + Error field received from MACRX_ABORT_REQUEST.Macrx_abort_reason[2:0] + + +*/ + +#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 + + +/* Description PHYRX_ABORT_REASON + + Field only valid when No_ack_transmit_reason is set to NO_ACK_PHY_error + + + Error field received from PHYRX_ABORT_REQUEST.Phyrx_abort_reason + + + +*/ + +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 + + +/* Description FRAME_CONTROL + + frame control field of the received (first properly received) + frame + + +*/ + +#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 +#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 +#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + + +/* Description RX_PPDU_DURATION + + The length of this PPDU reception in us + +*/ + +#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 +#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff + + +/* Description SR_PPDU_DURING_OBSS + + Field only valid with SRP Responder support + + Indicates that the received frame was sent using SRP as + indicated by the 'SR PPDU' bit in the 'CAS Control' in the + 'HE A-Control' in one of the MPDUs received, and that the + response could not be generated due to OBSS traffic setting + the NAV + +*/ + +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 + + +/* Description SELFGEN_RESPONSE_REASON_TO_SR_PPDU + + Field only valid with SRP Responder support + + This field indicates why the received SR PPDU needs a response + in SIFS time. The e-num used is the same as in the field + selfgen_response_reason in 'ACK_REPORT' structure although + some of these will be unused in case of an SR PPDU. + + + + + Qboost trigger received + PSPOLL trigger received + Unscheduled APSD trigger received + + the CBF frame needs to be send as + a result of NDP or BRPOLL + 11ax trigger received for this + device + 11ax wildcardtrigger has + been received + 11ax wildcard trigger + for unassociated STAs has been received + EHT R1 trigger received for + this device + + + Ranging NDP + LMR need + to be sent in response to ranging NDPA + NDP + + +*/ + +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 + + +/* Description RESERVED_1 + + +*/ + +#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 +#define NO_ACK_REPORT_RESERVED_1_LSB 29 +#define NO_ACK_REPORT_RESERVED_1_MSB 31 +#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 + + +/* Description PRE_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the first received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + After power up, this field is all initialized to 0 + + Bits: [31:28]: always 0 + + + +*/ + +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + + +/* Description FIRST_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the first received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + If no COEX_STATUS_BROADCAST tlv is received during this + PPDU reception, this field will be set to 0 + +*/ + +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 + + +/* Description RESERVED_2 + + +*/ + +#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 +#define NO_ACK_REPORT_RESERVED_2_LSB 24 +#define NO_ACK_REPORT_RESERVED_2_MSB 31 +#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 + + +/* Description SECOND_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the second received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + If no second COEX_STATUS_BROADCAST tlv is received during + this PPDU reception, this field will be set to 0 + +*/ + +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + + +/* Description RESERVED_3 + + +*/ + +#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c +#define NO_ACK_REPORT_RESERVED_3_LSB 12 +#define NO_ACK_REPORT_RESERVED_3_MSB 31 +#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 + + + +#endif // NO_ACK_REPORT diff --git a/drivers/staging/fw-api/hw/qcn6432/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/qcn6432/ofdma_trigger_details.h new file mode 100644 index 0000000000000000000000000000000000000000..b4bd6ec2535ce46191f272c409228acf6fadb6ed --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/ofdma_trigger_details.h @@ -0,0 +1,2619 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _OFDMA_TRIGGER_DETAILS_H_ +#define _OFDMA_TRIGGER_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22 + +#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 11 + + +struct ofdma_trigger_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ax_trigger_source : 1, // [0:0] + rx_trigger_frame_user_source : 2, // [2:1] + received_bandwidth : 3, // [5:3] + txop_duration_all_ones : 1, // [6:6] + eht_trigger_response : 1, // [7:7] + pre_rssi_comb : 8, // [15:8] + rssi_comb : 8, // [23:16] + rxpcu_pcie_l0_req_duration : 8; // [31:24] + uint32_t he_trigger_ul_ppdu_length : 5, // [4:0] + he_trigger_ru_allocation : 8, // [12:5] + he_trigger_dl_tx_power : 5, // [17:13] + he_trigger_ul_target_rssi : 5, // [22:18] + he_trigger_ul_mcs : 2, // [24:23] + he_trigger_reserved : 1, // [25:25] + bss_color : 6; // [31:26] + uint32_t trigger_type : 4, // [3:0] + lsig_response_length : 12, // [15:4] + cascade_indication : 1, // [16:16] + carrier_sense : 1, // [17:17] + bandwidth : 2, // [19:18] + cp_ltf_size : 2, // [21:20] + mu_mimo_ltf_mode : 1, // [22:22] + number_of_ltfs : 3, // [25:23] + stbc : 1, // [26:26] + ldpc_extra_symbol : 1, // [27:27] + ap_tx_power_lsb_part : 4; // [31:28] + uint32_t ap_tx_power_msb_part : 2, // [1:0] + packet_extension_a_factor : 2, // [3:2] + packet_extension_pe_disambiguity : 1, // [4:4] + spatial_reuse : 16, // [20:5] + doppler : 1, // [21:21] + he_siga_reserved : 9, // [30:22] + reserved_3b : 1; // [31:31] + uint32_t aid12 : 12, // [11:0] + ru_allocation : 9, // [20:12] + mcs : 4, // [24:21] + dcm : 1, // [25:25] + start_spatial_stream : 3, // [28:26] + number_of_spatial_stream : 3; // [31:29] + uint32_t target_rssi : 7, // [6:0] + coding_type : 1, // [7:7] + mpdu_mu_spacing_factor : 2, // [9:8] + tid_aggregation_limit : 3, // [12:10] + reserved_5b : 1, // [13:13] + prefered_ac : 2, // [15:14] + bar_control_ack_policy : 1, // [16:16] + bar_control_multi_tid : 1, // [17:17] + bar_control_compressed_bitmap : 1, // [18:18] + bar_control_reserved : 9, // [27:19] + bar_control_tid_info : 4; // [31:28] + uint32_t nr0_per_tid_info_reserved : 12, // [11:0] + nr0_per_tid_info_tid_value : 4, // [15:12] + nr0_start_seq_ctrl_frag_number : 4, // [19:16] + nr0_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr1_per_tid_info_reserved : 12, // [11:0] + nr1_per_tid_info_tid_value : 4, // [15:12] + nr1_start_seq_ctrl_frag_number : 4, // [19:16] + nr1_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr2_per_tid_info_reserved : 12, // [11:0] + nr2_per_tid_info_tid_value : 4, // [15:12] + nr2_start_seq_ctrl_frag_number : 4, // [19:16] + nr2_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr3_per_tid_info_reserved : 12, // [11:0] + nr3_per_tid_info_tid_value : 4, // [15:12] + nr3_start_seq_ctrl_frag_number : 4, // [19:16] + nr3_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr4_per_tid_info_reserved : 12, // [11:0] + nr4_per_tid_info_tid_value : 4, // [15:12] + nr4_start_seq_ctrl_frag_number : 4, // [19:16] + nr4_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr5_per_tid_info_reserved : 12, // [11:0] + nr5_per_tid_info_tid_value : 4, // [15:12] + nr5_start_seq_ctrl_frag_number : 4, // [19:16] + nr5_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr6_per_tid_info_reserved : 12, // [11:0] + nr6_per_tid_info_tid_value : 4, // [15:12] + nr6_start_seq_ctrl_frag_number : 4, // [19:16] + nr6_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr7_per_tid_info_reserved : 12, // [11:0] + nr7_per_tid_info_tid_value : 4, // [15:12] + nr7_start_seq_ctrl_frag_number : 4, // [19:16] + nr7_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t fb_segment_retransmission_bitmap : 8, // [7:0] + reserved_14a : 2, // [9:8] + u_sig_puncture_pattern_encoding : 6, // [15:10] + dot11be_puncture_bitmap : 16; // [31:16] + uint32_t rx_chain_mask : 8, // [7:0] + rx_duration_field : 16, // [23:8] + scrambler_seed : 7, // [30:24] + rx_chain_mask_type : 1; // [31:31] + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t normalized_pre_rssi_comb : 8, // [23:16] + normalized_rssi_comb : 8; // [31:24] + uint32_t sw_peer_id : 16, // [15:0] + response_tx_duration : 16; // [31:16] + uint32_t ranging_trigger_subtype : 4, // [3:0] + tbr_trigger_common_info_79_68 : 12, // [15:4] + tbr_trigger_sound_reserved_20_12 : 9, // [24:16] + i2r_rep : 3, // [27:25] + tbr_trigger_sound_reserved_25_24 : 2, // [29:28] + reserved_18a : 1, // [30:30] + qos_null_only_response_tx : 1; // [31:31] + uint32_t tbr_trigger_sound_sac : 16, // [15:0] + reserved_19a : 8, // [23:16] + u_sig_reserved2 : 5, // [28:24] + reserved_19b : 3; // [31:29] + uint32_t eht_special_aid12 : 12, // [11:0] + phy_version : 3, // [14:12] + bandwidth_ext : 2, // [16:15] + eht_spatial_reuse : 8, // [24:17] + u_sig_reserved1 : 7; // [31:25] + uint32_t eht_trigger_special_user_info_71_40 : 32; // [31:0] +#else + uint32_t rxpcu_pcie_l0_req_duration : 8, // [31:24] + rssi_comb : 8, // [23:16] + pre_rssi_comb : 8, // [15:8] + eht_trigger_response : 1, // [7:7] + txop_duration_all_ones : 1, // [6:6] + received_bandwidth : 3, // [5:3] + rx_trigger_frame_user_source : 2, // [2:1] + ax_trigger_source : 1; // [0:0] + uint32_t bss_color : 6, // [31:26] + he_trigger_reserved : 1, // [25:25] + he_trigger_ul_mcs : 2, // [24:23] + he_trigger_ul_target_rssi : 5, // [22:18] + he_trigger_dl_tx_power : 5, // [17:13] + he_trigger_ru_allocation : 8, // [12:5] + he_trigger_ul_ppdu_length : 5; // [4:0] + uint32_t ap_tx_power_lsb_part : 4, // [31:28] + ldpc_extra_symbol : 1, // [27:27] + stbc : 1, // [26:26] + number_of_ltfs : 3, // [25:23] + mu_mimo_ltf_mode : 1, // [22:22] + cp_ltf_size : 2, // [21:20] + bandwidth : 2, // [19:18] + carrier_sense : 1, // [17:17] + cascade_indication : 1, // [16:16] + lsig_response_length : 12, // [15:4] + trigger_type : 4; // [3:0] + uint32_t reserved_3b : 1, // [31:31] + he_siga_reserved : 9, // [30:22] + doppler : 1, // [21:21] + spatial_reuse : 16, // [20:5] + packet_extension_pe_disambiguity : 1, // [4:4] + packet_extension_a_factor : 2, // [3:2] + ap_tx_power_msb_part : 2; // [1:0] + uint32_t number_of_spatial_stream : 3, // [31:29] + start_spatial_stream : 3, // [28:26] + dcm : 1, // [25:25] + mcs : 4, // [24:21] + ru_allocation : 9, // [20:12] + aid12 : 12; // [11:0] + uint32_t bar_control_tid_info : 4, // [31:28] + bar_control_reserved : 9, // [27:19] + bar_control_compressed_bitmap : 1, // [18:18] + bar_control_multi_tid : 1, // [17:17] + bar_control_ack_policy : 1, // [16:16] + prefered_ac : 2, // [15:14] + reserved_5b : 1, // [13:13] + tid_aggregation_limit : 3, // [12:10] + mpdu_mu_spacing_factor : 2, // [9:8] + coding_type : 1, // [7:7] + target_rssi : 7; // [6:0] + uint32_t nr0_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr0_start_seq_ctrl_frag_number : 4, // [19:16] + nr0_per_tid_info_tid_value : 4, // [15:12] + nr0_per_tid_info_reserved : 12; // [11:0] + uint32_t nr1_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr1_start_seq_ctrl_frag_number : 4, // [19:16] + nr1_per_tid_info_tid_value : 4, // [15:12] + nr1_per_tid_info_reserved : 12; // [11:0] + uint32_t nr2_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr2_start_seq_ctrl_frag_number : 4, // [19:16] + nr2_per_tid_info_tid_value : 4, // [15:12] + nr2_per_tid_info_reserved : 12; // [11:0] + uint32_t nr3_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr3_start_seq_ctrl_frag_number : 4, // [19:16] + nr3_per_tid_info_tid_value : 4, // [15:12] + nr3_per_tid_info_reserved : 12; // [11:0] + uint32_t nr4_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr4_start_seq_ctrl_frag_number : 4, // [19:16] + nr4_per_tid_info_tid_value : 4, // [15:12] + nr4_per_tid_info_reserved : 12; // [11:0] + uint32_t nr5_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr5_start_seq_ctrl_frag_number : 4, // [19:16] + nr5_per_tid_info_tid_value : 4, // [15:12] + nr5_per_tid_info_reserved : 12; // [11:0] + uint32_t nr6_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr6_start_seq_ctrl_frag_number : 4, // [19:16] + nr6_per_tid_info_tid_value : 4, // [15:12] + nr6_per_tid_info_reserved : 12; // [11:0] + uint32_t nr7_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr7_start_seq_ctrl_frag_number : 4, // [19:16] + nr7_per_tid_info_tid_value : 4, // [15:12] + nr7_per_tid_info_reserved : 12; // [11:0] + uint32_t dot11be_puncture_bitmap : 16, // [31:16] + u_sig_puncture_pattern_encoding : 6, // [15:10] + reserved_14a : 2, // [9:8] + fb_segment_retransmission_bitmap : 8; // [7:0] + uint32_t rx_chain_mask_type : 1, // [31:31] + scrambler_seed : 7, // [30:24] + rx_duration_field : 16, // [23:8] + rx_chain_mask : 8; // [7:0] + uint32_t normalized_rssi_comb : 8, // [31:24] + normalized_pre_rssi_comb : 8; // [23:16] + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint32_t response_tx_duration : 16, // [31:16] + sw_peer_id : 16; // [15:0] + uint32_t qos_null_only_response_tx : 1, // [31:31] + reserved_18a : 1, // [30:30] + tbr_trigger_sound_reserved_25_24 : 2, // [29:28] + i2r_rep : 3, // [27:25] + tbr_trigger_sound_reserved_20_12 : 9, // [24:16] + tbr_trigger_common_info_79_68 : 12, // [15:4] + ranging_trigger_subtype : 4; // [3:0] + uint32_t reserved_19b : 3, // [31:29] + u_sig_reserved2 : 5, // [28:24] + reserved_19a : 8, // [23:16] + tbr_trigger_sound_sac : 16; // [15:0] + uint32_t u_sig_reserved1 : 7, // [31:25] + eht_spatial_reuse : 8, // [24:17] + bandwidth_ext : 2, // [16:15] + phy_version : 3, // [14:12] + eht_special_aid12 : 12; // [11:0] + uint32_t eht_trigger_special_user_info_71_40 : 32; // [31:0] +#endif +}; + + +/* Description AX_TRIGGER_SOURCE + + + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001 + + +/* Description RX_TRIGGER_FRAME_USER_SOURCE + + Field not really needed by PDG, but is there for debugging + purposes to be put in event. + + + wildcard trigger + for associated STAs + wildcard + trigger for unassociated STAs + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006 + + +/* Description RECEIVED_BANDWIDTH + + Received Packet bandwidth of the trigger frame. + + Note that this is not the BW indicated within the trigger + frame itself. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038 + + +/* Description TXOP_DURATION_ALL_ONES + + When set, TXOP_DURATION of the received frame was set to + all 1s. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040 + + +/* Description EHT_TRIGGER_RESPONSE + + 0: Trigger expects an HE TB PPDU Tx response. + 1: Trigger expects an EHT TB PPDU Tx response. + +*/ + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080 + + +/* Description PRE_RSSI_COMB + + Combined pre_rssi of all chains. Based on primary channel + RSSI. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00 + + +/* Description RSSI_COMB + + Combined rssi of all chains. Based on primary channel RSSI. + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000 + + +/* Description RXPCU_PCIE_L0_REQ_DURATION + + RXPCU fills the duration in µs for which it has asserted + the 'L0 request' signal to PCIe when it generates this + TLV. This may be capped by either the max. PCIe L1SS exit + latency (~75 µs) or the max. value possible for this field. + + + This is filled as zero if ILP is unsupported + + PDG uses this to fill Qos_null_only_response_tx. + +*/ + +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000 + + +/* Description HE_TRIGGER_UL_PPDU_LENGTH + + Field only valid when ax_trigger_source = he_control_based_trigger + + + Field extracted from the HE control field. + length of the HE trigger-based PPDU response. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000 + + +/* Description HE_TRIGGER_RU_ALLOCATION + + Field only valid when ax_trigger_source = he_control_based_trigger + + + Field extracted from the HE control field. + RU allocation for HE based trigger + + +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000 + + +/* Description HE_TRIGGER_DL_TX_POWER + + Field only valid when ax_trigger_source = he_control_based_trigger + + + Field extracted from the HE control field. + Downlink TX power + + +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000 + + +/* Description HE_TRIGGER_UL_TARGET_RSSI + + Field only valid when ax_trigger_source = he_control_based_trigger + + + Field extracted from the HE control field. + Ul target RSSI + + +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000 + + +/* Description HE_TRIGGER_UL_MCS + + Field only valid when ax_trigger_source = he_control_based_trigger + + + Field extracted from the HE control field. + UL MCS + + +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000 + + +/* Description HE_TRIGGER_RESERVED + + Field only valid when ax_trigger_source = he_control_based_trigger + + + Field extracted from the HE control field. + Reserved field + + +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000 + + +/* Description BSS_COLOR + + The BSS color of the AP + +*/ + +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000 + + +/* Description TRIGGER_TYPE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Indicates what kind of response is required to the received + OFDMA trigger... + + Field not really needed by PDG, but is there for debugging + purposes to be put in event. + + TXPCU sends back whatever SW has + programmed...for the basic response.. + TXPCU is only allowed to send + CBF frame(s) back + TXPCU shall first send BA info, + and optionally followed with data. No info from SCH is expected + + TXPCU shall only send CTS back. + No info from SCH is expected + Also known as the BSRP trigger. + TXPCU sends back whatever SW has programmed...for the basic + response.. + + Bandwidth Query Report Poll + NDP feedback report + Poll + ranging Trigger Frame of + subvariant indicated by Ranging_Trigger_Subtype + + + + + + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f + + +/* Description LSIG_RESPONSE_LENGTH + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Indicates the value of the L-SIG Length field of the HE + trigger-based PPDU that is the response to the Trigger frame + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0 + + +/* Description CASCADE_INDICATION + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + When set to 1, then a subsequent Trigger frame follows the + current Trigger frame. + +*/ + +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000 + + +/* Description CARRIER_SENSE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Need to sense the energy before transmit when CS=1 if allocated + channel is not available do not transmit . If CS=0 no need + to check for idle channel. For region based restrict ignore + this bit and always check channel before transmit. + +*/ + +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000 + + +/* Description BANDWIDTH + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Indicates the bandwidth in the HE-SIG-A/U-SIG of the HE/EHT + Trigger based PPDU + + Also see field Bandwidth_ext that determines 320 MHz bandwidth + for EHT. + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000 + + +/* Description CP_LTF_SIZE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Indicates the CP and HE-LTF type + + 1xLTF + 1.6 us CP + 2x LTF + 1.6 µs CP + 4x LTF + 3.2 µs CP + + +*/ + +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000 + + +/* Description MU_MIMO_LTF_MODE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + MU MIMO LTF mode field indicates the mode in which pilots + are allocated + + Must be set to 0 for HE-Ranging NDPs (11az) or Short-NDP + + + 0: Single-stream pilot + 1: Mask LTF sequence of each spatial stream by a distinct + orthogonal code + +*/ + +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000 + + +/* Description NUMBER_OF_LTFS + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + includes the total number of LTFs the STA must include in + the response TRIG PPDU + +*/ + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000 + + +/* Description STBC + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + indicates whether STBS is used (for all STAs) + It is set to 1 if STBC encoding is used and set to 0 otherwise. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000 + + +/* Description LDPC_EXTRA_SYMBOL + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + indicates the status of LDPC Extra Symbol. It is set to + 1 when LDPC extra symbol is present and set to 0 otherwise + + +*/ + +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000 + + +/* Description AP_TX_POWER_LSB_PART + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Bits [3:0] of the ap_tx_power + + indicates the combined average power per 20 MHz bandwidth + of all transmit antennas used to transmit the trigger frame + at the HE AP. The resolution for the transmit power reported + in the Common Info field is 1dB + + Values 0 to 61 maps to -20 dBm to 40 dBm + Other values are reserved. + +*/ + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000 + + +/* Description AP_TX_POWER_MSB_PART + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Bits [5:4] of the ap_tx_power + See description above + +*/ + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000 + + +/* Description SPATIAL_REUSE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + indicates the value of the Spatial Reuse in the HE-SIGA + of the HE_TRIG PPDU transmitted as a response to the Trigger + frame + +*/ + +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000 + + +/* Description DOPPLER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + TODO: add description + +*/ + +#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000 + + +/* Description HE_SIGA_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + indicates the values of the reserved bits in the HE-SIGA + of the HE_TRIG PPDU transmitted as a response to the Trigger + frame + + In case of an EHT AP, bits [23:22] indicate the bits [55:54] + of the Trigger 'Common Info' called 'Special User Info Field + Present' and 'HE/EHT P160.' These are used along with Reserved_18a + to determine the presence of the EHT 'Special User Info' + field and EHT_trigger_response. +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000 + + +/* Description RESERVED_3B + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Reserved bit 63 in the Trigger 'Common Info' + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000 + + +/* Description AID12 + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + The AID12 subfield of the Per User Info field indicates + the LSB 12 bits of the AID of the STA allocated the RU to + transmit the MPDU(s) in the HE trigger-based PPDU + + Note strictly needed, but added here for debugging purposes. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff + + +/* Description RU_ALLOCATION + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + trigger based RU definition + + If EHT_trigger_response = 0, only lower 8 bits are valid. + + If EHT_trigger_response = 1, all 9 bits re valid. + +*/ + +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000 + + +/* Description MCS + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + indicates the MCS of the HE trigger-based PPDU response + of the STA identified by User Identifier field + +*/ + +#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 +#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 +#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000 + + +/* Description DCM + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + indicates dual carrier modulation of the HE trigger-based + PPDU response of the STA identified by User Identifier + subfield. A value of 1 indicates that the HE trigger-based + PPDU response shall use DCM. + Set to 0 to indicate that DCM shall not be used + +*/ + +#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000 + + +/* Description START_SPATIAL_STREAM + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + Indicates the starting spatial stream, STARTING_SS_NUM, + and is set to STARTING_SS_NUM - 1 of the HE trigger-based + PPDU response of the STA identified by User Identifier + field. + +*/ + +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000 + + +/* Description NUMBER_OF_SPATIAL_STREAM + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + indicates the number of spatial streams, NUM_SS and is set + to NUM_SS - 1, of the HE trigger-based PPDU response of + the STA identified by User Identifier field. + + In case of EHT_trigger_response=1, RXPCU fills the MSB of + STARTING_SS_NUM in bit 31. If this is set, it will cause + PDG to indicate to PHY > 4-stream transmission resulting + in an abort in EHT R1 chips. + + TODO: Cleanup for EHT R2 chips + +*/ + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000 + + +/* Description TARGET_RSSI + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + Indicates the target received signal power of the the HE + trigger-based PPDU response. The resolution for the Target + RSSI in the Per User Info field is 1dB + + Values 0 to 90 maps to -110 dBm to -20 dBm + Other values are reserved. + + Value 127 indicates to the STA to transmit an HE triggerbased + PPDU response at its maximum transmit power for the assigned + MCS. If Trigger_type = ax_tb_ranging_trigger and Ranging_Trigger_Subtype + = TF_Sound or TF_Secure_Sound, value 127 indicates to the + STA to transmit an HE TB-ranging NDP response at its maximum + transmit power for MCS 0. + + Used for power control algorithm + +*/ + +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000 + + +/* Description CODING_TYPE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + indicates the code type of the HE trigger-based PPDU response + of the STA identified by User Identifier subfield. + 0: BCC + 1: LDPC + +*/ + +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000 + + +/* Description MPDU_MU_SPACING_FACTOR + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Basic trigger variant user info + + + + + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000 + + +/* Description TID_AGGREGATION_LIMIT + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Basic trigger variant user info + + indicates the of the number of TIDs that can be aggregated + by a STA in a multi-TID A-MPDU carried in the responding + Trigger-based PPDU + + + TXPCU will also evaluate this field, when trigger type is + Basic trigger. In that case, when this field is 0, TXPCU + will not send any data from user 0, but will immediately + go to user 1, which has the QoSNULL data frames... + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000 + + +/* Description RESERVED_5B + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000 + + +/* Description PREFERED_AC + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Basic trigger variant user info + + + + + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000 + + +/* Description BAR_CONTROL_ACK_POLICY + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Bar control field ack policy extracted from the trigger + frame + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000 + + +/* Description BAR_CONTROL_MULTI_TID + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Bar control field multi_tid extracted from the trigger frame + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000 + + +/* Description BAR_CONTROL_COMPRESSED_BITMAP + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Bar control field compressed bitmap extracted from the trigger + frame + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000 + + +/* Description BAR_CONTROL_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Bar control field reserved part extracted from the trigger + frame + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000 + + +/* Description BAR_CONTROL_TID_INFO + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Bar control field tid info extracted from the trigger frame + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000 + + +/* Description NR0_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=0 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + + +/* Description NR0_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=0 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + + +/* Description NR0_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=0 + + OR + + Field only valid if the BAR control type indicates Basic + Block ACK request + + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + + +/* Description NR0_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=0 + + OR + + Field valid if the BAR control type indicates Basic Block + ACK request + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + + +/* Description NR1_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=1 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + + +/* Description NR1_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=1 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + + +/* Description NR1_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=1 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + + +/* Description NR1_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=1 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + + +/* Description NR2_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=2 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + + +/* Description NR2_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=2 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + + +/* Description NR2_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=2 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + + +/* Description NR2_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=2 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + + +/* Description NR3_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=3 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + + +/* Description NR3_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=3 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + + +/* Description NR3_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=3 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + + +/* Description NR3_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=3 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + + +/* Description NR4_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=4 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + + +/* Description NR4_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=4 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + + +/* Description NR4_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=4 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + + +/* Description NR4_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=4 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + + +/* Description NR5_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=5 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + + +/* Description NR5_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=5 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + + +/* Description NR5_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=5 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + + +/* Description NR5_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=5 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + + +/* Description NR6_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=6 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + + +/* Description NR6_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=6 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + + +/* Description NR6_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=6 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + + +/* Description NR6_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=6 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + + +/* Description NR7_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=7 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + + +/* Description NR7_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=7 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + + +/* Description NR7_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=7 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + + +/* Description NR7_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=7 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + + +/* Description FB_SEGMENT_RETRANSMISSION_BITMAP + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Beamforming_report_poll trigger variant user info + + Segment information field extracted from the trigger frame + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff + + +/* Description RESERVED_14A + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + This field is only valid if the trigger was received in + an EHT PPDU. + + The 6-bit value used in U-SIG and/or EHT-SIG Common field + for the puncture pattern + +*/ + +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00 + + +/* Description DOT11BE_PUNCTURE_BITMAP + + This field is only valid if the trigger was received in + an EHT PPDU. + + The bitmap of 20 MHz sub-bands valid in the EHT PPDU reception + + + RXPCU gets this from the received U-SIG and/or EHT-SIG via + PHY microcode. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000 + + +/* Description RX_CHAIN_MASK + + Description dependent on the setting of field Rx_chain_mask_type. + + + The chain mask at the start of the reception of this frame + when Rx_chain_mask_type is set to 1'b0. In this mode used + in 11ax TPC calculations for UL OFDMA/MIMO and has to be + in sync with the rssi_comb value as this is also used by + the MAC for the TPC calculations. + + + The final rx chain mask used for the frame reception when + Rx_chain_mask_type is set to 1'b1 + + each bit is one antenna + 0: the chain is NOT used + 1: the chain is used + + Supports up to 8 chains + +*/ + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000 + + +/* Description RX_DURATION_FIELD + + The duration field embedded in the received trigger frame. + + PDG uses this field to calculate what the duration field + value should be in the response frame. + This is returned to the TX PCU + +*/ + +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000 + + +/* Description SCRAMBLER_SEED + + This field provides the 7-bit seed for the data scrambler. + + Used in response generation to MU-RTS trigger, where CTS + needs to have the same scrambler seed as the RTS + +*/ + +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000 + + +/* Description RX_CHAIN_MASK_TYPE + + Indicates if the field rx_chain_mask represents the mask + at start of reception (on which the Rssi_comb value is + based), or the setting used during the remainder of the + reception + + 1'b0: rxtd.listen_pri80_mask + 1'b1: Final receive mask + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + + +/* Description RESERVED_0A + + +*/ + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + + +/* Description NORMALIZED_PRE_RSSI_COMB + + Combined pre_rssi of all chains, but "normalized" back to + a single chain. This avoids PDG from having to evaluate + this in combination with receive chain mask and perform + all kinds of pre-processing algorithms. + + Based on primary channel RSSI. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 + + +/* Description NORMALIZED_RSSI_COMB + + Combined rssi of all chains, but "normalized" back to a + single chain. This avoids PDG from having to evaluate this + in combination with receive chain mask and perform all + kinds of pre-processing algorithms. + + Based on primary channel RSSI. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 + + +/* Description SW_PEER_ID + + Used by the PHY to correlated received trigger frames with + an AP and calculate long term statistics for this AP + +*/ + +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 + + +/* Description RESPONSE_TX_DURATION + + Field filled in by PDG based on the value that is given + in field response_Length in the RECEIVED_TRIGGER_INFO TLV + + + The amount of time the transmission of the HW response shall + take (in us) + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000 + + +/* Description RANGING_TRIGGER_SUBTYPE + + Indicates the Trigger subtype for the current ranging TF + + + + + + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000000f + + +/* Description TBR_TRIGGER_COMMON_INFO_79_68 + + Field only valid if Trigger_type = ax_tb_ranging_trigger + + + Ranging trigger variant common info + + Includes fields "Reserved," "Token," "Sounding Dialog Token + Number" + + If the Trigger Dependent Common Info sub-field is less than + 16 bits, the upper bits are set to 0. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0 + + +/* Description TBR_TRIGGER_SOUND_RESERVED_20_12 + + Field only valid if Trigger_type = ax_tb_ranging_trigger + and Ranging_Trigger_Subtype = TF_Sound or TF_Secure_Sound + + + Ranging trigger variant sounding/secure sounding sub-variant + user info bits [20:12] + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000 + + +/* Description I2R_REP + + Field only valid if Trigger_type = ax_tb_ranging_trigger + and Ranging_Trigger_Subtype = TF_Sound or TF_Secure_Sound + + + Ranging trigger variant sounding/secure sounding sub-variant + user info field "I2R Rep" + + PDG uses this to to populate Nrep in 'MACTX_11AZ_USER_DESC_PER_USER.' + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000 + + +/* Description TBR_TRIGGER_SOUND_RESERVED_25_24 + + Field only valid if Trigger_type = ax_tb_ranging_trigger + and Ranging_Trigger_Subtype = TF_Sound or TF_Secure_Sound + + + Ranging trigger variant sounding/secure sounding sub-variant + user info bits [25:24] + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000 + + +/* Description RESERVED_18A + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + Reserved bit 39 in the Trigger 'User Info' + + In case of an EHT AP, the bit 39 of the Trigger 'User Info' + called 'PS160' is used along with HE_SIGA_Reserved to determine + EHT_trigger_response. In case of EHT, 'PS160' is also included + in the MSB of field RU_allocation. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000 + + +/* Description QOS_NULL_ONLY_RESPONSE_TX + + Field filled in by PDG based on Rxpcu_PCIe_L0_req_duration + + + If based on the duration for which RXPCU has asserted the + 'L0 request' signal to PCIe and the PCIe L1SS exit + MAC + + PHY Tx latencies, PDG determines that null delimiters + + a programmable minimum MPDU size cannot fit the trigger + response, PDG sets this bit. + + HWSCH uses this bit to determine whether to select only + the 'SCHEDULER_CMD' with Trig_resp_qos_null_only set, i.e. + which transmit only QoS Nulls. + + This is filled as zero if ILP is unsupported or disabled + +*/ + +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000 + + +/* Description TBR_TRIGGER_SOUND_SAC + + Field only valid if Trigger_type = ax_tb_ranging_trigger + and Ranging_Trigger_Subtype = TF_Secure_Sound + + Ranging trigger variant secure sounding sub-variant user + info field "SAC" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000 + + +/* Description RESERVED_19A + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000 + + +/* Description U_SIG_RESERVED2 + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + Indicates the values of the 5 'disregard' bits [41:37] in + the U-SIG of the EHT_TRIG PPDU transmitted as a response + to the Trigger frame + +*/ + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000 + + +/* Description RESERVED_19B + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + Reserved bits in the Trigger + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000 + + +/* Description EHT_SPECIAL_AID12 + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + The AID12 subfield of the Special User Info field should + be '2007' for EHT R1 triggers. + + Note strictly needed, but added here for debugging purposes. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff + + +/* Description PHY_VERSION + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + The PHY version should be '0' for EHT R1 triggers. + + Note strictly needed, but added here for debugging purposes. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000 + + +/* Description BANDWIDTH_EXT + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + + + This along with the field Bandwidth determines the HE-SIG-A/U-SIG + BW value for the HE/EHT Trigger-based PPDU. + + Bandwidth/Bandwidth_ext: + 0/0: 20 MHz + 1/0: 40 MHz + 2/0: 80 MHz + 3/1: 160 MHz + 3/2: 320 MHz channelization 1 + 3/3: 320 MHz channelization 2 + All other cominations are reserved. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000 + + +/* Description EHT_SPATIAL_REUSE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + Indicates the value of the Spatial Reuse in the U-SIG of + the EHT_TRIG PPDU transmitted as a response to the Trigger + frame + +*/ + +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000 + + +/* Description U_SIG_RESERVED1 + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + Indicates the values of the 6 'disregard' bits [25:20] and + 1 'validate' bit [28] in the U-SIG of the EHT_TRIG PPDU + transmitted as a response to the Trigger frame + +*/ + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000 + + +/* Description EHT_TRIGGER_SPECIAL_USER_INFO_71_40 + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Trigger Dependent field in Special User Info + + If the Trigger Dependent User Info sub-field is less than + 32 bits, the upper bits are set to 0. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000 + + + +#endif // OFDMA_TRIGGER_DETAILS diff --git a/drivers/staging/fw-api/hw/qcn6432/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/qcn6432/pcu_ppdu_setup_init.h new file mode 100644 index 0000000000000000000000000000000000000000..bc413e6f4ba87b653be188eb1cbf855cf2f565ee --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/pcu_ppdu_setup_init.h @@ -0,0 +1,7454 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PCU_PPDU_SETUP_INIT_H_ +#define _PCU_PPDU_SETUP_INIT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 + +#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29 + + +struct pcu_ppdu_setup_init { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t medium_prot_type : 3, // [2:0] + response_type : 5, // [7:3] + response_info_part2_required : 1, // [8:8] + response_to_response : 3, // [11:9] + mba_user_order : 2, // [13:12] + expected_mba_size : 11, // [24:14] + required_ul_mu_resp_user_count : 6, // [30:25] + transmitted_bssid_check_en : 1; // [31:31] + uint32_t mprot_required_bw1 : 1, // [0:0] + mprot_required_bw20 : 1, // [1:1] + mprot_required_bw40 : 1, // [2:2] + mprot_required_bw80 : 1, // [3:3] + mprot_required_bw160 : 1, // [4:4] + mprot_required_bw240 : 1, // [5:5] + mprot_required_bw320 : 1, // [6:6] + ppdu_allowed_bw1 : 1, // [7:7] + ppdu_allowed_bw20 : 1, // [8:8] + ppdu_allowed_bw40 : 1, // [9:9] + ppdu_allowed_bw80 : 1, // [10:10] + ppdu_allowed_bw160 : 1, // [11:11] + ppdu_allowed_bw240 : 1, // [12:12] + ppdu_allowed_bw320 : 1, // [13:13] + set_fc_pwr_mgt : 1, // [14:14] + use_cts_duration_for_data_tx : 1, // [15:15] + update_timestamp_64 : 1, // [16:16] + update_timestamp_32_lower : 1, // [17:17] + update_timestamp_32_upper : 1, // [18:18] + reserved_1a : 13; // [31:19] + uint32_t insert_timestamp_offset_0 : 16, // [15:0] + insert_timestamp_offset_1 : 16; // [31:16] + uint32_t max_bw40_try_count : 4, // [3:0] + max_bw80_try_count : 4, // [7:4] + max_bw160_try_count : 4, // [11:8] + max_bw240_try_count : 4, // [15:12] + max_bw320_try_count : 4, // [19:16] + insert_wur_timestamp_offset : 6, // [25:20] + update_wur_timestamp : 1, // [26:26] + wur_embedded_bssid_present : 1, // [27:27] + insert_wur_fcs : 1, // [28:28] + reserved_3b : 3; // [31:29] + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_hw_response_tx_duration : 16, // [15:0] + r2r_rx_duration_field : 16; // [31:16] + uint32_t r2r_group_id : 6, // [5:0] + r2r_response_frame_type : 4, // [9:6] + r2r_sta_partial_aid : 11, // [20:10] + use_address_fields_for_protection : 1, // [21:21] + r2r_set_required_response_time : 1, // [22:22] + reserved_29a : 3, // [25:23] + r2r_bw20_active_channel : 3, // [28:26] + r2r_bw40_active_channel : 3; // [31:29] + uint32_t r2r_bw80_active_channel : 3, // [2:0] + r2r_bw160_active_channel : 3, // [5:3] + r2r_bw240_active_channel : 3, // [8:6] + r2r_bw320_active_channel : 3, // [11:9] + r2r_bw20 : 3, // [14:12] + r2r_bw40 : 3, // [17:15] + r2r_bw80 : 3, // [20:18] + r2r_bw160 : 3, // [23:21] + r2r_bw240 : 3, // [26:24] + r2r_bw320 : 3, // [29:27] + reserved_30a : 2; // [31:30] + uint32_t mu_response_expected_bitmap_31_0 : 32; // [31:0] + uint32_t mu_response_expected_bitmap_36_32 : 5, // [4:0] + mu_expected_response_cbf_count : 6, // [10:5] + mu_expected_response_sta_count : 6, // [16:11] + transmit_includes_multidestination : 1, // [17:17] + insert_prev_tx_start_timing_info : 1, // [18:18] + insert_current_tx_start_timing_info : 1, // [19:19] + tx_start_transmit_time_byte_offset : 12; // [31:20] + uint32_t protection_frame_ad1_31_0 : 32; // [31:0] + uint32_t protection_frame_ad1_47_32 : 16, // [15:0] + protection_frame_ad2_15_0 : 16; // [31:16] + uint32_t protection_frame_ad2_47_16 : 32; // [31:0] + uint32_t dynamic_medium_prot_threshold : 24, // [23:0] + dynamic_medium_prot_type : 1, // [24:24] + reserved_54a : 7; // [31:25] + uint32_t protection_frame_ad3_31_0 : 32; // [31:0] + uint32_t protection_frame_ad3_47_32 : 16, // [15:0] + protection_frame_ad4_15_0 : 16; // [31:16] + uint32_t protection_frame_ad4_47_16 : 32; // [31:0] +#else + uint32_t transmitted_bssid_check_en : 1, // [31:31] + required_ul_mu_resp_user_count : 6, // [30:25] + expected_mba_size : 11, // [24:14] + mba_user_order : 2, // [13:12] + response_to_response : 3, // [11:9] + response_info_part2_required : 1, // [8:8] + response_type : 5, // [7:3] + medium_prot_type : 3; // [2:0] + uint32_t reserved_1a : 13, // [31:19] + update_timestamp_32_upper : 1, // [18:18] + update_timestamp_32_lower : 1, // [17:17] + update_timestamp_64 : 1, // [16:16] + use_cts_duration_for_data_tx : 1, // [15:15] + set_fc_pwr_mgt : 1, // [14:14] + ppdu_allowed_bw320 : 1, // [13:13] + ppdu_allowed_bw240 : 1, // [12:12] + ppdu_allowed_bw160 : 1, // [11:11] + ppdu_allowed_bw80 : 1, // [10:10] + ppdu_allowed_bw40 : 1, // [9:9] + ppdu_allowed_bw20 : 1, // [8:8] + ppdu_allowed_bw1 : 1, // [7:7] + mprot_required_bw320 : 1, // [6:6] + mprot_required_bw240 : 1, // [5:5] + mprot_required_bw160 : 1, // [4:4] + mprot_required_bw80 : 1, // [3:3] + mprot_required_bw40 : 1, // [2:2] + mprot_required_bw20 : 1, // [1:1] + mprot_required_bw1 : 1; // [0:0] + uint32_t insert_timestamp_offset_1 : 16, // [31:16] + insert_timestamp_offset_0 : 16; // [15:0] + uint32_t reserved_3b : 3, // [31:29] + insert_wur_fcs : 1, // [28:28] + wur_embedded_bssid_present : 1, // [27:27] + update_wur_timestamp : 1, // [26:26] + insert_wur_timestamp_offset : 6, // [25:20] + max_bw320_try_count : 4, // [19:16] + max_bw240_try_count : 4, // [15:12] + max_bw160_try_count : 4, // [11:8] + max_bw80_try_count : 4, // [7:4] + max_bw40_try_count : 4; // [3:0] + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_rx_duration_field : 16, // [31:16] + r2r_hw_response_tx_duration : 16; // [15:0] + uint32_t r2r_bw40_active_channel : 3, // [31:29] + r2r_bw20_active_channel : 3, // [28:26] + reserved_29a : 3, // [25:23] + r2r_set_required_response_time : 1, // [22:22] + use_address_fields_for_protection : 1, // [21:21] + r2r_sta_partial_aid : 11, // [20:10] + r2r_response_frame_type : 4, // [9:6] + r2r_group_id : 6; // [5:0] + uint32_t reserved_30a : 2, // [31:30] + r2r_bw320 : 3, // [29:27] + r2r_bw240 : 3, // [26:24] + r2r_bw160 : 3, // [23:21] + r2r_bw80 : 3, // [20:18] + r2r_bw40 : 3, // [17:15] + r2r_bw20 : 3, // [14:12] + r2r_bw320_active_channel : 3, // [11:9] + r2r_bw240_active_channel : 3, // [8:6] + r2r_bw160_active_channel : 3, // [5:3] + r2r_bw80_active_channel : 3; // [2:0] + uint32_t mu_response_expected_bitmap_31_0 : 32; // [31:0] + uint32_t tx_start_transmit_time_byte_offset : 12, // [31:20] + insert_current_tx_start_timing_info : 1, // [19:19] + insert_prev_tx_start_timing_info : 1, // [18:18] + transmit_includes_multidestination : 1, // [17:17] + mu_expected_response_sta_count : 6, // [16:11] + mu_expected_response_cbf_count : 6, // [10:5] + mu_response_expected_bitmap_36_32 : 5; // [4:0] + uint32_t protection_frame_ad1_31_0 : 32; // [31:0] + uint32_t protection_frame_ad2_15_0 : 16, // [31:16] + protection_frame_ad1_47_32 : 16; // [15:0] + uint32_t protection_frame_ad2_47_16 : 32; // [31:0] + uint32_t reserved_54a : 7, // [31:25] + dynamic_medium_prot_type : 1, // [24:24] + dynamic_medium_prot_threshold : 24; // [23:0] + uint32_t protection_frame_ad3_31_0 : 32; // [31:0] + uint32_t protection_frame_ad4_15_0 : 16, // [31:16] + protection_frame_ad3_47_32 : 16; // [15:0] + uint32_t protection_frame_ad4_47_16 : 32; // [31:0] +#endif +}; + + +/* Description MEDIUM_PROT_TYPE + + Self Gen Medium Protection type used + + + + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x0000000000000007 + + +/* Description RESPONSE_TYPE + + PPDU transmission Response type expected + + Used by PDG to calculate the anticipated response duration + time. + + Used by TXPCU to prepare for expecting to receive a response. + + + After transmission of this + frame, no response in SIFS time is expected + + When TXPCU sees this setting, it shall not generated the + EXPECTED_RESPONSE TLV. + + RXPCU should never see this setting + An ACK frame is expected as response + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 64 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 256 bitmap is expected. + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending + NDP or BR-Poll. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + PDG uses the size info and assumes + single BA format with ACK and 64 bitmap embedded. + If SW expects more bitmaps in case of multi-TID, is shall + program the 'Extend_duration_value_bw...' field for additional + duration time. + For TXPCU only the fact that an ACK and/or BA is received + is important. Reception of only ACK or BA is also considered + a success. + SW also typically sets this when sending VHT single MPDU. + Some chip vendors might send BA rather than ACK in response + to VHT single MPDU but still we want to accept BA as well. + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after queuing RTS frame + as standalone packet and sending it. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending PS-Poll. + + + For TXPCU either ACK and/or data reception is considered + success. + PDG basis it's response duration calculation on an ACK. + For the data portion, SW shall program the 'Extend_duration_value_bw...' + field + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for + 11ah usage + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO MU_Response_BA_bitmap + if indeed BA was received + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_data_bitmap + and MU_Response_BA_bitmap if indeed BA and data was received + + When selected, CBF frames are expected to be received in + MU reception (uplink OFDMA or uplink MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_cbf_bitmap + if indeed CBF frames were received. + When selected, MPDU frames + are expected in the MU reception (uplink OFDMA or uplink + MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_bitmap + if indeed frames were received. + Any response expected + to be send to this device in SIFS time is acceptable. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any frame in the medium to + this or any other device, is acceptable as response. + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any MU frameless + reception generated by the PHY is acceptable. + + PHY indicates this type of reception explicitly in TLV PHYRX_RSSI_LEGACY, + field Reception_type == reception_is_frameless + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU. + + This can be used for complex MU-MIMO or OFDMA scenarios, + like receiving MU-CTS. + + PDG can not calculate the uplink duration. Therefor SW shall + program the 'Extend_duration_value_bw...' field + SW sets this after + sending ranging NDPA followed by NDP as an ISTA and NDP + and LMR (Action No Ack) are expected as back-to-back reception + in SIFS. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 512 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 1024 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + When selected, CTS2S + frames are expected to be received in MU reception (uplink + OFDMA) + + RXPCU shall check each response for CTS2S and report to + TXPCU. + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed CTS2S + frames were received. + When selected, UL NDP + frames are expected to be received in MU reception (uplink + spatial multiplexing) + + RXPCU shall check each response for NDP and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed NDP + frames were received. + When selected, LMR frames + are expected to be received in MU reception (uplink OFDMA + or uplink MIMO) + + RXPCU shall check each response for LMR and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed LMR + frames were received. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x00000000000000f8 + + +/* Description RESPONSE_INFO_PART2_REQUIRED + + Field only valid when Response_type is NOT set to No_response_expected + + + When set to 1, RXPCU shall generate the RECEIVED_RESPONSE_INFO_PART2 + TLV after having received the response frame. TXPCU shall + wait for this TLV before sending the TX_FES_STATUS_END + TLV. + + When NOT set, RXPCU shall NOT generate the above mentioned + TLV. TXPCU shall not wait for this TLV and after having + received RECEIVED_RESPONSE_INFO TLV, it can immediately + generate the TX_FES_STATUS_END TLV. + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0000000000000100 + + +/* Description RESPONSE_TO_RESPONSE + + Field indicates if after receiving an expected PPDU response + (as indicated by the Response_type), TXPCU is expected + to generate a reponse to that response + + Example: OFDMA trigger frame is sent, with expected response + being UL OFDMA data, which result in a response to the + response of MBA + + No response after response allowed. + The response after response that TXPCU is + allowed to generate is a single BA. Even if RXPCU is indicating + that multiple users are received, TXPCU shall only send + a BA for 1 STA. Response_to_response rates can be found + in fields 'response_to_response_rate_info_bw...' + The response after response that TXPCU is + allowed to generate is only Multi Destination Multi User + BA. Response_to_response rates can be found in fields 'response_to_response_rate_info_bw...' + + + A response to response + is expected to be generated. In other words, RXPCU will + likely indicate to TXPCU at the end of upcoming reception + that a response is needed. TXPCU is however to ignore this + indication from RXPCU, and assume for a moment that no + response to response is needed, as all the details on how + to handle this is provided in the next scheduling command, + which is marked as a 'response_to_response' type. + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x0000000000000e00 + + +/* Description MBA_USER_ORDER + + Field only valid in case of 'response_to_response' set to + MU_BA. + + TXPCU shall ask RXPCU for + BA info for all TX users, in order from user 0 to user + N + TXPCU shall ask RXPCU + for BA info for all TX users, but let RXPCU determine in + which order the BA bitmaps for each user shall be returned. + Note that RXPCU might return some 'invalid' bitmaps in case + there was no data received from all the users. + TXPCU shall ask RXPCU for + BA info for the number RX users that RXPCU indicated in + the 'Max_rx_user_count' in the RX_PPDU_START TLV. TXPCU + shall let RXPCU determine in which order the BA bitmaps + for each user shall be returned. Note that RXPCU might + still return some 'invalid' bitmaps in case there were only + frames with FCS errors for some of the users + TXPCU shall ask + RXPCU for BA info for the number bitmaps that RXPCU indicated + in the (SUM of) response_ack_count, response_ba64_count, + response_ba256_count fields in RX_RESPONSE_REQUIRED. TXPCU + shall let RXPCU determine in which order the BA bitmaps + for each user (and sometimes multiple bitmaps for a the + same user in case of multi TID) shall be returned. It is + not expected that RXPCU will return invalid bitmaps for + this scenario as RXPCU earlier indicates that this number + of bitmaps was actually available in RXPCU... + + +*/ + +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x0000000000003000 + + +/* Description EXPECTED_MBA_SIZE + + Field only valid for: + Mba_user_order == mu_ba_fixed_user_order, mu_ba_optimized_user_order + + + The expected number of bytes in response (Multi destination) + BA that TXPCU shall request to PDG. + NOTE that SW should have pre-calculated and thus looked-up + the window sizes for each of the STAs. + +*/ + +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x0000000001ffc000 + + +/* Description REQUIRED_UL_MU_RESP_USER_COUNT + + Field only valid for: Response_to_response + == MU_BA + or + RESPONSE_TO_RESPONSE_CMD + + Field MU_RX_successful_user_count as reported in the RECEIVED_RESPONSE_INFO + TLV shall be >= to this field, in order to consider the + reception successful. + + Note that the value in this field shall always be equal + or smaller to the number of bits set in field MU_Response_expected_bitmap_.... + + +*/ + +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x000000007e000000 + + +/* Description TRANSMITTED_BSSID_CHECK_EN + + When set to 1, RXPCU shall assume group addressed frame + with Tx_AD2 equal to TBSSID was sent. RxPCU should properly + handle receive frame(s) from STA(s) which A1 is TBSSID + or any VAPs.When NOT set, RXPCU shall compare received frame's + A1 with Tx_AD2 only. + +*/ + +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0000000080000000 + + +/* Description MPROT_REQUIRED_BW1 + + Field only valid when ppdu_allowed_bw1 is set. + + When set, Medium protection transmission is required for + a 1 MHz bandwidth PPDU transmission. In case of MU transmissions, + all the medium protection settings are coming from user0. +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 32 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 32 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x0000000100000000 + + +/* Description MPROT_REQUIRED_BW20 + + Field only valid when ppdu_allowed_bw20_bw2 is set. + + NOTE: This field is also known as Mprot_required_pattern_0 + in case punctured transmission is enabled. + + When set, Medium protection transmission is required for + a 20 MHz or 2Mhz 11ah bandwidth PPDU transmission + +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 33 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 33 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x0000000200000000 + + +/* Description MPROT_REQUIRED_BW40 + + Field only valid when ppdu_allowed_bw40_bw4 is set. + + NOTE: This field is also known as Mprot_required_pattern_1 + in case punctured transmission is enabled. + + When set, Medium protection transmission is required for + a 40 MHz or 4Mhz 11ah bandwidth PPDU transmission + +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 34 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 34 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x0000000400000000 + + +/* Description MPROT_REQUIRED_BW80 + + Field only valid when ppdu_allowed_bw80_bw8 is set. + + + NOTE: This field is also known as Mprot_required_pattern_2 + in case punctured transmission is enabled. + + When set, Medium protection transmission is required for + a 80 MHz or 8MHz 11ah bandwidth PPDU transmission + +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 35 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 35 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x0000000800000000 + + +/* Description MPROT_REQUIRED_BW160 + + Field only valid when ppdu_allowed_bw160_bw16 is set. + + NOTE: This field is also known as Mprot_required_pattern_3 + in case punctured transmission is enabled. + + When set, Medium protection transmission is required for + a 160 MHz or 16MHz 11ah bandwidth PPDU transmission. + +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 36 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 36 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x0000001000000000 + + +/* Description MPROT_REQUIRED_BW240 + + Field only valid when ppdu_allowed_bw240 is set. + + NOTE: This field is also known as Mprot_required_pattern_4 + in case punctured transmission is enabled. + + When set, Medium protection transmission is required for + a 240 MHz bandwidth PPDU transmission. + +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 37 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 37 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x0000002000000000 + + +/* Description MPROT_REQUIRED_BW320 + + Field only valid when ppdu_allowed_bw320 is set. + + NOTE: This field is also known as Mprot_required_pattern_5 + in case punctured transmission is enabled. + + When set, Medium protection transmission is required for + a 320 MHz bandwidth PPDU transmission. + +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 38 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 38 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x0000004000000000 + + +/* Description PPDU_ALLOWED_BW1 + + When set, allow PPDU transmission with 1 MHz 11ah bandwidth. + + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 39 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 39 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x0000008000000000 + + +/* Description PPDU_ALLOWED_BW20 + + Field Not valid in case punctured transmission is enabled. + This fields meaning is than taken over by field TX_PUNCTURE_SETUP. + + puncture_pattern_count + + When set, allow PPDU transmission with 20 MHz or 2MHz 11ah + bandwidth + + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 40 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 40 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x0000010000000000 + + +/* Description PPDU_ALLOWED_BW40 + + Field Not valid in case punctured transmission is enabled. + This fields meaning is than taken over by field TX_PUNCTURE_SETUP. + + puncture_pattern_count + + When set, allow PPDU transmission with 40 MHz or 4MHz 11ah + bandwidth + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 41 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 41 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x0000020000000000 + + +/* Description PPDU_ALLOWED_BW80 + + Field Not valid in case punctured transmission is enabled. + This fields meaning is than taken over by field TX_PUNCTURE_SETUP. + + puncture_pattern_count + + When set, allow PPDU transmission with 80 MHz or 8MHz 11ah + bandwidth + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 42 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 42 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x0000040000000000 + + +/* Description PPDU_ALLOWED_BW160 + + Field Not valid in case punctured transmission is enabled. + This fields meaning is than taken over by field TX_PUNCTURE_SETUP. + + puncture_pattern_count + + When set, allow PPDU transmission with 160 MHz or 16MHz + 11ah bandwidth + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 43 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 43 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x0000080000000000 + + +/* Description PPDU_ALLOWED_BW240 + + Field Not valid in case punctured transmission is enabled. + This fields meaning is than taken over by field TX_PUNCTURE_SETUP. + + puncture_pattern_count + + When set, allow PPDU transmission with 240 MHz bandwidth + + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 44 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 44 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x0000100000000000 + + +/* Description PPDU_ALLOWED_BW320 + + Field Not valid in case punctured transmission is enabled. + This fields meaning is than taken over by field TX_PUNCTURE_SETUP. + + puncture_pattern_count + + When set, allow PPDU transmission with 320 MHz bandwidth + + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 45 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 45 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x0000200000000000 + + +/* Description SET_FC_PWR_MGT + + Field valid for SU transmissions only + + When set, the TXPCU will set the power management bit in + the Frame Control field for the transmitted frames. + + Note: this is there for backup purposes only. TXOLE is the + module now that should be setting the pm bit to the proper + value. + + +*/ + +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 46 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 46 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x0000400000000000 + + +/* Description USE_CTS_DURATION_FOR_DATA_TX + + When set, take the value of the duration field from the + CTS frame, and use this as the reference point for how long + the 'data' ppdu transmission can be. + This is an E2E feature. + +*/ + +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 47 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 47 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x0000800000000000 + + +/* Description UPDATE_TIMESTAMP_64 + + When set, TXPCU shall update the timestamp value at the + indicated location. + +*/ + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 48 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 48 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x0001000000000000 + + +/* Description UPDATE_TIMESTAMP_32_LOWER + + Update the 32 bit timestamp at the offset specified by the + insert_timestamp_offset_32. This will be used for AWDL + action frames. The value of the TSF will be added to the + timestamp field in the packet buffer in memory. The tx_delay + should also be included in the timestamp field + +*/ + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 49 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 49 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x0002000000000000 + + +/* Description UPDATE_TIMESTAMP_32_UPPER + + Update the 64 bit TSF at the offset specified by the insert_timestamp_offset_64. + This will be used for beacons and probe response frames. + The value of the TSF will be added to the TSF field in + the packet buffer in memory. The tx_delay should also be + included in the TSF field + +*/ + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 50 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 50 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x0004000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff8000000000000 + + +/* Description INSERT_TIMESTAMP_OFFSET_0 + + Byte offset to the first byte of the lower 32 bit timestamp + to be inserted. This is applicable to both beacon and + probe response TSF and the AWDL timestamp +*/ + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x000000000000ffff + + +/* Description INSERT_TIMESTAMP_OFFSET_1 + + Byte offset to the first byte of the upper 32 bit timestamp + to be inserted. This is applicable to both beacon and + probe response TSF and the AWDL timestamp +*/ + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0x00000000ffff0000 + + +/* Description MAX_BW40_TRY_COUNT + + Field only valid when ppdu_allowed_bw40_bw4 or Mprot_required_bw40_bw4 + is set. + + NOTE: This field is also known as Max_try_count_pattern_1 + in case punctured transmission is enabled. + + The maximum number of times that TXPCU will try to do a + transmission at this or a higher BW, before deciding to + go to a lower BW. + If this count (as indicated by field Optimal_bw_retry_count + in TX_FES_SETUP) has not been reached yet, and this BW + is not available, TXPCU will generate a flush with flush + reason set to 'TXPCU_FLREQ_RETRY_FOR_OPTIMAL_BW.' + + When value is 0, it means that if this BW is not available, + TXPCU should immediately try a lower BW. + + Note that this value shall always be equal or greater then: + Max_bw80_try_count + + +*/ + +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 32 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 35 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f00000000 + + +/* Description MAX_BW80_TRY_COUNT + + Field only valid when ppdu_allowed_bw80_bw4 or Mprot_required_bw80_bw4 + is set. + + NOTE: This field is also known as Max_try_count_pattern_2 + in case punctured transmission is enabled. + + The maximum number of times that TXPCU will try to do a + transmission at this or a higher BW, before deciding to + go to a lower BW. + If this count (as indicated by field Optimal_bw_retry_count + in TX_FES_SETUP) has not been reached yet, and this BW + is not available, TXPCU will generate a flush with flush + reason set to 'TXPCU_FLREQ_RETRY_FOR_OPTIMAL_BW.' + + When value is 0, it means that if this BW is not available, + TXPCU should immediately try a lower BW. + + Note that this value shall always be equal or greater then: + Max_bw160_try_count + + +*/ + +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 36 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 39 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f000000000 + + +/* Description MAX_BW160_TRY_COUNT + + Field only valid when ppdu_allowed_bw160_bw16 or Mprot_required_bw160_bw16 + is set. + + NOTE: This field is also known as Max_try_count_pattern_3 + in case punctured transmission is enabled. + + The maximum number of times that TXPCU will try to do a + transmission at this, before deciding to go to a lower BW. + + If this count (as indicated by field Optimal_bw_retry_count + in TX_FES_SETUP) has not been reached yet, and this BW + is not available, TXPCU will generate a flush with flush + reason set to 'TXPCU_FLREQ_RETRY_FOR_OPTIMAL_BW.' + + When value is 0, it means that if this BW is not available, + TXPCU should immediately try a lower BW. + + +*/ + +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 40 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 43 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f0000000000 + + +/* Description MAX_BW240_TRY_COUNT + + Field only valid when ppdu_allowed_bw240 or Mprot_required_bw240 + is set. + + NOTE: This field is also known as Max_try_count_pattern_4 + in case punctured transmission is enabled. + + The maximum number of times that TXPCU will try to do a + transmission at this, before deciding to go to a lower BW. + + If this count (as indicated by field Optimal_bw_retry_count + in TX_FES_SETUP) has not been reached yet, and this BW + is not available, TXPCU will generate a flush with flush + reason set to 'TXPCU_FLREQ_RETRY_FOR_OPTIMAL_BW.' + + When value is 0, it means that if this BW is not available, + TXPCU should immediately try a lower BW. + + +*/ + +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 44 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 47 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f00000000000 + + +/* Description MAX_BW320_TRY_COUNT + + Field only valid when ppdu_allowed_bw320 or Mprot_required_bw320 + is set. + + NOTE: This field is also known as Max_try_count_pattern_5 + in case punctured transmission is enabled. + + The maximum number of times that TXPCU will try to do a + transmission at this, before deciding to go to a lower BW. + + If this count (as indicated by field Optimal_bw_retry_count + in TX_FES_SETUP) has not been reached yet, and this BW + is not available, TXPCU will generate a flush with flush + reason set to 'TXPCU_FLREQ_RETRY_FOR_OPTIMAL_BW.' + + When value is 0, it means that if this BW is not available, + TXPCU should immediately try a lower BW. + + +*/ + +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 48 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 51 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f000000000000 + + +/* Description INSERT_WUR_TIMESTAMP_OFFSET + + Field only to be used in case PCU_PPDU_SETUP_START.pkt_type + indicates a .11ba packet + + Used by TXPCU to determine the offset within a WUR packet, + e.g. a WUR beacon into which to insert the timestamp. + + +*/ + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 52 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 57 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f0000000000000 + + +/* Description UPDATE_WUR_TIMESTAMP + + Field only to be used in case PCU_PPDU_SETUP_START.pkt_type + indicates a .11ba packet + + TXPCU will insert the timestamp into a WUR packet if this + bit is set. + + +*/ + +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 58 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 58 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x0400000000000000 + + +/* Description WUR_EMBEDDED_BSSID_PRESENT + + Field only to be used in case PCU_PPDU_SETUP_START.pkt_type + indicates a .11ba packet + + If this bit is set, TXPCU will assume the packet includes + an extra 16 bits which contain the embedded BSSID to be + used in the WUR FCS calculation. TXPCU will replace the + 16 bits with the 16-bit FCS field. + If this bit is clear, TXPCU will append the 16-bit FCS calculated + without any embedded BSSID. + + +*/ + +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 59 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 59 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x0800000000000000 + + +/* Description INSERT_WUR_FCS + + Field only to be used in case PCU_PPDU_SETUP_START.pkt_type + indicates a .11ba packet + + TXPCU will replace/append the FCS bytes for a WUR packet + if this bit is set. The replace/append choice is based + on WUR_embedded_BSSID_present. + + +*/ + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 60 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 60 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x1000000000000000 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xe000000000000000 + + +/* Description RESPONSE_TO_RESPONSE_RATE_INFO_BW20 + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + NOTE: This field is also known as response_to_response_rate_info_pattern_0 + in case punctured transmission is enabled. + + Used by TXPCU to determine what the transmit rates are for + the response to response transmission in case original + transmission was 20 MHz. + + Note: + see field R2R_bw20_active_channel for the BW of this transmission + +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x0000000000000001 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x000000001e000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x0000000020000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x0000000040000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x0000000080000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff00000000 + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x0007000000000000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x3800000000000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x000000000000000f + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x0000000000000070 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x0000000000000080 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x000000000000ff00 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x0000000000ff0000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0x00000000ff000000 + + +/* Description RESERVED_3A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000ff00000000 + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x0000030000000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00003c0000000000 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MASK 0x0000c00000000000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff000000000000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff00000000000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x0000000000000001 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x0000000000002000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + + +/* Description RESERVED_4A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0x00000000f8000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x0000040000000000 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x0000380000000000 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + + +/* Description RESERVED_5A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f0000000000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + + +/* Description RESERVED_0A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + + +/* Description RESPONSE_TO_RESPONSE_RATE_INFO_BW40 + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + NOTE: This field is also known as response_to_response_rate_info_pattern_1 + in case punctured transmission is enabled. + + Used by TXPCU to determine what the transmit rates are for + the response to response transmission in case original + transmission was 40 MHz. + + Note: + see field R2R_bw40_active_channel for the BW of this transmission + +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x0000000100000000 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e00000000000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x2000000000000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x4000000000000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x8000000000000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x00000000000000ff + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x0000000000070000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x0000000038000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x0000000f00000000 + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x0000007000000000 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x0000008000000000 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff000000000000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff00000000000000 + + +/* Description RESERVED_3A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x00000000000000ff + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x0000000000000300 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x0000000000003c00 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MASK 0x000000000000c000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x0000000000ff0000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0x00000000ff000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x0000000100000000 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x0000200000000000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + + +/* Description RESERVED_4A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf800000000000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x0000000000000400 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x0000000000003800 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + + +/* Description RESERVED_5A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x0000000003f00000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + + +/* Description RESERVED_0A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + + +/* Description RESPONSE_TO_RESPONSE_RATE_INFO_BW80 + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + NOTE: This field is also known as response_to_response_rate_info_pattern_2 + in case punctured transmission is enabled. + + Used by TXPCU to determine what the transmit rates are for + the response to response transmission in case original + transmission was 80 MHz. + + Note: + see field R2R_bw80_active_channel for the BW of this transmission + +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x0000000000000001 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x000000001e000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x0000000020000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x0000000040000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x0000000080000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff00000000 + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x0007000000000000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x3800000000000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x000000000000000f + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x0000000000000070 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x0000000000000080 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x000000000000ff00 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x0000000000ff0000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0x00000000ff000000 + + +/* Description RESERVED_3A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000ff00000000 + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x0000030000000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00003c0000000000 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MASK 0x0000c00000000000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff000000000000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff00000000000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x0000000000000001 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x0000000000002000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + + +/* Description RESERVED_4A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0x00000000f8000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x0000040000000000 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x0000380000000000 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + + +/* Description RESERVED_5A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f0000000000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + + +/* Description RESERVED_0A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + + +/* Description RESPONSE_TO_RESPONSE_RATE_INFO_BW160 + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + NOTE: This field is also known as response_to_response_rate_info_pattern_3 + in case punctured transmission is enabled. + + Used by TXPCU to determine what the transmit rates are for + the response to response transmission in case original + transmission was 160 MHz. + + Note: + see field R2R_bw160_active_channel for the BW of this transmission + +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x0000000100000000 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e00000000000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x2000000000000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x4000000000000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x8000000000000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x00000000000000ff + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x0000000000070000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x0000000038000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x0000000f00000000 + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x0000007000000000 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x0000008000000000 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff000000000000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000 + + +/* Description RESERVED_3A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x00000000000000ff + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x0000000000000300 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x0000000000003c00 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MASK 0x000000000000c000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x0000000000ff0000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0x00000000ff000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x0000000100000000 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x0000200000000000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + + +/* Description RESERVED_4A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf800000000000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x0000000000000400 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + + +/* Description RESERVED_5A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x0000000003f00000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + + +/* Description RESERVED_0A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + + +/* Description RESPONSE_TO_RESPONSE_RATE_INFO_BW240 + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + NOTE: This field is also known as response_to_response_rate_info_pattern_4 + in case punctured transmission is enabled. + + Used by TXPCU to determine what the transmit rates are for + the response to response transmission in case original + transmission was 240 MHz. + + Note: + see field R2R_bw240_active_channel for the BW of this transmission + +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x0000000000000001 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x000000001e000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x0000000020000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x0000000040000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x0000000080000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff00000000 + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x0007000000000000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x3800000000000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x000000000000000f + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x0000000000000070 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x0000000000000080 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x000000000000ff00 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x0000000000ff0000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000 + + +/* Description RESERVED_3A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000ff00000000 + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x0000030000000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00003c0000000000 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MASK 0x0000c00000000000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff000000000000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff00000000000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x0000000000000001 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x0000000000002000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + + +/* Description RESERVED_4A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0x00000000f8000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x0000040000000000 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + + +/* Description RESERVED_5A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f0000000000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + + +/* Description RESERVED_0A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + + +/* Description RESPONSE_TO_RESPONSE_RATE_INFO_BW320 + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + NOTE: This field is also known as response_to_response_rate_info_pattern_5 + in case punctured transmission is enabled. + + Used by TXPCU to determine what the transmit rates are for + the response to response transmission in case original + transmission was 320 MHz. + + Note: + see field R2R_bw320_active_channel for the BW of this transmission + +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x0000000100000000 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e00000000000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x2000000000000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x4000000000000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x8000000000000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x00000000000000ff + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x0000000000070000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x0000000038000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x0000000f00000000 + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x0000007000000000 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x0000008000000000 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff000000000000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000 + + +/* Description RESERVED_3A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x00000000000000ff + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x0000000000000300 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x0000000000003c00 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MASK 0x000000000000c000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x0000000000ff0000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0x00000000ff000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x0000000100000000 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x0000200000000000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + + +/* Description RESERVED_4A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf800000000000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x0000000000000400 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + + +/* Description RESERVED_5A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x0000000003f00000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + + +/* Description RESERVED_0A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + + +/* Description R2R_HW_RESPONSE_TX_DURATION + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + The amount of time the transmission of the HW response to + response will take (in us) + + Used for coex as well as e.g. for sync MLO to align R2R + times on the medium across multiple channels + + This field also represents the 'alt_hw_response_tx_duration'. + Note that this implies that no different duration can be + programmed for the default and alt setting. SW should program + the worst case value in the RXPCU table in case they are + different. + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x000000000000ffff + + +/* Description R2R_RX_DURATION_FIELD + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + The duration field assumed to have been received in the + response frame and what will be used in the duration field + calculation for the response_to_response_Frame + + PDG uses this field to calculate what the duration field + value should be in the response frame. + This is returned to the TXPCU + + Note that if PDG has protection in place to wrap around... + I the actual transmit time is larger then the value programmed + here, PDG HW will set the duration field in the response + to response frame to zero. + + This field is used in 11ah mode as well + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0x00000000ffff0000 + + +/* Description R2R_GROUP_ID + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + Specifies the Group ID to be used in the response to response + frame. + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 37 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f00000000 + + +/* Description R2R_RESPONSE_FRAME_TYPE + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + Response_frame_type to be indicated in the PDG_RESPONSE + TLV for the response to response frame. + + Coex related field + + also used for M-BA + + + + + + + + + + This can be a multi STA BA or multi TID BA + + + NDP followed by LMR response for + Rx ranging NDPA followed by NDP + + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 38 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 41 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c000000000 + + +/* Description R2R_STA_PARTIAL_AID + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + Specifies the partial AID of the response to response frame + in case it is transmitted at VHT rates. + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 42 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 52 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc0000000000 + + +/* Description USE_ADDRESS_FIELDS_FOR_PROTECTION + + When set, the protection_frame_ad1/ad2 fields are to be + used for RTS/CTS2S frames + + When set and not disabled through a TXPCU register bit, + the protection_frame_ad2* fields are also copied to the + tx_ad2* fields of the 'EXPECTED_RESPONSE' TLV (i.e. the + expected response Rx AD1) to RXPCU for all frames. + + +*/ + +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 53 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 53 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x0020000000000000 + + +/* Description R2R_SET_REQUIRED_RESPONSE_TIME + + Field only valid in case of response to response + + When set, TXPCU shall copy the R2R_Hw_response_tx_duration + field and pass it on to PDG in field required_response_time + in 'PDG_RESPONSE.' + + This allows SW to force an R2R time e.g. in case of sync + MLO, making sure that the R2R times on the medium for multiple + links are aligned. + + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 54 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 54 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x0040000000000000 + + +/* Description RESERVED_29A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 55 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x0380000000000000 + + +/* Description R2R_BW20_ACTIVE_CHANNEL + + Field only valid for 20 BW + + NOTE: This field is also known as R2R_active_channel_pattern_0 + in case punctured transmission is enabled. + + This field indicates the active frequency band when the + initial trigger frame transmission was in 20 MHz + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 58 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 60 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c00000000000000 + + +/* Description R2R_BW40_ACTIVE_CHANNEL + + Field only valid for 40 BW + + NOTE: This field is also known as R2R_active_channel_pattern_1 + in case punctured transmission is enabled. + + This field indicates the active frequency band when the + initial trigger frame transmission was in 40 MHz + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 61 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 63 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe000000000000000 + + +/* Description R2R_BW80_ACTIVE_CHANNEL + + Field only valid for 80 BW + + NOTE: This field is also known as R2R_active_channel_pattern_2 + in case punctured transmission is enabled. + + This field indicates the active frequency band when the + initial trigger frame transmission was in 80 MHz + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x0000000000000007 + + +/* Description R2R_BW160_ACTIVE_CHANNEL + + Field only valid for 160 BW + + NOTE: This field is also known as R2R_active_channel_pattern_3 + in case punctured transmission is enabled. + + This field indicates the active frequency band when the + initial trigger frame transmission was in 160 MHz + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x0000000000000038 + + +/* Description R2R_BW240_ACTIVE_CHANNEL + + Field only valid for 240 BW + + NOTE: This field is also known as R2R_active_channel_pattern_4 + in case punctured transmission is enabled. + + This field indicates the active frequency band when the + initial trigger frame transmission was in 240 MHz + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x00000000000001c0 + + +/* Description R2R_BW320_ACTIVE_CHANNEL + + Field only valid for 320 BW + + NOTE: This field is also known as R2R_active_channel_pattern_5 + in case punctured transmission is enabled. + + This field indicates the active frequency band when the + initial trigger frame transmission was in 320 MHz + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x0000000000000e00 + + +/* Description R2R_BW20 + + The BW for the response to response frame when the initial + trigger frame transmission was in 20 MHz + + NOTE: This field is also known as R2R_pattern_0 in case + punctured transmission is enabled. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x0000000000007000 + + +/* Description R2R_BW40 + + The BW for the response to response frame when the initial + trigger frame transmission was in 40 MHz + + NOTE: This field is also known as R2R_pattern_1 in case + punctured transmission is enabled. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x0000000000038000 + + +/* Description R2R_BW80 + + The BW for the response to response frame when the initial + trigger frame transmission was in 80 MHz + + NOTE: This field is also known as R2R_pattern_2 in case + punctured transmission is enabled. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x00000000001c0000 + + +/* Description R2R_BW160 + + The BW for the response to response frame when the initial + trigger frame transmission was in 160 MHz + + NOTE: This field is also known as R2R_pattern_3 in case + punctured transmission is enabled. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x0000000000e00000 + + +/* Description R2R_BW240 + + The BW for the response to response frame when the initial + trigger frame transmission was in 240 MHz + + NOTE: This field is also known as R2R_pattern_4 in case + punctured transmission is enabled. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x0000000007000000 + + +/* Description R2R_BW320 + + The BW for the response to response frame when the initial + trigger frame transmission was in 320 MHz + + NOTE: This field is also known as R2R_pattern_5 in case + punctured transmission is enabled. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x0000000038000000 + + +/* Description RESERVED_30A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MASK 0x00000000c0000000 + + +/* Description MU_RESPONSE_EXPECTED_BITMAP_31_0 + + Field only valid in case of MU transmission and a response + from other or more then just user0 is expected. + + Note that this implies that for all legacy SU exchanges, + or legacy MU-MIMO where only user 0 can get a response, + this field does not need to be programmed by SW. All existing + programming remains backwards compatible. + + Bit 0 represents user 0 + Bit 1 represents user 1 + ... + When set, a response from this user is expected, and TXPCU + shall generate the 'tx_fes_status_user_response' TLV for + this user + + Note that the number of bits set in bitmap fields 0 - 36 + (including next field), shall always be equal or greater + then the number indicated in field: Required_UL_MU_resp_user_count + + +*/ + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff00000000 + + +/* Description MU_RESPONSE_EXPECTED_BITMAP_36_32 + + Field only valid in case of MU transmission and a response + from other or more then just user0 is expected. + + Note that this implies that for all legacy SU exchanges, + or legacy MU-MIMO where only user 0 can get a response, + this field does not need to be programmed by SW. All existing + programming remains backwards compatible. + + Bit 0 represents user 32 + Bit 1 represents user 33 + ... + When set, a response from this user is expected, and TXPCU + shall generate the 'tx_fes_status_user_response' TLV for + this user + + Note that the number of bits set in bitmap fields 0 - 36 + (including previous field), shall always be equal or greater + then the number indicated in field: Required_UL_MU_resp_user_count + + +*/ + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x000000000000001f + + +/* Description MU_EXPECTED_RESPONSE_CBF_COUNT + + Field only valid when Response_type == MU_CBF_expected + + The number of STAs that are expected to send a CBF back + + Note that the actual amount could be smaller.... + +*/ + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x00000000000007e0 + + +/* Description MU_EXPECTED_RESPONSE_STA_COUNT + + SW shall program this field if the number of STAs that are + expected to send something (ACK, DATA, BA, CBF, etc...) + back is 2 or larger.. + + The number of STAs that are expected to send a response + back. + + Note that the actual amount could be smaller.... + +*/ + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x000000000001f800 + + +/* Description TRANSMIT_INCLUDES_MULTIDESTINATION + + Used by TXPCU + + When set, the MD (Multi Destination) feature is used for + this transmission. Either for real multi destination STA + transmissions or Multi TID transmissions. + + Used by TXPCU to know when it can start pre-fetching data + in order to do BW constrained frame drops. + + +*/ + +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x0000000000020000 + + +/* Description INSERT_PREV_TX_START_TIMING_INFO + + When set, TXPCU will insert the value in TXPCU register "prev_phy_tx_start_transmit_time" + in the transmit frame at the byte location indicated by + field tx_start_transmit_time_byte_offset + +*/ + +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x0000000000040000 + + +/* Description INSERT_CURRENT_TX_START_TIMING_INFO + + When set, TXPCU will insert the value in TXPCU register "current_phy_tx_start_transmit_time" + in the transmit frame at the byte location indicated by + field tx_start_transmit_time_byte_offset + +*/ + +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x0000000000080000 + + +/* Description TX_START_TRANSMIT_TIME_BYTE_OFFSET + + Field only valid when insert_prev_tx_start_timing_info or + insert_current_tx_start_timing_info is set. + Start byte offset where the 'start_time' needs to be overwritten + in the frame + +*/ + +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0x00000000fff00000 + + +/* Description PROTECTION_FRAME_AD1_31_0 + + Field only valid when use_address_fields_for_protection + is set + + The Least Significant 4 bytes of the Protection Frame MAC + Address AD1 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff00000000 + + +/* Description PROTECTION_FRAME_AD1_47_32 + + Field only valid when use_address_fields_for_protection + is set + + The 2 most significant bytes of the Protection Frame MAC + Address AD1 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x000000000000ffff + + +/* Description PROTECTION_FRAME_AD2_15_0 + + Field only valid when use_address_fields_for_protection + is set + + The Least Significant 2 bytes of the MAC Address AD2 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0x00000000ffff0000 + + +/* Description PROTECTION_FRAME_AD2_47_16 + + Field only valid when use_address_fields_for_protection + is set + + The 4 most significant bytes of the MAC Address AD2 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff00000000 + + +/* Description DYNAMIC_MEDIUM_PROT_THRESHOLD + + Threshold to enable the dynamic medium protection feature + in terms of PPDU duration in us or PSDU length in bytes + + + This is set to zero to disable the dynamic medium protection + feature. + + +*/ + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x0000000000ffffff + + +/* Description DYNAMIC_MEDIUM_PROT_TYPE + + dynamic_medium_prot_threshold + indicates PSDU length in bytes. + + dynamic_medium_prot_threshold indicates PPDU duration in + us. + +*/ + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x0000000001000000 + + +/* Description RESERVED_54A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0x00000000fe000000 + + +/* Description PROTECTION_FRAME_AD3_31_0 + + Field only valid when use_address_fields_for_protection + is set + + The least significant 4 bytes of the Protection Frame MAC + Address AD3 + + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff00000000 + + +/* Description PROTECTION_FRAME_AD3_47_32 + + Field only valid when use_address_fields_for_protection + is set + + The 2 most significant bytes of the Protection Frame MAC + Address AD3 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x000000000000ffff + + +/* Description PROTECTION_FRAME_AD4_15_0 + + Field only valid when use_address_fields_for_protection + is set + + The least significant 2 bytes of the Protection Frame MAC + Address AD4 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0x00000000ffff0000 + + +/* Description PROTECTION_FRAME_AD4_47_16 + + Field only valid when use_address_fields_for_protection + is set + + The 4 most significant bytes of the Protection Frame MAC + Address AD4 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff00000000 + + + +#endif // PCU_PPDU_SETUP_INIT diff --git a/drivers/staging/fw-api/hw/qcn6432/pdg_response.h b/drivers/staging/fw-api/hw/qcn6432/pdg_response.h new file mode 100644 index 0000000000000000000000000000000000000000..07285988b1a92745a917ae39c73f8718002c1187 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/pdg_response.h @@ -0,0 +1,1399 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PDG_RESPONSE_H_ +#define _PDG_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PDG_RESPONSE 12 + +#define NUM_OF_QWORDS_PDG_RESPONSE 6 + + +struct pdg_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t hw_response_tx_duration : 16, // [15:0] + rx_duration_field : 16; // [31:16] + uint32_t punctured_response_transmission : 1, // [0:0] + cca_subband_channel_bonding_mask : 16, // [16:1] + scrambler_seed_override : 2, // [18:17] + response_density_valid : 1, // [19:19] + response_density : 5, // [24:20] + more_data : 1, // [25:25] + duration_indication : 1, // [26:26] + relayed_frame : 1, // [27:27] + address_indicator : 1, // [28:28] + bandwidth : 3; // [31:29] + uint32_t ack_id : 16, // [15:0] + block_ack_bitmap : 16; // [31:16] + uint32_t response_frame_type : 4, // [3:0] + ack_id_ext : 10, // [13:4] + ftm_en : 1, // [14:14] + group_id : 6, // [20:15] + sta_partial_aid : 11; // [31:21] + uint32_t ndp_ba_start_seq_ctrl : 12, // [11:0] + active_channel : 3, // [14:12] + txop_duration_all_ones : 1, // [15:15] + frame_length : 16; // [31:16] +#else + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t rx_duration_field : 16, // [31:16] + hw_response_tx_duration : 16; // [15:0] + uint32_t bandwidth : 3, // [31:29] + address_indicator : 1, // [28:28] + relayed_frame : 1, // [27:27] + duration_indication : 1, // [26:26] + more_data : 1, // [25:25] + response_density : 5, // [24:20] + response_density_valid : 1, // [19:19] + scrambler_seed_override : 2, // [18:17] + cca_subband_channel_bonding_mask : 16, // [16:1] + punctured_response_transmission : 1; // [0:0] + uint32_t block_ack_bitmap : 16, // [31:16] + ack_id : 16; // [15:0] + uint32_t sta_partial_aid : 11, // [31:21] + group_id : 6, // [20:15] + ftm_en : 1, // [14:14] + ack_id_ext : 10, // [13:4] + response_frame_type : 4; // [3:0] + uint32_t frame_length : 16, // [31:16] + txop_duration_all_ones : 1, // [15:15] + active_channel : 3, // [14:12] + ndp_ba_start_seq_ctrl : 12; // [11:0] +#endif +}; + + +/* Description HW_RESPONSE_RATE_INFO + + All transmit rate related parameters +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000 + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x000000000000000f + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000 + + +/* Description RESERVED_3A + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff00000000 + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 45 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c0000000000 + + +/* Description RESERVED_3B + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 46 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c00000000000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + + +/* Description RESERVED_4A + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + + +/* Description RESERVED_5A + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + + +/* Description RESERVED_0A + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + + +/* Description HW_RESPONSE_TX_DURATION + + The amount of time the transmission of the HW response will + take (in us) + + Used for coex..... + + This field also represents the 'alt_hw_response_tx_duration'. + Note that this implies that no different duration can be + programmed for the default and alt setting. SW should program + the worst case value in the RXPCU table in case they are + different. + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000 + + +/* Description RX_DURATION_FIELD + + The duration field in the received frame. + PDG uses this field to calculate what the duration field + value should be in the response frame. + This is returned to the TX PCU + + This field is used in 11ah mode as well + +*/ + +#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48 +#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63 +#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000 + + +/* Description PUNCTURED_RESPONSE_TRANSMISSION + + When set, this response frame will be transmitted using + a puncture transmit pattern that is indicated in the cca_subband_channel_bonding_mask + field. + + Typically used in the Response to response transmissions. + + +*/ + +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001 + + +/* Description CCA_SUBBAND_CHANNEL_BONDING_MASK + + Field only valid when 'Punctured_response_transmission' + is set + + Indicates which 20 Mhz channels will be used for the transmission. + + + Bit 0: primary 20 Mhz + Bit 1: secondary 20 MHz. + Etc. + + +*/ + +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe + + +/* Description SCRAMBLER_SEED_OVERRIDE + + Used in dynamic BW RTS-CTS, BAR -BA, etc. kind of exchanges. + + + 0: PDG will use all 7 bits of the scrambler seed. + 1: PDG will override bits [6:5] of the scrambler_seed + with BW information. + 2: PDG will override bits [6:5] and bit [3] of the scrambler_seed + with BW information for .11be dynamic BW procedure. + + +*/ + +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000 + + +/* Description RESPONSE_DENSITY_VALID + + When set, field Response_density has valid info. TXPCU sets + this for multi segment CBF response generation. + +*/ + +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000 + + +/* Description RESPONSE_DENSITY + + Field only valid when Response_density_valid is set. + When Response_density_valid is NOT set, this field is set + to 0 + + The MPDU density is required for the response frame (in + us). PDG will translate this value into minimum number of + words per MPDU and give this back to TXPCU in TLV PCU_PPDU_SETUP_USER + field min_mpdu_spacing + + TXPCU gets this value from a register. + +*/ + +#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 +#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 +#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000 + + +/* Description MORE_DATA + + This setting is used for + NDP ACK response frames + NDP Modified ACK response frames + The value of this field comes from a register programming. + The register resides in TxPCU and is programmed by SW within + SIFS response time when responding with NDP ACK or NDP + Modified ACK. + +*/ + +#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_MORE_DATA_LSB 25 +#define PDG_RESPONSE_MORE_DATA_MSB 25 +#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000 + + +/* Description DURATION_INDICATION + + This setting is used for + NDP ACK response frames + NDP Modified ACK response frames + The value of this field comes from a register programming. + The register resides in TxPCU and is programmed by SW within + SIFS response time when responding with NDP ACK or NDP + Modified ACK. + +*/ + +#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000 + + +/* Description RELAYED_FRAME + + This setting is used to fill the field in the SIG preamble + for + NDP ACK response frame + This feature is not supported and TxPCU should program this + field to Zero. PDG will ignore this field. + +*/ + +#define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RELAYED_FRAME_LSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MASK 0x0000000008000000 + + +/* Description ADDRESS_INDICATOR + + This bit is used to fill the address_indicator field in + the SIG preamble of NDP CTS response frame. + + This feature is not supported and TxPCU should program this + field to Zero. PDG will use this field to populate the + NDP response frame + +*/ + +#define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x0000000010000000 + + +/* Description BANDWIDTH + + Packet bandwidth: + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_BANDWIDTH_LSB 29 +#define PDG_RESPONSE_BANDWIDTH_MSB 31 +#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000 + + +/* Description ACK_ID + + ACK_ID in NDP_ACK frames, NDP Modified ACK frames + + For BW > 1MHz + [15:0] = ack_id + + For BW = 1MHz + + [8:0] = ack_id + [15:9] = Reserved + For NDP BA + If BW=1MHz + [1:0] = Block ACK ID + [15:2] = Reserved + + If BW>1MHz + [5:0] = Block ACK ID + [15:2] = Reserved + +*/ + +#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_ACK_ID_LSB 32 +#define PDG_RESPONSE_ACK_ID_MSB 47 +#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000 + + +/* Description BLOCK_ACK_BITMAP + + Block Ack bitmap field for generating the NDP BA frames + in 1MHz and >= 2MHz + +*/ + +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000 + + +/* Description RESPONSE_FRAME_TYPE + + Coex related field + + also used for M-BA + + + + + + + + + + This can be a multi STA BA or multi TID BA + + + Ranging NDP response followed by + LMR response for Rx ranging NDPA followed by NDP + + +*/ + +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f + + +/* Description ACK_ID_EXT + + This is populated by TxPCU from the RX_RESPONSE_REQUIRED_INFO.ack_id_ext. + +*/ + +#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 +#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 +#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0 + + +/* Description FTM_EN + + This field is set to 1 if the response packet is either + an FTM_1 or an FTM_2 packet or an HE-Ranging NDP (11az). + + + 0: non-FTM frame + 1: FTM or HE-Randing NDP Frame + +*/ + +#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_FTM_EN_LSB 14 +#define PDG_RESPONSE_FTM_EN_MSB 14 +#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000 + + +/* Description GROUP_ID + + Specifies the Group ID of response frames transmitted at + VHT rates for MU transmissions. This filed applies to both + non-11ah and 11ah modes. +*/ + +#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_GROUP_ID_LSB 15 +#define PDG_RESPONSE_GROUP_ID_MSB 20 +#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000 + + +/* Description STA_PARTIAL_AID + + In 11AH mode of Operation: + + This field is used to populate the ID field in the SIG PPDUs + of BW>1MHz and non-NDP frames. For example, the use case + would be in a Speed Frame Exchange, we may be generating + the SIG PPDU in response and this field is needed to populate + the ID field in the SIGA preamble . This value is based + on the Table provided by 9.17b section of the Draft P802.11ah_D1.1 + Specification + + In 11AH mode of Operation: + + This field is also used to populate the field of RA/Parial_BSSID + in the NDP CTS response frames In non-11AH mode: + + In non-11AH mode of Operation: + + Specifies the partial AID of response frames transmitted + at VHT rates. + +*/ + +#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 +#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 +#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000 + + +/* Description NDP_BA_START_SEQ_CTRL + + Starting Sequence Control - Sequence number of the first + MPDU in the frame soliciting the Block Ack. +*/ + +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000 + + +/* Description ACTIVE_CHANNEL + + This field indicates the active frequency band when the + packet bandwidth is less than the channel bandwidth. For + non 11ax packets this is same as the primary channel + +*/ + +#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000 + + +/* Description TXOP_DURATION_ALL_ONES + + When set, either the TXOP_DURATION of the received frame + was set to all 1s or there is a BSS color collision. The + TXOP_DURATION of the transmit response should be forced + to all 1s. + + +*/ + +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000 + + +/* Description FRAME_LENGTH + + The response frame length in bytes + (This includes the FCS field) + +*/ + +#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_FRAME_LENGTH_LSB 48 +#define PDG_RESPONSE_FRAME_LENGTH_MSB 63 +#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000 + + + +#endif // PDG_RESPONSE diff --git a/drivers/staging/fw-api/hw/qcn6432/pdg_response_rate_setting.h b/drivers/staging/fw-api/hw/qcn6432/pdg_response_rate_setting.h new file mode 100644 index 0000000000000000000000000000000000000000..47572ca7ccdc417b0b4d82a8481256e162d62379 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/pdg_response_rate_setting.h @@ -0,0 +1,1033 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PDG_RESPONSE_RATE_SETTING_H_ +#define _PDG_RESPONSE_RATE_SETTING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 + + +struct pdg_response_rate_setting { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 1, // [0:0] + tx_antenna_sector_ctrl : 24, // [24:1] + pkt_type : 4, // [28:25] + smoothing : 1, // [29:29] + ldpc : 1, // [30:30] + stbc : 1; // [31:31] + uint32_t alt_tx_pwr : 8, // [7:0] + alt_min_tx_pwr : 8, // [15:8] + alt_nss : 3, // [18:16] + alt_tx_chain_mask : 8, // [26:19] + alt_bw : 3, // [29:27] + stf_ltf_3db_boost : 1, // [30:30] + force_extra_symbol : 1; // [31:31] + uint32_t alt_rate_mcs : 4, // [3:0] + nss : 3, // [6:4] + dpd_enable : 1, // [7:7] + tx_pwr : 8, // [15:8] + min_tx_pwr : 8, // [23:16] + tx_chain_mask : 8; // [31:24] + uint32_t reserved_3a : 8, // [7:0] + sgi : 2, // [9:8] + rate_mcs : 4, // [13:10] + reserved_3b : 2, // [15:14] + tx_pwr_1 : 8, // [23:16] + alt_tx_pwr_1 : 8; // [31:24] + uint32_t aggregation : 1, // [0:0] + dot11ax_bss_color_id : 6, // [6:1] + dot11ax_spatial_reuse : 4, // [10:7] + dot11ax_cp_ltf_size : 2, // [12:11] + dot11ax_dcm : 1, // [13:13] + dot11ax_doppler_indication : 1, // [14:14] + dot11ax_su_extended : 1, // [15:15] + dot11ax_min_packet_extension : 2, // [17:16] + dot11ax_pe_nss : 3, // [20:18] + dot11ax_pe_content : 1, // [21:21] + dot11ax_pe_ltf_size : 2, // [23:22] + dot11ax_chain_csd_en : 1, // [24:24] + dot11ax_pe_chain_csd_en : 1, // [25:25] + dot11ax_dl_ul_flag : 1, // [26:26] + reserved_4a : 5; // [31:27] + uint32_t dot11ax_ext_ru_start_index : 4, // [3:0] + dot11ax_ext_ru_size : 4, // [7:4] + eht_duplicate_mode : 2, // [9:8] + he_sigb_dcm : 1, // [10:10] + he_sigb_0_mcs : 3, // [13:11] + num_he_sigb_sym : 5, // [18:14] + required_response_time_source : 1, // [19:19] + reserved_5a : 6, // [25:20] + u_sig_puncture_pattern_encoding : 6; // [31:26] + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t required_response_time : 12, // [27:16] + dot11be_params_placeholder : 4; // [31:28] +#else + uint32_t stbc : 1, // [31:31] + ldpc : 1, // [30:30] + smoothing : 1, // [29:29] + pkt_type : 4, // [28:25] + tx_antenna_sector_ctrl : 24, // [24:1] + reserved_0a : 1; // [0:0] + uint32_t force_extra_symbol : 1, // [31:31] + stf_ltf_3db_boost : 1, // [30:30] + alt_bw : 3, // [29:27] + alt_tx_chain_mask : 8, // [26:19] + alt_nss : 3, // [18:16] + alt_min_tx_pwr : 8, // [15:8] + alt_tx_pwr : 8; // [7:0] + uint32_t tx_chain_mask : 8, // [31:24] + min_tx_pwr : 8, // [23:16] + tx_pwr : 8, // [15:8] + dpd_enable : 1, // [7:7] + nss : 3, // [6:4] + alt_rate_mcs : 4; // [3:0] + uint32_t alt_tx_pwr_1 : 8, // [31:24] + tx_pwr_1 : 8, // [23:16] + reserved_3b : 2, // [15:14] + rate_mcs : 4, // [13:10] + sgi : 2, // [9:8] + reserved_3a : 8; // [7:0] + uint32_t reserved_4a : 5, // [31:27] + dot11ax_dl_ul_flag : 1, // [26:26] + dot11ax_pe_chain_csd_en : 1, // [25:25] + dot11ax_chain_csd_en : 1, // [24:24] + dot11ax_pe_ltf_size : 2, // [23:22] + dot11ax_pe_content : 1, // [21:21] + dot11ax_pe_nss : 3, // [20:18] + dot11ax_min_packet_extension : 2, // [17:16] + dot11ax_su_extended : 1, // [15:15] + dot11ax_doppler_indication : 1, // [14:14] + dot11ax_dcm : 1, // [13:13] + dot11ax_cp_ltf_size : 2, // [12:11] + dot11ax_spatial_reuse : 4, // [10:7] + dot11ax_bss_color_id : 6, // [6:1] + aggregation : 1; // [0:0] + uint32_t u_sig_puncture_pattern_encoding : 6, // [31:26] + reserved_5a : 6, // [25:20] + required_response_time_source : 1, // [19:19] + num_he_sigb_sym : 5, // [18:14] + he_sigb_0_mcs : 3, // [13:11] + he_sigb_dcm : 1, // [10:10] + eht_duplicate_mode : 2, // [9:8] + dot11ax_ext_ru_size : 4, // [7:4] + dot11ax_ext_ru_start_index : 4; // [3:0] + uint32_t dot11be_params_placeholder : 4, // [31:28] + required_response_time : 12; // [27:16] + struct mlo_sta_id_details mlo_sta_id_details_rx; +#endif +}; + + +/* Description RESERVED_0A + + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 + + +/* Description RESERVED_3A + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00 + + +/* Description RESERVED_3B + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + + +/* Description RESERVED_4A + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + + +/* Description RESERVED_5A + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + + +/* Description RESERVED_0A + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + + + +#endif // PDG_RESPONSE_RATE_SETTING diff --git a/drivers/staging/fw-api/hw/qcn6432/pdg_tx_req.h b/drivers/staging/fw-api/hw/qcn6432/pdg_tx_req.h new file mode 100644 index 0000000000000000000000000000000000000000..27f177bd9c19855980f7a988479c291623838159 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/pdg_tx_req.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PDG_TX_REQ_H_ +#define _PDG_TX_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PDG_TX_REQ 2 + +#define NUM_OF_QWORDS_PDG_TX_REQ 1 + + +struct pdg_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_reason : 2, // [1:0] + use_puncture_pattern : 2, // [3:2] + req_bw : 3, // [6:4] + puncture_pattern_number : 6, // [12:7] + reserved_0b : 1, // [13:13] + req_paprd : 1, // [14:14] + duration_field_boundary_valid : 1, // [15:15] + duration_field_boundary : 16; // [31:16] + uint32_t puncture_subband_mask : 16, // [15:0] + reserved_0c : 16; // [31:16] +#else + uint32_t duration_field_boundary : 16, // [31:16] + duration_field_boundary_valid : 1, // [15:15] + req_paprd : 1, // [14:14] + reserved_0b : 1, // [13:13] + puncture_pattern_number : 6, // [12:7] + req_bw : 3, // [6:4] + use_puncture_pattern : 2, // [3:2] + tx_reason : 2; // [1:0] + uint32_t reserved_0c : 16, // [31:16] + puncture_subband_mask : 16; // [15:0] +#endif +}; + + +/* Description TX_REASON + + RTS, CTS2Self or 11h + protection type transmission preceding the regular PPDU + portion of the coming FES. + Regular PPDU transmission + that follows the transmission of medium protection frames:. + + Regular PPDU transmission without + preceding medium protection frame exchanges. + + Note: Response frame transmissions are initiated with the + PDG_RESPONSE TLV + + +*/ + +#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_TX_REASON_LSB 0 +#define PDG_TX_REQ_TX_REASON_MSB 1 +#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003 + + + +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c + + +/* Description REQ_BW + + Field not valid when use_puncture_pattern is set to PUNCTURE_FROM_TX_SETUP + + + The BW of the upcoming transmission. + Note: Coex might have changed this from the original request. + + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_REQ_BW_LSB 4 +#define PDG_TX_REQ_REQ_BW_MSB 6 +#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070 + + +/* Description PUNCTURE_PATTERN_NUMBER + + Field only valid when "use_puncture_pattern" is set. + + The pattern number in case punctured transmission is enabled + + +*/ + +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80 + + +/* Description RESERVED_0B + + +*/ + +#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_RESERVED_0B_LSB 13 +#define PDG_TX_REQ_RESERVED_0B_MSB 13 +#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000 + + +#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_REQ_PAPRD_LSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000 + + +/* Description DURATION_FIELD_BOUNDARY_VALID + + When set, PDG should take the 'duration_field_boundary' + value into account when it is calculating the TX and RX + boundaries for the upcoming transmission. Both RX and TX + should not go beyond this time duration provided. + + +*/ + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000 + + +/* Description DURATION_FIELD_BOUNDARY + + Field only valid when 'Duration_field_boundary_valid' is + set + + Amount of time to both TX and RX boundaries that PDG should + take into account for the upcoming transmission. + +*/ + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000 + + +/* Description PUNCTURE_SUBBAND_MASK + + Field only valid when use_puncture_pattern is set to PUNCTURE_FROM_ALL_ALLOWED_MODES + + + This mask indicates which 20 Mhz channels are actively used + in this transmission. + + Bit 0: primary 20 Mhz + Bit 1: secondary 20 MHz + Etc. + +*/ + +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000 + + +/* Description RESERVED_0C + + Reserved for future power bits: Generator should set to + 0, consumer shall ignore +*/ + +#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_RESERVED_0C_LSB 48 +#define PDG_TX_REQ_RESERVED_0C_MSB 63 +#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000 + + + +#endif // PDG_TX_REQ diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_abort_request_info.h new file mode 100644 index 0000000000000000000000000000000000000000..51ca3df60d45ce9cbbad4c8e010b8f020e72d176 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_abort_request_info.h @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ +#define _PHYRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 + + +struct phyrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phyrx_abort_reason : 8, // [7:0] + phy_enters_nap_state : 1, // [8:8] + phy_enters_defer_state : 1, // [9:9] + reserved_0 : 6, // [15:10] + receive_duration : 16; // [31:16] +#else + uint32_t receive_duration : 16, // [31:16] + reserved_0 : 6, // [15:10] + phy_enters_defer_state : 1, // [9:9] + phy_enters_nap_state : 1, // [8:8] + phyrx_abort_reason : 8; // [7:0] +#endif +}; + + +/* Description PHYRX_ABORT_REASON + + Reception aborted due to receiving + a PHY_OFF TLV + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Should not really be used. If + needed, ask for documentation update + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +*/ + +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff + + +/* Description PHY_ENTERS_NAP_STATE + + When set, PHY enters PHY NAP state after sending this abort + + + Note that nap and defer state are mutually exclusive. + + Field put pro-actively in place....usage still to be agreed + upon. + +*/ + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + + +/* Description PHY_ENTERS_DEFER_STATE + + When set, PHY enters PHY defer state after sending this + abort + + Note that nap and defer state are mutually exclusive. + + Field put pro-actively in place....usage still to be agreed + upon. + +*/ + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + + +/* Description RESERVED_0 + + +*/ + +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 10 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000fc00 + + +/* Description RECEIVE_DURATION + + The remaining receive duration of this PPDU in the medium + (in us). When PHY does not know this duration when this + TLV is generated, the field will be set to 0. + The timing reference point is the reception by the MAC of + this TLV. The value shall be accurate to within 2us. + + In case Phy_enters_nap_state and/or Phy_enters_defer_state + is set, there is a possibility that MAC PMM can also decide + to go into a low(er) power state. + +*/ + +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 + + + +#endif // PHYRX_ABORT_REQUEST_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_common_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..eaafa703b1fc54a2ef98b3369b1c0e0c6ab5205e --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_common_user_info.h @@ -0,0 +1,403 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_COMMON_USER_INFO_H_ +#define _PHYRX_COMMON_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4 + +#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2 + + +struct phyrx_common_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t receive_duration : 16, // [15:0] + reserved_0a : 16; // [31:16] + uint32_t u_sig_puncture_pattern_encoding : 6, // [5:0] + reserved_1a : 26; // [31:6] + uint32_t eht_ppdu_type : 2, // [1:0] + bss_color_id : 6, // [7:2] + dl_ul_flag : 1, // [8:8] + txop_duration : 7, // [15:9] + cp_setting : 2, // [17:16] + ltf_size : 2, // [19:18] + spatial_reuse : 4, // [23:20] + rx_ndp : 1, // [24:24] + dot11be_su_extended : 1, // [25:25] + reserved_2a : 6; // [31:26] + uint32_t eht_duplicate : 2, // [1:0] + eht_sig_cmn_field_type : 2, // [3:2] + doppler_indication : 1, // [4:4] + sta_id : 11, // [15:5] + puncture_bitmap : 16; // [31:16] +#else + uint32_t reserved_0a : 16, // [31:16] + receive_duration : 16; // [15:0] + uint32_t reserved_1a : 26, // [31:6] + u_sig_puncture_pattern_encoding : 6; // [5:0] + uint32_t reserved_2a : 6, // [31:26] + dot11be_su_extended : 1, // [25:25] + rx_ndp : 1, // [24:24] + spatial_reuse : 4, // [23:20] + ltf_size : 2, // [19:18] + cp_setting : 2, // [17:16] + txop_duration : 7, // [15:9] + dl_ul_flag : 1, // [8:8] + bss_color_id : 6, // [7:2] + eht_ppdu_type : 2; // [1:0] + uint32_t puncture_bitmap : 16, // [31:16] + sta_id : 11, // [15:5] + doppler_indication : 1, // [4:4] + eht_sig_cmn_field_type : 2, // [3:2] + eht_duplicate : 2; // [1:0] +#endif +}; + + +/* Description RECEIVE_DURATION + + The remaining receive duration of this PPDU in the medium + (in us). + The timing reference point is the assertion of 'rx_frame' + by PHY for the PPDU reception. The value shall be accurate + to within 2us. + RXPCU shall subtract the time elapsed between 'rx_frame' + assertion and reception of this TLV to find the actual remaining + receive duration. + +*/ + +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x000000000000ffff + + +/* Description RESERVED_0A + + +*/ + +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0x00000000ffff0000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + The 6-bit value used in U-SIG and/or EHT-SIG Common field + for the puncture pattern + +*/ + +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000000 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 32 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 37 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f00000000 + + +/* Description RESERVED_1A + + +*/ + +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 38 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 63 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0xffffffc000000000 + + +/* Description EHT_PPDU_TYPE + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + DO NOT USE + + Need to look at both EHT-SIG content + channels + Need to look at only one EHT-SIG content + channel + +*/ + +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_LSB 0 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MSB 1 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MASK 0x0000000000000003 + + +/* Description BSS_COLOR_ID + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + BSS color ID + + Field used by MAC HW + +*/ + +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x00000000000000fc + + +/* Description DL_UL_FLAG + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + Differentiates between DL and UL transmission + + + + +*/ + +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x0000000000000100 + + +/* Description TXOP_DURATION + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + Indicates the remaining time in the current TXOP + + Field used by MAC HW + +*/ + +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x000000000000fe00 + + +/* Description CP_SETTING + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + Legacy normal GI + Legacy short GI + HE related GI + HE related GI + +*/ + +#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x0000000000030000 + + +/* Description LTF_SIZE + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + Ltf size + + + + + +*/ + +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x00000000000c0000 + + +/* Description SPATIAL_REUSE + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + TODO: Placeholder + +*/ + +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x0000000000f00000 + + +/* Description RX_NDP + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + On RX side, looked at by MAC HW + + When set, PHY has received an (expected) NDP frame + +*/ + +#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24 +#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24 +#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x0000000001000000 + + +/* Description DOT11BE_SU_EXTENDED + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + On RX side, evaluated by MAC HW + + This is the only way for MAC RX to know that this was a + U_SIG_EHT_SU received in extended range format. + + When set, the 11be frame is of the extended range format. + + +*/ + +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_LSB 25 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MSB 25 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MASK 0x0000000002000000 + + +/* Description RESERVED_2A + + +*/ + +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0x00000000fc000000 + + +/* Description EHT_DUPLICATE + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 32 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 33 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x0000000300000000 + + +/* Description EHT_SIG_CMN_FIELD_TYPE + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + Indicates the type of EHT-SIG Common field + + Non-OFDMA, EHT-SIG Common field + does not contain puncturing information + Non-OFDMA, EHT-SIG Common field + contains puncturing information + + OFDMA, EHT-SIG Common field contains RU structure + +*/ + +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_LSB 34 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MSB 35 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MASK 0x0000000c00000000 + + +/* Description DOPPLER_INDICATION + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 36 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 36 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x0000001000000000 + + +/* Description STA_ID + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV + and EHT_PPDU_type is EHT_PPDU_MU (MU-MIMO or OFDMA). + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 37 +#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 47 +#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe000000000 + + +/* Description PUNCTURE_BITMAP + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV + and EHT_SIG_CMN_field_type is EHT_SIG_CMN_PUNC. + + Indicates which 20 MHz sub-bands will be modulated vs punctured + (bits [15:0]) in CCA order (primary/secondary) + + Bit 0: primary 20MHz sub-band + Bit 1: secondary 20 MHz sub-band + Bit 2: first 20 MHz sub-band in secondary 40 MHz + Bit 3: second 20 MHz sub-band in secondary 40 MHz + ... + Bit 15: last 20MHz sub-band in secondary 160 MHz + A value of 0 means the band is punctured + A value of 1 means the band is modulated + + If the PPDU BW is less than 320 MHz, the MSB bits are reserved + and set to 0. +*/ + +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 48 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 63 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff000000000000 + + + +#endif // PHYRX_COMMON_USER_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_a_mu_dl.h new file mode 100644 index 0000000000000000000000000000000000000000..524cc25c90d2963ada694e173ca2c78bbbb7bddc --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_a_mu_dl.h @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ +#define _PHYRX_HE_SIG_A_MU_DL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1 + + +struct phyrx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#endif +}; + + +/* Description PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + NOTE: This is unsupported for "HE MU" format (including "MU_SU") + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 + + +/* Description MCS_OF_SIG_B + + Indicates the MCS of HE-SIG-B + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e + + +/* Description DCM_OF_SIG_B + + Indicates whether dual sub-carrier modulation is applied + to HE-SIG-B + + 0: No DCM for HE_SIG_B + 1: DCM for HE_SIG_B + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 + + +/* Description SPATIAL_REUSE + + Spatial reuse + + For 20MHz one SR field corresponding to entire 20MHz (other + 3 fields indicate identical values) + For 40MHz two SR fields for each 20MHz (other 2 fields indicate + identical values) + For 80MHz four SR fields for each 20MHz + For 160MHz four SR fields for each 40MHz + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + 20 Mhz + 40 Mhz + 80 MHz non-preamble puncturing + mode + 160 MHz and 80+80 MHz non-preamble + puncturing mode + for preamble puncturing + in 80 MHz, where in the preamble only the secondary 20 + MHz is punctured + for preamble + puncturing in 80 MHz, where in the preamble only one of + the two 20 MHz sub-channels in secondary 40 MHz is punctured. + + for preamble puncturing + in 160 MHz or 80+80 MHz, where in the primary 80 MHz of + the preamble only the secondary 20 MHz is punctured. + for preamble + puncturing in 160 MHz or 80+80 MHz, where in the primary + 80 MHz of the preamble the primary 40 MHz is present. + + On RX side, Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 + + +/* Description NUM_SIG_B_SYMBOLS + + Number of symbols + + For OFDMA, the actual number of symbols is 1 larger then + indicated in this field. + + For MU-MIMO this is equal to the number of users - 1: the + following encoding is used: + 1 => 2 users + 2 => 3 users + Etc. + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 + + +/* Description COMP_MODE_SIG_B + + Indicates the compression mode of HE-SIG-B + + 0: Regular [uncomp mode] + 1: compressed mode (full-BW MU-MIMO only) + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 + + +/* Description CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + 4xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + 4x LTF + 3.2 µs CP + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 + + +/* Description DOPPLER_INDICATION + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 + + +/* Description RESERVED_0A + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + +/* Description RESERVED_1A + + Note: spec indicates this shall be set to 1 + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + + +/* Description NUM_LTF_SYMBOLS + + Indicates the number of HE-LTF symbols + + 0: 1 LTF + 1: 2 LTFs + 2: 4 LTFs + 3: 6 LTFs + 4: 8 LTFs + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 + + +/* Description LDPC_EXTRA_SYMBOL + + If LDPC, + 0: LDPC extra symbol not present + 1: LDPC extra symbol present + Else + Set to 1 + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 + + +/* Description STBC + + Indicates whether STBC is applied + 0: No STBC + 1: STBC + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // PHYRX_HE_SIG_A_MU_DL diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_a_mu_ul.h new file mode 100644 index 0000000000000000000000000000000000000000..a167f98e20273585ccea15006dd182421cfe5708 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_a_mu_ul.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ +#define _PHYRX_HE_SIG_A_MU_UL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1 + + +struct phyrx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +#endif +}; + + +/* Description PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description FORMAT_INDICATION + + Indicates whether the transmission is SU PPDU or a trigger + based UL MU PDDU + + + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + + +/* Description BSS_COLOR_ID + + BSS color ID + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e + + +/* Description SPATIAL_REUSE + + Spatial reuse + + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 + + +/* Description RESERVED_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + On RX side, Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 + + +/* Description RESERVED_0B + + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + +/* Description RESERVED_1A + + Set to value indicated in the trigger frame + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + This CRC may also cover some fields of L-SIG (TBD) + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + BCC encoding (similar to VHT-SIG-A) with 6 tail bits is + used + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // PHYRX_HE_SIG_A_MU_UL diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_a_su.h new file mode 100644 index 0000000000000000000000000000000000000000..38ffef5f286109572e737321bbbd8a67a30b7155 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_a_su.h @@ -0,0 +1,497 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HE_SIG_A_SU_H_ +#define _PHYRX_HE_SIG_A_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1 + + +struct phyrx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#endif +}; + + +/* Description PHYRX_HE_SIG_A_SU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description FORMAT_INDICATION + + + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + + +/* Description BEAM_CHANGE + + Indicates whether spatial mapping is changed between legacy + and HE portion of preamble. If not, channel estimation + can include legacy preamble to improve accuracy + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 + + +/* Description TRANSMIT_MCS + + Indicates the data MCS + + Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 + + +/* Description DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 + + +/* Description RESERVED_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 + + +/* Description SPATIAL_REUSE + + Spatial reuse + + For 20MHz one SR field corresponding to entire 20MHz (other + 3 fields indicate identical values) + For 40MHz two SR fields for each 20MHz (other 2 fields indicate + identical values) + For 80MHz four SR fields for each 20MHz + For 160MHz four SR fields for each 40MHz + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + For HE SU PPDU + + + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + For HE Extended Range SU PPDU + Set to 0 for 242-tone RU + + Set to 1 for right 106-tone RU within + the primary 20 MHz + + On RX side, Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 + + +/* Description CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + NOTE: + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 + + +/* Description NSTS + + Indicates number of streams used for the SU transmission + + + For HE SU PPDU + + + Set to n for n+1 space time stream, + where n = 0, 1, 2,.....,7. + + + + + For HE Extended Range PPDU + + + Set to 0 for 1 space time stream. + Value 1 is TBD + + + + Values 2 - 7 are reserved + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 + + +/* Description RESERVED_0B + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + +/* Description CODING + + Distinguishes between BCC and LDPC coding. + + 0: BCC + 1: LDPC + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 + + +/* Description LDPC_EXTRA_SYMBOL + + If LDPC, + 0: LDPC extra symbol not present + 1: LDPC extra symbol present + Else + Set to 1 + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 + + +/* Description STBC + + Indicates whether STBC is applied + 0: No STBC + 1: STBC + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 + + +/* Description RESERVED_1A + + Note: per standard, set to 1 + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 + + +/* Description DOPPLER_INDICATION + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description DOT11AX_SU_EXTENDED + + TX side: + Set to 0 + + RX side: + On RX side, evaluated by MAC HW. This is the only way for + MAC RX to know that this was an HE_SIG_A_SU received in + 'extended' format + + When set, the 11ax frame is of the extended range format + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + TX side: + Set to 0 + + RX side: + Field only contains valid info when dot11ax_su_extended + is set. + + On RX side, evaluated by MAC HW. This is the only way for + MAC RX to know what the number of based RUs was in this + extended range reception. It is used by the MAC to determine + the RU size for the response... + + + + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 + + +/* Description RX_NDP + + TX side: + Set to 0 + + RX side:Valid on RX side only, and looked at by MAC HW + + When set, PHY has received (expected) NDP frame + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // PHYRX_HE_SIG_A_SU diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_b1_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..3a705e8abfbbfc82876f4a3de504814d15c554f1 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_b1_mu.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HE_SIG_B1_MU_H_ +#define _PHYRX_HE_SIG_B1_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1 + + +struct phyrx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PHYRX_HE_SIG_B1_MU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description RU_ALLOCATION + + RU allocation for the user(s) following this common portion + of the SIG + + For details, refer to RU_TYPE description + +*/ + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff + + +/* Description RESERVED_0 + + +*/ + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing the HE-SIG-B common info has passed, + else set to 0 + + +*/ + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // PHYRX_HE_SIG_B1_MU diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_b2_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..2a810c86184e61696fe2ec6115fbad4480800443 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_b2_mu.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HE_SIG_B2_MU_H_ +#define _PHYRX_HE_SIG_B2_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1 + + +struct phyrx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#endif +}; + + +/* Description PHYRX_HE_SIG_B2_MU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description STA_SPATIAL_CONFIG + + Number of assigned spatial streams and their corresponding + index. + Total number of spatial streams assigned for the MU-MIMO + allocation is also signaled. +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 + + +/* Description STA_MCS + + Indicates the data MCS +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + + +/* Description RESERVED_0A + + +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 + + +/* Description NSTS + + MAC RX side usage only: + Needed by RXPCU. Provided by PHY so that RXPCU does not + need to have the RU number decoding logic. + + Number of spatial streams for this user + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this HE-SIG-B user info has passed, + else set to 0 + + +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description USER_ORDER + + RX side: Set to 0 + TX side: Ordering index of the User field + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + + +/* Description CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channel this User field + can go to + Bit 0: content channel 0 + Bit 1: content channel 1 + The other bits are unused, but could repeat the above pattern + for compatibility with 'EHT_SIG_USR_MU_MIMO_INFO.' + +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + + + +#endif // PHYRX_HE_SIG_B2_MU diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_b2_ofdma.h new file mode 100644 index 0000000000000000000000000000000000000000..df143557572a5f723bac6b497af3b774e3c247a1 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_he_sig_b2_ofdma.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ +#define _PHYRX_HE_SIG_B2_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1 + + +struct phyrx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#endif +}; + + +/* Description PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description NSTS + + MAC RX side usage only: + + Number of spatial streams for this user + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 + + +/* Description STA_MCS + + Indicates the data MCS +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + + +/* Description STA_DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + + +/* Description RESERVED_0 + + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this HE-SIG-B user info has passed, + else set to 0 + + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description USER_ORDER + + RX side: Set to 0 + TX side: Ordering index of the User field + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + + +/* Description CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channel this User field + can go to + Bit 0: content channel 0 + Bit 1: content channel 1 + The other bits are unused, but could repeat the above pattern + for compatibility with 'EHT_SIG_USR_OFDMA_INFO.' + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + + + +#endif // PHYRX_HE_SIG_B2_OFDMA diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_ht_sig.h new file mode 100644 index 0000000000000000000000000000000000000000..85c280dbf0c394d2e52bd15267f2eaab3167878f --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_ht_sig.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HT_SIG_H_ +#define _PHYRX_HT_SIG_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 + +#define NUM_OF_QWORDS_PHYRX_HT_SIG 1 + + +struct phyrx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info phyrx_ht_sig_info_details; +#else + struct ht_sig_info phyrx_ht_sig_info_details; +#endif +}; + + +/* Description PHYRX_HT_SIG_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description MCS + + Modulation Coding Scheme: + 0-7 are used for single stream + 8-15 are used for 2 streams + 16-23 are used for 3 streams + 24-31 are used for 4 streams + 32 is used for duplicate HT20 (unsupported) + 33-76 is used for unequal modulation (unsupported) + 77-127 is reserved. + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f + + +/* Description CBW + + Packet bandwidth: + + + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 + + +/* Description LENGTH + + This is the MPDU or A-MPDU length in octets of the PPDU + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 + + +/* Description RESERVED_0 + + This field is not part of HT-SIG + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + + +/* Description SMOOTHING + + Field indicates if smoothing is needed + E_num 0 do_smoothing Unsupported setting: indicates + smoothing is often used for beamforming + Indicates no smoothing is used + + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 + + +/* Description NOT_SOUNDING + + E_num 0 sounding Unsupported setting: indicates sounding + is used + Indicates no sounding is used + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 + + +/* Description HT_RESERVED + + Reserved: Should be set to 1 by the MAC and ignored by the + PHY + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 + + +/* Description AGGREGATION + + Indicates MPDU format + Indicates A-MPDU format + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 + + +/* Description STBC + + Indicates no STBC + Indicates 1 stream STBC + E_num 2 2_str_stbc Indicates 2 stream STBC (Unsupported) + + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 + + +/* Description FEC_CODING + + Indicates BCC coding + Indicates LDPC coding + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 + + +/* Description SHORT_GI + + Indicates normal guard interval + + Indicates short guard interval + + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 + + +/* Description NUM_EXT_SP_STR + + Number of extension spatial streams: (Used for TxBF) + No extension spatial streams + E_num 1 1_ext_sp_str Not supported: 1 extension spatial + streams + E_num 2 2_ext_sp_str Not supported: 2 extension spatial + streams + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 + + +/* Description CRC + + The CRC protects the HT-SIG (HT-SIG[0][23:0] and HT-SIG[1][9:0]. + The generator polynomial is G(D) = D8 + D2 + D + 1. +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + + +/* Description SIGNAL_TAIL + + The 6 bits of tail is always set to 0 is used to flush the + BCC encoder and decoder. +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 + + +/* Description RESERVED_1 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY. +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HT-SIG CRC check + has passed, else set to 0 + + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // PHYRX_HT_SIG diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_l_sig_a.h new file mode 100644 index 0000000000000000000000000000000000000000..b7ea7551a8abe9998339b36c143c29552dc4dded --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_l_sig_a.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_L_SIG_A_H_ +#define _PHYRX_L_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2 + +#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1 + + +struct phyrx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info phyrx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct l_sig_a_info phyrx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PHYRX_L_SIG_A_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description RATE + + This format is originally defined for OFDM as a 4 bit field + but the 5th bit was added to indicate 11b formatted frames. + In the standard bit [4] is specified as reserved. For + 11b frames this L-SIG is transformed in the PHY into the + 11b preamble format. The following are the rates: + 64-QAM 2/3 (48 Mbps) + 16-QAM 1/2 (24 Mbps) + QPSK 1/2 (12 Mbps) + BPSK 1/2 (6 Mbps) + 64-QAM 3/4 (54 Mbps) + 16-QAM 3/4 (36 Mbps) + QPSK 1/2 (18 Mbps) + BPSK 3/4 (9 Mbps) + +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f + + +/* Description LSIG_RESERVED + + Reserved: Should be set to 0 by the MAC and ignored by the + PHY + +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 + + +/* Description LENGTH + + The length indicates the number of octets in this MPDU. + Note that when using mixed mode .11n preamble or .11ac/.11ax/.11ba/.11be + this length provides the spoofed length for the PPDU. + This length provides part of the information (viz. PPDU + duration) to derive the actually PSDU length. For legacy + OFDM and 11B frames the maximum length is 4095. + +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 + + +/* Description PARITY + + 11a/n/ac TX: This field provides even parity over the first + 18 bits of the signal field which means that the sum of + 1s in the signal field will always be even on transmission. + The value of the field is computed by the MAC. + 11a/n/ac RX: this field contains the received parity field + from the L-SIG symbol for the current packet. + +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 + + +/* Description TAIL + + The 6 bits of tail is always set to 0 is used to flush the + BCC encoder and decoder. +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 + + +/* Description PKT_TYPE + + Only used on the RX side. + Note: This is not really part of L-SIG + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + + +/* Description CAPTURED_IMPLICIT_SOUNDING + + Only used on the RX side. + Note: This is not really part of L-SIG + + This indicates that the PHY has captured implicit sounding. + +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 + + +/* Description RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the L-SIG integrity + check has passed, else set to 0 + + +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32 +#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63 +#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // PHYRX_L_SIG_A diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_l_sig_b.h new file mode 100644 index 0000000000000000000000000000000000000000..88e64eeb5b46c1f8a506cc4e8d8dba0eb78f551d --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_l_sig_b.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_L_SIG_B_H_ +#define _PHYRX_L_SIG_B_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2 + +#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1 + + +struct phyrx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info phyrx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct l_sig_b_info phyrx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PHYRX_L_SIG_B_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description RATE + + DSSS 1 Mbps long + DSSS 2 Mbps long + CCK 5.5 Mbps long + CCK 11 Mbps long + DSSS 2 Mbps short + CCK 5.5 Mbps short + CCK 11 Mbps short + +*/ + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f + + +/* Description LENGTH + + The length indicates the number of octets in this MPDU. + +*/ + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 + + +/* Description RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the .11b PHY header + CRC check has passed, else set to 0 + + +*/ + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32 +#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63 +#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // PHYRX_L_SIG_B diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_location.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_location.h new file mode 100644 index 0000000000000000000000000000000000000000..39b43e05ac6e26d1d8db635971557c9a6b3f533a --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_location.h @@ -0,0 +1,911 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_LOCATION_H_ +#define _PHYRX_LOCATION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_location_info.h" +#define NUM_OF_DWORDS_PHYRX_LOCATION 28 + +#define NUM_OF_QWORDS_PHYRX_LOCATION 14 + + +struct phyrx_location { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_location_info rx_location_info_details; +#else + struct rx_location_info rx_location_info_details; +#endif +}; + + +/* Description RX_LOCATION_INFO_DETAILS + + Overview of location related info +*/ + + +/* Description RX_LOCATION_INFO_VALID + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001 + + +/* Description RTT_HW_IFFT_MODE + + Indicator showing if HW IFFT mode or SW IFFT mode + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002 + + +/* Description RTT_11AZ_MODE + + Indicator showing RTT5/.11mc or .11az mode for debug + + legacy RTT5/.11mc mode + .11az ISTA location info. sent + on Rx path after receiving R2I LMR + + .11az RSTA location info. sent + on Tx path after transmitting R2I LMR + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_LSB 2 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MSB 3 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MASK 0x000000000000000c + + +/* Description RESERVED_0 + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0 + + +/* Description RTT_NUM_FAC + + Number of valid first arrival correction (FAC) values (in + fields rtt_fac_0 - rtt_fac_31) + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00 + + +/* Description RTT_RX_CHAIN_MASK + + Rx chain mask, each bit is a Rx chain + 0: the Rx chain is not used + 1: the Rx chain is used + + Up to 4 Rx chains are supported. + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000 + + +/* Description RTT_NUM_STREAMS + + Number of streams used + + Up to 8 streams are supported. + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000 + + +/* Description RTT_FIRST_SELECTED_CHAIN + + For legacy RTT5/.11mc mode, this field shows the first selected + Rx chain that is used for FAC calculations, when forced + by a virtual register. + + + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000 + + +/* Description RTT_SECOND_SELECTED_CHAIN + + For legacy RTT5/.11mc mode, this field shows the second + selected Rx chain that is used for FAC calculations, when + forced by a virtual register. + + + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000 + + +/* Description RTT_CFR_STATUS + + Status of channel frequency response dump + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000 + + +/* Description RTT_CIR_STATUS + + Status of channel impulse response dump + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000 + + +/* Description RTT_CHE_BUFFER_POINTER_LOW32 + + The low 32 bits of the 40 bits pointer pointed to the external + RTT channel information buffer + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff + + +/* Description RTT_CHE_BUFFER_POINTER_HIGH8 + + The high 8 bits of the 40 bits pointer pointed to the external + RTT channel information buffer + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000 + + +/* Description RESERVED_3 + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000 + + +/* Description RTT_PKT_BW_VHT + + Indicate the bandwidth of (V)HT/HE-LTF + + + + + + Only valid for CFR, FAC + calculations are not PoR for 240 MHz. + Only valid for CFR, FAC + calculations are not PoR for 320 MHz. + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000 + + +/* Description RTT_PKT_BW_LEG + + Indicate the bandwidth of L-LTF + + + + + + Only valid for CFR, FAC + calculations are not PoR for 240 MHz. + Only valid for CFR, FAC + calculations are not PoR for 320 MHz. + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000 + + +/* Description RTT_MCS_RATE + + Bits 0~4 indicate MCS rate, if Legacy, + 0: 48 Mbps, + 1: 24 Mbps, + 2: 12 Mbps, + 3: 6 Mbps, + 4: 54 Mbps, + 5: 36 Mbps, + 6: 18 Mbps, + 7: 9 Mbps, + 8-15: reserved + + if HT, 0-7: MCS0-MCS7, 8-15: reserved, + if VHT, 0-9: MCS0-MCS9, 10-15: reserved, + if HE or EHT, 0-11: MCS0-MCS11, 12-13: 4096QAM, 14-15: reserved + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000 + + +/* Description RTT_CFO_MEASUREMENT + + CFO measurement. Needed for passive locationing + + 14 bits, signed 1.13. 13 bits fraction to provide a resolution + of 153 Hz + + In units of cycles/800 ns + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff + + +/* Description RTT_PREAMBLE_TYPE + + Indicate preamble type + + + + + + + + + + + + + + + + + + + + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000 + + +/* Description RTT_GI_TYPE + + Indicate GI (guard interval) type + + HE related GI. Can also be + used for HE + HE related GI. Can also be + used for HE + HE related GI + HE related GI + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000 + + +/* Description RX_START_TS + + RX packet start timestamp lower 32 bits + + It reports the time the first L-STF ADC sample arrived at + RX antenna. + + The clock unit is 960MHz. + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000 + + +/* Description RX_START_TS_UPPER + + RX packet start timestamp upper 32 bits + + It reports the time the first L-STF ADC sample arrived at + RX antenna. + + The clock unit is 960MHz. + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff + + +/* Description RX_END_TS + + RX packet end timestamp lower 32 bits + + It reports the time the last symbol's last ADC sample arrived + at RX antenna. + + The clock unit is 960MHz. Only 32 bits are reported. + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000 + + +/* Description GAIN_CHAIN0 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain0 +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff + + +/* Description GAIN_CHAIN1 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain1 +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000 + + +/* Description GAIN_CHAIN2 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain2 +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000 + + +/* Description GAIN_CHAIN3 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain3 +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000 + + +/* Description GAIN_REPORT_STATUS + + Number of valid gain reports (in fields gain_chain0 - gain_chain_3) + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff + + +/* Description RTT_TIMING_BACKOFF_SEL + + Indicate which timing backoff value is used + + + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00 + + +/* Description RTT_FAC_COMBINED + + Final adjusted and combined first arrival correction value + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_0 + + The fields 'rtt_fac_0' - 'rtt_fac_31' show the RTT first + arrival correction (FAC) value computed from the LTFs on + the selected Rx chains. + + 16 bits, signed 11.5. 11 integer bits to cover -3.2us to + 3.2us, and 5 fraction bits to cover 160 MHz with 32x FAC + interpolation. + + The clock unit is 320MHz. + + For .11az/MIMO, the FACs will be stored in spatial stream + order with multiple chains reported together for each stream. [ss0-ch0, + ss0-ch1, ..., ss1-ch0, ss1-ch1, ...] + + For legacy RTT5/.11mc, the FACs will be stored in preamble + order with multiple chains reported together for each LTF. [legacy-ch0, + legacy-ch1, ..., (v)ht/he-ch0, (v)ht/he-ch1, ...] +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_1 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000 + + +/* Description RTT_FAC_2 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff + + +/* Description RTT_FAC_3 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_4 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_5 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000 + + +/* Description RTT_FAC_6 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff + + +/* Description RTT_FAC_7 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_8 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_9 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000 + + +/* Description RTT_FAC_10 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff + + +/* Description RTT_FAC_11 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_12 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_13 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000 + + +/* Description RTT_FAC_14 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff + + +/* Description RTT_FAC_15 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_16 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_17 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000 + + +/* Description RTT_FAC_18 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff + + +/* Description RTT_FAC_19 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_20 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_21 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000 + + +/* Description RTT_FAC_22 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff + + +/* Description RTT_FAC_23 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_24 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_25 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000 + + +/* Description RTT_FAC_26 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff + + +/* Description RTT_FAC_27 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_28 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_29 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000 + + +/* Description RTT_FAC_30 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff + + +/* Description RTT_FAC_31 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000 + + +/* Description RESERVED_27A + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000 + + + +#endif // PHYRX_LOCATION diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_other_receive_info_ru_details.h new file mode 100644 index 0000000000000000000000000000000000000000..fd075e007260f098c343ae008743129c2e4607be --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_other_receive_info_ru_details.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4 + +#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2 + + +struct phyrx_other_receive_info_ru_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_details_channel_0 : 32; // [31:0] + uint32_t ru_details_channel_1 : 32; // [31:0] + uint32_t spare : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t ru_details_channel_0 : 32; // [31:0] + uint32_t ru_details_channel_1 : 32; // [31:0] + uint32_t spare : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description RU_DETAILS_CHANNEL_0 + + Ru_allocation from content channel 0 + [7:0] for 20/40 MHz + [15:0] for 80 MHz + [31:0] for 160 MHz + +*/ + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff + + +/* Description RU_DETAILS_CHANNEL_1 + + Ru_allocation from content channel 1 + [7:0] for 40 MHz + [15:0] for 80 MHz + [31:0] for 160 MHz + +*/ + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000 + + +/* Description SPARE + + Extra spare bits added to convey additional information + +*/ + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_pkt_end.h new file mode 100644 index 0000000000000000000000000000000000000000..624e32d2cc24f06ed0cd2e32532b67501ceb0ab6 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_pkt_end.h @@ -0,0 +1,1135 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_PKT_END_H_ +#define _PHYRX_PKT_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_pkt_end_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END 24 + +#define NUM_OF_QWORDS_PHYRX_PKT_END 12 + + +struct phyrx_pkt_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct phyrx_pkt_end_info rx_pkt_end_details; +#else + struct phyrx_pkt_end_info rx_pkt_end_details; +#endif +}; + + +/* Description RX_PKT_END_DETAILS + + Overview of the final receive related parameters from the + PHY RX +*/ + + +/* Description PHY_INTERNAL_NAP + + When set, PHY RX entered an internal NAP state, as PHY determined + that this reception was not destined to this device +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MASK 0x0000000000000001 + + +/* Description LOCATION_INFO_VALID + + Indicates that the RX_LOCATION_INFO structure later on in + the TLV contains valid info +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002 + + +/* Description TIMING_INFO_VALID + + Indicates that the RX_TIMING_OFFSET_INFO structure later + on in the TLV contains valid info +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004 + + +/* Description RSSI_INFO_VALID + + Indicates that the RECEIVE_RSSI_INFO structure later on + in the TLV contains valid info +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008 + + +/* Description RESERVED_0A + + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010 + + +/* Description FRAMELESS_FRAME_RECEIVED + + When set, PHY has received the 'frameless frame' . Can be + used in the 'MU-RTS -CTS exchange where CTS reception can + be problematic. + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020 + + +/* Description RESERVED_0B + + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0 + + +/* Description RSSI_COMB + + Combined rssi of all chains. Based on primary channel RSSI. + + + This can be used by SW for cases, e.g. Ack/BlockAck responses, + where 'PHYRX_RSSI_LEGACY' is not available to SW. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00 + + +/* Description RESERVED_0C + + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000 + + +/* Description PHY_TIMESTAMP_1_LOWER_32 + + TODO PHY: cleanup descriptionThe PHY timestamp in the AMPI + of the first rising edge of rx_clear_pri after TX_PHY_DESC. . + This field should set to 0 by the PHY and should be updated + by the AMPI before being forwarded to the rest of the MAC. + This field indicates the lower 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000 + + +/* Description PHY_TIMESTAMP_1_UPPER_32 + + TODO PHY: cleanup description + The PHY timestamp in the AMPI of the first rising edge of + rx_clear_pri after TX_PHY_DESC. This field should set + to 0 by the PHY and should be updated by the AMPI before + being forwarded to the rest of the MAC. This field indicates + the upper 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff + + +/* Description PHY_TIMESTAMP_2_LOWER_32 + + TODO PHY: cleanup description + The PHY timestamp in the AMPI of the rising edge of rx_clear_pri + after RX_RSSI_LEGACY. This field should set to 0 by the + PHY and should be updated by the AMPI before being forwarded + to the rest of the MAC. This field indicates the lower + 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000 + + +/* Description PHY_TIMESTAMP_2_UPPER_32 + + TODO PHY: cleanup description + The PHY timestamp in the AMPI of the rising edge of rx_clear_pri + after RX_RSSI_LEGACY. This field should set to 0 by the + PHY and should be updated by the AMPI before being forwarded + to the rest of the MAC. This field indicates the upper + 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff + + +/* Description RX_TIMING_OFFSET_INFO_DETAILS + + Overview of timing offset related info +*/ + + +/* Description RESIDUAL_PHASE_OFFSET + + Cumulative reference frequency error at end of RX packet, + expressed as the phase offset measured over 0.8us. + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000 + + +/* Description RESERVED + + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 44 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff00000000000 + + +/* Description POST_RSSI_INFO_DETAILS + + Overview of the post-RSSI values. +*/ + + +/* Description RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 + + +/* Description PHY_SW_STATUS_31_0 + + Some PHY micro code status that can be put in here. Details + of definition within SW specification + This field can be used for debugging, FW - SW message exchange, + etc. + It could for example be a pointer to a DDR memory location + where PHY FW put some debug info. + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff + + +/* Description PHY_SW_STATUS_63_32 + + Some PHY micro code status that can be put in here. Details + of definition within SW specification + This field can be used for debugging, FW - SW message exchange, + etc. + It could for example be a pointer to a DDR memory location + where PHY FW put some debug info. + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000 + + + +#endif // PHYRX_PKT_END diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_pkt_end_info.h new file mode 100644 index 0000000000000000000000000000000000000000..e2793699d057b10c91f1204c5ebfcb1b27e2f14f --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_pkt_end_info.h @@ -0,0 +1,1159 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_PKT_END_INFO_H_ +#define _PHYRX_PKT_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_rssi_info.h" +#include "rx_timing_offset_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 + + +struct phyrx_pkt_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_internal_nap : 1, // [0:0] + location_info_valid : 1, // [1:1] + timing_info_valid : 1, // [2:2] + rssi_info_valid : 1, // [3:3] + reserved_0a : 1, // [4:4] + frameless_frame_received : 1, // [5:5] + reserved_0b : 2, // [7:6] + rssi_comb : 8, // [15:8] + reserved_0c : 16; // [31:16] + uint32_t phy_timestamp_1_lower_32 : 32; // [31:0] + uint32_t phy_timestamp_1_upper_32 : 32; // [31:0] + uint32_t phy_timestamp_2_lower_32 : 32; // [31:0] + uint32_t phy_timestamp_2_upper_32 : 32; // [31:0] + struct rx_timing_offset_info rx_timing_offset_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; // [31:0] + uint32_t phy_sw_status_63_32 : 32; // [31:0] +#else + uint32_t reserved_0c : 16, // [31:16] + rssi_comb : 8, // [15:8] + reserved_0b : 2, // [7:6] + frameless_frame_received : 1, // [5:5] + reserved_0a : 1, // [4:4] + rssi_info_valid : 1, // [3:3] + timing_info_valid : 1, // [2:2] + location_info_valid : 1, // [1:1] + phy_internal_nap : 1; // [0:0] + uint32_t phy_timestamp_1_lower_32 : 32; // [31:0] + uint32_t phy_timestamp_1_upper_32 : 32; // [31:0] + uint32_t phy_timestamp_2_lower_32 : 32; // [31:0] + uint32_t phy_timestamp_2_upper_32 : 32; // [31:0] + struct rx_timing_offset_info rx_timing_offset_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; // [31:0] + uint32_t phy_sw_status_63_32 : 32; // [31:0] +#endif +}; + + +/* Description PHY_INTERNAL_NAP + + When set, PHY RX entered an internal NAP state, as PHY determined + that this reception was not destined to this device +*/ + +#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MSB 0 +#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MASK 0x00000001 + + +/* Description LOCATION_INFO_VALID + + Indicates that the RX_LOCATION_INFO structure later on in + the TLV contains valid info +*/ + +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 + + +/* Description TIMING_INFO_VALID + + Indicates that the RX_TIMING_OFFSET_INFO structure later + on in the TLV contains valid info +*/ + +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 + + +/* Description RSSI_INFO_VALID + + Indicates that the RECEIVE_RSSI_INFO structure later on + in the TLV contains valid info +*/ + +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 + + +/* Description RESERVED_0A + + +*/ + +#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 + + +/* Description FRAMELESS_FRAME_RECEIVED + + When set, PHY has received the 'frameless frame' . Can be + used in the 'MU-RTS -CTS exchange where CTS reception can + be problematic. + +*/ + +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + + +/* Description RESERVED_0B + + +*/ + +#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 + + +/* Description RSSI_COMB + + Combined rssi of all chains. Based on primary channel RSSI. + + + This can be used by SW for cases, e.g. Ack/BlockAck responses, + where 'PHYRX_RSSI_LEGACY' is not available to SW. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 + + +/* Description RESERVED_0C + + +*/ + +#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 + + +/* Description PHY_TIMESTAMP_1_LOWER_32 + + TODO PHY: cleanup descriptionThe PHY timestamp in the AMPI + of the first rising edge of rx_clear_pri after TX_PHY_DESC. . + This field should set to 0 by the PHY and should be updated + by the AMPI before being forwarded to the rest of the MAC. + This field indicates the lower 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + + +/* Description PHY_TIMESTAMP_1_UPPER_32 + + TODO PHY: cleanup description + The PHY timestamp in the AMPI of the first rising edge of + rx_clear_pri after TX_PHY_DESC. This field should set + to 0 by the PHY and should be updated by the AMPI before + being forwarded to the rest of the MAC. This field indicates + the upper 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + + +/* Description PHY_TIMESTAMP_2_LOWER_32 + + TODO PHY: cleanup description + The PHY timestamp in the AMPI of the rising edge of rx_clear_pri + after RX_RSSI_LEGACY. This field should set to 0 by the + PHY and should be updated by the AMPI before being forwarded + to the rest of the MAC. This field indicates the lower + 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + + +/* Description PHY_TIMESTAMP_2_UPPER_32 + + TODO PHY: cleanup description + The PHY timestamp in the AMPI of the rising edge of rx_clear_pri + after RX_RSSI_LEGACY. This field should set to 0 by the + PHY and should be updated by the AMPI before being forwarded + to the rest of the MAC. This field indicates the upper + 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + + +/* Description RX_TIMING_OFFSET_INFO_DETAILS + + Overview of timing offset related info +*/ + + +/* Description RESIDUAL_PHASE_OFFSET + + Cumulative reference frequency error at end of RX packet, + expressed as the phase offset measured over 0.8us. + +*/ + +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + + +/* Description RESERVED + + +*/ + +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 + + +/* Description POST_RSSI_INFO_DETAILS + + Overview of the post-RSSI values. +*/ + + +/* Description RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + + +/* Description PHY_SW_STATUS_31_0 + + Some PHY micro code status that can be put in here. Details + of definition within SW specification + This field can be used for debugging, FW - SW message exchange, + etc. + It could for example be a pointer to a DDR memory location + where PHY FW put some debug info. + +*/ + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff + + +/* Description PHY_SW_STATUS_63_32 + + Some PHY micro code status that can be put in here. Details + of definition within SW specification + This field can be used for debugging, FW - SW message exchange, + etc. + It could for example be a pointer to a DDR memory location + where PHY FW put some debug info. + +*/ + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff + + + +#endif // PHYRX_PKT_END_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_rssi_legacy.h new file mode 100644 index 0000000000000000000000000000000000000000..5e1e2282d6640a6904e834583d2b6247c65c48d7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_rssi_legacy.h @@ -0,0 +1,2243 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_RSSI_LEGACY_H_ +#define _PHYRX_RSSI_LEGACY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_rssi_info.h" +#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 + +#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21 + + +struct phyrx_rssi_legacy { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reception_type : 4, // [3:0] + rx_chain_mask_type : 1, // [4:4] + receive_bandwidth : 3, // [7:5] + rx_chain_mask : 8, // [15:8] + phy_ppdu_id : 16; // [31:16] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t preamble_time_to_rxframe : 8, // [7:0] + standalone_snifer_mode : 1, // [8:8] + reserved_5a : 23; // [31:9] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t pre_rssi_comb : 8, // [7:0] + rssi_comb : 8, // [15:8] + normalized_pre_rssi_comb : 8, // [23:16] + normalized_rssi_comb : 8; // [31:24] + uint32_t rssi_comb_ppdu : 8, // [7:0] + rssi_db_to_dbm_offset : 8, // [15:8] + rssi_for_spatial_reuse : 8, // [23:16] + rssi_for_trigger_resp : 8; // [31:24] +#else + uint32_t phy_ppdu_id : 16, // [31:16] + rx_chain_mask : 8, // [15:8] + receive_bandwidth : 3, // [7:5] + rx_chain_mask_type : 1, // [4:4] + reception_type : 4; // [3:0] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 23, // [31:9] + standalone_snifer_mode : 1, // [8:8] + preamble_time_to_rxframe : 8; // [7:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t normalized_rssi_comb : 8, // [31:24] + normalized_pre_rssi_comb : 8, // [23:16] + rssi_comb : 8, // [15:8] + pre_rssi_comb : 8; // [7:0] + uint32_t rssi_for_trigger_resp : 8, // [31:24] + rssi_for_spatial_reuse : 8, // [23:16] + rssi_db_to_dbm_offset : 8, // [15:8] + rssi_comb_ppdu : 8; // [7:0] +#endif +}; + + +/* Description RECEPTION_TYPE + + This field helps MAC SW determine which field in this (and + following TLVs) will contain valid information. For example + some RSSI info not valid in case of uplink_ofdma.. + + In case of UL MU OFDMA or UL MU-MIMO reception pre-announced + by MAC during trigger Tx, e-nums 0 or 1 should be used. + + + In case of UL MU OFDMA+MIMO reception, or in case of UL + MU reception when PHY has not been pre-informed, e-num 2 + should be used. + If this happens, the UL MU frame in the medium is by definition + not for this device. + + + + + PHY RX has been instructed + in advance that the upcoming reception is frameless. This + implieas that in advance it is known that all frames will + collide in the medium, and nothing can be properly decoded... + This can happen during the CTS reception in response to + the triggered MU-RTS transmission. + MAC takes no action when seeing this e_num. For the frameless + reception the indication in pkt_end is the final one evaluated + by the MAC + + For the relationship between pkt_type and this field, see + the table at the end of this TLV description. + +*/ + +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_LSB 0 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MSB 3 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MASK 0x000000000000000f + + +/* Description RX_CHAIN_MASK_TYPE + + Indicates if the field rx_chain_mask represents the mask + at start of reception (on which the Rssi_comb value is + based), or the setting used during the remainder of the + reception + + 1'b0: rxtd.listen_pri80_mask + 1'b1: Final receive mask + + +*/ + +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_LSB 4 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MSB 4 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MASK 0x0000000000000010 + + +/* Description RECEIVE_BANDWIDTH + + Full receive Bandwidth + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB 5 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB 7 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK 0x00000000000000e0 + + +/* Description RX_CHAIN_MASK + + The chain mask at the start of the reception of this frame. + + + each bit is one antenna + 0: the chain is NOT used + 1: the chain is used + + Supports up to 8 chains + + Used in 11ax TPC calculations for UL OFDMA/MIMO and has + to be in sync with the rssi_comb value as this is also used + by the MAC for the TPC calculations. + +*/ + +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_LSB 8 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MSB 15 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MASK 0x000000000000ff00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_LSB 16 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MSB 31 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description SW_PHY_META_DATA + + 32 bit Meta data that SW can program in a 32 bit PHY register + and PHY will insert the value in every RX_RSSI_LEGACY TLV + that it generates. + SW uses this field to embed among other things some SW channel + info. +*/ + +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 32 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 63 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0xffffffff00000000 + + +/* Description PPDU_START_TIMESTAMP_31_0 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, lower 32 bits + + Note that PHY will detect the start later, and will have + to derive out of the preamble info when the frame actually + appeared on the medium. +*/ + +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + + +/* Description PPDU_START_TIMESTAMP_63_32 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, upper 32 bits + + Note that PHY will detect the start later, and will have + to derive out of the preamble info when the frame actually + appeared on the medium. +*/ + +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_LSB 32 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MSB 63 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + NOTE: DO not assign a field... Internally used in RXPCU + to store 'RX_PPDU_START::Rxframe_assert_timestamp.' + +*/ + +#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description PREAMBLE_TIME_TO_RXFRAME + + The time taken (in us) from the frame starting on the medium + and PHY raising 'rx_frame' + +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff00000000 + + +/* Description STANDALONE_SNIFER_MODE + + When set to 1, PHY has been configured to operate in the + stand alone sniffer mode. + When 0, PHY is operating in the "normal" mission mode. + +*/ + +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_LSB 40 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_MSB 40 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_MASK 0x0000010000000000 + + +/* Description RESERVED_5A + + +*/ + +#define PHYRX_RSSI_LEGACY_RESERVED_5A_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_RESERVED_5A_LSB 41 +#define PHYRX_RSSI_LEGACY_RESERVED_5A_MSB 63 +#define PHYRX_RSSI_LEGACY_RESERVED_5A_MASK 0xfffffe0000000000 + + +/* Description RESERVED_6A + + NOTE: DO not assign a field... Internally used in RXPCU + to construct 'RX_PPDU_START.' + +*/ + +#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x0000000000000018 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + NOTE: DO not assign a field... Internally used in RXPCU + to construct 'RX_PPDU_START.' + +*/ + +#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000000000000018 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 32 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 63 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description PRE_RSSI_INFO_DETAILS + + This field is not valid when reception_is_uplink_ofdma + + Overview of the pre-RSSI values. That is RSSI values measured + on the medium before this reception started. +*/ + + +/* Description RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 + + +/* Description PREAMBLE_RSSI_INFO_DETAILS + + This field is not valid when reception_is_uplink_ofdma + + Overview of the RSSI values measured during the pre-amble + phase of this reception +*/ + + +/* Description RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 + + +/* Description PRE_RSSI_COMB + + Combined pre_rssi of all chains. Based on primary channel + RSSI. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x00000000000000ff + + +/* Description RSSI_COMB + + Combined rssi of all chains. Based on primary channel RSSI. + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x000000000000ff00 + + +/* Description NORMALIZED_PRE_RSSI_COMB + + Combined pre_rssi of all chains, but "normalized" back to + a single chain. This avoids PDG from having to evaluate + this in combination with receive chain mask and perform + all kinds of pre-processing algorithms. + + Based on primary channel RSSI. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 + + +/* Description NORMALIZED_RSSI_COMB + + Combined rssi of all chains, but "normalized" back to a + single chain. This avoids PDG from having to evaluate this + in combination with receive chain mask and perform all + kinds of pre-processing algorithms. + + Based on primary channel RSSI. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 + + +/* Description RSSI_COMB_PPDU + + Combined rssi of all chains, based on active RUs/subchannels, + a.k.a. rssi_pkt_bw_mac + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + When packet BW is 20 MHz, + rssi_comb_ppdu = rssi_comb. + + When packet BW > 20 MHz, + rssi_comb < rssi_comb_ppdu because rssi_comb only includes + power of primary 20 MHz while rssi_comb_ppdu includes power + of active RUs/subchannels. + + +*/ + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 32 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 39 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff00000000 + + +/* Description RSSI_DB_TO_DBM_OFFSET + + Offset between 'dB' and 'dBm' values. SW can use this value + to convert RSSI 'dBm' values back to 'dB,' and report both + the values. + + When rssi_db_to_dbm_offset = 0, + all rssi_xxx fields are defined in dB. + + When rssi_db_to_dbm_offset is a large negative value, all + rssi_xxx fields are defined in dBm. + + +*/ + +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 40 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 47 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff0000000000 + + +/* Description RSSI_FOR_SPATIAL_REUSE + + RSSI to be used by HWSCH for transmit (power) selection + during an SR opportunity, reported as an 8-bit signed value + + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + As per 802.11ax draft 3.3 subsubclauses 27.10.2.2/3, for + OBSS PD spatial reuse, the received signal strength level + should be measured from the L-STF or L-LTF (but not L-SIG), + just as measured to indicate CCA. + + Also, as per 802.11ax draft 3.3, for OBSS PD spatial reuse, + MAC should compare this value with its programmed OBSS_PDlevel + scaled from 20 MHz to the Rx PPDU bandwidth. Since MAC + does not do this scaling, PHY is instead expected to normalize + the reported RSSI to 20 MHz. + + Also as per 802.11ax draft 3.3 subsubclause 27.10.3.2, for + SRP spatial reuse, the received power level should be measured + from the L-STF or L-LTF (but not L-SIG) and normalized + to 20 MHz. + +*/ + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 48 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 55 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff000000000000 + + +/* Description RSSI_FOR_TRIGGER_RESP + + RSSI to be used by PDG for transmit (power) selection during + trigger response, reported as an 8-bit signed value + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + As per 802.11ax draft 3.3 subsubclauses 28.3.14.2, for trigger + response, the received power should be measured from the + non-HE portion of the preamble of the PPDU containing the + trigger, normalized to 20 MHz, averaged over the antennas + over which the average pathloss is being computed. + +*/ + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 56 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 63 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff00000000000000 + + + +#endif // PHYRX_RSSI_LEGACY diff --git a/drivers/staging/fw-api/hw/qcn6432/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/qcn6432/phyrx_vht_sig_a.h new file mode 100644 index 0000000000000000000000000000000000000000..2f252d311a11d1f74855e28ebd84ff0a0ff4b8d4 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phyrx_vht_sig_a.h @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_VHT_SIG_A_H_ +#define _PHYRX_VHT_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 + +#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1 + + +struct phyrx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#else + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#endif +}; + + +/* Description PHYRX_VHT_SIG_A_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description BANDWIDTH + + Packet bandwidth + + + + + + + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 + + +/* Description VHTA_RESERVED_0 + + Reserved. Set to 1 by MAC, PHY should ignore + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 + + +/* Description STBC + + Space time block coding: + Indicates STBC is disabled + Indicates STBC is enabled on + all streams + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 + + +/* Description GROUP_ID + + In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed + to an AP or to a mesh STA, the Group ID field is set to + 0, otherwise it is set to 63. In an NDP PPDU the Group + ID is set according to IEEE 802.11ac_D1.0 Section 9.30.6 + (Transmission of a VHT NDP). For a MU-MIMO PPDU the Group + ID is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group + ID). +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 + + +/* Description N_STS + + For MU: + 3 bits/user with maximum of 4 users (user u uses + vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2, + 3) + Set to 0 for 0 space time streams + Set to 1 for 1 space time stream + Set to 2 for 2 space time streams + Set to 3 for 3 space time streams + Set to 4 for 4 space time streams (not supported in Wifi + 3.0) + Values 5-7 are reserved + In this field, references to user "u" should be interpreted + as MU user "u". As described in the previous chapter in + this document (see chapter on User number), the MU user + value for a given client is defined for each MU group that + the client participates in. The MU user number is not related + to the internal user number that is used within the BFer. + + + + For SU: + vht_sig_a[0][12:10] + Set to 0 for 1 space time stream + Set to 1 for 2 space time streams + Set to 2 for 3 space time streams + Set to 3 for 4 space time streams + Set to 4 for 5 space time streams + Set to 5 for 6 space time streams + Set to 6 for 7 space time streams + Set to 7 for 8 space time streams + + vht_sig_a[0][21:13] + Partial AID: + Set to the value of the TXVECTOR parameter PARTIAL_AID. + Partial AID provides an abbreviated indication of the intended + recipient(s) of the frame (see IEEE802.11ac_D1.0 Section + 9.17a (Partial AID in VHT PPDUs)). + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 + + +/* Description TXOP_PS_NOT_ALLOWED + + E_num 0 txop_ps_allowed Not supported: If set to by + VHT AP if it allows non-AP VHT STAs in TXOP power save + mode to enter Doze state during a TXOP + Otherwise + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 + + +/* Description VHTA_RESERVED_0B + + Reserved: Should be set to 1 by the MAC and ignored by the + PHY +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 + + +/* Description RESERVED_0 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + + +/* Description GI_SETTING + + Indicates short guard interval is + not used in the data field + Indicates short guard interval is + used in the data field + Indicates short guard interval + is used in the data field and NSYM mod 10 = 9 + NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3 (TXTIME + and PSDU_LENGTH calculation). + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 + + +/* Description SU_MU_CODING + + For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For an + MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then + B2 indicates the coding used for user 0; set to 0 for BCC + and 1 for LDPC. If the MU[0] NSTS field is 0, then this + field is reserved and set to 1 +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 + + +/* Description LDPC_EXTRA_SYMBOL + + Set to 1 if the LDPC PPDU encoding process (if an SU PPDU), + or at least one LDPC user's PPDU encoding process (if an + MU PPDU), results in an extra OFDM symbol (or symbols) + as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 + (Encoding process for MU PPDUs). Set to 0 otherwise. +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 + + +/* Description MCS + + For SU: + Set to 0 for BPSK 1/2 + Set to 1 for QPSK 1/2 + Set to 2 for QPSK 3/4 + Set to 3 for 16-QAM 1/2 + Set to 4 for 16-QAM 3/4 + Set to 5 for 64-QAM 2/3 + Set to 6 for 64-QAM 3/4 + Set to 7 for 64-QAM 5/6 + Set to 8 for 256-QAM 3/4 + Set to 9 for 256-QAM 5/6 + For MU: + If NSTS for user 1 is non-zero, then vht_sig_a[1][4] indicates + coding for user 1: set to 0 for BCC, 1 for LDPC. + If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is + reserved and set to 1. + If NSTS for user 2 is non-zero, then vht_sig_a[1][5] indicates + coding for user 2: set to 0 for BCC, 1 for LDPC. + If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is + reserved and set to 1. + If NSTS for user 3 is non-zero, then vht_sig_a[1][6] indicates + coding for user 3: set to 0 for BCC, 1 for LDPC. + If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is + reserved and set to 1. + vht_sig_a[1][7] is reserved and set to 1 + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 + + +/* Description BEAMFORMED + + For SU: + Set to 1 if a Beamforming steering matrix is applied to + the waveform in an SU transmission as described in IEEE802.11ac_D1.0 + Section 19.3.11.11.2 (Spatial mapping), set to 0 otherwise. + + For MU: + Reserved and set to 1 + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 + + +/* Description VHTA_RESERVED_1 + + Reserved and set to 1. +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 + + +/* Description CRC + + CRC calculated as in IEEE802.11ac_D1.0 Section 19.3.9.4.4 + (CRC calculation for HTSIG) with C7 in vht_sig_a[1][10], + etc. +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + Set to 0. +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 + + +/* Description RESERVED_1 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the VHT-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // PHYRX_VHT_SIG_A diff --git a/drivers/staging/fw-api/hw/qcn6432/phytx_abort_request_info.h b/drivers/staging/fw-api/hw/qcn6432/phytx_abort_request_info.h new file mode 100644 index 0000000000000000000000000000000000000000..42931141f16a18810eb5fb898717215cb978a4f6 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phytx_abort_request_info.h @@ -0,0 +1,242 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ +#define _PHYTX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 + + +struct phytx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t phytx_abort_reason : 8, // [7:0] + user_number : 6, // [13:8] + reserved : 2; // [15:14] +#else + uint16_t reserved : 2, // [15:14] + user_number : 6, // [13:8] + phytx_abort_reason : 8; // [7:0] +#endif +}; + + +/* Description PHYTX_ABORT_REASON + + Reason for early termination of TX packet by the PHY + + This value is the default + value the MAC will fill in the status TLV (when not PHY + abort was received). + + Note that when PHY generates the PHYTX_ABORT_REQUEST, this + value shall never be used. + PHY ran out of transmit + data due to transmit underrun - this field is user-specific + (see user_number field) + + + + + + + + + + + + + + + + + + + + This used to be called 'error_illegal_nss.' + + + + This error indicates + that CV prefetch command indicated a CV index that is not + available. + This error indicates that + CV delete command indicated a CV index that did not contain + any valid info + Error found with the HE + transmission parameters + + + + + + + + + + + + + + + + + + + + + + All FIFO read + hang errors use this value. + All FIFO no read + errors use this value. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This is the merged Rx/Tx + CDC FIFO empty/full error code + All 'error_txtd_chn' codes + use this value as well. + This code is + used to abort the Tx when MAC Rx issues an abort request + with code 05 "macrx_abort_too_much_bad_data." + + + + + + + +*/ + +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff + + +/* Description USER_NUMBER + + For some errors, the user for which this error was detected + can be indicated in this field. + +*/ + +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 + + +/* Description RESERVED + + +*/ + +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 + + + +#endif // PHYTX_ABORT_REQUEST_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/phytx_ppdu_header_info_request.h b/drivers/staging/fw-api/hw/qcn6432/phytx_ppdu_header_info_request.h new file mode 100644 index 0000000000000000000000000000000000000000..6303d7987cb687a55349e3963ab65f142263fdbc --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/phytx_ppdu_header_info_request.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ +#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 + +#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 + + +struct phytx_ppdu_header_info_request { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t request_type : 5, // [4:0] + reserved : 11; // [15:5] + uint16_t tlv32_padding : 16; // [15:0] +#else + uint16_t reserved : 11, // [15:5] + request_type : 5; // [4:0] + uint16_t tlv32_padding : 16; // [15:0] +#endif +}; + + +/* Description REQUEST_TYPE + + Reason for the request by PHY + + + + + + + + + + + + + +*/ + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f + + +/* Description RESERVED + + +*/ + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 + + +/* Description TLV32_PADDING + + Automatic WORD padding inserted while converting TLV16 to + TLV32 for 64 bit ARCH + +*/ + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff + + + +#endif // PHYTX_PPDU_HEADER_INFO_REQUEST diff --git a/drivers/staging/fw-api/hw/qcn6432/receive_rssi_info.h b/drivers/staging/fw-api/hw/qcn6432/receive_rssi_info.h new file mode 100644 index 0000000000000000000000000000000000000000..3aa8915acd95ab74ec2ef8132e7edb89cdb5f0c3 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/receive_rssi_info.h @@ -0,0 +1,993 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVE_RSSI_INFO_H_ +#define _RECEIVE_RSSI_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 + + +struct receive_rssi_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_pri20_chain0 : 8, // [7:0] + rssi_ext20_chain0 : 8, // [15:8] + rssi_ext40_low20_chain0 : 8, // [23:16] + rssi_ext40_high20_chain0 : 8; // [31:24] + uint32_t rssi_ext80_low20_chain0 : 8, // [7:0] + rssi_ext80_low_high20_chain0 : 8, // [15:8] + rssi_ext80_high_low20_chain0 : 8, // [23:16] + rssi_ext80_high20_chain0 : 8; // [31:24] + uint32_t rssi_ext160_0_chain0 : 8, // [7:0] + rssi_ext160_1_chain0 : 8, // [15:8] + rssi_ext160_2_chain0 : 8, // [23:16] + rssi_ext160_3_chain0 : 8; // [31:24] + uint32_t rssi_ext160_4_chain0 : 8, // [7:0] + rssi_ext160_5_chain0 : 8, // [15:8] + rssi_ext160_6_chain0 : 8, // [23:16] + rssi_ext160_7_chain0 : 8; // [31:24] + uint32_t rssi_pri20_chain1 : 8, // [7:0] + rssi_ext20_chain1 : 8, // [15:8] + rssi_ext40_low20_chain1 : 8, // [23:16] + rssi_ext40_high20_chain1 : 8; // [31:24] + uint32_t rssi_ext80_low20_chain1 : 8, // [7:0] + rssi_ext80_low_high20_chain1 : 8, // [15:8] + rssi_ext80_high_low20_chain1 : 8, // [23:16] + rssi_ext80_high20_chain1 : 8; // [31:24] + uint32_t rssi_ext160_0_chain1 : 8, // [7:0] + rssi_ext160_1_chain1 : 8, // [15:8] + rssi_ext160_2_chain1 : 8, // [23:16] + rssi_ext160_3_chain1 : 8; // [31:24] + uint32_t rssi_ext160_4_chain1 : 8, // [7:0] + rssi_ext160_5_chain1 : 8, // [15:8] + rssi_ext160_6_chain1 : 8, // [23:16] + rssi_ext160_7_chain1 : 8; // [31:24] + uint32_t rssi_pri20_chain2 : 8, // [7:0] + rssi_ext20_chain2 : 8, // [15:8] + rssi_ext40_low20_chain2 : 8, // [23:16] + rssi_ext40_high20_chain2 : 8; // [31:24] + uint32_t rssi_ext80_low20_chain2 : 8, // [7:0] + rssi_ext80_low_high20_chain2 : 8, // [15:8] + rssi_ext80_high_low20_chain2 : 8, // [23:16] + rssi_ext80_high20_chain2 : 8; // [31:24] + uint32_t rssi_ext160_0_chain2 : 8, // [7:0] + rssi_ext160_1_chain2 : 8, // [15:8] + rssi_ext160_2_chain2 : 8, // [23:16] + rssi_ext160_3_chain2 : 8; // [31:24] + uint32_t rssi_ext160_4_chain2 : 8, // [7:0] + rssi_ext160_5_chain2 : 8, // [15:8] + rssi_ext160_6_chain2 : 8, // [23:16] + rssi_ext160_7_chain2 : 8; // [31:24] + uint32_t rssi_pri20_chain3 : 8, // [7:0] + rssi_ext20_chain3 : 8, // [15:8] + rssi_ext40_low20_chain3 : 8, // [23:16] + rssi_ext40_high20_chain3 : 8; // [31:24] + uint32_t rssi_ext80_low20_chain3 : 8, // [7:0] + rssi_ext80_low_high20_chain3 : 8, // [15:8] + rssi_ext80_high_low20_chain3 : 8, // [23:16] + rssi_ext80_high20_chain3 : 8; // [31:24] + uint32_t rssi_ext160_0_chain3 : 8, // [7:0] + rssi_ext160_1_chain3 : 8, // [15:8] + rssi_ext160_2_chain3 : 8, // [23:16] + rssi_ext160_3_chain3 : 8; // [31:24] + uint32_t rssi_ext160_4_chain3 : 8, // [7:0] + rssi_ext160_5_chain3 : 8, // [15:8] + rssi_ext160_6_chain3 : 8, // [23:16] + rssi_ext160_7_chain3 : 8; // [31:24] +#else + uint32_t rssi_ext40_high20_chain0 : 8, // [31:24] + rssi_ext40_low20_chain0 : 8, // [23:16] + rssi_ext20_chain0 : 8, // [15:8] + rssi_pri20_chain0 : 8; // [7:0] + uint32_t rssi_ext80_high20_chain0 : 8, // [31:24] + rssi_ext80_high_low20_chain0 : 8, // [23:16] + rssi_ext80_low_high20_chain0 : 8, // [15:8] + rssi_ext80_low20_chain0 : 8; // [7:0] + uint32_t rssi_ext160_3_chain0 : 8, // [31:24] + rssi_ext160_2_chain0 : 8, // [23:16] + rssi_ext160_1_chain0 : 8, // [15:8] + rssi_ext160_0_chain0 : 8; // [7:0] + uint32_t rssi_ext160_7_chain0 : 8, // [31:24] + rssi_ext160_6_chain0 : 8, // [23:16] + rssi_ext160_5_chain0 : 8, // [15:8] + rssi_ext160_4_chain0 : 8; // [7:0] + uint32_t rssi_ext40_high20_chain1 : 8, // [31:24] + rssi_ext40_low20_chain1 : 8, // [23:16] + rssi_ext20_chain1 : 8, // [15:8] + rssi_pri20_chain1 : 8; // [7:0] + uint32_t rssi_ext80_high20_chain1 : 8, // [31:24] + rssi_ext80_high_low20_chain1 : 8, // [23:16] + rssi_ext80_low_high20_chain1 : 8, // [15:8] + rssi_ext80_low20_chain1 : 8; // [7:0] + uint32_t rssi_ext160_3_chain1 : 8, // [31:24] + rssi_ext160_2_chain1 : 8, // [23:16] + rssi_ext160_1_chain1 : 8, // [15:8] + rssi_ext160_0_chain1 : 8; // [7:0] + uint32_t rssi_ext160_7_chain1 : 8, // [31:24] + rssi_ext160_6_chain1 : 8, // [23:16] + rssi_ext160_5_chain1 : 8, // [15:8] + rssi_ext160_4_chain1 : 8; // [7:0] + uint32_t rssi_ext40_high20_chain2 : 8, // [31:24] + rssi_ext40_low20_chain2 : 8, // [23:16] + rssi_ext20_chain2 : 8, // [15:8] + rssi_pri20_chain2 : 8; // [7:0] + uint32_t rssi_ext80_high20_chain2 : 8, // [31:24] + rssi_ext80_high_low20_chain2 : 8, // [23:16] + rssi_ext80_low_high20_chain2 : 8, // [15:8] + rssi_ext80_low20_chain2 : 8; // [7:0] + uint32_t rssi_ext160_3_chain2 : 8, // [31:24] + rssi_ext160_2_chain2 : 8, // [23:16] + rssi_ext160_1_chain2 : 8, // [15:8] + rssi_ext160_0_chain2 : 8; // [7:0] + uint32_t rssi_ext160_7_chain2 : 8, // [31:24] + rssi_ext160_6_chain2 : 8, // [23:16] + rssi_ext160_5_chain2 : 8, // [15:8] + rssi_ext160_4_chain2 : 8; // [7:0] + uint32_t rssi_ext40_high20_chain3 : 8, // [31:24] + rssi_ext40_low20_chain3 : 8, // [23:16] + rssi_ext20_chain3 : 8, // [15:8] + rssi_pri20_chain3 : 8; // [7:0] + uint32_t rssi_ext80_high20_chain3 : 8, // [31:24] + rssi_ext80_high_low20_chain3 : 8, // [23:16] + rssi_ext80_low_high20_chain3 : 8, // [15:8] + rssi_ext80_low20_chain3 : 8; // [7:0] + uint32_t rssi_ext160_3_chain3 : 8, // [31:24] + rssi_ext160_2_chain3 : 8, // [23:16] + rssi_ext160_1_chain3 : 8, // [15:8] + rssi_ext160_0_chain3 : 8; // [7:0] + uint32_t rssi_ext160_7_chain3 : 8, // [31:24] + rssi_ext160_6_chain3 : 8, // [23:16] + rssi_ext160_5_chain3 : 8, // [15:8] + rssi_ext160_4_chain3 : 8; // [7:0] +#endif +}; + + +/* Description RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + + + +#endif // RECEIVE_RSSI_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/receive_user_info.h b/drivers/staging/fw-api/hw/qcn6432/receive_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..f393d6a77314387d23c83472d1f040118fd4618a --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/receive_user_info.h @@ -0,0 +1,704 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVE_USER_INFO_H_ +#define _RECEIVE_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8 + + +struct receive_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, // [15:0] + user_rssi : 8, // [23:16] + pkt_type : 4, // [27:24] + stbc : 1, // [28:28] + reception_type : 3; // [31:29] + uint32_t rate_mcs : 4, // [3:0] + sgi : 2, // [5:4] + he_ranging_ndp : 1, // [6:6] + reserved_1a : 1, // [7:7] + mimo_ss_bitmap : 8, // [15:8] + receive_bandwidth : 3, // [18:16] + reserved_1b : 5, // [23:19] + dl_ofdma_user_index : 8; // [31:24] + uint32_t dl_ofdma_content_channel : 1, // [0:0] + reserved_2a : 7, // [7:1] + nss : 3, // [10:8] + stream_offset : 3, // [13:11] + sta_dcm : 1, // [14:14] + ldpc : 1, // [15:15] + ru_type_80_0 : 4, // [19:16] + ru_type_80_1 : 4, // [23:20] + ru_type_80_2 : 4, // [27:24] + ru_type_80_3 : 4; // [31:28] + uint32_t ru_start_index_80_0 : 6, // [5:0] + reserved_3a : 2, // [7:6] + ru_start_index_80_1 : 6, // [13:8] + reserved_3b : 2, // [15:14] + ru_start_index_80_2 : 6, // [21:16] + reserved_3c : 2, // [23:22] + ru_start_index_80_3 : 6, // [29:24] + reserved_3d : 2; // [31:30] + uint32_t user_fd_rssi_seg0 : 32; // [31:0] + uint32_t user_fd_rssi_seg1 : 32; // [31:0] + uint32_t user_fd_rssi_seg2 : 32; // [31:0] + uint32_t user_fd_rssi_seg3 : 32; // [31:0] +#else + uint32_t reception_type : 3, // [31:29] + stbc : 1, // [28:28] + pkt_type : 4, // [27:24] + user_rssi : 8, // [23:16] + phy_ppdu_id : 16; // [15:0] + uint32_t dl_ofdma_user_index : 8, // [31:24] + reserved_1b : 5, // [23:19] + receive_bandwidth : 3, // [18:16] + mimo_ss_bitmap : 8, // [15:8] + reserved_1a : 1, // [7:7] + he_ranging_ndp : 1, // [6:6] + sgi : 2, // [5:4] + rate_mcs : 4; // [3:0] + uint32_t ru_type_80_3 : 4, // [31:28] + ru_type_80_2 : 4, // [27:24] + ru_type_80_1 : 4, // [23:20] + ru_type_80_0 : 4, // [19:16] + ldpc : 1, // [15:15] + sta_dcm : 1, // [14:14] + stream_offset : 3, // [13:11] + nss : 3, // [10:8] + reserved_2a : 7, // [7:1] + dl_ofdma_content_channel : 1; // [0:0] + uint32_t reserved_3d : 2, // [31:30] + ru_start_index_80_3 : 6, // [29:24] + reserved_3c : 2, // [23:22] + ru_start_index_80_2 : 6, // [21:16] + reserved_3b : 2, // [15:14] + ru_start_index_80_1 : 6, // [13:8] + reserved_3a : 2, // [7:6] + ru_start_index_80_0 : 6; // [5:0] + uint32_t user_fd_rssi_seg0 : 32; // [31:0] + uint32_t user_fd_rssi_seg1 : 32; // [31:0] + uint32_t user_fd_rssi_seg2 : 32; // [31:0] + uint32_t user_fd_rssi_seg3 : 32; // [31:0] +#endif +}; + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff + + +/* Description USER_RSSI + + RSSI for this user + Frequency domain RSSI measurement for this user. Based on + the channel estimate. + + +*/ + +#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_USER_RSSI_LSB 16 +#define RECEIVE_USER_INFO_USER_RSSI_MSB 23 +#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 + + +/* Description PKT_TYPE + + Packet type: + + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 +#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 +#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_STBC_LSB 28 +#define RECEIVE_USER_INFO_STBC_MSB 28 +#define RECEIVE_USER_INFO_STBC_MASK 0x10000000 + + +/* Description RECEPTION_TYPE + + Indicates what type of reception this is. + Basic SU reception (not + part of OFDMA or MU-MIMO) + This is related to + DL type of reception + This is related to + DL type of reception + This is related + to DL type of reception + This is related + to UL type of reception + This is related + to UL type of reception + This is related + to UL type of reception + + +*/ + +#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + +*/ + +#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RATE_MCS_LSB 0 +#define RECEIVE_USER_INFO_RATE_MCS_MSB 3 +#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f + + +/* Description SGI + + Field only valid when pkt type is HT, VHT or HE. + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_SGI_LSB 4 +#define RECEIVE_USER_INFO_SGI_MSB 5 +#define RECEIVE_USER_INFO_SGI_MASK 0x00000030 + + +/* Description HE_RANGING_NDP + + Set to 1 for expected HE TB ranging NDP Rx in response to + sounding/secure sounding ranging Trigger Tx + + +*/ + +#define RECEIVE_USER_INFO_HE_RANGING_NDP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_HE_RANGING_NDP_LSB 6 +#define RECEIVE_USER_INFO_HE_RANGING_NDP_MSB 6 +#define RECEIVE_USER_INFO_HE_RANGING_NDP_MASK 0x00000040 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1A_LSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x00000080 + + +/* Description MIMO_SS_BITMAP + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + LSB related to SS 0 + + 0: spatial stream not used for this reception + 1: spatial stream used for this reception + + +*/ + +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 + + +/* Description RECEIVE_BANDWIDTH + + Full receive Bandwidth + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 + + +/* Description RESERVED_1B + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 +#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 + + +/* Description DL_OFDMA_USER_INDEX + + Field only valid in the of DL MU OFDMA reception + + The user number within the RU_allocation. + + This is needed for SW to determine the exact RU position + within the reception. + +*/ + +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 + + +/* Description DL_OFDMA_CONTENT_CHANNEL + + Field only valid in the of DL MU OFDMA/MIMO reception + + In case of DL MU reception, this field indicates the content + channel number where PHY found the RU information for this + user + + This is needed for SW to determine the exact RU position + within the reception. + + + + + +*/ + +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 + + +/* Description RESERVED_2A + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 +#define RECEIVE_USER_INFO_RESERVED_2A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe + + +/* Description NSS + + Field only valid in case of Uplink_receive_type == mimo_only + OR ofdma_mimo + + Number of Spatial Streams occupied by the User + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_NSS_LSB 8 +#define RECEIVE_USER_INFO_NSS_MSB 10 +#define RECEIVE_USER_INFO_NSS_MASK 0x00000700 + + +/* Description STREAM_OFFSET + + Field only valid in case of Uplink_receive_type == mimo_only + OR ofdma_mimo + + Stream Offset from which the User occupies the Streams + + Note MAC: + directly from pdg_fes_setup, based on BW +*/ + +#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 + + +/* Description STA_DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STA_DCM_LSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 + + +/* Description LDPC + + When set, use LDPC transmission rates were used. + +*/ + +#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_LDPC_LSB 15 +#define RECEIVE_USER_INFO_LDPC_MSB 15 +#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 + + +/* Description RU_TYPE_80_0 + + Indicates the size of the RU in the first 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 + + +/* Description RU_TYPE_80_1 + + Indicates the size of the RU in the second 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 + + +/* Description RU_TYPE_80_2 + + Indicates the size of the RU in the third 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 + + +/* Description RU_TYPE_80_3 + + Indicates the size of the RU in the fourth 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 + + +/* Description RU_START_INDEX_80_0 + + RU index number to which User is assigned in the first 80 + MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f + + +/* Description RESERVED_3A + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 +#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 + + +/* Description RU_START_INDEX_80_1 + + RU index number to which User is assigned in the second + 80 MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 + + +/* Description RESERVED_3B + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 +#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 +#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 + + +/* Description RU_START_INDEX_80_2 + + RU index number to which User is assigned in the third 80 + MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 + + +/* Description RESERVED_3C + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 +#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 + + +/* Description RU_START_INDEX_80_3 + + RU index number to which User is assigned in the fourth + 80 MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 + + +/* Description RESERVED_3D + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30 +#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 +#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000 + + +/* Description USER_FD_RSSI_SEG0 + + Frequency domain RSSI measurement for the lowest 80 MHz + subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff + + +/* Description USER_FD_RSSI_SEG1 + + Frequency domain RSSI measurement for the second lowest + 80 MHz subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff + + +/* Description USER_FD_RSSI_SEG2 + + Frequency domain RSSI measurement for the third lowest 80 + MHz subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff + + +/* Description USER_FD_RSSI_SEG3 + + Frequency domain RSSI measurement for the highest 80 MHz + subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff + + + +#endif // RECEIVE_USER_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/received_response_user_15_8.h b/drivers/staging/fw-api/hw/qcn6432/received_response_user_15_8.h new file mode 100644 index 0000000000000000000000000000000000000000..6abbee7ca11b2422df12c4320d14ae352cce585f --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/received_response_user_15_8.h @@ -0,0 +1,3075 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ +#define _RECEIVED_RESPONSE_USER_15_8_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32 + + +struct received_response_user_15_8 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#else + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#endif +}; + + +/* Description RECEIVED_RESPONSE_DETAILS_USER8 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER9 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER10 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER11 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER12 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER13 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER14 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER15 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + + +#endif // RECEIVED_RESPONSE_USER_15_8 diff --git a/drivers/staging/fw-api/hw/qcn6432/received_response_user_23_16.h b/drivers/staging/fw-api/hw/qcn6432/received_response_user_23_16.h new file mode 100644 index 0000000000000000000000000000000000000000..565575ca5fea3a90fdedbb2903e1dd2ad6c902ff --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/received_response_user_23_16.h @@ -0,0 +1,3074 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ +#define _RECEIVED_RESPONSE_USER_23_16_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32 + + +struct received_response_user_23_16 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#else + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#endif +}; + + +/* Description RECEIVED_RESPONSE_DETAILS_USER16 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER17 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER18 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER19 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER20 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER21 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER22 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER23 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + + +#endif // RECEIVED_RESPONSE_USER_23_16 diff --git a/drivers/staging/fw-api/hw/qcn6432/received_response_user_31_24.h b/drivers/staging/fw-api/hw/qcn6432/received_response_user_31_24.h new file mode 100644 index 0000000000000000000000000000000000000000..cf1b34a98e68e55adb454b6ce6f03a40b08b147d --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/received_response_user_31_24.h @@ -0,0 +1,3077 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ +#define _RECEIVED_RESPONSE_USER_31_24_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32 + + +struct received_response_user_31_24 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#else + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#endif +}; + + +/* Description RECEIVED_RESPONSE_DETAILS_USER24 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER25 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER26 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER27 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER28 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER29 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER30 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER31 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + + +#endif // RECEIVED_RESPONSE_USER_31_24 diff --git a/drivers/staging/fw-api/hw/qcn6432/received_response_user_36_32.h b/drivers/staging/fw-api/hw/qcn6432/received_response_user_36_32.h new file mode 100644 index 0000000000000000000000000000000000000000..120e33da33a331701cd8ea5bed911a0181fcb5fd --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/received_response_user_36_32.h @@ -0,0 +1,1936 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ +#define _RECEIVED_RESPONSE_USER_36_32_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20 + + +struct received_response_user_36_32 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#else + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#endif +}; + + +/* Description RECEIVED_RESPONSE_DETAILS_USER32 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER33 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER34 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER35 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER36 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + + +#endif // RECEIVED_RESPONSE_USER_36_32 diff --git a/drivers/staging/fw-api/hw/qcn6432/received_response_user_7_0.h b/drivers/staging/fw-api/hw/qcn6432/received_response_user_7_0.h new file mode 100644 index 0000000000000000000000000000000000000000..504cd139d70051867677c0c14c232d0a12920bbc --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/received_response_user_7_0.h @@ -0,0 +1,3076 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ +#define _RECEIVED_RESPONSE_USER_7_0_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32 + + +struct received_response_user_7_0 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#else + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#endif +}; + + +/* Description RECEIVED_RESPONSE_DETAILS_USER0 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER1 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER2 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER3 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER4 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER5 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER6 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER7 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + + +#endif // RECEIVED_RESPONSE_USER_7_0 diff --git a/drivers/staging/fw-api/hw/qcn6432/received_response_user_info.h b/drivers/staging/fw-api/hw/qcn6432/received_response_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..a43365550dc87ace50ee506192ee8491a2434d31 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/received_response_user_info.h @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ +#define _RECEIVED_RESPONSE_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 + + +struct received_response_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_fcs_pass_count : 12, // [11:0] + mpdu_fcs_fail_count : 12, // [23:12] + qosnull_frame_count : 4, // [27:24] + reserved_0a : 3, // [30:28] + user_info_valid : 1; // [31:31] + uint32_t null_delimiter_count : 22, // [21:0] + reserved_1a : 9, // [30:22] + ht_control_valid : 1; // [31:31] + uint32_t ht_control : 32; // [31:0] + uint32_t qos_control_valid : 16, // [15:0] + eosp : 16; // [31:16] + uint32_t qos_control_15_8_tid_0 : 8, // [7:0] + qos_control_15_8_tid_1 : 8, // [15:8] + qos_control_15_8_tid_2 : 8, // [23:16] + qos_control_15_8_tid_3 : 8; // [31:24] + uint32_t qos_control_15_8_tid_4 : 8, // [7:0] + qos_control_15_8_tid_5 : 8, // [15:8] + qos_control_15_8_tid_6 : 8, // [23:16] + qos_control_15_8_tid_7 : 8; // [31:24] + uint32_t qos_control_15_8_tid_8 : 8, // [7:0] + qos_control_15_8_tid_9 : 8, // [15:8] + qos_control_15_8_tid_10 : 8, // [23:16] + qos_control_15_8_tid_11 : 8; // [31:24] + uint32_t qos_control_15_8_tid_12 : 8, // [7:0] + qos_control_15_8_tid_13 : 8, // [15:8] + qos_control_15_8_tid_14 : 8, // [23:16] + qos_control_15_8_tid_15 : 8; // [31:24] +#else + uint32_t user_info_valid : 1, // [31:31] + reserved_0a : 3, // [30:28] + qosnull_frame_count : 4, // [27:24] + mpdu_fcs_fail_count : 12, // [23:12] + mpdu_fcs_pass_count : 12; // [11:0] + uint32_t ht_control_valid : 1, // [31:31] + reserved_1a : 9, // [30:22] + null_delimiter_count : 22; // [21:0] + uint32_t ht_control : 32; // [31:0] + uint32_t eosp : 16, // [31:16] + qos_control_valid : 16; // [15:0] + uint32_t qos_control_15_8_tid_3 : 8, // [31:24] + qos_control_15_8_tid_2 : 8, // [23:16] + qos_control_15_8_tid_1 : 8, // [15:8] + qos_control_15_8_tid_0 : 8; // [7:0] + uint32_t qos_control_15_8_tid_7 : 8, // [31:24] + qos_control_15_8_tid_6 : 8, // [23:16] + qos_control_15_8_tid_5 : 8, // [15:8] + qos_control_15_8_tid_4 : 8; // [7:0] + uint32_t qos_control_15_8_tid_11 : 8, // [31:24] + qos_control_15_8_tid_10 : 8, // [23:16] + qos_control_15_8_tid_9 : 8, // [15:8] + qos_control_15_8_tid_8 : 8; // [7:0] + uint32_t qos_control_15_8_tid_15 : 8, // [31:24] + qos_control_15_8_tid_14 : 8, // [23:16] + qos_control_15_8_tid_13 : 8, // [15:8] + qos_control_15_8_tid_12 : 8; // [7:0] +#endif +}; + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + + + +#endif // RECEIVED_RESPONSE_USER_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/received_trigger_info.h b/drivers/staging/fw-api/hw/qcn6432/received_trigger_info.h new file mode 100644 index 0000000000000000000000000000000000000000..eaf9548a78e62b97ebfe22a00f818187840840a7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/received_trigger_info.h @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_TRIGGER_INFO_H_ +#define _RECEIVED_TRIGGER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_trigger_info_details.h" +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6 + +#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3 + + +struct received_trigger_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_trigger_info_details received_trigger_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct received_trigger_info_details received_trigger_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description RECEIVED_TRIGGER_DETAILS + + Info related to the type of trigger (that potentially requires + SIFS response) that was received +*/ + + +/* Description TRIGGER_TYPE + + This field indicates for what type of trigger has been received + + + + + + + Field "AX_trigger_type" indicates the ID of the received + trigger + + Field "AX_trigger_type" indicates the ID of the received + trigger + + Field "AX_trigger_type" indicates the ID of the received + trigger + + Field "AX_trigger_type" indicates the ID of the received + trigger + Field "AX_trigger_type" + indicates the subtype of the received trigger + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f + + +/* Description AX_TRIGGER_SOURCE + + Field Only valid when Trigger_type is an 11ax related trigger + + + + + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010 + + +/* Description AX_TRIGGER_TYPE + + Field Only valid when Trigger_type is an 11ax related trigger + + + The 11AX trigger type/ trigger number: + It identifies which trigger was received. + + + + + + + + + Indicates the reception of + Ranging Trigger Frame of subvariant indicated by Ranging_Trigger_Subtype + + + + + + + + + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0 + + +/* Description TRIGGER_SOURCE_STA_FULL_AID + + The sta_full_aid of the sta/ap that generated the trigger. + + Comes from the address_search_entry + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00 + + +/* Description FRAME_CONTROL_VALID + + When set, the 'frame_control' field contains valid info + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000 + + +/* Description QOS_CONTROL_VALID + + When set, the 'QoS_control' field contains valid info + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000 + + +/* Description HE_CONTROL_INFO_VALID + + When set, the 'HE control' field contains valid info + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000 + + +/* Description RANGING_TRIGGER_SUBTYPE + + Field only valid if AX_Trigger_type = ax_tb_ranging_trigger + + + Indicates the Trigger subtype for the current ranging TF + + + + + + + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000001e000000 + + +/* Description RESERVED_0B + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_LSB 29 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MASK 0x00000000e0000000 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000 + + +/* Description LSIG_RESPONSE_LENGTH + + Field only valid in case of OFDMA trigger + + Indicates the value of the L-SIG Length field of the HE + trigger-based PPDU that is the response to the Trigger frame + + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 60 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0xf000000000000000 + + +/* Description FRAME_CONTROL + + frame control field of the received frame + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff + + +/* Description QOS_CONTROL + + frame control field of the received frame (if present) + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000 + + +/* Description SW_PEER_ID + + A unique identifier for this STA. Extracted from the Address_Search_Entry + + + Used by the SCH to find linkage between this trigger and + potentially pre-programmed responses. + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 + + +/* Description RESERVED_3A + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 48 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xffff000000000000 + + +/* Description HE_CONTROL + + Field only valid when HE_control_info_valid is set + + This is the 'RAW HE_CONTROL field' that was present in the + frame. + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_OFFSET 0x0000000000000010 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_LSB 32 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MSB 63 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RECEIVED_TRIGGER_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/received_trigger_info_details.h b/drivers/staging/fw-api/hw/qcn6432/received_trigger_info_details.h new file mode 100644 index 0000000000000000000000000000000000000000..4f4ae9d63e96d96f9b0a0f3a642988a89aa43420 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/received_trigger_info_details.h @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ +#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5 + + +struct received_trigger_info_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t trigger_type : 4, // [3:0] + ax_trigger_source : 1, // [4:4] + ax_trigger_type : 4, // [8:5] + trigger_source_sta_full_aid : 13, // [21:9] + frame_control_valid : 1, // [22:22] + qos_control_valid : 1, // [23:23] + he_control_info_valid : 1, // [24:24] + ranging_trigger_subtype : 4, // [28:25] + reserved_0b : 3; // [31:29] + uint32_t phy_ppdu_id : 16, // [15:0] + lsig_response_length : 12, // [27:16] + reserved_1a : 4; // [31:28] + uint32_t frame_control : 16, // [15:0] + qos_control : 16; // [31:16] + uint32_t sw_peer_id : 16, // [15:0] + reserved_3a : 16; // [31:16] + uint32_t he_control : 32; // [31:0] +#else + uint32_t reserved_0b : 3, // [31:29] + ranging_trigger_subtype : 4, // [28:25] + he_control_info_valid : 1, // [24:24] + qos_control_valid : 1, // [23:23] + frame_control_valid : 1, // [22:22] + trigger_source_sta_full_aid : 13, // [21:9] + ax_trigger_type : 4, // [8:5] + ax_trigger_source : 1, // [4:4] + trigger_type : 4; // [3:0] + uint32_t reserved_1a : 4, // [31:28] + lsig_response_length : 12, // [27:16] + phy_ppdu_id : 16; // [15:0] + uint32_t qos_control : 16, // [31:16] + frame_control : 16; // [15:0] + uint32_t reserved_3a : 16, // [31:16] + sw_peer_id : 16; // [15:0] + uint32_t he_control : 32; // [31:0] +#endif +}; + + +/* Description TRIGGER_TYPE + + This field indicates for what type of trigger has been received + + + + + + + Field "AX_trigger_type" indicates the ID of the received + trigger + + Field "AX_trigger_type" indicates the ID of the received + trigger + + Field "AX_trigger_type" indicates the ID of the received + trigger + + Field "AX_trigger_type" indicates the ID of the received + trigger + Field "AX_trigger_type" + indicates the subtype of the received trigger + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + + +/* Description AX_TRIGGER_SOURCE + + Field Only valid when Trigger_type is an 11ax related trigger + + + + + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 + + +/* Description AX_TRIGGER_TYPE + + Field Only valid when Trigger_type is an 11ax related trigger + + + The 11AX trigger type/ trigger number: + It identifies which trigger was received. + + + + + + + + + Indicates the reception of + Ranging Trigger Frame of subvariant indicated by Ranging_Trigger_Subtype + + + + + + + + + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 + + +/* Description TRIGGER_SOURCE_STA_FULL_AID + + The sta_full_aid of the sta/ap that generated the trigger. + + Comes from the address_search_entry + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 + + +/* Description FRAME_CONTROL_VALID + + When set, the 'frame_control' field contains valid info + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 + + +/* Description QOS_CONTROL_VALID + + When set, the 'QoS_control' field contains valid info + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 + + +/* Description HE_CONTROL_INFO_VALID + + When set, the 'HE control' field contains valid info + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 + + +/* Description RANGING_TRIGGER_SUBTYPE + + Field only valid if AX_Trigger_type = ax_tb_ranging_trigger + + + Indicates the Trigger subtype for the current ranging TF + + + + + + + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000 + + +/* Description RESERVED_0B + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_LSB 29 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MASK 0xe0000000 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + + +/* Description LSIG_RESPONSE_LENGTH + + Field only valid in case of OFDMA trigger + + Indicates the value of the L-SIG Length field of the HE + trigger-based PPDU that is the response to the Trigger frame + + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000 + + +/* Description FRAME_CONTROL + + frame control field of the received frame + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff + + +/* Description QOS_CONTROL + + frame control field of the received frame (if present) + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 + + +/* Description SW_PEER_ID + + A unique identifier for this STA. Extracted from the Address_Search_Entry + + + Used by the SCH to find linkage between this trigger and + potentially pre-programmed responses. + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff + + +/* Description RESERVED_3A + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xffff0000 + + +/* Description HE_CONTROL + + Field only valid when HE_control_info_valid is set + + This is the 'RAW HE_CONTROL field' that was present in the + frame. + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff + + + +#endif // RECEIVED_TRIGGER_INFO_DETAILS diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_descriptor_threshold_reached_status.h b/drivers/staging/fw-api/hw/qcn6432/reo_descriptor_threshold_reached_status.h new file mode 100644 index 0000000000000000000000000000000000000000..0e64268c3e41bec203b44b473407eb28c2e82e90 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_descriptor_threshold_reached_status.h @@ -0,0 +1,563 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 26 + +#define NUM_OF_QWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 13 + + +struct reo_descriptor_threshold_reached_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t threshold_index : 2, // [1:0] + reserved_2 : 30; // [31:2] + uint32_t link_descriptor_counter0 : 24, // [23:0] + reserved_3 : 8; // [31:24] + uint32_t link_descriptor_counter1 : 24, // [23:0] + reserved_4 : 8; // [31:24] + uint32_t link_descriptor_counter2 : 24, // [23:0] + reserved_5 : 8; // [31:24] + uint32_t link_descriptor_counter_sum : 26, // [25:0] + reserved_6 : 6; // [31:26] + uint32_t reserved_7 : 32; // [31:0] + uint32_t reserved_8 : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t reserved_25a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 30, // [31:2] + threshold_index : 2; // [1:0] + uint32_t reserved_3 : 8, // [31:24] + link_descriptor_counter0 : 24; // [23:0] + uint32_t reserved_4 : 8, // [31:24] + link_descriptor_counter1 : 24; // [23:0] + uint32_t reserved_5 : 8, // [31:24] + link_descriptor_counter2 : 24; // [23:0] + uint32_t reserved_6 : 6, // [31:26] + link_descriptor_counter_sum : 26; // [25:0] + uint32_t reserved_7 : 32; // [31:0] + uint32_t reserved_8 : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 28; // [27:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description THRESHOLD_INDEX + + The index of the threshold register whose value got reached + + + + + + + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x0000000000000003 + + +/* Description RESERVED_2 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0x00000000fffffffc + + +/* Description LINK_DESCRIPTOR_COUNTER0 + + Value of this counter at generation of this message + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 55 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff00000000 + + +/* Description RESERVED_3 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 56 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff00000000000000 + + +/* Description LINK_DESCRIPTOR_COUNTER1 + + Value of this counter at generation of this message + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x0000000000ffffff + + +/* Description RESERVED_4 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0x00000000ff000000 + + +/* Description LINK_DESCRIPTOR_COUNTER2 + + Value of this counter at generation of this message + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 55 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff00000000 + + +/* Description RESERVED_5 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 56 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff00000000000000 + + +/* Description LINK_DESCRIPTOR_COUNTER_SUM + + Value of this counter at generation of this message + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000000000000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x0000000003ffffff + + +/* Description RESERVED_6 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000000000000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0x00000000fc000000 + + +/* Description RESERVED_7 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x0000000000000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff00000000 + + +/* Description RESERVED_8 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x0000000000000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description RESERVED_10A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + +/* Description RESERVED_11A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + +/* Description RESERVED_12A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + +/* Description RESERVED_13A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + +/* Description RESERVED_14A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + +/* Description RESERVED_15A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + +/* Description RESERVED_16A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + +/* Description RESERVED_17A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + +/* Description RESERVED_18A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + +/* Description RESERVED_19A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + +/* Description RESERVED_20A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + +/* Description RESERVED_21A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + +/* Description RESERVED_22A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + +/* Description RESERVED_23A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + +/* Description RESERVED_25A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 59 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 60 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_destination_ring.h b/drivers/staging/fw-api/hw/qcn6432/reo_destination_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..80fc32b88c066b92d7b26c2a6a7818a2c44bf191 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_destination_ring.h @@ -0,0 +1,945 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_DESTINATION_RING_H_ +#define _REO_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_REO_DESTINATION_RING 8 + + +struct reo_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t reo_dest_buffer_type : 1, // [0:0] + reo_push_reason : 2, // [2:1] + reo_error_code : 5, // [7:3] + captured_msdu_data_size : 4, // [11:8] + sw_exception : 1, // [12:12] + src_link_id : 3, // [15:13] + reo_destination_struct_signature : 4, // [19:16] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reo_destination_struct_signature : 4, // [19:16] + src_link_id : 3, // [15:13] + sw_exception : 1, // [12:12] + captured_msdu_data_size : 4, // [11:8] + reo_error_code : 5, // [7:3] + reo_push_reason : 2, // [2:1] + reo_dest_buffer_type : 1; // [0:0] +#endif +}; + + +/* Description BUF_OR_LINK_DESC_ADDR_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Details of the physical address of the a buffer or MSDU + link descriptor +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MPDU_DESC_INFO_DETAILS + + Consumer: REO/SW/FW + Producer: RXDMA + + General information related to the MPDU that is passed on + from REO entrance ring to the REO destination ring + + When enabled in REO, REO will overwrite this structure to + have only the 'Msdu_count' field and 56 bits of the previous + PN from 'RX_REO_QUEUE' +*/ + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + General information related to the MSDU that is passed on + from RXDMA all the way to to the REO destination ring. +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description BUFFER_VIRT_ADDR_31_0 + + Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address + + + Lower 32 bits of the 64-bit virtual address corresponding + to Buf_or_link_desc_addr_info + +*/ + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_VIRT_ADDR_63_32 + + Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address + + + Upper 32 bits of the 64-bit virtual address corresponding + to Buf_or_link_desc_addr_info + +*/ + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + + +/* Description REO_DEST_BUFFER_TYPE + + Indicates the type of address provided in the 'Buf_or_link_desc_addr_info' + + + The address of an MSDU buffer + The address of the MSDU + link descriptor. + + +*/ + +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 + + +/* Description REO_PUSH_REASON + + Indicates why REO pushed the frame to this exit ring + + Reo detected an error an pushed + this frame to this queue + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + +*/ + +#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 + + +/* Description REO_ERROR_CODE + + Field only valid when 'Reo_push_reason' set to 'reo_error_detected'. + + + Reo queue descriptor provided + in the REO_ENTRANCE ring is set to 0 + Reo queue descriptor valid + bit is NOT set + AMPDU frame received without BA + session having been setup. + Non-BA session, SN equal to SSN, + Retry bit set: duplicate frame + BA session, duplicate frame + A normal (management/data + frame) received with 2K jump in SN + A bar received with 2K jump in + SSN + A normal (management/data frame) + received with SN falling within the OOR window + A bar received with SSN falling within + the OOR window + A bar received without + a BA session + A bar received with SSN + equal to SN + PN Check Failed packet. + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set + in the REO Queue descriptor + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in + the REO Queue descriptor + Frame is forwarded + as a result of the queue descriptor(address) being blocked + as SW/FW seems to be currently in the process of making + updates to this descriptor... + + +*/ + +#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 + + +/* Description CAPTURED_MSDU_DATA_SIZE + + The number of following REO_DESTINATION STRUCTs that have + been replaced with msdu_data extracted from the msdu_buffer + and copied into the ring for easy FW/SW access. + Note that it is possible that these STRUCTs wrap around + the end of the ring. + +*/ + +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 + + +/* Description SW_EXCEPTION + + This field has the same setting as the SW_exception field + in the corresponding REO_entrance_ring descriptor. + When set, the REO entrance descriptor is generated by FW, + and the MPDU was processed in the following way: + - NO re-order function is needed. + - MPDU delinking is determined by the setting of Entrance + ring field: SW_excection_mpdu_delink + - Destination ring selection is based on the setting of + the Entrance ring field SW_exception_destination _ring_valid + + +*/ + +#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 +#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 +#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 + + +/* Description REO_DESTINATION_STRUCT_SIGNATURE + + Set to value 0x8 when msdu capture mode is enabled for this + ring +*/ + +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 + + +/* Description RING_ID + + The buffer pointer ring ID. + 0 refers to the IDLE ring + 1 - N refers to other rings + + Helps with debugging when dumping ring contents. + + This can be used in conjunction with the Reo_destination_struct_signature. + + + For debugging, if enabled, REO may fill the Rx MPDU sequence + number in {Looping_count, ring_id}. + + +*/ + +#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_RING_ID_LSB 20 +#define REO_DESTINATION_RING_RING_ID_MSB 27 +#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + For debugging, if enabled, REO may fill the Rx MPDU sequence + number in {Looping_count, ring_id}. + + +*/ + +#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // REO_DESTINATION_RING diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_entrance_ring.h b/drivers/staging/fw-api/hw/qcn6432/reo_entrance_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..4c6e500559440bd84e46c6f749c5205add5123b5 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_entrance_ring.h @@ -0,0 +1,933 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_ENTRANCE_RING_H_ +#define _REO_ENTRANCE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_details.h" +#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 + + +struct reo_entrance_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] + rounded_mpdu_byte_count : 14, // [21:8] + reo_destination_indication : 5, // [26:22] + frameless_bar : 1, // [27:27] + reserved_5a : 4; // [31:28] + uint32_t rxdma_push_reason : 2, // [1:0] + rxdma_error_code : 5, // [6:2] + mpdu_fragment_number : 4, // [10:7] + sw_exception : 1, // [11:11] + sw_exception_mpdu_delink : 1, // [12:12] + sw_exception_destination_ring_valid : 1, // [13:13] + sw_exception_destination_ring : 5, // [18:14] + mpdu_sequence_number : 12, // [30:19] + reserved_6a : 1; // [31:31] + uint32_t phy_ppdu_id : 16, // [15:0] + src_link_id : 3, // [18:16] + reserved_7a : 1, // [19:19] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t reserved_5a : 4, // [31:28] + frameless_bar : 1, // [27:27] + reo_destination_indication : 5, // [26:22] + rounded_mpdu_byte_count : 14, // [21:8] + rx_reo_queue_desc_addr_39_32 : 8; // [7:0] + uint32_t reserved_6a : 1, // [31:31] + mpdu_sequence_number : 12, // [30:19] + sw_exception_destination_ring : 5, // [18:14] + sw_exception_destination_ring_valid : 1, // [13:13] + sw_exception_mpdu_delink : 1, // [12:12] + sw_exception : 1, // [11:11] + mpdu_fragment_number : 4, // [10:7] + rxdma_error_code : 5, // [6:2] + rxdma_push_reason : 2; // [1:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reserved_7a : 1, // [19:19] + src_link_id : 3, // [18:16] + phy_ppdu_id : 16; // [15:0] +#endif +}; + + +/* Description REO_LEVEL_MPDU_FRAME_INFO + + Consumer: REO + Producer: RXDMA + + Details related to the MPDU being pushed into the REO +*/ + + +/* Description MSDU_LINK_DESC_ADDR_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Details of the physical address of the MSDU link descriptor + that contains pointers to MSDUs related to this MPDU +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MPDU_DESC_INFO_DETAILS + + Consumer: REO/SW/FW + Producer: RXDMA + + General information related to the MPDU that should be passed + on from REO entrance ring to the REO destination ring +*/ + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + +/* Description RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + Producer: RXDMA + + Address (lower 32 bits) of the REO queue descriptor + + Alternatively, REO internally looks up the + queue descriptor address from 'Sw_peer_id' and 'Tid.' In + this mode, RXDMA fills 'Sw_peer_id' from 'RX_MPDU_START' + in the LSB 16 bits. 'Tid' is available in 'RX_MPDU_DETAILS.' + + +*/ + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + + +/* Description RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + Producer: RXDMA + + Address (upper 8 bits) of the REO queue descriptor + Alternatively, REO internally looks up the + queue descriptor address from 'Sw_peer_id' and 'Tid.' In + this mode, this field is unused. + +*/ + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + + +/* Description ROUNDED_MPDU_BYTE_COUNT + + An approximation of the number of bytes received in this + MPDU. + Used to keeps stats on the amount of data flowing through + a queue. + +*/ + +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 + + +/* Description REO_DESTINATION_INDICATION + + RXDMA copy the MPDU's first MSDU's destination indication + field here. This is used for REO to be able to re-route + the packet to a different SW destination ring if the packet + is detected as error in REO. + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 + + +/* Description FRAMELESS_BAR + + When set, this REO entrance ring struct contains BAR info + from a multi TID BAR frame. The original multi TID BAR + frame itself contained all the REO info for the first TID, + but all the subsequent TID info and their linkage to the + REO descriptors is passed down as 'frameless' BAR info. + + + The only fields valid in this descriptor when this bit is + set are: + Rx_reo_queue_desc_addr_31_0 + RX_reo_queue_desc_addr_39_32 + + And within the + Reo_level_mpdu_frame_info: + Within Rx_mpdu_desc_info_details: + Mpdu_Sequence_number + BAR_frame + Peer_meta_data + All other fields shall be set to 0 + + +*/ + +#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 + + +/* Description RESERVED_5A + + +*/ + +#define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RESERVED_5A_LSB 28 +#define REO_ENTRANCE_RING_RESERVED_5A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000 + + +/* Description RXDMA_PUSH_REASON + + Indicates why rxdma pushed the frame to this ring + + This field is ignored by REO. + + RXDMA detected an error an + pushed this frame to this queue + RXDMA pushed the frame + to this queue per received routing instructions. No error + within RXDMA was detected + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" + set, but instead WBM might just see a NULL pointer in the + MSDU link descriptor. This is to be considered a normal + condition for this scenario. + + +*/ + +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 + + +/* Description RXDMA_ERROR_CODE + + Field only valid when 'rxdma_push_reason' set to 'rxdma_error_detected'. + + + This field is ignored by REO. + + MPDU frame is not complete due + to a FIFO overflow error in RXPCU. + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + FCS check on the MPDU frame failed + + CRYPTO reported a decryption error + or CRYPTO received an encrypted frame, but did not get + a valid corresponding key id in the peer entry. + CRYPTO reported a TKIP MIC error + + CRYPTO reported an unencrypted + frame error when encrypted was expected + RX OLE reported an MSDU length + error + RX OLE reported that max number + of MSDUs allowed in an MPDU got exceeded + RX OLE reported a parsing error + + RX OLE reported an A-MSDU + parsing error + RX OLE reported a timeout + during SA search + RX OLE reported a timeout + during DA search + RX OLE reported a timeout + during flow search + RXDMA received a flush request + + RX OLE reported a multicast + echo + RX OLE reported an + A-MSDU with either 'from DS = 0' with an SA mismatching + TA or 'to DS = 0' with a DA mismatching RA. + RX PCU reported that + Rx peer entry did not indicate 'authorized_to_send_WDS' + and also indicated 'from DS = to DS = 1.' + RX PCU reported + a broadcast or multicast RA as well as either A-MSDU present + or 'from DS = to DS = 1.' +*/ + +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c + + +/* Description MPDU_FRAGMENT_NUMBER + + Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.Fragment_flag + is set. + + The fragment number from the 802.11 header. + + Note that the sequence number is embedded in the field: + Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. Mpdu_sequence_number + + + +*/ + +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + + +/* Description SW_EXCEPTION + + When not set, REO is performing all its default MPDU processing + operations, + When set, this REO entrance descriptor is generated by FW, + and should be processed as an exception. This implies: + NO re-order function is needed. + MPDU delinking is determined by the setting of field SW_excection_mpdu_delink + + Destination ring selection is based on the setting of the + field SW_exception_destination_ring_valid + In the destination ring descriptor set bit: SW_exception_entry + + +*/ + +#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 + + +/* Description SW_EXCEPTION_MPDU_DELINK + + Field only valid when SW_exception is set. + 1'b0: REO should NOT delink the MPDU, and thus pass this + MPDU on to the destination ring as is. This implies that + in the REO_DESTINATION_RING struct field Buf_or_link_desc_addr_info + should point to an MSDU link descriptor + 1'b1: REO should perform the normal MPDU delink into MSDU + operations. + +*/ + +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 + + +/* Description SW_EXCEPTION_DESTINATION_RING_VALID + + Field only valid when SW_exception is set. + 1'b0: REO shall push the MPDU (or delinked MPDU based on + the setting of SW_exception_mpdu_delink) to the destination + ring according to field reo_destination_indication. + 1'b1: REO shall push the MPDU (or delinked MPDU based on + the setting of SW_exception_mpdu_delink) to the destination + ring according to field SW_exception_destination_ring. + +*/ + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 + + +/* Description SW_EXCEPTION_DESTINATION_RING + + Field only valid when fields SW_exception and SW_exception_destination_ring_valid + are set. + The ID of the ring where REO shall push this frame. + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 + + +/* Description MPDU_SEQUENCE_NUMBER + + Consumer: REO/SW/FW + Producer: RXDMA + + The field can have two different meanings based on the setting + of sub-field Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.BAR_frame: + + + 'BAR_frame' is NOT set: + The MPDU sequence number of the received frame. + + 'BAR_frame' is set. + The MPDU Start sequence number from the BAR frame + +*/ + +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 + + +/* Description RESERVED_6A + + Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. + Mpdu_qos_control_valid is set + + This indicates whether the 'Ack policy' field within the + QoS control field of the MPDU indicates 'no-Ack.' + +*/ + +#define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RESERVED_6A_LSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000 + + +/* Description PHY_PPDU_ID + + A PPDU counter value that PHY increments for every PPDU + received + The counter value wraps around. RXDMA can be configured + to copy this from the RX_PPDU_START TLV for every output + descriptor. + + This field is ignored by REO. + + +*/ + +#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 + + + +#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RESERVED_7A_LSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000 + + +/* Description RING_ID + + Consumer: SW/REO/DEBUG + Producer: SRNG (of RXDMA) + + For debugging. + This field is filled in by the SRNG module. + It help to identify the ring that is being looked +*/ + +#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RING_ID_LSB 20 +#define REO_ENTRANCE_RING_RING_ID_MSB 27 +#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: SW/REO/DEBUG + Producer: SRNG (of RXDMA) + + For debugging. + This field is filled in by the SRNG module. + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // REO_ENTRANCE_RING diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_flush_cache.h b/drivers/staging/fw-api/hw/qcn6432/reo_flush_cache.h new file mode 100644 index 0000000000000000000000000000000000000000..63fd70669c2f14b1721097ae6becbb3c3d388c9e --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_flush_cache.h @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_FLUSH_CACHE_H_ +#define _REO_FLUSH_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE 10 + +#define NUM_OF_QWORDS_REO_FLUSH_CACHE 5 + + +struct reo_flush_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; // [31:0] + uint32_t flush_addr_39_32 : 8, // [7:0] + forward_all_mpdus_in_queue : 1, // [8:8] + release_cache_block_index : 1, // [9:9] + cache_block_resource_index : 2, // [11:10] + flush_without_invalidate : 1, // [12:12] + block_cache_usage_after_flush : 1, // [13:13] + flush_entire_cache : 1, // [14:14] + flush_queue_1k_desc : 1, // [15:15] + reserved_2b : 16; // [31:16] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; // [31:0] + uint32_t reserved_2b : 16, // [31:16] + flush_queue_1k_desc : 1, // [15:15] + flush_entire_cache : 1, // [14:14] + block_cache_usage_after_flush : 1, // [13:13] + flush_without_invalidate : 1, // [12:12] + cache_block_resource_index : 2, // [11:10] + release_cache_block_index : 1, // [9:9] + forward_all_mpdus_in_queue : 1, // [8:8] + flush_addr_39_32 : 8; // [7:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description CMD_HEADER + + Consumer: REO + Producer: SW + + Details for command execution tracking purposes. +*/ + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + +/* Description FLUSH_ADDR_31_0 + + Consumer: REO + Producer: SW + + Address (lower 32 bits) of the descriptor to flush + +*/ + +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000 + + +/* Description FLUSH_ADDR_39_32 + + Consumer: REO + Producer: SW + + Address (upper 8 bits) of the descriptor to flush + +*/ + +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff + + +/* Description FORWARD_ALL_MPDUS_IN_QUEUE + + Is only allowed to be set when the flush address corresponds + with a REO descriptor. + + When set, REO shall first forward all the MPDUs held in + the indicated re-order queue, before flushing the descriptor + from the cache. + +*/ + +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100 + + +/* Description RELEASE_CACHE_BLOCK_INDEX + + Field not valid when Flush_entire_cache is set. + + If SW has previously used a blocking resource that it now + wants to re-use for this command, this bit shall be set. + It prevents SW from having to send a separate REO_UNBLOCK_CACHE + command. + + When set, HW will first release the blocking resource (indicated + in field 'Cache_block_resouce_index') before this command + gets executed. + If that resource was already unblocked, this will be considered + an error. This command will not be executed, and an error + shall be returned. + +*/ + +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200 + + +/* Description CACHE_BLOCK_RESOURCE_INDEX + + Field not valid when Flush_entire_cache is set. + + Indicates which of the four blocking resources in REO will + be assigned for managing the blocking of this (descriptor) + address + +*/ + +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00 + + +/* Description FLUSH_WITHOUT_INVALIDATE + + Field not valid when Flush_entire_cache is set. + + When set, REO shall flush the cache line contents from the + cache, but there is NO need to invalidate the cache line + entry... The contents in the cache can be maintained. This + feature can be used by SW (and DV) to get a current snapshot + of the contents in the cache + + +*/ + +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000 + + +/* Description BLOCK_CACHE_USAGE_AFTER_FLUSH + + Field not valid when Flush_entire_cache is set. + + When set, REO shall block any cache accesses to this address + till explicitly unblocked. + + Whenever SW sets this bit, SW shall also set bit 'Forward_all_mpdus_in_queue' + to ensure all packets are flushed out in order to make sure + this queue desc is not in one of the aging link lists. + In case SW does not want to flush the MPDUs in the queue, + see the recipe description below this TLV definition. + + The 'blocking' index to be used for this is indicated in + field 'cache_block_resource_index'. If SW had previously + used this blocking resource and was not freed up yet, SW + shall first unblock that index (by setting bit Release_cache_block_index) + or use an unblock command. + + If the resource indicated here was already blocked (and + did not get unblocked in this command), it is considered + an error scenario... + No flush shall happen. The status for this command shall + indicate error. + + +*/ + +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000 + + +/* Description FLUSH_ENTIRE_CACHE + + When set, the entire cache shall be flushed. The entire + cache will also remain blocked, till the 'REO_UNBLOCK_COMMAND' + is received with bit unblock type set to unblock_cache. + All other fields in this command are to be ignored. + + Note that flushing the entire cache has no changes to the + current settings of the blocking resource settings + + +*/ + +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000 + + +/* Description FLUSH_QUEUE_1K_DESC + + When set, REO will flush the 'RX_REO_QUEUE_1K' descriptor + after flushing the 'RX_REO_QUEUE' descriptor. + + This bit shall only be set when the BA_window_size > 255 + in 'RX_REO_QUEUE.' + +*/ + +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000 + + +/* Description RESERVED_2B + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 +#define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000 + + +/* Description RESERVED_3A + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_RESERVED_3A_LSB 32 +#define REO_FLUSH_CACHE_RESERVED_3A_MSB 63 +#define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_RESERVED_5A_LSB 32 +#define REO_FLUSH_CACHE_RESERVED_5A_MSB 63 +#define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_RESERVED_7A_LSB 32 +#define REO_FLUSH_CACHE_RESERVED_7A_MSB 63 +#define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32 +#define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63 +#define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // REO_FLUSH_CACHE diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_flush_cache_status.h b/drivers/staging/fw-api/hw/qcn6432/reo_flush_cache_status.h new file mode 100644 index 0000000000000000000000000000000000000000..d8d7e4adc68d4a0d7836935a721d7277eb435176 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_flush_cache_status.h @@ -0,0 +1,646 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_FLUSH_CACHE_STATUS_H_ +#define _REO_FLUSH_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26 + +#define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13 + + +struct reo_flush_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, // [0:0] + block_error_details : 2, // [2:1] + reserved_2a : 5, // [7:3] + cache_controller_flush_status_hit : 1, // [8:8] + cache_controller_flush_status_desc_type : 3, // [11:9] + cache_controller_flush_status_client_id : 4, // [15:12] + cache_controller_flush_status_error : 2, // [17:16] + cache_controller_flush_count : 8, // [25:18] + flush_queue_1k_desc : 1, // [26:26] + reserved_2b : 5; // [31:27] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t reserved_25a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2b : 5, // [31:27] + flush_queue_1k_desc : 1, // [26:26] + cache_controller_flush_count : 8, // [25:18] + cache_controller_flush_status_error : 2, // [17:16] + cache_controller_flush_status_client_id : 4, // [15:12] + cache_controller_flush_status_desc_type : 3, // [11:9] + cache_controller_flush_status_hit : 1, // [8:8] + reserved_2a : 5, // [7:3] + block_error_details : 2, // [2:1] + error_detected : 1; // [0:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 28; // [27:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description ERROR_DETECTED + + Status for blocking resource handling + + 0: No error has been detected while executing this command + + 1: an error in the blocking resource management was detected + + See field 'Block_error_details' +*/ + +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + + +/* Description BLOCK_ERROR_DETAILS + + Field only valid when 'Error_detected' is set. + 0: no blocking related error found + 1: blocking resource was already in use + 2: resource that was asked to be unblocked, was not blocked + + +*/ + +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x0000000000000006 + + +/* Description RESERVED_2A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x00000000000000f8 + + +/* Description CACHE_CONTROLLER_FLUSH_STATUS_HIT + + The status that the cache controller returned for executing + the flush command + + descriptor hit + 1 = hit + 0 = miss + +*/ + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x0000000000000100 + + +/* Description CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE + + The status that the cache controller returned for executing + the flush command + Descriptor type + FLOW_QUEUE_DESCRIPTOR 3'd0 + MPDU_LINK_DESCRIPTOR 3'd4 + +*/ + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x0000000000000e00 + + +/* Description CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID + + The status that the cache controller returned for executing + the flush command + + client ID + Module who made flush the request + + In REO, this is always set to 0 + +*/ + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x000000000000f000 + + +/* Description CACHE_CONTROLLER_FLUSH_STATUS_ERROR + + The status that the cache controller returned for executing + the flush command + + Error condition + 2'b00: No error found + 2'b01: HW IF still busy + 2'b10: Line is currently locked. Used for the one line flush + command. + 2'b11: At least one line is currently still locked. Used + for the cache flush command. + + +*/ + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x0000000000030000 + + +/* Description CACHE_CONTROLLER_FLUSH_COUNT + + The number of lines that were actually flushed out. + +*/ + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x0000000003fc0000 + + +/* Description FLUSH_QUEUE_1K_DESC + + When set, REO has flushed the 'RX_REO_QUEUE_1K' descriptor + after flushing the 'RX_REO_QUEUE' descriptor. + +*/ + +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x0000000004000000 + + +/* Description RESERVED_2B + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0x00000000f8000000 + + +/* Description RESERVED_3A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description RESERVED_10A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + +/* Description RESERVED_11A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + +/* Description RESERVED_12A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + +/* Description RESERVED_13A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + +/* Description RESERVED_14A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + +/* Description RESERVED_15A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + +/* Description RESERVED_16A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + +/* Description RESERVED_17A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + +/* Description RESERVED_18A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + +/* Description RESERVED_19A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + +/* Description RESERVED_20A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + +/* Description RESERVED_21A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + +/* Description RESERVED_22A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + +/* Description RESERVED_23A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + +/* Description RESERVED_25A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 59 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_FLUSH_CACHE_STATUS diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_flush_queue.h b/drivers/staging/fw-api/hw/qcn6432/reo_flush_queue.h new file mode 100644 index 0000000000000000000000000000000000000000..ef3b20a05a6c14f06c15e154d57403b5c2e15100 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_flush_queue.h @@ -0,0 +1,272 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_FLUSH_QUEUE_H_ +#define _REO_FLUSH_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10 + +#define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5 + + +struct reo_flush_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; // [31:0] + uint32_t flush_desc_addr_39_32 : 8, // [7:0] + block_desc_addr_usage_after_flush : 1, // [8:8] + block_resource_index : 2, // [10:9] + reserved_2a : 21; // [31:11] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; // [31:0] + uint32_t reserved_2a : 21, // [31:11] + block_resource_index : 2, // [10:9] + block_desc_addr_usage_after_flush : 1, // [8:8] + flush_desc_addr_39_32 : 8; // [7:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description CMD_HEADER + + Consumer: REO + Producer: SW + + Details for command execution tracking purposes. +*/ + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + +/* Description FLUSH_DESC_ADDR_31_0 + + Consumer: REO + Producer: SW + + Address (lower 32 bits) of the descriptor to flush + +*/ + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000 + + +/* Description FLUSH_DESC_ADDR_39_32 + + Consumer: REO + Producer: SW + + Address (upper 8 bits) of the descriptor to flush + +*/ + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff + + +/* Description BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH + + When set, REO shall not re-fetch this address till SW explicitly + unblocked this address + + If the blocking resource was already used, this command + shall fail and an error is reported + + +*/ + +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100 + + +/* Description BLOCK_RESOURCE_INDEX + + Field only valid when 'Block_desc_addr_usage_after_flush + ' is set. + + Indicates which of the four blocking resources in REO will + be assigned for managing the blocking of this address. + +*/ + +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600 + + +/* Description RESERVED_2A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 +#define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff800 + + +/* Description RESERVED_3A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32 +#define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63 +#define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32 +#define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63 +#define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32 +#define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63 +#define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32 +#define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63 +#define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // REO_FLUSH_QUEUE diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_flush_queue_status.h b/drivers/staging/fw-api/hw/qcn6432/reo_flush_queue_status.h new file mode 100644 index 0000000000000000000000000000000000000000..27edde9d0a3f427854752bb08bb2808a85442b31 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_flush_queue_status.h @@ -0,0 +1,503 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_FLUSH_QUEUE_STATUS_H_ +#define _REO_FLUSH_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26 + +#define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13 + + +struct reo_flush_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, // [0:0] + reserved_2a : 31; // [31:1] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t reserved_25a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 31, // [31:1] + error_detected : 1; // [0:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 28; // [27:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description ERROR_DETECTED + + Status of the blocking resource + 0: No error has been detected while executing this command + + 1: Error detected: The resource to be used for blocking + was already in use. +*/ + +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + + +/* Description RESERVED_2A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000fffffffe + + +/* Description RESERVED_3A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description RESERVED_10A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + +/* Description RESERVED_11A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + +/* Description RESERVED_12A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + +/* Description RESERVED_13A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + +/* Description RESERVED_14A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + +/* Description RESERVED_15A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + +/* Description RESERVED_16A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + +/* Description RESERVED_17A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + +/* Description RESERVED_18A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + +/* Description RESERVED_19A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + +/* Description RESERVED_20A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + +/* Description RESERVED_21A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + +/* Description RESERVED_22A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + +/* Description RESERVED_23A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + +/* Description RESERVED_25A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 59 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_FLUSH_QUEUE_STATUS diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_flush_timeout_list.h b/drivers/staging/fw-api/hw/qcn6432/reo_flush_timeout_list.h new file mode 100644 index 0000000000000000000000000000000000000000..7cde3b5c261c28ec62635d9180ea0dfd2e59c407 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_flush_timeout_list.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_FLUSH_TIMEOUT_LIST_H_ +#define _REO_FLUSH_TIMEOUT_LIST_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 10 + +#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST 5 + + +struct reo_flush_timeout_list { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t ac_timout_list : 2, // [1:0] + reserved_1 : 30; // [31:2] + uint32_t minimum_release_desc_count : 16, // [15:0] + minimum_forward_buf_count : 16; // [31:16] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1 : 30, // [31:2] + ac_timout_list : 2; // [1:0] + uint32_t minimum_forward_buf_count : 16, // [31:16] + minimum_release_desc_count : 16; // [15:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description CMD_HEADER + + Consumer: REO + Producer: SW + + Details for command execution tracking purposes. +*/ + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + +/* Description AC_TIMOUT_LIST + + Consumer: REO + Producer: SW + + The AC_timeout list to be used for this command + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB 33 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK 0x0000000300000000 + + +/* Description RESERVED_1 + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB 34 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK 0xfffffffc00000000 + + +/* Description MINIMUM_RELEASE_DESC_COUNT + + Consumer: REO + Producer: SW + + The minimum number of link descriptors requested to be released. + If set to 0, only buffer release counts seems to be important... + When set to very high value, likely the entire timeout list + will be exhausted before this count is reached or maybe + this count will not get reached. REO however will stop + here as it can not do anything else. + + When both this field and field Minimum_forward_buf_count + are > 0, REO needs to meet both requirements. When both + entries are 0 (which should be a programming error), REO + does not need to do anything. + + Note that this includes counts of MPDU link Desc as well + as MSDU link Desc. Where the count of MSDU link Desc is + not known to REO it's approximated by deriving from MSDU + count + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK 0x000000000000ffff + + +/* Description MINIMUM_FORWARD_BUF_COUNT + + Consumer: REO + Producer: SW + + The minimum number of buffer descriptors requested to be + passed on to the REO destination rings. + + If set to 0, only descriptor release counts seems to be + important... + + When set to very high value, likely the entire timeout list + will be exhausted before this count is reached or maybe + this count will not get reached. REO however will stop + here as it can not do anything else. + + Note that REO does not know the exact buffer count. This + can be approximated by using the MSDU_COUNT + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK 0x00000000ffff0000 + + +/* Description RESERVED_3A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // REO_FLUSH_TIMEOUT_LIST diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_flush_timeout_list_status.h b/drivers/staging/fw-api/hw/qcn6432/reo_flush_timeout_list_status.h new file mode 100644 index 0000000000000000000000000000000000000000..4ee609203eda5cfa31d7e8aa91e9a09f1d0ab54e --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_flush_timeout_list_status.h @@ -0,0 +1,542 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26 + +#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13 + + +struct reo_flush_timeout_list_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, // [0:0] + timout_list_empty : 1, // [1:1] + reserved_2a : 30; // [31:2] + uint32_t release_desc_count : 16, // [15:0] + forward_buf_count : 16; // [31:16] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t reserved_25a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, // [31:2] + timout_list_empty : 1, // [1:1] + error_detected : 1; // [0:0] + uint32_t forward_buf_count : 16, // [31:16] + release_desc_count : 16; // [15:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 28; // [27:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description ERROR_DETECTED + + 0: No error has been detected while executing this command + + 1: command not properly executed and returned with an error + + + NOTE: Current no error is defined, but field is put in place + to avoid data structure changes in future... +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + + +/* Description TIMOUT_LIST_EMPTY + + When set, REO has depleted the timeout list and all entries + are gone. + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x0000000000000002 + + +/* Description RESERVED_2A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0x00000000fffffffc + + +/* Description RELEASE_DESC_COUNT + + Consumer: REO + Producer: SW + + The number of link descriptors released + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 47 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff00000000 + + +/* Description FORWARD_BUF_COUNT + + Consumer: REO + Producer: SW + + The number of buffers forwarded to the REO destination rings + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 48 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff000000000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description RESERVED_10A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + +/* Description RESERVED_11A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + +/* Description RESERVED_12A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + +/* Description RESERVED_13A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + +/* Description RESERVED_14A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + +/* Description RESERVED_15A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + +/* Description RESERVED_16A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + +/* Description RESERVED_17A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + +/* Description RESERVED_18A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + +/* Description RESERVED_19A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + +/* Description RESERVED_20A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + +/* Description RESERVED_21A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + +/* Description RESERVED_22A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + +/* Description RESERVED_23A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + +/* Description RESERVED_25A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 59 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 60 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_FLUSH_TIMEOUT_LIST_STATUS diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_get_queue_stats.h b/drivers/staging/fw-api/hw/qcn6432/reo_get_queue_stats.h new file mode 100644 index 0000000000000000000000000000000000000000..1b226dfff22701e5aefdac6211f424552f123e70 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_get_queue_stats.h @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_GET_QUEUE_STATS_H_ +#define _REO_GET_QUEUE_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 10 + +#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS 5 + + +struct reo_get_queue_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] + clear_stats : 1, // [8:8] + reserved_2a : 23; // [31:9] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t reserved_2a : 23, // [31:9] + clear_stats : 1, // [8:8] + rx_reo_queue_desc_addr_39_32 : 8; // [7:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description CMD_HEADER + + Consumer: REO + Producer: SW + + Details for command execution tracking purposes. +*/ + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + Producer: SW + + Address (lower 32 bits) of the REO queue descriptor + +*/ + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + Producer: SW + + Address (upper 8 bits) of the REO queue descriptor + +*/ + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff + + +/* Description CLEAR_STATS + + Clear stat settings.... + + Do NOT clear the stats after generating + the status + Clear the stats after generating + the status. + + The stats actually cleared are: + Timeout_count + Forward_due_to_bar_count + Duplicate_count + Frames_in_order_count + BAR_received_count + MPDU_Frames_processed_count + MSDU_Frames_processed_count + Total_processed_byte_count + Late_receive_MPDU_count + window_jump_2k + Hole_count + +*/ + +#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x0000000000000100 + + +/* Description RESERVED_2A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0x00000000fffffe00 + + +/* Description RESERVED_3A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 32 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 63 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 32 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 63 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 32 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 63 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define REO_GET_QUEUE_STATS_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_TLV64_PADDING_LSB 32 +#define REO_GET_QUEUE_STATS_TLV64_PADDING_MSB 63 +#define REO_GET_QUEUE_STATS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // REO_GET_QUEUE_STATS diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_get_queue_stats_status.h b/drivers/staging/fw-api/hw/qcn6432/reo_get_queue_stats_status.h new file mode 100644 index 0000000000000000000000000000000000000000..202d4158fd0376c9b794d85a76b4678a7d4ff919 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_get_queue_stats_status.h @@ -0,0 +1,737 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_GET_QUEUE_STATS_STATUS_H_ +#define _REO_GET_QUEUE_STATS_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 26 + +#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS_STATUS 13 + + +struct reo_get_queue_stats_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t ssn : 12, // [11:0] + current_index : 10, // [21:12] + reserved_2 : 10; // [31:22] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t last_rx_enqueue_timestamp : 32; // [31:0] + uint32_t last_rx_dequeue_timestamp : 32; // [31:0] + uint32_t rx_bitmap_31_0 : 32; // [31:0] + uint32_t rx_bitmap_63_32 : 32; // [31:0] + uint32_t rx_bitmap_95_64 : 32; // [31:0] + uint32_t rx_bitmap_127_96 : 32; // [31:0] + uint32_t rx_bitmap_159_128 : 32; // [31:0] + uint32_t rx_bitmap_191_160 : 32; // [31:0] + uint32_t rx_bitmap_223_192 : 32; // [31:0] + uint32_t rx_bitmap_255_224 : 32; // [31:0] + uint32_t rx_bitmap_287_256 : 32; // [31:0] + uint32_t current_mpdu_count : 7, // [6:0] + current_msdu_count : 25; // [31:7] + uint32_t window_jump_2k : 4, // [3:0] + timeout_count : 6, // [9:4] + forward_due_to_bar_count : 6, // [15:10] + duplicate_count : 16; // [31:16] + uint32_t frames_in_order_count : 24, // [23:0] + bar_received_count : 8; // [31:24] + uint32_t mpdu_frames_processed_count : 32; // [31:0] + uint32_t msdu_frames_processed_count : 32; // [31:0] + uint32_t total_processed_byte_count : 32; // [31:0] + uint32_t late_receive_mpdu_count : 12, // [11:0] + hole_count : 16, // [27:12] + get_queue_1k_stats_status_to_follow : 1, // [28:28] + reserved_24a : 3; // [31:29] + uint32_t aging_drop_mpdu_count : 16, // [15:0] + aging_drop_interval : 8, // [23:16] + reserved_25a : 4, // [27:24] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 10, // [31:22] + current_index : 10, // [21:12] + ssn : 12; // [11:0] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t last_rx_enqueue_timestamp : 32; // [31:0] + uint32_t last_rx_dequeue_timestamp : 32; // [31:0] + uint32_t rx_bitmap_31_0 : 32; // [31:0] + uint32_t rx_bitmap_63_32 : 32; // [31:0] + uint32_t rx_bitmap_95_64 : 32; // [31:0] + uint32_t rx_bitmap_127_96 : 32; // [31:0] + uint32_t rx_bitmap_159_128 : 32; // [31:0] + uint32_t rx_bitmap_191_160 : 32; // [31:0] + uint32_t rx_bitmap_223_192 : 32; // [31:0] + uint32_t rx_bitmap_255_224 : 32; // [31:0] + uint32_t rx_bitmap_287_256 : 32; // [31:0] + uint32_t current_msdu_count : 25, // [31:7] + current_mpdu_count : 7; // [6:0] + uint32_t duplicate_count : 16, // [31:16] + forward_due_to_bar_count : 6, // [15:10] + timeout_count : 6, // [9:4] + window_jump_2k : 4; // [3:0] + uint32_t bar_received_count : 8, // [31:24] + frames_in_order_count : 24; // [23:0] + uint32_t mpdu_frames_processed_count : 32; // [31:0] + uint32_t msdu_frames_processed_count : 32; // [31:0] + uint32_t total_processed_byte_count : 32; // [31:0] + uint32_t reserved_24a : 3, // [31:29] + get_queue_1k_stats_status_to_follow : 1, // [28:28] + hole_count : 16, // [27:12] + late_receive_mpdu_count : 12; // [11:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 4, // [27:24] + aging_drop_interval : 8, // [23:16] + aging_drop_mpdu_count : 16; // [15:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description SSN + + Starting Sequence number of the session, this changes whenever + window moves. (can be filled by SW then maintained by REO) + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK 0x0000000000000fff + + +/* Description CURRENT_INDEX + + Points to last forwarded packet + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB 21 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK 0x00000000003ff000 + + +/* Description RESERVED_2 + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB 22 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK 0x00000000ffc00000 + + +/* Description PN_31_0 + + Bits [31:0] of the PN number extracted from the IV field + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK 0xffffffff00000000 + + +/* Description PN_63_32 + + Bits [63:32] of the PN number. + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK 0x00000000ffffffff + + +/* Description PN_95_64 + + Bits [95:64] of the PN number. + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK 0xffffffff00000000 + + +/* Description PN_127_96 + + Bits [127:96] of the PN number. + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK 0x00000000ffffffff + + +/* Description LAST_RX_ENQUEUE_TIMESTAMP + + Timestamp of arrival of the last MPDU for this queue + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description LAST_RX_DEQUEUE_TIMESTAMP + + Timestamp of forwarding an MPDU + + If the queue is empty when a frame gets received, this time + shall be initialized to the 'enqueue' timestamp + + Used for aging + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0x00000000ffffffff + + +/* Description RX_BITMAP_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + The bitmap is Fully managed by HW. + SW shall init this to 0, and then never ever change it + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK 0xffffffff00000000 + + +/* Description RX_BITMAP_63_32 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET 0x0000000000000028 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK 0x00000000ffffffff + + +/* Description RX_BITMAP_95_64 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET 0x0000000000000028 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK 0xffffffff00000000 + + +/* Description RX_BITMAP_127_96 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET 0x0000000000000030 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK 0x00000000ffffffff + + +/* Description RX_BITMAP_159_128 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET 0x0000000000000030 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK 0xffffffff00000000 + + +/* Description RX_BITMAP_191_160 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET 0x0000000000000038 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK 0x00000000ffffffff + + +/* Description RX_BITMAP_223_192 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET 0x0000000000000038 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK 0xffffffff00000000 + + +/* Description RX_BITMAP_255_224 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET 0x0000000000000040 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK 0x00000000ffffffff + + +/* Description RX_BITMAP_287_256 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET 0x0000000000000040 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK 0xffffffff00000000 + + +/* Description CURRENT_MPDU_COUNT + + The number of MPDUs in the queue. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB 6 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK 0x000000000000007f + + +/* Description CURRENT_MSDU_COUNT + + The number of MSDUs in the queue. + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB 7 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK 0x00000000ffffff80 + + +/* Description WINDOW_JUMP_2K + + The number of times the window moved more then 2K + + The counter saturates and freezes at 0xF + + (Note: field name can not start with number: previous 2k_window_jump) + + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB 35 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK 0x0000000f00000000 + + +/* Description TIMEOUT_COUNT + + The number of times that REO started forwarding frames even + though there is a hole in the bitmap. Forwarding reason + is Timeout + + The counter saturates and freezes at 0x3F + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB 36 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB 41 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK 0x000003f000000000 + + +/* Description FORWARD_DUE_TO_BAR_COUNT + + The number of times that REO started forwarding frames even + though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + The counter saturates and freezes at 0x3F + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB 42 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB 47 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc0000000000 + + +/* Description DUPLICATE_COUNT + + The number of duplicate frames that have been detected + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB 48 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK 0xffff000000000000 + + +/* Description FRAMES_IN_ORDER_COUNT + + The number of frames that have been received in order (without + a hole that prevented them from being forwarded immediately) + + + This corresponds to the Reorder opcodes: + 'FWDCUR' and 'FWD BUF' + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000000000000050 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB 23 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK 0x0000000000ffffff + + +/* Description BAR_RECEIVED_COUNT + + The number of times a BAR frame is received. + + This corresponds to the Reorder opcodes with 'DROP' + + The counter saturates and freezes at 0xFF + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET 0x0000000000000050 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK 0x00000000ff000000 + + +/* Description MPDU_FRAMES_PROCESSED_COUNT + + The total number of MPDU frames that have been processed + by REO. This includes the duplicates. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000050 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff00000000 + + +/* Description MSDU_FRAMES_PROCESSED_COUNT + + The total number of MSDU frames that have been processed + by REO. This includes the duplicates. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000058 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK 0x00000000ffffffff + + +/* Description TOTAL_PROCESSED_BYTE_COUNT + + An approximation of the number of bytes received for this + queue. + + In 64 byte units + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000000000000058 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff00000000 + + +/* Description LATE_RECEIVE_MPDU_COUNT + + The number of MPDUs received after the window had already + moved on. The 'late' sequence window is defined as (Window + SSN - 256) - (Window SSN - 1) + + This corresponds with Out of order detection in duplicate + detect FSM + + The counter saturates and freezes at 0xFFF + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK 0x0000000000000fff + + +/* Description HOLE_COUNT + + The number of times a hole was created in the receive bitmap. + + + This corresponds to the Reorder opcodes with 'QCUR' + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK 0x000000000ffff000 + + +/* Description GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW + + Indicates that the queue supports a BA window size above + 256, so a 'REO_GET_QUEUE_STATS_1K_STATUS' status TLV will + immediately follow. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK 0x0000000010000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB 29 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK 0x00000000e0000000 + + +/* Description AGING_DROP_MPDU_COUNT + + The number of holes in the bitmap that moved due to aging + counter expiry + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MSB 47 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff00000000 + + +/* Description AGING_DROP_INTERVAL + + The number of times holes got removed from the bitmap due + to aging counter expiry + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_LSB 48 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MSB 55 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MASK 0x00ff000000000000 + + +/* Description RESERVED_25A + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB 56 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB 59 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK 0x0f00000000000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB 60 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_GET_QUEUE_STATS_STATUS diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_unblock_cache.h b/drivers/staging/fw-api/hw/qcn6432/reo_unblock_cache.h new file mode 100644 index 0000000000000000000000000000000000000000..b966abc208fb9e1257660924ecec72b9d60108e8 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_unblock_cache.h @@ -0,0 +1,262 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_UNBLOCK_CACHE_H_ +#define _REO_UNBLOCK_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 10 + +#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE 5 + + +struct reo_unblock_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t unblock_type : 1, // [0:0] + cache_block_resource_index : 2, // [2:1] + reserved_1a : 29; // [31:3] + uint32_t reserved_2a : 32; // [31:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1a : 29, // [31:3] + cache_block_resource_index : 2, // [2:1] + unblock_type : 1; // [0:0] + uint32_t reserved_2a : 32; // [31:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description CMD_HEADER + + Consumer: REO + Producer: SW + + Details for command execution tracking purposes. +*/ + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + +/* Description UNBLOCK_TYPE + + Unblock type + + Unblock a block resource, + whose index is given in field 'cache_block_resource_index'. + + If the indicated blocking resource is not in use (=> not + blocking an address at the moment), the command status + will indicate an error. + + The entire cache usage is unblocked. + + If the entire cache is not in a blocked mode at the moment + this command is received, the command status will indicate + an error. + Note that unlocking the "entire cache" has no changes to + the current settings of the blocking resource settings + + +*/ + +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 32 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 32 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x0000000100000000 + + +/* Description CACHE_BLOCK_RESOURCE_INDEX + + Field not valid when field Unblock_type is set to unblock_cache. + + + Indicates which of the four blocking resources in REO should + be released from blocking a (descriptor) address. + +*/ + +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 33 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 34 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000600000000 + + +/* Description RESERVED_1A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 35 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff800000000 + + +/* Description RESERVED_2A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0x00000000ffffffff + + +/* Description RESERVED_3A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 32 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 32 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 32 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define REO_UNBLOCK_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_TLV64_PADDING_LSB 32 +#define REO_UNBLOCK_CACHE_TLV64_PADDING_MSB 63 +#define REO_UNBLOCK_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // REO_UNBLOCK_CACHE diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_unblock_cache_status.h b/drivers/staging/fw-api/hw/qcn6432/reo_unblock_cache_status.h new file mode 100644 index 0000000000000000000000000000000000000000..53f97e1cc835966650ce83755e7ff1d51ec09232 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_unblock_cache_status.h @@ -0,0 +1,525 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_UNBLOCK_CACHE_STATUS_H_ +#define _REO_UNBLOCK_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 26 + +#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE_STATUS 13 + + +struct reo_unblock_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, // [0:0] + unblock_type : 1, // [1:1] + reserved_2a : 30; // [31:2] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t reserved_25a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, // [31:2] + unblock_type : 1, // [1:1] + error_detected : 1; // [0:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 28; // [27:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description ERROR_DETECTED + + Status for blocking resource handling + + 0: No error has been detected while executing this command + + 1: The blocking resource was not in use, and therefor it + could not be 'unblocked' +*/ + +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + + +/* Description UNBLOCK_TYPE + + Reference to the type of Unblock command type... + + Unblock a blocking resource + + + The entire cache usage is unblock. + + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x0000000000000002 + + +/* Description RESERVED_2A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0x00000000fffffffc + + +/* Description RESERVED_3A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description RESERVED_10A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + +/* Description RESERVED_11A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + +/* Description RESERVED_12A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + +/* Description RESERVED_13A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + +/* Description RESERVED_14A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + +/* Description RESERVED_15A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + +/* Description RESERVED_16A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + +/* Description RESERVED_17A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + +/* Description RESERVED_18A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + +/* Description RESERVED_19A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + +/* Description RESERVED_20A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + +/* Description RESERVED_21A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + +/* Description RESERVED_22A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + +/* Description RESERVED_23A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + +/* Description RESERVED_25A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 59 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_UNBLOCK_CACHE_STATUS diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_update_rx_reo_queue.h b/drivers/staging/fw-api/hw/qcn6432/reo_update_rx_reo_queue.h new file mode 100644 index 0000000000000000000000000000000000000000..66f2c1793af36ab21801c27c65cd45a13a7a123b --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_update_rx_reo_queue.h @@ -0,0 +1,1056 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_UPDATE_RX_REO_QUEUE_H_ +#define _REO_UPDATE_RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10 + +#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5 + + +struct reo_update_rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] + update_receive_queue_number : 1, // [8:8] + update_vld : 1, // [9:9] + update_associated_link_descriptor_counter : 1, // [10:10] + update_disable_duplicate_detection : 1, // [11:11] + update_soft_reorder_enable : 1, // [12:12] + update_ac : 1, // [13:13] + update_bar : 1, // [14:14] + update_rty : 1, // [15:15] + update_chk_2k_mode : 1, // [16:16] + update_oor_mode : 1, // [17:17] + update_ba_window_size : 1, // [18:18] + update_pn_check_needed : 1, // [19:19] + update_pn_shall_be_even : 1, // [20:20] + update_pn_shall_be_uneven : 1, // [21:21] + update_pn_handling_enable : 1, // [22:22] + update_pn_size : 1, // [23:23] + update_ignore_ampdu_flag : 1, // [24:24] + update_svld : 1, // [25:25] + update_ssn : 1, // [26:26] + update_seq_2k_error_detected_flag : 1, // [27:27] + update_pn_error_detected_flag : 1, // [28:28] + update_pn_valid : 1, // [29:29] + update_pn : 1, // [30:30] + clear_stat_counters : 1; // [31:31] + uint32_t receive_queue_number : 16, // [15:0] + vld : 1, // [16:16] + associated_link_descriptor_counter : 2, // [18:17] + disable_duplicate_detection : 1, // [19:19] + soft_reorder_enable : 1, // [20:20] + ac : 2, // [22:21] + bar : 1, // [23:23] + rty : 1, // [24:24] + chk_2k_mode : 1, // [25:25] + oor_mode : 1, // [26:26] + pn_check_needed : 1, // [27:27] + pn_shall_be_even : 1, // [28:28] + pn_shall_be_uneven : 1, // [29:29] + pn_handling_enable : 1, // [30:30] + ignore_ampdu_flag : 1; // [31:31] + uint32_t ba_window_size : 10, // [9:0] + pn_size : 2, // [11:10] + svld : 1, // [12:12] + ssn : 12, // [24:13] + seq_2k_error_detected_flag : 1, // [25:25] + pn_error_detected_flag : 1, // [26:26] + pn_valid : 1, // [27:27] + flush_from_cache : 1, // [28:28] + reserved_4a : 3; // [31:29] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t clear_stat_counters : 1, // [31:31] + update_pn : 1, // [30:30] + update_pn_valid : 1, // [29:29] + update_pn_error_detected_flag : 1, // [28:28] + update_seq_2k_error_detected_flag : 1, // [27:27] + update_ssn : 1, // [26:26] + update_svld : 1, // [25:25] + update_ignore_ampdu_flag : 1, // [24:24] + update_pn_size : 1, // [23:23] + update_pn_handling_enable : 1, // [22:22] + update_pn_shall_be_uneven : 1, // [21:21] + update_pn_shall_be_even : 1, // [20:20] + update_pn_check_needed : 1, // [19:19] + update_ba_window_size : 1, // [18:18] + update_oor_mode : 1, // [17:17] + update_chk_2k_mode : 1, // [16:16] + update_rty : 1, // [15:15] + update_bar : 1, // [14:14] + update_ac : 1, // [13:13] + update_soft_reorder_enable : 1, // [12:12] + update_disable_duplicate_detection : 1, // [11:11] + update_associated_link_descriptor_counter : 1, // [10:10] + update_vld : 1, // [9:9] + update_receive_queue_number : 1, // [8:8] + rx_reo_queue_desc_addr_39_32 : 8; // [7:0] + uint32_t ignore_ampdu_flag : 1, // [31:31] + pn_handling_enable : 1, // [30:30] + pn_shall_be_uneven : 1, // [29:29] + pn_shall_be_even : 1, // [28:28] + pn_check_needed : 1, // [27:27] + oor_mode : 1, // [26:26] + chk_2k_mode : 1, // [25:25] + rty : 1, // [24:24] + bar : 1, // [23:23] + ac : 2, // [22:21] + soft_reorder_enable : 1, // [20:20] + disable_duplicate_detection : 1, // [19:19] + associated_link_descriptor_counter : 2, // [18:17] + vld : 1, // [16:16] + receive_queue_number : 16; // [15:0] + uint32_t reserved_4a : 3, // [31:29] + flush_from_cache : 1, // [28:28] + pn_valid : 1, // [27:27] + pn_error_detected_flag : 1, // [26:26] + seq_2k_error_detected_flag : 1, // [25:25] + ssn : 12, // [24:13] + svld : 1, // [12:12] + pn_size : 2, // [11:10] + ba_window_size : 10; // [9:0] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description CMD_HEADER + + Consumer: REO + Producer: SW + + Details for command execution tracking purposes. +*/ + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + Producer: SW + + Address (lower 32 bits) of the REO queue descriptor + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + Producer: SW + + Address (upper 8 bits) of the REO queue descriptor + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff + + +/* Description UPDATE_RECEIVE_QUEUE_NUMBER + + Consumer: REO + Producer: SW + When set, receive_queue_number from this command will be + updated in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000000100 + + +/* Description UPDATE_VLD + + Consumer: REO + Producer: SW + + When clear, REO will NOT update the VLD bit setting. For + this setting, SW MUST set the Flush_from_cache bit in this + command. + + When set, VLD from this command will be updated in the descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x0000000000000200 + + +/* Description UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER + + Consumer: REO + Producer: SW + When set, Associated_link_descriptor_counter from this command + will be updated in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0000000000000400 + + +/* Description UPDATE_DISABLE_DUPLICATE_DETECTION + + Consumer: REO + Producer: SW + When set, Disable_duplicate_detection from this command + will be updated in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x0000000000000800 + + +/* Description UPDATE_SOFT_REORDER_ENABLE + + Consumer: REO + Producer: SW + When set, Soft_reorder_enable from this command will be + updated in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x0000000000001000 + + +/* Description UPDATE_AC + + Consumer: REO + Producer: SW + When set, AC from this command will be updated in the descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x0000000000002000 + + +/* Description UPDATE_BAR + + Consumer: REO + Producer: SW + When set, BAR from this command will be updated in the descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x0000000000004000 + + +/* Description UPDATE_RTY + + Consumer: REO + Producer: SW + When set, RTY from this command will be updated in the descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x0000000000008000 + + +/* Description UPDATE_CHK_2K_MODE + + Consumer: REO + Producer: SW + When set, Chk_2k_mode from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x0000000000010000 + + +/* Description UPDATE_OOR_MODE + + Consumer: REO + Producer: SW + When set, OOR_Mode from this command will be updated in + the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x0000000000020000 + + +/* Description UPDATE_BA_WINDOW_SIZE + + Consumer: REO + Producer: SW + When set, BA_window_size from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x0000000000040000 + + +/* Description UPDATE_PN_CHECK_NEEDED + + Consumer: REO + Producer: SW + When set, Pn_check_needed from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x0000000000080000 + + +/* Description UPDATE_PN_SHALL_BE_EVEN + + Consumer: REO + Producer: SW + When set, Pn_shall_be_even from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x0000000000100000 + + +/* Description UPDATE_PN_SHALL_BE_UNEVEN + + Consumer: REO + Producer: SW + When set, Pn_shall_be_uneven from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x0000000000200000 + + +/* Description UPDATE_PN_HANDLING_ENABLE + + Consumer: REO + Producer: SW + When set, Pn_handling_enable from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x0000000000400000 + + +/* Description UPDATE_PN_SIZE + + Consumer: REO + Producer: SW + When set, Pn_size from this command will be updated in the + descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x0000000000800000 + + +/* Description UPDATE_IGNORE_AMPDU_FLAG + + Consumer: REO + Producer: SW + When set, Ignore_ampdu_flag from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x0000000001000000 + + +/* Description UPDATE_SVLD + + Consumer: REO + Producer: SW + When set, Svld from this command will be updated in the + descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x0000000002000000 + + +/* Description UPDATE_SSN + + Consumer: REO + Producer: SW + When set, SSN from this command will be updated in the descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x0000000004000000 + + +/* Description UPDATE_SEQ_2K_ERROR_DETECTED_FLAG + + Consumer: REO + Producer: SW + When set, Seq_2k_error_detected_flag from this command will + be updated in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000008000000 + + +/* Description UPDATE_PN_ERROR_DETECTED_FLAG + + Consumer: REO + Producer: SW + When set, pn_error_detected_flag from this command will + be updated in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000010000000 + + +/* Description UPDATE_PN_VALID + + Consumer: REO + Producer: SW + When set, pn_valid from this command will be updated in + the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x0000000020000000 + + +/* Description UPDATE_PN + + Consumer: REO + Producer: SW + When set, all pn_... fields from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x0000000040000000 + + +/* Description CLEAR_STAT_COUNTERS + + Consumer: REO + Producer: SW + When set, REO will clear (=> set to 0) the following stat + counters in the REO_QUEUE_STRUCT + + Last_rx_enqueue_TimeStamp + Last_rx_dequeue_Timestamp + Rx_bitmap (not a counter, but bitmap is cleared) + Timeout_count + Forward_due_to_bar_count + Duplicate_count + Frames_in_order_count + BAR_received_count + MPDU_Frames_processed_count + MSDU_Frames_processed_count + Total_processed_byte_count + Late_receive_MPDU_count + window_jump_2k + Hole_count + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x0000000080000000 + + +/* Description RECEIVE_QUEUE_NUMBER + + Field only valid when Update_receive_queue_number is set + + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 47 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff00000000 + + +/* Description VLD + + Field only valid when Update_VLD is set + + For Update_VLD set and VLD clear, SW MUST set the Flush_from_cache + bit in this command. + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 48 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 48 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x0001000000000000 + + +/* Description ASSOCIATED_LINK_DESCRIPTOR_COUNTER + + Field only valid when Update_Associated_link_descriptor_counter + is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 49 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 50 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0006000000000000 + + +/* Description DISABLE_DUPLICATE_DETECTION + + Field only valid when Update_Disable_duplicate_detection + is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 51 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 51 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x0008000000000000 + + +/* Description SOFT_REORDER_ENABLE + + Field only valid when Update_Soft_reorder_enable is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 52 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 52 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x0010000000000000 + + +/* Description AC + + Field only valid when Update_AC is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_AC_LSB 53 +#define REO_UPDATE_RX_REO_QUEUE_AC_MSB 54 +#define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x0060000000000000 + + +/* Description BAR + + Field only valid when Update_BAR is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 55 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 55 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x0080000000000000 + + +/* Description RTY + + Field only valid when Update_RTY is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 56 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 56 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x0100000000000000 + + +/* Description CHK_2K_MODE + + Field only valid when Update_Chk_2k_Mode is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 57 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 57 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x0200000000000000 + + +/* Description OOR_MODE + + Field only valid when Update_OOR_Mode is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 58 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 58 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x0400000000000000 + + +/* Description PN_CHECK_NEEDED + + Field only valid when Update_Pn_check_needed is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 59 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 59 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x0800000000000000 + + +/* Description PN_SHALL_BE_EVEN + + Field only valid when Update_Pn_shall_be_even is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 60 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 60 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x1000000000000000 + + +/* Description PN_SHALL_BE_UNEVEN + + Field only valid when Update_Pn_shall_be_uneven is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 61 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 61 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x2000000000000000 + + +/* Description PN_HANDLING_ENABLE + + Field only valid when Update_Pn_handling_enable is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 62 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 62 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x4000000000000000 + + +/* Description IGNORE_AMPDU_FLAG + + Field only valid when Update_Ignore_ampdu_flag is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 63 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x8000000000000000 + + +/* Description BA_WINDOW_SIZE + + Field only valid when Update_BA_window_size is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x00000000000003ff + + +/* Description PN_SIZE + + Field only valid when Update_Pn_size is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + + + + + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x0000000000000c00 + + +/* Description SVLD + + Field only valid when Update_Svld is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x0000000000001000 + + +/* Description SSN + + Field only valid when Update_SSN is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x0000000001ffe000 + + +/* Description SEQ_2K_ERROR_DETECTED_FLAG + + Field only valid when Update_Seq_2k_error_detected_flag + is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000002000000 + + +/* Description PN_ERROR_DETECTED_FLAG + + Field only valid when Update_pn_error_detected_flag is set + + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000004000000 + + +/* Description PN_VALID + + Field only valid when Update_pn_valid is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x0000000008000000 + + +/* Description FLUSH_FROM_CACHE + + When set, REO shall, after finishing the execution of this + command, flush the related descriptor from the cache. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x0000000010000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0x00000000e0000000 + + +/* Description PN_31_0 + + Field only valid when Update_Pn is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff00000000 + + +/* Description PN_63_32 + + Field only valid when Update_pn is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0x00000000ffffffff + + +/* Description PN_95_64 + + Field only valid when Update_pn is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff00000000 + + +/* Description PN_127_96 + + Field only valid when Update_pn is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // REO_UPDATE_RX_REO_QUEUE diff --git a/drivers/staging/fw-api/hw/qcn6432/reo_update_rx_reo_queue_status.h b/drivers/staging/fw-api/hw/qcn6432/reo_update_rx_reo_queue_status.h new file mode 100644 index 0000000000000000000000000000000000000000..57dbb82173a52e2019a1516dace3e52db8476528 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/reo_update_rx_reo_queue_status.h @@ -0,0 +1,486 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 26 + +#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 13 + + +struct reo_update_rx_reo_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; // [31:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t reserved_25a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; // [31:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 28; // [27:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description RESERVED_2A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000ffffffff + + +/* Description RESERVED_3A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description RESERVED_10A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + +/* Description RESERVED_11A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + +/* Description RESERVED_12A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + +/* Description RESERVED_13A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + +/* Description RESERVED_14A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + +/* Description RESERVED_15A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + +/* Description RESERVED_16A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + +/* Description RESERVED_17A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + +/* Description RESERVED_18A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + +/* Description RESERVED_19A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + +/* Description RESERVED_20A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + +/* Description RESERVED_21A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + +/* Description RESERVED_22A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + +/* Description RESERVED_23A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + +/* Description RESERVED_25A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 59 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_UPDATE_RX_REO_QUEUE_STATUS diff --git a/drivers/staging/fw-api/hw/qcn6432/response_end_status.h b/drivers/staging/fw-api/hw/qcn6432/response_end_status.h new file mode 100644 index 0000000000000000000000000000000000000000..ebf79d40e9e20f70da46328b16eecac83c98d04e --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/response_end_status.h @@ -0,0 +1,1203 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RESPONSE_END_STATUS_H_ +#define _RESPONSE_END_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_RESPONSE_END_STATUS 22 + +#define NUM_OF_QWORDS_RESPONSE_END_STATUS 11 + + +struct response_end_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t coex_bt_tx_while_wlan_tx : 1, // [0:0] + coex_wan_tx_while_wlan_tx : 1, // [1:1] + coex_wlan_tx_while_wlan_tx : 1, // [2:2] + global_data_underflow_warning : 1, // [3:3] + response_transmit_status : 4, // [7:4] + phytx_pkt_end_info_valid : 1, // [8:8] + phytx_abort_request_info_valid : 1, // [9:9] + generated_response : 3, // [12:10] + mba_user_count : 7, // [19:13] + mba_fake_bitmap_count : 7, // [26:20] + coex_based_tx_bw : 3, // [29:27] + trig_response_related : 1, // [30:30] + dpdtrain_done : 1; // [31:31] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t cbf_segment_request_mask : 8, // [23:16] + cbf_segment_sent_mask : 8; // [31:24] + uint32_t underflow_mpdu_count : 9, // [8:0] + data_underflow_warning : 2, // [10:9] + phy_tx_gain_setting : 8, // [18:11] + timing_status : 2, // [20:19] + only_null_delim_sent : 1, // [21:21] + brp_info_valid : 1, // [22:22] + reserved_2a : 9; // [31:23] + uint32_t mu_response_bitmap_31_0 : 32; // [31:0] + uint32_t mu_response_bitmap_36_32 : 5, // [4:0] + reserved_4a : 11, // [15:5] + transmit_delay : 16; // [31:16] + uint32_t start_of_frame_timestamp_15_0 : 16, // [15:0] + start_of_frame_timestamp_31_16 : 16; // [31:16] + uint32_t end_of_frame_timestamp_15_0 : 16, // [15:0] + end_of_frame_timestamp_31_16 : 16; // [31:16] + uint32_t tx_group_delay : 12, // [11:0] + reserved_7a : 4, // [15:12] + tpc_dbg_info_cmn_15_0 : 16; // [31:16] + uint32_t tpc_dbg_info_31_16 : 16, // [15:0] + tpc_dbg_info_47_32 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_15_0 : 16, // [15:0] + tpc_dbg_info_chn1_31_16 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_47_32 : 16, // [15:0] + tpc_dbg_info_chn1_63_48 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_79_64 : 16, // [15:0] + tpc_dbg_info_chn2_15_0 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_31_16 : 16, // [15:0] + tpc_dbg_info_chn2_47_32 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_63_48 : 16, // [15:0] + tpc_dbg_info_chn2_79_64 : 16; // [31:16] + uint32_t phytx_tx_end_sw_info_15_0 : 16, // [15:0] + phytx_tx_end_sw_info_31_16 : 16; // [31:16] + uint32_t phytx_tx_end_sw_info_47_32 : 16, // [15:0] + phytx_tx_end_sw_info_63_48 : 16; // [31:16] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr1_47_32 : 16, // [15:0] + addr2_15_0 : 16; // [31:16] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t addr3_31_0 : 32; // [31:0] + uint32_t addr3_47_32 : 16, // [15:0] + ranging : 1, // [16:16] + secure : 1, // [17:17] + ranging_ftm_frame_sent : 1, // [18:18] + reserved_20a : 13; // [31:19] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t dpdtrain_done : 1, // [31:31] + trig_response_related : 1, // [30:30] + coex_based_tx_bw : 3, // [29:27] + mba_fake_bitmap_count : 7, // [26:20] + mba_user_count : 7, // [19:13] + generated_response : 3, // [12:10] + phytx_abort_request_info_valid : 1, // [9:9] + phytx_pkt_end_info_valid : 1, // [8:8] + response_transmit_status : 4, // [7:4] + global_data_underflow_warning : 1, // [3:3] + coex_wlan_tx_while_wlan_tx : 1, // [2:2] + coex_wan_tx_while_wlan_tx : 1, // [1:1] + coex_bt_tx_while_wlan_tx : 1; // [0:0] + uint32_t cbf_segment_sent_mask : 8, // [31:24] + cbf_segment_request_mask : 8; // [23:16] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t reserved_2a : 9, // [31:23] + brp_info_valid : 1, // [22:22] + only_null_delim_sent : 1, // [21:21] + timing_status : 2, // [20:19] + phy_tx_gain_setting : 8, // [18:11] + data_underflow_warning : 2, // [10:9] + underflow_mpdu_count : 9; // [8:0] + uint32_t mu_response_bitmap_31_0 : 32; // [31:0] + uint32_t transmit_delay : 16, // [31:16] + reserved_4a : 11, // [15:5] + mu_response_bitmap_36_32 : 5; // [4:0] + uint32_t start_of_frame_timestamp_31_16 : 16, // [31:16] + start_of_frame_timestamp_15_0 : 16; // [15:0] + uint32_t end_of_frame_timestamp_31_16 : 16, // [31:16] + end_of_frame_timestamp_15_0 : 16; // [15:0] + uint32_t tpc_dbg_info_cmn_15_0 : 16, // [31:16] + reserved_7a : 4, // [15:12] + tx_group_delay : 12; // [11:0] + uint32_t tpc_dbg_info_47_32 : 16, // [31:16] + tpc_dbg_info_31_16 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_31_16 : 16, // [31:16] + tpc_dbg_info_chn1_15_0 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_63_48 : 16, // [31:16] + tpc_dbg_info_chn1_47_32 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_15_0 : 16, // [31:16] + tpc_dbg_info_chn1_79_64 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_47_32 : 16, // [31:16] + tpc_dbg_info_chn2_31_16 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_79_64 : 16, // [31:16] + tpc_dbg_info_chn2_63_48 : 16; // [15:0] + uint32_t phytx_tx_end_sw_info_31_16 : 16, // [31:16] + phytx_tx_end_sw_info_15_0 : 16; // [15:0] + uint32_t phytx_tx_end_sw_info_63_48 : 16, // [31:16] + phytx_tx_end_sw_info_47_32 : 16; // [15:0] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr2_15_0 : 16, // [31:16] + addr1_47_32 : 16; // [15:0] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t addr3_31_0 : 32; // [31:0] + uint32_t reserved_20a : 13, // [31:19] + ranging_ftm_frame_sent : 1, // [18:18] + secure : 1, // [17:17] + ranging : 1, // [16:16] + addr3_47_32 : 16; // [15:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description COEX_BT_TX_WHILE_WLAN_TX + + When set, a BT tx coex event started while wlan was in the + middle of response transmission. + + Field set when coex_status_broadcast TLV received with bt + tx activity set and WLAN tx ongoing. + +*/ + +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 + + +/* Description COEX_WAN_TX_WHILE_WLAN_TX + + When set, a WAN tx coex event started while wlan was in + the middle of response transmission. + + Field set when coex_status_broadcast TLV received with WAN + tx activity set and WLAN tx ongoing + +*/ + +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000002 + + +/* Description COEX_WLAN_TX_WHILE_WLAN_TX + + When set, a WLAN tx coex event started while wlan was in + the middle of response transmission. + + Field set when coex_status_broadcast TLV received with WLAN + tx activity set and WLAN tx ongoing + +*/ + +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 + + +/* Description GLOBAL_DATA_UNDERFLOW_WARNING + + Consumer: SCH/SW + Producer: TXPCU + + When set, during response transmission a data underflow + occurred for one or more users. +*/ + +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 + + +/* Description RESPONSE_TRANSMIT_STATUS + + Successful transmission of the selfgen + response frame + Set if transmission is + terminated because of the coex soft abort. + Set if transmission is terminated + because PHY generated an abort request + Set if transmission is + terminated because RXPCU received a flush request + Set if transmission is terminated + because of other errors within the RXPCU + +*/ + +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 + + +/* Description PHYTX_PKT_END_INFO_VALID + + All the fields originating from PHYTX_PKT_END TLV contain + valid info + + Note that when "trig_response_related" is set, this bit + will often not be set as the trigger response contents might + have come from a scheduling command which is not reported + as part of the 'response' transmission. +*/ + +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 + + +/* Description PHYTX_ABORT_REQUEST_INFO_VALID + + Field Phytx_abort_request_info_details contains valid info + +*/ + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 + + +/* Description GENERATED_RESPONSE + + The generated response frame + + TXPCU generated an ACK response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated an CTS response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated a BA response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated an M BA response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated a CBF response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + + TXPCU generated a trigger related response of a type not + specified above. Note that in this case bit trig_response_related + will be set as well. + This e-num will also be used when TXPCU has been programmed + to overwrite it's own self gen response generation, and + wait for the response to come from SCH.. + Also applicable for basic trigger response. + + TXPCU generated a self-gen NDP + followed by a self-gen LMR for the ranging NDPA followed + by NDP received by RXPCU. + + +*/ + +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 + + +/* Description MBA_USER_COUNT + + Field only valid in case of selfgen_MBA + + The number of users included in the generated MBA + + Note that this value will be the same as in TLV/field: RESPONSE_START_STATUS.response_STA_count + + + +*/ + +#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 + + +/* Description MBA_FAKE_BITMAP_COUNT + + Field only valid in case of MU OFDMA selfgen_MBA + + The number of users for which RXPCU did not have a bitmap, + and thus provided a 'fake bitmap' + +*/ + +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 + + +/* Description COEX_BASED_TX_BW + + This is the transmit bandwidth value + that is granted by Coex for the response frame + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 + + +/* Description TRIG_RESPONSE_RELATED + + When set, this TLV is generated by TXPCU in the context + of a response transmission to a received trigger frame. + + +*/ + +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 + + +/* Description DPDTRAIN_DONE + + Field only valid when PHYTX_PKT_END_info_valid is set + + For DPD Training packets, this bit is set to indicate that + DPD Training was successfully run to completion. Also + reused by Implicit BF Calibration Packets. This bit is intended + for debug purposes. + +*/ + +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_LSB 31 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_MSB 31 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_MASK 0x0000000080000000 + + +/* Description PHYTX_ABORT_REQUEST_INFO_DETAILS + + Field only valid when PHYTX_ABORT_REQUEST_info_valid is + set + + The reason why PHYTX is requested an abort +*/ + + +/* Description PHYTX_ABORT_REASON + + Reason for early termination of TX packet by the PHY + + +*/ + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + + +/* Description USER_NUMBER + + For some errors, the user for which this error was detected + can be indicated in this field. + +*/ + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + + +/* Description RESERVED + + +*/ + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + + +/* Description CBF_SEGMENT_REQUEST_MASK + + Field only valid when brp_info_valid is set. + + Field equal to the 'Feedback Segment Retransmission Bitmap' + from the Beamform Report Poll frame OR Beamform Report Poll + Trigger frame + + Bit 0 represents segment 0 + Bit 1 represents segment 1 + Etc. + + 1'b1: Segment is requested + 1'b0: Segment is NOT requested + + +*/ + +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 + + +/* Description CBF_SEGMENT_SENT_MASK + + Field only valid when brp_info_valid is set. + + Bit 0 represents segment 0 + Bit 1 represents segment 1 + Etc. + + 1'b1: Segment is sent + 1'b0: Segment is not sent + + +*/ + +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 + + +/* Description UNDERFLOW_MPDU_COUNT + + The MPDU count transmitted when the first underrun condition + was detected + +*/ + +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff + + +/* Description DATA_UNDERFLOW_WARNING + + Mac data underflow warning + + No data underflow + PCU experienced data + underflow in between MPDUs + PCU experienced data + underflow within an MPDU + +*/ + +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 + + +/* Description PHY_TX_GAIN_SETTING + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + The gain setting that the PHY used for this last PPDU transmission + +*/ + +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_LSB 11 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MSB 18 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MASK 0x000000000007f800 + + +/* Description TIMING_STATUS + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + The MAC did not request for + the transmission to start at a particular time + MAC did request for transmission + to start at a particular time and PHY was able to do so. + + PHY was not able to honour + the requested transmit time by the MAC. The transmission + started later, and field transmit_delay indicates how much + later. + +*/ + +#define RESPONSE_END_STATUS_TIMING_STATUS_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_TIMING_STATUS_LSB 19 +#define RESPONSE_END_STATUS_TIMING_STATUS_MSB 20 +#define RESPONSE_END_STATUS_TIMING_STATUS_MASK 0x0000000000180000 + + +/* Description ONLY_NULL_DELIM_SENT + + Field only valid when "trig_response_related" is set. + + When set, TXPCU only sent NULL delimiters to the PHY for + the entire duration of the trigger response time. + + Note that SCH does not evaluate this field. It is only for + SW to look at. + + Setting this bit can only happen when a trigger is received, + and either the trigger allocated an incorrectly small duration, + or SW had not programmed a response scheduler command in + time to respond, which may not comply with the 11ax IEEE + spec. + + +*/ + +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 + + +/* Description BRP_INFO_VALID + + When set, TXPCU sent CBF segments. + + Fields cbf_segment_request_mask and cbf_segment_sent_mask + contain valid info. + + +*/ + +#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 + + +/* Description RESERVED_2A + + +*/ + +#define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_RESERVED_2A_LSB 23 +#define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_2A_MASK 0x00000000ff800000 + + +/* Description MU_RESPONSE_BITMAP_31_0 + + Bit 0 represents user 0 + Bit 1 represents user 1 + ... + When set, at least 1 MPDU from this user has been properly + received => FCS OK + + TODO: remove these + Field can not be filled in with the self generated response + +*/ + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 + + +/* Description MU_RESPONSE_BITMAP_36_32 + + Bit 0 represents user 32 + Bit 1 represents user 33 + ... + When set, at least 1 MPDU from this user has been properly + received => FCS OK + TODO: remove these + Field can not be filled in with the self generated response + + Note: Received_response already goes to SW, so probably + no need to copy this bitmap info to TX_FES_STATUS TLV. +*/ + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f + + +/* Description RESERVED_4A + + +*/ + +#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 +#define RESPONSE_END_STATUS_RESERVED_4A_MSB 15 +#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x000000000000ffe0 + + +/* Description TRANSMIT_DELAY + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + The number of 480 MHz clock cycles that the transmission + started after the actual requested transmit start time. + + Value saturates at 0xFFFF + +*/ + +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_LSB 16 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_MSB 31 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + + +/* Description START_OF_FRAME_TIMESTAMP_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 15:0 of a 64 bit time stamp + Start of frame in the medium @960 MHz + +*/ + +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + + +/* Description START_OF_FRAME_TIMESTAMP_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 31:16 of a 64 bit time stamp + Start of frame in the medium @960 MHz + +*/ + +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + + +/* Description END_OF_FRAME_TIMESTAMP_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 15:0 of a 64 bit time stamp + End of frame in the medium @960 MHz + +*/ + +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + + +/* Description END_OF_FRAME_TIMESTAMP_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 31:16 of a 64 bit time stamp + End of frame in the medium @960 MHz + +*/ + +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + + +/* Description TX_GROUP_DELAY + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Group delay on TxTD+PHYRF path for this PPDU (packet BW + dependent), useful for RTT + + Unit is 960MHz cycles. + +*/ + +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_LSB 32 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_MSB 43 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_MASK 0x00000fff00000000 + + +/* Description RESERVED_7A + + +*/ + +#define RESPONSE_END_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_RESERVED_7A_LSB 44 +#define RESPONSE_END_STATUS_RESERVED_7A_MSB 47 +#define RESPONSE_END_STATUS_RESERVED_7A_MASK 0x0000f00000000000 + + +/* Description TPC_DBG_INFO_CMN_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug infothat PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN1_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN1_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CHN1_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN1_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN1_79_64 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN2_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CHN2_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN2_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN2_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN2_79_64 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 + + +/* Description PHYTX_TX_END_SW_INFO_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + + +/* Description PHYTX_TX_END_SW_INFO_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + + +/* Description PHYTX_TX_END_SW_INFO_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + + +/* Description PHYTX_TX_END_SW_INFO_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + + +/* Description ADDR1_31_0 + + To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO + +*/ + +#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 +#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0x00000000ffffffff + + +/* Description ADDR1_47_32 + + To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO + +*/ + +#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 32 +#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 47 +#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff00000000 + + +/* Description ADDR2_15_0 + + To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO + +*/ + +#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 48 +#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 63 +#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff000000000000 + + +/* Description ADDR2_47_16 + + To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO + +*/ + +#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000048 +#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 +#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 +#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0x00000000ffffffff + + +/* Description ADDR3_31_0 + + To be copied over from TX_CBF_INFO +*/ + +#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000048 +#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 32 +#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 63 +#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff00000000 + + +/* Description ADDR3_47_32 + + To be copied over from TX_CBF_INFO +*/ + +#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 +#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 +#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x000000000000ffff + + +/* Description RANGING + + To be copied over from TX_CBF_INFO: Set to 1 if the status + is generated due to an active ranging session (.11az) +*/ + +#define RESPONSE_END_STATUS_RANGING_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_RANGING_LSB 16 +#define RESPONSE_END_STATUS_RANGING_MSB 16 +#define RESPONSE_END_STATUS_RANGING_MASK 0x0000000000010000 + + +/* Description SECURE + + To be copied over from TX_CBF_INFO: Only valid if Ranging + is set to 1, this indicates if the current ranging session + is secure. +*/ + +#define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_SECURE_LSB 17 +#define RESPONSE_END_STATUS_SECURE_MSB 17 +#define RESPONSE_END_STATUS_SECURE_MASK 0x0000000000020000 + + +/* Description RANGING_FTM_FRAME_SENT + + Only valid if Ranging is set to 1 + + TXPCU sets this bit if an FTM frame aggregated with an LMR + was sent. +*/ + +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x0000000000040000 + + +/* Description RESERVED_20A + + +*/ + +#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 +#define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0x00000000fff80000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RESPONSE_END_STATUS_TLV64_PADDING_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_TLV64_PADDING_LSB 32 +#define RESPONSE_END_STATUS_TLV64_PADDING_MSB 63 +#define RESPONSE_END_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RESPONSE_END_STATUS diff --git a/drivers/staging/fw-api/hw/qcn6432/response_start_status.h b/drivers/staging/fw-api/hw/qcn6432/response_start_status.h new file mode 100644 index 0000000000000000000000000000000000000000..1959c5fabf725f34ee44cafa5ad30b967bee6594 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/response_start_status.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RESPONSE_START_STATUS_H_ +#define _RESPONSE_START_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 + +#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 + + +struct response_start_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t generated_response : 3, // [2:0] + ftm_tm : 2, // [4:3] + trig_response_related : 1, // [5:5] + response_sta_count : 7, // [12:6] + reserved : 19; // [31:13] + uint32_t phy_ppdu_id : 16, // [15:0] + sw_peer_id : 16; // [31:16] +#else + uint32_t reserved : 19, // [31:13] + response_sta_count : 7, // [12:6] + trig_response_related : 1, // [5:5] + ftm_tm : 2, // [4:3] + generated_response : 3; // [2:0] + uint32_t sw_peer_id : 16, // [31:16] + phy_ppdu_id : 16; // [15:0] +#endif +}; + + +/* Description GENERATED_RESPONSE + + The generated response frame + + TXPCU generated an ACK response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated an CTS response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated a BA response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated an M BA response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated a CBF response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + + TXPCU generated a trigger related response of a type not + specified above. Note that in this case bit trig_response_related + will be set as well. + + This e-num will also be used when TXPCU has been programmed + to overwrite it's own self gen response generation, and + wait for the response to come from SCH.. + Also applicable for basic trigger response. + + TXPCU generated a self-gen NDP + followed by a self-gen LMR for the ranging NDPA followed + by NDP received by RXPCU. + + +*/ + +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 + + +/* Description FTM_TM + + This field Indicates if the response is related to receiving + a TM or FTM frame + + 0: no TM and no FTM frame => there is NO measurement done + + 1: FTM frame + 2: TM frame + 3: reserved +*/ + +#define RESPONSE_START_STATUS_FTM_TM_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_FTM_TM_LSB 3 +#define RESPONSE_START_STATUS_FTM_TM_MSB 4 +#define RESPONSE_START_STATUS_FTM_TM_MASK 0x0000000000000018 + + +/* Description TRIG_RESPONSE_RELATED + + When set, this TLV is generated by TXPCU in the context + of a response transmission to a received trigger frame. + + +*/ + +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 + + +/* Description RESPONSE_STA_COUNT + + The number of STAs to which the responses need to be sent. + + + In case of multiple ACKs/BAs to be send, TXPCU uses this + field to determine what address formatting to use for the + response frame: This could be broadcast or unicast. + + +*/ + +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 + + +/* Description RESERVED + + +*/ + +#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_RESERVED_LSB 13 +#define RESPONSE_START_STATUS_RESERVED_MSB 31 +#define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffffe000 + + +/* Description PHY_PPDU_ID + + The PHY_PPDU_ID of the received PPDU for which this response + is generated. +*/ + +#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 + + +/* Description SW_PEER_ID + + This field is only valid when Response_STA_count is set + to 1 + + An identifier indicating for which device this response + is needed. + +*/ + +#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 +#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 +#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 + + + +#endif // RESPONSE_START_STATUS diff --git a/drivers/staging/fw-api/hw/qcn6432/ru_allocation_160_info.h b/drivers/staging/fw-api/hw/qcn6432/ru_allocation_160_info.h new file mode 100644 index 0000000000000000000000000000000000000000..72d9ea9e629aaaeaf165b392fab2ee6c2b2f79b2 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/ru_allocation_160_info.h @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RU_ALLOCATION_160_INFO_H_ +#define _RU_ALLOCATION_160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 + + +struct ru_allocation_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation_band0_0 : 9, // [8:0] + ru_allocation_band0_1 : 9, // [17:9] + reserved_0a : 6, // [23:18] + ru_allocations_01_subband80_mask : 4, // [27:24] + ru_allocations_23_subband80_mask : 4; // [31:28] + uint32_t ru_allocation_band0_2 : 9, // [8:0] + ru_allocation_band0_3 : 9, // [17:9] + reserved_1a : 14; // [31:18] + uint32_t ru_allocation_band1_0 : 9, // [8:0] + ru_allocation_band1_1 : 9, // [17:9] + reserved_2a : 14; // [31:18] + uint32_t ru_allocation_band1_2 : 9, // [8:0] + ru_allocation_band1_3 : 9, // [17:9] + reserved_3a : 14; // [31:18] +#else + uint32_t ru_allocations_23_subband80_mask : 4, // [31:28] + ru_allocations_01_subband80_mask : 4, // [27:24] + reserved_0a : 6, // [23:18] + ru_allocation_band0_1 : 9, // [17:9] + ru_allocation_band0_0 : 9; // [8:0] + uint32_t reserved_1a : 14, // [31:18] + ru_allocation_band0_3 : 9, // [17:9] + ru_allocation_band0_2 : 9; // [8:0] + uint32_t reserved_2a : 14, // [31:18] + ru_allocation_band1_1 : 9, // [17:9] + ru_allocation_band1_0 : 9; // [8:0] + uint32_t reserved_3a : 14, // [31:18] + ru_allocation_band1_3 : 9, // [17:9] + ru_allocation_band1_2 : 9; // [8:0] +#endif +}; + + +/* Description RU_ALLOCATION_BAND0_0 + + Field not used for MIMO + + Indicates RU arrangement in frequency domain. RU allocated + for MU-MIMO, and number of users in the MU-MIMO. + 0 - valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 + 1 - valid for HE_80/HE_160 (80+80)/ EHT_80/EHT_160/EHT_240/EHT_320 + + 2 - valid for HE_160 (80+80)/ EHT_160/EHT_240/EHT_320 + 3 - valid for HE_160 (80+80)/ EHT_160/EHT_240/EHT_320 + + The four bands are for HE_SIGB0 & B1 respectively or for + EHT_SIG0, EHT_SIG1, EHT_SIG2 & EHT_SIG3 respectively. + + valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 packets and denotes RU-map of the first + 20MHz band of HE_SIGB0 or EHT_SIG0 + +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + + +/* Description RU_ALLOCATION_BAND0_1 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_80/HE_160/ EHT_80/EHT_160/EHT_240/EHT_320 packets + and denotes RU-map of the second 20MHz band of HE_SIGB0 + or EHT_SIG0 +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + + +/* Description RESERVED_0A + + +*/ + +#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 + + +/* Description RU_ALLOCATIONS_01_SUBBAND80_MASK + + Field not used for HE + + Indicates what 80 MHz subbands 'ru_allocation_band{0, 1}_{0, + 1}' are valid for + Bit 0: lowest 80 MHz + Bit 1: 2nd lowest 80 MHz + Bit 2: 2nd highest 80 MHz + Bit 3: highest 80 MHz + + In other 80 MHz subbands PHY microcode should override these + with 'zero-user RU996.' + +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + + +/* Description RU_ALLOCATIONS_23_SUBBAND80_MASK + + Field not used for HE + + Indicates what 80 MHz subbands 'ru_allocation_band{0, 1}_{2, + 3}' are valid for + Bit 0: lowest 80 MHz + Bit 1: 2nd lowest 80 MHz + Bit 2: 2nd highest 80 MHz + Bit 3: highest 80 MHz + + In other 80 MHz subbands PHY microcode should override these + with 'zero-user RU996.' + +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + + +/* Description RU_ALLOCATION_BAND0_2 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the third 20MHz band of HE_SIGB0 or EHT_SIG0 +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + + +/* Description RU_ALLOCATION_BAND0_3 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the fourth 20MHz band of HE_SIGB0 or EHT_SIG0 + +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + + +/* Description RESERVED_1A + + +*/ + +#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 + + +/* Description RU_ALLOCATION_BAND1_0 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_40/HE_80/HE_160/ EHT_40/EHT_80/EHT_160/ EHT_240/EHT_320 + packets and denotes RU-map of the first 20MHz band of HE_SIGB1 + or EHT_SIG1 +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + + +/* Description RU_ALLOCATION_BAND1_1 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_80/HE_160/ EHT_80/EHT_160/EHT_240/EHT_320 packets + and denotes RU-map of the second 20MHz band of HE_SIGB1 + or EHT_SIG1 +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + + +/* Description RESERVED_2A + + +*/ + +#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 + + +/* Description RU_ALLOCATION_BAND1_2 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the third 20MHz band of HE_SIGB1 or EHT_SIG1 +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + + +/* Description RU_ALLOCATION_BAND1_3 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the fourth 20MHz band of HE_SIGB1 or EHT_SIG1 + +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + + +/* Description RESERVED_3A + + +*/ + +#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 + + + +#endif // RU_ALLOCATION_160_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_attention.h b/drivers/staging/fw-api/hw/qcn6432/rx_attention.h new file mode 100644 index 0000000000000000000000000000000000000000..6bf0a1188d1e40a86514f2dc4636191301f80f89 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_attention.h @@ -0,0 +1,873 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_ATTENTION_H_ +#define _RX_ATTENTION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_ATTENTION 4 + +#define NUM_OF_QWORDS_RX_ATTENTION 2 + + +struct rx_attention { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] + sw_frame_group_id : 7, // [8:2] + reserved_0 : 7, // [15:9] + phy_ppdu_id : 16; // [31:16] + uint32_t first_mpdu : 1, // [0:0] + reserved_1a : 1, // [1:1] + mcast_bcast : 1, // [2:2] + ast_index_not_found : 1, // [3:3] + ast_index_timeout : 1, // [4:4] + power_mgmt : 1, // [5:5] + non_qos : 1, // [6:6] + null_data : 1, // [7:7] + mgmt_type : 1, // [8:8] + ctrl_type : 1, // [9:9] + more_data : 1, // [10:10] + eosp : 1, // [11:11] + a_msdu_error : 1, // [12:12] + fragment_flag : 1, // [13:13] + order : 1, // [14:14] + cce_match : 1, // [15:15] + overflow_err : 1, // [16:16] + msdu_length_err : 1, // [17:17] + tcp_udp_chksum_fail : 1, // [18:18] + ip_chksum_fail : 1, // [19:19] + sa_idx_invalid : 1, // [20:20] + da_idx_invalid : 1, // [21:21] + reserved_1b : 1, // [22:22] + rx_in_tx_decrypt_byp : 1, // [23:23] + encrypt_required : 1, // [24:24] + directed : 1, // [25:25] + buffer_fragment : 1, // [26:26] + mpdu_length_err : 1, // [27:27] + tkip_mic_err : 1, // [28:28] + decrypt_err : 1, // [29:29] + unencrypted_frame_err : 1, // [30:30] + fcs_err : 1; // [31:31] + uint32_t flow_idx_timeout : 1, // [0:0] + flow_idx_invalid : 1, // [1:1] + wifi_parser_error : 1, // [2:2] + amsdu_parser_error : 1, // [3:3] + sa_idx_timeout : 1, // [4:4] + da_idx_timeout : 1, // [5:5] + msdu_limit_error : 1, // [6:6] + da_is_valid : 1, // [7:7] + da_is_mcbc : 1, // [8:8] + sa_is_valid : 1, // [9:9] + decrypt_status_code : 3, // [12:10] + rx_bitmap_not_updated : 1, // [13:13] + reserved_2 : 17, // [30:14] + msdu_done : 1; // [31:31] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t phy_ppdu_id : 16, // [31:16] + reserved_0 : 7, // [15:9] + sw_frame_group_id : 7, // [8:2] + rxpcu_mpdu_filter_in_category : 2; // [1:0] + uint32_t fcs_err : 1, // [31:31] + unencrypted_frame_err : 1, // [30:30] + decrypt_err : 1, // [29:29] + tkip_mic_err : 1, // [28:28] + mpdu_length_err : 1, // [27:27] + buffer_fragment : 1, // [26:26] + directed : 1, // [25:25] + encrypt_required : 1, // [24:24] + rx_in_tx_decrypt_byp : 1, // [23:23] + reserved_1b : 1, // [22:22] + da_idx_invalid : 1, // [21:21] + sa_idx_invalid : 1, // [20:20] + ip_chksum_fail : 1, // [19:19] + tcp_udp_chksum_fail : 1, // [18:18] + msdu_length_err : 1, // [17:17] + overflow_err : 1, // [16:16] + cce_match : 1, // [15:15] + order : 1, // [14:14] + fragment_flag : 1, // [13:13] + a_msdu_error : 1, // [12:12] + eosp : 1, // [11:11] + more_data : 1, // [10:10] + ctrl_type : 1, // [9:9] + mgmt_type : 1, // [8:8] + null_data : 1, // [7:7] + non_qos : 1, // [6:6] + power_mgmt : 1, // [5:5] + ast_index_timeout : 1, // [4:4] + ast_index_not_found : 1, // [3:3] + mcast_bcast : 1, // [2:2] + reserved_1a : 1, // [1:1] + first_mpdu : 1; // [0:0] + uint32_t msdu_done : 1, // [31:31] + reserved_2 : 17, // [30:14] + rx_bitmap_not_updated : 1, // [13:13] + decrypt_status_code : 3, // [12:10] + sa_is_valid : 1, // [9:9] + da_is_mcbc : 1, // [8:8] + da_is_valid : 1, // [7:7] + msdu_limit_error : 1, // [6:6] + da_idx_timeout : 1, // [5:5] + sa_idx_timeout : 1, // [4:4] + amsdu_parser_error : 1, // [3:3] + wifi_parser_error : 1, // [2:2] + flow_idx_invalid : 1, // [1:1] + flow_idx_timeout : 1; // [0:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + This MPDU passed the normal frame + filter programming of rxpcu + This MPDU did NOT pass the + regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + This MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + +*/ + +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + +/* Description SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. This + field indicates to what sw classification this MPDU is + mapped. + The classification is given in priority order + + + + + + This includes mpdus of + type Data Null. + This includes QoS + Null frames except in UL MU or TB PPDUs. + This includes + QoS Null frames in UL MU or TB PPDUs. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + PHY reported an error + + + +*/ + +#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + +/* Description RESERVED_0 + + +*/ + +#define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RESERVED_0_LSB 9 +#define RX_ATTENTION_RESERVED_0_MSB 15 +#define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_PHY_PPDU_ID_LSB 16 +#define RX_ATTENTION_PHY_PPDU_ID_MSB 31 +#define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description FIRST_MPDU + + Indicates the first MSDU of the PPDU. If both first_mpdu + and last_mpdu are set in the MSDU then this is a not an + A-MPDU frame but a stand alone MPDU. Interior MPDU in + an A-MPDU shall have both first_mpdu and last_mpdu bits + set to 0. The PPDU start status will only be valid when + this bit is set. +*/ + +#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 +#define RX_ATTENTION_FIRST_MPDU_LSB 32 +#define RX_ATTENTION_FIRST_MPDU_MSB 32 +#define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 + + +/* Description RESERVED_1A + + +*/ + +#define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RESERVED_1A_LSB 33 +#define RX_ATTENTION_RESERVED_1A_MSB 33 +#define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 + + +/* Description MCAST_BCAST + + Multicast / broadcast indicator. Only set when the MAC + address 1 bit 0 is set indicating mcast/bcast and the BSSID + matches one of the 4 BSSID registers. Only set when first_msdu + is set. +*/ + +#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MCAST_BCAST_LSB 34 +#define RX_ATTENTION_MCAST_BCAST_MSB 34 +#define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 + + +/* Description AST_INDEX_NOT_FOUND + + Only valid when first_msdu is set. + + Indicates no AST matching entries within the the max search + count. +*/ + +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 + + +/* Description AST_INDEX_TIMEOUT + + Only valid when first_msdu is set. + + Indicates an unsuccessful search in the address seach table + due to timeout. +*/ + +#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 + + +/* Description POWER_MGMT + + Power management bit set in the 802.11 header. Only set + when first_msdu is set. +*/ + +#define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 +#define RX_ATTENTION_POWER_MGMT_LSB 37 +#define RX_ATTENTION_POWER_MGMT_MSB 37 +#define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 + + +/* Description NON_QOS + + Set if packet is not a non-QoS data frame. Only set when + first_msdu is set. +*/ + +#define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 +#define RX_ATTENTION_NON_QOS_LSB 38 +#define RX_ATTENTION_NON_QOS_MSB 38 +#define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 + + +/* Description NULL_DATA + + Set if frame type indicates either null data or QoS null + data format. Only set when first_msdu is set. +*/ + +#define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 +#define RX_ATTENTION_NULL_DATA_LSB 39 +#define RX_ATTENTION_NULL_DATA_MSB 39 +#define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 + + +/* Description MGMT_TYPE + + Set if packet is a management packet. Only set when first_msdu + is set. +*/ + +#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MGMT_TYPE_LSB 40 +#define RX_ATTENTION_MGMT_TYPE_MSB 40 +#define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 + + +/* Description CTRL_TYPE + + Set if packet is a control packet. Only set when first_msdu + is set. +*/ + +#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 +#define RX_ATTENTION_CTRL_TYPE_LSB 41 +#define RX_ATTENTION_CTRL_TYPE_MSB 41 +#define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 + + +/* Description MORE_DATA + + Set if more bit in frame control is set. Only set when + first_msdu is set. +*/ + +#define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MORE_DATA_LSB 42 +#define RX_ATTENTION_MORE_DATA_MSB 42 +#define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 + + +/* Description EOSP + + Set if the EOSP (end of service period) bit in the QoS control + field is set. Only set when first_msdu is set. +*/ + +#define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 +#define RX_ATTENTION_EOSP_LSB 43 +#define RX_ATTENTION_EOSP_MSB 43 +#define RX_ATTENTION_EOSP_MASK 0x0000080000000000 + + +/* Description A_MSDU_ERROR + + Set if number of MSDUs in A-MSDU is above a threshold or + if the size of the MSDU is invalid. This receive buffer + will contain all of the remainder of the MSDUs in this + MPDU without decapsulation. +*/ + +#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_A_MSDU_ERROR_LSB 44 +#define RX_ATTENTION_A_MSDU_ERROR_MSB 44 +#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 + + +/* Description FRAGMENT_FLAG + + Indicates that this is an 802.11 fragment frame. This is + set when either the more_frag bit is set in the frame control + or the fragment number is not zero. Only set when first_msdu + is set. +*/ + +#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 +#define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 +#define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 +#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 + + +/* Description ORDER + + Set if the order bit in the frame control is set. Only + set when first_msdu is set. +*/ + +#define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 +#define RX_ATTENTION_ORDER_LSB 46 +#define RX_ATTENTION_ORDER_MSB 46 +#define RX_ATTENTION_ORDER_MASK 0x0000400000000000 + + +/* Description CCE_MATCH + + Indicates that this status has a corresponding MSDU that + requires FW processing. The OLE will have classification + ring mask registers which will indicate the ring(s) for + packets and descriptors which need FW attention. +*/ + +#define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 +#define RX_ATTENTION_CCE_MATCH_LSB 47 +#define RX_ATTENTION_CCE_MATCH_MSB 47 +#define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 + + +/* Description OVERFLOW_ERR + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + This MPDU will not be ACKed. + RXPCU might still be able to correctly receive the following + MPDUs in the PPDU if enough fifo space became available + in time +*/ + +#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_OVERFLOW_ERR_LSB 48 +#define RX_ATTENTION_OVERFLOW_ERR_MSB 48 +#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 + + +/* Description MSDU_LENGTH_ERR + + Indicates that the MSDU length from the 802.3 encapsulated + length field extends beyond the MPDU boundary or if the + length is less than 14 bytes. + Merged with original "other_msdu_err": Indicates that the + MSDU threshold was exceeded and thus all the rest of the + MSDUs will not be scattered and will not be decasulated + but will be DMA'ed in RAW format as a single MSDU buffer + +*/ + +#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Indicates that the computed checksum (tcp_udp_chksum in 'RX_MSDU_END') + did not match the checksum in the TCP/UDP header. +*/ + +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 + + +/* Description IP_CHKSUM_FAIL + + Indicates that the computed checksum (ip_hdr_chksum in 'RX_MSDU_END') + did not match the checksum in the IP header. +*/ + +#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 +#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 + + +/* Description SA_IDX_INVALID + + Indicates no matching entry was found in the address search + table for the source MAC address. +*/ + +#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_SA_IDX_INVALID_LSB 52 +#define RX_ATTENTION_SA_IDX_INVALID_MSB 52 +#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 + + +/* Description DA_IDX_INVALID + + Indicates no matching entry was found in the address search + table for the destination MAC address. +*/ + +#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_DA_IDX_INVALID_LSB 53 +#define RX_ATTENTION_DA_IDX_INVALID_MSB 53 +#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RESERVED_1B_LSB 54 +#define RX_ATTENTION_RESERVED_1B_MSB 54 +#define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 + + +/* Description RX_IN_TX_DECRYPT_BYP + + Indicates that RX packet is not decrypted as Crypto is busy + with TX packet processing. +*/ + +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 + + +/* Description ENCRYPT_REQUIRED + + Indicates that this data type frame is not encrypted even + if the policy for this MPDU requires encryption as indicated + in the peer entry key type. +*/ + +#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 +#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 + + +/* Description DIRECTED + + MPDU is a directed packet which means that the RA matched + our STA addresses. In proxySTA it means that the TA matched + an entry in our address search table with the corresponding + "no_ack" bit is the address search entry cleared. +*/ + +#define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 +#define RX_ATTENTION_DIRECTED_LSB 57 +#define RX_ATTENTION_DIRECTED_MSB 57 +#define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 + + +/* Description BUFFER_FRAGMENT + + Indicates that at least one of the rx buffers has been fragmented. + If set the FW should look at the rx_frag_info descriptor + described below. +*/ + +#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 +#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 +#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 +#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 + + +/* Description MPDU_LENGTH_ERR + + Indicates that the MPDU was pre-maturely terminated resulting + in a truncated MPDU. Don't trust the MPDU length field. + +*/ + +#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 + + +/* Description TKIP_MIC_ERR + + Indicates that the MPDU Michael integrity check failed +*/ + +#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 +#define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 +#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 + + +/* Description DECRYPT_ERR + + Indicates that the MPDU decrypt integrity check failed or + CRYPTO received an encrypted frame, but did not get a valid + corresponding key id in the peer entry. +*/ + +#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_DECRYPT_ERR_LSB 61 +#define RX_ATTENTION_DECRYPT_ERR_MSB 61 +#define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 + + +/* Description UNENCRYPTED_FRAME_ERR + + Copied here by RX OLE from the RX_MPDU_END TLV +*/ + +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 + + +/* Description FCS_ERR + + Indicates that the MPDU FCS check failed +*/ + +#define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_FCS_ERR_LSB 63 +#define RX_ATTENTION_FCS_ERR_MSB 63 +#define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 + + +/* Description FLOW_IDX_TIMEOUT + + Indicates an unsuccessful flow search due to the expiring + of the search timer. + +*/ + +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 + + +/* Description FLOW_IDX_INVALID + + flow id is not valid + +*/ + +#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 +#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 + + +/* Description WIFI_PARSER_ERROR + + Indicates that the WiFi frame has one of the following errors + + o has less than minimum allowed bytes as per standard + o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) + +*/ + +#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 +#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 + + +/* Description AMSDU_PARSER_ERROR + + A-MSDU could not be properly de-agregated. + +*/ + +#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 + + +/* Description SA_IDX_TIMEOUT + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. +*/ + +#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 +#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 + + +/* Description DA_IDX_TIMEOUT + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. +*/ + +#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 + + +/* Description MSDU_LIMIT_ERROR + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will + not be decasulated but will be DMA'ed in RAW format as + a single MSDU buffer +*/ + +#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 + + +/* Description DA_IS_VALID + + Indicates that OLE found a valid DA entry +*/ + +#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DA_IS_VALID_LSB 7 +#define RX_ATTENTION_DA_IS_VALID_MSB 7 +#define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address. + +*/ + +#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DA_IS_MCBC_LSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 + + +/* Description SA_IS_VALID + + Indicates that OLE found a valid SA entry +*/ + +#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 +#define RX_ATTENTION_SA_IS_VALID_LSB 9 +#define RX_ATTENTION_SA_IS_VALID_MSB 9 +#define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 + + +/* Description DECRYPT_STATUS_CODE + + Field provides insight into the decryption performed + + Frame had protection enabled and decrypted + properly + Frame is unprotected + and hence bypassed + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + Frame has protection enabled + but the key that was required to decrypt this frame was + not valid + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + Reserved for other indications + + +*/ + +#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 + + +/* Description RX_BITMAP_NOT_UPDATED + + Frame is received, but RXPCU could not update the receive + bitmap due to (temporary) fifo contraints. + +*/ + +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 + + +/* Description RESERVED_2 + + +*/ + +#define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 +#define RX_ATTENTION_RESERVED_2_LSB 14 +#define RX_ATTENTION_RESERVED_2_MSB 30 +#define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 + + +/* Description MSDU_DONE + + If set indicates that the RX packet data, RX header data, + RX PPDU start descriptor, RX MPDU start/end descriptor, + RX MSDU start/end descriptors and RX Attention descriptor + are all valid. This bit must be in the last octet of the + descriptor. +*/ + +#define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 +#define RX_ATTENTION_MSDU_DONE_LSB 31 +#define RX_ATTENTION_MSDU_DONE_MSB 31 +#define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 +#define RX_ATTENTION_TLV64_PADDING_LSB 32 +#define RX_ATTENTION_TLV64_PADDING_MSB 63 +#define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_ATTENTION diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/qcn6432/rx_flow_search_entry.h new file mode 100644 index 0000000000000000000000000000000000000000..4dd89018e3d5c19b0fa0163e25a02856cd875bc1 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_flow_search_entry.h @@ -0,0 +1,571 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_FLOW_SEARCH_ENTRY_H_ +#define _RX_FLOW_SEARCH_ENTRY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 + + +struct rx_flow_search_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_ip_127_96 : 32; // [31:0] + uint32_t src_ip_95_64 : 32; // [31:0] + uint32_t src_ip_63_32 : 32; // [31:0] + uint32_t src_ip_31_0 : 32; // [31:0] + uint32_t dest_ip_127_96 : 32; // [31:0] + uint32_t dest_ip_95_64 : 32; // [31:0] + uint32_t dest_ip_63_32 : 32; // [31:0] + uint32_t dest_ip_31_0 : 32; // [31:0] + uint32_t src_port : 16, // [15:0] + dest_port : 16; // [31:16] + uint32_t l4_protocol : 8, // [7:0] + valid : 1, // [8:8] + reserved_9 : 4, // [12:9] + service_code : 9, // [21:13] + priority_valid : 1, // [22:22] + use_ppe : 1, // [23:23] + reo_destination_indication : 5, // [28:24] + msdu_drop : 1, // [29:29] + reo_destination_handler : 2; // [31:30] + uint32_t metadata : 32; // [31:0] + uint32_t aggregation_count : 7, // [6:0] + lro_eligible : 1, // [7:7] + msdu_count : 24; // [31:8] + uint32_t msdu_byte_count : 32; // [31:0] + uint32_t timestamp : 32; // [31:0] + uint32_t cumulative_ip_length_pmac1 : 16, // [15:0] + cumulative_ip_length : 16; // [31:16] + uint32_t tcp_sequence_number : 32; // [31:0] +#else + uint32_t src_ip_127_96 : 32; // [31:0] + uint32_t src_ip_95_64 : 32; // [31:0] + uint32_t src_ip_63_32 : 32; // [31:0] + uint32_t src_ip_31_0 : 32; // [31:0] + uint32_t dest_ip_127_96 : 32; // [31:0] + uint32_t dest_ip_95_64 : 32; // [31:0] + uint32_t dest_ip_63_32 : 32; // [31:0] + uint32_t dest_ip_31_0 : 32; // [31:0] + uint32_t dest_port : 16, // [31:16] + src_port : 16; // [15:0] + uint32_t reo_destination_handler : 2, // [31:30] + msdu_drop : 1, // [29:29] + reo_destination_indication : 5, // [28:24] + use_ppe : 1, // [23:23] + priority_valid : 1, // [22:22] + service_code : 9, // [21:13] + reserved_9 : 4, // [12:9] + valid : 1, // [8:8] + l4_protocol : 8; // [7:0] + uint32_t metadata : 32; // [31:0] + uint32_t msdu_count : 24, // [31:8] + lro_eligible : 1, // [7:7] + aggregation_count : 7; // [6:0] + uint32_t msdu_byte_count : 32; // [31:0] + uint32_t timestamp : 32; // [31:0] + uint32_t cumulative_ip_length : 16, // [31:16] + cumulative_ip_length_pmac1 : 16; // [15:0] + uint32_t tcp_sequence_number : 32; // [31:0] +#endif +}; + + +/* Description SRC_IP_127_96 + + Uppermost 32 bits of source IPv6 address or prefix as per + Common Parser register field IP_DA_SA_PREFIX (with the + first byte in the MSB and the last byte in the LSB, i.e. + requiring a byte-swap for little-endian SW w.r.t. the byte + order in an IPv6 packet) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff + + +/* Description SRC_IP_95_64 + + Next 32 bits of source IPv6 address or prefix (requiring + a byte-swap for little-endian SW) +*/ + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff + + +/* Description SRC_IP_63_32 + + Next 32 bits of source IPv6 address or lowest 32 bits of + prefix (requiring a byte-swap for little-endian SW) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff + + +/* Description SRC_IP_31_0 + + Lowest 32 bits of source IPv6 address, or source IPv4 address + (requiring a byte-swap for little-endian SW w.r.t. the + byte order in an IPv6 or IPv4 packet) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff + + +/* Description DEST_IP_127_96 + + Uppermost 32 bits of destination IPv6 address or prefix + as per Common Parser register field IP_DA_SA_PREFIX (with + the first byte in the MSB and the last byte in the LSB, + i.e. requiring a byte-swap for little-endian SW w.r.t. the + byte order as in an IPv6 packet) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff + + +/* Description DEST_IP_95_64 + + Next 32 bits of destination IPv6 address or prefix (requiring + a byte-swap for little-endian SW) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff + + +/* Description DEST_IP_63_32 + + Next 32 bits of destination IPv6 address or lowest 32 bits + of prefix (requiring a byte-swap for little-endian SW) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff + + +/* Description DEST_IP_31_0 + + Lowest 32 bits of destination IPv6 address, or destination + IPv4 address (requiring a byte-swap for little-endian SW + w.r.t. the byte order in an IPv6 or IPv4 packet) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff + + +/* Description SRC_PORT + + LSB of SPI in case of ESP/AH + else source port in case of TCP/UDP without IPsec, + else zeros in case of ICMP (with the first/third byte in + the MSB and the second/fourth byte in the LSB, i.e. requiring + a byte-swap for little-endian SW w.r.t. the byte order + as in an IPv6 or IPv4 packet) +*/ + +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff + + +/* Description DEST_PORT + + MSB of SPI in case of ESP/AH + else destination port in case of TCP/UDP without IPsec, + else zeros in case of ICMP (with the first byte in the MSB + and the second byte in the LSB, i.e. requiring a byte-swap + for little-endian SW w.r.t. the byte order as in an IPv6 + or IPv4 packet) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 + + +/* Description L4_PROTOCOL + + IPsec or L4 protocol + + + + + + + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff + + +/* Description VALID + + Indicates validity of entry + +*/ + +#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 + + +/* Description RESERVED_9 + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 + + +/* Description USE_PPE + + Indicates to RXDMA to ignore the REO_destination_indication + and use a programmed value corresponding to the REO2PPE + ring + + This override to REO2PPE for packets requiring multiple + buffers shall be disabled based on an RXDMA configuration, + as PPE may not support such packets. + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 + + +/* Description REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 + + +/* Description MSDU_DROP + + Overriding indication to REO to forward to REO release ring + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 + + +/* Description REO_DESTINATION_HANDLER + + Indicates how to decide the REO destination indication + Follow this entry + Use address search+peer table entry + + Follow this entry + Use CCE super-rule + +*/ + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 + + +/* Description METADATA + + Value to be passed to SW if this flow search entry matches + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 +#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff + + +/* Description AGGREGATION_COUNT + + FISA: Number'of MSDU's aggregated so far + + Based on an RXOLE register, this can be changed to reflect + aggregation of MSDUs from PMAC0 only. + + Set to zero in chips not supporting FISA + +*/ + +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f + + +/* Description LRO_ELIGIBLE + + FISA: + To indicate whether the previous MSDU for this flow is eligible + for LRO/FISA + + Based on an RXOLE register, this can be changed to reflect + the LRO/FISA eligibility for MSDUs from PMAC0 only. + + This bit is also known as RDI_invalid. + When RXOLE is configured to enable flow search (but ignore + the REO_destination_indication) for the first fragment, + it will set this bit if a flow entry matches. + Subsequently when RXOLE matches this flow entry for any + other packet, the REO_destination_indication in this entry + is considered invalid and w.r.t. REO routing the flow search + is considered to have failed. + +*/ + +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 + + +/* Description MSDU_COUNT + + Number of Rx MSDUs matching this flow + + Based on an RXOLE register, this can be changed to reflect + the number of Rx MSDUs from PMAC0 matching the flow. + +*/ + +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 + + +/* Description MSDU_BYTE_COUNT + + Number of bytes in Rx MSDUs matching this flow + + Based on an RXOLE register, this can be changed to reflect + the number of Rx MSDUs from PMAC1 matching the flow. + + Based on an RXOLE register, the MSB 8 bits can be changed + to reflect the 'aggregation_count' and 'LRO_eligible' of + MSDUs from PMAC1. + +*/ + +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff + + +/* Description TIMESTAMP + + Time of last reception (as measured at Rx OLE) matching + this flow + +*/ + +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff + + +/* Description CUMULATIVE_IP_LENGTH_PMAC1 + + Based on an RXOLE register, this can be changed to reflect + the 'cumulative_IP_length' for MSDUs from PMAC1. + +*/ + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff + + +/* Description CUMULATIVE_IP_LENGTH + + FISA: Total MSDU length that is part of this flow aggregated + so far + + Based on an RXOLE register, this can be changed to reflect + aggregation of MSDUs from PMAC0 only. + + Set to zero in chips not supporting FISA + +*/ + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + + +/* Description TCP_SEQUENCE_NUMBER + + FISA: TCP Sequence number of the last packet in this flow + to detect sequence number jump + + Based on an RXOLE register, this can be changed so that + the bottom half of this field reflects the LSBs of the TCP + sequence number of the last packet from PMAC0 and the top + half reflects the LSBs of the TCP sequence number of the + last packet from PMAC1. + + Set to zero in chips not supporting FISA + +*/ + +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff + + + +#endif // RX_FLOW_SEARCH_ENTRY diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_frame_1k_bitmap_ack.h b/drivers/staging/fw-api/hw/qcn6432/rx_frame_1k_bitmap_ack.h new file mode 100644 index 0000000000000000000000000000000000000000..a56ad866754779f0a0664a95326c899dd349bb84 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_frame_1k_bitmap_ack.h @@ -0,0 +1,630 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ +#define _RX_FRAME_1K_BITMAP_ACK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 + +#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 + + +struct rx_frame_1k_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 5, // [4:0] + ba_bitmap_size : 2, // [6:5] + reserved_0b : 3, // [9:7] + ba_tid : 4, // [13:10] + sta_full_aid : 13, // [26:14] + reserved_0c : 5; // [31:27] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr1_47_32 : 16, // [15:0] + addr2_15_0 : 16; // [31:16] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t ba_ts_ctrl : 16, // [15:0] + ba_ts_seq : 16; // [31:16] + uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] + uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] + uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] + uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] + uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] + uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] + uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] + uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] + uint32_t ba_ts_bitmap_287_256 : 32; // [31:0] + uint32_t ba_ts_bitmap_319_288 : 32; // [31:0] + uint32_t ba_ts_bitmap_351_320 : 32; // [31:0] + uint32_t ba_ts_bitmap_383_352 : 32; // [31:0] + uint32_t ba_ts_bitmap_415_384 : 32; // [31:0] + uint32_t ba_ts_bitmap_447_416 : 32; // [31:0] + uint32_t ba_ts_bitmap_479_448 : 32; // [31:0] + uint32_t ba_ts_bitmap_511_480 : 32; // [31:0] + uint32_t ba_ts_bitmap_543_512 : 32; // [31:0] + uint32_t ba_ts_bitmap_575_544 : 32; // [31:0] + uint32_t ba_ts_bitmap_607_576 : 32; // [31:0] + uint32_t ba_ts_bitmap_639_608 : 32; // [31:0] + uint32_t ba_ts_bitmap_671_640 : 32; // [31:0] + uint32_t ba_ts_bitmap_703_672 : 32; // [31:0] + uint32_t ba_ts_bitmap_735_704 : 32; // [31:0] + uint32_t ba_ts_bitmap_767_736 : 32; // [31:0] + uint32_t ba_ts_bitmap_799_768 : 32; // [31:0] + uint32_t ba_ts_bitmap_831_800 : 32; // [31:0] + uint32_t ba_ts_bitmap_863_832 : 32; // [31:0] + uint32_t ba_ts_bitmap_895_864 : 32; // [31:0] + uint32_t ba_ts_bitmap_927_896 : 32; // [31:0] + uint32_t ba_ts_bitmap_959_928 : 32; // [31:0] + uint32_t ba_ts_bitmap_991_960 : 32; // [31:0] + uint32_t ba_ts_bitmap_1023_992 : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0c : 5, // [31:27] + sta_full_aid : 13, // [26:14] + ba_tid : 4, // [13:10] + reserved_0b : 3, // [9:7] + ba_bitmap_size : 2, // [6:5] + reserved_0a : 5; // [4:0] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr2_15_0 : 16, // [31:16] + addr1_47_32 : 16; // [15:0] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t ba_ts_seq : 16, // [31:16] + ba_ts_ctrl : 16; // [15:0] + uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] + uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] + uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] + uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] + uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] + uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] + uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] + uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] + uint32_t ba_ts_bitmap_287_256 : 32; // [31:0] + uint32_t ba_ts_bitmap_319_288 : 32; // [31:0] + uint32_t ba_ts_bitmap_351_320 : 32; // [31:0] + uint32_t ba_ts_bitmap_383_352 : 32; // [31:0] + uint32_t ba_ts_bitmap_415_384 : 32; // [31:0] + uint32_t ba_ts_bitmap_447_416 : 32; // [31:0] + uint32_t ba_ts_bitmap_479_448 : 32; // [31:0] + uint32_t ba_ts_bitmap_511_480 : 32; // [31:0] + uint32_t ba_ts_bitmap_543_512 : 32; // [31:0] + uint32_t ba_ts_bitmap_575_544 : 32; // [31:0] + uint32_t ba_ts_bitmap_607_576 : 32; // [31:0] + uint32_t ba_ts_bitmap_639_608 : 32; // [31:0] + uint32_t ba_ts_bitmap_671_640 : 32; // [31:0] + uint32_t ba_ts_bitmap_703_672 : 32; // [31:0] + uint32_t ba_ts_bitmap_735_704 : 32; // [31:0] + uint32_t ba_ts_bitmap_767_736 : 32; // [31:0] + uint32_t ba_ts_bitmap_799_768 : 32; // [31:0] + uint32_t ba_ts_bitmap_831_800 : 32; // [31:0] + uint32_t ba_ts_bitmap_863_832 : 32; // [31:0] + uint32_t ba_ts_bitmap_895_864 : 32; // [31:0] + uint32_t ba_ts_bitmap_927_896 : 32; // [31:0] + uint32_t ba_ts_bitmap_959_928 : 32; // [31:0] + uint32_t ba_ts_bitmap_991_960 : 32; // [31:0] + uint32_t ba_ts_bitmap_1023_992 : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description RESERVED_0A + + +*/ + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f + + +/* Description BA_BITMAP_SIZE + + Bitmap size set to window of 512 + + Bitmap size set to window of 1024 + + + +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 + + +/* Description RESERVED_0B + + +*/ + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000380 + + +/* Description BA_TID + + The tid for the BA +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 + + +/* Description STA_FULL_AID + + The full AID of this station. +*/ + +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 + + +/* Description RESERVED_0C + + +*/ + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 + + +/* Description ADDR1_31_0 + + lower 32 bits of addr1 of the received frame +*/ + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 + + +/* Description ADDR1_47_32 + + upper 16 bits of addr1 of the received frame +*/ + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff + + +/* Description ADDR2_15_0 + + lower 16 bits of addr2 of the received frame +*/ + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 + + +/* Description ADDR2_47_16 + + upper 32 bits of addr2 of the received frame +*/ + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 + + +/* Description BA_TS_CTRL + + Transmit BA control + RXPCU assumes the C-BA format, NOT M-BA format. + In case TXPCU is responding with M-BA, TXPCU will ignore + this field. TXPCU will generate it +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff + + +/* Description BA_TS_SEQ + + Transmit BA sequence number. +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 + + +/* Description BA_TS_BITMAP_31_0 + + Transmit BA bitmap[31:0] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_63_32 + + Transmit BA bitmap[63:32] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_95_64 + + Transmit BA bitmap[95:64] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_127_96 + + Transmit BA bitmap[127:96] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_159_128 + + Transmit BA bitmap[159:128] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_191_160 + + Transmit BA bitmap[191:160] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_223_192 + + Transmit BA bitmap[223:192] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_255_224 + + Transmit BA bitmap[255:224] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_287_256 + + Transmit BA bitmap[287:256] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000030 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_319_288 + + Transmit BA bitmap[319:288] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_351_320 + + Transmit BA bitmap[351:320] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000038 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_383_352 + + Transmit BA bitmap[383:352] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_415_384 + + Transmit BA bitmap[415:384] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000040 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_447_416 + + Transmit BA bitmap[447:416] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_479_448 + + Transmit BA bitmap[479:448] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000048 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_511_480 + + Transmit BA bitmap[511:480] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_543_512 + + Transmit BA bitmap[543:512] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000050 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_575_544 + + Transmit BA bitmap[575:544] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_607_576 + + Transmit BA bitmap[607:576] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000058 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_639_608 + + Transmit BA bitmap[639:608] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_671_640 + + Transmit BA bitmap[671:640] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000060 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_703_672 + + Transmit BA bitmap[703:672] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_735_704 + + Transmit BA bitmap[735:704] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000068 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_767_736 + + Transmit BA bitmap[767:736] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_799_768 + + Transmit BA bitmap[799:768] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000070 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_831_800 + + Transmit BA bitmap[831:800] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_863_832 + + Transmit BA bitmap[863:832] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000078 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_895_864 + + Transmit BA bitmap[895:864] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_927_896 + + Transmit BA bitmap[927:896] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000080 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_959_928 + + Transmit BA bitmap[959:928] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_991_960 + + Transmit BA bitmap[991:960] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000088 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_1023_992 + + Transmit BA bitmap[1023:992] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000090 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_FRAME_1K_BITMAP_ACK diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_frame_bitmap_ack.h b/drivers/staging/fw-api/hw/qcn6432/rx_frame_bitmap_ack.h new file mode 100644 index 0000000000000000000000000000000000000000..9c61fdb08d0fdb09b546ced3170cbfd7798cfede --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_frame_bitmap_ack.h @@ -0,0 +1,397 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_FRAME_BITMAP_ACK_H_ +#define _RX_FRAME_BITMAP_ACK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 + +#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 + + +struct rx_frame_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_bitmap_available : 1, // [0:0] + explicit_ack : 1, // [1:1] + explict_ack_type : 3, // [4:2] + ba_bitmap_size : 2, // [6:5] + reserved_0a : 3, // [9:7] + ba_tid : 4, // [13:10] + sta_full_aid : 13, // [26:14] + reserved_0b : 5; // [31:27] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr1_47_32 : 16, // [15:0] + addr2_15_0 : 16; // [31:16] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t ba_ts_ctrl : 16, // [15:0] + ba_ts_seq : 16; // [31:16] + uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] + uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] + uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] + uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] + uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] + uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] + uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] + uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0b : 5, // [31:27] + sta_full_aid : 13, // [26:14] + ba_tid : 4, // [13:10] + reserved_0a : 3, // [9:7] + ba_bitmap_size : 2, // [6:5] + explict_ack_type : 3, // [4:2] + explicit_ack : 1, // [1:1] + no_bitmap_available : 1; // [0:0] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr2_15_0 : 16, // [31:16] + addr1_47_32 : 16; // [15:0] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t ba_ts_seq : 16, // [31:16] + ba_ts_ctrl : 16; // [15:0] + uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] + uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] + uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] + uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] + uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] + uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] + uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] + uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description NO_BITMAP_AVAILABLE + + When set, RXPCU does not have any info available for the + requested user. + + RXPCU will set the TA/RA, addresses with the devices OWN + address. + All other fields are set to 0 + + TXPCU will just blindly follow RXPCUs info. + (only for status reporting is TXPCU using this). + + Note that this field and field "Explicit_ack" can not be + simultaneously set. + +*/ + +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 + + +/* Description EXPLICIT_ACK + + When set, no BA is needed for this STA. Instead just a single + ACK indication + + Note that this field and field "No_bitmap_available" can + not be simultaneously set. + + Also note that RXPCU might not know if the response that + TXPCU is generating is a single ACK or M(sta) BA. + For that reason, RXPCU shall also properly fill in all the + BA related fields. TXPCU will based on the explicit ack + type and in case of BA type response, blindely copy the + required BA related fields and not change their contents: + + The related fields are: + Ba_tid + ba_ts_ctrl + ba_ts_seq + ba_ts_bitmap_... + + +*/ + +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 + + +/* Description EXPLICT_ACK_TYPE + + Field only valid when Explicit_ack is set + + Note that TXPCU only needs to evaluate this field in case + of generating a multi (STA) BA + + set when only a single + data frame was received that indicated explicitly a 'normal' + ack (no BA) to be sent. + set when a management frame + was received + set when a PS_POLL frame was received + + set when an association request + was received from an unassociated STA. + set when RXPCU determined that + all frames have been properly received. + +*/ + +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c + + +/* Description BA_BITMAP_SIZE + + Field not valid when "No_bitmap_available" or "Explicit_ack" + is set. + + + Bitmap size set to window of 32 + Bitmap size set to window of 64 + Bitmap size set to window of 128 + + Bitmap size set to window of 256 + + + +*/ + +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 + + +/* Description RESERVED_0A + + +*/ + +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000380 + + +/* Description BA_TID + + The tid for the BA +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 + + +/* Description STA_FULL_AID + + The full AID of this station. +*/ + +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 + + +/* Description RESERVED_0B + + +*/ + +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 + + +/* Description ADDR1_31_0 + + lower 32 bits of addr1 of the received frame +*/ + +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 32 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 63 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 + + +/* Description ADDR1_47_32 + + upper 16 bits of addr1 of the received frame +*/ + +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff + + +/* Description ADDR2_15_0 + + lower 16 bits of addr2 of the received frame +*/ + +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 + + +/* Description ADDR2_47_16 + + upper 32 bits of addr2 of the received frame +*/ + +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 32 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 63 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 + + +/* Description BA_TS_CTRL + + Transmit BA control + RXPCU assumes the C-BA format, NOT M-BA format. + In case TXPCU is responding with M-BA, TXPCU will ignore + this field. TXPCU will generate it +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff + + +/* Description BA_TS_SEQ + + Transmit BA sequence number. +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 + + +/* Description BA_TS_BITMAP_31_0 + + Transmit BA bitmap[31:0] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_63_32 + + Transmit BA bitmap[63:32] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_95_64 + + Transmit BA bitmap[95:64] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_127_96 + + Transmit BA bitmap[127:96] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_159_128 + + Transmit BA bitmap[159:128] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_191_160 + + Transmit BA bitmap[191:160] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_223_192 + + Transmit BA bitmap[223:192] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_255_224 + + Transmit BA bitmap[255:224] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000030 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_LSB 32 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MSB 63 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_FRAME_BITMAP_ACK diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_frame_bitmap_req.h b/drivers/staging/fw-api/hw/qcn6432/rx_frame_bitmap_req.h new file mode 100644 index 0000000000000000000000000000000000000000..cd04492e446b0683886bbf69278996479f9953a6 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_frame_bitmap_req.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_FRAME_BITMAP_REQ_H_ +#define _RX_FRAME_BITMAP_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2 + +#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1 + + +struct rx_frame_bitmap_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t explicit_user_request : 1, // [0:0] + user_request_type : 1, // [1:1] + user_number : 6, // [7:2] + sw_peer_id : 16, // [23:8] + tid_specific_request : 1, // [24:24] + requested_tid : 4, // [28:25] + reserved_0 : 3; // [31:29] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0 : 3, // [31:29] + requested_tid : 4, // [28:25] + tid_specific_request : 1, // [24:24] + sw_peer_id : 16, // [23:8] + user_number : 6, // [7:2] + user_request_type : 1, // [1:1] + explicit_user_request : 1; // [0:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description EXPLICIT_USER_REQUEST + + Note: TXCPU is allowed to interleave requests of the two + different types + + Also, for either request, RXPCU shall clear the internal + flag that linked the bitmap to the just received frame + + + When set, TXPCU is asking for the bitmap for an explicit + user. This is typically only to be used after an MU OFDMA + or MU MIMO reception. Note that this request can be used + to retrieve bitmaps that do not necessarily belong to the + just received PPDU, but might have been generated a while + ago. + + When not set, it is up to RXPCU to decide which bitmap it + wants to give to TXPCU based on what is available (and + has not been passed on the TXPCU in a previous request, + which might have included a request in the 'Explicit_user_request' + format). This type of request is typically (but not required + to be) used in case of a non OFDMA reception, where a + BA needs to be send back as response. + It is mode is typically (but not required to be) used by + TXPCU in case of sending a Multi STA BA + Note that this request can only be used to retrieve bitmaps + that are generated as result of the just received PPDU, + and can not be used to retrieve bitmaps of earlier received + PPDUs. + + + +*/ + +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x0000000000000001 + + +/* Description USER_REQUEST_TYPE + + Field only valid when Explicit_user_request is set + + The request is based + on a user_number. This method is typically used in case + of SIFS response for Multi User BA + + The request is based + on the sw_peer_id. This method is typically used in the + response to response scenario where TXPCU got a new scheduling + command for the response to response part, and SW now explicitly + indicates for which STAs a BA shall be requested. + +*/ + +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x0000000000000002 + + +/* Description USER_NUMBER + + Field only valid when Explicit_user_request is set + and User_request_type is set to bitmap_req_user_number_based + + + The user number for which the bitmap is requested. + +*/ + +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x00000000000000fc + + +/* Description SW_PEER_ID + + Field only valid when Explicit_user_request is set + and User_request_type is set to bitmap_req_sw_peer_id_based + + + The sw_peer_id for which the bitmap is requested. + +*/ + +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x0000000000ffff00 + + +/* Description TID_SPECIFIC_REQUEST + + Field only valid when Explicit_user_request is set + + When set, the request is going out for a specific TID, indicated + in field TID + + When clear, it is up to RXPCU to determine in which order + it wants to return bitmaps to TXPCU. Note that these bitmaps + do need to all belong the the requested user, as Explicit_user_request + has also been set. + +*/ + +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x0000000001000000 + + +/* Description REQUESTED_TID + + Field only valid when Explicit_user_request is set + and User_request_type is set to bitmap_req_sw_peer_id_based + + and Tid_specific_request is set + + The TID for which a BA bitmap is requested + +*/ + +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x000000001e000000 + + +/* Description RESERVED_0 + + +*/ + +#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0x00000000e0000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB 32 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB 63 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_FRAME_BITMAP_REQ diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_location_info.h b/drivers/staging/fw-api/hw/qcn6432/rx_location_info.h new file mode 100644 index 0000000000000000000000000000000000000000..fe7854fe8e693a70ae7f97903d70749a031b5860 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_location_info.h @@ -0,0 +1,1026 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_LOCATION_INFO_H_ +#define _RX_LOCATION_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_LOCATION_INFO 28 + + +struct rx_location_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_location_info_valid : 1, // [0:0] + rtt_hw_ifft_mode : 1, // [1:1] + rtt_11az_mode : 2, // [3:2] + reserved_0 : 4, // [7:4] + rtt_num_fac : 8, // [15:8] + rtt_rx_chain_mask : 8, // [23:16] + rtt_num_streams : 8; // [31:24] + uint32_t rtt_first_selected_chain : 8, // [7:0] + rtt_second_selected_chain : 8, // [15:8] + rtt_cfr_status : 8, // [23:16] + rtt_cir_status : 8; // [31:24] + uint32_t rtt_che_buffer_pointer_low32 : 32; // [31:0] + uint32_t rtt_che_buffer_pointer_high8 : 8, // [7:0] + reserved_3 : 8, // [15:8] + rtt_pkt_bw_vht : 4, // [19:16] + rtt_pkt_bw_leg : 4, // [23:20] + rtt_mcs_rate : 8; // [31:24] + uint32_t rtt_cfo_measurement : 16, // [15:0] + rtt_preamble_type : 8, // [23:16] + rtt_gi_type : 8; // [31:24] + uint32_t rx_start_ts : 32; // [31:0] + uint32_t rx_start_ts_upper : 32; // [31:0] + uint32_t rx_end_ts : 32; // [31:0] + uint32_t gain_chain0 : 16, // [15:0] + gain_chain1 : 16; // [31:16] + uint32_t gain_chain2 : 16, // [15:0] + gain_chain3 : 16; // [31:16] + uint32_t gain_report_status : 8, // [7:0] + rtt_timing_backoff_sel : 8, // [15:8] + rtt_fac_combined : 16; // [31:16] + uint32_t rtt_fac_0 : 16, // [15:0] + rtt_fac_1 : 16; // [31:16] + uint32_t rtt_fac_2 : 16, // [15:0] + rtt_fac_3 : 16; // [31:16] + uint32_t rtt_fac_4 : 16, // [15:0] + rtt_fac_5 : 16; // [31:16] + uint32_t rtt_fac_6 : 16, // [15:0] + rtt_fac_7 : 16; // [31:16] + uint32_t rtt_fac_8 : 16, // [15:0] + rtt_fac_9 : 16; // [31:16] + uint32_t rtt_fac_10 : 16, // [15:0] + rtt_fac_11 : 16; // [31:16] + uint32_t rtt_fac_12 : 16, // [15:0] + rtt_fac_13 : 16; // [31:16] + uint32_t rtt_fac_14 : 16, // [15:0] + rtt_fac_15 : 16; // [31:16] + uint32_t rtt_fac_16 : 16, // [15:0] + rtt_fac_17 : 16; // [31:16] + uint32_t rtt_fac_18 : 16, // [15:0] + rtt_fac_19 : 16; // [31:16] + uint32_t rtt_fac_20 : 16, // [15:0] + rtt_fac_21 : 16; // [31:16] + uint32_t rtt_fac_22 : 16, // [15:0] + rtt_fac_23 : 16; // [31:16] + uint32_t rtt_fac_24 : 16, // [15:0] + rtt_fac_25 : 16; // [31:16] + uint32_t rtt_fac_26 : 16, // [15:0] + rtt_fac_27 : 16; // [31:16] + uint32_t rtt_fac_28 : 16, // [15:0] + rtt_fac_29 : 16; // [31:16] + uint32_t rtt_fac_30 : 16, // [15:0] + rtt_fac_31 : 16; // [31:16] + uint32_t reserved_27a : 32; // [31:0] +#else + uint32_t rtt_num_streams : 8, // [31:24] + rtt_rx_chain_mask : 8, // [23:16] + rtt_num_fac : 8, // [15:8] + reserved_0 : 4, // [7:4] + rtt_11az_mode : 2, // [3:2] + rtt_hw_ifft_mode : 1, // [1:1] + rx_location_info_valid : 1; // [0:0] + uint32_t rtt_cir_status : 8, // [31:24] + rtt_cfr_status : 8, // [23:16] + rtt_second_selected_chain : 8, // [15:8] + rtt_first_selected_chain : 8; // [7:0] + uint32_t rtt_che_buffer_pointer_low32 : 32; // [31:0] + uint32_t rtt_mcs_rate : 8, // [31:24] + rtt_pkt_bw_leg : 4, // [23:20] + rtt_pkt_bw_vht : 4, // [19:16] + reserved_3 : 8, // [15:8] + rtt_che_buffer_pointer_high8 : 8; // [7:0] + uint32_t rtt_gi_type : 8, // [31:24] + rtt_preamble_type : 8, // [23:16] + rtt_cfo_measurement : 16; // [15:0] + uint32_t rx_start_ts : 32; // [31:0] + uint32_t rx_start_ts_upper : 32; // [31:0] + uint32_t rx_end_ts : 32; // [31:0] + uint32_t gain_chain1 : 16, // [31:16] + gain_chain0 : 16; // [15:0] + uint32_t gain_chain3 : 16, // [31:16] + gain_chain2 : 16; // [15:0] + uint32_t rtt_fac_combined : 16, // [31:16] + rtt_timing_backoff_sel : 8, // [15:8] + gain_report_status : 8; // [7:0] + uint32_t rtt_fac_1 : 16, // [31:16] + rtt_fac_0 : 16; // [15:0] + uint32_t rtt_fac_3 : 16, // [31:16] + rtt_fac_2 : 16; // [15:0] + uint32_t rtt_fac_5 : 16, // [31:16] + rtt_fac_4 : 16; // [15:0] + uint32_t rtt_fac_7 : 16, // [31:16] + rtt_fac_6 : 16; // [15:0] + uint32_t rtt_fac_9 : 16, // [31:16] + rtt_fac_8 : 16; // [15:0] + uint32_t rtt_fac_11 : 16, // [31:16] + rtt_fac_10 : 16; // [15:0] + uint32_t rtt_fac_13 : 16, // [31:16] + rtt_fac_12 : 16; // [15:0] + uint32_t rtt_fac_15 : 16, // [31:16] + rtt_fac_14 : 16; // [15:0] + uint32_t rtt_fac_17 : 16, // [31:16] + rtt_fac_16 : 16; // [15:0] + uint32_t rtt_fac_19 : 16, // [31:16] + rtt_fac_18 : 16; // [15:0] + uint32_t rtt_fac_21 : 16, // [31:16] + rtt_fac_20 : 16; // [15:0] + uint32_t rtt_fac_23 : 16, // [31:16] + rtt_fac_22 : 16; // [15:0] + uint32_t rtt_fac_25 : 16, // [31:16] + rtt_fac_24 : 16; // [15:0] + uint32_t rtt_fac_27 : 16, // [31:16] + rtt_fac_26 : 16; // [15:0] + uint32_t rtt_fac_29 : 16, // [31:16] + rtt_fac_28 : 16; // [15:0] + uint32_t rtt_fac_31 : 16, // [31:16] + rtt_fac_30 : 16; // [15:0] + uint32_t reserved_27a : 32; // [31:0] +#endif +}; + + +/* Description RX_LOCATION_INFO_VALID + + + + +*/ + +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001 + + +/* Description RTT_HW_IFFT_MODE + + Indicator showing if HW IFFT mode or SW IFFT mode + + + + +*/ + +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002 + + +/* Description RTT_11AZ_MODE + + Indicator showing RTT5/.11mc or .11az mode for debug + + legacy RTT5/.11mc mode + .11az ISTA location info. sent + on Rx path after receiving R2I LMR + + .11az RSTA location info. sent + on Tx path after transmitting R2I LMR + +*/ + +#define RX_LOCATION_INFO_RTT_11AZ_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_LSB 2 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MSB 3 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MASK 0x0000000c + + +/* Description RESERVED_0 + + +*/ + +#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RESERVED_0_LSB 4 +#define RX_LOCATION_INFO_RESERVED_0_MSB 7 +#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0 + + +/* Description RTT_NUM_FAC + + Number of valid first arrival correction (FAC) values (in + fields rtt_fac_0 - rtt_fac_31) + +*/ + +#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00 + + +/* Description RTT_RX_CHAIN_MASK + + Rx chain mask, each bit is a Rx chain + 0: the Rx chain is not used + 1: the Rx chain is used + + Up to 4 Rx chains are supported. + + +*/ + +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 + + +/* Description RTT_NUM_STREAMS + + Number of streams used + + Up to 8 streams are supported. + + +*/ + +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000 + + +/* Description RTT_FIRST_SELECTED_CHAIN + + For legacy RTT5/.11mc mode, this field shows the first selected + Rx chain that is used for FAC calculations, when forced + by a virtual register. + + + + + + +*/ + +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff + + +/* Description RTT_SECOND_SELECTED_CHAIN + + For legacy RTT5/.11mc mode, this field shows the second + selected Rx chain that is used for FAC calculations, when + forced by a virtual register. + + + + + + +*/ + +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 + + +/* Description RTT_CFR_STATUS + + Status of channel frequency response dump + + + + +*/ + +#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000 + + +/* Description RTT_CIR_STATUS + + Status of channel impulse response dump + + + + +*/ + +#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000 + + +/* Description RTT_CHE_BUFFER_POINTER_LOW32 + + The low 32 bits of the 40 bits pointer pointed to the external + RTT channel information buffer + +*/ + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + + +/* Description RTT_CHE_BUFFER_POINTER_HIGH8 + + The high 8 bits of the 40 bits pointer pointed to the external + RTT channel information buffer + +*/ + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff + + +/* Description RESERVED_3 + + +*/ + +#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RESERVED_3_LSB 8 +#define RX_LOCATION_INFO_RESERVED_3_MSB 15 +#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00 + + +/* Description RTT_PKT_BW_VHT + + Indicate the bandwidth of (V)HT/HE-LTF + + + + + + Only valid for CFR, FAC + calculations are not PoR for 240 MHz. + Only valid for CFR, FAC + calculations are not PoR for 320 MHz. + +*/ + +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000 + + +/* Description RTT_PKT_BW_LEG + + Indicate the bandwidth of L-LTF + + + + + + Only valid for CFR, FAC + calculations are not PoR for 240 MHz. + Only valid for CFR, FAC + calculations are not PoR for 320 MHz. + +*/ + +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000 + + +/* Description RTT_MCS_RATE + + Bits 0~4 indicate MCS rate, if Legacy, + 0: 48 Mbps, + 1: 24 Mbps, + 2: 12 Mbps, + 3: 6 Mbps, + 4: 54 Mbps, + 5: 36 Mbps, + 6: 18 Mbps, + 7: 9 Mbps, + 8-15: reserved + + if HT, 0-7: MCS0-MCS7, 8-15: reserved, + if VHT, 0-9: MCS0-MCS9, 10-15: reserved, + if HE or EHT, 0-11: MCS0-MCS11, 12-13: 4096QAM, 14-15: reserved + + +*/ + +#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000 + + +/* Description RTT_CFO_MEASUREMENT + + CFO measurement. Needed for passive locationing + + 14 bits, signed 1.13. 13 bits fraction to provide a resolution + of 153 Hz + + In units of cycles/800 ns + +*/ + +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff + + +/* Description RTT_PREAMBLE_TYPE + + Indicate preamble type + + + + + + + + + + + + + + + + + + + + + + + +*/ + +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 + + +/* Description RTT_GI_TYPE + + Indicate GI (guard interval) type + + HE related GI. Can also be + used for HE + HE related GI. Can also be + used for HE + HE related GI + HE related GI + +*/ + +#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000 + + +/* Description RX_START_TS + + RX packet start timestamp lower 32 bits + + It reports the time the first L-STF ADC sample arrived at + RX antenna. + + The clock unit is 960MHz. + +*/ + +#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014 +#define RX_LOCATION_INFO_RX_START_TS_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff + + +/* Description RX_START_TS_UPPER + + RX packet start timestamp upper 32 bits + + It reports the time the first L-STF ADC sample arrived at + RX antenna. + + The clock unit is 960MHz. + +*/ + +#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff + + +/* Description RX_END_TS + + RX packet end timestamp lower 32 bits + + It reports the time the last symbol's last ADC sample arrived + at RX antenna. + + The clock unit is 960MHz. Only 32 bits are reported. + +*/ + +#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c +#define RX_LOCATION_INFO_RX_END_TS_LSB 0 +#define RX_LOCATION_INFO_RX_END_TS_MSB 31 +#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff + + +/* Description GAIN_CHAIN0 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain0 +*/ + +#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff + + +/* Description GAIN_CHAIN1 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain1 +*/ + +#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000 + + +/* Description GAIN_CHAIN2 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain2 +*/ + +#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff + + +/* Description GAIN_CHAIN3 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain3 +*/ + +#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000 + + +/* Description GAIN_REPORT_STATUS + + Number of valid gain reports (in fields gain_chain0 - gain_chain_3) + + +*/ + +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff + + +/* Description RTT_TIMING_BACKOFF_SEL + + Indicate which timing backoff value is used + + + + + + +*/ + +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 + + +/* Description RTT_FAC_COMBINED + + Final adjusted and combined first arrival correction value + + +*/ + +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000 + + +/* Description RTT_FAC_0 + + The fields 'rtt_fac_0' - 'rtt_fac_31' show the RTT first + arrival correction (FAC) value computed from the LTFs on + the selected Rx chains. + + 16 bits, signed 11.5. 11 integer bits to cover -3.2us to + 3.2us, and 5 fraction bits to cover 160 MHz with 32x FAC + interpolation. + + The clock unit is 320MHz. + + For .11az/MIMO, the FACs will be stored in spatial stream + order with multiple chains reported together for each stream. [ss0-ch0, + ss0-ch1, ..., ss1-ch0, ss1-ch1, ...] + + For legacy RTT5/.11mc, the FACs will be stored in preamble + order with multiple chains reported together for each LTF. [legacy-ch0, + legacy-ch1, ..., (v)ht/he-ch0, (v)ht/he-ch1, ...] +*/ + +#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff + + +/* Description RTT_FAC_1 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000 + + +/* Description RTT_FAC_2 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff + + +/* Description RTT_FAC_3 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000 + + +/* Description RTT_FAC_4 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff + + +/* Description RTT_FAC_5 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000 + + +/* Description RTT_FAC_6 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff + + +/* Description RTT_FAC_7 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000 + + +/* Description RTT_FAC_8 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff + + +/* Description RTT_FAC_9 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000 + + +/* Description RTT_FAC_10 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff + + +/* Description RTT_FAC_11 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000 + + +/* Description RTT_FAC_12 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff + + +/* Description RTT_FAC_13 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000 + + +/* Description RTT_FAC_14 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff + + +/* Description RTT_FAC_15 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000 + + +/* Description RTT_FAC_16 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff + + +/* Description RTT_FAC_17 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000 + + +/* Description RTT_FAC_18 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff + + +/* Description RTT_FAC_19 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000 + + +/* Description RTT_FAC_20 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff + + +/* Description RTT_FAC_21 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000 + + +/* Description RTT_FAC_22 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff + + +/* Description RTT_FAC_23 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000 + + +/* Description RTT_FAC_24 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff + + +/* Description RTT_FAC_25 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000 + + +/* Description RTT_FAC_26 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff + + +/* Description RTT_FAC_27 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000 + + +/* Description RTT_FAC_28 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff + + +/* Description RTT_FAC_29 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000 + + +/* Description RTT_FAC_30 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff + + +/* Description RTT_FAC_31 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000 + + +/* Description RESERVED_27A + + +*/ + +#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_LOCATION_INFO_RESERVED_27A_LSB 0 +#define RX_LOCATION_INFO_RESERVED_27A_MSB 31 +#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff + + + +#endif // RX_LOCATION_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_desc_info.h new file mode 100644 index 0000000000000000000000000000000000000000..b395c42098585f05339e58e7605c6e7dac3b70d6 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_desc_info.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MPDU_DESC_INFO_H_ +#define _RX_MPDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 + + +struct rx_mpdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_count : 8, // [7:0] + fragment_flag : 1, // [8:8] + mpdu_retry_bit : 1, // [9:9] + ampdu_flag : 1, // [10:10] + bar_frame : 1, // [11:11] + pn_fields_contain_valid_info : 1, // [12:12] + raw_mpdu : 1, // [13:13] + more_fragment_flag : 1, // [14:14] + src_info : 12, // [26:15] + mpdu_qos_control_valid : 1, // [27:27] + tid : 4; // [31:28] + uint32_t peer_meta_data : 32; // [31:0] +#else + uint32_t tid : 4, // [31:28] + mpdu_qos_control_valid : 1, // [27:27] + src_info : 12, // [26:15] + more_fragment_flag : 1, // [14:14] + raw_mpdu : 1, // [13:13] + pn_fields_contain_valid_info : 1, // [12:12] + bar_frame : 1, // [11:11] + ampdu_flag : 1, // [10:10] + mpdu_retry_bit : 1, // [9:9] + fragment_flag : 1, // [8:8] + msdu_count : 8; // [7:0] + uint32_t peer_meta_data : 32; // [31:0] +#endif +}; + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 +#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 +#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_TID_LSB 28 +#define RX_MPDU_DESC_INFO_TID_MSB 31 +#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff + + + +#endif // RX_MPDU_DESC_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_details.h b/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_details.h new file mode 100644 index 0000000000000000000000000000000000000000..d90b3c380f79c7e4282e846c2a7cbbedd0012f0c --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_details.h @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MPDU_DETAILS_H_ +#define _RX_MPDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 + + +struct rx_mpdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#else + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#endif +}; + + +/* Description MSDU_LINK_DESC_ADDR_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Details of the physical address of the MSDU link descriptor + that contains pointers to MSDUs related to this MPDU +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MPDU_DESC_INFO_DETAILS + + Consumer: REO/SW/FW + Producer: RXDMA + + General information related to the MPDU that should be passed + on from REO entrance ring to the REO destination ring +*/ + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + + +#endif // RX_MPDU_DETAILS diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_end.h b/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_end.h new file mode 100644 index 0000000000000000000000000000000000000000..e0508f3cd21ff313375611a8ab9a1d35f59fb7b8 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_end.h @@ -0,0 +1,531 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MPDU_END_H_ +#define _RX_MPDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_END 4 + +#define NUM_OF_QWORDS_RX_MPDU_END 2 + + +struct rx_mpdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] + sw_frame_group_id : 7, // [8:2] + reserved_0 : 7, // [15:9] + phy_ppdu_id : 16; // [31:16] + uint32_t reserved_1a : 11, // [10:0] + unsup_ktype_short_frame : 1, // [11:11] + rx_in_tx_decrypt_byp : 1, // [12:12] + overflow_err : 1, // [13:13] + mpdu_length_err : 1, // [14:14] + tkip_mic_err : 1, // [15:15] + decrypt_err : 1, // [16:16] + unencrypted_frame_err : 1, // [17:17] + pn_fields_contain_valid_info : 1, // [18:18] + fcs_err : 1, // [19:19] + msdu_length_err : 1, // [20:20] + rxdma0_destination_ring : 3, // [23:21] + rxdma1_destination_ring : 3, // [26:24] + decrypt_status_code : 3, // [29:27] + rx_bitmap_not_updated : 1, // [30:30] + reserved_1b : 1; // [31:31] + uint32_t reserved_2a : 15, // [14:0] + rxpcu_mgmt_sequence_nr_valid : 1, // [15:15] + rxpcu_mgmt_sequence_nr : 16; // [31:16] + uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0] +#else + uint32_t phy_ppdu_id : 16, // [31:16] + reserved_0 : 7, // [15:9] + sw_frame_group_id : 7, // [8:2] + rxpcu_mpdu_filter_in_category : 2; // [1:0] + uint32_t reserved_1b : 1, // [31:31] + rx_bitmap_not_updated : 1, // [30:30] + decrypt_status_code : 3, // [29:27] + rxdma1_destination_ring : 3, // [26:24] + rxdma0_destination_ring : 3, // [23:21] + msdu_length_err : 1, // [20:20] + fcs_err : 1, // [19:19] + pn_fields_contain_valid_info : 1, // [18:18] + unencrypted_frame_err : 1, // [17:17] + decrypt_err : 1, // [16:16] + tkip_mic_err : 1, // [15:15] + mpdu_length_err : 1, // [14:14] + overflow_err : 1, // [13:13] + rx_in_tx_decrypt_byp : 1, // [12:12] + unsup_ktype_short_frame : 1, // [11:11] + reserved_1a : 11; // [10:0] + uint32_t rxpcu_mgmt_sequence_nr : 16, // [31:16] + rxpcu_mgmt_sequence_nr_valid : 1, // [15:15] + reserved_2a : 15; // [14:0] + uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0] +#endif +}; + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + This MPDU passed the normal frame + filter programming of rxpcu + This MPDU did NOT pass the + regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + This MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + +*/ + +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + +/* Description SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. This + field indicates to what sw classification this MPDU is + mapped. + The classification is given in priority order + + + + + + This includes mpdus of + type Data Null. + This includes QoS + Null frames except in UL MU or TB PPDUs. + This includes + QoS Null frames in UL MU or TB PPDUs. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + PHY reported an error + + + +*/ + +#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + +/* Description RESERVED_0 + + +*/ + +#define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RESERVED_0_LSB 9 +#define RX_MPDU_END_RESERVED_0_MSB 15 +#define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_MPDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description RESERVED_1A + + +*/ + +#define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RESERVED_1A_LSB 32 +#define RX_MPDU_END_RESERVED_1A_MSB 42 +#define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000 + + +/* Description UNSUP_KTYPE_SHORT_FRAME + + This bit will be '1' when WEP or TKIP or WAPI key type is + received for 11ah short frame. Crypto will bypass the + received packet without decryption to RxOLE after setting + this bit. +*/ + +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 + + +/* Description RX_IN_TX_DECRYPT_BYP + + Indicates that RX packet is not decrypted as Crypto is busy + with TX packet processing. +*/ + +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 + + +/* Description OVERFLOW_ERR + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + This MPDU will not be ACKed. + RXPCU might still be able to correctly receive the following + MPDUs in the PPDU if enough fifo space became available + in time +*/ + +#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_OVERFLOW_ERR_LSB 45 +#define RX_MPDU_END_OVERFLOW_ERR_MSB 45 +#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 + + +/* Description MPDU_LENGTH_ERR + + Set by RXPCU if the expected MPDU length does not correspond + with the actually received number of bytes in the MPDU. + +*/ + +#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 + + +/* Description TKIP_MIC_ERR + + Set by RX CRYPTO when CRYPTO detected a TKIP MIC error for + this MPDU +*/ + +#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 +#define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 +#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 + + +/* Description DECRYPT_ERR + + Set by RX CRYPTO when CRYPTO detected a decrypt error for + this MPDU or CRYPTO received an encrypted frame, but did + not get a valid corresponding key id in the peer entry. + +*/ + +#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_DECRYPT_ERR_LSB 48 +#define RX_MPDU_END_DECRYPT_ERR_MSB 48 +#define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 + + +/* Description UNENCRYPTED_FRAME_ERR + + Set by RX CRYPTO when CRYPTO detected an unencrypted frame + while in the peer entry field 'All_frames_shall_be_encrypted' + is set. +*/ + +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Set by RX CRYPTO to indicate that there is a valid PN field + present in this MPDU +*/ + +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 + + +/* Description FCS_ERR + + Set by RXPCU when there is an FCS error detected for this + MPDU + NOTE that when this field is set, all other (error) field + settings should be ignored as modules could have made wrong + decisions based on the corrupted data. +*/ + +#define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_FCS_ERR_LSB 51 +#define RX_MPDU_END_FCS_ERR_MSB 51 +#define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 + + +/* Description MSDU_LENGTH_ERR + + Set by RXOLE when there is an msdu length error detected + in at least 1 of the MSDUs embedded within the MPDU +*/ + +#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 + + +/* Description RXDMA0_DESTINATION_RING + + The ring to which RXDMA0 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA0 might change the RXDMA0 destination + + RXDMA0 shall push the frame + to the Release ring. Effectively this means the frame needs + to be dropped. + + RXDMA0 shall push the frame + to the FW ring for PMAC0. + + RXDMA0 shall push the frame to + the SW ring + + RXDMA0 shall push the frame to + the REO entrance ring + + RXDMA0 shall push the frame + to the FW ring for PMAC1. + + RXDMA0 shall push the frame + to the first MLO REO entrance ring. + + RXDMA0 shall push the frame + to the second MLO REO entrance ring. + + +*/ + +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000 + + +/* Description RXDMA1_DESTINATION_RING + + The ring to which RXDMA1 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA1 might change the RXDMA destination + + DO NOT USE. + + DO NOT USE. + + RXDMA1 shall push the frame to + the SW ring + + DO NOT USE. + + DO NOT USE. + + DO NOT USE. + + DO NOT USE. + + +*/ + +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000 + + +/* Description DECRYPT_STATUS_CODE + + Field provides insight into the decryption performed + + Frame had protection enabled and decrypted + properly + Frame is unprotected + and hence bypassed + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + Frame has protection enabled + but the key that was required to decrypt this frame was + not valid + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + Reserved for other indications + + +*/ + +#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 + + +/* Description RX_BITMAP_NOT_UPDATED + + Frame is received, but RXPCU could not update the receive + bitmap due to (temporary) fifo contraints. + +*/ + +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RESERVED_1B_LSB 63 +#define RX_MPDU_END_RESERVED_1B_MSB 63 +#define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000 + + +/* Description RESERVED_2A + + +*/ + +#define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RESERVED_2A_LSB 0 +#define RX_MPDU_END_RESERVED_2A_MSB 14 +#define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff + + +/* Description RXPCU_MGMT_SEQUENCE_NR_VALID + + This field gets set by RXPCU when the received management + frame is destined to this device, passes FCS and is categorized + as one for which RXPCU should assign a rxpcu_mgmt_sequence_number. + After assigning a number, the RXPCU will increment the sequence + number for the next management frame that meets these criteria. + + + +*/ + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 + + +/* Description RXPCU_MGMT_SEQUENCE_NR + + Field only valid when rxpcu_mgmt_sequence_nr_valid is set + + + This RXPCU generated sequence number is assigned to this + management frame. It is used by FW and host SW for management + frame reordering across multiple bands/links. + + +*/ + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 + + +/* Description RXFRAME_ASSERT_MLO_TIMESTAMP + + 'mlo_global_timestamp' that indicates when for the PPDU + that contained this MPDU, the 'rx_frame' signal got asserted. + + + This field is always valid, irrespective of the frame being + related to MLO reception or not. It is used by FW and host + SW for management frame reordering purposes. + + +*/ + +#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_LSB 32 +#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MSB 63 +#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MASK 0xffffffff00000000 + + + +#endif // RX_MPDU_END diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_info.h b/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_info.h new file mode 100644 index 0000000000000000000000000000000000000000..13f8770c1a3c7ffa2c1b148e56f945cf73a8fe57 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_info.h @@ -0,0 +1,2415 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MPDU_INFO_H_ +#define _RX_MPDU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rxpt_classify_info.h" +#define NUM_OF_DWORDS_RX_MPDU_INFO 30 + + +struct rx_mpdu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] + receive_queue_number : 16, // [23:8] + pre_delim_err_warning : 1, // [24:24] + first_delim_err : 1, // [25:25] + reserved_2a : 6; // [31:26] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t epd_en : 1, // [0:0] + all_frames_shall_be_encrypted : 1, // [1:1] + encrypt_type : 4, // [5:2] + wep_key_width_for_variable_key : 2, // [7:6] + mesh_sta : 2, // [9:8] + bssid_hit : 1, // [10:10] + bssid_number : 4, // [14:11] + tid : 4, // [18:15] + reserved_7a : 13; // [31:19] + uint32_t peer_meta_data : 32; // [31:0] + uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] + sw_frame_group_id : 7, // [8:2] + ndp_frame : 1, // [9:9] + phy_err : 1, // [10:10] + phy_err_during_mpdu_header : 1, // [11:11] + protocol_version_err : 1, // [12:12] + ast_based_lookup_valid : 1, // [13:13] + ranging : 1, // [14:14] + reserved_9a : 1, // [15:15] + phy_ppdu_id : 16; // [31:16] + uint32_t ast_index : 16, // [15:0] + sw_peer_id : 16; // [31:16] + uint32_t mpdu_frame_control_valid : 1, // [0:0] + mpdu_duration_valid : 1, // [1:1] + mac_addr_ad1_valid : 1, // [2:2] + mac_addr_ad2_valid : 1, // [3:3] + mac_addr_ad3_valid : 1, // [4:4] + mac_addr_ad4_valid : 1, // [5:5] + mpdu_sequence_control_valid : 1, // [6:6] + mpdu_qos_control_valid : 1, // [7:7] + mpdu_ht_control_valid : 1, // [8:8] + frame_encryption_info_valid : 1, // [9:9] + mpdu_fragment_number : 4, // [13:10] + more_fragment_flag : 1, // [14:14] + reserved_11a : 1, // [15:15] + fr_ds : 1, // [16:16] + to_ds : 1, // [17:17] + encrypted : 1, // [18:18] + mpdu_retry : 1, // [19:19] + mpdu_sequence_number : 12; // [31:20] + uint32_t key_id_octet : 8, // [7:0] + new_peer_entry : 1, // [8:8] + decrypt_needed : 1, // [9:9] + decap_type : 2, // [11:10] + rx_insert_vlan_c_tag_padding : 1, // [12:12] + rx_insert_vlan_s_tag_padding : 1, // [13:13] + strip_vlan_c_tag_decap : 1, // [14:14] + strip_vlan_s_tag_decap : 1, // [15:15] + pre_delim_count : 12, // [27:16] + ampdu_flag : 1, // [28:28] + bar_frame : 1, // [29:29] + raw_mpdu : 1, // [30:30] + reserved_12 : 1; // [31:31] + uint32_t mpdu_length : 14, // [13:0] + first_mpdu : 1, // [14:14] + mcast_bcast : 1, // [15:15] + ast_index_not_found : 1, // [16:16] + ast_index_timeout : 1, // [17:17] + power_mgmt : 1, // [18:18] + non_qos : 1, // [19:19] + null_data : 1, // [20:20] + mgmt_type : 1, // [21:21] + ctrl_type : 1, // [22:22] + more_data : 1, // [23:23] + eosp : 1, // [24:24] + fragment_flag : 1, // [25:25] + order : 1, // [26:26] + u_apsd_trigger : 1, // [27:27] + encrypt_required : 1, // [28:28] + directed : 1, // [29:29] + amsdu_present : 1, // [30:30] + reserved_13 : 1; // [31:31] + uint32_t mpdu_frame_control_field : 16, // [15:0] + mpdu_duration_field : 16; // [31:16] + uint32_t mac_addr_ad1_31_0 : 32; // [31:0] + uint32_t mac_addr_ad1_47_32 : 16, // [15:0] + mac_addr_ad2_15_0 : 16; // [31:16] + uint32_t mac_addr_ad2_47_16 : 32; // [31:0] + uint32_t mac_addr_ad3_31_0 : 32; // [31:0] + uint32_t mac_addr_ad3_47_32 : 16, // [15:0] + mpdu_sequence_control_field : 16; // [31:16] + uint32_t mac_addr_ad4_31_0 : 32; // [31:0] + uint32_t mac_addr_ad4_47_32 : 16, // [15:0] + mpdu_qos_control_field : 16; // [31:16] + uint32_t mpdu_ht_control_field : 32; // [31:0] + uint32_t vdev_id : 8, // [7:0] + service_code : 9, // [16:8] + priority_valid : 1, // [17:17] + src_info : 12, // [29:18] + reserved_23a : 1, // [30:30] + multi_link_addr_ad1_ad2_valid : 1; // [31:31] + uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] + uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0] + multi_link_addr_ad2_15_0 : 16; // [31:16] + uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] + uint32_t authorized_to_send_wds : 1, // [0:0] + reserved_27a : 31; // [31:1] + uint32_t reserved_28a : 32; // [31:0] + uint32_t reserved_29a : 32; // [31:0] +#else + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t reserved_2a : 6, // [31:26] + first_delim_err : 1, // [25:25] + pre_delim_err_warning : 1, // [24:24] + receive_queue_number : 16, // [23:8] + rx_reo_queue_desc_addr_39_32 : 8; // [7:0] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t reserved_7a : 13, // [31:19] + tid : 4, // [18:15] + bssid_number : 4, // [14:11] + bssid_hit : 1, // [10:10] + mesh_sta : 2, // [9:8] + wep_key_width_for_variable_key : 2, // [7:6] + encrypt_type : 4, // [5:2] + all_frames_shall_be_encrypted : 1, // [1:1] + epd_en : 1; // [0:0] + uint32_t peer_meta_data : 32; // [31:0] + uint32_t phy_ppdu_id : 16, // [31:16] + reserved_9a : 1, // [15:15] + ranging : 1, // [14:14] + ast_based_lookup_valid : 1, // [13:13] + protocol_version_err : 1, // [12:12] + phy_err_during_mpdu_header : 1, // [11:11] + phy_err : 1, // [10:10] + ndp_frame : 1, // [9:9] + sw_frame_group_id : 7, // [8:2] + rxpcu_mpdu_filter_in_category : 2; // [1:0] + uint32_t sw_peer_id : 16, // [31:16] + ast_index : 16; // [15:0] + uint32_t mpdu_sequence_number : 12, // [31:20] + mpdu_retry : 1, // [19:19] + encrypted : 1, // [18:18] + to_ds : 1, // [17:17] + fr_ds : 1, // [16:16] + reserved_11a : 1, // [15:15] + more_fragment_flag : 1, // [14:14] + mpdu_fragment_number : 4, // [13:10] + frame_encryption_info_valid : 1, // [9:9] + mpdu_ht_control_valid : 1, // [8:8] + mpdu_qos_control_valid : 1, // [7:7] + mpdu_sequence_control_valid : 1, // [6:6] + mac_addr_ad4_valid : 1, // [5:5] + mac_addr_ad3_valid : 1, // [4:4] + mac_addr_ad2_valid : 1, // [3:3] + mac_addr_ad1_valid : 1, // [2:2] + mpdu_duration_valid : 1, // [1:1] + mpdu_frame_control_valid : 1; // [0:0] + uint32_t reserved_12 : 1, // [31:31] + raw_mpdu : 1, // [30:30] + bar_frame : 1, // [29:29] + ampdu_flag : 1, // [28:28] + pre_delim_count : 12, // [27:16] + strip_vlan_s_tag_decap : 1, // [15:15] + strip_vlan_c_tag_decap : 1, // [14:14] + rx_insert_vlan_s_tag_padding : 1, // [13:13] + rx_insert_vlan_c_tag_padding : 1, // [12:12] + decap_type : 2, // [11:10] + decrypt_needed : 1, // [9:9] + new_peer_entry : 1, // [8:8] + key_id_octet : 8; // [7:0] + uint32_t reserved_13 : 1, // [31:31] + amsdu_present : 1, // [30:30] + directed : 1, // [29:29] + encrypt_required : 1, // [28:28] + u_apsd_trigger : 1, // [27:27] + order : 1, // [26:26] + fragment_flag : 1, // [25:25] + eosp : 1, // [24:24] + more_data : 1, // [23:23] + ctrl_type : 1, // [22:22] + mgmt_type : 1, // [21:21] + null_data : 1, // [20:20] + non_qos : 1, // [19:19] + power_mgmt : 1, // [18:18] + ast_index_timeout : 1, // [17:17] + ast_index_not_found : 1, // [16:16] + mcast_bcast : 1, // [15:15] + first_mpdu : 1, // [14:14] + mpdu_length : 14; // [13:0] + uint32_t mpdu_duration_field : 16, // [31:16] + mpdu_frame_control_field : 16; // [15:0] + uint32_t mac_addr_ad1_31_0 : 32; // [31:0] + uint32_t mac_addr_ad2_15_0 : 16, // [31:16] + mac_addr_ad1_47_32 : 16; // [15:0] + uint32_t mac_addr_ad2_47_16 : 32; // [31:0] + uint32_t mac_addr_ad3_31_0 : 32; // [31:0] + uint32_t mpdu_sequence_control_field : 16, // [31:16] + mac_addr_ad3_47_32 : 16; // [15:0] + uint32_t mac_addr_ad4_31_0 : 32; // [31:0] + uint32_t mpdu_qos_control_field : 16, // [31:16] + mac_addr_ad4_47_32 : 16; // [15:0] + uint32_t mpdu_ht_control_field : 32; // [31:0] + uint32_t multi_link_addr_ad1_ad2_valid : 1, // [31:31] + reserved_23a : 1, // [30:30] + src_info : 12, // [29:18] + priority_valid : 1, // [17:17] + service_code : 9, // [16:8] + vdev_id : 8; // [7:0] + uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] + uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16] + multi_link_addr_ad1_47_32 : 16; // [15:0] + uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] + uint32_t reserved_27a : 31, // [31:1] + authorized_to_send_wds : 1; // [0:0] + uint32_t reserved_28a : 32; // [31:0] + uint32_t reserved_29a : 32; // [31:0] +#endif +}; + + +/* Description RXPT_CLASSIFY_INFO_DETAILS + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + RXOLE related classification info + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description LMAC_PEER_ID_MSB + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb + is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, + hash[3:0]} using the chosen Toeplitz hash from Common Parser + if flow search fails. + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb + 's not 2'b00, Rx OLE uses a REO desination indication of + {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz + hash from Common Parser if flow search fails. + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + + +/* Description USE_FLOW_ID_TOEPLITZ_CLFY + + Indication to Rx OLE to enable REO destination routing based + on the chosen Toeplitz hash from Common Parser, in case + flow search fails + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + + +/* Description PKT_SELECTION_FP_UCAST_DATA + + Filter pass Unicast data frame (matching rxpcu_filter_pass + and sw_frame_group_Unicast_data) routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + + +/* Description PKT_SELECTION_FP_MCAST_DATA + + Filter pass Multicast data frame (matching rxpcu_filter_pass + and sw_frame_group_Multicast_data) routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + + +/* Description PKT_SELECTION_FP_1000 + + Filter pass BAR frame (matching rxpcu_filter_pass and sw_frame_group_ctrl_1000) + routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + + +/* Description RXDMA0_SOURCE_RING_SELECTION + + Field only valid when for the received frame type the corresponding + pkt_selection_fp_... bit is set + + The data buffer for + this frame shall be sourced by sw2rxdma0 buffer source + ring. + The data buffer + for this frame shall be sourced by fw2rxdma buffer source + ring for PMAC0. + The data buffer for + this frame shall be sourced by sw2rxdma1 buffer source + ring. + The frame shall not be written + to any data buffer. + The data buffer + for this frame shall be sourced by sw2rxdma_exception buffer + source ring. + The data buffer + for this frame shall be sourced by fw2rxdma buffer source + ring for PMAC1. + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + + +/* Description RXDMA0_DESTINATION_RING_SELECTION + + Field only valid when for the received frame type the corresponding + pkt_selection_fp_... bit is set + + RXDMA0 shall push the frame + to the Release ring. Effectively this means the frame needs + to be dropped. + RXDMA0 shall push the frame + to the FW ring for PMAC0. + RXDMA0 shall push the frame to the + SW ring. + RXDMA0 shall push the frame to + the REO entrance ring. + RXDMA0 shall push the frame + to the FW ring for PMAC1. + RXDMA0 shall push the frame + to the first MLO REO entrance ring. + RXDMA0 shall push the frame + to the second MLO REO entrance ring. + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + + +/* Description MCAST_ECHO_DROP_ENABLE + + If set, for multicast packets, multicast echo check (i.e. + SA search with mcast_echo_check = 1) shall be performed + by RXOLE, and any multicast echo packets should be indicated + to RXDMA for release to WBM + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + + +/* Description WDS_LEARNING_DETECT_EN + + If set, WDS learning detection based on SA search and notification + to FW (using RXDMA0 status ring) is enabled and the "timestamp" + field in address search failure cache-only entry should + be used to avoid multiple WDS learning notifications. + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + + +/* Description INTRABSS_CHECK_EN + + If set, intra-BSS routing detection is enabled + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 + + +/* Description USE_PPE + + Indicates to RXDMA to ignore the REO_destination_indication + and use a programmed value corresponding to the REO2PPE + ring + + This override to REO2PPE for packets requiring multiple + buffers shall be disabled based on an RXDMA configuration, + as PPE may not support such packets. + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 + + +/* Description PPE_ROUTING_ENABLE + + Global enable/disable bit for routing to PPE, used to disable + PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE' + + + This is set by SW for peers which are being handled by a + host SW/accelerator subsystem that also handles packet + buffer management for WiFi-to-PPE routing. + + This is cleared by SW for peers which are being handled + by a different subsystem, completely disabling WiFi-to-PPE + routing for such peers. + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 + + +/* Description RESERVED_0B + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffc00000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_31_0 + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Address (lower 32 bits) of the REO queue descriptor. + + If no Peer entry lookup happened for this frame, the value + wil be set to 0, and the frame shall never be pushed to + REO entrance ring. + +*/ + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + + +/* Description RX_REO_QUEUE_DESC_ADDR_39_32 + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Address (upper 8 bits) of the REO queue descriptor. + + If no Peer entry lookup happened for this frame, the value + wil be set to 0, and the frame shall never be pushed to + REO entrance ring. + +*/ + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + + +/* Description RECEIVE_QUEUE_NUMBER + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Indicates the MPDU queue ID to which this MPDU link descriptor + belongs + Used for tracking and debugging + +*/ + +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + + +/* Description PRE_DELIM_ERR_WARNING + + Indicates that a delimiter FCS error was found in between + the Previous MPDU and this MPDU. + + Note that this is just a warning, and does not mean that + this MPDU is corrupted in any way. If it is, there will + be other errors indicated such as FCS or decrypt errors + + + In case of ndp or phy_err, this field will indicate at least + one of delimiters located after the last MPDU in the previous + PPDU has been corrupted. +*/ + +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + + +/* Description FIRST_DELIM_ERR + + Indicates that the first delimiter had a FCS failure. Only + valid when first_mpdu and first_msdu are set. + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x00000008 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 + + +/* Description RESERVED_2A + + +*/ + +#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_INFO_RESERVED_2A_LSB 26 +#define RX_MPDU_INFO_RESERVED_2A_MSB 31 +#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 + + +/* Description PN_31_0 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [31:0] of the PN number extracted from the IV field + + WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] + is valid. + TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, WEPSeed[1], + pn1}. Only pn[47:0] is valid. + AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1, + pn0}. Only pn[47:0] is valid. + WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11, + pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}. + pn[127:0] are valid. + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_INFO_PN_31_0_OFFSET 0x0000000c +#define RX_MPDU_INFO_PN_31_0_LSB 0 +#define RX_MPDU_INFO_PN_31_0_MSB 31 +#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff + + +/* Description PN_63_32 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [63:32] of the PN number. See description for pn_31_0. + + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000010 +#define RX_MPDU_INFO_PN_63_32_LSB 0 +#define RX_MPDU_INFO_PN_63_32_MSB 31 +#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff + + +/* Description PN_95_64 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [95:64] of the PN number. See description for pn_31_0. + + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000014 +#define RX_MPDU_INFO_PN_95_64_LSB 0 +#define RX_MPDU_INFO_PN_95_64_MSB 31 +#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff + + +/* Description PN_127_96 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [127:96] of the PN number. See description for pn_31_0. + + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_INFO_PN_127_96_OFFSET 0x00000018 +#define RX_MPDU_INFO_PN_127_96_LSB 0 +#define RX_MPDU_INFO_PN_127_96_MSB 31 +#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff + + +/* Description EPD_EN + + Field only valid when AST_based_lookup_valid == 1. + + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + If set to one use EPD instead of LPD + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_EPD_EN_OFFSET 0x0000001c +#define RX_MPDU_INFO_EPD_EN_LSB 0 +#define RX_MPDU_INFO_EPD_EN_MSB 0 +#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 + + +/* Description ALL_FRAMES_SHALL_BE_ENCRYPTED + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, all frames (data only ?) shall be encrypted. If + not, RX CRYPTO shall set an error flag. + +*/ + +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + + +/* Description ENCRYPT_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + WEP 40-bit + WEP 104-bit + TKIP without MIC + WEP 128-bit + TKIP with MIC + WAPI + AES CCMP 128 + No crypto + AES CCMP 256 + AES CCMP 128 + AES CCMP 256 + WAPI GCM SM4 + + WEP encryption. As for WEP per + keyid the key bit width can vary, the key bit width for + this MPDU will be indicated in field wep_key_width_for_variable + key + +*/ + +#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x0000001c +#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c + + +/* Description WEP_KEY_WIDTH_FOR_VARIABLE_KEY + + Field only valid when key_type is set to wep_varied_width. + + + This field indicates the size of the wep key for this MPDU. + + + WEP 40-bit + WEP 104-bit + WEP 128-bit + + +*/ + +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + + +/* Description MESH_STA + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, this is a Mesh (11s) STA. + + The interpretation of the A-MSDU 'Length' field in the MPDU + (if any) is decided by the e-numerations below. + + + A-MSDU 'Length' is big endian and includes + the length of Mesh Control. + A-MSDU 'Length' is big endian and excludes + the length of Mesh Control. + A-MSDU 'Length' is little endian and + excludes the length of Mesh Control. This is 802.11s-compliant. + + +*/ + +#define RX_MPDU_INFO_MESH_STA_OFFSET 0x0000001c +#define RX_MPDU_INFO_MESH_STA_LSB 8 +#define RX_MPDU_INFO_MESH_STA_MSB 9 +#define RX_MPDU_INFO_MESH_STA_MASK 0x00000300 + + +/* Description BSSID_HIT + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, the BSSID of the incoming frame matched one of + the 8 BSSID register values + + +*/ + +#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x0000001c +#define RX_MPDU_INFO_BSSID_HIT_LSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 + + +/* Description BSSID_NUMBER + + Field only valid when bssid_hit is set. + + This number indicates which one out of the 8 BSSID register + values matched the incoming frame + +*/ + +#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x0000001c +#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 +#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 +#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define RX_MPDU_INFO_TID_OFFSET 0x0000001c +#define RX_MPDU_INFO_TID_LSB 15 +#define RX_MPDU_INFO_TID_MSB 18 +#define RX_MPDU_INFO_TID_MASK 0x00078000 + + +/* Description RESERVED_7A + + +*/ + +#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RX_MPDU_INFO_RESERVED_7A_LSB 19 +#define RX_MPDU_INFO_RESERVED_7A_MSB 31 +#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 + + +/* Description PEER_META_DATA + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + This MPDU passed the normal frame + filter programming of rxpcu + This MPDU did NOT pass the + regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + This MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + + Note: for ndp frame, if it was expected because the preceding + NDPA was filter_pass, the setting rxpcu_filter_pass will + be used. This setting will also be used for every ndp frame + in case Promiscuous mode is enabled. + + In case promiscuous is not enabled, and an NDP is not preceded + by a NPDA filter pass frame, the only other setting that + could appear here for the NDP is rxpcu_monitor_other. + (rxpcu has a configuration bit specifically for this scenario) + + + Note: for + +*/ + +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + + +/* Description SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. This + field indicates to what sw classification this MPDU is + mapped. + The classification is given in priority order + + Note: The corresponding + Rxpcu_Mpdu_filter_in_category can be rxpcu_filter_pass + or rxpcu_monitor_other + + + + This includes mpdus of + type Data Null. + This includes QoS + Null frames except in UL MU or TB PPDUs. + This includes + QoS Null frames in UL MU or TB PPDUs. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + Note: The corresponding Rxpcu_Mpdu_filter_in_category can + only be rxpcu_monitor_other + + PHY reported an error + + Note: The corresponding Rxpcu_Mpdu_filter_in_category can + be rxpcu_filter_pass + + +*/ + +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc + + +/* Description NDP_FRAME + + When set, the received frame was an NDP frame, and thus + there will be no MPDU data. + TODO: Should this be extended to 2-bit e-num? + +*/ + +#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x00000024 +#define RX_MPDU_INFO_NDP_FRAME_LSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 + + +/* Description PHY_ERR + + When set, a PHY error was received before MAC received any + data, and thus there will be no MPDU data. + +*/ + +#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_PHY_ERR_LSB 10 +#define RX_MPDU_INFO_PHY_ERR_MSB 10 +#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 + + +/* Description PHY_ERR_DURING_MPDU_HEADER + + When set, a PHY error was received before MAC received the + complete MPDU header which was needed for proper decoding + + +*/ + +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + + +/* Description PROTOCOL_VERSION_ERR + + Set when RXPCU detected a version error in the Frame control + field + +*/ + +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 + + +/* Description AST_BASED_LOOKUP_VALID + + When set, AST based lookup for this frame has found a valid + result. + + Note that for NDP frame this will never be set + +*/ + +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + + +/* Description RANGING + + When set, a ranging NDPA or a ranging NDP was received. + + This field is only for FW visibility. HW is not expected + to take any action on this. + +*/ + +#define RX_MPDU_INFO_RANGING_OFFSET 0x00000024 +#define RX_MPDU_INFO_RANGING_LSB 14 +#define RX_MPDU_INFO_RANGING_MSB 14 +#define RX_MPDU_INFO_RANGING_MASK 0x00004000 + + +/* Description RESERVED_9A + + +*/ + +#define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x00000024 +#define RX_MPDU_INFO_RESERVED_9A_LSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 + + +/* Description AST_INDEX + + This field indicates the index of the AST entry corresponding + to this MPDU. It is provided by the GSE module instantiated + in RXPCU. + A value of 0xFFFF indicates an invalid AST index, meaning + that No AST entry was found or NO AST search was performed + + + In case of ndp or phy_err, this field will be set to 0xFFFF + + +*/ + +#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_INFO_AST_INDEX_LSB 0 +#define RX_MPDU_INFO_AST_INDEX_MSB 15 +#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff + + +/* Description SW_PEER_ID + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + This field indicates a unique peer identifier. It is set + equal to field 'sw_peer_id' from the AST entry + + +*/ + +#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_INFO_SW_PEER_ID_LSB 16 +#define RX_MPDU_INFO_SW_PEER_ID_MSB 31 +#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 + + +/* Description MPDU_FRAME_CONTROL_VALID + + When set, the field Mpdu_Frame_control_field has valid information + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + + +/* Description MPDU_DURATION_VALID + + When set, the field Mpdu_duration_field has valid information + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 + + +/* Description MAC_ADDR_AD1_VALID + + When set, the fields mac_addr_ad1_..... have valid information + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 + + +/* Description MAC_ADDR_AD2_VALID + + When set, the fields mac_addr_ad2_..... have valid information + + + For MPDUs without Address 2, this field will not be set. + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 + + +/* Description MAC_ADDR_AD3_VALID + + When set, the fields mac_addr_ad3_..... have valid information + + + For MPDUs without Address 3, this field will not be set. + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 + + +/* Description MAC_ADDR_AD4_VALID + + When set, the fields mac_addr_ad4_..... have valid information + + + For MPDUs without Address 4, this field will not be set. + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 + + +/* Description MPDU_SEQUENCE_CONTROL_VALID + + When set, the fields mpdu_sequence_control_field and mpdu_sequence_number + have valid information as well as field + + For MPDUs without a sequence control field, this field will + not be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the field mpdu_qos_control_field has valid information + + + For MPDUs without a QoS control field, this field will not + be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + + +/* Description MPDU_HT_CONTROL_VALID + + When set, the field mpdu_HT_control_field has valid information + + + For MPDUs without a HT control field, this field will not + be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + + +/* Description FRAME_ENCRYPTION_INFO_VALID + + When set, the encryption related info fields, like IV and + PN are valid + + For MPDUs that are not encrypted, this will not be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + + +/* Description MPDU_FRAGMENT_NUMBER + + Field only valid when Mpdu_sequence_control_valid is set + AND Fragment_flag is set + + The fragment number from the 802.11 header + + +*/ + +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description RESERVED_11A + + +*/ + +#define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x0000002c +#define RX_MPDU_INFO_RESERVED_11A_LSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 + + +/* Description FR_DS + + Field only valid when Mpdu_frame_control_valid is set + + Set if the from DS bit is set in the frame control. + +*/ + +#define RX_MPDU_INFO_FR_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_FR_DS_LSB 16 +#define RX_MPDU_INFO_FR_DS_MSB 16 +#define RX_MPDU_INFO_FR_DS_MASK 0x00010000 + + +/* Description TO_DS + + Field only valid when Mpdu_frame_control_valid is set + + Set if the to DS bit is set in the frame control. + +*/ + +#define RX_MPDU_INFO_TO_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_TO_DS_LSB 17 +#define RX_MPDU_INFO_TO_DS_MSB 17 +#define RX_MPDU_INFO_TO_DS_MASK 0x00020000 + + +/* Description ENCRYPTED + + Field only valid when Mpdu_frame_control_valid is set. + + Protected bit from the frame control. + +*/ + +#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x0000002c +#define RX_MPDU_INFO_ENCRYPTED_LSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 + + +/* Description MPDU_RETRY + + Field only valid when Mpdu_frame_control_valid is set. + + Retry bit from the frame control. Only valid when first_msdu + is set. + +*/ + +#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_RETRY_LSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 + + +/* Description MPDU_SEQUENCE_NUMBER + + Field only valid when Mpdu_sequence_control_valid is set. + + + The sequence number from the 802.11 header. + +*/ + +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + + +/* Description KEY_ID_OCTET + + Field only valid when Frame_encryption_info_valid is set + + + The key ID octet from the IV. + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + +*/ + +#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff + + +/* Description NEW_PEER_ENTRY + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY + doesn't follow so RX DECRYPTION module either uses old + peer entry or not decrypt. + +*/ + +#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 + + +/* Description DECRYPT_NEEDED + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Set if decryption is needed. + + Note: + When RXPCU sets bit 'ast_index_not_found' and/or ast_index_timeout', + RXPCU will also ensure that this bit is NOT set + CRYPTO for that reason only needs to evaluate this bit and + non of the other ones. + +*/ + +#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 + + +/* Description DECAP_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Used by the OLE during decapsulation. + + Indicates the decapsulation that HW will perform: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECAP_TYPE_LSB 10 +#define RX_MPDU_INFO_DECAP_TYPE_MSB 11 +#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 + + +/* Description RX_INSERT_VLAN_C_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Insert 4 byte of all zeros as VLAN tag if the rx payload + does not have VLAN. Used during decapsulation. + +*/ + +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + + +/* Description RX_INSERT_VLAN_S_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Insert 4 byte of all zeros as double VLAN tag if the rx + payload does not have VLAN. Used during + +*/ + +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + + +/* Description STRIP_VLAN_C_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Strip the VLAN during decapsulation. Used by the OLE. + +*/ + +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + + +/* Description STRIP_VLAN_S_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Strip the double VLAN during decapsulation. Used by the + OLE. + +*/ + +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + + +/* Description PRE_DELIM_COUNT + + The number of delimiters before this MPDU. + + Note that this number is cleared at PPDU start. + + If this MPDU is the first received MPDU in the PPDU and + this MPDU gets filtered-in, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + If this MPDU is located after the first received MPDU in + an PPDU, this field will indicate the number of delimiters + located between the previous MPDU and this MPDU. + + In case of ndp or phy_err, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + +*/ + +#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 + + +/* Description AMPDU_FLAG + + When set, received frame was part of an A-MPDU. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 + + +/* Description BAR_FRAME + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, received frame is a BAR frame + +*/ + +#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_INFO_BAR_FRAME_LSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 + + +/* Description RAW_MPDU + + Consumer: SW + Producer: RXOLE + + RXPCU sets this field to 0 and RXOLE overwrites it. + + Set to 1 by RXOLE when it has not performed any 802.11 to + Ethernet/Natvie WiFi header conversion on this MPDU. + +*/ + +#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_INFO_RAW_MPDU_LSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 + + +/* Description RESERVED_12 + + +*/ + +#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_INFO_RESERVED_12_LSB 31 +#define RX_MPDU_INFO_RESERVED_12_MSB 31 +#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 + + +/* Description MPDU_LENGTH + + In case of ndp or phy_err this field will be set to 0 + + MPDU length before decapsulation. + +*/ + +#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 +#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 +#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff + + +/* Description FIRST_MPDU + + See definition in RX attention descriptor + + In case of ndp or phy_err, this field will be set. Note + however that there will not actually be any data contents + in the MPDU. + +*/ + +#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_INFO_FIRST_MPDU_LSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 + + +/* Description MCAST_BCAST + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_INFO_MCAST_BCAST_LSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 + + +/* Description AST_INDEX_NOT_FOUND + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 + + +/* Description AST_INDEX_TIMEOUT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 + + +/* Description POWER_MGMT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_INFO_POWER_MGMT_LSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 + + +/* Description NON_QOS + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 1 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_INFO_NON_QOS_LSB 19 +#define RX_MPDU_INFO_NON_QOS_MSB 19 +#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 + + +/* Description NULL_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_NULL_DATA_LSB 20 +#define RX_MPDU_INFO_NULL_DATA_MSB 20 +#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 + + +/* Description MGMT_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_MGMT_TYPE_LSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 + + +/* Description CTRL_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_CTRL_TYPE_LSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 + + +/* Description MORE_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_MORE_DATA_LSB 23 +#define RX_MPDU_INFO_MORE_DATA_MSB 23 +#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 + + +/* Description EOSP + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 +#define RX_MPDU_INFO_EOSP_LSB 24 +#define RX_MPDU_INFO_EOSP_MSB 24 +#define RX_MPDU_INFO_EOSP_MASK 0x01000000 + + +/* Description FRAGMENT_FLAG + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 + + +/* Description ORDER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + + +*/ + +#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 +#define RX_MPDU_INFO_ORDER_LSB 26 +#define RX_MPDU_INFO_ORDER_MSB 26 +#define RX_MPDU_INFO_ORDER_MASK 0x04000000 + + +/* Description U_APSD_TRIGGER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 + + +/* Description ENCRYPT_REQUIRED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 + + +/* Description DIRECTED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_INFO_DIRECTED_LSB 29 +#define RX_MPDU_INFO_DIRECTED_MSB 29 +#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 + + +/* Description AMSDU_PRESENT + + Field only valid when Mpdu_qos_control_valid is set + + The 'amsdu_present' bit within the QoS control field of + the MPDU + +*/ + +#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 + + +/* Description RESERVED_13 + + Field only valid when Mpdu_qos_control_valid is set + + This indicates whether the 'Ack policy' field within the + QoS control field of the MPDU indicates 'no-Ack.' + +*/ + +#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_INFO_RESERVED_13_LSB 31 +#define RX_MPDU_INFO_RESERVED_13_MSB 31 +#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 + + +/* Description MPDU_FRAME_CONTROL_FIELD + + Field only valid when Mpdu_frame_control_valid is set + + The frame control field of this received MPDU. + + Field only valid when Ndp_frame and phy_err are NOT set + + Bytes 0 + 1 of the received MPDU + +*/ + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + + +/* Description MPDU_DURATION_FIELD + + Field only valid when Mpdu_duration_valid is set + + The duration field of this received MPDU. + +*/ + +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 + + +/* Description MAC_ADDR_AD1_31_0 + + Field only valid when mac_addr_ad1_valid is set + + The Least Significant 4 bytes of the Received Frames MAC + Address AD1 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff + + +/* Description MAC_ADDR_AD1_47_32 + + Field only valid when mac_addr_ad1_valid is set + + The 2 most significant bytes of the Received Frames MAC + Address AD1 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + + +/* Description MAC_ADDR_AD2_15_0 + + Field only valid when mac_addr_ad2_valid is set + + The Least Significant 2 bytes of the Received Frames MAC + Address AD2 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + + +/* Description MAC_ADDR_AD2_47_16 + + Field only valid when mac_addr_ad2_valid is set + + The 4 most significant bytes of the Received Frames MAC + Address AD2 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff + + +/* Description MAC_ADDR_AD3_31_0 + + Field only valid when mac_addr_ad3_valid is set + + The Least Significant 4 bytes of the Received Frames MAC + Address AD3 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff + + +/* Description MAC_ADDR_AD3_47_32 + + Field only valid when mac_addr_ad3_valid is set + + The 2 most significant bytes of the Received Frames MAC + Address AD3 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + + +/* Description MPDU_SEQUENCE_CONTROL_FIELD + + Field only valid when mpdu_sequence_control_valid is set + + + The sequence control field of the MPDU + +*/ + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + + +/* Description MAC_ADDR_AD4_31_0 + + Field only valid when mac_addr_ad4_valid is set + + The Least Significant 4 bytes of the Received Frames MAC + Address AD4 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff + + +/* Description MAC_ADDR_AD4_47_32 + + Field only valid when mac_addr_ad4_valid is set + + The 2 most significant bytes of the Received Frames MAC + Address AD4 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + + +/* Description MPDU_QOS_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + The sequence control field of the MPDU + +*/ + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + + +/* Description MPDU_HT_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + The HT control field of the MPDU + +*/ + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + + +/* Description VDEV_ID + + Consumer: RXOLE + Producer: FW + + Virtual device associated with this peer + + RXOLE uses this to determine intra-BSS routing. + + +*/ + +#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c +#define RX_MPDU_INFO_VDEV_ID_LSB 0 +#define RX_MPDU_INFO_VDEV_ID_MSB 7 +#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MPDU_INFO_SERVICE_CODE_LSB 8 +#define RX_MPDU_INFO_SERVICE_CODE_MSB 16 +#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c +#define RX_MPDU_INFO_SRC_INFO_LSB 18 +#define RX_MPDU_INFO_SRC_INFO_MSB 29 +#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 + + +/* Description RESERVED_23A + + +*/ + +#define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c +#define RX_MPDU_INFO_RESERVED_23A_LSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 + + +/* Description MULTI_LINK_ADDR_AD1_AD2_VALID + + If set, Rx OLE shall convert Address1 and Address2 of received + data frames to multi-link addresses during decapsulation + to Ethernet or Native WiFi + +*/ + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000005c +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x80000000 + + +/* Description MULTI_LINK_ADDR_AD1_31_0 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link receiver address (address1), bits [31:0] +*/ + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x00000060 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MASK 0xffffffff + + +/* Description MULTI_LINK_ADDR_AD1_47_32 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link receiver address (address1), bits [47:32] +*/ + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x00000064 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff + + +/* Description MULTI_LINK_ADDR_AD2_15_0 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link transmitter address (address2), bits [15:0] +*/ + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x00000064 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff0000 + + +/* Description MULTI_LINK_ADDR_AD2_47_16 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link transmitter address (address2), bits [47:16] +*/ + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x00000068 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MASK 0xffffffff + + +/* Description AUTHORIZED_TO_SEND_WDS + + If not set, RXDMA shall perform error-routing for WDS packets + as the sender is not authorized and might misuse WDS frame + format to inject packets with arbitrary DA/SA. + +*/ + +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 + + +/* Description RESERVED_27A + + Bit 1: disallow_mcbc_da_in_unicast_mpdu: + + If set, RX OLE shall disallow multicast/broadcast DA in + A-MSDU subframes in case of ToDS=0 MPDUs. This may be enabled + for TDLS peers. + +*/ + +#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_MPDU_INFO_RESERVED_27A_LSB 1 +#define RX_MPDU_INFO_RESERVED_27A_MSB 31 +#define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe + + +/* Description RESERVED_28A + + +*/ + +#define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 +#define RX_MPDU_INFO_RESERVED_28A_LSB 0 +#define RX_MPDU_INFO_RESERVED_28A_MSB 31 +#define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff + + +/* Description RESERVED_29A + + +*/ + +#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 +#define RX_MPDU_INFO_RESERVED_29A_LSB 0 +#define RX_MPDU_INFO_RESERVED_29A_MSB 31 +#define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff + + + +#endif // RX_MPDU_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_link_ptr.h new file mode 100644 index 0000000000000000000000000000000000000000..06455b63151ed8cda73fdc7cef75060a6abced7e --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_link_ptr.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MPDU_LINK_PTR_H_ +#define _RX_MPDU_LINK_PTR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 + + +struct rx_mpdu_link_ptr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info mpdu_link_desc_addr_info; +#else + struct buffer_addr_info mpdu_link_desc_addr_info; +#endif +}; + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif // RX_MPDU_LINK_PTR diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_start.h b/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..46b9f167c25aecf92dc4ebcb346749f90b89d8b4 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_mpdu_start.h @@ -0,0 +1,2207 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MPDU_START_H_ +#define _RX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_info.h" +#define NUM_OF_DWORDS_RX_MPDU_START 30 + +#define NUM_OF_QWORDS_RX_MPDU_START 15 + + +struct rx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_info rx_mpdu_info_details; +#else + struct rx_mpdu_info rx_mpdu_info_details; +#endif +}; + + +/* Description RX_MPDU_INFO_DETAILS + + Structure containing all the MPDU header details that might + be needed for other modules further down the received path + +*/ + + +/* Description RXPT_CLASSIFY_INFO_DETAILS + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + RXOLE related classification info + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f + + +/* Description LMAC_PEER_ID_MSB + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb + is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, + hash[3:0]} using the chosen Toeplitz hash from Common Parser + if flow search fails. + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb + 's not 2'b00, Rx OLE uses a REO desination indication of + {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz + hash from Common Parser if flow search fails. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060 + + +/* Description USE_FLOW_ID_TOEPLITZ_CLFY + + Indication to Rx OLE to enable REO destination routing based + on the chosen Toeplitz hash from Common Parser, in case + flow search fails + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080 + + +/* Description PKT_SELECTION_FP_UCAST_DATA + + Filter pass Unicast data frame (matching rxpcu_filter_pass + and sw_frame_group_Unicast_data) routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100 + + +/* Description PKT_SELECTION_FP_MCAST_DATA + + Filter pass Multicast data frame (matching rxpcu_filter_pass + and sw_frame_group_Multicast_data) routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200 + + +/* Description PKT_SELECTION_FP_1000 + + Filter pass BAR frame (matching rxpcu_filter_pass and sw_frame_group_ctrl_1000) + routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400 + + +/* Description RXDMA0_SOURCE_RING_SELECTION + + Field only valid when for the received frame type the corresponding + pkt_selection_fp_... bit is set + + The data buffer for + this frame shall be sourced by sw2rxdma0 buffer source + ring. + The data buffer + for this frame shall be sourced by fw2rxdma buffer source + ring for PMAC0. + The data buffer for + this frame shall be sourced by sw2rxdma1 buffer source + ring. + The frame shall not be written + to any data buffer. + The data buffer + for this frame shall be sourced by sw2rxdma_exception buffer + source ring. + The data buffer + for this frame shall be sourced by fw2rxdma buffer source + ring for PMAC1. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800 + + +/* Description RXDMA0_DESTINATION_RING_SELECTION + + Field only valid when for the received frame type the corresponding + pkt_selection_fp_... bit is set + + RXDMA0 shall push the frame + to the Release ring. Effectively this means the frame needs + to be dropped. + RXDMA0 shall push the frame + to the FW ring for PMAC0. + RXDMA0 shall push the frame to the + SW ring. + RXDMA0 shall push the frame to + the REO entrance ring. + RXDMA0 shall push the frame + to the FW ring for PMAC1. + RXDMA0 shall push the frame + to the first MLO REO entrance ring. + RXDMA0 shall push the frame + to the second MLO REO entrance ring. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000 + + +/* Description MCAST_ECHO_DROP_ENABLE + + If set, for multicast packets, multicast echo check (i.e. + SA search with mcast_echo_check = 1) shall be performed + by RXOLE, and any multicast echo packets should be indicated + to RXDMA for release to WBM + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000 + + +/* Description WDS_LEARNING_DETECT_EN + + If set, WDS learning detection based on SA search and notification + to FW (using RXDMA0 status ring) is enabled and the "timestamp" + field in address search failure cache-only entry should + be used to avoid multiple WDS learning notifications. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000 + + +/* Description INTRABSS_CHECK_EN + + If set, intra-BSS routing detection is enabled + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000 + + +/* Description USE_PPE + + Indicates to RXDMA to ignore the REO_destination_indication + and use a programmed value corresponding to the REO2PPE + ring + + This override to REO2PPE for packets requiring multiple + buffers shall be disabled based on an RXDMA configuration, + as PPE may not support such packets. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x0000000000100000 + + +/* Description PPE_ROUTING_ENABLE + + Global enable/disable bit for routing to PPE, used to disable + PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE' + + + This is set by SW for peers which are being handled by a + host SW/accelerator subsystem that also handles packet + buffer management for WiFi-to-PPE routing. + + This is cleared by SW for peers which are being handled + by a different subsystem, completely disabling WiFi-to-PPE + routing for such peers. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000 + + +/* Description RESERVED_0B + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ffc00000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_31_0 + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Address (lower 32 bits) of the REO queue descriptor. + + If no Peer entry lookup happened for this frame, the value + wil be set to 0, and the frame shall never be pushed to + REO entrance ring. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_39_32 + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Address (upper 8 bits) of the REO queue descriptor. + + If no Peer entry lookup happened for this frame, the value + wil be set to 0, and the frame shall never be pushed to + REO entrance ring. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff + + +/* Description RECEIVE_QUEUE_NUMBER + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Indicates the MPDU queue ID to which this MPDU link descriptor + belongs + Used for tracking and debugging + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000ffff00 + + +/* Description PRE_DELIM_ERR_WARNING + + Indicates that a delimiter FCS error was found in between + the Previous MPDU and this MPDU. + + Note that this is just a warning, and does not mean that + this MPDU is corrupted in any way. If it is, there will + be other errors indicated such as FCS or decrypt errors + + + In case of ndp or phy_err, this field will indicate at least + one of delimiters located after the last MPDU in the previous + PPDU has been corrupted. +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x0000000001000000 + + +/* Description FIRST_DELIM_ERR + + Indicates that the first delimiter had a FCS failure. Only + valid when first_mpdu and first_msdu are set. + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x0000000002000000 + + +/* Description RESERVED_2A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0x00000000fc000000 + + +/* Description PN_31_0 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [31:0] of the PN number extracted from the IV field + + WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] + is valid. + TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, WEPSeed[1], + pn1}. Only pn[47:0] is valid. + AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1, + pn0}. Only pn[47:0] is valid. + WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11, + pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}. + pn[127:0] are valid. + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff00000000 + + +/* Description PN_63_32 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [63:32] of the PN number. See description for pn_31_0. + + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x0000000000000010 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0x00000000ffffffff + + +/* Description PN_95_64 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [95:64] of the PN number. See description for pn_31_0. + + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x0000000000000010 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff00000000 + + +/* Description PN_127_96 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [127:96] of the PN number. See description for pn_31_0. + + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0x00000000ffffffff + + +/* Description EPD_EN + + Field only valid when AST_based_lookup_valid == 1. + + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + If set to one use EPD instead of LPD + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x0000000100000000 + + +/* Description ALL_FRAMES_SHALL_BE_ENCRYPTED + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, all frames (data only ?) shall be encrypted. If + not, RX CRYPTO shall set an error flag. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x0000000200000000 + + +/* Description ENCRYPT_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + WEP 40-bit + WEP 104-bit + TKIP without MIC + WEP 128-bit + TKIP with MIC + WAPI + AES CCMP 128 + No crypto + AES CCMP 256 + AES CCMP 128 + AES CCMP 256 + WAPI GCM SM4 + + WEP encryption. As for WEP per + keyid the key bit width can vary, the key bit width for + this MPDU will be indicated in field wep_key_width_for_variable + key + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 37 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c00000000 + + +/* Description WEP_KEY_WIDTH_FOR_VARIABLE_KEY + + Field only valid when key_type is set to wep_varied_width. + + + This field indicates the size of the wep key for this MPDU. + + + WEP 40-bit + WEP 104-bit + WEP 128-bit + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 38 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c000000000 + + +/* Description MESH_STA + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, this is a Mesh (11s) STA. + + The interpretation of the A-MSDU 'Length' field in the MPDU + (if any) is decided by the e-numerations below. + + + A-MSDU 'Length' is big endian and includes + the length of Mesh Control. + A-MSDU 'Length' is big endian and excludes + the length of Mesh Control. + A-MSDU 'Length' is little endian and + excludes the length of Mesh Control. This is 802.11s-compliant. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_LSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_MSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_MASK 0x0000030000000000 + + +/* Description BSSID_HIT + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, the BSSID of the incoming frame matched one of + the 8 BSSID register values + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x0000040000000000 + + +/* Description BSSID_NUMBER + + Field only valid when bssid_hit is set. + + This number indicates which one out of the 8 BSSID register + values matched the incoming frame + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 43 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x0000780000000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x0007800000000000 + + +/* Description RESERVED_7A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff8000000000000 + + +/* Description PEER_META_DATA + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0x00000000ffffffff + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + This MPDU passed the normal frame + filter programming of rxpcu + This MPDU did NOT pass the + regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + This MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + + Note: for ndp frame, if it was expected because the preceding + NDPA was filter_pass, the setting rxpcu_filter_pass will + be used. This setting will also be used for every ndp frame + in case Promiscuous mode is enabled. + + In case promiscuous is not enabled, and an NDP is not preceded + by a NPDA filter pass frame, the only other setting that + could appear here for the NDP is rxpcu_monitor_other. + (rxpcu has a configuration bit specifically for this scenario) + + + Note: for + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000300000000 + + +/* Description SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. This + field indicates to what sw classification this MPDU is + mapped. + The classification is given in priority order + + Note: The corresponding + Rxpcu_Mpdu_filter_in_category can be rxpcu_filter_pass + or rxpcu_monitor_other + + + + This includes mpdus of + type Data Null. + This includes QoS + Null frames except in UL MU or TB PPDUs. + This includes + QoS Null frames in UL MU or TB PPDUs. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + Note: The corresponding Rxpcu_Mpdu_filter_in_category can + only be rxpcu_monitor_other + + PHY reported an error + + Note: The corresponding Rxpcu_Mpdu_filter_in_category can + be rxpcu_filter_pass + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc00000000 + + +/* Description NDP_FRAME + + When set, the received frame was an NDP frame, and thus + there will be no MPDU data. + TODO: Should this be extended to 2-bit e-num? + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x0000020000000000 + + +/* Description PHY_ERR + + When set, a PHY error was received before MAC received any + data, and thus there will be no MPDU data. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x0000040000000000 + + +/* Description PHY_ERR_DURING_MPDU_HEADER + + When set, a PHY error was received before MAC received the + complete MPDU header which was needed for proper decoding + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 43 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 43 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x0000080000000000 + + +/* Description PROTOCOL_VERSION_ERR + + Set when RXPCU detected a version error in the Frame control + field + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 44 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 44 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x0000100000000000 + + +/* Description AST_BASED_LOOKUP_VALID + + When set, AST based lookup for this frame has found a valid + result. + + Note that for NDP frame this will never be set + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x0000200000000000 + + +/* Description RANGING + + When set, a ranging NDPA or a ranging NDP was received. + + This field is only for FW visibility. HW is not expected + to take any action on this. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_LSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_MASK 0x0000400000000000 + + +/* Description RESERVED_9A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000800000000000 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff000000000000 + + +/* Description AST_INDEX + + This field indicates the index of the AST entry corresponding + to this MPDU. It is provided by the GSE module instantiated + in RXPCU. + A value of 0xFFFF indicates an invalid AST index, meaning + that No AST entry was found or NO AST search was performed + + + In case of ndp or phy_err, this field will be set to 0xFFFF + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x000000000000ffff + + +/* Description SW_PEER_ID + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + This field indicates a unique peer identifier. It is set + equal to field 'sw_peer_id' from the AST entry + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0x00000000ffff0000 + + +/* Description MPDU_FRAME_CONTROL_VALID + + When set, the field Mpdu_Frame_control_field has valid information + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x0000000100000000 + + +/* Description MPDU_DURATION_VALID + + When set, the field Mpdu_duration_field has valid information + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x0000000200000000 + + +/* Description MAC_ADDR_AD1_VALID + + When set, the fields mac_addr_ad1_..... have valid information + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x0000000400000000 + + +/* Description MAC_ADDR_AD2_VALID + + When set, the fields mac_addr_ad2_..... have valid information + + + For MPDUs without Address 2, this field will not be set. + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 35 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 35 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x0000000800000000 + + +/* Description MAC_ADDR_AD3_VALID + + When set, the fields mac_addr_ad3_..... have valid information + + + For MPDUs without Address 3, this field will not be set. + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 36 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 36 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x0000001000000000 + + +/* Description MAC_ADDR_AD4_VALID + + When set, the fields mac_addr_ad4_..... have valid information + + + For MPDUs without Address 4, this field will not be set. + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 37 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 37 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x0000002000000000 + + +/* Description MPDU_SEQUENCE_CONTROL_VALID + + When set, the fields mpdu_sequence_control_field and mpdu_sequence_number + have valid information as well as field + + For MPDUs without a sequence control field, this field will + not be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 38 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 38 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x0000004000000000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the field mpdu_qos_control_field has valid information + + + For MPDUs without a QoS control field, this field will not + be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x0000008000000000 + + +/* Description MPDU_HT_CONTROL_VALID + + When set, the field mpdu_HT_control_field has valid information + + + For MPDUs without a HT control field, this field will not + be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x0000010000000000 + + +/* Description FRAME_ENCRYPTION_INFO_VALID + + When set, the encryption related info fields, like IV and + PN are valid + + For MPDUs that are not encrypted, this will not be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x0000020000000000 + + +/* Description MPDU_FRAGMENT_NUMBER + + Field only valid when Mpdu_sequence_control_valid is set + AND Fragment_flag is set + + The fragment number from the 802.11 header + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c0000000000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x0000400000000000 + + +/* Description RESERVED_11A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x0000800000000000 + + +/* Description FR_DS + + Field only valid when Mpdu_frame_control_valid is set + + Set if the from DS bit is set in the frame control. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x0001000000000000 + + +/* Description TO_DS + + Field only valid when Mpdu_frame_control_valid is set + + Set if the to DS bit is set in the frame control. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x0002000000000000 + + +/* Description ENCRYPTED + + Field only valid when Mpdu_frame_control_valid is set. + + Protected bit from the frame control. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x0004000000000000 + + +/* Description MPDU_RETRY + + Field only valid when Mpdu_frame_control_valid is set. + + Retry bit from the frame control. Only valid when first_msdu + is set. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x0008000000000000 + + +/* Description MPDU_SEQUENCE_NUMBER + + Field only valid when Mpdu_sequence_control_valid is set. + + + The sequence number from the 802.11 header. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 52 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff0000000000000 + + +/* Description KEY_ID_OCTET + + Field only valid when Frame_encryption_info_valid is set + + + The key ID octet from the IV. + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x00000000000000ff + + +/* Description NEW_PEER_ENTRY + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY + doesn't follow so RX DECRYPTION module either uses old + peer entry or not decrypt. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x0000000000000100 + + +/* Description DECRYPT_NEEDED + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Set if decryption is needed. + + Note: + When RXPCU sets bit 'ast_index_not_found' and/or ast_index_timeout', + RXPCU will also ensure that this bit is NOT set + CRYPTO for that reason only needs to evaluate this bit and + non of the other ones. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x0000000000000200 + + +/* Description DECAP_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Used by the OLE during decapsulation. + + Indicates the decapsulation that HW will perform: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x0000000000000c00 + + +/* Description RX_INSERT_VLAN_C_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Insert 4 byte of all zeros as VLAN tag if the rx payload + does not have VLAN. Used during decapsulation. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x0000000000001000 + + +/* Description RX_INSERT_VLAN_S_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Insert 4 byte of all zeros as double VLAN tag if the rx + payload does not have VLAN. Used during + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x0000000000002000 + + +/* Description STRIP_VLAN_C_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Strip the VLAN during decapsulation. Used by the OLE. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x0000000000004000 + + +/* Description STRIP_VLAN_S_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Strip the double VLAN during decapsulation. Used by the + OLE. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x0000000000008000 + + +/* Description PRE_DELIM_COUNT + + The number of delimiters before this MPDU. + + Note that this number is cleared at PPDU start. + + If this MPDU is the first received MPDU in the PPDU and + this MPDU gets filtered-in, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + If this MPDU is located after the first received MPDU in + an PPDU, this field will indicate the number of delimiters + located between the previous MPDU and this MPDU. + + In case of ndp or phy_err, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x000000000fff0000 + + +/* Description AMPDU_FLAG + + When set, received frame was part of an A-MPDU. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x0000000010000000 + + +/* Description BAR_FRAME + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, received frame is a BAR frame + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x0000000020000000 + + +/* Description RAW_MPDU + + Consumer: SW + Producer: RXOLE + + RXPCU sets this field to 0 and RXOLE overwrites it. + + Set to 1 by RXOLE when it has not performed any 802.11 to + Ethernet/Natvie WiFi header conversion on this MPDU. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x0000000040000000 + + +/* Description RESERVED_12 + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x0000000080000000 + + +/* Description MPDU_LENGTH + + In case of ndp or phy_err this field will be set to 0 + + MPDU length before decapsulation. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff00000000 + + +/* Description FIRST_MPDU + + See definition in RX attention descriptor + + In case of ndp or phy_err, this field will be set. Note + however that there will not actually be any data contents + in the MPDU. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x0000400000000000 + + +/* Description MCAST_BCAST + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x0000800000000000 + + +/* Description AST_INDEX_NOT_FOUND + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x0001000000000000 + + +/* Description AST_INDEX_TIMEOUT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x0002000000000000 + + +/* Description POWER_MGMT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x0004000000000000 + + +/* Description NON_QOS + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 1 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x0008000000000000 + + +/* Description NULL_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 52 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 52 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x0010000000000000 + + +/* Description MGMT_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 53 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 53 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x0020000000000000 + + +/* Description CTRL_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 54 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 54 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x0040000000000000 + + +/* Description MORE_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 55 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 55 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x0080000000000000 + + +/* Description EOSP + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 56 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 56 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x0100000000000000 + + +/* Description FRAGMENT_FLAG + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 57 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 57 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x0200000000000000 + + +/* Description ORDER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 58 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 58 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x0400000000000000 + + +/* Description U_APSD_TRIGGER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 59 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 59 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x0800000000000000 + + +/* Description ENCRYPT_REQUIRED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 60 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 60 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x1000000000000000 + + +/* Description DIRECTED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 61 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 61 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x2000000000000000 + + +/* Description AMSDU_PRESENT + + Field only valid when Mpdu_qos_control_valid is set + + The 'amsdu_present' bit within the QoS control field of + the MPDU + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x4000000000000000 + + +/* Description RESERVED_13 + + Field only valid when Mpdu_qos_control_valid is set + + This indicates whether the 'Ack policy' field within the + QoS control field of the MPDU indicates 'no-Ack.' + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x8000000000000000 + + +/* Description MPDU_FRAME_CONTROL_FIELD + + Field only valid when Mpdu_frame_control_valid is set + + The frame control field of this received MPDU. + + Field only valid when Ndp_frame and phy_err are NOT set + + Bytes 0 + 1 of the received MPDU + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x000000000000ffff + + +/* Description MPDU_DURATION_FIELD + + Field only valid when Mpdu_duration_valid is set + + The duration field of this received MPDU. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x0000000000000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0x00000000ffff0000 + + +/* Description MAC_ADDR_AD1_31_0 + + Field only valid when mac_addr_ad1_valid is set + + The Least Significant 4 bytes of the Received Frames MAC + Address AD1 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000000000000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff00000000 + + +/* Description MAC_ADDR_AD1_47_32 + + Field only valid when mac_addr_ad1_valid is set + + The 2 most significant bytes of the Received Frames MAC + Address AD1 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x0000000000000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x000000000000ffff + + +/* Description MAC_ADDR_AD2_15_0 + + Field only valid when mac_addr_ad2_valid is set + + The Least Significant 2 bytes of the Received Frames MAC + Address AD2 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x0000000000000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0x00000000ffff0000 + + +/* Description MAC_ADDR_AD2_47_16 + + Field only valid when mac_addr_ad2_valid is set + + The 4 most significant bytes of the Received Frames MAC + Address AD2 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x0000000000000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff00000000 + + +/* Description MAC_ADDR_AD3_31_0 + + Field only valid when mac_addr_ad3_valid is set + + The Least Significant 4 bytes of the Received Frames MAC + Address AD3 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x0000000000000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0x00000000ffffffff + + +/* Description MAC_ADDR_AD3_47_32 + + Field only valid when mac_addr_ad3_valid is set + + The 2 most significant bytes of the Received Frames MAC + Address AD3 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000000000000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff00000000 + + +/* Description MPDU_SEQUENCE_CONTROL_FIELD + + Field only valid when mpdu_sequence_control_valid is set + + + The sequence control field of the MPDU + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000000000000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff000000000000 + + +/* Description MAC_ADDR_AD4_31_0 + + Field only valid when mac_addr_ad4_valid is set + + The Least Significant 4 bytes of the Received Frames MAC + Address AD4 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x0000000000000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0x00000000ffffffff + + +/* Description MAC_ADDR_AD4_47_32 + + Field only valid when mac_addr_ad4_valid is set + + The 2 most significant bytes of the Received Frames MAC + Address AD4 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x0000000000000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff00000000 + + +/* Description MPDU_QOS_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + The sequence control field of the MPDU + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x0000000000000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff000000000000 + + +/* Description MPDU_HT_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + The HT control field of the MPDU + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0x00000000ffffffff + + +/* Description VDEV_ID + + Consumer: RXOLE + Producer: FW + + Virtual device associated with this peer + + RXOLE uses this to determine intra-BSS routing. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff00000000 + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff0000000000 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x0002000000000000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 61 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc000000000000 + + +/* Description RESERVED_23A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK 0x4000000000000000 + + +/* Description MULTI_LINK_ADDR_AD1_AD2_VALID + + If set, Rx OLE shall convert Address1 and Address2 of received + data frames to multi-link addresses during decapsulation + to Ethernet or Native WiFi + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x8000000000000000 + + +/* Description MULTI_LINK_ADDR_AD1_31_0 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link receiver address (address1), bits [31:0] +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x0000000000000060 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_MASK 0x00000000ffffffff + + +/* Description MULTI_LINK_ADDR_AD1_47_32 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link receiver address (address1), bits [47:32] +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x0000000000000060 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff00000000 + + +/* Description MULTI_LINK_ADDR_AD2_15_0 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link transmitter address (address2), bits [15:0] +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x0000000000000060 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff000000000000 + + +/* Description MULTI_LINK_ADDR_AD2_47_16 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link transmitter address (address2), bits [47:16] +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x0000000000000068 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_MASK 0x00000000ffffffff + + +/* Description AUTHORIZED_TO_SEND_WDS + + If not set, RXDMA shall perform error-routing for WDS packets + as the sender is not authorized and might misuse WDS frame + format to inject packets with arbitrary DA/SA. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000000000000068 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x0000000100000000 + + +/* Description RESERVED_27A + + Bit 1: disallow_mcbc_da_in_unicast_mpdu: + + If set, RX OLE shall disallow multicast/broadcast DA in + A-MSDU subframes in case of ToDS=0 MPDUs. This may be enabled + for TDLS peers. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xfffffffe00000000 + + +/* Description RESERVED_28A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_OFFSET 0x0000000000000070 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MASK 0x00000000ffffffff + + +/* Description RESERVED_29A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x0000000000000070 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xffffffff00000000 + + + +#endif // RX_MPDU_START diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/qcn6432/rx_msdu_desc_info.h new file mode 100644 index 0000000000000000000000000000000000000000..1b1c8691b9024668029f960bba8d583be80ac176 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_msdu_desc_info.h @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MSDU_DESC_INFO_H_ +#define _RX_MSDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 + + +struct rx_msdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t first_msdu_in_mpdu_flag : 1, // [0:0] + last_msdu_in_mpdu_flag : 1, // [1:1] + msdu_continuation : 1, // [2:2] + msdu_length : 14, // [16:3] + msdu_drop : 1, // [17:17] + sa_is_valid : 1, // [18:18] + da_is_valid : 1, // [19:19] + da_is_mcbc : 1, // [20:20] + l3_header_padding_msb : 1, // [21:21] + tcp_udp_chksum_fail : 1, // [22:22] + ip_chksum_fail : 1, // [23:23] + fr_ds : 1, // [24:24] + to_ds : 1, // [25:25] + intra_bss : 1, // [26:26] + dest_chip_id : 2, // [28:27] + decap_format : 2, // [30:29] + dest_chip_pmac_id : 1; // [31:31] +#else + uint32_t dest_chip_pmac_id : 1, // [31:31] + decap_format : 2, // [30:29] + dest_chip_id : 2, // [28:27] + intra_bss : 1, // [26:26] + to_ds : 1, // [25:25] + fr_ds : 1, // [24:24] + ip_chksum_fail : 1, // [23:23] + tcp_udp_chksum_fail : 1, // [22:22] + l3_header_padding_msb : 1, // [21:21] + da_is_mcbc : 1, // [20:20] + da_is_valid : 1, // [19:19] + sa_is_valid : 1, // [18:18] + msdu_drop : 1, // [17:17] + msdu_length : 14, // [16:3] + msdu_continuation : 1, // [2:2] + last_msdu_in_mpdu_flag : 1, // [1:1] + first_msdu_in_mpdu_flag : 1; // [0:0] +#endif +}; + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FR_DS_LSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TO_DS_LSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + + +#endif // RX_MSDU_DESC_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_msdu_details.h b/drivers/staging/fw-api/hw/qcn6432/rx_msdu_details.h new file mode 100644 index 0000000000000000000000000000000000000000..2ff3a4725e0dbf36be783ced7947c9d0cec7942d --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_msdu_details.h @@ -0,0 +1,642 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MSDU_DETAILS_H_ +#define _RX_MSDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_msdu_ext_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 + + +struct rx_msdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#else + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#endif +}; + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + + +#endif // RX_MSDU_DETAILS diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_msdu_end.h b/drivers/staging/fw-api/hw/qcn6432/rx_msdu_end.h new file mode 100644 index 0000000000000000000000000000000000000000..c3d6ae8910527ed6649b138ec4efde40e06dfc06 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_msdu_end.h @@ -0,0 +1,2439 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MSDU_END_H_ +#define _RX_MSDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_END 32 + +#define NUM_OF_QWORDS_RX_MSDU_END 16 + + +struct rx_msdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] + sw_frame_group_id : 7, // [8:2] + reserved_0 : 7, // [15:9] + phy_ppdu_id : 16; // [31:16] + uint32_t ip_hdr_chksum : 16, // [15:0] + reported_mpdu_length : 14, // [29:16] + reserved_1a : 2; // [31:30] + uint32_t reserved_2a : 8, // [7:0] + cce_super_rule : 6, // [13:8] + cce_classify_not_done_truncate : 1, // [14:14] + cce_classify_not_done_cce_dis : 1, // [15:15] + cumulative_l3_checksum : 16; // [31:16] + uint32_t rule_indication_31_0 : 32; // [31:0] + uint32_t ipv6_options_crc : 32; // [31:0] + uint32_t da_offset : 6, // [5:0] + sa_offset : 6, // [11:6] + da_offset_valid : 1, // [12:12] + sa_offset_valid : 1, // [13:13] + reserved_5a : 2, // [15:14] + l3_type : 16; // [31:16] + uint32_t rule_indication_63_32 : 32; // [31:0] + uint32_t tcp_seq_number : 32; // [31:0] + uint32_t tcp_ack_number : 32; // [31:0] + uint32_t tcp_flag : 9, // [8:0] + lro_eligible : 1, // [9:9] + reserved_9a : 6, // [15:10] + window_size : 16; // [31:16] + uint32_t sa_sw_peer_id : 16, // [15:0] + sa_idx_timeout : 1, // [16:16] + da_idx_timeout : 1, // [17:17] + to_ds : 1, // [18:18] + tid : 4, // [22:19] + sa_is_valid : 1, // [23:23] + da_is_valid : 1, // [24:24] + da_is_mcbc : 1, // [25:25] + l3_header_padding : 2, // [27:26] + first_msdu : 1, // [28:28] + last_msdu : 1, // [29:29] + fr_ds : 1, // [30:30] + ip_chksum_fail_copy : 1; // [31:31] + uint32_t sa_idx : 16, // [15:0] + da_idx_or_sw_peer_id : 16; // [31:16] + uint32_t msdu_drop : 1, // [0:0] + reo_destination_indication : 5, // [5:1] + flow_idx : 20, // [25:6] + use_ppe : 1, // [26:26] + mesh_sta : 2, // [28:27] + vlan_ctag_stripped : 1, // [29:29] + vlan_stag_stripped : 1, // [30:30] + fragment_flag : 1; // [31:31] + uint32_t fse_metadata : 32; // [31:0] + uint32_t cce_metadata : 16, // [15:0] + tcp_udp_chksum : 16; // [31:16] + uint32_t aggregation_count : 8, // [7:0] + flow_aggregation_continuation : 1, // [8:8] + fisa_timeout : 1, // [9:9] + tcp_udp_chksum_fail_copy : 1, // [10:10] + msdu_limit_error : 1, // [11:11] + flow_idx_timeout : 1, // [12:12] + flow_idx_invalid : 1, // [13:13] + cce_match : 1, // [14:14] + amsdu_parser_error : 1, // [15:15] + cumulative_ip_length : 16; // [31:16] + uint32_t key_id_octet : 8, // [7:0] + reserved_16a : 24; // [31:8] + uint32_t reserved_17a : 6, // [5:0] + service_code : 9, // [14:6] + priority_valid : 1, // [15:15] + intra_bss : 1, // [16:16] + dest_chip_id : 2, // [18:17] + multicast_echo : 1, // [19:19] + wds_learning_event : 1, // [20:20] + wds_roaming_event : 1, // [21:21] + wds_keep_alive_event : 1, // [22:22] + dest_chip_pmac_id : 1, // [23:23] + reserved_17b : 8; // [31:24] + uint32_t msdu_length : 14, // [13:0] + stbc : 1, // [14:14] + ipsec_esp : 1, // [15:15] + l3_offset : 7, // [22:16] + ipsec_ah : 1, // [23:23] + l4_offset : 8; // [31:24] + uint32_t msdu_number : 8, // [7:0] + decap_format : 2, // [9:8] + ipv4_proto : 1, // [10:10] + ipv6_proto : 1, // [11:11] + tcp_proto : 1, // [12:12] + udp_proto : 1, // [13:13] + ip_frag : 1, // [14:14] + tcp_only_ack : 1, // [15:15] + da_is_bcast_mcast : 1, // [16:16] + toeplitz_hash_sel : 2, // [18:17] + ip_fixed_header_valid : 1, // [19:19] + ip_extn_header_valid : 1, // [20:20] + tcp_udp_header_valid : 1, // [21:21] + mesh_control_present : 1, // [22:22] + ldpc : 1, // [23:23] + ip4_protocol_ip6_next_header : 8; // [31:24] + uint32_t vlan_ctag_ci : 16, // [15:0] + vlan_stag_ci : 16; // [31:16] + uint32_t peer_meta_data : 32; // [31:0] + uint32_t user_rssi : 8, // [7:0] + pkt_type : 4, // [11:8] + sgi : 2, // [13:12] + rate_mcs : 4, // [17:14] + receive_bandwidth : 3, // [20:18] + reception_type : 3, // [23:21] + mimo_ss_bitmap : 7, // [30:24] + msdu_done_copy : 1; // [31:31] + uint32_t flow_id_toeplitz : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] + uint32_t reserved_28a : 16, // [15:0] + sa_15_0 : 16; // [31:16] + uint32_t sa_47_16 : 32; // [31:0] + uint32_t first_mpdu : 1, // [0:0] + reserved_30a : 1, // [1:1] + mcast_bcast : 1, // [2:2] + ast_index_not_found : 1, // [3:3] + ast_index_timeout : 1, // [4:4] + power_mgmt : 1, // [5:5] + non_qos : 1, // [6:6] + null_data : 1, // [7:7] + mgmt_type : 1, // [8:8] + ctrl_type : 1, // [9:9] + more_data : 1, // [10:10] + eosp : 1, // [11:11] + a_msdu_error : 1, // [12:12] + reserved_30b : 1, // [13:13] + order : 1, // [14:14] + wifi_parser_error : 1, // [15:15] + overflow_err : 1, // [16:16] + msdu_length_err : 1, // [17:17] + tcp_udp_chksum_fail : 1, // [18:18] + ip_chksum_fail : 1, // [19:19] + sa_idx_invalid : 1, // [20:20] + da_idx_invalid : 1, // [21:21] + amsdu_addr_mismatch : 1, // [22:22] + rx_in_tx_decrypt_byp : 1, // [23:23] + encrypt_required : 1, // [24:24] + directed : 1, // [25:25] + buffer_fragment : 1, // [26:26] + mpdu_length_err : 1, // [27:27] + tkip_mic_err : 1, // [28:28] + decrypt_err : 1, // [29:29] + unencrypted_frame_err : 1, // [30:30] + fcs_err : 1; // [31:31] + uint32_t reserved_31a : 10, // [9:0] + decrypt_status_code : 3, // [12:10] + rx_bitmap_not_updated : 1, // [13:13] + reserved_31b : 17, // [30:14] + msdu_done : 1; // [31:31] +#else + uint32_t phy_ppdu_id : 16, // [31:16] + reserved_0 : 7, // [15:9] + sw_frame_group_id : 7, // [8:2] + rxpcu_mpdu_filter_in_category : 2; // [1:0] + uint32_t reserved_1a : 2, // [31:30] + reported_mpdu_length : 14, // [29:16] + ip_hdr_chksum : 16; // [15:0] + uint32_t cumulative_l3_checksum : 16, // [31:16] + cce_classify_not_done_cce_dis : 1, // [15:15] + cce_classify_not_done_truncate : 1, // [14:14] + cce_super_rule : 6, // [13:8] + reserved_2a : 8; // [7:0] + uint32_t rule_indication_31_0 : 32; // [31:0] + uint32_t ipv6_options_crc : 32; // [31:0] + uint32_t l3_type : 16, // [31:16] + reserved_5a : 2, // [15:14] + sa_offset_valid : 1, // [13:13] + da_offset_valid : 1, // [12:12] + sa_offset : 6, // [11:6] + da_offset : 6; // [5:0] + uint32_t rule_indication_63_32 : 32; // [31:0] + uint32_t tcp_seq_number : 32; // [31:0] + uint32_t tcp_ack_number : 32; // [31:0] + uint32_t window_size : 16, // [31:16] + reserved_9a : 6, // [15:10] + lro_eligible : 1, // [9:9] + tcp_flag : 9; // [8:0] + uint32_t ip_chksum_fail_copy : 1, // [31:31] + fr_ds : 1, // [30:30] + last_msdu : 1, // [29:29] + first_msdu : 1, // [28:28] + l3_header_padding : 2, // [27:26] + da_is_mcbc : 1, // [25:25] + da_is_valid : 1, // [24:24] + sa_is_valid : 1, // [23:23] + tid : 4, // [22:19] + to_ds : 1, // [18:18] + da_idx_timeout : 1, // [17:17] + sa_idx_timeout : 1, // [16:16] + sa_sw_peer_id : 16; // [15:0] + uint32_t da_idx_or_sw_peer_id : 16, // [31:16] + sa_idx : 16; // [15:0] + uint32_t fragment_flag : 1, // [31:31] + vlan_stag_stripped : 1, // [30:30] + vlan_ctag_stripped : 1, // [29:29] + mesh_sta : 2, // [28:27] + use_ppe : 1, // [26:26] + flow_idx : 20, // [25:6] + reo_destination_indication : 5, // [5:1] + msdu_drop : 1; // [0:0] + uint32_t fse_metadata : 32; // [31:0] + uint32_t tcp_udp_chksum : 16, // [31:16] + cce_metadata : 16; // [15:0] + uint32_t cumulative_ip_length : 16, // [31:16] + amsdu_parser_error : 1, // [15:15] + cce_match : 1, // [14:14] + flow_idx_invalid : 1, // [13:13] + flow_idx_timeout : 1, // [12:12] + msdu_limit_error : 1, // [11:11] + tcp_udp_chksum_fail_copy : 1, // [10:10] + fisa_timeout : 1, // [9:9] + flow_aggregation_continuation : 1, // [8:8] + aggregation_count : 8; // [7:0] + uint32_t reserved_16a : 24, // [31:8] + key_id_octet : 8; // [7:0] + uint32_t reserved_17b : 8, // [31:24] + dest_chip_pmac_id : 1, // [23:23] + wds_keep_alive_event : 1, // [22:22] + wds_roaming_event : 1, // [21:21] + wds_learning_event : 1, // [20:20] + multicast_echo : 1, // [19:19] + dest_chip_id : 2, // [18:17] + intra_bss : 1, // [16:16] + priority_valid : 1, // [15:15] + service_code : 9, // [14:6] + reserved_17a : 6; // [5:0] + uint32_t l4_offset : 8, // [31:24] + ipsec_ah : 1, // [23:23] + l3_offset : 7, // [22:16] + ipsec_esp : 1, // [15:15] + stbc : 1, // [14:14] + msdu_length : 14; // [13:0] + uint32_t ip4_protocol_ip6_next_header : 8, // [31:24] + ldpc : 1, // [23:23] + mesh_control_present : 1, // [22:22] + tcp_udp_header_valid : 1, // [21:21] + ip_extn_header_valid : 1, // [20:20] + ip_fixed_header_valid : 1, // [19:19] + toeplitz_hash_sel : 2, // [18:17] + da_is_bcast_mcast : 1, // [16:16] + tcp_only_ack : 1, // [15:15] + ip_frag : 1, // [14:14] + udp_proto : 1, // [13:13] + tcp_proto : 1, // [12:12] + ipv6_proto : 1, // [11:11] + ipv4_proto : 1, // [10:10] + decap_format : 2, // [9:8] + msdu_number : 8; // [7:0] + uint32_t vlan_stag_ci : 16, // [31:16] + vlan_ctag_ci : 16; // [15:0] + uint32_t peer_meta_data : 32; // [31:0] + uint32_t msdu_done_copy : 1, // [31:31] + mimo_ss_bitmap : 7, // [30:24] + reception_type : 3, // [23:21] + receive_bandwidth : 3, // [20:18] + rate_mcs : 4, // [17:14] + sgi : 2, // [13:12] + pkt_type : 4, // [11:8] + user_rssi : 8; // [7:0] + uint32_t flow_id_toeplitz : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] + uint32_t sa_15_0 : 16, // [31:16] + reserved_28a : 16; // [15:0] + uint32_t sa_47_16 : 32; // [31:0] + uint32_t fcs_err : 1, // [31:31] + unencrypted_frame_err : 1, // [30:30] + decrypt_err : 1, // [29:29] + tkip_mic_err : 1, // [28:28] + mpdu_length_err : 1, // [27:27] + buffer_fragment : 1, // [26:26] + directed : 1, // [25:25] + encrypt_required : 1, // [24:24] + rx_in_tx_decrypt_byp : 1, // [23:23] + amsdu_addr_mismatch : 1, // [22:22] + da_idx_invalid : 1, // [21:21] + sa_idx_invalid : 1, // [20:20] + ip_chksum_fail : 1, // [19:19] + tcp_udp_chksum_fail : 1, // [18:18] + msdu_length_err : 1, // [17:17] + overflow_err : 1, // [16:16] + wifi_parser_error : 1, // [15:15] + order : 1, // [14:14] + reserved_30b : 1, // [13:13] + a_msdu_error : 1, // [12:12] + eosp : 1, // [11:11] + more_data : 1, // [10:10] + ctrl_type : 1, // [9:9] + mgmt_type : 1, // [8:8] + null_data : 1, // [7:7] + non_qos : 1, // [6:6] + power_mgmt : 1, // [5:5] + ast_index_timeout : 1, // [4:4] + ast_index_not_found : 1, // [3:3] + mcast_bcast : 1, // [2:2] + reserved_30a : 1, // [1:1] + first_mpdu : 1; // [0:0] + uint32_t msdu_done : 1, // [31:31] + reserved_31b : 17, // [30:14] + rx_bitmap_not_updated : 1, // [13:13] + decrypt_status_code : 3, // [12:10] + reserved_31a : 10; // [9:0] +#endif +}; + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + This MPDU passed the normal frame + filter programming of rxpcu + This MPDU did NOT pass the + regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + This MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + +*/ + +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + + +#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + +/* Description RESERVED_0 + + +*/ + +#define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_MSDU_END_RESERVED_0_LSB 9 +#define RX_MSDU_END_RESERVED_0_MSB 15 +#define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description IP_HDR_CHKSUM + + This can include the IP header checksum or the pseudo header + checksum used by TCP/UDP checksum. + (with the first byte in the MSB and the second byte in the + LSB, i.e. requiring a byte-swap for little-endian FW/SW + w.r.t. the byte order in a packet) +*/ + +#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 +#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 +#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 +#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 + + +/* Description REPORTED_MPDU_LENGTH + + MPDU length before decapsulation. Only valid when first_msdu + is set. This field is taken directly from the length field + of the A-MPDU delimiter or the preamble length field for + non-A-MPDU frames. +*/ + +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_MSDU_END_RESERVED_1A_LSB 62 +#define RX_MSDU_END_RESERVED_1A_MSB 63 +#define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 + + +#define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_MSDU_END_RESERVED_2A_LSB 0 +#define RX_MSDU_END_RESERVED_2A_MSB 7 +#define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff + + +/* Description CCE_SUPER_RULE + + Indicates the super filter rule +*/ + +#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 +#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 +#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 + + +/* Description CCE_CLASSIFY_NOT_DONE_TRUNCATE + + Classification failed due to truncated frame +*/ + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 + + +/* Description CCE_CLASSIFY_NOT_DONE_CCE_DIS + + Classification failed due to CCE global disable +*/ + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 + + +/* Description CUMULATIVE_L3_CHECKSUM + + FISA: IP header checksum including the total MSDU length + that is part of this flow aggregated so far, reported if + 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set + + Set to zero in chips not supporting FISA + +*/ + +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 + + +/* Description RULE_INDICATION_31_0 + + Bitmap indicating which of rules 31-0 have matched + + In chips with more than 64 CCE rules, RXOLE + shall have a configuration to report any two rule_indication_* + in 'RX_MSDU_END.' +*/ + +#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 +#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 +#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 +#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 + + +#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff + + +/* Description DA_OFFSET + + Offset into MSDU buffer for DA +*/ + +#define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 +#define RX_MSDU_END_DA_OFFSET_LSB 32 +#define RX_MSDU_END_DA_OFFSET_MSB 37 +#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 + + +/* Description SA_OFFSET + + Offset into MSDU buffer for SA +*/ + +#define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 +#define RX_MSDU_END_SA_OFFSET_LSB 38 +#define RX_MSDU_END_SA_OFFSET_MSB 43 +#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 + + +/* Description DA_OFFSET_VALID + + da_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when DA is compressed +*/ + +#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 +#define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 +#define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 +#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 + + +/* Description SA_OFFSET_VALID + + sa_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when SA is compressed +*/ + +#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 +#define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 +#define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 +#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 + + +/* Description RESERVED_5A + + +*/ + +#define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 +#define RX_MSDU_END_RESERVED_5A_LSB 46 +#define RX_MSDU_END_RESERVED_5A_MSB 47 +#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 + + +/* Description L3_TYPE + + The 16-bit type value indicating the type of L3 later extracted + from LLC/SNAP, set to zero if SNAP is not available +*/ + +#define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 +#define RX_MSDU_END_L3_TYPE_LSB 48 +#define RX_MSDU_END_L3_TYPE_MSB 63 +#define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 + + +/* Description RULE_INDICATION_63_32 + + Bitmap indicating which of rules 63-32 have matched + + In chips with more than 64 CCE rules, RXOLE + shall have a configuration to report any two rule_indication_* + in 'RX_MSDU_END.' + +*/ + +#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 +#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 +#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 +#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff + + +/* Description TCP_SEQ_NUMBER + + TCP sequence number (as a number assembled from a TCP packet + in big-endian order, i.e. requiring a byte-swap for little-endian + FW/SW w.r.t. the byte order in a packet) + + If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' + is set, toeplitz_hash_2_or_4 from 'RX_MSDU_START' will be + reported here: + Controlled by multiple RxOLE registers for TCP/UDP over + IPv4/IPv6 - Either Toeplitz hash computed over 2-tuple IPv4 + or IPv6 src/dest addresses is reported; or, Toeplitz hash + computed over 4-tuple IPv4 or IPv6 src/dest addresses and + src/dest ports is reported. The Flow_id_toeplitz hash can + also be reported here. Usually the hash reported here is + the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy + in 'RXPT_CLASSIFY_INFO'). Optionally the 3-tuple Toeplitz + hash over IPv4 or IPv6 src/dest addresses and L4 protocol + can be reported here. +*/ + +#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 + + +/* Description TCP_ACK_NUMBER + + TCP acknowledge number (as a number assembled from a TCP + packet in big-endian order, i.e. requiring a byte-swap + for little-endian FW/SW w.r.t. the byte order in a packet) + + + If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' + is set, flow_id_toeplitz from 'RX_MSDU_START' will be reported + here: + Toeplitz hash of 5-tuple {IP source address, IP destination + address, IP source port, IP destination port, L4 protocol} + in case of non-IPSec. In case of IPSec - Toeplitz hash + of 4-tuple {IP source address, IP destination address, SPI, + L4 protocol}. Optionally the 3-tuple Toeplitz hash over + IPv4 or IPv6 src/dest addresses and L4 protocol can be reported + here. + The relevant Toeplitz key registers are provided in RxOLE's + instance of common parser module. These registers are separate + from the Toeplitz keys used by ASE/FSE modules inside RxOLE. + The actual value will be passed on from common parser module + to RxOLE in one of the WHO_* TLVs. +*/ + +#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 +#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 +#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 +#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff + + +/* Description TCP_FLAG + + TCP flags + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit in + bit 8 and the FIN bit in bit 0, i.e. in big-endian order, + i.e. requiring a byte-swap for little-endian FW/SW w.r.t. + the byte order in a packet) +*/ + +#define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 +#define RX_MSDU_END_TCP_FLAG_LSB 32 +#define RX_MSDU_END_TCP_FLAG_MSB 40 +#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 + + +/* Description LRO_ELIGIBLE + + Computed out of TCP and IP fields to indicate that this + MSDU is eligible for LRO +*/ + +#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 +#define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 +#define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 +#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 + + +/* Description RESERVED_9A + + NOTE: DO not assign a field... Internally used in RXOLE.. + + +*/ + +#define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 +#define RX_MSDU_END_RESERVED_9A_LSB 42 +#define RX_MSDU_END_RESERVED_9A_MSB 47 +#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 + + +/* Description WINDOW_SIZE + + TCP receive window size (as a number assembled from a TCP + packet in big-endian order, i.e. requiring a byte-swap + for little-endian FW/SW w.r.t. the byte order in a packet) + + + If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' + is set, msdu_length from 'RX_MSDU_START' will be reported + in the 14 LSBs here: + MSDU length in bytes after decapsulation. This field is + still valid for MPDU frames without A-MSDU. It still represents + MSDU length after decapsulation. +*/ + +#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 +#define RX_MSDU_END_WINDOW_SIZE_LSB 48 +#define RX_MSDU_END_WINDOW_SIZE_MSB 63 +#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 + + +/* Description SA_SW_PEER_ID + + sw_peer_id from the address search entry corresponding to + the source address of the MSDU + + +*/ + +#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 +#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 +#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff + + +/* Description SA_IDX_TIMEOUT + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. +*/ + +#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 + + +/* Description DA_IDX_TIMEOUT + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. +*/ + +#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 + + +/* Description TO_DS + + Set if the to DS bit is set in the frame control. + + RXOLE copies this from the 'Struct RX_MPDU_INFO' in 'RX_MPDU_PCU_START.' + + + +*/ + +#define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 +#define RX_MSDU_END_TO_DS_LSB 18 +#define RX_MSDU_END_TO_DS_MSB 18 +#define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 + + + +#define RX_MSDU_END_TID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_TID_LSB 19 +#define RX_MSDU_END_TID_MSB 22 +#define RX_MSDU_END_TID_MASK 0x0000000000780000 + + +/* Description SA_IS_VALID + + Indicates that OLE found a valid SA entry +*/ + +#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_IS_VALID_LSB 23 +#define RX_MSDU_END_SA_IS_VALID_MSB 23 +#define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 + + +/* Description DA_IS_VALID + + Indicates that OLE found a valid DA entry +*/ + +#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IS_VALID_LSB 24 +#define RX_MSDU_END_DA_IS_VALID_MSB 24 +#define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address. + +*/ + +#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IS_MCBC_LSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 + + +/* Description L3_HEADER_PADDING + + Number of bytes padded to make sure that the L3 header + will always start of a Dword boundary +*/ + +#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 +#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 +#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 +#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 + + +/* Description FIRST_MSDU + + Indicates the first MSDU of A-MSDU. If both first_msdu + and last_msdu are set in the MSDU then this is a non-aggregated + MSDU frame: normal MPDU. Interior MSDU in an A-MSDU shall + have both first_mpdu and last_mpdu bits set to 0. +*/ + +#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 +#define RX_MSDU_END_FIRST_MSDU_LSB 28 +#define RX_MSDU_END_FIRST_MSDU_MSB 28 +#define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 + + +/* Description LAST_MSDU + + Indicates the last MSDU of the A-MSDU. MPDU end status + is only valid when last_msdu is set. +*/ + +#define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 +#define RX_MSDU_END_LAST_MSDU_LSB 29 +#define RX_MSDU_END_LAST_MSDU_MSB 29 +#define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 + + +/* Description FR_DS + + Set if the from DS bit is set in the frame control. + + RXOLE copies this from the 'Struct RX_MPDU_INFO' in 'RX_MPDU_PCU_START.' + + +*/ + +#define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 +#define RX_MSDU_END_FR_DS_LSB 30 +#define RX_MSDU_END_FR_DS_MSB 30 +#define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 + + +/* Description IP_CHKSUM_FAIL_COPY + + If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is set, + ip_chksum_fail from 'RX_ATTENTION' will be reported in the + MSB here: + Indicates that the computed checksum (ip_hdr_chksum) did + not match the checksum in the IP header. +*/ + +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 + + +/* Description SA_IDX + + The offset in the address table which matches the MAC source + address. +*/ + +#define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_IDX_LSB 32 +#define RX_MSDU_END_SA_IDX_MSB 47 +#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 + + +/* Description DA_IDX_OR_SW_PEER_ID + + Based on a register configuration in RXOLE, this field will + contain: + The offset in the address table which matches the MAC destination + address + OR: + sw_peer_id from the address search entry corresponding to + the destination address of the MSDU +*/ + +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 + + +/* Description MSDU_DROP + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 +#define RX_MSDU_END_MSDU_DROP_LSB 0 +#define RX_MSDU_END_MSDU_DROP_MSB 0 +#define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 + + +/* Description REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e + + +/* Description FLOW_IDX + + Flow table index + +*/ + +#define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 +#define RX_MSDU_END_FLOW_IDX_LSB 6 +#define RX_MSDU_END_FLOW_IDX_MSB 25 +#define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 + + +/* Description USE_PPE + + Indicates to RXDMA to ignore the REO_destination_indication + and use a programmed value corresponding to the REO2PPE + ring + + This override to REO2PPE for packets requiring multiple + buffers shall be disabled based on an RXDMA configuration, + as PPE may not support such packets. + +*/ + +#define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 +#define RX_MSDU_END_USE_PPE_LSB 26 +#define RX_MSDU_END_USE_PPE_MSB 26 +#define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 + + +/* Description MESH_STA + + When set, this is a Mesh (11s) STA. + + The interpretation of the A-MSDU 'Length' field in the MPDU + (if any) is decided by the e-numerations below. + + + A-MSDU 'Length' is big endian and includes + the length of Mesh Control. + A-MSDU 'Length' is big endian and excludes + the length of Mesh Control. + A-MSDU 'Length' is little endian and + excludes the length of Mesh Control. This is 802.11s-compliant. + + +*/ + +#define RX_MSDU_END_MESH_STA_OFFSET 0x0000000000000030 +#define RX_MSDU_END_MESH_STA_LSB 27 +#define RX_MSDU_END_MESH_STA_MSB 28 +#define RX_MSDU_END_MESH_STA_MASK 0x0000000018000000 + + +/* Description VLAN_CTAG_STRIPPED + + Set by RXOLE if it stripped 4-bytes of C-VLAN Tag from the + packet + +*/ + +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 + + +/* Description VLAN_STAG_STRIPPED + + Set by RXOLE if it stripped 4-bytes of S-VLAN Tag from the + packet + +*/ + +#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 + + +/* Description FRAGMENT_FLAG + + Indicates that this is an 802.11 fragment frame. This is + set when either the more_frag bit is set in the frame control + or the fragment number is not zero. Only set when first_msdu + is set. +*/ + +#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 +#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 + + +/* Description FSE_METADATA + + FSE related meta data: + +*/ + +#define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 +#define RX_MSDU_END_FSE_METADATA_LSB 32 +#define RX_MSDU_END_FSE_METADATA_MSB 63 +#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 + + +/* Description CCE_METADATA + + CCE related meta data: + +*/ + +#define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 +#define RX_MSDU_END_CCE_METADATA_LSB 0 +#define RX_MSDU_END_CCE_METADATA_MSB 15 +#define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff + + + +#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 +#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 + + +/* Description AGGREGATION_COUNT + + FISA: Number of MSDU's aggregated so far + + Set to zero in chips not supporting FISA + +*/ + +#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 +#define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 +#define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 +#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 + + +/* Description FLOW_AGGREGATION_CONTINUATION + + FISA: To indicate that this MSDU can be aggregated with + the previous packet with the same flow id + + Set to zero in chips not supporting FISA + +*/ + +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 + + +/* Description FISA_TIMEOUT + + FISA: To indicate that the aggregation has restarted for + this flow due to timeout + + Set to zero in chips not supporting FISA + +*/ + +#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FISA_TIMEOUT_LSB 41 +#define RX_MSDU_END_FISA_TIMEOUT_MSB 41 +#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 + + +/* Description TCP_UDP_CHKSUM_FAIL_COPY + + if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is set, + tcp_udp_chksum_fail from 'RX_ATTENTION' will be reported + here: + Indicates that the computed checksum (tcp_udp_chksum) did + not match the checksum in the TCP/UDP header. +*/ + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 + + +/* Description MSDU_LIMIT_ERROR + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will + not be decapsulated but will be DMA'ed in RAW format as + a single MSDU buffer +*/ + +#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 + + +/* Description FLOW_IDX_TIMEOUT + + Indicates an unsuccessful flow search due to the expiring + of the search timer. + +*/ + +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 + + +/* Description FLOW_IDX_INVALID + + flow id is not valid + +*/ + +#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 +#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 +#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 + + +/* Description CCE_MATCH + + Indicates that this status has a corresponding MSDU that + requires FW processing. The OLE will have classification + ring mask registers which will indicate the ring(s) for + packets and descriptors which need FW attention. +*/ + +#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 +#define RX_MSDU_END_CCE_MATCH_LSB 46 +#define RX_MSDU_END_CCE_MATCH_MSB 46 +#define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 + + +/* Description AMSDU_PARSER_ERROR + + A-MSDU could not be properly de-agregated. + +*/ + +#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 + + +/* Description CUMULATIVE_IP_LENGTH + + FISA: Total MSDU length that is part of this flow aggregated + so far + + Set to zero in chips not supporting FISA + +*/ + +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 + + +/* Description KEY_ID_OCTET + + The key ID octet from the IV. Only valid when first_msdu + is set. +*/ + +#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 +#define RX_MSDU_END_KEY_ID_OCTET_LSB 0 +#define RX_MSDU_END_KEY_ID_OCTET_MSB 7 +#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff + + + +#define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 +#define RX_MSDU_END_RESERVED_16A_LSB 8 +#define RX_MSDU_END_RESERVED_16A_MSB 31 +#define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 + + +/* Description RESERVED_17A + + +*/ + +#define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 +#define RX_MSDU_END_RESERVED_17A_LSB 32 +#define RX_MSDU_END_RESERVED_17A_MSB 37 +#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 +#define RX_MSDU_END_SERVICE_CODE_LSB 38 +#define RX_MSDU_END_SERVICE_CODE_MSB 46 +#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 +#define RX_MSDU_END_PRIORITY_VALID_LSB 47 +#define RX_MSDU_END_PRIORITY_VALID_MSB 47 +#define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 +#define RX_MSDU_END_INTRA_BSS_LSB 48 +#define RX_MSDU_END_INTRA_BSS_MSB 48 +#define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 +#define RX_MSDU_END_DEST_CHIP_ID_LSB 49 +#define RX_MSDU_END_DEST_CHIP_ID_MSB 50 +#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 + + +/* Description MULTICAST_ECHO + + If set, this packet is a multicast echo, i.e. the DA is + multicast and Rx OLE SA search with mcast_echo_check = 1 + passed. RXDMA should release such packets to WBM. + + +*/ + +#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 +#define RX_MSDU_END_MULTICAST_ECHO_LSB 51 +#define RX_MSDU_END_MULTICAST_ECHO_MSB 51 +#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 + + +/* Description WDS_LEARNING_EVENT + + If set, this packet has an SA search failure with WDS learning + enabled for the peer. RXOLE should route this TLV to the + RXDMA0 status ring to notify FW. + + +*/ + +#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 +#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 + + +/* Description WDS_ROAMING_EVENT + + If set, this packet's SA 'Sw_peer_id' mismatches the 'Sw_peer_id' + of the peer through which the packet was got, indicating + the SA node has roamed. RXOLE should route this TLV to + the RXDMA0 status ring to notify FW. + + +*/ + +#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 +#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 + + +/* Description WDS_KEEP_ALIVE_EVENT + + If set, the AST timestamp for this packet's SA is older + than the current timestamp by more than a threshold programmed + in RXOLE. RXOLE should route this TLV to the RXDMA0 status + ring to notify FW to keep the AST entry for the SA alive. + + + +*/ + +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_END_DEST_CHIP_PMAC_ID_OFFSET 0x0000000000000040 +#define RX_MSDU_END_DEST_CHIP_PMAC_ID_LSB 55 +#define RX_MSDU_END_DEST_CHIP_PMAC_ID_MSB 55 +#define RX_MSDU_END_DEST_CHIP_PMAC_ID_MASK 0x0080000000000000 + + +/* Description RESERVED_17B + + +*/ + +#define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 +#define RX_MSDU_END_RESERVED_17B_LSB 56 +#define RX_MSDU_END_RESERVED_17B_MSB 63 +#define RX_MSDU_END_RESERVED_17B_MASK 0xff00000000000000 + + +/* Description MSDU_LENGTH + + MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation +*/ + +#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 +#define RX_MSDU_END_MSDU_LENGTH_LSB 0 +#define RX_MSDU_END_MSDU_LENGTH_MSB 13 +#define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 +#define RX_MSDU_END_STBC_LSB 14 +#define RX_MSDU_END_STBC_MSB 14 +#define RX_MSDU_END_STBC_MASK 0x0000000000004000 + + +/* Description IPSEC_ESP + + Set if IPv4/v6 packet is using IPsec ESP +*/ + +#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPSEC_ESP_LSB 15 +#define RX_MSDU_END_IPSEC_ESP_MSB 15 +#define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 + + +/* Description L3_OFFSET + + Depending upon mode bit, this field either indicates the + L3 offset in bytes from the start of the RX_HEADER or the + IP offset in bytes from the start of the packet after decapsulation. + The latter is only valid if ipv4_proto or ipv6_proto is + set. +*/ + +#define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 +#define RX_MSDU_END_L3_OFFSET_LSB 16 +#define RX_MSDU_END_L3_OFFSET_MSB 22 +#define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 + + +/* Description IPSEC_AH + + Set if IPv4/v6 packet is using IPsec AH +*/ + +#define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPSEC_AH_LSB 23 +#define RX_MSDU_END_IPSEC_AH_MSB 23 +#define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 + + +/* Description L4_OFFSET + + Depending upon mode bit, this field either indicates the + L4 offset nin bytes from the start of RX_HEADER(only valid + if either ipv4_proto or ipv6_proto is set to 1) or indicates + the offset in bytes to the start of TCP or UDP header from + the start of the IP header after decapsulation(Only valid + if tcp_proto or udp_proto is set). The value 0 indicates + that the offset is longer than 127 bytes. +*/ + +#define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 +#define RX_MSDU_END_L4_OFFSET_LSB 24 +#define RX_MSDU_END_L4_OFFSET_MSB 31 +#define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 + + +/* Description MSDU_NUMBER + + Indicates the MSDU number within a MPDU. This value is + reset to zero at the start of each MPDU. If the number + of MSDU exceeds 255 this number will wrap using modulo 256. + +*/ + +#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 +#define RX_MSDU_END_MSDU_NUMBER_LSB 32 +#define RX_MSDU_END_MSDU_NUMBER_MSB 39 +#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 +#define RX_MSDU_END_DECAP_FORMAT_LSB 40 +#define RX_MSDU_END_DECAP_FORMAT_MSB 41 +#define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 + + +/* Description IPV4_PROTO + + Set if L2 layer indicates IPv4 protocol. +*/ + +#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPV4_PROTO_LSB 42 +#define RX_MSDU_END_IPV4_PROTO_MSB 42 +#define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 + + +/* Description IPV6_PROTO + + Set if L2 layer indicates IPv6 protocol. +*/ + +#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPV6_PROTO_LSB 43 +#define RX_MSDU_END_IPV6_PROTO_MSB 43 +#define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 + + +/* Description TCP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP protocol + indicates TCP. +*/ + +#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TCP_PROTO_LSB 44 +#define RX_MSDU_END_TCP_PROTO_MSB 44 +#define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 + + +/* Description UDP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP protocol + indicates UDP. +*/ + +#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_UDP_PROTO_LSB 45 +#define RX_MSDU_END_UDP_PROTO_MSB 45 +#define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 + + +/* Description IP_FRAG + + Indicates that either the IP More frag bit is set or IP + frag number is non-zero. If set indicates that this is + a fragmented IP packet. +*/ + +#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP_FRAG_LSB 46 +#define RX_MSDU_END_IP_FRAG_MSB 46 +#define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 + + +/* Description TCP_ONLY_ACK + + Set if only the TCP Ack bit is set in the TCP flags and + if the TCP payload is 0. +*/ + +#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 +#define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 +#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 + + +/* Description DA_IS_BCAST_MCAST + + The destination address is broadcast or multicast. +*/ + +#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 + + +/* Description TOEPLITZ_HASH_SEL + + Actual choosen Hash. + + 0 -> Toeplitz hash of 2-tuple (IP source address, IP destination + address)1 -> Toeplitz hash of 4-tuple (IP source address, + IP destination address, L4 (TCP/UDP) source port, L4 (TCP/UDP) + destination port) + 2 -> Toeplitz of flow_id + 3 -> "Zero" is used + +*/ + +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 + + +/* Description IP_FIXED_HEADER_VALID + + Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed + fully within first 256 bytes of the packet +*/ + +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 + + +/* Description IP_EXTN_HEADER_VALID + + IPv6/IPv6 header, including IPv4 options and recognizable + extension headers parsed fully within first 256 bytes of + the packet +*/ + +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 + + +/* Description TCP_UDP_HEADER_VALID + + Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP + header parsed fully within first 256 bytes of the packet + +*/ + +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 + + +/* Description MESH_CONTROL_PRESENT + + When set, this MSDU includes the 'Mesh Control' field + +*/ + +#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 + + +/* Description LDPC + + When set, indicates that LDPC coding was used. + +*/ + +#define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 +#define RX_MSDU_END_LDPC_LSB 55 +#define RX_MSDU_END_LDPC_MSB 55 +#define RX_MSDU_END_LDPC_MASK 0x0080000000000000 + + +/* Description IP4_PROTOCOL_IP6_NEXT_HEADER + + For IPv4 this is the 8 bit protocol field (when ipv4_proto + is set). For IPv6 this is the 8 bit next_header field (when + ipv6_proto is set). +*/ + +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 + + + +#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 +#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 +#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff + + + +#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 +#define RX_MSDU_END_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_END_VLAN_STAG_CI_MSB 31 +#define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 + + +#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 +#define RX_MSDU_END_PEER_META_DATA_LSB 32 +#define RX_MSDU_END_PEER_META_DATA_MSB 63 +#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 + + +/* Description USER_RSSI + + RSSI for this user + +*/ + +#define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 +#define RX_MSDU_END_USER_RSSI_LSB 0 +#define RX_MSDU_END_USER_RSSI_MSB 7 +#define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 +#define RX_MSDU_END_PKT_TYPE_LSB 8 +#define RX_MSDU_END_PKT_TYPE_MSB 11 +#define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 + + +/* Description SGI + + Field only valid when pkt type is HT, VHT or HE. + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 +#define RX_MSDU_END_SGI_LSB 12 +#define RX_MSDU_END_SGI_MSB 13 +#define RX_MSDU_END_SGI_MASK 0x0000000000003000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 +#define RX_MSDU_END_RATE_MCS_LSB 14 +#define RX_MSDU_END_RATE_MCS_MSB 17 +#define RX_MSDU_END_RATE_MCS_MASK 0x000000000003c000 + + +/* Description RECEIVE_BANDWIDTH + + Full receive Bandwidth + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x00000000001c0000 + + +#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 +#define RX_MSDU_END_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_END_RECEPTION_TYPE_MSB 23 +#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000000e00000 + + +/* Description MIMO_SS_BITMAP + + Field only valid when Reception_type for the MPDU from this + STA is some form of MIMO reception + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + LSB related to SS 0 + + 0: spatial stream not used for this reception + 1: spatial stream used for this reception + + Note: Only 7 bits are reported here to accommodate field + 'msdu_done_copy.' + +*/ + +#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 +#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 +#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007f000000 + + +/* Description MSDU_DONE_COPY + + If set indicates that the RX packet data, RX header data, + RX PPDU start descriptor, RX MPDU start/end descriptor, + RX MSDU start/end descriptors and RX Attention descriptor + are all valid. + + +*/ + +#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 +#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 + + +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 + + +/* Description PPDU_START_TIMESTAMP_63_32 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, upper 32 bits + +*/ + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff + + +/* Description SW_PHY_META_DATA + + SW programmed Meta data provided by the PHY. + + Can be used for SW to indicate the channel the device is + on. + +*/ + +#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 +#define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 +#define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 +#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 + + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + + +/* Description TOEPLITZ_HASH_2_OR_4 + + Controlled by multiple RxOLE registers for TCP/UDP over + IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple + IPv4 or IPv6 src/dest addresses is reported; or, Toeplitz + hash computed over 4-tuple IPv4 or IPv6 src/dest addresses + and src/dest ports is reported. The Flow_id_toeplitz hash + can also be reported here. Usually the hash reported here + is the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy + in 'RXPT_CLASSIFY_INFO'). + + Optionally the 3-tuple Toeplitz hash over IPv4 + or IPv6 src/dest addresses and L4 protocol can be reported +*/ + +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 + + +/* Description RESERVED_28A + + +*/ + +#define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 +#define RX_MSDU_END_RESERVED_28A_LSB 0 +#define RX_MSDU_END_RESERVED_28A_MSB 15 +#define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff + + +/* Description SA_15_0 + + Source MAC address bits [15:0] (with the fifth byte in the + MSB and the last byte in the LSB, i.e. requiring a byte-swap + for little-endian FW) +*/ + +#define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 +#define RX_MSDU_END_SA_15_0_LSB 16 +#define RX_MSDU_END_SA_15_0_MSB 31 +#define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 + + +/* Description SA_47_16 + + Source MAC address bits [47:16] (with the first byte in + the MSB and the fourth byte in the LSB, i.e. requiring a + byte-swap for little-endian FW) +*/ + +#define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 +#define RX_MSDU_END_SA_47_16_LSB 32 +#define RX_MSDU_END_SA_47_16_MSB 63 +#define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 + + +#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 +#define RX_MSDU_END_FIRST_MPDU_LSB 0 +#define RX_MSDU_END_FIRST_MPDU_MSB 0 +#define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 + + +/* Description RESERVED_30A + + +*/ + +#define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_30A_LSB 1 +#define RX_MSDU_END_RESERVED_30A_MSB 1 +#define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 + + +/* Description MCAST_BCAST + + Multicast / broadcast indicator. Only set when the MAC + address 1 bit 0 is set indicating mcast/bcast and the BSSID + matches one of the 4 BSSID registers. Only set when first_msdu + is set. +*/ + +#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MCAST_BCAST_LSB 2 +#define RX_MSDU_END_MCAST_BCAST_MSB 2 +#define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 + + +/* Description AST_INDEX_NOT_FOUND + + Only valid when first_msdu is set. + + Indicates no AST matching entries within the the max search + count. +*/ + +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 + + +/* Description AST_INDEX_TIMEOUT + + Only valid when first_msdu is set. + + Indicates an unsuccessful search in the address seach table + due to timeout. +*/ + +#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 + + +/* Description POWER_MGMT + + Power management bit set in the 802.11 header. Only set + when first_msdu is set. +*/ + +#define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 +#define RX_MSDU_END_POWER_MGMT_LSB 5 +#define RX_MSDU_END_POWER_MGMT_MSB 5 +#define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 + + +/* Description NON_QOS + + Set if packet is not a non-QoS data frame. Only set when + first_msdu is set. +*/ + +#define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 +#define RX_MSDU_END_NON_QOS_LSB 6 +#define RX_MSDU_END_NON_QOS_MSB 6 +#define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 + + +/* Description NULL_DATA + + Set if frame type indicates either null data or QoS null + data format. Only set when first_msdu is set. +*/ + +#define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 +#define RX_MSDU_END_NULL_DATA_LSB 7 +#define RX_MSDU_END_NULL_DATA_MSB 7 +#define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 + + +/* Description MGMT_TYPE + + Set if packet is a management packet. Only set when first_msdu + is set. +*/ + +#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MGMT_TYPE_LSB 8 +#define RX_MSDU_END_MGMT_TYPE_MSB 8 +#define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 + + +/* Description CTRL_TYPE + + Set if packet is a control packet. Only set when first_msdu + is set. +*/ + +#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_CTRL_TYPE_LSB 9 +#define RX_MSDU_END_CTRL_TYPE_MSB 9 +#define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 + + +/* Description MORE_DATA + + Set if more bit in frame control is set. Only set when + first_msdu is set. +*/ + +#define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MORE_DATA_LSB 10 +#define RX_MSDU_END_MORE_DATA_MSB 10 +#define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 + + +/* Description EOSP + + Set if the EOSP (end of service period) bit in the QoS control + field is set. Only set when first_msdu is set. +*/ + +#define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 +#define RX_MSDU_END_EOSP_LSB 11 +#define RX_MSDU_END_EOSP_MSB 11 +#define RX_MSDU_END_EOSP_MASK 0x0000000000000800 + + +/* Description A_MSDU_ERROR + + Set if number of MSDUs in A-MSDU is above a threshold or + if the size of the MSDU is invalid. This receive buffer + will contain all of the remainder of the MSDUs in this + MPDU without decapsulation. +*/ + +#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_A_MSDU_ERROR_LSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 + + +#define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_30B_LSB 13 +#define RX_MSDU_END_RESERVED_30B_MSB 13 +#define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 + + +/* Description ORDER + + Set if the order bit in the frame control is set. Only + set when first_msdu is set. +*/ + +#define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 +#define RX_MSDU_END_ORDER_LSB 14 +#define RX_MSDU_END_ORDER_MSB 14 +#define RX_MSDU_END_ORDER_MASK 0x0000000000004000 + + +/* Description WIFI_PARSER_ERROR + + Indicates that the WiFi frame has one of the following errors + + o has less than minimum allowed bytes as per standard + o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) + +*/ + +#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 + + +/* Description OVERFLOW_ERR + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + This MPDU will not be ACKed. + RXPCU might still be able to correctly receive the following + MPDUs in the PPDU if enough fifo space became available + in time +*/ + +#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_OVERFLOW_ERR_LSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 + + +/* Description MSDU_LENGTH_ERR + + Indicates that the MSDU length from the 802.3 encapsulated + length field extends beyond the MPDU boundary or if the + length is less than 14 bytes. + Merged with original "other_msdu_err": Indicates that the + MSDU threshold was exceeded and thus all the rest of the + MSDUs will not be scattered and will not be decasulated + but will be DMA'ed in RAW format as a single MSDU buffer + +*/ + +#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Indicates that the computed checksum (tcp_udp_chksum in 'RX_MSDU_END') + did not match the checksum in the TCP/UDP header. +*/ + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 + + +/* Description IP_CHKSUM_FAIL + + Indicates that the computed checksum (ip_hdr_chksum in 'RX_MSDU_END') + did not match the checksum in the IP header. +*/ + +#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 +#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 + + +/* Description SA_IDX_INVALID + + Indicates no matching entry was found in the address search + table for the source MAC address. +*/ + +#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 +#define RX_MSDU_END_SA_IDX_INVALID_LSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 + + +/* Description DA_IDX_INVALID + + Indicates no matching entry was found in the address search + table for the destination MAC address. +*/ + +#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DA_IDX_INVALID_LSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 + + +/* Description AMSDU_ADDR_MISMATCH + + Indicates that an A-MSDU with 'from DS = 0' had an SA mismatching + TA or an A-MDU with 'to DS = 0' had a DA mismatching RA + +*/ + +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 + + +/* Description RX_IN_TX_DECRYPT_BYP + + Indicates that RX packet is not decrypted as Crypto is busy + with TX packet processing. +*/ + +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 + + +/* Description ENCRYPT_REQUIRED + + Indicates that this data type frame is not encrypted even + if the policy for this MPDU requires encryption as indicated + in the peer entry key type. +*/ + +#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 +#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 + + +/* Description DIRECTED + + MPDU is a directed packet which means that the RA matched + our STA addresses. In proxySTA it means that the TA matched + an entry in our address search table with the corresponding + "no_ack" bit is the address search entry cleared. +*/ + +#define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DIRECTED_LSB 25 +#define RX_MSDU_END_DIRECTED_MSB 25 +#define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 + + +/* Description BUFFER_FRAGMENT + + Indicates that at least one of the rx buffers has been fragmented. + If set the FW should look at the rx_frag_info descriptor + described below. +*/ + +#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 +#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 + + +/* Description MPDU_LENGTH_ERR + + Indicates that the MPDU was pre-maturely terminated resulting + in a truncated MPDU. Don't trust the MPDU length field. + +*/ + +#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 + + +/* Description TKIP_MIC_ERR + + Indicates that the MPDU Michael integrity check failed +*/ + +#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 + + +/* Description DECRYPT_ERR + + Indicates that the MPDU decrypt integrity check failed or + CRYPTO received an encrypted frame, but did not get a valid + corresponding key id in the peer entry. +*/ + +#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DECRYPT_ERR_LSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 + + +/* Description UNENCRYPTED_FRAME_ERR + + Copied here by RX OLE from the RX_MPDU_END TLV +*/ + +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 + + +/* Description FCS_ERR + + Indicates that the MPDU FCS check failed +*/ + +#define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_FCS_ERR_LSB 31 +#define RX_MSDU_END_FCS_ERR_MSB 31 +#define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 + + +/* Description RESERVED_31A + + +*/ + +#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_31A_LSB 32 +#define RX_MSDU_END_RESERVED_31A_MSB 41 +#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 + + +/* Description DECRYPT_STATUS_CODE + + Field provides insight into the decryption performed + + Frame had protection enabled and decrypted + properly + Frame is unprotected + and hence bypassed + Frame has protection enabled + and could not be properly d ecrypted due to MIC/ICV mismatch + etc. + Frame has protection enabled + but the key that was required to decrypt this frame was + not valid + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + Reserved for other indications + + +*/ + +#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 + + +/* Description RX_BITMAP_NOT_UPDATED + + Frame is received, but RXPCU could not update the receive + bitmap due to (temporary) fifo contraints. + +*/ + +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 + + +/* Description RESERVED_31B + + +*/ + +#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_31B_LSB 46 +#define RX_MSDU_END_RESERVED_31B_MSB 62 +#define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000 + + +#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MSDU_DONE_LSB 63 +#define RX_MSDU_END_MSDU_DONE_MSB 63 +#define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 + + + +#endif // RX_MSDU_END diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_msdu_ext_desc_info.h b/drivers/staging/fw-api/hw/qcn6432/rx_msdu_ext_desc_info.h new file mode 100644 index 0000000000000000000000000000000000000000..d24572cadde13fee0d4a54e4179735c705524c6d --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_msdu_ext_desc_info.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MSDU_EXT_DESC_INFO_H_ +#define _RX_MSDU_EXT_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 + + +struct rx_msdu_ext_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, // [4:0] + service_code : 9, // [13:5] + priority_valid : 1, // [14:14] + data_offset : 12, // [26:15] + src_link_id : 3, // [29:27] + reserved_0a : 2; // [31:30] +#else + uint32_t reserved_0a : 2, // [31:30] + src_link_id : 3, // [29:27] + data_offset : 12, // [26:15] + priority_valid : 1, // [14:14] + service_code : 9, // [13:5] + reo_destination_indication : 5; // [4:0] +#endif +}; + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 + + + +#endif // RX_MSDU_EXT_DESC_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_msdu_link.h b/drivers/staging/fw-api/hw/qcn6432/rx_msdu_link.h new file mode 100644 index 0000000000000000000000000000000000000000..1160dabaf48a2529705b212b5d3d7f42db1211b0 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_msdu_link.h @@ -0,0 +1,4050 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MSDU_LINK_H_ +#define _RX_MSDU_LINK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "buffer_addr_info.h" +#include "rx_msdu_details.h" +#define NUM_OF_DWORDS_RX_MSDU_LINK 32 + + +struct rx_msdu_link { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t receive_queue_number : 16, // [15:0] + first_rx_msdu_link_struct : 1, // [16:16] + reserved_3a : 15; // [31:17] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#else + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t reserved_3a : 15, // [31:17] + first_rx_msdu_link_struct : 1, // [16:16] + receive_queue_number : 16; // [15:0] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#endif +}; + + +/* Description DESCRIPTOR_HEADER + + Details about which module owns this struct. + Note that sub field "Buffer_type" shall be set to "Receive_MSDU_Link_descriptor" + +*/ + + +/* Description OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + The owner of this data structure: + Buffer Manager currently owns this data + structure. + Software of FW currently owns this + data structure. + Transmit Queue Manager currently owns + this data structure. + Receive DMA currently owns this data + structure. + Reorder currently owns this data structure. + + SWITCH currently owns this data structure. + + + +*/ + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + +/* Description BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Field describing what contents format is of this descriptor + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + +*/ + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + +/* Description TX_MPDU_QUEUE_NUMBER + + Consumer: TQM/Debug + Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) + + Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor + + + Indicates the MPDU queue ID to which this MPDU descriptor + belongs + Used for tracking and debugging + + +*/ + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + + +/* Description NEXT_MSDU_LINK_DESC_ADDR_INFO + + Details of the physical address of the next MSDU link descriptor + that contains info about additional MSDUs that are part + of this MPDU. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RECEIVE_QUEUE_NUMBER + + Indicates the Receive queue to which this MPDU descriptor + belongs + Used for tracking, finding bugs and debugging. + +*/ + +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + + +/* Description FIRST_RX_MSDU_LINK_STRUCT + + When set, this RX_MSDU_link descriptor is the first one + in the MSDU link list. Field MSDU_0 points to the very first + MSDU buffer descriptor in the MPDU + +*/ + +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 + + +/* Description RESERVED_3A + + +*/ + +#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_LINK_RESERVED_3A_LSB 17 +#define RX_MSDU_LINK_RESERVED_3A_MSB 31 +#define RX_MSDU_LINK_RESERVED_3A_MASK 0xfffe0000 + + +/* Description PN_31_0 + + Field only valid when First_RX_MSDU_link_struct is set. + + + 31-0 bits of the 256-bit packet number bitmap. + +*/ + +#define RX_MSDU_LINK_PN_31_0_OFFSET 0x00000010 +#define RX_MSDU_LINK_PN_31_0_LSB 0 +#define RX_MSDU_LINK_PN_31_0_MSB 31 +#define RX_MSDU_LINK_PN_31_0_MASK 0xffffffff + + +/* Description PN_63_32 + + Field only valid when First_RX_MSDU_link_struct is set. + + + 63-32 bits of the 256-bit packet number bitmap. + +*/ + +#define RX_MSDU_LINK_PN_63_32_OFFSET 0x00000014 +#define RX_MSDU_LINK_PN_63_32_LSB 0 +#define RX_MSDU_LINK_PN_63_32_MSB 31 +#define RX_MSDU_LINK_PN_63_32_MASK 0xffffffff + + +/* Description PN_95_64 + + Field only valid when First_RX_MSDU_link_struct is set. + + + 95-64 bits of the 256-bit packet number bitmap. + +*/ + +#define RX_MSDU_LINK_PN_95_64_OFFSET 0x00000018 +#define RX_MSDU_LINK_PN_95_64_LSB 0 +#define RX_MSDU_LINK_PN_95_64_MSB 31 +#define RX_MSDU_LINK_PN_95_64_MASK 0xffffffff + + +/* Description PN_127_96 + + Field only valid when First_RX_MSDU_link_struct is set. + + + 127-96 bits of the 256-bit packet number bitmap. + +*/ + +#define RX_MSDU_LINK_PN_127_96_OFFSET 0x0000001c +#define RX_MSDU_LINK_PN_127_96_LSB 0 +#define RX_MSDU_LINK_PN_127_96_MSB 31 +#define RX_MSDU_LINK_PN_127_96_MASK 0xffffffff + + +/* Description MSDU_0 + + When First_RX_MSDU_link_struct is set, this MSDU is the + first in the MPDU + + When First_RX_MSDU_link_struct is NOT set, this MSDU follows + the last MSDU in the previous RX_MSDU_link data structure + +*/ + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + +/* Description MSDU_1 + + Details of next MSDU in this (MSDU flow) linked list +*/ + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + +/* Description MSDU_2 + + Details of next MSDU in this (MSDU flow) linked list +*/ + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + +/* Description MSDU_3 + + Details of next MSDU in this (MSDU flow) linked list +*/ + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + +/* Description MSDU_4 + + Details of next MSDU in this (MSDU flow) linked list +*/ + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + +/* Description MSDU_5 + + Details of next MSDU in this (MSDU flow) linked list +*/ + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + + +#endif // RX_MSDU_LINK diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_msdu_start.h b/drivers/staging/fw-api/hw/qcn6432/rx_msdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..f38103c1da163191662cb4bddb0a5b4ffe12d158 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_msdu_start.h @@ -0,0 +1,766 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MSDU_START_H_ +#define _RX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_START 10 + +#define NUM_OF_QWORDS_RX_MSDU_START 5 + + +struct rx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] + sw_frame_group_id : 7, // [8:2] + reserved_0 : 7, // [15:9] + phy_ppdu_id : 16; // [31:16] + uint32_t msdu_length : 14, // [13:0] + stbc : 1, // [14:14] + ipsec_esp : 1, // [15:15] + l3_offset : 7, // [22:16] + ipsec_ah : 1, // [23:23] + l4_offset : 8; // [31:24] + uint32_t msdu_number : 8, // [7:0] + decap_format : 2, // [9:8] + ipv4_proto : 1, // [10:10] + ipv6_proto : 1, // [11:11] + tcp_proto : 1, // [12:12] + udp_proto : 1, // [13:13] + ip_frag : 1, // [14:14] + tcp_only_ack : 1, // [15:15] + da_is_bcast_mcast : 1, // [16:16] + toeplitz_hash_sel : 2, // [18:17] + ip_fixed_header_valid : 1, // [19:19] + ip_extn_header_valid : 1, // [20:20] + tcp_udp_header_valid : 1, // [21:21] + mesh_control_present : 1, // [22:22] + ldpc : 1, // [23:23] + ip4_protocol_ip6_next_header : 8; // [31:24] + uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] + uint32_t flow_id_toeplitz : 32; // [31:0] + uint32_t user_rssi : 8, // [7:0] + pkt_type : 4, // [11:8] + sgi : 2, // [13:12] + rate_mcs : 4, // [17:14] + receive_bandwidth : 3, // [20:18] + reception_type : 3, // [23:21] + mimo_ss_bitmap : 8; // [31:24] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t vlan_ctag_ci : 16, // [15:0] + vlan_stag_ci : 16; // [31:16] +#else + uint32_t phy_ppdu_id : 16, // [31:16] + reserved_0 : 7, // [15:9] + sw_frame_group_id : 7, // [8:2] + rxpcu_mpdu_filter_in_category : 2; // [1:0] + uint32_t l4_offset : 8, // [31:24] + ipsec_ah : 1, // [23:23] + l3_offset : 7, // [22:16] + ipsec_esp : 1, // [15:15] + stbc : 1, // [14:14] + msdu_length : 14; // [13:0] + uint32_t ip4_protocol_ip6_next_header : 8, // [31:24] + ldpc : 1, // [23:23] + mesh_control_present : 1, // [22:22] + tcp_udp_header_valid : 1, // [21:21] + ip_extn_header_valid : 1, // [20:20] + ip_fixed_header_valid : 1, // [19:19] + toeplitz_hash_sel : 2, // [18:17] + da_is_bcast_mcast : 1, // [16:16] + tcp_only_ack : 1, // [15:15] + ip_frag : 1, // [14:14] + udp_proto : 1, // [13:13] + tcp_proto : 1, // [12:12] + ipv6_proto : 1, // [11:11] + ipv4_proto : 1, // [10:10] + decap_format : 2, // [9:8] + msdu_number : 8; // [7:0] + uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] + uint32_t flow_id_toeplitz : 32; // [31:0] + uint32_t mimo_ss_bitmap : 8, // [31:24] + reception_type : 3, // [23:21] + receive_bandwidth : 3, // [20:18] + rate_mcs : 4, // [17:14] + sgi : 2, // [13:12] + pkt_type : 4, // [11:8] + user_rssi : 8; // [7:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t vlan_stag_ci : 16, // [31:16] + vlan_ctag_ci : 16; // [15:0] +#endif +}; + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + This MPDU passed the normal frame + filter programming of rxpcu + This MPDU did NOT pass the + regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + This MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + +*/ + +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + +/* Description SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. This + field indicates to what sw classification this MPDU is + mapped. + The classification is given in priority order + + + + + + This includes mpdus of + type Data Null. + This includes QoS + Null frames except in UL MU or TB PPDUs. + This includes + QoS Null frames in UL MU or TB PPDUs. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + PHY reported an error + + + +*/ + +#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + +/* Description RESERVED_0 + + +*/ + +#define RX_MSDU_START_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_MSDU_START_RESERVED_0_LSB 9 +#define RX_MSDU_START_RESERVED_0_MSB 15 +#define RX_MSDU_START_RESERVED_0_MASK 0x000000000000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_START_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_START_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_START_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description MSDU_LENGTH + + MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation +*/ + +#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x0000000000000000 +#define RX_MSDU_START_MSDU_LENGTH_LSB 32 +#define RX_MSDU_START_MSDU_LENGTH_MSB 45 +#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff00000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define RX_MSDU_START_STBC_OFFSET 0x0000000000000000 +#define RX_MSDU_START_STBC_LSB 46 +#define RX_MSDU_START_STBC_MSB 46 +#define RX_MSDU_START_STBC_MASK 0x0000400000000000 + + +/* Description IPSEC_ESP + + Set if IPv4/v6 packet is using IPsec ESP +*/ + +#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x0000000000000000 +#define RX_MSDU_START_IPSEC_ESP_LSB 47 +#define RX_MSDU_START_IPSEC_ESP_MSB 47 +#define RX_MSDU_START_IPSEC_ESP_MASK 0x0000800000000000 + + +/* Description L3_OFFSET + + Depending upon mode bit, this field either indicates the + L3 offset in bytes from the start of the RX_HEADER or the + IP offset in bytes from the start of the packet after decapsulation. + The latter is only valid if ipv4_proto or ipv6_proto is + set. +*/ + +#define RX_MSDU_START_L3_OFFSET_OFFSET 0x0000000000000000 +#define RX_MSDU_START_L3_OFFSET_LSB 48 +#define RX_MSDU_START_L3_OFFSET_MSB 54 +#define RX_MSDU_START_L3_OFFSET_MASK 0x007f000000000000 + + +/* Description IPSEC_AH + + Set if IPv4/v6 packet is using IPsec AH +*/ + +#define RX_MSDU_START_IPSEC_AH_OFFSET 0x0000000000000000 +#define RX_MSDU_START_IPSEC_AH_LSB 55 +#define RX_MSDU_START_IPSEC_AH_MSB 55 +#define RX_MSDU_START_IPSEC_AH_MASK 0x0080000000000000 + + +/* Description L4_OFFSET + + Depending upon mode bit, this field either indicates the + L4 offset nin bytes from the start of RX_HEADER(only valid + if either ipv4_proto or ipv6_proto is set to 1) or indicates + the offset in bytes to the start of TCP or UDP header from + the start of the IP header after decapsulation(Only valid + if tcp_proto or udp_proto is set). The value 0 indicates + that the offset is longer than 127 bytes. +*/ + +#define RX_MSDU_START_L4_OFFSET_OFFSET 0x0000000000000000 +#define RX_MSDU_START_L4_OFFSET_LSB 56 +#define RX_MSDU_START_L4_OFFSET_MSB 63 +#define RX_MSDU_START_L4_OFFSET_MASK 0xff00000000000000 + + +/* Description MSDU_NUMBER + + Indicates the MSDU number within a MPDU. This value is + reset to zero at the start of each MPDU. If the number + of MSDU exceeds 255 this number will wrap using modulo 256. + +*/ + +#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x0000000000000008 +#define RX_MSDU_START_MSDU_NUMBER_LSB 0 +#define RX_MSDU_START_MSDU_NUMBER_MSB 7 +#define RX_MSDU_START_MSDU_NUMBER_MASK 0x00000000000000ff + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x0000000000000008 +#define RX_MSDU_START_DECAP_FORMAT_LSB 8 +#define RX_MSDU_START_DECAP_FORMAT_MSB 9 +#define RX_MSDU_START_DECAP_FORMAT_MASK 0x0000000000000300 + + +/* Description IPV4_PROTO + + Set if L2 layer indicates IPv4 protocol. +*/ + +#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IPV4_PROTO_LSB 10 +#define RX_MSDU_START_IPV4_PROTO_MSB 10 +#define RX_MSDU_START_IPV4_PROTO_MASK 0x0000000000000400 + + +/* Description IPV6_PROTO + + Set if L2 layer indicates IPv6 protocol. +*/ + +#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IPV6_PROTO_LSB 11 +#define RX_MSDU_START_IPV6_PROTO_MSB 11 +#define RX_MSDU_START_IPV6_PROTO_MASK 0x0000000000000800 + + +/* Description TCP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP protocol + indicates TCP. +*/ + +#define RX_MSDU_START_TCP_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TCP_PROTO_LSB 12 +#define RX_MSDU_START_TCP_PROTO_MSB 12 +#define RX_MSDU_START_TCP_PROTO_MASK 0x0000000000001000 + + +/* Description UDP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP protocol + indicates UDP. +*/ + +#define RX_MSDU_START_UDP_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_UDP_PROTO_LSB 13 +#define RX_MSDU_START_UDP_PROTO_MSB 13 +#define RX_MSDU_START_UDP_PROTO_MASK 0x0000000000002000 + + +/* Description IP_FRAG + + Indicates that either the IP More frag bit is set or IP + frag number is non-zero. If set indicates that this is + a fragmented IP packet. +*/ + +#define RX_MSDU_START_IP_FRAG_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP_FRAG_LSB 14 +#define RX_MSDU_START_IP_FRAG_MSB 14 +#define RX_MSDU_START_IP_FRAG_MASK 0x0000000000004000 + + +/* Description TCP_ONLY_ACK + + Set if only the TCP Ack bit is set in the TCP flags and + if the TCP payload is 0. +*/ + +#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x0000000000008000 + + +/* Description DA_IS_BCAST_MCAST + + The destination address is broadcast or multicast. +*/ + +#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000008 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x0000000000010000 + + +/* Description TOEPLITZ_HASH_SEL + + Actual choosen Hash. + + 0 -> Toeplitz hash of 2-tuple (IP source address, IP destination + address)1 -> Toeplitz hash of 4-tuple (IP source address, + IP destination address, L4 (TCP/UDP) source port, L4 (TCP/UDP) + destination port) + 2 -> Toeplitz of flow_id + 3 -> "Zero" is used + +*/ + +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x0000000000060000 + + +/* Description IP_FIXED_HEADER_VALID + + Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed + fully within first 256 bytes of the packet +*/ + +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x0000000000080000 + + +/* Description IP_EXTN_HEADER_VALID + + IPv6/IPv6 header, including IPv4 options and recognizable + extension headers parsed fully within first 256 bytes of + the packet +*/ + +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x0000000000100000 + + +/* Description TCP_UDP_HEADER_VALID + + Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP + header parsed fully within first 256 bytes of the packet + +*/ + +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x0000000000200000 + + +/* Description MESH_CONTROL_PRESENT + + When set, this MSDU includes the 'Mesh Control' field + +*/ + +#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000008 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x0000000000400000 + + +/* Description LDPC + + When set, indicates that LDPC coding was used. + +*/ + +#define RX_MSDU_START_LDPC_OFFSET 0x0000000000000008 +#define RX_MSDU_START_LDPC_LSB 23 +#define RX_MSDU_START_LDPC_MSB 23 +#define RX_MSDU_START_LDPC_MASK 0x0000000000800000 + + +/* Description IP4_PROTOCOL_IP6_NEXT_HEADER + + For IPv4 this is the 8 bit protocol field (when ipv4_proto + is set). For IPv6 this is the 8 bit next_header field (when + ipv6_proto is set). +*/ + +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00000000ff000000 + + +/* Description TOEPLITZ_HASH_2_OR_4 + + Controlled by multiple RxOLE registers for TCP/UDP over + IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple + IPv4 or IPv6 src/dest addresses is reported; or, Toeplitz + hash computed over 4-tuple IPv4 or IPv6 src/dest addresses + and src/dest ports is reported. The Flow_id_toeplitz hash + can also be reported here. Usually the hash reported here + is the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy + in 'RXPT_CLASSIFY_INFO'). + + Optionally the 3-tuple Toeplitz hash over IPv4 + or IPv6 src/dest addresses and L4 protocol can be reported + here. +*/ + +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 32 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 63 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 + + +/* Description FLOW_ID_TOEPLITZ + + Toeplitz hash of 5-tuple + {IP source address, IP destination address, IP source port, + IP destination port, L4 protocol} in case of non-IPSec. + + In case of IPSec - Toeplitz hash of 4-tuple + {IP source address, IP destination address, SPI, L4 protocol} + + Optionally the 3-tuple Toeplitz hash over IPv4 + or IPv6 src/dest addresses and L4 protocol can be reported + here. + + The relevant Toeplitz key registers are provided in RxOLE's + instance of common parser module. These registers are separate + from the Toeplitz keys used by ASE/FSE modules inside RxOLE.The + actual value will be passed on from common parser module + to RxOLE in one of the WHO_* TLVs. + +*/ + +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000010 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0x00000000ffffffff + + +/* Description USER_RSSI + + RSSI for this user + +*/ + +#define RX_MSDU_START_USER_RSSI_OFFSET 0x0000000000000010 +#define RX_MSDU_START_USER_RSSI_LSB 32 +#define RX_MSDU_START_USER_RSSI_MSB 39 +#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff00000000 + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RX_MSDU_START_PKT_TYPE_OFFSET 0x0000000000000010 +#define RX_MSDU_START_PKT_TYPE_LSB 40 +#define RX_MSDU_START_PKT_TYPE_MSB 43 +#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f0000000000 + + +/* Description SGI + + Field only valid when pkt type is HT, VHT or HE. + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define RX_MSDU_START_SGI_OFFSET 0x0000000000000010 +#define RX_MSDU_START_SGI_LSB 44 +#define RX_MSDU_START_SGI_MSB 45 +#define RX_MSDU_START_SGI_MASK 0x0000300000000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define RX_MSDU_START_RATE_MCS_OFFSET 0x0000000000000010 +#define RX_MSDU_START_RATE_MCS_LSB 46 +#define RX_MSDU_START_RATE_MCS_MSB 49 +#define RX_MSDU_START_RATE_MCS_MASK 0x0003c00000000000 + + +/* Description RECEIVE_BANDWIDTH + + Full receive Bandwidth + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000010 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 50 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 52 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c000000000000 + + +/* Description RECEPTION_TYPE + + Indicates what type of reception this is. + Basic SU reception (not + part of OFDMA or MIMO) + This is related to + DL type of reception + This is related to + DL type of reception + This is related + to DL type of reception + This is related + to UL type of reception + This is related + to UL type of reception + This is related + to UL type of reception + + +*/ + +#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x0000000000000010 +#define RX_MSDU_START_RECEPTION_TYPE_LSB 53 +#define RX_MSDU_START_RECEPTION_TYPE_MSB 55 +#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e0000000000000 + + +/* Description MIMO_SS_BITMAP + + Field only valid when Reception_type for the MPDU from this + STA is some form of MIMO reception + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + LSB related to SS 0 + + 0: spatial stream not used for this reception + 1: spatial stream used for this reception + + +*/ + +#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x0000000000000010 +#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 56 +#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 63 +#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff00000000000000 + + +/* Description PPDU_START_TIMESTAMP_31_0 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, lower 32 bits + +*/ + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000018 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + + +/* Description PPDU_START_TIMESTAMP_63_32 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, upper 32 bits + +*/ + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000018 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 + + +/* Description SW_PHY_META_DATA + + SW programmed Meta data provided by the PHY. + + Can be used for SW to indicate the channel the device is + on. + +*/ + +#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000020 +#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 +#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0x00000000ffffffff + + +/* Description VLAN_CTAG_CI + + 2 bytes of C-VLAN Tag Control Information from WHO_L2_LLC + +*/ + +#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x0000000000000020 +#define RX_MSDU_START_VLAN_CTAG_CI_LSB 32 +#define RX_MSDU_START_VLAN_CTAG_CI_MSB 47 +#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff00000000 + + +/* Description VLAN_STAG_CI + + 2 bytes of S-VLAN Tag Control Information from WHO_L2_LLC + in case of double VLAN +*/ + +#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x0000000000000020 +#define RX_MSDU_START_VLAN_STAG_CI_LSB 48 +#define RX_MSDU_START_VLAN_STAG_CI_MSB 63 +#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff000000000000 + + + +#endif // RX_MSDU_START diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_ack_report.h b/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_ack_report.h new file mode 100644 index 0000000000000000000000000000000000000000..5555f058db65002658b12a29d2f20ef0bc8f5258 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_ack_report.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PPDU_ACK_REPORT_H_ +#define _RX_PPDU_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2 + +#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1 + + +struct rx_ppdu_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ack_report ack_report_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct ack_report ack_report_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description ACK_REPORT_DETAILS + + Info indicating why the received frame needed a SIFS response. + +*/ + + +/* Description SELFGEN_RESPONSE_REASON + + Field that indicates why the received frame needs a response + in SIFS time. The possible responses are listed in order. + + + + + + Qboost trigger received + PSPOLL trigger received + Unscheduled APSD trigger received + + the CBF frame needs to be send as + a result of NDP or BRPOLL + 11ax trigger received for this + device + 11ax wildcardtrigger has + been received + 11ax wildcard trigger + for unassociated STAs has been received + EHT R1 trigger received for + this device + + + + Ranging NDP + LMR need + to be sent in response to ranging NDPA + NDP + + +*/ + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x000000000000000f + + +/* Description AX_TRIGGER_TYPE + + Field Only valid when selfgen_response_reason is an 11ax + related trigger + + The 11AX trigger type/ trigger number: + It identifies which trigger was received. + + + + + + + + + + + + + + + + + + +*/ + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000000f0 + + +/* Description SR_PPDU + + Field only valid with SRP Responder support + + Indicates if the received frame was sent using SRP as indicated + by the 'SR PPDU' bit in the 'CAS Control' in the 'HE A-Control' + in one of the MPDUs received + +*/ + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x0000000000000100 + + +/* Description RESERVED + + +*/ + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x000000000000fe00 + + +/* Description FRAME_CONTROL + + Field not valid when selfgen_response_reason is MU_UL_response_to_response + + + For SU receptions: + frame control field of the received frame + + In 11ah Mode of Operation, for non-NDP frames the BW information + is extracted from Frame Control fields [11:8]. + + Decode is as follows + + Bits[11] - Dynamic/Static + Bits[10:8] - Channel BW +*/ + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB 32 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB 63 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_PPDU_ACK_REPORT diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_end_user_stats.h new file mode 100644 index 0000000000000000000000000000000000000000..63069e303920c01c7c142d29bb1cda3c46107ae7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_end_user_stats.h @@ -0,0 +1,1839 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PPDU_END_USER_STATS_H_ +#define _RX_PPDU_END_USER_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 + +#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15 + + +struct rx_ppdu_end_user_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t sta_full_aid : 13, // [12:0] + mcs : 4, // [16:13] + nss : 3, // [19:17] + expected_response_ack_or_ba : 1, // [20:20] + reserved_1a : 11; // [31:21] + uint32_t sw_peer_id : 16, // [15:0] + mpdu_cnt_fcs_err : 11, // [26:16] + sw2rxdma0_buf_source_used : 1, // [27:27] + fw2rxdma_pmac0_buf_source_used : 1, // [28:28] + sw2rxdma1_buf_source_used : 1, // [29:29] + sw2rxdma_exception_buf_source_used : 1, // [30:30] + fw2rxdma_pmac1_buf_source_used : 1; // [31:31] + uint32_t mpdu_cnt_fcs_ok : 11, // [10:0] + frame_control_info_valid : 1, // [11:11] + qos_control_info_valid : 1, // [12:12] + ht_control_info_valid : 1, // [13:13] + data_sequence_control_info_valid : 1, // [14:14] + ht_control_info_null_valid : 1, // [15:15] + rxdma2fw_pmac1_ring_used : 1, // [16:16] + rxdma2reo_ring_used : 1, // [17:17] + rxdma2fw_pmac0_ring_used : 1, // [18:18] + rxdma2sw_ring_used : 1, // [19:19] + rxdma_release_ring_used : 1, // [20:20] + ht_control_field_pkt_type : 4, // [24:21] + rxdma2reo_remote0_ring_used : 1, // [25:25] + rxdma2reo_remote1_ring_used : 1, // [26:26] + reserved_3b : 5; // [31:27] + uint32_t ast_index : 16, // [15:0] + frame_control_field : 16; // [31:16] + uint32_t first_data_seq_ctrl : 16, // [15:0] + qos_control_field : 16; // [31:16] + uint32_t ht_control_field : 32; // [31:0] + uint32_t fcs_ok_bitmap_31_0 : 32; // [31:0] + uint32_t fcs_ok_bitmap_63_32 : 32; // [31:0] + uint32_t udp_msdu_count : 16, // [15:0] + tcp_msdu_count : 16; // [31:16] + uint32_t other_msdu_count : 16, // [15:0] + tcp_ack_msdu_count : 16; // [31:16] + uint32_t sw_response_reference_ptr : 32; // [31:0] + uint32_t received_qos_data_tid_bitmap : 16, // [15:0] + received_qos_data_tid_eosp_bitmap : 16; // [31:16] + uint32_t qosctrl_15_8_tid0 : 8, // [7:0] + qosctrl_15_8_tid1 : 8, // [15:8] + qosctrl_15_8_tid2 : 8, // [23:16] + qosctrl_15_8_tid3 : 8; // [31:24] + uint32_t qosctrl_15_8_tid4 : 8, // [7:0] + qosctrl_15_8_tid5 : 8, // [15:8] + qosctrl_15_8_tid6 : 8, // [23:16] + qosctrl_15_8_tid7 : 8; // [31:24] + uint32_t qosctrl_15_8_tid8 : 8, // [7:0] + qosctrl_15_8_tid9 : 8, // [15:8] + qosctrl_15_8_tid10 : 8, // [23:16] + qosctrl_15_8_tid11 : 8; // [31:24] + uint32_t qosctrl_15_8_tid12 : 8, // [7:0] + qosctrl_15_8_tid13 : 8, // [15:8] + qosctrl_15_8_tid14 : 8, // [23:16] + qosctrl_15_8_tid15 : 8; // [31:24] + uint32_t mpdu_ok_byte_count : 25, // [24:0] + ampdu_delim_ok_count_6_0 : 7; // [31:25] + uint32_t ampdu_delim_err_count : 25, // [24:0] + ampdu_delim_ok_count_13_7 : 7; // [31:25] + uint32_t mpdu_err_byte_count : 25, // [24:0] + ampdu_delim_ok_count_20_14 : 7; // [31:25] + uint32_t non_consecutive_delimiter_err : 16, // [15:0] + retried_msdu_count : 16; // [31:16] + uint32_t ht_control_null_field : 32; // [31:0] + uint32_t sw_response_reference_ptr_ext : 32; // [31:0] + uint32_t corrupted_due_to_fifo_delay : 1, // [0:0] + frame_control_info_null_valid : 1, // [1:1] + frame_control_field_null : 16, // [17:2] + retried_mpdu_count : 11, // [28:18] + reserved_23a : 3; // [31:29] + uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] + sw_frame_group_id : 7, // [8:2] + reserved_24a : 4, // [12:9] + frame_control_info_mgmt_ctrl_valid : 1, // [13:13] + mac_addr_ad2_valid : 1, // [14:14] + mcast_bcast : 1, // [15:15] + frame_control_field_mgmt_ctrl : 16; // [31:16] + uint32_t user_ppdu_len : 24, // [23:0] + reserved_25a : 8; // [31:24] + uint32_t mac_addr_ad2_31_0 : 32; // [31:0] + uint32_t mac_addr_ad2_47_32 : 16, // [15:0] + amsdu_msdu_count : 16; // [31:16] + uint32_t non_amsdu_msdu_count : 16, // [15:0] + ucast_msdu_count : 16; // [31:16] + uint32_t bcast_msdu_count : 16, // [15:0] + mcast_bcast_msdu_count : 16; // [31:16] +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t reserved_1a : 11, // [31:21] + expected_response_ack_or_ba : 1, // [20:20] + nss : 3, // [19:17] + mcs : 4, // [16:13] + sta_full_aid : 13; // [12:0] + uint32_t fw2rxdma_pmac1_buf_source_used : 1, // [31:31] + sw2rxdma_exception_buf_source_used : 1, // [30:30] + sw2rxdma1_buf_source_used : 1, // [29:29] + fw2rxdma_pmac0_buf_source_used : 1, // [28:28] + sw2rxdma0_buf_source_used : 1, // [27:27] + mpdu_cnt_fcs_err : 11, // [26:16] + sw_peer_id : 16; // [15:0] + uint32_t reserved_3b : 5, // [31:27] + rxdma2reo_remote1_ring_used : 1, // [26:26] + rxdma2reo_remote0_ring_used : 1, // [25:25] + ht_control_field_pkt_type : 4, // [24:21] + rxdma_release_ring_used : 1, // [20:20] + rxdma2sw_ring_used : 1, // [19:19] + rxdma2fw_pmac0_ring_used : 1, // [18:18] + rxdma2reo_ring_used : 1, // [17:17] + rxdma2fw_pmac1_ring_used : 1, // [16:16] + ht_control_info_null_valid : 1, // [15:15] + data_sequence_control_info_valid : 1, // [14:14] + ht_control_info_valid : 1, // [13:13] + qos_control_info_valid : 1, // [12:12] + frame_control_info_valid : 1, // [11:11] + mpdu_cnt_fcs_ok : 11; // [10:0] + uint32_t frame_control_field : 16, // [31:16] + ast_index : 16; // [15:0] + uint32_t qos_control_field : 16, // [31:16] + first_data_seq_ctrl : 16; // [15:0] + uint32_t ht_control_field : 32; // [31:0] + uint32_t fcs_ok_bitmap_31_0 : 32; // [31:0] + uint32_t fcs_ok_bitmap_63_32 : 32; // [31:0] + uint32_t tcp_msdu_count : 16, // [31:16] + udp_msdu_count : 16; // [15:0] + uint32_t tcp_ack_msdu_count : 16, // [31:16] + other_msdu_count : 16; // [15:0] + uint32_t sw_response_reference_ptr : 32; // [31:0] + uint32_t received_qos_data_tid_eosp_bitmap : 16, // [31:16] + received_qos_data_tid_bitmap : 16; // [15:0] + uint32_t qosctrl_15_8_tid3 : 8, // [31:24] + qosctrl_15_8_tid2 : 8, // [23:16] + qosctrl_15_8_tid1 : 8, // [15:8] + qosctrl_15_8_tid0 : 8; // [7:0] + uint32_t qosctrl_15_8_tid7 : 8, // [31:24] + qosctrl_15_8_tid6 : 8, // [23:16] + qosctrl_15_8_tid5 : 8, // [15:8] + qosctrl_15_8_tid4 : 8; // [7:0] + uint32_t qosctrl_15_8_tid11 : 8, // [31:24] + qosctrl_15_8_tid10 : 8, // [23:16] + qosctrl_15_8_tid9 : 8, // [15:8] + qosctrl_15_8_tid8 : 8; // [7:0] + uint32_t qosctrl_15_8_tid15 : 8, // [31:24] + qosctrl_15_8_tid14 : 8, // [23:16] + qosctrl_15_8_tid13 : 8, // [15:8] + qosctrl_15_8_tid12 : 8; // [7:0] + uint32_t ampdu_delim_ok_count_6_0 : 7, // [31:25] + mpdu_ok_byte_count : 25; // [24:0] + uint32_t ampdu_delim_ok_count_13_7 : 7, // [31:25] + ampdu_delim_err_count : 25; // [24:0] + uint32_t ampdu_delim_ok_count_20_14 : 7, // [31:25] + mpdu_err_byte_count : 25; // [24:0] + uint32_t retried_msdu_count : 16, // [31:16] + non_consecutive_delimiter_err : 16; // [15:0] + uint32_t ht_control_null_field : 32; // [31:0] + uint32_t sw_response_reference_ptr_ext : 32; // [31:0] + uint32_t reserved_23a : 3, // [31:29] + retried_mpdu_count : 11, // [28:18] + frame_control_field_null : 16, // [17:2] + frame_control_info_null_valid : 1, // [1:1] + corrupted_due_to_fifo_delay : 1; // [0:0] + uint32_t frame_control_field_mgmt_ctrl : 16, // [31:16] + mcast_bcast : 1, // [15:15] + mac_addr_ad2_valid : 1, // [14:14] + frame_control_info_mgmt_ctrl_valid : 1, // [13:13] + reserved_24a : 4, // [12:9] + sw_frame_group_id : 7, // [8:2] + rxpcu_mpdu_filter_in_category : 2; // [1:0] + uint32_t reserved_25a : 8, // [31:24] + user_ppdu_len : 24; // [23:0] + uint32_t mac_addr_ad2_31_0 : 32; // [31:0] + uint32_t amsdu_msdu_count : 16, // [31:16] + mac_addr_ad2_47_32 : 16; // [15:0] + uint32_t ucast_msdu_count : 16, // [31:16] + non_amsdu_msdu_count : 16; // [15:0] + uint32_t mcast_bcast_msdu_count : 16, // [31:16] + bcast_msdu_count : 16; // [15:0] +#endif +}; + + +/* Description RXPCU_CLASSIFICATION_DETAILS + + Details related to what RXPCU classification types of MPDUs + have been received +*/ + + +/* Description FILTER_PASS_MPDUS + + When set, at least one Filter Pass MPDU has been received. + FCS might or might not have been passing. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 + + +/* Description FILTER_PASS_MPDUS_FCS_OK + + When set, at least one Filter Pass MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 + + +/* Description MONITOR_DIRECT_MPDUS + + When set, at least one Monitor Direct MPDU has been received. + FCS might or might not have been passing + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 + + +/* Description MONITOR_DIRECT_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 + + +/* Description MONITOR_OTHER_MPDUS + + When set, at least one Monitor Direct MPDU has been received. + FCS might or might not have been passing. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 + + +/* Description MONITOR_OTHER_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 + + +/* Description PHYRX_ABORT_RECEIVED + + When set, PPDU reception was aborted by the PHY + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 + + +/* Description FILTER_PASS_MONITOR_OVRD_MPDUS + + When set, at least one 'Filter Pass Monitor Override' MPDU + has been received. FCS might or might not have been passing. + + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 + + +/* Description FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK + + When set, at least one 'Filter Pass Monitor Override' MPDU + has been received that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 + + +/* Description RESERVED_0 + + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description STA_FULL_AID + + Consumer: FW + Producer: RXPCU + + The full AID of this station. + + +*/ + +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 + + +/* Description MCS + + MCS of the received frame + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_MCS_LSB 45 +#define RX_PPDU_END_USER_STATS_MCS_MSB 48 +#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e00000000000 + + +/* Description NSS + + Number of spatial streams. + + NOTE: RXPCU derives this from the 'Mimo_ss_bitmap' + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_NSS_LSB 49 +#define RX_PPDU_END_USER_STATS_NSS_MSB 51 +#define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e000000000000 + + +/* Description EXPECTED_RESPONSE_ACK_OR_BA + + When set, it indicates an Ack or BA matching 'EXPECTED_RESPONSE' + from TXPCU +*/ + +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 52 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 52 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0010000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 53 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe0000000000000 + + +/* Description SW_PEER_ID + + This field indicates a unique peer identifier, set from + the field 'sw_peer_id' in the AST entry corresponding to + this MPDU. It is provided by RXPCU. + A value of 0xFFFF indicates no AST entry was found or no + AST search was performed. + +*/ + +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff + + +/* Description MPDU_CNT_FCS_ERR + + The number of MPDUs received from this STA in this PPDU + with FCS errors + +*/ + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 + + +/* Description SW2RXDMA0_BUF_SOURCE_USED + + Field filled in by RXDMA + + When set, RXDMA has used the sw2rxdma0 buffer ring as source + for at least one of the frames in this PPDU. +*/ + +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 + + +/* Description FW2RXDMA_PMAC0_BUF_SOURCE_USED + + Field filled in by RXDMA + + When set, RXDMA has used the fw2rxdma buffer ring for PMAC0 + as source for at least one of the frames in this PPDU. +*/ + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x0000000010000000 + + +/* Description SW2RXDMA1_BUF_SOURCE_USED + + Field filled in by RXDMA + + When set, RXDMA has used the sw2rxdma1 buffer ring as source + for at least one of the frames in this PPDU. +*/ + +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 + + +/* Description SW2RXDMA_EXCEPTION_BUF_SOURCE_USED + + Field filled in by RXDMA + + When set, RXDMA has used the sw2rxdma_exception buffer ring + as source for at least one of the frames in this PPDU. +*/ + +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x0000000040000000 + + +/* Description FW2RXDMA_PMAC1_BUF_SOURCE_USED + + Field filled in by RXDMA + + When set, RXDMA has used the fw2rxdma buffer ring for PMAC1 + as source for at least one of the frames in this PPDU. +*/ + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x0000000080000000 + + +/* Description MPDU_CNT_FCS_OK + + The number of MPDUs received from this STA in this PPDU + with correct FCS + +*/ + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 + + +/* Description FRAME_CONTROL_INFO_VALID + + When set, the frame_control_info field contains valid information + + +*/ + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 + + +/* Description QOS_CONTROL_INFO_VALID + + When set, the QoS_control_info field contains valid information + + +*/ + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 + + +/* Description HT_CONTROL_INFO_VALID + + When set, the HT_control_field contains valid information + + +*/ + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 + + +/* Description DATA_SEQUENCE_CONTROL_INFO_VALID + + When set, the First_data_seq_ctrl field contains valid information + + +*/ + +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 + + +/* Description HT_CONTROL_INFO_NULL_VALID + + When set, the HT_control_NULL_field contains valid information + + +*/ + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 + + +/* Description RXDMA2FW_PMAC1_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 48 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 48 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x0001000000000000 + + +/* Description RXDMA2REO_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 49 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 49 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x0002000000000000 + + +/* Description RXDMA2FW_PMAC0_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 50 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 50 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x0004000000000000 + + +/* Description RXDMA2SW_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 51 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 51 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x0008000000000000 + + +/* Description RXDMA_RELEASE_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 52 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 52 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x0010000000000000 + + +/* Description HT_CONTROL_FIELD_PKT_TYPE + + Field only valid when HT_control_info_valid or HT_control_info_NULL_valid + is set. + + Indicates what the PHY receive type was for receiving this + frame. Can help determine if the HT_CONTROL field shall + be interpreted as HT/VHT or HE. + + NOTE: later on in the 11ax IEEE spec a bit within the HT + control field was introduced that explicitly indicated + how to interpret the HT control field.... As HT, VHT, or + HE. + + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 + + +/* Description RXDMA2REO_REMOTE0_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 57 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 57 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x0200000000000000 + + +/* Description RXDMA2REO_REMOTE1_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 58 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 58 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x0400000000000000 + + +/* Description RESERVED_3B + + +*/ + +#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 59 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xf800000000000000 + + +/* Description AST_INDEX + + This field indicates the index of the AST entry corresponding + to this MPDU. It is provided by the GSE module instantiated + in RXPCU. + A value of 0xFFFF indicates an invalid AST index, meaning + that No AST entry was found or NO AST search was performed + + +*/ + +#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff + + +/* Description FRAME_CONTROL_FIELD + + Field only valid when Frame_control_info_valid is set. + + Last successfully received Frame_control field of data frame + (excluding Data NULL/ QoS Null) for this user + Mainly used to track the PM state of the transmitted device + + + NOTE: only data frame info is needed, as control and management + frames are already routed to the FW. + +*/ + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 + + +/* Description FIRST_DATA_SEQ_CTRL + + Field only valid when Data_sequence_control_info_valid is + set. + + Sequence control field of the first data frame (excluding + Data NULL or QoS Data null) received for this user with + correct FCS + + NOTE: only data frame info is needed, as control and management + frames are already routed to the FW. + +*/ + +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 + + +/* Description QOS_CONTROL_FIELD + + Field only valid when QoS_control_info_valid is set. + + Last successfully received QoS_control field of data frame + (excluding Data NULL/ QoS Null) for this user + + Note that in case of multi TID, this field can only reflect + the last properly received MPDU, and thus can not indicate + all potentially different TIDs that had been received earlier. + + + There are however per TID fields, that will contain among + other things all buffer status info: See + QoSCtrl_15_8_tid??? + +*/ + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 + + +/* Description HT_CONTROL_FIELD + + Field only valid when HT_control_info_valid is set. + + Last successfully received HT_CONTROL/VHT_CONTROL/HE_CONTROL + field of data frames, excluding QoS Null frames for this + user. + + NOTE: HT control fields from QoS Null frames are captured + in field HT_control_NULL_field + +*/ + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff + + +/* Description FCS_OK_BITMAP_31_0 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 + + +/* Description FCS_OK_BITMAP_63_32 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + + NOTE: for users 0, 1, 2 and 3, additional bitmap info (up + to 256 bitmap window) is provided in RX_PPDU_END_USER_STATS_EXT + TLV + +*/ + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff + + +/* Description UDP_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + that contain UDP frames. + +*/ + +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 + + +/* Description TCP_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + that contain TCP frames. + + (Note: This does NOT include TCP-ACK) + +*/ + +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 + + +/* Description OTHER_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + that contain neither UDP or TCP frames. + + Includes Management and control frames. + + +*/ + +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff + + +/* Description TCP_ACK_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + that contain TCP ack frames. + +*/ + +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 + + +/* Description SW_RESPONSE_REFERENCE_PTR + + Pointer that SW uses to refer back to an expected response + reception. Used for Rate adaptation purposes. + When a reception occurs that is not tied to an expected + response, this field is set to 0x0. + + Note: further on in this TLV there is also the field: Sw_response_reference_ptr_ext. + + +*/ + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 + + +/* Description RECEIVED_QOS_DATA_TID_BITMAP + + Whenever a frame is received that contains a QoS control + field (that includes QoS Data and/or QoS Null), the bit + in this field that corresponds to the received TID shall + be set. + ...Bitmap[0] = TID0 + ...Bitmap[1] = TID1 + Etc. + +*/ + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff + + +/* Description RECEIVED_QOS_DATA_TID_EOSP_BITMAP + + Field initialized to 0 + For every QoS Data frame that is correctly received, the + EOSP bit of that frame is copied over into the corresponding + TID related field. + Note that this implies that the bits here represent the + EOSP bit status for each TID of the last MPDU received for + that TID. + + received TID shall be set. + ...eosp_bitmap[0] = eosp of TID0 + ...eosp_bitmap[1] = eosp of TID1 + Etc. + +*/ + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 + + +/* Description QOSCTRL_15_8_TID0 + + Field only valid when Received_qos_data_tid_bitmap[0] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 0 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 + + +/* Description QOSCTRL_15_8_TID1 + + Field only valid when Received_qos_data_tid_bitmap[1] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 1 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 + + +/* Description QOSCTRL_15_8_TID2 + + Field only valid when Received_qos_data_tid_bitmap[2] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 2 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 + + +/* Description QOSCTRL_15_8_TID3 + + Field only valid when Received_qos_data_tid_bitmap[3] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 3 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 + + +/* Description QOSCTRL_15_8_TID4 + + Field only valid when Received_qos_data_tid_bitmap[4] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 4 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff + + +/* Description QOSCTRL_15_8_TID5 + + Field only valid when Received_qos_data_tid_bitmap[5] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 5 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 + + +/* Description QOSCTRL_15_8_TID6 + + Field only valid when Received_qos_data_tid_bitmap[6] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 6 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 + + +/* Description QOSCTRL_15_8_TID7 + + Field only valid when Received_qos_data_tid_bitmap[7] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 7 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 + + +/* Description QOSCTRL_15_8_TID8 + + Field only valid when Received_qos_data_tid_bitmap[8] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 8 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 + + +/* Description QOSCTRL_15_8_TID9 + + Field only valid when Received_qos_data_tid_bitmap[9] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 9 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 + + +/* Description QOSCTRL_15_8_TID10 + + Field only valid when Received_qos_data_tid_bitmap[10] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 10 + +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 + + +/* Description QOSCTRL_15_8_TID11 + + Field only valid when Received_qos_data_tid_bitmap[11] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 11 + +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 + + +/* Description QOSCTRL_15_8_TID12 + + Field only valid when Received_qos_data_tid_bitmap[12] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 12 + +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff + + +/* Description QOSCTRL_15_8_TID13 + + Field only valid when Received_qos_data_tid_bitmap[13] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 13 + +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 + + +/* Description QOSCTRL_15_8_TID14 + + Field only valid when Received_qos_data_tid_bitmap[14] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 14 + +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 + + +/* Description QOSCTRL_15_8_TID15 + + Field only valid when Received_qos_data_tid_bitmap[15] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 15 + +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 + + +/* Description MPDU_OK_BYTE_COUNT + + The number of bytes received within an MPDU for this user + with correct FCS. This includes the FCS field + + NOTE: + The sum of the four fields..... + Mpdu_ok_byte_count + + mpdu_err_byte_count + + (Ampdu_delim_ok_count x 4) + (Ampdu_delim_err_count x 4) + + .....is the total number of bytes that were received for + this user from the PHY. + + +*/ + +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 + + +/* Description AMPDU_DELIM_OK_COUNT_6_0 + + Number of AMPDU delimiter received with correct structure + + LSB 7 bits from this counter + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + + +*/ + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 + + +/* Description AMPDU_DELIM_ERR_COUNT + + The number of MPDU delimiter errors counted for this user. + + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + +*/ + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff + + +/* Description AMPDU_DELIM_OK_COUNT_13_7 + + Number of AMPDU delimiters received with correct structure + + Bits 13-7 from this counter + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + +*/ + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 + + +/* Description MPDU_ERR_BYTE_COUNT + + The number of bytes belonging to MPDUs with an FCS error. + This includes the FCS field. + + +*/ + +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 + + +/* Description AMPDU_DELIM_OK_COUNT_20_14 + + Number of AMPDU delimiters received with correct structure + + Bits 20-14 from this counter + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + + +*/ + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 + + +/* Description NON_CONSECUTIVE_DELIMITER_ERR + + The number of times an MPDU delimiter error is detected + that is not immediately preceded by another MPDU delimiter + also with FCS error. + + The counter saturates at 0xFFFF + + +*/ + +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff + + +/* Description RETRIED_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + that have the retry bit set. + +*/ + +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 + + +/* Description HT_CONTROL_NULL_FIELD + + Field only valid when HT_control_info_NULL_valid is set. + + + Last successfully received HT_CONTROL/VHT_CONTROL/HE_CONTROL + field from QoS Null frame for this user. + +*/ + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 + + +/* Description SW_RESPONSE_REFERENCE_PTR_EXT + + Extended Pointer info that SW uses to refer back to an expected + response transmission. Used for Rate adaptation purposes. + + When a reception occurs that is not tied to an expected + response, this field is set to 0x0. + + Note: earlier on in this TLV there is also the field: Sw_response_reference_ptr. + + +*/ + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff + + +/* Description CORRUPTED_DUE_TO_FIFO_DELAY + + Set if Rx PCU avoided a hang due to SFM delays by writing + a corrupted 'RX_PPDU_END_USER_STATS*' and/or 'RX_PPDU_END.' + +*/ + +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 + + +/* Description FRAME_CONTROL_INFO_NULL_VALID + + When set, Frame_control_field_null contains valid information + + +*/ + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 + + +/* Description FRAME_CONTROL_FIELD_NULL + + Field only valid when Frame_control_info_null_valid is set. + + + Last successfully received Frame_control field of Data Null/QoS + Null for this user, mainly used to track the PM state of + the transmitted device + +*/ + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 + + +/* Description RETRIED_MPDU_COUNT + + Field filled in by RXPCU + + The number of MPDUs without FCS error, that have the retry + bit set. + +*/ + +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 + + +/* Description RESERVED_23A + + +*/ + +#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that the last successfully + received MPDU was allowed to come into the receive path + by RXPCU. + The last MPDU passed the normal + frame filter programming of rxpcu + The last MPDU did NOT pass + the regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' + category. + The last MPDU did NOT pass + the regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + The last MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + +/* Description SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. This + field indicates to what sw classification the last successfully + received MPDU is mapped. + The classification is given in priority order + + + + + + This includes mpdus of + type Data Null. + This includes QoS + Null frames except in UL MU or TB PPDUs. + This includes + QoS Null frames in UL MU or TB PPDUs. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + PHY reported an error + + + +*/ + +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + +/* Description RESERVED_24A + + +*/ + +#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x0000000000001e00 + + +/* Description FRAME_CONTROL_INFO_MGMT_CTRL_VALID + + When set, Frame_control_field_mgmt_ctrl contains valid information. + + +*/ + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x0000000000002000 + + +/* Description MAC_ADDR_AD2_VALID + + When set, the fields mac_addr_ad2_... contain valid information. + + +*/ + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x0000000000004000 + + +/* Description MCAST_BCAST + + Multicast / broadcast indicator + + Only set when the MAC address 1 bit 0 is set indicating + mcast/bcast and the BSSID matches one of the BSSID registers, + for the last successfully received MPDU + +*/ + +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x0000000000008000 + + +/* Description FRAME_CONTROL_FIELD_MGMT_CTRL + + Field only valid when Frame_control_info_mgmt_ctrl_valid + is set + + Last successfully received 'Frame control' field of control + or management frames for this user, mainly used in Rx monitor + mode + +*/ + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0x00000000ffff0000 + + +/* Description USER_PPDU_LEN + + The sum of the mpdu_length fields of all the 'RX_MPDU_START' + TLVs generated for this user for this PPDU +*/ + +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 32 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 55 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff00000000 + + +/* Description RESERVED_25A + + +*/ + +#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 56 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff00000000000000 + + +/* Description MAC_ADDR_AD2_31_0 + + Field only valid when mac_addr_ad2_valid is set + + The least significant 4 bytes of the last successfully received + frame's MAC Address AD2 + +*/ + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x0000000000000068 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0x00000000ffffffff + + +/* Description MAC_ADDR_AD2_47_32 + + Field only valid when mac_addr_ad2_valid is set + + The 2 most significant bytes of the last successfully received + frame's MAC Address AD2 + +*/ + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000000000000068 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 32 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 47 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff00000000 + + +/* Description AMSDU_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of A-MSDUs that are part + of MPDUs without FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000068 +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 48 +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 63 +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff000000000000 + + +/* Description NON_AMSDU_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are not part of A-MSDUs that are + part of MPDUs without FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000070 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x000000000000ffff + + +/* Description UCAST_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + that are directed to a unicast destination address + +*/ + +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x0000000000000070 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0x00000000ffff0000 + + +/* Description BCAST_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + whose destination addresses are broadcast (0xFFFF_FFFF_FFFF) + + +*/ + +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 47 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff00000000 + + +/* Description MCAST_BCAST_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + whose destination addresses are either multicast or broadcast + + +*/ + +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 48 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 63 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff000000000000 + + + +#endif // RX_PPDU_END_USER_STATS diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_end_user_stats_ext.h new file mode 100644 index 0000000000000000000000000000000000000000..3e9cc4860838c9fce290cf6cdc532edf86e8a2bc --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_end_user_stats_ext.h @@ -0,0 +1,343 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ +#define _RX_PPDU_END_USER_STATS_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 + +#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4 + + +struct rx_ppdu_end_user_stats_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; // [31:0] + uint32_t fcs_ok_bitmap_127_96 : 32; // [31:0] + uint32_t fcs_ok_bitmap_159_128 : 32; // [31:0] + uint32_t fcs_ok_bitmap_191_160 : 32; // [31:0] + uint32_t fcs_ok_bitmap_223_192 : 32; // [31:0] + uint32_t fcs_ok_bitmap_255_224 : 32; // [31:0] + uint32_t corrupted_due_to_fifo_delay : 1, // [0:0] + reserved_7a : 31; // [31:1] +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; // [31:0] + uint32_t fcs_ok_bitmap_127_96 : 32; // [31:0] + uint32_t fcs_ok_bitmap_159_128 : 32; // [31:0] + uint32_t fcs_ok_bitmap_191_160 : 32; // [31:0] + uint32_t fcs_ok_bitmap_223_192 : 32; // [31:0] + uint32_t fcs_ok_bitmap_255_224 : 32; // [31:0] + uint32_t reserved_7a : 31, // [31:1] + corrupted_due_to_fifo_delay : 1; // [0:0] +#endif +}; + + +/* Description RXPCU_CLASSIFICATION_DETAILS + + Details related to what RXPCU classification types of MPDUs + have been received +*/ + + +/* Description FILTER_PASS_MPDUS + + When set, at least one Filter Pass MPDU has been received. + FCS might or might not have been passing. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 + + +/* Description FILTER_PASS_MPDUS_FCS_OK + + When set, at least one Filter Pass MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 + + +/* Description MONITOR_DIRECT_MPDUS + + When set, at least one Monitor Direct MPDU has been received. + FCS might or might not have been passing + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 + + +/* Description MONITOR_DIRECT_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 + + +/* Description MONITOR_OTHER_MPDUS + + When set, at least one Monitor Direct MPDU has been received. + FCS might or might not have been passing. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 + + +/* Description MONITOR_OTHER_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 + + +/* Description PHYRX_ABORT_RECEIVED + + When set, PPDU reception was aborted by the PHY + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 + + +/* Description FILTER_PASS_MONITOR_OVRD_MPDUS + + When set, at least one 'Filter Pass Monitor Override' MPDU + has been received. FCS might or might not have been passing. + + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 + + +/* Description FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK + + When set, at least one 'Filter Pass Monitor Override' MPDU + has been received that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 + + +/* Description RESERVED_0 + + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description FCS_OK_BITMAP_95_64 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff00000000 + + +/* Description FCS_OK_BITMAP_127_96 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0x00000000ffffffff + + +/* Description FCS_OK_BITMAP_159_128 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff00000000 + + +/* Description FCS_OK_BITMAP_191_160 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0x00000000ffffffff + + +/* Description FCS_OK_BITMAP_223_192 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff00000000 + + +/* Description FCS_OK_BITMAP_255_224 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0x00000000ffffffff + + +/* Description CORRUPTED_DUE_TO_FIFO_DELAY + + Set if Rx PCU avoided a hang due to SFM delays by writing + a corrupted 'RX_PPDU_END_USER_STATS*' and/or 'RX_PPDU_END.' + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 + + +/* Description RESERVED_7A + + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 33 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe00000000 + + + +#endif // RX_PPDU_END_USER_STATS_EXT diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_no_ack_report.h b/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_no_ack_report.h new file mode 100644 index 0000000000000000000000000000000000000000..c0db1395059dac92ec1664b62bec06ba92e2e099 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_no_ack_report.h @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PPDU_NO_ACK_REPORT_H_ +#define _RX_PPDU_NO_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "no_ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 + +#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2 + + +struct rx_ppdu_no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct no_ack_report no_ack_report_details; +#else + struct no_ack_report no_ack_report_details; +#endif +}; + + +/* Description NO_ACK_REPORT_DETAILS + + Info indicating why frame did not require a response transmission + in SIFS time. +*/ + + +/* Description NO_ACK_TRANSMIT_REASON + + Field that indicates why the received frame is not needing + any transmit response in SIFS time. + + The possible responses are listed in order. + + All received frames have + FCS errors. + All received + frames did not require a response. + Broadcast frame received + Multicast frame received + Frames received are not directed + to this device (based on addr1) + The AST entry indicated that NO + ACK shall be send + PHY dropped the incoming frame + dur to GID mismatch + PHY dropped the incoming frame + dur to AID mismatch + PHY reported an error during + reception. For details, see the 'phy_error...' fields + The requested BW for the + CTS response frame is not available + An NDPA frame got received + An NDP frame got received + a trigger frame was received, + but due to NAV setting, no response could be generated + A trigger frame was received, + but this device's AID was not in the list + No ACK is needed as + SW asked RXPCU to send a abort_request to the PHYRX + placeholder in case non + of the above properly cover the reasons + + Also see the field SR_PPDU_during_OBSS. + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x000000000000000f + + +/* Description MACRX_ABORT_REASON + + Field only valid when No_ack_transmit_reason is set to NO_ACK_MAC_ABORT_REQ + + + Error field received from MACRX_ABORT_REQUEST.Macrx_abort_reason[2:0] + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000f0 + + +/* Description PHYRX_ABORT_REASON + + Field only valid when No_ack_transmit_reason is set to NO_ACK_PHY_error + + + Error field received from PHYRX_ABORT_REQUEST.Phyrx_abort_reason + + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000000000ff00 + + +/* Description FRAME_CONTROL + + frame control field of the received (first properly received) + frame + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 + + +/* Description RX_PPDU_DURATION + + The length of this PPDU reception in us + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 32 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 55 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff00000000 + + +/* Description SR_PPDU_DURING_OBSS + + Field only valid with SRP Responder support + + Indicates that the received frame was sent using SRP as + indicated by the 'SR PPDU' bit in the 'CAS Control' in the + 'HE A-Control' in one of the MPDUs received, and that the + response could not be generated due to OBSS traffic setting + the NAV + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 56 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 56 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x0100000000000000 + + +/* Description SELFGEN_RESPONSE_REASON_TO_SR_PPDU + + Field only valid with SRP Responder support + + This field indicates why the received SR PPDU needs a response + in SIFS time. The e-num used is the same as in the field + selfgen_response_reason in 'ACK_REPORT' structure although + some of these will be unused in case of an SR PPDU. + + + + + Qboost trigger received + PSPOLL trigger received + Unscheduled APSD trigger received + + the CBF frame needs to be send as + a result of NDP or BRPOLL + 11ax trigger received for this + device + 11ax wildcardtrigger has + been received + 11ax wildcard trigger + for unassociated STAs has been received + EHT R1 trigger received for + this device + + + Ranging NDP + LMR need + to be sent in response to ranging NDPA + NDP + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000 + + +/* Description RESERVED_1 + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 61 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 63 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe000000000000000 + + +/* Description PRE_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the first received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + After power up, this field is all initialized to 0 + + Bits: [31:28]: always 0 + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff + + +/* Description FIRST_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the first received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + If no COEX_STATUS_BROADCAST tlv is received during this + PPDU reception, this field will be set to 0 + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000 + + +/* Description RESERVED_2 + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0x00000000ff000000 + + +/* Description SECOND_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the second received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + If no second COEX_STATUS_BROADCAST tlv is received during + this PPDU reception, this field will be set to 0 + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000 + + +/* Description RESERVED_3 + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 44 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 63 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff00000000000 + + + +#endif // RX_PPDU_NO_ACK_REPORT diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_start.h b/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..beef101ceebda3aa97e27cbd3da6dc180bfb3d79 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_start.h @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PPDU_START_H_ +#define _RX_PPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_PPDU_START 6 + +#define NUM_OF_QWORDS_RX_PPDU_START 3 + + +struct rx_ppdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, // [15:0] + preamble_time_to_rxframe : 8, // [23:16] + reserved_0a : 8; // [31:24] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t rxframe_assert_timestamp : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0a : 8, // [31:24] + preamble_time_to_rxframe : 8, // [23:16] + phy_ppdu_id : 16; // [15:0] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t rxframe_assert_timestamp : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_START_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff + + +/* Description PREAMBLE_TIME_TO_RXFRAME + + The amount of time (in us) of the frame being put on the + medium, and PHY raising rx_frame + + From 'PHYRX_RSSI_LEGACY. Preamble_time_to_rx_frame' + + +*/ + +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 + + +/* Description RESERVED_0A + + Reserved + +*/ + +#define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_PPDU_START_RESERVED_0A_LSB 24 +#define RX_PPDU_START_RESERVED_0A_MSB 31 +#define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 + + +/* Description SW_PHY_META_DATA + + SW programmed Meta data provided by the PHY. + + Can be used for SW to indicate the channel the device is + on. + + From 'PHYRX_RSSI_LEGACY.Sw_phy_meta_data' +*/ + +#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 +#define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 +#define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 +#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 + + +/* Description PPDU_START_TIMESTAMP_31_0 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, lower 32 bits. + + The timestamp is captured by the PHY and given to the MAC + in 'PHYRX_RSSI_LEGACY.ppdu_start_timestamp_*.' + +*/ + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + + +/* Description PPDU_START_TIMESTAMP_63_32 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, upper 32 bits. + + The timestamp is captured by the PHY and given to the MAC + in 'PHYRX_RSSI_LEGACY.ppdu_start_timestamp_*.' + +*/ + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 + + +/* Description RXFRAME_ASSERT_TIMESTAMP + + MAC timer Timestamp that indicates when PHY asserted the + 'rx_frame' signal for the reception of this PPDU + +*/ + +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 +#define RX_PPDU_START_TLV64_PADDING_LSB 32 +#define RX_PPDU_START_TLV64_PADDING_MSB 63 +#define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_PPDU_START diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_start_user_info.h b/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_start_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..703ad1824cac21c6b01aa641229524e607ed93bf --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_ppdu_start_user_info.h @@ -0,0 +1,625 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PPDU_START_USER_INFO_H_ +#define _RX_PPDU_START_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_user_info.h" +#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8 + +#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 4 + + +struct rx_ppdu_start_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_user_info receive_user_info_details; +#else + struct receive_user_info receive_user_info_details; +#endif +}; + + +/* Description RECEIVE_USER_INFO_DETAILS + + Overview of receive parameters that the MAC needs to prepend + to every received MSDU/MPDU. +*/ + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff + + +/* Description USER_RSSI + + RSSI for this user + Frequency domain RSSI measurement for this user. Based on + the channel estimate. + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 + + +/* Description PKT_TYPE + + Packet type: + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 + + +/* Description RECEPTION_TYPE + + Indicates what type of reception this is. + Basic SU reception (not + part of OFDMA or MU-MIMO) + This is related to + DL type of reception + This is related to + DL type of reception + This is related + to DL type of reception + This is related + to UL type of reception + This is related + to UL type of reception + This is related + to UL type of reception + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 35 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f00000000 + + +/* Description SGI + + Field only valid when pkt type is HT, VHT or HE. + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 36 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 37 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000003000000000 + + +/* Description HE_RANGING_NDP + + Set to 1 for expected HE TB ranging NDP Rx in response to + sounding/secure sounding ranging Trigger Tx + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_HE_RANGING_NDP_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_HE_RANGING_NDP_LSB 38 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_HE_RANGING_NDP_MSB 38 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_HE_RANGING_NDP_MASK 0x0000004000000000 + + +/* Description RESERVED_1A + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 39 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 39 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + + +/* Description MIMO_SS_BITMAP + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + LSB related to SS 0 + + 0: spatial stream not used for this reception + 1: spatial stream used for this reception + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 + + +/* Description RECEIVE_BANDWIDTH + + Full receive Bandwidth + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 + + +/* Description DL_OFDMA_USER_INDEX + + Field only valid in the of DL MU OFDMA reception + + The user number within the RU_allocation. + + This is needed for SW to determine the exact RU position + within the reception. + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 + + +/* Description DL_OFDMA_CONTENT_CHANNEL + + Field only valid in the of DL MU OFDMA/MIMO reception + + In case of DL MU reception, this field indicates the content + channel number where PHY found the RU information for this + user + + This is needed for SW to determine the exact RU position + within the reception. + + + + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 + + +/* Description RESERVED_2A + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x00000000000000fe + + +/* Description NSS + + Field only valid in case of Uplink_receive_type == mimo_only + OR ofdma_mimo + + Number of Spatial Streams occupied by the User + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 + + +/* Description STREAM_OFFSET + + Field only valid in case of Uplink_receive_type == mimo_only + OR ofdma_mimo + + Stream Offset from which the User occupies the Streams + + Note MAC: + directly from pdg_fes_setup, based on BW +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 + + +/* Description STA_DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 + + +/* Description LDPC + + When set, use LDPC transmission rates were used. + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 + + +/* Description RU_TYPE_80_0 + + Indicates the size of the RU in the first 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 + + +/* Description RU_TYPE_80_1 + + Indicates the size of the RU in the second 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 + + +/* Description RU_TYPE_80_2 + + Indicates the size of the RU in the third 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 + + +/* Description RU_TYPE_80_3 + + Indicates the size of the RU in the fourth 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 + + +/* Description RU_START_INDEX_80_0 + + RU index number to which User is assigned in the first 80 + MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 + + +/* Description RESERVED_3A + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 + + +/* Description RU_START_INDEX_80_1 + + RU index number to which User is assigned in the second + 80 MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 + + +/* Description RESERVED_3B + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 + + +/* Description RU_START_INDEX_80_2 + + RU index number to which User is assigned in the third 80 + MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 + + +/* Description RESERVED_3C + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 + + +/* Description RU_START_INDEX_80_3 + + RU index number to which User is assigned in the fourth + 80 MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 + + +/* Description RESERVED_3D + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000 + + +/* Description USER_FD_RSSI_SEG0 + + Frequency domain RSSI measurement for the lowest 80 MHz + subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff + + +/* Description USER_FD_RSSI_SEG1 + + Frequency domain RSSI measurement for the second lowest + 80 MHz subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 + + +/* Description USER_FD_RSSI_SEG2 + + Frequency domain RSSI measurement for the third lowest 80 + MHz subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff + + +/* Description USER_FD_RSSI_SEG3 + + Frequency domain RSSI measurement for the highest 80 MHz + subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 + + + +#endif // RX_PPDU_START_USER_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_preamble.h b/drivers/staging/fw-api/hw/qcn6432/rx_preamble.h new file mode 100644 index 0000000000000000000000000000000000000000..3f3214664377065078b151075965cd3b8fdde722 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_preamble.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PREAMBLE_H_ +#define _RX_PREAMBLE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_PREAMBLE 2 + +#define NUM_OF_QWORDS_RX_PREAMBLE 1 + + +struct rx_preamble { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, // [5:0] + pkt_type : 4, // [9:6] + direction : 1, // [10:10] + reserved_0a : 21; // [31:11] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0a : 21, // [31:11] + direction : 1, // [10:10] + pkt_type : 4, // [9:6] + num_users : 6; // [5:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description NUM_USERS + + The number of users in the receiving OFDMA frame. +*/ + +#define RX_PREAMBLE_NUM_USERS_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_NUM_USERS_LSB 0 +#define RX_PREAMBLE_NUM_USERS_MSB 5 +#define RX_PREAMBLE_NUM_USERS_MASK 0x000000000000003f + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_PKT_TYPE_LSB 6 +#define RX_PREAMBLE_PKT_TYPE_MSB 9 +#define RX_PREAMBLE_PKT_TYPE_MASK 0x00000000000003c0 + + +/* Description DIRECTION + + Field only valid in case of pkt_type = dot11ax + + + + +*/ + +#define RX_PREAMBLE_DIRECTION_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_DIRECTION_LSB 10 +#define RX_PREAMBLE_DIRECTION_MSB 10 +#define RX_PREAMBLE_DIRECTION_MASK 0x0000000000000400 + + +/* Description RESERVED_0A + + +*/ + +#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_RESERVED_0A_LSB 11 +#define RX_PREAMBLE_RESERVED_0A_MSB 31 +#define RX_PREAMBLE_RESERVED_0A_MASK 0x00000000fffff800 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_PREAMBLE_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_TLV64_PADDING_LSB 32 +#define RX_PREAMBLE_TLV64_PADDING_MSB 63 +#define RX_PREAMBLE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_PREAMBLE diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_reo_queue.h b/drivers/staging/fw-api/hw/qcn6432/rx_reo_queue.h new file mode 100644 index 0000000000000000000000000000000000000000..0dc7126e490e602120f016de6f6d6cdd65e498d2 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_reo_queue.h @@ -0,0 +1,1261 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_REO_QUEUE_H_ +#define _RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE 32 + + +struct rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t receive_queue_number : 16, // [15:0] + reserved_1b : 16; // [31:16] + uint32_t vld : 1, // [0:0] + associated_link_descriptor_counter : 2, // [2:1] + disable_duplicate_detection : 1, // [3:3] + soft_reorder_enable : 1, // [4:4] + ac : 2, // [6:5] + bar : 1, // [7:7] + rty : 1, // [8:8] + chk_2k_mode : 1, // [9:9] + oor_mode : 1, // [10:10] + ba_window_size : 10, // [20:11] + pn_check_needed : 1, // [21:21] + pn_shall_be_even : 1, // [22:22] + pn_shall_be_uneven : 1, // [23:23] + pn_handling_enable : 1, // [24:24] + pn_size : 2, // [26:25] + ignore_ampdu_flag : 1, // [27:27] + reserved_2b : 4; // [31:28] + uint32_t svld : 1, // [0:0] + ssn : 12, // [12:1] + current_index : 10, // [22:13] + seq_2k_error_detected_flag : 1, // [23:23] + pn_error_detected_flag : 1, // [24:24] + reserved_3a : 6, // [30:25] + pn_valid : 1; // [31:31] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t last_rx_enqueue_timestamp : 32; // [31:0] + uint32_t last_rx_dequeue_timestamp : 32; // [31:0] + uint32_t ptr_to_next_aging_queue_31_0 : 32; // [31:0] + uint32_t ptr_to_next_aging_queue_39_32 : 8, // [7:0] + reserved_11a : 24; // [31:8] + uint32_t ptr_to_previous_aging_queue_31_0 : 32; // [31:0] + uint32_t ptr_to_previous_aging_queue_39_32 : 8, // [7:0] + statistics_counter_index : 6, // [13:8] + reserved_13a : 18; // [31:14] + uint32_t rx_bitmap_31_0 : 32; // [31:0] + uint32_t rx_bitmap_63_32 : 32; // [31:0] + uint32_t rx_bitmap_95_64 : 32; // [31:0] + uint32_t rx_bitmap_127_96 : 32; // [31:0] + uint32_t rx_bitmap_159_128 : 32; // [31:0] + uint32_t rx_bitmap_191_160 : 32; // [31:0] + uint32_t rx_bitmap_223_192 : 32; // [31:0] + uint32_t rx_bitmap_255_224 : 32; // [31:0] + uint32_t rx_bitmap_287_256 : 32; // [31:0] + uint32_t current_mpdu_count : 7, // [6:0] + current_msdu_count : 25; // [31:7] + uint32_t last_sn_reg_index : 4, // [3:0] + timeout_count : 6, // [9:4] + forward_due_to_bar_count : 6, // [15:10] + duplicate_count : 16; // [31:16] + uint32_t frames_in_order_count : 24, // [23:0] + bar_received_count : 8; // [31:24] + uint32_t mpdu_frames_processed_count : 32; // [31:0] + uint32_t msdu_frames_processed_count : 32; // [31:0] + uint32_t total_processed_byte_count : 32; // [31:0] + uint32_t late_receive_mpdu_count : 12, // [11:0] + window_jump_2k : 4, // [15:12] + hole_count : 16; // [31:16] + uint32_t aging_drop_mpdu_count : 16, // [15:0] + aging_drop_interval : 8, // [23:16] + reserved_30 : 8; // [31:24] + uint32_t reserved_31 : 32; // [31:0] +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1b : 16, // [31:16] + receive_queue_number : 16; // [15:0] + uint32_t reserved_2b : 4, // [31:28] + ignore_ampdu_flag : 1, // [27:27] + pn_size : 2, // [26:25] + pn_handling_enable : 1, // [24:24] + pn_shall_be_uneven : 1, // [23:23] + pn_shall_be_even : 1, // [22:22] + pn_check_needed : 1, // [21:21] + ba_window_size : 10, // [20:11] + oor_mode : 1, // [10:10] + chk_2k_mode : 1, // [9:9] + rty : 1, // [8:8] + bar : 1, // [7:7] + ac : 2, // [6:5] + soft_reorder_enable : 1, // [4:4] + disable_duplicate_detection : 1, // [3:3] + associated_link_descriptor_counter : 2, // [2:1] + vld : 1; // [0:0] + uint32_t pn_valid : 1, // [31:31] + reserved_3a : 6, // [30:25] + pn_error_detected_flag : 1, // [24:24] + seq_2k_error_detected_flag : 1, // [23:23] + current_index : 10, // [22:13] + ssn : 12, // [12:1] + svld : 1; // [0:0] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t last_rx_enqueue_timestamp : 32; // [31:0] + uint32_t last_rx_dequeue_timestamp : 32; // [31:0] + uint32_t ptr_to_next_aging_queue_31_0 : 32; // [31:0] + uint32_t reserved_11a : 24, // [31:8] + ptr_to_next_aging_queue_39_32 : 8; // [7:0] + uint32_t ptr_to_previous_aging_queue_31_0 : 32; // [31:0] + uint32_t reserved_13a : 18, // [31:14] + statistics_counter_index : 6, // [13:8] + ptr_to_previous_aging_queue_39_32 : 8; // [7:0] + uint32_t rx_bitmap_31_0 : 32; // [31:0] + uint32_t rx_bitmap_63_32 : 32; // [31:0] + uint32_t rx_bitmap_95_64 : 32; // [31:0] + uint32_t rx_bitmap_127_96 : 32; // [31:0] + uint32_t rx_bitmap_159_128 : 32; // [31:0] + uint32_t rx_bitmap_191_160 : 32; // [31:0] + uint32_t rx_bitmap_223_192 : 32; // [31:0] + uint32_t rx_bitmap_255_224 : 32; // [31:0] + uint32_t rx_bitmap_287_256 : 32; // [31:0] + uint32_t current_msdu_count : 25, // [31:7] + current_mpdu_count : 7; // [6:0] + uint32_t duplicate_count : 16, // [31:16] + forward_due_to_bar_count : 6, // [15:10] + timeout_count : 6, // [9:4] + last_sn_reg_index : 4; // [3:0] + uint32_t bar_received_count : 8, // [31:24] + frames_in_order_count : 24; // [23:0] + uint32_t mpdu_frames_processed_count : 32; // [31:0] + uint32_t msdu_frames_processed_count : 32; // [31:0] + uint32_t total_processed_byte_count : 32; // [31:0] + uint32_t hole_count : 16, // [31:16] + window_jump_2k : 4, // [15:12] + late_receive_mpdu_count : 12; // [11:0] + uint32_t reserved_30 : 8, // [31:24] + aging_drop_interval : 8, // [23:16] + aging_drop_mpdu_count : 16; // [15:0] + uint32_t reserved_31 : 32; // [31:0] +#endif +}; + + +/* Description DESCRIPTOR_HEADER + + Details about which module owns this struct. + Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_descriptor" + +*/ + + +/* Description OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + The owner of this data structure: + Buffer Manager currently owns this data + structure. + Software of FW currently owns this + data structure. + Transmit Queue Manager currently owns + this data structure. + Receive DMA currently owns this data + structure. + Reorder currently owns this data structure. + + SWITCH currently owns this data structure. + + + +*/ + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + +/* Description BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Field describing what contents format is of this descriptor + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + +*/ + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + +/* Description TX_MPDU_QUEUE_NUMBER + + Consumer: TQM/Debug + Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) + + Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor + + + Indicates the MPDU queue ID to which this MPDU descriptor + belongs + Used for tracking and debugging + + +*/ + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + + +/* Description RESERVED_0A + + +*/ + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + + +/* Description RECEIVE_QUEUE_NUMBER + + Indicates the MPDU queue ID to which this MPDU link descriptor + belongs + Used for tracking and debugging + +*/ + +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + + +/* Description RESERVED_1B + + +*/ + +#define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 +#define RX_REO_QUEUE_RESERVED_1B_LSB 16 +#define RX_REO_QUEUE_RESERVED_1B_MSB 31 +#define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 + + +/* Description VLD + + Valid bit indicating a session is established and the queue + descriptor is valid(Filled by SW) + +*/ + +#define RX_REO_QUEUE_VLD_OFFSET 0x00000008 +#define RX_REO_QUEUE_VLD_LSB 0 +#define RX_REO_QUEUE_VLD_MSB 0 +#define RX_REO_QUEUE_VLD_MASK 0x00000001 + + +/* Description ASSOCIATED_LINK_DESCRIPTOR_COUNTER + + Indicates which of the 3 link descriptor counters shall + be incremented or decremented when link descriptors are + added or removed from this flow queue. + MSDU link descriptors related with MPDUs stored in the re-order + buffer shall also be included in this count. + + +*/ + +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 + + +/* Description DISABLE_DUPLICATE_DETECTION + + When set, do not perform any duplicate detection. + + +*/ + +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 + + +/* Description SOFT_REORDER_ENABLE + + When set, REO has been instructed to not perform the actual + re-ordering of frames for this queue, but just to insert + the reorder opcodes. + + Note that this implies that REO is also not going to perform + any MSDU level operations, and the entire MPDU (and thus + pointer to the MSDU link descriptor) will be pushed to + a destination ring that SW has programmed in a SW programmable + configuration register in REO + + +*/ + +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 + + +/* Description AC + + Indicates which access category the queue descriptor belongs + to(filled by SW) + +*/ + +#define RX_REO_QUEUE_AC_OFFSET 0x00000008 +#define RX_REO_QUEUE_AC_LSB 5 +#define RX_REO_QUEUE_AC_MSB 6 +#define RX_REO_QUEUE_AC_MASK 0x00000060 + + +/* Description BAR + + Indicates if BAR has been received (mostly used for debug + purpose and this is filled by REO) + +*/ + +#define RX_REO_QUEUE_BAR_OFFSET 0x00000008 +#define RX_REO_QUEUE_BAR_LSB 7 +#define RX_REO_QUEUE_BAR_MSB 7 +#define RX_REO_QUEUE_BAR_MASK 0x00000080 + + +/* Description RTY + + Retry bit is checked if this bit is set. + +*/ + +#define RX_REO_QUEUE_RTY_OFFSET 0x00000008 +#define RX_REO_QUEUE_RTY_LSB 8 +#define RX_REO_QUEUE_RTY_MSB 8 +#define RX_REO_QUEUE_RTY_MASK 0x00000100 + + +/* Description CHK_2K_MODE + + Indicates what type of operation is expected from Reo when + the received frame SN falls within the 2K window + + +*/ + +#define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 + + +/* Description OOR_MODE + + Out of Order mode: + Indicates what type of operation is expected when the received + frame falls within the OOR window. + + +*/ + +#define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_OOR_MODE_LSB 10 +#define RX_REO_QUEUE_OOR_MODE_MSB 10 +#define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 + + +/* Description BA_WINDOW_SIZE + + Indicates the negotiated (window size + 1). + It can go up to Max of 256bits. + + A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means + non-BA session, with window size of 0). The 3 values here + are the main values validated, but other values should + work as well. + + A value 1023 means 1024 bitmap, 511 means 512 bitmap. The + 2 values here are the main values validated for 1k-bitmap + support, but other values should work as well. + + A BA window size of 0 (=> one frame entry bitmap), means + that there is NO RX_REO_QUEUE_EXT descriptor following + this RX_REO_QUEUE STRUCT in memory + + A BA window size of 1 - 105 means that there is 1 RX_REO_QUEUE_EXT + descriptor directly following this RX_REO_QUEUE STRUCT + in memory. + + A BA window size of 106 - 210 means that there are 2 RX_REO_QUEUE_EXT + descriptors directly following this RX_REO_QUEUE STRUCT + in memory + + A BA window size of 211 - 256 means that there are 3 RX_REO_QUEUE_EXT + descriptors directly following this RX_REO_QUEUE STRUCT + in memory + + A BA window size of 257 - 315 means that there is one RX_REO_QUEUE_1K + descriptor followed by 3 RX_REO_QUEUE_EXT descriptors directly + following this RX_REO_QUEUE STRUCT in memory + + A BA window size of 316 - 420 means that there is one RX_REO_QUEUE_1K + descriptor followed by 4 RX_REO_QUEUE_EXT descriptors directly + following this RX_REO_QUEUE STRUCT in memory + ... + A BA window size of 946 - 1024 means that there is one RX_REO_QUEUE_1K + descriptor followed by 10 RX_REO_QUEUE_EXT descriptors + directly following this RX_REO_QUEUE STRUCT in memory + + TODO: Should the above text use '255' and '1023' instead + of '256' and '1024'? + +*/ + +#define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 + + +/* Description PN_CHECK_NEEDED + + When set, REO shall perform the PN increment check + +*/ + +#define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 + + +/* Description PN_SHALL_BE_EVEN + + Field only valid when 'pn_check_needed' is set. + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an even number + +*/ + +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 + + +/* Description PN_SHALL_BE_UNEVEN + + Field only valid when 'pn_check_needed' is set. + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an uneven number + + +*/ + +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 + + +/* Description PN_HANDLING_ENABLE + + Field only valid when 'pn_check_needed' is set. + + When set, and REO detected a PN error, HW shall set the 'pn_error_detected_flag'. + + +*/ + +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 + + +/* Description PN_SIZE + + Size of the PN field check. + Needed for wrap around handling... + + + + + + +*/ + +#define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SIZE_LSB 25 +#define RX_REO_QUEUE_PN_SIZE_MSB 26 +#define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 + + +/* Description IGNORE_AMPDU_FLAG + + When set, REO shall ignore the ampdu_flag on the entrance + descriptor for this queue. + +*/ + +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 + + +/* Description RESERVED_2B + + +*/ + +#define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 +#define RX_REO_QUEUE_RESERVED_2B_LSB 28 +#define RX_REO_QUEUE_RESERVED_2B_MSB 31 +#define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 + + +/* Description SVLD + + Sequence number in next field is valid one. It can be filled + by SW if the want to fill in the any negotiated SSN, otherwise + REO will fill the sequence number of first received packet + and set this bit to 1. + +*/ + +#define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c +#define RX_REO_QUEUE_SVLD_LSB 0 +#define RX_REO_QUEUE_SVLD_MSB 0 +#define RX_REO_QUEUE_SVLD_MASK 0x00000001 + + +/* Description SSN + + Starting Sequence number of the session, this changes whenever + window moves. (can be filled by SW then maintained by REO) + + +*/ + +#define RX_REO_QUEUE_SSN_OFFSET 0x0000000c +#define RX_REO_QUEUE_SSN_LSB 1 +#define RX_REO_QUEUE_SSN_MSB 12 +#define RX_REO_QUEUE_SSN_MASK 0x00001ffe + + +/* Description CURRENT_INDEX + + Points to last forwarded packet + +*/ + +#define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c +#define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 +#define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 +#define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 + + +/* Description SEQ_2K_ERROR_DETECTED_FLAG + + Set by REO, can only be cleared by SW + + When set, REO has detected a 2k error jump in the sequence + number and from that moment forward, all new frames are + forwarded directly to FW, without duplicate detect, reordering, + etc. + +*/ + +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 + + +/* Description PN_ERROR_DETECTED_FLAG + + Set by REO, can only be cleared by SW + + When set, REO has detected a PN error and from that moment + forward, all new frames are forwarded directly to FW, without + duplicate detect, reordering, etc. + +*/ + +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 + + +/* Description RESERVED_3A + + +*/ + +#define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c +#define RX_REO_QUEUE_RESERVED_3A_LSB 25 +#define RX_REO_QUEUE_RESERVED_3A_MSB 30 +#define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 + + +/* Description PN_VALID + + PN number in next fields are valid. It can be filled by + SW if it wants to fill in the any negotiated SSN, otherwise + REO will fill the pn based on the first received packet + and set this bit to 1. + +*/ + +#define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_VALID_LSB 31 +#define RX_REO_QUEUE_PN_VALID_MSB 31 +#define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 + + +/* Description PN_31_0 + + Bits [31:0] of the PN number extracted from the IV field + + +*/ + +#define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_PN_31_0_LSB 0 +#define RX_REO_QUEUE_PN_31_0_MSB 31 +#define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff + + +/* Description PN_63_32 + + Bits [63:32] of the PN number. + +*/ + +#define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_PN_63_32_LSB 0 +#define RX_REO_QUEUE_PN_63_32_MSB 31 +#define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff + + +/* Description PN_95_64 + + Bits [95:64] of the PN number. + +*/ + +#define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 +#define RX_REO_QUEUE_PN_95_64_LSB 0 +#define RX_REO_QUEUE_PN_95_64_MSB 31 +#define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff + + +/* Description PN_127_96 + + Bits [127:96] of the PN number. + +*/ + +#define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c +#define RX_REO_QUEUE_PN_127_96_LSB 0 +#define RX_REO_QUEUE_PN_127_96_MSB 31 +#define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff + + +/* Description LAST_RX_ENQUEUE_TIMESTAMP + + This timestamp is updated when an MPDU is received and accesses + this Queue Descriptor. It does not include the access due + to Command TLVs or Aging (which will be updated in Last_rx_dequeue_timestamp). + + +*/ + +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + + +/* Description LAST_RX_DEQUEUE_TIMESTAMP + + This timestamp is used for Aging. When an MPDU or multiple + MPDUs are forwarded, either due to window movement, bar, + aging or command flush, this timestamp is updated. Also + when the bitmap is all zero and the first time an MPDU is + queued (opcode=QCUR), this timestamp is updated for aging. + + +*/ + +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + + +/* Description PTR_TO_NEXT_AGING_QUEUE_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE descriptor + in the 'receive timestamp' ordered list. + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + Value 0x0 indicates the 'NULL' pointer which implies that + this is the last entry in the list. + +*/ + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff + + +/* Description PTR_TO_NEXT_AGING_QUEUE_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE descriptor + in the 'receive timestamp' ordered list. + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + Value 0x0 indicates the 'NULL' pointer which implies that + this is the last entry in the list. + +*/ + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff + + +/* Description RESERVED_11A + + +*/ + +#define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c +#define RX_REO_QUEUE_RESERVED_11A_LSB 8 +#define RX_REO_QUEUE_RESERVED_11A_MSB 31 +#define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 + + +/* Description PTR_TO_PREVIOUS_AGING_QUEUE_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE descriptor + in the 'receive timestamp' ordered list. + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + Value 0x0 indicates the 'NULL' pointer which implies that + this is the first entry in the list. + +*/ + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff + + +/* Description PTR_TO_PREVIOUS_AGING_QUEUE_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE descriptor + in the 'receive timestamp' ordered list. + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + Value 0x0 indicates the 'NULL' pointer which implies that + this is the first entry in the list. + +*/ + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff + + +/* Description STATISTICS_COUNTER_INDEX + + Usually all the queues pertaining to one virtual device + use one statistics register set, and each virtual device + maps to a different set in case of not too many virtual + devices. + +*/ + +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00 + + +/* Description RESERVED_13A + + +*/ + +#define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 +#define RX_REO_QUEUE_RESERVED_13A_LSB 14 +#define RX_REO_QUEUE_RESERVED_13A_MSB 31 +#define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000 + + +/* Description RX_BITMAP_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + The bitmap is Fully managed by HW. + SW shall init this to 0, and then never ever change it + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff + + +/* Description RX_BITMAP_63_32 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff + + +/* Description RX_BITMAP_95_64 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 +#define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff + + +/* Description RX_BITMAP_127_96 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 +#define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff + + +/* Description RX_BITMAP_159_128 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 +#define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff + + +/* Description RX_BITMAP_191_160 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c +#define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff + + +/* Description RX_BITMAP_223_192 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 +#define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff + + +/* Description RX_BITMAP_255_224 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 +#define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff + + +/* Description RX_BITMAP_287_256 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 +#define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff + + +/* Description CURRENT_MPDU_COUNT + + The number of MPDUs in the queue. + + +*/ + +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f + + +/* Description CURRENT_MSDU_COUNT + + The number of MSDUs in the queue. + +*/ + +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 + + +/* Description LAST_SN_REG_INDEX + + REO has registers to save the last SN seen in up to 9 REO + queues, to support "leaky APs." + + This field gives the register number to use for saving the + last SN of this REO queue. + +*/ + +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f + + +/* Description TIMEOUT_COUNT + + The number of times that REO started forwarding frames even + though there is a hole in the bitmap. Forwarding reason + is Timeout + + The counter saturates and freezes at 0x3F + + +*/ + +#define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 + + +/* Description FORWARD_DUE_TO_BAR_COUNT + + The number of times that REO started forwarding frames even + though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + The counter saturates and freezes at 0x3F + + +*/ + +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + + +/* Description DUPLICATE_COUNT + + The number of duplicate frames that have been detected + +*/ + +#define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 + + +/* Description FRAMES_IN_ORDER_COUNT + + The number of frames that have been received in order (without + a hole that prevented them from being forwarded immediately) + + + This corresponds to the Reorder opcodes: + 'FWDCUR' and 'FWD BUF' + + +*/ + +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + + +/* Description BAR_RECEIVED_COUNT + + The number of times a BAR frame is received. + + This corresponds to the Reorder opcodes with 'DROP' + + The counter saturates and freezes at 0xFF + +*/ + +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 + + +/* Description MPDU_FRAMES_PROCESSED_COUNT + + The total number of MPDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + Note that this count includes duplicates, frames that later + had errors, etc. + + Note that field 'Duplicate_count' indicates how many of + these MPDUs were duplicates. + + +*/ + +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + + +/* Description MSDU_FRAMES_PROCESSED_COUNT + + The total number of MSDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + Note that this count includes duplicates, frames that later + had errors, etc. + + +*/ + +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + + +/* Description TOTAL_PROCESSED_BYTE_COUNT + + An approximation of the number of bytes processed for this + queue. + 'Processing' here means that REO has received them out of + the entrance ring, and retrieved the corresponding RX_REO_QUEUE + Descriptor. + + Note that this count includes duplicates, frames that later + had errors, etc. + + In 64 byte units + +*/ + +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + + +/* Description LATE_RECEIVE_MPDU_COUNT + + The number of MPDUs received after the window had already + moved on. The 'late' sequence window is defined as (Window + SSN - 256) - (Window SSN - 1) + + This corresponds with Out of order detection in duplicate + detect FSM + + The counter saturates and freezes at 0xFFF + + +*/ + +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + + +/* Description WINDOW_JUMP_2K + + The number of times the window moved more then 2K + + The counter saturates and freezes at 0xF + + (Note: field name can not start with number: previous 2k_window_jump) + + + +*/ + +#define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 + + +/* Description HOLE_COUNT + + The number of times a hole was created in the receive bitmap. + + + This corresponds to the Reorder opcodes with 'QCUR' + + +*/ + +#define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_HOLE_COUNT_LSB 16 +#define RX_REO_QUEUE_HOLE_COUNT_MSB 31 +#define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 + + +/* Description AGING_DROP_MPDU_COUNT + + The number of holes in the bitmap that moved due to aging + counter expiry + +*/ + +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff + + +/* Description AGING_DROP_INTERVAL + + The number of times holes got removed from the bitmap due + to aging counter expiry + +*/ + +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000 + + +/* Description RESERVED_30 + + +*/ + +#define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_RESERVED_30_LSB 24 +#define RX_REO_QUEUE_RESERVED_30_MSB 31 +#define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000 + + +/* Description RESERVED_31 + + +*/ + +#define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_RESERVED_31_MSB 31 +#define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff + + + +#endif // RX_REO_QUEUE diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_reo_queue_1k.h b/drivers/staging/fw-api/hw/qcn6432/rx_reo_queue_1k.h new file mode 100644 index 0000000000000000000000000000000000000000..a197febb4aa7977d7b07b585fac5e2d5d399139f --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_reo_queue_1k.h @@ -0,0 +1,567 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_REO_QUEUE_1K_H_ +#define _RX_REO_QUEUE_1K_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32 + + +struct rx_reo_queue_1k { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t rx_bitmap_319_288 : 32; // [31:0] + uint32_t rx_bitmap_351_320 : 32; // [31:0] + uint32_t rx_bitmap_383_352 : 32; // [31:0] + uint32_t rx_bitmap_415_384 : 32; // [31:0] + uint32_t rx_bitmap_447_416 : 32; // [31:0] + uint32_t rx_bitmap_479_448 : 32; // [31:0] + uint32_t rx_bitmap_511_480 : 32; // [31:0] + uint32_t rx_bitmap_543_512 : 32; // [31:0] + uint32_t rx_bitmap_575_544 : 32; // [31:0] + uint32_t rx_bitmap_607_576 : 32; // [31:0] + uint32_t rx_bitmap_639_608 : 32; // [31:0] + uint32_t rx_bitmap_671_640 : 32; // [31:0] + uint32_t rx_bitmap_703_672 : 32; // [31:0] + uint32_t rx_bitmap_735_704 : 32; // [31:0] + uint32_t rx_bitmap_767_736 : 32; // [31:0] + uint32_t rx_bitmap_799_768 : 32; // [31:0] + uint32_t rx_bitmap_831_800 : 32; // [31:0] + uint32_t rx_bitmap_863_832 : 32; // [31:0] + uint32_t rx_bitmap_895_864 : 32; // [31:0] + uint32_t rx_bitmap_927_896 : 32; // [31:0] + uint32_t rx_bitmap_959_928 : 32; // [31:0] + uint32_t rx_bitmap_991_960 : 32; // [31:0] + uint32_t rx_bitmap_1023_992 : 32; // [31:0] + uint32_t reserved_24 : 32; // [31:0] + uint32_t reserved_25 : 32; // [31:0] + uint32_t reserved_26 : 32; // [31:0] + uint32_t reserved_27 : 32; // [31:0] + uint32_t reserved_28 : 32; // [31:0] + uint32_t reserved_29 : 32; // [31:0] + uint32_t reserved_30 : 32; // [31:0] + uint32_t reserved_31 : 32; // [31:0] +#else + struct uniform_descriptor_header descriptor_header; + uint32_t rx_bitmap_319_288 : 32; // [31:0] + uint32_t rx_bitmap_351_320 : 32; // [31:0] + uint32_t rx_bitmap_383_352 : 32; // [31:0] + uint32_t rx_bitmap_415_384 : 32; // [31:0] + uint32_t rx_bitmap_447_416 : 32; // [31:0] + uint32_t rx_bitmap_479_448 : 32; // [31:0] + uint32_t rx_bitmap_511_480 : 32; // [31:0] + uint32_t rx_bitmap_543_512 : 32; // [31:0] + uint32_t rx_bitmap_575_544 : 32; // [31:0] + uint32_t rx_bitmap_607_576 : 32; // [31:0] + uint32_t rx_bitmap_639_608 : 32; // [31:0] + uint32_t rx_bitmap_671_640 : 32; // [31:0] + uint32_t rx_bitmap_703_672 : 32; // [31:0] + uint32_t rx_bitmap_735_704 : 32; // [31:0] + uint32_t rx_bitmap_767_736 : 32; // [31:0] + uint32_t rx_bitmap_799_768 : 32; // [31:0] + uint32_t rx_bitmap_831_800 : 32; // [31:0] + uint32_t rx_bitmap_863_832 : 32; // [31:0] + uint32_t rx_bitmap_895_864 : 32; // [31:0] + uint32_t rx_bitmap_927_896 : 32; // [31:0] + uint32_t rx_bitmap_959_928 : 32; // [31:0] + uint32_t rx_bitmap_991_960 : 32; // [31:0] + uint32_t rx_bitmap_1023_992 : 32; // [31:0] + uint32_t reserved_24 : 32; // [31:0] + uint32_t reserved_25 : 32; // [31:0] + uint32_t reserved_26 : 32; // [31:0] + uint32_t reserved_27 : 32; // [31:0] + uint32_t reserved_28 : 32; // [31:0] + uint32_t reserved_29 : 32; // [31:0] + uint32_t reserved_30 : 32; // [31:0] + uint32_t reserved_31 : 32; // [31:0] +#endif +}; + + +/* Description DESCRIPTOR_HEADER + + Details about which module owns this struct. + Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_1k_descriptor" + +*/ + + +/* Description OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + The owner of this data structure: + Buffer Manager currently owns this data + structure. + Software of FW currently owns this + data structure. + Transmit Queue Manager currently owns + this data structure. + Receive DMA currently owns this data + structure. + Reorder currently owns this data structure. + + SWITCH currently owns this data structure. + + + +*/ + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + +/* Description BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Field describing what contents format is of this descriptor + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + +*/ + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + +/* Description TX_MPDU_QUEUE_NUMBER + + Consumer: TQM/Debug + Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) + + Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor + + + Indicates the MPDU queue ID to which this MPDU descriptor + belongs + Used for tracking and debugging + + +*/ + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + + +/* Description RESERVED_0A + + +*/ + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + + +/* Description RX_BITMAP_319_288 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + The bitmap is Fully managed by HW. + SW shall init this to 0, and then never ever change it + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff + + +/* Description RX_BITMAP_351_320 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff + + +/* Description RX_BITMAP_383_352 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff + + +/* Description RX_BITMAP_415_384 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff + + +/* Description RX_BITMAP_447_416 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff + + +/* Description RX_BITMAP_479_448 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff + + +/* Description RX_BITMAP_511_480 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff + + +/* Description RX_BITMAP_543_512 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff + + +/* Description RX_BITMAP_575_544 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff + + +/* Description RX_BITMAP_607_576 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff + + +/* Description RX_BITMAP_639_608 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff + + +/* Description RX_BITMAP_671_640 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff + + +/* Description RX_BITMAP_703_672 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff + + +/* Description RX_BITMAP_735_704 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff + + +/* Description RX_BITMAP_767_736 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff + + +/* Description RX_BITMAP_799_768 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff + + +/* Description RX_BITMAP_831_800 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff + + +/* Description RX_BITMAP_863_832 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff + + +/* Description RX_BITMAP_895_864 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff + + +/* Description RX_BITMAP_927_896 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff + + +/* Description RX_BITMAP_959_928 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff + + +/* Description RX_BITMAP_991_960 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff + + +/* Description RX_BITMAP_1023_992 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff + + +/* Description RESERVED_24 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060 +#define RX_REO_QUEUE_1K_RESERVED_24_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_24_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff + + +/* Description RESERVED_25 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064 +#define RX_REO_QUEUE_1K_RESERVED_25_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_25_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff + + +/* Description RESERVED_26 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068 +#define RX_REO_QUEUE_1K_RESERVED_26_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_26_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff + + +/* Description RESERVED_27 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c +#define RX_REO_QUEUE_1K_RESERVED_27_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_27_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff + + +/* Description RESERVED_28 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070 +#define RX_REO_QUEUE_1K_RESERVED_28_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_28_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff + + +/* Description RESERVED_29 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074 +#define RX_REO_QUEUE_1K_RESERVED_29_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_29_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff + + +/* Description RESERVED_30 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_1K_RESERVED_30_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_30_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff + + +/* Description RESERVED_31 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_1K_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_31_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff + + + +#endif // RX_REO_QUEUE_1K diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_reo_queue_ext.h b/drivers/staging/fw-api/hw/qcn6432/rx_reo_queue_ext.h new file mode 100644 index 0000000000000000000000000000000000000000..a7d48395438b1752b16b751374809b3848305842 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_reo_queue_ext.h @@ -0,0 +1,2447 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_REO_QUEUE_EXT_H_ +#define _RX_REO_QUEUE_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_link_ptr.h" +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 + + +struct rx_reo_queue_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; // [31:0] + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; // [31:0] + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#endif +}; + + +/* Description DESCRIPTOR_HEADER + + Details about which module owns this struct. + Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_ext_descriptor" + +*/ + + +/* Description OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + The owner of this data structure: + Buffer Manager currently owns this data + structure. + Software of FW currently owns this + data structure. + Transmit Queue Manager currently owns + this data structure. + Receive DMA currently owns this data + structure. + Reorder currently owns this data structure. + + SWITCH currently owns this data structure. + + + +*/ + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + +/* Description BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Field describing what contents format is of this descriptor + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + +*/ + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + +/* Description TX_MPDU_QUEUE_NUMBER + + Consumer: TQM/Debug + Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) + + Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor + + + Indicates the MPDU queue ID to which this MPDU descriptor + belongs + Used for tracking and debugging + + +*/ + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + + +/* Description RESERVED_0A + + +*/ + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + + +/* Description RESERVED_1A + + +*/ + +#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004 +#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff + + +/* Description MPDU_LINK_POINTER_0 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_1 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_2 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_3 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_4 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_5 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_6 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_7 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_8 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_9 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_10 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_11 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_12 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_13 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_14 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif // RX_REO_QUEUE_EXT diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_reo_queue_reference.h b/drivers/staging/fw-api/hw/qcn6432/rx_reo_queue_reference.h new file mode 100644 index 0000000000000000000000000000000000000000..15aa8ce4f567491dcfc3bacbb62a01749fc744a8 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_reo_queue_reference.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_REO_QUEUE_REFERENCE_H_ +#define _RX_REO_QUEUE_REFERENCE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_REO_QUEUE_REFERENCE 2 + + +struct rx_reo_queue_reference { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] + reserved_1 : 8, // [15:8] + receive_queue_number : 16; // [31:16] +#else + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t receive_queue_number : 16, // [31:16] + reserved_1 : 8, // [15:8] + rx_reo_queue_desc_addr_39_32 : 8; // [7:0] +#endif +}; + + +/* Description RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: RXDMA + Producer: RXOLE + + Address (lower 32 bits) of the REO queue descriptor. + +*/ + +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000000 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + + +/* Description RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: RXDMA + Producer: RXOLE + + Address (upper 8 bits) of the REO queue descriptor. + +*/ + +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000004 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + + +/* Description RESERVED_1 + + +*/ + +#define RX_REO_QUEUE_REFERENCE_RESERVED_1_OFFSET 0x00000004 +#define RX_REO_QUEUE_REFERENCE_RESERVED_1_LSB 8 +#define RX_REO_QUEUE_REFERENCE_RESERVED_1_MSB 15 +#define RX_REO_QUEUE_REFERENCE_RESERVED_1_MASK 0x0000ff00 + + +/* Description RECEIVE_QUEUE_NUMBER + + Indicates the MPDU queue ID to which this MPDU link descriptor + belongs + Used for tracking and debugging + +*/ + +#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_LSB 16 +#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MSB 31 +#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 + + + +#endif // RX_REO_QUEUE_REFERENCE diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_response_required_info.h b/drivers/staging/fw-api/hw/qcn6432/rx_response_required_info.h new file mode 100644 index 0000000000000000000000000000000000000000..48f42c702f7cb43f3f329791b3cb7b417ba09973 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_response_required_info.h @@ -0,0 +1,2100 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ +#define _RX_RESPONSE_REQUIRED_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 + +#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 + + +struct rx_response_required_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, // [15:0] + su_or_uplink_mu_reception : 1, // [16:16] + trigger_frame_received : 1, // [17:17] + ftm_tm : 2, // [19:18] + tb_ranging_response_required : 2, // [21:20] + mac_security : 1, // [22:22] + filter_pass_monitor_ovrd : 1, // [23:23] + ast_search_incomplete : 1, // [24:24] + r2r_end_status_to_follow : 1, // [25:25] + reserved_0a : 2, // [27:26] + three_or_more_type_subtypes : 1, // [28:28] + wait_sifs_config_valid : 1, // [29:29] + wait_sifs : 2; // [31:30] + uint32_t general_frame_control : 16, // [15:0] + second_frame_control : 16; // [31:16] + uint32_t duration : 16, // [15:0] + pkt_type : 4, // [19:16] + dot11ax_su_extended : 1, // [20:20] + rate_mcs : 4, // [24:21] + sgi : 2, // [26:25] + stbc : 1, // [27:27] + ldpc : 1, // [28:28] + ampdu : 1, // [29:29] + vht_ack : 1, // [30:30] + rts_ta_grp_bit : 1; // [31:31] + uint32_t ctrl_frame_soliciting_resp : 1, // [0:0] + ast_fail_for_dot11ax_su_ext : 1, // [1:1] + service_dynamic : 1, // [2:2] + m_pkt : 1, // [3:3] + sta_partial_aid : 12, // [15:4] + group_id : 6, // [21:16] + ctrl_resp_pwr_mgmt : 1, // [22:22] + response_indication : 2, // [24:23] + ndp_indication : 1, // [25:25] + ndp_frame_type : 3, // [28:26] + second_frame_control_valid : 1, // [29:29] + reserved_3a : 2; // [31:30] + uint32_t ack_id : 16, // [15:0] + ack_id_ext : 10, // [25:16] + agc_cbw : 3, // [28:26] + service_cbw : 3; // [31:29] + uint32_t response_sta_count : 7, // [6:0] + reserved : 4, // [10:7] + ht_vht_sig_cbw : 3, // [13:11] + cts_cbw : 3, // [16:14] + response_ack_count : 7, // [23:17] + response_assoc_ack_count : 7, // [30:24] + txop_duration_all_ones : 1; // [31:31] + uint32_t response_ba32_count : 7, // [6:0] + response_ba64_count : 7, // [13:7] + response_ba128_count : 7, // [20:14] + response_ba256_count : 7, // [27:21] + multi_tid : 1, // [28:28] + sw_response_tlv_from_crypto : 1, // [29:29] + dot11ax_dl_ul_flag : 1, // [30:30] + reserved_6a : 1; // [31:31] + uint32_t sw_response_frame_length : 16, // [15:0] + response_ba512_count : 7, // [22:16] + response_ba1024_count : 7, // [29:23] + reserved_7a : 2; // [31:30] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr1_47_32 : 16, // [15:0] + addr2_15_0 : 16; // [31:16] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t dot11ax_received_format_indication : 1, // [0:0] + dot11ax_received_dl_ul_flag : 1, // [1:1] + dot11ax_received_bss_color_id : 6, // [7:2] + dot11ax_received_spatial_reuse : 4, // [11:8] + dot11ax_received_cp_size : 2, // [13:12] + dot11ax_received_ltf_size : 2, // [15:14] + dot11ax_received_coding : 1, // [16:16] + dot11ax_received_dcm : 1, // [17:17] + dot11ax_received_doppler_indication : 1, // [18:18] + dot11ax_received_ext_ru_size : 4, // [22:19] + ftm_fields_valid : 1, // [23:23] + ftm_pe_nss : 3, // [26:24] + ftm_pe_ltf_size : 2, // [28:27] + ftm_pe_content : 1, // [29:29] + ftm_chain_csd_en : 1, // [30:30] + ftm_pe_chain_csd_en : 1; // [31:31] + uint32_t dot11ax_response_rate_source : 8, // [7:0] + dot11ax_ext_response_rate_source : 8, // [15:8] + sw_peer_id : 16; // [31:16] + uint32_t dot11be_puncture_bitmap : 16, // [15:0] + dot11be_response : 1, // [16:16] + punctured_response : 1, // [17:17] + eht_duplicate_mode : 2, // [19:18] + force_extra_symbol : 1, // [20:20] + reserved_13a : 5, // [25:21] + u_sig_puncture_pattern_encoding : 6; // [31:26] + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t he_a_control_response_time : 12, // [27:16] + reserved_after_struct16 : 4; // [31:28] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t wait_sifs : 2, // [31:30] + wait_sifs_config_valid : 1, // [29:29] + three_or_more_type_subtypes : 1, // [28:28] + reserved_0a : 2, // [27:26] + r2r_end_status_to_follow : 1, // [25:25] + ast_search_incomplete : 1, // [24:24] + filter_pass_monitor_ovrd : 1, // [23:23] + mac_security : 1, // [22:22] + tb_ranging_response_required : 2, // [21:20] + ftm_tm : 2, // [19:18] + trigger_frame_received : 1, // [17:17] + su_or_uplink_mu_reception : 1, // [16:16] + phy_ppdu_id : 16; // [15:0] + uint32_t second_frame_control : 16, // [31:16] + general_frame_control : 16; // [15:0] + uint32_t rts_ta_grp_bit : 1, // [31:31] + vht_ack : 1, // [30:30] + ampdu : 1, // [29:29] + ldpc : 1, // [28:28] + stbc : 1, // [27:27] + sgi : 2, // [26:25] + rate_mcs : 4, // [24:21] + dot11ax_su_extended : 1, // [20:20] + pkt_type : 4, // [19:16] + duration : 16; // [15:0] + uint32_t reserved_3a : 2, // [31:30] + second_frame_control_valid : 1, // [29:29] + ndp_frame_type : 3, // [28:26] + ndp_indication : 1, // [25:25] + response_indication : 2, // [24:23] + ctrl_resp_pwr_mgmt : 1, // [22:22] + group_id : 6, // [21:16] + sta_partial_aid : 12, // [15:4] + m_pkt : 1, // [3:3] + service_dynamic : 1, // [2:2] + ast_fail_for_dot11ax_su_ext : 1, // [1:1] + ctrl_frame_soliciting_resp : 1; // [0:0] + uint32_t service_cbw : 3, // [31:29] + agc_cbw : 3, // [28:26] + ack_id_ext : 10, // [25:16] + ack_id : 16; // [15:0] + uint32_t txop_duration_all_ones : 1, // [31:31] + response_assoc_ack_count : 7, // [30:24] + response_ack_count : 7, // [23:17] + cts_cbw : 3, // [16:14] + ht_vht_sig_cbw : 3, // [13:11] + reserved : 4, // [10:7] + response_sta_count : 7; // [6:0] + uint32_t reserved_6a : 1, // [31:31] + dot11ax_dl_ul_flag : 1, // [30:30] + sw_response_tlv_from_crypto : 1, // [29:29] + multi_tid : 1, // [28:28] + response_ba256_count : 7, // [27:21] + response_ba128_count : 7, // [20:14] + response_ba64_count : 7, // [13:7] + response_ba32_count : 7; // [6:0] + uint32_t reserved_7a : 2, // [31:30] + response_ba1024_count : 7, // [29:23] + response_ba512_count : 7, // [22:16] + sw_response_frame_length : 16; // [15:0] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr2_15_0 : 16, // [31:16] + addr1_47_32 : 16; // [15:0] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t ftm_pe_chain_csd_en : 1, // [31:31] + ftm_chain_csd_en : 1, // [30:30] + ftm_pe_content : 1, // [29:29] + ftm_pe_ltf_size : 2, // [28:27] + ftm_pe_nss : 3, // [26:24] + ftm_fields_valid : 1, // [23:23] + dot11ax_received_ext_ru_size : 4, // [22:19] + dot11ax_received_doppler_indication : 1, // [18:18] + dot11ax_received_dcm : 1, // [17:17] + dot11ax_received_coding : 1, // [16:16] + dot11ax_received_ltf_size : 2, // [15:14] + dot11ax_received_cp_size : 2, // [13:12] + dot11ax_received_spatial_reuse : 4, // [11:8] + dot11ax_received_bss_color_id : 6, // [7:2] + dot11ax_received_dl_ul_flag : 1, // [1:1] + dot11ax_received_format_indication : 1; // [0:0] + uint32_t sw_peer_id : 16, // [31:16] + dot11ax_ext_response_rate_source : 8, // [15:8] + dot11ax_response_rate_source : 8; // [7:0] + uint32_t u_sig_puncture_pattern_encoding : 6, // [31:26] + reserved_13a : 5, // [25:21] + force_extra_symbol : 1, // [20:20] + eht_duplicate_mode : 2, // [19:18] + punctured_response : 1, // [17:17] + dot11be_response : 1, // [16:16] + dot11be_puncture_bitmap : 16; // [15:0] + uint32_t reserved_after_struct16 : 4, // [31:28] + he_a_control_response_time : 12; // [27:16] + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff + + +/* Description SU_OR_UPLINK_MU_RECEPTION + + This TLV is the result of an SU + reception. Note that this can be regular SU reception or + an SU reception as part of a downlink MU - MIMO/OFDMA transmission. + + + This TLV is the result of an MU_OFDMA + uplink reception or MU_MIMO uplink reception + + NOTE:When a STA receives a downlink MU-MIMO or DL MU_OFDMA, + this field shall still be set to Reception_is_SU. From the + STA perspective, it is only receiving from one other device. + + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 + + +/* Description TRIGGER_FRAME_RECEIVED + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + When set, this TLV has been sent because a trigger frame + has been received. + + Note that in case there were other frames received as well + that required an immediate response, like data or management + frames, this will still be indicated here in this TLV with + the fields "Response_..._count". + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 + + +/* Description FTM_TM + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field Indicates if the response is related to receiving + a TM or FTM frame + + 0: no TM and no FTM frame => there is NO measurement done + + 1: FTM frame + 2: TM frame + 3: reserved +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_TM_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_FTM_TM_LSB 18 +#define RX_RESPONSE_REQUIRED_INFO_FTM_TM_MSB 19 +#define RX_RESPONSE_REQUIRED_INFO_FTM_TM_MASK 0x00000000000c0000 + + +/* Description TB_RANGING_RESPONSE_REQUIRED + + Field only valid in case of TB Ranging + + TXPCU to generate CTS-to-self + in TB response + TXPCU to generate LMR in + TB response + DO NOT USE. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000300000 + + +/* Description MAC_SECURITY + + Field only valid if TB_Ranging_response_required = LMR_Resp_to_TF_report + + + Indicates whether MAC security is enabled for LMR + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 + + +/* Description FILTER_PASS_MONITOR_OVRD + + Consumer: TXMON/SW + Producer: RXPCU + + This indicates that the Rx MPDU passed the 'normal' frame + filter programming of RXPCU and additionally the MAC address + search matched an 'ADDR_SEARCH_ENTRY' of a 'Monitor_override_sta.' + + + When enabled in TXMON, it will discard the upstream response + TLVs for cases not matching the 'Filter_pass_Monitor_ovrd' + criterion. + + If RXPCU is generating this TLV before the address search + is complete, it shall fill this bit based on a register + configuration 'FILTER_PASS_OVRD_AST_NOT_DONE.' + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 + + +/* Description AST_SEARCH_INCOMPLETE + + Consumer: SW + Producer: RXPCU + + If RXPCU is generating this TLV before the address search + is complete, it shall set this bit. This is to indicate + to SW (via TXMON) that the Filter_pass_Monitor_ovrd bit + is unreliable and SW may have to add their own filtering + logic. + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 + + +/* Description R2R_END_STATUS_TO_FOLLOW + + Consumer: TXMON + Producer: TXPCU + + When set, TXPCU will generate an R2R frame (typically M-BA), + and the 'R2R_STATUS_END' TLV. + + TXMON uses this to identify the continuation of a Tx sequence + (typically including Trigger frames) with R2R Tx. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MASK 0x000000000c000000 + + +/* Description THREE_OR_MORE_TYPE_SUBTYPES + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + When set, there are 3 or more different frame type/subtypes + received that all required a response. + Note that the HW will only report the very first two that + have been seen +*/ + +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 + + +/* Description WAIT_SIFS_CONFIG_VALID + + When set, TXPCU shall follow the wait_sifs configuration. + + + Field added to be backwards compatible, and transition to + the new signalling. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 + + +/* Description WAIT_SIFS + + Indicates to the TXPCU how precise the SIFS the response + timing shall be... + + The configuration for this is coming from SW programmable + register in RXPCU + + Transmission shall start with the + normal delay in PHY after receiving this notification + Transmission shall be made + at the SIFS boundary. If shall never start before SIFS boundary, + but if it a little later, it is not ideal and should be + flagged, but transmission shall not be aborted. + Transmission shall be made + at exactly SIFS boundary. If this notification is received + by the PHY after SIFS boundary already passed, the PHY + shall abort the transmission + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 + + +/* Description GENERAL_FRAME_CONTROL + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + In case only a single frame is receive, this field will + always contain the frame control field of the received frame. + + + In case multiple frames are received that require a response, + and one of those frames is not a data frame, this field + will always contain the frame control field of that received + frame. + + In case multiple frames are received that require a response, + but all have them have the same type/subtype, this field + will contain the very first one of them. + + Note: In case of a BAR frame reception, the 'response_ack_...' + fields will indicate for how many TIDs a BA is needed, as + well as their individual sizes. + + Used by TXPCU to determine the type of response that is + needed + + TODO: Look at table below for all the possible combination + of frames types reported here and in the next field: Second_frame_control + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 + + +/* Description SECOND_FRAME_CONTROL + + Field only valid when Second_frame_control_valid ==1 + + In case multiple frames of different frame type/subtype + are received that require a response, this field will always + contain the frame control field remaining after the 'frame_control + ' field has been filled in. + + NOTE: in case more then 2 different frame type/subtypes + are received (which only happens if the transmitter did + something wrong), only the first two frame types are reported + in this and the General_frame_control field. All the other + ones are ignored, but bit 'three_or_more_type_subtypes' + shall be set. + + Note: In case of a BAR frame reception, the 'response_ack_...' + fields will indicate for how many TIDs a BA is needed, as + well as their individual sizes. + + Used by TXPCU to determine the type of response that is + needed +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 + + +/* Description DURATION + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + duration field of the received frame +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff + + +/* Description PKT_TYPE + + Packet type: + + Note that for MU UL reception, this field can only be set + to dot11ax. + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 + + +/* Description DOT11AX_SU_EXTENDED + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be + + When set, the 11ax or 11be reception was an extended range + SU +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 + + +/* Description RATE_MCS + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000001e00000 + + +/* Description SGI + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Field only valid when pkt type is HT, VHT or HE. + + Specify the right GI for HE-Ranging NDPs (11az). + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x0000000006000000 + + +/* Description STBC + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Indicate STBC + + In 11ah mode of Operation, this bit indicates the STBC bit + setting in the SIG Preamble. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000008000000 + + +/* Description LDPC + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Indicate LDPC + + In 11ah mode of Operation, this bit indicates the LDPC bit + setting in the SIG Preamble. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000010000000 + + +/* Description AMPDU + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Field indicates if the received frame was in ampdu format + or not. If set, it implies the reception was 11n, aggregation, + 11ac or 11ax. + + Within TXPCU it is used to determine if the response will + have to be BA format or not. Note that there are some exceptions + where received frame was A-MPDU format, but the response + will still be just an ACK frame. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000020000000 + + +/* Description VHT_ACK + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + set when ACK is required to be generated +*/ + +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x0000000040000000 + + +/* Description RTS_TA_GRP_BIT + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + frame is rts and TA G/I bit is set +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 + + +/* Description CTRL_FRAME_SOLICITING_RESP + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + frame is rts, bar or ps_poll and TA G/I bit is set +*/ + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 + + +/* Description AST_FAIL_FOR_DOT11AX_SU_EXT + + Field only valid in case of + dot11ax_su_extended = 1 + + When set, the just finished reception had address search + failure (e.g. unassociated STA). + This field can be used to determine special response rates + for those types of STAs. + This field shall be analyzed in combination with pkt_type + and dot11ax_su_extended settings. + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 + + +/* Description SERVICE_DYNAMIC + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Dynamic field extracted from Service field + + Reserved for 11ah. Should be populated to zero by RxPCU +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 + + +/* Description M_PKT + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Indicates that RXPCU has detected a 802.11v M packet. The + TXPCU should generate a TX_FREEZE_CAPTURE_CHANNEL message + to the PHY so that the PHY will hold the current channel + capture so FW can read the channel capture memory over + APB. + Reserved for 11ah. Should be populated to zero by RxPCU +*/ + +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 + + +/* Description STA_PARTIAL_AID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Specifies the partial AID of response frames transmitted + at VHT rates. + + In 11ah mode of operation, this field is used to populate + the RA/partial BSSID filed in the NDP CTS response frame. + Please refer to the 802.11 spec for details on the NDP CTS + frame format. + + Reserved for 11ah. + Should be populated to zero by RxPCU +*/ + +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 + + +/* Description GROUP_ID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Reserved for 11ah. + Should be populated to zero by RxPCU +*/ + +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 + + +/* Description CTRL_RESP_PWR_MGMT + + Field valid in case of both SU_or_uplink_MU_reception = + Reception_is_SU + AND + SU_or_uplink_MU_reception = Reception_is_MU + + RX PCU passes this bit (coming from the peer entry) setting + on to TX PCU, where the setting of this bit is inserted + in the pwr_mgt bit in the control field of the SIFS response + control frames: ACK, CTS, BA + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 + + +/* Description RESPONSE_INDICATION + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + + + + + + + This field indicates the Response Indication of the received + PPDU. RxPCU populates this field using the Response Indication + bits extracted from the SIG in the received PPDU. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 + + +/* Description NDP_INDICATION + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is valid in 11ah mode of opearation only. In + non-11ah mode, this bit is reserved and RxPCU populates + this bit to Zero. + + NDP Indication bit. + + This field is set if the received SIG has the NDP Indication + bit set. + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 + + +/* Description NDP_FRAME_TYPE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Include the ndp_frame_type encoding. + + This field is valid in 11ah mode of opearation only. In + non-11ah mode, this bit is reserved and RxPCU populates + this bit to Zero. + + The ndp_frame_type filed form the SIG is extracted and is + populated in this field by RxPCU. TxPCU can decode the + NDP frame type. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 + + +/* Description SECOND_FRAME_CONTROL_VALID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + When set, the second frame control field is valid. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 + + +/* Description RESERVED_3A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0xc000000000000000 + + +/* Description ACK_ID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Indicates the ACD_ID to be used in NDP response frames (NDP + ACK and NDP Modified ACK). + + For NDP ACK + ACK_ID (16bits)= {Scrambler Initialization[0:6], FCS[23:31} + for 2MHz + ACK_ID (9bits)= { Scrambler Initialization[0:6], FCS[30:31]} + for 1MHz. Bits[15:9] should be filled with Zero by RxPCU + + + For NDP Modified ACK + ACK_ID (16bits)= {CRC[0:3],TA[0:8],RA[6:8]} for 2MHz + ACK_ID (9bits)= { CRC[0:3], TA[4:8]} for 1MHz; Bits[15:9] + should be filled with Zero by RxPCU. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x000000000000ffff + + +/* Description ACK_ID_EXT + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This is populated by RxPCU when the Duration Indication + Bit is set to Zero in the Received NDP PS-Poll Frame. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 + + +/* Description AGC_CBW + + BW as detected by the AGC + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 + + +/* Description SERVICE_CBW + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field reflects the BW extracted from the Serivce Field + for 11ac mode of operation and from the FC portion of the + MAC header in 11ah mode of operation. This field is used + in the context of Dynamic/Static BW evaluation purposes + in TxPCU + CBW field extracted from Service field by RXPCU and populates + this + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 + + +/* Description RESPONSE_STA_COUNT + + The number of STAs to which the responses need to be sent. + + + In case of multiple ACKs/BAs to be send, TXPCU uses this + field to determine what address formatting to use for the + response frame: This could be broadcast or unicast. + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 + + +/* Description RESERVED + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 39 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000078000000000 + + +/* Description HT_VHT_SIG_CBW + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Bandwidth of the received frame from either the HT-SIG or + VHT-SIG-A or HE-SIG. For HT-SIG, this bandwidth can be + 20 MHz or 40 MHz, For VHT or HE, this bandwidth can be 20, + 40, 80, or 160 MHz: + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 + + +/* Description CTS_CBW + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Calculated bandwidth for the CTS response frame + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 + + +/* Description RESPONSE_ACK_COUNT + + Field valid for both SU and MU reception + + ACK Count for management action frames, PS_POLL frames, + single data frame and the general "ACK ALL". For this last + one, a single "ACK" should be interpreted by the receiver + that all transmitted frames have been properly received. + + + For SU: + Max count can be 1 + Note that Response_ba64_count and/or Response_ba256_count + can be > 0, which implies that both an ACK and BA needs + to be send back. + + For MU: + The number of users that need an 'ACK' response. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 + + +/* Description RESPONSE_ASSOC_ACK_COUNT + + Field ONLY valid for Reception_is_MU. This count can only + be set to > 0, when there were wildcards send in the trigger + frame. + + ACK Count to be generated for Management frames from STAs + that are not yet associated to this device. These STAs + can only send this type of response when the trigger frame + included some wildcards. + + Note that in the MBA frame, this "ack" has a special format, + and includes more bytes then the normal "ack". For that + reason TXPCU needs to be able to differentiate between the + 'normal acks' and these association request acks... + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 + + +/* Description TXOP_DURATION_ALL_ONES + + When set, either the TXOP_DURATION of the received frame + was set to all 1s or there is a BSS color collision. The + TXOP_DURATION of the transmit response should be forced + to all 1s. + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 + + +/* Description RESPONSE_BA32_COUNT + + Field valid for both Reception_is_SU and Reception_is_MU + + + For SU: + Total number of '32 bitmap BA' responses for this one user. + + If this value is > 1, in implies that multi TID response + is needed. Also, if the sum of all the Response_ba??? Counts + ) > 1, a multi TID response is needed. + + For MU: + Total number of '32 bitmap BA' responses shared between + all the users. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f + + +/* Description RESPONSE_BA64_COUNT + + Field valid for both Reception_is_SU and Reception_is_MU + + + For SU: + Total number of '64 bitmap BA' responses for this one user. + + If this value is > 1, in implies that multi TID response + is needed. Also, if the sum of all the Response_ba??? Counts + ) > 1, a multi TID response is needed. + + For MU: + Total number of '64 bitmap BA' responses shared between + all the users. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 + + +/* Description RESPONSE_BA128_COUNT + + Field valid for both Reception_is_SU and Reception_is_MU + + + For SU: + Total number of '128 bitmap BA' responses for this one user. + + If this value is > 1, in implies that multi TID response + is needed. Also, if the sum of all the Response_ba??? Counts + ) > 1, a multi TID response is needed. + + For MU: + Total number of '128 bitmap BA' responses shared between + all the users. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 + + +/* Description RESPONSE_BA256_COUNT + + Field valid for both Reception_is_SU and Reception_is_MU + + + For SU: + Total number of '256 bitmap BA' responses for this one user. + + If this value is > 1, in implies that multi TID response + is needed. Also, if the sum of all the Response_ba??? Counts + ) > 1, a multi TID response is needed. + + For MU: + Total number of '256 bitmap BA' responses shared between + all the users. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 + + +/* Description MULTI_TID + + Field valid for both Reception_is_SU and Reception_is_MU + + + When set, RXPCU has for at least one user multiple bitmaps + available (which corresponds to multiple TIDs) + + Note that the sum of Response_ack_count, + response_ba32_count, response_ba64_count, + response_ba128_count, response_ba256_count is larger then + the total number of users. + + Note: There is no restriction on TXPCU to retrieve all the + bitmaps using explicit_user_request mode or not. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 + + +/* Description SW_RESPONSE_TLV_FROM_CRYPTO + + Field can only be set by MAC mitigation logic + + The idea is here that normally TXPCU generates the BA frame. + + But as a backup scenario, in case of a last moment BA format + change or some other issue, the BA frame could be fully + generated in the MAC micro CPU and pushed into TXPCU through + the Crypto - TXPCU TLV interface. + This feature can be used for any response frame generation. + From TXPCU perspective, all interaction with PDG remains + exactly the same, accept that the frame length is now coming + from field SW_Response_frame_length and the response frame + is pushed into TXPCU over the CRYPTO - TXPCU TLV interface + + + When set, this feature kick in + When clear, this feature is not enabled + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 + + +/* Description DOT11AX_DL_UL_FLAG + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + DL_UL_flag to be used for response frame sent to this device. + + + Differentiates between DL and UL transmission + + + + + Note: this setting can also come from response look-up table + in TXPCU... + The selection is SW programmable + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 + + +/* Description RESERVED_6A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MASK 0x0000000080000000 + + +/* Description SW_RESPONSE_FRAME_LENGTH + + Field only valid when SW_Response_tlv_from_crypto is set + + + This is the size of the frame that SW will generate as the + response frame. In those scenarios where TXPCU needs to + indicate a frame_length in the PDG_RESPONSE TLV, this will + be the value that TXPCU needs to use. + + Note that this value shall always be such that when PDG + calculates the LSIG duration field, the calculated value + is less then the max time duration that the LSIG length + can hold. + + Note that the MAX range here for + 11ax, MCS 11, BW 180, might not be reached. But as this + is just for 'normal HW generated response' frames, the range + is size here is more then enough. + Also not that this field is NOT used for trigger responses. + + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 + + +/* Description RESPONSE_BA512_COUNT + + Field valid for both Reception_is_SU and Reception_is_MU + + + For SU: + Total number of '512 bitmap BA' responses for this one user. + + If this value is > 1, in implies that multi TID response + is needed. Also, if the sum of all the Response_ba??? Counts + > 1, a multi TID response is needed. + + For MU: + Total number of '512 bitmap BA' responses shared between + all the users. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 + + +/* Description RESPONSE_BA1024_COUNT + + Field valid for both Reception_is_SU and Reception_is_MU + + + For SU: + Total number of '1024 bitmap BA' responses for this one + user. + If this value is > 1, in implies that multi TID response + is needed. Also, if the sum of all the Response_ba??? Counts + > 1, a multi TID response is needed. + + For MU: + Total number of '1024 bitmap BA' responses shared between + all the users. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 + + +/* Description RESERVED_7A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 + + +/* Description ADDR1_31_0 + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + lower 32 bits of addr1 of the received frame + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff + + +/* Description ADDR1_47_32 + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + upper 16 bits of addr1 of the received frame + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 + + +/* Description ADDR2_15_0 + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + lower 16 bits of addr2 of the received frame + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 + + +/* Description ADDR2_47_16 + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + upper 32 bits of addr2 of the received frame + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff + + +/* Description DOT11AX_RECEIVED_FORMAT_INDICATION + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + Format_Indication from the received frame. + + + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 + + +/* Description DOT11AX_RECEIVED_DL_UL_FLAG + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + DL_UL_flag from the received frame + + Differentiates between DL and UL transmission + + + + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 + + +/* Description DOT11AX_RECEIVED_BSS_COLOR_ID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + BSS_color_id from the received frame + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 + + +/* Description DOT11AX_RECEIVED_SPATIAL_REUSE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + Spatial reuse from the received frame + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 + + +/* Description DOT11AX_RECEIVED_CP_SIZE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + CP size of the received frame + + Specify the right GI for HE-Ranging NDPs (11az). + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 + + +/* Description DOT11AX_RECEIVED_LTF_SIZE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + LTF size of the received frame + + Specify the right LTF-size for HE-Ranging NDPs (11az). + + + + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 + + +/* Description DOT11AX_RECEIVED_CODING + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + Coding from the received frame + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 + + +/* Description DOT11AX_RECEIVED_DCM + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + DCM from the received frame + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 + + +/* Description DOT11AX_RECEIVED_DOPPLER_INDICATION + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + Doppler_indication from the received frame + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 + + +/* Description DOT11AX_RECEIVED_EXT_RU_SIZE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be AND dot11ax_su_extended is set + The number of (basic) RUs in this extended range reception + + + RXPCU gets this from the received HE_SIG_A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 + + +/* Description FTM_FIELDS_VALID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Field only valid in case ftm_en is set. + + When set, the other ftm_ fields are valid and TXCPU shall + use these in the response frame instead of the response + table based fields with a similar name. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 + + +/* Description FTM_PE_NSS + + Field only valid in case ftm_fields_valid is set. + + Number of active spatial streams during packet extension + for ftm related frame exchanges + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 + + +/* Description FTM_PE_LTF_SIZE + + Field only valid in case ftm_fields_valid is set. + + LTF size to be used during packet extention for ftm related + frame exchanges. + + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 + + +/* Description FTM_PE_CONTENT + + Field only valid in case ftm_fields_valid is set. + + The pe content for ftm related frame exchanges. + + Content of packet extension. + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 + + +/* Description FTM_CHAIN_CSD_EN + + Field only valid in case ftm_fields_valid is set. + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 + + +/* Description FTM_PE_CHAIN_CSD_EN + + Field only valid in case ftm_fields_valid is set. + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 + + +/* Description DOT11AX_RESPONSE_RATE_SOURCE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Valid for response generation to an 11ax pkt_type received + frame, but NOT 11ax extended pkt_type of frame + + When set to 0, use the register based lookup for determining + the 11ax response rates. + + When > 0, TXPCU shall use this response table index for + the 20 MHz response, and higher BW responses are in the + subsequent response table entries + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff + + +/* Description DOT11AX_EXT_RESPONSE_RATE_SOURCE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax and dot11ax_su_extended + is set + + When set to 0, the response rates are based on the 11ax + extended response register based indexes in TXPCU. + + When > 0, TXPCU shall use this response table index for + the response to a 1RU reception. Higher RU count reception + responses can be found in the subsequent response table + entries: Next entry is for 2 RU receptions, then 4 RU + receptions, then >= 8 RU receptions... + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 + + +/* Description SW_PEER_ID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + An identifier indicating for which device this response + is needed. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 + + +/* Description DOT11BE_PUNCTURE_BITMAP + + This field is only valid if Punctured_response is set + + The bitmap of 20 MHz sub-bands valid in this EHT reception + + + RXPCU gets this from the received U-SIG and/or EHT-SIG via + PHY microcode. + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 + + +/* Description DOT11BE_RESPONSE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Indicates that the peer supports .11be response protocols, + e.g. .11be BW indication in scrambler seed, .11be dynamic + BW procedure, punctured response, etc. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 + + +/* Description PUNCTURED_RESPONSE + + Field only valid if Dot11be_response is set + + Indicates that the response shall use preamble puncturing + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 + + +/* Description RESERVED_13A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 53 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e0000000000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + This field is only valid if Punctured_response is set + + The 6-bit value used in U-SIG and/or EHT-SIG Common field + for the puncture pattern + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + + +/* Description HE_A_CONTROL_RESPONSE_TIME + + When non-zero, indicates the value from an HE A-Control + in the received frame requiring a specific response time + (e.g. for sync MLO) + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 + + +/* Description RESERVED_AFTER_STRUCT16 + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_RESPONSE_REQUIRED_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/qcn6432/rx_rxpcu_classification_overview.h new file mode 100644 index 0000000000000000000000000000000000000000..d9cea64643f610a9c1fb1808c30f0ab5a2431998 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_rxpcu_classification_overview.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 + + +struct rx_rxpcu_classification_overview { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t filter_pass_mpdus : 1, // [0:0] + filter_pass_mpdus_fcs_ok : 1, // [1:1] + monitor_direct_mpdus : 1, // [2:2] + monitor_direct_mpdus_fcs_ok : 1, // [3:3] + monitor_other_mpdus : 1, // [4:4] + monitor_other_mpdus_fcs_ok : 1, // [5:5] + phyrx_abort_received : 1, // [6:6] + filter_pass_monitor_ovrd_mpdus : 1, // [7:7] + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, // [8:8] + reserved_0 : 7, // [15:9] + phy_ppdu_id : 16; // [31:16] +#else + uint32_t phy_ppdu_id : 16, // [31:16] + reserved_0 : 7, // [15:9] + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, // [8:8] + filter_pass_monitor_ovrd_mpdus : 1, // [7:7] + phyrx_abort_received : 1, // [6:6] + monitor_other_mpdus_fcs_ok : 1, // [5:5] + monitor_other_mpdus : 1, // [4:4] + monitor_direct_mpdus_fcs_ok : 1, // [3:3] + monitor_direct_mpdus : 1, // [2:2] + filter_pass_mpdus_fcs_ok : 1, // [1:1] + filter_pass_mpdus : 1; // [0:0] +#endif +}; + + +/* Description FILTER_PASS_MPDUS + + When set, at least one Filter Pass MPDU has been received. + FCS might or might not have been passing. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 + + +/* Description FILTER_PASS_MPDUS_FCS_OK + + When set, at least one Filter Pass MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + + +/* Description MONITOR_DIRECT_MPDUS + + When set, at least one Monitor Direct MPDU has been received. + FCS might or might not have been passing + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + + +/* Description MONITOR_DIRECT_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + + +/* Description MONITOR_OTHER_MPDUS + + When set, at least one Monitor Direct MPDU has been received. + FCS might or might not have been passing. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 + + +/* Description MONITOR_OTHER_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + + +/* Description PHYRX_ABORT_RECEIVED + + When set, PPDU reception was aborted by the PHY + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + + +/* Description FILTER_PASS_MONITOR_OVRD_MPDUS + + When set, at least one 'Filter Pass Monitor Override' MPDU + has been received. FCS might or might not have been passing. + + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 + + +/* Description FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK + + When set, at least one 'Filter Pass Monitor Override' MPDU + has been received that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 + + +/* Description RESERVED_0 + + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 + + + +#endif // RX_RXPCU_CLASSIFICATION_OVERVIEW diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_start_param.h b/drivers/staging/fw-api/hw/qcn6432/rx_start_param.h new file mode 100644 index 0000000000000000000000000000000000000000..361284e903c95cb658236e8501e021ae41b18dbf --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_start_param.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_START_PARAM_H_ +#define _RX_START_PARAM_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_START_PARAM 2 + +#define NUM_OF_QWORDS_RX_START_PARAM 1 + + +struct rx_start_param { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, // [3:0] + reserved_0a : 12, // [15:4] + remaining_rx_time : 16; // [31:16] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t remaining_rx_time : 16, // [31:16] + reserved_0a : 12, // [15:4] + pkt_type : 4; // [3:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RX_START_PARAM_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_START_PARAM_PKT_TYPE_LSB 0 +#define RX_START_PARAM_PKT_TYPE_MSB 3 +#define RX_START_PARAM_PKT_TYPE_MASK 0x000000000000000f + + +/* Description RESERVED_0A + + +*/ + +#define RX_START_PARAM_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_START_PARAM_RESERVED_0A_LSB 4 +#define RX_START_PARAM_RESERVED_0A_MSB 15 +#define RX_START_PARAM_RESERVED_0A_MASK 0x000000000000fff0 + + +/* Description REMAINING_RX_TIME + + Remaining time (in us) for the current frame in the medium. + + (received from PHY in TLV: PHYRX_COMMON_USER_INFO.Receive_duration) + + +*/ + +#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x0000000000000000 +#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 +#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 +#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0x00000000ffff0000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_START_PARAM_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_START_PARAM_TLV64_PADDING_LSB 32 +#define RX_START_PARAM_TLV64_PADDING_MSB 63 +#define RX_START_PARAM_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_START_PARAM diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_timing_offset_info.h b/drivers/staging/fw-api/hw/qcn6432/rx_timing_offset_info.h new file mode 100644 index 0000000000000000000000000000000000000000..64a481aac2081dfad568420ff4999448297a7e86 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_timing_offset_info.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_TIMING_OFFSET_INFO_H_ +#define _RX_TIMING_OFFSET_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1 + + +struct rx_timing_offset_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t residual_phase_offset : 12, // [11:0] + reserved : 20; // [31:12] +#else + uint32_t reserved : 20, // [31:12] + residual_phase_offset : 12; // [11:0] +#endif +}; + + +/* Description RESIDUAL_PHASE_OFFSET + + Cumulative reference frequency error at end of RX packet, + expressed as the phase offset measured over 0.8us. + +*/ + +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_LSB 0 +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MSB 11 +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + + +/* Description RESERVED + + +*/ + +#define RX_TIMING_OFFSET_INFO_RESERVED_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_RESERVED_LSB 12 +#define RX_TIMING_OFFSET_INFO_RESERVED_MSB 31 +#define RX_TIMING_OFFSET_INFO_RESERVED_MASK 0xfffff000 + + + +#endif // RX_TIMING_OFFSET_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/rx_trig_info.h b/drivers/staging/fw-api/hw/qcn6432/rx_trig_info.h new file mode 100644 index 0000000000000000000000000000000000000000..0ad3b33bdc86b7ea51e3baaf5861a1c2e02c00a7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rx_trig_info.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_TRIG_INFO_H_ +#define _RX_TRIG_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_TRIG_INFO 2 + +#define NUM_OF_QWORDS_RX_TRIG_INFO 1 + + +struct rx_trig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_trigger_frame_type : 2, // [1:0] + trigger_resp_type : 3, // [4:2] + reserved_0 : 27; // [31:5] + uint32_t ppdu_duration : 16, // [15:0] + unique_destination_id : 16; // [31:16] +#else + uint32_t reserved_0 : 27, // [31:5] + trigger_resp_type : 3, // [4:2] + rx_trigger_frame_type : 2; // [1:0] + uint32_t unique_destination_id : 16, // [31:16] + ppdu_duration : 16; // [15:0] +#endif +}; + + +/* Description RX_TRIGGER_FRAME_TYPE + + Trigger frame type. + + Field not really needed by PDG, but is there for debugging + purposes to be put in event. + + + + + + +*/ + +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003 + + +/* Description TRIGGER_RESP_TYPE + + Indicates what kind of response is required to the received + OFDMA trigger... + + Field not really needed by PDG, but is there for debugging + purposes to be put in event. + OFDMA trigger indicates an OFDMA + based transmission, where the contents shall be and ACK + frame. + OFDMA trigger indicates an OFDMA + based transmission, where the contents shall be a BA frame. + + OFDMA trigger indicates an OFDMA + based transmission, where the contents shall be only data. + + OFDMA trigger indicates an + OFDMA based transmission, where the contents shall be a + BA frame and data. + + +*/ + +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c + + +/* Description RESERVED_0 + + Reserved and unused by HW + +*/ + +#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_RESERVED_0_LSB 5 +#define RX_TRIG_INFO_RESERVED_0_MSB 31 +#define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0 + + +/* Description PPDU_DURATION + + 11ax + This field is valid only when rx_trig_frame is dot11ax_direct_trigger_frame + or dot11ax_wildcard_trigger_frame or dot11ax_usassoc_wildcard_trigger_frame + + + The PPDU duration populated in trigger frame. This is the + duration that station is allowed to use to transmit the + packet +*/ + +#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_PPDU_DURATION_LSB 32 +#define RX_TRIG_INFO_PPDU_DURATION_MSB 47 +#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000 + + +/* Description UNIQUE_DESTINATION_ID + + 11ax + This field is valid only when rx_trig_frame is dot11ax_direct_trigger_frame + or dot11ax_wildcard_trigger_frame or dot11ax_usassoc_wildcard_trigger_frame + + + Unique destination identification number used by HWSCH to + compare with the station ID in the command +*/ + +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000 + + + +#endif // RX_TRIG_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/rxpcu_early_rx_indication.h b/drivers/staging/fw-api/hw/qcn6432/rxpcu_early_rx_indication.h new file mode 100644 index 0000000000000000000000000000000000000000..27d3d7b5f95f329c43510130da912736c3854686 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rxpcu_early_rx_indication.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RXPCU_EARLY_RX_INDICATION_H_ +#define _RXPCU_EARLY_RX_INDICATION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2 + +#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1 + + +struct rxpcu_early_rx_indication { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, // [3:0] + dot11ax_su_extended : 1, // [4:4] + rate_mcs : 4, // [8:5] + dot11ax_received_ext_ru_size : 4, // [12:9] + reserved_0a : 19; // [31:13] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0a : 19, // [31:13] + dot11ax_received_ext_ru_size : 4, // [12:9] + rate_mcs : 4, // [8:5] + dot11ax_su_extended : 1, // [4:4] + pkt_type : 4; // [3:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PKT_TYPE + + Packet type: + + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x000000000000000f + + +/* Description DOT11AX_SU_EXTENDED + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be + + When set, the 11ax or 11be reception was an extended range + SU +*/ + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x0000000000000010 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 8 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x00000000000001e0 + + +/* Description DOT11AX_RECEIVED_EXT_RU_SIZE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be AND dot11ax_su_extended is set + The number of (basic) RUs in this extended range reception + + + RXPCU gets this from the received HE_SIG_A + + +*/ + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 9 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 12 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0000000000001e00 + + +/* Description RESERVED_0A + + +*/ + +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 13 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0x00000000ffffe000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB 32 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB 63 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RXPCU_EARLY_RX_INDICATION diff --git a/drivers/staging/fw-api/hw/qcn6432/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/qcn6432/rxpcu_ppdu_end_info.h new file mode 100644 index 0000000000000000000000000000000000000000..00b1430707d21b4f8ad7f1f495f49dc32c07f309 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rxpcu_ppdu_end_info.h @@ -0,0 +1,2002 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RXPCU_PPDU_END_INFO_H_ +#define _RXPCU_PPDU_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_abort_request_info.h" +#include "macrx_abort_request_info.h" +#include "rxpcu_ppdu_end_layout_info.h" +#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 28 + +#define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 14 + + +struct rxpcu_ppdu_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t wb_timestamp_lower_32 : 32; // [31:0] + uint32_t wb_timestamp_upper_32 : 32; // [31:0] + uint32_t rx_antenna : 24, // [23:0] + tx_ht_vht_ack : 1, // [24:24] + unsupported_mu_nc : 1, // [25:25] + otp_txbf_disable : 1, // [26:26] + previous_tlv_corrupted : 1, // [27:27] + phyrx_abort_request_info_valid : 1, // [28:28] + macrx_abort_request_info_valid : 1, // [29:29] + reserved : 2; // [31:30] + uint32_t coex_bt_tx_from_start_of_rx : 1, // [0:0] + coex_bt_tx_after_start_of_rx : 1, // [1:1] + coex_wan_tx_from_start_of_rx : 1, // [2:2] + coex_wan_tx_after_start_of_rx : 1, // [3:3] + coex_wlan_tx_from_start_of_rx : 1, // [4:4] + coex_wlan_tx_after_start_of_rx : 1, // [5:5] + mpdu_delimiter_errors_seen : 1, // [6:6] + ftm_tm : 2, // [8:7] + dialog_token : 8, // [16:9] + follow_up_dialog_token : 8, // [24:17] + bb_captured_channel : 1, // [25:25] + bb_captured_reason : 3, // [28:26] + bb_captured_timeout : 1, // [29:29] + reserved_3 : 2; // [31:30] + uint32_t before_mpdu_count_passing_fcs : 10, // [9:0] + before_mpdu_count_failing_fcs : 10, // [19:10] + after_mpdu_count_passing_fcs : 10, // [29:20] + reserved_4 : 2; // [31:30] + uint32_t after_mpdu_count_failing_fcs : 10, // [9:0] + reserved_5 : 22; // [31:10] + uint32_t phy_timestamp_tx_lower_32 : 32; // [31:0] + uint32_t phy_timestamp_tx_upper_32 : 32; // [31:0] + uint32_t bb_length : 16, // [15:0] + bb_data : 1, // [16:16] + reserved_8 : 3, // [19:17] + first_bt_broadcast_status_details : 12; // [31:20] + uint32_t rx_ppdu_duration : 24, // [23:0] + reserved_9 : 8; // [31:24] + uint32_t ast_index : 16, // [15:0] + ast_index_valid : 1, // [16:16] + reserved_10 : 3, // [19:17] + second_bt_broadcast_status_details : 12; // [31:20] + struct phyrx_abort_request_info phyrx_abort_request_info_details; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint16_t pre_bt_broadcast_status_details : 12, // [27:16] + reserved_12a : 4; // [31:28] + uint32_t non_qos_sn_info_valid : 1, // [0:0] + reserved_13a : 5, // [5:1] + non_qos_sn_highest : 12, // [17:6] + non_qos_sn_highest_retry_setting : 1, // [18:18] + non_qos_sn_lowest : 12, // [30:19] + non_qos_sn_lowest_retry_setting : 1; // [31:31] + uint32_t qos_sn_1_info_valid : 1, // [0:0] + reserved_14a : 1, // [1:1] + qos_sn_1_tid : 4, // [5:2] + qos_sn_1_highest : 12, // [17:6] + qos_sn_1_highest_retry_setting : 1, // [18:18] + qos_sn_1_lowest : 12, // [30:19] + qos_sn_1_lowest_retry_setting : 1; // [31:31] + uint32_t qos_sn_2_info_valid : 1, // [0:0] + reserved_15a : 1, // [1:1] + qos_sn_2_tid : 4, // [5:2] + qos_sn_2_highest : 12, // [17:6] + qos_sn_2_highest_retry_setting : 1, // [18:18] + qos_sn_2_lowest : 12, // [30:19] + qos_sn_2_lowest_retry_setting : 1; // [31:31] + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t corrupted_due_to_fifo_delay : 1, // [0:0] + qos_sn_1_more_frag_state : 1, // [1:1] + qos_sn_1_frag_num_state : 4, // [5:2] + qos_sn_2_more_frag_state : 1, // [6:6] + qos_sn_2_frag_num_state : 4, // [10:7] + reserved_26a : 21; // [31:11] + uint32_t rx_ppdu_end_marker : 32; // [31:0] +#else + uint32_t wb_timestamp_lower_32 : 32; // [31:0] + uint32_t wb_timestamp_upper_32 : 32; // [31:0] + uint32_t reserved : 2, // [31:30] + macrx_abort_request_info_valid : 1, // [29:29] + phyrx_abort_request_info_valid : 1, // [28:28] + previous_tlv_corrupted : 1, // [27:27] + otp_txbf_disable : 1, // [26:26] + unsupported_mu_nc : 1, // [25:25] + tx_ht_vht_ack : 1, // [24:24] + rx_antenna : 24; // [23:0] + uint32_t reserved_3 : 2, // [31:30] + bb_captured_timeout : 1, // [29:29] + bb_captured_reason : 3, // [28:26] + bb_captured_channel : 1, // [25:25] + follow_up_dialog_token : 8, // [24:17] + dialog_token : 8, // [16:9] + ftm_tm : 2, // [8:7] + mpdu_delimiter_errors_seen : 1, // [6:6] + coex_wlan_tx_after_start_of_rx : 1, // [5:5] + coex_wlan_tx_from_start_of_rx : 1, // [4:4] + coex_wan_tx_after_start_of_rx : 1, // [3:3] + coex_wan_tx_from_start_of_rx : 1, // [2:2] + coex_bt_tx_after_start_of_rx : 1, // [1:1] + coex_bt_tx_from_start_of_rx : 1; // [0:0] + uint32_t reserved_4 : 2, // [31:30] + after_mpdu_count_passing_fcs : 10, // [29:20] + before_mpdu_count_failing_fcs : 10, // [19:10] + before_mpdu_count_passing_fcs : 10; // [9:0] + uint32_t reserved_5 : 22, // [31:10] + after_mpdu_count_failing_fcs : 10; // [9:0] + uint32_t phy_timestamp_tx_lower_32 : 32; // [31:0] + uint32_t phy_timestamp_tx_upper_32 : 32; // [31:0] + uint32_t first_bt_broadcast_status_details : 12, // [31:20] + reserved_8 : 3, // [19:17] + bb_data : 1, // [16:16] + bb_length : 16; // [15:0] + uint32_t reserved_9 : 8, // [31:24] + rx_ppdu_duration : 24; // [23:0] + uint32_t second_bt_broadcast_status_details : 12, // [31:20] + reserved_10 : 3, // [19:17] + ast_index_valid : 1, // [16:16] + ast_index : 16; // [15:0] + struct phyrx_abort_request_info phyrx_abort_request_info_details; + uint32_t reserved_12a : 4, // [31:28] + pre_bt_broadcast_status_details : 12; // [27:16] + struct macrx_abort_request_info macrx_abort_request_info_details; + uint32_t non_qos_sn_lowest_retry_setting : 1, // [31:31] + non_qos_sn_lowest : 12, // [30:19] + non_qos_sn_highest_retry_setting : 1, // [18:18] + non_qos_sn_highest : 12, // [17:6] + reserved_13a : 5, // [5:1] + non_qos_sn_info_valid : 1; // [0:0] + uint32_t qos_sn_1_lowest_retry_setting : 1, // [31:31] + qos_sn_1_lowest : 12, // [30:19] + qos_sn_1_highest_retry_setting : 1, // [18:18] + qos_sn_1_highest : 12, // [17:6] + qos_sn_1_tid : 4, // [5:2] + reserved_14a : 1, // [1:1] + qos_sn_1_info_valid : 1; // [0:0] + uint32_t qos_sn_2_lowest_retry_setting : 1, // [31:31] + qos_sn_2_lowest : 12, // [30:19] + qos_sn_2_highest_retry_setting : 1, // [18:18] + qos_sn_2_highest : 12, // [17:6] + qos_sn_2_tid : 4, // [5:2] + reserved_15a : 1, // [1:1] + qos_sn_2_info_valid : 1; // [0:0] + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t reserved_26a : 21, // [31:11] + qos_sn_2_frag_num_state : 4, // [10:7] + qos_sn_2_more_frag_state : 1, // [6:6] + qos_sn_1_frag_num_state : 4, // [5:2] + qos_sn_1_more_frag_state : 1, // [1:1] + corrupted_due_to_fifo_delay : 1; // [0:0] + uint32_t rx_ppdu_end_marker : 32; // [31:0] +#endif +}; + + +/* Description WB_TIMESTAMP_LOWER_32 + + WLAN/BT timestamp is a 1 usec resolution timestamp which + does not get updated based on receive beacon like TSF. + The same rules for capturing tsf_timestamp are used to + capture the wb_timestamp. This field represents the lower + 32 bits of the 64-bit timestamp +*/ + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + + +/* Description WB_TIMESTAMP_UPPER_32 + + WLAN/BT timestamp is a 1 usec resolution timestamp which + does not get updated based on receive beacon like TSF. + The same rules for capturing tsf_timestamp are used to + capture the wb_timestamp. This field represents the upper + 32 bits of the 64-bit timestamp +*/ + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + + +/* Description RX_ANTENNA + + Receive antenna value ??? +*/ + +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff + + +/* Description TX_HT_VHT_ACK + + Indicates that a HT or VHT Ack/BA frame was transmitted + in response to this receive packet. +*/ + +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 + + + +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 + + +/* Description OTP_TXBF_DISABLE + + Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is + set and if RXPU receives directed NDPA frame. Then, RXPCU + should not send TX_EXPECT_NDP TLV to SW but set this bit + to inform SW. +*/ + +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 + + +/* Description PREVIOUS_TLV_CORRUPTED + + When set, the TLV preceding this RXPCU_END_INFO TLV within + the RX_PPDU_END TLV, is corrupted. Not the entire TLV was + received.... Likely due to an abort scenario... If abort + is to blame, see the abort data datastructure for details. + + +*/ + +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 + + +/* Description PHYRX_ABORT_REQUEST_INFO_VALID + + When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to RXPCU. + The abort fields embedded in this TLV contain valid info. + + +*/ + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 + + +/* Description MACRX_ABORT_REQUEST_INFO_VALID + + When set, the MAC sent an MACRX_ABORT_REQUEST TLV to PHYRX. + The abort fields embedded in this TLV contain valid info. + + +*/ + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 + + +/* Description RESERVED + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_MASK 0x00000000c0000000 + + +/* Description COEX_BT_TX_FROM_START_OF_RX + + Set when BT TX was ongoing when WLAN RX started +*/ + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 + + +/* Description COEX_BT_TX_AFTER_START_OF_RX + + Set when BT TX started while WLAN RX was already ongoing + +*/ + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 + + +/* Description COEX_WAN_TX_FROM_START_OF_RX + + Set when WAN TX was ongoing when WLAN RX started +*/ + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 + + +/* Description COEX_WAN_TX_AFTER_START_OF_RX + + Set when WAN TX started while WLAN RX was already ongoing + +*/ + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 + + +/* Description COEX_WLAN_TX_FROM_START_OF_RX + + Set when other WLAN TX was ongoing when WLAN RX started +*/ + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 + + +/* Description COEX_WLAN_TX_AFTER_START_OF_RX + + Set when other WLAN TX started while WLAN RX was already + ongoing +*/ + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 + + +/* Description MPDU_DELIMITER_ERRORS_SEEN + + When set, MPDU delimiter errors have been detected during + this PPDU reception +*/ + +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 + + +/* Description FTM_TM + + Indicate the timestamp is for the FTM or TM frame + + 0: non TM or FTM frame + 1: FTM frame + 2: TM frame + 3: reserved + +*/ + +#define RXPCU_PPDU_END_INFO_FTM_TM_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_FTM_TM_LSB 39 +#define RXPCU_PPDU_END_INFO_FTM_TM_MSB 40 +#define RXPCU_PPDU_END_INFO_FTM_TM_MASK 0x0000018000000000 + + +/* Description DIALOG_TOKEN + + The dialog token in the FTM or TM frame. Only valid when + the FTM is set. Clear to 254 for a non-FTM frame + +*/ + +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 + + +/* Description FOLLOW_UP_DIALOG_TOKEN + + The follow up dialog token in the FTM or TM frame. Only + valid when the FTM is set. Clear to 0 for a non-FTM frame, + The follow up dialog token in the FTM frame. Only valid + when the FTM is set. Clear to 255 for a non-FTM frame +*/ + +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 + + +/* Description BB_CAPTURED_CHANNEL + + Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is sent + to PHY, FW check it to correlate current PPDU TLVs with + uploaded channel information. + + +*/ + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 + + +/* Description BB_CAPTURED_REASON + + Copy "capture_reason" of MACRX_FREEZE_CAPTURE_CHANNEL TLV + to here for FW usage. Valid when bb_captured_channel or + bb_captured_timeout is set. + + This field indicates why the MAC asked to capture the channel + + + + + + + + + +*/ + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 + + +/* Description BB_CAPTURED_TIMEOUT + + Set by RxPCU to indicate channel capture condition is meet, + but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due + to AST long delay, which means the rx_frame_falling edge + to FREEZE TLV ready time exceed the threshold time defined + by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. + Bb_captured_reason is still valid in this case. + + +*/ + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 + + +/* Description RESERVED_3 + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_3_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_RESERVED_3_LSB 62 +#define RXPCU_PPDU_END_INFO_RESERVED_3_MSB 63 +#define RXPCU_PPDU_END_INFO_RESERVED_3_MASK 0xc000000000000000 + + +/* Description BEFORE_MPDU_COUNT_PASSING_FCS + + Number of MPDUs received in this PPDU that passed the FCS + check before the Coex TX started + + The counter saturates at 0x3FF. + +*/ + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff + + +/* Description BEFORE_MPDU_COUNT_FAILING_FCS + + Number of MPDUs received in this PPDU that failed the FCS + check before the Coex TX started + + The counter saturates at 0x3FF. + +*/ + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 + + +/* Description AFTER_MPDU_COUNT_PASSING_FCS + + Number of MPDUs received in this PPDU that passed the FCS + check after the moment the Coex TX started + + (Note: The partially received MPDU when the COEX tx start + event came in falls in the "after" category) + + The counter saturates at 0x3FF. + +*/ + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 + + +/* Description RESERVED_4 + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 + + +/* Description AFTER_MPDU_COUNT_FAILING_FCS + + Number of MPDUs received in this PPDU that failed the FCS + check after the moment the Coex TX started + + (Note: The partially received MPDU when the COEX tx start + event came in falls in the "after" category) + + The counter saturates at 0x3FF. + +*/ + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 + + +/* Description RESERVED_5 + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 + + +/* Description PHY_TIMESTAMP_TX_LOWER_32 + + The PHY timestamp in the AMPI of the most recent rising + edge (TODO: of what ???) after the TX_PHY_DESC. This field + indicates the lower 32 bits of the timestamp +*/ + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff + + +/* Description PHY_TIMESTAMP_TX_UPPER_32 + + The PHY timestamp in the AMPI of the most recent rising + edge (TODO: of what ???) after the TX_PHY_DESC. This field + indicates the upper 32 bits of the timestamp +*/ + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 + + +/* Description BB_LENGTH + + Indicates the number of bytes of baseband information for + PPDUs where the BB descriptor preamble type is 0x80 to + 0xFF which indicates that this is not a normal PPDU but + rather contains baseband debug information. + TODO: Is this still needed ??? +*/ + +#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff + + + +#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 + + +/* Description RESERVED_8 + + Reserved: HW should fill with 0, FW should ignore. +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 + + +/* Description FIRST_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the first received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + If no COEX_STATUS_BROADCAST tlv is received during this + PPDU reception, this field will be set to 0 + + +*/ + +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 + + +/* Description RX_PPDU_DURATION + + The length of this PPDU reception in us +*/ + +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 + + +/* Description RESERVED_9 + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 + + +/* Description AST_INDEX + + The AST index of the receive Ack/BA. This information is + provided from the TXPCU to the RXPCU for receive Ack/BA + for implicit beamforming. + +*/ + +#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff + + +/* Description AST_INDEX_VALID + + Indicates that ast_index is valid. Should only be set for + receive Ack/BA where single stream implicit sounding is + captured. +*/ + +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 + + +/* Description RESERVED_10 + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 + + +/* Description SECOND_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the second received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + If no second COEX_STATUS_BROADCAST tlv is received during + this PPDU reception, this field will be set to 0 + + +*/ + +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 + + +/* Description PHYRX_ABORT_REQUEST_INFO_DETAILS + + Field only valid when Phyrx_abort_request_info_valid is + set + The reason why PHY generated an abort request +*/ + + +/* Description PHYRX_ABORT_REASON + + Reception aborted due to receiving + a PHY_OFF TLV + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Should not really be used. If + needed, ask for documentation update + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +*/ + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 + + +/* Description PHY_ENTERS_NAP_STATE + + When set, PHY enters PHY NAP state after sending this abort + + + Note that nap and defer state are mutually exclusive. + + Field put pro-actively in place....usage still to be agreed + upon. + +*/ + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 + + +/* Description PHY_ENTERS_DEFER_STATE + + When set, PHY enters PHY defer state after sending this + abort + + Note that nap and defer state are mutually exclusive. + + Field put pro-actively in place....usage still to be agreed + upon. + +*/ + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 + + +/* Description RESERVED_0 + + +*/ + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 42 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc0000000000 + + +/* Description RECEIVE_DURATION + + The remaining receive duration of this PPDU in the medium + (in us). When PHY does not know this duration when this + TLV is generated, the field will be set to 0. + The timing reference point is the reception by the MAC of + this TLV. The value shall be accurate to within 2us. + + In case Phy_enters_nap_state and/or Phy_enters_defer_state + is set, there is a possibility that MAC PMM can also decide + to go into a low(er) power state. + +*/ + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 + + +/* Description MACRX_ABORT_REQUEST_INFO_DETAILS + + Field only valid when macrx_abort_request_info_valid is + set + The reason why MACRX generated an abort request +*/ + + +/* Description MACRX_ABORT_REASON + + + Upon receiving this + abort reason, PHY should stop reception of the current frame + and go back into a search mode + + MAC FW + issued an abort for channel switch reasons + MAC FW issued + an abort power save reasons + RXPCU is terminating + the current ongoing reception, as the data that MAC is + receiving seems to be all garbage... The PER is too high, + or in case of MU UL, Likely the trigger frame never got + properly received by any of the targeted MU UL devices. + After the abort, PHYRX can resume a normal search mode. + RXPCU is terminating + the current ongoing UL MU reception, because at the end + of the "early_termination_window," the required number + of users with at least one valid MPDU delimiter was not + reached. Likely the trigger frame never got properly received + by the required number of targeted devices. After the abort, + PHYRX can resume a normal search mode. + + +*/ + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff + + +/* Description RESERVED_0 + + +*/ + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 + + +/* Description PRE_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" of + the last received COEX_STATUS_BROADCAST tlv before this + PPDU reception. + After power up, this field is all initialized to 0 + + +*/ + +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 + + +/* Description RESERVED_12A + + Bits: [27:16] + Same contents as field "bt_broadcast_status_details" of + the last received COEX_STATUS_BROADCAST tlv before this + PPDU reception. + After power up, this field is all initialized to 0 + + Bits: [31:28]: always 0 + + + For detailed info see doc: TBD + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 + + +/* Description NON_QOS_SN_INFO_VALID + + When set, the non_QoS_SN_... fields contain valid info. + + This field will ONLY be set upon the very first reception + of a non QoS frame. + + +*/ + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 + + +/* Description RESERVED_13A + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 33 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003e00000000 + + +/* Description NON_QOS_SN_HIGHEST + + Field only valid when non_QoS_SN_info_valid is set + + Lowest and highest are defined based on a 2K window. + When only 1 non-QoS frame is received, the 'highest' and + 'lowest' fields will have the same values. + + The highest MPDU sequence number for a non-QoS frame received + in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 + + +/* Description NON_QOS_SN_HIGHEST_RETRY_SETTING + + Field only valid when non_QoS_SN_info_valid is set + + The 'retry' bit setting of the highest MPDU sequence number + non-QOS frame received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 + + +/* Description NON_QOS_SN_LOWEST + + Field only valid when non_QoS_SN_info_valid is set + + Lowest and highest are defined based on a 2K window. + When only 1 non-QoS frame is received, the 'highest' and + 'lowest' fields will have the same values. + + The lowest MPDU sequence number for a non-QoS frame received + in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 + + +/* Description NON_QOS_SN_LOWEST_RETRY_SETTING + + Field only valid when non_QoS_SN_info_valid is set + + The 'retry' bit setting of the lowest MPDU sequence number + non-QoS frame received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 + + +/* Description QOS_SN_1_INFO_VALID + + When set, the QoS_SN_1_... fields contain valid info. + + This field will ONLY be set upon the very first reception + of a QoS frame. + + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 + + +/* Description RESERVED_14A + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 + + +/* Description QOS_SN_1_TID + + Field only valid when QoS_SN_1_info_valid is set. + + The TID of the frames related to the QoS_SN_1_... fields + + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c + + +/* Description QOS_SN_1_HIGHEST + + Field only valid when QoS_SN_1_info_valid is set. + + Lowest and highest are defined based on a 2K window. + When only 1 QoS frame of the relevant TID is received, the + 'highest' and 'lowest' fields will have the same values. + + + The highest MPDU sequence number for a QoS frame with TID + QoS_SN_1_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 + + +/* Description QOS_SN_1_HIGHEST_RETRY_SETTING + + Field only valid when QoS_SN_1_info_valid is set. + + The 'retry' bit setting of the highest MPDU sequence number + QoS frame with TID QoS_SN_1_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 + + +/* Description QOS_SN_1_LOWEST + + Field only valid when QoS_SN_1_info_valid is set. + + Lowest and highest are defined based on a 2K window. + When only 1 QoS frame of the relevant TID is received, the + 'highest' and 'lowest' fields will have the same values. + + + The lowest MPDU sequence number for a QoS frame with TID + QoS_SN_1_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 + + +/* Description QOS_SN_1_LOWEST_RETRY_SETTING + + Field only valid when QoS_SN_1_info_valid is set. + + The 'retry' bit setting of the lowest MPDU sequence number + QoS frame with TID QoS_SN_1_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 + + +/* Description QOS_SN_2_INFO_VALID + + When set, the QoS_SN_2_... fields contain valid info. + + This field can ONLY be set in case of a multi-TID PPDU reception. + This field is set upon the very first reception of a QoS + frame belonging to the second TID in the PPDU. + + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 + + +/* Description RESERVED_15A + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 + + +/* Description QOS_SN_2_TID + + Field only valid when QoS_SN_2_info_valid is set. + + The TID of the frames related to the QoS_SN_2_... fields + + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 + + +/* Description QOS_SN_2_HIGHEST + + Field only valid when QoS_SN_2_info_valid is set. + + Lowest and highest are defined based on a 2K window. + When only 1 QoS frame of the relevant TID is received, the + highest and lowest fields will have the same values. + + The highest MPDU sequence number for a QoS frame with TID + QoS_SN_2_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 + + +/* Description QOS_SN_2_HIGHEST_RETRY_SETTING + + Field only valid when QoS_SN_2_info_valid is set. + + The 'retry' bit setting of the highest MPDU sequence number + QoS frame with TID QoS_SN_2_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 + + +/* Description QOS_SN_2_LOWEST + + Field only valid when QoS_SN_2_info_valid is set. + + Lowest and highest are defined based on a 2K window. + When only 1 QoS frame of the relevant TID is received, the + highest and lowest fields will have the same values. + + The lowest MPDU sequence number for a QoS frame with TID + QoS_SN_2_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 + + +/* Description QOS_SN_2_LOWEST_RETRY_SETTING + + Field only valid when QoS_SN_2_info_valid is set. + + The 'retry' bit setting of the lowest MPDU sequence number + QoS frame with TID QoS_SN_2_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 + + +/* Description RXPCU_PPDU_END_LAYOUT_DETAILS + + Structure containing the relative offsets of preamble TLVs + within 'RX_PPDU_END' documenting the layout within 'RX_PPDU_END' + +*/ + + +/* Description RSSI_LEGACY_OFFSET + + Offset in units of 4 bytes of 'PHYRX_RSSI_LEGACY' within + 'RX_PPDU_END' +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 + + +/* Description L_SIG_A_OFFSET + + Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc + + +/* Description L_SIG_B_OFFSET + + Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 + + +/* Description HT_SIG_OFFSET + + Offset of 'PHYRX_HT_SIG' within 'RX_PPDU_END' Set to zero + if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 + + +/* Description VHT_SIG_A_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_A' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 + + +/* Description REPEAT_L_SIG_A_OFFSET + + Offset in units of 4 bytes of the repeat 'PHYRX_L_SIG_A' (in + HE and EHT cases) within 'RX_PPDU_END' + + Set to zero if the TLV is not included + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 + + +/* Description HE_SIG_A_SU_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_SU' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 + + +/* Description HE_SIG_A_MU_DL_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_DL' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 + + +/* Description HE_SIG_A_MU_UL_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_UL' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 + + +/* Description GENERIC_U_SIG_OFFSET + + Offset in units of 4 bytes of 'PHYRX_GENERIC_U_SIG' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 + + +/* Description RSSI_HT_OFFSET + + Offset in units of 4 bytes of 'PHYRX_RSSI_HT' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 + + +/* Description VHT_SIG_B_SU20_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU20' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f + + +/* Description VHT_SIG_B_SU40_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU40' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 + + +/* Description VHT_SIG_B_SU80_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU80' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 + + +/* Description VHT_SIG_B_SU160_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU160' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 + + +/* Description RESERVED_2A + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 + + +/* Description VHT_SIG_B_MU20_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU20' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 + + +/* Description VHT_SIG_B_MU40_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU40' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 + + +/* Description VHT_SIG_B_MU80_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU80' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 + + +/* Description VHT_SIG_B_MU160_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU160' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 + + +/* Description RESERVED_3A + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 + + +/* Description HE_SIG_B1_MU_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_B1_MU' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f + + +/* Description HE_SIG_B2_MU_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_MU' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 + + +/* Description HE_SIG_B2_OFDMA_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_OFDMA' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 + + +/* Description FIRST_GENERIC_EHT_SIG_OFFSET + + Offset in units of 4 bytes of the first 'PHYRX_GENERIC_EHT_SIG' + within 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 + + +/* Description MULTIPLE_GENERIC_EHT_SIG_INCLUDED + + Set to one if more than one 'PHYRX_GENERIC_EHT_SIG' TLVs + are included in 'RX_PPDU_END,' set to zero otherwise + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 + + +/* Description RESERVED_4A + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 + + +/* Description COMMON_USER_INFO_OFFSET + + Offset in units of 4 bytes of 'PHYRX_COMMON_USER_INFO' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 + + +/* Description FIRST_DEBUG_INFO_OFFSET + + Offset in units of 4 bytes of the first 'PHYRX_DEBUG_INFO' + within 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 + + +/* Description MULTIPLE_DEBUG_INFO_INCLUDED + + Set to one if more than one 'PHYRX_DEBUG_INFO' TLVs are + included in 'RX_PPDU_END,' set to zero otherwise + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 + + +/* Description FIRST_OTHER_RECEIVE_INFO_OFFSET + + Offset in units of 4 bytes of the first 'PHYRX_OTHER_RECEIVE_INFO' + within 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 + + +/* Description MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED + + Set to one if more than one 'PHYRX_OTHER_RECEIVE_INFO' TLVs + are included in 'RX_PPDU_END,' set to zero otherwise +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 + + +/* Description RESERVED_5A + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 + + +/* Description DATA_DONE_OFFSET + + Offset in units of 4 bytes of 'PHYRX_DATA_DONE' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff + + +/* Description GENERATED_CBF_DETAILS_OFFSET + + Offset in units of 4 bytes of 'PHYRX_GENERATED_CBF_DETAILS' + within 'RX_PPDU_END'Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 + + +/* Description PKT_END_PART1_OFFSET + + Offset in units of 4 bytes of 'PHYRX_PKT_END_PART1' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 + + +/* Description LOCATION_OFFSET + + Offset in units of 4 bytes of 'PHYRX_LOCATION' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 + + +/* Description AZ_INTEGRITY_DATA_OFFSET + + Offset in units of 4 bytes of 'PHYRX_11AZ_INTEGRITY_DATA' + within 'RX_PPDU_END' + + Set to zero if the TLV is not included + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MSB 39 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff00000000 + + +/* Description PKT_END_OFFSET + + Offset in units of 4 bytes of 'PHYRX_PKT_END' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 + + +/* Description ABORT_REQUEST_ACK_OFFSET + + Offset in units of 4 bytes of either 'PHYRX_ABORT_REQUEST' + or 'PHYRX_ABORT_ACK' within 'RX_PPDU_END' + + Set to zero if the TLV is not included + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 + + +/* Description RESERVED_7A + + Spare space in case the widths of the above offsets grow +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 + + +/* Description RESERVED_8A + + Spare space in case the widths of the above offsets grow + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + Spare space in case the widths of the above offsets grow + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description CORRUPTED_DUE_TO_FIFO_DELAY + + Set if Rx PCU avoided a hang due to SFM delays by writing + a corrupted 'RX_PPDU_END_USER_STATS' and/or 'RX_PPDU_END.' + +*/ + +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 + + +/* Description QOS_SN_1_MORE_FRAG_STATE + + Field only valid when QoS_SN_1_info_valid is set. + + The 'more fragments' state of the QoS frames with TID QoS_SN_1_TID + at the end of this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 + + +/* Description QOS_SN_1_FRAG_NUM_STATE + + Field only valid when QoS_SN_1_info_valid is set. + + The 'fragment number' state of the QoS frames with TID QoS_SN_1_TID + at the end of this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c + + +/* Description QOS_SN_2_MORE_FRAG_STATE + + Field only valid when QoS_SN_2_info_valid is set. + + The 'more fragments' state of the QoS frames with TID QoS_SN_2_TID + at the end of this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 + + +/* Description QOS_SN_2_FRAG_NUM_STATE + + Field only valid when QoS_SN_2_info_valid is set. + + The 'fragment number' state of the QoS frames with TID QoS_SN_2_TID + at the end of this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 + + +/* Description RESERVED_26A + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_26A_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_RESERVED_26A_LSB 11 +#define RXPCU_PPDU_END_INFO_RESERVED_26A_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_26A_MASK 0x00000000fffff800 + + +/* Description RX_PPDU_END_MARKER + + Field used by SW to double check that their structure alignment + is in sync with what HW has done. + +*/ + +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 + + + +#endif // RXPCU_PPDU_END_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/rxpcu_ppdu_end_layout_info.h b/drivers/staging/fw-api/hw/qcn6432/rxpcu_ppdu_end_layout_info.h new file mode 100644 index 0000000000000000000000000000000000000000..49ab1ee408862f4120c064b87fdaa3a130d80d03 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rxpcu_ppdu_end_layout_info.h @@ -0,0 +1,679 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ +#define _RXPCU_PPDU_END_LAYOUT_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 + + +struct rxpcu_ppdu_end_layout_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_legacy_offset : 2, // [1:0] + l_sig_a_offset : 6, // [7:2] + l_sig_b_offset : 6, // [13:8] + ht_sig_offset : 6, // [19:14] + vht_sig_a_offset : 6, // [25:20] + repeat_l_sig_a_offset : 6; // [31:26] + uint32_t he_sig_a_su_offset : 6, // [5:0] + he_sig_a_mu_dl_offset : 6, // [11:6] + he_sig_a_mu_ul_offset : 6, // [17:12] + generic_u_sig_offset : 6, // [23:18] + rssi_ht_offset : 7, // [30:24] + reserved_1a : 1; // [31:31] + uint32_t vht_sig_b_su20_offset : 7, // [6:0] + vht_sig_b_su40_offset : 7, // [13:7] + vht_sig_b_su80_offset : 7, // [20:14] + vht_sig_b_su160_offset : 7, // [27:21] + reserved_2a : 4; // [31:28] + uint32_t vht_sig_b_mu20_offset : 7, // [6:0] + vht_sig_b_mu40_offset : 7, // [13:7] + vht_sig_b_mu80_offset : 7, // [20:14] + vht_sig_b_mu160_offset : 7, // [27:21] + reserved_3a : 4; // [31:28] + uint32_t he_sig_b1_mu_offset : 7, // [6:0] + he_sig_b2_mu_offset : 7, // [13:7] + he_sig_b2_ofdma_offset : 7, // [20:14] + first_generic_eht_sig_offset : 7, // [27:21] + multiple_generic_eht_sig_included : 1, // [28:28] + reserved_4a : 3; // [31:29] + uint32_t common_user_info_offset : 7, // [6:0] + first_debug_info_offset : 8, // [14:7] + multiple_debug_info_included : 1, // [15:15] + first_other_receive_info_offset : 8, // [23:16] + multiple_other_receive_info_included : 1, // [24:24] + reserved_5a : 7; // [31:25] + uint32_t data_done_offset : 8, // [7:0] + generated_cbf_details_offset : 8, // [15:8] + pkt_end_part1_offset : 8, // [23:16] + location_offset : 8; // [31:24] + uint32_t az_integrity_data_offset : 8, // [7:0] + pkt_end_offset : 8, // [15:8] + abort_request_ack_offset : 8, // [23:16] + reserved_7a : 8; // [31:24] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] +#else + uint32_t repeat_l_sig_a_offset : 6, // [31:26] + vht_sig_a_offset : 6, // [25:20] + ht_sig_offset : 6, // [19:14] + l_sig_b_offset : 6, // [13:8] + l_sig_a_offset : 6, // [7:2] + rssi_legacy_offset : 2; // [1:0] + uint32_t reserved_1a : 1, // [31:31] + rssi_ht_offset : 7, // [30:24] + generic_u_sig_offset : 6, // [23:18] + he_sig_a_mu_ul_offset : 6, // [17:12] + he_sig_a_mu_dl_offset : 6, // [11:6] + he_sig_a_su_offset : 6; // [5:0] + uint32_t reserved_2a : 4, // [31:28] + vht_sig_b_su160_offset : 7, // [27:21] + vht_sig_b_su80_offset : 7, // [20:14] + vht_sig_b_su40_offset : 7, // [13:7] + vht_sig_b_su20_offset : 7; // [6:0] + uint32_t reserved_3a : 4, // [31:28] + vht_sig_b_mu160_offset : 7, // [27:21] + vht_sig_b_mu80_offset : 7, // [20:14] + vht_sig_b_mu40_offset : 7, // [13:7] + vht_sig_b_mu20_offset : 7; // [6:0] + uint32_t reserved_4a : 3, // [31:29] + multiple_generic_eht_sig_included : 1, // [28:28] + first_generic_eht_sig_offset : 7, // [27:21] + he_sig_b2_ofdma_offset : 7, // [20:14] + he_sig_b2_mu_offset : 7, // [13:7] + he_sig_b1_mu_offset : 7; // [6:0] + uint32_t reserved_5a : 7, // [31:25] + multiple_other_receive_info_included : 1, // [24:24] + first_other_receive_info_offset : 8, // [23:16] + multiple_debug_info_included : 1, // [15:15] + first_debug_info_offset : 8, // [14:7] + common_user_info_offset : 7; // [6:0] + uint32_t location_offset : 8, // [31:24] + pkt_end_part1_offset : 8, // [23:16] + generated_cbf_details_offset : 8, // [15:8] + data_done_offset : 8; // [7:0] + uint32_t reserved_7a : 8, // [31:24] + abort_request_ack_offset : 8, // [23:16] + pkt_end_offset : 8, // [15:8] + az_integrity_data_offset : 8; // [7:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] +#endif +}; + + +/* Description RSSI_LEGACY_OFFSET + + Offset in units of 4 bytes of 'PHYRX_RSSI_LEGACY' within + 'RX_PPDU_END' +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 + + +/* Description L_SIG_A_OFFSET + + Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc + + +/* Description L_SIG_B_OFFSET + + Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 + + +/* Description HT_SIG_OFFSET + + Offset of 'PHYRX_HT_SIG' within 'RX_PPDU_END' Set to zero + if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 + + +/* Description VHT_SIG_A_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_A' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 + + +/* Description REPEAT_L_SIG_A_OFFSET + + Offset in units of 4 bytes of the repeat 'PHYRX_L_SIG_A' (in + HE and EHT cases) within 'RX_PPDU_END' + + Set to zero if the TLV is not included + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 + + +/* Description HE_SIG_A_SU_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_SU' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f + + +/* Description HE_SIG_A_MU_DL_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_DL' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 + + +/* Description HE_SIG_A_MU_UL_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_UL' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 + + +/* Description GENERIC_U_SIG_OFFSET + + Offset in units of 4 bytes of 'PHYRX_GENERIC_U_SIG' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 + + +/* Description RSSI_HT_OFFSET + + Offset in units of 4 bytes of 'PHYRX_RSSI_HT' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 + + +/* Description RESERVED_1A + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 + + +/* Description VHT_SIG_B_SU20_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU20' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f + + +/* Description VHT_SIG_B_SU40_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU40' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 + + +/* Description VHT_SIG_B_SU80_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU80' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 + + +/* Description VHT_SIG_B_SU160_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU160' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 + + +/* Description RESERVED_2A + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 + + +/* Description VHT_SIG_B_MU20_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU20' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f + + +/* Description VHT_SIG_B_MU40_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU40' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 + + +/* Description VHT_SIG_B_MU80_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU80' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 + + +/* Description VHT_SIG_B_MU160_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU160' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 + + +/* Description RESERVED_3A + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 + + +/* Description HE_SIG_B1_MU_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_B1_MU' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f + + +/* Description HE_SIG_B2_MU_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_MU' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 + + +/* Description HE_SIG_B2_OFDMA_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_OFDMA' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 + + +/* Description FIRST_GENERIC_EHT_SIG_OFFSET + + Offset in units of 4 bytes of the first 'PHYRX_GENERIC_EHT_SIG' + within 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 + + +/* Description MULTIPLE_GENERIC_EHT_SIG_INCLUDED + + Set to one if more than one 'PHYRX_GENERIC_EHT_SIG' TLVs + are included in 'RX_PPDU_END,' set to zero otherwise + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 + + +/* Description RESERVED_4A + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 + + +/* Description COMMON_USER_INFO_OFFSET + + Offset in units of 4 bytes of 'PHYRX_COMMON_USER_INFO' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f + + +/* Description FIRST_DEBUG_INFO_OFFSET + + Offset in units of 4 bytes of the first 'PHYRX_DEBUG_INFO' + within 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 + + +/* Description MULTIPLE_DEBUG_INFO_INCLUDED + + Set to one if more than one 'PHYRX_DEBUG_INFO' TLVs are + included in 'RX_PPDU_END,' set to zero otherwise + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 + + +/* Description FIRST_OTHER_RECEIVE_INFO_OFFSET + + Offset in units of 4 bytes of the first 'PHYRX_OTHER_RECEIVE_INFO' + within 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 + + +/* Description MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED + + Set to one if more than one 'PHYRX_OTHER_RECEIVE_INFO' TLVs + are included in 'RX_PPDU_END,' set to zero otherwise +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 + + +/* Description RESERVED_5A + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 + + +/* Description DATA_DONE_OFFSET + + Offset in units of 4 bytes of 'PHYRX_DATA_DONE' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff + + +/* Description GENERATED_CBF_DETAILS_OFFSET + + Offset in units of 4 bytes of 'PHYRX_GENERATED_CBF_DETAILS' + within 'RX_PPDU_END'Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 + + +/* Description PKT_END_PART1_OFFSET + + Offset in units of 4 bytes of 'PHYRX_PKT_END_PART1' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 + + +/* Description LOCATION_OFFSET + + Offset in units of 4 bytes of 'PHYRX_LOCATION' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 + + +/* Description AZ_INTEGRITY_DATA_OFFSET + + Offset in units of 4 bytes of 'PHYRX_11AZ_INTEGRITY_DATA' + within 'RX_PPDU_END' + + Set to zero if the TLV is not included + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff + + +/* Description PKT_END_OFFSET + + Offset in units of 4 bytes of 'PHYRX_PKT_END' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 + + +/* Description ABORT_REQUEST_ACK_OFFSET + + Offset in units of 4 bytes of either 'PHYRX_ABORT_REQUEST' + or 'PHYRX_ABORT_ACK' within 'RX_PPDU_END' + + Set to zero if the TLV is not included + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 + + +/* Description RESERVED_7A + + Spare space in case the widths of the above offsets grow +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 + + +/* Description RESERVED_8A + + Spare space in case the widths of the above offsets grow + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff + + +/* Description RESERVED_9A + + Spare space in case the widths of the above offsets grow + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff + + + +#endif // RXPCU_PPDU_END_LAYOUT_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/rxpt_classify_info.h b/drivers/staging/fw-api/hw/qcn6432/rxpt_classify_info.h new file mode 100644 index 0000000000000000000000000000000000000000..41e8fd858c7f34bf1b13fe4a2c6dbb6f371055c7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/rxpt_classify_info.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RXPT_CLASSIFY_INFO_H_ +#define _RXPT_CLASSIFY_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 + + +struct rxpt_classify_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, // [4:0] + lmac_peer_id_msb : 2, // [6:5] + use_flow_id_toeplitz_clfy : 1, // [7:7] + pkt_selection_fp_ucast_data : 1, // [8:8] + pkt_selection_fp_mcast_data : 1, // [9:9] + pkt_selection_fp_1000 : 1, // [10:10] + rxdma0_source_ring_selection : 3, // [13:11] + rxdma0_destination_ring_selection : 3, // [16:14] + mcast_echo_drop_enable : 1, // [17:17] + wds_learning_detect_en : 1, // [18:18] + intrabss_check_en : 1, // [19:19] + use_ppe : 1, // [20:20] + ppe_routing_enable : 1, // [21:21] + reserved_0b : 10; // [31:22] +#else + uint32_t reserved_0b : 10, // [31:22] + ppe_routing_enable : 1, // [21:21] + use_ppe : 1, // [20:20] + intrabss_check_en : 1, // [19:19] + wds_learning_detect_en : 1, // [18:18] + mcast_echo_drop_enable : 1, // [17:17] + rxdma0_destination_ring_selection : 3, // [16:14] + rxdma0_source_ring_selection : 3, // [13:11] + pkt_selection_fp_1000 : 1, // [10:10] + pkt_selection_fp_mcast_data : 1, // [9:9] + pkt_selection_fp_ucast_data : 1, // [8:8] + use_flow_id_toeplitz_clfy : 1, // [7:7] + lmac_peer_id_msb : 2, // [6:5] + reo_destination_indication : 5; // [4:0] +#endif +}; + + +/* Description REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description LMAC_PEER_ID_MSB + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb + is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, + hash[3:0]} using the chosen Toeplitz hash from Common Parser + if flow search fails. + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb + 's not 2'b00, Rx OLE uses a REO desination indication of + {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz + hash from Common Parser if flow search fails. + +*/ + +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060 + + +/* Description USE_FLOW_ID_TOEPLITZ_CLFY + + Indication to Rx OLE to enable REO destination routing based + on the chosen Toeplitz hash from Common Parser, in case + flow search fails + +*/ + +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + + +/* Description PKT_SELECTION_FP_UCAST_DATA + + Filter pass Unicast data frame (matching rxpcu_filter_pass + and sw_frame_group_Unicast_data) routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + + +/* Description PKT_SELECTION_FP_MCAST_DATA + + Filter pass Multicast data frame (matching rxpcu_filter_pass + and sw_frame_group_Multicast_data) routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + + +/* Description PKT_SELECTION_FP_1000 + + Filter pass BAR frame (matching rxpcu_filter_pass and sw_frame_group_ctrl_1000) + routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400 + + +/* Description RXDMA0_SOURCE_RING_SELECTION + + Field only valid when for the received frame type the corresponding + pkt_selection_fp_... bit is set + + The data buffer for + this frame shall be sourced by sw2rxdma0 buffer source + ring. + The data buffer + for this frame shall be sourced by fw2rxdma buffer source + ring for PMAC0. + The data buffer for + this frame shall be sourced by sw2rxdma1 buffer source + ring. + The frame shall not be written + to any data buffer. + The data buffer + for this frame shall be sourced by sw2rxdma_exception buffer + source ring. + The data buffer + for this frame shall be sourced by fw2rxdma buffer source + ring for PMAC1. + + +*/ + +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + + +/* Description RXDMA0_DESTINATION_RING_SELECTION + + Field only valid when for the received frame type the corresponding + pkt_selection_fp_... bit is set + + RXDMA0 shall push the frame + to the Release ring. Effectively this means the frame needs + to be dropped. + RXDMA0 shall push the frame + to the FW ring for PMAC0. + RXDMA0 shall push the frame to the + SW ring. + RXDMA0 shall push the frame to + the REO entrance ring. + RXDMA0 shall push the frame + to the FW ring for PMAC1. + RXDMA0 shall push the frame + to the first MLO REO entrance ring. + RXDMA0 shall push the frame + to the second MLO REO entrance ring. + + +*/ + +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + + +/* Description MCAST_ECHO_DROP_ENABLE + + If set, for multicast packets, multicast echo check (i.e. + SA search with mcast_echo_check = 1) shall be performed + by RXOLE, and any multicast echo packets should be indicated + to RXDMA for release to WBM + + +*/ + +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + + +/* Description WDS_LEARNING_DETECT_EN + + If set, WDS learning detection based on SA search and notification + to FW (using RXDMA0 status ring) is enabled and the "timestamp" + field in address search failure cache-only entry should + be used to avoid multiple WDS learning notifications. + + +*/ + +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + + +/* Description INTRABSS_CHECK_EN + + If set, intra-BSS routing detection is enabled + + +*/ + +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000 + + +/* Description USE_PPE + + Indicates to RXDMA to ignore the REO_destination_indication + and use a programmed value corresponding to the REO2PPE + ring + + This override to REO2PPE for packets requiring multiple + buffers shall be disabled based on an RXDMA configuration, + as PPE may not support such packets. + + +*/ + +#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000 + + +/* Description PPE_ROUTING_ENABLE + + Global enable/disable bit for routing to PPE, used to disable + PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE' + + + This is set by SW for peers which are being handled by a + host SW/accelerator subsystem that also handles packet + buffer management for WiFi-to-PPE routing. + + This is cleared by SW for peers which are being handled + by a different subsystem, completely disabling WiFi-to-PPE + routing for such peers. + + +*/ + +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000 + + +/* Description RESERVED_0B + + +*/ + +#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 22 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xffc00000 + + + +#endif // RXPT_CLASSIFY_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/seq_hwio.h b/drivers/staging/fw-api/hw/qcn6432/seq_hwio.h new file mode 100644 index 0000000000000000000000000000000000000000..2bc27c246ee4cc0c6da1ff490c1861c1ff9b02f5 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/seq_hwio.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __SEQ_H__ +#define __SEQ_H__ + +#include "HALhwio.h" + + + +/**** Register Ref Read ****/ +#define SEQ_INH(base, regtype, reg) \ + SEQ_##regtype##_INH(base, reg) + +/**** Masked Register Read ****/ +#define SEQ_INMH(base, regtype, reg, mask) \ + SEQ_##regtype##_INMH(base, reg, mask) + + +/**** Ref Reg Field Read ****/ +#define SEQ_INFH(base, regtype, reg, fld) \ + (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) + + +/**** Ref Register Write ****/ +#define SEQ_OUTH(base, regtype, reg, val) \ + SEQ_##regtype##_OUTH(base, reg, val) + +/**** Ref Register Masked Write ****/ +#define SEQ_OUTMH(base, regtype, reg, mask, val) \ + SEQ_##regtype##_OUTMH(base, reg, mask, val) + + +/**** Ref Register Field Write ****/ +#define SEQ_OUTFH(base, regtype, reg, fld, val) \ + SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) + + +/**** seq_msg() **** + +typedef enum { + DEBUG, + INFO, + WARNING, + ERROR, + FATAL +} SeverityLevel ; + +void seq_msg(SeverityLevel severity, unsigned int msg_id, const char *format_str, ... ); + +*/ + +/************ seq_wait() ************/ + +typedef enum { + SEC, + MS, + US, + NS +} SEQ_TimeUnit; + +extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); + + +/************ seq_poll() ************/ +extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); + +#endif /* __SEQ_H__ */ + + + + + + + + + + + + + + + + + + + diff --git a/drivers/staging/fw-api/hw/qcn6432/service_info.h b/drivers/staging/fw-api/hw/qcn6432/service_info.h new file mode 100644 index 0000000000000000000000000000000000000000..44d70f5ccd29094a84f36350580648919f39a601 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/service_info.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _SERVICE_INFO_H_ +#define _SERVICE_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_SERVICE_INFO 1 + + +struct service_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t scrambler_seed : 7, // [6:0] + reserved : 1, // [7:7] + sig_b_crc_user : 8, // [15:8] + reserved_1 : 16; // [31:16] +#else + uint32_t reserved_1 : 16, // [31:16] + sig_b_crc_user : 8, // [15:8] + reserved : 1, // [7:7] + scrambler_seed : 7; // [6:0] +#endif +}; + + +/* Description SCRAMBLER_SEED + + This field provides the 7-bit seed for the data scrambler. + +*/ + +#define SERVICE_INFO_SCRAMBLER_SEED_OFFSET 0x00000000 +#define SERVICE_INFO_SCRAMBLER_SEED_LSB 0 +#define SERVICE_INFO_SCRAMBLER_SEED_MSB 6 +#define SERVICE_INFO_SCRAMBLER_SEED_MASK 0x0000007f + + +/* Description RESERVED + + Reserved. Set to 0 by sender and ignored by receiver. +*/ + +#define SERVICE_INFO_RESERVED_OFFSET 0x00000000 +#define SERVICE_INFO_RESERVED_LSB 7 +#define SERVICE_INFO_RESERVED_MSB 7 +#define SERVICE_INFO_RESERVED_MASK 0x00000080 + + +/* Description SIG_B_CRC_USER + + In case of vht transmission: vht_sig_b_crc_user + +*/ + +#define SERVICE_INFO_SIG_B_CRC_USER_OFFSET 0x00000000 +#define SERVICE_INFO_SIG_B_CRC_USER_LSB 8 +#define SERVICE_INFO_SIG_B_CRC_USER_MSB 15 +#define SERVICE_INFO_SIG_B_CRC_USER_MASK 0x0000ff00 + + +/* Description RESERVED_1 + + +*/ + +#define SERVICE_INFO_RESERVED_1_OFFSET 0x00000000 +#define SERVICE_INFO_RESERVED_1_LSB 16 +#define SERVICE_INFO_RESERVED_1_MSB 31 +#define SERVICE_INFO_RESERVED_1_MASK 0xffff0000 + + + +#endif // SERVICE_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/sw_monitor_ring.h b/drivers/staging/fw-api/hw/qcn6432/sw_monitor_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..5660d9a9d770f0e3df82cf3f9bc1799237d7eb9b --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/sw_monitor_ring.h @@ -0,0 +1,746 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _SW_MONITOR_RING_H_ +#define _SW_MONITOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_details.h" +#define NUM_OF_DWORDS_SW_MONITOR_RING 8 + + +struct sw_monitor_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_details reo_level_mpdu_frame_info; + struct buffer_addr_info status_buff_addr_info; + uint32_t rxdma_push_reason : 2, // [1:0] + rxdma_error_code : 5, // [6:2] + mpdu_fragment_number : 4, // [10:7] + frameless_bar : 1, // [11:11] + status_buf_count : 4, // [15:12] + end_of_ppdu : 1, // [16:16] + reserved_6a : 15; // [31:17] + uint32_t phy_ppdu_id : 16, // [15:0] + reserved_7a : 4, // [19:16] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + struct rx_mpdu_details reo_level_mpdu_frame_info; + struct buffer_addr_info status_buff_addr_info; + uint32_t reserved_6a : 15, // [31:17] + end_of_ppdu : 1, // [16:16] + status_buf_count : 4, // [15:12] + frameless_bar : 1, // [11:11] + mpdu_fragment_number : 4, // [10:7] + rxdma_error_code : 5, // [6:2] + rxdma_push_reason : 2; // [1:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reserved_7a : 4, // [19:16] + phy_ppdu_id : 16; // [15:0] +#endif +}; + + +/* Description REO_LEVEL_MPDU_FRAME_INFO + + Consumer: SW + Producer: RXDMA + + Details related to the MPDU being pushed to SW, valid only + if end_of_ppdu is set to 0 +*/ + + +/* Description MSDU_LINK_DESC_ADDR_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Details of the physical address of the MSDU link descriptor + that contains pointers to MSDUs related to this MPDU +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MPDU_DESC_INFO_DETAILS + + Consumer: REO/SW/FW + Producer: RXDMA + + General information related to the MPDU that should be passed + on from REO entrance ring to the REO destination ring +*/ + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + +/* Description STATUS_BUFF_ADDR_INFO + + Consumer: SW + Producer: RXDMA + + Details of the physical address of the first status buffer + used for the PPDU (either the PPDU that included the MPDU + being pushed to SW if end_of_ppdu = 0, or the PPDU whose + end is indicated through end_of_ppdu = 1) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RXDMA_PUSH_REASON + + Indicates why RXDMA pushed the frame to this ring + + RXDMA detected an error an + pushed this frame to this queue + RXDMA pushed the frame + to this queue per received routing instructions. No error + within RXDMA was detected + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" + set, but instead WBM might just see a NULL pointer in the + MSDU link descriptor. This is to be considered a normal + condition for this scenario. + + +*/ + +#define SW_MONITOR_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define SW_MONITOR_RING_RXDMA_PUSH_REASON_LSB 0 +#define SW_MONITOR_RING_RXDMA_PUSH_REASON_MSB 1 +#define SW_MONITOR_RING_RXDMA_PUSH_REASON_MASK 0x00000003 + + +#define SW_MONITOR_RING_RXDMA_ERROR_CODE_LSB 2 +#define SW_MONITOR_RING_RXDMA_ERROR_CODE_MSB 6 +#define SW_MONITOR_RING_RXDMA_ERROR_CODE_MASK 0x0000007c + + +/* Description MPDU_FRAGMENT_NUMBER + + Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.Fragment_flag + is set and end_of_ppdu is set to 0. + + The fragment number from the 802.11 header. + + Note that the sequence number is embedded in the field: + Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. Mpdu_sequence_number + + + +*/ + +#define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_LSB 7 +#define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_MSB 10 +#define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + + +/* Description FRAMELESS_BAR + + When set, this SW monitor ring struct contains BAR info + from a multi TID BAR frame. The original multi TID BAR frame + itself contained all the REO info for the first TID, but + all the subsequent TID info and their linkage to the REO + descriptors is passed down as 'frameless' BAR info. + + The only fields valid in this descriptor when this bit is + within the + Reo_level_mpdu_frame_info: + Within Rx_mpdu_desc_info_details: + Mpdu_Sequence_number + BAR_frame + Peer_meta_data + All other fields shall be set to 0. + + +*/ + +#define SW_MONITOR_RING_FRAMELESS_BAR_OFFSET 0x00000018 +#define SW_MONITOR_RING_FRAMELESS_BAR_LSB 11 +#define SW_MONITOR_RING_FRAMELESS_BAR_MSB 11 +#define SW_MONITOR_RING_FRAMELESS_BAR_MASK 0x00000800 + + +/* Description STATUS_BUF_COUNT + + A count of status buffers used so far for the PPDU (either + the PPDU that included the MPDU being pushed to SW if end_of_ppdu + = 0, or the PPDU whose end is indicated through end_of_ppdu + = 1) +*/ + +#define SW_MONITOR_RING_STATUS_BUF_COUNT_OFFSET 0x00000018 +#define SW_MONITOR_RING_STATUS_BUF_COUNT_LSB 12 +#define SW_MONITOR_RING_STATUS_BUF_COUNT_MSB 15 +#define SW_MONITOR_RING_STATUS_BUF_COUNT_MASK 0x0000f000 + + +/* Description END_OF_PPDU + + RXDMA can be configured to generate a separate 'SW_MONITOR_RING' + descriptor at the end of a PPDU (either through an 'RX_PPDU_END' + TLV or through an 'RX_FLUSH') to demarcate PPDUs. + + For such a descriptor, this bit is set to 1 and fields Reo_level_mpdu_frame_info, + mpdu_fragment_number and Frameless_bar are all set to 0. + + + Otherwise this bit is set to 0. +*/ + +#define SW_MONITOR_RING_END_OF_PPDU_OFFSET 0x00000018 +#define SW_MONITOR_RING_END_OF_PPDU_LSB 16 +#define SW_MONITOR_RING_END_OF_PPDU_MSB 16 +#define SW_MONITOR_RING_END_OF_PPDU_MASK 0x00010000 + + +/* Description RESERVED_6A + + +*/ + +#define SW_MONITOR_RING_RESERVED_6A_OFFSET 0x00000018 +#define SW_MONITOR_RING_RESERVED_6A_LSB 17 +#define SW_MONITOR_RING_RESERVED_6A_MSB 31 +#define SW_MONITOR_RING_RESERVED_6A_MASK 0xfffe0000 + + +/* Description PHY_PPDU_ID + + A PPDU counter value that PHY increments for every PPDU + received + The counter value wraps around. RXDMA can be configured + to copy this from the RX_PPDU_START TLV for every output + descriptor. + + +*/ + +#define SW_MONITOR_RING_PHY_PPDU_ID_OFFSET 0x0000001c +#define SW_MONITOR_RING_PHY_PPDU_ID_LSB 0 +#define SW_MONITOR_RING_PHY_PPDU_ID_MSB 15 +#define SW_MONITOR_RING_PHY_PPDU_ID_MASK 0x0000ffff + + +/* Description RESERVED_7A + + +*/ + +#define SW_MONITOR_RING_RESERVED_7A_OFFSET 0x0000001c +#define SW_MONITOR_RING_RESERVED_7A_LSB 16 +#define SW_MONITOR_RING_RESERVED_7A_MSB 19 +#define SW_MONITOR_RING_RESERVED_7A_MASK 0x000f0000 + + +/* Description RING_ID + + Consumer: SW/REO/DEBUG + Producer: SRNG (of RXDMA) + + For debugging. + This field is filled in by the SRNG module. + It help to identify the ring that is being looked +*/ + +#define SW_MONITOR_RING_RING_ID_OFFSET 0x0000001c +#define SW_MONITOR_RING_RING_ID_LSB 20 +#define SW_MONITOR_RING_RING_ID_MSB 27 +#define SW_MONITOR_RING_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: SW/REO/DEBUG + Producer: SRNG (of RXDMA) + + For debugging. + This field is filled in by the SRNG module. + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define SW_MONITOR_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define SW_MONITOR_RING_LOOPING_COUNT_LSB 28 +#define SW_MONITOR_RING_LOOPING_COUNT_MSB 31 +#define SW_MONITOR_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // SW_MONITOR_RING diff --git a/drivers/staging/fw-api/hw/qcn6432/tcl_data_cmd.h b/drivers/staging/fw-api/hw/qcn6432/tcl_data_cmd.h new file mode 100644 index 0000000000000000000000000000000000000000..e1478926cb4c2b5b5412a533adf2485c64a17cfe --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tcl_data_cmd.h @@ -0,0 +1,793 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TCL_DATA_CMD_H_ +#define _TCL_DATA_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_TCL_DATA_CMD 8 + + +struct tcl_data_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; + uint32_t tcl_cmd_type : 1, // [0:0] + buf_or_ext_desc_type : 1, // [1:1] + bank_id : 6, // [7:2] + tx_notify_frame : 3, // [10:8] + header_length_read_sel : 1, // [11:11] + buffer_timestamp : 19, // [30:12] + buffer_timestamp_valid : 1; // [31:31] + uint32_t reserved_3a : 16, // [15:0] + tcl_cmd_number : 16; // [31:16] + uint32_t data_length : 16, // [15:0] + ipv4_checksum_en : 1, // [16:16] + udp_over_ipv4_checksum_en : 1, // [17:17] + udp_over_ipv6_checksum_en : 1, // [18:18] + tcp_over_ipv4_checksum_en : 1, // [19:19] + tcp_over_ipv6_checksum_en : 1, // [20:20] + to_fw : 1, // [21:21] + reserved_4a : 1, // [22:22] + packet_offset : 9; // [31:23] + uint32_t hlos_tid_overwrite : 1, // [0:0] + flow_override_enable : 1, // [1:1] + who_classify_info_sel : 2, // [3:2] + hlos_tid : 4, // [7:4] + flow_override : 1, // [8:8] + pmac_id : 2, // [10:9] + msdu_color : 2, // [12:11] + reserved_5a : 11, // [23:13] + vdev_id : 8; // [31:24] + uint32_t search_index : 20, // [19:0] + cache_set_num : 4, // [23:20] + index_lookup_override : 1, // [24:24] + reserved_6a : 7; // [31:25] + uint32_t reserved_7a : 20, // [19:0] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + struct buffer_addr_info buf_addr_info; + uint32_t buffer_timestamp_valid : 1, // [31:31] + buffer_timestamp : 19, // [30:12] + header_length_read_sel : 1, // [11:11] + tx_notify_frame : 3, // [10:8] + bank_id : 6, // [7:2] + buf_or_ext_desc_type : 1, // [1:1] + tcl_cmd_type : 1; // [0:0] + uint32_t tcl_cmd_number : 16, // [31:16] + reserved_3a : 16; // [15:0] + uint32_t packet_offset : 9, // [31:23] + reserved_4a : 1, // [22:22] + to_fw : 1, // [21:21] + tcp_over_ipv6_checksum_en : 1, // [20:20] + tcp_over_ipv4_checksum_en : 1, // [19:19] + udp_over_ipv6_checksum_en : 1, // [18:18] + udp_over_ipv4_checksum_en : 1, // [17:17] + ipv4_checksum_en : 1, // [16:16] + data_length : 16; // [15:0] + uint32_t vdev_id : 8, // [31:24] + reserved_5a : 11, // [23:13] + msdu_color : 2, // [12:11] + pmac_id : 2, // [10:9] + flow_override : 1, // [8:8] + hlos_tid : 4, // [7:4] + who_classify_info_sel : 2, // [3:2] + flow_override_enable : 1, // [1:1] + hlos_tid_overwrite : 1; // [0:0] + uint32_t reserved_6a : 7, // [31:25] + index_lookup_override : 1, // [24:24] + cache_set_num : 4, // [23:20] + search_index : 20; // [19:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reserved_7a : 20; // [19:0] +#endif +}; + + +/* Description BUF_ADDR_INFO + + Details of the physical address for a single buffer containing + the entire MSDU or an MSDU extension descriptor. + It also contains return ownership info as well as some meta + data for SW related to this buffer. + + In case of Buf_or_ext_desc_type indicating 'MSDU_buffer', + this address indicates the start of the meta data that is + preceding the actual packet data. + The start of the actual packet data is provided by field: + Packet_offset +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description TCL_CMD_TYPE + + This field is used to select the type of TCL Command decriptor + that is queued by SW/FW. For 'TCL_DATA_CMD' this has to + be 0. + +*/ + +#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001 + + +/* Description BUF_OR_EXT_DESC_TYPE + + The address points to an MSDU buffer. + + The address points to an MSDU + link extension descriptor + < legal all> +*/ + +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002 + + +/* Description BANK_ID + + This is used to select one of the TCL register banks for + fields removed from 'TCL_DATA_CMD' that do not change often + within one virtual device or a set of virtual devices: + EPD + encap_type + Encrypt_type + src_buffer_swap + Link_meta_swap + Search_type + AddrX_en + AddrY_en + DSCP_TID_TABLE_NUM + mesh_enable +*/ + +#define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BANK_ID_LSB 2 +#define TCL_DATA_CMD_BANK_ID_MSB 7 +#define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc + + +/* Description TX_NOTIFY_FRAME + + TCL copies this value to 'TQM_ENTRANCE_RING' field FW_tx_notify_frame. + + Note: TCL can also have CCE/LCE rules to set 'Tx_notify_frame.' + TCL shall have a register to choose the notify type in case + of a conflict between the two settings. +*/ + +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700 + + +/* Description HEADER_LENGTH_READ_SEL + + This field is used to select the per 'encap_type' register + set for MSDU header read length. + 0: set 0 header read length register + 1: set 1 header read length register + +*/ + +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800 + + +/* Description BUFFER_TIMESTAMP + + Field only valid when 'Buffer_timestamp_valid ' is set. + + Frame system entrance timestamp. The timestamp is related + to the global system timer + + Generally the first module (SW, TCL or TQM). that sees this + frame and this timestamp field is not valid, shall fill + in this field. + + Timestamp in units determined by the UMCMN 'TX_TIMESTAMP_RESOLUTION_SELECT' + register + +*/ + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000 + + +/* Description BUFFER_TIMESTAMP_VALID + + When set, the Buffer_timestamp field contains valid info. + +*/ + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000 + + +/* Description RESERVED_3A + + +*/ + +#define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c +#define TCL_DATA_CMD_RESERVED_3A_LSB 0 +#define TCL_DATA_CMD_RESERVED_3A_MSB 15 +#define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff + + +/* Description TCL_CMD_NUMBER + + This number can be used by SW to track, identify and link + the created commands with the command statuses + + Is set to the value 'TCL_CMD_Number' of the related TCL_DATA + command + +*/ + +#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c +#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000 + + +/* Description DATA_LENGTH + + Valid Data length in bytes. + + MSDU length in case of direct descriptor. + Length of link extension descriptor in case of Link extension + descriptor. This is used to know the size of Metadata. + +*/ + +#define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010 +#define TCL_DATA_CMD_DATA_LENGTH_LSB 0 +#define TCL_DATA_CMD_DATA_LENGTH_MSB 15 +#define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff + + +/* Description IPV4_CHECKSUM_EN + + OLE related control + Enable IPv4 checksum replacement +*/ + +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000 + + +/* Description UDP_OVER_IPV4_CHECKSUM_EN + + OLE related control + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. +*/ + +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 + + +/* Description UDP_OVER_IPV6_CHECKSUM_EN + + OLE related control + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. +*/ + +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 + + +/* Description TCP_OVER_IPV4_CHECKSUM_EN + + OLE related control + Enable TCP checksum over IPv4 replacement +*/ + +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 + + +/* Description TCP_OVER_IPV6_CHECKSUM_EN + + OLE related control + Enable TCP checksum over IPv6 replacement +*/ + +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 + + +/* Description TO_FW + + Forward packet to FW along with classification result. The + packet will not be forward to TQM when this bit is set + + 1'b0: Use classification result to forward the packet. + 1'b1: Override classification result and forward packet + only to FW. + +*/ + +#define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010 +#define TCL_DATA_CMD_TO_FW_LSB 21 +#define TCL_DATA_CMD_TO_FW_MSB 21 +#define TCL_DATA_CMD_TO_FW_MASK 0x00200000 + + +/* Description RESERVED_4A + + +*/ + +#define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010 +#define TCL_DATA_CMD_RESERVED_4A_LSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000 + + +/* Description PACKET_OFFSET + + Packet offset from Metadata in case of direct buffer descriptor. + This field is valid when Buf_or_ext_desc_type is reset(= + 0). + +*/ + +#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010 +#define TCL_DATA_CMD_PACKET_OFFSET_LSB 23 +#define TCL_DATA_CMD_PACKET_OFFSET_MSB 31 +#define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000 + + +/* Description HLOS_TID_OVERWRITE + + When set, TCL shall ignore the IP DSCP and VLAN PCP fields + and use HLOS_TID as the final TID. Otherwise TCL shall + consider the DSCP and PCP fields as well as HLOS_TID and + choose a final TID based on the configured priority + +*/ + +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001 + + +/* Description FLOW_OVERRIDE_ENABLE + + TCL uses this to select the flow pointer from the peer table, + which can be overridden by SW for pre-encrypted raw WiFi + packets that cannot be parsed for UDP or for other MLO + or enterprise use cases: + Use the flow-pointer based on parsing + the IPv4 or IPv6 header. + Use the who_classify_info_sel and + flow_override fields to select the flow-pointer. + +*/ + +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002 + + +/* Description WHO_CLASSIFY_INFO_SEL + + Field only valid when flow_override_enable is set to FP_USE_OVERRIDE. + + + This field is used to select one of the 'WHO_CLASSIFY_INFO's + in the peer table in case more than 2 flows are mapped + to a single TID. + 0: To choose Flow 0 and 1 of any TID use this value. + 1: To choose Flow 2 and 3 of any TID use this value. + 2: To choose Flow 4 and 5 of any TID use this value. + 3: To choose Flow 6 and 7 of any TID use this value. + + If who_classify_info sel is not in sync with the num_tx_classify_info + field from address search, then TCL will set 'who_classify_info_sel' + to 0 use flows 0 and 1. + +*/ + +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c + + +/* Description HLOS_TID + + HLOS MSDU priority + + Field is used when HLOS_TID_overwrite is set or flow_override_enable + is set to FP_USE_OVERRIDE. + + Field is also used when HLOS_TID_overwrite is not set and + DSCP/PCP is not available in the packet. + +*/ + +#define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_LSB 4 +#define TCL_DATA_CMD_HLOS_TID_MSB 7 +#define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0 + + +/* Description FLOW_OVERRIDE + + Field only valid when flow_override_enable is set to FP_USE_OVERRIDE. + + + TCL uses this to select the flow pointer from the peer table, + which can be overridden by SW for pre-encrypted raw WiFi + packets that cannot be parsed for UDP or for other MLO + or enterprise use cases: + Use the non-UDP flow pointer (flow + 0) + Use the UDP flow pointer (flow 1) + + +*/ + +#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100 + + +/* Description PMAC_ID + + TCL uses this PMAC_ID in address search, i.e, while finding + matching entry for the packet in AST corresponding to given + PMAC_ID + If PMAC ID is all 1s (=> value 3), it indicates wildcard + match for any PMAC + +*/ + +#define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_PMAC_ID_LSB 9 +#define TCL_DATA_CMD_PMAC_ID_MSB 10 +#define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600 + + +/* Description MSDU_COLOR + + Consumer: TQM + Producer: SW + + TCL copies this value to 'TQM_ENTRANCE_RING' in the structure + 'TX_MSDU_DETAILS' field msdu_color. + + When set, TQM will check the color and choose the color + based threshold with which it will decide if the MSDU has + to be dropped. + + MSDUs which have no color and TQM + uses legacy drop thresholds for these MSDUs. + + + + +*/ + +#define TCL_DATA_CMD_MSDU_COLOR_OFFSET 0x00000014 +#define TCL_DATA_CMD_MSDU_COLOR_LSB 11 +#define TCL_DATA_CMD_MSDU_COLOR_MSB 12 +#define TCL_DATA_CMD_MSDU_COLOR_MASK 0x00001800 + + +/* Description RESERVED_5A + + +*/ + +#define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_DATA_CMD_RESERVED_5A_LSB 13 +#define TCL_DATA_CMD_RESERVED_5A_MSB 23 +#define TCL_DATA_CMD_RESERVED_5A_MASK 0x00ffe000 + + +/* Description VDEV_ID + + Virtual device ID to check against the address search entry + to avoid security issues from transmitting packets from + an incorrect virtual device + +*/ + +#define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_VDEV_ID_LSB 24 +#define TCL_DATA_CMD_VDEV_ID_MSB 31 +#define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000 + + +/* Description SEARCH_INDEX + + The index that will be used for index based address or flow + search. The field is valid when 'search_type' is 1 or + 2. + +*/ + +#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018 +#define TCL_DATA_CMD_SEARCH_INDEX_LSB 0 +#define TCL_DATA_CMD_SEARCH_INDEX_MSB 19 +#define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff + + +/* Description CACHE_SET_NUM + + Cache set number that should be used to cache the index + based search results, for address and flow search. This + value should be equal to LSB four bits of the hash value + of match data, in case of search index points to an entry + which may be used in content based search also. The value + can be anything when the entry pointed by search index + will not be used for content based search. + +*/ + +#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018 +#define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20 +#define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23 +#define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000 + + +/* Description INDEX_LOOKUP_OVERRIDE + + When set, address search and packet routing is forced to + use 'search_index' instead of following the register configuration + seleced by Bank_id. + +*/ + +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000 + + +/* Description RESERVED_6A + + +*/ + +#define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_DATA_CMD_RESERVED_6A_LSB 25 +#define TCL_DATA_CMD_RESERVED_6A_MSB 31 +#define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000 + + +/* Description RESERVED_7A + + +*/ + +#define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_DATA_CMD_RESERVED_7A_LSB 0 +#define TCL_DATA_CMD_RESERVED_7A_MSB 19 +#define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff + + +/* Description RING_ID + + The buffer pointer ring ID. + 0 refers to the IDLE ring + 1 - N refers to other rings + + Helps with debugging when dumping ring contents. + +*/ + +#define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_DATA_CMD_RING_ID_LSB 20 +#define TCL_DATA_CMD_RING_ID_MSB 27 +#define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into the Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_DATA_CMD_LOOPING_COUNT_LSB 28 +#define TCL_DATA_CMD_LOOPING_COUNT_MSB 31 +#define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // TCL_DATA_CMD diff --git a/drivers/staging/fw-api/hw/qcn6432/tcl_entrance_from_ppe_ring.h b/drivers/staging/fw-api/hw/qcn6432/tcl_entrance_from_ppe_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..4aac1783c0fd107a936deaf82a53ab64ac6fcd80 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tcl_entrance_from_ppe_ring.h @@ -0,0 +1,727 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TCL_ENTRANCE_FROM_PPE_RING_H_ +#define _TCL_ENTRANCE_FROM_PPE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_ENTRANCE_FROM_PPE_RING 8 + + +struct tcl_entrance_from_ppe_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_addr_lo : 32; // [31:0] + uint32_t buffer_addr_hi : 8, // [7:0] + drop_prec : 2, // [9:8] + fake_mac_header : 1, // [10:10] + known_ind : 1, // [11:11] + cpu_code_valid : 1, // [12:12] + tunnel_term_ind : 1, // [13:13] + tunnel_type : 1, // [14:14] + wifi_qos_flag : 1, // [15:15] + service_code : 9, // [24:16] + reserved_1b : 1, // [25:25] + int_pri : 4, // [29:26] + more : 1, // [30:30] + reserved_1a : 1; // [31:31] + uint32_t opaque_lo : 32; // [31:0] + uint32_t opaque_hi : 32; // [31:0] + uint32_t src_info : 16, // [15:0] + dst_info : 16; // [31:16] + uint32_t data_length : 18, // [17:0] + pool_id : 6, // [23:18] + wifi_qos : 8; // [31:24] + uint32_t data_offset : 12, // [11:0] + l4_csum_status : 1, // [12:12] + l3_csum_status : 1, // [13:13] + hash_flag : 2, // [15:14] + hash_value : 16; // [31:16] + uint32_t dscp : 8, // [7:0] + valid_toggle : 1, // [8:8] + pppoe_flag : 1, // [9:9] + svlan_flag : 1, // [10:10] + cvlan_flag : 1, // [11:11] + pid : 4, // [15:12] + l3_offset : 8, // [23:16] + l4_offset : 8; // [31:24] +#else + uint32_t buffer_addr_lo : 32; // [31:0] + uint32_t reserved_1a : 1, // [31:31] + more : 1, // [30:30] + int_pri : 4, // [29:26] + reserved_1b : 1, // [25:25] + service_code : 9, // [24:16] + wifi_qos_flag : 1, // [15:15] + tunnel_type : 1, // [14:14] + tunnel_term_ind : 1, // [13:13] + cpu_code_valid : 1, // [12:12] + known_ind : 1, // [11:11] + fake_mac_header : 1, // [10:10] + drop_prec : 2, // [9:8] + buffer_addr_hi : 8; // [7:0] + uint32_t opaque_lo : 32; // [31:0] + uint32_t opaque_hi : 32; // [31:0] + uint32_t dst_info : 16, // [31:16] + src_info : 16; // [15:0] + uint32_t wifi_qos : 8, // [31:24] + pool_id : 6, // [23:18] + data_length : 18; // [17:0] + uint32_t hash_value : 16, // [31:16] + hash_flag : 2, // [15:14] + l3_csum_status : 1, // [13:13] + l4_csum_status : 1, // [12:12] + data_offset : 12; // [11:0] + uint32_t l4_offset : 8, // [31:24] + l3_offset : 8, // [23:16] + pid : 4, // [15:12] + cvlan_flag : 1, // [11:11] + svlan_flag : 1, // [10:10] + pppoe_flag : 1, // [9:9] + valid_toggle : 1, // [8:8] + dscp : 8; // [7:0] +#endif +}; + + +/* Description BUFFER_ADDR_LO + + Consumer: TCL + Producer: PPE DMA/SW + + Lower 32 bits of the buffer address buffer_addr_31_0. + + This is the address of the starting point of the buffer + directly from the PPE Rx Fill descriptor. TCL needs to calculate + the packet data address based on DATA_OFFSET. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_OFFSET 0x00000000 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MASK 0xffffffff + + +/* Description BUFFER_ADDR_HI + + Consumer: TCL/TXDMA + Producer: PPE DMA/SW + + Higher 8 bits of the buffer address buffer_addr_39_32 (Not + supported PPE but could be supported by PPE in + future). Also see BUFFER_ADDR_LO. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MSB 7 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MASK 0x000000ff + + +/* Description DROP_PREC + + Consumer: TCL/TQM + Producer: Switch Core + + Packet drop precedence + + TCL maps DROP_PREC to field msdu_color in structure + 'TX_MSDU_DETAILS' in 'TQM_ENTRANCE_RING' if the internal + parameter 'DROP_PREC_ENABLE' is set (see field DST_INFO) + and DROP_PREC is set to a legal value. Otherwise msdu_color + is set to MSDU_COLORLESS. + + + + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_LSB 8 +#define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MSB 9 +#define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MASK 0x00000300 + + +/* Description FAKE_MAC_HEADER + + Consumer: SW + Producer: Switch Core + + Indicates the MAC header is fake (Not supported for direct + switch connect) + 0: No fake MAC header + 1: Fake MAC header + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_LSB 10 +#define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MSB 10 +#define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MASK 0x00000400 + + +/* Description KNOWN_IND + + Consumer: TCL + Producer: Switch Core + + Known packet indication + 0: packet is unknown flooding. + 1: packet is forwarded by any known entry. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_LSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MASK 0x00000800 + + +/* Description CPU_CODE_VALID + + Consumer: SW + Producer: Switch Core + + Indicates validity of 'CPU_CODE' (used to indicate the reason + the packet is sent to the CPU) (Not supported for direct + switch connect) + 0: Invalid + 1: Valid + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_LSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MASK 0x00001000 + + +/* Description TUNNEL_TERM_IND + + Consumer: TCL + Producer: Switch Core + + Tunnel termination indication + 0: packet is not decapsulated + 1: packet is decapsulated + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_LSB 13 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MSB 13 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MASK 0x00002000 + + +/* Description TUNNEL_TYPE + + Consumer: TCL + Producer: Switch Core + + Tunnel Type + 0: Layer 2 tunnel + 1: Layer 3 tunnel + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_LSB 14 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MSB 14 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MASK 0x00004000 + + +/* Description WIFI_QOS_FLAG + + Consumer: TCL + Producer: Switch Core + + Wi-Fi QoS Flag + 0: If WIFI_QOS[7] is set, WIFI_QOS[3:1] provides a 3-bit + HLOS_TID value and HLOS_TID_overwrite is enabled, else + there is no overwrite. + 1: WIFI_QOS[5:0] provides a 6-bit "flow pointer override" + value by using: + who_classify_info_sel = WIFI_QOS[5:4], + HLOS_TID = WIFI_QOS[3:1], + flow_override = WIFI_QOS[0], + and HLOS_TID_overwrite and flow_override_enable are set. + + + Also see field INT_PRI for another way to enable HLOS_TID_overwrite. + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_LSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MASK 0x00008000 + + +/* Description SERVICE_CODE + + Consumer: TCL + Producer: Switch Core + + Opaque service code between engines + 0: Indicates the end of service path + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_LSB 16 +#define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MSB 24 +#define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MASK 0x01ff0000 + + +/* Description RESERVED_1B + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_LSB 25 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MSB 25 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MASK 0x02000000 + + +/* Description INT_PRI + + Consumer: TCL + Producer: Switch Core + + Internal/User Priority + + TCL maps INT_PRI to HLOS_TID using an internal mapping + table if the internal parameter 'USE_PPE_INT_PRI_FOR_TID' + is set (see field DST_INFO) and WIFI_QOS_FLAG is unset and + WIFI_QOS[7] is unset. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_LSB 26 +#define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MSB 29 +#define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MASK 0x3c000000 + + +/* Description MORE + + Consumer: TCL + Producer: PPE DMA + + 0: The last segment of packet + 1: More segments to follow, indicating scatter/gather + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_MORE_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_MORE_LSB 30 +#define TCL_ENTRANCE_FROM_PPE_RING_MORE_MSB 30 +#define TCL_ENTRANCE_FROM_PPE_RING_MORE_MASK 0x40000000 + + +/* Description RESERVED_1A + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_LSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MASK 0x80000000 + + +/* Description OPAQUE_LO + + Consumer: TCL/WBM/SW + Producer: PPE DMA/SW + + Lower 32 bits of opaque SW value + + OPAQUE_LO[19:0] are used for Sw_buffer_cookie with OPAQUE_LO[31:20] + ignored, for direct switch connect. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_OFFSET 0x00000008 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MASK 0xffffffff + + +/* Description OPAQUE_HI + + Consumer: SW + Producer: PPE DMA/SW + + Higher 32 bits of opaque SW value, ignored completely for + direct switch connect + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_OFFSET 0x0000000c +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MASK 0xffffffff + + +/* Description SRC_INFO + + Consumer: TCL + Producer: Switch Core + + Source port: SRC_INFO[15:12] = 'b0010, SRC_INFO[11:0] is + the PORT_ID. + See DST_INFO for PORT_ID values. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_OFFSET 0x00000010 +#define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MASK 0x0000ffff + + +/* Description DST_INFO + + Consumer: TCL + Producer: Switch Core + + Destination port or next hop information + + DST_INFO[15:12] = 'b0000 indicates invalid information. + If DST_INFO[15:12] = 'b0001, DST_INFO[11:0] is the next + hop index (Not supported for direct switch connect). + If DST_INFO[15:12] = 'b0010, DST_INFO[11:0] is the PORT_ID, + which TCL can process. + If DST_INFO[15:12] = 'b0011, DST_INFO[11:0] is the destination + port bitmap (Not supported for direct switch connect). + + PORT_ID: + 0-31 indicates a physical Ethernet port. + 32-63 indicates a link aggregation group (LAG) of ports (Not + supported for direct switch connect). + 64-255 indicates a virtual port, which TCL maps + to Bank_id, PMAC_ID, vdev_id, To_FW and Search_index. + TCL also maps this to internal parameters 'USE_PPE_INT_PRI_FOR_TID' + and 'DROP_PREC_ENABLE' (see fields INT_PRI and DROP_PREC). + + Other values are reserved. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_OFFSET 0x00000010 +#define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_LSB 16 +#define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MASK 0xffff0000 + + +/* Description DATA_LENGTH + + Consumer: TCL/TXDMA + Producer: PPE DMA + + Length of valid packet data in the current buffer in bytes + (Bits [17:16] not supported PPE and bits [17:14] + not supported) + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_OFFSET 0x00000014 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MSB 17 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MASK 0x0003ffff + + +/* Description POOL_ID + + Consumer: TCL/SW + Producer: PPE DMA/SW + + To be used for hardware buffer management + + SW must ensure 1:1 mapping between PPE Rx Fill and PPE Rx + completion descriptors. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_OFFSET 0x00000014 +#define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_LSB 18 +#define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MSB 23 +#define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MASK 0x00fc0000 + + +/* Description WIFI_QOS + + Consumer: TCL + Producer: Switch Core + + Wi-Fi QoS Value + + TCL maps as follows: + who_classify_info_sel = WIFI_QOS[5:4] if WIFI_QOS_FLAG set + + HLOS_TID = WIFI_QOS[3:1] if HLOS_TID_overwrite enabled + flow_override = WIFI_QOS [0] if WIFI_QOS_FLAG set + flow_override_enable = WIFI_QOS_FLAG + HLOS_TID_overwrite = WIFI_QOS_FLAG || WIFI_QOS[7] + + WIFI_QOS[6] is ignored by TCL. + + Also see field INT_PRI for another way to enable HLOS_TID_overwrite. + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_OFFSET 0x00000014 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_LSB 24 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MASK 0xff000000 + + +/* Description DATA_OFFSET + + Consumer: TCL + Producer: PPE DMA + + Offset to the packet data from the buffer address + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MASK 0x00000fff + + +/* Description L4_CSUM_STATUS + + Consumer: TCL + Producer: PPE DMA/Switch Core + + Layer 4 checksum verification result + 0: Unknown or invalid + 1: Valid + The default value is 0. Only when PPE DMA performs the checksum + calculation and the result is correct, is this bit set. + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_LSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MASK 0x00001000 + + +/* Description L3_CSUM_STATUS + + Consumer: TCL + Producer: PPE DMA/Switch Core + + Layer 3 checksum verification result + 0: Unknown or invalid + 1: Valid + The default value is 0. Only when PPE DMA performs the checksum + calculation and the result is correct, is this bit set. + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_LSB 13 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MSB 13 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MASK 0x00002000 + + +/* Description HASH_FLAG + + Consumer: SW + Producer: Switch Core + + Hash type + 00: Hash invalid + 01: 5-tuple hash + 10: 3-tuple hash + 11: Reserved + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_LSB 14 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MASK 0x0000c000 + + +/* Description HASH_VALUE + + Consumer: SW + Producer: Switch Core + + Hash value + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_LSB 16 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MASK 0xffff0000 + + +/* Description DSCP + + Consumer: TCL + Producer: PPE DMA/Switch Core + + Differential Services Code Point value + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_DSCP_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_DSCP_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MSB 7 +#define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MASK 0x000000ff + + +/* Description VALID_TOGGLE + + Consumer: TCL + Producer: PPE DMA + + Toggle bit to indicate the validity of the descriptor + The value is toggled when the producer pointer wraps around. + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_LSB 8 +#define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MSB 8 +#define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MASK 0x00000100 + + +/* Description PPPOE_FLAG + + Consumer: TCL + Producer: Switch Core + + Indicates a PPPoE packet + 0: No PPPoE header + 1: PPPoE header exists + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_LSB 9 +#define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MSB 9 +#define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MASK 0x00000200 + + +/* Description SVLAN_FLAG + + Consumer: TCL + Producer: PPE DMA/Switch Core + + Indicates the existence of S-VLAN tag + 0: No S-VLAN + 1: S-VLAN exists, including priority + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_LSB 10 +#define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MSB 10 +#define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MASK 0x00000400 + + +/* Description CVLAN_FLAG + + Consumer: TCL + Producer: PPE DMA/Switch Core + + Indicates the existence of C-VLAN tag + 0: No C-VLAN + 1: C-VLAN exists, including priority + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_LSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MASK 0x00000800 + + +/* Description PID + + Consumer: TCL + Producer: Switch Core + + Protocol ID, indicating the protocol type of the packet + 0: IPv4 (no supported L4) + 1: TCP over IPv4 + 2: UDP over IPv4 + 3: UDP-Lite over IPv4 + 4: IPv6 (no supported L4) + 5: TCP over IPv6 + 6: UDP over IPv6 + 7: UDP-Lite over IPv6 + 8: Non-IP + Other values are reserved + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_PID_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_PID_LSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_PID_MSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_PID_MASK 0x0000f000 + + +/* Description L3_OFFSET + + Consumer: TCL + Producer: PPE DMA + + Layer 3 header offset from DATA_OFFSET + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_LSB 16 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MSB 23 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MASK 0x00ff0000 + + +/* Description L4_OFFSET + + Consumer: TCL + Producer: PPE DMA + + Layer 4 header offset from DATA_OFFSET + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_LSB 24 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MASK 0xff000000 + + + +#endif // TCL_ENTRANCE_FROM_PPE_RING diff --git a/drivers/staging/fw-api/hw/qcn6432/tcl_gse_cmd.h b/drivers/staging/fw-api/hw/qcn6432/tcl_gse_cmd.h new file mode 100644 index 0000000000000000000000000000000000000000..04c4b271a7fb44fc952480b58df2095dd34eaffa --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tcl_gse_cmd.h @@ -0,0 +1,336 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TCL_GSE_CMD_H_ +#define _TCL_GSE_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_GSE_CMD 8 + + +struct tcl_gse_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t control_buffer_addr_31_0 : 32; // [31:0] + uint32_t control_buffer_addr_39_32 : 8, // [7:0] + gse_ctrl : 4, // [11:8] + gse_sel : 1, // [12:12] + status_destination_ring_id : 1, // [13:13] + swap : 1, // [14:14] + index_search_en : 1, // [15:15] + cache_set_num : 4, // [19:16] + reserved_1a : 12; // [31:20] + uint32_t tcl_cmd_type : 1, // [0:0] + reserved_2a : 31; // [31:1] + uint32_t cmd_meta_data_31_0 : 32; // [31:0] + uint32_t cmd_meta_data_63_32 : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 20, // [19:0] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t control_buffer_addr_31_0 : 32; // [31:0] + uint32_t reserved_1a : 12, // [31:20] + cache_set_num : 4, // [19:16] + index_search_en : 1, // [15:15] + swap : 1, // [14:14] + status_destination_ring_id : 1, // [13:13] + gse_sel : 1, // [12:12] + gse_ctrl : 4, // [11:8] + control_buffer_addr_39_32 : 8; // [7:0] + uint32_t reserved_2a : 31, // [31:1] + tcl_cmd_type : 1; // [0:0] + uint32_t cmd_meta_data_31_0 : 32; // [31:0] + uint32_t cmd_meta_data_63_32 : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reserved_7a : 20; // [19:0] +#endif +}; + + +/* Description CONTROL_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of a control buffer containing additional + info needed for this command execution. + +*/ + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description CONTROL_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of a control buffer containing additional + info needed for this command execution. + +*/ + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description GSE_CTRL + + GSE control operations. This includes cache operations and + table entry statistics read/clear operation. + Report or Read statistics + Search disable. Report only Hash + Write Back single entry + Write Back entire cache entry + Invalidate single cache entry + Invalidate entire cache + Write back and Invalidate single + entry in cache + write back and invalidate entire + cache + Clear statistics for single entry + + + Rest of the values reserved. + For all single entry control operations (write back, Invalidate + or both)Statistics will be reported +*/ + +#define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_CTRL_LSB 8 +#define TCL_GSE_CMD_GSE_CTRL_MSB 11 +#define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00 + + +/* Description GSE_SEL + + Bit to select the ASE or FSE to do the operation mention + by GSE_ctrl bit + 0: FSE select + 1: ASE select +*/ + +#define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_SEL_LSB 12 +#define TCL_GSE_CMD_GSE_SEL_MSB 12 +#define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000 + + +/* Description STATUS_DESTINATION_RING_ID + + The TCL status ring to which the GSE status needs to be + send. + + + + + +*/ + +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000 + + +/* Description SWAP + + Bit to enable byte swapping of contents of buffer + + + +*/ + +#define TCL_GSE_CMD_SWAP_OFFSET 0x00000004 +#define TCL_GSE_CMD_SWAP_LSB 14 +#define TCL_GSE_CMD_SWAP_MSB 14 +#define TCL_GSE_CMD_SWAP_MASK 0x00004000 + + +/* Description INDEX_SEARCH_EN + + When this bit is set to 1 control_buffer_addr[19:0] will + be considered as index of the AST or Flow table and GSE + commands will be executed accordingly on the entry pointed + by the index. + This feature is disabled by setting this bit to 0. + + + + +*/ + +#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000 + + +/* Description CACHE_SET_NUM + + Cache set number that should be used to cache the index + based search results, for address and flow search. This + value should be equal to value of cache_set_num for the + index that is issued in TCL_DATA_CMD during search index + based ASE or FSE. This field is valid for index based GSE + commands + +*/ + +#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004 +#define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16 +#define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19 +#define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000 + + +/* Description RESERVED_1A + + +*/ + +#define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004 +#define TCL_GSE_CMD_RESERVED_1A_LSB 20 +#define TCL_GSE_CMD_RESERVED_1A_MSB 31 +#define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000 + + +/* Description TCL_CMD_TYPE + + This field is used to select the type of TCL Command decriptor + that is queued by SW/FW. For 'TCL_GSE_CMD' this has to + be 1. + +*/ + +#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001 + + +/* Description RESERVED_2A + + +*/ + +#define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008 +#define TCL_GSE_CMD_RESERVED_2A_LSB 1 +#define TCL_GSE_CMD_RESERVED_2A_MSB 31 +#define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe + + +/* Description CMD_META_DATA_31_0 + + Meta data to be returned in the status descriptor + +*/ + +#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff + + +/* Description CMD_META_DATA_63_32 + + Meta data to be returned in the status descriptor + +*/ + +#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff + + +/* Description RESERVED_5A + + +*/ + +#define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_GSE_CMD_RESERVED_5A_LSB 0 +#define TCL_GSE_CMD_RESERVED_5A_MSB 31 +#define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff + + +/* Description RESERVED_6A + + +*/ + +#define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_GSE_CMD_RESERVED_6A_LSB 0 +#define TCL_GSE_CMD_RESERVED_6A_MSB 31 +#define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff + + +/* Description RESERVED_7A + + +*/ + +#define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_GSE_CMD_RESERVED_7A_LSB 0 +#define TCL_GSE_CMD_RESERVED_7A_MSB 19 +#define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff + + +/* Description RING_ID + + Helps with debugging when dumping ring contents. + +*/ + +#define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_GSE_CMD_RING_ID_LSB 20 +#define TCL_GSE_CMD_RING_ID_MSB 27 +#define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into the Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_GSE_CMD_LOOPING_COUNT_LSB 28 +#define TCL_GSE_CMD_LOOPING_COUNT_MSB 31 +#define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // TCL_GSE_CMD diff --git a/drivers/staging/fw-api/hw/qcn6432/tcl_status_ring.h b/drivers/staging/fw-api/hw/qcn6432/tcl_status_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..167833f2a869a8b51246ee8df4138f23504de97c --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tcl_status_ring.h @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TCL_STATUS_RING_H_ +#define _TCL_STATUS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_STATUS_RING 8 + + +struct tcl_status_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t gse_ctrl : 4, // [3:0] + ase_fse_sel : 1, // [4:4] + cache_op_res : 2, // [6:5] + index_search_en : 1, // [7:7] + msdu_cnt_n : 24; // [31:8] + uint32_t msdu_byte_cnt_n : 32; // [31:0] + uint32_t msdu_timestmp_n : 32; // [31:0] + uint32_t cmd_meta_data_31_0 : 32; // [31:0] + uint32_t cmd_meta_data_63_32 : 32; // [31:0] + uint32_t hash_indx_val : 20, // [19:0] + cache_set_num : 4, // [23:20] + reserved_5a : 8; // [31:24] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 20, // [19:0] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t msdu_cnt_n : 24, // [31:8] + index_search_en : 1, // [7:7] + cache_op_res : 2, // [6:5] + ase_fse_sel : 1, // [4:4] + gse_ctrl : 4; // [3:0] + uint32_t msdu_byte_cnt_n : 32; // [31:0] + uint32_t msdu_timestmp_n : 32; // [31:0] + uint32_t cmd_meta_data_31_0 : 32; // [31:0] + uint32_t cmd_meta_data_63_32 : 32; // [31:0] + uint32_t reserved_5a : 8, // [31:24] + cache_set_num : 4, // [23:20] + hash_indx_val : 20; // [19:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reserved_7a : 20; // [19:0] +#endif +}; + + +/* Description GSE_CTRL + + GSE control operations. This includes cache operations and + table entry statistics read/clear operation. + Report or Read statistics + Search disable. Report only Hash + Write Back single entry + Write Back entire cache entry + Invalidate single cache entry + Invalidate entire cache + Write back and Invalidate single + entry in cache + write back and invalidate entire + cache + Clear statistics for single entry + + + Rest of the values reserved. + For all single entry control operations (write back, Invalidate + or both)Statistics will be reported +*/ + +#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 +#define TCL_STATUS_RING_GSE_CTRL_LSB 0 +#define TCL_STATUS_RING_GSE_CTRL_MSB 3 +#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f + + +/* Description ASE_FSE_SEL + + Search Engine for which operation is done. + 1'b0: Address Search Engine Result + 1'b1: Flow Search Engine result +*/ + +#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 +#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 + + +/* Description CACHE_OP_RES + + Cache operation result. Following are results of cache operation. + + Operation successful + Entry not found in Table + Timeout Error + +*/ + +#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 +#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 +#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 +#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 + + +/* Description INDEX_SEARCH_EN + + When this bit is set to 1 control_buffer_addr[19:0] will + be considered as index of the AST or Flow table and GSE + commands will be executed accordingly on the entry pointed + by the index. + This feature is disabled by setting this bit to 0. + + + + +*/ + +#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 + + +/* Description MSDU_CNT_N + + MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and + 4'b1000 +*/ + +#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 +#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 +#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 + + +/* Description MSDU_BYTE_CNT_N + + MSDU byte count for entry 1. Valid when GSE_CTRL is 4'b0111 + and 4'b1000 +*/ + +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff + + +/* Description MSDU_TIMESTMP_N + + MSDU timestamp for entry 1. Valid when GSE_CTRL is 4'b0111 + and 4'b1000 +*/ + +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff + + +/* Description CMD_META_DATA_31_0 + + Meta data from input ring + +*/ + +#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff + + +/* Description CMD_META_DATA_63_32 + + Meta data from input ring + +*/ + +#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff + + +/* Description HASH_INDX_VAL + + Index of entry in the table in case of search pass (or) + + Hash value of the entry in table in case of search failed + or search disable. + +*/ + +#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 +#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 +#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 +#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff + + +/* Description CACHE_SET_NUM + + Cache set number copied from TCL_GSE_CMD +*/ + +#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 +#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 +#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 + + +/* Description RESERVED_5A + + +*/ + +#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 +#define TCL_STATUS_RING_RESERVED_5A_LSB 24 +#define TCL_STATUS_RING_RESERVED_5A_MSB 31 +#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 + + +/* Description RESERVED_6A + + +*/ + +#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 +#define TCL_STATUS_RING_RESERVED_6A_LSB 0 +#define TCL_STATUS_RING_RESERVED_6A_MSB 31 +#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff + + +/* Description RESERVED_7A + + +*/ + +#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c +#define TCL_STATUS_RING_RESERVED_7A_LSB 0 +#define TCL_STATUS_RING_RESERVED_7A_MSB 19 +#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff + + +/* Description RING_ID + + The buffer pointer ring ID. + + Helps with debugging when dumping ring contents. + +*/ + +#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c +#define TCL_STATUS_RING_RING_ID_LSB 20 +#define TCL_STATUS_RING_RING_ID_MSB 27 +#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into the Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 +#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 +#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // TCL_STATUS_RING diff --git a/drivers/staging/fw-api/hw/qcn6432/tlv_hdr.h b/drivers/staging/fw-api/hw/qcn6432/tlv_hdr.h new file mode 100644 index 0000000000000000000000000000000000000000..c1dae4b6022928b77e984036374802c062c9cda8 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tlv_hdr.h @@ -0,0 +1,626 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TLV_HDR_H_ +#define _TLV_HDR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define _TLV_USERID_WIDTH_ 6 +#define _TLV_DATA_WIDTH_ 32 +#define _TLV_TAG_WIDTH_ 9 + +#define _TLV_MRV_EN_LEN_WIDTH_ 9 +#define _TLV_MRV_DIS_LEN_WIDTH_ 12 + +#define _TLV_16_DATA_WIDTH_ 16 +#define _TLV_16_TAG_WIDTH_ 5 +#define _TLV_16_LEN_WIDTH_ 4 +#define _TLV_CTAG_WIDTH_ 5 +#define _TLV_44_DATA_WIDTH_ 44 +#define _TLV_64_DATA_WIDTH_ 64 +#define _TLV_76_DATA_WIDTH_ 64 +#define _TLV_CDATA_WIDTH_ 32 +#define _TLV_CDATA_76_WIDTH_ 64 + +struct tlv_usr_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint16_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_reserved : 6; +#else + uint16_t tlv_reserved : 6, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +// ----------------------------------------------------------------- +// TLV 32 onwards support two formats, +// link id based where some bits of length have been re-purposed +// non link id based where legacy length width is available +// ----------------------------------------------------------------- + +struct tlv_mlo_usr_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mlo_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 6; +#else + uint32_t tlv_reserved : 6, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mlo_usr_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_mlo_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; + +struct tlv_mlo_usr_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_reserved : 10, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mlo_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 16, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mlo_usr_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, +#endif + tlv_reserved : 32; + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_mlo_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + tlv_reserved : 32; +#endif + uint64_t pad_64to128_bit : 64; +}; + + + + + + +struct tlv_mac_usr_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 6; +#else + uint32_t tlv_reserved : 6, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_usr_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_mac_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; + +struct tlv_mac_usr_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_reserved : 10, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 16, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_usr_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, +#endif + tlv_reserved : 32; + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_mac_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + tlv_reserved : 32; +#endif + uint64_t pad_64to128_bit : 64; +}; + +// ----------------------------------------------------------------- +// Compressed TLVs do not support the MLO variant +// ----------------------------------------------------------------- + +struct tlv_usr_c_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata : _TLV_CDATA_WIDTH_, + pad_44to64_bit : 20; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_52 : 52; + uint64_t tlv_cdata_upper_12 : 12, + pad_76to128_bit : 52; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + tlv_cdata_middle_32 : 32; + uint64_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12, + pad_96to128_bit : 32; +#endif +}; + + +// ----------------------------------------------------------------- +// !!! For backward compatibility ONLY. !!! +// !!! As per SW request, legacy tlv_32_hdr and tlv_usr_32_hdr !!! +// !!! types are mapped to new 64 bit headers. !!! +// ----------------------------------------------------------------- +struct tlv_usr_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; +// ----------------------------------------------------------------- + +// ----------------------------------------------------------------- +// !!! Tag-length word structures using uint32_t !!! +// !!! For endianness considerations !!! +// !!! 'tlword' is replaced with 'tlw32' !!! +// ----------------------------------------------------------------- + +struct tlv_mlo_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mlo_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +// ----------------------------------------------------------------- +// Compressed TLVs do not support the MLO variant +// ----------------------------------------------------------------- + +struct tlv_usr_c_44_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_upper_12 : 12, + pad_44to64_bit : 20; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t tlv_cdata_upper_12 : 12, + pad_76to96_bit : 20; + uint32_t pad_96to128_bit : 32; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12; + uint32_t pad_96to128_bit : 32; +#endif +}; +// ----------------------------------------------------------------- + + +#endif // _TLV_HDR_H_ diff --git a/drivers/staging/fw-api/hw/qcn6432/tlv_tag_def.h b/drivers/staging/fw-api/hw/qcn6432/tlv_tag_def.h new file mode 100644 index 0000000000000000000000000000000000000000..fe16fb955e00deb96a4e00738833df9f7442c7b1 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tlv_tag_def.h @@ -0,0 +1,508 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TLV_TAG_DEF_ +#define _TLV_TAG_DEF_ + +typedef enum tlv_tag_def{ + WIFIMACTX_CBF_START_E = 0 /* 0x0 */, + WIFIPHYRX_DATA_E = 1 /* 0x1 */, + WIFIPHYRX_CBF_DATA_RESP_E = 2 /* 0x2 */, + WIFIPHYRX_ABORT_REQUEST_E = 3 /* 0x3 */, + WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 /* 0x4 */, + WIFIMACTX_DATA_RESP_E = 5 /* 0x5 */, + WIFIMACTX_CBF_DATA_E = 6 /* 0x6 */, + WIFIMACTX_CBF_DONE_E = 7 /* 0x7 */, + WIFIPHYRX_LMR_DATA_RESP_E = 8 /* 0x8 */, + WIFIRXPCU_TO_UCODE_START_E = 9 /* 0x9 */, + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 /* 0xa */, + WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 /* 0xb */, + WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 /* 0xc */, + WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 /* 0xd */, + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 /* 0xe */, + WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 /* 0xf */, + WIFIRXPCU_TO_UCODE_END_E = 16 /* 0x10 */, + WIFIMACRX_CBF_READ_REQUEST_E = 32 /* 0x20 */, + WIFIMACRX_CBF_DATA_REQUEST_E = 33 /* 0x21 */, + WIFIMACRX_EXPECT_NDP_RECEPTION_E = 34 /* 0x22 */, + WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 35 /* 0x23 */, + WIFIMACRX_NDP_TIMEOUT_E = 36 /* 0x24 */, + WIFIMACRX_ABORT_ACK_E = 37 /* 0x25 */, + WIFIMACRX_REQ_IMPLICIT_FB_E = 38 /* 0x26 */, + WIFIMACRX_CHAIN_MASK_E = 39 /* 0x27 */, + WIFIMACRX_NAP_USER_E = 40 /* 0x28 */, + WIFIMACRX_ABORT_REQUEST_E = 41 /* 0x29 */, + WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 42 /* 0x2a */, + WIFIPHYTX_ABORT_ACK_E = 43 /* 0x2b */, + WIFIPHYTX_ABORT_REQUEST_E = 44 /* 0x2c */, + WIFIPHYTX_PKT_END_E = 45 /* 0x2d */, + WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 46 /* 0x2e */, + WIFIPHYTX_REQUEST_CTRL_INFO_E = 47 /* 0x2f */, + WIFIPHYTX_DATA_REQUEST_E = 48 /* 0x30 */, + WIFIPHYTX_BF_CV_LOADING_DONE_E = 49 /* 0x31 */, + WIFIPHYTX_NAP_ACK_E = 50 /* 0x32 */, + WIFIPHYTX_NAP_DONE_E = 51 /* 0x33 */, + WIFIPHYTX_OFF_ACK_E = 52 /* 0x34 */, + WIFIPHYTX_ON_ACK_E = 53 /* 0x35 */, + WIFIPHYTX_SYNTH_OFF_ACK_E = 54 /* 0x36 */, + WIFIPHYTX_DEBUG16_E = 55 /* 0x37 */, + WIFIMACTX_ABORT_REQUEST_E = 56 /* 0x38 */, + WIFIMACTX_ABORT_ACK_E = 57 /* 0x39 */, + WIFIMACTX_PKT_END_E = 58 /* 0x3a */, + WIFIMACTX_PRE_PHY_DESC_E = 59 /* 0x3b */, + WIFIMACTX_BF_PARAMS_COMMON_E = 60 /* 0x3c */, + WIFIMACTX_BF_PARAMS_PER_USER_E = 61 /* 0x3d */, + WIFIMACTX_PREFETCH_CV_E = 62 /* 0x3e */, + WIFIMACTX_USER_DESC_COMMON_E = 63 /* 0x3f */, + WIFIMACTX_USER_DESC_PER_USER_E = 64 /* 0x40 */, + WIFIEXAMPLE_USER_TLV_16_E = 65 /* 0x41 */, + WIFIEXAMPLE_TLV_16_E = 66 /* 0x42 */, + WIFIMACTX_PHY_OFF_E = 67 /* 0x43 */, + WIFIMACTX_PHY_ON_E = 68 /* 0x44 */, + WIFIMACTX_SYNTH_OFF_E = 69 /* 0x45 */, + WIFIMACTX_EXPECT_CBF_COMMON_E = 70 /* 0x46 */, + WIFIMACTX_EXPECT_CBF_PER_USER_E = 71 /* 0x47 */, + WIFIMACTX_PHY_DESC_E = 72 /* 0x48 */, + WIFIMACTX_L_SIG_A_E = 73 /* 0x49 */, + WIFIMACTX_L_SIG_B_E = 74 /* 0x4a */, + WIFIMACTX_HT_SIG_E = 75 /* 0x4b */, + WIFIMACTX_VHT_SIG_A_E = 76 /* 0x4c */, + WIFIMACTX_VHT_SIG_B_SU20_E = 77 /* 0x4d */, + WIFIMACTX_VHT_SIG_B_SU40_E = 78 /* 0x4e */, + WIFIMACTX_VHT_SIG_B_SU80_E = 79 /* 0x4f */, + WIFIMACTX_VHT_SIG_B_SU160_E = 80 /* 0x50 */, + WIFIMACTX_VHT_SIG_B_MU20_E = 81 /* 0x51 */, + WIFIMACTX_VHT_SIG_B_MU40_E = 82 /* 0x52 */, + WIFIMACTX_VHT_SIG_B_MU80_E = 83 /* 0x53 */, + WIFIMACTX_VHT_SIG_B_MU160_E = 84 /* 0x54 */, + WIFIMACTX_SERVICE_E = 85 /* 0x55 */, + WIFIMACTX_HE_SIG_A_SU_E = 86 /* 0x56 */, + WIFIMACTX_HE_SIG_A_MU_DL_E = 87 /* 0x57 */, + WIFIMACTX_HE_SIG_A_MU_UL_E = 88 /* 0x58 */, + WIFIMACTX_HE_SIG_B1_MU_E = 89 /* 0x59 */, + WIFIMACTX_HE_SIG_B2_MU_E = 90 /* 0x5a */, + WIFIMACTX_HE_SIG_B2_OFDMA_E = 91 /* 0x5b */, + WIFIMACTX_DELETE_CV_E = 92 /* 0x5c */, + WIFIMACTX_MU_UPLINK_COMMON_E = 93 /* 0x5d */, + WIFIMACTX_MU_UPLINK_USER_SETUP_E = 94 /* 0x5e */, + WIFIMACTX_OTHER_TRANSMIT_INFO_E = 95 /* 0x5f */, + WIFIMACTX_PHY_NAP_E = 96 /* 0x60 */, + WIFIMACTX_DEBUG_E = 97 /* 0x61 */, + WIFIPHYRX_ABORT_ACK_E = 98 /* 0x62 */, + WIFIPHYRX_GENERATED_CBF_DETAILS_E = 99 /* 0x63 */, + WIFIPHYRX_RSSI_LEGACY_E = 100 /* 0x64 */, + WIFIPHYRX_RSSI_HT_E = 101 /* 0x65 */, + WIFIPHYRX_USER_INFO_E = 102 /* 0x66 */, + WIFIPHYRX_PKT_END_E = 103 /* 0x67 */, + WIFIPHYRX_DEBUG_E = 104 /* 0x68 */, + WIFIPHYRX_CBF_TRANSFER_DONE_E = 105 /* 0x69 */, + WIFIPHYRX_CBF_TRANSFER_ABORT_E = 106 /* 0x6a */, + WIFIPHYRX_L_SIG_A_E = 107 /* 0x6b */, + WIFIPHYRX_L_SIG_B_E = 108 /* 0x6c */, + WIFIPHYRX_HT_SIG_E = 109 /* 0x6d */, + WIFIPHYRX_VHT_SIG_A_E = 110 /* 0x6e */, + WIFIPHYRX_VHT_SIG_B_SU20_E = 111 /* 0x6f */, + WIFIPHYRX_VHT_SIG_B_SU40_E = 112 /* 0x70 */, + WIFIPHYRX_VHT_SIG_B_SU80_E = 113 /* 0x71 */, + WIFIPHYRX_VHT_SIG_B_SU160_E = 114 /* 0x72 */, + WIFIPHYRX_VHT_SIG_B_MU20_E = 115 /* 0x73 */, + WIFIPHYRX_VHT_SIG_B_MU40_E = 116 /* 0x74 */, + WIFIPHYRX_VHT_SIG_B_MU80_E = 117 /* 0x75 */, + WIFIPHYRX_VHT_SIG_B_MU160_E = 118 /* 0x76 */, + WIFIPHYRX_HE_SIG_A_SU_E = 119 /* 0x77 */, + WIFIPHYRX_HE_SIG_A_MU_DL_E = 120 /* 0x78 */, + WIFIPHYRX_HE_SIG_A_MU_UL_E = 121 /* 0x79 */, + WIFIPHYRX_HE_SIG_B1_MU_E = 122 /* 0x7a */, + WIFIPHYRX_HE_SIG_B2_MU_E = 123 /* 0x7b */, + WIFIPHYRX_HE_SIG_B2_OFDMA_E = 124 /* 0x7c */, + WIFIPHYRX_OTHER_RECEIVE_INFO_E = 125 /* 0x7d */, + WIFIPHYRX_COMMON_USER_INFO_E = 126 /* 0x7e */, + WIFIPHYRX_DATA_DONE_E = 127 /* 0x7f */, + WIFICOEX_TX_REQ_E = 128 /* 0x80 */, + WIFIDUMMY_E = 129 /* 0x81 */, + WIFIEXAMPLE_TLV_32_NAME_E = 130 /* 0x82 */, + WIFIMPDU_LIMIT_E = 131 /* 0x83 */, + WIFINA_LENGTH_END_E = 132 /* 0x84 */, + WIFIOLE_BUF_STATUS_E = 133 /* 0x85 */, + WIFIPCU_PPDU_SETUP_DONE_E = 134 /* 0x86 */, + WIFIPCU_PPDU_SETUP_END_E = 135 /* 0x87 */, + WIFIPCU_PPDU_SETUP_INIT_E = 136 /* 0x88 */, + WIFIPCU_PPDU_SETUP_START_E = 137 /* 0x89 */, + WIFIPDG_FES_SETUP_E = 138 /* 0x8a */, + WIFIPDG_RESPONSE_E = 139 /* 0x8b */, + WIFIPDG_TX_REQ_E = 140 /* 0x8c */, + WIFISCH_WAIT_INSTR_E = 141 /* 0x8d */, + WIFITQM_FLOW_EMPTY_STATUS_E = 143 /* 0x8f */, + WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 144 /* 0x90 */, + WIFITQM_GEN_MPDU_LENGTH_LIST_E = 145 /* 0x91 */, + WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 146 /* 0x92 */, + WIFITQM_GEN_MPDUS_E = 147 /* 0x93 */, + WIFITQM_GEN_MPDUS_STATUS_E = 148 /* 0x94 */, + WIFITQM_REMOVE_MPDU_E = 149 /* 0x95 */, + WIFITQM_REMOVE_MPDU_STATUS_E = 150 /* 0x96 */, + WIFITQM_REMOVE_MSDU_E = 151 /* 0x97 */, + WIFITQM_REMOVE_MSDU_STATUS_E = 152 /* 0x98 */, + WIFITQM_UPDATE_TX_MPDU_COUNT_E = 153 /* 0x99 */, + WIFITQM_WRITE_CMD_E = 154 /* 0x9a */, + WIFIOFDMA_TRIGGER_DETAILS_E = 155 /* 0x9b */, + WIFITX_DATA_E = 156 /* 0x9c */, + WIFITX_FES_SETUP_E = 157 /* 0x9d */, + WIFIRX_PACKET_E = 158 /* 0x9e */, + WIFIEXPECTED_RESPONSE_E = 159 /* 0x9f */, + WIFITX_MPDU_END_E = 160 /* 0xa0 */, + WIFITX_MPDU_START_E = 161 /* 0xa1 */, + WIFITX_MSDU_END_E = 162 /* 0xa2 */, + WIFITX_MSDU_START_E = 163 /* 0xa3 */, + WIFITX_SW_MODE_SETUP_E = 164 /* 0xa4 */, + WIFITXPCU_BUFFER_STATUS_E = 165 /* 0xa5 */, + WIFITXPCU_USER_BUFFER_STATUS_E = 166 /* 0xa6 */, + WIFIDATA_TO_TIME_CONFIG_E = 167 /* 0xa7 */, + WIFIEXAMPLE_USER_TLV_32_E = 168 /* 0xa8 */, + WIFIMPDU_INFO_E = 169 /* 0xa9 */, + WIFIPDG_USER_SETUP_E = 170 /* 0xaa */, + WIFITX_11AH_SETUP_E = 171 /* 0xab */, + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 172 /* 0xac */, + WIFITX_PEER_ENTRY_E = 173 /* 0xad */, + WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 174 /* 0xae */, + WIFIEXAMPLE_USER_TLV_44_E = 175 /* 0xaf */, + WIFITX_FLUSH_E = 176 /* 0xb0 */, + WIFITX_FLUSH_REQ_E = 177 /* 0xb1 */, + WIFITQM_WRITE_CMD_STATUS_E = 178 /* 0xb2 */, + WIFITQM_GET_MPDU_QUEUE_STATS_E = 179 /* 0xb3 */, + WIFITQM_GET_MSDU_FLOW_STATS_E = 180 /* 0xb4 */, + WIFIEXAMPLE_USER_CTLV_44_E = 181 /* 0xb5 */, + WIFITX_FES_STATUS_START_E = 182 /* 0xb6 */, + WIFITX_FES_STATUS_USER_PPDU_E = 183 /* 0xb7 */, + WIFITX_FES_STATUS_USER_RESPONSE_E = 184 /* 0xb8 */, + WIFITX_FES_STATUS_END_E = 185 /* 0xb9 */, + WIFIRX_TRIG_INFO_E = 186 /* 0xba */, + WIFIRXPCU_TX_SETUP_CLEAR_E = 187 /* 0xbb */, + WIFIRX_FRAME_BITMAP_REQ_E = 188 /* 0xbc */, + WIFIRX_FRAME_BITMAP_ACK_E = 189 /* 0xbd */, + WIFICOEX_RX_STATUS_E = 190 /* 0xbe */, + WIFIRX_START_PARAM_E = 191 /* 0xbf */, + WIFIRX_PPDU_START_E = 192 /* 0xc0 */, + WIFIRX_PPDU_END_E = 193 /* 0xc1 */, + WIFIRX_MPDU_START_E = 194 /* 0xc2 */, + WIFIRX_MPDU_END_E = 195 /* 0xc3 */, + WIFIRX_MSDU_START_E = 196 /* 0xc4 */, + WIFIRX_MSDU_END_E = 197 /* 0xc5 */, + WIFIRX_ATTENTION_E = 198 /* 0xc6 */, + WIFIRECEIVED_RESPONSE_INFO_E = 199 /* 0xc7 */, + WIFIRX_PHY_SLEEP_E = 200 /* 0xc8 */, + WIFIRX_HEADER_E = 201 /* 0xc9 */, + WIFIRX_PEER_ENTRY_E = 202 /* 0xca */, + WIFIRX_FLUSH_E = 203 /* 0xcb */, + WIFIRX_RESPONSE_REQUIRED_INFO_E = 204 /* 0xcc */, + WIFIRX_FRAMELESS_BAR_DETAILS_E = 205 /* 0xcd */, + WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 206 /* 0xce */, + WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 207 /* 0xcf */, + WIFITX_CBF_INFO_E = 208 /* 0xd0 */, + WIFIPCU_PPDU_SETUP_USER_E = 209 /* 0xd1 */, + WIFIRX_MPDU_PCU_START_E = 210 /* 0xd2 */, + WIFIRX_PM_INFO_E = 211 /* 0xd3 */, + WIFIRX_USER_PPDU_END_E = 212 /* 0xd4 */, + WIFIRX_PRE_PPDU_START_E = 213 /* 0xd5 */, + WIFIRX_PREAMBLE_E = 214 /* 0xd6 */, + WIFITX_FES_SETUP_COMPLETE_E = 215 /* 0xd7 */, + WIFITX_LAST_MPDU_FETCHED_E = 216 /* 0xd8 */, + WIFITXDMA_STOP_REQUEST_E = 217 /* 0xd9 */, + WIFIRXPCU_SETUP_E = 218 /* 0xda */, + WIFIRXPCU_USER_SETUP_E = 219 /* 0xdb */, + WIFITX_FES_STATUS_ACK_OR_BA_E = 220 /* 0xdc */, + WIFITQM_ACKED_MPDU_E = 221 /* 0xdd */, + WIFICOEX_TX_RESP_E = 222 /* 0xde */, + WIFICOEX_TX_STATUS_E = 223 /* 0xdf */, + WIFIMACTX_COEX_PHY_CTRL_E = 224 /* 0xe0 */, + WIFICOEX_STATUS_BROADCAST_E = 225 /* 0xe1 */, + WIFIRESPONSE_START_STATUS_E = 226 /* 0xe2 */, + WIFIRESPONSE_END_STATUS_E = 227 /* 0xe3 */, + WIFICRYPTO_STATUS_E = 228 /* 0xe4 */, + WIFIRECEIVED_TRIGGER_INFO_E = 229 /* 0xe5 */, + WIFICOEX_TX_STOP_CTRL_E = 230 /* 0xe6 */, + WIFIRX_PPDU_ACK_REPORT_E = 231 /* 0xe7 */, + WIFIRX_PPDU_NO_ACK_REPORT_E = 232 /* 0xe8 */, + WIFISCH_COEX_STATUS_E = 233 /* 0xe9 */, + WIFISCHEDULER_COMMAND_STATUS_E = 234 /* 0xea */, + WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 235 /* 0xeb */, + WIFITX_FES_STATUS_PROT_E = 236 /* 0xec */, + WIFITX_FES_STATUS_START_PPDU_E = 237 /* 0xed */, + WIFITX_FES_STATUS_START_PROT_E = 238 /* 0xee */, + WIFITXPCU_PHYTX_DEBUG32_E = 239 /* 0xef */, + WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 240 /* 0xf0 */, + WIFITX_MPDU_COUNT_TRANSFER_END_E = 241 /* 0xf1 */, + WIFIWHO_ANCHOR_OFFSET_E = 242 /* 0xf2 */, + WIFIWHO_ANCHOR_VALUE_E = 243 /* 0xf3 */, + WIFIWHO_CCE_INFO_E = 244 /* 0xf4 */, + WIFIWHO_COMMIT_E = 245 /* 0xf5 */, + WIFIWHO_COMMIT_DONE_E = 246 /* 0xf6 */, + WIFIWHO_FLUSH_E = 247 /* 0xf7 */, + WIFIWHO_L2_LLC_E = 248 /* 0xf8 */, + WIFIWHO_L2_PAYLOAD_E = 249 /* 0xf9 */, + WIFIWHO_L3_CHECKSUM_E = 250 /* 0xfa */, + WIFIWHO_L3_INFO_E = 251 /* 0xfb */, + WIFIWHO_L4_CHECKSUM_E = 252 /* 0xfc */, + WIFIWHO_L4_INFO_E = 253 /* 0xfd */, + WIFIWHO_MSDU_E = 254 /* 0xfe */, + WIFIWHO_MSDU_MISC_E = 255 /* 0xff */, + WIFIWHO_PACKET_DATA_E = 256 /* 0x100 */, + WIFIWHO_PACKET_HDR_E = 257 /* 0x101 */, + WIFIWHO_PPDU_END_E = 258 /* 0x102 */, + WIFIWHO_PPDU_START_E = 259 /* 0x103 */, + WIFIWHO_TSO_E = 260 /* 0x104 */, + WIFIWHO_WMAC_HEADER_PV0_E = 261 /* 0x105 */, + WIFIWHO_WMAC_HEADER_PV1_E = 262 /* 0x106 */, + WIFIWHO_WMAC_IV_E = 263 /* 0x107 */, + WIFIMPDU_INFO_END_E = 264 /* 0x108 */, + WIFIMPDU_INFO_BITMAP_E = 265 /* 0x109 */, + WIFITX_QUEUE_EXTENSION_E = 266 /* 0x10a */, + WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 267 /* 0x10b */, + WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 268 /* 0x10c */, + WIFITQM_ACKED_MPDU_STATUS_E = 269 /* 0x10d */, + WIFITQM_ADD_MSDU_STATUS_E = 270 /* 0x10e */, + WIFITQM_LIST_GEN_DONE_E = 271 /* 0x10f */, + WIFIWHO_TERMINATE_E = 272 /* 0x110 */, + WIFITX_LAST_MPDU_END_E = 273 /* 0x111 */, + WIFITX_CV_DATA_E = 274 /* 0x112 */, + WIFIPPDU_TX_END_E = 275 /* 0x113 */, + WIFIPROT_TX_END_E = 276 /* 0x114 */, + WIFIMPDU_INFO_GLOBAL_END_E = 277 /* 0x115 */, + WIFITQM_SCH_INSTR_GLOBAL_END_E = 278 /* 0x116 */, + WIFIRX_PPDU_END_USER_STATS_E = 279 /* 0x117 */, + WIFIRX_PPDU_END_USER_STATS_EXT_E = 280 /* 0x118 */, + WIFIREO_GET_QUEUE_STATS_E = 281 /* 0x119 */, + WIFIREO_FLUSH_QUEUE_E = 282 /* 0x11a */, + WIFIREO_FLUSH_CACHE_E = 283 /* 0x11b */, + WIFIREO_UNBLOCK_CACHE_E = 284 /* 0x11c */, + WIFIREO_GET_QUEUE_STATS_STATUS_E = 285 /* 0x11d */, + WIFIREO_FLUSH_QUEUE_STATUS_E = 286 /* 0x11e */, + WIFIREO_FLUSH_CACHE_STATUS_E = 287 /* 0x11f */, + WIFIREO_UNBLOCK_CACHE_STATUS_E = 288 /* 0x120 */, + WIFITQM_FLUSH_CACHE_E = 289 /* 0x121 */, + WIFITQM_UNBLOCK_CACHE_E = 290 /* 0x122 */, + WIFITQM_FLUSH_CACHE_STATUS_E = 291 /* 0x123 */, + WIFITQM_UNBLOCK_CACHE_STATUS_E = 292 /* 0x124 */, + WIFIRX_PPDU_END_STATUS_DONE_E = 293 /* 0x125 */, + WIFIRX_STATUS_BUFFER_DONE_E = 294 /* 0x126 */, + WIFISCHEDULER_MLO_SW_MSG_STATUS_E = 295 /* 0x127 */, + WIFISCHEDULER_TXOP_DURATION_TRIGGER_E = 296 /* 0x128 */, + WIFITX_DATA_SYNC_E = 297 /* 0x129 */, + WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 298 /* 0x12a */, + WIFITQM_GET_MPDU_HEAD_INFO_E = 299 /* 0x12b */, + WIFITQM_SYNC_CMD_E = 300 /* 0x12c */, + WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 301 /* 0x12d */, + WIFITQM_SYNC_CMD_STATUS_E = 302 /* 0x12e */, + WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 303 /* 0x12f */, + WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 304 /* 0x130 */, + WIFIREO_FLUSH_TIMEOUT_LIST_E = 305 /* 0x131 */, + WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 306 /* 0x132 */, + WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 307 /* 0x133 */, + WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 308 /* 0x134 */, + WIFIEXAMPLE_USER_TLV_32_NAME_E = 309 /* 0x135 */, + WIFIRX_PPDU_START_USER_INFO_E = 310 /* 0x136 */, + WIFIRX_RING_MASK_E = 311 /* 0x137 */, + WIFICOEX_MAC_NAP_E = 312 /* 0x138 */, + WIFIRXPCU_PPDU_END_INFO_E = 313 /* 0x139 */, + WIFIWHO_MESH_CONTROL_E = 314 /* 0x13a */, + WIFIPDG_SW_MODE_BW_START_E = 315 /* 0x13b */, + WIFIPDG_SW_MODE_BW_END_E = 316 /* 0x13c */, + WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 317 /* 0x13d */, + WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 318 /* 0x13e */, + WIFISCHEDULER_END_E = 319 /* 0x13f */, + WIFIRX_PPDU_START_DROPPED_E = 320 /* 0x140 */, + WIFIRX_PPDU_END_DROPPED_E = 321 /* 0x141 */, + WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 322 /* 0x142 */, + WIFIRX_MPDU_START_DROPPED_E = 323 /* 0x143 */, + WIFIRX_MSDU_START_DROPPED_E = 324 /* 0x144 */, + WIFIRX_MSDU_END_DROPPED_E = 325 /* 0x145 */, + WIFIRX_MPDU_END_DROPPED_E = 326 /* 0x146 */, + WIFIRX_ATTENTION_DROPPED_E = 327 /* 0x147 */, + WIFITXPCU_USER_SETUP_E = 328 /* 0x148 */, + WIFIRXPCU_USER_SETUP_EXT_E = 329 /* 0x149 */, + WIFICMD_PART_0_END_E = 330 /* 0x14a */, + WIFIMACTX_SYNTH_ON_E = 331 /* 0x14b */, + WIFISCH_CRITICAL_TLV_REFERENCE_E = 332 /* 0x14c */, + WIFITQM_MPDU_GLOBAL_START_E = 333 /* 0x14d */, + WIFIEXAMPLE_TLV_32_E = 334 /* 0x14e */, + WIFITQM_UPDATE_TX_MSDU_FLOW_E = 335 /* 0x14f */, + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 336 /* 0x150 */, + WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 337 /* 0x151 */, + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 338 /* 0x152 */, + WIFIREO_UPDATE_RX_REO_QUEUE_E = 339 /* 0x153 */, + WIFITQM_MPDU_QUEUE_EMPTY_STATUS_E = 340 /* 0x154 */, + WIFITQM_2_SCH_MPDU_AVAILABLE_E = 341 /* 0x155 */, + WIFIPDG_TRIG_RESPONSE_E = 342 /* 0x156 */, + WIFITRIGGER_RESPONSE_TX_DONE_E = 343 /* 0x157 */, + WIFIABORT_FROM_PHYRX_DETAILS_E = 344 /* 0x158 */, + WIFISCH_TQM_CMD_WRAPPER_E = 345 /* 0x159 */, + WIFIMPDUS_AVAILABLE_E = 346 /* 0x15a */, + WIFIRECEIVED_RESPONSE_INFO_PART2_E = 347 /* 0x15b */, + WIFIPHYRX_TX_START_TIMING_E = 348 /* 0x15c */, + WIFITXPCU_PREAMBLE_DONE_E = 349 /* 0x15d */, + WIFINDP_PREAMBLE_DONE_E = 350 /* 0x15e */, + WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 351 /* 0x15f */, + WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 352 /* 0x160 */, + WIFIMACTX_CLEAR_PREV_TX_INFO_E = 353 /* 0x161 */, + WIFITX_PUNCTURE_SETUP_E = 354 /* 0x162 */, + WIFIR2R_STATUS_END_E = 355 /* 0x163 */, + WIFIMACTX_PREFETCH_CV_COMMON_E = 356 /* 0x164 */, + WIFIEND_OF_FLUSH_MARKER_E = 357 /* 0x165 */, + WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 358 /* 0x166 */, + WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 359 /* 0x167 */, + WIFIRECEIVED_RESPONSE_USER_7_0_E = 360 /* 0x168 */, + WIFIRECEIVED_RESPONSE_USER_15_8_E = 361 /* 0x169 */, + WIFIRECEIVED_RESPONSE_USER_23_16_E = 362 /* 0x16a */, + WIFIRECEIVED_RESPONSE_USER_31_24_E = 363 /* 0x16b */, + WIFIRECEIVED_RESPONSE_USER_36_32_E = 364 /* 0x16c */, + WIFITX_LOOPBACK_SETUP_E = 365 /* 0x16d */, + WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 366 /* 0x16e */, + WIFISCH_WAIT_INSTR_TX_PATH_E = 367 /* 0x16f */, + WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 368 /* 0x170 */, + WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 369 /* 0x171 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 370 /* 0x172 */, + WIFITX_WUR_DATA_E = 371 /* 0x173 */, + WIFIRX_PPDU_END_START_E = 372 /* 0x174 */, + WIFIRX_PPDU_END_MIDDLE_E = 373 /* 0x175 */, + WIFIRX_PPDU_END_LAST_E = 374 /* 0x176 */, + WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 375 /* 0x177 */, + WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 376 /* 0x178 */, + WIFISRP_INFO_E = 377 /* 0x179 */, + WIFIOBSS_SR_INFO_E = 378 /* 0x17a */, + WIFISCHEDULER_SW_MSG_STATUS_E = 379 /* 0x17b */, + WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 380 /* 0x17c */, + WIFIRXPCU_SETUP_COMPLETE_E = 381 /* 0x17d */, + WIFISNOOP_PPDU_START_E = 382 /* 0x17e */, + WIFISNOOP_MPDU_USR_DBG_INFO_E = 383 /* 0x17f */, + WIFISNOOP_MSDU_USR_DBG_INFO_E = 384 /* 0x180 */, + WIFISNOOP_MSDU_USR_DATA_E = 385 /* 0x181 */, + WIFISNOOP_MPDU_USR_STAT_INFO_E = 386 /* 0x182 */, + WIFISNOOP_PPDU_END_E = 387 /* 0x183 */, + WIFISNOOP_SPARE_E = 388 /* 0x184 */, + WIFILMR_TX_END_E = 389 /* 0x185 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 390 /* 0x186 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 391 /* 0x187 */, + WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 392 /* 0x188 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 393 /* 0x189 */, + WIFISCH_TLV_WRAPPER_E = 394 /* 0x18a */, + WIFISCHEDULER_STATUS_WRAPPER_E = 395 /* 0x18b */, + WIFIMPDU_INFO_6X_E = 396 /* 0x18c */, + WIFIMACTX_11AZ_USER_DESC_PER_USER_E = 397 /* 0x18d */, + WIFIMACTX_U_SIG_EHT_SU_MU_E = 398 /* 0x18e */, + WIFIMACTX_U_SIG_EHT_TB_E = 399 /* 0x18f */, + WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E = 400 /* 0x190 */, + WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E = 401 /* 0x191 */, + WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E = 402 /* 0x192 */, + WIFIPHYRX_U_SIG_EHT_SU_MU_E = 403 /* 0x193 */, + WIFIPHYRX_U_SIG_EHT_TB_E = 404 /* 0x194 */, + WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E = 405 /* 0x195 */, + WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 406 /* 0x196 */, + WIFITX_PUNCTURE_6PATTERNS_SETUP_E = 407 /* 0x197 */, + WIFIMACRX_LMR_READ_REQUEST_E = 408 /* 0x198 */, + WIFIMACRX_LMR_DATA_REQUEST_E = 409 /* 0x199 */, + WIFIPHYRX_LMR_TRANSFER_DONE_E = 410 /* 0x19a */, + WIFIPHYRX_LMR_TRANSFER_ABORT_E = 411 /* 0x19b */, + WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 412 /* 0x19c */, + WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 413 /* 0x19d */, + WIFIPHYRX_USER_INFO_MU_UL_E = 414 /* 0x19e */, + WIFIMPDU_QUEUE_OVERVIEW_E = 415 /* 0x19f */, + WIFISCHEDULER_NAV_INFO_E = 416 /* 0x1a0 */, + WIFILMR_PEER_ENTRY_E = 418 /* 0x1a2 */, + WIFILMR_MPDU_START_E = 419 /* 0x1a3 */, + WIFILMR_DATA_E = 420 /* 0x1a4 */, + WIFILMR_MPDU_END_E = 421 /* 0x1a5 */, + WIFIREO_GET_QUEUE_1K_STATS_STATUS_E = 422 /* 0x1a6 */, + WIFIRX_FRAME_1K_BITMAP_ACK_E = 423 /* 0x1a7 */, + WIFITX_FES_STATUS_1K_BA_E = 424 /* 0x1a8 */, + WIFITQM_ACKED_1K_MPDU_E = 425 /* 0x1a9 */, + WIFIMACRX_INBSS_OBSS_IND_E = 426 /* 0x1aa */, + WIFIPHYRX_LOCATION_E = 427 /* 0x1ab */, + WIFIMLO_TX_NOTIFICATION_SU_E = 428 /* 0x1ac */, + WIFIMLO_TX_NOTIFICATION_MU_E = 429 /* 0x1ad */, + WIFIMLO_TX_REQ_SU_E = 430 /* 0x1ae */, + WIFIMLO_TX_REQ_MU_E = 431 /* 0x1af */, + WIFIMLO_TX_RESP_E = 432 /* 0x1b0 */, + WIFIMLO_RX_NOTIFICATION_E = 433 /* 0x1b1 */, + WIFIMLO_BKOFF_TRUNC_REQ_E = 434 /* 0x1b2 */, + WIFIMLO_TBTT_NOTIFICATION_E = 435 /* 0x1b3 */, + WIFIMLO_MESSAGE_E = 436 /* 0x1b4 */, + WIFIMLO_TS_SYNC_MSG_E = 437 /* 0x1b5 */, + WIFIMLO_FES_SETUP_E = 438 /* 0x1b6 */, + WIFIMLO_PDG_FES_SETUP_SU_E = 439 /* 0x1b7 */, + WIFIMLO_PDG_FES_SETUP_MU_E = 440 /* 0x1b8 */, + WIFIMPDU_INFO_1K_BITMAP_E = 441 /* 0x1b9 */, + WIFIMON_BUFFER_ADDR_E = 442 /* 0x1ba */, + WIFITX_FRAG_STATE_E = 443 /* 0x1bb */, + WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 444 /* 0x1bc */, + WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 445 /* 0x1bd */, + WIFIMACTX_EHT_SIG_USR_OFDMA_E = 446 /* 0x1be */, + WIFIPHYRX_EHT_SIG_CMN_PUNC_E = 448 /* 0x1c0 */, + WIFIPHYRX_EHT_SIG_CMN_OFDMA_E = 450 /* 0x1c2 */, + WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 454 /* 0x1c6 */, + WIFIPHYRX_PKT_END_PART1_E = 456 /* 0x1c8 */, + WIFIMACTX_EXPECT_NDP_RECEPTION_E = 457 /* 0x1c9 */, + WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 458 /* 0x1ca */, + WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 460 /* 0x1cc */, + WIFIPHYRX_11AZ_INTEGRITY_DATA_E = 461 /* 0x1cd */, + WIFIPHYTX_LOCATION_E = 462 /* 0x1ce */, + WIFIPHYTX_11AZ_INTEGRITY_DATA_E = 463 /* 0x1cf */, + WIFIMACTX_EHT_SIG_USR_SU_E = 466 /* 0x1d2 */, + WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 467 /* 0x1d3 */, + WIFIPHYRX_EHT_SIG_USR_SU_E = 468 /* 0x1d4 */, + WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 469 /* 0x1d5 */, + WIFIPHYRX_GENERIC_U_SIG_E = 470 /* 0x1d6 */, + WIFIPHYRX_GENERIC_EHT_SIG_E = 471 /* 0x1d7 */, + WIFIOVERWRITE_RESP_START_E = 472 /* 0x1d8 */, + WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 473 /* 0x1d9 */, + WIFIOVERWRITE_RESP_FRAME_INFO_E = 474 /* 0x1da */, + WIFIOVERWRITE_RESP_END_E = 475 /* 0x1db */, + WIFIRXPCU_EARLY_RX_INDICATION_E = 476 /* 0x1dc */, + WIFIMON_DROP_E = 477 /* 0x1dd */, + WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 478 /* 0x1de */, + WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 479 /* 0x1df */, + WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 480 /* 0x1e0 */, + WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 481 /* 0x1e1 */, + WIFIMACTX_PREFETCH_CV_DMA_E = 482 /* 0x1e2 */, + WIFIMACTX_PREFETCH_CV_PER_USER_E = 483 /* 0x1e3 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 484 /* 0x1e4 */, + WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 485 /* 0x1e5 */, + WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 486 /* 0x1e6 */, + WIFIRANGING_USER_DETAILS_E = 487 /* 0x1e7 */, + WIFIPHYTX_CV_CORR_STATUS_E = 488 /* 0x1e8 */, + WIFIPHYTX_CV_CORR_COMMON_E = 489 /* 0x1e9 */, + WIFIPHYTX_CV_CORR_USER_E = 490 /* 0x1ea */, + WIFIMACTX_CV_CORR_COMMON_E = 491 /* 0x1eb */, + WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 492 /* 0x1ec */, + WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 493 /* 0x1ed */, + WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 494 /* 0x1ee */, + WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 495 /* 0x1ef */, + WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 496 /* 0x1f0 */, + WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 497 /* 0x1f1 */, + WIFIRX_PPDU_END_USER_STATS_EXT2_E = 498 /* 0x1f2 */, + WIFIFW2SW_MON_E = 499 /* 0x1f3 */, + WIFIWSI_DIRECT_MESSAGE_E = 500 /* 0x1f4 */, + WIFIMACTX_EMLSR_PRE_SWITCH_E = 501 /* 0x1f5 */, + WIFIMACTX_EMLSR_SWITCH_E = 502 /* 0x1f6 */, + WIFIMACTX_EMLSR_SWITCH_BACK_E = 503 /* 0x1f7 */, + WIFIPHYTX_EMLSR_SWITCH_ACK_E = 504 /* 0x1f8 */, + WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 505 /* 0x1f9 */, + WIFISPARE_REUSE_TAG_0_E = 506 /* 0x1fa */, + WIFISPARE_REUSE_TAG_1_E = 507 /* 0x1fb */, + WIFISPARE_REUSE_TAG_2_E = 508 /* 0x1fc */, + WIFISPARE_REUSE_TAG_3_E = 509 /* 0x1fd */ +} tlv_tag_def__e; + + +#endif diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_cbf_info.h b/drivers/staging/fw-api/hw/qcn6432/tx_cbf_info.h new file mode 100644 index 0000000000000000000000000000000000000000..bed277fb9133f3c2ba834d519201f3923f603b34 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_cbf_info.h @@ -0,0 +1,1189 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_CBF_INFO_H_ +#define _TX_CBF_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_CBF_INFO 16 + +#define NUM_OF_QWORDS_TX_CBF_INFO 8 + + +struct tx_cbf_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sw_peer_id : 16, // [15:0] + pre_cbf_duration : 16; // [31:16] + uint32_t brpoll_info_valid : 1, // [0:0] + trigger_brpoll_info_valid : 1, // [1:1] + npda_info_11ac_valid : 1, // [2:2] + npda_info_11ax_valid : 1, // [3:3] + dot11ax_su_extended : 1, // [4:4] + bandwidth : 3, // [7:5] + brpoll_info : 8, // [15:8] + cbf_response_table_base_index : 8, // [23:16] + peer_index : 3, // [26:24] + pkt_type : 4, // [30:27] + txop_duration_all_ones : 1; // [31:31] + uint32_t trigger_brpoll_common_info_15_0 : 16, // [15:0] + trigger_brpoll_common_info_31_16 : 16; // [31:16] + uint32_t trigger_brpoll_user_info_15_0 : 16, // [15:0] + trigger_brpoll_user_info_31_16 : 16; // [31:16] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr1_47_32 : 16, // [15:0] + addr2_15_0 : 16; // [31:16] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t addr3_31_0 : 32; // [31:0] + uint32_t addr3_47_32 : 16, // [15:0] + sta_partial_aid : 11, // [26:16] + reserved_8a : 4, // [30:27] + cbf_resp_pwr_mgmt : 1; // [31:31] + uint32_t group_id : 6, // [5:0] + rssi_comb : 8, // [13:6] + reserved_9a : 2, // [15:14] + vht_ndpa_sta_info : 16; // [31:16] + uint32_t he_eht_sta_info_15_0 : 16, // [15:0] + he_eht_sta_info_31_16 : 16; // [31:16] + uint32_t dot11ax_received_format_indication : 1, // [0:0] + dot11ax_received_dl_ul_flag : 1, // [1:1] + dot11ax_received_bss_color_id : 6, // [7:2] + dot11ax_received_spatial_reuse : 4, // [11:8] + dot11ax_received_cp_size : 2, // [13:12] + dot11ax_received_ltf_size : 2, // [15:14] + dot11ax_received_coding : 1, // [16:16] + dot11ax_received_dcm : 1, // [17:17] + dot11ax_received_doppler_indication : 1, // [18:18] + dot11ax_received_ext_ru_size : 4, // [22:19] + dot11ax_dl_ul_flag : 1, // [23:23] + reserved_11a : 8; // [31:24] + uint32_t sw_response_frame_length : 16, // [15:0] + sw_response_tlv_from_crypto : 1, // [16:16] + wait_sifs_config_valid : 1, // [17:17] + wait_sifs : 2, // [19:18] + ranging : 1, // [20:20] + secure : 1, // [21:21] + tb_ranging_response_required : 2, // [23:22] + reserved_12a : 2, // [25:24] + u_sig_puncture_pattern_encoding : 6; // [31:26] + uint32_t dot11be_puncture_bitmap : 16, // [15:0] + dot11be_response : 1, // [16:16] + punctured_response : 1, // [17:17] + npda_info_11be_valid : 1, // [18:18] + eht_duplicate_mode : 2, // [20:19] + reserved_13a : 11; // [31:21] + uint32_t eht_sta_info_39_32 : 8, // [7:0] + reserved_14a : 24; // [31:8] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t pre_cbf_duration : 16, // [31:16] + sw_peer_id : 16; // [15:0] + uint32_t txop_duration_all_ones : 1, // [31:31] + pkt_type : 4, // [30:27] + peer_index : 3, // [26:24] + cbf_response_table_base_index : 8, // [23:16] + brpoll_info : 8, // [15:8] + bandwidth : 3, // [7:5] + dot11ax_su_extended : 1, // [4:4] + npda_info_11ax_valid : 1, // [3:3] + npda_info_11ac_valid : 1, // [2:2] + trigger_brpoll_info_valid : 1, // [1:1] + brpoll_info_valid : 1; // [0:0] + uint32_t trigger_brpoll_common_info_31_16 : 16, // [31:16] + trigger_brpoll_common_info_15_0 : 16; // [15:0] + uint32_t trigger_brpoll_user_info_31_16 : 16, // [31:16] + trigger_brpoll_user_info_15_0 : 16; // [15:0] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr2_15_0 : 16, // [31:16] + addr1_47_32 : 16; // [15:0] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t addr3_31_0 : 32; // [31:0] + uint32_t cbf_resp_pwr_mgmt : 1, // [31:31] + reserved_8a : 4, // [30:27] + sta_partial_aid : 11, // [26:16] + addr3_47_32 : 16; // [15:0] + uint32_t vht_ndpa_sta_info : 16, // [31:16] + reserved_9a : 2, // [15:14] + rssi_comb : 8, // [13:6] + group_id : 6; // [5:0] + uint32_t he_eht_sta_info_31_16 : 16, // [31:16] + he_eht_sta_info_15_0 : 16; // [15:0] + uint32_t reserved_11a : 8, // [31:24] + dot11ax_dl_ul_flag : 1, // [23:23] + dot11ax_received_ext_ru_size : 4, // [22:19] + dot11ax_received_doppler_indication : 1, // [18:18] + dot11ax_received_dcm : 1, // [17:17] + dot11ax_received_coding : 1, // [16:16] + dot11ax_received_ltf_size : 2, // [15:14] + dot11ax_received_cp_size : 2, // [13:12] + dot11ax_received_spatial_reuse : 4, // [11:8] + dot11ax_received_bss_color_id : 6, // [7:2] + dot11ax_received_dl_ul_flag : 1, // [1:1] + dot11ax_received_format_indication : 1; // [0:0] + uint32_t u_sig_puncture_pattern_encoding : 6, // [31:26] + reserved_12a : 2, // [25:24] + tb_ranging_response_required : 2, // [23:22] + secure : 1, // [21:21] + ranging : 1, // [20:20] + wait_sifs : 2, // [19:18] + wait_sifs_config_valid : 1, // [17:17] + sw_response_tlv_from_crypto : 1, // [16:16] + sw_response_frame_length : 16; // [15:0] + uint32_t reserved_13a : 11, // [31:21] + eht_duplicate_mode : 2, // [20:19] + npda_info_11be_valid : 1, // [18:18] + punctured_response : 1, // [17:17] + dot11be_response : 1, // [16:16] + dot11be_puncture_bitmap : 16; // [15:0] + uint32_t reserved_14a : 24, // [31:8] + eht_sta_info_39_32 : 8; // [7:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description SW_PEER_ID + + An identifier indicating from which AP this CBF is being + requested. Helps in crosschecking that the MAC and PHY + are still in sync on what is stored in the cbf_mem_index + location. + +*/ + +#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_SW_PEER_ID_LSB 0 +#define TX_CBF_INFO_SW_PEER_ID_MSB 15 +#define TX_CBF_INFO_SW_PEER_ID_MASK 0x000000000000ffff + + +/* Description PRE_CBF_DURATION + + NPDA_duration_field - SIFS - NDP_pkt_time or BRPOLL_duration_field. + The cbf_duration_field = pre_cbf_duration - cbf_pkt_time + + + This will be the pre-NDP duration or pre-LMR duration in + case of .11az ranging (field Ranging below is set). +*/ + +#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 +#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 +#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0x00000000ffff0000 + + +/* Description BRPOLL_INFO_VALID + + When set, legacy type brpoll info is valid. TXPCU will have + to trigger the PDG for response transmission + + It will not be clear here what the PHY's response format + will be. Could be 11ac or 11ax. MAC is not 'remembering' + the format type, but PHY will know. + + MAC will get to know based on the field Cbf_response_type + in the PHYRX_CBF_READ_REQUEST_ACK TLV. + + +*/ + +#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 32 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 32 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x0000000100000000 + + +/* Description TRIGGER_BRPOLL_INFO_VALID + + When set with Ranging = 0, trigger based brpoll info is + valid. + When set with Ranging = 1, .11az sounding trigger info is + valid for trigger-based ranging (TBR). + This also implies that RXPCU has already triggered the PDG + for response transmission + +*/ + +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 33 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 33 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x0000000200000000 + + +/* Description NPDA_INFO_11AC_VALID + + When set, 11ac_NDPA info is valid. + TXPCU will have to trigger the PDG for response transmission + + + PHY's response will be be in 11ac format + +*/ + +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 34 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 34 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x0000000400000000 + + +/* Description NPDA_INFO_11AX_VALID + + When set, 11ax_NDPA info is valid. + TXPCU will have to trigger the PDG for response transmission + + + PHY's response will be be in 11ax format + + There is a separate Npda_info_11be_valid field near the + end of this TLV. + +*/ + +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 35 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 35 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x0000000800000000 + + +/* Description DOT11AX_SU_EXTENDED + + When set, frame was received in 11ax or 11be extended range + format +*/ + +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 36 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 36 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000001000000000 + + +/* Description BANDWIDTH + + Field only valid when Brpoll_info_valid , Npda_info_11ac_valid + or Npda_info_11ax_valid is set. + + The bandwidth that TXPCU uses to select the final response + table entry. That entry will contain all response info + for the CBF frame. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BANDWIDTH_LSB 37 +#define TX_CBF_INFO_BANDWIDTH_MSB 39 +#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e000000000 + + +/* Description BRPOLL_INFO + + Field only valid when Brpoll_info_valid is set. + + Feedback Segment retransmission feedback field from the + BRPOLL frame. + +*/ + +#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BRPOLL_INFO_LSB 40 +#define TX_CBF_INFO_BRPOLL_INFO_MSB 47 +#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff0000000000 + + +/* Description CBF_RESPONSE_TABLE_BASE_INDEX + + Field only valid when Brpoll_info_valid or + Npda_info_11ac_valid or Npda_info_11ax_valid is set. + + When set to 0, use the register based lookup for determining + the CBF response rates. + + When > 0, TXPCU shall use this response table index for + the 20 MHz response, and higher BW responses are in the + subsequent response table entries + + This will be the LMR response table base index in case of + .11az ranging (field Ranging below is set). + + +*/ + +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 48 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 55 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff000000000000 + + +/* Description PEER_INDEX + + Field only valid when Brpoll_info_valid or + Npda_info_11ac_valid or Npda_info_11ax_valid is set. + + + Indicates the CBF peer index to be used by TxPCU to determine + the look-up table index for CBF response frames. RxPCU + populate this field from the peer_entry. + +*/ + +#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PEER_INDEX_LSB 56 +#define TX_CBF_INFO_PEER_INDEX_MSB 58 +#define TX_CBF_INFO_PEER_INDEX_MASK 0x0700000000000000 + + +/* Description PKT_TYPE + + Received Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PKT_TYPE_LSB 59 +#define TX_CBF_INFO_PKT_TYPE_MSB 62 +#define TX_CBF_INFO_PKT_TYPE_MASK 0x7800000000000000 + + +/* Description TXOP_DURATION_ALL_ONES + + When set, either the TXOP_DURATION of the received frame + was set to all 1s or there is a BSS color collision. The + TXOP_DURATION of the transmit response should be forced + to all 1s. + + +*/ + +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 63 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 63 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 + + +/* Description TRIGGER_BRPOLL_COMMON_INFO_15_0 + + Field only valid when Trigger_Brpoll_info_valid is set. + + + Trigger based BRPOLL or .11az sounding (TBR) request info... + bits [15:0] + + This is the variable common info field from the trigger + related to the BTPOLL. For field definition see IEEE spec + + + Note: final IEEE field might not need all these bits. If + so, the extra bits become reserved fields. + +*/ + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x000000000000ffff + + +/* Description TRIGGER_BRPOLL_COMMON_INFO_31_16 + + Field only valid when Trigger_Brpoll_info_valid is set. + + + Trigger based BRPOLL or .11az sounding (TBR) request info... + bits [31:15] + + This is the variable common info field from the trigger + related to the BTPOLL. For field definition see IEEE spec + + + Note: final IEEE field might not need all these bits. If + so, the extra bits become reserved fields. + +*/ + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0x00000000ffff0000 + + +/* Description TRIGGER_BRPOLL_USER_INFO_15_0 + + Field only valid when Trigger_Brpoll_info_valid is set. + + + BRPOLL or .11az sounding (TBR) trigger Type dependent User + information bits [15:0] + + This is the variable user info field from the trigger related + to the BTPOLL. + + For field definition see IEEE spec + + Note: final IEEE field might not need all these bits. If + so, the extra bits become reserved fields. + +*/ + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 32 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 47 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff00000000 + + +/* Description TRIGGER_BRPOLL_USER_INFO_31_16 + + Field only valid when Trigger_Brpoll_info_valid is set. + + + BRPOLL or .11az sounding (TBR) trigger Type dependent User + information bits [31:16] + + This is the variable user info field from the trigger related + to the BTPOLL. + + For field definition see IEEE spec + + Note: final IEEE field might not need all these bits. If + so, the extra bits become reserved fields. + +*/ + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 48 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 63 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff000000000000 + + +/* Description ADDR1_31_0 + + CBF address1[31:0] +*/ + +#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR1_31_0_LSB 0 +#define TX_CBF_INFO_ADDR1_31_0_MSB 31 +#define TX_CBF_INFO_ADDR1_31_0_MASK 0x00000000ffffffff + + +/* Description ADDR1_47_32 + + CBF address1[47:32] +*/ + +#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR1_47_32_LSB 32 +#define TX_CBF_INFO_ADDR1_47_32_MSB 47 +#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 + + +/* Description ADDR2_15_0 + + CBF address2[15:0] +*/ + +#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR2_15_0_LSB 48 +#define TX_CBF_INFO_ADDR2_15_0_MSB 63 +#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff000000000000 + + +/* Description ADDR2_47_16 + + CBF address2[47:16] +*/ + +#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x0000000000000018 +#define TX_CBF_INFO_ADDR2_47_16_LSB 0 +#define TX_CBF_INFO_ADDR2_47_16_MSB 31 +#define TX_CBF_INFO_ADDR2_47_16_MASK 0x00000000ffffffff + + +/* Description ADDR3_31_0 + + CBF address3[31:0] +*/ + +#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000000000000018 +#define TX_CBF_INFO_ADDR3_31_0_LSB 32 +#define TX_CBF_INFO_ADDR3_31_0_MSB 63 +#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff00000000 + + +/* Description ADDR3_47_32 + + CBF address3[47:16] +*/ + +#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_ADDR3_47_32_LSB 0 +#define TX_CBF_INFO_ADDR3_47_32_MSB 15 +#define TX_CBF_INFO_ADDR3_47_32_MASK 0x000000000000ffff + + +/* Description STA_PARTIAL_AID + + Partial AID field +*/ + +#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 +#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 +#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x0000000007ff0000 + + +/* Description RESERVED_8A + + +*/ + +#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RESERVED_8A_LSB 27 +#define TX_CBF_INFO_RESERVED_8A_MSB 30 +#define TX_CBF_INFO_RESERVED_8A_MASK 0x0000000078000000 + + +/* Description CBF_RESP_PWR_MGMT + + Power management bit of the response CBF frame or LMR frame + in case of .11az ranging (field Ranging below is set). +*/ + +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x0000000080000000 + + +/* Description GROUP_ID + + Group ID field +*/ + +#define TX_CBF_INFO_GROUP_ID_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_GROUP_ID_LSB 32 +#define TX_CBF_INFO_GROUP_ID_MSB 37 +#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f00000000 + + +/* Description RSSI_COMB + + The combined RSSI of the legacy STF of RX PPDU of all active + chains and bandwidths. +*/ + +#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RSSI_COMB_LSB 38 +#define TX_CBF_INFO_RSSI_COMB_MSB 45 +#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc000000000 + + +/* Description RESERVED_9A + + Bit 14: force_extra_symbol: + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) + + +*/ + +#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RESERVED_9A_LSB 46 +#define TX_CBF_INFO_RESERVED_9A_MSB 47 +#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c00000000000 + + +/* Description VHT_NDPA_STA_INFO + + Field only valid when Npda_info_11ac_valid is set + + The complete (RAW) STA INFO field that MAC extracted from + the VHT NDPA frame. + + Put here for backup reasons in case last moment fields got + added that PHY needs to be able to interpret + + This field contains + { + VHT STA_INFO.NC_INDEX[2:0], + VHT STA_INFO.FEEDBACK_TYPE, + VHT STA_INFO.AID12[11:0] + } + +*/ + +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 48 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 63 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff000000000000 + + +/* Description HE_EHT_STA_INFO_15_0 + + Field only valid when Npda_info_11ax_valid or Npda_info_11be_valid + is set + + The first 16 bits of the RAW HE or EHT STA INFO field in + the NDPA frame + + Put here for backup reasons in case last moment fields got + added that PHY needs to be able to interpret + +*/ + +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x000000000000ffff + + +/* Description HE_EHT_STA_INFO_31_16 + + Field only valid when Npda_info_11ax_valid or Npda_info_11be_valid + is set + + The second 16 bits of the RAW HE or EHT STA INFO field in + the NDPA frame + + Put here for backup reasons in case last moment fields got + added that PHY needs to be able to interpret + + There is an EHT_STA_INFO_39_32 field near the end of this + TLV. + +*/ + +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0x00000000ffff0000 + + +/* Description DOT11AX_RECEIVED_FORMAT_INDICATION + + This field is only valid for pkt_type == 11ax + + Format_Indication from the received frame. + + + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 + + +/* Description DOT11AX_RECEIVED_DL_UL_FLAG + + This field is only valid for pkt_type == 11ax + + DL_UL_flag from the received frame + + Differentiates between DL and UL transmission + + + + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 + + +/* Description DOT11AX_RECEIVED_BSS_COLOR_ID + + This field is only valid for pkt_type == 11ax + + BSS_color_id from the received frame + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 + + +/* Description DOT11AX_RECEIVED_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + Spatial reuse from the received frame + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 + + +/* Description DOT11AX_RECEIVED_CP_SIZE + + This field is only valid for pkt_type == 11ax + + CP size of the received frame + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 + + +/* Description DOT11AX_RECEIVED_LTF_SIZE + + This field is only valid for pkt_type == 11ax + + LTF size of the received frame + + + + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 + + +/* Description DOT11AX_RECEIVED_CODING + + This field is only valid for pkt_type == 11ax + + Coding from the received frame + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 48 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 48 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 + + +/* Description DOT11AX_RECEIVED_DCM + + This field is only valid for pkt_type == 11ax + + DCM from the received frame + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 49 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 49 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 + + +/* Description DOT11AX_RECEIVED_DOPPLER_INDICATION + + This field is only valid for pkt_type == 11ax + + Doppler_indication from the received frame + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 + + +/* Description DOT11AX_RECEIVED_EXT_RU_SIZE + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be AND dot11ax_su_extended is set + The number of (basic) RUs in this extended range reception + + + RXPCU gets this from the received HE_SIG_A + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 + + +/* Description DOT11AX_DL_UL_FLAG + + This field is only valid for pkt_type == 11ax + + DL_UL_flag to be used for response frame sent to this device. + + + Differentiates between DL and UL transmission + + + + + Note: this setting can also come from response look-up table + in TXPCU... + The selection is SW programmable + + +*/ + +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 55 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 55 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0080000000000000 + + +/* Description RESERVED_11A + + +*/ + +#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_RESERVED_11A_LSB 56 +#define TX_CBF_INFO_RESERVED_11A_MSB 63 +#define TX_CBF_INFO_RESERVED_11A_MASK 0xff00000000000000 + + +/* Description SW_RESPONSE_FRAME_LENGTH + + Field only valid when SW_Response_tlv_from_crypto is set + + + This is the size of the frame (in bytes) that SW will generate + as the response frame. In those scenarios where TXPCU needs + to indicate a frame_length in the PDG_RESPONSE TLV, this + will be the value that TXPCU needs to use. + + Note that this length value includes the FCS. + +*/ + +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x000000000000ffff + + +/* Description SW_RESPONSE_TLV_FROM_CRYPTO + + Field can only be set by MAC mitigation logic + + The idea is here that normally TXPCU generates the response + frame. + But as a backup scenario, in case of a last moment some + CBF frame BA format change happens or there is some other + issue, the CBF frame could be fully generated in the MAC + micro CPU and pushed into TXPCU through the Crypto - TXPCU + TLV interface. + + From TXPCU perspective, all interaction with PDG remains + exactly the same, accept that the frame length is now coming + from field SW_Response_frame_length and the response frame + is pushed into TXPCU over the CRYPTO - TXPCU TLV interface + + + When set, this feature kick in + When clear, this feature is not enabled + +*/ + +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000000010000 + + +/* Description WAIT_SIFS_CONFIG_VALID + + When set, TXPCU shall follow the wait_sifs configuration. + + + +*/ + +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000000020000 + + +/* Description WAIT_SIFS + + Indicates to the TXPCU how precise the SIFS the response + timing shall be... + + The configuration for this is coming from SW programmable + registers in RXPCU, where RXPCU shall allow SW to program + different settings for the following scenarios: BRPOLL, + NDPA-NDP, 11ax trigger frame based BRPOLL + + Transmission shall start with the + normal delay in PHY after receiving this notification + Transmission shall be made + at the SIFS boundary. If shall never start before SIFS boundary, + but if it a little later, it is not ideal and should be + flagged, but transmission shall not be aborted. + Transmission shall be made + at exactly SIFS boundary. If this notification is received + by the PHY after SIFS boundary already passed, the PHY + shall abort the transmission + +*/ + +#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_WAIT_SIFS_LSB 18 +#define TX_CBF_INFO_WAIT_SIFS_MSB 19 +#define TX_CBF_INFO_WAIT_SIFS_MASK 0x00000000000c0000 + + +/* Description RANGING + + 0: This TLV is generated for Tx CBF generation. + 1: TLV is generated due to an active ranging session (.11az). + + +*/ + +#define TX_CBF_INFO_RANGING_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_RANGING_LSB 20 +#define TX_CBF_INFO_RANGING_MSB 20 +#define TX_CBF_INFO_RANGING_MASK 0x0000000000100000 + + +/* Description SECURE + + Field only valid if Ranging is set to 1. + 0: Current ranging session is non-secure. + 1: Current ranging session is secure. + +*/ + +#define TX_CBF_INFO_SECURE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SECURE_LSB 21 +#define TX_CBF_INFO_SECURE_MSB 21 +#define TX_CBF_INFO_SECURE_MASK 0x0000000000200000 + + +/* Description TB_RANGING_RESPONSE_REQUIRED + + Field only valid in case of TB Ranging + + DO NOT USE. + DO NOT USE. + TXPCU to generate TB ranging + NDP in response + +*/ + +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 22 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 23 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000c00000 + + +/* Description RESERVED_12A + + +*/ + +#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_RESERVED_12A_LSB 24 +#define TX_CBF_INFO_RESERVED_12A_MSB 25 +#define TX_CBF_INFO_RESERVED_12A_MASK 0x0000000003000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + This field is only valid if Punctured_response is set + + The 6-bit value used in U-SIG and/or EHT-SIG Common field + for the puncture pattern + +*/ + +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + + +/* Description DOT11BE_PUNCTURE_BITMAP + + This field is only valid if Punctured_response is set + + The bitmap of 20 MHz sub-bands valid in this EHT reception + + + RXPCU gets this from the received U-SIG and/or EHT-SIG via + PHY microcode. + + +*/ + +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 + + +/* Description DOT11BE_RESPONSE + + Indicates that the peer supports .11be response protocols, + e.g. .11be BW indication in scrambler seed, .11be dynamic + BW procedure, punctured response, etc. +*/ + +#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 48 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 48 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 + + +/* Description PUNCTURED_RESPONSE + + Field only valid if Dot11be_response is set + + Indicates that the response shall use preamble puncturing + +*/ + +#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 49 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 49 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 + + +/* Description NPDA_INFO_11BE_VALID + + When set, 11be_NDPA info is valid. + TXPCU will have to trigger the PDG for response transmission + . + + PHY's response will be in 11be format. + +*/ + +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 50 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 50 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x0004000000000000 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 51 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 52 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x0018000000000000 + + +/* Description RESERVED_13A + + +*/ + +#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_RESERVED_13A_LSB 53 +#define TX_CBF_INFO_RESERVED_13A_MSB 63 +#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe0000000000000 + + +/* Description EHT_STA_INFO_39_32 + + Field only valid when Npda_info_11be_valid is set + + The fifth 8 bits of the RAW EHT STA INFO field in the NDPA + frame +*/ + +#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x00000000000000ff + + +/* Description RESERVED_14A + + Can be used for future expansion + +*/ + +#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_RESERVED_14A_LSB 8 +#define TX_CBF_INFO_RESERVED_14A_MSB 31 +#define TX_CBF_INFO_RESERVED_14A_MASK 0x00000000ffffff00 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define TX_CBF_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_TLV64_PADDING_LSB 32 +#define TX_CBF_INFO_TLV64_PADDING_MSB 63 +#define TX_CBF_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // TX_CBF_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_fes_setup.h b/drivers/staging/fw-api/hw/qcn6432/tx_fes_setup.h new file mode 100644 index 0000000000000000000000000000000000000000..e5eb6356218e1542bc4dab42878af2e8b9bda025 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_fes_setup.h @@ -0,0 +1,1593 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_SETUP_H_ +#define _TX_FES_SETUP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_SETUP 10 + +#define NUM_OF_QWORDS_TX_FES_SETUP 5 + + +struct tx_fes_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; // [31:0] + uint32_t fes_in_11ax_trigger_response_config : 1, // [0:0] + bo_based_tid_aggregation_limit : 4, // [4:1] + ranging : 1, // [5:5] + expect_i2r_lmr : 1, // [6:6] + transmit_start_reason : 3, // [9:7] + use_alt_power_sr : 1, // [10:10] + static_2_pwr_mode_status : 1, // [11:11] + obss_srg_opport_transmit_status : 1, // [12:12] + srp_based_transmit_status : 1, // [13:13] + obss_pd_based_transmit_status : 1, // [14:14] + puncture_from_all_allowed_modes : 1, // [15:15] + schedule_cmd_ring_id : 5, // [20:16] + fes_control_mode : 2, // [22:21] + number_of_users : 6, // [28:23] + mu_type : 1, // [29:29] + ofdma_triggered_response : 1, // [30:30] + response_to_response_cmd : 1; // [31:31] + uint32_t schedule_try : 4, // [3:0] + ndp_frame : 2, // [5:4] + txbf : 1, // [6:6] + allow_txop_exceed_in_1st_pkt : 1, // [7:7] + ignore_bw_available : 1, // [8:8] + ignore_tbtt : 1, // [9:9] + static_bandwidth : 3, // [12:10] + set_txop_duration_all_ones : 1, // [13:13] + transmission_contains_mu_rts : 1, // [14:14] + bw_restricted_frames_embedded : 1, // [15:15] + ast_index : 16; // [31:16] + uint32_t cv_id : 8, // [7:0] + trigger_resp_txpdu_ppdu_boundary : 2, // [9:8] + rxpcu_setup_complete_present : 1, // [10:10] + rbo_must_have_data_user_limit : 4, // [14:11] + mu_ndp : 1, // [15:15] + bf_type : 2, // [17:16] + cbf_nc_index_mask : 1, // [18:18] + cbf_nc_index : 3, // [21:19] + cbf_nr_index_mask : 1, // [22:22] + cbf_nr_index : 3, // [25:23] + secure_ranging_ista : 1, // [26:26] + ndpa : 1, // [27:27] + wait_sifs : 2, // [29:28] + cbf_feedback_type_mask : 1, // [30:30] + cbf_feedback_type : 1; // [31:31] + uint32_t cbf_sounding_token : 6, // [5:0] + cbf_sounding_token_mask : 1, // [6:6] + cbf_bw_mask : 1, // [7:7] + cbf_bw : 3, // [10:8] + use_static_bw : 1, // [11:11] + coex_nack_count : 5, // [16:12] + sch_tx_burst_ongoing : 1, // [17:17] + gen_tqm_update_mpdu_count_tlv : 1, // [18:18] + transmit_vif : 4, // [22:19] + optimal_bw_retry_count : 4, // [26:23] + fes_continuation_ratio_threshold : 5; // [31:27] + uint32_t transmit_cca_bitmap : 32; // [31:0] + uint32_t tb_ranging : 1, // [0:0] + ranging_trigger_subtype : 4, // [4:1] + min_cts2self_count : 4, // [8:5] + max_cts2self_count : 4, // [12:9] + wifi_radar_enable : 1, // [13:13] + reserved_6a : 18; // [31:14] + uint32_t monitor_override_sta_31_0 : 32; // [31:0] + uint32_t monitor_override_sta_36_32 : 5, // [4:0] + reserved_8a : 27; // [31:5] + uint32_t fw2sw_info : 32; // [31:0] +#else + uint32_t schedule_id : 32; // [31:0] + uint32_t response_to_response_cmd : 1, // [31:31] + ofdma_triggered_response : 1, // [30:30] + mu_type : 1, // [29:29] + number_of_users : 6, // [28:23] + fes_control_mode : 2, // [22:21] + schedule_cmd_ring_id : 5, // [20:16] + puncture_from_all_allowed_modes : 1, // [15:15] + obss_pd_based_transmit_status : 1, // [14:14] + srp_based_transmit_status : 1, // [13:13] + obss_srg_opport_transmit_status : 1, // [12:12] + static_2_pwr_mode_status : 1, // [11:11] + use_alt_power_sr : 1, // [10:10] + transmit_start_reason : 3, // [9:7] + expect_i2r_lmr : 1, // [6:6] + ranging : 1, // [5:5] + bo_based_tid_aggregation_limit : 4, // [4:1] + fes_in_11ax_trigger_response_config : 1; // [0:0] + uint32_t ast_index : 16, // [31:16] + bw_restricted_frames_embedded : 1, // [15:15] + transmission_contains_mu_rts : 1, // [14:14] + set_txop_duration_all_ones : 1, // [13:13] + static_bandwidth : 3, // [12:10] + ignore_tbtt : 1, // [9:9] + ignore_bw_available : 1, // [8:8] + allow_txop_exceed_in_1st_pkt : 1, // [7:7] + txbf : 1, // [6:6] + ndp_frame : 2, // [5:4] + schedule_try : 4; // [3:0] + uint32_t cbf_feedback_type : 1, // [31:31] + cbf_feedback_type_mask : 1, // [30:30] + wait_sifs : 2, // [29:28] + ndpa : 1, // [27:27] + secure_ranging_ista : 1, // [26:26] + cbf_nr_index : 3, // [25:23] + cbf_nr_index_mask : 1, // [22:22] + cbf_nc_index : 3, // [21:19] + cbf_nc_index_mask : 1, // [18:18] + bf_type : 2, // [17:16] + mu_ndp : 1, // [15:15] + rbo_must_have_data_user_limit : 4, // [14:11] + rxpcu_setup_complete_present : 1, // [10:10] + trigger_resp_txpdu_ppdu_boundary : 2, // [9:8] + cv_id : 8; // [7:0] + uint32_t fes_continuation_ratio_threshold : 5, // [31:27] + optimal_bw_retry_count : 4, // [26:23] + transmit_vif : 4, // [22:19] + gen_tqm_update_mpdu_count_tlv : 1, // [18:18] + sch_tx_burst_ongoing : 1, // [17:17] + coex_nack_count : 5, // [16:12] + use_static_bw : 1, // [11:11] + cbf_bw : 3, // [10:8] + cbf_bw_mask : 1, // [7:7] + cbf_sounding_token_mask : 1, // [6:6] + cbf_sounding_token : 6; // [5:0] + uint32_t transmit_cca_bitmap : 32; // [31:0] + uint32_t reserved_6a : 18, // [31:14] + wifi_radar_enable : 1, // [13:13] + max_cts2self_count : 4, // [12:9] + min_cts2self_count : 4, // [8:5] + ranging_trigger_subtype : 4, // [4:1] + tb_ranging : 1; // [0:0] + uint32_t monitor_override_sta_31_0 : 32; // [31:0] + uint32_t reserved_8a : 27, // [31:5] + monitor_override_sta_36_32 : 5; // [4:0] + uint32_t fw2sw_info : 32; // [31:0] +#endif +}; + + +/* Description SCHEDULE_ID + + Consumer: PDG/TXDMA/TXOLE/TXCRYPTO/TXPCU + Producer: SCH + + This field is overwritten by the scheduler module and it's + value is coming from the"schedule_id" field in the Scheduler + command. + + Configured by scheduler in HW transmit mode + A field that HW copies over into the scheduling status report, + so that SW can determine to which scheduler command the + status report belongs. + This schedule ID is also reported in the PPDU status. + + +*/ + +#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 +#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 +#define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff + + +/* Description FES_IN_11AX_TRIGGER_RESPONSE_CONFIG + + Consumer: PDG/TXPCU + Producer: SW + When set, this scheduler command has some additional settings + that PDG and TXPCU need to take into account, depending + on if the transmission has been iniated as a backoff expiration + or as the result of an 11ax trigger reception. + + 0: not in special trigger response config + 1: command is special trigger response config. + + When set to 1, there are some programming limitations: There + can only be 1 group, up to 8 users, SW shall have specified + the AC for each user, and AC order per user is from BE + to VO + (see PDG_USER_SETUP, fields Triggered_mpdu_AC_category) + + +*/ + +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 + + +/* Description BO_BASED_TID_AGGREGATION_LIMIT + + Consumer: PDG + Producer: SW + + Field only valid when Ofdma_triggered_response is NOT set + (=> implies transmission started due to backoff expiration) + + + Field only valid for SU and "MU_SU" transmissions. + + The requirements for what to transmit depend on what the + reason is that this transmission started. If it is 11ax + trigger based, the trigger frame will specify all the constrains + like max TID count, prefered AC, etc. + However if this command starts executing due to backoff + expiration, the requirements could be different from those + that might have come from the trigger frame. + This field specifies what the constaints are when the transmission + is Backoff initiated. + + If zero, this feature is disabled. + If non-zero, this indicates the number of users within a + group that can be aggregated by a STA in a multi-TID A-MPDU. + This can also be used to block the series of QoS-null MPDUs + when an RBO+Trig queue transmits using RBO. + + Based on this number, PDG will mask of user numbers >= this + count + +*/ + +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 + + +/* Description RANGING + + Consumer: TXPCU + Producer: SW + + Set to 1 in case the frame queued is: + a .11az ranging NDPA, + a .11az ranging NDP, or + an ISTA2RSTA LMR. + Set to 0 for all other cases. +*/ + +#define TX_FES_SETUP_RANGING_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_RANGING_LSB 37 +#define TX_FES_SETUP_RANGING_MSB 37 +#define TX_FES_SETUP_RANGING_MASK 0x0000002000000000 + + +/* Description EXPECT_I2R_LMR + + Consumer: TXPCU + Producer: SW + + Set to 1 in case the frame queued is a .11az randing NDPA/NDP + and if the ISTA2RSTA LMR frame is also queued after SIFS. + + + Set to 0 otherwise. +*/ + +#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 + + +/* Description TRANSMIT_START_REASON + + Indicates what the SCH start reason reason was for initiating + this transmission. + + The transmission of this + PPDU got initiated by the scheduler due to Backoff expiration + + The transmission of + this PPDU got initiated by the scheduler due to reception + (by the SCH) of the TLV RECEIVED_TRIGGER_INFO that RXPCU + generated. Note that this can be an OFDMA trigger frame + based transmission as well as some legacy trigger (PS-POLL, + Qboost, U-APSD, etc.) based transmission + This transmission + of this PPDU got initiated as part of SIFS continuation. + An earlier PPDU was transmitted due to RBO expiration. Next + command is also expected to be transmitted in SIFS burst. + + This transmission + of this PPDU got initiated as part of SIFS continuation + and this is the last command in the burst. An earlier PPDU + was transmitted due to RBO expiration. + DO NOT USE + +*/ + +#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 + + +/* Description USE_ALT_POWER_SR + + 0: Primary/default power1: Alternate power + +*/ + +#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 + + +/* Description STATIC_2_PWR_MODE_STATUS + + 0: Static 2 power mode disabled1: Static 2 power mode enabled + + +*/ + +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 + + +/* Description OBSS_SRG_OPPORT_TRANSMIT_STATUS + + 0: Transmit based on SRG OBSS_PD opportunity initiated1: + Transmit based on non-SRG OBSS_PD opportunity initiated + +*/ + +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 + + +/* Description SRP_BASED_TRANSMIT_STATUS + + 0: non-SRP based transmit initiated1: SRP based transmit + initiated + +*/ + +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 + + +/* Description OBSS_PD_BASED_TRANSMIT_STATUS + + 0: non-OBSS_PD based transmit initiated1: obss_pd based + transmit initiated + +*/ + +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 + + +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 + + +/* Description SCHEDULE_CMD_RING_ID + + Consumer: PDG/TXDMA/TXOLE/TXCRYPTO/TXPCU + Producer: SCH + + This field is overwritten by the scheduler module and its + value is based on the scheduler ring where the command + is initiated. + + The schedule command ring that originated this transmission + + + + + + + + + + + + + + + + + + + + + + + + +*/ + +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 + + +/* Description FES_CONTROL_MODE + + Consumer: PDG/TXDMA/TXOLE/TXCRYPTO/TXPCU + Producer: SCH + + This field is overwritten by the scheduler module and it's + value is coming from the "FES_control_mode" field in the + Scheduler command. + + No HW generated TLVs + PDG is activated to generate + TLVs + + Note: Final Bandwidth selection is always performed by TX + PCU. + +*/ + +#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 +#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 +#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 + + +/* Description NUMBER_OF_USERS + + Consumer: PDG/TXDMA/TXOLE/TXCRYPTO/TXPCU + Producer: SCH + + The number of users in this transmission. Can be MU-MIMO + or OFDMA in case the number is > 1 + +*/ + +#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 +#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 +#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 + + +/* Description MU_TYPE + + In case the Number_of_users > 1, the transmission could + be MU or OFDMA. + This field indicates which one it is. + + 0: MU-MIMO + 1: OFDMA + + + In case the number_of_user == 1, and PDG_FES_SETUP.mu_su_transmission + is set, this field indicates:0: SU transmitted in MU MIMO + format in compressed mode;1: SU transmitted in MU-OFDMA + format in uncompressed mode + + Note: Within OFDMA classification, it could be that within + one or more RUs there will be MIMO transmission...This + is still considered as an 'OFDMA' class of MU transmission. + + + +*/ + +#define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_MU_TYPE_LSB 61 +#define TX_FES_SETUP_MU_TYPE_MSB 61 +#define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 + + +/* Description OFDMA_TRIGGERED_RESPONSE + + Consumer: TXPCU/PDG + Producer: SCH/SW + + SW should always set this bit to 0 + SCH will always overwrite this field and set it to the appropriate + value for the upcoming transmission. + + When set (by SCH), this FES is initiated as a result of + receiving an OFDMA transmit trigger. PDG already has received + all transmit info from RXPCU. PDG can ignore most of the + transmit initialization info. + + +*/ + +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 + + +/* Description RESPONSE_TO_RESPONSE_CMD + + When set, this scheduler command contains the transmission + control for the response_to_response transmission + +*/ + +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 + + +/* Description SCHEDULE_TRY + + Consumer: TXPCU + Producer: SCH + + This field is overwritten by the scheduler module and it's + value is coming from an internal counter in the scheduler + that keeps track of how many times a scheduling command + has been tried. + + This count indicates how many times the FES did not successfully + complete as the ACK/BA frame did not get received. + +*/ + +#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 +#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 +#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f + + +/* Description NDP_FRAME + + Consumer: PDG/TXPCU + Producer: SCH + + When set, the scheduling command contains an NDP frame. + This can only be done using the SW transmit mode. + + No NDP transmission + Beamforming NDP + 11az NDP (HE Ranging NDP) + Short TB (HE Feedback NDP) +*/ + +#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_NDP_FRAME_LSB 4 +#define TX_FES_SETUP_NDP_FRAME_MSB 5 +#define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000000030 + + +/* Description TXBF + + Consumer: PDG/TXPCU + Producer: SCH + + If set, this bit indicates that this is a TX beamformed + SU transaction or MU transaction + + + In case of a beamformed transmission, note that in the PCU_PPDU_SETUP_INIT + TLV, SW can narrow down for which of the BW the beamforming + shall take place. For example, SW can decide that BW is + only desired for 40MHz BW, but not for 20... + If for any of the allowed BW, beamforming is desired, this + field should be set, and the 'bf_type' shall be properly + programmed. + + TXPCU controls with bit 'beamforming' in the MACTX_PRE_PHY_DESC + if the final actual transmission shall be beamformed. +*/ + +#define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TXBF_LSB 6 +#define TX_FES_SETUP_TXBF_MSB 6 +#define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 + + +/* Description ALLOW_TXOP_EXCEED_IN_1ST_PKT + + Consumer: PDG + Producer: SCH + + Field only valid for SU transmissions. + + When set, a single MPDU transmission after RBO is allowed + to exceed TXOP. In this setting, this field has priority + over the setting of the duration_field_boundary. Reason + for this is that if Coex issues on the receiver STA start + preventing the transmission of frames on this device, it + can lead to a death spiral. With some luck, this frame + although maybe too long, might still be received. + + When 0, single MPDU after RBO is not allowed to exceed TXOP. + + +*/ + +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 + + +/* Description IGNORE_BW_AVAILABLE + + Consumer: TXPCU + Producer: SCH + + If set, TXPCU ignores 'BW available signals' from the scheduler + and transmit using the single BW that SW has programmed + the transmission to go out in. This bit should be set for + SIFS response frame to PS-Poll/uAPSD/QBoost and note that + for this mode, SW is only allowed to program a single transmit + BW. + Also note that this bit can not be set in combination with + preamble puncturing. + +*/ + +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 + + +/* Description IGNORE_TBTT + + Consumer: PDG + Producer: SCH + + If set, PDG ignores remaining TBTTs in PPDU time calculation. + + +*/ + +#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 + + +/* Description STATIC_BANDWIDTH + + Consumer: PDG/TXPCU + Producer: SCH + + Field is reserved when use_static_bw is clear. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 + + +/* Description SET_TXOP_DURATION_ALL_ONES + + Consumer: PDG + Producer: SCH + + When set, SW embedded a PS_POLL frame in this transmission + or the frame in this transmission is for a BSS with BSS + Color disabled, e.g. due to BSS color collision. + PDG sets the TXOP_DURATION of the transmit PPDU to all 1s. + + +*/ + +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 + + +/* Description TRANSMISSION_CONTAINS_MU_RTS + + Consumer: PDG + Producer: SCH + + When set, SW embedded a MU-RTS trigger frame in this transmission. + + TXPCU will have to do something special for this with the + CTS response timeout (whose value comes from a MU-CTS timeout + register) + + +*/ + +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 + + +/* Description BW_RESTRICTED_FRAMES_EMBEDDED + + Consumer: TXPCU + Producer: SW + + This bit should be set by SW when the transmission includes + bandwidth restricted frames. As a result of this bit being + set, TXPCU will hold of indicating that buffer space is + available to TXDMA till the BW decision is done. This allows + TXPCU to drop the BW restricted frames at SFM input. + + +*/ + +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 + + +/* Description AST_INDEX + + Consumer: RXPCU + Producer: SCH + + Used for implicit BF sounding capture on receive Ack/BA. + The RXPCU needs to tag the receive sounding with ast_index + so FW will know which STA is associated with Ack/BA sounding. + + + +*/ + +#define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_AST_INDEX_LSB 16 +#define TX_FES_SETUP_AST_INDEX_MSB 31 +#define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 + + +/* Description CV_ID + + Consumer: TXPCU + Producer: SCH + + This field is only valid when expect_cbf is set. + + A unique ID corresponding to the CV data expected from the + CBF frame. + + TXPCU copies this field over to the TX_FES_STATUS TLV + +*/ + +#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CV_ID_LSB 32 +#define TX_FES_SETUP_CV_ID_MSB 39 +#define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 + + +/* Description TRIGGER_RESP_TXPDU_PPDU_BOUNDARY + + This field indicates to TXPCU how far into the 11ax trigger + response transmission, TXPCU should still accept Trigger + response related configuration info from the SCHEDULER (and + PDG) to be processed. + + The field indicates a percentage of the total byte count + to be given to the PHY, up to which point TXPCU will still + accept all the setup related TLVS to arrive. After that, + TXPCU will ignore any remaining setup TLVs to come in and + not initiate any MPDU based transfers to the PHY anymore. + This is to help avoid corner cases. + If any setup TLVs did arrive after this point, TXPCU will + keep on continuing giving NULL data to the PHY, but once + PHYTX_PKT_END is received, TXPCU shall issue a FLUSH request + to the SCH, with flush code: TXPCU_TRIG_RESPONSE_INFO_TOO_LATE + + TXPCU should not abort the transmission halfway, as that + can cause problems for the MU UL receiver... + + TXPCU will not + initiate SCH based MPDU transfers after 75% of the PPDU + octed count has already been given to the PHY. + + TXPCU will not + initiate SCH based MPDU transfers after 50% of the PPDU + octed count has already been given to the PHY. + + TXPCU will not + initiate SCH based MPDU transfers after 75% of the PPDU + octed count has already been given to the PHY. + + Note that if TXPCU receives a TX_FES_SETUP with "11ax trigger + response transmission" set, and it had already finished + sending a response , it should generate a flush with code: + TXPCU_TRIG_RESPONSE_MODE_CORRUPTION + + +*/ + +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 + + +/* Description RXPCU_SETUP_COMPLETE_PRESENT + + To notify current TXFES use new mode and delay "RXPCU_*_SETUP" + for HWSCH/TXPCU/RXPCU module + +*/ + +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 + + +/* Description RBO_MUST_HAVE_DATA_USER_LIMIT + + Consumer: PDG + Producer: SW + + Field only valid when Ofdma_triggered_response is NOT set + (=> implies transmission started due to backoff expiration) + + + Field only valid for SU and "MU_SU" transmissions. + + The requirements for what to transmit depend on what the + reason is that this transmission started. If it is 11ax + trigger based, the trigger frame will specify all the constrains + like max TID count, prefered AC, etc. + However if this command starts executing due to backoff + expiration, the requirements could be different from those + that might have come from the trigger frame. + This field specifies what the constaints are when the transmission + is Backoff initiated. + + When set to 0, this feature is disabled + When set to 1, user 0 must have data otherwise PDG should + flush the transmission + When set to 2, user 0 AND/OR user 1 must have data otherwise + PDG should flush the transmission + When set to 3, user 0 AND/OR user 1 AND/OR user 2 must have + data otherwise PDG should flush the transmission + ... + +*/ + +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 + + +/* Description MU_NDP + + Field only valid when ndp_frame is set. + + If set indicates that this packet is an NDP used for MU + channel estimation. This bit will be used by the TPC to + signal that the analog gain settings can be updated. The + analog gain settings will not change for subsequent MU + data packets. + +*/ + +#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_MU_NDP_LSB 47 +#define TX_FES_SETUP_MU_NDP_MSB 47 +#define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 + + +/* Description BF_TYPE + + Consumer: PDG/TXPCU + Producer: SCH + + Field is ONLY valid when 'txbf' is set... + + Defines the type of beamforming that is required using this + transmission. + Note that in the PCU_PPDU_SETUP_INIT TLV, SW can narrow + down for which BW the beamforming shall take place. For + example, SW can decide that BW is only desired for 40MHz + BW, but not for 20... + If for any of the allowed BW, beamforming is desired, this + field should indicate which type of BF. + + + + + + +*/ + +#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_BF_TYPE_LSB 48 +#define TX_FES_SETUP_BF_TYPE_MSB 49 +#define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 + + +/* Description CBF_NC_INDEX_MASK + + Consumer: TXPCU + Producer: SCH + + When set, TXPCU shall confirm that the received cbf_nc_index + is equal to the expected one, indicated by field: cbf_nc_index + + + This field is only allowed to be set in case of a single + SU CBF reception. + + +*/ + +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 + + +/* Description CBF_NC_INDEX + + Consumer: TXPCU + Producer: SCH + + Field only valid when cbf_nc_index_mask is set + + Expected Nc_index of received CBF frame after sending NDP + or BR-Poll. + + + + + + + + + + +*/ + +#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 +#define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 + + +/* Description CBF_NR_INDEX_MASK + + Consumer: TXPCU + Producer: SCH + + When set, TXPCU shall confirm that the received cbf_nr_index + is equal to the expected one, indicated in the field: cbf_nr_index + + + This field is only allowed to be set in case of a single + SU CBF reception. + +*/ + +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 + + +/* Description CBF_NR_INDEX + + Expected Nr_index of received CBF frame after sending NDP + or BR-Poll. This field is compared only if cbf_nr_index_mask + is set to 1. + + + + + + + + + +*/ + +#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 +#define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 + + +/* Description SECURE_RANGING_ISTA + + Consumer: Crypto + Producer: SW + + If set to 1, Crypto will use the 'TX_PEER_ENTRY' for encryption + but not for the 'TX_DATA' from TXOLE interface but will + wait for 'LMR_{MPDU_START, DATA, MPDU_END}' TLVs from TXPCU + to encrypt the ISTA2RSTA LMR. + + If set to 0, Crypto will encrypt 'TX_DATA' as for any non-.11az-ranging + frame. +*/ + +#define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 58 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 58 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x0400000000000000 + + +/* Description NDPA + + When set, this packet is an NDP announcement. +*/ + +#define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_NDPA_LSB 59 +#define TX_FES_SETUP_NDPA_MSB 59 +#define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 + + +/* Description WAIT_SIFS + + Consumer: TXPCU + Producer: SCH + + This field is passed over to the tx_phy_desc by the PDG + module. If set, the AMPI will hold this tx_phy_desc TLV + from the TX PCU until SIFS has elapsed and then forward + the tx_phy_desc to the PHY. The PHY should ignore this + bit. This bit is used to make sure that transmit SIFS response + to a receive frame is cycle accurate and consistent to + enable accurate RTT measurement. + + Transmission shall start with the + normal delay in PHY after receiving this notification + Transmission shall be made + at the SIFS boundary. If shall never start before SIFS boundary, + but if it a little later, it is not ideal and should be + flagged, but transmission shall not be aborted. + Transmission shall be made + at exactly SIFS boundary. If this notification is received + by the PHY after SIFS boundary already passed, the PHY + shall abort the transmission + +*/ + +#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_WAIT_SIFS_LSB 60 +#define TX_FES_SETUP_WAIT_SIFS_MSB 61 +#define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 + + +/* Description CBF_FEEDBACK_TYPE_MASK + + Consumer: TXPCU + Producer: SCH + + When set, TXPCU shall confirm that the cbf_feedback_type + is equal to the expected one, indicated in the field: cbf_feedback_type + + + This field is only allowed to be set in case of a single + SU CBF reception. + +*/ + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 + + +/* Description CBF_FEEDBACK_TYPE + + Consumer: TXPCU + Producer: SCH + + Expected feedback type of received CBF frame after sending + NDP or BR-Poll. This field is compared only if cbf_feedback_type_mask + is set to 1. + + + +*/ + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 + + +/* Description CBF_SOUNDING_TOKEN + + Consumer: TXPCU + Producer: SCH + + Expected sounding token of received CBF frame after sending + NDP or BR-Poll. This field is compared only if cbf_sounding_token_mask + is set to 1. + +*/ + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f + + +/* Description CBF_SOUNDING_TOKEN_MASK + + Consumer: TXPCU + Producer: SCH + + When set, TXPCU shall confirm that the cbf_sounding_token + is equal to the expected one, indicated in the field: cbf_sounding_token + + + This field is only allowed to be set in case of a single + SU CBF reception. + +*/ + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 + + +/* Description CBF_BW_MASK + + Consumer: TXPCU + Producer: SCH + + When set, TXPCU shall confirm that the cbf_bw_mask is equal + to the expected one, indicated in the field: cbf_bw + + This field is only allowed to be set in case of a single + SU CBF reception. + +*/ + +#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 + + +/* Description CBF_BW + + Consumer: TXPCU + Producer: SCH + + Expected channel width of received CBF frame after sending + NDP or BR-Poll. This field is compared only if cbf_bw_mask + is set to 1. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_BW_LSB 8 +#define TX_FES_SETUP_CBF_BW_MSB 10 +#define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 + + +/* Description USE_STATIC_BW + + Consumer: TXPCU + Producer: SCH + + Part of TX_BF_PARAMS: This field is used to indicate to + the SVD that the b/w that will be defined in the TX_PHY_DESC + for the upcoming TXBF packet will be the same as the static + bandwidth, i.e. the bandwidth that was in operation during + sounding for the clients in question + +*/ + +#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 + + +/* Description COEX_NACK_COUNT + + Consumer: TXPCU + Producer: SCH + + The number of times PDG informed the SCHeduler module that + for this scheduling command, the WLAN transmission can + not be initialized due to getting a NACK response from the + Coex engine, or PDG not being able to fit a transmission + within the timing constraints given by Coex. + + Note that SCH will (re)set this count to 0 at the start + of reading a new SCH command. + This count is maintained on a per ring basis by the SCHeduler + + + +*/ + +#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 +#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 +#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 + + +/* Description SCH_TX_BURST_ONGOING + + Consumer: PDG/TXPCU + Producer: SCH + + This field is overwritten by the scheduler module and it's + value is coming from the" sifs_burst_continuation" field + in the Scheduler command. + + 0: No action + 1: The next scheduling command needs to start at SIFS time + after finishing the frame transmissions in this command. + This allows for SIFS based bursting + +*/ + +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 + + +/* Description GEN_TQM_UPDATE_MPDU_COUNT_TLV + + Consumer: TXPCU + Producer: SW + + NOTE: When PDG is configured to do transmissions in SW mode, + this bit shall NEVER be set. + + When set, TXPCU shall generate the TQM_UPDATE_TX_MPDU_COUNT + TLV immediately after PPDU transmission has finished (and + before any response frame might have been received) + + When set, SW shall also generate the RXPCU_USER_SETUP TLVs + as this is where TXPCU will get the MPDU_queue addresses. + + +*/ + +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 + + +/* Description TRANSMIT_VIF + + Consumer: TXOLE + Producer: SW + + The VIF for this transmission. Used in MCC mode to control/overwrite + the PM bit settings. Based on this VIF value, TXOLE gets + the pm bit control instructions from the pm_state_overwrite_per_vif + register + + +*/ + +#define TX_FES_SETUP_TRANSMIT_VIF_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_TRANSMIT_VIF_LSB 19 +#define TX_FES_SETUP_TRANSMIT_VIF_MSB 22 +#define TX_FES_SETUP_TRANSMIT_VIF_MASK 0x0000000000780000 + + +/* Description OPTIMAL_BW_RETRY_COUNT + + Consumer: TXPCU + Producer: SCH + + This field is overwritten by the scheduler module and it's + value is coming from an internal counter in the scheduler + that keeps track of how many times this scheduling command + has been flushed by TXPCU as a result of most desired BW + not being available (=> flush code: TXPCU_FLREQ_RETRY_FOR_OPTIMAL_BW) + + + For the first transmission, this count is always set to + 0. + +*/ + +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 + + +/* Description FES_CONTINUATION_RATIO_THRESHOLD + + Field evaluated by TXPCU only. + + Field can be used in both SU and MU transmissions, but might + be most useful in MU transmissions. + + TXPCU keeps track of how many MPDU data words are transmited + as well as how many Null delimiters are transmitted. In + case of an MU and/or multi TID transmission, these two + counters are the aggregates over all the users. + + At the end of the FES, TXPCU determines the ratio between + the actual MPDU data words and Null delimiters. If this + ratio is LESS then the ratio indicated here, TXPCU should + indicate "Transmit_data_null_ratio_not_met" in the TX_FES_STATUS_END + + + TXPCU does not need + to do any evaluation on the ratio between actual data transmitted + and NULL delimiters inserted. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 16:1. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 8:1. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 4:1. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 2:1. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 1:1. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 1:2. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 1:4. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 1:8. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 1:16. If not met, TXPCU should terminate FES. + + +*/ + +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 + + +/* Description TRANSMIT_CCA_BITMAP + + The CCA signals that shall be evaluated by TXPCU to determine + the BW/puncture pattern available for transmission. + + 0: CCA signal not needed. Ignore the CCA setting + 1: CCA signals shall be evaluated + + Bit [1:0] => cca20_0 related signals + Bit [3:2] => cca20_1 related signals + ... + Bit [31:30] => cca20_15 related signals + + Within the 2 bits, the order is always: + Bit0: ED + Bit1: GI + + NOTE: HW Sch takes care of MUXing ED1/ED2 with ED0 and MUXing + GI1 with GI0. Hence this field should be set to 0x55555555 + for chips not supporting GI-correlation and 0xFFFFFFFF + for chips that support, usually. + +*/ + +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 + + +/* Description TB_RANGING + + Indicates that this frame is generated for a TB ranging + sequence + +*/ + +#define TX_FES_SETUP_TB_RANGING_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_TB_RANGING_LSB 0 +#define TX_FES_SETUP_TB_RANGING_MSB 0 +#define TX_FES_SETUP_TB_RANGING_MASK 0x0000000000000001 + + +/* Description RANGING_TRIGGER_SUBTYPE + + Field only valid if TB_Ranging is set + + Indicates the Trigger subtype for the current ranging TF + + + + + + + + +*/ + +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000001e + + +/* Description MIN_CTS2SELF_COUNT + + Field only valid when max_cts2self_count is non-zero + + This is the minimum number of CTS2SELF frames that PDG should + transmit before the actual data transmission. +*/ + +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 + + +/* Description MAX_CTS2SELF_COUNT + + Field only valid when non-zero + + This is the maximum number of CTS2SELF frames that PDG is + allowed to transmit before the actual data transmission. + PDG will only use these additional frames if MPDU info from + TQM or CV-correlation info from microcode is delayed. +*/ + +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 + + +/* Description WIFI_RADAR_ENABLE + + When set to 1, the packet is intended to be used by PHY + for WiFi radar (by sensing the reflected WiFi signal). + +*/ + +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 + + +/* Description RESERVED_6A + + Bit 14: cqi_feedback: + Consumer: TXPCU + Producer: SCH + + MSB of the expected feedback type of received CBF frame + after sending NDP or BR-Poll in case of HE/EHT sounding. + See field cbf_feedback_type above for the LSB. This field + is compared only if cbf_feedback_type_mask is set to 1. + + 0: compressed beamforming feedback + 1: CQI feedback + + +*/ + +#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_RESERVED_6A_LSB 14 +#define TX_FES_SETUP_RESERVED_6A_MSB 31 +#define TX_FES_SETUP_RESERVED_6A_MASK 0x00000000ffffc000 + + +/* Description MONITOR_OVERRIDE_STA_31_0 + + Used by TXMON + + LSB 32 bits of a 37-bit user bitmap with 1s denoting the + 'tlv_usr' values that correspond to'Monitor override client's + + + When enabled in TXMON, it will discard the user-TLVs of + the users not selected by the bitmap. FW should program + this setting in line with the 'Monitor_override_sta' setting + in the 'ADDR_SEARCH_ENTRY' corresponding to each of the + clients. + + +*/ + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 + + +/* Description MONITOR_OVERRIDE_STA_36_32 + + Used by TXMON + + MSB 5 bits of a 37-bit user bitmap with 1s denoting the 'tlv_usr' + values that correspond to 'Monitor override client's + + +*/ + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f + + +/* Description RESERVED_8A + + +*/ + +#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_RESERVED_8A_LSB 5 +#define TX_FES_SETUP_RESERVED_8A_MSB 31 +#define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000ffffffe0 + + +/* Description FW2SW_INFO + + This field is provided by FW, to be logged via TXMON to + host SW. It is transparent to HW. + + +*/ + +#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_FW2SW_INFO_LSB 32 +#define TX_FES_SETUP_FW2SW_INFO_MSB 63 +#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 + + + +#endif // TX_FES_SETUP diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_1k_ba.h b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_1k_ba.h new file mode 100644 index 0000000000000000000000000000000000000000..a8e57321e1cf5124c6b3d387620a0b4afc175d2b --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_1k_ba.h @@ -0,0 +1,670 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_1K_BA_H_ +#define _TX_FES_STATUS_1K_BA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 + +#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 + + +struct tx_fes_status_1k_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, // [0:0] + ba_type : 1, // [1:1] + ba_tid : 4, // [5:2] + unexpected_ack_or_ba : 1, // [6:6] + response_timeout : 1, // [7:7] + ack_frame_rssi : 8, // [15:8] + ssn : 12, // [27:16] + reserved_0b : 4; // [31:28] + uint32_t sw_peer_id : 16, // [15:0] + reserved_1a : 16; // [31:16] + uint32_t ba_bitmap_31_0 : 32; // [31:0] + uint32_t ba_bitmap_63_32 : 32; // [31:0] + uint32_t ba_bitmap_95_64 : 32; // [31:0] + uint32_t ba_bitmap_127_96 : 32; // [31:0] + uint32_t ba_bitmap_159_128 : 32; // [31:0] + uint32_t ba_bitmap_191_160 : 32; // [31:0] + uint32_t ba_bitmap_223_192 : 32; // [31:0] + uint32_t ba_bitmap_255_224 : 32; // [31:0] + uint32_t ba_bitmap_287_256 : 32; // [31:0] + uint32_t ba_bitmap_319_288 : 32; // [31:0] + uint32_t ba_bitmap_351_320 : 32; // [31:0] + uint32_t ba_bitmap_383_352 : 32; // [31:0] + uint32_t ba_bitmap_415_384 : 32; // [31:0] + uint32_t ba_bitmap_447_416 : 32; // [31:0] + uint32_t ba_bitmap_479_448 : 32; // [31:0] + uint32_t ba_bitmap_511_480 : 32; // [31:0] + uint32_t ba_bitmap_543_512 : 32; // [31:0] + uint32_t ba_bitmap_575_544 : 32; // [31:0] + uint32_t ba_bitmap_607_576 : 32; // [31:0] + uint32_t ba_bitmap_639_608 : 32; // [31:0] + uint32_t ba_bitmap_671_640 : 32; // [31:0] + uint32_t ba_bitmap_703_672 : 32; // [31:0] + uint32_t ba_bitmap_735_704 : 32; // [31:0] + uint32_t ba_bitmap_767_736 : 32; // [31:0] + uint32_t ba_bitmap_799_768 : 32; // [31:0] + uint32_t ba_bitmap_831_800 : 32; // [31:0] + uint32_t ba_bitmap_863_832 : 32; // [31:0] + uint32_t ba_bitmap_895_864 : 32; // [31:0] + uint32_t ba_bitmap_927_896 : 32; // [31:0] + uint32_t ba_bitmap_959_928 : 32; // [31:0] + uint32_t ba_bitmap_991_960 : 32; // [31:0] + uint32_t ba_bitmap_1023_992 : 32; // [31:0] +#else + uint32_t reserved_0b : 4, // [31:28] + ssn : 12, // [27:16] + ack_frame_rssi : 8, // [15:8] + response_timeout : 1, // [7:7] + unexpected_ack_or_ba : 1, // [6:6] + ba_tid : 4, // [5:2] + ba_type : 1, // [1:1] + ack_ba_status_type : 1; // [0:0] + uint32_t reserved_1a : 16, // [31:16] + sw_peer_id : 16; // [15:0] + uint32_t ba_bitmap_31_0 : 32; // [31:0] + uint32_t ba_bitmap_63_32 : 32; // [31:0] + uint32_t ba_bitmap_95_64 : 32; // [31:0] + uint32_t ba_bitmap_127_96 : 32; // [31:0] + uint32_t ba_bitmap_159_128 : 32; // [31:0] + uint32_t ba_bitmap_191_160 : 32; // [31:0] + uint32_t ba_bitmap_223_192 : 32; // [31:0] + uint32_t ba_bitmap_255_224 : 32; // [31:0] + uint32_t ba_bitmap_287_256 : 32; // [31:0] + uint32_t ba_bitmap_319_288 : 32; // [31:0] + uint32_t ba_bitmap_351_320 : 32; // [31:0] + uint32_t ba_bitmap_383_352 : 32; // [31:0] + uint32_t ba_bitmap_415_384 : 32; // [31:0] + uint32_t ba_bitmap_447_416 : 32; // [31:0] + uint32_t ba_bitmap_479_448 : 32; // [31:0] + uint32_t ba_bitmap_511_480 : 32; // [31:0] + uint32_t ba_bitmap_543_512 : 32; // [31:0] + uint32_t ba_bitmap_575_544 : 32; // [31:0] + uint32_t ba_bitmap_607_576 : 32; // [31:0] + uint32_t ba_bitmap_639_608 : 32; // [31:0] + uint32_t ba_bitmap_671_640 : 32; // [31:0] + uint32_t ba_bitmap_703_672 : 32; // [31:0] + uint32_t ba_bitmap_735_704 : 32; // [31:0] + uint32_t ba_bitmap_767_736 : 32; // [31:0] + uint32_t ba_bitmap_799_768 : 32; // [31:0] + uint32_t ba_bitmap_831_800 : 32; // [31:0] + uint32_t ba_bitmap_863_832 : 32; // [31:0] + uint32_t ba_bitmap_895_864 : 32; // [31:0] + uint32_t ba_bitmap_927_896 : 32; // [31:0] + uint32_t ba_bitmap_959_928 : 32; // [31:0] + uint32_t ba_bitmap_991_960 : 32; // [31:0] + uint32_t ba_bitmap_1023_992 : 32; // [31:0] +#endif +}; + + +/* Description ACK_BA_STATUS_TYPE + + Consumer: SW + Producer: RXPCU + + This TLV represents an BA reception. + + +*/ + +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 + + +/* Description BA_TYPE + + + +*/ + +#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 + + +/* Description BA_TID + + The TID field copied from the BA frame + +*/ + +#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c + + +/* Description UNEXPECTED_ACK_OR_BA + + Set when RXPCU received a BA for which there was no " RXPCU_USER_SETUP_EXT + TLV' received. + This can happen when a BA for unexpected TID is received. + + + This message enables SW to still pass this BA information + on to the right TQM queue. + +*/ + +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 + + +/* Description RESPONSE_TIMEOUT + + When set, there was delay in RXPCU (likely due to AST fetch + delay) that resulted in TXPCU not being able to send the + RX_RESPONSE_REQUIRED_INFO TLV within a certain timeout + from the falling edge of the frame. This status TLV is still + generated but RXPCU will NOT have generated the RX_RESPONSE_REQUIRED + TLV. + +*/ + +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 + + +/* Description ACK_FRAME_RSSI + + RSSI of the received ACK, BA or M-BA frame. + + +*/ + +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 + + +/* Description SSN + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Ack_ba_status_type indicating: + BA_type + + The starting Sequence number of the (B)ACK bitmap +*/ + +#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_SSN_LSB 16 +#define TX_FES_STATUS_1K_BA_SSN_MSB 27 +#define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 + + +/* Description RESERVED_0B + + +*/ + +#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 + + +/* Description SW_PEER_ID + + The sw_peer_id for which the bitmap is requested. + + SW could use this info to link this TLV back to the right + TQM queue (if needed) + +*/ + +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 + + +/* Description BA_BITMAP_31_0 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_31_0 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_63_32 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_63_32 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_95_64 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_95_64 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_127_96 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_127_96 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_159_128 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_159_128 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_191_160 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_191_160 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_223_192 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_223_192 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_255_224 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_255_224 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_287_256 + + Ba_bitmap_287_256 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_319_288 + + Ba_bitmap_319_288 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_351_320 + + Ba_bitmap_351_320 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_383_352 + + Ba_bitmap_383_352 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_415_384 + + Ba_bitmap_415_384 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_447_416 + + Ba_bitmap_447_416 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_479_448 + + Ba_bitmap_479_448 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_511_480 + + Ba_bitmap_511_480 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_543_512 + + Ba_bitmap_543_512 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_575_544 + + Ba_bitmap_575_544 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_607_576 + + Ba_bitmap_607_576 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_639_608 + + Ba_bitmap_639_608 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_671_640 + + Ba_bitmap_671_640 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_703_672 + + Ba_bitmap_703_672 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_735_704 + + Ba_bitmap_735_704 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_767_736 + + Ba_bitmap_767_736 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_799_768 + + Ba_bitmap_799_768 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_831_800 + + Ba_bitmap_831_800 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_863_832 + + Ba_bitmap_863_832 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_895_864 + + Ba_bitmap_895_864 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_927_896 + + Ba_bitmap_927_896 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_959_928 + + Ba_bitmap_959_928 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_991_960 + + Ba_bitmap_991_960 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_1023_992 + + Ba_bitmap_1023_992 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 + + + +#endif // TX_FES_STATUS_1K_BA diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_ack_or_ba.h b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_ack_or_ba.h new file mode 100644 index 0000000000000000000000000000000000000000..989fa6fa45ec25670c4de39b9ed3e975c60cdb4e --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_ack_or_ba.h @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ +#define _TX_FES_STATUS_ACK_OR_BA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 + +#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5 + + +struct tx_fes_status_ack_or_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, // [0:0] + ba_type : 1, // [1:1] + ba_tid : 4, // [5:2] + unexpected_ack_or_ba : 1, // [6:6] + response_timeout : 1, // [7:7] + ack_frame_rssi : 8, // [15:8] + ssn : 12, // [27:16] + reserved_0b : 4; // [31:28] + uint32_t sw_peer_id : 16, // [15:0] + reserved_1a : 16; // [31:16] + uint32_t ba_bitmap_31_0 : 32; // [31:0] + uint32_t ba_bitmap_63_32 : 32; // [31:0] + uint32_t ba_bitmap_95_64 : 32; // [31:0] + uint32_t ba_bitmap_127_96 : 32; // [31:0] + uint32_t ba_bitmap_159_128 : 32; // [31:0] + uint32_t ba_bitmap_191_160 : 32; // [31:0] + uint32_t ba_bitmap_223_192 : 32; // [31:0] + uint32_t ba_bitmap_255_224 : 32; // [31:0] +#else + uint32_t reserved_0b : 4, // [31:28] + ssn : 12, // [27:16] + ack_frame_rssi : 8, // [15:8] + response_timeout : 1, // [7:7] + unexpected_ack_or_ba : 1, // [6:6] + ba_tid : 4, // [5:2] + ba_type : 1, // [1:1] + ack_ba_status_type : 1; // [0:0] + uint32_t reserved_1a : 16, // [31:16] + sw_peer_id : 16; // [15:0] + uint32_t ba_bitmap_31_0 : 32; // [31:0] + uint32_t ba_bitmap_63_32 : 32; // [31:0] + uint32_t ba_bitmap_95_64 : 32; // [31:0] + uint32_t ba_bitmap_127_96 : 32; // [31:0] + uint32_t ba_bitmap_159_128 : 32; // [31:0] + uint32_t ba_bitmap_191_160 : 32; // [31:0] + uint32_t ba_bitmap_223_192 : 32; // [31:0] + uint32_t ba_bitmap_255_224 : 32; // [31:0] +#endif +}; + + +/* Description ACK_BA_STATUS_TYPE + + Consumer: SW + Producer: RXPCU + + This TLV represents an ACK reception. + + This TLV represents an BA reception. + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 + + +/* Description BA_TYPE + + Field only valid when Ack_ba_status_type == BA_type + + + + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x0000000000000002 + + +/* Description BA_TID + + Field only valid when Ack_ba_status_type == BA_type + + The TID field copied from the BA frame + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x000000000000003c + + +/* Description UNEXPECTED_ACK_OR_BA + + Set when RXPCU received a BA for which there was no " RXPCU_USER_SETUP_EXT + TLV' received. + This can happen when a BA for unexpected TID is received. + + + This message enables SW to still pass this BA information + on to the right TQM queue. + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 + + +/* Description RESPONSE_TIMEOUT + + When set, there was delay in RXPCU (likely due to AST fetch + delay) that resulted in TXPCU not being able to send the + RX_RESPONSE_REQUIRED_INFO TLV within a certain timeout + from the falling edge of the frame. This status TLV is still + generated but RXPCU will NOT have generated the RX_RESPONSE_REQUIRED + TLV. + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 + + +/* Description ACK_FRAME_RSSI + + RSSI of the received ACK, BA or M-BA frame. + + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 + + +/* Description SSN + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Ack_ba_status_type indicating: + BA_type + + The starting Sequence number of the (B)ACK bitmap +*/ + +#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x000000000fff0000 + + +/* Description RESERVED_0B + + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0x00000000f0000000 + + +/* Description SW_PEER_ID + + The sw_peer_id for which the bitmap is requested. + + SW could use this info to link this TLV back to the right + TQM queue (if needed) + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 47 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 48 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff000000000000 + + +/* Description BA_BITMAP_31_0 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Ack_ba_status_type indicating: + BA_type + + Ba_bitmap_31_0 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_63_32 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Ack_ba_status_type indicating: + BA_type + + Ba_bitmap_63_32 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_95_64 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Remove_acked_cmd_type + indicating: + remove_Block_Acked_mpdus + + Ba_bitmap_95_64 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_127_96 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Remove_acked_cmd_type + indicating: + remove_Block_Acked_mpdus + + Ba_bitmap_127_96 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_159_128 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Remove_acked_cmd_type + indicating: + remove_Block_Acked_mpdus + + Ba_bitmap_159_128 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_191_160 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Remove_acked_cmd_type + indicating: + remove_Block_Acked_mpdus + + Ba_bitmap_191_160 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_223_192 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Remove_acked_cmd_type + indicating: + remove_Block_Acked_mpdus + + Ba_bitmap_223_192 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_255_224 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Remove_acked_cmd_type + indicating: + remove_Block_Acked_mpdus + + Ba_bitmap_255_224 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 + + + +#endif // TX_FES_STATUS_ACK_OR_BA diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_end.h b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_end.h new file mode 100644 index 0000000000000000000000000000000000000000..9f0a81e0b805f600c3916ec7b5c6b18051218f17 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_end.h @@ -0,0 +1,2198 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_END_H_ +#define _TX_FES_STATUS_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_END 22 + +#define NUM_OF_QWORDS_TX_FES_STATUS_END 11 + + +struct tx_fes_status_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_coex_bt_tx_while_wlan_tx : 1, // [0:0] + prot_coex_bt_tx_while_wlan_rx : 1, // [1:1] + prot_coex_wan_tx_while_wlan_tx : 1, // [2:2] + prot_coex_wan_tx_while_wlan_rx : 1, // [3:3] + prot_coex_wlan_tx_while_wlan_tx : 1, // [4:4] + prot_coex_wlan_tx_while_wlan_rx : 1, // [5:5] + coex_bt_tx_while_wlan_tx : 1, // [6:6] + coex_bt_tx_while_wlan_rx : 1, // [7:7] + coex_wan_tx_while_wlan_tx : 1, // [8:8] + coex_wan_tx_while_wlan_rx : 1, // [9:9] + coex_wlan_tx_while_wlan_tx : 1, // [10:10] + coex_wlan_tx_while_wlan_rx : 1, // [11:11] + global_data_underflow_warning : 1, // [12:12] + global_fes_transmit_result : 4, // [16:13] + cbf_bw_received_valid : 1, // [17:17] + cbf_bw_received : 3, // [20:18] + actual_received_ack_type : 4, // [24:21] + sta_response_count : 6, // [30:25] + dpdtrain_done : 1; // [31:31] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 4, // [19:16] + brp_info_valid : 1, // [20:20] + reserved_1a : 6, // [26:21] + phytx_pkt_end_info_valid : 1, // [27:27] + phytx_abort_request_info_valid : 1, // [28:28] + fes_in_11ax_trigger_response_config : 1, // [29:29] + null_delim_inserted_before_mpdus : 1, // [30:30] + only_null_delim_sent : 1; // [31:31] + uint32_t start_of_frame_timestamp_15_0 : 16, // [15:0] + start_of_frame_timestamp_31_16 : 16; // [31:16] + uint32_t end_of_frame_timestamp_15_0 : 16, // [15:0] + end_of_frame_timestamp_31_16 : 16; // [31:16] + uint32_t terminate_ranging_sequence : 1, // [0:0] + reserved_4a : 7, // [7:1] + timing_status : 2, // [9:8] + response_type : 5, // [14:10] + r2r_end_status_to_follow : 1, // [15:15] + transmit_delay : 16; // [31:16] + uint32_t tx_group_delay : 12, // [11:0] + reserved_5a : 4, // [15:12] + tpc_dbg_info_cmn_15_0 : 16; // [31:16] + uint32_t tpc_dbg_info_cmn_31_16 : 16, // [15:0] + tpc_dbg_info_47_32 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_15_0 : 16, // [15:0] + tpc_dbg_info_chn1_31_16 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_47_32 : 16, // [15:0] + tpc_dbg_info_chn1_63_48 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_79_64 : 16, // [15:0] + tpc_dbg_info_chn2_15_0 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_31_16 : 16, // [15:0] + tpc_dbg_info_chn2_47_32 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_63_48 : 16, // [15:0] + tpc_dbg_info_chn2_79_64 : 16; // [31:16] + uint32_t phytx_tx_end_sw_info_15_0 : 16, // [15:0] + phytx_tx_end_sw_info_31_16 : 16; // [31:16] + uint32_t phytx_tx_end_sw_info_47_32 : 16, // [15:0] + phytx_tx_end_sw_info_63_48 : 16; // [31:16] + uint32_t beamform_masked_user_bitmap_15_0 : 16, // [15:0] + beamform_masked_user_bitmap_31_16 : 16; // [31:16] + uint32_t cbf_segment_request_mask : 8, // [7:0] + cbf_segment_sent_mask : 8, // [15:8] + highest_achieved_data_null_ratio : 5, // [20:16] + use_alt_power_sr : 1, // [21:21] + static_2_pwr_mode_status : 1, // [22:22] + obss_srg_opport_transmit_status : 1, // [23:23] + srp_based_transmit_status : 1, // [24:24] + obss_pd_based_transmit_status : 1, // [25:25] + beamform_masked_user_bitmap_36_32 : 5, // [30:26] + pdg_mpdu_ready : 1; // [31:31] + uint32_t pdg_mpdu_count : 16, // [15:0] + pdg_est_mpdu_tx_count : 16; // [31:16] + uint32_t pdg_overview_length : 24, // [23:0] + txop_duration : 7, // [30:24] + pdg_dropped_mpdu_warning : 1; // [31:31] + uint32_t packet_extension_a_factor : 2, // [1:0] + packet_extension_pe_disambiguity : 1, // [2:2] + packet_extension : 3, // [5:3] + fec_type : 1, // [6:6] + stbc : 1, // [7:7] + num_data_symbols : 16, // [23:8] + ru_size : 4, // [27:24] + reserved_17a : 4; // [31:28] + uint32_t num_ltf_symbols : 3, // [2:0] + ltf_size : 2, // [4:3] + cp_setting : 2, // [6:5] + reserved_18a : 5, // [11:7] + dcm : 1, // [12:12] + ldpc_extra_symbol : 1, // [13:13] + force_extra_symbol : 1, // [14:14] + reserved_18b : 1, // [15:15] + tx_pwr_shared : 8, // [23:16] + tx_pwr_unshared : 8; // [31:24] + uint32_t ranging_active_user_map : 16, // [15:0] + ranging_sent_dummy_tx : 1, // [16:16] + ranging_ftm_frame_sent : 1, // [17:17] + reserved_20a : 6, // [23:18] + cv_corr_status : 8; // [31:24] + uint32_t current_tx_duration : 16, // [15:0] + reserved_21a : 16; // [31:16] +#else + uint32_t dpdtrain_done : 1, // [31:31] + sta_response_count : 6, // [30:25] + actual_received_ack_type : 4, // [24:21] + cbf_bw_received : 3, // [20:18] + cbf_bw_received_valid : 1, // [17:17] + global_fes_transmit_result : 4, // [16:13] + global_data_underflow_warning : 1, // [12:12] + coex_wlan_tx_while_wlan_rx : 1, // [11:11] + coex_wlan_tx_while_wlan_tx : 1, // [10:10] + coex_wan_tx_while_wlan_rx : 1, // [9:9] + coex_wan_tx_while_wlan_tx : 1, // [8:8] + coex_bt_tx_while_wlan_rx : 1, // [7:7] + coex_bt_tx_while_wlan_tx : 1, // [6:6] + prot_coex_wlan_tx_while_wlan_rx : 1, // [5:5] + prot_coex_wlan_tx_while_wlan_tx : 1, // [4:4] + prot_coex_wan_tx_while_wlan_rx : 1, // [3:3] + prot_coex_wan_tx_while_wlan_tx : 1, // [2:2] + prot_coex_bt_tx_while_wlan_rx : 1, // [1:1] + prot_coex_bt_tx_while_wlan_tx : 1; // [0:0] + uint32_t only_null_delim_sent : 1, // [31:31] + null_delim_inserted_before_mpdus : 1, // [30:30] + fes_in_11ax_trigger_response_config : 1, // [29:29] + phytx_abort_request_info_valid : 1, // [28:28] + phytx_pkt_end_info_valid : 1, // [27:27] + reserved_1a : 6, // [26:21] + brp_info_valid : 1, // [20:20] + reserved_after_struct16 : 4; // [19:16] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t start_of_frame_timestamp_31_16 : 16, // [31:16] + start_of_frame_timestamp_15_0 : 16; // [15:0] + uint32_t end_of_frame_timestamp_31_16 : 16, // [31:16] + end_of_frame_timestamp_15_0 : 16; // [15:0] + uint32_t transmit_delay : 16, // [31:16] + r2r_end_status_to_follow : 1, // [15:15] + response_type : 5, // [14:10] + timing_status : 2, // [9:8] + reserved_4a : 7, // [7:1] + terminate_ranging_sequence : 1; // [0:0] + uint32_t tpc_dbg_info_cmn_15_0 : 16, // [31:16] + reserved_5a : 4, // [15:12] + tx_group_delay : 12; // [11:0] + uint32_t tpc_dbg_info_47_32 : 16, // [31:16] + tpc_dbg_info_cmn_31_16 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_31_16 : 16, // [31:16] + tpc_dbg_info_chn1_15_0 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_63_48 : 16, // [31:16] + tpc_dbg_info_chn1_47_32 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_15_0 : 16, // [31:16] + tpc_dbg_info_chn1_79_64 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_47_32 : 16, // [31:16] + tpc_dbg_info_chn2_31_16 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_79_64 : 16, // [31:16] + tpc_dbg_info_chn2_63_48 : 16; // [15:0] + uint32_t phytx_tx_end_sw_info_31_16 : 16, // [31:16] + phytx_tx_end_sw_info_15_0 : 16; // [15:0] + uint32_t phytx_tx_end_sw_info_63_48 : 16, // [31:16] + phytx_tx_end_sw_info_47_32 : 16; // [15:0] + uint32_t beamform_masked_user_bitmap_31_16 : 16, // [31:16] + beamform_masked_user_bitmap_15_0 : 16; // [15:0] + uint32_t pdg_mpdu_ready : 1, // [31:31] + beamform_masked_user_bitmap_36_32 : 5, // [30:26] + obss_pd_based_transmit_status : 1, // [25:25] + srp_based_transmit_status : 1, // [24:24] + obss_srg_opport_transmit_status : 1, // [23:23] + static_2_pwr_mode_status : 1, // [22:22] + use_alt_power_sr : 1, // [21:21] + highest_achieved_data_null_ratio : 5, // [20:16] + cbf_segment_sent_mask : 8, // [15:8] + cbf_segment_request_mask : 8; // [7:0] + uint32_t pdg_est_mpdu_tx_count : 16, // [31:16] + pdg_mpdu_count : 16; // [15:0] + uint32_t pdg_dropped_mpdu_warning : 1, // [31:31] + txop_duration : 7, // [30:24] + pdg_overview_length : 24; // [23:0] + uint32_t reserved_17a : 4, // [31:28] + ru_size : 4, // [27:24] + num_data_symbols : 16, // [23:8] + stbc : 1, // [7:7] + fec_type : 1, // [6:6] + packet_extension : 3, // [5:3] + packet_extension_pe_disambiguity : 1, // [2:2] + packet_extension_a_factor : 2; // [1:0] + uint32_t tx_pwr_unshared : 8, // [31:24] + tx_pwr_shared : 8, // [23:16] + reserved_18b : 1, // [15:15] + force_extra_symbol : 1, // [14:14] + ldpc_extra_symbol : 1, // [13:13] + dcm : 1, // [12:12] + reserved_18a : 5, // [11:7] + cp_setting : 2, // [6:5] + ltf_size : 2, // [4:3] + num_ltf_symbols : 3; // [2:0] + uint32_t cv_corr_status : 8, // [31:24] + reserved_20a : 6, // [23:18] + ranging_ftm_frame_sent : 1, // [17:17] + ranging_sent_dummy_tx : 1, // [16:16] + ranging_active_user_map : 16; // [15:0] + uint32_t reserved_21a : 16, // [31:16] + current_tx_duration : 16; // [15:0] +#endif +}; + + +/* Description PROT_COEX_BT_TX_WHILE_WLAN_TX + + When set, a BT tx coex event started while wlan was in the + middle of TX a transmission. + + Field set when coex_status_broadcast TLV received with bt + tx activity set and during WLAN tx + +*/ + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 + + +/* Description PROT_COEX_BT_TX_WHILE_WLAN_RX + + When set, a BT tx coex event started while wlan was in the + middle of TX a transmission. + + Field set when coex broadcast TLV received with bt tx activity + set and during WLAN rx + +*/ + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000002 + + +/* Description PROT_COEX_WAN_TX_WHILE_WLAN_TX + + When set, a WAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex_status_broadcast TLV received with WAN + tx activity set and during WLAN tx + +*/ + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 + + +/* Description PROT_COEX_WAN_TX_WHILE_WLAN_RX + + When set, a WAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex broadcast TLV received with WAN tx activity + set and during WLAN rx + +*/ + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000008 + + +/* Description PROT_COEX_WLAN_TX_WHILE_WLAN_TX + + When set, a WLAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex_status_broadcast TLV received with WLAN + tx activity set and during WLAN tx + +*/ + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000010 + + +/* Description PROT_COEX_WLAN_TX_WHILE_WLAN_RX + + When set, a WLAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex broadcast TLV received with WLAN tx + activity set and during WLAN rx + +*/ + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000020 + + +/* Description COEX_BT_TX_WHILE_WLAN_TX + + When set, a BT tx coex event started while wlan was in the + middle of TX a transmission. + + Field set when coex_status_broadcast TLV received with bt + tx activity set and during WLAN tx + +*/ + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000040 + + +/* Description COEX_BT_TX_WHILE_WLAN_RX + + When set, a BT tx coex event started while wlan was in the + middle of TX a transmission. + + Field set when coex broadcast TLV received with bt tx activity + set and during WLAN rx + +*/ + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000080 + + +/* Description COEX_WAN_TX_WHILE_WLAN_TX + + When set, a WAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex_status_broadcast TLV received with WAN + tx activity set and during WLAN tx + +*/ + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000100 + + +/* Description COEX_WAN_TX_WHILE_WLAN_RX + + When set, a WAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex broadcast TLV received with WAN tx activity + set and during WLAN rx + +*/ + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000200 + + +/* Description COEX_WLAN_TX_WHILE_WLAN_TX + + When set, a WLAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex_status_broadcast TLV received with WLAN + tx activity set and during WLAN tx + +*/ + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000400 + + +/* Description COEX_WLAN_TX_WHILE_WLAN_RX + + When set, a WLAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex broadcast TLV received with WLAN tx + activity set and during WLAN rx + +*/ + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000800 + + +/* Description GLOBAL_DATA_UNDERFLOW_WARNING + + Consumer: SCH/SW + Producer: TXPCU + + When set, during transmission a data underflow occurred + for one or more users. +*/ + +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 + + +/* Description GLOBAL_FES_TRANSMIT_RESULT + + Consumer: SCH/SW + Producer: TXPCU + + Global Transmit result, not per USER transmit result + + Note: field "Response_type" indicates if the expected response + was MU related or not. + + Successful transmission of entire Frame exchange + sequence + + No Protection response frame received so timeout is triggered. + + No PPDU response frame received + so timeout is triggered. + Response frame was received + with an invalid FCS. + Response frame is received + without CRC error but it's not matched with expected SU_Response_type. + + Set if CBF is received without + any error but the Nr, Nc, BW, type or token in VHT MIMO + control field is not matched with expected values which + are specified by TX_FES_SETUP.cbf_* fields. + Response frame is received + without CRC error but it's not matched with expected SU_Response_type. + + For this user, no MPDU + was received at all, or all received MPDUs had an FCS error. + + An MU UL response + reception was expected. That response came but the threshold + for number of successful user receptions was not met. + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + transmission + was successful and proper responses have been received. + But the required ratio between useful MPDU data and null + delimiters was not met as specified by field : Fes_continuation_ratio_threshold. + The FES (and potentially the SIFS burst) shall be terminated + by the SCHeduler + NOTE 1: This e-num will only be used in the TX_FES_STATUS_END + TLV... + + A TB ranging response was + expected for a sounding TF, but the response did not arrive + and timeout is triggered. + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + A TB ranging response + was expected for a sounding TF, but the reception did not + match the expected response. + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + + +*/ + +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 + + +/* Description CBF_BW_RECEIVED_VALID + + Field only valid in case of SU reception. + In MU set to 0 + + When set, the cbf_bw_received field contains valid info +*/ + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 + + +/* Description CBF_BW_RECEIVED + + Field only valid when cbf_bw_received_valid is set. + + In MU set to 0 + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 + + +/* Description ACTUAL_RECEIVED_ACK_TYPE + + Field only valid in case of SU reception. + In MU set to 0 + + + Field indicates what type of ACK was received. Can help + determine if unexpected ACK Types (like 256 BA instead of + 64 BA) is received. + + No ACK type response was received + or expected + a basic ACk frame is received + + An ACK embedded in BA frame is received + + a 32 bit BA has been received + + a 64 bit BA has been received + + a 128 bit BA has been received + + + a 256 bit BA has been received + + a 512-bit BA has been received + + a 1024-bit BA has been received + + multiple BA responses + have been received. This field to be used in scenarios + where multi TID data was send or data with management frames + was send + + +*/ + +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 + + +/* Description STA_RESPONSE_COUNT + + In of case of a transmission where a response from multiple + STAs in SIFS time is expected, this field indicates how + many STAs actually send a response. + + +*/ + +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 + + +/* Description DPDTRAIN_DONE + + Field only valid when PHYTX_PKT_END_info_valid is set + + For DPD Training packets, this bit is set to indicate that + DPD Training was successfully run to completion. Also + reused by Implicit BF Calibration Packets. This bit is intended + for debug purposes. + +*/ + +#define TX_FES_STATUS_END_DPDTRAIN_DONE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_LSB 31 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_MSB 31 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_MASK 0x0000000080000000 + + +/* Description PHYTX_ABORT_REQUEST_INFO_DETAILS + + Field only valid when PHYTX_ABORT_REQUEST_info_valid is + set + + The reason why PHYTX is requested an abort +*/ + + +/* Description PHYTX_ABORT_REASON + + Reason for early termination of TX packet by the PHY + + +*/ + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + + +/* Description USER_NUMBER + + For some errors, the user for which this error was detected + can be indicated in this field. + +*/ + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + + +/* Description RESERVED + + +*/ + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + + +/* Description RESERVED_AFTER_STRUCT16 + + +*/ + +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 + + +/* Description BRP_INFO_VALID + + When set, TXPCU sent CBF segments. + + Fields cbf_segment_request_mask and cbf_segment_sent_mask + contain valid info. + + +*/ + +#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_RESERVED_1A_LSB 53 +#define TX_FES_STATUS_END_RESERVED_1A_MSB 58 +#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07e0000000000000 + + +/* Description PHYTX_PKT_END_INFO_VALID + + All the fields originating from PHYTX_PKT_END TLV contain + valid info +*/ + +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 + + +/* Description PHYTX_ABORT_REQUEST_INFO_VALID + + Field Phytx_abort_request_info_details contains valid info + +*/ + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 + + +/* Description FES_IN_11AX_TRIGGER_RESPONSE_CONFIG + + When set, this transmission was the result of responding + to the reception of an 11ax trigger. This is a copy of + field Fes_in_11ax_Trigger_response_config in the TX_FES_SETUP + TLV. + +*/ + +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 + + +/* Description NULL_DELIM_INSERTED_BEFORE_MPDUS + + Field only valid when "Fes_in_11ax_Trigger_response_config" + is set. + + This bit will get set if any NULL delimiter is sent out + to PHY, during the whole transmit duration(self_gen + FES). + + This bit will NOT be set, if no MPDU data is sent out to + PHY and whole transmit duration is filled with NULL delimiters. + + + Note that SCH does not evaluate this field. It is only for + SW to look at. + + +*/ + +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 + + +/* Description ONLY_NULL_DELIM_SENT + + Field only valid when "Fes_in_11ax_Trigger_response_config" + is set. + + This bit will be set if only NULL delimiters are sent to + the PHY and no SCH sourced MPDU data is sent out. + NOTE here that self-gen MPDU data will not be considered + while evaluating this bit. + + Note that SCH does not evaluate this field. It is only for + SW to look at. + + +*/ + +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 + + +/* Description START_OF_FRAME_TIMESTAMP_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 15:0 of a 64 bit time stamp + Start of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + + +/* Description START_OF_FRAME_TIMESTAMP_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 31:16 of a 64 bit time stamp + Start of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + + +/* Description END_OF_FRAME_TIMESTAMP_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 15:0 of a 64 bit time stamp + End of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + + +/* Description END_OF_FRAME_TIMESTAMP_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 31:16 of a 64 bit time stamp + End of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + + +/* Description TERMINATE_RANGING_SEQUENCE + + Consumer: SW/SCH + Producer: TXPCU + + If set to 1, HWSCH will flush the TX pipeline and terminate + the ongoing SIFS sequence for TB Ranging. + + TXPCU to set it only in the context of TB Ranging, when + the condition to terminate the TB Ranging sequence is met + + + +*/ + +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x0000000000000001 + + +/* Description RESERVED_4A + + +*/ + +#define TX_FES_STATUS_END_RESERVED_4A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESERVED_4A_LSB 1 +#define TX_FES_STATUS_END_RESERVED_4A_MSB 7 +#define TX_FES_STATUS_END_RESERVED_4A_MASK 0x00000000000000fe + + +/* Description TIMING_STATUS + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + The MAC did not request for + the transmission to start at a particular time + MAC did request for transmission + to start at a particular time and PHY was able to do so. + + PHY was not able to honour + the requested transmit time by the MAC. The transmission + started later, and field transmit_delay indicates how much + later. + +*/ + +#define TX_FES_STATUS_END_TIMING_STATUS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TIMING_STATUS_LSB 8 +#define TX_FES_STATUS_END_TIMING_STATUS_MSB 9 +#define TX_FES_STATUS_END_TIMING_STATUS_MASK 0x0000000000000300 + + +/* Description RESPONSE_TYPE + + The response type that TXPCU was checking for + + After transmission of this + frame, no response in SIFS time is expected + + When TXPCU sees this setting, it shall not generated the + EXPECTED_RESPONSE TLV. + + RXPCU should never see this setting + An ACK frame is expected as response + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 64 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 256 bitmap is expected. + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending + NDP or BR-Poll. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + PDG uses the size info and assumes + single BA format with ACK and 64 bitmap embedded. + If SW expects more bitmaps in case of multi-TID, is shall + program the 'Extend_duration_value_bw...' field for additional + duration time. + For TXPCU only the fact that an ACK and/or BA is received + is important. Reception of only ACK or BA is also considered + a success. + SW also typically sets this when sending VHT single MPDU. + Some chip vendors might send BA rather than ACK in response + to VHT single MPDU but still we want to accept BA as well. + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after queuing RTS frame + as standalone packet and sending it. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending PS-Poll. + + + For TXPCU either ACK and/or data reception is considered + success. + PDG basis it's response duration calculation on an ACK. + For the data portion, SW shall program the 'Extend_duration_value_bw...' + field + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for + 11ah usage + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO MU_Response_BA_bitmap + if indeed BA was received + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_data_bitmap + and MU_Response_BA_bitmap if indeed BA and data was received + + When selected, CBF frames are expected to be received in + MU reception (uplink OFDMA or uplink MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_cbf_bitmap + if indeed CBF frames were received. + When selected, MPDU frames + are expected in the MU reception (uplink OFDMA or uplink + MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_bitmap + if indeed frames were received. + Any response expected + to be send to this device in SIFS time is acceptable. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any frame in the medium to + this or any other device, is acceptable as response. + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any MU frameless + reception generated by the PHY is acceptable. + + PHY indicates this type of reception explicitly in TLV PHYRX_RSSI_LEGACY, + field Reception_type == reception_is_frameless + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU. + + This can be used for complex MU-MIMO or OFDMA scenarios, + like receiving MU-CTS. + + PDG can not calculate the uplink duration. Therefor SW shall + program the 'Extend_duration_value_bw...' field + SW sets this after + sending ranging NDPA followed by NDP as an ISTA and NDP + and LMR (Action No Ack) are expected as back-to-back reception + in SIFS. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 512 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 1024 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + When selected, CTS2S + frames are expected to be received in MU reception (uplink + OFDMA) + + RXPCU shall check each response for CTS2S and report to + TXPCU. + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed CTS2S + frames were received. + When selected, UL NDP + frames are expected to be received in MU reception (uplink + spatial multiplexing) + + RXPCU shall check each response for NDP and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed NDP + frames were received. + When selected, LMR frames + are expected to be received in MU reception (uplink OFDMA + or uplink MIMO) + + RXPCU shall check each response for LMR and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed LMR + frames were received. +*/ + +#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 10 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 14 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x0000000000007c00 + + +/* Description R2R_END_STATUS_TO_FOLLOW + + When set, TXPCU will still generate an R2R frame (typically + M-BA), and the 'R2R_STATUS_END' TLV. + +*/ + +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 15 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 15 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000008000 + + +/* Description TRANSMIT_DELAY + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + The number of 480 MHz clock cycles that the transmission + started after the actual requested transmit start time. + + Value saturates at 0xFFFF + +*/ + +#define TX_FES_STATUS_END_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_LSB 16 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_MSB 31 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + + +/* Description TX_GROUP_DELAY + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Group delay on TxTD+PHYRF path for this PPDU (packet BW + dependent), useful for RTT + + Unit is 960MHz cycles. + +*/ + +#define TX_FES_STATUS_END_TX_GROUP_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_LSB 32 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_MSB 43 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_MASK 0x00000fff00000000 + + +/* Description RESERVED_5A + + Bits [14:12]: service_cbw: + + Field only valid when a response was received + + Source of the info here is the 'RECEIVED_RESPONSE_INFO' + TLV + + This field reflects the BW extracted from the Serivce Field + for 11ac mode of operation . + + This field is used in the context of Dynamic BW evaluation + purposes in SCH in case of SW-queued protection frame. + + Please refer 'BW_ENUM' e-num for the values used. + +*/ + +#define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESERVED_5A_LSB 44 +#define TX_FES_STATUS_END_RESERVED_5A_MSB 47 +#define TX_FES_STATUS_END_RESERVED_5A_MASK 0x0000f00000000000 + + +/* Description TPC_DBG_INFO_CMN_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CMN_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debu info that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN1_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN1_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CHN1_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN1_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN1_79_64 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN2_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CHN2_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN2_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN2_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN2_79_64 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 + + +/* Description PHYTX_TX_END_SW_INFO_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + + +/* Description PHYTX_TX_END_SW_INFO_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + + +/* Description PHYTX_TX_END_SW_INFO_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + + +/* Description PHYTX_TX_END_SW_INFO_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + + +/* Description BEAMFORM_MASKED_USER_BITMAP_15_0 + + Lower 16 bits of 'Beamform_masked_user_bitmap' + + PHY indicates in this field for which users it actually + did not beamform it's transmission even though this was + requested + + Bit 0: user 0, bit 1: user 1, etc. + + When 0: No beamform issue for this user + When 1: PHY could not beamform for this user, but did not + terminate the transmission + + +*/ + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x000000000000ffff + + +/* Description BEAMFORM_MASKED_USER_BITMAP_31_16 + + Middle 16 bits of 'Beamform_masked_user_bitmap' + See description above. + +*/ + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x00000000ffff0000 + + +/* Description CBF_SEGMENT_REQUEST_MASK + + Field only valid when brp_info_valid is set. + + Field equal to the 'Feedback Segment Retransmission Bitmap' + from the Beamform Report Poll frame OR Beamform Report Poll + Trigger frame + + Bit 0 represents segment 0 + Bit 1 represents segment 1 + Etc. + + 1'b1: Segment is requested + 1'b0: Segment is NOT requested + + +*/ + +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 32 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 39 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff00000000 + + +/* Description CBF_SEGMENT_SENT_MASK + + Field only valid when brp_info_valid is set. + + Bit 0 represents segment 0 + Bit 1 represents segment 1 + Etc. + + 1'b1: Segment is sent + 1'b0: Segment is not sent + + +*/ + +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 40 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 47 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff0000000000 + + +/* Description HIGHEST_ACHIEVED_DATA_NULL_RATIO + + Highest DATA:NULL ratio achieved for the current FES + + There was no Data:NULL + ratio established. + Best Data:NULL ratio was 16:1. + + Best Data:NULL ratio was 8:1. + + Best Data:NULL ratio was 4:1. + + Best Data:NULL ratio was 2:1. + + Best Data:NULL ratio was 1:1. + + terminate FES. + Best Data:NULL ratio was 1:2. + + Best Data:NULL ratio was 1:4. + + Best Data:NULL ratio was 1:8. + + Best Data:NULL ratio was 1:16. + + + +*/ + +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 48 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 52 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f000000000000 + + +/* Description USE_ALT_POWER_SR + + 0: Primary/default power1: Alternate power + +*/ + +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 53 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 53 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0020000000000000 + + +/* Description STATIC_2_PWR_MODE_STATUS + + 0: Static 2 power mode disabled1: Static 2 power mode enabled + + +*/ + +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 54 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 54 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0040000000000000 + + +/* Description OBSS_SRG_OPPORT_TRANSMIT_STATUS + + 0: Transmit based on SRG OBSS_PD opportunity initiated1: + Transmit based on non-SRG OBSS_PD opportunity initiated + +*/ + +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 55 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 55 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0080000000000000 + + +/* Description SRP_BASED_TRANSMIT_STATUS + + 0: non-SRP based transmit initiated1: SRP based transmit + initiated + +*/ + +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 56 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 56 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0100000000000000 + + +/* Description OBSS_PD_BASED_TRANSMIT_STATUS + + 0: non-OBSS_PD based transmit initiated1: obss_pd based + transmit initiated + +*/ + +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 57 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 57 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0200000000000000 + + +/* Description BEAMFORM_MASKED_USER_BITMAP_36_32 + + Upper 5 bits of 'Beamform_masked_user_bitmap' + See description above. + +*/ + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 58 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 62 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c00000000000000 + + +/* Description PDG_MPDU_READY + + Field only valid in case of SU transmissions, copied over + by TXPCU from 'PCU_PPDU_SETUP_END' + + Indicates the 'MPDU_INFO' or 'MPDU_QUEUE_OVERVIEW' ready + status in PDG. + +*/ + +#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 63 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 63 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x8000000000000000 + + +/* Description PDG_MPDU_COUNT + + Field only valid in case of SU transmissions when pdg_MPDU_ready + is set, copied over by TXPCU from 'PCU_PPDU_SETUP_END' + + Total MPDU count from 'MPDU_INFO' or 'MPDU_QUEUE_OVERVIEW' + + +*/ + +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x000000000000ffff + + +/* Description PDG_EST_MPDU_TX_COUNT + + Field only valid in case of SU transmissions when pdg_MPDU_ready + is set, copied over by TXPCU from 'PCU_PPDU_SETUP_END' + + PDG estimated MPDU Tx count from 'MPDU_INFO' or 'MPDU_QUEUE_OVERVIEW' + limited by timing boundaries (HWSCH, COEX, SR, etc.) + +*/ + +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0x00000000ffff0000 + + +/* Description PDG_OVERVIEW_LENGTH + + Field only valid in case of SU transmissions when pdg_MPDU_ready + is set, copied over by TXPCU from 'PCU_PPDU_SETUP_END' + + PDG estimated A-MPDU length from 'MPDU_QUEUE_OVERVIEW' limited + by timing boundaries (HWSCH, COEX, SR, etc.) + +*/ + +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 32 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 55 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff00000000 + + +/* Description TXOP_DURATION + + TXOP_DURATION of HE-SIG-A calculated by PDG, to be copied + from 'PCU_PPDU_SETUP_END' by TXPCU +*/ + +#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_TXOP_DURATION_LSB 56 +#define TX_FES_STATUS_END_TXOP_DURATION_MSB 62 +#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f00000000000000 + + +/* Description PDG_DROPPED_MPDU_WARNING + + Warning that PDG has dropped MPDUs due to SFM FIFO full + condition, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU + +*/ + +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 63 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 63 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x8000000000000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + The "a-factor" of the trigger-based PPDU response, to be + copied from 'PCU_PPDU_SETUP_END' by TXPCU + + This affects the packet extension duration. + + + + + + + +*/ + +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + The "PE-Disambiguity" of the trigger-based PPDU response, + to be copied from 'PCU_PPDU_SETUP_END' by TXPCU + + This affects the packet extension duration. + + +*/ + +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 + + +/* Description PACKET_EXTENSION + + Packet extension size, to be copied from 'PCU_PPDU_SETUP_END' + by TXPCU + + This is valid for all PPDUs including HE-Ranging NDPs (11az) + and Short-NDPs. + + + + + + + + +*/ + +#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000000000000038 + + +/* Description FEC_TYPE + + For trigger-based PPDU response, to be copied from 'PCU_PPDU_SETUP_END' + by TXPCU + 0: BCC + 1: LDPC + +*/ + +#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_FEC_TYPE_LSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000000000000040 + + +/* Description STBC + + For trigger-based PPDU response, to be copied from 'PCU_PPDU_SETUP_END' + by TXPCU + + When set, this transmission is based on STBC rates. +*/ + +#define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_STBC_LSB 7 +#define TX_FES_STATUS_END_STBC_MSB 7 +#define TX_FES_STATUS_END_STBC_MASK 0x0000000000000080 + + +/* Description NUM_DATA_SYMBOLS + + The number of data symbols in the transmission, to be copied + from 'PCU_PPDU_SETUP_END' by TXPCU + + This does not include PE_LTF. Also for STBC packets this + has to be an even number. This is valid for all PPDUs. +*/ + +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x0000000000ffff00 + + +/* Description RU_SIZE + + The size of the RU for this user, for trigger-based PPDU + response, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU + + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + HW will use per-user sub-band-mask + to infer the actual RU-size for Multi-large-RU/SU-Puncturing + + multi small RU + multi small RU + +*/ + +#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RU_SIZE_LSB 24 +#define TX_FES_STATUS_END_RU_SIZE_MSB 27 +#define TX_FES_STATUS_END_RU_SIZE_MASK 0x000000000f000000 + + + +#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_17A_LSB 28 +#define TX_FES_STATUS_END_RESERVED_17A_MSB 31 +#define TX_FES_STATUS_END_RESERVED_17A_MASK 0x00000000f0000000 + + +/* Description NUM_LTF_SYMBOLS + + Indicates the number of HE-LTF symbols, for trigger-based + PPDU response, to be copied from 'PCU_PPDU_SETUP_END' by + TXPCU + + 0: 1 symbol + 1: 2 symbols + 2: 3 symbols + 3: 4 symbols + 4: 5 symbols + 5: 6 symbols + 6: 7 symbols + 7: 8 symbols + + NOTE that this encoding is different from what is in "Num_LTF_symbols" + in the HE_SIG_A_MU_DL. + +*/ + +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 32 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 34 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 + + +/* Description LTF_SIZE + + Ltf size, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU + + + This is valid for all PPDUs including HE-Ranging NDPs (11az) + and Short-NDPs. + + + + + +*/ + +#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_LTF_SIZE_LSB 35 +#define TX_FES_STATUS_END_LTF_SIZE_MSB 36 +#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000001800000000 + + +/* Description CP_SETTING + + Field only valid when pkt type is HT, VHT or HE + + GI setting, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU + + + This is valid for all PPDUs including HE-Ranging NDPs (11az) + and Short-NDPs. + + Legacy normal GI + Legacy short GI + HE related GI + HE related GI + +*/ + +#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_CP_SETTING_LSB 37 +#define TX_FES_STATUS_END_CP_SETTING_MSB 38 +#define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000006000000000 + + + +#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_18A_LSB 39 +#define TX_FES_STATUS_END_RESERVED_18A_MSB 43 +#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f8000000000 + + +/* Description DCM + + Field only valid in case of 11ax transmission + + Indicates whether dual sub-carrier modulation is applied, + for trigger-based PPDU response, to be copied from 'PCU_PPDU_SETUP_END' + by TXPCU + 0: No DCM + 1:DCM + +*/ + +#define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_DCM_LSB 44 +#define TX_FES_STATUS_END_DCM_MSB 44 +#define TX_FES_STATUS_END_DCM_MASK 0x0000100000000000 + + +/* Description LDPC_EXTRA_SYMBOL + + Set to 1 if the LDPC PPDU encoding process (if an SU PPDU), + or at least one LDPC user's PPDU encoding process (if an + MU PPDU), results in an extra OFDM symbol (or symbols) + as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 + (Encoding process for MU PPDUs). Set to 0 otherwise. + + To be copied from 'PCU_PPDU_SETUP_END' by TXPCU + +*/ + +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 45 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 45 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000200000000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if none of the users' PPDU encoding process resuls in an + extra OFDM symbol (or symbols). + + To be copied from 'PCU_PPDU_SETUP_END' by TXPCU + +*/ + +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 46 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 46 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000400000000000 + + +/* Description RESERVED_18B + + +*/ + +#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_18B_LSB 47 +#define TX_FES_STATUS_END_RESERVED_18B_MSB 47 +#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000800000000000 + + +/* Description TX_PWR_SHARED + + Transmit Power (signed value) in units of 0.25 dBm, to be + copied from 'PCU_PPDU_SETUP_END' by TXPCU + +*/ + +#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 48 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 55 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff000000000000 + + +/* Description TX_PWR_UNSHARED + + Transmit Power (signed value) in units of 0.25 dBm, to be + copied from 'PCU_PPDU_SETUP_END' by TXPCU + +*/ + +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 56 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 63 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff00000000000000 + + +/* Description RANGING_ACTIVE_USER_MAP + + Field only valid for TB Ranging transmissions + + TXPCU sets this to the current active user bitmap, with + each bit set to: + 1: for an active user, and + 0: for any user not part of the ranging. + +*/ + +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x000000000000ffff + + +/* Description RANGING_SENT_DUMMY_TX + + Field only valid for TB Ranging transmissions + + TXPCU sets this bit if some user's 'STA Info' or 'User Info' + was sent out as dummy, or the whole transmission was sent + out as dummy. +*/ + +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x0000000000010000 + + +/* Description RANGING_FTM_FRAME_SENT + + Field only valid for Ranging transmissions + + TXPCU sets this bit if an FTM frame aggregated with an LMR + was sent. +*/ + +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x0000000000020000 + + +/* Description RESERVED_20A + + +*/ + +#define TX_FES_STATUS_END_RESERVED_20A_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RESERVED_20A_LSB 18 +#define TX_FES_STATUS_END_RESERVED_20A_MSB 23 +#define TX_FES_STATUS_END_RESERVED_20A_MASK 0x0000000000fc0000 + + +/* Description CV_CORR_STATUS + + CV correlation status from 'PHYTX_CV_CORR_STATUS,' to be + copied from 'PCU_PPDU_SETUP_END' by TXPCU + +*/ + +#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0x00000000ff000000 + + +/* Description CURRENT_TX_DURATION + + The duration of the transmission in us, copied over from + PCU_PPDU_SETUP_{END, START} as the case may be + +*/ + +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 32 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 47 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff00000000 + + +/* Description RESERVED_21A + + Bits [19:16]: num_cts2self_transmitted: + + Number of CTS2SELF frames transmitted in this FES + + +*/ + +#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RESERVED_21A_LSB 48 +#define TX_FES_STATUS_END_RESERVED_21A_MSB 63 +#define TX_FES_STATUS_END_RESERVED_21A_MASK 0xffff000000000000 + + + +#endif // TX_FES_STATUS_END diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_prot.h b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_prot.h new file mode 100644 index 0000000000000000000000000000000000000000..b7091a653d99fc6fdb6d2d0e4bc4a0d9f0e9ebec --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_prot.h @@ -0,0 +1,861 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_PROT_H_ +#define _TX_FES_STATUS_PROT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 14 + +#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 7 + + +struct tx_fes_status_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t success : 1, // [0:0] + phytx_pkt_end_info_valid : 1, // [1:1] + phytx_abort_request_info_valid : 1, // [2:2] + reserved_0 : 20, // [22:3] + pkt_type : 4, // [26:23] + dot11ax_su_extended : 1, // [27:27] + rate_mcs : 4; // [31:28] + uint32_t frame_type : 2, // [1:0] + frame_subtype : 4, // [5:2] + rx_pwr_mgmt : 1, // [6:6] + status : 1, // [7:7] + duration_field : 16, // [23:8] + reserved_1a : 2, // [25:24] + agc_cbw : 3, // [28:26] + service_cbw : 3; // [31:29] + uint32_t start_of_frame_timestamp_15_0 : 16, // [15:0] + start_of_frame_timestamp_31_16 : 16; // [31:16] + uint32_t end_of_frame_timestamp_15_0 : 16, // [15:0] + end_of_frame_timestamp_31_16 : 16; // [31:16] + uint32_t tx_group_delay : 12, // [11:0] + timing_status : 2, // [13:12] + dpdtrain_done : 1, // [14:14] + reserved_4 : 1, // [15:15] + transmit_delay : 16; // [31:16] + uint32_t tpc_dbg_info_cmn_15_0 : 16, // [15:0] + tpc_dbg_info_cmn_31_16 : 16; // [31:16] + uint32_t tpc_dbg_info_cmn_47_32 : 16, // [15:0] + tpc_dbg_info_chn1_15_0 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_31_16 : 16, // [15:0] + tpc_dbg_info_chn1_47_32 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_63_48 : 16, // [15:0] + tpc_dbg_info_chn1_79_64 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_15_0 : 16, // [15:0] + tpc_dbg_info_chn2_31_16 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_47_32 : 16, // [15:0] + tpc_dbg_info_chn2_63_48 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_79_64 : 16; // [15:0] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t phytx_tx_end_sw_info_15_0 : 16, // [15:0] + phytx_tx_end_sw_info_31_16 : 16; // [31:16] + uint32_t phytx_tx_end_sw_info_47_32 : 16, // [15:0] + phytx_tx_end_sw_info_63_48 : 16; // [31:16] +#else + uint32_t rate_mcs : 4, // [31:28] + dot11ax_su_extended : 1, // [27:27] + pkt_type : 4, // [26:23] + reserved_0 : 20, // [22:3] + phytx_abort_request_info_valid : 1, // [2:2] + phytx_pkt_end_info_valid : 1, // [1:1] + success : 1; // [0:0] + uint32_t service_cbw : 3, // [31:29] + agc_cbw : 3, // [28:26] + reserved_1a : 2, // [25:24] + duration_field : 16, // [23:8] + status : 1, // [7:7] + rx_pwr_mgmt : 1, // [6:6] + frame_subtype : 4, // [5:2] + frame_type : 2; // [1:0] + uint32_t start_of_frame_timestamp_31_16 : 16, // [31:16] + start_of_frame_timestamp_15_0 : 16; // [15:0] + uint32_t end_of_frame_timestamp_31_16 : 16, // [31:16] + end_of_frame_timestamp_15_0 : 16; // [15:0] + uint32_t transmit_delay : 16, // [31:16] + reserved_4 : 1, // [15:15] + dpdtrain_done : 1, // [14:14] + timing_status : 2, // [13:12] + tx_group_delay : 12; // [11:0] + uint32_t tpc_dbg_info_cmn_31_16 : 16, // [31:16] + tpc_dbg_info_cmn_15_0 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_15_0 : 16, // [31:16] + tpc_dbg_info_cmn_47_32 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_47_32 : 16, // [31:16] + tpc_dbg_info_chn1_31_16 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_79_64 : 16, // [31:16] + tpc_dbg_info_chn1_63_48 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_31_16 : 16, // [31:16] + tpc_dbg_info_chn2_15_0 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_63_48 : 16, // [31:16] + tpc_dbg_info_chn2_47_32 : 16; // [15:0] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t tpc_dbg_info_chn2_79_64 : 16; // [15:0] + uint32_t phytx_tx_end_sw_info_31_16 : 16, // [31:16] + phytx_tx_end_sw_info_15_0 : 16; // [15:0] + uint32_t phytx_tx_end_sw_info_63_48 : 16, // [31:16] + phytx_tx_end_sw_info_47_32 : 16; // [15:0] +#endif +}; + + +/* Description SUCCESS + + When set, protection response has been received +*/ + +#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 + + +/* Description PHYTX_PKT_END_INFO_VALID + + All the fields originating from PHYTX_PKT_END TLV contain + valid info +*/ + +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 + + +/* Description PHYTX_ABORT_REQUEST_INFO_VALID + + Field Phytx_abort_request_info_details contains valid info + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 + + +/* Description RESERVED_0 + + +*/ + +#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 +#define TX_FES_STATUS_PROT_RESERVED_0_MSB 22 +#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000007ffff8 + + +/* Description PKT_TYPE + + Field only valid when success is set + Source of the info here is the 'RECEIVED_RESPONSE_INFO' + TLV. + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23 +#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26 +#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000007800000 + + +/* Description DOT11AX_SU_EXTENDED + + Field only valid when success is set and pkt_type == 11ax + OR pkt_type == 11be + Source of the info here is the 'RECEIVED_RESPONSE_INFO' + TLV. + + When set, the 11ax or 11be reception was an extended range + SU +*/ + +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000008000000 + + +/* Description RATE_MCS + + Field only valid when success is set + Source of the info here is the 'RECEIVED_RESPONSE_INFO' + TLV. + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RATE_MCS_LSB 28 +#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 +#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f0000000 + + +/* Description FRAME_TYPE + + Field only valid when 'success' is set. + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + 802.11 frame type field + This field applies for 11ah as well. +*/ + +#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 + + +/* Description FRAME_SUBTYPE + + Field only valid when 'success' is set. + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + 802.11 frame subtype field + This field applies for 11ah as well. +*/ + +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 + + +/* Description RX_PWR_MGMT + + Field only valid when 'success' is set. + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + Power Management bit extracted from the header of the received + frame. +*/ + +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 + + +/* Description STATUS + + Field only valid when 'success' is set. + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + If set indicates that receive packet passed FCS check. +*/ + +#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_STATUS_LSB 39 +#define TX_FES_STATUS_PROT_STATUS_MSB 39 +#define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 + + +/* Description DURATION_FIELD + + Field only valid when 'success' is set. + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + The contents of the duration field of the received frame. + + +*/ + +#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 +#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 +#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 + + +/* Description AGC_CBW + + Field only valid when 'success' is set. + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + BW as detected by the AGC + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 +#define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 +#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 + + +/* Description SERVICE_CBW + + Field only valid when 'success' is set. + + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + This field reflects the BW extracted from the Serivce Field + for 11ac mode of operation . + + This field is used in the context of Dynamic/Static BW evaluation + purposes in TxPCU + CBW field extracted from Service field + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 + + +/* Description START_OF_FRAME_TIMESTAMP_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 15:0 of a 64 bit time stamp + Start of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + + +/* Description START_OF_FRAME_TIMESTAMP_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 31:16 of a 64 bit time stamp + Start of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + + +/* Description END_OF_FRAME_TIMESTAMP_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 15:0 of a 64 bit time stamp + End of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + + +/* Description END_OF_FRAME_TIMESTAMP_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 31:16 of a 64 bit time stamp + End of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + + +/* Description TX_GROUP_DELAY + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Group delay on TxTD+PHYRF path for this PPDU (packet BW + dependent), useful for RTT + + Unit is 960MHz cycles. + +*/ + +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_LSB 0 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MSB 11 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MASK 0x0000000000000fff + + +/* Description TIMING_STATUS + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + The MAC did not request for + the transmission to start at a particular time + MAC did request for transmission + to start at a particular time and PHY was able to do so. + + PHY was not able to honour + the requested transmit time by the MAC. The transmission + started later, and field transmit_delay indicates how much + later. + +*/ + +#define TX_FES_STATUS_PROT_TIMING_STATUS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TIMING_STATUS_LSB 12 +#define TX_FES_STATUS_PROT_TIMING_STATUS_MSB 13 +#define TX_FES_STATUS_PROT_TIMING_STATUS_MASK 0x0000000000003000 + + +/* Description DPDTRAIN_DONE + + Field only valid when PHYTX_PKT_END_info_valid is set + + For DPD Training packets, this bit is set to indicate that + DPD Training was successfully run to completion. Also + reused by Implicit BF Calibration Packets. This bit is intended + for debug purposes. + +*/ + +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_LSB 14 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MSB 14 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MASK 0x0000000000004000 + + +/* Description RESERVED_4 + + PHYTX_PKT_END info + + +*/ + +#define TX_FES_STATUS_PROT_RESERVED_4_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_RESERVED_4_LSB 15 +#define TX_FES_STATUS_PROT_RESERVED_4_MSB 15 +#define TX_FES_STATUS_PROT_RESERVED_4_MASK 0x0000000000008000 + + +/* Description TRANSMIT_DELAY + + PHYTX_PKT_END info + + The number of 480 MHz clock cycles that the transmission + started after the actual requested transmit start time. + + Value saturates at 0xFFFF + +*/ + +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_LSB 16 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MSB 31 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CMN_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CMN_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CMN_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN1_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN1_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN1_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CHN1_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN1_79_64 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN2_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN2_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CHN2_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN2_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN2_79_64 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff00000000 + + +/* Description PHYTX_ABORT_REQUEST_INFO_DETAILS + + Field only valid when PHYTX_ABORT_REQUEST_info_valid is + set + + The reason why PHYTX is requested an abort +*/ + + +/* Description PHYTX_ABORT_REASON + + Reason for early termination of TX packet by the PHY + + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 48 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 55 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00ff000000000000 + + +/* Description USER_NUMBER + + For some errors, the user for which this error was detected + can be indicated in this field. + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 56 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 61 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x3f00000000000000 + + +/* Description RESERVED + + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 62 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 63 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0xc000000000000000 + + +/* Description PHYTX_TX_END_SW_INFO_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + + +/* Description PHYTX_TX_END_SW_INFO_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + + +/* Description PHYTX_TX_END_SW_INFO_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + + +/* Description PHYTX_TX_END_SW_INFO_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + + + +#endif // TX_FES_STATUS_PROT diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_start.h b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_start.h new file mode 100644 index 0000000000000000000000000000000000000000..f4937a8ce31f2686687979c3bd483bb13a7d07f7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_start.h @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_START_H_ +#define _TX_FES_STATUS_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START 2 + + +struct tx_fes_status_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; // [31:0] + uint32_t reserved_1a : 8, // [7:0] + transmit_start_reason : 3, // [10:8] + disabled_user_bitmap_36_32 : 5, // [15:11] + schedule_cmd_ring_id : 5, // [20:16] + fes_control_mode : 2, // [22:21] + schedule_try : 4, // [26:23] + medium_prot_type : 3, // [29:27] + reserved_1b : 2; // [31:30] + uint32_t optimal_bw_try_count : 4, // [3:0] + number_of_users : 7, // [10:4] + coex_nack_count : 5, // [15:11] + cca_ed0 : 16; // [31:16] + uint32_t disabled_user_bitmap_31_0 : 32; // [31:0] +#else + uint32_t schedule_id : 32; // [31:0] + uint32_t reserved_1b : 2, // [31:30] + medium_prot_type : 3, // [29:27] + schedule_try : 4, // [26:23] + fes_control_mode : 2, // [22:21] + schedule_cmd_ring_id : 5, // [20:16] + disabled_user_bitmap_36_32 : 5, // [15:11] + transmit_start_reason : 3, // [10:8] + reserved_1a : 8; // [7:0] + uint32_t cca_ed0 : 16, // [31:16] + coex_nack_count : 5, // [15:11] + number_of_users : 7, // [10:4] + optimal_bw_try_count : 4; // [3:0] + uint32_t disabled_user_bitmap_31_0 : 32; // [31:0] +#endif +}; + + +/* Description SCHEDULE_ID + + A field that SW can use to link this FES status to the schedule + command that originated this transmission. +*/ + +#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 +#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 +#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0x00000000ffffffff + + + +#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_RESERVED_1A_LSB 32 +#define TX_FES_STATUS_START_RESERVED_1A_MSB 39 +#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff00000000 + + +/* Description TRANSMIT_START_REASON + + Indicates what the SCH start reason reason was for initiating + this transmission. + + The transmission of this + PPDU got initiated by the scheduler due to Backoff expiration + + The transmission of + this PPDU got initiated by the scheduler due to reception + (by the SCH) of the TLV RECEIVED_TRIGGER_INFO that RXPCU + generated. Note that this can be an OFDMA trigger frame + based transmission as well as some legacy trigger (PS-POLL, + Qboost, U-APSD, etc.) based transmission + This transmission + of this PPDU got initiated as part of SIFS continuation. + An earlier PPDU was transmitted due to RBO expiration. Next + command is also expected to be transmitted in SIFS burst. + + This transmission + of this PPDU got initiated as part of SIFS continuation + and this is the last command in the burst. An earlier PPDU + was transmitted due to RBO expiration. + DO NOT USE + +*/ + +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 40 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 42 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x0000070000000000 + + +/* Description DISABLED_USER_BITMAP_36_32 + + Bitmap of users that are disabled for this transmission, + MSB 5 bits + + TXPCU converts disabled_group_bitmap_* in 'PCU_PPDU_SETUP_START' + from groups to users. + +*/ + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 43 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 47 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f80000000000 + + +/* Description SCHEDULE_CMD_RING_ID + + The schedule command ring that originated this transmission + + + + + + + + + + + + + + + + + + + + + + + + +*/ + +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 48 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 52 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 + + +/* Description FES_CONTROL_MODE + + No HW generated TLVs + PDG is activated to generate + TLVs + + + Note: Final Bandwidth selection is always performed by TX + PCU. + + +*/ + +#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 53 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 54 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x0060000000000000 + + +/* Description SCHEDULE_TRY + + The number of times this scheduler command has been tried + + +*/ + +#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 55 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 58 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x0780000000000000 + + +/* Description MEDIUM_PROT_TYPE + + Self Gen Medium Prot type used + + + + + + + + + + Field only valid for user0 FES status. +*/ + +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 59 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 61 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x3800000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_RESERVED_1B_LSB 62 +#define TX_FES_STATUS_START_RESERVED_1B_MSB 63 +#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc000000000000000 + + +/* Description OPTIMAL_BW_TRY_COUNT + + This field indicates how many times this scheduling command + has been flushed by TXPCU as a result of most desired + BW not being available. + +*/ + +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x000000000000000f + + +/* Description NUMBER_OF_USERS + + The number of users in this transmission. +*/ + +#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x00000000000007f0 + + +/* Description COEX_NACK_COUNT + + Consumer: SCH + Producer: TXPCU + + The number of times PDG informed the SCHeduler module that + for this scheduling command, the WLAN transmission can + not be initialized due to getting a NACK response from the + Coex engine, or PDG not being able to fit a transmission + within the timing constraints given by Coex. + + Note that SCH will (re)set this count to 0 at the start + of reading a new SCH command. + This count is maintained on a per ring basis by the SCHeduler + + + + +*/ + +#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x000000000000f800 + + +/* Description CCA_ED0 + + Used by TXPCU to report CCA status at time of transmit bandwidth + selection. Each bit is a sample of BUSY/IDLE of ED[0] (as + provided by SCH to TXPCU) for each 20 MHz sub-band. These + stats could potentially be used in future for rate adaptation. + + +*/ + +#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_CCA_ED0_LSB 16 +#define TX_FES_STATUS_START_CCA_ED0_MSB 31 +#define TX_FES_STATUS_START_CCA_ED0_MASK 0x00000000ffff0000 + + +/* Description DISABLED_USER_BITMAP_31_0 + + Bitmap of users that are disabled for this transmission, + LSB 32 bits + + TXPCU converts disabled_group_bitmap_* in 'PCU_PPDU_SETUP_START' + from groups to users. + + +*/ + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 32 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 63 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff00000000 + + + +#endif // TX_FES_STATUS_START diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_start_ppdu.h b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_start_ppdu.h new file mode 100644 index 0000000000000000000000000000000000000000..edbf9095aaaff1f6aa91331c1a14302da9186747 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_start_ppdu.h @@ -0,0 +1,607 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_START_PPDU_H_ +#define _TX_FES_STATUS_START_PPDU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 2 + + +struct tx_fes_status_start_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_timestamp_lower_32 : 32; // [31:0] + uint32_t ppdu_timestamp_upper_32 : 32; // [31:0] + uint32_t subband_mask : 16, // [15:0] + ndp_frame : 2, // [17:16] + reserved_2b : 2, // [19:18] + coex_based_tx_bw : 3, // [22:20] + coex_based_ant_mask : 8, // [30:23] + reserved_2c : 1; // [31:31] + uint32_t coex_based_tx_pwr_shared_ant : 8, // [7:0] + coex_based_tx_pwr_ant : 8, // [15:8] + concurrent_bt_tx : 1, // [16:16] + concurrent_wlan_tx : 1, // [17:17] + concurrent_wan_tx : 1, // [18:18] + concurrent_wan_rx : 1, // [19:19] + coex_pwr_reduction_bt : 1, // [20:20] + coex_pwr_reduction_wlan : 1, // [21:21] + coex_pwr_reduction_wan : 1, // [22:22] + coex_result_alt_based : 1, // [23:23] + request_packet_bw : 3, // [26:24] + response_type : 5; // [31:27] +#else + uint32_t ppdu_timestamp_lower_32 : 32; // [31:0] + uint32_t ppdu_timestamp_upper_32 : 32; // [31:0] + uint32_t reserved_2c : 1, // [31:31] + coex_based_ant_mask : 8, // [30:23] + coex_based_tx_bw : 3, // [22:20] + reserved_2b : 2, // [19:18] + ndp_frame : 2, // [17:16] + subband_mask : 16; // [15:0] + uint32_t response_type : 5, // [31:27] + request_packet_bw : 3, // [26:24] + coex_result_alt_based : 1, // [23:23] + coex_pwr_reduction_wan : 1, // [22:22] + coex_pwr_reduction_wlan : 1, // [21:21] + coex_pwr_reduction_bt : 1, // [20:20] + concurrent_wan_rx : 1, // [19:19] + concurrent_wan_tx : 1, // [18:18] + concurrent_wlan_tx : 1, // [17:17] + concurrent_bt_tx : 1, // [16:16] + coex_based_tx_pwr_ant : 8, // [15:8] + coex_based_tx_pwr_shared_ant : 8; // [7:0] +#endif +}; + + +/* Description PPDU_TIMESTAMP_LOWER_32 + + Global timer value at start of Protection transmission +*/ + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + + +/* Description PPDU_TIMESTAMP_UPPER_32 + + Global timer value at start of Protection transmission +*/ + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 32 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 63 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + + +/* Description SUBBAND_MASK + + This mask indicates which 20 Mhz channels are actively used + in the BW or puncture pattern selected for transmit. + + Bit 0: primary 20 Mhz + Bit 1: secondary 20 MHz + Etc. + + +*/ + +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x000000000000ffff + + +/* Description NDP_FRAME + + Bit copied from the TX_FES_SETUP TLV + + No NDP transmission + Beamforming NDP + 11az NDP (HE Ranging NDP) + Short TB (HE Feedback NDP) +*/ + +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 17 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x0000000000030000 + + +/* Description RESERVED_2B + + +*/ + +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 18 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x00000000000c0000 + + +/* Description COEX_BASED_TX_BW + + Field valid for regular PPDU frame transmission + + This is the transmit bandwidth value + that is granted by Coex. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x0000000000700000 + + +/* Description COEX_BASED_ANT_MASK + + Field valid for regular PPDU or Response frame transmission + + + The antennas allowed to be used for this transmission. + (Coex is allowed to reduce the number of antennas to be + used, but not the number of SS) + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 + + +/* Description RESERVED_2C + + +*/ + +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x0000000080000000 + + +/* Description COEX_BASED_TX_PWR_SHARED_ANT + + Field valid for regular PPDU or Response frame transmission + + + Granted tx power for the shared antenna. + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 32 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 39 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 + + +/* Description COEX_BASED_TX_PWR_ANT + + Field valid for regular PPDU or Response frame transmission + + + Granted tx power for the unshared antenna + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 40 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 47 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff0000000000 + + +/* Description CONCURRENT_BT_TX + + Indicate the current TX is concurrent with a BT transmission. + This bit is to be copied over into the FES status info. + + +*/ + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 48 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 48 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x0001000000000000 + + +/* Description CONCURRENT_WLAN_TX + + Field valid for regular PPDU or Response frame transmission + + + Indicate the current TX is concurrent with other WLAN transmission. + This bit is to be copied over into FES status info. + +*/ + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 49 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 49 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 + + +/* Description CONCURRENT_WAN_TX + + Field valid for regular PPDU or Response frame transmission + + + Indicate the current TX is concurrent with WAN transmission. + This bit is to be copied over into FES status info. + +*/ + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 50 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 50 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x0004000000000000 + + +/* Description CONCURRENT_WAN_RX + + Field valid for regular PPDU or Response frame transmission + + + Indicate the current TX is concurrent with WAN reception. + This bit is to be copied over into FES status info. + +*/ + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 51 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 51 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x0008000000000000 + + +/* Description COEX_PWR_REDUCTION_BT + + Field valid for regular or response frame transmission. + When set, transmit power is reduced due to BT coex reason + + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 52 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 52 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 + + +/* Description COEX_PWR_REDUCTION_WLAN + + Field valid for regular or response frame transmission. + When set, transmit power is reduced due to wlan coex reason + + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 53 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 53 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 + + +/* Description COEX_PWR_REDUCTION_WAN + + Field valid for regular or response frame transmission. + When set, transmit power is reduced due to wan coex reason + + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 54 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 54 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 + + +/* Description COEX_RESULT_ALT_BASED + + Field valid for regular PPDU or Response frame transmission + + + When set, the resulting Coex transmit parameters are based + alternate transmit settings in the TX_RATE_SETTING STRUCT + of the original selected BW + + When not set, the resulting Coex parameters are based on + the default transmit settings in the TX_RATE_SETTING STRUCT + + + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 55 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 55 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x0080000000000000 + + +/* Description REQUEST_PACKET_BW + + The requested transmit BW to PDG + Note that Coex can have changed the actual allowed transmit + bandwidth. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 56 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 58 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x0700000000000000 + + +/* Description RESPONSE_TYPE + + PPDU transmission Response type expected + + After transmission of this + frame, no response in SIFS time is expected + + When TXPCU sees this setting, it shall not generated the + EXPECTED_RESPONSE TLV. + + RXPCU should never see this setting + An ACK frame is expected as response + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 64 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 256 bitmap is expected. + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending + NDP or BR-Poll. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + PDG uses the size info and assumes + single BA format with ACK and 64 bitmap embedded. + If SW expects more bitmaps in case of multi-TID, is shall + program the 'Extend_duration_value_bw...' field for additional + duration time. + For TXPCU only the fact that an ACK and/or BA is received + is important. Reception of only ACK or BA is also considered + a success. + SW also typically sets this when sending VHT single MPDU. + Some chip vendors might send BA rather than ACK in response + to VHT single MPDU but still we want to accept BA as well. + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after queuing RTS frame + as standalone packet and sending it. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending PS-Poll. + + + For TXPCU either ACK and/or data reception is considered + success. + PDG basis it's response duration calculation on an ACK. + For the data portion, SW shall program the 'Extend_duration_value_bw...' + field + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for + 11ah usage + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO MU_Response_BA_bitmap + if indeed BA was received + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_data_bitmap + and MU_Response_BA_bitmap if indeed BA and data was received + + When selected, CBF frames are expected to be received in + MU reception (uplink OFDMA or uplink MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_cbf_bitmap + if indeed CBF frames were received. + When selected, MPDU frames + are expected in the MU reception (uplink OFDMA or uplink + MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_bitmap + if indeed frames were received. + Any response expected + to be send to this device in SIFS time is acceptable. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any frame in the medium to + this or any other device, is acceptable as response. + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any MU frameless + reception generated by the PHY is acceptable. + + PHY indicates this type of reception explicitly in TLV PHYRX_RSSI_LEGACY, + field Reception_type == reception_is_frameless + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU. + + This can be used for complex MU-MIMO or OFDMA scenarios, + like receiving MU-CTS. + + PDG can not calculate the uplink duration. Therefor SW shall + program the 'Extend_duration_value_bw...' field + SW sets this after + sending ranging NDPA followed by NDP as an ISTA and NDP + and LMR (Action No Ack) are expected as back-to-back reception + in SIFS. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 512 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 1024 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + When selected, CTS2S + frames are expected to be received in MU reception (uplink + OFDMA) + + RXPCU shall check each response for CTS2S and report to + TXPCU. + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed CTS2S + frames were received. + When selected, UL NDP + frames are expected to be received in MU reception (uplink + spatial multiplexing) + + RXPCU shall check each response for NDP and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed NDP + frames were received. + When selected, LMR frames + are expected to be received in MU reception (uplink OFDMA + or uplink MIMO) + + RXPCU shall check each response for LMR and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed LMR + frames were received. +*/ + +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 59 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 63 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf800000000000000 + + + +#endif // TX_FES_STATUS_START_PPDU diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_start_prot.h b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_start_prot.h new file mode 100644 index 0000000000000000000000000000000000000000..cda00f04c27ac11892f5d89862c861b68be65dc4 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_start_prot.h @@ -0,0 +1,577 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_START_PROT_H_ +#define _TX_FES_STATUS_START_PROT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 2 + + +struct tx_fes_status_start_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_timestamp_lower_32 : 32; // [31:0] + uint32_t prot_timestamp_upper_32 : 32; // [31:0] + uint32_t subband_mask : 16, // [15:0] + reserved_2b : 4, // [19:16] + prot_coex_based_tx_bw : 3, // [22:20] + prot_coex_based_ant_mask : 8, // [30:23] + prot_coex_result_alt_based : 1; // [31:31] + uint32_t prot_coex_tx_pwr_shared_ant : 8, // [7:0] + prot_coex_tx_pwr_ant : 8, // [15:8] + prot_concurrent_bt_tx : 1, // [16:16] + prot_concurrent_wlan_tx : 1, // [17:17] + prot_concurrent_wan_tx : 1, // [18:18] + prot_concurrent_wan_rx : 1, // [19:19] + prot_coex_pwr_reduction_bt : 1, // [20:20] + prot_coex_pwr_reduction_wlan : 1, // [21:21] + prot_coex_pwr_reduction_wan : 1, // [22:22] + prot_request_packet_bw : 3, // [25:23] + response_type : 5, // [30:26] + reserved_3a : 1; // [31:31] +#else + uint32_t prot_timestamp_lower_32 : 32; // [31:0] + uint32_t prot_timestamp_upper_32 : 32; // [31:0] + uint32_t prot_coex_result_alt_based : 1, // [31:31] + prot_coex_based_ant_mask : 8, // [30:23] + prot_coex_based_tx_bw : 3, // [22:20] + reserved_2b : 4, // [19:16] + subband_mask : 16; // [15:0] + uint32_t reserved_3a : 1, // [31:31] + response_type : 5, // [30:26] + prot_request_packet_bw : 3, // [25:23] + prot_coex_pwr_reduction_wan : 1, // [22:22] + prot_coex_pwr_reduction_wlan : 1, // [21:21] + prot_coex_pwr_reduction_bt : 1, // [20:20] + prot_concurrent_wan_rx : 1, // [19:19] + prot_concurrent_wan_tx : 1, // [18:18] + prot_concurrent_wlan_tx : 1, // [17:17] + prot_concurrent_bt_tx : 1, // [16:16] + prot_coex_tx_pwr_ant : 8, // [15:8] + prot_coex_tx_pwr_shared_ant : 8; // [7:0] +#endif +}; + + +/* Description PROT_TIMESTAMP_LOWER_32 + + Global timer value at start of Protection transmission +*/ + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + + +/* Description PROT_TIMESTAMP_UPPER_32 + + Global timer value at start of Protection transmission +*/ + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 32 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 63 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + + +/* Description SUBBAND_MASK + + This mask indicates which 20 Mhz channels are actively used + in the BW or puncture pattern selected for transmit. + + Bit 0: primary 20 Mhz + Bit 1: secondary 20 MHz + Etc. + + +*/ + +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x000000000000ffff + + +/* Description RESERVED_2B + + +*/ + +#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x00000000000f0000 + + +/* Description PROT_COEX_BASED_TX_BW + + Field valid for Protection frame transmission + + This is the transmit bandwidth value + that is granted by Coex. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x0000000000700000 + + +/* Description PROT_COEX_BASED_ANT_MASK + + Field valid for Protection frame transmission + + The antennas allowed to be used for this transmission. + (Coex is allowed to reduce the number of antennas to be + used, but not the number of SS) + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 + + +/* Description PROT_COEX_RESULT_ALT_BASED + + Field valid for Protection frame transmission + + When set, the resulting Coex transmit parameters are based + alternate transmit settings in the TX_RATE_SETTING STRUCT + of the original selected BW + + When not set, the resulting Coex parameters are based on + the default transmit settings in the TX_RATE_SETTING STRUCT + + + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x0000000080000000 + + +/* Description PROT_COEX_TX_PWR_SHARED_ANT + + Field valid for Protection frame transmission + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 32 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 39 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 + + +/* Description PROT_COEX_TX_PWR_ANT + + Field valid for Protection frame transmission + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 40 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 47 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff0000000000 + + +/* Description PROT_CONCURRENT_BT_TX + + Field valid for Protection frame transmission + + Indicate the current TX is concurrent with a BT transmission. + This bit is to be copied over into the FES status info. + + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 48 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 48 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x0001000000000000 + + +/* Description PROT_CONCURRENT_WLAN_TX + + Field valid for Protection frame transmission + + Indicate the current TX is concurrent with other WLAN transmission. + This bit is to be copied over into FES status info. +*/ + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 49 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 49 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 + + +/* Description PROT_CONCURRENT_WAN_TX + + Field valid for Protection frame transmission + + Indicate the current TX is concurrent with WAN transmission. + This bit is to be copied over into FES status info. + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 50 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 50 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x0004000000000000 + + +/* Description PROT_CONCURRENT_WAN_RX + + Field valid for Protection frame transmission + + Indicate the current TX is concurrent with WAN reception. + This bit is to be copied over into FES status info. + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 51 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 51 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x0008000000000000 + + +/* Description PROT_COEX_PWR_REDUCTION_BT + + When set, transmit power for the protection frame is reduced + due to BT coex reason + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 52 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 52 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 + + +/* Description PROT_COEX_PWR_REDUCTION_WLAN + + When set, transmit power for the protection frame is reduced + due to wlan coex reason + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 53 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 53 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 + + +/* Description PROT_COEX_PWR_REDUCTION_WAN + + When set, transmit power for the protection frame is reduced + due to wan coex reason + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 54 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 54 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 + + +/* Description PROT_REQUEST_PACKET_BW + + The requested transmit BW to PDG + Note that Coex can have changed the actual allowed transmit + bandwidth. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 55 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 57 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x0380000000000000 + + +/* Description RESPONSE_TYPE + + PPDU transmission Response type expected + + After transmission of this + frame, no response in SIFS time is expected + + When TXPCU sees this setting, it shall not generated the + EXPECTED_RESPONSE TLV. + + RXPCU should never see this setting + An ACK frame is expected as response + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 64 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 256 bitmap is expected. + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending + NDP or BR-Poll. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + PDG uses the size info and assumes + single BA format with ACK and 64 bitmap embedded. + If SW expects more bitmaps in case of multi-TID, is shall + program the 'Extend_duration_value_bw...' field for additional + duration time. + For TXPCU only the fact that an ACK and/or BA is received + is important. Reception of only ACK or BA is also considered + a success. + SW also typically sets this when sending VHT single MPDU. + Some chip vendors might send BA rather than ACK in response + to VHT single MPDU but still we want to accept BA as well. + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after queuing RTS frame + as standalone packet and sending it. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending PS-Poll. + + + For TXPCU either ACK and/or data reception is considered + success. + PDG basis it's response duration calculation on an ACK. + For the data portion, SW shall program the 'Extend_duration_value_bw...' + field + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for + 11ah usage + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO MU_Response_BA_bitmap + if indeed BA was received + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_data_bitmap + and MU_Response_BA_bitmap if indeed BA and data was received + + When selected, CBF frames are expected to be received in + MU reception (uplink OFDMA or uplink MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_cbf_bitmap + if indeed CBF frames were received. + When selected, MPDU frames + are expected in the MU reception (uplink OFDMA or uplink + MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_bitmap + if indeed frames were received. + Any response expected + to be send to this device in SIFS time is acceptable. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any frame in the medium to + this or any other device, is acceptable as response. + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any MU frameless + reception generated by the PHY is acceptable. + + PHY indicates this type of reception explicitly in TLV PHYRX_RSSI_LEGACY, + field Reception_type == reception_is_frameless + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU. + + This can be used for complex MU-MIMO or OFDMA scenarios, + like receiving MU-CTS. + + PDG can not calculate the uplink duration. Therefor SW shall + program the 'Extend_duration_value_bw...' field + SW sets this after + sending ranging NDPA followed by NDP as an ISTA and NDP + and LMR (Action No Ack) are expected as back-to-back reception + in SIFS. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 512 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 1024 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + When selected, CTS2S + frames are expected to be received in MU reception (uplink + OFDMA) + + RXPCU shall check each response for CTS2S and report to + TXPCU. + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed CTS2S + frames were received. + When selected, UL NDP + frames are expected to be received in MU reception (uplink + spatial multiplexing) + + RXPCU shall check each response for NDP and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed NDP + frames were received. + When selected, LMR frames + are expected to be received in MU reception (uplink OFDMA + or uplink MIMO) + + RXPCU shall check each response for LMR and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed LMR + frames were received. +*/ + +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 58 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 62 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c00000000000000 + + +/* Description RESERVED_3A + +*/ + +#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 63 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 63 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x8000000000000000 + + + +#endif // TX_FES_STATUS_START_PROT diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_user_ppdu.h b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_user_ppdu.h new file mode 100644 index 0000000000000000000000000000000000000000..0cd7097b0749d2c5c5799207ba9b37584d36f9cc --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_user_ppdu.h @@ -0,0 +1,517 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_USER_PPDU_H_ +#define _TX_FES_STATUS_USER_PPDU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 + +#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 + + +struct tx_fes_status_user_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t underflow_mpdu_count : 9, // [8:0] + data_underflow_warning : 2, // [10:9] + bw_drop_underflow_warning : 1, // [11:11] + qc_eosp_setting : 1, // [12:12] + fc_more_data_setting : 1, // [13:13] + fc_pwr_mgt_setting : 1, // [14:14] + mpdu_tx_count : 9, // [23:15] + user_blocked : 1, // [24:24] + pre_trig_response_delim_count : 7; // [31:25] + uint32_t underflow_byte_count : 16, // [15:0] + coex_abort_mpdu_count_valid : 1, // [16:16] + coex_abort_mpdu_count : 9, // [25:17] + transmitted_tid : 4, // [29:26] + txdma_dropped_mpdu_warning : 1, // [30:30] + reserved_1 : 1; // [31:31] + uint32_t duration : 16, // [15:0] + num_eof_delim_added : 16; // [31:16] + uint32_t psdu_octet : 24, // [23:0] + qos_buf_state : 8; // [31:24] + uint32_t num_null_delim_added : 22, // [21:0] + reserved_4a : 2, // [23:22] + cv_corr_user_valid_in_phy : 1, // [24:24] + nss : 3, // [27:25] + mcs : 4; // [31:28] + uint32_t ht_control : 32; // [31:0] +#else + uint32_t pre_trig_response_delim_count : 7, // [31:25] + user_blocked : 1, // [24:24] + mpdu_tx_count : 9, // [23:15] + fc_pwr_mgt_setting : 1, // [14:14] + fc_more_data_setting : 1, // [13:13] + qc_eosp_setting : 1, // [12:12] + bw_drop_underflow_warning : 1, // [11:11] + data_underflow_warning : 2, // [10:9] + underflow_mpdu_count : 9; // [8:0] + uint32_t reserved_1 : 1, // [31:31] + txdma_dropped_mpdu_warning : 1, // [30:30] + transmitted_tid : 4, // [29:26] + coex_abort_mpdu_count : 9, // [25:17] + coex_abort_mpdu_count_valid : 1, // [16:16] + underflow_byte_count : 16; // [15:0] + uint32_t num_eof_delim_added : 16, // [31:16] + duration : 16; // [15:0] + uint32_t qos_buf_state : 8, // [31:24] + psdu_octet : 24; // [23:0] + uint32_t mcs : 4, // [31:28] + nss : 3, // [27:25] + cv_corr_user_valid_in_phy : 1, // [24:24] + reserved_4a : 2, // [23:22] + num_null_delim_added : 22; // [21:0] + uint32_t ht_control : 32; // [31:0] +#endif +}; + + +/* Description UNDERFLOW_MPDU_COUNT + + The MPDU count correctly received from TX DMA when the first + underrun condition was detected + +*/ + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff + + +/* Description DATA_UNDERFLOW_WARNING + + Mac data underflow warning for this user + + No data underflow + PCU experienced data + underflow in between MPDUs + PCU experienced data + underflow within an MPDU + +*/ + +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 + + +/* Description BW_DROP_UNDERFLOW_WARNING + + When set, data underflow happened while TXPCU was busy with + dropping a frame that is only allowed to go out at certain + BW, which is not the BW of the current transmission + +*/ + +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 + + +/* Description QC_EOSP_SETTING + + This field indicates if TX PCU set the eosp bit in the QoS + control field for this user (indicated in field User_Id.) + + 0: No action + 1: eosp bit is set in all the transmitted frames. This is + done upon request of the PDG. + +*/ + +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 + + +/* Description FC_MORE_DATA_SETTING + + This field indicates what the setting was of the More data + bit in the Frame control field for this user (indicated + in field User_Id.) + + Note that TXPCU, depending on programming, might overwrite + this bit in the Frame control field or just passes on what + SW and/or OLE has already programmed. Either way, TXPCU + just blindly copies the final setting of this "more Data" + bit in the frame control field into this field in the TLV. + + + 0: more_data bit NOT set + 1: more_data bit is set + +*/ + +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000002000 + + +/* Description FC_PWR_MGT_SETTING + + This field indicates what the setting was of the pwr bit + in the Frame control field for this user (indicated in + field User_Id.) + + Note that TXPCU never manipulates the pwr bit in the FC + field. Generating the correct setting is all managed by + TX OLE. + TXPCU just reports here what the pwr setting was of the (last) + transmitted MPDU. + + 0: pwr_mgt bit NOT set + 1: pwr_mgt bit is set + +*/ + +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000004000 + + +/* Description MPDU_TX_COUNT + + Number of MPDU frames transmitted + + Note: MPDUs that had an underrun during transmission will + still be listed here. The assumption is that underrun is + a very rare occasion, and any miscounting can therefor + be accepted. If underrun happens too often, SW should change + the density settings. + +*/ + +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ff8000 + + +/* Description USER_BLOCKED + + When set, TXPCU received the TX_PEER_ENTRY TLV with bit 'Block_this_user' + set. As a result TXDMA did not push in any MPDUs for this + user and non were expected to be transmitted. TXPCU will + therefor NOT report any underrun conditions for this user + + +*/ + +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 + + +/* Description PRE_TRIG_RESPONSE_DELIM_COUNT + + This field is only valid when this TX_FES_STATUS_USER_PPDU + is generated in the context of sending a response to a + received trigger frame....(=> TX_FES_STATUS start indicated + for field Transmit_start_reason == Trigger_based_transmit_start) + + + The number of NULL delimiters the TXPCU passed on to the + PHY before any real MPDU (response) data is given to the + PHY that originated from the SCHeduler command. + + NOTE that this should not be flagged as an underrun condition. + + + In units of 32 delimiters. + + +*/ + +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 + + +/* Description UNDERFLOW_BYTE_COUNT + + The number of bytes correctly received for this MPDU when + the first underrun condition was detected + + In case of self-gen + SCH related data, self-gen will not + be part of the underflow byte count. For example, in case + of BA/CBF, if underrun is hit immediately after BA/CBF + is sent, the underflow byte count will be 0.the BA/CBF bytes + will not be part of the underflow byte count. +*/ + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 + + +/* Description COEX_ABORT_MPDU_COUNT_VALID + + When set to 1, the (A-MPDU) transmission was silently aborted + in the middle of transmission. The PHY faked the remaining + transmission on the medium, so that TX PCU is still waiting + for the BA frame to be received. +*/ + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 + + +/* Description COEX_ABORT_MPDU_COUNT + + Field only valid when 'Coex_abort_mpdu_count_valid' is set. + + The number of MPDU frames that were properly sent bdoefore + the coex transmit abort request was received + +*/ + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 + + +/* Description TRANSMITTED_TID + + TID field blindy copied over from the TX_QUEUE_EXTENSION + TLV, field qos_ctrl[3:0] + +*/ + +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 + + +/* Description TXDMA_DROPPED_MPDU_WARNING + + Indication to FW a warning that Tx DMA has dropped MPDUs + due to SFM FIFO full condition + TXPCU fills this from OR of all TXDMA_dropped_mpdu_warning + in 'TX_MPDU_STARTs' for this PPDU. + +*/ + +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 + + +/* Description RESERVED_1 + + Reserved and not used by HW + +*/ + +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 63 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 63 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x8000000000000000 + + +/* Description DURATION + + The value of the duration field that TXPCU inserted in transmitted + frames, for Tx Monitor to report + + For frames of encap type Ethernet or 802_3 TXPCU will always + insert this value + + + For frames of encap type: RAW and Native WiFi, TXPCU will + check the 'Duration_field_mask' setting in TX_RAW_OR_NATIVE_FRAME_SETUP + TLV to find out if overwrite is enabled. (This is per user) + + + In case of multi TID transmission of Multi STA transmission, + TXPCU will look at the 'TX_RAW_OR_NATIVE_FRAME_SETUP' of + the 'first user' + +*/ + +#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 +#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 +#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff + + +/* Description NUM_EOF_DELIM_ADDED + + The total number of EOF pad delimiters added by TXPCU to + the current PPDU for the MD/multi-TID group this user belongs + to + + Set to 0xFFFF if the number exceeds the field width + +*/ + +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 + + +/* Description PSDU_OCTET + + Field only valid in case in 'TX_FES_STATUS_START' the field + Transmit_start_reason != Trigger_based_transmit_start + + PSDU length in octets which includes all useful data in + a packet which includes EOF padding and final padding (including + the last 0 - 3 bytes). + + This is copied by TXPCU from 'PCU_PPDU_SETUP_USER.' + + +*/ + +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 + + +/* Description QOS_BUF_STATE + + The value of the buffer state field in the QoS control that + TXPCU inserted in transmitted frames, for Tx Monitor to + report + + TXPCU checks the '*Buf_state*' settings in 'TX_QUEUE_EXTENSION' + TLV to determine the value to insert. + + If TXPCU did not overwrite the buffer state field, this + shall be set to 0x0. + +*/ + +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 + + +/* Description NUM_NULL_DELIM_ADDED + + The total number of non-EOF pad/null delimiters added by + TXPCU to the current PPDU for this user + + +*/ + +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff + + +/* Description RESERVED_4A + + +*/ + +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x0000000000c00000 + + +/* Description CV_CORR_USER_VALID_IN_PHY + + PDG sets this as 1 for up to 8 users enabled in 'PHYTX_CV_CORR_STATUS' + after CV correlation, to be copied from 'PCU_PPDU_SETUP_USER.' + + + +*/ + +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x0000000001000000 + + +/* Description NSS + + Number of Spatial Streams occupied by the User, to be copied + from 'PCU_PPDU_SETUP_USER' by TXPCU + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_NSS_LSB 25 +#define TX_FES_STATUS_USER_PPDU_NSS_MSB 27 +#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x000000000e000000 + + +/* Description MCS + + Modulation Coding Scheme for the User, to be copied from + 'PCU_PPDU_SETUP_USER' by TXPCU + + +*/ + +#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_MCS_LSB 28 +#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 +#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f0000000 + + +/* Description HT_CONTROL + + The value of the HT control field that TXPCU inserted in + transmitted frames, for Tx Monitor to report + + TXPCU checks the various HT-control-related settings in 'TX_QUEUE_EXTENSION' + TLV to determine the value to insert. + + If TXPCU did not overwrite the HT control field, this shall + be set to 0x0. + +*/ + +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 + + + +#endif // TX_FES_STATUS_USER_PPDU diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_user_response.h new file mode 100644 index 0000000000000000000000000000000000000000..7950cd8324a6bdac543d504db97f51e9f15c579c --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_fes_status_user_response.h @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ +#define _TX_FES_STATUS_USER_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 + +#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1 + + +struct tx_fes_status_user_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fes_transmit_result : 4, // [3:0] + reserved_0 : 28; // [31:4] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 16; // [31:16] +#else + uint32_t reserved_0 : 28, // [31:4] + fes_transmit_result : 4; // [3:0] + uint32_t reserved_after_struct16 : 16; // [31:16] + struct phytx_abort_request_info phytx_abort_request_info_details; +#endif +}; + + +/* Description FES_TRANSMIT_RESULT + + Transmit result: + + Successful transmission of entire Frame exchange + sequence + + No Protection response frame received so timeout is triggered. + + No PPDU response frame received + so timeout is triggered. + Response frame was received + with an invalid FCS. + Response frame is received + without CRC error but it's not matched with expected SU_Response_type. + + Set if CBF is received without + any error but the Nr, Nc, BW, type or token in VHT MIMO + control field is not matched with expected values which + are specified by TX_FES_SETUP.cbf_* fields. + Response frame is received + without CRC error but it's not matched with expected SU_Response_type. + + For this user, no MPDU + was received at all, or all received MPDUs had an FCS error. + + + An MU UL response + reception was expected. That response came but the threshold + for number of successful user receptions was not met. + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + transmission + was successful and proper responses have been received. + But the required ratio between useful MPDU data and null + delimiters was not met as specified by field : Fes_continuation_ratio_threshold. + The FES (and potentially the SIFS burst) shall be terminated + by the SCHeduler + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + + A TB ranging response was + expected for a sounding TF, but the response did not arrive + and timeout is triggered. + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + A TB ranging response + was expected for a sounding TF, but the reception did not + match the expected response. + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + + +*/ + +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x000000000000000f + + +/* Description RESERVED_0 + + Bits [15:4]: BAR_start_sequence_number: + + Starting sequence number to be overwritten by TXPCU for + BAR or MU-BAR Trigger, to be copied from 'MPDU_QUEUE_OVERVIEW' + by TXPCU + + Bit [16]: BAR_SSN_overwrite_enable: + + Enable for TXPCU overwrite of the starting sequence number + for BAR or MU-BAR Trigger, to be copied from 'TX_QUEUE_EXTENSION' + by TXPCU + + +*/ + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 31 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0x00000000fffffff0 + + +/* Description PHYTX_ABORT_REQUEST_INFO_DETAILS + + The reason why PHYTX is requesting an abort +*/ + + +/* Description PHYTX_ABORT_REASON + + Reason for early termination of TX packet by the PHY + + +*/ + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + + +/* Description USER_NUMBER + + For some errors, the user for which this error was detected + can be indicated in this field. + +*/ + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + + +/* Description RESERVED + + +*/ + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + + +/* Description RESERVED_AFTER_STRUCT16 + + +*/ + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 48 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 63 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xffff000000000000 + + + +#endif // TX_FES_STATUS_USER_RESPONSE diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_flush_req.h b/drivers/staging/fw-api/hw/qcn6432/tx_flush_req.h new file mode 100644 index 0000000000000000000000000000000000000000..ddfd6c67ffd72c96f80e6a871e45d31eaee4b62f --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_flush_req.h @@ -0,0 +1,748 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FLUSH_REQ_H_ +#define _TX_FLUSH_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FLUSH_REQ 2 + +#define NUM_OF_QWORDS_TX_FLUSH_REQ 1 + + +struct tx_flush_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t flush_req_reason : 8, // [7:0] + phytx_abort_reason : 8, // [15:8] + flush_req_user_number_or_link_id : 6, // [21:16] + mlo_abort_reason : 5, // [26:22] + reserved_0a : 5; // [31:27] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0a : 5, // [31:27] + mlo_abort_reason : 5, // [26:22] + flush_req_user_number_or_link_id : 6, // [21:16] + phytx_abort_reason : 8, // [15:8] + flush_req_reason : 8; // [7:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description FLUSH_REQ_REASON + + The reason why the flush request was generated. + + This is included for clean implementation + and verification. This code should NOT be used during a + valid FLUSH. It is used as a keeper value when flush logic + is idle + Flush request issued + by TXPCU in case of a WCOEX abort. + This is a corner case scenario. + A situation where: + a.A RX is just over and CCA indication is IDLE + b.Crypt is still busy decrypting + c.A TX just starts. + The TX should be tried later. This situation may be rare. + Just taking an extra precaution. + This is the static + BW failure happening right after start_tx for either RTS + frame or data packet + This is the static + BW failure in the protection sequence (CTS). + This is PDG signaling + not enough TXOP for transmission + When SW issues a flush + WHICH CAUSES AN ONGOING FES to terminate + Not enough TXOP remaining + in either SW or HW mode. This checks if the remaining TXOP + < a parameterized minimum time. Currently half SIFS duration + (5 us). + HWSCH flush when Parser + engine encounters a header with all zeros in the DWORD + Issued in case + TLV transmission exceeds start_tx time + SW mode abort. When HWSCH + determines that none of the SW programmed (upto 3) BW times + can fit into the current TXOP remaining + Flush + request issued by TXPCU in case none of the PPDU_ALLOW_BW_* + fields are set in PCU_PPDU_SETUP TLV + Flush request issued by + TXPCU if RXPCU initiates a response generation for a MU + reception even though MU reception was not expected + Flush request issued by HWSCH + when a coex event caused this transmit to be aborted + Flush request issued by HWSCH + when the PHY does not return the SVD_READY before a timeout + expires + Flush request issued by TXPCU + when the number of MPDU counter for selected BW is zero + + Flush request issued by TXPCU if + TXPCU receives TX_PKT_END with error_unsupported_cbf during + CV transfer. + Indicates + TXPCU has not received PCU_PPDU_SETUP_INIT from PDG, by + the time it received PRE_START_TX from HWSCH. + Indicates + TXPCU has not received PCU_PPDU_SETUP_START from PDG, by + the time it received START_TX from HWSCH. + Indicates + TXPCU has not received TX_PHY_DESCRIPTOR within REQD_TLVS_WAIT_TIME + after receiving START_TX from HWSCH. + TXPCU did nor receive + the CBF info TLVs from the PHY fast enough which resulted + in a timeout. + Indicates + the total number of MPDUs that needs to be send out by + TXDMA is less than the number indicated by PDG/TXPCU in + the MPDU_LIMIT_STATUS + Fragmentation is + enabled in TX_FES_SETUP for an AMSDU or AMPDU + more_frag + bit in TX_FES_SETUP TLV is set for the last MPDU fragment + + Indicates TXPCU + has detected a mismatch between BWs detected at PRE_START_TX + and START_TX + flush request and + is asserted by TXPCU when the final negotiated BW from + COEX is not allowed by SW + flush request + and is asserted by TXPCU when the final negotiated BW from + COEX is not allowed by SW + Fragmentation + is enabled in raw mode buffer chaining mode. + A1 and A2 set + to MAC addresses for 11ah PV1 short frame which is an AMSDU + + An unsupported key_type + is set for a PV1 frames. WEP, TKIP and WAPI are not supported + for PV1 frames + Unexpected Tx Mpdu length. + Asserted if the MSDU PACKET TLV length is less than the + expected WMAC header + Asserted by PDG when COEX + related logic in PDG requires a flush request. + Full MSDU + packet was not provided by TXDMA when checksum/TSO/fragmentation + was enabled + The + length field in the incoming 802.3 ethernet frame doesn't + match with the actual number of bytes in the data TLV. + Non-QoS frames are + queued as part of AMSDU + Key type in peer + table set to NO_CIPHER for protected frames + This flush is initiated + by scheduler when (if enabled) CCA goes busy in the middle + of a PIFS burst + This flush is initiated + by TXPCU when a protection frame is send, but TXPCU has + not received address fields in time. + PDG generated this flush + request because not one MPDU length info has been received + at the required timeout (which is programmable) + PDG generated this + flush request because PHY issued an unexpected preamble + request type + The most desired + BW was not available, and TXPCU would like to try the most + optimal transmit BW again after a new BO period. + LLC received incomplete + frame + PDG received a CTS frame + that reduced the BW, As a result the MPDU does not fit + in the previous reserved time, the thus this transmission + is aborted + PDG received a CTS + frame that a reduced duration field. As a result the MPDU + does not fit in the previous reserved time, the thus this + transmission is aborted + + Note the duration field in CTS can be reduced as a result + of COEX reasons + HWSCH flush when Parser + engine encounters a header whose length is greater than + 511 dwords. This excludes DUMMY TLVs. + HWSCH flush when + Parser engine encounters a header whose TAG does not match + the XML specified length. This check excludes zero length + and variable length TLVs + HWSCH flush when + Parser engine encounters a non contiguous error check code, + while reading SFM. This check is primarily to catch data + write or read issues within the buffering process of scheduler + TLV in SFM + When HWSCH + attempts to transmit a packet based on OBSS_PD non-SRG + opportunity, a flush with this code is generated if "ReceivedRssi + from RXPCU > Scheduler_cmd.RssiAltNonSrg". + When HWSCH + attempts to transmit a packet based on OBSS_PD non-SRG + opportunity, a flush with this code is generated if "ReceivedRssi + from RXPCU > Scheduler_cmd.RssiAltSrg". + When HWSCH + attempts to transmit a packet within an SRP opportunity + window, a flush with this code is generated if "Scheduler_cmd.SrpAltPwr + > SRP_less_RSSI". + parse errors + HWSCH flush when Parser + engine encounters a header whose TAG is not listed in the + XML TAG table + An abort from PHY TX got + received + A soft from coex got + received before even a single MPDU got transmitted. Therefor + transmission is terminated. + PDG was asked to start + an MU transmission, but the number of users with actual + data was less then the threshold (Min_users_with_data_count) + + PDG was asked to start + an SU transmission, but the number of bytes that PDG has + been informed about that can be transmitted is less then + the required threshold (min_ppdu_bytes) + PDG was asked to start + an SU transmission, but the number of MPDUs that PDG has + been informed about that can be transmitted is less then + the required threshold (min_mpdus_in_ppdu) + PDG uses this code + when the min PPDU time to pad up to (pad_min_ppdu_time) + can not be met due to other boundary conditions (e.g. FES + time/TXOP time/TBTT) + Flush request initiated by + the ucode (M3) + TXPCU uses this code on + encountering an error condition (e.g. late MACTX_PHY_DESC + or CV error) while generating a response. + This flush code + is used by HWSCH to indicate that during SIFS bursting, + an SVD_READY timeout was detected, which resulted in the + SIFS burst to be aborted. + TXPCU has not been + properly initialized when the first data request from the + PHY has been seen. + TXPCU found + that the medium was not idle for the Carries Sense check + that PDG indicated was needed for the triggered response + frame. + PDG found + out that when trying to assign the RUs among the available + users, the number of unused RUs remained above the allowed + threshold + This happens when + Crypto receives TLVs for more TX users than it can support + at that point of time + This happens when + Crypto receives unsupported Key types (WEP, TKIP) for MU + + CBF response generation by + TXPCU ran into issues due to info not being available from + the PHY + TXPCU received + a PHY NAP TLV from rxpcu while a transmission was ongoing. + The transmission will be terminated with this abort reason. + + RXPCU found out that + the trigger frame that was received and for which the TX + path has been activated to generate a response, had an + FCS error. + Asserted by PDG + when COEX indicated to PDG that the transmit request is + NOT granted because a higher priority BT activity is ongoing. + + TXPCU detected a conflict + between an FES transmission and a self-gen response transmission. + This is when the PHY + RXPCU delays cause a self-gen to + overlap with the pre-backoff time from HWSCH for the next + FES. + PDG received + a MU-RTS trigger for which the CTS RU response setting + is not valid + PDG received a trigger + based transmission request for an RU size that is blocked + by SW. + Asserted when + PDG gets a TX_FES_SETUP with field "Fes_in_11ax_Trigger_response_config" + not being in sync with what it was expecting. + PDG received + OFDMA_TRIGGER_DETAILS and the configuration in there (which + RXPCU gets from the trigger frame has invalid field value + combinations + This flush request will be + asserted if the length of a checksum enabled MSDU is more + than 2400 bytes. + This flush request will + be asserted if mesh_enable is set for an MSDU subframe + while its not set for another MSDU subframe in the same + AMSDU + This flush request + will be asserted if mesh_enable is set for an ethernet + frame + Asserted when + TXPCU gets a TX_FES_SETUP with field "ofdma_triggered_response" + not being in sync with what it was expecting. + PDG received an 11ax + transmit set of parameters that is not allowed or not supported + + TXPCU generates + this flush request because trigger response transmission + setup info from the SCH was received too late + When HWSCH + attempts to transmit a packet having obss_pd disabled within + an obss_pd opportunity window this flush code is generated + + When HWSCH attempts + to transmit a packet having SRP disabled within an obss_pd + opportunity window this flush code is generated + In SRP SR, PDG will + generate flush if receiving PDG_TX_REQ in a blocking window + around SRP SR limit + PDG generates when no + data can be sent for the users specified by TX_FES_SETUP + field "RBO_must_have_data_user_limit." + Used by PDG for an + MU-MIMO sounding plus steering burst when it did not receive + CBF from any recipient STA + PDG generates + when encountering a 'HARD_NOTIFY' or a 'SEMI_HARD_NOTIFY' + frame unless ignore_tx_notify_setting is set in 'PDG_FES_SETUP' + + PDG was asked to + start a transmission, but the time required to transmit + the PPDU is less than the required threshold (flush_min_ppdu_time) + + Used by TXPCU + when Tx is complete and it is about to generate 'EXPECTED_RESPONSE' + but it has not got any 'RXPCU_SETUP_COMPLETE' although 'rxpcu_setup_complete_present' + was set in 'TX_FES_SETUP' + Used by TXPCU when the + 'RECEIVED_TRIGER_INFO' TLV is sent to SCH after the 'pre_phy_desc' + timer has expired, if enabled + Used by PDG when the + first 'MPDU_INFO' is not available when sending 'PCU_PPDU_SETUP_START' + so PDG has assumed a regular MPDU ('FW_tx_notify_frame = + NO_TX_NOTIFY'), but later the MPDU turned out to be a notify + frame, if enabled + TXDMA generates this flush + request when it gets 'MPDU_INFO's for a user that it is + unable to write into SFM since its SFM allocation is full. + + Used in TXPCU for + generating a flush request when 'PRE_PHY_DESC' is received + late (determined by a timer) + This flush request + code is used by PDG if the trigger response MPDUs cannot + be fit to avoid sending only null delimiters for e.g. unassociated + UORA and colliding with another STA with valid data. + Flush request used + by PDG in case of unexpected 'TX_FES_SETUP' + Flush request used by + PDG in case of MLO constraints forcing an abort + Flush request used + by HWSCH if an MLO backoff truncation request resulted in + a forced abort to avoid windows too close to transmissions + + Flush request + used by TXOLE if fragmentation is requested but the settings + are illegal + Flush request + used by TXPCU when required overwrite TLVs are not received + from microcode, or when overwrite TLVs are dropped in MAC + due to SFM full condition + Flush request by TXPCU if + PHY does not respond to 'MACRX_LMR_READ_REQUEST' or 'MACRX_LMR_DATA_REQUEST' + on time + Flush request by TXPCU + if PHY sent 'PHYRX_LMR_TRANSFER_ABORT' or 'PHYRX_LMR_READ_REQUEST_ACK' + with status anything other than OK + Flush request by + TXPCU on getting a mismatched TLV from RXPCU for 'RX_FRAME_*BITMAP_ACK' (1Kbit + instead of 256-bit or vice versa) + Flush request + by TXPCU on getting an 'RX_RESPONSE_REQUIRED_INFO' with + A-MPDU set, VHT Ack clear and 'response_ba*_cnt' zero, + to avoid a system hang + Flush request by + TXPCU on not getting a 'MACTX_CBF_DONE' from RXPCU after + sending 'RESPONSE_END_STATUS' TLV + Flush request by TXPCU if + SFM indicates 'user_fifo_full' + PDG was asked + to start an MU transmission, but one of the users' RU is + such that within the PPDU time the PSDU length that can + be fit is too low (based on a threshold in a PDG register) + + PDG was + asked to start an OBSS PD SR transmission, but the time + required to transmit the PPDU is less than the required + threshold (flush_min_ppdu_time_obss_pd_sr) + PDG was asked + to start an OBSS PD SR transmission, but the time required + for the FES is more than the OBSS PPDU duration (max_fes_time_obss_pd_sr) + + PDG timed out waiting + for CV correlation TLVs from microcode + Flush request from + PDG if CV correlation is enabled and the 'PHYTX_CV_CORR_STATUS' + from microcode indicates that the primary user's CBF has + failed + HWSCH-issued + flush when the SFM availability check fails during a SIFS + burst or when fetching part 2 TLVs + PDG uses this code + when the response time to pad up to (required_response_time) + cannot be met due to the frame length in 'PDG_RESPONSE' + exceeding the calculated padded length + Flush request to terminate + an FES when RXPCU aborted an UL MU reception early because + at the end of the "early_termination_window," the required + number of users with at least one valid MPDU delimiter + was not reached. + + Placeholder for future + needs + TXPCU uses this code when + more than the configured maximum CTS2SELF are being sent. + + TXPCU uses this code when + at the time of the main PPDU transmission, fewer than the + configured minimum CTS2SELF were sent. + TXDMA uses this code when + it is about to issue zero-address or zero-length read or + when it read a 'TX_MSDU_LINK' but the Buffer_type field + in the uniform descriptor header does not indicate 'Transmit_MSDU_Link_descriptor' + + + TXPCU uses this code when + it gets a 'pre_start_tx' pulse from SCH but has not yet + got the 'TX_FES_SETUP' TLV + + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Used by SCH when it + receives an undefined flush request reason code +*/ + +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff + + +/* Description PHYTX_ABORT_REASON + + Field only valid when Flush_req_reason == TXPCU_PHYTX_ABORT_ERR + + + This value is the default + value the MAC will fill in the status TLV (when not PHY + abort was received). + + Note that when PHY generates the PHYTX_ABORT_REQUEST, this + value shall never be used. + PHY ran out of transmit + data due to transmit underrun - this field is user-specific + (see user_number field) + + + + + + + + + + + + + + + + + + + + This used to be called 'error_illegal_nss.' + + + + This error indicates + that CV prefetch command indicated a CV index that is not + available. + This error indicates that + CV delete command indicated a CV index that did not contain + any valid info + Error found with the HE + transmission parameters + + + + + + + + + + + + + + + + + + + + + + All FIFO read + hang errors use this value. + All FIFO no read + errors use this value. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This is the merged Rx/Tx + CDC FIFO empty/full error code + All 'error_txtd_chn' codes + use this value as well. + This code is + used to abort the Tx when MAC Rx issues an abort request + with code 05 "macrx_abort_too_much_bad_data." + + + + + + + +*/ + +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00 + + +/* Description FLUSH_REQ_USER_NUMBER_OR_LINK_ID + + Field only valid when Flush_req_reason == TXPCU_PHYTX_ABORT_ERR + or PDG_FLREQ_CODE_{TXOP, MLO}_ABORT + + In case of TXPCU_PHYTX_ABORT_ERR, for some errors, the user + for which this error was detected can be indicated in this + field. + + In case of PDG_FLREQ_CODE_*_ABORT due to MLO, this field + will carry the partner link ID and validity due to which + the abort was initiated. + Bit [5]: partner link ID valid + Bits [4:3]: set to 0 + Bits [2:0]: partner link ID + +*/ + +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000 + + +/* Description MLO_ABORT_REASON + + Field valid only when Flush_req_reason == PDG_FLREQ_CODE_{TXOP, + MLO}_ABORT + + SW-specified block of the peer + for self-link + SW-specified block of the peer + from a partner link + Blocked due to RX ongoing in partner + link + MLO truncated CTS2SELF leading + to abort + Maximum padding exceeded + Maximum overlap duration exceeded + + User collision + threshold for MU exceeded + SW-specified block due to VDEV + ID collision with a non-MLO broadcast/multicast + + Blocked due to EMLSR black-out + window + T2 response changed in 'MLO_TX_RESP' + + PPDU duration zero in 'MLO_TX_RESP' + + PPDU duration + bigger than allowed in non-response mode 'MLO_TX_RESP' + PPDU in non-A-MPDU format + cannot be padded + PPDU duration truncated + in response mode 'MLO_TX_RESP' + flush generated due to TXOP + abort + flush generated due to + TXOP abort as MPDU count is zero for all users in 'MPDU_QUEUE_OVERVIEW' + + flush generated due to MLO + abort as 'MPDU_QUEUE_OVERVIEW' is not ready for all users + at PPDU phase + Trigger frame + end-alignment cannot be met, e.g. due to LDPC extra symbol + + +*/ + +#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000 + + +/* Description RESERVED_0A + + +*/ + +#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 +#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 +#define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_TLV64_PADDING_LSB 32 +#define TX_FLUSH_REQ_TLV64_PADDING_MSB 63 +#define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // TX_FLUSH_REQ diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_mpdu_start.h b/drivers/staging/fw-api/hw/qcn6432/tx_mpdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..2dfa8fbf40185436549337798d417b6c54044ec2 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_mpdu_start.h @@ -0,0 +1,777 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_MPDU_START_H_ +#define _TX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MPDU_START 10 + +#define NUM_OF_QWORDS_TX_MPDU_START 5 + + +struct tx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_length : 14, // [13:0] + frame_not_from_tqm : 1, // [14:14] + vht_control_present : 1, // [15:15] + mpdu_header_length : 8, // [23:16] + retry_count : 7, // [30:24] + wds : 1; // [31:31] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_47_32 : 16, // [15:0] + mpdu_sequence_number : 12, // [27:16] + raw_already_encrypted : 1, // [28:28] + frame_type : 2, // [30:29] + txdma_dropped_mpdu_warning : 1; // [31:31] + uint32_t iv_byte_0 : 8, // [7:0] + iv_byte_1 : 8, // [15:8] + iv_byte_2 : 8, // [23:16] + iv_byte_3 : 8; // [31:24] + uint32_t iv_byte_4 : 8, // [7:0] + iv_byte_5 : 8, // [15:8] + iv_byte_6 : 8, // [23:16] + iv_byte_7 : 8; // [31:24] + uint32_t iv_byte_8 : 8, // [7:0] + iv_byte_9 : 8, // [15:8] + iv_byte_10 : 8, // [23:16] + iv_byte_11 : 8; // [31:24] + uint32_t iv_byte_12 : 8, // [7:0] + iv_byte_13 : 8, // [15:8] + iv_byte_14 : 8, // [23:16] + iv_byte_15 : 8; // [31:24] + uint32_t iv_byte_16 : 8, // [7:0] + iv_byte_17 : 8, // [15:8] + iv_len : 5, // [20:16] + icv_len : 5, // [25:21] + vht_control_offset : 6; // [31:26] + uint32_t mpdu_type : 1, // [0:0] + transmit_bw_restriction : 1, // [1:1] + allowed_transmit_bw : 4, // [5:2] + tx_notify_frame : 3, // [8:6] + reserved_8a : 23; // [31:9] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t wds : 1, // [31:31] + retry_count : 7, // [30:24] + mpdu_header_length : 8, // [23:16] + vht_control_present : 1, // [15:15] + frame_not_from_tqm : 1, // [14:14] + mpdu_length : 14; // [13:0] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t txdma_dropped_mpdu_warning : 1, // [31:31] + frame_type : 2, // [30:29] + raw_already_encrypted : 1, // [28:28] + mpdu_sequence_number : 12, // [27:16] + pn_47_32 : 16; // [15:0] + uint32_t iv_byte_3 : 8, // [31:24] + iv_byte_2 : 8, // [23:16] + iv_byte_1 : 8, // [15:8] + iv_byte_0 : 8; // [7:0] + uint32_t iv_byte_7 : 8, // [31:24] + iv_byte_6 : 8, // [23:16] + iv_byte_5 : 8, // [15:8] + iv_byte_4 : 8; // [7:0] + uint32_t iv_byte_11 : 8, // [31:24] + iv_byte_10 : 8, // [23:16] + iv_byte_9 : 8, // [15:8] + iv_byte_8 : 8; // [7:0] + uint32_t iv_byte_15 : 8, // [31:24] + iv_byte_14 : 8, // [23:16] + iv_byte_13 : 8, // [15:8] + iv_byte_12 : 8; // [7:0] + uint32_t vht_control_offset : 6, // [31:26] + icv_len : 5, // [25:21] + iv_len : 5, // [20:16] + iv_byte_17 : 8, // [15:8] + iv_byte_16 : 8; // [7:0] + uint32_t reserved_8a : 23, // [31:9] + tx_notify_frame : 3, // [8:6] + allowed_transmit_bw : 4, // [5:2] + transmit_bw_restriction : 1, // [1:1] + mpdu_type : 1; // [0:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MPDU_LENGTH + + Consumer: TXOLE/CRYPTO/TXPCU + Producer: TXDMA + + Expected Length of the entire MPDU, which includes all MSDUs + within the MPDU and all OLE and Crypto processing. This + length includes the FCS field. +*/ + +#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 +#define TX_MPDU_START_MPDU_LENGTH_LSB 0 +#define TX_MPDU_START_MPDU_LENGTH_MSB 13 +#define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff + + +/* Description FRAME_NOT_FROM_TQM + + When set, TXPCU shall not take this frame into account for + indicating to TQM how many frames from it's queue got transmitted. + + + TXDMA gets this field from the TX_MSDU_DETAILS STRUCT (of + the first MSDU in the MPDU) in the MSDU link descriptor. + + + SW sets this bit (in TX_MSDU_DETAILS STRUCT) when it generates + a frame outside of the TQM path and that frame can be intermingled + with the other frames from the TQM. For example a trigger + frame embedded or put in front of data frames from TQM + within the same A-MPDU. For this SW generated frame, TXPCU + shall not include this frame in the transmit frame count + that is reported to TQM as that would result in incorrect + reporting to TQM. + + +*/ + +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 + + +/* Description VHT_CONTROL_PRESENT + + TXOLE sets this bit when it added 4 placeholder bytes for + VHT-CONTROL field in the MPDU header. + + For RAW frames, OLE will set this bit and compute vht_control_offset + when the order bit and QoS bit in frame_control field are + set to 1. For RAW management frame, this bit will be set + if order bit is set to 1. + + Used by TXPCU, to find out if it needs to overwrite the + HE-CONTROL field. + +*/ + +#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 + + +/* Description MPDU_HEADER_LENGTH + + This field is filled in by the OLE + Used by PCU, This prevents PCU from having to do this again + (in the same way)) +*/ + +#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 + + +/* Description RETRY_COUNT + + Consumer: TXOLE/TXPCU + Producer: TXDMA + + The number of times the frame is transmitted + +*/ + +#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 +#define TX_MPDU_START_RETRY_COUNT_LSB 24 +#define TX_MPDU_START_RETRY_COUNT_MSB 30 +#define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 + + +/* Description WDS + + If set the current packet is 4-address frame. + + Required because an aggregate can include some frames with + 3 address format and other frames with 4 address format. + Used by the OLE during encapsulation. + + TXDMA sets this when wds in the extension descriptor is + set. + + If no extension descriptor is used for this MPDU, TXDMA + gets the setting for this bit from a control register in + TXDMA + +*/ + +#define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 +#define TX_MPDU_START_WDS_LSB 31 +#define TX_MPDU_START_WDS_MSB 31 +#define TX_MPDU_START_WDS_MASK 0x0000000080000000 + + +/* Description PN_31_0 + + Consumer: TXOLE + Producer: TXDMA + + Bits 31 - 0 for the Packet Number used by encryption + +*/ + +#define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 +#define TX_MPDU_START_PN_31_0_LSB 32 +#define TX_MPDU_START_PN_31_0_MSB 63 +#define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 + + +/* Description PN_47_32 + + Consumer: TXOLE + Producer: TXDMA + + Bits 47 - 32 for the Packet Number used by encryption + +*/ + +#define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 +#define TX_MPDU_START_PN_47_32_LSB 0 +#define TX_MPDU_START_PN_47_32_MSB 15 +#define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff + + +/* Description MPDU_SEQUENCE_NUMBER + + Consumer: TXOLE + Producer: TXDMA + + Sequence number assigned to this MPDU + +*/ + +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 + + +/* Description RAW_ALREADY_ENCRYPTED + + Consumer: CRYPTO + Producer: TXDMA + + If set it indicates that the RAW MPDU has already been encrypted + and does not require HW encryption. If clear and if the + frame control indicates that this is a "protected" MPDU + and the peer key type indicates a cipher type then the + HW is expected to encrypt this packet. + +*/ + +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 + + +/* Description FRAME_TYPE + + Consumer: TXMON + Producer: TXOLE + + 802.11 frame type field + + TXDMA fills this as zero and TXOLE overwrites it. + + +*/ + +#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 +#define TX_MPDU_START_FRAME_TYPE_LSB 29 +#define TX_MPDU_START_FRAME_TYPE_MSB 30 +#define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 + + +/* Description TXDMA_DROPPED_MPDU_WARNING + + Consumer: FW + Producer: TXDMA + + Indication to TXPCU to indicate to FW a warning that Tx + DMA has dropped MPDUs due to SFM FIFO full condition + +*/ + +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 + + +/* Description IV_BYTE_0 + + Byte 0 of the IV field of the MPDU + Based on the Encryption type the iv_byte_0 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_0_LSB 32 +#define TX_MPDU_START_IV_BYTE_0_MSB 39 +#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 + + +/* Description IV_BYTE_1 + + Byte 1 of the IV field of the MPDU + Based on the Encryption type the iv_byte_1 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_1_LSB 40 +#define TX_MPDU_START_IV_BYTE_1_MSB 47 +#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 + + +/* Description IV_BYTE_2 + + Byte 2 of the IV field of the MDPU + Based on the Encryption type the iv_byte_2 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_2_LSB 48 +#define TX_MPDU_START_IV_BYTE_2_MSB 55 +#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 + + +/* Description IV_BYTE_3 + + Byte 3 of the IV field of the MPDU + Based on the Encryption type the iv_byte_3 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_3_LSB 56 +#define TX_MPDU_START_IV_BYTE_3_MSB 63 +#define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 + + +/* Description IV_BYTE_4 + + Byte 4 of the IV field of the MPDU + Based on the Encryption type the iv_byte_4 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_4_LSB 0 +#define TX_MPDU_START_IV_BYTE_4_MSB 7 +#define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff + + +/* Description IV_BYTE_5 + + Byte 5 of the IV field of the MPDU + Based on the Encryption type the iv_byte_5 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_5_LSB 8 +#define TX_MPDU_START_IV_BYTE_5_MSB 15 +#define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 + + +/* Description IV_BYTE_6 + + Byte 6 of the IV field of the MDPU + Based on the Encryption type the iv_byte_6 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_6_LSB 16 +#define TX_MPDU_START_IV_BYTE_6_MSB 23 +#define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 + + +/* Description IV_BYTE_7 + + Byte 7 of the IV field of the MPDU + Based on the Encryption type the iv_byte_7 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_7_LSB 24 +#define TX_MPDU_START_IV_BYTE_7_MSB 31 +#define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 + + +/* Description IV_BYTE_8 + + Byte 8 of the IV field of the MPDU + Based on the Encryption type the iv_byte_8 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_8_LSB 32 +#define TX_MPDU_START_IV_BYTE_8_MSB 39 +#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 + + +/* Description IV_BYTE_9 + + Byte 9 of the IV field of the MPDU + Based on the Encryption type the iv_byte_9 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_9_LSB 40 +#define TX_MPDU_START_IV_BYTE_9_MSB 47 +#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 + + +/* Description IV_BYTE_10 + + Byte 10 of the IV field of the MDPU + Based on the Encryption type the iv_byte_10 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_10_LSB 48 +#define TX_MPDU_START_IV_BYTE_10_MSB 55 +#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 + + +/* Description IV_BYTE_11 + + Byte 11 of the IV field of the MPDU + Based on the Encryption type the iv_byte_11 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_11_LSB 56 +#define TX_MPDU_START_IV_BYTE_11_MSB 63 +#define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 + + +/* Description IV_BYTE_12 + + Byte 8 of the IV field of the MPDU + Based on the Encryption type the iv_byte_12 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_12_LSB 0 +#define TX_MPDU_START_IV_BYTE_12_MSB 7 +#define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff + + +/* Description IV_BYTE_13 + + Byte 9 of the IV field of the MPDU + Based on the Encryption type the iv_byte_13 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_13_LSB 8 +#define TX_MPDU_START_IV_BYTE_13_MSB 15 +#define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 + + +/* Description IV_BYTE_14 + + Byte 10 of the IV field of the MDPU + Based on the Encryption type the iv_byte_14 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_14_LSB 16 +#define TX_MPDU_START_IV_BYTE_14_MSB 23 +#define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 + + +/* Description IV_BYTE_15 + + Byte 11 of the IV field of the MPDU + Based on the Encryption type the iv_byte_15 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_15_LSB 24 +#define TX_MPDU_START_IV_BYTE_15_MSB 31 +#define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 + + +/* Description IV_BYTE_16 + + Byte 8 of the IV field of the MPDU + Based on the Encryption type the iv_byte_16 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_16_LSB 32 +#define TX_MPDU_START_IV_BYTE_16_MSB 39 +#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 + + +/* Description IV_BYTE_17 + + Byte 9 of the IV field of the MPDU + Based on the Encryption type the iv_byte_17 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_17_LSB 40 +#define TX_MPDU_START_IV_BYTE_17_MSB 47 +#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 + + +/* Description IV_LEN + + Length of the IV field generated by Tx OLE +*/ + +#define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_LEN_LSB 48 +#define TX_MPDU_START_IV_LEN_MSB 52 +#define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 + + +/* Description ICV_LEN + + Length of the ICV field generated by Tx OLE. OLE will insert + zeros in the ICV field when it pushes a frame +*/ + +#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 +#define TX_MPDU_START_ICV_LEN_LSB 53 +#define TX_MPDU_START_ICV_LEN_MSB 57 +#define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 + + +/* Description VHT_CONTROL_OFFSET + + Field only valid when vht_control_present is set. + + Field filled in by TXOLE, used by TXPCU + + The starting byte number of the VHT control field in the + header + +*/ + +#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 + + +/* Description MPDU_TYPE + + Indicates the type of MPDU that OLE will generate: + + This MPDU is not in the A-MSDU + format (meaning there is no A-MSDU delimeter present) if + there is only 1 MSDU in the MPDU. When there are multiple + MSDUs in the MPDU, there is no choice, and the MSDUs within + the MPDU shall all have A-MSDU delimiters in front of them. + + The MSDUs within the MPDU will + all have to be in the A-MSDU format, even if there is just + a single MSDU embedded in the MPDU. In other words, there + is always an A-MSDU delimiter in front of the MSDU(s) in + the MPDU. + +*/ + +#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 +#define TX_MPDU_START_MPDU_TYPE_LSB 0 +#define TX_MPDU_START_MPDU_TYPE_MSB 0 +#define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 + + +/* Description TRANSMIT_BW_RESTRICTION + + Consumer: TXPCU + Producer: TXDMA + + 1'b0: This is a normal frame and there are no restrictions + on the BW that this frame can be transmitted on. + + 1'b1: This MPDU is only allowed to be transmitted at certain + BWs. The one and only allowed BW is indicated in field + allowed_transmit_bw + When TXPCU has made a BW selection and then encounters this + frame, the frame will be dropped and TXPCU will continue + transmitting the next frame (assuming there is no BW restriction + on that one) + +*/ + +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 + + +/* Description ALLOWED_TRANSMIT_BW + + Consumer: TXPCU + Producer: TXDMA + + Field only valid when transmit_bw_restriction is set + + TXDMA gets this from the three or four upper bits of the + "Sw_buffer_cookie" field from the TX_MPDU_DETAILS STRUCT + + + In case of NON punctured transmission: + allowed_transmit_bw[2:0] = 3'b000: 20 MHz TX only + allowed_transmit_bw[2:0] = 3'b001: 40 MHz TX only + allowed_transmit_bw[2:0] = 3'b010: 80 MHz TX only + allowed_transmit_bw[2:0] = 3'b011: 160 MHz TX only + allowed_transmit_bw[2:0] = 3'b100: 240 MHz TX only + allowed_transmit_bw[2:0] = 3'b101: 320 MHz TX only + allowed_transmit_bw[2:1] = 2'b11: reserved + + In case of punctured transmission: + allowed_transmit_bw[3:0] = 4'b0000: pattern 0 only + allowed_transmit_bw[3:0] = 4'b0001: pattern 1 only + allowed_transmit_bw[3:0] = 4'b0010: pattern 2 only + allowed_transmit_bw[3:0] = 4'b0011: pattern 3 only + allowed_transmit_bw[3:0] = 4'b0100: pattern 4 only + allowed_transmit_bw[3:0] = 4'b0101: pattern 5 only + allowed_transmit_bw[3:0] = 4'b0110: pattern 6 only + allowed_transmit_bw[3:0] = 4'b0111: pattern 7 only + allowed_transmit_bw[3:0] = 4'b1000: pattern 8 only + allowed_transmit_bw[3:0] = 4'b1001: pattern 9 only + allowed_transmit_bw[3:0] = 4'b1010: pattern 10 only + allowed_transmit_bw[3:0] = 4'b1011: pattern 11 only + allowed_transmit_bw[3:2] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c + + +/* Description TX_NOTIFY_FRAME + + Consumer: TQM/PDG/TXOLE + Producer: FW/SW + + When clear, this frame does not require any special handling. + + + When set, this MPDU contains an MSDU with the 'FW_tx_notify_frame' + field set. + This means this MPDU is a special frame that requires special + handling in TQM. + + Note that FW/SW shall always set the amsdu_not_allowed bit + in 'TX_MSDU_DETAILS' for any notify frame. + + Not a notify frame + + + + Rate cannot be overridden + by PDG + +*/ + +#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 + + +/* Description RESERVED_8A + + Bit 9: self_gen: + + Field only used in the MAC-flexibility feature in TXPCU + and PHY microcode + + 0: Indicates a normal data MPDU + 1: Indicates a self-gen MPDU + + +*/ + +#define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_MPDU_START_RESERVED_8A_LSB 9 +#define TX_MPDU_START_RESERVED_8A_MSB 31 +#define TX_MPDU_START_RESERVED_8A_MASK 0x00000000fffffe00 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TLV64_PADDING_LSB 32 +#define TX_MPDU_START_TLV64_PADDING_MSB 63 +#define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // TX_MPDU_START diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_msdu_extension.h b/drivers/staging/fw-api/hw/qcn6432/tx_msdu_extension.h new file mode 100644 index 0000000000000000000000000000000000000000..20dd83b78dc358e0c8855269e4e58b3fa2eff8bb --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_msdu_extension.h @@ -0,0 +1,797 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_MSDU_EXTENSION_H_ +#define _TX_MSDU_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 + + +struct tx_msdu_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tso_enable : 1, // [0:0] + reserved_0a : 6, // [6:1] + tcp_flag : 9, // [15:7] + tcp_flag_mask : 9, // [24:16] + reserved_0b : 7; // [31:25] + uint32_t l2_length : 16, // [15:0] + ip_length : 16; // [31:16] + uint32_t tcp_seq_number : 32; // [31:0] + uint32_t ip_identification : 16, // [15:0] + udp_length : 16; // [31:16] + uint32_t checksum_offset : 14, // [13:0] + partial_checksum_en : 1, // [14:14] + reserved_4a : 1, // [15:15] + payload_start_offset : 14, // [29:16] + reserved_4b : 2; // [31:30] + uint32_t payload_end_offset : 14, // [13:0] + reserved_5a : 2, // [15:14] + wds : 1, // [16:16] + reserved_5b : 15; // [31:17] + uint32_t buf0_ptr_31_0 : 32; // [31:0] + uint32_t buf0_ptr_39_32 : 8, // [7:0] + extn_override : 1, // [8:8] + encap_type : 2, // [10:9] + encrypt_type : 4, // [14:11] + tqm_no_drop : 1, // [15:15] + buf0_len : 16; // [31:16] + uint32_t buf1_ptr_31_0 : 32; // [31:0] + uint32_t buf1_ptr_39_32 : 8, // [7:0] + epd : 1, // [8:8] + mesh_enable : 2, // [10:9] + reserved_9a : 5, // [15:11] + buf1_len : 16; // [31:16] + uint32_t buf2_ptr_31_0 : 32; // [31:0] + uint32_t buf2_ptr_39_32 : 8, // [7:0] + dscp_tid_table_num : 6, // [13:8] + reserved_11a : 2, // [15:14] + buf2_len : 16; // [31:16] + uint32_t buf3_ptr_31_0 : 32; // [31:0] + uint32_t buf3_ptr_39_32 : 8, // [7:0] + reserved_13a : 8, // [15:8] + buf3_len : 16; // [31:16] + uint32_t buf4_ptr_31_0 : 32; // [31:0] + uint32_t buf4_ptr_39_32 : 8, // [7:0] + reserved_15a : 8, // [15:8] + buf4_len : 16; // [31:16] + uint32_t buf5_ptr_31_0 : 32; // [31:0] + uint32_t buf5_ptr_39_32 : 8, // [7:0] + reserved_17a : 8, // [15:8] + buf5_len : 16; // [31:16] +#else + uint32_t reserved_0b : 7, // [31:25] + tcp_flag_mask : 9, // [24:16] + tcp_flag : 9, // [15:7] + reserved_0a : 6, // [6:1] + tso_enable : 1; // [0:0] + uint32_t ip_length : 16, // [31:16] + l2_length : 16; // [15:0] + uint32_t tcp_seq_number : 32; // [31:0] + uint32_t udp_length : 16, // [31:16] + ip_identification : 16; // [15:0] + uint32_t reserved_4b : 2, // [31:30] + payload_start_offset : 14, // [29:16] + reserved_4a : 1, // [15:15] + partial_checksum_en : 1, // [14:14] + checksum_offset : 14; // [13:0] + uint32_t reserved_5b : 15, // [31:17] + wds : 1, // [16:16] + reserved_5a : 2, // [15:14] + payload_end_offset : 14; // [13:0] + uint32_t buf0_ptr_31_0 : 32; // [31:0] + uint32_t buf0_len : 16, // [31:16] + tqm_no_drop : 1, // [15:15] + encrypt_type : 4, // [14:11] + encap_type : 2, // [10:9] + extn_override : 1, // [8:8] + buf0_ptr_39_32 : 8; // [7:0] + uint32_t buf1_ptr_31_0 : 32; // [31:0] + uint32_t buf1_len : 16, // [31:16] + reserved_9a : 5, // [15:11] + mesh_enable : 2, // [10:9] + epd : 1, // [8:8] + buf1_ptr_39_32 : 8; // [7:0] + uint32_t buf2_ptr_31_0 : 32; // [31:0] + uint32_t buf2_len : 16, // [31:16] + reserved_11a : 2, // [15:14] + dscp_tid_table_num : 6, // [13:8] + buf2_ptr_39_32 : 8; // [7:0] + uint32_t buf3_ptr_31_0 : 32; // [31:0] + uint32_t buf3_len : 16, // [31:16] + reserved_13a : 8, // [15:8] + buf3_ptr_39_32 : 8; // [7:0] + uint32_t buf4_ptr_31_0 : 32; // [31:0] + uint32_t buf4_len : 16, // [31:16] + reserved_15a : 8, // [15:8] + buf4_ptr_39_32 : 8; // [7:0] + uint32_t buf5_ptr_31_0 : 32; // [31:0] + uint32_t buf5_len : 16, // [31:16] + reserved_17a : 8, // [15:8] + buf5_ptr_39_32 : 8; // [7:0] +#endif +}; + + +/* Description TSO_ENABLE + + Enable transmit segmentation offload +*/ + +#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 + + +/* Description RESERVED_0A + + FW will set to 0, MAC will ignore. +*/ + +#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 +#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 +#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e + + +/* Description TCP_FLAG + + TCP flags + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} +*/ + +#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 +#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 + + +/* Description TCP_FLAG_MASK + + TCP flag mask. Tcp_flag is inserted into the header based + on the mask, if TSO is enabled +*/ + +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 + + +/* Description RESERVED_0B + + FW will set to 0, MAC will ignore. +*/ + +#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 +#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 + + +/* Description L2_LENGTH + + L2 length for the msdu, if TSO is enabled +*/ + +#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 +#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 +#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff + + +/* Description IP_LENGTH + + IP length for the msdu, if TSO is enabled +*/ + +#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 + + +/* Description TCP_SEQ_NUMBER + + Tcp_seq_number for the msdu, if TSO is enabled + +*/ + +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff + + +/* Description IP_IDENTIFICATION + + IP_identification for the msdu, if TSO is enabled +*/ + +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff + + +/* Description UDP_LENGTH + + TXDMA is copies this field into MSDU START TLV +*/ + +#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 + + +/* Description CHECKSUM_OFFSET + + The calculated checksum from start offset to end offset + will be added to the checksum at the offset given by this + field +*/ + +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff + + +/* Description PARTIAL_CHECKSUM_EN + + Partial Checksum Enable Bit. + +*/ + +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 + + +/* Description RESERVED_4A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 + + +/* Description PAYLOAD_START_OFFSET + + L4 checksum calculations will start fromt this offset + +*/ + +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 + + +/* Description RESERVED_4B + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 +#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 + + +/* Description PAYLOAD_END_OFFSET + + L4 checksum calculations will end at this offset. + +*/ + +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff + + +/* Description RESERVED_5A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 + + +/* Description WDS + + If set the current packet is 4-address frame. Required + because an aggregate can include some frames with 3 address + format and other frames with 4 address format. Used by + the OLE during encapsulation. + Note: there is also global wds tx control in the TX_PEER_ENTRY + + +*/ + +#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_WDS_LSB 16 +#define TX_MSDU_EXTENSION_WDS_MSB 16 +#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 + + +/* Description RESERVED_5B + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 +#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 + + +/* Description BUF0_PTR_31_0 + + Lower 32 bits of the first buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this buffer + together with the 'cookie' info for this MSDU_EXTENSION + descriptor + +*/ + +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff + + +/* Description BUF0_PTR_39_32 + + Upper 8 bits of the first buffer pointer +*/ + +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff + + +/* Description EXTN_OVERRIDE + + Field only used by TCL + + When set, the fields encap_type, Encrypt_type, TQM_NO_DROP, + EPD and mesh_enable are valid and override any TCL per-bank + registers specifying these values (except TQM_NO_DROP). + + + When clear, the values for encap_type, Encrypt_type, EPD, + mesh_enable and DSCP_TID_TABLE_NUM are taken from per-bank + registers in TCL and TQM_NO_DROP is not being requested + by SW. + + +*/ + +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK 0x00000100 + + +/* Description ENCAP_TYPE + + Field only used by TCL, only valid if Extn_override is set. + + + Indicates the encapsulation that HW will perform: + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + DO NOT USE. Indicate Ethernet + + Used by the OLE during encapsulation. + +*/ + +#define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB 9 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB 10 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK 0x00000600 + + +/* Description ENCRYPT_TYPE + + Field only used by TCL, only valid if Extn_override is set + and encap_type = RAW + + Indicates type of decrypt cipher used (as defined in the + peer entry) + WEP 40-bit + WEP 104-bit + TKIP without MIC + WEP 128-bit + TKIP with MIC + WAPI + AES CCMP 128 + No crypto + AES CCMP 256 + AES CCMP 128 + AES CCMP 256 + WAPI GCM SM4 + + DO not use... Only for higher + layer modules.. + +*/ + +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB 11 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB 14 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK 0x00007800 + + +/* Description TQM_NO_DROP + + Field only used by TCL, only valid if Extn_override is set. + + + This bit is used to stop TQM from dropping MSDUs while adding + them to MSDU flows1'b1: Do not drop MSDU when any of the + threshold value is met while adding MSDU in a flow1'b1: + Drop MSDU when any of the threshold value is met while adding + MSDU in a flow + Note: TCL can also have CCE/LCE rules to set 'TQM_NO_DROP' + which will be OR'd to this value. + +*/ + +#define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK 0x00008000 + + +/* Description BUF0_LEN + + Length of the first buffer +*/ + +#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 + + +/* Description BUF1_PTR_31_0 + + Lower 32 bits of the second buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this buffer + together with the 'cookie' info for this MSDU_EXTENSION + descriptor + +*/ + +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff + + +/* Description BUF1_PTR_39_32 + + Upper 8 bits of the second buffer pointer +*/ + +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff + + +/* Description EPD + + Field only used by TCL, only valid if Extn_override is set. + + + When this bit is set then input packet is an EPD type + +*/ + +#define TX_MSDU_EXTENSION_EPD_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_EPD_LSB 8 +#define TX_MSDU_EXTENSION_EPD_MSB 8 +#define TX_MSDU_EXTENSION_EPD_MASK 0x00000100 + + +/* Description MESH_ENABLE + + Field only used by TCL, only valid if Extn_override is set. + + + If set to a non-zero value: + * For raw WiFi frames, this indicates transmission to a + mesh STA, enabling the interpretation of the 'Mesh Control + Present' bit (bit 8) of QoS Control (otherwise this bit + is ignored). The interpretation of the A-MSDU 'Length' + field is decided by the e-numerations below. + * For native WiFi frames, this indicates that a 'Mesh Control' + field is present between the header and the LLC. The three + non-zero values are interchangeable. + + + A-MSDU 'Length' is big endian and includes + the length of Mesh Control. + A-MSDU 'Length' is big endian and excludes + the length of Mesh Control. + A-MSDU 'Length' is little endian and + excludes the length of Mesh Control. This is 802.11s-compliant. + + +*/ + +#define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_MESH_ENABLE_LSB 9 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MSB 10 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MASK 0x00000600 + + +/* Description RESERVED_9A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 11 +#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000f800 + + +/* Description BUF1_LEN + + Length of the second buffer +*/ + +#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 + + +/* Description BUF2_PTR_31_0 + + Lower 32 bits of the third buffer pointer + NOTE: SW/FW manages the 'cookie' info related to this buffer + together with the 'cookie' info for this MSDU_EXTENSION + descriptor + +*/ + +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff + + +/* Description BUF2_PTR_39_32 + + Upper 8 bits of the third buffer pointer +*/ + +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff + + +/* Description DSCP_TID_TABLE_NUM + + Field only used by TCL, only valid if Extn_override is set. + + + This specifies the DSCP to TID mapping table to be used + for the MSDU + +*/ + +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_LSB 8 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MSB 13 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MASK 0x00003f00 + + +/* Description RESERVED_11A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000c000 + + +/* Description BUF2_LEN + + Length of the third buffer +*/ + +#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 + + +/* Description BUF3_PTR_31_0 + + Lower 32 bits of the fourth buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this buffer + together with the 'cookie' info for this MSDU_EXTENSION + descriptor + +*/ + +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff + + +/* Description BUF3_PTR_39_32 + + Upper 8 bits of the fourth buffer pointer +*/ + +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff + + +/* Description RESERVED_13A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 + + +/* Description BUF3_LEN + + Length of the fourth buffer +*/ + +#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 + + +/* Description BUF4_PTR_31_0 + + Lower 32 bits of the fifth buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this buffer + together with the 'cookie' info for this MSDU_EXTENSION + descriptor + +*/ + +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff + + +/* Description BUF4_PTR_39_32 + + Upper 8 bits of the fifth buffer pointer +*/ + +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff + + +/* Description RESERVED_15A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 + + +/* Description BUF4_LEN + + Length of the fifth buffer +*/ + +#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 + + +/* Description BUF5_PTR_31_0 + + Lower 32 bits of the sixth buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this buffer + together with the 'cookie' info for this MSDU_EXTENSION + descriptor + +*/ + +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff + + +/* Description BUF5_PTR_39_32 + + Upper 8 bits of the sixth buffer pointer +*/ + +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff + + +/* Description RESERVED_17A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 + + +/* Description BUF5_LEN + + Length of the sixth buffer +*/ + +#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 + + + +#endif // TX_MSDU_EXTENSION diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_msdu_start.h b/drivers/staging/fw-api/hw/qcn6432/tx_msdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..bfb5bea7244fac37ce01df7edfa8fce062dbf52d --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_msdu_start.h @@ -0,0 +1,529 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_MSDU_START_H_ +#define _TX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MSDU_START 8 + +#define NUM_OF_QWORDS_TX_MSDU_START 4 + + +struct tx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_len : 14, // [13:0] + first_msdu : 1, // [14:14] + last_msdu : 1, // [15:15] + encap_type : 2, // [17:16] + epd_en : 1, // [18:18] + da_sa_present : 2, // [20:19] + ipv4_checksum_en : 1, // [21:21] + udp_over_ipv4_checksum_en : 1, // [22:22] + udp_over_ipv6_checksum_en : 1, // [23:23] + tcp_over_ipv4_checksum_en : 1, // [24:24] + tcp_over_ipv6_checksum_en : 1, // [25:25] + dummy_msdu_delimitation : 1, // [26:26] + reserved_0a : 5; // [31:27] + uint32_t tso_enable : 1, // [0:0] + reserved_1a : 6, // [6:1] + tcp_flag : 9, // [15:7] + tcp_flag_mask : 9, // [24:16] + mesh_enable : 1, // [25:25] + reserved_1b : 6; // [31:26] + uint32_t l2_length : 16, // [15:0] + ip_length : 16; // [31:16] + uint32_t tcp_seq_number : 32; // [31:0] + uint32_t ip_identification : 16, // [15:0] + checksum_offset : 13, // [28:16] + partial_checksum_en : 1, // [29:29] + reserved_4 : 2; // [31:30] + uint32_t payload_start_offset : 14, // [13:0] + reserved_5a : 2, // [15:14] + payload_end_offset : 14, // [29:16] + reserved_5b : 2; // [31:30] + uint32_t udp_length : 16, // [15:0] + reserved_6 : 16; // [31:16] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0a : 5, // [31:27] + dummy_msdu_delimitation : 1, // [26:26] + tcp_over_ipv6_checksum_en : 1, // [25:25] + tcp_over_ipv4_checksum_en : 1, // [24:24] + udp_over_ipv6_checksum_en : 1, // [23:23] + udp_over_ipv4_checksum_en : 1, // [22:22] + ipv4_checksum_en : 1, // [21:21] + da_sa_present : 2, // [20:19] + epd_en : 1, // [18:18] + encap_type : 2, // [17:16] + last_msdu : 1, // [15:15] + first_msdu : 1, // [14:14] + msdu_len : 14; // [13:0] + uint32_t reserved_1b : 6, // [31:26] + mesh_enable : 1, // [25:25] + tcp_flag_mask : 9, // [24:16] + tcp_flag : 9, // [15:7] + reserved_1a : 6, // [6:1] + tso_enable : 1; // [0:0] + uint32_t ip_length : 16, // [31:16] + l2_length : 16; // [15:0] + uint32_t tcp_seq_number : 32; // [31:0] + uint32_t reserved_4 : 2, // [31:30] + partial_checksum_en : 1, // [29:29] + checksum_offset : 13, // [28:16] + ip_identification : 16; // [15:0] + uint32_t reserved_5b : 2, // [31:30] + payload_end_offset : 14, // [29:16] + reserved_5a : 2, // [15:14] + payload_start_offset : 14; // [13:0] + uint32_t reserved_6 : 16, // [31:16] + udp_length : 16; // [15:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MSDU_LEN + + MSDU length before encapsulation. It is the same value as + the length in the MSDU packet TLV +*/ + +#define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_MSDU_LEN_LSB 0 +#define TX_MSDU_START_MSDU_LEN_MSB 13 +#define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff + + +/* Description FIRST_MSDU + + If set the current MSDU is the first MSDU in MPDU. Used + by the OLE during encapsulation. +*/ + +#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000 +#define TX_MSDU_START_FIRST_MSDU_LSB 14 +#define TX_MSDU_START_FIRST_MSDU_MSB 14 +#define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000 + + +/* Description LAST_MSDU + + If set the current MSDU is the last MSDU in MPDU. Used + by the OLE during encapsulation. +*/ + +#define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000 +#define TX_MSDU_START_LAST_MSDU_LSB 15 +#define TX_MSDU_START_LAST_MSDU_MSB 15 +#define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000 + + +/* Description ENCAP_TYPE + + Indicates the encapsulation that HW will perform: + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + DO NOT USE. Indicate Ethernet + Used by the OLE during encapsulation. + +*/ + +#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_ENCAP_TYPE_LSB 16 +#define TX_MSDU_START_ENCAP_TYPE_MSB 17 +#define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000 + + +/* Description EPD_EN + + Consumer: TXOLE + Producer: SW/TCL + + If set to one use EPD instead of LPD + +*/ + +#define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_EPD_EN_LSB 18 +#define TX_MSDU_START_EPD_EN_MSB 18 +#define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000 + + +/* Description DA_SA_PRESENT + + Used for 11ah + + Indicates the encapsulation that HW will perform: + DA and SA absent + DA Present, SA Absent + + Both DA and SA are present + Used by the OLE during encapsulation. + + TXDMA gets this configuration from a sw configuration register. + + + +*/ + +#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000 +#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 +#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 +#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000 + + +/* Description IPV4_CHECKSUM_EN + + Enable IPv4 checksum replacement +*/ + +#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000 + + +/* Description UDP_OVER_IPV4_CHECKSUM_EN + + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. +*/ + +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000 + + +/* Description UDP_OVER_IPV6_CHECKSUM_EN + + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. +*/ + +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000 + + +/* Description TCP_OVER_IPV4_CHECKSUM_EN + + Enable TCP checksum over IPv4 replacement +*/ + +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000 + + +/* Description TCP_OVER_IPV6_CHECKSUM_EN + + Enable TCP checksum over IPv6 eplacement +*/ + +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000 + + +/* Description DUMMY_MSDU_DELIMITATION + + This bit is mainly for debug. + + TXDMA sets this bit when sending a dummy 'TX_MSDU_END' + 'TX_MSDU_START' + sequence for a user to delimit user arbitration where it + could switch to packet data from other users before continuing + this MSDU. + + This is done mainly for long raw Wi-Fi packets where TXDMA + needs to switch users in the midst of the packet but other + blocks assume TXDMA switch only at MSDU boundaries. + +*/ + +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000 + + +/* Description RESERVED_0A + + FW will set to 0, MAC will ignore. +*/ + +#define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_0A_LSB 27 +#define TX_MSDU_START_RESERVED_0A_MSB 31 +#define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000 + + +/* Description TSO_ENABLE + + Enable transmit segmentation offload. + + In case MSDU_EXTENSION is used, TXDMA gets the setting for + this bit from that descriptor. + In case MSDU_EXTENSION is NOT use, TXDMA gets the setting + for this bit from an internal SW programmable register. + + +*/ + +#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TSO_ENABLE_LSB 32 +#define TX_MSDU_START_TSO_ENABLE_MSB 32 +#define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000 + + +/* Description RESERVED_1A + + FW will set to 0, MAC will ignore. +*/ + +#define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_1A_LSB 33 +#define TX_MSDU_START_RESERVED_1A_MSB 38 +#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000 + + +/* Description TCP_FLAG + + TCP flags + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} +*/ + +#define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_FLAG_LSB 39 +#define TX_MSDU_START_TCP_FLAG_MSB 47 +#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000 + + +/* Description TCP_FLAG_MASK + + TCP flag mask. Tcp_flag is inserted into the header based + on the mask, if TSO is enabled +*/ + +#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_FLAG_MASK_LSB 48 +#define TX_MSDU_START_TCP_FLAG_MASK_MSB 56 +#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000 + + +/* Description MESH_ENABLE + + If set to 1: + + * For raw WiFi frames, this indicates transmission to a + mesh STA but is ignored by HW + + * For native WiFi frames, this is used to indicate to TX + OLE that a 'Mesh Control' field is present between the + header and the LLC +*/ + +#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_MESH_ENABLE_LSB 57 +#define TX_MSDU_START_MESH_ENABLE_MSB 57 +#define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000 + + +/* Description RESERVED_1B + + FW will set to 0, MAC will ignore. +*/ + +#define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_1B_LSB 58 +#define TX_MSDU_START_RESERVED_1B_MSB 63 +#define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000 + + +/* Description L2_LENGTH + + L2 length for the msdu, if TSO is enabled +*/ + +#define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008 +#define TX_MSDU_START_L2_LENGTH_LSB 0 +#define TX_MSDU_START_L2_LENGTH_MSB 15 +#define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff + + +/* Description IP_LENGTH + + IP length for the msdu, if TSO is enabled +*/ + +#define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008 +#define TX_MSDU_START_IP_LENGTH_LSB 16 +#define TX_MSDU_START_IP_LENGTH_MSB 31 +#define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000 + + +/* Description TCP_SEQ_NUMBER + + Tcp_seq_number for the msdu, if TSO is enabled + +*/ + +#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008 +#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 + + +/* Description IP_IDENTIFICATION + + IP_identification for the msdu, if TSO is enabled +*/ + +#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010 +#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff + + +/* Description CHECKSUM_OFFSET + + The calculated checksum from start offset to end offset + will be added to the checksum at the offset given by this + field +*/ + +#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 +#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 +#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000 + + +/* Description PARTIAL_CHECKSUM_EN + + Enable Partial Checksum, MAV feature +*/ + +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000 + + +/* Description RESERVED_4 + + +*/ + +#define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_4_LSB 30 +#define TX_MSDU_START_RESERVED_4_MSB 31 +#define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000 + + +/* Description PAYLOAD_START_OFFSET + + L4 checksum calculations will start fromt this offset + +*/ + +#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000 + + +/* Description RESERVED_5A + + +*/ + +#define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_5A_LSB 46 +#define TX_MSDU_START_RESERVED_5A_MSB 47 +#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000 + + +/* Description PAYLOAD_END_OFFSET + + L4 checksum calculations will end at this offset. + +*/ + +#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000 + + +/* Description RESERVED_5B + + +*/ + +#define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_5B_LSB 62 +#define TX_MSDU_START_RESERVED_5B_MSB 63 +#define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000 + + +/* Description UDP_LENGTH + + This field indicates UDP length/UDP lite checksum coverage + field to be used by L4 checksum engine in case TSO is enabled + for UDP/UDP lite respectively + +*/ + +#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018 +#define TX_MSDU_START_UDP_LENGTH_LSB 0 +#define TX_MSDU_START_UDP_LENGTH_MSB 15 +#define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff + + +/* Description RESERVED_6 + + +*/ + +#define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018 +#define TX_MSDU_START_RESERVED_6_LSB 16 +#define TX_MSDU_START_RESERVED_6_MSB 31 +#define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018 +#define TX_MSDU_START_TLV64_PADDING_LSB 32 +#define TX_MSDU_START_TLV64_PADDING_MSB 63 +#define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // TX_MSDU_START diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_peer_entry.h b/drivers/staging/fw-api/hw/qcn6432/tx_peer_entry.h new file mode 100644 index 0000000000000000000000000000000000000000..429ac21b564e7b36b594bf1f2115e2e51c675ec4 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_peer_entry.h @@ -0,0 +1,845 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_PEER_ENTRY_H_ +#define _TX_PEER_ENTRY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_PEER_ENTRY 18 + +#define NUM_OF_QWORDS_TX_PEER_ENTRY 9 + + +struct tx_peer_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mac_addr_a_31_0 : 32; // [31:0] + uint32_t mac_addr_a_47_32 : 16, // [15:0] + mac_addr_b_15_0 : 16; // [31:16] + uint32_t mac_addr_b_47_16 : 32; // [31:0] + uint32_t use_ad_b : 1, // [0:0] + strip_insert_vlan_inner : 1, // [1:1] + strip_insert_vlan_outer : 1, // [2:2] + vlan_llc_mode : 1, // [3:3] + key_type : 4, // [7:4] + a_msdu_wds_ad3_ad4 : 3, // [10:8] + ignore_hard_filters : 1, // [11:11] + ignore_soft_filters : 1, // [12:12] + epd_output : 1, // [13:13] + wds : 1, // [14:14] + insert_or_strip : 1, // [15:15] + sw_filter_id : 16; // [31:16] + uint32_t temporal_key_31_0 : 32; // [31:0] + uint32_t temporal_key_63_32 : 32; // [31:0] + uint32_t temporal_key_95_64 : 32; // [31:0] + uint32_t temporal_key_127_96 : 32; // [31:0] + uint32_t temporal_key_159_128 : 32; // [31:0] + uint32_t temporal_key_191_160 : 32; // [31:0] + uint32_t temporal_key_223_192 : 32; // [31:0] + uint32_t temporal_key_255_224 : 32; // [31:0] + uint32_t sta_partial_aid : 11, // [10:0] + transmit_vif : 4, // [14:11] + block_this_user : 1, // [15:15] + mesh_amsdu_mode : 2, // [17:16] + use_qos_alt_mute_mask : 1, // [18:18] + dl_ul_direction : 1, // [19:19] + reserved_12 : 12; // [31:20] + uint32_t insert_vlan_outer_tci : 16, // [15:0] + insert_vlan_inner_tci : 16; // [31:16] + uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] + uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0] + multi_link_addr_ad2_15_0 : 16; // [31:16] + uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] + uint32_t multi_link_addr_crypto_enable : 1, // [0:0] + reserved_17a : 15, // [15:1] + sw_peer_id : 16; // [31:16] +#else + uint32_t mac_addr_a_31_0 : 32; // [31:0] + uint32_t mac_addr_b_15_0 : 16, // [31:16] + mac_addr_a_47_32 : 16; // [15:0] + uint32_t mac_addr_b_47_16 : 32; // [31:0] + uint32_t sw_filter_id : 16, // [31:16] + insert_or_strip : 1, // [15:15] + wds : 1, // [14:14] + epd_output : 1, // [13:13] + ignore_soft_filters : 1, // [12:12] + ignore_hard_filters : 1, // [11:11] + a_msdu_wds_ad3_ad4 : 3, // [10:8] + key_type : 4, // [7:4] + vlan_llc_mode : 1, // [3:3] + strip_insert_vlan_outer : 1, // [2:2] + strip_insert_vlan_inner : 1, // [1:1] + use_ad_b : 1; // [0:0] + uint32_t temporal_key_31_0 : 32; // [31:0] + uint32_t temporal_key_63_32 : 32; // [31:0] + uint32_t temporal_key_95_64 : 32; // [31:0] + uint32_t temporal_key_127_96 : 32; // [31:0] + uint32_t temporal_key_159_128 : 32; // [31:0] + uint32_t temporal_key_191_160 : 32; // [31:0] + uint32_t temporal_key_223_192 : 32; // [31:0] + uint32_t temporal_key_255_224 : 32; // [31:0] + uint32_t reserved_12 : 12, // [31:20] + dl_ul_direction : 1, // [19:19] + use_qos_alt_mute_mask : 1, // [18:18] + mesh_amsdu_mode : 2, // [17:16] + block_this_user : 1, // [15:15] + transmit_vif : 4, // [14:11] + sta_partial_aid : 11; // [10:0] + uint32_t insert_vlan_inner_tci : 16, // [31:16] + insert_vlan_outer_tci : 16; // [15:0] + uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] + uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16] + multi_link_addr_ad1_47_32 : 16; // [15:0] + uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] + uint32_t sw_peer_id : 16, // [31:16] + reserved_17a : 15, // [15:1] + multi_link_addr_crypto_enable : 1; // [0:0] +#endif +}; + + +/* Description MAC_ADDR_A_31_0 + + Consumer: TX OLE + Producer: SW + + Lower 32 bits of the MAC address A used by HW for encapsulating + 802.11 + +*/ + +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff + + +/* Description MAC_ADDR_A_47_32 + + Consumer: TX OLE + Producer: SW + + Upper 16 bits of the MAC address A used by HW for encapsulating + 802.11 + +*/ + +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 + + +/* Description MAC_ADDR_B_15_0 + + Consumer: TX OLE + Producer: SW + + Lower 16 bits of the MAC address B used by HW for encapsulating + 802.11 + +*/ + +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 + + +/* Description MAC_ADDR_B_47_16 + + Consumer: TX OLE + Producer: SW + + Upper 32 bits of the MAC address B used by HW for encapsulating + 802.11 + +*/ + +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff + + +/* Description USE_AD_B + + Consumer: TX OLE + Producer: SW + + The bit is only evaluated when this MSDU is the first MSDU + in an MPDU. For other MSDUs this bit setting is ignored. + + It is part of the sw_msdu_param coming from the QM ADD frame + command. + + Normally in AP mode the DA address is used as the RA. This + is normally fine but the use_ad_b bit should be set when + DA is a multicast/broadcast address but we want to send + this packet using the destination STA address which will + be held in the mac_addr_b field of the peer descriptor. + + +*/ + +#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_USE_AD_B_LSB 32 +#define TX_PEER_ENTRY_USE_AD_B_MSB 32 +#define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 + + +/* Description STRIP_INSERT_VLAN_INNER + + Consumer: TX OLE + Producer: SW + + Strip or insert C-VLAN during encapsulation. + Insert_or_strip determines whether C-VLAN is to be stripped + or inserted. + +*/ + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 + + +/* Description STRIP_INSERT_VLAN_OUTER + + Consumer: TX OLE + Producer: SW + + Strip or insert S-VLAN during encapsulation. + Insert or strip determines whether S-VLAN is to be stripped + or inserted. + +*/ + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 + + +/* Description VLAN_LLC_MODE + + Consumer: TX OLE + Producer: SW + + If set encapsulate/decapsulate using the Scorpion compatible + VLAN LLC format +*/ + +#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 + + +/* Description KEY_TYPE + + Consumer: TX OLE, TX CRYPTO + Producer: SW + + The key_type indicates the cipher suite corresponding to + this peer entry: + WEP 40-bit + WEP 104-bit + TKIP without MIC + WEP 128-bit + TKIP with MIC + WAPI + AES CCMP 128 + No crypto + AES CCMP 256 + AES GCMP 128 + AES GCMP 256 + WAPI GCM SM4 + + DO NOT USE. This Key type ONLY + to be used for RX side + + +*/ + +#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_KEY_TYPE_LSB 36 +#define TX_PEER_ENTRY_KEY_TYPE_MSB 39 +#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 + + +/* Description A_MSDU_WDS_AD3_AD4 + + Consumer: TX OLE + Producer: SW + + Determines the selection of AD3 and AD4 for A-MSDU 4 address + frames (WDS): + AD3 = AD_A, AD4 = AD_A + AD3 = AD_A, AD4 = AD_B + AD3 = AD_B, AD4 = AD_A + AD3 = AD_B, AD4 = AD_B + AD3 = DA, AD4 = SA + +*/ + +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 + + +/* Description IGNORE_HARD_FILTERS + + SW can program this bit to 0x1 to ignore HARD filter conditions + and HWSCH will proceed with transmission, even if the HARD + filter bit is set in Filter LUT. + Note that SOFT filter conditions will filter the command, + even if this bit is set and ignore_soft_filters is not set + + For filtering all frames marked in the Filter LUT, both + ignore_soft_filters and ignore_hard_filters should be set + + +*/ + +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 + + +/* Description IGNORE_SOFT_FILTERS + + SW can program this bit to 0x1 to ignore SOFT filter conditions + and HWSCH will proceed with transmission, even if the SOFT + filter bit is set in Filter LUT. + Note that HARD filter conditions will filter the command, + even if this bit is set and ignore_hard_filters is not set + + For filtering all frames marked in the Filter LUT, both + ignore_soft_filters and ignore_hard_filters should be set + + + +*/ + +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 + + +/* Description EPD_OUTPUT + + Consumer: TX OLE + Producer: SW + + If set use EPD instead of LPD +*/ + +#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 +#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 +#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 + + +/* Description WDS + + If set all the frames in this transmission (for this user) + are 4-address frame. + + If not all frames need to use 4 address format, SW has per + frame 'wds' control, by using the 'wds' flag in the MSDU_EXTENSION + descriptor + + Used by the OLE during encapsulation. + +*/ + +#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_WDS_LSB 46 +#define TX_PEER_ENTRY_WDS_MSB 46 +#define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 + + +/* Description INSERT_OR_STRIP + + TXOLE will strip inner or outer + VLAN (if present in the frame) based on Strip_insert_vlan_{inner, + outer} + TXOLE will insert inner or outer + VLAN (only if absent in the frame) based on Strip_insert_vlan_{inner, + outer} with the TCI(s) given by Insert_vlan_{inner, outer}_tci + + NOTE: Strip VLAN is not supported by TCL. + +*/ + +#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 + + +/* Description SW_FILTER_ID + + Consumer: SCH + Producer: SW + + The full STA AID. + Use by SCH to determine if transmission for this STA should + be filtered as it just went into power save state. + In case of MU transmission, it means only this STA needs + to be removed from the transmission... + + +*/ + +#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 +#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 +#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 + + +/* Description TEMPORAL_KEY_31_0 + + Consumer: TX CRYPTO + Producer: SW + + First 32 bits of the temporal key material. The temporal + key for WEP 40-bit uses the first 40 bits, WEP 104-bit + uses the first 104 bits, WEP 128-bit uses all 128 bits, + TKIP with/without MIC uses 128 bits, WAPI uses all 128 bits, + and AES-CCM uses all 128 bits. + + Note that for TKIP, the 64 MIC bits are located in fields + 'temporal_key[255:192] + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff + + +/* Description TEMPORAL_KEY_63_32 + + Consumer: TX CRYPTO + Producer: SW + + Second 32 bits of the temporal key material. See the description + of temporal_key_31_0. + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 + + +/* Description TEMPORAL_KEY_95_64 + + Consumer: TX CRYPTO + Producer: SW + + Third 32 bits of the temporal key material. See the description + of temporal_key_31_0. + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff + + +/* Description TEMPORAL_KEY_127_96 + + Consumer: TX CRYPTO + Producer: SW + + Fourth 32 bits of the temporal key material. See the description + of temporal_key_31_0. + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 + + +/* Description TEMPORAL_KEY_159_128 + + Consumer: TX CRYPTO + Producer: SW + + Fifth 32 bits of the temporal key material. See the description + of temporal_key_31_0. + + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff + + +/* Description TEMPORAL_KEY_191_160 + + Consumer: TX CRYPTO + Producer: SW + + Final 32 bits of the temporal key material. See the description + of temporal_key_31_0. + + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 + + +/* Description TEMPORAL_KEY_223_192 + + Consumer: TX CRYPTO + Producer: SW + + Final 32 bits of the temporal key material. See the description + of temporal_key_31_0. + + For TKIP this is the TX MIC key[31:0]. + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff + + +/* Description TEMPORAL_KEY_255_224 + + Consumer: TX CRYPTO + Producer: SW + + Final 32 bits of the temporal key material. See the description + of temporal_key_31_0. + + For TKIP this is the TX MIC key[63:32]. + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 + + +/* Description STA_PARTIAL_AID + + This field in only used by the PDG. All other modules should + ignore this field. + + This field is only valid in case of a transmission at VHT + rates or HE rates. + + For VHT: + This field is the Partial AID to be filled in to the VHT + preamble. + + For HE: + This field is the sta_aid to be filled into the SIG B field. + + + In 11ah mode of operation, this field is provided by SW + to populate the the ID value of the SIG preamble of the + PPDU +*/ + +#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff + + +/* Description TRANSMIT_VIF + + Consumer: TXOLE + Producer: SW + + The VIF for this transmission. Used in MCC mode to control/overwrite + the PM bit settings. + +*/ + +#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 + + +/* Description BLOCK_THIS_USER + + Consumer: PDG + Producer: SCH + + Set by SCH when a MU transmission is started and this STA + has (just) entered or is in power save mode. + Due to the MU transmission SCH shall not terminate this + MU transmission (as is done with SU transmission), but continue + with the transmissions for all other STAs. + + As a result of this bit being set, PDG will at certain moment + generate the MPDU limit TLV with field Num_mpdu_user set + to 0 + + PDG shall treat this user as a user without any data. All + rules related to terminating MU transmissions when too + many users do not have any data shall include this user + as a user having zero data. + + When clear, PDG can ignore this bit + +*/ + +#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 + + +/* Description MESH_AMSDU_MODE + + Consumer: TX OLE + Producer: SW + + This field is used only when the first MSDU of any MPDU + that TX OLE encounters is in Native WiFi format and includes + a 'Mesh Control' field between the header and the LLC. + + The creation of the A-MSDU 'Length' field in the MPDU (if + aggregating multiple MSDUs) is decided by the value of + this field. + + DO NOT USE + A-MSDU 'Length' is big endian and + includes the length of Mesh Control. + A-MSDU 'Length' is big endian + and excludes the length of Mesh Control. + A-MSDU 'Length' is little endian + and excludes the length of Mesh Control. This is 802.11s-compliant. + + + NOTE 1: For compatibility TXOLE treats MESH_MODE_0 identically + to MESH_MODE_Q2Q. + + NOTE 2: This e-numeration is different from other fields + named Mesh_sta or mesh_enable where the value zero disables + mesh processing. + +*/ + +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 + + + +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 + + +/* Description DL_UL_DIRECTION + + 'Direction' to be inferred for raw WiFi esp. management + frames sent to a multi-link peer, for translating RA and/or + TA. + + + + +*/ + +#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 + + +/* Description RESERVED_12 + + +*/ + +#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_RESERVED_12_LSB 20 +#define TX_PEER_ENTRY_RESERVED_12_MSB 31 +#define TX_PEER_ENTRY_RESERVED_12_MASK 0x00000000fff00000 + + +/* Description INSERT_VLAN_OUTER_TCI + + The tag control info to use when TXOLE inserts outer VLAN + if enabled by Strip_insert_vlan_outer and Insert_or_strip + +*/ + +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 + + +/* Description INSERT_VLAN_INNER_TCI + + The tag control info to use when TXOLE inserts inner VLAN + if enabled by Strip_insert_vlan_inner and Insert_or_strip + +*/ + +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 + + +/* Description MULTI_LINK_ADDR_AD1_31_0 + + Consumer: TX CRYPTO + Producer: FW + + Field only valid if Multi_link_addr_crypto_enable is set + + + Multi-link receiver address (address1) for transmissions + matching this peer entry, bits [31:0] +*/ + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x0000000000000038 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_LSB 0 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MSB 31 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MASK 0x00000000ffffffff + + +/* Description MULTI_LINK_ADDR_AD1_47_32 + + Consumer: TX CRYPTO + Producer: FW + + Field only valid if Multi_link_addr_crypto_enable is set + + + Multi-link receiver address (address1) for transmissions + matching this peer entry, bits [47:32] +*/ + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x0000000000000038 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_LSB 32 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MSB 47 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff00000000 + + +/* Description MULTI_LINK_ADDR_AD2_15_0 + + Consumer: TX CRYPTO + Producer: FW + + Field only valid if Multi_link_addr_crypto_enable is set + + + Multi-link transmitter address (address2) for transmissions + matching this peer entry, bits [15:0] +*/ + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x0000000000000038 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_LSB 48 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MSB 63 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff000000000000 + + +/* Description MULTI_LINK_ADDR_AD2_47_16 + + Consumer: TX CRYPTO + Producer: FW + + Field only valid if Multi_link_addr_crypto_enable is set + + + Multi-link transmitter address (address2) for transmissions + matching this peer entry, bits [47:16] +*/ + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_LSB 0 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MSB 31 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MASK 0x00000000ffffffff + + +/* Description MULTI_LINK_ADDR_CRYPTO_ENABLE + + Consumer: TX CRYPTO + Producer: FW + + If set, TX CRYPTO shall convert Address1, Address2 and BSSID + of received data frames to multi-link addresses for the + AAD and Nonce during encryption. + +*/ + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 + + +/* Description RESERVED_17A + + +*/ + +#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_RESERVED_17A_LSB 33 +#define TX_PEER_ENTRY_RESERVED_17A_MSB 47 +#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe00000000 + + +/* Description SW_PEER_ID + + This field indicates a unique peer identifier provided by + FW, to be logged via TXMON to host SW. + + +*/ + +#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 +#define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 +#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 + + + +#endif // TX_PEER_ENTRY diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_queue_extension.h b/drivers/staging/fw-api/hw/qcn6432/tx_queue_extension.h new file mode 100644 index 0000000000000000000000000000000000000000..f98b42e21791349dad83ced1baa771a10dce0ba5 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_queue_extension.h @@ -0,0 +1,833 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_QUEUE_EXTENSION_H_ +#define _TX_QUEUE_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 + +#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 7 + + +struct tx_queue_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t frame_ctl : 16, // [15:0] + qos_ctl : 16; // [31:16] + uint32_t ampdu_flag : 1, // [0:0] + tx_notify_no_htc_override : 1, // [1:1] + reserved_1a : 7, // [8:2] + checksum_tso_disable_for_frag : 1, // [9:9] + key_id : 8, // [17:10] + qos_buf_state_overwrite : 1, // [18:18] + buf_state_sta_id : 1, // [19:19] + buf_state_source : 1, // [20:20] + ht_control_overwrite_enable : 1, // [21:21] + ht_control_overwrite_source : 4, // [25:22] + reserved_1b : 6; // [31:26] + uint32_t ul_headroom_insertion_enable : 1, // [0:0] + ul_headroom_offset : 5, // [5:1] + bqrp_insertion_enable : 1, // [6:6] + bqrp_offset : 5, // [11:7] + ul_headroom_rsvd_7_6 : 2, // [13:12] + bqr_rsvd_9_8 : 2, // [15:14] + base_pn_63_48 : 16; // [31:16] + uint32_t base_pn_95_64 : 32; // [31:0] + uint32_t base_pn_127_96 : 32; // [31:0] + uint32_t ht_control_field_bw20 : 32; // [31:0] + uint32_t ht_control_field_bw40 : 32; // [31:0] + uint32_t ht_control_field_bw80 : 32; // [31:0] + uint32_t ht_control_field_bw160 : 32; // [31:0] + uint32_t ht_control_overwrite_mask : 32; // [31:0] + uint32_t cas_control_info : 8, // [7:0] + cas_offset : 5, // [12:8] + cas_insertion_enable : 1, // [13:13] + reserved_10a : 2, // [15:14] + ht_control_overwrite_source_for_srp : 4, // [19:16] + ht_control_overwrite_source_for_bsrp : 4, // [23:20] + reserved_10b : 6, // [29:24] + mpdu_hdr_len_override_en : 1, // [30:30] + bar_ssn_overwrite_enable : 1; // [31:31] + uint32_t bar_ssn_offset : 12, // [11:0] + mpdu_hdr_len_override_val : 9, // [20:12] + reserved_11a : 11; // [31:21] + uint32_t ht_control_field_bw320 : 32; // [31:0] + uint32_t fw2sw_info : 32; // [31:0] +#else + uint32_t qos_ctl : 16, // [31:16] + frame_ctl : 16; // [15:0] + uint32_t reserved_1b : 6, // [31:26] + ht_control_overwrite_source : 4, // [25:22] + ht_control_overwrite_enable : 1, // [21:21] + buf_state_source : 1, // [20:20] + buf_state_sta_id : 1, // [19:19] + qos_buf_state_overwrite : 1, // [18:18] + key_id : 8, // [17:10] + checksum_tso_disable_for_frag : 1, // [9:9] + reserved_1a : 7, // [8:2] + tx_notify_no_htc_override : 1, // [1:1] + ampdu_flag : 1; // [0:0] + uint32_t base_pn_63_48 : 16, // [31:16] + bqr_rsvd_9_8 : 2, // [15:14] + ul_headroom_rsvd_7_6 : 2, // [13:12] + bqrp_offset : 5, // [11:7] + bqrp_insertion_enable : 1, // [6:6] + ul_headroom_offset : 5, // [5:1] + ul_headroom_insertion_enable : 1; // [0:0] + uint32_t base_pn_95_64 : 32; // [31:0] + uint32_t base_pn_127_96 : 32; // [31:0] + uint32_t ht_control_field_bw20 : 32; // [31:0] + uint32_t ht_control_field_bw40 : 32; // [31:0] + uint32_t ht_control_field_bw80 : 32; // [31:0] + uint32_t ht_control_field_bw160 : 32; // [31:0] + uint32_t ht_control_overwrite_mask : 32; // [31:0] + uint32_t bar_ssn_overwrite_enable : 1, // [31:31] + mpdu_hdr_len_override_en : 1, // [30:30] + reserved_10b : 6, // [29:24] + ht_control_overwrite_source_for_bsrp : 4, // [23:20] + ht_control_overwrite_source_for_srp : 4, // [19:16] + reserved_10a : 2, // [15:14] + cas_insertion_enable : 1, // [13:13] + cas_offset : 5, // [12:8] + cas_control_info : 8; // [7:0] + uint32_t reserved_11a : 11, // [31:21] + mpdu_hdr_len_override_val : 9, // [20:12] + bar_ssn_offset : 12; // [11:0] + uint32_t ht_control_field_bw320 : 32; // [31:0] + uint32_t fw2sw_info : 32; // [31:0] +#endif +}; + + +/* Description FRAME_CTL + + Consumer: TXOLE + Producer: SW + + + 802.11 Frame control field: + fc [1:0]: Protocol Version + fc[7:2]: type/subtypeFor non-11ah fc[3:2] = Type fc[7:4] = + Subtype For 11ah fc[4:2] = Typefc[7:5] = PTID/SubType + fc [8]: To DS ( for Non-11ah) From DS ( for 11ah ) + fc [9]: From DS ( for Non-11ah ) + More Frag ( for 11ah ) + fc [10]: More Frag ( for Non-11ah ) + Power Management ( for 11ah) + fc [11]: Retry ( for Non-11ah ) + More Data ( for 11ah ) + fc [12]: Pwr Mgt ( for Non-11ah ) + Protected Frame ( for 11ah ) + fc [13]: More Data( for Non-11ah ) + EOSP ( for 11ah ) + fc [14]: Protected Frame ( for Non-11ah) + Relayed Frame ( for 11ah ) + fc [15]: Order ( for Non-11ah ) + Ack Policy ( for 11ah ) + Used by OLE during the encapsulation process for Native + WiFi, Ethernet II, and 802.3. + When the Order field is set, TXOLE shall insert 4 placeholder + bytes for the HE-control field in the frame. TXPCU will + overwrite them with the final actual value... +*/ + +#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff + + +/* Description QOS_CTL + + Consumer: TXOLE + Producer: SW + + QoS control field is valid if the type field is data and + the upper bit of the subtype field is set. The field decode + is as below: + qos_ctl[3:0]: TID + qos_ctl[4]: EOSP (with some exceptions) + qos_ctl[6:5]: Ack Policy + 0x0: Normal Ack or Implicit BAR + 0x1: No Ack + 0x2: No explicit Ack or PSMP Ack (not supported) + 0x3: Block Ack (Not supported) + Qos_ctl[7]: A-MSDU Present (with some exceptions) + Qos_ctl[15:8]: TXOP limit, AP PS buffer state, TXOP duration + requested or queue size + This field is inserted into the 802.11 header during the + encapsulation process + +*/ + +#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 +#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 +#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 + + +/* Description AMPDU_FLAG + + Consumer: PDG/TXPCU + Producer: SW + + Note: + For legacy rate transmissions (11 b and 11a, an 11g), this + bit shall always be set to zero. + + 0: + For legacy and .11n rates: + MPDUs are only allowed to be sent out 1 at a time in NON + A-MPDU format. + For .11ac and .11ax rates: + MPDUs are sent out in S-MPDU format (TXPCU sets the 'EOF' + bit in the MPDU delimiter). + 1: All MPDUs should be sent out using the A-MPDU format, + even if there is only one MPDU. + + Note that this bit should be set to 0 in order to construct + an S-MPDU frame. VHT and HE frames are all A-MPDU format + but if this bit is clear, EOF bit is set to 1 for the MPDU + delimiter in A-MPDU, which is the indicator of S-MPDU and + solicits ACK rather than BA as response frame. + + This bit shall be set to 1 for any MD (Multi Destination) + transmission. +*/ + +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 + + +/* Description TX_NOTIFY_NO_HTC_OVERRIDE + + When set, and a 'TX_MPDU_START' TLV has Tx_notify_frame + set to TX_HARD_NOTIFY or TX_SOFT_NOTIFY or TX_SEMI_HARD_NOTIFY, + then PDG would have updated the rate fields for a legacy + PPDU which may not support HT Control. + + In this case TXOLE shall not: + set the Order/+HTC bit in the 'Frame Control,' + include 4 bytes for TXPCU to fill the HT Control, or + set vht_control_present in 'TX_MPDU_START,' + even if requested, and instead shall subtract '4' from the + mpdu_length in 'TX_MPDU_START' and overwrite it. + + +*/ + +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 + + + +#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 + + +/* Description CHECKSUM_TSO_DISABLE_FOR_FRAG + + Field only valid in case of level-1 fragmentation, identified + by TXOLE getting the 'TX_FRAG_STATE' TLV + + If set, TXOLE disables all checksum and TSO overwrites for + the fragment(s) being transmitted. + + This is useful if it is known that the checksum and TSO + overwrites affect only the first fragment (or first few + fragments) and for the rest these can be safely disabled. + + + +*/ + +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 + + +/* Description KEY_ID + + Field only valid in case of encryption, and TXOLE being + instructured to insert the IV. + + TXOLE blindly copies this field into the key ID octet (which + is part of the IV) of the encrypted frame. + + For AES/TKIP the encoding is: + key_id_octet[7:6]: key ID + key_id_octet[5]: extended IV: + key_id_octet[4:0]: Reserved bits + + For WEP the encoding is: + key_id_octet[7:6]: key ID + key_id_octet[5]: extended IV: + key_id_octet[4:0]: Reserved bits + + For WAPI the encoding is: + key_id_octet[7:2]: Reserved bits + key_id_octet[1:0]: key ID + + +*/ + +#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 +#define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 +#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 + + +/* Description QOS_BUF_STATE_OVERWRITE + + When clear, TXPCU shall not overwrite buffer state field + in the QoS frame control field. + + When set, TXPCU shall overwrite the buffer state field in + the QoS frame control field, with info that SW has programmed + in TXPCU registers. Note that TXPCU shall pick up the values + related to this TID. + +*/ + +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 + + +/* Description BUF_STATE_STA_ID + + Field only valid when QoS_Buf_state_overwrite is set. + + This field indicates what the STA ID register source is + of the buffer status. + + 1'b0: TXPCU registers: STA0_buf_status_... + 1'b1: TXPCU registers: STA1_buf_status_... + +*/ + +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 + + +/* Description BUF_STATE_SOURCE + + Field only valid when QoS_Buf_state_overwrite is set. + + This field indicates what the source is of the actual value + TXPCU will insert + + TXPCU looks at the TID field + in the QoS control frame and based on this TID, selects + the buffer source value from the corresponding TID register. + + TXPCU inserts the value from + the buffer_state_sum register + + +*/ + +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 + + +/* Description HT_CONTROL_OVERWRITE_ENABLE + + When set, TXPCU shall overwrite some (or all) of the HT_CONTROL + field with values that are programmed in TXPCU registers: + HT_CONTROL_OVERWRITE_IX??? + + See HT/HE control overwrite order NOTE after this table + + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 + + +/* Description HT_CONTROL_OVERWRITE_SOURCE + + Field only valid when HT_control_overwrite_enable is set. + + + This field indicates the index of the TXPCU register HT_CONTROL_OVERWRITE_IX??? + That is the source of the overwrite data. + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 + + + +#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 + + +/* Description UL_HEADROOM_INSERTION_ENABLE + + When set, and this transmission services a trigger response + transmission, TXPCU shall create and insert the UL headroom + info in the HE control field, starting at offset indicated + by field: UL_headroom_offset + + See HT/HE control overwrite order NOTE after this table + +*/ + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 + + +/* Description UL_HEADROOM_OFFSET + + Field only valid when UL_headroom_insertion_enable is set. + + + The bit location in HE_CONTROL Field where TXPCU will start + writing the the 4 bit Control ID field that needs to be + inserted, followed by the lower 6 bits of the 8 bit bit + UL_headroom info (UPH Control). + + NOTE: currently on 6 bits are defined in the UPH control + field. The upper two bits are provided by SW in UL_headroom_rsvd_7_6. + + + +*/ + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e + + +/* Description BQRP_INSERTION_ENABLE + + When set, and this transmission services a BQRP trigger + response transmission, TXPCU shall create and insert the + BQR control field into the HE control field, as well as + the 4 bit preceding Control ID field. + + See HT/HE control overwrite order NOTE after this table + +*/ + +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 + + +/* Description BQRP_OFFSET + + Field only valid when BQRP_insertion_enable is set. + + The bit location in HE_CONTROL Field where TXPCU will start + writing the 4 bit Control ID field that needs to be inserted, + followed by the lower 8 bits of the 10 bit BQR control field. + + + NOTE: currently only 8 bits are defined in the 10 bit BQR + control field. The upper two bits are provided by SW in + BQR_rsvd_9_8. + + +*/ + +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 + + +/* Description UL_HEADROOM_RSVD_7_6 + + These will be used by TXPCU to fill the upper two bits of + the UPH control field. + +*/ + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 + + +/* Description BQR_RSVD_9_8 + + These will be used by TXPCU to fill the upper two bits of + the BQR control field. + NOTE: When overwriting CAS control (8-bit) at the same offset + as BQR control (10-bit), TXPCU will ignore the BQR overwrite, + including these upper two bits. + +*/ + +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 + + +/* Description BASE_PN_63_48 + + Upper bits PN number, in case a larger then 48 bit PN number + needs to be inserted in the transmit frame. + + 63-48 bits of the 128-bit packet number + +*/ + +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 + + +/* Description BASE_PN_95_64 + + Upper bits PN number, in case a larger then 48 bit PN number + needs to be inserted in the transmit frame. + + 95-64 bits of the 128-bit packet number + +*/ + +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 + + +/* Description BASE_PN_127_96 + + Upper bits PN number, in case a larger then 48 bit PN number + needs to be inserted in the transmit frame. + + 127-96 bits of the 128-bit packet number + +*/ + +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff + + +/* Description HT_CONTROL_FIELD_BW20 + + Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present + is set. + + Note that TXPCU might overwrite some fields. This is controlled + with field HT_control_overwrite_enable + + See HT/HE control overwrite order NOTE after this table + + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x0000000000000010 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff00000000 + + +/* Description HT_CONTROL_FIELD_BW40 + + Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present + is set. + + Note that TXPCU might overwrite some fields. This is controlled + with field HT_control_overwrite_enable + + See HT/HE control overwrite order NOTE after this table + + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x0000000000000018 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0x00000000ffffffff + + +/* Description HT_CONTROL_FIELD_BW80 + + Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present + is set. + + Note that TXPCU might overwrite some fields. This is controlled + with field HT_control_overwrite_enable + + See HT/HE control overwrite order NOTE after this table + + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000000000000018 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff00000000 + + +/* Description HT_CONTROL_FIELD_BW160 + + Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present + is set. + + Note that TXPCU might overwrite some fields. This is controlled + with field HT_control_overwrite_enable + + See HT/HE control overwrite order NOTE after this table + + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x0000000000000020 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0x00000000ffffffff + + +/* Description HT_CONTROL_OVERWRITE_MASK + + Field only valid when HT_control_overwrite_enable is set. + + + This field indicates which bits of the HT_CONTROL_FIELD + shall be overwritten with bits from TXPCU register HT_CONTROL_OVERWRITE_IX??? + + Every bit that needs to be overwritten is set to 1 in this + register. + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 + + +/* Description CAS_CONTROL_INFO + + This contains 8-bit CAS control field to be used for transmission + during SRP window + +*/ + +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff + + +/* Description CAS_OFFSET + + 5 bit offset for CAS insertion + +*/ + +#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 + + +/* Description CAS_INSERTION_ENABLE + + single bit used as ENABLE for CAS control insertion for + transmission during SRP window + +*/ + +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 + + +/* Description RESERVED_10A + + +*/ + +#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 + + +/* Description HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP + + 4-bit index similar to HT_control_overwrite_source field + to be used for transmission during SRP window + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 + + +/* Description HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP + + 4-bit index similar to HT_control_overwrite_source field + to be used for response to BSRP triggers (even during SRP + window) + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 + + +/* Description RESERVED_10B + + +*/ + +#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003f000000 + + +/* Description MPDU_HDR_LEN_OVERRIDE_EN + + This is for the FW override of MPDU overhead length programmed + in the TQM queue. + + If enabled, PDG will update the length of each MPDU by subtracting + the value of field Mpdu_header_length in 'MPDU_QUEUE_OVERVIEW' + and adding Mpdu_hdr_len_override_val (in this TLV). + +*/ + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 + + +/* Description BAR_SSN_OVERWRITE_ENABLE + + If enabled, TXPCU will overwrite the starting sequence number + in case of Tx BAR or MU-BAR Trigger from with the sequence + number from 'MPDU_QUEUE_OVERVIEW' + +*/ + +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 + + +/* Description BAR_SSN_OFFSET + + Offset to the starting sequence number in case of Tx BAR + or MU-BAR Trigger that TXPCU can overwrite with the sequence + number from 'MPDU_QUEUE_OVERVIEW' + +*/ + +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 + + +/* Description MPDU_HDR_LEN_OVERRIDE_VAL + + This is for the FW override of MPDU overhead length programmed + in the TQM queue. + + +*/ + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 + + + +#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 + + +/* Description HT_CONTROL_FIELD_BW320 + + Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present + is set. + + Note that TXPCU might overwrite some fields. This is controlled + with field HT_control_overwrite_enable + + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x0000000000000030 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0x00000000ffffffff + + +/* Description FW2SW_INFO + + This field is provided by FW, to be logged via TXMON to + host SW. It is transparent to HW. + + +*/ + +#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 32 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 63 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff00000000 + + + +#endif // TX_QUEUE_EXTENSION diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/qcn6432/tx_rate_stats_info.h new file mode 100644 index 0000000000000000000000000000000000000000..b46492f421051791ce27669ba1f3594ca99c6d05 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_rate_stats_info.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_RATE_STATS_INFO_H_ +#define _TX_RATE_STATS_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 + + +struct tx_rate_stats_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_rate_stats_info_valid : 1, // [0:0] + transmit_bw : 3, // [3:1] + transmit_pkt_type : 4, // [7:4] + transmit_stbc : 1, // [8:8] + transmit_ldpc : 1, // [9:9] + transmit_sgi : 2, // [11:10] + transmit_mcs : 4, // [15:12] + ofdma_transmission : 1, // [16:16] + tones_in_ru : 12, // [28:17] + transmit_nss : 3; // [31:29] + uint32_t ppdu_transmission_tsf : 32; // [31:0] +#else + uint32_t transmit_nss : 3, // [31:29] + tones_in_ru : 12, // [28:17] + ofdma_transmission : 1, // [16:16] + transmit_mcs : 4, // [15:12] + transmit_sgi : 2, // [11:10] + transmit_ldpc : 1, // [9:9] + transmit_stbc : 1, // [8:8] + transmit_pkt_type : 4, // [7:4] + transmit_bw : 3, // [3:1] + tx_rate_stats_info_valid : 1; // [0:0] + uint32_t ppdu_transmission_tsf : 32; // [31:0] +#endif +}; + + +/* Description TX_RATE_STATS_INFO_VALID + + When set all other fields in this STRUCT contain valid info. + + + When clear, none of the other fields contain valid info. + + +*/ + +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + + +/* Description TRANSMIT_BW + + Field only valid when Tx_rate_stats_info_valid is set + + Indicates the BW of the upcoming transmission that shall + likely start in about 3 -4 us on the medium + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e + + +/* Description TRANSMIT_PKT_TYPE + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + The packet type + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + + +/* Description TRANSMIT_STBC + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + When set, STBC transmission rate was used. +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100 + + +/* Description TRANSMIT_LDPC + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + When set, use LDPC transmission rates +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200 + + +/* Description TRANSMIT_SGI + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + Specify the right GI for HE-Ranging NDPs (11az)/Short NDP. + + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00 + + +/* Description TRANSMIT_MCS + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + For details, refer to MCS_TYPE description + +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 15 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0000f000 + + +/* Description OFDMA_TRANSMISSION + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + + Set when the transmission was an OFDMA transmission (DL + or UL). + +*/ + +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00010000 + + +/* Description TONES_IN_RU + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + The number of tones in the RU used. + +*/ + +#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 17 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1ffe0000 + + +/* Description TRANSMIT_NSS + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG + Not valid when in SW transmit mode + + The number of spatial streams used in the transmission + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB 29 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB 31 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK 0xe0000000 + + +/* Description PPDU_TRANSMISSION_TSF + + Field only valid when Tx_rate_stats_info_valid is set + + Based on a HWSCH configuration register setting, this field + either contains: + + Lower 32 bits of the TSF, snapshot of this value when transmission + of the PPDU containing the frame finished. + OR + Lower 32 bits of the TSF, snapshot of this value when transmission + of the PPDU containing the frame started + + +*/ + +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + + + +#endif // TX_RATE_STATS_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/qcn6432/tx_raw_or_native_frame_setup.h new file mode 100644 index 0000000000000000000000000000000000000000..da80a7b3c46b2b42b36301fcac0c0a947a6bfbc5 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/tx_raw_or_native_frame_setup.h @@ -0,0 +1,1024 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ +#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 + +#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 1 + + +struct tx_raw_or_native_frame_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fc_to_ds_mask : 1, // [0:0] + fc_from_ds_mask : 1, // [1:1] + fc_more_frag_mask : 1, // [2:2] + fc_retry_mask : 1, // [3:3] + fc_pwr_mgt_mask : 1, // [4:4] + fc_more_data_mask : 1, // [5:5] + fc_prot_frame_mask : 1, // [6:6] + fc_order_mask : 1, // [7:7] + duration_field_mask : 1, // [8:8] + sequence_control_mask : 1, // [9:9] + qc_tid_mask : 1, // [10:10] + qc_eosp_mask : 1, // [11:11] + qc_ack_policy_mask : 1, // [12:12] + qc_amsdu_mask : 1, // [13:13] + reserved_0a : 1, // [14:14] + qc_15to8_mask : 1, // [15:15] + iv_mask : 1, // [16:16] + fc_to_ds_setting : 1, // [17:17] + fc_from_ds_setting : 1, // [18:18] + fc_more_frag_setting : 1, // [19:19] + fc_retry_setting : 2, // [21:20] + fc_pwr_mgt_setting : 1, // [22:22] + fc_more_data_setting : 2, // [24:23] + fc_prot_frame_setting : 2, // [26:25] + fc_order_setting : 1, // [27:27] + qc_tid_setting : 4; // [31:28] + uint32_t qc_eosp_setting : 2, // [1:0] + qc_ack_policy_setting : 2, // [3:2] + qc_amsdu_setting : 1, // [4:4] + qc_15to8_setting : 8, // [12:5] + mlo_addr_override : 1, // [13:13] + mlo_ignore_addr3_override : 1, // [14:14] + sequence_control_source : 1, // [15:15] + fragment_number : 4, // [19:16] + sequence_number : 12; // [31:20] +#else + uint32_t qc_tid_setting : 4, // [31:28] + fc_order_setting : 1, // [27:27] + fc_prot_frame_setting : 2, // [26:25] + fc_more_data_setting : 2, // [24:23] + fc_pwr_mgt_setting : 1, // [22:22] + fc_retry_setting : 2, // [21:20] + fc_more_frag_setting : 1, // [19:19] + fc_from_ds_setting : 1, // [18:18] + fc_to_ds_setting : 1, // [17:17] + iv_mask : 1, // [16:16] + qc_15to8_mask : 1, // [15:15] + reserved_0a : 1, // [14:14] + qc_amsdu_mask : 1, // [13:13] + qc_ack_policy_mask : 1, // [12:12] + qc_eosp_mask : 1, // [11:11] + qc_tid_mask : 1, // [10:10] + sequence_control_mask : 1, // [9:9] + duration_field_mask : 1, // [8:8] + fc_order_mask : 1, // [7:7] + fc_prot_frame_mask : 1, // [6:6] + fc_more_data_mask : 1, // [5:5] + fc_pwr_mgt_mask : 1, // [4:4] + fc_retry_mask : 1, // [3:3] + fc_more_frag_mask : 1, // [2:2] + fc_from_ds_mask : 1, // [1:1] + fc_to_ds_mask : 1; // [0:0] + uint32_t sequence_number : 12, // [31:20] + fragment_number : 4, // [19:16] + sequence_control_source : 1, // [15:15] + mlo_ignore_addr3_override : 1, // [14:14] + mlo_addr_override : 1, // [13:13] + qc_15to8_setting : 8, // [12:5] + qc_amsdu_setting : 1, // [4:4] + qc_ack_policy_setting : 2, // [3:2] + qc_eosp_setting : 2; // [1:0] +#endif +}; + + +/* Description FC_TO_DS_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + Note: Enc_type is NOT allowed b + + Note: + When enc_type != RAW or Native WiFi, OLE will get the setting + from the frame_ctl field in the MPDU_queue extension data + structure. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_to_ds_setting. + : HW is not allowed to update the contents + of this field. + + + + In 11ah mode of Operation, same description as above applies + if this field is a part of FC field of the MPDU. This field + does not apply to Short MAC header (PV=1) and is ignored + by HW +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x0000000000000001 + + +/* Description FC_FROM_DS_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will get the setting + from the frame_ctl field in the MPDU_queue extension data + structure. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_from_ds_setting. + : HW is not allowed to update the contents + of this field. + + + + In 11ah mode of Operation, same description as above applies + if this field is a part of FC field of the MPDU. +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x0000000000000002 + + +/* Description FC_MORE_FRAG_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will get the setting + from the frame_ctl field in the MPDU_queue extension data + structure. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_more_frag_setting. + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x0000000000000004 + + +/* Description FC_RETRY_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the setting + for this field on the retry_bitmap_31_0 and retry_bitmap_63_32 + fields in the MPDU_queue_extension descriptor + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_retry_setting. + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x0000000000000008 + + +/* Description FC_PWR_MGT_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will get the setting + from the frame_ctl field in the MPDU_queue extension data + structure. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_pwr_mgt_setting. + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x0000000000000010 + + +/* Description FC_MORE_DATA_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will get the setting + from the frame_ctl field in the MPDU_queue extension data + structure. + + TX_PCU has the abilty of overwrite the More data field, + based on the Set_fc_more_data field in the PPDU_SS_... TLVs + given by PDG. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_more_data_setting. + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x0000000000000020 + + +/* Description FC_PROT_FRAME_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the setting + for the Protected frame bit on the key_type setting in + the peer entry. When NO encryption is needed, the bit will + be set to 0, When the any encryption is needed, the bit + will be set to 0. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_prot_frame_setting. When fc_prot_frame_setting is set, + OLE will encrypt the frame, based on the encryption type + indicate with the key_type setting in the peer entry + + : HW is not allowed to update the contents + of this field. + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x0000000000000040 + + +/* Description FC_ORDER_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will get the setting + from the frame_ctl field in the MPDU_queue extension data + structure. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_order_setting. + : HW is not allowed to update the contents + of this field. + + + + In 11ah mode of Operation, same description as above applies + if this field is a part of FC field of the MPDU. +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x0000000000000080 + + +/* Description DURATION_FIELD_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, TX PCU will get the + value for this field from the Duration fields in the PPDU_SS_... + TLVs from PDG. + + : HW is allowed to update this field. + The value that HW (TX_PCU) will insert is coming from the + Duration fields in the PPDU_SS_... TLVs from PDG (similar + as with NON RAW/Native WiFi frames). + : HW is not allowed to update the contents + of this field. + + + + In 11ah mode of Operation, same description as above applies + if this field is a part of FC field of the MPDU. +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x0000000000000100 + + +/* Description SEQUENCE_CONTROL_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the value + for this field on sequence number field in the TX_MPDU_START + descriptor + + : HW is allowed to update this field. + The value that HW (OLE) will insert is dependent on the + setting in the 'sequence_control_source' field + + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x0000000000000200 + + +/* Description QC_TID_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the value + for this field on the qos_ctl field from the MPDU_queue_ext + data structure. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + qc_tid_setting. + + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x0000000000000400 + + +/* Description QC_EOSP_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the value + for this field on the qos_ctl field from the MPDU_queue_ext + data structure. + + TX_PCU has the abilty of overwrite the QoS eosp field, based + on the Set_fc_more_data field in the PPDU_SS_... TLVs given + by PDG. + + : HW is allowed to update the QoS eosp + field. The value that HW (OLE) will insert is the given + in field: qc_eosp_setting. + + : HW is not allowed to update the contents + of this field. + + + + In 11ah mode of Operation, same description as above applies + if this field is a part of FC field of the MPDU. +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x0000000000000800 + + +/* Description QC_ACK_POLICY_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the value + for this field on the qos_ctl field from the MPDU_queue_ext + data structure. + + : HW is allowed to update the QoS ack + policy field. The value that HW (OLE) will insert is determined + by field: qc_ack_policy_setting. + + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x0000000000001000 + + +/* Description QC_AMSDU_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the value + for this field on the qos_ctl field from the MPDU_queue_ext + data structure. + + : HW is allowed to update the QoS amsdu + field. The value that HW (OLE) will insert is determined + by field: qc_amsdu_setting. + + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x0000000000002000 + + +/* Description RESERVED_0A + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x0000000000004000 + + +/* Description QC_15TO8_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the value + for this field on the qos_ctl field from the MPDU_queue_ext + data structure. + + : HW is allowed to update the QoS control + field, bits 15-8. The value that HW (OLE) will insert is + determined by field: qc_15to8_setting. + + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x0000000000008000 + + +/* Description IV_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the IV + field insertion/value on the on the encryption type indicate + with the key_type setting in the peer entry + + : OLE is allowed to overwrite the IV + field, in case key_type setting in the peer entry indicates + some encryption. + + : OLE is not allowed to overwrite any + of the IV field contents. + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x0000000000010000 + + +/* Description FC_TO_DS_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_to_ds_mask is not set. + + : OLE will set the frame control field, to + ds bit to 0 + : OLE will set the frame control field, to ds + bit to 1 + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x0000000000020000 + + +/* Description FC_FROM_DS_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_from_ds_mask is not set. + + : OLE will set the frame control field, from + ds bit to 0 + : OLE will set the frame control field, from + ds bit to 1 + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x0000000000040000 + + +/* Description FC_MORE_FRAG_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_more_frag_mask is not set. + + + : OLE will set the frame control field, more + frag bit to 0 + : OLE will set the frame control field, more + frag bit to 1 + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x0000000000080000 + + +/* Description FC_RETRY_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_retry_mask is not set. + + : OLE will set the frame control + field, retry bit to 0 + : OLE will set the frame control field, + retry bit to 1 + : OLE will base the setting + for this field on the retry_bitmap_31_0 and retry_bitmap_63_32 + fields in the MPDU_queue_extension descriptor + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x0000000000300000 + + +/* Description FC_PWR_MGT_SETTING + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_pwr_mgt_mask is not set. + + : OLE will set the frame control field, pwr_mgt + bit to 0 + : OLE will set the frame control field, pwr_mgt + bit to 1 + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x0000000000400000 + + +/* Description FC_MORE_DATA_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_more_Data_mask is not set. + + + : OLE will set the frame control + field, More data bit to 0 + : OLE will set the frame control + field, More data bit to 1 + + : OLE will set the Frame + control, More data bit to 0, but TX_PCU has the abilty to + overwrite this based on the Set_fc_more_data field in the + PPDU_SS_... TLVs given by PDG. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x0000000001800000 + + +/* Description FC_PROT_FRAME_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_prot_frame_mask is not set. + + + : OLE will set the frame control + field , "Protected Frame" bit to 0 + : OLE will set the frame control + field , "Protected Frame" bit to 1 + : OLE configures + the Frame Control field, Prot frame bit according to the + following rule: + When the encryption type indicated with the key_type setting + in the peer entry is set to no crypto, the Frame control + "Protected Frame" bit is set to 0. + When the encryption type indicated with the key_type setting + in the peer entry is set to some encryption type, the OLE + will set the frame control "Protected Frame" bit to 1. + OLE changes only the value of the prot_frame bit. It won't + push IV in the frame according to this bit. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x0000000006000000 + + +/* Description FC_ORDER_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_order_mask is not set. + + : OLE will set the frame control field , order + bit to 0 + : OLE will set the frame control field , order + bit to 1 + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x0000000008000000 + + +/* Description QC_TID_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Qc_tid_mask is not set. + + OLE sets the TID field in the QoS control field to this + value. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0x00000000f0000000 + + +/* Description QC_EOSP_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Qc_eosp_mask is not set. + + : OLE will set the QoS control bit + to 0 + : OLE will set the QoS control bit to + 1 + : OLE will set the QoS control + bit to 0, but TX_PCU has the abilty of overwrite the QoS + eosp field, based on the Set_fc_more_data field in the + PPDU_SS_... TLVs given by PDG. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 32 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 33 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x0000000300000000 + + +/* Description QC_ACK_POLICY_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Qc_ack_policy_mask is not set. + + + This is is QoS ACK policy value that RXOLE shall put in + the ACK policy field in the QoS control field + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 34 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 35 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c00000000 + + +/* Description QC_AMSDU_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Qc_amsdu_mask is not set. + + : OLE will set the QoS control field amsdu + bit to 0 + : OLE will set the QoS control field amsdu bit + to 1 + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 36 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 36 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x0000001000000000 + + +/* Description QC_15TO8_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Qc_15to8_mask is not set. + + OLE sets bit 8 to 16 in the QoS control field to this value. + + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 37 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 44 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe000000000 + + +/* Description MLO_ADDR_OVERRIDE + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + + Enables address translation for raw Wi-Fi frames to multi-link + peers, esp. management frames + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 45 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 45 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x0000200000000000 + + +/* Description MLO_IGNORE_ADDR3_OVERRIDE + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi when Mlo_addr_override is set. + + Preserves Address3 (BSSID) for raw Wi-Fi management frames + to multi-link peers. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 46 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 46 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x0000400000000000 + + +/* Description SEQUENCE_CONTROL_SOURCE + + Field only valid when field Sequence_control_mask is set + to 'mask_disable'. + + : OLE will set the sequence + control field based on what is indicated in the TX_MPDU_START + TLV. + + : OLE will set the sequence + control field based on what is indicated in this TLV, fields + Fragment_number and Sequence_number + Note that this setting assumes that there is only a single + RAW or Native Wifi MPDU for this user in the transmit path. + This works well for level 1 fragmentation. Reason that there + should only be a single RAW or Native WiFi frames is that + with this feature they would all get the same sequence + + fragment number + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 47 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 47 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x0000800000000000 + + +/* Description FRAGMENT_NUMBER + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + + Field only valid when field Sequence_control_mask = mask_disable + AND sequence_control_source is set to seq_ctrl_source_this_tlv + + + The Fragment number to be filled in + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 48 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 51 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f000000000000 + + +/* Description SEQUENCE_NUMBER + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + + Field only valid when field Sequence_control_mask = mask_disable + AND sequence_control_source is set to seq_ctrl_source_this_tlv + + + The Sequence number to be filled in + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 52 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 63 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff0000000000000 + + + +#endif // TX_RAW_OR_NATIVE_FRAME_SETUP diff --git a/drivers/staging/fw-api/hw/qcn6432/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/qcn6432/txpcu_buffer_basics.h new file mode 100644 index 0000000000000000000000000000000000000000..09648f63351e8e7c6515717704b1c3f6fa9b6f13 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/txpcu_buffer_basics.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TXPCU_BUFFER_BASICS_H_ +#define _TXPCU_BUFFER_BASICS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 + + +struct txpcu_buffer_basics { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t available_memory : 8, // [7:0] + partial_tx_data_tlv_count : 8, // [15:8] + tx_data_tlv_count : 16; // [31:16] +#else + uint32_t tx_data_tlv_count : 16, // [31:16] + partial_tx_data_tlv_count : 8, // [15:8] + available_memory : 8; // [7:0] +#endif +}; + + +/* Description AVAILABLE_MEMORY + + The amount of TX_FIFO memory in 128 byte units that is available. + + TXPCU gets this from the Avail_fifo_mem signal from SFM. + + + When SFM is indicating a larger available amount, that value + shall be saturated to 0xFF in this field. + + +*/ + +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff + + +/* Description PARTIAL_TX_DATA_TLV_COUNT + + The number of 16 bytes units received of the TX_DATA TLV + that is currently under reception by TXPCU. + Value saturates at 255 in case TX_DATA TLV length is larger + then 4080 bytes. This is unlikely as TX_DATA will generally + not be larger then then the Max MSDU size. + +*/ + +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + + +/* Description TX_DATA_TLV_COUNT + + The number of completely received TX_DATA TLVs (of all the + users together) received by TXPCU + +*/ + +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 + + + +#endif // TXPCU_BUFFER_BASICS diff --git a/drivers/staging/fw-api/hw/qcn6432/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/qcn6432/txpcu_buffer_status.h new file mode 100644 index 0000000000000000000000000000000000000000..7969b926911eba8f81c9b0f93fcee71f59cb46ed --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/txpcu_buffer_status.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TXPCU_BUFFER_STATUS_H_ +#define _TXPCU_BUFFER_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 + +#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1 + + +struct txpcu_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t reserved : 15, // [14:0] + msdu_end : 1, // [15:15] + tx_data_sync_value : 16; // [31:16] +#else + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t tx_data_sync_value : 16, // [31:16] + msdu_end : 1, // [15:15] + reserved : 15; // [14:0] +#endif +}; + + +/* Description TXPCU_BASIX_BUFFER_INFO + + Global overview of the TXPCU buffer + +*/ + + +/* Description AVAILABLE_MEMORY + + The amount of TX_FIFO memory in 128 byte units that is available. + + TXPCU gets this from the Avail_fifo_mem signal from SFM. + + + When SFM is indicating a larger available amount, that value + shall be saturated to 0xFF in this field. + + +*/ + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff + + +/* Description PARTIAL_TX_DATA_TLV_COUNT + + The number of 16 bytes units received of the TX_DATA TLV + that is currently under reception by TXPCU. + Value saturates at 255 in case TX_DATA TLV length is larger + then 4080 bytes. This is unlikely as TX_DATA will generally + not be larger then then the Max MSDU size. + +*/ + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 + + +/* Description TX_DATA_TLV_COUNT + + The number of completely received TX_DATA TLVs (of all the + users together) received by TXPCU + +*/ + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 + + +/* Description RESERVED + + +*/ + +#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_RESERVED_LSB 32 +#define TXPCU_BUFFER_STATUS_RESERVED_MSB 46 +#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000 + + +/* Description MSDU_END + + Bit to indicate that TXPCU has received an entire MSDU and + 'TX_MSDU_END' + +*/ + +#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47 +#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47 +#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 + + +/* Description TX_DATA_SYNC_VALUE + + The last received sync_value number from the TX_DATA_SYNC + TLV + At reception of TX_FES_SETUP, TXPCU initializes this value + to 0 + +*/ + +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 + + + +#endif // TXPCU_BUFFER_STATUS diff --git a/drivers/staging/fw-api/hw/qcn6432/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/qcn6432/txpcu_user_buffer_status.h new file mode 100644 index 0000000000000000000000000000000000000000..3c5a6fa7370592f7df09fd6da496be60e4dc3624 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/txpcu_user_buffer_status.h @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TXPCU_USER_BUFFER_STATUS_H_ +#define _TXPCU_USER_BUFFER_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 + +#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1 + + +struct txpcu_user_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t stored_word_count_user : 14, // [13:0] + reserved_1a : 1, // [14:14] + msdu_end : 1, // [15:15] + tx_data_sync_value : 16; // [31:16] +#else + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t tx_data_sync_value : 16, // [31:16] + msdu_end : 1, // [15:15] + reserved_1a : 1, // [14:14] + stored_word_count_user : 14; // [13:0] +#endif +}; + + +/* Description TXPCU_BASIC_BUFFER_INFO + + Global overview of the TXPCU buffer + +*/ + + +/* Description AVAILABLE_MEMORY + + The amount of TX_FIFO memory in 128 byte units that is available. + + TXPCU gets this from the Avail_fifo_mem signal from SFM. + + + When SFM is indicating a larger available amount, that value + shall be saturated to 0xFF in this field. + + +*/ + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff + + +/* Description PARTIAL_TX_DATA_TLV_COUNT + + The number of 16 bytes units received of the TX_DATA TLV + that is currently under reception by TXPCU. + Value saturates at 255 in case TX_DATA TLV length is larger + then 4080 bytes. This is unlikely as TX_DATA will generally + not be larger then then the Max MSDU size. + +*/ + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 + + +/* Description TX_DATA_TLV_COUNT + + The number of completely received TX_DATA TLVs (of all the + users together) received by TXPCU + +*/ + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 + + +/* Description STORED_WORD_COUNT_USER + + Number of 4 word units (4 x 32 bits) stored for this user + in the buffer + + +*/ + +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 32 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 45 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 46 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 46 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x0000400000000000 + + +/* Description MSDU_END + + Bit to indicate that TXPCU has received an entire MSDU and + 'TX_MSDU_END' + +*/ + +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 47 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 47 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 + + +/* Description TX_DATA_SYNC_VALUE + + The last received sync_value number from the TX_DATA_SYNC + TLV + At reception of TX_FES_SETUP, TXPCU initializes this value + to 0 + +*/ + +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 + + + +#endif // TXPCU_USER_BUFFER_STATUS diff --git a/drivers/staging/fw-api/hw/qcn6432/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/qcn6432/u_sig_eht_su_mu_info.h new file mode 100644 index 0000000000000000000000000000000000000000..6346a7a49c75cb8b0280ff508d39577441a63ede --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/u_sig_eht_su_mu_info.h @@ -0,0 +1,376 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _U_SIG_EHT_SU_MU_INFO_H_ +#define _U_SIG_EHT_SU_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 + + +struct u_sig_eht_su_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, // [2:0] + transmit_bw : 3, // [5:3] + dl_ul_flag : 1, // [6:6] + bss_color_id : 6, // [12:7] + txop_duration : 7, // [19:13] + disregard_0a : 5, // [24:20] + validate_0b : 1, // [25:25] + reserved_0c : 6; // [31:26] + uint32_t eht_ppdu_sig_cmn_type : 2, // [1:0] + validate_1a : 1, // [2:2] + punctured_channel_information : 5, // [7:3] + validate_1b : 1, // [8:8] + mcs_of_eht_sig : 2, // [10:9] + num_eht_sig_symbols : 5, // [15:11] + crc : 4, // [19:16] + tail : 6, // [25:20] + dot11ax_su_extended : 1, // [26:26] + reserved_1d : 3, // [29:27] + rx_ndp : 1, // [30:30] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0c : 6, // [31:26] + validate_0b : 1, // [25:25] + disregard_0a : 5, // [24:20] + txop_duration : 7, // [19:13] + bss_color_id : 6, // [12:7] + dl_ul_flag : 1, // [6:6] + transmit_bw : 3, // [5:3] + phy_version : 3; // [2:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + rx_ndp : 1, // [30:30] + reserved_1d : 3, // [29:27] + dot11ax_su_extended : 1, // [26:26] + tail : 6, // [25:20] + crc : 4, // [19:16] + num_eht_sig_symbols : 5, // [15:11] + mcs_of_eht_sig : 2, // [10:9] + validate_1b : 1, // [8:8] + punctured_channel_information : 5, // [7:3] + validate_1a : 1, // [2:2] + eht_ppdu_sig_cmn_type : 2; // [1:0] +#endif +}; + + +/* Description PHY_VERSION + + + Values 1 - 7 are reserved. + 20 MHz + 40 MHz + 80 MHz + 160 MHz + 320 MHz + DO NOT USE + + Microcode remaps 'U_SIG_BW320' based on channelization. + + On RX side, field used by MAC HW + +*/ + +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field used by MAC HW + +*/ + +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field used by MAC HW + +*/ + +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 + + +/* Description DISREGARD_0A + + Note: spec indicates this shall be set to 1s + +*/ + +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 + + +/* Description VALIDATE_0B + + Note: spec indicates this shall be set to 1 + +*/ + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 + + +/* Description RESERVED_0C + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 + + +/* Description EHT_PPDU_SIG_CMN_TYPE + + DO NOT USE + Need to look at both + EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO) + + Need to look at both EHT-SIG + content channels + Need to look at only one EHT-SIG + content channel + +*/ + +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + + +/* Description VALIDATE_1A + + Note: spec indicates this shall be set to 1 + +*/ + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 + + +/* Description PUNCTURED_CHANNEL_INFORMATION + + For OFDMA BW 20 MHz or 40 MHz: + Set to all 1s, i.e. 31 + + For OFDMA of higher BW: + Bit 3 = lowest 20 MHz in the current 80 MHz + Bit 6 = highest 20 MHz in the current 80 MHz + Bit 7 = 1 + + Each bit indicates whether the 20 MHz is modulated or punctured + + 0 = punctured + 1 = modulated + + For non-OFDMA: + Set to a 5-bit value encoding the puncture pattern, a.k.a. 'U_sig_puncture_pattern_encoding' + elsewhere in the data structures + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 + + +/* Description VALIDATE_1B + + Note: spec indicates this shall be set to 1 + +*/ + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 + + +/* Description MCS_OF_EHT_SIG + + Indicates the MCS of EHT-SIG + 0 - 1: MCS 0 - 1 + 2: MCS 3 + 3: MCS 0 with DCM + +*/ + +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 + + +/* Description NUM_EHT_SIG_SYMBOLS + + Number of symbols + + The actual number of symbols is 1 larger than indicated + in this field. + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 + + +/* Description CRC + + CRC for U-SIG contents + +*/ + +#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 +#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 + + +/* Description TAIL + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 + + +/* Description DOT11AX_SU_EXTENDED + + TX side: + Set to 0 + + RX side: On RX side, evaluated by MAC HW + + This is the only way for MAC RX to know that this was a + U_SIG_EHT_SU received in extended range format. + + When set, the 11be frame is of the extended range format. + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + + +/* Description RESERVED_1D + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 + + +/* Description RX_NDP + + TX side: + Set to 0 + + RX side: On RX side, looked at by MAC HW + + When set, PHY has received an (expected) NDP frame + +*/ + +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the U-SIG CRC check + has passed, else set to 0 + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // U_SIG_EHT_SU_MU_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/qcn6432/u_sig_eht_tb_info.h new file mode 100644 index 0000000000000000000000000000000000000000..ba8f462574012ea3fa4bbd4a89f2fd7555c5d2ba --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/u_sig_eht_tb_info.h @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _U_SIG_EHT_TB_INFO_H_ +#define _U_SIG_EHT_TB_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 + + +struct u_sig_eht_tb_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, // [2:0] + transmit_bw : 3, // [5:3] + dl_ul_flag : 1, // [6:6] + bss_color_id : 6, // [12:7] + txop_duration : 7, // [19:13] + disregard_0a : 6, // [25:20] + reserved_0c : 6; // [31:26] + uint32_t eht_ppdu_sig_cmn_type : 2, // [1:0] + validate_1a : 1, // [2:2] + spatial_reuse : 8, // [10:3] + disregard_1b : 5, // [15:11] + crc : 4, // [19:16] + tail : 6, // [25:20] + reserved_1c : 5, // [30:26] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0c : 6, // [31:26] + disregard_0a : 6, // [25:20] + txop_duration : 7, // [19:13] + bss_color_id : 6, // [12:7] + dl_ul_flag : 1, // [6:6] + transmit_bw : 3, // [5:3] + phy_version : 3; // [2:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_1c : 5, // [30:26] + tail : 6, // [25:20] + crc : 4, // [19:16] + disregard_1b : 5, // [15:11] + spatial_reuse : 8, // [10:3] + validate_1a : 1, // [2:2] + eht_ppdu_sig_cmn_type : 2; // [1:0] +#endif +}; + + +/* Description PHY_VERSION + + + Values 1 - 7 are reserved. + +*/ + +#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU, as indicated in the trigger frame + + + 20 MHz + 40 MHz + 80 MHz + 160 MHz + 320 MHz channelization scheme 1 + 320 MHz channelization scheme 2 + + On RX side, field used by MAC HW + +*/ + +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field used by MAC HW + +*/ + +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field used by MAC HW + +*/ + +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 + + +/* Description DISREGARD_0A + + Set to value indicated in the trigger frame + +*/ + +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 + + +/* Description RESERVED_0C + + +*/ + +#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 + + +/* Description EHT_PPDU_SIG_CMN_TYPE + + DO NOT USE + Need to look at both + EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO) + + Need to look at both EHT-SIG + content channels + Need to look at only one EHT-SIG + content channel + +*/ + +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + + +/* Description VALIDATE_1A + + Set to value indicated in the trigger frame + +*/ + +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 + + +/* Description SPATIAL_REUSE + + TODO: Placeholder + +*/ + +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 + + +/* Description DISREGARD_1B + + Set to value indicated in the trigger frame + +*/ + +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 + + +/* Description CRC + + CRC for U-SIG contents + +*/ + +#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_CRC_LSB 16 +#define U_SIG_EHT_TB_INFO_CRC_MSB 19 +#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 + + +/* Description TAIL + + +*/ + +#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 +#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 +#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 + + +/* Description RESERVED_1C + + +*/ + +#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the U-SIG CRC check + has passed, else set to 0 + + +*/ + +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // U_SIG_EHT_TB_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/qcn6432/unallocated_ru_160_info.h new file mode 100644 index 0000000000000000000000000000000000000000..04c613a0a3223b41e692d82618c93d5a8a0914ea --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/unallocated_ru_160_info.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _UNALLOCATED_RU_160_INFO_H_ +#define _UNALLOCATED_RU_160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 + + +struct unallocated_ru_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t subband80_0_cc0 : 8, // [7:0] + subband80_0_cc1 : 8, // [15:8] + subband80_1_cc0 : 8, // [23:16] + subband80_1_cc1 : 8; // [31:24] +#else + uint32_t subband80_1_cc1 : 8, // [31:24] + subband80_1_cc0 : 8, // [23:16] + subband80_0_cc1 : 8, // [15:8] + subband80_0_cc0 : 8; // [7:0] +#endif +}; + + +/* Description SUBBAND80_0_CC0 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 0 (HE_SIGB0 or EHT_SIG0) + for the lower 80 MHz + + Valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 + +*/ + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff + + +/* Description SUBBAND80_0_CC1 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 1 (HE_SIGB1 or EHT_SIG1) + for the lower 80 MHz + + Valid for HE_40/HE_80/HE_160 (80+80)/ EHT_40/EHT_80/EHT_160/EHT_240/EHT_320 + + +*/ + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 + + +/* Description SUBBAND80_1_CC0 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 0 (HE_SIGB0 or EHT_SIG0) + for the higher 80 MHz + + Valid for EHT_160/EHT_240/EHT_320 + All 80 MHz subbands are identical for HE_160 (80+80). + +*/ + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 + + +/* Description SUBBAND80_1_CC1 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 1 (HE_SIGB1 or EHT_SIG1) + for the higher 80 MHz + + Valid for EHT_160/EHT_240/EHT_320 + All 80 MHz subbands are identical for HE_160 (80+80). + +*/ + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 + + + +#endif // UNALLOCATED_RU_160_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/qcn6432/uniform_descriptor_header.h new file mode 100644 index 0000000000000000000000000000000000000000..89aefa9765c57c71b8c8d90243e92c92190a932e --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/uniform_descriptor_header.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ +#define _UNIFORM_DESCRIPTOR_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 + + +struct uniform_descriptor_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t owner : 4, // [3:0] + buffer_type : 4, // [7:4] + tx_mpdu_queue_number : 20, // [27:8] + reserved_0a : 4; // [31:28] +#else + uint32_t reserved_0a : 4, // [31:28] + tx_mpdu_queue_number : 20, // [27:8] + buffer_type : 4, // [7:4] + owner : 4; // [3:0] +#endif +}; + + +/* Description OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + The owner of this data structure: + Buffer Manager currently owns this data + structure. + Software of FW currently owns this + data structure. + Transmit Queue Manager currently owns + this data structure. + Receive DMA currently owns this data + structure. + Reorder currently owns this data structure. + + SWITCH currently owns this data structure. + + + +*/ + +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + +/* Description BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Field describing what contents format is of this descriptor + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + +*/ + +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + +/* Description TX_MPDU_QUEUE_NUMBER + + Consumer: TQM/Debug + Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) + + Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor + + + Indicates the MPDU queue ID to which this MPDU descriptor + belongs + Used for tracking and debugging + + +*/ + +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + + +/* Description RESERVED_0A + + +*/ + +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + + + +#endif // UNIFORM_DESCRIPTOR_HEADER diff --git a/drivers/staging/fw-api/hw/qcn6432/uniform_reo_cmd_header.h b/drivers/staging/fw-api/hw/qcn6432/uniform_reo_cmd_header.h new file mode 100644 index 0000000000000000000000000000000000000000..92d8880f80491008ac94b1d293563b7b77cc1934 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/uniform_reo_cmd_header.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _UNIFORM_REO_CMD_HEADER_H_ +#define _UNIFORM_REO_CMD_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1 + + +struct uniform_reo_cmd_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_cmd_number : 16, // [15:0] + reo_status_required : 1, // [16:16] + reserved_0a : 15; // [31:17] +#else + uint32_t reserved_0a : 15, // [31:17] + reo_status_required : 1, // [16:16] + reo_cmd_number : 16; // [15:0] +#endif +}; + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + + +/* Description RESERVED_0A + + +*/ + +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_LSB 17 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + + + +#endif // UNIFORM_REO_CMD_HEADER diff --git a/drivers/staging/fw-api/hw/qcn6432/uniform_reo_status_header.h b/drivers/staging/fw-api/hw/qcn6432/uniform_reo_status_header.h new file mode 100644 index 0000000000000000000000000000000000000000..956331f6fa768670e497f551c2e40e99d1e3d707 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/uniform_reo_status_header.h @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _UNIFORM_REO_STATUS_HEADER_H_ +#define _UNIFORM_REO_STATUS_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2 + + +struct uniform_reo_status_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_status_number : 16, // [15:0] + cmd_execution_time : 10, // [25:16] + reo_cmd_execution_status : 2, // [27:26] + reserved_0a : 4; // [31:28] + uint32_t timestamp : 32; // [31:0] +#else + uint32_t reserved_0a : 4, // [31:28] + reo_cmd_execution_status : 2, // [27:26] + cmd_execution_time : 10, // [25:16] + reo_status_number : 16; // [15:0] + uint32_t timestamp : 32; // [31:0] +#endif +}; + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + + +/* Description RESERVED_0A + + +*/ + +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_LSB 28 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + + + +#endif // UNIFORM_REO_STATUS_HEADER diff --git a/drivers/staging/fw-api/hw/qcn6432/vht_sig_a_info.h b/drivers/staging/fw-api/hw/qcn6432/vht_sig_a_info.h new file mode 100644 index 0000000000000000000000000000000000000000..0389198647b883317f6436f07129c192cb848029 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/vht_sig_a_info.h @@ -0,0 +1,386 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_A_INFO_H_ +#define _VHT_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 + + +struct vht_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t bandwidth : 2, // [1:0] + vhta_reserved_0 : 1, // [2:2] + stbc : 1, // [3:3] + group_id : 6, // [9:4] + n_sts : 12, // [21:10] + txop_ps_not_allowed : 1, // [22:22] + vhta_reserved_0b : 1, // [23:23] + reserved_0 : 8; // [31:24] + uint32_t gi_setting : 2, // [1:0] + su_mu_coding : 1, // [2:2] + ldpc_extra_symbol : 1, // [3:3] + mcs : 4, // [7:4] + beamformed : 1, // [8:8] + vhta_reserved_1 : 1, // [9:9] + crc : 8, // [17:10] + tail : 6, // [23:18] + reserved_1 : 7, // [30:24] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0 : 8, // [31:24] + vhta_reserved_0b : 1, // [23:23] + txop_ps_not_allowed : 1, // [22:22] + n_sts : 12, // [21:10] + group_id : 6, // [9:4] + stbc : 1, // [3:3] + vhta_reserved_0 : 1, // [2:2] + bandwidth : 2; // [1:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_1 : 7, // [30:24] + tail : 6, // [23:18] + crc : 8, // [17:10] + vhta_reserved_1 : 1, // [9:9] + beamformed : 1, // [8:8] + mcs : 4, // [7:4] + ldpc_extra_symbol : 1, // [3:3] + su_mu_coding : 1, // [2:2] + gi_setting : 2; // [1:0] +#endif +}; + + +/* Description BANDWIDTH + + Packet bandwidth + + + + + + + +*/ + +#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0 +#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1 +#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003 + + +/* Description VHTA_RESERVED_0 + + Reserved. Set to 1 by MAC, PHY should ignore + +*/ + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004 + + +/* Description STBC + + Space time block coding: + Indicates STBC is disabled + Indicates STBC is enabled on + all streams + +*/ + +#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_STBC_LSB 3 +#define VHT_SIG_A_INFO_STBC_MSB 3 +#define VHT_SIG_A_INFO_STBC_MASK 0x00000008 + + +/* Description GROUP_ID + + In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed + to an AP or to a mesh STA, the Group ID field is set to + 0, otherwise it is set to 63. In an NDP PPDU the Group + ID is set according to IEEE 802.11ac_D1.0 Section 9.30.6 + (Transmission of a VHT NDP). For a MU-MIMO PPDU the Group + ID is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group + ID). +*/ + +#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_GROUP_ID_LSB 4 +#define VHT_SIG_A_INFO_GROUP_ID_MSB 9 +#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0 + + +/* Description N_STS + + For MU: + 3 bits/user with maximum of 4 users (user u uses + vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2, + 3) + Set to 0 for 0 space time streams + Set to 1 for 1 space time stream + Set to 2 for 2 space time streams + Set to 3 for 3 space time streams + Set to 4 for 4 space time streams (not supported in Wifi + 3.0) + Values 5-7 are reserved + In this field, references to user "u" should be interpreted + as MU user "u". As described in the previous chapter in + this document (see chapter on User number), the MU user + value for a given client is defined for each MU group that + the client participates in. The MU user number is not related + to the internal user number that is used within the BFer. + + + + For SU: + vht_sig_a[0][12:10] + Set to 0 for 1 space time stream + Set to 1 for 2 space time streams + Set to 2 for 3 space time streams + Set to 3 for 4 space time streams + Set to 4 for 5 space time streams + Set to 5 for 6 space time streams + Set to 6 for 7 space time streams + Set to 7 for 8 space time streams + + vht_sig_a[0][21:13] + Partial AID: + Set to the value of the TXVECTOR parameter PARTIAL_AID. + Partial AID provides an abbreviated indication of the intended + recipient(s) of the frame (see IEEE802.11ac_D1.0 Section + 9.17a (Partial AID in VHT PPDUs)). + +*/ + +#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_N_STS_LSB 10 +#define VHT_SIG_A_INFO_N_STS_MSB 21 +#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00 + + +/* Description TXOP_PS_NOT_ALLOWED + + E_num 0 txop_ps_allowed Not supported: If set to by + VHT AP if it allows non-AP VHT STAs in TXOP power save + mode to enter Doze state during a TXOP + Otherwise + +*/ + +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + + +/* Description VHTA_RESERVED_0B + + Reserved: Should be set to 1 by the MAC and ignored by the + PHY +*/ + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000 + + +/* Description RESERVED_0 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_RESERVED_0_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000 + + +/* Description GI_SETTING + + Indicates short guard interval is + not used in the data field + Indicates short guard interval is + used in the data field + Indicates short guard interval + is used in the data field and NSYM mod 10 = 9 + NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3 (TXTIME + and PSDU_LENGTH calculation). + +*/ + +#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_GI_SETTING_LSB 0 +#define VHT_SIG_A_INFO_GI_SETTING_MSB 1 +#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003 + + +/* Description SU_MU_CODING + + For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For an + MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then + B2 indicates the coding used for user 0; set to 0 for BCC + and 1 for LDPC. If the MU[0] NSTS field is 0, then this + field is reserved and set to 1 +*/ + +#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004 + + +/* Description LDPC_EXTRA_SYMBOL + + Set to 1 if the LDPC PPDU encoding process (if an SU PPDU), + or at least one LDPC user's PPDU encoding process (if an + MU PPDU), results in an extra OFDM symbol (or symbols) + as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 + (Encoding process for MU PPDUs). Set to 0 otherwise. +*/ + +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + + +/* Description MCS + + For SU: + Set to 0 for BPSK 1/2 + Set to 1 for QPSK 1/2 + Set to 2 for QPSK 3/4 + Set to 3 for 16-QAM 1/2 + Set to 4 for 16-QAM 3/4 + Set to 5 for 64-QAM 2/3 + Set to 6 for 64-QAM 3/4 + Set to 7 for 64-QAM 5/6 + Set to 8 for 256-QAM 3/4 + Set to 9 for 256-QAM 5/6 + For MU: + If NSTS for user 1 is non-zero, then vht_sig_a[1][4] indicates + coding for user 1: set to 0 for BCC, 1 for LDPC. + If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is + reserved and set to 1. + If NSTS for user 2 is non-zero, then vht_sig_a[1][5] indicates + coding for user 2: set to 0 for BCC, 1 for LDPC. + If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is + reserved and set to 1. + If NSTS for user 3 is non-zero, then vht_sig_a[1][6] indicates + coding for user 3: set to 0 for BCC, 1 for LDPC. + If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is + reserved and set to 1. + vht_sig_a[1][7] is reserved and set to 1 + +*/ + +#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_MCS_LSB 4 +#define VHT_SIG_A_INFO_MCS_MSB 7 +#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0 + + +/* Description BEAMFORMED + + For SU: + Set to 1 if a Beamforming steering matrix is applied to + the waveform in an SU transmission as described in IEEE802.11ac_D1.0 + Section 19.3.11.11.2 (Spatial mapping), set to 0 otherwise. + + For MU: + Reserved and set to 1 + +*/ + +#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100 + + +/* Description VHTA_RESERVED_1 + + Reserved and set to 1. +*/ + +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200 + + +/* Description CRC + + CRC calculated as in IEEE802.11ac_D1.0 Section 19.3.9.4.4 + (CRC calculation for HTSIG) with C7 in vht_sig_a[1][10], + etc. +*/ + +#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_CRC_LSB 10 +#define VHT_SIG_A_INFO_CRC_MSB 17 +#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + Set to 0. +*/ + +#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_TAIL_LSB 18 +#define VHT_SIG_A_INFO_TAIL_MSB 23 +#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000 + + +/* Description RESERVED_1 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RESERVED_1_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the VHT-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // VHT_SIG_A_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_mu160_info.h new file mode 100644 index 0000000000000000000000000000000000000000..e14b09ce2b971c577cfee3349722078ee6f16518 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_mu160_info.h @@ -0,0 +1,490 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_MU160_INFO_H_ +#define _VHT_SIG_B_MU160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 + + +struct vht_sig_b_mu160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, // [18:0] + mcs : 4, // [22:19] + tail : 6, // [28:23] + reserved_0 : 3; // [31:29] + uint32_t length_copy_a : 19, // [18:0] + mcs_copy_a : 4, // [22:19] + tail_copy_a : 6, // [28:23] + reserved_1 : 3; // [31:29] + uint32_t length_copy_b : 19, // [18:0] + mcs_copy_b : 4, // [22:19] + tail_copy_b : 6, // [28:23] + reserved_2 : 3; // [31:29] + uint32_t length_copy_c : 19, // [18:0] + mcs_copy_c : 4, // [22:19] + tail_copy_c : 6, // [28:23] + reserved_3 : 3; // [31:29] + uint32_t length_copy_d : 19, // [18:0] + mcs_copy_d : 4, // [22:19] + tail_copy_d : 6, // [28:23] + reserved_4 : 3; // [31:29] + uint32_t length_copy_e : 19, // [18:0] + mcs_copy_e : 4, // [22:19] + tail_copy_e : 6, // [28:23] + reserved_5 : 3; // [31:29] + uint32_t length_copy_f : 19, // [18:0] + mcs_copy_f : 4, // [22:19] + tail_copy_f : 6, // [28:23] + mu_user_number : 3; // [31:29] + uint32_t length_copy_g : 19, // [18:0] + mcs_copy_g : 4, // [22:19] + tail_copy_g : 6, // [28:23] + reserved_7 : 3; // [31:29] +#else + uint32_t reserved_0 : 3, // [31:29] + tail : 6, // [28:23] + mcs : 4, // [22:19] + length : 19; // [18:0] + uint32_t reserved_1 : 3, // [31:29] + tail_copy_a : 6, // [28:23] + mcs_copy_a : 4, // [22:19] + length_copy_a : 19; // [18:0] + uint32_t reserved_2 : 3, // [31:29] + tail_copy_b : 6, // [28:23] + mcs_copy_b : 4, // [22:19] + length_copy_b : 19; // [18:0] + uint32_t reserved_3 : 3, // [31:29] + tail_copy_c : 6, // [28:23] + mcs_copy_c : 4, // [22:19] + length_copy_c : 19; // [18:0] + uint32_t reserved_4 : 3, // [31:29] + tail_copy_d : 6, // [28:23] + mcs_copy_d : 4, // [22:19] + length_copy_d : 19; // [18:0] + uint32_t reserved_5 : 3, // [31:29] + tail_copy_e : 6, // [28:23] + mcs_copy_e : 4, // [22:19] + length_copy_e : 19; // [18:0] + uint32_t mu_user_number : 3, // [31:29] + tail_copy_f : 6, // [28:23] + mcs_copy_f : 4, // [22:19] + length_copy_f : 19; // [18:0] + uint32_t reserved_7 : 3, // [31:29] + tail_copy_g : 6, // [28:23] + mcs_copy_g : 4, // [22:19] + length_copy_g : 19; // [18:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 + + +/* Description LENGTH_COPY_A + + Same as "length". This field is not valid for RX packets + +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff + + +/* Description MCS_COPY_A + + Same as "mcs". This field is not valid for RX packets +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 + + +/* Description TAIL_COPY_A + + Same as "tail". This field is not valid for RX packets +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + + +/* Description RESERVED_1 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 + + +/* Description LENGTH_COPY_B + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff + + +/* Description MCS_COPY_B + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 + + +/* Description TAIL_COPY_B + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + + +/* Description RESERVED_2 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 + + +/* Description LENGTH_COPY_C + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff + + +/* Description MCS_COPY_C + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 + + +/* Description TAIL_COPY_C + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + + +/* Description RESERVED_3 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 + + +/* Description LENGTH_COPY_D + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff + + +/* Description MCS_COPY_D + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 + + +/* Description TAIL_COPY_D + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + + +/* Description RESERVED_4 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 + + +/* Description LENGTH_COPY_E + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff + + +/* Description MCS_COPY_E + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 + + +/* Description TAIL_COPY_E + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + + +/* Description RESERVED_5 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 + + +/* Description LENGTH_COPY_F + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff + + +/* Description MCS_COPY_F + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 + + +/* Description TAIL_COPY_F + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. +*/ + +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 + + +/* Description LENGTH_COPY_G + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff + + +/* Description MCS_COPY_G + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 + + +/* Description TAIL_COPY_G + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + + +/* Description RESERVED_7 + + +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 + + + +#endif // VHT_SIG_B_MU160_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_mu20_info.h new file mode 100644 index 0000000000000000000000000000000000000000..df3da93f18a28c3e4f38e442f2877d8e9ba2f726 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_mu20_info.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_MU20_INFO_H_ +#define _VHT_SIG_B_MU20_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 + + +struct vht_sig_b_mu20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 16, // [15:0] + mcs : 4, // [19:16] + tail : 6, // [25:20] + mu_user_number : 3, // [28:26] + reserved_0 : 3; // [31:29] +#else + uint32_t reserved_0 : 3, // [31:29] + mu_user_number : 3, // [28:26] + tail : 6, // [25:20] + mcs : 4, // [19:16] + length : 16; // [15:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 +#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 +#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 +#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + +*/ + +#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. + +*/ + +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 + + +/* Description RESERVED_0 + + +*/ + +#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 + + + +#endif // VHT_SIG_B_MU20_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_mu40_info.h new file mode 100644 index 0000000000000000000000000000000000000000..9af70697d0aadf7cdd5385023be7ab72acd39e5f --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_mu40_info.h @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_MU40_INFO_H_ +#define _VHT_SIG_B_MU40_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 + + +struct vht_sig_b_mu40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, // [16:0] + mcs : 4, // [20:17] + tail : 6, // [26:21] + reserved_0 : 2, // [28:27] + mu_user_number : 3; // [31:29] + uint32_t length_copy : 17, // [16:0] + mcs_copy : 4, // [20:17] + tail_copy : 6, // [26:21] + reserved_1 : 5; // [31:27] +#else + uint32_t mu_user_number : 3, // [31:29] + reserved_0 : 2, // [28:27] + tail : 6, // [26:21] + mcs : 4, // [20:17] + length : 17; // [16:0] + uint32_t reserved_1 : 5, // [31:27] + tail_copy : 6, // [26:21] + mcs_copy : 4, // [20:17] + length_copy : 17; // [16:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) +*/ + +#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. + +*/ + +#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. +*/ + +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 + + +/* Description LENGTH_COPY + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff + + +/* Description MCS_COPY + + Same as "mcs". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 + + +/* Description TAIL_COPY + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 + + +/* Description RESERVED_1 + + +*/ + +#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 + + + +#endif // VHT_SIG_B_MU40_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_mu80_info.h new file mode 100644 index 0000000000000000000000000000000000000000..850b66a04e571ef7d96dfec7ffd83d752371215a --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_mu80_info.h @@ -0,0 +1,262 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_MU80_INFO_H_ +#define _VHT_SIG_B_MU80_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 + + +struct vht_sig_b_mu80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, // [18:0] + mcs : 4, // [22:19] + tail : 6, // [28:23] + reserved_0 : 3; // [31:29] + uint32_t length_copy_a : 19, // [18:0] + mcs_copy_a : 4, // [22:19] + tail_copy_a : 6, // [28:23] + reserved_1 : 3; // [31:29] + uint32_t length_copy_b : 19, // [18:0] + mcs_copy_b : 4, // [22:19] + tail_copy_b : 6, // [28:23] + mu_user_number : 3; // [31:29] + uint32_t length_copy_c : 19, // [18:0] + mcs_copy_c : 4, // [22:19] + tail_copy_c : 6, // [28:23] + reserved_3 : 3; // [31:29] +#else + uint32_t reserved_0 : 3, // [31:29] + tail : 6, // [28:23] + mcs : 4, // [22:19] + length : 19; // [18:0] + uint32_t reserved_1 : 3, // [31:29] + tail_copy_a : 6, // [28:23] + mcs_copy_a : 4, // [22:19] + length_copy_a : 19; // [18:0] + uint32_t mu_user_number : 3, // [31:29] + tail_copy_b : 6, // [28:23] + mcs_copy_b : 4, // [22:19] + length_copy_b : 19; // [18:0] + uint32_t reserved_3 : 3, // [31:29] + tail_copy_c : 6, // [28:23] + mcs_copy_c : 4, // [22:19] + length_copy_c : 19; // [18:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + +*/ + +#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 + + +/* Description LENGTH_COPY_A + + Same as "length". This field is not valid for RX packets + +*/ + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff + + +/* Description MCS_COPY_A + + Same as "mcs". This field is not valid for RX packets +*/ + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 + + +/* Description TAIL_COPY_A + + Same as "tail". This field is not valid for RX packets +*/ + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + + +/* Description RESERVED_1 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 + + +/* Description LENGTH_COPY_B + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff + + +/* Description MCS_COPY_B + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 + + +/* Description TAIL_COPY_B + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. +*/ + +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 + + +/* Description LENGTH_COPY_C + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff + + +/* Description MCS_COPY_C + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 + + +/* Description TAIL_COPY_C + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + + +/* Description RESERVED_3 + + +*/ + +#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 + + + +#endif // VHT_SIG_B_MU80_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_su160_info.h new file mode 100644 index 0000000000000000000000000000000000000000..62e30032409ccd20a529a1fb5b52be2a391742d1 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_su160_info.h @@ -0,0 +1,575 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_SU160_INFO_H_ +#define _VHT_SIG_B_SU160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 + + +struct vht_sig_b_su160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, // [20:0] + vhtb_reserved : 2, // [22:21] + tail : 6, // [28:23] + reserved_0 : 2, // [30:29] + rx_ndp : 1; // [31:31] + uint32_t length_copy_a : 21, // [20:0] + vhtb_reserved_copy_a : 2, // [22:21] + tail_copy_a : 6, // [28:23] + reserved_1 : 2, // [30:29] + rx_ndp_copy_a : 1; // [31:31] + uint32_t length_copy_b : 21, // [20:0] + vhtb_reserved_copy_b : 2, // [22:21] + tail_copy_b : 6, // [28:23] + reserved_2 : 2, // [30:29] + rx_ndp_copy_b : 1; // [31:31] + uint32_t length_copy_c : 21, // [20:0] + vhtb_reserved_copy_c : 2, // [22:21] + tail_copy_c : 6, // [28:23] + reserved_3 : 2, // [30:29] + rx_ndp_copy_c : 1; // [31:31] + uint32_t length_copy_d : 21, // [20:0] + vhtb_reserved_copy_d : 2, // [22:21] + tail_copy_d : 6, // [28:23] + reserved_4 : 2, // [30:29] + rx_ndp_copy_d : 1; // [31:31] + uint32_t length_copy_e : 21, // [20:0] + vhtb_reserved_copy_e : 2, // [22:21] + tail_copy_e : 6, // [28:23] + reserved_5 : 2, // [30:29] + rx_ndp_copy_e : 1; // [31:31] + uint32_t length_copy_f : 21, // [20:0] + vhtb_reserved_copy_f : 2, // [22:21] + tail_copy_f : 6, // [28:23] + reserved_6 : 2, // [30:29] + rx_ndp_copy_f : 1; // [31:31] + uint32_t length_copy_g : 21, // [20:0] + vhtb_reserved_copy_g : 2, // [22:21] + tail_copy_g : 6, // [28:23] + reserved_7 : 2, // [30:29] + rx_ndp_copy_g : 1; // [31:31] +#else + uint32_t rx_ndp : 1, // [31:31] + reserved_0 : 2, // [30:29] + tail : 6, // [28:23] + vhtb_reserved : 2, // [22:21] + length : 21; // [20:0] + uint32_t rx_ndp_copy_a : 1, // [31:31] + reserved_1 : 2, // [30:29] + tail_copy_a : 6, // [28:23] + vhtb_reserved_copy_a : 2, // [22:21] + length_copy_a : 21; // [20:0] + uint32_t rx_ndp_copy_b : 1, // [31:31] + reserved_2 : 2, // [30:29] + tail_copy_b : 6, // [28:23] + vhtb_reserved_copy_b : 2, // [22:21] + length_copy_b : 21; // [20:0] + uint32_t rx_ndp_copy_c : 1, // [31:31] + reserved_3 : 2, // [30:29] + tail_copy_c : 6, // [28:23] + vhtb_reserved_copy_c : 2, // [22:21] + length_copy_c : 21; // [20:0] + uint32_t rx_ndp_copy_d : 1, // [31:31] + reserved_4 : 2, // [30:29] + tail_copy_d : 6, // [28:23] + vhtb_reserved_copy_d : 2, // [22:21] + length_copy_d : 21; // [20:0] + uint32_t rx_ndp_copy_e : 1, // [31:31] + reserved_5 : 2, // [30:29] + tail_copy_e : 6, // [28:23] + vhtb_reserved_copy_e : 2, // [22:21] + length_copy_e : 21; // [20:0] + uint32_t rx_ndp_copy_f : 1, // [31:31] + reserved_6 : 2, // [30:29] + tail_copy_f : 6, // [28:23] + vhtb_reserved_copy_f : 2, // [22:21] + length_copy_f : 21; // [20:0] + uint32_t rx_ndp_copy_g : 1, // [31:31] + reserved_7 : 2, // [30:29] + tail_copy_g : 6, // [28:23] + vhtb_reserved_copy_g : 2, // [22:21] + length_copy_g : 21; // [20:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones for non-NDP frames and ignored + on receive +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 + + +/* Description LENGTH_COPY_A + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_A + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + + +/* Description TAIL_COPY_A + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + + +/* Description RESERVED_1 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 + + +/* Description RX_NDP_COPY_A + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 + + +/* Description LENGTH_COPY_B + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_B + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + + +/* Description TAIL_COPY_B + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + + +/* Description RESERVED_2 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 + + +/* Description RX_NDP_COPY_B + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 + + +/* Description LENGTH_COPY_C + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_C + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + + +/* Description TAIL_COPY_C + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + + +/* Description RESERVED_3 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 + + +/* Description RX_NDP_COPY_C + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 + + +/* Description LENGTH_COPY_D + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_D + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 + + +/* Description TAIL_COPY_D + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + + +/* Description RESERVED_4 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 + + +/* Description RX_NDP_COPY_D + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 + + +/* Description LENGTH_COPY_E + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_E + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 + + +/* Description TAIL_COPY_E + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + + +/* Description RESERVED_5 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 + + +/* Description RX_NDP_COPY_E + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 + + +/* Description LENGTH_COPY_F + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_F + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 + + +/* Description TAIL_COPY_F + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + + +/* Description RESERVED_6 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 + + +/* Description RX_NDP_COPY_F + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 + + +/* Description LENGTH_COPY_G + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_G + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 + + +/* Description TAIL_COPY_G + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + + +/* Description RESERVED_7 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 + + +/* Description RX_NDP_COPY_G + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 + + + +#endif // VHT_SIG_B_SU160_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_su20_info.h new file mode 100644 index 0000000000000000000000000000000000000000..1a90cae3c2ba876a410de37cb8ec69c7d7db847f --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_su20_info.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_SU20_INFO_H_ +#define _VHT_SIG_B_SU20_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 + + +struct vht_sig_b_su20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, // [16:0] + vhtb_reserved : 3, // [19:17] + tail : 6, // [25:20] + reserved : 5, // [30:26] + rx_ndp : 1; // [31:31] +#else + uint32_t rx_ndp : 1, // [31:31] + reserved : 5, // [30:26] + tail : 6, // [25:20] + vhtb_reserved : 3, // [19:17] + length : 17; // [16:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones for non-NDP frames and ignored + on receive + +*/ + +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 + + +/* Description RESERVED + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 +#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 + + + +#endif // VHT_SIG_B_SU20_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_su40_info.h new file mode 100644 index 0000000000000000000000000000000000000000..32d5f3e755a06c1e67125c3b0f111136f0dbb8a8 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_su40_info.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_SU40_INFO_H_ +#define _VHT_SIG_B_SU40_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 + + +struct vht_sig_b_su40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, // [18:0] + vhtb_reserved : 2, // [20:19] + tail : 6, // [26:21] + reserved : 4, // [30:27] + rx_ndp : 1; // [31:31] + uint32_t length_copy : 19, // [18:0] + vhtb_reserved_copy : 2, // [20:19] + tail_copy : 6, // [26:21] + reserved_copy : 4, // [30:27] + rx_ndp_copy : 1; // [31:31] +#else + uint32_t rx_ndp : 1, // [31:31] + reserved : 4, // [30:27] + tail : 6, // [26:21] + vhtb_reserved : 2, // [20:19] + length : 19; // [18:0] + uint32_t rx_ndp_copy : 1, // [31:31] + reserved_copy : 4, // [30:27] + tail_copy : 6, // [26:21] + vhtb_reserved_copy : 2, // [20:19] + length_copy : 19; // [18:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones and ignored on receive +*/ + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 + + +/* Description RESERVED + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 + + +/* Description LENGTH_COPY + + Same as "length" +*/ + +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff + + +/* Description VHTB_RESERVED_COPY + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 + + +/* Description TAIL_COPY + + Same as "tail" +*/ + +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 + + +/* Description RESERVED_COPY + + Same as "reserved" +*/ + +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 + + +/* Description RX_NDP_COPY + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 + + + +#endif // VHT_SIG_B_SU40_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_su80_info.h new file mode 100644 index 0000000000000000000000000000000000000000..2f38636dc708597774b6c7bb0324beda361ac2ba --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/vht_sig_b_su80_info.h @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_SU80_INFO_H_ +#define _VHT_SIG_B_SU80_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 + + +struct vht_sig_b_su80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, // [20:0] + vhtb_reserved : 2, // [22:21] + tail : 6, // [28:23] + reserved_0 : 2, // [30:29] + rx_ndp : 1; // [31:31] + uint32_t length_copy_a : 21, // [20:0] + vhtb_reserved_copy_a : 2, // [22:21] + tail_copy_a : 6, // [28:23] + reserved_1 : 2, // [30:29] + rx_ndp_copy_a : 1; // [31:31] + uint32_t length_copy_b : 21, // [20:0] + vhtb_reserved_copy_b : 2, // [22:21] + tail_copy_b : 6, // [28:23] + reserved_2 : 2, // [30:29] + rx_ndp_copy_b : 1; // [31:31] + uint32_t length_copy_c : 21, // [20:0] + vhtb_reserved_copy_c : 2, // [22:21] + tail_copy_c : 6, // [28:23] + reserved_3 : 2, // [30:29] + rx_ndp_copy_c : 1; // [31:31] +#else + uint32_t rx_ndp : 1, // [31:31] + reserved_0 : 2, // [30:29] + tail : 6, // [28:23] + vhtb_reserved : 2, // [22:21] + length : 21; // [20:0] + uint32_t rx_ndp_copy_a : 1, // [31:31] + reserved_1 : 2, // [30:29] + tail_copy_a : 6, // [28:23] + vhtb_reserved_copy_a : 2, // [22:21] + length_copy_a : 21; // [20:0] + uint32_t rx_ndp_copy_b : 1, // [31:31] + reserved_2 : 2, // [30:29] + tail_copy_b : 6, // [28:23] + vhtb_reserved_copy_b : 2, // [22:21] + length_copy_b : 21; // [20:0] + uint32_t rx_ndp_copy_c : 1, // [31:31] + reserved_3 : 2, // [30:29] + tail_copy_c : 6, // [28:23] + vhtb_reserved_copy_c : 2, // [22:21] + length_copy_c : 21; // [20:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones for non-NDP frames and ignored + on receive +*/ + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 + + +/* Description LENGTH_COPY_A + + Same as "length" +*/ + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_A + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + + +/* Description TAIL_COPY_A + + Same as "tail" +*/ + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + + +/* Description RESERVED_1 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 + + +/* Description RX_NDP_COPY_A + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 + + +/* Description LENGTH_COPY_B + + Same as "length" +*/ + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_B + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + + +/* Description TAIL_COPY_B + + Same as "tail" +*/ + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + + +/* Description RESERVED_2 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 + + +/* Description RX_NDP_COPY_B + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 + + +/* Description LENGTH_COPY_C + + Same as "length" +*/ + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_C + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + + +/* Description TAIL_COPY_C + + Same as "tail" +*/ + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + + +/* Description RESERVED_3 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 + + +/* Description RX_NDP_COPY_C + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 + + + +#endif // VHT_SIG_B_SU80_INFO diff --git a/drivers/staging/fw-api/hw/qcn6432/wbm2sw_completion_ring_rx.h b/drivers/staging/fw-api/hw/qcn6432/wbm2sw_completion_ring_rx.h new file mode 100644 index 0000000000000000000000000000000000000000..a55eb0a92084eb7b90d316f580c9d29d49a26c68 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/wbm2sw_completion_ring_rx.h @@ -0,0 +1,967 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM2SW_COMPLETION_RING_RX_H_ +#define _WBM2SW_COMPLETION_RING_RX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 + + +struct wbm2sw_completion_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t release_source_module : 3, // [2:0] + bm_action : 3, // [5:3] + buffer_or_desc_type : 3, // [8:6] + return_buffer_manager : 4, // [12:9] + reserved_2a : 2, // [14:13] + cache_id : 1, // [15:15] + cookie_conversion_status : 1, // [16:16] + rxdma_push_reason : 2, // [18:17] + rxdma_error_code : 5, // [23:19] + reo_push_reason : 2, // [25:24] + reo_error_code : 5, // [30:26] + wbm_internal_error : 1; // [31:31] + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; // [31:0] + uint32_t buffer_phys_addr_39_32 : 8, // [7:0] + sw_buffer_cookie : 20, // [27:8] + looping_count : 4; // [31:28] +#else + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t wbm_internal_error : 1, // [31:31] + reo_error_code : 5, // [30:26] + reo_push_reason : 2, // [25:24] + rxdma_error_code : 5, // [23:19] + rxdma_push_reason : 2, // [18:17] + cookie_conversion_status : 1, // [16:16] + cache_id : 1, // [15:15] + reserved_2a : 2, // [14:13] + return_buffer_manager : 4, // [12:9] + buffer_or_desc_type : 3, // [8:6] + bm_action : 3, // [5:3] + release_source_module : 3; // [2:0] + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + sw_buffer_cookie : 20, // [27:8] + buffer_phys_addr_39_32 : 8; // [7:0] +#endif +}; + + +/* Description BUFFER_VIRT_ADDR_31_0 + + Lower 32 bits of the 64-bit virtual address corresponding + to the MSDU being released + +*/ + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_VIRT_ADDR_63_32 + + Upper 32 bits of the 64-bit virtual address corresponding + to the MSDU being released + +*/ + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + + +/* Description RELEASE_SOURCE_MODULE + + Indicates which module initiated the release of this buffer + or descriptor + + RXDMA released this buffer + or descriptor + REO released this buffer or + descriptor + FW released this buffer or + descriptor + SW released this buffer or + descriptor + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + +/* Description BM_ACTION + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when the field return_buffer_manager in + the Released_buff_or_desc_addr_info indicates: + WBM_IDLE_BUF_LIST or + WBM_IDLE_DESC_LIST + + An MSDU extension descriptor shall never be marked as WBM + being the 'owner', and thus WBM will forward it to FW/SW + + + Put the buffer or descriptor back + in the idle list. In case of MSDU or MDPU link descriptor, + BM does not need to check to release any individual MSDU + buffers + + This BM action can only be used + in combination with buffer_or_desc_type being msdu_link_descriptor. + Field first_msdu_index points out which MSDU pointer in + the MSDU link descriptor is the first of an MPDU that is + released. + BM shall release all the MSDU buffers linked to this first + MSDU buffer pointer. All related MSDU buffer pointer entries + shall be set to value 0, which represents the 'NULL" pointer. + When all MSDU buffer pointers in the MSDU link descriptor + are 'NULL', the MSDU link descriptor itself shall also + be released. + + CURRENTLY NOT IMPLEMENTED.... + + Put the buffer or descriptor back in the idle list. Only + valid in combination with buffer_or_desc_type indicating + MDPU_link_descriptor. + BM shall release the MPDU link descriptor as well as all + MSDUs that are linked to the MPDUs in this descriptor. + + + TODO: Any restrictions? + +*/ + +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 + + +/* Description BUFFER_OR_DESC_TYPE + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when WBM is marked as the return_buffer_manager + in the Released_Buffer_address_info + + Indicates that type of buffer or descriptor is being released + + + The address points to an MSDU buffer + + The address points to an TX + MSDU link descriptor + The address points to an MPDU + link descriptor + The address points to an MSDU + extension descriptor. + In case BM finds this one in a release ring, it passes it + on to FW... + The address points to an TQM + queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + TODO: Any restrictions? + +*/ + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + +/* Description RETURN_BUFFER_MANAGER + + 'Return_buffer_manager' field of the MSDU's buffer address + info, for debug +*/ + +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + + +/* Description RESERVED_2A + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 + + +/* Description CACHE_ID + + Indicates the WBM cache the MSDU was released from + +*/ + +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 + + +/* Description COOKIE_CONVERSION_STATUS + + 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' + + 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' + +*/ + +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + + +/* Description RXDMA_PUSH_REASON + + Field only valid when Release_source_module is set to release_source_RXDMA + + + Indicates why rxdma pushed the frame to this ring + + RXDMA detected an error an + pushed this frame to this queue + RXDMA pushed the frame + to this queue per received routing instructions. No error + within RXDMA was detected + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" + set, but instead WBM might just see a NULL pointer in the + MSDU link descriptor. This is to be considered a normal + condition for this scenario. + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + + +/* Description REO_PUSH_REASON + + Field only valid when Release_source_module is set to release_source_REO + + + Indicates why REO pushed the frame to this release ring + + Reo detected an error an pushed + this frame to this queue + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + + +/* Description REO_ERROR_CODE + + Field only valid when 'Reo_push_reason' set to 'reo_error_detected'. + + + Reo queue descriptor provided + in the REO_ENTRANCE ring is set to 0 + Reo queue descriptor valid + bit is NOT set + AMPDU frame received without BA + session having been setup. + Non-BA session, SN equal to SSN, + Retry bit set: duplicate frame + BA session, duplicate frame + A normal (management/data + frame) received with 2K jump in SN + A bar received with 2K jump in + SSN + A normal (management/data frame) + received with SN falling within the OOR window + A bar received with SSN falling within + the OOR window + A bar received without + a BA session + A bar received with SSN + equal to SN + PN Check Failed packet. + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set + in the REO Queue descriptor + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in + the REO Queue descriptor + Frame is forwarded + as a result of the queue descriptor(address) being blocked + as SW/FW seems to be currently in the process of making + updates to this descriptor... + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + + +/* Description WBM_INTERNAL_ERROR + + Can only be set by WBM. + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link related + activity + OR + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + + +/* Description RX_MPDU_DESC_INFO_DETAILS + + Consumer: REO/SW/FW + Producer: RXDMA + + General information related to the MPDU whose link descriptors + are being released from Rx DMA or REO +*/ + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: TQM/SW + Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) + + In case of RXDMA or REO releasing Rx MSDU link descriptors,' + WBM fills this field with Rx_msdu_desc_info_details when + releasing the MSDUs to SW. +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description BUFFER_PHYS_ADDR_31_0 + + LSB 32 bits of the physical address from the MSDU's buffer + address info, for debug +*/ + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_PHYS_ADDR_39_32 + + MSB 8 bits of the physical address from the MSDU's buffer + address info, for debug +*/ + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff + + +/* Description SW_BUFFER_COOKIE + + 'Sw_buffer_cookie' field of the MSDU's buffer address info + used to fill 'Buffer_virt_addr_*,' for debug + + For further debugging, if enabled, WBM may fill the Rx MPDU + sequence number in bits [27:16] (copying from field Reserved_7a + in 'WBM_RELEASE_RING_RX'). + +*/ + +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 + + +/* Description LOOPING_COUNT + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + If WBM_internal_error is set, this descriptor is sent to + the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count + is used to indicate an error code. + + The values reported are documented further in the WBM MLD + doc. + + If WBM_internal_error is not set, the following holds. + + A count value that indicates the number of times the producer + of entries into the Buffer Manager Ring has looped around + the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // WBM2SW_COMPLETION_RING_RX diff --git a/drivers/staging/fw-api/hw/qcn6432/wbm2sw_completion_ring_tx.h b/drivers/staging/fw-api/hw/qcn6432/wbm2sw_completion_ring_tx.h new file mode 100644 index 0000000000000000000000000000000000000000..17da3a266e610d1fe7838f7e3b8e5613a298cb01 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/wbm2sw_completion_ring_tx.h @@ -0,0 +1,833 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM2SW_COMPLETION_RING_TX_H_ +#define _WBM2SW_COMPLETION_RING_TX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "tx_rate_stats_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8 + + +struct wbm2sw_completion_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t release_source_module : 3, // [2:0] + cache_id : 1, // [3:3] + reserved_2a : 2, // [5:4] + buffer_or_desc_type : 3, // [8:6] + return_buffer_manager : 4, // [12:9] + tqm_release_reason : 4, // [16:13] + rbm_override_valid : 1, // [17:17] + sw_buffer_cookie_11_0 : 12, // [29:18] + cookie_conversion_status : 1, // [30:30] + wbm_internal_error : 1; // [31:31] + uint32_t tqm_status_number : 24, // [23:0] + transmit_count : 7, // [30:24] + sw_release_details_valid : 1; // [31:31] + uint32_t ack_frame_rssi : 8, // [7:0] + first_msdu : 1, // [8:8] + last_msdu : 1, // [9:9] + fw_tx_notify_frame : 3, // [12:10] + buffer_timestamp : 19; // [31:13] + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, // [15:0] + tid : 4, // [19:16] + sw_buffer_cookie_19_12 : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t wbm_internal_error : 1, // [31:31] + cookie_conversion_status : 1, // [30:30] + sw_buffer_cookie_11_0 : 12, // [29:18] + rbm_override_valid : 1, // [17:17] + tqm_release_reason : 4, // [16:13] + return_buffer_manager : 4, // [12:9] + buffer_or_desc_type : 3, // [8:6] + reserved_2a : 2, // [5:4] + cache_id : 1, // [3:3] + release_source_module : 3; // [2:0] + uint32_t sw_release_details_valid : 1, // [31:31] + transmit_count : 7, // [30:24] + tqm_status_number : 24; // [23:0] + uint32_t buffer_timestamp : 19, // [31:13] + fw_tx_notify_frame : 3, // [12:10] + last_msdu : 1, // [9:9] + first_msdu : 1, // [8:8] + ack_frame_rssi : 8; // [7:0] + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, // [31:28] + sw_buffer_cookie_19_12 : 8, // [27:20] + tid : 4, // [19:16] + sw_peer_id : 16; // [15:0] +#endif +}; + + +/* Description BUFFER_VIRT_ADDR_31_0 + + Lower 32 bits of the 64-bit virtual address corresponding + to the MSDU being released + +*/ + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_VIRT_ADDR_63_32 + + Upper 32 bits of the 64-bit virtual address corresponding + to the MSDU being released + +*/ + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + + +/* Description RELEASE_SOURCE_MODULE + + Indicates which module initiated the release of this buffer + or descriptor + + DO NOT USE + DO NOT USE + DO NOT USE + DO NOT USE + TQM released this buffer or + descriptor + FW released this buffer or + descriptor + SW released this buffer or + descriptor + +*/ + +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + +/* Description CACHE_ID + + To improve WBM performance, out-of-order completions may + be allowed to process multiple MPDUs in parallel. + + The MSDUs released from each cache would be in order so 'First_msdu' + and this field together can be used by SW to reorder the + completions back to the original order by keeping all MSDUs + of an MPDU from one cache together before switching to + the next MPDU (from either cache). + +*/ + +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008 + + +/* Description RESERVED_2A + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030 + + +/* Description BUFFER_OR_DESC_TYPE + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when WBM is marked as the return_buffer_manager + in the Released_Buffer_address_info + + Indicates that type of buffer or descriptor is being released + + + The address points to an MSDU buffer + + The address points to an TX + MSDU link descriptor + The address points to an MPDU + link descriptor + The address points to an MSDU + extension descriptor. + In case BM finds this one in a release ring, it passes it + on to FW... + The address points to an TQM + queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + +/* Description RETURN_BUFFER_MANAGER + + 'Return_buffer_manager' field of the MSDU's buffer address + info, for debug +*/ + +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + + +/* Description TQM_RELEASE_REASON + + Consumer: WBM/SW/FW + Producer: TQM + + Field only valid when Release_source_module is set to release_source_TQM + + + (rr = Release Reason) + frame is removed because an + ACK of BA for it was received + frame is removed because a remove + command of type "Remove_mpdus" initiated by SW + frame is removed because a remove + command of type "Remove_transmitted_mpdus" initiated by + SW + frame is removed because a + remove command of type "Remove_untransmitted_mpdus" initiated + by SW + frame is removed because a + remove command of type "Remove_aged_mpdus" or "Remove_aged_msdus" + initiated by SW + frame is removed because a remove + command where fw indicated that remove reason is fw_reason1 + + frame is removed because a remove + command where fw indicated that remove reason is fw_reason1 + + frame is removed because a remove + command where fw indicated that remove reason is fw_reason1 + + frame is removed because + a remove command of type "remove_mpdus_and_disable_queue" + or "remove_msdus_and_disable_flow" initiated by SW + frame is removed + because remove command of type "remove_till_nonmatching_mpdu" + initiated by SW + frame is dropped at TQM + entrance due to one of slow/medium/hard drop threshold criteria + + frame is dropped + at TQM entrance due to the WBM2TQM_LINK_RING having fewer + descriptors than a threshold programmed in TQM + frame is dropped at + TQM entrance due to 'TQM_Drop_frame' being set or "null" + MSDU flow pointer or MSDU flow pointer 'Flow_valid' being + zero or MSDU_length being zero + frame is dropped at TQM + entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' + set to TCL_multicast_drop_for_vdev. + frame is dropped at + TQM entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' + set to TCL_vdev_id_mismatch_drop. + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + + +/* Description RBM_OVERRIDE_VALID + + This is set to 0 for Tx cases not involving reinjection, + and set to 1 for TQM release cases requiring FW reinjection + + When set to 1, WBM releases the MSDU buffers to FW and overrides + the tx_rate_stats field with words 2 and 3 of the 'TX_MSDU_DETAILS' + structure, for FW reinjection of these MSDUs + + When releasing to host SW, this will be 0 if there is no + misprogramming. + +*/ + +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + + +/* Description SW_BUFFER_COOKIE_11_0 + + LSB 12 bits of the 'Sw_buffer_cookie' field of the MSDU's + buffer address info used to fill 'Buffer_virt_addr_*,' + for debug +*/ + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 + + +/* Description COOKIE_CONVERSION_STATUS + + 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' + + 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' + +*/ + +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + + +/* Description WBM_INTERNAL_ERROR + + Can only be set by WBM. + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link related + activity + OR + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + + +/* Description TQM_STATUS_NUMBER + + Field only valid when Release_source_module is set to release_source_TQM + + + The value in this field is equal to value of the 'TQM_CMD_Number' + field from the TQM command or the 'TQM_add_cmd_Number' field + from the TQM entrance ring descriptor LSB 24-bits. + + This field helps to correlate the statuses with the TQM + commands. + + NOTE that SW could program this number to be equal to the + PPDU_ID number in case direct correlation with the PPDU + ID is desired + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + + +/* Description TRANSMIT_COUNT + + Field only valid when Release_source_module is set to release_source_TQM + + + The number of times this frame has been transmitted +*/ + +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + + +/* Description SW_RELEASE_DETAILS_VALID + + Consumer: SW + Producer: WBM + + When set, some WBM specific release info for SW is valid. + + This is set when WMB got a 'release_msdu_list' command from + TQM and the return buffer manager is not WMB. WBM will + then de-aggregate all the MSDUs and pass them one at a time + on to the 'buffer owner' + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + + +/* Description ACK_FRAME_RSSI + + This field is only valid when the source is TQM. + + If this frame is removed as the result of the reception + of an ACK or BA, this field indicates the RSSI of the received + ACK or BA frame. + + When the frame is removed as result of a direct remove command + from the SW, this field is set to 0x0 (which is never + a valid value when real RSSI is available) + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + + +/* Description FIRST_MSDU + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + When set, this MSDU is the first MSDU pointed to in the 'release_msdu_list' + command. + +*/ + +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100 + + +/* Description LAST_MSDU + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + When set, this MSDU is the last MSDU pointed to in the 'release_msdu_list' + command. + +*/ + +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200 + + +/* Description FW_TX_NOTIFY_FRAME + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + This is the FW_tx_notify_frame field from the TX_MSDU_DETAILS + for this frame from the MSDU link descriptor + +*/ + +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + + +/* Description BUFFER_TIMESTAMP + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + This is the Buffer_timestamp field from the TX_MSDU_DETAILS + for this frame from the MSDU link descriptor. + + Timestamp in units determined by the UMCMN 'TX_TIMESTAMP_RESOLUTION_SELECT' + register + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + + +/* Description TX_RATE_STATS + + Consumer: TQM/SW + Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) + + Details for command execution tracking purposes. +*/ + + +/* Description TX_RATE_STATS_INFO_VALID + + When set all other fields in this STRUCT contain valid info. + + + When clear, none of the other fields contain valid info. + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + + +/* Description TRANSMIT_BW + + Field only valid when Tx_rate_stats_info_valid is set + + Indicates the BW of the upcoming transmission that shall + likely start in about 3 -4 us on the medium + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + + +/* Description TRANSMIT_PKT_TYPE + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + The packet type + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + + +/* Description TRANSMIT_STBC + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + When set, STBC transmission rate was used. +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + + +/* Description TRANSMIT_LDPC + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + When set, use LDPC transmission rates +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + + +/* Description TRANSMIT_SGI + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + Specify the right GI for HE-Ranging NDPs (11az)/Short NDP. + + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + + +/* Description TRANSMIT_MCS + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + For details, refer to MCS_TYPE description + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + + +/* Description OFDMA_TRANSMISSION + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + + Set when the transmission was an OFDMA transmission (DL + or UL). + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + + +/* Description TONES_IN_RU + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + The number of tones in the RU used. + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + + +/* Description TRANSMIT_NSS + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG + Not valid when in SW transmit mode + + The number of spatial streams used in the transmission + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 + + +/* Description PPDU_TRANSMISSION_TSF + + Field only valid when Tx_rate_stats_info_valid is set + + Based on a HWSCH configuration register setting, this field + either contains: + + Lower 32 bits of the TSF, snapshot of this value when transmission + of the PPDU containing the frame finished. + OR + Lower 32 bits of the TSF, snapshot of this value when transmission + of the PPDU containing the frame started + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + + +/* Description SW_PEER_ID + + Field only valid when Release_source_module is set to release_source_TQM + + + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason + can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this + e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). + + Sw_peer_id from the TX_MSDU_FLOW descriptor or TX_MPDU_QUEUE + descriptor + +*/ + +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff + + +/* Description TID + + Field only valid when Release_source_module is set to release_source_TQM + + + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason + can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this + e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). + + + This field represents the TID from the TX_MSDU_FLOW descriptor + or TX_MPDU_QUEUE descriptor + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_TID_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TID_MSB 19 +#define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000 + + +/* Description SW_BUFFER_COOKIE_19_12 + + MSB 8 bits of the 'Sw_buffer_cookie' field of the MSDU's + buffer address info used to fill 'Buffer_virt_addr_*,' + for debug. + WBM shall have configuration to copy 'TQM_Status_Number_31_24' + from the WBM input descriptor here instead. +*/ + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + If WBM_internal_error is set, this descriptor is sent to + the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count + is used to indicate an error code. + + The values reported are documented further in the WBM MLD + doc. + + If WBM_internal_error is not set, the following holds. + + A count value that indicates the number of times the producer + of entries into the Buffer Manager Ring has looped around + the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // WBM2SW_COMPLETION_RING_TX diff --git a/drivers/staging/fw-api/hw/qcn6432/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/qcn6432/wbm_buffer_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..41a166c1339f9c6ac566c0a0d596848d64bd6d9e --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/wbm_buffer_ring.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM_BUFFER_RING_H_ +#define _WBM_BUFFER_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 + + +struct wbm_buffer_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; +#else + struct buffer_addr_info buf_addr_info; +#endif +}; + + +/* Description BUF_ADDR_INFO + + Consumer: WBM + Producer: WBM + + Details of the physical address of the buffer + source buffer + owner + some SW meta data. + All modules getting this buffer address info, shall keep + all the 64 bits of info in this descriptor together and + eventually all 64 bits shall be given back to WMB when + the buffer is released. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif // WBM_BUFFER_RING diff --git a/drivers/staging/fw-api/hw/qcn6432/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/qcn6432/wbm_link_descriptor_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..bc624c0459c6b74c8087c36a64eeffead47efff7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/wbm_link_descriptor_ring.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ +#define _WBM_LINK_DESCRIPTOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 + + +struct wbm_link_descriptor_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info desc_addr_info; +#else + struct buffer_addr_info desc_addr_info; +#endif +}; + + +/* Description DESC_ADDR_INFO + + Consumer: WBM + Producer: WBM + + Details of the physical address of the buffer + source buffer + owner + some SW meta data + All modules getting this link descriptor address info, shall + keep all the 64 bits in this descriptor together and eventually + all 64 bits shall be given back to WBM when the link descriptor + is released. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif // WBM_LINK_DESCRIPTOR_RING diff --git a/drivers/staging/fw-api/hw/qcn6432/wbm_release_ring.h b/drivers/staging/fw-api/hw/qcn6432/wbm_release_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..6a1e08a80054c377877fa2a235325a0ece359c37 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/wbm_release_ring.h @@ -0,0 +1,411 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM_RELEASE_RING_H_ +#define _WBM_RELEASE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 + + +struct wbm_release_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, // [2:0] + reserved_2a : 3, // [5:3] + buffer_or_desc_type : 3, // [8:6] + reserved_2b : 22, // [30:9] + wbm_internal_error : 1; // [31:31] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, // [31:31] + reserved_2b : 22, // [30:9] + buffer_or_desc_type : 3, // [8:6] + reserved_2a : 3, // [5:3] + release_source_module : 3; // [2:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_7a : 28; // [27:0] +#endif +}; + + +/* Description RELEASED_BUFF_OR_DESC_ADDR_INFO + + DO NOT USE. This may be a 'BUFFER_ADDR_INFO' structure or + a 64-bit virtual address. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RELEASE_SOURCE_MODULE + + Indicates which module initiated the release of this buffer + or descriptor + + RXDMA released this buffer + or descriptor + REO released this buffer or + descriptor + FW released this buffer or + descriptor + SW released this buffer or + descriptor + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + +/* Description RESERVED_2A + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2A_LSB 3 +#define WBM_RELEASE_RING_RESERVED_2A_MSB 5 +#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 + + +/* Description BUFFER_OR_DESC_TYPE + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when WBM is marked as the return_buffer_manager + in the Released_Buffer_address_info + + Indicates that type of buffer or descriptor is being released + + + The address points to an MSDU buffer + + The address points to an TX + MSDU link descriptor + The address points to an MPDU + link descriptor + The address points to an MSDU + extension descriptor. + In case BM finds this one in a release ring, it passes it + on to FW... + The address points to an TQM + queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + TODO: Any restrictions? + +*/ + +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + +/* Description RESERVED_2B + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2B_LSB 9 +#define WBM_RELEASE_RING_RESERVED_2B_MSB 30 +#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 + + +/* Description WBM_INTERNAL_ERROR + + Can only be set by WBM. + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link related + activity + OR + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + +*/ + +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 + + +/* Description RESERVED_3A + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RESERVED_3A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_3A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff + + +/* Description RESERVED_4A + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RESERVED_4A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_4A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff + + +/* Description RESERVED_5A + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RESERVED_5A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_5A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff + + +/* Description RESERVED_6A + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff + + +/* Description RESERVED_7A + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_7A_MSB 27 +#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff + + +/* Description LOOPING_COUNT + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + If WBM_internal_error is set, this descriptor is sent to + the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count + is used to indicate an error code. + + The values reported are documented further in the WBM MLD + doc. + + If WBM_internal_error is not set, the following holds. + + A count value that indicates the number of times the producer + of entries into the Buffer Manager Ring has looped around + the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // WBM_RELEASE_RING diff --git a/drivers/staging/fw-api/hw/qcn6432/wbm_release_ring_rx.h b/drivers/staging/fw-api/hw/qcn6432/wbm_release_ring_rx.h new file mode 100644 index 0000000000000000000000000000000000000000..5c9fbc6a7490191463017b76b59f385457120ab2 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/wbm_release_ring_rx.h @@ -0,0 +1,1101 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM_RELEASE_RING_RX_H_ +#define _WBM_RELEASE_RING_RX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8 + + +struct wbm_release_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, // [2:0] + bm_action : 3, // [5:3] + buffer_or_desc_type : 3, // [8:6] + first_msdu_index : 4, // [12:9] + reserved_2a : 2, // [14:13] + cache_id : 1, // [15:15] + cookie_conversion_status : 1, // [16:16] + rxdma_push_reason : 2, // [18:17] + rxdma_error_code : 5, // [23:19] + reo_push_reason : 2, // [25:24] + reo_error_code : 5, // [30:26] + wbm_internal_error : 1; // [31:31] + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 20, // [19:0] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, // [31:31] + reo_error_code : 5, // [30:26] + reo_push_reason : 2, // [25:24] + rxdma_error_code : 5, // [23:19] + rxdma_push_reason : 2, // [18:17] + cookie_conversion_status : 1, // [16:16] + cache_id : 1, // [15:15] + reserved_2a : 2, // [14:13] + first_msdu_index : 4, // [12:9] + buffer_or_desc_type : 3, // [8:6] + bm_action : 3, // [5:3] + release_source_module : 3; // [2:0] + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reserved_7a : 20; // [19:0] +#endif +}; + + +/* Description RELEASED_BUFF_OR_DESC_ADDR_INFO + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Details of the physical address of the buffer or link descriptor + that is being released. Note that within this descriptor, + WBM will look at the 'owner' of the released buffer/descriptor + and forward it to SW/FW is WBM is not the owner. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RELEASE_SOURCE_MODULE + + Indicates which module initiated the release of this buffer + or descriptor + + RXDMA released this buffer + or descriptor + REO released this buffer or + descriptor + FW released this buffer or + descriptor + SW released this buffer or + descriptor + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + +/* Description BM_ACTION + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when the field return_buffer_manager in + the Released_buff_or_desc_addr_info indicates: + WBM_IDLE_BUF_LIST or + WBM_IDLE_DESC_LIST + + An MSDU extension descriptor shall never be marked as WBM + being the 'owner', and thus WBM will forward it to FW/SW + + + Put the buffer or descriptor back + in the idle list. In case of MSDU or MDPU link descriptor, + BM does not need to check to release any individual MSDU + buffers + + This BM action can only be used + in combination with buffer_or_desc_type being msdu_link_descriptor. + Field first_msdu_index points out which MSDU pointer in + the MSDU link descriptor is the first of an MPDU that is + released. + BM shall release all the MSDU buffers linked to this first + MSDU buffer pointer. All related MSDU buffer pointer entries + shall be set to value 0, which represents the 'NULL" pointer. + When all MSDU buffer pointers in the MSDU link descriptor + are 'NULL', the MSDU link descriptor itself shall also + be released. + + CURRENTLY NOT IMPLEMENTED.... + + Put the buffer or descriptor back in the idle list. Only + valid in combination with buffer_or_desc_type indicating + MDPU_link_descriptor. + BM shall release the MPDU link descriptor as well as all + MSDUs that are linked to the MPDUs in this descriptor. + + + TODO: Any restrictions? + +*/ + +#define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_RX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_RX_BM_ACTION_MASK 0x00000038 + + +/* Description BUFFER_OR_DESC_TYPE + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when WBM is marked as the return_buffer_manager + in the Released_Buffer_address_info + + Indicates that type of buffer or descriptor is being released + + + The address points to an MSDU buffer + + The address points to an TX + MSDU link descriptor + The address points to an MPDU + link descriptor + The address points to an MSDU + extension descriptor. + In case BM finds this one in a release ring, it passes it + on to FW... + The address points to an TQM + queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + TODO: Any restrictions? + +*/ + +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + +/* Description FIRST_MSDU_INDEX + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid for the bm_action release_msdu_list. + + The index of the first MSDU in an MSDU link descriptor all + belonging to the same MPDU. + + TODO: Any restrictions? + +*/ + +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK 0x00001e00 + + +/* Description RESERVED_2A + + +*/ + +#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 13 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 14 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x00006000 + + +/* Description CACHE_ID + + Indicates the WBM cache the MSDU was released from + +*/ + +#define WBM_RELEASE_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_CACHE_ID_LSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MASK 0x00008000 + + +/* Description COOKIE_CONVERSION_STATUS + + 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' + + 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' + +*/ + +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + + +/* Description RXDMA_PUSH_REASON + + Field only valid when Release_source_module is set to release_source_RXDMA + + + Indicates why rxdma pushed the frame to this ring + + RXDMA detected an error an + pushed this frame to this queue + RXDMA pushed the frame + to this queue per received routing instructions. No error + within RXDMA was detected + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" + set, but instead WBM might just see a NULL pointer in the + MSDU link descriptor. This is to be considered a normal + condition for this scenario. + + +*/ + +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + + + +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + + +/* Description REO_PUSH_REASON + + Field only valid when Release_source_module is set to release_source_REO + + + Indicates why REO pushed the frame to this release ring + + Reo detected an error an pushed + this frame to this queue + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + +*/ + +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + + +/* Description REO_ERROR_CODE + + Field only valid when 'Reo_push_reason' set to 'reo_error_detected'. + + + Reo queue descriptor provided + in the REO_ENTRANCE ring is set to 0 + Reo queue descriptor valid + bit is NOT set + AMPDU frame received without BA + session having been setup. + Non-BA session, SN equal to SSN, + Retry bit set: duplicate frame + BA session, duplicate frame + A normal (management/data + frame) received with 2K jump in SN + A bar received with 2K jump in + SSN + A normal (management/data frame) + received with SN falling within the OOR window + A bar received with SSN falling within + the OOR window + A bar received without + a BA session + A bar received with SSN + equal to SN + PN Check Failed packet. + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set + in the REO Queue descriptor + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in + the REO Queue descriptor + Frame is forwarded + as a result of the queue descriptor(address) being blocked + as SW/FW seems to be currently in the process of making + updates to this descriptor... + + +*/ + +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + + +/* Description WBM_INTERNAL_ERROR + + Can only be set by WBM. + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link related + activity + OR + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + +*/ + +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + + +/* Description RX_MPDU_DESC_INFO_DETAILS + + Consumer: REO/SW/FW + Producer: RXDMA + + General information related to the MPDU whose link descriptors + are being released from Rx DMA or REO + + When enabled in REO, REO will overwrite this structure to + have only the 'Msdu_count' field and 56 bits of the previous + PN from 'RX_REO_QUEUE' +*/ + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: TQM/SW + Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) + + In case of RXDMA or REO releasing Rx MSDU link descriptors,' + WBM fills this field with Rx_msdu_desc_info_details when + releasing the MSDUs to SW. +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RESERVED_6A + + +*/ + +#define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RX_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MASK 0xffffffff + + +/* Description RESERVED_7A + + For debugging, RXDMA and REO may fill the Rx MPDU sequence + number in bits [11:0] and WBM may copy over when it releases + Rx MSDUs. + + +*/ + +#define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MSB 19 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MASK 0x000fffff + + +/* Description RING_ID + + Consumer: TQM/REO/RXDMA/SW + Producer: SRNG (of RXDMA) + + For debugging. + This field is filled in by the SRNG module. + It help to identify the ring that is being looked +*/ + +#define WBM_RELEASE_RING_RX_RING_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RING_ID_LSB 20 +#define WBM_RELEASE_RING_RX_RING_ID_MSB 27 +#define WBM_RELEASE_RING_RX_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + If WBM_internal_error is set, this descriptor is sent to + the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count + is used to indicate an error code. + + The values reported are documented further in the WBM MLD + doc. + + If WBM_internal_error is not set, the following holds. + + A count value that indicates the number of times the producer + of entries into the Buffer Manager Ring has looped around + the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // WBM_RELEASE_RING_RX diff --git a/drivers/staging/fw-api/hw/qcn6432/wbm_release_ring_tx.h b/drivers/staging/fw-api/hw/qcn6432/wbm_release_ring_tx.h new file mode 100644 index 0000000000000000000000000000000000000000..493349ea00c746743bd530cb6400880443e6fe85 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/wbm_release_ring_tx.h @@ -0,0 +1,1044 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM_RELEASE_RING_TX_H_ +#define _WBM_RELEASE_RING_TX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "tx_rate_stats_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8 + + +struct wbm_release_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, // [2:0] + bm_action : 3, // [5:3] + buffer_or_desc_type : 3, // [8:6] + first_msdu_index : 4, // [12:9] + tqm_release_reason : 4, // [16:13] + rbm_override_valid : 1, // [17:17] + rbm_override : 4, // [21:18] + reserved_2a : 7, // [28:22] + cache_id : 1, // [29:29] + cookie_conversion_status : 1, // [30:30] + wbm_internal_error : 1; // [31:31] + uint32_t tqm_status_number : 24, // [23:0] + transmit_count : 7, // [30:24] + sw_release_details_valid : 1; // [31:31] + uint32_t ack_frame_rssi : 8, // [7:0] + first_msdu : 1, // [8:8] + last_msdu : 1, // [9:9] + fw_tx_notify_frame : 3, // [12:10] + buffer_timestamp : 19; // [31:13] + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, // [15:0] + tid : 4, // [19:16] + tqm_status_number_31_24 : 8, // [27:20] + looping_count : 4; // [31:28] +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, // [31:31] + cookie_conversion_status : 1, // [30:30] + cache_id : 1, // [29:29] + reserved_2a : 7, // [28:22] + rbm_override : 4, // [21:18] + rbm_override_valid : 1, // [17:17] + tqm_release_reason : 4, // [16:13] + first_msdu_index : 4, // [12:9] + buffer_or_desc_type : 3, // [8:6] + bm_action : 3, // [5:3] + release_source_module : 3; // [2:0] + uint32_t sw_release_details_valid : 1, // [31:31] + transmit_count : 7, // [30:24] + tqm_status_number : 24; // [23:0] + uint32_t buffer_timestamp : 19, // [31:13] + fw_tx_notify_frame : 3, // [12:10] + last_msdu : 1, // [9:9] + first_msdu : 1, // [8:8] + ack_frame_rssi : 8; // [7:0] + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, // [31:28] + tqm_status_number_31_24 : 8, // [27:20] + tid : 4, // [19:16] + sw_peer_id : 16; // [15:0] +#endif +}; + + +/* Description RELEASED_BUFF_OR_DESC_ADDR_INFO + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Details of the physical address of the buffer or link descriptor + that is being released. Note that within this descriptor, + WBM will look at the 'owner' of the released buffer/descriptor + and forward it to SW/FW is WBM is not the owner. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RELEASE_SOURCE_MODULE + + Indicates which module initiated the release of this buffer + or descriptor + + DO NOT USE + DO NOT USE + DO NOT USE + DO NOT USE + TQM released this buffer or + descriptor + FW released this buffer or + descriptor + SW released this buffer or + descriptor + +*/ + +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + +/* Description BM_ACTION + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when the field return_buffer_manager in + the Released_buff_or_desc_addr_info indicates: + WBM_IDLE_BUF_LIST or + WBM_IDLE_DESC_LIST + + An MSDU extension descriptor shall never be marked as WBM + being the 'owner', and thus WBM will forward it to FW/SW + + + Put the buffer or descriptor back + in the idle list. In case of MSDU or MDPU link descriptor, + BM does not need to check to release any individual MSDU + buffers + + This BM action can only be used + in combination with buffer_or_desc_type being msdu_link_descriptor. + Field first_msdu_index points out which MSDU pointer in + the MSDU link descriptor is the first of an MPDU that is + released. + BM shall release all the MSDU buffers linked to this first + MSDU buffer pointer. All related MSDU buffer pointer entries + shall be set to value 0, which represents the 'NULL" pointer. + When all MSDU buffer pointers in the MSDU link descriptor + are 'NULL', the MSDU link descriptor itself shall also + be released. + + CURRENTLY NOT IMPLEMENTED.... + + Put the buffer or descriptor back in the idle list. Only + valid in combination with buffer_or_desc_type indicating + MDPU_link_descriptor. + BM shall release the MPDU link descriptor as well as all + MSDUs that are linked to the MPDUs in this descriptor. + + + +*/ + +#define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_TX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_TX_BM_ACTION_MASK 0x00000038 + + +/* Description BUFFER_OR_DESC_TYPE + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when WBM is marked as the return_buffer_manager + in the Released_Buffer_address_info + + Indicates that type of buffer or descriptor is being released + + + The address points to an MSDU buffer + + The address points to an TX + MSDU link descriptor + The address points to an MPDU + link descriptor + The address points to an MSDU + extension descriptor. + In case BM finds this one in a release ring, it passes it + on to FW... + The address points to an TQM + queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + +*/ + +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + +/* Description FIRST_MSDU_INDEX + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid for the bm_action release_msdu_list. + + The index of the first MSDU in an MSDU link descriptor all + belonging to the same MPDU. + + +*/ + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK 0x00001e00 + + +/* Description TQM_RELEASE_REASON + + Consumer: WBM/SW/FW + Producer: TQM + + Field only valid when Release_source_module is set to release_source_TQM + + + (rr = Release Reason) + frame is removed because an + ACK of BA for it was received + frame is removed because a remove + command of type "Remove_mpdus" initiated by SW + frame is removed because a remove + command of type "Remove_transmitted_mpdus" initiated by + SW + frame is removed because a + remove command of type "Remove_untransmitted_mpdus" initiated + by SW + frame is removed because a + remove command of type "Remove_aged_mpdus" or "Remove_aged_msdus" + initiated by SW + frame is removed because a remove + command where fw indicated that remove reason is fw_reason1 + + frame is removed because a remove + command where fw indicated that remove reason is fw_reason1 + + frame is removed because a remove + command where fw indicated that remove reason is fw_reason1 + + frame is removed because + a remove command of type "remove_mpdus_and_disable_queue" + or "remove_msdus_and_disable_flow" initiated by SW + frame is removed + because remove command of type "remove_till_nonmatching_mpdu" + initiated by SW + frame is dropped at TQM + entrance due to one of slow/medium/hard drop threshold criteria + + frame is dropped + at TQM entrance due to the WBM2TQM_LINK_RING having fewer + descriptors than a threshold programmed in TQM + frame is dropped at + TQM entrance due to 'TQM_Drop_frame' being set or "null" + MSDU flow pointer or MSDU flow pointer 'Flow_valid' being + zero or MSDU length being zero + frame is dropped at TQM + entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' + set to TCL_multicast_drop_for_vdev. + frame is dropped at + TQM entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' + set to TCL_vdev_id_mismatch_drop. + + +*/ + +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + + +/* Description RBM_OVERRIDE_VALID + + This is set to 0 for Tx cases not involving reinjection, + and set to 1 for TQM release cases requiring FW reinjection + + When set to 1, WBM releases the MSDU buffers to FW and overrides + the tx_rate_stats field with words 2 and 3 of the 'TX_MSDU_DETAILS' + structure, for FW reinjection of these MSDUs + + +*/ + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + + +/* Description RBM_OVERRIDE + + Field only valid when rbm_override_valid = 1 + + WBM releases the MSDU buffers to FW and overrides the tx_rate_stats + field with words 2 and 3 of the 'TX_MSDU_DETAILS' structure, + for FW reinjection of these MSDUs. + +*/ + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB 18 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB 21 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK 0x003c0000 + + +/* Description RESERVED_2A + + +*/ + +#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 22 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 28 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0x1fc00000 + + +/* Description CACHE_ID + + To improve WBM performance, out-of-order completions may + be allowed to process multiple MPDUs in parallel. + + The MSDUs released from each cache would be in order so 'First_msdu' + and this field together can be used by SW to reorder the + completions back to the original order by keeping all MSDUs + of an MPDU from one cache together before switching to + the next MPDU (from either cache). + +*/ + +#define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_CACHE_ID_LSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MASK 0x20000000 + + +/* Description COOKIE_CONVERSION_STATUS + + 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' + + 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' + +*/ + +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + + +/* Description WBM_INTERNAL_ERROR + + Can only be set by WBM. + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link related + activity + OR + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + +*/ + +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + + +/* Description TQM_STATUS_NUMBER + + Field only valid when Release_source_module is set to release_source_TQM + + + The value in this field is equal to value of the 'TQM_CMD_Number' + field from the TQM command or the 'TQM_add_cmd_Number' field + from the TQM entrance ring descriptor LSB 24-bits. + + This field helps to correlate the statuses with the TQM + commands. + + NOTE that SW could program this number to be equal to the + PPDU_ID number in case direct correlation with the PPDU + ID is desired + + +*/ + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + + +/* Description TRANSMIT_COUNT + + Field only valid when Release_source_module is set to release_source_TQM + + + The number of times this frame has been transmitted +*/ + +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + + +/* Description SW_RELEASE_DETAILS_VALID + + Consumer: SW + Producer: WBM + + When set, some WBM specific release info for SW is valid. + + This is set when WMB got a 'release_msdu_list' command from + TQM and the return buffer manager is not WMB. WBM will + then de-aggregate all the MSDUs and pass them one at a time + on to the 'buffer owner' + + +*/ + +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + + +/* Description ACK_FRAME_RSSI + + This field is only valid when the source is TQM. + + If this frame is removed as the result of the reception + of an ACK or BA, this field indicates the RSSI of the received + ACK or BA frame. + + When the frame is removed as result of a direct remove command + from the SW, this field is set to 0x0 (which is never + a valid value when real RSSI is available) + + +*/ + +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + + +/* Description FIRST_MSDU + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + When set, this MSDU is the first MSDU pointed to in the 'release_msdu_list' + command. + + First_msdu ≠ last_msdu indicates the MSDU was part of + an A-MSDU. + +*/ + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK 0x00000100 + + +/* Description LAST_MSDU + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + When set, this MSDU is the last MSDU pointed to in the 'release_msdu_list' + command. + + First_msdu ≠ last_msdu indicates the MSDU was part of + an A-MSDU. + +*/ + +#define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_LAST_MSDU_LSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MASK 0x00000200 + + +/* Description FW_TX_NOTIFY_FRAME + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + This is the FW_tx_notify_frame field from the TX_MSDU_DETAILS + for this frame from the MSDU link descriptor + +*/ + +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + + +/* Description BUFFER_TIMESTAMP + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + This is the Buffer_timestamp field from the TX_MSDU_DETAILS + for this frame from the MSDU link descriptor. + + Timestamp in units determined by the UMCMN 'TX_TIMESTAMP_RESOLUTION_SELECT' + register + + +*/ + +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + + +/* Description TX_RATE_STATS + + Consumer: TQM/SW + Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) + + Details for command execution tracking purposes. +*/ + + +/* Description TX_RATE_STATS_INFO_VALID + + When set all other fields in this STRUCT contain valid info. + + + When clear, none of the other fields contain valid info. + + +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + + +/* Description TRANSMIT_BW + + Field only valid when Tx_rate_stats_info_valid is set + + Indicates the BW of the upcoming transmission that shall + likely start in about 3 -4 us on the medium + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + + +/* Description TRANSMIT_PKT_TYPE + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + The packet type + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + + +/* Description TRANSMIT_STBC + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + When set, STBC transmission rate was used. +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + + +/* Description TRANSMIT_LDPC + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + When set, use LDPC transmission rates +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + + +/* Description TRANSMIT_SGI + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + Specify the right GI for HE-Ranging NDPs (11az)/Short NDP. + + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + + +/* Description TRANSMIT_MCS + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + For details, refer to MCS_TYPE description + +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + + +/* Description OFDMA_TRANSMISSION + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + + Set when the transmission was an OFDMA transmission (DL + or UL). + +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + + +/* Description TONES_IN_RU + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + The number of tones in the RU used. + +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + + +/* Description TRANSMIT_NSS + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG + Not valid when in SW transmit mode + + The number of spatial streams used in the transmission + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 + + +/* Description PPDU_TRANSMISSION_TSF + + Field only valid when Tx_rate_stats_info_valid is set + + Based on a HWSCH configuration register setting, this field + either contains: + + Lower 32 bits of the TSF, snapshot of this value when transmission + of the PPDU containing the frame finished. + OR + Lower 32 bits of the TSF, snapshot of this value when transmission + of the PPDU containing the frame started + + +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + + +/* Description SW_PEER_ID + + Field only valid when Release_source_module is set to release_source_TQM + + + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason + can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this + e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). + + Sw_peer_id from the TX_MSDU_FLOW descriptor or TX_MPDU_QUEUE + descriptor + +*/ + +#define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB 0 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB 15 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK 0x0000ffff + + +/* Description TID + + Field only valid when Release_source_module is set to release_source_TQM + + + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason + can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this + e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). + + + This field represents the TID from the TX_MSDU_FLOW descriptor + or TX_MPDU_QUEUE descriptor + + +*/ + +#define WBM_RELEASE_RING_TX_TID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TID_LSB 16 +#define WBM_RELEASE_RING_TX_TID_MSB 19 +#define WBM_RELEASE_RING_TX_TID_MASK 0x000f0000 + + +/* Description TQM_STATUS_NUMBER_31_24 + + Field only valid when Release_source_module is set to release_source_TQM + + + The value in this field is equal to value of the 'TQM_CMD_Number' + field from the TQM command or the 'TQM_add_cmd_Number' field + from the TQM entrance ring descriptor MSB 8-bits. + + This field helps to correlate the statuses with the TQM + commands. + + +*/ + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB 20 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB 27 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + If WBM_internal_error is set, this descriptor is sent to + the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count + is used to indicate an error code. + + The values reported are documented further in the WBM MLD + doc. + + If WBM_internal_error is not set, the following holds. + + A count value that indicates the number of times the producer + of entries into the Buffer Manager Ring has looped around + the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // WBM_RELEASE_RING_TX diff --git a/drivers/staging/fw-api/hw/qcn6432/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/qcn6432/wcss_seq_hwiobase.h new file mode 100644 index 0000000000000000000000000000000000000000..aa57da708877de968e9d6cbc7b9ceabfa54b1d8c --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/wcss_seq_hwiobase.h @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __WCSS_SEQ_HWIOBASE_H__ +#define __WCSS_SEQ_HWIOBASE_H__ +/*---------------------------------------------------------------------------- + * BASE: WCSS_CFGBUS + *--------------------------------------------------------------------------*/ + +#define WCSS_CFGBUS_BASE 0x00008000 +#define WCSS_CFGBUS_BASE_SIZE 0x00004000 +#define WCSS_CFGBUS_BASE_PHYS 0x00008000 + +/*---------------------------------------------------------------------------- + * BASE: UMAC_NOC + *--------------------------------------------------------------------------*/ + +#define UMAC_NOC_BASE 0x00140000 +#define UMAC_NOC_BASE_SIZE 0x00004200 +#define UMAC_NOC_BASE_PHYS 0x00140000 + +/*---------------------------------------------------------------------------- + * BASE: PHYA0 + *--------------------------------------------------------------------------*/ + +#define PHYA0_BASE 0x00300000 +#define PHYA0_BASE_SIZE 0x00300000 +#define PHYA0_BASE_PHYS 0x00300000 + +/*---------------------------------------------------------------------------- + * BASE: DMAC + *--------------------------------------------------------------------------*/ + +#define DMAC_BASE 0x00900000 +#define DMAC_BASE_SIZE 0x00080000 +#define DMAC_BASE_PHYS 0x00900000 + +/*---------------------------------------------------------------------------- + * BASE: UMAC + *--------------------------------------------------------------------------*/ + +#define UMAC_BASE 0x00a00000 +#define UMAC_BASE_SIZE 0x0004d000 +#define UMAC_BASE_PHYS 0x00a00000 + +/*---------------------------------------------------------------------------- + * BASE: PMAC0 + *--------------------------------------------------------------------------*/ + +#define PMAC0_BASE 0x00a80000 +#define PMAC0_BASE_SIZE 0x00040000 +#define PMAC0_BASE_PHYS 0x00a80000 + +/*---------------------------------------------------------------------------- + * BASE: MAC_WSIB + *--------------------------------------------------------------------------*/ + +#define MAC_WSIB_BASE 0x00b3c000 +#define MAC_WSIB_BASE_SIZE 0x00004000 +#define MAC_WSIB_BASE_PHYS 0x00b3c000 + +/*---------------------------------------------------------------------------- + * BASE: CXC + *--------------------------------------------------------------------------*/ + +#define CXC_BASE 0x00b40000 +#define CXC_BASE_SIZE 0x00010000 +#define CXC_BASE_PHYS 0x00b40000 + +/*---------------------------------------------------------------------------- + * BASE: WFSS_PMM + *--------------------------------------------------------------------------*/ + +#define WFSS_PMM_BASE 0x00b50000 +#define WFSS_PMM_BASE_SIZE 0x00002401 +#define WFSS_PMM_BASE_PHYS 0x00b50000 + +/*---------------------------------------------------------------------------- + * BASE: WFSS_CC + *--------------------------------------------------------------------------*/ + +#define WFSS_CC_BASE 0x00b60000 +#define WFSS_CC_BASE_SIZE 0x00008000 +#define WFSS_CC_BASE_PHYS 0x00b60000 + +/*---------------------------------------------------------------------------- + * BASE: WCMN_CORE + *--------------------------------------------------------------------------*/ + +#define WCMN_CORE_BASE 0x00b68000 +#define WCMN_CORE_BASE_SIZE 0x000008a9 +#define WCMN_CORE_BASE_PHYS 0x00b68000 + +/*---------------------------------------------------------------------------- + * BASE: WIFI_CFGBUS_APB_TSLV + *--------------------------------------------------------------------------*/ + +#define WIFI_CFGBUS_APB_TSLV_BASE 0x00b6b000 +#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000 + +/*---------------------------------------------------------------------------- + * BASE: WFSS_CFGBUS + *--------------------------------------------------------------------------*/ + +#define WFSS_CFGBUS_BASE 0x00b6c000 +#define WFSS_CFGBUS_BASE_SIZE 0x000000a0 +#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000 + +/*---------------------------------------------------------------------------- + * BASE: WIFI_CFGBUS_AHB_TSLV + *--------------------------------------------------------------------------*/ + +#define WIFI_CFGBUS_AHB_TSLV_BASE 0x00b6d000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000 + +/*---------------------------------------------------------------------------- + * BASE: UMAC_ACMT + *--------------------------------------------------------------------------*/ + +#define UMAC_ACMT_BASE 0x00b6e000 +#define UMAC_ACMT_BASE_SIZE 0x00001000 +#define UMAC_ACMT_BASE_PHYS 0x00b6e000 + +/*---------------------------------------------------------------------------- + * BASE: WCSS_CC + *--------------------------------------------------------------------------*/ + +#define WCSS_CC_BASE 0x00b80000 +#define WCSS_CC_BASE_SIZE 0x00010000 +#define WCSS_CC_BASE_PHYS 0x00b80000 + +/*---------------------------------------------------------------------------- + * BASE: PMM_TOP + *--------------------------------------------------------------------------*/ + +#define PMM_TOP_BASE 0x00b90000 +#define PMM_TOP_BASE_SIZE 0x00010000 +#define PMM_TOP_BASE_PHYS 0x00b90000 + +/*---------------------------------------------------------------------------- + * BASE: WCSS_TOP_CMN + *--------------------------------------------------------------------------*/ + +#define WCSS_TOP_CMN_BASE 0x00ba0000 +#define WCSS_TOP_CMN_BASE_SIZE 0x00004000 +#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000 + +/*---------------------------------------------------------------------------- + * BASE: WCSS_IE + *--------------------------------------------------------------------------*/ + +#define WCSS_IE_BASE 0x00ba4000 +#define WCSS_IE_BASE_SIZE 0x00001000 +#define WCSS_IE_BASE_PHYS 0x00ba4000 + +/*---------------------------------------------------------------------------- + * BASE: MSIP + *--------------------------------------------------------------------------*/ + +#define MSIP_BASE 0x00bb0000 +#define MSIP_BASE_SIZE 0x00010000 +#define MSIP_BASE_PHYS 0x00bb0000 + +/*---------------------------------------------------------------------------- + * BASE: DBG + *--------------------------------------------------------------------------*/ + +#define DBG_BASE 0x01000000 +#define DBG_BASE_SIZE 0x00100000 +#define DBG_BASE_PHYS 0x01000000 + + +#endif /* __WCSS_SEQ_HWIOBASE_H__ */ diff --git a/drivers/staging/fw-api/hw/qcn6432/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/qcn6432/wcss_seq_hwioreg_umac.h new file mode 100644 index 0000000000000000000000000000000000000000..d778ba3194704a0039682d435c9945f4bc6c3aa7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/wcss_seq_hwioreg_umac.h @@ -0,0 +1,50347 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __WCSS_SEQ_HWIOREG_UMAC_H__ +#define __WCSS_SEQ_HWIOREG_UMAC_H__ + +#include "seq_hwio.h" +#include "wcss_seq_hwiobase.h" +#ifdef SCALE_INCLUDES +#include "HALhwio.h" +#else +#include "msmhwio.h" +#endif + +/*---------------------------------------------------------------------------- + * MODULE: MAC_UMXI_REG + *--------------------------------------------------------------------------*/ + +#define MAC_UMXI_REG_REG_BASE (UMAC_BASE + 0x00030000) +#define MAC_UMXI_REG_REG_BASE_SIZE 0x4000 +#define MAC_UMXI_REG_REG_BASE_USED 0x610 +#define MAC_UMXI_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00030000) +#define MAC_UMXI_REG_REG_BASE_OFFS 0x00030000 + +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_ADDR(x) ((x) + 0x0) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_PHYS(x) ((x) + 0x0) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_OFFS (0x0) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RMSK 0x8000007f +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_ADDR(x)) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_ADDR(x),m,v,HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_IN(x)) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 31 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_WR_PERF_CNT_1_BMSK 0x40 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_WR_PERF_CNT_1_SHFT 6 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_WR_PERF_CNT_0_BMSK 0x20 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_WR_PERF_CNT_0_SHFT 5 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_3_BMSK 0x10 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_3_SHFT 4 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_2_BMSK 0x8 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_2_SHFT 3 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_1_BMSK 0x4 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_1_SHFT 2 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_0_BMSK 0x2 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_0_SHFT 1 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_UNUSED_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_UNUSED_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_ADDR(x) ((x) + 0x4) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_PHYS(x) ((x) + 0x4) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_OFFS (0x4) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_ADDR(x) ((x) + 0x8) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_PHYS(x) ((x) + 0x8) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_OFFS (0x8) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_RMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_VALUE_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_ADDR(x) ((x) + 0xc) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_PHYS(x) ((x) + 0xc) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_OFFS (0xc) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_RMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_VALUE_BMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_ADDR(x) ((x) + 0x10) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_PHYS(x) ((x) + 0x10) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_OFFS (0x10) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_ADDR(x) ((x) + 0x14) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_PHYS(x) ((x) + 0x14) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_OFFS (0x14) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_RMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_VALUE_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_ADDR(x) ((x) + 0x18) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_PHYS(x) ((x) + 0x18) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_OFFS (0x18) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_RMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_VALUE_BMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDR(x) ((x) + 0x1c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_PHYS(x) ((x) + 0x1c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_OFFS (0x1c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ATTR 0x0 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDRESS_RANGE_LIMIT_SHFT 30 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_WINDOW_SIZE_BMSK 0x38000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_WINDOW_SIZE_SHFT 27 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_RESET_CNT_BMSK 0x4000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_RESET_CNT_SHFT 26 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_CNTR_EN_BMSK 0x2000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_CNTR_EN_SHFT 25 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ID_BITMAP_BMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x) ((x) + 0x20) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_PHYS(x) ((x) + 0x20) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_OFFS (0x20) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x) ((x) + 0x24) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_PHYS(x) ((x) + 0x24) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_OFFS (0x24) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_ADDR(x) ((x) + 0x28) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_PHYS(x) ((x) + 0x28) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_OFFS (0x28) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_ADDR(x) ((x) + 0x2c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_PHYS(x) ((x) + 0x2c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_OFFS (0x2c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDR(x) ((x) + 0x30) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_PHYS(x) ((x) + 0x30) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_OFFS (0x30) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ATTR 0x0 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDRESS_RANGE_LIMIT_SHFT 30 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_WINDOW_SIZE_BMSK 0x38000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_WINDOW_SIZE_SHFT 27 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_RESET_CNT_BMSK 0x4000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_RESET_CNT_SHFT 26 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_CNTR_EN_BMSK 0x2000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_CNTR_EN_SHFT 25 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ID_BITMAP_BMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x) ((x) + 0x34) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_PHYS(x) ((x) + 0x34) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_OFFS (0x34) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x) ((x) + 0x38) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_PHYS(x) ((x) + 0x38) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_OFFS (0x38) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_ADDR(x) ((x) + 0x3c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_PHYS(x) ((x) + 0x3c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_OFFS (0x3c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_ADDR(x) ((x) + 0x40) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_PHYS(x) ((x) + 0x40) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_OFFS (0x40) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDR(x) ((x) + 0x44) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_PHYS(x) ((x) + 0x44) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_OFFS (0x44) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ATTR 0x0 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDRESS_RANGE_LIMIT_SHFT 30 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_WINDOW_SIZE_BMSK 0x38000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_WINDOW_SIZE_SHFT 27 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_RESET_CNT_BMSK 0x4000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_RESET_CNT_SHFT 26 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_CNTR_EN_BMSK 0x2000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_CNTR_EN_SHFT 25 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ID_BITMAP_BMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ADDR(x) ((x) + 0x48) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_PHYS(x) ((x) + 0x48) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_OFFS (0x48) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ADDR(x) ((x) + 0x4c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_PHYS(x) ((x) + 0x4c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_OFFS (0x4c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_ADDR(x) ((x) + 0x50) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_PHYS(x) ((x) + 0x50) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_OFFS (0x50) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_ADDR(x) ((x) + 0x54) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_PHYS(x) ((x) + 0x54) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_OFFS (0x54) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDR(x) ((x) + 0x58) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_PHYS(x) ((x) + 0x58) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_OFFS (0x58) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ATTR 0x0 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDRESS_RANGE_LIMIT_SHFT 30 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_WINDOW_SIZE_BMSK 0x38000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_WINDOW_SIZE_SHFT 27 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_RESET_CNT_BMSK 0x4000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_RESET_CNT_SHFT 26 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_CNTR_EN_BMSK 0x2000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_CNTR_EN_SHFT 25 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ID_BITMAP_BMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ADDR(x) ((x) + 0x5c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_PHYS(x) ((x) + 0x5c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_OFFS (0x5c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ADDR(x) ((x) + 0x60) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_PHYS(x) ((x) + 0x60) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_OFFS (0x60) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_ADDR(x) ((x) + 0x64) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_PHYS(x) ((x) + 0x64) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_OFFS (0x64) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_ADDR(x) ((x) + 0x68) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_PHYS(x) ((x) + 0x68) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_OFFS (0x68) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_ADDR(x) ((x) + 0x6c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_PHYS(x) ((x) + 0x6c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_OFFS (0x6c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_RMSK 0x70101 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_ATTR 0x0 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_WINDOW_SIZE_BMSK 0x70000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_WINDOW_SIZE_SHFT 16 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_RESET_CNT_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_RESET_CNT_SHFT 8 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_CNTR_EN_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_CNTR_EN_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ADDR(x) ((x) + 0x70) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_PHYS(x) ((x) + 0x70) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_OFFS (0x70) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_RMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ID_BITMAP_BMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x) ((x) + 0x74) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_PHYS(x) ((x) + 0x74) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_OFFS (0x74) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x) ((x) + 0x78) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_PHYS(x) ((x) + 0x78) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_OFFS (0x78) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_ADDR(x) ((x) + 0x7c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_PHYS(x) ((x) + 0x7c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_OFFS (0x7c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_ADDR(x) ((x) + 0x80) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_PHYS(x) ((x) + 0x80) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_OFFS (0x80) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_ADDR(x) ((x) + 0x84) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_PHYS(x) ((x) + 0x84) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_OFFS (0x84) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_RMSK 0x70101 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_ATTR 0x0 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_WINDOW_SIZE_BMSK 0x70000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_WINDOW_SIZE_SHFT 16 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_RESET_CNT_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_RESET_CNT_SHFT 8 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_CNTR_EN_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_CNTR_EN_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x) ((x) + 0x88) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_PHYS(x) ((x) + 0x88) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_OFFS (0x88) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x) ((x) + 0x8c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_PHYS(x) ((x) + 0x8c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_OFFS (0x8c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ADDR(x) ((x) + 0x90) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_PHYS(x) ((x) + 0x90) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_OFFS (0x90) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_RMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ID_BITMAP_BMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_ADDR(x) ((x) + 0x94) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_PHYS(x) ((x) + 0x94) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_OFFS (0x94) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_ADDR(x) ((x) + 0x98) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_PHYS(x) ((x) + 0x98) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_OFFS (0x98) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_ADDR(x) ((x) + 0x9c) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_PHYS(x) ((x) + 0x9c) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_OFFS (0x9c) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_WR_REMAP_EN_BMSK 0x80000000 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_WR_REMAP_EN_SHFT 31 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_RD_REMAP_EN_BMSK 0x40000000 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_RD_REMAP_EN_SHFT 30 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_REMAP_SEC_BMSK 0x20000000 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_REMAP_SEC_SHFT 29 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_REMAP_ADDR_BMSK 0x1fffffff +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_REMAP_ADDR_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x) ((x) + 0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x) ((x) + 0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS (0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK 0x7 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK 0x7 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x) ((x) + 0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x) ((x) + 0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS (0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR 0x00001ffe +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK 0x1ffe000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT 13 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK 0x1ffe +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT 1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x) ((x) + 0xa8) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_PHYS(x) ((x) + 0xa8) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_OFFS (0xa8) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_VAL_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_VAL_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x) ((x) + 0xac) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_PHYS(x) ((x) + 0xac) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_OFFS (0xac) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x) ((x) + 0xb0) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_PHYS(x) ((x) + 0xb0) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_OFFS (0xb0) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_RMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x) ((x) + 0xb4) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_PHYS(x) ((x) + 0xb4) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_OFFS (0xb4) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_BASE_ADDR_MASK_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_BASE_ADDR_MASK_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x) ((x) + 0xb8) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_PHYS(x) ((x) + 0xb8) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_OFFS (0xb8) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_RMSK 0xc00000ff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_POR 0x00000010 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_SS_UP_CHK_ENABLE_BMSK 0x80000000 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_SS_UP_CHK_ENABLE_SHFT 31 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_PCIE_STATE_CHK_ENABLE_BMSK 0x40000000 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_PCIE_STATE_CHK_ENABLE_SHFT 30 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_BASE_ADDR_MASK_MSB_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_BASE_ADDR_MASK_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_ADDR(x) ((x) + 0xbc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_PHYS(x) ((x) + 0xbc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_OFFS (0xbc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_ADDR(x) ((x) + 0xc0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_PHYS(x) ((x) + 0xc0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_OFFS (0xc0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_RMSK 0xff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_VALUE_BMSK 0xff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_ADDR(x) ((x) + 0xc4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_PHYS(x) ((x) + 0xc4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_OFFS (0xc4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_RMSK 0xfff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_POR 0x00000211 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0xe00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 9 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x1f0 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 4 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0xf +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x) ((x) + 0xc8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_PHYS(x) ((x) + 0xc8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_OFFS (0xc8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x) ((x) + 0xcc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_PHYS(x) ((x) + 0xcc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_OFFS (0xcc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RMSK 0x80003fff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 31 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x2000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 13 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_BST_FIFO_AXI_MAS_BMSK 0x1000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_BST_FIFO_AXI_MAS_SHFT 12 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_BST_FIFO_AXI_MAS_BMSK 0x800 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_BST_FIFO_AXI_MAS_SHFT 11 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x400 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 10 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x200 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 9 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x80 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 7 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x40 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 6 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x20 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 5 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x10 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 4 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x4 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 2 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x2 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ADDR(x) ((x) + 0xd0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_PHYS(x) ((x) + 0xd0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_OFFS (0xd0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_RMSK 0x81011f01 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x80000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 31 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x1000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 24 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x10000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK 0x1000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT 12 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK 0x800 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT 11 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK 0x400 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT 10 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK 0x200 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT 9 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_HW_ERR_INT_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_HW_ERR_INT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_WARN_INT_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_WARN_INT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_ADDR(x) ((x) + 0xd4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_PHYS(x) ((x) + 0xd4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_OFFS (0xd4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_RMSK 0xffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0xff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0xff00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0xff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x) ((x) + 0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x) ((x) + 0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS (0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK 0xff000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT 24 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK 0xff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK 0xff00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK 0xff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_ADDR(x) ((x) + 0xdc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_PHYS(x) ((x) + 0xdc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_OFFS (0xdc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_RMSK 0x1010101 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_WR_ACC_ERR_BMSK 0x1000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_WR_ACC_ERR_SHFT 24 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_RD_ACC_ERR_BMSK 0x10000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_RD_ACC_ERR_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_WR_TIMEOUT_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_WR_TIMEOUT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_RD_TIMEOUT_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_RD_TIMEOUT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_ADDR(x) ((x) + 0xe0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_PHYS(x) ((x) + 0xe0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_OFFS (0xe0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_RMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_AXI_WR_PCIE_L0_ACC_ERR_PORT_BMSK 0xff00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_AXI_WR_PCIE_L0_ACC_ERR_PORT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_AXI_RD_PCIE_L0_ACC_ERR_PORT_BMSK 0xff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_AXI_RD_PCIE_L0_ACC_ERR_PORT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x) ((x) + 0xe4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_PHYS(x) ((x) + 0xe4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_OFFS (0xe4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 24 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0xff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x3f00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x3f +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x) ((x) + 0xe8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_PHYS(x) ((x) + 0xe8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_OFFS (0xe8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 24 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0xff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x3f00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x3f +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x) ((x) + 0xec) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_PHYS(x) ((x) + 0xec) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_OFFS (0xec) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_RMSK 0xefffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_POR 0x46000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_READ_BURST_SIZE_INT_BMSK 0xe0000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_READ_BURST_SIZE_INT_SHFT 29 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_READ_BURST_SIZE_EXT_BMSK 0xe000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_READ_BURST_SIZE_EXT_SHFT 25 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_READ_ISSUE_THRESHOLD_BMSK 0x1ffe000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_READ_ISSUE_THRESHOLD_SHFT 13 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x1ffe +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_CLEAR_STATS_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_CLEAR_STATS_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x) ((x) + 0xf0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_PHYS(x) ((x) + 0xf0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_OFFS (0xf0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_RMSK 0xc00007ff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_POR 0x00000013 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_BURST_SIZE_SEL_ENABLE_BMSK 0x80000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_BURST_SIZE_SEL_ENABLE_SHFT 31 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_BURST_SPLIT_DISABLE_BMSK 0x40000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_BURST_SPLIT_DISABLE_SHFT 30 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_DELAYED_RD_FLUSH_BMSK 0x400 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_DELAYED_RD_FLUSH_SHFT 10 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_DELAYED_WR_FLUSH_BMSK 0x200 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_DELAYED_WR_FLUSH_SHFT 9 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_DISABLE_WR_PREFIL_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_DISABLE_WR_PREFIL_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x80 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 7 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x40 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 6 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_WRITE_BURST_SIZE_INT_BMSK 0x38 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_WRITE_BURST_SIZE_INT_SHFT 3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_WRITE_BURST_SIZE_EXT_BMSK 0x7 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_WRITE_BURST_SIZE_EXT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x) ((x) + 0xf4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_PHYS(x) ((x) + 0xf4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_OFFS (0xf4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_RMSK 0xffff0001 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_POR 0x00ff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_LIMIT_BMSK 0xffff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_LIMIT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_DISABLE_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_DISABLE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_ADDR(x) ((x) + 0xf8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_PHYS(x) ((x) + 0xf8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_OFFS (0xf8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_RMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_GXI_WDOG_WARN_STATUS_BMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_GXI_WDOG_WARN_STATUS_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_ADDR(x) ((x) + 0xfc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_PHYS(x) ((x) + 0xfc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_OFFS (0xfc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x) ((x) + 0x100) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_PHYS(x) ((x) + 0x100) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_OFFS (0x100) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_RMSK 0xffff0001 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_POR 0x00ff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_GXI_WDOG_HW_ERR_LIMIT_BMSK 0xffff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_GXI_WDOG_HW_ERR_LIMIT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_GXI_WDOG_HW_ERR_DISABLE_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_GXI_WDOG_HW_ERR_DISABLE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_ADDR(x) ((x) + 0x104) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_PHYS(x) ((x) + 0x104) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_OFFS (0x104) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_RMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_GXI_WDOG_HW_ERR_STATUS_BMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_GXI_WDOG_HW_ERR_STATUS_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) ((x) + 0x108) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) ((x) + 0x108) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_OFFS (0x108) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_RMSK 0xfffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 17 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) ((x) + 0x10c) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) ((x) + 0x10c) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_OFFS (0x10c) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_RMSK 0xfffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 17 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x110) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x110) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OFFS (0x110) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x114) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x114) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OFFS (0x114) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x118) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x118) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OFFS (0x118) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x11c) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x11c) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OFFS (0x11c) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) ((x) + 0x120) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) ((x) + 0x120) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_OFFS (0x120) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0xbfbf +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x8000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 15 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x3f00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x80 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 7 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x3f +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x) ((x) + 0x124) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_PHYS(x) ((x) + 0x124) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_OFFS (0x124) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RMSK 0xbfbf +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_WR_CMD_FIFO_DBG_EN_BMSK 0x8000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_WR_CMD_FIFO_DBG_EN_SHFT 15 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_WR_CMD_FIFO_ADDR_BMSK 0x3f00 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_WR_CMD_FIFO_ADDR_SHFT 8 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RD_CMD_FIFO_DBG_EN_BMSK 0x80 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RD_CMD_FIFO_DBG_EN_SHFT 7 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RD_CMD_FIFO_ADDR_BMSK 0x3f +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RD_CMD_FIFO_ADDR_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_ADDR(x) ((x) + 0x128) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_PHYS(x) ((x) + 0x128) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_OFFS (0x128) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RMSK 0x3f3f3f3f +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_WR_CMD_FIFO_WR_PTR_BMSK 0x3f000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_WR_CMD_FIFO_WR_PTR_SHFT 24 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_WR_CMD_FIFO_RD_PTR_BMSK 0x3f0000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_WR_CMD_FIFO_RD_PTR_SHFT 16 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RD_CMD_FIFO_WR_PTR_BMSK 0x3f00 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RD_CMD_FIFO_WR_PTR_SHFT 8 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RD_CMD_FIFO_RD_PTR_BMSK 0x3f +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RD_CMD_FIFO_RD_PTR_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_ADDR(x) ((x) + 0x12c) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_PHYS(x) ((x) + 0x12c) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_OFFS (0x12c) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_ADDR(x) ((x) + 0x130) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_PHYS(x) ((x) + 0x130) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_OFFS (0x130) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_ADDR(x) ((x) + 0x134) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_PHYS(x) ((x) + 0x134) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_OFFS (0x134) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_ADDR(x) ((x) + 0x138) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_PHYS(x) ((x) + 0x138) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_OFFS (0x138) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x) ((x) + 0x13c) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_PHYS(x) ((x) + 0x13c) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_OFFS (0x13c) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_REG_INT_ADDR_MASK_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_REG_INT_ADDR_MASK_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x) ((x) + 0x140) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_PHYS(x) ((x) + 0x140) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_OFFS (0x140) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_RMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_POR 0x00000010 +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_REG_INT_ADDR_MASK_MSB_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_REG_INT_ADDR_MASK_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x) ((x) + 0x144) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_PHYS(x) ((x) + 0x144) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_OFFS (0x144) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_POR 0x00b80000 +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_REG_SS_ADDR_RANGE_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_REG_SS_ADDR_RANGE_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x) ((x) + 0x148) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_PHYS(x) ((x) + 0x148) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_OFFS (0x148) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_RMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_POR 0x00000010 +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_REG_SS_ADDR_RANGE_MSB_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_REG_SS_ADDR_RANGE_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x) ((x) + 0x14c) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_PHYS(x) ((x) + 0x14c) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_OFFS (0x14c) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_RMSK 0xff13ff13 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_PORT_ID_BMSK 0xff000000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_PORT_ID_SHFT 24 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_ERR_INJ_DONE_BMSK 0x100000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_ERR_INJ_DONE_SHFT 20 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_PORT_CHK_EN_BMSK 0x20000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_PORT_CHK_EN_SHFT 17 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_INJ_ENABLE_BMSK 0x10000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_INJ_ENABLE_SHFT 16 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_PORT_ID_BMSK 0xff00 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_PORT_ID_SHFT 8 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_ERR_INJ_DONE_BMSK 0x10 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_ERR_INJ_DONE_SHFT 4 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_PORT_CHK_EN_BMSK 0x2 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_PORT_CHK_EN_SHFT 1 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_INJ_ENABLE_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_INJ_ENABLE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x) ((x) + 0x150) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_PHYS(x) ((x) + 0x150) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_OFFS (0x150) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_RMSK 0xff07ff07 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_PORT_ID_BMSK 0xff000000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_PORT_ID_SHFT 24 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_ERR_INJ_DONE_BMSK 0x40000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_ERR_INJ_DONE_SHFT 18 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_PORT_CHK_EN_BMSK 0x20000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_PORT_CHK_EN_SHFT 17 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_INJ_ENABLE_BMSK 0x10000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_INJ_ENABLE_SHFT 16 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_PORT_ID_BMSK 0xff00 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_PORT_ID_SHFT 8 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_ERR_INJ_DONE_BMSK 0x4 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_ERR_INJ_DONE_SHFT 2 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_PORT_CHK_EN_BMSK 0x2 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_PORT_CHK_EN_SHFT 1 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_INJ_ENABLE_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_INJ_ENABLE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x) ((x) + 0x154) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_PHYS(x) ((x) + 0x154) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_OFFS (0x154) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x) ((x) + 0x158) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_PHYS(x) ((x) + 0x158) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_OFFS (0x158) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_RMSK 0xff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_BMSK 0xff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x) ((x) + 0x15c) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_PHYS(x) ((x) + 0x15c) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_OFFS (0x15c) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x) ((x) + 0x160) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_PHYS(x) ((x) + 0x160) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_OFFS (0x160) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x) ((x) + 0x164) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_PHYS(x) ((x) + 0x164) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_OFFS (0x164) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x) ((x) + 0x168) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_PHYS(x) ((x) + 0x168) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_OFFS (0x168) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_RMSK 0xff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_BMSK 0xff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x) ((x) + 0x16c) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_PHYS(x) ((x) + 0x16c) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_OFFS (0x16c) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x) ((x) + 0x170) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_PHYS(x) ((x) + 0x170) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_OFFS (0x170) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x) ((x) + 0x174) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_PHYS(x) ((x) + 0x174) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_OFFS (0x174) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_RMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_POR 0x08000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TIMING_TRACKER_UNIT_BMSK 0x20000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TIMING_TRACKER_UNIT_SHFT 29 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACK_WRITES_ENABLE_BMSK 0x10000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACK_WRITES_ENABLE_SHFT 28 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACK_READS_ENABLE_BMSK 0x8000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACK_READS_ENABLE_SHFT 27 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACKING_EN_FOR_TIMEOUT_BMSK 0x4000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACKING_EN_FOR_TIMEOUT_SHFT 26 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACKING_EN_FOR_ERROR_BMSK 0x2000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACKING_EN_FOR_ERROR_SHFT 25 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_BMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x) ((x) + 0x178) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_PHYS(x) ((x) + 0x178) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_OFFS (0x178) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x) ((x) + 0x17c) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_PHYS(x) ((x) + 0x17c) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_OFFS (0x17c) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ADDR(x) ((x) + 0x180) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_PHYS(x) ((x) + 0x180) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_OFFS (0x180) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_RMSK 0xf +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ERROR_TRACKING_ARRAY_INDEX_BMSK 0xc +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ERROR_TRACKING_ARRAY_INDEX_SHFT 2 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_AXI_TIMEOUT_STATUS_BMSK 0x2 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_AXI_TIMEOUT_STATUS_SHFT 1 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_AXI_ERROR_STATUS_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_AXI_ERROR_STATUS_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR(base,n) ((base) + 0X184 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_PHYS(base,n) ((base) + 0X184 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_OFFS(n) (0X184 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_MAXn 3 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_RMSK) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR_LOW_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR_LOW_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR(base,n) ((base) + 0X194 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_PHYS(base,n) ((base) + 0X194 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_OFFS(n) (0X194 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_RMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_MAXn 3 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_RMSK) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_TRANSACTION_ONGOING_BMSK 0x20000000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_TRANSACTION_ONGOING_SHFT 29 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_NEXT_MISSED_CAPTURED_COUNT_BMSK 0x1c000000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_NEXT_MISSED_CAPTURED_COUNT_SHFT 26 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_TRANSACTION_SIZE_BMSK 0x3ffc000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_TRANSACTION_SIZE_SHFT 14 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_TRANSACTION_TYPE_BMSK 0x2000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_TRANSACTION_TYPE_SHFT 13 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_MID_BMSK 0x1f00 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_MID_SHFT 8 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR_HIGH_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR_HIGH_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n) ((base) + 0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n) ((base) + 0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n) (0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK 0xfff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn 3 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK 0xfff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_ADDR(x) ((x) + 0x1b4) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_PHYS(x) ((x) + 0x1b4) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_OFFS (0x1b4) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_TIMESTAMP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_TIMESTAMP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_ADDR(x) ((x) + 0x1b8) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_PHYS(x) ((x) + 0x1b8) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_OFFS (0x1b8) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_TIMESTAMP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_TIMESTAMP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x) ((x) + 0x1bc) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_PHYS(x) ((x) + 0x1bc) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_OFFS (0x1bc) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_RMSK 0xfff +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_POR 0x00000049 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TQM_SEC_BIT_OVERRIDE_VAL_BMSK 0xc00 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TQM_SEC_BIT_OVERRIDE_VAL_SHFT 10 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TQM_SEC_BIT_OVERRIDE_EN_BMSK 0x200 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TQM_SEC_BIT_OVERRIDE_EN_SHFT 9 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_REO_SEC_BIT_OVERRIDE_VAL_BMSK 0x180 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_REO_SEC_BIT_OVERRIDE_VAL_SHFT 7 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_REO_SEC_BIT_OVERRIDE_EN_BMSK 0x40 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_REO_SEC_BIT_OVERRIDE_EN_SHFT 6 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_WBM_SEC_BIT_OVERRIDE_VAL_BMSK 0x30 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_WBM_SEC_BIT_OVERRIDE_VAL_SHFT 4 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_WBM_SEC_BIT_OVERRIDE_EN_BMSK 0x8 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_WBM_SEC_BIT_OVERRIDE_EN_SHFT 3 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TCL_SEC_BIT_OVERRIDE_VAL_BMSK 0x6 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TCL_SEC_BIT_OVERRIDE_VAL_SHFT 1 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TCL_SEC_BIT_OVERRIDE_EN_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TCL_SEC_BIT_OVERRIDE_EN_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_ADDR(x) ((x) + 0x1c0) +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_PHYS(x) ((x) + 0x1c0) +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_OFFS (0x1c0) +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_RMSK 0x1ff01ff +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_WR_FLUSH_CNT_NOT_ZERO_BMSK 0x1000000 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_WR_FLUSH_CNT_NOT_ZERO_SHFT 24 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_WR_PORT_ID_BMSK 0xff0000 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_WR_PORT_ID_SHFT 16 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_RD_FLUSH_CNT_NOT_ZERO_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_RD_FLUSH_CNT_NOT_ZERO_SHFT 8 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_RD_PORT_ID_BMSK 0xff +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_RD_PORT_ID_SHFT 0 + +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x500) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x500) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_OFFS (0x500) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_RMSK 0x1001f +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R1_TESTBUS_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x10000 +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 16 +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x1f +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0 + +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_ADDR(x) ((x) + 0x504) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_PHYS(x) ((x) + 0x504) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_OFFS (0x504) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_POR 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_MASK_SHFT 0 + +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n) (0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn 63 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_ADDR(x) ((x) + 0x608) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_PHYS(x) ((x) + 0x608) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_OFFS (0x608) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_POR 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_MASK_SHFT 0 + +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x60c) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x60c) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x60c) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 17 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 2 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 1 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0 + +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x610) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x610) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_OFFS (0x610) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_IN(x)) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: WBM_REG + *--------------------------------------------------------------------------*/ + +#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) +#define WBM_REG_REG_BASE_SIZE 0x4000 +#define WBM_REG_REG_BASE_USED 0x3124 +#define WBM_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00034000) +#define WBM_REG_REG_BASE_OFFS 0x00034000 + +#define HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) +#define HWIO_WBM_R0_GENERAL_ENABLE_PHYS(x) ((x) + 0x0) +#define HWIO_WBM_R0_GENERAL_ENABLE_OFFS (0x0) +#define HWIO_WBM_R0_GENERAL_ENABLE_RMSK 0x9ff +#define HWIO_WBM_R0_GENERAL_ENABLE_POR 0x00000020 +#define HWIO_WBM_R0_GENERAL_ENABLE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_GENERAL_ENABLE_ATTR 0x3 +#define HWIO_WBM_R0_GENERAL_ENABLE_IN(x) \ + in_dword(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x)) +#define HWIO_WBM_R0_GENERAL_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), m) +#define HWIO_WBM_R0_GENERAL_ENABLE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x),v) +#define HWIO_WBM_R0_GENERAL_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x),m,v,HWIO_WBM_R0_GENERAL_ENABLE_IN(x)) +#define HWIO_WBM_R0_GENERAL_ENABLE_LOWER_WATERMARK_DISABLE_BMSK 0x800 +#define HWIO_WBM_R0_GENERAL_ENABLE_LOWER_WATERMARK_DISABLE_SHFT 11 +#define HWIO_WBM_R0_GENERAL_ENABLE_LPM_CACHE_SELF_FLUSH_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_GENERAL_ENABLE_LPM_CACHE_SELF_FLUSH_ENABLE_SHFT 8 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x80 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT 7 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_BMSK 0x40 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_SHFT 6 +#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_BMSK 0x20 +#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_SHFT 5 +#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_BMSK 0x10 +#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_SHFT 4 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x8 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_SHFT 3 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x4 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_SHFT 2 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x2 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_SHFT 1 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_DUP_DET_CFG_ADDR(x) ((x) + 0x4) +#define HWIO_WBM_R0_DUP_DET_CFG_PHYS(x) ((x) + 0x4) +#define HWIO_WBM_R0_DUP_DET_CFG_OFFS (0x4) +#define HWIO_WBM_R0_DUP_DET_CFG_RMSK 0x1ff +#define HWIO_WBM_R0_DUP_DET_CFG_POR 0x000000ff +#define HWIO_WBM_R0_DUP_DET_CFG_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_CFG_ATTR 0x3 +#define HWIO_WBM_R0_DUP_DET_CFG_IN(x) \ + in_dword(HWIO_WBM_R0_DUP_DET_CFG_ADDR(x)) +#define HWIO_WBM_R0_DUP_DET_CFG_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_DUP_DET_CFG_ADDR(x), m) +#define HWIO_WBM_R0_DUP_DET_CFG_OUT(x, v) \ + out_dword(HWIO_WBM_R0_DUP_DET_CFG_ADDR(x),v) +#define HWIO_WBM_R0_DUP_DET_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_DUP_DET_CFG_ADDR(x),m,v,HWIO_WBM_R0_DUP_DET_CFG_IN(x)) +#define HWIO_WBM_R0_DUP_DET_CFG_IDLE_DIST_DUP_CHECK_BMSK 0x100 +#define HWIO_WBM_R0_DUP_DET_CFG_IDLE_DIST_DUP_CHECK_SHFT 8 +#define HWIO_WBM_R0_DUP_DET_CFG_SW_TX_RELEASE_RING_EN_BMSK 0x80 +#define HWIO_WBM_R0_DUP_DET_CFG_SW_TX_RELEASE_RING_EN_SHFT 7 +#define HWIO_WBM_R0_DUP_DET_CFG_FW_TX_RELEASE_RING_EN_BMSK 0x40 +#define HWIO_WBM_R0_DUP_DET_CFG_FW_TX_RELEASE_RING_EN_SHFT 6 +#define HWIO_WBM_R0_DUP_DET_CFG_TQM_RELEASE_RING_EN_BMSK 0x20 +#define HWIO_WBM_R0_DUP_DET_CFG_TQM_RELEASE_RING_EN_SHFT 5 +#define HWIO_WBM_R0_DUP_DET_CFG_SW_RX_RELEASE_RING_EN_BMSK 0x10 +#define HWIO_WBM_R0_DUP_DET_CFG_SW_RX_RELEASE_RING_EN_SHFT 4 +#define HWIO_WBM_R0_DUP_DET_CFG_FW_RX_RELEASE_RING_EN_BMSK 0x8 +#define HWIO_WBM_R0_DUP_DET_CFG_FW_RX_RELEASE_RING_EN_SHFT 3 +#define HWIO_WBM_R0_DUP_DET_CFG_REO_RELEASE_RING_EN_BMSK 0x4 +#define HWIO_WBM_R0_DUP_DET_CFG_REO_RELEASE_RING_EN_SHFT 2 +#define HWIO_WBM_R0_DUP_DET_CFG_RXDMA_RELEASE_RING_EN_BMSK 0x2 +#define HWIO_WBM_R0_DUP_DET_CFG_RXDMA_RELEASE_RING_EN_SHFT 1 +#define HWIO_WBM_R0_DUP_DET_CFG_DUPLICATE_DETECTION_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_DUP_DET_CFG_DUPLICATE_DETECTION_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x) ((x) + 0x8) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_PHYS(x) ((x) + 0x8) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_OFFS (0x8) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_RMSK 0xff +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_POR 0x00000000 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_ATTR 0x3 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x)) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x), m) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x),v) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x),m,v,HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_IN(x)) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_OUT2_SRNG_P_MLO_BMSK 0xc0 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_OUT2_SRNG_P_MLO_SHFT 6 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_OUT1_SRNG_P_MLO_BMSK 0x30 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_OUT1_SRNG_P_MLO_SHFT 4 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_IN2_SRNG_C_MLO_BMSK 0xc +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_IN2_SRNG_C_MLO_SHFT 2 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_IN1_SRNG_C_MLO_BMSK 0x3 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_IN1_SRNG_C_MLO_SHFT 0 + +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x) ((x) + 0xc) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_PHYS(x) ((x) + 0xc) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_OFFS (0xc) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_RMSK 0x3 +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x)) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x),m,v,HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_IN(x)) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_WBM2WBM_OUT2_BMSK 0x2 +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_WBM2WBM_OUT2_SHFT 1 +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_WBM2WBM_OUT1_BMSK 0x1 +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_WBM2WBM_OUT1_SHFT 0 + +#define HWIO_WBM_R0_VC_ID_CFG_ADDR(x) ((x) + 0x10) +#define HWIO_WBM_R0_VC_ID_CFG_PHYS(x) ((x) + 0x10) +#define HWIO_WBM_R0_VC_ID_CFG_OFFS (0x10) +#define HWIO_WBM_R0_VC_ID_CFG_RMSK 0xfbbe +#define HWIO_WBM_R0_VC_ID_CFG_POR 0x00000800 +#define HWIO_WBM_R0_VC_ID_CFG_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VC_ID_CFG_ATTR 0x3 +#define HWIO_WBM_R0_VC_ID_CFG_IN(x) \ + in_dword(HWIO_WBM_R0_VC_ID_CFG_ADDR(x)) +#define HWIO_WBM_R0_VC_ID_CFG_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VC_ID_CFG_ADDR(x), m) +#define HWIO_WBM_R0_VC_ID_CFG_OUT(x, v) \ + out_dword(HWIO_WBM_R0_VC_ID_CFG_ADDR(x),v) +#define HWIO_WBM_R0_VC_ID_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_VC_ID_CFG_ADDR(x),m,v,HWIO_WBM_R0_VC_ID_CFG_IN(x)) +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_OUT2_VC_ID_BMSK 0x8000 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_OUT2_VC_ID_SHFT 15 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_OUT1_VC_ID_BMSK 0x4000 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_OUT1_VC_ID_SHFT 14 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_IN2_VC_ID_BMSK 0x2000 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_IN2_VC_ID_SHFT 13 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_IN1_VC_ID_BMSK 0x1000 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_IN1_VC_ID_SHFT 12 +#define HWIO_WBM_R0_VC_ID_CFG_VA_GXI_VC_ID_BMSK 0x800 +#define HWIO_WBM_R0_VC_ID_CFG_VA_GXI_VC_ID_SHFT 11 +#define HWIO_WBM_R0_VC_ID_CFG_CACHE1_GXI_VC_ID_BMSK 0x200 +#define HWIO_WBM_R0_VC_ID_CFG_CACHE1_GXI_VC_ID_SHFT 9 +#define HWIO_WBM_R0_VC_ID_CFG_IDLE_LINK_P_RING_VC_ID_BMSK 0x100 +#define HWIO_WBM_R0_VC_ID_CFG_IDLE_LINK_P_RING_VC_ID_SHFT 8 +#define HWIO_WBM_R0_VC_ID_CFG_IDLE_LINK_C_RING_VC_ID_BMSK 0x80 +#define HWIO_WBM_R0_VC_ID_CFG_IDLE_LINK_C_RING_VC_ID_SHFT 7 +#define HWIO_WBM_R0_VC_ID_CFG_RXDMA0_RELEASE_RING_VC_ID_BMSK 0x20 +#define HWIO_WBM_R0_VC_ID_CFG_RXDMA0_RELEASE_RING_VC_ID_SHFT 5 +#define HWIO_WBM_R0_VC_ID_CFG_FW_RELEASE_RING_VC_ID_BMSK 0x10 +#define HWIO_WBM_R0_VC_ID_CFG_FW_RELEASE_RING_VC_ID_SHFT 4 +#define HWIO_WBM_R0_VC_ID_CFG_SW_RELEASE_RING_VC_ID_BMSK 0x8 +#define HWIO_WBM_R0_VC_ID_CFG_SW_RELEASE_RING_VC_ID_SHFT 3 +#define HWIO_WBM_R0_VC_ID_CFG_REO_RELEASE_RING_VC_ID_BMSK 0x4 +#define HWIO_WBM_R0_VC_ID_CFG_REO_RELEASE_RING_VC_ID_SHFT 2 +#define HWIO_WBM_R0_VC_ID_CFG_TQM_RELEASE_RING_VC_ID_BMSK 0x2 +#define HWIO_WBM_R0_VC_ID_CFG_TQM_RELEASE_RING_VC_ID_SHFT 1 + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x) ((x) + 0x14) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_PHYS(x) ((x) + 0x14) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OFFS (0x14) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RMSK 0xfe +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_POR 0x00000000 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_ATTR 0x3 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x) \ + in_dword(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x)) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), m) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x),v) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x),m,v,HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x)) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA2_RELEASE_RING_ENABLE_BMSK 0x80 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA2_RELEASE_RING_ENABLE_SHFT 7 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA1_RELEASE_RING_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA1_RELEASE_RING_ENABLE_SHFT 6 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA0_RELEASE_RING_ENABLE_BMSK 0x20 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA0_RELEASE_RING_ENABLE_SHFT 5 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_FW_RELEASE_RING_ENABLE_BMSK 0x10 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_FW_RELEASE_RING_ENABLE_SHFT 4 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_SW_RELEASE_RING_ENABLE_BMSK 0x8 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_SW_RELEASE_RING_ENABLE_SHFT 3 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x4 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 2 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_TQM_RELEASE_RING_ENABLE_BMSK 0x2 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_TQM_RELEASE_RING_ENABLE_SHFT 1 + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_ADDR(x) ((x) + 0x18) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_PHYS(x) ((x) + 0x18) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_OFFS (0x18) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_RMSK 0x6 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_POR 0x00000000 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_ATTR 0x3 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_IN(x) \ + in_dword(HWIO_WBM_R0_RELEASE_RING_ENABLE_2_ADDR(x)) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RELEASE_RING_ENABLE_2_ADDR(x), m) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RELEASE_RING_ENABLE_2_ADDR(x),v) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_ENABLE_2_ADDR(x),m,v,HWIO_WBM_R0_RELEASE_RING_ENABLE_2_IN(x)) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_MLO_IN2_RELEASE_RING_ENABLE_BMSK 0x4 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_MLO_IN2_RELEASE_RING_ENABLE_SHFT 2 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_MLO_IN1_RELEASE_RING_ENABLE_BMSK 0x2 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_MLO_IN1_RELEASE_RING_ENABLE_SHFT 1 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x) ((x) + 0x1c) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_PHYS(x) ((x) + 0x1c) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OFFS (0x1c) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_RMSK 0x3f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ATTR 0x3 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x)) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x),v) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x),m,v,HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x)) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA2_BUF_RING_ENABLE_BMSK 0x20 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA2_BUF_RING_ENABLE_SHFT 5 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA1_BUF_RING_ENABLE_BMSK 0x10 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA1_BUF_RING_ENABLE_SHFT 4 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA0_BUF_RING_ENABLE_BMSK 0x8 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA0_BUF_RING_ENABLE_SHFT 3 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2FW_BUF_RING_ENABLE_BMSK 0x4 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2FW_BUF_RING_ENABLE_SHFT 2 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2SW_BUF_RING_ENABLE_BMSK 0x2 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2SW_BUF_RING_ENABLE_SHFT 1 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2PPE_BUF_RING_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2PPE_BUF_RING_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x) ((x) + 0x20) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_PHYS(x) ((x) + 0x20) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OFFS (0x20) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_RMSK 0x7f +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA2_LINK_RING_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA2_LINK_RING_ENABLE_SHFT 6 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA1_LINK_RING_ENABLE_BMSK 0x20 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA1_LINK_RING_ENABLE_SHFT 5 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA0_LINK_RING_ENABLE_BMSK 0x10 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA0_LINK_RING_ENABLE_SHFT 4 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2FW_LINK_RING_ENABLE_BMSK 0x8 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2FW_LINK_RING_ENABLE_SHFT 3 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2SW_LINK_RING_ENABLE_BMSK 0x4 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2SW_LINK_RING_ENABLE_SHFT 2 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x2 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 1 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2TQM_LINK_RING_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2TQM_LINK_RING_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_OWN_CHIP_ID_ADDR(x) ((x) + 0x24) +#define HWIO_WBM_R0_OWN_CHIP_ID_PHYS(x) ((x) + 0x24) +#define HWIO_WBM_R0_OWN_CHIP_ID_OFFS (0x24) +#define HWIO_WBM_R0_OWN_CHIP_ID_RMSK 0xf +#define HWIO_WBM_R0_OWN_CHIP_ID_POR 0x00000001 +#define HWIO_WBM_R0_OWN_CHIP_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_OWN_CHIP_ID_ATTR 0x3 +#define HWIO_WBM_R0_OWN_CHIP_ID_IN(x) \ + in_dword(HWIO_WBM_R0_OWN_CHIP_ID_ADDR(x)) +#define HWIO_WBM_R0_OWN_CHIP_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_OWN_CHIP_ID_ADDR(x), m) +#define HWIO_WBM_R0_OWN_CHIP_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_OWN_CHIP_ID_ADDR(x),v) +#define HWIO_WBM_R0_OWN_CHIP_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_OWN_CHIP_ID_ADDR(x),m,v,HWIO_WBM_R0_OWN_CHIP_ID_IN(x)) +#define HWIO_WBM_R0_OWN_CHIP_ID_RBM_BMSK 0xf +#define HWIO_WBM_R0_OWN_CHIP_ID_RBM_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT1_CFG_ADDR(x) ((x) + 0x28) +#define HWIO_WBM_R0_MLO_OUT1_CFG_PHYS(x) ((x) + 0x28) +#define HWIO_WBM_R0_MLO_OUT1_CFG_OFFS (0x28) +#define HWIO_WBM_R0_MLO_OUT1_CFG_RMSK 0x3ff +#define HWIO_WBM_R0_MLO_OUT1_CFG_POR 0x00000005 +#define HWIO_WBM_R0_MLO_OUT1_CFG_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_CFG_ATTR 0x3 +#define HWIO_WBM_R0_MLO_OUT1_CFG_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT1_CFG_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT1_CFG_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT1_CFG_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT1_CFG_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MLO_OUT1_CFG_ADDR(x),v) +#define HWIO_WBM_R0_MLO_OUT1_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MLO_OUT1_CFG_ADDR(x),m,v,HWIO_WBM_R0_MLO_OUT1_CFG_IN(x)) +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM2_BMSK 0x3c0 +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM2_SHFT 6 +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM2_ENABLE_BMSK 0x20 +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM2_ENABLE_SHFT 5 +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM1_BMSK 0x1e +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM1_SHFT 1 +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM1_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM1_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT2_CFG_ADDR(x) ((x) + 0x2c) +#define HWIO_WBM_R0_MLO_OUT2_CFG_PHYS(x) ((x) + 0x2c) +#define HWIO_WBM_R0_MLO_OUT2_CFG_OFFS (0x2c) +#define HWIO_WBM_R0_MLO_OUT2_CFG_RMSK 0x3ff +#define HWIO_WBM_R0_MLO_OUT2_CFG_POR 0x00000007 +#define HWIO_WBM_R0_MLO_OUT2_CFG_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_CFG_ATTR 0x3 +#define HWIO_WBM_R0_MLO_OUT2_CFG_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT2_CFG_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT2_CFG_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT2_CFG_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT2_CFG_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MLO_OUT2_CFG_ADDR(x),v) +#define HWIO_WBM_R0_MLO_OUT2_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MLO_OUT2_CFG_ADDR(x),m,v,HWIO_WBM_R0_MLO_OUT2_CFG_IN(x)) +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM2_BMSK 0x3c0 +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM2_SHFT 6 +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM2_ENABLE_BMSK 0x20 +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM2_ENABLE_SHFT 5 +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM1_BMSK 0x1e +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM1_SHFT 1 +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM1_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM1_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x) ((x) + 0x30) +#define HWIO_WBM_R0_MISC_RING_ENABLE_PHYS(x) ((x) + 0x30) +#define HWIO_WBM_R0_MISC_RING_ENABLE_OFFS (0x30) +#define HWIO_WBM_R0_MISC_RING_ENABLE_RMSK 0x7ff +#define HWIO_WBM_R0_MISC_RING_ENABLE_POR 0x000007ff +#define HWIO_WBM_R0_MISC_RING_ENABLE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MISC_RING_ENABLE_ATTR 0x3 +#define HWIO_WBM_R0_MISC_RING_ENABLE_IN(x) \ + in_dword(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x)) +#define HWIO_WBM_R0_MISC_RING_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), m) +#define HWIO_WBM_R0_MISC_RING_ENABLE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x),v) +#define HWIO_WBM_R0_MISC_RING_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x),m,v,HWIO_WBM_R0_MISC_RING_ENABLE_IN(x)) +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2WBM_OUT2_MLO_RELEASE_RING_ENABLE_BMSK 0x400 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2WBM_OUT2_MLO_RELEASE_RING_ENABLE_SHFT 10 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2WBM_OUT1_MLO_RELEASE_RING_ENABLE_BMSK 0x200 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2WBM_OUT1_MLO_RELEASE_RING_ENABLE_SHFT 9 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW6_RELEASE_RING_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW6_RELEASE_RING_ENABLE_SHFT 8 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW5_RELEASE_RING_ENABLE_BMSK 0x80 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW5_RELEASE_RING_ENABLE_SHFT 7 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM_ERROR_RELEASE_RING_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM_ERROR_RELEASE_RING_ENABLE_SHFT 6 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW4_RELEASE_RING_ENABLE_BMSK 0x20 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW4_RELEASE_RING_ENABLE_SHFT 5 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW3_RELEASE_RING_ENABLE_BMSK 0x10 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW3_RELEASE_RING_ENABLE_SHFT 4 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW2_RELEASE_RING_ENABLE_BMSK 0x8 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW2_RELEASE_RING_ENABLE_SHFT 3 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW1_RELEASE_RING_ENABLE_BMSK 0x4 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW1_RELEASE_RING_ENABLE_SHFT 2 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW0_RELEASE_RING_ENABLE_BMSK 0x2 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW0_RELEASE_RING_ENABLE_SHFT 1 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2FW_RELEASE_RING_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2FW_RELEASE_RING_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x34) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x34) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_OFFS (0x34) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RMSK 0xfe +#define HWIO_WBM_R0_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA2_RELEASE_RING_NOT_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA2_RELEASE_RING_NOT_IDLE_SHFT 7 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA1_RELEASE_RING_NOT_IDLE_BMSK 0x40 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA1_RELEASE_RING_NOT_IDLE_SHFT 6 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA0_RELEASE_RING_NOT_IDLE_BMSK 0x20 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA0_RELEASE_RING_NOT_IDLE_SHFT 5 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_FW_RELEASE_RING_NOT_IDLE_BMSK 0x10 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_FW_RELEASE_RING_NOT_IDLE_SHFT 4 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_SW_RELEASE_RING_NOT_IDLE_BMSK 0x8 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_SW_RELEASE_RING_NOT_IDLE_SHFT 3 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_REO_RELEASE_RING_NOT_IDLE_BMSK 0x4 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_REO_RELEASE_RING_NOT_IDLE_SHFT 2 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_TQM_RELEASE_RING_NOT_IDLE_BMSK 0x2 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_TQM_RELEASE_RING_NOT_IDLE_SHFT 1 + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_ADDR(x) ((x) + 0x38) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_PHYS(x) ((x) + 0x38) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_OFFS (0x38) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_RMSK 0x6 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_POR 0x00000000 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_ATTR 0x1 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_IN(x) \ + in_dword(HWIO_WBM_R0_RELEASE_RING_STATUS_2_ADDR(x)) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RELEASE_RING_STATUS_2_ADDR(x), m) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_WBM2WBM_IN2_MLO_RING_NOT_IDLE_BMSK 0x4 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_WBM2WBM_IN2_MLO_RING_NOT_IDLE_SHFT 2 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_WBM2WBM_IN1_MLO_RING_NOT_IDLE_BMSK 0x2 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_WBM2WBM_IN1_MLO_RING_NOT_IDLE_SHFT 1 + +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x) ((x) + 0x3c) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_PHYS(x) ((x) + 0x3c) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_OFFS (0x3c) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_RMSK 0xfffff +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_POR 0x00000000 +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_ATTR 0x3 +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_IN(x) \ + in_dword(HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x)) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x), m) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x),v) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x),m,v,HWIO_WBM_R0_DUP_DET_START_COOKIE_IN(x)) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_DUP_DET_START_COOKIE_BMSK 0xfffff +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_DUP_DET_START_COOKIE_SHFT 0 + +#define HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x40) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_PHYS(x) ((x) + 0x40) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_OFFS (0x40) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CFG0_POR 0x00000000 +#define HWIO_WBM_R0_SW_COOKIE_CFG0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CFG0_ATTR 0x3 +#define HWIO_WBM_R0_SW_COOKIE_CFG0_IN(x) \ + in_dword(HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x)) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x), m) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x),v) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_WBM_R0_SW_COOKIE_CFG0_IN(x)) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT 0 + +#define HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x44) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PHYS(x) ((x) + 0x44) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_OFFS (0x44) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_RMSK 0x7ffff +#define HWIO_WBM_R0_SW_COOKIE_CFG1_POR 0x00011700 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CFG1_ATTR 0x3 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_IN(x) \ + in_dword(HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x)) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x), m) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x),v) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_WBM_R0_SW_COOKIE_CFG1_IN(x)) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_WBM_R0_BP_WARNING_STATUS_ADDR(x) ((x) + 0x48) +#define HWIO_WBM_R0_BP_WARNING_STATUS_PHYS(x) ((x) + 0x48) +#define HWIO_WBM_R0_BP_WARNING_STATUS_OFFS (0x48) +#define HWIO_WBM_R0_BP_WARNING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_BP_WARNING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_BP_WARNING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_BP_WARNING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_BP_WARNING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_BP_WARNING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_BP_WARNING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_BP_WARNING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_BP_WARNING_STATUS_BP_STATUS_BMSK 0xffffffff +#define HWIO_WBM_R0_BP_WARNING_STATUS_BP_STATUS_SHFT 0 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x) ((x) + 0x4c) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_PHYS(x) ((x) + 0x4c) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OFFS (0x4c) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_RMSK 0x3f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA2_BUF_RING_NOT_IDLE_BMSK 0x20 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA2_BUF_RING_NOT_IDLE_SHFT 5 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA1_BUF_RING_NOT_IDLE_BMSK 0x10 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA1_BUF_RING_NOT_IDLE_SHFT 4 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA0_BUF_RING_NOT_IDLE_BMSK 0x8 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA0_BUF_RING_NOT_IDLE_SHFT 3 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2FW_BUF_RING_NOT_IDLE_BMSK 0x4 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2FW_BUF_RING_NOT_IDLE_SHFT 2 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2SW_BUF_RING_NOT_IDLE_BMSK 0x2 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2SW_BUF_RING_NOT_IDLE_SHFT 1 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2PPE_BUF_RING_NOT_IDLE_BMSK 0x1 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2PPE_BUF_RING_NOT_IDLE_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x) ((x) + 0x50) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_PHYS(x) ((x) + 0x50) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OFFS (0x50) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_RMSK 0x7f +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA2_LINK_RING_NOT_IDLE_BMSK 0x40 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA2_LINK_RING_NOT_IDLE_SHFT 6 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA1_LINK_RING_NOT_IDLE_BMSK 0x20 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA1_LINK_RING_NOT_IDLE_SHFT 5 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA0_LINK_RING_NOT_IDLE_BMSK 0x10 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA0_LINK_RING_NOT_IDLE_SHFT 4 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2FW_LINK_RING_NOT_IDLE_BMSK 0x8 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2FW_LINK_RING_NOT_IDLE_SHFT 3 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2SW_LINK_RING_NOT_IDLE_BMSK 0x4 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2SW_LINK_RING_NOT_IDLE_SHFT 2 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2REO_LINK_RING_NOT_IDLE_BMSK 0x2 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2REO_LINK_RING_NOT_IDLE_SHFT 1 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2TQM_LINK_RING_NOT_IDLE_BMSK 0x1 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2TQM_LINK_RING_NOT_IDLE_SHFT 0 + +#define HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x) ((x) + 0x54) +#define HWIO_WBM_R0_MISC_RING_STATUS_PHYS(x) ((x) + 0x54) +#define HWIO_WBM_R0_MISC_RING_STATUS_OFFS (0x54) +#define HWIO_WBM_R0_MISC_RING_STATUS_RMSK 0x1fff +#define HWIO_WBM_R0_MISC_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_MISC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MISC_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_MISC_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_MISC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_MISC_RING_STATUS_SW6_BUFFER_RING_NOT_IDLE_BMSK 0x1000 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW6_BUFFER_RING_NOT_IDLE_SHFT 12 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW5_BUFFER_RING_NOT_IDLE_BMSK 0x800 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW5_BUFFER_RING_NOT_IDLE_SHFT 11 +#define HWIO_WBM_R0_MISC_RING_STATUS_ERROR_RELEASE_RING_NOT_IDLE_BMSK 0x400 +#define HWIO_WBM_R0_MISC_RING_STATUS_ERROR_RELEASE_RING_NOT_IDLE_SHFT 10 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW4_BUFFER_RING_NOT_IDLE_BMSK 0x200 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW4_BUFFER_RING_NOT_IDLE_SHFT 9 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_BMSK 0x100 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_SHFT 8 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_SHFT 7 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_BMSK 0x40 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_SHFT 6 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_BMSK 0x20 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_SHFT 5 +#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_BMSK 0x10 +#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_SHFT 4 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x8 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT 3 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x4 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT 2 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x2 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT 1 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x1 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT 0 + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x) ((x) + 0x58) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_PHYS(x) ((x) + 0x58) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OFFS (0x58) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RMSK 0x13fff +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_POR 0x00000000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_ATTR 0x3 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x) \ + in_dword(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x)) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), m) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x),v) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x),m,v,HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x)) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_BMSK 0x10000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_SHFT 16 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_BMSK 0x2000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_SHFT 13 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_BMSK 0x1000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_SHFT 12 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_BMSK 0xfff +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_SHFT 0 + +#define HWIO_WBM_R0_IDLE_STATUS_ADDR(x) ((x) + 0x5c) +#define HWIO_WBM_R0_IDLE_STATUS_PHYS(x) ((x) + 0x5c) +#define HWIO_WBM_R0_IDLE_STATUS_OFFS (0x5c) +#define HWIO_WBM_R0_IDLE_STATUS_RMSK 0x17ffff +#define HWIO_WBM_R0_IDLE_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_STATUS_ADDR(x)) +#define HWIO_WBM_R0_IDLE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_STATUS_WBM2WBM_OUT2_MLO_PROD_FIFO_IN_IDLE_BMSK 0x100000 +#define HWIO_WBM_R0_IDLE_STATUS_WBM2WBM_OUT2_MLO_PROD_FIFO_IN_IDLE_SHFT 20 +#define HWIO_WBM_R0_IDLE_STATUS_SW6_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x40000 +#define HWIO_WBM_R0_IDLE_STATUS_SW6_BUFFER_PROD_FIFO_IN_IDLE_SHFT 18 +#define HWIO_WBM_R0_IDLE_STATUS_SW5_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x20000 +#define HWIO_WBM_R0_IDLE_STATUS_SW5_BUFFER_PROD_FIFO_IN_IDLE_SHFT 17 +#define HWIO_WBM_R0_IDLE_STATUS_ERROR_RELEASE_PROD_FIFO_IN_IDLE_BMSK 0x10000 +#define HWIO_WBM_R0_IDLE_STATUS_ERROR_RELEASE_PROD_FIFO_IN_IDLE_SHFT 16 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_BMSK 0x8000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_SHFT 15 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_BMSK 0x4000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_SHFT 14 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_BMSK 0x2000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_SHFT 13 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_BMSK 0x1000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_SHFT 12 +#define HWIO_WBM_R0_IDLE_STATUS_SW4_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x800 +#define HWIO_WBM_R0_IDLE_STATUS_SW4_BUFFER_PROD_FIFO_IN_IDLE_SHFT 11 +#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x400 +#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_SHFT 10 +#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x200 +#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_SHFT 9 +#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x100 +#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_SHFT 8 +#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_SHFT 7 +#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x40 +#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_SHFT 6 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_BMSK 0x20 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_SHFT 5 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x10 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT 4 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x8 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT 3 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x4 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT 2 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x2 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT 1 +#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_SHFT 0 + +#define HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x) ((x) + 0x70) +#define HWIO_WBM_R0_IDLE_SEQUENCE_PHYS(x) ((x) + 0x70) +#define HWIO_WBM_R0_IDLE_SEQUENCE_OFFS (0x70) +#define HWIO_WBM_R0_IDLE_SEQUENCE_RMSK 0x3f +#define HWIO_WBM_R0_IDLE_SEQUENCE_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_SEQUENCE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_SEQUENCE_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_SEQUENCE_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x)) +#define HWIO_WBM_R0_IDLE_SEQUENCE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_BMSK 0x20 +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_SHFT 5 +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_BMSK 0x10 +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_SHFT 4 +#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_BMSK 0xf +#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x) ((x) + 0x74) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_PHYS(x) ((x) + 0x74) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OFFS (0x74) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_RMSK 0x7 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_ATTR 0x3 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x),v) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x),m,v,HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x)) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_BMSK 0x4 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_SHFT 2 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_BMSK 0x2 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_SHFT 1 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_BMSK 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x) ((x) + 0x78) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_PHYS(x) ((x) + 0x78) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_OFFS (0x78) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK 0xfff +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_POR 0x00000441 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_BMSK 0x800 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_SHFT 11 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_BMSK 0x400 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_SHFT 10 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_BMSK 0x3c0 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_SHFT 6 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_BMSK 0x20 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_SHFT 5 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_BMSK 0x1f +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_SHFT 0 + +#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x7c) +#define HWIO_WBM_R0_MISC_CONTROL_PHYS(x) ((x) + 0x7c) +#define HWIO_WBM_R0_MISC_CONTROL_OFFS (0x7c) +#define HWIO_WBM_R0_MISC_CONTROL_RMSK 0xffffffff +#define HWIO_WBM_R0_MISC_CONTROL_POR 0x000001c0 +#define HWIO_WBM_R0_MISC_CONTROL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MISC_CONTROL_ATTR 0x3 +#define HWIO_WBM_R0_MISC_CONTROL_IN(x) \ + in_dword(HWIO_WBM_R0_MISC_CONTROL_ADDR(x)) +#define HWIO_WBM_R0_MISC_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MISC_CONTROL_ADDR(x), m) +#define HWIO_WBM_R0_MISC_CONTROL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MISC_CONTROL_ADDR(x),v) +#define HWIO_WBM_R0_MISC_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MISC_CONTROL_ADDR(x),m,v,HWIO_WBM_R0_MISC_CONTROL_IN(x)) +#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0xfffffffc +#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 2 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_BMSK 0x2 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_SHFT 1 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_BMSK 0x1 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_SHFT 0 + +#define HWIO_WBM_R0_SPARE_CTRL_2_ADDR(x) ((x) + 0x80) +#define HWIO_WBM_R0_SPARE_CTRL_2_PHYS(x) ((x) + 0x80) +#define HWIO_WBM_R0_SPARE_CTRL_2_OFFS (0x80) +#define HWIO_WBM_R0_SPARE_CTRL_2_RMSK 0xffffffff +#define HWIO_WBM_R0_SPARE_CTRL_2_POR 0x00000000 +#define HWIO_WBM_R0_SPARE_CTRL_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SPARE_CTRL_2_ATTR 0x3 +#define HWIO_WBM_R0_SPARE_CTRL_2_IN(x) \ + in_dword(HWIO_WBM_R0_SPARE_CTRL_2_ADDR(x)) +#define HWIO_WBM_R0_SPARE_CTRL_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SPARE_CTRL_2_ADDR(x), m) +#define HWIO_WBM_R0_SPARE_CTRL_2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SPARE_CTRL_2_ADDR(x),v) +#define HWIO_WBM_R0_SPARE_CTRL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SPARE_CTRL_2_ADDR(x),m,v,HWIO_WBM_R0_SPARE_CTRL_2_IN(x)) +#define HWIO_WBM_R0_SPARE_CTRL_2_SPARE_CONTROL_2_BMSK 0xffffffff +#define HWIO_WBM_R0_SPARE_CTRL_2_SPARE_CONTROL_2_SHFT 0 + +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_ADDR(x) ((x) + 0x84) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_PHYS(x) ((x) + 0x84) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_OFFS (0x84) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_RMSK 0x3ffffcf +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_POR 0x00000000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_ATTR 0x3 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_IN(x) \ + in_dword(HWIO_WBM_R0_RING_PRIORITY_CFG0_ADDR(x)) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RING_PRIORITY_CFG0_ADDR(x), m) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RING_PRIORITY_CFG0_ADDR(x),v) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RING_PRIORITY_CFG0_ADDR(x),m,v,HWIO_WBM_R0_RING_PRIORITY_CFG0_IN(x)) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2RXDMA0_LINK_RING_PRIORITY_BMSK 0x3000000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2RXDMA0_LINK_RING_PRIORITY_SHFT 24 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2FW_LINK_RING_PRIORITY_BMSK 0xc00000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2FW_LINK_RING_PRIORITY_SHFT 22 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2SW_LINK_RING_PRIORITY_BMSK 0x300000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2SW_LINK_RING_PRIORITY_SHFT 20 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2REO_LINK_RING_PRIORITY_BMSK 0xc0000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2REO_LINK_RING_PRIORITY_SHFT 18 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2TQM_LINK_RING_PRIORITY_BMSK 0x30000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2TQM_LINK_RING_PRIORITY_SHFT 16 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_RXDMA0_RELEASE_RING_PRIORITY_BMSK 0xc000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_RXDMA0_RELEASE_RING_PRIORITY_SHFT 14 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_FW_RELEASE_RING_PRIORITY_BMSK 0x3000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_FW_RELEASE_RING_PRIORITY_SHFT 12 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_SW_RELEASE_RING_PRIORITY_BMSK 0xc00 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_SW_RELEASE_RING_PRIORITY_SHFT 10 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_REO_RELEASE_RING_PRIORITY_BMSK 0x300 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_REO_RELEASE_RING_PRIORITY_SHFT 8 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_TQM_RELEASE_RING_PRIORITY_BMSK 0xc0 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_TQM_RELEASE_RING_PRIORITY_SHFT 6 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_LINK_IDLE_LIST_CONSUMER_RING_PRIORITY_BMSK 0xc +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_LINK_IDLE_LIST_CONSUMER_RING_PRIORITY_SHFT 2 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_LINK_IDLE_LIST_PRODUCER_RING_PRIORITY_BMSK 0x3 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_LINK_IDLE_LIST_PRODUCER_RING_PRIORITY_SHFT 0 + +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_ADDR(x) ((x) + 0x88) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_PHYS(x) ((x) + 0x88) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_OFFS (0x88) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_RMSK 0xfffff +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_POR 0x00000000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_ATTR 0x3 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_IN(x) \ + in_dword(HWIO_WBM_R0_RING_PRIORITY_CFG1_ADDR(x)) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RING_PRIORITY_CFG1_ADDR(x), m) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RING_PRIORITY_CFG1_ADDR(x),v) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RING_PRIORITY_CFG1_ADDR(x),m,v,HWIO_WBM_R0_RING_PRIORITY_CFG1_IN(x)) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_SW_COOKIE_CONV_GXI_PRIORITY_BMSK 0xc0000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_SW_COOKIE_CONV_GXI_PRIORITY_SHFT 18 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW6_RELEASE_RING_PRIORITY_BMSK 0x30000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW6_RELEASE_RING_PRIORITY_SHFT 16 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW5_RELEASE_RING_PRIORITY_BMSK 0xc000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW5_RELEASE_RING_PRIORITY_SHFT 14 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM_ERROR_RELEASE_RING_PRIORITY_BMSK 0x3000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM_ERROR_RELEASE_RING_PRIORITY_SHFT 12 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW4_RELEASE_RING_PRIORITY_BMSK 0xc00 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW4_RELEASE_RING_PRIORITY_SHFT 10 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW3_RELEASE_RING_PRIORITY_BMSK 0x300 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW3_RELEASE_RING_PRIORITY_SHFT 8 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW2_RELEASE_RING_PRIORITY_BMSK 0xc0 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW2_RELEASE_RING_PRIORITY_SHFT 6 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW1_RELEASE_RING_PRIORITY_BMSK 0x30 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW1_RELEASE_RING_PRIORITY_SHFT 4 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW0_RELEASE_RING_PRIORITY_BMSK 0xc +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW0_RELEASE_RING_PRIORITY_SHFT 2 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2FW_RELEASE_RING_PRIORITY_BMSK 0x3 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2FW_RELEASE_RING_PRIORITY_SHFT 0 + +#define HWIO_WBM_R0_WBM_CFG_2_ADDR(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_PHYS(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_OFFS (0x90) +#define HWIO_WBM_R0_WBM_CFG_2_RMSK 0x4b +#define HWIO_WBM_R0_WBM_CFG_2_POR 0x00000040 +#define HWIO_WBM_R0_WBM_CFG_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_CFG_2_ATTR 0x3 +#define HWIO_WBM_R0_WBM_CFG_2_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x)) +#define HWIO_WBM_R0_WBM_CFG_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_CFG_2_ADDR(x), m) +#define HWIO_WBM_R0_WBM_CFG_2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),v) +#define HWIO_WBM_R0_WBM_CFG_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),m,v,HWIO_WBM_R0_WBM_CFG_2_IN(x)) +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK 0x40 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_SHFT 6 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_BMSK 0x8 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_SHFT 3 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_SHFT 1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0 + +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x94) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_PHYS(x) ((x) + 0x94) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_OFFS (0x94) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_RMSK 0x1ff +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_POR 0x000001fe +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ATTR 0x3 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_IN(x) \ + in_dword(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x)) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x), m) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),v) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),m,v,HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_IN(x)) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_SHFT 7 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_SHFT 6 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_SHFT 5 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_SHFT 4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_SHFT 3 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_SHFT 2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_SHFT 1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x) ((x) + 0x98) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_PHYS(x) ((x) + 0x98) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_OFFS (0x98) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG0_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_WBM2REO_LINK_RING_WATERMARK_BMSK 0xffff0000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_WBM2REO_LINK_RING_WATERMARK_SHFT 16 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_WBM2TQM_LINK_RING_WATERMARK_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_WBM2TQM_LINK_RING_WATERMARK_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x) ((x) + 0x9c) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_PHYS(x) ((x) + 0x9c) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_OFFS (0x9c) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG1_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_WBM2FW_LINK_RING_WATERMARK_BMSK 0xffff0000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_WBM2FW_LINK_RING_WATERMARK_SHFT 16 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_WBM2SW_LINK_RING_WATERMARK_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_WBM2SW_LINK_RING_WATERMARK_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x) ((x) + 0xa0) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_PHYS(x) ((x) + 0xa0) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_OFFS (0xa0) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_RMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG2_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_WBM2RXDMA0_LINK_RING_WATERMARK_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_WBM2RXDMA0_LINK_RING_WATERMARK_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_ADDR(x) ((x) + 0xa4) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_PHYS(x) ((x) + 0xa4) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_OFFS (0xa4) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG3_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG3_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG3_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG3_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG3_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_WBM2REO_LINK_RING_WATERMARK_LOWER_BMSK 0xffff0000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_WBM2REO_LINK_RING_WATERMARK_LOWER_SHFT 16 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_WBM2TQM_LINK_RING_WATERMARK_LOWER_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_WBM2TQM_LINK_RING_WATERMARK_LOWER_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_ADDR(x) ((x) + 0xa8) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_PHYS(x) ((x) + 0xa8) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_OFFS (0xa8) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG4_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG4_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG4_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG4_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG4_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_WBM2FW_LINK_RING_WATERMARK_LOWER_BMSK 0xffff0000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_WBM2FW_LINK_RING_WATERMARK_LOWER_SHFT 16 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_WBM2SW_LINK_RING_WATERMARK_LOWER_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_WBM2SW_LINK_RING_WATERMARK_LOWER_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_ADDR(x) ((x) + 0xac) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_PHYS(x) ((x) + 0xac) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_OFFS (0xac) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_RMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG5_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG5_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG5_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG5_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG5_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_WBM2RXDMA0_LINK_RING_WATERMARK_LOWER_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_WBM2RXDMA0_LINK_RING_WATERMARK_LOWER_SHFT 0 + +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x) ((x) + 0xb0) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_PHYS(x) ((x) + 0xb0) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OFFS (0xb0) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RMSK 0x3fff +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_POR 0x00000000 +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_ATTR 0x3 +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x) \ + in_dword(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x)) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), m) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x),v) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x),m,v,HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x)) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK 0x3000 +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT 12 +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_ADDR(x) ((x) + 0xb4) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_PHYS(x) ((x) + 0xb4) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_OFFS (0xb4) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_RMSK 0x3fff +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_POR 0x00000000 +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_ATTR 0x3 +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_IN(x) \ + in_dword(HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_ADDR(x)) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_ADDR(x), m) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_ADDR(x),v) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_ADDR(x),m,v,HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_IN(x)) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK 0x3000 +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT 12 +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x) ((x) + 0xb8) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_PHYS(x) ((x) + 0xb8) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OFFS (0xb8) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RMSK 0x3fff +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_POR 0x00000000 +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ATTR 0x3 +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_IN(x) \ + in_dword(HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x)) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x), m) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OUT(x, v) \ + out_dword(HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x),v) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x),m,v,HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_IN(x)) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RESOLUTION_UNITS_BMSK 0x3000 +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RESOLUTION_UNITS_SHFT 12 +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_VALUE_BMSK 0xfff +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_VALUE_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x) ((x) + 0xbc) +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_PHYS(x) ((x) + 0xbc) +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_OFFS (0xbc) +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_RMSK 0x1fffff +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_ATTR 0x1 +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_ERR_BMSK 0x1e0000 +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_ERR_SHFT 17 +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_BMSK 0x1fff0 +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_SHFT 4 +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_P_STATE_ENC_BMSK 0xf +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_P_STATE_ENC_SHFT 0 + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x) ((x) + 0xc0) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_PHYS(x) ((x) + 0xc0) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OFFS (0xc0) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RMSK 0xffffffff +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_POR 0x00000000 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ATTR 0x1 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x) \ + in_dword(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x)) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), m) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_BMSK 0x80000000 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_SHFT 31 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_BMSK 0x40000000 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_SHFT 30 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_BMSK 0x30000000 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_SHFT 28 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_BMSK 0xffffe00 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_SHFT 9 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BM_ACTION_BMSK 0x180 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BM_ACTION_SHFT 7 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_BMSK 0x70 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_SHFT 4 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_BMSK 0xf +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_SHFT 0 + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_ADDR(x) ((x) + 0xc4) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_PHYS(x) ((x) + 0xc4) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_OFFS (0xc4) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_RMSK 0x7 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_POR 0x00000000 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_ATTR 0x1 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_IN(x) \ + in_dword(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_ADDR(x)) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_ADDR(x), m) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_RELEASE_SOURCE_MODULE_BMSK 0x7 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_RELEASE_SOURCE_MODULE_SHFT 0 + +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x) ((x) + 0xc8) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_PHYS(x) ((x) + 0xc8) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OFFS (0xc8) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_RMSK 0x7ffff +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_POR 0x00000000 +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ATTR 0x1 +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword(HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x)) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), m) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_TYPE_BMSK 0x60000 +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_TYPE_SHFT 17 +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_BMSK 0x1ffff +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_ADDR(x) ((x) + 0xcc) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_PHYS(x) ((x) + 0xcc) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_OFFS (0xcc) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_RMSK 0x7 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_ADDR(x)) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_ADDR(x),m,v,HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_IN(x)) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_BYPASS_COUNTER_FULL_BMSK 0x4 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_BYPASS_COUNTER_FULL_SHFT 2 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_FREEPOOL_COUNTER_FULL_BMSK 0x2 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_FREEPOOL_COUNTER_FULL_SHFT 1 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_COUNTER_CLR_BMSK 0x1 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_COUNTER_CLR_SHFT 0 + +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_ADDR(x) ((x) + 0xd0) +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_PHYS(x) ((x) + 0xd0) +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_OFFS (0xd0) +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_RMSK 0xffffffff +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_ATTR 0x1 +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_ADDR(x) ((x) + 0xd4) +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_PHYS(x) ((x) + 0xd4) +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_OFFS (0xd4) +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_RMSK 0xffffffff +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_ATTR 0x1 +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_ADDR(x) ((x) + 0xd8) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_PHYS(x) ((x) + 0xd8) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_OFFS (0xd8) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_POR 0x00000000 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_ATTR 0x1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_IN(x) \ + in_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_ADDR(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_ADDR(x), m) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_VALUE_SHFT 0 + +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_ADDR(x) ((x) + 0xdc) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_PHYS(x) ((x) + 0xdc) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_OFFS (0xdc) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_POR 0x00000000 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_ATTR 0x1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_IN(x) \ + in_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_ADDR(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_ADDR(x), m) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_VALUE_SHFT 0 + +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_ADDR(x) ((x) + 0xe0) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_PHYS(x) ((x) + 0xe0) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_OFFS (0xe0) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_POR 0x00000000 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_ATTR 0x1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_IN(x) \ + in_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_ADDR(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_ADDR(x), m) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_VALUE_SHFT 0 + +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_ADDR(x) ((x) + 0xe4) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_PHYS(x) ((x) + 0xe4) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_OFFS (0xe4) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_POR 0x00000000 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_ATTR 0x1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_IN(x) \ + in_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_ADDR(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_ADDR(x), m) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_VALUE_SHFT 0 + +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_ADDR(x) ((x) + 0xe8) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_PHYS(x) ((x) + 0xe8) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_OFFS (0xe8) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_POR 0x00000000 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_ATTR 0x1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_IN(x) \ + in_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_ADDR(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_ADDR(x), m) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_ADDR(x) ((x) + 0xec) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_PHYS(x) ((x) + 0xec) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_OFFS (0xec) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_RMSK 0x1f +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_POR 0x00000000 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_ATTR 0x3 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_IN(x) \ + in_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_ADDR(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_ADDR(x), m) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_OUT(x, v) \ + out_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_ADDR(x),v) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_ADDR(x),m,v,HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_IN(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_RXDMA_CLR_BMSK 0x10 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_RXDMA_CLR_SHFT 4 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_FW_CLR_BMSK 0x8 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_FW_CLR_SHFT 3 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_SW_CLR_BMSK 0x4 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_SW_CLR_SHFT 2 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_REO_CLR_BMSK 0x2 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_REO_CLR_SHFT 1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_TQM_CLR_BMSK 0x1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_TQM_CLR_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_ADDR(x) ((x) + 0xf0) +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_PHYS(x) ((x) + 0xf0) +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_OFFS (0xf0) +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_RMSK 0x1ffffff +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_COUNT_BMSK 0x1e00000 +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_COUNT_SHFT 21 +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_COOKIE_BMSK 0x1ffffe +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_COOKIE_SHFT 1 +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_VALID_BMSK 0x1 +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_VALID_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_ADDR(x) ((x) + 0xf4) +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_PHYS(x) ((x) + 0xf4) +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_OFFS (0xf4) +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_RMSK 0x1ffffff +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_ATTR 0x1 +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_COUNT_BMSK 0x1e00000 +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_COUNT_SHFT 21 +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_COOKIE_BMSK 0x1ffffe +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_COOKIE_SHFT 1 +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_VALID_BMSK 0x1 +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_VALID_SHFT 0 + +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_ADDR(x) ((x) + 0xf8) +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_PHYS(x) ((x) + 0xf8) +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_OFFS (0xf8) +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_RMSK 0x1ffffff +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_ADDR(x)) +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_COUNT_BMSK 0x1e00000 +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_COUNT_SHFT 21 +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_COOKIE_BMSK 0x1ffffe +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_COOKIE_SHFT 1 +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_VALID_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_VALID_SHFT 0 + +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_ADDR(x) ((x) + 0xfc) +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_PHYS(x) ((x) + 0xfc) +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_OFFS (0xfc) +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_RMSK 0xfffff +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_POR 0x00000000 +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_ATTR 0x1 +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_ADDR(x)) +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_ADDR(x), m) +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_COUNT_SHFT 0 + +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_ADDR(x) ((x) + 0x100) +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_PHYS(x) ((x) + 0x100) +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_OFFS (0x100) +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_RMSK 0xfffff +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_POR 0x00000000 +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_ATTR 0x1 +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_IN(x) \ + in_dword(HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_ADDR(x)) +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_ADDR(x), m) +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_COUNT_SHFT 0 + +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_ADDR(x) ((x) + 0x104) +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_PHYS(x) ((x) + 0x104) +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_OFFS (0x104) +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_RMSK 0xfffff +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_POR 0x00000000 +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_ATTR 0x1 +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_IN(x) \ + in_dword(HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_ADDR(x)) +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_ADDR(x), m) +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_COUNT_SHFT 0 + +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_ADDR(x) ((x) + 0x108) +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_PHYS(x) ((x) + 0x108) +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_OFFS (0x108) +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_RMSK 0xfffff +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_POR 0x00000000 +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_ATTR 0x1 +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_IN(x) \ + in_dword(HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_ADDR(x)) +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_ADDR(x), m) +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_COUNT_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_ADDR(x) ((x) + 0x10c) +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_PHYS(x) ((x) + 0x10c) +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_OFFS (0x10c) +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_RMSK 0xfffff +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_ATTR 0x1 +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_COUNT_SHFT 0 + +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_ADDR(x) ((x) + 0x110) +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_PHYS(x) ((x) + 0x110) +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_OFFS (0x110) +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_RMSK 0xfffff +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_POR 0x00000000 +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_ATTR 0x1 +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_IN(x) \ + in_dword(HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_ADDR(x)) +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_ADDR(x), m) +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_COUNT_SHFT 0 + +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_ADDR(x) ((x) + 0x114) +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_PHYS(x) ((x) + 0x114) +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_OFFS (0x114) +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_RMSK 0xfffff +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_POR 0x00000000 +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_ATTR 0x1 +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_IN(x) \ + in_dword(HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_ADDR(x)) +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_ADDR(x), m) +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_COUNT_SHFT 0 + +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_ADDR(x) ((x) + 0x118) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_PHYS(x) ((x) + 0x118) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_OFFS (0x118) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_RMSK 0x3ff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_RD_PTR_BMSK 0x3fe +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x11c) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x11c) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_OFFS (0x11c) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x120) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x120) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_OFFS (0x120) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_ADDR(x) ((x) + 0x124) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_PHYS(x) ((x) + 0x124) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_OFFS (0x124) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_RMSK 0x1ff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x1e0 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_INTERNAL_PTR_SHFT 5 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_UD_CNT_BMSK 0x1f +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_ADDR(x) ((x) + 0x128) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_PHYS(x) ((x) + 0x128) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_OFFS (0x128) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_RMSK 0x1f +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_RD_PTR_BMSK 0x1e +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x12c) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x12c) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_OFFS (0x12c) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x130) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x130) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_OFFS (0x130) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x134) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x134) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_OFFS (0x134) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_RMSK 0x3ffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_INTERNAL_BF_RDPTR_BMSK 0x3c000 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_INTERNAL_BF_RDPTR_SHFT 14 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_BUD_CNT_BMSK 0x3e00 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_BUD_CNT_SHFT 9 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_INTERNAL_RDPTR_BMSK 0x1e0 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_INTERNAL_RDPTR_SHFT 5 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x1f +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x138) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x138) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_OFFS (0x138) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_RMSK 0x1f +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x1e +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x13c) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x13c) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_OFFS (0x13c) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x140) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x140) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_OFFS (0x140) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_ADDR(x) ((x) + 0x144) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_PHYS(x) ((x) + 0x144) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_OFFS (0x144) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_RMSK 0x1f +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_RD_PTR_BMSK 0x1e +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x148) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x148) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_OFFS (0x148) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x14c) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x14c) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_OFFS (0x14c) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x) ((x) + 0x150) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_PHYS(x) ((x) + 0x150) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_OFFS (0x150) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_RMSK 0x7ff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x7c0 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_INTERNAL_PTR_SHFT 6 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x) ((x) + 0x154) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_PHYS(x) ((x) + 0x154) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_OFFS (0x154) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x158) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x158) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_OFFS (0x158) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x15c) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x15c) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_OFFS (0x15c) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x160) +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x160) +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_OFFS (0x160) +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x164) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x164) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_OFFS (0x164) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x168) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x168) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_OFFS (0x168) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x16c) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x16c) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_OFFS (0x16c) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x170) +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x170) +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_OFFS (0x170) +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x174) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x174) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_OFFS (0x174) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x178) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x178) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_OFFS (0x178) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x17c) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x17c) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_OFFS (0x17c) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x180) +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x180) +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_OFFS (0x180) +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x184) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x184) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_OFFS (0x184) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x188) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x188) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_OFFS (0x188) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x18c) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x18c) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_OFFS (0x18c) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x190) +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x190) +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_OFFS (0x190) +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x194) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x194) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_OFFS (0x194) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x198) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x198) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_OFFS (0x198) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x19c) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x19c) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_OFFS (0x19c) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1a0) +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1a0) +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_OFFS (0x1a0) +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1a4) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1a4) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_OFFS (0x1a4) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1a8) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1a8) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_OFFS (0x1a8) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1ac) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1ac) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_OFFS (0x1ac) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1b0) +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1b0) +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_OFFS (0x1b0) +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1b4) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1b4) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_OFFS (0x1b4) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1b8) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1b8) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_OFFS (0x1b8) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1bc) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1bc) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_OFFS (0x1bc) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1c0) +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1c0) +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_OFFS (0x1c0) +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1c4) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1c4) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_OFFS (0x1c4) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1c8) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1c8) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_OFFS (0x1c8) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1cc) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1cc) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_OFFS (0x1cc) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1d0) +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1d0) +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_OFFS (0x1d0) +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1d4) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1d4) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_OFFS (0x1d4) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1d8) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1d8) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_OFFS (0x1d8) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1dc) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1dc) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_OFFS (0x1dc) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1e0) +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1e0) +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_OFFS (0x1e0) +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1e4) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1e4) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_OFFS (0x1e4) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1e8) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1e8) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_OFFS (0x1e8) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1ec) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1ec) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_OFFS (0x1ec) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1f0) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1f0) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_OFFS (0x1f0) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1f4) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1f4) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_OFFS (0x1f4) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1f8) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1f8) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_OFFS (0x1f8) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1fc) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1fc) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_OFFS (0x1fc) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x200) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x200) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_OFFS (0x200) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x204) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x204) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_OFFS (0x204) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x208) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x208) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_OFFS (0x208) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x20c) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x20c) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_OFFS (0x20c) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x) ((x) + 0x210) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_PHYS(x) ((x) + 0x210) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_OFFS (0x210) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_RMSK 0x7f +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_PTR_BMSK 0x7e +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x) ((x) + 0x214) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_PHYS(x) ((x) + 0x214) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_OFFS (0x214) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_RMSK 0x1fff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x1f80 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_UD_CNT_BMSK 0x7f +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x218) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x218) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_OFFS (0x218) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x21c) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x21c) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_OFFS (0x21c) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x) ((x) + 0x220) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_PHYS(x) ((x) + 0x220) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_OFFS (0x220) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_RMSK 0x1f +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x18 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_INTERNAL_PTR_SHFT 3 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_UD_CNT_BMSK 0x7 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x) ((x) + 0x224) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_PHYS(x) ((x) + 0x224) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OFFS (0x224) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RMSK 0x7 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_PTR_BMSK 0x6 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x228) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x228) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_OFFS (0x228) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x) ((x) + 0x238) +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_PHYS(x) ((x) + 0x238) +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_OFFS (0x238) +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_RMSK 0xfffffff +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_VALUE_BMSK 0xfffffff +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_VALUE_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x) ((x) + 0x23c) +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_PHYS(x) ((x) + 0x23c) +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_OFFS (0x23c) +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_RMSK 0xfffffff +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ATTR 0x1 +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_VALUE_BMSK 0xfffffff +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_VALUE_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x240) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_PHYS(x) ((x) + 0x240) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OFFS (0x240) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK 0x7ff +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_POR 0x00000010 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x)) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x244) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_PHYS(x) ((x) + 0x244) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OFFS (0x244) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_POR 0x00020002 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x),m,v,HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x)) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x250) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_PHYS(x) ((x) + 0x250) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OFFS (0x250) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x254) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_PHYS(x) ((x) + 0x254) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OFFS (0x254) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x260) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_PHYS(x) ((x) + 0x260) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OFFS (0x260) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x264) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_PHYS(x) ((x) + 0x264) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OFFS (0x264) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK 0x1fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x270) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_PHYS(x) ((x) + 0x270) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OFFS (0x270) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x274) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_PHYS(x) ((x) + 0x274) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OFFS (0x274) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK 0x1fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x27c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_PHYS(x) ((x) + 0x27c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OFFS (0x27c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK 0xfffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x) ((x) + 0x284) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_PHYS(x) ((x) + 0x284) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OFFS (0x284) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK 0xfffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x) ((x) + 0x288) +#define HWIO_WBM_R0_CLK_GATE_CTRL_PHYS(x) ((x) + 0x288) +#define HWIO_WBM_R0_CLK_GATE_CTRL_OFFS (0x288) +#define HWIO_WBM_R0_CLK_GATE_CTRL_RMSK 0x3fffff +#define HWIO_WBM_R0_CLK_GATE_CTRL_POR 0x00020000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_CLK_GATE_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_CLK_GATE_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x)) +#define HWIO_WBM_R0_CLK_GATE_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_CLK_GATE_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_CLK_GATE_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x),m,v,HWIO_WBM_R0_CLK_GATE_CTRL_IN(x)) +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE1_BMSK 0x3c0000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE1_SHFT 18 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_BMSK 0x20000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_SHFT 17 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_BMSK 0x10000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_SHFT 16 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_BMSK 0xffff +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x28c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x28c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OFFS (0x28c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x290) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x290) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OFFS (0x290) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x) ((x) + 0x294) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_PHYS(x) ((x) + 0x294) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OFFS (0x294) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x298) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x298) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OFFS (0x298) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x) ((x) + 0x29c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_PHYS(x) ((x) + 0x29c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OFFS (0x29c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x2a8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x2a8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OFFS (0x2a8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x2ac) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x2ac) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OFFS (0x2ac) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x2bc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x2bc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x2bc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x2c0) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x2c0) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x2c0) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x2c4) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x2c4) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0x2c4) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x2c8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x2c8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x2c8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x2cc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x2cc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x2cc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x2d0) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x2d0) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x2d0) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x2d4) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x2d4) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x2d4) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x2d8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x2d8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x2d8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x2dc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x2dc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_OFFS (0x2dc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x2fc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x2fc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x2fc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x300) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x300) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_OFFS (0x300) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x304) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x304) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OFFS (0x304) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x308) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x308) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OFFS (0x308) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x) ((x) + 0x30c) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_PHYS(x) ((x) + 0x30c) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OFFS (0x30c) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x310) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x310) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OFFS (0x310) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x) ((x) + 0x314) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_PHYS(x) ((x) + 0x314) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OFFS (0x314) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x320) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x320) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OFFS (0x320) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x324) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x324) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OFFS (0x324) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x334) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x334) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x334) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x338) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x338) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x338) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x33c) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x33c) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0x33c) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x340) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x340) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x340) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x344) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x344) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x344) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x348) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x348) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x348) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x34c) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x34c) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x34c) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x350) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x350) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x350) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x354) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x354) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_OFFS (0x354) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x374) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x374) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x374) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x378) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x378) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_OFFS (0x378) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x37c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x37c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OFFS (0x37c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x380) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x380) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OFFS (0x380) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x) ((x) + 0x384) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_PHYS(x) ((x) + 0x384) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OFFS (0x384) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x388) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x388) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OFFS (0x388) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x) ((x) + 0x38c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_PHYS(x) ((x) + 0x38c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OFFS (0x38c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x398) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x398) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OFFS (0x398) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x39c) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x39c) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OFFS (0x39c) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x3ac) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x3ac) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x3ac) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x3b0) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x3b0) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x3b0) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x3b4) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x3b4) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0x3b4) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3b8) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3b8) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3b8) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x3bc) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x3bc) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x3bc) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x3c0) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x3c0) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x3c0) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x3c4) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x3c4) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x3c4) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x3c8) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x3c8) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x3c8) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x3cc) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x3cc) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OFFS (0x3cc) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x3ec) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x3ec) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x3ec) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x3f0) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x3f0) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_OFFS (0x3f0) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x4e4) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x4e4) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OFFS (0x4e4) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x4e8) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x4e8) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OFFS (0x4e8) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x) ((x) + 0x4ec) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_PHYS(x) ((x) + 0x4ec) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OFFS (0x4ec) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x4f0) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x4f0) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OFFS (0x4f0) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x) ((x) + 0x4f4) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_PHYS(x) ((x) + 0x4f4) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OFFS (0x4f4) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x500) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x500) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OFFS (0x500) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x504) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x504) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OFFS (0x504) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x514) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x514) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x514) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x518) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x518) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x518) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x51c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x51c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0x51c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x520) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x520) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x520) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x524) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x524) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x524) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x528) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x528) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x528) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x52c) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x52c) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x52c) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x530) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x530) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x530) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x534) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x534) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OFFS (0x534) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x554) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x554) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x554) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x558) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x558) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_OFFS (0x558) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x55c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x55c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OFFS (0x55c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x560) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x560) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OFFS (0x560) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x) ((x) + 0x564) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_PHYS(x) ((x) + 0x564) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OFFS (0x564) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x568) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x568) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OFFS (0x568) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x) ((x) + 0x56c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_PHYS(x) ((x) + 0x56c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OFFS (0x56c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x578) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x578) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OFFS (0x578) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x57c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x57c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OFFS (0x57c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x58c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x58c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x58c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x590) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x590) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x590) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x594) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x594) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0x594) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x598) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x598) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x598) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x59c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x59c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x59c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x5a0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x5a0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x5a0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x5a4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x5a4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x5a4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x5a8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x5a8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x5a8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x5ac) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x5ac) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_OFFS (0x5ac) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x5cc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x5cc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x5cc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x5d0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x5d0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_OFFS (0x5d0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0x994) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0x994) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OFFS (0x994) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0x998) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0x998) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OFFS (0x998) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x) ((x) + 0x99c) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_PHYS(x) ((x) + 0x99c) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OFFS (0x99c) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x) ((x) + 0x9a0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_PHYS(x) ((x) + 0x9a0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OFFS (0x9a0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x) ((x) + 0x9a4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_PHYS(x) ((x) + 0x9a4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OFFS (0x9a4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x9a8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x9a8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OFFS (0x9a8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x9ac) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x9ac) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OFFS (0x9ac) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x9b8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x9b8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OFFS (0x9b8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x9bc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x9bc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OFFS (0x9bc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x9c0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x9c0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0x9c0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x9dc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x9dc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OFFS (0x9dc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x9e0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x9e0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OFFS (0x9e0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x) ((x) + 0x9e4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_PHYS(x) ((x) + 0x9e4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OFFS (0x9e4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x9e8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x9e8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0x9e8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x9ec) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x9ec) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_OFFS (0x9ec) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x9f0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x9f0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_OFFS (0x9f0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_ADDR(x) ((x) + 0x9f4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_PHYS(x) ((x) + 0x9f4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_OFFS (0x9f4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa04) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa04) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xa04) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x) ((x) + 0xa08) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_PHYS(x) ((x) + 0xa08) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_OFFS (0xa08) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xa0c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0xa0c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OFFS (0xa0c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0xa10) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0xa10) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OFFS (0xa10) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x) ((x) + 0xa14) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_PHYS(x) ((x) + 0xa14) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OFFS (0xa14) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) ((x) + 0xa18) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) ((x) + 0xa18) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OFFS (0xa18) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x) ((x) + 0xa1c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_PHYS(x) ((x) + 0xa1c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OFFS (0xa1c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xa20) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xa20) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OFFS (0xa20) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xa24) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xa24) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OFFS (0xa24) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xa30) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xa30) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OFFS (0xa30) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xa34) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xa34) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OFFS (0xa34) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xa38) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xa38) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0xa38) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa54) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa54) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OFFS (0xa54) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa58) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa58) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OFFS (0xa58) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x) ((x) + 0xa5c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_PHYS(x) ((x) + 0xa5c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_OFFS (0xa5c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xa60) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xa60) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0xa60) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xa64) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xa64) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_OFFS (0xa64) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xa68) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xa68) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_OFFS (0xa68) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_ADDR(x) ((x) + 0xa6c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_PHYS(x) ((x) + 0xa6c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_OFFS (0xa6c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa7c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa7c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xa7c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x) ((x) + 0xa80) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_PHYS(x) ((x) + 0xa80) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_OFFS (0xa80) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xa84) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0xa84) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OFFS (0xa84) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0xa88) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0xa88) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OFFS (0xa88) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x) ((x) + 0xa8c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_PHYS(x) ((x) + 0xa8c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OFFS (0xa8c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x) ((x) + 0xa90) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_PHYS(x) ((x) + 0xa90) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OFFS (0xa90) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x) ((x) + 0xa94) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_PHYS(x) ((x) + 0xa94) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OFFS (0xa94) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xa98) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xa98) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OFFS (0xa98) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xa9c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xa9c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OFFS (0xa9c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xaa8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xaa8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OFFS (0xaa8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xaac) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xaac) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OFFS (0xaac) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xab0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xab0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0xab0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xacc) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xacc) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OFFS (0xacc) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xad0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xad0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OFFS (0xad0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x) ((x) + 0xad4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_PHYS(x) ((x) + 0xad4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OFFS (0xad4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xad8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xad8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0xad8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xadc) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xadc) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_OFFS (0xadc) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xae0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xae0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_OFFS (0xae0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x) ((x) + 0xae4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_PHYS(x) ((x) + 0xae4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_OFFS (0xae4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xaf4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xaf4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xaf4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x) ((x) + 0xaf8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_PHYS(x) ((x) + 0xaf8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_OFFS (0xaf8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xafc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0xafc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OFFS (0xafc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0xb00) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0xb00) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OFFS (0xb00) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x) ((x) + 0xb04) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_PHYS(x) ((x) + 0xb04) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OFFS (0xb04) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x) ((x) + 0xb08) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_PHYS(x) ((x) + 0xb08) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OFFS (0xb08) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x) ((x) + 0xb0c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_PHYS(x) ((x) + 0xb0c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OFFS (0xb0c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xb10) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xb10) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OFFS (0xb10) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xb14) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xb14) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OFFS (0xb14) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xb20) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xb20) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OFFS (0xb20) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xb24) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xb24) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OFFS (0xb24) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xb28) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xb28) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0xb28) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xb44) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xb44) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OFFS (0xb44) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xb48) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xb48) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OFFS (0xb48) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x) ((x) + 0xb4c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_PHYS(x) ((x) + 0xb4c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OFFS (0xb4c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xb50) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xb50) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0xb50) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xb54) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xb54) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_OFFS (0xb54) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xb58) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xb58) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_OFFS (0xb58) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_ADDR(x) ((x) + 0xb5c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_PHYS(x) ((x) + 0xb5c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_OFFS (0xb5c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xb6c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xb6c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xb6c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_ADDR(x) ((x) + 0xb70) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_PHYS(x) ((x) + 0xb70) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_OFFS (0xb70) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xb74) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0xb74) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OFFS (0xb74) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0xb78) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0xb78) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OFFS (0xb78) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x) ((x) + 0xb7c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_PHYS(x) ((x) + 0xb7c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OFFS (0xb7c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x) ((x) + 0xb80) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_PHYS(x) ((x) + 0xb80) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OFFS (0xb80) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x) ((x) + 0xb84) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_PHYS(x) ((x) + 0xb84) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OFFS (0xb84) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xb88) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xb88) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OFFS (0xb88) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xb8c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xb8c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OFFS (0xb8c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xb98) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xb98) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OFFS (0xb98) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xb9c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xb9c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OFFS (0xb9c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xba0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xba0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0xba0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xbbc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xbbc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_OFFS (0xbbc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xbc0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xbc0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_OFFS (0xbc0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x) ((x) + 0xbc4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_PHYS(x) ((x) + 0xbc4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_OFFS (0xbc4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xbc8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xbc8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0xbc8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xbcc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xbcc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_OFFS (0xbcc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xbd0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xbd0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_OFFS (0xbd0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_ADDR(x) ((x) + 0xbd4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_PHYS(x) ((x) + 0xbd4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_OFFS (0xbd4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xbe4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xbe4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xbe4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_ADDR(x) ((x) + 0xbe8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_PHYS(x) ((x) + 0xbe8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_OFFS (0xbe8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xd3c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0xd3c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OFFS (0xd3c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0xd40) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0xd40) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OFFS (0xd40) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x) ((x) + 0xd44) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_PHYS(x) ((x) + 0xd44) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OFFS (0xd44) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x) ((x) + 0xd48) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_PHYS(x) ((x) + 0xd48) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OFFS (0xd48) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0xd4c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_PHYS(x) ((x) + 0xd4c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OFFS (0xd4c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xd50) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xd50) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OFFS (0xd50) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xd54) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xd54) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OFFS (0xd54) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xd58) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xd58) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OFFS (0xd58) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xd5c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xd5c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OFFS (0xd5c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xd60) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xd60) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OFFS (0xd60) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xd64) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xd64) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OFFS (0xd64) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xd68) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xd68) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0xd68) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xd6c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xd6c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xd6c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xd70) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xd70) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xd70) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xd74) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xd74) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OFFS (0xd74) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xd78) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xd78) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xd78) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xd7c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xd7c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xd7c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xd80) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xd80) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xd80) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xd84) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xd84) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0xd84) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xd88) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xd88) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xd88) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x) ((x) + 0xd8c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_PHYS(x) ((x) + 0xd8c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_OFFS (0xd8c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xd90) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xd90) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OFFS (0xd90) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xd94) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xd94) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OFFS (0xd94) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x) ((x) + 0xd98) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_PHYS(x) ((x) + 0xd98) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OFFS (0xd98) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xd9c) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xd9c) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OFFS (0xd9c) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x) ((x) + 0xda0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_PHYS(x) ((x) + 0xda0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OFFS (0xda0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xda4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xda4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OFFS (0xda4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xda8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xda8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OFFS (0xda8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xdb4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xdb4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xdb4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xdb8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xdb8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xdb8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xdbc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xdbc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xdbc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xdd8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xdd8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xdd8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xddc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xddc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xddc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xde0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xde0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OFFS (0xde0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xde4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xde4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xde4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xde8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xde8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xde8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xdec) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xdec) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xdec) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xdf0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xdf0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_OFFS (0xdf0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xe00) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xe00) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xe00) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xe04) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xe04) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_OFFS (0xe04) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe08) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xe08) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OFFS (0xe08) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xe0c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xe0c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OFFS (0xe0c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x) ((x) + 0xe10) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_PHYS(x) ((x) + 0xe10) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OFFS (0xe10) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xe14) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xe14) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OFFS (0xe14) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x) ((x) + 0xe18) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_PHYS(x) ((x) + 0xe18) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OFFS (0xe18) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xe1c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xe1c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OFFS (0xe1c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xe20) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xe20) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OFFS (0xe20) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xe2c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xe2c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xe2c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xe30) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xe30) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xe30) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xe34) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xe34) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xe34) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xe50) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xe50) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xe50) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xe54) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xe54) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xe54) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xe58) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xe58) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OFFS (0xe58) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xe5c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xe5c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xe5c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xe60) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xe60) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xe60) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xe64) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xe64) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xe64) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xe68) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xe68) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_OFFS (0xe68) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xe78) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xe78) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xe78) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xe7c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xe7c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_OFFS (0xe7c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe80) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xe80) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OFFS (0xe80) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xe84) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xe84) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OFFS (0xe84) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x) ((x) + 0xe88) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_PHYS(x) ((x) + 0xe88) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OFFS (0xe88) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xe8c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xe8c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OFFS (0xe8c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x) ((x) + 0xe90) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_PHYS(x) ((x) + 0xe90) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OFFS (0xe90) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xe94) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xe94) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OFFS (0xe94) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xe98) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xe98) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OFFS (0xe98) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xea4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xea4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xea4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xea8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xea8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xea8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xeac) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xeac) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xeac) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xec8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xec8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xec8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xecc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xecc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xecc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xed0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xed0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OFFS (0xed0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xed4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xed4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xed4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xed8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xed8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xed8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xedc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xedc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xedc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xee0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xee0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_OFFS (0xee0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xef0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xef0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xef0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xef4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xef4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_OFFS (0xef4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xef8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xef8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OFFS (0xef8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xefc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xefc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OFFS (0xefc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x) ((x) + 0xf00) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_PHYS(x) ((x) + 0xf00) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OFFS (0xf00) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xf04) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xf04) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OFFS (0xf04) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x) ((x) + 0xf08) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_PHYS(x) ((x) + 0xf08) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OFFS (0xf08) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xf0c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xf0c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OFFS (0xf0c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xf10) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xf10) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OFFS (0xf10) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xf1c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xf1c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xf1c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xf20) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xf20) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xf20) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xf24) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xf24) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xf24) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xf40) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xf40) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xf40) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xf44) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xf44) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xf44) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xf48) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xf48) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OFFS (0xf48) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xf4c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xf4c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xf4c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xf50) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xf50) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xf50) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xf54) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xf54) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xf54) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xf58) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xf58) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_OFFS (0xf58) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xf68) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xf68) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xf68) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xf6c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xf6c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_OFFS (0xf6c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xf70) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xf70) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OFFS (0xf70) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xf74) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xf74) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OFFS (0xf74) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x) ((x) + 0xf78) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_PHYS(x) ((x) + 0xf78) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OFFS (0xf78) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xf7c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xf7c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OFFS (0xf7c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x) ((x) + 0xf80) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_PHYS(x) ((x) + 0xf80) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OFFS (0xf80) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xf84) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xf84) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OFFS (0xf84) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xf88) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xf88) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OFFS (0xf88) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xf94) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xf94) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xf94) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xf98) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xf98) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xf98) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xf9c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xf9c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xf9c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xfb8) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xfb8) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xfb8) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xfbc) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xfbc) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xfbc) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xfc0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xfc0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OFFS (0xfc0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xfc4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xfc4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xfc4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xfc8) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xfc8) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xfc8) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xfcc) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xfcc) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xfcc) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xfd0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xfd0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_OFFS (0xfd0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xfe0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xfe0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xfe0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xfe4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xfe4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_OFFS (0xfe4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xfe8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xfe8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_OFFS (0xfe8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xfec) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xfec) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_OFFS (0xfec) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x) ((x) + 0xff0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_PHYS(x) ((x) + 0xff0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_OFFS (0xff0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xff4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xff4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_OFFS (0xff4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x) ((x) + 0xff8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_PHYS(x) ((x) + 0xff8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_OFFS (0xff8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xffc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xffc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_OFFS (0xffc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x1000) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x1000) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_OFFS (0x1000) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x100c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x100c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x100c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x1010) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x1010) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x1010) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x1014) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x1014) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x1014) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1030) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1030) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x1030) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1034) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1034) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x1034) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x1038) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x1038) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_OFFS (0x1038) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x103c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x103c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x103c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x1040) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x1040) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x1040) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x1044) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x1044) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x1044) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x1048) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x1048) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_OFFS (0x1048) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1058) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1058) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x1058) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x105c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x105c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_OFFS (0x105c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x1060) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x1060) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_OFFS (0x1060) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x1064) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x1064) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_OFFS (0x1064) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x) ((x) + 0x1068) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_PHYS(x) ((x) + 0x1068) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_OFFS (0x1068) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x106c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x106c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_OFFS (0x106c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x) ((x) + 0x1070) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_PHYS(x) ((x) + 0x1070) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_OFFS (0x1070) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x1074) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x1074) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_OFFS (0x1074) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x1078) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x1078) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_OFFS (0x1078) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x1084) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x1084) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x1084) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x1088) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x1088) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x1088) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x108c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x108c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x108c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x10a8) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x10a8) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x10a8) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x10ac) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x10ac) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x10ac) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x10b0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x10b0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_OFFS (0x10b0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x10b4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x10b4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x10b4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x10b8) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x10b8) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x10b8) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x10bc) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x10bc) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x10bc) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x10c0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x10c0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_OFFS (0x10c0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x10d0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x10d0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x10d0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x10d4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x10d4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_OFFS (0x10d4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x10d8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x10d8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_OFFS (0x10d8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x10dc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x10dc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_OFFS (0x10dc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x) ((x) + 0x10e0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_PHYS(x) ((x) + 0x10e0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_OFFS (0x10e0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x10e4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x10e4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_OFFS (0x10e4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x) ((x) + 0x10e8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_PHYS(x) ((x) + 0x10e8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_OFFS (0x10e8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x10ec) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x10ec) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_OFFS (0x10ec) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x10f0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x10f0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_OFFS (0x10f0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x10fc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x10fc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x10fc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x1100) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x1100) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x1100) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x1104) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x1104) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x1104) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1120) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1120) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x1120) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1124) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1124) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x1124) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x1128) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x1128) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_OFFS (0x1128) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x112c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x112c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x112c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x1130) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x1130) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x1130) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x1134) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x1134) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x1134) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x1138) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x1138) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_OFFS (0x1138) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1148) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1148) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x1148) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x114c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x114c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_OFFS (0x114c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x1150) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x1150) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_OFFS (0x1150) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x1154) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x1154) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_OFFS (0x1154) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ADDR(x) ((x) + 0x1158) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_PHYS(x) ((x) + 0x1158) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_OFFS (0x1158) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x115c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x115c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_OFFS (0x115c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADDR(x) ((x) + 0x1160) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_PHYS(x) ((x) + 0x1160) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_OFFS (0x1160) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x1164) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x1164) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_OFFS (0x1164) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x1168) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x1168) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_OFFS (0x1168) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x1174) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x1174) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x1174) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x1178) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x1178) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x1178) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x117c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x117c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x117c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1198) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1198) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x1198) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x119c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x119c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x119c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x11a0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x11a0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_OFFS (0x11a0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x11a4) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x11a4) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x11a4) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x11a8) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x11a8) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x11a8) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x11ac) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x11ac) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x11ac) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x11b0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x11b0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_OFFS (0x11b0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x11c0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x11c0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x11c0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x11c4) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x11c4) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_OFFS (0x11c4) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_ADDR(x) ((x) + 0x11c8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_PHYS(x) ((x) + 0x11c8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_OFFS (0x11c8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_ADDR(x) ((x) + 0x11cc) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_PHYS(x) ((x) + 0x11cc) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_OFFS (0x11cc) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ADDR(x) ((x) + 0x11d0) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_PHYS(x) ((x) + 0x11d0) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_OFFS (0x11d0) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_ADDR(x) ((x) + 0x11d4) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_PHYS(x) ((x) + 0x11d4) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_OFFS (0x11d4) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_ADDR(x) ((x) + 0x11d8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_PHYS(x) ((x) + 0x11d8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_OFFS (0x11d8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x11e4) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x11e4) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_OFFS (0x11e4) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x11e8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x11e8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_OFFS (0x11e8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x11f8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x11f8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x11f8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x11fc) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x11fc) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x11fc) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x1200) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x1200) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_OFFS (0x1200) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x1204) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x1204) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x1204) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x1208) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x1208) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x1208) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x120c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x120c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x120c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1210) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1210) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_OFFS (0x1210) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1214) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1214) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_OFFS (0x1214) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_ADDR(x) ((x) + 0x1218) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_PHYS(x) ((x) + 0x1218) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_OFFS (0x1218) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1238) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1238) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_OFFS (0x1238) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_ADDR(x) ((x) + 0x123c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_PHYS(x) ((x) + 0x123c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_OFFS (0x123c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x1240) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x1240) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_OFFS (0x1240) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x1244) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x1244) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OFFS (0x1244) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x1248) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x1248) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OFFS (0x1248) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x124c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x124c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OFFS (0x124c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x1250) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x1250) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OFFS (0x1250) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_ADDR(x) ((x) + 0x1254) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_PHYS(x) ((x) + 0x1254) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_OFFS (0x1254) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_ADDR(x) ((x) + 0x1258) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_PHYS(x) ((x) + 0x1258) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_OFFS (0x1258) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_ADDR(x) ((x) + 0x125c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_PHYS(x) ((x) + 0x125c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_OFFS (0x125c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ADDR(x) ((x) + 0x1260) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_PHYS(x) ((x) + 0x1260) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_OFFS (0x1260) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_ADDR(x) ((x) + 0x1264) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_PHYS(x) ((x) + 0x1264) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_OFFS (0x1264) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_ADDR(x) ((x) + 0x1268) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_PHYS(x) ((x) + 0x1268) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_OFFS (0x1268) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1274) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1274) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_OFFS (0x1274) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x1278) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x1278) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_OFFS (0x1278) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x1288) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x1288) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x1288) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x128c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x128c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x128c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x1290) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x1290) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_OFFS (0x1290) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x1294) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x1294) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x1294) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x1298) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x1298) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x1298) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x129c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x129c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x129c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x12a0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x12a0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_OFFS (0x12a0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x12a4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x12a4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_OFFS (0x12a4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_ADDR(x) ((x) + 0x12a8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_PHYS(x) ((x) + 0x12a8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_OFFS (0x12a8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x12c8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x12c8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_OFFS (0x12c8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_ADDR(x) ((x) + 0x12cc) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_PHYS(x) ((x) + 0x12cc) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_OFFS (0x12cc) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x12d0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x12d0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_OFFS (0x12d0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x12d4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x12d4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OFFS (0x12d4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x12d8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x12d8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OFFS (0x12d8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x12dc) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x12dc) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OFFS (0x12dc) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x12e0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x12e0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OFFS (0x12e0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_ADDR(x) ((x) + 0x12e4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_PHYS(x) ((x) + 0x12e4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_OFFS (0x12e4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_ADDR(x) ((x) + 0x12e8) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_PHYS(x) ((x) + 0x12e8) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_OFFS (0x12e8) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_ADDR(x) ((x) + 0x12ec) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_PHYS(x) ((x) + 0x12ec) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_OFFS (0x12ec) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ADDR(x) ((x) + 0x12f0) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_PHYS(x) ((x) + 0x12f0) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_OFFS (0x12f0) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_ADDR(x) ((x) + 0x12f4) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_PHYS(x) ((x) + 0x12f4) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_OFFS (0x12f4) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADDR(x) ((x) + 0x12f8) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_PHYS(x) ((x) + 0x12f8) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_OFFS (0x12f8) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x12fc) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x12fc) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_OFFS (0x12fc) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x1300) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x1300) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_OFFS (0x1300) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x130c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x130c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_OFFS (0x130c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x1310) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x1310) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_OFFS (0x1310) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x1314) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x1314) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_OFFS (0x1314) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1330) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1330) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_OFFS (0x1330) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1334) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1334) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_OFFS (0x1334) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_ADDR(x) ((x) + 0x1338) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_PHYS(x) ((x) + 0x1338) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_OFFS (0x1338) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x133c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x133c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_OFFS (0x133c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x1340) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x1340) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_OFFS (0x1340) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x1344) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x1344) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_OFFS (0x1344) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_ADDR(x) ((x) + 0x1348) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_PHYS(x) ((x) + 0x1348) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_OFFS (0x1348) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1358) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1358) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_OFFS (0x1358) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_ADDR(x) ((x) + 0x135c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_PHYS(x) ((x) + 0x135c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_OFFS (0x135c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x1360) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x1360) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_OFFS (0x1360) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x1364) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x1364) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OFFS (0x1364) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x1368) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x1368) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OFFS (0x1368) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x136c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x136c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_OFFS (0x136c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x1370) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x1370) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_OFFS (0x1370) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_ADDR(x) ((x) + 0x1374) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_PHYS(x) ((x) + 0x1374) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_OFFS (0x1374) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_ADDR(x) ((x) + 0x1378) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_PHYS(x) ((x) + 0x1378) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_OFFS (0x1378) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_ADDR(x) ((x) + 0x137c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_PHYS(x) ((x) + 0x137c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_OFFS (0x137c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ADDR(x) ((x) + 0x1380) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_PHYS(x) ((x) + 0x1380) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_OFFS (0x1380) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_ADDR(x) ((x) + 0x1384) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_PHYS(x) ((x) + 0x1384) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_OFFS (0x1384) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADDR(x) ((x) + 0x1388) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_PHYS(x) ((x) + 0x1388) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_OFFS (0x1388) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x138c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x138c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_OFFS (0x138c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x1390) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x1390) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_OFFS (0x1390) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x139c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x139c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_OFFS (0x139c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x13a0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x13a0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_OFFS (0x13a0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x13a4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x13a4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_OFFS (0x13a4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x13c0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x13c0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_OFFS (0x13c0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x13c4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x13c4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_OFFS (0x13c4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_ADDR(x) ((x) + 0x13c8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_PHYS(x) ((x) + 0x13c8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_OFFS (0x13c8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x13cc) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x13cc) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_OFFS (0x13cc) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x13d0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x13d0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_OFFS (0x13d0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x13d4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x13d4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_OFFS (0x13d4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_ADDR(x) ((x) + 0x13d8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_PHYS(x) ((x) + 0x13d8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_OFFS (0x13d8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x13e8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x13e8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_OFFS (0x13e8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_ADDR(x) ((x) + 0x13ec) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_PHYS(x) ((x) + 0x13ec) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_OFFS (0x13ec) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x13f0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x13f0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_OFFS (0x13f0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x13f4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x13f4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OFFS (0x13f4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x13f8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x13f8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OFFS (0x13f8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x13fc) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x13fc) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_OFFS (0x13fc) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x1400) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x1400) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_OFFS (0x1400) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_ADDR(x) ((x) + 0x1404) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_PHYS(x) ((x) + 0x1404) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_OFFS (0x1404) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x2000) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x2000) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_OFFS (0x2000) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x)) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x2004) +#define HWIO_WBM_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x2004) +#define HWIO_WBM_R1_TESTBUS_CTRL_OFFS (0x2004) +#define HWIO_WBM_R1_TESTBUS_CTRL_RMSK 0x3f +#define HWIO_WBM_R1_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_WBM_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_WBM_R1_TESTBUS_CTRL_IN(x) \ + in_dword(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x)) +#define HWIO_WBM_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_WBM_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_WBM_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_WBM_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_BMSK 0x3f +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_SHFT 0 + +#define HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x) ((x) + 0x2008) +#define HWIO_WBM_R1_TESTBUS_LOWER_PHYS(x) ((x) + 0x2008) +#define HWIO_WBM_R1_TESTBUS_LOWER_OFFS (0x2008) +#define HWIO_WBM_R1_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_LOWER_POR 0x00000000 +#define HWIO_WBM_R1_TESTBUS_LOWER_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_LOWER_ATTR 0x1 +#define HWIO_WBM_R1_TESTBUS_LOWER_IN(x) \ + in_dword(HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x)) +#define HWIO_WBM_R1_TESTBUS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), m) +#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_SHFT 0 + +#define HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x) ((x) + 0x200c) +#define HWIO_WBM_R1_TESTBUS_HIGHER_PHYS(x) ((x) + 0x200c) +#define HWIO_WBM_R1_TESTBUS_HIGHER_OFFS (0x200c) +#define HWIO_WBM_R1_TESTBUS_HIGHER_RMSK 0xff +#define HWIO_WBM_R1_TESTBUS_HIGHER_POR 0x00000000 +#define HWIO_WBM_R1_TESTBUS_HIGHER_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_HIGHER_ATTR 0x1 +#define HWIO_WBM_R1_TESTBUS_HIGHER_IN(x) \ + in_dword(HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x)) +#define HWIO_WBM_R1_TESTBUS_HIGHER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), m) +#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_BMSK 0xff +#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_SHFT 0 + +#define HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x) ((x) + 0x2010) +#define HWIO_WBM_R1_SM_STATES_IX_0_PHYS(x) ((x) + 0x2010) +#define HWIO_WBM_R1_SM_STATES_IX_0_OFFS (0x2010) +#define HWIO_WBM_R1_SM_STATES_IX_0_RMSK 0x7fffffff +#define HWIO_WBM_R1_SM_STATES_IX_0_POR 0x00000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_SM_STATES_IX_0_ATTR 0x1 +#define HWIO_WBM_R1_SM_STATES_IX_0_IN(x) \ + in_dword(HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x)) +#define HWIO_WBM_R1_SM_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), m) +#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_BMSK 0x60000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_SHFT 29 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_BMSK 0x18000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_SHFT 27 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_BMSK 0x6000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_SHFT 25 +#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_BMSK 0x1800000 +#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_SHFT 23 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_BMSK 0x600000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_SHFT 21 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_BMSK 0x180000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_SHFT 19 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_BMSK 0x60000 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_SHFT 17 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_BMSK 0x18000 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_SHFT 15 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_BMSK 0x7000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_SHFT 12 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_BMSK 0xc00 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_SHFT 10 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_BMSK 0x380 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_SHFT 7 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_BMSK 0x60 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_SHFT 5 +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_BMSK 0x1c +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_SHFT 2 +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_BMSK 0x3 +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_SHFT 0 + +#define HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x) ((x) + 0x2014) +#define HWIO_WBM_R1_SM_STATES_IX_1_PHYS(x) ((x) + 0x2014) +#define HWIO_WBM_R1_SM_STATES_IX_1_OFFS (0x2014) +#define HWIO_WBM_R1_SM_STATES_IX_1_RMSK 0xffffffff +#define HWIO_WBM_R1_SM_STATES_IX_1_POR 0x00000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_SM_STATES_IX_1_ATTR 0x1 +#define HWIO_WBM_R1_SM_STATES_IX_1_IN(x) \ + in_dword(HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x)) +#define HWIO_WBM_R1_SM_STATES_IX_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), m) +#define HWIO_WBM_R1_SM_STATES_IX_1_SW4_BUFFER_P_STATE_BMSK 0xc0000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_SW4_BUFFER_P_STATE_SHFT 30 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_DIST_NULL_PTR_BMSK 0x20000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_DIST_NULL_PTR_SHFT 29 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_DIST_NULL_PTR_BMSK 0x10000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_DIST_NULL_PTR_SHFT 28 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_BMSK 0xe000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_SHFT 25 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_BMSK 0x1c00000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_SHFT 22 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_BMSK 0x380000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_SHFT 19 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_BMSK 0x70000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_SHFT 16 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_C_STATE_BMSK 0xe000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_C_STATE_SHFT 13 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_P_STATE_BMSK 0x1c00 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_P_STATE_SHFT 10 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_C_STATE_BMSK 0x380 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_C_STATE_SHFT 7 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_P_STATE_BMSK 0x70 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_P_STATE_SHFT 4 +#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_BMSK 0xc +#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_SHFT 2 +#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_BMSK 0x3 +#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_SHFT 0 + +#define HWIO_WBM_R1_SM_STATES_IX_2_ADDR(x) ((x) + 0x2018) +#define HWIO_WBM_R1_SM_STATES_IX_2_PHYS(x) ((x) + 0x2018) +#define HWIO_WBM_R1_SM_STATES_IX_2_OFFS (0x2018) +#define HWIO_WBM_R1_SM_STATES_IX_2_RMSK 0x3ff +#define HWIO_WBM_R1_SM_STATES_IX_2_POR 0x00000000 +#define HWIO_WBM_R1_SM_STATES_IX_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_SM_STATES_IX_2_ATTR 0x1 +#define HWIO_WBM_R1_SM_STATES_IX_2_IN(x) \ + in_dword(HWIO_WBM_R1_SM_STATES_IX_2_ADDR(x)) +#define HWIO_WBM_R1_SM_STATES_IX_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_SM_STATES_IX_2_ADDR(x), m) +#define HWIO_WBM_R1_SM_STATES_IX_2_MLO_OUT2_REL_P_STATE_BMSK 0x300 +#define HWIO_WBM_R1_SM_STATES_IX_2_MLO_OUT2_REL_P_STATE_SHFT 8 +#define HWIO_WBM_R1_SM_STATES_IX_2_MLO_OUT1_REL_P_STATE_BMSK 0xc0 +#define HWIO_WBM_R1_SM_STATES_IX_2_MLO_OUT1_REL_P_STATE_SHFT 6 +#define HWIO_WBM_R1_SM_STATES_IX_2_ERROR_RELEASE_P_STATE_BMSK 0x30 +#define HWIO_WBM_R1_SM_STATES_IX_2_ERROR_RELEASE_P_STATE_SHFT 4 +#define HWIO_WBM_R1_SM_STATES_IX_2_SW6_BUFFER_P_STATE_BMSK 0xc +#define HWIO_WBM_R1_SM_STATES_IX_2_SW6_BUFFER_P_STATE_SHFT 2 +#define HWIO_WBM_R1_SM_STATES_IX_2_SW5_BUFFER_P_STATE_BMSK 0x3 +#define HWIO_WBM_R1_SM_STATES_IX_2_SW5_BUFFER_P_STATE_SHFT 0 + +#define HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x) ((x) + 0x201c) +#define HWIO_WBM_R1_EVENTMASK_IX_0_PHYS(x) ((x) + 0x201c) +#define HWIO_WBM_R1_EVENTMASK_IX_0_OFFS (0x201c) +#define HWIO_WBM_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_POR 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_ATTR 0x3 +#define HWIO_WBM_R1_EVENTMASK_IX_0_IN(x) \ + in_dword(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), m) +#define HWIO_WBM_R1_EVENTMASK_IX_0_OUT(x, v) \ + out_dword(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x),v) +#define HWIO_WBM_R1_EVENTMASK_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_WBM_R1_EVENTMASK_IX_0_IN(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_SHFT 0 + +#define HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x) ((x) + 0x2020) +#define HWIO_WBM_R1_EVENTMASK_IX_1_PHYS(x) ((x) + 0x2020) +#define HWIO_WBM_R1_EVENTMASK_IX_1_OFFS (0x2020) +#define HWIO_WBM_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_POR 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_ATTR 0x3 +#define HWIO_WBM_R1_EVENTMASK_IX_1_IN(x) \ + in_dword(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), m) +#define HWIO_WBM_R1_EVENTMASK_IX_1_OUT(x, v) \ + out_dword(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x),v) +#define HWIO_WBM_R1_EVENTMASK_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_WBM_R1_EVENTMASK_IX_1_IN(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_SHFT 0 + +#define HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x) ((x) + 0x2024) +#define HWIO_WBM_R1_EVENTMASK_IX_2_PHYS(x) ((x) + 0x2024) +#define HWIO_WBM_R1_EVENTMASK_IX_2_OFFS (0x2024) +#define HWIO_WBM_R1_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_POR 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_ATTR 0x3 +#define HWIO_WBM_R1_EVENTMASK_IX_2_IN(x) \ + in_dword(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), m) +#define HWIO_WBM_R1_EVENTMASK_IX_2_OUT(x, v) \ + out_dword(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x),v) +#define HWIO_WBM_R1_EVENTMASK_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x),m,v,HWIO_WBM_R1_EVENTMASK_IX_2_IN(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_SHFT 0 + +#define HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x) ((x) + 0x2028) +#define HWIO_WBM_R1_EVENTMASK_IX_3_PHYS(x) ((x) + 0x2028) +#define HWIO_WBM_R1_EVENTMASK_IX_3_OFFS (0x2028) +#define HWIO_WBM_R1_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_POR 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_ATTR 0x3 +#define HWIO_WBM_R1_EVENTMASK_IX_3_IN(x) \ + in_dword(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_3_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), m) +#define HWIO_WBM_R1_EVENTMASK_IX_3_OUT(x, v) \ + out_dword(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x),v) +#define HWIO_WBM_R1_EVENTMASK_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x),m,v,HWIO_WBM_R1_EVENTMASK_IX_3_IN(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_SHFT 0 + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x202c) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x202c) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x202c) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 17 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 2 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 1 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0 + +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x) ((x) + 0x3000) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_PHYS(x) ((x) + 0x3000) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OFFS (0x3000) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x) ((x) + 0x3004) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_PHYS(x) ((x) + 0x3004) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OFFS (0x3004) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x) ((x) + 0x3008) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_PHYS(x) ((x) + 0x3008) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OFFS (0x3008) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x) ((x) + 0x300c) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_PHYS(x) ((x) + 0x300c) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OFFS (0x300c) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_PHYS(x) ((x) + 0x3010) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OFFS (0x3010) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x) ((x) + 0x3014) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_PHYS(x) ((x) + 0x3014) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OFFS (0x3014) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3028) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_PHYS(x) ((x) + 0x3028) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OFFS (0x3028) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x) ((x) + 0x302c) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_PHYS(x) ((x) + 0x302c) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OFFS (0x302c) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x) ((x) + 0x3030) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_PHYS(x) ((x) + 0x3030) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OFFS (0x3030) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x) ((x) + 0x3034) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_PHYS(x) ((x) + 0x3034) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OFFS (0x3034) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x) ((x) + 0x3078) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_PHYS(x) ((x) + 0x3078) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OFFS (0x3078) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x) ((x) + 0x307c) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_PHYS(x) ((x) + 0x307c) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OFFS (0x307c) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x) ((x) + 0x3080) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_PHYS(x) ((x) + 0x3080) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OFFS (0x3080) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x) ((x) + 0x3084) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_PHYS(x) ((x) + 0x3084) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OFFS (0x3084) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x) ((x) + 0x3088) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_PHYS(x) ((x) + 0x3088) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OFFS (0x3088) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x) ((x) + 0x308c) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_PHYS(x) ((x) + 0x308c) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OFFS (0x308c) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x) ((x) + 0x3090) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_PHYS(x) ((x) + 0x3090) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OFFS (0x3090) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x) ((x) + 0x3094) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_PHYS(x) ((x) + 0x3094) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OFFS (0x3094) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x) ((x) + 0x3098) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_PHYS(x) ((x) + 0x3098) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OFFS (0x3098) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x) ((x) + 0x309c) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_PHYS(x) ((x) + 0x309c) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OFFS (0x309c) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x30b8) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_PHYS(x) ((x) + 0x30b8) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OFFS (0x30b8) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x) ((x) + 0x30bc) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_PHYS(x) ((x) + 0x30bc) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OFFS (0x30bc) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x) ((x) + 0x30c0) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_PHYS(x) ((x) + 0x30c0) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OFFS (0x30c0) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x) ((x) + 0x30c4) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_PHYS(x) ((x) + 0x30c4) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OFFS (0x30c4) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x30c8) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_PHYS(x) ((x) + 0x30c8) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OFFS (0x30c8) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x) ((x) + 0x30cc) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_PHYS(x) ((x) + 0x30cc) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OFFS (0x30cc) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x30d0) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_PHYS(x) ((x) + 0x30d0) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OFFS (0x30d0) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x) ((x) + 0x30d4) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_PHYS(x) ((x) + 0x30d4) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OFFS (0x30d4) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x) ((x) + 0x30d8) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_PHYS(x) ((x) + 0x30d8) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OFFS (0x30d8) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x) ((x) + 0x30dc) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_PHYS(x) ((x) + 0x30dc) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OFFS (0x30dc) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x) ((x) + 0x30e0) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_PHYS(x) ((x) + 0x30e0) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OFFS (0x30e0) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x) ((x) + 0x30e4) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_PHYS(x) ((x) + 0x30e4) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OFFS (0x30e4) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x) ((x) + 0x30e8) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_PHYS(x) ((x) + 0x30e8) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_OFFS (0x30e8) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x) ((x) + 0x30ec) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_PHYS(x) ((x) + 0x30ec) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_OFFS (0x30ec) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x) ((x) + 0x30f0) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_PHYS(x) ((x) + 0x30f0) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_OFFS (0x30f0) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x) ((x) + 0x30f4) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_PHYS(x) ((x) + 0x30f4) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_OFFS (0x30f4) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x) ((x) + 0x30f8) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_PHYS(x) ((x) + 0x30f8) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_OFFS (0x30f8) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x) ((x) + 0x30fc) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_PHYS(x) ((x) + 0x30fc) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_OFFS (0x30fc) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_ADDR(x) ((x) + 0x3100) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_PHYS(x) ((x) + 0x3100) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_OFFS (0x3100) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_ADDR(x) ((x) + 0x3104) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_PHYS(x) ((x) + 0x3104) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_OFFS (0x3104) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_ADDR(x) ((x) + 0x3108) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_PHYS(x) ((x) + 0x3108) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_OFFS (0x3108) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_ADDR(x) ((x) + 0x310c) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_PHYS(x) ((x) + 0x310c) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_OFFS (0x310c) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_ADDR(x) ((x) + 0x3110) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_PHYS(x) ((x) + 0x3110) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_OFFS (0x3110) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_ADDR(x) ((x) + 0x3114) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_PHYS(x) ((x) + 0x3114) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_OFFS (0x3114) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_ADDR(x) ((x) + 0x3118) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_PHYS(x) ((x) + 0x3118) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_OFFS (0x3118) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_ADDR(x) ((x) + 0x311c) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_PHYS(x) ((x) + 0x311c) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_OFFS (0x311c) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_ADDR(x) ((x) + 0x3120) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_PHYS(x) ((x) + 0x3120) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_OFFS (0x3120) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_ADDR(x) ((x) + 0x3124) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_PHYS(x) ((x) + 0x3124) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_OFFS (0x3124) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_TAIL_PTR_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: REO_REG + *--------------------------------------------------------------------------*/ + +#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) +#define REO_REG_REG_BASE_SIZE 0x4000 +#define REO_REG_REG_BASE_USED 0x30ac +#define REO_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00038000) +#define REO_REG_REG_BASE_OFFS 0x00038000 + +#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) +#define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) ((x) + 0x0) +#define HWIO_REO_R0_GENERAL_ENABLE_OFFS (0x0) +#define HWIO_REO_R0_GENERAL_ENABLE_RMSK 0xffffffff +#define HWIO_REO_R0_GENERAL_ENABLE_POR 0x00000100 +#define HWIO_REO_R0_GENERAL_ENABLE_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GENERAL_ENABLE_ATTR 0x3 +#define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \ + in_dword(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x)) +#define HWIO_REO_R0_GENERAL_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), m) +#define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, v) \ + out_dword(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x),v) +#define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x),m,v,HWIO_REO_R0_GENERAL_ENABLE_IN(x)) +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_BMSK 0x80000000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_SHFT 31 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_BMSK 0x40000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_SHFT 30 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_BMSK 0x20000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_SHFT 29 +#define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_BMSK 0x10000000 +#define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_SHFT 28 +#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x8000000 +#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 27 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW8_RING_ENABLE_BMSK 0x4000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW8_RING_ENABLE_SHFT 26 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW7_RING_ENABLE_BMSK 0x2000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW7_RING_ENABLE_SHFT 25 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO3_RING_ENABLE_BMSK 0x1000000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO3_RING_ENABLE_SHFT 24 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO2_RING_ENABLE_BMSK 0x800000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO2_RING_ENABLE_SHFT 23 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK 0x400000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT 22 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK 0x200000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT 21 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK 0x100000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT 20 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x80000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 19 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW0_RING_ENABLE_BMSK 0x40000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW0_RING_ENABLE_SHFT 18 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK 0x20000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT 17 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK 0x10000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT 16 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK 0x8000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT 15 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK 0x4000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT 14 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK 0x2000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT 13 +#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x1000 +#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 12 +#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK 0xe00 +#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT 9 +#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK 0x100 +#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT 8 +#define HWIO_REO_R0_GENERAL_ENABLE_BACKUP_1_BMSK 0xe0 +#define HWIO_REO_R0_GENERAL_ENABLE_BACKUP_1_SHFT 5 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2PPE_RING_ENABLE_BMSK 0x10 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2PPE_RING_ENABLE_SHFT 4 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x8 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 3 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x4 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 2 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT 1 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK 0x1 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x4) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x) ((x) + 0x4) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OFFS (0x4) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_POR 0x76543210 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x8) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x) ((x) + 0x8) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OFFS (0x8) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_POR 0x6666b668 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x) ((x) + 0xc) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OFFS (0xc) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x) ((x) + 0x10) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OFFS (0x10) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x) ((x) + 0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x) ((x) + 0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS (0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR 0x76543210 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x) ((x) + 0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x) ((x) + 0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS (0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x6666b668 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x) ((x) + 0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x) ((x) + 0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS (0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x) ((x) + 0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x) ((x) + 0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS (0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x) ((x) + 0x24) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x) ((x) + 0x24) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OFFS (0x24) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_POR 0x76543210 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x) ((x) + 0x28) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x) ((x) + 0x28) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OFFS (0x28) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_POR 0x6666b668 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x) ((x) + 0x2c) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x) ((x) + 0x2c) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OFFS (0x2c) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x) ((x) + 0x30) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x) ((x) + 0x30) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OFFS (0x30) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT 0 + +#define HWIO_REO_R0_TIMESTAMP_ADDR(x) ((x) + 0x34) +#define HWIO_REO_R0_TIMESTAMP_PHYS(x) ((x) + 0x34) +#define HWIO_REO_R0_TIMESTAMP_OFFS (0x34) +#define HWIO_REO_R0_TIMESTAMP_RMSK 0xffffffff +#define HWIO_REO_R0_TIMESTAMP_POR 0x00000000 +#define HWIO_REO_R0_TIMESTAMP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_TIMESTAMP_ATTR 0x3 +#define HWIO_REO_R0_TIMESTAMP_IN(x) \ + in_dword(HWIO_REO_R0_TIMESTAMP_ADDR(x)) +#define HWIO_REO_R0_TIMESTAMP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_TIMESTAMP_ADDR(x), m) +#define HWIO_REO_R0_TIMESTAMP_OUT(x, v) \ + out_dword(HWIO_REO_R0_TIMESTAMP_ADDR(x),v) +#define HWIO_REO_R0_TIMESTAMP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x),m,v,HWIO_REO_R0_TIMESTAMP_IN(x)) +#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK 0xffffffff +#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x38) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x) ((x) + 0x38) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OFFS (0x38) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x3c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x) ((x) + 0x3c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OFFS (0x3c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x) ((x) + 0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x) ((x) + 0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS (0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x) ((x) + 0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x) ((x) + 0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS (0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT 0 + +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x) ((x) + 0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x) ((x) + 0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS (0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK 0x1ffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR 0x00000000 +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR 0x3 +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x) \ + in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v) \ + out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK 0x1ffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT 0 + +#define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x) ((x) + 0x4c) +#define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x) ((x) + 0x4c) +#define HWIO_REO_R0_IDLE_REQ_CTRL_OFFS (0x4c) +#define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK 0x3 +#define HWIO_REO_R0_IDLE_REQ_CTRL_POR 0x00000003 +#define HWIO_REO_R0_IDLE_REQ_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_IDLE_REQ_CTRL_ATTR 0x3 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x) \ + in_dword(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x)) +#define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), m) +#define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x),v) +#define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x),m,v,HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)) +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK 0x2 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT 1 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK 0x1 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT 0 + +#define HWIO_REO_R0_LAST_SN_0_ADDR(x) ((x) + 0x50) +#define HWIO_REO_R0_LAST_SN_0_PHYS(x) ((x) + 0x50) +#define HWIO_REO_R0_LAST_SN_0_OFFS (0x50) +#define HWIO_REO_R0_LAST_SN_0_RMSK 0xffffff +#define HWIO_REO_R0_LAST_SN_0_POR 0x00001001 +#define HWIO_REO_R0_LAST_SN_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_LAST_SN_0_ATTR 0x1 +#define HWIO_REO_R0_LAST_SN_0_IN(x) \ + in_dword(HWIO_REO_R0_LAST_SN_0_ADDR(x)) +#define HWIO_REO_R0_LAST_SN_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_LAST_SN_0_ADDR(x), m) +#define HWIO_REO_R0_LAST_SN_0_Q1_BMSK 0xfff000 +#define HWIO_REO_R0_LAST_SN_0_Q1_SHFT 12 +#define HWIO_REO_R0_LAST_SN_0_Q0_BMSK 0xfff +#define HWIO_REO_R0_LAST_SN_0_Q0_SHFT 0 + +#define HWIO_REO_R0_LAST_SN_1_ADDR(x) ((x) + 0x54) +#define HWIO_REO_R0_LAST_SN_1_PHYS(x) ((x) + 0x54) +#define HWIO_REO_R0_LAST_SN_1_OFFS (0x54) +#define HWIO_REO_R0_LAST_SN_1_RMSK 0xffffff +#define HWIO_REO_R0_LAST_SN_1_POR 0x00001001 +#define HWIO_REO_R0_LAST_SN_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_LAST_SN_1_ATTR 0x1 +#define HWIO_REO_R0_LAST_SN_1_IN(x) \ + in_dword(HWIO_REO_R0_LAST_SN_1_ADDR(x)) +#define HWIO_REO_R0_LAST_SN_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_LAST_SN_1_ADDR(x), m) +#define HWIO_REO_R0_LAST_SN_1_Q3_BMSK 0xfff000 +#define HWIO_REO_R0_LAST_SN_1_Q3_SHFT 12 +#define HWIO_REO_R0_LAST_SN_1_Q2_BMSK 0xfff +#define HWIO_REO_R0_LAST_SN_1_Q2_SHFT 0 + +#define HWIO_REO_R0_LAST_SN_2_ADDR(x) ((x) + 0x58) +#define HWIO_REO_R0_LAST_SN_2_PHYS(x) ((x) + 0x58) +#define HWIO_REO_R0_LAST_SN_2_OFFS (0x58) +#define HWIO_REO_R0_LAST_SN_2_RMSK 0xffffff +#define HWIO_REO_R0_LAST_SN_2_POR 0x00001001 +#define HWIO_REO_R0_LAST_SN_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_LAST_SN_2_ATTR 0x1 +#define HWIO_REO_R0_LAST_SN_2_IN(x) \ + in_dword(HWIO_REO_R0_LAST_SN_2_ADDR(x)) +#define HWIO_REO_R0_LAST_SN_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_LAST_SN_2_ADDR(x), m) +#define HWIO_REO_R0_LAST_SN_2_Q5_BMSK 0xfff000 +#define HWIO_REO_R0_LAST_SN_2_Q5_SHFT 12 +#define HWIO_REO_R0_LAST_SN_2_Q4_BMSK 0xfff +#define HWIO_REO_R0_LAST_SN_2_Q4_SHFT 0 + +#define HWIO_REO_R0_LAST_SN_3_ADDR(x) ((x) + 0x5c) +#define HWIO_REO_R0_LAST_SN_3_PHYS(x) ((x) + 0x5c) +#define HWIO_REO_R0_LAST_SN_3_OFFS (0x5c) +#define HWIO_REO_R0_LAST_SN_3_RMSK 0xffffff +#define HWIO_REO_R0_LAST_SN_3_POR 0x00001001 +#define HWIO_REO_R0_LAST_SN_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_LAST_SN_3_ATTR 0x1 +#define HWIO_REO_R0_LAST_SN_3_IN(x) \ + in_dword(HWIO_REO_R0_LAST_SN_3_ADDR(x)) +#define HWIO_REO_R0_LAST_SN_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_LAST_SN_3_ADDR(x), m) +#define HWIO_REO_R0_LAST_SN_3_Q7_BMSK 0xfff000 +#define HWIO_REO_R0_LAST_SN_3_Q7_SHFT 12 +#define HWIO_REO_R0_LAST_SN_3_Q6_BMSK 0xfff +#define HWIO_REO_R0_LAST_SN_3_Q6_SHFT 0 + +#define HWIO_REO_R0_LAST_SN_4_ADDR(x) ((x) + 0x60) +#define HWIO_REO_R0_LAST_SN_4_PHYS(x) ((x) + 0x60) +#define HWIO_REO_R0_LAST_SN_4_OFFS (0x60) +#define HWIO_REO_R0_LAST_SN_4_RMSK 0xfff +#define HWIO_REO_R0_LAST_SN_4_POR 0x00000001 +#define HWIO_REO_R0_LAST_SN_4_POR_RMSK 0xffffffff +#define HWIO_REO_R0_LAST_SN_4_ATTR 0x1 +#define HWIO_REO_R0_LAST_SN_4_IN(x) \ + in_dword(HWIO_REO_R0_LAST_SN_4_ADDR(x)) +#define HWIO_REO_R0_LAST_SN_4_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_LAST_SN_4_ADDR(x), m) +#define HWIO_REO_R0_LAST_SN_4_Q8_BMSK 0xfff +#define HWIO_REO_R0_LAST_SN_4_Q8_SHFT 0 + +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_ADDR(x) ((x) + 0x64) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_PHYS(x) ((x) + 0x64) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_OFFS (0x64) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_RMSK 0x1 +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_POR 0x00000000 +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_ATTR 0x3 +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_IN(x) \ + in_dword(HWIO_REO_R0_MODULE_STRESS_CONTROL_ADDR(x)) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MODULE_STRESS_CONTROL_ADDR(x), m) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_OUT(x, v) \ + out_dword(HWIO_REO_R0_MODULE_STRESS_CONTROL_ADDR(x),v) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MODULE_STRESS_CONTROL_ADDR(x),m,v,HWIO_REO_R0_MODULE_STRESS_CONTROL_IN(x)) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_HANG_AND_CLEAR_ON_RESET_BMSK 0x1 +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_HANG_AND_CLEAR_ON_RESET_SHFT 0 + +#define HWIO_REO_R0_PN_IN_DEST_ADDR(x) ((x) + 0x68) +#define HWIO_REO_R0_PN_IN_DEST_PHYS(x) ((x) + 0x68) +#define HWIO_REO_R0_PN_IN_DEST_OFFS (0x68) +#define HWIO_REO_R0_PN_IN_DEST_RMSK 0x1 +#define HWIO_REO_R0_PN_IN_DEST_POR 0x00000000 +#define HWIO_REO_R0_PN_IN_DEST_POR_RMSK 0xffffffff +#define HWIO_REO_R0_PN_IN_DEST_ATTR 0x3 +#define HWIO_REO_R0_PN_IN_DEST_IN(x) \ + in_dword(HWIO_REO_R0_PN_IN_DEST_ADDR(x)) +#define HWIO_REO_R0_PN_IN_DEST_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_PN_IN_DEST_ADDR(x), m) +#define HWIO_REO_R0_PN_IN_DEST_OUT(x, v) \ + out_dword(HWIO_REO_R0_PN_IN_DEST_ADDR(x),v) +#define HWIO_REO_R0_PN_IN_DEST_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_PN_IN_DEST_ADDR(x),m,v,HWIO_REO_R0_PN_IN_DEST_IN(x)) +#define HWIO_REO_R0_PN_IN_DEST_PN_FIELD_EN_IN_DEST_BMSK 0x1 +#define HWIO_REO_R0_PN_IN_DEST_PN_FIELD_EN_IN_DEST_SHFT 0 + +#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x6c) +#define HWIO_REO_R0_SW_COOKIE_CFG0_PHYS(x) ((x) + 0x6c) +#define HWIO_REO_R0_SW_COOKIE_CFG0_OFFS (0x6c) +#define HWIO_REO_R0_SW_COOKIE_CFG0_RMSK 0xffffffff +#define HWIO_REO_R0_SW_COOKIE_CFG0_POR 0x00000000 +#define HWIO_REO_R0_SW_COOKIE_CFG0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW_COOKIE_CFG0_ATTR 0x3 +#define HWIO_REO_R0_SW_COOKIE_CFG0_IN(x) \ + in_dword(HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x)) +#define HWIO_REO_R0_SW_COOKIE_CFG0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x), m) +#define HWIO_REO_R0_SW_COOKIE_CFG0_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x),v) +#define HWIO_REO_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_REO_R0_SW_COOKIE_CFG0_IN(x)) +#define HWIO_REO_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT 0 + +#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x70) +#define HWIO_REO_R0_SW_COOKIE_CFG1_PHYS(x) ((x) + 0x70) +#define HWIO_REO_R0_SW_COOKIE_CFG1_OFFS (0x70) +#define HWIO_REO_R0_SW_COOKIE_CFG1_RMSK 0x1fffff +#define HWIO_REO_R0_SW_COOKIE_CFG1_POR 0x00111700 +#define HWIO_REO_R0_SW_COOKIE_CFG1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW_COOKIE_CFG1_ATTR 0x3 +#define HWIO_REO_R0_SW_COOKIE_CFG1_IN(x) \ + in_dword(HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x)) +#define HWIO_REO_R0_SW_COOKIE_CFG1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x), m) +#define HWIO_REO_R0_SW_COOKIE_CFG1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x),v) +#define HWIO_REO_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_REO_R0_SW_COOKIE_CFG1_IN(x)) +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x) ((x) + 0x74) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_PHYS(x) ((x) + 0x74) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_OFFS (0x74) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_POR 0x00000000 +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ATTR 0x3 +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x)) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x), m) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_OUT(x, v) \ + out_dword(HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x),v) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x),m,v,HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_IN(x)) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_VALUE_SHFT 0 + +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x) ((x) + 0x78) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_PHYS(x) ((x) + 0x78) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_OFFS (0x78) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_POR 0x00000000 +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ATTR 0x3 +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x)) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x), m) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_OUT(x, v) \ + out_dword(HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x),v) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x),m,v,HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_IN(x)) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_VALUE_SHFT 0 + +#define HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x) ((x) + 0x7c) +#define HWIO_REO_R0_QDESC_ADDR_READ_PHYS(x) ((x) + 0x7c) +#define HWIO_REO_R0_QDESC_ADDR_READ_OFFS (0x7c) +#define HWIO_REO_R0_QDESC_ADDR_READ_RMSK 0x1ff +#define HWIO_REO_R0_QDESC_ADDR_READ_POR 0x00000000 +#define HWIO_REO_R0_QDESC_ADDR_READ_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_READ_ATTR 0x3 +#define HWIO_REO_R0_QDESC_ADDR_READ_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x)) +#define HWIO_REO_R0_QDESC_ADDR_READ_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x), m) +#define HWIO_REO_R0_QDESC_ADDR_READ_OUT(x, v) \ + out_dword(HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x),v) +#define HWIO_REO_R0_QDESC_ADDR_READ_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x),m,v,HWIO_REO_R0_QDESC_ADDR_READ_IN(x)) +#define HWIO_REO_R0_QDESC_ADDR_READ_GXI_SWAP_BMSK 0x100 +#define HWIO_REO_R0_QDESC_ADDR_READ_GXI_SWAP_SHFT 8 +#define HWIO_REO_R0_QDESC_ADDR_READ_LUT_FEATURE_ENABLE_BMSK 0x80 +#define HWIO_REO_R0_QDESC_ADDR_READ_LUT_FEATURE_ENABLE_SHFT 7 +#define HWIO_REO_R0_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY_BMSK 0x40 +#define HWIO_REO_R0_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY_SHFT 6 +#define HWIO_REO_R0_QDESC_ADDR_READ_INDEX_BMSK 0x3f +#define HWIO_REO_R0_QDESC_ADDR_READ_INDEX_SHFT 0 + +#define HWIO_REO_R0_QDESC_ADDR_LOWER_ADDR(x) ((x) + 0x80) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_PHYS(x) ((x) + 0x80) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_OFFS (0x80) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_LOWER_POR 0x00000000 +#define HWIO_REO_R0_QDESC_ADDR_LOWER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_LOWER_ATTR 0x1 +#define HWIO_REO_R0_QDESC_ADDR_LOWER_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_ADDR_LOWER_ADDR(x)) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_ADDR_LOWER_ADDR(x), m) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_QDESC_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_LOWER_QDESC_ADDR_SHFT 0 + +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_ADDR(x) ((x) + 0x84) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_PHYS(x) ((x) + 0x84) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_OFFS (0x84) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_RMSK 0x3ffffff +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_POR 0x00000000 +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_ATTR 0x1 +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_ADDR_HIGHER_ADDR(x)) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_ADDR_HIGHER_ADDR(x), m) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_Q_INDEX_BMSK 0x3ffff00 +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_Q_INDEX_SHFT 8 +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_QDESC_ADDR_BMSK 0xff +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_QDESC_ADDR_SHFT 0 + +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x) ((x) + 0x88) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_PHYS(x) ((x) + 0x88) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_OFFS (0x88) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_RMSK 0x1fff +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_POR 0x00000000 +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ATTR 0x3 +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x)) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x), m) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x),v) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x),m,v,HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_IN(x)) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_MAX_SUPPORTED_BMSK 0x1fff +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_MAX_SUPPORTED_SHFT 0 + +#define HWIO_REO_R0_RX_STATS_CMD_ADDR(x) ((x) + 0x8c) +#define HWIO_REO_R0_RX_STATS_CMD_PHYS(x) ((x) + 0x8c) +#define HWIO_REO_R0_RX_STATS_CMD_OFFS (0x8c) +#define HWIO_REO_R0_RX_STATS_CMD_RMSK 0xff +#define HWIO_REO_R0_RX_STATS_CMD_POR 0x00000000 +#define HWIO_REO_R0_RX_STATS_CMD_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_CMD_ATTR 0x3 +#define HWIO_REO_R0_RX_STATS_CMD_IN(x) \ + in_dword(HWIO_REO_R0_RX_STATS_CMD_ADDR(x)) +#define HWIO_REO_R0_RX_STATS_CMD_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RX_STATS_CMD_ADDR(x), m) +#define HWIO_REO_R0_RX_STATS_CMD_OUT(x, v) \ + out_dword(HWIO_REO_R0_RX_STATS_CMD_ADDR(x),v) +#define HWIO_REO_R0_RX_STATS_CMD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RX_STATS_CMD_ADDR(x),m,v,HWIO_REO_R0_RX_STATS_CMD_IN(x)) +#define HWIO_REO_R0_RX_STATS_CMD_CLEAR_ALL_VDEV_ID_RX_STATS_BMSK 0x80 +#define HWIO_REO_R0_RX_STATS_CMD_CLEAR_ALL_VDEV_ID_RX_STATS_SHFT 7 +#define HWIO_REO_R0_RX_STATS_CMD_CLEAR_SINGLE_VDEV_RX_STATS_BMSK 0x40 +#define HWIO_REO_R0_RX_STATS_CMD_CLEAR_SINGLE_VDEV_RX_STATS_SHFT 6 +#define HWIO_REO_R0_RX_STATS_CMD_VDEV_ID_BMSK 0x3f +#define HWIO_REO_R0_RX_STATS_CMD_VDEV_ID_SHFT 0 + +#define HWIO_REO_R0_RX_STATS_LOWER_ADDR(x) ((x) + 0x90) +#define HWIO_REO_R0_RX_STATS_LOWER_PHYS(x) ((x) + 0x90) +#define HWIO_REO_R0_RX_STATS_LOWER_OFFS (0x90) +#define HWIO_REO_R0_RX_STATS_LOWER_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_LOWER_POR 0x00000000 +#define HWIO_REO_R0_RX_STATS_LOWER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_LOWER_ATTR 0x1 +#define HWIO_REO_R0_RX_STATS_LOWER_IN(x) \ + in_dword(HWIO_REO_R0_RX_STATS_LOWER_ADDR(x)) +#define HWIO_REO_R0_RX_STATS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RX_STATS_LOWER_ADDR(x), m) +#define HWIO_REO_R0_RX_STATS_LOWER_MSDU_BYTE_COUNT_BMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_LOWER_MSDU_BYTE_COUNT_SHFT 0 + +#define HWIO_REO_R0_RX_STATS_HIGHER_ADDR(x) ((x) + 0x94) +#define HWIO_REO_R0_RX_STATS_HIGHER_PHYS(x) ((x) + 0x94) +#define HWIO_REO_R0_RX_STATS_HIGHER_OFFS (0x94) +#define HWIO_REO_R0_RX_STATS_HIGHER_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_HIGHER_POR 0x00000000 +#define HWIO_REO_R0_RX_STATS_HIGHER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_HIGHER_ATTR 0x1 +#define HWIO_REO_R0_RX_STATS_HIGHER_IN(x) \ + in_dword(HWIO_REO_R0_RX_STATS_HIGHER_ADDR(x)) +#define HWIO_REO_R0_RX_STATS_HIGHER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RX_STATS_HIGHER_ADDR(x), m) +#define HWIO_REO_R0_RX_STATS_HIGHER_MSDU_COUNT_BMSK 0xfffffff0 +#define HWIO_REO_R0_RX_STATS_HIGHER_MSDU_COUNT_SHFT 4 +#define HWIO_REO_R0_RX_STATS_HIGHER_MSDU_BYTE_COUNT_BMSK 0xf +#define HWIO_REO_R0_RX_STATS_HIGHER_MSDU_BYTE_COUNT_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x) ((x) + 0x98) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x) ((x) + 0x98) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OFFS (0x98) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x) ((x) + 0x9c) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x) ((x) + 0x9c) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OFFS (0x9c) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) ((x) + 0xa0) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) ((x) + 0xa0) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OFFS (0xa0) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x) ((x) + 0xa4) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x) ((x) + 0xa4) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OFFS (0xa4) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x) ((x) + 0xa8) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x) ((x) + 0xa8) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OFFS (0xa8) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xb4) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xb4) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OFFS (0xb4) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xb8) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xb8) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OFFS (0xb8) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xc8) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xc8) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xc8) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xcc) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xcc) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xcc) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xd0) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xd0) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OFFS (0xd0) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xd4) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xd4) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xd4) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xd8) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xd8) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xd8) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xdc) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xdc) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xdc) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x108) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x108) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OFFS (0x108) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_ADDR(x) ((x) + 0x10c) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_PHYS(x) ((x) + 0x10c) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_OFFS (0x10c) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_ADDR(x) ((x) + 0x110) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_PHYS(x) ((x) + 0x110) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_OFFS (0x110) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_ADDR(x) ((x) + 0x114) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_PHYS(x) ((x) + 0x114) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_OFFS (0x114) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ADDR(x) ((x) + 0x118) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_PHYS(x) ((x) + 0x118) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_OFFS (0x118) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_ADDR(x) ((x) + 0x11c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_PHYS(x) ((x) + 0x11c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_OFFS (0x11c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_ADDR(x) ((x) + 0x120) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_PHYS(x) ((x) + 0x120) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_OFFS (0x120) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x12c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x12c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_OFFS (0x12c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x130) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x130) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_OFFS (0x130) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x140) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x140) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x140) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x144) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x144) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x144) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x148) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x148) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_OFFS (0x148) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x14c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x14c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x14c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x150) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x150) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x150) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x154) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x154) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x154) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x158) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x158) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_OFFS (0x158) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x15c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x15c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_OFFS (0x15c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_ADDR(x) ((x) + 0x160) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_PHYS(x) ((x) + 0x160) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_OFFS (0x160) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x180) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x180) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_OFFS (0x180) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_ADDR(x) ((x) + 0x184) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_PHYS(x) ((x) + 0x184) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_OFFS (0x184) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x188) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x188) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_OFFS (0x188) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x18c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x18c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OFFS (0x18c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x190) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x190) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OFFS (0x190) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x194) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x194) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OFFS (0x194) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x198) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x198) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OFFS (0x198) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_ADDR(x) ((x) + 0x19c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_PHYS(x) ((x) + 0x19c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_OFFS (0x19c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_ADDR(x) ((x) + 0x1a0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_PHYS(x) ((x) + 0x1a0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_OFFS (0x1a0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_ADDR(x) ((x) + 0x1a4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_PHYS(x) ((x) + 0x1a4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_OFFS (0x1a4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ADDR(x) ((x) + 0x1a8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_PHYS(x) ((x) + 0x1a8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_OFFS (0x1a8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_ADDR(x) ((x) + 0x1ac) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_PHYS(x) ((x) + 0x1ac) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_OFFS (0x1ac) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_ADDR(x) ((x) + 0x1b0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_PHYS(x) ((x) + 0x1b0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_OFFS (0x1b0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1bc) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1bc) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_OFFS (0x1bc) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x1c0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x1c0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_OFFS (0x1c0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x1d0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x1d0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x1d0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x1d4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x1d4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x1d4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x1d8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x1d8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_OFFS (0x1d8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x1dc) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x1dc) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x1dc) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x1e0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x1e0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x1e0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x1e4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x1e4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x1e4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1e8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1e8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_OFFS (0x1e8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1ec) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1ec) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_OFFS (0x1ec) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_ADDR(x) ((x) + 0x1f0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_PHYS(x) ((x) + 0x1f0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_OFFS (0x1f0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x210) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x210) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_OFFS (0x210) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_ADDR(x) ((x) + 0x214) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_PHYS(x) ((x) + 0x214) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_OFFS (0x214) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x218) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x218) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_OFFS (0x218) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x21c) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x21c) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OFFS (0x21c) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x220) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x220) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OFFS (0x220) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x224) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x224) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OFFS (0x224) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x228) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x228) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OFFS (0x228) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_ADDR(x) ((x) + 0x22c) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_PHYS(x) ((x) + 0x22c) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_OFFS (0x22c) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0x230) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0x230) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OFFS (0x230) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0x234) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0x234) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OFFS (0x234) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) ((x) + 0x238) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) ((x) + 0x238) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OFFS (0x238) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0xff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) ((x) + 0x23c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) ((x) + 0x23c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OFFS (0x23c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x) ((x) + 0x240) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x) ((x) + 0x240) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OFFS (0x240) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x24c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x24c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OFFS (0x24c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x250) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x250) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OFFS (0x250) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x260) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x260) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x260) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x264) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x264) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x264) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x268) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x268) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OFFS (0x268) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x26c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x26c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x26c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x270) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x270) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x270) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x274) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x274) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x274) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x2a0) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x2a0) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OFFS (0x2a0) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x) ((x) + 0x2a4) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_PHYS(x) ((x) + 0x2a4) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_OFFS (0x2a4) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) ((x) + 0x2a8) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x) ((x) + 0x2a8) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OFFS (0x2a8) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x) ((x) + 0x2ac) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x) ((x) + 0x2ac) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OFFS (0x2ac) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) ((x) + 0x2b0) +#define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) ((x) + 0x2b0) +#define HWIO_REO_R0_REO_CMD_RING_ID_OFFS (0x2b0) +#define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_ID_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x) ((x) + 0x2b4) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x) ((x) + 0x2b4) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_OFFS (0x2b4) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x) ((x) + 0x2b8) +#define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x) ((x) + 0x2b8) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OFFS (0x2b8) +#define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_REO_CMD_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO_CMD_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x2c4) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x2c4) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OFFS (0x2c4) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x2c8) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x2c8) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OFFS (0x2c8) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x2d8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x2d8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x2d8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x2dc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x2dc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x2dc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x2e0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x2e0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OFFS (0x2e0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x2e4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x2e4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x2e4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x2e8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x2e8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x2e8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x2ec) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x2ec) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x2ec) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x2f0) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x2f0) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OFFS (0x2f0) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x2f4) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x2f4) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OFFS (0x2f4) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x) ((x) + 0x2f8) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x) ((x) + 0x2f8) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OFFS (0x2f8) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x318) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x318) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OFFS (0x318) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x) ((x) + 0x31c) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_PHYS(x) ((x) + 0x31c) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_OFFS (0x31c) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x320) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x) ((x) + 0x320) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OFFS (0x320) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x) ((x) + 0x324) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x) ((x) + 0x324) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OFFS (0x324) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) ((x) + 0x328) +#define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) ((x) + 0x328) +#define HWIO_REO_R0_SW2REO_RING_ID_OFFS (0x328) +#define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_ID_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x) ((x) + 0x32c) +#define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x) ((x) + 0x32c) +#define HWIO_REO_R0_SW2REO_RING_STATUS_OFFS (0x32c) +#define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x) ((x) + 0x330) +#define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x) ((x) + 0x330) +#define HWIO_REO_R0_SW2REO_RING_MISC_OFFS (0x330) +#define HWIO_REO_R0_SW2REO_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_SW2REO_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_SW2REO_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MISC_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x33c) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x33c) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OFFS (0x33c) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x340) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x340) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OFFS (0x340) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x350) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x350) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x350) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x354) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x354) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x354) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x358) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x358) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OFFS (0x358) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x35c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x35c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x35c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x360) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x360) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x360) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x364) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x364) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x364) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x368) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x368) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OFFS (0x368) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x36c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x36c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OFFS (0x36c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x) ((x) + 0x370) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x) ((x) + 0x370) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OFFS (0x370) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x390) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x390) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OFFS (0x390) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x) ((x) + 0x394) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_PHYS(x) ((x) + 0x394) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_OFFS (0x394) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_SW2REO_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_SW2REO_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x) ((x) + 0x398) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_PHYS(x) ((x) + 0x398) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OFFS (0x398) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x) ((x) + 0x39c) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_PHYS(x) ((x) + 0x39c) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OFFS (0x39c) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x) ((x) + 0x3a0) +#define HWIO_REO_R0_SW2REO1_RING_ID_PHYS(x) ((x) + 0x3a0) +#define HWIO_REO_R0_SW2REO1_RING_ID_OFFS (0x3a0) +#define HWIO_REO_R0_SW2REO1_RING_ID_RMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_ID_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x) ((x) + 0x3a4) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_PHYS(x) ((x) + 0x3a4) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_OFFS (0x3a4) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x) ((x) + 0x3a8) +#define HWIO_REO_R0_SW2REO1_RING_MISC_PHYS(x) ((x) + 0x3a8) +#define HWIO_REO_R0_SW2REO1_RING_MISC_OFFS (0x3a8) +#define HWIO_REO_R0_SW2REO1_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_SW2REO1_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_SW2REO1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MISC_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x3b4) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x3b4) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OFFS (0x3b4) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x3b8) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x3b8) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OFFS (0x3b8) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x3c8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x3c8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x3c8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x3cc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x3cc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x3cc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x3d0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x3d0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OFFS (0x3d0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3d4) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3d4) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3d4) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x3d8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x3d8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x3d8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x3dc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x3dc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x3dc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x3e0) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x3e0) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OFFS (0x3e0) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x3e4) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x3e4) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OFFS (0x3e4) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x) ((x) + 0x3e8) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_PHYS(x) ((x) + 0x3e8) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OFFS (0x3e8) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x408) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x408) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OFFS (0x408) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x) ((x) + 0x40c) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_PHYS(x) ((x) + 0x40c) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_OFFS (0x40c) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x500) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x) ((x) + 0x500) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OFFS (0x500) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x504) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x) ((x) + 0x504) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OFFS (0x504) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x508) +#define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x) ((x) + 0x508) +#define HWIO_REO_R0_REO2SW1_RING_ID_OFFS (0x508) +#define HWIO_REO_R0_REO2SW1_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW1_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) ((x) + 0x50c) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x) ((x) + 0x50c) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_OFFS (0x50c) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x510) +#define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x) ((x) + 0x510) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OFFS (0x510) +#define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW1_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x514) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x514) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OFFS (0x514) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x518) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x518) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OFFS (0x518) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x524) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x524) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OFFS (0x524) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x528) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x528) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OFFS (0x528) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x52c) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x52c) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OFFS (0x52c) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x548) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x548) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OFFS (0x548) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x54c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x54c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OFFS (0x54c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x550) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x) ((x) + 0x550) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OFFS (0x550) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x554) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x554) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_OFFS (0x554) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x558) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x558) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_OFFS (0x558) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x55c) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x55c) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_OFFS (0x55c) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x560) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_PHYS(x) ((x) + 0x560) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_OFFS (0x560) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x570) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x570) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OFFS (0x570) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x574) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_PHYS(x) ((x) + 0x574) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_OFFS (0x574) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x578) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x) ((x) + 0x578) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OFFS (0x578) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x) ((x) + 0x57c) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x) ((x) + 0x57c) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OFFS (0x57c) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x) ((x) + 0x580) +#define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x) ((x) + 0x580) +#define HWIO_REO_R0_REO2SW2_RING_ID_OFFS (0x580) +#define HWIO_REO_R0_REO2SW2_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW2_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x) ((x) + 0x584) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x) ((x) + 0x584) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_OFFS (0x584) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x) ((x) + 0x588) +#define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x) ((x) + 0x588) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OFFS (0x588) +#define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW2_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x58c) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x58c) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OFFS (0x58c) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x590) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x590) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OFFS (0x590) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x59c) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x59c) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OFFS (0x59c) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x5a0) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x5a0) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OFFS (0x5a0) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x5a4) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x5a4) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OFFS (0x5a4) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x5c0) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x5c0) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OFFS (0x5c0) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x5c4) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x5c4) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OFFS (0x5c4) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x) ((x) + 0x5c8) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x) ((x) + 0x5c8) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OFFS (0x5c8) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x5cc) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x5cc) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_OFFS (0x5cc) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x5d0) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x5d0) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_OFFS (0x5d0) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x5d4) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x5d4) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_OFFS (0x5d4) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x) ((x) + 0x5d8) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_PHYS(x) ((x) + 0x5d8) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_OFFS (0x5d8) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x5e8) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x5e8) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OFFS (0x5e8) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x) ((x) + 0x5ec) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_PHYS(x) ((x) + 0x5ec) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_OFFS (0x5ec) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x) ((x) + 0x5f0) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x) ((x) + 0x5f0) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OFFS (0x5f0) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x) ((x) + 0x5f4) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x) ((x) + 0x5f4) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OFFS (0x5f4) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x) ((x) + 0x5f8) +#define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x) ((x) + 0x5f8) +#define HWIO_REO_R0_REO2SW3_RING_ID_OFFS (0x5f8) +#define HWIO_REO_R0_REO2SW3_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW3_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x) ((x) + 0x5fc) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x) ((x) + 0x5fc) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_OFFS (0x5fc) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x) ((x) + 0x600) +#define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x) ((x) + 0x600) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OFFS (0x600) +#define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW3_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW3_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x604) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x604) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OFFS (0x604) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x608) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x608) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OFFS (0x608) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x614) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x614) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OFFS (0x614) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x618) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x618) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OFFS (0x618) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x61c) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x61c) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OFFS (0x61c) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x638) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x638) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OFFS (0x638) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x63c) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x63c) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OFFS (0x63c) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x) ((x) + 0x640) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x) ((x) + 0x640) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OFFS (0x640) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x644) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x644) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_OFFS (0x644) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x648) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x648) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_OFFS (0x648) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x64c) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x64c) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_OFFS (0x64c) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x) ((x) + 0x650) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_PHYS(x) ((x) + 0x650) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_OFFS (0x650) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x660) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x660) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OFFS (0x660) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x) ((x) + 0x664) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_PHYS(x) ((x) + 0x664) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_OFFS (0x664) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x) ((x) + 0x668) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x) ((x) + 0x668) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OFFS (0x668) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x) ((x) + 0x66c) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x) ((x) + 0x66c) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OFFS (0x66c) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x) ((x) + 0x670) +#define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x) ((x) + 0x670) +#define HWIO_REO_R0_REO2SW4_RING_ID_OFFS (0x670) +#define HWIO_REO_R0_REO2SW4_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW4_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x) ((x) + 0x674) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x) ((x) + 0x674) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_OFFS (0x674) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x) ((x) + 0x678) +#define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x) ((x) + 0x678) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OFFS (0x678) +#define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW4_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW4_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x67c) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x67c) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OFFS (0x67c) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x680) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x680) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OFFS (0x680) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x68c) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x68c) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OFFS (0x68c) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x690) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x690) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OFFS (0x690) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x694) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x694) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OFFS (0x694) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x6b0) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x6b0) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OFFS (0x6b0) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x6b4) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x6b4) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OFFS (0x6b4) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x) ((x) + 0x6b8) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x) ((x) + 0x6b8) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OFFS (0x6b8) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x6bc) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x6bc) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_OFFS (0x6bc) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x6c0) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x6c0) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_OFFS (0x6c0) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x6c4) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x6c4) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_OFFS (0x6c4) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x) ((x) + 0x6c8) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_PHYS(x) ((x) + 0x6c8) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_OFFS (0x6c8) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x6d8) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x6d8) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OFFS (0x6d8) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x) ((x) + 0x6dc) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_PHYS(x) ((x) + 0x6dc) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_OFFS (0x6dc) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x) ((x) + 0x6e0) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_PHYS(x) ((x) + 0x6e0) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OFFS (0x6e0) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x) ((x) + 0x6e4) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_PHYS(x) ((x) + 0x6e4) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OFFS (0x6e4) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x) ((x) + 0x6e8) +#define HWIO_REO_R0_REO2SW5_RING_ID_PHYS(x) ((x) + 0x6e8) +#define HWIO_REO_R0_REO2SW5_RING_ID_OFFS (0x6e8) +#define HWIO_REO_R0_REO2SW5_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW5_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW5_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x) ((x) + 0x6ec) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_PHYS(x) ((x) + 0x6ec) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_OFFS (0x6ec) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x) ((x) + 0x6f0) +#define HWIO_REO_R0_REO2SW5_RING_MISC_PHYS(x) ((x) + 0x6f0) +#define HWIO_REO_R0_REO2SW5_RING_MISC_OFFS (0x6f0) +#define HWIO_REO_R0_REO2SW5_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW5_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW5_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW5_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW5_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW5_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW5_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW5_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW5_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW5_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW5_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6f4) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6f4) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OFFS (0x6f4) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x6f8) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x6f8) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OFFS (0x6f8) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x704) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x704) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OFFS (0x704) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x708) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x708) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_OFFS (0x708) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x70c) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x70c) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OFFS (0x70c) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x728) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x728) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OFFS (0x728) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x72c) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x72c) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OFFS (0x72c) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x) ((x) + 0x730) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_PHYS(x) ((x) + 0x730) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OFFS (0x730) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x734) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x734) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_OFFS (0x734) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x738) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x738) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_OFFS (0x738) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x73c) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x73c) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_OFFS (0x73c) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x) ((x) + 0x740) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_PHYS(x) ((x) + 0x740) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_OFFS (0x740) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x750) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x750) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OFFS (0x750) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x) ((x) + 0x754) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_PHYS(x) ((x) + 0x754) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_OFFS (0x754) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x) ((x) + 0x758) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_PHYS(x) ((x) + 0x758) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OFFS (0x758) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x) ((x) + 0x75c) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_PHYS(x) ((x) + 0x75c) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OFFS (0x75c) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x) ((x) + 0x760) +#define HWIO_REO_R0_REO2SW6_RING_ID_PHYS(x) ((x) + 0x760) +#define HWIO_REO_R0_REO2SW6_RING_ID_OFFS (0x760) +#define HWIO_REO_R0_REO2SW6_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW6_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW6_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x) ((x) + 0x764) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_PHYS(x) ((x) + 0x764) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_OFFS (0x764) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x) ((x) + 0x768) +#define HWIO_REO_R0_REO2SW6_RING_MISC_PHYS(x) ((x) + 0x768) +#define HWIO_REO_R0_REO2SW6_RING_MISC_OFFS (0x768) +#define HWIO_REO_R0_REO2SW6_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW6_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW6_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW6_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW6_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW6_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW6_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW6_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW6_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW6_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW6_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x76c) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x76c) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OFFS (0x76c) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x770) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x770) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OFFS (0x770) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x77c) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x77c) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OFFS (0x77c) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x780) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x780) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_OFFS (0x780) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x784) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x784) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OFFS (0x784) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x7a0) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x7a0) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OFFS (0x7a0) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x7a4) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x7a4) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OFFS (0x7a4) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x) ((x) + 0x7a8) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_PHYS(x) ((x) + 0x7a8) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OFFS (0x7a8) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x7ac) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x7ac) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_OFFS (0x7ac) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x7b0) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x7b0) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_OFFS (0x7b0) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x7b4) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x7b4) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_OFFS (0x7b4) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x) ((x) + 0x7b8) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_PHYS(x) ((x) + 0x7b8) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_OFFS (0x7b8) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x7c8) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x7c8) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OFFS (0x7c8) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x) ((x) + 0x7cc) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_PHYS(x) ((x) + 0x7cc) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_OFFS (0x7cc) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0x8c0) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_PHYS(x) ((x) + 0x8c0) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_OFFS (0x8c0) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x) ((x) + 0x8c4) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_PHYS(x) ((x) + 0x8c4) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_OFFS (0x8c4) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x) ((x) + 0x8c8) +#define HWIO_REO_R0_REO2SW0_RING_ID_PHYS(x) ((x) + 0x8c8) +#define HWIO_REO_R0_REO2SW0_RING_ID_OFFS (0x8c8) +#define HWIO_REO_R0_REO2SW0_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW0_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW0_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_STATUS_ADDR(x) ((x) + 0x8cc) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_PHYS(x) ((x) + 0x8cc) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_OFFS (0x8cc) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW0_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW0_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW0_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x) ((x) + 0x8d0) +#define HWIO_REO_R0_REO2SW0_RING_MISC_PHYS(x) ((x) + 0x8d0) +#define HWIO_REO_R0_REO2SW0_RING_MISC_OFFS (0x8d0) +#define HWIO_REO_R0_REO2SW0_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW0_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW0_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW0_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW0_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW0_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW0_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW0_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW0_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x8d4) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x8d4) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_OFFS (0x8d4) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x8d8) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x8d8) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_OFFS (0x8d8) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x8e4) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x8e4) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_OFFS (0x8e4) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x8e8) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x8e8) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_OFFS (0x8e8) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x8ec) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x8ec) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_OFFS (0x8ec) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x908) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x908) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_OFFS (0x908) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x90c) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x90c) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_OFFS (0x90c) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x) ((x) + 0x910) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_PHYS(x) ((x) + 0x910) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_OFFS (0x910) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x914) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x914) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_OFFS (0x914) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x918) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x918) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_OFFS (0x918) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x91c) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x91c) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_OFFS (0x91c) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x) ((x) + 0x920) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_PHYS(x) ((x) + 0x920) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_OFFS (0x920) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x930) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x930) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_OFFS (0x930) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x) ((x) + 0x934) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_PHYS(x) ((x) + 0x934) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_OFFS (0x934) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x) ((x) + 0x938) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_PHYS(x) ((x) + 0x938) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_OFFS (0x938) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x) ((x) + 0x93c) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_PHYS(x) ((x) + 0x93c) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_OFFS (0x93c) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x) ((x) + 0x940) +#define HWIO_REO_R0_REO2PPE_RING_ID_PHYS(x) ((x) + 0x940) +#define HWIO_REO_R0_REO2PPE_RING_ID_OFFS (0x940) +#define HWIO_REO_R0_REO2PPE_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2PPE_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2PPE_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_STATUS_ADDR(x) ((x) + 0x944) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_PHYS(x) ((x) + 0x944) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_OFFS (0x944) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2PPE_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2PPE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2PPE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2PPE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x) ((x) + 0x948) +#define HWIO_REO_R0_REO2PPE_RING_MISC_PHYS(x) ((x) + 0x948) +#define HWIO_REO_R0_REO2PPE_RING_MISC_OFFS (0x948) +#define HWIO_REO_R0_REO2PPE_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2PPE_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2PPE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2PPE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2PPE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2PPE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2PPE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2PPE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2PPE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2PPE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2PPE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2PPE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2PPE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2PPE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x94c) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x94c) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_OFFS (0x94c) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x950) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x950) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_OFFS (0x950) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x95c) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x95c) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_OFFS (0x95c) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x960) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x960) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_OFFS (0x960) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x964) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x964) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_OFFS (0x964) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x980) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x980) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_OFFS (0x980) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x984) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x984) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_OFFS (0x984) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x) ((x) + 0x988) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_PHYS(x) ((x) + 0x988) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_OFFS (0x988) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x98c) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x98c) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_OFFS (0x98c) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x990) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x990) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_OFFS (0x990) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x994) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x994) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_OFFS (0x994) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x) ((x) + 0x998) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_PHYS(x) ((x) + 0x998) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_OFFS (0x998) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x9a8) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x9a8) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_OFFS (0x9a8) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x) ((x) + 0x9ac) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_PHYS(x) ((x) + 0x9ac) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_OFFS (0x9ac) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x) ((x) + 0x9b0) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x) ((x) + 0x9b0) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OFFS (0x9b0) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x) ((x) + 0x9b4) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x) ((x) + 0x9b4) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OFFS (0x9b4) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x) ((x) + 0x9b8) +#define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x) ((x) + 0x9b8) +#define HWIO_REO_R0_REO2FW_RING_ID_OFFS (0x9b8) +#define HWIO_REO_R0_REO2FW_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2FW_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x) ((x) + 0x9bc) +#define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x) ((x) + 0x9bc) +#define HWIO_REO_R0_REO2FW_RING_STATUS_OFFS (0x9bc) +#define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x) ((x) + 0x9c0) +#define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x) ((x) + 0x9c0) +#define HWIO_REO_R0_REO2FW_RING_MISC_OFFS (0x9c0) +#define HWIO_REO_R0_REO2FW_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2FW_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2FW_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2FW_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x9c4) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x9c4) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OFFS (0x9c4) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x9c8) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x9c8) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OFFS (0x9c8) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x9d4) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x9d4) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OFFS (0x9d4) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x9d8) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x9d8) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OFFS (0x9d8) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x9dc) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x9dc) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OFFS (0x9dc) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x9f8) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x9f8) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OFFS (0x9f8) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x9fc) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x9fc) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OFFS (0x9fc) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x) ((x) + 0xa00) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x) ((x) + 0xa00) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OFFS (0xa00) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xa04) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xa04) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_OFFS (0xa04) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xa08) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xa08) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_OFFS (0xa08) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xa0c) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xa0c) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_OFFS (0xa0c) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_ADDR(x) ((x) + 0xa10) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_PHYS(x) ((x) + 0xa10) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_OFFS (0xa10) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa20) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa20) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OFFS (0xa20) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MISC_1_ADDR(x) ((x) + 0xa24) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_PHYS(x) ((x) + 0xa24) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_OFFS (0xa24) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2FW_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2FW_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2FW_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xa28) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xa28) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OFFS (0xa28) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xa2c) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xa2c) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OFFS (0xa2c) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x) ((x) + 0xa30) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x) ((x) + 0xa30) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_OFFS (0xa30) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xa34) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xa34) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OFFS (0xa34) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x) ((x) + 0xa38) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x) ((x) + 0xa38) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OFFS (0xa38) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xa3c) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xa3c) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OFFS (0xa3c) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xa40) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xa40) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OFFS (0xa40) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xa4c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xa4c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xa4c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xa50) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xa50) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xa50) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xa54) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xa54) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xa54) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xa7c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xa7c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xa7c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa98) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa98) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xa98) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xa9c) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xa9c) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_OFFS (0xa9c) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0xaa0) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0xaa0) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OFFS (0xaa0) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0xaa4) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0xaa4) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OFFS (0xaa4) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x) ((x) + 0xaa8) +#define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x) ((x) + 0xaa8) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OFFS (0xaa8) +#define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x) ((x) + 0xaac) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x) ((x) + 0xaac) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OFFS (0xaac) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x) ((x) + 0xab0) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x) ((x) + 0xab0) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OFFS (0xab0) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xab4) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xab4) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OFFS (0xab4) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xab8) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xab8) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OFFS (0xab8) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xac4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xac4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0xac4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xac8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xac8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0xac8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xacc) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xacc) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0xacc) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xae8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xae8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OFFS (0xae8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xaec) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xaec) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OFFS (0xaec) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xaf0) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xaf0) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OFFS (0xaf0) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xaf4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xaf4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_OFFS (0xaf4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xaf8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xaf8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_OFFS (0xaf8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xafc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xafc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_OFFS (0xafc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x) ((x) + 0xb00) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_PHYS(x) ((x) + 0xb00) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_OFFS (0xb00) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xb10) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xb10) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xb10) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x) ((x) + 0xb14) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_PHYS(x) ((x) + 0xb14) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_OFFS (0xb14) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) ((x) + 0xb18) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) ((x) + 0xb18) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OFFS (0xb18) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0xffff3fff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_POR 0x03e80fa0 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ATTR 0x3 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \ + in_dword(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x)) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), m) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, v) \ + out_dword(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x),v) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x),m,v,HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_WARNING_TIMEOUT_BMSK 0xffff0000 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_WARNING_TIMEOUT_SHFT 16 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK 0x3000 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT 12 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ERROR_TIMEOUT_BMSK 0xfff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ERROR_TIMEOUT_SHFT 0 + +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_ADDR(x) ((x) + 0xb1c) +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_PHYS(x) ((x) + 0xb1c) +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_OFFS (0xb1c) +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_RMSK 0x1e7f +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_WATCHDOG_WARNING_STATUS_ADDR(x)) +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WATCHDOG_WARNING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2PPE_RING_BACK_PRESSURE_BMSK 0x1000 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2PPE_RING_BACK_PRESSURE_SHFT 12 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO_RELEASE_RING_BACK_PRESSURE_BMSK 0x800 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO_RELEASE_RING_BACK_PRESSURE_SHFT 11 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO_STATUS_RING_BACK_PRESSURE_BMSK 0x400 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO_STATUS_RING_BACK_PRESSURE_SHFT 10 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2FW_RING_BACK_PRESSURE_BMSK 0x200 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2FW_RING_BACK_PRESSURE_SHFT 9 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW6_RING_BACK_PRESSURE_BMSK 0x40 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW6_RING_BACK_PRESSURE_SHFT 6 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW5_RING_BACK_PRESSURE_BMSK 0x20 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW5_RING_BACK_PRESSURE_SHFT 5 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW4_RING_BACK_PRESSURE_BMSK 0x10 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW4_RING_BACK_PRESSURE_SHFT 4 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW3_RING_BACK_PRESSURE_BMSK 0x8 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW3_RING_BACK_PRESSURE_SHFT 3 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW2_RING_BACK_PRESSURE_BMSK 0x4 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW2_RING_BACK_PRESSURE_SHFT 2 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW1_RING_BACK_PRESSURE_BMSK 0x2 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW1_RING_BACK_PRESSURE_SHFT 1 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW0_RING_BACK_PRESSURE_BMSK 0x1 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW0_RING_BACK_PRESSURE_SHFT 0 + +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x) ((x) + 0xb20) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x) ((x) + 0xb20) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OFFS (0xb20) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_POR 0x00000000 +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ATTR 0x1 +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x)) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), m) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK 0xffffffff +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT 0 + +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x) ((x) + 0xb24) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x) ((x) + 0xb24) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS (0xb24) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK 0x1ff +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR 0x0000002d +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR 0x3 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x) \ + in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v) \ + out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK 0x1fe +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT 1 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK 0x1 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0xb28) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x) ((x) + 0xb28) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OFFS (0xb28) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_POR 0x000186a0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ATTR 0x3 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x),v) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x),m,v,HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0xb2c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x) ((x) + 0xb2c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OFFS (0xb2c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_POR 0x000186a0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ATTR 0x3 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x),v) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x),m,v,HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0xb30) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x) ((x) + 0xb30) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OFFS (0xb30) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_POR 0x00009c40 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ATTR 0x3 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x),v) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x),m,v,HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0xb34) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x) ((x) + 0xb34) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OFFS (0xb34) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_POR 0x00009c40 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ATTR 0x3 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x),v) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x),m,v,HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x) ((x) + 0xb38) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x) ((x) + 0xb38) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OFFS (0xb38) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x) ((x) + 0xb3c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x) ((x) + 0xb3c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OFFS (0xb3c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x) ((x) + 0xb40) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x) ((x) + 0xb40) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OFFS (0xb40) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x) ((x) + 0xb44) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x) ((x) + 0xb44) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OFFS (0xb44) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x) ((x) + 0xb48) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x) ((x) + 0xb48) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OFFS (0xb48) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x) ((x) + 0xb4c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x) ((x) + 0xb4c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OFFS (0xb4c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x) ((x) + 0xb50) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x) ((x) + 0xb50) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OFFS (0xb50) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x) ((x) + 0xb54) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x) ((x) + 0xb54) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OFFS (0xb54) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x) ((x) + 0xb58) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x) ((x) + 0xb58) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OFFS (0xb58) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x) ((x) + 0xb5c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x) ((x) + 0xb5c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OFFS (0xb5c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x) ((x) + 0xb60) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x) ((x) + 0xb60) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OFFS (0xb60) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x) ((x) + 0xb64) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x) ((x) + 0xb64) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OFFS (0xb64) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x) ((x) + 0xb68) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x) ((x) + 0xb68) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OFFS (0xb68) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x) ((x) + 0xb6c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x) ((x) + 0xb6c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OFFS (0xb6c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x) ((x) + 0xb70) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x) ((x) + 0xb70) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OFFS (0xb70) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x) ((x) + 0xb74) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x) ((x) + 0xb74) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OFFS (0xb74) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x) ((x) + 0xb78) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x) ((x) + 0xb78) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OFFS (0xb78) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT 0 + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x) ((x) + 0xb7c) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x) ((x) + 0xb7c) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OFFS (0xb7c) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT 0 + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x) ((x) + 0xb80) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x) ((x) + 0xb80) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OFFS (0xb80) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT 0 + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x) ((x) + 0xb84) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x) ((x) + 0xb84) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OFFS (0xb84) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT 0 + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x) ((x) + 0xb88) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x) ((x) + 0xb88) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OFFS (0xb88) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT 0 + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x) ((x) + 0xb8c) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x) ((x) + 0xb8c) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OFFS (0xb8c) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT 0 + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x) ((x) + 0xb90) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x) ((x) + 0xb90) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OFFS (0xb90) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT 0 + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x) ((x) + 0xb94) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x) ((x) + 0xb94) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OFFS (0xb94) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT 0 + +#define HWIO_REO_R0_AGING_CONTROL_ADDR(x) ((x) + 0xb98) +#define HWIO_REO_R0_AGING_CONTROL_PHYS(x) ((x) + 0xb98) +#define HWIO_REO_R0_AGING_CONTROL_OFFS (0xb98) +#define HWIO_REO_R0_AGING_CONTROL_RMSK 0x1f +#define HWIO_REO_R0_AGING_CONTROL_POR 0x00000000 +#define HWIO_REO_R0_AGING_CONTROL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_CONTROL_ATTR 0x3 +#define HWIO_REO_R0_AGING_CONTROL_IN(x) \ + in_dword(HWIO_REO_R0_AGING_CONTROL_ADDR(x)) +#define HWIO_REO_R0_AGING_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_CONTROL_ADDR(x), m) +#define HWIO_REO_R0_AGING_CONTROL_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_CONTROL_ADDR(x),v) +#define HWIO_REO_R0_AGING_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x),m,v,HWIO_REO_R0_AGING_CONTROL_IN(x)) +#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK 0x1f +#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0xb9c) +#define HWIO_REO_R0_MISC_CTL_PHYS(x) ((x) + 0xb9c) +#define HWIO_REO_R0_MISC_CTL_OFFS (0xb9c) +#define HWIO_REO_R0_MISC_CTL_RMSK 0x3fffffff +#define HWIO_REO_R0_MISC_CTL_POR 0x0cac0008 +#define HWIO_REO_R0_MISC_CTL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MISC_CTL_ATTR 0x3 +#define HWIO_REO_R0_MISC_CTL_IN(x) \ + in_dword(HWIO_REO_R0_MISC_CTL_ADDR(x)) +#define HWIO_REO_R0_MISC_CTL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MISC_CTL_ADDR(x), m) +#define HWIO_REO_R0_MISC_CTL_OUT(x, v) \ + out_dword(HWIO_REO_R0_MISC_CTL_ADDR(x),v) +#define HWIO_REO_R0_MISC_CTL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_ADDR(x),m,v,HWIO_REO_R0_MISC_CTL_IN(x)) +#define HWIO_REO_R0_MISC_CTL_WCSS_INDICATION_BMSK 0x20000000 +#define HWIO_REO_R0_MISC_CTL_WCSS_INDICATION_SHFT 29 +#define HWIO_REO_R0_MISC_CTL_SOFT_REORDER_DEST_RING_BMSK 0x1e000000 +#define HWIO_REO_R0_MISC_CTL_SOFT_REORDER_DEST_RING_SHFT 25 +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 +#define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_BMSK 0x10000 +#define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_SHFT 16 +#define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_BMSK 0x8000 +#define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_SHFT 15 +#define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_BMSK 0x7fff +#define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0 + +#define HWIO_REO_R0_MISC_CTL_2_ADDR(x) ((x) + 0xba0) +#define HWIO_REO_R0_MISC_CTL_2_PHYS(x) ((x) + 0xba0) +#define HWIO_REO_R0_MISC_CTL_2_OFFS (0xba0) +#define HWIO_REO_R0_MISC_CTL_2_RMSK 0x3ffffff +#define HWIO_REO_R0_MISC_CTL_2_POR 0x00000000 +#define HWIO_REO_R0_MISC_CTL_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MISC_CTL_2_ATTR 0x3 +#define HWIO_REO_R0_MISC_CTL_2_IN(x) \ + in_dword(HWIO_REO_R0_MISC_CTL_2_ADDR(x)) +#define HWIO_REO_R0_MISC_CTL_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MISC_CTL_2_ADDR(x), m) +#define HWIO_REO_R0_MISC_CTL_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_MISC_CTL_2_ADDR(x),v) +#define HWIO_REO_R0_MISC_CTL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_2_ADDR(x),m,v,HWIO_REO_R0_MISC_CTL_2_IN(x)) +#define HWIO_REO_R0_MISC_CTL_2_REO2PPE_RING_PRIORITY_BMSK 0x3000000 +#define HWIO_REO_R0_MISC_CTL_2_REO2PPE_RING_PRIORITY_SHFT 24 +#define HWIO_REO_R0_MISC_CTL_2_REO_STATUS_RING_PRIORITY_BMSK 0xc00000 +#define HWIO_REO_R0_MISC_CTL_2_REO_STATUS_RING_PRIORITY_SHFT 22 +#define HWIO_REO_R0_MISC_CTL_2_REO_RELEASE_RING_PRIORITY_BMSK 0x300000 +#define HWIO_REO_R0_MISC_CTL_2_REO_RELEASE_RING_PRIORITY_SHFT 20 +#define HWIO_REO_R0_MISC_CTL_2_REO2FW_RING_PRIORITY_BMSK 0xc0000 +#define HWIO_REO_R0_MISC_CTL_2_REO2FW_RING_PRIORITY_SHFT 18 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW0_RING_PRIORITY_BMSK 0x30000 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW0_RING_PRIORITY_SHFT 16 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW8_RING_PRIORITY_BMSK 0xc000 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW8_RING_PRIORITY_SHFT 14 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW7_RING_PRIORITY_BMSK 0x3000 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW7_RING_PRIORITY_SHFT 12 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW6_RING_PRIORITY_BMSK 0xc00 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW6_RING_PRIORITY_SHFT 10 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW5_RING_PRIORITY_BMSK 0x300 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW5_RING_PRIORITY_SHFT 8 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW4_RING_PRIORITY_BMSK 0xc0 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW4_RING_PRIORITY_SHFT 6 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW3_RING_PRIORITY_BMSK 0x30 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW3_RING_PRIORITY_SHFT 4 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW2_RING_PRIORITY_BMSK 0xc +#define HWIO_REO_R0_MISC_CTL_2_REO2SW2_RING_PRIORITY_SHFT 2 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW1_RING_PRIORITY_BMSK 0x3 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW1_RING_PRIORITY_SHFT 0 + +#define HWIO_REO_R0_MISC_CTL_3_ADDR(x) ((x) + 0xba4) +#define HWIO_REO_R0_MISC_CTL_3_PHYS(x) ((x) + 0xba4) +#define HWIO_REO_R0_MISC_CTL_3_OFFS (0xba4) +#define HWIO_REO_R0_MISC_CTL_3_RMSK 0xfff +#define HWIO_REO_R0_MISC_CTL_3_POR 0x00000e00 +#define HWIO_REO_R0_MISC_CTL_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MISC_CTL_3_ATTR 0x3 +#define HWIO_REO_R0_MISC_CTL_3_IN(x) \ + in_dword(HWIO_REO_R0_MISC_CTL_3_ADDR(x)) +#define HWIO_REO_R0_MISC_CTL_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MISC_CTL_3_ADDR(x), m) +#define HWIO_REO_R0_MISC_CTL_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_MISC_CTL_3_ADDR(x),v) +#define HWIO_REO_R0_MISC_CTL_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_3_ADDR(x),m,v,HWIO_REO_R0_MISC_CTL_3_IN(x)) +#define HWIO_REO_R0_MISC_CTL_3_REO_QDESC_VC_ID_BMSK 0x800 +#define HWIO_REO_R0_MISC_CTL_3_REO_QDESC_VC_ID_SHFT 11 +#define HWIO_REO_R0_MISC_CTL_3_REO_VA_VC_ID_BMSK 0x400 +#define HWIO_REO_R0_MISC_CTL_3_REO_VA_VC_ID_SHFT 10 +#define HWIO_REO_R0_MISC_CTL_3_SEQ_VC_ID_BMSK 0x200 +#define HWIO_REO_R0_MISC_CTL_3_SEQ_VC_ID_SHFT 9 +#define HWIO_REO_R0_MISC_CTL_3_ENTR_LINK_DESC_VC_ID_BMSK 0x100 +#define HWIO_REO_R0_MISC_CTL_3_ENTR_LINK_DESC_VC_ID_SHFT 8 +#define HWIO_REO_R0_MISC_CTL_3_ENTR_CMD_VC_ID_BMSK 0x80 +#define HWIO_REO_R0_MISC_CTL_3_ENTR_CMD_VC_ID_SHFT 7 +#define HWIO_REO_R0_MISC_CTL_3_ENTR6_VC_ID_BMSK 0x40 +#define HWIO_REO_R0_MISC_CTL_3_ENTR6_VC_ID_SHFT 6 +#define HWIO_REO_R0_MISC_CTL_3_ENTR5_VC_ID_BMSK 0x20 +#define HWIO_REO_R0_MISC_CTL_3_ENTR5_VC_ID_SHFT 5 +#define HWIO_REO_R0_MISC_CTL_3_ENTR4_VC_ID_BMSK 0x10 +#define HWIO_REO_R0_MISC_CTL_3_ENTR4_VC_ID_SHFT 4 +#define HWIO_REO_R0_MISC_CTL_3_ENTR3_VC_ID_BMSK 0x8 +#define HWIO_REO_R0_MISC_CTL_3_ENTR3_VC_ID_SHFT 3 +#define HWIO_REO_R0_MISC_CTL_3_ENTR2_VC_ID_BMSK 0x4 +#define HWIO_REO_R0_MISC_CTL_3_ENTR2_VC_ID_SHFT 2 +#define HWIO_REO_R0_MISC_CTL_3_ENTR1_VC_ID_BMSK 0x2 +#define HWIO_REO_R0_MISC_CTL_3_ENTR1_VC_ID_SHFT 1 +#define HWIO_REO_R0_MISC_CTL_3_ENTR0_VC_ID_BMSK 0x1 +#define HWIO_REO_R0_MISC_CTL_3_ENTR0_VC_ID_SHFT 0 + +#define HWIO_REO_R0_MISC_CTL_4_ADDR(x) ((x) + 0xba8) +#define HWIO_REO_R0_MISC_CTL_4_PHYS(x) ((x) + 0xba8) +#define HWIO_REO_R0_MISC_CTL_4_OFFS (0xba8) +#define HWIO_REO_R0_MISC_CTL_4_RMSK 0x1fffff +#define HWIO_REO_R0_MISC_CTL_4_POR 0x00000000 +#define HWIO_REO_R0_MISC_CTL_4_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MISC_CTL_4_ATTR 0x3 +#define HWIO_REO_R0_MISC_CTL_4_IN(x) \ + in_dword(HWIO_REO_R0_MISC_CTL_4_ADDR(x)) +#define HWIO_REO_R0_MISC_CTL_4_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MISC_CTL_4_ADDR(x), m) +#define HWIO_REO_R0_MISC_CTL_4_OUT(x, v) \ + out_dword(HWIO_REO_R0_MISC_CTL_4_ADDR(x),v) +#define HWIO_REO_R0_MISC_CTL_4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_4_ADDR(x),m,v,HWIO_REO_R0_MISC_CTL_4_IN(x)) +#define HWIO_REO_R0_MISC_CTL_4_CACHE_FLUSH_TIMER_ENABLE_BMSK 0x100000 +#define HWIO_REO_R0_MISC_CTL_4_CACHE_FLUSH_TIMER_ENABLE_SHFT 20 +#define HWIO_REO_R0_MISC_CTL_4_CACHE_FLUSH_TIMER_LIMIT_BMSK 0xfffff +#define HWIO_REO_R0_MISC_CTL_4_CACHE_FLUSH_TIMER_LIMIT_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_ADDR(base,n) ((base) + 0XBAC + (0x4*(n))) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_PHYS(base,n) ((base) + 0XBAC + (0x4*(n))) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_OFFS(n) (0XBAC + (0x4*(n))) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_RMSK 0xffff +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_MAXn 16 +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_INI(base,n) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_INT_PRI_n_ADDR(base,n), HWIO_REO_R0_REO2PPE_INT_PRI_n_RMSK) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_INT_PRI_n_ADDR(base,n), mask) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_OUTI(base,n,val) \ + out_dword(HWIO_REO_R0_REO2PPE_INT_PRI_n_ADDR(base,n),val) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_INT_PRI_n_ADDR(base,n),mask,val,HWIO_REO_R0_REO2PPE_INT_PRI_n_INI(base,n)) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_TABLE_BMSK 0xffff +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_TABLE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_ADDR(base,n) ((base) + 0XBF0 + (0x4*(n))) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_PHYS(base,n) ((base) + 0XBF0 + (0x4*(n))) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_OFFS(n) (0XBF0 + (0x4*(n))) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_RMSK 0xffff +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_MAXn 63 +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_INI(base,n) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_SRC_INFO_n_ADDR(base,n), HWIO_REO_R0_REO2PPE_SRC_INFO_n_RMSK) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_SRC_INFO_n_ADDR(base,n), mask) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_OUTI(base,n,val) \ + out_dword(HWIO_REO_R0_REO2PPE_SRC_INFO_n_ADDR(base,n),val) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_SRC_INFO_n_ADDR(base,n),mask,val,HWIO_REO_R0_REO2PPE_SRC_INFO_n_INI(base,n)) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_TABLE_BMSK 0xffff +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_TABLE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(x) ((x) + 0xcf0) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_PHYS(x) ((x) + 0xcf0) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_OFFS (0xcf0) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_RMSK 0xffff +#define HWIO_REO_R0_REO2PPE_DEST_INFO_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_DEST_INFO_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_DEST_INFO_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_DEST_INFO_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_DEST_INFO_IN(x)) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_DST_INFO_BMSK 0xffff +#define HWIO_REO_R0_REO2PPE_DEST_INFO_DST_INFO_SHFT 0 + +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x) ((x) + 0xcf4) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x) ((x) + 0xcf4) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OFFS (0xcf4) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_POR 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_POR_RMSK 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ATTR 0x3 +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x) \ + in_dword(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x)) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), m) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, v) \ + out_dword(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x),v) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x),m,v,HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x) ((x) + 0xcf8) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x) ((x) + 0xcf8) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OFFS (0xcf8) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x)) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT 0 + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x) ((x) + 0xcfc) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x) ((x) + 0xcfc) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OFFS (0xcfc) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x)) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT 0 + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x) ((x) + 0xd00) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x) ((x) + 0xd00) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OFFS (0xd00) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x)) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT 0 + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x) ((x) + 0xd04) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x) ((x) + 0xd04) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OFFS (0xd04) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x)) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x) ((x) + 0xd08) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x) ((x) + 0xd08) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OFFS (0xd08) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_POR 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x) ((x) + 0xd0c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x) ((x) + 0xd0c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OFFS (0xd0c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_POR 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x) ((x) + 0xd10) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x) ((x) + 0xd10) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OFFS (0xd10) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_POR 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x) ((x) + 0xd14) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x) ((x) + 0xd14) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OFFS (0xd14) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK 0x3ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_POR 0x03ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x3ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x) ((x) + 0xd18) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x) ((x) + 0xd18) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OFFS (0xd18) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_POR 0x00000000 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x) ((x) + 0xd1c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x) ((x) + 0xd1c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OFFS (0xd1c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_POR 0x00000000 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x) ((x) + 0xd20) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x) ((x) + 0xd20) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OFFS (0xd20) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_POR 0x00000000 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x) ((x) + 0xd24) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x) ((x) + 0xd24) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OFFS (0xd24) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK 0x1 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_POR 0x00000000 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x1 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x) ((x) + 0xd28) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x) ((x) + 0xd28) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OFFS (0xd28) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x) ((x) + 0xd2c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x) ((x) + 0xd2c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OFFS (0xd2c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x) ((x) + 0xd30) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x) ((x) + 0xd30) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OFFS (0xd30) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x) ((x) + 0xd34) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x) ((x) + 0xd34) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OFFS (0xd34) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x) ((x) + 0xd38) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x) ((x) + 0xd38) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OFFS (0xd38) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x) ((x) + 0xd3c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x) ((x) + 0xd3c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OFFS (0xd3c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x) ((x) + 0xd40) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x) ((x) + 0xd40) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OFFS (0xd40) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x) ((x) + 0xd44) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x) ((x) + 0xd44) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OFFS (0xd44) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x) ((x) + 0xd48) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x) ((x) + 0xd48) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OFFS (0xd48) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK 0x1f +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK 0x10 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT 4 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK 0xf +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x) ((x) + 0xd74) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x) ((x) + 0xd74) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OFFS (0xd74) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_POR 0x008609ff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \ + in_dword(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, v) \ + out_dword(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_BMSK 0xff000000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_SHFT 24 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_BMSK 0x800000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_SHFT 23 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x400000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 22 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x200000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 21 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x100000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 20 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x80000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 19 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x40000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 18 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x20000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 17 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x1fe00 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 9 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x1ff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x) ((x) + 0xd78) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x) ((x) + 0xd78) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OFFS (0xd78) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK 0x3 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_POR 0x00000000 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_CONTROL_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \ + in_dword(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, v) \ + out_dword(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_BMSK 0x2 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_SHFT 1 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x1 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x) ((x) + 0xd7c) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_PHYS(x) ((x) + 0xd7c) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OFFS (0xd7c) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK 0x1ffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_POR 0x00000000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x) \ + in_dword(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUT(x, v) \ + out_dword(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_BMSK 0x1ffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x) ((x) + 0xd80) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_PHYS(x) ((x) + 0xd80) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OFFS (0xd80) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK 0x3ff +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_POR 0x000000f0 +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x) \ + in_dword(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUT(x, v) \ + out_dword(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_BMSK 0x3ff +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x) ((x) + 0xd84) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_PHYS(x) ((x) + 0xd84) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_OFFS (0xd84) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_RMSK 0x7 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_POR 0x00000002 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_IN(x) \ + in_dword(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_OUT(x, v) \ + out_dword(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_VC_ID_BMSK 0x4 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_VC_ID_SHFT 2 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_GXI_PRIORITY_BMSK 0x3 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_GXI_PRIORITY_SHFT 0 + +#define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x) ((x) + 0xd88) +#define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x) ((x) + 0xd88) +#define HWIO_REO_R0_CLK_GATE_CTRL_OFFS (0xd88) +#define HWIO_REO_R0_CLK_GATE_CTRL_RMSK 0x7ffff +#define HWIO_REO_R0_CLK_GATE_CTRL_POR 0x00000400 +#define HWIO_REO_R0_CLK_GATE_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CLK_GATE_CTRL_ATTR 0x3 +#define HWIO_REO_R0_CLK_GATE_CTRL_IN(x) \ + in_dword(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x)) +#define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), m) +#define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x),v) +#define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x),m,v,HWIO_REO_R0_CLK_GATE_CTRL_IN(x)) +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK 0x40000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT 18 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK 0x20000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT 17 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK 0x10000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT 16 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK 0x8000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT 15 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK 0x4000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT 14 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK 0x2000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT 13 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_BMSK 0x1000 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_SHFT 12 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_BMSK 0x800 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_SHFT 11 +#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x400 +#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT 10 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK 0x3ff +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT 0 + +#define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x) ((x) + 0xd8c) +#define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x) ((x) + 0xd8c) +#define HWIO_REO_R0_EVENTMASK_IX_0_OFFS (0xd8c) +#define HWIO_REO_R0_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_0_POR 0x00000000 +#define HWIO_REO_R0_EVENTMASK_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_0_ATTR 0x3 +#define HWIO_REO_R0_EVENTMASK_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x)) +#define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), m) +#define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x),v) +#define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_REO_R0_EVENTMASK_IX_0_IN(x)) +#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT 0 + +#define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x) ((x) + 0xd90) +#define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x) ((x) + 0xd90) +#define HWIO_REO_R0_EVENTMASK_IX_1_OFFS (0xd90) +#define HWIO_REO_R0_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_1_POR 0x00000000 +#define HWIO_REO_R0_EVENTMASK_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_1_ATTR 0x3 +#define HWIO_REO_R0_EVENTMASK_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x)) +#define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), m) +#define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x),v) +#define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_REO_R0_EVENTMASK_IX_1_IN(x)) +#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT 0 + +#define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x) ((x) + 0xd94) +#define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x) ((x) + 0xd94) +#define HWIO_REO_R0_EVENTMASK_IX_2_OFFS (0xd94) +#define HWIO_REO_R0_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_2_POR 0x00000000 +#define HWIO_REO_R0_EVENTMASK_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_2_ATTR 0x3 +#define HWIO_REO_R0_EVENTMASK_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x)) +#define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), m) +#define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x),v) +#define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x),m,v,HWIO_REO_R0_EVENTMASK_IX_2_IN(x)) +#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT 0 + +#define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x) ((x) + 0xd98) +#define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x) ((x) + 0xd98) +#define HWIO_REO_R0_EVENTMASK_IX_3_OFFS (0xd98) +#define HWIO_REO_R0_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_3_POR 0x00000000 +#define HWIO_REO_R0_EVENTMASK_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_3_ATTR 0x3 +#define HWIO_REO_R0_EVENTMASK_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x)) +#define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), m) +#define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x),v) +#define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x),m,v,HWIO_REO_R0_EVENTMASK_IX_3_IN(x)) +#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT 0 + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x) ((x) + 0x2000) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x) ((x) + 0x2000) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_OFFS (0x2000) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK 0xffffffff +#define HWIO_REO_R1_MISC_DEBUG_CTRL_POR 0x100771f0 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R1_MISC_DEBUG_CTRL_ATTR 0x3 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x) \ + in_dword(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x)) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), m) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x),v) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x),m,v,HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_BMSK 0x80000000 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_SHFT 31 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_BMSK 0x40000000 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_SHFT 30 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK 0x3ff00000 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT 20 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK 0xffc00 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT 10 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK 0x3ff +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT 0 + +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x) ((x) + 0x2004) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x) ((x) + 0x2004) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OFFS (0x2004) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK 0xffffff +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_POR 0x003ff03f +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ATTR 0x3 +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x) \ + in_dword(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x)) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), m) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x),v) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x),m,v,HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0xfff000 +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT 12 +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK 0xfff +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) ((x) + 0x2008) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) ((x) + 0x2008) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OFFS (0x2008) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x1fff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_POR 0x00001000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x1000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 12 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 11 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x400 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 10 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x3ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) ((x) + 0x200c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) ((x) + 0x200c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OFFS (0x200c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) ((x) + 0x2010) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) ((x) + 0x2010) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OFFS (0x2010) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0xffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0xffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) ((x) + 0x2014) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) ((x) + 0x2014) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OFFS (0x2014) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) ((x) + 0x2018) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) ((x) + 0x2018) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OFFS (0x2018) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x) ((x) + 0x201c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x) ((x) + 0x201c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OFFS (0x201c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK 0x1ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x1ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) ((x) + 0x2020) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) ((x) + 0x2020) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OFFS (0x2020) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0x3fffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x3ff800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 11 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x7ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x) ((x) + 0x2024) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_PHYS(x) ((x) + 0x2024) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OFFS (0x2024) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK 0x3fffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_BMSK 0x3ff800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_SHFT 11 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_BMSK 0x7ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x) ((x) + 0x2028) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_PHYS(x) ((x) + 0x2028) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OFFS (0x2028) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK 0x3fffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_BMSK 0x3ff800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_SHFT 11 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_BMSK 0x7ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x) ((x) + 0x202c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_PHYS(x) ((x) + 0x202c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OFFS (0x202c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK 0x3fffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_BMSK 0x3ff800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_SHFT 11 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_BMSK 0x7ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x) ((x) + 0x2030) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_PHYS(x) ((x) + 0x2030) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OFFS (0x2030) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x) ((x) + 0x2034) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_PHYS(x) ((x) + 0x2034) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OFFS (0x2034) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x) ((x) + 0x2038) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_PHYS(x) ((x) + 0x2038) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OFFS (0x2038) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK 0xfffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_BMSK 0xffc00 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_SHFT 10 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_BMSK 0x3ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x203c) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x203c) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OFFS (0x203c) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x) ((x) + 0x2040) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_PHYS(x) ((x) + 0x2040) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OFFS (0x2040) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK 0x7ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_BMSK 0x7f8 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_SHFT 3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_BMSK 0x4 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_SHFT 2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_BMSK 0x2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_SHFT 1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_BMSK 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x) ((x) + 0x2044) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_PHYS(x) ((x) + 0x2044) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OFFS (0x2044) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x) ((x) + 0x2048) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_PHYS(x) ((x) + 0x2048) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OFFS (0x2048) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x) ((x) + 0x204c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_PHYS(x) ((x) + 0x204c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OFFS (0x204c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK 0x3fffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_POR 0x00000001 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_BMSK 0x3fc00000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_SHFT 22 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_BMSK 0x3ff000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_SHFT 12 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_BMSK 0x800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_SHFT 11 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_BMSK 0x600 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_SHFT 9 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_BMSK 0x1e0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_SHFT 5 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_BMSK 0x1c +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_SHFT 2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_BMSK 0x2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_SHFT 1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_BMSK 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR(x) ((x) + 0x2050) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_PHYS(x) ((x) + 0x2050) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_OFFS (0x2050) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_RMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ACT_ADDR_BMSK 0xf0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ACT_ADDR_SHFT 4 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_EXP_ADDR_BMSK 0xf +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_EXP_ADDR_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x205c) +#define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x205c) +#define HWIO_REO_R1_END_OF_TEST_CHECK_OFFS (0x205c) +#define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_REO_R1_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_REO_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_REO_R1_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)) +#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) ((x) + 0x2060) +#define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) ((x) + 0x2060) +#define HWIO_REO_R1_SM_ALL_IDLE_OFFS (0x2060) +#define HWIO_REO_R1_SM_ALL_IDLE_RMSK 0x7 +#define HWIO_REO_R1_SM_ALL_IDLE_POR 0x00000001 +#define HWIO_REO_R1_SM_ALL_IDLE_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_ALL_IDLE_ATTR 0x1 +#define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \ + in_dword(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x)) +#define HWIO_REO_R1_SM_ALL_IDLE_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), m) +#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK 0x4 +#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT 2 +#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK 0x2 +#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT 1 +#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK 0x1 +#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT 0 + +#define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x2064) +#define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x2064) +#define HWIO_REO_R1_TESTBUS_CTRL_OFFS (0x2064) +#define HWIO_REO_R1_TESTBUS_CTRL_RMSK 0x7f +#define HWIO_REO_R1_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_REO_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \ + in_dword(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x)) +#define HWIO_REO_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_REO_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x7f +#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0 + +#define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) ((x) + 0x2068) +#define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) ((x) + 0x2068) +#define HWIO_REO_R1_TESTBUS_LOWER_OFFS (0x2068) +#define HWIO_REO_R1_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_LOWER_POR 0x00000000 +#define HWIO_REO_R1_TESTBUS_LOWER_POR_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_LOWER_ATTR 0x1 +#define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \ + in_dword(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x)) +#define HWIO_REO_R1_TESTBUS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), m) +#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT 0 + +#define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) ((x) + 0x206c) +#define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) ((x) + 0x206c) +#define HWIO_REO_R1_TESTBUS_HIGHER_OFFS (0x206c) +#define HWIO_REO_R1_TESTBUS_HIGHER_RMSK 0xff +#define HWIO_REO_R1_TESTBUS_HIGHER_POR 0x00000000 +#define HWIO_REO_R1_TESTBUS_HIGHER_POR_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_HIGHER_ATTR 0x1 +#define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \ + in_dword(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x)) +#define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), m) +#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK 0xff +#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) ((x) + 0x2070) +#define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) ((x) + 0x2070) +#define HWIO_REO_R1_SM_STATES_IX_0_OFFS (0x2070) +#define HWIO_REO_R1_SM_STATES_IX_0_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_0_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_0_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) ((x) + 0x2074) +#define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) ((x) + 0x2074) +#define HWIO_REO_R1_SM_STATES_IX_1_OFFS (0x2074) +#define HWIO_REO_R1_SM_STATES_IX_1_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_1_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_1_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) ((x) + 0x2078) +#define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) ((x) + 0x2078) +#define HWIO_REO_R1_SM_STATES_IX_2_OFFS (0x2078) +#define HWIO_REO_R1_SM_STATES_IX_2_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_2_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_2_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) ((x) + 0x207c) +#define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) ((x) + 0x207c) +#define HWIO_REO_R1_SM_STATES_IX_3_OFFS (0x207c) +#define HWIO_REO_R1_SM_STATES_IX_3_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_3_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_3_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) ((x) + 0x2080) +#define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) ((x) + 0x2080) +#define HWIO_REO_R1_SM_STATES_IX_4_OFFS (0x2080) +#define HWIO_REO_R1_SM_STATES_IX_4_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_4_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_4_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_4_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_4_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) ((x) + 0x2084) +#define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) ((x) + 0x2084) +#define HWIO_REO_R1_SM_STATES_IX_5_OFFS (0x2084) +#define HWIO_REO_R1_SM_STATES_IX_5_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_5_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_5_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_5_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_5_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) ((x) + 0x2088) +#define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) ((x) + 0x2088) +#define HWIO_REO_R1_SM_STATES_IX_6_OFFS (0x2088) +#define HWIO_REO_R1_SM_STATES_IX_6_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_6_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_6_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_6_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_6_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_7_ADDR(x) ((x) + 0x208c) +#define HWIO_REO_R1_SM_STATES_IX_7_PHYS(x) ((x) + 0x208c) +#define HWIO_REO_R1_SM_STATES_IX_7_OFFS (0x208c) +#define HWIO_REO_R1_SM_STATES_IX_7_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_7_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_7_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_7_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_7_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_7_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_7_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_7_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_7_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_7_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_8_ADDR(x) ((x) + 0x2090) +#define HWIO_REO_R1_SM_STATES_IX_8_PHYS(x) ((x) + 0x2090) +#define HWIO_REO_R1_SM_STATES_IX_8_OFFS (0x2090) +#define HWIO_REO_R1_SM_STATES_IX_8_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_8_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_8_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_8_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_8_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_8_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_8_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_8_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_8_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_8_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_9_ADDR(x) ((x) + 0x2094) +#define HWIO_REO_R1_SM_STATES_IX_9_PHYS(x) ((x) + 0x2094) +#define HWIO_REO_R1_SM_STATES_IX_9_OFFS (0x2094) +#define HWIO_REO_R1_SM_STATES_IX_9_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_9_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_9_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_9_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_9_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_9_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_9_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_9_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_9_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_9_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_10_ADDR(x) ((x) + 0x2098) +#define HWIO_REO_R1_SM_STATES_IX_10_PHYS(x) ((x) + 0x2098) +#define HWIO_REO_R1_SM_STATES_IX_10_OFFS (0x2098) +#define HWIO_REO_R1_SM_STATES_IX_10_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_10_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_10_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_10_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_10_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_10_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_10_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_10_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_10_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_10_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_11_ADDR(x) ((x) + 0x209c) +#define HWIO_REO_R1_SM_STATES_IX_11_PHYS(x) ((x) + 0x209c) +#define HWIO_REO_R1_SM_STATES_IX_11_OFFS (0x209c) +#define HWIO_REO_R1_SM_STATES_IX_11_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_11_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_11_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_11_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_11_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_11_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_11_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_11_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_11_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_11_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_12_ADDR(x) ((x) + 0x20a0) +#define HWIO_REO_R1_SM_STATES_IX_12_PHYS(x) ((x) + 0x20a0) +#define HWIO_REO_R1_SM_STATES_IX_12_OFFS (0x20a0) +#define HWIO_REO_R1_SM_STATES_IX_12_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_12_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_12_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_12_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_12_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_12_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_12_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_12_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_12_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_12_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_13_ADDR(x) ((x) + 0x20a4) +#define HWIO_REO_R1_SM_STATES_IX_13_PHYS(x) ((x) + 0x20a4) +#define HWIO_REO_R1_SM_STATES_IX_13_OFFS (0x20a4) +#define HWIO_REO_R1_SM_STATES_IX_13_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_13_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_13_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_13_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_13_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_13_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_13_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_13_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_13_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_13_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) ((x) + 0x20a8) +#define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) ((x) + 0x20a8) +#define HWIO_REO_R1_IDLE_STATES_IX_0_OFFS (0x20a8) +#define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_0_POR 0x00000000 +#define HWIO_REO_R1_IDLE_STATES_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_0_ATTR 0x1 +#define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \ + in_dword(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x)) +#define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), m) +#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT 0 + +#define HWIO_REO_R1_IDLE_STATES_IX_1_ADDR(x) ((x) + 0x20ac) +#define HWIO_REO_R1_IDLE_STATES_IX_1_PHYS(x) ((x) + 0x20ac) +#define HWIO_REO_R1_IDLE_STATES_IX_1_OFFS (0x20ac) +#define HWIO_REO_R1_IDLE_STATES_IX_1_RMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_1_POR 0x00000000 +#define HWIO_REO_R1_IDLE_STATES_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_1_ATTR 0x1 +#define HWIO_REO_R1_IDLE_STATES_IX_1_IN(x) \ + in_dword(HWIO_REO_R1_IDLE_STATES_IX_1_ADDR(x)) +#define HWIO_REO_R1_IDLE_STATES_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_IDLE_STATES_IX_1_ADDR(x), m) +#define HWIO_REO_R1_IDLE_STATES_IX_1_IDLE_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_1_IDLE_STATE_SHFT 0 + +#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x) ((x) + 0x20b0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x) ((x) + 0x20b0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS (0x20b0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK 0x3f +#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR 0x00000000 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR 0x1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x) \ + in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK 0x20 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT 5 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK 0x10 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT 4 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK 0x8 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT 3 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK 0x4 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT 2 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK 0x2 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT 1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK 0x1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT 0 + +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x) ((x) + 0x20b4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x) ((x) + 0x20b4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS (0x20b4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR 0x00000000 +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR 0x3 +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x) \ + in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v) \ + out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT 0 + +#define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) ((x) + 0x20b8) +#define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) ((x) + 0x20b8) +#define HWIO_REO_R1_INVALID_APB_ACCESS_OFFS (0x20b8) +#define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK 0x7ffff +#define HWIO_REO_R1_INVALID_APB_ACCESS_POR 0x00000000 +#define HWIO_REO_R1_INVALID_APB_ACCESS_POR_RMSK 0xffffffff +#define HWIO_REO_R1_INVALID_APB_ACCESS_ATTR 0x3 +#define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \ + in_dword(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x)) +#define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), m) +#define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, v) \ + out_dword(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x),v) +#define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x),m,v,HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)) +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK 0x60000 +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT 17 +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK 0x1ffff +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT 0 + +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x) ((x) + 0x3000) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x) ((x) + 0x3000) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OFFS (0x3000) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x)) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x),m,v,HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x) ((x) + 0x3004) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x) ((x) + 0x3004) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OFFS (0x3004) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x)) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x),m,v,HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_ADDR(x) ((x) + 0x3008) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_PHYS(x) ((x) + 0x3008) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_OFFS (0x3008) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_ADDR(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_ADDR(x),m,v,HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_IN(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_ADDR(x) ((x) + 0x300c) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_PHYS(x) ((x) + 0x300c) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_OFFS (0x300c) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_ADDR(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_ADDR(x),m,v,HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_IN(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_ADDR(x) ((x) + 0x3010) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_PHYS(x) ((x) + 0x3010) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_OFFS (0x3010) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_ADDR(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_ADDR(x),m,v,HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_IN(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_ADDR(x) ((x) + 0x3014) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_PHYS(x) ((x) + 0x3014) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_OFFS (0x3014) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_ADDR(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_ADDR(x),m,v,HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_IN(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x) ((x) + 0x3018) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x) ((x) + 0x3018) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OFFS (0x3018) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x)) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x),m,v,HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x) ((x) + 0x301c) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x) ((x) + 0x301c) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OFFS (0x301c) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x)) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x),m,v,HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) ((x) + 0x3020) +#define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x) ((x) + 0x3020) +#define HWIO_REO_R2_REO_CMD_RING_HP_OFFS (0x3020) +#define HWIO_REO_R2_REO_CMD_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_REO_CMD_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO_CMD_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_CMD_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO_CMD_RING_HP_IN(x)) +#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x) ((x) + 0x3024) +#define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x) ((x) + 0x3024) +#define HWIO_REO_R2_REO_CMD_RING_TP_OFFS (0x3024) +#define HWIO_REO_R2_REO_CMD_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_REO_CMD_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO_CMD_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_CMD_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO_CMD_RING_TP_IN(x)) +#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028) +#define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x) ((x) + 0x3028) +#define HWIO_REO_R2_SW2REO_RING_HP_OFFS (0x3028) +#define HWIO_REO_R2_SW2REO_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x)) +#define HWIO_REO_R2_SW2REO_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2REO_RING_HP_IN(x)) +#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x) ((x) + 0x302c) +#define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x) ((x) + 0x302c) +#define HWIO_REO_R2_SW2REO_RING_TP_OFFS (0x302c) +#define HWIO_REO_R2_SW2REO_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x)) +#define HWIO_REO_R2_SW2REO_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2REO_RING_TP_IN(x)) +#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x) ((x) + 0x3030) +#define HWIO_REO_R2_SW2REO1_RING_HP_PHYS(x) ((x) + 0x3030) +#define HWIO_REO_R2_SW2REO1_RING_HP_OFFS (0x3030) +#define HWIO_REO_R2_SW2REO1_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO1_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO1_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO1_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x)) +#define HWIO_REO_R2_SW2REO1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO1_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2REO1_RING_HP_IN(x)) +#define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x) ((x) + 0x3034) +#define HWIO_REO_R2_SW2REO1_RING_TP_PHYS(x) ((x) + 0x3034) +#define HWIO_REO_R2_SW2REO1_RING_TP_OFFS (0x3034) +#define HWIO_REO_R2_SW2REO1_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO1_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO1_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO1_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x)) +#define HWIO_REO_R2_SW2REO1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO1_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2REO1_RING_TP_IN(x)) +#define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3048) +#define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x) ((x) + 0x3048) +#define HWIO_REO_R2_REO2SW1_RING_HP_OFFS (0x3048) +#define HWIO_REO_R2_REO2SW1_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW1_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW1_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW1_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x304c) +#define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x) ((x) + 0x304c) +#define HWIO_REO_R2_REO2SW1_RING_TP_OFFS (0x304c) +#define HWIO_REO_R2_REO2SW1_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW1_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW1_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW1_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3050) +#define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x) ((x) + 0x3050) +#define HWIO_REO_R2_REO2SW2_RING_HP_OFFS (0x3050) +#define HWIO_REO_R2_REO2SW2_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW2_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW2_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW2_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x) ((x) + 0x3054) +#define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x) ((x) + 0x3054) +#define HWIO_REO_R2_REO2SW2_RING_TP_OFFS (0x3054) +#define HWIO_REO_R2_REO2SW2_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW2_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW2_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW2_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x) ((x) + 0x3058) +#define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x) ((x) + 0x3058) +#define HWIO_REO_R2_REO2SW3_RING_HP_OFFS (0x3058) +#define HWIO_REO_R2_REO2SW3_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW3_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW3_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW3_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW3_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x) ((x) + 0x305c) +#define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x) ((x) + 0x305c) +#define HWIO_REO_R2_REO2SW3_RING_TP_OFFS (0x305c) +#define HWIO_REO_R2_REO2SW3_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW3_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW3_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW3_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW3_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x) ((x) + 0x3060) +#define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x) ((x) + 0x3060) +#define HWIO_REO_R2_REO2SW4_RING_HP_OFFS (0x3060) +#define HWIO_REO_R2_REO2SW4_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW4_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW4_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW4_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW4_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x) ((x) + 0x3064) +#define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x) ((x) + 0x3064) +#define HWIO_REO_R2_REO2SW4_RING_TP_OFFS (0x3064) +#define HWIO_REO_R2_REO2SW4_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW4_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW4_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW4_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW4_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x) ((x) + 0x3068) +#define HWIO_REO_R2_REO2SW5_RING_HP_PHYS(x) ((x) + 0x3068) +#define HWIO_REO_R2_REO2SW5_RING_HP_OFFS (0x3068) +#define HWIO_REO_R2_REO2SW5_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW5_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW5_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW5_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW5_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW5_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW5_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW5_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW5_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW5_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW5_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x) ((x) + 0x306c) +#define HWIO_REO_R2_REO2SW5_RING_TP_PHYS(x) ((x) + 0x306c) +#define HWIO_REO_R2_REO2SW5_RING_TP_OFFS (0x306c) +#define HWIO_REO_R2_REO2SW5_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW5_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW5_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW5_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW5_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW5_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW5_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW5_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW5_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW5_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW5_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x) ((x) + 0x3070) +#define HWIO_REO_R2_REO2SW6_RING_HP_PHYS(x) ((x) + 0x3070) +#define HWIO_REO_R2_REO2SW6_RING_HP_OFFS (0x3070) +#define HWIO_REO_R2_REO2SW6_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW6_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW6_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW6_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW6_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW6_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW6_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW6_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW6_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW6_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW6_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x) ((x) + 0x3074) +#define HWIO_REO_R2_REO2SW6_RING_TP_PHYS(x) ((x) + 0x3074) +#define HWIO_REO_R2_REO2SW6_RING_TP_OFFS (0x3074) +#define HWIO_REO_R2_REO2SW6_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW6_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW6_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW6_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW6_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW6_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW6_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW6_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW6_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW6_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW6_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x3088) +#define HWIO_REO_R2_REO2SW0_RING_HP_PHYS(x) ((x) + 0x3088) +#define HWIO_REO_R2_REO2SW0_RING_HP_OFFS (0x3088) +#define HWIO_REO_R2_REO2SW0_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW0_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW0_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW0_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW0_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW0_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW0_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW0_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW0_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW0_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW0_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x) ((x) + 0x308c) +#define HWIO_REO_R2_REO2SW0_RING_TP_PHYS(x) ((x) + 0x308c) +#define HWIO_REO_R2_REO2SW0_RING_TP_OFFS (0x308c) +#define HWIO_REO_R2_REO2SW0_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW0_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW0_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW0_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW0_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW0_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW0_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW0_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW0_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW0_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW0_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x) ((x) + 0x3090) +#define HWIO_REO_R2_REO2PPE_RING_HP_PHYS(x) ((x) + 0x3090) +#define HWIO_REO_R2_REO2PPE_RING_HP_OFFS (0x3090) +#define HWIO_REO_R2_REO2PPE_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2PPE_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2PPE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2PPE_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2PPE_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2PPE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2PPE_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2PPE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2PPE_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2PPE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2PPE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x) ((x) + 0x3094) +#define HWIO_REO_R2_REO2PPE_RING_TP_PHYS(x) ((x) + 0x3094) +#define HWIO_REO_R2_REO2PPE_RING_TP_OFFS (0x3094) +#define HWIO_REO_R2_REO2PPE_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2PPE_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2PPE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2PPE_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2PPE_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2PPE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2PPE_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2PPE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2PPE_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2PPE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2PPE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x) ((x) + 0x3098) +#define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x) ((x) + 0x3098) +#define HWIO_REO_R2_REO2FW_RING_HP_OFFS (0x3098) +#define HWIO_REO_R2_REO2FW_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2FW_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2FW_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2FW_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2FW_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2FW_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x) ((x) + 0x309c) +#define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x) ((x) + 0x309c) +#define HWIO_REO_R2_REO2FW_RING_TP_OFFS (0x309c) +#define HWIO_REO_R2_REO2FW_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2FW_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2FW_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2FW_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2FW_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2FW_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x) ((x) + 0x30a0) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x) ((x) + 0x30a0) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_OFFS (0x30a0) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_REO_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x) ((x) + 0x30a4) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x) ((x) + 0x30a4) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_OFFS (0x30a4) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_REO_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) ((x) + 0x30a8) +#define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x) ((x) + 0x30a8) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OFFS (0x30a8) +#define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)) +#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x) ((x) + 0x30ac) +#define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x) ((x) + 0x30ac) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OFFS (0x30ac) +#define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)) +#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: TQM_REG + *--------------------------------------------------------------------------*/ + +#define TQM_REG_REG_BASE (UMAC_BASE + 0x0003c000) +#define TQM_REG_REG_BASE_SIZE 0x4000 +#define TQM_REG_REG_BASE_USED 0x305c +#define TQM_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x0003c000) +#define TQM_REG_REG_BASE_OFFS 0x0003c000 + +#define HWIO_TQM_R0_CONTROL_ADDR(x) ((x) + 0x0) +#define HWIO_TQM_R0_CONTROL_PHYS(x) ((x) + 0x0) +#define HWIO_TQM_R0_CONTROL_OFFS (0x0) +#define HWIO_TQM_R0_CONTROL_RMSK 0x1b +#define HWIO_TQM_R0_CONTROL_POR 0x00000012 +#define HWIO_TQM_R0_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CONTROL_ATTR 0x3 +#define HWIO_TQM_R0_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R0_CONTROL_ADDR(x)) +#define HWIO_TQM_R0_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CONTROL_ADDR(x), m) +#define HWIO_TQM_R0_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CONTROL_ADDR(x),v) +#define HWIO_TQM_R0_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_CONTROL_IN(x)) +#define HWIO_TQM_R0_CONTROL_INIT_PREFETCH_BUFFER_PTRS_BMSK 0x10 +#define HWIO_TQM_R0_CONTROL_INIT_PREFETCH_BUFFER_PTRS_SHFT 4 +#define HWIO_TQM_R0_CONTROL_BLOCK_PREFETCH_BMSK 0x8 +#define HWIO_TQM_R0_CONTROL_BLOCK_PREFETCH_SHFT 3 +#define HWIO_TQM_R0_CONTROL_CONCURRENT_PROC_BMSK 0x2 +#define HWIO_TQM_R0_CONTROL_CONCURRENT_PROC_SHFT 1 +#define HWIO_TQM_R0_CONTROL_ENABLE_BMSK 0x1 +#define HWIO_TQM_R0_CONTROL_ENABLE_SHFT 0 + +#define HWIO_TQM_R0_PAUSE_CONTROL_ADDR(x) ((x) + 0x4) +#define HWIO_TQM_R0_PAUSE_CONTROL_PHYS(x) ((x) + 0x4) +#define HWIO_TQM_R0_PAUSE_CONTROL_OFFS (0x4) +#define HWIO_TQM_R0_PAUSE_CONTROL_RMSK 0x7 +#define HWIO_TQM_R0_PAUSE_CONTROL_POR 0x00000003 +#define HWIO_TQM_R0_PAUSE_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PAUSE_CONTROL_ATTR 0x3 +#define HWIO_TQM_R0_PAUSE_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R0_PAUSE_CONTROL_ADDR(x)) +#define HWIO_TQM_R0_PAUSE_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PAUSE_CONTROL_ADDR(x), m) +#define HWIO_TQM_R0_PAUSE_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PAUSE_CONTROL_ADDR(x),v) +#define HWIO_TQM_R0_PAUSE_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PAUSE_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_PAUSE_CONTROL_IN(x)) +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_MPDU_BMSK 0x4 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_MPDU_SHFT 2 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HWSCH_CMD_BMSK 0x2 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HWSCH_CMD_SHFT 1 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_SW_CMD_BMSK 0x1 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_SW_CMD_SHFT 0 + +#define HWIO_TQM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x8) +#define HWIO_TQM_R0_MISC_CONTROL_PHYS(x) ((x) + 0x8) +#define HWIO_TQM_R0_MISC_CONTROL_OFFS (0x8) +#define HWIO_TQM_R0_MISC_CONTROL_RMSK 0x3ff +#define HWIO_TQM_R0_MISC_CONTROL_POR 0x00000010 +#define HWIO_TQM_R0_MISC_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MISC_CONTROL_ATTR 0x3 +#define HWIO_TQM_R0_MISC_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R0_MISC_CONTROL_ADDR(x)) +#define HWIO_TQM_R0_MISC_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MISC_CONTROL_ADDR(x), m) +#define HWIO_TQM_R0_MISC_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MISC_CONTROL_ADDR(x),v) +#define HWIO_TQM_R0_MISC_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MISC_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_MISC_CONTROL_IN(x)) +#define HWIO_TQM_R0_MISC_CONTROL_GEN_ACKED_MPDU_INFO_END_BMSK 0x200 +#define HWIO_TQM_R0_MISC_CONTROL_GEN_ACKED_MPDU_INFO_END_SHFT 9 +#define HWIO_TQM_R0_MISC_CONTROL_RETAIN_CACHE_BMSK 0x100 +#define HWIO_TQM_R0_MISC_CONTROL_RETAIN_CACHE_SHFT 8 +#define HWIO_TQM_R0_MISC_CONTROL_FLUSH_IDLE_COUNT_BMSK 0xff +#define HWIO_TQM_R0_MISC_CONTROL_FLUSH_IDLE_COUNT_SHFT 0 + +#define HWIO_TQM_R0_LINK_0_ADDR(x) ((x) + 0xc) +#define HWIO_TQM_R0_LINK_0_PHYS(x) ((x) + 0xc) +#define HWIO_TQM_R0_LINK_0_OFFS (0xc) +#define HWIO_TQM_R0_LINK_0_RMSK 0x3f +#define HWIO_TQM_R0_LINK_0_POR 0x00000000 +#define HWIO_TQM_R0_LINK_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_0_ATTR 0x3 +#define HWIO_TQM_R0_LINK_0_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_0_ADDR(x)) +#define HWIO_TQM_R0_LINK_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_0_ADDR(x), m) +#define HWIO_TQM_R0_LINK_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_0_ADDR(x),v) +#define HWIO_TQM_R0_LINK_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_0_ADDR(x),m,v,HWIO_TQM_R0_LINK_0_IN(x)) +#define HWIO_TQM_R0_LINK_0_SESSION_ID_BMSK 0x3f +#define HWIO_TQM_R0_LINK_0_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_1_ADDR(x) ((x) + 0x10) +#define HWIO_TQM_R0_LINK_1_PHYS(x) ((x) + 0x10) +#define HWIO_TQM_R0_LINK_1_OFFS (0x10) +#define HWIO_TQM_R0_LINK_1_RMSK 0x3f +#define HWIO_TQM_R0_LINK_1_POR 0x00000000 +#define HWIO_TQM_R0_LINK_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_1_ATTR 0x3 +#define HWIO_TQM_R0_LINK_1_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_1_ADDR(x)) +#define HWIO_TQM_R0_LINK_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_1_ADDR(x), m) +#define HWIO_TQM_R0_LINK_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_1_ADDR(x),v) +#define HWIO_TQM_R0_LINK_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_1_ADDR(x),m,v,HWIO_TQM_R0_LINK_1_IN(x)) +#define HWIO_TQM_R0_LINK_1_SESSION_ID_BMSK 0x3f +#define HWIO_TQM_R0_LINK_1_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_A_ADDR(x) ((x) + 0x14) +#define HWIO_TQM_R0_LINK_A_PHYS(x) ((x) + 0x14) +#define HWIO_TQM_R0_LINK_A_OFFS (0x14) +#define HWIO_TQM_R0_LINK_A_RMSK 0xff +#define HWIO_TQM_R0_LINK_A_POR 0x00000000 +#define HWIO_TQM_R0_LINK_A_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_A_ATTR 0x3 +#define HWIO_TQM_R0_LINK_A_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_A_ADDR(x)) +#define HWIO_TQM_R0_LINK_A_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_A_ADDR(x), m) +#define HWIO_TQM_R0_LINK_A_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_A_ADDR(x),v) +#define HWIO_TQM_R0_LINK_A_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_A_ADDR(x),m,v,HWIO_TQM_R0_LINK_A_IN(x)) +#define HWIO_TQM_R0_LINK_A_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_A_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_B_ADDR(x) ((x) + 0x18) +#define HWIO_TQM_R0_LINK_B_PHYS(x) ((x) + 0x18) +#define HWIO_TQM_R0_LINK_B_OFFS (0x18) +#define HWIO_TQM_R0_LINK_B_RMSK 0xff +#define HWIO_TQM_R0_LINK_B_POR 0x00000000 +#define HWIO_TQM_R0_LINK_B_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_B_ATTR 0x3 +#define HWIO_TQM_R0_LINK_B_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_B_ADDR(x)) +#define HWIO_TQM_R0_LINK_B_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_B_ADDR(x), m) +#define HWIO_TQM_R0_LINK_B_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_B_ADDR(x),v) +#define HWIO_TQM_R0_LINK_B_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_B_ADDR(x),m,v,HWIO_TQM_R0_LINK_B_IN(x)) +#define HWIO_TQM_R0_LINK_B_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_B_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_C_ADDR(x) ((x) + 0x1c) +#define HWIO_TQM_R0_LINK_C_PHYS(x) ((x) + 0x1c) +#define HWIO_TQM_R0_LINK_C_OFFS (0x1c) +#define HWIO_TQM_R0_LINK_C_RMSK 0xff +#define HWIO_TQM_R0_LINK_C_POR 0x00000000 +#define HWIO_TQM_R0_LINK_C_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_C_ATTR 0x3 +#define HWIO_TQM_R0_LINK_C_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_C_ADDR(x)) +#define HWIO_TQM_R0_LINK_C_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_C_ADDR(x), m) +#define HWIO_TQM_R0_LINK_C_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_C_ADDR(x),v) +#define HWIO_TQM_R0_LINK_C_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_C_ADDR(x),m,v,HWIO_TQM_R0_LINK_C_IN(x)) +#define HWIO_TQM_R0_LINK_C_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_C_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_D_ADDR(x) ((x) + 0x20) +#define HWIO_TQM_R0_LINK_D_PHYS(x) ((x) + 0x20) +#define HWIO_TQM_R0_LINK_D_OFFS (0x20) +#define HWIO_TQM_R0_LINK_D_RMSK 0xff +#define HWIO_TQM_R0_LINK_D_POR 0x00000000 +#define HWIO_TQM_R0_LINK_D_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_D_ATTR 0x3 +#define HWIO_TQM_R0_LINK_D_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_D_ADDR(x)) +#define HWIO_TQM_R0_LINK_D_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_D_ADDR(x), m) +#define HWIO_TQM_R0_LINK_D_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_D_ADDR(x),v) +#define HWIO_TQM_R0_LINK_D_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_D_ADDR(x),m,v,HWIO_TQM_R0_LINK_D_IN(x)) +#define HWIO_TQM_R0_LINK_D_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_D_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_E_ADDR(x) ((x) + 0x24) +#define HWIO_TQM_R0_LINK_E_PHYS(x) ((x) + 0x24) +#define HWIO_TQM_R0_LINK_E_OFFS (0x24) +#define HWIO_TQM_R0_LINK_E_RMSK 0xff +#define HWIO_TQM_R0_LINK_E_POR 0x00000000 +#define HWIO_TQM_R0_LINK_E_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_E_ATTR 0x3 +#define HWIO_TQM_R0_LINK_E_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_E_ADDR(x)) +#define HWIO_TQM_R0_LINK_E_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_E_ADDR(x), m) +#define HWIO_TQM_R0_LINK_E_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_E_ADDR(x),v) +#define HWIO_TQM_R0_LINK_E_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_E_ADDR(x),m,v,HWIO_TQM_R0_LINK_E_IN(x)) +#define HWIO_TQM_R0_LINK_E_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_E_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_F_ADDR(x) ((x) + 0x28) +#define HWIO_TQM_R0_LINK_F_PHYS(x) ((x) + 0x28) +#define HWIO_TQM_R0_LINK_F_OFFS (0x28) +#define HWIO_TQM_R0_LINK_F_RMSK 0xff +#define HWIO_TQM_R0_LINK_F_POR 0x00000000 +#define HWIO_TQM_R0_LINK_F_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_F_ATTR 0x3 +#define HWIO_TQM_R0_LINK_F_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_F_ADDR(x)) +#define HWIO_TQM_R0_LINK_F_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_F_ADDR(x), m) +#define HWIO_TQM_R0_LINK_F_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_F_ADDR(x),v) +#define HWIO_TQM_R0_LINK_F_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_F_ADDR(x),m,v,HWIO_TQM_R0_LINK_F_IN(x)) +#define HWIO_TQM_R0_LINK_F_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_F_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_G_ADDR(x) ((x) + 0x2c) +#define HWIO_TQM_R0_LINK_G_PHYS(x) ((x) + 0x2c) +#define HWIO_TQM_R0_LINK_G_OFFS (0x2c) +#define HWIO_TQM_R0_LINK_G_RMSK 0xff +#define HWIO_TQM_R0_LINK_G_POR 0x00000000 +#define HWIO_TQM_R0_LINK_G_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_G_ATTR 0x3 +#define HWIO_TQM_R0_LINK_G_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_G_ADDR(x)) +#define HWIO_TQM_R0_LINK_G_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_G_ADDR(x), m) +#define HWIO_TQM_R0_LINK_G_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_G_ADDR(x),v) +#define HWIO_TQM_R0_LINK_G_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_G_ADDR(x),m,v,HWIO_TQM_R0_LINK_G_IN(x)) +#define HWIO_TQM_R0_LINK_G_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_G_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ADDR(x) ((x) + 0x30) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_PHYS(x) ((x) + 0x30) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_OFFS (0x30) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_RMSK 0x3ff +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_POR 0x0000000a +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ATTR 0x3 +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ADDR(x)) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ADDR(x), m) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ADDR(x),v) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_IN(x)) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ENABLE_PREFETCH_BMSK 0x200 +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ENABLE_PREFETCH_SHFT 9 +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_CMD_EXECUTION_TIME_VALID_BMSK 0x100 +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_CMD_EXECUTION_TIME_VALID_SHFT 8 +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_MAX_CMD_EXECUTION_TIME_BMSK 0xff +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_MAX_CMD_EXECUTION_TIME_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) ((x) + 0x34) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) ((x) + 0x34) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_OFFS (0x34) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) ((x) + 0x38) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) ((x) + 0x38) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_OFFS (0x38) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_ID_ADDR(x) ((x) + 0x3c) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_PHYS(x) ((x) + 0x3c) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_OFFS (0x3c) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_TCL2TQM_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_ID_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_ADDR(x) ((x) + 0x40) +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_PHYS(x) ((x) + 0x40) +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_OFFS (0x40) +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_ADDR(x) ((x) + 0x44) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_PHYS(x) ((x) + 0x44) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_OFFS (0x44) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x50) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x50) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_OFFS (0x50) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x54) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x54) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_OFFS (0x54) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x64) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x64) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x64) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x68) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x68) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x68) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x6c) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x6c) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_OFFS (0x6c) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x70) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x70) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x70) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x74) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x74) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x74) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x78) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x78) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x78) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x7c) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x7c) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_OFFS (0x7c) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x80) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x80) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_OFFS (0x80) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x) ((x) + 0x84) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_PHYS(x) ((x) + 0x84) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_OFFS (0x84) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa4) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa4) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OFFS (0xa4) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_ADDR(x) ((x) + 0xa8) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_PHYS(x) ((x) + 0xa8) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_OFFS (0xa8) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_ADDR(x) ((x) + 0xac) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_PHYS(x) ((x) + 0xac) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_OFFS (0xac) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_ADDR(x) ((x) + 0xb0) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_PHYS(x) ((x) + 0xb0) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_OFFS (0xb0) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_ID_ADDR(x) ((x) + 0xb4) +#define HWIO_TQM_R0_FW2TQM_RING_ID_PHYS(x) ((x) + 0xb4) +#define HWIO_TQM_R0_FW2TQM_RING_ID_OFFS (0xb4) +#define HWIO_TQM_R0_FW2TQM_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_FW2TQM_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_ID_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_FW2TQM_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_ADDR(x) ((x) + 0xb8) +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_PHYS(x) ((x) + 0xb8) +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_OFFS (0xb8) +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_MISC_ADDR(x) ((x) + 0xbc) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_PHYS(x) ((x) + 0xbc) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_OFFS (0xbc) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_FW2TQM_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_MISC_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xc8) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xc8) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_OFFS (0xc8) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xcc) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xcc) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_OFFS (0xcc) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xdc) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xdc) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xdc) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xe0) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xe0) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xe0) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xe4) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xe4) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_OFFS (0xe4) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xe8) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xe8) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xe8) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xec) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xec) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xec) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xf0) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xf0) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xf0) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xf4) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xf4) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_OFFS (0xf4) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xf8) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xf8) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_OFFS (0xf8) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_ADDR(x) ((x) + 0xfc) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_PHYS(x) ((x) + 0xfc) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_OFFS (0xfc) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x11c) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x11c) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_OFFS (0x11c) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_ADDR(x) ((x) + 0x120) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_PHYS(x) ((x) + 0x120) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_OFFS (0x120) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_ADDR(x) ((x) + 0x124) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_PHYS(x) ((x) + 0x124) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_OFFS (0x124) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_ADDR(x) ((x) + 0x128) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_PHYS(x) ((x) + 0x128) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_OFFS (0x128) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_ID_ADDR(x) ((x) + 0x12c) +#define HWIO_TQM_R0_SW_CMD_RING_ID_PHYS(x) ((x) + 0x12c) +#define HWIO_TQM_R0_SW_CMD_RING_ID_OFFS (0x12c) +#define HWIO_TQM_R0_SW_CMD_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_SW_CMD_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_ID_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_ADDR(x) ((x) + 0x130) +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_PHYS(x) ((x) + 0x130) +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_OFFS (0x130) +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_MISC_ADDR(x) ((x) + 0x134) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_PHYS(x) ((x) + 0x134) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_OFFS (0x134) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_SW_CMD_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_MISC_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x140) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x140) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_OFFS (0x140) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x144) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x144) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_OFFS (0x144) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x154) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x154) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x154) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x158) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x158) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x158) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x15c) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x15c) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_OFFS (0x15c) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x160) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x160) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x160) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x164) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x164) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x164) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x168) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x168) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x168) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x16c) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x16c) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_OFFS (0x16c) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x170) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x170) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_OFFS (0x170) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_ADDR(x) ((x) + 0x174) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_PHYS(x) ((x) + 0x174) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_OFFS (0x174) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x194) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x194) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_OFFS (0x194) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_ADDR(x) ((x) + 0x198) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_PHYS(x) ((x) + 0x198) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_OFFS (0x198) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_ADDR(x) ((x) + 0x19c) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_PHYS(x) ((x) + 0x19c) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_OFFS (0x19c) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_ADDR(x) ((x) + 0x1a0) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_PHYS(x) ((x) + 0x1a0) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_OFFS (0x1a0) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_ID_ADDR(x) ((x) + 0x1a4) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_PHYS(x) ((x) + 0x1a4) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_OFFS (0x1a4) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_SW_CMD1_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_ID_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_ADDR(x) ((x) + 0x1a8) +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_PHYS(x) ((x) + 0x1a8) +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_OFFS (0x1a8) +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_ADDR(x) ((x) + 0x1ac) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_PHYS(x) ((x) + 0x1ac) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_OFFS (0x1ac) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_MISC_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1b8) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1b8) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_OFFS (0x1b8) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x1bc) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x1bc) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_OFFS (0x1bc) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x1cc) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x1cc) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x1cc) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x1d0) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x1d0) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x1d0) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x1d4) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x1d4) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_OFFS (0x1d4) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x1d8) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x1d8) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x1d8) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x1dc) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x1dc) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x1dc) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x1e0) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x1e0) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x1e0) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1e4) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1e4) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_OFFS (0x1e4) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1e8) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1e8) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_OFFS (0x1e8) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_ADDR(x) ((x) + 0x1ec) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_PHYS(x) ((x) + 0x1ec) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_OFFS (0x1ec) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x20c) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x20c) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_OFFS (0x20c) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_ADDR(x) ((x) + 0x210) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_PHYS(x) ((x) + 0x210) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_OFFS (0x210) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0x214) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0x214) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_OFFS (0x214) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0x218) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0x218) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_OFFS (0x218) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ADDR(x) ((x) + 0x21c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_PHYS(x) ((x) + 0x21c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_OFFS (0x21c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x) ((x) + 0x220) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_PHYS(x) ((x) + 0x220) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_OFFS (0x220) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x) ((x) + 0x224) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_PHYS(x) ((x) + 0x224) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_OFFS (0x224) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x230) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x230) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_OFFS (0x230) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x234) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x234) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_OFFS (0x234) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x244) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x244) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x244) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x248) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x248) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x248) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x24c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x24c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_OFFS (0x24c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x250) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x250) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x250) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x254) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x254) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x254) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x258) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x258) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x258) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x25c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x25c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OFFS (0x25c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x260) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x260) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OFFS (0x260) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x) ((x) + 0x264) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_PHYS(x) ((x) + 0x264) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OFFS (0x264) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x284) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x284) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OFFS (0x284) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x) ((x) + 0x288) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_PHYS(x) ((x) + 0x288) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_OFFS (0x288) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x28c) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x28c) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_OFFS (0x28c) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x290) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x290) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_OFFS (0x290) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_ADDR(x) ((x) + 0x294) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_PHYS(x) ((x) + 0x294) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_OFFS (0x294) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x298) +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x298) +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_OFFS (0x298) +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADDR(x) ((x) + 0x29c) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_PHYS(x) ((x) + 0x29c) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_OFFS (0x29c) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x2a0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x2a0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_OFFS (0x2a0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x2a4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x2a4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_OFFS (0x2a4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x2b0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x2b0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x2b0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x2b4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x2b4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x2b4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x2b8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x2b8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x2b8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x2d4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x2d4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x2d4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x2d8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x2d8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x2d8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x2dc) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x2dc) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_OFFS (0x2dc) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x2e0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x2e0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x2e0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x2e4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x2e4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x2e4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x2e8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x2e8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x2e8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x2ec) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x2ec) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_OFFS (0x2ec) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x2fc) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x2fc) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x2fc) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x300) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x300) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_OFFS (0x300) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x304) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x304) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_OFFS (0x304) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x308) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x308) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_OFFS (0x308) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_ADDR(x) ((x) + 0x30c) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_PHYS(x) ((x) + 0x30c) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_OFFS (0x30c) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_RMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_ADDR(x) ((x) + 0x310) +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_PHYS(x) ((x) + 0x310) +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_OFFS (0x310) +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADDR(x) ((x) + 0x314) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_PHYS(x) ((x) + 0x314) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_OFFS (0x314) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_RMSK 0x7ffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x318) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x318) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_OFFS (0x318) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x31c) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x31c) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_OFFS (0x31c) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x328) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x328) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x328) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x32c) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x32c) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x32c) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x330) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x330) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x330) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x34c) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x34c) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_OFFS (0x34c) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x350) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x350) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_OFFS (0x350) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x354) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x354) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_OFFS (0x354) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x358) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x358) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_OFFS (0x358) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x35c) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x35c) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_OFFS (0x35c) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x360) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x360) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_OFFS (0x360) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_ADDR(x) ((x) + 0x364) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_PHYS(x) ((x) + 0x364) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_OFFS (0x364) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x374) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x374) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x374) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_ADDR(x) ((x) + 0x378) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_PHYS(x) ((x) + 0x378) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_OFFS (0x378) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_ADDR(x) ((x) + 0x37c) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_PHYS(x) ((x) + 0x37c) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_OFFS (0x37c) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_ADDR(x) ((x) + 0x380) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_PHYS(x) ((x) + 0x380) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_OFFS (0x380) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_ADDR(x) ((x) + 0x384) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_PHYS(x) ((x) + 0x384) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_OFFS (0x384) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_RMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_RING_ID_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_ADDR(x) ((x) + 0x388) +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_PHYS(x) ((x) + 0x388) +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_OFFS (0x388) +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADDR(x) ((x) + 0x38c) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_PHYS(x) ((x) + 0x38c) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_OFFS (0x38c) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_RMSK 0x7ffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x390) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x390) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_OFFS (0x390) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x394) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x394) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_OFFS (0x394) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x3a0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x3a0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_OFFS (0x3a0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x3a4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x3a4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_OFFS (0x3a4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x3a8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x3a8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_OFFS (0x3a8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x3c4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x3c4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_OFFS (0x3c4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x3c8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x3c8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_OFFS (0x3c8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_ADDR(x) ((x) + 0x3cc) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_PHYS(x) ((x) + 0x3cc) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_OFFS (0x3cc) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x3d0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x3d0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_OFFS (0x3d0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x3d4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x3d4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_OFFS (0x3d4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x3d8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x3d8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_OFFS (0x3d8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_ADDR(x) ((x) + 0x3dc) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_PHYS(x) ((x) + 0x3dc) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_OFFS (0x3dc) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x3ec) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x3ec) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_OFFS (0x3ec) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_ADDR(x) ((x) + 0x3f0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_PHYS(x) ((x) + 0x3f0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_OFFS (0x3f0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_ADDR(x) ((x) + 0x3f4) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_PHYS(x) ((x) + 0x3f4) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_OFFS (0x3f4) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_RMSK 0xffffffff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_POR 0x008609ff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_ATTR 0x3 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_IN(x) \ + in_dword(HWIO_TQM_R0_CACHE_CTL_CONFIG_ADDR(x)) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CACHE_CTL_CONFIG_ADDR(x), m) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CACHE_CTL_CONFIG_ADDR(x),v) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTL_CONFIG_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTL_CONFIG_IN(x)) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_BMSK 0xff000000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_SHFT 24 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_BMSK 0x800000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_SHFT 23 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x400000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 22 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x200000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 21 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x100000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 20 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x80000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 19 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x40000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 18 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x20000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 17 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x1fe00 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 9 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x1ff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0 + +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_ADDR(x) ((x) + 0x3f8) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_PHYS(x) ((x) + 0x3f8) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_OFFS (0x3f8) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_RMSK 0x3 +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_POR 0x00000000 +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_ATTR 0x3 +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R0_CACHE_CTL_CONTROL_ADDR(x)) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CACHE_CTL_CONTROL_ADDR(x), m) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CACHE_CTL_CONTROL_ADDR(x),v) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTL_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTL_CONTROL_IN(x)) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_BMSK 0x2 +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_SHFT 1 +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x1 +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0 + +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_ADDR(x) ((x) + 0x3fc) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_PHYS(x) ((x) + 0x3fc) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_OFFS (0x3fc) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_RMSK 0x1ffffff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_POR 0x00000000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_ATTR 0x3 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_IN(x) \ + in_dword(HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_ADDR(x)) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_ADDR(x), m) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_ADDR(x),v) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_IN(x)) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_BMSK 0x1ffffff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_SHFT 0 + +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_ADDR(x) ((x) + 0x400) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_PHYS(x) ((x) + 0x400) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_OFFS (0x400) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_RMSK 0x3ff +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_POR 0x000000f0 +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_ATTR 0x3 +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_IN(x) \ + in_dword(HWIO_TQM_R0_CACHE_CTL_SET_SIZE_ADDR(x)) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CACHE_CTL_SET_SIZE_ADDR(x), m) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CACHE_CTL_SET_SIZE_ADDR(x),v) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTL_SET_SIZE_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTL_SET_SIZE_IN(x)) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_BMSK 0x3ff +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_SHFT 0 + +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x) ((x) + 0x404) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_PHYS(x) ((x) + 0x404) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_OFFS (0x404) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_RMSK 0x7 +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_POR 0x00000002 +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_ATTR 0x3 +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_IN(x) \ + in_dword(HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x)) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x), m) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x),v) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_IN(x)) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_VC_ID_BMSK 0x4 +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_VC_ID_SHFT 2 +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_GXI_PRIORITY_BMSK 0x3 +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_GXI_PRIORITY_SHFT 0 + +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ADDR(x) ((x) + 0x408) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_PHYS(x) ((x) + 0x408) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_OFFS (0x408) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_RMSK 0xffffffff +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_POR 0x10041c10 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ATTR 0x3 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_IN(x) \ + in_dword(HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ADDR(x)) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ADDR(x), m) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ADDR(x),v) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ADDR(x),m,v,HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_IN(x)) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_MIN_READ_SIZE_BMSK 0xff000000 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_MIN_READ_SIZE_SHFT 24 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_DESC_THRESHOLD_BMSK 0xff0000 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_DESC_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_CMD_THRESHOLD_BMSK 0xff00 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_CMD_THRESHOLD_SHFT 8 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ENTRANCE_THRESHOLD_BMSK 0xff +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ENTRANCE_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_ADDR(x) ((x) + 0x40c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_PHYS(x) ((x) + 0x40c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_OFFS (0x40c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_POR 0x002f0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_SW_CMD_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_SW_CMD_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_SW_CMD_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_SW_CMD_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_ADDR(x) ((x) + 0x410) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_PHYS(x) ((x) + 0x410) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_OFFS (0x410) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_POR 0x008b0030 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_HWSCH_CMD1_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_HWSCH_CMD1_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_HWSCH_CMD1_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_HWSCH_CMD1_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_ADDR(x) ((x) + 0x414) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_PHYS(x) ((x) + 0x414) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_OFFS (0x414) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_POR 0x00bb008c +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_MSDU_ENTRANCE1_CMD_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_MSDU_ENTRANCE1_CMD_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_MSDU_ENTRANCE1_CMD_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_MSDU_ENTRANCE1_CMD_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_ADDR(x) ((x) + 0x418) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_PHYS(x) ((x) + 0x418) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_OFFS (0x418) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_POR 0x00d300bc +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_DESC_PTRS_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_DESC_PTRS_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_DESC_PTRS_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_DESC_PTRS_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_ADDR(x) ((x) + 0x41c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_PHYS(x) ((x) + 0x41c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_OFFS (0x41c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_POR 0x012f00d4 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_HWSCH_CMD2_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_HWSCH_CMD2_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_HWSCH_CMD2_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_HWSCH_CMD2_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_ADDR(x) ((x) + 0x420) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_PHYS(x) ((x) + 0x420) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_OFFS (0x420) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_POR 0x015f0130 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_MSDU_ENTRANCE3_CMD_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_MSDU_ENTRANCE3_CMD_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_MSDU_ENTRANCE3_CMD_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_MSDU_ENTRANCE3_CMD_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_ADDR(x) ((x) + 0x424) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_PHYS(x) ((x) + 0x424) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_OFFS (0x424) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_POR 0x018f0160 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_SW_CMD1_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_SW_CMD1_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_SW_CMD1_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_SW_CMD1_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ADDR(x) ((x) + 0x428) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_PHYS(x) ((x) + 0x428) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_OFFS (0x428) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_RMSK 0x1f7f +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_POR 0x00001441 +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ATTR 0x3 +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_IN(x) \ + in_dword(HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ADDR(x)) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ADDR(x), m) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_OUT(x, v) \ + out_dword(HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ADDR(x),v) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ADDR(x),m,v,HWIO_TQM_R0_STATUS_BUFFER_PARTITION_IN(x)) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ISSUE_MULTIPLE_BMSK 0x1000 +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ISSUE_MULTIPLE_SHFT 12 +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_WAIT_THRESHOLD_BMSK 0xf00 +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_WAIT_THRESHOLD_SHFT 8 +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_STATUS0_END_ADDR_BMSK 0x7f +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_STATUS0_END_ADDR_SHFT 0 + +#define HWIO_TQM_R0_WATCHDOG_ADDR(x) ((x) + 0x42c) +#define HWIO_TQM_R0_WATCHDOG_PHYS(x) ((x) + 0x42c) +#define HWIO_TQM_R0_WATCHDOG_OFFS (0x42c) +#define HWIO_TQM_R0_WATCHDOG_RMSK 0x7fffffff +#define HWIO_TQM_R0_WATCHDOG_POR 0x00002710 +#define HWIO_TQM_R0_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WATCHDOG_ATTR 0x3 +#define HWIO_TQM_R0_WATCHDOG_IN(x) \ + in_dword(HWIO_TQM_R0_WATCHDOG_ADDR(x)) +#define HWIO_TQM_R0_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WATCHDOG_ADDR(x), m) +#define HWIO_TQM_R0_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WATCHDOG_ADDR(x),v) +#define HWIO_TQM_R0_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_IN(x)) +#define HWIO_TQM_R0_WATCHDOG_STATUS_BMSK 0x7fff0000 +#define HWIO_TQM_R0_WATCHDOG_STATUS_SHFT 16 +#define HWIO_TQM_R0_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_TQM_R0_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_TQM_R0_TESTBUS_CTRL_ADDR(x) ((x) + 0x430) +#define HWIO_TQM_R0_TESTBUS_CTRL_PHYS(x) ((x) + 0x430) +#define HWIO_TQM_R0_TESTBUS_CTRL_OFFS (0x430) +#define HWIO_TQM_R0_TESTBUS_CTRL_RMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_TQM_R0_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_TQM_R0_TESTBUS_CTRL_IN(x) \ + in_dword(HWIO_TQM_R0_TESTBUS_CTRL_ADDR(x)) +#define HWIO_TQM_R0_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_TQM_R0_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_TQM_R0_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TQM_R0_TESTBUS_CTRL_IN(x)) +#define HWIO_TQM_R0_TESTBUS_CTRL_SELECT_TQM_BMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_CTRL_SELECT_TQM_SHFT 0 + +#define HWIO_TQM_R0_TESTBUS_LOWER_ADDR(x) ((x) + 0x434) +#define HWIO_TQM_R0_TESTBUS_LOWER_PHYS(x) ((x) + 0x434) +#define HWIO_TQM_R0_TESTBUS_LOWER_OFFS (0x434) +#define HWIO_TQM_R0_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_LOWER_POR 0x00000000 +#define HWIO_TQM_R0_TESTBUS_LOWER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_LOWER_ATTR 0x1 +#define HWIO_TQM_R0_TESTBUS_LOWER_IN(x) \ + in_dword(HWIO_TQM_R0_TESTBUS_LOWER_ADDR(x)) +#define HWIO_TQM_R0_TESTBUS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TESTBUS_LOWER_ADDR(x), m) +#define HWIO_TQM_R0_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_LOWER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TESTBUS_UPPER_ADDR(x) ((x) + 0x438) +#define HWIO_TQM_R0_TESTBUS_UPPER_PHYS(x) ((x) + 0x438) +#define HWIO_TQM_R0_TESTBUS_UPPER_OFFS (0x438) +#define HWIO_TQM_R0_TESTBUS_UPPER_RMSK 0xff +#define HWIO_TQM_R0_TESTBUS_UPPER_POR 0x00000000 +#define HWIO_TQM_R0_TESTBUS_UPPER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_UPPER_ATTR 0x1 +#define HWIO_TQM_R0_TESTBUS_UPPER_IN(x) \ + in_dword(HWIO_TQM_R0_TESTBUS_UPPER_ADDR(x)) +#define HWIO_TQM_R0_TESTBUS_UPPER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TESTBUS_UPPER_ADDR(x), m) +#define HWIO_TQM_R0_TESTBUS_UPPER_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TESTBUS_UPPER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_EVENTMASK_IX_0_ADDR(x) ((x) + 0x43c) +#define HWIO_TQM_R0_EVENTMASK_IX_0_PHYS(x) ((x) + 0x43c) +#define HWIO_TQM_R0_EVENTMASK_IX_0_OFFS (0x43c) +#define HWIO_TQM_R0_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_0_POR 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_0_ATTR 0x3 +#define HWIO_TQM_R0_EVENTMASK_IX_0_IN(x) \ + in_dword(HWIO_TQM_R0_EVENTMASK_IX_0_ADDR(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_0_ADDR(x), m) +#define HWIO_TQM_R0_EVENTMASK_IX_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_EVENTMASK_IX_0_ADDR(x),v) +#define HWIO_TQM_R0_EVENTMASK_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_0_IN(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_0_MASK_SHFT 0 + +#define HWIO_TQM_R0_EVENTMASK_IX_1_ADDR(x) ((x) + 0x440) +#define HWIO_TQM_R0_EVENTMASK_IX_1_PHYS(x) ((x) + 0x440) +#define HWIO_TQM_R0_EVENTMASK_IX_1_OFFS (0x440) +#define HWIO_TQM_R0_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_1_POR 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_1_ATTR 0x3 +#define HWIO_TQM_R0_EVENTMASK_IX_1_IN(x) \ + in_dword(HWIO_TQM_R0_EVENTMASK_IX_1_ADDR(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_1_ADDR(x), m) +#define HWIO_TQM_R0_EVENTMASK_IX_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_EVENTMASK_IX_1_ADDR(x),v) +#define HWIO_TQM_R0_EVENTMASK_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_1_IN(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_1_MASK_SHFT 0 + +#define HWIO_TQM_R0_EVENTMASK_IX_2_ADDR(x) ((x) + 0x444) +#define HWIO_TQM_R0_EVENTMASK_IX_2_PHYS(x) ((x) + 0x444) +#define HWIO_TQM_R0_EVENTMASK_IX_2_OFFS (0x444) +#define HWIO_TQM_R0_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_2_POR 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_2_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_2_ATTR 0x3 +#define HWIO_TQM_R0_EVENTMASK_IX_2_IN(x) \ + in_dword(HWIO_TQM_R0_EVENTMASK_IX_2_ADDR(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_2_ADDR(x), m) +#define HWIO_TQM_R0_EVENTMASK_IX_2_OUT(x, v) \ + out_dword(HWIO_TQM_R0_EVENTMASK_IX_2_ADDR(x),v) +#define HWIO_TQM_R0_EVENTMASK_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_2_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_2_IN(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_2_MASK_SHFT 0 + +#define HWIO_TQM_R0_EVENTMASK_IX_3_ADDR(x) ((x) + 0x448) +#define HWIO_TQM_R0_EVENTMASK_IX_3_PHYS(x) ((x) + 0x448) +#define HWIO_TQM_R0_EVENTMASK_IX_3_OFFS (0x448) +#define HWIO_TQM_R0_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_3_POR 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_3_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_3_ATTR 0x3 +#define HWIO_TQM_R0_EVENTMASK_IX_3_IN(x) \ + in_dword(HWIO_TQM_R0_EVENTMASK_IX_3_ADDR(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_3_ADDR(x), m) +#define HWIO_TQM_R0_EVENTMASK_IX_3_OUT(x, v) \ + out_dword(HWIO_TQM_R0_EVENTMASK_IX_3_ADDR(x),v) +#define HWIO_TQM_R0_EVENTMASK_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_3_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_3_IN(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_3_MASK_SHFT 0 + +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x44c) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x44c) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x44c) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword(HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_IN(x)) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 17 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 2 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 1 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0 + +#define HWIO_TQM_R0_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x450) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x450) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_OFFS (0x450) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_TQM_R0_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_TQM_R0_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_TQM_R0_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_TQM_R0_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_TQM_R0_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_TQM_R0_END_OF_TEST_CHECK_IN(x)) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_TQM_R0_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_ADDR(x) ((x) + 0x454) +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_PHYS(x) ((x) + 0x454) +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_OFFS (0x454) +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_RMSK 0x1ffff +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_POR 0x00000000 +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_ATTR 0x1 +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword(HWIO_TQM_R0_INVALID_APB_ACC_ADDR_ADDR(x)) +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_INVALID_APB_ACC_ADDR_ADDR(x), m) +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_VALUE_BMSK 0x1ffff +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SM_STATES_IX0_ADDR(x) ((x) + 0x458) +#define HWIO_TQM_R0_SM_STATES_IX0_PHYS(x) ((x) + 0x458) +#define HWIO_TQM_R0_SM_STATES_IX0_OFFS (0x458) +#define HWIO_TQM_R0_SM_STATES_IX0_RMSK 0x3fffffff +#define HWIO_TQM_R0_SM_STATES_IX0_POR 0x00000000 +#define HWIO_TQM_R0_SM_STATES_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SM_STATES_IX0_ATTR 0x1 +#define HWIO_TQM_R0_SM_STATES_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_SM_STATES_IX0_ADDR(x)) +#define HWIO_TQM_R0_SM_STATES_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SM_STATES_IX0_ADDR(x), m) +#define HWIO_TQM_R0_SM_STATES_IX0_GET_QUEUE_STATS_SM_BMSK 0x3e000000 +#define HWIO_TQM_R0_SM_STATES_IX0_GET_QUEUE_STATS_SM_SHFT 25 +#define HWIO_TQM_R0_SM_STATES_IX0_GET_MPDU_HEAD_INFO_SM_BMSK 0x1e00000 +#define HWIO_TQM_R0_SM_STATES_IX0_GET_MPDU_HEAD_INFO_SM_SHFT 21 +#define HWIO_TQM_R0_SM_STATES_IX0_FLUSH_AND_UNBLOCK_CACHE_SM_BMSK 0x180000 +#define HWIO_TQM_R0_SM_STATES_IX0_FLUSH_AND_UNBLOCK_CACHE_SM_SHFT 19 +#define HWIO_TQM_R0_SM_STATES_IX0_ADD_MPDU_LINK_SM_BMSK 0x78000 +#define HWIO_TQM_R0_SM_STATES_IX0_ADD_MPDU_LINK_SM_SHFT 15 +#define HWIO_TQM_R0_SM_STATES_IX0_CREATE_MPDU_SM_BMSK 0x7c00 +#define HWIO_TQM_R0_SM_STATES_IX0_CREATE_MPDU_SM_SHFT 10 +#define HWIO_TQM_R0_SM_STATES_IX0_GEN_MPDU_SM_BMSK 0x3e0 +#define HWIO_TQM_R0_SM_STATES_IX0_GEN_MPDU_SM_SHFT 5 +#define HWIO_TQM_R0_SM_STATES_IX0_ADD_MSDU_SM_BMSK 0x1f +#define HWIO_TQM_R0_SM_STATES_IX0_ADD_MSDU_SM_SHFT 0 + +#define HWIO_TQM_R0_SM_STATES_IX1_ADDR(x) ((x) + 0x45c) +#define HWIO_TQM_R0_SM_STATES_IX1_PHYS(x) ((x) + 0x45c) +#define HWIO_TQM_R0_SM_STATES_IX1_OFFS (0x45c) +#define HWIO_TQM_R0_SM_STATES_IX1_RMSK 0xffffffff +#define HWIO_TQM_R0_SM_STATES_IX1_POR 0x00000000 +#define HWIO_TQM_R0_SM_STATES_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SM_STATES_IX1_ATTR 0x1 +#define HWIO_TQM_R0_SM_STATES_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_SM_STATES_IX1_ADDR(x)) +#define HWIO_TQM_R0_SM_STATES_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SM_STATES_IX1_ADDR(x), m) +#define HWIO_TQM_R0_SM_STATES_IX1_ARB_STATUS_BLK1_SM_BMSK 0xc0000000 +#define HWIO_TQM_R0_SM_STATES_IX1_ARB_STATUS_BLK1_SM_SHFT 30 +#define HWIO_TQM_R0_SM_STATES_IX1_ARB_STATUS_BLK0_SM_BMSK 0x30000000 +#define HWIO_TQM_R0_SM_STATES_IX1_ARB_STATUS_BLK0_SM_SHFT 28 +#define HWIO_TQM_R0_SM_STATES_IX1_UPDATE_TX_MPDU_COUNT_SM_BMSK 0xf800000 +#define HWIO_TQM_R0_SM_STATES_IX1_UPDATE_TX_MPDU_COUNT_SM_SHFT 23 +#define HWIO_TQM_R0_SM_STATES_IX1_REM_MSDU_SM_BMSK 0x7c0000 +#define HWIO_TQM_R0_SM_STATES_IX1_REM_MSDU_SM_SHFT 18 +#define HWIO_TQM_R0_SM_STATES_IX1_REM_MPDU_SM_BMSK 0x3f000 +#define HWIO_TQM_R0_SM_STATES_IX1_REM_MPDU_SM_SHFT 12 +#define HWIO_TQM_R0_SM_STATES_IX1_WRITE_CMD_SM_BMSK 0xe00 +#define HWIO_TQM_R0_SM_STATES_IX1_WRITE_CMD_SM_SHFT 9 +#define HWIO_TQM_R0_SM_STATES_IX1_LIST_MPDU_MAIN_SM_BMSK 0x1f0 +#define HWIO_TQM_R0_SM_STATES_IX1_LIST_MPDU_MAIN_SM_SHFT 4 +#define HWIO_TQM_R0_SM_STATES_IX1_LIST_TLV_SM_BMSK 0xf +#define HWIO_TQM_R0_SM_STATES_IX1_LIST_TLV_SM_SHFT 0 + +#define HWIO_TQM_R0_SM_STATES_IX2_ADDR(x) ((x) + 0x460) +#define HWIO_TQM_R0_SM_STATES_IX2_PHYS(x) ((x) + 0x460) +#define HWIO_TQM_R0_SM_STATES_IX2_OFFS (0x460) +#define HWIO_TQM_R0_SM_STATES_IX2_RMSK 0xffffffff +#define HWIO_TQM_R0_SM_STATES_IX2_POR 0x00000000 +#define HWIO_TQM_R0_SM_STATES_IX2_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SM_STATES_IX2_ATTR 0x1 +#define HWIO_TQM_R0_SM_STATES_IX2_IN(x) \ + in_dword(HWIO_TQM_R0_SM_STATES_IX2_ADDR(x)) +#define HWIO_TQM_R0_SM_STATES_IX2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SM_STATES_IX2_ADDR(x), m) +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_ASYNC_SM_BMSK 0x80000000 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_ASYNC_SM_SHFT 31 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_MSDU_ENT_SM_BMSK 0x70000000 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_MSDU_ENT_SM_SHFT 28 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_SW_CMD_SM_BMSK 0xf000000 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_SW_CMD_SM_SHFT 24 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_HWSCH_CMD_SM_BMSK 0xf00000 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_HWSCH_CMD_SM_SHFT 20 +#define HWIO_TQM_R0_SM_STATES_IX2_PREFETCH_READ_SM_BMSK 0xc0000 +#define HWIO_TQM_R0_SM_STATES_IX2_PREFETCH_READ_SM_SHFT 18 +#define HWIO_TQM_R0_SM_STATES_IX2_PREFETCH_SM_BMSK 0x3ffff +#define HWIO_TQM_R0_SM_STATES_IX2_PREFETCH_SM_SHFT 0 + +#define HWIO_TQM_R0_SM_STATES_IX3_ADDR(x) ((x) + 0x464) +#define HWIO_TQM_R0_SM_STATES_IX3_PHYS(x) ((x) + 0x464) +#define HWIO_TQM_R0_SM_STATES_IX3_OFFS (0x464) +#define HWIO_TQM_R0_SM_STATES_IX3_RMSK 0xffffff +#define HWIO_TQM_R0_SM_STATES_IX3_POR 0x00000000 +#define HWIO_TQM_R0_SM_STATES_IX3_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SM_STATES_IX3_ATTR 0x1 +#define HWIO_TQM_R0_SM_STATES_IX3_IN(x) \ + in_dword(HWIO_TQM_R0_SM_STATES_IX3_ADDR(x)) +#define HWIO_TQM_R0_SM_STATES_IX3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SM_STATES_IX3_ADDR(x), m) +#define HWIO_TQM_R0_SM_STATES_IX3_PREFETCH_SM_BMSK 0xff0000 +#define HWIO_TQM_R0_SM_STATES_IX3_PREFETCH_SM_SHFT 16 +#define HWIO_TQM_R0_SM_STATES_IX3_TQM2TQM_OUT2_SM_STATE_BMSK 0xc000 +#define HWIO_TQM_R0_SM_STATES_IX3_TQM2TQM_OUT2_SM_STATE_SHFT 14 +#define HWIO_TQM_R0_SM_STATES_IX3_TQM2TQM_OUT1_SM_STATE_BMSK 0x3000 +#define HWIO_TQM_R0_SM_STATES_IX3_TQM2TQM_OUT1_SM_STATE_SHFT 12 +#define HWIO_TQM_R0_SM_STATES_IX3_UPDATE_QUEUE_DESC_SM_BMSK 0xf80 +#define HWIO_TQM_R0_SM_STATES_IX3_UPDATE_QUEUE_DESC_SM_SHFT 7 +#define HWIO_TQM_R0_SM_STATES_IX3_AXI_TO_TLV_SM_BMSK 0x60 +#define HWIO_TQM_R0_SM_STATES_IX3_AXI_TO_TLV_SM_SHFT 5 +#define HWIO_TQM_R0_SM_STATES_IX3_LIST_TLV_STATE_BMSK 0x1c +#define HWIO_TQM_R0_SM_STATES_IX3_LIST_TLV_STATE_SHFT 2 +#define HWIO_TQM_R0_SM_STATES_IX3_DATA_ALIGN_SM_BMSK 0x3 +#define HWIO_TQM_R0_SM_STATES_IX3_DATA_ALIGN_SM_SHFT 0 + +#define HWIO_TQM_R0_MISC_CFG_ADDR(x) ((x) + 0x468) +#define HWIO_TQM_R0_MISC_CFG_PHYS(x) ((x) + 0x468) +#define HWIO_TQM_R0_MISC_CFG_OFFS (0x468) +#define HWIO_TQM_R0_MISC_CFG_RMSK 0xffdfefff +#define HWIO_TQM_R0_MISC_CFG_POR 0x9a576fe0 +#define HWIO_TQM_R0_MISC_CFG_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MISC_CFG_ATTR 0x3 +#define HWIO_TQM_R0_MISC_CFG_IN(x) \ + in_dword(HWIO_TQM_R0_MISC_CFG_ADDR(x)) +#define HWIO_TQM_R0_MISC_CFG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MISC_CFG_ADDR(x), m) +#define HWIO_TQM_R0_MISC_CFG_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MISC_CFG_ADDR(x),v) +#define HWIO_TQM_R0_MISC_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MISC_CFG_ADDR(x),m,v,HWIO_TQM_R0_MISC_CFG_IN(x)) +#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK 0x80000000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT 31 +#define HWIO_TQM_R0_MISC_CFG_DISABLE_LINK_STARVATION_WAIT_BMSK 0x40000000 +#define HWIO_TQM_R0_MISC_CFG_DISABLE_LINK_STARVATION_WAIT_SHFT 30 +#define HWIO_TQM_R0_MISC_CFG_DISABLE_STATUS_FOR_INVALID_FLOW_BMSK 0x20000000 +#define HWIO_TQM_R0_MISC_CFG_DISABLE_STATUS_FOR_INVALID_FLOW_SHFT 29 +#define HWIO_TQM_R0_MISC_CFG_ENB_ACKED_MPDU_QUEUE_OVERVIEW_BMSK 0x10000000 +#define HWIO_TQM_R0_MISC_CFG_ENB_ACKED_MPDU_QUEUE_OVERVIEW_SHFT 28 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_TLV_FILTER_BMSK 0x8000000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_TLV_FILTER_SHFT 27 +#define HWIO_TQM_R0_MISC_CFG_SEND_MSI_AFTER_IDLE_RESP_BMSK 0x4000000 +#define HWIO_TQM_R0_MISC_CFG_SEND_MSI_AFTER_IDLE_RESP_SHFT 26 +#define HWIO_TQM_R0_MISC_CFG_FILTER_INVALID_ADDRESS_IN_COMMANDS_BMSK 0x2000000 +#define HWIO_TQM_R0_MISC_CFG_FILTER_INVALID_ADDRESS_IN_COMMANDS_SHFT 25 +#define HWIO_TQM_R0_MISC_CFG_STATUS1_WRITE_POSTED_BMSK 0x1000000 +#define HWIO_TQM_R0_MISC_CFG_STATUS1_WRITE_POSTED_SHFT 24 +#define HWIO_TQM_R0_MISC_CFG_STATUS_WRITE_POSTED_BMSK 0x800000 +#define HWIO_TQM_R0_MISC_CFG_STATUS_WRITE_POSTED_SHFT 23 +#define HWIO_TQM_R0_MISC_CFG_UPDATE_FW2TQM_TP_AT_8W_BOUNDARY_BMSK 0x400000 +#define HWIO_TQM_R0_MISC_CFG_UPDATE_FW2TQM_TP_AT_8W_BOUNDARY_SHFT 22 +#define HWIO_TQM_R0_MISC_CFG_UPDATE_TCL2TQM_TP_AT_8W_BOUNDARY_BMSK 0x100000 +#define HWIO_TQM_R0_MISC_CFG_UPDATE_TCL2TQM_TP_AT_8W_BOUNDARY_SHFT 20 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_FILTER_GEN_MPDU_EMPTY_STATUS_BMSK 0x80000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_FILTER_GEN_MPDU_EMPTY_STATUS_SHFT 19 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_INVALIDATE_CACHE_FOR_INVALID_DESC_BMSK 0x40000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_INVALIDATE_CACHE_FOR_INVALID_DESC_SHFT 18 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_UPDATE_TX_COUNT_DURING_FLUSH_BMSK 0x20000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_UPDATE_TX_COUNT_DURING_FLUSH_SHFT 17 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_BA_PROC_DURING_FLUSH_BMSK 0x10000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_BA_PROC_DURING_FLUSH_SHFT 16 +#define HWIO_TQM_R0_MISC_CFG_WRITE_CMD_SWAP_BIT_BMSK 0x8000 +#define HWIO_TQM_R0_MISC_CFG_WRITE_CMD_SWAP_BIT_SHFT 15 +#define HWIO_TQM_R0_MISC_CFG_WRITE_CMD_POSTED_BMSK 0x4000 +#define HWIO_TQM_R0_MISC_CFG_WRITE_CMD_POSTED_SHFT 14 +#define HWIO_TQM_R0_MISC_CFG_DESC_PTR_RELEASE_POSTED_BMSK 0x2000 +#define HWIO_TQM_R0_MISC_CFG_DESC_PTR_RELEASE_POSTED_SHFT 13 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_REM_MSDU_BMSK 0x800 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_REM_MSDU_SHFT 11 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_LIST_MPDU_BMSK 0x400 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_LIST_MPDU_SHFT 10 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_GEN_MPDU_BMSK 0x200 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_GEN_MPDU_SHFT 9 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_REM_MPDU_BMSK 0x100 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_REM_MPDU_SHFT 8 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_ACKED_MPDU_BMSK 0x80 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_ACKED_MPDU_SHFT 7 +#define HWIO_TQM_R0_MISC_CFG_FORCE_TO_REPORT_STATUS_BMSK 0x40 +#define HWIO_TQM_R0_MISC_CFG_FORCE_TO_REPORT_STATUS_SHFT 6 +#define HWIO_TQM_R0_MISC_CFG_LIST_MPDU_POSTED_BMSK 0x20 +#define HWIO_TQM_R0_MISC_CFG_LIST_MPDU_POSTED_SHFT 5 +#define HWIO_TQM_R0_MISC_CFG_LIST_MPDU_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_MISC_CFG_LIST_MPDU_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_MISC_CFG_LIST_MPDU_SECURITY_BIT_BMSK 0x8 +#define HWIO_TQM_R0_MISC_CFG_LIST_MPDU_SECURITY_BIT_SHFT 3 +#define HWIO_TQM_R0_MISC_CFG_GEN_MPDU_POSTED_BMSK 0x4 +#define HWIO_TQM_R0_MISC_CFG_GEN_MPDU_POSTED_SHFT 2 +#define HWIO_TQM_R0_MISC_CFG_GEN_MPDU_SWAP_BIT_BMSK 0x2 +#define HWIO_TQM_R0_MISC_CFG_GEN_MPDU_SWAP_BIT_SHFT 1 +#define HWIO_TQM_R0_MISC_CFG_GEN_MPDU_SECURITY_BIT_BMSK 0x1 +#define HWIO_TQM_R0_MISC_CFG_GEN_MPDU_SECURITY_BIT_SHFT 0 + +#define HWIO_TQM_R0_MISC_CFG_1_ADDR(x) ((x) + 0x46c) +#define HWIO_TQM_R0_MISC_CFG_1_PHYS(x) ((x) + 0x46c) +#define HWIO_TQM_R0_MISC_CFG_1_OFFS (0x46c) +#define HWIO_TQM_R0_MISC_CFG_1_RMSK 0x3fff +#define HWIO_TQM_R0_MISC_CFG_1_POR 0x00001040 +#define HWIO_TQM_R0_MISC_CFG_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MISC_CFG_1_ATTR 0x3 +#define HWIO_TQM_R0_MISC_CFG_1_IN(x) \ + in_dword(HWIO_TQM_R0_MISC_CFG_1_ADDR(x)) +#define HWIO_TQM_R0_MISC_CFG_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MISC_CFG_1_ADDR(x), m) +#define HWIO_TQM_R0_MISC_CFG_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MISC_CFG_1_ADDR(x),v) +#define HWIO_TQM_R0_MISC_CFG_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MISC_CFG_1_ADDR(x),m,v,HWIO_TQM_R0_MISC_CFG_1_IN(x)) +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK 0x2000 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT 13 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK 0x1000 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT 12 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK 0x800 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT 11 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK 0x400 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT 10 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_TQM2TQM_GEN_MPDUS_BMSK 0x200 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_TQM2TQM_GEN_MPDUS_SHFT 9 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_MLO_FRAGMENTATION_BMSK 0x100 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_MLO_FRAGMENTATION_SHFT 8 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_SESSION_ID_BMSK 0x80 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_SESSION_ID_SHFT 7 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_OWNER_CHECK_BMSK 0x40 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_OWNER_CHECK_SHFT 6 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_DROP_COUNT_UPDATES_FOR_MULTICAST_BMSK 0x20 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_DROP_COUNT_UPDATES_FOR_MULTICAST_SHFT 5 +#define HWIO_TQM_R0_MISC_CFG_1_UNMASK_EVENT_BUS_POT_BMSK 0x10 +#define HWIO_TQM_R0_MISC_CFG_1_UNMASK_EVENT_BUS_POT_SHFT 4 +#define HWIO_TQM_R0_MISC_CFG_1_ALLOW_REGISTER_FLUSH_ACK_BMSK 0x8 +#define HWIO_TQM_R0_MISC_CFG_1_ALLOW_REGISTER_FLUSH_ACK_SHFT 3 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_SINGLE_FLOW_CONCURRENCY_BMSK 0x4 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_SINGLE_FLOW_CONCURRENCY_SHFT 2 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_UPDATE_REQUIREMENT_CHECK_BMSK 0x2 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_UPDATE_REQUIREMENT_CHECK_SHFT 1 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_PREFETCH_FIX_BMSK 0x1 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_PREFETCH_FIX_SHFT 0 + +#define HWIO_TQM_R0_CLKGATE_CTRL_ADDR(x) ((x) + 0x470) +#define HWIO_TQM_R0_CLKGATE_CTRL_PHYS(x) ((x) + 0x470) +#define HWIO_TQM_R0_CLKGATE_CTRL_OFFS (0x470) +#define HWIO_TQM_R0_CLKGATE_CTRL_RMSK 0xdfffffff +#define HWIO_TQM_R0_CLKGATE_CTRL_POR 0x00000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CLKGATE_CTRL_ATTR 0x3 +#define HWIO_TQM_R0_CLKGATE_CTRL_IN(x) \ + in_dword(HWIO_TQM_R0_CLKGATE_CTRL_ADDR(x)) +#define HWIO_TQM_R0_CLKGATE_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_ADDR(x), m) +#define HWIO_TQM_R0_CLKGATE_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CLKGATE_CTRL_ADDR(x),v) +#define HWIO_TQM_R0_CLKGATE_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_IN(x)) +#define HWIO_TQM_R0_CLKGATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x80000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_CLOCK_ENS_EXTEND_SHFT 31 +#define HWIO_TQM_R0_CLKGATE_CTRL_CLK_GATE_DISABLE_APB_BMSK 0x40000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_CLK_GATE_DISABLE_APB_SHFT 30 +#define HWIO_TQM_R0_CLKGATE_CTRL_COMMON_LOGIC_DESC_DISABLE_BMSK 0x10000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_COMMON_LOGIC_DESC_DISABLE_SHFT 28 +#define HWIO_TQM_R0_CLKGATE_CTRL_HWSCH_TX_TLV2_DISABLE_BMSK 0x8000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_HWSCH_TX_TLV2_DISABLE_SHFT 27 +#define HWIO_TQM_R0_CLKGATE_CTRL_HWSCH_TX_TLV1_DISABLE_BMSK 0x4000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_HWSCH_TX_TLV1_DISABLE_SHFT 26 +#define HWIO_TQM_R0_CLKGATE_CTRL_DESC_REL_RING_DISABLE_BMSK 0x2000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_DESC_REL_RING_DISABLE_SHFT 25 +#define HWIO_TQM_R0_CLKGATE_CTRL_STATUS1_RING_DISABLE_BMSK 0x1000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_STATUS1_RING_DISABLE_SHFT 24 +#define HWIO_TQM_R0_CLKGATE_CTRL_STATUS_RING_DISABLE_BMSK 0x800000 +#define HWIO_TQM_R0_CLKGATE_CTRL_STATUS_RING_DISABLE_SHFT 23 +#define HWIO_TQM_R0_CLKGATE_CTRL_DESC_PTR_RING_DISABLE_BMSK 0x400000 +#define HWIO_TQM_R0_CLKGATE_CTRL_DESC_PTR_RING_DISABLE_SHFT 22 +#define HWIO_TQM_R0_CLKGATE_CTRL_SW_CMD1_RING_DISABLE_BMSK 0x200000 +#define HWIO_TQM_R0_CLKGATE_CTRL_SW_CMD1_RING_DISABLE_SHFT 21 +#define HWIO_TQM_R0_CLKGATE_CTRL_SW_CMD_RING_DISABLE_BMSK 0x100000 +#define HWIO_TQM_R0_CLKGATE_CTRL_SW_CMD_RING_DISABLE_SHFT 20 +#define HWIO_TQM_R0_CLKGATE_CTRL_MSDU_ENT3_RING_DISABLE_BMSK 0x80000 +#define HWIO_TQM_R0_CLKGATE_CTRL_MSDU_ENT3_RING_DISABLE_SHFT 19 +#define HWIO_TQM_R0_CLKGATE_CTRL_MSDU_ENT1_RING_DISABLE_BMSK 0x40000 +#define HWIO_TQM_R0_CLKGATE_CTRL_MSDU_ENT1_RING_DISABLE_SHFT 18 +#define HWIO_TQM_R0_CLKGATE_CTRL_UPDATE_QUEUE_DESC_CLK_GATE_DISABLE_BMSK 0x20000 +#define HWIO_TQM_R0_CLKGATE_CTRL_UPDATE_QUEUE_DESC_CLK_GATE_DISABLE_SHFT 17 +#define HWIO_TQM_R0_CLKGATE_CTRL_CACHE_MEM_CLK_GATE_DISABLE_BMSK 0x10000 +#define HWIO_TQM_R0_CLKGATE_CTRL_CACHE_MEM_CLK_GATE_DISABLE_SHFT 16 +#define HWIO_TQM_R0_CLKGATE_CTRL_TLV_IF_CLK_GATE_DISABLE_BMSK 0x8000 +#define HWIO_TQM_R0_CLKGATE_CTRL_TLV_IF_CLK_GATE_DISABLE_SHFT 15 +#define HWIO_TQM_R0_CLKGATE_CTRL_AXI_IF_CLK_GATE_DISABLE_BMSK 0x4000 +#define HWIO_TQM_R0_CLKGATE_CTRL_AXI_IF_CLK_GATE_DISABLE_SHFT 14 +#define HWIO_TQM_R0_CLKGATE_CTRL_COMMON_LOGIC_CLK_GATE_DISABLE_BMSK 0x2000 +#define HWIO_TQM_R0_CLKGATE_CTRL_COMMON_LOGIC_CLK_GATE_DISABLE_SHFT 13 +#define HWIO_TQM_R0_CLKGATE_CTRL_FLUSH_UNBLK_CACHE_CLK_GATE_DISABLE_BMSK 0x1000 +#define HWIO_TQM_R0_CLKGATE_CTRL_FLUSH_UNBLK_CACHE_CLK_GATE_DISABLE_SHFT 12 +#define HWIO_TQM_R0_CLKGATE_CTRL_GET_MPDU_HEAD_INFO_CLK_GATE_DISABLE_BMSK 0x800 +#define HWIO_TQM_R0_CLKGATE_CTRL_GET_MPDU_HEAD_INFO_CLK_GATE_DISABLE_SHFT 11 +#define HWIO_TQM_R0_CLKGATE_CTRL_REM_MSDU_CLK_GATE_DISABLE_BMSK 0x400 +#define HWIO_TQM_R0_CLKGATE_CTRL_REM_MSDU_CLK_GATE_DISABLE_SHFT 10 +#define HWIO_TQM_R0_CLKGATE_CTRL_REM_MPDU_CLK_GATE_DISABLE_BMSK 0x200 +#define HWIO_TQM_R0_CLKGATE_CTRL_REM_MPDU_CLK_GATE_DISABLE_SHFT 9 +#define HWIO_TQM_R0_CLKGATE_CTRL_GET_QUEUE_STATS_CLK_GATE_DISABLE_BMSK 0x100 +#define HWIO_TQM_R0_CLKGATE_CTRL_GET_QUEUE_STATS_CLK_GATE_DISABLE_SHFT 8 +#define HWIO_TQM_R0_CLKGATE_CTRL_TX_MPDU_COUNT_CLK_GATE_DISABLE_BMSK 0x80 +#define HWIO_TQM_R0_CLKGATE_CTRL_TX_MPDU_COUNT_CLK_GATE_DISABLE_SHFT 7 +#define HWIO_TQM_R0_CLKGATE_CTRL_LIST_MPDU_CLK_GATE_DISABLE_BMSK 0x40 +#define HWIO_TQM_R0_CLKGATE_CTRL_LIST_MPDU_CLK_GATE_DISABLE_SHFT 6 +#define HWIO_TQM_R0_CLKGATE_CTRL_GEN_MPDU_CLK_GATE_DISABLE_BMSK 0x20 +#define HWIO_TQM_R0_CLKGATE_CTRL_GEN_MPDU_CLK_GATE_DISABLE_SHFT 5 +#define HWIO_TQM_R0_CLKGATE_CTRL_ADD_MSDU_CLK_GATE_DISABLE_BMSK 0x10 +#define HWIO_TQM_R0_CLKGATE_CTRL_ADD_MSDU_CLK_GATE_DISABLE_SHFT 4 +#define HWIO_TQM_R0_CLKGATE_CTRL_ARBITER_CLK_GATE_DISABLE_BMSK 0x8 +#define HWIO_TQM_R0_CLKGATE_CTRL_ARBITER_CLK_GATE_DISABLE_SHFT 3 +#define HWIO_TQM_R0_CLKGATE_CTRL_PREFETCH_CLK_GATE_DISABLE_BMSK 0x4 +#define HWIO_TQM_R0_CLKGATE_CTRL_PREFETCH_CLK_GATE_DISABLE_SHFT 2 +#define HWIO_TQM_R0_CLKGATE_CTRL_CACHE_CTL_CLK_GATE_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_CLKGATE_CTRL_CACHE_CTL_CLK_GATE_DISABLE_SHFT 1 +#define HWIO_TQM_R0_CLKGATE_CTRL_TOP_CLK_GATE_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_CLKGATE_CTRL_TOP_CLK_GATE_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_ADDR(x) ((x) + 0x474) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_PHYS(x) ((x) + 0x474) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_OFFS (0x474) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_RMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_POR 0x00000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_LINK_DESCRIPTOR_COUNTER_BMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_LINK_DESCRIPTOR_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_ADDR(x) ((x) + 0x478) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_PHYS(x) ((x) + 0x478) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_OFFS (0x478) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_RMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_POR 0x00000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_LINK_DESCRIPTOR_COUNTER_BMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_LINK_DESCRIPTOR_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_ADDR(x) ((x) + 0x47c) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_PHYS(x) ((x) + 0x47c) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_OFFS (0x47c) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_RMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_POR 0x00000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_LINK_DESCRIPTOR_COUNTER_BMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_LINK_DESCRIPTOR_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_ADDR(x) ((x) + 0x480) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_PHYS(x) ((x) + 0x480) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_OFFS (0x480) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_RMSK 0xf0ffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_POR 0x00ffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_MESSAGE_ENABLE_BMSK 0x80000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_MESSAGE_ENABLE_SHFT 31 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_MESSAGE_GENERATED_BMSK 0x40000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_MESSAGE_GENERATED_SHFT 30 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_PAUSE_ENABLE_BMSK 0x20000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_PAUSE_ENABLE_SHFT 29 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_PAUSE_STATUS_BMSK 0x10000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_PAUSE_STATUS_SHFT 28 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_LINK_DESCRIPTOR_COUNTER0_THRESHOLD_BMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_LINK_DESCRIPTOR_COUNTER0_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_ADDR(x) ((x) + 0x484) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_PHYS(x) ((x) + 0x484) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_OFFS (0x484) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_RMSK 0xf0ffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_POR 0x00000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_MESSAGE_ENABLE_BMSK 0x80000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_MESSAGE_ENABLE_SHFT 31 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_MESSAGE_GENERATED_BMSK 0x40000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_MESSAGE_GENERATED_SHFT 30 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_PAUSE_ENABLE_BMSK 0x20000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_PAUSE_ENABLE_SHFT 29 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_PAUSE_STATUS_BMSK 0x10000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_PAUSE_STATUS_SHFT 28 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_LINK_DESCRIPTOR_COUNTER1_THRESHOLD_BMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_LINK_DESCRIPTOR_COUNTER1_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_ADDR(x) ((x) + 0x488) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_PHYS(x) ((x) + 0x488) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_OFFS (0x488) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_RMSK 0xf0ffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_POR 0x00000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_MESSAGE_ENABLE_BMSK 0x80000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_MESSAGE_ENABLE_SHFT 31 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_MESSAGE_GENERATED_BMSK 0x40000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_MESSAGE_GENERATED_SHFT 30 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_PAUSE_ENABLE_BMSK 0x20000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_PAUSE_ENABLE_SHFT 29 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_PAUSE_STATUS_BMSK 0x10000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_PAUSE_STATUS_SHFT 28 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_LINK_DESCRIPTOR_COUNTER2_THRESHOLD_BMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_LINK_DESCRIPTOR_COUNTER2_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_ADDR(x) ((x) + 0x48c) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_PHYS(x) ((x) + 0x48c) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_OFFS (0x48c) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_RMSK 0xf3ffffff +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_POR 0x00000000 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_ATTR 0x3 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_IN(x) \ + in_dword(HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_ADDR(x)) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_ADDR(x), m) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_OUT(x, v) \ + out_dword(HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_ADDR(x),v) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_ADDR(x),m,v,HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_IN(x)) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_MESSAGE_ENABLE_BMSK 0x80000000 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_MESSAGE_ENABLE_SHFT 31 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_MESSAGE_GENERATED_BMSK 0x40000000 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_MESSAGE_GENERATED_SHFT 30 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_PAUSE_ENABLE_BMSK 0x20000000 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_PAUSE_ENABLE_SHFT 29 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_PAUSE_STATUS_BMSK 0x10000000 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_PAUSE_STATUS_SHFT 28 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_LINK_DESCRIPTOR_COUNTER_SUM_THRESHOLD_BMSK 0x3ffffff +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_LINK_DESCRIPTOR_COUNTER_SUM_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_ADDR(x) ((x) + 0x490) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_PHYS(x) ((x) + 0x490) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_OFFS (0x490) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_RMSK 0xa3ff17ff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_POR 0x00ff0000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_STATUS_FW2TQM_BMSK 0x80000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_STATUS_FW2TQM_SHFT 31 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_STATUS_TCL2TQM_BMSK 0x20000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_STATUS_TCL2TQM_SHFT 29 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_UNPAUSE_LINK_DESC_THRESHOLD_BMSK 0x3ff0000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_UNPAUSE_LINK_DESC_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_FW2TQM_BMSK 0x1000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_FW2TQM_SHFT 12 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_TCL2TQM_BMSK 0x400 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_TCL2TQM_SHFT 10 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_LINK_DESC_THRESHOLD_BMSK 0x3ff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_LINK_DESC_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_DESC_PTR_RELEASE_ADDR(x) ((x) + 0x494) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_PHYS(x) ((x) + 0x494) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_OFFS (0x494) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_RMSK 0xffff +#define HWIO_TQM_R0_DESC_PTR_RELEASE_POR 0x00001740 +#define HWIO_TQM_R0_DESC_PTR_RELEASE_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DESC_PTR_RELEASE_ATTR 0x3 +#define HWIO_TQM_R0_DESC_PTR_RELEASE_IN(x) \ + in_dword(HWIO_TQM_R0_DESC_PTR_RELEASE_ADDR(x)) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DESC_PTR_RELEASE_ADDR(x), m) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DESC_PTR_RELEASE_ADDR(x),v) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DESC_PTR_RELEASE_ADDR(x),m,v,HWIO_TQM_R0_DESC_PTR_RELEASE_IN(x)) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_THRESH_BMSK 0xff00 +#define HWIO_TQM_R0_DESC_PTR_RELEASE_THRESH_SHFT 8 +#define HWIO_TQM_R0_DESC_PTR_RELEASE_TIMEOUT_BMSK 0xff +#define HWIO_TQM_R0_DESC_PTR_RELEASE_TIMEOUT_SHFT 0 + +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x498) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x498) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_OFFS (0x498) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x49c) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x49c) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_OFFS (0x49c) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xfffe +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 1 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4a0) +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4a0) +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_OFFS (0x4a0) +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4a4) +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4a4) +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_OFFS (0x4a4) +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4a8) +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4a8) +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_OFFS (0x4a8) +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_RMSK 0xffe1 +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4ac) +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4ac) +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_OFFS (0x4ac) +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4b0) +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4b0) +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_OFFS (0x4b0) +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4b4) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4b4) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_OFFS (0x4b4) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4b8) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4b8) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_OFFS (0x4b8) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_ERROR_STATUS_1_ADDR(x) ((x) + 0x4bc) +#define HWIO_TQM_R0_ERROR_STATUS_1_PHYS(x) ((x) + 0x4bc) +#define HWIO_TQM_R0_ERROR_STATUS_1_OFFS (0x4bc) +#define HWIO_TQM_R0_ERROR_STATUS_1_RMSK 0x3fff +#define HWIO_TQM_R0_ERROR_STATUS_1_POR 0x00000000 +#define HWIO_TQM_R0_ERROR_STATUS_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_ERROR_STATUS_1_ATTR 0x0 +#define HWIO_TQM_R0_ERROR_STATUS_1_IN(x) \ + in_dword(HWIO_TQM_R0_ERROR_STATUS_1_ADDR(x)) +#define HWIO_TQM_R0_ERROR_STATUS_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_ERROR_STATUS_1_ADDR(x), m) +#define HWIO_TQM_R0_ERROR_STATUS_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_ERROR_STATUS_1_ADDR(x),v) +#define HWIO_TQM_R0_ERROR_STATUS_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_ERROR_STATUS_1_ADDR(x),m,v,HWIO_TQM_R0_ERROR_STATUS_1_IN(x)) +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_TQM2TQM_IN2_RING_BMSK 0x2000 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_TQM2TQM_IN2_RING_SHFT 13 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_TQM2TQM_IN1_RING_BMSK 0x1000 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_TQM2TQM_IN1_RING_SHFT 12 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_SW_CMD_1_RING_BMSK 0x800 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_SW_CMD_1_RING_SHFT 11 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_SW_CMD_0_RING_BMSK 0x400 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_SW_CMD_0_RING_SHFT 10 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_UPDATE_TX_MPDU_COUNT_BMSK 0x200 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_UPDATE_TX_MPDU_COUNT_SHFT 9 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_REM_MSDU_BMSK 0x100 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_REM_MSDU_SHFT 8 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_ACKED_MPDU_BMSK 0x80 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_ACKED_MPDU_SHFT 7 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_REM_MPDU_BMSK 0x40 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_REM_MPDU_SHFT 6 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_LIST_MPDU_BMSK 0x20 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_LIST_MPDU_SHFT 5 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GET_MPDU_QUEUE_STATS_BMSK 0x10 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GET_MPDU_QUEUE_STATS_SHFT 4 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GET_FLOW_QUEUE_STATS_BMSK 0x8 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GET_FLOW_QUEUE_STATS_SHFT 3 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GET_MPDU_HEAD_INFO_BMSK 0x4 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GET_MPDU_HEAD_INFO_SHFT 2 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GEN_MPDU_BMSK 0x2 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GEN_MPDU_SHFT 1 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_ADD_MSDU_BMSK 0x1 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_ADD_MSDU_SHFT 0 + +#define HWIO_TQM_R0_TLV_IF_ADDR(x) ((x) + 0x4c0) +#define HWIO_TQM_R0_TLV_IF_PHYS(x) ((x) + 0x4c0) +#define HWIO_TQM_R0_TLV_IF_OFFS (0x4c0) +#define HWIO_TQM_R0_TLV_IF_RMSK 0x7 +#define HWIO_TQM_R0_TLV_IF_POR 0x00000000 +#define HWIO_TQM_R0_TLV_IF_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TLV_IF_ATTR 0x3 +#define HWIO_TQM_R0_TLV_IF_IN(x) \ + in_dword(HWIO_TQM_R0_TLV_IF_ADDR(x)) +#define HWIO_TQM_R0_TLV_IF_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TLV_IF_ADDR(x), m) +#define HWIO_TQM_R0_TLV_IF_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TLV_IF_ADDR(x),v) +#define HWIO_TQM_R0_TLV_IF_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TLV_IF_ADDR(x),m,v,HWIO_TQM_R0_TLV_IF_IN(x)) +#define HWIO_TQM_R0_TLV_IF_ASYNC_GP_FIFO_2_SYNC_RESET_BMSK 0x4 +#define HWIO_TQM_R0_TLV_IF_ASYNC_GP_FIFO_2_SYNC_RESET_SHFT 2 +#define HWIO_TQM_R0_TLV_IF_ASYNC_GP_FIFO_1_SYNC_RESET_BMSK 0x2 +#define HWIO_TQM_R0_TLV_IF_ASYNC_GP_FIFO_1_SYNC_RESET_SHFT 1 +#define HWIO_TQM_R0_TLV_IF_ASYNC_GP_FIFO_0_SYNC_RESET_BMSK 0x1 +#define HWIO_TQM_R0_TLV_IF_ASYNC_GP_FIFO_0_SYNC_RESET_SHFT 0 + +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_ADDR(x) ((x) + 0x4c4) +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_PHYS(x) ((x) + 0x4c4) +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_OFFS (0x4c4) +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_ATTR 0x1 +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_ADDR(x)) +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_TQM_REFERENCE_TIMESTAMP_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_TQM_REFERENCE_TIMESTAMP_SHFT 0 + +#define HWIO_TQM_R0_SPARE_ADDR(x) ((x) + 0x4c8) +#define HWIO_TQM_R0_SPARE_PHYS(x) ((x) + 0x4c8) +#define HWIO_TQM_R0_SPARE_OFFS (0x4c8) +#define HWIO_TQM_R0_SPARE_RMSK 0xffffffff +#define HWIO_TQM_R0_SPARE_POR 0x00000000 +#define HWIO_TQM_R0_SPARE_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SPARE_ATTR 0x3 +#define HWIO_TQM_R0_SPARE_IN(x) \ + in_dword(HWIO_TQM_R0_SPARE_ADDR(x)) +#define HWIO_TQM_R0_SPARE_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SPARE_ADDR(x), m) +#define HWIO_TQM_R0_SPARE_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SPARE_ADDR(x),v) +#define HWIO_TQM_R0_SPARE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SPARE_ADDR(x),m,v,HWIO_TQM_R0_SPARE_IN(x)) +#define HWIO_TQM_R0_SPARE_SPAREBITS_BMSK 0xffffffff +#define HWIO_TQM_R0_SPARE_SPAREBITS_SHFT 0 + +#define HWIO_TQM_R0_SPEAR_ADDR(x) ((x) + 0x4cc) +#define HWIO_TQM_R0_SPEAR_PHYS(x) ((x) + 0x4cc) +#define HWIO_TQM_R0_SPEAR_OFFS (0x4cc) +#define HWIO_TQM_R0_SPEAR_RMSK 0xffffffff +#define HWIO_TQM_R0_SPEAR_POR 0x00000000 +#define HWIO_TQM_R0_SPEAR_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SPEAR_ATTR 0x3 +#define HWIO_TQM_R0_SPEAR_IN(x) \ + in_dword(HWIO_TQM_R0_SPEAR_ADDR(x)) +#define HWIO_TQM_R0_SPEAR_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SPEAR_ADDR(x), m) +#define HWIO_TQM_R0_SPEAR_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SPEAR_ADDR(x),v) +#define HWIO_TQM_R0_SPEAR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SPEAR_ADDR(x),m,v,HWIO_TQM_R0_SPEAR_IN(x)) +#define HWIO_TQM_R0_SPEAR_SPEAR_BMSK 0xffffffff +#define HWIO_TQM_R0_SPEAR_SPEAR_SHFT 0 + +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_ADDR(x) ((x) + 0x4d0) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_PHYS(x) ((x) + 0x4d0) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_OFFS (0x4d0) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_RMSK 0x1f +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_POR 0x00000001 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_ATTR 0x3 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_IN(x) \ + in_dword(HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_ADDR(x)) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_ADDR(x), m) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_OUT(x, v) \ + out_dword(HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_ADDR(x),v) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_ADDR(x),m,v,HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_IN(x)) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_REM_MPDU_BMSK 0x10 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_REM_MPDU_SHFT 4 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_REM_MSDU_BMSK 0x8 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_REM_MSDU_SHFT 3 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_UPDATE_MSDU_FLOW_BMSK 0x4 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_UPDATE_MSDU_FLOW_SHFT 2 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_UPDATE_MPDU_QUEUE_BMSK 0x2 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_UPDATE_MPDU_QUEUE_SHFT 1 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_GEN_MPDUS_BMSK 0x1 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_GEN_MPDUS_SHFT 0 + +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_ADDR(x) ((x) + 0x4d4) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_PHYS(x) ((x) + 0x4d4) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_OFFS (0x4d4) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_RMSK 0x3fffff +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_POR 0x00150000 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_ATTR 0x3 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_IN(x) \ + in_dword(HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_ADDR(x)) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_ADDR(x), m) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_OUT(x, v) \ + out_dword(HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_ADDR(x),v) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_ADDR(x),m,v,HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_IN(x)) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_BAR_ASSIST_BMSK 0x300000 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_BAR_ASSIST_SHFT 20 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_LIST_MPDU_BMSK 0xc0000 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_LIST_MPDU_SHFT 18 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_MISC_TRANSFERS_BMSK 0x30000 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_MISC_TRANSFERS_SHFT 16 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_STATUS1_RING_BMSK 0xc000 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_STATUS1_RING_SHFT 14 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_STATUS_RING_BMSK 0x3000 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_STATUS_RING_SHFT 12 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_DESC_PTR_RELEASE_RING_BMSK 0xc00 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_DESC_PTR_RELEASE_RING_SHFT 10 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_DESC_PTR_FETCH_RING_BMSK 0x300 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_DESC_PTR_FETCH_RING_SHFT 8 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_SW_CMD1_RING_BMSK 0xc0 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_SW_CMD1_RING_SHFT 6 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_SW_CMD_RING_BMSK 0x30 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_SW_CMD_RING_SHFT 4 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_FW2TQM_ENTRANCE_RING_BMSK 0xc +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_FW2TQM_ENTRANCE_RING_SHFT 2 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_TCL2TQM_ENTRANCE_RING_BMSK 0x3 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_TCL2TQM_ENTRANCE_RING_SHFT 0 + +#define HWIO_TQM_R0_VC_ID_ADDR(x) ((x) + 0x4d8) +#define HWIO_TQM_R0_VC_ID_PHYS(x) ((x) + 0x4d8) +#define HWIO_TQM_R0_VC_ID_OFFS (0x4d8) +#define HWIO_TQM_R0_VC_ID_RMSK 0x3f +#define HWIO_TQM_R0_VC_ID_POR 0x00000000 +#define HWIO_TQM_R0_VC_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_VC_ID_ATTR 0x3 +#define HWIO_TQM_R0_VC_ID_IN(x) \ + in_dword(HWIO_TQM_R0_VC_ID_ADDR(x)) +#define HWIO_TQM_R0_VC_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_VC_ID_ADDR(x), m) +#define HWIO_TQM_R0_VC_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_VC_ID_ADDR(x),v) +#define HWIO_TQM_R0_VC_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_VC_ID_ADDR(x),m,v,HWIO_TQM_R0_VC_ID_IN(x)) +#define HWIO_TQM_R0_VC_ID_WBM2TQM_C_SRNG_BMSK 0x20 +#define HWIO_TQM_R0_VC_ID_WBM2TQM_C_SRNG_SHFT 5 +#define HWIO_TQM_R0_VC_ID_SW_CMD1_C_SRNG_BMSK 0x10 +#define HWIO_TQM_R0_VC_ID_SW_CMD1_C_SRNG_SHFT 4 +#define HWIO_TQM_R0_VC_ID_SW_CMD_C_SRNG_BMSK 0x8 +#define HWIO_TQM_R0_VC_ID_SW_CMD_C_SRNG_SHFT 3 +#define HWIO_TQM_R0_VC_ID_FW2TQM_ENTRANCE_C_SRNG_BMSK 0x4 +#define HWIO_TQM_R0_VC_ID_FW2TQM_ENTRANCE_C_SRNG_SHFT 2 +#define HWIO_TQM_R0_VC_ID_TCL2TQM_ENTRANCE_C_SRNG_BMSK 0x2 +#define HWIO_TQM_R0_VC_ID_TCL2TQM_ENTRANCE_C_SRNG_SHFT 1 +#define HWIO_TQM_R0_VC_ID_MISC_TRANSFER_BMSK 0x1 +#define HWIO_TQM_R0_VC_ID_MISC_TRANSFER_SHFT 0 + +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_ADDR(x) ((x) + 0x4dc) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_PHYS(x) ((x) + 0x4dc) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_OFFS (0x4dc) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_RMSK 0xffffffff +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_POR 0x00000000 +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_ATTR 0x3 +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_IN(x) \ + in_dword(HWIO_TQM_R0_BARRIER_RD_CTL_0_ADDR(x)) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_BARRIER_RD_CTL_0_ADDR(x), m) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_BARRIER_RD_CTL_0_ADDR(x),v) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_BARRIER_RD_CTL_0_ADDR(x),m,v,HWIO_TQM_R0_BARRIER_RD_CTL_0_IN(x)) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_LSB_SHFT 0 + +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_ADDR(x) ((x) + 0x4e0) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_PHYS(x) ((x) + 0x4e0) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_OFFS (0x4e0) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_RMSK 0xff +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_POR 0x00000000 +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_ATTR 0x3 +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_IN(x) \ + in_dword(HWIO_TQM_R0_BARRIER_RD_CTL_1_ADDR(x)) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_BARRIER_RD_CTL_1_ADDR(x), m) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_BARRIER_RD_CTL_1_ADDR(x),v) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_BARRIER_RD_CTL_1_ADDR(x),m,v,HWIO_TQM_R0_BARRIER_RD_CTL_1_IN(x)) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_MSB_BMSK 0xff +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_MSB_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_ADDR(x) ((x) + 0x4e4) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_PHYS(x) ((x) + 0x4e4) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_OFFS (0x4e4) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_ADDR(x) ((x) + 0x4e8) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_PHYS(x) ((x) + 0x4e8) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_OFFS (0x4e8) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_ADDR(x) ((x) + 0x4ec) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_PHYS(x) ((x) + 0x4ec) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_OFFS (0x4ec) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x) ((x) + 0x4f0) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x) ((x) + 0x4f0) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS (0x4f0) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x) ((x) + 0x4f4) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x) ((x) + 0x4f4) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS (0x4f4) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x) ((x) + 0x4f8) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x) ((x) + 0x4f8) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS (0x4f8) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT 0 + +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_ADDR(x) ((x) + 0x4fc) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_PHYS(x) ((x) + 0x4fc) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_OFFS (0x4fc) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_RMSK 0xff +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_POR 0x00000000 +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_ATTR 0x3 +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_ADDR(x)) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_ADDR(x), m) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_ADDR(x),v) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_ADDR(x),m,v,HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_IN(x)) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ADDR(x) ((x) + 0x500) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_PHYS(x) ((x) + 0x500) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_OFFS (0x500) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_RMSK 0x3fffffff +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_POR 0x00000000 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ATTR 0x3 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_IN(x) \ + in_dword(HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ADDR(x)) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ADDR(x), m) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_OUT(x, v) \ + out_dword(HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ADDR(x),v) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ADDR(x),m,v,HWIO_TQM_R0_UNLOCKED_CONCURRENCY_IN(x)) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ENB_MSDU_PREF_BMSK 0x20000000 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ENB_MSDU_PREF_SHFT 29 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_MPDU_COUNT_BMSK 0x1ffe0000 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_MPDU_COUNT_SHFT 17 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_MSDU_COUNT_BMSK 0x1fffe +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_MSDU_COUNT_SHFT 1 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ENB_BMSK 0x1 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ENB_SHFT 0 + +#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x) ((x) + 0x504) +#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x) ((x) + 0x504) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS (0x504) +#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK 0xfff +#define HWIO_TQM_R0_WATCHDOG_SRNG_POR 0x00000710 +#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR 0x3 +#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x) \ + in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)) +#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)) +#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK 0xfff +#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_ADDR(x) ((x) + 0x508) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_PHYS(x) ((x) + 0x508) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_OFFS (0x508) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_ADDR(x) ((x) + 0x50c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_PHYS(x) ((x) + 0x50c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_OFFS (0x50c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ADDR(x) ((x) + 0x510) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_PHYS(x) ((x) + 0x510) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_OFFS (0x510) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_ADDR(x) ((x) + 0x514) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_PHYS(x) ((x) + 0x514) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_OFFS (0x514) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_ADDR(x) ((x) + 0x518) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_PHYS(x) ((x) + 0x518) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_OFFS (0x518) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x524) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x524) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_OFFS (0x524) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x528) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x528) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_OFFS (0x528) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x538) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x538) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x538) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x53c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x53c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x53c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x540) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x540) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_OFFS (0x540) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x544) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x544) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x544) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x548) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x548) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x548) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x54c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x54c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x54c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x550) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x550) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_OFFS (0x550) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x554) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x554) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_OFFS (0x554) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_ADDR(x) ((x) + 0x558) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_PHYS(x) ((x) + 0x558) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_OFFS (0x558) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x578) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x578) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_OFFS (0x578) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_ADDR(x) ((x) + 0x57c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_PHYS(x) ((x) + 0x57c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_OFFS (0x57c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x580) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x580) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_OFFS (0x580) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x584) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x584) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OFFS (0x584) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x588) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x588) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OFFS (0x588) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x58c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x58c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OFFS (0x58c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x590) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x590) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OFFS (0x590) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_ADDR(x) ((x) + 0x594) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_PHYS(x) ((x) + 0x594) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_OFFS (0x594) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_ADDR(x) ((x) + 0x598) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_PHYS(x) ((x) + 0x598) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_OFFS (0x598) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_ADDR(x) ((x) + 0x59c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_PHYS(x) ((x) + 0x59c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_OFFS (0x59c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ADDR(x) ((x) + 0x5a0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_PHYS(x) ((x) + 0x5a0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_OFFS (0x5a0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_ADDR(x) ((x) + 0x5a4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_PHYS(x) ((x) + 0x5a4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_OFFS (0x5a4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_ADDR(x) ((x) + 0x5a8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_PHYS(x) ((x) + 0x5a8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_OFFS (0x5a8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x5b4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x5b4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_OFFS (0x5b4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x5b8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x5b8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_OFFS (0x5b8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x5c8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x5c8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x5c8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x5cc) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x5cc) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x5cc) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x5d0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x5d0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_OFFS (0x5d0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x5d4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x5d4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x5d4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x5d8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x5d8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x5d8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x5dc) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x5dc) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x5dc) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x5e0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x5e0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_OFFS (0x5e0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x5e4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x5e4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_OFFS (0x5e4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_ADDR(x) ((x) + 0x5e8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_PHYS(x) ((x) + 0x5e8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_OFFS (0x5e8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x608) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x608) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_OFFS (0x608) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_ADDR(x) ((x) + 0x60c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_PHYS(x) ((x) + 0x60c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_OFFS (0x60c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x610) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x610) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_OFFS (0x610) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x614) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x614) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OFFS (0x614) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x618) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x618) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OFFS (0x618) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x61c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x61c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OFFS (0x61c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x620) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x620) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OFFS (0x620) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_ADDR(x) ((x) + 0x624) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_PHYS(x) ((x) + 0x624) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_OFFS (0x624) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_ADDR(x) ((x) + 0x628) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_PHYS(x) ((x) + 0x628) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_OFFS (0x628) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_ADDR(x) ((x) + 0x62c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_PHYS(x) ((x) + 0x62c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_OFFS (0x62c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ADDR(x) ((x) + 0x630) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_PHYS(x) ((x) + 0x630) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_OFFS (0x630) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_RING_ID_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_ADDR(x) ((x) + 0x634) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_PHYS(x) ((x) + 0x634) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_OFFS (0x634) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADDR(x) ((x) + 0x638) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_PHYS(x) ((x) + 0x638) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_OFFS (0x638) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_RMSK 0x7ffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x63c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x63c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_OFFS (0x63c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x640) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x640) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_OFFS (0x640) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x64c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x64c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_OFFS (0x64c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x650) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x650) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_OFFS (0x650) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x654) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x654) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_OFFS (0x654) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x670) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x670) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_OFFS (0x670) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x674) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x674) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_OFFS (0x674) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_ADDR(x) ((x) + 0x678) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_PHYS(x) ((x) + 0x678) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_OFFS (0x678) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x67c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x67c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_OFFS (0x67c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x680) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x680) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_OFFS (0x680) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x684) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x684) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_OFFS (0x684) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_ADDR(x) ((x) + 0x688) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_PHYS(x) ((x) + 0x688) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_OFFS (0x688) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x698) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x698) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_OFFS (0x698) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_ADDR(x) ((x) + 0x69c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_PHYS(x) ((x) + 0x69c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_OFFS (0x69c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x6a0) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x6a0) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_OFFS (0x6a0) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x6a4) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x6a4) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OFFS (0x6a4) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x6a8) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x6a8) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OFFS (0x6a8) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x6ac) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x6ac) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_OFFS (0x6ac) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x6b0) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x6b0) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_OFFS (0x6b0) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_ADDR(x) ((x) + 0x6b4) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_PHYS(x) ((x) + 0x6b4) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_OFFS (0x6b4) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_ADDR(x) ((x) + 0x6b8) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_PHYS(x) ((x) + 0x6b8) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_OFFS (0x6b8) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_ADDR(x) ((x) + 0x6bc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_PHYS(x) ((x) + 0x6bc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_OFFS (0x6bc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ADDR(x) ((x) + 0x6c0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_PHYS(x) ((x) + 0x6c0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_OFFS (0x6c0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_RING_ID_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_ADDR(x) ((x) + 0x6c4) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_PHYS(x) ((x) + 0x6c4) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_OFFS (0x6c4) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADDR(x) ((x) + 0x6c8) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_PHYS(x) ((x) + 0x6c8) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_OFFS (0x6c8) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_RMSK 0x7ffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_OFFS (0x6cc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x6d0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x6d0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_OFFS (0x6d0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x6dc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x6dc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_OFFS (0x6dc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x6e0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x6e0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_OFFS (0x6e0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x6e4) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x6e4) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_OFFS (0x6e4) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x700) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x700) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_OFFS (0x700) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x704) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x704) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_OFFS (0x704) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_ADDR(x) ((x) + 0x708) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_PHYS(x) ((x) + 0x708) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_OFFS (0x708) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x70c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x70c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_OFFS (0x70c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x710) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x710) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_OFFS (0x710) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x714) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x714) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_OFFS (0x714) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_ADDR(x) ((x) + 0x718) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_PHYS(x) ((x) + 0x718) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_OFFS (0x718) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x728) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x728) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_OFFS (0x728) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_ADDR(x) ((x) + 0x72c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_PHYS(x) ((x) + 0x72c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_OFFS (0x72c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x730) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x730) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_OFFS (0x730) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x734) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x734) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OFFS (0x734) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x738) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x738) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OFFS (0x738) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x73c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x73c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_OFFS (0x73c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x740) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x740) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_OFFS (0x740) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_ADDR(x) ((x) + 0x744) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_PHYS(x) ((x) + 0x744) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_OFFS (0x744) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_ADDR(x) ((x) + 0x748) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_PHYS(x) ((x) + 0x748) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_OFFS (0x748) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_POR 0x01df0190 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_ADDR(x) ((x) + 0x74c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_PHYS(x) ((x) + 0x74c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_OFFS (0x74c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_POR 0x022f01e0 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_ADDR(x) ((x) + 0x750) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_PHYS(x) ((x) + 0x750) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_OFFS (0x750) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_POR 0x027f0230 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_ADDR(x) ((x) + 0x754) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_PHYS(x) ((x) + 0x754) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_OFFS (0x754) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_POR 0x02cf0280 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_ADDR(x) ((x) + 0x758) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_PHYS(x) ((x) + 0x758) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_OFFS (0x758) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_POR 0x02e702d0 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_ADDR(x) ((x) + 0x75c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_PHYS(x) ((x) + 0x75c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_OFFS (0x75c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_POR 0x02ff02e8 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_MLO_CHIP_ID_ADDR(x) ((x) + 0x760) +#define HWIO_TQM_R0_MLO_CHIP_ID_PHYS(x) ((x) + 0x760) +#define HWIO_TQM_R0_MLO_CHIP_ID_OFFS (0x760) +#define HWIO_TQM_R0_MLO_CHIP_ID_RMSK 0x3 +#define HWIO_TQM_R0_MLO_CHIP_ID_POR 0x00000000 +#define HWIO_TQM_R0_MLO_CHIP_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MLO_CHIP_ID_ATTR 0x3 +#define HWIO_TQM_R0_MLO_CHIP_ID_IN(x) \ + in_dword(HWIO_TQM_R0_MLO_CHIP_ID_ADDR(x)) +#define HWIO_TQM_R0_MLO_CHIP_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MLO_CHIP_ID_ADDR(x), m) +#define HWIO_TQM_R0_MLO_CHIP_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MLO_CHIP_ID_ADDR(x),v) +#define HWIO_TQM_R0_MLO_CHIP_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MLO_CHIP_ID_ADDR(x),m,v,HWIO_TQM_R0_MLO_CHIP_ID_IN(x)) +#define HWIO_TQM_R0_MLO_CHIP_ID_VALUE_BMSK 0x3 +#define HWIO_TQM_R0_MLO_CHIP_ID_VALUE_SHFT 0 + +#define HWIO_TQM_R0_MLO_VC_ID_ADDR(x) ((x) + 0x764) +#define HWIO_TQM_R0_MLO_VC_ID_PHYS(x) ((x) + 0x764) +#define HWIO_TQM_R0_MLO_VC_ID_OFFS (0x764) +#define HWIO_TQM_R0_MLO_VC_ID_RMSK 0xf +#define HWIO_TQM_R0_MLO_VC_ID_POR 0x00000000 +#define HWIO_TQM_R0_MLO_VC_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MLO_VC_ID_ATTR 0x3 +#define HWIO_TQM_R0_MLO_VC_ID_IN(x) \ + in_dword(HWIO_TQM_R0_MLO_VC_ID_ADDR(x)) +#define HWIO_TQM_R0_MLO_VC_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MLO_VC_ID_ADDR(x), m) +#define HWIO_TQM_R0_MLO_VC_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MLO_VC_ID_ADDR(x),v) +#define HWIO_TQM_R0_MLO_VC_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MLO_VC_ID_ADDR(x),m,v,HWIO_TQM_R0_MLO_VC_ID_IN(x)) +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_OUT2_MLO_P_SRNG_BMSK 0x8 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_OUT2_MLO_P_SRNG_SHFT 3 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_OUT1_MLO_P_SRNG_BMSK 0x4 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_OUT1_MLO_P_SRNG_SHFT 2 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_IN2_MLO_C_SRNG_BMSK 0x2 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_IN2_MLO_C_SRNG_SHFT 1 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_IN1_MLO_C_SRNG_BMSK 0x1 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_IN1_MLO_C_SRNG_SHFT 0 + +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x) ((x) + 0x768) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_PHYS(x) ((x) + 0x768) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_OFFS (0x768) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_RMSK 0xff +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_POR 0x00000000 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_ATTR 0x3 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_IN(x) \ + in_dword(HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x)) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x), m) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x),v) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x),m,v,HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_IN(x)) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_OUT2_SRNG_P_MLO_BMSK 0xc0 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_OUT2_SRNG_P_MLO_SHFT 6 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_OUT1_SRNG_P_MLO_BMSK 0x30 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_OUT1_SRNG_P_MLO_SHFT 4 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_IN2_SRNG_C_MLO_BMSK 0xc +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_IN2_SRNG_C_MLO_SHFT 2 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_IN1_SRNG_C_MLO_BMSK 0x3 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_IN1_SRNG_C_MLO_SHFT 0 + +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x) ((x) + 0x76c) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_PHYS(x) ((x) + 0x76c) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_OFFS (0x76c) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_RMSK 0x3 +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_POR 0x00000000 +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_ATTR 0x3 +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_IN(x) \ + in_dword(HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x)) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x), m) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x),v) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x),m,v,HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_IN(x)) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_TQM2TQM_OUT2_BMSK 0x2 +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_TQM2TQM_OUT2_SHFT 1 +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_TQM2TQM_OUT1_BMSK 0x1 +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_TQM2TQM_OUT1_SHFT 0 + +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ADDR(x) ((x) + 0x770) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_PHYS(x) ((x) + 0x770) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_OFFS (0x770) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_RMSK 0xfff +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_POR 0x00000003 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ATTR 0x3 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_IN(x) \ + in_dword(HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ADDR(x)) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ADDR(x), m) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ADDR(x),v) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ADDR(x),m,v,HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_IN(x)) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT2_WRITE_THRESHOLD_BMSK 0xf00 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT2_WRITE_THRESHOLD_SHFT 8 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT1_WRITE_THRESHOLD_BMSK 0xf0 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT1_WRITE_THRESHOLD_SHFT 4 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT2_ISSUE_MULTIPLE_TLVS_BMSK 0x8 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT2_ISSUE_MULTIPLE_TLVS_SHFT 3 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT1_ISSUE_MULTIPLE_TLVS_BMSK 0x4 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT1_ISSUE_MULTIPLE_TLVS_SHFT 2 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ENB_TQM2TQM_OUT2_BMSK 0x2 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ENB_TQM2TQM_OUT2_SHFT 1 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ENB_TQM2TQM_OUT1_BMSK 0x1 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ENB_TQM2TQM_OUT1_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) ((x) + 0x2000) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) ((x) + 0x2000) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_OFFS (0x2000) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x1fff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_POR 0x00001000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x1000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 12 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x800 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 11 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x400 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 10 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x3ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) ((x) + 0x2004) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) ((x) + 0x2004) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_OFFS (0x2004) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) ((x) + 0x2008) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) ((x) + 0x2008) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_OFFS (0x2008) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0xffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0xffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) ((x) + 0x200c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) ((x) + 0x200c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OFFS (0x200c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) ((x) + 0x2010) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) ((x) + 0x2010) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OFFS (0x2010) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_ADDR(x) ((x) + 0x2014) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_PHYS(x) ((x) + 0x2014) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_OFFS (0x2014) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_RMSK 0x1ffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x1ffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) ((x) + 0x2018) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) ((x) + 0x2018) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_OFFS (0x2018) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0x3fffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x3ff800 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 11 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x7ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x) ((x) + 0x201c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_PHYS(x) ((x) + 0x201c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_OFFS (0x201c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK 0x3fffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_BMSK 0x3ff800 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_SHFT 11 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_BMSK 0x7ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x) ((x) + 0x2020) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_PHYS(x) ((x) + 0x2020) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_OFFS (0x2020) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK 0x3fffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_BMSK 0x3ff800 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_SHFT 11 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_BMSK 0x7ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x) ((x) + 0x2024) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_PHYS(x) ((x) + 0x2024) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_OFFS (0x2024) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK 0x3fffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_BMSK 0x3ff800 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_SHFT 11 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_BMSK 0x7ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x) ((x) + 0x2028) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_PHYS(x) ((x) + 0x2028) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OFFS (0x2028) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x) ((x) + 0x202c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_PHYS(x) ((x) + 0x202c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OFFS (0x202c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x) ((x) + 0x2030) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_PHYS(x) ((x) + 0x2030) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OFFS (0x2030) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK 0xfffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_BMSK 0xffc00 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_SHFT 10 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_BMSK 0x3ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x2034) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x2034) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_OFFS (0x2034) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x) ((x) + 0x2038) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_PHYS(x) ((x) + 0x2038) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OFFS (0x2038) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK 0x7ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_BMSK 0x7f8 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_SHFT 3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_BMSK 0x4 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_SHFT 2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_BMSK 0x2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_SHFT 1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_BMSK 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x) ((x) + 0x203c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_PHYS(x) ((x) + 0x203c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OFFS (0x203c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x) ((x) + 0x2040) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_PHYS(x) ((x) + 0x2040) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OFFS (0x2040) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_BMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x) ((x) + 0x2044) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_PHYS(x) ((x) + 0x2044) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OFFS (0x2044) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK 0x3fffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_POR 0x00000001 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_BMSK 0x3fc00000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_SHFT 22 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_BMSK 0x3ff000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_SHFT 12 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_BMSK 0x800 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_SHFT 11 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_BMSK 0x600 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_SHFT 9 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_BMSK 0x1e0 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_SHFT 5 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_BMSK 0x1c +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_SHFT 2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_BMSK 0x2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_SHFT 1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_BMSK 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR(x) ((x) + 0x2048) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_PHYS(x) ((x) + 0x2048) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_OFFS (0x2048) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_RMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ACT_ADDR_BMSK 0xf0 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ACT_ADDR_SHFT 4 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_EXP_ADDR_BMSK 0xf +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_EXP_ADDR_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_TQM_R1_PREFETCH_BUF_ADDR(x) ((x) + 0x2054) +#define HWIO_TQM_R1_PREFETCH_BUF_PHYS(x) ((x) + 0x2054) +#define HWIO_TQM_R1_PREFETCH_BUF_OFFS (0x2054) +#define HWIO_TQM_R1_PREFETCH_BUF_RMSK 0x7ff +#define HWIO_TQM_R1_PREFETCH_BUF_POR 0x00000000 +#define HWIO_TQM_R1_PREFETCH_BUF_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_PREFETCH_BUF_ATTR 0x3 +#define HWIO_TQM_R1_PREFETCH_BUF_IN(x) \ + in_dword(HWIO_TQM_R1_PREFETCH_BUF_ADDR(x)) +#define HWIO_TQM_R1_PREFETCH_BUF_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_PREFETCH_BUF_ADDR(x), m) +#define HWIO_TQM_R1_PREFETCH_BUF_OUT(x, v) \ + out_dword(HWIO_TQM_R1_PREFETCH_BUF_ADDR(x),v) +#define HWIO_TQM_R1_PREFETCH_BUF_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_PREFETCH_BUF_ADDR(x),m,v,HWIO_TQM_R1_PREFETCH_BUF_IN(x)) +#define HWIO_TQM_R1_PREFETCH_BUF_ADDR_BMSK 0x7ff +#define HWIO_TQM_R1_PREFETCH_BUF_ADDR_SHFT 0 + +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_ADDR(x) ((x) + 0x2058) +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_PHYS(x) ((x) + 0x2058) +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_OFFS (0x2058) +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_RMSK 0xffffffff +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_POR 0x00000000 +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_ATTR 0x1 +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_IN(x) \ + in_dword(HWIO_TQM_R1_PREFETCH_BUF_DATA_ADDR(x)) +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_PREFETCH_BUF_DATA_ADDR(x), m) +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_BUF_ADDR(x) ((x) + 0x205c) +#define HWIO_TQM_R1_CACHE_BUF_PHYS(x) ((x) + 0x205c) +#define HWIO_TQM_R1_CACHE_BUF_OFFS (0x205c) +#define HWIO_TQM_R1_CACHE_BUF_RMSK 0x7fff +#define HWIO_TQM_R1_CACHE_BUF_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_BUF_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_BUF_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_BUF_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_BUF_ADDR(x)) +#define HWIO_TQM_R1_CACHE_BUF_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_BUF_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_BUF_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_BUF_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_BUF_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_BUF_ADDR(x),m,v,HWIO_TQM_R1_CACHE_BUF_IN(x)) +#define HWIO_TQM_R1_CACHE_BUF_ADDR_BMSK 0x7fff +#define HWIO_TQM_R1_CACHE_BUF_ADDR_SHFT 0 + +#define HWIO_TQM_R1_CACHE_BUF_DATA_ADDR(x) ((x) + 0x2060) +#define HWIO_TQM_R1_CACHE_BUF_DATA_PHYS(x) ((x) + 0x2060) +#define HWIO_TQM_R1_CACHE_BUF_DATA_OFFS (0x2060) +#define HWIO_TQM_R1_CACHE_BUF_DATA_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_BUF_DATA_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_BUF_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_BUF_DATA_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_BUF_DATA_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_BUF_DATA_ADDR(x)) +#define HWIO_TQM_R1_CACHE_BUF_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_BUF_DATA_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_BUF_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_BUF_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_ADDR(x) ((x) + 0x2064) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_PHYS(x) ((x) + 0x2064) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_OFFS (0x2064) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_RMSK 0x3 +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_POR 0x00000000 +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_ATTR 0x3 +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_IN(x) \ + in_dword(HWIO_TQM_R1_MISC_DEBUG_CTRL_ADDR(x)) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_MISC_DEBUG_CTRL_ADDR(x), m) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R1_MISC_DEBUG_CTRL_ADDR(x),v) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_MISC_DEBUG_CTRL_ADDR(x),m,v,HWIO_TQM_R1_MISC_DEBUG_CTRL_IN(x)) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_IDLE_REQ_BMSK 0x2 +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_IDLE_REQ_SHFT 1 +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_IDLE_REQ_DONE_BMSK 0x1 +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_IDLE_REQ_DONE_SHFT 0 + +#define HWIO_TQM_R1_LOG_ADDR(x) ((x) + 0x2068) +#define HWIO_TQM_R1_LOG_PHYS(x) ((x) + 0x2068) +#define HWIO_TQM_R1_LOG_OFFS (0x2068) +#define HWIO_TQM_R1_LOG_RMSK 0xfffffff +#define HWIO_TQM_R1_LOG_POR 0x0fffffff +#define HWIO_TQM_R1_LOG_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_ATTR 0x1 +#define HWIO_TQM_R1_LOG_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_ADDR(x)) +#define HWIO_TQM_R1_LOG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_ADDR(x), m) +#define HWIO_TQM_R1_LOG_CURR_CMD_IDX_BMSK 0xf000000 +#define HWIO_TQM_R1_LOG_CURR_CMD_IDX_SHFT 24 +#define HWIO_TQM_R1_LOG_CURR_CMD_NUM_BMSK 0xffffff +#define HWIO_TQM_R1_LOG_CURR_CMD_NUM_SHFT 0 + +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_ADDR(x) ((x) + 0x206c) +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_PHYS(x) ((x) + 0x206c) +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_OFFS (0x206c) +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_RMSK 0x3fffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_POR 0x00000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_ATTR 0x1 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_IN(x) \ + in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX0_ADDR(x)) +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX0_ADDR(x), m) +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_GET_QUEUE_STATS_SM_BMSK 0x3e000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_GET_QUEUE_STATS_SM_SHFT 25 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_GET_MPDU_HEAD_INFO_SM_BMSK 0x1e00000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_GET_MPDU_HEAD_INFO_SM_SHFT 21 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_FLUSH_AND_UNBLOCK_CACHE_SM_BMSK 0x180000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_FLUSH_AND_UNBLOCK_CACHE_SM_SHFT 19 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_ADD_MPDU_LINK_SM_BMSK 0x78000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_ADD_MPDU_LINK_SM_SHFT 15 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_CREATE_MPDU_SM_BMSK 0x7c00 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_CREATE_MPDU_SM_SHFT 10 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_GEN_MPDU_SM_BMSK 0x3e0 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_GEN_MPDU_SM_SHFT 5 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_ADD_MSDU_SM_BMSK 0x1f +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_ADD_MSDU_SM_SHFT 0 + +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_ADDR(x) ((x) + 0x2070) +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_PHYS(x) ((x) + 0x2070) +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_OFFS (0x2070) +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_RMSK 0xffffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_POR 0x00000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_ATTR 0x1 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_IN(x) \ + in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX1_ADDR(x)) +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX1_ADDR(x), m) +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_ARB_STATUS_BLK1_SM_BMSK 0xc0000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_ARB_STATUS_BLK1_SM_SHFT 30 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_ARB_STATUS_BLK0_SM_BMSK 0x30000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_ARB_STATUS_BLK0_SM_SHFT 28 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_UPDATE_TX_MPDU_COUNT_SM_BMSK 0xf800000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_UPDATE_TX_MPDU_COUNT_SM_SHFT 23 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_REM_MSDU_SM_BMSK 0x7c0000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_REM_MSDU_SM_SHFT 18 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_REM_MPDU_SM_BMSK 0x3f000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_REM_MPDU_SM_SHFT 12 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_WRITE_CMD_SM_BMSK 0xe00 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_WRITE_CMD_SM_SHFT 9 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_LIST_MPDU_MAIN_SM_BMSK 0x1f0 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_LIST_MPDU_MAIN_SM_SHFT 4 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_LIST_TLV_SM_BMSK 0xf +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_LIST_TLV_SM_SHFT 0 + +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ADDR(x) ((x) + 0x2074) +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_PHYS(x) ((x) + 0x2074) +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_OFFS (0x2074) +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_RMSK 0xffffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_POR 0x00000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ATTR 0x1 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_IN(x) \ + in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX2_ADDR(x)) +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX2_ADDR(x), m) +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_ASYNC_SM_BMSK 0x80000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_ASYNC_SM_SHFT 31 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_MSDU_ENT_SM_BMSK 0x70000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_MSDU_ENT_SM_SHFT 28 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_SW_CMD_SM_BMSK 0xf000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_SW_CMD_SM_SHFT 24 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_HWSCH_CMD_SM_BMSK 0xf00000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_HWSCH_CMD_SM_SHFT 20 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_PREFETCH_READ_SM_BMSK 0xc0000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_PREFETCH_READ_SM_SHFT 18 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_PREFETCH_SM_BMSK 0x3ffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_PREFETCH_SM_SHFT 0 + +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_ADDR(x) ((x) + 0x2078) +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_PHYS(x) ((x) + 0x2078) +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_OFFS (0x2078) +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_RMSK 0xffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_POR 0x00000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_ATTR 0x1 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_IN(x) \ + in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX3_ADDR(x)) +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX3_ADDR(x), m) +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_PREFETCH_SM_BMSK 0xff0000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_PREFETCH_SM_SHFT 16 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_TQM2TQM_OUT2_SM_STATE_BMSK 0xc000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_TQM2TQM_OUT2_SM_STATE_SHFT 14 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_TQM2TQM_OUT1_SM_STATE_BMSK 0x3000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_TQM2TQM_OUT1_SM_STATE_SHFT 12 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_UPDATE_QUEUE_DESC_SM_BMSK 0xf80 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_UPDATE_QUEUE_DESC_SM_SHFT 7 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_AXI_TO_TLV_SM_BMSK 0x60 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_AXI_TO_TLV_SM_SHFT 5 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_LIST_TLV_STATE_BMSK 0x1c +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_LIST_TLV_STATE_SHFT 2 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_DATA_ALIGN_SM_BMSK 0x3 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_DATA_ALIGN_SM_SHFT 0 + +#define HWIO_TQM_R1_CCMN_IDLE_ADDR(x) ((x) + 0x207c) +#define HWIO_TQM_R1_CCMN_IDLE_PHYS(x) ((x) + 0x207c) +#define HWIO_TQM_R1_CCMN_IDLE_OFFS (0x207c) +#define HWIO_TQM_R1_CCMN_IDLE_RMSK 0xffffffff +#define HWIO_TQM_R1_CCMN_IDLE_POR 0x00000000 +#define HWIO_TQM_R1_CCMN_IDLE_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CCMN_IDLE_ATTR 0x1 +#define HWIO_TQM_R1_CCMN_IDLE_IN(x) \ + in_dword(HWIO_TQM_R1_CCMN_IDLE_ADDR(x)) +#define HWIO_TQM_R1_CCMN_IDLE_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CCMN_IDLE_ADDR(x), m) +#define HWIO_TQM_R1_CCMN_IDLE_SOURCES_BMSK 0xffffffff +#define HWIO_TQM_R1_CCMN_IDLE_SOURCES_SHFT 0 + +#define HWIO_TQM_R1_CURRENT_COMMAND_ADDR(x) ((x) + 0x2080) +#define HWIO_TQM_R1_CURRENT_COMMAND_PHYS(x) ((x) + 0x2080) +#define HWIO_TQM_R1_CURRENT_COMMAND_OFFS (0x2080) +#define HWIO_TQM_R1_CURRENT_COMMAND_RMSK 0xffffffff +#define HWIO_TQM_R1_CURRENT_COMMAND_POR 0x00000000 +#define HWIO_TQM_R1_CURRENT_COMMAND_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CURRENT_COMMAND_ATTR 0x1 +#define HWIO_TQM_R1_CURRENT_COMMAND_IN(x) \ + in_dword(HWIO_TQM_R1_CURRENT_COMMAND_ADDR(x)) +#define HWIO_TQM_R1_CURRENT_COMMAND_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CURRENT_COMMAND_ADDR(x), m) +#define HWIO_TQM_R1_CURRENT_COMMAND_POINTER_BMSK 0xf0000000 +#define HWIO_TQM_R1_CURRENT_COMMAND_POINTER_SHFT 28 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_6_BMSK 0xf000000 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_6_SHFT 24 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_5_BMSK 0xf00000 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_5_SHFT 20 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_4_BMSK 0xf0000 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_4_SHFT 16 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_3_BMSK 0xf000 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_3_SHFT 12 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_2_BMSK 0xf00 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_2_SHFT 8 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_1_BMSK 0xf0 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_1_SHFT 4 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_0_BMSK 0xf +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_0_SHFT 0 + +#define HWIO_TQM_R1_LOG_ADD_MSDU_ADDR(x) ((x) + 0x2084) +#define HWIO_TQM_R1_LOG_ADD_MSDU_PHYS(x) ((x) + 0x2084) +#define HWIO_TQM_R1_LOG_ADD_MSDU_OFFS (0x2084) +#define HWIO_TQM_R1_LOG_ADD_MSDU_RMSK 0xffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_POR 0x00ffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_ATTR 0x1 +#define HWIO_TQM_R1_LOG_ADD_MSDU_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_ADD_MSDU_ADDR(x)) +#define HWIO_TQM_R1_LOG_ADD_MSDU_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_ADD_MSDU_ADDR(x), m) +#define HWIO_TQM_R1_LOG_ADD_MSDU_CURR_CMD_NUM_BMSK 0xffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_CURR_CMD_NUM_SHFT 0 + +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_ADDR(x) ((x) + 0x2088) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_PHYS(x) ((x) + 0x2088) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_OFFS (0x2088) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_RMSK 0x3fffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_POR 0x00000000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_ATTR 0x1 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_TIMESTAMP_IX0_ADDR(x)) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_TIMESTAMP_IX0_ADDR(x), m) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INDEX_2_BMSK 0x3ff00000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INDEX_2_SHFT 20 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INDEX_1_BMSK 0xffc00 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INDEX_1_SHFT 10 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INDEX_0_BMSK 0x3ff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INDEX_0_SHFT 0 + +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_ADDR(x) ((x) + 0x208c) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_PHYS(x) ((x) + 0x208c) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_OFFS (0x208c) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_RMSK 0x3fffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_POR 0x00000000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_ATTR 0x1 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_TIMESTAMP_IX1_ADDR(x)) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_TIMESTAMP_IX1_ADDR(x), m) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INDEX_5_BMSK 0x3ff00000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INDEX_5_SHFT 20 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INDEX_4_BMSK 0xffc00 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INDEX_4_SHFT 10 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INDEX_3_BMSK 0x3ff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INDEX_3_SHFT 0 + +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_ADDR(x) ((x) + 0x2090) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_PHYS(x) ((x) + 0x2090) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_OFFS (0x2090) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_RMSK 0x7fffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_POR 0x00000000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_ATTR 0x1 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_TIMESTAMP_IX2_ADDR(x)) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_TIMESTAMP_IX2_ADDR(x), m) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_POINTER_BMSK 0x700000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_POINTER_SHFT 20 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_INDEX_7_BMSK 0xffc00 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_INDEX_7_SHFT 10 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_INDEX_6_BMSK 0x3ff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_INDEX_6_SHFT 0 + +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_ADDR(x) ((x) + 0x2094) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_PHYS(x) ((x) + 0x2094) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_OFFS (0x2094) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_POR 0x00000000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_ATTR 0x1 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_TIMESTAMP_IX3_ADDR(x)) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_TIMESTAMP_IX3_ADDR(x), m) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_WATCHDOG_SNAPSHOT_BMSK 0xfffffc00 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_WATCHDOG_SNAPSHOT_SHFT 10 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_TIMESTAMP_BMSK 0x3ff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_TIMESTAMP_SHFT 0 + +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_ADDR(x) ((x) + 0x2098) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_PHYS(x) ((x) + 0x2098) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_OFFS (0x2098) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_RMSK 0xffffffff +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_POR 0x00000000 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_ATTR 0x1 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_IN(x) \ + in_dword(HWIO_TQM_R1_WATCHDOG_STATUS_IX0_ADDR(x)) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WATCHDOG_STATUS_IX0_ADDR(x), m) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_SW_SM_WATCHDOG_BMSK 0xffff0000 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_SW_SM_WATCHDOG_SHFT 16 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_HW_SM_WATCHDOG_BMSK 0xffff +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_HW_SM_WATCHDOG_SHFT 0 + +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_ADDR(x) ((x) + 0x209c) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_PHYS(x) ((x) + 0x209c) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_OFFS (0x209c) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_RMSK 0x1fffff +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_POR 0x00000000 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_ATTR 0x1 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_IN(x) \ + in_dword(HWIO_TQM_R1_WATCHDOG_STATUS_IX1_ADDR(x)) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WATCHDOG_STATUS_IX1_ADDR(x), m) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_IDLE_SEQUENCE_SM_BMSK 0x1f0000 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_IDLE_SEQUENCE_SM_SHFT 16 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_ENTRANCE_SM_WATCHDOG_BMSK 0xffff +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_ENTRANCE_SM_WATCHDOG_SHFT 0 + +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_ADDR(x) ((x) + 0x20a0) +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_PHYS(x) ((x) + 0x20a0) +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_OFFS (0x20a0) +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_POR 0x00000000 +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_ATTR 0x1 +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_ADDR(x)) +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_ADDR(x), m) +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_ADDRESS_BMSK 0xffffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_ADDRESS_SHFT 0 + +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_ADDR(x) ((x) + 0x20a4) +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_PHYS(x) ((x) + 0x20a4) +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_OFFS (0x20a4) +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_POR 0x00000000 +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_ATTR 0x1 +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_ADDR(x)) +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_ADDR(x), m) +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_ADDRESS_BMSK 0xffffffff +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_ADDRESS_SHFT 0 + +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_ADDR(x) ((x) + 0x20a8) +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_PHYS(x) ((x) + 0x20a8) +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_OFFS (0x20a8) +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_RMSK 0x7fffffff +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_POR 0x71d1e1a1 +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_ATTR 0x1 +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_IN(x) \ + in_dword(HWIO_TQM_R1_IDLE_SEQUENCE_LOG_ADDR(x)) +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_IDLE_SEQUENCE_LOG_ADDR(x), m) +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_TIMER_1_BMSK 0x7fff0000 +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_TIMER_1_SHFT 16 +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_TIMER_0_BMSK 0xfffe +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_TIMER_0_SHFT 1 +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_INDEX_BMSK 0x1 +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_INDEX_SHFT 0 + +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_ADDR(x) ((x) + 0x20ac) +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_PHYS(x) ((x) + 0x20ac) +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_OFFS (0x20ac) +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_RMSK 0x3ffff3f +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_ADDR(x)) +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_FREE_SLOTS_BMSK 0x3ff0000 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_FREE_SLOTS_SHFT 16 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_CURR_REQ_LEN_BMSK 0xff00 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_CURR_REQ_LEN_SHFT 8 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_FLUSH_STATE_BMSK 0x30 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_FLUSH_STATE_SHFT 4 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_SM_STATE_BMSK 0xe +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_SM_STATE_SHFT 1 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_IDLE_BMSK 0x1 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_IDLE_SHFT 0 + +#define HWIO_TQM_R1_SCH2TQM0_STATUS_ADDR(x) ((x) + 0x20b0) +#define HWIO_TQM_R1_SCH2TQM0_STATUS_PHYS(x) ((x) + 0x20b0) +#define HWIO_TQM_R1_SCH2TQM0_STATUS_OFFS (0x20b0) +#define HWIO_TQM_R1_SCH2TQM0_STATUS_RMSK 0x7fffffff +#define HWIO_TQM_R1_SCH2TQM0_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_SCH2TQM0_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_SCH2TQM0_STATUS_ADDR(x)) +#define HWIO_TQM_R1_SCH2TQM0_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_SCH2TQM0_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_SCH2TQM0_STATUS_FLUSH_SESSION_ID_BMSK 0x7f800000 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_FLUSH_SESSION_ID_SHFT 23 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_FLUSH_SRC_ID_BMSK 0x700000 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_FLUSH_SRC_ID_SHFT 20 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_FLUSH_STATUS_BMSK 0xf0000 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_FLUSH_STATUS_SHFT 16 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_HEADER_BMSK 0xffff +#define HWIO_TQM_R1_SCH2TQM0_STATUS_HEADER_SHFT 0 + +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_ADDR(x) ((x) + 0x20b4) +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_PHYS(x) ((x) + 0x20b4) +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_OFFS (0x20b4) +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_RMSK 0x3ffff3f +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_ADDR(x)) +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_FREE_SLOTS_BMSK 0x3ff0000 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_FREE_SLOTS_SHFT 16 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_CURR_REQ_LEN_BMSK 0xff00 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_CURR_REQ_LEN_SHFT 8 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_FLUSH_STATE_BMSK 0x30 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_FLUSH_STATE_SHFT 4 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_SM_STATE_BMSK 0xe +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_SM_STATE_SHFT 1 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_IDLE_BMSK 0x1 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_IDLE_SHFT 0 + +#define HWIO_TQM_R1_SCH2TQM1_STATUS_ADDR(x) ((x) + 0x20b8) +#define HWIO_TQM_R1_SCH2TQM1_STATUS_PHYS(x) ((x) + 0x20b8) +#define HWIO_TQM_R1_SCH2TQM1_STATUS_OFFS (0x20b8) +#define HWIO_TQM_R1_SCH2TQM1_STATUS_RMSK 0x7fffffff +#define HWIO_TQM_R1_SCH2TQM1_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_SCH2TQM1_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_SCH2TQM1_STATUS_ADDR(x)) +#define HWIO_TQM_R1_SCH2TQM1_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_SCH2TQM1_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_SCH2TQM1_STATUS_FLUSH_SESSION_ID_BMSK 0x7f800000 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_FLUSH_SESSION_ID_SHFT 23 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_FLUSH_SRC_ID_BMSK 0x700000 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_FLUSH_SRC_ID_SHFT 20 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_FLUSH_STATUS_BMSK 0xf0000 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_FLUSH_STATUS_SHFT 16 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_HEADER_BMSK 0xffff +#define HWIO_TQM_R1_SCH2TQM1_STATUS_HEADER_SHFT 0 + +#define HWIO_TQM_R1_FLUSH_ADDR(x) ((x) + 0x20bc) +#define HWIO_TQM_R1_FLUSH_PHYS(x) ((x) + 0x20bc) +#define HWIO_TQM_R1_FLUSH_OFFS (0x20bc) +#define HWIO_TQM_R1_FLUSH_RMSK 0xffffffff +#define HWIO_TQM_R1_FLUSH_POR 0x00000000 +#define HWIO_TQM_R1_FLUSH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_FLUSH_ATTR 0x3 +#define HWIO_TQM_R1_FLUSH_IN(x) \ + in_dword(HWIO_TQM_R1_FLUSH_ADDR(x)) +#define HWIO_TQM_R1_FLUSH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_FLUSH_ADDR(x), m) +#define HWIO_TQM_R1_FLUSH_OUT(x, v) \ + out_dword(HWIO_TQM_R1_FLUSH_ADDR(x),v) +#define HWIO_TQM_R1_FLUSH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_FLUSH_ADDR(x),m,v,HWIO_TQM_R1_FLUSH_IN(x)) +#define HWIO_TQM_R1_FLUSH_BACKUP_10_BMSK 0x80000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_10_SHFT 31 +#define HWIO_TQM_R1_FLUSH_BACKUP_9_BMSK 0x40000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_9_SHFT 30 +#define HWIO_TQM_R1_FLUSH_BACKUP_8_BMSK 0x20000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_8_SHFT 29 +#define HWIO_TQM_R1_FLUSH_BACKUP_7_BMSK 0x10000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_7_SHFT 28 +#define HWIO_TQM_R1_FLUSH_BACKUP_6_BMSK 0x8000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_6_SHFT 27 +#define HWIO_TQM_R1_FLUSH_BACKUP_5_BMSK 0x4000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_5_SHFT 26 +#define HWIO_TQM_R1_FLUSH_BACKUP_4_BMSK 0x2000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_4_SHFT 25 +#define HWIO_TQM_R1_FLUSH_BACKUP_3_BMSK 0x1000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_3_SHFT 24 +#define HWIO_TQM_R1_FLUSH_BACKUP_2_BMSK 0x800000 +#define HWIO_TQM_R1_FLUSH_BACKUP_2_SHFT 23 +#define HWIO_TQM_R1_FLUSH_BACKUP_1_BMSK 0x400000 +#define HWIO_TQM_R1_FLUSH_BACKUP_1_SHFT 22 +#define HWIO_TQM_R1_FLUSH_BACKUP_0_BMSK 0x200000 +#define HWIO_TQM_R1_FLUSH_BACKUP_0_SHFT 21 +#define HWIO_TQM_R1_FLUSH_CMD_AND_PTR_PREFETCH_FLUSH_P_BMSK 0x100000 +#define HWIO_TQM_R1_FLUSH_CMD_AND_PTR_PREFETCH_FLUSH_P_SHFT 20 +#define HWIO_TQM_R1_FLUSH_CMD_ARBITER_FLUSH_P_BMSK 0x80000 +#define HWIO_TQM_R1_FLUSH_CMD_ARBITER_FLUSH_P_SHFT 19 +#define HWIO_TQM_R1_FLUSH_COMMON_LOGIC_FLUSH_P_BMSK 0x40000 +#define HWIO_TQM_R1_FLUSH_COMMON_LOGIC_FLUSH_P_SHFT 18 +#define HWIO_TQM_R1_FLUSH_ADD_MSDU_SM_FLUSH_P_BMSK 0x20000 +#define HWIO_TQM_R1_FLUSH_ADD_MSDU_SM_FLUSH_P_SHFT 17 +#define HWIO_TQM_R1_FLUSH_GEN_MPDU_SM_FLUSH_P_BMSK 0x10000 +#define HWIO_TQM_R1_FLUSH_GEN_MPDU_SM_FLUSH_P_SHFT 16 +#define HWIO_TQM_R1_FLUSH_UPDATE_TX_MPDU_COUNT_SM_FLUSH_P_BMSK 0x8000 +#define HWIO_TQM_R1_FLUSH_UPDATE_TX_MPDU_COUNT_SM_FLUSH_P_SHFT 15 +#define HWIO_TQM_R1_FLUSH_LIST_MPDU_SM_FLUSH_P_BMSK 0x4000 +#define HWIO_TQM_R1_FLUSH_LIST_MPDU_SM_FLUSH_P_SHFT 14 +#define HWIO_TQM_R1_FLUSH_WRITE_CMD_SM_FLUSH_P_BMSK 0x2000 +#define HWIO_TQM_R1_FLUSH_WRITE_CMD_SM_FLUSH_P_SHFT 13 +#define HWIO_TQM_R1_FLUSH_ACKED_MPDU_SM_FLUSH_P_BMSK 0x1000 +#define HWIO_TQM_R1_FLUSH_ACKED_MPDU_SM_FLUSH_P_SHFT 12 +#define HWIO_TQM_R1_FLUSH_REM_MPDU_SM_FLUSH_P_BMSK 0x800 +#define HWIO_TQM_R1_FLUSH_REM_MPDU_SM_FLUSH_P_SHFT 11 +#define HWIO_TQM_R1_FLUSH_REM_MSDU_SM_FLUSH_P_BMSK 0x400 +#define HWIO_TQM_R1_FLUSH_REM_MSDU_SM_FLUSH_P_SHFT 10 +#define HWIO_TQM_R1_FLUSH_HWSCH_AXI_IF_FLUSH_P_BMSK 0x200 +#define HWIO_TQM_R1_FLUSH_HWSCH_AXI_IF_FLUSH_P_SHFT 9 +#define HWIO_TQM_R1_FLUSH_AXI_TO_TLV_FLUSH_P_BMSK 0x100 +#define HWIO_TQM_R1_FLUSH_AXI_TO_TLV_FLUSH_P_SHFT 8 +#define HWIO_TQM_R1_FLUSH_GET_MPDU_HEAD_INFO_SM_FLUSH_P_BMSK 0x80 +#define HWIO_TQM_R1_FLUSH_GET_MPDU_HEAD_INFO_SM_FLUSH_P_SHFT 7 +#define HWIO_TQM_R1_FLUSH_GET_MPDU_QUEUE_STAT_SM_FLUSH_P_BMSK 0x40 +#define HWIO_TQM_R1_FLUSH_GET_MPDU_QUEUE_STAT_SM_FLUSH_P_SHFT 6 +#define HWIO_TQM_R1_FLUSH_GET_MSDU_FLOW_STAT_SM_FLUSH_P_BMSK 0x20 +#define HWIO_TQM_R1_FLUSH_GET_MSDU_FLOW_STAT_SM_FLUSH_P_SHFT 5 +#define HWIO_TQM_R1_FLUSH_FLUSH_CACHE_SM_FLUSH_P_BMSK 0x10 +#define HWIO_TQM_R1_FLUSH_FLUSH_CACHE_SM_FLUSH_P_SHFT 4 +#define HWIO_TQM_R1_FLUSH_UNBLOCK_CACHE_SM_FLUSH_P_BMSK 0x8 +#define HWIO_TQM_R1_FLUSH_UNBLOCK_CACHE_SM_FLUSH_P_SHFT 3 +#define HWIO_TQM_R1_FLUSH_UPDATE_TX_MPDU_QUEUE_HEAD_SM_FLUSH_P_BMSK 0x4 +#define HWIO_TQM_R1_FLUSH_UPDATE_TX_MPDU_QUEUE_HEAD_SM_FLUSH_P_SHFT 2 +#define HWIO_TQM_R1_FLUSH_UPDATE_TX_MSDU_FLOW_SM_FLUSH_P_BMSK 0x2 +#define HWIO_TQM_R1_FLUSH_UPDATE_TX_MSDU_FLOW_SM_FLUSH_P_SHFT 1 +#define HWIO_TQM_R1_FLUSH_TQM_IDLE_SEQUENCE_FLUSH_P_BMSK 0x1 +#define HWIO_TQM_R1_FLUSH_TQM_IDLE_SEQUENCE_FLUSH_P_SHFT 0 + +#define HWIO_TQM_R1_WARN_WDG_0_ADDR(x) ((x) + 0x20c0) +#define HWIO_TQM_R1_WARN_WDG_0_PHYS(x) ((x) + 0x20c0) +#define HWIO_TQM_R1_WARN_WDG_0_OFFS (0x20c0) +#define HWIO_TQM_R1_WARN_WDG_0_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_0_POR 0x00000000 +#define HWIO_TQM_R1_WARN_WDG_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_0_ATTR 0x3 +#define HWIO_TQM_R1_WARN_WDG_0_IN(x) \ + in_dword(HWIO_TQM_R1_WARN_WDG_0_ADDR(x)) +#define HWIO_TQM_R1_WARN_WDG_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WARN_WDG_0_ADDR(x), m) +#define HWIO_TQM_R1_WARN_WDG_0_OUT(x, v) \ + out_dword(HWIO_TQM_R1_WARN_WDG_0_ADDR(x),v) +#define HWIO_TQM_R1_WARN_WDG_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_WARN_WDG_0_ADDR(x),m,v,HWIO_TQM_R1_WARN_WDG_0_IN(x)) +#define HWIO_TQM_R1_WARN_WDG_0_RELEASE_FIFO_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_WARN_WDG_0_RELEASE_FIFO_STATUS_SHFT 16 +#define HWIO_TQM_R1_WARN_WDG_0_RELEASE_FIFO_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_WARN_WDG_0_RELEASE_FIFO_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_WARN_WDG_1_ADDR(x) ((x) + 0x20c4) +#define HWIO_TQM_R1_WARN_WDG_1_PHYS(x) ((x) + 0x20c4) +#define HWIO_TQM_R1_WARN_WDG_1_OFFS (0x20c4) +#define HWIO_TQM_R1_WARN_WDG_1_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_1_POR 0x00000000 +#define HWIO_TQM_R1_WARN_WDG_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_1_ATTR 0x3 +#define HWIO_TQM_R1_WARN_WDG_1_IN(x) \ + in_dword(HWIO_TQM_R1_WARN_WDG_1_ADDR(x)) +#define HWIO_TQM_R1_WARN_WDG_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WARN_WDG_1_ADDR(x), m) +#define HWIO_TQM_R1_WARN_WDG_1_OUT(x, v) \ + out_dword(HWIO_TQM_R1_WARN_WDG_1_ADDR(x),v) +#define HWIO_TQM_R1_WARN_WDG_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_WARN_WDG_1_ADDR(x),m,v,HWIO_TQM_R1_WARN_WDG_1_IN(x)) +#define HWIO_TQM_R1_WARN_WDG_1_DESC_RING_FIFO_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_WARN_WDG_1_DESC_RING_FIFO_STATUS_SHFT 16 +#define HWIO_TQM_R1_WARN_WDG_1_DESC_RING_FIFO_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_WARN_WDG_1_DESC_RING_FIFO_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_WARN_WDG_2_ADDR(x) ((x) + 0x20c8) +#define HWIO_TQM_R1_WARN_WDG_2_PHYS(x) ((x) + 0x20c8) +#define HWIO_TQM_R1_WARN_WDG_2_OFFS (0x20c8) +#define HWIO_TQM_R1_WARN_WDG_2_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_2_POR 0x00000000 +#define HWIO_TQM_R1_WARN_WDG_2_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_2_ATTR 0x3 +#define HWIO_TQM_R1_WARN_WDG_2_IN(x) \ + in_dword(HWIO_TQM_R1_WARN_WDG_2_ADDR(x)) +#define HWIO_TQM_R1_WARN_WDG_2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WARN_WDG_2_ADDR(x), m) +#define HWIO_TQM_R1_WARN_WDG_2_OUT(x, v) \ + out_dword(HWIO_TQM_R1_WARN_WDG_2_ADDR(x),v) +#define HWIO_TQM_R1_WARN_WDG_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_WARN_WDG_2_ADDR(x),m,v,HWIO_TQM_R1_WARN_WDG_2_IN(x)) +#define HWIO_TQM_R1_WARN_WDG_2_STATUS_RING_FIFO_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_WARN_WDG_2_STATUS_RING_FIFO_STATUS_SHFT 16 +#define HWIO_TQM_R1_WARN_WDG_2_STATUS_RING_FIFO_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_WARN_WDG_2_STATUS_RING_FIFO_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_WARN_WDG_3_ADDR(x) ((x) + 0x20cc) +#define HWIO_TQM_R1_WARN_WDG_3_PHYS(x) ((x) + 0x20cc) +#define HWIO_TQM_R1_WARN_WDG_3_OFFS (0x20cc) +#define HWIO_TQM_R1_WARN_WDG_3_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_3_POR 0x00000000 +#define HWIO_TQM_R1_WARN_WDG_3_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_3_ATTR 0x3 +#define HWIO_TQM_R1_WARN_WDG_3_IN(x) \ + in_dword(HWIO_TQM_R1_WARN_WDG_3_ADDR(x)) +#define HWIO_TQM_R1_WARN_WDG_3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WARN_WDG_3_ADDR(x), m) +#define HWIO_TQM_R1_WARN_WDG_3_OUT(x, v) \ + out_dword(HWIO_TQM_R1_WARN_WDG_3_ADDR(x),v) +#define HWIO_TQM_R1_WARN_WDG_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_WARN_WDG_3_ADDR(x),m,v,HWIO_TQM_R1_WARN_WDG_3_IN(x)) +#define HWIO_TQM_R1_WARN_WDG_3_STATUS1_RING_FIFO_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_WARN_WDG_3_STATUS1_RING_FIFO_STATUS_SHFT 16 +#define HWIO_TQM_R1_WARN_WDG_3_STATUS1_RING_FIFO_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_WARN_WDG_3_STATUS1_RING_FIFO_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_WARN_WDG_4_ADDR(x) ((x) + 0x20d0) +#define HWIO_TQM_R1_WARN_WDG_4_PHYS(x) ((x) + 0x20d0) +#define HWIO_TQM_R1_WARN_WDG_4_OFFS (0x20d0) +#define HWIO_TQM_R1_WARN_WDG_4_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_4_POR 0x00000000 +#define HWIO_TQM_R1_WARN_WDG_4_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_4_ATTR 0x3 +#define HWIO_TQM_R1_WARN_WDG_4_IN(x) \ + in_dword(HWIO_TQM_R1_WARN_WDG_4_ADDR(x)) +#define HWIO_TQM_R1_WARN_WDG_4_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WARN_WDG_4_ADDR(x), m) +#define HWIO_TQM_R1_WARN_WDG_4_OUT(x, v) \ + out_dword(HWIO_TQM_R1_WARN_WDG_4_ADDR(x),v) +#define HWIO_TQM_R1_WARN_WDG_4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_WARN_WDG_4_ADDR(x),m,v,HWIO_TQM_R1_WARN_WDG_4_IN(x)) +#define HWIO_TQM_R1_WARN_WDG_4_TLV_FIFO_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_WARN_WDG_4_TLV_FIFO_STATUS_SHFT 16 +#define HWIO_TQM_R1_WARN_WDG_4_TLV_FIFO_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_WARN_WDG_4_TLV_FIFO_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_ADDR(x) ((x) + 0x20d4) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_PHYS(x) ((x) + 0x20d4) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_OFFS (0x20d4) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_RMSK 0x1f +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_POR 0x00000000 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_ATTR 0x0 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_IN(x) \ + in_dword(HWIO_TQM_R1_WARN_WDG_STATUS_0_ADDR(x)) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WARN_WDG_STATUS_0_ADDR(x), m) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_OUT(x, v) \ + out_dword(HWIO_TQM_R1_WARN_WDG_STATUS_0_ADDR(x),v) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_WARN_WDG_STATUS_0_ADDR(x),m,v,HWIO_TQM_R1_WARN_WDG_STATUS_0_IN(x)) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_TLV_FIFO_FULL_INTERRUPT_BMSK 0x10 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_TLV_FIFO_FULL_INTERRUPT_SHFT 4 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_STATUS1_RING_FIFO_FULL_INTERRUPT_BMSK 0x8 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_STATUS1_RING_FIFO_FULL_INTERRUPT_SHFT 3 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_STATUS_RING_FIFO_FULL_INTERRUPT_BMSK 0x4 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_STATUS_RING_FIFO_FULL_INTERRUPT_SHFT 2 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_DESC_RING_FIFO_EMPTY_INTERRUPT_BMSK 0x2 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_DESC_RING_FIFO_EMPTY_INTERRUPT_SHFT 1 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_RELEASE_RING_FIFO_FULL_INTERRUPT_BMSK 0x1 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_RELEASE_RING_FIFO_FULL_INTERRUPT_SHFT 0 + +#define HWIO_TQM_R1_ERR_WDG_0_ADDR(x) ((x) + 0x20d8) +#define HWIO_TQM_R1_ERR_WDG_0_PHYS(x) ((x) + 0x20d8) +#define HWIO_TQM_R1_ERR_WDG_0_OFFS (0x20d8) +#define HWIO_TQM_R1_ERR_WDG_0_RMSK 0xffffffff +#define HWIO_TQM_R1_ERR_WDG_0_POR 0x00000000 +#define HWIO_TQM_R1_ERR_WDG_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_ERR_WDG_0_ATTR 0x3 +#define HWIO_TQM_R1_ERR_WDG_0_IN(x) \ + in_dword(HWIO_TQM_R1_ERR_WDG_0_ADDR(x)) +#define HWIO_TQM_R1_ERR_WDG_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_ERR_WDG_0_ADDR(x), m) +#define HWIO_TQM_R1_ERR_WDG_0_OUT(x, v) \ + out_dword(HWIO_TQM_R1_ERR_WDG_0_ADDR(x),v) +#define HWIO_TQM_R1_ERR_WDG_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_ERR_WDG_0_ADDR(x),m,v,HWIO_TQM_R1_ERR_WDG_0_IN(x)) +#define HWIO_TQM_R1_ERR_WDG_0_HW_SM_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_ERR_WDG_0_HW_SM_STATUS_SHFT 16 +#define HWIO_TQM_R1_ERR_WDG_0_HW_SM_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_ERR_WDG_0_HW_SM_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_ERR_WDG_1_ADDR(x) ((x) + 0x20dc) +#define HWIO_TQM_R1_ERR_WDG_1_PHYS(x) ((x) + 0x20dc) +#define HWIO_TQM_R1_ERR_WDG_1_OFFS (0x20dc) +#define HWIO_TQM_R1_ERR_WDG_1_RMSK 0xffffffff +#define HWIO_TQM_R1_ERR_WDG_1_POR 0x00000000 +#define HWIO_TQM_R1_ERR_WDG_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_ERR_WDG_1_ATTR 0x3 +#define HWIO_TQM_R1_ERR_WDG_1_IN(x) \ + in_dword(HWIO_TQM_R1_ERR_WDG_1_ADDR(x)) +#define HWIO_TQM_R1_ERR_WDG_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_ERR_WDG_1_ADDR(x), m) +#define HWIO_TQM_R1_ERR_WDG_1_OUT(x, v) \ + out_dword(HWIO_TQM_R1_ERR_WDG_1_ADDR(x),v) +#define HWIO_TQM_R1_ERR_WDG_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_ERR_WDG_1_ADDR(x),m,v,HWIO_TQM_R1_ERR_WDG_1_IN(x)) +#define HWIO_TQM_R1_ERR_WDG_1_SW_SM_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_ERR_WDG_1_SW_SM_STATUS_SHFT 16 +#define HWIO_TQM_R1_ERR_WDG_1_SW_SM_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_ERR_WDG_1_SW_SM_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_ERR_WDG_2_ADDR(x) ((x) + 0x20e0) +#define HWIO_TQM_R1_ERR_WDG_2_PHYS(x) ((x) + 0x20e0) +#define HWIO_TQM_R1_ERR_WDG_2_OFFS (0x20e0) +#define HWIO_TQM_R1_ERR_WDG_2_RMSK 0xffffffff +#define HWIO_TQM_R1_ERR_WDG_2_POR 0x00000000 +#define HWIO_TQM_R1_ERR_WDG_2_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_ERR_WDG_2_ATTR 0x3 +#define HWIO_TQM_R1_ERR_WDG_2_IN(x) \ + in_dword(HWIO_TQM_R1_ERR_WDG_2_ADDR(x)) +#define HWIO_TQM_R1_ERR_WDG_2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_ERR_WDG_2_ADDR(x), m) +#define HWIO_TQM_R1_ERR_WDG_2_OUT(x, v) \ + out_dword(HWIO_TQM_R1_ERR_WDG_2_ADDR(x),v) +#define HWIO_TQM_R1_ERR_WDG_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_ERR_WDG_2_ADDR(x),m,v,HWIO_TQM_R1_ERR_WDG_2_IN(x)) +#define HWIO_TQM_R1_ERR_WDG_2_ENT_SM_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_ERR_WDG_2_ENT_SM_STATUS_SHFT 16 +#define HWIO_TQM_R1_ERR_WDG_2_ENT_SM_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_ERR_WDG_2_ENT_SM_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_ERROR_STATUS_0_ADDR(x) ((x) + 0x20e4) +#define HWIO_TQM_R1_ERROR_STATUS_0_PHYS(x) ((x) + 0x20e4) +#define HWIO_TQM_R1_ERROR_STATUS_0_OFFS (0x20e4) +#define HWIO_TQM_R1_ERROR_STATUS_0_RMSK 0x7 +#define HWIO_TQM_R1_ERROR_STATUS_0_POR 0x00000000 +#define HWIO_TQM_R1_ERROR_STATUS_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_ERROR_STATUS_0_ATTR 0x0 +#define HWIO_TQM_R1_ERROR_STATUS_0_IN(x) \ + in_dword(HWIO_TQM_R1_ERROR_STATUS_0_ADDR(x)) +#define HWIO_TQM_R1_ERROR_STATUS_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_ERROR_STATUS_0_ADDR(x), m) +#define HWIO_TQM_R1_ERROR_STATUS_0_OUT(x, v) \ + out_dword(HWIO_TQM_R1_ERROR_STATUS_0_ADDR(x),v) +#define HWIO_TQM_R1_ERROR_STATUS_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_ERROR_STATUS_0_ADDR(x),m,v,HWIO_TQM_R1_ERROR_STATUS_0_IN(x)) +#define HWIO_TQM_R1_ERROR_STATUS_0_MSDU_ENT_SM_INTERRUPT_BMSK 0x4 +#define HWIO_TQM_R1_ERROR_STATUS_0_MSDU_ENT_SM_INTERRUPT_SHFT 2 +#define HWIO_TQM_R1_ERROR_STATUS_0_SW_CMD_SM_INTERRUPT_BMSK 0x2 +#define HWIO_TQM_R1_ERROR_STATUS_0_SW_CMD_SM_INTERRUPT_SHFT 1 +#define HWIO_TQM_R1_ERROR_STATUS_0_HWSCH_SM_INTERRUPT_BMSK 0x1 +#define HWIO_TQM_R1_ERROR_STATUS_0_HWSCH_SM_INTERRUPT_SHFT 0 + +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_ADDR(x) ((x) + 0x20e8) +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_PHYS(x) ((x) + 0x20e8) +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_OFFS (0x20e8) +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_RMSK 0xffffffff +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_POR 0x00000000 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_ATTR 0x1 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_IN(x) \ + in_dword(HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_ADDR(x)) +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_ADDR(x), m) +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_TLV_HDR_BMSK 0xffff0000 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_TLV_HDR_SHFT 16 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_3_BMSK 0xf000 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_3_SHFT 12 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_2_BMSK 0xf00 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_2_SHFT 8 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_1_BMSK 0xf0 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_1_SHFT 4 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_0_BMSK 0xf +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_0_SHFT 0 + +#define HWIO_TQM_R2_TCL2TQM_RING_HP_ADDR(x) ((x) + 0x3000) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_PHYS(x) ((x) + 0x3000) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_OFFS (0x3000) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TCL2TQM_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TCL2TQM_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TCL2TQM_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TCL2TQM_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TCL2TQM_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TCL2TQM_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TCL2TQM_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TCL2TQM_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TCL2TQM_RING_HP_IN(x)) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TCL2TQM_RING_TP_ADDR(x) ((x) + 0x3004) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_PHYS(x) ((x) + 0x3004) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_OFFS (0x3004) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TCL2TQM_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TCL2TQM_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TCL2TQM_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TCL2TQM_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TCL2TQM_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TCL2TQM_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TCL2TQM_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TCL2TQM_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TCL2TQM_RING_TP_IN(x)) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_FW2TQM_RING_HP_ADDR(x) ((x) + 0x3008) +#define HWIO_TQM_R2_FW2TQM_RING_HP_PHYS(x) ((x) + 0x3008) +#define HWIO_TQM_R2_FW2TQM_RING_HP_OFFS (0x3008) +#define HWIO_TQM_R2_FW2TQM_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_FW2TQM_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_FW2TQM_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_FW2TQM_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_FW2TQM_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_FW2TQM_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_FW2TQM_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_FW2TQM_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_FW2TQM_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_FW2TQM_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_FW2TQM_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_FW2TQM_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_FW2TQM_RING_HP_IN(x)) +#define HWIO_TQM_R2_FW2TQM_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_FW2TQM_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_FW2TQM_RING_TP_ADDR(x) ((x) + 0x300c) +#define HWIO_TQM_R2_FW2TQM_RING_TP_PHYS(x) ((x) + 0x300c) +#define HWIO_TQM_R2_FW2TQM_RING_TP_OFFS (0x300c) +#define HWIO_TQM_R2_FW2TQM_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_FW2TQM_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_FW2TQM_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_FW2TQM_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_FW2TQM_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_FW2TQM_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_FW2TQM_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_FW2TQM_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_FW2TQM_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_FW2TQM_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_FW2TQM_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_FW2TQM_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_FW2TQM_RING_TP_IN(x)) +#define HWIO_TQM_R2_FW2TQM_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_FW2TQM_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_SW_CMD_RING_HP_ADDR(x) ((x) + 0x3010) +#define HWIO_TQM_R2_SW_CMD_RING_HP_PHYS(x) ((x) + 0x3010) +#define HWIO_TQM_R2_SW_CMD_RING_HP_OFFS (0x3010) +#define HWIO_TQM_R2_SW_CMD_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_SW_CMD_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_SW_CMD_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_SW_CMD_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_SW_CMD_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_SW_CMD_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_SW_CMD_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_SW_CMD_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_SW_CMD_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_SW_CMD_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_SW_CMD_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_SW_CMD_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_SW_CMD_RING_HP_IN(x)) +#define HWIO_TQM_R2_SW_CMD_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_SW_CMD_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_SW_CMD_RING_TP_ADDR(x) ((x) + 0x3014) +#define HWIO_TQM_R2_SW_CMD_RING_TP_PHYS(x) ((x) + 0x3014) +#define HWIO_TQM_R2_SW_CMD_RING_TP_OFFS (0x3014) +#define HWIO_TQM_R2_SW_CMD_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_SW_CMD_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_SW_CMD_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_SW_CMD_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_SW_CMD_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_SW_CMD_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_SW_CMD_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_SW_CMD_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_SW_CMD_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_SW_CMD_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_SW_CMD_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_SW_CMD_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_SW_CMD_RING_TP_IN(x)) +#define HWIO_TQM_R2_SW_CMD_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_SW_CMD_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_SW_CMD1_RING_HP_ADDR(x) ((x) + 0x3018) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_PHYS(x) ((x) + 0x3018) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_OFFS (0x3018) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_SW_CMD1_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_SW_CMD1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_SW_CMD1_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_SW_CMD1_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_SW_CMD1_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_SW_CMD1_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_SW_CMD1_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_SW_CMD1_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_SW_CMD1_RING_HP_IN(x)) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_SW_CMD1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_SW_CMD1_RING_TP_ADDR(x) ((x) + 0x301c) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_PHYS(x) ((x) + 0x301c) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_OFFS (0x301c) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_SW_CMD1_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_SW_CMD1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_SW_CMD1_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_SW_CMD1_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_SW_CMD1_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_SW_CMD1_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_SW_CMD1_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_SW_CMD1_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_SW_CMD1_RING_TP_IN(x)) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_SW_CMD1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_ADDR(x) ((x) + 0x3020) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_PHYS(x) ((x) + 0x3020) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_OFFS (0x3020) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_IN(x)) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_ADDR(x) ((x) + 0x3024) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_PHYS(x) ((x) + 0x3024) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_OFFS (0x3024) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_IN(x)) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_ADDR(x) ((x) + 0x3028) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_PHYS(x) ((x) + 0x3028) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_OFFS (0x3028) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM_RELEASE_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM_RELEASE_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_ADDR(x) ((x) + 0x302c) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_PHYS(x) ((x) + 0x302c) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_OFFS (0x302c) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM_RELEASE_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM_RELEASE_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_ADDR(x) ((x) + 0x3030) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_PHYS(x) ((x) + 0x3030) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_OFFS (0x3030) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM_STATUS_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM_STATUS_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM_STATUS_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM_STATUS_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM_STATUS_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_ADDR(x) ((x) + 0x3034) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_PHYS(x) ((x) + 0x3034) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_OFFS (0x3034) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM_STATUS_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM_STATUS_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM_STATUS_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM_STATUS_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM_STATUS_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_ADDR(x) ((x) + 0x3038) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_PHYS(x) ((x) + 0x3038) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_OFFS (0x3038) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM_STATUS1_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM_STATUS1_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM_STATUS1_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM_STATUS1_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM_STATUS1_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_ADDR(x) ((x) + 0x303c) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_PHYS(x) ((x) + 0x303c) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_OFFS (0x303c) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM_STATUS1_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM_STATUS1_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM_STATUS1_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM_STATUS1_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM_STATUS1_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_ADDR(x) ((x) + 0x3040) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_PHYS(x) ((x) + 0x3040) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_OFFS (0x3040) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_ADDR(x) ((x) + 0x3044) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_PHYS(x) ((x) + 0x3044) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_OFFS (0x3044) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_ADDR(x) ((x) + 0x3048) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_PHYS(x) ((x) + 0x3048) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_OFFS (0x3048) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_ADDR(x) ((x) + 0x304c) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_PHYS(x) ((x) + 0x304c) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_OFFS (0x304c) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_ADDR(x) ((x) + 0x3050) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_PHYS(x) ((x) + 0x3050) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_OFFS (0x3050) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_ADDR(x) ((x) + 0x3054) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_PHYS(x) ((x) + 0x3054) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_OFFS (0x3054) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_ADDR(x) ((x) + 0x3058) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_PHYS(x) ((x) + 0x3058) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_OFFS (0x3058) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_ADDR(x) ((x) + 0x305c) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_PHYS(x) ((x) + 0x305c) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_OFFS (0x305c) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_TAIL_PTR_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: MAC_UMCMN_REG + *--------------------------------------------------------------------------*/ + +#define MAC_UMCMN_REG_REG_BASE (UMAC_BASE + 0x00040000) +#define MAC_UMCMN_REG_REG_BASE_SIZE 0x4000 +#define MAC_UMCMN_REG_REG_BASE_USED 0x200c +#define MAC_UMCMN_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00040000) +#define MAC_UMCMN_REG_REG_BASE_OFFS 0x00040000 + +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_ADDR(x) ((x) + 0x0) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_PHYS(x) ((x) + 0x0) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_OFFS (0x0) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_RMSK 0x6ffe22 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_POR 0x006ffe22 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_ATTR 0x3 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_ADDR(x)) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_ADDR(x), m) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_ADDR(x),v) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_ADDR(x),m,v,HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_IN(x)) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_MXI_BMSK 0x400000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_MXI_SHFT 22 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_UMAC_DBG_BMSK 0x200000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_UMAC_DBG_SHFT 21 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TRC_APB_BMSK 0x80000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TRC_APB_SHFT 19 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TRC_BMSK 0x40000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TRC_SHFT 18 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_WBM_APB_BMSK 0x20000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_WBM_APB_SHFT 17 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_WBM_BMSK 0x10000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_WBM_SHFT 16 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TQM_APB_BMSK 0x8000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TQM_APB_SHFT 15 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TQM_BMSK 0x4000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TQM_SHFT 14 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TCL_APB_BMSK 0x2000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TCL_APB_SHFT 13 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TCL_BMSK 0x1000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TCL_SHFT 12 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_REO_APB_BMSK 0x800 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_REO_APB_SHFT 11 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_REO_BMSK 0x400 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_REO_SHFT 10 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_NOC_DBG_BMSK 0x200 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_NOC_DBG_SHFT 9 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_CMEM_BMSK 0x20 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_CMEM_SHFT 5 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_NOC_BMSK 0x2 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_NOC_SHFT 1 + +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_ADDR(x) ((x) + 0x4) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_PHYS(x) ((x) + 0x4) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_OFFS (0x4) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_RMSK 0x6ffc22 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_POR 0x00000002 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_ATTR 0x3 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_ADDR(x)) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_ADDR(x), m) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_ADDR(x),v) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_ADDR(x),m,v,HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_IN(x)) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_MXI_BMSK 0x400000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_MXI_SHFT 22 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_UMAC_DBG_BMSK 0x200000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_UMAC_DBG_SHFT 21 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TRC_APB_BMSK 0x80000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TRC_APB_SHFT 19 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TRC_BMSK 0x40000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TRC_SHFT 18 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_WBM_APB_BMSK 0x20000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_WBM_APB_SHFT 17 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_WBM_BMSK 0x10000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_WBM_SHFT 16 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TQM_APB_BMSK 0x8000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TQM_APB_SHFT 15 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TQM_BMSK 0x4000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TQM_SHFT 14 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TCL_APB_BMSK 0x2000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TCL_APB_SHFT 13 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TCL_BMSK 0x1000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TCL_SHFT 12 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_REO_APB_BMSK 0x800 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_REO_APB_SHFT 11 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_REO_BMSK 0x400 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_REO_SHFT 10 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_CMEM_BMSK 0x20 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_CMEM_SHFT 5 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_NOC_BMSK 0x2 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_NOC_SHFT 1 + +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_ADDR(x) ((x) + 0x8) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_PHYS(x) ((x) + 0x8) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_OFFS (0x8) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_RMSK 0xdf3 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_POR 0x00000000 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_ATTR 0x3 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMRCM_SOFTRESET_ADDR(x)) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMRCM_SOFTRESET_ADDR(x), m) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMRCM_SOFTRESET_ADDR(x),v) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMRCM_SOFTRESET_ADDR(x),m,v,HWIO_UMCMN_R0_UMRCM_SOFTRESET_IN(x)) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_MXI_BMSK 0x800 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_MXI_SHFT 11 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_UMAC_DBG_BMSK 0x400 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_UMAC_DBG_SHFT 10 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_TRC_BMSK 0x100 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_TRC_SHFT 8 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_WBM_BMSK 0x80 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_WBM_SHFT 7 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_TQM_BMSK 0x40 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_TQM_SHFT 6 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_TCL_BMSK 0x20 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_TCL_SHFT 5 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_REO_BMSK 0x10 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_REO_SHFT 4 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_CMEM_BMSK 0x2 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_CMEM_SHFT 1 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_NOC_BMSK 0x1 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_NOC_SHFT 0 + +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_ADDR(x) ((x) + 0xc) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_PHYS(x) ((x) + 0xc) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_OFFS (0xc) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_RMSK 0x7e +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_POR 0x00000000 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_ATTR 0x3 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMRCM_CONFIGRESET_ADDR(x)) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMRCM_CONFIGRESET_ADDR(x), m) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMRCM_CONFIGRESET_ADDR(x),v) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMRCM_CONFIGRESET_ADDR(x),m,v,HWIO_UMCMN_R0_UMRCM_CONFIGRESET_IN(x)) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_MXI_BMSK 0x40 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_MXI_SHFT 6 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_TRC_BMSK 0x20 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_TRC_SHFT 5 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_WBM_BMSK 0x10 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_WBM_SHFT 4 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_TQM_BMSK 0x8 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_TQM_SHFT 3 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_TCL_BMSK 0x4 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_TCL_SHFT 2 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_REO_BMSK 0x2 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_REO_SHFT 1 + +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_ADDR(x) ((x) + 0x10) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_PHYS(x) ((x) + 0x10) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_OFFS (0x10) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_RMSK 0xcffc22 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_POR 0x00000000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_ATTR 0x3 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_ADDR(x)) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_ADDR(x), m) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_ADDR(x),v) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_ADDR(x),m,v,HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_IN(x)) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_MXI_BMSK 0x800000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_MXI_SHFT 23 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_UMAC_DBG_BMSK 0x400000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_UMAC_DBG_SHFT 22 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TRC_APB_BMSK 0x80000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TRC_APB_SHFT 19 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TRC_BMSK 0x40000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TRC_SHFT 18 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_WBM_APB_BMSK 0x20000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_WBM_APB_SHFT 17 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_WBM_BMSK 0x10000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_WBM_SHFT 16 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TQM_APB_BMSK 0x8000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TQM_APB_SHFT 15 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TQM_BMSK 0x4000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TQM_SHFT 14 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TCL_APB_BMSK 0x2000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TCL_APB_SHFT 13 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TCL_BMSK 0x1000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TCL_SHFT 12 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_REO_APB_BMSK 0x800 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_REO_APB_SHFT 11 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_REO_BMSK 0x400 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_REO_SHFT 10 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_CMEM_BMSK 0x20 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_CMEM_SHFT 5 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_NOC_BMSK 0x2 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_NOC_SHFT 1 + +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_ADDR(x) ((x) + 0x14) +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_PHYS(x) ((x) + 0x14) +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_OFFS (0x14) +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_POR 0x00000000 +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_ATTR 0x1 +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_RTL_VERSION_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_RTL_VERSION_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_VAL_BMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_VAL_SHFT 0 + +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_ADDR(x) ((x) + 0x18) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_PHYS(x) ((x) + 0x18) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_OFFS (0x18) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_RMSK 0x1f +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_POR 0x00000000 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_ATTR 0x3 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_IN(x) \ + in_dword(HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_ADDR(x)) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_ADDR(x), m) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_ADDR(x),v) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_ADDR(x),m,v,HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_IN(x)) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_PHY2_BMSK 0x10 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_PHY2_SHFT 4 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_PHY1_BMSK 0x8 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_PHY1_SHFT 3 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_WMAC3_BMSK 0x4 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_WMAC3_SHFT 2 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_WMAC2_BMSK 0x2 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_WMAC2_SHFT 1 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_WMAC1_BMSK 0x1 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_WMAC1_SHFT 0 + +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_ADDR(x) ((x) + 0x1c) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_PHYS(x) ((x) + 0x1c) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_OFFS (0x1c) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_POR 0x00000000 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_ATTR 0x3 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_IN(x) \ + in_dword(HWIO_UMCMN_R0_CLK_GATE_DISABLE_ADDR(x)) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CLK_GATE_DISABLE_ADDR(x), m) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CLK_GATE_DISABLE_ADDR(x),v) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CLK_GATE_DISABLE_ADDR(x),m,v,HWIO_UMCMN_R0_CLK_GATE_DISABLE_IN(x)) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_CLK_ENS_EXTEND_BMSK 0x80000000 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_CLK_ENS_EXTEND_SHFT 31 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_CLK_ENS_EXTEND_APB_BMSK 0x40000000 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_CLK_ENS_EXTEND_APB_SHFT 30 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_TBD_BMSK 0x3fffff80 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_TBD_SHFT 7 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_RRI_BMSK 0x40 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_RRI_SHFT 6 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_APB_VAL_BMSK 0x20 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_APB_VAL_SHFT 5 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_INTR_EXTEND_BMSK 0x10 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_INTR_EXTEND_SHFT 4 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_IND_INTR_BMSK 0x8 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_IND_INTR_SHFT 3 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_PCIE_LOW_POWER_REQ_BMSK 0x4 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_PCIE_LOW_POWER_REQ_SHFT 2 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_UMAC_IDLE_GENERATE_BMSK 0x2 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_UMAC_IDLE_GENERATE_SHFT 1 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_UMCMN_TOP_BMSK 0x1 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_UMCMN_TOP_SHFT 0 + +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_ADDR(x) ((x) + 0x20) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_PHYS(x) ((x) + 0x20) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_OFFS (0x20) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_RMSK 0xf +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_POR 0x00000001 +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_ATTR 0x3 +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_IN(x) \ + in_dword(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_ADDR(x)) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_ADDR(x), m) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_ADDR(x),v) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_ADDR(x),m,v,HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_IN(x)) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_VALUE_BMSK 0xf +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_ADDR(x) ((x) + 0x24) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_PHYS(x) ((x) + 0x24) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_OFFS (0x24) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_RMSK 0x1 +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_POR 0x00000001 +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_ATTR 0x3 +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_IN(x) \ + in_dword(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_ADDR(x)) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_ADDR(x), m) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_ADDR(x),v) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_ADDR(x),m,v,HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_IN(x)) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_VALUE_BMSK 0x1 +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_ADDR(x) ((x) + 0x28) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_PHYS(x) ((x) + 0x28) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_OFFS (0x28) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_RMSK 0xfffffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_POR 0x00000000 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_ATTR 0x3 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_IN(x) \ + in_dword(HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_ADDR(x)) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_ADDR(x), m) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_ADDR(x),v) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_ADDR(x),m,v,HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_IN(x)) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_SIZE_BMSK 0xfff0000 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_SIZE_SHFT 16 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_BASE_BMSK 0xffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_BASE_SHFT 0 + +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_ADDR(x) ((x) + 0x2c) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_PHYS(x) ((x) + 0x2c) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_OFFS (0x2c) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_RMSK 0xfffffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_POR 0x00000000 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_ATTR 0x3 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_IN(x) \ + in_dword(HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_ADDR(x)) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_ADDR(x), m) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_ADDR(x),v) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_ADDR(x),m,v,HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_IN(x)) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_SIZE_BMSK 0xfff0000 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_SIZE_SHFT 16 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_BASE_BMSK 0xffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_BASE_SHFT 0 + +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_ADDR(x) ((x) + 0x30) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_PHYS(x) ((x) + 0x30) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_OFFS (0x30) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_RMSK 0xfffffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_POR 0x00000000 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_ATTR 0x3 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_IN(x) \ + in_dword(HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_ADDR(x)) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_ADDR(x), m) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_ADDR(x),v) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_ADDR(x),m,v,HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_IN(x)) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_SIZE_BMSK 0xfff0000 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_SIZE_SHFT 16 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_BASE_BMSK 0xffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_BASE_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_P_ADDR(x) ((x) + 0x34) +#define HWIO_UMCMN_R0_ISR_P_PHYS(x) ((x) + 0x34) +#define HWIO_UMCMN_R0_ISR_P_OFFS (0x34) +#define HWIO_UMCMN_R0_ISR_P_RMSK 0x3fffd +#define HWIO_UMCMN_R0_ISR_P_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_P_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_P_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_P_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_P_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_P_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_P_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_P_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_P_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_P_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_P_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_P_IN(x)) +#define HWIO_UMCMN_R0_ISR_P_GXI_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_P_GXI_SHFT 17 +#define HWIO_UMCMN_R0_ISR_P_TQM2_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_P_TQM2_SHFT 16 +#define HWIO_UMCMN_R0_ISR_P_TQM1_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_P_TQM1_SHFT 15 +#define HWIO_UMCMN_R0_ISR_P_TQM0_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_P_TQM0_SHFT 14 +#define HWIO_UMCMN_R0_ISR_P_TCL1_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_P_TCL1_SHFT 13 +#define HWIO_UMCMN_R0_ISR_P_TCL0_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_P_TCL0_SHFT 12 +#define HWIO_UMCMN_R0_ISR_P_REO4_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_P_REO4_SHFT 11 +#define HWIO_UMCMN_R0_ISR_P_REO3_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_P_REO3_SHFT 10 +#define HWIO_UMCMN_R0_ISR_P_REO2_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_P_REO2_SHFT 9 +#define HWIO_UMCMN_R0_ISR_P_REO1_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_P_REO1_SHFT 8 +#define HWIO_UMCMN_R0_ISR_P_REO0_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_P_REO0_SHFT 7 +#define HWIO_UMCMN_R0_ISR_P_WBM3_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_P_WBM3_SHFT 6 +#define HWIO_UMCMN_R0_ISR_P_WBM2_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_P_WBM2_SHFT 5 +#define HWIO_UMCMN_R0_ISR_P_WBM1_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_P_WBM1_SHFT 4 +#define HWIO_UMCMN_R0_ISR_P_WBM0_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_P_WBM0_SHFT 3 +#define HWIO_UMCMN_R0_ISR_P_MEM_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_P_MEM_SHFT 2 +#define HWIO_UMCMN_R0_ISR_P_APB_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_P_APB_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S0_ADDR(x) ((x) + 0x38) +#define HWIO_UMCMN_R0_ISR_S0_PHYS(x) ((x) + 0x38) +#define HWIO_UMCMN_R0_ISR_S0_OFFS (0x38) +#define HWIO_UMCMN_R0_ISR_S0_RMSK 0x71fffff +#define HWIO_UMCMN_R0_ISR_S0_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S0_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S0_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S0_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S0_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S0_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S0_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S0_IN(x)) +#define HWIO_UMCMN_R0_ISR_S0_MXI_APB_RD_INVALID_BMSK 0x4000000 +#define HWIO_UMCMN_R0_ISR_S0_MXI_APB_RD_INVALID_SHFT 26 +#define HWIO_UMCMN_R0_ISR_S0_MXI_APB_WR_INVALID_BMSK 0x2000000 +#define HWIO_UMCMN_R0_ISR_S0_MXI_APB_WR_INVALID_SHFT 25 +#define HWIO_UMCMN_R0_ISR_S0_MXI_APB_WR_TO_RD_INVALID_BMSK 0x1000000 +#define HWIO_UMCMN_R0_ISR_S0_MXI_APB_WR_TO_RD_INVALID_SHFT 24 +#define HWIO_UMCMN_R0_ISR_S0_UMCMN_APB_RD_INVALID_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S0_UMCMN_APB_RD_INVALID_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S0_UMCMN_APB_WR_INVALID_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S0_UMCMN_APB_WR_INVALID_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S0_UMCMN_APB_WR_TO_RD_INVALID_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S0_UMCMN_APB_WR_TO_RD_INVALID_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S0_TQM_APB_RD_INVALID_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S0_TQM_APB_RD_INVALID_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S0_TQM_APB_WR_INVALID_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S0_TQM_APB_WR_INVALID_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S0_TQM_APB_WR_TO_RD_INVALID_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S0_TQM_APB_WR_TO_RD_INVALID_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S0_CMN_PRSR_APB_RD_INVALID_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S0_CMN_PRSR_APB_RD_INVALID_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S0_CMN_PRSR_APB_WR_INVALID_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S0_CMN_PRSR_APB_WR_INVALID_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S0_CMN_PRSR_APB_WR_TO_RD_INVALID_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S0_CMN_PRSR_APB_WR_TO_RD_INVALID_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S0_CCE_APB_RD_INVALID_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S0_CCE_APB_RD_INVALID_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S0_CCE_APB_WR_INVALID_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S0_CCE_APB_WR_INVALID_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S0_CCE_APB_WR_TO_RD_INVALID_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S0_CCE_APB_WR_TO_RD_INVALID_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S0_WBM_APB_RD_INVALID_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S0_WBM_APB_RD_INVALID_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S0_WBM_APB_WR_INVALID_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S0_WBM_APB_WR_INVALID_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S0_WBM_APB_WR_TO_RD_INVALID_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S0_WBM_APB_WR_TO_RD_INVALID_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S0_TCL_APB_RD_INVALID_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S0_TCL_APB_RD_INVALID_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S0_TCL_APB_WR_INVALID_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S0_TCL_APB_WR_INVALID_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S0_TCL_APB_WR_TO_RD_INVALID_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S0_TCL_APB_WR_TO_RD_INVALID_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S0_REO_APB_RD_INVALID_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S0_REO_APB_RD_INVALID_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S0_REO_APB_WR_INVALID_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S0_REO_APB_WR_INVALID_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S0_REO_APB_WR_TO_RD_INVALID_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S0_REO_APB_WR_TO_RD_INVALID_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S2_ADDR(x) ((x) + 0x3c) +#define HWIO_UMCMN_R0_ISR_S2_PHYS(x) ((x) + 0x3c) +#define HWIO_UMCMN_R0_ISR_S2_OFFS (0x3c) +#define HWIO_UMCMN_R0_ISR_S2_RMSK 0xf +#define HWIO_UMCMN_R0_ISR_S2_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S2_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S2_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S2_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S2_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S2_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S2_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S2_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S2_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S2_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S2_IN(x)) +#define HWIO_UMCMN_R0_ISR_S2_MEM_REMOTE_ACC_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S2_MEM_REMOTE_ACC_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S2_MEM_ACC_RANGE_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S2_MEM_ACC_RANGE_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S2_MEM_NON_SEC_ACC_ERR2_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S2_MEM_NON_SEC_ACC_ERR2_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S2_MEM_NON_SEC_ACC_ERR1_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S2_MEM_NON_SEC_ACC_ERR1_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S3_ADDR(x) ((x) + 0x40) +#define HWIO_UMCMN_R0_ISR_S3_PHYS(x) ((x) + 0x40) +#define HWIO_UMCMN_R0_ISR_S3_OFFS (0x40) +#define HWIO_UMCMN_R0_ISR_S3_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S3_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S3_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S3_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S3_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S3_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S3_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S3_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S3_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S3_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S3_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S3_IN(x)) +#define HWIO_UMCMN_R0_ISR_S3_MSDU_PARSER_DUP_DET_EVENT_INTR_BMSK 0x80000000 +#define HWIO_UMCMN_R0_ISR_S3_MSDU_PARSER_DUP_DET_EVENT_INTR_SHFT 31 +#define HWIO_UMCMN_R0_ISR_S3_REL_PARSER_DUP_DET_EVENT_INTR_BMSK 0x40000000 +#define HWIO_UMCMN_R0_ISR_S3_REL_PARSER_DUP_DET_EVENT_INTR_SHFT 30 +#define HWIO_UMCMN_R0_ISR_S3_LINK_DIST_DUP_DET_EVENT_INTR_BMSK 0x20000000 +#define HWIO_UMCMN_R0_ISR_S3_LINK_DIST_DUP_DET_EVENT_INTR_SHFT 29 +#define HWIO_UMCMN_R0_ISR_S3_SW_COOKIE_IDLE_TIMEOUT_BMSK 0x10000000 +#define HWIO_UMCMN_R0_ISR_S3_SW_COOKIE_IDLE_TIMEOUT_SHFT 28 +#define HWIO_UMCMN_R0_ISR_S3_DELINK_B2B_DUPLI_PTR_INTR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_ISR_S3_DELINK_B2B_DUPLI_PTR_INTR_SHFT 27 +#define HWIO_UMCMN_R0_ISR_S3_LINK_DIST_B2B_DUPLI_INTR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_ISR_S3_LINK_DIST_B2B_DUPLI_INTR_SHFT 26 +#define HWIO_UMCMN_R0_ISR_S3_IDLE_SEQUENCE_WD_INTR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_ISR_S3_IDLE_SEQUENCE_WD_INTR_SHFT 25 +#define HWIO_UMCMN_R0_ISR_S3_WBM_VA_CONV_ERR_INT_BMSK 0x1000000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_VA_CONV_ERR_INT_SHFT 24 +#define HWIO_UMCMN_R0_ISR_S3_WBM_BP_WARN_INT_BMSK 0x800000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_BP_WARN_INT_SHFT 23 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW6_BUF_PROD_WDG_BMSK 0x400000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW6_BUF_PROD_WDG_SHFT 22 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW5_BUF_PROD_WDG_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW5_BUF_PROD_WDG_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW4_BUF_PROD_WDG_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW4_BUF_PROD_WDG_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S3_WBM_ERROR_BUF_PROD_WDG_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_ERROR_BUF_PROD_WDG_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S3_WBM_MSDU_PARSER_ERR_BMSK 0x70000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_MSDU_PARSER_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S3_WBM_MSDU_DELINK_PARSE_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S3_WBM_MSDU_DELINK_PARSE_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S3_WBM_MSDU_DELINK_WDG_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S3_WBM_MSDU_DELINK_WDG_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LNK_IDLE_LIST_DIST_C_WDG_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LNK_IDLE_LIST_DIST_C_WDG_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LNK_IDLE_LIST_DIST_P_WDG_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LNK_IDLE_LIST_DIST_P_WDG_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S3_WBM_FW_BUF_PROD_WDG_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S3_WBM_FW_BUF_PROD_WDG_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW3_BUF_PROD_WDG_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW3_BUF_PROD_WDG_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW2_BUF_PROD_WDG_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW2_BUF_PROD_WDG_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW1_BUF_PROD_WDG_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW1_BUF_PROD_WDG_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW0_BUF_PROD_WDG_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW0_BUF_PROD_WDG_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LNK_IDLE_LIST_PROD_WDG_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LNK_IDLE_LIST_PROD_WDG_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S3_WBM_REL_REQ_PARSER_C_WDG_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S3_WBM_REL_REQ_PARSER_C_WDG_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S3_WBM_REL_REQ_PARSER_P_WDG_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S3_WBM_REL_REQ_PARSER_P_WDG_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S4_ADDR(x) ((x) + 0x44) +#define HWIO_UMCMN_R0_ISR_S4_PHYS(x) ((x) + 0x44) +#define HWIO_UMCMN_R0_ISR_S4_OFFS (0x44) +#define HWIO_UMCMN_R0_ISR_S4_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S4_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S4_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S4_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S4_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S4_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S4_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S4_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S4_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S4_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S4_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S4_IN(x)) +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW6_RELEASE_RING_WDG_ERR_BMSK 0x80000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW6_RELEASE_RING_WDG_ERR_SHFT 31 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW5_RELEASE_RING_WDG_ERR_BMSK 0x40000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW5_RELEASE_RING_WDG_ERR_SHFT 30 +#define HWIO_UMCMN_R0_ISR_S4_WBM2ERROR_RELEASE_RING_WDG_ERR_BMSK 0x20000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2ERROR_RELEASE_RING_WDG_ERR_SHFT 29 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW4_RELEASE_RING_WDG_ERR_BMSK 0x10000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW4_RELEASE_RING_WDG_ERR_SHFT 28 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW3_RELEASE_RING_WDG_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW3_RELEASE_RING_WDG_ERR_SHFT 27 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW2_RELEASE_RING_WDG_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW2_RELEASE_RING_WDG_ERR_SHFT 26 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW1_RELEASE_RING_WDG_ERR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW1_RELEASE_RING_WDG_ERR_SHFT 25 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW0_RELEASE_RING_WDG_ERR_BMSK 0x1000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW0_RELEASE_RING_WDG_ERR_SHFT 24 +#define HWIO_UMCMN_R0_ISR_S4_WBM2FW_RELEASE_RING_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2FW_RELEASE_RING_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_ISR_S4_WBM_IDLE_LINK_RING_WDG_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_ISR_S4_WBM_IDLE_LINK_RING_WDG_ERR_SHFT 22 +#define HWIO_UMCMN_R0_ISR_S4_WBM_IDLE_BUF_RING_WDG_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S4_WBM_IDLE_BUF_RING_WDG_ERR_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA2_LINK_RING_WDG_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA2_LINK_RING_WDG_ERR_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA1_LINK_RING_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA1_LINK_RING_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA0_LINK_RING_WDG_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA0_LINK_RING_WDG_ERR_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S4_WBM2FW_LINK_RING_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2FW_LINK_RING_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW_LINK_RING_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW_LINK_RING_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S4_WBM2REO_LINK_RING_WDG_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2REO_LINK_RING_WDG_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S4_WBM2TQM_LINK_RING_WDG_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2TQM_LINK_RING_WDG_ERR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA2_BUF_RING_WDG_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA2_BUF_RING_WDG_ERR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA1_BUF_RING_WDG_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA1_BUF_RING_WDG_ERR_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA0_BUF_RING_WDG_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA0_BUF_RING_WDG_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S4_WBM2FW_BUF_RING_WDG_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S4_WBM2FW_BUF_RING_WDG_ERR_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW_BUF_RING_WDG_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW_BUF_RING_WDG_ERR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S4_WBM2PPE_BUF_RING_WDG_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S4_WBM2PPE_BUF_RING_WDG_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S4_RXDMA2_RELEASE_RING_WDG_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S4_RXDMA2_RELEASE_RING_WDG_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S4_RXDMA1_RELEASE_RING_WDG_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S4_RXDMA1_RELEASE_RING_WDG_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S4_RXDMA0_RELEASE_RING_WDG_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S4_RXDMA0_RELEASE_RING_WDG_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S4_FW_RELEASE_RING_WDG_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S4_FW_RELEASE_RING_WDG_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S4_SW_RELEASE_RING_WDG_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S4_SW_RELEASE_RING_WDG_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S4_REO_RELEASE_RING_WDG_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S4_REO_RELEASE_RING_WDG_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S4_TQM_RELEASE_RING_WDG_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S4_TQM_RELEASE_RING_WDG_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S4_PPE_RELEASE_RING_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S4_PPE_RELEASE_RING_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S5_ADDR(x) ((x) + 0x48) +#define HWIO_UMCMN_R0_ISR_S5_PHYS(x) ((x) + 0x48) +#define HWIO_UMCMN_R0_ISR_S5_OFFS (0x48) +#define HWIO_UMCMN_R0_ISR_S5_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S5_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S5_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S5_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S5_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S5_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S5_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S5_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S5_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S5_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S5_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S5_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S5_IN(x)) +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW6_RELEASE_RING_REQ_ERR_BMSK 0x80000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW6_RELEASE_RING_REQ_ERR_SHFT 31 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW5_RELEASE_RING_REQ_ERR_BMSK 0x40000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW5_RELEASE_RING_REQ_ERR_SHFT 30 +#define HWIO_UMCMN_R0_ISR_S5_WBM2ERROR_RELEASE_RING_REQ_ERR_BMSK 0x20000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2ERROR_RELEASE_RING_REQ_ERR_SHFT 29 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW4_RELEASE_RING_REQ_ERR_BMSK 0x10000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW4_RELEASE_RING_REQ_ERR_SHFT 28 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW3_RELEASE_RING_REQ_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW3_RELEASE_RING_REQ_ERR_SHFT 27 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW2_RELEASE_RING_REQ_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW2_RELEASE_RING_REQ_ERR_SHFT 26 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW1_RELEASE_RING_REQ_ERR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW1_RELEASE_RING_REQ_ERR_SHFT 25 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW0_RELEASE_RING_REQ_ERR_BMSK 0x1000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW0_RELEASE_RING_REQ_ERR_SHFT 24 +#define HWIO_UMCMN_R0_ISR_S5_WBM2FW_RELEASE_RING_REQ_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2FW_RELEASE_RING_REQ_ERR_SHFT 23 +#define HWIO_UMCMN_R0_ISR_S5_WBM_IDLE_LINK_RING_REQ_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_ISR_S5_WBM_IDLE_LINK_RING_REQ_ERR_SHFT 22 +#define HWIO_UMCMN_R0_ISR_S5_WBM_IDLE_BUF_RING_REQ_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S5_WBM_IDLE_BUF_RING_REQ_ERR_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA2_LINK_RING_REQ_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA2_LINK_RING_REQ_ERR_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA1_LINK_RING_REQ_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA1_LINK_RING_REQ_ERR_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA0_LINK_RING_REQ_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA0_LINK_RING_REQ_ERR_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S5_WBM2FW_LINK_RING_REQ_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2FW_LINK_RING_REQ_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW_LINK_RING_REQ_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW_LINK_RING_REQ_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S5_WBM2REO_LINK_RING_REQ_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2REO_LINK_RING_REQ_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S5_WBM2TQM_LINK_RING_REQ_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2TQM_LINK_RING_REQ_ERR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA2_BUF_RING_REQ_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA2_BUF_RING_REQ_ERR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA1_BUF_RING_REQ_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA1_BUF_RING_REQ_ERR_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA0_BUF_RING_REQ_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA0_BUF_RING_REQ_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S5_WBM2FW_BUF_RING_REQ_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S5_WBM2FW_BUF_RING_REQ_ERR_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW_BUF_RING_REQ_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW_BUF_RING_REQ_ERR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S5_WBM2PPE_BUF_RING_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S5_WBM2PPE_BUF_RING_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S5_RXDMA2_RELEASE_RING_REQ_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S5_RXDMA2_RELEASE_RING_REQ_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S5_RXDMA1_RELEASE_RING_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S5_RXDMA1_RELEASE_RING_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S5_RXDMA0_RELEASE_RING_REQ_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S5_RXDMA0_RELEASE_RING_REQ_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S5_FW_RELEASE_RING_REQ_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S5_FW_RELEASE_RING_REQ_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S5_SW_RELEASE_RING_REQ_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S5_SW_RELEASE_RING_REQ_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S5_REO_RELEASE_RING_REQ_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S5_REO_RELEASE_RING_REQ_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S5_TQM_RELEASE_RING_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S5_TQM_RELEASE_RING_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S5_PPE_RELEASE_RING_REQ_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S5_PPE_RELEASE_RING_REQ_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S6_ADDR(x) ((x) + 0x4c) +#define HWIO_UMCMN_R0_ISR_S6_PHYS(x) ((x) + 0x4c) +#define HWIO_UMCMN_R0_ISR_S6_OFFS (0x4c) +#define HWIO_UMCMN_R0_ISR_S6_RMSK 0x3fffff +#define HWIO_UMCMN_R0_ISR_S6_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S6_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S6_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S6_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S6_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S6_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S6_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S6_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S6_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S6_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S6_IN(x)) +#define HWIO_UMCMN_R0_ISR_S6_REO2PPE_RING_WDG_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S6_REO2PPE_RING_WDG_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW8_RING_WDG_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW8_RING_WDG_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW7_RING_WDG_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW7_RING_WDG_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S6_REO_STATUS_RING_WDG_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S6_REO_STATUS_RING_WDG_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S6_REO_RELEASE_RING_WDG_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S6_REO_RELEASE_RING_WDG_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S6_REO2FW_RING_WDG_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S6_REO2FW_RING_WDG_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW0_RING_WDG_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW0_RING_WDG_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW6_RING_WDG_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW6_RING_WDG_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW5_RING_WDG_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW5_RING_WDG_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW4_RING_WDG_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW4_RING_WDG_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW3_RING_WDG_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW3_RING_WDG_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW2_RING_WDG_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW2_RING_WDG_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW1_RING_WDG_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW1_RING_WDG_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO_RING_WDG_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO_RING_WDG_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO1_RING_WDG_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO1_RING_WDG_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO2_RING_WDG_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO2_RING_WDG_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO3_RING_WDG_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO3_RING_WDG_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S6_REO_CMD_RING_WDG_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S6_REO_CMD_RING_WDG_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S6_WBM2REO_LINK_RING_WDG_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S6_WBM2REO_LINK_RING_WDG_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S6_RXDMA2REO2_MLO_RING_WDG_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S6_RXDMA2REO2_MLO_RING_WDG_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S6_RXDMA2REO1_MLO_RING_WDG_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S6_RXDMA2REO1_MLO_RING_WDG_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S6_RXDMA2REO0_RING_WDG_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S6_RXDMA2REO0_RING_WDG_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S7_ADDR(x) ((x) + 0x50) +#define HWIO_UMCMN_R0_ISR_S7_PHYS(x) ((x) + 0x50) +#define HWIO_UMCMN_R0_ISR_S7_OFFS (0x50) +#define HWIO_UMCMN_R0_ISR_S7_RMSK 0xffff000f +#define HWIO_UMCMN_R0_ISR_S7_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S7_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S7_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S7_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S7_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S7_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S7_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S7_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S7_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S7_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S7_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S7_IN(x)) +#define HWIO_UMCMN_R0_ISR_S7_REO_CACHE_INT_BMSK 0xffff0000 +#define HWIO_UMCMN_R0_ISR_S7_REO_CACHE_INT_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S7_REO_AC_BUF_OVER_THRESH_BMSK 0xf +#define HWIO_UMCMN_R0_ISR_S7_REO_AC_BUF_OVER_THRESH_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S8_ADDR(x) ((x) + 0x54) +#define HWIO_UMCMN_R0_ISR_S8_PHYS(x) ((x) + 0x54) +#define HWIO_UMCMN_R0_ISR_S8_OFFS (0x54) +#define HWIO_UMCMN_R0_ISR_S8_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S8_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S8_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S8_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S8_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S8_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S8_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S8_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S8_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S8_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S8_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S8_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S8_IN(x)) +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_RESERVED_BMSK 0xfff00000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_RESERVED_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_INVALID_TLV_CMD_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_INVALID_TLV_CMD_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_SW_ZERO_DESC_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_SW_ZERO_DESC_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_AGE_ZERO_DESC_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_AGE_ZERO_DESC_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BA_NON_AMPDU_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BA_NON_AMPDU_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_SEQ_PN_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_SEQ_PN_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BAR_SNEQUAL_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BAR_SNEQUAL_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BAR_NONBA_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BAR_NONBA_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_OOR_BAR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_OOR_BAR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_OOR_REG_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_OOR_REG_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_2K_BAR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_2K_BAR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_2K_REG_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_2K_REG_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BA_DD_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BA_DD_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_NONBA_DD_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_NONBA_DD_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_AMPDU_NONBA_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_AMPDU_NONBA_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_QD_NOTVALID_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_QD_NOTVALID_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_QD_ADDR_ZERO_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_QD_ADDR_ZERO_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S9_ADDR(x) ((x) + 0x58) +#define HWIO_UMCMN_R0_ISR_S9_PHYS(x) ((x) + 0x58) +#define HWIO_UMCMN_R0_ISR_S9_OFFS (0x58) +#define HWIO_UMCMN_R0_ISR_S9_RMSK 0xffffff +#define HWIO_UMCMN_R0_ISR_S9_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S9_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S9_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S9_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S9_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S9_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S9_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S9_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S9_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S9_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S9_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S9_IN(x)) +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_BMSK 0xf00000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_WARNING_INTR_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_WARNING_INTR_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST7_PROD_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST7_PROD_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST6_PROD_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST6_PROD_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST5_PROD_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST5_PROD_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST4_PROD_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST4_PROD_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_STATUS_PROD_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_STATUS_PROD_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_RELEASE_PROD_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_RELEASE_PROD_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_WIFI_PROD_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_WIFI_PROD_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_TCL_PROD_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_TCL_PROD_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST3_PROD_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST3_PROD_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST2_PROD_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST2_PROD_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST1_PROD_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST1_PROD_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST0_PROD_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST0_PROD_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_SEQUENCER_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_SEQUENCER_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REORDER_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REORDER_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_CMD_TLV_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_CMD_TLV_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S10_ADDR(x) ((x) + 0x5c) +#define HWIO_UMCMN_R0_ISR_S10_PHYS(x) ((x) + 0x5c) +#define HWIO_UMCMN_R0_ISR_S10_OFFS (0x5c) +#define HWIO_UMCMN_R0_ISR_S10_RMSK 0x3ffff +#define HWIO_UMCMN_R0_ISR_S10_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S10_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S10_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S10_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S10_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S10_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S10_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S10_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S10_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S10_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S10_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S10_IN(x)) +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG11_REQ_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG11_REQ_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG10_REQ_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG10_REQ_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG9_REQ_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG9_REQ_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG8_REQ_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG8_REQ_ERR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG7_REQ_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG7_REQ_ERR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG6_REQ_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG6_REQ_ERR_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG5_REQ_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG5_REQ_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG4_REQ_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG4_REQ_ERR_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG3_REQ_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG3_REQ_ERR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG2_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG2_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG1_REQ_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG1_REQ_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG0_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG0_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S11_ADDR(x) ((x) + 0x60) +#define HWIO_UMCMN_R0_ISR_S11_PHYS(x) ((x) + 0x60) +#define HWIO_UMCMN_R0_ISR_S11_OFFS (0x60) +#define HWIO_UMCMN_R0_ISR_S11_RMSK 0x3ffffff +#define HWIO_UMCMN_R0_ISR_S11_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S11_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S11_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S11_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S11_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S11_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S11_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S11_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S11_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S11_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S11_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S11_IN(x)) +#define HWIO_UMCMN_R0_ISR_S11_TCL_PPE2TCL1_RING_WDG_ERR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_PPE2TCL1_RING_WDG_ERR_SHFT 25 +#define HWIO_UMCMN_R0_ISR_S11_TCL_PPE2TCL1_RING_REQ_ERR_BMSK 0x1000000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_PPE2TCL1_RING_REQ_ERR_SHFT 24 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT2_RING_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT2_RING_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT2_RING_REQ_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT2_RING_REQ_ERR_SHFT 22 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL5_RING_WDG_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL5_RING_WDG_ERR_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL5_RING_REQ_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL5_RING_REQ_ERR_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL4_RING_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL4_RING_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL4_RING_REQ_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL4_RING_REQ_ERR_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS2_RING_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS2_RING_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS2_RING_REQ_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS2_RING_REQ_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS1_RING_WDG_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS1_RING_WDG_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS1_RING_REQ_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS1_RING_REQ_ERR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2FW_RING_WDG_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2FW_RING_WDG_ERR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2FW_RING_REQ_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2FW_RING_REQ_ERR_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2TQM_RING_WDG_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2TQM_RING_WDG_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2TQM_RING_REQ_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2TQM_RING_REQ_ERR_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT_RING_WDG_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT_RING_WDG_ERR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT_RING_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT_RING_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S11_TCL_FW2TCL1_RING_WDG_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S11_TCL_FW2TCL1_RING_WDG_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S11_TCL_FW2TCL1_RING_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S11_TCL_FW2TCL1_RING_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL3_RING_WDG_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL3_RING_WDG_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL3_RING_REQ_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL3_RING_REQ_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL2_RING_WDG_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL2_RING_WDG_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL2_RING_REQ_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL2_RING_REQ_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL1_RING_WDG_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL1_RING_WDG_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL1_RING_REQ_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL1_RING_REQ_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S12_ADDR(x) ((x) + 0x64) +#define HWIO_UMCMN_R0_ISR_S12_PHYS(x) ((x) + 0x64) +#define HWIO_UMCMN_R0_ISR_S12_OFFS (0x64) +#define HWIO_UMCMN_R0_ISR_S12_RMSK 0x3fffff +#define HWIO_UMCMN_R0_ISR_S12_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S12_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S12_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S12_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S12_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S12_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S12_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S12_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S12_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S12_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S12_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S12_IN(x)) +#define HWIO_UMCMN_R0_ISR_S12_TCL_PARSER_OUT_TLV_SEQ_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_PARSER_OUT_TLV_SEQ_ERR_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S12_TCL_PPE2TCL1_ZERO_LEN_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_PPE2TCL1_ZERO_LEN_ERR_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL_CREDIT2_ZERO_LEN_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL_CREDIT2_ZERO_LEN_ERR_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_LENGTH_ERROR_INT_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_LENGTH_ERROR_INT_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S12_TCL_BANK_ID_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_BANK_ID_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S12_TCL_WDG_WARNING_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_WDG_WARNING_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL5_ZERO_LEN_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL5_ZERO_LEN_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL4_ZERO_LEN_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL4_ZERO_LEN_ERR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CCE_ERR_CLASSIFY_DIS_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CCE_ERR_CLASSIFY_DIS_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CCE_WDG_TO_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CCE_WDG_TO_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_IPV6_JUMBOGRAM_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_IPV6_JUMBOGRAM_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_MSDU_LEN_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_MSDU_LEN_ERR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_ETH_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_ETH_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_WMAC_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_WMAC_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_WDG_TO_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_WDG_TO_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL_CREDIT_ZERO_LEN_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL_CREDIT_ZERO_LEN_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S12_TCL_FW2TCL1_ZERO_LEN_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S12_TCL_FW2TCL1_ZERO_LEN_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL3_ZERO_LEN_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL3_ZERO_LEN_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL2_ZERO_LEN_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL2_ZERO_LEN_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL1_ZERO_LEN_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL1_ZERO_LEN_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S12_TCL_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S12_TCL_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S13_ADDR(x) ((x) + 0x68) +#define HWIO_UMCMN_R0_ISR_S13_PHYS(x) ((x) + 0x68) +#define HWIO_UMCMN_R0_ISR_S13_OFFS (0x68) +#define HWIO_UMCMN_R0_ISR_S13_RMSK 0x3ffff +#define HWIO_UMCMN_R0_ISR_S13_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S13_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S13_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S13_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S13_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S13_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S13_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S13_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S13_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S13_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S13_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S13_IN(x)) +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_RELEASE_RING_REQ_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_RELEASE_RING_REQ_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_RELEASE_RING_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_RELEASE_RING_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS1_UPDATE_RING_REQ_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS1_UPDATE_RING_REQ_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS1_UPDATE_RING_WDG_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS1_UPDATE_RING_WDG_ERR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS_UPDATE_RING_REQ_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS_UPDATE_RING_REQ_ERR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS_UPDATE_RING_WDG_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS_UPDATE_RING_WDG_ERR_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_FETCH_RING_REQ_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_FETCH_RING_REQ_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_FETCH_RING_WDG_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_FETCH_RING_WDG_ERR_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV1_LINK_ID_MISMATCH_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV1_LINK_ID_MISMATCH_ERR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV1_FLUSH_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV1_FLUSH_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV0_LINK_ID_MISMATCH_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV0_LINK_ID_MISMATCH_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV0_FLUSH_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV0_FLUSH_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S13_TQM_SW_CMD_RING_REQ_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S13_TQM_SW_CMD_RING_REQ_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S13_TQM_SW_CMD_RING_WDG_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S13_TQM_SW_CMD_RING_WDG_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT3_RING_REQ_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT3_RING_REQ_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT3_RING_WDG_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT3_RING_WDG_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT1_RING_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT1_RING_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT1_RING_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT1_RING_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S14_ADDR(x) ((x) + 0x6c) +#define HWIO_UMCMN_R0_ISR_S14_PHYS(x) ((x) + 0x6c) +#define HWIO_UMCMN_R0_ISR_S14_OFFS (0x6c) +#define HWIO_UMCMN_R0_ISR_S14_RMSK 0x7ffffff +#define HWIO_UMCMN_R0_ISR_S14_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S14_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S14_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S14_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S14_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S14_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S14_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S14_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S14_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S14_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S14_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S14_IN(x)) +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT2_SRNG_P_FETCH_POLLING_TIMEOUT_INT_BMSK 0x4000000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT2_SRNG_P_FETCH_POLLING_TIMEOUT_INT_SHFT 26 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT2_SRNG_P_REQ_ERR_INT_BMSK 0x2000000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT2_SRNG_P_REQ_ERR_INT_SHFT 25 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT2_SRNG_P_WATCHDOG_ERR_INT_BMSK 0x1000000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT2_SRNG_P_WATCHDOG_ERR_INT_SHFT 24 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT1_SRNG_P_FETCH_POLLING_TIMEOUT_INT_BMSK 0x800000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT1_SRNG_P_FETCH_POLLING_TIMEOUT_INT_SHFT 23 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT1_SRNG_P_REQ_ERR_INT_BMSK 0x400000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT1_SRNG_P_REQ_ERR_INT_SHFT 22 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT1_SRNG_P_WATCHDOG_ERR_INT_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT1_SRNG_P_WATCHDOG_ERR_INT_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN2_SRNG_C_FETCH_POLLING_TIMEOUT_INT_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN2_SRNG_C_FETCH_POLLING_TIMEOUT_INT_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN2_SRNG_C_REQ_ERR_INT_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN2_SRNG_C_REQ_ERR_INT_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN2_SRNG_C_WATCHDOG_ERR_INT_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN2_SRNG_C_WATCHDOG_ERR_INT_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN1_SRNG_C_FETCH_POLLING_TIMEOUT_INT_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN1_SRNG_C_FETCH_POLLING_TIMEOUT_INT_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN1_SRNG_C_REQ_ERR_INT_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN1_SRNG_C_REQ_ERR_INT_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN1_SRNG_C_WATCHDOG_ERR_INT_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN1_SRNG_C_WATCHDOG_ERR_INT_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S14_TQM_CACHE_CTL_ERR_BMSK 0x7ff8 +#define HWIO_UMCMN_R0_ISR_S14_TQM_CACHE_CTL_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S14_TQM_WARNING_WDG_TIMEOUT_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S14_TQM_WARNING_WDG_TIMEOUT_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S14_TQM_HW_ERROR_INTR_TIMEOUT_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S14_TQM_HW_ERROR_INTR_TIMEOUT_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S14_TQM_SW_PRGM_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S14_TQM_SW_PRGM_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S15_ADDR(x) ((x) + 0x70) +#define HWIO_UMCMN_R0_ISR_S15_PHYS(x) ((x) + 0x70) +#define HWIO_UMCMN_R0_ISR_S15_OFFS (0x70) +#define HWIO_UMCMN_R0_ISR_S15_RMSK 0x7fff +#define HWIO_UMCMN_R0_ISR_S15_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S15_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S15_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S15_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S15_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S15_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S15_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S15_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S15_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S15_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S15_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S15_IN(x)) +#define HWIO_UMCMN_R0_ISR_S15_TQM_UNPAUSE_LINK_DESC_THRESHOLD_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S15_TQM_UNPAUSE_LINK_DESC_THRESHOLD_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S15_TQM_ILLEGAL_HWSCH_CMD_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S15_TQM_ILLEGAL_HWSCH_CMD_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S15_TQM_ILLEGAL_SW_CMD_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S15_TQM_ILLEGAL_SW_CMD_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT2_DEC_EMPTY_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT2_DEC_EMPTY_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT1_DEC_EMPTY_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT1_DEC_EMPTY_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT0_DEC_EMPTY_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT0_DEC_EMPTY_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT2_SATURATE_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT2_SATURATE_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT1_SATURATE_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT1_SATURATE_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT0_SATURATE_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT0_SATURATE_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_THRESHOLD2_REACHED_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_THRESHOLD2_REACHED_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_THRESHOLD1_REACHED_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_THRESHOLD1_REACHED_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_THRESHOLD0_REACHED_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_THRESHOLD0_REACHED_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S15_TQM_AGGR_LINK_DESC_THRESHOLD_REACHED_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S15_TQM_AGGR_LINK_DESC_THRESHOLD_REACHED_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S15_TQM_SW_CMD1_RING_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S15_TQM_SW_CMD1_RING_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S15_TQM_SW_CMD1_RING_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S15_TQM_SW_CMD1_RING_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S16_ADDR(x) ((x) + 0x74) +#define HWIO_UMCMN_R0_ISR_S16_PHYS(x) ((x) + 0x74) +#define HWIO_UMCMN_R0_ISR_S16_OFFS (0x74) +#define HWIO_UMCMN_R0_ISR_S16_RMSK 0x1ff +#define HWIO_UMCMN_R0_ISR_S16_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S16_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S16_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S16_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S16_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S16_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S16_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S16_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S16_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S16_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S16_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S16_IN(x)) +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_WDTO_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_WDTO_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_AXI_WR_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_AXI_WR_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_AXI_RD_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_AXI_RD_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_LAST_WR_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_LAST_WR_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_WDTO_WAR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_WDTO_WAR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S17_ADDR(x) ((x) + 0x78) +#define HWIO_UMCMN_R0_ISR_S17_PHYS(x) ((x) + 0x78) +#define HWIO_UMCMN_R0_ISR_S17_OFFS (0x78) +#define HWIO_UMCMN_R0_ISR_S17_RMSK 0xffff +#define HWIO_UMCMN_R0_ISR_S17_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S17_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S17_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S17_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S17_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S17_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S17_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S17_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S17_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S17_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S17_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S17_IN(x)) +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_MLO_P_WATCHDOG_ERR_INT_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_MLO_P_WATCHDOG_ERR_INT_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_MLO_P_WATCHDOG_ERR_INT_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_MLO_P_WATCHDOG_ERR_INT_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_RING_REQ_ERROR_INTR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_RING_REQ_ERROR_INTR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_RING_REQ_ERROR_INTR_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_RING_REQ_ERROR_INTR_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_RING_WATCHDOG_ERR_INTR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_RING_WATCHDOG_ERR_INTR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_RING_WATCHDOG_ERR_INTR_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_RING_WATCHDOG_ERR_INTR_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN2_RING_WATCHDOG_ERR_INTR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN2_RING_WATCHDOG_ERR_INTR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN1_RING_WATCHDOG_ERR_INTR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN1_RING_WATCHDOG_ERR_INTR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN2_RING_REQ_ERROR_INTR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN2_RING_REQ_ERROR_INTR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN1_RING_REQ_ERROR_INTR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN1_RING_REQ_ERROR_INTR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_FETCH_POINTER_ERR_INTR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_FETCH_POINTER_ERR_INTR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_FETCH_POINTER_ERR_INTR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_FETCH_POINTER_ERR_INTR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN2_FETCH_POINTER_ERR_INTR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN2_FETCH_POINTER_ERR_INTR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN1_FETCH_POINTER_ERR_INTR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN1_FETCH_POINTER_ERR_INTR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S17_SW1_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S17_SW1_RELEASE_RING_REQ_ERROR_INTR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S17_SW1_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S17_SW1_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_P_ADDR(x) ((x) + 0x7c) +#define HWIO_UMCMN_R0_IMR_P_PHYS(x) ((x) + 0x7c) +#define HWIO_UMCMN_R0_IMR_P_OFFS (0x7c) +#define HWIO_UMCMN_R0_IMR_P_RMSK 0x3fffd +#define HWIO_UMCMN_R0_IMR_P_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_P_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_P_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_P_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_P_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_P_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_P_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_P_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_P_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_P_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_P_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_P_IN(x)) +#define HWIO_UMCMN_R0_IMR_P_GXI_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_P_GXI_SHFT 17 +#define HWIO_UMCMN_R0_IMR_P_TQM2_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_P_TQM2_SHFT 16 +#define HWIO_UMCMN_R0_IMR_P_TQM1_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_P_TQM1_SHFT 15 +#define HWIO_UMCMN_R0_IMR_P_TQM0_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_P_TQM0_SHFT 14 +#define HWIO_UMCMN_R0_IMR_P_TCL1_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_P_TCL1_SHFT 13 +#define HWIO_UMCMN_R0_IMR_P_TCL0_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_P_TCL0_SHFT 12 +#define HWIO_UMCMN_R0_IMR_P_REO4_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_P_REO4_SHFT 11 +#define HWIO_UMCMN_R0_IMR_P_REO3_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_P_REO3_SHFT 10 +#define HWIO_UMCMN_R0_IMR_P_REO2_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_P_REO2_SHFT 9 +#define HWIO_UMCMN_R0_IMR_P_REO1_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_P_REO1_SHFT 8 +#define HWIO_UMCMN_R0_IMR_P_REO0_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_P_REO0_SHFT 7 +#define HWIO_UMCMN_R0_IMR_P_WBM3_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_P_WBM3_SHFT 6 +#define HWIO_UMCMN_R0_IMR_P_WBM2_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_P_WBM2_SHFT 5 +#define HWIO_UMCMN_R0_IMR_P_WBM1_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_P_WBM1_SHFT 4 +#define HWIO_UMCMN_R0_IMR_P_WBM0_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_P_WBM0_SHFT 3 +#define HWIO_UMCMN_R0_IMR_P_MEM_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_P_MEM_SHFT 2 +#define HWIO_UMCMN_R0_IMR_P_APB_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_P_APB_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S0_ADDR(x) ((x) + 0x80) +#define HWIO_UMCMN_R0_IMR_S0_PHYS(x) ((x) + 0x80) +#define HWIO_UMCMN_R0_IMR_S0_OFFS (0x80) +#define HWIO_UMCMN_R0_IMR_S0_RMSK 0x71fffff +#define HWIO_UMCMN_R0_IMR_S0_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S0_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S0_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S0_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S0_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S0_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S0_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S0_IN(x)) +#define HWIO_UMCMN_R0_IMR_S0_MXI_APB_RD_INVALID_BMSK 0x4000000 +#define HWIO_UMCMN_R0_IMR_S0_MXI_APB_RD_INVALID_SHFT 26 +#define HWIO_UMCMN_R0_IMR_S0_MXI_APB_WR_INVALID_BMSK 0x2000000 +#define HWIO_UMCMN_R0_IMR_S0_MXI_APB_WR_INVALID_SHFT 25 +#define HWIO_UMCMN_R0_IMR_S0_MXI_APB_WR_TO_RD_INVALID_BMSK 0x1000000 +#define HWIO_UMCMN_R0_IMR_S0_MXI_APB_WR_TO_RD_INVALID_SHFT 24 +#define HWIO_UMCMN_R0_IMR_S0_UMCMN_APB_RD_INVALID_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S0_UMCMN_APB_RD_INVALID_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S0_UMCMN_APB_WR_INVALID_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S0_UMCMN_APB_WR_INVALID_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S0_UMCMN_APB_WR_TO_RD_INVALID_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S0_UMCMN_APB_WR_TO_RD_INVALID_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S0_TQM_APB_RD_INVALID_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S0_TQM_APB_RD_INVALID_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S0_TQM_APB_WR_INVALID_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S0_TQM_APB_WR_INVALID_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S0_TQM_APB_WR_TO_RD_INVALID_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S0_TQM_APB_WR_TO_RD_INVALID_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S0_CMN_PRSR_APB_RD_INVALID_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S0_CMN_PRSR_APB_RD_INVALID_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S0_CMN_PRSR_APB_WR_INVALID_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S0_CMN_PRSR_APB_WR_INVALID_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S0_CMN_PRSR_APB_WR_TO_RD_INVALID_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S0_CMN_PRSR_APB_WR_TO_RD_INVALID_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S0_CCE_APB_RD_INVALID_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S0_CCE_APB_RD_INVALID_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S0_CCE_APB_WR_INVALID_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S0_CCE_APB_WR_INVALID_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S0_CCE_APB_WR_TO_RD_INVALID_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S0_CCE_APB_WR_TO_RD_INVALID_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S0_WBM_APB_RD_INVALID_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S0_WBM_APB_RD_INVALID_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S0_WBM_APB_WR_INVALID_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S0_WBM_APB_WR_INVALID_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S0_WBM_APB_WR_TO_RD_INVALID_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S0_WBM_APB_WR_TO_RD_INVALID_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S0_TCL_APB_RD_INVALID_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S0_TCL_APB_RD_INVALID_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S0_TCL_APB_WR_INVALID_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S0_TCL_APB_WR_INVALID_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S0_TCL_APB_WR_TO_RD_INVALID_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S0_TCL_APB_WR_TO_RD_INVALID_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S0_REO_APB_RD_INVALID_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S0_REO_APB_RD_INVALID_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S0_REO_APB_WR_INVALID_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S0_REO_APB_WR_INVALID_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S0_REO_APB_WR_TO_RD_INVALID_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S0_REO_APB_WR_TO_RD_INVALID_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S2_ADDR(x) ((x) + 0x84) +#define HWIO_UMCMN_R0_IMR_S2_PHYS(x) ((x) + 0x84) +#define HWIO_UMCMN_R0_IMR_S2_OFFS (0x84) +#define HWIO_UMCMN_R0_IMR_S2_RMSK 0xf +#define HWIO_UMCMN_R0_IMR_S2_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S2_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S2_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S2_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S2_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S2_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S2_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S2_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S2_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S2_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S2_IN(x)) +#define HWIO_UMCMN_R0_IMR_S2_MEM_REMOTE_ACC_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S2_MEM_REMOTE_ACC_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S2_MEM_ACC_RANGE_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S2_MEM_ACC_RANGE_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S2_MEM_NON_SEC_ACC_ERR2_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S2_MEM_NON_SEC_ACC_ERR2_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S2_MEM_NON_SEC_ACC_ERR1_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S2_MEM_NON_SEC_ACC_ERR1_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S3_ADDR(x) ((x) + 0x88) +#define HWIO_UMCMN_R0_IMR_S3_PHYS(x) ((x) + 0x88) +#define HWIO_UMCMN_R0_IMR_S3_OFFS (0x88) +#define HWIO_UMCMN_R0_IMR_S3_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S3_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S3_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S3_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S3_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S3_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S3_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S3_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S3_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S3_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S3_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S3_IN(x)) +#define HWIO_UMCMN_R0_IMR_S3_MSDU_PARSER_DUP_DET_EVENT_INTR_BMSK 0x80000000 +#define HWIO_UMCMN_R0_IMR_S3_MSDU_PARSER_DUP_DET_EVENT_INTR_SHFT 31 +#define HWIO_UMCMN_R0_IMR_S3_REL_PARSER_DUP_DET_EVENT_INTR_BMSK 0x40000000 +#define HWIO_UMCMN_R0_IMR_S3_REL_PARSER_DUP_DET_EVENT_INTR_SHFT 30 +#define HWIO_UMCMN_R0_IMR_S3_LINK_DIST_DUP_DET_EVENT_INTR_BMSK 0x20000000 +#define HWIO_UMCMN_R0_IMR_S3_LINK_DIST_DUP_DET_EVENT_INTR_SHFT 29 +#define HWIO_UMCMN_R0_IMR_S3_SW_COOKIE_IDLE_TIMEOUT_BMSK 0x10000000 +#define HWIO_UMCMN_R0_IMR_S3_SW_COOKIE_IDLE_TIMEOUT_SHFT 28 +#define HWIO_UMCMN_R0_IMR_S3_DELINK_B2B_DUPLI_PTR_INTR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_IMR_S3_DELINK_B2B_DUPLI_PTR_INTR_SHFT 27 +#define HWIO_UMCMN_R0_IMR_S3_LINK_DIST_B2B_DUPLI_INTR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_IMR_S3_LINK_DIST_B2B_DUPLI_INTR_SHFT 26 +#define HWIO_UMCMN_R0_IMR_S3_IDLE_SEQUENCE_WD_INTR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_IMR_S3_IDLE_SEQUENCE_WD_INTR_SHFT 25 +#define HWIO_UMCMN_R0_IMR_S3_WBM_VA_CONV_ERR_INT_BMSK 0x1000000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_VA_CONV_ERR_INT_SHFT 24 +#define HWIO_UMCMN_R0_IMR_S3_WBM_BP_WARN_INT_BMSK 0x800000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_BP_WARN_INT_SHFT 23 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW6_BUF_PROD_WDG_BMSK 0x400000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW6_BUF_PROD_WDG_SHFT 22 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW5_BUF_PROD_WDG_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW5_BUF_PROD_WDG_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW4_BUF_PROD_WDG_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW4_BUF_PROD_WDG_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S3_WBM_ERROR_BUF_PROD_WDG_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_ERROR_BUF_PROD_WDG_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S3_WBM_MSDU_PARSER_ERR_BMSK 0x70000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_MSDU_PARSER_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S3_WBM_MSDU_DELINK_PARSE_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S3_WBM_MSDU_DELINK_PARSE_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S3_WBM_MSDU_DELINK_WDG_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S3_WBM_MSDU_DELINK_WDG_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LNK_IDLE_LIST_DIST_C_WDG_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LNK_IDLE_LIST_DIST_C_WDG_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LNK_IDLE_LIST_DIST_P_WDG_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LNK_IDLE_LIST_DIST_P_WDG_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S3_WBM_FW_BUF_PROD_WDG_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S3_WBM_FW_BUF_PROD_WDG_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW3_BUF_PROD_WDG_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW3_BUF_PROD_WDG_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW2_BUF_PROD_WDG_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW2_BUF_PROD_WDG_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW1_BUF_PROD_WDG_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW1_BUF_PROD_WDG_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW0_BUF_PROD_WDG_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW0_BUF_PROD_WDG_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LNK_IDLE_LIST_PROD_WDG_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LNK_IDLE_LIST_PROD_WDG_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S3_WBM_REL_REQ_PARSER_C_WDG_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S3_WBM_REL_REQ_PARSER_C_WDG_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S3_WBM_REL_REQ_PARSER_P_WDG_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S3_WBM_REL_REQ_PARSER_P_WDG_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S4_ADDR(x) ((x) + 0x8c) +#define HWIO_UMCMN_R0_IMR_S4_PHYS(x) ((x) + 0x8c) +#define HWIO_UMCMN_R0_IMR_S4_OFFS (0x8c) +#define HWIO_UMCMN_R0_IMR_S4_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S4_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S4_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S4_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S4_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S4_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S4_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S4_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S4_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S4_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S4_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S4_IN(x)) +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW6_RELEASE_RING_WDG_ERR_BMSK 0x80000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW6_RELEASE_RING_WDG_ERR_SHFT 31 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW5_RELEASE_RING_WDG_ERR_BMSK 0x40000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW5_RELEASE_RING_WDG_ERR_SHFT 30 +#define HWIO_UMCMN_R0_IMR_S4_WBM2ERROR_RELEASE_RING_WDG_ERR_BMSK 0x20000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2ERROR_RELEASE_RING_WDG_ERR_SHFT 29 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW4_RELEASE_RING_WDG_ERR_BMSK 0x10000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW4_RELEASE_RING_WDG_ERR_SHFT 28 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW3_RELEASE_RING_WDG_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW3_RELEASE_RING_WDG_ERR_SHFT 27 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW2_RELEASE_RING_WDG_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW2_RELEASE_RING_WDG_ERR_SHFT 26 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW1_RELEASE_RING_WDG_ERR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW1_RELEASE_RING_WDG_ERR_SHFT 25 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW0_RELEASE_RING_WDG_ERR_BMSK 0x1000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW0_RELEASE_RING_WDG_ERR_SHFT 24 +#define HWIO_UMCMN_R0_IMR_S4_WBM2FW_RELEASE_RING_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2FW_RELEASE_RING_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_IMR_S4_WBM_IDLE_LINK_RING_WDG_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_IMR_S4_WBM_IDLE_LINK_RING_WDG_ERR_SHFT 22 +#define HWIO_UMCMN_R0_IMR_S4_WBM_IDLE_BUF_RING_WDG_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S4_WBM_IDLE_BUF_RING_WDG_ERR_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA2_LINK_RING_WDG_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA2_LINK_RING_WDG_ERR_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA1_LINK_RING_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA1_LINK_RING_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA0_LINK_RING_WDG_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA0_LINK_RING_WDG_ERR_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S4_WBM2FW_LINK_RING_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2FW_LINK_RING_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW_LINK_RING_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW_LINK_RING_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S4_WBM2REO_LINK_RING_WDG_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2REO_LINK_RING_WDG_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S4_WBM2TQM_LINK_RING_WDG_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2TQM_LINK_RING_WDG_ERR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA2_BUF_RING_WDG_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA2_BUF_RING_WDG_ERR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA1_BUF_RING_WDG_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA1_BUF_RING_WDG_ERR_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA0_BUF_RING_WDG_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA0_BUF_RING_WDG_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S4_WBM2FW_BUF_RING_WDG_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S4_WBM2FW_BUF_RING_WDG_ERR_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW_BUF_RING_WDG_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW_BUF_RING_WDG_ERR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S4_WBM2PPE_BUF_RING_WDG_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S4_WBM2PPE_BUF_RING_WDG_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S4_RXDMA2_RELEASE_RING_WDG_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S4_RXDMA2_RELEASE_RING_WDG_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S4_RXDMA1_RELEASE_RING_WDG_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S4_RXDMA1_RELEASE_RING_WDG_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S4_RXDMA0_RELEASE_RING_WDG_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S4_RXDMA0_RELEASE_RING_WDG_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S4_FW_RELEASE_RING_WDG_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S4_FW_RELEASE_RING_WDG_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S4_SW_RELEASE_RING_WDG_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S4_SW_RELEASE_RING_WDG_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S4_REO_RELEASE_RING_WDG_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S4_REO_RELEASE_RING_WDG_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S4_TQM_RELEASE_RING_WDG_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S4_TQM_RELEASE_RING_WDG_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S4_PPE_RELEASE_RING_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S4_PPE_RELEASE_RING_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S5_ADDR(x) ((x) + 0x90) +#define HWIO_UMCMN_R0_IMR_S5_PHYS(x) ((x) + 0x90) +#define HWIO_UMCMN_R0_IMR_S5_OFFS (0x90) +#define HWIO_UMCMN_R0_IMR_S5_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S5_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S5_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S5_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S5_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S5_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S5_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S5_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S5_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S5_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S5_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S5_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S5_IN(x)) +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW6_RELEASE_RING_REQ_ERR_BMSK 0x80000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW6_RELEASE_RING_REQ_ERR_SHFT 31 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW5_RELEASE_RING_REQ_ERR_BMSK 0x40000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW5_RELEASE_RING_REQ_ERR_SHFT 30 +#define HWIO_UMCMN_R0_IMR_S5_WBM2ERROR_RELEASE_RING_REQ_ERR_BMSK 0x20000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2ERROR_RELEASE_RING_REQ_ERR_SHFT 29 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW4_RELEASE_RING_REQ_ERR_BMSK 0x10000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW4_RELEASE_RING_REQ_ERR_SHFT 28 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW3_RELEASE_RING_REQ_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW3_RELEASE_RING_REQ_ERR_SHFT 27 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW2_RELEASE_RING_REQ_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW2_RELEASE_RING_REQ_ERR_SHFT 26 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW1_RELEASE_RING_REQ_ERR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW1_RELEASE_RING_REQ_ERR_SHFT 25 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW0_RELEASE_RING_REQ_ERR_BMSK 0x1000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW0_RELEASE_RING_REQ_ERR_SHFT 24 +#define HWIO_UMCMN_R0_IMR_S5_WBM2FW_RELEASE_RING_REQ_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2FW_RELEASE_RING_REQ_ERR_SHFT 23 +#define HWIO_UMCMN_R0_IMR_S5_WBM_IDLE_LINK_RING_REQ_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_IMR_S5_WBM_IDLE_LINK_RING_REQ_ERR_SHFT 22 +#define HWIO_UMCMN_R0_IMR_S5_WBM_IDLE_BUF_RING_REQ_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S5_WBM_IDLE_BUF_RING_REQ_ERR_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA2_LINK_RING_REQ_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA2_LINK_RING_REQ_ERR_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA1_LINK_RING_REQ_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA1_LINK_RING_REQ_ERR_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA0_LINK_RING_REQ_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA0_LINK_RING_REQ_ERR_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S5_WBM2FW_LINK_RING_REQ_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2FW_LINK_RING_REQ_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW_LINK_RING_REQ_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW_LINK_RING_REQ_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S5_WBM2REO_LINK_RING_REQ_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2REO_LINK_RING_REQ_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S5_WBM2TQM_LINK_RING_REQ_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2TQM_LINK_RING_REQ_ERR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA2_BUF_RING_REQ_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA2_BUF_RING_REQ_ERR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA1_BUF_RING_REQ_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA1_BUF_RING_REQ_ERR_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA0_BUF_RING_REQ_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA0_BUF_RING_REQ_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S5_WBM2FW_BUF_RING_REQ_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S5_WBM2FW_BUF_RING_REQ_ERR_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW_BUF_RING_REQ_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW_BUF_RING_REQ_ERR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S5_WBM2PPE_BUF_RING_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S5_WBM2PPE_BUF_RING_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S5_RXDMA2_RELEASE_RING_REQ_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S5_RXDMA2_RELEASE_RING_REQ_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S5_RXDMA1_RELEASE_RING_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S5_RXDMA1_RELEASE_RING_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S5_RXDMA0_RELEASE_RING_REQ_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S5_RXDMA0_RELEASE_RING_REQ_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S5_FW_RELEASE_RING_REQ_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S5_FW_RELEASE_RING_REQ_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S5_SW_RELEASE_RING_REQ_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S5_SW_RELEASE_RING_REQ_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S5_REO_RELEASE_RING_REQ_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S5_REO_RELEASE_RING_REQ_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S5_TQM_RELEASE_RING_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S5_TQM_RELEASE_RING_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S5_PPE_RELEASE_RING_REQ_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S5_PPE_RELEASE_RING_REQ_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S6_ADDR(x) ((x) + 0x94) +#define HWIO_UMCMN_R0_IMR_S6_PHYS(x) ((x) + 0x94) +#define HWIO_UMCMN_R0_IMR_S6_OFFS (0x94) +#define HWIO_UMCMN_R0_IMR_S6_RMSK 0x3fffff +#define HWIO_UMCMN_R0_IMR_S6_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S6_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S6_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S6_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S6_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S6_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S6_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S6_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S6_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S6_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S6_IN(x)) +#define HWIO_UMCMN_R0_IMR_S6_REO2PPE_RING_WDG_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S6_REO2PPE_RING_WDG_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW8_RING_WDG_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW8_RING_WDG_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW7_RING_WDG_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW7_RING_WDG_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S6_REO_STATUS_RING_WDG_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S6_REO_STATUS_RING_WDG_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S6_REO_RELEASE_RING_WDG_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S6_REO_RELEASE_RING_WDG_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S6_REO2FW_RING_WDG_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S6_REO2FW_RING_WDG_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW0_RING_WDG_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW0_RING_WDG_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW6_RING_WDG_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW6_RING_WDG_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW5_RING_WDG_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW5_RING_WDG_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW4_RING_WDG_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW4_RING_WDG_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW3_RING_WDG_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW3_RING_WDG_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW2_RING_WDG_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW2_RING_WDG_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW1_RING_WDG_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW1_RING_WDG_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO_RING_WDG_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO_RING_WDG_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO1_RING_WDG_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO1_RING_WDG_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO2_RING_WDG_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO2_RING_WDG_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO3_RING_WDG_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO3_RING_WDG_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S6_REO_CMD_RING_WDG_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S6_REO_CMD_RING_WDG_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S6_WBM2REO_LINK_RING_WDG_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S6_WBM2REO_LINK_RING_WDG_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S6_RXDMA2REO2_MLO_RING_WDG_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S6_RXDMA2REO2_MLO_RING_WDG_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S6_RXDMA2REO1_MLO_RING_WDG_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S6_RXDMA2REO1_MLO_RING_WDG_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S6_RXDMA2REO0_RING_WDG_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S6_RXDMA2REO0_RING_WDG_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S7_ADDR(x) ((x) + 0x98) +#define HWIO_UMCMN_R0_IMR_S7_PHYS(x) ((x) + 0x98) +#define HWIO_UMCMN_R0_IMR_S7_OFFS (0x98) +#define HWIO_UMCMN_R0_IMR_S7_RMSK 0xffff000f +#define HWIO_UMCMN_R0_IMR_S7_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S7_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S7_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S7_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S7_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S7_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S7_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S7_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S7_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S7_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S7_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S7_IN(x)) +#define HWIO_UMCMN_R0_IMR_S7_REO_CACHE_INT_BMSK 0xffff0000 +#define HWIO_UMCMN_R0_IMR_S7_REO_CACHE_INT_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S7_REO_AC_BUF_OVER_THRESH_BMSK 0xf +#define HWIO_UMCMN_R0_IMR_S7_REO_AC_BUF_OVER_THRESH_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S8_ADDR(x) ((x) + 0x9c) +#define HWIO_UMCMN_R0_IMR_S8_PHYS(x) ((x) + 0x9c) +#define HWIO_UMCMN_R0_IMR_S8_OFFS (0x9c) +#define HWIO_UMCMN_R0_IMR_S8_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S8_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S8_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S8_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S8_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S8_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S8_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S8_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S8_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S8_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S8_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S8_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S8_IN(x)) +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_RESERVED_BMSK 0xfff00000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_RESERVED_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_INVALID_TLV_CMD_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_INVALID_TLV_CMD_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_SW_ZERO_DESC_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_SW_ZERO_DESC_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_AGE_ZERO_DESC_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_AGE_ZERO_DESC_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BA_NON_AMPDU_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BA_NON_AMPDU_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_SEQ_PN_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_SEQ_PN_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BAR_SNEQUAL_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BAR_SNEQUAL_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BAR_NONBA_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BAR_NONBA_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_OOR_BAR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_OOR_BAR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_OOR_REG_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_OOR_REG_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_2K_BAR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_2K_BAR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_2K_REG_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_2K_REG_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BA_DD_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BA_DD_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_NONBA_DD_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_NONBA_DD_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_AMPDU_NONBA_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_AMPDU_NONBA_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_QD_NOTVALID_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_QD_NOTVALID_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_QD_ADDR_ZERO_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_QD_ADDR_ZERO_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S9_ADDR(x) ((x) + 0xa0) +#define HWIO_UMCMN_R0_IMR_S9_PHYS(x) ((x) + 0xa0) +#define HWIO_UMCMN_R0_IMR_S9_OFFS (0xa0) +#define HWIO_UMCMN_R0_IMR_S9_RMSK 0xffffff +#define HWIO_UMCMN_R0_IMR_S9_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S9_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S9_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S9_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S9_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S9_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S9_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S9_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S9_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S9_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S9_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S9_IN(x)) +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_BMSK 0xf00000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_WARNING_INTR_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_WARNING_INTR_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST7_PROD_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST7_PROD_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST6_PROD_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST6_PROD_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST5_PROD_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST5_PROD_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST4_PROD_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST4_PROD_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_STATUS_PROD_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_STATUS_PROD_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_RELEASE_PROD_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_RELEASE_PROD_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_WIFI_PROD_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_WIFI_PROD_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_TCL_PROD_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_TCL_PROD_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST3_PROD_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST3_PROD_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST2_PROD_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST2_PROD_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST1_PROD_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST1_PROD_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST0_PROD_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST0_PROD_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_SEQUENCER_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_SEQUENCER_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REORDER_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REORDER_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_CMD_TLV_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_CMD_TLV_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S10_ADDR(x) ((x) + 0xa4) +#define HWIO_UMCMN_R0_IMR_S10_PHYS(x) ((x) + 0xa4) +#define HWIO_UMCMN_R0_IMR_S10_OFFS (0xa4) +#define HWIO_UMCMN_R0_IMR_S10_RMSK 0x3ffff +#define HWIO_UMCMN_R0_IMR_S10_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S10_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S10_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S10_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S10_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S10_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S10_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S10_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S10_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S10_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S10_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S10_IN(x)) +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG11_REQ_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG11_REQ_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG10_REQ_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG10_REQ_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG9_REQ_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG9_REQ_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG8_REQ_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG8_REQ_ERR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG7_REQ_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG7_REQ_ERR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG6_REQ_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG6_REQ_ERR_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG5_REQ_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG5_REQ_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG4_REQ_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG4_REQ_ERR_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG3_REQ_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG3_REQ_ERR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG2_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG2_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG1_REQ_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG1_REQ_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG0_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG0_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S11_ADDR(x) ((x) + 0xa8) +#define HWIO_UMCMN_R0_IMR_S11_PHYS(x) ((x) + 0xa8) +#define HWIO_UMCMN_R0_IMR_S11_OFFS (0xa8) +#define HWIO_UMCMN_R0_IMR_S11_RMSK 0x3ffffff +#define HWIO_UMCMN_R0_IMR_S11_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S11_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S11_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S11_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S11_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S11_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S11_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S11_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S11_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S11_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S11_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S11_IN(x)) +#define HWIO_UMCMN_R0_IMR_S11_TCL_PPE2TCL1_RING_WDG_ERR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_PPE2TCL1_RING_WDG_ERR_SHFT 25 +#define HWIO_UMCMN_R0_IMR_S11_TCL_PPE2TCL1_RING_REQ_ERR_BMSK 0x1000000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_PPE2TCL1_RING_REQ_ERR_SHFT 24 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT2_RING_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT2_RING_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT2_RING_REQ_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT2_RING_REQ_ERR_SHFT 22 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL5_RING_WDG_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL5_RING_WDG_ERR_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL5_RING_REQ_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL5_RING_REQ_ERR_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL4_RING_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL4_RING_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL4_RING_REQ_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL4_RING_REQ_ERR_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS2_RING_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS2_RING_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS2_RING_REQ_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS2_RING_REQ_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS1_RING_WDG_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS1_RING_WDG_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS1_RING_REQ_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS1_RING_REQ_ERR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2FW_RING_WDG_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2FW_RING_WDG_ERR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2FW_RING_REQ_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2FW_RING_REQ_ERR_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2TQM_RING_WDG_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2TQM_RING_WDG_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2TQM_RING_REQ_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2TQM_RING_REQ_ERR_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT_RING_WDG_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT_RING_WDG_ERR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT_RING_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT_RING_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S11_TCL_FW2TCL1_RING_WDG_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S11_TCL_FW2TCL1_RING_WDG_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S11_TCL_FW2TCL1_RING_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S11_TCL_FW2TCL1_RING_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL3_RING_WDG_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL3_RING_WDG_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL3_RING_REQ_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL3_RING_REQ_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL2_RING_WDG_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL2_RING_WDG_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL2_RING_REQ_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL2_RING_REQ_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL1_RING_WDG_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL1_RING_WDG_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL1_RING_REQ_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL1_RING_REQ_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S12_ADDR(x) ((x) + 0xac) +#define HWIO_UMCMN_R0_IMR_S12_PHYS(x) ((x) + 0xac) +#define HWIO_UMCMN_R0_IMR_S12_OFFS (0xac) +#define HWIO_UMCMN_R0_IMR_S12_RMSK 0x3fffff +#define HWIO_UMCMN_R0_IMR_S12_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S12_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S12_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S12_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S12_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S12_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S12_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S12_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S12_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S12_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S12_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S12_IN(x)) +#define HWIO_UMCMN_R0_IMR_S12_TCL_PARSER_OUT_TLV_SEQ_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_PARSER_OUT_TLV_SEQ_ERR_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S12_TCL_PPE2TCL1_ZERO_LEN_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_PPE2TCL1_ZERO_LEN_ERR_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL_CREDIT2_ZERO_LEN_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL_CREDIT2_ZERO_LEN_ERR_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_LENGTH_ERROR_INT_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_LENGTH_ERROR_INT_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S12_TCL_BANK_ID_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_BANK_ID_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S12_TCL_WDG_WARNING_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_WDG_WARNING_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL5_ZERO_LEN_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL5_ZERO_LEN_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL4_ZERO_LEN_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL4_ZERO_LEN_ERR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CCE_ERR_CLASSIFY_DIS_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CCE_ERR_CLASSIFY_DIS_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CCE_WDG_TO_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CCE_WDG_TO_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_IPV6_JUMBOGRAM_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_IPV6_JUMBOGRAM_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_MSDU_LEN_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_MSDU_LEN_ERR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_ETH_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_ETH_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_WMAC_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_WMAC_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_WDG_TO_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_WDG_TO_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL_CREDIT_ZERO_LEN_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL_CREDIT_ZERO_LEN_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S12_TCL_FW2TCL1_ZERO_LEN_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S12_TCL_FW2TCL1_ZERO_LEN_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL3_ZERO_LEN_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL3_ZERO_LEN_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL2_ZERO_LEN_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL2_ZERO_LEN_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL1_ZERO_LEN_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL1_ZERO_LEN_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S12_TCL_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S12_TCL_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S13_ADDR(x) ((x) + 0xb0) +#define HWIO_UMCMN_R0_IMR_S13_PHYS(x) ((x) + 0xb0) +#define HWIO_UMCMN_R0_IMR_S13_OFFS (0xb0) +#define HWIO_UMCMN_R0_IMR_S13_RMSK 0x3ffff +#define HWIO_UMCMN_R0_IMR_S13_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S13_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S13_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S13_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S13_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S13_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S13_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S13_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S13_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S13_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S13_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S13_IN(x)) +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_RELEASE_RING_REQ_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_RELEASE_RING_REQ_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_RELEASE_RING_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_RELEASE_RING_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS1_UPDATE_RING_REQ_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS1_UPDATE_RING_REQ_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS1_UPDATE_RING_WDG_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS1_UPDATE_RING_WDG_ERR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS_UPDATE_RING_REQ_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS_UPDATE_RING_REQ_ERR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS_UPDATE_RING_WDG_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS_UPDATE_RING_WDG_ERR_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_FETCH_RING_REQ_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_FETCH_RING_REQ_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_FETCH_RING_WDG_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_FETCH_RING_WDG_ERR_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV1_LINK_ID_MISMATCH_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV1_LINK_ID_MISMATCH_ERR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV1_FLUSH_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV1_FLUSH_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV0_LINK_ID_MISMATCH_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV0_LINK_ID_MISMATCH_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV0_FLUSH_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV0_FLUSH_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S13_TQM_SW_CMD_RING_REQ_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S13_TQM_SW_CMD_RING_REQ_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S13_TQM_SW_CMD_RING_WDG_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S13_TQM_SW_CMD_RING_WDG_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT3_RING_REQ_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT3_RING_REQ_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT3_RING_WDG_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT3_RING_WDG_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT1_RING_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT1_RING_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT1_RING_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT1_RING_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S14_ADDR(x) ((x) + 0xb4) +#define HWIO_UMCMN_R0_IMR_S14_PHYS(x) ((x) + 0xb4) +#define HWIO_UMCMN_R0_IMR_S14_OFFS (0xb4) +#define HWIO_UMCMN_R0_IMR_S14_RMSK 0x7ffffff +#define HWIO_UMCMN_R0_IMR_S14_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S14_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S14_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S14_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S14_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S14_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S14_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S14_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S14_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S14_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S14_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S14_IN(x)) +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT2_SRNG_P_FETCH_POLLING_TIMEOUT_INT_BMSK 0x4000000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT2_SRNG_P_FETCH_POLLING_TIMEOUT_INT_SHFT 26 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT2_SRNG_P_REQ_ERR_INT_BMSK 0x2000000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT2_SRNG_P_REQ_ERR_INT_SHFT 25 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT2_SRNG_P_WATCHDOG_ERR_INT_BMSK 0x1000000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT2_SRNG_P_WATCHDOG_ERR_INT_SHFT 24 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT1_SRNG_P_FETCH_POLLING_TIMEOUT_INT_BMSK 0x800000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT1_SRNG_P_FETCH_POLLING_TIMEOUT_INT_SHFT 23 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT1_SRNG_P_REQ_ERR_INT_BMSK 0x400000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT1_SRNG_P_REQ_ERR_INT_SHFT 22 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT1_SRNG_P_WATCHDOG_ERR_INT_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT1_SRNG_P_WATCHDOG_ERR_INT_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN2_SRNG_C_FETCH_POLLING_TIMEOUT_INT_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN2_SRNG_C_FETCH_POLLING_TIMEOUT_INT_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN2_SRNG_C_REQ_ERR_INT_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN2_SRNG_C_REQ_ERR_INT_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN2_SRNG_C_WATCHDOG_ERR_INT_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN2_SRNG_C_WATCHDOG_ERR_INT_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN1_SRNG_C_FETCH_POLLING_TIMEOUT_INT_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN1_SRNG_C_FETCH_POLLING_TIMEOUT_INT_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN1_SRNG_C_REQ_ERR_INT_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN1_SRNG_C_REQ_ERR_INT_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN1_SRNG_C_WATCHDOG_ERR_INT_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN1_SRNG_C_WATCHDOG_ERR_INT_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S14_TQM_CACHE_CTL_ERR_BMSK 0x7ff8 +#define HWIO_UMCMN_R0_IMR_S14_TQM_CACHE_CTL_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S14_TQM_WARNING_WDG_TIMEOUT_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S14_TQM_WARNING_WDG_TIMEOUT_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S14_TQM_HW_ERROR_INTR_TIMEOUT_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S14_TQM_HW_ERROR_INTR_TIMEOUT_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S14_TQM_SW_PRGM_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S14_TQM_SW_PRGM_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S15_ADDR(x) ((x) + 0xb8) +#define HWIO_UMCMN_R0_IMR_S15_PHYS(x) ((x) + 0xb8) +#define HWIO_UMCMN_R0_IMR_S15_OFFS (0xb8) +#define HWIO_UMCMN_R0_IMR_S15_RMSK 0x7fff +#define HWIO_UMCMN_R0_IMR_S15_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S15_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S15_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S15_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S15_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S15_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S15_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S15_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S15_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S15_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S15_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S15_IN(x)) +#define HWIO_UMCMN_R0_IMR_S15_TQM_UNPAUSE_LINK_DESC_THRESHOLD_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S15_TQM_UNPAUSE_LINK_DESC_THRESHOLD_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S15_TQM_ILLEGAL_HWSCH_CMD_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S15_TQM_ILLEGAL_HWSCH_CMD_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S15_TQM_ILLEGAL_SW_CMD_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S15_TQM_ILLEGAL_SW_CMD_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT2_DEC_EMPTY_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT2_DEC_EMPTY_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT1_DEC_EMPTY_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT1_DEC_EMPTY_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT0_DEC_EMPTY_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT0_DEC_EMPTY_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT2_SATURATE_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT2_SATURATE_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT1_SATURATE_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT1_SATURATE_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT0_SATURATE_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT0_SATURATE_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_THRESHOLD2_REACHED_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_THRESHOLD2_REACHED_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_THRESHOLD1_REACHED_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_THRESHOLD1_REACHED_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_THRESHOLD0_REACHED_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_THRESHOLD0_REACHED_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S15_TQM_AGGR_LINK_DESC_THRESHOLD_REACHED_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S15_TQM_AGGR_LINK_DESC_THRESHOLD_REACHED_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S15_TQM_SW_CMD1_RING_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S15_TQM_SW_CMD1_RING_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S15_TQM_SW_CMD1_RING_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S15_TQM_SW_CMD1_RING_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S16_ADDR(x) ((x) + 0xbc) +#define HWIO_UMCMN_R0_IMR_S16_PHYS(x) ((x) + 0xbc) +#define HWIO_UMCMN_R0_IMR_S16_OFFS (0xbc) +#define HWIO_UMCMN_R0_IMR_S16_RMSK 0x1ff +#define HWIO_UMCMN_R0_IMR_S16_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S16_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S16_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S16_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S16_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S16_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S16_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S16_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S16_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S16_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S16_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S16_IN(x)) +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_WDTO_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_WDTO_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_AXI_WR_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_AXI_WR_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_AXI_RD_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_AXI_RD_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_LAST_WR_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_LAST_WR_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_WDTO_WAR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_WDTO_WAR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S17_ADDR(x) ((x) + 0xc0) +#define HWIO_UMCMN_R0_IMR_S17_PHYS(x) ((x) + 0xc0) +#define HWIO_UMCMN_R0_IMR_S17_OFFS (0xc0) +#define HWIO_UMCMN_R0_IMR_S17_RMSK 0xffff +#define HWIO_UMCMN_R0_IMR_S17_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S17_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S17_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S17_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S17_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S17_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S17_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S17_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S17_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S17_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S17_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S17_IN(x)) +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_MLO_P_WATCHDOG_ERR_INT_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_MLO_P_WATCHDOG_ERR_INT_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_MLO_P_WATCHDOG_ERR_INT_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_MLO_P_WATCHDOG_ERR_INT_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_RING_REQ_ERROR_INTR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_RING_REQ_ERROR_INTR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_RING_REQ_ERROR_INTR_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_RING_REQ_ERROR_INTR_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_RING_WATCHDOG_ERR_INTR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_RING_WATCHDOG_ERR_INTR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_RING_WATCHDOG_ERR_INTR_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_RING_WATCHDOG_ERR_INTR_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN2_RING_WATCHDOG_ERR_INTR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN2_RING_WATCHDOG_ERR_INTR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN1_RING_WATCHDOG_ERR_INTR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN1_RING_WATCHDOG_ERR_INTR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN2_RING_REQ_ERROR_INTR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN2_RING_REQ_ERROR_INTR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN1_RING_REQ_ERROR_INTR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN1_RING_REQ_ERROR_INTR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_FETCH_POINTER_ERR_INTR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_FETCH_POINTER_ERR_INTR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_FETCH_POINTER_ERR_INTR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_FETCH_POINTER_ERR_INTR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN2_FETCH_POINTER_ERR_INTR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN2_FETCH_POINTER_ERR_INTR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN1_FETCH_POINTER_ERR_INTR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN1_FETCH_POINTER_ERR_INTR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S17_SW1_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S17_SW1_RELEASE_RING_REQ_ERROR_INTR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S17_SW1_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S17_SW1_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 0 + +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_ADDR(x) ((x) + 0xc4) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_PHYS(x) ((x) + 0xc4) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_OFFS (0xc4) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_RMSK 0x1 +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_POR 0x00000000 +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_ATTR 0x3 +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_IN(x) \ + in_dword(HWIO_UMCMN_R0_WOCLR_ISR_P_EN_ADDR(x)) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_WOCLR_ISR_P_EN_ADDR(x), m) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_WOCLR_ISR_P_EN_ADDR(x),v) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_WOCLR_ISR_P_EN_ADDR(x),m,v,HWIO_UMCMN_R0_WOCLR_ISR_P_EN_IN(x)) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_VAL_BMSK 0x1 +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_VAL_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_REVISION_ADDR(x) ((x) + 0xc8) +#define HWIO_UMCMN_R0_UMAC_REVISION_PHYS(x) ((x) + 0xc8) +#define HWIO_UMCMN_R0_UMAC_REVISION_OFFS (0xc8) +#define HWIO_UMCMN_R0_UMAC_REVISION_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_REVISION_POR 0x20050000 +#define HWIO_UMCMN_R0_UMAC_REVISION_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_REVISION_ATTR 0x1 +#define HWIO_UMCMN_R0_UMAC_REVISION_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_REVISION_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_REVISION_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_REVISION_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_REVISION_MAJOR_BMSK 0xf0000000 +#define HWIO_UMCMN_R0_UMAC_REVISION_MAJOR_SHFT 28 +#define HWIO_UMCMN_R0_UMAC_REVISION_MINOR_BMSK 0xfff0000 +#define HWIO_UMCMN_R0_UMAC_REVISION_MINOR_SHFT 16 +#define HWIO_UMCMN_R0_UMAC_REVISION_STEP_BMSK 0xffff +#define HWIO_UMCMN_R0_UMAC_REVISION_STEP_SHFT 0 + +#define HWIO_UMCMN_R0_IDLE_CTRL0_ADDR(x) ((x) + 0xcc) +#define HWIO_UMCMN_R0_IDLE_CTRL0_PHYS(x) ((x) + 0xcc) +#define HWIO_UMCMN_R0_IDLE_CTRL0_OFFS (0xcc) +#define HWIO_UMCMN_R0_IDLE_CTRL0_RMSK 0x3bffff +#define HWIO_UMCMN_R0_IDLE_CTRL0_POR 0x000007de +#define HWIO_UMCMN_R0_IDLE_CTRL0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IDLE_CTRL0_ATTR 0x3 +#define HWIO_UMCMN_R0_IDLE_CTRL0_IN(x) \ + in_dword(HWIO_UMCMN_R0_IDLE_CTRL0_ADDR(x)) +#define HWIO_UMCMN_R0_IDLE_CTRL0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IDLE_CTRL0_ADDR(x), m) +#define HWIO_UMCMN_R0_IDLE_CTRL0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IDLE_CTRL0_ADDR(x),v) +#define HWIO_UMCMN_R0_IDLE_CTRL0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IDLE_CTRL0_ADDR(x),m,v,HWIO_UMCMN_R0_IDLE_CTRL0_IN(x)) +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_NOC_IDLE_REQ_BMSK 0x200000 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_NOC_IDLE_REQ_SHFT 21 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_WBM_IDLE_REQ_BMSK 0x100000 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_WBM_IDLE_REQ_SHFT 20 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_TQM_IDLE_REQ_BMSK 0x80000 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_TQM_IDLE_REQ_SHFT 19 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_REO_IDLE_REQ_BMSK 0x20000 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_REO_IDLE_REQ_SHFT 17 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_TCL_IDLE_REQ_BMSK 0x10000 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_TCL_IDLE_REQ_SHFT 16 +#define HWIO_UMCMN_R0_IDLE_CTRL0_INTER_STATE_DLY_BMSK 0xffc0 +#define HWIO_UMCMN_R0_IDLE_CTRL0_INTER_STATE_DLY_SHFT 6 +#define HWIO_UMCMN_R0_IDLE_CTRL0_IDLE_INTG_CHK_DLY_BMSK 0x3e +#define HWIO_UMCMN_R0_IDLE_CTRL0_IDLE_INTG_CHK_DLY_SHFT 1 +#define HWIO_UMCMN_R0_IDLE_CTRL0_SW_IDLE_REQ_BMSK 0x1 +#define HWIO_UMCMN_R0_IDLE_CTRL0_SW_IDLE_REQ_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_ADDR(x) ((x) + 0xd0) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_PHYS(x) ((x) + 0xd0) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_OFFS (0xd0) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_RMSK 0x1f9f +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_POR 0x00000000 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_ATTR 0x3 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_ADDR(x),v) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_ADDR(x),m,v,HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_IN(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_NOC_IDLE_REQ_SW_DATA_BMSK 0x1000 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_NOC_IDLE_REQ_SW_DATA_SHFT 12 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_NOC_IDLE_REQ_SW_OVR_BMSK 0x800 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_NOC_IDLE_REQ_SW_OVR_SHFT 11 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_WBM_IDLE_REQ_SW_DATA_BMSK 0x400 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_WBM_IDLE_REQ_SW_DATA_SHFT 10 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_WBM_IDLE_REQ_SW_OVR_BMSK 0x200 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_WBM_IDLE_REQ_SW_OVR_SHFT 9 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TQM_IDLE_REQ_SW_DATA_BMSK 0x100 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TQM_IDLE_REQ_SW_DATA_SHFT 8 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TQM_IDLE_REQ_SW_OVR_BMSK 0x80 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TQM_IDLE_REQ_SW_OVR_SHFT 7 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_REO_IDLE_REQ_SW_DATA_BMSK 0x10 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_REO_IDLE_REQ_SW_DATA_SHFT 4 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_REO_IDLE_REQ_SW_OVR_BMSK 0x8 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_REO_IDLE_REQ_SW_OVR_SHFT 3 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TCL_IDLE_REQ_SW_DATA_BMSK 0x4 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TCL_IDLE_REQ_SW_DATA_SHFT 2 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TCL_IDLE_REQ_SW_OVR_BMSK 0x2 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TCL_IDLE_REQ_SW_OVR_SHFT 1 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_GLOBAL_SW_OVR_BMSK 0x1 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_GLOBAL_SW_OVR_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_ADDR(x) ((x) + 0xd4) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_PHYS(x) ((x) + 0xd4) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_OFFS (0xd4) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_RMSK 0x3ffff +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_POR 0x00000001 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_ATTR 0x3 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_ADDR(x),v) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_ADDR(x),m,v,HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_IN(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_FSM_WAIT_IN_STATE_BMSK 0x3fffc +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_FSM_WAIT_IN_STATE_SHFT 2 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_FSM_FORCE_IDLE_BMSK 0x2 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_FSM_FORCE_IDLE_SHFT 1 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_FSM_EN_BMSK 0x1 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_FSM_EN_SHFT 0 + +#define HWIO_UMCMN_R0_IDLE_SIGNAL_ADDR(x) ((x) + 0xd8) +#define HWIO_UMCMN_R0_IDLE_SIGNAL_PHYS(x) ((x) + 0xd8) +#define HWIO_UMCMN_R0_IDLE_SIGNAL_OFFS (0xd8) +#define HWIO_UMCMN_R0_IDLE_SIGNAL_RMSK 0x1f +#define HWIO_UMCMN_R0_IDLE_SIGNAL_POR 0x0000001f +#define HWIO_UMCMN_R0_IDLE_SIGNAL_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IDLE_SIGNAL_ATTR 0x1 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_IN(x) \ + in_dword(HWIO_UMCMN_R0_IDLE_SIGNAL_ADDR(x)) +#define HWIO_UMCMN_R0_IDLE_SIGNAL_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IDLE_SIGNAL_ADDR(x), m) +#define HWIO_UMCMN_R0_IDLE_SIGNAL_MXI_BMSK 0x10 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_MXI_SHFT 4 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_REO_BMSK 0x8 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_REO_SHFT 3 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_TCL_BMSK 0x4 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_TCL_SHFT 2 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_WBM_BMSK 0x2 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_WBM_SHFT 1 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_TQM_BMSK 0x1 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_TQM_SHFT 0 + +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_ADDR(x) ((x) + 0xdc) +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_PHYS(x) ((x) + 0xdc) +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_OFFS (0xdc) +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_RMSK 0x1e +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_POR 0x00000000 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_ATTR 0x1 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_IN(x) \ + in_dword(HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_ADDR(x)) +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_ADDR(x), m) +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_WBM_REL_RING_BMSK 0x10 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_WBM_REL_RING_SHFT 4 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_TQM_CMD_RING_BMSK 0x8 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_TQM_CMD_RING_SHFT 3 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_REO_CMD_RING_BMSK 0x4 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_REO_CMD_RING_SHFT 2 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_TCL_CMD_RING_BMSK 0x2 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_TCL_CMD_RING_SHFT 1 + +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_ADDR(x) ((x) + 0xe0) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_PHYS(x) ((x) + 0xe0) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_OFFS (0xe0) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_RMSK 0xfcf +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_POR 0x00000000 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_ATTR 0x3 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_ADDR(x),v) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_ADDR(x),m,v,HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_IN(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_NOC_IDLE_SWOVR_DATA_BMSK 0x800 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_NOC_IDLE_SWOVR_DATA_SHFT 11 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_NOC_IDLE_SWOVR_BMSK 0x400 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_NOC_IDLE_SWOVR_SHFT 10 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_WBM_IDLE_SWOVR_DATA_BMSK 0x200 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_WBM_IDLE_SWOVR_DATA_SHFT 9 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_WBM_IDLE_SWOVR_BMSK 0x100 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_WBM_IDLE_SWOVR_SHFT 8 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TQM_IDLE_SWOVR_DATA_BMSK 0x80 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TQM_IDLE_SWOVR_DATA_SHFT 7 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TQM_IDLE_SWOVR_BMSK 0x40 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TQM_IDLE_SWOVR_SHFT 6 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_REO_IDLE_SWOVR_DATA_BMSK 0x8 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_REO_IDLE_SWOVR_DATA_SHFT 3 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_REO_IDLE_SWOVR_BMSK 0x4 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_REO_IDLE_SWOVR_SHFT 2 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TCL_IDLE_SWOVR_DATA_BMSK 0x2 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TCL_IDLE_SWOVR_DATA_SHFT 1 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TCL_IDLE_SWOVR_BMSK 0x1 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TCL_IDLE_SWOVR_SHFT 0 + +#define HWIO_UMCMN_R0_S_PARE_0_ADDR(x) ((x) + 0xe4) +#define HWIO_UMCMN_R0_S_PARE_0_PHYS(x) ((x) + 0xe4) +#define HWIO_UMCMN_R0_S_PARE_0_OFFS (0xe4) +#define HWIO_UMCMN_R0_S_PARE_0_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_0_POR 0x00000000 +#define HWIO_UMCMN_R0_S_PARE_0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_0_ATTR 0x3 +#define HWIO_UMCMN_R0_S_PARE_0_IN(x) \ + in_dword(HWIO_UMCMN_R0_S_PARE_0_ADDR(x)) +#define HWIO_UMCMN_R0_S_PARE_0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_S_PARE_0_ADDR(x), m) +#define HWIO_UMCMN_R0_S_PARE_0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_S_PARE_0_ADDR(x),v) +#define HWIO_UMCMN_R0_S_PARE_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_S_PARE_0_ADDR(x),m,v,HWIO_UMCMN_R0_S_PARE_0_IN(x)) +#define HWIO_UMCMN_R0_S_PARE_0_S_PARE_0_BITS_BMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_0_S_PARE_0_BITS_SHFT 0 + +#define HWIO_UMCMN_R0_S_PARE_1_ADDR(x) ((x) + 0xe8) +#define HWIO_UMCMN_R0_S_PARE_1_PHYS(x) ((x) + 0xe8) +#define HWIO_UMCMN_R0_S_PARE_1_OFFS (0xe8) +#define HWIO_UMCMN_R0_S_PARE_1_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_1_POR 0x00000000 +#define HWIO_UMCMN_R0_S_PARE_1_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_1_ATTR 0x3 +#define HWIO_UMCMN_R0_S_PARE_1_IN(x) \ + in_dword(HWIO_UMCMN_R0_S_PARE_1_ADDR(x)) +#define HWIO_UMCMN_R0_S_PARE_1_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_S_PARE_1_ADDR(x), m) +#define HWIO_UMCMN_R0_S_PARE_1_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_S_PARE_1_ADDR(x),v) +#define HWIO_UMCMN_R0_S_PARE_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_S_PARE_1_ADDR(x),m,v,HWIO_UMCMN_R0_S_PARE_1_IN(x)) +#define HWIO_UMCMN_R0_S_PARE_1_S_PARE_1_BITS_BMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_1_S_PARE_1_BITS_SHFT 0 + +#define HWIO_UMCMN_R0_S_PARE_2_ADDR(x) ((x) + 0xec) +#define HWIO_UMCMN_R0_S_PARE_2_PHYS(x) ((x) + 0xec) +#define HWIO_UMCMN_R0_S_PARE_2_OFFS (0xec) +#define HWIO_UMCMN_R0_S_PARE_2_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_2_POR 0x00000000 +#define HWIO_UMCMN_R0_S_PARE_2_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_2_ATTR 0x3 +#define HWIO_UMCMN_R0_S_PARE_2_IN(x) \ + in_dword(HWIO_UMCMN_R0_S_PARE_2_ADDR(x)) +#define HWIO_UMCMN_R0_S_PARE_2_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_S_PARE_2_ADDR(x), m) +#define HWIO_UMCMN_R0_S_PARE_2_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_S_PARE_2_ADDR(x),v) +#define HWIO_UMCMN_R0_S_PARE_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_S_PARE_2_ADDR(x),m,v,HWIO_UMCMN_R0_S_PARE_2_IN(x)) +#define HWIO_UMCMN_R0_S_PARE_2_S_PARE_2_BITS_BMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_2_S_PARE_2_BITS_SHFT 0 + +#define HWIO_UMCMN_R0_S_PARE_3_ADDR(x) ((x) + 0xf0) +#define HWIO_UMCMN_R0_S_PARE_3_PHYS(x) ((x) + 0xf0) +#define HWIO_UMCMN_R0_S_PARE_3_OFFS (0xf0) +#define HWIO_UMCMN_R0_S_PARE_3_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_3_POR 0x00000000 +#define HWIO_UMCMN_R0_S_PARE_3_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_3_ATTR 0x3 +#define HWIO_UMCMN_R0_S_PARE_3_IN(x) \ + in_dword(HWIO_UMCMN_R0_S_PARE_3_ADDR(x)) +#define HWIO_UMCMN_R0_S_PARE_3_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_S_PARE_3_ADDR(x), m) +#define HWIO_UMCMN_R0_S_PARE_3_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_S_PARE_3_ADDR(x),v) +#define HWIO_UMCMN_R0_S_PARE_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_S_PARE_3_ADDR(x),m,v,HWIO_UMCMN_R0_S_PARE_3_IN(x)) +#define HWIO_UMCMN_R0_S_PARE_3_S_PARE_3_BITS_BMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_3_S_PARE_3_BITS_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_ADDR(x) ((x) + 0xf4) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_PHYS(x) ((x) + 0xf4) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_OFFS (0xf4) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_RMSK 0xffff +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_POR 0x00000008 +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_ATTR 0x3 +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_ADDR(x),v) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_ADDR(x),m,v,HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_IN(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_VALUE_BMSK 0xffff +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_ADDR(x) ((x) + 0xfc) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_PHYS(x) ((x) + 0xfc) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_OFFS (0xfc) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_RMSK 0xf +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_POR 0x00000000 +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_ATTR 0x3 +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_ADDR(x),v) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_ADDR(x),m,v,HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_IN(x)) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_SUBSYSTEM_ID_BMSK 0xc +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_SUBSYSTEM_ID_SHFT 2 +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_TESTBUS_VALID_CONTROL_BMSK 0x3 +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_TESTBUS_VALID_CONTROL_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_ADDR(x) ((x) + 0x100) +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_PHYS(x) ((x) + 0x100) +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_OFFS (0x100) +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_RMSK 0x3f +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_POR 0x00000000 +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_ATTR 0x1 +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_NOC_MONITOR_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_NOC_MONITOR_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_UMAC_NOC_DCD_CLKON_OUT_BMSK 0x20 +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_UMAC_NOC_DCD_CLKON_OUT_SHFT 5 +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_UMAC_NOC_DCD_CLKDIV_BMSK 0x1f +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_UMAC_NOC_DCD_CLKDIV_SHFT 0 + +#define HWIO_UMCMN_R0_BUF_INIT_ADDR(x) ((x) + 0x104) +#define HWIO_UMCMN_R0_BUF_INIT_PHYS(x) ((x) + 0x104) +#define HWIO_UMCMN_R0_BUF_INIT_OFFS (0x104) +#define HWIO_UMCMN_R0_BUF_INIT_RMSK 0x1 +#define HWIO_UMCMN_R0_BUF_INIT_POR 0x00000000 +#define HWIO_UMCMN_R0_BUF_INIT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_BUF_INIT_ATTR 0x3 +#define HWIO_UMCMN_R0_BUF_INIT_IN(x) \ + in_dword(HWIO_UMCMN_R0_BUF_INIT_ADDR(x)) +#define HWIO_UMCMN_R0_BUF_INIT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_BUF_INIT_ADDR(x), m) +#define HWIO_UMCMN_R0_BUF_INIT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_BUF_INIT_ADDR(x),v) +#define HWIO_UMCMN_R0_BUF_INIT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_BUF_INIT_ADDR(x),m,v,HWIO_UMCMN_R0_BUF_INIT_IN(x)) +#define HWIO_UMCMN_R0_BUF_INIT_VALUE_BMSK 0x1 +#define HWIO_UMCMN_R0_BUF_INIT_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_CONTROL_ADDR(x) ((x) + 0x108) +#define HWIO_UMCMN_R0_CONTROL_PHYS(x) ((x) + 0x108) +#define HWIO_UMCMN_R0_CONTROL_OFFS (0x108) +#define HWIO_UMCMN_R0_CONTROL_RMSK 0x1 +#define HWIO_UMCMN_R0_CONTROL_POR 0x00000000 +#define HWIO_UMCMN_R0_CONTROL_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CONTROL_ATTR 0x3 +#define HWIO_UMCMN_R0_CONTROL_IN(x) \ + in_dword(HWIO_UMCMN_R0_CONTROL_ADDR(x)) +#define HWIO_UMCMN_R0_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CONTROL_ADDR(x), m) +#define HWIO_UMCMN_R0_CONTROL_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CONTROL_ADDR(x),v) +#define HWIO_UMCMN_R0_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CONTROL_ADDR(x),m,v,HWIO_UMCMN_R0_CONTROL_IN(x)) +#define HWIO_UMCMN_R0_CONTROL_ENABLE_VALUE_BMSK 0x1 +#define HWIO_UMCMN_R0_CONTROL_ENABLE_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_ADDR(x) ((x) + 0x10c) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_PHYS(x) ((x) + 0x10c) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_OFFS (0x10c) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_POR 0x00000000 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_ATTR 0x3 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_IN(x) \ + in_dword(HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_ADDR(x)) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_ADDR(x), m) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_ADDR(x),v) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_ADDR(x),m,v,HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_IN(x)) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_CLK_ENS_EXTEND_BMSK 0x80000000 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_CLK_ENS_EXTEND_SHFT 31 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_CLK_ENS_EXTEND_APB_BMSK 0x40000000 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_CLK_ENS_EXTEND_APB_SHFT 30 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_TBD_BMSK 0x3ffffffc +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_TBD_SHFT 2 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_APB_VAL_BMSK 0x2 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_APB_VAL_SHFT 1 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_VAL_BMSK 0x1 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_VAL_SHFT 0 + +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_ADDR(x) ((x) + 0x110) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_PHYS(x) ((x) + 0x110) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_OFFS (0x110) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_RMSK 0x7f +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_POR 0x00000000 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_ATTR 0x3 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_IN(x) \ + in_dword(HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_ADDR(x)) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_ADDR(x), m) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_ADDR(x),v) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_ADDR(x),m,v,HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_IN(x)) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK 0x40 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT 6 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_CLK_WCMN_MISC_EVENT_BMSK 0x20 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_CLK_WCMN_MISC_EVENT_SHFT 5 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_WCMN_MISC_EVENT_BMSK 0x10 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_WCMN_MISC_EVENT_SHFT 4 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_CLK_WMAC2_BMSK 0x8 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_CLK_WMAC2_SHFT 3 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_CLK_WMAC1_BMSK 0x4 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_CLK_WMAC1_SHFT 2 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_WMAC2_BMSK 0x2 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_WMAC2_SHFT 1 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_WMAC1_BMSK 0x1 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_WMAC1_SHFT 0 + +#define HWIO_UMCMN_R0_VID0_ADDR(x) ((x) + 0x114) +#define HWIO_UMCMN_R0_VID0_PHYS(x) ((x) + 0x114) +#define HWIO_UMCMN_R0_VID0_OFFS (0x114) +#define HWIO_UMCMN_R0_VID0_RMSK 0x1ffffff1 +#define HWIO_UMCMN_R0_VID0_POR 0x0d314830 +#define HWIO_UMCMN_R0_VID0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_VID0_ATTR 0x3 +#define HWIO_UMCMN_R0_VID0_IN(x) \ + in_dword(HWIO_UMCMN_R0_VID0_ADDR(x)) +#define HWIO_UMCMN_R0_VID0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_VID0_ADDR(x), m) +#define HWIO_UMCMN_R0_VID0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_VID0_ADDR(x),v) +#define HWIO_UMCMN_R0_VID0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_VID0_ADDR(x),m,v,HWIO_UMCMN_R0_VID0_IN(x)) +#define HWIO_UMCMN_R0_VID0_MXI_BMSK 0x1f000000 +#define HWIO_UMCMN_R0_VID0_MXI_SHFT 24 +#define HWIO_UMCMN_R0_VID0_TCL_BMSK 0xf80000 +#define HWIO_UMCMN_R0_VID0_TCL_SHFT 19 +#define HWIO_UMCMN_R0_VID0_WBM_BMSK 0x7c000 +#define HWIO_UMCMN_R0_VID0_WBM_SHFT 14 +#define HWIO_UMCMN_R0_VID0_TQM_BMSK 0x3e00 +#define HWIO_UMCMN_R0_VID0_TQM_SHFT 9 +#define HWIO_UMCMN_R0_VID0_REO_BMSK 0x1f0 +#define HWIO_UMCMN_R0_VID0_REO_SHFT 4 +#define HWIO_UMCMN_R0_VID0_MODULE_EN_BMSK 0x1 +#define HWIO_UMCMN_R0_VID0_MODULE_EN_SHFT 0 + +#define HWIO_UMCMN_R0_VID0_EXT_ADDR(x) ((x) + 0x118) +#define HWIO_UMCMN_R0_VID0_EXT_PHYS(x) ((x) + 0x118) +#define HWIO_UMCMN_R0_VID0_EXT_OFFS (0x118) +#define HWIO_UMCMN_R0_VID0_EXT_RMSK 0xfffff +#define HWIO_UMCMN_R0_VID0_EXT_POR 0x0005a928 +#define HWIO_UMCMN_R0_VID0_EXT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_VID0_EXT_ATTR 0x3 +#define HWIO_UMCMN_R0_VID0_EXT_IN(x) \ + in_dword(HWIO_UMCMN_R0_VID0_EXT_ADDR(x)) +#define HWIO_UMCMN_R0_VID0_EXT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_VID0_EXT_ADDR(x), m) +#define HWIO_UMCMN_R0_VID0_EXT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_VID0_EXT_ADDR(x),v) +#define HWIO_UMCMN_R0_VID0_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_VID0_EXT_ADDR(x),m,v,HWIO_UMCMN_R0_VID0_EXT_IN(x)) +#define HWIO_UMCMN_R0_VID0_EXT_TQM2_BMSK 0xf8000 +#define HWIO_UMCMN_R0_VID0_EXT_TQM2_SHFT 15 +#define HWIO_UMCMN_R0_VID0_EXT_REO2_BMSK 0x7c00 +#define HWIO_UMCMN_R0_VID0_EXT_REO2_SHFT 10 +#define HWIO_UMCMN_R0_VID0_EXT_WBM2_BMSK 0x3e0 +#define HWIO_UMCMN_R0_VID0_EXT_WBM2_SHFT 5 +#define HWIO_UMCMN_R0_VID0_EXT_TCL_1_BMSK 0x1f +#define HWIO_UMCMN_R0_VID0_EXT_TCL_1_SHFT 0 + +#define HWIO_UMCMN_R0_SS_ID_ADDR(x) ((x) + 0x11c) +#define HWIO_UMCMN_R0_SS_ID_PHYS(x) ((x) + 0x11c) +#define HWIO_UMCMN_R0_SS_ID_OFFS (0x11c) +#define HWIO_UMCMN_R0_SS_ID_RMSK 0x7e1 +#define HWIO_UMCMN_R0_SS_ID_POR 0x000001e0 +#define HWIO_UMCMN_R0_SS_ID_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_SS_ID_ATTR 0x3 +#define HWIO_UMCMN_R0_SS_ID_IN(x) \ + in_dword(HWIO_UMCMN_R0_SS_ID_ADDR(x)) +#define HWIO_UMCMN_R0_SS_ID_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_SS_ID_ADDR(x), m) +#define HWIO_UMCMN_R0_SS_ID_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_SS_ID_ADDR(x),v) +#define HWIO_UMCMN_R0_SS_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_SS_ID_ADDR(x),m,v,HWIO_UMCMN_R0_SS_ID_IN(x)) +#define HWIO_UMCMN_R0_SS_ID_WCMN_MISC_BMSK 0x600 +#define HWIO_UMCMN_R0_SS_ID_WCMN_MISC_SHFT 9 +#define HWIO_UMCMN_R0_SS_ID_UMAC_DBG_BMSK 0x180 +#define HWIO_UMCMN_R0_SS_ID_UMAC_DBG_SHFT 7 +#define HWIO_UMCMN_R0_SS_ID_UMAC_BMSK 0x60 +#define HWIO_UMCMN_R0_SS_ID_UMAC_SHFT 5 +#define HWIO_UMCMN_R0_SS_ID_ENABLE_BMSK 0x1 +#define HWIO_UMCMN_R0_SS_ID_ENABLE_SHFT 0 + +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ADDR(x) ((x) + 0x120) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_PHYS(x) ((x) + 0x120) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_OFFS (0x120) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_RMSK 0x1 +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_POR 0x00000000 +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ATTR 0x3 +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_IN(x) \ + in_dword(HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ADDR(x)) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ADDR(x), m) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ADDR(x),v) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ADDR(x),m,v,HWIO_UMCMN_R0_CLK_TESTBUS_OUT_IN(x)) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ENABLE_BMSK 0x1 +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ENABLE_SHFT 0 + +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_ADDR(base,n) ((base) + 0X124 + (0x4*(n))) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_PHYS(base,n) ((base) + 0X124 + (0x4*(n))) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_OFFS(n) (0X124 + (0x4*(n))) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_RMSK 0x7c1f +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_MAXn 7 +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_POR 0x00000000 +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_ATTR 0x3 +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_INI(base,n) \ + in_dword_masked(HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_ADDR(base,n), HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_RMSK) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_ADDR(base,n), mask) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_OUTI(base,n,val) \ + out_dword(HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_ADDR(base,n),val) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_ADDR(base,n),mask,val,HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_INI(base,n)) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_BLK_SEL_BMSK 0x7c00 +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_BLK_SEL_SHFT 10 +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_SIG_SEL_BMSK 0x1f +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_SIG_SEL_SHFT 0 + +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_ADDR(base,n) ((base) + 0X144 + (0x4*(n))) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_PHYS(base,n) ((base) + 0X144 + (0x4*(n))) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_OFFS(n) (0X144 + (0x4*(n))) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_RMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_MAXn 7 +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_POR 0x00000000 +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_ATTR 0x1 +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_INI(base,n) \ + in_dword_masked(HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_ADDR(base,n), HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_RMSK) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_ADDR(base,n), mask) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_VALUE_BMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_ADDR(x) ((x) + 0x164) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_PHYS(x) ((x) + 0x164) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_OFFS (0x164) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_RMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_POR 0x00000000 +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_ATTR 0x3 +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_IN(x) \ + in_dword(HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_ADDR(x)) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_ADDR(x), m) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_ADDR(x),v) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_ADDR(x),m,v,HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_IN(x)) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_VALUE_BMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x) ((x) + 0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x) ((x) + 0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS (0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK 0xf +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR 0x0000000a +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR 0x3 +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x) \ + in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK 0xf +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_LINK_ID_ADDR(x) ((x) + 0x16c) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_PHYS(x) ((x) + 0x16c) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_OFFS (0x16c) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_RMSK 0x3ffff +#define HWIO_UMCMN_R0_UMAC_LINK_ID_POR 0x0002c688 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_LINK_ID_ATTR 0x3 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_LINK_ID_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_LINK_ID_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMAC_LINK_ID_ADDR(x),v) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMAC_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_UMAC_LINK_ID_IN(x)) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_5_BMSK 0x38000 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_5_SHFT 15 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_4_BMSK 0x7000 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_4_SHFT 12 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_3_BMSK 0xe00 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_3_SHFT 9 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_2_BMSK 0x1c0 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_2_SHFT 6 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_1_BMSK 0x38 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_1_SHFT 3 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_0_BMSK 0x7 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_0_SHFT 0 + +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_ADDR(x) ((x) + 0x170) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_PHYS(x) ((x) + 0x170) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_OFFS (0x170) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_RMSK 0x3f +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_POR 0x0000003f +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_ATTR 0x3 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_IN(x) \ + in_dword(HWIO_UMCMN_R0_ENABLE_LINK_ID_ADDR(x)) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ENABLE_LINK_ID_ADDR(x), m) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ENABLE_LINK_ID_ADDR(x),v) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ENABLE_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_ENABLE_LINK_ID_IN(x)) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_5_BMSK 0x20 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_5_SHFT 5 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_4_BMSK 0x10 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_4_SHFT 4 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_3_BMSK 0x8 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_3_SHFT 3 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_2_BMSK 0x4 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_2_SHFT 2 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_1_BMSK 0x2 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_1_SHFT 1 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_0_BMSK 0x1 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_0_SHFT 0 + +#define HWIO_UMCMN_R0_TRC_CTRL_1_ADDR(x) ((x) + 0x174) +#define HWIO_UMCMN_R0_TRC_CTRL_1_PHYS(x) ((x) + 0x174) +#define HWIO_UMCMN_R0_TRC_CTRL_1_OFFS (0x174) +#define HWIO_UMCMN_R0_TRC_CTRL_1_RMSK 0x7fffffff +#define HWIO_UMCMN_R0_TRC_CTRL_1_POR 0x00000000 +#define HWIO_UMCMN_R0_TRC_CTRL_1_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_TRC_CTRL_1_ATTR 0x3 +#define HWIO_UMCMN_R0_TRC_CTRL_1_IN(x) \ + in_dword(HWIO_UMCMN_R0_TRC_CTRL_1_ADDR(x)) +#define HWIO_UMCMN_R0_TRC_CTRL_1_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_TRC_CTRL_1_ADDR(x), m) +#define HWIO_UMCMN_R0_TRC_CTRL_1_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_TRC_CTRL_1_ADDR(x),v) +#define HWIO_UMCMN_R0_TRC_CTRL_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_TRC_CTRL_1_ADDR(x),m,v,HWIO_UMCMN_R0_TRC_CTRL_1_IN(x)) +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_EVENTBUS_VALID_BMSK 0x40000000 +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_EVENTBUS_VALID_SHFT 30 +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_MODULE_ID_BMSK 0x3c000000 +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_MODULE_ID_SHFT 26 +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_EVENT_ID_BMSK 0x3f00000 +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_EVENT_ID_SHFT 20 +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_EVENTDATA_BMSK 0xfffff +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_EVENTDATA_SHFT 0 + +#define HWIO_UMCMN_R0_TRC_CTRL_2_ADDR(x) ((x) + 0x178) +#define HWIO_UMCMN_R0_TRC_CTRL_2_PHYS(x) ((x) + 0x178) +#define HWIO_UMCMN_R0_TRC_CTRL_2_OFFS (0x178) +#define HWIO_UMCMN_R0_TRC_CTRL_2_RMSK 0xffffffff +#define HWIO_UMCMN_R0_TRC_CTRL_2_POR 0x00000000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_TRC_CTRL_2_ATTR 0x3 +#define HWIO_UMCMN_R0_TRC_CTRL_2_IN(x) \ + in_dword(HWIO_UMCMN_R0_TRC_CTRL_2_ADDR(x)) +#define HWIO_UMCMN_R0_TRC_CTRL_2_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_TRC_CTRL_2_ADDR(x), m) +#define HWIO_UMCMN_R0_TRC_CTRL_2_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_TRC_CTRL_2_ADDR(x),v) +#define HWIO_UMCMN_R0_TRC_CTRL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_TRC_CTRL_2_ADDR(x),m,v,HWIO_UMCMN_R0_TRC_CTRL_2_IN(x)) +#define HWIO_UMCMN_R0_TRC_CTRL_2_TRC_EVENT_SEL_BMSK 0x80000000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_TRC_EVENT_SEL_SHFT 31 +#define HWIO_UMCMN_R0_TRC_CTRL_2_SUB_SYS_TESTBUS_SEL_BMSK 0x70000000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_SUB_SYS_TESTBUS_SEL_SHFT 28 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_BIT_1_BMSK 0xff00000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_BIT_1_SHFT 20 +#define HWIO_UMCMN_R0_TRC_CTRL_2_UMAC_MISC_TRC_EVENT_SEL_BMSK 0x80000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_UMAC_MISC_TRC_EVENT_SEL_SHFT 19 +#define HWIO_UMCMN_R0_TRC_CTRL_2_TRC_BUS_MUX_SEL_BMSK 0x78000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_TRC_BUS_MUX_SEL_SHFT 15 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK 0x4000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT 14 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK 0x2000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT 13 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK 0x1000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT 12 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK 0x800 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT 11 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK 0x400 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT 10 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK 0x200 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT 9 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK 0x100 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT 8 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK 0x80 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT 7 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK 0x40 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT 6 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK 0x20 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT 5 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK 0x10 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT 4 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK 0x8 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT 3 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK 0x4 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT 2 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK 0x2 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT 1 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK 0x1 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT 0 + +#define HWIO_UMCMN_R0_EVENTMASK_IX0_ADDR(x) ((x) + 0x17c) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_PHYS(x) ((x) + 0x17c) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_OFFS (0x17c) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_RMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENTMASK_IX0_POR 0x00000000 +#define HWIO_UMCMN_R0_EVENTMASK_IX0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENTMASK_IX0_ATTR 0x3 +#define HWIO_UMCMN_R0_EVENTMASK_IX0_IN(x) \ + in_dword(HWIO_UMCMN_R0_EVENTMASK_IX0_ADDR(x)) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_EVENTMASK_IX0_ADDR(x), m) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_EVENTMASK_IX0_ADDR(x),v) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_EVENTMASK_IX0_ADDR(x),m,v,HWIO_UMCMN_R0_EVENTMASK_IX0_IN(x)) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_VALUE_BMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENTMASK_IX0_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_EVENTMASK_IX1_ADDR(x) ((x) + 0x180) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_PHYS(x) ((x) + 0x180) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_OFFS (0x180) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_RMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENTMASK_IX1_POR 0x00000000 +#define HWIO_UMCMN_R0_EVENTMASK_IX1_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENTMASK_IX1_ATTR 0x3 +#define HWIO_UMCMN_R0_EVENTMASK_IX1_IN(x) \ + in_dword(HWIO_UMCMN_R0_EVENTMASK_IX1_ADDR(x)) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_EVENTMASK_IX1_ADDR(x), m) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_EVENTMASK_IX1_ADDR(x),v) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_EVENTMASK_IX1_ADDR(x),m,v,HWIO_UMCMN_R0_EVENTMASK_IX1_IN(x)) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_VALUE_BMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENTMASK_IX1_VALUE_SHFT 0 + +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_ADDR(x) ((x) + 0x2000) +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_PHYS(x) ((x) + 0x2000) +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_OFFS (0x2000) +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_RMSK 0xfff +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_POR 0x00000000 +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_ATTR 0x1 +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword(HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_ADDR(x)) +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_ADDR(x), m) +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_VALUE_BMSK 0xfff +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_VALUE_SHFT 0 + +#define HWIO_UMCMN_R1_UMAC_IDLE_ADDR(x) ((x) + 0x2004) +#define HWIO_UMCMN_R1_UMAC_IDLE_PHYS(x) ((x) + 0x2004) +#define HWIO_UMCMN_R1_UMAC_IDLE_OFFS (0x2004) +#define HWIO_UMCMN_R1_UMAC_IDLE_RMSK 0x1f +#define HWIO_UMCMN_R1_UMAC_IDLE_POR 0x00000000 +#define HWIO_UMCMN_R1_UMAC_IDLE_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_UMAC_IDLE_ATTR 0x1 +#define HWIO_UMCMN_R1_UMAC_IDLE_IN(x) \ + in_dword(HWIO_UMCMN_R1_UMAC_IDLE_ADDR(x)) +#define HWIO_UMCMN_R1_UMAC_IDLE_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R1_UMAC_IDLE_ADDR(x), m) +#define HWIO_UMCMN_R1_UMAC_IDLE_UMAC_IDLE_GEN_MOD_BUSY_BMSK 0x10 +#define HWIO_UMCMN_R1_UMAC_IDLE_UMAC_IDLE_GEN_MOD_BUSY_SHFT 4 +#define HWIO_UMCMN_R1_UMAC_IDLE_MAIN_SM_CS_BMSK 0xf +#define HWIO_UMCMN_R1_UMAC_IDLE_MAIN_SM_CS_SHFT 0 + +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_ADDR(x) ((x) + 0x2008) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_PHYS(x) ((x) + 0x2008) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_OFFS (0x2008) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_RMSK 0xffffff +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_POR 0x00000000 +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_ATTR 0x1 +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_IN(x) \ + in_dword(HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_ADDR(x)) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_ADDR(x), m) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_VALUE_BMSK 0xffffff +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_VALUE_SHFT 0 + +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_ADDR(x) ((x) + 0x200c) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_PHYS(x) ((x) + 0x200c) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_OFFS (0x200c) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_RMSK 0x7df +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_POR 0x00000000 +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_ATTR 0x3 +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_IN(x) \ + in_dword(HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_ADDR(x)) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_ADDR(x), m) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_OUT(x, v) \ + out_dword(HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_ADDR(x),v) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_ADDR(x),m,v,HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_IN(x)) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_IDLE_ERR_STATUS_SW_WDATA_BMSK 0x7c0 +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_IDLE_ERR_STATUS_SW_WDATA_SHFT 6 +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_STATUS_BMSK 0x1f +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_STATUS_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: MAC_TCL_REG + *--------------------------------------------------------------------------*/ + +#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) +#define MAC_TCL_REG_REG_BASE_SIZE 0x3000 +#define MAC_TCL_REG_REG_BASE_USED 0x205c +#define MAC_TCL_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00044000) +#define MAC_TCL_REG_REG_BASE_OFFS 0x00044000 + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) ((x) + 0x0) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) ((x) + 0x0) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OFFS (0x0) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) ((x) + 0x4) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) ((x) + 0x4) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OFFS (0x4) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) ((x) + 0x8) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) ((x) + 0x8) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OFFS (0x8) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x) ((x) + 0xc) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_PHYS(x) ((x) + 0xc) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_OFFS (0xc) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) ((x) + 0x14) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) ((x) + 0x14) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OFFS (0x14) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x) ((x) + 0x18) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_PHYS(x) ((x) + 0x18) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OFFS (0x18) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_ADDR(x) ((x) + 0x1c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_PHYS(x) ((x) + 0x1c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_OFFS (0x1c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) ((x) + 0x20) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OFFS (0x20) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0xfff7f7f +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_POR 0x0b700000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ATTR 0x3 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ + in_dword(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x)) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), m) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x),v) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x),m,v,HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE_RING_EN_BMSK 0x8000000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE_RING_EN_SHFT 27 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_VLAN_LLC_SEL_BMSK 0x4000000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_VLAN_LLC_SEL_SHFT 26 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_BMSK 0x2000000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_SHFT 25 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_BMSK 0x1000000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_SHFT 24 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_BMSK 0x700000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_SHFT 20 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_BMSK 0x80000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_SHFT 19 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_BMSK 0x40000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_SHFT 18 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_STAT_BMSK 0x20000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_STAT_SHFT 17 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_BMSK 0x10000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_SHFT 16 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL4_RNG_HALT_STAT_BMSK 0x4000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL4_RNG_HALT_STAT_SHFT 14 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_BMSK 0x2000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_SHFT 13 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_BMSK 0x1000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_SHFT 12 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_BMSK 0x800 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_SHFT 11 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_BMSK 0x400 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT 10 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_BMSK 0x200 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_SHFT 9 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_BMSK 0x100 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_SHFT 8 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL4_RNG_HALT_BMSK 0x40 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL4_RNG_HALT_SHFT 6 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_BMSK 0x20 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_SHFT 5 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_BMSK 0x10 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_SHFT 4 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_BMSK 0x8 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_SHFT 3 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x4 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 2 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK 0x2 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT 1 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK 0x1 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT 0 + +#define HWIO_TCL_R0_CMN_CONFIG_ADDR(x) ((x) + 0x24) +#define HWIO_TCL_R0_CMN_CONFIG_PHYS(x) ((x) + 0x24) +#define HWIO_TCL_R0_CMN_CONFIG_OFFS (0x24) +#define HWIO_TCL_R0_CMN_CONFIG_RMSK 0xfffffff +#define HWIO_TCL_R0_CMN_CONFIG_POR 0x067993a2 +#define HWIO_TCL_R0_CMN_CONFIG_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CMN_CONFIG_ATTR 0x3 +#define HWIO_TCL_R0_CMN_CONFIG_IN(x) \ + in_dword(HWIO_TCL_R0_CMN_CONFIG_ADDR(x)) +#define HWIO_TCL_R0_CMN_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CMN_CONFIG_ADDR(x), m) +#define HWIO_TCL_R0_CMN_CONFIG_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CMN_CONFIG_ADDR(x),v) +#define HWIO_TCL_R0_CMN_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CMN_CONFIG_ADDR(x),m,v,HWIO_TCL_R0_CMN_CONFIG_IN(x)) +#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK 0x8000000 +#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT 27 +#define HWIO_TCL_R0_CMN_CONFIG_CLFY_DIS_INVALID_PPE_DESC_BMSK 0x4000000 +#define HWIO_TCL_R0_CMN_CONFIG_CLFY_DIS_INVALID_PPE_DESC_SHFT 26 +#define HWIO_TCL_R0_CMN_CONFIG_CLFY_DIS_INVALID_BANK_ID_BMSK 0x2000000 +#define HWIO_TCL_R0_CMN_CONFIG_CLFY_DIS_INVALID_BANK_ID_SHFT 25 +#define HWIO_TCL_R0_CMN_CONFIG_CLFY_DIS_MIN_BUFFER_LEN_ERR_BMSK 0x1000000 +#define HWIO_TCL_R0_CMN_CONFIG_CLFY_DIS_MIN_BUFFER_LEN_ERR_SHFT 24 +#define HWIO_TCL_R0_CMN_CONFIG_ASE_SKIP_SEARCH_EN_BMSK 0x800000 +#define HWIO_TCL_R0_CMN_CONFIG_ASE_SKIP_SEARCH_EN_SHFT 23 +#define HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK 0x400000 +#define HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT 22 +#define HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK 0x200000 +#define HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT 21 +#define HWIO_TCL_R0_CMN_CONFIG_FLOW_POINTER_NULL_EXCEPTION_BMSK 0x100000 +#define HWIO_TCL_R0_CMN_CONFIG_FLOW_POINTER_NULL_EXCEPTION_SHFT 20 +#define HWIO_TCL_R0_CMN_CONFIG_FLOW_OVERRIDE_EXCEPTION_BMSK 0x80000 +#define HWIO_TCL_R0_CMN_CONFIG_FLOW_OVERRIDE_EXCEPTION_SHFT 19 +#define HWIO_TCL_R0_CMN_CONFIG_TX_NOTIFY_PRIORITY_BMSK 0x40000 +#define HWIO_TCL_R0_CMN_CONFIG_TX_NOTIFY_PRIORITY_SHFT 18 +#define HWIO_TCL_R0_CMN_CONFIG_PMAC_ID_SEL_BMSK 0x20000 +#define HWIO_TCL_R0_CMN_CONFIG_PMAC_ID_SEL_SHFT 17 +#define HWIO_TCL_R0_CMN_CONFIG_C9D1_8870_VALUE_BMSK 0x1fffe +#define HWIO_TCL_R0_CMN_CONFIG_C9D1_8870_VALUE_SHFT 1 +#define HWIO_TCL_R0_CMN_CONFIG_ENABLE_C9D1_8870_BMSK 0x1 +#define HWIO_TCL_R0_CMN_CONFIG_ENABLE_C9D1_8870_SHFT 0 + +#define HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x) ((x) + 0x28) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PHYS(x) ((x) + 0x28) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_OFFS (0x28) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_RMSK 0x7fffffff +#define HWIO_TCL_R0_CMN_CONFIG_PPE_POR 0x120c3fe8 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CMN_CONFIG_PPE_ATTR 0x3 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_IN(x) \ + in_dword(HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x)) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x), m) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x),v) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x),m,v,HWIO_TCL_R0_CMN_CONFIG_PPE_IN(x)) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PPE_MAX_DATA_LENGTH_BMSK 0x7ffe0000 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PPE_MAX_DATA_LENGTH_SHFT 17 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PPE_MAX_DATA_OFFSET_BMSK 0x1ffe0 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PPE_MAX_DATA_OFFSET_SHFT 5 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK 0x10 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT 4 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_DATA_BUF_ERR_EXCEPTION_BMSK 0x8 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_DATA_BUF_ERR_EXCEPTION_SHFT 3 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK 0x4 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT 2 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK 0x2 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT 1 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK 0x1 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x) ((x) + 0x2c) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x) ((x) + 0x2c) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OFFS (0x2c) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK 0xffff +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_DROP_NO_DROP_PRIORITY_BMSK 0xc000 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_DROP_NO_DROP_PRIORITY_SHFT 14 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_BMSK 0x2000 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_SHFT 13 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_BMSK 0x1000 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_SHFT 12 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0xfff +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x) ((x) + 0x30) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x) ((x) + 0x30) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OFFS (0x30) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK 0xfff +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0xfff +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x) ((x) + 0x34) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x) ((x) + 0x34) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OFFS (0x34) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK 0xfff +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0xfff +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0 + +#define HWIO_TCL_R0_GEN_CTRL_ADDR(x) ((x) + 0x3c) +#define HWIO_TCL_R0_GEN_CTRL_PHYS(x) ((x) + 0x3c) +#define HWIO_TCL_R0_GEN_CTRL_OFFS (0x3c) +#define HWIO_TCL_R0_GEN_CTRL_RMSK 0xffffe1fb +#define HWIO_TCL_R0_GEN_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_GEN_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_GEN_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_GEN_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_GEN_CTRL_ADDR(x)) +#define HWIO_TCL_R0_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_GEN_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_GEN_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x),m,v,HWIO_TCL_R0_GEN_CTRL_IN(x)) +#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000 +#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 16 +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_BMSK 0x8000 +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_SHFT 15 +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK 0x4000 +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT 14 +#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK 0x2000 +#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT 13 +#define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_BMSK 0x100 +#define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_SHFT 8 +#define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_BMSK 0x80 +#define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_SHFT 7 +#define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_BMSK 0x40 +#define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_SHFT 6 +#define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_BMSK 0x20 +#define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_SHFT 5 +#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x10 +#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 4 +#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK 0x8 +#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT 3 +#define HWIO_TCL_R0_GEN_CTRL_TO_FW_BMSK 0x2 +#define HWIO_TCL_R0_GEN_CTRL_TO_FW_SHFT 1 +#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK 0x1 +#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT 0 + +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n) ((base) + 0X40 + (0x4*(n))) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_PHYS(base,n) ((base) + 0X40 + (0x4*(n))) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_OFFS(n) (0X40 + (0x4*(n))) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_MAXn 1 +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_POR 0x005a0060 +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_ATTR 0x3 +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n), HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_RMSK) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n),val) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n),mask,val,HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_INI(base,n)) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_NATIVE_WIFI_BMSK 0xffff0000 +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_NATIVE_WIFI_SHFT 16 +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_RAW_WIFI_BMSK 0xffff +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_RAW_WIFI_SHFT 0 + +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n) ((base) + 0X48 + (0x4*(n))) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_PHYS(base,n) ((base) + 0X48 + (0x4*(n))) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_OFFS(n) (0X48 + (0x4*(n))) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_MAXn 1 +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_POR 0x004a004a +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ATTR 0x3 +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n), HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_RMSK) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n),val) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n),mask,val,HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_INI(base,n)) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_IEEE_802_BMSK 0xffff0000 +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_IEEE_802_SHFT 16 +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ETHERNET_II_BMSK 0xffff +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ETHERNET_II_SHFT 0 + +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_ADDR(x) ((x) + 0x50) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_PHYS(x) ((x) + 0x50) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_OFFS (0x50) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_POR 0x00300036 +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_ATTR 0x3 +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_IN(x) \ + in_dword(HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_ADDR(x)) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_ADDR(x), m) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_ADDR(x),v) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_ADDR(x),m,v,HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_IN(x)) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_NATIVE_WIFI_BMSK 0xffff0000 +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_NATIVE_WIFI_SHFT 16 +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_RAW_WIFI_BMSK 0xffff +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_RAW_WIFI_SHFT 0 + +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ADDR(x) ((x) + 0x54) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_PHYS(x) ((x) + 0x54) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_OFFS (0x54) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_POR 0x001a001a +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ATTR 0x3 +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_IN(x) \ + in_dword(HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ADDR(x)) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ADDR(x), m) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ADDR(x),v) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ADDR(x),m,v,HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_IN(x)) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_IEEE_802_BMSK 0xffff0000 +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_IEEE_802_SHFT 16 +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ETHERNET_II_BMSK 0xffff +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ETHERNET_II_SHFT 0 + +#define HWIO_TCL_R0_UMXI_PRIORITY0_ADDR(x) ((x) + 0x58) +#define HWIO_TCL_R0_UMXI_PRIORITY0_PHYS(x) ((x) + 0x58) +#define HWIO_TCL_R0_UMXI_PRIORITY0_OFFS (0x58) +#define HWIO_TCL_R0_UMXI_PRIORITY0_RMSK 0xff3ffcff +#define HWIO_TCL_R0_UMXI_PRIORITY0_POR 0x55000000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_UMXI_PRIORITY0_ATTR 0x3 +#define HWIO_TCL_R0_UMXI_PRIORITY0_IN(x) \ + in_dword(HWIO_TCL_R0_UMXI_PRIORITY0_ADDR(x)) +#define HWIO_TCL_R0_UMXI_PRIORITY0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_UMXI_PRIORITY0_ADDR(x), m) +#define HWIO_TCL_R0_UMXI_PRIORITY0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_UMXI_PRIORITY0_ADDR(x),v) +#define HWIO_TCL_R0_UMXI_PRIORITY0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_UMXI_PRIORITY0_ADDR(x),m,v,HWIO_TCL_R0_UMXI_PRIORITY0_IN(x)) +#define HWIO_TCL_R0_UMXI_PRIORITY0_METADATA_FETCH_GXI_RD_BMSK 0xc0000000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_METADATA_FETCH_GXI_RD_SHFT 30 +#define HWIO_TCL_R0_UMXI_PRIORITY0_PEER_TABLE_FETCH_GXI_RD_BMSK 0x30000000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_PEER_TABLE_FETCH_GXI_RD_SHFT 28 +#define HWIO_TCL_R0_UMXI_PRIORITY0_DATA_FETCH_GXI_RD_BMSK 0xc000000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_DATA_FETCH_GXI_RD_SHFT 26 +#define HWIO_TCL_R0_UMXI_PRIORITY0_EXTN_DESC_GXI_RD_BMSK 0x3000000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_EXTN_DESC_GXI_RD_SHFT 24 +#define HWIO_TCL_R0_UMXI_PRIORITY0_TCL_STATUS1_RING_BMSK 0x300000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_TCL_STATUS1_RING_SHFT 20 +#define HWIO_TCL_R0_UMXI_PRIORITY0_TCL2FW_RING_BMSK 0xc0000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_TCL2FW_RING_SHFT 18 +#define HWIO_TCL_R0_UMXI_PRIORITY0_TCL2TQM_RING_BMSK 0x30000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_TCL2TQM_RING_SHFT 16 +#define HWIO_TCL_R0_UMXI_PRIORITY0_PPE2TCL1_RING_BMSK 0xc000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_PPE2TCL1_RING_SHFT 14 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL_CREDIT_RING_BMSK 0x3000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL_CREDIT_RING_SHFT 12 +#define HWIO_TCL_R0_UMXI_PRIORITY0_FW2TCL_RING_BMSK 0xc00 +#define HWIO_TCL_R0_UMXI_PRIORITY0_FW2TCL_RING_SHFT 10 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL4_RING_BMSK 0xc0 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL4_RING_SHFT 6 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL3_RING_BMSK 0x30 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL3_RING_SHFT 4 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL2_RING_BMSK 0xc +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL2_RING_SHFT 2 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL1_RING_BMSK 0x3 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL1_RING_SHFT 0 + +#define HWIO_TCL_R0_UMXI_PRIORITY1_ADDR(x) ((x) + 0x5c) +#define HWIO_TCL_R0_UMXI_PRIORITY1_PHYS(x) ((x) + 0x5c) +#define HWIO_TCL_R0_UMXI_PRIORITY1_OFFS (0x5c) +#define HWIO_TCL_R0_UMXI_PRIORITY1_RMSK 0xf +#define HWIO_TCL_R0_UMXI_PRIORITY1_POR 0x00000005 +#define HWIO_TCL_R0_UMXI_PRIORITY1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_UMXI_PRIORITY1_ATTR 0x3 +#define HWIO_TCL_R0_UMXI_PRIORITY1_IN(x) \ + in_dword(HWIO_TCL_R0_UMXI_PRIORITY1_ADDR(x)) +#define HWIO_TCL_R0_UMXI_PRIORITY1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_UMXI_PRIORITY1_ADDR(x), m) +#define HWIO_TCL_R0_UMXI_PRIORITY1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_UMXI_PRIORITY1_ADDR(x),v) +#define HWIO_TCL_R0_UMXI_PRIORITY1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_UMXI_PRIORITY1_ADDR(x),m,v,HWIO_TCL_R0_UMXI_PRIORITY1_IN(x)) +#define HWIO_TCL_R0_UMXI_PRIORITY1_ASE_STAT_GXI_WR_BMSK 0xc +#define HWIO_TCL_R0_UMXI_PRIORITY1_ASE_STAT_GXI_WR_SHFT 2 +#define HWIO_TCL_R0_UMXI_PRIORITY1_ASE_LOOKUP_GXI_RD_BMSK 0x3 +#define HWIO_TCL_R0_UMXI_PRIORITY1_ASE_LOOKUP_GXI_RD_SHFT 0 + +#define HWIO_TCL_R0_VC_ID_MAP_ADDR(x) ((x) + 0x60) +#define HWIO_TCL_R0_VC_ID_MAP_PHYS(x) ((x) + 0x60) +#define HWIO_TCL_R0_VC_ID_MAP_OFFS (0x60) +#define HWIO_TCL_R0_VC_ID_MAP_RMSK 0xfef +#define HWIO_TCL_R0_VC_ID_MAP_POR 0x00000f00 +#define HWIO_TCL_R0_VC_ID_MAP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_VC_ID_MAP_ATTR 0x3 +#define HWIO_TCL_R0_VC_ID_MAP_IN(x) \ + in_dword(HWIO_TCL_R0_VC_ID_MAP_ADDR(x)) +#define HWIO_TCL_R0_VC_ID_MAP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_VC_ID_MAP_ADDR(x), m) +#define HWIO_TCL_R0_VC_ID_MAP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_VC_ID_MAP_ADDR(x),v) +#define HWIO_TCL_R0_VC_ID_MAP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_VC_ID_MAP_ADDR(x),m,v,HWIO_TCL_R0_VC_ID_MAP_IN(x)) +#define HWIO_TCL_R0_VC_ID_MAP_METADATA_FETCH_GXI_RD_BMSK 0x800 +#define HWIO_TCL_R0_VC_ID_MAP_METADATA_FETCH_GXI_RD_SHFT 11 +#define HWIO_TCL_R0_VC_ID_MAP_PEER_TABLE_FETCH_GXI_RD_BMSK 0x400 +#define HWIO_TCL_R0_VC_ID_MAP_PEER_TABLE_FETCH_GXI_RD_SHFT 10 +#define HWIO_TCL_R0_VC_ID_MAP_DATA_FETCH_GXI_RD_BMSK 0x200 +#define HWIO_TCL_R0_VC_ID_MAP_DATA_FETCH_GXI_RD_SHFT 9 +#define HWIO_TCL_R0_VC_ID_MAP_EXTN_DESC_GXI_RD_BMSK 0x100 +#define HWIO_TCL_R0_VC_ID_MAP_EXTN_DESC_GXI_RD_SHFT 8 +#define HWIO_TCL_R0_VC_ID_MAP_PPE2TCL1_RING_BMSK 0x80 +#define HWIO_TCL_R0_VC_ID_MAP_PPE2TCL1_RING_SHFT 7 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL_CREDIT_RING_BMSK 0x40 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL_CREDIT_RING_SHFT 6 +#define HWIO_TCL_R0_VC_ID_MAP_FW2TCL_RING_BMSK 0x20 +#define HWIO_TCL_R0_VC_ID_MAP_FW2TCL_RING_SHFT 5 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL4_RING_BMSK 0x8 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL4_RING_SHFT 3 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL3_RING_BMSK 0x4 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL3_RING_SHFT 2 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL2_RING_BMSK 0x2 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL2_RING_SHFT 1 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL1_RING_BMSK 0x1 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL1_RING_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_ADDR(x) ((x) + 0x68) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_PHYS(x) ((x) + 0x68) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_OFFS (0x68) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_DESC_RD_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_ADDR(x) ((x) + 0x6c) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_PHYS(x) ((x) + 0x6c) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_OFFS (0x6c) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_DESC_RD_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_ADDR(x) ((x) + 0x70) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_PHYS(x) ((x) + 0x70) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_OFFS (0x70) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_DESC_RD_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_ADDR(x) ((x) + 0x74) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_PHYS(x) ((x) + 0x74) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_OFFS (0x74) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_DESC_RD_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL_DESC_RD_ADDR(x) ((x) + 0x7c) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_PHYS(x) ((x) + 0x7c) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_OFFS (0x7c) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_FW2TCL_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_FW2TCL_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL_DESC_RD_IN(x)) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_FW2TCL_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_FW2TCL_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_FW2TCL_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_ADDR(x) ((x) + 0x80) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_PHYS(x) ((x) + 0x80) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_OFFS (0x80) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_ADDR(x) ((x) + 0x84) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_PHYS(x) ((x) + 0x84) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_OFFS (0x84) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_DESC_RD_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_RBM_MAPPING0_ADDR(x) ((x) + 0x88) +#define HWIO_TCL_R0_RBM_MAPPING0_PHYS(x) ((x) + 0x88) +#define HWIO_TCL_R0_RBM_MAPPING0_OFFS (0x88) +#define HWIO_TCL_R0_RBM_MAPPING0_RMSK 0xfff0ffff +#define HWIO_TCL_R0_RBM_MAPPING0_POR 0x00000000 +#define HWIO_TCL_R0_RBM_MAPPING0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_RBM_MAPPING0_ATTR 0x3 +#define HWIO_TCL_R0_RBM_MAPPING0_IN(x) \ + in_dword(HWIO_TCL_R0_RBM_MAPPING0_ADDR(x)) +#define HWIO_TCL_R0_RBM_MAPPING0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_RBM_MAPPING0_ADDR(x), m) +#define HWIO_TCL_R0_RBM_MAPPING0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_RBM_MAPPING0_ADDR(x),v) +#define HWIO_TCL_R0_RBM_MAPPING0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_RBM_MAPPING0_ADDR(x),m,v,HWIO_TCL_R0_RBM_MAPPING0_IN(x)) +#define HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_BMSK 0xf0000000 +#define HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT 28 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_BMSK 0xf000000 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT 24 +#define HWIO_TCL_R0_RBM_MAPPING0_FW2TCL_RING_BMSK 0xf00000 +#define HWIO_TCL_R0_RBM_MAPPING0_FW2TCL_RING_SHFT 20 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL4_RING_BMSK 0xf000 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL4_RING_SHFT 12 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL3_RING_BMSK 0xf00 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL3_RING_SHFT 8 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_BMSK 0xf0 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT 4 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK 0xf +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_SHFT 0 + +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X8C + (0x4*(n))) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PHYS(base,n) ((base) + 0X8C + (0x4*(n))) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_OFFS(n) (0X8C + (0x4*(n))) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_RMSK 0x7fffff +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MAXn 23 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_POR 0x00000038 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ATTR 0x3 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n), HWIO_TCL_R0_SW_CONFIG_BANK_n_RMSK) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n),val) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n),mask,val,HWIO_TCL_R0_SW_CONFIG_BANK_n_INI(base,n)) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_BMSK 0x7e0000 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_BMSK 0x18000 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT 15 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_BMSK 0x4000 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_BMSK 0x3000 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_BMSK 0x800 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT 11 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_BMSK 0x400 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT 10 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_BMSK 0x200 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT 9 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_BMSK 0x100 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_BMSK 0x80 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_BMSK 0x78 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_BMSK 0x6 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_BMSK 0x1 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 + +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n) ((base) + 0X14C + (0x4*(n))) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_PHYS(base,n) ((base) + 0X14C + (0x4*(n))) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_OFFS(n) (0X14C + (0x4*(n))) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_RMSK 0xffffffff +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_MAXn 15 +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_POR 0x00000000 +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ATTR 0x3 +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n), HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_RMSK) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n),val) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n),mask,val,HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_INI(base,n)) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT 0 + +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_ADDR(x) ((x) + 0x18c) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_PHYS(x) ((x) + 0x18c) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_OFFS (0x18c) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_RMSK 0xffffffff +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_POR 0x00000064 +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_ATTR 0x3 +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_IN(x) \ + in_dword(HWIO_TCL_R0_MCAST_ECHO_CHECK_ADDR(x)) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MCAST_ECHO_CHECK_ADDR(x), m) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MCAST_ECHO_CHECK_ADDR(x),v) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MCAST_ECHO_CHECK_ADDR(x),m,v,HWIO_TCL_R0_MCAST_ECHO_CHECK_IN(x)) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_TIMESTAMP_AGEING_BMSK 0xffffffff +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_TIMESTAMP_AGEING_SHFT 0 + +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x) ((x) + 0x190) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_PHYS(x) ((x) + 0x190) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_OFFS (0x190) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_RMSK 0xf +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_POR 0x00000002 +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ATTR 0x3 +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_IN(x) \ + in_dword(HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x)) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x), m) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x),v) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x),m,v,HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_IN(x)) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_MSB_BMSK 0xf +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_MSB_SHFT 0 + +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n) ((base) + 0X194 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PHYS(base,n) ((base) + 0X194 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_OFFS(n) (0X194 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_RMSK 0x3fffffff +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_MAXn 31 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_POR 0x20000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ATTR 0x3 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n), HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_RMSK) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n),val) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n),mask,val,HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_INI(base,n)) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_BMSK 0x20000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_SHFT 29 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_BMSK 0x10000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_SHFT 28 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK 0x8000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT 27 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_BMSK 0x7000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_SHFT 24 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_BMSK 0xff0000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_SHFT 16 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_BMSK 0xfc00 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_SHFT 10 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_BMSK 0x300 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_SHFT 8 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_BMSK 0xff +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_SHFT 0 + +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n) ((base) + 0X214 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_PHYS(base,n) ((base) + 0X214 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_OFFS(n) (0X214 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_RMSK 0xffffff +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_MAXn 7 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_POR 0x00000000 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ATTR 0x3 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n), HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_RMSK) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n),val) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n),mask,val,HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_INI(base,n)) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_CACHE_SET_BMSK 0xf00000 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_CACHE_SET_SHFT 20 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_SEARCH_INDEX_BMSK 0xfffff +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_SEARCH_INDEX_SHFT 0 + +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x) ((x) + 0x234) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_PHYS(x) ((x) + 0x234) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_OFFS (0x234) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_RMSK 0x3fffffff +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_POR 0x00000000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ATTR 0x3 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_IN(x) \ + in_dword(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x)) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x), m) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x),v) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x),m,v,HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_IN(x)) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_9_BMSK 0x38000000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_9_SHFT 27 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_8_BMSK 0x7000000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_8_SHFT 24 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_7_BMSK 0xe00000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_7_SHFT 21 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_6_BMSK 0x1c0000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_6_SHFT 18 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_5_BMSK 0x38000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_5_SHFT 15 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_4_BMSK 0x7000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_4_SHFT 12 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_3_BMSK 0xe00 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_3_SHFT 9 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_2_BMSK 0x1c0 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_2_SHFT 6 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_1_BMSK 0x38 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_1_SHFT 3 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK 0x7 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT 0 + +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x) ((x) + 0x238) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_PHYS(x) ((x) + 0x238) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_OFFS (0x238) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_RMSK 0x3ffff +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_POR 0x00000000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ATTR 0x3 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_IN(x) \ + in_dword(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x)) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x), m) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x),v) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x),m,v,HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_IN(x)) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_15_BMSK 0x38000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_15_SHFT 15 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_14_BMSK 0x7000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_14_SHFT 12 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_13_BMSK 0xe00 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_13_SHFT 9 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_12_BMSK 0x1c0 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_12_SHFT 6 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_11_BMSK 0x38 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_11_SHFT 3 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK 0x7 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT 0 + +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x) ((x) + 0x23c) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_PHYS(x) ((x) + 0x23c) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_OFFS (0x23c) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_RMSK 0x3f +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_POR 0x00000039 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ATTR 0x3 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_IN(x) \ + in_dword(HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x)) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x), m) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x),v) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x),m,v,HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_IN(x)) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_RED_2_BMSK 0x30 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_RED_2_SHFT 4 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_YELLOW_1_BMSK 0xc +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_YELLOW_1_SHFT 2 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_GREEN_0_BMSK 0x3 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_GREEN_0_SHFT 0 + +#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X240 + (0x4*(n))) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_PHYS(base,n) ((base) + 0X240 + (0x4*(n))) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_OFFS(n) (0X240 + (0x4*(n))) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff +#define HWIO_TCL_R0_DSCP_TID_MAP_n_MAXn 143 +#define HWIO_TCL_R0_DSCP_TID_MAP_n_POR 0x00000000 +#define HWIO_TCL_R0_DSCP_TID_MAP_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_DSCP_TID_MAP_n_ATTR 0x3 +#define HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n), HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n),val) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n),mask,val,HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base,n)) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_SHFT 0 + +#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) ((x) + 0x6c0) +#define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) ((x) + 0x6c0) +#define HWIO_TCL_R0_PCP_TID_MAP_OFFS (0x6c0) +#define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0xffffff +#define HWIO_TCL_R0_PCP_TID_MAP_POR 0x00000000 +#define HWIO_TCL_R0_PCP_TID_MAP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PCP_TID_MAP_ATTR 0x3 +#define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ + in_dword(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x)) +#define HWIO_TCL_R0_PCP_TID_MAP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), m) +#define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x),v) +#define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x),m,v,HWIO_TCL_R0_PCP_TID_MAP_IN(x)) +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0xe00000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 21 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x1c0000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 18 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x38000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 15 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x7000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 12 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0xe00 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 9 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x1c0 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 6 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x38 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 3 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x7 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0 + +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x) ((x) + 0x6c4) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x) ((x) + 0x6c4) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OFFS (0x6c4) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_POR 0x00000000 +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ATTR 0x3 +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x)) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), m) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x),v) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x),m,v,HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0 + +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x) ((x) + 0x6c8) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x) ((x) + 0x6c8) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OFFS (0x6c8) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_POR 0x00000000 +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ATTR 0x3 +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x)) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), m) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x),v) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x),m,v,HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0 + +#define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x) ((x) + 0x6cc) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x) ((x) + 0x6cc) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_OFFS (0x6cc) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK 0x1 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_POR 0x00000000 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_64_ATTR 0x3 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x)) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), m) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x),v) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x),m,v,HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x1 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0 + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x) ((x) + 0x6d0) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x) ((x) + 0x6d0) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OFFS (0x6d0) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK 0xfffdfc +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_POR 0x00840014 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ATTR 0x3 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \ + in_dword(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x)) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), m) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x),v) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x),m,v,HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_BMSK 0x800000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_SHFT 23 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_BMSK 0x700000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_SHFT 20 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_BMSK 0xe0000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_SHFT 17 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_BMSK 0x1c000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_SHFT 14 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x2000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 13 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK 0x1000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT 12 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK 0x800 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT 11 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK 0x400 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT 10 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK 0x1c0 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT 6 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK 0x30 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT 4 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK 0xc +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT 2 + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x) ((x) + 0x6d4) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x) ((x) + 0x6d4) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OFFS (0x6d4) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_POR 0x00000000 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ATTR 0x3 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \ + in_dword(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x)) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), m) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x),v) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x),m,v,HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0 + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x) ((x) + 0x6d8) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x) ((x) + 0x6d8) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OFFS (0x6d8) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK 0xff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_POR 0x00000000 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ATTR 0x3 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \ + in_dword(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x)) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), m) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x),v) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x),m,v,HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0xff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0 + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x) ((x) + 0x6dc) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x) ((x) + 0x6dc) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OFFS (0x6dc) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_POR 0x00000000 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ATTR 0x3 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \ + in_dword(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x)) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), m) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x),v) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x),m,v,HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0 + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x) ((x) + 0x6e0) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x) ((x) + 0x6e0) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OFFS (0x6e0) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK 0xff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_POR 0x00000000 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ATTR 0x3 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \ + in_dword(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x)) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), m) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x),v) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x),m,v,HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0xff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0 + +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x) ((x) + 0x6e4) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x) ((x) + 0x6e4) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OFFS (0x6e4) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK 0xffffffff +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_POR 0x00000000 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ATTR 0x3 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \ + in_dword(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x)) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), m) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x),v) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x),m,v,HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 16 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK 0xffff +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT 0 + +#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) ((x) + 0x6e8) +#define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) ((x) + 0x6e8) +#define HWIO_TCL_R0_TID_MAP_PRTY_OFFS (0x6e8) +#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0xef +#define HWIO_TCL_R0_TID_MAP_PRTY_POR 0x00000000 +#define HWIO_TCL_R0_TID_MAP_PRTY_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TID_MAP_PRTY_ATTR 0x3 +#define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ + in_dword(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x)) +#define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), m) +#define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x),v) +#define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x),m,v,HWIO_TCL_R0_TID_MAP_PRTY_IN(x)) +#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0xe0 +#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 5 +#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0xf +#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0 + +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x) ((x) + 0x6ec) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x) ((x) + 0x6ec) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OFFS (0x6ec) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK 0xffffffff +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_POR 0x00000000 +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ATTR 0x1 +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x)) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), m) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0 + +#define HWIO_TCL_R0_WATCHDOG_WARNING_ADDR(x) ((x) + 0x6f0) +#define HWIO_TCL_R0_WATCHDOG_WARNING_PHYS(x) ((x) + 0x6f0) +#define HWIO_TCL_R0_WATCHDOG_WARNING_OFFS (0x6f0) +#define HWIO_TCL_R0_WATCHDOG_WARNING_RMSK 0xffffffff +#define HWIO_TCL_R0_WATCHDOG_WARNING_POR 0x0000ffff +#define HWIO_TCL_R0_WATCHDOG_WARNING_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_WATCHDOG_WARNING_ATTR 0x3 +#define HWIO_TCL_R0_WATCHDOG_WARNING_IN(x) \ + in_dword(HWIO_TCL_R0_WATCHDOG_WARNING_ADDR(x)) +#define HWIO_TCL_R0_WATCHDOG_WARNING_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_WATCHDOG_WARNING_ADDR(x), m) +#define HWIO_TCL_R0_WATCHDOG_WARNING_OUT(x, v) \ + out_dword(HWIO_TCL_R0_WATCHDOG_WARNING_ADDR(x),v) +#define HWIO_TCL_R0_WATCHDOG_WARNING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_WARNING_ADDR(x),m,v,HWIO_TCL_R0_WATCHDOG_WARNING_IN(x)) +#define HWIO_TCL_R0_WATCHDOG_WARNING_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_WATCHDOG_WARNING_STATUS_SHFT 16 +#define HWIO_TCL_R0_WATCHDOG_WARNING_LIMIT_BMSK 0xffff +#define HWIO_TCL_R0_WATCHDOG_WARNING_LIMIT_SHFT 0 + +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_ADDR(x) ((x) + 0x6f4) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_PHYS(x) ((x) + 0x6f4) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_OFFS (0x6f4) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_RMSK 0xffffffff +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_POR 0x0000ffff +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_ATTR 0x3 +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_IN(x) \ + in_dword(HWIO_TCL_R0_WATCHDOG_HW_ERROR_ADDR(x)) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_WATCHDOG_HW_ERROR_ADDR(x), m) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_OUT(x, v) \ + out_dword(HWIO_TCL_R0_WATCHDOG_HW_ERROR_ADDR(x),v) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_HW_ERROR_ADDR(x),m,v,HWIO_TCL_R0_WATCHDOG_HW_ERROR_IN(x)) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_STATUS_SHFT 16 +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_LIMIT_BMSK 0xffff +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_LIMIT_SHFT 0 + +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_ADDR(x) ((x) + 0x6f8) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_PHYS(x) ((x) + 0x6f8) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_OFFS (0x6f8) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_RMSK 0xffff +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_POR 0x0000000a +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_ADDR(x)) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_ADDR(x),m,v,HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_IN(x)) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_STATUS_BMSK 0xff00 +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_STATUS_SHFT 8 +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_LIMIT_BMSK 0xff +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_LIMIT_SHFT 0 + +#define HWIO_TCL_R0_LCE_RULE_n_ADDR(base,n) ((base) + 0X6FC + (0x4*(n))) +#define HWIO_TCL_R0_LCE_RULE_n_PHYS(base,n) ((base) + 0X6FC + (0x4*(n))) +#define HWIO_TCL_R0_LCE_RULE_n_OFFS(n) (0X6FC + (0x4*(n))) +#define HWIO_TCL_R0_LCE_RULE_n_RMSK 0xffffff +#define HWIO_TCL_R0_LCE_RULE_n_MAXn 26 +#define HWIO_TCL_R0_LCE_RULE_n_POR 0x00000000 +#define HWIO_TCL_R0_LCE_RULE_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_LCE_RULE_n_ATTR 0x3 +#define HWIO_TCL_R0_LCE_RULE_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_LCE_RULE_n_ADDR(base,n), HWIO_TCL_R0_LCE_RULE_n_RMSK) +#define HWIO_TCL_R0_LCE_RULE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_LCE_RULE_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_LCE_RULE_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_LCE_RULE_n_ADDR(base,n),val) +#define HWIO_TCL_R0_LCE_RULE_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_LCE_RULE_n_ADDR(base,n),mask,val,HWIO_TCL_R0_LCE_RULE_n_INI(base,n)) +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK 0x800000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT 23 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_IP_PROT_BMSK 0x400000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_IP_PROT_SHFT 22 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_ADDR_BIT_0_BMSK 0x200000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_ADDR_BIT_0_SHFT 21 +#define HWIO_TCL_R0_LCE_RULE_n_TCP_OR_UDP_BMSK 0x180000 +#define HWIO_TCL_R0_LCE_RULE_n_TCP_OR_UDP_SHFT 19 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_PORT_BMSK 0x40000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_PORT_SHFT 18 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_SRC_PORT_BMSK 0x20000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_SRC_PORT_SHFT 17 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_L3_TYPE_BMSK 0x10000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_L3_TYPE_SHFT 16 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_VAL_BMSK 0xffff +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_VAL_SHFT 0 + +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base,n) ((base) + 0X768 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_PHYS(base,n) ((base) + 0X768 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OFFS(n) (0X768 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_RMSK 0xffffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_MAXn 26 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_POR 0x00000000 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ATTR 0x3 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base,n), HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_RMSK) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base,n),val) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base,n),mask,val,HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INI(base,n)) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_VAL_SHFT 0 + +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base,n) ((base) + 0X7D4 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_PHYS(base,n) ((base) + 0X7D4 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OFFS(n) (0X7D4 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_RMSK 0xff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_MAXn 26 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_POR 0x00000000 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ATTR 0x3 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base,n), HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_RMSK) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base,n),val) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base,n),mask,val,HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INI(base,n)) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_VAL_BMSK 0xff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_VAL_SHFT 0 + +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base,n) ((base) + 0X840 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_PHYS(base,n) ((base) + 0X840 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OFFS(n) (0X840 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RMSK 0x3ffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MAXn 26 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_POR 0x00000000 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ATTR 0x3 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base,n), HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RMSK) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base,n),val) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base,n),mask,val,HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INI(base,n)) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TX_NOTIFY_FRAME_BMSK 0x3800000 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TX_NOTIFY_FRAME_SHFT 23 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_NO_DROP_BMSK 0x400000 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_NO_DROP_SHFT 22 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RULE_HIT_BMSK 0x200000 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RULE_HIT_SHFT 21 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_METADATA_BMSK 0x1fffe0 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_METADATA_SHFT 5 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MSDU_DROP_BMSK 0x10 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MSDU_DROP_SHFT 4 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TO_TQM_IF_M0_FW_BMSK 0x8 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TO_TQM_IF_M0_FW_SHFT 3 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_LOOP_HANDLER_BMSK 0x4 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_LOOP_HANDLER_SHFT 2 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_HANDLER_BMSK 0x3 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_HANDLER_SHFT 0 + +#define HWIO_TCL_R0_CLKGATE_DISABLE0_ADDR(x) ((x) + 0x8ac) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_PHYS(x) ((x) + 0x8ac) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_OFFS (0x8ac) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_RMSK 0xfffffeff +#define HWIO_TCL_R0_CLKGATE_DISABLE0_POR 0x00000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE0_ATTR 0x3 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_IN(x) \ + in_dword(HWIO_TCL_R0_CLKGATE_DISABLE0_ADDR(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE0_ADDR(x), m) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CLKGATE_DISABLE0_ADDR(x),v) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE0_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE0_IN(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TQM_SRNG_BUNCH_BMSK 0x80000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TQM_SRNG_BUNCH_SHFT 31 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_APB_CLK_BMSK 0x40000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_APB_CLK_SHFT 30 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_CLFY_RES_MEM_BMSK 0x20000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_CLFY_RES_MEM_SHFT 29 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_GSE_CTRL_BMSK 0x10000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_GSE_CTRL_SHFT 28 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_GSE_CCE_RES_BMSK 0x8000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_GSE_CCE_RES_SHFT 27 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2_STATUS2_PROD_RING_BMSK 0x4000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2_STATUS2_PROD_RING_SHFT 26 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2_STATUS1_PROD_RING_BMSK 0x2000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2_STATUS1_PROD_RING_SHFT 25 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2FW_PROD_RING_BMSK 0x1000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2FW_PROD_RING_SHFT 24 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2TQM_PROD_RING_BMSK 0x800000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2TQM_PROD_RING_SHFT 23 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_PROD_RING_CTRL_BMSK 0x400000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_PROD_RING_CTRL_SHFT 22 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TLV_DECODE_BMSK 0x200000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TLV_DECODE_SHFT 21 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TLV_GEN_BMSK 0x100000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TLV_GEN_SHFT 20 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DATA_FETCH_BMSK 0x80000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DATA_FETCH_SHFT 19 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DATA_BUF_BMSK 0x40000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DATA_BUF_SHFT 18 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DESC_BUF_BMSK 0x20000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DESC_BUF_SHFT 17 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DESC_RD_BMSK 0x10000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DESC_RD_SHFT 16 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_ASE_BMSK 0x8000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_ASE_SHFT 15 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_3_BMSK 0x4000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_3_SHFT 14 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_2_BMSK 0x2000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_2_SHFT 13 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_1_BMSK 0x1000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_1_SHFT 12 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_0_BMSK 0x800 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_0_SHFT 11 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_6_BMSK 0x400 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_6_SHFT 10 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_5_BMSK 0x200 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_5_SHFT 9 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_3_BMSK 0x80 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_3_SHFT 7 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_2_BMSK 0x40 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_2_SHFT 6 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_1_BMSK 0x20 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_1_SHFT 5 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_0_BMSK 0x10 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_0_SHFT 4 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL_IDLE_REQ_SM_BMSK 0x8 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL_IDLE_REQ_SM_SHFT 3 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_CCE_BMSK 0x4 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_CCE_SHFT 2 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_LCE_BMSK 0x2 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_LCE_SHFT 1 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_PARSER_BMSK 0x1 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_PARSER_SHFT 0 + +#define HWIO_TCL_R0_CLKGATE_DISABLE1_ADDR(x) ((x) + 0x8b0) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_PHYS(x) ((x) + 0x8b0) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_OFFS (0x8b0) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_RMSK 0x3f +#define HWIO_TCL_R0_CLKGATE_DISABLE1_POR 0x00000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE1_ATTR 0x3 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_IN(x) \ + in_dword(HWIO_TCL_R0_CLKGATE_DISABLE1_ADDR(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE1_ADDR(x), m) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CLKGATE_DISABLE1_ADDR(x),v) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE1_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE1_IN(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_CLK_ENS_EXTEND_BMSK 0x20 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_CLK_ENS_EXTEND_SHFT 5 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_CPU_IF_EXTEND_BMSK 0x10 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_CPU_IF_EXTEND_SHFT 4 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK 0x8 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT 3 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_ERR_RECOV_BMSK 0x4 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_ERR_RECOV_SHFT 2 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_SRNG_C_7_BMSK 0x2 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_SRNG_C_7_SHFT 1 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_FW_SRNG_BUNCH_BMSK 0x1 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_FW_SRNG_BUNCH_SHFT 0 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_ADDR(x) ((x) + 0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_PHYS(x) ((x) + 0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_OFFS (0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_RMSK 0x7ef +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_POR 0x00000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_IN(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_RING_ARB_BMSK 0x400 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_RING_ARB_SHFT 10 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_FIFO_BMSK 0x200 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_FIFO_SHFT 9 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_STR_CTRL_BMSK 0x100 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_STR_CTRL_SHFT 8 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING7_BMSK 0x80 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING7_SHFT 7 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING6_BMSK 0x40 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING6_SHFT 6 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING5_BMSK 0x20 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING5_SHFT 5 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING3_BMSK 0x8 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING3_SHFT 3 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING2_BMSK 0x4 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING2_SHFT 2 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING1_BMSK 0x2 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING1_SHFT 1 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING0_BMSK 0x1 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING0_SHFT 0 + +#define HWIO_TCL_R0_CREDIT_COUNT_ADDR(x) ((x) + 0x8b8) +#define HWIO_TCL_R0_CREDIT_COUNT_PHYS(x) ((x) + 0x8b8) +#define HWIO_TCL_R0_CREDIT_COUNT_OFFS (0x8b8) +#define HWIO_TCL_R0_CREDIT_COUNT_RMSK 0x1ffff +#define HWIO_TCL_R0_CREDIT_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_CREDIT_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CREDIT_COUNT_ATTR 0x3 +#define HWIO_TCL_R0_CREDIT_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_CREDIT_COUNT_ADDR(x)) +#define HWIO_TCL_R0_CREDIT_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_CREDIT_COUNT_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CREDIT_COUNT_ADDR(x),v) +#define HWIO_TCL_R0_CREDIT_COUNT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CREDIT_COUNT_ADDR(x),m,v,HWIO_TCL_R0_CREDIT_COUNT_IN(x)) +#define HWIO_TCL_R0_CREDIT_COUNT_ENABLE_BMSK 0x10000 +#define HWIO_TCL_R0_CREDIT_COUNT_ENABLE_SHFT 16 +#define HWIO_TCL_R0_CREDIT_COUNT_VAL_BMSK 0xffff +#define HWIO_TCL_R0_CREDIT_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x) ((x) + 0x8bc) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_PHYS(x) ((x) + 0x8bc) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_OFFS (0x8bc) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_RMSK 0xffff +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ATTR 0x1 +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x)) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_VAL_BMSK 0xffff +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_READ_ADDR(x) ((x) + 0x8c8) +#define HWIO_TCL_R0_ERR_RECOV_READ_PHYS(x) ((x) + 0x8c8) +#define HWIO_TCL_R0_ERR_RECOV_READ_OFFS (0x8c8) +#define HWIO_TCL_R0_ERR_RECOV_READ_RMSK 0x1 +#define HWIO_TCL_R0_ERR_RECOV_READ_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_READ_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_READ_ATTR 0x3 +#define HWIO_TCL_R0_ERR_RECOV_READ_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_READ_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_READ_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_READ_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_READ_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ERR_RECOV_READ_ADDR(x),v) +#define HWIO_TCL_R0_ERR_RECOV_READ_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ERR_RECOV_READ_ADDR(x),m,v,HWIO_TCL_R0_ERR_RECOV_READ_IN(x)) +#define HWIO_TCL_R0_ERR_RECOV_READ_ENABLE_BMSK 0x1 +#define HWIO_TCL_R0_ERR_RECOV_READ_ENABLE_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_ADDR(x) ((x) + 0x8cc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_PHYS(x) ((x) + 0x8cc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_OFFS (0x8cc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_RMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_VAL_BMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_ADDR(x) ((x) + 0x8d0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_PHYS(x) ((x) + 0x8d0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_OFFS (0x8d0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_RMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_VAL_BMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_ADDR(x) ((x) + 0x8d4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_PHYS(x) ((x) + 0x8d4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_OFFS (0x8d4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_RMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_VAL_BMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_ADDR(x) ((x) + 0x8d8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_PHYS(x) ((x) + 0x8d8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_OFFS (0x8d8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_RMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_VAL_BMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_ADDR(x) ((x) + 0x8dc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_PHYS(x) ((x) + 0x8dc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_OFFS (0x8dc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_RMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_VAL_BMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_ADDR(x) ((x) + 0x8e0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_PHYS(x) ((x) + 0x8e0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_OFFS (0x8e0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_ADDR(x) ((x) + 0x8e4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_PHYS(x) ((x) + 0x8e4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_OFFS (0x8e4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_ADDR(x) ((x) + 0x8e8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_PHYS(x) ((x) + 0x8e8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_OFFS (0x8e8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_ADDR(x) ((x) + 0x8ec) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_PHYS(x) ((x) + 0x8ec) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_OFFS (0x8ec) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_ADDR(x) ((x) + 0x8f0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_PHYS(x) ((x) + 0x8f0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_OFFS (0x8f0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_ADDR(x) ((x) + 0x8f4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_PHYS(x) ((x) + 0x8f4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_OFFS (0x8f4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_ADDR(x) ((x) + 0x8f8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_PHYS(x) ((x) + 0x8f8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_OFFS (0x8f8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_ADDR(x) ((x) + 0x8fc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_PHYS(x) ((x) + 0x8fc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_OFFS (0x8fc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_ADDR(x) ((x) + 0x900) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_PHYS(x) ((x) + 0x900) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_OFFS (0x900) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_ADDR(x) ((x) + 0x904) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_PHYS(x) ((x) + 0x904) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_OFFS (0x904) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x) ((x) + 0x908) +#define HWIO_TCL_R0_S_PARE_REGISTER_PHYS(x) ((x) + 0x908) +#define HWIO_TCL_R0_S_PARE_REGISTER_OFFS (0x908) +#define HWIO_TCL_R0_S_PARE_REGISTER_RMSK 0xffffffff +#define HWIO_TCL_R0_S_PARE_REGISTER_POR 0x00000000 +#define HWIO_TCL_R0_S_PARE_REGISTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_S_PARE_REGISTER_ATTR 0x3 +#define HWIO_TCL_R0_S_PARE_REGISTER_IN(x) \ + in_dword(HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x)) +#define HWIO_TCL_R0_S_PARE_REGISTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), m) +#define HWIO_TCL_R0_S_PARE_REGISTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x),v) +#define HWIO_TCL_R0_S_PARE_REGISTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x),m,v,HWIO_TCL_R0_S_PARE_REGISTER_IN(x)) +#define HWIO_TCL_R0_S_PARE_REGISTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_S_PARE_REGISTER_VAL_SHFT 0 + +#define HWIO_TCL_R0_MISC_CTRL_ADDR(x) ((x) + 0x90c) +#define HWIO_TCL_R0_MISC_CTRL_PHYS(x) ((x) + 0x90c) +#define HWIO_TCL_R0_MISC_CTRL_OFFS (0x90c) +#define HWIO_TCL_R0_MISC_CTRL_RMSK 0x3 +#define HWIO_TCL_R0_MISC_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_MISC_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MISC_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_MISC_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_MISC_CTRL_ADDR(x)) +#define HWIO_TCL_R0_MISC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MISC_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_MISC_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MISC_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_MISC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MISC_CTRL_ADDR(x),m,v,HWIO_TCL_R0_MISC_CTRL_IN(x)) +#define HWIO_TCL_R0_MISC_CTRL_DATA_CORRUPT_FIX_DISABLE_CHK_BIT_BMSK 0x2 +#define HWIO_TCL_R0_MISC_CTRL_DATA_CORRUPT_FIX_DISABLE_CHK_BIT_SHFT 1 +#define HWIO_TCL_R0_MISC_CTRL_MSI_DISABLE_CHK_BIT_BMSK 0x1 +#define HWIO_TCL_R0_MISC_CTRL_MSI_DISABLE_CHK_BIT_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x910) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) ((x) + 0x910) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OFFS (0x910) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x914) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) ((x) + 0x914) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OFFS (0x914) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x918) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) ((x) + 0x918) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OFFS (0x918) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) ((x) + 0x91c) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) ((x) + 0x91c) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OFFS (0x91c) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x920) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) ((x) + 0x920) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OFFS (0x920) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x92c) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x92c) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OFFS (0x92c) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x930) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x930) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OFFS (0x930) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x940) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x940) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x940) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x944) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x944) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x944) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x948) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x948) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OFFS (0x948) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x94c) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x94c) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x94c) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x950) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x950) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x950) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x954) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x954) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x954) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x958) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x958) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OFFS (0x958) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x95c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x95c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OFFS (0x95c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x960) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) ((x) + 0x960) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OFFS (0x960) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x980) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x980) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OFFS (0x980) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x) ((x) + 0x984) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_PHYS(x) ((x) + 0x984) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_OFFS (0x984) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x988) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) ((x) + 0x988) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OFFS (0x988) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) ((x) + 0x98c) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) ((x) + 0x98c) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OFFS (0x98c) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) ((x) + 0x990) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) ((x) + 0x990) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OFFS (0x990) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) ((x) + 0x994) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) ((x) + 0x994) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OFFS (0x994) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) ((x) + 0x998) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) ((x) + 0x998) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OFFS (0x998) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x9a4) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x9a4) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OFFS (0x9a4) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x9a8) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x9a8) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OFFS (0x9a8) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x9b8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x9b8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x9b8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x9bc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x9bc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x9bc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x9c0) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x9c0) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OFFS (0x9c0) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x9c4) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x9c4) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x9c4) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x9c8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x9c8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x9c8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x9cc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x9cc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x9cc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x9d0) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x9d0) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OFFS (0x9d0) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x9d4) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x9d4) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OFFS (0x9d4) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) ((x) + 0x9d8) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) ((x) + 0x9d8) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OFFS (0x9d8) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x9f8) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x9f8) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OFFS (0x9f8) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x) ((x) + 0x9fc) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_PHYS(x) ((x) + 0x9fc) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_OFFS (0x9fc) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) ((x) + 0xa00) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) ((x) + 0xa00) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OFFS (0xa00) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) ((x) + 0xa04) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) ((x) + 0xa04) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OFFS (0xa04) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) ((x) + 0xa08) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) ((x) + 0xa08) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OFFS (0xa08) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) ((x) + 0xa0c) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) ((x) + 0xa0c) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OFFS (0xa0c) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) ((x) + 0xa10) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) ((x) + 0xa10) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OFFS (0xa10) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xa1c) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xa1c) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OFFS (0xa1c) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xa20) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xa20) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OFFS (0xa20) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xa30) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xa30) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xa30) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xa34) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xa34) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xa34) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xa38) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xa38) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OFFS (0xa38) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xa3c) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xa3c) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xa3c) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xa40) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xa40) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xa40) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xa44) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xa44) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xa44) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa48) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa48) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OFFS (0xa48) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4c) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4c) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OFFS (0xa4c) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) ((x) + 0xa50) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) ((x) + 0xa50) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OFFS (0xa50) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa70) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa70) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OFFS (0xa70) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x) ((x) + 0xa74) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_PHYS(x) ((x) + 0xa74) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_OFFS (0xa74) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x) ((x) + 0xa78) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_PHYS(x) ((x) + 0xa78) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_OFFS (0xa78) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x) ((x) + 0xa7c) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_PHYS(x) ((x) + 0xa7c) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_OFFS (0xa7c) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x) ((x) + 0xa80) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_PHYS(x) ((x) + 0xa80) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_OFFS (0xa80) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_ADDR(x) ((x) + 0xa84) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_PHYS(x) ((x) + 0xa84) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_OFFS (0xa84) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x) ((x) + 0xa88) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_PHYS(x) ((x) + 0xa88) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_OFFS (0xa88) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xa94) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xa94) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_OFFS (0xa94) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xa98) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xa98) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_OFFS (0xa98) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xaa8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xaa8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xaa8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xaac) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xaac) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xaac) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xab0) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xab0) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_OFFS (0xab0) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xab4) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xab4) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xab4) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xab8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xab8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xab8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xabc) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xabc) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xabc) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xac0) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xac0) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_OFFS (0xac0) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xac4) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xac4) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_OFFS (0xac4) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x) ((x) + 0xac8) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_PHYS(x) ((x) + 0xac8) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_OFFS (0xac8) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xae8) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xae8) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_OFFS (0xae8) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x) ((x) + 0xaec) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_PHYS(x) ((x) + 0xaec) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_OFFS (0xaec) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) ((x) + 0xb68) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_PHYS(x) ((x) + 0xb68) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OFFS (0xb68) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x) ((x) + 0xb6c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_PHYS(x) ((x) + 0xb6c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OFFS (0xb6c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x) ((x) + 0xb70) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_PHYS(x) ((x) + 0xb70) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OFFS (0xb70) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x) ((x) + 0xb74) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_PHYS(x) ((x) + 0xb74) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_OFFS (0xb74) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x) ((x) + 0xb78) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_PHYS(x) ((x) + 0xb78) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OFFS (0xb78) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xb84) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xb84) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OFFS (0xb84) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xb88) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xb88) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OFFS (0xb88) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xb98) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xb98) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xb98) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xb9c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xb9c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xb9c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xba0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xba0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_OFFS (0xba0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xba4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xba4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xba4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xba8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xba8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xba8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xbac) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xbac) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xbac) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xbb0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xbb0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OFFS (0xbb0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xbb4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xbb4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OFFS (0xbb4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x) ((x) + 0xbb8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_PHYS(x) ((x) + 0xbb8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OFFS (0xbb8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xbd8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xbd8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OFFS (0xbd8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x) ((x) + 0xbdc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_PHYS(x) ((x) + 0xbdc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_OFFS (0xbdc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0xbe0) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) ((x) + 0xbe0) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OFFS (0xbe0) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0xbe4) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) ((x) + 0xbe4) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OFFS (0xbe4) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) ((x) + 0xbe8) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) ((x) + 0xbe8) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_OFFS (0xbe8) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) ((x) + 0xbec) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) ((x) + 0xbec) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OFFS (0xbec) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) ((x) + 0xbf0) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) ((x) + 0xbf0) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OFFS (0xbf0) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xbfc) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xbfc) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OFFS (0xbfc) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xc00) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xc00) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OFFS (0xc00) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xc10) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xc10) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xc10) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xc14) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xc14) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xc14) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xc18) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xc18) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OFFS (0xc18) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xc1c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xc1c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xc1c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xc20) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xc20) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xc20) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xc24) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xc24) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xc24) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xc28) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xc28) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OFFS (0xc28) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xc2c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xc2c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OFFS (0xc2c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0xc30) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) ((x) + 0xc30) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OFFS (0xc30) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xc50) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xc50) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OFFS (0xc50) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_ADDR(x) ((x) + 0xc54) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_PHYS(x) ((x) + 0xc54) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_OFFS (0xc54) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0xc58) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_PHYS(x) ((x) + 0xc58) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_OFFS (0xc58) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0xc5c) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_PHYS(x) ((x) + 0xc5c) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_OFFS (0xc5c) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x) ((x) + 0xc60) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_PHYS(x) ((x) + 0xc60) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_OFFS (0xc60) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_ID_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_ADDR(x) ((x) + 0xc64) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_PHYS(x) ((x) + 0xc64) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_OFFS (0xc64) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x) ((x) + 0xc68) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_PHYS(x) ((x) + 0xc68) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_OFFS (0xc68) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MISC_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xc74) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xc74) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_OFFS (0xc74) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xc78) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xc78) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_OFFS (0xc78) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xc88) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xc88) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xc88) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xc8c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xc8c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xc8c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xc90) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xc90) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_OFFS (0xc90) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xc94) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xc94) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xc94) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xc98) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xc98) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xc98) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xc9c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xc9c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xc9c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xca0) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xca0) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_OFFS (0xca0) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xca4) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xca4) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_OFFS (0xca4) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0xca8) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_PHYS(x) ((x) + 0xca8) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_OFFS (0xca8) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xcc8) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xcc8) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_OFFS (0xcc8) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x) ((x) + 0xccc) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_PHYS(x) ((x) + 0xccc) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_OFFS (0xccc) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) ((x) + 0xcd0) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) ((x) + 0xcd0) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OFFS (0xcd0) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) ((x) + 0xcd4) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) ((x) + 0xcd4) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OFFS (0xcd4) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) ((x) + 0xcd8) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) ((x) + 0xcd8) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_OFFS (0xcd8) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0xffff +#define HWIO_TCL_R0_TCL2TQM_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 8 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) ((x) + 0xcdc) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) ((x) + 0xcdc) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OFFS (0xcdc) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) ((x) + 0xce0) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) ((x) + 0xce0) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OFFS (0xce0) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x7ffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xce4) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xce4) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OFFS (0xce4) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xce8) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xce8) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OFFS (0xce8) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xcf4) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xcf4) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OFFS (0xcf4) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xcf8) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xcf8) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OFFS (0xcf8) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xcfc) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xcfc) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OFFS (0xcfc) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xd18) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xd18) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_OFFS (0xd18) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xd1c) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xd1c) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_OFFS (0xd1c) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x) ((x) + 0xd20) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_PHYS(x) ((x) + 0xd20) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_OFFS (0xd20) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xd24) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xd24) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_OFFS (0xd24) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xd28) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xd28) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_OFFS (0xd28) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xd2c) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xd2c) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_OFFS (0xd2c) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_ADDR(x) ((x) + 0xd30) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_PHYS(x) ((x) + 0xd30) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_OFFS (0xd30) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xd40) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xd40) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OFFS (0xd40) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_ADDR(x) ((x) + 0xd44) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_PHYS(x) ((x) + 0xd44) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_OFFS (0xd44) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) ((x) + 0xd48) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) ((x) + 0xd48) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OFFS (0xd48) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) ((x) + 0xd4c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) ((x) + 0xd4c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OFFS (0xd4c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) ((x) + 0xd50) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) ((x) + 0xd50) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OFFS (0xd50) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) ((x) + 0xd54) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) ((x) + 0xd54) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OFFS (0xd54) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) ((x) + 0xd58) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) ((x) + 0xd58) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OFFS (0xd58) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x7ffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xd5c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xd5c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OFFS (0xd5c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xd60) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xd60) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OFFS (0xd60) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xd6c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xd6c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OFFS (0xd6c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xd70) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xd70) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OFFS (0xd70) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xd74) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xd74) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OFFS (0xd74) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xd90) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xd90) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OFFS (0xd90) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xd94) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xd94) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OFFS (0xd94) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) ((x) + 0xd98) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) ((x) + 0xd98) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OFFS (0xd98) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xd9c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xd9c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_OFFS (0xd9c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xda0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xda0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_OFFS (0xda0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xda4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xda4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_OFFS (0xda4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x) ((x) + 0xda8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_PHYS(x) ((x) + 0xda8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_OFFS (0xda8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xdb8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xdb8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OFFS (0xdb8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x) ((x) + 0xdbc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_PHYS(x) ((x) + 0xdbc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_OFFS (0xdbc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) ((x) + 0xe38) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) ((x) + 0xe38) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OFFS (0xe38) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) ((x) + 0xe3c) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) ((x) + 0xe3c) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OFFS (0xe3c) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) ((x) + 0xe40) +#define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) ((x) + 0xe40) +#define HWIO_TCL_R0_TCL2FW_RING_ID_OFFS (0xe40) +#define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0xffff +#define HWIO_TCL_R0_TCL2FW_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 8 +#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) ((x) + 0xe44) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) ((x) + 0xe44) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OFFS (0xe44) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) ((x) + 0xe48) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) ((x) + 0xe48) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_OFFS (0xe48) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x7ffffff +#define HWIO_TCL_R0_TCL2FW_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xe4c) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xe4c) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OFFS (0xe4c) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xe50) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xe50) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OFFS (0xe50) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xe5c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xe5c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OFFS (0xe5c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xe60) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xe60) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OFFS (0xe60) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xe64) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xe64) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OFFS (0xe64) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xe80) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xe80) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_OFFS (0xe80) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xe84) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xe84) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_OFFS (0xe84) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x) ((x) + 0xe88) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_PHYS(x) ((x) + 0xe88) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_OFFS (0xe88) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xe8c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xe8c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_OFFS (0xe8c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xe90) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xe90) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_OFFS (0xe90) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xe94) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xe94) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_OFFS (0xe94) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_ADDR(x) ((x) + 0xe98) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_PHYS(x) ((x) + 0xe98) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_OFFS (0xe98) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xea8) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xea8) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OFFS (0xea8) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_ADDR(x) ((x) + 0xeac) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_PHYS(x) ((x) + 0xeac) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_OFFS (0xeac) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) ((x) + 0xeb0) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) ((x) + 0xeb0) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OFFS (0xeb0) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_POR 0x00000000 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ATTR 0x3 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x)) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), m) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x),v) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x),m,v,HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0 + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) ((x) + 0xeb4) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) ((x) + 0xeb4) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OFFS (0xeb4) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0xff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_POR 0x00000000 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ATTR 0x3 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x)) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), m) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x),v) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x),m,v,HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0xff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0 + +#define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) ((x) + 0xeb8) +#define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) ((x) + 0xeb8) +#define HWIO_TCL_R0_ASE_GST_SIZE_OFFS (0xeb8) +#define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0xfffff +#define HWIO_TCL_R0_ASE_GST_SIZE_POR 0x00000000 +#define HWIO_TCL_R0_ASE_GST_SIZE_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_SIZE_ATTR 0x3 +#define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x)) +#define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), m) +#define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x),v) +#define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x),m,v,HWIO_TCL_R0_ASE_GST_SIZE_IN(x)) +#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0xfffff +#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0 + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) ((x) + 0xebc) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) ((x) + 0xebc) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OFFS (0xebc) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff3fff +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_POR 0x00003806 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x)) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x),m,v,HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 16 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_CMD_READ_BYPASS_EN_BMSK 0x2000 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_CMD_READ_BYPASS_EN_SHFT 13 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_WRITE_BACK_FIX_EN_BMSK 0x1000 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_WRITE_BACK_FIX_EN_SHFT 12 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_ONLY_ENTRY_CMD_FIX_EN_BMSK 0x800 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_ONLY_ENTRY_CMD_FIX_EN_SHFT 11 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_BMSK 0x400 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_SHFT 10 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x200 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT 9 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x100 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT 8 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK 0xff +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT 0 + +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_ADDR(x) ((x) + 0xec0) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_PHYS(x) ((x) + 0xec0) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_OFFS (0xec0) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_RMSK 0x3 +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_PCIE_VC_CTRL_ADDR(x)) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_PCIE_VC_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_PCIE_VC_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_PCIE_VC_CTRL_ADDR(x),m,v,HWIO_TCL_R0_ASE_PCIE_VC_CTRL_IN(x)) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_GXI_RD_VCID_1_BMSK 0x2 +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_GXI_RD_VCID_1_SHFT 1 +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_GXI_RD_VCID_0_BMSK 0x1 +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_GXI_RD_VCID_0_SHFT 0 + +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_ADDR(x) ((x) + 0xec4) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_PHYS(x) ((x) + 0xec4) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_OFFS (0xec4) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_POR 0x0000ffff +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_ATTR 0x3 +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_WATCHDOG_WAR_ADDR(x)) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_WATCHDOG_WAR_ADDR(x), m) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_WATCHDOG_WAR_ADDR(x),v) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_WAR_ADDR(x),m,v,HWIO_TCL_R0_ASE_WATCHDOG_WAR_IN(x)) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_STATUS_SHFT 16 +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_LIMIT_BMSK 0xffff +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_LIMIT_SHFT 0 + +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_ADDR(x) ((x) + 0xec8) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_PHYS(x) ((x) + 0xec8) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_OFFS (0xec8) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_POR 0x0000ffff +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_ATTR 0x3 +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_WATCHDOG_ERR_ADDR(x)) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_WATCHDOG_ERR_ADDR(x), m) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_WATCHDOG_ERR_ADDR(x),v) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ERR_ADDR(x),m,v,HWIO_TCL_R0_ASE_WATCHDOG_ERR_IN(x)) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_STATUS_SHFT 16 +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_LIMIT_BMSK 0xffff +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_LIMIT_SHFT 0 + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) ((x) + 0xecc) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) ((x) + 0xecc) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OFFS (0xecc) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_POR 0x00000000 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ATTR 0x3 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x)) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), m) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x),v) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x),m,v,HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_SHFT 31 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 30 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_BMSK 0x3ffffe00 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_SHFT 9 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_BMSK 0x100 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_SHFT 8 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_BMSK 0x80 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_SHFT 7 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_BMSK 0x40 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_SHFT 6 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_BMSK 0x20 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_SHFT 5 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_BMSK 0x10 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_SHFT 4 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_BMSK 0x8 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_SHFT 3 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_BMSK 0x4 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_SHFT 2 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_BMSK 0x2 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_SHFT 1 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_BMSK 0x1 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_SHFT 0 + +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) ((x) + 0xed0) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) ((x) + 0xed0) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OFFS (0xed0) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x1 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_POR 0x00000000 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ATTR 0x1 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x)) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), m) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x1 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0 + +#define HWIO_TCL_R1_CACHE_FLUSH_ADDR(x) ((x) + 0x1000) +#define HWIO_TCL_R1_CACHE_FLUSH_PHYS(x) ((x) + 0x1000) +#define HWIO_TCL_R1_CACHE_FLUSH_OFFS (0x1000) +#define HWIO_TCL_R1_CACHE_FLUSH_RMSK 0x3 +#define HWIO_TCL_R1_CACHE_FLUSH_POR 0x00000000 +#define HWIO_TCL_R1_CACHE_FLUSH_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_CACHE_FLUSH_ATTR 0x3 +#define HWIO_TCL_R1_CACHE_FLUSH_IN(x) \ + in_dword(HWIO_TCL_R1_CACHE_FLUSH_ADDR(x)) +#define HWIO_TCL_R1_CACHE_FLUSH_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), m) +#define HWIO_TCL_R1_CACHE_FLUSH_OUT(x, v) \ + out_dword(HWIO_TCL_R1_CACHE_FLUSH_ADDR(x),v) +#define HWIO_TCL_R1_CACHE_FLUSH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_CACHE_FLUSH_ADDR(x),m,v,HWIO_TCL_R1_CACHE_FLUSH_IN(x)) +#define HWIO_TCL_R1_CACHE_FLUSH_STATUS_BMSK 0x2 +#define HWIO_TCL_R1_CACHE_FLUSH_STATUS_SHFT 1 +#define HWIO_TCL_R1_CACHE_FLUSH_ENABLE_BMSK 0x1 +#define HWIO_TCL_R1_CACHE_FLUSH_ENABLE_SHFT 0 + +#define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) ((x) + 0x1004) +#define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) ((x) + 0x1004) +#define HWIO_TCL_R1_SM_STATES_IX_0_OFFS (0x1004) +#define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x7fff8fff +#define HWIO_TCL_R1_SM_STATES_IX_0_POR 0x00000000 +#define HWIO_TCL_R1_SM_STATES_IX_0_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_SM_STATES_IX_0_ATTR 0x1 +#define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ + in_dword(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x)) +#define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), m) +#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x78000000 +#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 27 +#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x7000000 +#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 24 +#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK 0xe00000 +#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT 21 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CREDIT_RING_BMSK 0x1c0000 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CREDIT_RING_SHFT 18 +#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x38000 +#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT 15 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL4_RING_BMSK 0xe00 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL4_RING_SHFT 9 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x1c0 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT 6 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x38 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT 3 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x7 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0 + +#define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) ((x) + 0x1008) +#define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) ((x) + 0x1008) +#define HWIO_TCL_R1_SM_STATES_IX_1_OFFS (0x1008) +#define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0xfffe3fff +#define HWIO_TCL_R1_SM_STATES_IX_1_POR 0x00000000 +#define HWIO_TCL_R1_SM_STATES_IX_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_SM_STATES_IX_1_ATTR 0x1 +#define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ + in_dword(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x)) +#define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), m) +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_BMSK 0xe0000000 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_SHFT 29 +#define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_BMSK 0x1c000000 +#define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_SHFT 26 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_RING_FW_CTRL_BMSK 0x3800000 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_RING_FW_CTRL_SHFT 23 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_METADATA_BMSK 0x700000 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_METADATA_SHFT 20 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0xe0000 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 17 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x3800 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT 11 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK 0x700 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT 8 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0xe0 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 5 +#define HWIO_TCL_R1_SM_STATES_IX_1_GSE_CTRL_RES_WR_BMSK 0x18 +#define HWIO_TCL_R1_SM_STATES_IX_1_GSE_CTRL_RES_WR_SHFT 3 +#define HWIO_TCL_R1_SM_STATES_IX_1_GSE_CTRL_BMSK 0x7 +#define HWIO_TCL_R1_SM_STATES_IX_1_GSE_CTRL_SHFT 0 + +#define HWIO_TCL_R1_SM_STATES_IX_2_ADDR(x) ((x) + 0x100c) +#define HWIO_TCL_R1_SM_STATES_IX_2_PHYS(x) ((x) + 0x100c) +#define HWIO_TCL_R1_SM_STATES_IX_2_OFFS (0x100c) +#define HWIO_TCL_R1_SM_STATES_IX_2_RMSK 0x3ff +#define HWIO_TCL_R1_SM_STATES_IX_2_POR 0x00000000 +#define HWIO_TCL_R1_SM_STATES_IX_2_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_SM_STATES_IX_2_ATTR 0x1 +#define HWIO_TCL_R1_SM_STATES_IX_2_IN(x) \ + in_dword(HWIO_TCL_R1_SM_STATES_IX_2_ADDR(x)) +#define HWIO_TCL_R1_SM_STATES_IX_2_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_SM_STATES_IX_2_ADDR(x), m) +#define HWIO_TCL_R1_SM_STATES_IX_2_ASE_SKIP_RES_HANDLER_BMSK 0x380 +#define HWIO_TCL_R1_SM_STATES_IX_2_ASE_SKIP_RES_HANDLER_SHFT 7 +#define HWIO_TCL_R1_SM_STATES_IX_2_PPE2TCL1_RING_BMSK 0x70 +#define HWIO_TCL_R1_SM_STATES_IX_2_PPE2TCL1_RING_SHFT 4 +#define HWIO_TCL_R1_SM_STATES_IX_2_GSE_CCE_RES_CLFY_DIS_BMSK 0xc +#define HWIO_TCL_R1_SM_STATES_IX_2_GSE_CCE_RES_CLFY_DIS_SHFT 2 +#define HWIO_TCL_R1_SM_STATES_IX_2_TLV_DEC_CLFY_DIS_BMSK 0x3 +#define HWIO_TCL_R1_SM_STATES_IX_2_TLV_DEC_CLFY_DIS_SHFT 0 + +#define HWIO_TCL_R1_STATUS_ADDR(x) ((x) + 0x1010) +#define HWIO_TCL_R1_STATUS_PHYS(x) ((x) + 0x1010) +#define HWIO_TCL_R1_STATUS_OFFS (0x1010) +#define HWIO_TCL_R1_STATUS_RMSK 0xfffffbff +#define HWIO_TCL_R1_STATUS_POR 0x00000000 +#define HWIO_TCL_R1_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_STATUS_ATTR 0x1 +#define HWIO_TCL_R1_STATUS_IN(x) \ + in_dword(HWIO_TCL_R1_STATUS_ADDR(x)) +#define HWIO_TCL_R1_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_STATUS_ADDR(x), m) +#define HWIO_TCL_R1_STATUS_ASE_SKIP_RES_HANDLER_IDLE_BMSK 0x80000000 +#define HWIO_TCL_R1_STATUS_ASE_SKIP_RES_HANDLER_IDLE_SHFT 31 +#define HWIO_TCL_R1_STATUS_HDR_BUF_EMPTY_BMSK 0x40000000 +#define HWIO_TCL_R1_STATUS_HDR_BUF_EMPTY_SHFT 30 +#define HWIO_TCL_R1_STATUS_DESC_BUF_EMPTY_BMSK 0x20000000 +#define HWIO_TCL_R1_STATUS_DESC_BUF_EMPTY_SHFT 29 +#define HWIO_TCL_R1_STATUS_GSE_CCE_RES_IDLE_BMSK 0x10000000 +#define HWIO_TCL_R1_STATUS_GSE_CCE_RES_IDLE_SHFT 28 +#define HWIO_TCL_R1_STATUS_PROD_RING_FW_FIFO_CTRL_IDLE_BMSK 0x8000000 +#define HWIO_TCL_R1_STATUS_PROD_RING_FW_FIFO_CTRL_IDLE_SHFT 27 +#define HWIO_TCL_R1_STATUS_PROD_RING_BUNCH_FIFO_CTRL_IDLE_BMSK 0x4000000 +#define HWIO_TCL_R1_STATUS_PROD_RING_BUNCH_FIFO_CTRL_IDLE_SHFT 26 +#define HWIO_TCL_R1_STATUS_PROD_RING_CTRL_IDLE_BMSK 0x2000000 +#define HWIO_TCL_R1_STATUS_PROD_RING_CTRL_IDLE_SHFT 25 +#define HWIO_TCL_R1_STATUS_TLV_DECODER_IDLE_BMSK 0x1000000 +#define HWIO_TCL_R1_STATUS_TLV_DECODER_IDLE_SHFT 24 +#define HWIO_TCL_R1_STATUS_TLV_GEN_IDLE_BMSK 0x800000 +#define HWIO_TCL_R1_STATUS_TLV_GEN_IDLE_SHFT 23 +#define HWIO_TCL_R1_STATUS_GSE_CTRL_IDLE_BMSK 0x400000 +#define HWIO_TCL_R1_STATUS_GSE_CTRL_IDLE_SHFT 22 +#define HWIO_TCL_R1_STATUS_CLFY_WRAP_IDLE_BMSK 0x200000 +#define HWIO_TCL_R1_STATUS_CLFY_WRAP_IDLE_SHFT 21 +#define HWIO_TCL_R1_STATUS_CCE_OR_LCE_IDLE_BMSK 0x100000 +#define HWIO_TCL_R1_STATUS_CCE_OR_LCE_IDLE_SHFT 20 +#define HWIO_TCL_R1_STATUS_ASE_IDLE_BMSK 0x80000 +#define HWIO_TCL_R1_STATUS_ASE_IDLE_SHFT 19 +#define HWIO_TCL_R1_STATUS_PARSER_IDLE_BMSK 0x40000 +#define HWIO_TCL_R1_STATUS_PARSER_IDLE_SHFT 18 +#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x20000 +#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 17 +#define HWIO_TCL_R1_STATUS_TCL_STATUS1_PROD_IDLE_BMSK 0x10000 +#define HWIO_TCL_R1_STATUS_TCL_STATUS1_PROD_IDLE_SHFT 16 +#define HWIO_TCL_R1_STATUS_TCL2FW_PROD_IDLE_BMSK 0x8000 +#define HWIO_TCL_R1_STATUS_TCL2FW_PROD_IDLE_SHFT 15 +#define HWIO_TCL_R1_STATUS_TCL2TQM_PROD_IDLE_BMSK 0x4000 +#define HWIO_TCL_R1_STATUS_TCL2TQM_PROD_IDLE_SHFT 14 +#define HWIO_TCL_R1_STATUS_PPE2TCL1_CONS_IDLE_BMSK 0x2000 +#define HWIO_TCL_R1_STATUS_PPE2TCL1_CONS_IDLE_SHFT 13 +#define HWIO_TCL_R1_STATUS_SW2TCL_CREDIT_CONS_IDLE_BMSK 0x1000 +#define HWIO_TCL_R1_STATUS_SW2TCL_CREDIT_CONS_IDLE_SHFT 12 +#define HWIO_TCL_R1_STATUS_FW2TCL1_CONS_IDLE_BMSK 0x800 +#define HWIO_TCL_R1_STATUS_FW2TCL1_CONS_IDLE_SHFT 11 +#define HWIO_TCL_R1_STATUS_SW2TCL4_CONS_IDLE_BMSK 0x200 +#define HWIO_TCL_R1_STATUS_SW2TCL4_CONS_IDLE_SHFT 9 +#define HWIO_TCL_R1_STATUS_SW2TCL3_CONS_IDLE_BMSK 0x100 +#define HWIO_TCL_R1_STATUS_SW2TCL3_CONS_IDLE_SHFT 8 +#define HWIO_TCL_R1_STATUS_SW2TCL2_CONS_IDLE_BMSK 0x80 +#define HWIO_TCL_R1_STATUS_SW2TCL2_CONS_IDLE_SHFT 7 +#define HWIO_TCL_R1_STATUS_SW2TCL1_CONS_IDLE_BMSK 0x40 +#define HWIO_TCL_R1_STATUS_SW2TCL1_CONS_IDLE_SHFT 6 +#define HWIO_TCL_R1_STATUS_GXI_IDLE_BMSK 0x20 +#define HWIO_TCL_R1_STATUS_GXI_IDLE_SHFT 5 +#define HWIO_TCL_R1_STATUS_DESC_RD_IDLE_BMSK 0x10 +#define HWIO_TCL_R1_STATUS_DESC_RD_IDLE_SHFT 4 +#define HWIO_TCL_R1_STATUS_SDU_HDR_FETCH_IDLE_BMSK 0x8 +#define HWIO_TCL_R1_STATUS_SDU_HDR_FETCH_IDLE_SHFT 3 +#define HWIO_TCL_R1_STATUS_LINK_DESC_FETCH_IDLE_BMSK 0x4 +#define HWIO_TCL_R1_STATUS_LINK_DESC_FETCH_IDLE_SHFT 2 +#define HWIO_TCL_R1_STATUS_DATA_FETCH_IDLE_BMSK 0x2 +#define HWIO_TCL_R1_STATUS_DATA_FETCH_IDLE_SHFT 1 +#define HWIO_TCL_R1_STATUS_TCL_INT_IDLE_BMSK 0x1 +#define HWIO_TCL_R1_STATUS_TCL_INT_IDLE_SHFT 0 + +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_ADDR(x) ((x) + 0x1014) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_PHYS(x) ((x) + 0x1014) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_OFFS (0x1014) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_RMSK 0x7fff8fff +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_POR 0x00000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_ATTR 0x1 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_IN(x) \ + in_dword(HWIO_TCL_R1_WDOG_SM_STATES_IX_0_ADDR(x)) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_WDOG_SM_STATES_IX_0_ADDR(x), m) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_TLV_GEN_BMSK 0x78000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_TLV_GEN_SHFT 27 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x7000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 24 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_MSDU_FETCH_BMSK 0xe00000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_MSDU_FETCH_SHFT 21 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL_CREDIT_RING_BMSK 0x1c0000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL_CREDIT_RING_SHFT 18 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x38000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_FW2TCL1_RING_SHFT 15 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL4_RING_BMSK 0xe00 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL4_RING_SHFT 9 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x1c0 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL3_RING_SHFT 6 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x38 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL2_RING_SHFT 3 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x7 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0 + +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_ADDR(x) ((x) + 0x1018) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PHYS(x) ((x) + 0x1018) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_OFFS (0x1018) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_RMSK 0xfffe3fff +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_POR 0x00000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_ATTR 0x1 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_IN(x) \ + in_dword(HWIO_TCL_R1_WDOG_SM_STATES_IX_1_ADDR(x)) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_WDOG_SM_STATES_IX_1_ADDR(x), m) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_BMSK 0xe0000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_SHFT 29 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_DSCP_TABLE_ACC_BMSK 0x1c000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_DSCP_TABLE_ACC_SHFT 26 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PROD_RING_FW_CTRL_BMSK 0x3800000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PROD_RING_FW_CTRL_SHFT 23 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PROD_CTRL_METADATA_BMSK 0x700000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PROD_CTRL_METADATA_SHFT 20 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PROD_CTRL_BMSK 0xe0000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PROD_CTRL_SHFT 17 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x3800 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL_STATUS1_SHFT 11 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL2FW_BMSK 0x700 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL2FW_SHFT 8 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL2TQM_BMSK 0xe0 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL2TQM_SHFT 5 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_GSE_CTRL_RES_WR_BMSK 0x18 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_GSE_CTRL_RES_WR_SHFT 3 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_GSE_CTRL_BMSK 0x7 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_GSE_CTRL_SHFT 0 + +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_ADDR(x) ((x) + 0x101c) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_PHYS(x) ((x) + 0x101c) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_OFFS (0x101c) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_RMSK 0x3ff +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_POR 0x00000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_ATTR 0x1 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_IN(x) \ + in_dword(HWIO_TCL_R1_WDOG_SM_STATES_IX_2_ADDR(x)) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_WDOG_SM_STATES_IX_2_ADDR(x), m) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_ASE_SKIP_RES_HANDLER_BMSK 0x380 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_ASE_SKIP_RES_HANDLER_SHFT 7 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_PPE2TCL1_RING_BMSK 0x70 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_PPE2TCL1_RING_SHFT 4 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_GSE_CCE_RES_CLFY_DIS_BMSK 0xc +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_GSE_CCE_RES_CLFY_DIS_SHFT 2 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_TLV_DEC_CLFY_DIS_BMSK 0x3 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_TLV_DEC_CLFY_DIS_SHFT 0 + +#define HWIO_TCL_R1_WDOG_STATUS_ADDR(x) ((x) + 0x1020) +#define HWIO_TCL_R1_WDOG_STATUS_PHYS(x) ((x) + 0x1020) +#define HWIO_TCL_R1_WDOG_STATUS_OFFS (0x1020) +#define HWIO_TCL_R1_WDOG_STATUS_RMSK 0xfffffbff +#define HWIO_TCL_R1_WDOG_STATUS_POR 0x00000000 +#define HWIO_TCL_R1_WDOG_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_WDOG_STATUS_ATTR 0x1 +#define HWIO_TCL_R1_WDOG_STATUS_IN(x) \ + in_dword(HWIO_TCL_R1_WDOG_STATUS_ADDR(x)) +#define HWIO_TCL_R1_WDOG_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_WDOG_STATUS_ADDR(x), m) +#define HWIO_TCL_R1_WDOG_STATUS_ASE_SKIP_RES_HANDLER_IDLE_BMSK 0x80000000 +#define HWIO_TCL_R1_WDOG_STATUS_ASE_SKIP_RES_HANDLER_IDLE_SHFT 31 +#define HWIO_TCL_R1_WDOG_STATUS_HDR_BUF_EMPTY_BMSK 0x40000000 +#define HWIO_TCL_R1_WDOG_STATUS_HDR_BUF_EMPTY_SHFT 30 +#define HWIO_TCL_R1_WDOG_STATUS_DESC_BUF_EMPTY_BMSK 0x20000000 +#define HWIO_TCL_R1_WDOG_STATUS_DESC_BUF_EMPTY_SHFT 29 +#define HWIO_TCL_R1_WDOG_STATUS_GSE_CCE_RES_IDLE_BMSK 0x10000000 +#define HWIO_TCL_R1_WDOG_STATUS_GSE_CCE_RES_IDLE_SHFT 28 +#define HWIO_TCL_R1_WDOG_STATUS_PROD_RING_FW_FIFO_CTRL_IDLE_BMSK 0x8000000 +#define HWIO_TCL_R1_WDOG_STATUS_PROD_RING_FW_FIFO_CTRL_IDLE_SHFT 27 +#define HWIO_TCL_R1_WDOG_STATUS_PROD_RING_BUNCH_FIFO_CTRL_IDLE_BMSK 0x4000000 +#define HWIO_TCL_R1_WDOG_STATUS_PROD_RING_BUNCH_FIFO_CTRL_IDLE_SHFT 26 +#define HWIO_TCL_R1_WDOG_STATUS_PROD_RING_CTRL_IDLE_BMSK 0x2000000 +#define HWIO_TCL_R1_WDOG_STATUS_PROD_RING_CTRL_IDLE_SHFT 25 +#define HWIO_TCL_R1_WDOG_STATUS_TLV_DECODER_IDLE_BMSK 0x1000000 +#define HWIO_TCL_R1_WDOG_STATUS_TLV_DECODER_IDLE_SHFT 24 +#define HWIO_TCL_R1_WDOG_STATUS_TLV_GEN_IDLE_BMSK 0x800000 +#define HWIO_TCL_R1_WDOG_STATUS_TLV_GEN_IDLE_SHFT 23 +#define HWIO_TCL_R1_WDOG_STATUS_GSE_CTRL_IDLE_BMSK 0x400000 +#define HWIO_TCL_R1_WDOG_STATUS_GSE_CTRL_IDLE_SHFT 22 +#define HWIO_TCL_R1_WDOG_STATUS_CLFY_WRAP_IDLE_BMSK 0x200000 +#define HWIO_TCL_R1_WDOG_STATUS_CLFY_WRAP_IDLE_SHFT 21 +#define HWIO_TCL_R1_WDOG_STATUS_CCE_OR_LCE_IDLE_BMSK 0x100000 +#define HWIO_TCL_R1_WDOG_STATUS_CCE_OR_LCE_IDLE_SHFT 20 +#define HWIO_TCL_R1_WDOG_STATUS_ASE_IDLE_BMSK 0x80000 +#define HWIO_TCL_R1_WDOG_STATUS_ASE_IDLE_SHFT 19 +#define HWIO_TCL_R1_WDOG_STATUS_PARSER_IDLE_BMSK 0x40000 +#define HWIO_TCL_R1_WDOG_STATUS_PARSER_IDLE_SHFT 18 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x20000 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 17 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_STATUS1_PROD_IDLE_BMSK 0x10000 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_STATUS1_PROD_IDLE_SHFT 16 +#define HWIO_TCL_R1_WDOG_STATUS_TCL2FW_PROD_IDLE_BMSK 0x8000 +#define HWIO_TCL_R1_WDOG_STATUS_TCL2FW_PROD_IDLE_SHFT 15 +#define HWIO_TCL_R1_WDOG_STATUS_TCL2TQM_PROD_IDLE_BMSK 0x4000 +#define HWIO_TCL_R1_WDOG_STATUS_TCL2TQM_PROD_IDLE_SHFT 14 +#define HWIO_TCL_R1_WDOG_STATUS_PPE2TCL1_CONS_IDLE_BMSK 0x2000 +#define HWIO_TCL_R1_WDOG_STATUS_PPE2TCL1_CONS_IDLE_SHFT 13 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL_CREDIT_CONS_IDLE_BMSK 0x1000 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL_CREDIT_CONS_IDLE_SHFT 12 +#define HWIO_TCL_R1_WDOG_STATUS_FW2TCL1_CONS_IDLE_BMSK 0x800 +#define HWIO_TCL_R1_WDOG_STATUS_FW2TCL1_CONS_IDLE_SHFT 11 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL4_CONS_IDLE_BMSK 0x200 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL4_CONS_IDLE_SHFT 9 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL3_CONS_IDLE_BMSK 0x100 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL3_CONS_IDLE_SHFT 8 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL2_CONS_IDLE_BMSK 0x80 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL2_CONS_IDLE_SHFT 7 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL1_CONS_IDLE_BMSK 0x40 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL1_CONS_IDLE_SHFT 6 +#define HWIO_TCL_R1_WDOG_STATUS_GXI_IDLE_BMSK 0x20 +#define HWIO_TCL_R1_WDOG_STATUS_GXI_IDLE_SHFT 5 +#define HWIO_TCL_R1_WDOG_STATUS_DESC_RD_IDLE_BMSK 0x10 +#define HWIO_TCL_R1_WDOG_STATUS_DESC_RD_IDLE_SHFT 4 +#define HWIO_TCL_R1_WDOG_STATUS_SDU_HDR_FETCH_IDLE_BMSK 0x8 +#define HWIO_TCL_R1_WDOG_STATUS_SDU_HDR_FETCH_IDLE_SHFT 3 +#define HWIO_TCL_R1_WDOG_STATUS_LINK_DESC_FETCH_IDLE_BMSK 0x4 +#define HWIO_TCL_R1_WDOG_STATUS_LINK_DESC_FETCH_IDLE_SHFT 2 +#define HWIO_TCL_R1_WDOG_STATUS_DATA_FETCH_IDLE_BMSK 0x2 +#define HWIO_TCL_R1_WDOG_STATUS_DATA_FETCH_IDLE_SHFT 1 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_INT_IDLE_BMSK 0x1 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_INT_IDLE_SHFT 0 + +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_ADDR(x) ((x) + 0x1024) +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PHYS(x) ((x) + 0x1024) +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_OFFS (0x1024) +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_RMSK 0x3f7ef +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_POR 0x00000000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_ATTR 0x1 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_IN(x) \ + in_dword(HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_ADDR(x)) +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_ADDR(x), m) +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PARSER_BMSK 0x20000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PARSER_SHFT 17 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_ASE_BMSK 0x10000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_ASE_SHFT 16 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_METADATA_FETCH_BMSK 0x8000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_METADATA_FETCH_SHFT 15 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PEER_DATA_FETCH_BMSK 0x4000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PEER_DATA_FETCH_SHFT 14 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_HDR_DATA_FETCH_BMSK 0x2000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_HDR_DATA_FETCH_SHFT 13 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_LINK_EXTN_FETCH_BMSK 0x1000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_LINK_EXTN_FETCH_SHFT 12 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_TCL_STATUS1_BMSK 0x400 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_TCL_STATUS1_SHFT 10 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_TCL2FW_BMSK 0x200 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_TCL2FW_SHFT 9 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_TCL2TQM_BMSK 0x100 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_TCL2TQM_SHFT 8 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PPE2TCL1_BMSK 0x80 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PPE2TCL1_SHFT 7 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL_CREDIT_BMSK 0x40 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL_CREDIT_SHFT 6 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_FW2TCL1_BMSK 0x20 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_FW2TCL1_SHFT 5 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL4_BMSK 0x8 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL4_SHFT 3 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL3_BMSK 0x4 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL3_SHFT 2 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL2_BMSK 0x2 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL2_SHFT 1 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL1_BMSK 0x1 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL1_SHFT 0 + +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_ADDR(x) ((x) + 0x1028) +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_PHYS(x) ((x) + 0x1028) +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_OFFS (0x1028) +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_RMSK 0xff +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_POR 0x00000000 +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_ATTR 0x1 +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_IN(x) \ + in_dword(HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_ADDR(x)) +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_ADDR(x), m) +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_REQ_RESP_TIME_BMSK 0xff +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_REQ_RESP_TIME_SHFT 0 + +#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x102c) +#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x102c) +#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS (0x102c) +#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK 0x1ff +#define HWIO_TCL_R1_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x) \ + in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)) +#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x100 +#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 8 +#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK 0xc0 +#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT 6 +#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK 0x3f +#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT 0 + +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X1030 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X1030 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X1030 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn 511 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) ((x) + 0x1830) +#define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) ((x) + 0x1830) +#define HWIO_TCL_R1_TESTBUS_LOW_OFFS (0x1830) +#define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_LOW_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_LOW_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_LOW_ATTR 0x1 +#define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ + in_dword(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x)) +#define HWIO_TCL_R1_TESTBUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), m) +#define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0 + +#define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) ((x) + 0x1834) +#define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) ((x) + 0x1834) +#define HWIO_TCL_R1_TESTBUS_HIGH_OFFS (0x1834) +#define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0xff +#define HWIO_TCL_R1_TESTBUS_HIGH_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_HIGH_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_HIGH_ATTR 0x1 +#define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ + in_dword(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x)) +#define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), m) +#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0xff +#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0 + +#define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) ((x) + 0x1838) +#define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) ((x) + 0x1838) +#define HWIO_TCL_R1_EVENTMASK_IX_0_OFFS (0x1838) +#define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_POR 0x0000ffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_ATTR 0x3 +#define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ + in_dword(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), m) +#define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, v) \ + out_dword(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x),v) +#define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0 + +#define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) ((x) + 0x183c) +#define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) ((x) + 0x183c) +#define HWIO_TCL_R1_EVENTMASK_IX_1_OFFS (0x183c) +#define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_POR 0x0000ffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_ATTR 0x3 +#define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ + in_dword(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), m) +#define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, v) \ + out_dword(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x),v) +#define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0 + +#define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) ((x) + 0x1840) +#define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) ((x) + 0x1840) +#define HWIO_TCL_R1_EVENTMASK_IX_2_OFFS (0x1840) +#define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_POR 0x0000ffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_ATTR 0x3 +#define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ + in_dword(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), m) +#define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, v) \ + out_dword(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x),v) +#define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x),m,v,HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0 + +#define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) ((x) + 0x1844) +#define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) ((x) + 0x1844) +#define HWIO_TCL_R1_EVENTMASK_IX_3_OFFS (0x1844) +#define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_POR 0x0000ffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_ATTR 0x3 +#define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ + in_dword(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), m) +#define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, v) \ + out_dword(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x),v) +#define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x),m,v,HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0 + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x1848) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x1848) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x1848) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 17 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 2 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 1 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0 + +#define HWIO_TCL_R1_SPARE_REGISTER_ADDR(x) ((x) + 0x184c) +#define HWIO_TCL_R1_SPARE_REGISTER_PHYS(x) ((x) + 0x184c) +#define HWIO_TCL_R1_SPARE_REGISTER_OFFS (0x184c) +#define HWIO_TCL_R1_SPARE_REGISTER_RMSK 0xffffffff +#define HWIO_TCL_R1_SPARE_REGISTER_POR 0x00000000 +#define HWIO_TCL_R1_SPARE_REGISTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_SPARE_REGISTER_ATTR 0x3 +#define HWIO_TCL_R1_SPARE_REGISTER_IN(x) \ + in_dword(HWIO_TCL_R1_SPARE_REGISTER_ADDR(x)) +#define HWIO_TCL_R1_SPARE_REGISTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), m) +#define HWIO_TCL_R1_SPARE_REGISTER_OUT(x, v) \ + out_dword(HWIO_TCL_R1_SPARE_REGISTER_ADDR(x),v) +#define HWIO_TCL_R1_SPARE_REGISTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_SPARE_REGISTER_ADDR(x),m,v,HWIO_TCL_R1_SPARE_REGISTER_IN(x)) +#define HWIO_TCL_R1_SPARE_REGISTER_TCL_SPARE_FIELD_32_BMSK 0xffffffff +#define HWIO_TCL_R1_SPARE_REGISTER_TCL_SPARE_FIELD_32_SHFT 0 + +#define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x1850) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x1850) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_OFFS (0x1850) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x1854) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x1854) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OFFS (0x1854) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) ((x) + 0x1858) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) ((x) + 0x1858) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OFFS (0x1858) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ATTR 0x3 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, v) \ + out_dword(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x),v) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x),m,v,HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) ((x) + 0x185c) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) ((x) + 0x185c) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OFFS (0x185c) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) ((x) + 0x1860) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) ((x) + 0x1860) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OFFS (0x1860) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_ADDR(x) ((x) + 0x1864) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_PHYS(x) ((x) + 0x1864) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_OFFS (0x1864) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_VAL_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) ((x) + 0x1868) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) ((x) + 0x1868) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OFFS (0x1868) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0xfffff +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0xffc00 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 10 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x3ff +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) ((x) + 0x186c) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) ((x) + 0x186c) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OFFS (0x186c) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x3ffffff +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x3fffc00 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 10 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x3e0 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 5 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x1f +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_ADDR(x) ((x) + 0x1870) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_PHYS(x) ((x) + 0x1870) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_OFFS (0x1870) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_VAL_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_ADDR(x) ((x) + 0x1874) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_PHYS(x) ((x) + 0x1874) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_OFFS (0x1874) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_VAL_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_ADDR(x) ((x) + 0x1878) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_PHYS(x) ((x) + 0x1878) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_OFFS (0x1878) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_VAL_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_ADDR(x) ((x) + 0x187c) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_PHYS(x) ((x) + 0x187c) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_OFFS (0x187c) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_RMSK 0x3ff +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_PEAK_NUM_SEARCH_PENDING_BMSK 0x3e0 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_PEAK_NUM_SEARCH_PENDING_SHFT 5 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_NUM_SEARCH_PENDING_BMSK 0x1f +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_NUM_SEARCH_PENDING_SHFT 0 + +#define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) ((x) + 0x1880) +#define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) ((x) + 0x1880) +#define HWIO_TCL_R1_ASE_SM_STATES_OFFS (0x1880) +#define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x3fff0f +#define HWIO_TCL_R1_ASE_SM_STATES_POR 0x00000000 +#define HWIO_TCL_R1_ASE_SM_STATES_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_SM_STATES_ATTR 0x1 +#define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x)) +#define HWIO_TCL_R1_ASE_SM_STATES_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), m) +#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x300000 +#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 20 +#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK 0xc0000 +#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT 18 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK 0x30000 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT 16 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK 0xc000 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT 14 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK 0x3800 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT 11 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK 0x700 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT 8 +#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK 0xf +#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT 0 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) ((x) + 0x1884) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) ((x) + 0x1884) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OFFS (0x1884) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x3ff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_POR 0x00000000 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ATTR 0x3 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x)) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), m) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, v) \ + out_dword(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x),v) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x),m,v,HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x3ff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) ((x) + 0x1888) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) ((x) + 0x1888) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OFFS (0x1888) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x7fffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_POR 0x00000000 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ATTR 0x1 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x)) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), m) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x7ffff8 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 3 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x4 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 2 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x2 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 1 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x1 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base,n) ((base) + 0X188C + (0x4*(n))) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base,n) ((base) + 0X188C + (0x4*(n))) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OFFS(n) (0X188C + (0x4*(n))) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_POR 0x00000000 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ATTR 0x1 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base,n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base,n), mask) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) ((x) + 0x2000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OFFS (0x2000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) ((x) + 0x2004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OFFS (0x2004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) ((x) + 0x2008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OFFS (0x2008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) ((x) + 0x200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) ((x) + 0x200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OFFS (0x200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) ((x) + 0x2010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) ((x) + 0x2010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OFFS (0x2010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL3_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) ((x) + 0x2014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) ((x) + 0x2014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OFFS (0x2014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL3_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x) ((x) + 0x2018) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_PHYS(x) ((x) + 0x2018) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_OFFS (0x2018) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL4_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL4_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL4_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL4_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL4_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL4_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x) ((x) + 0x201c) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_PHYS(x) ((x) + 0x201c) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_OFFS (0x201c) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL4_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL4_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL4_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL4_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL4_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL4_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x) ((x) + 0x2028) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_PHYS(x) ((x) + 0x2028) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OFFS (0x2028) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x) ((x) + 0x202c) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_PHYS(x) ((x) + 0x202c) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OFFS (0x202c) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) ((x) + 0x2030) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) ((x) + 0x2030) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OFFS (0x2030) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0xffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_FW2TCL1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) ((x) + 0x2034) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) ((x) + 0x2034) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OFFS (0x2034) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0xffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_FW2TCL1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x) ((x) + 0x2038) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_PHYS(x) ((x) + 0x2038) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_OFFS (0x2038) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_PPE2TCL1_RING_HP_IN(x)) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x) ((x) + 0x203c) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_PHYS(x) ((x) + 0x203c) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_OFFS (0x203c) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_PPE2TCL1_RING_TP_IN(x)) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x) ((x) + 0x2040) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x) ((x) + 0x2040) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_OFFS (0x2040) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK 0xffff +#define HWIO_TCL_R2_TCL2TQM_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_TCL2TQM_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL2TQM_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x) ((x) + 0x2044) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x) ((x) + 0x2044) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_OFFS (0x2044) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK 0xffff +#define HWIO_TCL_R2_TCL2TQM_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_TCL2TQM_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL2TQM_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) ((x) + 0x2048) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) ((x) + 0x2048) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OFFS (0x2048) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0xffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) ((x) + 0x204c) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) ((x) + 0x204c) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OFFS (0x204c) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0xffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x) ((x) + 0x2058) +#define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x) ((x) + 0x2058) +#define HWIO_TCL_R2_TCL2FW_RING_HP_OFFS (0x2058) +#define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK 0xffff +#define HWIO_TCL_R2_TCL2FW_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_TCL2FW_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL2FW_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)) +#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x) ((x) + 0x205c) +#define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x) ((x) + 0x205c) +#define HWIO_TCL_R2_TCL2FW_RING_TP_OFFS (0x205c) +#define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK 0xffff +#define HWIO_TCL_R2_TCL2FW_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_TCL2FW_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL2FW_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)) +#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: MAC_CMN_PARSER_REG + *--------------------------------------------------------------------------*/ + +#define MAC_CMN_PARSER_REG_REG_BASE (UMAC_BASE + 0x00047000) +#define MAC_CMN_PARSER_REG_REG_BASE_SIZE 0x3000 +#define MAC_CMN_PARSER_REG_REG_BASE_USED 0x508 +#define MAC_CMN_PARSER_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00047000) +#define MAC_CMN_PARSER_REG_REG_BASE_OFFS 0x00047000 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_ADDR(x) ((x) + 0x0) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_PHYS(x) ((x) + 0x0) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_OFFS (0x0) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_ATTR 0x1 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_ADDR(x) ((x) + 0x4) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_PHYS(x) ((x) + 0x4) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_OFFS (0x4) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_POR 0x0000002b +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_ATTR 0x1 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_ADDR(x) ((x) + 0x8) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_PHYS(x) ((x) + 0x8) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_OFFS (0x8) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_POR 0x0000003c +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_ATTR 0x1 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_ADDR(x) ((x) + 0xc) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_PHYS(x) ((x) + 0xc) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_OFFS (0xc) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_POR 0x00000033 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_ATTR 0x1 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_ADDR(x) ((x) + 0x10) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_PHYS(x) ((x) + 0x10) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_OFFS (0x10) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_POR 0x00000887 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_ATTR 0x1 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_ADDR(x) ((x) + 0x14) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_PHYS(x) ((x) + 0x14) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_OFFS (0x14) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_POR 0x0000082c +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_ATTR 0x1 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_ADDR(x) ((x) + 0x18) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_PHYS(x) ((x) + 0x18) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_OFFS (0x18) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_ADDR(x) ((x) + 0x1c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_PHYS(x) ((x) + 0x1c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_OFFS (0x1c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_ADDR(x) ((x) + 0x20) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_PHYS(x) ((x) + 0x20) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_OFFS (0x20) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_ADDR(x) ((x) + 0x24) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_PHYS(x) ((x) + 0x24) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_OFFS (0x24) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_ADDR(x) ((x) + 0x28) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_PHYS(x) ((x) + 0x28) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_OFFS (0x28) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_ADDR(x) ((x) + 0x2c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_PHYS(x) ((x) + 0x2c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_OFFS (0x2c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_ADDR(x) ((x) + 0x30) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_PHYS(x) ((x) + 0x30) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_OFFS (0x30) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_ADDR(x) ((x) + 0x34) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_PHYS(x) ((x) + 0x34) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_OFFS (0x34) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_ADDR(x) ((x) + 0x38) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_PHYS(x) ((x) + 0x38) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_OFFS (0x38) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_ADDR(x) ((x) + 0x3c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_PHYS(x) ((x) + 0x3c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_OFFS (0x3c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_ADDR(x) ((x) + 0x40) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_PHYS(x) ((x) + 0x40) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_OFFS (0x40) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_RMSK 0xff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_POR 0x00000000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_ATTR 0x3 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_ADDR(x)) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_ADDR(x), m) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_ADDR(x),v) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_ADDR(x),m,v,HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_IN(x)) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_HEADERS1_BMSK 0xf0 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_HEADERS1_SHFT 4 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_HEADERS0_BMSK 0xf +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_HEADERS0_SHFT 0 + +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_ADDR(x) ((x) + 0x44) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_PHYS(x) ((x) + 0x44) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_OFFS (0x44) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_POR 0x00000000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_ATTR 0x3 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_ADDR(x)) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_ADDR(x), m) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_ADDR(x),v) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_ADDR(x),m,v,HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_IN(x)) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL3_BMSK 0xff000000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL3_SHFT 24 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL2_BMSK 0xff0000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL2_SHFT 16 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL1_BMSK 0xff00 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL1_SHFT 8 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL0_BMSK 0xff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL0_SHFT 0 + +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_ADDR(x) ((x) + 0x48) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_PHYS(x) ((x) + 0x48) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_OFFS (0x48) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_POR 0x00000000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_ATTR 0x3 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_ADDR(x)) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_ADDR(x), m) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_ADDR(x),v) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_ADDR(x),m,v,HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_IN(x)) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL7_BMSK 0xff000000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL7_SHFT 24 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL6_BMSK 0xff0000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL6_SHFT 16 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL5_BMSK 0xff00 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL5_SHFT 8 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL4_BMSK 0xff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL4_SHFT 0 + +#define HWIO_CP_R0_IPV6_CONFIG_ADDR(x) ((x) + 0x8c) +#define HWIO_CP_R0_IPV6_CONFIG_PHYS(x) ((x) + 0x8c) +#define HWIO_CP_R0_IPV6_CONFIG_OFFS (0x8c) +#define HWIO_CP_R0_IPV6_CONFIG_RMSK 0xfff +#define HWIO_CP_R0_IPV6_CONFIG_POR 0x00000080 +#define HWIO_CP_R0_IPV6_CONFIG_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_CONFIG_ATTR 0x3 +#define HWIO_CP_R0_IPV6_CONFIG_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_CONFIG_ADDR(x)) +#define HWIO_CP_R0_IPV6_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_CONFIG_ADDR(x), m) +#define HWIO_CP_R0_IPV6_CONFIG_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_CONFIG_ADDR(x),v) +#define HWIO_CP_R0_IPV6_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_CONFIG_ADDR(x),m,v,HWIO_CP_R0_IPV6_CONFIG_IN(x)) +#define HWIO_CP_R0_IPV6_CONFIG_USE_AH_FOR_FLOW_ID_BMSK 0x800 +#define HWIO_CP_R0_IPV6_CONFIG_USE_AH_FOR_FLOW_ID_SHFT 11 +#define HWIO_CP_R0_IPV6_CONFIG_SPI_FROM_AH_OR_ESP_BMSK 0x400 +#define HWIO_CP_R0_IPV6_CONFIG_SPI_FROM_AH_OR_ESP_SHFT 10 +#define HWIO_CP_R0_IPV6_CONFIG_L4_BYTES_EXCEEDED_256_BMSK 0x200 +#define HWIO_CP_R0_IPV6_CONFIG_L4_BYTES_EXCEEDED_256_SHFT 9 +#define HWIO_CP_R0_IPV6_CONFIG_L3_BYTES_EXCEEDED_256_BMSK 0x100 +#define HWIO_CP_R0_IPV6_CONFIG_L3_BYTES_EXCEEDED_256_SHFT 8 +#define HWIO_CP_R0_IPV6_CONFIG_EXT_HEADER_BYTES_BMSK 0xff +#define HWIO_CP_R0_IPV6_CONFIG_EXT_HEADER_BYTES_SHFT 0 + +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_ADDR(x) ((x) + 0x90) +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_PHYS(x) ((x) + 0x90) +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_OFFS (0x90) +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_RMSK 0x1ffff +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_POR 0x00010040 +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_POR_RMSK 0xffffffff +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_ATTR 0x1 +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_IN(x) \ + in_dword(HWIO_CP_R0_COMMIT_TLV_CONFIG_ADDR(x)) +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_COMMIT_TLV_CONFIG_ADDR(x), m) +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_COMMIT_DONE_NUM_BMSK 0x1ff00 +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_COMMIT_DONE_NUM_SHFT 8 +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_COMMIT_NUM_BMSK 0xff +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_COMMIT_NUM_SHFT 0 + +#define HWIO_CP_R0_CLKGATE_DISABLE_ADDR(x) ((x) + 0x94) +#define HWIO_CP_R0_CLKGATE_DISABLE_PHYS(x) ((x) + 0x94) +#define HWIO_CP_R0_CLKGATE_DISABLE_OFFS (0x94) +#define HWIO_CP_R0_CLKGATE_DISABLE_RMSK 0xffffffff +#define HWIO_CP_R0_CLKGATE_DISABLE_POR 0x00000000 +#define HWIO_CP_R0_CLKGATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_CP_R0_CLKGATE_DISABLE_ATTR 0x3 +#define HWIO_CP_R0_CLKGATE_DISABLE_IN(x) \ + in_dword(HWIO_CP_R0_CLKGATE_DISABLE_ADDR(x)) +#define HWIO_CP_R0_CLKGATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_CLKGATE_DISABLE_ADDR(x), m) +#define HWIO_CP_R0_CLKGATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_CP_R0_CLKGATE_DISABLE_ADDR(x),v) +#define HWIO_CP_R0_CLKGATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_CLKGATE_DISABLE_ADDR(x),m,v,HWIO_CP_R0_CLKGATE_DISABLE_IN(x)) +#define HWIO_CP_R0_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 +#define HWIO_CP_R0_CLKGATE_DISABLE_CLK_EXTEND_SHFT 31 +#define HWIO_CP_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 +#define HWIO_CP_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 30 +#define HWIO_CP_R0_CLKGATE_DISABLE_CP_RSRVD_BMSK 0x3fffff00 +#define HWIO_CP_R0_CLKGATE_DISABLE_CP_RSRVD_SHFT 8 +#define HWIO_CP_R0_CLKGATE_DISABLE_CCE_SM_BMSK 0x80 +#define HWIO_CP_R0_CLKGATE_DISABLE_CCE_SM_SHFT 7 +#define HWIO_CP_R0_CLKGATE_DISABLE_NWIFI_BMSK 0x40 +#define HWIO_CP_R0_CLKGATE_DISABLE_NWIFI_SHFT 6 +#define HWIO_CP_R0_CLKGATE_DISABLE_ETH_BMSK 0x20 +#define HWIO_CP_R0_CLKGATE_DISABLE_ETH_SHFT 5 +#define HWIO_CP_R0_CLKGATE_DISABLE_AMSDU_11AH_BMSK 0x10 +#define HWIO_CP_R0_CLKGATE_DISABLE_AMSDU_11AH_SHFT 4 +#define HWIO_CP_R0_CLKGATE_DISABLE_AMSDU_11AC_BMSK 0x8 +#define HWIO_CP_R0_CLKGATE_DISABLE_AMSDU_11AC_SHFT 3 +#define HWIO_CP_R0_CLKGATE_DISABLE_WIFI_BMSK 0x4 +#define HWIO_CP_R0_CLKGATE_DISABLE_WIFI_SHFT 2 +#define HWIO_CP_R0_CLKGATE_DISABLE_CORE_BMSK 0x2 +#define HWIO_CP_R0_CLKGATE_DISABLE_CORE_SHFT 1 +#define HWIO_CP_R0_CLKGATE_DISABLE_APB_BMSK 0x1 +#define HWIO_CP_R0_CLKGATE_DISABLE_APB_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_ADDR(x) ((x) + 0x98) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_PHYS(x) ((x) + 0x98) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_OFFS (0x98) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_ADDR(x) ((x) + 0x9c) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_PHYS(x) ((x) + 0x9c) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_OFFS (0x9c) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_ADDR(x) ((x) + 0xa0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_PHYS(x) ((x) + 0xa0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_OFFS (0xa0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_ADDR(x) ((x) + 0xa4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_PHYS(x) ((x) + 0xa4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_OFFS (0xa4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_ADDR(x) ((x) + 0xa8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_PHYS(x) ((x) + 0xa8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_OFFS (0xa8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_ADDR(x) ((x) + 0xac) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_PHYS(x) ((x) + 0xac) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_OFFS (0xac) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_ADDR(x) ((x) + 0xb0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_PHYS(x) ((x) + 0xb0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_OFFS (0xb0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_ADDR(x) ((x) + 0xb4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_PHYS(x) ((x) + 0xb4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_OFFS (0xb4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_ADDR(x) ((x) + 0xb8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_PHYS(x) ((x) + 0xb8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_OFFS (0xb8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_ADDR(x) ((x) + 0xbc) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_PHYS(x) ((x) + 0xbc) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_OFFS (0xbc) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_ADDR(x) ((x) + 0xc0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_PHYS(x) ((x) + 0xc0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_OFFS (0xc0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_ADDR(x) ((x) + 0xc4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_PHYS(x) ((x) + 0xc4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_OFFS (0xc4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_ADDR(x) ((x) + 0xc8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_PHYS(x) ((x) + 0xc8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_OFFS (0xc8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_ADDR(x) ((x) + 0xcc) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_PHYS(x) ((x) + 0xcc) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_OFFS (0xcc) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_ADDR(x) ((x) + 0xd0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_PHYS(x) ((x) + 0xd0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_OFFS (0xd0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_RMSK 0xffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_VALUE_1_BMSK 0xff00 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_VALUE_1_SHFT 8 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_VALUE_0_BMSK 0xff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_VALUE_0_SHFT 0 + +#define HWIO_CP_R0_MISC_CONFIG_ADDR(x) ((x) + 0xd4) +#define HWIO_CP_R0_MISC_CONFIG_PHYS(x) ((x) + 0xd4) +#define HWIO_CP_R0_MISC_CONFIG_OFFS (0xd4) +#define HWIO_CP_R0_MISC_CONFIG_RMSK 0x1fffffff +#define HWIO_CP_R0_MISC_CONFIG_POR 0x0003c110 +#define HWIO_CP_R0_MISC_CONFIG_POR_RMSK 0xffffffff +#define HWIO_CP_R0_MISC_CONFIG_ATTR 0x3 +#define HWIO_CP_R0_MISC_CONFIG_IN(x) \ + in_dword(HWIO_CP_R0_MISC_CONFIG_ADDR(x)) +#define HWIO_CP_R0_MISC_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_MISC_CONFIG_ADDR(x), m) +#define HWIO_CP_R0_MISC_CONFIG_OUT(x, v) \ + out_dword(HWIO_CP_R0_MISC_CONFIG_ADDR(x),v) +#define HWIO_CP_R0_MISC_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_MISC_CONFIG_ADDR(x),m,v,HWIO_CP_R0_MISC_CONFIG_IN(x)) +#define HWIO_CP_R0_MISC_CONFIG_REPORT_FLOW_ID_OR_HASH_3_BMSK 0x10000000 +#define HWIO_CP_R0_MISC_CONFIG_REPORT_FLOW_ID_OR_HASH_3_SHFT 28 +#define HWIO_CP_R0_MISC_CONFIG_ETH_MIN_PACKET_LEN_BMSK 0xffff000 +#define HWIO_CP_R0_MISC_CONFIG_ETH_MIN_PACKET_LEN_SHFT 12 +#define HWIO_CP_R0_MISC_CONFIG_TIMEOUT_EN_BMSK 0x800 +#define HWIO_CP_R0_MISC_CONFIG_TIMEOUT_EN_SHFT 11 +#define HWIO_CP_R0_MISC_CONFIG_ENABLE_8870_BMSK 0x400 +#define HWIO_CP_R0_MISC_CONFIG_ENABLE_8870_SHFT 10 +#define HWIO_CP_R0_MISC_CONFIG_ENABLE_C9D1_BMSK 0x200 +#define HWIO_CP_R0_MISC_CONFIG_ENABLE_C9D1_SHFT 9 +#define HWIO_CP_R0_MISC_CONFIG_VLAN_LLC_FOR_802_3_BMSK 0x100 +#define HWIO_CP_R0_MISC_CONFIG_VLAN_LLC_FOR_802_3_SHFT 8 +#define HWIO_CP_R0_MISC_CONFIG_IP_DA_SA_PREFIX_BMSK 0xc0 +#define HWIO_CP_R0_MISC_CONFIG_IP_DA_SA_PREFIX_SHFT 6 +#define HWIO_CP_R0_MISC_CONFIG_UDP_LITE_PARSE_EN_BMSK 0x20 +#define HWIO_CP_R0_MISC_CONFIG_UDP_LITE_PARSE_EN_SHFT 5 +#define HWIO_CP_R0_MISC_CONFIG_TPID_BITMAP_VALUE_BMSK 0x1f +#define HWIO_CP_R0_MISC_CONFIG_TPID_BITMAP_VALUE_SHFT 0 + +#define HWIO_CP_R0_WATCHDOG_TIMER_ADDR(x) ((x) + 0xd8) +#define HWIO_CP_R0_WATCHDOG_TIMER_PHYS(x) ((x) + 0xd8) +#define HWIO_CP_R0_WATCHDOG_TIMER_OFFS (0xd8) +#define HWIO_CP_R0_WATCHDOG_TIMER_RMSK 0xffffffff +#define HWIO_CP_R0_WATCHDOG_TIMER_POR 0x00000000 +#define HWIO_CP_R0_WATCHDOG_TIMER_POR_RMSK 0xffffffff +#define HWIO_CP_R0_WATCHDOG_TIMER_ATTR 0x3 +#define HWIO_CP_R0_WATCHDOG_TIMER_IN(x) \ + in_dword(HWIO_CP_R0_WATCHDOG_TIMER_ADDR(x)) +#define HWIO_CP_R0_WATCHDOG_TIMER_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_WATCHDOG_TIMER_ADDR(x), m) +#define HWIO_CP_R0_WATCHDOG_TIMER_OUT(x, v) \ + out_dword(HWIO_CP_R0_WATCHDOG_TIMER_ADDR(x),v) +#define HWIO_CP_R0_WATCHDOG_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_WATCHDOG_TIMER_ADDR(x),m,v,HWIO_CP_R0_WATCHDOG_TIMER_IN(x)) +#define HWIO_CP_R0_WATCHDOG_TIMER_VALUE_BMSK 0xfffffffe +#define HWIO_CP_R0_WATCHDOG_TIMER_VALUE_SHFT 1 +#define HWIO_CP_R0_WATCHDOG_TIMER_ENABLE_BMSK 0x1 +#define HWIO_CP_R0_WATCHDOG_TIMER_ENABLE_SHFT 0 + +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x500) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x500) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x500) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xffffffff +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword(HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 17 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 2 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 1 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0 + +#define HWIO_CP_R1_SM_STATES_ADDR(x) ((x) + 0x504) +#define HWIO_CP_R1_SM_STATES_PHYS(x) ((x) + 0x504) +#define HWIO_CP_R1_SM_STATES_OFFS (0x504) +#define HWIO_CP_R1_SM_STATES_RMSK 0xffffffff +#define HWIO_CP_R1_SM_STATES_POR 0x00000000 +#define HWIO_CP_R1_SM_STATES_POR_RMSK 0xffffffff +#define HWIO_CP_R1_SM_STATES_ATTR 0x1 +#define HWIO_CP_R1_SM_STATES_IN(x) \ + in_dword(HWIO_CP_R1_SM_STATES_ADDR(x)) +#define HWIO_CP_R1_SM_STATES_INM(x, m) \ + in_dword_masked(HWIO_CP_R1_SM_STATES_ADDR(x), m) +#define HWIO_CP_R1_SM_STATES_MISC_BMSK 0xfffffc00 +#define HWIO_CP_R1_SM_STATES_MISC_SHFT 10 +#define HWIO_CP_R1_SM_STATES_STATE_INFO_BMSK 0x3e0 +#define HWIO_CP_R1_SM_STATES_STATE_INFO_SHFT 5 +#define HWIO_CP_R1_SM_STATES_STATE_MAIN_BMSK 0x1f +#define HWIO_CP_R1_SM_STATES_STATE_MAIN_SHFT 0 + +#define HWIO_CP_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x508) +#define HWIO_CP_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x508) +#define HWIO_CP_R1_END_OF_TEST_CHECK_OFFS (0x508) +#define HWIO_CP_R1_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_CP_R1_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_CP_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_CP_R1_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_CP_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_CP_R1_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_CP_R1_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_CP_R1_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_CP_R1_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_CP_R1_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_CP_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_CP_R1_END_OF_TEST_CHECK_IN(x)) +#define HWIO_CP_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_CP_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: UMAC_NOC + *--------------------------------------------------------------------------*/ + +#define UMAC_NOC_REG_BASE (UMAC_NOC_BASE + 0x00000000) +#define UMAC_NOC_REG_BASE_SIZE 0x4200 +#define UMAC_NOC_REG_BASE_USED 0x4180 +#define UMAC_NOC_REG_BASE_PHYS (UMAC_NOC_BASE_PHYS + 0x00000000) +#define UMAC_NOC_REG_BASE_OFFS 0x00000000 + +#define HWIO_UMAC_NOC_ERL_SWID_LOW_ADDR(x) ((x) + 0x0) +#define HWIO_UMAC_NOC_ERL_SWID_LOW_PHYS(x) ((x) + 0x0) +#define HWIO_UMAC_NOC_ERL_SWID_LOW_OFFS (0x0) +#define HWIO_UMAC_NOC_ERL_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_ERL_SWID_LOW_POR 0x000124c9 +#define HWIO_UMAC_NOC_ERL_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_ERL_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_ERL_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_ERL_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_ADDR(x) ((x) + 0x4) +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_PHYS(x) ((x) + 0x4) +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_OFFS (0x4) +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ADDR(x) ((x) + 0x8) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_PHYS(x) ((x) + 0x8) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_OFFS (0x8) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_RMSK 0xff03 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_POR 0x00000003 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_ERL_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ERRIGNORE_BMSK 0xff00 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ERRIGNORE_SHFT 8 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_STALLEN_BMSK 0x2 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_STALLEN_SHFT 1 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_FAULTEN_BMSK 0x1 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_FAULTEN_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_ADDR(x) ((x) + 0x10) +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_PHYS(x) ((x) + 0x10) +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_OFFS (0x10) +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRVLD_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRVLD_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_ERRVLD_BMSK 0x1 +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_ERRVLD_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_ADDR(x) ((x) + 0x18) +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_PHYS(x) ((x) + 0x18) +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_OFFS (0x18) +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_ERL_ERRCLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_ERRCLR_BMSK 0x1 +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_ERRCLR_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ADDR(x) ((x) + 0x20) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_PHYS(x) ((x) + 0x20) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_OFFS (0x20) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_RMSK 0xf3f7777 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ATOPC_BMSK 0xf000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ATOPC_SHFT 24 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ADDRSPACE_BMSK 0x3f0000 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ADDRSPACE_SHFT 16 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_TRTYPE_BMSK 0x7000 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_TRTYPE_SHFT 12 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ERRCODE_BMSK 0x700 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ERRCODE_SHFT 8 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_OPC_BMSK 0x70 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_OPC_SHFT 4 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_NONSECURE_BMSK 0x4 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_NONSECURE_SHFT 2 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_WORDERROR_BMSK 0x2 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_WORDERROR_SHFT 1 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_LOGINFOVLD_BMSK 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_LOGINFOVLD_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_ADDR(x) ((x) + 0x24) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_PHYS(x) ((x) + 0x24) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_OFFS (0x24) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_RMSK 0xff03ff +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_REDIRECT_BMSK 0xff0000 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_REDIRECT_SHFT 16 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_LEN1_BMSK 0x3ff +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_LEN1_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_ADDR(x) ((x) + 0x28) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_PHYS(x) ((x) + 0x28) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_OFFS (0x28) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_PATH_BMSK 0xffff +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_PATH_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_ADDR(x) ((x) + 0x2c) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_PHYS(x) ((x) + 0x2c) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_OFFS (0x2c) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_RMSK 0x3ffff +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_EXTID_BMSK 0x3ffff +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_EXTID_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_ADDR(x) ((x) + 0x30) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_PHYS(x) ((x) + 0x30) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_OFFS (0x30) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_ERRLOG2_LSB_BMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_ERRLOG2_LSB_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_ADDR(x) ((x) + 0x34) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_PHYS(x) ((x) + 0x34) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_OFFS (0x34) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_RMSK 0x7fffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_ERRLOG2_MSB_BMSK 0x7fffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_ERRLOG2_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_ADDR(x) ((x) + 0x38) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_PHYS(x) ((x) + 0x38) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_OFFS (0x38) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_ERRLOG3_LSB_BMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_ERRLOG3_LSB_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_ADDR(x) ((x) + 0x3c) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_PHYS(x) ((x) + 0x3c) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_OFFS (0x3c) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_ERRLOG3_MSB_BMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_ERRLOG3_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_DCD_SWID_LOW_ADDR(x) ((x) + 0x100) +#define HWIO_UMAC_NOC_DCD_SWID_LOW_PHYS(x) ((x) + 0x100) +#define HWIO_UMAC_NOC_DCD_SWID_LOW_OFFS (0x100) +#define HWIO_UMAC_NOC_DCD_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_DCD_SWID_LOW_POR 0x0000e93b +#define HWIO_UMAC_NOC_DCD_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_DCD_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_DCD_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_DCD_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_DCD_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_DCD_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_DCD_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_DCD_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_DCD_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_ADDR(x) ((x) + 0x104) +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_PHYS(x) ((x) + 0x104) +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_OFFS (0x104) +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_DCD_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_DCD_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_ADDR(x) ((x) + 0x108) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_PHYS(x) ((x) + 0x108) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_OFFS (0x108) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_RMSK 0x7 +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_DCD_MAXDIV_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_DCD_MAXDIV_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_DCD_MAXDIV_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_DCD_MAXDIV_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_DCD_MAXDIV_LOW_IN(x)) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_MAXDIV_BMSK 0x7 +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_MAXDIV_SHFT 0 + +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_ADDR(x) ((x) + 0x110) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_PHYS(x) ((x) + 0x110) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_OFFS (0x110) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_POR 0x00000100 +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_IN(x)) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_FIRSTHYSTCNT_BMSK 0xffff +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_FIRSTHYSTCNT_SHFT 0 + +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_ADDR(x) ((x) + 0x118) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_PHYS(x) ((x) + 0x118) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_OFFS (0x118) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_RMSK 0xfff +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_POR 0x00000080 +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_IN(x)) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_NEXTHYSTCNT_BMSK 0xfff +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_NEXTHYSTCNT_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_ADDR(x) ((x) + 0x200) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_PHYS(x) ((x) + 0x200) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_OFFS (0x200) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_POR 0x000e3a95 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_ADDR(x) ((x) + 0x204) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_PHYS(x) ((x) + 0x204) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_OFFS (0x204) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_ADDR(x) ((x) + 0x240) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PHYS(x) ((x) + 0x240) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_OFFS (0x240) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_IN(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT15_BMSK 0x8000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT15_SHFT 15 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT14_BMSK 0x4000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT14_SHFT 14 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT12_BMSK 0x1000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT12_SHFT 12 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT7_BMSK 0x80 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT7_SHFT 7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_ADDR(x) ((x) + 0x248) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PHYS(x) ((x) + 0x248) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_OFFS (0x248) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT15_BMSK 0x8000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT15_SHFT 15 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT14_BMSK 0x4000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT14_SHFT 14 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT12_BMSK 0x1000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT12_SHFT 12 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT7_BMSK 0x80 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT7_SHFT 7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_ADDR(x) ((x) + 0x280) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PHYS(x) ((x) + 0x280) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_OFFS (0x280) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_RMSK 0x2f7e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT1_SHFT 1 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_ADDR(x) ((x) + 0x288) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PHYS(x) ((x) + 0x288) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_OFFS (0x288) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_RMSK 0x2f7e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT1_SHFT 1 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_ADDR(x) ((x) + 0x290) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PHYS(x) ((x) + 0x290) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_OFFS (0x290) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_RMSK 0x2f7e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_POR 0x00002f7e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT1_SHFT 1 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_ADDR(x) ((x) + 0x300) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PHYS(x) ((x) + 0x300) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_OFFS (0x300) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_RMSK 0x2f7e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT1_SHFT 1 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_ADDR(x) ((x) + 0x600) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_PHYS(x) ((x) + 0x600) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_OFFS (0x600) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_POR 0x000e9029 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_ADDR(x) ((x) + 0x604) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_PHYS(x) ((x) + 0x604) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_OFFS (0x604) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_ADDR(x) ((x) + 0x640) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PHYS(x) ((x) + 0x640) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_OFFS (0x640) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_IN(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_ADDR(x) ((x) + 0x648) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PHYS(x) ((x) + 0x648) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_OFFS (0x648) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_ADDR(x) ((x) + 0x680) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PHYS(x) ((x) + 0x680) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_OFFS (0x680) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_RMSK 0xfffff7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT23_BMSK 0x800000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT23_SHFT 23 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT22_BMSK 0x400000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT22_SHFT 22 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT21_BMSK 0x200000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT21_SHFT 21 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT20_BMSK 0x100000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT20_SHFT 20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT19_BMSK 0x80000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT19_SHFT 19 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT18_BMSK 0x40000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT18_SHFT 18 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT17_BMSK 0x20000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT17_SHFT 17 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT16_BMSK 0x10000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT16_SHFT 16 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT15_BMSK 0x8000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT15_SHFT 15 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT14_BMSK 0x4000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT14_SHFT 14 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT12_BMSK 0x1000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT12_SHFT 12 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT7_BMSK 0x80 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT7_SHFT 7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_ADDR(x) ((x) + 0x688) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PHYS(x) ((x) + 0x688) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_OFFS (0x688) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_RMSK 0xfffff7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT23_BMSK 0x800000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT23_SHFT 23 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT22_BMSK 0x400000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT22_SHFT 22 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT21_BMSK 0x200000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT21_SHFT 21 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT20_BMSK 0x100000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT20_SHFT 20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT19_BMSK 0x80000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT19_SHFT 19 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT18_BMSK 0x40000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT18_SHFT 18 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT17_BMSK 0x20000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT17_SHFT 17 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT16_BMSK 0x10000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT16_SHFT 16 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT15_BMSK 0x8000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT15_SHFT 15 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT14_BMSK 0x4000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT14_SHFT 14 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT12_BMSK 0x1000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT12_SHFT 12 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT7_BMSK 0x80 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT7_SHFT 7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_ADDR(x) ((x) + 0x690) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PHYS(x) ((x) + 0x690) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_OFFS (0x690) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_RMSK 0xfffff7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_POR 0x00000001 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT23_BMSK 0x800000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT23_SHFT 23 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT22_BMSK 0x400000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT22_SHFT 22 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT21_BMSK 0x200000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT21_SHFT 21 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT20_BMSK 0x100000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT20_SHFT 20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT19_BMSK 0x80000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT19_SHFT 19 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT18_BMSK 0x40000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT18_SHFT 18 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT17_BMSK 0x20000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT17_SHFT 17 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT16_BMSK 0x10000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT16_SHFT 16 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT15_BMSK 0x8000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT15_SHFT 15 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT14_BMSK 0x4000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT14_SHFT 14 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT12_BMSK 0x1000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT12_SHFT 12 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT7_BMSK 0x80 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT7_SHFT 7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_ADDR(x) ((x) + 0x700) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PHYS(x) ((x) + 0x700) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_OFFS (0x700) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_RMSK 0xffff6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT19_BMSK 0x80000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT19_SHFT 19 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT18_BMSK 0x40000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT18_SHFT 18 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT17_BMSK 0x20000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT17_SHFT 17 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT16_BMSK 0x10000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT16_SHFT 16 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT15_BMSK 0x8000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT15_SHFT 15 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT14_BMSK 0x4000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT14_SHFT 14 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT12_BMSK 0x1000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT12_SHFT 12 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT7_BMSK 0x80 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT7_SHFT 7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT1_SHFT 1 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_ADDR(x) ((x) + 0x800) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_PHYS(x) ((x) + 0x800) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_OFFS (0x800) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_POR 0x00083dc8 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_ADDR(x) ((x) + 0x804) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_PHYS(x) ((x) + 0x804) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_OFFS (0x804) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_ADDR(x) ((x) + 0x808) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_PHYS(x) ((x) + 0x808) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_OFFS (0x808) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_RMSK 0x1003f3f +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_POR 0x00000008 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_URGDELAY_BMSK 0x3f00 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_URGDELAY_SHFT 8 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_BMSK 0x30 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_SHFT 4 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_SLVURGMSGEN_BMSK 0x8 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_SLVURGMSGEN_SHFT 3 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_STOP_BMSK 0x4 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_STOP_SHFT 2 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_SHAPEREN_BMSK 0x2 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_SHAPEREN_SHFT 1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_BWLIMITEN_BMSK 0x1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_BWLIMITEN_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_ADDR(x) ((x) + 0x810) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_PHYS(x) ((x) + 0x810) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_OFFS (0x810) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_RMSK 0xfff003f +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_POR 0x00f00000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_BMSK 0xfff0000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_SHFT 16 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_PENDING_BMSK 0x3f +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_PENDING_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_ADDR(x) ((x) + 0x818) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_PHYS(x) ((x) + 0x818) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_OFFS (0x818) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_POR 0x00800266 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_ADDR(x) ((x) + 0x820) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_PHYS(x) ((x) + 0x820) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_OFFS (0x820) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_RMSK 0x1f1f1f1f +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL3_BMSK 0x1f000000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL3_SHFT 24 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL2_BMSK 0x1f0000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL2_SHFT 16 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL1_BMSK 0x1f00 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL1_SHFT 8 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL0_BMSK 0x1f +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL0_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_ADDR(x) ((x) + 0x840) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_PHYS(x) ((x) + 0x840) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_OFFS (0x840) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_RMSK 0x3303 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_BMSK 0x3000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_SHFT 12 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_BMSK 0x300 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_SHFT 8 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_ADDR(x) ((x) + 0x848) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_PHYS(x) ((x) + 0x848) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_OFFS (0x848) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_POR 0x00400133 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_ADDR(x) ((x) + 0x880) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_PHYS(x) ((x) + 0x880) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_OFFS (0x880) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_POR 0x00084b7e +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_ADDR(x) ((x) + 0x884) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_PHYS(x) ((x) + 0x884) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_OFFS (0x884) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_ADDR(x) ((x) + 0x888) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_PHYS(x) ((x) + 0x888) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_OFFS (0x888) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_RMSK 0x1003f37 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_URGDELAY_BMSK 0x3f00 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_URGDELAY_SHFT 8 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_BMSK 0x30 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_SHFT 4 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_STOP_BMSK 0x4 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_STOP_SHFT 2 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_SHAPEREN_BMSK 0x2 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_SHAPEREN_SHFT 1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_BWLIMITEN_BMSK 0x1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_BWLIMITEN_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_ADDR(x) ((x) + 0x890) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_PHYS(x) ((x) + 0x890) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_OFFS (0x890) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_RMSK 0xfff001f +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_POR 0x00f00000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_BMSK 0xfff0000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_SHFT 16 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_PENDING_BMSK 0x1f +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_PENDING_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_ADDR(x) ((x) + 0x898) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_PHYS(x) ((x) + 0x898) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_OFFS (0x898) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_POR 0x00c000cc +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_ADDR(x) ((x) + 0x8a0) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_PHYS(x) ((x) + 0x8a0) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_OFFS (0x8a0) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_RMSK 0x1f1f1f1f +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL3_BMSK 0x1f000000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL3_SHFT 24 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL2_BMSK 0x1f0000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL2_SHFT 16 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL1_BMSK 0x1f00 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL1_SHFT 8 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL0_BMSK 0x1f +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL0_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_ADDR(x) ((x) + 0x8c0) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_PHYS(x) ((x) + 0x8c0) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_OFFS (0x8c0) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_RMSK 0x3303 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_BMSK 0x3000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_SHFT 12 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_BMSK 0x300 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_SHFT 8 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_ADDR(x) ((x) + 0x8c8) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_PHYS(x) ((x) + 0x8c8) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_OFFS (0x8c8) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_POR 0x00600066 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_ADDR(x) ((x) + 0x900) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_PHYS(x) ((x) + 0x900) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_OFFS (0x900) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_POR 0x00085ef3 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_ADDR(x) ((x) + 0x904) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_PHYS(x) ((x) + 0x904) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_OFFS (0x904) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_ADDR(x) ((x) + 0x908) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_PHYS(x) ((x) + 0x908) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_OFFS (0x908) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_RMSK 0x1003f37 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_URGDELAY_BMSK 0x3f00 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_URGDELAY_SHFT 8 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_BMSK 0x30 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_SHFT 4 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_STOP_BMSK 0x4 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_STOP_SHFT 2 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_SHAPEREN_BMSK 0x2 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_SHAPEREN_SHFT 1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_BWLIMITEN_BMSK 0x1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_BWLIMITEN_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_ADDR(x) ((x) + 0x910) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_PHYS(x) ((x) + 0x910) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_OFFS (0x910) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_RMSK 0xfff003f +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_POR 0x00f00000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_BMSK 0xfff0000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_SHFT 16 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_PENDING_BMSK 0x3f +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_PENDING_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_ADDR(x) ((x) + 0x918) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_PHYS(x) ((x) + 0x918) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_OFFS (0x918) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_POR 0x00c00266 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_ADDR(x) ((x) + 0x920) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_PHYS(x) ((x) + 0x920) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_OFFS (0x920) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_RMSK 0x3f3f3f3f +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL3_BMSK 0x3f000000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL3_SHFT 24 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL2_BMSK 0x3f0000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL2_SHFT 16 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL1_BMSK 0x3f00 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL1_SHFT 8 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL0_BMSK 0x3f +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL0_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_ADDR(x) ((x) + 0x940) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_PHYS(x) ((x) + 0x940) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_OFFS (0x940) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_RMSK 0x3303 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_BMSK 0x3000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_SHFT 12 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_BMSK 0x300 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_SHFT 8 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_ADDR(x) ((x) + 0x948) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_PHYS(x) ((x) + 0x948) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_OFFS (0x948) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_POR 0x00600133 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_ADDR(x) ((x) + 0x980) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_PHYS(x) ((x) + 0x980) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_OFFS (0x980) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_POR 0x0008cb8d +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_ADDR(x) ((x) + 0x984) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_PHYS(x) ((x) + 0x984) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_OFFS (0x984) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_ADDR(x) ((x) + 0x988) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_PHYS(x) ((x) + 0x988) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_OFFS (0x988) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_RMSK 0x1003f37 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_URGDELAY_BMSK 0x3f00 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_URGDELAY_SHFT 8 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_BMSK 0x30 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_SHFT 4 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_STOP_BMSK 0x4 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_STOP_SHFT 2 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_SHAPEREN_BMSK 0x2 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_SHAPEREN_SHFT 1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_BWLIMITEN_BMSK 0x1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_BWLIMITEN_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_ADDR(x) ((x) + 0x990) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_PHYS(x) ((x) + 0x990) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_OFFS (0x990) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_RMSK 0xfff000f +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_POR 0x00f00000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_BMSK 0xfff0000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_SHFT 16 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_PENDING_BMSK 0xf +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_PENDING_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_ADDR(x) ((x) + 0x998) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_PHYS(x) ((x) + 0x998) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_OFFS (0x998) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_POR 0x00c00266 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_ADDR(x) ((x) + 0x9a0) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_PHYS(x) ((x) + 0x9a0) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_OFFS (0x9a0) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_RMSK 0x7070707 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL3_BMSK 0x7000000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL3_SHFT 24 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL2_BMSK 0x70000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL2_SHFT 16 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL1_BMSK 0x700 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL1_SHFT 8 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL0_BMSK 0x7 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL0_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_ADDR(x) ((x) + 0x9c0) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_PHYS(x) ((x) + 0x9c0) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_OFFS (0x9c0) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_RMSK 0x3303 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_BMSK 0x3000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_SHFT 12 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_BMSK 0x300 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_SHFT 8 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_ADDR(x) ((x) + 0x9c8) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_PHYS(x) ((x) + 0x9c8) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_OFFS (0x9c8) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_POR 0x00600133 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_STP_SWID_LOW_ADDR(x) ((x) + 0xe00) +#define HWIO_UMAC_NOC_STP_SWID_LOW_PHYS(x) ((x) + 0xe00) +#define HWIO_UMAC_NOC_STP_SWID_LOW_OFFS (0xe00) +#define HWIO_UMAC_NOC_STP_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_STP_SWID_LOW_POR 0x000ce93b +#define HWIO_UMAC_NOC_STP_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_STP_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_STP_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_STP_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_STP_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_STP_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_STP_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_STP_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_STP_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_STP_SWID_HIGH_ADDR(x) ((x) + 0xe04) +#define HWIO_UMAC_NOC_STP_SWID_HIGH_PHYS(x) ((x) + 0xe04) +#define HWIO_UMAC_NOC_STP_SWID_HIGH_OFFS (0xe04) +#define HWIO_UMAC_NOC_STP_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_STP_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_STP_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_STP_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_STP_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_STP_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_STP_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_ADDR(x) ((x) + 0xe08) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_PHYS(x) ((x) + 0xe08) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_OFFS (0xe08) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_STP_ATBEN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_STP_ATBEN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_STP_ATBEN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_STP_ATBEN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_STP_ATBEN_LOW_IN(x)) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_ATBEN_BMSK 0x1 +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_ATBEN_SHFT 0 + +#define HWIO_UMAC_NOC_STP_ATBID_LOW_ADDR(x) ((x) + 0xe10) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_PHYS(x) ((x) + 0xe10) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_OFFS (0xe10) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_RMSK 0x7f +#define HWIO_UMAC_NOC_STP_ATBID_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_STP_ATBID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_ATBID_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_STP_ATBID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_STP_ATBID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_STP_ATBID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_STP_ATBID_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_STP_ATBID_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_STP_ATBID_LOW_IN(x)) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_ATBID_BMSK 0x7f +#define HWIO_UMAC_NOC_STP_ATBID_LOW_ATBID_SHFT 0 + +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_ADDR(x) ((x) + 0xe18) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_PHYS(x) ((x) + 0xe18) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_OFFS (0xe18) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_RMSK 0x3ff +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_IN(x)) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_SYNCOUTPERIOD_BMSK 0x3ff +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_SYNCOUTPERIOD_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_ADDR(x) ((x) + 0x1000) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_PHYS(x) ((x) + 0x1000) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_OFFS (0x1000) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_POR 0x0012178b +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_ADDR(x) ((x) + 0x1004) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_PHYS(x) ((x) + 0x1004) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_OFFS (0x1004) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ADDR(x) ((x) + 0x1008) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_PHYS(x) ((x) + 0x1008) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_OFFS (0x1008) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_RMSK 0x2f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_BMSK 0x20 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_SHFT 5 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ALARMEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ALARMEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_DUMPEN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_DUMPEN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_GLBEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_GLBEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_ADDR(x) ((x) + 0x1010) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_PHYS(x) ((x) + 0x1010) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_OFFS (0x1010) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_ADDR(x) ((x) + 0x1018) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_PHYS(x) ((x) + 0x1018) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_OFFS (0x1018) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_ADDR(x) ((x) + 0x1020) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_PHYS(x) ((x) + 0x1020) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_OFFS (0x1020) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_ADDR(x) ((x) + 0x1028) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_PHYS(x) ((x) + 0x1028) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_OFFS (0x1028) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_ADDR(x) ((x) + 0x1030) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_PHYS(x) ((x) + 0x1030) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_OFFS (0x1030) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_RMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_PORTSEL_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_PORTSEL_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x) ((x) + 0x1100) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_PHYS(x) ((x) + 0x1100) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OFFS (0x1100) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x) ((x) + 0x1108) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_PHYS(x) ((x) + 0x1108) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OFFS (0x1108) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1120) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1120) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OFFS (0x1120) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1124) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1124) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OFFS (0x1124) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1128) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1128) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OFFS (0x1128) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x112c) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x112c) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OFFS (0x112c) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x) ((x) + 0x1138) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_PHYS(x) ((x) + 0x1138) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_OFFS (0x1138) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x) ((x) + 0x1140) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_PHYS(x) ((x) + 0x1140) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_OFFS (0x1140) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1178) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1178) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OFFS (0x1178) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1180) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1180) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OFFS (0x1180) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x) ((x) + 0x1200) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_PHYS(x) ((x) + 0x1200) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OFFS (0x1200) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x) ((x) + 0x1208) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_PHYS(x) ((x) + 0x1208) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OFFS (0x1208) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1220) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1220) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OFFS (0x1220) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1224) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1224) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OFFS (0x1224) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1228) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1228) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OFFS (0x1228) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x122c) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x122c) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OFFS (0x122c) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x) ((x) + 0x1238) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_PHYS(x) ((x) + 0x1238) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_OFFS (0x1238) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x) ((x) + 0x1240) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_PHYS(x) ((x) + 0x1240) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_OFFS (0x1240) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1278) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1278) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OFFS (0x1278) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1280) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1280) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OFFS (0x1280) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_ADDR(x) ((x) + 0x1400) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_PHYS(x) ((x) + 0x1400) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_OFFS (0x1400) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_POR 0x0012dc84 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_ADDR(x) ((x) + 0x1404) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_PHYS(x) ((x) + 0x1404) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_OFFS (0x1404) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ADDR(x) ((x) + 0x1408) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_PHYS(x) ((x) + 0x1408) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_OFFS (0x1408) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_RMSK 0x2f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_BMSK 0x20 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_SHFT 5 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ALARMEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ALARMEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_DUMPEN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_DUMPEN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_GLBEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_GLBEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_ADDR(x) ((x) + 0x1410) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_PHYS(x) ((x) + 0x1410) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_OFFS (0x1410) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_ADDR(x) ((x) + 0x1418) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_PHYS(x) ((x) + 0x1418) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_OFFS (0x1418) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_ADDR(x) ((x) + 0x1420) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_PHYS(x) ((x) + 0x1420) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_OFFS (0x1420) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_ADDR(x) ((x) + 0x1428) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_PHYS(x) ((x) + 0x1428) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_OFFS (0x1428) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_ADDR(x) ((x) + 0x1430) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_PHYS(x) ((x) + 0x1430) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_OFFS (0x1430) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_RMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_PORTSEL_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_PORTSEL_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x) ((x) + 0x1500) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_PHYS(x) ((x) + 0x1500) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OFFS (0x1500) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x) ((x) + 0x1508) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_PHYS(x) ((x) + 0x1508) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OFFS (0x1508) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1520) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1520) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OFFS (0x1520) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1524) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1524) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OFFS (0x1524) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1528) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1528) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OFFS (0x1528) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x152c) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x152c) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OFFS (0x152c) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x) ((x) + 0x1538) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_PHYS(x) ((x) + 0x1538) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_OFFS (0x1538) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x) ((x) + 0x1540) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_PHYS(x) ((x) + 0x1540) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_OFFS (0x1540) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1578) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1578) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OFFS (0x1578) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1580) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1580) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OFFS (0x1580) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x) ((x) + 0x1600) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_PHYS(x) ((x) + 0x1600) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OFFS (0x1600) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x) ((x) + 0x1608) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_PHYS(x) ((x) + 0x1608) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OFFS (0x1608) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1620) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1620) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OFFS (0x1620) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1624) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1624) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OFFS (0x1624) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1628) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1628) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OFFS (0x1628) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x162c) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x162c) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OFFS (0x162c) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x) ((x) + 0x1638) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_PHYS(x) ((x) + 0x1638) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_OFFS (0x1638) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x) ((x) + 0x1640) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_PHYS(x) ((x) + 0x1640) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_OFFS (0x1640) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1678) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1678) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OFFS (0x1678) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1680) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1680) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OFFS (0x1680) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_ADDR(x) ((x) + 0x1800) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_PHYS(x) ((x) + 0x1800) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_OFFS (0x1800) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_POR 0x0012178b +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_ADDR(x) ((x) + 0x1804) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_PHYS(x) ((x) + 0x1804) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_OFFS (0x1804) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ADDR(x) ((x) + 0x1808) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_PHYS(x) ((x) + 0x1808) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_OFFS (0x1808) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_RMSK 0x2f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_BMSK 0x20 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_SHFT 5 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ALARMEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ALARMEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_DUMPEN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_DUMPEN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_GLBEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_GLBEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_ADDR(x) ((x) + 0x1810) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_PHYS(x) ((x) + 0x1810) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_OFFS (0x1810) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_ADDR(x) ((x) + 0x1818) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_PHYS(x) ((x) + 0x1818) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_OFFS (0x1818) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_ADDR(x) ((x) + 0x1820) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_PHYS(x) ((x) + 0x1820) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_OFFS (0x1820) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_ADDR(x) ((x) + 0x1828) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_PHYS(x) ((x) + 0x1828) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_OFFS (0x1828) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_ADDR(x) ((x) + 0x1830) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_PHYS(x) ((x) + 0x1830) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_OFFS (0x1830) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_RMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_PORTSEL_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_PORTSEL_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x) ((x) + 0x1900) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_PHYS(x) ((x) + 0x1900) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OFFS (0x1900) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x) ((x) + 0x1908) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_PHYS(x) ((x) + 0x1908) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OFFS (0x1908) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1920) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1920) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OFFS (0x1920) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1924) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1924) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OFFS (0x1924) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1928) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1928) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OFFS (0x1928) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x192c) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x192c) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OFFS (0x192c) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x) ((x) + 0x1938) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_PHYS(x) ((x) + 0x1938) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_OFFS (0x1938) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x) ((x) + 0x1940) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_PHYS(x) ((x) + 0x1940) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_OFFS (0x1940) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1978) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1978) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OFFS (0x1978) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1980) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1980) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OFFS (0x1980) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x) ((x) + 0x1a00) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_PHYS(x) ((x) + 0x1a00) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OFFS (0x1a00) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x) ((x) + 0x1a08) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_PHYS(x) ((x) + 0x1a08) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OFFS (0x1a08) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1a20) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1a20) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OFFS (0x1a20) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1a24) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1a24) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OFFS (0x1a24) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1a28) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1a28) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OFFS (0x1a28) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x1a2c) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x1a2c) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OFFS (0x1a2c) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x) ((x) + 0x1a38) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_PHYS(x) ((x) + 0x1a38) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_OFFS (0x1a38) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x) ((x) + 0x1a40) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_PHYS(x) ((x) + 0x1a40) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_OFFS (0x1a40) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1a78) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1a78) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OFFS (0x1a78) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1a80) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1a80) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OFFS (0x1a80) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_ADDR(x) ((x) + 0x1c00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_PHYS(x) ((x) + 0x1c00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_OFFS (0x1c00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_POR 0x0012dc84 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_ADDR(x) ((x) + 0x1c04) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_PHYS(x) ((x) + 0x1c04) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_OFFS (0x1c04) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ADDR(x) ((x) + 0x1c08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_PHYS(x) ((x) + 0x1c08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_OFFS (0x1c08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_RMSK 0x2f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_BMSK 0x20 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_SHFT 5 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ALARMEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ALARMEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_DUMPEN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_DUMPEN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_GLBEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_GLBEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_ADDR(x) ((x) + 0x1c10) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_PHYS(x) ((x) + 0x1c10) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_OFFS (0x1c10) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_ADDR(x) ((x) + 0x1c18) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_PHYS(x) ((x) + 0x1c18) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_OFFS (0x1c18) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_ADDR(x) ((x) + 0x1c20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_PHYS(x) ((x) + 0x1c20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_OFFS (0x1c20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_ADDR(x) ((x) + 0x1c28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_PHYS(x) ((x) + 0x1c28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_OFFS (0x1c28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_ADDR(x) ((x) + 0x1c30) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_PHYS(x) ((x) + 0x1c30) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_OFFS (0x1c30) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_RMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_PORTSEL_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_PORTSEL_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x) ((x) + 0x1d00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_PHYS(x) ((x) + 0x1d00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OFFS (0x1d00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x) ((x) + 0x1d08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_PHYS(x) ((x) + 0x1d08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OFFS (0x1d08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1d20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1d20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OFFS (0x1d20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1d24) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1d24) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OFFS (0x1d24) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1d28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1d28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OFFS (0x1d28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x1d2c) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x1d2c) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OFFS (0x1d2c) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x) ((x) + 0x1d38) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_PHYS(x) ((x) + 0x1d38) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_OFFS (0x1d38) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x) ((x) + 0x1d40) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_PHYS(x) ((x) + 0x1d40) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_OFFS (0x1d40) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1d78) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1d78) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OFFS (0x1d78) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1d80) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1d80) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OFFS (0x1d80) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x) ((x) + 0x1e00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_PHYS(x) ((x) + 0x1e00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OFFS (0x1e00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x) ((x) + 0x1e08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_PHYS(x) ((x) + 0x1e08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OFFS (0x1e08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1e20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1e20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OFFS (0x1e20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1e24) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1e24) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OFFS (0x1e24) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1e28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1e28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OFFS (0x1e28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x1e2c) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x1e2c) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OFFS (0x1e2c) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x) ((x) + 0x1e38) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_PHYS(x) ((x) + 0x1e38) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_OFFS (0x1e38) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x) ((x) + 0x1e40) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_PHYS(x) ((x) + 0x1e40) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_OFFS (0x1e40) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1e78) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1e78) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OFFS (0x1e78) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1e80) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1e80) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OFFS (0x1e80) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_EC_SWID_LOW_ADDR(x) ((x) + 0x3000) +#define HWIO_UMAC_NOC_EC_SWID_LOW_PHYS(x) ((x) + 0x3000) +#define HWIO_UMAC_NOC_EC_SWID_LOW_OFFS (0x3000) +#define HWIO_UMAC_NOC_EC_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_EC_SWID_LOW_POR 0x000203e0 +#define HWIO_UMAC_NOC_EC_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_EC_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_EC_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_EC_SWID_HIGH_ADDR(x) ((x) + 0x3004) +#define HWIO_UMAC_NOC_EC_SWID_HIGH_PHYS(x) ((x) + 0x3004) +#define HWIO_UMAC_NOC_EC_SWID_HIGH_OFFS (0x3004) +#define HWIO_UMAC_NOC_EC_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_EC_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_EC_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_ADDR(x) ((x) + 0x3008) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_PHYS(x) ((x) + 0x3008) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_OFFS (0x3008) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_RMSK 0x7 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_IGNORECTITRIGIN0_BMSK 0x4 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_IGNORECTITRIGIN0_SHFT 2 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_DUMPEN_BMSK 0x2 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_DUMPEN_SHFT 1 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_GLBEN_BMSK 0x1 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_GLBEN_SHFT 0 + +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_ADDR(x) ((x) + 0x3010) +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_PHYS(x) ((x) + 0x3010) +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_OFFS (0x3010) +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_DUMPGO_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_DUMPGO_BMSK 0x1 +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_DUMPGO_SHFT 0 + +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_ADDR(x) ((x) + 0x3018) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_PHYS(x) ((x) + 0x3018) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_OFFS (0x3018) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_DUMPPERIOD_BMSK 0x1f +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_DUMPPERIOD_SHFT 0 + +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_ADDR(x) ((x) + 0x3020) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_PHYS(x) ((x) + 0x3020) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_OFFS (0x3020) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_DUMPTHR_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_DUMPTHR_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_DUMPTHR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_DUMPTHR_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_DUMPTHR_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_DUMPTHR_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_DUMPTHR_SHFT 0 + +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ADDR(x) ((x) + 0x3028) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_PHYS(x) ((x) + 0x3028) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_OFFS (0x3028) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_ALARMMIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ALARMMIN_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ALARMMIN_SHFT 0 + +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ADDR(x) ((x) + 0x3030) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_PHYS(x) ((x) + 0x3030) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_OFFS (0x3030) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_ALARMMAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ALARMMAX_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ALARMMAX_SHFT 0 + +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_ADDR(x) ((x) + 0x3038) +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_PHYS(x) ((x) + 0x3038) +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_OFFS (0x3038) +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_ALARMSTATUS_BMSK 0x1 +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_ALARMSTATUS_SHFT 0 + +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_ADDR(x) ((x) + 0x3040) +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_PHYS(x) ((x) + 0x3040) +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_OFFS (0x3040) +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_ALARMCLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_ALARMCLR_BMSK 0x1 +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_ALARMCLR_SHFT 0 + +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_ADDR(x) ((x) + 0x3048) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_PHYS(x) ((x) + 0x3048) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_OFFS (0x3048) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_ALARMEN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_ALARMEN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_ALARMEN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_ALARMEN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_ALARMEN_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_ALARMEN_BMSK 0x1 +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_ALARMEN_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_ADDR(x) ((x) + 0x3050) +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_PHYS(x) ((x) + 0x3050) +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_OFFS (0x3050) +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_RMSK 0xff +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_COUNTERCLR_BMSK 0xff +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_COUNTERCLR_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ADDR(x) ((x) + 0x3100) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_PHYS(x) ((x) + 0x3100) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_OFFS (0x3100) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_ADDR(x) ((x) + 0x3140) +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_PHYS(x) ((x) + 0x3140) +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_OFFS (0x3140) +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_COUNTER0VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_COUNTER0VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ADDR(x) ((x) + 0x3180) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_PHYS(x) ((x) + 0x3180) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_OFFS (0x3180) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_ADDR(x) ((x) + 0x31c0) +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_PHYS(x) ((x) + 0x31c0) +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_OFFS (0x31c0) +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_COUNTER1VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_COUNTER1VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ADDR(x) ((x) + 0x3200) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_PHYS(x) ((x) + 0x3200) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_OFFS (0x3200) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_ADDR(x) ((x) + 0x3240) +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_PHYS(x) ((x) + 0x3240) +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_OFFS (0x3240) +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_COUNTER2VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_COUNTER2VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ADDR(x) ((x) + 0x3280) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_PHYS(x) ((x) + 0x3280) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_OFFS (0x3280) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_ADDR(x) ((x) + 0x32c0) +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_PHYS(x) ((x) + 0x32c0) +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_OFFS (0x32c0) +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_COUNTER3VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_COUNTER3VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ADDR(x) ((x) + 0x3300) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_PHYS(x) ((x) + 0x3300) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_OFFS (0x3300) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_ADDR(x) ((x) + 0x3340) +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_PHYS(x) ((x) + 0x3340) +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_OFFS (0x3340) +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_COUNTER4VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_COUNTER4VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ADDR(x) ((x) + 0x3380) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_PHYS(x) ((x) + 0x3380) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_OFFS (0x3380) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_ADDR(x) ((x) + 0x33c0) +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_PHYS(x) ((x) + 0x33c0) +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_OFFS (0x33c0) +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_COUNTER5VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_COUNTER5VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ADDR(x) ((x) + 0x3400) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_PHYS(x) ((x) + 0x3400) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_OFFS (0x3400) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_ADDR(x) ((x) + 0x3440) +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_PHYS(x) ((x) + 0x3440) +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_OFFS (0x3440) +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_COUNTER6VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_COUNTER6VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ADDR(x) ((x) + 0x3480) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_PHYS(x) ((x) + 0x3480) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_OFFS (0x3480) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_ADDR(x) ((x) + 0x34c0) +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_PHYS(x) ((x) + 0x34c0) +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_OFFS (0x34c0) +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_COUNTER7VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_COUNTER7VAL_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_ADDR(x) ((x) + 0x4000) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_PHYS(x) ((x) + 0x4000) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_OFFS (0x4000) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_POR 0x0003fc04 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_ADDR(x) ((x) + 0x4004) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_PHYS(x) ((x) + 0x4004) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_OFFS (0x4004) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_ADDR(x) ((x) + 0x4008) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_PHYS(x) ((x) + 0x4008) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_OFFS (0x4008) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_RMSK 0x33f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_POR 0x00000020 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_HISTPENDLAW_BMSK 0x300 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_HISTPENDLAW_SHFT 8 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_IGNORECTITRIGIN0_BMSK 0x20 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_IGNORECTITRIGIN0_SHFT 5 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_CTITRIGOUTEN_BMSK 0x10 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_CTITRIGOUTEN_SHFT 4 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_SCALEEN_BMSK 0x8 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_SCALEEN_SHFT 3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_DUMPEN_BMSK 0x4 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_DUMPEN_SHFT 2 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_MODE_BMSK 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_MODE_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_ADDR(x) ((x) + 0x4010) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_PHYS(x) ((x) + 0x4010) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_OFFS (0x4010) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_DUMPGO_BMSK 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_DUMPGO_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_ADDR(x) ((x) + 0x4018) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_PHYS(x) ((x) + 0x4018) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_OFFS (0x4018) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_POR 0x00001000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_DUMPTHR_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_DUMPTHR_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_ADDR(x) ((x) + 0x4020) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_PHYS(x) ((x) + 0x4020) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_OFFS (0x4020) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_RMSK 0xfffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_POR 0x00f0083f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_NOMINALFREQ_BMSK 0xfff0000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_NOMINALFREQ_SHFT 16 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_OFFSET_BMSK 0xff00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_OFFSET_SHFT 8 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_WIDTH_BMSK 0xff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_WIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_ADDR(x) ((x) + 0x4028) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_PHYS(x) ((x) + 0x4028) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_OFFS (0x4028) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_LATSUM_LSB_BMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_LATSUM_LSB_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_ADDR(x) ((x) + 0x402c) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_PHYS(x) ((x) + 0x402c) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_OFFS (0x402c) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_TRCNT_BMSK 0xffffff00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_TRCNT_SHFT 8 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_LATSUM_MSB_BMSK 0xff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_LATSUM_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_ADDR(x) ((x) + 0x4040) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_PHYS(x) ((x) + 0x4040) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_OFFS (0x4040) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_HISTBIN0_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_HISTBIN0_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_ADDR(x) ((x) + 0x4048) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_PHYS(x) ((x) + 0x4048) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_OFFS (0x4048) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_HISTBIN1_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_HISTBIN1_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_ADDR(x) ((x) + 0x4050) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_PHYS(x) ((x) + 0x4050) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_OFFS (0x4050) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_HISTBIN2_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_HISTBIN2_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_ADDR(x) ((x) + 0x4058) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_PHYS(x) ((x) + 0x4058) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_OFFS (0x4058) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_HISTBIN3_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_HISTBIN3_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_ADDR(x) ((x) + 0x4060) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_PHYS(x) ((x) + 0x4060) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_OFFS (0x4060) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_HISTBIN4_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_HISTBIN4_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_ADDR(x) ((x) + 0x4068) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_PHYS(x) ((x) + 0x4068) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_OFFS (0x4068) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_HISTBIN5_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_HISTBIN5_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_ADDR(x) ((x) + 0x4070) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_PHYS(x) ((x) + 0x4070) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_OFFS (0x4070) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_HISTBIN6_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_HISTBIN6_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_ADDR(x) ((x) + 0x4078) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_PHYS(x) ((x) + 0x4078) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_OFFS (0x4078) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_HISTBIN7_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_HISTBIN7_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_ADDR(x) ((x) + 0x4080) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_PHYS(x) ((x) + 0x4080) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_OFFS (0x4080) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_RMSK 0xff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_LATMAX_BMSK 0xff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_LATMAX_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_ADDR(x) ((x) + 0x4120) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_PHYS(x) ((x) + 0x4120) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_OFFS (0x4120) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_RMSK 0xfffffc00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xfffffc00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_VALUE_LSB_SHFT 10 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x4124) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x4124) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_OFFS (0x4124) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_RMSK 0x1f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0x1f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_ADDR(x) ((x) + 0x4128) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_PHYS(x) ((x) + 0x4128) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_OFFS (0x4128) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_RMSK 0xfffffc00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_POR 0xfffffc00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xfffffc00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_VALUE_LSB_SHFT 10 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x412c) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x412c) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_OFFS (0x412c) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_RMSK 0x1f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_POR 0x0000001f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0x1f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ADDR(x) ((x) + 0x4138) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_PHYS(x) ((x) + 0x4138) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_OFFS (0x4138) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_POR 0x00000003 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_ADDR(x) ((x) + 0x4178) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_PHYS(x) ((x) + 0x4178) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_OFFS (0x4178) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_FILTER_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_FILTER_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_ADDR(x) ((x) + 0x4180) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_PHYS(x) ((x) + 0x4180) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_OFFS (0x4180) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_FILTER_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_FILTER_EXTID_MASK_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: UMAC_ACMT + *--------------------------------------------------------------------------*/ + +#define UMAC_ACMT_REG_BASE (UMAC_ACMT_BASE + 0x00000000) +#define UMAC_ACMT_REG_BASE_SIZE 0x1000 +#define UMAC_ACMT_REG_BASE_USED 0x13c +#define UMAC_ACMT_REG_BASE_PHYS (UMAC_ACMT_BASE_PHYS + 0x00000000) +#define UMAC_ACMT_REG_BASE_OFFS 0x00000000 + +#define HWIO_UMAC_ACMT_CTRL_ADDR(x) ((x) + 0x0) +#define HWIO_UMAC_ACMT_CTRL_PHYS(x) ((x) + 0x0) +#define HWIO_UMAC_ACMT_CTRL_OFFS (0x0) +#define HWIO_UMAC_ACMT_CTRL_RMSK 0x1 +#define HWIO_UMAC_ACMT_CTRL_POR 0x00000000 +#define HWIO_UMAC_ACMT_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_CTRL_ATTR 0x3 +#define HWIO_UMAC_ACMT_CTRL_IN(x) \ + in_dword(HWIO_UMAC_ACMT_CTRL_ADDR(x)) +#define HWIO_UMAC_ACMT_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_CTRL_ADDR(x), m) +#define HWIO_UMAC_ACMT_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_CTRL_ADDR(x),v) +#define HWIO_UMAC_ACMT_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_CTRL_ADDR(x),m,v,HWIO_UMAC_ACMT_CTRL_IN(x)) +#define HWIO_UMAC_ACMT_CTRL_ENABLE_BMSK 0x1 +#define HWIO_UMAC_ACMT_CTRL_ENABLE_SHFT 0 + +#define HWIO_UMAC_ACMT_INTR_ENABLE_ADDR(x) ((x) + 0x4) +#define HWIO_UMAC_ACMT_INTR_ENABLE_PHYS(x) ((x) + 0x4) +#define HWIO_UMAC_ACMT_INTR_ENABLE_OFFS (0x4) +#define HWIO_UMAC_ACMT_INTR_ENABLE_RMSK 0x1 +#define HWIO_UMAC_ACMT_INTR_ENABLE_POR 0x00000000 +#define HWIO_UMAC_ACMT_INTR_ENABLE_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_INTR_ENABLE_ATTR 0x3 +#define HWIO_UMAC_ACMT_INTR_ENABLE_IN(x) \ + in_dword(HWIO_UMAC_ACMT_INTR_ENABLE_ADDR(x)) +#define HWIO_UMAC_ACMT_INTR_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_INTR_ENABLE_ADDR(x), m) +#define HWIO_UMAC_ACMT_INTR_ENABLE_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_INTR_ENABLE_ADDR(x),v) +#define HWIO_UMAC_ACMT_INTR_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_INTR_ENABLE_ADDR(x),m,v,HWIO_UMAC_ACMT_INTR_ENABLE_IN(x)) +#define HWIO_UMAC_ACMT_INTR_ENABLE_INTR_EN_BMSK 0x1 +#define HWIO_UMAC_ACMT_INTR_ENABLE_INTR_EN_SHFT 0 + +#define HWIO_UMAC_ACMT_INTR_STATUS_ADDR(x) ((x) + 0x8) +#define HWIO_UMAC_ACMT_INTR_STATUS_PHYS(x) ((x) + 0x8) +#define HWIO_UMAC_ACMT_INTR_STATUS_OFFS (0x8) +#define HWIO_UMAC_ACMT_INTR_STATUS_RMSK 0x1 +#define HWIO_UMAC_ACMT_INTR_STATUS_POR 0x00000000 +#define HWIO_UMAC_ACMT_INTR_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_INTR_STATUS_ATTR 0x1 +#define HWIO_UMAC_ACMT_INTR_STATUS_IN(x) \ + in_dword(HWIO_UMAC_ACMT_INTR_STATUS_ADDR(x)) +#define HWIO_UMAC_ACMT_INTR_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_INTR_STATUS_ADDR(x), m) +#define HWIO_UMAC_ACMT_INTR_STATUS_VALID_BMSK 0x1 +#define HWIO_UMAC_ACMT_INTR_STATUS_VALID_SHFT 0 + +#define HWIO_UMAC_ACMT_INTR_CLEAR_ADDR(x) ((x) + 0xc) +#define HWIO_UMAC_ACMT_INTR_CLEAR_PHYS(x) ((x) + 0xc) +#define HWIO_UMAC_ACMT_INTR_CLEAR_OFFS (0xc) +#define HWIO_UMAC_ACMT_INTR_CLEAR_RMSK 0x1 +#define HWIO_UMAC_ACMT_INTR_CLEAR_POR 0x00000000 +#define HWIO_UMAC_ACMT_INTR_CLEAR_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_INTR_CLEAR_ATTR 0x2 +#define HWIO_UMAC_ACMT_INTR_CLEAR_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_INTR_CLEAR_ADDR(x),v) +#define HWIO_UMAC_ACMT_INTR_CLEAR_CLR_BMSK 0x1 +#define HWIO_UMAC_ACMT_INTR_CLEAR_CLR_SHFT 0 + +#define HWIO_UMAC_ACMT_DEBUG0_ADDR(x) ((x) + 0x10) +#define HWIO_UMAC_ACMT_DEBUG0_PHYS(x) ((x) + 0x10) +#define HWIO_UMAC_ACMT_DEBUG0_OFFS (0x10) +#define HWIO_UMAC_ACMT_DEBUG0_RMSK 0xffffff +#define HWIO_UMAC_ACMT_DEBUG0_POR 0x00000000 +#define HWIO_UMAC_ACMT_DEBUG0_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_DEBUG0_ATTR 0x1 +#define HWIO_UMAC_ACMT_DEBUG0_IN(x) \ + in_dword(HWIO_UMAC_ACMT_DEBUG0_ADDR(x)) +#define HWIO_UMAC_ACMT_DEBUG0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_DEBUG0_ADDR(x), m) +#define HWIO_UMAC_ACMT_DEBUG0_ADDRESS_BMSK 0xffffff +#define HWIO_UMAC_ACMT_DEBUG0_ADDRESS_SHFT 0 + +#define HWIO_UMAC_ACMT_DEBUG1_ADDR(x) ((x) + 0x14) +#define HWIO_UMAC_ACMT_DEBUG1_PHYS(x) ((x) + 0x14) +#define HWIO_UMAC_ACMT_DEBUG1_OFFS (0x14) +#define HWIO_UMAC_ACMT_DEBUG1_RMSK 0x10000000 +#define HWIO_UMAC_ACMT_DEBUG1_POR 0x00000000 +#define HWIO_UMAC_ACMT_DEBUG1_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_DEBUG1_ATTR 0x1 +#define HWIO_UMAC_ACMT_DEBUG1_IN(x) \ + in_dword(HWIO_UMAC_ACMT_DEBUG1_ADDR(x)) +#define HWIO_UMAC_ACMT_DEBUG1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_DEBUG1_ADDR(x), m) +#define HWIO_UMAC_ACMT_DEBUG1_RW_BMSK 0x10000000 +#define HWIO_UMAC_ACMT_DEBUG1_RW_SHFT 28 + +#define HWIO_UMAC_ACMT_CFG_ADDR(x) ((x) + 0x1c) +#define HWIO_UMAC_ACMT_CFG_PHYS(x) ((x) + 0x1c) +#define HWIO_UMAC_ACMT_CFG_OFFS (0x1c) +#define HWIO_UMAC_ACMT_CFG_RMSK 0x11 +#define HWIO_UMAC_ACMT_CFG_POR 0x00000001 +#define HWIO_UMAC_ACMT_CFG_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_CFG_ATTR 0x1 +#define HWIO_UMAC_ACMT_CFG_IN(x) \ + in_dword(HWIO_UMAC_ACMT_CFG_ADDR(x)) +#define HWIO_UMAC_ACMT_CFG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_CFG_ADDR(x), m) +#define HWIO_UMAC_ACMT_CFG_DFLT_PROTECTION_BMSK 0x10 +#define HWIO_UMAC_ACMT_CFG_DFLT_PROTECTION_SHFT 4 +#define HWIO_UMAC_ACMT_CFG_PROTECTION_MODE_BMSK 0x1 +#define HWIO_UMAC_ACMT_CFG_PROTECTION_MODE_SHFT 0 + +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_ADDR(x) ((x) + 0x40) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_PHYS(x) ((x) + 0x40) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_OFFS (0x40) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_RMSK 0x111 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_POR 0x00000111 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_ATTR 0x3 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_IN(x) \ + in_dword(HWIO_UMAC_ACMT_NOC_TSLV_CTRL_ADDR(x)) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_NOC_TSLV_CTRL_ADDR(x), m) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_NOC_TSLV_CTRL_ADDR(x),v) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_NOC_TSLV_CTRL_ADDR(x),m,v,HWIO_UMAC_ACMT_NOC_TSLV_CTRL_IN(x)) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_RET_AHB_FORCE_POSTED_WR_BMSK 0x100 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_RET_AHB_FORCE_POSTED_WR_SHFT 8 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_RET_AHB_DEVBUFFABLE_BMSK 0x10 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_RET_AHB_DEVBUFFABLE_SHFT 4 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_TIMEOUT_ENABLE_BMSK 0x1 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_TIMEOUT_ENABLE_SHFT 0 + +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_ADDR(x) ((x) + 0x44) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_PHYS(x) ((x) + 0x44) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_OFFS (0x44) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_RMSK 0xf +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_POR 0x00000000 +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_ATTR 0x3 +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_IN(x) \ + in_dword(HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_ADDR(x)) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_ADDR(x), m) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_ADDR(x),v) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_ADDR(x),m,v,HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_IN(x)) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_TESTBUS_SEL_BMSK 0xf +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_TESTBUS_SEL_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_ADDR(x) ((x) + 0x100) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_PHYS(x) ((x) + 0x100) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_OFFS (0x100) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE0_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE0_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE0_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE0_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE0_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_ADDR(x) ((x) + 0x104) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_PHYS(x) ((x) + 0x104) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_OFFS (0x104) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE1_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE1_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE1_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE1_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE1_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_ADDR(x) ((x) + 0x108) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_PHYS(x) ((x) + 0x108) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_OFFS (0x108) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE2_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE2_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE2_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE2_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE2_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_ADDR(x) ((x) + 0x10c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_PHYS(x) ((x) + 0x10c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_OFFS (0x10c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE3_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE3_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE3_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE3_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE3_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_ADDR(x) ((x) + 0x110) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_PHYS(x) ((x) + 0x110) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_OFFS (0x110) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE4_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE4_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE4_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE4_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE4_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_ADDR(x) ((x) + 0x114) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_PHYS(x) ((x) + 0x114) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_OFFS (0x114) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE5_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE5_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE5_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE5_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE5_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_ADDR(x) ((x) + 0x118) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_PHYS(x) ((x) + 0x118) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_OFFS (0x118) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE6_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE6_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE6_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE6_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE6_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_ADDR(x) ((x) + 0x11c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_PHYS(x) ((x) + 0x11c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_OFFS (0x11c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE7_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE7_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE7_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE7_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE7_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_ADDR(x) ((x) + 0x120) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_PHYS(x) ((x) + 0x120) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_OFFS (0x120) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE8_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE8_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE8_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE8_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE8_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_ADDR(x) ((x) + 0x124) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_PHYS(x) ((x) + 0x124) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_OFFS (0x124) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE9_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE9_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE9_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE9_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE9_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_ADDR(x) ((x) + 0x128) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_PHYS(x) ((x) + 0x128) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_OFFS (0x128) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE10_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE10_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE10_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE10_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE10_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_ADDR(x) ((x) + 0x12c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_PHYS(x) ((x) + 0x12c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_OFFS (0x12c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE11_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE11_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE11_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE11_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE11_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_ADDR(x) ((x) + 0x130) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_PHYS(x) ((x) + 0x130) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_OFFS (0x130) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE12_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE12_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE12_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE12_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE12_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_ADDR(x) ((x) + 0x134) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_PHYS(x) ((x) + 0x134) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_OFFS (0x134) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE13_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE13_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE13_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE13_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE13_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_ADDR(x) ((x) + 0x138) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_PHYS(x) ((x) + 0x138) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_OFFS (0x138) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE14_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE14_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE14_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE14_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE14_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_ADDR(x) ((x) + 0x13c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_PHYS(x) ((x) + 0x13c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_OFFS (0x13c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE15_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE15_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE15_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE15_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE15_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_REGS_BASE_SHFT 0 + + +#endif /* __WCSS_SEQ_HWIOREG_UMAC_H__ */ diff --git a/drivers/staging/fw-api/hw/qcn6432/wcss_version.h b/drivers/staging/fw-api/hw/qcn6432/wcss_version.h new file mode 100644 index 0000000000000000000000000000000000000000..bd717cbce65063b751bf50a106d1ede3a8628cd5 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/wcss_version.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#define WCSS_VERSION 2447 diff --git a/drivers/staging/fw-api/hw/qcn6432/wfss_ce_reg_seq_hwioreg.h b/drivers/staging/fw-api/hw/qcn6432/wfss_ce_reg_seq_hwioreg.h new file mode 100644 index 0000000000000000000000000000000000000000..81b0ec15e538403e9760710bdd213cbd138ca425 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn6432/wfss_ce_reg_seq_hwioreg.h @@ -0,0 +1,15675 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __WFSS_CE_REG_SEQ_HWIOREG_H__ +#define __WFSS_CE_REG_SEQ_HWIOREG_H__ + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_0_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ +#define SOC_WFSS_CE_REG_BASE 0x1B80000 + +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000u) +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00000000u) +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00000000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_0_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000u) +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00001000u) +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS 0x00001000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_1_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000u) +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00002000u) +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00002000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_1_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000u) +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00003000u) +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS 0x00003000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_2_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00004000u) +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00004000u) +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00004000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_2_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00005000u) +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00005000u) +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS 0x00005000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_3_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00006000u) +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00006000u) +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00006000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_3_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00007000u) +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00007000u) +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS 0x00007000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_4_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00008000u) +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00008000u) +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00008000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_4_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00009000u) +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00009000u) +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS 0x00009000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_5_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000a000u) +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000a000u) +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000a000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_5_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000b000u) +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000b000u) +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000b000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_6_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000c000u) +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000c000u) +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000c000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_6_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000d000u) +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000d000u) +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000d000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_7_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000e000u) +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000e000u) +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000e000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_7_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000f000u) +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000f000u) +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000f000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_8_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00010000ul) +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00010000ul) +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00010000ul + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_8_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00011000ul) +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00011000ul) +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS 0x00011000ul + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_9_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00012000ul) +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00012000ul) +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00012000ul + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_9_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00013000ul) +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00013000ul) +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS 0x00013000ul + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_10_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00014000ul) +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00014000ul) +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00014000ul + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_10_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00015000ul) +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00015000ul) +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS 0x00015000ul + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_11_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00016000ul) +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00016000ul) +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00016000ul + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_11_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00017000ul) +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00017000ul) +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS 0x00017000ul + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_COMMON_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_COMMON_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00018000ul) +#define WFSS_CE_COMMON_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_COMMON_REG_REG_BASE_USED 0x418u +#define WFSS_CE_COMMON_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00018000ul) +#define WFSS_CE_COMMON_REG_REG_BASE_OFFS 0x00018000ul + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OFFS (0x0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OFFS (0x4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK 0xffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK 0xffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OFFS (0x8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_POR 0x00000211u +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0xe00u +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 9u +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x1f0u +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 4u +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0xfu +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OFFS (0xcu) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OFFS (0x10u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK 0x80000ffful +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 31u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_BMSK 0x800u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_SHFT 11u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x400u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 10u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x200u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 9u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x100u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 8u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x80u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 7u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x40u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 6u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x20u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 5u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x10u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 4u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x8u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 3u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x4u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 2u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x2u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_SHFT 1u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x) ((x) + 0x14u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS(x) ((x) + 0x14u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OFFS (0x14u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK 0x1010101ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x1000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 24u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x100u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 8u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x) ((x) + 0x18u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS(x) ((x) + 0x18u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OFFS (0x18u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK 0x3f3f3ful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x3f0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x3f00u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 8u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x3fu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OFFS (0x1cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3ful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 24u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0xff0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x3f00u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 8u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x3fu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OFFS (0x20u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK 0xffff3f3ful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 24u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0xff0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x3f00u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 8u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x3fu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x) ((x) + 0x24u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS(x) ((x) + 0x24u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OFFS (0x24u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK 0xffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_POR 0x00240000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x8000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 27u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x4000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 26u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x2000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 25u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x1000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 24u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x800000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 23u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x700000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 20u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0xe0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 17u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x1fe00ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 9u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x1feu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 1u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x) ((x) + 0x28u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS(x) ((x) + 0x28u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OFFS (0x28u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK 0xffff0001ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_POR 0x00ff0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x) ((x) + 0x2cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS(x) ((x) + 0x2cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OFFS (0x2cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK 0xffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0xffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OFFS (0x30u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0xffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OFFS (0x34u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK 0xffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 17u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OFFS (0x38u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK 0xffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 17u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OFFS (0x3cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OFFS (0x40u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OFFS (0x44u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OFFS (0x48u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OFFS (0x4cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK 0x1fffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK 0x1000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT 24u +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK 0xfff000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT 12u +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OFFS (0x50u) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OFFS (0x54u) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK 0xfffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK 0xfff000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT 12u +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OFFS (0x58u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK 0x1fffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK 0x1000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT 24u +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK 0xfff000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT 12u +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OFFS (0x5cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OFFS (0x60u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OFFS (0x64u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OFFS (0x68u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OFFS (0x6cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OFFS (0x70u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x) ((x) + 0x74u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_PHYS(x) ((x) + 0x74u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OFFS (0x74u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x) ((x) + 0x78u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS(x) ((x) + 0x78u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OFFS (0x78u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OFFS (0x7cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OFFS (0x80u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OFFS (0x84u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x) ((x) + 0x88u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_PHYS(x) ((x) + 0x88u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OFFS (0x88u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK 0xfffdfffful +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_BMSK 0x80000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_SHFT 31u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_BMSK 0x40000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_SHFT 30u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_BMSK 0x3ffc0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_SHFT 18u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_BMSK 0xf000u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_SHFT 12u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x) ((x) + 0x8cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_PHYS(x) ((x) + 0x8cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OFFS (0x8cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK 0xfffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_BMSK 0xfff000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_SHFT 12u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x) ((x) + 0x90u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_PHYS(x) ((x) + 0x90u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OFFS (0x90u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK 0x1fffu +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_BMSK 0x1000u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_SHFT 12u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x) ((x) + 0x94u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_PHYS(x) ((x) + 0x94u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OFFS (0x94u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x) ((x) + 0x98u) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_PHYS(x) ((x) + 0x98u) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_OFFS (0x98u) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x) ((x) + 0x9cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_PHYS(x) ((x) + 0x9cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OFFS (0x9cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OFFS (0xa0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_RMSK 0xf00fful +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_POR 0x0003000aul +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA_PRIORITY_BMSK 0xf0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA_PRIORITY_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA3_READ_AXI_MAX_LENGTH_CFG_BMSK 0xc0u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA3_READ_AXI_MAX_LENGTH_CFG_SHFT 6u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA2_READ_AXI_MAX_LENGTH_CFG_BMSK 0x30u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA2_READ_AXI_MAX_LENGTH_CFG_SHFT 4u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA1_READ_AXI_MAX_LENGTH_CFG_BMSK 0xcu +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA1_READ_AXI_MAX_LENGTH_CFG_SHFT 2u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA0_READ_AXI_MAX_LENGTH_CFG_BMSK 0x3u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA0_READ_AXI_MAX_LENGTH_CFG_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OFFS (0xa4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_RMSK 0x10ffful +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_POR 0x00000ffful +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_IDLE_INTR_STSRING_TPEQHP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_IDLE_INTR_STSRING_TPEQHP_EN_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_CSM_IDLE_REQ_EN_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_CSM_IDLE_REQ_EN_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_OFFS (0xa8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_RMSK 0x10ffful +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_GXI_IDLE_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_GXI_IDLE_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_CE_CSM_IDLE_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_CE_CSM_IDLE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OFFS (0xacu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RMSK 0x100fful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_POR 0x000000b5ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_BUS_SINGLE_TRIGGER_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_BUS_SINGLE_TRIGGER_EN_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WR_GRANT_HP_CNT_INIT_BMSK 0xe0u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WR_GRANT_HP_CNT_INIT_SHFT 5u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RD_GRANT_HP_CNT_INIT_BMSK 0x1cu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RD_GRANT_HP_CNT_INIT_SHFT 2u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WEIGHTED_ROUNDROBIN_EN_BMSK 0x2u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WEIGHTED_ROUNDROBIN_EN_SHFT 1u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_PRIORITY_EN_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_PRIORITY_EN_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_OFFS (0xb0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_GXI_BUS_STATUS_0_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_GXI_BUS_STATUS_0_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_OFFS (0xb4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_GXI_BUS_STATUS_1_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_GXI_BUS_STATUS_1_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_OFFS (0xb8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_GXI_BUS_STATUS_2_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_GXI_BUS_STATUS_2_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR(x) ((x) + 0xbcu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_PHYS(x) ((x) + 0xbcu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_OFFS (0xbcu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_GXI_BUS_STATUS_3_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_GXI_BUS_STATUS_3_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR(x) ((x) + 0xc0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_PHYS(x) ((x) + 0xc0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_OFFS (0xc0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_GXI_BUS_STATUS_4_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_GXI_BUS_STATUS_4_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR(x) ((x) + 0xc4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_PHYS(x) ((x) + 0xc4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_OFFS (0xc4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RMSK 0x3u +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_POR 0x00000003u +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CONFIG_N_BMSK 0x2u +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CONFIG_N_SHFT 1u +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CE_N_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CE_N_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OFFS (0x400u) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK 0x100fful +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK 0xffu +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OFFS (0x404u) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_POR 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OFFS (0x408u) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_POR 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OFFS (0x40cu) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x) ((x) + 0x410u) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS(x) ((x) + 0x410u) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OFFS (0x410u) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK 0xffu +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK 0xffu +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x414u) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x414u) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x414u) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002ul +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000ul +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 17u +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffcul +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 2u +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2u +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 1u +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x418u) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x418u) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OFFS (0x418u) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0u + + +#endif /* __WFSS_CE_REG_SEQ_HWIOREG_H__ */ diff --git a/drivers/staging/fw-api/hw/qcn9224/v1/mon_buffer_addr.h b/drivers/staging/fw-api/hw/qcn9224/v1/mon_buffer_addr.h index 050db3aac6d1cf434b5cba8076c597e4a1678770..b711c84afc8e47addeb65d4927896661ceb3e0ea 100644 --- a/drivers/staging/fw-api/hw/qcn9224/v1/mon_buffer_addr.h +++ b/drivers/staging/fw-api/hw/qcn9224/v1/mon_buffer_addr.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -34,7 +34,7 @@ struct mon_buffer_addr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t buffer_virt_addr_31_0 : 32; uint32_t buffer_virt_addr_63_32 : 32; uint32_t dma_length : 12, diff --git a/drivers/staging/fw-api/hw/qcn9224/v1/mon_destination_ring.h b/drivers/staging/fw-api/hw/qcn9224/v1/mon_destination_ring.h index 98ae42071fb7c468d6d55a39eeded1f51d6e968d..861a72aef747e34aee1e48128470c8fefd15efac 100644 --- a/drivers/staging/fw-api/hw/qcn9224/v1/mon_destination_ring.h +++ b/drivers/staging/fw-api/hw/qcn9224/v1/mon_destination_ring.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -32,7 +32,7 @@ struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t stat_buf_virt_addr_31_0 : 32; uint32_t stat_buf_virt_addr_63_32 : 32; uint32_t ppdu_id : 32; diff --git a/drivers/staging/fw-api/hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h b/drivers/staging/fw-api/hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h new file mode 100644 index 0000000000000000000000000000000000000000..71b2fe9ce122a45d7ec0f8b9a640b05c5a52ba22 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h @@ -0,0 +1,653 @@ + +/* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 66 + +#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 33 + + +struct phyrx_other_receive_info_evm_details { + uint32_t number_of_data_sym : 16, + number_of_streams : 8, + number_of_pilots : 8; + uint32_t acc_linear_evm_0_0 : 32; + uint32_t acc_linear_evm_1_0 : 32; + uint32_t acc_linear_evm_0_1 : 32; + uint32_t acc_linear_evm_1_1 : 32; + uint32_t acc_linear_evm_0_2 : 32; + uint32_t acc_linear_evm_1_2 : 32; + uint32_t acc_linear_evm_0_3 : 32; + uint32_t acc_linear_evm_1_3 : 32; + uint32_t acc_linear_evm_0_4 : 32; + uint32_t acc_linear_evm_1_4 : 32; + uint32_t acc_linear_evm_0_5 : 32; + uint32_t acc_linear_evm_1_5 : 32; + uint32_t acc_linear_evm_0_6 : 32; + uint32_t acc_linear_evm_1_6 : 32; + uint32_t acc_linear_evm_0_7 : 32; + uint32_t acc_linear_evm_1_7 : 32; + uint32_t acc_linear_evm_0_8 : 32; + uint32_t acc_linear_evm_1_8 : 32; + uint32_t acc_linear_evm_0_9 : 32; + uint32_t acc_linear_evm_1_9 : 32; + uint32_t acc_linear_evm_0_10 : 32; + uint32_t acc_linear_evm_1_10 : 32; + uint32_t acc_linear_evm_0_11 : 32; + uint32_t acc_linear_evm_1_11 : 32; + uint32_t acc_linear_evm_0_12 : 32; + uint32_t acc_linear_evm_1_12 : 32; + uint32_t acc_linear_evm_0_13 : 32; + uint32_t acc_linear_evm_1_13 : 32; + uint32_t acc_linear_evm_0_14 : 32; + uint32_t acc_linear_evm_1_14 : 32; + uint32_t acc_linear_evm_0_15 : 32; + uint32_t acc_linear_evm_1_15 : 32; + uint32_t acc_linear_evm_0_16 : 32; + uint32_t acc_linear_evm_1_16 : 32; + uint32_t acc_linear_evm_0_17 : 32; + uint32_t acc_linear_evm_1_17 : 32; + uint32_t acc_linear_evm_0_18 : 32; + uint32_t acc_linear_evm_1_18 : 32; + uint32_t acc_linear_evm_0_19 : 32; + uint32_t acc_linear_evm_1_19 : 32; + uint32_t acc_linear_evm_0_20 : 32; + uint32_t acc_linear_evm_1_20 : 32; + uint32_t acc_linear_evm_0_21 : 32; + uint32_t acc_linear_evm_1_21 : 32; + uint32_t acc_linear_evm_0_22 : 32; + uint32_t acc_linear_evm_1_22 : 32; + uint32_t acc_linear_evm_0_23 : 32; + uint32_t acc_linear_evm_1_23 : 32; + uint32_t acc_linear_evm_0_24 : 32; + uint32_t acc_linear_evm_1_24 : 32; + uint32_t acc_linear_evm_0_25 : 32; + uint32_t acc_linear_evm_1_25 : 32; + uint32_t acc_linear_evm_0_26 : 32; + uint32_t acc_linear_evm_1_26 : 32; + uint32_t acc_linear_evm_0_27 : 32; + uint32_t acc_linear_evm_1_27 : 32; + uint32_t acc_linear_evm_0_28 : 32; + uint32_t acc_linear_evm_1_28 : 32; + uint32_t acc_linear_evm_0_29 : 32; + uint32_t acc_linear_evm_1_29 : 32; + uint32_t acc_linear_evm_0_30 : 32; + uint32_t acc_linear_evm_1_30 : 32; + uint32_t acc_linear_evm_0_31 : 32; + uint32_t acc_linear_evm_1_31 : 32; + uint32_t tlv64_padding : 32; +}; + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MSB 15 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MASK 0x000000000000ffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_LSB 16 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MSB 23 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MASK 0x0000000000ff0000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_LSB 24 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MASK 0x00000000ff000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_OFFSET 0x0000000000000010 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_OFFSET 0x0000000000000010 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_OFFSET 0x0000000000000018 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_OFFSET 0x0000000000000018 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_OFFSET 0x0000000000000020 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_OFFSET 0x0000000000000020 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_OFFSET 0x0000000000000028 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_OFFSET 0x0000000000000028 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_OFFSET 0x0000000000000030 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_OFFSET 0x0000000000000030 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_OFFSET 0x0000000000000038 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_OFFSET 0x0000000000000038 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_OFFSET 0x0000000000000040 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_OFFSET 0x0000000000000040 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_OFFSET 0x0000000000000048 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_OFFSET 0x0000000000000048 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_OFFSET 0x0000000000000050 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_OFFSET 0x0000000000000050 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_OFFSET 0x0000000000000058 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_OFFSET 0x0000000000000058 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_OFFSET 0x0000000000000060 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_OFFSET 0x0000000000000060 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_OFFSET 0x0000000000000068 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_OFFSET 0x0000000000000068 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_OFFSET 0x0000000000000070 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_OFFSET 0x0000000000000070 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_OFFSET 0x0000000000000078 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_OFFSET 0x0000000000000078 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_OFFSET 0x0000000000000080 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_OFFSET 0x0000000000000080 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_OFFSET 0x0000000000000088 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_OFFSET 0x0000000000000088 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_OFFSET 0x0000000000000090 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_OFFSET 0x0000000000000090 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_OFFSET 0x0000000000000098 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_OFFSET 0x0000000000000098 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_OFFSET 0x00000000000000a0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_OFFSET 0x00000000000000a0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_OFFSET 0x00000000000000a8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_OFFSET 0x00000000000000a8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_OFFSET 0x00000000000000b0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_OFFSET 0x00000000000000b0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_OFFSET 0x00000000000000b8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_OFFSET 0x00000000000000b8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_OFFSET 0x00000000000000c0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_OFFSET 0x00000000000000c0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_OFFSET 0x00000000000000c8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_OFFSET 0x00000000000000c8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_OFFSET 0x00000000000000d0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_OFFSET 0x00000000000000d0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_OFFSET 0x00000000000000d8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_OFFSET 0x00000000000000d8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_OFFSET 0x00000000000000e0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_OFFSET 0x00000000000000e0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_OFFSET 0x00000000000000e8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_OFFSET 0x00000000000000e8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_OFFSET 0x00000000000000f0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_OFFSET 0x00000000000000f0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_OFFSET 0x00000000000000f8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_OFFSET 0x00000000000000f8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_OFFSET 0x0000000000000100 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000100 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/drivers/staging/fw-api/hw/qcn9224/v2/mon_buffer_addr.h b/drivers/staging/fw-api/hw/qcn9224/v2/mon_buffer_addr.h index 050db3aac6d1cf434b5cba8076c597e4a1678770..b711c84afc8e47addeb65d4927896661ceb3e0ea 100644 --- a/drivers/staging/fw-api/hw/qcn9224/v2/mon_buffer_addr.h +++ b/drivers/staging/fw-api/hw/qcn9224/v2/mon_buffer_addr.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -34,7 +34,7 @@ struct mon_buffer_addr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t buffer_virt_addr_31_0 : 32; uint32_t buffer_virt_addr_63_32 : 32; uint32_t dma_length : 12, diff --git a/drivers/staging/fw-api/hw/qcn9224/v2/mon_destination_ring.h b/drivers/staging/fw-api/hw/qcn9224/v2/mon_destination_ring.h index 98ae42071fb7c468d6d55a39eeded1f51d6e968d..861a72aef747e34aee1e48128470c8fefd15efac 100644 --- a/drivers/staging/fw-api/hw/qcn9224/v2/mon_destination_ring.h +++ b/drivers/staging/fw-api/hw/qcn9224/v2/mon_destination_ring.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -32,7 +32,7 @@ struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t stat_buf_virt_addr_31_0 : 32; uint32_t stat_buf_virt_addr_63_32 : 32; uint32_t ppdu_id : 32; diff --git a/drivers/staging/fw-api/hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h b/drivers/staging/fw-api/hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h new file mode 100644 index 0000000000000000000000000000000000000000..71b2fe9ce122a45d7ec0f8b9a640b05c5a52ba22 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h @@ -0,0 +1,653 @@ + +/* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 66 + +#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 33 + + +struct phyrx_other_receive_info_evm_details { + uint32_t number_of_data_sym : 16, + number_of_streams : 8, + number_of_pilots : 8; + uint32_t acc_linear_evm_0_0 : 32; + uint32_t acc_linear_evm_1_0 : 32; + uint32_t acc_linear_evm_0_1 : 32; + uint32_t acc_linear_evm_1_1 : 32; + uint32_t acc_linear_evm_0_2 : 32; + uint32_t acc_linear_evm_1_2 : 32; + uint32_t acc_linear_evm_0_3 : 32; + uint32_t acc_linear_evm_1_3 : 32; + uint32_t acc_linear_evm_0_4 : 32; + uint32_t acc_linear_evm_1_4 : 32; + uint32_t acc_linear_evm_0_5 : 32; + uint32_t acc_linear_evm_1_5 : 32; + uint32_t acc_linear_evm_0_6 : 32; + uint32_t acc_linear_evm_1_6 : 32; + uint32_t acc_linear_evm_0_7 : 32; + uint32_t acc_linear_evm_1_7 : 32; + uint32_t acc_linear_evm_0_8 : 32; + uint32_t acc_linear_evm_1_8 : 32; + uint32_t acc_linear_evm_0_9 : 32; + uint32_t acc_linear_evm_1_9 : 32; + uint32_t acc_linear_evm_0_10 : 32; + uint32_t acc_linear_evm_1_10 : 32; + uint32_t acc_linear_evm_0_11 : 32; + uint32_t acc_linear_evm_1_11 : 32; + uint32_t acc_linear_evm_0_12 : 32; + uint32_t acc_linear_evm_1_12 : 32; + uint32_t acc_linear_evm_0_13 : 32; + uint32_t acc_linear_evm_1_13 : 32; + uint32_t acc_linear_evm_0_14 : 32; + uint32_t acc_linear_evm_1_14 : 32; + uint32_t acc_linear_evm_0_15 : 32; + uint32_t acc_linear_evm_1_15 : 32; + uint32_t acc_linear_evm_0_16 : 32; + uint32_t acc_linear_evm_1_16 : 32; + uint32_t acc_linear_evm_0_17 : 32; + uint32_t acc_linear_evm_1_17 : 32; + uint32_t acc_linear_evm_0_18 : 32; + uint32_t acc_linear_evm_1_18 : 32; + uint32_t acc_linear_evm_0_19 : 32; + uint32_t acc_linear_evm_1_19 : 32; + uint32_t acc_linear_evm_0_20 : 32; + uint32_t acc_linear_evm_1_20 : 32; + uint32_t acc_linear_evm_0_21 : 32; + uint32_t acc_linear_evm_1_21 : 32; + uint32_t acc_linear_evm_0_22 : 32; + uint32_t acc_linear_evm_1_22 : 32; + uint32_t acc_linear_evm_0_23 : 32; + uint32_t acc_linear_evm_1_23 : 32; + uint32_t acc_linear_evm_0_24 : 32; + uint32_t acc_linear_evm_1_24 : 32; + uint32_t acc_linear_evm_0_25 : 32; + uint32_t acc_linear_evm_1_25 : 32; + uint32_t acc_linear_evm_0_26 : 32; + uint32_t acc_linear_evm_1_26 : 32; + uint32_t acc_linear_evm_0_27 : 32; + uint32_t acc_linear_evm_1_27 : 32; + uint32_t acc_linear_evm_0_28 : 32; + uint32_t acc_linear_evm_1_28 : 32; + uint32_t acc_linear_evm_0_29 : 32; + uint32_t acc_linear_evm_1_29 : 32; + uint32_t acc_linear_evm_0_30 : 32; + uint32_t acc_linear_evm_1_30 : 32; + uint32_t acc_linear_evm_0_31 : 32; + uint32_t acc_linear_evm_1_31 : 32; + uint32_t tlv64_padding : 32; +}; + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MSB 15 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MASK 0x000000000000ffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_LSB 16 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MSB 23 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MASK 0x0000000000ff0000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_LSB 24 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MASK 0x00000000ff000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_OFFSET 0x0000000000000010 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_OFFSET 0x0000000000000010 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_OFFSET 0x0000000000000018 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_OFFSET 0x0000000000000018 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_OFFSET 0x0000000000000020 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_OFFSET 0x0000000000000020 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_OFFSET 0x0000000000000028 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_OFFSET 0x0000000000000028 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_OFFSET 0x0000000000000030 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_OFFSET 0x0000000000000030 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_OFFSET 0x0000000000000038 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_OFFSET 0x0000000000000038 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_OFFSET 0x0000000000000040 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_OFFSET 0x0000000000000040 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_OFFSET 0x0000000000000048 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_OFFSET 0x0000000000000048 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_OFFSET 0x0000000000000050 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_OFFSET 0x0000000000000050 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_OFFSET 0x0000000000000058 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_OFFSET 0x0000000000000058 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_OFFSET 0x0000000000000060 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_OFFSET 0x0000000000000060 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_OFFSET 0x0000000000000068 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_OFFSET 0x0000000000000068 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_OFFSET 0x0000000000000070 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_OFFSET 0x0000000000000070 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_OFFSET 0x0000000000000078 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_OFFSET 0x0000000000000078 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_OFFSET 0x0000000000000080 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_OFFSET 0x0000000000000080 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_OFFSET 0x0000000000000088 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_OFFSET 0x0000000000000088 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_OFFSET 0x0000000000000090 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_OFFSET 0x0000000000000090 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_OFFSET 0x0000000000000098 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_OFFSET 0x0000000000000098 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_OFFSET 0x00000000000000a0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_OFFSET 0x00000000000000a0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_OFFSET 0x00000000000000a8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_OFFSET 0x00000000000000a8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_OFFSET 0x00000000000000b0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_OFFSET 0x00000000000000b0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_OFFSET 0x00000000000000b8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_OFFSET 0x00000000000000b8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_OFFSET 0x00000000000000c0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_OFFSET 0x00000000000000c0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_OFFSET 0x00000000000000c8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_OFFSET 0x00000000000000c8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_OFFSET 0x00000000000000d0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_OFFSET 0x00000000000000d0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_OFFSET 0x00000000000000d8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_OFFSET 0x00000000000000d8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_OFFSET 0x00000000000000e0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_OFFSET 0x00000000000000e0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_OFFSET 0x00000000000000e8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_OFFSET 0x00000000000000e8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_OFFSET 0x00000000000000f0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_OFFSET 0x00000000000000f0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_OFFSET 0x00000000000000f8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_OFFSET 0x00000000000000f8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_OFFSET 0x0000000000000100 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000100 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/HALcomdef.h b/drivers/staging/fw-api/hw/wcn6450/v1/HALcomdef.h new file mode 100644 index 0000000000000000000000000000000000000000..9e8d68aea47eb183c1139ab3acc8765fe40f4468 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/HALcomdef.h @@ -0,0 +1,53 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_COMDEF_H +#define HAL_COMDEF_H + +#ifndef _ARM_ASM_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "com_dtypes.h" + +#ifndef _BOOL32_DEFINED +typedef unsigned long int bool32; +#define _BOOL32_DEFINED +#endif + +#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF + + #define inp(port) (*((volatile byte *) (port))) + #define inpw(port) (*((volatile word *) (port))) + #define inpdw(port) (*((volatile dword *)(port))) + + #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) + #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) + #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/HALhwio.h b/drivers/staging/fw-api/hw/wcn6450/v1/HALhwio.h new file mode 100644 index 0000000000000000000000000000000000000000..b3b004df85ba664d5273931f9d8a1bd89a839be5 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/HALhwio.h @@ -0,0 +1,424 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_HWIO_H +#define HAL_HWIO_H + +#include "HALcomdef.h" + +#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET +#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET + +#define HWIO_BASE_PTR(base) base##_BASE_PTR + +#ifdef __ARMCC_VERSION + #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) +#else + #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) +#endif + +#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) +#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) +#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) +#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) + +#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) +#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) +#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) +#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) +#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) +#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) +#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) + +#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) +#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) +#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) +#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) +#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) +#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) +#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) + +#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) +#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) +#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) +#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) + +#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) +#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) +#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) +#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) + +#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) +#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) +#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) +#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) +#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) +#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) +#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) + +#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) +#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) +#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) +#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) + +#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) +#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) +#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) +#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) +#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) +#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) +#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) + +#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) +#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) +#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) +#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) +#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) +#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) +#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OPT_OUTM2(hwiosym, mask1, mask2, val1, val2) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUTM3(hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUTM4(hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUTM5(hwiosym, mask1, mask2, mask3, mask4, mask5, val1, val2, val3, val4, val5) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + reg = (reg & ~mask5) | (val5 & mask5); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUTM6(hwiosym, mask1, mask2, mask3, mask4, mask5, mask6, val1, val2, val3, val4, val5, val6) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + reg = (reg & ~mask5) | (val5 & mask5); \ + reg = (reg & ~mask6) | (val6 & mask6); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUT2F(io, field1, field2, val1, val2) HWIO_OPT_OUTM2(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OPT_OUT3F(io, field1, field2, field3, val1, val2, val3) HWIO_OPT_OUTM3(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OPT_OUT4F(io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OPT_OUTM4(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) +#define HWIO_OPT_OUT5F(io, field1, field2, field3, field4, field5, val1, val2, val3, val4, val5) HWIO_OPT_OUTM5(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5) ) +#define HWIO_OPT_OUT6F(io, field1, field2, field3, field4, field5, field6, val1, val2, val3, val4, val5, val6) HWIO_OPT_OUTM6(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), HWIO_FMSK(io, field6), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5), (uint32)(val6) << HWIO_SHFT(io, field6) ) + +#define HWIO_OPT_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTXM5(base, hwiosym, mask1, mask2, mask3, mask4, mask5, val1, val2, val3, val4, val5) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + reg = (reg & ~mask5) | (val5 & mask5); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTXM6(base, hwiosym, mask1, mask2, mask3, mask4, mask5, mask6, val1, val2, val3, val4, val5, val6) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + reg = (reg & ~mask5) | (val5 & mask5); \ + reg = (reg & ~mask6) | (val6 & mask6); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OPT_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OPT_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OPT_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OPT_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OPT_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) +#define HWIO_OPT_OUTX5F(base, io, field1, field2, field3, field4, field5, val1, val2, val3, val4, val5) HWIO_OPT_OUTXM5(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5) ) +#define HWIO_OPT_OUTX6F(base, io, field1, field2, field3, field4, field5, field6, val1, val2, val3, val4, val5, val6) HWIO_OPT_OUTXM6(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), HWIO_FMSK(io, field6), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5), (uint32)(val6) << HWIO_SHFT(io, field6) ) + +#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) + +#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) +#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) +#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) +#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) +#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) +#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) +#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) + +#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) +#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) + +#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN +#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) +#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) +#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) +#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) +#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) +#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) +#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) +#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) +#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) +#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) +#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) +#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) +#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) +#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) +#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) +#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR +#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) +#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) +#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) +#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS +#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) +#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) +#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) +#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) +#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) +#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK +#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) +#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK +#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT +#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT +#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow +#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) +#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL + +#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) +#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) +#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) +#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) +#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) +#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) +#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) +#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) +#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) +#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) +#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) +#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) +#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) +#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + } +#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + } +#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + HWIO_##hwiosym##_OUTM(base, mask4, val4); \ + } + +#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) +#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) +#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) +#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) +#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) +#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) +#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) +#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) +#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) +#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) +#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) + +#define HWIO_INTLOCK() +#define HWIO_INTFREE() + +#define __inp(port) (*((volatile uint8 *) (port))) +#define __inpw(port) (*((volatile uint16 *) (port))) +#ifdef PLAT_MSL_REG_READ +#ifdef __cplusplus +extern "C" { +#endif +extern uint32 plat_register_read(uint32 addr); +#ifdef __cplusplus +} +#endif + +#define __inpdw(port) plat_register_read((uint32) (port)) +#else +#define __inpdw(port) (*((volatile uint32 *) (port))) +#endif +#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) +#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) + +#ifdef HAL_HWIO_EXTERNAL + +#undef __inp +#undef __inpw +#undef __inpdw +#undef __outp +#undef __outpw +#undef __outpdw + +#define __inp(port) __inp_extern(port) +#define __inpw(port) __inpw_extern(port) +#define __inpdw(port) __inpdw_extern(port) +#define __outp(port, val) __outp_extern(port, val) +#define __outpw(port, val) __outpw_extern(port, val) +#define __outpdw(port, val) __outpdw_extern(port, val) + +extern uint8 __inp_extern ( uint32 nAddr ); +extern uint16 __inpw_extern ( uint32 nAddr ); +extern uint32 __inpdw_extern ( uint32 nAddr ); +extern void __outp_extern ( uint32 nAddr, uint8 nData ); +extern void __outpw_extern ( uint32 nAddr, uint16 nData ); +extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); + +#endif + +#define in_byte(addr) (__inp(addr)) +#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) +#define out_byte(addr, val) __outp(addr,val) +#define out_byte_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + out_byte( io, shadow); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + HWIO_INTFREE() +#define out_byte_masked_ns(io, mask, val, current_reg_content) \ + out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_word(addr) (__inpw(addr)) +#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) +#define out_word(addr, val) __outpw(addr,val) +#define out_word_masked(io, mask, val, shadow) \ + HWIO_INTLOCK( ); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + out_word( io, shadow); \ + HWIO_INTFREE( ) +#define out_word_masked_ns(io, mask, val, current_reg_content) \ + out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_dword(addr) (__inpdw(addr)) +#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) +#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ + out_dword( io, shadow); \ + HWIO_INTFREE() +#define out_dword_masked_ns(io, mask, val, current_reg_content) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + ((uint32)((val) & (mask)))) ) + +#endif + diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/buffer_addr_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/buffer_addr_info.h new file mode 100644 index 0000000000000000000000000000000000000000..1c8adb53220b2126105e72d0619f01cf165c6efe --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/buffer_addr_info.h @@ -0,0 +1,52 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _BUFFER_ADDR_INFO_H_ +#define _BUFFER_ADDR_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 + +struct buffer_addr_info { + uint32_t buffer_addr_31_0 : 32; + uint32_t buffer_addr_39_32 : 8, + return_buffer_manager : 3, + sw_buffer_cookie : 21; +}; + +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8 +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11 +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/ce_src_desc.h b/drivers/staging/fw-api/hw/wcn6450/v1/ce_src_desc.h new file mode 100644 index 0000000000000000000000000000000000000000..6563dade5ec4643f6362c5827934d5780dcb3d95 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/ce_src_desc.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _CE_SRC_DESC_H_ +#define _CE_SRC_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_SRC_DESC 4 + +struct ce_src_desc { + uint32_t src_buffer_low : 32; + uint32_t src_buffer_high : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + ce_res_0 : 4, + length : 16; + uint32_t fw_metadata : 16, + ce_res_1 : 16; + uint32_t ce_res_2 : 20, + ring_id : 8, + looping_count : 4; +}; + +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET 0x00000000 +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB 0 +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK 0xffffffff + +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET 0x00000004 +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB 0 +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK 0x000000ff + +#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET 0x00000004 +#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB 8 +#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_SRC_DESC_1_SRC_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_1_SRC_SWAP_LSB 9 +#define CE_SRC_DESC_1_SRC_SWAP_MASK 0x00000200 + +#define CE_SRC_DESC_1_DEST_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_1_DEST_SWAP_LSB 10 +#define CE_SRC_DESC_1_DEST_SWAP_MASK 0x00000400 + +#define CE_SRC_DESC_1_GATHER_OFFSET 0x00000004 +#define CE_SRC_DESC_1_GATHER_LSB 11 +#define CE_SRC_DESC_1_GATHER_MASK 0x00000800 + +#define CE_SRC_DESC_1_CE_RES_0_OFFSET 0x00000004 +#define CE_SRC_DESC_1_CE_RES_0_LSB 12 +#define CE_SRC_DESC_1_CE_RES_0_MASK 0x0000f000 + +#define CE_SRC_DESC_1_LENGTH_OFFSET 0x00000004 +#define CE_SRC_DESC_1_LENGTH_LSB 16 +#define CE_SRC_DESC_1_LENGTH_MASK 0xffff0000 + +#define CE_SRC_DESC_2_FW_METADATA_OFFSET 0x00000008 +#define CE_SRC_DESC_2_FW_METADATA_LSB 0 +#define CE_SRC_DESC_2_FW_METADATA_MASK 0x0000ffff + +#define CE_SRC_DESC_2_CE_RES_1_OFFSET 0x00000008 +#define CE_SRC_DESC_2_CE_RES_1_LSB 16 +#define CE_SRC_DESC_2_CE_RES_1_MASK 0xffff0000 + +#define CE_SRC_DESC_3_CE_RES_2_OFFSET 0x0000000c +#define CE_SRC_DESC_3_CE_RES_2_LSB 0 +#define CE_SRC_DESC_3_CE_RES_2_MASK 0x000fffff + +#define CE_SRC_DESC_3_RING_ID_OFFSET 0x0000000c +#define CE_SRC_DESC_3_RING_ID_LSB 20 +#define CE_SRC_DESC_3_RING_ID_MASK 0x0ff00000 + +#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_SRC_DESC_3_LOOPING_COUNT_LSB 28 +#define CE_SRC_DESC_3_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/ce_stat_desc.h b/drivers/staging/fw-api/hw/wcn6450/v1/ce_stat_desc.h new file mode 100644 index 0000000000000000000000000000000000000000..721480683df4a10f41fe04dca11a88c2fdb0cccc --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/ce_stat_desc.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _CE_STAT_DESC_H_ +#define _CE_STAT_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_STAT_DESC 4 + +struct ce_stat_desc { + uint32_t ce_res_5 : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + ce_res_6 : 4, + length : 16; + uint32_t toeplitz_hash_0 : 32; + uint32_t toeplitz_hash_1 : 32; + uint32_t fw_metadata : 16, + ce_res_7 : 4, + ring_id : 8, + looping_count : 4; +}; + +#define CE_STAT_DESC_0_CE_RES_5_OFFSET 0x00000000 +#define CE_STAT_DESC_0_CE_RES_5_LSB 0 +#define CE_STAT_DESC_0_CE_RES_5_MASK 0x000000ff + +#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET 0x00000000 +#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB 8 +#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_STAT_DESC_0_SRC_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_0_SRC_SWAP_LSB 9 +#define CE_STAT_DESC_0_SRC_SWAP_MASK 0x00000200 + +#define CE_STAT_DESC_0_DEST_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_0_DEST_SWAP_LSB 10 +#define CE_STAT_DESC_0_DEST_SWAP_MASK 0x00000400 + +#define CE_STAT_DESC_0_GATHER_OFFSET 0x00000000 +#define CE_STAT_DESC_0_GATHER_LSB 11 +#define CE_STAT_DESC_0_GATHER_MASK 0x00000800 + +#define CE_STAT_DESC_0_CE_RES_6_OFFSET 0x00000000 +#define CE_STAT_DESC_0_CE_RES_6_LSB 12 +#define CE_STAT_DESC_0_CE_RES_6_MASK 0x0000f000 + +#define CE_STAT_DESC_0_LENGTH_OFFSET 0x00000000 +#define CE_STAT_DESC_0_LENGTH_LSB 16 +#define CE_STAT_DESC_0_LENGTH_MASK 0xffff0000 + +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET 0x00000004 +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB 0 +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK 0xffffffff + +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET 0x00000008 +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB 0 +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK 0xffffffff + +#define CE_STAT_DESC_3_FW_METADATA_OFFSET 0x0000000c +#define CE_STAT_DESC_3_FW_METADATA_LSB 0 +#define CE_STAT_DESC_3_FW_METADATA_MASK 0x0000ffff + +#define CE_STAT_DESC_3_CE_RES_7_OFFSET 0x0000000c +#define CE_STAT_DESC_3_CE_RES_7_LSB 16 +#define CE_STAT_DESC_3_CE_RES_7_MASK 0x000f0000 + +#define CE_STAT_DESC_3_RING_ID_OFFSET 0x0000000c +#define CE_STAT_DESC_3_RING_ID_LSB 20 +#define CE_STAT_DESC_3_RING_ID_MASK 0x0ff00000 + +#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_STAT_DESC_3_LOOPING_COUNT_LSB 28 +#define CE_STAT_DESC_3_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/com_dtypes.h b/drivers/staging/fw-api/hw/wcn6450/v1/com_dtypes.h new file mode 100644 index 0000000000000000000000000000000000000000..83c89f3358602f427c3515114d8e32363807fc7e --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/com_dtypes.h @@ -0,0 +1,182 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef COM_DTYPES_H +#define COM_DTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef T_WINNT + #ifndef WIN32 + #define WIN32 + #endif + #include +#endif + +#ifdef TRUE +#undef TRUE +#endif + +#ifdef FALSE +#undef FALSE +#endif + +#define TRUE 1 +#define FALSE 0 + +#define ON 1 +#define OFF 0 + +#ifndef NULL + #define NULL 0 +#endif + +#ifndef _ARM_ASM_ +#ifndef _BOOLEAN_DEFINED + +typedef unsigned char boolean; +#define _BOOLEAN_DEFINED +#endif + +#if defined(DALSTDDEF_H) +#define _BOOLEAN_DEFINED +#define _UINT32_DEFINED +#define _UINT16_DEFINED +#define _UINT8_DEFINED +#define _INT32_DEFINED +#define _INT16_DEFINED +#define _INT8_DEFINED +#define _UINT64_DEFINED +#define _INT64_DEFINED +#define _BYTE_DEFINED +#endif + +#ifndef _UINT32_DEFINED + +typedef unsigned long int uint32; +#define _UINT32_DEFINED +#endif + +#ifndef _UINT16_DEFINED + +typedef unsigned short uint16; +#define _UINT16_DEFINED +#endif + +#ifndef _UINT8_DEFINED + +typedef unsigned char uint8; +#define _UINT8_DEFINED +#endif + +#ifndef _INT32_DEFINED + +typedef signed long int int32; +#define _INT32_DEFINED +#endif + +#ifndef _INT16_DEFINED + +typedef signed short int16; +#define _INT16_DEFINED +#endif + +#ifndef _INT8_DEFINED + +typedef signed char int8; +#define _INT8_DEFINED +#endif + +#ifndef _BYTE_DEFINED + +typedef unsigned char byte; +#define _BYTE_DEFINED +#endif + +typedef unsigned short word; + +typedef unsigned long dword; + +typedef unsigned char uint1; + +typedef unsigned short uint2; + +typedef unsigned long uint4; + +typedef signed char int1; + +typedef signed short int2; + +typedef long int int4; + +typedef signed long sint31; + +typedef signed short sint15; + +typedef signed char sint7; + +typedef uint16 UWord16 ; +typedef uint32 UWord32 ; +typedef int32 Word32 ; +typedef int16 Word16 ; +typedef uint8 UWord8 ; +typedef int8 Word8 ; +typedef int32 Vect32 ; + +#if (! defined T_WINNT) && (! defined __GNUC__) + + #ifndef _INT64_DEFINED + + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif +#else + + #if (defined __GNUC__) + #ifndef _INT64_DEFINED + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif + #else + typedef __int64 int64; + #ifndef _UINT64_DEFINED + typedef unsigned __int64 uint64; + #define _UINT64_DEFINED + #endif + #endif +#endif + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_mu_dl_info.h new file mode 100644 index 0000000000000000000000000000000000000000..85ffe9701396cc7cf5005419724f58c3cd67bcae --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_mu_dl_info.h @@ -0,0 +1,137 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_A_MU_DL_INFO_H_ +#define _HE_SIG_A_MU_DL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 + +struct he_sig_a_mu_dl_info { + uint32_t dl_ul_flag : 1, + mcs_of_sig_b : 3, + dcm_of_sig_b : 1, + bss_color_id : 6, + spatial_reuse : 4, + transmit_bw : 3, + num_sig_b_symbols : 4, + comp_mode_sig_b : 1, + cp_ltf_size : 2, + doppler_indication : 1, + reserved_0a : 6; + uint32_t txop_duration : 7, + reserved_1a : 1, + num_ltf_symbols : 3, + ldpc_extra_symbol : 1, + stbc : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity: 1, + crc : 4, + tail : 6, + reserved_1b : 6; +}; + +#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_LSB 0 +#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_MASK 0x00000001 + +#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_LSB 1 +#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_MASK 0x0000000e + +#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_LSB 4 +#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_MASK 0x00000010 + +#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_LSB 5 +#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_MASK 0x000007e0 + +#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_LSB 11 +#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_MASK 0x00007800 + +#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_LSB 15 +#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_MASK 0x00038000 + +#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_LSB 18 +#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_LSB 22 +#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_MASK 0x00400000 + +#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_LSB 23 +#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_MASK 0x01800000 + +#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_LSB 25 +#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_MASK 0x02000000 + +#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_LSB 26 +#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_MASK 0xfc000000 + +#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_MASK 0x00000080 + +#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_LSB 8 +#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_LSB 11 +#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define HE_SIG_A_MU_DL_INFO_1_STBC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_STBC_LSB 12 +#define HE_SIG_A_MU_DL_INFO_1_STBC_MASK 0x00001000 + +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define HE_SIG_A_MU_DL_INFO_1_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_CRC_LSB 16 +#define HE_SIG_A_MU_DL_INFO_1_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_DL_INFO_1_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_TAIL_LSB 20 +#define HE_SIG_A_MU_DL_INFO_1_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_MASK 0xfc000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_mu_ul_info.h new file mode 100644 index 0000000000000000000000000000000000000000..0e8230eee2217a391b7737b37cb64a7cb8bd87ff --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_mu_ul_info.h @@ -0,0 +1,87 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_A_MU_UL_INFO_H_ +#define _HE_SIG_A_MU_UL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 + +struct he_sig_a_mu_ul_info { + uint32_t format_indication : 1, + bss_color_id : 6, + spatial_reuse : 16, + reserved_0a : 1, + transmit_bw : 2, + reserved_0b : 6; + uint32_t txop_duration : 7, + reserved_1a : 9, + crc : 4, + tail : 6, + reserved_1b : 6; +}; + +#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_LSB 1 +#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_MASK 0x0000007e + +#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_LSB 7 +#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_MASK 0x007fff80 + +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_LSB 23 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_MASK 0x00800000 + +#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_LSB 24 +#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_MASK 0x03000000 + +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_MASK 0x0000ff80 + +#define HE_SIG_A_MU_UL_INFO_1_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_CRC_LSB 16 +#define HE_SIG_A_MU_UL_INFO_1_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_UL_INFO_1_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_TAIL_LSB 20 +#define HE_SIG_A_MU_UL_INFO_1_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_MASK 0xfc000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_su_info.h new file mode 100644 index 0000000000000000000000000000000000000000..72f6e8535441f70410e519244857061d180805ab --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_su_info.h @@ -0,0 +1,162 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_A_SU_INFO_H_ +#define _HE_SIG_A_SU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 + +struct he_sig_a_su_info { + uint32_t format_indication : 1, + beam_change : 1, + dl_ul_flag : 1, + transmit_mcs : 4, + dcm : 1, + bss_color_id : 6, + reserved_0a : 1, + spatial_reuse : 4, + transmit_bw : 2, + cp_ltf_size : 2, + nsts : 3, + reserved_0b : 6; + uint32_t txop_duration : 7, + coding : 1, + ldpc_extra_symbol : 1, + stbc : 1, + txbf : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity: 1, + reserved_1a : 1, + doppler_indication : 1, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + dot11ax_ext_ru_size : 4, + rx_ndp : 1; +}; + +#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_LSB 1 +#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_MASK 0x00000002 + +#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_LSB 2 +#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_MASK 0x00000004 + +#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_LSB 3 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_MASK 0x00000078 + +#define HE_SIG_A_SU_INFO_0_DCM_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_DCM_LSB 7 +#define HE_SIG_A_SU_INFO_0_DCM_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_LSB 8 +#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_MASK 0x00003f00 + +#define HE_SIG_A_SU_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_RESERVED_0A_LSB 14 +#define HE_SIG_A_SU_INFO_0_RESERVED_0A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_LSB 15 +#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_MASK 0x00078000 + +#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_LSB 19 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_MASK 0x00180000 + +#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_LSB 21 +#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_MASK 0x00600000 + +#define HE_SIG_A_SU_INFO_0_NSTS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_NSTS_LSB 23 +#define HE_SIG_A_SU_INFO_0_NSTS_MASK 0x03800000 + +#define HE_SIG_A_SU_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_RESERVED_0B_LSB 26 +#define HE_SIG_A_SU_INFO_0_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_LSB 0 +#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_SU_INFO_1_CODING_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_CODING_LSB 7 +#define HE_SIG_A_SU_INFO_1_CODING_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_LSB 8 +#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define HE_SIG_A_SU_INFO_1_STBC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_STBC_LSB 9 +#define HE_SIG_A_SU_INFO_1_STBC_MASK 0x00000200 + +#define HE_SIG_A_SU_INFO_1_TXBF_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_TXBF_LSB 10 +#define HE_SIG_A_SU_INFO_1_TXBF_MASK 0x00000400 + +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define HE_SIG_A_SU_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_RESERVED_1A_LSB 14 +#define HE_SIG_A_SU_INFO_1_RESERVED_1A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_LSB 15 +#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_MASK 0x00008000 + +#define HE_SIG_A_SU_INFO_1_CRC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_CRC_LSB 16 +#define HE_SIG_A_SU_INFO_1_CRC_MASK 0x000f0000 + +#define HE_SIG_A_SU_INFO_1_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_TAIL_LSB 20 +#define HE_SIG_A_SU_INFO_1_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_LSB 26 +#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_LSB 27 +#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_MASK 0x78000000 + +#define HE_SIG_A_SU_INFO_1_RX_NDP_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_RX_NDP_LSB 31 +#define HE_SIG_A_SU_INFO_1_RX_NDP_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b1_mu_info.h new file mode 100644 index 0000000000000000000000000000000000000000..8a077e7fe7bd1a7c47580afc456986253aacfa91 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b1_mu_info.h @@ -0,0 +1,42 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_B1_MU_INFO_H_ +#define _HE_SIG_B1_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 + +struct he_sig_b1_mu_info { + uint32_t ru_allocation : 8, + reserved_0 : 24; +}; + +#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_LSB 0 +#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_MASK 0x000000ff + +#define HE_SIG_B1_MU_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_0_RESERVED_0_LSB 8 +#define HE_SIG_B1_MU_INFO_0_RESERVED_0_MASK 0xffffff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b2_mu_info.h new file mode 100644 index 0000000000000000000000000000000000000000..ca97877b50a306777d2702a42e35b65068c69b83 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b2_mu_info.h @@ -0,0 +1,67 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_B2_MU_INFO_H_ +#define _HE_SIG_B2_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 1 + +struct he_sig_b2_mu_info { + uint32_t sta_id : 11, + sta_spatial_config : 4, + sta_mcs : 4, + reserved_set_to_1 : 1, + sta_coding : 1, + reserved_0a : 8, + nsts : 3; +}; + +#define HE_SIG_B2_MU_INFO_0_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_ID_LSB 0 +#define HE_SIG_B2_MU_INFO_0_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_LSB 11 +#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define HE_SIG_B2_MU_INFO_0_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_MCS_LSB 15 +#define HE_SIG_B2_MU_INFO_0_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_LSB 19 +#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_MASK 0x00080000 + +#define HE_SIG_B2_MU_INFO_0_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_CODING_LSB 20 +#define HE_SIG_B2_MU_INFO_0_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_LSB 21 +#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_MASK 0x1fe00000 + +#define HE_SIG_B2_MU_INFO_0_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_NSTS_LSB 29 +#define HE_SIG_B2_MU_INFO_0_NSTS_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b2_ofdma_info.h new file mode 100644 index 0000000000000000000000000000000000000000..6f6a8381e4828c4e424ea6b549cdc6fc194f19df --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b2_ofdma_info.h @@ -0,0 +1,67 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_B2_OFDMA_INFO_H_ +#define _HE_SIG_B2_OFDMA_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 1 + +struct he_sig_b2_ofdma_info { + uint32_t sta_id : 11, + nsts : 3, + txbf : 1, + sta_mcs : 4, + sta_dcm : 1, + sta_coding : 1, + reserved_0 : 11; +}; + +#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_OFDMA_INFO_0_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_NSTS_LSB 11 +#define HE_SIG_B2_OFDMA_INFO_0_NSTS_MASK 0x00003800 + +#define HE_SIG_B2_OFDMA_INFO_0_TXBF_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_TXBF_LSB 14 +#define HE_SIG_B2_OFDMA_INFO_0_TXBF_MASK 0x00004000 + +#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_LSB 15 +#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_LSB 19 +#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_MASK 0x00080000 + +#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_LSB 20 +#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_LSB 21 +#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_MASK 0xffe00000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/ht_sig_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/ht_sig_info.h new file mode 100644 index 0000000000000000000000000000000000000000..2205a0c0818ba62fa224bddc054a7e9717ea5843 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/ht_sig_info.h @@ -0,0 +1,107 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HT_SIG_INFO_H_ +#define _HT_SIG_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HT_SIG_INFO 2 + +struct ht_sig_info { + uint32_t mcs : 7, + cbw : 1, + length : 16, + reserved_0 : 8; + uint32_t smoothing : 1, + not_sounding : 1, + ht_reserved : 1, + aggregation : 1, + stbc : 2, + fec_coding : 1, + short_gi : 1, + num_ext_sp_str : 2, + crc : 8, + signal_tail : 6, + reserved_1 : 8; +}; + +#define HT_SIG_INFO_0_MCS_OFFSET 0x00000000 +#define HT_SIG_INFO_0_MCS_LSB 0 +#define HT_SIG_INFO_0_MCS_MASK 0x0000007f + +#define HT_SIG_INFO_0_CBW_OFFSET 0x00000000 +#define HT_SIG_INFO_0_CBW_LSB 7 +#define HT_SIG_INFO_0_CBW_MASK 0x00000080 + +#define HT_SIG_INFO_0_LENGTH_OFFSET 0x00000000 +#define HT_SIG_INFO_0_LENGTH_LSB 8 +#define HT_SIG_INFO_0_LENGTH_MASK 0x00ffff00 + +#define HT_SIG_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define HT_SIG_INFO_0_RESERVED_0_LSB 24 +#define HT_SIG_INFO_0_RESERVED_0_MASK 0xff000000 + +#define HT_SIG_INFO_1_SMOOTHING_OFFSET 0x00000004 +#define HT_SIG_INFO_1_SMOOTHING_LSB 0 +#define HT_SIG_INFO_1_SMOOTHING_MASK 0x00000001 + +#define HT_SIG_INFO_1_NOT_SOUNDING_OFFSET 0x00000004 +#define HT_SIG_INFO_1_NOT_SOUNDING_LSB 1 +#define HT_SIG_INFO_1_NOT_SOUNDING_MASK 0x00000002 + +#define HT_SIG_INFO_1_HT_RESERVED_OFFSET 0x00000004 +#define HT_SIG_INFO_1_HT_RESERVED_LSB 2 +#define HT_SIG_INFO_1_HT_RESERVED_MASK 0x00000004 + +#define HT_SIG_INFO_1_AGGREGATION_OFFSET 0x00000004 +#define HT_SIG_INFO_1_AGGREGATION_LSB 3 +#define HT_SIG_INFO_1_AGGREGATION_MASK 0x00000008 + +#define HT_SIG_INFO_1_STBC_OFFSET 0x00000004 +#define HT_SIG_INFO_1_STBC_LSB 4 +#define HT_SIG_INFO_1_STBC_MASK 0x00000030 + +#define HT_SIG_INFO_1_FEC_CODING_OFFSET 0x00000004 +#define HT_SIG_INFO_1_FEC_CODING_LSB 6 +#define HT_SIG_INFO_1_FEC_CODING_MASK 0x00000040 + +#define HT_SIG_INFO_1_SHORT_GI_OFFSET 0x00000004 +#define HT_SIG_INFO_1_SHORT_GI_LSB 7 +#define HT_SIG_INFO_1_SHORT_GI_MASK 0x00000080 + +#define HT_SIG_INFO_1_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define HT_SIG_INFO_1_NUM_EXT_SP_STR_LSB 8 +#define HT_SIG_INFO_1_NUM_EXT_SP_STR_MASK 0x00000300 + +#define HT_SIG_INFO_1_CRC_OFFSET 0x00000004 +#define HT_SIG_INFO_1_CRC_LSB 10 +#define HT_SIG_INFO_1_CRC_MASK 0x0003fc00 + +#define HT_SIG_INFO_1_SIGNAL_TAIL_OFFSET 0x00000004 +#define HT_SIG_INFO_1_SIGNAL_TAIL_LSB 18 +#define HT_SIG_INFO_1_SIGNAL_TAIL_MASK 0x00fc0000 + +#define HT_SIG_INFO_1_RESERVED_1_OFFSET 0x00000004 +#define HT_SIG_INFO_1_RESERVED_1_LSB 24 +#define HT_SIG_INFO_1_RESERVED_1_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/hwio.h b/drivers/staging/fw-api/hw/wcn6450/v1/hwio.h new file mode 100644 index 0000000000000000000000000000000000000000..f2498dd31705aa791cb727ecbdf94e12b152970e --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/hwio.h @@ -0,0 +1,1322 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef __HWIO_H__ +#define __HWIO_H__ + +#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_TOP_BASE + 0x00000000) +#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE_SIZE 0x1000 +#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE_USED 0x8c + +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x0) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_BASE_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x4) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x8) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_START_OFFSET_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_START_OFFSET_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_SIZE_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_SIZE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0xc) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_BASE_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x10) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_RMSK 0x3ff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_DESC_SKIP_DWORD_BMSK 0x300 +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_DESC_SKIP_DWORD_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x14) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_START_OFFSET_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_START_OFFSET_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_SIZE_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_SIZE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x18) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_RMSK 0x1ffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_TARGET_MSI_EN_BMSK 0x1000000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_TARGET_MSI_EN_SHFT 24 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_FW_EN_BMSK 0x800000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_FW_EN_SHFT 23 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_DEST_BMSK 0x400000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_DEST_SHFT 22 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_SRC_BMSK 0x200000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_SRC_SHFT 21 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_PREFETCH_EN_BMSK 0x100000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_PREFETCH_EN_SHFT 20 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IDX_UPD_EN_BMSK 0x80000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IDX_UPD_EN_SHFT 19 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_BMSK 0x40000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_SHFT 18 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_BMSK 0x20000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SHFT 17 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_HOST_MSI_EN_BMSK 0x10000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_HOST_MSI_EN_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x1c) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_RMSK 0xf +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_DST_AXI_MAX_LEN_BMSK 0xc +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_DST_AXI_MAX_LEN_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_SRC_AXI_MAX_LEN_BMSK 0x3 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_SRC_AXI_MAX_LEN_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x20) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_RMSK 0xf +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_STATUS_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_STATUS_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_DST_FLUSH_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_DST_FLUSH_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_SRC_FLUSH_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_SRC_FLUSH_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x24) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x28) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x2c) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x30) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x34) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_RMSK 0xfffff +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_PARSER_INT_BMSK 0xfc000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_PARSER_INT_SHFT 14 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_RD_BMSK 0x2000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_RD_SHFT 13 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_WR_BMSK 0x1000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_WR_SHFT 12 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_RO_WR_BMSK 0x800 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_RO_WR_SHFT 11 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_TIMEOUT_ERR_BMSK 0x400 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_TIMEOUT_ERR_SHFT 10 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_ERR_BMSK 0x200 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_ERR_SHFT 9 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_LEN_ERR_BMSK 0x100 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_LEN_ERR_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_MAX_LEN_VIO_BMSK 0x80 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_MAX_LEN_VIO_SHFT 7 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_OVERFLOW_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_OVERFLOW_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_OVERFLOW_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_OVERFLOW_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x38) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_RMSK 0xfffff +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_PARSER_INT_BMSK 0xfc000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_PARSER_INT_SHFT 14 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_RD_BMSK 0x2000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_RD_SHFT 13 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_WR_BMSK 0x1000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_WR_SHFT 12 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_RO_WR_BMSK 0x800 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_RO_WR_SHFT 11 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_TIMEOUT_ERR_BMSK 0x400 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_TIMEOUT_ERR_SHFT 10 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_BUS_ERR_BMSK 0x200 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_BUS_ERR_SHFT 9 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_LEN_ERR_BMSK 0x100 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_LEN_ERR_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_MAX_LEN_VIO_BMSK 0x80 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_MAX_LEN_VIO_SHFT 7 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_OVERFLOW_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_OVERFLOW_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_OVERFLOW_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_OVERFLOW_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x3c) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_SRC_WR_INDEX_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_SRC_WR_INDEX_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x40) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_DST_WR_INDEX_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_DST_WR_INDEX_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x44) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_CURRENT_SRRI_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_CURRENT_SRRI_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x48) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_CURRENT_DRRI_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_CURRENT_DRRI_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x4c) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x50) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x54) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_RMSK 0x7 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_PRIORITY_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_PRIORITY_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x58) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x5c) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x60) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_MSI_DATA_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_MSI_DATA_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x64) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x68) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_RMSK 0x3 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x6c) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x70) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x74) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x78) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x7c) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x80) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x84) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x88) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x8c) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_MSI_DATA_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_MSI_DATA_SHFT 0 + +#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_TOP_BASE + 0x00001000) +#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE_SIZE 0x1000 +#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE_USED 0x8c + +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x0) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_BASE_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x4) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x8) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_START_OFFSET_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_START_OFFSET_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_SIZE_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_SIZE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0xc) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_BASE_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x10) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_RMSK 0x3ff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_DESC_SKIP_DWORD_BMSK 0x300 +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_DESC_SKIP_DWORD_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x14) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_START_OFFSET_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_START_OFFSET_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_SIZE_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_SIZE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x18) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_RMSK 0x1ffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_TARGET_MSI_EN_BMSK 0x1000000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_TARGET_MSI_EN_SHFT 24 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_FW_EN_BMSK 0x800000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_FW_EN_SHFT 23 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_DEST_BMSK 0x400000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_DEST_SHFT 22 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_SRC_BMSK 0x200000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_SRC_SHFT 21 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_PREFETCH_EN_BMSK 0x100000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_PREFETCH_EN_SHFT 20 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IDX_UPD_EN_BMSK 0x80000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IDX_UPD_EN_SHFT 19 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DST_RING_BYTE_SWAP_EN_BMSK 0x40000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DST_RING_BYTE_SWAP_EN_SHFT 18 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_BMSK 0x20000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SHFT 17 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_HOST_MSI_EN_BMSK 0x10000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_HOST_MSI_EN_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x1c) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_RMSK 0xf +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_DST_AXI_MAX_LEN_BMSK 0xc +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_DST_AXI_MAX_LEN_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_SRC_AXI_MAX_LEN_BMSK 0x3 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_SRC_AXI_MAX_LEN_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x20) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_RMSK 0xf +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_STATUS_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_STATUS_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_DST_FLUSH_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_DST_FLUSH_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_SRC_FLUSH_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_SRC_FLUSH_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x24) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x28) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x2c) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x30) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x34) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_RMSK 0xfffff +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_PARSER_INT_BMSK 0xfc000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_PARSER_INT_SHFT 14 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_RD_BMSK 0x2000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_RD_SHFT 13 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_WR_BMSK 0x1000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_WR_SHFT 12 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_RO_WR_BMSK 0x800 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_RO_WR_SHFT 11 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_TIMEOUT_ERR_BMSK 0x400 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_TIMEOUT_ERR_SHFT 10 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_ERR_BMSK 0x200 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_ERR_SHFT 9 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_LEN_ERR_BMSK 0x100 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_LEN_ERR_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_MAX_LEN_VIO_BMSK 0x80 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_MAX_LEN_VIO_SHFT 7 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_OVERFLOW_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_OVERFLOW_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_OVERFLOW_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_OVERFLOW_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x38) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_RMSK 0xfffff +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_PARSER_INT_BMSK 0xfc000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_PARSER_INT_SHFT 14 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_RD_BMSK 0x2000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_RD_SHFT 13 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_WR_BMSK 0x1000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_WR_SHFT 12 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_RO_WR_BMSK 0x800 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_RO_WR_SHFT 11 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_TIMEOUT_ERR_BMSK 0x400 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_TIMEOUT_ERR_SHFT 10 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_BUS_ERR_BMSK 0x200 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_BUS_ERR_SHFT 9 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_LEN_ERR_BMSK 0x100 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_LEN_ERR_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_MAX_LEN_VIO_BMSK 0x80 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_MAX_LEN_VIO_SHFT 7 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_OVERFLOW_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_OVERFLOW_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_OVERFLOW_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_OVERFLOW_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x3c) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_SRC_WR_INDEX_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_SRC_WR_INDEX_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x40) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_DST_WR_INDEX_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_DST_WR_INDEX_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x44) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_CURRENT_SRRI_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_CURRENT_SRRI_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x48) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_CURRENT_DRRI_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_CURRENT_DRRI_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x4c) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x50) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x54) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_RMSK 0x7 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_PRIORITY_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_PRIORITY_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x58) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x5c) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x60) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_MSI_DATA_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_MSI_DATA_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x64) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x68) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_RMSK 0x3 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x6c) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x70) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x74) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x78) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x7c) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x80) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x84) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x88) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x8c) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_MSI_DATA_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_MSI_DATA_SHFT 0 + +#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE (HOST_SOC_WFSS_CE_REG_TOP_BASE + 0x00010000) +#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE_SIZE 0x1000 +#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE_USED 0x10 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x0) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_RMSK 0xfff000 +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_BMSK 0xfff000 +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_SHFT 12 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x4) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_VAL_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_VAL_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x8) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_VAL_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_VAL_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0xc) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_VAL_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_VAL_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x10) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_VAL_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_VAL_SHFT 0 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/l_sig_a_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/l_sig_a_info.h new file mode 100644 index 0000000000000000000000000000000000000000..c55cb46730d3c2c32c93b9fed3876abff0ca8318 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/l_sig_a_info.h @@ -0,0 +1,72 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _L_SIG_A_INFO_H_ +#define _L_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_A_INFO 1 + +struct l_sig_a_info { + uint32_t rate : 4, + lsig_reserved : 1, + length : 12, + parity : 1, + tail : 6, + pkt_type : 4, + captured_implicit_sounding : 1, + reserved : 3; +}; + +#define L_SIG_A_INFO_0_RATE_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_RATE_LSB 0 +#define L_SIG_A_INFO_0_RATE_MASK 0x0000000f + +#define L_SIG_A_INFO_0_LSIG_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_LSIG_RESERVED_LSB 4 +#define L_SIG_A_INFO_0_LSIG_RESERVED_MASK 0x00000010 + +#define L_SIG_A_INFO_0_LENGTH_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_LENGTH_LSB 5 +#define L_SIG_A_INFO_0_LENGTH_MASK 0x0001ffe0 + +#define L_SIG_A_INFO_0_PARITY_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_PARITY_LSB 17 +#define L_SIG_A_INFO_0_PARITY_MASK 0x00020000 + +#define L_SIG_A_INFO_0_TAIL_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_TAIL_LSB 18 +#define L_SIG_A_INFO_0_TAIL_MASK 0x00fc0000 + +#define L_SIG_A_INFO_0_PKT_TYPE_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_PKT_TYPE_LSB 24 +#define L_SIG_A_INFO_0_PKT_TYPE_MASK 0x0f000000 + +#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define L_SIG_A_INFO_0_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_RESERVED_LSB 29 +#define L_SIG_A_INFO_0_RESERVED_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/l_sig_b_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/l_sig_b_info.h new file mode 100644 index 0000000000000000000000000000000000000000..13d842077556d1efc3b3bd25aac23462bc63ebb5 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/l_sig_b_info.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _L_SIG_B_INFO_H_ +#define _L_SIG_B_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_B_INFO 1 + +struct l_sig_b_info { + uint32_t rate : 4, + length : 12, + reserved : 16; +}; + +#define L_SIG_B_INFO_0_RATE_OFFSET 0x00000000 +#define L_SIG_B_INFO_0_RATE_LSB 0 +#define L_SIG_B_INFO_0_RATE_MASK 0x0000000f + +#define L_SIG_B_INFO_0_LENGTH_OFFSET 0x00000000 +#define L_SIG_B_INFO_0_LENGTH_LSB 4 +#define L_SIG_B_INFO_0_LENGTH_MASK 0x0000fff0 + +#define L_SIG_B_INFO_0_RESERVED_OFFSET 0x00000000 +#define L_SIG_B_INFO_0_RESERVED_LSB 16 +#define L_SIG_B_INFO_0_RESERVED_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/macrx_abort_request_info.h new file mode 100644 index 0000000000000000000000000000000000000000..d9b718575707087a66851423a95d75b017dfca54 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/macrx_abort_request_info.h @@ -0,0 +1,42 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACRX_ABORT_REQUEST_INFO_H_ +#define _MACRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 + +struct macrx_abort_request_info { + uint16_t macrx_abort_reason : 8, + reserved_0 : 8; +}; + +#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_LSB 0 +#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_MASK 0x000000ff + +#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 8 +#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000ff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/msmhwiobase.h b/drivers/staging/fw-api/hw/wcn6450/v1/msmhwiobase.h new file mode 100644 index 0000000000000000000000000000000000000000..55619985a8354356c342ed711a276c237f12dc8f --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/msmhwiobase.h @@ -0,0 +1,27 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __MSMHWIOBASE_H__ +#define __MSMHWIOBASE_H__ + +#define HOST_SOC_WFSS_CE_REG_TOP_BASE 0x1b80000 +#define HOST_SOC_WFSS_CE_REG_TOP_BASE_SIZE 0x0001c000 +#define HOST_SOC_WFSS_CE_REG_TOP_BASE_PHYS 0x01b80000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_abort_request_info.h new file mode 100644 index 0000000000000000000000000000000000000000..bf0cad1fbfed5e0f4cb1f3b4f5c208803a5b93d3 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_abort_request_info.h @@ -0,0 +1,57 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ +#define _PHYRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 + +struct phyrx_abort_request_info { + uint32_t phyrx_abort_reason : 8, + phy_enters_nap_state : 1, + phy_enters_defer_state : 1, + reserved_0 : 6, + receive_duration : 16; +}; + +#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_LSB 0 +#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_MASK 0x000000ff + +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_LSB 8 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_LSB 9 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 10 +#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000fc00 + +#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_LSB 16 +#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_common_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..ca0e568d6184c05727ca30d84a64c44a81bc36ed --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_common_user_info.h @@ -0,0 +1,42 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_COMMON_USER_INFO_H_ +#define _PHYRX_COMMON_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 1 + +struct phyrx_common_user_info { + uint32_t receive_duration : 16, + reserved_0a : 16; +}; + +#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_LSB 0 +#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_MASK 0x0000ffff + +#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_LSB 16 +#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h new file mode 100644 index 0000000000000000000000000000000000000000..e41b29af5fafa9d07a7bb3bfbeb38da13517b720 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h @@ -0,0 +1,119 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ +#define _PHYRX_HE_SIG_A_MU_DL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_dl_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 + +struct phyrx_he_sig_a_mu_dl { + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +}; + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h new file mode 100644 index 0000000000000000000000000000000000000000..98bae636ad88bf7ec83119c45214328666eb5f0d --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h @@ -0,0 +1,79 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ +#define _PHYRX_HE_SIG_A_MU_UL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_ul_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 + +struct phyrx_he_sig_a_mu_ul { + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +}; + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80 + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000 + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000 + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80 + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_su.h new file mode 100644 index 0000000000000000000000000000000000000000..97ec7273f97805ce486dac6665167b076f9cd7c8 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_su.h @@ -0,0 +1,139 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_A_SU_H_ +#define _PHYRX_HE_SIG_A_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_su_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 + +struct phyrx_he_sig_a_su { + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +}; + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x78000000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 31 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b1_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..6b4c32f30ba1f9710b9c9a6d6e8c5d920c1583ac --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b1_mu.h @@ -0,0 +1,43 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_B1_MU_H_ +#define _PHYRX_HE_SIG_B1_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b1_mu_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1 + +struct phyrx_he_sig_b1_mu { + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; +}; + +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff + +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0xffffff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b2_mu.h new file mode 100644 index 0000000000000000000000000000000000000000..c641efc8054bd213825b59f148bd97b2e6ef5254 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b2_mu.h @@ -0,0 +1,63 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_B2_MU_H_ +#define _PHYRX_HE_SIG_B2_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_mu_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 1 + +struct phyrx_he_sig_b2_mu { + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +}; + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x1fe00000 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 29 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h new file mode 100644 index 0000000000000000000000000000000000000000..08b9f511fc9827f841020e111cfd3c45d8e69cb6 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h @@ -0,0 +1,63 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ +#define _PHYRX_HE_SIG_B2_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_ofdma_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 1 + +struct phyrx_he_sig_b2_ofdma { + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +}; + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0xffe00000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_ht_sig.h new file mode 100644 index 0000000000000000000000000000000000000000..2677b0bdc30985b496ac55a11572d53773fcac7d --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_ht_sig.h @@ -0,0 +1,95 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HT_SIG_H_ +#define _PHYRX_HT_SIG_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ht_sig_info.h" + +#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 + +struct phyrx_ht_sig { + struct ht_sig_info phyrx_ht_sig_info_details; +}; + +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f + +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080 + +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00 + +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 4 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_l_sig_a.h new file mode 100644 index 0000000000000000000000000000000000000000..568c80c44c49fb534de0c05616d72bccaa626705 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_l_sig_a.h @@ -0,0 +1,67 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_L_SIG_A_H_ +#define _PHYRX_L_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_a_info.h" + +#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1 + +struct phyrx_l_sig_a { + struct l_sig_a_info phyrx_l_sig_a_info_details; +}; + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_l_sig_b.h new file mode 100644 index 0000000000000000000000000000000000000000..37e0e4bc857a80d3d6bcfebb7707c484536678f8 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_l_sig_b.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_L_SIG_B_H_ +#define _PHYRX_L_SIG_B_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_b_info.h" + +#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1 + +struct phyrx_l_sig_b { + struct l_sig_b_info phyrx_l_sig_b_info_details; +}; + +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f + +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0 + +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h new file mode 100644 index 0000000000000000000000000000000000000000..54a54ddccb3a5c20ca040eb89a837ebaf2f21355 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 3 + +struct phyrx_other_receive_info_ru_details { + uint32_t ru_details_channel_0 : 32; + uint32_t ru_details_channel_1 : 32; + uint32_t spare : 32; +}; + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_OFFSET 0x00000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_MASK 0xffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_OFFSET 0x00000004 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_MASK 0xffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_OFFSET 0x00000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_pkt_end.h new file mode 100644 index 0000000000000000000000000000000000000000..1a86068be10c046cc8bbd2a0ca7153a6ea9241d9 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_pkt_end.h @@ -0,0 +1,503 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_PKT_END_H_ +#define _PHYRX_PKT_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_pkt_end_info.h" + +#define NUM_OF_DWORDS_PHYRX_PKT_END 33 + +struct phyrx_pkt_end { + struct phyrx_pkt_end_info rx_pkt_end_details; +}; + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x00000002 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x00000004 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x00000008 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_LSB 4 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_LSB 6 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x00000fc0 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_LSB 12 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_MASK 0x00001000 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_LSB 13 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_LSB 20 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_LSB 27 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0xf8000000 + +#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff + +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 + +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff + +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000 + +#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024 +#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 +#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff + +#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028 +#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 +#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff + +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0 +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff + +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12 +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000 + +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 + +#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030 +#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000 + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000 + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000 + +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 + +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000007c +#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0xffffffff + +#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x00000080 +#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_pkt_end_info.h new file mode 100644 index 0000000000000000000000000000000000000000..d71467a50c1e7df114a455de2e8fb35666247001 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_pkt_end_info.h @@ -0,0 +1,524 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_PKT_END_INFO_H_ +#define _PHYRX_PKT_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_location_info.h" +#include "rx_timing_offset_info.h" +#include "receive_rssi_info.h" + +#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33 + +struct phyrx_pkt_end_info { + uint32_t __reserved_g_0001 : 1, + location_info_valid : 1, + timing_info_valid : 1, + rssi_info_valid : 1, + rx_frame_correction_needed : 1, + frameless_frame_received : 1, + reserved_0a : 6, + dl_ofdma_info_valid : 1, + dl_ofdma_ru_start_index : 7, + dl_ofdma_ru_width : 7, + reserved_0b : 5; + uint32_t phy_timestamp_1_lower_32 : 32; + uint32_t phy_timestamp_1_upper_32 : 32; + uint32_t phy_timestamp_2_lower_32 : 32; + uint32_t phy_timestamp_2_upper_32 : 32; + struct rx_location_info rx_location_info_details; + struct rx_timing_offset_info rx_timing_offset_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; + uint32_t phy_sw_status_63_32 : 32; +}; + +#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002 + +#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004 + +#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008 + +#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 +#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 + +#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +#define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6 +#define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0x00000fc0 + +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB 12 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK 0x00001000 + +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB 13 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 + +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB 20 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 + +#define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB 27 +#define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK 0xf8000000 + +#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff + +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 + +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff + +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000 + +#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 +#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 +#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0 +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff + +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12 +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000 + +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000 + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000 + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000 + +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 + +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c +#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 +#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_rssi_legacy.h new file mode 100644 index 0000000000000000000000000000000000000000..f9732e34b669ad75fd2cd140226cb283766f7f55 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_rssi_legacy.h @@ -0,0 +1,628 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_RSSI_LEGACY_H_ +#define _PHYRX_RSSI_LEGACY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_rssi_info.h" + +#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 37 + +struct phyrx_rssi_legacy { + uint32_t reception_type : 4, + rx_chain_mask_type : 1, + reserved_0 : 1, + receive_bandwidth : 2, + rx_chain_mask : 8, + phy_ppdu_id : 16; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp : 32; + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t pre_rssi_comb : 8, + rssi_comb : 8, + normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t rssi_comb_ppdu : 8, + rssi_db_to_dbm_offset : 8, + rssi_for_spatial_reuse : 8, + rssi_for_trigger_resp : 8; +}; + +#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_LSB 0 +#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_MASK 0x0000000f + +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_LSB 4 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_MASK 0x00000010 + +#define PHYRX_RSSI_LEGACY_0_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RESERVED_0_LSB 5 +#define PHYRX_RSSI_LEGACY_0_RESERVED_0_MASK 0x00000020 + +#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_LSB 6 +#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_LSB 8 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_LSB 16 +#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_OFFSET 0x00000004 +#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_LSB 0 +#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008 +#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_LSB 0 +#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_LSB 0 +#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_LSB 8 +#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_LSB 24 +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_LSB 0 +#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_LSB 8 +#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_LSB 16 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_LSB 24 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_user_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..2724759cf5be7e283b64a9b77a27dc9d1a9ef3a4 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_user_info.h @@ -0,0 +1,95 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_USER_INFO_H_ +#define _PHYRX_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_user_info.h" + +#define NUM_OF_DWORDS_PHYRX_USER_INFO 3 + +struct phyrx_user_info { + struct receive_user_info receive_user_info_details; +}; + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000 + +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 0 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00000001 + +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET 0x00000008 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB 1 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK 0x000000fe + +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 8 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_vht_sig_a.h new file mode 100644 index 0000000000000000000000000000000000000000..b9490245dbdea5d7b285b136f5d61875623f44b8 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_vht_sig_a.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_VHT_SIG_A_H_ +#define _PHYRX_VHT_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_a_info.h" + +#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 + +struct phyrx_vht_sig_a { + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +}; + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/receive_rssi_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/receive_rssi_info.h new file mode 100644 index 0000000000000000000000000000000000000000..3d3133b6f1601a9456b18fbec9cdc0af57005f46 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/receive_rssi_info.h @@ -0,0 +1,352 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVE_RSSI_INFO_H_ +#define _RECEIVE_RSSI_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 + +struct receive_rssi_info { + uint32_t rssi_pri20_chain0 : 8, + rssi_ext20_chain0 : 8, + rssi_ext40_low20_chain0 : 8, + rssi_ext40_high20_chain0 : 8; + uint32_t rssi_ext80_low20_chain0 : 8, + rssi_ext80_low_high20_chain0 : 8, + rssi_ext80_high_low20_chain0 : 8, + rssi_ext80_high20_chain0 : 8; + uint32_t rssi_pri20_chain1 : 8, + rssi_ext20_chain1 : 8, + rssi_ext40_low20_chain1 : 8, + rssi_ext40_high20_chain1 : 8; + uint32_t rssi_ext80_low20_chain1 : 8, + rssi_ext80_low_high20_chain1 : 8, + rssi_ext80_high_low20_chain1 : 8, + rssi_ext80_high20_chain1 : 8; + uint32_t rssi_pri20_chain2 : 8, + rssi_ext20_chain2 : 8, + rssi_ext40_low20_chain2 : 8, + rssi_ext40_high20_chain2 : 8; + uint32_t rssi_ext80_low20_chain2 : 8, + rssi_ext80_low_high20_chain2 : 8, + rssi_ext80_high_low20_chain2 : 8, + rssi_ext80_high20_chain2 : 8; + uint32_t rssi_pri20_chain3 : 8, + rssi_ext20_chain3 : 8, + rssi_ext40_low20_chain3 : 8, + rssi_ext40_high20_chain3 : 8; + uint32_t rssi_ext80_low20_chain3 : 8, + rssi_ext80_low_high20_chain3 : 8, + rssi_ext80_high_low20_chain3 : 8, + rssi_ext80_high20_chain3 : 8; + uint32_t rssi_pri20_chain4 : 8, + rssi_ext20_chain4 : 8, + rssi_ext40_low20_chain4 : 8, + rssi_ext40_high20_chain4 : 8; + uint32_t rssi_ext80_low20_chain4 : 8, + rssi_ext80_low_high20_chain4 : 8, + rssi_ext80_high_low20_chain4 : 8, + rssi_ext80_high20_chain4 : 8; + uint32_t rssi_pri20_chain5 : 8, + rssi_ext20_chain5 : 8, + rssi_ext40_low20_chain5 : 8, + rssi_ext40_high20_chain5 : 8; + uint32_t rssi_ext80_low20_chain5 : 8, + rssi_ext80_low_high20_chain5 : 8, + rssi_ext80_high_low20_chain5 : 8, + rssi_ext80_high20_chain5 : 8; + uint32_t rssi_pri20_chain6 : 8, + rssi_ext20_chain6 : 8, + rssi_ext40_low20_chain6 : 8, + rssi_ext40_high20_chain6 : 8; + uint32_t rssi_ext80_low20_chain6 : 8, + rssi_ext80_low_high20_chain6 : 8, + rssi_ext80_high_low20_chain6 : 8, + rssi_ext80_high20_chain6 : 8; + uint32_t rssi_pri20_chain7 : 8, + rssi_ext20_chain7 : 8, + rssi_ext40_low20_chain7 : 8, + rssi_ext40_high20_chain7 : 8; + uint32_t rssi_ext80_low20_chain7 : 8, + rssi_ext80_low_high20_chain7 : 8, + rssi_ext80_high_low20_chain7 : 8, + rssi_ext80_high20_chain7 : 8; +}; + +#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_LSB 0 +#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_LSB 8 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_LSB 0 +#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_LSB 8 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_LSB 0 +#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_LSB 8 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_LSB 0 +#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_LSB 8 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/receive_user_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/receive_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..9b2eb60e1410ceab4772678eac97af55b149452d --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/receive_user_info.h @@ -0,0 +1,107 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVE_USER_INFO_H_ +#define _RECEIVE_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_USER_INFO 3 + +struct receive_user_info { + uint32_t phy_ppdu_id : 16, + user_rssi : 8, + pkt_type : 4, + stbc : 1, + reception_type : 3; + uint32_t rate_mcs : 4, + sgi : 2, + receive_bandwidth : 2, + mimo_ss_bitmap : 8, + ofdma_ru_allocation : 8, + ofdma_user_index : 7, + ofdma_content_channel : 1; + uint32_t ldpc : 1, + ru_width : 7, + reserved_2a : 24; +}; + +#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_LSB 0 +#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVE_USER_INFO_0_USER_RSSI_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_USER_RSSI_LSB 16 +#define RECEIVE_USER_INFO_0_USER_RSSI_MASK 0x00ff0000 + +#define RECEIVE_USER_INFO_0_PKT_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_PKT_TYPE_LSB 24 +#define RECEIVE_USER_INFO_0_PKT_TYPE_MASK 0x0f000000 + +#define RECEIVE_USER_INFO_0_STBC_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_STBC_LSB 28 +#define RECEIVE_USER_INFO_0_STBC_MASK 0x10000000 + +#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_LSB 29 +#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_MASK 0xe0000000 + +#define RECEIVE_USER_INFO_1_RATE_MCS_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_RATE_MCS_LSB 0 +#define RECEIVE_USER_INFO_1_RATE_MCS_MASK 0x0000000f + +#define RECEIVE_USER_INFO_1_SGI_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_SGI_LSB 4 +#define RECEIVE_USER_INFO_1_SGI_MASK 0x00000030 + +#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_LSB 6 +#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_LSB 8 +#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_LSB 16 +#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_MASK 0x00ff0000 + +#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_LSB 24 +#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_MASK 0x7f000000 + +#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_LSB 31 +#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_MASK 0x80000000 + +#define RECEIVE_USER_INFO_2_LDPC_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_2_LDPC_LSB 0 +#define RECEIVE_USER_INFO_2_LDPC_MASK 0x00000001 + +#define RECEIVE_USER_INFO_2_RU_WIDTH_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_2_RU_WIDTH_LSB 1 +#define RECEIVE_USER_INFO_2_RU_WIDTH_MASK 0x000000fe + +#define RECEIVE_USER_INFO_2_RESERVED_2A_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_2_RESERVED_2A_LSB 8 +#define RECEIVE_USER_INFO_2_RESERVED_2A_MASK 0xffffff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h new file mode 100644 index 0000000000000000000000000000000000000000..27f7972cc4ebf227f258ef198c134a410d49be07 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h @@ -0,0 +1,200 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25 + +struct reo_descriptor_threshold_reached_status { + struct uniform_reo_status_header status_header; + uint32_t threshold_index : 2, + reserved_2 : 30; + uint32_t link_descriptor_counter0 : 24, + reserved_3 : 8; + uint32_t link_descriptor_counter1 : 24, + reserved_4 : 8; + uint32_t link_descriptor_counter2 : 24, + reserved_5 : 8; + uint32_t link_descriptor_counter_sum : 26, + reserved_6 : 6; + uint32_t reserved_7 : 32; + uint32_t reserved_8 : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET 0x00000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB 2 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK 0xfffffffc + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK 0xfc000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET 0x0000001c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET 0x00000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_destination_ring.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_destination_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..361b405f3342bb08e362447726c83b4f5fcaad62 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_destination_ring.h @@ -0,0 +1,301 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_DESTINATION_RING_H_ +#define _REO_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_desc_info.h" +#include "rx_msdu_desc_info.h" + +#define NUM_OF_DWORDS_REO_DESTINATION_RING 16 + +struct reo_destination_ring { + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + reo_dest_buffer_type : 1, + reo_push_reason : 2, + reo_error_code : 5, + receive_queue_number : 16; + uint32_t soft_reorder_info_valid : 1, + reorder_opcode : 4, + reorder_slot_index : 8, + mpdu_fragment_number : 4, + captured_msdu_data_size : 4, + sw_exception : 1, + reserved_8a : 10; + uint32_t reo_destination_struct_signature: 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15 : 20, + ring_id : 8, + looping_count : 4; +}; + +#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8 +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100 + +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9 +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600 + +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11 +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800 + +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16 +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 + +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0 +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001 + +#define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1 +#define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e + +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5 +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0 + +#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_LSB 13 +#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_MASK 0x0001e000 + +#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_LSB 17 +#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_MASK 0x001e0000 + +#define REO_DESTINATION_RING_8_SW_EXCEPTION_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_SW_EXCEPTION_LSB 21 +#define REO_DESTINATION_RING_8_SW_EXCEPTION_MASK 0x00200000 + +#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_RESERVED_8A_LSB 22 +#define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffc00000 + +#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x00000024 +#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_LSB 0 +#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0xffffffff + +#define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0 +#define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff + +#define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0 +#define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff + +#define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0 +#define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff + +#define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0 +#define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff + +#define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0 +#define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff + +#define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_RESERVED_15_LSB 0 +#define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff + +#define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_RING_ID_LSB 20 +#define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000 + +#define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_entrance_ring.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_entrance_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..65bf3e407d7640be83b111227a06add6fa55e42d --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_entrance_ring.h @@ -0,0 +1,201 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_ENTRANCE_RING_H_ +#define _REO_ENTRANCE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_details.h" + +#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 + +struct reo_entrance_ring { + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + rounded_mpdu_byte_count : 14, + reo_destination_indication : 5, + frameless_bar : 1, + reserved_5a : 4; + uint32_t rxdma_push_reason : 2, + rxdma_error_code : 5, + mpdu_fragment_number : 4, + sw_exception : 1, + sw_exception_mpdu_delink : 1, + sw_exception_destination_ring_valid: 1, + sw_exception_destination_ring : 5, + reserved_6a : 13; + uint32_t phy_ppdu_id : 16, + reserved_7a : 4, + ring_id : 8, + looping_count : 4; +}; + +#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8 +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 + +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22 +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000 + +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27 +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000 + +#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28 +#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000 + +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0 +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 + +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2 +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c + +#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7 +#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_LSB 11 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MASK 0x00000800 + +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_LSB 12 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 + +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 + +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_LSB 14 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 + +#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 19 +#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xfff80000 + +#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_LSB 0 +#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_MASK 0x0000ffff + +#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 16 +#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000f0000 + +#define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_RING_ID_LSB 20 +#define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000 + +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28 +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_cache.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_cache.h new file mode 100644 index 0000000000000000000000000000000000000000..56304c89d5ad56b6babca26e798d482d01280116 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_cache.h @@ -0,0 +1,122 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_CACHE_H_ +#define _REO_FLUSH_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9 + +struct reo_flush_cache { + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; + uint32_t flush_addr_39_32 : 8, + forward_all_mpdus_in_queue : 1, + release_cache_block_index : 1, + cache_block_resource_index : 2, + flush_without_invalidate : 1, + block_cache_usage_after_flush : 1, + flush_entire_cache : 1, + reserved_2b : 17; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0 +#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff + +#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0 +#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff + +#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 +#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100 + +#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9 +#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200 + +#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 +#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00 + +#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12 +#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000 + +#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 +#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000 + +#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14 +#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000 + +#define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15 +#define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000 + +#define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_cache_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_cache_status.h new file mode 100644 index 0000000000000000000000000000000000000000..2030075c6cb9c6869db98e2f22165d6beaa0ae59 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_cache_status.h @@ -0,0 +1,215 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_CACHE_STATUS_H_ +#define _REO_FLUSH_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 25 + +struct reo_flush_cache_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + block_error_details : 2, + reserved_2a : 5, + cache_controller_flush_status_hit: 1, + cache_controller_flush_status_desc_type: 3, + cache_controller_flush_status_client_id: 4, + cache_controller_flush_status_error: 2, + cache_controller_flush_count : 8, + reserved_2b : 6; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_LSB 1 +#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_MASK 0x00000006 + +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_LSB 3 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_MASK 0x000000f8 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000 + +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_LSB 26 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_MASK 0xfc000000 + +#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_queue.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_queue.h new file mode 100644 index 0000000000000000000000000000000000000000..9dbfc74a6ae5165579280a65e0699d66cf23eaf5 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_queue.h @@ -0,0 +1,107 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_QUEUE_H_ +#define _REO_FLUSH_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9 + +struct reo_flush_queue { + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; + uint32_t flush_desc_addr_39_32 : 8, + block_desc_addr_usage_after_flush: 1, + block_resource_index : 2, + invalidate_queue_and_flush : 1, + reserved_2a : 20; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0 +#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0 +#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 +#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100 + +#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9 +#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600 + +#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_LSB 11 +#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_MASK 0x00000800 + +#define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 12 +#define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff000 + +#define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_queue_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_queue_status.h new file mode 100644 index 0000000000000000000000000000000000000000..612b138c390139944d6eff5360f94d578cae187d --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_queue_status.h @@ -0,0 +1,180 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_QUEUE_STATUS_H_ +#define _REO_FLUSH_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 25 + +struct reo_flush_queue_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + reserved_2a : 31; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_LSB 1 +#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_MASK 0xfffffffe + +#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_timeout_list.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_timeout_list.h new file mode 100644 index 0000000000000000000000000000000000000000..87acea7b1260be62d32f32774d0f3719caf9e0b3 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_timeout_list.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_H_ +#define _REO_FLUSH_TIMEOUT_LIST_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9 + +struct reo_flush_timeout_list { + struct uniform_reo_cmd_header cmd_header; + uint32_t ac_timout_list : 2, + reserved_1 : 30; + uint32_t minimum_release_desc_count : 16, + minimum_forward_buf_count : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_MASK 0x00000003 + +#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_MASK 0xfffffffc + +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_MASK 0xffff0000 + +#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_timeout_list_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_timeout_list_status.h new file mode 100644 index 0000000000000000000000000000000000000000..edea895c217832ccdc0c0996bb5992d99135b623 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_timeout_list_status.h @@ -0,0 +1,190 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 25 + +struct reo_flush_timeout_list_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + timout_list_empty : 1, + reserved_2a : 30; + uint32_t release_desc_count : 16, + forward_buf_count : 16; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_LSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_MASK 0x00000002 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_MASK 0xfffffffc + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_MASK 0xffff0000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_get_queue_stats.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_get_queue_stats.h new file mode 100644 index 0000000000000000000000000000000000000000..cda805b4754534f84310cc9fc6cf5b7dfdb70859 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_get_queue_stats.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_GET_QUEUE_STATS_H_ +#define _REO_GET_QUEUE_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9 + +struct reo_get_queue_stats { + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + clear_stats : 1, + reserved_2a : 23; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_LSB 8 +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_MASK 0x00000100 + +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_LSB 9 +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_MASK 0xfffffe00 + +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_LSB 0 +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_LSB 0 +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_LSB 0 +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_LSB 0 +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_LSB 0 +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_LSB 0 +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_get_queue_stats_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_get_queue_stats_status.h new file mode 100644 index 0000000000000000000000000000000000000000..02f1e74010fa3e32374ddce489d479d8efeecc18 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_get_queue_stats_status.h @@ -0,0 +1,220 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_GET_QUEUE_STATS_STATUS_H_ +#define _REO_GET_QUEUE_STATS_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 25 + +struct reo_get_queue_stats_status { + struct uniform_reo_status_header status_header; + uint32_t ssn : 12, + current_index : 8, + reserved_2 : 12; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t reserved_18 : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + window_jump_2k : 4, + hole_count : 16; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_MASK 0x00000fff + +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_MASK 0x000ff000 + +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_LSB 20 +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_MASK 0xfff00000 + +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_OFFSET 0x00000024 +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_OFFSET 0x00000028 +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_OFFSET 0x0000002c +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_OFFSET 0x00000030 +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_OFFSET 0x00000034 +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_OFFSET 0x00000038 +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_OFFSET 0x0000003c +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_OFFSET 0x00000040 +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_MASK 0x0000007f + +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_LSB 7 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_MASK 0x0000000f + +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_LSB 4 +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_MASK 0x000003f0 + +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_MASK 0xffff0000 + +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_MASK 0xff000000 + +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000054 +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000058 +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_MASK 0x0000f000 + +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_MASK 0xffff0000 + +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_unblock_cache.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_unblock_cache.h new file mode 100644 index 0000000000000000000000000000000000000000..bff80e52bae245935ef6d17a9dda176f83104bc0 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_unblock_cache.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UNBLOCK_CACHE_H_ +#define _REO_UNBLOCK_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9 + +struct reo_unblock_cache { + struct uniform_reo_cmd_header cmd_header; + uint32_t unblock_type : 1, + cache_block_resource_index : 2, + reserved_1a : 29; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_LSB 0 +#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_MASK 0x00000001 + +#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_LSB 1 +#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000006 + +#define REO_UNBLOCK_CACHE_1_RESERVED_1A_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_1_RESERVED_1A_LSB 3 +#define REO_UNBLOCK_CACHE_1_RESERVED_1A_MASK 0xfffffff8 + +#define REO_UNBLOCK_CACHE_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_2_RESERVED_2A_LSB 0 +#define REO_UNBLOCK_CACHE_2_RESERVED_2A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_3_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_3_RESERVED_3A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_4_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_4_RESERVED_4A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_5_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_5_RESERVED_5A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_6_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_6_RESERVED_6A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_7_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_7_RESERVED_7A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_8_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_unblock_cache_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_unblock_cache_status.h new file mode 100644 index 0000000000000000000000000000000000000000..cd59f3a521f4943f4e8934c41ae8b4e451ead1f2 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_unblock_cache_status.h @@ -0,0 +1,185 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UNBLOCK_CACHE_STATUS_H_ +#define _REO_UNBLOCK_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 25 + +struct reo_unblock_cache_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + unblock_type : 1, + reserved_2a : 30; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_LSB 1 +#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_MASK 0x00000002 + +#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_LSB 2 +#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_MASK 0xfffffffc + +#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_update_rx_reo_queue.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_update_rx_reo_queue.h new file mode 100644 index 0000000000000000000000000000000000000000..86f8b3566477012ed7991bb3445ddd8eac4b8cae --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_update_rx_reo_queue.h @@ -0,0 +1,317 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_H_ +#define _REO_UPDATE_RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9 + +struct reo_update_rx_reo_queue { + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + update_receive_queue_number : 1, + update_vld : 1, + update_associated_link_descriptor_counter: 1, + update_disable_duplicate_detection: 1, + update_soft_reorder_enable : 1, + update_ac : 1, + update_bar : 1, + update_rty : 1, + update_chk_2k_mode : 1, + update_oor_mode : 1, + update_ba_window_size : 1, + update_pn_check_needed : 1, + update_pn_shall_be_even : 1, + update_pn_shall_be_uneven : 1, + update_pn_handling_enable : 1, + update_pn_size : 1, + update_ignore_ampdu_flag : 1, + update_svld : 1, + update_ssn : 1, + update_seq_2k_error_detected_flag: 1, + update_pn_error_detected_flag : 1, + update_pn_valid : 1, + update_pn : 1, + clear_stat_counters : 1; + uint32_t receive_queue_number : 16, + vld : 1, + associated_link_descriptor_counter: 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + ignore_ampdu_flag : 1; + uint32_t ba_window_size : 8, + pn_size : 2, + svld : 1, + ssn : 12, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + pn_valid : 1, + flush_from_cache : 1, + reserved_4a : 5; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; +}; + +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x00000100 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_LSB 9 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_MASK 0x00000200 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_MASK 0x00001000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_MASK 0x00002000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_LSB 14 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_MASK 0x00004000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_LSB 15 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_MASK 0x00008000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_MASK 0x00020000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_LSB 18 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_MASK 0x00040000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_MASK 0x00080000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_MASK 0x00100000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x00200000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_LSB 22 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_MASK 0x00400000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_MASK 0x20000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_MASK 0x40000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_MASK 0x80000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_3_VLD_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_VLD_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_3_VLD_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000 + +#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_MASK 0x00080000 + +#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_MASK 0x00100000 + +#define REO_UPDATE_RX_REO_QUEUE_3_AC_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_AC_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_3_AC_MASK 0x00600000 + +#define REO_UPDATE_RX_REO_QUEUE_3_BAR_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_BAR_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_3_BAR_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_3_RTY_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_RTY_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_3_RTY_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_MASK 0x20000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_MASK 0x40000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_MASK 0x80000000 + +#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_MASK 0x000000ff + +#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_MASK 0x00000300 + +#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_MASK 0x00000400 + +#define REO_UPDATE_RX_REO_QUEUE_4_SSN_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_SSN_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_4_SSN_MASK 0x007ff800 + +#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_MASK 0xf8000000 + +#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_update_rx_reo_queue_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_update_rx_reo_queue_status.h new file mode 100644 index 0000000000000000000000000000000000000000..35afee0f3819e4eaf09773bbd6c1778605cc4815 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_update_rx_reo_queue_status.h @@ -0,0 +1,175 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25 + +struct reo_update_rx_reo_queue_status { + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_attention.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_attention.h new file mode 100644 index 0000000000000000000000000000000000000000..28f64d6d67b3b3bb03ce174ccdecb724c342dc2a --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_attention.h @@ -0,0 +1,282 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_ATTENTION_H_ +#define _RX_ATTENTION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_ATTENTION 3 + +struct rx_attention { + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t first_mpdu : 1, + reserved_1a : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + a_msdu_error : 1, + fragment_flag : 1, + order : 1, + cce_match : 1, + overflow_err : 1, + msdu_length_err : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + sa_idx_invalid : 1, + da_idx_invalid : 1, + reserved_1b : 1, + rx_in_tx_decrypt_byp : 1, + encrypt_required : 1, + directed : 1, + buffer_fragment : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + fcs_err : 1; + uint32_t flow_idx_timeout : 1, + flow_idx_invalid : 1, + wifi_parser_error : 1, + amsdu_parser_error : 1, + sa_idx_timeout : 1, + da_idx_timeout : 1, + msdu_limit_error : 1, + da_is_valid : 1, + da_is_mcbc : 1, + sa_is_valid : 1, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_2 : 17, + msdu_done : 1; +}; + +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_ATTENTION_0_RESERVED_0_OFFSET 0x00000000 +#define RX_ATTENTION_0_RESERVED_0_LSB 9 +#define RX_ATTENTION_0_RESERVED_0_MASK 0x0000fe00 + +#define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_ATTENTION_0_PHY_PPDU_ID_LSB 16 +#define RX_ATTENTION_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_ATTENTION_1_FIRST_MPDU_OFFSET 0x00000004 +#define RX_ATTENTION_1_FIRST_MPDU_LSB 0 +#define RX_ATTENTION_1_FIRST_MPDU_MASK 0x00000001 + +#define RX_ATTENTION_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_ATTENTION_1_RESERVED_1A_LSB 1 +#define RX_ATTENTION_1_RESERVED_1A_MASK 0x00000002 + +#define RX_ATTENTION_1_MCAST_BCAST_OFFSET 0x00000004 +#define RX_ATTENTION_1_MCAST_BCAST_LSB 2 +#define RX_ATTENTION_1_MCAST_BCAST_MASK 0x00000004 + +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET 0x00000004 +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK 0x00000008 + +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET 0x00000004 +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB 4 +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK 0x00000010 + +#define RX_ATTENTION_1_POWER_MGMT_OFFSET 0x00000004 +#define RX_ATTENTION_1_POWER_MGMT_LSB 5 +#define RX_ATTENTION_1_POWER_MGMT_MASK 0x00000020 + +#define RX_ATTENTION_1_NON_QOS_OFFSET 0x00000004 +#define RX_ATTENTION_1_NON_QOS_LSB 6 +#define RX_ATTENTION_1_NON_QOS_MASK 0x00000040 + +#define RX_ATTENTION_1_NULL_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_1_NULL_DATA_LSB 7 +#define RX_ATTENTION_1_NULL_DATA_MASK 0x00000080 + +#define RX_ATTENTION_1_MGMT_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_1_MGMT_TYPE_LSB 8 +#define RX_ATTENTION_1_MGMT_TYPE_MASK 0x00000100 + +#define RX_ATTENTION_1_CTRL_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_1_CTRL_TYPE_LSB 9 +#define RX_ATTENTION_1_CTRL_TYPE_MASK 0x00000200 + +#define RX_ATTENTION_1_MORE_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_1_MORE_DATA_LSB 10 +#define RX_ATTENTION_1_MORE_DATA_MASK 0x00000400 + +#define RX_ATTENTION_1_EOSP_OFFSET 0x00000004 +#define RX_ATTENTION_1_EOSP_LSB 11 +#define RX_ATTENTION_1_EOSP_MASK 0x00000800 + +#define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET 0x00000004 +#define RX_ATTENTION_1_A_MSDU_ERROR_LSB 12 +#define RX_ATTENTION_1_A_MSDU_ERROR_MASK 0x00001000 + +#define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET 0x00000004 +#define RX_ATTENTION_1_FRAGMENT_FLAG_LSB 13 +#define RX_ATTENTION_1_FRAGMENT_FLAG_MASK 0x00002000 + +#define RX_ATTENTION_1_ORDER_OFFSET 0x00000004 +#define RX_ATTENTION_1_ORDER_LSB 14 +#define RX_ATTENTION_1_ORDER_MASK 0x00004000 + +#define RX_ATTENTION_1_CCE_MATCH_OFFSET 0x00000004 +#define RX_ATTENTION_1_CCE_MATCH_LSB 15 +#define RX_ATTENTION_1_CCE_MATCH_MASK 0x00008000 + +#define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_OVERFLOW_ERR_LSB 16 +#define RX_ATTENTION_1_OVERFLOW_ERR_MASK 0x00010000 + +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB 17 +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK 0x00020000 + +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 + +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB 19 +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK 0x00080000 + +#define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_1_SA_IDX_INVALID_LSB 20 +#define RX_ATTENTION_1_SA_IDX_INVALID_MASK 0x00100000 + +#define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_1_DA_IDX_INVALID_LSB 21 +#define RX_ATTENTION_1_DA_IDX_INVALID_MASK 0x00200000 + +#define RX_ATTENTION_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_ATTENTION_1_RESERVED_1B_LSB 22 +#define RX_ATTENTION_1_RESERVED_1B_MASK 0x00400000 + +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 + +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET 0x00000004 +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB 24 +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK 0x01000000 + +#define RX_ATTENTION_1_DIRECTED_OFFSET 0x00000004 +#define RX_ATTENTION_1_DIRECTED_LSB 25 +#define RX_ATTENTION_1_DIRECTED_MASK 0x02000000 + +#define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET 0x00000004 +#define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB 26 +#define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK 0x04000000 + +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB 27 +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK 0x08000000 + +#define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_TKIP_MIC_ERR_LSB 28 +#define RX_ATTENTION_1_TKIP_MIC_ERR_MASK 0x10000000 + +#define RX_ATTENTION_1_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_DECRYPT_ERR_LSB 29 +#define RX_ATTENTION_1_DECRYPT_ERR_MASK 0x20000000 + +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 + +#define RX_ATTENTION_1_FCS_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_FCS_ERR_LSB 31 +#define RX_ATTENTION_1_FCS_ERR_MASK 0x80000000 + +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB 0 +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK 0x00000001 + +#define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB 1 +#define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK 0x00000002 + +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB 2 +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK 0x00000004 + +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB 3 +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK 0x00000008 + +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB 4 +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK 0x00000010 + +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB 5 +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK 0x00000020 + +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB 6 +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK 0x00000040 + +#define RX_ATTENTION_2_DA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IS_VALID_LSB 7 +#define RX_ATTENTION_2_DA_IS_VALID_MASK 0x00000080 + +#define RX_ATTENTION_2_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IS_MCBC_LSB 8 +#define RX_ATTENTION_2_DA_IS_MCBC_MASK 0x00000100 + +#define RX_ATTENTION_2_SA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_SA_IS_VALID_LSB 9 +#define RX_ATTENTION_2_SA_IS_VALID_MASK 0x00000200 + +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET 0x00000008 +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB 10 +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK 0x00001c00 + +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008 +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 + +#define RX_ATTENTION_2_RESERVED_2_OFFSET 0x00000008 +#define RX_ATTENTION_2_RESERVED_2_LSB 14 +#define RX_ATTENTION_2_RESERVED_2_MASK 0x7fffc000 + +#define RX_ATTENTION_2_MSDU_DONE_OFFSET 0x00000008 +#define RX_ATTENTION_2_MSDU_DONE_LSB 31 +#define RX_ATTENTION_2_MSDU_DONE_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_flow_search_entry.h new file mode 100644 index 0000000000000000000000000000000000000000..fea3afad657ea20230e76af7a79d4424d32dfaf4 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_flow_search_entry.h @@ -0,0 +1,157 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_FLOW_SEARCH_ENTRY_H_ +#define _RX_FLOW_SEARCH_ENTRY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 + +struct rx_flow_search_entry { + uint32_t src_ip_127_96 : 32; + uint32_t src_ip_95_64 : 32; + uint32_t src_ip_63_32 : 32; + uint32_t src_ip_31_0 : 32; + uint32_t dest_ip_127_96 : 32; + uint32_t dest_ip_95_64 : 32; + uint32_t dest_ip_63_32 : 32; + uint32_t dest_ip_31_0 : 32; + uint32_t src_port : 16, + dest_port : 16; + uint32_t l4_protocol : 8, + valid : 1, + reserved_9 : 15, + reo_destination_indication : 5, + msdu_drop : 1, + reo_destination_handler : 2; + uint32_t metadata : 32; + uint32_t aggregation_count : 7, + lro_eligible : 1, + msdu_count : 24; + uint32_t msdu_byte_count : 32; + uint32_t timestamp : 32; + uint32_t cumulative_l4_checksum : 16, + cumulative_ip_length : 16; + uint32_t tcp_sequence_number : 32; +}; + +#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_OFFSET 0x00000000 +#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_OFFSET 0x00000004 +#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_OFFSET 0x00000008 +#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_OFFSET 0x0000000c +#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_OFFSET 0x00000010 +#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_OFFSET 0x00000014 +#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_OFFSET 0x00000018 +#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_OFFSET 0x0000001c +#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_MASK 0x000000ff + +#define RX_FLOW_SEARCH_ENTRY_9_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_VALID_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_9_VALID_MASK 0x00000100 + +#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_LSB 9 +#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_MASK 0x00fffe00 + +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_LSB 24 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_MASK 0x1f000000 + +#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_LSB 29 +#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_MASK 0x20000000 + +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_LSB 30 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_MASK 0xc0000000 + +#define RX_FLOW_SEARCH_ENTRY_10_METADATA_OFFSET 0x00000028 +#define RX_FLOW_SEARCH_ENTRY_10_METADATA_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_10_METADATA_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_MASK 0x0000007f + +#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_LSB 7 +#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_MASK 0x00000080 + +#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_MASK 0xffffff00 + +#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_OFFSET 0x00000030 +#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_OFFSET 0x00000034 +#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c +#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_location_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_location_info.h new file mode 100644 index 0000000000000000000000000000000000000000..49a98519e03299c227b87f0b7aeaef40f86023fa --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_location_info.h @@ -0,0 +1,207 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_LOCATION_INFO_H_ +#define _RX_LOCATION_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_LOCATION_INFO 9 + +struct rx_location_info { + uint32_t rtt_fac_legacy : 16, + rtt_fac_legacy_ext80 : 16; + uint32_t rtt_fac_vht : 16, + rtt_fac_vht_ext80 : 16; + uint32_t rtt_fac_legacy_status : 1, + rtt_fac_legacy_ext80_status : 1, + rtt_fac_vht_status : 1, + rtt_fac_vht_ext80_status : 1, + rtt_fac_sifs : 12, + rtt_fac_sifs_status : 2, + rtt_cfr_status : 1, + rtt_cir_status : 1, + rtt_channel_dump_size : 11, + rtt_hw_ifft_mode : 1; + uint32_t rtt_btcf_status : 1, + rtt_preamble_type : 5, + rtt_pkt_bw_leg : 2, + rtt_pkt_bw_vht : 2, + rtt_gi_type : 2, + rtt_mcs_rate : 5, + rtt_strongest_chain : 3, + rtt_strongest_chain_ext80 : 3, + rtt_rx_chain_mask : 8, + reserved_3 : 1; + uint32_t rx_start_ts : 32; + uint32_t rx_end_ts : 32; + uint32_t sfo_phase_pkt_start : 12, + sfo_phase_pkt_end : 12, + rtt_che_buffer_pointer_high8 : 8; + uint32_t rtt_che_buffer_pointer_low32 : 32; + uint32_t rtt_cfo_measurement : 14, + rtt_chan_spread : 8, + rtt_timing_backoff_sel : 2, + reserved_8 : 7, + rx_location_info_valid : 1; +}; + +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_OFFSET 0x00000000 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_LSB 0 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_MASK 0x0000ffff + +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000000 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_LSB 16 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 + +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_OFFSET 0x00000004 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_LSB 0 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_MASK 0x0000ffff + +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_OFFSET 0x00000004 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_LSB 16 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_MASK 0xffff0000 + +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_LSB 0 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 + +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 + +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_LSB 2 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_MASK 0x00000004 + +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_LSB 3 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 + +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_LSB 4 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_MASK 0x0000fff0 + +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_LSB 16 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_MASK 0x00030000 + +#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_LSB 18 +#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_MASK 0x00040000 + +#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_LSB 19 +#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_MASK 0x00080000 + +#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_LSB 20 +#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 + +#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_LSB 31 +#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_MASK 0x80000000 + +#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_LSB 0 +#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_MASK 0x00000001 + +#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_LSB 1 +#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_MASK 0x0000003e + +#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_LSB 6 +#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_MASK 0x000000c0 + +#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_LSB 8 +#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_MASK 0x00000300 + +#define RX_LOCATION_INFO_3_RTT_GI_TYPE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_GI_TYPE_LSB 10 +#define RX_LOCATION_INFO_3_RTT_GI_TYPE_MASK 0x00000c00 + +#define RX_LOCATION_INFO_3_RTT_MCS_RATE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_MCS_RATE_LSB 12 +#define RX_LOCATION_INFO_3_RTT_MCS_RATE_MASK 0x0001f000 + +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_LSB 17 +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_MASK 0x000e0000 + +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_LSB 20 +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 + +#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_LSB 23 +#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_MASK 0x7f800000 + +#define RX_LOCATION_INFO_3_RESERVED_3_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RESERVED_3_LSB 31 +#define RX_LOCATION_INFO_3_RESERVED_3_MASK 0x80000000 + +#define RX_LOCATION_INFO_4_RX_START_TS_OFFSET 0x00000010 +#define RX_LOCATION_INFO_4_RX_START_TS_LSB 0 +#define RX_LOCATION_INFO_4_RX_START_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_5_RX_END_TS_OFFSET 0x00000014 +#define RX_LOCATION_INFO_5_RX_END_TS_LSB 0 +#define RX_LOCATION_INFO_5_RX_END_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_OFFSET 0x00000018 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_LSB 0 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_MASK 0x00000fff + +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_OFFSET 0x00000018 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_LSB 12 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_MASK 0x00fff000 + +#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x00000018 +#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 +#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 + +#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000001c +#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_LSB 0 +#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_MASK 0x00003fff + +#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_LSB 14 +#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_MASK 0x003fc000 + +#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_LSB 22 +#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 + +#define RX_LOCATION_INFO_8_RESERVED_8_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RESERVED_8_LSB 24 +#define RX_LOCATION_INFO_8_RESERVED_8_MASK 0x7f000000 + +#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_LSB 31 +#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_desc_info.h new file mode 100644 index 0000000000000000000000000000000000000000..3bca315ebb6259993696455a8db1e17b14736d5a --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_desc_info.h @@ -0,0 +1,107 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_DESC_INFO_H_ +#define _RX_MPDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 + +struct rx_mpdu_desc_info { + uint32_t msdu_count : 8, + mpdu_sequence_number : 12, + fragment_flag : 1, + mpdu_retry_bit : 1, + ampdu_flag : 1, + bar_frame : 1, + pn_fields_contain_valid_info : 1, + sa_is_valid : 1, + sa_idx_timeout : 1, + da_is_valid : 1, + da_is_mcbc : 1, + da_idx_timeout : 1, + raw_mpdu : 1, + more_fragment_flag : 1; + uint32_t peer_meta_data : 32; +}; + +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB 0 +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB 8 +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_LSB 20 +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK 0x00100000 + +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_LSB 21 +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK 0x00200000 + +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_LSB 22 +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK 0x00400000 + +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB 23 +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK 0x00800000 + +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_LSB 25 +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_MASK 0x02000000 + +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 26 +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x04000000 + +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_LSB 27 +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_MASK 0x08000000 + +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_LSB 28 +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x10000000 + +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 29 +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x20000000 + +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_LSB 30 +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_LSB 31 +#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET 0x00000004 +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB 0 +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_details.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_details.h new file mode 100644 index 0000000000000000000000000000000000000000..36216b3f25e9ee352c6c55cfa3e48cd7f3c01b0c --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_details.h @@ -0,0 +1,113 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_DETAILS_H_ +#define _RX_MPDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_desc_info.h" + +#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 + +struct rx_mpdu_details { + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +}; + +#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_end.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_end.h new file mode 100644 index 0000000000000000000000000000000000000000..8a22fcba1e6f9c1655134f4ff19a0b2470014da6 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_end.h @@ -0,0 +1,132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_END_H_ +#define _RX_MPDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_END 2 + +struct rx_mpdu_end { + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t reserved_1a : 11, + unsup_ktype_short_frame : 1, + rx_in_tx_decrypt_byp : 1, + overflow_err : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + pn_fields_contain_valid_info : 1, + fcs_err : 1, + msdu_length_err : 1, + rxdma0_destination_ring : 2, + rxdma1_destination_ring : 2, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_1b : 3; +}; + +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MPDU_END_0_RESERVED_0_LSB 9 +#define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00 + +#define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MPDU_END_1_RESERVED_1A_LSB 0 +#define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff + +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11 +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 + +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12 +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 + +#define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13 +#define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000 + +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14 +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000 + +#define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15 +#define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000 + +#define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_DECRYPT_ERR_LSB 16 +#define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000 + +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17 +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 + +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 + +#define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_FCS_ERR_LSB 19 +#define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000 + +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20 +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000 + +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21 +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000 + +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23 +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000 + +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004 +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25 +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000 + +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28 +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000 + +#define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_MPDU_END_1_RESERVED_1B_LSB 29 +#define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_info.h new file mode 100644 index 0000000000000000000000000000000000000000..c95fde7332c4eb70b0cdf84db4c21b5d1d423932 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_info.h @@ -0,0 +1,537 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_INFO_H_ +#define _RX_MPDU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rxpt_classify_info.h" + +#define NUM_OF_DWORDS_RX_MPDU_INFO 23 + +struct rx_mpdu_info { + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + receive_queue_number : 16, + pre_delim_err_warning : 1, + first_delim_err : 1, + reserved_2a : 6; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t epd_en : 1, + all_frames_shall_be_encrypted : 1, + encrypt_type : 4, + wep_key_width_for_variable_key : 2, + __reserved_g_0003 : 2, + bssid_hit : 1, + bssid_number : 4, + tid : 4, + reserved_7a : 13; + uint32_t peer_meta_data : 32; + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + ndp_frame : 1, + phy_err : 1, + phy_err_during_mpdu_header : 1, + protocol_version_err : 1, + ast_based_lookup_valid : 1, + reserved_9a : 2, + phy_ppdu_id : 16; + uint32_t ast_index : 16, + sw_peer_id : 16; + uint32_t mpdu_frame_control_valid : 1, + mpdu_duration_valid : 1, + mac_addr_ad1_valid : 1, + mac_addr_ad2_valid : 1, + mac_addr_ad3_valid : 1, + mac_addr_ad4_valid : 1, + mpdu_sequence_control_valid : 1, + mpdu_qos_control_valid : 1, + mpdu_ht_control_valid : 1, + frame_encryption_info_valid : 1, + mpdu_fragment_number : 4, + more_fragment_flag : 1, + reserved_11a : 1, + fr_ds : 1, + to_ds : 1, + encrypted : 1, + mpdu_retry : 1, + mpdu_sequence_number : 12; + uint32_t key_id_octet : 8, + new_peer_entry : 1, + decrypt_needed : 1, + decap_type : 2, + rx_insert_vlan_c_tag_padding : 1, + rx_insert_vlan_s_tag_padding : 1, + strip_vlan_c_tag_decap : 1, + strip_vlan_s_tag_decap : 1, + pre_delim_count : 12, + ampdu_flag : 1, + bar_frame : 1, + raw_mpdu : 1, + reserved_12 : 1; + uint32_t mpdu_length : 14, + first_mpdu : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + fragment_flag : 1, + order : 1, + u_apsd_trigger : 1, + encrypt_required : 1, + directed : 1, + amsdu_present : 1, + reserved_13 : 1; + uint32_t mpdu_frame_control_field : 16, + mpdu_duration_field : 16; + uint32_t mac_addr_ad1_31_0 : 32; + uint32_t mac_addr_ad1_47_32 : 16, + mac_addr_ad2_15_0 : 16; + uint32_t mac_addr_ad2_47_16 : 32; + uint32_t mac_addr_ad3_31_0 : 32; + uint32_t mac_addr_ad3_47_32 : 16, + mpdu_sequence_control_field : 16; + uint32_t mac_addr_ad4_31_0 : 32; + uint32_t mac_addr_ad4_47_32 : 16, + mpdu_qos_control_field : 16; + uint32_t mpdu_ht_control_field : 32; +}; + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 + +#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_MASK 0x02000000 + +#define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RESERVED_2A_LSB 26 +#define RX_MPDU_INFO_2_RESERVED_2A_MASK 0xfc000000 + +#define RX_MPDU_INFO_3_PN_31_0_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_PN_31_0_LSB 0 +#define RX_MPDU_INFO_3_PN_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_4_PN_63_32_OFFSET 0x00000010 +#define RX_MPDU_INFO_4_PN_63_32_LSB 0 +#define RX_MPDU_INFO_4_PN_63_32_MASK 0xffffffff + +#define RX_MPDU_INFO_5_PN_95_64_OFFSET 0x00000014 +#define RX_MPDU_INFO_5_PN_95_64_LSB 0 +#define RX_MPDU_INFO_5_PN_95_64_MASK 0xffffffff + +#define RX_MPDU_INFO_6_PN_127_96_OFFSET 0x00000018 +#define RX_MPDU_INFO_6_PN_127_96_LSB 0 +#define RX_MPDU_INFO_6_PN_127_96_MASK 0xffffffff + +#define RX_MPDU_INFO_7_EPD_EN_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_EPD_EN_LSB 0 +#define RX_MPDU_INFO_7_EPD_EN_MASK 0x00000001 + +#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +#define RX_MPDU_INFO_7_ENCRYPT_TYPE_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_INFO_7_ENCRYPT_TYPE_MASK 0x0000003c + +#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +#define RX_MPDU_INFO_7_BSSID_HIT_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_BSSID_HIT_LSB 10 +#define RX_MPDU_INFO_7_BSSID_HIT_MASK 0x00000400 + +#define RX_MPDU_INFO_7_BSSID_NUMBER_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_BSSID_NUMBER_LSB 11 +#define RX_MPDU_INFO_7_BSSID_NUMBER_MASK 0x00007800 + +#define RX_MPDU_INFO_7_TID_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_TID_LSB 15 +#define RX_MPDU_INFO_7_TID_MASK 0x00078000 + +#define RX_MPDU_INFO_7_RESERVED_7A_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_RESERVED_7A_LSB 19 +#define RX_MPDU_INFO_7_RESERVED_7A_MASK 0xfff80000 + +#define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 +#define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff + +#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_INFO_9_NDP_FRAME_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_NDP_FRAME_LSB 9 +#define RX_MPDU_INFO_9_NDP_FRAME_MASK 0x00000200 + +#define RX_MPDU_INFO_9_PHY_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PHY_ERR_LSB 10 +#define RX_MPDU_INFO_9_PHY_ERR_MASK 0x00000400 + +#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +#define RX_MPDU_INFO_9_RESERVED_9A_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_RESERVED_9A_LSB 14 +#define RX_MPDU_INFO_9_RESERVED_9A_MASK 0x0000c000 + +#define RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_INFO_9_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_10_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_INFO_10_AST_INDEX_LSB 0 +#define RX_MPDU_INFO_10_AST_INDEX_MASK 0x0000ffff + +#define RX_MPDU_INFO_10_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_INFO_10_SW_PEER_ID_LSB 16 +#define RX_MPDU_INFO_10_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_MASK 0x00000002 + +#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_INFO_11_RESERVED_11A_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_RESERVED_11A_LSB 15 +#define RX_MPDU_INFO_11_RESERVED_11A_MASK 0x00008000 + +#define RX_MPDU_INFO_11_FR_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_FR_DS_LSB 16 +#define RX_MPDU_INFO_11_FR_DS_MASK 0x00010000 + +#define RX_MPDU_INFO_11_TO_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_TO_DS_LSB 17 +#define RX_MPDU_INFO_11_TO_DS_MASK 0x00020000 + +#define RX_MPDU_INFO_11_ENCRYPTED_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_ENCRYPTED_LSB 18 +#define RX_MPDU_INFO_11_ENCRYPTED_MASK 0x00040000 + +#define RX_MPDU_INFO_11_MPDU_RETRY_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_RETRY_LSB 19 +#define RX_MPDU_INFO_11_MPDU_RETRY_MASK 0x00080000 + +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +#define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 + +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 + +#define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 +#define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 + +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 + +#define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 +#define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 + +#define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 +#define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 + +#define RX_MPDU_INFO_12_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RAW_MPDU_LSB 30 +#define RX_MPDU_INFO_12_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RESERVED_12_LSB 31 +#define RX_MPDU_INFO_12_RESERVED_12_MASK 0x80000000 + +#define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 +#define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff + +#define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 +#define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 + +#define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 +#define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 + +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 + +#define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 +#define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 + +#define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_NON_QOS_LSB 19 +#define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 + +#define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_NULL_DATA_LSB 20 +#define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 + +#define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 +#define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 + +#define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 +#define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 + +#define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MORE_DATA_LSB 23 +#define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 + +#define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_EOSP_LSB 24 +#define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 + +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 + +#define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_ORDER_LSB 26 +#define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 + +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 + +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 + +#define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_DIRECTED_LSB 29 +#define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 + +#define RX_MPDU_INFO_13_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_INFO_13_AMSDU_PRESENT_MASK 0x40000000 + +#define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_RESERVED_13_LSB 31 +#define RX_MPDU_INFO_13_RESERVED_13_MASK 0x80000000 + +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_link_ptr.h new file mode 100644 index 0000000000000000000000000000000000000000..2abf815d92a05eac1c0cb3493f8c54cc1175cd2d --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_link_ptr.h @@ -0,0 +1,51 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_LINK_PTR_H_ +#define _RX_MPDU_LINK_PTR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 + +struct rx_mpdu_link_ptr { + struct buffer_addr_info mpdu_link_desc_addr_info; +}; + +#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_start.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..6ba62e26d35539318659b0c6ef67f5e9fd7d497e --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_start.h @@ -0,0 +1,443 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_START_H_ +#define _RX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_info.h" + +#define NUM_OF_DWORDS_RX_MPDU_START 23 + +struct rx_mpdu_start { + struct rx_mpdu_info rx_mpdu_info_details; +}; + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 + +#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000 + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc000000 + +#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000c +#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 +#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff + +#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000010 +#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 +#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff + +#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000014 +#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 +#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff + +#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x00000018 +#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 +#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 10 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000400 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 11 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00007800 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_LSB 15 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_MASK 0x00078000 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 19 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff80000 + +#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 14 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000c000 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff + +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x00008000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x80000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_LSB 24 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_LSB 26 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x40000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 31 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x80000000 + +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_desc_info.h new file mode 100644 index 0000000000000000000000000000000000000000..085d111db807e8e06c791c4c99f883bf248b637b --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_desc_info.h @@ -0,0 +1,127 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_DESC_INFO_H_ +#define _RX_MSDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2 + +struct rx_msdu_desc_info { + uint32_t first_msdu_in_mpdu_flag : 1, + last_msdu_in_mpdu_flag : 1, + msdu_continuation : 1, + msdu_length : 14, + reo_destination_indication : 5, + msdu_drop : 1, + sa_is_valid : 1, + sa_idx_timeout : 1, + da_is_valid : 1, + da_is_mcbc : 1, + da_idx_timeout : 1, + l3_header_padding_msb : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + raw_mpdu : 1; + uint32_t sa_idx_or_sw_peer_id_14_0 : 15, + mpdu_ast_idx_or_sw_peer_id_14_0 : 15, + fr_ds : 1, + to_ds : 1; +}; + +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB 22 +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB 23 +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB 25 +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB 26 +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_RAW_MPDU_LSB 31 +#define RX_MSDU_DESC_INFO_0_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_DESC_INFO_1_FR_DS_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_FR_DS_LSB 30 +#define RX_MSDU_DESC_INFO_1_FR_DS_MASK 0x40000000 + +#define RX_MSDU_DESC_INFO_1_TO_DS_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_TO_DS_LSB 31 +#define RX_MSDU_DESC_INFO_1_TO_DS_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_details.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_details.h new file mode 100644 index 0000000000000000000000000000000000000000..70f0aa00145b06e88b46d9557a7e327adde0e537 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_details.h @@ -0,0 +1,129 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_DETAILS_H_ +#define _RX_MSDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_msdu_desc_info.h" + +#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 + +struct rx_msdu_details { + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; +}; + +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_end.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_end.h new file mode 100644 index 0000000000000000000000000000000000000000..03f1714d66ef4dd0aff9d27e9709cdd2ba16d04f --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_end.h @@ -0,0 +1,322 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_END_H_ +#define _RX_MSDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_END 17 + +struct rx_msdu_end { + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t ip_hdr_chksum : 16, + reported_mpdu_length : 14, + reserved_1a : 2; + uint32_t key_id_octet : 8, + cce_super_rule : 6, + cce_classify_not_done_truncate : 1, + cce_classify_not_done_cce_dis : 1, + cumulative_l3_checksum : 16; + uint32_t rule_indication_31_0 : 32; + uint32_t rule_indication_63_32 : 32; + uint32_t da_offset : 6, + sa_offset : 6, + da_offset_valid : 1, + sa_offset_valid : 1, + reserved_5a : 2, + l3_type : 16; + uint32_t ipv6_options_crc : 32; + uint32_t tcp_seq_number : 32; + uint32_t tcp_ack_number : 32; + uint32_t tcp_flag : 9, + lro_eligible : 1, + reserved_9a : 6, + window_size : 16; + uint32_t tcp_udp_chksum : 16, + sa_idx_timeout : 1, + da_idx_timeout : 1, + msdu_limit_error : 1, + flow_idx_timeout : 1, + flow_idx_invalid : 1, + wifi_parser_error : 1, + amsdu_parser_error : 1, + sa_is_valid : 1, + da_is_valid : 1, + da_is_mcbc : 1, + l3_header_padding : 2, + first_msdu : 1, + last_msdu : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1; + uint32_t sa_idx : 16, + da_idx_or_sw_peer_id : 16; + uint32_t msdu_drop : 1, + reo_destination_indication : 5, + flow_idx : 20, + reserved_12a : 6; + uint32_t fse_metadata : 32; + uint32_t cce_metadata : 16, + sa_sw_peer_id : 16; + uint32_t aggregation_count : 8, + flow_aggregation_continuation : 1, + fisa_timeout : 1, + reserved_15a : 22; + uint32_t cumulative_l4_checksum : 16, + cumulative_ip_length : 16; +}; + +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_END_0_RESERVED_0_LSB 9 +#define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 + +#define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 +#define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 +#define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff + +#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_LSB 16 +#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_MASK 0x3fff0000 + +#define RX_MSDU_END_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_END_1_RESERVED_1A_LSB 30 +#define RX_MSDU_END_1_RESERVED_1A_MASK 0xc0000000 + +#define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 +#define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 +#define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 +#define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 + +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 + +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 + +#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008 +#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_LSB 16 +#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000 + +#define RX_MSDU_END_3_RULE_INDICATION_31_0_OFFSET 0x0000000c +#define RX_MSDU_END_3_RULE_INDICATION_31_0_LSB 0 +#define RX_MSDU_END_3_RULE_INDICATION_31_0_MASK 0xffffffff + +#define RX_MSDU_END_4_RULE_INDICATION_63_32_OFFSET 0x00000010 +#define RX_MSDU_END_4_RULE_INDICATION_63_32_LSB 0 +#define RX_MSDU_END_4_RULE_INDICATION_63_32_MASK 0xffffffff + +#define RX_MSDU_END_5_DA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_OFFSET_LSB 0 +#define RX_MSDU_END_5_DA_OFFSET_MASK 0x0000003f + +#define RX_MSDU_END_5_SA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_5_SA_OFFSET_LSB 6 +#define RX_MSDU_END_5_SA_OFFSET_MASK 0x00000fc0 + +#define RX_MSDU_END_5_DA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_OFFSET_VALID_LSB 12 +#define RX_MSDU_END_5_DA_OFFSET_VALID_MASK 0x00001000 + +#define RX_MSDU_END_5_SA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_SA_OFFSET_VALID_LSB 13 +#define RX_MSDU_END_5_SA_OFFSET_VALID_MASK 0x00002000 + +#define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 +#define RX_MSDU_END_5_RESERVED_5A_LSB 14 +#define RX_MSDU_END_5_RESERVED_5A_MASK 0x0000c000 + +#define RX_MSDU_END_5_L3_TYPE_OFFSET 0x00000014 +#define RX_MSDU_END_5_L3_TYPE_LSB 16 +#define RX_MSDU_END_5_L3_TYPE_MASK 0xffff0000 + +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff + +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 +#define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 +#define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff + +#define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 +#define RX_MSDU_END_9_TCP_FLAG_LSB 0 +#define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff + +#define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 +#define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 +#define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 + +#define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 +#define RX_MSDU_END_9_RESERVED_9A_LSB 10 +#define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 + +#define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 +#define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 +#define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 + +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET 0x00000028 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB 0 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK 0x0000ffff + +#define RX_MSDU_END_10_SA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_10_SA_IDX_TIMEOUT_LSB 16 +#define RX_MSDU_END_10_SA_IDX_TIMEOUT_MASK 0x00010000 + +#define RX_MSDU_END_10_DA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_IDX_TIMEOUT_LSB 17 +#define RX_MSDU_END_10_DA_IDX_TIMEOUT_MASK 0x00020000 + +#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_OFFSET 0x00000028 +#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_LSB 18 +#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_MASK 0x00040000 + +#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB 19 +#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK 0x00080000 + +#define RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_FLOW_IDX_INVALID_LSB 20 +#define RX_MSDU_END_10_FLOW_IDX_INVALID_MASK 0x00100000 + +#define RX_MSDU_END_10_WIFI_PARSER_ERROR_OFFSET 0x00000028 +#define RX_MSDU_END_10_WIFI_PARSER_ERROR_LSB 21 +#define RX_MSDU_END_10_WIFI_PARSER_ERROR_MASK 0x00200000 + +#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_OFFSET 0x00000028 +#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_LSB 22 +#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_MASK 0x00400000 + +#define RX_MSDU_END_10_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_SA_IS_VALID_LSB 23 +#define RX_MSDU_END_10_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_END_10_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_IS_VALID_LSB 24 +#define RX_MSDU_END_10_DA_IS_VALID_MASK 0x01000000 + +#define RX_MSDU_END_10_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_IS_MCBC_LSB 25 +#define RX_MSDU_END_10_DA_IS_MCBC_MASK 0x02000000 + +#define RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET 0x00000028 +#define RX_MSDU_END_10_L3_HEADER_PADDING_LSB 26 +#define RX_MSDU_END_10_L3_HEADER_PADDING_MASK 0x0c000000 + +#define RX_MSDU_END_10_FIRST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_10_FIRST_MSDU_LSB 28 +#define RX_MSDU_END_10_FIRST_MSDU_MASK 0x10000000 + +#define RX_MSDU_END_10_LAST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_10_LAST_MSDU_LSB 29 +#define RX_MSDU_END_10_LAST_MSDU_MASK 0x20000000 + +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_END_10_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_END_10_IP_CHKSUM_FAIL_LSB 31 +#define RX_MSDU_END_10_IP_CHKSUM_FAIL_MASK 0x80000000 + +#define RX_MSDU_END_11_SA_IDX_OFFSET 0x0000002c +#define RX_MSDU_END_11_SA_IDX_LSB 0 +#define RX_MSDU_END_11_SA_IDX_MASK 0x0000ffff + +#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c +#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB 16 +#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MSDU_END_12_MSDU_DROP_OFFSET 0x00000030 +#define RX_MSDU_END_12_MSDU_DROP_LSB 0 +#define RX_MSDU_END_12_MSDU_DROP_MASK 0x00000001 + +#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET 0x00000030 +#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB 1 +#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK 0x0000003e + +#define RX_MSDU_END_12_FLOW_IDX_OFFSET 0x00000030 +#define RX_MSDU_END_12_FLOW_IDX_LSB 6 +#define RX_MSDU_END_12_FLOW_IDX_MASK 0x03ffffc0 + +#define RX_MSDU_END_12_RESERVED_12A_OFFSET 0x00000030 +#define RX_MSDU_END_12_RESERVED_12A_LSB 26 +#define RX_MSDU_END_12_RESERVED_12A_MASK 0xfc000000 + +#define RX_MSDU_END_13_FSE_METADATA_OFFSET 0x00000034 +#define RX_MSDU_END_13_FSE_METADATA_LSB 0 +#define RX_MSDU_END_13_FSE_METADATA_MASK 0xffffffff + +#define RX_MSDU_END_14_CCE_METADATA_OFFSET 0x00000038 +#define RX_MSDU_END_14_CCE_METADATA_LSB 0 +#define RX_MSDU_END_14_CCE_METADATA_MASK 0x0000ffff + +#define RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET 0x00000038 +#define RX_MSDU_END_14_SA_SW_PEER_ID_LSB 16 +#define RX_MSDU_END_14_SA_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET 0x0000003c +#define RX_MSDU_END_15_AGGREGATION_COUNT_LSB 0 +#define RX_MSDU_END_15_AGGREGATION_COUNT_MASK 0x000000ff + +#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c +#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB 8 +#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100 + +#define RX_MSDU_END_15_FISA_TIMEOUT_OFFSET 0x0000003c +#define RX_MSDU_END_15_FISA_TIMEOUT_LSB 9 +#define RX_MSDU_END_15_FISA_TIMEOUT_MASK 0x00000200 + +#define RX_MSDU_END_15_RESERVED_15A_OFFSET 0x0000003c +#define RX_MSDU_END_15_RESERVED_15A_LSB 10 +#define RX_MSDU_END_15_RESERVED_15A_MASK 0xfffffc00 + +#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000040 +#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB 0 +#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff + +#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET 0x00000040 +#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_link.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_link.h new file mode 100644 index 0000000000000000000000000000000000000000..f068d4b9c4b765b0477a04ec7399803274a6168d --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_link.h @@ -0,0 +1,659 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_LINK_H_ +#define _RX_MSDU_LINK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "buffer_addr_info.h" +#include "rx_msdu_details.h" + +#define NUM_OF_DWORDS_RX_MSDU_LINK 32 + +struct rx_msdu_link { + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t receive_queue_number : 16, + first_rx_msdu_link_struct : 1, + reserved_3a : 15; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +}; + +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 +#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 + +#define RX_MSDU_LINK_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_RESERVED_3A_LSB 17 +#define RX_MSDU_LINK_3_RESERVED_3A_MASK 0xfffe0000 + +#define RX_MSDU_LINK_4_PN_31_0_OFFSET 0x00000010 +#define RX_MSDU_LINK_4_PN_31_0_LSB 0 +#define RX_MSDU_LINK_4_PN_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_5_PN_63_32_OFFSET 0x00000014 +#define RX_MSDU_LINK_5_PN_63_32_LSB 0 +#define RX_MSDU_LINK_5_PN_63_32_MASK 0xffffffff + +#define RX_MSDU_LINK_6_PN_95_64_OFFSET 0x00000018 +#define RX_MSDU_LINK_6_PN_95_64_LSB 0 +#define RX_MSDU_LINK_6_PN_95_64_MASK 0xffffffff + +#define RX_MSDU_LINK_7_PN_127_96_OFFSET 0x0000001c +#define RX_MSDU_LINK_7_PN_127_96_LSB 0 +#define RX_MSDU_LINK_7_PN_127_96_MASK 0xffffffff + +#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_start.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..44aec32984825db3e92ff9c16a4fef87e2e59bfc --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_start.h @@ -0,0 +1,232 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_START_H_ +#define _RX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_START 9 + +struct rx_msdu_start { + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t msdu_length : 14, + reserved_1a : 1, + ipsec_esp : 1, + l3_offset : 7, + ipsec_ah : 1, + l4_offset : 8; + uint32_t msdu_number : 8, + decap_format : 2, + ipv4_proto : 1, + ipv6_proto : 1, + tcp_proto : 1, + udp_proto : 1, + ip_frag : 1, + tcp_only_ack : 1, + da_is_bcast_mcast : 1, + toeplitz_hash_sel : 2, + ip_fixed_header_valid : 1, + ip_extn_header_valid : 1, + tcp_udp_header_valid : 1, + mesh_control_present : 1, + ldpc : 1, + ip4_protocol_ip6_next_header : 8; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t flow_id_toeplitz : 32; + uint32_t user_rssi : 8, + pkt_type : 4, + stbc : 1, + sgi : 2, + rate_mcs : 4, + receive_bandwidth : 2, + reception_type : 3, + mimo_ss_bitmap : 8; + uint32_t ppdu_start_timestamp : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t vlan_ctag_ci : 16, + vlan_stag_ci : 16; +}; + +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MSDU_START_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_START_0_RESERVED_0_LSB 9 +#define RX_MSDU_START_0_RESERVED_0_MASK 0x0000fe00 + +#define RX_MSDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_START_0_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_START_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MSDU_START_1_MSDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_START_1_MSDU_LENGTH_LSB 0 +#define RX_MSDU_START_1_MSDU_LENGTH_MASK 0x00003fff + +#define RX_MSDU_START_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_START_1_RESERVED_1A_LSB 14 +#define RX_MSDU_START_1_RESERVED_1A_MASK 0x00004000 + +#define RX_MSDU_START_1_IPSEC_ESP_OFFSET 0x00000004 +#define RX_MSDU_START_1_IPSEC_ESP_LSB 15 +#define RX_MSDU_START_1_IPSEC_ESP_MASK 0x00008000 + +#define RX_MSDU_START_1_L3_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_1_L3_OFFSET_LSB 16 +#define RX_MSDU_START_1_L3_OFFSET_MASK 0x007f0000 + +#define RX_MSDU_START_1_IPSEC_AH_OFFSET 0x00000004 +#define RX_MSDU_START_1_IPSEC_AH_LSB 23 +#define RX_MSDU_START_1_IPSEC_AH_MASK 0x00800000 + +#define RX_MSDU_START_1_L4_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_1_L4_OFFSET_LSB 24 +#define RX_MSDU_START_1_L4_OFFSET_MASK 0xff000000 + +#define RX_MSDU_START_2_MSDU_NUMBER_OFFSET 0x00000008 +#define RX_MSDU_START_2_MSDU_NUMBER_LSB 0 +#define RX_MSDU_START_2_MSDU_NUMBER_MASK 0x000000ff + +#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_START_2_DECAP_FORMAT_LSB 8 +#define RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 + +#define RX_MSDU_START_2_IPV4_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_IPV4_PROTO_LSB 10 +#define RX_MSDU_START_2_IPV4_PROTO_MASK 0x00000400 + +#define RX_MSDU_START_2_IPV6_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_IPV6_PROTO_LSB 11 +#define RX_MSDU_START_2_IPV6_PROTO_MASK 0x00000800 + +#define RX_MSDU_START_2_TCP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_PROTO_LSB 12 +#define RX_MSDU_START_2_TCP_PROTO_MASK 0x00001000 + +#define RX_MSDU_START_2_UDP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_UDP_PROTO_LSB 13 +#define RX_MSDU_START_2_UDP_PROTO_MASK 0x00002000 + +#define RX_MSDU_START_2_IP_FRAG_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_FRAG_LSB 14 +#define RX_MSDU_START_2_IP_FRAG_MASK 0x00004000 + +#define RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_START_2_TCP_ONLY_ACK_MASK 0x00008000 + +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_OFFSET 0x00000008 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_MASK 0x00010000 + +#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_OFFSET 0x00000008 +#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_MASK 0x00060000 + +#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_MASK 0x00080000 + +#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_MASK 0x00100000 + +#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_MASK 0x00200000 + +#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_OFFSET 0x00000008 +#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_MASK 0x00400000 + +#define RX_MSDU_START_2_LDPC_OFFSET 0x00000008 +#define RX_MSDU_START_2_LDPC_LSB 23 +#define RX_MSDU_START_2_LDPC_MASK 0x00800000 + +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000 + +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000c +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff + +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET 0x00000010 +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK 0xffffffff + +#define RX_MSDU_START_5_USER_RSSI_OFFSET 0x00000014 +#define RX_MSDU_START_5_USER_RSSI_LSB 0 +#define RX_MSDU_START_5_USER_RSSI_MASK 0x000000ff + +#define RX_MSDU_START_5_PKT_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_5_PKT_TYPE_LSB 8 +#define RX_MSDU_START_5_PKT_TYPE_MASK 0x00000f00 + +#define RX_MSDU_START_5_STBC_OFFSET 0x00000014 +#define RX_MSDU_START_5_STBC_LSB 12 +#define RX_MSDU_START_5_STBC_MASK 0x00001000 + +#define RX_MSDU_START_5_SGI_OFFSET 0x00000014 +#define RX_MSDU_START_5_SGI_LSB 13 +#define RX_MSDU_START_5_SGI_MASK 0x00006000 + +#define RX_MSDU_START_5_RATE_MCS_OFFSET 0x00000014 +#define RX_MSDU_START_5_RATE_MCS_LSB 15 +#define RX_MSDU_START_5_RATE_MCS_MASK 0x00078000 + +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET 0x00000014 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB 19 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK 0x00180000 + +#define RX_MSDU_START_5_RECEPTION_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_5_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_START_5_RECEPTION_TYPE_MASK 0x00e00000 + +#define RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET 0x00000014 +#define RX_MSDU_START_5_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_START_5_MIMO_SS_BITMAP_MASK 0xff000000 + +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_OFFSET 0x00000018 +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_LSB 0 +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_MASK 0xffffffff + +#define RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET 0x0000001c +#define RX_MSDU_START_7_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_7_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_MSDU_START_8_VLAN_CTAG_CI_OFFSET 0x00000020 +#define RX_MSDU_START_8_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_START_8_VLAN_CTAG_CI_MASK 0x0000ffff + +#define RX_MSDU_START_8_VLAN_STAG_CI_OFFSET 0x00000020 +#define RX_MSDU_START_8_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_START_8_VLAN_STAG_CI_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_end_user_stats.h new file mode 100644 index 0000000000000000000000000000000000000000..f7b1ed9093469c0dfc0ea842d305a3f3be3f673f --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_end_user_stats.h @@ -0,0 +1,406 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_END_USER_STATS_H_ +#define _RX_PPDU_END_USER_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" + +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 23 + +struct rx_ppdu_end_user_stats { + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t sta_full_aid : 13, + mcs : 4, + nss : 3, + ofdma_info_valid : 1, + dl_ofdma_ru_start_index : 7, + reserved_1a : 4; + uint32_t dl_ofdma_ru_width : 7, + reserved_2a : 1, + user_receive_quality : 8, + mpdu_cnt_fcs_err : 10, + wbm2rxdma_buf_source_used : 1, + fw2rxdma_buf_source_used : 1, + sw2rxdma_buf_source_used : 1, + reserved_2b : 3; + uint32_t mpdu_cnt_fcs_ok : 9, + frame_control_info_valid : 1, + qos_control_info_valid : 1, + ht_control_info_valid : 1, + data_sequence_control_info_valid: 1, + ht_control_info_null_valid : 1, + reserved_3a : 2, + rxdma2reo_ring_used : 1, + rxdma2fw_ring_used : 1, + rxdma2sw_ring_used : 1, + rxdma_release_ring_used : 1, + ht_control_field_pkt_type : 4, + reserved_3b : 8; + uint32_t ast_index : 16, + frame_control_field : 16; + uint32_t first_data_seq_ctrl : 16, + qos_control_field : 16; + uint32_t ht_control_field : 32; + uint32_t fcs_ok_bitmap_31_0 : 32; + uint32_t fcs_ok_bitmap_63_32 : 32; + uint32_t udp_msdu_count : 16, + tcp_msdu_count : 16; + uint32_t other_msdu_count : 16, + tcp_ack_msdu_count : 16; + uint32_t sw_response_reference_ptr : 32; + uint32_t received_qos_data_tid_bitmap : 16, + received_qos_data_tid_eosp_bitmap: 16; + uint32_t qosctrl_15_8_tid0 : 8, + qosctrl_15_8_tid1 : 8, + qosctrl_15_8_tid2 : 8, + qosctrl_15_8_tid3 : 8; + uint32_t qosctrl_15_8_tid4 : 8, + qosctrl_15_8_tid5 : 8, + qosctrl_15_8_tid6 : 8, + qosctrl_15_8_tid7 : 8; + uint32_t qosctrl_15_8_tid8 : 8, + qosctrl_15_8_tid9 : 8, + qosctrl_15_8_tid10 : 8, + qosctrl_15_8_tid11 : 8; + uint32_t qosctrl_15_8_tid12 : 8, + qosctrl_15_8_tid13 : 8, + qosctrl_15_8_tid14 : 8, + qosctrl_15_8_tid15 : 8; + uint32_t mpdu_ok_byte_count : 25, + ampdu_delim_ok_count_6_0 : 7; + uint32_t ampdu_delim_err_count : 25, + ampdu_delim_ok_count_13_7 : 7; + uint32_t mpdu_err_byte_count : 25, + ampdu_delim_ok_count_20_14 : 7; + uint32_t non_consecutive_delimiter_err : 16, + reserved_20a : 16; + uint32_t ht_control_null_field : 32; + uint32_t sw_response_reference_ptr_ext : 32; +}; + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_LSB 0 +#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_MASK 0x00001fff + +#define RX_PPDU_END_USER_STATS_1_MCS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_MCS_LSB 13 +#define RX_PPDU_END_USER_STATS_1_MCS_MASK 0x0001e000 + +#define RX_PPDU_END_USER_STATS_1_NSS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_NSS_LSB 17 +#define RX_PPDU_END_USER_STATS_1_NSS_MASK 0x000e0000 + +#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_LSB 20 +#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_MASK 0x00100000 + +#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_LSB 21 +#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_MASK 0x0fe00000 + +#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_LSB 28 +#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_MASK 0xf0000000 + +#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_LSB 0 +#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_MASK 0x0000007f + +#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_LSB 7 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_MASK 0x00000080 + +#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_LSB 8 +#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_LSB 16 +#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_MASK 0x03ff0000 + +#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_LSB 26 +#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_MASK 0x04000000 + +#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_LSB 27 +#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_MASK 0x08000000 + +#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_LSB 28 +#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_MASK 0x10000000 + +#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_LSB 29 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_MASK 0xe0000000 + +#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_LSB 0 +#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_MASK 0x000001ff + +#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_LSB 9 +#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_MASK 0x00000200 + +#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_LSB 10 +#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_MASK 0x00000400 + +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_LSB 11 +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_MASK 0x00000800 + +#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 12 +#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00001000 + +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_LSB 13 +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_MASK 0x00002000 + +#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_LSB 14 +#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_MASK 0x0000c000 + +#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_LSB 16 +#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_MASK 0x00010000 + +#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_LSB 17 +#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_MASK 0x00020000 + +#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_LSB 18 +#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_MASK 0x00040000 + +#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_LSB 19 +#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_MASK 0x00080000 + +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_LSB 20 +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x00f00000 + +#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_LSB 24 +#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_4_AST_INDEX_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_4_AST_INDEX_LSB 0 +#define RX_PPDU_END_USER_STATS_4_AST_INDEX_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_LSB 0 +#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_OFFSET 0x0000001c +#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_LSB 0 +#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_OFFSET 0x00000020 +#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_LSB 0 +#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000002c +#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_LSB 0 +#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_LSB 0 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_LSB 8 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_LSB 16 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_LSB 24 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_LSB 0 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_LSB 8 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_LSB 16 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_LSB 24 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_LSB 0 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_LSB 8 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_LSB 16 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_LSB 24 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_LSB 0 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_LSB 8 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_LSB 16 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_LSB 24 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_LSB 25 +#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_LSB 25 +#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 +#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_LSB 16 +#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_OFFSET 0x00000054 +#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x00000058 +#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 +#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h new file mode 100644 index 0000000000000000000000000000000000000000..15a74c95ee51b606549d9860274cc00ac07fd5e5 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h @@ -0,0 +1,101 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ +#define _RX_PPDU_END_USER_STATS_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" + +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 7 + +struct rx_ppdu_end_user_stats_ext { + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; + uint32_t fcs_ok_bitmap_127_96 : 32; + uint32_t fcs_ok_bitmap_159_128 : 32; + uint32_t fcs_ok_bitmap_191_160 : 32; + uint32_t fcs_ok_bitmap_223_192 : 32; + uint32_t fcs_ok_bitmap_255_224 : 32; +}; + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_start.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_start.h new file mode 100644 index 0000000000000000000000000000000000000000..3873d3b56e31766bbf204b644642ea77908a6158 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_start.h @@ -0,0 +1,52 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_START_H_ +#define _RX_PPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_PPDU_START 3 + +struct rx_ppdu_start { + uint32_t phy_ppdu_id : 16, + reserved_15 : 16; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp : 32; +}; + +#define RX_PPDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_0_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_0_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_PPDU_START_0_RESERVED_15_OFFSET 0x00000000 +#define RX_PPDU_START_0_RESERVED_15_LSB 16 +#define RX_PPDU_START_0_RESERVED_15_MASK 0xffff0000 + +#define RX_PPDU_START_1_SW_PHY_META_DATA_OFFSET 0x00000004 +#define RX_PPDU_START_1_SW_PHY_META_DATA_LSB 0 +#define RX_PPDU_START_1_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008 +#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_LSB 0 +#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_start_user_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_start_user_info.h new file mode 100644 index 0000000000000000000000000000000000000000..149db67cf91b85221e81989c7f208463e071d8e0 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_start_user_info.h @@ -0,0 +1,95 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_START_USER_INFO_H_ +#define _RX_PPDU_START_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_user_info.h" + +#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 3 + +struct rx_ppdu_start_user_info { + struct receive_user_info receive_user_info_details; +}; + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000 + +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 0 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00000001 + +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB 1 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK 0x000000fe + +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 8 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_reo_queue.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_reo_queue.h new file mode 100644 index 0000000000000000000000000000000000000000..1d9d6935a5c1ef991d7fe9e3cfa4d95f8588f137 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_reo_queue.h @@ -0,0 +1,362 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_REO_QUEUE_H_ +#define _RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" + +#define NUM_OF_DWORDS_RX_REO_QUEUE 32 + +struct rx_reo_queue { + struct uniform_descriptor_header descriptor_header; + uint32_t receive_queue_number : 16, + reserved_1b : 16; + uint32_t vld : 1, + associated_link_descriptor_counter: 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + ba_window_size : 8, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + pn_size : 2, + ignore_ampdu_flag : 1, + reserved_2b : 6; + uint32_t svld : 1, + ssn : 12, + current_index : 8, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + reserved_3a : 8, + pn_valid : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t ptr_to_next_aging_queue_31_0 : 32; + uint32_t ptr_to_next_aging_queue_39_32 : 8, + reserved_11a : 24; + uint32_t ptr_to_previous_aging_queue_31_0: 32; + uint32_t ptr_to_previous_aging_queue_39_32: 8, + reserved_13a : 24; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t reserved_23 : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + window_jump_2k : 4, + hole_count : 16; + uint32_t reserved_29 : 32; + uint32_t reserved_30 : 32; + uint32_t reserved_31 : 32; +}; + +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_REO_QUEUE_1_RESERVED_1B_LSB 16 +#define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000 + +#define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_VLD_LSB 0 +#define RX_REO_QUEUE_2_VLD_MASK 0x00000001 + +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 + +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3 +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 + +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4 +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010 + +#define RX_REO_QUEUE_2_AC_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_AC_LSB 5 +#define RX_REO_QUEUE_2_AC_MASK 0x00000060 + +#define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_BAR_LSB 7 +#define RX_REO_QUEUE_2_BAR_MASK 0x00000080 + +#define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_RTY_LSB 8 +#define RX_REO_QUEUE_2_RTY_MASK 0x00000100 + +#define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9 +#define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200 + +#define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_OOR_MODE_LSB 10 +#define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400 + +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11 +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800 + +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19 +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000 + +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20 +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000 + +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21 +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000 + +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22 +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000 + +#define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SIZE_LSB 23 +#define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000 + +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25 +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000 + +#define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_RESERVED_2B_LSB 26 +#define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000 + +#define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SVLD_LSB 0 +#define RX_REO_QUEUE_3_SVLD_MASK 0x00000001 + +#define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SSN_LSB 1 +#define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe + +#define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13 +#define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000 + +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21 +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000 + +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22 +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000 + +#define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_RESERVED_3A_LSB 23 +#define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000 + +#define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_PN_VALID_LSB 31 +#define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000 + +#define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_4_PN_31_0_LSB 0 +#define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_5_PN_63_32_LSB 0 +#define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018 +#define RX_REO_QUEUE_6_PN_95_64_LSB 0 +#define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c +#define RX_REO_QUEUE_7_PN_127_96_LSB 0 +#define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c +#define RX_REO_QUEUE_11_RESERVED_11A_LSB 8 +#define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00 + +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034 +#define RX_REO_QUEUE_13_RESERVED_13A_LSB 8 +#define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00 + +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0 +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0 +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040 +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0 +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044 +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0 +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048 +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0 +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff + +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0 +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff + +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050 +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0 +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff + +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054 +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0 +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff + +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058 +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f + +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058 +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7 +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +#define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_RESERVED_23_LSB 0 +#define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f + +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4 +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0 + +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16 +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0 +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24 +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000 + +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12 +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000 + +#define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16 +#define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074 +#define RX_REO_QUEUE_29_RESERVED_29_LSB 0 +#define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff + +#define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_30_RESERVED_30_LSB 0 +#define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff + +#define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_31_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_reo_queue_ext.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_reo_queue_ext.h new file mode 100644 index 0000000000000000000000000000000000000000..fe0a9b7cf150f2b8abb78e8483d1fb95552b9cfb --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_reo_queue_ext.h @@ -0,0 +1,308 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_REO_QUEUE_EXT_H_ +#define _RX_REO_QUEUE_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "rx_mpdu_link_ptr.h" + +#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 + +struct rx_reo_queue_ext { + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +}; + +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0 +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 +#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 +#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 +#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 +#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 +#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 +#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_rxpcu_classification_overview.h new file mode 100644 index 0000000000000000000000000000000000000000..8e8ffad90e79a11ae4fcda0a4cfb4c2c0cf5f981 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_rxpcu_classification_overview.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 + +struct rx_rxpcu_classification_overview { + uint32_t filter_pass_mpdus : 1, + filter_pass_mpdus_fcs_ok : 1, + monitor_direct_mpdus : 1, + monitor_direct_mpdus_fcs_ok : 1, + monitor_other_mpdus : 1, + monitor_other_mpdus_fcs_ok : 1, + phyrx_abort_received : 1, + reserved_0 : 9, + phy_ppdu_id : 16; +}; + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_LSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_LSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_MASK 0x0000ff80 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_LSB 16 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_timing_offset_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_timing_offset_info.h new file mode 100644 index 0000000000000000000000000000000000000000..14e630e9637b2d1f5bf6fc92eaef3b1bc3fc9ad7 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_timing_offset_info.h @@ -0,0 +1,42 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_TIMING_OFFSET_INFO_H_ +#define _RX_TIMING_OFFSET_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1 + +struct rx_timing_offset_info { + uint32_t residual_phase_offset : 12, + reserved : 20; +}; + +#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_LSB 0 +#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define RX_TIMING_OFFSET_INFO_0_RESERVED_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_0_RESERVED_LSB 12 +#define RX_TIMING_OFFSET_INFO_0_RESERVED_MASK 0xfffff000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rxpcu_ppdu_end_info.h new file mode 100644 index 0000000000000000000000000000000000000000..2db684821b4d11e03e008f8a43b3b7e3caa649c2 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rxpcu_ppdu_end_info.h @@ -0,0 +1,278 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RXPCU_PPDU_END_INFO_H_ +#define _RXPCU_PPDU_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_abort_request_info.h" +#include "macrx_abort_request_info.h" + +#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 14 + +struct rxpcu_ppdu_end_info { + uint32_t wb_timestamp_lower_32 : 32; + uint32_t wb_timestamp_upper_32 : 32; + uint32_t rx_antenna : 24, + tx_ht_vht_ack : 1, + unsupported_mu_nc : 1, + otp_txbf_disable : 1, + previous_tlv_corrupted : 1, + phyrx_abort_request_info_valid : 1, + macrx_abort_request_info_valid : 1, + reserved : 2; + uint32_t coex_bt_tx_from_start_of_rx : 1, + coex_bt_tx_after_start_of_rx : 1, + coex_wan_tx_from_start_of_rx : 1, + coex_wan_tx_after_start_of_rx : 1, + coex_wlan_tx_from_start_of_rx : 1, + coex_wlan_tx_after_start_of_rx : 1, + mpdu_delimiter_errors_seen : 1, + __reserved_g_0012 : 2, + dialog_token : 8, + follow_up_dialog_token : 8, + bb_captured_channel : 1, + bb_captured_reason : 3, + bb_captured_timeout : 1, + reserved_3 : 2; + uint32_t before_mpdu_count_passing_fcs : 10, + before_mpdu_count_failing_fcs : 10, + after_mpdu_count_passing_fcs : 10, + reserved_4 : 2; + uint32_t after_mpdu_count_failing_fcs : 10, + reserved_5 : 22; + uint32_t phy_timestamp_tx_lower_32 : 32; + uint32_t phy_timestamp_tx_upper_32 : 32; + uint32_t bb_length : 16, + bb_data : 1, + reserved_8 : 3, + first_bt_broadcast_status_details: 12; + uint32_t rx_ppdu_duration : 24, + reserved_9 : 8; + uint32_t ast_index : 16, + ast_index_valid : 1, + reserved_10 : 3, + second_bt_broadcast_status_details: 12; + struct phyrx_abort_request_info phyrx_abort_request_info_details; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint16_t pre_bt_broadcast_status_details : 12, + reserved_12a : 4; + uint32_t rx_ppdu_end_marker : 32; +}; + +#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000 +#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004 +#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_LSB 0 +#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_MASK 0x00ffffff + +#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_LSB 24 +#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_MASK 0x01000000 + +#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_LSB 25 +#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_MASK 0x02000000 + +#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_LSB 26 +#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_MASK 0x04000000 + +#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_LSB 27 +#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000 + +#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 + +#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 +#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000 + +#define RXPCU_PPDU_END_INFO_2_RESERVED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_RESERVED_LSB 30 +#define RXPCU_PPDU_END_INFO_2_RESERVED_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_LSB 0 +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_LSB 1 +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_LSB 2 +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004 + +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3 +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008 + +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4 +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010 + +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5 +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020 + +#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_LSB 6 +#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040 + +#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_LSB 9 +#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_MASK 0x0001fe00 + +#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_LSB 17 +#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000 + +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_LSB 25 +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_MASK 0x02000000 + +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_LSB 26 +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_MASK 0x1c000000 + +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_LSB 29 +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_MASK 0x20000000 + +#define RXPCU_PPDU_END_INFO_3_RESERVED_3_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_RESERVED_3_LSB 30 +#define RXPCU_PPDU_END_INFO_3_RESERVED_3_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff + +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00 + +#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 +#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000 + +#define RXPCU_PPDU_END_INFO_4_RESERVED_4_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_RESERVED_4_LSB 30 +#define RXPCU_PPDU_END_INFO_4_RESERVED_4_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff + +#define RXPCU_PPDU_END_INFO_5_RESERVED_5_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_5_RESERVED_5_LSB 10 +#define RXPCU_PPDU_END_INFO_5_RESERVED_5_MASK 0xfffffc00 + +#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018 +#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c +#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_LSB 0 +#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_MASK 0x0000ffff + +#define RXPCU_PPDU_END_INFO_8_BB_DATA_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_BB_DATA_LSB 16 +#define RXPCU_PPDU_END_INFO_8_BB_DATA_MASK 0x00010000 + +#define RXPCU_PPDU_END_INFO_8_RESERVED_8_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_RESERVED_8_LSB 17 +#define RXPCU_PPDU_END_INFO_8_RESERVED_8_MASK 0x000e0000 + +#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + +#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 0 +#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 0x00ffffff + +#define RXPCU_PPDU_END_INFO_9_RESERVED_9_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_9_RESERVED_9_LSB 24 +#define RXPCU_PPDU_END_INFO_9_RESERVED_9_MASK 0xff000000 + +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_LSB 0 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_MASK 0x0000ffff + +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_LSB 16 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_MASK 0x00010000 + +#define RXPCU_PPDU_END_INFO_10_RESERVED_10_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_RESERVED_10_LSB 17 +#define RXPCU_PPDU_END_INFO_10_RESERVED_10_MASK 0x000e0000 + +#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 10 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc00 + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000 + +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_LSB 0 +#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rxpt_classify_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rxpt_classify_info.h new file mode 100644 index 0000000000000000000000000000000000000000..8f2d34d9e13a7d17ae89dda5d9b2becc4addd28d --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rxpt_classify_info.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RXPT_CLASSIFY_INFO_H_ +#define _RXPT_CLASSIFY_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 + +struct rxpt_classify_info { + uint32_t reo_destination_indication : 5, + lmac_peer_id_msb : 2, + use_flow_id_toeplitz_clfy : 1, + pkt_selection_fp_ucast_data : 1, + pkt_selection_fp_mcast_data : 1, + pkt_selection_fp_1000 : 1, + rxdma0_source_ring_selection : 2, + rxdma0_destination_ring_selection: 2, + reserved_0b : 17; +}; + +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_LSB 0 +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_LSB 5 +#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_LSB 10 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 + +#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 + +#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_LSB 15 +#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_MASK 0xffff8000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/seq_hwio.h b/drivers/staging/fw-api/hw/wcn6450/v1/seq_hwio.h new file mode 100644 index 0000000000000000000000000000000000000000..6da319320aa426806c913fb1f65e5e48e52969d1 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/seq_hwio.h @@ -0,0 +1,57 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef __SEQ_H__ +#define __SEQ_H__ + +#include "HALhwio.h" + +#define SEQ_INH(base, regtype, reg) \ + SEQ_##regtype##_INH(base, reg) + +#define SEQ_INMH(base, regtype, reg, mask) \ + SEQ_##regtype##_INMH(base, reg, mask) + +#define SEQ_INFH(base, regtype, reg, fld) \ + (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) + +#define SEQ_OUTH(base, regtype, reg, val) \ + SEQ_##regtype##_OUTH(base, reg, val) + +#define SEQ_OUTMH(base, regtype, reg, mask, val) \ + SEQ_##regtype##_OUTMH(base, reg, mask, val) + +#define SEQ_OUTFH(base, regtype, reg, fld, val) \ + SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) + +typedef enum { + SEC, + MS, + US, + NS +} SEQ_TimeUnit; + +extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); + +extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); + +#endif + diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tcl_data_cmd.h b/drivers/staging/fw-api/hw/wcn6450/v1/tcl_data_cmd.h new file mode 100644 index 0000000000000000000000000000000000000000..bc7a04c6cd523f7ea046ac7a47a3713f1ef8029b --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tcl_data_cmd.h @@ -0,0 +1,231 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TCL_DATA_CMD_H_ +#define _TCL_DATA_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +#define NUM_OF_DWORDS_TCL_DATA_CMD 7 + +struct tcl_data_cmd { + struct buffer_addr_info buf_addr_info; + uint32_t buf_or_ext_desc_type : 1, + epd : 1, + encap_type : 2, + encrypt_type : 4, + src_buffer_swap : 1, + link_meta_swap : 1, + tqm_no_drop : 1, + reserved_2a : 1, + search_type : 2, + addrx_en : 1, + addry_en : 1, + tcl_cmd_number : 16; + uint32_t data_length : 16, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + to_fw : 1, + reserved_3a : 1, + packet_offset : 9; + uint32_t buffer_timestamp : 19, + buffer_timestamp_valid : 1, + reserved_4a : 1, + hlos_tid_overwrite : 1, + hlos_tid : 4, + lmac_id : 2, + udp_flow_override : 2, + reserved_4b : 2; + uint32_t dscp_tid_table_num : 6, + search_index : 20, + cache_set_num : 4, + mesh_enable : 2; + uint32_t reserved_6a : 20, + ring_id : 8, + looping_count : 4; +}; + +#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 0 +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001 + +#define TCL_DATA_CMD_2_EPD_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_EPD_LSB 1 +#define TCL_DATA_CMD_2_EPD_MASK 0x00000002 + +#define TCL_DATA_CMD_2_ENCAP_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ENCAP_TYPE_LSB 2 +#define TCL_DATA_CMD_2_ENCAP_TYPE_MASK 0x0000000c + +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_LSB 4 +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_MASK 0x000000f0 + +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_LSB 8 +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_MASK 0x00000100 + +#define TCL_DATA_CMD_2_LINK_META_SWAP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_LINK_META_SWAP_LSB 9 +#define TCL_DATA_CMD_2_LINK_META_SWAP_MASK 0x00000200 + +#define TCL_DATA_CMD_2_TQM_NO_DROP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_TQM_NO_DROP_LSB 10 +#define TCL_DATA_CMD_2_TQM_NO_DROP_MASK 0x00000400 + +#define TCL_DATA_CMD_2_RESERVED_2A_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_RESERVED_2A_LSB 11 +#define TCL_DATA_CMD_2_RESERVED_2A_MASK 0x00000800 + +#define TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_SEARCH_TYPE_LSB 12 +#define TCL_DATA_CMD_2_SEARCH_TYPE_MASK 0x00003000 + +#define TCL_DATA_CMD_2_ADDRX_EN_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ADDRX_EN_LSB 14 +#define TCL_DATA_CMD_2_ADDRX_EN_MASK 0x00004000 + +#define TCL_DATA_CMD_2_ADDRY_EN_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ADDRY_EN_LSB 15 +#define TCL_DATA_CMD_2_ADDRY_EN_MASK 0x00008000 + +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_LSB 16 +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_MASK 0xffff0000 + +#define TCL_DATA_CMD_3_DATA_LENGTH_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_DATA_LENGTH_LSB 0 +#define TCL_DATA_CMD_3_DATA_LENGTH_MASK 0x0000ffff + +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_LSB 16 +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_MASK 0x00010000 + +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 + +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 + +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 + +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 + +#define TCL_DATA_CMD_3_TO_FW_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TO_FW_LSB 21 +#define TCL_DATA_CMD_3_TO_FW_MASK 0x00200000 + +#define TCL_DATA_CMD_3_RESERVED_3A_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_RESERVED_3A_LSB 22 +#define TCL_DATA_CMD_3_RESERVED_3A_MASK 0x00400000 + +#define TCL_DATA_CMD_3_PACKET_OFFSET_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_PACKET_OFFSET_LSB 23 +#define TCL_DATA_CMD_3_PACKET_OFFSET_MASK 0xff800000 + +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_LSB 0 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_MASK 0x0007ffff + +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_LSB 19 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_MASK 0x00080000 + +#define TCL_DATA_CMD_4_RESERVED_4A_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_RESERVED_4A_LSB 20 +#define TCL_DATA_CMD_4_RESERVED_4A_MASK 0x00100000 + +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_LSB 21 +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_MASK 0x00200000 + +#define TCL_DATA_CMD_4_HLOS_TID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_HLOS_TID_LSB 22 +#define TCL_DATA_CMD_4_HLOS_TID_MASK 0x03c00000 + +#define TCL_DATA_CMD_4_LMAC_ID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_LMAC_ID_LSB 26 +#define TCL_DATA_CMD_4_LMAC_ID_MASK 0x0c000000 + +#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_LSB 28 +#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_MASK 0x30000000 + +#define TCL_DATA_CMD_4_RESERVED_4B_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_RESERVED_4B_LSB 30 +#define TCL_DATA_CMD_4_RESERVED_4B_MASK 0xc0000000 + +#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_LSB 0 +#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_MASK 0x0000003f + +#define TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_SEARCH_INDEX_LSB 6 +#define TCL_DATA_CMD_5_SEARCH_INDEX_MASK 0x03ffffc0 + +#define TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_CACHE_SET_NUM_LSB 26 +#define TCL_DATA_CMD_5_CACHE_SET_NUM_MASK 0x3c000000 + +#define TCL_DATA_CMD_5_MESH_ENABLE_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_MESH_ENABLE_LSB 30 +#define TCL_DATA_CMD_5_MESH_ENABLE_MASK 0xc0000000 + +#define TCL_DATA_CMD_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_RESERVED_6A_LSB 0 +#define TCL_DATA_CMD_6_RESERVED_6A_MASK 0x000fffff + +#define TCL_DATA_CMD_6_RING_ID_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_RING_ID_LSB 20 +#define TCL_DATA_CMD_6_RING_ID_MASK 0x0ff00000 + +#define TCL_DATA_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_LOOPING_COUNT_LSB 28 +#define TCL_DATA_CMD_6_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tcl_gse_cmd.h b/drivers/staging/fw-api/hw/wcn6450/v1/tcl_gse_cmd.h new file mode 100644 index 0000000000000000000000000000000000000000..21edac8b3ed05867f86005c9d19024335192ce03 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tcl_gse_cmd.h @@ -0,0 +1,112 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TCL_GSE_CMD_H_ +#define _TCL_GSE_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_GSE_CMD 7 + +struct tcl_gse_cmd { + uint32_t control_buffer_addr_31_0 : 32; + uint32_t control_buffer_addr_39_32 : 8, + gse_ctrl : 4, + gse_sel : 1, + status_destination_ring_id : 1, + swap : 1, + index_search_en : 1, + cache_set_num : 4, + reserved_1a : 12; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 20, + ring_id : 8, + looping_count : 4; +}; + +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0 +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0 +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_GSE_CTRL_LSB 8 +#define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00 + +#define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_GSE_SEL_LSB 12 +#define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000 + +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13 +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000 + +#define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_SWAP_LSB 14 +#define TCL_GSE_CMD_1_SWAP_MASK 0x00004000 + +#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_LSB 15 +#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_MASK 0x00008000 + +#define TCL_GSE_CMD_1_CACHE_SET_NUM_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_CACHE_SET_NUM_LSB 16 +#define TCL_GSE_CMD_1_CACHE_SET_NUM_MASK 0x000f0000 + +#define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_RESERVED_1A_LSB 20 +#define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xfff00000 + +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008 +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0 +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0 +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010 +#define TCL_GSE_CMD_4_RESERVED_4A_LSB 0 +#define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff + +#define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014 +#define TCL_GSE_CMD_5_RESERVED_5A_LSB 0 +#define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff + +#define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_RESERVED_6A_LSB 0 +#define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff + +#define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_RING_ID_LSB 20 +#define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000 + +#define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28 +#define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tcl_status_ring.h b/drivers/staging/fw-api/hw/wcn6450/v1/tcl_status_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..29a3520b63889c6e0842847066aefb503379154d --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tcl_status_ring.h @@ -0,0 +1,112 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TCL_STATUS_RING_H_ +#define _TCL_STATUS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_STATUS_RING 8 + +struct tcl_status_ring { + uint32_t gse_ctrl : 4, + ase_fse_sel : 1, + cache_op_res : 2, + index_search_en : 1, + msdu_cnt_n : 24; + uint32_t msdu_byte_cnt_n : 32; + uint32_t msdu_timestmp_n : 32; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t hash_indx_val : 20, + cache_set_num : 4, + reserved_5a : 8; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +}; + +#define TCL_STATUS_RING_0_GSE_CTRL_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_GSE_CTRL_LSB 0 +#define TCL_STATUS_RING_0_GSE_CTRL_MASK 0x0000000f + +#define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB 4 +#define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK 0x00000010 + +#define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_CACHE_OP_RES_LSB 5 +#define TCL_STATUS_RING_0_CACHE_OP_RES_MASK 0x00000060 + +#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_LSB 7 +#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_MASK 0x00000080 + +#define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_MSDU_CNT_N_LSB 8 +#define TCL_STATUS_RING_0_MSDU_CNT_N_MASK 0xffffff00 + +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET 0x00000004 +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB 0 +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK 0xffffffff + +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET 0x00000008 +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB 0 +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK 0xffffffff + +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB 0 +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB 0 +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB 0 +#define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK 0x000fffff + +#define TCL_STATUS_RING_5_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_CACHE_SET_NUM_LSB 20 +#define TCL_STATUS_RING_5_CACHE_SET_NUM_MASK 0x00f00000 + +#define TCL_STATUS_RING_5_RESERVED_5A_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_RESERVED_5A_LSB 24 +#define TCL_STATUS_RING_5_RESERVED_5A_MASK 0xff000000 + +#define TCL_STATUS_RING_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_STATUS_RING_6_RESERVED_6A_LSB 0 +#define TCL_STATUS_RING_6_RESERVED_6A_MASK 0xffffffff + +#define TCL_STATUS_RING_7_RESERVED_7A_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_RESERVED_7A_LSB 0 +#define TCL_STATUS_RING_7_RESERVED_7A_MASK 0x000fffff + +#define TCL_STATUS_RING_7_RING_ID_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_RING_ID_LSB 20 +#define TCL_STATUS_RING_7_RING_ID_MASK 0x0ff00000 + +#define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_LOOPING_COUNT_LSB 28 +#define TCL_STATUS_RING_7_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tlv_hdr.h b/drivers/staging/fw-api/hw/wcn6450/v1/tlv_hdr.h new file mode 100644 index 0000000000000000000000000000000000000000..2129cb642f08c8ac420ee3de70d944c571651e1c --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tlv_hdr.h @@ -0,0 +1,123 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TLV_HDR_H_ + +#define _TLV_HDR_H_ + +#if !defined(__ASSEMBLER__) + +#endif + +struct tlv_usr_16_hdr { + + volatile uint16_t tlv_cflg_reserved : 1, + + tlv_tag : 5, + + tlv_len : 4, + + tlv_usrid : 6; + +}; + +struct tlv_16_hdr { + + volatile uint16_t tlv_cflg_reserved : 1, + + tlv_tag : 5, + + tlv_len : 4, + + tlv_reserved : 6; + +}; + +struct tlv_usr_32_hdr { + + volatile uint32_t tlv_cflg_reserved : 1, + + tlv_tag : 9, + + tlv_len : 16, + + tlv_usrid : 6; + +}; + +struct tlv_32_hdr { + + volatile uint32_t tlv_cflg_reserved : 1, + + tlv_tag : 9, + + tlv_len : 16, + + tlv_reserved : 6; + +}; + +struct tlv_usr_42_hdr { + + volatile uint64_t tlv_compression : 1, + + tlv_tag : 9, + + tlv_len : 16, + + tlv_usrid : 6, + + tlv_reserved : 10, + + pad_42to64_bit : 22; + +}; + +struct tlv_42_hdr { + + volatile uint64_t tlv_compression : 1, + + tlv_tag : 9, + + tlv_len : 16, + + tlv_reserved : 16, + + pad_42to64_bit : 22; + +}; + +struct tlv_usr_c_42_hdr { + + volatile uint64_t tlv_compression : 1, + + tlv_ctag : 3, + + tlv_usrid : 6, + + tlv_cdata : 32, + + pad_42to64_bit : 22; + +}; + +#endif + diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tlv_tag_def.h b/drivers/staging/fw-api/hw/wcn6450/v1/tlv_tag_def.h new file mode 100644 index 0000000000000000000000000000000000000000..817873f23860cca9b3d2c0129b8d6baa71f2f814 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tlv_tag_def.h @@ -0,0 +1,528 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TLV_TAG_DEF_ +#define _TLV_TAG_DEF_ + +typedef enum { + + WIFIMACTX_CBF_START_E = 0 , + WIFIPHYRX_DATA_E = 1 , + WIFIPHYRX_CBF_DATA_RESP_E = 2 , + WIFIPHYRX_ABORT_REQUEST_E = 3 , + WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , + WIFIMACTX_DATA_RESP_E = 5 , + WIFIMACTX_CBF_DATA_E = 6 , + WIFIMACTX_CBF_DONE_E = 7 , + WIFIMACRX_CBF_READ_REQUEST_E = 8 , + WIFIMACRX_CBF_DATA_REQUEST_E = 9 , + WIFIMACRX_EXPECT_NDP_RECEPTION_E = 10 , + WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 11 , + WIFIMACRX_NDP_TIMEOUT_E = 12 , + WIFIMACRX_ABORT_ACK_E = 13 , + WIFIMACRX_REQ_IMPLICIT_FB_E = 14 , + WIFIMACRX_CHAIN_MASK_E = 15 , + WIFIMACRX_NAP_USER_E = 16 , + WIFIMACRX_ABORT_REQUEST_E = 17 , + WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 18 , + WIFIPHYTX_ABORT_ACK_E = 19 , + WIFIPHYTX_ABORT_REQUEST_E = 20 , + WIFIPHYTX_PKT_END_E = 21 , + WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 22 , + WIFIPHYTX_REQUEST_CTRL_INFO_E = 23 , + WIFIPHYTX_DATA_REQUEST_E = 24 , + WIFIPHYTX_BF_CV_LOADING_DONE_E = 25 , + WIFIPHYTX_NAP_ACK_E = 26 , + WIFIPHYTX_NAP_DONE_E = 27 , + WIFIPHYTX_OFF_ACK_E = 28 , + WIFIPHYTX_ON_ACK_E = 29 , + WIFIPHYTX_SYNTH_OFF_ACK_E = 30 , + WIFIPHYTX_DEBUG16_E = 31 , + WIFIMACTX_ABORT_REQUEST_E = 32 , + WIFIMACTX_ABORT_ACK_E = 33 , + WIFIMACTX_PKT_END_E = 34 , + WIFIMACTX_PRE_PHY_DESC_E = 35 , + WIFIMACTX_BF_PARAMS_COMMON_E = 36 , + WIFIMACTX_BF_PARAMS_PER_USER_E = 37 , + WIFIMACTX_PREFETCH_CV_E = 38 , + WIFIMACTX_USER_DESC_COMMON_E = 39 , + WIFIMACTX_USER_DESC_PER_USER_E = 40 , + WIFIEXAMPLE_USER_TLV_16_E = 41 , + WIFIEXAMPLE_TLV_16_E = 42 , + WIFIMACTX_PHY_OFF_E = 43 , + WIFIMACTX_PHY_ON_E = 44 , + WIFIMACTX_SYNTH_OFF_E = 45 , + WIFIMACTX_EXPECT_CBF_COMMON_E = 46 , + WIFIMACTX_EXPECT_CBF_PER_USER_E = 47 , + WIFIMACTX_PHY_DESC_E = 48 , + WIFIMACTX_L_SIG_A_E = 49 , + WIFIMACTX_L_SIG_B_E = 50 , + WIFIMACTX_HT_SIG_E = 51 , + WIFIMACTX_VHT_SIG_A_E = 52 , + WIFIMACTX_VHT_SIG_B_SU20_E = 53 , + WIFIMACTX_VHT_SIG_B_SU40_E = 54 , + WIFIMACTX_VHT_SIG_B_SU80_E = 55 , + WIFIMACTX_VHT_SIG_B_SU160_E = 56 , + WIFIMACTX_VHT_SIG_B_MU20_E = 57 , + WIFIMACTX_VHT_SIG_B_MU40_E = 58 , + WIFIMACTX_VHT_SIG_B_MU80_E = 59 , + WIFIMACTX_VHT_SIG_B_MU160_E = 60 , + WIFIMACTX_SERVICE_E = 61 , + WIFIMACTX_HE_SIG_A_SU_E = 62 , + WIFIMACTX_HE_SIG_A_MU_DL_E = 63 , + WIFIMACTX_HE_SIG_A_MU_UL_E = 64 , + WIFIMACTX_HE_SIG_B1_MU_E = 65 , + WIFIMACTX_HE_SIG_B2_MU_E = 66 , + WIFIMACTX_HE_SIG_B2_OFDMA_E = 67 , + WIFIMACTX_DELETE_CV_E = 68 , + WIFIMACTX_MU_UPLINK_COMMON_E = 69 , + WIFIMACTX_MU_UPLINK_USER_SETUP_E = 70 , + WIFIMACTX_OTHER_TRANSMIT_INFO_E = 71 , + WIFIMACTX_PHY_NAP_E = 72 , + WIFIMACTX_DEBUG_E = 73 , + WIFIPHYRX_ABORT_ACK_E = 74 , + WIFIPHYRX_GENERATED_CBF_DETAILS_E = 75 , + WIFIPHYRX_RSSI_LEGACY_E = 76 , + WIFIPHYRX_RSSI_HT_E = 77 , + WIFIPHYRX_USER_INFO_E = 78 , + WIFIPHYRX_PKT_END_E = 79 , + WIFIPHYRX_DEBUG_E = 80 , + WIFIPHYRX_CBF_TRANSFER_DONE_E = 81 , + WIFIPHYRX_CBF_TRANSFER_ABORT_E = 82 , + WIFIPHYRX_L_SIG_A_E = 83 , + WIFIPHYRX_L_SIG_B_E = 84 , + WIFIPHYRX_HT_SIG_E = 85 , + WIFIPHYRX_VHT_SIG_A_E = 86 , + WIFIPHYRX_VHT_SIG_B_SU20_E = 87 , + WIFIPHYRX_VHT_SIG_B_SU40_E = 88 , + WIFIPHYRX_VHT_SIG_B_SU80_E = 89 , + WIFIPHYRX_VHT_SIG_B_SU160_E = 90 , + WIFIPHYRX_VHT_SIG_B_MU20_E = 91 , + WIFIPHYRX_VHT_SIG_B_MU40_E = 92 , + WIFIPHYRX_VHT_SIG_B_MU80_E = 93 , + WIFIPHYRX_VHT_SIG_B_MU160_E = 94 , + WIFIPHYRX_HE_SIG_A_SU_E = 95 , + WIFIPHYRX_HE_SIG_A_MU_DL_E = 96 , + WIFIPHYRX_HE_SIG_A_MU_UL_E = 97 , + WIFIPHYRX_HE_SIG_B1_MU_E = 98 , + WIFIPHYRX_HE_SIG_B2_MU_E = 99 , + WIFIPHYRX_HE_SIG_B2_OFDMA_E = 100 , + WIFIPHYRX_OTHER_RECEIVE_INFO_E = 101 , + WIFIPHYRX_COMMON_USER_INFO_E = 102 , + WIFIPHYRX_DATA_DONE_E = 103 , + WIFIRECEIVE_RSSI_INFO_E = 104 , + WIFIRECEIVE_USER_INFO_E = 105 , + WIFIMIMO_CONTROL_INFO_E = 106 , + WIFIRX_LOCATION_INFO_E = 107 , + WIFICOEX_TX_REQ_E = 108 , + WIFIDUMMY_E = 109 , + WIFIRX_TIMING_OFFSET_INFO_E = 110 , + WIFIEXAMPLE_TLV_32_NAME_E = 111 , + WIFIMPDU_LIMIT_E = 112 , + WIFINA_LENGTH_END_E = 113 , + WIFIOLE_BUF_STATUS_E = 114 , + WIFIPCU_PPDU_SETUP_DONE_E = 115 , + WIFIPCU_PPDU_SETUP_END_E = 116 , + WIFIPCU_PPDU_SETUP_INIT_E = 117 , + WIFIPCU_PPDU_SETUP_START_E = 118 , + WIFIPDG_FES_SETUP_E = 119 , + WIFIPDG_RESPONSE_E = 120 , + WIFIPDG_TX_REQ_E = 121 , + WIFISCH_WAIT_INSTR_E = 122 , + WIFISCHEDULER_TLV_E = 123 , + WIFITQM_FLOW_EMPTY_STATUS_E = 124 , + WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 125 , + WIFITQM_GEN_MPDU_LENGTH_LIST_E = 126 , + WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 127 , + WIFITQM_GEN_MPDUS_E = 128 , + WIFITQM_GEN_MPDUS_STATUS_E = 129 , + WIFITQM_REMOVE_MPDU_E = 130 , + WIFITQM_REMOVE_MPDU_STATUS_E = 131 , + WIFITQM_REMOVE_MSDU_E = 132 , + WIFITQM_REMOVE_MSDU_STATUS_E = 133 , + WIFITQM_UPDATE_TX_MPDU_COUNT_E = 134 , + WIFITQM_WRITE_CMD_E = 135 , + WIFIOFDMA_TRIGGER_DETAILS_E = 136 , + WIFITX_DATA_E = 137 , + WIFITX_FES_SETUP_E = 138 , + WIFIRX_PACKET_E = 139 , + WIFIEXPECTED_RESPONSE_E = 140 , + WIFITX_MPDU_END_E = 141 , + WIFITX_MPDU_START_E = 142 , + WIFITX_MSDU_END_E = 143 , + WIFITX_MSDU_START_E = 144 , + WIFITX_SW_MODE_SETUP_E = 145 , + WIFITXPCU_BUFFER_STATUS_E = 146 , + WIFITXPCU_USER_BUFFER_STATUS_E = 147 , + WIFIDATA_TO_TIME_CONFIG_E = 148 , + WIFIEXAMPLE_USER_TLV_32_E = 149 , + WIFIMPDU_INFO_E = 150 , + WIFIPDG_USER_SETUP_E = 151 , + WIFITX_11AH_SETUP_E = 152 , + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 153 , + WIFITX_PEER_ENTRY_E = 154 , + WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 155 , + WIFIEXAMPLE_STRUCT_NAME_E = 156 , + WIFIPCU_PPDU_SETUP_END_INFO_E = 157 , + WIFIPPDU_RATE_SETTING_E = 158 , + WIFIPROT_RATE_SETTING_E = 159 , + WIFIRX_MPDU_DETAILS_E = 160 , + WIFIEXAMPLE_USER_TLV_42_E = 161 , + WIFIRX_MSDU_LINK_E = 162 , + WIFIRX_REO_QUEUE_E = 163 , + WIFIADDR_SEARCH_ENTRY_E = 164 , + WIFISCHEDULER_CMD_E = 165 , + WIFITX_FLUSH_E = 166 , + WIFITQM_ENTRANCE_RING_E = 167 , + WIFITX_DATA_WORD_E = 168 , + WIFITX_MPDU_DETAILS_E = 169 , + WIFITX_MPDU_LINK_E = 170 , + WIFITX_MPDU_LINK_PTR_E = 171 , + WIFITX_MPDU_QUEUE_HEAD_E = 172 , + WIFITX_MPDU_QUEUE_EXT_E = 173 , + WIFITX_MPDU_QUEUE_EXT_PTR_E = 174 , + WIFITX_MSDU_DETAILS_E = 175 , + WIFITX_MSDU_EXTENSION_E = 176 , + WIFITX_MSDU_FLOW_E = 177 , + WIFITX_MSDU_LINK_E = 178 , + WIFITX_MSDU_LINK_ENTRY_PTR_E = 179 , + WIFIRESPONSE_RATE_SETTING_E = 180 , + WIFITXPCU_BUFFER_BASICS_E = 181 , + WIFIUNIFORM_DESCRIPTOR_HEADER_E = 182 , + WIFIUNIFORM_TQM_CMD_HEADER_E = 183 , + WIFIUNIFORM_TQM_STATUS_HEADER_E = 184 , + WIFIUSER_RATE_SETTING_E = 185 , + WIFIWBM_BUFFER_RING_E = 186 , + WIFIWBM_LINK_DESCRIPTOR_RING_E = 187 , + WIFIWBM_RELEASE_RING_E = 188 , + WIFITX_FLUSH_REQ_E = 189 , + WIFIRX_MSDU_DETAILS_E = 190 , + WIFITQM_WRITE_CMD_STATUS_E = 191 , + WIFITQM_GET_MPDU_QUEUE_STATS_E = 192 , + WIFITQM_GET_MSDU_FLOW_STATS_E = 193 , + WIFIEXAMPLE_USER_CTLV_32_E = 194 , + WIFITX_FES_STATUS_START_E = 195 , + WIFITX_FES_STATUS_USER_PPDU_E = 196 , + WIFITX_FES_STATUS_USER_RESPONSE_E = 197 , + WIFITX_FES_STATUS_END_E = 198 , + WIFIRX_TRIG_INFO_E = 199 , + WIFIRXPCU_TX_SETUP_CLEAR_E = 200 , + WIFIRX_FRAME_BITMAP_REQ_E = 201 , + WIFIRX_FRAME_BITMAP_ACK_E = 202 , + WIFICOEX_RX_STATUS_E = 203 , + WIFIRX_START_PARAM_E = 204 , + WIFIRX_PPDU_START_E = 205 , + WIFIRX_PPDU_END_E = 206 , + WIFIRX_MPDU_START_E = 207 , + WIFIRX_MPDU_END_E = 208 , + WIFIRX_MSDU_START_E = 209 , + WIFIRX_MSDU_END_E = 210 , + WIFIRX_ATTENTION_E = 211 , + WIFIRECEIVED_RESPONSE_INFO_E = 212 , + WIFIRX_PHY_SLEEP_E = 213 , + WIFIRX_HEADER_E = 214 , + WIFIRX_PEER_ENTRY_E = 215 , + WIFIRX_FLUSH_E = 216 , + WIFIRX_RESPONSE_REQUIRED_INFO_E = 217 , + WIFIRX_FRAMELESS_BAR_DETAILS_E = 218 , + WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 219 , + WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 220 , + WIFITX_CBF_INFO_E = 221 , + WIFIPCU_PPDU_SETUP_USER_E = 222 , + WIFIRX_MPDU_PCU_START_E = 223 , + WIFIRX_PM_INFO_E = 224 , + WIFIRX_USER_PPDU_END_E = 225 , + WIFIRX_PRE_PPDU_START_E = 226 , + WIFIRX_PREAMBLE_E = 227 , + WIFITX_FES_SETUP_COMPLETE_E = 228 , + WIFITX_LAST_MPDU_FETCHED_E = 229 , + WIFITXDMA_STOP_REQUEST_E = 230 , + WIFIRXPCU_SETUP_E = 231 , + WIFIRXPCU_USER_SETUP_E = 232 , + WIFITX_FES_STATUS_ACK_OR_BA_E = 233 , + WIFITQM_ACKED_MPDU_E = 234 , + WIFICOEX_TX_RESP_E = 235 , + WIFICOEX_TX_STATUS_E = 236 , + WIFIMACTX_COEX_PHY_CTRL_E = 237 , + WIFICOEX_STATUS_BROADCAST_E = 238 , + WIFIRESPONSE_START_STATUS_E = 239 , + WIFIRESPONSE_END_STATUS_E = 240 , + WIFICRYPTO_STATUS_E = 241 , + WIFIRECEIVED_TRIGGER_INFO_E = 242 , + WIFIREO_ENTRANCE_RING_E = 243 , + WIFIRX_MPDU_LINK_E = 244 , + WIFICOEX_TX_STOP_CTRL_E = 245 , + WIFIRX_PPDU_ACK_REPORT_E = 246 , + WIFIRX_PPDU_NO_ACK_REPORT_E = 247 , + WIFISCH_COEX_STATUS_E = 248 , + WIFISCHEDULER_COMMAND_STATUS_E = 249 , + WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 250 , + WIFITX_FES_STATUS_PROT_E = 251 , + WIFITX_FES_STATUS_START_PPDU_E = 252 , + WIFITX_FES_STATUS_START_PROT_E = 253 , + WIFITXPCU_PHYTX_DEBUG32_E = 254 , + WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 255 , + WIFITX_MPDU_COUNT_TRANSFER_END_E = 256 , + WIFIWHO_ANCHOR_OFFSET_E = 257 , + WIFIWHO_ANCHOR_VALUE_E = 258 , + WIFIWHO_CCE_INFO_E = 259 , + WIFIWHO_COMMIT_E = 260 , + WIFIWHO_COMMIT_DONE_E = 261 , + WIFIWHO_FLUSH_E = 262 , + WIFIWHO_L2_LLC_E = 263 , + WIFIWHO_L2_PAYLOAD_E = 264 , + WIFIWHO_L3_CHECKSUM_E = 265 , + WIFIWHO_L3_INFO_E = 266 , + WIFIWHO_L4_CHECKSUM_E = 267 , + WIFIWHO_L4_INFO_E = 268 , + WIFIWHO_MSDU_E = 269 , + WIFIWHO_MSDU_MISC_E = 270 , + WIFIWHO_PACKET_DATA_E = 271 , + WIFIWHO_PACKET_HDR_E = 272 , + WIFIWHO_PPDU_END_E = 273 , + WIFIWHO_PPDU_START_E = 274 , + WIFIWHO_TSO_E = 275 , + WIFIWHO_WMAC_HEADER_PV0_E = 276 , + WIFIWHO_WMAC_HEADER_PV1_E = 277 , + WIFIWHO_WMAC_IV_E = 278 , + WIFIMPDU_INFO_END_E = 279 , + WIFIMPDU_INFO_BITMAP_E = 280 , + WIFITX_QUEUE_EXTENSION_E = 281 , + WIFIRX_PEER_ENTRY_DETAILS_E = 282 , + WIFIRX_REO_QUEUE_REFERENCE_E = 283 , + WIFIRX_REO_QUEUE_EXT_E = 284 , + WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 285 , + WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 286 , + WIFITQM_ACKED_MPDU_STATUS_E = 287 , + WIFITQM_ADD_MSDU_STATUS_E = 288 , + WIFIRX_MPDU_LINK_PTR_E = 289 , + WIFIREO_DESTINATION_RING_E = 290 , + WIFITQM_LIST_GEN_DONE_E = 291 , + WIFIWHO_TERMINATE_E = 292 , + WIFITX_LAST_MPDU_END_E = 293 , + WIFITX_CV_DATA_E = 294 , + WIFITCL_ENTRANCE_FROM_PPE_RING_E = 295 , + WIFIPPDU_TX_END_E = 296 , + WIFIPROT_TX_END_E = 297 , + WIFIPDG_RESPONSE_RATE_SETTING_E = 298 , + WIFIMPDU_INFO_GLOBAL_END_E = 299 , + WIFITQM_SCH_INSTR_GLOBAL_END_E = 300 , + WIFIRX_PPDU_END_USER_STATS_E = 301 , + WIFIRX_PPDU_END_USER_STATS_EXT_E = 302 , + WIFINO_ACK_REPORT_E = 303 , + WIFIACK_REPORT_E = 304 , + WIFIUNIFORM_REO_CMD_HEADER_E = 305 , + WIFIREO_GET_QUEUE_STATS_E = 306 , + WIFIREO_FLUSH_QUEUE_E = 307 , + WIFIREO_FLUSH_CACHE_E = 308 , + WIFIREO_UNBLOCK_CACHE_E = 309 , + WIFIUNIFORM_REO_STATUS_HEADER_E = 310 , + WIFIREO_GET_QUEUE_STATS_STATUS_E = 311 , + WIFIREO_FLUSH_QUEUE_STATUS_E = 312 , + WIFIREO_FLUSH_CACHE_STATUS_E = 313 , + WIFIREO_UNBLOCK_CACHE_STATUS_E = 314 , + WIFITQM_FLUSH_CACHE_E = 315 , + WIFITQM_UNBLOCK_CACHE_E = 316 , + WIFITQM_FLUSH_CACHE_STATUS_E = 317 , + WIFITQM_UNBLOCK_CACHE_STATUS_E = 318 , + WIFIRX_PPDU_END_STATUS_DONE_E = 319 , + WIFIRX_STATUS_BUFFER_DONE_E = 320 , + WIFIBUFFER_ADDR_INFO_E = 321 , + WIFIRX_MSDU_DESC_INFO_E = 322 , + WIFIRX_MPDU_DESC_INFO_E = 323 , + WIFITCL_DATA_CMD_E = 324 , + WIFITCL_GSE_CMD_E = 325 , + WIFITCL_EXIT_BASE_E = 326 , + WIFITCL_COMPACT_EXIT_RING_E = 327 , + WIFITCL_REGULAR_EXIT_RING_E = 328 , + WIFITCL_EXTENDED_EXIT_RING_E = 329 , + WIFIUPLINK_COMMON_INFO_E = 330 , + WIFIUPLINK_USER_SETUP_INFO_E = 331 , + WIFITX_DATA_SYNC_E = 332 , + WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 333 , + WIFITCL_STATUS_RING_E = 334 , + WIFITQM_GET_MPDU_HEAD_INFO_E = 335 , + WIFITQM_SYNC_CMD_E = 336 , + WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 337 , + WIFITQM_SYNC_CMD_STATUS_E = 338 , + WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 339 , + WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 340 , + WIFIREO_FLUSH_TIMEOUT_LIST_E = 341 , + WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 342 , + WIFIREO_TO_PPE_RING_E = 343 , + WIFIRX_MPDU_INFO_E = 344 , + WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 345 , + WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 346 , + WIFIEXAMPLE_USER_TLV_32_NAME_E = 347 , + WIFIRX_PPDU_START_USER_INFO_E = 348 , + WIFIRX_RXPCU_CLASSIFICATION_OVERVIEW_E = 349 , + WIFIRX_RING_MASK_E = 350 , + WIFIWHO_CLASSIFY_INFO_E = 351 , + WIFITXPT_CLASSIFY_INFO_E = 352 , + WIFIRXPT_CLASSIFY_INFO_E = 353 , + WIFITX_FLOW_SEARCH_ENTRY_E = 354 , + WIFIRX_FLOW_SEARCH_ENTRY_E = 355 , + WIFIRECEIVED_TRIGGER_INFO_DETAILS_E = 356 , + WIFICOEX_MAC_NAP_E = 357 , + WIFIMACRX_ABORT_REQUEST_INFO_E = 358 , + WIFIMACTX_ABORT_REQUEST_INFO_E = 359 , + WIFIPHYRX_ABORT_REQUEST_INFO_E = 360 , + WIFIPHYTX_ABORT_REQUEST_INFO_E = 361 , + WIFIRXPCU_PPDU_END_INFO_E = 362 , + WIFIWHO_MESH_CONTROL_E = 363 , + WIFIL_SIG_A_INFO_E = 364 , + WIFIL_SIG_B_INFO_E = 365 , + WIFIHT_SIG_INFO_E = 366 , + WIFIVHT_SIG_A_INFO_E = 367 , + WIFIVHT_SIG_B_SU20_INFO_E = 368 , + WIFIVHT_SIG_B_SU40_INFO_E = 369 , + WIFIVHT_SIG_B_SU80_INFO_E = 370 , + WIFIVHT_SIG_B_SU160_INFO_E = 371 , + WIFIVHT_SIG_B_MU20_INFO_E = 372 , + WIFIVHT_SIG_B_MU40_INFO_E = 373 , + WIFIVHT_SIG_B_MU80_INFO_E = 374 , + WIFIVHT_SIG_B_MU160_INFO_E = 375 , + WIFISERVICE_INFO_E = 376 , + WIFIHE_SIG_A_SU_INFO_E = 377 , + WIFIHE_SIG_A_MU_DL_INFO_E = 378 , + WIFIHE_SIG_A_MU_UL_INFO_E = 379 , + WIFIHE_SIG_B1_MU_INFO_E = 380 , + WIFIHE_SIG_B2_MU_INFO_E = 381 , + WIFIHE_SIG_B2_OFDMA_INFO_E = 382 , + WIFIPDG_SW_MODE_BW_START_E = 383 , + WIFIPDG_SW_MODE_BW_END_E = 384 , + WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 385 , + WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 386 , + WIFISCHEDULER_END_E = 387 , + WIFIPEER_TABLE_ENTRY_E = 388 , + WIFISW_PEER_INFO_E = 389 , + WIFIRXOLE_CCE_CLASSIFY_INFO_E = 390 , + WIFITCL_CCE_CLASSIFY_INFO_E = 391 , + WIFIRXOLE_CCE_INFO_E = 392 , + WIFITCL_CCE_INFO_E = 393 , + WIFITCL_CCE_SUPERRULE_E = 394 , + WIFICCE_RULE_E = 395 , + WIFIRX_PPDU_START_DROPPED_E = 396 , + WIFIRX_PPDU_END_DROPPED_E = 397 , + WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 398 , + WIFIRX_MPDU_START_DROPPED_E = 399 , + WIFIRX_MSDU_START_DROPPED_E = 400 , + WIFIRX_MSDU_END_DROPPED_E = 401 , + WIFIRX_MPDU_END_DROPPED_E = 402 , + WIFIRX_ATTENTION_DROPPED_E = 403 , + WIFITXPCU_USER_SETUP_E = 404 , + WIFIRXPCU_USER_SETUP_EXT_E = 405 , + WIFICE_SRC_DESC_E = 406 , + WIFICE_STAT_DESC_E = 407 , + WIFIRXOLE_CCE_SUPERRULE_E = 408 , + WIFITX_RATE_STATS_INFO_E = 409 , + WIFICMD_PART_0_END_E = 410 , + WIFIMACTX_SYNTH_ON_E = 411 , + WIFISCH_CRITICAL_TLV_REFERENCE_E = 412 , + WIFITQM_MPDU_GLOBAL_START_E = 413 , + WIFIEXAMPLE_TLV_32_E = 414 , + WIFITQM_UPDATE_TX_MSDU_FLOW_E = 415 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 416 , + WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 417 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418 , + WIFIREO_UPDATE_RX_REO_QUEUE_E = 419 , + WIFICE_DST_DESC_E = 420 , + WIFITQM_MPDU_QUEUE_EMPTY_STATUS_E = 421 , + WIFITQM_2_SCH_MPDU_AVAILABLE_E = 422 , + WIFIPDG_TRIG_RESPONSE_E = 423 , + WIFITRIGGER_RESPONSE_TX_DONE_E = 424 , + WIFIABORT_FROM_PHYRX_DETAILS_E = 425 , + WIFISCH_TQM_CMD_WRAPPER_E = 426 , + WIFIMPDUS_AVAILABLE_E = 427 , + WIFIRECEIVED_RESPONSE_INFO_PART2_E = 428 , + WIFIPHYRX_PKT_END_INFO_E = 429 , + WIFIPHYRX_TX_START_TIMING_E = 430 , + WIFITXPCU_PREAMBLE_DONE_E = 431 , + WIFINDP_PREAMBLE_DONE_E = 432 , + WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 433 , + WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 434 , + WIFIMACTX_CLEAR_PREV_TX_INFO_E = 435 , + WIFITX_PUNCTURE_SETUP_E = 436 , + WIFITX_PUNCTURE_PATTERN_E = 437 , + WIFIR2R_STATUS_END_E = 438 , + WIFIMACTX_PREFETCH_CV_COMMON_E = 439 , + WIFIEND_OF_FLUSH_MARKER_E = 440 , + WIFIUPLINK_COMMON_INFO_PUNC_E = 441 , + WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 442 , + WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 443 , + WIFIRECEIVED_RESPONSE_USER_7_0_E = 444 , + WIFIRECEIVED_RESPONSE_USER_15_8_E = 445 , + WIFIRECEIVED_RESPONSE_USER_23_16_E = 446 , + WIFIRECEIVED_RESPONSE_USER_31_24_E = 447 , + WIFIRECEIVED_RESPONSE_USER_36_32_E = 448 , + WIFIRECEIVED_RESPONSE_USER_INFO_E = 449 , + WIFITX_LOOPBACK_SETUP_E = 450 , + WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 451 , + WIFISCH_WAIT_INSTR_TX_PATH_E = 452 , + WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 453 , + WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 454 , + WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 455 , + WIFITX_WUR_DATA_E = 456 , + WIFIRX_PPDU_END_START_E = 457 , + WIFIRX_PPDU_END_MIDDLE_E = 458 , + WIFIRX_PPDU_END_LAST_E = 459 , + WIFIRECEIVE_USER_INFO_L1_E = 460 , + WIFIMIMO_CONTROL_INFO_L1_E = 461 , + WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 462 , + WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 463 , + WIFISRP_INFO_E = 464 , + WIFIOBSS_SR_INFO_E = 465 , + WIFISCHEDULER_SW_MSG_STATUS_E = 466 , + WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 467 , + WIFIRXPCU_SETUP_COMPLETE_E = 468 , + WIFISNOOP_PPDU_START_E = 469 , + WIFISNOOP_MPDU_USR_DBG_INFO_E = 470 , + WIFISNOOP_MSDU_USR_DBG_INFO_E = 471 , + WIFISNOOP_MSDU_USR_DATA_E = 472 , + WIFISNOOP_MPDU_USR_STAT_INFO_E = 473 , + WIFISNOOP_PPDU_END_E = 474 , + WIFISNOOP_SPARE_E = 475 , + WIFIMACTX_PREFETCH_CV_BULK_E = 476 , + WIFIMACTX_PREFETCH_CV_BULK_USER_E = 477 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 478 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 479 , + WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 480 , + WIFISW_MONITOR_RING_E = 481 , + WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 482 , + WIFISCH_TLV_WRAPPER_E = 483 , + WIFISCHEDULER_STATUS_WRAPPER_E = 484 , + WIFIMACTX_OTHER_TRANSMIT_INFO_EXPECT_RX_E = 485 , + WIFITX_HW_MPDU_LINK_E = 486 , + WIFITX_HW_MPDU_LINK_PTR_E = 487 , + WIFITX_HW_MPDU_QUEUE_EXT_E = 488 , + WIFITX_HW_MPDU_QUEUE_HEAD_E = 489 , + WIFITQM_ADD_MPDUS_E = 490 , + WIFITQM_WRITE_BACK_MPDU_INFO_E = 491 , + WIFIUNIFORM_TQM_LITE_STATUS_HEADER_E = 492 , + WIFITQM_ADD_MPDUS_STATUS_E = 493 , + WIFITQM_MPDU_RELEASE_STATUS_E = 494 , + WIFITQM_WRITE_BACK_MPDU_INFO_STATUS_E = 495 , + WIFITX_HW_MPDU_DETAILS_E = 496 , + WIFITLV_BASE_E = 511 + +} tlv_tag_def__e; + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tx_msdu_extension.h b/drivers/staging/fw-api/hw/wcn6450/v1/tx_msdu_extension.h new file mode 100644 index 0000000000000000000000000000000000000000..f4822ae285f404d7b0008a5647468016de6cb93f --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tx_msdu_extension.h @@ -0,0 +1,247 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_MSDU_EXTENSION_H_ +#define _TX_MSDU_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 + +struct tx_msdu_extension { + uint32_t tso_enable : 1, + reserved_0a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + reserved_0b : 7; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + udp_length : 16; + uint32_t checksum_offset : 14, + partial_checksum_en : 1, + reserved_4a : 1, + payload_start_offset : 14, + reserved_4b : 2; + uint32_t payload_end_offset : 14, + reserved_5a : 2, + wds : 1, + reserved_5b : 15; + uint32_t buf0_ptr_31_0 : 32; + uint32_t buf0_ptr_39_32 : 8, + reserved_7a : 8, + buf0_len : 16; + uint32_t buf1_ptr_31_0 : 32; + uint32_t buf1_ptr_39_32 : 8, + reserved_9a : 8, + buf1_len : 16; + uint32_t buf2_ptr_31_0 : 32; + uint32_t buf2_ptr_39_32 : 8, + reserved_11a : 8, + buf2_len : 16; + uint32_t buf3_ptr_31_0 : 32; + uint32_t buf3_ptr_39_32 : 8, + reserved_13a : 8, + buf3_len : 16; + uint32_t buf4_ptr_31_0 : 32; + uint32_t buf4_ptr_39_32 : 8, + reserved_15a : 8, + buf4_len : 16; + uint32_t buf5_ptr_31_0 : 32; + uint32_t buf5_ptr_39_32 : 8, + reserved_17a : 8, + buf5_len : 16; +}; + +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0 +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001 + +#define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 1 +#define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x0000007e + +#define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80 + +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000 + +#define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25 +#define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000 + +#define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0 +#define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008 +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14 +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000 + +#define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15 +#define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000 + +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16 +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000 + +#define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30 +#define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000 + +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14 +#define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000 + +#define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_WDS_LSB 16 +#define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000 + +#define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17 +#define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000 + +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018 +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8 +#define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16 +#define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020 +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8 +#define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16 +#define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028 +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8 +#define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16 +#define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030 +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8 +#define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16 +#define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038 +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8 +#define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16 +#define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040 +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8 +#define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16 +#define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/tx_rate_stats_info.h new file mode 100644 index 0000000000000000000000000000000000000000..0e18d62733c154d9ee3d8a6ee9f2f956331eabd2 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tx_rate_stats_info.h @@ -0,0 +1,87 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_RATE_STATS_INFO_H_ +#define _TX_RATE_STATS_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 + +struct tx_rate_stats_info { + uint32_t tx_rate_stats_info_valid : 1, + transmit_bw : 2, + transmit_pkt_type : 4, + transmit_stbc : 1, + transmit_ldpc : 1, + transmit_sgi : 2, + transmit_mcs : 4, + ofdma_transmission : 1, + tones_in_ru : 12, + reserved_0a : 4; + uint32_t ppdu_transmission_tsf : 32; +}; + +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_LSB 0 +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_LSB 1 +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_MASK 0x00000006 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_LSB 3 +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_MASK 0x00000078 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_LSB 7 +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_MASK 0x00000080 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_LSB 8 +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_MASK 0x00000100 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_LSB 9 +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_MASK 0x00000600 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_LSB 11 +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_MASK 0x00007800 + +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_LSB 15 +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_MASK 0x00008000 + +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_LSB 16 +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_MASK 0x0fff0000 + +#define TX_RATE_STATS_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_RESERVED_0A_LSB 28 +#define TX_RATE_STATS_INFO_0_RESERVED_0A_MASK 0xf0000000 + +#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 +#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_LSB 0 +#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/wcn6450/v1/uniform_descriptor_header.h new file mode 100644 index 0000000000000000000000000000000000000000..d68432fde385e27fe5f04fcdf3ff62db7b58f358 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/uniform_descriptor_header.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ +#define _UNIFORM_DESCRIPTOR_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 + +struct uniform_descriptor_header { + uint32_t owner : 4, + buffer_type : 4, + reserved_0a : 24; +}; + +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB 0 +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK 0x0000000f + +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB 4 +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK 0x000000f0 + +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK 0xffffff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/uniform_reo_cmd_header.h b/drivers/staging/fw-api/hw/wcn6450/v1/uniform_reo_cmd_header.h new file mode 100644 index 0000000000000000000000000000000000000000..fdc8da7a9a5b53b3abb85c98bf363cd735fbaf0f --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/uniform_reo_cmd_header.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNIFORM_REO_CMD_HEADER_H_ +#define _UNIFORM_REO_CMD_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1 + +struct uniform_reo_cmd_header { + uint32_t reo_cmd_number : 16, + reo_status_required : 1, + reserved_0a : 15; +}; + +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_LSB 0 +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_LSB 16 +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_LSB 17 +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_MASK 0xfffe0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/uniform_reo_status_header.h b/drivers/staging/fw-api/hw/wcn6450/v1/uniform_reo_status_header.h new file mode 100644 index 0000000000000000000000000000000000000000..0f6014b64e0afc71d7f7884bbd06bad9d4c0f86a --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/uniform_reo_status_header.h @@ -0,0 +1,57 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNIFORM_REO_STATUS_HEADER_H_ +#define _UNIFORM_REO_STATUS_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2 + +struct uniform_reo_status_header { + uint32_t reo_status_number : 16, + cmd_execution_time : 10, + reo_cmd_execution_status : 2, + reserved_0a : 4; + uint32_t timestamp : 32; +}; + +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_LSB 16 +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_LSB 26 +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_LSB 28 +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_MASK 0xf0000000 + +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_OFFSET 0x00000004 +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/vht_sig_a_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/vht_sig_a_info.h new file mode 100644 index 0000000000000000000000000000000000000000..16bc396179ad8cdf561e4098a256b6cbffd2bbd3 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/vht_sig_a_info.h @@ -0,0 +1,117 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_A_INFO_H_ +#define _VHT_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 + +struct vht_sig_a_info { + uint32_t bandwidth : 2, + vhta_reserved_0 : 1, + stbc : 1, + group_id : 6, + n_sts : 12, + txop_ps_not_allowed : 1, + vhta_reserved_0b : 1, + reserved_0 : 8; + uint32_t gi_setting : 2, + su_mu_coding : 1, + ldpc_extra_symbol : 1, + mcs : 4, + beamformed : 1, + vhta_reserved_1 : 1, + crc : 8, + tail : 6, + reserved_1 : 8; +}; + +#define VHT_SIG_A_INFO_0_BANDWIDTH_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_BANDWIDTH_LSB 0 +#define VHT_SIG_A_INFO_0_BANDWIDTH_MASK 0x00000003 + +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_LSB 2 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_MASK 0x00000004 + +#define VHT_SIG_A_INFO_0_STBC_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_STBC_LSB 3 +#define VHT_SIG_A_INFO_0_STBC_MASK 0x00000008 + +#define VHT_SIG_A_INFO_0_GROUP_ID_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_GROUP_ID_LSB 4 +#define VHT_SIG_A_INFO_0_GROUP_ID_MASK 0x000003f0 + +#define VHT_SIG_A_INFO_0_N_STS_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_N_STS_LSB 10 +#define VHT_SIG_A_INFO_0_N_STS_MASK 0x003ffc00 + +#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_LSB 22 +#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_LSB 23 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_MASK 0x00800000 + +#define VHT_SIG_A_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_RESERVED_0_LSB 24 +#define VHT_SIG_A_INFO_0_RESERVED_0_MASK 0xff000000 + +#define VHT_SIG_A_INFO_1_GI_SETTING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_GI_SETTING_LSB 0 +#define VHT_SIG_A_INFO_1_GI_SETTING_MASK 0x00000003 + +#define VHT_SIG_A_INFO_1_SU_MU_CODING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_SU_MU_CODING_LSB 2 +#define VHT_SIG_A_INFO_1_SU_MU_CODING_MASK 0x00000004 + +#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_LSB 3 +#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define VHT_SIG_A_INFO_1_MCS_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_MCS_LSB 4 +#define VHT_SIG_A_INFO_1_MCS_MASK 0x000000f0 + +#define VHT_SIG_A_INFO_1_BEAMFORMED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_BEAMFORMED_LSB 8 +#define VHT_SIG_A_INFO_1_BEAMFORMED_MASK 0x00000100 + +#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_LSB 9 +#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_MASK 0x00000200 + +#define VHT_SIG_A_INFO_1_CRC_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_CRC_LSB 10 +#define VHT_SIG_A_INFO_1_CRC_MASK 0x0003fc00 + +#define VHT_SIG_A_INFO_1_TAIL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_TAIL_LSB 18 +#define VHT_SIG_A_INFO_1_TAIL_MASK 0x00fc0000 + +#define VHT_SIG_A_INFO_1_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_RESERVED_1_LSB 24 +#define VHT_SIG_A_INFO_1_RESERVED_1_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/wcn6450/v1/wbm_buffer_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..bfb268f6fbf1c0b5400034f2b0309c8d3cc33dae --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/wbm_buffer_ring.h @@ -0,0 +1,51 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_BUFFER_RING_H_ +#define _WBM_BUFFER_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 + +struct wbm_buffer_ring { + struct buffer_addr_info buf_addr_info; +}; + +#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/wcn6450/v1/wbm_link_descriptor_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..70820a174c649c58d5237ea0481b9a52119ec4d7 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/wbm_link_descriptor_ring.h @@ -0,0 +1,51 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ +#define _WBM_LINK_DESCRIPTOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 + +struct wbm_link_descriptor_ring { + struct buffer_addr_info desc_addr_info; +}; + +#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/wbm_release_ring.h b/drivers/staging/fw-api/hw/wcn6450/v1/wbm_release_ring.h new file mode 100644 index 0000000000000000000000000000000000000000..37e37b06e1ccbeeaba307fda7a1252d38d8e6d3b --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/wbm_release_ring.h @@ -0,0 +1,217 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_RELEASE_RING_H_ +#define _WBM_RELEASE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "tx_rate_stats_info.h" + +#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 + +struct wbm_release_ring { + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + first_msdu_index : 4, + tqm_release_reason : 4, + rxdma_push_reason : 2, + rxdma_error_code : 5, + reo_push_reason : 2, + reo_error_code : 5, + wbm_internal_error : 1; + uint32_t tqm_status_number : 24, + transmit_count : 7, + msdu_continuation : 1; + uint32_t ack_frame_rssi : 8, + sw_release_details_valid : 1, + first_msdu : 1, + last_msdu : 1, + msdu_part_of_amsdu : 1, + fw_tx_notify_frame : 1, + buffer_timestamp : 19; + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, + tid : 4, + ring_id : 8, + looping_count : 4; +}; + +#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_2_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_2_BM_ACTION_MASK 0x00000038 + +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_MASK 0x00001e00 + +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB 13 +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK 0x0001e000 + +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB 17 +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK 0x00060000 + +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB 19 +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK 0x00f80000 + +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB 24 +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK 0x03000000 + +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB 26 +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK 0x7c000000 + +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_LSB 0 +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_MASK 0x00ffffff + +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_LSB 24 +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_MASK 0x7f000000 + +#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB 31 +#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK 0x80000000 + +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_LSB 0 +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_MASK 0x000000ff + +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_LSB 8 +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_MASK 0x00000100 + +#define WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_FIRST_MSDU_LSB 9 +#define WBM_RELEASE_RING_4_FIRST_MSDU_MASK 0x00000200 + +#define WBM_RELEASE_RING_4_LAST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_LAST_MSDU_LSB 10 +#define WBM_RELEASE_RING_4_LAST_MSDU_MASK 0x00000400 + +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_LSB 11 +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_MASK 0x00000800 + +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_LSB 12 +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_MASK 0x00001000 + +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_LSB 13 +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_MASK 0xffffe000 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_MASK 0x00000006 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 3 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x00000078 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_LSB 7 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000080 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_LSB 8 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000100 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_LSB 9 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000600 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_LSB 11 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x00007800 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 15 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00008000 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_LSB 16 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_MASK 0x0fff0000 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_LSB 28 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_MASK 0xf0000000 + +#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#define WBM_RELEASE_RING_7_SW_PEER_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_SW_PEER_ID_LSB 0 +#define WBM_RELEASE_RING_7_SW_PEER_ID_MASK 0x0000ffff + +#define WBM_RELEASE_RING_7_TID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_TID_LSB 16 +#define WBM_RELEASE_RING_7_TID_MASK 0x000f0000 + +#define WBM_RELEASE_RING_7_RING_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_RING_ID_LSB 20 +#define WBM_RELEASE_RING_7_RING_ID_MASK 0x0ff00000 + +#define WBM_RELEASE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_7_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/wcn6450/v1/wcss_seq_hwiobase.h new file mode 100644 index 0000000000000000000000000000000000000000..65de18e53ae3aa8e87853533e7ddd2a3e76f0fd1 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/wcss_seq_hwiobase.h @@ -0,0 +1,609 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef __WCSS_SEQ_BASE_H__ +#define __WCSS_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + +#ifndef SOC_WCSS_BASE_ADDR + #if defined(WCSS_BASE) + #if ( WCSS_BASE != 0x0 ) + #error WCSS_BASE incorrectly redefined! + #endif + #endif + + #define SOC_WCSS_BASE_ADDR 0x0 +#else + #if ( SOC_WCSS_BASE_ADDR != 0x0 ) + #error SOC_WCSS_BASE_ADDR incorrectly redefined! + #endif +#endif + +#define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 +#define SEQ_WCSS_PHYA_OFFSET 0x00300000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00300000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00338000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00338400 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00338800 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00338c00 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00339000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00339400 +#define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00339800 +#define SEQ_WCSS_PHYA_WFAX_PCSS_IUSS_REG_MAP_OFFSET 0x0033f400 +#define SEQ_WCSS_PHYA_WFAX_PCSS_IUSS_COMMON_REG_MAP_OFFSET 0x0033f600 +#define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00388000 +#define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00390000 +#define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x003a0000 +#define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x003b0000 +#define SEQ_WCSS_PHYA_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00400000 +#define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x00480000 +#define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x004b0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x005cf000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x005cf400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x005cf800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x005cfc00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x005c5000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x005d1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x005d1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OTP_OFFSET 0x005d1038 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OFFSET 0x005d10cc +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x005c7000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x005c9b00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x005c7000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x005cb000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SW_RST_OFFSET 0x005d41fc +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_RAH_OFFSET 0x005d4204 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x005d43c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x005d4424 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x005d4880 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4c00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x005d5c00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6840 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6900 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6940 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6980 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d69c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d7000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d7040 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d7100 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d7140 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d7180 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d71c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x005d7400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x005d7400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x005d7438 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OFFSET 0x005d74cc +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET 0x005d8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET 0x005d8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET 0x005d8400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x005d8800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x005d8880 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x005d88c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x005d8940 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x005d8980 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x005dc000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x005dc000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DRM_REG_OFFSET 0x005dc400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET 0x005dc800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_OFFSET 0x005dcc00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_OFFSET 0x005dd000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_OFFSET 0x005dd400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x005dd800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x005dd980 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x005dd9c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x005ddac0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x005dfc00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x005dfc40 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x005dfc80 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x005dfcc0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x005dfd40 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x005e0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x005e021c +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x005e1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e21b8 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x005e4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x005e8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x005e821c +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e8400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e8800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x005ec000 +#define SEQ_WCSS_UMAC_OFFSET 0x00a00000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 +#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 +#define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 +#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 +#define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 +#define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 +#define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 +#define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 +#define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 +#define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 +#define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 +#define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 +#define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 +#define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 +#define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 +#define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 +#define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 +#define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 +#define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 +#define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 +#define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 +#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 +#define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 +#define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000 +#define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b58000 +#define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 +#define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000 +#define SEQ_WCSS_MSIP_OFFSET 0x00b80000 +#define SEQ_WCSS_MSIP_RBIST_TX_CH0_OFFSET 0x00b80000 +#define SEQ_WCSS_MSIP_WL_DAC_CH0_OFFSET 0x00b80180 +#define SEQ_WCSS_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00b80190 +#define SEQ_WCSS_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00b80200 +#define SEQ_WCSS_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x00b802c0 +#define SEQ_WCSS_MSIP_WL_ADC_CH0_OFFSET 0x00b80400 +#define SEQ_WCSS_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00b80434 +#define SEQ_WCSS_MSIP_MSIP_SHD_OTP_OFFSET 0x00b8d000 +#define SEQ_WCSS_MSIP_MSIP_TMUX_OFFSET 0x00b8d040 +#define SEQ_WCSS_MSIP_MSIP_OTP_OFFSET 0x00b8d080 +#define SEQ_WCSS_MSIP_MSIP_LDO_CTRL_OFFSET 0x00b8d0b4 +#define SEQ_WCSS_MSIP_MSIP_CLKGEN_OFFSET 0x00b8d100 +#define SEQ_WCSS_MSIP_MSIP_BIAS_OFFSET 0x00b8e000 +#define SEQ_WCSS_MSIP_BBPLL_OFFSET 0x00b8f000 +#define SEQ_WCSS_MSIP_WL_CLKGEN_OFFSET 0x00b8f800 +#define SEQ_WCSS_MSIP_MSIP_DRM_REG_OFFSET 0x00b8fc00 +#define SEQ_WCSS_DBG_OFFSET 0x00b90000 +#define SEQ_WCSS_DBG_WCSS_DBG_ROM_TABLE_OFFSET 0x00b90000 +#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 +#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 +#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000 +#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 +#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 +#define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET 0x00bb0000 +#define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb1000 +#define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET 0x00bb2000 +#define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb3000 +#define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET 0x00bb4000 +#define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb5000 +#define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00bb6000 +#define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00bb8000 +#define SEQ_WCSS_DBG_TPDM_OFFSET 0x00bb9000 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000 +#define SEQ_WCSS_DBG_TPDA_OFFSET 0x00bba000 +#define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00bbb000 +#define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00bbc000 +#define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbe000 +#define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbf000 +#define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00bc0000 +#define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00bc1000 +#define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00bc4000 +#define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00bc5000 +#define SEQ_WCSS_DBG_BTSS_PMM_FUN_CXATBFUNNEL_32W2SP_OFFSET 0x00bc9000 +#define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET 0x00bd0000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET 0x00be0000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00be0000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00be4000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00be5000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00be6000 +#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c31000 +#define SEQ_WCSS_RET_AHB_OFFSET 0x00c90000 +#define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00ca0000 +#define SEQ_WCSS_CC_OFFSET 0x00cb0000 +#define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00cc0000 + +#define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 +#define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00038000 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00038400 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00038800 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00038c00 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00039000 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00039400 +#define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00039800 +#define SEQ_WFAX_TOP_WFAX_PCSS_IUSS_REG_MAP_OFFSET 0x0003f400 +#define SEQ_WFAX_TOP_WFAX_PCSS_IUSS_COMMON_REG_MAP_OFFSET 0x0003f600 +#define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00088000 +#define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00090000 +#define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x000a0000 +#define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x000b0000 +#define SEQ_WFAX_TOP_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00100000 +#define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x00180000 +#define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x001b0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x002c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x002c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x002cf000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x002cf400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x002cf800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x002cfc00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x002c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x002c5000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x002d1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x002d1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OTP_OFFSET 0x002d1038 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OFFSET 0x002d10cc +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x002c7000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x002c9b00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x002c7000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x002cb000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x002d4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x002d4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SW_RST_OFFSET 0x002d41fc +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_RAH_OFFSET 0x002d4204 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x002d4300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x002d43c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x002d4424 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x002d4800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x002d4880 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x002d4c00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x002d5c00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x002d6800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x002d6840 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x002d6900 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x002d6940 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x002d6980 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x002d69c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x002d7000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x002d7040 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x002d7100 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x002d7140 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x002d7180 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x002d71c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x002d7c00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x002d7400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x002d7400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x002d7438 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OFFSET 0x002d74cc +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET 0x002d8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET 0x002d8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET 0x002d8400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x002d8800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x002d8880 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x002d88c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x002d8940 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x002d8980 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x002dc000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x002dc000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DRM_REG_OFFSET 0x002dc400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET 0x002dc800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_OFFSET 0x002dcc00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_OFFSET 0x002dd000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_OFFSET 0x002dd400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x002dd800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x002dd980 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x002dd9c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x002ddac0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x002dfc00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x002dfc40 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x002dfc80 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x002dfcc0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x002dfd40 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x002e0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x002e0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x002e021c +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x002e1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x002e1300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x002e21b8 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x002e4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x002e8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x002e821c +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x002e8400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x002e8800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x002e9000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x002e9300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x002ea000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x002ec000 + +#define SEQ_RFA_FROM_WSI_RFA_SOC_OFFSET 0x00000000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_TLMM_OFFSET 0x0000f400 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00 +#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TLMM_OFFSET 0x00000000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x00005000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_OFFSET 0x00011000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x00011000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_OTP_OFFSET 0x00011038 +#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_OFFSET 0x000110cc +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00009b00 +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x00007000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x0000b000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SW_RST_OFFSET 0x000141fc +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_RAH_OFFSET 0x00014204 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300 +#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000143c0 +#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_CAL_OFFSET 0x00014424 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014800 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014880 +#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014c00 +#define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET 0x00015c00 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016800 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016840 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016900 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016940 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016980 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000169c0 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00017000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00017040 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00017100 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00017140 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00017180 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000171c0 +#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00 +#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_OFFSET 0x00017400 +#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x00017400 +#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x00017438 +#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_OFFSET 0x000174cc +#define SEQ_RFA_FROM_WSI_RFA_FM_OFFSET 0x00018000 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_MC_OFFSET 0x00018000 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_RX_OFFSET 0x00018400 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BS_OFFSET 0x00018800 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x00018880 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BIST_OFFSET 0x000188c0 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_PC_OFFSET 0x00018940 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_AC_OFFSET 0x00018980 +#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TOP_OFFSET 0x0001c000 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DRM_REG_OFFSET 0x0001c400 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXBB_OFFSET 0x0001c800 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXFE_OFFSET 0x0001cc00 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXBB_OFFSET 0x0001d000 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXFE_OFFSET 0x0001d400 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x0001d800 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_OFFSET 0x0001d980 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x0001d9c0 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_MISC_OFFSET 0x0001dac0 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001fc00 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001fc40 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001fc80 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001fcc0 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x0001fd40 +#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00020000 +#define SEQ_RFA_FROM_WSI_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x0002021c +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00021000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00021300 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x000221b8 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00024000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00028000 +#define SEQ_RFA_FROM_WSI_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x0002821c +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00028400 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00028800 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00029000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00029300 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0002a000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0002c000 + +#define SEQ_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000 +#define SEQ_RFA_SOC_AO_TLMM_OFFSET 0x0000f400 +#define SEQ_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800 +#define SEQ_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00 +#define SEQ_RFA_SOC_HZ_TLMM_OFFSET 0x00000000 +#define SEQ_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x00005000 +#define SEQ_RFA_SOC_PMU_OFFSET 0x00011000 +#define SEQ_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x00011000 +#define SEQ_RFA_SOC_PMU_PMU_OTP_OFFSET 0x00011038 +#define SEQ_RFA_SOC_PMU_PMU_OFFSET 0x000110cc +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000 +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00009b00 +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x00007000 +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x0000b000 + +#define SEQ_PMU_TOP_PMU_SHD_OTP_OFFSET 0x00000000 +#define SEQ_PMU_TOP_PMU_OTP_OFFSET 0x00000038 +#define SEQ_PMU_TOP_PMU_OFFSET 0x000000cc + +#define SEQ_SECURITY_CONTROL_BT_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00002b00 +#define SEQ_SECURITY_CONTROL_BT_CMN_QFPROM_RAW_FUSE_OFFSET 0x00000000 +#define SEQ_SECURITY_CONTROL_BT_CMN_QFPROM_CORR_FUSE_OFFSET 0x00004000 + +#define SEQ_RFA_CMN_AON_OFFSET 0x00000000 +#define SEQ_RFA_CMN_RFA_SW_RST_OFFSET 0x000001fc +#define SEQ_RFA_CMN_WL_RAH_OFFSET 0x00000204 +#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 +#define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000003c0 +#define SEQ_RFA_CMN_AON_COEX_CAL_OFFSET 0x00000424 +#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000800 +#define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000880 +#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000c00 +#define SEQ_RFA_CMN_BTFMPLL_OFFSET 0x00001c00 +#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002800 +#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002840 +#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002900 +#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002940 +#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002980 +#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000029c0 +#define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00003000 +#define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00003040 +#define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00003100 +#define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00003140 +#define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00003180 +#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000031c0 +#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00 +#define SEQ_RFA_CMN_PMU_TEST_OFFSET 0x00003400 +#define SEQ_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x00003400 +#define SEQ_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x00003438 +#define SEQ_RFA_CMN_PMU_TEST_PMU_OFFSET 0x000034cc + +#define SEQ_RFA_FM_FM_MC_OFFSET 0x00000000 +#define SEQ_RFA_FM_FM_RX_OFFSET 0x00000400 +#define SEQ_RFA_FM_FM_SYNTH_BS_OFFSET 0x00000800 +#define SEQ_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x00000880 +#define SEQ_RFA_FM_FM_SYNTH_BIST_OFFSET 0x000008c0 +#define SEQ_RFA_FM_FM_SYNTH_PC_OFFSET 0x00000940 +#define SEQ_RFA_FM_FM_SYNTH_AC_OFFSET 0x00000980 + +#define SEQ_RFA_BT_BT_TOP_OFFSET 0x00000000 +#define SEQ_RFA_BT_BT_DRM_REG_OFFSET 0x00000400 +#define SEQ_RFA_BT_BT_TXBB_OFFSET 0x00000800 +#define SEQ_RFA_BT_BT_TXFE_OFFSET 0x00000c00 +#define SEQ_RFA_BT_BT_RXBB_OFFSET 0x00001000 +#define SEQ_RFA_BT_BT_RXFE_OFFSET 0x00001400 +#define SEQ_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x00001800 +#define SEQ_RFA_BT_BT_DAC_OFFSET 0x00001980 +#define SEQ_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x000019c0 +#define SEQ_RFA_BT_BT_DAC_MISC_OFFSET 0x00001ac0 +#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00003c00 +#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00003c40 +#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00003c80 +#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x00003cc0 +#define SEQ_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x00003d40 + +#define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00000000 +#define SEQ_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x0000021c +#define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00001000 +#define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00001300 +#define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x000021b8 +#define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00004000 +#define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00008000 +#define SEQ_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x0000821c +#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00008400 +#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00008800 +#define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00009000 +#define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00009300 +#define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0000a000 +#define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0000c000 + +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 +#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 +#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 +#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 + +#define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 +#define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 +#define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 +#define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 +#define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 +#define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 + +#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 +#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 +#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 +#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 +#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 +#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 +#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 +#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 +#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 +#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 +#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 +#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 +#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 + +#define SEQ_MSIP_RBIST_TX_CH0_OFFSET 0x00000000 +#define SEQ_MSIP_WL_DAC_CH0_OFFSET 0x00000180 +#define SEQ_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00000190 +#define SEQ_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00000200 +#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x000002c0 +#define SEQ_MSIP_WL_ADC_CH0_OFFSET 0x00000400 +#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00000434 +#define SEQ_MSIP_MSIP_SHD_OTP_OFFSET 0x0000d000 +#define SEQ_MSIP_MSIP_TMUX_OFFSET 0x0000d040 +#define SEQ_MSIP_MSIP_OTP_OFFSET 0x0000d080 +#define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET 0x0000d0b4 +#define SEQ_MSIP_MSIP_CLKGEN_OFFSET 0x0000d100 +#define SEQ_MSIP_MSIP_BIAS_OFFSET 0x0000e000 +#define SEQ_MSIP_BBPLL_OFFSET 0x0000f000 +#define SEQ_MSIP_WL_CLKGEN_OFFSET 0x0000f800 +#define SEQ_MSIP_MSIP_DRM_REG_OFFSET 0x0000fc00 + +#define SEQ_WCSSDBG_WCSS_DBG_ROM_TABLE_OFFSET 0x00000000 +#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 +#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 +#define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000 +#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 +#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 +#define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET 0x00020000 +#define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00021000 +#define SEQ_WCSSDBG_TLV_MACTLV_OFFSET 0x00022000 +#define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00023000 +#define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET 0x00024000 +#define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00025000 +#define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00026000 +#define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00028000 +#define SEQ_WCSSDBG_TPDM_OFFSET 0x00029000 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000 +#define SEQ_WCSSDBG_TPDA_OFFSET 0x0002a000 +#define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x0002b000 +#define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x0002c000 +#define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002e000 +#define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002f000 +#define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00030000 +#define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00031000 +#define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00034000 +#define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00035000 +#define SEQ_WCSSDBG_BTSS_PMM_FUN_CXATBFUNNEL_32W2SP_OFFSET 0x00039000 +#define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET 0x00040000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET 0x00050000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00050000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00054000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00055000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00056000 +#define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x000a1000 + +#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 +#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 + +#define SEQ_PHYA_DBG_PHYA_NOC_OFFSET 0x00000000 +#define SEQ_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000 +#define SEQ_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000 +#define SEQ_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000 + +#endif + diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/wcss_version.h b/drivers/staging/fw-api/hw/wcn6450/v1/wcss_version.h new file mode 100644 index 0000000000000000000000000000000000000000..1fe87c66bad5f8711d51510b2d85704a9d53ab51 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/wcss_version.h @@ -0,0 +1,20 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#define WCSS_VERSION 33 diff --git a/drivers/staging/iio/resolver/ad2s1210.c b/drivers/staging/iio/resolver/ad2s1210.c index aca983f34f5e2fc6b1f6185f6ab73e3c16d3cc89..f41ee9243801ed18ea5cc405ade2f7e1f902adaf 100644 --- a/drivers/staging/iio/resolver/ad2s1210.c +++ b/drivers/staging/iio/resolver/ad2s1210.c @@ -85,7 +85,7 @@ struct ad2s1210_state { static const int ad2s1210_mode_vals[4][2] = { [MOD_POS] = { 0, 0 }, [MOD_VEL] = { 0, 1 }, - [MOD_CONFIG] = { 1, 0 }, + [MOD_CONFIG] = { 1, 1 }, }; static inline void ad2s1210_set_mode(enum ad2s1210_mode mode, diff --git a/drivers/staging/ks7010/ks_wlan_net.c b/drivers/staging/ks7010/ks_wlan_net.c index f624d0d53a8f2a58fe39605a4e5081dbb0946de7..1b6226efe15ebddb2b88fb42469d30f59333712c 100644 --- a/drivers/staging/ks7010/ks_wlan_net.c +++ b/drivers/staging/ks7010/ks_wlan_net.c @@ -1584,8 +1584,10 @@ static int ks_wlan_set_encode_ext(struct net_device *dev, commit |= SME_WEP_FLAG; } if (enc->key_len) { - memcpy(&key->key_val[0], &enc->key[0], enc->key_len); - key->key_len = enc->key_len; + int key_len = clamp_val(enc->key_len, 0, IW_ENCODING_TOKEN_MAX); + + memcpy(&key->key_val[0], &enc->key[0], key_len); + key->key_len = key_len; commit |= (SME_WEP_VAL1 << index); } break; diff --git a/drivers/staging/mt7621-spi/spi-mt7621.c b/drivers/staging/mt7621-spi/spi-mt7621.c index b73823830e3a734cdb9a967e983dbbce4ef8381f..75ed48f60c8c7f461c9af98d3d49ee355c01b924 100644 --- a/drivers/staging/mt7621-spi/spi-mt7621.c +++ b/drivers/staging/mt7621-spi/spi-mt7621.c @@ -442,9 +442,11 @@ static int mt7621_spi_probe(struct platform_device *pdev) return PTR_ERR(base); clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(clk)) - return dev_err_probe(&pdev->dev, PTR_ERR(clk), - "unable to get SYS clock\n"); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n", + status); + return PTR_ERR(clk); + } status = clk_prepare_enable(clk); if (status) diff --git a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_legacy.c b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_legacy.c index 0997fccce51ae02bd90050f84695b63c8691b4c0..366069e97a25567979b72ceb27fc4b8361bf71fd 100644 --- a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_legacy.c +++ b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_legacy.c @@ -1317,7 +1317,7 @@ struct ce_ops ce_service_legacy = { #endif }; -struct ce_ops *ce_services_legacy() +struct ce_ops *ce_services_legacy(void) { return &ce_service_legacy; } diff --git a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_srng.c b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_srng.c index 32d5cfe3623c6f3340c1c6b008ef67675e6d5812..013f7d98c61998185ae775426510b85b669ce868 100644 --- a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_srng.c +++ b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_srng.c @@ -1014,7 +1014,7 @@ static struct ce_ops ce_service_srng = { #endif }; -struct ce_ops *ce_services_srng() +struct ce_ops *ce_services_srng(void) { return &ce_service_srng; } diff --git a/drivers/staging/qca-wifi-host-cmn/target_if/core/src/target_if_main.c b/drivers/staging/qca-wifi-host-cmn/target_if/core/src/target_if_main.c index a622ca425d36dbaab38388a758cfc925858cc9b2..a565aab1d547719106fd24b8301812a4f9b9fee0 100644 --- a/drivers/staging/qca-wifi-host-cmn/target_if/core/src/target_if_main.c +++ b/drivers/staging/qca-wifi-host-cmn/target_if/core/src/target_if_main.c @@ -88,7 +88,7 @@ static struct target_if_ctx *g_target_if_ctx; -struct target_if_ctx *target_if_get_ctx() +struct target_if_ctx *target_if_get_ctx(void) { return g_target_if_ctx; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_filter.c b/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_filter.c index 1c20975a94c06f4fa3bb7ca5bcf46f5aab32814b..bbde9124c273ac2920a6b1b5c6d113d8ec97faa5 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_filter.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_filter.c @@ -1179,7 +1179,9 @@ bool scm_filter_match(struct wlan_objmgr_psoc *psoc, */ if (!match && util_scan_entry_is_hidden_ap(db_entry)) { for (i = 0; i < filter->num_of_auth; i++) { - if (filter->auth_type[i] == WLAN_AUTH_TYPE_OWE) { + if (filter->auth_type[i] == WLAN_AUTH_TYPE_OWE && + util_is_bssid_match(&filter->bssid_hint, + &db_entry->bssid)) { match = true; break; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_extscan_api.c b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_extscan_api.c index 9bfacca33021ec044e788f197a97a5f1fcdf3060..60bf653a7e7f78407318066f3ca4d1e2c9fc9d6f 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_extscan_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_extscan_api.c @@ -100,7 +100,7 @@ wlan_extscan_global_init(struct wlan_objmgr_psoc *psoc, } QDF_STATUS -wlan_extscan_global_deinit() +wlan_extscan_global_deinit(void) { return QDF_STATUS_SUCCESS; } diff --git a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c index 2d332ec9191b376fe8ad81b864313bda0483e768..b1ccd9b7034eb6fc4f6e174f18b9deac33c01f4d 100644 --- a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c +++ b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/drivers/staging/qcacld-3.0/Kbuild b/drivers/staging/qcacld-3.0/Kbuild index 2d2026eb6490627654acb457643e4a37e911194b..ed0072de671bdf0b8144b02fbee88a6c2a9c3a7e 100644 --- a/drivers/staging/qcacld-3.0/Kbuild +++ b/drivers/staging/qcacld-3.0/Kbuild @@ -3238,7 +3238,7 @@ ccflags-y += -DWLAN_PDEV_MAX_VDEVS=$(CONFIG_WLAN_PDEV_MAX_VDEVS) CONFIG_WLAN_PSOC_MAX_VDEVS ?= $(CONFIG_WLAN_MAX_VDEVS) ccflags-y += -DWLAN_PSOC_MAX_VDEVS=$(CONFIG_WLAN_PSOC_MAX_VDEVS) -CONFIG_MAX_SCAN_CACHE_SIZE ?= 300 +CONFIG_MAX_SCAN_CACHE_SIZE ?= 500 ccflags-y += -DMAX_SCAN_CACHE_SIZE=$(CONFIG_MAX_SCAN_CACHE_SIZE) CONFIG_SCAN_MAX_REST_TIME ?= 0 ccflags-y += -DSCAN_MAX_REST_TIME=$(CONFIG_SCAN_MAX_REST_TIME) diff --git a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h index 849658669e620a94d5ccb20e2fe2c2d27db84bc9..46a6a4ff82c0944ef799c006fcd9064cfb6d6fbb 100644 --- a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h +++ b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2750,6 +2750,22 @@ QDF_STATUS policy_mgr_get_updated_scan_and_fw_mode_config( uint32_t *fw_mode_config, uint32_t dual_mac_disable_ini, uint32_t channel_select_logic_conc); +/** + * policy_mgr_is_sta_present_on_dfs_channel() - to find whether any DFS STA is + * present + * @psoc: PSOC object information + * @vdev_id: pointer to vdev_id. It will be filled with the vdev_id of DFS STA + * @ch_freq: pointer to channel frequency on which DFS STA is present + * @ch_width: pointer channel width on which DFS STA is connected + * If any STA is connected on DFS channel then this function will return true + * + * Return: true if session is on DFS or false if session is on non-dfs channel + */ +bool policy_mgr_is_sta_present_on_dfs_channel(struct wlan_objmgr_psoc *psoc, + uint8_t *vdev_id, + qdf_freq_t *ch_freq, + enum hw_mode_bandwidth *ch_width); + /** * policy_mgr_is_safe_channel - Check if the channel is in LTE * coex channel avoidance list @@ -2959,6 +2975,16 @@ bool policy_mgr_is_sta_sap_scc_allowed_on_dfs_chan( */ bool policy_mgr_is_sta_connected_2g(struct wlan_objmgr_psoc *psoc); +/** + * policy_mgr_is_connected_sta_5g() - check if sta connected in 5 GHz + * @psoc: pointer to soc + * @freq: Pointer to the frequency on which sta is connected + * + * Return: true if sta is connected in 5 GHz else false + */ +bool policy_mgr_is_connected_sta_5g(struct wlan_objmgr_psoc *psoc, + qdf_freq_t *freq); + /** * policy_mgr_scan_trim_5g_chnls_for_dfs_ap() - check if sta scan should skip * 5g channel when dfs ap is present. diff --git a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_action.c b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_action.c index bdc9a7bf374722bc20fef16d36b4877b2f78fbe0..f0d81f83a97fc26000e8cedc0078cb4a70162016 100644 --- a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_action.c +++ b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_action.c @@ -1,5 +1,7 @@ /* * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the diff --git a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c index a1ca9e79d6a92ff0a389961246ca92c1a425ae22..4fb7c1b01197967e6bbefa035fa9e5e7202a8f75 100644 --- a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c +++ b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -3150,6 +3150,43 @@ bool policy_mgr_is_multiple_active_sta_sessions(struct wlan_objmgr_psoc *psoc) psoc, PM_STA_MODE, NULL) > 1; } +bool policy_mgr_is_sta_present_on_dfs_channel(struct wlan_objmgr_psoc *psoc, + uint8_t *vdev_id, + qdf_freq_t *ch_freq, + enum hw_mode_bandwidth *ch_width) +{ + struct policy_mgr_conc_connection_info *conn_info; + bool status = false; + uint32_t conn_index = 0; + struct policy_mgr_psoc_priv_obj *pm_ctx; + + pm_ctx = policy_mgr_get_context(psoc); + if (!pm_ctx) { + policy_mgr_err("Invalid Context"); + return false; + } + qdf_mutex_acquire(&pm_ctx->qdf_conc_list_lock); + for (conn_index = 0; conn_index < MAX_NUMBER_OF_CONC_CONNECTIONS; + conn_index++) { + conn_info = &pm_conc_connection_list[conn_index]; + if (conn_info->in_use && + (conn_info->mode == PM_STA_MODE || + conn_info->mode == PM_P2P_CLIENT_MODE) && + (wlan_reg_is_dfs_for_freq(pm_ctx->pdev, conn_info->freq) || + (wlan_reg_is_5ghz_ch_freq(conn_info->freq) && + conn_info->bw == HW_MODE_160_MHZ))) { + *vdev_id = conn_info->vdev_id; + *ch_freq = pm_conc_connection_list[conn_index].freq; + *ch_width = conn_info->bw; + status = true; + break; + } + } + qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); + + return status; +} + /** * policy_mgr_is_sta_active_connection_exists() - Check if a STA * connection is active @@ -3861,6 +3898,35 @@ bool policy_mgr_is_sta_connected_2g(struct wlan_objmgr_psoc *psoc) return ret; } +bool +policy_mgr_is_connected_sta_5g(struct wlan_objmgr_psoc *psoc, qdf_freq_t *freq) +{ + struct policy_mgr_psoc_priv_obj *pm_ctx; + uint32_t conn_index; + bool ret = false; + + pm_ctx = policy_mgr_get_context(psoc); + if (!pm_ctx) { + policy_mgr_err("Invalid Context"); + return ret; + } + + qdf_mutex_acquire(&pm_ctx->qdf_conc_list_lock); + for (conn_index = 0; conn_index < MAX_NUMBER_OF_CONC_CONNECTIONS; + conn_index++) { + *freq = pm_conc_connection_list[conn_index].freq; + if (pm_conc_connection_list[conn_index].mode == PM_STA_MODE && + WLAN_REG_IS_5GHZ_CH_FREQ(*freq) && + pm_conc_connection_list[conn_index].in_use) { + ret = true; + break; + } + } + qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); + + return ret; +} + uint32_t policy_mgr_get_connection_info(struct wlan_objmgr_psoc *psoc, struct connection_info *info) { diff --git a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_pcl.c b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_pcl.c index 707a3a84a6f56dd7cb3ddaf8af95030c98fbf33d..b3f3e772cd392155c0df95266be33ed1b3d5721c 100644 --- a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_pcl.c +++ b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_pcl.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2255,6 +2256,11 @@ QDF_STATUS policy_mgr_modify_sap_pcl_based_on_mandatory_channel( uint32_t i, j, pcl_len = 0; bool found; struct policy_mgr_psoc_priv_obj *pm_ctx; + qdf_freq_t dfs_sta_freq = 0; + qdf_freq_t sta_5GHz_freq = 0; + enum hw_mode_bandwidth sta_ch_width; + uint8_t sta_vdev_id = 0, scc_on_dfs_channel = 0; + bool sta_sap_scc_on_5ghz_channel; pm_ctx = policy_mgr_get_context(psoc); if (!pm_ctx) { @@ -2273,7 +2279,16 @@ QDF_STATUS policy_mgr_modify_sap_pcl_based_on_mandatory_channel( for (i = 0; i < pm_ctx->sap_mandatory_channels_len; i++) policy_mgr_debug("fav chan:%d", - pm_ctx->sap_mandatory_channels[i]); + pm_ctx->sap_mandatory_channels[i]); + + policy_mgr_get_sta_sap_scc_on_dfs_chnl(psoc, &scc_on_dfs_channel); + if (scc_on_dfs_channel) + policy_mgr_is_sta_present_on_dfs_channel(psoc, + &sta_vdev_id, + &dfs_sta_freq, + &sta_ch_width); + sta_sap_scc_on_5ghz_channel = + policy_mgr_is_connected_sta_5g(psoc, &sta_5GHz_freq); for (i = 0; i < *pcl_len_org; i++) { found = false; @@ -2281,6 +2296,22 @@ QDF_STATUS policy_mgr_modify_sap_pcl_based_on_mandatory_channel( policy_mgr_debug("index is exceeding NUM_CHANNELS"); break; } + + if (scc_on_dfs_channel && policy_mgr_is_force_scc(psoc) && + pcl_list_org[i] == dfs_sta_freq) { + policy_mgr_debug("dfs chan:%d", pcl_list_org[i]); + found = true; + goto update_pcl; + } + + if (sta_sap_scc_on_5ghz_channel && + policy_mgr_is_force_scc(psoc) && + pcl_list_org[i] == sta_5GHz_freq) { + policy_mgr_debug("scc chan:%d", pcl_list_org[i]); + found = true; + goto update_pcl; + } + for (j = 0; j < pm_ctx->sap_mandatory_channels_len; j++) { if (pcl_list_org[i] == pm_ctx->sap_mandatory_channels[j]) { @@ -2288,6 +2319,8 @@ QDF_STATUS policy_mgr_modify_sap_pcl_based_on_mandatory_channel( break; } } + +update_pcl: if (found && (pcl_len < NUM_CHANNELS)) { pcl_list_org[pcl_len] = pcl_list_org[i]; weight_list_org[pcl_len++] = weight_list_org[i]; diff --git a/drivers/staging/qcacld-3.0/components/nan/core/src/nan_main.c b/drivers/staging/qcacld-3.0/components/nan/core/src/nan_main.c index 4e806a8a10a6da06a1ff1d2b4d63d5c51f4b4bac..e58de1fe1610fc3d642216fee36e7e8ca6d7b781 100644 --- a/drivers/staging/qcacld-3.0/components/nan/core/src/nan_main.c +++ b/drivers/staging/qcacld-3.0/components/nan/core/src/nan_main.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -543,11 +544,13 @@ static QDF_STATUS nan_handle_confirm( peer = wlan_objmgr_get_peer_by_mac(psoc, confirm->peer_ndi_mac_addr.bytes, WLAN_NAN_ID); - if (!peer) { + if (!peer && confirm->rsp_code == NAN_DATAPATH_RESPONSE_ACCEPT) { nan_debug("Drop NDP confirm as peer isn't available"); return QDF_STATUS_E_NULL_VALUE; } - wlan_objmgr_peer_release_ref(peer, WLAN_NAN_ID); + + if (peer) + wlan_objmgr_peer_release_ref(peer, WLAN_NAN_ID); psoc_nan_obj = nan_get_psoc_priv_obj(psoc); if (!psoc_nan_obj) { diff --git a/drivers/staging/qcacld-3.0/configs/qca6390_defconfig b/drivers/staging/qcacld-3.0/configs/qca6390_defconfig index e11bdab1f2336db90597b457d056f88eb26b21bd..b3493ed65b1009bb79a76419499f3b7b51cb65cd 100644 --- a/drivers/staging/qcacld-3.0/configs/qca6390_defconfig +++ b/drivers/staging/qcacld-3.0/configs/qca6390_defconfig @@ -771,9 +771,3 @@ CONFIG_SAP_DHCP_FW_IND := y #Enable FW Offload CONFIG_WLAN_FW_OFFLOAD := y -#Enable Desc Debug Check -CONFIG_RX_DESC_DEBUG_CHECK := y - -#Enable Power Debug -CONFIG_WLAN_POWER_DEBUG := y - diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c index b7ccd41741b4fd6e01f83abbd1ea33163a022de7..d8b029ea7988bf4ff1b7c3d361276473a480db6e 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c @@ -18883,7 +18883,8 @@ static int wlan_hdd_cfg80211_connect_start(struct hdd_adapter *adapter, const u8 *ssid, size_t ssid_len, const u8 *bssid, const u8 *bssid_hint, uint32_t oper_freq, - enum nl80211_chan_width ch_width) + enum nl80211_chan_width ch_width, + uint32_t ch_freq_hint) { int status = 0; QDF_STATUS qdf_status; @@ -19099,6 +19100,8 @@ static int wlan_hdd_cfg80211_connect_start(struct hdd_adapter *adapter, &roam_profile->ch_params); } + roam_profile->freq_hint = ch_freq_hint; + if (wlan_hdd_cfg80211_check_pmf_valid(roam_profile)) { status = -EINVAL; goto conn_failure; @@ -20668,7 +20671,8 @@ static int __wlan_hdd_cfg80211_join_ibss(struct wiphy *wiphy, params->ssid_len, bssid.bytes, NULL, conn_info_channel, - params->chandef.width); + params->chandef.width, + 0); if (0 > status) { hdd_err("connect failed"); @@ -21345,6 +21349,7 @@ static int __wlan_hdd_cfg80211_connect(struct wiphy *wiphy, struct hdd_context *hdd_ctx; uint8_t vdev_id_list[MAX_NUMBER_OF_CONC_CONNECTIONS], i; bool disable_nan = true; + uint32_t ch_freq_hint = 0; hdd_enter(); @@ -21469,11 +21474,15 @@ static int __wlan_hdd_cfg80211_connect(struct wiphy *wiphy, else ch_freq = 0; + if (req->channel_hint) + ch_freq_hint = req->channel_hint->center_freq; + wlan_hdd_check_ht20_ht40_ind(hdd_ctx, adapter, req); status = wlan_hdd_cfg80211_connect_start(adapter, req->ssid, req->ssid_len, req->bssid, - bssid_hint, ch_freq, 0); + bssid_hint, ch_freq, 0, + ch_freq_hint); if (status) { wlan_hdd_cfg80211_clear_privacy(adapter); hdd_err("connect failed"); diff --git a/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h b/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h index 97805cbfce99284af501736c7669bc6035558e9c..bb8377b824a34b48414c8dea888af5e2ffe8b816 100644 --- a/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h +++ b/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h @@ -32,9 +32,9 @@ #define QWLAN_VERSION_MAJOR 5 #define QWLAN_VERSION_MINOR 2 #define QWLAN_VERSION_PATCH 022 -#define QWLAN_VERSION_EXTRA "T" -#define QWLAN_VERSION_BUILD 11 +#define QWLAN_VERSION_EXTRA "A" +#define QWLAN_VERSION_BUILD 12 -#define QWLAN_VERSIONSTR "5.2.022.11T" +#define QWLAN_VERSIONSTR "5.2.022.12A" #endif /* QWLAN_VERSION_H */ diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.c index 25b5c858e588db6e41d583dfbb841b79abb554d9..f4ad67174fdd2bbdda221f8a3eec3319e2d3ffb0 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.c @@ -1934,22 +1934,16 @@ static void __lim_process_channel_switch_timeout(struct pe_session *pe_session) } /* - * If the channel-list that AP is asking us to switch is invalid - * then we cannot switch the channel. Just disassociate from AP. - * We will find a better AP !!! + * The channel switch request received from AP is carrying + * invalid channel. It's ok to ignore this channel switch + * request as it might be from spoof AP. If it's from genuine + * AP, it may lead to heart beat failure and result in + * disconnection. DUT can go ahead and reconnect to it/any + * other AP once it disconnects. */ - if ((pe_session->limMlmState == - eLIM_MLM_LINK_ESTABLISHED_STATE) && - (pe_session->limSmeState != eLIM_SME_WT_DISASSOC_STATE) && - (pe_session->limSmeState != eLIM_SME_WT_DEAUTH_STATE)) { - pe_err("Invalid channel! Disconnect"); - lim_tear_down_link_with_ap(mac, - mac->lim.lim_timers. - gLimChannelSwitchTimer.sessionId, - eSIR_MAC_UNSUPPORTED_CHANNEL_CSA, - eLIM_LINK_MONITORING_DISASSOC); - return; - } + pe_err("Invalid channel freq %u Ignore CSA request", + channel_freq); + return; } switch (pe_session->gLimChannelSwitch.state) { case eLIM_CHANNEL_SWITCH_PRIMARY_ONLY: diff --git a/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/parser_api.c b/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/parser_api.c index 07b75109a9d6c6dba91163aeeee40b7707dba74c..83ea867e194466ab1f407e4046b4adb149e5ee19 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/parser_api.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/parser_api.c @@ -5916,7 +5916,7 @@ QDF_STATUS populate_dot11f_rrm_ie(struct mac_context *mac, void populate_mdie(struct mac_context *mac, tDot11fIEMobilityDomain *pDot11f, - uint8_t mdie[SIR_MDIE_SIZE]) + uint8_t mdie[]) { pDot11f->present = 1; pDot11f->MDID = (uint16_t) ((mdie[1] << 8) | (mdie[0])); diff --git a/drivers/staging/qcacld-3.0/core/sap/src/sap_ch_select.c b/drivers/staging/qcacld-3.0/core/sap/src/sap_ch_select.c index 0bbf75bce2f88da4d0bc51089789839ab59ecf28..9a94a404c60b145cace4384d09bb10361fd344a1 100644 --- a/drivers/staging/qcacld-3.0/core/sap/src/sap_ch_select.c +++ b/drivers/staging/qcacld-3.0/core/sap/src/sap_ch_select.c @@ -464,7 +464,10 @@ static bool sap_chan_sel_init(mac_handle_t mac_handle, } if (!include_dfs_ch || - sta_sap_scc_on_dfs_chnl_config_value == 1) { + (sta_sap_scc_on_dfs_chnl_config_value == + PM_STA_SAP_ON_DFS_MASTER_MODE_DISABLED && + !policy_mgr_is_sta_sap_scc(mac->psoc, + pSpectCh->chan_freq))) { if (wlan_reg_is_dfs_for_freq(mac->pdev, pSpectCh->chan_freq)) { QDF_TRACE(QDF_MODULE_ID_SAP, diff --git a/drivers/staging/qcacld-3.0/core/sme/inc/csr_api.h b/drivers/staging/qcacld-3.0/core/sme/inc/csr_api.h index ecafada0dcd653a3ac9cab110c6b401055c4de86..a19e54e845a26ab357151edafec9c7931020dc12 100644 --- a/drivers/staging/qcacld-3.0/core/sme/inc/csr_api.h +++ b/drivers/staging/qcacld-3.0/core/sme/inc/csr_api.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -713,6 +714,7 @@ struct csr_roam_profile { tCsrKeys Keys; tCsrChannelInfo ChannelInfo; uint32_t op_freq; + uint32_t freq_hint; struct ch_params ch_params; /* If this is 0, SME will fill in for caller. */ uint16_t beaconInterval; diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c index ea344f1bac433f1aae9e61f772751680f9fcbb2c..6155600df38359c0f81b6d5edcbe15df38c972f9 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1427,6 +1428,15 @@ QDF_STATUS csr_scan_for_ssid(struct mac_context *mac_ctx, uint32_t session_id, req->scan_req.chan_list.num_chan = num_chan; } + /* Add freq hint for scan for ssid */ + if (!num_chan && profile->freq_hint && + csr_roam_is_valid_channel(mac_ctx, profile->freq_hint)) { + sme_debug("add freq hint %d", profile->freq_hint); + req->scan_req.chan_list.chan[0].freq = + profile->freq_hint; + req->scan_req.chan_list.num_chan = 1; + } + /* Extend it for multiple SSID */ if (profile->SSIDs.numOfSSIDs) { if (profile->SSIDs.SSIDList[0].SSID.length > WLAN_SSID_MAX_LEN) { diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c index 32b57d9c4e506d91156635bdb8d81e0e600cecd8..3ca5ec0350d9714a44fe309662ec1dafe2b94c15 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c @@ -4965,7 +4965,7 @@ int wma_extscan_hotlist_match_event_handler(void *handle, return -ENOMEM; dest_ap = &dest_hotlist->ap[0]; - dest_hotlist->numOfAps = event->total_entries; + dest_hotlist->numOfAps = numap; dest_hotlist->requestId = event->config_request_id; if (event->first_entry_index + @@ -5132,6 +5132,7 @@ static int wma_group_num_bss_to_scan_id(const u_int8_t *cmd_param_info, struct extscan_cached_scan_results *t_cached_result; struct extscan_cached_scan_result *t_scan_id_grp; int i, j; + uint32_t total_scan_num_results = 0; tSirWifiScanResult *ap; param_buf = (WMI_EXTSCAN_CACHED_RESULTS_EVENTID_param_tlvs *) @@ -5142,17 +5143,19 @@ static int wma_group_num_bss_to_scan_id(const u_int8_t *cmd_param_info, t_cached_result = cached_result; t_scan_id_grp = &t_cached_result->result[0]; - if ((t_cached_result->num_scan_ids * - QDF_MIN(t_scan_id_grp->num_results, - param_buf->num_bssid_list)) > param_buf->num_bssid_list) { - WMA_LOGE("%s:num_scan_ids %d, num_results %d num_bssid_list %d", - __func__, - t_cached_result->num_scan_ids, - t_scan_id_grp->num_results, - param_buf->num_bssid_list); + for (i = 0; i < t_cached_result->num_scan_ids; i++) { + total_scan_num_results += t_scan_id_grp->num_results; + t_scan_id_grp++; + } + + if (total_scan_num_results > param_buf->num_bssid_list) { + wma_err("total_scan_num_results %d, num_bssid_list %d", + total_scan_num_results, + param_buf->num_bssid_list); return -EINVAL; } + t_scan_id_grp = &t_cached_result->result[0]; WMA_LOGD("%s: num_scan_ids:%d", __func__, t_cached_result->num_scan_ids); for (i = 0; i < t_cached_result->num_scan_ids; i++) { @@ -5164,8 +5167,7 @@ static int wma_group_num_bss_to_scan_id(const u_int8_t *cmd_param_info, return -ENOMEM; ap = &t_scan_id_grp->ap[0]; - for (j = 0; j < QDF_MIN(t_scan_id_grp->num_results, - param_buf->num_bssid_list); j++) { + for (j = 0; j < t_scan_id_grp->num_results; j++) { ap->channel = src_hotlist->channel; ap->ts = WMA_MSEC_TO_USEC(src_rssi->tstamp); ap->rtt = src_hotlist->rtt; diff --git a/drivers/staging/qcacld-3.0/os_if/sync/src/osif_vdev_sync.c b/drivers/staging/qcacld-3.0/os_if/sync/src/osif_vdev_sync.c index fc6293b17aeef5e4b9c377b325cee42f5276a948..6f795221694f5c92c82cdb62aaf1a9d0adc33e07 100644 --- a/drivers/staging/qcacld-3.0/os_if/sync/src/osif_vdev_sync.c +++ b/drivers/staging/qcacld-3.0/os_if/sync/src/osif_vdev_sync.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -262,6 +263,9 @@ int __osif_vdev_sync_trans_start(struct net_device *net_dev, dsc_vdev_trans_start); osif_vdev_sync_unlock(); + if (!errno) + osif_vdev_sync_wait_for_ops(*out_vdev_sync); + return errno; } @@ -276,6 +280,9 @@ int __osif_vdev_sync_trans_start_wait(struct net_device *net_dev, out_vdev_sync, desc, dsc_vdev_trans_start_wait); + if (!errno) + osif_vdev_sync_wait_for_ops(*out_vdev_sync); + return errno; } diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c index da73998bc5f703fa758c194d96341fced307a956..d5ef1986bde4d36a292fd7afbb7001661e0c7fc2 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c @@ -778,6 +778,7 @@ static int _rtl92e_sta_up(struct net_device *dev, bool is_silent_reset) else netif_wake_queue(dev); + priv->bfirst_after_down = false; return 0; } diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c index 9bf95bd0ad13f9f91f590e1943a6ff099fe0da54..ca2113823387afd5fa92566e835d8b4c4d950ff7 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c @@ -193,7 +193,6 @@ static void _rtl92e_dm_init_fsync(struct net_device *dev); static void _rtl92e_dm_deinit_fsync(struct net_device *dev); static void _rtl92e_dm_check_txrateandretrycount(struct net_device *dev); -static void _rtl92e_dm_check_ac_dc_power(struct net_device *dev); static void _rtl92e_dm_check_fsync(struct net_device *dev); static void _rtl92e_dm_check_rf_ctrl_gpio(void *data); static void _rtl92e_dm_fsync_timer_callback(struct timer_list *t); @@ -246,8 +245,6 @@ void rtl92e_dm_watchdog(struct net_device *dev) if (priv->being_init_adapter) return; - _rtl92e_dm_check_ac_dc_power(dev); - _rtl92e_dm_check_txrateandretrycount(dev); _rtl92e_dm_check_edca_turbo(dev); @@ -265,30 +262,6 @@ void rtl92e_dm_watchdog(struct net_device *dev) _rtl92e_dm_cts_to_self(dev); } -static void _rtl92e_dm_check_ac_dc_power(struct net_device *dev) -{ - struct r8192_priv *priv = rtllib_priv(dev); - static char const ac_dc_script[] = "/etc/acpi/wireless-rtl-ac-dc-power.sh"; - char *argv[] = {(char *)ac_dc_script, DRV_NAME, NULL}; - static char *envp[] = {"HOME=/", - "TERM=linux", - "PATH=/usr/bin:/bin", - NULL}; - - if (priv->ResetProgress == RESET_TYPE_SILENT) { - RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF), - "GPIOChangeRFWorkItemCallBack(): Silent Reset!!!!!!!\n"); - return; - } - - if (priv->rtllib->state != RTLLIB_LINKED) - return; - call_usermodehelper(ac_dc_script, argv, envp, UMH_WAIT_PROC); - - return; -}; - - void rtl92e_init_adaptive_rate(struct net_device *dev) { @@ -1809,10 +1782,6 @@ static void _rtl92e_dm_check_rf_ctrl_gpio(void *data) u8 tmp1byte; enum rt_rf_power_state eRfPowerStateToSet; bool bActuallySet = false; - char *argv[3]; - static char const RadioPowerPath[] = "/etc/acpi/events/RadioPower.sh"; - static char *envp[] = {"HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", - NULL}; bActuallySet = false; @@ -1844,14 +1813,6 @@ static void _rtl92e_dm_check_rf_ctrl_gpio(void *data) mdelay(1000); priv->bHwRfOffAction = 1; rtl92e_set_rf_state(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW); - if (priv->bHwRadioOff) - argv[1] = "RFOFF"; - else - argv[1] = "RFON"; - - argv[0] = (char *)RadioPowerPath; - argv[2] = NULL; - call_usermodehelper(RadioPowerPath, argv, envp, UMH_WAIT_PROC); } } diff --git a/drivers/target/iscsi/iscsi_target.c b/drivers/target/iscsi/iscsi_target.c index 58ccded1be857e5401eaab1926e0802de918f0b3..7738e249c4a2418a35d9c1d987faaf479c6decf2 100644 --- a/drivers/target/iscsi/iscsi_target.c +++ b/drivers/target/iscsi/iscsi_target.c @@ -4056,9 +4056,12 @@ static void iscsit_release_commands_from_conn(struct iscsi_conn *conn) list_for_each_entry_safe(cmd, cmd_tmp, &tmp_list, i_conn_node) { struct se_cmd *se_cmd = &cmd->se_cmd; - if (se_cmd->se_tfo != NULL) { - spin_lock_irq(&se_cmd->t_state_lock); - if (se_cmd->transport_state & CMD_T_ABORTED) { + if (!se_cmd->se_tfo) + continue; + + spin_lock_irq(&se_cmd->t_state_lock); + if (se_cmd->transport_state & CMD_T_ABORTED) { + if (!(se_cmd->transport_state & CMD_T_TAS)) /* * LIO's abort path owns the cleanup for this, * so put it back on the list and let @@ -4066,11 +4069,10 @@ static void iscsit_release_commands_from_conn(struct iscsi_conn *conn) */ list_move_tail(&cmd->i_conn_node, &conn->conn_cmd_list); - } else { - se_cmd->transport_state |= CMD_T_FABRIC_STOP; - } - spin_unlock_irq(&se_cmd->t_state_lock); + } else { + se_cmd->transport_state |= CMD_T_FABRIC_STOP; } + spin_unlock_irq(&se_cmd->t_state_lock); } spin_unlock_bh(&conn->cmd_lock); diff --git a/drivers/target/iscsi/iscsi_target_configfs.c b/drivers/target/iscsi/iscsi_target_configfs.c index d25cadc4f4f11f7f476b127c8086c53064d4adcb..ac071abae7e90ee9458b92d64d481bfc37665f77 100644 --- a/drivers/target/iscsi/iscsi_target_configfs.c +++ b/drivers/target/iscsi/iscsi_target_configfs.c @@ -516,102 +516,102 @@ static ssize_t lio_target_nacl_info_show(struct config_item *item, char *page) spin_lock_bh(&se_nacl->nacl_sess_lock); se_sess = se_nacl->nacl_sess; if (!se_sess) { - rb += sprintf(page+rb, "No active iSCSI Session for Initiator" + rb += sysfs_emit_at(page, rb, "No active iSCSI Session for Initiator" " Endpoint: %s\n", se_nacl->initiatorname); } else { sess = se_sess->fabric_sess_ptr; - rb += sprintf(page+rb, "InitiatorName: %s\n", + rb += sysfs_emit_at(page, rb, "InitiatorName: %s\n", sess->sess_ops->InitiatorName); - rb += sprintf(page+rb, "InitiatorAlias: %s\n", + rb += sysfs_emit_at(page, rb, "InitiatorAlias: %s\n", sess->sess_ops->InitiatorAlias); - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "LIO Session ID: %u ISID: 0x%6ph TSIH: %hu ", sess->sid, sess->isid, sess->tsih); - rb += sprintf(page+rb, "SessionType: %s\n", + rb += sysfs_emit_at(page, rb, "SessionType: %s\n", (sess->sess_ops->SessionType) ? "Discovery" : "Normal"); - rb += sprintf(page+rb, "Session State: "); + rb += sysfs_emit_at(page, rb, "Session State: "); switch (sess->session_state) { case TARG_SESS_STATE_FREE: - rb += sprintf(page+rb, "TARG_SESS_FREE\n"); + rb += sysfs_emit_at(page, rb, "TARG_SESS_FREE\n"); break; case TARG_SESS_STATE_ACTIVE: - rb += sprintf(page+rb, "TARG_SESS_STATE_ACTIVE\n"); + rb += sysfs_emit_at(page, rb, "TARG_SESS_STATE_ACTIVE\n"); break; case TARG_SESS_STATE_LOGGED_IN: - rb += sprintf(page+rb, "TARG_SESS_STATE_LOGGED_IN\n"); + rb += sysfs_emit_at(page, rb, "TARG_SESS_STATE_LOGGED_IN\n"); break; case TARG_SESS_STATE_FAILED: - rb += sprintf(page+rb, "TARG_SESS_STATE_FAILED\n"); + rb += sysfs_emit_at(page, rb, "TARG_SESS_STATE_FAILED\n"); break; case TARG_SESS_STATE_IN_CONTINUE: - rb += sprintf(page+rb, "TARG_SESS_STATE_IN_CONTINUE\n"); + rb += sysfs_emit_at(page, rb, "TARG_SESS_STATE_IN_CONTINUE\n"); break; default: - rb += sprintf(page+rb, "ERROR: Unknown Session" + rb += sysfs_emit_at(page, rb, "ERROR: Unknown Session" " State!\n"); break; } - rb += sprintf(page+rb, "---------------------[iSCSI Session" + rb += sysfs_emit_at(page, rb, "---------------------[iSCSI Session" " Values]-----------------------\n"); - rb += sprintf(page+rb, " CmdSN/WR : CmdSN/WC : ExpCmdSN" + rb += sysfs_emit_at(page, rb, " CmdSN/WR : CmdSN/WC : ExpCmdSN" " : MaxCmdSN : ITT : TTT\n"); max_cmd_sn = (u32) atomic_read(&sess->max_cmd_sn); - rb += sprintf(page+rb, " 0x%08x 0x%08x 0x%08x 0x%08x" + rb += sysfs_emit_at(page, rb, " 0x%08x 0x%08x 0x%08x 0x%08x" " 0x%08x 0x%08x\n", sess->cmdsn_window, (max_cmd_sn - sess->exp_cmd_sn) + 1, sess->exp_cmd_sn, max_cmd_sn, sess->init_task_tag, sess->targ_xfer_tag); - rb += sprintf(page+rb, "----------------------[iSCSI" + rb += sysfs_emit_at(page, rb, "----------------------[iSCSI" " Connections]-------------------------\n"); spin_lock(&sess->conn_lock); list_for_each_entry(conn, &sess->sess_conn_list, conn_list) { - rb += sprintf(page+rb, "CID: %hu Connection" + rb += sysfs_emit_at(page, rb, "CID: %hu Connection" " State: ", conn->cid); switch (conn->conn_state) { case TARG_CONN_STATE_FREE: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_FREE\n"); break; case TARG_CONN_STATE_XPT_UP: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_XPT_UP\n"); break; case TARG_CONN_STATE_IN_LOGIN: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_IN_LOGIN\n"); break; case TARG_CONN_STATE_LOGGED_IN: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_LOGGED_IN\n"); break; case TARG_CONN_STATE_IN_LOGOUT: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_IN_LOGOUT\n"); break; case TARG_CONN_STATE_LOGOUT_REQUESTED: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_LOGOUT_REQUESTED\n"); break; case TARG_CONN_STATE_CLEANUP_WAIT: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_CLEANUP_WAIT\n"); break; default: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "ERROR: Unknown Connection State!\n"); break; } - rb += sprintf(page+rb, " Address %pISc %s", &conn->login_sockaddr, + rb += sysfs_emit_at(page, rb, " Address %pISc %s", &conn->login_sockaddr, (conn->network_transport == ISCSI_TCP) ? "TCP" : "SCTP"); - rb += sprintf(page+rb, " StatSN: 0x%08x\n", + rb += sysfs_emit_at(page, rb, " StatSN: 0x%08x\n", conn->stat_sn); } spin_unlock(&sess->conn_lock); diff --git a/drivers/target/iscsi/iscsi_target_nego.c b/drivers/target/iscsi/iscsi_target_nego.c index 5db8842a8026534942876bf372dc757d668d149e..e39177f9fdb0a2f634236199ce4ca3fadaf6530b 100644 --- a/drivers/target/iscsi/iscsi_target_nego.c +++ b/drivers/target/iscsi/iscsi_target_nego.c @@ -1072,6 +1072,7 @@ int iscsi_target_locate_portal( iscsi_target_set_sock_callbacks(conn); login->np = np; + conn->tpg = NULL; login_req = (struct iscsi_login_req *) login->req; payload_length = ntoh24(login_req->dlength); @@ -1141,7 +1142,6 @@ int iscsi_target_locate_portal( */ sessiontype = strncmp(s_buf, DISCOVERY, 9); if (!sessiontype) { - conn->tpg = iscsit_global->discovery_tpg; if (!login->leading_connection) goto get_target; @@ -1158,9 +1158,11 @@ int iscsi_target_locate_portal( * Serialize access across the discovery struct iscsi_portal_group to * process login attempt. */ + conn->tpg = iscsit_global->discovery_tpg; if (iscsit_access_np(np, conn->tpg) < 0) { iscsit_tx_login_rsp(conn, ISCSI_STATUS_CLS_TARGET_ERR, ISCSI_LOGIN_STATUS_SVC_UNAVAILABLE); + conn->tpg = NULL; ret = -1; goto out; } diff --git a/drivers/target/iscsi/iscsi_target_parameters.c b/drivers/target/iscsi/iscsi_target_parameters.c index 29a37b242d30a3f225f52ea9f34a00e412f02d95..01f93de93c8c7f8742ecb79cfb42aa007d6a02a5 100644 --- a/drivers/target/iscsi/iscsi_target_parameters.c +++ b/drivers/target/iscsi/iscsi_target_parameters.c @@ -1270,18 +1270,20 @@ static struct iscsi_param *iscsi_check_key( return param; if (!(param->phase & phase)) { - pr_err("Key \"%s\" may not be negotiated during ", - param->name); + char *phase_name; + switch (phase) { case PHASE_SECURITY: - pr_debug("Security phase.\n"); + phase_name = "Security"; break; case PHASE_OPERATIONAL: - pr_debug("Operational phase.\n"); + phase_name = "Operational"; break; default: - pr_debug("Unknown phase.\n"); + phase_name = "Unknown"; } + pr_err("Key \"%s\" may not be negotiated during %s phase.\n", + param->name, phase_name); return NULL; } diff --git a/drivers/target/target_core_device.c b/drivers/target/target_core_device.c index 1b381519c16492cec667512e8bb73a4cf5244dfe..a23dcbe79e14ad8612949dcc09c5e9a45ac5b302 100644 --- a/drivers/target/target_core_device.c +++ b/drivers/target/target_core_device.c @@ -881,7 +881,6 @@ sector_t target_to_linux_sector(struct se_device *dev, sector_t lb) EXPORT_SYMBOL(target_to_linux_sector); struct devices_idr_iter { - struct config_item *prev_item; int (*fn)(struct se_device *dev, void *data); void *data; }; @@ -891,11 +890,9 @@ static int target_devices_idr_iter(int id, void *p, void *data) { struct devices_idr_iter *iter = data; struct se_device *dev = p; + struct config_item *item; int ret; - config_item_put(iter->prev_item); - iter->prev_item = NULL; - /* * We add the device early to the idr, so it can be used * by backend modules during configuration. We do not want @@ -905,12 +902,13 @@ static int target_devices_idr_iter(int id, void *p, void *data) if (!target_dev_configured(dev)) return 0; - iter->prev_item = config_item_get_unless_zero(&dev->dev_group.cg_item); - if (!iter->prev_item) + item = config_item_get_unless_zero(&dev->dev_group.cg_item); + if (!item) return 0; mutex_unlock(&device_mutex); ret = iter->fn(dev, iter->data); + config_item_put(item); mutex_lock(&device_mutex); return ret; @@ -933,7 +931,6 @@ int target_for_each_device(int (*fn)(struct se_device *dev, void *data), mutex_lock(&device_mutex); ret = idr_for_each(&devices_idr, target_devices_idr_iter, &iter); mutex_unlock(&device_mutex); - config_item_put(iter.prev_item); return ret; } diff --git a/drivers/thermal/intel_powerclamp.c b/drivers/thermal/intel_powerclamp.c index dffefcde0628fc04f48f29383cd27dcfd8a7b8c0..351fa43c1ee3cc4d00399ab99a06c08f675113f4 100644 --- a/drivers/thermal/intel_powerclamp.c +++ b/drivers/thermal/intel_powerclamp.c @@ -72,6 +72,7 @@ static unsigned int target_mwait; static struct dentry *debug_dir; +static bool poll_pkg_cstate_enable; /* user selected target */ static unsigned int set_target_ratio; @@ -280,6 +281,9 @@ static unsigned int get_compensation(int ratio) { unsigned int comp = 0; + if (!poll_pkg_cstate_enable) + return 0; + /* we only use compensation if all adjacent ones are good */ if (ratio == 1 && cal_data[ratio].confidence >= CONFIDENCE_OK && @@ -552,7 +556,8 @@ static int start_power_clamp(void) control_cpu = cpumask_first(cpu_online_mask); clamping = true; - schedule_delayed_work(&poll_pkg_cstate_work, 0); + if (poll_pkg_cstate_enable) + schedule_delayed_work(&poll_pkg_cstate_work, 0); /* start one kthread worker per online cpu */ for_each_online_cpu(cpu) { @@ -621,11 +626,15 @@ static int powerclamp_get_max_state(struct thermal_cooling_device *cdev, static int powerclamp_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state) { - if (true == clamping) - *state = pkg_cstate_ratio_cur; - else + if (clamping) { + if (poll_pkg_cstate_enable) + *state = pkg_cstate_ratio_cur; + else + *state = set_target_ratio; + } else { /* to save power, do not poll idle ratio while not clamping */ *state = -1; /* indicates invalid state */ + } return 0; } @@ -770,6 +779,9 @@ static int __init powerclamp_init(void) goto exit_unregister; } + if (topology_max_packages() == 1) + poll_pkg_cstate_enable = true; + cooling_dev = thermal_cooling_device_register("intel_powerclamp", NULL, &powerclamp_cooling_ops); if (IS_ERR(cooling_dev)) { diff --git a/drivers/thermal/intel_quark_dts_thermal.c b/drivers/thermal/intel_quark_dts_thermal.c index 5d33b350da1c68d937d2b7d97a4ea8650ea0c4a4..ad92d8f0add1972bd185506775e8c354cdb65b18 100644 --- a/drivers/thermal/intel_quark_dts_thermal.c +++ b/drivers/thermal/intel_quark_dts_thermal.c @@ -440,22 +440,14 @@ MODULE_DEVICE_TABLE(x86cpu, qrk_thermal_ids); static int __init intel_quark_thermal_init(void) { - int err = 0; - if (!x86_match_cpu(qrk_thermal_ids) || !iosf_mbi_available()) return -ENODEV; soc_dts = alloc_soc_dts(); - if (IS_ERR(soc_dts)) { - err = PTR_ERR(soc_dts); - goto err_free; - } + if (IS_ERR(soc_dts)) + return PTR_ERR(soc_dts); return 0; - -err_free: - free_soc_dts(soc_dts); - return err; } static void __exit intel_quark_thermal_exit(void) diff --git a/drivers/thermal/intel_soc_dts_iosf.c b/drivers/thermal/intel_soc_dts_iosf.c index e0813dfaa2783c17ea43012df3cedf2f70b11f3f..435a093998000739505a2e77a7c954e86615caa0 100644 --- a/drivers/thermal/intel_soc_dts_iosf.c +++ b/drivers/thermal/intel_soc_dts_iosf.c @@ -405,7 +405,7 @@ struct intel_soc_dts_sensors *intel_soc_dts_iosf_init( { struct intel_soc_dts_sensors *sensors; bool notification; - u32 tj_max; + int tj_max; int ret; int i; diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c index bf2d358c79c6c6a97f73a6590ba038137345a87b..aab2dca801c780cac1981b0b698ec3617ecf2a34 100644 --- a/drivers/thermal/thermal_core.c +++ b/drivers/thermal/thermal_core.c @@ -793,7 +793,8 @@ int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz, if (result) goto release_ida; - sprintf(dev->attr_name, "cdev%d_trip_point", dev->id); + snprintf(dev->attr_name, sizeof(dev->attr_name), "cdev%d_trip_point", + dev->id); sysfs_attr_init(&dev->attr.attr); dev->attr.attr.name = dev->attr_name; dev->attr.attr.mode = 0644; @@ -825,7 +826,8 @@ int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz, if (result) goto remove_upper_file; - sprintf(dev->weight_attr_name, "cdev%d_weight", dev->id); + snprintf(dev->weight_attr_name, sizeof(dev->weight_attr_name), + "cdev%d_weight", dev->id); sysfs_attr_init(&dev->weight_attr.attr); dev->weight_attr.attr.name = dev->weight_attr_name; dev->weight_attr.attr.mode = S_IWUSR | S_IRUGO; diff --git a/drivers/thermal/tsens-mtc.c b/drivers/thermal/tsens-mtc.c index 590f702d870dac949d6bed0594954a2f6bcedf1c..9381a7c7ef6f21bd6b776f0355f8ffbf7bb98cad 100644 --- a/drivers/thermal/tsens-mtc.c +++ b/drivers/thermal/tsens-mtc.c @@ -22,7 +22,7 @@ struct tsens_device *tsens_controller_is_present(void) } EXPORT_SYMBOL(tsens_controller_is_present); -static int tsens_mtc_reset_history_counter(unsigned int zone) +int tsens_mtc_reset_history_counter(unsigned int zone) { unsigned int reg_cntl, is_valid; void __iomem *sensor_addr; diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index 384623c49cfeed62349310f68cf33de318b0d1ca..d22c7216d68ca274531c774ebfe7407e5b66bfb3 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -38,7 +38,7 @@ #define NHI_MAILBOX_TIMEOUT 500 /* ms */ -static int ring_interrupt_index(struct tb_ring *ring) +static int ring_interrupt_index(const struct tb_ring *ring) { int bit = ring->hop; if (!ring->is_tx) diff --git a/drivers/tty/cyclades.c b/drivers/tty/cyclades.c index db048dbe9f785fc81c5cfbc92bfab5ff063749e9..6fec20c01ef15a6fcc0a4c7e10ad65fa53d61cca 100644 --- a/drivers/tty/cyclades.c +++ b/drivers/tty/cyclades.c @@ -3648,7 +3648,7 @@ static int cy_pci_probe(struct pci_dev *pdev, struct cyclades_card *card; void __iomem *addr0 = NULL, *addr2 = NULL; char *card_name = NULL; - u32 uninitialized_var(mailbox); + u32 mailbox; unsigned int device_id, nchan = 0, card_no, i, j; unsigned char plx_ver; int retval, irq; diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c index 47ffb485ff34ca3ac1b11b12babd59fb230aa9b0..c89f93ff07c57fe3b6a47286b3a2a34330870ec2 100644 --- a/drivers/tty/hvc/hvc_xen.c +++ b/drivers/tty/hvc/hvc_xen.c @@ -43,6 +43,7 @@ struct xencons_info { int irq; int vtermno; grant_ref_t gntref; + spinlock_t ring_lock; }; static LIST_HEAD(xenconsoles); @@ -89,12 +90,15 @@ static int __write_console(struct xencons_info *xencons, XENCONS_RING_IDX cons, prod; struct xencons_interface *intf = xencons->intf; int sent = 0; + unsigned long flags; + spin_lock_irqsave(&xencons->ring_lock, flags); cons = intf->out_cons; prod = intf->out_prod; mb(); /* update queue values before going on */ if ((prod - cons) > sizeof(intf->out)) { + spin_unlock_irqrestore(&xencons->ring_lock, flags); pr_err_once("xencons: Illegal ring page indices"); return -EINVAL; } @@ -104,6 +108,7 @@ static int __write_console(struct xencons_info *xencons, wmb(); /* write ring before updating pointer */ intf->out_prod = prod; + spin_unlock_irqrestore(&xencons->ring_lock, flags); if (sent) notify_daemon(xencons); @@ -146,16 +151,19 @@ static int domU_read_console(uint32_t vtermno, char *buf, int len) int recv = 0; struct xencons_info *xencons = vtermno_to_xencons(vtermno); unsigned int eoiflag = 0; + unsigned long flags; if (xencons == NULL) return -EINVAL; intf = xencons->intf; + spin_lock_irqsave(&xencons->ring_lock, flags); cons = intf->in_cons; prod = intf->in_prod; mb(); /* get pointers before reading ring */ if ((prod - cons) > sizeof(intf->in)) { + spin_unlock_irqrestore(&xencons->ring_lock, flags); pr_err_once("xencons: Illegal ring page indices"); return -EINVAL; } @@ -179,10 +187,13 @@ static int domU_read_console(uint32_t vtermno, char *buf, int len) xencons->out_cons = intf->out_cons; xencons->out_cons_same = 0; } + if (!recv && xencons->out_cons_same++ > 1) { + eoiflag = XEN_EOI_FLAG_SPURIOUS; + } + spin_unlock_irqrestore(&xencons->ring_lock, flags); + if (recv) { notify_daemon(xencons); - } else if (xencons->out_cons_same++ > 1) { - eoiflag = XEN_EOI_FLAG_SPURIOUS; } xen_irq_lateeoi(xencons->irq, eoiflag); @@ -239,6 +250,7 @@ static int xen_hvm_console_init(void) info = kzalloc(sizeof(struct xencons_info), GFP_KERNEL); if (!info) return -ENOMEM; + spin_lock_init(&info->ring_lock); } else if (info->intf != NULL) { /* already configured */ return 0; @@ -275,6 +287,7 @@ static int xen_hvm_console_init(void) static int xencons_info_pv_init(struct xencons_info *info, int vtermno) { + spin_lock_init(&info->ring_lock); info->evtchn = xen_start_info->console.domU.evtchn; /* GFN == MFN for PV guest */ info->intf = gfn_to_virt(xen_start_info->console.domU.mfn); @@ -325,6 +338,7 @@ static int xen_initial_domain_console_init(void) info = kzalloc(sizeof(struct xencons_info), GFP_KERNEL); if (!info) return -ENOMEM; + spin_lock_init(&info->ring_lock); } info->irq = bind_virq_to_irq(VIRQ_CONSOLE, 0, false); @@ -482,6 +496,7 @@ static int xencons_probe(struct xenbus_device *dev, info = kzalloc(sizeof(struct xencons_info), GFP_KERNEL); if (!info) return -ENOMEM; + spin_lock_init(&info->ring_lock); dev_set_drvdata(&dev->dev, info); info->xbdev = dev; info->vtermno = xenbus_devid_to_vtermno(devid); @@ -572,7 +587,7 @@ static int __init xen_hvc_init(void) ops = &dom0_hvc_ops; r = xen_initial_domain_console_init(); if (r < 0) - return r; + goto register_fe; info = vtermno_to_xencons(HVC_COOKIE); } else { ops = &domU_hvc_ops; @@ -581,7 +596,7 @@ static int __init xen_hvc_init(void) else r = xen_pv_console_init(); if (r < 0) - return r; + goto register_fe; info = vtermno_to_xencons(HVC_COOKIE); info->irq = bind_evtchn_to_irq_lateeoi(info->evtchn); @@ -606,6 +621,7 @@ static int __init xen_hvc_init(void) } r = 0; + register_fe: #ifdef CONFIG_HVC_XEN_FRONTEND r = xenbus_register_frontend(&xencons_driver); #endif diff --git a/drivers/tty/isicom.c b/drivers/tty/isicom.c index 8d96e86966f1b5ddf2bb43067a4899ee1d4653f4..274480a3c4b97f51a7d8ca8c5cbf02425165cc6b 100644 --- a/drivers/tty/isicom.c +++ b/drivers/tty/isicom.c @@ -1537,7 +1537,7 @@ static unsigned int card_count; static int isicom_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { - unsigned int uninitialized_var(signature), index; + unsigned int signature, index; int retval = -EPERM; struct isi_board *board = NULL; diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h index ebfb0bd5bef59d679c36cd0a2562145a11509f1a..b0c5f0dba6fcca771f0d6474feae2b815fc6ee93 100644 --- a/drivers/tty/serial/8250/8250.h +++ b/drivers/tty/serial/8250/8250.h @@ -85,7 +85,6 @@ struct serial8250_config { #define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */ #define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */ #define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */ -#define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */ #ifdef CONFIG_SERIAL_8250_SHARE_IRQ @@ -217,6 +216,13 @@ extern int serial8250_rx_dma(struct uart_8250_port *); extern void serial8250_rx_dma_flush(struct uart_8250_port *); extern int serial8250_request_dma(struct uart_8250_port *); extern void serial8250_release_dma(struct uart_8250_port *); + +static inline bool serial8250_tx_dma_running(struct uart_8250_port *p) +{ + struct uart_8250_dma *dma = p->dma; + + return dma && dma->tx_running; +} #else static inline int serial8250_tx_dma(struct uart_8250_port *p) { @@ -232,6 +238,11 @@ static inline int serial8250_request_dma(struct uart_8250_port *p) return -1; } static inline void serial8250_release_dma(struct uart_8250_port *p) { } + +static inline bool serial8250_tx_dma_running(struct uart_8250_port *p) +{ + return false; +} #endif static inline int ns16550a_goto_highspeed(struct uart_8250_port *up) diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c index d2df7d71d6667e74b4ec01fcdfe874e432fcffe9..a0325af2832a0977891e6edce5ae9ba9db562c74 100644 --- a/drivers/tty/serial/8250/8250_core.c +++ b/drivers/tty/serial/8250/8250_core.c @@ -1125,6 +1125,7 @@ void serial8250_unregister_port(int line) uart->port.type = PORT_UNKNOWN; uart->port.dev = &serial8250_isa_devs->dev; uart->capabilities = 0; + serial8250_init_port(uart); serial8250_apply_quirks(uart); uart_add_one_port(&serial8250_reg, &uart->port); } else { diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c new file mode 100644 index 0000000000000000000000000000000000000000..1cf229cca59281923fd78199889ec5369dc46e9f --- /dev/null +++ b/drivers/tty/serial/8250/8250_dwlib.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Synopsys DesignWare 8250 library. */ + +#include +#include +#include +#include +#include +#include + +#include "8250_dwlib.h" + +/* Offsets for the DesignWare specific registers */ +#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ +#define DW_UART_CPR 0xf4 /* Component Parameter Register */ +#define DW_UART_UCV 0xf8 /* UART Component Version */ + +/* Component Parameter Register bits */ +#define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) +#define DW_UART_CPR_AFCE_MODE (1 << 4) +#define DW_UART_CPR_THRE_MODE (1 << 5) +#define DW_UART_CPR_SIR_MODE (1 << 6) +#define DW_UART_CPR_SIR_LP_MODE (1 << 7) +#define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) +#define DW_UART_CPR_FIFO_ACCESS (1 << 9) +#define DW_UART_CPR_FIFO_STAT (1 << 10) +#define DW_UART_CPR_SHADOW (1 << 11) +#define DW_UART_CPR_ENCODED_PARMS (1 << 12) +#define DW_UART_CPR_DMA_EXTRA (1 << 13) +#define DW_UART_CPR_FIFO_MODE (0xff << 16) + +/* Helper for FIFO size calculation */ +#define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) + +static inline u32 dw8250_readl_ext(struct uart_port *p, int offset) +{ + if (p->iotype == UPIO_MEM32BE) + return ioread32be(p->membase + offset); + return readl(p->membase + offset); +} + +static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg) +{ + if (p->iotype == UPIO_MEM32BE) + iowrite32be(reg, p->membase + offset); + else + writel(reg, p->membase + offset); +} + +/* + * divisor = div(I) + div(F) + * "I" means integer, "F" means fractional + * quot = div(I) = clk / (16 * baud) + * frac = div(F) * 2^dlf_size + * + * let rem = clk % (16 * baud) + * we have: div(F) * (16 * baud) = rem + * so frac = 2^dlf_size * rem / (16 * baud) = (rem << dlf_size) / (16 * baud) + */ +static unsigned int dw8250_get_divisor(struct uart_port *p, unsigned int baud, + unsigned int *frac) +{ + unsigned int quot, rem, base_baud = baud * 16; + struct dw8250_port_data *d = p->private_data; + + quot = p->uartclk / base_baud; + rem = p->uartclk % base_baud; + *frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud); + + return quot; +} + +static void dw8250_set_divisor(struct uart_port *p, unsigned int baud, + unsigned int quot, unsigned int quot_frac) +{ + dw8250_writel_ext(p, DW_UART_DLF, quot_frac); + serial8250_do_set_divisor(p, baud, quot, quot_frac); +} + +void dw8250_setup_port(struct uart_port *p) +{ + struct uart_8250_port *up = up_to_u8250p(p); + u32 reg, old_dlf; + + /* + * If the Component Version Register returns zero, we know that + * ADDITIONAL_FEATURES are not enabled. No need to go any further. + */ + reg = dw8250_readl_ext(p, DW_UART_UCV); + if (!reg) + return; + + dev_dbg(p->dev, "Designware UART version %c.%c%c\n", + (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); + + /* Preserve value written by firmware or bootloader */ + old_dlf = dw8250_readl_ext(p, DW_UART_DLF); + dw8250_writel_ext(p, DW_UART_DLF, ~0U); + reg = dw8250_readl_ext(p, DW_UART_DLF); + dw8250_writel_ext(p, DW_UART_DLF, old_dlf); + + if (reg) { + struct dw8250_port_data *d = p->private_data; + + d->dlf_size = fls(reg); + p->get_divisor = dw8250_get_divisor; + p->set_divisor = dw8250_set_divisor; + } + + reg = dw8250_readl_ext(p, DW_UART_CPR); + if (!reg) + return; + + /* Select the type based on FIFO */ + if (reg & DW_UART_CPR_FIFO_MODE) { + p->type = PORT_16550A; + p->flags |= UPF_FIXED_TYPE; + p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); + up->capabilities = UART_CAP_FIFO; + } + + if (reg & DW_UART_CPR_AFCE_MODE) + up->capabilities |= UART_CAP_AFE; + + if (reg & DW_UART_CPR_SIR_MODE) + up->capabilities |= UART_CAP_IRDA; +} +EXPORT_SYMBOL_GPL(dw8250_setup_port); diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h new file mode 100644 index 0000000000000000000000000000000000000000..87a4db2a8aba6499bebe9a43fe2c0a416aa31986 --- /dev/null +++ b/drivers/tty/serial/8250/8250_dwlib.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Synopsys DesignWare 8250 library header file. */ + +#include + +#include "8250.h" + +struct dw8250_port_data { + /* Port properties */ + int line; + + /* DMA operations */ + struct uart_8250_dma dma; + + /* Hardware configuration */ + u8 dlf_size; +}; + +void dw8250_setup_port(struct uart_port *p); diff --git a/drivers/tty/serial/8250/8250_em.c b/drivers/tty/serial/8250/8250_em.c index 2a76e22d2ec046158d5ad4d1d689b5b7098c3de6..5670c8a267d87ae9400487787a45b55dad136d8d 100644 --- a/drivers/tty/serial/8250/8250_em.c +++ b/drivers/tty/serial/8250/8250_em.c @@ -102,8 +102,8 @@ static int serial8250_em_probe(struct platform_device *pdev) memset(&up, 0, sizeof(up)); up.port.mapbase = regs->start; up.port.irq = irq->start; - up.port.type = PORT_UNKNOWN; - up.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP; + up.port.type = PORT_16750; + up.port.flags = UPF_FIXED_PORT | UPF_IOREMAP | UPF_FIXED_TYPE; up.port.dev = &pdev->dev; up.port.private_data = priv; diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index fd9dd800e1a6a41f446bb3d0a31e288e2c447cb5..d05b155b48673cb814a2d17bff29a5c5e89da2a0 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -1049,14 +1049,6 @@ static int pci_oxsemi_tornado_init(struct pci_dev *dev) return number_uarts; } -static int pci_asix_setup(struct serial_private *priv, - const struct pciserial_board *board, - struct uart_8250_port *port, int idx) -{ - port->bugs |= UART_BUG_PARITY; - return pci_default_setup(priv, board, port, idx); -} - /* Quatech devices have their own extra interface features */ struct quatech_feature { @@ -1648,6 +1640,8 @@ pci_wch_ch38x_setup(struct serial_private *priv, #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 #define PCI_VENDOR_ID_ADVANTECH 0x13fe #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 +#define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600 +#define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 @@ -1681,7 +1675,6 @@ pci_wch_ch38x_setup(struct serial_private *priv, #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 #define PCI_VENDOR_ID_AGESTAR 0x5372 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 -#define PCI_VENDOR_ID_ASIX 0x9710 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e @@ -2452,16 +2445,6 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = { .subdevice = PCI_ANY_ID, .setup = pci_wch_ch38x_setup, }, - /* - * ASIX devices with FIFO bug - */ - { - .vendor = PCI_VENDOR_ID_ASIX, - .device = PCI_ANY_ID, - .subvendor = PCI_ANY_ID, - .subdevice = PCI_ANY_ID, - .setup = pci_asix_setup, - }, /* * Broadcom TruManage (NetXtreme) */ @@ -3840,6 +3823,9 @@ static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, pciserial_resume_one); static const struct pci_device_id serial_pci_tbl[] = { + { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600, + PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0, + pbn_b0_4_921600 }, /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, @@ -4785,6 +4771,12 @@ static const struct pci_device_id serial_pci_tbl[] = { 0, 0, pbn_b1_bt_1_115200 }, + /* + * IntaShield IS-100 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x0D60, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, + pbn_b2_1_115200 }, /* * IntaShield IS-200 */ @@ -4812,10 +4804,14 @@ static const struct pci_device_id serial_pci_tbl[] = { PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_b2_1_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0AA2, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_1_115200 }, /* - * Brainboxes UC-257 + * Brainboxes UC-253/UC-734 */ - { PCI_VENDOR_ID_INTASHIELD, 0x0861, + { PCI_VENDOR_ID_INTASHIELD, 0x0CA1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_b2_2_115200 }, @@ -4851,6 +4847,14 @@ static const struct pci_device_id serial_pci_tbl[] = { PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x08E2, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x08E3, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, /* * Brainboxes UC-310 */ @@ -4861,6 +4865,14 @@ static const struct pci_device_id serial_pci_tbl[] = { /* * Brainboxes UC-313 */ + { PCI_VENDOR_ID_INTASHIELD, 0x08A1, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x08A2, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, { PCI_VENDOR_ID_INTASHIELD, 0x08A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, @@ -4875,6 +4887,10 @@ static const struct pci_device_id serial_pci_tbl[] = { /* * Brainboxes UC-346 */ + { PCI_VENDOR_ID_INTASHIELD, 0x0B01, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_4_115200 }, { PCI_VENDOR_ID_INTASHIELD, 0x0B02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, @@ -4886,6 +4902,10 @@ static const struct pci_device_id serial_pci_tbl[] = { PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0A82, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, { PCI_VENDOR_ID_INTASHIELD, 0x0A83, PCI_ANY_ID, PCI_ANY_ID, 0, 0, @@ -4898,12 +4918,94 @@ static const struct pci_device_id serial_pci_tbl[] = { 0, 0, pbn_b2_4_115200 }, /* - * Brainboxes UC-420/431 + * Brainboxes UC-420 */ { PCI_VENDOR_ID_INTASHIELD, 0x0921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_b2_4_115200 }, + /* + * Brainboxes UC-607 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x09A1, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x09A2, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x09A3, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + /* + * Brainboxes UC-836 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x0D41, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_4_115200 }, + /* + * Brainboxes UP-189 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x0AC1, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0AC2, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0AC3, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + /* + * Brainboxes UP-200 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x0B21, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0B22, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0B23, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + /* + * Brainboxes UP-869 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x0C01, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0C02, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0C03, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + /* + * Brainboxes UP-880 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x0C21, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0C22, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0C23, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, /* * Perle PCI-RAS cards */ diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index 311a92482ff496242bf1287095e52d791b208814..2fac047a27139cbab9eb04e419516f1365609e85 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -1885,6 +1886,7 @@ int serial8250_handle_irq(struct uart_port *port, unsigned int iir) unsigned char status; unsigned long flags; struct uart_8250_port *up = up_to_u8250p(port); + struct tty_port *tport = &port->state->port; bool skip_rx = false; if (iir & UART_IIR_NO_INT) @@ -1908,6 +1910,11 @@ int serial8250_handle_irq(struct uart_port *port, unsigned int iir) skip_rx = true; if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) { + struct irq_data *d; + + d = irq_get_irq_data(port->irq); + if (d && irqd_is_wakeup_set(d)) + pm_wakeup_event(tport->tty->dev, 0); if (!up->dma || handle_rx_dma(up, iir)) status = serial8250_rx_chars(up, status); } @@ -1963,19 +1970,25 @@ static int serial8250_tx_threshold_handle_irq(struct uart_port *port) static unsigned int serial8250_tx_empty(struct uart_port *port) { struct uart_8250_port *up = up_to_u8250p(port); + unsigned int result = 0; unsigned long flags; unsigned int lsr; serial8250_rpm_get(up); spin_lock_irqsave(&port->lock, flags); - lsr = serial_port_in(port, UART_LSR); - up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; + if (!serial8250_tx_dma_running(up)) { + lsr = serial_port_in(port, UART_LSR); + up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; + + if ((lsr & BOTH_EMPTY) == BOTH_EMPTY) + result = TIOCSER_TEMT; + } spin_unlock_irqrestore(&port->lock, flags); serial8250_rpm_put(up); - return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; + return result; } unsigned int serial8250_do_get_mctrl(struct uart_port *port) @@ -2607,11 +2620,8 @@ static unsigned char serial8250_compute_lcr(struct uart_8250_port *up, if (c_cflag & CSTOPB) cval |= UART_LCR_STOP; - if (c_cflag & PARENB) { + if (c_cflag & PARENB) cval |= UART_LCR_PARITY; - if (up->bugs & UART_BUG_PARITY) - up->fifo_bug = true; - } if (!(c_cflag & PARODD)) cval |= UART_LCR_EPAR; #ifdef CMSPAR @@ -2725,8 +2735,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, up->lcr = cval; /* Save computed LCR */ if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) { - /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */ - if ((baud < 2400 && !up->dma) || up->fifo_bug) { + if (baud < 2400 && !up->dma) { up->fcr &= ~UART_FCR_TRIGGER_MASK; up->fcr |= UART_FCR_TRIGGER_1; } @@ -3062,8 +3071,7 @@ static int do_set_rxtrig(struct tty_port *port, unsigned char bytes) struct uart_8250_port *up = up_to_u8250p(uport); int rxtrig; - if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 || - up->fifo_bug) + if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1) return -EINVAL; rxtrig = bytes_to_fcr_rxtrig(up, bytes); @@ -3219,6 +3227,7 @@ void serial8250_init_port(struct uart_8250_port *up) struct uart_port *port = &up->port; spin_lock_init(&port->lock); + port->pm = NULL; port->ops = &serial8250_pops; up->cur_iotype = 0xFF; diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index a9ddd76d41701524c2a90c4a61cfc850d12f45eb..733ac320938c1cb04946b0702d85f4a51d309d33 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -312,6 +312,9 @@ config SERIAL_8250_RSA If you don't have such card, or if unsure, say N. +config SERIAL_8250_DWLIB + bool + config SERIAL_8250_ACORN tristate "Acorn expansion card serial port support" depends on ARCH_ACORN && SERIAL_8250 diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index 18751bc63a848ec6c806415eefd3c4088df06c3e..9b451d81588b27d61e03ae962e814fc610f01028 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_SERIAL_8250) += 8250.o 8250_base.o 8250-$(CONFIG_SERIAL_8250_PNP) += 8250_pnp.o 8250_base-y := 8250_port.o 8250_base-$(CONFIG_SERIAL_8250_DMA) += 8250_dma.o +8250_base-$(CONFIG_SERIAL_8250_DWLIB) += 8250_dwlib.o 8250_base-$(CONFIG_SERIAL_8250_FINTEK) += 8250_fintek.o obj-$(CONFIG_SERIAL_8250_GSC) += 8250_gsc.o obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o diff --git a/drivers/tty/serial/arc_uart.c b/drivers/tty/serial/arc_uart.c index d904a3a345e747854eba20b531c7e40147b2ba3c..dd4be3c8c049c21207e9b1de0772b17d82ea27f1 100644 --- a/drivers/tty/serial/arc_uart.c +++ b/drivers/tty/serial/arc_uart.c @@ -613,10 +613,11 @@ static int arc_serial_probe(struct platform_device *pdev) } uart->baud = val; - port->membase = of_iomap(np, 0); - if (!port->membase) + port->membase = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(port->membase)) { /* No point of dev_err since UART itself is hosed here */ - return -ENXIO; + return PTR_ERR(port->membase); + } port->irq = irq_of_parse_and_map(np, 0); diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index 50c4058a00e6a49b75a9e2e7397852ba91038bc0..1688c190fc7d86e3286d602230cd66039661a4f5 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -791,11 +791,11 @@ static void atmel_complete_tx_dma(void *arg) port->icount.tx += atmel_port->tx_len; - spin_lock_irq(&atmel_port->lock_tx); + spin_lock(&atmel_port->lock_tx); async_tx_ack(atmel_port->desc_tx); atmel_port->cookie_tx = -EINVAL; atmel_port->desc_tx = NULL; - spin_unlock_irq(&atmel_port->lock_tx); + spin_unlock(&atmel_port->lock_tx); if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) uart_write_wakeup(port); diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_core.c b/drivers/tty/serial/cpm_uart/cpm_uart_core.c index ad40c75bb58f84d5aceba4ca5340f673b16e0a75..375d4790e058ba480cfb529c7b42ad7939a9345a 100644 --- a/drivers/tty/serial/cpm_uart/cpm_uart_core.c +++ b/drivers/tty/serial/cpm_uart/cpm_uart_core.c @@ -1269,19 +1269,14 @@ static void cpm_uart_console_write(struct console *co, const char *s, { struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index]; unsigned long flags; - int nolock = oops_in_progress; - if (unlikely(nolock)) { + if (unlikely(oops_in_progress)) { local_irq_save(flags); - } else { - spin_lock_irqsave(&pinfo->port.lock, flags); - } - - cpm_uart_early_write(pinfo, s, count, true); - - if (unlikely(nolock)) { + cpm_uart_early_write(pinfo, s, count, true); local_irq_restore(flags); } else { + spin_lock_irqsave(&pinfo->port.lock, flags); + cpm_uart_early_write(pinfo, s, count, true); spin_unlock_irqrestore(&pinfo->port.lock, flags); } } diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 069d02354c825e170cd5ca2165e438cb1f28a548..af23d41b98438bc98e8ca84d744c1fd8ecf60917 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -994,7 +994,7 @@ static inline int lpuart_start_rx_dma(struct lpuart_port *sport) * 10ms at any baud rate. */ sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; - sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); + sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len)); if (sport->rx_dma_rng_buf_len < 16) sport->rx_dma_rng_buf_len = 16; @@ -1197,12 +1197,34 @@ static void lpuart32_break_ctl(struct uart_port *port, int break_state) { unsigned long temp; - temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; - - if (break_state != 0) - temp |= UARTCTRL_SBK; + temp = lpuart32_read(port, UARTCTRL); - lpuart32_write(port, temp, UARTCTRL); + /* + * LPUART IP now has two known bugs, one is CTS has higher priority than the + * break signal, which causes the break signal sending through UARTCTRL_SBK + * may impacted by the CTS input if the HW flow control is enabled. It + * exists on all platforms we support in this driver. + * Another bug is i.MX8QM LPUART may have an additional break character + * being sent after SBK was cleared. + * To avoid above two bugs, we use Transmit Data Inversion function to send + * the break signal instead of UARTCTRL_SBK. + */ + if (break_state != 0) { + /* + * Disable the transmitter to prevent any data from being sent out + * during break, then invert the TX line to send break. + */ + temp &= ~UARTCTRL_TE; + lpuart32_write(port, temp, UARTCTRL); + temp |= UARTCTRL_TXINV; + lpuart32_write(port, temp, UARTCTRL); + } else { + /* Disable the TXINV to turn off break and re-enable transmitter. */ + temp &= ~UARTCTRL_TXINV; + lpuart32_write(port, temp, UARTCTRL); + temp |= UARTCTRL_TE; + lpuart32_write(port, temp, UARTCTRL); + } } static void lpuart_setup_watermark(struct lpuart_port *sport) @@ -2114,6 +2136,8 @@ static int __init lpuart32_imx_early_console_setup(struct earlycon_device *devic OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); +OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup); +OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c index 044128277248b0298a67667c872b96dfc11fe472..6cd168cb673fd493a90a26d7a709e10ba8737b0d 100644 --- a/drivers/tty/serial/lantiq.c +++ b/drivers/tty/serial/lantiq.c @@ -113,6 +113,13 @@ struct ltq_uart_port { unsigned int err_irq; }; +static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg) +{ + u32 tmp = __raw_readl(reg); + + __raw_writel((tmp & ~clear) | set, reg); +} + static inline struct ltq_uart_port *to_ltq_uart_port(struct uart_port *port) { @@ -138,7 +145,7 @@ lqasc_start_tx(struct uart_port *port) static void lqasc_stop_rx(struct uart_port *port) { - ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); + __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); } static int @@ -147,11 +154,12 @@ lqasc_rx_chars(struct uart_port *port) struct tty_port *tport = &port->state->port; unsigned int ch = 0, rsr = 0, fifocnt; - fifocnt = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; + fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & + ASCFSTAT_RXFFLMASK; while (fifocnt--) { u8 flag = TTY_NORMAL; - ch = ltq_r8(port->membase + LTQ_ASC_RBUF); - rsr = (ltq_r32(port->membase + LTQ_ASC_STATE) + ch = readb(port->membase + LTQ_ASC_RBUF); + rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX; tty_flip_buffer_push(tport); port->icount.rx++; @@ -163,16 +171,16 @@ lqasc_rx_chars(struct uart_port *port) if (rsr & ASCSTATE_ANY) { if (rsr & ASCSTATE_PE) { port->icount.parity++; - ltq_w32_mask(0, ASCWHBSTATE_CLRPE, + asc_update_bits(0, ASCWHBSTATE_CLRPE, port->membase + LTQ_ASC_WHBSTATE); } else if (rsr & ASCSTATE_FE) { port->icount.frame++; - ltq_w32_mask(0, ASCWHBSTATE_CLRFE, + asc_update_bits(0, ASCWHBSTATE_CLRFE, port->membase + LTQ_ASC_WHBSTATE); } if (rsr & ASCSTATE_ROE) { port->icount.overrun++; - ltq_w32_mask(0, ASCWHBSTATE_CLRROE, + asc_update_bits(0, ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); } @@ -211,10 +219,10 @@ lqasc_tx_chars(struct uart_port *port) return; } - while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) & + while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) { if (port->x_char) { - ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF); + writeb(port->x_char, port->membase + LTQ_ASC_TBUF); port->icount.tx++; port->x_char = 0; continue; @@ -223,7 +231,7 @@ lqasc_tx_chars(struct uart_port *port) if (uart_circ_empty(xmit)) break; - ltq_w8(port->state->xmit.buf[port->state->xmit.tail], + writeb(port->state->xmit.buf[port->state->xmit.tail], port->membase + LTQ_ASC_TBUF); xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); port->icount.tx++; @@ -239,7 +247,7 @@ lqasc_tx_int(int irq, void *_port) unsigned long flags; struct uart_port *port = (struct uart_port *)_port; spin_lock_irqsave(<q_asc_lock, flags); - ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); + __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); spin_unlock_irqrestore(<q_asc_lock, flags); lqasc_start_tx(port); return IRQ_HANDLED; @@ -251,8 +259,9 @@ lqasc_err_int(int irq, void *_port) unsigned long flags; struct uart_port *port = (struct uart_port *)_port; spin_lock_irqsave(<q_asc_lock, flags); + __raw_writel(ASC_IRNCR_EIR, port->membase + LTQ_ASC_IRNCR); /* clear any pending interrupts */ - ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | + asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); spin_unlock_irqrestore(<q_asc_lock, flags); return IRQ_HANDLED; @@ -264,7 +273,7 @@ lqasc_rx_int(int irq, void *_port) unsigned long flags; struct uart_port *port = (struct uart_port *)_port; spin_lock_irqsave(<q_asc_lock, flags); - ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); + __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); lqasc_rx_chars(port); spin_unlock_irqrestore(<q_asc_lock, flags); return IRQ_HANDLED; @@ -274,7 +283,8 @@ static unsigned int lqasc_tx_empty(struct uart_port *port) { int status; - status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; + status = __raw_readl(port->membase + LTQ_ASC_FSTAT) & + ASCFSTAT_TXFFLMASK; return status ? 0 : TIOCSER_TEMT; } @@ -304,15 +314,15 @@ lqasc_startup(struct uart_port *port) clk_enable(ltq_port->clk); port->uartclk = clk_get_rate(ltq_port->fpiclk); - ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), + asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), port->membase + LTQ_ASC_CLC); - ltq_w32(0, port->membase + LTQ_ASC_PISEL); - ltq_w32( + __raw_writel(0, port->membase + LTQ_ASC_PISEL); + __raw_writel( ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + LTQ_ASC_TXFCON); - ltq_w32( + __raw_writel( ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + LTQ_ASC_RXFCON); @@ -320,7 +330,7 @@ lqasc_startup(struct uart_port *port) * setting enable bits */ wmb(); - ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | + asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + LTQ_ASC_CON); retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, @@ -344,7 +354,7 @@ lqasc_startup(struct uart_port *port) goto err2; } - ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, + __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, port->membase + LTQ_ASC_IRNREN); return 0; @@ -363,10 +373,10 @@ lqasc_shutdown(struct uart_port *port) free_irq(ltq_port->rx_irq, port); free_irq(ltq_port->err_irq, port); - ltq_w32(0, port->membase + LTQ_ASC_CON); - ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, + __raw_writel(0, port->membase + LTQ_ASC_CON); + asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, port->membase + LTQ_ASC_RXFCON); - ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, + asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, port->membase + LTQ_ASC_TXFCON); if (!IS_ERR(ltq_port->clk)) clk_disable(ltq_port->clk); @@ -438,7 +448,7 @@ lqasc_set_termios(struct uart_port *port, spin_lock_irqsave(<q_asc_lock, flags); /* set up CON */ - ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON); + asc_update_bits(0, con, port->membase + LTQ_ASC_CON); /* Set baud rate - take a divider of 2 into account */ baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); @@ -446,22 +456,22 @@ lqasc_set_termios(struct uart_port *port, divisor = divisor / 2 - 1; /* disable the baudrate generator */ - ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON); + asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON); /* make sure the fractional divider is off */ - ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); + asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); /* set up to use divisor of 2 */ - ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); + asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); /* now we can write the new baudrate into the register */ - ltq_w32(divisor, port->membase + LTQ_ASC_BG); + __raw_writel(divisor, port->membase + LTQ_ASC_BG); /* turn the baudrate generator back on */ - ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON); + asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON); /* enable rx */ - ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); + __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); spin_unlock_irqrestore(<q_asc_lock, flags); @@ -572,10 +582,10 @@ lqasc_console_putchar(struct uart_port *port, int ch) return; do { - fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT) + fifofree = (__raw_readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF; } while (fifofree == 0); - ltq_w8(ch, port->membase + LTQ_ASC_TBUF); + writeb(ch, port->membase + LTQ_ASC_TBUF); } static void lqasc_serial_port_write(struct uart_port *port, const char *s, diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c index 1838d0be37044ac546d0f69230703c17701e903f..adb0bbcecd24f6f8692501aa4f04b50a98fdc85f 100644 --- a/drivers/tty/serial/meson_uart.c +++ b/drivers/tty/serial/meson_uart.c @@ -72,7 +72,8 @@ #define AML_UART_BAUD_USE BIT(23) #define AML_UART_BAUD_XTAL BIT(24) -#define AML_UART_PORT_NUM 6 +#define AML_UART_PORT_NUM 12 +#define AML_UART_PORT_OFFSET 6 #define AML_UART_DEV_NAME "ttyAML" @@ -370,10 +371,14 @@ static void meson_uart_set_termios(struct uart_port *port, else val |= AML_UART_STOP_BIT_1SB; - if (cflags & CRTSCTS) - val &= ~AML_UART_TWO_WIRE_EN; - else + if (cflags & CRTSCTS) { + if (port->flags & UPF_HARD_FLOW) + val &= ~AML_UART_TWO_WIRE_EN; + else + termios->c_cflag &= ~CRTSCTS; + } else { val |= AML_UART_TWO_WIRE_EN; + } writel(val, port->membase + AML_UART_CONTROL); @@ -664,13 +669,27 @@ static int meson_uart_probe_clocks(struct platform_device *pdev, static int meson_uart_probe(struct platform_device *pdev) { - struct resource *res_mem, *res_irq; + struct resource *res_mem; struct uart_port *port; + u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */ int ret = 0; + int irq; + bool has_rtscts; if (pdev->dev.of_node) pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); + if (pdev->id < 0) { + int id; + + for (id = AML_UART_PORT_OFFSET; id < AML_UART_PORT_NUM; id++) { + if (!meson_ports[id]) { + pdev->id = id; + break; + } + } + } + if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM) return -EINVAL; @@ -678,9 +697,12 @@ static int meson_uart_probe(struct platform_device *pdev) if (!res_mem) return -ENODEV; - res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res_irq) - return -ENODEV; + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + of_property_read_u32(pdev->dev.of_node, "fifo-size", &fifosize); + has_rtscts = of_property_read_bool(pdev->dev.of_node, "uart-has-rtscts"); if (meson_ports[pdev->id]) { dev_err(&pdev->dev, "port %d already allocated\n", pdev->id); @@ -703,14 +725,16 @@ static int meson_uart_probe(struct platform_device *pdev) port->iotype = UPIO_MEM; port->mapbase = res_mem->start; port->mapsize = resource_size(res_mem); - port->irq = res_irq->start; + port->irq = irq; port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY; + if (has_rtscts) + port->flags |= UPF_HARD_FLOW; port->dev = &pdev->dev; port->line = pdev->id; port->type = PORT_MESON; port->x_char = 0; port->ops = &meson_uart_ops; - port->fifosize = 64; + port->fifosize = fifosize; meson_ports[pdev->id] = port; platform_set_drvdata(pdev, port); diff --git a/drivers/tty/serial/msm_geni_serial.c b/drivers/tty/serial/msm_geni_serial.c index eda66fdd0b948ffc464721d6f152efe3ba08e6d5..0aa47d2ac9118c3910e7215c286c0fd81a9a7c6f 100644 --- a/drivers/tty/serial/msm_geni_serial.c +++ b/drivers/tty/serial/msm_geni_serial.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -3601,6 +3601,7 @@ static int msm_geni_serial_remove(struct platform_device *pdev) if (!uart_console(&port->uport)) { wakeup_source_unregister(port->geni_wake); + port->geni_wake = NULL; flush_workqueue(port->qwork); destroy_workqueue(port->qwork); } diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index 964d6d33b60972675323748672e172deabe2db92..5f1f52cc63951bf7b4d0f3f704b6608ee58209aa 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c @@ -1199,8 +1199,12 @@ static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, continue; rate = clk_get_rate(clk); - if (!rate) + if (!rate) { + dev_err(ourport->port.dev, + "Failed to get clock rate for %s.\n", clkname); + clk_put(clk); continue; + } if (ourport->info->has_divslot) { unsigned long div = rate / req_baud; @@ -1226,10 +1230,18 @@ static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, calc_deviation = -calc_deviation; if (calc_deviation < deviation) { + /* + * If we find a better clk, release the previous one, if + * any. + */ + if (!IS_ERR(*best_clk)) + clk_put(*best_clk); *best_clk = clk; best_quot = quot; *clk_num = cnt; deviation = calc_deviation; + } else { + clk_put(clk); } } diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index ebea4a9d8e694bddf7789a3ee751925b6c30d973..d4496a44abdfed16cf702cbc35f801ba921b400d 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -1166,9 +1166,18 @@ static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, state |= BIT(offset); else state &= ~BIT(offset); - sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); + + /* + * If we write IOSTATE first, and then IODIR, the output value is not + * transferred to the corresponding I/O pin. + * The datasheet states that each register bit will be transferred to + * the corresponding I/O pin programmed as output when writing to + * IOSTATE. Therefore, configure direction first with IODIR, and then + * set value after with IOSTATE. + */ sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), BIT(offset)); + sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); return 0; } @@ -1255,6 +1264,13 @@ static int sc16is7xx_probe(struct device *dev, s->p[i].port.type = PORT_SC16IS7XX; s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; + s->p[i].port.iobase = i; + /* + * Use all ones as membase to make sure uart_configure_port() in + * serial_core.c does not abort for SPI/I2C devices where the + * membase address is not applicable. + */ + s->p[i].port.membase = (void __iomem *)~0; s->p[i].port.iotype = UPIO_PORT; s->p[i].port.uartclk = freq; s->p[i].port.rs485_config = sc16is7xx_config_rs485; diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c index 41fe45f2349efa4dd2693922bdeb23f1edddac82..a30f7ed123469544df52c8c42a6862bffd93ad07 100644 --- a/drivers/tty/serial/serial-tegra.c +++ b/drivers/tty/serial/serial-tegra.c @@ -944,7 +944,11 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup) tup->ier_shadow = 0; tup->current_baud = 0; - clk_prepare_enable(tup->uart_clk); + ret = clk_prepare_enable(tup->uart_clk); + if (ret) { + dev_err(tup->uport.dev, "could not enable clk\n"); + return ret; + } /* Reset the UART controller to clear all previous status.*/ reset_control_assert(tup->rst); diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index ba7f0b44b7107a37b26616538408cab5f91ebb0f..dfe9ac3b95af249a3e9f764d4c1af07fc41a2cde 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -2908,6 +2908,13 @@ static int sci_init_single(struct platform_device *dev, for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) sci_port->irqs[i] = platform_get_irq(dev, i); + /* + * The fourth interrupt on SCI port is transmit end interrupt, so + * shuffle the interrupts. + */ + if (p->type == PORT_SCI) + swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); + /* The SCI generates several interrupts. They can be muxed together or * connected to different interrupt lines. In the muxed case only one * interrupt resource is specified as there is only one interrupt ID. @@ -2973,7 +2980,7 @@ static int sci_init_single(struct platform_device *dev, port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; port->fifosize = sci_port->params->fifosize; - if (port->type == PORT_SCI) { + if (port->type == PORT_SCI && !dev->dev.of_node) { if (sci_port->reg_size >= 0x20) port->regshift = 2; else diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c index 9da56ca0a29e83a8827335b3b9d813443244f3c8..5b8e30d85a2dac970e28ead19acc795ca98d078e 100644 --- a/drivers/tty/tty_io.c +++ b/drivers/tty/tty_io.c @@ -875,13 +875,13 @@ static ssize_t tty_read(struct file *file, char __user *buf, size_t count, return i; } -static void tty_write_unlock(struct tty_struct *tty) +void tty_write_unlock(struct tty_struct *tty) { mutex_unlock(&tty->atomic_write_lock); wake_up_interruptible_poll(&tty->write_wait, EPOLLOUT); } -static int tty_write_lock(struct tty_struct *tty, int ndelay) +int tty_write_lock(struct tty_struct *tty, int ndelay) { if (!mutex_trylock(&tty->atomic_write_lock)) { if (ndelay) @@ -1155,14 +1155,16 @@ static struct tty_struct *tty_driver_lookup_tty(struct tty_driver *driver, { struct tty_struct *tty; - if (driver->ops->lookup) + if (driver->ops->lookup) { if (!file) tty = ERR_PTR(-EIO); else tty = driver->ops->lookup(driver, file, idx); - else + } else { + if (idx >= driver->num) + return ERR_PTR(-EINVAL); tty = driver->ttys[idx]; - + } if (!IS_ERR(tty)) tty_kref_get(tty); return tty; diff --git a/drivers/tty/tty_ioctl.c b/drivers/tty/tty_ioctl.c index d99fec44036c38156c996d840ac5c45643d2da2c..095c8780e210ba38f098ce05f09d0e9a1c73cd98 100644 --- a/drivers/tty/tty_ioctl.c +++ b/drivers/tty/tty_ioctl.c @@ -397,21 +397,42 @@ static int set_termios(struct tty_struct *tty, void __user *arg, int opt) tmp_termios.c_ispeed = tty_termios_input_baud_rate(&tmp_termios); tmp_termios.c_ospeed = tty_termios_baud_rate(&tmp_termios); - ld = tty_ldisc_ref(tty); + if (opt & (TERMIOS_FLUSH|TERMIOS_WAIT)) { +retry_write_wait: + retval = wait_event_interruptible(tty->write_wait, !tty_chars_in_buffer(tty)); + if (retval < 0) + return retval; - if (ld != NULL) { - if ((opt & TERMIOS_FLUSH) && ld->ops->flush_buffer) - ld->ops->flush_buffer(tty); - tty_ldisc_deref(ld); - } + if (tty_write_lock(tty, 0) < 0) + goto retry_write_wait; - if (opt & TERMIOS_WAIT) { - tty_wait_until_sent(tty, 0); - if (signal_pending(current)) - return -ERESTARTSYS; - } + /* Racing writer? */ + if (tty_chars_in_buffer(tty)) { + tty_write_unlock(tty); + goto retry_write_wait; + } + + ld = tty_ldisc_ref(tty); + if (ld != NULL) { + if ((opt & TERMIOS_FLUSH) && ld->ops->flush_buffer) + ld->ops->flush_buffer(tty); + tty_ldisc_deref(ld); + } + + if ((opt & TERMIOS_WAIT) && tty->ops->wait_until_sent) { + tty->ops->wait_until_sent(tty, 0); + if (signal_pending(current)) { + tty_write_unlock(tty); + return -ERESTARTSYS; + } + } + + tty_set_termios(tty, &tmp_termios); - tty_set_termios(tty, &tmp_termios); + tty_write_unlock(tty); + } else { + tty_set_termios(tty, &tmp_termios); + } /* FIXME: Arguably if tmp_termios == tty->termios AND the actual requested termios was not tmp_termios then we may diff --git a/drivers/tty/tty_jobctrl.c b/drivers/tty/tty_jobctrl.c index ffcab80ba77d9e7bad5b83930acc4b5e8a5f5032..73fdd55c6bef98de3d2ae14b8aab77ae22d919d1 100644 --- a/drivers/tty/tty_jobctrl.c +++ b/drivers/tty/tty_jobctrl.c @@ -290,12 +290,7 @@ void disassociate_ctty(int on_exit) return; } - spin_lock_irq(¤t->sighand->siglock); - put_pid(current->signal->tty_old_pgrp); - current->signal->tty_old_pgrp = NULL; - tty = tty_kref_get(current->signal->tty); - spin_unlock_irq(¤t->sighand->siglock); - + tty = get_current_tty(); if (tty) { unsigned long flags; @@ -310,6 +305,16 @@ void disassociate_ctty(int on_exit) tty_kref_put(tty); } + /* If tty->ctrl.pgrp is not NULL, it may be assigned to + * current->signal->tty_old_pgrp in a race condition, and + * cause pid memleak. Release current->signal->tty_old_pgrp + * after tty->ctrl.pgrp set to NULL. + */ + spin_lock_irq(¤t->sighand->siglock); + put_pid(current->signal->tty_old_pgrp); + current->signal->tty_old_pgrp = NULL; + spin_unlock_irq(¤t->sighand->siglock); + /* Now clear signal->tty under the lock */ read_lock(&tasklist_lock); session_clear_tty(task_session(current)); diff --git a/drivers/tty/vcc.c b/drivers/tty/vcc.c index 10a832a2135e2974b235e5dc0e2720cc7a3d704a..31ecba113315950633865c88612826f2c9c5c605 100644 --- a/drivers/tty/vcc.c +++ b/drivers/tty/vcc.c @@ -586,18 +586,22 @@ static int vcc_probe(struct vio_dev *vdev, const struct vio_device_id *id) return -ENOMEM; name = kstrdup(dev_name(&vdev->dev), GFP_KERNEL); + if (!name) { + rv = -ENOMEM; + goto free_port; + } rv = vio_driver_init(&port->vio, vdev, VDEV_CONSOLE_CON, vcc_versions, ARRAY_SIZE(vcc_versions), NULL, name); if (rv) - goto free_port; + goto free_name; port->vio.debug = vcc_dbg_vio; vcc_ldc_cfg.debug = vcc_dbg_ldc; rv = vio_ldc_alloc(&port->vio, &vcc_ldc_cfg, port); if (rv) - goto free_port; + goto free_name; spin_lock_init(&port->lock); @@ -631,6 +635,11 @@ static int vcc_probe(struct vio_dev *vdev, const struct vio_device_id *id) goto unreg_tty; } port->domain = kstrdup(domain, GFP_KERNEL); + if (!port->domain) { + rv = -ENOMEM; + goto unreg_tty; + } + mdesc_release(hp); @@ -660,8 +669,9 @@ static int vcc_probe(struct vio_dev *vdev, const struct vio_device_id *id) vcc_table_remove(port->index); free_ldc: vio_ldc_free(&port->vio); -free_port: +free_name: kfree(name); +free_port: kfree(port); return rv; diff --git a/drivers/tty/vt/vc_screen.c b/drivers/tty/vt/vc_screen.c index 5b5e800ab15490919606f95ee147e587d0c75473..78ea9b9c64501926a70dd966fdba89ff786f7659 100644 --- a/drivers/tty/vt/vc_screen.c +++ b/drivers/tty/vt/vc_screen.c @@ -182,39 +182,47 @@ vcs_vc(struct inode *inode, int *viewed) return vc_cons[currcons].d; } -/* - * Returns size for VC carried by inode. +/** + * vcs_size -- return size for a VC in @vc + * @vc: which VC + * @attr: does it use attributes? + * @unicode: is it unicode? + * * Must be called with console_lock. */ -static int -vcs_size(struct inode *inode) +static int vcs_size(const struct vc_data *vc, bool attr, bool unicode) { int size; - struct vc_data *vc; WARN_CONSOLE_UNLOCKED(); - vc = vcs_vc(inode, NULL); - if (!vc) - return -ENXIO; - size = vc->vc_rows * vc->vc_cols; - if (use_attributes(inode)) { - if (use_unicode(inode)) + if (attr) { + if (unicode) return -EOPNOTSUPP; - size = 2*size + HEADER_SIZE; - } else if (use_unicode(inode)) + + size = 2 * size + HEADER_SIZE; + } else if (unicode) size *= 4; + return size; } static loff_t vcs_lseek(struct file *file, loff_t offset, int orig) { + struct inode *inode = file_inode(file); + struct vc_data *vc; int size; console_lock(); - size = vcs_size(file_inode(file)); + vc = vcs_vc(inode, NULL); + if (!vc) { + console_unlock(); + return -ENXIO; + } + + size = vcs_size(vc, use_attributes(inode), use_unicode(inode)); console_unlock(); if (size < 0) return size; @@ -276,12 +284,10 @@ vcs_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) * as copy_to_user at the end of this loop * could sleep. */ - size = vcs_size(inode); + size = vcs_size(vc, attr, uni_mode); if (size < 0) { - if (read) - break; ret = size; - goto unlock_out; + break; } if (pos >= size) break; @@ -459,7 +465,11 @@ vcs_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) if (!vc) goto unlock_out; - size = vcs_size(inode); + size = vcs_size(vc, attr, false); + if (size < 0) { + ret = size; + goto unlock_out; + } ret = -EINVAL; if (pos < 0 || pos > size) goto unlock_out; @@ -494,11 +504,18 @@ vcs_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) } } - /* The vcs_size might have changed while we slept to grab - * the user buffer, so recheck. + /* The vc might have been freed or vcs_size might have changed + * while we slept to grab the user buffer, so recheck. * Return data written up to now on failure. */ - size = vcs_size(inode); + vc = vcs_vc(inode, &viewed); + if (!vc) { + if (written) + break; + ret = -ENXIO; + goto unlock_out; + } + size = vcs_size(vc, attr, false); if (size < 0) { if (written) break; diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h index 6a2cc5cd0281d8d728fb4f083798b2ea6bf55cc8..d0e9f3265f5a0c82b1ac4f10c628eeb5f9be9fd6 100644 --- a/drivers/usb/chipidea/ci.h +++ b/drivers/usb/chipidea/ci.h @@ -202,6 +202,7 @@ struct hw_bank { * @in_lpm: if the core in low power mode * @wakeup_int: if wakeup interrupt occur * @rev: The revision number for controller + * @mutex: protect code from concorrent running when doing role switch */ struct ci_hdrc { struct device *dev; @@ -254,6 +255,7 @@ struct ci_hdrc { bool in_lpm; bool wakeup_int; enum ci_revision rev; + struct mutex mutex; }; static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci) diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index c13f9a153a5c63f7abc6cde619004261b93f0ef6..9f6a52ed038e27576f879a80c28d004c7ba9e9a5 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -872,9 +872,16 @@ static ssize_t role_store(struct device *dev, strlen(ci->roles[role]->name))) break; - if (role == CI_ROLE_END || role == ci->role) + if (role == CI_ROLE_END) return -EINVAL; + mutex_lock(&ci->mutex); + + if (role == ci->role) { + mutex_unlock(&ci->mutex); + return n; + } + pm_runtime_get_sync(dev); disable_irq(ci->irq); ci_role_stop(ci); @@ -883,6 +890,7 @@ static ssize_t role_store(struct device *dev, ci_handle_vbus_change(ci); enable_irq(ci->irq); pm_runtime_put_sync(dev); + mutex_unlock(&ci->mutex); return (ret == 0) ? n : ret; } @@ -921,6 +929,7 @@ static int ci_hdrc_probe(struct platform_device *pdev) return -ENOMEM; spin_lock_init(&ci->lock); + mutex_init(&ci->mutex); ci->dev = dev; ci->platdata = dev_get_platdata(dev); ci->imx28_write_fix = !!(ci->platdata->flags & @@ -975,7 +984,7 @@ static int ci_hdrc_probe(struct platform_device *pdev) ret = ci_usb_phy_init(ci); if (ret) { dev_err(dev, "unable to init phy: %d\n", ret); - return ret; + goto ulpi_exit; } ci->hw_bank.phys = res->start; diff --git a/drivers/usb/chipidea/otg.c b/drivers/usb/chipidea/otg.c index f25d4827fd49c41179326f517b8aeaa7999f54dd..a714cf3f0ab7a5b0fc0f402b4ade1a381125ec4a 100644 --- a/drivers/usb/chipidea/otg.c +++ b/drivers/usb/chipidea/otg.c @@ -164,8 +164,10 @@ static int hw_wait_vbus_lower_bsv(struct ci_hdrc *ci) static void ci_handle_id_switch(struct ci_hdrc *ci) { - enum ci_role role = ci_otg_role(ci); + enum ci_role role; + mutex_lock(&ci->mutex); + role = ci_otg_role(ci); if (role != ci->role) { dev_dbg(ci->dev, "switching from %s to %s\n", ci_role(ci)->name, ci->roles[role]->name); @@ -188,6 +190,7 @@ static void ci_handle_id_switch(struct ci_hdrc *ci) if (role == CI_ROLE_GADGET) ci_handle_vbus_change(ci); } + mutex_unlock(&ci->mutex); } /** * ci_otg_work - perform otg (vbus/id) event handle diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index 4785f286c7e275b3199e45b9b7e29fa4889b5322..46ff20048d6f063563f9cabb8a9a64e19ad784ac 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -153,6 +153,10 @@ int usb_device_supports_lpm(struct usb_device *udev) if (udev->quirks & USB_QUIRK_NO_LPM) return 0; + /* Skip if the device BOS descriptor couldn't be read */ + if (!udev->bos) + return 0; + /* USB 2.1 (and greater) devices indicate LPM support through * their USB 2.0 Extended Capabilities BOS descriptor. */ @@ -329,6 +333,10 @@ static void usb_set_lpm_parameters(struct usb_device *udev) if (!udev->lpm_capable || udev->speed < USB_SPEED_SUPER) return; + /* Skip if the device BOS descriptor couldn't be read */ + if (!udev->bos) + return; + hub = usb_hub_to_struct_hub(udev->parent); /* It doesn't take time to transition the roothub into U0, since it * doesn't have an upstream link. @@ -2656,7 +2664,8 @@ int usb_authorize_device(struct usb_device *usb_dev) } /* - * Return 1 if port speed is SuperSpeedPlus, 0 otherwise + * Return 1 if port speed is SuperSpeedPlus, 0 otherwise or if the + * capability couldn't be checked. * check it from the link protocol field of the current speed ID attribute. * current speed ID is got from ext port status request. Sublink speed attribute * table is returned with the hub BOS SSP device capability descriptor @@ -2666,8 +2675,12 @@ static int port_speed_is_ssp(struct usb_device *hdev, int speed_id) int ssa_count; u32 ss_attr; int i; - struct usb_ssp_cap_descriptor *ssp_cap = hdev->bos->ssp_cap; + struct usb_ssp_cap_descriptor *ssp_cap; + if (!hdev->bos) + return 0; + + ssp_cap = hdev->bos->ssp_cap; if (!ssp_cap) return 0; @@ -4072,8 +4085,15 @@ static void usb_enable_link_state(struct usb_hcd *hcd, struct usb_device *udev, enum usb3_link_state state) { int timeout, ret; - __u8 u1_mel = udev->bos->ss_cap->bU1devExitLat; - __le16 u2_mel = udev->bos->ss_cap->bU2DevExitLat; + __u8 u1_mel; + __le16 u2_mel; + + /* Skip if the device BOS descriptor couldn't be read */ + if (!udev->bos) + return; + + u1_mel = udev->bos->ss_cap->bU1devExitLat; + u2_mel = udev->bos->ss_cap->bU2DevExitLat; /* If the device says it doesn't have *any* exit latency to come out of * U1 or U2, it's probably lying. Assume it doesn't implement that link diff --git a/drivers/usb/core/hub.h b/drivers/usb/core/hub.h index df3aa0b69188fb9b4837d6f1e602532b38b0a4d8..d1845e5ff7006d09d25f329dead619b8f0fbe472 100644 --- a/drivers/usb/core/hub.h +++ b/drivers/usb/core/hub.h @@ -139,7 +139,7 @@ static inline int hub_is_superspeedplus(struct usb_device *hdev) { return (hdev->descriptor.bDeviceProtocol == USB_HUB_PR_SS && le16_to_cpu(hdev->descriptor.bcdUSB) >= 0x0310 && - hdev->bos->ssp_cap); + hdev->bos && hdev->bos->ssp_cap); } static inline unsigned hub_power_on_good_delay(struct usb_hub *hub) diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c index 1346c600ebedfa4d99450a572f569ca7f28d195b..48cda9b7a8f247cc981f1d92835899f5e2228ebc 100644 --- a/drivers/usb/core/quirks.c +++ b/drivers/usb/core/quirks.c @@ -437,6 +437,10 @@ static const struct usb_device_id usb_quirk_list[] = { /* novation SoundControl XL */ { USB_DEVICE(0x1235, 0x0061), .driver_info = USB_QUIRK_RESET_RESUME }, + /* Focusrite Scarlett Solo USB */ + { USB_DEVICE(0x1235, 0x8211), .driver_info = + USB_QUIRK_DISCONNECT_SUSPEND }, + /* Huawei 4G LTE module */ { USB_DEVICE(0x12d1, 0x15bb), .driver_info = USB_QUIRK_DISCONNECT_SUSPEND }, diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c index 88fe9aa65799a30768a91a6ba81b192e6388cff4..a7faf5101bcfd51fefddbc9341e82d7f15653f0c 100644 --- a/drivers/usb/core/usb.c +++ b/drivers/usb/core/usb.c @@ -209,6 +209,82 @@ int usb_find_common_endpoints_reverse(struct usb_host_interface *alt, } EXPORT_SYMBOL_GPL(usb_find_common_endpoints_reverse); +/** + * usb_find_endpoint() - Given an endpoint address, search for the endpoint's + * usb_host_endpoint structure in an interface's current altsetting. + * @intf: the interface whose current altsetting should be searched + * @ep_addr: the endpoint address (number and direction) to find + * + * Search the altsetting's list of endpoints for one with the specified address. + * + * Return: Pointer to the usb_host_endpoint if found, %NULL otherwise. + */ +static const struct usb_host_endpoint *usb_find_endpoint( + const struct usb_interface *intf, unsigned int ep_addr) +{ + int n; + const struct usb_host_endpoint *ep; + + n = intf->cur_altsetting->desc.bNumEndpoints; + ep = intf->cur_altsetting->endpoint; + for (; n > 0; (--n, ++ep)) { + if (ep->desc.bEndpointAddress == ep_addr) + return ep; + } + return NULL; +} + +/** + * usb_check_bulk_endpoints - Check whether an interface's current altsetting + * contains a set of bulk endpoints with the given addresses. + * @intf: the interface whose current altsetting should be searched + * @ep_addrs: 0-terminated array of the endpoint addresses (number and + * direction) to look for + * + * Search for endpoints with the specified addresses and check their types. + * + * Return: %true if all the endpoints are found and are bulk, %false otherwise. + */ +bool usb_check_bulk_endpoints( + const struct usb_interface *intf, const u8 *ep_addrs) +{ + const struct usb_host_endpoint *ep; + + for (; *ep_addrs; ++ep_addrs) { + ep = usb_find_endpoint(intf, *ep_addrs); + if (!ep || !usb_endpoint_xfer_bulk(&ep->desc)) + return false; + } + return true; +} +EXPORT_SYMBOL_GPL(usb_check_bulk_endpoints); + +/** + * usb_check_int_endpoints - Check whether an interface's current altsetting + * contains a set of interrupt endpoints with the given addresses. + * @intf: the interface whose current altsetting should be searched + * @ep_addrs: 0-terminated array of the endpoint addresses (number and + * direction) to look for + * + * Search for endpoints with the specified addresses and check their types. + * + * Return: %true if all the endpoints are found and are interrupt, + * %false otherwise. + */ +bool usb_check_int_endpoints( + const struct usb_interface *intf, const u8 *ep_addrs) +{ + const struct usb_host_endpoint *ep; + + for (; *ep_addrs; ++ep_addrs) { + ep = usb_find_endpoint(intf, *ep_addrs); + if (!ep || !usb_endpoint_xfer_int(&ep->desc)) + return false; + } + return true; +} +EXPORT_SYMBOL_GPL(usb_check_int_endpoints); + /** * usb_find_alt_setting() - Given a configuration, find the alternate setting * for the given interface. diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index cfda88318583860053f5cc898c7f7b04902ea74d..91fa831328fce7b0826a5ff09fbcaab8e463df4b 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -4845,8 +4845,8 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, if (qh_allocated && qh->channel && qh->channel->qh == qh) qh->channel->qh = NULL; fail2: - spin_unlock_irqrestore(&hsotg->lock, flags); urb->hcpriv = NULL; + spin_unlock_irqrestore(&hsotg->lock, flags); kfree(qtd); qtd = NULL; fail1: diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index f31305a76271fdfa5a9de1b19a5a7d22ff2ef9d7..a46eb14416d68675363fdee6327068cd0c578274 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -239,11 +239,48 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) /* * We're resetting only the device side because, if we're in host mode, * XHCI driver will reset the host block. If dwc3 was configured for - * host-only mode, then we can return early. + * host-only mode or current role is host, then we can return early. */ if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) return 0; + /* + * If the dr_mode is host and the dwc->current_dr_role is not the + * corresponding DWC3_GCTL_PRTCAP_HOST, then the dwc3_core_init_mode + * isn't executed yet. Ensure the phy is ready before the controller + * updates the GCTL.PRTCAPDIR or other settings by soft-resetting + * the phy. + * + * Note: GUSB3PIPECTL[n] and GUSB2PHYCFG[n] are port settings where n + * is port index. If this is a multiport host, then we need to reset + * all active ports. + */ + if (dwc->dr_mode == USB_DR_MODE_HOST) { + u32 usb3_port; + u32 usb2_port; + + usb3_port = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + usb3_port |= DWC3_GUSB3PIPECTL_PHYSOFTRST; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port); + + usb2_port = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + usb2_port |= DWC3_GUSB2PHYCFG_PHYSOFTRST; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port); + + /* Small delay for phy reset assertion */ + usleep_range(1000, 2000); + + usb3_port &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port); + + usb2_port &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port); + + /* Wait for clock synchronization */ + msleep(50); + return 0; + } + reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg |= DWC3_DCTL_CSFTRST; dwc3_writel(dwc->regs, DWC3_DCTL, reg); @@ -1021,21 +1058,6 @@ int dwc3_core_init(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); } - if (dwc->dr_mode == USB_DR_MODE_HOST || dwc3_is_otg_or_drd(dwc)) { - reg = dwc3_readl(dwc->regs, DWC3_GUCTL); - - /* - * Enable Auto retry Feature to make the controller operating in - * Host mode on seeing transaction errors(CRC errors or internal - * overrun scenerios) on IN transfers to reply to the device - * with a non-terminating retry ACK (i.e, an ACK transcation - * packet with Retry=1 & Nump != 0) - */ - reg |= DWC3_GUCTL_HSTINAUTORETRY; - - dwc3_writel(dwc->regs, DWC3_GUCTL, reg); - } - /* * Must config both number of packets and max burst settings to enable * RX and/or TX threshold. diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index ab6594716a958c8afacbfdd2c979b9dfbc39f9dc..9980293fb220da56ae3ec8391d998eb826eca0a8 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -259,9 +259,6 @@ #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) #define DWC3_GCTL_DSBLCLKGTNG BIT(0) -/* Global User Control Register */ -#define DWC3_GUCTL_HSTINAUTORETRY BIT(14) - /* Global User Control 1 Register */ #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c index ed6220cbf091c2fb550a21ef5f79117f8c39fa44..0a54a517af7d3c0599b7d5c5a7072b2d770529e1 100644 --- a/drivers/usb/dwc3/dwc3-msm.c +++ b/drivers/usb/dwc3/dwc3-msm.c @@ -2006,6 +2006,24 @@ static void dwc3_gsi_event_buf_alloc(struct dwc3 *dwc) } } +static void dwc3_msm_modify_pipectl(struct dwc3 *dwc, bool set) +{ + struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); + u32 reg; + + reg = dwc3_msm_read_reg(mdwc->base, DWC3_GUSB3PIPECTL(0)); + + if (set) { + if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && + (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) + reg |= DWC3_GUSB3PIPECTL_SUSPHY; + } else { + reg &= ~(DWC3_GUSB3PIPECTL_SUSPHY); + } + + dwc3_msm_write_reg(mdwc->base, DWC3_GUSB3PIPECTL(0), reg); +} + static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event, unsigned int value) { @@ -2071,6 +2089,9 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event, break; case DWC3_CONTROLLER_CONNDONE_EVENT: dev_dbg(mdwc->dev, "DWC3_CONTROLLER_CONNDONE_EVENT received\n"); + + dwc3_msm_modify_pipectl(dwc, true); + /* * Add power event if the dbm indicates coming out of L1 by * interrupt @@ -2195,6 +2216,13 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event, break; case DWC3_CONTROLLER_NOTIFY_CLEAR_DB: dev_dbg(mdwc->dev, "DWC3_CONTROLLER_NOTIFY_CLEAR_DB\n"); + + /* + * Clear the susphy bit here to ensure it is not set during + * the course of controller initialisation process. + */ + dwc3_msm_modify_pipectl(dwc, false); + if (!mdwc->gsi_ev_buff) break; @@ -2267,15 +2295,6 @@ static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc) dev_err(mdwc->dev, "%s: dwc3_core init failed (%d)\n", __func__, ret); - /* Get initial P3 status and enable IN_P3 event */ - if (dwc3_is_usb31(dwc)) - val = dwc3_msm_read_reg_field(mdwc->base, - DWC31_LINK_GDBGLTSSM, - DWC3_GDBGLTSSM_LINKSTATE_MASK); - else - val = dwc3_msm_read_reg_field(mdwc->base, - DWC3_GDBGLTSSM, DWC3_GDBGLTSSM_LINKSTATE_MASK); - atomic_set(&mdwc->in_p3, val == DWC3_LINK_STATE_U3); dwc3_msm_write_reg_field(mdwc->base, PWR_EVNT_IRQ_MASK_REG, PWR_EVNT_POWERDOWN_IN_P3_MASK, 1); diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c index 955bf820f41025a84915702516d41d029bd14deb..8d4f1b13f415735f29bdfe652a121ad7a01afc7c 100644 --- a/drivers/usb/dwc3/dwc3-pci.c +++ b/drivers/usb/dwc3/dwc3-pci.c @@ -171,10 +171,12 @@ static int dwc3_pci_quirks(struct dwc3_pci *dwc) /* * A lot of BYT devices lack ACPI resource entries for - * the GPIOs, add a fallback mapping to the reference + * the GPIOs. If the ACPI entry for the GPIO controller + * is present add a fallback mapping to the reference * design GPIOs which all boards seem to use. */ - gpiod_add_lookup_table(&platform_bytcr_gpios); + if (acpi_dev_present("INT33FC", NULL, -1)) + gpiod_add_lookup_table(&platform_bytcr_gpios); /* * These GPIOs will turn on the USB2 PHY. Note that we have to diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 58e1bc3a77d80671eb1b5b97a0b7dcf850d390b6..0f090188e265b4857c1c1cf67a113a772bffac32 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -176,55 +176,58 @@ static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom) /* Only usable in contexts where the role can not change. */ static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom) { - struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); + struct dwc3 *dwc; + + /* + * FIXME: Fix this layering violation. + */ + dwc = platform_get_drvdata(qcom->dwc3); + + /* Core driver may not have probed yet. */ + if (!dwc) + return false; return dwc->xhci; } +static void dwc3_qcom_enable_wakeup_irq(int irq) +{ + if (!irq) + return; + + enable_irq(irq); + enable_irq_wake(irq); +} + +static void dwc3_qcom_disable_wakeup_irq(int irq) +{ + if (!irq) + return; + + disable_irq_wake(irq); + disable_irq_nosync(irq); +} + static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) { - if (qcom->hs_phy_irq) { - disable_irq_wake(qcom->hs_phy_irq); - disable_irq_nosync(qcom->hs_phy_irq); - } + dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq); - if (qcom->dp_hs_phy_irq) { - disable_irq_wake(qcom->dp_hs_phy_irq); - disable_irq_nosync(qcom->dp_hs_phy_irq); - } + dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); - if (qcom->dm_hs_phy_irq) { - disable_irq_wake(qcom->dm_hs_phy_irq); - disable_irq_nosync(qcom->dm_hs_phy_irq); - } + dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); - if (qcom->ss_phy_irq) { - disable_irq_wake(qcom->ss_phy_irq); - disable_irq_nosync(qcom->ss_phy_irq); - } + dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq); } static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) { - if (qcom->hs_phy_irq) { - enable_irq(qcom->hs_phy_irq); - enable_irq_wake(qcom->hs_phy_irq); - } + dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq); - if (qcom->dp_hs_phy_irq) { - enable_irq(qcom->dp_hs_phy_irq); - enable_irq_wake(qcom->dp_hs_phy_irq); - } + dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq); - if (qcom->dm_hs_phy_irq) { - enable_irq(qcom->dm_hs_phy_irq); - enable_irq_wake(qcom->dm_hs_phy_irq); - } + dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq); - if (qcom->ss_phy_irq) { - enable_irq(qcom->ss_phy_irq); - enable_irq_wake(qcom->ss_phy_irq); - } + dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq); } static int dwc3_qcom_suspend(struct dwc3_qcom *qcom) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 6160be6af52aab6b0d93b13ed6b3ef9e21360b55..c5daf40582e9679c63031a203ab7e07978788325 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -288,6 +288,7 @@ static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep, list_del(&req->list); req->remaining = 0; req->needs_extra_trb = false; + req->num_trbs = 0; if (req->request.status == -EINPROGRESS) req->request.status = status; @@ -2521,8 +2522,11 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) /* prevent pending bh to run later */ flush_work(&dwc->bh_work); - if (is_on) - dwc3_device_core_soft_reset(dwc); + if (is_on) { + ret = dwc3_device_core_soft_reset(dwc); + if (ret != 0) + goto done; + } spin_lock_irqsave(&dwc->lock, flags); if (dwc->ep0state != EP0_SETUP_PHASE) @@ -2551,6 +2555,7 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) } enable_irq(dwc->irq); +done: pm_runtime_mark_last_busy(dwc->dev); pm_runtime_put_autosuspend(dwc->dev); dbg_event(0xFF, "Pullup put", @@ -4494,6 +4499,8 @@ void dwc3_gadget_process_pending_events(struct dwc3 *dwc) { if (dwc->pending_events) { dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); + dwc3_thread_interrupt(dwc->irq_gadget, dwc->ev_buf); + pm_runtime_put(dwc->dev); dwc->pending_events = false; enable_irq(dwc->irq_gadget); } diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index 1c38b65505f04eb0180f36e92c246abd073280f6..aaf0c440c9ac4ff8ec10134d1d42e825b129752e 100644 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -3843,10 +3843,9 @@ static void ffs_func_unbind(struct usb_configuration *c, /* Drain any pending AIO completions */ drain_workqueue(ffs->io_completion_wq); - if (!--opts->refcnt) { - ffs_event_add(ffs, FUNCTIONFS_UNBIND); + ffs_event_add(ffs, FUNCTIONFS_UNBIND); + if (!--opts->refcnt) functionfs_unbind(ffs); - } /* cleanup after autoconfig */ spin_lock_irqsave(&func->ffs->eps_lock, flags); @@ -3870,12 +3869,8 @@ static void ffs_func_unbind(struct usb_configuration *c, func->function.ssp_descriptors = NULL; func->interfaces_nums = NULL; - if (opts->refcnt) { - ffs_event_add(ffs, FUNCTIONFS_UNBIND); - - ffs_log("exit: state %d setup_state %d flag %lu", ffs->state, - ffs->setup_state, ffs->flags); - } + ffs_log("exit: state %d setup_state %d flag %lu", ffs->state, + ffs->setup_state, ffs->flags); } static struct usb_function *ffs_alloc(struct usb_function_instance *fi) diff --git a/drivers/usb/gadget/function/f_mass_storage.c b/drivers/usb/gadget/function/f_mass_storage.c index 0b7b4d09785b6e22be0d3a22d111bf9402e003ff..4f221ca7aad15bc4193b79d15cc2c84947b40ad8 100644 --- a/drivers/usb/gadget/function/f_mass_storage.c +++ b/drivers/usb/gadget/function/f_mass_storage.c @@ -950,7 +950,7 @@ static void invalidate_sub(struct fsg_lun *curlun) { struct file *filp = curlun->filp; struct inode *inode = file_inode(filp); - unsigned long rc; + unsigned long __maybe_unused rc; rc = invalidate_mapping_pages(inode->i_mapping, 0, -1); VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc); diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c index d6d7b66197c29294b7975da0f2f53a730d02479c..a7c34ec7ffa0ac3a788b67d7179c28eb57543f39 100644 --- a/drivers/usb/gadget/function/f_ncm.c +++ b/drivers/usb/gadget/function/f_ncm.c @@ -23,6 +23,7 @@ #include "u_ether.h" #include "u_ether_configfs.h" #include "u_ncm.h" +#include "configfs.h" /* * This function is a "CDC Network Control Model" (CDC NCM) Ethernet link. @@ -35,9 +36,7 @@ /* to trigger crc/non-crc ndp signature */ -#define NCM_NDP_HDR_CRC_MASK 0x01000000 #define NCM_NDP_HDR_CRC 0x01000000 -#define NCM_NDP_HDR_NOCRC 0x00000000 enum ncm_notify_state { NCM_NOTIFY_NONE, /* don't notify */ @@ -531,6 +530,7 @@ static inline void ncm_reset_values(struct f_ncm *ncm) { ncm->parser_opts = &ndp16_opts; ncm->is_crc = false; + ncm->ndp_sign = ncm->parser_opts->ndp_sign; ncm->port.cdc_filter = DEFAULT_FILTER; /* doesn't make sense for ncm, fixed size used */ @@ -813,25 +813,20 @@ static int ncm_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) case ((USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8) | USB_CDC_SET_CRC_MODE: { - int ndp_hdr_crc = 0; - if (w_length != 0 || w_index != ncm->ctrl_id) goto invalid; switch (w_value) { case 0x0000: ncm->is_crc = false; - ndp_hdr_crc = NCM_NDP_HDR_NOCRC; DBG(cdev, "non-CRC mode selected\n"); break; case 0x0001: ncm->is_crc = true; - ndp_hdr_crc = NCM_NDP_HDR_CRC; DBG(cdev, "CRC mode selected\n"); break; default: goto invalid; } - ncm->ndp_sign = ncm->parser_opts->ndp_sign | ndp_hdr_crc; value = 0; break; } @@ -848,6 +843,8 @@ static int ncm_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) ctrl->bRequestType, ctrl->bRequest, w_value, w_index, w_length); } + ncm->ndp_sign = ncm->parser_opts->ndp_sign | + (ncm->is_crc ? NCM_NDP_HDR_CRC : 0); /* respond with data transfer or status phase? */ if (value >= 0) { @@ -1183,7 +1180,8 @@ static int ncm_unwrap_ntb(struct gether *port, struct sk_buff_head *list) { struct f_ncm *ncm = func_to_ncm(&port->func); - __le16 *tmp = (void *) skb->data; + unsigned char *ntb_ptr = skb->data; + __le16 *tmp; unsigned index, index2; int ndp_index; unsigned dg_len, dg_len2; @@ -1196,6 +1194,10 @@ static int ncm_unwrap_ntb(struct gether *port, const struct ndp_parser_opts *opts = ncm->parser_opts; unsigned crc_len = ncm->is_crc ? sizeof(uint32_t) : 0; int dgram_counter; + int to_process = skb->len; + +parse_ntb: + tmp = (__le16 *)ntb_ptr; /* dwSignature */ if (get_unaligned_le32(tmp) != opts->nth_sign) { @@ -1242,7 +1244,7 @@ static int ncm_unwrap_ntb(struct gether *port, * walk through NDP * dwSignature */ - tmp = (void *)(skb->data + ndp_index); + tmp = (__le16 *)(ntb_ptr + ndp_index); if (get_unaligned_le32(tmp) != ncm->ndp_sign) { INFO(port->func.config->cdev, "Wrong NDP SIGN\n"); goto err; @@ -1299,11 +1301,11 @@ static int ncm_unwrap_ntb(struct gether *port, if (ncm->is_crc) { uint32_t crc, crc2; - crc = get_unaligned_le32(skb->data + + crc = get_unaligned_le32(ntb_ptr + index + dg_len - crc_len); crc2 = ~crc32_le(~0, - skb->data + index, + ntb_ptr + index, dg_len - crc_len); if (crc != crc2) { INFO(port->func.config->cdev, @@ -1330,7 +1332,7 @@ static int ncm_unwrap_ntb(struct gether *port, dg_len - crc_len); if (skb2 == NULL) goto err; - skb_put_data(skb2, skb->data + index, + skb_put_data(skb2, ntb_ptr + index, dg_len - crc_len); skb_queue_tail(list, skb2); @@ -1343,10 +1345,17 @@ static int ncm_unwrap_ntb(struct gether *port, } while (ndp_len > 2 * (opts->dgram_item_len * 2)); } while (ndp_index); - dev_consume_skb_any(skb); - VDBG(port->func.config->cdev, "Parsed NTB with %d frames\n", dgram_counter); + + to_process -= block_len; + if (to_process != 0) { + ntb_ptr = (unsigned char *)(ntb_ptr + block_len); + goto parse_ntb; + } + + dev_consume_skb_any(skb); + return 0; err: skb_queue_purge(list); @@ -1434,6 +1443,16 @@ static int ncm_bind(struct usb_configuration *c, struct usb_function *f) return -EINVAL; ncm_opts = container_of(f->fi, struct f_ncm_opts, func_inst); + + if (cdev->use_os_string) { + f->os_desc_table = kzalloc(sizeof(*f->os_desc_table), + GFP_KERNEL); + if (!f->os_desc_table) + return -ENOMEM; + f->os_desc_n = 1; + f->os_desc_table[0].os_desc = &ncm_opts->ncm_os_desc; + } + /* * in drivers/usb/gadget/configfs.c:configfs_composite_bind() * configurations are bound in sequence with list_for_each_entry, @@ -1492,6 +1511,10 @@ static int ncm_bind(struct usb_configuration *c, struct usb_function *f) ncm_control_intf.bInterfaceNumber = status; ncm_union_desc.bMasterInterface0 = status; + if (cdev->use_os_string) + f->os_desc_table[0].if_id = + ncm_iad_desc.bFirstInterface; + status = usb_interface_id(c, f); if (status < 0) goto fail; @@ -1571,6 +1594,9 @@ static int ncm_bind(struct usb_configuration *c, struct usb_function *f) return 0; fail: + kfree(f->os_desc_table); + f->os_desc_n = 0; + if (ncm->notify_req) { kfree(ncm->notify_req->buf); usb_ep_free_request(ncm->notify, ncm->notify_req); @@ -1674,20 +1700,38 @@ static void ncm_free_inst(struct usb_function_instance *f) opts = container_of(f, struct f_ncm_opts, func_inst); if (opts->bound) gether_cleanup(netdev_priv(opts->net)); + kfree(opts->ncm_interf_group); kfree(opts); } static struct usb_function_instance *ncm_alloc_inst(void) { struct f_ncm_opts *opts; + struct usb_os_desc *descs[1]; + char *names[1]; + struct config_group *ncm_interf_group; opts = kzalloc(sizeof(*opts), GFP_KERNEL); if (!opts) return ERR_PTR(-ENOMEM); + opts->ncm_os_desc.ext_compat_id = opts->ncm_ext_compat_id; + mutex_init(&opts->lock); opts->func_inst.free_func_inst = ncm_free_inst; + INIT_LIST_HEAD(&opts->ncm_os_desc.ext_prop); + + descs[0] = &opts->ncm_os_desc; + names[0] = "ncm"; config_group_init_type_name(&opts->func_inst.group, "", &ncm_func_type); + ncm_interf_group = + usb_os_desc_prepare_interf_dir(&opts->func_inst.group, 1, descs, + names, THIS_MODULE); + if (IS_ERR(ncm_interf_group)) { + ncm_free_inst(&opts->func_inst); + return ERR_CAST(ncm_interf_group); + } + opts->ncm_interf_group = ncm_interf_group; #ifdef CONFIG_USB_CONFIGFS_UEVENT _ncm_setup_desc = kzalloc(sizeof(*_ncm_setup_desc), GFP_KERNEL); @@ -1725,6 +1769,9 @@ static void ncm_unbind(struct usb_configuration *c, struct usb_function *f) hrtimer_cancel(&ncm->task_timer); + kfree(f->os_desc_table); + f->os_desc_n = 0; + ncm_string_defs[0].id = 0; usb_free_all_descriptors(f); diff --git a/drivers/usb/gadget/function/u_audio.c b/drivers/usb/gadget/function/u_audio.c index 28cd0e8ea95d9c83111befe3d20d18f1fdf0281e..70944f5f7b7f77b8a82320da1c1d69164106fa97 100644 --- a/drivers/usb/gadget/function/u_audio.c +++ b/drivers/usb/gadget/function/u_audio.c @@ -631,7 +631,7 @@ void g_audio_cleanup(struct g_audio *g_audio) uac = g_audio->uac; card = uac->card; if (card) - snd_card_free(card); + snd_card_free_when_closed(card); kfree(uac->p_prm.ureq); kfree(uac->c_prm.ureq); diff --git a/drivers/usb/gadget/function/u_ether.c b/drivers/usb/gadget/function/u_ether.c index 376312a31f5ea8aa5cb265f22bc5b2898fa06b6b..3d71ed861a84b71817696df8cefc173e3e13e7ac 100644 --- a/drivers/usb/gadget/function/u_ether.c +++ b/drivers/usb/gadget/function/u_ether.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include "u_ether.h" @@ -103,41 +105,6 @@ static inline int qlen(struct usb_gadget *gadget, unsigned qmult) /*-------------------------------------------------------------------------*/ -/* REVISIT there must be a better way than having two sets - * of debug calls ... - */ - -#undef DBG -#undef VDBG -#undef ERROR -#undef INFO - -#define xprintk(d, level, fmt, args...) \ - printk(level "%s: " fmt , (d)->net->name , ## args) - -#ifdef DEBUG -#undef DEBUG -#define DBG(dev, fmt, args...) \ - xprintk(dev , KERN_DEBUG , fmt , ## args) -#else -#define DBG(dev, fmt, args...) \ - do { } while (0) -#endif /* DEBUG */ - -#ifdef VERBOSE_DEBUG -#define VDBG DBG -#else -#define VDBG(dev, fmt, args...) \ - do { } while (0) -#endif /* DEBUG */ - -#define ERROR(dev, fmt, args...) \ - xprintk(dev , KERN_ERR , fmt , ## args) -#define INFO(dev, fmt, args...) \ - xprintk(dev , KERN_INFO , fmt , ## args) - -/*-------------------------------------------------------------------------*/ - /* NETWORK DRIVER HOOKUP (to the layer above this driver) */ static void eth_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *p) @@ -979,6 +946,8 @@ int gether_get_host_addr_cdc(struct net_device *net, char *host_addr, int len) dev = netdev_priv(net); snprintf(host_addr, len, "%pm", dev->host_mac); + string_upper(host_addr, host_addr); + return strlen(host_addr); } EXPORT_SYMBOL_GPL(gether_get_host_addr_cdc); diff --git a/drivers/usb/gadget/function/u_ncm.h b/drivers/usb/gadget/function/u_ncm.h index 785bda0a4c7f4f8c12590fd462951cb0e8db7747..c53bed76f3091b6a433549bd1f142e0262717161 100644 --- a/drivers/usb/gadget/function/u_ncm.h +++ b/drivers/usb/gadget/function/u_ncm.h @@ -20,6 +20,9 @@ struct f_ncm_opts { struct net_device *net; bool bound; + struct config_group *ncm_interf_group; + struct usb_os_desc ncm_os_desc; + char ncm_ext_compat_id[16]; /* * Read/write access to configfs attributes is handled by configfs. * diff --git a/drivers/usb/gadget/udc/amd5536udc_pci.c b/drivers/usb/gadget/udc/amd5536udc_pci.c index 362284057d30728ed3047e310bfb68bf977b3fd5..a3d15c3fb82a99078479ea5a010da8baf7e323d3 100644 --- a/drivers/usb/gadget/udc/amd5536udc_pci.c +++ b/drivers/usb/gadget/udc/amd5536udc_pci.c @@ -171,6 +171,9 @@ static int udc_pci_probe( retval = -ENODEV; goto err_probe; } + + udc = dev; + return 0; err_probe: diff --git a/drivers/usb/gadget/udc/fsl_qe_udc.c b/drivers/usb/gadget/udc/fsl_qe_udc.c index 2707be6282988f281e134139ea7e60d181176091..cbd8d6c74c93809cc0d01193f740afab26512a26 100644 --- a/drivers/usb/gadget/udc/fsl_qe_udc.c +++ b/drivers/usb/gadget/udc/fsl_qe_udc.c @@ -1950,9 +1950,13 @@ static void ch9getstatus(struct qe_udc *udc, u8 request_type, u16 value, } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) { /* Get endpoint status */ int pipe = index & USB_ENDPOINT_NUMBER_MASK; - struct qe_ep *target_ep = &udc->eps[pipe]; + struct qe_ep *target_ep; u16 usep; + if (pipe >= USB_MAX_ENDPOINTS) + goto stall; + target_ep = &udc->eps[pipe]; + /* stall if endpoint doesn't exist */ if (!target_ep->ep.desc) goto stall; diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c index c17d7a71e29a3fcb2d4d7a2418fc821ad5cf9134..013db752d55da4af319044300794eed0808156a9 100644 --- a/drivers/usb/gadget/udc/renesas_usb3.c +++ b/drivers/usb/gadget/udc/renesas_usb3.c @@ -2478,6 +2478,7 @@ static int renesas_usb3_remove(struct platform_device *pdev) debugfs_remove_recursive(usb3->dentry); device_remove_file(&pdev->dev, &dev_attr_role); + cancel_work_sync(&usb3->role_work); usb_role_switch_unregister(usb3->role_sw); usb_del_gadget_udc(&usb3->gadget); diff --git a/drivers/usb/gadget/udc/udc-xilinx.c b/drivers/usb/gadget/udc/udc-xilinx.c index 72f1bc6a680e37d7f29431325550f1c3fa29e7ff..5b73a2aecf7ae07fc7d19f9eb548b8db6148e2ca 100644 --- a/drivers/usb/gadget/udc/udc-xilinx.c +++ b/drivers/usb/gadget/udc/udc-xilinx.c @@ -496,11 +496,13 @@ static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req, /* Get the Buffer address and copy the transmit data.*/ eprambase = (u32 __force *)(udc->addr + ep->rambase); if (ep->is_in) { - memcpy(eprambase, bufferptr, bytestosend); + memcpy_toio((void __iomem *)eprambase, bufferptr, + bytestosend); udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF0COUNT_OFFSET, bufferlen); } else { - memcpy(bufferptr, eprambase, bytestosend); + memcpy_toio((void __iomem *)bufferptr, eprambase, + bytestosend); } /* * Enable the buffer for transmission. @@ -514,11 +516,13 @@ static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req, eprambase = (u32 __force *)(udc->addr + ep->rambase + ep->ep_usb.maxpacket); if (ep->is_in) { - memcpy(eprambase, bufferptr, bytestosend); + memcpy_toio((void __iomem *)eprambase, bufferptr, + bytestosend); udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF1COUNT_OFFSET, bufferlen); } else { - memcpy(bufferptr, eprambase, bytestosend); + memcpy_toio((void __iomem *)bufferptr, eprambase, + bytestosend); } /* * Enable the buffer for transmission. @@ -1020,7 +1024,7 @@ static int __xudc_ep0_queue(struct xusb_ep *ep0, struct xusb_req *req) udc->addr); length = req->usb_req.actual = min_t(u32, length, EP0_MAX_PACKET); - memcpy(corebuf, req->usb_req.buf, length); + memcpy_toio((void __iomem *)corebuf, req->usb_req.buf, length); udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, length); udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); } else { @@ -1746,7 +1750,7 @@ static void xudc_handle_setup(struct xusb_udc *udc) /* Load up the chapter 9 command buffer.*/ ep0rambase = (u32 __force *) (udc->addr + XUSB_SETUP_PKT_ADDR_OFFSET); - memcpy(&setup, ep0rambase, 8); + memcpy_toio((void __iomem *)&setup, ep0rambase, 8); udc->setup = setup; udc->setup.wValue = cpu_to_le16(setup.wValue); @@ -1833,7 +1837,7 @@ static void xudc_ep0_out(struct xusb_udc *udc) (ep0->rambase << 2)); buffer = req->usb_req.buf + req->usb_req.actual; req->usb_req.actual = req->usb_req.actual + bytes_to_rx; - memcpy(buffer, ep0rambase, bytes_to_rx); + memcpy_toio((void __iomem *)buffer, ep0rambase, bytes_to_rx); if (req->usb_req.length == req->usb_req.actual) { /* Data transfer completed get ready for Status stage */ @@ -1909,7 +1913,7 @@ static void xudc_ep0_in(struct xusb_udc *udc) (ep0->rambase << 2)); buffer = req->usb_req.buf + req->usb_req.actual; req->usb_req.actual = req->usb_req.actual + length; - memcpy(ep0rambase, buffer, length); + memcpy_toio((void __iomem *)ep0rambase, buffer, length); } udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, count); udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index ec6739ef3129e405f594f4486e739a31f5c657a9..687aeab64e4dbd2f9c9d331675525f542aa589e3 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -642,7 +642,13 @@ ohci_hcd_at91_drv_resume(struct device *dev) at91_start_clock(ohci_at91); - ohci_resume(hcd, false); + /* + * According to the comment in ohci_hcd_at91_drv_suspend() + * we need to do a reset if the 48Mhz clock was stopped, + * that is, if ohci_at91->wakeup is clear. Tell ohci_resume() + * to reset in this case by setting its "hibernated" flag. + */ + ohci_resume(hcd, !ohci_at91->wakeup); ohci_at91_port_suspend(ohci_at91->sfr_regmap, 0); diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c index 3e24749597359108a723410be8e213961916b6aa..7679fb583e4161af1e7f624c841f2609c6865fe6 100644 --- a/drivers/usb/host/ohci-pxa27x.c +++ b/drivers/usb/host/ohci-pxa27x.c @@ -148,7 +148,7 @@ static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode) uhcrhda |= RH_A_NPS; break; case PMM_GLOBAL_MODE: - uhcrhda &= ~(RH_A_NPS & RH_A_PSM); + uhcrhda &= ~(RH_A_NPS | RH_A_PSM); break; case PMM_PERPORT_MODE: uhcrhda &= ~(RH_A_NPS); diff --git a/drivers/usb/host/xhci-debugfs.c b/drivers/usb/host/xhci-debugfs.c index 448d7b11dec4cab8987d4fe2999af8e65e2f3249..608104cdcf33bae99428c34d10167dab4a548e1b 100644 --- a/drivers/usb/host/xhci-debugfs.c +++ b/drivers/usb/host/xhci-debugfs.c @@ -132,6 +132,7 @@ static void xhci_debugfs_regset(struct xhci_hcd *xhci, u32 base, regset->regs = regs; regset->nregs = nregs; regset->base = hcd->regs + base; + regset->dev = hcd->self.controller; debugfs_create_regset32((const char *)rgs->name, 0444, parent, regset); } diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c index f4b2e766f195b981875105407464d4bd12abb6f8..cb22beb55f7e0a45026422e220555b098fbe32d3 100644 --- a/drivers/usb/host/xhci-mtk.c +++ b/drivers/usb/host/xhci-mtk.c @@ -538,6 +538,7 @@ static int xhci_mtk_probe(struct platform_device *pdev) } device_init_wakeup(dev, true); + dma_set_max_seg_size(dev, UINT_MAX); xhci = hcd_to_xhci(hcd); xhci->main_hcd = hcd; diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c index 32e15856878858dc028202d02e1620b10089666d..fc9d6189c310f7bdab0a0cbc050cc8a4911f650f 100644 --- a/drivers/usb/host/xhci-mvebu.c +++ b/drivers/usb/host/xhci-mvebu.c @@ -31,7 +31,7 @@ static void xhci_mvebu_mbus_config(void __iomem *base, /* Program each DRAM CS in a seperate window */ for (win = 0; win < dram->num_cs; win++) { - const struct mbus_dram_window *cs = dram->cs + win; + const struct mbus_dram_window *cs = &dram->cs[win]; writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | (dram->mbus_dram_target_id << 4) | 1, diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c index 4ebbe2c23292678dd66a3991ef3ac07cdeebeb73..4353c1948e5c6f210368cd150fa55731af88b2bb 100644 --- a/drivers/usb/host/xhci-rcar.c +++ b/drivers/usb/host/xhci-rcar.c @@ -74,7 +74,6 @@ MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3); /* For soc_device_attribute */ #define RCAR_XHCI_FIRMWARE_V2 BIT(0) /* FIRMWARE V2 */ -#define RCAR_XHCI_FIRMWARE_V3 BIT(1) /* FIRMWARE V3 */ static const struct soc_device_attribute rcar_quirks_match[] = { { @@ -156,8 +155,6 @@ static int xhci_rcar_download_firmware(struct usb_hcd *hcd) if (quirks & RCAR_XHCI_FIRMWARE_V2) firmware_name = XHCI_RCAR_FIRMWARE_NAME_V2; - else if (quirks & RCAR_XHCI_FIRMWARE_V3) - firmware_name = XHCI_RCAR_FIRMWARE_NAME_V3; else firmware_name = priv->firmware_name; diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 8371e9b9a822cbddd7983c2e7e1bc604e13ec249..46b0d8a304535da463b92f513cf2d58f902562cd 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -689,7 +689,7 @@ static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, struct xhci_ring *ring, struct xhci_td *td) { - struct device *dev = xhci_to_hcd(xhci)->self.controller; + struct device *dev = xhci_to_hcd(xhci)->self.sysdev; struct xhci_segment *seg = td->bounce_seg; struct urb *urb = td->urb; size_t len; @@ -3199,7 +3199,7 @@ static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, u32 *trb_buff_len, struct xhci_segment *seg) { - struct device *dev = xhci_to_hcd(xhci)->self.controller; + struct device *dev = xhci_to_hcd(xhci)->self.sysdev; unsigned int unalign; unsigned int max_pkt; u32 new_buff_len; diff --git a/drivers/usb/misc/sisusbvga/sisusb.c b/drivers/usb/misc/sisusbvga/sisusb.c index 4877bf82ad395dc4038d5f0bdef3d5f7ed5ff1f5..6a68a9f8d57f03505eeeedaafe973b8286171bde 100644 --- a/drivers/usb/misc/sisusbvga/sisusb.c +++ b/drivers/usb/misc/sisusbvga/sisusb.c @@ -3016,6 +3016,20 @@ static int sisusb_probe(struct usb_interface *intf, struct usb_device *dev = interface_to_usbdev(intf); struct sisusb_usb_data *sisusb; int retval = 0, i; + static const u8 ep_addresses[] = { + SISUSB_EP_GFX_IN | USB_DIR_IN, + SISUSB_EP_GFX_OUT | USB_DIR_OUT, + SISUSB_EP_GFX_BULK_OUT | USB_DIR_OUT, + SISUSB_EP_GFX_LBULK_OUT | USB_DIR_OUT, + SISUSB_EP_BRIDGE_IN | USB_DIR_IN, + SISUSB_EP_BRIDGE_OUT | USB_DIR_OUT, + 0}; + + /* Are the expected endpoints present? */ + if (!usb_check_bulk_endpoints(intf, ep_addresses)) { + dev_err(&intf->dev, "Invalid USB2VGA device\n"); + return -EINVAL; + } dev_info(&dev->dev, "USB2VGA dongle found at address %d\n", dev->devnum); diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c index b4d6d9bb32395eec719cee5cbe85e327d438ccae..c545b27ea56819bd255442d4cd400a069333a426 100644 --- a/drivers/usb/musb/cppi_dma.c +++ b/drivers/usb/musb/cppi_dma.c @@ -1146,7 +1146,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id) struct musb_hw_ep *hw_ep = NULL; u32 rx, tx; int i, index; - unsigned long uninitialized_var(flags); + unsigned long flags; cppi = container_of(musb->dma_controller, struct cppi, controller); if (cppi->irq) diff --git a/drivers/usb/musb/musb_debugfs.c b/drivers/usb/musb/musb_debugfs.c index 0c6204add616167a2be0e139823c0c82aa2b6a59..1efd5ce48f893ce4843394251afaa89812fda133 100644 --- a/drivers/usb/musb/musb_debugfs.c +++ b/drivers/usb/musb/musb_debugfs.c @@ -39,7 +39,7 @@ static const struct musb_register_map musb_regmap[] = { { "IntrUsbE", MUSB_INTRUSBE, 8 }, { "DevCtl", MUSB_DEVCTL, 8 }, { "VControl", 0x68, 32 }, - { "HWVers", 0x69, 16 }, + { "HWVers", MUSB_HWVERS, 16 }, { "LinkInfo", MUSB_LINKINFO, 8 }, { "VPLen", MUSB_VPLEN, 8 }, { "HS_EOF1", MUSB_HS_EOF1, 8 }, diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c index a1c4fc56d429dbeb5bbe4f0d48afda92b250f244..1e50efc5869c1a1d9c4c14acbe5a2e2886879871 100644 --- a/drivers/usb/musb/musb_host.c +++ b/drivers/usb/musb/musb_host.c @@ -321,10 +321,16 @@ static void musb_advance_schedule(struct musb *musb, struct urb *urb, musb_giveback(musb, urb, status); qh->is_ready = ready; + /* + * musb->lock had been unlocked in musb_giveback, so qh may + * be freed, need to get it again + */ + qh = musb_ep_get_qh(hw_ep, is_in); + /* reclaim resources (and bandwidth) ASAP; deschedule it, and * invalidate qh as soon as list_empty(&hep->urb_list) */ - if (list_empty(&qh->hep->urb_list)) { + if (qh && list_empty(&qh->hep->urb_list)) { struct list_head *head; struct dma_controller *dma = musb->dma_controller; @@ -2398,6 +2404,7 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) * and its URB list has emptied, recycle this qh. */ if (ready && list_empty(&qh->hep->urb_list)) { + musb_ep_set_qh(qh->hw_ep, is_in, NULL); qh->hep->hcpriv = NULL; list_del(&qh->ring); kfree(qh); diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c index e5aa24c1e4fd7341f609e32ff48ce16f757cc4d4..8af2ee3713b6ddea00e75809f43310bf8282792c 100644 --- a/drivers/usb/phy/phy-mxs-usb.c +++ b/drivers/usb/phy/phy-mxs-usb.c @@ -312,14 +312,8 @@ static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect) static bool mxs_phy_is_otg_host(struct mxs_phy *mxs_phy) { - void __iomem *base = mxs_phy->phy.io_priv; - u32 phyctrl = readl(base + HW_USBPHY_CTRL); - - if (IS_ENABLED(CONFIG_USB_OTG) && - !(phyctrl & BM_USBPHY_CTRL_OTG_ID_VALUE)) - return true; - - return false; + return IS_ENABLED(CONFIG_USB_OTG) && + mxs_phy->phy.last_event == USB_EVENT_ID; } static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on) diff --git a/drivers/usb/phy/phy-tahvo.c b/drivers/usb/phy/phy-tahvo.c index 60d390e28289fd03c26b123788b3677eac492d66..2923a7f6952dc5baf19d462790d0469159c6b5d6 100644 --- a/drivers/usb/phy/phy-tahvo.c +++ b/drivers/usb/phy/phy-tahvo.c @@ -398,7 +398,7 @@ static int tahvo_usb_probe(struct platform_device *pdev) tu->irq = ret = platform_get_irq(pdev, 0); if (ret < 0) - return ret; + goto err_remove_phy; ret = request_threaded_irq(tu->irq, NULL, tahvo_usb_vbus_interrupt, IRQF_ONESHOT, "tahvo-vbus", tu); diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c index 7932a65324d2fa68ac433094bdf08195dfd7bbf3..c203b2e7b83864369d880a246dcb1f9dbe879efb 100644 --- a/drivers/usb/serial/cp210x.c +++ b/drivers/usb/serial/cp210x.c @@ -121,6 +121,7 @@ static const struct usb_device_id id_table[] = { { USB_DEVICE(0x10C4, 0x826B) }, /* Cygnal Integrated Products, Inc., Fasttrax GPS demonstration module */ { USB_DEVICE(0x10C4, 0x8281) }, /* Nanotec Plug & Drive */ { USB_DEVICE(0x10C4, 0x8293) }, /* Telegesis ETRX2USB */ + { USB_DEVICE(0x10C4, 0x82AA) }, /* Silicon Labs IFS-USB-DATACABLE used with Quint UPS */ { USB_DEVICE(0x10C4, 0x82EF) }, /* CESINEL FALCO 6105 AC Power Supply */ { USB_DEVICE(0x10C4, 0x82F1) }, /* CESINEL MEDCAL EFD Earth Fault Detector */ { USB_DEVICE(0x10C4, 0x82F2) }, /* CESINEL MEDCAL ST Network Analyzer */ diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index 17cfa0fd6175b197dbd63a3a196a0a2ff3736a97..7fab049e790ff04ca43b7eb3b309e96a3899e4cf 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -203,6 +203,9 @@ static void option_instat_callback(struct urb *urb); #define DELL_PRODUCT_5829E_ESIM 0x81e4 #define DELL_PRODUCT_5829E 0x81e6 +#define DELL_PRODUCT_FM101R 0x8213 +#define DELL_PRODUCT_FM101R_ESIM 0x8215 + #define KYOCERA_VENDOR_ID 0x0c88 #define KYOCERA_PRODUCT_KPC650 0x17da #define KYOCERA_PRODUCT_KPC680 0x180a @@ -248,7 +251,10 @@ static void option_instat_callback(struct urb *urb); #define QUECTEL_VENDOR_ID 0x2c7c /* These Quectel products use Quectel's vendor ID */ #define QUECTEL_PRODUCT_EC21 0x0121 +#define QUECTEL_PRODUCT_EM061K_LTA 0x0123 +#define QUECTEL_PRODUCT_EM061K_LMS 0x0124 #define QUECTEL_PRODUCT_EC25 0x0125 +#define QUECTEL_PRODUCT_EM060K_128 0x0128 #define QUECTEL_PRODUCT_EG91 0x0191 #define QUECTEL_PRODUCT_EG95 0x0195 #define QUECTEL_PRODUCT_BG96 0x0296 @@ -256,6 +262,7 @@ static void option_instat_callback(struct urb *urb); #define QUECTEL_PRODUCT_EM05G 0x030a #define QUECTEL_PRODUCT_EM060K 0x030b #define QUECTEL_PRODUCT_EM05G_CS 0x030c +#define QUECTEL_PRODUCT_EM05GV2 0x030e #define QUECTEL_PRODUCT_EM05CN_SG 0x0310 #define QUECTEL_PRODUCT_EM05G_SG 0x0311 #define QUECTEL_PRODUCT_EM05CN 0x0312 @@ -266,6 +273,9 @@ static void option_instat_callback(struct urb *urb); #define QUECTEL_PRODUCT_RM520N 0x0801 #define QUECTEL_PRODUCT_EC200U 0x0901 #define QUECTEL_PRODUCT_EC200S_CN 0x6002 +#define QUECTEL_PRODUCT_EC200A 0x6005 +#define QUECTEL_PRODUCT_EM061K_LWW 0x6008 +#define QUECTEL_PRODUCT_EM061K_LCN 0x6009 #define QUECTEL_PRODUCT_EC200T 0x6026 #define QUECTEL_PRODUCT_RM500K 0x7001 @@ -595,6 +605,11 @@ static void option_instat_callback(struct urb *urb); #define SIERRA_VENDOR_ID 0x1199 #define SIERRA_PRODUCT_EM9191 0x90d3 +/* UNISOC (Spreadtrum) products */ +#define UNISOC_VENDOR_ID 0x1782 +/* TOZED LT70-C based on UNISOC SL8563 uses UNISOC's vendor ID */ +#define TOZED_PRODUCT_LT70C 0x4055 + /* Device flags */ /* Highest interface number which can be used with NCTRL() and RSVD() */ @@ -1096,6 +1111,8 @@ static const struct usb_device_id option_ids[] = { .driver_info = RSVD(0) | RSVD(6) }, { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5829E_ESIM), .driver_info = RSVD(0) | RSVD(6) }, + { USB_DEVICE_INTERFACE_CLASS(DELL_VENDOR_ID, DELL_PRODUCT_FM101R, 0xff) }, + { USB_DEVICE_INTERFACE_CLASS(DELL_VENDOR_ID, DELL_PRODUCT_FM101R_ESIM, 0xff) }, { USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_E100A) }, /* ADU-E100, ADU-310 */ { USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_500A) }, { USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_620UW) }, @@ -1142,6 +1159,10 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x90fa), .driver_info = RSVD(3) }, /* u-blox products */ + { USB_DEVICE(UBLOX_VENDOR_ID, 0x1311) }, /* u-blox LARA-R6 01B */ + { USB_DEVICE(UBLOX_VENDOR_ID, 0x1312), /* u-blox LARA-R6 01B (RMNET) */ + .driver_info = RSVD(4) }, + { USB_DEVICE_INTERFACE_CLASS(UBLOX_VENDOR_ID, 0x1313, 0xff) }, /* u-blox LARA-R6 01B (ECM) */ { USB_DEVICE(UBLOX_VENDOR_ID, 0x1341) }, /* u-blox LARA-L6 */ { USB_DEVICE(UBLOX_VENDOR_ID, 0x1342), /* u-blox LARA-L6 (RMNET) */ .driver_info = RSVD(4) }, @@ -1175,6 +1196,8 @@ static const struct usb_device_id option_ids[] = { .driver_info = RSVD(6) | ZLP }, { USB_DEVICE_INTERFACE_CLASS(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM05G_GR, 0xff), .driver_info = RSVD(6) | ZLP }, + { USB_DEVICE_INTERFACE_CLASS(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM05GV2, 0xff), + .driver_info = RSVD(4) | ZLP }, { USB_DEVICE_INTERFACE_CLASS(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM05G_CS, 0xff), .driver_info = RSVD(6) | ZLP }, { USB_DEVICE_INTERFACE_CLASS(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM05G_RS, 0xff), @@ -1184,6 +1207,21 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K, 0xff, 0x00, 0x40) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K, 0xff, 0xff, 0x30) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K, 0xff, 0xff, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K_128, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K_128, 0xff, 0x00, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K_128, 0xff, 0xff, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LCN, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LCN, 0xff, 0x00, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LCN, 0xff, 0xff, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LMS, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LMS, 0xff, 0x00, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LMS, 0xff, 0xff, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LTA, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LTA, 0xff, 0x00, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LTA, 0xff, 0xff, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LWW, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LWW, 0xff, 0x00, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LWW, 0xff, 0xff, 0x40) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM12, 0xff, 0xff, 0xff), .driver_info = RSVD(1) | RSVD(2) | RSVD(3) | RSVD(4) | NUMEP2 }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM12, 0xff, 0, 0) }, @@ -1198,6 +1236,9 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM520N, 0xff, 0xff, 0x30) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM520N, 0xff, 0, 0x40) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM520N, 0xff, 0, 0) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, 0x0900, 0xff, 0, 0), /* RM500U-CN */ + .driver_info = ZLP }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200A, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200U, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200S_CN, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200T, 0xff, 0, 0) }, @@ -1254,6 +1295,7 @@ static const struct usb_device_id option_ids[] = { .driver_info = NCTRL(0) | RSVD(3) }, { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1033, 0xff), /* Telit LE910C1-EUX (ECM) */ .driver_info = NCTRL(0) }, + { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1035, 0xff) }, /* Telit LE910C4-WWX (ECM) */ { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE922_USBCFG0), .driver_info = RSVD(0) | RSVD(1) | NCTRL(2) | RSVD(3) }, { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE922_USBCFG1), @@ -1300,6 +1342,14 @@ static const struct usb_device_id option_ids[] = { .driver_info = NCTRL(0) | RSVD(1) }, { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1075, 0xff), /* Telit FN990 (PCIe) */ .driver_info = RSVD(0) }, + { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1080, 0xff), /* Telit FE990 (rmnet) */ + .driver_info = NCTRL(0) | RSVD(1) | RSVD(2) }, + { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1081, 0xff), /* Telit FE990 (MBIM) */ + .driver_info = NCTRL(0) | RSVD(1) }, + { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1082, 0xff), /* Telit FE990 (RNDIS) */ + .driver_info = NCTRL(2) | RSVD(3) }, + { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1083, 0xff), /* Telit FE990 (ECM) */ + .driver_info = NCTRL(0) | RSVD(1) }, { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_ME910), .driver_info = NCTRL(0) | RSVD(1) | RSVD(3) }, { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_ME910_DUAL_MODEM), @@ -2191,6 +2241,10 @@ static const struct usb_device_id option_ids[] = { .driver_info = RSVD(0) | RSVD(1) | RSVD(6) }, { USB_DEVICE_INTERFACE_CLASS(0x0489, 0xe0db, 0xff), /* Foxconn T99W265 MBIM */ .driver_info = RSVD(3) }, + { USB_DEVICE_INTERFACE_CLASS(0x0489, 0xe0ee, 0xff), /* Foxconn T99W368 MBIM */ + .driver_info = RSVD(3) }, + { USB_DEVICE_INTERFACE_CLASS(0x0489, 0xe0f0, 0xff), /* Foxconn T99W373 MBIM */ + .driver_info = RSVD(3) }, { USB_DEVICE(0x1508, 0x1001), /* Fibocom NL668 (IOT version) */ .driver_info = RSVD(4) | RSVD(5) | RSVD(6) }, { USB_DEVICE(0x1782, 0x4d10) }, /* Fibocom L610 (AT mode) */ @@ -2214,7 +2268,9 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1406, 0xff) }, /* GosunCn GM500 ECM/NCM */ { USB_DEVICE_AND_INTERFACE_INFO(OPPO_VENDOR_ID, OPPO_PRODUCT_R11, 0xff, 0xff, 0x30) }, { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0xff, 0x40) }, { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0, 0) }, + { USB_DEVICE_AND_INTERFACE_INFO(UNISOC_VENDOR_ID, TOZED_PRODUCT_LT70C, 0xff, 0, 0) }, { } /* Terminating entry */ }; MODULE_DEVICE_TABLE(usb, option_ids); diff --git a/drivers/usb/serial/usb-serial-simple.c b/drivers/usb/serial/usb-serial-simple.c index 4c6747889a194664a04f90824e417bedec625b3f..24b8772a345e2f898dcc345b9f01582b1a87e76a 100644 --- a/drivers/usb/serial/usb-serial-simple.c +++ b/drivers/usb/serial/usb-serial-simple.c @@ -38,16 +38,6 @@ static struct usb_serial_driver vendor##_device = { \ { USB_DEVICE(0x0a21, 0x8001) } /* MMT-7305WW */ DEVICE(carelink, CARELINK_IDS); -/* ZIO Motherboard USB driver */ -#define ZIO_IDS() \ - { USB_DEVICE(0x1CBE, 0x0103) } -DEVICE(zio, ZIO_IDS); - -/* Funsoft Serial USB driver */ -#define FUNSOFT_IDS() \ - { USB_DEVICE(0x1404, 0xcddc) } -DEVICE(funsoft, FUNSOFT_IDS); - /* Infineon Flashloader driver */ #define FLASHLOADER_IDS() \ { USB_DEVICE_INTERFACE_CLASS(0x058b, 0x0041, USB_CLASS_CDC_DATA) }, \ @@ -55,6 +45,11 @@ DEVICE(funsoft, FUNSOFT_IDS); { USB_DEVICE(0x8087, 0x0801) } DEVICE(flashloader, FLASHLOADER_IDS); +/* Funsoft Serial USB driver */ +#define FUNSOFT_IDS() \ + { USB_DEVICE(0x1404, 0xcddc) } +DEVICE(funsoft, FUNSOFT_IDS); + /* Google Serial USB SubClass */ #define GOOGLE_IDS() \ { USB_VENDOR_AND_INTERFACE_INFO(0x18d1, \ @@ -63,16 +58,21 @@ DEVICE(flashloader, FLASHLOADER_IDS); 0x01) } DEVICE(google, GOOGLE_IDS); +/* HP4x (48/49) Generic Serial driver */ +#define HP4X_IDS() \ + { USB_DEVICE(0x03f0, 0x0121) } +DEVICE(hp4x, HP4X_IDS); + +/* KAUFMANN RKS+CAN VCP */ +#define KAUFMANN_IDS() \ + { USB_DEVICE(0x16d0, 0x0870) } +DEVICE(kaufmann, KAUFMANN_IDS); + /* Libtransistor USB console */ #define LIBTRANSISTOR_IDS() \ { USB_DEVICE(0x1209, 0x8b00) } DEVICE(libtransistor, LIBTRANSISTOR_IDS); -/* ViVOpay USB Serial Driver */ -#define VIVOPAY_IDS() \ - { USB_DEVICE(0x1d5f, 0x1004) } /* ViVOpay 8800 */ -DEVICE(vivopay, VIVOPAY_IDS); - /* Motorola USB Phone driver */ #define MOTO_IDS() \ { USB_DEVICE(0x05c6, 0x3197) }, /* unknown Motorola phone */ \ @@ -101,10 +101,10 @@ DEVICE(nokia, NOKIA_IDS); { USB_DEVICE(0x09d7, 0x0100) } /* NovAtel FlexPack GPS */ DEVICE_N(novatel_gps, NOVATEL_IDS, 3); -/* HP4x (48/49) Generic Serial driver */ -#define HP4X_IDS() \ - { USB_DEVICE(0x03f0, 0x0121) } -DEVICE(hp4x, HP4X_IDS); +/* Siemens USB/MPI adapter */ +#define SIEMENS_IDS() \ + { USB_DEVICE(0x908, 0x0004) } +DEVICE(siemens_mpi, SIEMENS_IDS); /* Suunto ANT+ USB Driver */ #define SUUNTO_IDS() \ @@ -112,45 +112,52 @@ DEVICE(hp4x, HP4X_IDS); { USB_DEVICE(0x0fcf, 0x1009) } /* Dynastream ANT USB-m Stick */ DEVICE(suunto, SUUNTO_IDS); -/* Siemens USB/MPI adapter */ -#define SIEMENS_IDS() \ - { USB_DEVICE(0x908, 0x0004) } -DEVICE(siemens_mpi, SIEMENS_IDS); +/* ViVOpay USB Serial Driver */ +#define VIVOPAY_IDS() \ + { USB_DEVICE(0x1d5f, 0x1004) } /* ViVOpay 8800 */ +DEVICE(vivopay, VIVOPAY_IDS); + +/* ZIO Motherboard USB driver */ +#define ZIO_IDS() \ + { USB_DEVICE(0x1CBE, 0x0103) } +DEVICE(zio, ZIO_IDS); /* All of the above structures mushed into two lists */ static struct usb_serial_driver * const serial_drivers[] = { &carelink_device, - &zio_device, - &funsoft_device, &flashloader_device, + &funsoft_device, &google_device, + &hp4x_device, + &kaufmann_device, &libtransistor_device, - &vivopay_device, &moto_modem_device, &motorola_tetra_device, &nokia_device, &novatel_gps_device, - &hp4x_device, - &suunto_device, &siemens_mpi_device, + &suunto_device, + &vivopay_device, + &zio_device, NULL }; static const struct usb_device_id id_table[] = { CARELINK_IDS(), - ZIO_IDS(), - FUNSOFT_IDS(), FLASHLOADER_IDS(), + FUNSOFT_IDS(), GOOGLE_IDS(), + HP4X_IDS(), + KAUFMANN_IDS(), LIBTRANSISTOR_IDS(), - VIVOPAY_IDS(), MOTO_IDS(), MOTOROLA_TETRA_IDS(), NOKIA_IDS(), NOVATEL_IDS(), - HP4X_IDS(), - SUUNTO_IDS(), SIEMENS_IDS(), + SUUNTO_IDS(), + VIVOPAY_IDS(), + ZIO_IDS(), { }, }; MODULE_DEVICE_TABLE(usb, id_table); diff --git a/drivers/usb/storage/alauda.c b/drivers/usb/storage/alauda.c index 6fcf5fd2ff98782c11ac56a320d3aae9b34b6406..50c8bd7cbfddb5db960c8a94a1bf5a67458cfc74 100644 --- a/drivers/usb/storage/alauda.c +++ b/drivers/usb/storage/alauda.c @@ -317,7 +317,8 @@ static int alauda_get_media_status(struct us_data *us, unsigned char *data) rc = usb_stor_ctrl_transfer(us, us->recv_ctrl_pipe, command, 0xc0, 0, 1, data, 2); - usb_stor_dbg(us, "Media status %02X %02X\n", data[0], data[1]); + if (rc == USB_STOR_XFER_GOOD) + usb_stor_dbg(us, "Media status %02X %02X\n", data[0], data[1]); return rc; } @@ -453,10 +454,14 @@ static int alauda_init_media(struct us_data *us) static int alauda_check_media(struct us_data *us) { struct alauda_info *info = (struct alauda_info *) us->extra; - unsigned char status[2]; + unsigned char *status = us->iobuf; int rc; rc = alauda_get_media_status(us, status); + if (rc != USB_STOR_XFER_GOOD) { + status[0] = 0xF0; /* Pretend there's no media */ + status[1] = 0; + } /* Check for no media or door open */ if ((status[0] & 0x80) || ((status[0] & 0x1F) == 0x10) diff --git a/drivers/usb/storage/ene_ub6250.c b/drivers/usb/storage/ene_ub6250.c index 54679679c825dc438536900b4da34c07263ab50d..16b63f2cd661eb871c739c69786b0a27135f5c26 100644 --- a/drivers/usb/storage/ene_ub6250.c +++ b/drivers/usb/storage/ene_ub6250.c @@ -937,7 +937,7 @@ static int ms_lib_process_bootblock(struct us_data *us, u16 PhyBlock, u8 *PageDa struct ms_lib_type_extdat ExtraData; struct ene_ub6250_info *info = (struct ene_ub6250_info *) us->extra; - PageBuffer = kmalloc(MS_BYTES_PER_PAGE, GFP_KERNEL); + PageBuffer = kzalloc(MS_BYTES_PER_PAGE * 2, GFP_KERNEL); if (PageBuffer == NULL) return (u32)-1; diff --git a/drivers/usb/storage/scsiglue.c b/drivers/usb/storage/scsiglue.c index 995dd1ed81ce82ab893f161dbf6010f7c11f45f0..02c152211612ac534b04132b9e3777fdf6c59184 100644 --- a/drivers/usb/storage/scsiglue.c +++ b/drivers/usb/storage/scsiglue.c @@ -399,22 +399,25 @@ static DEF_SCSI_QCMD(queuecommand) ***********************************************************************/ /* Command timeout and abort */ -static int command_abort(struct scsi_cmnd *srb) +static int command_abort_matching(struct us_data *us, struct scsi_cmnd *srb_match) { - struct us_data *us = host_to_us(srb->device->host); - - usb_stor_dbg(us, "%s called\n", __func__); - /* * us->srb together with the TIMED_OUT, RESETTING, and ABORTING * bits are protected by the host lock. */ scsi_lock(us_to_host(us)); - /* Is this command still active? */ - if (us->srb != srb) { + /* is there any active pending command to abort ? */ + if (!us->srb) { scsi_unlock(us_to_host(us)); usb_stor_dbg(us, "-- nothing to abort\n"); + return SUCCESS; + } + + /* Does the command match the passed srb if any ? */ + if (srb_match && us->srb != srb_match) { + scsi_unlock(us_to_host(us)); + usb_stor_dbg(us, "-- pending command mismatch\n"); return FAILED; } @@ -437,6 +440,14 @@ static int command_abort(struct scsi_cmnd *srb) return SUCCESS; } +static int command_abort(struct scsi_cmnd *srb) +{ + struct us_data *us = host_to_us(srb->device->host); + + usb_stor_dbg(us, "%s called\n", __func__); + return command_abort_matching(us, srb); +} + /* * This invokes the transport reset mechanism to reset the state of the * device @@ -448,6 +459,9 @@ static int device_reset(struct scsi_cmnd *srb) usb_stor_dbg(us, "%s called\n", __func__); + /* abort any pending command before reset */ + command_abort_matching(us, NULL); + /* lock the device pointers and do the reset */ mutex_lock(&(us->dev_mutex)); result = us->transport_reset(us); diff --git a/drivers/usb/storage/sddr55.c b/drivers/usb/storage/sddr55.c index b8527c55335b6e3a977995fa41cc8d7a3337b219..35306c05596222f72870d4b1372a134ba02b1c2e 100644 --- a/drivers/usb/storage/sddr55.c +++ b/drivers/usb/storage/sddr55.c @@ -553,8 +553,8 @@ static int sddr55_reset(struct us_data *us) static unsigned long sddr55_get_capacity(struct us_data *us) { - unsigned char uninitialized_var(manufacturerID); - unsigned char uninitialized_var(deviceID); + unsigned char manufacturerID; + unsigned char deviceID; int result; struct sddr55_card_info *info = (struct sddr55_card_info *)us->extra; diff --git a/drivers/usb/storage/unusual_cypress.h b/drivers/usb/storage/unusual_cypress.h index fb99e526cd48e21eb11313da43fc4d9858cf8449..7f7534098d533cbd9fe9f16bb6a0b181df48a15e 100644 --- a/drivers/usb/storage/unusual_cypress.h +++ b/drivers/usb/storage/unusual_cypress.h @@ -19,7 +19,7 @@ UNUSUAL_DEV( 0x04b4, 0x6831, 0x0000, 0x9999, "Cypress ISD-300LP", USB_SC_CYP_ATACB, USB_PR_DEVICE, NULL, 0), -UNUSUAL_DEV( 0x14cd, 0x6116, 0x0160, 0x0160, +UNUSUAL_DEV( 0x14cd, 0x6116, 0x0150, 0x0160, "Super Top", "USB 2.0 SATA BRIDGE", USB_SC_CYP_ATACB, USB_PR_DEVICE, NULL, 0), diff --git a/drivers/usb/storage/unusual_uas.h b/drivers/usb/storage/unusual_uas.h index d4fa29b623ff949fa71c3c6aee2e8b9d632f17bc..a4513dd931b27c1eeb611e00d10ec1cd21176fef 100644 --- a/drivers/usb/storage/unusual_uas.h +++ b/drivers/usb/storage/unusual_uas.h @@ -111,6 +111,13 @@ UNUSUAL_DEV(0x152d, 0x0578, 0x0000, 0x9999, USB_SC_DEVICE, USB_PR_DEVICE, NULL, US_FL_BROKEN_FUA), +/* Reported by: Yaroslav Furman */ +UNUSUAL_DEV(0x152d, 0x0583, 0x0000, 0x9999, + "JMicron", + "JMS583Gen 2", + USB_SC_DEVICE, USB_PR_DEVICE, NULL, + US_FL_NO_REPORT_OPCODES), + /* Reported-by: Thinh Nguyen */ UNUSUAL_DEV(0x154b, 0xf00b, 0x0000, 0x9999, "PNY", diff --git a/drivers/usb/typec/altmodes/displayport.c b/drivers/usb/typec/altmodes/displayport.c index 7387f52cb58d1d496dc6c5a96adfc6709ace855a..bc09de5ea17d25f899ccc8f25c488410103d623b 100644 --- a/drivers/usb/typec/altmodes/displayport.c +++ b/drivers/usb/typec/altmodes/displayport.c @@ -501,6 +501,10 @@ static ssize_t pin_assignment_show(struct device *dev, mutex_unlock(&dp->lock); + /* get_current_pin_assignments can return 0 when no matching pin assignments are found */ + if (len == 0) + len++; + buf[len - 1] = '\n'; return len; } diff --git a/drivers/usb/typec/tcpci.c b/drivers/usb/typec/tcpci.c index 9f98376d9bef4c1f0b0a4bff4880d1911420cde0..d1393371b6b0a7a7f249d9198323f91056cb2867 100644 --- a/drivers/usb/typec/tcpci.c +++ b/drivers/usb/typec/tcpci.c @@ -379,6 +379,10 @@ static int tcpci_init(struct tcpc_dev *tcpc) if (time_after(jiffies, timeout)) return -ETIMEDOUT; + ret = tcpci_write16(tcpci, TCPC_FAULT_STATUS, TCPC_FAULT_STATUS_ALL_REG_RST_TO_DEFAULT); + if (ret < 0) + return ret; + /* Handle vendor init */ if (tcpci->data->init) { ret = tcpci->data->init(tcpci, tcpci->data); diff --git a/drivers/usb/typec/tcpci.h b/drivers/usb/typec/tcpci.h index 303ebde265465c05a82221886bf15c79df7b81c4..dcf60399f161f21949cfaa826ad45ff1632ba7c3 100644 --- a/drivers/usb/typec/tcpci.h +++ b/drivers/usb/typec/tcpci.h @@ -72,6 +72,7 @@ #define TCPC_POWER_STATUS_VBUS_PRES BIT(2) #define TCPC_FAULT_STATUS 0x1f +#define TCPC_FAULT_STATUS_ALL_REG_RST_TO_DEFAULT BIT(7) #define TCPC_COMMAND 0x23 #define TCPC_CMD_WAKE_I2C 0x11 diff --git a/drivers/usb/typec/tcpm.c b/drivers/usb/typec/tcpm.c index e4308f97d97391aace49635182bf813d456e9456..0fdae44c9b8cfc3c6b6b38febb5ad7d952b7248f 100644 --- a/drivers/usb/typec/tcpm.c +++ b/drivers/usb/typec/tcpm.c @@ -1006,7 +1006,21 @@ static bool svdm_consume_svids(struct tcpm_port *port, const __le32 *payload, pmdata->svids[pmdata->nsvids++] = svid; tcpm_log(port, "SVID %d: 0x%x", pmdata->nsvids, svid); } - return true; + + /* + * PD3.0 Spec 6.4.4.3.2: The SVIDs are returned 2 per VDO (see Table + * 6-43), and can be returned maximum 6 VDOs per response (see Figure + * 6-19). If the Respondersupports 12 or more SVID then the Discover + * SVIDs Command Shall be executed multiple times until a Discover + * SVIDs VDO is returned ending either with a SVID value of 0x0000 in + * the last part of the last VDO or with a VDO containing two SVIDs + * with values of 0x0000. + * + * However, some odd dockers support SVIDs less than 12 but without + * 0x0000 in the last VDO, so we need to break the Discover SVIDs + * request and return false here. + */ + return cnt == 7; abort: tcpm_log(port, "SVID_DISCOVERY_MAX(%d) too low!", SVID_DISCOVERY_MAX); return false; diff --git a/drivers/usb/usbip/stub_dev.c b/drivers/usb/usbip/stub_dev.c index c64964c32cc97b90b4d8736a1180b44f47644fd6..ebcb8d52d1e3abe07dbbfe8d828a44734614324b 100644 --- a/drivers/usb/usbip/stub_dev.c +++ b/drivers/usb/usbip/stub_dev.c @@ -497,8 +497,13 @@ static void stub_disconnect(struct usb_device *udev) /* release port */ rc = usb_hub_release_port(udev->parent, udev->portnum, (struct usb_dev_state *) udev); - if (rc) { - dev_dbg(&udev->dev, "unable to release port\n"); + /* + * NOTE: If a HUB disconnect triggered disconnect of the down stream + * device usb_hub_release_port will return -ENODEV so we can safely ignore + * that error here. + */ + if (rc && (rc != -ENODEV)) { + dev_dbg(&udev->dev, "unable to release port (%i)\n", rc); return; } diff --git a/drivers/vhost/net.c b/drivers/vhost/net.c index 5ea7b0a94fe383ef72ba882d74b9a2024b238709..4dc1842e3e8e1099d7842602cef1886061ffebbb 100644 --- a/drivers/vhost/net.c +++ b/drivers/vhost/net.c @@ -828,7 +828,7 @@ static int get_rx_bufs(struct vhost_virtqueue *vq, /* len is always initialized before use since we are always called with * datalen > 0. */ - u32 uninitialized_var(len); + u32 len; while (datalen > 0 && headcount < quota) { if (unlikely(seg >= UIO_MAXIOV)) { @@ -885,7 +885,7 @@ static void handle_rx(struct vhost_net *net) { struct vhost_net_virtqueue *nvq = &net->vqs[VHOST_NET_VQ_RX]; struct vhost_virtqueue *vq = &nvq->vq; - unsigned uninitialized_var(in), log; + unsigned in, log; struct vhost_log *vq_log; struct msghdr msg = { .msg_name = NULL, diff --git a/drivers/video/backlight/bd6107.c b/drivers/video/backlight/bd6107.c index fdb2f7e2c6b5d45586bdfe0d620d142b75eb0ea5..3eaa250f10de28e8c4189df80612489a050a3c9c 100644 --- a/drivers/video/backlight/bd6107.c +++ b/drivers/video/backlight/bd6107.c @@ -110,7 +110,7 @@ static int bd6107_backlight_check_fb(struct backlight_device *backlight, { struct bd6107 *bd = bl_get_data(backlight); - return bd->pdata->fbdev == NULL || bd->pdata->fbdev == info->dev; + return bd->pdata->fbdev == NULL || bd->pdata->fbdev == info->device; } static const struct backlight_ops bd6107_backlight_ops = { diff --git a/drivers/video/backlight/gpio_backlight.c b/drivers/video/backlight/gpio_backlight.c index 51c49f03ed835735306bb22f6dc152ab80d7eb06..c2b8b6bf4fcb283d0b0ba4a01f4f6e875f2a9282 100644 --- a/drivers/video/backlight/gpio_backlight.c +++ b/drivers/video/backlight/gpio_backlight.c @@ -48,7 +48,7 @@ static int gpio_backlight_check_fb(struct backlight_device *bl, { struct gpio_backlight *gbl = bl_get_data(bl); - return gbl->fbdev == NULL || gbl->fbdev == info->dev; + return gbl->fbdev == NULL || gbl->fbdev == info->device; } static const struct backlight_ops gpio_backlight_ops = { diff --git a/drivers/video/backlight/lv5207lp.c b/drivers/video/backlight/lv5207lp.c index 8ab7297b118ae2fced4620a43519db2bec4d89f6..08aa615cb2a9709a611681960a07a0b6f611df7a 100644 --- a/drivers/video/backlight/lv5207lp.c +++ b/drivers/video/backlight/lv5207lp.c @@ -75,7 +75,7 @@ static int lv5207lp_backlight_check_fb(struct backlight_device *backlight, { struct lv5207lp *lv = bl_get_data(backlight); - return lv->pdata->fbdev == NULL || lv->pdata->fbdev == info->dev; + return lv->pdata->fbdev == NULL || lv->pdata->fbdev == info->device; } static const struct backlight_ops lv5207lp_backlight_ops = { diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig index 06ecf8e52c25e179845b42a3aab89178d36bb219..9ccb6da2778307e9c0e009669b9110241af3eb1f 100644 --- a/drivers/video/fbdev/Kconfig +++ b/drivers/video/fbdev/Kconfig @@ -2085,7 +2085,7 @@ config FB_COBALT config FB_SH7760 bool "SH7760/SH7763/SH7720/SH7721 LCDC support" - depends on FB && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \ + depends on FB=y && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \ || CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721) select FB_CFB_FILLRECT select FB_CFB_COPYAREA diff --git a/drivers/video/fbdev/aty/atyfb_base.c b/drivers/video/fbdev/aty/atyfb_base.c index 05111e90f1681c0e40a8438c5eb427ff25f9ffc3..5ef008e9c61c3e46b0689cbccd8e192bce15a822 100644 --- a/drivers/video/fbdev/aty/atyfb_base.c +++ b/drivers/video/fbdev/aty/atyfb_base.c @@ -3435,11 +3435,15 @@ static int atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, } info->fix.mmio_start = raddr; +#if defined(__i386__) || defined(__ia64__) /* * By using strong UC we force the MTRR to never have an * effect on the MMIO region on both non-PAT and PAT systems. */ par->ati_regbase = ioremap_uc(info->fix.mmio_start, 0x1000); +#else + par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000); +#endif if (par->ati_regbase == NULL) return -ENOMEM; diff --git a/drivers/video/fbdev/au1200fb.c b/drivers/video/fbdev/au1200fb.c index 3872ccef4cb2c429a744e6dc4ea563e1c4b159c7..593c390e98629f53326498576c10ca21e9201052 100644 --- a/drivers/video/fbdev/au1200fb.c +++ b/drivers/video/fbdev/au1200fb.c @@ -1039,6 +1039,9 @@ static int au1200fb_fb_check_var(struct fb_var_screeninfo *var, u32 pixclock; int screen_size, plane; + if (!var->pixclock) + return -EINVAL; + plane = fbdev->plane; /* Make sure that the mode respect all LCD controller and @@ -1741,6 +1744,9 @@ static int au1200fb_drv_probe(struct platform_device *dev) /* Now hook interrupt too */ irq = platform_get_irq(dev, 0); + if (irq < 0) + return irq; + ret = request_irq(irq, au1200fb_handle_irq, IRQF_SHARED, "lcd", (void *)dev); if (ret) { diff --git a/drivers/video/fbdev/core/bitblit.c b/drivers/video/fbdev/core/bitblit.c index 436365efae7310c3559a02356161a74925d2c5d2..5bb2b07cbe1a0e36518b06922f023e9016299ee4 100644 --- a/drivers/video/fbdev/core/bitblit.c +++ b/drivers/video/fbdev/core/bitblit.c @@ -247,6 +247,9 @@ static void bit_cursor(struct vc_data *vc, struct fb_info *info, int mode, cursor.set = 0; + if (!vc->vc_font.data) + return; + c = scr_readw((u16 *) vc->vc_pos); attribute = get_attribute(info, c); src = vc->vc_font.data + ((c & charmask) * (w * vc->vc_font.height)); diff --git a/drivers/video/fbdev/core/modedb.c b/drivers/video/fbdev/core/modedb.c index 6473e0dfe1464b616ff1999cae7516340456c0d8..e78ec7f7284634a1a4d0b5148e5a1be31c30d658 100644 --- a/drivers/video/fbdev/core/modedb.c +++ b/drivers/video/fbdev/core/modedb.c @@ -257,6 +257,11 @@ static const struct fb_videomode modedb[] = { { NULL, 72, 480, 300, 33386, 40, 24, 11, 19, 80, 3, 0, FB_VMODE_DOUBLE }, + /* 1920x1080 @ 60 Hz, 67.3 kHz hsync */ + { NULL, 60, 1920, 1080, 6734, 148, 88, 36, 4, 44, 5, 0, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED }, + /* 1920x1200 @ 60 Hz, 74.5 Khz hsync */ { NULL, 60, 1920, 1200, 5177, 128, 336, 1, 38, 208, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, diff --git a/drivers/video/fbdev/core/sysimgblt.c b/drivers/video/fbdev/core/sysimgblt.c index a4d05b1b17d7da6dfdebcf6c7df3f538cbb982e6..665ef7a0a2495bde34d6306d268cdb41353f9061 100644 --- a/drivers/video/fbdev/core/sysimgblt.c +++ b/drivers/video/fbdev/core/sysimgblt.c @@ -188,23 +188,29 @@ static void fast_imageblit(const struct fb_image *image, struct fb_info *p, { u32 fgx = fgcolor, bgx = bgcolor, bpp = p->var.bits_per_pixel; u32 ppw = 32/bpp, spitch = (image->width + 7)/8; - u32 bit_mask, end_mask, eorx, shift; - const char *s = image->data, *src; + u32 bit_mask, eorx, shift; + const u8 *s = image->data, *src; u32 *dst; - const u32 *tab = NULL; + const u32 *tab; + size_t tablen; + u32 colortab[16]; int i, j, k; switch (bpp) { case 8: tab = fb_be_math(p) ? cfb_tab8_be : cfb_tab8_le; + tablen = 16; break; case 16: tab = fb_be_math(p) ? cfb_tab16_be : cfb_tab16_le; + tablen = 4; break; case 32: - default: tab = cfb_tab32; + tablen = 2; break; + default: + return; } for (i = ppw-1; i--; ) { @@ -218,20 +224,62 @@ static void fast_imageblit(const struct fb_image *image, struct fb_info *p, eorx = fgx ^ bgx; k = image->width/ppw; + for (i = 0; i < tablen; ++i) + colortab[i] = (tab[i] & eorx) ^ bgx; + for (i = image->height; i--; ) { dst = dst1; shift = 8; src = s; - for (j = k; j--; ) { + /* + * Manually unroll the per-line copying loop for better + * performance. This works until we processed the last + * completely filled source byte (inclusive). + */ + switch (ppw) { + case 4: /* 8 bpp */ + for (j = k; j >= 2; j -= 2, ++src) { + *dst++ = colortab[(*src >> 4) & bit_mask]; + *dst++ = colortab[(*src >> 0) & bit_mask]; + } + break; + case 2: /* 16 bpp */ + for (j = k; j >= 4; j -= 4, ++src) { + *dst++ = colortab[(*src >> 6) & bit_mask]; + *dst++ = colortab[(*src >> 4) & bit_mask]; + *dst++ = colortab[(*src >> 2) & bit_mask]; + *dst++ = colortab[(*src >> 0) & bit_mask]; + } + break; + case 1: /* 32 bpp */ + for (j = k; j >= 8; j -= 8, ++src) { + *dst++ = colortab[(*src >> 7) & bit_mask]; + *dst++ = colortab[(*src >> 6) & bit_mask]; + *dst++ = colortab[(*src >> 5) & bit_mask]; + *dst++ = colortab[(*src >> 4) & bit_mask]; + *dst++ = colortab[(*src >> 3) & bit_mask]; + *dst++ = colortab[(*src >> 2) & bit_mask]; + *dst++ = colortab[(*src >> 1) & bit_mask]; + *dst++ = colortab[(*src >> 0) & bit_mask]; + } + break; + } + + /* + * For image widths that are not a multiple of 8, there + * are trailing pixels left on the current line. Print + * them as well. + */ + for (; j--; ) { shift -= ppw; - end_mask = tab[(*src >> shift) & bit_mask]; - *dst++ = (end_mask & eorx) ^ bgx; + *dst++ = colortab[(*src >> shift) & bit_mask]; if (!shift) { shift = 8; - src++; + ++src; } } + dst1 += p->fix.line_length; s += spitch; } diff --git a/drivers/video/fbdev/ep93xx-fb.c b/drivers/video/fbdev/ep93xx-fb.c index 75f0db25d19fef774b4903f71b43f9beb5a578f2..e81593a93d23ee343e4cfdf95310167e56a6a402 100644 --- a/drivers/video/fbdev/ep93xx-fb.c +++ b/drivers/video/fbdev/ep93xx-fb.c @@ -478,7 +478,6 @@ static int ep93xxfb_probe(struct platform_device *pdev) if (!info) return -ENOMEM; - info->dev = &pdev->dev; platform_set_drvdata(pdev, info); fbi = info->par; fbi->mach_info = mach_info; diff --git a/drivers/video/fbdev/fsl-diu-fb.c b/drivers/video/fbdev/fsl-diu-fb.c index bc9eb8afc3137dbea13728a9d1bff9fc03bff016..0a86a916140855722ca47ec1d7904740cdc7a058 100644 --- a/drivers/video/fbdev/fsl-diu-fb.c +++ b/drivers/video/fbdev/fsl-diu-fb.c @@ -495,7 +495,7 @@ static enum fsl_diu_monitor_port fsl_diu_name_to_port(const char *s) * Workaround for failed writing desc register of planes. * Needed with MPC5121 DIU rev 2.0 silicon. */ -void wr_reg_wa(u32 *reg, u32 val) +static void wr_reg_wa(u32 *reg, u32 val) { do { out_be32(reg, val); diff --git a/drivers/video/fbdev/geode/lxfb_core.c b/drivers/video/fbdev/geode/lxfb_core.c index 138da6cb6cbcd5efbb8d1668ab66b87abfd99de7..4345246b4c798f22cabb5e062c2fdd4f6b216b23 100644 --- a/drivers/video/fbdev/geode/lxfb_core.c +++ b/drivers/video/fbdev/geode/lxfb_core.c @@ -247,6 +247,9 @@ static void get_modedb(struct fb_videomode **modedb, unsigned int *size) static int lxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { + if (!var->pixclock) + return -EINVAL; + if (var->xres > 1920 || var->yres > 1440) return -EINVAL; diff --git a/drivers/video/fbdev/imsttfb.c b/drivers/video/fbdev/imsttfb.c index ecdcf358ad5eac2d76f20439add5818625ff64e2..30ba79d3dbea4e2879429d69a791cdd74bfc1fd5 100644 --- a/drivers/video/fbdev/imsttfb.c +++ b/drivers/video/fbdev/imsttfb.c @@ -1348,7 +1348,7 @@ static struct fb_ops imsttfb_ops = { .fb_ioctl = imsttfb_ioctl, }; -static void init_imstt(struct fb_info *info) +static int init_imstt(struct fb_info *info) { struct imstt_par *par = info->par; __u32 i, tmp, *ip, *end; @@ -1420,7 +1420,7 @@ static void init_imstt(struct fb_info *info) || !(compute_imstt_regvals(par, info->var.xres, info->var.yres))) { printk("imsttfb: %ux%ux%u not supported\n", info->var.xres, info->var.yres, info->var.bits_per_pixel); framebuffer_release(info); - return; + return -ENODEV; } sprintf(info->fix.id, "IMS TT (%s)", par->ramdac == IBM ? "IBM" : "TVP"); @@ -1456,12 +1456,13 @@ static void init_imstt(struct fb_info *info) if (register_framebuffer(info) < 0) { framebuffer_release(info); - return; + return -ENODEV; } tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8; fb_info(info, "%s frame buffer; %uMB vram; chip version %u\n", info->fix.id, info->fix.smem_len >> 20, tmp); + return 0; } static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -1470,6 +1471,7 @@ static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) struct imstt_par *par; struct fb_info *info; struct device_node *dp; + int ret = -ENOMEM; dp = pci_device_to_OF_node(pdev); if(dp) @@ -1491,8 +1493,8 @@ static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (!request_mem_region(addr, size, "imsttfb")) { printk(KERN_ERR "imsttfb: Can't reserve memory region\n"); - framebuffer_release(info); - return -ENODEV; + ret = -ENODEV; + goto release_info; } switch (pdev->device) { @@ -1508,23 +1510,42 @@ static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) default: printk(KERN_INFO "imsttfb: Device 0x%x unknown, " "contact maintainer.\n", pdev->device); - release_mem_region(addr, size); - framebuffer_release(info); - return -ENODEV; + ret = -ENODEV; + goto release_mem_region; } info->fix.smem_start = addr; info->screen_base = (__u8 *)ioremap(addr, par->ramdac == IBM ? 0x400000 : 0x800000); + if (!info->screen_base) + goto release_mem_region; info->fix.mmio_start = addr + 0x800000; par->dc_regs = ioremap(addr + 0x800000, 0x1000); + if (!par->dc_regs) + goto unmap_screen_base; par->cmap_regs_phys = addr + 0x840000; par->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000); + if (!par->cmap_regs) + goto unmap_dc_regs; info->pseudo_palette = par->palette; - init_imstt(info); + ret = init_imstt(info); + if (ret) + goto unmap_cmap_regs; pci_set_drvdata(pdev, info); return 0; + +unmap_cmap_regs: + iounmap(par->cmap_regs); +unmap_dc_regs: + iounmap(par->dc_regs); +unmap_screen_base: + iounmap(info->screen_base); +release_mem_region: + release_mem_region(addr, size); +release_info: + framebuffer_release(info); + return ret; } static void imsttfb_remove(struct pci_dev *pdev) diff --git a/drivers/video/fbdev/imxfb.c b/drivers/video/fbdev/imxfb.c index c4eb8661f7516d965d3a988400ce10730a181a4e..8ec260ed9a6f69217d87904700ac0cbcb8ba3585 100644 --- a/drivers/video/fbdev/imxfb.c +++ b/drivers/video/fbdev/imxfb.c @@ -601,10 +601,10 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf if (var->hsync_len < 1 || var->hsync_len > 64) printk(KERN_ERR "%s: invalid hsync_len %d\n", info->fix.id, var->hsync_len); - if (var->left_margin > 255) + if (var->left_margin < 3 || var->left_margin > 255) printk(KERN_ERR "%s: invalid left_margin %d\n", info->fix.id, var->left_margin); - if (var->right_margin > 255) + if (var->right_margin < 1 || var->right_margin > 255) printk(KERN_ERR "%s: invalid right_margin %d\n", info->fix.id, var->right_margin); if (var->yres < 1 || var->yres > ymax_mask) diff --git a/drivers/video/fbdev/intelfb/intelfbdrv.c b/drivers/video/fbdev/intelfb/intelfbdrv.c index d7463a2a5d83f2f11ae00662aab3edc7b1682cba..c97c0c85148095794119e269b0e35c808c73d748 100644 --- a/drivers/video/fbdev/intelfb/intelfbdrv.c +++ b/drivers/video/fbdev/intelfb/intelfbdrv.c @@ -1215,6 +1215,9 @@ static int intelfb_check_var(struct fb_var_screeninfo *var, dinfo = GET_DINFO(info); + if (!var->pixclock) + return -EINVAL; + /* update the pitch */ if (intelfbhw_validate_mode(dinfo, var) != 0) return -EINVAL; diff --git a/drivers/video/fbdev/matrox/matroxfb_maven.c b/drivers/video/fbdev/matrox/matroxfb_maven.c index bf5ce04f9aea55733bf513bc237f42c489666d26..267b31ddb02d34efa03cf4679b9557956a5e919d 100644 --- a/drivers/video/fbdev/matrox/matroxfb_maven.c +++ b/drivers/video/fbdev/matrox/matroxfb_maven.c @@ -299,7 +299,7 @@ static int matroxfb_mavenclock(const struct matrox_pll_ctl *ctl, unsigned int* in, unsigned int* feed, unsigned int* post, unsigned int* htotal2) { unsigned int fvco; - unsigned int uninitialized_var(p); + unsigned int p; fvco = matroxfb_PLL_mavenclock(&maven1000_pll, ctl, htotal, vtotal, in, feed, &p, htotal2); if (!fvco) @@ -731,8 +731,8 @@ static int maven_find_exact_clocks(unsigned int ht, unsigned int vt, for (x = 0; x < 8; x++) { unsigned int c; - unsigned int uninitialized_var(a), uninitialized_var(b), - uninitialized_var(h2); + unsigned int a, b, + h2; unsigned int h = ht + 2 + x; if (!matroxfb_mavenclock((m->mode == MATROXFB_OUTPUT_MODE_PAL) ? &maven_PAL : &maven_NTSC, h, vt, &a, &b, &c, &h2)) { diff --git a/drivers/video/fbdev/mmp/hw/mmp_ctrl.c b/drivers/video/fbdev/mmp/hw/mmp_ctrl.c index fcdbb2df137f891e58bcdce792a3a3101daa73d1..2277d64310abf7ab89117752d09dfa2b75b371ac 100644 --- a/drivers/video/fbdev/mmp/hw/mmp_ctrl.c +++ b/drivers/video/fbdev/mmp/hw/mmp_ctrl.c @@ -523,7 +523,9 @@ static int mmphw_probe(struct platform_device *pdev) ret = -ENOENT; goto failed; } - clk_prepare_enable(ctrl->clk); + ret = clk_prepare_enable(ctrl->clk); + if (ret) + goto failed; /* init global regs */ ctrl_set_default(ctrl); diff --git a/drivers/video/fbdev/msm/mdss_mdp.c b/drivers/video/fbdev/msm/mdss_mdp.c index f89e62d12aef31b36fc47adb3c4d01b798edf455..149b5fca772c5d1beffa9dabd027e38503366abf 100644 --- a/drivers/video/fbdev/msm/mdss_mdp.c +++ b/drivers/video/fbdev/msm/mdss_mdp.c @@ -4868,7 +4868,7 @@ struct mdss_panel_cfg *mdss_panel_intf_type(int intf_val) } EXPORT_SYMBOL(mdss_panel_intf_type); -struct irq_info *mdss_intr_line() +struct irq_info *mdss_intr_line(void) { return mdss_mdp_hw.irq_info; } diff --git a/drivers/video/fbdev/msm/mdss_util.c b/drivers/video/fbdev/msm/mdss_util.c index f0fa58dcf8f7e501e9e684b42559057fa561dbab..f86c17fbdd995754d7a9947e6f5c9d1350004b4a 100644 --- a/drivers/video/fbdev/msm/mdss_util.c +++ b/drivers/video/fbdev/msm/mdss_util.c @@ -223,7 +223,7 @@ struct mdss_util_intf mdss_util = { .mdp_probe_done = false }; -struct mdss_util_intf *mdss_get_util_intf() +struct mdss_util_intf *mdss_get_util_intf(void) { return &mdss_util; } diff --git a/drivers/video/fbdev/nvidia/nvidia.c b/drivers/video/fbdev/nvidia/nvidia.c index fbeeed5afe350deff19eea67c1463ba5ba158fe6..aa502b3ba25aeb7187921b4a4a4b408a701515ac 100644 --- a/drivers/video/fbdev/nvidia/nvidia.c +++ b/drivers/video/fbdev/nvidia/nvidia.c @@ -766,6 +766,8 @@ static int nvidiafb_check_var(struct fb_var_screeninfo *var, int pitch, err = 0; NVTRACE_ENTER(); + if (!var->pixclock) + return -EINVAL; var->transp.offset = 0; var->transp.length = 0; diff --git a/drivers/video/fbdev/omap/lcd_mipid.c b/drivers/video/fbdev/omap/lcd_mipid.c index e3a85432f9266943886e6e2504e5415b66f359d4..5730355ee5986898362a83160b4f3adc240bd7f6 100644 --- a/drivers/video/fbdev/omap/lcd_mipid.c +++ b/drivers/video/fbdev/omap/lcd_mipid.c @@ -576,11 +576,15 @@ static int mipid_spi_probe(struct spi_device *spi) r = mipid_detect(md); if (r < 0) - return r; + goto free_md; omapfb_register_panel(&md->panel); return 0; + +free_md: + kfree(md); + return r; } static int mipid_spi_remove(struct spi_device *spi) diff --git a/drivers/video/fbdev/pm3fb.c b/drivers/video/fbdev/pm3fb.c index 6130aa56a1e93239dbad34558ed6273ce155d4e2..7bd45334dcac4005ecb3d6d13764550f3e1190d8 100644 --- a/drivers/video/fbdev/pm3fb.c +++ b/drivers/video/fbdev/pm3fb.c @@ -821,9 +821,9 @@ static void pm3fb_write_mode(struct fb_info *info) wmb(); { - unsigned char uninitialized_var(m); /* ClkPreScale */ - unsigned char uninitialized_var(n); /* ClkFeedBackScale */ - unsigned char uninitialized_var(p); /* ClkPostScale */ + unsigned char m; /* ClkPreScale */ + unsigned char n; /* ClkFeedBackScale */ + unsigned char p; /* ClkPostScale */ unsigned long pixclock = PICOS2KHZ(info->var.pixclock); (void)pm3fb_calculate_clock(pixclock, &m, &n, &p); diff --git a/drivers/video/fbdev/riva/riva_hw.c b/drivers/video/fbdev/riva/riva_hw.c index 0601c13f21050970f7112b6f9be52034827a343d..f90b9327bae73f56705bd81459a9cf45046fe554 100644 --- a/drivers/video/fbdev/riva/riva_hw.c +++ b/drivers/video/fbdev/riva/riva_hw.c @@ -1245,8 +1245,7 @@ int CalcStateExt ) { int pixelDepth; - int uninitialized_var(VClk),uninitialized_var(m), - uninitialized_var(n), uninitialized_var(p); + int VClk, m, n, p; /* * Save mode parameters. diff --git a/drivers/video/fbdev/stifb.c b/drivers/video/fbdev/stifb.c index 9530ed46f4358e3be23eddcc3e42d1c8b1d3ad5d..9c2be080265148d4f6be875a6c17f762dc930e72 100644 --- a/drivers/video/fbdev/stifb.c +++ b/drivers/video/fbdev/stifb.c @@ -921,6 +921,28 @@ SETUP_HCRX(struct stifb_info *fb) /* ------------------- driver specific functions --------------------------- */ +static int +stifb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct stifb_info *fb = container_of(info, struct stifb_info, info); + + if (var->xres != fb->info.var.xres || + var->yres != fb->info.var.yres || + var->bits_per_pixel != fb->info.var.bits_per_pixel) + return -EINVAL; + + var->xres_virtual = var->xres; + var->yres_virtual = var->yres; + var->xoffset = 0; + var->yoffset = 0; + var->grayscale = fb->info.var.grayscale; + var->red.length = fb->info.var.red.length; + var->green.length = fb->info.var.green.length; + var->blue.length = fb->info.var.blue.length; + + return 0; +} + static int stifb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, u_int transp, struct fb_info *info) @@ -1103,6 +1125,7 @@ stifb_init_display(struct stifb_info *fb) static struct fb_ops stifb_ops = { .owner = THIS_MODULE, + .fb_check_var = stifb_check_var, .fb_setcolreg = stifb_setcolreg, .fb_blank = stifb_blank, .fb_fillrect = cfb_fillrect, @@ -1122,6 +1145,7 @@ static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref) struct stifb_info *fb; struct fb_info *info; unsigned long sti_rom_address; + char modestr[32]; char *dev_name; int bpp, xres, yres; @@ -1300,6 +1324,9 @@ static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref) info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA; info->pseudo_palette = &fb->pseudo_palette; + scnprintf(modestr, sizeof(modestr), "%dx%d-%d", xres, yres, bpp); + fb_find_mode(&info->var, info, modestr, NULL, 0, NULL, bpp); + /* This has to be done !!! */ if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0)) goto out_err1; @@ -1344,6 +1371,7 @@ static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref) iounmap(info->screen_base); out_err0: kfree(fb); + sti->info = NULL; return -ENXIO; } diff --git a/drivers/video/fbdev/tgafb.c b/drivers/video/fbdev/tgafb.c index 65ba9921506e2b818f05fa4a308ac383f90c7ddf..9d2912947eef6e6d53e30c23b37df781fbf88bf5 100644 --- a/drivers/video/fbdev/tgafb.c +++ b/drivers/video/fbdev/tgafb.c @@ -166,6 +166,9 @@ tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { struct tga_par *par = (struct tga_par *)info->par; + if (!var->pixclock) + return -EINVAL; + if (par->tga_type == TGA_TYPE_8PLANE) { if (var->bits_per_pixel != 8) return -EINVAL; diff --git a/drivers/video/fbdev/uvesafb.c b/drivers/video/fbdev/uvesafb.c index f6ebca8839127564e1b759fecf100fb1e4010f79..1ded93f106f0796db382d85e30d9c71818883542 100644 --- a/drivers/video/fbdev/uvesafb.c +++ b/drivers/video/fbdev/uvesafb.c @@ -1932,10 +1932,10 @@ static void uvesafb_exit(void) } } - cn_del_callback(&uvesafb_cn_id); driver_remove_file(&uvesafb_driver.driver, &driver_attr_v86d); platform_device_unregister(uvesafb_device); platform_driver_unregister(&uvesafb_driver); + cn_del_callback(&uvesafb_cn_id); } module_exit(uvesafb_exit); diff --git a/drivers/virtio/virtio_balloon.c b/drivers/virtio/virtio_balloon.c index 1afcbef397ab7d3ee0e56ffb67f51e75cdeeb08e..017444b3f74582cb4b4abd033a295617d5529ca4 100644 --- a/drivers/virtio/virtio_balloon.c +++ b/drivers/virtio/virtio_balloon.c @@ -345,7 +345,11 @@ static inline s64 towards_target(struct virtio_balloon *vb) if (!virtio_has_feature(vb->vdev, VIRTIO_F_VERSION_1)) num_pages = le32_to_cpu((__force __le32)num_pages); - target = num_pages; + /* + * Aligned up to guest page size to avoid inflating and deflating + * balloon endlessly. + */ + target = ALIGN(num_pages, VIRTIO_BALLOON_PAGES_PER_PAGE); return target - vb->num_pages; } diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index 17cd682acc22b3763b30ab9beb1feabf7930888b..3597d7b7feda4370b5e2ea3632880292d20e0946 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -536,11 +536,9 @@ static void virtio_mmio_release_dev(struct device *_d) { struct virtio_device *vdev = container_of(_d, struct virtio_device, dev); - struct virtio_mmio_device *vm_dev = - container_of(vdev, struct virtio_mmio_device, vdev); - struct platform_device *pdev = vm_dev->pdev; + struct virtio_mmio_device *vm_dev = to_virtio_mmio_device(vdev); - devm_kfree(&pdev->dev, vm_dev); + kfree(vm_dev); } /* Platform device */ @@ -548,19 +546,10 @@ static void virtio_mmio_release_dev(struct device *_d) static int virtio_mmio_probe(struct platform_device *pdev) { struct virtio_mmio_device *vm_dev; - struct resource *mem; unsigned long magic; int rc; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!mem) - return -EINVAL; - - if (!devm_request_mem_region(&pdev->dev, mem->start, - resource_size(mem), pdev->name)) - return -EBUSY; - - vm_dev = devm_kzalloc(&pdev->dev, sizeof(*vm_dev), GFP_KERNEL); + vm_dev = kzalloc(sizeof(*vm_dev), GFP_KERNEL); if (!vm_dev) return -ENOMEM; @@ -571,15 +560,18 @@ static int virtio_mmio_probe(struct platform_device *pdev) INIT_LIST_HEAD(&vm_dev->virtqueues); spin_lock_init(&vm_dev->lock); - vm_dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); - if (vm_dev->base == NULL) - return -EFAULT; + vm_dev->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(vm_dev->base)) { + rc = PTR_ERR(vm_dev->base); + goto free_vm_dev; + } /* Check magic value */ magic = readl(vm_dev->base + VIRTIO_MMIO_MAGIC_VALUE); if (magic != ('v' | 'i' << 8 | 'r' << 16 | 't' << 24)) { dev_warn(&pdev->dev, "Wrong magic value 0x%08lx!\n", magic); - return -ENODEV; + rc = -ENODEV; + goto free_vm_dev; } /* Check device version */ @@ -587,7 +579,8 @@ static int virtio_mmio_probe(struct platform_device *pdev) if (vm_dev->version < 1 || vm_dev->version > 2) { dev_err(&pdev->dev, "Version %ld not supported!\n", vm_dev->version); - return -ENXIO; + rc = -ENXIO; + goto free_vm_dev; } vm_dev->vdev.id.device = readl(vm_dev->base + VIRTIO_MMIO_DEVICE_ID); @@ -596,7 +589,8 @@ static int virtio_mmio_probe(struct platform_device *pdev) * virtio-mmio device with an ID 0 is a (dummy) placeholder * with no function. End probing now with no error reported. */ - return -ENODEV; + rc = -ENODEV; + goto free_vm_dev; } vm_dev->vdev.id.vendor = readl(vm_dev->base + VIRTIO_MMIO_VENDOR_ID); @@ -626,6 +620,10 @@ static int virtio_mmio_probe(struct platform_device *pdev) put_device(&vm_dev->vdev.dev); return rc; + +free_vm_dev: + kfree(vm_dev); + return rc; } static int virtio_mmio_remove(struct platform_device *pdev) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 0cc0cfd3a3cb744f32a5677908e68af8a27144f4..8acfbe420b5a044757cab26848851cda574fa946 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -268,7 +268,7 @@ static inline int virtqueue_add(struct virtqueue *_vq, struct vring_virtqueue *vq = to_vvq(_vq); struct scatterlist *sg; struct vring_desc *desc; - unsigned int i, n, avail, descs_used, uninitialized_var(prev), err_idx; + unsigned int i, n, avail, descs_used, prev, err_idx; int head; bool indirect; diff --git a/drivers/w1/w1.c b/drivers/w1/w1.c index cb3650efc29cde2cce6b6b68747a7816034931a2..8db9ca241d99c43cdc02a1107ee69cd58955567c 100644 --- a/drivers/w1/w1.c +++ b/drivers/w1/w1.c @@ -1237,10 +1237,10 @@ static int __init w1_init(void) static void __exit w1_fini(void) { - struct w1_master *dev; + struct w1_master *dev, *n; /* Set netlink removal messages and some cleanup */ - list_for_each_entry(dev, &w1_masters, w1_master_entry) + list_for_each_entry_safe(dev, n, &w1_masters, w1_master_entry) __w1_remove_master_device(dev); w1_fini_netlink(); diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index f4050a229eb5865574f3085be11d747d2ff020ee..aaa3c5a8c45700511f274cc8a3557be90ef4a1b4 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -206,10 +206,9 @@ static int at91_wdt_init(struct platform_device *pdev, struct at91wdt *wdt) "min heartbeat and max heartbeat might be too close for the system to handle it correctly\n"); if ((tmp & AT91_WDT_WDFIEN) && wdt->irq) { - err = request_irq(wdt->irq, wdt_interrupt, - IRQF_SHARED | IRQF_IRQPOLL | - IRQF_NO_SUSPEND, - pdev->name, wdt); + err = devm_request_irq(dev, wdt->irq, wdt_interrupt, + IRQF_SHARED | IRQF_IRQPOLL | IRQF_NO_SUSPEND, + pdev->name, wdt); if (err) return err; } diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c index 347f0389b0899d4183021254203e0a0938600267..5ec52032117a7cf093bae7ca305293b30e6a5559 100644 --- a/drivers/watchdog/iTCO_wdt.c +++ b/drivers/watchdog/iTCO_wdt.c @@ -401,6 +401,20 @@ static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev) return time_left; } +/* Returns true if the watchdog was running */ +static bool iTCO_wdt_set_running(struct iTCO_wdt_private *p) +{ + u16 val; + + /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled */ + val = inw(TCO1_CNT(p)); + if (!(val & BIT(11))) { + set_bit(WDOG_HW_RUNNING, &p->wddev.status); + return true; + } + return false; +} + /* * Kernel Interfaces */ @@ -476,9 +490,6 @@ static int iTCO_wdt_probe(struct platform_device *pdev) return -ENODEV; /* Cannot reset NO_REBOOT bit */ } - /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ - p->update_no_reboot_bit(p->no_reboot_priv, true); - /* The TCO logic uses the TCO_EN bit in the SMI_EN register */ if (!devm_request_region(dev, p->smi_res->start, resource_size(p->smi_res), @@ -537,8 +548,13 @@ static int iTCO_wdt_probe(struct platform_device *pdev) watchdog_set_drvdata(&p->wddev, p); platform_set_drvdata(pdev, p); - /* Make sure the watchdog is not running */ - iTCO_wdt_stop(&p->wddev); + if (!iTCO_wdt_set_running(p)) { + /* + * If the watchdog was not running set NO_REBOOT now to + * prevent later reboots. + */ + p->update_no_reboot_bit(p->no_reboot_priv, true); + } /* Check that the heartbeat value is within it's range; if not reset to the default */ diff --git a/drivers/watchdog/intel-mid_wdt.c b/drivers/watchdog/intel-mid_wdt.c index 72c108a12c19d72d9958c71a62a315b8e3a4668a..0dec3fba02b999118549c0c035de99a7f4da0a73 100644 --- a/drivers/watchdog/intel-mid_wdt.c +++ b/drivers/watchdog/intel-mid_wdt.c @@ -186,3 +186,4 @@ module_platform_driver(mid_wdt_driver); MODULE_AUTHOR("David Cohen "); MODULE_DESCRIPTION("Watchdog Driver for Intel MID platform"); MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:intel_mid_wdt"); diff --git a/drivers/watchdog/menz69_wdt.c b/drivers/watchdog/menz69_wdt.c index ed18238c54074e8c98cd6a21fa35b5ff557f2f52..96a25d18ab643b923c94fcbdc5458fc2af731036 100644 --- a/drivers/watchdog/menz69_wdt.c +++ b/drivers/watchdog/menz69_wdt.c @@ -98,14 +98,6 @@ static const struct watchdog_ops men_z069_ops = { .set_timeout = men_z069_wdt_set_timeout, }; -static struct watchdog_device men_z069_wdt = { - .info = &men_z069_info, - .ops = &men_z069_ops, - .timeout = MEN_Z069_DEFAULT_TIMEOUT, - .min_timeout = 1, - .max_timeout = MEN_Z069_WDT_COUNTER_MAX / MEN_Z069_TIMER_FREQ, -}; - static int men_z069_probe(struct mcb_device *dev, const struct mcb_device_id *id) { @@ -125,15 +117,19 @@ static int men_z069_probe(struct mcb_device *dev, goto release_mem; drv->mem = mem; + drv->wdt.info = &men_z069_info; + drv->wdt.ops = &men_z069_ops; + drv->wdt.timeout = MEN_Z069_DEFAULT_TIMEOUT; + drv->wdt.min_timeout = 1; + drv->wdt.max_timeout = MEN_Z069_WDT_COUNTER_MAX / MEN_Z069_TIMER_FREQ; - drv->wdt = men_z069_wdt; watchdog_init_timeout(&drv->wdt, 0, &dev->dev); watchdog_set_nowayout(&drv->wdt, nowayout); watchdog_set_drvdata(&drv->wdt, drv); drv->wdt.parent = &dev->dev; mcb_set_drvdata(dev, drv); - return watchdog_register_device(&men_z069_wdt); + return watchdog_register_device(&drv->wdt); release_mem: mcb_release_mem(mem); diff --git a/drivers/watchdog/pcwd_usb.c b/drivers/watchdog/pcwd_usb.c index 4d02f26156f9ce10f03993d8dd88b79b4715f848..b7b9d562da13792ef05f9c995bea28ed12fec924 100644 --- a/drivers/watchdog/pcwd_usb.c +++ b/drivers/watchdog/pcwd_usb.c @@ -329,7 +329,8 @@ static int usb_pcwd_set_heartbeat(struct usb_pcwd_private *usb_pcwd, int t) static int usb_pcwd_get_temperature(struct usb_pcwd_private *usb_pcwd, int *temperature) { - unsigned char msb, lsb; + unsigned char msb = 0x00; + unsigned char lsb = 0x00; usb_pcwd_send_command(usb_pcwd, CMD_READ_TEMP, &msb, &lsb); @@ -345,7 +346,8 @@ static int usb_pcwd_get_temperature(struct usb_pcwd_private *usb_pcwd, static int usb_pcwd_get_timeleft(struct usb_pcwd_private *usb_pcwd, int *time_left) { - unsigned char msb, lsb; + unsigned char msb = 0x00; + unsigned char lsb = 0x00; /* Read the time that's left before rebooting */ /* Note: if the board is not yet armed then we will read 0xFFFF */ diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c index e8bd9887c56638aaf81659c45d7505c424266b55..1ffb0394c8a1745f9976de8fd7cde342fc3db646 100644 --- a/drivers/watchdog/sbsa_gwdt.c +++ b/drivers/watchdog/sbsa_gwdt.c @@ -130,6 +130,7 @@ static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd, struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); wdd->timeout = timeout; + timeout = clamp_t(unsigned int, timeout, 1, wdd->max_hw_heartbeat_ms / 1000); if (action) writel(gwdt->clk * timeout, diff --git a/drivers/watchdog/watchdog_dev.c b/drivers/watchdog/watchdog_dev.c index 8fe59b7d8eec855d8eee56cb5949aefb8a179dd5..808896c9e1c20c48080818f1b9b9d3a82c124bde 100644 --- a/drivers/watchdog/watchdog_dev.c +++ b/drivers/watchdog/watchdog_dev.c @@ -989,8 +989,8 @@ static int watchdog_cdev_register(struct watchdog_device *wdd) if (wdd->id == 0) { misc_deregister(&watchdog_miscdev); old_wd_data = NULL; - put_device(&wd_data->dev); } + put_device(&wd_data->dev); return err; } diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c index b6b3131cb079f9e23ef4e1a32c55be187a679cab..3b27b98175c6d8b78bd38e304d612d12a7168610 100644 --- a/drivers/xen/events/events_base.c +++ b/drivers/xen/events/events_base.c @@ -82,23 +82,13 @@ const struct evtchn_ops *evtchn_ops; */ static DEFINE_MUTEX(irq_mapping_update_lock); -/* - * Lock protecting event handling loop against removing event channels. - * Adding of event channels is no issue as the associated IRQ becomes active - * only after everything is setup (before request_[threaded_]irq() the handler - * can't be entered for an event, as the event channel will be unmasked only - * then). - */ -static DEFINE_RWLOCK(evtchn_rwlock); - /* * Lock hierarchy: * * irq_mapping_update_lock - * evtchn_rwlock - * IRQ-desc lock - * percpu eoi_list_lock - * irq_info->lock + * IRQ-desc lock + * percpu eoi_list_lock + * irq_info->lock */ static LIST_HEAD(xen_irq_list_head); @@ -213,6 +203,22 @@ static void set_info_for_irq(unsigned int irq, struct irq_info *info) irq_set_chip_data(irq, info); } +static void delayed_free_irq(struct work_struct *work) +{ + struct irq_info *info = container_of(to_rcu_work(work), struct irq_info, + rwork); + unsigned int irq = info->irq; + + /* Remove the info pointer only now, with no potential users left. */ + set_info_for_irq(irq, NULL); + + kfree(info); + + /* Legacy IRQ descriptors are managed by the arch. */ + if (irq >= nr_legacy_irqs()) + irq_free_desc(irq); +} + /* Constructors for packed IRQ information. */ static int xen_irq_info_common_setup(struct irq_info *info, unsigned irq, @@ -484,7 +490,9 @@ static void lateeoi_list_add(struct irq_info *info) spin_lock_irqsave(&eoi->eoi_list_lock, flags); - if (list_empty(&eoi->eoi_list)) { + elem = list_first_entry_or_null(&eoi->eoi_list, struct irq_info, + eoi_list); + if (!elem || info->eoi_time < elem->eoi_time) { list_add(&info->eoi_list, &eoi->eoi_list); mod_delayed_work_on(info->eoi_cpu, system_wq, &eoi->delayed, delay); @@ -547,33 +555,36 @@ static void xen_irq_lateeoi_worker(struct work_struct *work) eoi = container_of(to_delayed_work(work), struct lateeoi_work, delayed); - read_lock_irqsave(&evtchn_rwlock, flags); + rcu_read_lock(); while (true) { - spin_lock(&eoi->eoi_list_lock); + spin_lock_irqsave(&eoi->eoi_list_lock, flags); info = list_first_entry_or_null(&eoi->eoi_list, struct irq_info, eoi_list); - if (info == NULL || now < info->eoi_time) { - spin_unlock(&eoi->eoi_list_lock); + if (info == NULL) + break; + + if (now < info->eoi_time) { + mod_delayed_work_on(info->eoi_cpu, system_wq, + &eoi->delayed, + info->eoi_time - now); break; } list_del_init(&info->eoi_list); - spin_unlock(&eoi->eoi_list_lock); + spin_unlock_irqrestore(&eoi->eoi_list_lock, flags); info->eoi_time = 0; xen_irq_lateeoi_locked(info, false); } - if (info) - mod_delayed_work_on(info->eoi_cpu, system_wq, - &eoi->delayed, info->eoi_time - now); + spin_unlock_irqrestore(&eoi->eoi_list_lock, flags); - read_unlock_irqrestore(&evtchn_rwlock, flags); + rcu_read_unlock(); } static void xen_cpu_init_eoi(unsigned int cpu) @@ -588,16 +599,15 @@ static void xen_cpu_init_eoi(unsigned int cpu) void xen_irq_lateeoi(unsigned int irq, unsigned int eoi_flags) { struct irq_info *info; - unsigned long flags; - read_lock_irqsave(&evtchn_rwlock, flags); + rcu_read_lock(); info = info_for_irq(irq); if (info) xen_irq_lateeoi_locked(info, eoi_flags & XEN_EOI_FLAG_SPURIOUS); - read_unlock_irqrestore(&evtchn_rwlock, flags); + rcu_read_unlock(); } EXPORT_SYMBOL_GPL(xen_irq_lateeoi); @@ -616,6 +626,7 @@ static void xen_irq_init(unsigned irq) info->type = IRQT_UNBOUND; info->refcnt = -1; + INIT_RCU_WORK(&info->rwork, delayed_free_irq); set_info_for_irq(irq, info); @@ -668,31 +679,18 @@ static int __must_check xen_allocate_irq_gsi(unsigned gsi) static void xen_free_irq(unsigned irq) { struct irq_info *info = info_for_irq(irq); - unsigned long flags; if (WARN_ON(!info)) return; - write_lock_irqsave(&evtchn_rwlock, flags); - if (!list_empty(&info->eoi_list)) lateeoi_list_del(info); list_del(&info->list); - set_info_for_irq(irq, NULL); - WARN_ON(info->refcnt > 0); - write_unlock_irqrestore(&evtchn_rwlock, flags); - - kfree(info); - - /* Legacy IRQ descriptors are managed by the arch. */ - if (irq < nr_legacy_irqs()) - return; - - irq_free_desc(irq); + queue_rcu_work(system_wq, &info->rwork); } static void xen_evtchn_close(unsigned int port) @@ -1603,7 +1601,14 @@ static void __xen_evtchn_do_upcall(void) unsigned count; struct evtchn_loop_ctrl ctrl = { 0 }; - read_lock(&evtchn_rwlock); + /* + * When closing an event channel the associated IRQ must not be freed + * until all cpus have left the event handling loop. This is ensured + * by taking the rcu_read_lock() while handling events, as freeing of + * the IRQ is handled via queue_rcu_work() _after_ closing the event + * channel. + */ + rcu_read_lock(); do { vcpu_info->evtchn_upcall_pending = 0; @@ -1620,7 +1625,7 @@ static void __xen_evtchn_do_upcall(void) } while (count != 1 || vcpu_info->evtchn_upcall_pending); out: - read_unlock(&evtchn_rwlock); + rcu_read_unlock(); /* * Increment irq_epoch only now to defer EOIs only for diff --git a/drivers/xen/events/events_internal.h b/drivers/xen/events/events_internal.h index cc37b711491cef0838a56be7de378d5f2d87dc2f..1d9d9e6f1dee19cba6a3499834b36460a465fa46 100644 --- a/drivers/xen/events/events_internal.h +++ b/drivers/xen/events/events_internal.h @@ -8,6 +8,7 @@ */ #ifndef __EVENTS_INTERNAL_H__ #define __EVENTS_INTERNAL_H__ +#include /* Interrupt types. */ enum xen_irq_type { @@ -33,6 +34,7 @@ enum xen_irq_type { struct irq_info { struct list_head list; struct list_head eoi_list; + struct rcu_work rwork; short refcnt; short spurious_cnt; short type; /* type */ diff --git a/drivers/xen/pvcalls-back.c b/drivers/xen/pvcalls-back.c index f94bb6034a5a89248cf86a1325794bc1d785e08b..3441371a4ab47a0fb009e2401fa48f925d3a9f34 100644 --- a/drivers/xen/pvcalls-back.c +++ b/drivers/xen/pvcalls-back.c @@ -330,8 +330,10 @@ static struct sock_mapping *pvcalls_new_active_socket( void *page; map = kzalloc(sizeof(*map), GFP_KERNEL); - if (map == NULL) + if (map == NULL) { + sock_release(sock); return NULL; + } map->fedata = fedata; map->sock = sock; @@ -423,10 +425,8 @@ static int pvcalls_back_connect(struct xenbus_device *dev, req->u.connect.ref, req->u.connect.evtchn, sock); - if (!map) { + if (!map) ret = -EFAULT; - sock_release(sock); - } out: rsp = RING_GET_RESPONSE(&fedata->ring, fedata->ring.rsp_prod_pvt++); @@ -567,7 +567,6 @@ static void __pvcalls_back_accept(struct work_struct *work) sock); if (!map) { ret = -EFAULT; - sock_release(sock); goto out_error; } diff --git a/fs/afs/dir.c b/fs/afs/dir.c index 59eb924840518feed38834aa53bd3b219eb9a8f3..31055d71b7882807c90cb5672df8d0b527861442 100644 --- a/fs/afs/dir.c +++ b/fs/afs/dir.c @@ -887,7 +887,7 @@ static struct dentry *afs_lookup(struct inode *dir, struct dentry *dentry, static int afs_d_revalidate(struct dentry *dentry, unsigned int flags) { struct afs_vnode *vnode, *dir; - struct afs_fid uninitialized_var(fid); + struct afs_fid fid; struct dentry *parent; struct inode *inode; struct key *key; diff --git a/fs/afs/security.c b/fs/afs/security.c index 66042b432baa8a88012af6298d834b286ba3839b..e12e532069eef12d12f25cff2b2289f4d672d49d 100644 --- a/fs/afs/security.c +++ b/fs/afs/security.c @@ -340,7 +340,7 @@ int afs_check_permit(struct afs_vnode *vnode, struct key *key, int afs_permission(struct inode *inode, int mask) { struct afs_vnode *vnode = AFS_FS_I(inode); - afs_access_t uninitialized_var(access); + afs_access_t access; struct key *key; int ret; diff --git a/fs/attr.c b/fs/attr.c index 4df3ad1651b45dc241379a39787052e2c48572c0..90c8f5ce8144f0fda1c3fb403c586749fa449c7c 100644 --- a/fs/attr.c +++ b/fs/attr.c @@ -256,9 +256,25 @@ int notify_change2(struct vfsmount *mnt, struct dentry * dentry, struct iattr * } if ((ia_valid & ATTR_MODE)) { - umode_t amode = attr->ia_mode; + /* + * Don't allow changing the mode of symlinks: + * + * (1) The vfs doesn't take the mode of symlinks into account + * during permission checking. + * (2) This has never worked correctly. Most major filesystems + * did return EOPNOTSUPP due to interactions with POSIX ACLs + * but did still updated the mode of the symlink. + * This inconsistency led system call wrapper providers such + * as libc to block changing the mode of symlinks with + * EOPNOTSUPP already. + * (3) To even do this in the first place one would have to use + * specific file descriptors and quite some effort. + */ + if (S_ISLNK(inode->i_mode)) + return -EOPNOTSUPP; + /* Flag setting protected by i_mutex */ - if (is_sxid(amode)) + if (is_sxid(attr->ia_mode)) inode->i_flags &= ~S_NOSEC; } diff --git a/fs/autofs/waitq.c b/fs/autofs/waitq.c index f6385c6ef0a56afe90dee6f14dd9329ee62818c2..44ba0cd4ebc4f5910d6cb8ba0648b00afd8827ef 100644 --- a/fs/autofs/waitq.c +++ b/fs/autofs/waitq.c @@ -35,8 +35,9 @@ void autofs_catatonic_mode(struct autofs_sb_info *sbi) wq->status = -ENOENT; /* Magic is gone - report failure */ kfree(wq->name.name); wq->name.name = NULL; - wq->wait_ctr--; wake_up_interruptible(&wq->queue); + if (!--wq->wait_ctr) + kfree(wq); wq = nwq; } fput(sbi->pipe); /* Close the pipe */ diff --git a/fs/binfmt_elf_fdpic.c b/fs/binfmt_elf_fdpic.c index 64d0b838085d37d7b1d48198ab6a301354fd06c9..a7c2efcd0a4a31751b90bf0263dc359c2f2113f8 100644 --- a/fs/binfmt_elf_fdpic.c +++ b/fs/binfmt_elf_fdpic.c @@ -349,10 +349,9 @@ static int load_elf_fdpic_binary(struct linux_binprm *bprm) /* there's now no turning back... the old userspace image is dead, * defunct, deceased, etc. */ + SET_PERSONALITY(exec_params.hdr); if (elf_check_fdpic(&exec_params.hdr)) - set_personality(PER_LINUX_FDPIC); - else - set_personality(PER_LINUX); + current->personality |= PER_LINUX_FDPIC; if (elf_read_implies_exec(&exec_params.hdr, executable_stack)) current->personality |= READ_IMPLIES_EXEC; diff --git a/fs/btrfs/ctree.c b/fs/btrfs/ctree.c index 00dc1b5c873722ec0a439f79ce626e52d71acfdb..e48c6d7a860f420fda928ba3953c61d6698978cb 100644 --- a/fs/btrfs/ctree.c +++ b/fs/btrfs/ctree.c @@ -3590,6 +3590,8 @@ static noinline int split_node(struct btrfs_trans_handle *trans, ret = tree_mod_log_eb_copy(fs_info, split, c, 0, mid, c_nritems - mid); if (ret) { + btrfs_tree_unlock(split); + free_extent_buffer(split); btrfs_abort_transaction(trans, ret); return ret; } @@ -5151,10 +5153,12 @@ int btrfs_del_items(struct btrfs_trans_handle *trans, struct btrfs_root *root, int btrfs_prev_leaf(struct btrfs_root *root, struct btrfs_path *path) { struct btrfs_key key; + struct btrfs_key orig_key; struct btrfs_disk_key found_key; int ret; btrfs_item_key_to_cpu(path->nodes[0], &key, 0); + orig_key = key; if (key.offset > 0) { key.offset--; @@ -5171,8 +5175,36 @@ int btrfs_prev_leaf(struct btrfs_root *root, struct btrfs_path *path) btrfs_release_path(path); ret = btrfs_search_slot(NULL, root, &key, path, 0, 0); - if (ret < 0) + if (ret <= 0) return ret; + + /* + * Previous key not found. Even if we were at slot 0 of the leaf we had + * before releasing the path and calling btrfs_search_slot(), we now may + * be in a slot pointing to the same original key - this can happen if + * after we released the path, one of more items were moved from a + * sibling leaf into the front of the leaf we had due to an insertion + * (see push_leaf_right()). + * If we hit this case and our slot is > 0 and just decrement the slot + * so that the caller does not process the same key again, which may or + * may not break the caller, depending on its logic. + */ + if (path->slots[0] < btrfs_header_nritems(path->nodes[0])) { + btrfs_item_key(path->nodes[0], &found_key, path->slots[0]); + ret = comp_keys(&found_key, &orig_key); + if (ret == 0) { + if (path->slots[0] > 0) { + path->slots[0]--; + return 0; + } + /* + * At slot 0, same key as before, it means orig_key is + * the lowest, leftmost, key in the tree. We're done. + */ + return 1; + } + } + btrfs_item_key(path->nodes[0], &found_key, 0); ret = comp_keys(&found_key, &key); /* diff --git a/fs/btrfs/delayed-inode.c b/fs/btrfs/delayed-inode.c index 1fbe2dee1e7052ba899754337e436d0c40aed3f7..469a90b07d3f0a5eba36f7b7f56361b83d9f117a 100644 --- a/fs/btrfs/delayed-inode.c +++ b/fs/btrfs/delayed-inode.c @@ -1171,20 +1171,33 @@ static int __btrfs_run_delayed_items(struct btrfs_trans_handle *trans, int nr) ret = __btrfs_commit_inode_delayed_items(trans, path, curr_node); if (ret) { - btrfs_release_delayed_node(curr_node); - curr_node = NULL; btrfs_abort_transaction(trans, ret); break; } prev_node = curr_node; curr_node = btrfs_next_delayed_node(curr_node); + /* + * See the comment below about releasing path before releasing + * node. If the commit of delayed items was successful the path + * should always be released, but in case of an error, it may + * point to locked extent buffers (a leaf at the very least). + */ + ASSERT(path->nodes[0] == NULL); btrfs_release_delayed_node(prev_node); } + /* + * Release the path to avoid a potential deadlock and lockdep splat when + * releasing the delayed node, as that requires taking the delayed node's + * mutex. If another task starts running delayed items before we take + * the mutex, it will first lock the mutex and then it may try to lock + * the same btree path (leaf). + */ + btrfs_free_path(path); + if (curr_node) btrfs_release_delayed_node(curr_node); - btrfs_free_path(path); trans->block_rsv = block_rsv; return ret; diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 98f87cc47433262ffc34257b570d9ae31bc58c4e..437ca4691967d5796cb9f855bdb3215deac54680 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -4348,7 +4348,11 @@ static void btrfs_destroy_delalloc_inodes(struct btrfs_root *root) */ inode = igrab(&btrfs_inode->vfs_inode); if (inode) { + unsigned int nofs_flag; + + nofs_flag = memalloc_nofs_save(); invalidate_inode_pages2(inode->i_mapping); + memalloc_nofs_restore(nofs_flag); iput(inode); } spin_lock(&root->delalloc_lock); @@ -4466,7 +4470,12 @@ static void btrfs_cleanup_bg_io(struct btrfs_block_group_cache *cache) inode = cache->io_ctl.inode; if (inode) { + unsigned int nofs_flag; + + nofs_flag = memalloc_nofs_save(); invalidate_inode_pages2(inode->i_mapping); + memalloc_nofs_restore(nofs_flag); + BTRFS_I(inode)->generation = 0; cache->io_ctl.inode = NULL; iput(inode); diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c index d71f800e8bf6078fdca4a73b3170c1cdf493ccd2..902ab00bfd7ab931602cbf1864133469f4abefee 100644 --- a/fs/btrfs/extent-tree.c +++ b/fs/btrfs/extent-tree.c @@ -1549,6 +1549,11 @@ int lookup_inline_extent_backref(struct btrfs_trans_handle *trans, err = -ENOENT; goto out; } else if (WARN_ON(ret)) { + btrfs_print_leaf(path->nodes[0]); + btrfs_err(fs_info, +"extent item not found for insert, bytenr %llu num_bytes %llu parent %llu root_objectid %llu owner %llu offset %llu", + bytenr, num_bytes, parent, root_objectid, owner, + offset); err = -EIO; goto out; } @@ -2322,12 +2327,12 @@ static int run_delayed_tree_ref(struct btrfs_trans_handle *trans, parent = ref->parent; ref_root = ref->root; - if (node->ref_mod != 1) { + if (unlikely(node->ref_mod != 1)) { btrfs_err(trans->fs_info, - "btree block(%llu) has %d references rather than 1: action %d ref_root %llu parent %llu", + "btree block %llu has %d references rather than 1: action %d ref_root %llu parent %llu", node->bytenr, node->ref_mod, node->action, ref_root, parent); - return -EIO; + return -EUCLEAN; } if (node->action == BTRFS_ADD_DELAYED_REF && insert_reserved) { BUG_ON(!extent_op || !extent_op->update_flags); diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c index dabf153843e90a18398513d04e6918c45f8950a6..504d63fb81fa1889b7e37c2e416a012e989eced0 100644 --- a/fs/btrfs/extent_io.c +++ b/fs/btrfs/extent_io.c @@ -3928,11 +3928,12 @@ int btree_write_cache_pages(struct address_space *mapping, free_extent_buffer(eb); /* - * the filesystem may choose to bump up nr_to_write. + * The filesystem may choose to bump up nr_to_write. * We have to make sure to honor the new nr_to_write - * at any time + * at any time. */ - nr_to_write_done = wbc->nr_to_write <= 0; + nr_to_write_done = (wbc->sync_mode == WB_SYNC_NONE && + wbc->nr_to_write <= 0); } pagevec_release(&pvec); cond_resched(); diff --git a/fs/btrfs/free-space-cache.c b/fs/btrfs/free-space-cache.c index 6511cb71986c926cf9d637d8901d1000fd495788..b623e9f3b4c49eed2e38e4309506ade8f3b42144 100644 --- a/fs/btrfs/free-space-cache.c +++ b/fs/btrfs/free-space-cache.c @@ -783,15 +783,16 @@ static int __load_free_space_cache(struct btrfs_root *root, struct inode *inode, } spin_lock(&ctl->tree_lock); ret = link_free_space(ctl, e); - ctl->total_bitmaps++; - ctl->op->recalc_thresholds(ctl); - spin_unlock(&ctl->tree_lock); if (ret) { + spin_unlock(&ctl->tree_lock); btrfs_err(fs_info, "Duplicate entries in free space cache, dumping"); kmem_cache_free(btrfs_free_space_cachep, e); goto free_cache; } + ctl->total_bitmaps++; + ctl->op->recalc_thresholds(ctl); + spin_unlock(&ctl->tree_lock); list_add_tail(&e->list, &bitmaps); } diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c index f314b2c2d14870c436965725497dcf03953fd83c..e4a4074ef33dab1a9b45aa3d46afad24261e84f7 100644 --- a/fs/btrfs/inode.c +++ b/fs/btrfs/inode.c @@ -6620,7 +6620,7 @@ static int btrfs_mknod(struct inode *dir, struct dentry *dentry, if (IS_ERR(trans)) return PTR_ERR(trans); - err = btrfs_find_free_ino(root, &objectid); + err = btrfs_find_free_objectid(root, &objectid); if (err) goto out_unlock; @@ -6684,7 +6684,7 @@ static int btrfs_create(struct inode *dir, struct dentry *dentry, if (IS_ERR(trans)) return PTR_ERR(trans); - err = btrfs_find_free_ino(root, &objectid); + err = btrfs_find_free_objectid(root, &objectid); if (err) goto out_unlock; @@ -6837,7 +6837,7 @@ static int btrfs_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) if (IS_ERR(trans)) return PTR_ERR(trans); - err = btrfs_find_free_ino(root, &objectid); + err = btrfs_find_free_objectid(root, &objectid); if (err) goto out_fail; @@ -9819,7 +9819,7 @@ static int btrfs_whiteout_for_rename(struct btrfs_trans_handle *trans, u64 objectid; u64 index; - ret = btrfs_find_free_ino(root, &objectid); + ret = btrfs_find_free_objectid(root, &objectid); if (ret) return ret; @@ -10316,7 +10316,7 @@ static int btrfs_symlink(struct inode *dir, struct dentry *dentry, if (IS_ERR(trans)) return PTR_ERR(trans); - err = btrfs_find_free_ino(root, &objectid); + err = btrfs_find_free_objectid(root, &objectid); if (err) goto out_unlock; @@ -10600,7 +10600,7 @@ static int btrfs_tmpfile(struct inode *dir, struct dentry *dentry, umode_t mode) if (IS_ERR(trans)) return PTR_ERR(trans); - ret = btrfs_find_free_ino(root, &objectid); + ret = btrfs_find_free_objectid(root, &objectid); if (ret) goto out; diff --git a/fs/btrfs/ioctl.c b/fs/btrfs/ioctl.c index 4f25133885676be0b916e993f9709b1f83722c75..23beabb4892312c6561b02ef5b8c5b4a0b49ac40 100644 --- a/fs/btrfs/ioctl.c +++ b/fs/btrfs/ioctl.c @@ -2045,7 +2045,7 @@ static noinline int key_in_sk(struct btrfs_key *key, static noinline int copy_to_sk(struct btrfs_path *path, struct btrfs_key *key, struct btrfs_ioctl_search_key *sk, - size_t *buf_size, + u64 *buf_size, char __user *ubuf, unsigned long *sk_offset, int *num_found) @@ -2177,7 +2177,7 @@ static noinline int copy_to_sk(struct btrfs_path *path, static noinline int search_ioctl(struct inode *inode, struct btrfs_ioctl_search_key *sk, - size_t *buf_size, + u64 *buf_size, char __user *ubuf) { struct btrfs_fs_info *info = btrfs_sb(inode->i_sb); @@ -2249,7 +2249,7 @@ static noinline int btrfs_ioctl_tree_search(struct file *file, struct btrfs_ioctl_search_key sk; struct inode *inode; int ret; - size_t buf_size; + u64 buf_size; if (!capable(CAP_SYS_ADMIN)) return -EPERM; @@ -2283,8 +2283,8 @@ static noinline int btrfs_ioctl_tree_search_v2(struct file *file, struct btrfs_ioctl_search_args_v2 args; struct inode *inode; int ret; - size_t buf_size; - const size_t buf_limit = SZ_16M; + u64 buf_size; + const u64 buf_limit = SZ_16M; if (!capable(CAP_SYS_ADMIN)) return -EPERM; @@ -4526,7 +4526,7 @@ static void get_block_group_info(struct list_head *groups_list, static long btrfs_ioctl_space_info(struct btrfs_fs_info *fs_info, void __user *arg) { - struct btrfs_ioctl_space_args space_args; + struct btrfs_ioctl_space_args space_args = { 0 }; struct btrfs_ioctl_space_info space; struct btrfs_ioctl_space_info *dest; struct btrfs_ioctl_space_info *dest_orig; @@ -4722,6 +4722,11 @@ static long btrfs_ioctl_scrub(struct file *file, void __user *arg) if (IS_ERR(sa)) return PTR_ERR(sa); + if (sa->flags & ~BTRFS_SCRUB_SUPPORTED_FLAGS) { + ret = -EOPNOTSUPP; + goto out; + } + if (!(sa->flags & BTRFS_SCRUB_READONLY)) { ret = mnt_want_write_file(file); if (ret) @@ -5879,7 +5884,7 @@ static int _btrfs_ioctl_send(struct file *file, void __user *argp, bool compat) if (compat) { #if defined(CONFIG_64BIT) && defined(CONFIG_COMPAT) - struct btrfs_ioctl_send_args_32 args32; + struct btrfs_ioctl_send_args_32 args32 = { 0 }; ret = copy_from_user(&args32, argp, sizeof(args32)); if (ret) diff --git a/fs/btrfs/print-tree.c b/fs/btrfs/print-tree.c index 4b217e9a581ce63359c66a529830ad31a930a18d..e3de0c4ecbfc049c626eaf493abdd36b8c335a9b 100644 --- a/fs/btrfs/print-tree.c +++ b/fs/btrfs/print-tree.c @@ -109,10 +109,10 @@ static void print_extent_item(struct extent_buffer *eb, int slot, int type) pr_cont("shared data backref parent %llu count %u\n", offset, btrfs_shared_data_ref_count(eb, sref)); /* - * offset is supposed to be a tree block which - * must be aligned to nodesize. + * Offset is supposed to be a tree block which must be + * aligned to sectorsize. */ - if (!IS_ALIGNED(offset, eb->fs_info->nodesize)) + if (!IS_ALIGNED(offset, eb->fs_info->sectorsize)) pr_info( "\t\t\t(parent %llu not aligned to sectorsize %u)\n", offset, eb->fs_info->sectorsize); diff --git a/fs/btrfs/qgroup.c b/fs/btrfs/qgroup.c index 69b43df186a8977220186d75ee6e8f0e04fc997e..ef95525fa6cdfec5eef487a3010fc4f4d00f0839 100644 --- a/fs/btrfs/qgroup.c +++ b/fs/btrfs/qgroup.c @@ -1115,7 +1115,9 @@ int btrfs_quota_disable(struct btrfs_fs_info *fs_info) goto end_trans; } + spin_lock(&fs_info->trans_lock); list_del("a_root->dirty_list); + spin_unlock(&fs_info->trans_lock); btrfs_tree_lock(quota_root->node); clean_tree_block(fs_info, quota_root->node); diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c index 06c6a66a991f26fcd1ba5e47ff38a960d2f1149d..3b9318a3d421b28a4f56e132f03028557d0a8aee 100644 --- a/fs/btrfs/relocation.c +++ b/fs/btrfs/relocation.c @@ -2341,7 +2341,7 @@ int prepare_to_merge(struct reloc_control *rc, int err) list_splice(&reloc_roots, &rc->reloc_roots); if (!err) - btrfs_commit_transaction(trans); + err = btrfs_commit_transaction(trans); else btrfs_end_transaction(trans); return err; @@ -3930,8 +3930,12 @@ int prepare_to_relocate(struct reloc_control *rc) */ return PTR_ERR(trans); } - btrfs_commit_transaction(trans); - return 0; + + ret = btrfs_commit_transaction(trans); + if (ret) + unset_reloc_control(rc); + + return ret; } static noinline_for_stack int relocate_block_group(struct reloc_control *rc) @@ -4097,7 +4101,9 @@ static noinline_for_stack int relocate_block_group(struct reloc_control *rc) err = PTR_ERR(trans); goto out_free; } - btrfs_commit_transaction(trans); + ret = btrfs_commit_transaction(trans); + if (ret && !err) + err = ret; out_free: btrfs_free_block_rsv(fs_info, rc->block_rsv); btrfs_free_path(path); diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c index 521f6c2091ad15e20e18fdac0a66bd2552d56f44..a595439518519a57095ee138e60a9ea903a9895e 100644 --- a/fs/btrfs/super.c +++ b/fs/btrfs/super.c @@ -2196,7 +2196,7 @@ static int btrfs_statfs(struct dentry *dentry, struct kstatfs *buf) * calculated f_bavail. */ if (!mixed && block_rsv->space_info->full && - total_free_meta - thresh < block_rsv->size) + (total_free_meta < thresh || total_free_meta - thresh < block_rsv->size)) buf->f_bavail = 0; buf->f_type = BTRFS_SUPER_MAGIC; diff --git a/fs/btrfs/transaction.c b/fs/btrfs/transaction.c index 049535115c9dc1e924859342fd14b2454225db51..a34c0436ebb1dcf065c31578326623a04f0fc5dc 100644 --- a/fs/btrfs/transaction.c +++ b/fs/btrfs/transaction.c @@ -200,10 +200,11 @@ static noinline int join_transaction(struct btrfs_fs_info *fs_info, spin_unlock(&fs_info->trans_lock); /* - * If we are ATTACH, we just want to catch the current transaction, - * and commit it. If there is no transaction, just return ENOENT. + * If we are ATTACH or TRANS_JOIN_NOSTART, we just want to catch the + * current transaction, and commit it. If there is no transaction, just + * return ENOENT. */ - if (type == TRANS_ATTACH) + if (type == TRANS_ATTACH || type == TRANS_JOIN_NOSTART) return -ENOENT; /* @@ -703,8 +704,13 @@ btrfs_attach_transaction_barrier(struct btrfs_root *root) trans = start_transaction(root, 0, TRANS_ATTACH, BTRFS_RESERVE_NO_FLUSH, true); - if (trans == ERR_PTR(-ENOENT)) - btrfs_wait_for_commit(root->fs_info, 0); + if (trans == ERR_PTR(-ENOENT)) { + int ret; + + ret = btrfs_wait_for_commit(root->fs_info, 0); + if (ret) + return ERR_PTR(ret); + } return trans; } diff --git a/fs/btrfs/tree-log.c b/fs/btrfs/tree-log.c index 0fe32c567ed74c1f8bd6a69f786081e3d8781962..23ec766eeb0a376629185e43094a03f9d25c0eb1 100644 --- a/fs/btrfs/tree-log.c +++ b/fs/btrfs/tree-log.c @@ -4236,7 +4236,7 @@ static int btrfs_log_prealloc_extents(struct btrfs_trans_handle *trans, struct extent_buffer *leaf; int slot; int ins_nr = 0; - int start_slot; + int start_slot = 0; int ret; if (!(inode->flags & BTRFS_INODE_PREALLOC)) diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c index 0294f519c29ee02534ffca4fc40ec97b31da4128..b69d6f7012f440ed2aae394815048d3e48ad4e8d 100644 --- a/fs/btrfs/volumes.c +++ b/fs/btrfs/volumes.c @@ -4106,8 +4106,7 @@ int btrfs_cancel_balance(struct btrfs_fs_info *fs_info) } } - BUG_ON(fs_info->balance_ctl || - test_bit(BTRFS_FS_BALANCE_RUNNING, &fs_info->flags)); + ASSERT(!test_bit(BTRFS_FS_BALANCE_RUNNING, &fs_info->flags)); atomic_dec(&fs_info->balance_cancel_req); mutex_unlock(&fs_info->balance_mutex); return 0; diff --git a/fs/ceph/caps.c b/fs/ceph/caps.c index 6443ba1e60eb425260fc10fe5dd7cb21daba809c..fcfba2af5f98a50d6ace64a8b63b6c0b04c779d6 100644 --- a/fs/ceph/caps.c +++ b/fs/ceph/caps.c @@ -1554,6 +1554,7 @@ void ceph_flush_snaps(struct ceph_inode_info *ci, struct inode *inode = &ci->vfs_inode; struct ceph_mds_client *mdsc = ceph_inode_to_client(inode)->mdsc; struct ceph_mds_session *session = NULL; + bool need_put = false; int mds; dout("ceph_flush_snaps %p\n", inode); @@ -1607,8 +1608,13 @@ void ceph_flush_snaps(struct ceph_inode_info *ci, } /* we flushed them all; remove this inode from the queue */ spin_lock(&mdsc->snap_flush_lock); + if (!list_empty(&ci->i_snap_flush_item)) + need_put = true; list_del_init(&ci->i_snap_flush_item); spin_unlock(&mdsc->snap_flush_lock); + + if (need_put) + iput(inode); } /* @@ -3279,6 +3285,15 @@ static void handle_cap_grant(struct inode *inode, } BUG_ON(cap->issued & ~cap->implemented); + /* don't let check_caps skip sending a response to MDS for revoke msgs */ + if (le32_to_cpu(grant->op) == CEPH_CAP_OP_REVOKE) { + cap->mds_wanted = 0; + if (cap == ci->i_auth_cap) + check_caps = 1; /* check auth cap only */ + else + check_caps = 2; /* check all caps */ + } + if (extra_info->inline_version > 0 && extra_info->inline_version >= ci->i_inline_version) { ci->i_inline_version = extra_info->inline_version; diff --git a/fs/ceph/inode.c b/fs/ceph/inode.c index 5f041fede7aa93075926c2c90e5e93f2e536f58e..d6f181e3c1acd0446edcc977293ea14c4a6077aa 100644 --- a/fs/ceph/inode.c +++ b/fs/ceph/inode.c @@ -631,9 +631,7 @@ int ceph_fill_file_size(struct inode *inode, int issued, ci->i_truncate_seq = truncate_seq; /* the MDS should have revoked these caps */ - WARN_ON_ONCE(issued & (CEPH_CAP_FILE_EXCL | - CEPH_CAP_FILE_RD | - CEPH_CAP_FILE_WR | + WARN_ON_ONCE(issued & (CEPH_CAP_FILE_RD | CEPH_CAP_FILE_LAZYIO)); /* * If we hold relevant caps, or in the case where we're diff --git a/fs/ceph/snap.c b/fs/ceph/snap.c index a5ef8275440d59c2a40c281708713b4157d5b998..4f727f2c98db9efed99cf8c94cdaa47d0f1adc69 100644 --- a/fs/ceph/snap.c +++ b/fs/ceph/snap.c @@ -623,8 +623,10 @@ int __ceph_finish_cap_snap(struct ceph_inode_info *ci, capsnap->size); spin_lock(&mdsc->snap_flush_lock); - if (list_empty(&ci->i_snap_flush_item)) + if (list_empty(&ci->i_snap_flush_item)) { + ihold(inode); list_add_tail(&ci->i_snap_flush_item, &mdsc->snap_flush_list); + } spin_unlock(&mdsc->snap_flush_lock); return 1; /* caller may want to ceph_flush_snaps */ } @@ -976,6 +978,19 @@ void ceph_handle_snap(struct ceph_mds_client *mdsc, continue; adjust_snap_realm_parent(mdsc, child, realm->ino); } + } else { + /* + * In the non-split case both 'num_split_inos' and + * 'num_split_realms' should be 0, making this a no-op. + * However the MDS happens to populate 'split_realms' list + * in one of the UPDATE op cases by mistake. + * + * Skip both lists just in case to ensure that 'p' is + * positioned at the start of realm info, as expected by + * ceph_update_snap_trace(). + */ + p += sizeof(u64) * num_split_inos; + p += sizeof(u64) * num_split_realms; } /* diff --git a/fs/cifs/cifs_spnego.c b/fs/cifs/cifs_spnego.c index 7f01c6e607918d4e1356a9e7d305113777910089..6eb65988321fc465f9e2ae36c6c1e985740c5515 100644 --- a/fs/cifs/cifs_spnego.c +++ b/fs/cifs/cifs_spnego.c @@ -76,8 +76,8 @@ struct key_type cifs_spnego_key_type = { * strlen(";sec=ntlmsspi") */ #define MAX_MECH_STR_LEN 13 -/* strlen of "host=" */ -#define HOST_KEY_LEN 5 +/* strlen of ";host=" */ +#define HOST_KEY_LEN 6 /* strlen of ";ip4=" or ";ip6=" */ #define IP_KEY_LEN 5 diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c index 52b1524b40cdce172ebd3e0c6bb7c905020d4f92..ef1a43f4bd663ed43a088eb145570ce50ea2fc5a 100644 --- a/fs/cifs/cifsfs.c +++ b/fs/cifs/cifsfs.c @@ -663,11 +663,6 @@ cifs_get_root(struct smb_vol *vol, struct super_block *sb) struct inode *dir = d_inode(dentry); struct dentry *child; - if (!dir) { - dput(dentry); - dentry = ERR_PTR(-ENOENT); - break; - } if (!S_ISDIR(dir->i_mode)) { dput(dentry); dentry = ERR_PTR(-ENOTDIR); @@ -684,7 +679,7 @@ cifs_get_root(struct smb_vol *vol, struct super_block *sb) while (*s && *s != sep) s++; - child = lookup_one_len_unlocked(p, dentry, s - p); + child = lookup_positive_unlocked(p, dentry, s - p); dput(dentry); dentry = child; } while (!IS_ERR(dentry)); diff --git a/fs/cifs/cifsfs.h b/fs/cifs/cifsfs.h index f047e87871a1c83a5c35106c8d99fe6358c8d79b..c1d5daa4b351d24992fb381fc71a946819b8cca8 100644 --- a/fs/cifs/cifsfs.h +++ b/fs/cifs/cifsfs.h @@ -121,7 +121,10 @@ extern const struct dentry_operations cifs_ci_dentry_ops; #ifdef CONFIG_CIFS_DFS_UPCALL extern struct vfsmount *cifs_dfs_d_automount(struct path *path); #else -#define cifs_dfs_d_automount NULL +static inline struct vfsmount *cifs_dfs_d_automount(struct path *path) +{ + return ERR_PTR(-EREMOTE); +} #endif /* Functions related to symlinks */ diff --git a/fs/cifs/cifssmb.c b/fs/cifs/cifssmb.c index cb70f0c6aa1b756712d7bfcf8b554f8a36c7357c..d16fd8d1f291f3b144a5fa98b4e6891562091e8c 100644 --- a/fs/cifs/cifssmb.c +++ b/fs/cifs/cifssmb.c @@ -4895,8 +4895,13 @@ CIFSGetDFSRefer(const unsigned int xid, struct cifs_ses *ses, return -ENODEV; getDFSRetry: - rc = smb_init(SMB_COM_TRANSACTION2, 15, ses->tcon_ipc, (void **) &pSMB, - (void **) &pSMBr); + /* + * Use smb_init_no_reconnect() instead of smb_init() as + * CIFSGetDFSRefer() may be called from cifs_reconnect_tcon() and thus + * causing an infinite recursion. + */ + rc = smb_init_no_reconnect(SMB_COM_TRANSACTION2, 15, ses->tcon_ipc, + (void **)&pSMB, (void **)&pSMBr); if (rc) return rc; diff --git a/fs/cifs/file.c b/fs/cifs/file.c index 7b482489bd227984735ca4a05253243e71fd8d7f..0613b86cc3fd0aba5e464266ae0f0081c2da21b1 100644 --- a/fs/cifs/file.c +++ b/fs/cifs/file.c @@ -3991,9 +3991,9 @@ static int cifs_readpage_worker(struct file *file, struct page *page, io_error: kunmap(page); - unlock_page(page); read_complete: + unlock_page(page); return rc; } diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c index f906984eb25b0c00023e8ab36e1b0ed5b60dfaf0..01ab4496cb897d8a0fb6d831c01cb4bf360702df 100644 --- a/fs/cifs/smb2ops.c +++ b/fs/cifs/smb2ops.c @@ -79,6 +79,7 @@ smb2_add_credits(struct TCP_Server_Info *server, const unsigned int add, *val = 65000; /* Don't get near 64K credits, avoid srv bugs */ printk_once(KERN_WARNING "server overflowed SMB3 credits\n"); } + WARN_ON_ONCE(server->in_flight == 0); server->in_flight--; if (server->in_flight == 0 && (optype & CIFS_OP_MASK) != CIFS_NEG_OP) rc = change_conf(server); @@ -475,7 +476,7 @@ SMB3_request_interfaces(const unsigned int xid, struct cifs_tcon *tcon) if (rc == -EOPNOTSUPP) { cifs_dbg(FYI, "server does not support query network interfaces\n"); - goto out; + ret_data_len = 0; } else if (rc != 0) { cifs_dbg(VFS, "error %d on ioctl to get interface list\n", rc); goto out; @@ -1180,7 +1181,7 @@ smb2_copychunk_range(const unsigned int xid, pcchunk->SourceOffset = cpu_to_le64(src_off); pcchunk->TargetOffset = cpu_to_le64(dest_off); pcchunk->Length = - cpu_to_le32(min_t(u32, len, tcon->max_bytes_chunk)); + cpu_to_le32(min_t(u64, len, tcon->max_bytes_chunk)); /* Request server copy to target from src identified by key */ kfree(retbuf); diff --git a/fs/cifs/smbdirect.c b/fs/cifs/smbdirect.c index 591cd5c7043234f063754946f787df682c82c25e..117dc475bea814ff53d5058dc3d8a39b6cd6ddfc 100644 --- a/fs/cifs/smbdirect.c +++ b/fs/cifs/smbdirect.c @@ -706,8 +706,13 @@ static struct rdma_cm_id *smbd_create_id( log_rdma_event(ERR, "rdma_resolve_addr() failed %i\n", rc); goto out; } - wait_for_completion_interruptible_timeout( + rc = wait_for_completion_interruptible_timeout( &info->ri_done, msecs_to_jiffies(RDMA_RESOLVE_TIMEOUT)); + /* e.g. if interrupted returns -ERESTARTSYS */ + if (rc < 0) { + log_rdma_event(ERR, "rdma_resolve_addr timeout rc: %i\n", rc); + goto out; + } rc = info->ri_rc; if (rc) { log_rdma_event(ERR, "rdma_resolve_addr() completed %i\n", rc); @@ -720,8 +725,13 @@ static struct rdma_cm_id *smbd_create_id( log_rdma_event(ERR, "rdma_resolve_route() failed %i\n", rc); goto out; } - wait_for_completion_interruptible_timeout( + rc = wait_for_completion_interruptible_timeout( &info->ri_done, msecs_to_jiffies(RDMA_RESOLVE_TIMEOUT)); + /* e.g. if interrupted returns -ERESTARTSYS */ + if (rc < 0) { + log_rdma_event(ERR, "rdma_resolve_addr timeout rc: %i\n", rc); + goto out; + } rc = info->ri_rc; if (rc) { log_rdma_event(ERR, "rdma_resolve_route() completed %i\n", rc); @@ -1887,6 +1897,7 @@ static struct smbd_connection *_smbd_get_connection( allocate_mr_failed: /* At this point, need to a full transport shutdown */ + server->smbd_conn = info; smbd_destroy(server); return NULL; @@ -2453,6 +2464,7 @@ static int allocate_mr_list(struct smbd_connection *info) atomic_set(&info->mr_ready_count, 0); atomic_set(&info->mr_used_count, 0); init_waitqueue_head(&info->wait_for_mr_cleanup); + INIT_WORK(&info->mr_recovery_work, smbd_mr_recovery_work); /* Allocate more MRs (2x) than hardware responder_resources */ for (i = 0; i < info->responder_resources * 2; i++) { smbdirect_mr = kzalloc(sizeof(*smbdirect_mr), GFP_KERNEL); @@ -2481,13 +2493,13 @@ static int allocate_mr_list(struct smbd_connection *info) list_add_tail(&smbdirect_mr->list, &info->mr_list); atomic_inc(&info->mr_ready_count); } - INIT_WORK(&info->mr_recovery_work, smbd_mr_recovery_work); return 0; out: kfree(smbdirect_mr); list_for_each_entry_safe(smbdirect_mr, tmp, &info->mr_list, list) { + list_del(&smbdirect_mr->list); ib_dereg_mr(smbdirect_mr->mr); kfree(smbdirect_mr->sgl); kfree(smbdirect_mr); diff --git a/fs/crypto/policy.c b/fs/crypto/policy.c index c7a67f5d9a9fed1717eb2fa93d5490bb568a988b..9d836592e41e2fb91a099c8ccb9c7c7b70e4b748 100644 --- a/fs/crypto/policy.c +++ b/fs/crypto/policy.c @@ -645,12 +645,13 @@ EXPORT_SYMBOL(fscrypt_has_permitted_context); #define SDHCI "sdhci" -static int fscrypt_update_context(union fscrypt_context *ctx) +static int fscrypt_update_context(union fscrypt_context *ctx, + const char *file_system_type) { char *boot = "ufs"; if (!fscrypt_find_storage_type(&boot)) { - if (!strcmp(boot, SDHCI)) + if (!strcmp(boot, SDHCI) && !strcmp(file_system_type, "f2fs")) ctx->v1.flags |= FSCRYPT_POLICY_FLAG_IV_INO_LBLK_32; return 0; } @@ -673,6 +674,7 @@ int fscrypt_inherit_context(struct inode *parent, struct inode *child, int ctxsize; struct fscrypt_info *ci; int res; + const char *file_system_type; res = fscrypt_get_encryption_info(parent); if (res < 0) @@ -682,10 +684,14 @@ int fscrypt_inherit_context(struct inode *parent, struct inode *child, if (ci == NULL) return -ENOKEY; + file_system_type = ci->ci_inode->i_sb->s_type->name; + if (!file_system_type) + return -EINVAL; + ctxsize = fscrypt_new_context_from_policy(&ctx, &ci->ci_policy); if (fscrypt_policy_contents_mode(&ci->ci_policy) == FSCRYPT_MODE_PRIVATE) { - res = fscrypt_update_context(&ctx); + res = fscrypt_update_context(&ctx, file_system_type); if (res) return res; } diff --git a/fs/debugfs/file.c b/fs/debugfs/file.c index a57d080d2ba57e3b8c4fa0f34c56b01eef279678..acdc802bfe9a831a4a33630bc516ad74cb7cdfb4 100644 --- a/fs/debugfs/file.c +++ b/fs/debugfs/file.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include "internal.h" @@ -1084,7 +1085,14 @@ static int debugfs_show_regset32(struct seq_file *s, void *data) { struct debugfs_regset32 *regset = s->private; + if (regset->dev) + pm_runtime_get_sync(regset->dev); + debugfs_print_regs32(s, regset->regs, regset->nregs, regset->base, ""); + + if (regset->dev) + pm_runtime_put(regset->dev); + return 0; } diff --git a/fs/debugfs/inode.c b/fs/debugfs/inode.c index 4661ecaf6741cc3e863942e9f643a89cb5f45102..1e4ae78f64a8f3f30024e6c8250b6817e6f33979 100644 --- a/fs/debugfs/inode.c +++ b/fs/debugfs/inode.c @@ -275,13 +275,9 @@ struct dentry *debugfs_lookup(const char *name, struct dentry *parent) if (!parent) parent = debugfs_mount->mnt_root; - dentry = lookup_one_len_unlocked(name, parent, strlen(name)); + dentry = lookup_positive_unlocked(name, parent, strlen(name)); if (IS_ERR(dentry)) return NULL; - if (!d_really_is_positive(dentry)) { - dput(dentry); - return NULL; - } return dentry; } EXPORT_SYMBOL_GPL(debugfs_lookup); diff --git a/fs/dlm/lock.c b/fs/dlm/lock.c index d4e204473e76b5c2dfb2d0ee8081e832ebf09f80..0864481d8551cefb457561b81186348522444ae6 100644 --- a/fs/dlm/lock.c +++ b/fs/dlm/lock.c @@ -1858,7 +1858,7 @@ static void del_timeout(struct dlm_lkb *lkb) void dlm_scan_timeout(struct dlm_ls *ls) { struct dlm_rsb *r; - struct dlm_lkb *lkb; + struct dlm_lkb *lkb = NULL, *iter; int do_cancel, do_warn; s64 wait_us; @@ -1869,27 +1869,28 @@ void dlm_scan_timeout(struct dlm_ls *ls) do_cancel = 0; do_warn = 0; mutex_lock(&ls->ls_timeout_mutex); - list_for_each_entry(lkb, &ls->ls_timeout, lkb_time_list) { + list_for_each_entry(iter, &ls->ls_timeout, lkb_time_list) { wait_us = ktime_to_us(ktime_sub(ktime_get(), - lkb->lkb_timestamp)); + iter->lkb_timestamp)); - if ((lkb->lkb_exflags & DLM_LKF_TIMEOUT) && - wait_us >= (lkb->lkb_timeout_cs * 10000)) + if ((iter->lkb_exflags & DLM_LKF_TIMEOUT) && + wait_us >= (iter->lkb_timeout_cs * 10000)) do_cancel = 1; - if ((lkb->lkb_flags & DLM_IFL_WATCH_TIMEWARN) && + if ((iter->lkb_flags & DLM_IFL_WATCH_TIMEWARN) && wait_us >= dlm_config.ci_timewarn_cs * 10000) do_warn = 1; if (!do_cancel && !do_warn) continue; - hold_lkb(lkb); + hold_lkb(iter); + lkb = iter; break; } mutex_unlock(&ls->ls_timeout_mutex); - if (!do_cancel && !do_warn) + if (!lkb) break; r = lkb->lkb_resource; @@ -5243,21 +5244,18 @@ void dlm_recover_waiters_pre(struct dlm_ls *ls) static struct dlm_lkb *find_resend_waiter(struct dlm_ls *ls) { - struct dlm_lkb *lkb; - int found = 0; + struct dlm_lkb *lkb = NULL, *iter; mutex_lock(&ls->ls_waiters_mutex); - list_for_each_entry(lkb, &ls->ls_waiters, lkb_wait_reply) { - if (lkb->lkb_flags & DLM_IFL_RESEND) { - hold_lkb(lkb); - found = 1; + list_for_each_entry(iter, &ls->ls_waiters, lkb_wait_reply) { + if (iter->lkb_flags & DLM_IFL_RESEND) { + hold_lkb(iter); + lkb = iter; break; } } mutex_unlock(&ls->ls_waiters_mutex); - if (!found) - lkb = NULL; return lkb; } @@ -5916,37 +5914,36 @@ int dlm_user_adopt_orphan(struct dlm_ls *ls, struct dlm_user_args *ua_tmp, int mode, uint32_t flags, void *name, unsigned int namelen, unsigned long timeout_cs, uint32_t *lkid) { - struct dlm_lkb *lkb; + struct dlm_lkb *lkb = NULL, *iter; struct dlm_user_args *ua; int found_other_mode = 0; - int found = 0; int rv = 0; mutex_lock(&ls->ls_orphans_mutex); - list_for_each_entry(lkb, &ls->ls_orphans, lkb_ownqueue) { - if (lkb->lkb_resource->res_length != namelen) + list_for_each_entry(iter, &ls->ls_orphans, lkb_ownqueue) { + if (iter->lkb_resource->res_length != namelen) continue; - if (memcmp(lkb->lkb_resource->res_name, name, namelen)) + if (memcmp(iter->lkb_resource->res_name, name, namelen)) continue; - if (lkb->lkb_grmode != mode) { + if (iter->lkb_grmode != mode) { found_other_mode = 1; continue; } - found = 1; - list_del_init(&lkb->lkb_ownqueue); - lkb->lkb_flags &= ~DLM_IFL_ORPHAN; - *lkid = lkb->lkb_id; + lkb = iter; + list_del_init(&iter->lkb_ownqueue); + iter->lkb_flags &= ~DLM_IFL_ORPHAN; + *lkid = iter->lkb_id; break; } mutex_unlock(&ls->ls_orphans_mutex); - if (!found && found_other_mode) { + if (!lkb && found_other_mode) { rv = -EAGAIN; goto out; } - if (!found) { + if (!lkb) { rv = -ENOENT; goto out; } diff --git a/fs/dlm/netlink.c b/fs/dlm/netlink.c index 43a96c330570d68c6b12b6c4701afad30144312b..ea50f59610e523afdcd9d598e5310d4c076e27b7 100644 --- a/fs/dlm/netlink.c +++ b/fs/dlm/netlink.c @@ -115,7 +115,7 @@ static void fill_data(struct dlm_lock_data *data, struct dlm_lkb *lkb) void dlm_timeout_warn(struct dlm_lkb *lkb) { - struct sk_buff *uninitialized_var(send_skb); + struct sk_buff *send_skb; struct dlm_lock_data *data; size_t size; int rv; diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c index e0c05e08d8bfe2739c3a38ee08106e90fc7b82b2..c6079f6c6a798f7088adac06d9695979d08791e2 100644 --- a/fs/dlm/plock.c +++ b/fs/dlm/plock.c @@ -22,20 +22,20 @@ static struct list_head recv_list; static wait_queue_head_t send_wq; static wait_queue_head_t recv_wq; -struct plock_op { - struct list_head list; - int done; - struct dlm_plock_info info; - int (*callback)(struct file_lock *fl, int result); -}; - -struct plock_xop { - struct plock_op xop; +struct plock_async_data { void *fl; void *file; struct file_lock flc; + int (*callback)(struct file_lock *fl, int result); }; +struct plock_op { + struct list_head list; + int done; + struct dlm_plock_info info; + /* if set indicates async handling */ + struct plock_async_data *data; +}; static inline void set_version(struct dlm_plock_info *info) { @@ -61,6 +61,12 @@ static int check_version(struct dlm_plock_info *info) return 0; } +static void dlm_release_plock_op(struct plock_op *op) +{ + kfree(op->data); + kfree(op); +} + static void send_op(struct plock_op *op) { set_version(&op->info); @@ -77,8 +83,7 @@ static void send_op(struct plock_op *op) abandoned waiter. So, we have to insert the unlock-close when the lock call is interrupted. */ -static void do_unlock_close(struct dlm_ls *ls, u64 number, - struct file *file, struct file_lock *fl) +static void do_unlock_close(const struct dlm_plock_info *info) { struct plock_op *op; @@ -87,15 +92,12 @@ static void do_unlock_close(struct dlm_ls *ls, u64 number, return; op->info.optype = DLM_PLOCK_OP_UNLOCK; - op->info.pid = fl->fl_pid; - op->info.fsid = ls->ls_global_id; - op->info.number = number; + op->info.pid = info->pid; + op->info.fsid = info->fsid; + op->info.number = info->number; op->info.start = 0; op->info.end = OFFSET_MAX; - if (fl->fl_lmops && fl->fl_lmops->lm_grant) - op->info.owner = (__u64) fl->fl_pid; - else - op->info.owner = (__u64)(long) fl->fl_owner; + op->info.owner = info->owner; op->info.flags |= DLM_PLOCK_FL_CLOSE; send_op(op); @@ -104,22 +106,21 @@ static void do_unlock_close(struct dlm_ls *ls, u64 number, int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, int cmd, struct file_lock *fl) { + struct plock_async_data *op_data; struct dlm_ls *ls; struct plock_op *op; - struct plock_xop *xop; int rv; ls = dlm_find_lockspace_local(lockspace); if (!ls) return -EINVAL; - xop = kzalloc(sizeof(*xop), GFP_NOFS); - if (!xop) { + op = kzalloc(sizeof(*op), GFP_NOFS); + if (!op) { rv = -ENOMEM; goto out; } - op = &xop->xop; op->info.optype = DLM_PLOCK_OP_LOCK; op->info.pid = fl->fl_pid; op->info.ex = (fl->fl_type == F_WRLCK); @@ -128,35 +129,45 @@ int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, op->info.number = number; op->info.start = fl->fl_start; op->info.end = fl->fl_end; + /* async handling */ if (fl->fl_lmops && fl->fl_lmops->lm_grant) { + op_data = kzalloc(sizeof(*op_data), GFP_NOFS); + if (!op_data) { + dlm_release_plock_op(op); + rv = -ENOMEM; + goto out; + } + /* fl_owner is lockd which doesn't distinguish processes on the nfs client */ op->info.owner = (__u64) fl->fl_pid; - op->callback = fl->fl_lmops->lm_grant; - locks_init_lock(&xop->flc); - locks_copy_lock(&xop->flc, fl); - xop->fl = fl; - xop->file = file; + op_data->callback = fl->fl_lmops->lm_grant; + locks_init_lock(&op_data->flc); + locks_copy_lock(&op_data->flc, fl); + op_data->fl = fl; + op_data->file = file; + + op->data = op_data; + + send_op(op); + rv = FILE_LOCK_DEFERRED; + goto out; } else { op->info.owner = (__u64)(long) fl->fl_owner; } send_op(op); - if (!op->callback) { - rv = wait_event_interruptible(recv_wq, (op->done != 0)); - if (rv == -ERESTARTSYS) { - log_debug(ls, "dlm_posix_lock: wait killed %llx", - (unsigned long long)number); - spin_lock(&ops_lock); - list_del(&op->list); - spin_unlock(&ops_lock); - kfree(xop); - do_unlock_close(ls, number, file, fl); - goto out; - } - } else { - rv = FILE_LOCK_DEFERRED; + rv = wait_event_killable(recv_wq, (op->done != 0)); + if (rv == -ERESTARTSYS) { + spin_lock(&ops_lock); + list_del(&op->list); + spin_unlock(&ops_lock); + log_debug(ls, "%s: wait interrupted %x %llx pid %d", + __func__, ls->ls_global_id, + (unsigned long long)number, op->info.pid); + dlm_release_plock_op(op); + do_unlock_close(&op->info); goto out; } @@ -176,7 +187,7 @@ int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, (unsigned long long)number); } - kfree(xop); + dlm_release_plock_op(op); out: dlm_put_lockspace(ls); return rv; @@ -186,11 +197,11 @@ EXPORT_SYMBOL_GPL(dlm_posix_lock); /* Returns failure iff a successful lock operation should be canceled */ static int dlm_plock_callback(struct plock_op *op) { + struct plock_async_data *op_data = op->data; struct file *file; struct file_lock *fl; struct file_lock *flc; int (*notify)(struct file_lock *fl, int result) = NULL; - struct plock_xop *xop = (struct plock_xop *)op; int rv = 0; spin_lock(&ops_lock); @@ -202,10 +213,10 @@ static int dlm_plock_callback(struct plock_op *op) spin_unlock(&ops_lock); /* check if the following 2 are still valid or make a copy */ - file = xop->file; - flc = &xop->flc; - fl = xop->fl; - notify = op->callback; + file = op_data->file; + flc = &op_data->flc; + fl = op_data->fl; + notify = op_data->callback; if (op->info.rv) { notify(fl, op->info.rv); @@ -236,7 +247,7 @@ static int dlm_plock_callback(struct plock_op *op) } out: - kfree(xop); + dlm_release_plock_op(op); return rv; } @@ -306,7 +317,7 @@ int dlm_posix_unlock(dlm_lockspace_t *lockspace, u64 number, struct file *file, rv = 0; out_free: - kfree(op); + dlm_release_plock_op(op); out: dlm_put_lockspace(ls); fl->fl_flags = fl_flags; @@ -366,13 +377,15 @@ int dlm_posix_get(dlm_lockspace_t *lockspace, u64 number, struct file *file, locks_init_lock(fl); fl->fl_type = (op->info.ex) ? F_WRLCK : F_RDLCK; fl->fl_flags = FL_POSIX; - fl->fl_pid = -op->info.pid; + fl->fl_pid = op->info.pid; + if (op->info.nodeid != dlm_our_nodeid()) + fl->fl_pid = -fl->fl_pid; fl->fl_start = op->info.start; fl->fl_end = op->info.end; rv = 0; } - kfree(op); + dlm_release_plock_op(op); out: dlm_put_lockspace(ls); return rv; @@ -395,7 +408,7 @@ static ssize_t dev_read(struct file *file, char __user *u, size_t count, if (op->info.flags & DLM_PLOCK_FL_CLOSE) list_del(&op->list); else - list_move(&op->list, &recv_list); + list_move_tail(&op->list, &recv_list); memcpy(&info, &op->info, sizeof(info)); } spin_unlock(&ops_lock); @@ -408,7 +421,7 @@ static ssize_t dev_read(struct file *file, char __user *u, size_t count, (the process did not make an unlock call). */ if (op->info.flags & DLM_PLOCK_FL_CLOSE) - kfree(op); + dlm_release_plock_op(op); if (copy_to_user(u, &info, sizeof(info))) return -EFAULT; @@ -420,9 +433,9 @@ static ssize_t dev_read(struct file *file, char __user *u, size_t count, static ssize_t dev_write(struct file *file, const char __user *u, size_t count, loff_t *ppos) { + struct plock_op *op = NULL, *iter; struct dlm_plock_info info; - struct plock_op *op; - int found = 0, do_callback = 0; + int do_callback = 0; if (count != sizeof(info)) return -EINVAL; @@ -433,31 +446,63 @@ static ssize_t dev_write(struct file *file, const char __user *u, size_t count, if (check_version(&info)) return -EINVAL; + /* + * The results for waiting ops (SETLKW) can be returned in any + * order, so match all fields to find the op. The results for + * non-waiting ops are returned in the order that they were sent + * to userspace, so match the result with the first non-waiting op. + */ spin_lock(&ops_lock); - list_for_each_entry(op, &recv_list, list) { - if (op->info.fsid == info.fsid && - op->info.number == info.number && - op->info.owner == info.owner) { - list_del_init(&op->list); - memcpy(&op->info, &info, sizeof(info)); - if (op->callback) - do_callback = 1; - else - op->done = 1; - found = 1; - break; + if (info.wait) { + list_for_each_entry(iter, &recv_list, list) { + if (iter->info.fsid == info.fsid && + iter->info.number == info.number && + iter->info.owner == info.owner && + iter->info.pid == info.pid && + iter->info.start == info.start && + iter->info.end == info.end && + iter->info.ex == info.ex && + iter->info.wait) { + op = iter; + break; + } } + } else { + list_for_each_entry(iter, &recv_list, list) { + if (!iter->info.wait && + iter->info.fsid == info.fsid) { + op = iter; + break; + } + } + } + + if (op) { + /* Sanity check that op and info match. */ + if (info.wait) + WARN_ON(op->info.optype != DLM_PLOCK_OP_LOCK); + else + WARN_ON(op->info.number != info.number || + op->info.owner != info.owner || + op->info.optype != info.optype); + + list_del_init(&op->list); + memcpy(&op->info, &info, sizeof(info)); + if (op->data) + do_callback = 1; + else + op->done = 1; } spin_unlock(&ops_lock); - if (found) { + if (op) { if (do_callback) dlm_plock_callback(op); else wake_up(&recv_wq); } else - log_print("dev_write no op %x %llx", info.fsid, - (unsigned long long)info.number); + log_print("%s: no op %x %llx", __func__, + info.fsid, (unsigned long long)info.number); return count; } diff --git a/fs/dlm/recover.c b/fs/dlm/recover.c index ce2aa54ca2e2484f35b11d2cc12614b080656465..98b710cc9cf307bbac03fe898cba5c93732e9b7b 100644 --- a/fs/dlm/recover.c +++ b/fs/dlm/recover.c @@ -734,10 +734,9 @@ void dlm_recovered_lock(struct dlm_rsb *r) static void recover_lvb(struct dlm_rsb *r) { - struct dlm_lkb *lkb, *high_lkb = NULL; + struct dlm_lkb *big_lkb = NULL, *iter, *high_lkb = NULL; uint32_t high_seq = 0; int lock_lvb_exists = 0; - int big_lock_exists = 0; int lvblen = r->res_ls->ls_lvblen; if (!rsb_flag(r, RSB_NEW_MASTER2) && @@ -753,37 +752,37 @@ static void recover_lvb(struct dlm_rsb *r) /* we are the new master, so figure out if VALNOTVALID should be set, and set the rsb lvb from the best lkb available. */ - list_for_each_entry(lkb, &r->res_grantqueue, lkb_statequeue) { - if (!(lkb->lkb_exflags & DLM_LKF_VALBLK)) + list_for_each_entry(iter, &r->res_grantqueue, lkb_statequeue) { + if (!(iter->lkb_exflags & DLM_LKF_VALBLK)) continue; lock_lvb_exists = 1; - if (lkb->lkb_grmode > DLM_LOCK_CR) { - big_lock_exists = 1; + if (iter->lkb_grmode > DLM_LOCK_CR) { + big_lkb = iter; goto setflag; } - if (((int)lkb->lkb_lvbseq - (int)high_seq) >= 0) { - high_lkb = lkb; - high_seq = lkb->lkb_lvbseq; + if (((int)iter->lkb_lvbseq - (int)high_seq) >= 0) { + high_lkb = iter; + high_seq = iter->lkb_lvbseq; } } - list_for_each_entry(lkb, &r->res_convertqueue, lkb_statequeue) { - if (!(lkb->lkb_exflags & DLM_LKF_VALBLK)) + list_for_each_entry(iter, &r->res_convertqueue, lkb_statequeue) { + if (!(iter->lkb_exflags & DLM_LKF_VALBLK)) continue; lock_lvb_exists = 1; - if (lkb->lkb_grmode > DLM_LOCK_CR) { - big_lock_exists = 1; + if (iter->lkb_grmode > DLM_LOCK_CR) { + big_lkb = iter; goto setflag; } - if (((int)lkb->lkb_lvbseq - (int)high_seq) >= 0) { - high_lkb = lkb; - high_seq = lkb->lkb_lvbseq; + if (((int)iter->lkb_lvbseq - (int)high_seq) >= 0) { + high_lkb = iter; + high_seq = iter->lkb_lvbseq; } } @@ -792,7 +791,7 @@ static void recover_lvb(struct dlm_rsb *r) goto out; /* lvb is invalidated if only NL/CR locks remain */ - if (!big_lock_exists) + if (!big_lkb) rsb_set_flag(r, RSB_VALNOTVALID); if (!r->res_lvbptr) { @@ -801,9 +800,9 @@ static void recover_lvb(struct dlm_rsb *r) goto out; } - if (big_lock_exists) { - r->res_lvbseq = lkb->lkb_lvbseq; - memcpy(r->res_lvbptr, lkb->lkb_lvbptr, lvblen); + if (big_lkb) { + r->res_lvbseq = big_lkb->lkb_lvbseq; + memcpy(r->res_lvbptr, big_lkb->lkb_lvbptr, lvblen); } else if (high_lkb) { r->res_lvbseq = high_lkb->lkb_lvbseq; memcpy(r->res_lvbptr, high_lkb->lkb_lvbptr, lvblen); diff --git a/fs/eventfd.c b/fs/eventfd.c index ce1d1711fbbaf1ff7fe9de6e419d6cd891890827..66864100b823c46d33d8dc1a2858fffe2a4f1618 100644 --- a/fs/eventfd.c +++ b/fs/eventfd.c @@ -174,11 +174,14 @@ static __poll_t eventfd_poll(struct file *file, poll_table *wait) return events; } -static void eventfd_ctx_do_read(struct eventfd_ctx *ctx, __u64 *cnt) +void eventfd_ctx_do_read(struct eventfd_ctx *ctx, __u64 *cnt) { - *cnt = (ctx->flags & EFD_SEMAPHORE) ? 1 : ctx->count; + lockdep_assert_held(&ctx->wqh.lock); + + *cnt = ((ctx->flags & EFD_SEMAPHORE) && ctx->count) ? 1 : ctx->count; ctx->count -= *cnt; } +EXPORT_SYMBOL_GPL(eventfd_ctx_do_read); /** * eventfd_ctx_remove_wait_queue - Read the current counter and removes wait queue. diff --git a/fs/exfat/.github/workflows/c-cpp.yml b/fs/exfat/.github/workflows/c-cpp.yml new file mode 100644 index 0000000000000000000000000000000000000000..375c800ac23c9238138a6db60b8c47068e683df7 --- /dev/null +++ b/fs/exfat/.github/workflows/c-cpp.yml @@ -0,0 +1,196 @@ +name: linux-exfat-oot CI + +on: + push: + branches: [ "master" ] + pull_request: + branches: [ "master" ] + +jobs: + build: + + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v3 + - name: Download the kernel + run: | + sudo apt-get update + sudo apt-get install libelf-dev wget tar gzip python2.7 + wget https://mirrors.edge.kernel.org/pub/linux/kernel/v4.x/linux-4.1.36.tar.gz + tar xf linux-4.1.36.tar.gz + mv linux-4.1.36 linux-stable + - name: Prerequisite for xfstests testing + run: | + sudo apt-get install linux-headers-$(uname -r) + sudo apt-get install autoconf libtool pkg-config libnl-3-dev libnl-genl-3-dev + sudo apt-get install xfslibs-dev uuid-dev libtool-bin xfsprogs libgdbm-dev gawk fio attr libattr1-dev libacl1-dev libaio-dev + git clone --branch=exfat-next https://github.com/exfat-utils/exfat-utils + git clone https://github.com/namjaejeon/exfat-testsuites + export LD_LIBRARY_PATH=/usr/local/lib:$LD_LIBRARY_PATH + export PATH=/usr/local/lib:$PATH + sudo useradd fsgqa + sudo useradd 123456-fsgqa + - name: Copy exfat source to kernel + run: | + mv linux-stable ../ + mkdir ../linux-stable/fs/exfat + cp -ar * ../linux-stable/fs/exfat/ + - name: Compile with 4.1 kernel + run: | + cd ../linux-stable + yes "" | make oldconfig > /dev/null + echo 'obj-$(CONFIG_EXFAT_FS) += exfat/' >> fs/Makefile + echo 'source "fs/exfat/Kconfig"' >> fs/Kconfig + echo 'CONFIG_EXFAT_FS=m' >> .config + echo 'CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"' >> .config + make -j$((`nproc`+1)) fs/exfat/exfat.ko + - name: Run xfstests testsuite + run: | + cd ../linux-exfat-oot + make > /dev/null + sudo make install > /dev/null + sudo insmod exfat.ko + cd exfat-utils + ./autogen.sh > /dev/null + ./configure > /dev/null + make -j$((`nproc`+1)) > /dev/null + sudo make install > /dev/null + cd .. + sudo mkdir -p /mnt/scratch + sudo mkdir -p /mnt/test + sudo mkdir -p full_test + - name: create file/director test + run: | + truncate -s 10G full_test.img + sudo losetup /dev/loop22 full_test.img + sudo mkfs.exfat /dev/loop22 + sudo mount -t exfat /dev/loop22 ./full_test/ + cd full_test/ + i=1;while [ $i -le 10000 ];do sudo touch file$i;if [ $? != 0 ]; then exit 1; fi; i=$(($i + 1));done + sync + sudo fsck.exfat /dev/loop22 + sudo rm -rf * + i=1;while [ $i -le 10000 ];do sudo mkdir file$i;if [ $? != 0 ]; then exit 1; fi; i=$(($i + 1));done + sync + sudo rm -rf * + sudo fsck.exfat /dev/loop22 + cd .. + sudo umount ./full_test/ + sudo fsck.exfat /dev/loop22 + sudo losetup -d /dev/loop22 + rm full_test.img + - name: xfstest tests + run: | + cd exfat-testsuites/ + tar xzvf xfstests-exfat.tgz > /dev/null + cd xfstests-exfat + make -j$((`nproc`+1)) > /dev/null + truncate -s 100G test.img + truncate -s 100G scratch.img + sudo losetup /dev/loop20 test.img + sudo losetup /dev/loop21 scratch.img + sudo mkfs.exfat /dev/loop20 + sudo mkfs.exfat /dev/loop21 + sudo ./check generic/001 + sudo ./check generic/006 + sudo ./check generic/007 + sudo ./check generic/011 + sudo ./check generic/013 + sudo ./check generic/014 + sudo ./check generic/028 + sudo ./check generic/029 + sudo ./check generic/030 + sudo ./check generic/034 + sudo ./check generic/035 + sudo ./check generic/036 + sudo ./check generic/069 + sudo ./check generic/073 + sudo ./check generic/074 + sudo ./check generic/075 + sudo ./check generic/076 + sudo ./check generic/080 + sudo ./check generic/084 + sudo ./check generic/091 + sudo ./check generic/095 + sudo ./check generic/098 + sudo ./check generic/100 + sudo ./check generic/112 + sudo ./check generic/113 + sudo ./check generic/114 + sudo ./check generic/120 + sudo ./check generic/123 + sudo ./check generic/124 + sudo ./check generic/127 + sudo ./check generic/129 + sudo ./check generic/130 + sudo ./check generic/131 + sudo ./check generic/132 + sudo ./check generic/133 + sudo ./check generic/135 + sudo ./check generic/141 + sudo ./check generic/169 + sudo ./check generic/198 + sudo ./check generic/207 + sudo ./check generic/208 + sudo ./check generic/209 + sudo ./check generic/210 + sudo ./check generic/211 + sudo ./check generic/212 + sudo ./check generic/215 + sudo losetup -d /dev/loop20 + sudo losetup -d /dev/loop21 + rm test.img + rm scratch.img + truncate -s 100G test.img + truncate -s 100G scratch.img + sudo losetup /dev/loop20 test.img + sudo losetup /dev/loop21 scratch.img + sudo mkfs.exfat /dev/loop20 + sudo mkfs.exfat /dev/loop21 + sudo ./check generic/221 + sudo ./check generic/239 + sudo ./check generic/240 + sudo ./check generic/241 + sudo ./check generic/245 + sudo ./check generic/246 + sudo ./check generic/247 + sudo ./check generic/248 + sudo ./check generic/249 + sudo ./check generic/257 + sudo ./check generic/260 + sudo ./check generic/263 + sudo ./check generic/285 + sudo ./check generic/288 + sudo ./check generic/308 + sudo ./check generic/309 + sudo ./check generic/310 + sudo ./check generic/313 + sudo ./check generic/323 + sudo ./check generic/325 + sudo ./check generic/338 + sudo ./check generic/339 + sudo ./check generic/340 + sudo ./check generic/344 + sudo ./check generic/345 + sudo ./check generic/346 + sudo ./check generic/354 + sudo ./check generic/376 + sudo ./check generic/393 + sudo ./check generic/394 + sudo ./check generic/405 + sudo ./check generic/406 + sudo ./check generic/409 + sudo ./check generic/410 + sudo ./check generic/411 + sudo ./check generic/412 + sudo ./check generic/418 + sudo ./check generic/428 + sudo ./check generic/437 + sudo ./check generic/438 + sudo ./check generic/441 + sudo ./check generic/443 + sudo ./check generic/448 + sudo ./check generic/450 + sudo ./check generic/451 + sudo ./check generic/452 diff --git a/fs/exfat/.travis.yml b/fs/exfat/.travis.yml deleted file mode 100644 index 04cc4a4136266fc5598ec3712a8debbcdcafdf26..0000000000000000000000000000000000000000 --- a/fs/exfat/.travis.yml +++ /dev/null @@ -1,96 +0,0 @@ -dist: bionic - -language: c - -notifications: - - email: true - -before_script: - # Download the kernel - - sudo apt-get install libelf-dev wget tar gzip python - - wget https://mirrors.edge.kernel.org/pub/linux/kernel/v4.x/linux-4.1.36.tar.gz - - tar xf linux-4.1.36.tar.gz - - mv linux-4.1.36 linux-stable - - ./.travis_get_mainline_kernel - - cp ./.travis_cmd_wrapper.pl ~/travis_cmd_wrapper.pl - # Prerequisite for xfstests testing - - sudo apt-get install linux-headers-$(uname -r) - - sudo apt-get install autoconf libtool pkg-config libnl-3-dev libnl-genl-3-dev - - sudo apt-get install xfslibs-dev uuid-dev libtool-bin xfsprogs libgdbm-dev gawk fio attr libattr1-dev libacl1-dev libaio-dev - - git clone --branch=exfat-next https://github.com/exfat-utils/exfat-utils - - git clone https://github.com/namjaejeon/exfat-testsuites - - export LD_LIBRARY_PATH=/usr/local/lib:$LD_LIBRARY_PATH - - export PATH=/usr/local/lib:$PATH - - sudo useradd fsgqa - - sudo useradd 123456-fsgqa - -script: - # Copy ksmbd source to kernel - - mv linux-stable ../ - - mv linux ../ - - mkdir ../linux-stable/fs/exfat - - cp -ar * ../linux-stable/fs/exfat/ - - cp -ar * ../linux/fs/exfat/ - - # Compile with 4.1 kernel - - cd ../linux-stable - - yes "" | make oldconfig > /dev/null - - echo 'obj-$(CONFIG_EXFAT_FS) += exfat/' >> fs/Makefile - - echo 'source "fs/exfat/Kconfig"' >> fs/Kconfig - - echo 'CONFIG_EXFAT_FS=m' >> .config - - echo 'CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"' >> .config - - make -j$((`nproc`+1)) fs/exfat/exfat.ko - - # Compile with latest Torvalds' kernel -# - cd ../linux -# - yes "" | make oldconfig > /dev/null -# - echo 'obj-$(CONFIG_EXFAT) += exfat/' >> fs/Makefile -# - echo 'source "fs/exfat/Kconfig"' >> fs/Kconfig -# - echo 'CONFIG_EXFAT_FS=m' >> .config -# - echo 'CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"' >> .config -# - make -j$((`nproc`+1)) fs/exfat/exfat.ko - - # Run xfstests testsuite - - cd ../linux-exfat-oot - - make > /dev/null - - sudo make install > /dev/null - - sudo modprobe exfat - - cd exfat-utils - - ./autogen.sh > /dev/null - - ./configure > /dev/null - - make -j$((`nproc`+1)) > /dev/null - - sudo make install > /dev/null - - sudo mkdir -p /mnt/scratch - - sudo mkdir -p /mnt/test - - sudo mkdir -p /mnt/full_test - # create file/director test - - truncate -s 10G full_test.img - - sudo losetup /dev/loop22 full_test.img - - sudo mkfs.exfat /dev/loop22 - - sudo mount -t exfat /dev/loop22 /mnt/full_test/ - - cd /mnt/full_test/ - - i=1;while [ $i -le 10000 ];do sudo touch file$i;if [ $? != 0 ]; then exit 1; fi; i=$(($i + 1));done - - sync - - sudo fsck.exfat /dev/loop22 - - sudo rm -rf * - - i=1;while [ $i -le 10000 ];do sudo mkdir file$i;if [ $? != 0 ]; then exit 1; fi; i=$(($i + 1));done - - sync - - sudo rm -rf * - - sudo fsck.exfat /dev/loop22 - - cd - - - sudo umount /mnt/full_test/ - - sudo fsck.exfat /dev/loop22 - # run xfstests test - - truncate -s 100G test.img - - truncate -s 100G scratch.img - - sudo losetup /dev/loop20 test.img - - sudo losetup /dev/loop21 scratch.img - - sudo mkfs.exfat /dev/loop20 - - sudo mkfs.exfat /dev/loop21 - - cd .. - - cd exfat-testsuites/ - - tar xzvf xfstests-exfat.tgz > /dev/null - - cd xfstests-exfat - - make -j$((`nproc`+1)) > /dev/null - - sudo ./check generic/001 - - sudo ./check generic/006 diff --git a/fs/exfat/.travis_cmd_wrapper.pl b/fs/exfat/.travis_cmd_wrapper.pl deleted file mode 100755 index 0cbaea440eb9e7d28748a22aea57e64f21cb89d6..0000000000000000000000000000000000000000 --- a/fs/exfat/.travis_cmd_wrapper.pl +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/perl - -# -# SPDX-License-Identifier: GPL-2.0-or-later -# -# Copyright (C) 2019 Samsung Electronics Co., Ltd. -# - -use strict; - -sub tweak_sysctl() -{ - `sudo sysctl kernel.hardlockup_panic=0`; - `sudo sysctl kernel.hung_task_panic=0`; - `sudo sysctl kernel.panic=128`; - `sudo sysctl kernel.panic_on_io_nmi=0`; - `sudo sysctl kernel.panic_on_oops=0`; - `sudo sysctl kernel.panic_on_rcu_stall=0`; - `sudo sysctl kernel.panic_on_unrecovered_nmi=0`; - `sudo sysctl kernel.panic_on_warn=0`; - `sudo sysctl kernel.softlockup_panic=0`; - `sudo sysctl kernel.unknown_nmi_panic=0`; -} - -sub execute($$) -{ - my $cmd = shift; - my $timeout = shift; - my $output = "Timeout"; - my $status = 1; - - $timeout = 8 * 60 if (!defined $timeout); - - tweak_sysctl(); - - eval { - local $SIG{ALRM} = sub { - print "TIMEOUT:\n"; - system("top -n 1"), print "top\n"; - system("free"), print "free\n"; - system("dmesg"), print "dmesg\n"; - die "Timeout\n"; - }; - - print "Executing $cmd with timeout $timeout\n"; - - alarm $timeout; - $output = `$cmd`; - $status = $?; - alarm 0; - print $output."\n"; - print "Finished: status $status\n"; - }; - - if ($@) { - die unless $@ eq "Timeout\n"; - } -} - -if (! defined $ARGV[0]) { - print "Usage:\n\t./.travis_cmd_wrapper.pl command [timeout seconds]\n"; - exit 1; -} - -execute($ARGV[0], $ARGV[1]); diff --git a/fs/exfat/.travis_get_mainline_kernel b/fs/exfat/.travis_get_mainline_kernel deleted file mode 100755 index 3356d15da772a2423ae03332afa895492ba03d7d..0000000000000000000000000000000000000000 --- a/fs/exfat/.travis_get_mainline_kernel +++ /dev/null @@ -1,37 +0,0 @@ -#!/bin/sh - -# -# A simple script we are using to get the latest mainline kernel -# tar ball -# - -wget https://www.kernel.org/releases.json -if [ $? -ne 0 ]; then - echo "Could not download kernel.org/releases.json" - exit 1 -fi - -VER=$(cat releases.json | python2.7 -c "import sys, json; print json.load(sys.stdin)['latest_stable']['version']") -if [ $? -ne 0 ]; then - echo "Could not parse release.json" - exit 1 -fi - -if [ "z$VER" = "z" ]; then - echo "Could not determine latest release version" - exit 1 -fi - -wget https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-"$VER".tar.gz -if [ $? -ne 0 ]; then - echo "Could not download $VER kernel version" - exit 1 -fi - -tar xf linux-"$VER".tar.gz -if [ $? -ne 0 ]; then - echo "Could not untar kernel tar ball" - exit 1 -fi - -mv linux-"$VER" linux diff --git a/fs/exfat/Kconfig b/fs/exfat/Kconfig index 2d3636dc5b8c31062ace5ab448d616cbd72bd340..b3e5e9ebabc86abdd2fbba2c0ef630770c903b84 100644 --- a/fs/exfat/Kconfig +++ b/fs/exfat/Kconfig @@ -3,6 +3,7 @@ config EXFAT_FS tristate "exFAT filesystem support" select NLS + select LEGACY_DIRECT_IO help This allows you to mount devices formatted with the exFAT file system. exFAT is typically used on SD-Cards or USB sticks. diff --git a/fs/exfat/balloc.c b/fs/exfat/balloc.c index 30c2414d859c818698059902c5193e987e0c852d..c226d5d1c36bb6c7271a9c43b136d3ed69db3ce4 100644 --- a/fs/exfat/balloc.c +++ b/fs/exfat/balloc.c @@ -12,6 +12,7 @@ #else #include #endif +#include #include "exfat_raw.h" #include "exfat_fs.h" @@ -75,8 +76,12 @@ static int exfat_allocate_bitmap(struct super_block *sb, } sbi->map_sectors = ((need_map_size - 1) >> (sb->s_blocksize_bits)) + 1; - sbi->vol_amap = kmalloc_array(sbi->map_sectors, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0) + sbi->vol_amap = kvmalloc_array(sbi->map_sectors, sizeof(struct buffer_head *), GFP_KERNEL); +#else + sbi->vol_amap = vmalloc(sbi->map_sectors * sizeof(struct buffer_head *)); +#endif if (!sbi->vol_amap) return -ENOMEM; @@ -90,7 +95,7 @@ static int exfat_allocate_bitmap(struct super_block *sb, while (j < i) brelse(sbi->vol_amap[j++]); - kfree(sbi->vol_amap); + kvfree(sbi->vol_amap); sbi->vol_amap = NULL; return -EIO; } @@ -144,7 +149,7 @@ void exfat_free_bitmap(struct exfat_sb_info *sbi) for (i = 0; i < sbi->map_sectors; i++) __brelse(sbi->vol_amap[i]); - kfree(sbi->vol_amap); + kvfree(sbi->vol_amap); } int exfat_set_bitmap(struct inode *inode, unsigned int clu, bool sync) diff --git a/fs/exfat/dir.c b/fs/exfat/dir.c index 07765a74251a50094c0e33769ee66abbfab8c89f..bf8eb5d1b1c258ad349478ffd337148e6486e1ba 100644 --- a/fs/exfat/dir.c +++ b/fs/exfat/dir.c @@ -30,15 +30,16 @@ static int exfat_extract_uni_name(struct exfat_dentry *ep, } -static void exfat_get_uniname_from_ext_entry(struct super_block *sb, +static int exfat_get_uniname_from_ext_entry(struct super_block *sb, struct exfat_chain *p_dir, int entry, unsigned short *uniname) { - int i; - struct exfat_entry_set_cache *es; + int i, err; + struct exfat_entry_set_cache es; + unsigned int uni_len = 0, len; - es = exfat_get_dentry_set(sb, p_dir, entry, ES_ALL_ENTRIES); - if (!es) - return; + err = exfat_get_dentry_set(&es, sb, p_dir, entry, ES_ALL_ENTRIES); + if (err) + return err; /* * First entry : file entry @@ -46,24 +47,28 @@ static void exfat_get_uniname_from_ext_entry(struct super_block *sb, * Third entry : first file-name entry * So, the index of first file-name dentry should start from 2. */ - for (i = 2; i < es->num_entries; i++) { - struct exfat_dentry *ep = exfat_get_dentry_cached(es, i); + for (i = ES_IDX_FIRST_FILENAME; i < es.num_entries; i++) { + struct exfat_dentry *ep = exfat_get_dentry_cached(&es, i); /* end of name entry */ if (exfat_get_entry_type(ep) != TYPE_EXTEND) break; - exfat_extract_uni_name(ep, uniname); + len = exfat_extract_uni_name(ep, uniname); + uni_len += len; + if (len != EXFAT_FILE_NAME_LEN || uni_len >= MAX_NAME_LENGTH) + break; uniname += EXFAT_FILE_NAME_LEN; } - exfat_free_dentry_set(es, false); + exfat_put_dentry_set(&es, false); + return 0; } /* read a directory entry from the opened directory */ static int exfat_readdir(struct inode *inode, loff_t *cpos, struct exfat_dir_entry *dir_entry) { - int i, dentries_per_clu, dentries_per_clu_bits = 0, num_ext; + int i, dentries_per_clu, num_ext, err; unsigned int type, clu_offset, max_dentries; struct exfat_chain dir, clu; struct exfat_uni_name uni_name; @@ -85,11 +90,10 @@ static int exfat_readdir(struct inode *inode, loff_t *cpos, struct exfat_dir_ent EXFAT_B_TO_CLU(i_size_read(inode), sbi), ei->flags); dentries_per_clu = sbi->dentries_per_clu; - dentries_per_clu_bits = ilog2(dentries_per_clu); max_dentries = (unsigned int)min_t(u64, MAX_EXFAT_DENTRIES, - (u64)sbi->num_clusters << dentries_per_clu_bits); + (u64)EXFAT_CLU_TO_DEN(sbi->num_clusters, sbi)); - clu_offset = dentry >> dentries_per_clu_bits; + clu_offset = EXFAT_DEN_TO_CLU(dentry, sbi); exfat_chain_dup(&clu, &dir); if (clu.flags == ALLOC_NO_FAT_CHAIN) { @@ -103,7 +107,7 @@ static int exfat_readdir(struct inode *inode, loff_t *cpos, struct exfat_dir_ent clu.dir = ei->hint_bmap.clu; } - while (clu_offset > 0) { + while (clu_offset > 0 && clu.dir != EXFAT_EOF_CLUSTER) { if (exfat_get_next_cluster(sb, &(clu.dir))) return -EIO; @@ -149,8 +153,12 @@ static int exfat_readdir(struct inode *inode, loff_t *cpos, struct exfat_dir_ent 0); *uni_name.name = 0x0; - exfat_get_uniname_from_ext_entry(sb, &clu, i, + err = exfat_get_uniname_from_ext_entry(sb, &clu, i, uni_name.name); + if (err) { + brelse(bh); + continue; + } exfat_utf16_to_nls(sb, &uni_name, dir_entry->namebuf.lfn, dir_entry->namebuf.lfnbuf_len); @@ -164,7 +172,7 @@ static int exfat_readdir(struct inode *inode, loff_t *cpos, struct exfat_dir_ent dir_entry->entry = dentry; brelse(bh); - ei->hint_bmap.off = dentry >> dentries_per_clu_bits; + ei->hint_bmap.off = EXFAT_DEN_TO_CLU(dentry, sbi); ei->hint_bmap.clu = clu.dir; *cpos = EXFAT_DEN_TO_B(dentry + 1 + num_ext); @@ -211,7 +219,10 @@ static void exfat_free_namebuf(struct exfat_dentry_namebuf *nb) exfat_init_namebuf(nb); } -/* skip iterating emit_dots when dir is empty */ +/* + * Before calling dir_emit*(), sbi->s_lock should be released + * because page fault can occur in dir_emit*(). + */ #define ITER_POS_FILLED_DOTS (2) static int exfat_iterate(struct file *filp, struct dir_context *ctx) { @@ -226,35 +237,33 @@ static int exfat_iterate(struct file *filp, struct dir_context *ctx) int err = 0, fake_offset = 0; exfat_init_namebuf(nb); - mutex_lock(&EXFAT_SB(sb)->s_lock); cpos = ctx->pos; if (!dir_emit_dots(filp, ctx)) - goto unlock; + goto out; if (ctx->pos == ITER_POS_FILLED_DOTS) { cpos = 0; fake_offset = 1; } - if (cpos & (DENTRY_SIZE - 1)) { - err = -ENOENT; - goto unlock; - } + cpos = round_up(cpos, DENTRY_SIZE); /* name buffer should be allocated before use */ err = exfat_alloc_namebuf(nb); if (err) - goto unlock; + goto out; get_new: + mutex_lock(&EXFAT_SB(sb)->s_lock); + if (ei->flags == ALLOC_NO_FAT_CHAIN && cpos >= i_size_read(inode)) goto end_of_dir; err = exfat_readdir(inode, &cpos, &de); if (err) { /* - * At least we tried to read a sector. Move cpos to next sector - * position (should be aligned). + * At least we tried to read a sector. + * Move cpos to next sector position (should be aligned). */ if (err == -EIO) { cpos += 1 << (sb->s_blocksize_bits); @@ -277,16 +286,10 @@ static int exfat_iterate(struct file *filp, struct dir_context *ctx) inum = iunique(sb, EXFAT_ROOT_INO); } - /* - * Before calling dir_emit(), sb_lock should be released. - * Because page fault can occur in dir_emit() when the size - * of buffer given from user is larger than one page size. - */ mutex_unlock(&EXFAT_SB(sb)->s_lock); if (!dir_emit(ctx, nb->lfn, strlen(nb->lfn), inum, (de.attr & ATTR_SUBDIR) ? DT_DIR : DT_REG)) - goto out_unlocked; - mutex_lock(&EXFAT_SB(sb)->s_lock); + goto out; ctx->pos = cpos; goto get_new; @@ -294,9 +297,8 @@ static int exfat_iterate(struct file *filp, struct dir_context *ctx) if (!cpos && fake_offset) cpos = ITER_POS_FILLED_DOTS; ctx->pos = cpos; -unlock: mutex_unlock(&EXFAT_SB(sb)->s_lock); -out_unlocked: +out: /* * To improve performance, free namebuf after unlock sb_lock. * If namebuf is not allocated, this function do nothing @@ -338,7 +340,7 @@ int exfat_calc_num_entries(struct exfat_uni_name *p_uniname) return -EINVAL; /* 1 file entry + 1 stream entry + name entries */ - return ((len - 1) / EXFAT_FILE_NAME_LEN + 3); + return ES_ENTRY_NUM(len); } unsigned int exfat_get_entry_type(struct exfat_dentry *ep) @@ -381,6 +383,12 @@ unsigned int exfat_get_entry_type(struct exfat_dentry *ep) return TYPE_ACL; return TYPE_CRITICAL_SEC; } + + if (ep->type == EXFAT_VENDOR_EXT) + return TYPE_VENDOR_EXT; + if (ep->type == EXFAT_VENDOR_ALLOC) + return TYPE_VENDOR_ALLOC; + return TYPE_BENIGN_SEC; } @@ -534,6 +542,25 @@ int exfat_update_dir_chksum(struct inode *inode, struct exfat_chain *p_dir, return ret; } +static void exfat_free_benign_secondary_clusters(struct inode *inode, + struct exfat_dentry *ep) +{ + struct super_block *sb = inode->i_sb; + struct exfat_chain dir; + unsigned int start_clu = + le32_to_cpu(ep->dentry.generic_secondary.start_clu); + u64 size = le64_to_cpu(ep->dentry.generic_secondary.size); + unsigned char flags = ep->dentry.generic_secondary.flags; + + if (!(flags & ALLOC_POSSIBLE) || !start_clu || !size) + return; + + exfat_chain_set(&dir, start_clu, + EXFAT_B_TO_CLU_ROUND_UP(size, EXFAT_SB(sb)), + flags); + exfat_free_cluster(inode, &dir); +} + int exfat_init_ext_entry(struct inode *inode, struct exfat_chain *p_dir, int entry, int num_entries, struct exfat_uni_name *p_uniname) { @@ -566,6 +593,9 @@ int exfat_init_ext_entry(struct inode *inode, struct exfat_chain *p_dir, if (!ep) return -EIO; + if (exfat_get_entry_type(ep) & TYPE_BENIGN_SEC) + exfat_free_benign_secondary_clusters(inode, ep); + exfat_init_name_entry(ep, uniname); exfat_update_bh(bh, sync); brelse(bh); @@ -589,6 +619,9 @@ int exfat_remove_entries(struct inode *inode, struct exfat_chain *p_dir, if (!ep) return -EIO; + if (exfat_get_entry_type(ep) & TYPE_BENIGN_SEC) + exfat_free_benign_secondary_clusters(inode, ep); + exfat_set_entry_type(ep, TYPE_DELETED); exfat_update_bh(bh, IS_DIRSYNC(inode)); brelse(bh); @@ -603,18 +636,18 @@ void exfat_update_dir_chksum_with_entry_set(struct exfat_entry_set_cache *es) unsigned short chksum = 0; struct exfat_dentry *ep; - for (i = 0; i < es->num_entries; i++) { + for (i = ES_IDX_FILE; i < es->num_entries; i++) { ep = exfat_get_dentry_cached(es, i); chksum = exfat_calc_chksum16(ep, DENTRY_SIZE, chksum, chksum_type); chksum_type = CS_DEFAULT; } - ep = exfat_get_dentry_cached(es, 0); + ep = exfat_get_dentry_cached(es, ES_IDX_FILE); ep->dentry.file.checksum = cpu_to_le16(chksum); es->modified = true; } -int exfat_free_dentry_set(struct exfat_entry_set_cache *es, int sync) +int exfat_put_dentry_set(struct exfat_entry_set_cache *es, int sync) { int i, err = 0; @@ -626,7 +659,10 @@ int exfat_free_dentry_set(struct exfat_entry_set_cache *es, int sync) bforget(es->bh[i]); else brelse(es->bh[i]); - kfree(es); + + if (IS_DYNAMIC_ES(es)) + kfree(es->bh); + return err; } @@ -754,6 +790,7 @@ enum exfat_validate_dentry_mode { ES_MODE_GET_STRM_ENTRY, ES_MODE_GET_NAME_ENTRY, ES_MODE_GET_CRITICAL_SEC_ENTRY, + ES_MODE_GET_BENIGN_SEC_ENTRY, }; static bool exfat_validate_entry(unsigned int type, @@ -767,36 +804,33 @@ static bool exfat_validate_entry(unsigned int type, if (type != TYPE_FILE && type != TYPE_DIR) return false; *mode = ES_MODE_GET_FILE_ENTRY; - return true; + break; case ES_MODE_GET_FILE_ENTRY: if (type != TYPE_STREAM) return false; *mode = ES_MODE_GET_STRM_ENTRY; - return true; + break; case ES_MODE_GET_STRM_ENTRY: if (type != TYPE_EXTEND) return false; *mode = ES_MODE_GET_NAME_ENTRY; - return true; + break; case ES_MODE_GET_NAME_ENTRY: - if (type == TYPE_STREAM) - return false; - if (type != TYPE_EXTEND) { - if (!(type & TYPE_CRITICAL_SEC)) - return false; - *mode = ES_MODE_GET_CRITICAL_SEC_ENTRY; - } - return true; - case ES_MODE_GET_CRITICAL_SEC_ENTRY: - if (type == TYPE_EXTEND || type == TYPE_STREAM) + if (type & TYPE_BENIGN_SEC) + *mode = ES_MODE_GET_BENIGN_SEC_ENTRY; + else if (type != TYPE_EXTEND) return false; - if ((type & TYPE_CRITICAL_SEC) != TYPE_CRITICAL_SEC) + break; + case ES_MODE_GET_BENIGN_SEC_ENTRY: + /* Assume unreconized benign secondary entry */ + if (!(type & TYPE_BENIGN_SEC)) return false; - return true; + break; default: - WARN_ON_ONCE(1); return false; } + + return true; } struct exfat_dentry *exfat_get_dentry_cached( @@ -823,14 +857,14 @@ struct exfat_dentry *exfat_get_dentry_cached( * pointer of entry set on success, * NULL on failure. */ -struct exfat_entry_set_cache *exfat_get_dentry_set(struct super_block *sb, - struct exfat_chain *p_dir, int entry, unsigned int type) +int exfat_get_dentry_set(struct exfat_entry_set_cache *es, + struct super_block *sb, struct exfat_chain *p_dir, int entry, + unsigned int type) { int ret, i, num_bh; - unsigned int off, byte_offset, clu = 0; + unsigned int off; sector_t sec; struct exfat_sb_info *sbi = EXFAT_SB(sb); - struct exfat_entry_set_cache *es; struct exfat_dentry *ep; int num_entries; enum exfat_validate_dentry_mode mode = ES_MODE_STARTED; @@ -838,52 +872,51 @@ struct exfat_entry_set_cache *exfat_get_dentry_set(struct super_block *sb, if (p_dir->dir == DIR_DELETED) { exfat_err(sb, "access to deleted dentry"); - return NULL; + return -EIO; } - byte_offset = EXFAT_DEN_TO_B(entry); - ret = exfat_walk_fat_chain(sb, p_dir, byte_offset, &clu); + ret = exfat_find_location(sb, p_dir, entry, &sec, &off); if (ret) - return NULL; + return ret; - es = kzalloc(sizeof(*es), GFP_KERNEL); - if (!es) - return NULL; + memset(es, 0, sizeof(*es)); es->sb = sb; es->modified = false; - - /* byte offset in cluster */ - byte_offset = EXFAT_CLU_OFFSET(byte_offset, sbi); - - /* byte offset in sector */ - off = EXFAT_BLK_OFFSET(byte_offset, sb); es->start_off = off; - - /* sector offset in cluster */ - sec = EXFAT_B_TO_BLK(byte_offset, sb); - sec += exfat_cluster_to_sector(sbi, clu); + es->bh = es->__bh; bh = sb_bread(sb, sec); if (!bh) - goto free_es; + return -EIO; es->bh[es->num_bh++] = bh; - ep = exfat_get_dentry_cached(es, 0); + ep = exfat_get_dentry_cached(es, ES_IDX_FILE); if (!exfat_validate_entry(exfat_get_entry_type(ep), &mode)) - goto free_es; + goto put_es; num_entries = type == ES_ALL_ENTRIES ? ep->dentry.file.num_ext + 1 : type; es->num_entries = num_entries; num_bh = EXFAT_B_TO_BLK_ROUND_UP(off + num_entries * DENTRY_SIZE, sb); + if (num_bh > ARRAY_SIZE(es->__bh)) { + es->bh = kmalloc_array(num_bh, sizeof(*es->bh), GFP_KERNEL); + if (!es->bh) { + brelse(bh); + return -ENOMEM; + } + es->bh[0] = bh; + } + for (i = 1; i < num_bh; i++) { /* get the next sector */ if (exfat_is_last_sector_in_cluster(sbi, sec)) { + unsigned int clu = exfat_sector_to_cluster(sbi, sec); + if (p_dir->flags == ALLOC_NO_FAT_CHAIN) clu++; else if (exfat_get_next_cluster(sb, &clu)) - goto free_es; + goto put_es; sec = exfat_cluster_to_sector(sbi, clu); } else { sec++; @@ -891,21 +924,51 @@ struct exfat_entry_set_cache *exfat_get_dentry_set(struct super_block *sb, bh = sb_bread(sb, sec); if (!bh) - goto free_es; + goto put_es; es->bh[es->num_bh++] = bh; } /* validate cached dentries */ - for (i = 1; i < num_entries; i++) { + for (i = ES_IDX_STREAM; i < num_entries; i++) { ep = exfat_get_dentry_cached(es, i); if (!exfat_validate_entry(exfat_get_entry_type(ep), &mode)) - goto free_es; + goto put_es; } - return es; + return 0; + +put_es: + exfat_put_dentry_set(es, false); + return -EIO; +} -free_es: - exfat_free_dentry_set(es, false); - return NULL; +static inline void exfat_reset_empty_hint(struct exfat_hint_femp *hint_femp) +{ + hint_femp->eidx = EXFAT_HINT_NONE; + hint_femp->count = 0; +} + +static inline void exfat_set_empty_hint(struct exfat_inode_info *ei, + struct exfat_hint_femp *candi_empty, struct exfat_chain *clu, + int dentry, int num_entries, int entry_type) +{ + if (ei->hint_femp.eidx == EXFAT_HINT_NONE || + ei->hint_femp.eidx > dentry) { + int total_entries = EXFAT_B_TO_DEN(i_size_read(&ei->vfs_inode)); + + if (candi_empty->count == 0) { + candi_empty->cur = *clu; + candi_empty->eidx = dentry; + } + + if (entry_type == TYPE_UNUSED) + candi_empty->count += total_entries - dentry; + else + candi_empty->count++; + + if (candi_empty->count == num_entries || + candi_empty->count + candi_empty->eidx == total_entries) + ei->hint_femp = *candi_empty; + } } enum { @@ -928,17 +991,21 @@ enum { */ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, struct exfat_chain *p_dir, struct exfat_uni_name *p_uniname, - int num_entries, unsigned int type, struct exfat_hint *hint_opt) + struct exfat_hint *hint_opt) { int i, rewind = 0, dentry = 0, end_eidx = 0, num_ext = 0, len; int order, step, name_len = 0; - int dentries_per_clu, num_empty = 0; + int dentries_per_clu; unsigned int entry_type; unsigned short *uniname = NULL; struct exfat_chain clu; struct exfat_hint *hint_stat = &ei->hint_stat; struct exfat_hint_femp candi_empty; struct exfat_sb_info *sbi = EXFAT_SB(sb); + int num_entries = exfat_calc_num_entries(p_uniname); + + if (num_entries < 0) + return num_entries; dentries_per_clu = sbi->dentries_per_clu; @@ -950,10 +1017,13 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, end_eidx = dentry; } - candi_empty.eidx = EXFAT_HINT_NONE; + exfat_reset_empty_hint(&ei->hint_femp); + rewind: order = 0; step = DIRENT_STEP_FILE; + exfat_reset_empty_hint(&candi_empty); + while (clu.dir != EXFAT_EOF_CLUSTER) { i = dentry & (dentries_per_clu - 1); for (; i < dentries_per_clu; i++, dentry++) { @@ -973,26 +1043,9 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, entry_type == TYPE_DELETED) { step = DIRENT_STEP_FILE; - num_empty++; - if (candi_empty.eidx == EXFAT_HINT_NONE && - num_empty == 1) { - exfat_chain_set(&candi_empty.cur, - clu.dir, clu.size, clu.flags); - } - - if (candi_empty.eidx == EXFAT_HINT_NONE && - num_empty >= num_entries) { - candi_empty.eidx = - dentry - (num_empty - 1); - WARN_ON(candi_empty.eidx < 0); - candi_empty.count = num_empty; - - if (ei->hint_femp.eidx == - EXFAT_HINT_NONE || - candi_empty.eidx <= - ei->hint_femp.eidx) - ei->hint_femp = candi_empty; - } + exfat_set_empty_hint(ei, &candi_empty, &clu, + dentry, num_entries, + entry_type); brelse(bh); if (entry_type == TYPE_UNUSED) @@ -1000,17 +1053,14 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, continue; } - num_empty = 0; - candi_empty.eidx = EXFAT_HINT_NONE; + exfat_reset_empty_hint(&candi_empty); if (entry_type == TYPE_FILE || entry_type == TYPE_DIR) { step = DIRENT_STEP_FILE; hint_opt->clu = clu.dir; hint_opt->eidx = i; - if (type == TYPE_ALL || type == entry_type) { - num_ext = ep->dentry.file.num_ext; - step = DIRENT_STEP_STRM; - } + num_ext = ep->dentry.file.num_ext; + step = DIRENT_STEP_STRM; brelse(bh); continue; } @@ -1041,7 +1091,8 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, if (entry_type == TYPE_EXTEND) { unsigned short entry_uniname[16], unichar; - if (step != DIRENT_STEP_NAME) { + if (step != DIRENT_STEP_NAME || + name_len >= MAX_NAME_LENGTH) { step = DIRENT_STEP_FILE; continue; } @@ -1101,12 +1152,19 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, rewind = 1; dentry = 0; clu.dir = p_dir->dir; - /* reset empty hint */ - num_empty = 0; - candi_empty.eidx = EXFAT_HINT_NONE; goto rewind; } + /* + * set the EXFAT_EOF_CLUSTER flag to avoid search + * from the beginning again when allocated a new cluster + */ + if (ei->hint_femp.eidx == EXFAT_HINT_NONE) { + ei->hint_femp.cur.dir = EXFAT_EOF_CLUSTER; + ei->hint_femp.eidx = p_dir->size * dentries_per_clu; + ei->hint_femp.count = 0; + } + /* initialized hint_stat */ hint_stat->clu = p_dir->dir; hint_stat->eidx = 0; @@ -1154,10 +1212,8 @@ int exfat_count_ext_entries(struct super_block *sb, struct exfat_chain *p_dir, type = exfat_get_entry_type(ext_ep); brelse(bh); - if (type == TYPE_EXTEND || type == TYPE_STREAM) + if (type & TYPE_CRITICAL_SEC || type & TYPE_BENIGN_SEC) count++; - else - break; } return count; } diff --git a/fs/exfat/exfat_fs.h b/fs/exfat/exfat_fs.h index 0db1f254212f2bde12b112c01d0ea64852530a09..b79f2fe2bea5478d92bfea0594a8c2c8f5812482 100644 --- a/fs/exfat/exfat_fs.h +++ b/fs/exfat/exfat_fs.h @@ -10,6 +10,11 @@ #include #include #include +#include + +#ifndef SECTOR_SIZE +#define SECTOR_SIZE 512 +#endif #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) #include @@ -50,7 +55,15 @@ enum { #define ES_2_ENTRIES 2 #define ES_ALL_ENTRIES 0 -#define DIR_DELETED 0xFFFF0321 +#define ES_IDX_FILE 0 +#define ES_IDX_STREAM 1 +#define ES_IDX_FIRST_FILENAME 2 +#define EXFAT_FILENAME_ENTRY_NUM(name_len) \ + DIV_ROUND_UP(name_len, EXFAT_FILE_NAME_LEN) +#define ES_IDX_LAST_FILENAME(name_len) \ + (ES_IDX_FIRST_FILENAME + EXFAT_FILENAME_ENTRY_NUM(name_len) - 1) + +#define DIR_DELETED 0xFFFFFFF7 /* type values */ #define TYPE_UNUSED 0x0000 @@ -71,15 +84,13 @@ enum { #define TYPE_PADDING 0x0402 #define TYPE_ACLTAB 0x0403 #define TYPE_BENIGN_SEC 0x0800 -#define TYPE_ALL 0x0FFF +#define TYPE_VENDOR_EXT 0x0801 +#define TYPE_VENDOR_ALLOC 0x0802 #define MAX_CHARSET_SIZE 6 /* max size of multi-byte character */ #define MAX_NAME_LENGTH 255 /* max len of file name excluding NULL */ #define MAX_VFSNAME_BUF_SIZE ((MAX_NAME_LENGTH + 1) * MAX_CHARSET_SIZE) -/* Enough size to hold 256 dentry (even 512 Byte sector) */ -#define DIR_CACHE_SIZE (256*sizeof(struct exfat_dentry)/512+1) - #define EXFAT_HINT_NONE -1 #define EXFAT_MIN_SUBDIR 2 @@ -104,11 +115,17 @@ enum { /* * helpers for block size to dentry size conversion. */ -#define EXFAT_B_TO_DEN_IDX(b, sbi) \ - ((b) << ((sbi)->cluster_size_bits - DENTRY_SIZE_BITS)) #define EXFAT_B_TO_DEN(b) ((b) >> DENTRY_SIZE_BITS) #define EXFAT_DEN_TO_B(b) ((b) << DENTRY_SIZE_BITS) +/* + * helpers for cluster size to dentry size conversion. + */ +#define EXFAT_CLU_TO_DEN(clu, sbi) \ + ((clu) << ((sbi)->cluster_size_bits - DENTRY_SIZE_BITS)) +#define EXFAT_DEN_TO_CLU(dentry, sbi) \ + ((dentry) >> ((sbi)->cluster_size_bits - DENTRY_SIZE_BITS)) + /* * helpers for fat entry. */ @@ -134,6 +151,17 @@ enum { #define BITS_PER_BYTE_MASK 0x7 #define IGNORED_BITS_REMAINED(clu, clu_base) ((1 << ((clu) - (clu_base))) - 1) +#define ES_ENTRY_NUM(name_len) (ES_IDX_LAST_FILENAME(name_len) + 1) +/* 19 entries = 1 file entry + 1 stream entry + 17 filename entries */ +#define ES_MAX_ENTRY_NUM ES_ENTRY_NUM(MAX_NAME_LENGTH) + +/* + * 19 entries x 32 bytes/entry = 608 bytes. + * The 608 bytes are in 3 sectors at most (even 512 Byte sector). + */ +#define DIR_CACHE_SIZE \ + (DIV_ROUND_UP(EXFAT_DEN_TO_B(ES_MAX_ENTRY_NUM), SECTOR_SIZE) + 1) + struct exfat_dentry_namebuf { char *lfn; int lfnbuf_len; /* usually MAX_UNINAME_BUF_SIZE */ @@ -175,13 +203,16 @@ struct exfat_hint { struct exfat_entry_set_cache { struct super_block *sb; - bool modified; unsigned int start_off; int num_bh; - struct buffer_head *bh[DIR_CACHE_SIZE]; + struct buffer_head *__bh[DIR_CACHE_SIZE]; + struct buffer_head **bh; unsigned int num_entries; + bool modified; }; +#define IS_DYNAMIC_ES(es) ((es)->__bh != (es)->bh) + struct exfat_dir_entry { struct exfat_chain dir; int entry; @@ -394,7 +425,7 @@ static inline sector_t exfat_cluster_to_sector(struct exfat_sb_info *sbi, sbi->data_start_sector; } -static inline int exfat_sector_to_cluster(struct exfat_sb_info *sbi, +static inline unsigned int exfat_sector_to_cluster(struct exfat_sb_info *sbi, sector_t sec) { return ((sec - sbi->data_start_sector) >> sbi->sect_per_clus_bits) + @@ -442,15 +473,23 @@ int exfat_trim_fs(struct inode *inode, struct fstrim_range *range); /* file.c */ extern const struct file_operations exfat_file_operations; -int __exfat_truncate(struct inode *inode, loff_t new_size); -void exfat_truncate(struct inode *inode, loff_t size); +int __exfat_truncate(struct inode *inode); +void exfat_truncate(struct inode *inode); #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) +int exfat_setattr(struct mnt_idmap *idmap, struct dentry *dentry, + struct iattr *attr); +int exfat_getattr(struct mnt_idmap *idmap, const struct path *path, + struct kstat *stat, unsigned int request_mask, + unsigned int query_flags); +#else int exfat_setattr(struct user_namespace *mnt_userns, struct dentry *dentry, struct iattr *attr); int exfat_getattr(struct user_namespace *mnt_userns, const struct path *path, struct kstat *stat, unsigned int request_mask, unsigned int query_flags); +#endif #else int exfat_setattr(struct dentry *dentry, struct iattr *attr); #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) @@ -496,15 +535,16 @@ void exfat_update_dir_chksum_with_entry_set(struct exfat_entry_set_cache *es); int exfat_calc_num_entries(struct exfat_uni_name *p_uniname); int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, struct exfat_chain *p_dir, struct exfat_uni_name *p_uniname, - int num_entries, unsigned int type, struct exfat_hint *hint_opt); + struct exfat_hint *hint_opt); int exfat_alloc_new_dir(struct inode *inode, struct exfat_chain *clu); struct exfat_dentry *exfat_get_dentry(struct super_block *sb, struct exfat_chain *p_dir, int entry, struct buffer_head **bh); struct exfat_dentry *exfat_get_dentry_cached(struct exfat_entry_set_cache *es, int num); -struct exfat_entry_set_cache *exfat_get_dentry_set(struct super_block *sb, - struct exfat_chain *p_dir, int entry, unsigned int type); -int exfat_free_dentry_set(struct exfat_entry_set_cache *es, int sync); +int exfat_get_dentry_set(struct exfat_entry_set_cache *es, + struct super_block *sb, struct exfat_chain *p_dir, int entry, + unsigned int type); +int exfat_put_dentry_set(struct exfat_entry_set_cache *es, int sync); int exfat_count_dir_entries(struct super_block *sb, struct exfat_chain *p_dir); /* inode.c */ diff --git a/fs/exfat/exfat_raw.h b/fs/exfat/exfat_raw.h index 7f39b1c6469c4e6938fc855ee4cd7a51ede9ec57..0ece2e43cf492c3a0fcc3dec0821623d9dcf485b 100644 --- a/fs/exfat/exfat_raw.h +++ b/fs/exfat/exfat_raw.h @@ -27,6 +27,7 @@ ((sbi)->num_clusters - EXFAT_RESERVED_CLUSTERS) /* AllocationPossible and NoFatChain field in GeneralSecondaryFlags Field */ +#define ALLOC_POSSIBLE 0x01 #define ALLOC_FAT_CHAIN 0x01 #define ALLOC_NO_FAT_CHAIN 0x03 @@ -50,6 +51,8 @@ #define EXFAT_STREAM 0xC0 /* stream entry */ #define EXFAT_NAME 0xC1 /* file name entry */ #define EXFAT_ACL 0xC2 /* stream entry */ +#define EXFAT_VENDOR_EXT 0xE0 /* vendor extension entry */ +#define EXFAT_VENDOR_ALLOC 0xE1 /* vendor allocation entry */ #define IS_EXFAT_CRITICAL_PRI(x) (x < 0xA0) #define IS_EXFAT_BENIGN_PRI(x) (x < 0xC0) @@ -155,6 +158,24 @@ struct exfat_dentry { __le32 start_clu; __le64 size; } __packed upcase; /* up-case table directory entry */ + struct { + __u8 flags; + __u8 vendor_guid[16]; + __u8 vendor_defined[14]; + } __packed vendor_ext; /* vendor extension directory entry */ + struct { + __u8 flags; + __u8 vendor_guid[16]; + __u8 vendor_defined[2]; + __le32 start_clu; + __le64 size; + } __packed vendor_alloc; /* vendor allocation directory entry */ + struct { + __u8 flags; + __u8 custom_defined[18]; + __le32 start_clu; + __le64 size; + } __packed generic_secondary; /* generic secondary directory entry */ } __packed dentry; } __packed; diff --git a/fs/exfat/fatent.c b/fs/exfat/fatent.c index ded465bcf84b881417a734fa4e63566573f5e9fe..c13a04e94ebcbb9c71667c810242b33d2c01f01a 100644 --- a/fs/exfat/fatent.c +++ b/fs/exfat/fatent.c @@ -322,7 +322,7 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, struct exfat_chain *p_chain, bool sync_bmap) { int ret = -ENOSPC; - unsigned int num_clusters = 0, total_cnt; + unsigned int total_cnt; unsigned int hint_clu, new_clu, last_clu = EXFAT_EOF_CLUSTER; struct super_block *sb = inode->i_sb; struct exfat_sb_info *sbi = EXFAT_SB(sb); @@ -359,17 +359,11 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, /* check cluster validation */ if (!is_valid_cluster(sbi, hint_clu)) { - exfat_err(sb, "hint_cluster is invalid (%u)", - hint_clu); + if (hint_clu != sbi->num_clusters) + exfat_err(sb, "hint_cluster is invalid (%u), rewind to the first cluster", + hint_clu); hint_clu = EXFAT_FIRST_CLUSTER; - if (p_chain->flags == ALLOC_NO_FAT_CHAIN) { - if (exfat_chain_cont_cluster(sb, p_chain->dir, - num_clusters)) { - ret = -EIO; - goto unlock; - } - p_chain->flags = ALLOC_FAT_CHAIN; - } + p_chain->flags = ALLOC_FAT_CHAIN; } p_chain->dir = EXFAT_EOF_CLUSTER; @@ -379,7 +373,7 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, if (new_clu != hint_clu && p_chain->flags == ALLOC_NO_FAT_CHAIN) { if (exfat_chain_cont_cluster(sb, p_chain->dir, - num_clusters)) { + p_chain->size)) { ret = -EIO; goto free_cluster; } @@ -392,8 +386,6 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, goto free_cluster; } - num_clusters++; - /* update FAT table */ if (p_chain->flags == ALLOC_FAT_CHAIN) { if (exfat_ent_set(sb, new_clu, EXFAT_EOF_CLUSTER)) { @@ -410,13 +402,14 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, goto free_cluster; } } + p_chain->size++; + last_clu = new_clu; - if (--num_alloc == 0) { + if (p_chain->size == num_alloc) { sbi->clu_srch_ptr = hint_clu; - sbi->used_clusters += num_clusters; + sbi->used_clusters += num_alloc; - p_chain->size += num_clusters; mutex_unlock(&sbi->bitmap_lock); return 0; } @@ -427,7 +420,7 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, if (p_chain->flags == ALLOC_NO_FAT_CHAIN) { if (exfat_chain_cont_cluster(sb, p_chain->dir, - num_clusters)) { + p_chain->size)) { ret = -EIO; goto free_cluster; } @@ -436,8 +429,7 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, } } free_cluster: - if (num_clusters) - __exfat_free_cluster(inode, p_chain); + __exfat_free_cluster(inode, p_chain); unlock: mutex_unlock(&sbi->bitmap_lock); return ret; diff --git a/fs/exfat/file.c b/fs/exfat/file.c index 6e37277bbd84475c3aed7052631bcb464f96712e..e35998f5aa8c40e107349a95c454fdbfc3f8b9a8 100644 --- a/fs/exfat/file.c +++ b/fs/exfat/file.c @@ -100,7 +100,7 @@ static int exfat_sanitize_mode(const struct exfat_sb_info *sbi, } /* resize the file length */ -int __exfat_truncate(struct inode *inode, loff_t new_size) +int __exfat_truncate(struct inode *inode) { unsigned int num_clusters_new, num_clusters_phys; unsigned int last_clu = EXFAT_FREE_CLUSTER; @@ -120,7 +120,7 @@ int __exfat_truncate(struct inode *inode, loff_t new_size) exfat_chain_set(&clu, ei->start_clu, num_clusters_phys, ei->flags); - if (new_size > 0) { + if (i_size_read(inode) > 0) { /* * Truncate FAT chain num_clusters after the first cluster * num_clusters = min(new, phys); @@ -150,8 +150,6 @@ int __exfat_truncate(struct inode *inode, loff_t new_size) ei->start_clu = EXFAT_EOF_CLUSTER; } - i_size_write(inode, new_size); - if (ei->type == TYPE_FILE) ei->attr |= ATTR_ARCHIVE; @@ -196,7 +194,7 @@ int __exfat_truncate(struct inode *inode, loff_t new_size) return 0; } -void exfat_truncate(struct inode *inode, loff_t size) +void exfat_truncate(struct inode *inode) { struct super_block *sb = inode->i_sb; struct exfat_sb_info *sbi = EXFAT_SB(sb); @@ -218,12 +216,11 @@ void exfat_truncate(struct inode *inode, loff_t size) goto write_size; } - err = __exfat_truncate(inode, i_size_read(inode)); + err = __exfat_truncate(inode); if (err) goto write_size; - inode->i_blocks = round_up(i_size_read(inode), sbi->cluster_size) >> - inode->i_blkbits; + inode->i_blocks = round_up(i_size_read(inode), sbi->cluster_size) >> 9; write_size: aligned_size = i_size_read(inode); if (aligned_size & (blocksize - 1)) { @@ -240,9 +237,15 @@ void exfat_truncate(struct inode *inode, loff_t size) } #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) +int exfat_getattr(struct mnt_idmap *idmap, const struct path *path, + struct kstat *stat, unsigned int request_mask, + unsigned int query_flags) +#else int exfat_getattr(struct user_namespace *mnt_uerns, const struct path *path, struct kstat *stat, unsigned int request_mask, unsigned int query_flags) +#endif #else #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) int exfat_getattr(const struct path *path, struct kstat *stat, @@ -261,7 +264,11 @@ int exfat_getattr(struct vfsmount *mnt, struct dentry *dentry, #endif #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + generic_fillattr(&nop_mnt_idmap, inode, stat); +#else generic_fillattr(&init_user_ns, inode, stat); +#endif #else generic_fillattr(inode, stat); #endif @@ -276,8 +283,13 @@ int exfat_getattr(struct vfsmount *mnt, struct dentry *dentry, } #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) +int exfat_setattr(struct mnt_idmap *idmap, struct dentry *dentry, + struct iattr *attr) +#else int exfat_setattr(struct user_namespace *mnt_userns, struct dentry *dentry, struct iattr *attr) +#endif #else int exfat_setattr(struct dentry *dentry, struct iattr *attr) #endif @@ -307,7 +319,11 @@ int exfat_setattr(struct dentry *dentry, struct iattr *attr) (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 37))) || \ (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)) #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + error = setattr_prepare(&nop_mnt_idmap, dentry, attr); +#else error = setattr_prepare(&init_user_ns, dentry, attr); +#endif #else error = setattr_prepare(dentry, attr); #endif @@ -345,7 +361,11 @@ int exfat_setattr(struct dentry *dentry, struct iattr *attr) #endif #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + setattr_copy(&nop_mnt_idmap, inode, attr); +#else setattr_copy(&init_user_ns, inode, attr); +#endif #else setattr_copy(inode, attr); #endif @@ -362,7 +382,7 @@ int exfat_setattr(struct dentry *dentry, struct iattr *attr) * __exfat_write_inode() is called from exfat_truncate(), inode * is already written by it, so mark_inode_dirty() is unneeded. */ - exfat_truncate(inode, attr->ia_size); + exfat_truncate(inode); up_write(&EXFAT_I(inode)->truncate_lock); } else mark_inode_dirty(inode); @@ -463,7 +483,11 @@ const struct file_operations exfat_file_operations = { #endif .mmap = generic_file_mmap, .fsync = exfat_file_fsync, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 5, 0) + .splice_read = filemap_splice_read, +#else .splice_read = generic_file_splice_read, +#endif .splice_write = iter_file_splice_write, }; diff --git a/fs/exfat/inode.c b/fs/exfat/inode.c index f3dbeb300c64a2c9f022424f3b24c8e756b49be2..4d4449e1df3d5a8145447834a051119fa416197b 100644 --- a/fs/exfat/inode.c +++ b/fs/exfat/inode.c @@ -23,7 +23,7 @@ int __exfat_write_inode(struct inode *inode, int sync) { unsigned long long on_disk_size; struct exfat_dentry *ep, *ep2; - struct exfat_entry_set_cache *es = NULL; + struct exfat_entry_set_cache es; struct super_block *sb = inode->i_sb; struct exfat_sb_info *sbi = EXFAT_SB(sb); struct exfat_inode_info *ei = EXFAT_I(inode); @@ -44,11 +44,10 @@ int __exfat_write_inode(struct inode *inode, int sync) exfat_set_volume_dirty(sb); /* get the directory entry of given file or directory */ - es = exfat_get_dentry_set(sb, &(ei->dir), ei->entry, ES_ALL_ENTRIES); - if (!es) + if (exfat_get_dentry_set(&es, sb, &(ei->dir), ei->entry, ES_ALL_ENTRIES)) return -EIO; - ep = exfat_get_dentry_cached(es, 0); - ep2 = exfat_get_dentry_cached(es, 1); + ep = exfat_get_dentry_cached(&es, ES_IDX_FILE); + ep2 = exfat_get_dentry_cached(&es, ES_IDX_STREAM); ep->dentry.file.attr = cpu_to_le16(exfat_make_attr(inode)); @@ -85,8 +84,8 @@ int __exfat_write_inode(struct inode *inode, int sync) ep2->dentry.stream.start_clu = EXFAT_FREE_CLUSTER; } - exfat_update_dir_chksum_with_entry_set(es); - return exfat_free_dentry_set(es, sync); + exfat_update_dir_chksum_with_entry_set(&es); + return exfat_put_dentry_set(&es, sync); } int exfat_write_inode(struct inode *inode, struct writeback_control *wbc) @@ -223,8 +222,7 @@ static int exfat_map_cluster(struct inode *inode, unsigned int clu_offset, num_clusters += num_to_be_allocated; *clu = new_clu.dir; - inode->i_blocks += - num_to_be_allocated << sbi->sect_per_clus_bits; + inode->i_blocks += EXFAT_CLU_TO_B(num_to_be_allocated, sbi) >> 9; /* * Move *clu pointer along FAT chains (hole care) because the @@ -362,10 +360,12 @@ static int exfat_readpages(struct file *file, struct address_space *mapping, } #endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0) static int exfat_writepage(struct page *page, struct writeback_control *wbc) { return block_write_full_page(page, exfat_get_block, wbc); } +#endif static int exfat_writepages(struct address_space *mapping, struct writeback_control *wbc) @@ -384,7 +384,7 @@ static void exfat_write_failed(struct address_space *mapping, loff_t to) #else inode->i_mtime = inode->i_ctime = CURRENT_TIME_SEC; #endif - exfat_truncate(inode, EXFAT_I(inode)->i_size_aligned); + exfat_truncate(inode); } } @@ -533,12 +533,19 @@ static const struct address_space_operations exfat_aops = { #else .readpages = exfat_readpages, #endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0) .writepage = exfat_writepage, +#endif .writepages = exfat_writepages, .write_begin = exfat_write_begin, .write_end = exfat_write_end, .direct_IO = exfat_direct_IO, +#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0) .bmap = exfat_aop_bmap +#else + .bmap = exfat_aop_bmap, + .migrate_folio = buffer_migrate_folio, +#endif }; static inline unsigned long exfat_hash(loff_t i_pos) @@ -616,7 +623,11 @@ static int exfat_fill_inode(struct inode *inode, struct exfat_dir_entry *info) #else inode->i_version++; #endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) + inode->i_generation = get_random_u32(); +#else inode->i_generation = prandom_u32(); +#endif if (info->attr & ATTR_SUBDIR) { /* directory */ inode->i_generation &= ~1; @@ -646,8 +657,7 @@ static int exfat_fill_inode(struct inode *inode, struct exfat_dir_entry *info) exfat_save_attr(inode, info->attr); - inode->i_blocks = round_up(i_size_read(inode), sbi->cluster_size) >> - inode->i_blkbits; + inode->i_blocks = round_up(i_size_read(inode), sbi->cluster_size) >> 9; inode->i_mtime = info->mtime; inode->i_ctime = info->mtime; ei->i_crtime = info->crtime; @@ -695,7 +705,7 @@ void exfat_evict_inode(struct inode *inode) if (!inode->i_nlink) { i_size_write(inode, 0); mutex_lock(&EXFAT_SB(inode->i_sb)->s_lock); - __exfat_truncate(inode, 0); + __exfat_truncate(inode); mutex_unlock(&EXFAT_SB(inode->i_sb)->s_lock); } diff --git a/fs/exfat/namei.c b/fs/exfat/namei.c index 3342f29a768320dc184c20f643aaca0f4295e08d..e6971c758892aa89534040448647dad2e825d042 100644 --- a/fs/exfat/namei.c +++ b/fs/exfat/namei.c @@ -251,11 +251,18 @@ static int exfat_search_empty_slot(struct super_block *sb, if (hint_femp->eidx != EXFAT_HINT_NONE) { dentry = hint_femp->eidx; - if (num_entries <= hint_femp->count) { - hint_femp->eidx = EXFAT_HINT_NONE; - return dentry; - } + /* + * If hint_femp->count is enough, it is needed to check if + * there are actual empty entries. + * Otherwise, and if "dentry + hint_famp->count" is also equal + * to "p_dir->size * dentries_per_clu", it means ENOSPC. + */ + if (dentry + hint_femp->count == p_dir->size * dentries_per_clu && + num_entries > hint_femp->count) + return -ENOSPC; + + hint_femp->eidx = EXFAT_HINT_NONE; exfat_chain_dup(&clu, &hint_femp->cur); } else { exfat_chain_dup(&clu, p_dir); @@ -320,6 +327,12 @@ static int exfat_search_empty_slot(struct super_block *sb, } } + hint_femp->eidx = p_dir->size * dentries_per_clu - num_empty; + hint_femp->count = num_empty; + if (num_empty == 0) + exfat_chain_set(&hint_femp->cur, EXFAT_EOF_CLUSTER, 0, + clu.flags); + return -ENOSPC; } @@ -396,15 +409,11 @@ static int exfat_find_empty_entry(struct inode *inode, if (exfat_ent_set(sb, last_clu, clu.dir)) return -EIO; - if (hint_femp.eidx == EXFAT_HINT_NONE) { - /* the special case that new dentry - * should be allocated from the start of new cluster - */ - hint_femp.eidx = EXFAT_B_TO_DEN_IDX(p_dir->size, sbi); - hint_femp.count = sbi->dentries_per_clu; - + if (hint_femp.cur.dir == EXFAT_EOF_CLUSTER) exfat_chain_set(&hint_femp.cur, clu.dir, 0, clu.flags); - } + + hint_femp.count += sbi->dentries_per_clu; + hint_femp.cur.size++; p_dir->size++; size = EXFAT_CLU_TO_B(p_dir->size, sbi); @@ -414,7 +423,7 @@ static int exfat_find_empty_entry(struct inode *inode, ei->i_size_ondisk += sbi->cluster_size; ei->i_size_aligned += sbi->cluster_size; ei->flags = p_dir->flags; - inode->i_blocks += 1 << sbi->sect_per_clus_bits; + inode->i_blocks += sbi->cluster_size >> 9; } return dentry; @@ -570,8 +579,13 @@ static int exfat_add_entry(struct inode *inode, const char *path, } #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) +static int exfat_create(struct mnt_idmap *idmap, struct inode *dir, + struct dentry *dentry, umode_t mode, bool excl) +#else static int exfat_create(struct user_namespace *mnt_userns, struct inode *dir, struct dentry *dentry, umode_t mode, bool excl) +#endif #else static int exfat_create(struct inode *dir, struct dentry *dentry, umode_t mode, bool excl) @@ -638,14 +652,14 @@ static int exfat_create(struct inode *dir, struct dentry *dentry, umode_t mode, static int exfat_find(struct inode *dir, struct qstr *qname, struct exfat_dir_entry *info) { - int ret, dentry, num_entries, count; + int ret, dentry, count; struct exfat_chain cdir; struct exfat_uni_name uni_name; struct super_block *sb = dir->i_sb; struct exfat_sb_info *sbi = EXFAT_SB(sb); struct exfat_inode_info *ei = EXFAT_I(dir); struct exfat_dentry *ep, *ep2; - struct exfat_entry_set_cache *es; + struct exfat_entry_set_cache es; /* for optimized dir & entry to prevent long traverse of cluster chain */ struct exfat_hint hint_opt; @@ -657,10 +671,6 @@ static int exfat_find(struct inode *dir, struct qstr *qname, if (ret) return ret; - num_entries = exfat_calc_num_entries(&uni_name); - if (num_entries < 0) - return num_entries; - /* check the validation of hint_stat and initialize it if required */ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 16, 0) if (ei->version != (inode_peek_iversion_raw(dir) & 0xffffffff)) { @@ -678,9 +688,7 @@ static int exfat_find(struct inode *dir, struct qstr *qname, } /* search the file name for directories */ - dentry = exfat_find_dir_entry(sb, ei, &cdir, &uni_name, - num_entries, TYPE_ALL, &hint_opt); - + dentry = exfat_find_dir_entry(sb, ei, &cdir, &uni_name, &hint_opt); if (dentry < 0) return dentry; /* -error value */ @@ -693,11 +701,10 @@ static int exfat_find(struct inode *dir, struct qstr *qname, if (cdir.flags & ALLOC_NO_FAT_CHAIN) cdir.size -= dentry / sbi->dentries_per_clu; dentry = hint_opt.eidx; - es = exfat_get_dentry_set(sb, &cdir, dentry, ES_2_ENTRIES); - if (!es) + if (exfat_get_dentry_set(&es, sb, &cdir, dentry, ES_2_ENTRIES)) return -EIO; - ep = exfat_get_dentry_cached(es, 0); - ep2 = exfat_get_dentry_cached(es, 1); + ep = exfat_get_dentry_cached(&es, ES_IDX_FILE); + ep2 = exfat_get_dentry_cached(&es, ES_IDX_STREAM); info->type = exfat_get_entry_type(ep); info->attr = le16_to_cpu(ep->dentry.file.attr); @@ -726,7 +733,7 @@ static int exfat_find(struct inode *dir, struct qstr *qname, ep->dentry.file.access_time, ep->dentry.file.access_date, 0); - exfat_free_dentry_set(es, false); + exfat_put_dentry_set(&es, false); if (ei->start_clu == EXFAT_FREE_CLUSTER) { exfat_fs_error(sb, @@ -911,8 +918,13 @@ static int exfat_unlink(struct inode *dir, struct dentry *dentry) } #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) +static int exfat_mkdir(struct mnt_idmap *idmap, struct inode *dir, + struct dentry *dentry, umode_t mode) +#else static int exfat_mkdir(struct user_namespace *mnt_userns, struct inode *dir, struct dentry *dentry, umode_t mode) +#endif #else static int exfat_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) #endif @@ -1283,7 +1295,7 @@ static int __exfat_rename(struct inode *old_parent_inode, struct exfat_inode_info *new_ei = NULL; unsigned int new_entry_type = TYPE_UNUSED; int new_entry = 0; - struct buffer_head *old_bh, *new_bh = NULL; + struct buffer_head *new_bh = NULL; /* check the validity of pointer parameters */ if (new_path == NULL || strlen(new_path) == 0) @@ -1299,13 +1311,6 @@ static int __exfat_rename(struct inode *old_parent_inode, EXFAT_I(old_parent_inode)->flags); dentry = ei->entry; - ep = exfat_get_dentry(sb, &olddir, dentry, &old_bh); - if (!ep) { - ret = -EIO; - goto out; - } - brelse(old_bh); - /* check whether new dir is existing directory and empty */ if (new_inode) { ret = -EIO; @@ -1407,10 +1412,17 @@ static int __exfat_rename(struct inode *old_parent_inode, } #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) +static int exfat_rename(struct mnt_idmap *idmap, + struct inode *old_dir, struct dentry *old_dentry, + struct inode *new_dir, struct dentry *new_dentry, + unsigned int flags) +#else static int exfat_rename(struct user_namespace *mnt_userns, struct inode *old_dir, struct dentry *old_dentry, struct inode *new_dir, struct dentry *new_dentry, unsigned int flags) +#endif #else #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) static int exfat_rename(struct inode *old_dir, struct dentry *old_dentry, diff --git a/fs/exfat/super.c b/fs/exfat/super.c index c5d55b0308a912a2e05ecb855cfd9f38c9626563..665c296e4ad43d9271cccc08bde3cf2b7588c557 100644 --- a/fs/exfat/super.c +++ b/fs/exfat/super.c @@ -632,8 +632,7 @@ static int exfat_read_root(struct inode *inode) inode->i_op = &exfat_dir_inode_operations; inode->i_fop = &exfat_dir_operations; - inode->i_blocks = round_up(i_size_read(inode), sbi->cluster_size) >> - inode->i_blkbits; + inode->i_blocks = round_up(i_size_read(inode), sbi->cluster_size) >> 9; ei->i_pos = ((loff_t)sbi->root_dir << 32) | 0xffffffff; ei->i_size_aligned = i_size_read(inode); ei->i_size_ondisk = i_size_read(inode); diff --git a/fs/ext2/ext2.h b/fs/ext2/ext2.h index 00e759f051619cfd37a58108265bc9f798554a21..598dc28748086e376484b93b7d6c43a3b60cb190 100644 --- a/fs/ext2/ext2.h +++ b/fs/ext2/ext2.h @@ -68,10 +68,7 @@ struct mb_cache; * second extended-fs super-block data in memory */ struct ext2_sb_info { - unsigned long s_frag_size; /* Size of a fragment in bytes */ - unsigned long s_frags_per_block;/* Number of fragments per block */ unsigned long s_inodes_per_block;/* Number of inodes per block */ - unsigned long s_frags_per_group;/* Number of fragments in a group */ unsigned long s_blocks_per_group;/* Number of blocks in a group */ unsigned long s_inodes_per_group;/* Number of inodes in a group */ unsigned long s_itb_per_group; /* Number of inode table blocks per group */ @@ -177,6 +174,7 @@ static inline struct ext2_sb_info *EXT2_SB(struct super_block *sb) #define EXT2_MIN_BLOCK_SIZE 1024 #define EXT2_MAX_BLOCK_SIZE 4096 #define EXT2_MIN_BLOCK_LOG_SIZE 10 +#define EXT2_MAX_BLOCK_LOG_SIZE 16 #define EXT2_BLOCK_SIZE(s) ((s)->s_blocksize) #define EXT2_ADDR_PER_BLOCK(s) (EXT2_BLOCK_SIZE(s) / sizeof (__u32)) #define EXT2_BLOCK_SIZE_BITS(s) ((s)->s_blocksize_bits) @@ -184,15 +182,6 @@ static inline struct ext2_sb_info *EXT2_SB(struct super_block *sb) #define EXT2_INODE_SIZE(s) (EXT2_SB(s)->s_inode_size) #define EXT2_FIRST_INO(s) (EXT2_SB(s)->s_first_ino) -/* - * Macro-instructions used to manage fragments - */ -#define EXT2_MIN_FRAG_SIZE 1024 -#define EXT2_MAX_FRAG_SIZE 4096 -#define EXT2_MIN_FRAG_LOG_SIZE 10 -#define EXT2_FRAG_SIZE(s) (EXT2_SB(s)->s_frag_size) -#define EXT2_FRAGS_PER_BLOCK(s) (EXT2_SB(s)->s_frags_per_block) - /* * Structure of a blocks group descriptor */ diff --git a/fs/ext2/super.c b/fs/ext2/super.c index 44a1f356aca295c5e926e3f0bfcc3fae2446c1a2..5c0af53f2e8fcb52c5e92c8f63e94cd768c33aa9 100644 --- a/fs/ext2/super.c +++ b/fs/ext2/super.c @@ -691,10 +691,9 @@ static int ext2_setup_super (struct super_block * sb, es->s_max_mnt_count = cpu_to_le16(EXT2_DFL_MAX_MNT_COUNT); le16_add_cpu(&es->s_mnt_count, 1); if (test_opt (sb, DEBUG)) - ext2_msg(sb, KERN_INFO, "%s, %s, bs=%lu, fs=%lu, gc=%lu, " + ext2_msg(sb, KERN_INFO, "%s, %s, bs=%lu, gc=%lu, " "bpg=%lu, ipg=%lu, mo=%04lx]", EXT2FS_VERSION, EXT2FS_DATE, sb->s_blocksize, - sbi->s_frag_size, sbi->s_groups_count, EXT2_BLOCKS_PER_GROUP(sb), EXT2_INODES_PER_GROUP(sb), @@ -978,6 +977,13 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent) goto failed_mount; } + if (le32_to_cpu(es->s_log_block_size) > + (EXT2_MAX_BLOCK_LOG_SIZE - BLOCK_SIZE_BITS)) { + ext2_msg(sb, KERN_ERR, + "Invalid log block size: %u", + le32_to_cpu(es->s_log_block_size)); + goto failed_mount; + } blocksize = BLOCK_SIZE << le32_to_cpu(sbi->s_es->s_log_block_size); if (sbi->s_mount_opt & EXT2_MOUNT_DAX) { @@ -1033,14 +1039,7 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent) } } - sbi->s_frag_size = EXT2_MIN_FRAG_SIZE << - le32_to_cpu(es->s_log_frag_size); - if (sbi->s_frag_size == 0) - goto cantfind_ext2; - sbi->s_frags_per_block = sb->s_blocksize / sbi->s_frag_size; - sbi->s_blocks_per_group = le32_to_cpu(es->s_blocks_per_group); - sbi->s_frags_per_group = le32_to_cpu(es->s_frags_per_group); sbi->s_inodes_per_group = le32_to_cpu(es->s_inodes_per_group); if (EXT2_INODE_SIZE(sb) == 0) @@ -1068,11 +1067,10 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent) goto failed_mount; } - if (sb->s_blocksize != sbi->s_frag_size) { + if (es->s_log_frag_size != es->s_log_block_size) { ext2_msg(sb, KERN_ERR, - "error: fragsize %lu != blocksize %lu" - "(not supported yet)", - sbi->s_frag_size, sb->s_blocksize); + "error: fragsize log %u != blocksize log %u", + le32_to_cpu(es->s_log_frag_size), sb->s_blocksize_bits); goto failed_mount; } @@ -1082,12 +1080,6 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent) sbi->s_blocks_per_group); goto failed_mount; } - if (sbi->s_frags_per_group > sb->s_blocksize * 8) { - ext2_msg(sb, KERN_ERR, - "error: #fragments per group too big: %lu", - sbi->s_frags_per_group); - goto failed_mount; - } if (sbi->s_inodes_per_group < sbi->s_inodes_per_block || sbi->s_inodes_per_group > sb->s_blocksize * 8) { ext2_msg(sb, KERN_ERR, diff --git a/fs/ext2/xattr.c b/fs/ext2/xattr.c index bd1d68ff3a9f81ffecb3c4138cd646532ba3733c..437175bce22e803aa43c6390ca37692e8cc3efbc 100644 --- a/fs/ext2/xattr.c +++ b/fs/ext2/xattr.c @@ -664,10 +664,10 @@ ext2_xattr_set2(struct inode *inode, struct buffer_head *old_bh, /* We need to allocate a new block */ ext2_fsblk_t goal = ext2_group_first_block_no(sb, EXT2_I(inode)->i_block_group); - int block = ext2_new_block(inode, goal, &error); + ext2_fsblk_t block = ext2_new_block(inode, goal, &error); if (error) goto cleanup; - ea_idebug(inode, "creating block %d", block); + ea_idebug(inode, "creating block %lu", block); new_bh = sb_getblk(sb, block); if (unlikely(!new_bh)) { diff --git a/fs/ext4/acl.h b/fs/ext4/acl.h index 9b63f5416a2f057d1dd7000b41d43e1b56e32b49..7f3b25b3fa6d3a02567d5c537174125cb2787fa3 100644 --- a/fs/ext4/acl.h +++ b/fs/ext4/acl.h @@ -67,6 +67,11 @@ extern int ext4_init_acl(handle_t *, struct inode *, struct inode *); static inline int ext4_init_acl(handle_t *handle, struct inode *inode, struct inode *dir) { + /* usually, the umask is applied by posix_acl_create(), but if + ext4 ACL support is disabled at compile time, we need to do + it here, because posix_acl_create() will never be called */ + inode->i_mode &= ~current_umask(); + return 0; } #endif /* CONFIG_EXT4_FS_POSIX_ACL */ diff --git a/fs/ext4/balloc.c b/fs/ext4/balloc.c index f9645de9d04cc55410f779df7cd0eea36670c9e8..9761aeb4b2248f91c155f98d657165662d39736f 100644 --- a/fs/ext4/balloc.c +++ b/fs/ext4/balloc.c @@ -303,6 +303,22 @@ struct ext4_group_desc * ext4_get_group_desc(struct super_block *sb, return desc; } +static ext4_fsblk_t ext4_valid_block_bitmap_padding(struct super_block *sb, + ext4_group_t block_group, + struct buffer_head *bh) +{ + ext4_grpblk_t next_zero_bit; + unsigned long bitmap_size = sb->s_blocksize * 8; + unsigned int offset = num_clusters_in_group(sb, block_group); + + if (bitmap_size <= offset) + return 0; + + next_zero_bit = ext4_find_next_zero_bit(bh->b_data, bitmap_size, offset); + + return (next_zero_bit < bitmap_size ? next_zero_bit : 0); +} + /* * Return the block number which was discovered to be invalid, or 0 if * the block bitmap is valid. @@ -395,6 +411,15 @@ static int ext4_validate_block_bitmap(struct super_block *sb, EXT4_GROUP_INFO_BBITMAP_CORRUPT); return -EFSCORRUPTED; } + blk = ext4_valid_block_bitmap_padding(sb, block_group, bh); + if (unlikely(blk != 0)) { + ext4_unlock_group(sb, block_group); + ext4_error(sb, "bg %u: block %llu: padding at end of block bitmap is not set", + block_group, blk); + ext4_mark_group_bitmap_corrupted(sb, block_group, + EXT4_GROUP_INFO_BBITMAP_CORRUPT); + return -EFSCORRUPTED; + } set_buffer_verified(bh); verified: ext4_unlock_group(sb, block_group); diff --git a/fs/ext4/ext4.h b/fs/ext4/ext4.h index 0136402cef979989ae68809ca8fc4f54409142a1..57abebbc7308676a2dc74393a1497f407731d119 100644 --- a/fs/ext4/ext4.h +++ b/fs/ext4/ext4.h @@ -933,11 +933,13 @@ do { \ * where the second inode has larger inode number * than the first * I_DATA_SEM_QUOTA - Used for quota inodes only + * I_DATA_SEM_EA - Used for ea_inodes only */ enum { I_DATA_SEM_NORMAL = 0, I_DATA_SEM_OTHER, I_DATA_SEM_QUOTA, + I_DATA_SEM_EA }; @@ -1417,7 +1419,7 @@ struct ext4_sb_info { unsigned long s_commit_interval; u32 s_max_batch_time; u32 s_min_batch_time; - struct block_device *journal_bdev; + struct block_device *s_journal_bdev; #ifdef CONFIG_QUOTA /* Names of quota files with journalled quota */ char __rcu *s_qf_names[EXT4_MAXQUOTAS]; @@ -1505,7 +1507,7 @@ struct ext4_sb_info { struct task_struct *s_mmp_tsk; /* record the last minlen when FITRIM is called. */ - atomic_t s_last_trim_minblks; + unsigned long s_last_trim_minblks; /* Reference to checksum algorithm driver via cryptoapi */ struct crypto_shash *s_chksum_driver; diff --git a/fs/ext4/extents.c b/fs/ext4/extents.c index cf03f293e3b2d029e5e8d940f9079bccacde4d48..fd63fb42df09f08757a2a0a7907e76effb80944e 100644 --- a/fs/ext4/extents.c +++ b/fs/ext4/extents.c @@ -997,6 +997,11 @@ static int ext4_ext_insert_index(handle_t *handle, struct inode *inode, ix = curp->p_idx; } + if (unlikely(ix > EXT_MAX_INDEX(curp->p_hdr))) { + EXT4_ERROR_INODE(inode, "ix > EXT_MAX_INDEX!"); + return -EFSCORRUPTED; + } + len = EXT_LAST_INDEX(curp->p_hdr) - ix + 1; BUG_ON(len < 0); if (len > 0) { @@ -1006,11 +1011,6 @@ static int ext4_ext_insert_index(handle_t *handle, struct inode *inode, memmove(ix + 1, ix, len * sizeof(struct ext4_extent_idx)); } - if (unlikely(ix > EXT_MAX_INDEX(curp->p_hdr))) { - EXT4_ERROR_INODE(inode, "ix > EXT_MAX_INDEX!"); - return -EFSCORRUPTED; - } - ix->ei_block = cpu_to_le32(logical); ext4_idx_store_pblock(ix, ptr); le16_add_cpu(&curp->p_hdr->eh_entries, 1); diff --git a/fs/ext4/fsmap.c b/fs/ext4/fsmap.c index 6f3f245f3a8032fefb771d96d3bfab5fe6d5c50c..69c76327792e0aa763a957f8b34938bf60e231cd 100644 --- a/fs/ext4/fsmap.c +++ b/fs/ext4/fsmap.c @@ -486,6 +486,8 @@ static int ext4_getfsmap_datadev(struct super_block *sb, keys[0].fmr_physical = bofs; if (keys[1].fmr_physical >= eofs) keys[1].fmr_physical = eofs - 1; + if (keys[1].fmr_physical < keys[0].fmr_physical) + return 0; start_fsb = keys[0].fmr_physical; end_fsb = keys[1].fmr_physical; @@ -574,8 +576,8 @@ static bool ext4_getfsmap_is_valid_device(struct super_block *sb, if (fm->fmr_device == 0 || fm->fmr_device == UINT_MAX || fm->fmr_device == new_encode_dev(sb->s_bdev->bd_dev)) return true; - if (EXT4_SB(sb)->journal_bdev && - fm->fmr_device == new_encode_dev(EXT4_SB(sb)->journal_bdev->bd_dev)) + if (EXT4_SB(sb)->s_journal_bdev && + fm->fmr_device == new_encode_dev(EXT4_SB(sb)->s_journal_bdev->bd_dev)) return true; return false; } @@ -645,9 +647,9 @@ int ext4_getfsmap(struct super_block *sb, struct ext4_fsmap_head *head, memset(handlers, 0, sizeof(handlers)); handlers[0].gfd_dev = new_encode_dev(sb->s_bdev->bd_dev); handlers[0].gfd_fn = ext4_getfsmap_datadev; - if (EXT4_SB(sb)->journal_bdev) { + if (EXT4_SB(sb)->s_journal_bdev) { handlers[1].gfd_dev = new_encode_dev( - EXT4_SB(sb)->journal_bdev->bd_dev); + EXT4_SB(sb)->s_journal_bdev->bd_dev); handlers[1].gfd_fn = ext4_getfsmap_logdev; } diff --git a/fs/ext4/indirect.c b/fs/ext4/indirect.c index 0cc0d22c08569d43c3e69ce5b4e552aee1af972e..9bf711d63368c7b2d5648cbab7ec34f6b34b3ebc 100644 --- a/fs/ext4/indirect.c +++ b/fs/ext4/indirect.c @@ -642,6 +642,14 @@ int ext4_ind_map_blocks(handle_t *handle, struct inode *inode, ext4_update_inode_fsync_trans(handle, inode, 1); count = ar.len; + + /* + * Update reserved blocks/metadata blocks after successful block + * allocation which had been deferred till now. + */ + if (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE) + ext4_da_update_reserve_space(inode, count, 1); + got_it: map->m_flags |= EXT4_MAP_MAPPED; map->m_pblk = le32_to_cpu(chain[depth-1].key); diff --git a/fs/ext4/inline.c b/fs/ext4/inline.c index 46130db20c88221bc1bb7608eccc3ed3d411fab7..d04c772f0958b9a8de5b4da73535947ad01e545c 100644 --- a/fs/ext4/inline.c +++ b/fs/ext4/inline.c @@ -33,6 +33,7 @@ static int get_max_inline_xattr_value_size(struct inode *inode, struct ext4_xattr_ibody_header *header; struct ext4_xattr_entry *entry; struct ext4_inode *raw_inode; + void *end; int free, min_offs; if (!EXT4_INODE_HAS_XATTR_SPACE(inode)) @@ -56,14 +57,23 @@ static int get_max_inline_xattr_value_size(struct inode *inode, raw_inode = ext4_raw_inode(iloc); header = IHDR(inode, raw_inode); entry = IFIRST(header); + end = (void *)raw_inode + EXT4_SB(inode->i_sb)->s_inode_size; /* Compute min_offs. */ - for (; !IS_LAST_ENTRY(entry); entry = EXT4_XATTR_NEXT(entry)) { + while (!IS_LAST_ENTRY(entry)) { + void *next = EXT4_XATTR_NEXT(entry); + + if (next >= end) { + EXT4_ERROR_INODE(inode, + "corrupt xattr in inline inode"); + return 0; + } if (!entry->e_value_inum && entry->e_value_size) { size_t offs = le16_to_cpu(entry->e_value_offs); if (offs < min_offs) min_offs = offs; } + entry = next; } free = min_offs - ((void *)entry - (void *)IFIRST(header)) - sizeof(__u32); @@ -158,7 +168,6 @@ int ext4_find_inline_data_nolock(struct inode *inode) (void *)ext4_raw_inode(&is.iloc)); EXT4_I(inode)->i_inline_size = EXT4_MIN_INLINE_DATA_SIZE + le32_to_cpu(is.s.here->e_value_size); - ext4_set_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA); } out: brelse(is.iloc.bh); @@ -208,7 +217,7 @@ static int ext4_read_inline_data(struct inode *inode, void *buffer, /* * write the buffer to the inline inode. * If 'create' is set, we don't need to do the extra copy in the xattr - * value since it is already handled by ext4_xattr_ibody_inline_set. + * value since it is already handled by ext4_xattr_ibody_set. * That saves us one memcpy. */ static void ext4_write_inline_data(struct inode *inode, struct ext4_iloc *iloc, @@ -290,7 +299,7 @@ static int ext4_create_inline_data(handle_t *handle, BUG_ON(!is.s.not_found); - error = ext4_xattr_ibody_inline_set(handle, inode, &i, &is); + error = ext4_xattr_ibody_set(handle, inode, &i, &is); if (error) { if (error == -ENOSPC) ext4_clear_inode_state(inode, @@ -350,7 +359,7 @@ static int ext4_update_inline_data(handle_t *handle, struct inode *inode, error = ext4_xattr_ibody_get(inode, i.name_index, i.name, value, len); - if (error == -ENODATA) + if (error < 0) goto out; BUFFER_TRACE(is.iloc.bh, "get_write_access"); @@ -362,7 +371,7 @@ static int ext4_update_inline_data(handle_t *handle, struct inode *inode, i.value = value; i.value_len = len; - error = ext4_xattr_ibody_inline_set(handle, inode, &i, &is); + error = ext4_xattr_ibody_set(handle, inode, &i, &is); if (error) goto out; @@ -435,7 +444,7 @@ static int ext4_destroy_inline_data_nolock(handle_t *handle, if (error) goto out; - error = ext4_xattr_ibody_inline_set(handle, inode, &i, &is); + error = ext4_xattr_ibody_set(handle, inode, &i, &is); if (error) goto out; @@ -1997,8 +2006,7 @@ int ext4_inline_data_truncate(struct inode *inode, int *has_inline) i.value = value; i.value_len = i_size > EXT4_MIN_INLINE_DATA_SIZE ? i_size - EXT4_MIN_INLINE_DATA_SIZE : 0; - err = ext4_xattr_ibody_inline_set(handle, inode, - &i, &is); + err = ext4_xattr_ibody_set(handle, inode, &i, &is); if (err) goto out_error; } diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c index 7aac5801f227abe79bf852215ae93990e72f1163..7e9020dbc98c843e6e52225c9c157564e68bee05 100644 --- a/fs/ext4/inode.c +++ b/fs/ext4/inode.c @@ -669,16 +669,6 @@ int ext4_map_blocks(handle_t *handle, struct inode *inode, */ ext4_clear_inode_state(inode, EXT4_STATE_EXT_MIGRATE); } - - /* - * Update reserved blocks/metadata blocks after successful - * block allocation which had been deferred till now. We don't - * support fallocate for non extent files. So we can update - * reserve space here. - */ - if ((retval > 0) && - (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE)) - ext4_da_update_reserve_space(inode, retval, 1); } if (retval > 0) { @@ -1442,7 +1432,8 @@ static int ext4_write_end(struct file *file, trace_android_fs_datawrite_end(inode, pos, len); trace_ext4_write_end(inode, pos, len, copied); - if (inline_data) { + if (inline_data && + ext4_test_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA)) { ret = ext4_write_inline_data_end(inode, pos, len, copied, page); if (ret < 0) { @@ -4947,8 +4938,13 @@ static inline int ext4_iget_extra_inode(struct inode *inode, if (EXT4_INODE_HAS_XATTR_SPACE(inode) && *magic == cpu_to_le32(EXT4_XATTR_MAGIC)) { + int err; + ext4_set_inode_state(inode, EXT4_STATE_XATTR); - return ext4_find_inline_data_nolock(inode); + err = ext4_find_inline_data_nolock(inode); + if (!err && ext4_has_inline_data(inode)) + ext4_set_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA); + return err; } else EXT4_I(inode)->i_inline_off = 0; return 0; @@ -5024,13 +5020,6 @@ struct inode *__ext4_iget(struct super_block *sb, unsigned long ino, goto bad_inode; raw_inode = ext4_raw_inode(&iloc); - if ((ino == EXT4_ROOT_INO) && (raw_inode->i_links_count == 0)) { - ext4_error_inode(inode, function, line, 0, - "iget: root inode unallocated"); - ret = -EFSCORRUPTED; - goto bad_inode; - } - if ((flags & EXT4_IGET_HANDLE) && (raw_inode->i_links_count == 0) && (raw_inode->i_mode == 0)) { ret = -ESTALE; @@ -5101,11 +5090,16 @@ struct inode *__ext4_iget(struct super_block *sb, unsigned long ino, * NeilBrown 1999oct15 */ if (inode->i_nlink == 0) { - if ((inode->i_mode == 0 || + if ((inode->i_mode == 0 || flags & EXT4_IGET_SPECIAL || !(EXT4_SB(inode->i_sb)->s_mount_state & EXT4_ORPHAN_FS)) && ino != EXT4_BOOT_LOADER_INO) { - /* this inode is deleted */ - ret = -ESTALE; + /* this inode is deleted or unallocated */ + if (flags & EXT4_IGET_SPECIAL) { + ext4_error_inode(inode, function, line, 0, + "iget: special inode unallocated"); + ret = -EFSCORRUPTED; + } else + ret = -ESTALE; goto bad_inode; } /* The only unlinked inodes we let through here have diff --git a/fs/ext4/ioctl.c b/fs/ext4/ioctl.c index df85333b5e96f40c61390c96cdefa675b9ecd6b3..aac4015b1af89bc8a4c682de322e73ebfb559663 100644 --- a/fs/ext4/ioctl.c +++ b/fs/ext4/ioctl.c @@ -178,6 +178,7 @@ static long swap_inode_boot_loader(struct super_block *sb, ei_bl->i_flags = 0; inode_set_iversion(inode_bl, 1); i_size_write(inode_bl, 0); + EXT4_I(inode_bl)->i_disksize = inode_bl->i_size; inode_bl->i_mode = S_IFREG; if (ext4_has_feature_extents(sb)) { ext4_set_inode_flag(inode_bl, EXT4_INODE_EXTENTS); @@ -578,6 +579,7 @@ static int ext4_shutdown(struct super_block *sb, unsigned long arg) { struct ext4_sb_info *sbi = EXT4_SB(sb); __u32 flags; + struct super_block *ret; if (!capable(CAP_SYS_ADMIN)) return -EPERM; @@ -596,7 +598,9 @@ static int ext4_shutdown(struct super_block *sb, unsigned long arg) switch (flags) { case EXT4_GOING_FLAGS_DEFAULT: - freeze_bdev(sb->s_bdev); + ret = freeze_bdev(sb->s_bdev); + if (IS_ERR(ret)) + return PTR_ERR(ret); set_bit(EXT4_FLAGS_SHUTDOWN, &sbi->s_ext4_flags); thaw_bdev(sb->s_bdev, sb); break; diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index 4ea4fe92eb8c9c21bf51ce345e2b3a3c0f30a9a4..fb2f255c48e814e86ac156462714cd18b0b8853c 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #ifdef CONFIG_EXT4_DEBUG @@ -3089,6 +3090,7 @@ ext4_mb_normalize_request(struct ext4_allocation_context *ac, struct ext4_allocation_request *ar) { struct ext4_sb_info *sbi = EXT4_SB(ac->ac_sb); + struct ext4_super_block *es = sbi->s_es; int bsbits, max; ext4_lblk_t end; loff_t size, start_off; @@ -3269,18 +3271,21 @@ ext4_mb_normalize_request(struct ext4_allocation_context *ac, ac->ac_g_ex.fe_len = EXT4_NUM_B2C(sbi, size); /* define goal start in order to merge */ - if (ar->pright && (ar->lright == (start + size))) { + if (ar->pright && (ar->lright == (start + size)) && + ar->pright >= size && + ar->pright - size >= le32_to_cpu(es->s_first_data_block)) { /* merge to the right */ ext4_get_group_no_and_offset(ac->ac_sb, ar->pright - size, - &ac->ac_f_ex.fe_group, - &ac->ac_f_ex.fe_start); + &ac->ac_g_ex.fe_group, + &ac->ac_g_ex.fe_start); ac->ac_flags |= EXT4_MB_HINT_TRY_GOAL; } - if (ar->pleft && (ar->lleft + 1 == start)) { + if (ar->pleft && (ar->lleft + 1 == start) && + ar->pleft + 1 < ext4_blocks_count(es)) { /* merge to the left */ ext4_get_group_no_and_offset(ac->ac_sb, ar->pleft + 1, - &ac->ac_f_ex.fe_group, - &ac->ac_f_ex.fe_start); + &ac->ac_g_ex.fe_group, + &ac->ac_g_ex.fe_start); ac->ac_flags |= EXT4_MB_HINT_TRY_GOAL; } @@ -3372,6 +3377,7 @@ static void ext4_mb_use_inode_pa(struct ext4_allocation_context *ac, BUG_ON(start < pa->pa_pstart); BUG_ON(end > pa->pa_pstart + EXT4_C2B(sbi, pa->pa_len)); BUG_ON(pa->pa_free < len); + BUG_ON(ac->ac_b_ex.fe_len <= 0); pa->pa_free -= len; mb_debug(1, "use %llu/%u from inode pa %p\n", start, len, pa); @@ -3676,10 +3682,8 @@ ext4_mb_new_inode_pa(struct ext4_allocation_context *ac) return -ENOMEM; if (ac->ac_b_ex.fe_len < ac->ac_g_ex.fe_len) { - int winl; - int wins; - int win; - int offs; + int new_bex_start; + int new_bex_end; /* we can't allocate as much as normalizer wants. * so, found space must get proper lstart @@ -3687,26 +3691,40 @@ ext4_mb_new_inode_pa(struct ext4_allocation_context *ac) BUG_ON(ac->ac_g_ex.fe_logical > ac->ac_o_ex.fe_logical); BUG_ON(ac->ac_g_ex.fe_len < ac->ac_o_ex.fe_len); - /* we're limited by original request in that - * logical block must be covered any way - * winl is window we can move our chunk within */ - winl = ac->ac_o_ex.fe_logical - ac->ac_g_ex.fe_logical; + /* + * Use the below logic for adjusting best extent as it keeps + * fragmentation in check while ensuring logical range of best + * extent doesn't overflow out of goal extent: + * + * 1. Check if best ex can be kept at end of goal and still + * cover original start + * 2. Else, check if best ex can be kept at start of goal and + * still cover original start + * 3. Else, keep the best ex at start of original request. + */ + new_bex_end = ac->ac_g_ex.fe_logical + + EXT4_C2B(sbi, ac->ac_g_ex.fe_len); + new_bex_start = new_bex_end - EXT4_C2B(sbi, ac->ac_b_ex.fe_len); + if (ac->ac_o_ex.fe_logical >= new_bex_start) + goto adjust_bex; - /* also, we should cover whole original request */ - wins = EXT4_C2B(sbi, ac->ac_b_ex.fe_len - ac->ac_o_ex.fe_len); + new_bex_start = ac->ac_g_ex.fe_logical; + new_bex_end = + new_bex_start + EXT4_C2B(sbi, ac->ac_b_ex.fe_len); + if (ac->ac_o_ex.fe_logical < new_bex_end) + goto adjust_bex; - /* the smallest one defines real window */ - win = min(winl, wins); + new_bex_start = ac->ac_o_ex.fe_logical; + new_bex_end = + new_bex_start + EXT4_C2B(sbi, ac->ac_b_ex.fe_len); - offs = ac->ac_o_ex.fe_logical % - EXT4_C2B(sbi, ac->ac_b_ex.fe_len); - if (offs && offs < win) - win = offs; +adjust_bex: + ac->ac_b_ex.fe_logical = new_bex_start; - ac->ac_b_ex.fe_logical = ac->ac_o_ex.fe_logical - - EXT4_NUM_B2C(sbi, win); BUG_ON(ac->ac_o_ex.fe_logical < ac->ac_b_ex.fe_logical); BUG_ON(ac->ac_o_ex.fe_len > ac->ac_b_ex.fe_len); + BUG_ON(new_bex_end > (ac->ac_g_ex.fe_logical + + EXT4_C2B(sbi, ac->ac_g_ex.fe_len))); } /* preallocation can change ac_b_ex, thus we store actually @@ -3893,7 +3911,11 @@ ext4_mb_release_group_pa(struct ext4_buddy *e4b, trace_ext4_mb_release_group_pa(sb, pa); BUG_ON(pa->pa_deleted == 0); ext4_get_group_no_and_offset(sb, pa->pa_pstart, &group, &bit); - BUG_ON(group != e4b->bd_group && pa->pa_len != 0); + if (unlikely(group != e4b->bd_group && pa->pa_len != 0)) { + ext4_warning(sb, "bad group: expected %u, group %u, pa_start %llu", + e4b->bd_group, group, pa->pa_pstart); + return 0; + } mb_free_blocks(pa->pa_inode, e4b, bit, pa->pa_len); atomic_add(pa->pa_len, &EXT4_SB(sb)->s_mb_discarded); trace_ext4_mballoc_discard(sb, NULL, group, bit, pa->pa_len); @@ -4927,8 +4949,8 @@ void ext4_free_blocks(handle_t *handle, struct inode *inode, * them with group lock_held */ if (test_opt(sb, DISCARD)) { - err = ext4_issue_discard(sb, block_group, bit, count, - NULL); + err = ext4_issue_discard(sb, block_group, bit, + count_clusters, NULL); if (err && err != -EOPNOTSUPP) ext4_msg(sb, KERN_WARNING, "discard request in" " group:%d block:%d count:%lu failed" @@ -5128,19 +5150,19 @@ int ext4_group_add_blocks(handle_t *handle, struct super_block *sb, * @sb: super block for the file system * @start: starting block of the free extent in the alloc. group * @count: number of blocks to TRIM - * @group: alloc. group we are working with * @e4b: ext4 buddy for the group * * Trim "count" blocks starting at "start" in the "group". To assure that no * one will allocate those blocks, mark it as used in buddy bitmap. This must * be called with under the group lock. */ -static int ext4_trim_extent(struct super_block *sb, int start, int count, - ext4_group_t group, struct ext4_buddy *e4b) +static int ext4_trim_extent(struct super_block *sb, + int start, int count, struct ext4_buddy *e4b) __releases(bitlock) __acquires(bitlock) { struct ext4_free_extent ex; + ext4_group_t group = e4b->bd_group; int ret = 0; trace_ext4_trim_extent(sb, group, start, count); @@ -5163,6 +5185,71 @@ __acquires(bitlock) return ret; } +static ext4_grpblk_t ext4_last_grp_cluster(struct super_block *sb, + ext4_group_t grp) +{ + if (grp < ext4_get_groups_count(sb)) + return EXT4_CLUSTERS_PER_GROUP(sb) - 1; + return (ext4_blocks_count(EXT4_SB(sb)->s_es) - + ext4_group_first_block_no(sb, grp) - 1) >> + EXT4_CLUSTER_BITS(sb); +} + +static bool ext4_trim_interrupted(void) +{ + return fatal_signal_pending(current) || freezing(current); +} + +static int ext4_try_to_trim_range(struct super_block *sb, + struct ext4_buddy *e4b, ext4_grpblk_t start, + ext4_grpblk_t max, ext4_grpblk_t minblocks) +{ + ext4_grpblk_t next, count, free_count; + bool set_trimmed = false; + void *bitmap; + + bitmap = e4b->bd_bitmap; + if (start == 0 && max >= ext4_last_grp_cluster(sb, e4b->bd_group)) + set_trimmed = true; + start = max(e4b->bd_info->bb_first_free, start); + count = 0; + free_count = 0; + + while (start <= max) { + start = mb_find_next_zero_bit(bitmap, max + 1, start); + if (start > max) + break; + next = mb_find_next_bit(bitmap, max + 1, start); + + if ((next - start) >= minblocks) { + int ret = ext4_trim_extent(sb, start, next - start, e4b); + + if (ret && ret != -EOPNOTSUPP) + return count; + count += next - start; + } + free_count += next - start; + start = next + 1; + + if (ext4_trim_interrupted()) + return count; + + if (need_resched()) { + ext4_unlock_group(sb, e4b->bd_group); + cond_resched(); + ext4_lock_group(sb, e4b->bd_group); + } + + if ((e4b->bd_info->bb_free - free_count) < minblocks) + break; + } + + if (set_trimmed) + EXT4_MB_GRP_SET_TRIMMED(e4b->bd_info); + + return count; +} + /** * ext4_trim_all_free -- function to trim all free space in alloc. group * @sb: super block for file system @@ -5186,10 +5273,8 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group, ext4_grpblk_t start, ext4_grpblk_t max, ext4_grpblk_t minblocks) { - void *bitmap; - ext4_grpblk_t next, count = 0, free_count = 0; struct ext4_buddy e4b; - int ret = 0; + int ret; trace_ext4_trim_all_free(sb, group, start, max); @@ -5199,58 +5284,20 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group, ret, group); return ret; } - bitmap = e4b.bd_bitmap; ext4_lock_group(sb, group); - if (EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) && - minblocks >= atomic_read(&EXT4_SB(sb)->s_last_trim_minblks)) - goto out; - - start = (e4b.bd_info->bb_first_free > start) ? - e4b.bd_info->bb_first_free : start; - - while (start <= max) { - start = mb_find_next_zero_bit(bitmap, max + 1, start); - if (start > max) - break; - next = mb_find_next_bit(bitmap, max + 1, start); - - if ((next - start) >= minblocks) { - ret = ext4_trim_extent(sb, start, - next - start, group, &e4b); - if (ret && ret != -EOPNOTSUPP) - break; - ret = 0; - count += next - start; - } - free_count += next - start; - start = next + 1; - - if (fatal_signal_pending(current)) { - count = -ERESTARTSYS; - break; - } - - if (need_resched()) { - ext4_unlock_group(sb, group); - cond_resched(); - ext4_lock_group(sb, group); - } - if ((e4b.bd_info->bb_free - free_count) < minblocks) - break; - } + if (!EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) || + minblocks < EXT4_SB(sb)->s_last_trim_minblks) + ret = ext4_try_to_trim_range(sb, &e4b, start, max, minblocks); + else + ret = 0; - if (!ret) { - ret = count; - EXT4_MB_GRP_SET_TRIMMED(e4b.bd_info); - } -out: ext4_unlock_group(sb, group); ext4_mb_unload_buddy(&e4b); ext4_debug("trimmed %d blocks in the group %d\n", - count, group); + ret, group); return ret; } @@ -5295,7 +5342,7 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) if (minlen > EXT4_CLUSTERS_PER_GROUP(sb)) goto out; } - if (end >= max_blks) + if (end >= max_blks - 1) end = max_blks - 1; if (end <= first_data_blk) goto out; @@ -5312,6 +5359,8 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) end = EXT4_CLUSTERS_PER_GROUP(sb) - 1; for (group = first_group; group <= last_group; group++) { + if (ext4_trim_interrupted()) + break; grp = ext4_get_group_info(sb, group); /* We only do this if the grp has never been initialized */ if (unlikely(EXT4_MB_GRP_NEED_INIT(grp))) { @@ -5328,10 +5377,9 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) */ if (group == last_group) end = last_cluster; - if (grp->bb_free >= minlen) { cnt = ext4_trim_all_free(sb, group, first_cluster, - end, minlen); + end, minlen); if (cnt < 0) { ret = cnt; break; @@ -5347,7 +5395,7 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) } if (!ret) - atomic_set(&EXT4_SB(sb)->s_last_trim_minblks, minlen); + EXT4_SB(sb)->s_last_trim_minblks = minlen; out: range->len = EXT4_C2B(EXT4_SB(sb), trimmed) << sb->s_blocksize_bits; @@ -5376,8 +5424,7 @@ ext4_mballoc_query_range( ext4_lock_group(sb, group); - start = (e4b.bd_info->bb_first_free > start) ? - e4b.bd_info->bb_first_free : start; + start = max(e4b.bd_info->bb_first_free, start); if (end >= EXT4_CLUSTERS_PER_GROUP(sb)) end = EXT4_CLUSTERS_PER_GROUP(sb) - 1; diff --git a/fs/ext4/namei.c b/fs/ext4/namei.c index e884e3e4d8fd50aad094e22da805f3331dd20b4b..e53f09dfb0bf3221aad93351ba83b03007428014 100644 --- a/fs/ext4/namei.c +++ b/fs/ext4/namei.c @@ -325,17 +325,17 @@ static struct ext4_dir_entry_tail *get_dirent_tail(struct inode *inode, struct ext4_dir_entry *de) { struct ext4_dir_entry_tail *t; + int blocksize = EXT4_BLOCK_SIZE(inode->i_sb); #ifdef PARANOID struct ext4_dir_entry *d, *top; d = de; top = (struct ext4_dir_entry *)(((void *)de) + - (EXT4_BLOCK_SIZE(inode->i_sb) - - sizeof(struct ext4_dir_entry_tail))); - while (d < top && d->rec_len) + (blocksize - sizeof(struct ext4_dir_entry_tail))); + while (d < top && ext4_rec_len_from_disk(d->rec_len, blocksize)) d = (struct ext4_dir_entry *)(((void *)d) + - le16_to_cpu(d->rec_len)); + ext4_rec_len_from_disk(d->rec_len, blocksize)); if (d != top) return NULL; @@ -346,7 +346,8 @@ static struct ext4_dir_entry_tail *get_dirent_tail(struct inode *inode, #endif if (t->det_reserved_zero1 || - le16_to_cpu(t->det_rec_len) != sizeof(struct ext4_dir_entry_tail) || + (ext4_rec_len_from_disk(t->det_rec_len, blocksize) != + sizeof(struct ext4_dir_entry_tail)) || t->det_reserved_zero2 || t->det_reserved_ft != EXT4_FT_DIR_CSUM) return NULL; @@ -428,13 +429,14 @@ static struct dx_countlimit *get_dx_countlimit(struct inode *inode, struct ext4_dir_entry *dp; struct dx_root_info *root; int count_offset; + int blocksize = EXT4_BLOCK_SIZE(inode->i_sb); + unsigned int rlen = ext4_rec_len_from_disk(dirent->rec_len, blocksize); - if (le16_to_cpu(dirent->rec_len) == EXT4_BLOCK_SIZE(inode->i_sb)) + if (rlen == blocksize) count_offset = 8; - else if (le16_to_cpu(dirent->rec_len) == 12) { + else if (rlen == 12) { dp = (struct ext4_dir_entry *)(((void *)dirent) + 12); - if (le16_to_cpu(dp->rec_len) != - EXT4_BLOCK_SIZE(inode->i_sb) - 12) + if (ext4_rec_len_from_disk(dp->rec_len, blocksize) != blocksize - 12) return NULL; root = (struct dx_root_info *)(((void *)dp + 12)); if (root->reserved_zero || @@ -1285,6 +1287,7 @@ static int dx_make_map(struct inode *dir, struct buffer_head *bh, unsigned int buflen = bh->b_size; char *base = bh->b_data; struct dx_hash_info h = *hinfo; + int blocksize = EXT4_BLOCK_SIZE(dir->i_sb); if (ext4_has_metadata_csum(dir->i_sb)) buflen -= sizeof(struct ext4_dir_entry_tail); @@ -1301,11 +1304,12 @@ static int dx_make_map(struct inode *dir, struct buffer_head *bh, map_tail--; map_tail->hash = h.hash; map_tail->offs = ((char *) de - base)>>2; - map_tail->size = le16_to_cpu(de->rec_len); + map_tail->size = ext4_rec_len_from_disk(de->rec_len, + blocksize); count++; cond_resched(); } - de = ext4_next_entry(de, dir->i_sb->s_blocksize); + de = ext4_next_entry(de, blocksize); } return count; } @@ -1578,11 +1582,10 @@ static struct buffer_head *__ext4_find_entry(struct inode *dir, int has_inline_data = 1; ret = ext4_find_inline_entry(dir, fname, res_dir, &has_inline_data); - if (has_inline_data) { - if (inlined) - *inlined = 1; + if (inlined) + *inlined = has_inline_data; + if (has_inline_data) goto cleanup_and_exit; - } } if ((namelen <= 2) && (name[0] == '.') && @@ -3736,7 +3739,8 @@ static void ext4_resetent(handle_t *handle, struct ext4_renament *ent, * so the old->de may no longer valid and need to find it again * before reset old inode info. */ - old.bh = ext4_find_entry(old.dir, &old.dentry->d_name, &old.de, NULL); + old.bh = ext4_find_entry(old.dir, &old.dentry->d_name, &old.de, + &old.inlined); if (IS_ERR(old.bh)) retval = PTR_ERR(old.bh); if (!old.bh) @@ -3898,7 +3902,8 @@ static int ext4_rename(struct inode *old_dir, struct dentry *old_dentry, return retval; } - old.bh = ext4_find_entry(old.dir, &old.dentry->d_name, &old.de, NULL); + old.bh = ext4_find_entry(old.dir, &old.dentry->d_name, &old.de, + &old.inlined); if (IS_ERR(old.bh)) return PTR_ERR(old.bh); /* diff --git a/fs/ext4/page-io.c b/fs/ext4/page-io.c index b73c13801b5a7bba55c805384e052f3dd41e5922..0d12b64511816db30530459e5e4cca59f0c5962b 100644 --- a/fs/ext4/page-io.c +++ b/fs/ext4/page-io.c @@ -381,7 +381,8 @@ static int io_submit_init_bio(struct ext4_io_submit *io, static int io_submit_add_bh(struct ext4_io_submit *io, struct inode *inode, - struct page *page, + struct page *pagecache_page, + struct page *bounce_page, struct buffer_head *bh) { int ret; @@ -397,10 +398,11 @@ static int io_submit_add_bh(struct ext4_io_submit *io, return ret; io->io_bio->bi_write_hint = inode->i_write_hint; } - ret = bio_add_page(io->io_bio, page, bh->b_size, bh_offset(bh)); + ret = bio_add_page(io->io_bio, bounce_page ?: pagecache_page, + bh->b_size, bh_offset(bh)); if (ret != bh->b_size) goto submit_and_retry; - wbc_account_io(io->io_wbc, page, bh->b_size); + wbc_account_io(io->io_wbc, pagecache_page, bh->b_size); io->io_next_block++; return 0; } @@ -507,7 +509,7 @@ int ext4_bio_write_page(struct ext4_io_submit *io, do { if (!buffer_async_write(bh)) continue; - ret = io_submit_add_bh(io, inode, bounce_page ?: page, bh); + ret = io_submit_add_bh(io, inode, page, bounce_page, bh); if (ret) { /* * We only get here on ENOMEM. Not much else diff --git a/fs/ext4/resize.c b/fs/ext4/resize.c index 288213cad91436b58a9c43f0fa5676cab73cd088..f4b3d450dead2079941a2a5e2aff65707d4040ab 100644 --- a/fs/ext4/resize.c +++ b/fs/ext4/resize.c @@ -572,13 +572,8 @@ static int setup_new_flex_group_blocks(struct super_block *sb, if (meta_bg == 0 && !ext4_bg_has_super(sb, group)) goto handle_itb; - if (meta_bg == 1) { - ext4_group_t first_group; - first_group = ext4_meta_bg_first_group(sb, group); - if (first_group != group + 1 && - first_group != group + EXT4_DESC_PER_BLOCK(sb) - 1) - goto handle_itb; - } + if (meta_bg == 1) + goto handle_itb; block = start + ext4_bg_has_super(sb, group); /* Copy all of the GDT blocks into the backup in this group */ @@ -1565,6 +1560,8 @@ static int ext4_flex_group_add(struct super_block *sb, int gdb_num_end = ((group + flex_gd->count - 1) / EXT4_DESC_PER_BLOCK(sb)); int meta_bg = ext4_has_feature_meta_bg(sb); + sector_t padding_blocks = meta_bg ? 0 : sbi->s_sbh->b_blocknr - + ext4_group_first_block_no(sb, 0); sector_t old_gdb = 0; update_backups(sb, ext4_group_first_block_no(sb, 0), @@ -1576,8 +1573,8 @@ static int ext4_flex_group_add(struct super_block *sb, gdb_num); if (old_gdb == gdb_bh->b_blocknr) continue; - update_backups(sb, gdb_bh->b_blocknr, gdb_bh->b_data, - gdb_bh->b_size, meta_bg); + update_backups(sb, gdb_bh->b_blocknr - padding_blocks, + gdb_bh->b_data, gdb_bh->b_size, meta_bg); old_gdb = gdb_bh->b_blocknr; } } @@ -1940,9 +1937,7 @@ static int ext4_convert_meta_bg(struct super_block *sb, struct inode *inode) errout: ret = ext4_journal_stop(handle); - if (!err) - err = ret; - return ret; + return err ? err : ret; invalid_resize_inode: ext4_error(sb, "corrupted/inconsistent resize inode"); diff --git a/fs/ext4/super.c b/fs/ext4/super.c index e07a29c7425a6372bdcebbb39c8ca896f5aa91ae..173ecd1e6476ba1e8d28510580b982369becfe41 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -906,10 +906,16 @@ static void ext4_blkdev_put(struct block_device *bdev) static void ext4_blkdev_remove(struct ext4_sb_info *sbi) { struct block_device *bdev; - bdev = sbi->journal_bdev; + bdev = sbi->s_journal_bdev; if (bdev) { + /* + * Invalidate the journal device's buffers. We don't want them + * floating about in memory - the physical journal device may + * hotswapped, and it breaks the `ro-after' testing code. + */ + invalidate_bdev(bdev); ext4_blkdev_put(bdev); - sbi->journal_bdev = NULL; + sbi->s_journal_bdev = NULL; } } @@ -1033,14 +1039,8 @@ static void ext4_put_super(struct super_block *sb) sync_blockdev(sb->s_bdev); invalidate_bdev(sb->s_bdev); - if (sbi->journal_bdev && sbi->journal_bdev != sb->s_bdev) { - /* - * Invalidate the journal device's buffers. We don't want them - * floating about in memory - the physical journal device may - * hotswapped, and it breaks the `ro-after' testing code. - */ - sync_blockdev(sbi->journal_bdev); - invalidate_bdev(sbi->journal_bdev); + if (sbi->s_journal_bdev && sbi->s_journal_bdev != sb->s_bdev) { + sync_blockdev(sbi->s_journal_bdev); ext4_blkdev_remove(sbi); } if (sbi->s_ea_inode_cache) { @@ -2530,11 +2530,9 @@ static __le16 ext4_group_desc_csum(struct super_block *sb, __u32 block_group, crc = crc16(crc, (__u8 *)gdp, offset); offset += sizeof(gdp->bg_checksum); /* skip checksum */ /* for checksum of struct ext4_group_desc do the rest...*/ - if (ext4_has_feature_64bit(sb) && - offset < le16_to_cpu(sbi->s_es->s_desc_size)) + if (ext4_has_feature_64bit(sb) && offset < sbi->s_desc_size) crc = crc16(crc, (__u8 *)gdp + offset, - le16_to_cpu(sbi->s_es->s_desc_size) - - offset); + sbi->s_desc_size - offset); out: return cpu_to_le16(crc); @@ -3655,7 +3653,7 @@ int ext4_calculate_overhead(struct super_block *sb) * Add the internal journal blocks whether the journal has been * loaded or not */ - if (sbi->s_journal && !sbi->journal_bdev) + if (sbi->s_journal && !sbi->s_journal_bdev) overhead += EXT4_NUM_B2C(sbi, sbi->s_journal->j_maxlen); else if (ext4_has_feature_journal(sb) && !sbi->s_journal && j_inum) { /* j_inum for internal journal is non-zero */ @@ -4837,6 +4835,7 @@ static int ext4_fill_super(struct super_block *sb, void *data, int silent) ext4_blkdev_remove(sbi); brelse(bh); out_fail: + invalidate_bdev(sb->s_bdev); sb->s_fs_info = NULL; kfree(sbi->s_blockgroup_lock); out_free_base: @@ -5012,7 +5011,7 @@ static journal_t *ext4_get_dev_journal(struct super_block *sb, be32_to_cpu(journal->j_superblock->s_nr_users)); goto out_journal; } - EXT4_SB(sb)->journal_bdev = bdev; + EXT4_SB(sb)->s_journal_bdev = bdev; ext4_init_journal_params(sb, journal); return journal; @@ -5665,9 +5664,6 @@ static int ext4_remount(struct super_block *sb, int *flags, char *data) } #ifdef CONFIG_QUOTA - /* Release old quota file names */ - for (i = 0; i < EXT4_MAXQUOTAS; i++) - kfree(old_opts.s_qf_names[i]); if (enable_quota) { if (sb_any_quota_suspended(sb)) dquot_resume(sb, -1); @@ -5677,6 +5673,9 @@ static int ext4_remount(struct super_block *sb, int *flags, char *data) goto restore_opts; } } + /* Release old quota file names */ + for (i = 0; i < EXT4_MAXQUOTAS; i++) + kfree(old_opts.s_qf_names[i]); #endif if (!test_opt(sb, BLOCK_VALIDITY) && sbi->system_blks) ext4_release_system_zone(sb); @@ -5693,6 +5692,13 @@ static int ext4_remount(struct super_block *sb, int *flags, char *data) return 0; restore_opts: + /* + * If there was a failing r/w to ro transition, we may need to + * re-enable quota + */ + if ((sb->s_flags & SB_RDONLY) && !(old_sb_flags & SB_RDONLY) && + sb_any_quota_suspended(sb)) + dquot_resume(sb, -1); sb->s_flags = old_sb_flags; sbi->s_mount_opt = old_opts.s_mount_opt; sbi->s_mount_opt2 = old_opts.s_mount_opt2; diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index 0772941bbe925d2129d59ebc7aaac5c317cfdfba..88bdb2714e519746ffeaf4b90e63a5cf8b8eac01 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -121,7 +121,11 @@ ext4_expand_inode_array(struct ext4_xattr_inode_array **ea_inode_array, #ifdef CONFIG_LOCKDEP void ext4_xattr_inode_set_class(struct inode *ea_inode) { + struct ext4_inode_info *ei = EXT4_I(ea_inode); + lockdep_set_subclass(&ea_inode->i_rwsem, 1); + (void) ei; /* shut up clang warning if !CONFIG_LOCKDEP */ + lockdep_set_subclass(&ei->i_data_sem, I_DATA_SEM_EA); } #endif @@ -384,6 +388,17 @@ static int ext4_xattr_inode_iget(struct inode *parent, unsigned long ea_ino, struct inode *inode; int err; + /* + * We have to check for this corruption early as otherwise + * iget_locked() could wait indefinitely for the state of our + * parent inode. + */ + if (parent->i_ino == ea_ino) { + ext4_error(parent->i_sb, + "Parent and EA inode have the same ino %lu", ea_ino); + return -EFSCORRUPTED; + } + inode = ext4_iget(parent->i_sb, ea_ino, EXT4_IGET_NORMAL); if (IS_ERR(inode)) { err = PTR_ERR(inode); @@ -1436,6 +1451,13 @@ static struct inode *ext4_xattr_inode_create(handle_t *handle, uid_t owner[2] = { i_uid_read(inode), i_gid_read(inode) }; int err; + if (inode->i_sb->s_root == NULL) { + ext4_warning(inode->i_sb, + "refuse to create EA inode when umounting"); + WARN_ON(1); + return ERR_PTR(-EINVAL); + } + /* * Let the next inode be the goal, so we try and allocate the EA inode * in the same group, or nearby one. @@ -1745,6 +1767,20 @@ static int ext4_xattr_set_entry(struct ext4_xattr_info *i, memmove(here, (void *)here + size, (void *)last - (void *)here + sizeof(__u32)); memset(last, 0, size); + + /* + * Update i_inline_off - moved ibody region might contain + * system.data attribute. Handling a failure here won't + * cause other complications for setting an xattr. + */ + if (!is_block && ext4_has_inline_data(inode)) { + ret = ext4_find_inline_data_nolock(inode); + if (ret) { + ext4_warning_inode(inode, + "unable to update i_inline_off"); + goto out; + } + } } else if (s->not_found) { /* Insert new name. */ size_t size = EXT4_XATTR_LEN(name_len); @@ -2019,8 +2055,9 @@ ext4_xattr_block_set(handle_t *handle, struct inode *inode, else { u32 ref; +#ifdef EXT4_XATTR_DEBUG WARN_ON_ONCE(dquot_initialize_needed(inode)); - +#endif /* The old block is released after updating the inode. */ error = dquot_alloc_block(inode, @@ -2082,8 +2119,9 @@ ext4_xattr_block_set(handle_t *handle, struct inode *inode, /* We need to allocate a new block */ ext4_fsblk_t goal, block; +#ifdef EXT4_XATTR_DEBUG WARN_ON_ONCE(dquot_initialize_needed(inode)); - +#endif goal = ext4_group_first_block_no(sb, EXT4_I(inode)->i_block_group); block = ext4_new_meta_blocks(handle, inode, goal, 0, @@ -2218,7 +2256,7 @@ int ext4_xattr_ibody_find(struct inode *inode, struct ext4_xattr_info *i, return 0; } -int ext4_xattr_ibody_inline_set(handle_t *handle, struct inode *inode, +int ext4_xattr_ibody_set(handle_t *handle, struct inode *inode, struct ext4_xattr_info *i, struct ext4_xattr_ibody_find *is) { @@ -2243,30 +2281,6 @@ int ext4_xattr_ibody_inline_set(handle_t *handle, struct inode *inode, return 0; } -static int ext4_xattr_ibody_set(handle_t *handle, struct inode *inode, - struct ext4_xattr_info *i, - struct ext4_xattr_ibody_find *is) -{ - struct ext4_xattr_ibody_header *header; - struct ext4_xattr_search *s = &is->s; - int error; - - if (EXT4_I(inode)->i_extra_isize == 0) - return -ENOSPC; - error = ext4_xattr_set_entry(i, s, handle, inode, false /* is_block */); - if (error) - return error; - header = IHDR(inode, ext4_raw_inode(&is->iloc)); - if (!IS_LAST_ENTRY(s->first)) { - header->h_magic = cpu_to_le32(EXT4_XATTR_MAGIC); - ext4_set_inode_state(inode, EXT4_STATE_XATTR); - } else { - header->h_magic = cpu_to_le32(0); - ext4_clear_inode_state(inode, EXT4_STATE_XATTR); - } - return 0; -} - static int ext4_xattr_value_same(struct ext4_xattr_search *s, struct ext4_xattr_info *i) { @@ -2579,13 +2593,13 @@ static int ext4_xattr_move_to_block(handle_t *handle, struct inode *inode, .in_inode = !!entry->e_value_inum, }; struct ext4_xattr_ibody_header *header = IHDR(inode, raw_inode); + int needs_kvfree = 0; int error; is = kzalloc(sizeof(struct ext4_xattr_ibody_find), GFP_NOFS); bs = kzalloc(sizeof(struct ext4_xattr_block_find), GFP_NOFS); - buffer = kvmalloc(value_size, GFP_NOFS); b_entry_name = kmalloc(entry->e_name_len + 1, GFP_NOFS); - if (!is || !bs || !buffer || !b_entry_name) { + if (!is || !bs || !b_entry_name) { error = -ENOMEM; goto out; } @@ -2597,12 +2611,18 @@ static int ext4_xattr_move_to_block(handle_t *handle, struct inode *inode, /* Save the entry name and the entry value */ if (entry->e_value_inum) { + buffer = kvmalloc(value_size, GFP_NOFS); + if (!buffer) { + error = -ENOMEM; + goto out; + } + needs_kvfree = 1; error = ext4_xattr_inode_get(inode, entry, buffer, value_size); if (error) goto out; } else { size_t value_offs = le16_to_cpu(entry->e_value_offs); - memcpy(buffer, (void *)IFIRST(header) + value_offs, value_size); + buffer = (void *)IFIRST(header) + value_offs; } memcpy(b_entry_name, entry->e_name, entry->e_name_len); @@ -2617,25 +2637,26 @@ static int ext4_xattr_move_to_block(handle_t *handle, struct inode *inode, if (error) goto out; - /* Remove the chosen entry from the inode */ - error = ext4_xattr_ibody_set(handle, inode, &i, is); - if (error) - goto out; - i.value = buffer; i.value_len = value_size; error = ext4_xattr_block_find(inode, &i, bs); if (error) goto out; - /* Add entry which was removed from the inode into the block */ + /* Move ea entry from the inode into the block */ error = ext4_xattr_block_set(handle, inode, &i, bs); if (error) goto out; - error = 0; + + /* Remove the chosen entry from the inode */ + i.value = NULL; + i.value_len = 0; + error = ext4_xattr_ibody_set(handle, inode, &i, is); + out: kfree(b_entry_name); - kvfree(buffer); + if (needs_kvfree && buffer) + kvfree(buffer); if (is) brelse(is->iloc.bh); if (bs) @@ -2810,6 +2831,9 @@ int ext4_expand_extra_isize_ea(struct inode *inode, int new_extra_isize, (void *)header, total_ino); EXT4_I(inode)->i_extra_isize = new_extra_isize; + if (ext4_has_inline_data(inode)) + error = ext4_find_inline_data_nolock(inode); + cleanup: if (error && (mnt_count != le16_to_cpu(sbi->s_es->s_mnt_count))) { ext4_warning(inode->i_sb, "Unable to expand inode %lu. Delete some EAs or run e2fsck.", diff --git a/fs/ext4/xattr.h b/fs/ext4/xattr.h index 231ef308d10cbcce14087268cb118ae3ebc78af7..66911f8a11f84474cbb470b8c3975eacf5809533 100644 --- a/fs/ext4/xattr.h +++ b/fs/ext4/xattr.h @@ -199,9 +199,9 @@ extern int ext4_xattr_ibody_find(struct inode *inode, struct ext4_xattr_info *i, extern int ext4_xattr_ibody_get(struct inode *inode, int name_index, const char *name, void *buffer, size_t buffer_size); -extern int ext4_xattr_ibody_inline_set(handle_t *handle, struct inode *inode, - struct ext4_xattr_info *i, - struct ext4_xattr_ibody_find *is); +extern int ext4_xattr_ibody_set(handle_t *handle, struct inode *inode, + struct ext4_xattr_info *i, + struct ext4_xattr_ibody_find *is); extern struct mb_cache *ext4_xattr_create_cache(void); extern void ext4_xattr_destroy_cache(struct mb_cache *); diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c index ee3c3a0e985eba5ee6d5531ab0a9993fcf3825fb..ef9eb9530dd9f2d7c5d8ca9ebe6d7fe1d57f02ba 100644 --- a/fs/f2fs/checkpoint.c +++ b/fs/f2fs/checkpoint.c @@ -301,8 +301,15 @@ static int __f2fs_write_meta_page(struct page *page, trace_f2fs_writepage(page, META); - if (unlikely(f2fs_cp_error(sbi))) + if (unlikely(f2fs_cp_error(sbi))) { + if (is_sbi_flag_set(sbi, SBI_IS_CLOSE)) { + ClearPageUptodate(page); + dec_page_count(sbi, F2FS_DIRTY_META); + unlock_page(page); + return 0; + } goto redirty_out; + } if (unlikely(is_sbi_flag_set(sbi, SBI_POR_DOING))) goto redirty_out; if (wbc->for_reclaim && page->index < GET_SUM_BLOCK(sbi, 0)) @@ -1268,7 +1275,8 @@ void f2fs_wait_on_all_pages(struct f2fs_sb_info *sbi, int type) if (!get_pages(sbi, type)) break; - if (unlikely(f2fs_cp_error(sbi))) + if (unlikely(f2fs_cp_error(sbi) && + !is_sbi_flag_set(sbi, SBI_IS_CLOSE))) break; if (type == F2FS_DIRTY_META) diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index e40b83350363b738b9a34e60469d4f6b38f5bd7e..7835a5ca9e838deb39b164e3a1ef157e2e20fd7d 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -758,7 +758,7 @@ int f2fs_submit_page_bio(struct f2fs_io_info *fio) } if (fio->io_wbc && !is_read_io(fio->op)) - wbc_account_io(fio->io_wbc, page, PAGE_SIZE); + wbc_account_io(fio->io_wbc, fio->page, PAGE_SIZE); __attach_io_flag(fio); bio_set_op_attrs(bio, fio->op, fio->op_flags); @@ -1041,7 +1041,7 @@ void f2fs_submit_page_write(struct f2fs_io_info *fio) } if (fio->io_wbc) - wbc_account_io(fio->io_wbc, bio_page, PAGE_SIZE); + wbc_account_io(fio->io_wbc, fio->page, PAGE_SIZE); io->last_block_in_bio = fio->new_blkaddr; f2fs_trace_ios(fio, 0); @@ -2822,7 +2822,8 @@ int f2fs_write_single_data_page(struct page *page, int *submitted, * don't drop any dirty dentry pages for keeping lastest * directory structure. */ - if (S_ISDIR(inode->i_mode)) + if (S_ISDIR(inode->i_mode) && + !is_sbi_flag_set(sbi, SBI_IS_CLOSE)) goto redirty_out; goto out; } diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c index d0e99c18bf7f191b10d6bf4d55b7e4925289f886..f3db6586415e8dc745a63cd915f6e6caf7bec993 100644 --- a/fs/f2fs/file.c +++ b/fs/f2fs/file.c @@ -257,16 +257,15 @@ static int f2fs_do_sync_file(struct file *file, loff_t start, loff_t end, .for_reclaim = 0, }; unsigned int seq_id = 0; +#ifdef CONFIG_F2FS_BD_STAT + u64 fsync_begin = 0, fsync_end = 0, wr_file_end, cp_begin = 0, + cp_end = 0, sync_node_begin = 0, sync_node_end = 0, + flush_begin = 0, flush_end = 0; +#endif if (unlikely(f2fs_readonly(inode->i_sb))) return 0; -#ifdef CONFIG_F2FS_BD_STAT - u64 fsync_begin = 0, fsync_end = 0, wr_file_end, cp_begin = 0, - cp_end = 0, sync_node_begin = 0, sync_node_end = 0, - flush_begin = 0, flush_end = 0; -#endif - trace_f2fs_sync_file_enter(inode); if (trace_android_fs_fsync_start_enabled()) { @@ -3377,6 +3376,7 @@ int f2fs_precache_extents(struct inode *inode) return -EOPNOTSUPP; map.m_lblk = 0; + map.m_pblk = 0; map.m_next_pgofs = NULL; map.m_next_extent = &m_next_extent; map.m_seg_type = NO_CHECK_TYPE; diff --git a/fs/f2fs/gc.c b/fs/f2fs/gc.c index cb683c633e88e1fe2386b57ea764dc9606e4a4b4..3f47bd82aced6c80f73745048915c0a72af52914 100644 --- a/fs/f2fs/gc.c +++ b/fs/f2fs/gc.c @@ -1675,7 +1675,8 @@ static int gc_data_segment(struct f2fs_sb_info *sbi, struct f2fs_summary *sum, if (phase == 3) { inode = f2fs_iget(sb, dni.ino); - if (IS_ERR(inode) || is_bad_inode(inode)) { + if (IS_ERR(inode) || is_bad_inode(inode) || + special_file(inode->i_mode)) { set_sbi_flag(sbi, SBI_NEED_FSCK); continue; } diff --git a/fs/f2fs/inline.c b/fs/f2fs/inline.c index 59037fb0db754acf540b4f99132343a5e6290ec4..42c921404c46ebed887e2b24478535647621f7f5 100644 --- a/fs/f2fs/inline.c +++ b/fs/f2fs/inline.c @@ -417,18 +417,17 @@ static int f2fs_move_inline_dirents(struct inode *dir, struct page *ipage, dentry_blk = page_address(page); + /* + * Start by zeroing the full block, to ensure that all unused space is + * zeroed and no uninitialized memory is leaked to disk. + */ + memset(dentry_blk, 0, F2FS_BLKSIZE); + make_dentry_ptr_inline(dir, &src, inline_dentry); make_dentry_ptr_block(dir, &dst, dentry_blk); /* copy data from inline dentry block to new dentry block */ memcpy(dst.bitmap, src.bitmap, src.nr_bitmap); - memset(dst.bitmap + src.nr_bitmap, 0, dst.nr_bitmap - src.nr_bitmap); - /* - * we do not need to zero out remainder part of dentry and filename - * field, since we have used bitmap for marking the usage status of - * them, besides, we can also ignore copying/zeroing reserved space - * of dentry block, because them haven't been used so far. - */ memcpy(dst.dentry, src.dentry, SIZE_OF_DIR_ENTRY * src.max); memcpy(dst.filename, src.filename, src.max * F2FS_SLOT_LEN); diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c index 73a44997c770c2d5f8f6647c868277b0638bf04c..bd7965d64032bd488513edcf2ad7c56e82f18796 100644 --- a/fs/f2fs/node.c +++ b/fs/f2fs/node.c @@ -895,8 +895,10 @@ static int truncate_dnode(struct dnode_of_data *dn) dn->ofs_in_node = 0; f2fs_truncate_data_blocks(dn); err = truncate_node(dn); - if (err) + if (err) { + f2fs_put_page(page, 1); return err; + } return 1; } diff --git a/fs/fat/dir.c b/fs/fat/dir.c index de60c05c0ca1d955e69d5d58cd3c27dd5063b7af..10769b2e4d468a75050ed4e5854278282266198b 100644 --- a/fs/fat/dir.c +++ b/fs/fat/dir.c @@ -1287,7 +1287,7 @@ int fat_add_entries(struct inode *dir, void *slots, int nr_slots, struct super_block *sb = dir->i_sb; struct msdos_sb_info *sbi = MSDOS_SB(sb); struct buffer_head *bh, *prev, *bhs[3]; /* 32*slots (672bytes) */ - struct msdos_dir_entry *uninitialized_var(de); + struct msdos_dir_entry *de; int err, free_slots, i, nr_bhs; loff_t pos, i_pos; diff --git a/fs/file.c b/fs/file.c index d6ca500a10536d98d5d60f994d6244577bca2419..928ba7b8df1e971ba3720801f09af4f79544deca 100644 --- a/fs/file.c +++ b/fs/file.c @@ -627,6 +627,7 @@ int __close_fd(struct files_struct *files, unsigned fd) fdt = files_fdtable(files); if (fd >= fdt->max_fds) goto out_unlock; + fd = array_index_nospec(fd, fdt->max_fds); file = fdt->fd[fd]; if (!file) goto out_unlock; diff --git a/fs/fs-writeback.c b/fs/fs-writeback.c index 3920d7e4ddc3d71539a5af039442271afe4dabdb..a7e05fd96ef12c9690052442f9ab6a90ed91cca0 100644 --- a/fs/fs-writeback.c +++ b/fs/fs-writeback.c @@ -705,7 +705,7 @@ void wbc_detach_inode(struct writeback_control *wbc) * is okay. The main goal is avoiding keeping an inode on * the wrong wb for an extended period of time. */ - if (hweight32(history) > WB_FRN_HIST_THR_SLOTS) + if (hweight16(history) > WB_FRN_HIST_THR_SLOTS) inode_switch_wbs(inode, max_id); } diff --git a/fs/fuse/control.c b/fs/fuse/control.c index acc35819aae64b5c98de795ca1827a05a69c7a0e..af253127b309a7eea293177784c289d56e15fee1 100644 --- a/fs/fuse/control.c +++ b/fs/fuse/control.c @@ -117,7 +117,7 @@ static ssize_t fuse_conn_max_background_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { - unsigned uninitialized_var(val); + unsigned val; ssize_t ret; ret = fuse_conn_limit_write(file, buf, count, ppos, &val, diff --git a/fs/fuse/cuse.c b/fs/fuse/cuse.c index e10e2b62ccf453f5e596bc0ec8bbab76af77c92c..acd985aa2cbab6a643a2736ab0bf5f119ea13d6b 100644 --- a/fs/fuse/cuse.c +++ b/fs/fuse/cuse.c @@ -269,7 +269,7 @@ static int cuse_parse_one(char **pp, char *end, char **keyp, char **valp) static int cuse_parse_devinfo(char *p, size_t len, struct cuse_devinfo *devinfo) { char *end = p + len; - char *uninitialized_var(key), *uninitialized_var(val); + char *key, *val; int rc; while (true) { diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c index ea378d592359ddf1c5ef1e4eaec5d32784400bc8..b09cf46b0b0452cb9e7fb5582e83f1ff998c27db 100644 --- a/fs/fuse/dev.c +++ b/fs/fuse/dev.c @@ -22,6 +22,7 @@ #include #include #include +#include MODULE_ALIAS_MISCDEV(FUSE_MINOR); MODULE_ALIAS("devname:fuse"); @@ -487,7 +488,9 @@ static void request_wait_answer(struct fuse_conn *fc, struct fuse_req *req) * Either request is already in userspace, or it was forced. * Wait it out. */ - wait_event(req->waitq, test_bit(FR_FINISHED, &req->flags)); + while (!test_bit(FR_FINISHED, &req->flags)) + wait_event_freezable(req->waitq, + test_bit(FR_FINISHED, &req->flags)); } static void __fuse_request_send(struct fuse_conn *fc, struct fuse_req *req) diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c index f5416e5b7cc8cdb2eba09f59a8e8063a4573c9d8..9c1af7ebc1998fbb71bb44fd8cf6f8be0eefd385 100644 --- a/fs/fuse/dir.c +++ b/fs/fuse/dir.c @@ -237,7 +237,7 @@ static int fuse_dentry_revalidate(struct dentry *entry, unsigned int flags) spin_unlock(&fc->lock); } kfree(forget); - if (ret == -ENOMEM) + if (ret == -ENOMEM || ret == -EINTR) goto out; if (ret || fuse_invalid_attr(&outarg.attr) || (outarg.attr.mode ^ inode->i_mode) & S_IFMT) @@ -301,7 +301,7 @@ static void fuse_dentry_canonical_path(const struct path *path, char *path_name; int err; - path_name = (char *)__get_free_page(GFP_KERNEL); + path_name = (char *)get_zeroed_page(GFP_KERNEL); if (!path_name) goto default_path; diff --git a/fs/fuse/file.c b/fs/fuse/file.c index c5b2e37fcfa93ed6a7ad2a13cad3d00dcae4d960..dae70b711b9c52a479c8a59ae46ab99ae78b3528 100644 --- a/fs/fuse/file.c +++ b/fs/fuse/file.c @@ -954,11 +954,9 @@ static ssize_t fuse_file_read_iter(struct kiocb *iocb, struct iov_iter *to) return err; } - if (ff && ff->passthrough.filp) + if (ff->passthrough.filp) return fuse_passthrough_read_iter(iocb, to); - else - return generic_file_read_iter(iocb, to); - + return generic_file_read_iter(iocb, to); } static void fuse_write_fill(struct fuse_req *req, struct fuse_file *ff, @@ -1203,6 +1201,9 @@ static ssize_t fuse_file_write_iter(struct kiocb *iocb, struct iov_iter *from) ssize_t err; loff_t endbyte = 0; + if (ff->passthrough.filp) + return fuse_passthrough_write_iter(iocb, from); + if (fuse_is_bad(inode)) return -EIO; @@ -2808,7 +2809,7 @@ static void fuse_register_polled_file(struct fuse_conn *fc, { spin_lock(&fc->lock); if (RB_EMPTY_NODE(&ff->polled_node)) { - struct rb_node **link, *uninitialized_var(parent); + struct rb_node **link, *parent; link = fuse_find_polled_node(fc, ff->kh, &parent); BUG_ON(*link); diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c index 7e8a25700411f255ea5bef6a9753d98b209824d1..15ca642de290ff8394233c2c2fea74446c163c10 100644 --- a/fs/fuse/inode.c +++ b/fs/fuse/inode.c @@ -945,6 +945,12 @@ static void process_init_reply(struct fuse_conn *fc, struct fuse_req *req) } if (arg->flags & FUSE_ABORT_ERROR) fc->abort_err = 1; + if (arg->flags & FUSE_PASSTHROUGH) { + fc->passthrough = 1; + /* Prevent further stacking */ + fc->sb->s_stack_depth = + FILESYSTEM_MAX_STACK_DEPTH; + } } else { ra_pages = fc->max_read / PAGE_SIZE; fc->no_lock = 1; @@ -976,7 +982,7 @@ static void fuse_send_init(struct fuse_conn *fc, struct fuse_req *req) FUSE_DO_READDIRPLUS | FUSE_READDIRPLUS_AUTO | FUSE_ASYNC_DIO | FUSE_WRITEBACK_CACHE | FUSE_NO_OPEN_SUPPORT | FUSE_PARALLEL_DIROPS | FUSE_HANDLE_KILLPRIV | FUSE_POSIX_ACL | - FUSE_PASSTHROUGH; + FUSE_ABORT_ERROR | FUSE_PASSTHROUGH; req->in.h.opcode = FUSE_INIT; req->in.numargs = 1; diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c index bed42f99ffffb4bbcfe76008fa3feaccccc58ad7..23bb7205e4a0584daed94564491292bfefcd4e50 100644 --- a/fs/fuse/passthrough.c +++ b/fs/fuse/passthrough.c @@ -15,11 +15,34 @@ struct fuse_aio_req { struct kiocb *iocb_fuse; }; +static void fuse_file_accessed(struct file *dst_file, struct file *src_file) +{ + struct inode *dst_inode; + struct inode *src_inode; + + if (dst_file->f_flags & O_NOATIME) + return; + + dst_inode = file_inode(dst_file); + src_inode = file_inode(src_file); + + if ((!timespec64_equal(&dst_inode->i_mtime, &src_inode->i_mtime) || + !timespec64_equal(&dst_inode->i_ctime, &src_inode->i_ctime))) { + dst_inode->i_mtime = src_inode->i_mtime; + dst_inode->i_ctime = src_inode->i_ctime; + } + + touch_atime(&dst_file->f_path); +} + static void fuse_copyattr(struct file *dst_file, struct file *src_file) { struct inode *dst = file_inode(dst_file); struct inode *src = file_inode(src_file); + dst->i_atime = src->i_atime; + dst->i_mtime = src->i_mtime; + dst->i_ctime = src->i_ctime; i_size_write(dst, i_size_read(src)); } @@ -84,6 +107,9 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse, } out: revert_creds(old_cred); + + fuse_file_accessed(fuse_filp, passthrough_filp); + return ret; } @@ -103,6 +129,8 @@ ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse, inode_lock(fuse_inode); + fuse_copyattr(fuse_filp, passthrough_filp); + old_cred = override_creds(ff->passthrough.cred); if (is_sync_kiocb(iocb_fuse)) { file_start_write(passthrough_filp); @@ -142,9 +170,7 @@ ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma) int ret; const struct cred *old_cred; struct fuse_file *ff = file->private_data; - struct inode *fuse_inode = file_inode(file); - struct file *passthrough_filp = ff->passthrough.filp; - struct inode *passthrough_inode = file_inode(passthrough_filp); + struct file *passthrough_filp = ff->passthrough.filp; if (!passthrough_filp->f_op->mmap) return -ENODEV; @@ -163,17 +189,7 @@ ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma) else fput(file); - if (file->f_flags & O_NOATIME) - return ret; - - if ((!timespec64_equal(&fuse_inode->i_mtime, - &passthrough_inode->i_mtime) || - !timespec64_equal(&fuse_inode->i_ctime, - &passthrough_inode->i_ctime))) { - fuse_inode->i_mtime = passthrough_inode->i_mtime; - fuse_inode->i_ctime = passthrough_inode->i_ctime; - } - touch_atime(&file->f_path); + fuse_file_accessed(file, passthrough_filp); return ret; } diff --git a/fs/gfs2/aops.c b/fs/gfs2/aops.c index f3bdc4bdd5b1630fe66909a632fd014b0c836af0..a3c448287f7803db2448687e8e19058f606ca1f9 100644 --- a/fs/gfs2/aops.c +++ b/fs/gfs2/aops.c @@ -179,7 +179,6 @@ static int __gfs2_jdata_writepage(struct page *page, struct writeback_control *w { struct inode *inode = page->mapping->host; struct gfs2_inode *ip = GFS2_I(inode); - struct gfs2_sbd *sdp = GFS2_SB(inode); if (PageChecked(page)) { ClearPageChecked(page); @@ -187,7 +186,7 @@ static int __gfs2_jdata_writepage(struct page *page, struct writeback_control *w create_empty_buffers(page, inode->i_sb->s_blocksize, BIT(BH_Dirty)|BIT(BH_Uptodate)); } - gfs2_page_add_databufs(ip, page, 0, sdp->sd_vfs->s_blocksize); + gfs2_page_add_databufs(ip, page, 0, PAGE_SIZE); } return gfs2_write_full_page(page, gfs2_get_block_noalloc, wbc); } @@ -360,7 +359,7 @@ static int gfs2_write_cache_jdata(struct address_space *mapping, int done = 0; struct pagevec pvec; int nr_pages; - pgoff_t uninitialized_var(writeback_index); + pgoff_t writeback_index; pgoff_t index; pgoff_t end; pgoff_t done_index; @@ -481,8 +480,6 @@ int stuffed_readpage(struct gfs2_inode *ip, struct page *page) return error; kaddr = kmap_atomic(page); - if (dsize > gfs2_max_stuffed_size(ip)) - dsize = gfs2_max_stuffed_size(ip); memcpy(kaddr, dibh->b_data + sizeof(struct gfs2_dinode), dsize); memset(kaddr + dsize, 0, PAGE_SIZE - dsize); kunmap_atomic(kaddr); diff --git a/fs/gfs2/bmap.c b/fs/gfs2/bmap.c index 150cec85c416d7e968b9b3234a00ca753de32d48..729f36fdced1fc460008d946737b51f62e91e4d9 100644 --- a/fs/gfs2/bmap.c +++ b/fs/gfs2/bmap.c @@ -72,9 +72,6 @@ static int gfs2_unstuffer_page(struct gfs2_inode *ip, struct buffer_head *dibh, void *kaddr = kmap(page); u64 dsize = i_size_read(inode); - if (dsize > gfs2_max_stuffed_size(ip)) - dsize = gfs2_max_stuffed_size(ip); - memcpy(kaddr, dibh->b_data + sizeof(struct gfs2_dinode), dsize); memset(kaddr + dsize, 0, PAGE_SIZE - dsize); kunmap(page); @@ -1757,7 +1754,7 @@ static int punch_hole(struct gfs2_inode *ip, u64 offset, u64 length) u64 lblock = (offset + (1 << bsize_shift) - 1) >> bsize_shift; __u16 start_list[GFS2_MAX_META_HEIGHT]; __u16 __end_list[GFS2_MAX_META_HEIGHT], *end_list = NULL; - unsigned int start_aligned, uninitialized_var(end_aligned); + unsigned int start_aligned, end_aligned; unsigned int strip_h = ip->i_height - 1; u32 btotal = 0; int ret, state; diff --git a/fs/gfs2/glops.c b/fs/gfs2/glops.c index 20f08f4391c9d9cfb881af85e1135bd9dd020113..ff35cc365930c48265b347566701ea6f5c039bc0 100644 --- a/fs/gfs2/glops.c +++ b/fs/gfs2/glops.c @@ -339,6 +339,7 @@ static int inode_go_demote_ok(const struct gfs2_glock *gl) static int gfs2_dinode_in(struct gfs2_inode *ip, const void *buf) { + struct gfs2_sbd *sdp = GFS2_SB(&ip->i_inode); const struct gfs2_dinode *str = buf; struct timespec64 atime; u16 height, depth; @@ -378,7 +379,7 @@ static int gfs2_dinode_in(struct gfs2_inode *ip, const void *buf) /* i_diskflags and i_eattr must be set before gfs2_set_inode_flags() */ gfs2_set_inode_flags(&ip->i_inode); height = be16_to_cpu(str->di_height); - if (unlikely(height > GFS2_MAX_META_HEIGHT)) + if (unlikely(height > sdp->sd_max_height)) goto corrupt; ip->i_height = (u8)height; @@ -388,6 +389,9 @@ static int gfs2_dinode_in(struct gfs2_inode *ip, const void *buf) ip->i_depth = (u8)depth; ip->i_entries = be32_to_cpu(str->di_entries); + if (gfs2_is_stuffed(ip) && ip->i_inode.i_size > gfs2_max_stuffed_size(ip)) + goto corrupt; + if (S_ISREG(ip->i_inode.i_mode)) gfs2_set_aops(&ip->i_inode); diff --git a/fs/gfs2/quota.c b/fs/gfs2/quota.c index dd0f9bc13164b81958f8b7db5854bb64fb311487..9f753595d90ee79b4277a88ef0a8bd63e236b7be 100644 --- a/fs/gfs2/quota.c +++ b/fs/gfs2/quota.c @@ -434,6 +434,17 @@ static int qd_check_sync(struct gfs2_sbd *sdp, struct gfs2_quota_data *qd, (sync_gen && (qd->qd_sync_gen >= *sync_gen))) return 0; + /* + * If qd_change is 0 it means a pending quota change was negated. + * We should not sync it, but we still have a qd reference and slot + * reference taken by gfs2_quota_change -> do_qc that need to be put. + */ + if (!qd->qd_change && test_and_clear_bit(QDF_CHANGE, &qd->qd_flags)) { + slot_put(qd); + qd_put(qd); + return 0; + } + if (!lockref_get_not_dead(&qd->qd_lockref)) return 0; diff --git a/fs/gfs2/super.c b/fs/gfs2/super.c index 3cc2237e58967af540ce5ba03c7fd0a2cf069d3b..29157f7d9663d3ea444b9da2ea3fabcc72d2dad1 100644 --- a/fs/gfs2/super.c +++ b/fs/gfs2/super.c @@ -1374,7 +1374,14 @@ static int gfs2_show_options(struct seq_file *s, struct dentry *root) { struct gfs2_sbd *sdp = root->d_sb->s_fs_info; struct gfs2_args *args = &sdp->sd_args; - int val; + unsigned int logd_secs, statfs_slow, statfs_quantum, quota_quantum; + + spin_lock(&sdp->sd_tune.gt_spin); + logd_secs = sdp->sd_tune.gt_logd_secs; + quota_quantum = sdp->sd_tune.gt_quota_quantum; + statfs_quantum = sdp->sd_tune.gt_statfs_quantum; + statfs_slow = sdp->sd_tune.gt_statfs_slow; + spin_unlock(&sdp->sd_tune.gt_spin); if (is_ancestor(root, sdp->sd_master_dir)) seq_puts(s, ",meta"); @@ -1429,17 +1436,14 @@ static int gfs2_show_options(struct seq_file *s, struct dentry *root) } if (args->ar_discard) seq_puts(s, ",discard"); - val = sdp->sd_tune.gt_logd_secs; - if (val != 30) - seq_printf(s, ",commit=%d", val); - val = sdp->sd_tune.gt_statfs_quantum; - if (val != 30) - seq_printf(s, ",statfs_quantum=%d", val); - else if (sdp->sd_tune.gt_statfs_slow) + if (logd_secs != 30) + seq_printf(s, ",commit=%d", logd_secs); + if (statfs_quantum != 30) + seq_printf(s, ",statfs_quantum=%d", statfs_quantum); + else if (statfs_slow) seq_puts(s, ",statfs_quantum=0"); - val = sdp->sd_tune.gt_quota_quantum; - if (val != 60) - seq_printf(s, ",quota_quantum=%d", val); + if (quota_quantum != 60) + seq_printf(s, ",quota_quantum=%d", quota_quantum); if (args->ar_statfs_percent) seq_printf(s, ",statfs_percent=%d", args->ar_statfs_percent); if (args->ar_errors != GFS2_ERRORS_DEFAULT) { @@ -1586,6 +1590,14 @@ static void gfs2_evict_inode(struct inode *inode) if (inode->i_nlink || sb_rdonly(sb)) goto out; + /* + * In case of an incomplete mount, gfs2_evict_inode() may be called for + * system files without having an active journal to write to. In that + * case, skip the filesystem evict. + */ + if (!sdp->sd_jdesc) + goto out; + if (test_bit(GIF_ALLOC_FAILED, &ip->i_flags)) { BUG_ON(!gfs2_glock_is_locked_by_me(ip->i_gl)); gfs2_holder_mark_uninitialized(&gh); diff --git a/fs/hfs/bnode.c b/fs/hfs/bnode.c index c0a73a6ffb28bd9c6201e3469f5e8314924ff336..397e02a566970fdf14a80f2bd377f1fe159c4f90 100644 --- a/fs/hfs/bnode.c +++ b/fs/hfs/bnode.c @@ -281,6 +281,7 @@ static struct hfs_bnode *__hfs_bnode_create(struct hfs_btree *tree, u32 cnid) tree->node_hash[hash] = node; tree->node_hash_cnt++; } else { + hfs_bnode_get(node2); spin_unlock(&tree->hash_lock); kfree(node); wait_event(node2->lock_wq, !test_bit(HFS_BNODE_NEW, &node2->flags)); diff --git a/fs/hfsplus/inode.c b/fs/hfsplus/inode.c index c7073a1517d68ffbbcb367dae8d47ccc97e84e72..a1d4ad584b10534d8cff353ab137a0d8b7047091 100644 --- a/fs/hfsplus/inode.c +++ b/fs/hfsplus/inode.c @@ -476,7 +476,11 @@ int hfsplus_cat_read_inode(struct inode *inode, struct hfs_find_data *fd) if (type == HFSPLUS_FOLDER) { struct hfsplus_cat_folder *folder = &entry.folder; - WARN_ON(fd->entrylength < sizeof(struct hfsplus_cat_folder)); + if (fd->entrylength < sizeof(struct hfsplus_cat_folder)) { + pr_err("bad catalog folder entry\n"); + res = -EIO; + goto out; + } hfs_bnode_read(fd->bnode, &entry, fd->entryoffset, sizeof(struct hfsplus_cat_folder)); hfsplus_get_perms(inode, &folder->permissions, 1); @@ -496,7 +500,11 @@ int hfsplus_cat_read_inode(struct inode *inode, struct hfs_find_data *fd) } else if (type == HFSPLUS_FILE) { struct hfsplus_cat_file *file = &entry.file; - WARN_ON(fd->entrylength < sizeof(struct hfsplus_cat_file)); + if (fd->entrylength < sizeof(struct hfsplus_cat_file)) { + pr_err("bad catalog file entry\n"); + res = -EIO; + goto out; + } hfs_bnode_read(fd->bnode, &entry, fd->entryoffset, sizeof(struct hfsplus_cat_file)); @@ -527,6 +535,7 @@ int hfsplus_cat_read_inode(struct inode *inode, struct hfs_find_data *fd) pr_err("bad catalog entry used to create inode\n"); res = -EIO; } +out: return res; } @@ -535,6 +544,7 @@ int hfsplus_cat_write_inode(struct inode *inode) struct inode *main_inode = inode; struct hfs_find_data fd; hfsplus_cat_entry entry; + int res = 0; if (HFSPLUS_IS_RSRC(inode)) main_inode = HFSPLUS_I(inode)->rsrc_inode; @@ -553,7 +563,11 @@ int hfsplus_cat_write_inode(struct inode *inode) if (S_ISDIR(main_inode->i_mode)) { struct hfsplus_cat_folder *folder = &entry.folder; - WARN_ON(fd.entrylength < sizeof(struct hfsplus_cat_folder)); + if (fd.entrylength < sizeof(struct hfsplus_cat_folder)) { + pr_err("bad catalog folder entry\n"); + res = -EIO; + goto out; + } hfs_bnode_read(fd.bnode, &entry, fd.entryoffset, sizeof(struct hfsplus_cat_folder)); /* simple node checks? */ @@ -578,7 +592,11 @@ int hfsplus_cat_write_inode(struct inode *inode) } else { struct hfsplus_cat_file *file = &entry.file; - WARN_ON(fd.entrylength < sizeof(struct hfsplus_cat_file)); + if (fd.entrylength < sizeof(struct hfsplus_cat_file)) { + pr_err("bad catalog file entry\n"); + res = -EIO; + goto out; + } hfs_bnode_read(fd.bnode, &entry, fd.entryoffset, sizeof(struct hfsplus_cat_file)); hfsplus_inode_write_fork(inode, &file->data_fork); @@ -599,5 +617,5 @@ int hfsplus_cat_write_inode(struct inode *inode) set_bit(HFSPLUS_I_CAT_DIRTY, &HFSPLUS_I(inode)->flags); out: hfs_find_exit(&fd); - return 0; + return res; } diff --git a/fs/hfsplus/super.c b/fs/hfsplus/super.c index eb4535eba95d9a5e13dfda5fb196849a069bda64..3b1356b10a4725b8153c82964097aebca733de35 100644 --- a/fs/hfsplus/super.c +++ b/fs/hfsplus/super.c @@ -294,11 +294,11 @@ static void hfsplus_put_super(struct super_block *sb) hfsplus_sync_fs(sb, 1); } + iput(sbi->alloc_file); + iput(sbi->hidden_dir); hfs_btree_close(sbi->attr_tree); hfs_btree_close(sbi->cat_tree); hfs_btree_close(sbi->ext_tree); - iput(sbi->alloc_file); - iput(sbi->hidden_dir); kfree(sbi->s_vhdr_buf); kfree(sbi->s_backup_vhdr_buf); unload_nls(sbi->nls); diff --git a/fs/hfsplus/unicode.c b/fs/hfsplus/unicode.c index c8d1b2be7854ea5a829dfe6749121d0a70182903..73342c925a4b6efb900885e849fa797fdc63782e 100644 --- a/fs/hfsplus/unicode.c +++ b/fs/hfsplus/unicode.c @@ -398,7 +398,7 @@ int hfsplus_hash_dentry(const struct dentry *dentry, struct qstr *str) astr = str->name; len = str->len; while (len > 0) { - int uninitialized_var(dsize); + int dsize; size = asc2unichar(sb, astr, len, &c); astr += size; len -= size; diff --git a/fs/incfs/main.c b/fs/incfs/main.c index aac87b105b5d04b2435e72eb44d9061933d5c609..6f8c4dd6e04248bae7ae01cbd731a48e3b24291b 100644 --- a/fs/incfs/main.c +++ b/fs/incfs/main.c @@ -30,6 +30,15 @@ static ssize_t corefs_show(struct kobject *kobj, static struct kobj_attribute corefs_attr = __ATTR_RO(corefs); +static ssize_t bugfix_inode_eviction_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buff) +{ + return snprintf(buff, PAGE_SIZE, "supported\n"); +} + +static struct kobj_attribute bugfix_inode_eviction_attr = + __ATTR_RO(bugfix_inode_eviction); + static ssize_t mounter_context_for_backing_rw_show(struct kobject *kobj, struct kobj_attribute *attr, char *buff) { @@ -41,6 +50,7 @@ static struct kobj_attribute mounter_context_for_backing_rw_attr = static struct attribute *attributes[] = { &corefs_attr.attr, + &bugfix_inode_eviction_attr.attr, &mounter_context_for_backing_rw_attr.attr, NULL, }; diff --git a/fs/incfs/vfs.c b/fs/incfs/vfs.c index 96981c63cdfe1ea5552a807361f3cd653b82c9cb..ac221619f19b52d896e293593f4ebadd08d6c32b 100644 --- a/fs/incfs/vfs.c +++ b/fs/incfs/vfs.c @@ -2309,6 +2309,13 @@ void incfs_kill_sb(struct super_block *sb) pr_debug("incfs: unmount\n"); + /* + * We must kill the super before freeing mi, since killing the super + * triggers inode eviction, which triggers the final update of the + * backing file, which uses certain information for mi + */ + kill_anon_super(sb); + if (mi) { if (mi->mi_backing_dir_path.dentry) dinode = d_inode(mi->mi_backing_dir_path.dentry); @@ -2320,7 +2327,6 @@ void incfs_kill_sb(struct super_block *sb) incfs_free_mount_info(mi); sb->s_fs_info = NULL; } - kill_anon_super(sb); } static int show_options(struct seq_file *m, struct dentry *root) diff --git a/fs/iomap.c b/fs/iomap.c index 9a20f76ac9970c214e117be27f7391b675ab31b4..4c47fbd669f99f05f1b16885529ee8aa471ba8e1 100644 --- a/fs/iomap.c +++ b/fs/iomap.c @@ -113,6 +113,7 @@ static struct iomap_page * iomap_page_create(struct inode *inode, struct page *page) { struct iomap_page *iop = to_iomap_page(page); + unsigned int nr_blocks = PAGE_SIZE / i_blocksize(inode); if (iop || i_blocksize(inode) == PAGE_SIZE) return iop; @@ -122,6 +123,8 @@ iomap_page_create(struct inode *inode, struct page *page) atomic_set(&iop->write_count, 0); spin_lock_init(&iop->uptodate_lock); bitmap_zero(iop->uptodate, PAGE_SIZE / SECTOR_SIZE); + if (PageUptodate(page)) + bitmap_fill(iop->uptodate, nr_blocks); /* * migrate_page_move_mapping() assumes that pages with private data have diff --git a/fs/isofs/namei.c b/fs/isofs/namei.c index 558e7c51ce0d4b99771f53ef2feb38954eb348ae..58f80e1b3ac0d5082c24b5dbfd064cf5bff7d5a5 100644 --- a/fs/isofs/namei.c +++ b/fs/isofs/namei.c @@ -153,8 +153,8 @@ isofs_find_entry(struct inode *dir, struct dentry *dentry, struct dentry *isofs_lookup(struct inode *dir, struct dentry *dentry, unsigned int flags) { int found; - unsigned long uninitialized_var(block); - unsigned long uninitialized_var(offset); + unsigned long block; + unsigned long offset; struct inode *inode; struct page *page; diff --git a/fs/jbd2/recovery.c b/fs/jbd2/recovery.c index a4967b27ffb636212ddd21234b1b2fc211a6038b..ed923a9765c268b47a388593d56805c60a8aeeee 100644 --- a/fs/jbd2/recovery.c +++ b/fs/jbd2/recovery.c @@ -247,6 +247,8 @@ int jbd2_journal_recover(journal_t *journal) journal_superblock_t * sb; struct recovery_info info; + errseq_t wb_err; + struct address_space *mapping; memset(&info, 0, sizeof(info)); sb = journal->j_superblock; @@ -264,6 +266,9 @@ int jbd2_journal_recover(journal_t *journal) return 0; } + wb_err = 0; + mapping = journal->j_fs_dev->bd_inode->i_mapping; + errseq_check_and_advance(&mapping->wb_err, &wb_err); err = do_one_pass(journal, &info, PASS_SCAN); if (!err) err = do_one_pass(journal, &info, PASS_REVOKE); @@ -282,6 +287,9 @@ int jbd2_journal_recover(journal_t *journal) jbd2_journal_clear_revoke(journal); err2 = sync_blockdev(journal->j_fs_dev); + if (!err) + err = err2; + err2 = errseq_check_and_advance(&mapping->wb_err, &wb_err); if (!err) err = err2; /* Make sure all replayed data is on permanent storage */ diff --git a/fs/jffs2/build.c b/fs/jffs2/build.c index 837cd55fd4c5e534b0b0c802b1dc1669c9b7a5c2..6ae9d6fefb8617593c72f6c5eb87c7e36bf26ff3 100644 --- a/fs/jffs2/build.c +++ b/fs/jffs2/build.c @@ -211,7 +211,10 @@ static int jffs2_build_filesystem(struct jffs2_sb_info *c) ic->scan_dents = NULL; cond_resched(); } - jffs2_build_xattr_subsystem(c); + ret = jffs2_build_xattr_subsystem(c); + if (ret) + goto exit; + c->flags &= ~JFFS2_SB_FLAG_BUILDING; dbg_fsbuild("FS build complete\n"); diff --git a/fs/jffs2/erase.c b/fs/jffs2/erase.c index 83b8f06b4a642f3917b7720a2acd687854927ca3..7e9abdb8971225f483451a8f9182bebdfceb99d8 100644 --- a/fs/jffs2/erase.c +++ b/fs/jffs2/erase.c @@ -401,7 +401,7 @@ static void jffs2_mark_erased_block(struct jffs2_sb_info *c, struct jffs2_eraseb { size_t retlen; int ret; - uint32_t uninitialized_var(bad_offset); + uint32_t bad_offset; switch (jffs2_block_check_erase(c, jeb, &bad_offset)) { case -EAGAIN: goto refile; diff --git a/fs/jffs2/file.c b/fs/jffs2/file.c index 34880a4c217327c10e49e4b472ae82c99b570b63..94bd4bbd3787507c9f779954d026e87b2c2de292 100644 --- a/fs/jffs2/file.c +++ b/fs/jffs2/file.c @@ -137,19 +137,18 @@ static int jffs2_write_begin(struct file *filp, struct address_space *mapping, struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode); struct jffs2_sb_info *c = JFFS2_SB_INFO(inode->i_sb); pgoff_t index = pos >> PAGE_SHIFT; - uint32_t pageofs = index << PAGE_SHIFT; int ret = 0; jffs2_dbg(1, "%s()\n", __func__); - if (pageofs > inode->i_size) { - /* Make new hole frag from old EOF to new page */ + if (pos > inode->i_size) { + /* Make new hole frag from old EOF to new position */ struct jffs2_raw_inode ri; struct jffs2_full_dnode *fn; uint32_t alloc_len; - jffs2_dbg(1, "Writing new hole frag 0x%x-0x%x between current EOF and new page\n", - (unsigned int)inode->i_size, pageofs); + jffs2_dbg(1, "Writing new hole frag 0x%x-0x%x between current EOF and new position\n", + (unsigned int)inode->i_size, (uint32_t)pos); ret = jffs2_reserve_space(c, sizeof(ri), &alloc_len, ALLOC_NORMAL, JFFS2_SUMMARY_INODE_SIZE); @@ -169,10 +168,10 @@ static int jffs2_write_begin(struct file *filp, struct address_space *mapping, ri.mode = cpu_to_jemode(inode->i_mode); ri.uid = cpu_to_je16(i_uid_read(inode)); ri.gid = cpu_to_je16(i_gid_read(inode)); - ri.isize = cpu_to_je32(max((uint32_t)inode->i_size, pageofs)); + ri.isize = cpu_to_je32((uint32_t)pos); ri.atime = ri.ctime = ri.mtime = cpu_to_je32(JFFS2_NOW()); ri.offset = cpu_to_je32(inode->i_size); - ri.dsize = cpu_to_je32(pageofs - inode->i_size); + ri.dsize = cpu_to_je32((uint32_t)pos - inode->i_size); ri.csize = cpu_to_je32(0); ri.compr = JFFS2_COMPR_ZERO; ri.node_crc = cpu_to_je32(crc32(0, &ri, sizeof(ri)-8)); @@ -202,7 +201,7 @@ static int jffs2_write_begin(struct file *filp, struct address_space *mapping, goto out_err; } jffs2_complete_reservation(c); - inode->i_size = pageofs; + inode->i_size = pos; mutex_unlock(&f->sem); } diff --git a/fs/jffs2/xattr.c b/fs/jffs2/xattr.c index da3e18503c6582074257e2714216bfb24b3a6f32..acb4492f5970ca96aa8e1e3c712ed8e855331f81 100644 --- a/fs/jffs2/xattr.c +++ b/fs/jffs2/xattr.c @@ -772,10 +772,10 @@ void jffs2_clear_xattr_subsystem(struct jffs2_sb_info *c) } #define XREF_TMPHASH_SIZE (128) -void jffs2_build_xattr_subsystem(struct jffs2_sb_info *c) +int jffs2_build_xattr_subsystem(struct jffs2_sb_info *c) { struct jffs2_xattr_ref *ref, *_ref; - struct jffs2_xattr_ref *xref_tmphash[XREF_TMPHASH_SIZE]; + struct jffs2_xattr_ref **xref_tmphash; struct jffs2_xattr_datum *xd, *_xd; struct jffs2_inode_cache *ic; struct jffs2_raw_node_ref *raw; @@ -784,9 +784,12 @@ void jffs2_build_xattr_subsystem(struct jffs2_sb_info *c) BUG_ON(!(c->flags & JFFS2_SB_FLAG_BUILDING)); + xref_tmphash = kcalloc(XREF_TMPHASH_SIZE, + sizeof(struct jffs2_xattr_ref *), GFP_KERNEL); + if (!xref_tmphash) + return -ENOMEM; + /* Phase.1 : Merge same xref */ - for (i=0; i < XREF_TMPHASH_SIZE; i++) - xref_tmphash[i] = NULL; for (ref=c->xref_temp; ref; ref=_ref) { struct jffs2_xattr_ref *tmp; @@ -884,6 +887,8 @@ void jffs2_build_xattr_subsystem(struct jffs2_sb_info *c) "%u of xref (%u dead, %u orphan) found.\n", xdatum_count, xdatum_unchecked_count, xdatum_orphan_count, xref_count, xref_dead_count, xref_orphan_count); + kfree(xref_tmphash); + return 0; } struct jffs2_xattr_datum *jffs2_setup_xattr_datum(struct jffs2_sb_info *c, diff --git a/fs/jffs2/xattr.h b/fs/jffs2/xattr.h index 720007b2fd65defb63ded33466f60a9ec52ec364..1b5030a3349db969cc5c1247b9d5e8fede23dc66 100644 --- a/fs/jffs2/xattr.h +++ b/fs/jffs2/xattr.h @@ -71,7 +71,7 @@ static inline int is_xattr_ref_dead(struct jffs2_xattr_ref *ref) #ifdef CONFIG_JFFS2_FS_XATTR extern void jffs2_init_xattr_subsystem(struct jffs2_sb_info *c); -extern void jffs2_build_xattr_subsystem(struct jffs2_sb_info *c); +extern int jffs2_build_xattr_subsystem(struct jffs2_sb_info *c); extern void jffs2_clear_xattr_subsystem(struct jffs2_sb_info *c); extern struct jffs2_xattr_datum *jffs2_setup_xattr_datum(struct jffs2_sb_info *c, @@ -103,7 +103,7 @@ extern ssize_t jffs2_listxattr(struct dentry *, char *, size_t); #else #define jffs2_init_xattr_subsystem(c) -#define jffs2_build_xattr_subsystem(c) +#define jffs2_build_xattr_subsystem(c) (0) #define jffs2_clear_xattr_subsystem(c) #define jffs2_xattr_do_crccheck_inode(c, ic) diff --git a/fs/jfs/jfs_dmap.c b/fs/jfs/jfs_dmap.c index f06796cad9aa8e91bc308a5a7ea7e1c92778ac26..2f452b5ee731336e7a6e88c21733b01838f23d14 100644 --- a/fs/jfs/jfs_dmap.c +++ b/fs/jfs/jfs_dmap.c @@ -100,7 +100,7 @@ static int dbAllocCtl(struct bmap * bmp, s64 nblocks, int l2nb, s64 blkno, static int dbExtend(struct inode *ip, s64 blkno, s64 nblocks, s64 addnblocks); static int dbFindBits(u32 word, int l2nb); static int dbFindCtl(struct bmap * bmp, int l2nb, int level, s64 * blkno); -static int dbFindLeaf(dmtree_t * tp, int l2nb, int *leafidx); +static int dbFindLeaf(dmtree_t *tp, int l2nb, int *leafidx, bool is_ctl); static int dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno, int nblocks); static int dbFreeDmap(struct bmap * bmp, struct dmap * dp, s64 blkno, @@ -191,7 +191,14 @@ int dbMount(struct inode *ipbmap) dbmp_le = (struct dbmap_disk *) mp->data; bmp->db_mapsize = le64_to_cpu(dbmp_le->dn_mapsize); bmp->db_nfree = le64_to_cpu(dbmp_le->dn_nfree); + bmp->db_l2nbperpage = le32_to_cpu(dbmp_le->dn_l2nbperpage); + if (bmp->db_l2nbperpage > L2PSIZE - L2MINBLOCKSIZE || + bmp->db_l2nbperpage < 0) { + err = -EINVAL; + goto err_release_metapage; + } + bmp->db_numag = le32_to_cpu(dbmp_le->dn_numag); if (!bmp->db_numag) { err = -EINVAL; @@ -201,12 +208,19 @@ int dbMount(struct inode *ipbmap) bmp->db_maxlevel = le32_to_cpu(dbmp_le->dn_maxlevel); bmp->db_maxag = le32_to_cpu(dbmp_le->dn_maxag); bmp->db_agpref = le32_to_cpu(dbmp_le->dn_agpref); + if (bmp->db_maxag >= MAXAG || bmp->db_maxag < 0 || + bmp->db_agpref >= MAXAG || bmp->db_agpref < 0) { + err = -EINVAL; + goto err_release_metapage; + } + bmp->db_aglevel = le32_to_cpu(dbmp_le->dn_aglevel); bmp->db_agheight = le32_to_cpu(dbmp_le->dn_agheight); bmp->db_agwidth = le32_to_cpu(dbmp_le->dn_agwidth); bmp->db_agstart = le32_to_cpu(dbmp_le->dn_agstart); bmp->db_agl2size = le32_to_cpu(dbmp_le->dn_agl2size); - if (bmp->db_agl2size > L2MAXL2SIZE - L2MAXAG) { + if (bmp->db_agl2size > L2MAXL2SIZE - L2MAXAG || + bmp->db_agl2size < 0) { err = -EINVAL; goto err_release_metapage; } @@ -275,6 +289,7 @@ int dbUnmount(struct inode *ipbmap, int mounterror) /* free the memory for the in-memory bmap. */ kfree(bmp); + JFS_SBI(ipbmap->i_sb)->bmap = NULL; return (0); } @@ -1783,7 +1798,7 @@ static int dbFindCtl(struct bmap * bmp, int l2nb, int level, s64 * blkno) * dbFindLeaf() returns the index of the leaf at which * free space was found. */ - rc = dbFindLeaf((dmtree_t *) dcp, l2nb, &leafidx); + rc = dbFindLeaf((dmtree_t *) dcp, l2nb, &leafidx, true); /* release the buffer. */ @@ -2030,9 +2045,12 @@ dbAllocDmapLev(struct bmap * bmp, * free space. if sufficient free space is found, dbFindLeaf() * returns the index of the leaf at which free space was found. */ - if (dbFindLeaf((dmtree_t *) & dp->tree, l2nb, &leafidx)) + if (dbFindLeaf((dmtree_t *) &dp->tree, l2nb, &leafidx, false)) return -ENOSPC; + if (leafidx < 0) + return -EIO; + /* determine the block number within the file system corresponding * to the leaf at which free space was found. */ @@ -2987,14 +3005,18 @@ static void dbAdjTree(dmtree_t * tp, int leafno, int newval) * leafidx - return pointer to be set to the index of the leaf * describing at least l2nb free blocks if sufficient * free blocks are found. + * is_ctl - determines if the tree is of type ctl * * RETURN VALUES: * 0 - success * -ENOSPC - insufficient free blocks. */ -static int dbFindLeaf(dmtree_t * tp, int l2nb, int *leafidx) +static int dbFindLeaf(dmtree_t *tp, int l2nb, int *leafidx, bool is_ctl) { int ti, n = 0, k, x = 0; + int max_size; + + max_size = is_ctl ? CTLTREESIZE : TREESIZE; /* first check the root of the tree to see if there is * sufficient free space. @@ -3015,6 +3037,8 @@ static int dbFindLeaf(dmtree_t * tp, int l2nb, int *leafidx) /* sufficient free space found. move to the next * level (or quit if this is the last level). */ + if (x + n > max_size) + return -ENOSPC; if (l2nb <= tp->dmt_stree[x + n]) break; } diff --git a/fs/jfs/jfs_extent.c b/fs/jfs/jfs_extent.c index 2ae7d59ab10a595120b7a3a124e3e19fe408841d..c971e8a6525dea71b702a59c979afad376c6f7f7 100644 --- a/fs/jfs/jfs_extent.c +++ b/fs/jfs/jfs_extent.c @@ -521,6 +521,11 @@ extBalloc(struct inode *ip, s64 hint, s64 * nblocks, s64 * blkno) * blocks in the map. in that case, we'll start off with the * maximum free. */ + + /* give up if no space left */ + if (bmp->db_maxfreebud == -1) + return -ENOSPC; + max = (s64) 1 << bmp->db_maxfreebud; if (*nblocks >= max && *nblocks > nbperpage) nb = nblks = (max > nbperpage) ? max : nbperpage; diff --git a/fs/jfs/jfs_filsys.h b/fs/jfs/jfs_filsys.h index 415bfa90607a21ad38707627063dc718f7e2abd4..0c36ce6318d53d3179c0427ca1a688217aa61f56 100644 --- a/fs/jfs/jfs_filsys.h +++ b/fs/jfs/jfs_filsys.h @@ -135,7 +135,9 @@ #define NUM_INODE_PER_IAG INOSPERIAG #define MINBLOCKSIZE 512 +#define L2MINBLOCKSIZE 9 #define MAXBLOCKSIZE 4096 +#define L2MAXBLOCKSIZE 12 #define MAXFILESIZE ((s64)1 << 52) #define JFS_LINK_MAX 0xffffffff diff --git a/fs/jfs/jfs_imap.c b/fs/jfs/jfs_imap.c index 93e8c590ff5c060eb6026bf96d15d3db07a25a9f..b45cc109e50635bb0bf5831875a69c5cc7c6d46e 100644 --- a/fs/jfs/jfs_imap.c +++ b/fs/jfs/jfs_imap.c @@ -208,6 +208,7 @@ int diUnmount(struct inode *ipimap, int mounterror) * free in-memory control structure */ kfree(imap); + JFS_IP(ipimap)->i_imap = NULL; return (0); } @@ -1334,7 +1335,7 @@ diInitInode(struct inode *ip, int iagno, int ino, int extno, struct iag * iagp) int diAlloc(struct inode *pip, bool dir, struct inode *ip) { int rc, ino, iagno, addext, extno, bitno, sword; - int nwords, rem, i, agno; + int nwords, rem, i, agno, dn_numag; u32 mask, inosmap, extsmap; struct inode *ipimap; struct metapage *mp; @@ -1370,6 +1371,9 @@ int diAlloc(struct inode *pip, bool dir, struct inode *ip) /* get the ag number of this iag */ agno = BLKTOAG(JFS_IP(pip)->agstart, JFS_SBI(pip->i_sb)); + dn_numag = JFS_SBI(pip->i_sb)->bmap->db_numag; + if (agno < 0 || agno > dn_numag) + return -EIO; if (atomic_read(&JFS_SBI(pip->i_sb)->bmap->db_active[agno])) { /* diff --git a/fs/jfs/jfs_txnmgr.c b/fs/jfs/jfs_txnmgr.c index 78789c5ed36b02f7106c40630e484656612c891f..e10db01f253b813da2483d99fd13c476725d00e2 100644 --- a/fs/jfs/jfs_txnmgr.c +++ b/fs/jfs/jfs_txnmgr.c @@ -367,6 +367,11 @@ tid_t txBegin(struct super_block *sb, int flag) jfs_info("txBegin: flag = 0x%x", flag); log = JFS_SBI(sb)->log; + if (!log) { + jfs_error(sb, "read-only filesystem\n"); + return 0; + } + TXN_LOCK(); INCREMENT(TxStat.txBegin); diff --git a/fs/jfs/namei.c b/fs/jfs/namei.c index 14528c0ffe635a30cb1a3efb403e4f2a429d5034..c2c439acbb780932d5039d8b9885c851cd27e4fa 100644 --- a/fs/jfs/namei.c +++ b/fs/jfs/namei.c @@ -811,6 +811,11 @@ static int jfs_link(struct dentry *old_dentry, if (rc) goto out; + if (isReadOnly(ip)) { + jfs_error(ip->i_sb, "read-only filesystem\n"); + return -EROFS; + } + tid = txBegin(ip->i_sb, 0); mutex_lock_nested(&JFS_IP(dir)->commit_mutex, COMMIT_MUTEX_PARENT); diff --git a/fs/kernfs/mount.c b/fs/kernfs/mount.c index d71c9405874a04d1d406a420317a0e4535400ac3..c0f1e7e7a88364954d49588096162a2ab0a6fe13 100644 --- a/fs/kernfs/mount.c +++ b/fs/kernfs/mount.c @@ -212,7 +212,7 @@ struct dentry *kernfs_node_dentry(struct kernfs_node *kn, dput(dentry); return ERR_PTR(-EINVAL); } - dtmp = lookup_one_len_unlocked(kntmp->name, dentry, + dtmp = lookup_positive_unlocked(kntmp->name, dentry, strlen(kntmp->name)); dput(dentry); if (IS_ERR(dtmp)) diff --git a/fs/lockd/mon.c b/fs/lockd/mon.c index 654594ef4f945ab95d6f4fdc6cb9365b9a4d8595..68a2eac548c3ccc6b1d123ee4f50f0cb4e222360 100644 --- a/fs/lockd/mon.c +++ b/fs/lockd/mon.c @@ -275,6 +275,9 @@ static struct nsm_handle *nsm_create_handle(const struct sockaddr *sap, { struct nsm_handle *new; + if (!hostname) + return NULL; + new = kzalloc(sizeof(*new) + hostname_len + 1, GFP_KERNEL); if (unlikely(new == NULL)) return NULL; diff --git a/fs/namei.c b/fs/namei.c index df6d9a20997832c053f7611a86395bd117fa6d35..94f388e94dd1d432ce0a744ecabe91928c9b92e5 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -2675,6 +2675,26 @@ struct dentry *lookup_one_len_unlocked(const char *name, } EXPORT_SYMBOL(lookup_one_len_unlocked); +/* + * Like lookup_one_len_unlocked(), except that it yields ERR_PTR(-ENOENT) + * on negatives. Returns known positive or ERR_PTR(); that's what + * most of the users want. Note that pinned negative with unlocked parent + * _can_ become positive at any time, so callers of lookup_one_len_unlocked() + * need to be very careful; pinned positives have ->d_inode stable, so + * this one avoids such problems. + */ +struct dentry *lookup_positive_unlocked(const char *name, + struct dentry *base, int len) +{ + struct dentry *ret = lookup_one_len_unlocked(name, base, len); + if (!IS_ERR(ret) && d_is_negative(ret)) { + dput(ret); + ret = ERR_PTR(-ENOENT); + } + return ret; +} +EXPORT_SYMBOL(lookup_positive_unlocked); + #ifdef CONFIG_UNIX98_PTYS int path_pts(struct path *path) { @@ -2693,7 +2713,7 @@ int path_pts(struct path *path) this.name = "pts"; this.len = 3; child = d_hash_and_lookup(parent, &this); - if (!child) + if (IS_ERR_OR_NULL(child)) return -ENOENT; path->dentry = child; diff --git a/fs/nfs/blocklayout/dev.c b/fs/nfs/blocklayout/dev.c index dec5880ac6de28aa393406e931c4a2f70d2a5fda..6e3a14fdff9c8841b0d1af30a88926081ef725ef 100644 --- a/fs/nfs/blocklayout/dev.c +++ b/fs/nfs/blocklayout/dev.c @@ -422,7 +422,7 @@ bl_parse_concat(struct nfs_server *server, struct pnfs_block_dev *d, int ret, i; d->children = kcalloc(v->concat.volumes_count, - sizeof(struct pnfs_block_dev), GFP_KERNEL); + sizeof(struct pnfs_block_dev), gfp_mask); if (!d->children) return -ENOMEM; @@ -451,7 +451,7 @@ bl_parse_stripe(struct nfs_server *server, struct pnfs_block_dev *d, int ret, i; d->children = kcalloc(v->stripe.volumes_count, - sizeof(struct pnfs_block_dev), GFP_KERNEL); + sizeof(struct pnfs_block_dev), gfp_mask); if (!d->children) return -ENOMEM; diff --git a/fs/nfs/flexfilelayout/flexfilelayout.c b/fs/nfs/flexfilelayout/flexfilelayout.c index fee421da219757f3109c2b26849c1086beb418bb..bb10f2b21cc1d47985e20cc2b59b2f1252497171 100644 --- a/fs/nfs/flexfilelayout/flexfilelayout.c +++ b/fs/nfs/flexfilelayout/flexfilelayout.c @@ -1189,6 +1189,7 @@ static void ff_layout_io_track_ds_error(struct pnfs_layout_segment *lseg, case -EPFNOSUPPORT: case -EPROTONOSUPPORT: case -EOPNOTSUPP: + case -EINVAL: case -ECONNREFUSED: case -ECONNRESET: case -EHOSTDOWN: diff --git a/fs/nfs/nfs4_fs.h b/fs/nfs/nfs4_fs.h index 5ac7bf24c507b822797a1c760d93bd4772a202c0..2d438318681a5a20507ba4de46872d3a44feb7f8 100644 --- a/fs/nfs/nfs4_fs.h +++ b/fs/nfs/nfs4_fs.h @@ -190,7 +190,7 @@ struct nfs4_state { unsigned int n_wronly; /* Number of write-only references */ unsigned int n_rdwr; /* Number of read/write references */ fmode_t state; /* State on the server (R,W, or RW) */ - atomic_t count; + refcount_t count; wait_queue_head_t waitq; }; diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c index 250fa88303fad9b1b266590b11727aa5f69738fe..c44efead1a329f5ed920becb552c81fbc4aa1151 100644 --- a/fs/nfs/nfs4proc.c +++ b/fs/nfs/nfs4proc.c @@ -1792,7 +1792,7 @@ static struct nfs4_state *nfs4_try_open_cached(struct nfs4_opendata *opendata) out: return ERR_PTR(ret); out_return_state: - atomic_inc(&state->count); + refcount_inc(&state->count); return state; } @@ -1851,8 +1851,7 @@ _nfs4_opendata_reclaim_to_nfs4_state(struct nfs4_opendata *data) if (!data->rpc_done) { if (data->rpc_status) return ERR_PTR(data->rpc_status); - /* cached opens have already been processed */ - goto update; + return nfs4_try_open_cached(data); } ret = nfs_refresh_inode(inode, &data->f_attr); @@ -1861,10 +1860,11 @@ _nfs4_opendata_reclaim_to_nfs4_state(struct nfs4_opendata *data) if (data->o_res.delegation_type != 0) nfs4_opendata_check_deleg(data, state); -update: - update_open_stateid(state, &data->o_res.stateid, NULL, - data->o_arg.fmode); - atomic_inc(&state->count); + + if (!update_open_stateid(state, &data->o_res.stateid, + NULL, data->o_arg.fmode)) + return ERR_PTR(-EAGAIN); + refcount_inc(&state->count); return state; } @@ -1902,7 +1902,7 @@ nfs4_opendata_find_nfs4_state(struct nfs4_opendata *data) return ERR_CAST(inode); if (data->state != NULL && data->state->inode == inode) { state = data->state; - atomic_inc(&state->count); + refcount_inc(&state->count); } else state = nfs4_get_open_state(inode, data->owner); iput(inode); @@ -1928,8 +1928,11 @@ _nfs4_opendata_to_nfs4_state(struct nfs4_opendata *data) if (data->o_res.delegation_type != 0) nfs4_opendata_check_deleg(data, state); - update_open_stateid(state, &data->o_res.stateid, NULL, - data->o_arg.fmode); + if (!update_open_stateid(state, &data->o_res.stateid, + NULL, data->o_arg.fmode)) { + nfs4_put_open_state(state); + state = ERR_PTR(-EAGAIN); + } out: nfs_release_seqid(data->o_arg.seqid); return state; @@ -1975,7 +1978,7 @@ static struct nfs4_opendata *nfs4_open_recoverdata_alloc(struct nfs_open_context if (opendata == NULL) return ERR_PTR(-ENOMEM); opendata->state = state; - atomic_inc(&state->count); + refcount_inc(&state->count); return opendata; } @@ -5140,7 +5143,7 @@ static void nfs4_proc_write_setup(struct nfs_pgio_header *hdr, msg->rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_WRITE]; nfs4_init_sequence(&hdr->args.seq_args, &hdr->res.seq_res, 0, 0); - nfs4_state_protect_write(server->nfs_client, clnt, msg, hdr); + nfs4_state_protect_write(hdr->ds_clp ? hdr->ds_clp : server->nfs_client, clnt, msg, hdr); } static void nfs4_proc_commit_rpc_prepare(struct rpc_task *task, struct nfs_commit_data *data) @@ -5181,7 +5184,8 @@ static void nfs4_proc_commit_setup(struct nfs_commit_data *data, struct rpc_mess data->res.server = server; msg->rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_COMMIT]; nfs4_init_sequence(&data->args.seq_args, &data->res.seq_res, 1, 0); - nfs4_state_protect(server->nfs_client, NFS_SP4_MACH_CRED_COMMIT, clnt, msg); + nfs4_state_protect(data->ds_clp ? data->ds_clp : server->nfs_client, + NFS_SP4_MACH_CRED_COMMIT, clnt, msg); } static int _nfs4_proc_commit(struct file *dst, struct nfs_commitargs *args, diff --git a/fs/nfs/nfs4state.c b/fs/nfs/nfs4state.c index b9fbd01ef4cfed72be74847c518e815c73cba860..f0f0fb7499e3a2f6f018d702842d1391d2d45095 100644 --- a/fs/nfs/nfs4state.c +++ b/fs/nfs/nfs4state.c @@ -66,6 +66,8 @@ #define OPENOWNER_POOL_SIZE 8 +static void nfs4_state_start_reclaim_reboot(struct nfs_client *clp); + const nfs4_stateid zero_stateid = { { .data = { 0 } }, .type = NFS4_SPECIAL_STATEID_TYPE, @@ -338,6 +340,8 @@ int nfs41_init_clientid(struct nfs_client *clp, struct rpc_cred *cred) status = nfs4_proc_create_session(clp, cred); if (status != 0) goto out; + if (!(clp->cl_exchange_flags & EXCHGID4_FLAG_CONFIRMED_R)) + nfs4_state_start_reclaim_reboot(clp); nfs41_finish_session_reset(clp); nfs_mark_client_ready(clp, NFS_CS_READY); out: @@ -675,7 +679,7 @@ nfs4_alloc_open_state(void) state = kzalloc(sizeof(*state), GFP_NOFS); if (!state) return NULL; - atomic_set(&state->count, 1); + refcount_set(&state->count, 1); INIT_LIST_HEAD(&state->lock_states); spin_lock_init(&state->state_lock); seqlock_init(&state->seqlock); @@ -709,7 +713,7 @@ __nfs4_find_state_byowner(struct inode *inode, struct nfs4_state_owner *owner) continue; if (!nfs4_valid_open_stateid(state)) continue; - if (atomic_inc_not_zero(&state->count)) + if (refcount_inc_not_zero(&state->count)) return state; } return NULL; @@ -763,7 +767,7 @@ void nfs4_put_open_state(struct nfs4_state *state) struct inode *inode = state->inode; struct nfs4_state_owner *owner = state->owner; - if (!atomic_dec_and_lock(&state->count, &owner->so_lock)) + if (!refcount_dec_and_lock(&state->count, &owner->so_lock)) return; spin_lock(&inode->i_lock); list_del(&state->inode_states); @@ -1596,7 +1600,7 @@ static int nfs4_reclaim_open_state(struct nfs4_state_owner *sp, const struct nfs continue; if (state->state == 0) continue; - atomic_inc(&state->count); + refcount_inc(&state->count); spin_unlock(&sp->so_lock); status = ops->recover_open(sp, state); if (status >= 0) { diff --git a/fs/nfs/pnfs_dev.c b/fs/nfs/pnfs_dev.c index e8a07b3f9aaaf7b7a5f4ba051746bf357c6a85e1..ba67906d6b2c064e0a305ae9cdc9e9026b88e950 100644 --- a/fs/nfs/pnfs_dev.c +++ b/fs/nfs/pnfs_dev.c @@ -152,7 +152,7 @@ nfs4_get_device_info(struct nfs_server *server, set_bit(NFS_DEVICEID_NOCACHE, &d->flags); out_free_pages: - for (i = 0; i < max_pages; i++) + while (--i >= 0) __free_page(pages[i]); kfree(pages); out_free_pdev: diff --git a/fs/nfs/write.c b/fs/nfs/write.c index ec0fd6b3d185ae16f686668e8b53ff0641be1a1b..65aaa6eaad2c1faceda214f4a082288b7788a0ed 100644 --- a/fs/nfs/write.c +++ b/fs/nfs/write.c @@ -598,9 +598,8 @@ nfs_lock_and_join_requests(struct page *page) static void nfs_write_error_remove_page(struct nfs_page *req) { + SetPageError(req->wb_page); nfs_end_page_writeback(req); - generic_error_remove_page(page_file_mapping(req->wb_page), - req->wb_page); nfs_release_request(req); } diff --git a/fs/nfsd/blocklayoutxdr.c b/fs/nfsd/blocklayoutxdr.c index 442543304930b8d90f6019a657735dcf25d1cf98..2455dc8be18a86a74463e911f2137bae3a316a0d 100644 --- a/fs/nfsd/blocklayoutxdr.c +++ b/fs/nfsd/blocklayoutxdr.c @@ -82,6 +82,15 @@ nfsd4_block_encode_getdeviceinfo(struct xdr_stream *xdr, int len = sizeof(__be32), ret, i; __be32 *p; + /* + * See paragraph 5 of RFC 8881 S18.40.3. + */ + if (!gdp->gd_maxcount) { + if (xdr_stream_encode_u32(xdr, 0) != XDR_UNIT) + return nfserr_resource; + return nfs_ok; + } + p = xdr_reserve_space(xdr, len + sizeof(__be32)); if (!p) return nfserr_resource; diff --git a/fs/nfsd/flexfilelayoutxdr.c b/fs/nfsd/flexfilelayoutxdr.c index e81d2a5cf381e39952f33fa6e230954bd9d08348..bb205328e043dafee5b2daa7d9f5023a576d8e32 100644 --- a/fs/nfsd/flexfilelayoutxdr.c +++ b/fs/nfsd/flexfilelayoutxdr.c @@ -85,6 +85,15 @@ nfsd4_ff_encode_getdeviceinfo(struct xdr_stream *xdr, int addr_len; __be32 *p; + /* + * See paragraph 5 of RFC 8881 S18.40.3. + */ + if (!gdp->gd_maxcount) { + if (xdr_stream_encode_u32(xdr, 0) != XDR_UNIT) + return nfserr_resource; + return nfs_ok; + } + /* len + padding for two strings */ addr_len = 16 + da->netaddr.netid_len + da->netaddr.addr_len; ver_len = 20; diff --git a/fs/nfsd/nfs3xdr.c b/fs/nfsd/nfs3xdr.c index b90bea1c434eb87e73ddfb5b6c7706d489afff74..9f537decdd9c7429abf3dabd53ff20527a8aa72d 100644 --- a/fs/nfsd/nfs3xdr.c +++ b/fs/nfsd/nfs3xdr.c @@ -855,13 +855,11 @@ compose_entry_fh(struct nfsd3_readdirres *cd, struct svc_fh *fhp, } else dchild = dget(dparent); } else - dchild = lookup_one_len_unlocked(name, dparent, namlen); + dchild = lookup_positive_unlocked(name, dparent, namlen); if (IS_ERR(dchild)) return rv; if (d_mountpoint(dchild)) goto out; - if (d_really_is_negative(dchild)) - goto out; if (dchild->d_inode->i_ino != ino) goto out; rv = fh_compose(fhp, exp, dchild, &cd->fh); diff --git a/fs/nfsd/nfs4layouts.c b/fs/nfsd/nfs4layouts.c index f4cf1c0793c6a0be6f558b4419daba1cd7d72509..cf81b5bc3e1566c8744b3da4ad106072b1ce1793 100644 --- a/fs/nfsd/nfs4layouts.c +++ b/fs/nfsd/nfs4layouts.c @@ -322,11 +322,11 @@ nfsd4_recall_file_layout(struct nfs4_layout_stateid *ls) if (ls->ls_recalled) goto out_unlock; - ls->ls_recalled = true; - atomic_inc(&ls->ls_stid.sc_file->fi_lo_recalls); if (list_empty(&ls->ls_layouts)) goto out_unlock; + ls->ls_recalled = true; + atomic_inc(&ls->ls_stid.sc_file->fi_lo_recalls); trace_nfsd_layout_recall(&ls->ls_stid.sc_stateid); refcount_inc(&ls->ls_stid.sc_count); diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c index a696a9b90786575546406c4c20612933e6e69e91..5ec90b252b6a50bb495d3acfb911acf0eabe39bb 100644 --- a/fs/nfsd/nfs4proc.c +++ b/fs/nfsd/nfs4proc.c @@ -870,8 +870,8 @@ nfsd4_rename(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, rename->rn_tname, rename->rn_tnamelen); if (status) return status; - set_change_info(&rename->rn_sinfo, &cstate->current_fh); - set_change_info(&rename->rn_tinfo, &cstate->save_fh); + set_change_info(&rename->rn_sinfo, &cstate->save_fh); + set_change_info(&rename->rn_tinfo, &cstate->current_fh); return nfs_ok; } diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 78191320f8e21223cf1252dec9697129b156b849..e958181b73618a4cbe878841d5c4eafc0f100b3c 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -1019,9 +1019,9 @@ static void revoke_delegation(struct nfs4_delegation *dp) WARN_ON(!list_empty(&dp->dl_recall_lru)); if (clp->cl_minorversion) { + spin_lock(&clp->cl_lock); dp->dl_stid.sc_type = NFS4_REVOKED_DELEG_STID; refcount_inc(&dp->dl_stid.sc_count); - spin_lock(&clp->cl_lock); list_add(&dp->dl_recall_lru, &clp->cl_revoked); spin_unlock(&clp->cl_lock); } @@ -4998,15 +4998,6 @@ static __be32 nfsd4_validate_stateid(struct nfs4_client *cl, stateid_t *stateid) if (ZERO_STATEID(stateid) || ONE_STATEID(stateid) || CLOSE_STATEID(stateid)) return status; - /* Client debugging aid. */ - if (!same_clid(&stateid->si_opaque.so_clid, &cl->cl_clientid)) { - char addr_str[INET6_ADDRSTRLEN]; - rpc_ntop((struct sockaddr *)&cl->cl_addr, addr_str, - sizeof(addr_str)); - pr_warn_ratelimited("NFSD: client %s testing state ID " - "with incorrect client ID\n", addr_str); - return status; - } spin_lock(&cl->cl_lock); s = find_stateid_locked(cl, stateid); if (!s) diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c index c82f898325c1c65f1f5dfe7a761e0685eb36d4a8..33827cdd8066f3033e83c08a16fc64436d0843a6 100644 --- a/fs/nfsd/nfs4xdr.c +++ b/fs/nfsd/nfs4xdr.c @@ -2984,18 +2984,9 @@ nfsd4_encode_dirent_fattr(struct xdr_stream *xdr, struct nfsd4_readdir *cd, __be32 nfserr; int ignore_crossmnt = 0; - dentry = lookup_one_len_unlocked(name, cd->rd_fhp->fh_dentry, namlen); + dentry = lookup_positive_unlocked(name, cd->rd_fhp->fh_dentry, namlen); if (IS_ERR(dentry)) return nfserrno(PTR_ERR(dentry)); - if (d_really_is_negative(dentry)) { - /* - * we're not holding the i_mutex here, so there's - * a window where this directory entry could have gone - * away. - */ - dput(dentry); - return nfserr_noent; - } exp_get(exp); /* @@ -3403,7 +3394,7 @@ nfsd4_encode_open(struct nfsd4_compoundres *resp, __be32 nfserr, struct nfsd4_op p = xdr_reserve_space(xdr, 32); if (!p) return nfserr_resource; - *p++ = cpu_to_be32(0); + *p++ = cpu_to_be32(open->op_recall); /* * TODO: space_limit's in delegations @@ -4135,20 +4126,17 @@ nfsd4_encode_getdeviceinfo(struct nfsd4_compoundres *resp, __be32 nfserr, *p++ = cpu_to_be32(gdev->gd_layout_type); - /* If maxcount is 0 then just update notifications */ - if (gdev->gd_maxcount != 0) { - ops = nfsd4_layout_ops[gdev->gd_layout_type]; - nfserr = ops->encode_getdeviceinfo(xdr, gdev); - if (nfserr) { - /* - * We don't bother to burden the layout drivers with - * enforcing gd_maxcount, just tell the client to - * come back with a bigger buffer if it's not enough. - */ - if (xdr->buf->len + 4 > gdev->gd_maxcount) - goto toosmall; - return nfserr; - } + ops = nfsd4_layout_ops[gdev->gd_layout_type]; + nfserr = ops->encode_getdeviceinfo(xdr, gdev); + if (nfserr) { + /* + * We don't bother to burden the layout drivers with + * enforcing gd_maxcount, just tell the client to + * come back with a bigger buffer if it's not enough. + */ + if (xdr->buf->len + 4 > gdev->gd_maxcount) + goto toosmall; + return nfserr; } if (gdev->gd_notify_types) { diff --git a/fs/nfsd/nfsctl.c b/fs/nfsd/nfsctl.c index ff9899cc9913f36bc831d9fc33620705f871d0bd..7af48d306f20ca5e72050bca76f0bcbff438e7dd 100644 --- a/fs/nfsd/nfsctl.c +++ b/fs/nfsd/nfsctl.c @@ -347,7 +347,7 @@ static ssize_t write_unlock_fs(struct file *file, char *buf, size_t size) static ssize_t write_filehandle(struct file *file, char *buf, size_t size) { char *dname, *path; - int uninitialized_var(maxsize); + int maxsize; char *mesg = buf; int len; struct auth_domain *dom; diff --git a/fs/nfsd/vfs.c b/fs/nfsd/vfs.c index 28e7f86c8c94edbd8679699c6a9fdaa80354e403..a7231d17e35950cda8ed2cc2fb6b4377cc68a914 100644 --- a/fs/nfsd/vfs.c +++ b/fs/nfsd/vfs.c @@ -1691,6 +1691,12 @@ nfsd_rename(struct svc_rqst *rqstp, struct svc_fh *ffhp, char *fname, int flen, if (!flen || isdotent(fname, flen) || !tlen || isdotent(tname, tlen)) goto out; + err = (rqstp->rq_vers == 2) ? nfserr_acces : nfserr_xdev; + if (ffhp->fh_export->ex_path.mnt != tfhp->fh_export->ex_path.mnt) + goto out; + if (ffhp->fh_export->ex_path.dentry != tfhp->fh_export->ex_path.dentry) + goto out; + host_err = fh_want_write(ffhp); if (host_err) { err = nfserrno(host_err); @@ -1724,12 +1730,6 @@ nfsd_rename(struct svc_rqst *rqstp, struct svc_fh *ffhp, char *fname, int flen, if (ndentry == trap) goto out_dput_new; - host_err = -EXDEV; - if (ffhp->fh_export->ex_path.mnt != tfhp->fh_export->ex_path.mnt) - goto out_dput_new; - if (ffhp->fh_export->ex_path.dentry != tfhp->fh_export->ex_path.dentry) - goto out_dput_new; - host_err = vfs_rename(fdir, odentry, tdir, ndentry, NULL, 0); if (!host_err) { host_err = commit_metadata(tfhp); diff --git a/fs/nilfs2/alloc.c b/fs/nilfs2/alloc.c index 235b959fc2b3a706866fd9e96447764641d94536..bbd82f650e93e81741e414e524ac24fea38089ee 100644 --- a/fs/nilfs2/alloc.c +++ b/fs/nilfs2/alloc.c @@ -205,7 +205,8 @@ static int nilfs_palloc_get_block(struct inode *inode, unsigned long blkoff, int ret; spin_lock(lock); - if (prev->bh && blkoff == prev->blkoff) { + if (prev->bh && blkoff == prev->blkoff && + likely(buffer_uptodate(prev->bh))) { get_bh(prev->bh); *bhp = prev->bh; spin_unlock(lock); diff --git a/fs/nilfs2/bmap.c b/fs/nilfs2/bmap.c index fb5a9a8a13cf7d734c0c13f38df097786c5ba5a1..2ba57e4b4f0a6f53bb973361f70156b9aba97cbe 100644 --- a/fs/nilfs2/bmap.c +++ b/fs/nilfs2/bmap.c @@ -67,20 +67,28 @@ int nilfs_bmap_lookup_at_level(struct nilfs_bmap *bmap, __u64 key, int level, down_read(&bmap->b_sem); ret = bmap->b_ops->bop_lookup(bmap, key, level, ptrp); - if (ret < 0) { - ret = nilfs_bmap_convert_error(bmap, __func__, ret); + if (ret < 0) goto out; - } + if (NILFS_BMAP_USE_VBN(bmap)) { ret = nilfs_dat_translate(nilfs_bmap_get_dat(bmap), *ptrp, &blocknr); if (!ret) *ptrp = blocknr; + else if (ret == -ENOENT) { + /* + * If there was no valid entry in DAT for the block + * address obtained by b_ops->bop_lookup, then pass + * internal code -EINVAL to nilfs_bmap_convert_error + * to treat it as metadata corruption. + */ + ret = -EINVAL; + } } out: up_read(&bmap->b_sem); - return ret; + return nilfs_bmap_convert_error(bmap, __func__, ret); } int nilfs_bmap_lookup_contig(struct nilfs_bmap *bmap, __u64 key, __u64 *ptrp, diff --git a/fs/nilfs2/btnode.c b/fs/nilfs2/btnode.c index 138ebbb7a1eefec20313837ff55e69e10b63a088..677ff78d54fba290af9942c19dd08103a8dbadff 100644 --- a/fs/nilfs2/btnode.c +++ b/fs/nilfs2/btnode.c @@ -295,6 +295,14 @@ void nilfs_btnode_abort_change_key(struct address_space *btnc, radix_tree_delete(&btnc->i_pages, newkey); xa_unlock_irq(&btnc->i_pages); unlock_page(ctxt->bh->b_page); - } else - brelse(nbh); + } else { + /* + * When canceling a buffer that a prepare operation has + * allocated to copy a node block to another location, use + * nilfs_btnode_delete() to initialize and release the buffer + * so that the buffer flags will not be in an inconsistent + * state when it is reallocated. + */ + nilfs_btnode_delete(nbh); + } } diff --git a/fs/nilfs2/gcinode.c b/fs/nilfs2/gcinode.c index 114774ac2185ac3455fc06a544623a2786f977f4..cef46650102e755442c886257693ed13f67c588f 100644 --- a/fs/nilfs2/gcinode.c +++ b/fs/nilfs2/gcinode.c @@ -73,10 +73,8 @@ int nilfs_gccache_submit_read_data(struct inode *inode, sector_t blkoff, struct the_nilfs *nilfs = inode->i_sb->s_fs_info; err = nilfs_dat_translate(nilfs->ns_dat, vbn, &pbn); - if (unlikely(err)) { /* -EIO, -ENOMEM, -ENOENT */ - brelse(bh); + if (unlikely(err)) /* -EIO, -ENOMEM, -ENOENT */ goto failed; - } } lock_buffer(bh); @@ -102,6 +100,8 @@ int nilfs_gccache_submit_read_data(struct inode *inode, sector_t blkoff, failed: unlock_page(bh->b_page); put_page(bh->b_page); + if (unlikely(err)) + brelse(bh); return err; } diff --git a/fs/nilfs2/inode.c b/fs/nilfs2/inode.c index cf01aa55dd44ce00eee3d382229a6acceea4259c..ea94dc21af0c95a732abcb512f95f98e5e72badb 100644 --- a/fs/nilfs2/inode.c +++ b/fs/nilfs2/inode.c @@ -930,6 +930,7 @@ void nilfs_evict_inode(struct inode *inode) struct nilfs_transaction_info ti; struct super_block *sb = inode->i_sb; struct nilfs_inode_info *ii = NILFS_I(inode); + struct the_nilfs *nilfs; int ret; if (inode->i_nlink || !ii->i_root || unlikely(is_bad_inode(inode))) { @@ -942,6 +943,23 @@ void nilfs_evict_inode(struct inode *inode) truncate_inode_pages_final(&inode->i_data); + nilfs = sb->s_fs_info; + if (unlikely(sb_rdonly(sb) || !nilfs->ns_writer)) { + /* + * If this inode is about to be disposed after the file system + * has been degraded to read-only due to file system corruption + * or after the writer has been detached, do not make any + * changes that cause writes, just clear it. + * Do this check after read-locking ns_segctor_sem by + * nilfs_transaction_begin() in order to avoid a race with + * the writer detach operation. + */ + clear_inode(inode); + nilfs_clear_inode(inode); + nilfs_transaction_abort(sb); + return; + } + /* TODO: some of the following operations may fail. */ nilfs_truncate_bmap(ii, 0); nilfs_mark_inode_dirty(inode); @@ -1018,7 +1036,7 @@ int nilfs_load_inode_block(struct inode *inode, struct buffer_head **pbh) int err; spin_lock(&nilfs->ns_inode_lock); - if (ii->i_bh == NULL) { + if (ii->i_bh == NULL || unlikely(!buffer_uptodate(ii->i_bh))) { spin_unlock(&nilfs->ns_inode_lock); err = nilfs_ifile_get_inode_block(ii->i_root->ifile, inode->i_ino, pbh); @@ -1027,7 +1045,10 @@ int nilfs_load_inode_block(struct inode *inode, struct buffer_head **pbh) spin_lock(&nilfs->ns_inode_lock); if (ii->i_bh == NULL) ii->i_bh = *pbh; - else { + else if (unlikely(!buffer_uptodate(ii->i_bh))) { + __brelse(ii->i_bh); + ii->i_bh = *pbh; + } else { brelse(*pbh); *pbh = ii->i_bh; } @@ -1094,9 +1115,17 @@ int nilfs_set_file_dirty(struct inode *inode, unsigned int nr_dirty) int __nilfs_mark_inode_dirty(struct inode *inode, int flags) { + struct the_nilfs *nilfs = inode->i_sb->s_fs_info; struct buffer_head *ibh; int err; + /* + * Do not dirty inodes after the log writer has been detached + * and its nilfs_root struct has been freed. + */ + if (unlikely(nilfs_purging(nilfs))) + return 0; + err = nilfs_load_inode_block(inode, &ibh); if (unlikely(err)) { nilfs_msg(inode->i_sb, KERN_WARNING, diff --git a/fs/nilfs2/ioctl.c b/fs/nilfs2/ioctl.c index 708aa1b92036b9d798b1ecccb9f678f633fb1661..dfb2083b8ce1c2b4c75faefaf690cb329f5a5166 100644 --- a/fs/nilfs2/ioctl.c +++ b/fs/nilfs2/ioctl.c @@ -70,7 +70,7 @@ static int nilfs_ioctl_wrap_copy(struct the_nilfs *nilfs, if (argv->v_index > ~(__u64)0 - argv->v_nmembs) return -EINVAL; - buf = (void *)__get_free_pages(GFP_NOFS, 0); + buf = (void *)get_zeroed_page(GFP_NOFS); if (unlikely(!buf)) return -ENOMEM; maxmembs = PAGE_SIZE / argv->v_size; diff --git a/fs/nilfs2/page.c b/fs/nilfs2/page.c index c726b42ca92d17328bb03e096b911785a96da58e..e5fee7fac9154def38065778e2b7f495246a311a 100644 --- a/fs/nilfs2/page.c +++ b/fs/nilfs2/page.c @@ -372,7 +372,15 @@ void nilfs_clear_dirty_pages(struct address_space *mapping, bool silent) struct page *page = pvec.pages[i]; lock_page(page); - nilfs_clear_dirty_page(page, silent); + + /* + * This page may have been removed from the address + * space by truncation or invalidation when the lock + * was acquired. Skip processing in that case. + */ + if (likely(page->mapping == mapping)) + nilfs_clear_dirty_page(page, silent); + unlock_page(page); } pagevec_release(&pvec); diff --git a/fs/nilfs2/segbuf.c b/fs/nilfs2/segbuf.c index 20c479b5e41b8c7a9bbd09d309cf33aa51e3a90d..e72466fc8ca93cf104980703fe98aba672b99934 100644 --- a/fs/nilfs2/segbuf.c +++ b/fs/nilfs2/segbuf.c @@ -101,6 +101,12 @@ int nilfs_segbuf_extend_segsum(struct nilfs_segment_buffer *segbuf) if (unlikely(!bh)) return -ENOMEM; + lock_buffer(bh); + if (!buffer_uptodate(bh)) { + memset(bh->b_data, 0, bh->b_size); + set_buffer_uptodate(bh); + } + unlock_buffer(bh); nilfs_segbuf_add_segsum_buffer(segbuf, bh); return 0; } diff --git a/fs/nilfs2/segment.c b/fs/nilfs2/segment.c index 11914b3585b34f446e09c22e04130668c9ede815..fdcbed6ee83267610739530615169c7c47962c28 100644 --- a/fs/nilfs2/segment.c +++ b/fs/nilfs2/segment.c @@ -435,6 +435,23 @@ static int nilfs_segctor_reset_segment_buffer(struct nilfs_sc_info *sci) return 0; } +/** + * nilfs_segctor_zeropad_segsum - zero pad the rest of the segment summary area + * @sci: segment constructor object + * + * nilfs_segctor_zeropad_segsum() zero-fills unallocated space at the end of + * the current segment summary block. + */ +static void nilfs_segctor_zeropad_segsum(struct nilfs_sc_info *sci) +{ + struct nilfs_segsum_pointer *ssp; + + ssp = sci->sc_blk_cnt > 0 ? &sci->sc_binfo_ptr : &sci->sc_finfo_ptr; + if (ssp->offset < ssp->bh->b_size) + memset(ssp->bh->b_data + ssp->offset, 0, + ssp->bh->b_size - ssp->offset); +} + static int nilfs_segctor_feed_segment(struct nilfs_sc_info *sci) { sci->sc_nblk_this_inc += sci->sc_curseg->sb_sum.nblocks; @@ -443,6 +460,7 @@ static int nilfs_segctor_feed_segment(struct nilfs_sc_info *sci) * The current segment is filled up * (internal code) */ + nilfs_segctor_zeropad_segsum(sci); sci->sc_curseg = NILFS_NEXT_SEGBUF(sci->sc_curseg); return nilfs_segctor_reset_segment_buffer(sci); } @@ -547,6 +565,7 @@ static int nilfs_segctor_add_file_block(struct nilfs_sc_info *sci, goto retry; } if (unlikely(required)) { + nilfs_segctor_zeropad_segsum(sci); err = nilfs_segbuf_extend_segsum(segbuf); if (unlikely(err)) goto failed; @@ -711,6 +730,11 @@ static size_t nilfs_lookup_dirty_data_buffers(struct inode *inode, struct page *page = pvec.pages[i]; lock_page(page); + if (unlikely(page->mapping != mapping)) { + /* Exclude pages removed from the address space */ + unlock_page(page); + continue; + } if (!page_has_buffers(page)) create_empty_buffers(page, i_blocksize(inode), 0); unlock_page(page); @@ -965,10 +989,13 @@ static void nilfs_segctor_fill_in_super_root(struct nilfs_sc_info *sci, unsigned int isz, srsz; bh_sr = NILFS_LAST_SEGBUF(&sci->sc_segbufs)->sb_super_root; + + lock_buffer(bh_sr); raw_sr = (struct nilfs_super_root *)bh_sr->b_data; isz = nilfs->ns_inode_size; srsz = NILFS_SR_BYTES(isz); + raw_sr->sr_sum = 0; /* Ensure initialization within this update */ raw_sr->sr_bytes = cpu_to_le16(srsz); raw_sr->sr_nongc_ctime = cpu_to_le64(nilfs_doing_gc() ? @@ -982,6 +1009,8 @@ static void nilfs_segctor_fill_in_super_root(struct nilfs_sc_info *sci, nilfs_write_inode_common(nilfs->ns_sufile, (void *)raw_sr + NILFS_SR_SUFILE_OFFSET(isz), 1); memset((void *)raw_sr + srsz, 0, nilfs->ns_blocksize - srsz); + set_buffer_uptodate(bh_sr); + unlock_buffer(bh_sr); } static void nilfs_redirty_inodes(struct list_head *head) @@ -1531,6 +1560,7 @@ static int nilfs_segctor_collect(struct nilfs_sc_info *sci, nadd = min_t(int, nadd << 1, SC_MAX_SEGDELTA); sci->sc_stage = prev_stage; } + nilfs_segctor_zeropad_segsum(sci); nilfs_segctor_truncate_segments(sci, sci->sc_curseg, nilfs->ns_sufile); return 0; @@ -1758,6 +1788,7 @@ static void nilfs_abort_logs(struct list_head *logs, int err) list_for_each_entry(segbuf, logs, sb_list) { list_for_each_entry(bh, &segbuf->sb_segsum_buffers, b_assoc_buffers) { + clear_buffer_uptodate(bh); if (bh->b_page != bd_page) { if (bd_page) end_page_writeback(bd_page); @@ -1769,6 +1800,7 @@ static void nilfs_abort_logs(struct list_head *logs, int err) b_assoc_buffers) { clear_buffer_async_write(bh); if (bh == segbuf->sb_super_root) { + clear_buffer_uptodate(bh); if (bh->b_page != bd_page) { end_page_writeback(bd_page); bd_page = bh->b_page; @@ -2019,6 +2051,9 @@ static int nilfs_segctor_do_construct(struct nilfs_sc_info *sci, int mode) struct the_nilfs *nilfs = sci->sc_super->s_fs_info; int err; + if (sb_rdonly(sci->sc_super)) + return -EROFS; + nilfs_sc_cstage_set(sci, NILFS_ST_INIT); sci->sc_cno = nilfs->ns_cno; @@ -2609,11 +2644,10 @@ static int nilfs_segctor_thread(void *arg) goto loop; end_thread: - spin_unlock(&sci->sc_state_lock); - /* end sync. */ sci->sc_task = NULL; wake_up(&sci->sc_wait_task); /* for nilfs_segctor_kill_thread() */ + spin_unlock(&sci->sc_state_lock); return 0; } @@ -2705,7 +2739,7 @@ static void nilfs_segctor_write_out(struct nilfs_sc_info *sci) flush_work(&sci->sc_iput_work); - } while (ret && retrycount-- > 0); + } while (ret && ret != -EROFS && retrycount-- > 0); } /** @@ -2816,6 +2850,7 @@ void nilfs_detach_log_writer(struct super_block *sb) nilfs_segctor_destroy(nilfs->ns_writer); nilfs->ns_writer = NULL; } + set_nilfs_purging(nilfs); /* Force to free the list of dirty files */ spin_lock(&nilfs->ns_inode_lock); @@ -2828,4 +2863,5 @@ void nilfs_detach_log_writer(struct super_block *sb) up_write(&nilfs->ns_segctor_sem); nilfs_dispose_list(nilfs, &garbage_list, 1); + clear_nilfs_purging(nilfs); } diff --git a/fs/nilfs2/sufile.c b/fs/nilfs2/sufile.c index 150845a432259ae79e681471cc206df8ecc8f329..d85d3c758d7b9e05a420a5b975f2aaa068b11653 100644 --- a/fs/nilfs2/sufile.c +++ b/fs/nilfs2/sufile.c @@ -782,6 +782,15 @@ int nilfs_sufile_resize(struct inode *sufile, __u64 newnsegs) goto out_header; sui->ncleansegs -= nsegs - newnsegs; + + /* + * If the sufile is successfully truncated, immediately adjust + * the segment allocation space while locking the semaphore + * "mi_sem" so that nilfs_sufile_alloc() never allocates + * segments in the truncated space. + */ + sui->allocmax = newnsegs - 1; + sui->allocmin = 0; } kaddr = kmap_atomic(header_bh->b_page); diff --git a/fs/nilfs2/super.c b/fs/nilfs2/super.c index 2961b5ceb4a7c39ddee70214e12b7998f56443a8..99bcb4ab47a6153b9742363562175e0cfd7c5e90 100644 --- a/fs/nilfs2/super.c +++ b/fs/nilfs2/super.c @@ -374,10 +374,31 @@ static int nilfs_move_2nd_super(struct super_block *sb, loff_t sb2off) goto out; } nsbp = (void *)nsbh->b_data + offset; - memset(nsbp, 0, nilfs->ns_blocksize); + lock_buffer(nsbh); if (sb2i >= 0) { + /* + * The position of the second superblock only changes by 4KiB, + * which is larger than the maximum superblock data size + * (= 1KiB), so there is no need to use memmove() to allow + * overlap between source and destination. + */ memcpy(nsbp, nilfs->ns_sbp[sb2i], nilfs->ns_sbsize); + + /* + * Zero fill after copy to avoid overwriting in case of move + * within the same block. + */ + memset(nsbh->b_data, 0, offset); + memset((void *)nsbp + nilfs->ns_sbsize, 0, + nsbh->b_size - offset - nilfs->ns_sbsize); + } else { + memset(nsbh->b_data, 0, nsbh->b_size); + } + set_buffer_uptodate(nsbh); + unlock_buffer(nsbh); + + if (sb2i >= 0) { brelse(nilfs->ns_sbh[sb2i]); nilfs->ns_sbh[sb2i] = nsbh; nilfs->ns_sbp[sb2i] = nsbp; @@ -484,6 +505,7 @@ static void nilfs_put_super(struct super_block *sb) up_write(&nilfs->ns_sem); } + nilfs_sysfs_delete_device_group(nilfs); iput(nilfs->ns_sufile); iput(nilfs->ns_cpfile); iput(nilfs->ns_dat); @@ -1110,6 +1132,7 @@ nilfs_fill_super(struct super_block *sb, void *data, int silent) nilfs_put_root(fsroot); failed_unload: + nilfs_sysfs_delete_device_group(nilfs); iput(nilfs->ns_sufile); iput(nilfs->ns_cpfile); iput(nilfs->ns_dat); diff --git a/fs/nilfs2/the_nilfs.c b/fs/nilfs2/the_nilfs.c index 6541e29a8b2006edafc850a0fe1484458ed70ebe..d550a564645e2396f4ce5a85eb203406e8c7bc7a 100644 --- a/fs/nilfs2/the_nilfs.c +++ b/fs/nilfs2/the_nilfs.c @@ -87,7 +87,6 @@ void destroy_nilfs(struct the_nilfs *nilfs) { might_sleep(); if (nilfs_init(nilfs)) { - nilfs_sysfs_delete_device_group(nilfs); brelse(nilfs->ns_sbh[0]); brelse(nilfs->ns_sbh[1]); } @@ -275,6 +274,10 @@ int load_nilfs(struct the_nilfs *nilfs, struct super_block *sb) goto failed; } + err = nilfs_sysfs_create_device_group(sb); + if (unlikely(err)) + goto sysfs_error; + if (valid_fs) goto skip_recovery; @@ -336,6 +339,9 @@ int load_nilfs(struct the_nilfs *nilfs, struct super_block *sb) goto failed; failed_unload: + nilfs_sysfs_delete_device_group(nilfs); + + sysfs_error: iput(nilfs->ns_cpfile); iput(nilfs->ns_sufile); iput(nilfs->ns_dat); @@ -369,6 +375,18 @@ unsigned long nilfs_nrsvsegs(struct the_nilfs *nilfs, unsigned long nsegs) 100)); } +/** + * nilfs_max_segment_count - calculate the maximum number of segments + * @nilfs: nilfs object + */ +static u64 nilfs_max_segment_count(struct the_nilfs *nilfs) +{ + u64 max_count = U64_MAX; + + do_div(max_count, nilfs->ns_blocks_per_segment); + return min_t(u64, max_count, ULONG_MAX); +} + void nilfs_set_nsegments(struct the_nilfs *nilfs, unsigned long nsegs) { nilfs->ns_nsegments = nsegs; @@ -378,6 +396,8 @@ void nilfs_set_nsegments(struct the_nilfs *nilfs, unsigned long nsegs) static int nilfs_store_disk_layout(struct the_nilfs *nilfs, struct nilfs_super_block *sbp) { + u64 nsegments, nblocks; + if (le32_to_cpu(sbp->s_rev_level) < NILFS_MIN_SUPP_REV) { nilfs_msg(nilfs->ns_sb, KERN_ERR, "unsupported revision (superblock rev.=%d.%d, current rev.=%d.%d). Please check the version of mkfs.nilfs(2).", @@ -424,7 +444,35 @@ static int nilfs_store_disk_layout(struct the_nilfs *nilfs, return -EINVAL; } - nilfs_set_nsegments(nilfs, le64_to_cpu(sbp->s_nsegments)); + nsegments = le64_to_cpu(sbp->s_nsegments); + if (nsegments > nilfs_max_segment_count(nilfs)) { + nilfs_msg(nilfs->ns_sb, KERN_ERR, + "segment count %llu exceeds upper limit (%llu segments)", + (unsigned long long)nsegments, + (unsigned long long)nilfs_max_segment_count(nilfs)); + return -EINVAL; + } + + nblocks = (u64)i_size_read(nilfs->ns_sb->s_bdev->bd_inode) >> + nilfs->ns_sb->s_blocksize_bits; + if (nblocks) { + u64 min_block_count = nsegments * nilfs->ns_blocks_per_segment; + /* + * To avoid failing to mount early device images without a + * second superblock, exclude that block count from the + * "min_block_count" calculation. + */ + + if (nblocks < min_block_count) { + nilfs_msg(nilfs->ns_sb, KERN_ERR, + "total number of segment blocks %llu exceeds device size (%llu blocks)", + (unsigned long long)min_block_count, + (unsigned long long)nblocks); + return -EINVAL; + } + } + + nilfs_set_nsegments(nilfs, nsegments); nilfs->ns_crc_seed = le32_to_cpu(sbp->s_crc_seed); return 0; } @@ -668,10 +716,6 @@ int init_nilfs(struct the_nilfs *nilfs, struct super_block *sb, char *data) if (err) goto failed_sbh; - err = nilfs_sysfs_create_device_group(sb); - if (err) - goto failed_sbh; - set_nilfs_init(nilfs); err = 0; out: diff --git a/fs/nilfs2/the_nilfs.h b/fs/nilfs2/the_nilfs.h index 380a543c5b19bd424782e8393ecc285af648396e..de6e24d80eb6528d439ff0ec7c0393da51801de7 100644 --- a/fs/nilfs2/the_nilfs.h +++ b/fs/nilfs2/the_nilfs.h @@ -29,6 +29,7 @@ enum { THE_NILFS_DISCONTINUED, /* 'next' pointer chain has broken */ THE_NILFS_GC_RUNNING, /* gc process is running */ THE_NILFS_SB_DIRTY, /* super block is dirty */ + THE_NILFS_PURGING, /* disposing dirty files for cleanup */ }; /** @@ -208,6 +209,7 @@ THE_NILFS_FNS(INIT, init) THE_NILFS_FNS(DISCONTINUED, discontinued) THE_NILFS_FNS(GC_RUNNING, gc_running) THE_NILFS_FNS(SB_DIRTY, sb_dirty) +THE_NILFS_FNS(PURGING, purging) /* * Mount option operations diff --git a/fs/nls/nls_base.c b/fs/nls/nls_base.c index 52ccd34b1e792370597b77f7d228c4d79bf96600..a026dbd3593f68febd24a08bc8de9340ea4959c8 100644 --- a/fs/nls/nls_base.c +++ b/fs/nls/nls_base.c @@ -272,7 +272,7 @@ int unregister_nls(struct nls_table * nls) return -EINVAL; } -static struct nls_table *find_nls(char *charset) +static struct nls_table *find_nls(const char *charset) { struct nls_table *nls; spin_lock(&nls_lock); @@ -288,7 +288,7 @@ static struct nls_table *find_nls(char *charset) return nls; } -struct nls_table *load_nls(char *charset) +struct nls_table *load_nls(const char *charset) { return try_then_request_module(find_nls(charset), "nls_%s", charset); } diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 046f5e3c9622ddf39a47a1845bb1f5235299c2db..c7cf0913229cbd21399f46dc430e019ac4f9c2f8 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -4722,7 +4722,7 @@ int ocfs2_insert_extent(handle_t *handle, struct ocfs2_alloc_context *meta_ac) { int status; - int uninitialized_var(free_records); + int free_records; struct buffer_head *last_eb_bh = NULL; struct ocfs2_insert_type insert = {0, }; struct ocfs2_extent_rec rec; @@ -7052,7 +7052,7 @@ int ocfs2_convert_inline_data_to_extents(struct inode *inode, int need_free = 0; u32 bit_off, num; handle_t *handle; - u64 uninitialized_var(block); + u64 block; struct ocfs2_inode_info *oi = OCFS2_I(inode); struct ocfs2_super *osb = OCFS2_SB(inode->i_sb); struct ocfs2_dinode *di = (struct ocfs2_dinode *)di_bh->b_data; diff --git a/fs/ocfs2/aops.c b/fs/ocfs2/aops.c index b6948813eb063896256e2640d61b2dc89e4cdae6..1353db3f7f48a13944e9a503483daae161e7bcd5 100644 --- a/fs/ocfs2/aops.c +++ b/fs/ocfs2/aops.c @@ -2003,11 +2003,25 @@ int ocfs2_write_end_nolock(struct address_space *mapping, } if (unlikely(copied < len) && wc->w_target_page) { + loff_t new_isize; + if (!PageUptodate(wc->w_target_page)) copied = 0; - ocfs2_zero_new_buffers(wc->w_target_page, start+copied, - start+len); + new_isize = max_t(loff_t, i_size_read(inode), pos + copied); + if (new_isize > page_offset(wc->w_target_page)) + ocfs2_zero_new_buffers(wc->w_target_page, start+copied, + start+len); + else { + /* + * When page is fully beyond new isize (data copy + * failed), do not bother zeroing the page. Invalidate + * it instead so that writeback does not get confused + * put page & buffer dirty bits into inconsistent + * state. + */ + block_invalidatepage(wc->w_target_page, 0, PAGE_SIZE); + } } if (wc->w_target_page) flush_dcache_page(wc->w_target_page); diff --git a/fs/ocfs2/dir.c b/fs/ocfs2/dir.c index c121abbdfc7dbcfb28675aa7e62a4cb9a70633a1..13f4bb4e174c4388f9fdf6167422caf9c60a8587 100644 --- a/fs/ocfs2/dir.c +++ b/fs/ocfs2/dir.c @@ -866,9 +866,9 @@ static int ocfs2_dx_dir_lookup(struct inode *inode, u64 *ret_phys_blkno) { int ret = 0; - unsigned int cend, uninitialized_var(clen); - u32 uninitialized_var(cpos); - u64 uninitialized_var(blkno); + unsigned int cend, clen; + u32 cpos; + u64 blkno; u32 name_hash = hinfo->major_hash; ret = ocfs2_dx_dir_lookup_rec(inode, el, name_hash, &cpos, &blkno, @@ -912,7 +912,7 @@ static int ocfs2_dx_dir_search(const char *name, int namelen, struct ocfs2_dir_lookup_result *res) { int ret, i, found; - u64 uninitialized_var(phys); + u64 phys; struct buffer_head *dx_leaf_bh = NULL; struct ocfs2_dx_leaf *dx_leaf; struct ocfs2_dx_entry *dx_entry = NULL; @@ -4420,9 +4420,9 @@ static int ocfs2_dx_dir_remove_index(struct inode *dir, int ocfs2_dx_dir_truncate(struct inode *dir, struct buffer_head *di_bh) { int ret; - unsigned int uninitialized_var(clen); - u32 major_hash = UINT_MAX, p_cpos, uninitialized_var(cpos); - u64 uninitialized_var(blkno); + unsigned int clen; + u32 major_hash = UINT_MAX, p_cpos, cpos; + u64 blkno; struct ocfs2_super *osb = OCFS2_SB(dir->i_sb); struct buffer_head *dx_root_bh = NULL; struct ocfs2_dx_root_block *dx_root; diff --git a/fs/ocfs2/dlm/dlmcommon.h b/fs/ocfs2/dlm/dlmcommon.h index d06e27ec4be475d7a382cbf1dbb7985fe63eef52..fb181f6d6c0645a50c206ecf33567927dc43ff6f 100644 --- a/fs/ocfs2/dlm/dlmcommon.h +++ b/fs/ocfs2/dlm/dlmcommon.h @@ -704,10 +704,6 @@ struct dlm_begin_reco __be32 pad2; }; - -#define BITS_PER_BYTE 8 -#define BITS_TO_BYTES(bits) (((bits)+BITS_PER_BYTE-1)/BITS_PER_BYTE) - struct dlm_query_join_request { u8 node_idx; diff --git a/fs/ocfs2/extent_map.c b/fs/ocfs2/extent_map.c index 06cb96462bf99a92172da155fe11933f76b22584..1f41171c14687c425eda3a4a3451112d42fd94e5 100644 --- a/fs/ocfs2/extent_map.c +++ b/fs/ocfs2/extent_map.c @@ -416,7 +416,7 @@ static int ocfs2_get_clusters_nocache(struct inode *inode, { int i, ret, tree_height, len; struct ocfs2_dinode *di; - struct ocfs2_extent_block *uninitialized_var(eb); + struct ocfs2_extent_block *eb; struct ocfs2_extent_list *el; struct ocfs2_extent_rec *rec; struct buffer_head *eb_bh = NULL; @@ -613,7 +613,7 @@ int ocfs2_get_clusters(struct inode *inode, u32 v_cluster, unsigned int *extent_flags) { int ret; - unsigned int uninitialized_var(hole_len), flags = 0; + unsigned int hole_len, flags = 0; struct buffer_head *di_bh = NULL; struct ocfs2_extent_rec rec; diff --git a/fs/ocfs2/file.c b/fs/ocfs2/file.c index 0141298bb2e5fb6f90c968eefcdb6d332dde2aa0..c1780b14d23db8b6760c5c1e9f54719014ae7a6a 100644 --- a/fs/ocfs2/file.c +++ b/fs/ocfs2/file.c @@ -2111,14 +2111,20 @@ static long ocfs2_fallocate(struct file *file, int mode, loff_t offset, struct ocfs2_space_resv sr; int change_size = 1; int cmd = OCFS2_IOC_RESVSP64; + int ret = 0; if (mode & ~(FALLOC_FL_KEEP_SIZE | FALLOC_FL_PUNCH_HOLE)) return -EOPNOTSUPP; if (!ocfs2_writes_unwritten_extents(osb)) return -EOPNOTSUPP; - if (mode & FALLOC_FL_KEEP_SIZE) + if (mode & FALLOC_FL_KEEP_SIZE) { change_size = 0; + } else { + ret = inode_newsize_ok(inode, offset + len); + if (ret) + return ret; + } if (mode & FALLOC_FL_PUNCH_HOLE) cmd = OCFS2_IOC_UNRESVSP64; diff --git a/fs/ocfs2/move_extents.c b/fs/ocfs2/move_extents.c index 1565dd8e8856ee62d68e4fa63df6e8cc5b79d48c..fbbc30f201731ad35f2bb13a602149ddc9a23b30 100644 --- a/fs/ocfs2/move_extents.c +++ b/fs/ocfs2/move_extents.c @@ -115,14 +115,6 @@ static int __ocfs2_move_extent(handle_t *handle, */ replace_rec.e_flags = ext_flags & ~OCFS2_EXT_REFCOUNTED; - ret = ocfs2_journal_access_di(handle, INODE_CACHE(inode), - context->et.et_root_bh, - OCFS2_JOURNAL_ACCESS_WRITE); - if (ret) { - mlog_errno(ret); - goto out; - } - ret = ocfs2_split_extent(handle, &context->et, path, index, &replace_rec, context->meta_ac, &context->dealloc); @@ -131,8 +123,6 @@ static int __ocfs2_move_extent(handle_t *handle, goto out; } - ocfs2_journal_dirty(handle, context->et.et_root_bh); - context->new_phys_cpos = new_p_cpos; /* @@ -454,7 +444,7 @@ static int ocfs2_find_victim_alloc_group(struct inode *inode, bg = (struct ocfs2_group_desc *)gd_bh->b_data; if (vict_blkno < (le64_to_cpu(bg->bg_blkno) + - le16_to_cpu(bg->bg_bits))) { + (le16_to_cpu(bg->bg_bits) << bits_per_unit))) { *ret_bh = gd_bh; *vict_bit = (vict_blkno - blkno) >> @@ -569,6 +559,7 @@ static void ocfs2_probe_alloc_group(struct inode *inode, struct buffer_head *bh, last_free_bits++; if (last_free_bits == move_len) { + i -= move_len; *goal_bit = i; *phys_cpos = base_cpos + i; break; @@ -1040,18 +1031,19 @@ int ocfs2_ioctl_move_extents(struct file *filp, void __user *argp) context->range = ⦥ + /* + * ok, the default theshold for the defragmentation + * is 1M, since our maximum clustersize was 1M also. + * any thought? + */ + if (!range.me_threshold) + range.me_threshold = 1024 * 1024; + + if (range.me_threshold > i_size_read(inode)) + range.me_threshold = i_size_read(inode); + if (range.me_flags & OCFS2_MOVE_EXT_FL_AUTO_DEFRAG) { context->auto_defrag = 1; - /* - * ok, the default theshold for the defragmentation - * is 1M, since our maximum clustersize was 1M also. - * any thought? - */ - if (!range.me_threshold) - range.me_threshold = 1024 * 1024; - - if (range.me_threshold > i_size_read(inode)) - range.me_threshold = i_size_read(inode); if (range.me_flags & OCFS2_MOVE_EXT_FL_PART_DEFRAG) context->partial = 1; diff --git a/fs/ocfs2/namei.c b/fs/ocfs2/namei.c index d437b219252282d43bb7603eeb7677219ed11856..bb8483510327f57fd3d7a78764f95f4f73b15a56 100644 --- a/fs/ocfs2/namei.c +++ b/fs/ocfs2/namei.c @@ -1538,6 +1538,10 @@ static int ocfs2_rename(struct inode *old_dir, status = ocfs2_add_entry(handle, new_dentry, old_inode, OCFS2_I(old_inode)->ip_blkno, new_dir_bh, &target_insert); + if (status < 0) { + mlog_errno(status); + goto bail; + } } old_inode->i_ctime = current_time(old_inode); @@ -2506,7 +2510,7 @@ int ocfs2_create_inode_in_orphan(struct inode *dir, struct buffer_head *new_di_bh = NULL; struct ocfs2_alloc_context *inode_ac = NULL; struct ocfs2_dir_lookup_result orphan_insert = { NULL, }; - u64 uninitialized_var(di_blkno), suballoc_loc; + u64 di_blkno, suballoc_loc; u16 suballoc_bit; status = ocfs2_inode_lock(dir, &parent_di_bh, 1); diff --git a/fs/ocfs2/refcounttree.c b/fs/ocfs2/refcounttree.c index fc197e599e8ce4a1ad56607e4950effd23777124..e184b36f8dd33a78571a5d8397a921ec2a0c37de 100644 --- a/fs/ocfs2/refcounttree.c +++ b/fs/ocfs2/refcounttree.c @@ -1069,7 +1069,7 @@ static int ocfs2_get_refcount_rec(struct ocfs2_caching_info *ci, struct buffer_head **ret_bh) { int ret = 0, i, found; - u32 low_cpos, uninitialized_var(cpos_end); + u32 low_cpos, cpos_end; struct ocfs2_extent_list *el; struct ocfs2_extent_rec *rec = NULL; struct ocfs2_extent_block *eb = NULL; diff --git a/fs/ocfs2/super.c b/fs/ocfs2/super.c index 7a08053d95c219d7938f8f992bb3ee825789d65b..4fd99ef7f33420a34c91441a58e81835eba0a540 100644 --- a/fs/ocfs2/super.c +++ b/fs/ocfs2/super.c @@ -985,8 +985,10 @@ static void ocfs2_disable_quotas(struct ocfs2_super *osb) for (type = 0; type < OCFS2_MAXQUOTAS; type++) { if (!sb_has_quota_loaded(sb, type)) continue; - oinfo = sb_dqinfo(sb, type)->dqi_priv; - cancel_delayed_work_sync(&oinfo->dqi_sync_work); + if (!sb_has_quota_suspended(sb, type)) { + oinfo = sb_dqinfo(sb, type)->dqi_priv; + cancel_delayed_work_sync(&oinfo->dqi_sync_work); + } inode = igrab(sb->s_dquot.files[type]); /* Turn off quotas. This will remove all dquot structures from * memory and so they will be automatically synced to global diff --git a/fs/ocfs2/xattr.c b/fs/ocfs2/xattr.c index c146e12a8601fe0b11e1478997a04dc8c5708781..54d881c9ac81efbef81da06b7776367258ecdb22 100644 --- a/fs/ocfs2/xattr.c +++ b/fs/ocfs2/xattr.c @@ -1219,7 +1219,7 @@ static int ocfs2_xattr_block_get(struct inode *inode, struct ocfs2_xattr_value_root *xv; size_t size; int ret = -ENODATA, name_offset, name_len, i; - int uninitialized_var(block_off); + int block_off; xs->bucket = ocfs2_xattr_bucket_new(inode); if (!xs->bucket) { diff --git a/fs/omfs/file.c b/fs/omfs/file.c index bf83e6644333f5edb4c7dfb6a4ad68415ad7e6ea..ce59b2fb50c74656fbc89611c67967deb70af540 100644 --- a/fs/omfs/file.c +++ b/fs/omfs/file.c @@ -220,7 +220,7 @@ static int omfs_get_block(struct inode *inode, sector_t block, struct buffer_head *bh; sector_t next, offset; int ret; - u64 uninitialized_var(new_block); + u64 new_block; u32 max_extents; int extent_count; struct omfs_extent *oe; diff --git a/fs/overlayfs/copy_up.c b/fs/overlayfs/copy_up.c index fb70ec3b254abc586d9d8b19350b8ba8324c86ed..bda5d2015a59991cf07fe07b30d531abd6017146 100644 --- a/fs/overlayfs/copy_up.c +++ b/fs/overlayfs/copy_up.c @@ -195,7 +195,7 @@ static int ovl_set_timestamps(struct dentry *upperdentry, struct kstat *stat) { struct iattr attr = { .ia_valid = - ATTR_ATIME | ATTR_MTIME | ATTR_ATIME_SET | ATTR_MTIME_SET, + ATTR_ATIME | ATTR_MTIME | ATTR_ATIME_SET | ATTR_MTIME_SET | ATTR_CTIME, .ia_atime = stat->atime, .ia_mtime = stat->mtime, }; @@ -713,7 +713,7 @@ static int ovl_copy_up_meta_inode_data(struct ovl_copy_up_ctx *c) struct path upperpath, datapath; int err; char *capability = NULL; - ssize_t uninitialized_var(cap_size); + ssize_t cap_size; ovl_path_upper(c->dentry, &upperpath); if (WARN_ON(upperpath.dentry == NULL)) diff --git a/fs/overlayfs/namei.c b/fs/overlayfs/namei.c index 499cd1f4fa85ee27df2861e98f2715eab0c28374..739033b98f3a812e33bee404fba568f34938fc81 100644 --- a/fs/overlayfs/namei.c +++ b/fs/overlayfs/namei.c @@ -205,7 +205,7 @@ static int ovl_lookup_single(struct dentry *base, struct ovl_lookup_data *d, int err; bool last_element = !post[0]; - this = lookup_one_len_unlocked(name, base, namelen); + this = lookup_positive_unlocked(name, base, namelen); if (IS_ERR(this)) { err = PTR_ERR(this); this = NULL; @@ -213,8 +213,6 @@ static int ovl_lookup_single(struct dentry *base, struct ovl_lookup_data *d, goto out; goto out_err; } - if (!this->d_inode) - goto put_and_out; if (ovl_dentry_weird(this)) { /* Don't support traversing automounts and other weirdness */ @@ -656,7 +654,7 @@ struct dentry *ovl_get_index_fh(struct ovl_fs *ofs, struct ovl_fh *fh) if (err) return ERR_PTR(err); - index = lookup_one_len_unlocked(name.name, ofs->indexdir, name.len); + index = lookup_positive_unlocked(name.name, ofs->indexdir, name.len); kfree(name.name); if (IS_ERR(index)) { if (PTR_ERR(index) == -ENOENT) @@ -664,9 +662,7 @@ struct dentry *ovl_get_index_fh(struct ovl_fs *ofs, struct ovl_fh *fh) return index; } - if (d_is_negative(index)) - err = 0; - else if (ovl_is_whiteout(index)) + if (ovl_is_whiteout(index)) err = -ESTALE; else if (ovl_dentry_weird(index)) err = -EIO; @@ -690,7 +686,7 @@ struct dentry *ovl_lookup_index(struct ovl_fs *ofs, struct dentry *upper, if (err) return ERR_PTR(err); - index = lookup_one_len_unlocked(name.name, ofs->indexdir, name.len); + index = lookup_positive_unlocked(name.name, ofs->indexdir, name.len); if (IS_ERR(index)) { err = PTR_ERR(index); if (err == -ENOENT) { @@ -705,9 +701,7 @@ struct dentry *ovl_lookup_index(struct ovl_fs *ofs, struct dentry *upper, } inode = d_inode(index); - if (d_is_negative(index)) { - goto out_dput; - } else if (ovl_is_whiteout(index) && !verify) { + if (ovl_is_whiteout(index) && !verify) { /* * When index lookup is called with !verify for decoding an * overlay file handle, a whiteout index implies that decode @@ -1136,7 +1130,7 @@ bool ovl_lower_positive(struct dentry *dentry) struct dentry *this; struct dentry *lowerdir = poe->lowerstack[i].dentry; - this = lookup_one_len_unlocked(name->name, lowerdir, + this = lookup_positive_unlocked(name->name, lowerdir, name->len); if (IS_ERR(this)) { switch (PTR_ERR(this)) { @@ -1153,10 +1147,8 @@ bool ovl_lower_positive(struct dentry *dentry) break; } } else { - if (this->d_inode) { - positive = !ovl_is_whiteout(this); - done = true; - } + positive = !ovl_is_whiteout(this); + done = true; dput(this); } } diff --git a/fs/proc/base.c b/fs/proc/base.c index 908d2366be751f2862e23b1b31e28b5e182c08fa..5c8ccae1f165f3d0a7aa29ae279af7bd9e686082 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -3982,7 +3982,8 @@ static int proc_tid_comm_permission(struct inode *inode, int mask) } static const struct inode_operations proc_tid_comm_inode_operations = { - .permission = proc_tid_comm_permission, + .setattr = proc_setattr, + .permission = proc_tid_comm_permission, }; /* diff --git a/fs/pstore/pmsg.c b/fs/pstore/pmsg.c index ffc13ea196d2ac295b9f271886d20af1c7935033..24db02de1787453d4ad838443dd39e4a7e948484 100644 --- a/fs/pstore/pmsg.c +++ b/fs/pstore/pmsg.c @@ -15,10 +15,9 @@ #include #include #include -#include #include "internal.h" -static DEFINE_RT_MUTEX(pmsg_lock); +static DEFINE_MUTEX(pmsg_lock); static ssize_t write_pmsg(struct file *file, const char __user *buf, size_t count, loff_t *ppos) @@ -37,9 +36,9 @@ static ssize_t write_pmsg(struct file *file, const char __user *buf, if (!access_ok(VERIFY_READ, buf, count)) return -EFAULT; - rt_mutex_lock(&pmsg_lock); + mutex_lock(&pmsg_lock); ret = psinfo->write_user(&record, buf); - rt_mutex_unlock(&pmsg_lock); + mutex_unlock(&pmsg_lock); return ret ? ret : count; } diff --git a/fs/pstore/ram_core.c b/fs/pstore/ram_core.c index 60dff7180412090387b5d9698058d864b8648c9f..efb765b8466f8d260b63d38beeed1c6ff176ccd7 100644 --- a/fs/pstore/ram_core.c +++ b/fs/pstore/ram_core.c @@ -500,7 +500,7 @@ static int persistent_ram_post_init(struct persistent_ram_zone *prz, u32 sig, sig ^= PERSISTENT_RAM_SIG; if (prz->buffer->sig == sig) { - if (buffer_size(prz) == 0) { + if (buffer_size(prz) == 0 && buffer_start(prz) == 0) { pr_debug("found existing empty buffer\n"); return 0; } diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index 770a2b14348561d61c4fc087943dd0883fb8a91c..868936076f41deb999f8d6889ecb1c822dd70aea 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -223,18 +223,31 @@ static void put_quota_format(struct quota_format_type *fmt) /* * Dquot List Management: - * The quota code uses three lists for dquot management: the inuse_list, - * free_dquots, and dquot_hash[] array. A single dquot structure may be - * on all three lists, depending on its current state. + * The quota code uses five lists for dquot management: the inuse_list, + * releasing_dquots, free_dquots, dqi_dirty_list, and dquot_hash[] array. + * A single dquot structure may be on some of those lists, depending on + * its current state. * * All dquots are placed to the end of inuse_list when first created, and this * list is used for invalidate operation, which must look at every dquot. * - * Unused dquots (dq_count == 0) are added to the free_dquots list when freed, - * and this list is searched whenever we need an available dquot. Dquots are - * removed from the list as soon as they are used again, and - * dqstats.free_dquots gives the number of dquots on the list. When - * dquot is invalidated it's completely released from memory. + * When the last reference of a dquot is dropped, the dquot is added to + * releasing_dquots. We'll then queue work item which will call + * synchronize_srcu() and after that perform the final cleanup of all the + * dquots on the list. Each cleaned up dquot is moved to free_dquots list. + * Both releasing_dquots and free_dquots use the dq_free list_head in the dquot + * struct. + * + * Unused and cleaned up dquots are in the free_dquots list and this list is + * searched whenever we need an available dquot. Dquots are removed from the + * list as soon as they are used again and dqstats.free_dquots gives the number + * of dquots on the list. When dquot is invalidated it's completely released + * from memory. + * + * Dirty dquots are added to the dqi_dirty_list of quota_info when mark + * dirtied, and this list is searched when writing dirty dquots back to + * quota file. Note that some filesystems do dirty dquot tracking on their + * own (e.g. in a journal) and thus don't use dqi_dirty_list. * * Dquots with a specific identity (device, type and id) are placed on * one of the dquot_hash[] hash chains. The provides an efficient search @@ -243,6 +256,7 @@ static void put_quota_format(struct quota_format_type *fmt) static LIST_HEAD(inuse_list); static LIST_HEAD(free_dquots); +static LIST_HEAD(releasing_dquots); static unsigned int dq_hash_bits, dq_hash_mask; static struct hlist_head *dquot_hash; @@ -253,6 +267,9 @@ static qsize_t inode_get_rsv_space(struct inode *inode); static qsize_t __inode_get_rsv_space(struct inode *inode); static int __dquot_initialize(struct inode *inode, int type); +static void quota_release_workfn(struct work_struct *work); +static DECLARE_DELAYED_WORK(quota_release_work, quota_release_workfn); + static inline unsigned int hashfn(const struct super_block *sb, struct kqid qid) { @@ -300,12 +317,21 @@ static inline void put_dquot_last(struct dquot *dquot) dqstats_inc(DQST_FREE_DQUOTS); } +static inline void put_releasing_dquots(struct dquot *dquot) +{ + list_add_tail(&dquot->dq_free, &releasing_dquots); + set_bit(DQ_RELEASING_B, &dquot->dq_flags); +} + static inline void remove_free_dquot(struct dquot *dquot) { if (list_empty(&dquot->dq_free)) return; list_del_init(&dquot->dq_free); - dqstats_dec(DQST_FREE_DQUOTS); + if (!test_bit(DQ_RELEASING_B, &dquot->dq_flags)) + dqstats_dec(DQST_FREE_DQUOTS); + else + clear_bit(DQ_RELEASING_B, &dquot->dq_flags); } static inline void put_inuse(struct dquot *dquot) @@ -331,6 +357,11 @@ static void wait_on_dquot(struct dquot *dquot) mutex_unlock(&dquot->dq_lock); } +static inline int dquot_active(struct dquot *dquot) +{ + return test_bit(DQ_ACTIVE_B, &dquot->dq_flags); +} + static inline int dquot_dirty(struct dquot *dquot) { return test_bit(DQ_MOD_B, &dquot->dq_flags); @@ -346,14 +377,14 @@ int dquot_mark_dquot_dirty(struct dquot *dquot) { int ret = 1; - if (!test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) + if (!dquot_active(dquot)) return 0; if (sb_dqopt(dquot->dq_sb)->flags & DQUOT_NOLIST_DIRTY) return test_and_set_bit(DQ_MOD_B, &dquot->dq_flags); /* If quota is dirty already, we don't have to acquire dq_list_lock */ - if (test_bit(DQ_MOD_B, &dquot->dq_flags)) + if (dquot_dirty(dquot)) return 1; spin_lock(&dq_list_lock); @@ -432,7 +463,7 @@ int dquot_acquire(struct dquot *dquot) smp_mb__before_atomic(); set_bit(DQ_READ_B, &dquot->dq_flags); /* Instantiate dquot if needed */ - if (!test_bit(DQ_ACTIVE_B, &dquot->dq_flags) && !dquot->dq_off) { + if (!dquot_active(dquot) && !dquot->dq_off) { ret = dqopt->ops[dquot->dq_id.type]->commit_dqblk(dquot); /* Write the info if needed */ if (info_dirty(&dqopt->info[dquot->dq_id.type])) { @@ -471,7 +502,7 @@ int dquot_commit(struct dquot *dquot) goto out_lock; /* Inactive dquot can be only if there was error during read/init * => we have better not writing it */ - if (test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) + if (dquot_active(dquot)) ret = dqopt->ops[dquot->dq_id.type]->commit_dqblk(dquot); else ret = -EIO; @@ -532,6 +563,8 @@ static void invalidate_dquots(struct super_block *sb, int type) struct dquot *dquot, *tmp; restart: + flush_delayed_work("a_release_work); + spin_lock(&dq_list_lock); list_for_each_entry_safe(dquot, tmp, &inuse_list, dq_inuse) { if (dquot->dq_sb != sb) @@ -540,7 +573,7 @@ static void invalidate_dquots(struct super_block *sb, int type) continue; /* Wait for dquot users */ if (atomic_read(&dquot->dq_count)) { - dqgrab(dquot); + atomic_inc(&dquot->dq_count); spin_unlock(&dq_list_lock); /* * Once dqput() wakes us up, we know it's time to free @@ -558,6 +591,15 @@ static void invalidate_dquots(struct super_block *sb, int type) * restart. */ goto restart; } + /* + * The last user already dropped its reference but dquot didn't + * get fully cleaned up yet. Restart the scan which flushes the + * work cleaning up released dquots. + */ + if (test_bit(DQ_RELEASING_B, &dquot->dq_flags)) { + spin_unlock(&dq_list_lock); + goto restart; + } /* * Quota now has no users and it has been written on last * dqput() @@ -582,14 +624,13 @@ int dquot_scan_active(struct super_block *sb, spin_lock(&dq_list_lock); list_for_each_entry(dquot, &inuse_list, dq_inuse) { - if (!test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) + if (!dquot_active(dquot)) continue; if (dquot->dq_sb != sb) continue; /* Now we have active dquot so we can just increase use count */ atomic_inc(&dquot->dq_count); spin_unlock(&dq_list_lock); - dqstats_inc(DQST_LOOKUPS); dqput(old_dquot); old_dquot = dquot; /* @@ -598,7 +639,7 @@ int dquot_scan_active(struct super_block *sb, * outstanding call and recheck the DQ_ACTIVE_B after that. */ wait_on_dquot(dquot); - if (test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) { + if (dquot_active(dquot)) { ret = fn(dquot, priv); if (ret < 0) goto out; @@ -614,6 +655,18 @@ int dquot_scan_active(struct super_block *sb, } EXPORT_SYMBOL(dquot_scan_active); +static inline int dquot_write_dquot(struct dquot *dquot) +{ + int ret = dquot->dq_sb->dq_op->write_dquot(dquot); + if (ret < 0) { + quota_error(dquot->dq_sb, "Can't write quota structure " + "(error %d). Quota may get out of sync!", ret); + /* Clear dirty bit anyway to avoid infinite loop. */ + clear_dquot_dirty(dquot); + } + return ret; +} + /* Write all dquot structures to quota files */ int dquot_writeback_dquots(struct super_block *sb, int type) { @@ -637,24 +690,23 @@ int dquot_writeback_dquots(struct super_block *sb, int type) dquot = list_first_entry(&dirty, struct dquot, dq_dirty); - WARN_ON(!test_bit(DQ_ACTIVE_B, &dquot->dq_flags)); + WARN_ON(!dquot_active(dquot)); + /* If the dquot is releasing we should not touch it */ + if (test_bit(DQ_RELEASING_B, &dquot->dq_flags)) { + spin_unlock(&dq_list_lock); + flush_delayed_work("a_release_work); + spin_lock(&dq_list_lock); + continue; + } /* Now we have active dquot from which someone is * holding reference so we can safely just increase * use count */ dqgrab(dquot); spin_unlock(&dq_list_lock); - dqstats_inc(DQST_LOOKUPS); - err = sb->dq_op->write_dquot(dquot); - if (err) { - /* - * Clear dirty bit anyway to avoid infinite - * loop here. - */ - clear_dquot_dirty(dquot); - if (!ret) - ret = err; - } + err = dquot_write_dquot(dquot); + if (err && !ret) + ret = err; dqput(dquot); spin_lock(&dq_list_lock); } @@ -747,13 +799,53 @@ static struct shrinker dqcache_shrinker = { .seeks = DEFAULT_SEEKS, }; +/* + * Safely release dquot and put reference to dquot. + */ +static void quota_release_workfn(struct work_struct *work) +{ + struct dquot *dquot; + struct list_head rls_head; + + spin_lock(&dq_list_lock); + /* Exchange the list head to avoid livelock. */ + list_replace_init(&releasing_dquots, &rls_head); + spin_unlock(&dq_list_lock); + synchronize_srcu(&dquot_srcu); + +restart: + spin_lock(&dq_list_lock); + while (!list_empty(&rls_head)) { + dquot = list_first_entry(&rls_head, struct dquot, dq_free); + WARN_ON_ONCE(atomic_read(&dquot->dq_count)); + /* + * Note that DQ_RELEASING_B protects us from racing with + * invalidate_dquots() calls so we are safe to work with the + * dquot even after we drop dq_list_lock. + */ + if (dquot_dirty(dquot)) { + spin_unlock(&dq_list_lock); + /* Commit dquot before releasing */ + dquot_write_dquot(dquot); + goto restart; + } + if (dquot_active(dquot)) { + spin_unlock(&dq_list_lock); + dquot->dq_sb->dq_op->release_dquot(dquot); + goto restart; + } + /* Dquot is inactive and clean, now move it to free list */ + remove_free_dquot(dquot); + put_dquot_last(dquot); + } + spin_unlock(&dq_list_lock); +} + /* * Put reference to dquot */ void dqput(struct dquot *dquot) { - int ret; - if (!dquot) return; #ifdef CONFIG_QUOTA_DEBUG @@ -765,7 +857,7 @@ void dqput(struct dquot *dquot) } #endif dqstats_inc(DQST_DROPS); -we_slept: + spin_lock(&dq_list_lock); if (atomic_read(&dquot->dq_count) > 1) { /* We have more than one user... nothing to do */ @@ -777,35 +869,16 @@ void dqput(struct dquot *dquot) spin_unlock(&dq_list_lock); return; } + /* Need to release dquot? */ - if (dquot_dirty(dquot)) { - spin_unlock(&dq_list_lock); - /* Commit dquot before releasing */ - ret = dquot->dq_sb->dq_op->write_dquot(dquot); - if (ret < 0) { - quota_error(dquot->dq_sb, "Can't write quota structure" - " (error %d). Quota may get out of sync!", - ret); - /* - * We clear dirty bit anyway, so that we avoid - * infinite loop here - */ - clear_dquot_dirty(dquot); - } - goto we_slept; - } - if (test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) { - spin_unlock(&dq_list_lock); - dquot->dq_sb->dq_op->release_dquot(dquot); - goto we_slept; - } - atomic_dec(&dquot->dq_count); #ifdef CONFIG_QUOTA_DEBUG /* sanity check */ BUG_ON(!list_empty(&dquot->dq_free)); #endif - put_dquot_last(dquot); + put_releasing_dquots(dquot); + atomic_dec(&dquot->dq_count); spin_unlock(&dq_list_lock); + queue_delayed_work(system_unbound_wq, "a_release_work, 1); } EXPORT_SYMBOL(dqput); @@ -892,10 +965,10 @@ struct dquot *dqget(struct super_block *sb, struct kqid qid) dqstats_inc(DQST_LOOKUPS); } /* Wait for dq_lock - after this we know that either dquot_release() is - * already finished or it will be canceled due to dq_count > 1 test */ + * already finished or it will be canceled due to dq_count > 0 test */ wait_on_dquot(dquot); /* Read the dquot / allocate space in quota file */ - if (!test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) { + if (!dquot_active(dquot)) { int err; err = sb->dq_op->acquire_dquot(dquot); @@ -1408,7 +1481,7 @@ static int info_bdq_free(struct dquot *dquot, qsize_t space) return QUOTA_NL_NOWARN; } -static int dquot_active(const struct inode *inode) +static int inode_quota_active(const struct inode *inode) { struct super_block *sb = inode->i_sb; @@ -1431,7 +1504,7 @@ static int __dquot_initialize(struct inode *inode, int type) qsize_t rsv; int ret = 0; - if (!dquot_active(inode)) + if (!inode_quota_active(inode)) return 0; dquots = i_dquot(inode); @@ -1539,7 +1612,7 @@ bool dquot_initialize_needed(struct inode *inode) struct dquot **dquots; int i; - if (!dquot_active(inode)) + if (!inode_quota_active(inode)) return false; dquots = i_dquot(inode); @@ -1650,7 +1723,7 @@ int __dquot_alloc_space(struct inode *inode, qsize_t number, int flags) int reserve = flags & DQUOT_SPACE_RESERVE; struct dquot **dquots; - if (!dquot_active(inode)) { + if (!inode_quota_active(inode)) { if (reserve) { spin_lock(&inode->i_lock); *inode_reserved_space(inode) += number; @@ -1722,7 +1795,7 @@ int dquot_alloc_inode(struct inode *inode) struct dquot_warn warn[MAXQUOTAS]; struct dquot * const *dquots; - if (!dquot_active(inode)) + if (!inode_quota_active(inode)) return 0; for (cnt = 0; cnt < MAXQUOTAS; cnt++) warn[cnt].w_type = QUOTA_NL_NOWARN; @@ -1765,7 +1838,7 @@ int dquot_claim_space_nodirty(struct inode *inode, qsize_t number) struct dquot **dquots; int cnt, index; - if (!dquot_active(inode)) { + if (!inode_quota_active(inode)) { spin_lock(&inode->i_lock); *inode_reserved_space(inode) -= number; __inode_add_bytes(inode, number); @@ -1807,7 +1880,7 @@ void dquot_reclaim_space_nodirty(struct inode *inode, qsize_t number) struct dquot **dquots; int cnt, index; - if (!dquot_active(inode)) { + if (!inode_quota_active(inode)) { spin_lock(&inode->i_lock); *inode_reserved_space(inode) += number; __inode_sub_bytes(inode, number); @@ -1851,7 +1924,7 @@ void __dquot_free_space(struct inode *inode, qsize_t number, int flags) struct dquot **dquots; int reserve = flags & DQUOT_SPACE_RESERVE, index; - if (!dquot_active(inode)) { + if (!inode_quota_active(inode)) { if (reserve) { spin_lock(&inode->i_lock); *inode_reserved_space(inode) -= number; @@ -1906,7 +1979,7 @@ void dquot_free_inode(struct inode *inode) struct dquot * const *dquots; int index; - if (!dquot_active(inode)) + if (!inode_quota_active(inode)) return; dquots = i_dquot(inode); @@ -2077,7 +2150,7 @@ int dquot_transfer(struct inode *inode, struct iattr *iattr) struct super_block *sb = inode->i_sb; int ret; - if (!dquot_active(inode)) + if (!inode_quota_active(inode)) return 0; if (iattr->ia_valid & ATTR_UID && !uid_eq(iattr->ia_uid, inode->i_uid)){ @@ -2312,6 +2385,20 @@ static int vfs_setup_quota_inode(struct inode *inode, int type) if (sb_has_quota_loaded(sb, type)) return -EBUSY; + /* + * Quota files should never be encrypted. They should be thought of as + * filesystem metadata, not user data. New-style internal quota files + * cannot be encrypted by users anyway, but old-style external quota + * files could potentially be incorrectly created in an encrypted + * directory, hence this explicit check. Some reasons why encrypted + * quota files don't work include: (1) some filesystems that support + * encryption don't handle it in their quota_read and quota_write, and + * (2) cleaning up encrypted quota files at unmount would need special + * consideration, as quota files are cleaned up later than user files. + */ + if (IS_ENCRYPTED(inode)) + return -EINVAL; + dqopt->files[type] = igrab(inode); if (!dqopt->files[type]) return -EIO; @@ -2407,7 +2494,8 @@ int dquot_load_quota_sb(struct super_block *sb, int type, int format_id, error = add_dquot_ref(sb, type); if (error) - dquot_disable(sb, type, flags); + dquot_disable(sb, type, + DQUOT_USAGE_ENABLED | DQUOT_LIMITS_ENABLED); return error; out_fmt: @@ -2534,21 +2622,15 @@ int dquot_quota_on_mount(struct super_block *sb, char *qf_name, struct dentry *dentry; int error; - dentry = lookup_one_len_unlocked(qf_name, sb->s_root, strlen(qf_name)); + dentry = lookup_positive_unlocked(qf_name, sb->s_root, strlen(qf_name)); if (IS_ERR(dentry)) return PTR_ERR(dentry); - if (d_really_is_negative(dentry)) { - error = -ENOENT; - goto out; - } - error = security_quota_on(dentry); if (!error) error = vfs_load_quota_inode(d_inode(dentry), type, format_id, DQUOT_USAGE_ENABLED | DQUOT_LIMITS_ENABLED); -out: dput(dentry); return error; } diff --git a/fs/reiserfs/journal.c b/fs/reiserfs/journal.c index 78be6dbcd7627016a6d8458561fa43ab5cae0150..3425a04bc8a015e5f0bce2b432088a10997ccff9 100644 --- a/fs/reiserfs/journal.c +++ b/fs/reiserfs/journal.c @@ -2336,7 +2336,7 @@ static struct buffer_head *reiserfs_breada(struct block_device *dev, int i, j; bh = __getblk(dev, block, bufsize); - if (buffer_uptodate(bh)) + if (!bh || buffer_uptodate(bh)) return (bh); if (block + BUFNR > max_block) { @@ -2346,6 +2346,8 @@ static struct buffer_head *reiserfs_breada(struct block_device *dev, j = 1; for (i = 1; i < blocks; i++) { bh = __getblk(dev, block + i, bufsize); + if (!bh) + break; if (buffer_uptodate(bh)) { brelse(bh); break; diff --git a/fs/reiserfs/xattr_security.c b/fs/reiserfs/xattr_security.c index 59d87f9f72fb4172bd31bcd1baa65e3b0ff1df3b..159af6c26f4bd1d717573f7b8d80bddd43f6d0ec 100644 --- a/fs/reiserfs/xattr_security.c +++ b/fs/reiserfs/xattr_security.c @@ -81,11 +81,15 @@ int reiserfs_security_write(struct reiserfs_transaction_handle *th, struct inode *inode, struct reiserfs_security_handle *sec) { + char xattr_name[XATTR_NAME_MAX + 1] = XATTR_SECURITY_PREFIX; int error; - if (strlen(sec->name) < sizeof(XATTR_SECURITY_PREFIX)) + + if (XATTR_SECURITY_PREFIX_LEN + strlen(sec->name) > XATTR_NAME_MAX) return -EINVAL; - error = reiserfs_xattr_set_handle(th, inode, sec->name, sec->value, + strlcat(xattr_name, sec->name, sizeof(xattr_name)); + + error = reiserfs_xattr_set_handle(th, inode, xattr_name, sec->value, sec->length, XATTR_CREATE); if (error == -ENODATA || error == -EOPNOTSUPP) error = 0; diff --git a/fs/statfs.c b/fs/statfs.c index 56f655f757ffb36cb53c9f60f35695652d929529..29786598c2b5d53ef4be02df7d76c0388673e4db 100644 --- a/fs/statfs.c +++ b/fs/statfs.c @@ -114,6 +114,7 @@ static int do_statfs_native(struct kstatfs *st, struct statfs __user *p) if (sizeof(buf) == sizeof(*st)) memcpy(&buf, st, sizeof(*st)); else { + memset(&buf, 0, sizeof(buf)); if (sizeof buf.f_blocks == 4) { if ((st->f_blocks | st->f_bfree | st->f_bavail | st->f_bsize | st->f_frsize) & @@ -142,7 +143,6 @@ static int do_statfs_native(struct kstatfs *st, struct statfs __user *p) buf.f_namelen = st->f_namelen; buf.f_frsize = st->f_frsize; buf.f_flags = st->f_flags; - memset(buf.f_spare, 0, sizeof(buf.f_spare)); } if (copy_to_user(p, &buf, sizeof(buf))) return -EFAULT; @@ -155,6 +155,7 @@ static int do_statfs64(struct kstatfs *st, struct statfs64 __user *p) if (sizeof(buf) == sizeof(*st)) memcpy(&buf, st, sizeof(*st)); else { + memset(&buf, 0, sizeof(buf)); buf.f_type = st->f_type; buf.f_bsize = st->f_bsize; buf.f_blocks = st->f_blocks; @@ -166,7 +167,6 @@ static int do_statfs64(struct kstatfs *st, struct statfs64 __user *p) buf.f_namelen = st->f_namelen; buf.f_frsize = st->f_frsize; buf.f_flags = st->f_flags; - memset(buf.f_spare, 0, sizeof(buf.f_spare)); } if (copy_to_user(p, &buf, sizeof(buf))) return -EFAULT; diff --git a/fs/sysfs/file.c b/fs/sysfs/file.c index 0c952040d128fb5a91993a04e84beb5648ae5f89..1dc81c949ec5bd1008e87e77e47773469aba61a3 100644 --- a/fs/sysfs/file.c +++ b/fs/sysfs/file.c @@ -601,7 +601,7 @@ int sysfs_emit_at(char *buf, int at, const char *fmt, ...) va_list args; int len; - if (WARN(!buf || offset_in_page(buf) || at < 0 || at >= PAGE_SIZE, + if (WARN(!buf || at < 0 || at >= PAGE_SIZE, "invalid sysfs_emit_at: buf:%p at:%d\n", buf, at)) return 0; diff --git a/fs/sysv/itree.c b/fs/sysv/itree.c index 31f66053e2393bf9beea05f47c75887052fc6a53..e3d1673b8ec9728c265b54dc3752b096f257a663 100644 --- a/fs/sysv/itree.c +++ b/fs/sysv/itree.c @@ -145,6 +145,10 @@ static int alloc_branch(struct inode *inode, */ parent = block_to_cpu(SYSV_SB(inode->i_sb), branch[n-1].key); bh = sb_getblk(inode->i_sb, parent); + if (!bh) { + sysv_free_block(inode->i_sb, branch[n].key); + break; + } lock_buffer(bh); memset(bh->b_data, 0, blocksize); branch[n].bh = bh; diff --git a/fs/ubifs/budget.c b/fs/ubifs/budget.c index 7ef22baf9d150781e97381780be20a6d9dee6d81..30c7bd63c2ad197465cfa2019782a12004614b93 100644 --- a/fs/ubifs/budget.c +++ b/fs/ubifs/budget.c @@ -224,11 +224,10 @@ long long ubifs_calc_available(const struct ubifs_info *c, int min_idx_lebs) subtract_lebs += 1; /* - * The GC journal head LEB is not really accessible. And since - * different write types go to different heads, we may count only on - * one head's space. + * Since different write types go to different heads, we should + * reserve one leb for each head. */ - subtract_lebs += c->jhead_cnt - 1; + subtract_lebs += c->jhead_cnt; /* We also reserve one LEB for deletions, which bypass budgeting */ subtract_lebs += 1; @@ -415,7 +414,7 @@ static int calc_dd_growth(const struct ubifs_info *c, dd_growth = req->dirtied_page ? c->bi.page_budget : 0; if (req->dirtied_ino) - dd_growth += c->bi.inode_budget << (req->dirtied_ino - 1); + dd_growth += c->bi.inode_budget * req->dirtied_ino; if (req->mod_dent) dd_growth += c->bi.dent_budget; dd_growth += req->dirtied_ino_d; diff --git a/fs/ubifs/commit.c b/fs/ubifs/commit.c index 591f2c7a48f072f6c6ea6df736f3a8ec2eaafa7c..583e20787689b1e4aa41a45ec9838e500654ea67 100644 --- a/fs/ubifs/commit.c +++ b/fs/ubifs/commit.c @@ -564,11 +564,11 @@ int dbg_old_index_check_init(struct ubifs_info *c, struct ubifs_zbranch *zroot) */ int dbg_check_old_index(struct ubifs_info *c, struct ubifs_zbranch *zroot) { - int lnum, offs, len, err = 0, uninitialized_var(last_level), child_cnt; + int lnum, offs, len, err = 0, last_level, child_cnt; int first = 1, iip; struct ubifs_debug_info *d = c->dbg; - union ubifs_key uninitialized_var(lower_key), upper_key, l_key, u_key; - unsigned long long uninitialized_var(last_sqnum); + union ubifs_key lower_key, upper_key, l_key, u_key; + unsigned long long last_sqnum; struct ubifs_idx_node *idx; struct list_head list; struct idx_node *i; diff --git a/fs/ubifs/dir.c b/fs/ubifs/dir.c index 11cea64a01fb2d8d676d236f43494631f01e7767..ec69e734a0f0e945df7a20c51e678cc4cce28b68 100644 --- a/fs/ubifs/dir.c +++ b/fs/ubifs/dir.c @@ -445,6 +445,7 @@ static int do_tmpfile(struct inode *dir, struct dentry *dentry, mutex_unlock(&dir_ui->ui_mutex); ubifs_release_budget(c, &req); + fscrypt_free_filename(&nm); return 0; @@ -1141,7 +1142,6 @@ static int ubifs_symlink(struct inode *dir, struct dentry *dentry, int err, sz_change, len = strlen(symname); struct fscrypt_str disk_link; struct ubifs_budget_req req = { .new_ino = 1, .new_dent = 1, - .new_ino_d = ALIGN(len, 8), .dirtied_ino = 1 }; struct fscrypt_name nm; @@ -1157,6 +1157,7 @@ static int ubifs_symlink(struct inode *dir, struct dentry *dentry, * Budget request settings: new inode, new direntry and changing parent * directory inode. */ + req.new_ino_d = ALIGN(disk_link.len - 1, 8); err = ubifs_budget_space(c, &req); if (err) return err; @@ -1293,7 +1294,7 @@ static int do_rename(struct inode *old_dir, struct dentry *old_dentry, struct ubifs_budget_req ino_req = { .dirtied_ino = 1, .dirtied_ino_d = ALIGN(old_inode_ui->data_len, 8) }; struct timespec64 time; - unsigned int uninitialized_var(saved_nlink); + unsigned int saved_nlink; struct fscrypt_name old_nm, new_nm; /* @@ -1309,9 +1310,13 @@ static int do_rename(struct inode *old_dir, struct dentry *old_dentry, old_dentry, old_inode->i_ino, old_dir->i_ino, new_dentry, new_dir->i_ino, flags); - if (unlink) + if (unlink) { ubifs_assert(c, inode_is_locked(new_inode)); + /* Budget for old inode's data when its nlink > 1. */ + req.dirtied_ino_d = ALIGN(ubifs_inode(new_inode)->data_len, 8); + } + if (unlink && is_dir) { err = ubifs_check_dir_empty(new_inode); if (err) @@ -1549,6 +1554,10 @@ static int ubifs_xrename(struct inode *old_dir, struct dentry *old_dentry, return err; } + err = ubifs_budget_space(c, &req); + if (err) + goto out; + lock_4_inodes(old_dir, new_dir, NULL, NULL); time = current_time(old_dir); @@ -1574,6 +1583,7 @@ static int ubifs_xrename(struct inode *old_dir, struct dentry *old_dentry, unlock_4_inodes(old_dir, new_dir, NULL, NULL); ubifs_release_budget(c, &req); +out: fscrypt_free_filename(&fst_nm); fscrypt_free_filename(&snd_nm); return err; diff --git a/fs/ubifs/file.c b/fs/ubifs/file.c index 3dbb5ac630e42cb76d43085b14e0f0f374c4ed07..fca3b7f483c79698518ccfe14b7474cbdd63e4fd 100644 --- a/fs/ubifs/file.c +++ b/fs/ubifs/file.c @@ -234,7 +234,7 @@ static int write_begin_slow(struct address_space *mapping, struct ubifs_info *c = inode->i_sb->s_fs_info; pgoff_t index = pos >> PAGE_SHIFT; struct ubifs_budget_req req = { .new_page = 1 }; - int uninitialized_var(err), appending = !!(pos + len > inode->i_size); + int err, appending = !!(pos + len > inode->i_size); struct page *page; dbg_gen("ino %lu, pos %llu, len %u, i_size %lld", @@ -438,7 +438,7 @@ static int ubifs_write_begin(struct file *file, struct address_space *mapping, struct ubifs_info *c = inode->i_sb->s_fs_info; struct ubifs_inode *ui = ubifs_inode(inode); pgoff_t index = pos >> PAGE_SHIFT; - int uninitialized_var(err), appending = !!(pos + len > inode->i_size); + int err, appending = !!(pos + len > inode->i_size); int skipped_read = 0; struct page *page; @@ -1043,7 +1043,7 @@ static int ubifs_writepage(struct page *page, struct writeback_control *wbc) if (page->index >= synced_i_size >> PAGE_SHIFT) { err = inode->i_sb->s_op->write_inode(inode, NULL); if (err) - goto out_unlock; + goto out_redirty; /* * The inode has been written, but the write-buffer has * not been synchronized, so in case of an unclean @@ -1071,11 +1071,17 @@ static int ubifs_writepage(struct page *page, struct writeback_control *wbc) if (i_size > synced_i_size) { err = inode->i_sb->s_op->write_inode(inode, NULL); if (err) - goto out_unlock; + goto out_redirty; } return do_writepage(page, len); - +out_redirty: + /* + * redirty_page_for_writepage() won't call ubifs_dirty_inode() because + * it passes I_DIRTY_PAGES flag while calling __mark_inode_dirty(), so + * there is no need to do space budget for dirty inode. + */ + redirty_page_for_writepage(wbc, page); out_unlock: unlock_page(page); return err; diff --git a/fs/ubifs/journal.c b/fs/ubifs/journal.c index 81e539780e7796c86bc6a1b5973eb42cf3970fce..6bd9ab72f0556e8e641936d1ac4e8b75baecdf50 100644 --- a/fs/ubifs/journal.c +++ b/fs/ubifs/journal.c @@ -1355,7 +1355,7 @@ int ubifs_jnl_truncate(struct ubifs_info *c, const struct inode *inode, union ubifs_key key, to_key; struct ubifs_ino_node *ino; struct ubifs_trun_node *trun; - struct ubifs_data_node *uninitialized_var(dn); + struct ubifs_data_node *dn; int err, dlen, len, lnum, offs, bit, sz, sync = IS_SYNC(inode); struct ubifs_inode *ui = ubifs_inode(inode); ino_t inum = inode->i_ino; diff --git a/fs/ubifs/lpt.c b/fs/ubifs/lpt.c index 31393370e334826c182a2ea159df1caa435af158..433bfcddc497c5548a01f9fba99d5ef301941db7 100644 --- a/fs/ubifs/lpt.c +++ b/fs/ubifs/lpt.c @@ -287,7 +287,7 @@ uint32_t ubifs_unpack_bits(const struct ubifs_info *c, uint8_t **addr, int *pos, const int k = 32 - nrbits; uint8_t *p = *addr; int b = *pos; - uint32_t uninitialized_var(val); + uint32_t val; const int bytes = (nrbits + b + 7) >> 3; ubifs_assert(c, nrbits > 0); diff --git a/fs/ubifs/tnc.c b/fs/ubifs/tnc.c index f15ac37956e7a2f1f9e9606f7f9736d7acbeaab8..330ccf72745bb704ba375cf6bfac6f449437986a 100644 --- a/fs/ubifs/tnc.c +++ b/fs/ubifs/tnc.c @@ -56,6 +56,33 @@ enum { NOT_ON_MEDIA = 3, }; +static void do_insert_old_idx(struct ubifs_info *c, + struct ubifs_old_idx *old_idx) +{ + struct ubifs_old_idx *o; + struct rb_node **p, *parent = NULL; + + p = &c->old_idx.rb_node; + while (*p) { + parent = *p; + o = rb_entry(parent, struct ubifs_old_idx, rb); + if (old_idx->lnum < o->lnum) + p = &(*p)->rb_left; + else if (old_idx->lnum > o->lnum) + p = &(*p)->rb_right; + else if (old_idx->offs < o->offs) + p = &(*p)->rb_left; + else if (old_idx->offs > o->offs) + p = &(*p)->rb_right; + else { + ubifs_err(c, "old idx added twice!"); + kfree(old_idx); + } + } + rb_link_node(&old_idx->rb, parent, p); + rb_insert_color(&old_idx->rb, &c->old_idx); +} + /** * insert_old_idx - record an index node obsoleted since the last commit start. * @c: UBIFS file-system description object @@ -81,35 +108,15 @@ enum { */ static int insert_old_idx(struct ubifs_info *c, int lnum, int offs) { - struct ubifs_old_idx *old_idx, *o; - struct rb_node **p, *parent = NULL; + struct ubifs_old_idx *old_idx; old_idx = kmalloc(sizeof(struct ubifs_old_idx), GFP_NOFS); if (unlikely(!old_idx)) return -ENOMEM; old_idx->lnum = lnum; old_idx->offs = offs; + do_insert_old_idx(c, old_idx); - p = &c->old_idx.rb_node; - while (*p) { - parent = *p; - o = rb_entry(parent, struct ubifs_old_idx, rb); - if (lnum < o->lnum) - p = &(*p)->rb_left; - else if (lnum > o->lnum) - p = &(*p)->rb_right; - else if (offs < o->offs) - p = &(*p)->rb_left; - else if (offs > o->offs) - p = &(*p)->rb_right; - else { - ubifs_err(c, "old idx added twice!"); - kfree(old_idx); - return 0; - } - } - rb_link_node(&old_idx->rb, parent, p); - rb_insert_color(&old_idx->rb, &c->old_idx); return 0; } @@ -211,23 +218,6 @@ static struct ubifs_znode *copy_znode(struct ubifs_info *c, __set_bit(DIRTY_ZNODE, &zn->flags); __clear_bit(COW_ZNODE, &zn->flags); - ubifs_assert(c, !ubifs_zn_obsolete(znode)); - __set_bit(OBSOLETE_ZNODE, &znode->flags); - - if (znode->level != 0) { - int i; - const int n = zn->child_cnt; - - /* The children now have new parent */ - for (i = 0; i < n; i++) { - struct ubifs_zbranch *zbr = &zn->zbranch[i]; - - if (zbr->znode) - zbr->znode->parent = zn; - } - } - - atomic_long_inc(&c->dirty_zn_cnt); return zn; } @@ -245,6 +235,42 @@ static int add_idx_dirt(struct ubifs_info *c, int lnum, int dirt) return ubifs_add_dirt(c, lnum, dirt); } +/** + * replace_znode - replace old znode with new znode. + * @c: UBIFS file-system description object + * @new_zn: new znode + * @old_zn: old znode + * @zbr: the branch of parent znode + * + * Replace old znode with new znode in TNC. + */ +static void replace_znode(struct ubifs_info *c, struct ubifs_znode *new_zn, + struct ubifs_znode *old_zn, struct ubifs_zbranch *zbr) +{ + ubifs_assert(c, !ubifs_zn_obsolete(old_zn)); + __set_bit(OBSOLETE_ZNODE, &old_zn->flags); + + if (old_zn->level != 0) { + int i; + const int n = new_zn->child_cnt; + + /* The children now have new parent */ + for (i = 0; i < n; i++) { + struct ubifs_zbranch *child = &new_zn->zbranch[i]; + + if (child->znode) + child->znode->parent = new_zn; + } + } + + zbr->znode = new_zn; + zbr->lnum = 0; + zbr->offs = 0; + zbr->len = 0; + + atomic_long_inc(&c->dirty_zn_cnt); +} + /** * dirty_cow_znode - ensure a znode is not being committed. * @c: UBIFS file-system description object @@ -277,21 +303,32 @@ static struct ubifs_znode *dirty_cow_znode(struct ubifs_info *c, return zn; if (zbr->len) { - err = insert_old_idx(c, zbr->lnum, zbr->offs); - if (unlikely(err)) - return ERR_PTR(err); + struct ubifs_old_idx *old_idx; + + old_idx = kmalloc(sizeof(struct ubifs_old_idx), GFP_NOFS); + if (unlikely(!old_idx)) { + err = -ENOMEM; + goto out; + } + old_idx->lnum = zbr->lnum; + old_idx->offs = zbr->offs; + err = add_idx_dirt(c, zbr->lnum, zbr->len); - } else - err = 0; + if (err) { + kfree(old_idx); + goto out; + } - zbr->znode = zn; - zbr->lnum = 0; - zbr->offs = 0; - zbr->len = 0; + do_insert_old_idx(c, old_idx); + } + + replace_znode(c, zn, znode, zbr); - if (unlikely(err)) - return ERR_PTR(err); return zn; + +out: + kfree(zn); + return ERR_PTR(err); } /** @@ -899,7 +936,7 @@ static int fallible_resolve_collision(struct ubifs_info *c, int adding) { struct ubifs_znode *o_znode = NULL, *znode = *zn; - int uninitialized_var(o_n), err, cmp, unsure = 0, nn = *n; + int o_n, err, cmp, unsure = 0, nn = *n; cmp = fallible_matches_name(c, &znode->zbranch[nn], nm); if (unlikely(cmp < 0)) @@ -1521,8 +1558,8 @@ int ubifs_tnc_locate(struct ubifs_info *c, const union ubifs_key *key, */ int ubifs_tnc_get_bu_keys(struct ubifs_info *c, struct bu_info *bu) { - int n, err = 0, lnum = -1, uninitialized_var(offs); - int uninitialized_var(len); + int n, err = 0, lnum = -1, offs; + int len; unsigned int block = key_block(c, &bu->key); struct ubifs_znode *znode; @@ -3046,6 +3083,21 @@ static void tnc_destroy_cnext(struct ubifs_info *c) cnext = cnext->cnext; if (ubifs_zn_obsolete(znode)) kfree(znode); + else if (!ubifs_zn_cow(znode)) { + /* + * Don't forget to update clean znode count after + * committing failed, because ubifs will check this + * count while closing tnc. Non-obsolete znode could + * be re-dirtied during committing process, so dirty + * flag is untrustable. The flag 'COW_ZNODE' is set + * for each dirty znode before committing, and it is + * cleared as long as the znode become clean, so we + * can statistic clean znode count according to this + * flag. + */ + atomic_long_inc(&c->clean_zn_cnt); + atomic_long_inc(&ubifs_clean_zn_cnt); + } } while (cnext && cnext != c->cnext); } diff --git a/fs/ubifs/tnc_misc.c b/fs/ubifs/tnc_misc.c index d90ee01076a9ea5559dd8afb26cffc4e61a5cb81..fe3b52d2749b439c56b44404988fce0b3fec37ed 100644 --- a/fs/ubifs/tnc_misc.c +++ b/fs/ubifs/tnc_misc.c @@ -138,8 +138,8 @@ int ubifs_search_zbranch(const struct ubifs_info *c, const struct ubifs_znode *znode, const union ubifs_key *key, int *n) { - int beg = 0, end = znode->child_cnt, uninitialized_var(mid); - int uninitialized_var(cmp); + int beg = 0, end = znode->child_cnt, mid; + int cmp; const struct ubifs_zbranch *zbr = &znode->zbranch[0]; ubifs_assert(c, end > beg); diff --git a/fs/udf/balloc.c b/fs/udf/balloc.c index fcda0fc97b90a14fd53aafbeb15885d85716e3a1..0dc98bbad9c466f0f014d38331569123ba73da8e 100644 --- a/fs/udf/balloc.c +++ b/fs/udf/balloc.c @@ -36,18 +36,41 @@ static int read_block_bitmap(struct super_block *sb, unsigned long bitmap_nr) { struct buffer_head *bh = NULL; - int retval = 0; + int i; + int max_bits, off, count; struct kernel_lb_addr loc; loc.logicalBlockNum = bitmap->s_extPosition; loc.partitionReferenceNum = UDF_SB(sb)->s_partition; bh = udf_tread(sb, udf_get_lb_pblock(sb, &loc, block)); + bitmap->s_block_bitmap[bitmap_nr] = bh; if (!bh) - retval = -EIO; + return -EIO; - bitmap->s_block_bitmap[bitmap_nr] = bh; - return retval; + /* Check consistency of Space Bitmap buffer. */ + max_bits = sb->s_blocksize * 8; + if (!bitmap_nr) { + off = sizeof(struct spaceBitmapDesc) << 3; + count = min(max_bits - off, bitmap->s_nr_groups); + } else { + /* + * Rough check if bitmap number is too big to have any bitmap + * blocks reserved. + */ + if (bitmap_nr > + (bitmap->s_nr_groups >> (sb->s_blocksize_bits + 3)) + 2) + return 0; + off = 0; + count = bitmap->s_nr_groups - bitmap_nr * max_bits + + (sizeof(struct spaceBitmapDesc) << 3); + count = min(count, max_bits); + } + + for (i = 0; i < count; i++) + if (udf_test_bit(i + off, bh->b_data)) + return -EFSCORRUPTED; + return 0; } static int __load_block_bitmap(struct super_block *sb, @@ -555,7 +578,7 @@ static udf_pblk_t udf_table_new_block(struct super_block *sb, udf_pblk_t newblock = 0; uint32_t adsize; uint32_t elen, goal_elen = 0; - struct kernel_lb_addr eloc, uninitialized_var(goal_eloc); + struct kernel_lb_addr eloc, goal_eloc; struct extent_position epos, goal_epos; int8_t etype; struct udf_inode_info *iinfo = UDF_I(table); diff --git a/fs/udf/directory.c b/fs/udf/directory.c index d9523013096f978c9d4a3ca1d8fdd23b55eeb275..73720320f0ab74cb5c1dde319eb93dc07f595803 100644 --- a/fs/udf/directory.c +++ b/fs/udf/directory.c @@ -34,7 +34,7 @@ struct fileIdentDesc *udf_fileident_read(struct inode *dir, loff_t *nf_pos, fibh->soffset = fibh->eoffset; if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { - fi = udf_get_fileident(iinfo->i_ext.i_data - + fi = udf_get_fileident(iinfo->i_data - (iinfo->i_efe ? sizeof(struct extendedFileEntry) : sizeof(struct fileEntry)), diff --git a/fs/udf/file.c b/fs/udf/file.c index cd31e4f6d6da95a84cfebb629e3c890519d6f431..8fff7ffc33a819a210aa113045e70bb9d8810e85 100644 --- a/fs/udf/file.c +++ b/fs/udf/file.c @@ -50,7 +50,7 @@ static void __udf_adinicb_readpage(struct page *page) * So just sample it once and use the same value everywhere. */ kaddr = kmap_atomic(page); - memcpy(kaddr, iinfo->i_ext.i_data + iinfo->i_lenEAttr, isize); + memcpy(kaddr, iinfo->i_data + iinfo->i_lenEAttr, isize); memset(kaddr + isize, 0, PAGE_SIZE - isize); flush_dcache_page(page); SetPageUptodate(page); @@ -76,8 +76,7 @@ static int udf_adinicb_writepage(struct page *page, BUG_ON(!PageLocked(page)); kaddr = kmap_atomic(page); - memcpy(iinfo->i_ext.i_data + iinfo->i_lenEAttr, kaddr, - i_size_read(inode)); + memcpy(iinfo->i_data + iinfo->i_lenEAttr, kaddr, i_size_read(inode)); SetPageUptodate(page); kunmap_atomic(kaddr); mark_inode_dirty(inode); @@ -148,26 +147,24 @@ static ssize_t udf_file_write_iter(struct kiocb *iocb, struct iov_iter *from) goto out; down_write(&iinfo->i_data_sem); - if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { - loff_t end = iocb->ki_pos + iov_iter_count(from); - - if (inode->i_sb->s_blocksize < - (udf_file_entry_alloc_offset(inode) + end)) { - err = udf_expand_file_adinicb(inode); - if (err) { - inode_unlock(inode); - udf_debug("udf_expand_adinicb: err=%d\n", err); - return err; - } - } else { - iinfo->i_lenAlloc = max(end, inode->i_size); - up_write(&iinfo->i_data_sem); + if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB && + inode->i_sb->s_blocksize < (udf_file_entry_alloc_offset(inode) + + iocb->ki_pos + iov_iter_count(from))) { + err = udf_expand_file_adinicb(inode); + if (err) { + inode_unlock(inode); + udf_debug("udf_expand_adinicb: err=%d\n", err); + return err; } } else up_write(&iinfo->i_data_sem); retval = __generic_file_write_iter(iocb, from); out: + down_write(&iinfo->i_data_sem); + if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB && retval > 0) + iinfo->i_lenAlloc = inode->i_size; + up_write(&iinfo->i_data_sem); inode_unlock(inode); if (retval > 0) { @@ -215,7 +212,7 @@ long udf_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return put_user(UDF_I(inode)->i_lenEAttr, (int __user *)arg); case UDF_GETEABLOCK: return copy_to_user((char __user *)arg, - UDF_I(inode)->i_ext.i_data, + UDF_I(inode)->i_data, UDF_I(inode)->i_lenEAttr) ? -EFAULT : 0; default: return -ENOIOCTLCMD; diff --git a/fs/udf/ialloc.c b/fs/udf/ialloc.c index f8e5872f7cc271d93ad6c27e34add63ebbc2c2f2..cdaa86e077b29e59da6c6d61b6c1549e72af45c5 100644 --- a/fs/udf/ialloc.c +++ b/fs/udf/ialloc.c @@ -67,16 +67,16 @@ struct inode *udf_new_inode(struct inode *dir, umode_t mode) iinfo->i_efe = 1; if (UDF_VERS_USE_EXTENDED_FE > sbi->s_udfrev) sbi->s_udfrev = UDF_VERS_USE_EXTENDED_FE; - iinfo->i_ext.i_data = kzalloc(inode->i_sb->s_blocksize - - sizeof(struct extendedFileEntry), - GFP_KERNEL); + iinfo->i_data = kzalloc(inode->i_sb->s_blocksize - + sizeof(struct extendedFileEntry), + GFP_KERNEL); } else { iinfo->i_efe = 0; - iinfo->i_ext.i_data = kzalloc(inode->i_sb->s_blocksize - - sizeof(struct fileEntry), - GFP_KERNEL); + iinfo->i_data = kzalloc(inode->i_sb->s_blocksize - + sizeof(struct fileEntry), + GFP_KERNEL); } - if (!iinfo->i_ext.i_data) { + if (!iinfo->i_data) { iput(inode); return ERR_PTR(-ENOMEM); } diff --git a/fs/udf/inode.c b/fs/udf/inode.c index 55a86120e756f1b3e7badd90177f8368389365bc..08d7208eb7b750fa8121683afd86111db9984219 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -50,15 +50,15 @@ static int udf_update_inode(struct inode *, int); static int udf_sync_inode(struct inode *inode); static int udf_alloc_i_data(struct inode *inode, size_t size); static sector_t inode_getblk(struct inode *, sector_t, int *, int *); -static int8_t udf_insert_aext(struct inode *, struct extent_position, - struct kernel_lb_addr, uint32_t); +static int udf_insert_aext(struct inode *, struct extent_position, + struct kernel_lb_addr, uint32_t); static void udf_split_extents(struct inode *, int *, int, udf_pblk_t, struct kernel_long_ad *, int *); static void udf_prealloc_extents(struct inode *, int, int, struct kernel_long_ad *, int *); static void udf_merge_extents(struct inode *, struct kernel_long_ad *, int *); -static void udf_update_extents(struct inode *, struct kernel_long_ad *, int, - int, struct extent_position *); +static int udf_update_extents(struct inode *, struct kernel_long_ad *, int, + int, struct extent_position *); static int udf_get_block(struct inode *, sector_t, struct buffer_head *, int); static void __udf_clear_extent_cache(struct inode *inode) @@ -150,8 +150,8 @@ void udf_evict_inode(struct inode *inode) truncate_inode_pages_final(&inode->i_data); invalidate_inode_buffers(inode); clear_inode(inode); - kfree(iinfo->i_ext.i_data); - iinfo->i_ext.i_data = NULL; + kfree(iinfo->i_data); + iinfo->i_data = NULL; udf_clear_extent_cache(inode); if (want_delete) { udf_free_inode(inode); @@ -278,14 +278,14 @@ int udf_expand_file_adinicb(struct inode *inode) kaddr = kmap_atomic(page); memset(kaddr + iinfo->i_lenAlloc, 0x00, PAGE_SIZE - iinfo->i_lenAlloc); - memcpy(kaddr, iinfo->i_ext.i_data + iinfo->i_lenEAttr, + memcpy(kaddr, iinfo->i_data + iinfo->i_lenEAttr, iinfo->i_lenAlloc); flush_dcache_page(page); SetPageUptodate(page); kunmap_atomic(kaddr); } down_write(&iinfo->i_data_sem); - memset(iinfo->i_ext.i_data + iinfo->i_lenEAttr, 0x00, + memset(iinfo->i_data + iinfo->i_lenEAttr, 0x00, iinfo->i_lenAlloc); iinfo->i_lenAlloc = 0; if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_SHORT_AD)) @@ -303,8 +303,7 @@ int udf_expand_file_adinicb(struct inode *inode) lock_page(page); down_write(&iinfo->i_data_sem); kaddr = kmap_atomic(page); - memcpy(iinfo->i_ext.i_data + iinfo->i_lenEAttr, kaddr, - inode->i_size); + memcpy(iinfo->i_data + iinfo->i_lenEAttr, kaddr, inode->i_size); kunmap_atomic(kaddr); unlock_page(page); iinfo->i_alloc_type = ICBTAG_FLAG_AD_IN_ICB; @@ -392,8 +391,7 @@ struct buffer_head *udf_expand_dir_adinicb(struct inode *inode, } mark_buffer_dirty_inode(dbh, inode); - memset(iinfo->i_ext.i_data + iinfo->i_lenEAttr, 0, - iinfo->i_lenAlloc); + memset(iinfo->i_data + iinfo->i_lenEAttr, 0, iinfo->i_lenAlloc); iinfo->i_lenAlloc = 0; eloc.logicalBlockNum = *block; eloc.partitionReferenceNum = @@ -521,8 +519,10 @@ static int udf_do_extend_file(struct inode *inode, } if (fake) { - udf_add_aext(inode, last_pos, &last_ext->extLocation, - last_ext->extLength, 1); + err = udf_add_aext(inode, last_pos, &last_ext->extLocation, + last_ext->extLength, 1); + if (err < 0) + goto out_err; count++; } else { struct kernel_lb_addr tmploc; @@ -556,7 +556,7 @@ static int udf_do_extend_file(struct inode *inode, err = udf_add_aext(inode, last_pos, &last_ext->extLocation, last_ext->extLength, 1); if (err) - return err; + goto out_err; count++; } if (new_block_bytes) { @@ -565,7 +565,7 @@ static int udf_do_extend_file(struct inode *inode, err = udf_add_aext(inode, last_pos, &last_ext->extLocation, last_ext->extLength, 1); if (err) - return err; + goto out_err; count++; } @@ -579,6 +579,11 @@ static int udf_do_extend_file(struct inode *inode, return -EIO; return count; +out_err: + /* Remove extents we've created so far */ + udf_clear_extent_cache(inode); + udf_truncate_extents(inode); + return err; } /* Extend the final block of the file to final_block_len bytes */ @@ -684,7 +689,7 @@ static sector_t inode_getblk(struct inode *inode, sector_t block, struct kernel_lb_addr eloc, tmpeloc; int c = 1; loff_t lbcount = 0, b_off = 0; - udf_pblk_t newblocknum, newblock; + udf_pblk_t newblocknum, newblock = 0; sector_t offset = 0; int8_t etype; struct udf_inode_info *iinfo = UDF_I(inode); @@ -787,25 +792,22 @@ static sector_t inode_getblk(struct inode *inode, sector_t block, ret = udf_do_extend_file(inode, &prev_epos, laarr, hole_len); if (ret < 0) { *err = ret; - newblock = 0; goto out_free; } c = 0; offset = 0; count += ret; - /* We are not covered by a preallocated extent? */ - if ((laarr[0].extLength & UDF_EXTENT_FLAG_MASK) != - EXT_NOT_RECORDED_ALLOCATED) { - /* Is there any real extent? - otherwise we overwrite - * the fake one... */ - if (count) - c = !c; - laarr[c].extLength = EXT_NOT_RECORDED_NOT_ALLOCATED | - inode->i_sb->s_blocksize; - memset(&laarr[c].extLocation, 0x00, - sizeof(struct kernel_lb_addr)); - count++; - } + /* + * Is there any real extent? - otherwise we overwrite the fake + * one... + */ + if (count) + c = !c; + laarr[c].extLength = EXT_NOT_RECORDED_NOT_ALLOCATED | + inode->i_sb->s_blocksize; + memset(&laarr[c].extLocation, 0x00, + sizeof(struct kernel_lb_addr)); + count++; endnum = c + 1; lastblock = 1; } else { @@ -852,7 +854,6 @@ static sector_t inode_getblk(struct inode *inode, sector_t block, goal, err); if (!newblocknum) { *err = -ENOSPC; - newblock = 0; goto out_free; } if (isBeyondEOF) @@ -878,7 +879,9 @@ static sector_t inode_getblk(struct inode *inode, sector_t block, /* write back the new extents, inserting new extents if the new number * of extents is greater than the old number, and deleting extents if * the new number of extents is less than the old number */ - udf_update_extents(inode, laarr, startnum, endnum, &prev_epos); + *err = udf_update_extents(inode, laarr, startnum, endnum, &prev_epos); + if (*err < 0) + goto out_free; newblock = udf_get_pblock(inode->i_sb, newblocknum, iinfo->i_location.partitionReferenceNum, 0); @@ -1082,23 +1085,8 @@ static void udf_merge_extents(struct inode *inode, struct kernel_long_ad *laarr, blocksize - 1) >> blocksize_bits)))) { if (((li->extLength & UDF_EXTENT_LENGTH_MASK) + - (lip1->extLength & UDF_EXTENT_LENGTH_MASK) + - blocksize - 1) & ~UDF_EXTENT_LENGTH_MASK) { - lip1->extLength = (lip1->extLength - - (li->extLength & - UDF_EXTENT_LENGTH_MASK) + - UDF_EXTENT_LENGTH_MASK) & - ~(blocksize - 1); - li->extLength = (li->extLength & - UDF_EXTENT_FLAG_MASK) + - (UDF_EXTENT_LENGTH_MASK + 1) - - blocksize; - lip1->extLocation.logicalBlockNum = - li->extLocation.logicalBlockNum + - ((li->extLength & - UDF_EXTENT_LENGTH_MASK) >> - blocksize_bits); - } else { + (lip1->extLength & UDF_EXTENT_LENGTH_MASK) + + blocksize - 1) <= UDF_EXTENT_LENGTH_MASK) { li->extLength = lip1->extLength + (((li->extLength & UDF_EXTENT_LENGTH_MASK) + @@ -1161,21 +1149,30 @@ static void udf_merge_extents(struct inode *inode, struct kernel_long_ad *laarr, } } -static void udf_update_extents(struct inode *inode, struct kernel_long_ad *laarr, - int startnum, int endnum, - struct extent_position *epos) +static int udf_update_extents(struct inode *inode, struct kernel_long_ad *laarr, + int startnum, int endnum, + struct extent_position *epos) { int start = 0, i; struct kernel_lb_addr tmploc; uint32_t tmplen; + int err; if (startnum > endnum) { for (i = 0; i < (startnum - endnum); i++) udf_delete_aext(inode, *epos); } else if (startnum < endnum) { for (i = 0; i < (endnum - startnum); i++) { - udf_insert_aext(inode, *epos, laarr[i].extLocation, - laarr[i].extLength); + err = udf_insert_aext(inode, *epos, + laarr[i].extLocation, + laarr[i].extLength); + /* + * If we fail here, we are likely corrupting the extent + * list and leaking blocks. At least stop early to + * limit the damage. + */ + if (err < 0) + return err; udf_next_aext(inode, epos, &laarr[i].extLocation, &laarr[i].extLength, 1); start++; @@ -1187,6 +1184,7 @@ static void udf_update_extents(struct inode *inode, struct kernel_long_ad *laarr udf_write_aext(inode, epos, &laarr[i].extLocation, laarr[i].extLength, 1); } + return 0; } struct buffer_head *udf_bread(struct inode *inode, udf_pblk_t block, @@ -1251,7 +1249,7 @@ int udf_setsize(struct inode *inode, loff_t newsize) if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { down_write(&iinfo->i_data_sem); udf_clear_extent_cache(inode); - memset(iinfo->i_ext.i_data + iinfo->i_lenEAttr + newsize, + memset(iinfo->i_data + iinfo->i_lenEAttr + newsize, 0x00, bsize - newsize - udf_file_entry_alloc_offset(inode)); iinfo->i_lenAlloc = newsize; @@ -1387,6 +1385,7 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) ret = -EIO; goto out; } + iinfo->i_hidden = hidden_inode; iinfo->i_unique = 0; iinfo->i_lenEAttr = 0; iinfo->i_lenExtents = 0; @@ -1400,7 +1399,7 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) sizeof(struct extendedFileEntry)); if (ret) goto out; - memcpy(iinfo->i_ext.i_data, + memcpy(iinfo->i_data, bh->b_data + sizeof(struct extendedFileEntry), bs - sizeof(struct extendedFileEntry)); } else if (fe->descTag.tagIdent == cpu_to_le16(TAG_IDENT_FE)) { @@ -1409,7 +1408,7 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) ret = udf_alloc_i_data(inode, bs - sizeof(struct fileEntry)); if (ret) goto out; - memcpy(iinfo->i_ext.i_data, + memcpy(iinfo->i_data, bh->b_data + sizeof(struct fileEntry), bs - sizeof(struct fileEntry)); } else if (fe->descTag.tagIdent == cpu_to_le16(TAG_IDENT_USE)) { @@ -1422,7 +1421,7 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) sizeof(struct unallocSpaceEntry)); if (ret) goto out; - memcpy(iinfo->i_ext.i_data, + memcpy(iinfo->i_data, bh->b_data + sizeof(struct unallocSpaceEntry), bs - sizeof(struct unallocSpaceEntry)); return 0; @@ -1480,6 +1479,8 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) iinfo->i_lenEAttr = le32_to_cpu(fe->lengthExtendedAttr); iinfo->i_lenAlloc = le32_to_cpu(fe->lengthAllocDescs); iinfo->i_checkpoint = le32_to_cpu(fe->checkpoint); + iinfo->i_streamdir = 0; + iinfo->i_lenStreams = 0; } else { inode->i_blocks = le64_to_cpu(efe->logicalBlocksRecorded) << (inode->i_sb->s_blocksize_bits - 9); @@ -1493,6 +1494,16 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) iinfo->i_lenEAttr = le32_to_cpu(efe->lengthExtendedAttr); iinfo->i_lenAlloc = le32_to_cpu(efe->lengthAllocDescs); iinfo->i_checkpoint = le32_to_cpu(efe->checkpoint); + + /* Named streams */ + iinfo->i_streamdir = (efe->streamDirectoryICB.extLength != 0); + iinfo->i_locStreamdir = + lelb_to_cpu(efe->streamDirectoryICB.extLocation); + iinfo->i_lenStreams = le64_to_cpu(efe->objectSize); + if (iinfo->i_lenStreams >= inode->i_size) + iinfo->i_lenStreams -= inode->i_size; + else + iinfo->i_lenStreams = 0; } inode->i_generation = iinfo->i_unique; @@ -1589,8 +1600,8 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) static int udf_alloc_i_data(struct inode *inode, size_t size) { struct udf_inode_info *iinfo = UDF_I(inode); - iinfo->i_ext.i_data = kmalloc(size, GFP_KERNEL); - if (!iinfo->i_ext.i_data) + iinfo->i_data = kmalloc(size, GFP_KERNEL); + if (!iinfo->i_data) return -ENOMEM; return 0; } @@ -1664,7 +1675,7 @@ static int udf_update_inode(struct inode *inode, int do_sync) use->lengthAllocDescs = cpu_to_le32(iinfo->i_lenAlloc); memcpy(bh->b_data + sizeof(struct unallocSpaceEntry), - iinfo->i_ext.i_data, inode->i_sb->s_blocksize - + iinfo->i_data, inode->i_sb->s_blocksize - sizeof(struct unallocSpaceEntry)); use->descTag.tagIdent = cpu_to_le16(TAG_IDENT_USE); crclen = sizeof(struct unallocSpaceEntry); @@ -1694,8 +1705,12 @@ static int udf_update_inode(struct inode *inode, int do_sync) if (S_ISDIR(inode->i_mode) && inode->i_nlink > 0) fe->fileLinkCount = cpu_to_le16(inode->i_nlink - 1); - else - fe->fileLinkCount = cpu_to_le16(inode->i_nlink); + else { + if (iinfo->i_hidden) + fe->fileLinkCount = cpu_to_le16(0); + else + fe->fileLinkCount = cpu_to_le16(inode->i_nlink); + } fe->informationLength = cpu_to_le64(inode->i_size); @@ -1733,7 +1748,7 @@ static int udf_update_inode(struct inode *inode, int do_sync) if (iinfo->i_efe == 0) { memcpy(bh->b_data + sizeof(struct fileEntry), - iinfo->i_ext.i_data, + iinfo->i_data, inode->i_sb->s_blocksize - sizeof(struct fileEntry)); fe->logicalBlocksRecorded = cpu_to_le64(lb_recorded); @@ -1752,12 +1767,22 @@ static int udf_update_inode(struct inode *inode, int do_sync) crclen = sizeof(struct fileEntry); } else { memcpy(bh->b_data + sizeof(struct extendedFileEntry), - iinfo->i_ext.i_data, + iinfo->i_data, inode->i_sb->s_blocksize - sizeof(struct extendedFileEntry)); - efe->objectSize = cpu_to_le64(inode->i_size); + efe->objectSize = + cpu_to_le64(inode->i_size + iinfo->i_lenStreams); efe->logicalBlocksRecorded = cpu_to_le64(lb_recorded); + if (iinfo->i_streamdir) { + struct long_ad *icb_lad = &efe->streamDirectoryICB; + + icb_lad->extLocation = + cpu_to_lelb(iinfo->i_locStreamdir); + icb_lad->extLength = + cpu_to_le32(inode->i_sb->s_blocksize); + } + udf_adjust_time(iinfo, inode->i_atime); udf_adjust_time(iinfo, inode->i_mtime); udf_adjust_time(iinfo, inode->i_ctime); @@ -1856,8 +1881,13 @@ struct inode *__udf_iget(struct super_block *sb, struct kernel_lb_addr *ino, if (!inode) return ERR_PTR(-ENOMEM); - if (!(inode->i_state & I_NEW)) + if (!(inode->i_state & I_NEW)) { + if (UDF_I(inode)->i_hidden != hidden_inode) { + iput(inode); + return ERR_PTR(-EFSCORRUPTED); + } return inode; + } memcpy(&UDF_I(inode)->i_location, ino, sizeof(struct kernel_lb_addr)); err = udf_read_inode(inode, hidden_inode); @@ -2038,7 +2068,7 @@ void udf_write_aext(struct inode *inode, struct extent_position *epos, struct udf_inode_info *iinfo = UDF_I(inode); if (!epos->bh) - ptr = iinfo->i_ext.i_data + epos->offset - + ptr = iinfo->i_data + epos->offset - udf_file_entry_alloc_offset(inode) + iinfo->i_lenEAttr; else @@ -2130,7 +2160,7 @@ int8_t udf_current_aext(struct inode *inode, struct extent_position *epos, if (!epos->bh) { if (!epos->offset) epos->offset = udf_file_entry_alloc_offset(inode); - ptr = iinfo->i_ext.i_data + epos->offset - + ptr = iinfo->i_data + epos->offset - udf_file_entry_alloc_offset(inode) + iinfo->i_lenEAttr; alen = udf_file_entry_alloc_offset(inode) + @@ -2171,12 +2201,13 @@ int8_t udf_current_aext(struct inode *inode, struct extent_position *epos, return etype; } -static int8_t udf_insert_aext(struct inode *inode, struct extent_position epos, - struct kernel_lb_addr neloc, uint32_t nelen) +static int udf_insert_aext(struct inode *inode, struct extent_position epos, + struct kernel_lb_addr neloc, uint32_t nelen) { struct kernel_lb_addr oeloc; uint32_t oelen; int8_t etype; + int err; if (epos.bh) get_bh(epos.bh); @@ -2186,10 +2217,10 @@ static int8_t udf_insert_aext(struct inode *inode, struct extent_position epos, neloc = oeloc; nelen = (etype << 30) | oelen; } - udf_add_aext(inode, &epos, &neloc, nelen, 1); + err = udf_add_aext(inode, &epos, &neloc, nelen, 1); brelse(epos.bh); - return (nelen >> 30); + return err; } int8_t udf_delete_aext(struct inode *inode, struct extent_position epos) diff --git a/fs/udf/misc.c b/fs/udf/misc.c index 853bcff51043fe97bb6a77244bdb13cff59a093c..1614d308d0f06039ee0a4b27e0e9e9f93c44e8da 100644 --- a/fs/udf/misc.c +++ b/fs/udf/misc.c @@ -52,9 +52,9 @@ struct genericFormat *udf_add_extendedattr(struct inode *inode, uint32_t size, uint16_t crclen; struct udf_inode_info *iinfo = UDF_I(inode); - ea = iinfo->i_ext.i_data; + ea = iinfo->i_data; if (iinfo->i_lenEAttr) { - ad = iinfo->i_ext.i_data + iinfo->i_lenEAttr; + ad = iinfo->i_data + iinfo->i_lenEAttr; } else { ad = ea; size += sizeof(struct extendedAttrHeaderDesc); @@ -153,7 +153,7 @@ struct genericFormat *udf_get_extendedattr(struct inode *inode, uint32_t type, uint32_t offset; struct udf_inode_info *iinfo = UDF_I(inode); - ea = iinfo->i_ext.i_data; + ea = iinfo->i_data; if (iinfo->i_lenEAttr) { struct extendedAttrHeaderDesc *eahd; diff --git a/fs/udf/namei.c b/fs/udf/namei.c index ef251622da1375978286b66b46d52c2b565852c1..05dd1f45ba90be9feedd981a6bd7c2effe206868 100644 --- a/fs/udf/namei.c +++ b/fs/udf/namei.c @@ -478,8 +478,7 @@ static struct fileIdentDesc *udf_add_entry(struct inode *dir, if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { block = dinfo->i_location.logicalBlockNum; fi = (struct fileIdentDesc *) - (dinfo->i_ext.i_data + - fibh->soffset - + (dinfo->i_data + fibh->soffset - udf_ext0_offset(dir) + dinfo->i_lenEAttr); } else { @@ -962,7 +961,7 @@ static int udf_symlink(struct inode *dir, struct dentry *dentry, mark_buffer_dirty_inode(epos.bh, inode); ea = epos.bh->b_data + udf_ext0_offset(inode); } else - ea = iinfo->i_ext.i_data + iinfo->i_lenEAttr; + ea = iinfo->i_data + iinfo->i_lenEAttr; eoffset = sb->s_blocksize - udf_ext0_offset(inode); pc = (struct pathComponent *)ea; @@ -1142,7 +1141,7 @@ static int udf_rename(struct inode *old_dir, struct dentry *old_dentry, retval = -EIO; if (old_iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { dir_fi = udf_get_fileident( - old_iinfo->i_ext.i_data - + old_iinfo->i_data - (old_iinfo->i_efe ? sizeof(struct extendedFileEntry) : sizeof(struct fileEntry)), diff --git a/fs/udf/partition.c b/fs/udf/partition.c index 090baff83990adc808f52449e4a9c1844ab60ce6..4cbf40575965ef56f836ad5b4a78787e42f2af5a 100644 --- a/fs/udf/partition.c +++ b/fs/udf/partition.c @@ -65,7 +65,7 @@ uint32_t udf_get_pblock_virt15(struct super_block *sb, uint32_t block, } if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { - loc = le32_to_cpu(((__le32 *)(iinfo->i_ext.i_data + + loc = le32_to_cpu(((__le32 *)(iinfo->i_data + vdata->s_start_offset))[block]); goto translate; } diff --git a/fs/udf/super.c b/fs/udf/super.c index b7fb7cd35d89aeb8b2ee820180a3c041a2d53b48..bce48a07790cb2ca6074de99ff1ce0d5eb207cf4 100644 --- a/fs/udf/super.c +++ b/fs/udf/super.c @@ -146,9 +146,12 @@ static struct inode *udf_alloc_inode(struct super_block *sb) ei->i_unique = 0; ei->i_lenExtents = 0; + ei->i_lenStreams = 0; ei->i_next_alloc_block = 0; ei->i_next_alloc_goal = 0; ei->i_strat4096 = 0; + ei->i_streamdir = 0; + ei->i_hidden = 0; init_rwsem(&ei->i_data_sem); ei->cached_extent.lstart = -1; spin_lock_init(&ei->i_extent_cache_lock); @@ -172,7 +175,7 @@ static void init_once(void *foo) { struct udf_inode_info *ei = (struct udf_inode_info *)foo; - ei->i_ext.i_data = NULL; + ei->i_data = NULL; inode_init_once(&ei->vfs_inode); } @@ -572,6 +575,11 @@ static int udf_parse_options(char *options, struct udf_options *uopt, if (!remount) { if (uopt->nls_map) unload_nls(uopt->nls_map); + /* + * load_nls() failure is handled later in + * udf_fill_super() after all options are + * parsed. + */ uopt->nls_map = load_nls(args[0].from); uopt->flags |= (1 << UDF_FLAG_NLS_MAP); } @@ -1200,7 +1208,7 @@ static int udf_load_vat(struct super_block *sb, int p_index, int type1_index) vat20 = (struct virtualAllocationTable20 *)bh->b_data; } else { vat20 = (struct virtualAllocationTable20 *) - vati->i_ext.i_data; + vati->i_data; } map->s_type_specific.s_virtual.s_start_offset = diff --git a/fs/udf/symlink.c b/fs/udf/symlink.c index 6023c97c6da2f269894bdd3966a5a415c6345955..aef3e4d9014d208843387f1081446874782c32c2 100644 --- a/fs/udf/symlink.c +++ b/fs/udf/symlink.c @@ -122,7 +122,7 @@ static int udf_symlink_filler(struct file *file, struct page *page) down_read(&iinfo->i_data_sem); if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { - symlink = iinfo->i_ext.i_data + iinfo->i_lenEAttr; + symlink = iinfo->i_data + iinfo->i_lenEAttr; } else { bh = sb_bread(inode->i_sb, pos); diff --git a/fs/udf/udf_i.h b/fs/udf/udf_i.h index 2ef0e212f08a3d55ce25b8c6e34843a03fa5f88c..b77bf713a1b6823b35df631e9223a76c22e2bc19 100644 --- a/fs/udf/udf_i.h +++ b/fs/udf/udf_i.h @@ -42,12 +42,12 @@ struct udf_inode_info { unsigned i_efe : 1; /* extendedFileEntry */ unsigned i_use : 1; /* unallocSpaceEntry */ unsigned i_strat4096 : 1; - unsigned reserved : 26; - union { - struct short_ad *i_sad; - struct long_ad *i_lad; - __u8 *i_data; - } i_ext; + unsigned i_streamdir : 1; + unsigned i_hidden : 1; /* hidden system inode */ + unsigned reserved : 24; + __u8 *i_data; + struct kernel_lb_addr i_locStreamdir; + __u64 i_lenStreams; struct rw_semaphore i_data_sem; struct udf_ext_cache cached_extent; /* Spinlock for protecting extent cache */ diff --git a/fs/udf/udf_sb.h b/fs/udf/udf_sb.h index d12e507e9eb2a8fb1faeb97bea5623c497c913dc..aa58173b468fbfac2055638940ebc37743954ee8 100644 --- a/fs/udf/udf_sb.h +++ b/fs/udf/udf_sb.h @@ -57,6 +57,8 @@ #define MF_DUPLICATE_MD 0x01 #define MF_MIRROR_FE_LOADED 0x02 +#define EFSCORRUPTED EUCLEAN + struct udf_meta_data { __u32 s_meta_file_loc; __u32 s_mirror_file_loc; diff --git a/fs/udf/unicode.c b/fs/udf/unicode.c index 5fcfa96463ebb820cef33b83460fc8d1a9bea8b2..85521d6b023707c39a7809e441449b0d72ef3703 100644 --- a/fs/udf/unicode.c +++ b/fs/udf/unicode.c @@ -247,7 +247,7 @@ static int udf_name_from_CS0(struct super_block *sb, } if (translate) { - if (str_o_len <= 2 && str_o[0] == '.' && + if (str_o_len > 0 && str_o_len <= 2 && str_o[0] == '.' && (str_o_len == 1 || str_o[1] == '.')) needsCRC = 1; if (needsCRC) { diff --git a/fs/verity/enable.c b/fs/verity/enable.c index 835c3399fee5dfc5541b0321cf86da9694adc8af..fbebb8b7d1343de856740c347101688cde917277 100644 --- a/fs/verity/enable.c +++ b/fs/verity/enable.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include @@ -391,25 +390,27 @@ int fsverity_ioctl_enable(struct file *filp, const void __user *uarg) goto out_drop_write; err = enable_verity(filp, &arg); - if (err) - goto out_allow_write_access; /* - * Some pages of the file may have been evicted from pagecache after - * being used in the Merkle tree construction, then read into pagecache - * again by another process reading from the file concurrently. Since - * these pages didn't undergo verification against the file digest which - * fs-verity now claims to be enforcing, we have to wipe the pagecache - * to ensure that all future reads are verified. + * We no longer drop the inode's pagecache after enabling verity. This + * used to be done to try to avoid a race condition where pages could be + * evicted after being used in the Merkle tree construction, then + * re-instantiated by a concurrent read. Such pages are unverified, and + * the backing storage could have filled them with different content, so + * they shouldn't be used to fulfill reads once verity is enabled. + * + * But, dropping the pagecache has a big performance impact, and it + * doesn't fully solve the race condition anyway. So for those reasons, + * and also because this race condition isn't very important relatively + * speaking (especially for small-ish files, where the chance of a page + * being used, evicted, *and* re-instantiated all while enabling verity + * is quite small), we no longer drop the inode's pagecache. */ - filemap_write_and_wait(inode->i_mapping); - invalidate_inode_pages2(inode->i_mapping); /* * allow_write_access() is needed to pair with deny_write_access(). * Regardless, the filesystem won't allow writing to verity files. */ -out_allow_write_access: allow_write_access(filp); out_drop_write: mnt_drop_write_file(filp); diff --git a/fs/verity/verify.c b/fs/verity/verify.c index 817ce4f8cd3c8dd5abf4d90ff4f0ad0e2e9c68e2..a879fdcc161fe3aae100f038f765f0271a268883 100644 --- a/fs/verity/verify.c +++ b/fs/verity/verify.c @@ -279,15 +279,15 @@ EXPORT_SYMBOL_GPL(fsverity_enqueue_verify_work); int __init fsverity_init_workqueue(void) { /* - * Use an unbound workqueue to allow bios to be verified in parallel - * even when they happen to complete on the same CPU. This sacrifices - * locality, but it's worthwhile since hashing is CPU-intensive. + * Use a high-priority workqueue to prioritize verification work, which + * blocks reads from completing, over regular application tasks. * - * Also use a high-priority workqueue to prioritize verification work, - * which blocks reads from completing, over regular application tasks. + * For performance reasons, don't use an unbound workqueue. Using an + * unbound workqueue for crypto operations causes excessive scheduler + * latency on ARM64. */ fsverity_read_workqueue = alloc_workqueue("fsverity_read_queue", - WQ_UNBOUND | WQ_HIGHPRI, + WQ_HIGHPRI, num_online_cpus()); if (!fsverity_read_workqueue) return -ENOMEM; diff --git a/fs/xfs/xfs_bmap_util.c b/fs/xfs/xfs_bmap_util.c index 3e1dd66bd6769b76d17fd1c8b7ad8da75c1b1c00..734b80a4220c1493aab08d0bbc92ca01624d0d59 100644 --- a/fs/xfs/xfs_bmap_util.c +++ b/fs/xfs/xfs_bmap_util.c @@ -130,7 +130,7 @@ xfs_bmap_rtalloc( * pick an extent that will space things out in the rt area. */ if (ap->eof && ap->offset == 0) { - xfs_rtblock_t uninitialized_var(rtx); /* realtime extent no */ + xfs_rtblock_t rtx; /* realtime extent no */ error = xfs_rtpick_extent(mp, ap->tp, ralen, &rtx); if (error) diff --git a/include/asm-generic/bugs.h b/include/asm-generic/bugs.h deleted file mode 100644 index 69021830f078d68331eadbab7f2a2240c1f863ba..0000000000000000000000000000000000000000 --- a/include/asm-generic/bugs.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_GENERIC_BUGS_H -#define __ASM_GENERIC_BUGS_H -/* - * This file is included by 'init/main.c' to check for - * architecture-dependent bugs. - */ - -static inline void check_bugs(void) { } - -#endif /* __ASM_GENERIC_BUGS_H */ diff --git a/include/asm-generic/word-at-a-time.h b/include/asm-generic/word-at-a-time.h index 20c93f08c9933b81d4a362701d30cd7fda5106d6..95a1d214108a5d38f01fb98108028f321e3c6d4e 100644 --- a/include/asm-generic/word-at-a-time.h +++ b/include/asm-generic/word-at-a-time.h @@ -38,7 +38,7 @@ static inline long find_zero(unsigned long mask) return (mask >> 8) ? byte : byte + 1; } -static inline bool has_zero(unsigned long val, unsigned long *data, const struct word_at_a_time *c) +static inline unsigned long has_zero(unsigned long val, unsigned long *data, const struct word_at_a_time *c) { unsigned long rhs = val | c->low_bits; *data = rhs; diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index a3c02470cc390b6b0eaba4fc47b7e5165eeec052..ed47ee513adcb64026edbf8b62549f5a9ae4fbde 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -317,19 +317,47 @@ struct drm_display_info { #define DRM_BUS_FLAG_DE_LOW (1<<0) #define DRM_BUS_FLAG_DE_HIGH (1<<1) -/* drive data on pos. edge */ + +/* + * Don't use those two flags directly, use the DRM_BUS_FLAG_PIXDATA_DRIVE_* + * and DRM_BUS_FLAG_PIXDATA_SAMPLE_* variants to qualify the flags explicitly. + * The DRM_BUS_FLAG_PIXDATA_SAMPLE_* flags are defined as the opposite of the + * DRM_BUS_FLAG_PIXDATA_DRIVE_* flags to make code simpler, as signals are + * usually to be sampled on the opposite edge of the driving edge. + */ #define DRM_BUS_FLAG_PIXDATA_POSEDGE (1<<2) -/* drive data on neg. edge */ #define DRM_BUS_FLAG_PIXDATA_NEGEDGE (1<<3) + +/* Drive data on rising edge */ +#define DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE DRM_BUS_FLAG_PIXDATA_POSEDGE +/* Drive data on falling edge */ +#define DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE DRM_BUS_FLAG_PIXDATA_NEGEDGE +/* Sample data on rising edge */ +#define DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE DRM_BUS_FLAG_PIXDATA_NEGEDGE +/* Sample data on falling edge */ +#define DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE DRM_BUS_FLAG_PIXDATA_POSEDGE + /* data is transmitted MSB to LSB on the bus */ #define DRM_BUS_FLAG_DATA_MSB_TO_LSB (1<<4) /* data is transmitted LSB to MSB on the bus */ #define DRM_BUS_FLAG_DATA_LSB_TO_MSB (1<<5) -/* drive sync on pos. edge */ + +/* + * Similarly to the DRM_BUS_FLAG_PIXDATA_* flags, don't use these two flags + * directly, use one of the DRM_BUS_FLAG_SYNC_(DRIVE|SAMPLE)_* instead. + */ #define DRM_BUS_FLAG_SYNC_POSEDGE (1<<6) -/* drive sync on neg. edge */ #define DRM_BUS_FLAG_SYNC_NEGEDGE (1<<7) +/* Drive sync on rising edge */ +#define DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE DRM_BUS_FLAG_SYNC_POSEDGE +/* Drive sync on falling edge */ +#define DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE DRM_BUS_FLAG_SYNC_NEGEDGE +/* Sample sync on rising edge */ +#define DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE DRM_BUS_FLAG_SYNC_NEGEDGE +/* Sample sync on falling edge */ +#define DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE DRM_BUS_FLAG_SYNC_POSEDGE + /** * @bus_flags: Additional information (like pixel signal polarity) for * the pixel data on the bus, using DRM_BUS_FLAGS\_ defines. diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 328f232f33eef1cb5bd4c8c68c5f1fe9f8aa5bc9..6d7fbac8fdf8345cc4afc47b0839697ad7b2b6ef 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -286,6 +286,10 @@ int mipi_dsi_dcs_set_display_brightness(struct mipi_dsi_device *dsi, u16 brightness); int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi, u16 *brightness); +int mipi_dsi_dcs_set_display_brightness_large(struct mipi_dsi_device *dsi, + u16 brightness); +int mipi_dsi_dcs_get_display_brightness_large(struct mipi_dsi_device *dsi, + u16 *brightness); /** * struct mipi_dsi_driver - DSI driver diff --git a/include/dt-bindings/clock/qcom,gcc-scuba.h b/include/dt-bindings/clock/qcom,gcc-scuba.h index f4eb89ce979847412816e8fd31d0479a542bfc6f..1c00e346ff251d9a830173145b5b06eb552c1133 100644 --- a/include/dt-bindings/clock/qcom,gcc-scuba.h +++ b/include/dt-bindings/clock/qcom,gcc-scuba.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SCUBA_H @@ -155,6 +156,7 @@ #define GCC_VIDEO_VENUS_CLK_SRC 145 #define GCC_VIDEO_VENUS_CTL_CLK 146 #define GCC_VIDEO_XO_CLK 147 +#define GCC_PWM0_XO512_DIV_CLK_SRC 148 /* GCC resets */ #define GCC_CAMSS_OPE_BCR 0 diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 96b9bfab653a47c1f05b7e2fff8dece59c2a2ecd..8642761dbf997763ba7499b9c8cb130737db553d 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -13,6 +13,7 @@ #define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_TYPE(long)) +#define BITS_TO_BYTES(nr) DIV_ROUND_UP(nr, BITS_PER_TYPE(char)) extern unsigned int __sw_hweight8(unsigned int w); extern unsigned int __sw_hweight16(unsigned int w); diff --git a/include/linux/build_bug.h b/include/linux/build_bug.h index 6099f754aad7ccc239abaadc657fc78350962455..ff67bd110f562685454a689d83e321330e3a1906 100644 --- a/include/linux/build_bug.h +++ b/include/linux/build_bug.h @@ -85,4 +85,23 @@ #define _Static_assert(expr, ...) #endif +/** + * static_assert - check integer constant expression at build time + * + * static_assert() is a wrapper for the C11 _Static_assert, with a + * little macro magic to make the message optional (defaulting to the + * stringification of the tested expression). + * + * Contrary to BUILD_BUG_ON(), static_assert() can be used at global + * scope, but requires the expression to be an integer constant + * expression (i.e., it is not enough that __builtin_constant_p() is + * true for expr). + * + * Also note that BUILD_BUG_ON() fails the build if the condition is + * true, while static_assert() fails the build if the expression is + * false. + */ +#define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr) +#define __static_assert(expr, msg, ...) _Static_assert(expr, msg) + #endif /* _LINUX_BUILD_BUG_H */ diff --git a/include/linux/clk.h b/include/linux/clk.h index 751506abe271d313d6af73c4af3134dc884e0ebe..d3147fe30e87e7f64819133217b806fb926a357d 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -175,6 +175,39 @@ int clk_get_scaled_duty_cycle(struct clk *clk, unsigned int scale); */ bool clk_is_match(const struct clk *p, const struct clk *q); +/** + * clk_rate_exclusive_get - get exclusivity over the rate control of a + * producer + * @clk: clock source + * + * This function allows drivers to get exclusive control over the rate of a + * provider. It prevents any other consumer to execute, even indirectly, + * opereation which could alter the rate of the provider or cause glitches + * + * If exlusivity is claimed more than once on clock, even by the same driver, + * the rate effectively gets locked as exclusivity can't be preempted. + * + * Must not be called from within atomic context. + * + * Returns success (0) or negative errno. + */ +int clk_rate_exclusive_get(struct clk *clk); + +/** + * clk_rate_exclusive_put - release exclusivity over the rate control of a + * producer + * @clk: clock source + * + * This function allows drivers to release the exclusivity it previously got + * from clk_rate_exclusive_get() + * + * The caller must balance the number of clk_rate_exclusive_get() and + * clk_rate_exclusive_put() calls. + * + * Must not be called from within atomic context. + */ +void clk_rate_exclusive_put(struct clk *clk); + #else static inline int clk_notifier_register(struct clk *clk, @@ -221,6 +254,13 @@ static inline bool clk_is_match(const struct clk *p, const struct clk *q) return p == q; } +static inline int clk_rate_exclusive_get(struct clk *clk) +{ + return 0; +} + +static inline void clk_rate_exclusive_put(struct clk *clk) {} + #endif /** @@ -364,38 +404,6 @@ struct clk *devm_clk_get(struct device *dev, const char *id); */ struct clk *devm_get_clk_from_child(struct device *dev, struct device_node *np, const char *con_id); -/** - * clk_rate_exclusive_get - get exclusivity over the rate control of a - * producer - * @clk: clock source - * - * This function allows drivers to get exclusive control over the rate of a - * provider. It prevents any other consumer to execute, even indirectly, - * opereation which could alter the rate of the provider or cause glitches - * - * If exlusivity is claimed more than once on clock, even by the same driver, - * the rate effectively gets locked as exclusivity can't be preempted. - * - * Must not be called from within atomic context. - * - * Returns success (0) or negative errno. - */ -int clk_rate_exclusive_get(struct clk *clk); - -/** - * clk_rate_exclusive_put - release exclusivity over the rate control of a - * producer - * @clk: clock source - * - * This function allows drivers to release the exclusivity it previously got - * from clk_rate_exclusive_get() - * - * The caller must balance the number of clk_rate_exclusive_get() and - * clk_rate_exclusive_put() calls. - * - * Must not be called from within atomic context. - */ -void clk_rate_exclusive_put(struct clk *clk); /** * clk_enable - inform the system when the clock source should be running. @@ -674,14 +682,6 @@ static inline void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) {} static inline void devm_clk_put(struct device *dev, struct clk *clk) {} - -static inline int clk_rate_exclusive_get(struct clk *clk) -{ - return 0; -} - -static inline void clk_rate_exclusive_put(struct clk *clk) {} - static inline int clk_enable(struct clk *clk) { return 0; diff --git a/include/linux/cpu.h b/include/linux/cpu.h index 9dc44bdeebca15bd1ab6a605ce50f2031f60f43e..0c5013f8ca60a3f9d105f05ea964d0c9165916f2 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h @@ -170,6 +170,12 @@ void arch_cpu_idle_enter(void); void arch_cpu_idle_exit(void); void arch_cpu_idle_dead(void); +#ifdef CONFIG_ARCH_HAS_CPU_FINALIZE_INIT +void arch_cpu_finalize_init(void); +#else +static inline void arch_cpu_finalize_init(void) { } +#endif + int cpu_report_state(int cpu); int cpu_check_up_prepare(int cpu); void cpu_set_state_online(int cpu); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 2a7359382954c96b2ebbf96e72a03c3b4674463f..41bd07c5d9340f776dcb8d148ee37068987e69ce 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -113,7 +113,7 @@ enum cpuhp_state { CPUHP_AP_PERF_X86_CSTATE_STARTING, CPUHP_AP_PERF_XTENSA_STARTING, CPUHP_AP_MIPS_OP_LOONGSON3_STARTING, - CPUHP_AP_ARM_SDEI_STARTING, + CPUHP_AP_ARM_SDEI_STARTING, // Android ABI preservation, not used. CPUHP_AP_ARM_VFP_STARTING, CPUHP_AP_ARM64_DEBUG_MONITORS_STARTING, CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING, diff --git a/include/linux/debugfs.h b/include/linux/debugfs.h index 6ebc269e48ace1a3c3aef092fe74197ef6315fa2..0624c9a1f01eafa5dd70d219839edfc1936c6960 100644 --- a/include/linux/debugfs.h +++ b/include/linux/debugfs.h @@ -35,6 +35,7 @@ struct debugfs_regset32 { const struct debugfs_reg32 *regs; int nregs; void __iomem *base; + struct device *dev; /* Optional device for Runtime PM */ }; extern struct dentry *arch_debugfs_dir; diff --git a/include/linux/device.h b/include/linux/device.h index 2d9e155fcc40b2ad090f8b36ecbce43a710306cf..11fb0bdce054e4fdae8d399b18a387dba7e6c540 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -359,6 +359,8 @@ extern int __must_check driver_create_file(struct device_driver *driver, extern void driver_remove_file(struct device_driver *driver, const struct driver_attribute *attr); +int driver_set_override(struct device *dev, const char **override, + const char *s, size_t len); extern int __must_check driver_for_each_device(struct device_driver *drv, struct device *start, void *data, diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h index e1e9eff096d05bc25e82aeebb03b3f6cccd5b2a8..2932a40060c1d928d4d1caeac3b73bde1d06505d 100644 --- a/include/linux/etherdevice.h +++ b/include/linux/etherdevice.h @@ -291,6 +291,18 @@ static inline void ether_addr_copy(u8 *dst, const u8 *src) #endif } +/** + * eth_hw_addr_set - Assign Ethernet address to a net_device + * @dev: pointer to net_device structure + * @addr: address to assign + * + * Assign given address to the net_device, addr_assign_type is not changed. + */ +static inline void eth_hw_addr_set(struct net_device *dev, const u8 *addr) +{ + ether_addr_copy(dev->dev_addr, addr); +} + /** * eth_hw_addr_inherit - Copy dev_addr from another net_device * @dst: pointer to net_device to copy dev_addr to diff --git a/include/linux/eventfd.h b/include/linux/eventfd.h index 3482f9365a4db29f01bd744543f93b9e6c911f17..de0ad39d4281f53208cbc2d3fd0add85dcccc1c4 100644 --- a/include/linux/eventfd.h +++ b/include/linux/eventfd.h @@ -41,6 +41,7 @@ struct eventfd_ctx *eventfd_ctx_fileget(struct file *file); __u64 eventfd_signal(struct eventfd_ctx *ctx, __u64 n); int eventfd_ctx_remove_wait_queue(struct eventfd_ctx *ctx, wait_queue_entry_t *wait, __u64 *cnt); +void eventfd_ctx_do_read(struct eventfd_ctx *ctx, __u64 *cnt); DECLARE_PER_CPU(int, eventfd_wake_count); @@ -82,6 +83,11 @@ static inline bool eventfd_signal_count(void) return false; } +static inline void eventfd_ctx_do_read(struct eventfd_ctx *ctx, __u64 *cnt) +{ + +} + #endif #endif /* _LINUX_EVENTFD_H */ diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h index 677a5eab83c5c1f8a02dec8af7e0969134394fdf..4cc81900426f2d91f4478469c7f0bf53bea77cf3 100644 --- a/include/linux/ftrace.h +++ b/include/linux/ftrace.h @@ -697,7 +697,7 @@ static inline void __ftrace_enabled_restore(int enabled) #define CALLER_ADDR5 ((unsigned long)ftrace_return_address(5)) #define CALLER_ADDR6 ((unsigned long)ftrace_return_address(6)) -static inline unsigned long get_lock_parent_ip(void) +static __always_inline unsigned long get_lock_parent_ip(void) { unsigned long addr = CALLER_ADDR0; diff --git a/include/linux/hid.h b/include/linux/hid.h index c51ebce2197e0ca8a99f8052ae331eb0b42f0d7e..79c6c3b4e0044bdb8ca011ecdbc72fc755623d04 100644 --- a/include/linux/hid.h +++ b/include/linux/hid.h @@ -799,6 +799,7 @@ struct hid_driver { * @raw_request: send raw report request to device (e.g. feature report) * @output_report: send output report to device * @idle: send idle request to device + * @max_buffer_size: over-ride maximum data buffer size (default: HID_MAX_BUFFER_SIZE) */ struct hid_ll_driver { int (*start)(struct hid_device *hdev); @@ -823,6 +824,8 @@ struct hid_ll_driver { int (*output_report) (struct hid_device *hdev, __u8 *buf, size_t len); int (*idle)(struct hid_device *hdev, int report, int idle, int reqtype); + + unsigned int max_buffer_size; }; extern struct hid_ll_driver i2c_hid_ll_driver; diff --git a/include/linux/if_arp.h b/include/linux/if_arp.h index c697a0524273522a9f6558f13b89a1bdd4d4b46d..a6f14d8e4e810d27be8814e7e339e18d2f1b5bb2 100644 --- a/include/linux/if_arp.h +++ b/include/linux/if_arp.h @@ -56,6 +56,10 @@ static inline bool dev_is_mac_header_xmit(const struct net_device *dev) case ARPHRD_NONE: case ARPHRD_RAWIP: case ARPHRD_PIMREG: + /* PPP adds its l2 header automatically in ppp_start_xmit(). + * This makes it look like an l3 device to __bpf_redirect() and tcf_mirred_init(). + */ + case ARPHRD_PPP: return false; default: return true; diff --git a/include/linux/if_team.h b/include/linux/if_team.h index ac42da56f7a28f375dbc50887fee19eaf97c2327..fd32538ae705ec1cef6de566bcb498ea170d9941 100644 --- a/include/linux/if_team.h +++ b/include/linux/if_team.h @@ -196,6 +196,8 @@ struct team { struct net_device *dev; /* associated netdevice */ struct team_pcpu_stats __percpu *pcpu_stats; + const struct header_ops *header_ops_cache; + struct mutex lock; /* used for overall locking, e.g. port lists write */ /* diff --git a/include/linux/ima.h b/include/linux/ima.h index 97914a2833d10ad566edf474918e2afed39f73fc..edd6d9195ce122470dea90d95e8b0ecd26f0b911 100644 --- a/include/linux/ima.h +++ b/include/linux/ima.h @@ -19,7 +19,8 @@ struct linux_binprm; extern int ima_bprm_check(struct linux_binprm *bprm); extern int ima_file_check(struct file *file, int mask); extern void ima_file_free(struct file *file); -extern int ima_file_mmap(struct file *file, unsigned long prot); +extern int ima_file_mmap(struct file *file, unsigned long reqprot, + unsigned long prot, unsigned long flags); extern int ima_load_data(enum kernel_load_data_id id); extern int ima_read_file(struct file *file, enum kernel_read_file_id id); extern int ima_post_read_file(struct file *file, void *buf, loff_t size, @@ -46,7 +47,8 @@ static inline void ima_file_free(struct file *file) return; } -static inline int ima_file_mmap(struct file *file, unsigned long prot) +static inline int ima_file_mmap(struct file *file, unsigned long reqprot, + unsigned long prot, unsigned long flags) { return 0; } diff --git a/include/linux/indirect_call_wrapper.h b/include/linux/indirect_call_wrapper.h new file mode 100644 index 0000000000000000000000000000000000000000..7c8b7f4948af5690c67402cf8bf818856fff8e0c --- /dev/null +++ b/include/linux/indirect_call_wrapper.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_INDIRECT_CALL_WRAPPER_H +#define _LINUX_INDIRECT_CALL_WRAPPER_H + +#ifdef CONFIG_RETPOLINE + +/* + * INDIRECT_CALL_$NR - wrapper for indirect calls with $NR known builtin + * @f: function pointer + * @f$NR: builtin functions names, up to $NR of them + * @__VA_ARGS__: arguments for @f + * + * Avoid retpoline overhead for known builtin, checking @f vs each of them and + * eventually invoking directly the builtin function. The functions are check + * in the given order. Fallback to the indirect call. + */ +#define INDIRECT_CALL_1(f, f1, ...) \ + ({ \ + likely(f == f1) ? f1(__VA_ARGS__) : f(__VA_ARGS__); \ + }) +#define INDIRECT_CALL_2(f, f2, f1, ...) \ + ({ \ + likely(f == f2) ? f2(__VA_ARGS__) : \ + INDIRECT_CALL_1(f, f1, __VA_ARGS__); \ + }) + +#define INDIRECT_CALLABLE_DECLARE(f) f +#define INDIRECT_CALLABLE_SCOPE + +#else +#define INDIRECT_CALL_1(f, name, ...) f(__VA_ARGS__) +#define INDIRECT_CALL_2(f, name, ...) f(__VA_ARGS__) +#define INDIRECT_CALLABLE_DECLARE(f) +#define INDIRECT_CALLABLE_SCOPE static +#endif + +/* + * We can use INDIRECT_CALL_$NR for ipv6 related functions only if ipv6 is + * builtin, this macro simplify dealing with indirect calls with only ipv4/ipv6 + * alternatives + */ +#if IS_BUILTIN(CONFIG_IPV6) +#define INDIRECT_CALL_INET(f, f2, f1, ...) \ + INDIRECT_CALL_2(f, f2, f1, __VA_ARGS__) +#elif IS_ENABLED(CONFIG_INET) +#define INDIRECT_CALL_INET(f, f2, f1, ...) INDIRECT_CALL_1(f, f1, __VA_ARGS__) +#else +#define INDIRECT_CALL_INET(f, f2, f1, ...) f(__VA_ARGS__) +#endif + +#endif diff --git a/include/linux/ipmi_smi.h b/include/linux/ipmi_smi.h index 1995ce1467890f03c9043d6d1ef70ea316398bde..75865064c70b2b8db575746fb84bb1450a8a4ceb 100644 --- a/include/linux/ipmi_smi.h +++ b/include/linux/ipmi_smi.h @@ -30,6 +30,14 @@ struct device; /* Structure for the low-level drivers. */ typedef struct ipmi_smi *ipmi_smi_t; +/* + * Flags for set_check_watch() below. Tells if the SMI should be + * waiting for watchdog timeouts, commands and/or messages. + */ +#define IPMI_WATCH_MASK_CHECK_MESSAGES (1 << 0) +#define IPMI_WATCH_MASK_CHECK_WATCHDOG (1 << 1) +#define IPMI_WATCH_MASK_CHECK_COMMANDS (1 << 2) + /* * Messages to/from the lower layer. The smi interface will take one * of these to send. After the send has occurred and a response has @@ -55,8 +63,10 @@ struct ipmi_smi_msg { int rsp_size; unsigned char rsp[IPMI_MAX_MSG_LENGTH]; - /* Will be called when the system is done with the message - (presumably to free it). */ + /* + * Will be called when the system is done with the message + * (presumably to free it). + */ void (*done)(struct ipmi_smi_msg *msg); }; @@ -105,12 +115,15 @@ struct ipmi_smi_handlers { /* * Called by the upper layer when some user requires that the - * interface watch for events, received messages, watchdog - * pretimeouts, or not. Used by the SMI to know if it should - * watch for these. This may be NULL if the SMI does not - * implement it. + * interface watch for received messages and watchdog + * pretimeouts (basically do a "Get Flags", or not. Used by + * the SMI to know if it should watch for these. This may be + * NULL if the SMI does not implement it. watch_mask is from + * IPMI_WATCH_MASK_xxx above. The interface should run slower + * timeouts for just watchdog checking or faster timeouts when + * waiting for the message queue. */ - void (*set_need_watch)(void *send_info, bool enable); + void (*set_need_watch)(void *send_info, unsigned int watch_mask); /* * Called when flushing all pending messages. diff --git a/include/linux/kernel_stat.h b/include/linux/kernel_stat.h index 7ee2bb43b251a890aae37c56d0ee8edde7012ac5..f7f20cf1bd3b1b997ee331c8a8945a8ef25f2831 100644 --- a/include/linux/kernel_stat.h +++ b/include/linux/kernel_stat.h @@ -73,7 +73,7 @@ extern unsigned int kstat_irqs_usr(unsigned int irq); /* * Number of interrupts per cpu, since bootup */ -static inline unsigned int kstat_cpu_irqs_sum(unsigned int cpu) +static inline unsigned long kstat_cpu_irqs_sum(unsigned int cpu) { return kstat_cpu(cpu).irqs_sum; } diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h index 304e7a0f6b16574192e12477efb3d0ca6de2a62c..08875d2d5649b92a5da093dcc76ca4d46b52ec8d 100644 --- a/include/linux/kprobes.h +++ b/include/linux/kprobes.h @@ -331,6 +331,8 @@ extern int proc_kprobes_optimization_handler(struct ctl_table *table, size_t *length, loff_t *ppos); #endif extern void wait_for_kprobe_optimizer(void); +bool optprobe_queued_unopt(struct optimized_kprobe *op); +bool kprobe_disarmed(struct kprobe *p); #else static inline void wait_for_kprobe_optimizer(void) { } #endif /* CONFIG_OPTPROBES */ diff --git a/include/linux/libata.h b/include/linux/libata.h index 73cd0182452c4462e0f571450edb6993efbb8b42..361a52e418f7815a985e1c1995c7e0c557e1ed67 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -278,6 +278,10 @@ enum { ATA_HOST_PARALLEL_SCAN = (1 << 2), /* Ports on this host can be scanned in parallel */ ATA_HOST_IGNORE_ATA = (1 << 3), /* Ignore ATA devices on this host. */ + ATA_HOST_NO_PART = (1 << 4), /* Host does not support partial */ + ATA_HOST_NO_SSC = (1 << 5), /* Host does not support slumber */ + ATA_HOST_NO_DEVSLP = (1 << 6), /* Host does not support devslp */ + /* bits 24:31 of host->flags are reserved for LLD specific flags */ /* various lengths of time */ @@ -311,7 +315,7 @@ enum { * advised to wait only for the following duration before * doing SRST. */ - ATA_TMOUT_PMP_SRST_WAIT = 5000, + ATA_TMOUT_PMP_SRST_WAIT = 10000, /* When the LPM policy is set to ATA_LPM_MAX_POWER, there might * be a spurious PHY event, so ignore the first PHY event that diff --git a/include/linux/mcb.h b/include/linux/mcb.h index b1a0ad9d23b3070ffb3fd5a8adc07d6330e96739..8052e5f20630ae739ed7ae519564416a20d8de21 100644 --- a/include/linux/mcb.h +++ b/include/linux/mcb.h @@ -66,7 +66,6 @@ static inline struct mcb_bus *to_mcb_bus(struct device *dev) struct mcb_device { struct device dev; struct mcb_bus *bus; - bool is_added; struct mcb_driver *driver; u16 id; int inst; diff --git a/include/linux/mm.h b/include/linux/mm.h index ed09016513d9340426c8d0a6132639f0ac233800..0fd1f73ffb13344ff839bae2b4c27b4e599e2536 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -1499,6 +1499,12 @@ int generic_access_phys(struct vm_area_struct *vma, unsigned long addr, #ifdef CONFIG_SPECULATIVE_PAGE_FAULT static inline void vm_write_begin(struct vm_area_struct *vma) { + /* + * Isolated vma might be freed without exclusive mmap_lock but + * speculative page fault handler still needs to know it was changed. + */ + if (!RB_EMPTY_NODE(&vma->vm_rb)) + WARN_ON_ONCE(!rwsem_is_locked(&(vma->vm_mm)->mmap_sem)); /* * The reads never spins and preemption * disablement is not required. @@ -2564,7 +2570,7 @@ int __must_check write_one_page(struct page *page); void task_dirty_inc(struct task_struct *tsk); /* readahead.c */ -#define VM_MAX_READAHEAD (totalram_pages > 0x100000 ? 512 : 128) /* kbytes */ +#define VM_MAX_READAHEAD 128 /* kbytes */ #define VM_MIN_READAHEAD 16 /* kbytes (includes current page) */ int force_page_cache_readahead(struct address_space *mapping, struct file *filp, diff --git a/include/linux/namei.h b/include/linux/namei.h index f4958974623791d9519e3fc40ca941980832ba0e..472328d02f7571a738681b013bb1d886279815a1 100644 --- a/include/linux/namei.h +++ b/include/linux/namei.h @@ -89,6 +89,7 @@ extern struct dentry *try_lookup_one_len(const char *, struct dentry *, int); extern struct dentry *lookup_one_len(const char *, struct dentry *, int); extern struct dentry *lookup_one_len2(const char *, struct vfsmount *mnt, struct dentry *, int); extern struct dentry *lookup_one_len_unlocked(const char *, struct dentry *, int); +extern struct dentry *lookup_positive_unlocked(const char *, struct dentry *, int); extern int follow_down_one(struct path *); extern int follow_down(struct path *); diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 584fc71a6352ae674643d82368b23abc6c58b1fa..1beafdd15b813609a9a8279edc078e3c787a0245 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -261,9 +261,11 @@ struct hh_cache { * relationship HH alignment <= LL alignment. */ #define LL_RESERVED_SPACE(dev) \ - ((((dev)->hard_header_len+(dev)->needed_headroom)&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) + ((((dev)->hard_header_len + READ_ONCE((dev)->needed_headroom)) \ + & ~(HH_DATA_MOD - 1)) + HH_DATA_MOD) #define LL_RESERVED_SPACE_EXTRA(dev,extra) \ - ((((dev)->hard_header_len+(dev)->needed_headroom+(extra))&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) + ((((dev)->hard_header_len + READ_ONCE((dev)->needed_headroom) + (extra)) \ + & ~(HH_DATA_MOD - 1)) + HH_DATA_MOD) struct header_ops { int (*create) (struct sk_buff *skb, struct net_device *dev, @@ -706,8 +708,11 @@ static inline void rps_record_sock_flow(struct rps_sock_flow_table *table, /* We only give a hint, preemption can change CPU under us */ val |= raw_smp_processor_id(); - if (table->ents[index] != val) - table->ents[index] = val; + /* The following WRITE_ONCE() is paired with the READ_ONCE() + * here, and another one in get_rps_cpu(). + */ + if (READ_ONCE(table->ents[index]) != val) + WRITE_ONCE(table->ents[index], val); } } @@ -1682,7 +1687,6 @@ enum netdev_priv_flags { * @tipc_ptr: TIPC specific data * @atalk_ptr: AppleTalk link * @ip_ptr: IPv4 specific data - * @dn_ptr: DECnet specific data * @ip6_ptr: IPv6 specific data * @ax25_ptr: AX.25 specific data * @ieee80211_ptr: IEEE 802.11 specific data, assign before registering @@ -1926,9 +1930,6 @@ struct net_device { void *atalk_ptr; #endif struct in_device __rcu *ip_ptr; -#if IS_ENABLED(CONFIG_DECNET) - struct dn_dev __rcu *dn_ptr; -#endif struct inet6_dev __rcu *ip6_ptr; #if IS_ENABLED(CONFIG_AX25) void *ax25_ptr; @@ -3697,7 +3698,7 @@ static __always_inline int ____dev_forward_skb(struct net_device *dev, return NET_RX_DROP; } - skb_scrub_packet(skb, true); + skb_scrub_packet(skb, !net_eq(dev_net(dev), dev_net(skb->dev))); skb->priority = 0; return 0; } @@ -4122,6 +4123,24 @@ void __hw_addr_unsync_dev(struct netdev_hw_addr_list *list, void __hw_addr_init(struct netdev_hw_addr_list *list); /* Functions used for device addresses handling */ +static inline void +__dev_addr_set(struct net_device *dev, const u8 *addr, size_t len) +{ + memcpy(dev->dev_addr, addr, len); +} + +static inline void dev_addr_set(struct net_device *dev, const u8 *addr) +{ + __dev_addr_set(dev, addr, dev->addr_len); +} + +static inline void +dev_addr_mod(struct net_device *dev, unsigned int offset, + const u8 *addr, size_t len) +{ + memcpy(&dev->dev_addr[offset], addr, len); +} + int dev_addr_add(struct net_device *dev, const unsigned char *addr, unsigned char addr_type); int dev_addr_del(struct net_device *dev, const unsigned char *addr, diff --git a/include/linux/netfilter.h b/include/linux/netfilter.h index 9460a5635c90b9f8de9fbee05c2a9f22b6c9bacb..c6a3080c965dfd524b7b80ad7c85199347af71b1 100644 --- a/include/linux/netfilter.h +++ b/include/linux/netfilter.h @@ -225,11 +225,6 @@ static inline int nf_hook(u_int8_t pf, unsigned int hook, struct net *net, hook_head = rcu_dereference(net->nf.hooks_bridge[hook]); #endif break; -#if IS_ENABLED(CONFIG_DECNET) - case NFPROTO_DECNET: - hook_head = rcu_dereference(net->nf.hooks_decnet[hook]); - break; -#endif default: WARN_ON_ONCE(1); break; diff --git a/include/linux/netfilter/nfnetlink.h b/include/linux/netfilter/nfnetlink.h index e713476ff29db29df6cc79356d0b07f4a22014e8..de206e410ee23893fe551398c33cf6c979819eee 100644 --- a/include/linux/netfilter/nfnetlink.h +++ b/include/linux/netfilter/nfnetlink.h @@ -32,7 +32,6 @@ struct nfnetlink_subsystem { struct module *owner; int (*commit)(struct net *net, struct sk_buff *skb); int (*abort)(struct net *net, struct sk_buff *skb); - void (*cleanup)(struct net *net); bool (*valid_genid)(struct net *net, u32 genid); }; @@ -50,6 +49,33 @@ static inline u16 nfnl_msg_type(u8 subsys, u8 msg_type) return subsys << 8 | msg_type; } +static inline void nfnl_fill_hdr(struct nlmsghdr *nlh, u8 family, u8 version, + __be16 res_id) +{ + struct nfgenmsg *nfmsg; + + nfmsg = nlmsg_data(nlh); + nfmsg->nfgen_family = family; + nfmsg->version = version; + nfmsg->res_id = res_id; +} + +static inline struct nlmsghdr *nfnl_msg_put(struct sk_buff *skb, u32 portid, + u32 seq, int type, int flags, + u8 family, u8 version, + __be16 res_id) +{ + struct nlmsghdr *nlh; + + nlh = nlmsg_put(skb, portid, seq, type, sizeof(struct nfgenmsg), flags); + if (!nlh) + return NULL; + + nfnl_fill_hdr(nlh, family, version, res_id); + + return nlh; +} + void nfnl_lock(__u8 subsys_id); void nfnl_unlock(__u8 subsys_id); #ifdef CONFIG_PROVE_LOCKING diff --git a/include/linux/netfilter_defs.h b/include/linux/netfilter_defs.h index 8dddfb151f004bb4adf402dcedde3a3f4454b7f0..a5f7bef1b3a47e7082234be8f3816d356cfae3fa 100644 --- a/include/linux/netfilter_defs.h +++ b/include/linux/netfilter_defs.h @@ -7,14 +7,6 @@ /* in/out/forward only */ #define NF_ARP_NUMHOOKS 3 -/* max hook is NF_DN_ROUTE (6), also see uapi/linux/netfilter_decnet.h */ -#define NF_DN_NUMHOOKS 7 - -#if IS_ENABLED(CONFIG_DECNET) -/* Largest hook number + 1, see uapi/linux/netfilter_decnet.h */ -#define NF_MAX_HOOKS NF_DN_NUMHOOKS -#else #define NF_MAX_HOOKS NF_INET_NUMHOOKS -#endif #endif diff --git a/include/linux/nls.h b/include/linux/nls.h index 499e486b3722d48746c4e4d44cae4ce7a18dfc8a..e0bf8367b274a3d754f77e6864fc87ba274b838e 100644 --- a/include/linux/nls.h +++ b/include/linux/nls.h @@ -47,7 +47,7 @@ enum utf16_endian { /* nls_base.c */ extern int __register_nls(struct nls_table *, struct module *); extern int unregister_nls(struct nls_table *); -extern struct nls_table *load_nls(char *); +extern struct nls_table *load_nls(const char *charset); extern void unload_nls(struct nls_table *); extern struct nls_table *load_nls_default(void); #define register_nls(nls) __register_nls((nls), THIS_MODULE) diff --git a/include/linux/nmi.h b/include/linux/nmi.h index ca96ccb61dcd55ad9b16ccf6fbfef463a97ab47c..e2f62fc94086c5debe36645ef80762b73049d6b6 100644 --- a/include/linux/nmi.h +++ b/include/linux/nmi.h @@ -214,7 +214,7 @@ u64 hw_nmi_get_sample_period(int watchdog_thresh); #endif #if defined(CONFIG_HARDLOCKUP_CHECK_TIMESTAMP) && \ - defined(CONFIG_HARDLOCKUP_DETECTOR) + defined(CONFIG_HARDLOCKUP_DETECTOR_PERF) void watchdog_update_hrtimer_threshold(u64 period); #else static inline void watchdog_update_hrtimer_threshold(u64 period) { } diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h index 7c4b8e27268c7455c9f13234d0d2790dfb46dfc4..1ebb88e7c184c9ce4246b043dfaf08cd00ba9357 100644 --- a/include/linux/pci-ats.h +++ b/include/linux/pci-ats.h @@ -40,6 +40,7 @@ void pci_disable_pasid(struct pci_dev *pdev); void pci_restore_pasid_state(struct pci_dev *pdev); int pci_pasid_features(struct pci_dev *pdev); int pci_max_pasids(struct pci_dev *pdev); +int pci_prg_resp_pasid_required(struct pci_dev *pdev); #else /* CONFIG_PCI_PASID */ @@ -66,6 +67,10 @@ static inline int pci_max_pasids(struct pci_dev *pdev) return -EINVAL; } +static inline int pci_prg_resp_pasid_required(struct pci_dev *pdev) +{ + return 0; +} #endif /* CONFIG_PCI_PASID */ diff --git a/include/linux/pci.h b/include/linux/pci.h index b56ad12977ec43aceb4feecf5b350e1dccdb651f..f3a42e76418f5538cae58237acbf75a9f6ca49e4 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -261,6 +261,7 @@ enum pci_bus_speed { PCIE_SPEED_5_0GT = 0x15, PCIE_SPEED_8_0GT = 0x16, PCIE_SPEED_16_0GT = 0x17, + PCIE_SPEED_32_0GT = 0x18, PCI_SPEED_UNKNOWN = 0xff, }; @@ -1656,6 +1657,7 @@ static inline struct pci_dev *pci_get_class(unsigned int class, #define pci_dev_put(dev) do { } while (0) static inline void pci_set_master(struct pci_dev *dev) { } +static inline void pci_clear_master(struct pci_dev *dev) { } static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } static inline void pci_disable_device(struct pci_dev *dev) { } static inline int pci_assign_resource(struct pci_dev *dev, int i) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 1658e9f8d8032fe4f64969b31faeac4afdea950e..76d5490231a75e7cf5c06d3a45715ebb2a471801 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -553,6 +553,7 @@ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443 +#define PCI_DEVICE_ID_AMD_VANGOGH_USB 0x163a #define PCI_DEVICE_ID_AMD_19H_DF_F3 0x1653 #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703 #define PCI_DEVICE_ID_AMD_LANCE 0x2000 @@ -3097,6 +3098,8 @@ #define PCI_VENDOR_ID_3COM_2 0xa727 +#define PCI_VENDOR_ID_SOLIDRUN 0xd063 + #define PCI_VENDOR_ID_DIGIUM 0xd161 #define PCI_DEVICE_ID_DIGIUM_HFC4S 0xb410 diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 83b667fd57043f4c8426d524a41016be4d23de2c..fc9ceace2931f27d95b14446def27f7f3c129fc6 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -597,13 +597,10 @@ struct perf_event { /* The cumulative AND of all event_caps for events in this group. */ int group_caps; +#ifndef __GENKSYMS__ /* ANDROID Bug: 307236803 to keep the crc preserved */ + unsigned int group_generation; +#endif struct perf_event *group_leader; - - /* - * Protect the pmu, attributes and context of a group leader. - * Note: does not protect the pointer to the group_leader. - */ - struct mutex group_leader_mutex; struct pmu *pmu; void *pmu_private; @@ -1016,15 +1013,31 @@ extern void perf_event_output(struct perf_event *event, struct pt_regs *regs); static inline bool -is_default_overflow_handler(struct perf_event *event) +__is_default_overflow_handler(perf_overflow_handler_t overflow_handler) { - if (likely(event->overflow_handler == perf_event_output_forward)) + if (likely(overflow_handler == perf_event_output_forward)) return true; - if (unlikely(event->overflow_handler == perf_event_output_backward)) + if (unlikely(overflow_handler == perf_event_output_backward)) return true; return false; } +#define is_default_overflow_handler(event) \ + __is_default_overflow_handler((event)->overflow_handler) + +#ifdef CONFIG_BPF_SYSCALL +static inline bool uses_default_overflow_handler(struct perf_event *event) +{ + if (likely(is_default_overflow_handler(event))) + return true; + + return __is_default_overflow_handler(event->orig_overflow_handler); +} +#else +#define uses_default_overflow_handler(event) \ + is_default_overflow_handler(event) +#endif + extern void perf_event_header__init_id(struct perf_event_header *header, struct perf_sample_data *data, diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index 1a9f38f27f65649c3fe4c4ca67e7880b3e1c5e1a..3ad24c6832e60433b45ca3364dfa22890d95cf74 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -29,7 +29,11 @@ struct platform_device { struct resource *resource; const struct platform_device_id *id_entry; - char *driver_override; /* Driver name to force a match */ + /* + * Driver name to force a match. Do not set directly, because core + * frees it. Use driver_set_override() to set or clear it. + */ + char *driver_override; /* MFD cell pointer */ struct mfd_cell *mfd_cell; @@ -51,6 +55,9 @@ extern struct device platform_bus; extern void arch_setup_pdev_archdata(struct platform_device *); extern struct resource *platform_get_resource(struct platform_device *, unsigned int, unsigned int); +extern void __iomem * +devm_platform_ioremap_resource(struct platform_device *pdev, + unsigned int index); extern int platform_get_irq(struct platform_device *, unsigned int); extern int platform_irq_count(struct platform_device *); extern struct resource *platform_get_resource_byname(struct platform_device *, diff --git a/include/linux/pm_wakeirq.h b/include/linux/pm_wakeirq.h index cd5b62db908454dc7f7fe2acc9479c467e1a1f67..e63a63aa47a374d27a5cc9da1ce96d7593036d5f 100644 --- a/include/linux/pm_wakeirq.h +++ b/include/linux/pm_wakeirq.h @@ -17,8 +17,8 @@ #ifdef CONFIG_PM extern int dev_pm_set_wake_irq(struct device *dev, int irq); -extern int dev_pm_set_dedicated_wake_irq(struct device *dev, - int irq); +extern int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq); +extern int dev_pm_set_dedicated_wake_irq_reverse(struct device *dev, int irq); extern void dev_pm_clear_wake_irq(struct device *dev); extern void dev_pm_enable_wake_irq(struct device *dev); extern void dev_pm_disable_wake_irq(struct device *dev); @@ -35,6 +35,11 @@ static inline int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq) return 0; } +static inline int dev_pm_set_dedicated_wake_irq_reverse(struct device *dev, int irq) +{ + return 0; +} + static inline void dev_pm_clear_wake_irq(struct device *dev) { } diff --git a/include/linux/power/bq27xxx_battery.h b/include/linux/power/bq27xxx_battery.h index 13d5dd4eb40b44436ca006b91806286764400a3b..95a8715624ed9d6636dc052bf25cc17650414347 100644 --- a/include/linux/power/bq27xxx_battery.h +++ b/include/linux/power/bq27xxx_battery.h @@ -63,6 +63,7 @@ struct bq27xxx_device_info { struct bq27xxx_access_methods bus; struct bq27xxx_reg_cache cache; int charge_design_full; + bool removed; unsigned long last_update; struct delayed_work work; struct power_supply *bat; diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index 452eb56184d648aaf195c19653c1b63b6f29af58..4c277a9b98cdd7368b55e947ca6e4ba462210ecc 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -696,8 +696,9 @@ extern int power_supply_get_battery_info(struct power_supply *psy, struct power_supply_battery_info *info); extern void power_supply_changed(struct power_supply *psy); extern int power_supply_am_i_supplied(struct power_supply *psy); -extern int power_supply_set_input_current_limit_from_supplier( - struct power_supply *psy); +int power_supply_get_property_from_supplier(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val); extern int power_supply_set_battery_charged(struct power_supply *psy); #ifdef CONFIG_POWER_SUPPLY diff --git a/include/linux/preempt.h b/include/linux/preempt.h index c01813c3fbe9336ed69a54a0296ed7bb69186a5f..abeec72b4d3595fc85cad120ce9fdebacb49387a 100644 --- a/include/linux/preempt.h +++ b/include/linux/preempt.h @@ -325,4 +325,34 @@ static inline void preempt_notifier_init(struct preempt_notifier *notifier, #endif +/** + * migrate_disable - Prevent migration of the current task + * + * Maps to preempt_disable() which also disables preemption. Use + * migrate_disable() to annotate that the intent is to prevent migration, + * but not necessarily preemption. + * + * Can be invoked nested like preempt_disable() and needs the corresponding + * number of migrate_enable() invocations. + */ +static __always_inline void migrate_disable(void) +{ + preempt_disable(); +} + +/** + * migrate_enable - Allow migration of the current task + * + * Counterpart to migrate_disable(). + * + * As migrate_disable() can be invoked nested, only the outermost invocation + * reenables migration. + * + * Currently mapped to preempt_enable(). + */ +static __always_inline void migrate_enable(void) +{ + preempt_enable(); +} + #endif /* __LINUX_PREEMPT_H */ diff --git a/include/linux/printk.h b/include/linux/printk.h index d3195ea1cc2cb8f080862c663f7e56dfb382a8e6..55814bd9b16502b6b6e700555e82e4e0e29eb9f1 100644 --- a/include/linux/printk.h +++ b/include/linux/printk.h @@ -526,4 +526,23 @@ static inline void print_hex_dump_debug(const char *prefix_str, int prefix_type, } #endif +#ifdef CONFIG_PRINTK +extern void __printk_safe_enter(void); +extern void __printk_safe_exit(void); +/* + * The printk_deferred_enter/exit macros are available only as a hack for + * some code paths that need to defer all printk console printing. Interrupts + * must be disabled for the deferred duration. + */ +#define printk_deferred_enter __printk_safe_enter +#define printk_deferred_exit __printk_safe_exit +#else +static inline void printk_deferred_enter(void) +{ +} +static inline void printk_deferred_exit(void) +{ +} +#endif + #endif diff --git a/include/linux/pwm.h b/include/linux/pwm.h index 40bdb16daabf24faef4cb9c16c8b0fd0afc0fb92..b59f09a49dcd2ca4def7b2e67d54dbad99806ca4 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -44,8 +44,8 @@ struct pwm_args { }; enum { - PWMF_REQUESTED = 1 << 0, - PWMF_EXPORTED = 1 << 1, + PWMF_REQUESTED = 0, + PWMF_EXPORTED = 1, }; /** diff --git a/include/linux/quota.h b/include/linux/quota.h index 3088ac929e56260c443f6a276b2e2e5e5a8b923e..17a67cf0d1093bee6f4dcf5137ce34392b5736cf 100644 --- a/include/linux/quota.h +++ b/include/linux/quota.h @@ -285,7 +285,9 @@ static inline void dqstats_dec(unsigned int type) #define DQ_FAKE_B 3 /* no limits only usage */ #define DQ_READ_B 4 /* dquot was read into memory */ #define DQ_ACTIVE_B 5 /* dquot is active (dquot_release not called) */ -#define DQ_LASTSET_B 6 /* Following 6 bits (see QIF_) are reserved\ +#define DQ_RELEASING_B 6 /* dquot is in releasing_dquots list waiting + * to be cleaned up */ +#define DQ_LASTSET_B 7 /* Following 6 bits (see QIF_) are reserved\ * for the mask of entries set via SETQUOTA\ * quotactl. They are set under dq_data_lock\ * and the quota format handling dquot can\ diff --git a/include/linux/quotaops.h b/include/linux/quotaops.h index ec10897f7f60c2e4902946b4006a7f3f13e548b5..844b5836d11d6ca99f35833a10bd2307fd345699 100644 --- a/include/linux/quotaops.h +++ b/include/linux/quotaops.h @@ -59,7 +59,7 @@ static inline bool dquot_is_busy(struct dquot *dquot) { if (test_bit(DQ_MOD_B, &dquot->dq_flags)) return true; - if (atomic_read(&dquot->dq_count) > 1) + if (atomic_read(&dquot->dq_count) > 0) return true; return false; } diff --git a/include/linux/raid_class.h b/include/linux/raid_class.h index ec8655514283ec722f2bdd1360e1435be24dca7d..c868bb927c3d7cfdbf35723c724dd54c1088b536 100644 --- a/include/linux/raid_class.h +++ b/include/linux/raid_class.h @@ -78,7 +78,3 @@ DEFINE_RAID_ATTRIBUTE(enum raid_state, state) struct raid_template *raid_class_attach(struct raid_function_template *); void raid_class_release(struct raid_template *); - -int __must_check raid_component_add(struct raid_template *, struct device *, - struct device *); - diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h index 68cbe111420bc05b698eb192c5f6c5191325829e..cf139d6e5c1d35db8801704a99b06609d7ee4d04 100644 --- a/include/linux/rcupdate.h +++ b/include/linux/rcupdate.h @@ -410,6 +410,24 @@ static inline void rcu_preempt_sleep_check(void) { } _r_a_p__v; \ }) +/** + * rcu_replace_pointer() - replace an RCU pointer, returning its old value + * @rcu_ptr: RCU pointer, whose old value is returned + * @ptr: regular pointer + * @c: the lockdep conditions under which the dereference will take place + * + * Perform a replacement, where @rcu_ptr is an RCU-annotated + * pointer and @c is the lockdep argument that is passed to the + * rcu_dereference_protected() call used to read that pointer. The old + * value of @rcu_ptr is returned, and @rcu_ptr is set to @ptr. + */ +#define rcu_replace_pointer(rcu_ptr, ptr, c) \ +({ \ + typeof(ptr) __tmp = rcu_dereference_protected((rcu_ptr), (c)); \ + rcu_assign_pointer((rcu_ptr), (ptr)); \ + __tmp; \ +}) + /** * rcu_swap_protected() - swap an RCU and a regular pointer * @rcu_ptr: RCU pointer diff --git a/include/linux/rmap.h b/include/linux/rmap.h index c10fe5c6118d30ffc910c293d3fd2d151aefb699..7aedd60e730e4342c7b649732f4638f290405a61 100644 --- a/include/linux/rmap.h +++ b/include/linux/rmap.h @@ -48,13 +48,7 @@ struct anon_vma { */ atomic_t refcount; - /* - * Count of child anon_vmas and VMAs which points to this anon_vma. - * - * This counter is used for making decision about reusing anon_vma - * instead of forking new one. See comments in function anon_vma_clone. - */ - unsigned degree; + unsigned degree; /* ANDROID: KABI preservation, DO NOT USE! */ struct anon_vma *parent; /* Parent of this anon_vma */ @@ -69,6 +63,25 @@ struct anon_vma { /* Interval tree of private "related" vmas */ struct rb_root_cached rb_root; + + /* + * ANDROID: KABI preservation, it's safe to put these at the end of this structure as it's + * only passed by a pointer everywhere, the size and internal structures are local to the + * core kernel. + */ +#ifndef __GENKSYMS__ + /* + * Count of child anon_vmas. Equals to the count of all anon_vmas that + * have ->parent pointing to this one, including itself. + * + * This counter is used for making decision about reusing anon_vma + * instead of forking new one. See comments in function anon_vma_clone. + */ + unsigned long num_children; + /* Count of VMAs whose ->anon_vma pointer points to this object. */ + unsigned long num_active_vmas; +#endif + }; /* diff --git a/include/linux/rpmsg.h b/include/linux/rpmsg.h index edd80527e77bd6fb247b43020d310b2c3531306c..7756698cbabd0128ba0914c64cc64c9411bbbbbc 100644 --- a/include/linux/rpmsg.h +++ b/include/linux/rpmsg.h @@ -42,7 +42,9 @@ struct rpmsg_channel_info { * rpmsg_device - device that belong to the rpmsg bus * @dev: the device struct * @id: device id (used to match between rpmsg drivers and devices) - * @driver_override: driver name to force a match + * @driver_override: driver name to force a match; do not set directly, + * because core frees it; use driver_set_override() to + * set or clear it. * @src: local address * @dst: destination address * @ept: the rpmsg endpoint of this channel @@ -51,7 +53,7 @@ struct rpmsg_channel_info { struct rpmsg_device { struct device dev; struct rpmsg_device_id id; - char *driver_override; + const char *driver_override; u32 src; u32 dst; struct rpmsg_endpoint *ept; @@ -119,6 +121,8 @@ struct rpmsg_driver { #if IS_ENABLED(CONFIG_RPMSG) +int rpmsg_register_device_override(struct rpmsg_device *rpdev, + const char *driver_override); int register_rpmsg_device(struct rpmsg_device *dev); void unregister_rpmsg_device(struct rpmsg_device *dev); int __register_rpmsg_driver(struct rpmsg_driver *drv, struct module *owner); @@ -146,6 +150,12 @@ int rpmsg_set_sigs(struct rpmsg_endpoint *ept, u32 sigs); #else +static inline int rpmsg_register_device_override(struct rpmsg_device *rpdev, + const char *driver_override) +{ + return -ENXIO; +} + static inline int register_rpmsg_device(struct rpmsg_device *dev) { return -ENXIO; diff --git a/include/linux/sched/task_stack.h b/include/linux/sched/task_stack.h index 4f099d3fed3a9ff412680f6b721508de7033d486..f1063380e6d8a9bc653a5c8e555246df592f9f6c 100644 --- a/include/linux/sched/task_stack.h +++ b/include/linux/sched/task_stack.h @@ -23,7 +23,7 @@ static inline void *task_stack_page(const struct task_struct *task) #define setup_thread_stack(new,old) do { } while(0) -static inline unsigned long *end_of_stack(const struct task_struct *task) +static __always_inline unsigned long *end_of_stack(const struct task_struct *task) { #ifdef CONFIG_STACK_GROWSUP return (unsigned long *)((unsigned long)task->stack + THREAD_SIZE) - 1; diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h index 5a655ba8d27307a491294bd944da1cf3613502e5..bfde7f1a7674dd0ec37a8a050a2fa86c7bcaf0de 100644 --- a/include/linux/serial_8250.h +++ b/include/linux/serial_8250.h @@ -99,7 +99,6 @@ struct uart_8250_port { struct list_head list; /* ports on this IRQ */ u32 capabilities; /* port capabilities */ unsigned short bugs; /* port bugs */ - bool fifo_bug; /* min RX trigger if enabled */ unsigned int tx_loadsz; /* transmit fifo load size */ unsigned char acr; unsigned char fcr; diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h index c255273b02810ebc1b9fcd9e517f87478bda2636..37ad81058d6aedfd86667e2f54e8e8b401fbff8f 100644 --- a/include/linux/sh_intc.h +++ b/include/linux/sh_intc.h @@ -97,7 +97,10 @@ struct intc_hw_desc { unsigned int nr_subgroups; }; -#define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : sizeof(a)/sizeof(*a) +#define _INTC_SIZEOF_OR_ZERO(a) (_Generic(a, \ + typeof(NULL): 0, \ + default: sizeof(a))) +#define _INTC_ARRAY(a) a, _INTC_SIZEOF_OR_ZERO(a)/sizeof(*a) #define INTC_HW_DESC(vectors, groups, mask_regs, \ prio_regs, sense_regs, ack_regs) \ diff --git a/include/linux/string_helpers.h b/include/linux/string_helpers.h index d23c5030901a2fe91a436a1e449273a543e015ca..0618885b3edc759bccffcd728c574d2c245846f8 100644 --- a/include/linux/string_helpers.h +++ b/include/linux/string_helpers.h @@ -2,6 +2,7 @@ #ifndef _LINUX_STRING_HELPERS_H_ #define _LINUX_STRING_HELPERS_H_ +#include #include struct file; @@ -72,6 +73,20 @@ static inline int string_escape_str_any_np(const char *src, char *dst, return string_escape_str(src, dst, sz, ESCAPE_ANY_NP, only); } +static inline void string_upper(char *dst, const char *src) +{ + do { + *dst++ = toupper(*src); + } while (*src++); +} + +static inline void string_lower(char *dst, const char *src) +{ + do { + *dst++ = tolower(*src); + } while (*src++); +} + char *kstrdup_quotable(const char *src, gfp_t gfp); char *kstrdup_quotable_cmdline(struct task_struct *task, gfp_t gfp); char *kstrdup_quotable_file(struct file *file, gfp_t gfp); diff --git a/include/linux/sunrpc/sched.h b/include/linux/sunrpc/sched.h index ad2e243f3f03202fe46a02c5f636d1e372bbd735..96837ae07822bd7b84e99bbee4505077f77f508e 100644 --- a/include/linux/sunrpc/sched.h +++ b/include/linux/sunrpc/sched.h @@ -88,8 +88,7 @@ struct rpc_task { #endif unsigned char tk_priority : 2,/* Task priority */ tk_garb_retry : 2, - tk_cred_retry : 2, - tk_rebind_retry : 2; + tk_cred_retry : 2; }; typedef void (*rpc_action)(struct rpc_task *); diff --git a/include/linux/tcp.h b/include/linux/tcp.h index 9a843fe1e4db981afc4f19612ddac9823d130cb9..e3b4fd4c7efa5a711907b6a92fcc99bce4548145 100644 --- a/include/linux/tcp.h +++ b/include/linux/tcp.h @@ -461,7 +461,7 @@ static inline void fastopen_queue_tune(struct sock *sk, int backlog) struct request_sock_queue *queue = &inet_csk(sk)->icsk_accept_queue; int somaxconn = READ_ONCE(sock_net(sk)->core.sysctl_somaxconn); - queue->fastopenq.max_qlen = min_t(unsigned int, backlog, somaxconn); + WRITE_ONCE(queue->fastopenq.max_qlen, min_t(unsigned int, backlog, somaxconn)); } static inline void tcp_move_syn(struct tcp_sock *tp, diff --git a/include/linux/tick.h b/include/linux/tick.h index 9e99133a6000a91be8e2877e5201c297dc5735a9..3382057e390f90f6bb575213406aa066a65d1a50 100644 --- a/include/linux/tick.h +++ b/include/linux/tick.h @@ -102,7 +102,8 @@ enum tick_dep_bits { TICK_DEP_BIT_POSIX_TIMER = 0, TICK_DEP_BIT_PERF_EVENTS = 1, TICK_DEP_BIT_SCHED = 2, - TICK_DEP_BIT_CLOCK_UNSTABLE = 3 + TICK_DEP_BIT_CLOCK_UNSTABLE = 3, + TICK_DEP_BIT_RCU = 4 }; #define TICK_DEP_MASK_NONE 0 @@ -110,6 +111,7 @@ enum tick_dep_bits { #define TICK_DEP_MASK_PERF_EVENTS (1 << TICK_DEP_BIT_PERF_EVENTS) #define TICK_DEP_MASK_SCHED (1 << TICK_DEP_BIT_SCHED) #define TICK_DEP_MASK_CLOCK_UNSTABLE (1 << TICK_DEP_BIT_CLOCK_UNSTABLE) +#define TICK_DEP_MASK_RCU (1 << TICK_DEP_BIT_RCU) extern void register_tick_sched_wakeup_callback(void (*cb)(void)); @@ -197,6 +199,7 @@ extern void tick_nohz_dep_set_signal(struct signal_struct *signal, enum tick_dep_bits bit); extern void tick_nohz_dep_clear_signal(struct signal_struct *signal, enum tick_dep_bits bit); +extern bool tick_nohz_cpu_hotpluggable(unsigned int cpu); /* * The below are tick_nohz_[set,clear]_dep() wrappers that optimize off-cases @@ -259,6 +262,10 @@ static inline bool tick_nohz_full_enabled(void) { return false; } static inline bool tick_nohz_full_cpu(int cpu) { return false; } static inline void tick_nohz_full_add_cpus_to(struct cpumask *mask) { } +static inline void tick_nohz_dep_set_cpu(int cpu, enum tick_dep_bits bit) { } +static inline void tick_nohz_dep_clear_cpu(int cpu, enum tick_dep_bits bit) { } +static inline bool tick_nohz_cpu_hotpluggable(unsigned int cpu) { return true; } + static inline void tick_dep_set(enum tick_dep_bits bit) { } static inline void tick_dep_clear(enum tick_dep_bits bit) { } static inline void tick_dep_set_cpu(int cpu, enum tick_dep_bits bit) { } diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h index dabb1e5e0bfdae6626a4456a0354065a54b0d356..6797f1d3d7a9995b09120dcd1dd305c2c42491e3 100644 --- a/include/linux/trace_events.h +++ b/include/linux/trace_events.h @@ -583,7 +583,8 @@ extern int perf_uprobe_init(struct perf_event *event, bool is_retprobe); extern void perf_uprobe_destroy(struct perf_event *event); extern int bpf_get_uprobe_info(const struct perf_event *event, u32 *fd_type, const char **filename, - u64 *probe_offset, bool perf_type_tracepoint); + u64 *probe_offset, u64 *probe_addr, + bool perf_type_tracepoint); #endif extern int ftrace_profile_set_filter(struct perf_event *event, int event_id, char *filter_str); diff --git a/include/linux/tracepoint.h b/include/linux/tracepoint.h index 4251cbfdb3c8c8a0ab1c1d5764d34e8657d0cb44..bff2f76aeff72a5e52acb8297ee3f141a30cbee6 100644 --- a/include/linux/tracepoint.h +++ b/include/linux/tracepoint.h @@ -233,12 +233,11 @@ static inline struct tracepoint *tracepoint_ptr_deref(tracepoint_ptr_t *p) * not add unwanted padding between the beginning of the section and the * structure. Force alignment to the same alignment as the section start. * - * When lockdep is enabled, we make sure to always do the RCU portions of - * the tracepoint code, regardless of whether tracing is on. However, - * don't check if the condition is false, due to interaction with idle - * instrumentation. This lets us find RCU issues triggered with tracepoints - * even when this tracepoint is off. This code has no purpose other than - * poking RCU a bit. + * When lockdep is enabled, we make sure to always test if RCU is + * "watching" regardless if the tracepoint is enabled or not. Tracepoints + * require RCU to be active, and it should always warn at the tracepoint + * site if it is not watching, as it will need to be active when the + * tracepoint is enabled. */ #define __DECLARE_TRACE(name, proto, args, cond, data_proto, data_args) \ extern struct tracepoint __tracepoint_##name; \ @@ -250,9 +249,7 @@ static inline struct tracepoint *tracepoint_ptr_deref(tracepoint_ptr_t *p) TP_ARGS(data_args), \ TP_CONDITION(cond), 0); \ if (IS_ENABLED(CONFIG_LOCKDEP) && (cond)) { \ - rcu_read_lock_sched_notrace(); \ - rcu_dereference_sched(__tracepoint_##name.funcs);\ - rcu_read_unlock_sched_notrace(); \ + WARN_ON_ONCE(!rcu_is_watching()); \ } \ } \ __DECLARE_TRACE_RCU(name, PARAMS(proto), PARAMS(args), \ diff --git a/include/linux/tty.h b/include/linux/tty.h index a75926ab316ecc7687f72d713860370d02c804e6..d30ad44af6d143f69c2e60e10b6ea739c73e8baa 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -484,6 +484,8 @@ extern void __stop_tty(struct tty_struct *tty); extern void stop_tty(struct tty_struct *tty); extern void __start_tty(struct tty_struct *tty); extern void start_tty(struct tty_struct *tty); +void tty_write_unlock(struct tty_struct *tty); +int tty_write_lock(struct tty_struct *tty, int ndelay); extern int tty_register_driver(struct tty_driver *driver); extern int tty_unregister_driver(struct tty_driver *driver); extern struct device *tty_register_device(struct tty_driver *driver, diff --git a/include/linux/usb.h b/include/linux/usb.h index 7f10330633088bd05475f1d2ec72769de5eecc2a..cedaa8937971044887af0566c7f237b9e1ddf59b 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -285,6 +285,11 @@ void usb_put_intf(struct usb_interface *intf); #define USB_MAXINTERFACES 32 #define USB_MAXIADS (USB_MAXINTERFACES/2) +bool usb_check_bulk_endpoints( + const struct usb_interface *intf, const u8 *ep_addrs); +bool usb_check_int_endpoints( + const struct usb_interface *intf, const u8 *ep_addrs); + /* * USB Resume Timer: Every Host controller driver should drive the resume * signalling on the bus for the amount of time defined by this macro. diff --git a/include/linux/usb/cdc_ncm.h b/include/linux/usb/cdc_ncm.h index 1646c06989df7cf7a6eeb87c37efe6e31592777b..0ce4377545f82cd19b35f7fdaa9b4354ad67bed7 100644 --- a/include/linux/usb/cdc_ncm.h +++ b/include/linux/usb/cdc_ncm.h @@ -46,9 +46,12 @@ #define CDC_NCM_DATA_ALTSETTING_NCM 1 #define CDC_NCM_DATA_ALTSETTING_MBIM 2 -/* CDC NCM subclass 3.2.1 */ +/* CDC NCM subclass 3.3.1 */ #define USB_CDC_NCM_NDP16_LENGTH_MIN 0x10 +/* CDC NCM subclass 3.3.2 */ +#define USB_CDC_NCM_NDP32_LENGTH_MIN 0x20 + /* Maximum NTB length */ #define CDC_NCM_NTB_MAX_SIZE_TX 32768 /* bytes */ #define CDC_NCM_NTB_MAX_SIZE_RX 32768 /* bytes */ @@ -84,7 +87,7 @@ /* Driver flags */ #define CDC_NCM_FLAG_NDP_TO_END 0x02 /* NDP is placed at end of frame */ #define CDC_MBIM_FLAG_AVOID_ALTSETTING_TOGGLE 0x04 /* Avoid altsetting toggle during init */ -#define CDC_NCM_FLAG_RESET_NTB16 0x08 /* set NDP16 one more time after altsetting switch */ +#define CDC_NCM_FLAG_PREFER_NTB32 0x08 /* prefer NDP32 over NDP16 */ #define cdc_ncm_comm_intf_is_mbim(x) ((x)->desc.bInterfaceSubClass == USB_CDC_SUBCLASS_MBIM && \ (x)->desc.bInterfaceProtocol == USB_CDC_PROTO_NONE) @@ -113,7 +116,11 @@ struct cdc_ncm_ctx { u32 timer_interval; u32 max_ndp_size; - struct usb_cdc_ncm_ndp16 *delayed_ndp16; + u8 is_ndp16; + union { + struct usb_cdc_ncm_ndp16 *delayed_ndp16; + struct usb_cdc_ncm_ndp32 *delayed_ndp32; + }; u32 tx_timer_pending; u32 tx_curr_frame_num; @@ -150,6 +157,8 @@ void cdc_ncm_unbind(struct usbnet *dev, struct usb_interface *intf); struct sk_buff *cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign); int cdc_ncm_rx_verify_nth16(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in); int cdc_ncm_rx_verify_ndp16(struct sk_buff *skb_in, int ndpoffset); +int cdc_ncm_rx_verify_nth32(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in); +int cdc_ncm_rx_verify_ndp32(struct sk_buff *skb_in, int ndpoffset); struct sk_buff * cdc_ncm_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags); int cdc_ncm_rx_fixup(struct usbnet *dev, struct sk_buff *skb_in); diff --git a/include/linux/virtio_net.h b/include/linux/virtio_net.h index 0e8ab43f2ef05743f336698094c5e9212a946c10..65b575c90ac107ffad6509e3c173e807e15b73b9 100644 --- a/include/linux/virtio_net.h +++ b/include/linux/virtio_net.h @@ -140,6 +140,10 @@ static inline int virtio_net_hdr_to_skb(struct sk_buff *skb, if (gso_type & SKB_GSO_UDP) nh_off -= thlen; + /* Kernel has a special handling for GSO_BY_FRAGS. */ + if (gso_size == GSO_BY_FRAGS) + return -EINVAL; + /* Too small packets are not really GSO ones. */ if (skb->len - nh_off > gso_size) { shinfo->gso_size = gso_size; diff --git a/include/linux/vt_buffer.h b/include/linux/vt_buffer.h index 848db1b1569ff9be66b4c49e6bd40511aa1a1ef0..919d999a8c1db2e431bc1e238f7be7844d9922e1 100644 --- a/include/linux/vt_buffer.h +++ b/include/linux/vt_buffer.h @@ -16,7 +16,7 @@ #include -#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE) +#if IS_ENABLED(CONFIG_VGA_CONSOLE) || IS_ENABLED(CONFIG_MDA_CONSOLE) #include #endif diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h index b2e3a8f5a54f683fda2c4bb07d28efb73e336712..7b8f609e6a997bc14cfcadc53dce8feb84d0fb3a 100644 --- a/include/linux/workqueue.h +++ b/include/linux/workqueue.h @@ -75,7 +75,6 @@ enum { WORK_OFFQ_FLAG_BASE = WORK_STRUCT_COLOR_SHIFT, __WORK_OFFQ_CANCELING = WORK_OFFQ_FLAG_BASE, - WORK_OFFQ_CANCELING = (1 << __WORK_OFFQ_CANCELING), /* * When a work item is off queue, its high bits point to the last @@ -86,12 +85,6 @@ enum { WORK_OFFQ_POOL_SHIFT = WORK_OFFQ_FLAG_BASE + WORK_OFFQ_FLAG_BITS, WORK_OFFQ_LEFT = BITS_PER_LONG - WORK_OFFQ_POOL_SHIFT, WORK_OFFQ_POOL_BITS = WORK_OFFQ_LEFT <= 31 ? WORK_OFFQ_LEFT : 31, - WORK_OFFQ_POOL_NONE = (1LU << WORK_OFFQ_POOL_BITS) - 1, - - /* convenience constants */ - WORK_STRUCT_FLAG_MASK = (1UL << WORK_STRUCT_FLAG_BITS) - 1, - WORK_STRUCT_WQ_DATA_MASK = ~WORK_STRUCT_FLAG_MASK, - WORK_STRUCT_NO_POOL = (unsigned long)WORK_OFFQ_POOL_NONE << WORK_OFFQ_POOL_SHIFT, /* bit mask for work_busy() return values */ WORK_BUSY_PENDING = 1 << 0, @@ -101,6 +94,14 @@ enum { WORKER_DESC_LEN = 24, }; +/* Convenience constants - of type 'unsigned long', not 'enum'! */ +#define WORK_OFFQ_CANCELING (1ul << __WORK_OFFQ_CANCELING) +#define WORK_OFFQ_POOL_NONE ((1ul << WORK_OFFQ_POOL_BITS) - 1) +#define WORK_STRUCT_NO_POOL (WORK_OFFQ_POOL_NONE << WORK_OFFQ_POOL_SHIFT) + +#define WORK_STRUCT_FLAG_MASK ((1ul << WORK_STRUCT_FLAG_BITS) - 1) +#define WORK_STRUCT_WQ_DATA_MASK (~WORK_STRUCT_FLAG_MASK) + struct work_struct { atomic_long_t data; struct list_head entry; diff --git a/include/media/dvb_net.h b/include/media/dvb_net.h index 5e31d37f25fac8581f0a6a9c5de90d896e2b3b29..cc01dffcc9f359a0a65ba055c9ecc57acb313c8c 100644 --- a/include/media/dvb_net.h +++ b/include/media/dvb_net.h @@ -41,6 +41,9 @@ * @exit: flag to indicate when the device is being removed. * @demux: pointer to &struct dmx_demux. * @ioctl_mutex: protect access to this struct. + * @remove_mutex: mutex that avoids a race condition between a callback + * called when the hardware is disconnected and the + * file_operations of dvb_net. * * Currently, the core supports up to %DVB_NET_DEVICES_MAX (10) network * devices. @@ -53,6 +56,7 @@ struct dvb_net { unsigned int exit:1; struct dmx_demux *demux; struct mutex ioctl_mutex; + struct mutex remove_mutex; }; /** diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h index d655720e16a1502dbfeb3571412c8a98b489002e..62c67e9e190c0df34709413bb981b09fefe2014d 100644 --- a/include/media/v4l2-mem2mem.h +++ b/include/media/v4l2-mem2mem.h @@ -405,7 +405,14 @@ void v4l2_m2m_buf_queue(struct v4l2_m2m_ctx *m2m_ctx, static inline unsigned int v4l2_m2m_num_src_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx) { - return m2m_ctx->out_q_ctx.num_rdy; + unsigned int num_buf_rdy; + unsigned long flags; + + spin_lock_irqsave(&m2m_ctx->out_q_ctx.rdy_spinlock, flags); + num_buf_rdy = m2m_ctx->out_q_ctx.num_rdy; + spin_unlock_irqrestore(&m2m_ctx->out_q_ctx.rdy_spinlock, flags); + + return num_buf_rdy; } /** @@ -417,7 +424,14 @@ unsigned int v4l2_m2m_num_src_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx) static inline unsigned int v4l2_m2m_num_dst_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx) { - return m2m_ctx->cap_q_ctx.num_rdy; + unsigned int num_buf_rdy; + unsigned long flags; + + spin_lock_irqsave(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags); + num_buf_rdy = m2m_ctx->cap_q_ctx.num_rdy; + spin_unlock_irqrestore(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags); + + return num_buf_rdy; } /** diff --git a/include/net/addrconf.h b/include/net/addrconf.h index ae614b57420f058b7240a05231aeba7e2a26032e..5f94749742f9ee22a81e84b23584e2949b4340b1 100644 --- a/include/net/addrconf.h +++ b/include/net/addrconf.h @@ -352,6 +352,22 @@ static inline struct inet6_dev *__in6_dev_get(const struct net_device *dev) return rcu_dereference_rtnl(dev->ip6_ptr); } +/** + * __in6_dev_stats_get - get inet6_dev pointer for stats + * @dev: network device + * @skb: skb for original incoming interface if neeeded + * + * Caller must hold rcu_read_lock or RTNL, because this function + * does not take a reference on the inet6_dev. + */ +static inline struct inet6_dev *__in6_dev_stats_get(const struct net_device *dev, + const struct sk_buff *skb) +{ + if (netif_is_l3_master(dev)) + dev = dev_get_by_index_rcu(dev_net(dev), inet6_iif(skb)); + return __in6_dev_get(dev); +} + /** * __in6_dev_get_safely - get inet6_dev pointer from netdevice * @dev: network device diff --git a/include/net/bonding.h b/include/net/bonding.h index c458f084f7bb98468674938cf4cb08aebbef1a99..7d317434e3d13110e859aae2d413059e3a9e0b38 100644 --- a/include/net/bonding.h +++ b/include/net/bonding.h @@ -675,37 +675,14 @@ static inline struct slave *bond_slave_has_mac(struct bonding *bond, } /* Caller must hold rcu_read_lock() for read */ -static inline struct slave *bond_slave_has_mac_rcu(struct bonding *bond, - const u8 *mac) +static inline bool bond_slave_has_mac_rcu(struct bonding *bond, const u8 *mac) { struct list_head *iter; struct slave *tmp; - bond_for_each_slave_rcu(bond, tmp, iter) - if (ether_addr_equal_64bits(mac, tmp->dev->dev_addr)) - return tmp; - - return NULL; -} - -/* Caller must hold rcu_read_lock() for read */ -static inline bool bond_slave_has_mac_rx(struct bonding *bond, const u8 *mac) -{ - struct list_head *iter; - struct slave *tmp; - struct netdev_hw_addr *ha; - bond_for_each_slave_rcu(bond, tmp, iter) if (ether_addr_equal_64bits(mac, tmp->dev->dev_addr)) return true; - - if (netdev_uc_empty(bond->dev)) - return false; - - netdev_for_each_uc_addr(ha, bond->dev) - if (ether_addr_equal_64bits(mac, ha->addr)) - return true; - return false; } diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h index d08a788fc11e4e8f187891bcd4d0516655e34b93..4dd650d9b4a16a745c9ce0e15803b10ab77dbcbe 100644 --- a/include/net/cfg80211.h +++ b/include/net/cfg80211.h @@ -465,6 +465,9 @@ ieee80211_get_sband_iftype_data(const struct ieee80211_supported_band *sband, if (WARN_ON(iftype >= NL80211_IFTYPE_MAX)) return NULL; + if (iftype == NL80211_IFTYPE_AP_VLAN) + iftype = NL80211_IFTYPE_AP; + for (i = 0; i < sband->n_iftype_data; i++) { const struct ieee80211_sband_iftype_data *data = &sband->iftype_data[i]; diff --git a/include/net/dn.h b/include/net/dn.h deleted file mode 100644 index 56ab0726c641a01e31db29c71b6f4b14e6ce20db..0000000000000000000000000000000000000000 --- a/include/net/dn.h +++ /dev/null @@ -1,231 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _NET_DN_H -#define _NET_DN_H - -#include -#include -#include -#include -#include - -struct dn_scp /* Session Control Port */ -{ - unsigned char state; -#define DN_O 1 /* Open */ -#define DN_CR 2 /* Connect Receive */ -#define DN_DR 3 /* Disconnect Reject */ -#define DN_DRC 4 /* Discon. Rej. Complete*/ -#define DN_CC 5 /* Connect Confirm */ -#define DN_CI 6 /* Connect Initiate */ -#define DN_NR 7 /* No resources */ -#define DN_NC 8 /* No communication */ -#define DN_CD 9 /* Connect Delivery */ -#define DN_RJ 10 /* Rejected */ -#define DN_RUN 11 /* Running */ -#define DN_DI 12 /* Disconnect Initiate */ -#define DN_DIC 13 /* Disconnect Complete */ -#define DN_DN 14 /* Disconnect Notificat */ -#define DN_CL 15 /* Closed */ -#define DN_CN 16 /* Closed Notification */ - - __le16 addrloc; - __le16 addrrem; - __u16 numdat; - __u16 numoth; - __u16 numoth_rcv; - __u16 numdat_rcv; - __u16 ackxmt_dat; - __u16 ackxmt_oth; - __u16 ackrcv_dat; - __u16 ackrcv_oth; - __u8 flowrem_sw; - __u8 flowloc_sw; -#define DN_SEND 2 -#define DN_DONTSEND 1 -#define DN_NOCHANGE 0 - __u16 flowrem_dat; - __u16 flowrem_oth; - __u16 flowloc_dat; - __u16 flowloc_oth; - __u8 services_rem; - __u8 services_loc; - __u8 info_rem; - __u8 info_loc; - - __u16 segsize_rem; - __u16 segsize_loc; - - __u8 nonagle; - __u8 multi_ireq; - __u8 accept_mode; - unsigned long seg_total; /* Running total of current segment */ - - struct optdata_dn conndata_in; - struct optdata_dn conndata_out; - struct optdata_dn discdata_in; - struct optdata_dn discdata_out; - struct accessdata_dn accessdata; - - struct sockaddr_dn addr; /* Local address */ - struct sockaddr_dn peer; /* Remote address */ - - /* - * In this case the RTT estimation is not specified in the - * docs, nor is any back off algorithm. Here we follow well - * known tcp algorithms with a few small variations. - * - * snd_window: Max number of packets we send before we wait for - * an ack to come back. This will become part of a - * more complicated scheme when we support flow - * control. - * - * nsp_srtt: Round-Trip-Time (x8) in jiffies. This is a rolling - * average. - * nsp_rttvar: Round-Trip-Time-Varience (x4) in jiffies. This is the - * varience of the smoothed average (but calculated in - * a simpler way than for normal statistical varience - * calculations). - * - * nsp_rxtshift: Backoff counter. Value is zero normally, each time - * a packet is lost is increases by one until an ack - * is received. Its used to index an array of backoff - * multipliers. - */ -#define NSP_MIN_WINDOW 1 -#define NSP_MAX_WINDOW (0x07fe) - unsigned long max_window; - unsigned long snd_window; -#define NSP_INITIAL_SRTT (HZ) - unsigned long nsp_srtt; -#define NSP_INITIAL_RTTVAR (HZ*3) - unsigned long nsp_rttvar; -#define NSP_MAXRXTSHIFT 12 - unsigned long nsp_rxtshift; - - /* - * Output queues, one for data, one for otherdata/linkservice - */ - struct sk_buff_head data_xmit_queue; - struct sk_buff_head other_xmit_queue; - - /* - * Input queue for other data - */ - struct sk_buff_head other_receive_queue; - int other_report; - - /* - * Stuff to do with the slow timer - */ - unsigned long stamp; /* time of last transmit */ - unsigned long persist; - int (*persist_fxn)(struct sock *sk); - unsigned long keepalive; - void (*keepalive_fxn)(struct sock *sk); - -}; - -static inline struct dn_scp *DN_SK(struct sock *sk) -{ - return (struct dn_scp *)(sk + 1); -} - -/* - * src,dst : Source and Destination DECnet addresses - * hops : Number of hops through the network - * dst_port, src_port : NSP port numbers - * services, info : Useful data extracted from conninit messages - * rt_flags : Routing flags byte - * nsp_flags : NSP layer flags byte - * segsize : Size of segment - * segnum : Number, for data, otherdata and linkservice - * xmit_count : Number of times we've transmitted this skb - * stamp : Time stamp of most recent transmission, used in RTT calculations - * iif: Input interface number - * - * As a general policy, this structure keeps all addresses in network - * byte order, and all else in host byte order. Thus dst, src, dst_port - * and src_port are in network order. All else is in host order. - * - */ -#define DN_SKB_CB(skb) ((struct dn_skb_cb *)(skb)->cb) -struct dn_skb_cb { - __le16 dst; - __le16 src; - __u16 hops; - __le16 dst_port; - __le16 src_port; - __u8 services; - __u8 info; - __u8 rt_flags; - __u8 nsp_flags; - __u16 segsize; - __u16 segnum; - __u16 xmit_count; - unsigned long stamp; - int iif; -}; - -static inline __le16 dn_eth2dn(unsigned char *ethaddr) -{ - return get_unaligned((__le16 *)(ethaddr + 4)); -} - -static inline __le16 dn_saddr2dn(struct sockaddr_dn *saddr) -{ - return *(__le16 *)saddr->sdn_nodeaddr; -} - -static inline void dn_dn2eth(unsigned char *ethaddr, __le16 addr) -{ - __u16 a = le16_to_cpu(addr); - ethaddr[0] = 0xAA; - ethaddr[1] = 0x00; - ethaddr[2] = 0x04; - ethaddr[3] = 0x00; - ethaddr[4] = (__u8)(a & 0xff); - ethaddr[5] = (__u8)(a >> 8); -} - -static inline void dn_sk_ports_copy(struct flowidn *fld, struct dn_scp *scp) -{ - fld->fld_sport = scp->addrloc; - fld->fld_dport = scp->addrrem; -} - -unsigned int dn_mss_from_pmtu(struct net_device *dev, int mtu); -void dn_register_sysctl(void); -void dn_unregister_sysctl(void); - -#define DN_MENUVER_ACC 0x01 -#define DN_MENUVER_USR 0x02 -#define DN_MENUVER_PRX 0x04 -#define DN_MENUVER_UIC 0x08 - -struct sock *dn_sklist_find_listener(struct sockaddr_dn *addr); -struct sock *dn_find_by_skb(struct sk_buff *skb); -#define DN_ASCBUF_LEN 9 -char *dn_addr2asc(__u16, char *); -int dn_destroy_timer(struct sock *sk); - -int dn_sockaddr2username(struct sockaddr_dn *addr, unsigned char *buf, - unsigned char type); -int dn_username2sockaddr(unsigned char *data, int len, struct sockaddr_dn *addr, - unsigned char *type); - -void dn_start_slow_timer(struct sock *sk); -void dn_stop_slow_timer(struct sock *sk); - -extern __le16 decnet_address; -extern int decnet_debug_level; -extern int decnet_time_wait; -extern int decnet_dn_count; -extern int decnet_di_count; -extern int decnet_dr_count; -extern int decnet_no_fc_max_cwnd; - -extern long sysctl_decnet_mem[3]; -extern int sysctl_decnet_wmem[3]; -extern int sysctl_decnet_rmem[3]; - -#endif /* _NET_DN_H */ diff --git a/include/net/dn_dev.h b/include/net/dn_dev.h deleted file mode 100644 index 595b4f6c1eb10aa6615f5fa86796b8505035dc87..0000000000000000000000000000000000000000 --- a/include/net/dn_dev.h +++ /dev/null @@ -1,199 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _NET_DN_DEV_H -#define _NET_DN_DEV_H - - -struct dn_dev; - -struct dn_ifaddr { - struct dn_ifaddr __rcu *ifa_next; - struct dn_dev *ifa_dev; - __le16 ifa_local; - __le16 ifa_address; - __u32 ifa_flags; - __u8 ifa_scope; - char ifa_label[IFNAMSIZ]; - struct rcu_head rcu; -}; - -#define DN_DEV_S_RU 0 /* Run - working normally */ -#define DN_DEV_S_CR 1 /* Circuit Rejected */ -#define DN_DEV_S_DS 2 /* Data Link Start */ -#define DN_DEV_S_RI 3 /* Routing Layer Initialize */ -#define DN_DEV_S_RV 4 /* Routing Layer Verify */ -#define DN_DEV_S_RC 5 /* Routing Layer Complete */ -#define DN_DEV_S_OF 6 /* Off */ -#define DN_DEV_S_HA 7 /* Halt */ - - -/* - * The dn_dev_parms structure contains the set of parameters - * for each device (hence inclusion in the dn_dev structure) - * and an array is used to store the default types of supported - * device (in dn_dev.c). - * - * The type field matches the ARPHRD_ constants and is used in - * searching the list for supported devices when new devices - * come up. - * - * The mode field is used to find out if a device is broadcast, - * multipoint, or pointopoint. Please note that DECnet thinks - * different ways about devices to the rest of the kernel - * so the normal IFF_xxx flags are invalid here. For devices - * which can be any combination of the previously mentioned - * attributes, you can set this on a per device basis by - * installing an up() routine. - * - * The device state field, defines the initial state in which the - * device will come up. In the dn_dev structure, it is the actual - * state. - * - * Things have changed here. I've killed timer1 since it's a user space - * issue for a user space routing deamon to sort out. The kernel does - * not need to be bothered with it. - * - * Timers: - * t2 - Rate limit timer, min time between routing and hello messages - * t3 - Hello timer, send hello messages when it expires - * - * Callbacks: - * up() - Called to initialize device, return value can veto use of - * device with DECnet. - * down() - Called to turn device off when it goes down - * timer3() - Called once for each ifaddr when timer 3 goes off - * - * sysctl - Hook for sysctl things - * - */ -struct dn_dev_parms { - int type; /* ARPHRD_xxx */ - int mode; /* Broadcast, Unicast, Mulitpoint */ -#define DN_DEV_BCAST 1 -#define DN_DEV_UCAST 2 -#define DN_DEV_MPOINT 4 - int state; /* Initial state */ - int forwarding; /* 0=EndNode, 1=L1Router, 2=L2Router */ - unsigned long t2; /* Default value of t2 */ - unsigned long t3; /* Default value of t3 */ - int priority; /* Priority to be a router */ - char *name; /* Name for sysctl */ - int (*up)(struct net_device *); - void (*down)(struct net_device *); - void (*timer3)(struct net_device *, struct dn_ifaddr *ifa); - void *sysctl; -}; - - -struct dn_dev { - struct dn_ifaddr __rcu *ifa_list; - struct net_device *dev; - struct dn_dev_parms parms; - char use_long; - struct timer_list timer; - unsigned long t3; - struct neigh_parms *neigh_parms; - __u8 addr[ETH_ALEN]; - struct neighbour *router; /* Default router on circuit */ - struct neighbour *peer; /* Peer on pointopoint links */ - unsigned long uptime; /* Time device went up in jiffies */ -}; - -struct dn_short_packet { - __u8 msgflg; - __le16 dstnode; - __le16 srcnode; - __u8 forward; -} __packed; - -struct dn_long_packet { - __u8 msgflg; - __u8 d_area; - __u8 d_subarea; - __u8 d_id[6]; - __u8 s_area; - __u8 s_subarea; - __u8 s_id[6]; - __u8 nl2; - __u8 visit_ct; - __u8 s_class; - __u8 pt; -} __packed; - -/*------------------------- DRP - Routing messages ---------------------*/ - -struct endnode_hello_message { - __u8 msgflg; - __u8 tiver[3]; - __u8 id[6]; - __u8 iinfo; - __le16 blksize; - __u8 area; - __u8 seed[8]; - __u8 neighbor[6]; - __le16 timer; - __u8 mpd; - __u8 datalen; - __u8 data[2]; -} __packed; - -struct rtnode_hello_message { - __u8 msgflg; - __u8 tiver[3]; - __u8 id[6]; - __u8 iinfo; - __le16 blksize; - __u8 priority; - __u8 area; - __le16 timer; - __u8 mpd; -} __packed; - - -void dn_dev_init(void); -void dn_dev_cleanup(void); - -int dn_dev_ioctl(unsigned int cmd, void __user *arg); - -void dn_dev_devices_off(void); -void dn_dev_devices_on(void); - -void dn_dev_init_pkt(struct sk_buff *skb); -void dn_dev_veri_pkt(struct sk_buff *skb); -void dn_dev_hello(struct sk_buff *skb); - -void dn_dev_up(struct net_device *); -void dn_dev_down(struct net_device *); - -int dn_dev_set_default(struct net_device *dev, int force); -struct net_device *dn_dev_get_default(void); -int dn_dev_bind_default(__le16 *addr); - -int register_dnaddr_notifier(struct notifier_block *nb); -int unregister_dnaddr_notifier(struct notifier_block *nb); - -static inline int dn_dev_islocal(struct net_device *dev, __le16 addr) -{ - struct dn_dev *dn_db; - struct dn_ifaddr *ifa; - int res = 0; - - rcu_read_lock(); - dn_db = rcu_dereference(dev->dn_ptr); - if (dn_db == NULL) { - printk(KERN_DEBUG "dn_dev_islocal: Called for non DECnet device\n"); - goto out; - } - - for (ifa = rcu_dereference(dn_db->ifa_list); - ifa != NULL; - ifa = rcu_dereference(ifa->ifa_next)) - if ((addr ^ ifa->ifa_local) == 0) { - res = 1; - break; - } -out: - rcu_read_unlock(); - return res; -} - -#endif /* _NET_DN_DEV_H */ diff --git a/include/net/dn_fib.h b/include/net/dn_fib.h deleted file mode 100644 index 6dd2213c5eb216a0cc08f4d2c02b82f0f5abcd20..0000000000000000000000000000000000000000 --- a/include/net/dn_fib.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _NET_DN_FIB_H -#define _NET_DN_FIB_H - -#include -#include - -extern const struct nla_policy rtm_dn_policy[]; - -struct dn_fib_res { - struct fib_rule *r; - struct dn_fib_info *fi; - unsigned char prefixlen; - unsigned char nh_sel; - unsigned char type; - unsigned char scope; -}; - -struct dn_fib_nh { - struct net_device *nh_dev; - unsigned int nh_flags; - unsigned char nh_scope; - int nh_weight; - int nh_power; - int nh_oif; - __le16 nh_gw; -}; - -struct dn_fib_info { - struct dn_fib_info *fib_next; - struct dn_fib_info *fib_prev; - int fib_treeref; - refcount_t fib_clntref; - int fib_dead; - unsigned int fib_flags; - int fib_protocol; - __le16 fib_prefsrc; - __u32 fib_priority; - __u32 fib_metrics[RTAX_MAX]; - int fib_nhs; - int fib_power; - struct dn_fib_nh fib_nh[0]; -#define dn_fib_dev fib_nh[0].nh_dev -}; - - -#define DN_FIB_RES_RESET(res) ((res).nh_sel = 0) -#define DN_FIB_RES_NH(res) ((res).fi->fib_nh[(res).nh_sel]) - -#define DN_FIB_RES_PREFSRC(res) ((res).fi->fib_prefsrc ? : __dn_fib_res_prefsrc(&res)) -#define DN_FIB_RES_GW(res) (DN_FIB_RES_NH(res).nh_gw) -#define DN_FIB_RES_DEV(res) (DN_FIB_RES_NH(res).nh_dev) -#define DN_FIB_RES_OIF(res) (DN_FIB_RES_NH(res).nh_oif) - -typedef struct { - __le16 datum; -} dn_fib_key_t; - -typedef struct { - __le16 datum; -} dn_fib_hash_t; - -typedef struct { - __u16 datum; -} dn_fib_idx_t; - -struct dn_fib_node { - struct dn_fib_node *fn_next; - struct dn_fib_info *fn_info; -#define DN_FIB_INFO(f) ((f)->fn_info) - dn_fib_key_t fn_key; - u8 fn_type; - u8 fn_scope; - u8 fn_state; -}; - - -struct dn_fib_table { - struct hlist_node hlist; - u32 n; - - int (*insert)(struct dn_fib_table *t, struct rtmsg *r, - struct nlattr *attrs[], struct nlmsghdr *n, - struct netlink_skb_parms *req); - int (*delete)(struct dn_fib_table *t, struct rtmsg *r, - struct nlattr *attrs[], struct nlmsghdr *n, - struct netlink_skb_parms *req); - int (*lookup)(struct dn_fib_table *t, const struct flowidn *fld, - struct dn_fib_res *res); - int (*flush)(struct dn_fib_table *t); - int (*dump)(struct dn_fib_table *t, struct sk_buff *skb, struct netlink_callback *cb); - - unsigned char data[0]; -}; - -#ifdef CONFIG_DECNET_ROUTER -/* - * dn_fib.c - */ -void dn_fib_init(void); -void dn_fib_cleanup(void); - -int dn_fib_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg); -struct dn_fib_info *dn_fib_create_info(const struct rtmsg *r, - struct nlattr *attrs[], - const struct nlmsghdr *nlh, int *errp); -int dn_fib_semantic_match(int type, struct dn_fib_info *fi, - const struct flowidn *fld, struct dn_fib_res *res); -void dn_fib_release_info(struct dn_fib_info *fi); -void dn_fib_flush(void); -void dn_fib_select_multipath(const struct flowidn *fld, struct dn_fib_res *res); - -/* - * dn_tables.c - */ -struct dn_fib_table *dn_fib_get_table(u32 n, int creat); -struct dn_fib_table *dn_fib_empty_table(void); -void dn_fib_table_init(void); -void dn_fib_table_cleanup(void); - -/* - * dn_rules.c - */ -void dn_fib_rules_init(void); -void dn_fib_rules_cleanup(void); -unsigned int dnet_addr_type(__le16 addr); -int dn_fib_lookup(struct flowidn *fld, struct dn_fib_res *res); - -int dn_fib_dump(struct sk_buff *skb, struct netlink_callback *cb); - -void dn_fib_free_info(struct dn_fib_info *fi); - -static inline void dn_fib_info_put(struct dn_fib_info *fi) -{ - if (refcount_dec_and_test(&fi->fib_clntref)) - dn_fib_free_info(fi); -} - -static inline void dn_fib_res_put(struct dn_fib_res *res) -{ - if (res->fi) - dn_fib_info_put(res->fi); - if (res->r) - fib_rule_put(res->r); -} - -#else /* Endnode */ - -#define dn_fib_init() do { } while(0) -#define dn_fib_cleanup() do { } while(0) - -#define dn_fib_lookup(fl, res) (-ESRCH) -#define dn_fib_info_put(fi) do { } while(0) -#define dn_fib_select_multipath(fl, res) do { } while(0) -#define dn_fib_rules_policy(saddr,res,flags) (0) -#define dn_fib_res_put(res) do { } while(0) - -#endif /* CONFIG_DECNET_ROUTER */ - -static inline __le16 dnet_make_mask(int n) -{ - if (n) - return cpu_to_le16(~((1 << (16 - n)) - 1)); - return cpu_to_le16(0); -} - -#endif /* _NET_DN_FIB_H */ diff --git a/include/net/dn_neigh.h b/include/net/dn_neigh.h deleted file mode 100644 index 2e3e7793973a8beeae42460986cd28e6111368be..0000000000000000000000000000000000000000 --- a/include/net/dn_neigh.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _NET_DN_NEIGH_H -#define _NET_DN_NEIGH_H - -/* - * The position of the first two fields of - * this structure are critical - SJW - */ -struct dn_neigh { - struct neighbour n; - __le16 addr; - unsigned long flags; -#define DN_NDFLAG_R1 0x0001 /* Router L1 */ -#define DN_NDFLAG_R2 0x0002 /* Router L2 */ -#define DN_NDFLAG_P3 0x0004 /* Phase III Node */ - unsigned long blksize; - __u8 priority; -}; - -void dn_neigh_init(void); -void dn_neigh_cleanup(void); -int dn_neigh_router_hello(struct net *net, struct sock *sk, struct sk_buff *skb); -int dn_neigh_endnode_hello(struct net *net, struct sock *sk, struct sk_buff *skb); -void dn_neigh_pointopoint_hello(struct sk_buff *skb); -int dn_neigh_elist(struct net_device *dev, unsigned char *ptr, int n); -int dn_to_neigh_output(struct net *net, struct sock *sk, struct sk_buff *skb); - -extern struct neigh_table dn_neigh_table; - -#endif /* _NET_DN_NEIGH_H */ diff --git a/include/net/dn_nsp.h b/include/net/dn_nsp.h deleted file mode 100644 index 413a15e5339cbf5b55b8055ede56d2972223c4b3..0000000000000000000000000000000000000000 --- a/include/net/dn_nsp.h +++ /dev/null @@ -1,203 +0,0 @@ -#ifndef _NET_DN_NSP_H -#define _NET_DN_NSP_H -/****************************************************************************** - (c) 1995-1998 E.M. Serrat emserrat@geocities.com - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*******************************************************************************/ -/* dn_nsp.c functions prototyping */ - -void dn_nsp_send_data_ack(struct sock *sk); -void dn_nsp_send_oth_ack(struct sock *sk); -void dn_send_conn_ack(struct sock *sk); -void dn_send_conn_conf(struct sock *sk, gfp_t gfp); -void dn_nsp_send_disc(struct sock *sk, unsigned char type, - unsigned short reason, gfp_t gfp); -void dn_nsp_return_disc(struct sk_buff *skb, unsigned char type, - unsigned short reason); -void dn_nsp_send_link(struct sock *sk, unsigned char lsflags, char fcval); -void dn_nsp_send_conninit(struct sock *sk, unsigned char flags); - -void dn_nsp_output(struct sock *sk); -int dn_nsp_check_xmit_queue(struct sock *sk, struct sk_buff *skb, - struct sk_buff_head *q, unsigned short acknum); -void dn_nsp_queue_xmit(struct sock *sk, struct sk_buff *skb, gfp_t gfp, - int oob); -unsigned long dn_nsp_persist(struct sock *sk); -int dn_nsp_xmit_timeout(struct sock *sk); - -int dn_nsp_rx(struct sk_buff *); -int dn_nsp_backlog_rcv(struct sock *sk, struct sk_buff *skb); - -struct sk_buff *dn_alloc_skb(struct sock *sk, int size, gfp_t pri); -struct sk_buff *dn_alloc_send_skb(struct sock *sk, size_t *size, int noblock, - long timeo, int *err); - -#define NSP_REASON_OK 0 /* No error */ -#define NSP_REASON_NR 1 /* No resources */ -#define NSP_REASON_UN 2 /* Unrecognised node name */ -#define NSP_REASON_SD 3 /* Node shutting down */ -#define NSP_REASON_ID 4 /* Invalid destination end user */ -#define NSP_REASON_ER 5 /* End user lacks resources */ -#define NSP_REASON_OB 6 /* Object too busy */ -#define NSP_REASON_US 7 /* Unspecified error */ -#define NSP_REASON_TP 8 /* Third-Party abort */ -#define NSP_REASON_EA 9 /* End user has aborted the link */ -#define NSP_REASON_IF 10 /* Invalid node name format */ -#define NSP_REASON_LS 11 /* Local node shutdown */ -#define NSP_REASON_LL 32 /* Node lacks logical-link resources */ -#define NSP_REASON_LE 33 /* End user lacks logical-link resources */ -#define NSP_REASON_UR 34 /* Unacceptable RQSTRID or PASSWORD field */ -#define NSP_REASON_UA 36 /* Unacceptable ACCOUNT field */ -#define NSP_REASON_TM 38 /* End user timed out logical link */ -#define NSP_REASON_NU 39 /* Node unreachable */ -#define NSP_REASON_NL 41 /* No-link message */ -#define NSP_REASON_DC 42 /* Disconnect confirm */ -#define NSP_REASON_IO 43 /* Image data field overflow */ - -#define NSP_DISCINIT 0x38 -#define NSP_DISCCONF 0x48 - -/*------------------------- NSP - messages ------------------------------*/ -/* Data Messages */ -/*---------------*/ - -/* Data Messages (data segment/interrupt/link service) */ - -struct nsp_data_seg_msg { - __u8 msgflg; - __le16 dstaddr; - __le16 srcaddr; -} __packed; - -struct nsp_data_opt_msg { - __le16 acknum; - __le16 segnum; - __le16 lsflgs; -} __packed; - -struct nsp_data_opt_msg1 { - __le16 acknum; - __le16 segnum; -} __packed; - - -/* Acknowledgment Message (data/other data) */ -struct nsp_data_ack_msg { - __u8 msgflg; - __le16 dstaddr; - __le16 srcaddr; - __le16 acknum; -} __packed; - -/* Connect Acknowledgment Message */ -struct nsp_conn_ack_msg { - __u8 msgflg; - __le16 dstaddr; -} __packed; - - -/* Connect Initiate/Retransmit Initiate/Connect Confirm */ -struct nsp_conn_init_msg { - __u8 msgflg; -#define NSP_CI 0x18 /* Connect Initiate */ -#define NSP_RCI 0x68 /* Retrans. Conn Init */ - __le16 dstaddr; - __le16 srcaddr; - __u8 services; -#define NSP_FC_NONE 0x00 /* Flow Control None */ -#define NSP_FC_SRC 0x04 /* Seg Req. Count */ -#define NSP_FC_SCMC 0x08 /* Sess. Control Mess */ -#define NSP_FC_MASK 0x0c /* FC type mask */ - __u8 info; - __le16 segsize; -} __packed; - -/* Disconnect Initiate/Disconnect Confirm */ -struct nsp_disconn_init_msg { - __u8 msgflg; - __le16 dstaddr; - __le16 srcaddr; - __le16 reason; -} __packed; - - - -struct srcobj_fmt { - __u8 format; - __u8 task; - __le16 grpcode; - __le16 usrcode; - __u8 dlen; -} __packed; - -/* - * A collection of functions for manipulating the sequence - * numbers used in NSP. Similar in operation to the functions - * of the same name in TCP. - */ -static __inline__ int dn_before(__u16 seq1, __u16 seq2) -{ - seq1 &= 0x0fff; - seq2 &= 0x0fff; - - return (int)((seq1 - seq2) & 0x0fff) > 2048; -} - - -static __inline__ int dn_after(__u16 seq1, __u16 seq2) -{ - seq1 &= 0x0fff; - seq2 &= 0x0fff; - - return (int)((seq2 - seq1) & 0x0fff) > 2048; -} - -static __inline__ int dn_equal(__u16 seq1, __u16 seq2) -{ - return ((seq1 ^ seq2) & 0x0fff) == 0; -} - -static __inline__ int dn_before_or_equal(__u16 seq1, __u16 seq2) -{ - return (dn_before(seq1, seq2) || dn_equal(seq1, seq2)); -} - -static __inline__ void seq_add(__u16 *seq, __u16 off) -{ - (*seq) += off; - (*seq) &= 0x0fff; -} - -static __inline__ int seq_next(__u16 seq1, __u16 seq2) -{ - return dn_equal(seq1 + 1, seq2); -} - -/* - * Can we delay the ack ? - */ -static __inline__ int sendack(__u16 seq) -{ - return (int)((seq & 0x1000) ? 0 : 1); -} - -/* - * Is socket congested ? - */ -static __inline__ int dn_congested(struct sock *sk) -{ - return atomic_read(&sk->sk_rmem_alloc) > (sk->sk_rcvbuf >> 1); -} - -#define DN_MAX_NSP_DATA_HEADER (11) - -#endif /* _NET_DN_NSP_H */ diff --git a/include/net/dn_route.h b/include/net/dn_route.h deleted file mode 100644 index 342d2503cba5cfc4d9a4912d27543815c1f834e5..0000000000000000000000000000000000000000 --- a/include/net/dn_route.h +++ /dev/null @@ -1,123 +0,0 @@ -#ifndef _NET_DN_ROUTE_H -#define _NET_DN_ROUTE_H - -/****************************************************************************** - (c) 1995-1998 E.M. Serrat emserrat@geocities.com - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*******************************************************************************/ - -struct sk_buff *dn_alloc_skb(struct sock *sk, int size, gfp_t pri); -int dn_route_output_sock(struct dst_entry __rcu **pprt, struct flowidn *, - struct sock *sk, int flags); -int dn_cache_dump(struct sk_buff *skb, struct netlink_callback *cb); -void dn_rt_cache_flush(int delay); -int dn_route_rcv(struct sk_buff *skb, struct net_device *dev, - struct packet_type *pt, struct net_device *orig_dev); - -/* Masks for flags field */ -#define DN_RT_F_PID 0x07 /* Mask for packet type */ -#define DN_RT_F_PF 0x80 /* Padding Follows */ -#define DN_RT_F_VER 0x40 /* Version =0 discard packet if ==1 */ -#define DN_RT_F_IE 0x20 /* Intra Ethernet, Reserved in short pkt */ -#define DN_RT_F_RTS 0x10 /* Packet is being returned to sender */ -#define DN_RT_F_RQR 0x08 /* Return packet to sender upon non-delivery */ - -/* Mask for types of routing packets */ -#define DN_RT_PKT_MSK 0x06 -/* Types of routing packets */ -#define DN_RT_PKT_SHORT 0x02 /* Short routing packet */ -#define DN_RT_PKT_LONG 0x06 /* Long routing packet */ - -/* Mask for control/routing selection */ -#define DN_RT_PKT_CNTL 0x01 /* Set to 1 if a control packet */ -/* Types of control packets */ -#define DN_RT_CNTL_MSK 0x0f /* Mask for control packets */ -#define DN_RT_PKT_INIT 0x01 /* Initialisation packet */ -#define DN_RT_PKT_VERI 0x03 /* Verification Message */ -#define DN_RT_PKT_HELO 0x05 /* Hello and Test Message */ -#define DN_RT_PKT_L1RT 0x07 /* Level 1 Routing Message */ -#define DN_RT_PKT_L2RT 0x09 /* Level 2 Routing Message */ -#define DN_RT_PKT_ERTH 0x0b /* Ethernet Router Hello */ -#define DN_RT_PKT_EEDH 0x0d /* Ethernet EndNode Hello */ - -/* Values for info field in hello message */ -#define DN_RT_INFO_TYPE 0x03 /* Type mask */ -#define DN_RT_INFO_L1RT 0x02 /* L1 Router */ -#define DN_RT_INFO_L2RT 0x01 /* L2 Router */ -#define DN_RT_INFO_ENDN 0x03 /* EndNode */ -#define DN_RT_INFO_VERI 0x04 /* Verification Reqd. */ -#define DN_RT_INFO_RJCT 0x08 /* Reject Flag, Reserved */ -#define DN_RT_INFO_VFLD 0x10 /* Verification Failed, Reserved */ -#define DN_RT_INFO_NOML 0x20 /* No Multicast traffic accepted */ -#define DN_RT_INFO_BLKR 0x40 /* Blocking Requested */ - -/* - * The fl structure is what we used to look up the route. - * The rt_saddr & rt_daddr entries are the same as key.saddr & key.daddr - * except for local input routes, where the rt_saddr = fl.fld_dst and - * rt_daddr = fl.fld_src to allow the route to be used for returning - * packets to the originating host. - */ -struct dn_route { - struct dst_entry dst; - struct dn_route __rcu *dn_next; - - struct neighbour *n; - - struct flowidn fld; - - __le16 rt_saddr; - __le16 rt_daddr; - __le16 rt_gateway; - __le16 rt_local_src; /* Source used for forwarding packets */ - __le16 rt_src_map; - __le16 rt_dst_map; - - unsigned int rt_flags; - unsigned int rt_type; -}; - -static inline bool dn_is_input_route(struct dn_route *rt) -{ - return rt->fld.flowidn_iif != 0; -} - -static inline bool dn_is_output_route(struct dn_route *rt) -{ - return rt->fld.flowidn_iif == 0; -} - -void dn_route_init(void); -void dn_route_cleanup(void); - -#include -#include - -static inline void dn_rt_send(struct sk_buff *skb) -{ - dev_queue_xmit(skb); -} - -static inline void dn_rt_finish_output(struct sk_buff *skb, char *dst, char *src) -{ - struct net_device *dev = skb->dev; - - if ((dev->type != ARPHRD_ETHER) && (dev->type != ARPHRD_LOOPBACK)) - dst = NULL; - - if (dev_hard_header(skb, dev, ETH_P_DNA_RT, dst, src, skb->len) >= 0) - dn_rt_send(skb); - else - kfree_skb(skb); -} - -#endif /* _NET_DN_ROUTE_H */ diff --git a/include/net/dst.h b/include/net/dst.h index d2728525df5a7ef29ed88979a089898f98409d0b..50258a813137792161eb289e4d81167b2cb77181 100644 --- a/include/net/dst.h +++ b/include/net/dst.h @@ -247,12 +247,6 @@ static inline void dst_use_noref(struct dst_entry *dst, unsigned long time) } } -static inline void dst_hold_and_use(struct dst_entry *dst, unsigned long time) -{ - dst_hold(dst); - dst_use_noref(dst, time); -} - static inline struct dst_entry *dst_clone(struct dst_entry *dst) { if (dst) diff --git a/include/net/ip.h b/include/net/ip.h index e2e0e9f5d009c08219d21aebbc02fcb5e3cd0bdd..5068fbd1726d0967d2bad8b04127d988508c2864 100644 --- a/include/net/ip.h +++ b/include/net/ip.h @@ -75,6 +75,7 @@ struct ipcm_cookie { __be32 addr; int oif; struct ip_options_rcu *opt; + __u8 protocol; __u8 ttl; __s16 tos; char priority; @@ -94,6 +95,7 @@ static inline void ipcm_init_sk(struct ipcm_cookie *ipcm, ipcm->sockc.tsflags = inet->sk.sk_tsflags; ipcm->oif = inet->sk.sk_bound_dev_if; ipcm->addr = inet->inet_saddr; + ipcm->protocol = inet->inet_num; } #define IPCB(skb) ((struct inet_skb_parm*)((skb)->cb)) diff --git a/include/net/ip6_tunnel.h b/include/net/ip6_tunnel.h index f594eb71c27469096d2b0dd99b9fb50f85509e2f..c26b39a3000002b031200524082763be93885924 100644 --- a/include/net/ip6_tunnel.h +++ b/include/net/ip6_tunnel.h @@ -57,7 +57,7 @@ struct ip6_tnl { /* These fields used only by GRE */ __u32 i_seqno; /* The last seen seqno */ - __u32 o_seqno; /* The last output seqno */ + atomic_t o_seqno; /* The last output seqno */ int hlen; /* tun_hlen + encap_hlen */ int tun_hlen; /* Precalculated header length */ int encap_hlen; /* Encap header length (FOU,GUE) */ diff --git a/include/net/ip_tunnels.h b/include/net/ip_tunnels.h index d5f62fb24cea19a4d2b7eb0fae905ded4330d30f..f898d42fafdbabe521db8fb20d85c66077d81cc4 100644 --- a/include/net/ip_tunnels.h +++ b/include/net/ip_tunnels.h @@ -113,7 +113,7 @@ struct ip_tunnel { /* These four fields used only by GRE */ u32 i_seqno; /* The last seen seqno */ - u32 o_seqno; /* The last output seqno */ + atomic_t o_seqno; /* The last output seqno */ int tun_hlen; /* Precalculated header length */ /* These four fields used only by ERSPAN */ diff --git a/include/net/ipv6.h b/include/net/ipv6.h index 7df50abbbb6c47a0dc542b405ac2ebbd2ff00526..d6f2e871aa14d7cbd552222bb9bf823b7e547146 100644 --- a/include/net/ipv6.h +++ b/include/net/ipv6.h @@ -602,12 +602,8 @@ static inline u32 ipv6_addr_hash(const struct in6_addr *a) /* more secured version of ipv6_addr_hash() */ static inline u32 __ipv6_addr_jhash(const struct in6_addr *a, const u32 initval) { - u32 v = (__force u32)a->s6_addr32[0] ^ (__force u32)a->s6_addr32[1]; - - return jhash_3words(v, - (__force u32)a->s6_addr32[2], - (__force u32)a->s6_addr32[3], - initval); + return jhash2((__force const u32 *)a->s6_addr32, + ARRAY_SIZE(a->s6_addr32), initval); } static inline bool ipv6_addr_loopback(const struct in6_addr *a) @@ -1042,6 +1038,8 @@ void ipv6_icmp_error(struct sock *sk, struct sk_buff *skb, int err, __be16 port, void ipv6_local_error(struct sock *sk, int err, struct flowi6 *fl6, u32 info); void ipv6_local_rxpmtu(struct sock *sk, struct flowi6 *fl6, u32 mtu); +void inet6_cleanup_sock(struct sock *sk); +void inet6_sock_destruct(struct sock *sk); int inet6_release(struct socket *sock); int inet6_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len); int inet6_getname(struct socket *sock, struct sockaddr *uaddr, diff --git a/include/net/lwtunnel.h b/include/net/lwtunnel.h index 33fd9ba7e0e5a29d5dd1705112a9213f08531612..ec75c0a1c529fb88c861b7a2a728871ec40fc052 100644 --- a/include/net/lwtunnel.h +++ b/include/net/lwtunnel.h @@ -16,9 +16,12 @@ #define LWTUNNEL_STATE_INPUT_REDIRECT BIT(1) #define LWTUNNEL_STATE_XMIT_REDIRECT BIT(2) +/* LWTUNNEL_XMIT_CONTINUE should be distinguishable from dst_output return + * values (NET_XMIT_xxx and NETDEV_TX_xxx in linux/netdevice.h) for safety. + */ enum { LWTUNNEL_XMIT_DONE, - LWTUNNEL_XMIT_CONTINUE, + LWTUNNEL_XMIT_CONTINUE = 0x100, }; diff --git a/include/net/neighbour.h b/include/net/neighbour.h index 5ce035984a4ddb091eba1fb9062ccff5e224e164..e58ef9e338de620a5991d0f3980ebd91145063dc 100644 --- a/include/net/neighbour.h +++ b/include/net/neighbour.h @@ -251,11 +251,6 @@ static inline void *neighbour_priv(const struct neighbour *n) #define NEIGH_UPDATE_F_ADMIN 0x80000000 -static inline bool neigh_key_eq16(const struct neighbour *n, const void *pkey) -{ - return *(const u16 *)n->primary_key == *(const u16 *)pkey; -} - static inline bool neigh_key_eq32(const struct neighbour *n, const void *pkey) { return *(const u32 *)n->primary_key == *(const u32 *)pkey; @@ -305,8 +300,6 @@ void neigh_table_init(int index, struct neigh_table *tbl); int neigh_table_clear(int index, struct neigh_table *tbl); struct neighbour *neigh_lookup(struct neigh_table *tbl, const void *pkey, struct net_device *dev); -struct neighbour *neigh_lookup_nodev(struct neigh_table *tbl, struct net *net, - const void *pkey); struct neighbour *__neigh_create(struct neigh_table *tbl, const void *pkey, struct net_device *dev, bool want_ref); static inline struct neighbour *neigh_create(struct neigh_table *tbl, diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index 93253ba1eeac3df071a130de2f75fa28d48db7ba..fd85286482c1e06726d63216ccc3338c7b83ce29 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -191,14 +191,13 @@ static inline enum nft_registers nft_type_to_reg(enum nft_data_types type) } int nft_parse_u32_check(const struct nlattr *attr, int max, u32 *dest); -unsigned int nft_parse_register(const struct nlattr *attr); int nft_dump_register(struct sk_buff *skb, unsigned int attr, unsigned int reg); -int nft_validate_register_load(enum nft_registers reg, unsigned int len); -int nft_validate_register_store(const struct nft_ctx *ctx, - enum nft_registers reg, - const struct nft_data *data, - enum nft_data_types type, unsigned int len); +int nft_parse_register_load(const struct nlattr *attr, u8 *sreg, u32 len); +int nft_parse_register_store(const struct nft_ctx *ctx, + const struct nlattr *attr, u8 *dreg, + const struct nft_data *data, + enum nft_data_types type, unsigned int len); /** * struct nft_userdata - user defined data associated with an object @@ -226,6 +225,10 @@ struct nft_set_elem { u32 buf[NFT_DATA_VALUE_MAXLEN / sizeof(u32)]; struct nft_data val; } key; + union { + u32 buf[NFT_DATA_VALUE_MAXLEN / sizeof(u32)]; + struct nft_data val; + } data; void *priv; }; @@ -471,6 +474,7 @@ struct nft_set_binding { }; enum nft_trans_phase; +void nf_tables_activate_set(const struct nft_ctx *ctx, struct nft_set *set); void nf_tables_deactivate_set(const struct nft_ctx *ctx, struct nft_set *set, struct nft_set_binding *binding, enum nft_trans_phase phase); @@ -732,6 +736,7 @@ struct nft_expr_type { enum nft_trans_phase { NFT_TRANS_PREPARE, + NFT_TRANS_PREPARE_ERROR, NFT_TRANS_ABORT, NFT_TRANS_COMMIT, NFT_TRANS_RELEASE @@ -987,6 +992,29 @@ int __nft_release_basechain(struct nft_ctx *ctx); unsigned int nft_do_chain(struct nft_pktinfo *pkt, void *priv); +static inline bool nft_use_inc(u32 *use) +{ + if (*use == UINT_MAX) + return false; + + (*use)++; + + return true; +} + +static inline void nft_use_dec(u32 *use) +{ + WARN_ON_ONCE((*use)-- == 0); +} + +/* For error and abort path: restore use counter to previous state. */ +static inline void nft_use_inc_restore(u32 *use) +{ + WARN_ON_ONCE(!nft_use_inc(use)); +} + +#define nft_use_dec_restore nft_use_dec + /** * struct nft_table - nf_tables table * @@ -1045,8 +1073,8 @@ struct nft_object { struct list_head list; char *name; struct nft_table *table; - u32 genmask:2, - use:30; + u32 genmask:2; + u32 use; u64 handle; /* runtime data below here */ const struct nft_object_ops *ops ____cacheline_aligned; @@ -1144,8 +1172,8 @@ struct nft_flowtable { int hooknum; int priority; int ops_len; - u32 genmask:2, - use:30; + u32 genmask:2; + u32 use; u64 handle; /* runtime data below here */ struct nf_hook_ops *ops ____cacheline_aligned; @@ -1156,6 +1184,10 @@ struct nft_flowtable *nft_flowtable_lookup(const struct nft_table *table, const struct nlattr *nla, u8 genmask); +void nf_tables_deactivate_flowtable(const struct nft_ctx *ctx, + struct nft_flowtable *flowtable, + enum nft_trans_phase phase); + void nft_register_flowtable_type(struct nf_flowtable_type *type); void nft_unregister_flowtable_type(struct nf_flowtable_type *type); @@ -1315,12 +1347,14 @@ static inline void nft_set_elem_clear_busy(struct nft_set_ext *ext) * struct nft_trans - nf_tables object update in transaction * * @list: used internally + * @binding_list: list of objects with possible bindings * @msg_type: message type * @ctx: transaction context * @data: internal information related to the transaction */ struct nft_trans { struct list_head list; + struct list_head binding_list; int msg_type; struct nft_ctx ctx; char data[0]; @@ -1405,4 +1439,15 @@ struct nft_trans_flowtable { int __init nft_chain_filter_init(void); void nft_chain_filter_fini(void); +struct nftables_pernet { + struct list_head tables; + struct list_head commit_list; + struct list_head binding_list; + struct list_head module_list; + struct list_head notify_list; + struct mutex commit_mutex; + unsigned int base_seq; + u8 validate_state; +}; + #endif /* _NET_NF_TABLES_H */ diff --git a/include/net/netfilter/nf_tables_core.h b/include/net/netfilter/nf_tables_core.h index 8da837d2aaf997d5d642b081154c1bf9d2b3b26b..6a3f76e012be37e330b1b8a083d8afd56f5410a5 100644 --- a/include/net/netfilter/nf_tables_core.h +++ b/include/net/netfilter/nf_tables_core.h @@ -21,13 +21,14 @@ void nf_tables_core_module_exit(void); struct nft_cmp_fast_expr { u32 data; - enum nft_registers sreg:8; + u32 mask; + u8 sreg; u8 len; }; struct nft_immediate_expr { struct nft_data data; - enum nft_registers dreg:8; + u8 dreg; u8 dlen; }; @@ -47,14 +48,14 @@ struct nft_payload { enum nft_payload_bases base:8; u8 offset; u8 len; - enum nft_registers dreg:8; + u8 dreg; }; struct nft_payload_set { enum nft_payload_bases base:8; u8 offset; u8 len; - enum nft_registers sreg:8; + u8 sreg; u8 csum_type; u8 csum_offset; u8 csum_flags; diff --git a/include/net/netfilter/nft_fib.h b/include/net/netfilter/nft_fib.h index a88f92737308d18c90fd4111ef3f469222454311..1f8726739529108f680af29718135aac53e7bb6a 100644 --- a/include/net/netfilter/nft_fib.h +++ b/include/net/netfilter/nft_fib.h @@ -3,7 +3,7 @@ #define _NFT_FIB_H_ struct nft_fib { - enum nft_registers dreg:8; + u8 dreg; u8 result; u32 flags; }; diff --git a/include/net/netfilter/nft_masq.h b/include/net/netfilter/nft_masq.h index e51ab3815797bef3d1c9377403959cded803e851..e69a8277b70b3005b854d7417d6a232c3a14d0cd 100644 --- a/include/net/netfilter/nft_masq.h +++ b/include/net/netfilter/nft_masq.h @@ -4,8 +4,8 @@ struct nft_masq { u32 flags; - enum nft_registers sreg_proto_min:8; - enum nft_registers sreg_proto_max:8; + u8 sreg_proto_min; + u8 sreg_proto_max; }; extern const struct nla_policy nft_masq_policy[]; diff --git a/include/net/netfilter/nft_redir.h b/include/net/netfilter/nft_redir.h index 4a970737c03c832fcbe20376cd0b8399dd9a81ff..2b4036c94cb3ee6a35bdcae1ff9cd5d39e688057 100644 --- a/include/net/netfilter/nft_redir.h +++ b/include/net/netfilter/nft_redir.h @@ -3,8 +3,8 @@ #define _NFT_REDIR_H_ struct nft_redir { - enum nft_registers sreg_proto_min:8; - enum nft_registers sreg_proto_max:8; + u8 sreg_proto_min; + u8 sreg_proto_max; u16 flags; }; diff --git a/include/net/netns/netfilter.h b/include/net/netns/netfilter.h index 47daca947b2d90c198cba391d8a8c02b4a5d761f..62f653925a090ecf27269ab59ecf4c0c888327c0 100644 --- a/include/net/netns/netfilter.h +++ b/include/net/netns/netfilter.h @@ -23,9 +23,6 @@ struct netns_nf { struct nf_hook_entries __rcu *hooks_arp[NF_ARP_NUMHOOKS]; #endif struct nf_hook_entries __rcu *hooks_bridge[NF_INET_NUMHOOKS]; -#if IS_ENABLED(CONFIG_DECNET) - struct nf_hook_entries __rcu *hooks_decnet[NF_DN_NUMHOOKS]; -#endif #if IS_ENABLED(CONFIG_NF_DEFRAG_IPV4) bool defrag_ipv4; #endif diff --git a/include/net/netns/nftables.h b/include/net/netns/nftables.h index 286fd960896fdd8fa79b9598cdc8081fc424867d..8c77832d024041c02ee2c38e0c7951d5c56eefda 100644 --- a/include/net/netns/nftables.h +++ b/include/net/netns/nftables.h @@ -5,12 +5,7 @@ #include struct netns_nftables { - struct list_head tables; - struct list_head commit_list; - struct mutex commit_mutex; - unsigned int base_seq; u8 gencursor; - u8 validate_state; }; #endif diff --git a/include/net/nfc/nfc.h b/include/net/nfc/nfc.h index bbdc73a3239dffbcafe8cf19f5997ddbeb7ada04..8b86560b5cfb12cfb9a8705fde0b2cf25725ecdb 100644 --- a/include/net/nfc/nfc.h +++ b/include/net/nfc/nfc.h @@ -278,7 +278,7 @@ struct sk_buff *nfc_alloc_send_skb(struct nfc_dev *dev, struct sock *sk, struct sk_buff *nfc_alloc_recv_skb(unsigned int size, gfp_t gfp); int nfc_set_remote_general_bytes(struct nfc_dev *dev, - u8 *gt, u8 gt_len); + const u8 *gt, u8 gt_len); u8 *nfc_get_local_general_bytes(struct nfc_dev *dev, size_t *gb_len); int nfc_fw_download_done(struct nfc_dev *dev, const char *firmware_name, @@ -292,7 +292,7 @@ int nfc_dep_link_is_up(struct nfc_dev *dev, u32 target_idx, u8 comm_mode, u8 rf_mode); int nfc_tm_activated(struct nfc_dev *dev, u32 protocol, u8 comm_mode, - u8 *gb, size_t gb_len); + const u8 *gb, size_t gb_len); int nfc_tm_deactivated(struct nfc_dev *dev); int nfc_tm_data_received(struct nfc_dev *dev, struct sk_buff *skb); diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h index 60cc46f86634a8e31675649455506ce639d5d4ac..5c6c6f406d867bf5a83ecdeb16cc936e743e7e30 100644 --- a/include/net/pkt_sched.h +++ b/include/net/pkt_sched.h @@ -130,6 +130,8 @@ static inline void qdisc_run(struct Qdisc *q) } } +extern const struct nla_policy rtm_tca_policy[TCA_MAX + 1]; + extern int tc_qdisc_flow_control(struct net_device *dev, u32 tcm_handle, int flow_enable); /* Calculate maximal size of packet seen by hard_start_xmit @@ -137,7 +139,7 @@ extern int tc_qdisc_flow_control(struct net_device *dev, u32 tcm_handle, */ static inline unsigned int psched_mtu(const struct net_device *dev) { - return dev->mtu + dev->hard_header_len; + return READ_ONCE(dev->mtu) + dev->hard_header_len; } static inline struct net *qdisc_net(struct Qdisc *q) diff --git a/include/net/scm.h b/include/net/scm.h index 1ce365f4c25604b54eced20aec9a3e1ef78581a7..585adc1346bd0150c4e4bafb181cb87445c92564 100644 --- a/include/net/scm.h +++ b/include/net/scm.h @@ -105,16 +105,27 @@ static inline void scm_passec(struct socket *sock, struct msghdr *msg, struct sc } } } + +static inline bool scm_has_secdata(struct socket *sock) +{ + return test_bit(SOCK_PASSSEC, &sock->flags); +} #else static inline void scm_passec(struct socket *sock, struct msghdr *msg, struct scm_cookie *scm) { } + +static inline bool scm_has_secdata(struct socket *sock) +{ + return false; +} #endif /* CONFIG_SECURITY_NETWORK */ static __inline__ void scm_recv(struct socket *sock, struct msghdr *msg, struct scm_cookie *scm, int flags) { if (!msg->msg_control) { - if (test_bit(SOCK_PASSCRED, &sock->flags) || scm->fp) + if (test_bit(SOCK_PASSCRED, &sock->flags) || scm->fp || + scm_has_secdata(sock)) msg->msg_flags |= MSG_CTRUNC; scm_destroy(scm); return; diff --git a/include/net/sock.h b/include/net/sock.h index a371d1e1dafbfa940e9f2cefeba7c8b5bb42c114..31ed1db62ea21cdeac4ee8dfc685b1e2afad4e68 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1026,8 +1026,12 @@ static inline void sock_rps_record_flow(const struct sock *sk) * OR an additional socket flag * [1] : sk_state and sk_prot are in the same cache line. */ - if (sk->sk_state == TCP_ESTABLISHED) - sock_rps_record_flow_hash(sk->sk_rxhash); + if (sk->sk_state == TCP_ESTABLISHED) { + /* This READ_ONCE() is paired with the WRITE_ONCE() + * from sock_rps_save_rxhash() and sock_rps_reset_rxhash(). + */ + sock_rps_record_flow_hash(READ_ONCE(sk->sk_rxhash)); + } } #endif } @@ -1036,15 +1040,19 @@ static inline void sock_rps_save_rxhash(struct sock *sk, const struct sk_buff *skb) { #ifdef CONFIG_RPS - if (unlikely(sk->sk_rxhash != skb->hash)) - sk->sk_rxhash = skb->hash; + /* The following WRITE_ONCE() is paired with the READ_ONCE() + * here, and another one in sock_rps_record_flow(). + */ + if (unlikely(READ_ONCE(sk->sk_rxhash) != skb->hash)) + WRITE_ONCE(sk->sk_rxhash, skb->hash); #endif } static inline void sock_rps_reset_rxhash(struct sock *sk) { #ifdef CONFIG_RPS - sk->sk_rxhash = 0; + /* Paired with READ_ONCE() in sock_rps_record_flow() */ + WRITE_ONCE(sk->sk_rxhash, 0); #endif } @@ -1180,6 +1188,7 @@ struct proto { /* * Pressure flag: try to collapse. * Technical note: it is used by multiple contexts non atomically. + * Make sure to use READ_ONCE()/WRITE_ONCE() for all reads/writes. * All the __sk_mem_schedule() is of this nature: accounting * is strict, actions are advisory and have some latency. */ @@ -1283,6 +1292,12 @@ static inline bool sk_has_memory_pressure(const struct sock *sk) return sk->sk_prot->memory_pressure != NULL; } +static inline bool sk_under_global_memory_pressure(const struct sock *sk) +{ + return sk->sk_prot->memory_pressure && + !!READ_ONCE(*sk->sk_prot->memory_pressure); +} + static inline bool sk_under_memory_pressure(const struct sock *sk) { if (!sk->sk_prot->memory_pressure) @@ -1292,7 +1307,7 @@ static inline bool sk_under_memory_pressure(const struct sock *sk) mem_cgroup_under_socket_pressure(sk->sk_memcg)) return true; - return !!*sk->sk_prot->memory_pressure; + return !!READ_ONCE(*sk->sk_prot->memory_pressure); } static inline long @@ -1346,7 +1361,7 @@ proto_memory_pressure(struct proto *prot) { if (!prot->memory_pressure) return false; - return !!*prot->memory_pressure; + return !!READ_ONCE(*prot->memory_pressure); } @@ -1718,7 +1733,12 @@ void sk_common_release(struct sock *sk); * Default socket callbacks and setup code */ -/* Initialise core socket variables */ +/* Initialise core socket variables using an explicit uid. */ +void sock_init_data_uid(struct socket *sock, struct sock *sk, kuid_t uid); + +/* Initialise core socket variables + * Assumes struct socket *sock is embedded in a struct socket_alloc. + */ void sock_init_data(struct socket *sock, struct sock *sk); /* @@ -1770,21 +1790,33 @@ static inline void sk_tx_queue_set(struct sock *sk, int tx_queue) /* sk_tx_queue_mapping accept only upto a 16-bit value */ if (WARN_ON_ONCE((unsigned short)tx_queue >= USHRT_MAX)) return; - sk->sk_tx_queue_mapping = tx_queue; + /* Paired with READ_ONCE() in sk_tx_queue_get() and + * other WRITE_ONCE() because socket lock might be not held. + */ + WRITE_ONCE(sk->sk_tx_queue_mapping, tx_queue); } #define NO_QUEUE_MAPPING USHRT_MAX static inline void sk_tx_queue_clear(struct sock *sk) { - sk->sk_tx_queue_mapping = NO_QUEUE_MAPPING; + /* Paired with READ_ONCE() in sk_tx_queue_get() and + * other WRITE_ONCE() because socket lock might be not held. + */ + WRITE_ONCE(sk->sk_tx_queue_mapping, NO_QUEUE_MAPPING); } static inline int sk_tx_queue_get(const struct sock *sk) { - if (sk && sk->sk_tx_queue_mapping != NO_QUEUE_MAPPING) - return sk->sk_tx_queue_mapping; + if (sk) { + /* Paired with WRITE_ONCE() in sk_tx_queue_clear() + * and sk_tx_queue_set(). + */ + int val = READ_ONCE(sk->sk_tx_queue_mapping); + if (val != NO_QUEUE_MAPPING) + return val; + } return -1; } @@ -1858,6 +1890,7 @@ static inline void sock_graft(struct sock *sk, struct socket *parent) } kuid_t sock_i_uid(struct sock *sk); +unsigned long __sock_i_ino(struct sock *sk); unsigned long sock_i_ino(struct sock *sk); static inline kuid_t sock_net_uid(const struct net *net, const struct sock *sk) @@ -1916,7 +1949,7 @@ static inline void dst_negative_advice(struct sock *sk) if (ndst != dst) { rcu_assign_pointer(sk->sk_dst_cache, ndst); sk_tx_queue_clear(sk); - sk->sk_dst_pending_confirm = 0; + WRITE_ONCE(sk->sk_dst_pending_confirm, 0); } } } @@ -1927,7 +1960,7 @@ __sk_dst_set(struct sock *sk, struct dst_entry *dst) struct dst_entry *old_dst; sk_tx_queue_clear(sk); - sk->sk_dst_pending_confirm = 0; + WRITE_ONCE(sk->sk_dst_pending_confirm, 0); old_dst = rcu_dereference_protected(sk->sk_dst_cache, lockdep_sock_is_held(sk)); rcu_assign_pointer(sk->sk_dst_cache, dst); @@ -1940,7 +1973,7 @@ sk_dst_set(struct sock *sk, struct dst_entry *dst) struct dst_entry *old_dst; sk_tx_queue_clear(sk); - sk->sk_dst_pending_confirm = 0; + WRITE_ONCE(sk->sk_dst_pending_confirm, 0); old_dst = xchg((__force struct dst_entry **)&sk->sk_dst_cache, dst); dst_release(old_dst); } @@ -2451,7 +2484,7 @@ static inline void sock_recv_ts_and_drops(struct msghdr *msg, struct sock *sk, __sock_recv_ts_and_drops(msg, sk, skb); else if (unlikely(sock_flag(sk, SOCK_TIMESTAMP))) sock_write_timestamp(sk, skb->tstamp); - else if (unlikely(sk->sk_stamp == SK_DEFAULT_STAMP)) + else if (unlikely(sock_read_timestamp(sk) == SK_DEFAULT_STAMP)) sock_write_timestamp(sk, 0); } diff --git a/include/net/tcp.h b/include/net/tcp.h index 2211a25af406992319a67882a1fe44b2e5c77ef9..5655de40aeeaaa70f4c879bd0acc2163637b7ec2 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -128,6 +128,7 @@ void tcp_time_wait(struct sock *sk, int state, int timeo); * to combine FIN-WAIT-2 timeout with * TIME-WAIT timer. */ +#define TCP_FIN_TIMEOUT_MAX (120 * HZ) /* max TCP_LINGER2 value (two minutes) */ #define TCP_DELACK_MAX ((unsigned)(HZ/5)) /* maximal time to delay before sending an ACK */ #if HZ >= 100 @@ -140,6 +141,9 @@ void tcp_time_wait(struct sock *sk, int state, int timeo); #define TCP_RTO_MAX ((unsigned)(120*HZ)) #define TCP_RTO_MIN ((unsigned)(HZ/5)) #define TCP_TIMEOUT_MIN (2U) /* Min timeout for TCP timers in jiffies */ + +#define TCP_TIMEOUT_MIN_US (2*USEC_PER_MSEC) /* Min TCP timeout in microsecs */ + #define TCP_TIMEOUT_INIT ((unsigned)(1*HZ)) /* RFC6298 2.1 initial RTO value */ #define TCP_TIMEOUT_FALLBACK ((unsigned)(3*HZ)) /* RFC 1122 initial RTO value, now * used as a fallback RTO for the @@ -365,13 +369,14 @@ extern int tcp_proc_delayed_ack_control(struct ctl_table *table, int write, void __user *buffer, size_t *length, loff_t *ppos); -void tcp_enter_quickack_mode(struct sock *sk, unsigned int max_quickacks); -static inline void tcp_dec_quickack_mode(struct sock *sk, - const unsigned int pkts) +static inline void tcp_dec_quickack_mode(struct sock *sk) { struct inet_connection_sock *icsk = inet_csk(sk); if (icsk->icsk_ack.quick) { + /* How many ACKs S/ACKing new data have we sent? */ + const unsigned int pkts = inet_csk_ack_scheduled(sk) ? 1 : 0; + if (pkts >= icsk->icsk_ack.quick) { icsk->icsk_ack.quick = 0; /* Leaving quickack mode we deflate ATO. */ @@ -1899,7 +1904,11 @@ void __tcp_v4_send_check(struct sk_buff *skb, __be32 saddr, __be32 daddr); static inline u32 tcp_notsent_lowat(const struct tcp_sock *tp) { struct net *net = sock_net((struct sock *)tp); - return tp->notsent_lowat ?: READ_ONCE(net->ipv4.sysctl_tcp_notsent_lowat); + u32 val; + + val = READ_ONCE(tp->notsent_lowat); + + return val ?: READ_ONCE(net->ipv4.sysctl_tcp_notsent_lowat); } static inline bool tcp_stream_memory_free(const struct sock *sk) diff --git a/include/net/udp.h b/include/net/udp.h index 8772bc33105ffd7c2e1270517657bfd420a8ac7d..07b4d7f81f8b656f5f242e42680b662d61f5a1ab 100644 --- a/include/net/udp.h +++ b/include/net/udp.h @@ -253,7 +253,7 @@ static inline int udp_rqueue_get(struct sock *sk) } /* net/ipv4/udp.c */ -void udp_destruct_sock(struct sock *sk); +void udp_destruct_common(struct sock *sk); void skb_consume_udp(struct sock *sk, struct sk_buff *skb, int len); int __udp_enqueue_schedule_skb(struct sock *sk, struct sk_buff *skb); void udp_skb_destructor(struct sock *sk, struct sk_buff *skb); diff --git a/include/net/udplite.h b/include/net/udplite.h index 9185e45b997ff67ce2999c6b0665c8d693b44338..c59ba86668af0e5734195263a8080f3e1f44a0a6 100644 --- a/include/net/udplite.h +++ b/include/net/udplite.h @@ -24,14 +24,6 @@ static __inline__ int udplite_getfrag(void *from, char *to, int offset, return copy_from_iter_full(to, len, &msg->msg_iter) ? 0 : -EFAULT; } -/* Designate sk as UDP-Lite socket */ -static inline int udplite_sk_init(struct sock *sk) -{ - udp_init_sock(sk); - udp_sk(sk)->pcflag = UDPLITE_BIT; - return 0; -} - /* * Checksumming routines */ diff --git a/include/scsi/scsi_host.h b/include/scsi/scsi_host.h index 0c750a8666d363e736a1f783dfe4a90d0e25c2ec..c743fcb2b1a5de8d259ed37170d3d31a2aea5f8e 100644 --- a/include/scsi/scsi_host.h +++ b/include/scsi/scsi_host.h @@ -775,7 +775,7 @@ extern void scsi_remove_host(struct Scsi_Host *); extern struct Scsi_Host *scsi_host_get(struct Scsi_Host *); extern int scsi_host_busy(struct Scsi_Host *shost); extern void scsi_host_put(struct Scsi_Host *t); -extern struct Scsi_Host *scsi_host_lookup(unsigned short); +extern struct Scsi_Host *scsi_host_lookup(unsigned int hostnum); extern const char *scsi_host_state_name(enum scsi_host_state); extern void scsi_cmd_get_serial(struct Scsi_Host *, struct scsi_cmnd *); diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h index 6dd0afe939d1da10ee006ede95c409e96439154b..70aa770f6da70d1c1b11310d388737345390597e 100644 --- a/include/soc/qcom/socinfo.h +++ b/include/soc/qcom/socinfo.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2009-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _ARCH_ARM_MACH_MSM_SOCINFO_H_ @@ -13,6 +14,64 @@ #include #include + +enum feature_code { + /* External feature code */ + SOCINFO_FC_UNKNOWN = 0x0, + SOCINFO_FC_AA, + SOCINFO_FC_AB, + SOCINFO_FC_AC, + SOCINFO_FC_AD, + SOCINFO_FC_AE, + SOCINFO_FC_AF, + SOCINFO_FC_AG, + SOCINFO_FC_AH, + SOCINFO_FC_EXT_RESERVE, + + /* Internal feature code */ + SOCINFO_FC_Y0 = 0xf1, + SOCINFO_FC_Y1, + SOCINFO_FC_Y2, + SOCINFO_FC_Y3, + SOCINFO_FC_Y4, + SOCINFO_FC_Y5, + SOCINFO_FC_Y6, + SOCINFO_FC_Y7, + SOCINFO_FC_INT_RESERVE +}; + +enum pcode { + SOCINFO_PCODE_UNKNOWN = 0, + SOCINFO_PCODE_0, + SOCINFO_PCODE_1, + SOCINFO_PCODE_2, + SOCINFO_PCODE_3, + SOCINFO_PCODE_4, + SOCINFO_PCODE_5, + SOCINFO_PCODE_6, + SOCINFO_PCODE_7, + SOCINFO_PCODE_8, + SOCINFO_PCODE_RESERVE = 0x7fffffff +}; + +enum socinfo_parttype { + SOCINFO_PART_GPU, + SOCINFO_PART_VIDEO, + SOCINFO_PART_CAMERA, + SOCINFO_PART_DISPLAY, + SOCINFO_PART_AUDIO, + SOCINFO_PART_MODEM, + SOCINFO_PART_WLAN, + SOCINFO_PART_COMP, + SOCINFO_PART_SENSORS, + SOCINFO_PART_NPU, + SOCINFO_PART_SPSS, + SOCINFO_PART_NAV, + SOCINFO_PART_COMPUTE_1, + SOCINFO_PART_DISPLAY_1, + SOCINFO_PART_MAX_PARTTYPE +}; + /* * SOC version type with major number in the upper 16 bits and minor * number in the lower 16 bits. For example: @@ -110,6 +169,8 @@ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msm8953") #define early_machine_is_sdm450() \ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sdm450") +#define early_machine_is_qcm2150() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,qcm2150") #else #define of_board_is_sim() 0 #define of_board_is_rumi() 0 @@ -158,6 +219,7 @@ #define early_machine_is_qm215() 0 #define early_machine_is_msm8953() 0 #define early_machine_is_sdm450() 0 +#define early_machine_is_qcm2150() 0 #endif #define PLATFORM_SUBTYPE_MDM 1 @@ -209,6 +271,7 @@ enum msm_cpu { MSM_CPU_QM215, MSM_CPU_8953, MSM_CPU_SDM450, + MSM_CPU_QCM2150, }; struct msm_soc_info { @@ -272,5 +335,8 @@ bool socinfo_get_part_info(enum subset_part_type part); enum pmic_model socinfo_get_pmic_model(void); uint32_t socinfo_get_pmic_die_revision(void); int __init socinfo_init(void) __must_check; +int socinfo_get_feature_code(void); +int socinfo_get_pcode(void); +char *socinfo_get_partinfo_details(unsigned int part_id); #endif diff --git a/include/trace/events/f2fs.h b/include/trace/events/f2fs.h index b7119a975d0a4f7b02fab62786f17dd4a5ce2e07..7053907de5130946170f19d48f490ea425387a73 100644 --- a/include/trace/events/f2fs.h +++ b/include/trace/events/f2fs.h @@ -519,7 +519,7 @@ TRACE_EVENT(f2fs_truncate_partial_nodes, TP_STRUCT__entry( __field(dev_t, dev) __field(ino_t, ino) - __field(nid_t, nid[3]) + __array(nid_t, nid, 3) __field(int, depth) __field(int, err) ), diff --git a/include/trace/events/timer.h b/include/trace/events/timer.h index a57e4ee989d6229476471c5527a44b230014926c..350b046e7576c917b11e5961ddef69aa822c5909 100644 --- a/include/trace/events/timer.h +++ b/include/trace/events/timer.h @@ -362,7 +362,8 @@ TRACE_EVENT(itimer_expire, tick_dep_name(POSIX_TIMER) \ tick_dep_name(PERF_EVENTS) \ tick_dep_name(SCHED) \ - tick_dep_name_end(CLOCK_UNSTABLE) + tick_dep_name(CLOCK_UNSTABLE) \ + tick_dep_name_end(RCU) #undef tick_dep_name #undef tick_dep_mask_name diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 1ceec56de0157671c6a42af07322ffb7fb8e1731..b72aeb766fc7a1d013ac8d3ed48addfe4353a8b1 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -272,13 +272,14 @@ union drm_amdgpu_vm { /* sched ioctl */ #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 +#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 struct drm_amdgpu_sched_in { /* AMDGPU_SCHED_OP_* */ __u32 op; __u32 fd; __s32 priority; - __u32 flags; + __u32 ctx_id; }; union drm_amdgpu_sched { diff --git a/include/uapi/linux/affs_hardblocks.h b/include/uapi/linux/affs_hardblocks.h index 5e2fb8481252a6e20e5d0b62cfd412e8f932dd9a..a5aff2eb5f708137e32afc79291a06473f1df098 100644 --- a/include/uapi/linux/affs_hardblocks.h +++ b/include/uapi/linux/affs_hardblocks.h @@ -7,42 +7,42 @@ /* Just the needed definitions for the RDB of an Amiga HD. */ struct RigidDiskBlock { - __u32 rdb_ID; + __be32 rdb_ID; __be32 rdb_SummedLongs; - __s32 rdb_ChkSum; - __u32 rdb_HostID; + __be32 rdb_ChkSum; + __be32 rdb_HostID; __be32 rdb_BlockBytes; - __u32 rdb_Flags; - __u32 rdb_BadBlockList; + __be32 rdb_Flags; + __be32 rdb_BadBlockList; __be32 rdb_PartitionList; - __u32 rdb_FileSysHeaderList; - __u32 rdb_DriveInit; - __u32 rdb_Reserved1[6]; - __u32 rdb_Cylinders; - __u32 rdb_Sectors; - __u32 rdb_Heads; - __u32 rdb_Interleave; - __u32 rdb_Park; - __u32 rdb_Reserved2[3]; - __u32 rdb_WritePreComp; - __u32 rdb_ReducedWrite; - __u32 rdb_StepRate; - __u32 rdb_Reserved3[5]; - __u32 rdb_RDBBlocksLo; - __u32 rdb_RDBBlocksHi; - __u32 rdb_LoCylinder; - __u32 rdb_HiCylinder; - __u32 rdb_CylBlocks; - __u32 rdb_AutoParkSeconds; - __u32 rdb_HighRDSKBlock; - __u32 rdb_Reserved4; + __be32 rdb_FileSysHeaderList; + __be32 rdb_DriveInit; + __be32 rdb_Reserved1[6]; + __be32 rdb_Cylinders; + __be32 rdb_Sectors; + __be32 rdb_Heads; + __be32 rdb_Interleave; + __be32 rdb_Park; + __be32 rdb_Reserved2[3]; + __be32 rdb_WritePreComp; + __be32 rdb_ReducedWrite; + __be32 rdb_StepRate; + __be32 rdb_Reserved3[5]; + __be32 rdb_RDBBlocksLo; + __be32 rdb_RDBBlocksHi; + __be32 rdb_LoCylinder; + __be32 rdb_HiCylinder; + __be32 rdb_CylBlocks; + __be32 rdb_AutoParkSeconds; + __be32 rdb_HighRDSKBlock; + __be32 rdb_Reserved4; char rdb_DiskVendor[8]; char rdb_DiskProduct[16]; char rdb_DiskRevision[4]; char rdb_ControllerVendor[8]; char rdb_ControllerProduct[16]; char rdb_ControllerRevision[4]; - __u32 rdb_Reserved5[10]; + __be32 rdb_Reserved5[10]; }; #define IDNAME_RIGIDDISK 0x5244534B /* "RDSK" */ @@ -50,16 +50,16 @@ struct RigidDiskBlock { struct PartitionBlock { __be32 pb_ID; __be32 pb_SummedLongs; - __s32 pb_ChkSum; - __u32 pb_HostID; + __be32 pb_ChkSum; + __be32 pb_HostID; __be32 pb_Next; - __u32 pb_Flags; - __u32 pb_Reserved1[2]; - __u32 pb_DevFlags; + __be32 pb_Flags; + __be32 pb_Reserved1[2]; + __be32 pb_DevFlags; __u8 pb_DriveName[32]; - __u32 pb_Reserved2[15]; + __be32 pb_Reserved2[15]; __be32 pb_Environment[17]; - __u32 pb_EReserved[15]; + __be32 pb_EReserved[15]; }; #define IDNAME_PARTITION 0x50415254 /* "PART" */ diff --git a/include/uapi/linux/blkzoned.h b/include/uapi/linux/blkzoned.h index ff5a5db8906a7c90dd44b40f2a48a10ba6ca40b6..2f3a0cca4b78bcdf5e8cdcf09b3269ce6169a823 100644 --- a/include/uapi/linux/blkzoned.h +++ b/include/uapi/linux/blkzoned.h @@ -51,13 +51,13 @@ enum blk_zone_type { * * The Zone Condition state machine in the ZBC/ZAC standards maps the above * deinitions as: - * - ZC1: Empty | BLK_ZONE_EMPTY + * - ZC1: Empty | BLK_ZONE_COND_EMPTY * - ZC2: Implicit Open | BLK_ZONE_COND_IMP_OPEN * - ZC3: Explicit Open | BLK_ZONE_COND_EXP_OPEN - * - ZC4: Closed | BLK_ZONE_CLOSED - * - ZC5: Full | BLK_ZONE_FULL - * - ZC6: Read Only | BLK_ZONE_READONLY - * - ZC7: Offline | BLK_ZONE_OFFLINE + * - ZC4: Closed | BLK_ZONE_COND_CLOSED + * - ZC5: Full | BLK_ZONE_COND_FULL + * - ZC6: Read Only | BLK_ZONE_COND_READONLY + * - ZC7: Offline | BLK_ZONE_COND_OFFLINE * * Conditions 0x5 to 0xC are reserved by the current ZBC/ZAC spec and should * be considered invalid. diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h index 8b9fb412fbe567b906d8471e013294b1b241598c..17cff15efcdf9612261825942c68353948751e47 100644 --- a/include/uapi/linux/bpf.h +++ b/include/uapi/linux/bpf.h @@ -695,7 +695,9 @@ union bpf_attr { * performed again, if the helper is used in combination with * direct packet access. * Return - * 0 on success, or a negative error in case of failure. + * 0 on success, or a negative error in case of failure. Positive + * error indicates a potential drop or congestion in the target + * device. The particular positive error codes are not defined. * * u64 bpf_get_current_pid_tgid(void) * Return diff --git a/include/uapi/linux/btrfs.h b/include/uapi/linux/btrfs.h index 5ca1d21fc4a7a85db1bd9c8cf15e5f334d8e59d6..dd7a7b3e53f4bf3b633806fe06d914982514130d 100644 --- a/include/uapi/linux/btrfs.h +++ b/include/uapi/linux/btrfs.h @@ -162,6 +162,7 @@ struct btrfs_scrub_progress { }; #define BTRFS_SCRUB_READONLY 1 +#define BTRFS_SCRUB_SUPPORTED_FLAGS (BTRFS_SCRUB_READONLY) struct btrfs_ioctl_scrub_args { __u64 devid; /* in */ __u64 start; /* in */ diff --git a/include/uapi/linux/dn.h b/include/uapi/linux/dn.h deleted file mode 100644 index 36ca71bd8bbe233ed11fbbc9d76ad387122e1124..0000000000000000000000000000000000000000 --- a/include/uapi/linux/dn.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _LINUX_DN_H -#define _LINUX_DN_H - -#include -#include -#include - -/* - - DECnet Data Structures and Constants - -*/ - -/* - * DNPROTO_NSP can't be the same as SOL_SOCKET, - * so increment each by one (compared to ULTRIX) - */ -#define DNPROTO_NSP 2 /* NSP protocol number */ -#define DNPROTO_ROU 3 /* Routing protocol number */ -#define DNPROTO_NML 4 /* Net mgt protocol number */ -#define DNPROTO_EVL 5 /* Evl protocol number (usr) */ -#define DNPROTO_EVR 6 /* Evl protocol number (evl) */ -#define DNPROTO_NSPT 7 /* NSP trace protocol number */ - - -#define DN_ADDL 2 -#define DN_MAXADDL 2 /* ULTRIX headers have 20 here, but pathworks has 2 */ -#define DN_MAXOPTL 16 -#define DN_MAXOBJL 16 -#define DN_MAXACCL 40 -#define DN_MAXALIASL 128 -#define DN_MAXNODEL 256 -#define DNBUFSIZE 65023 - -/* - * SET/GET Socket options - must match the DSO_ numbers below - */ -#define SO_CONDATA 1 -#define SO_CONACCESS 2 -#define SO_PROXYUSR 3 -#define SO_LINKINFO 7 - -#define DSO_CONDATA 1 /* Set/Get connect data */ -#define DSO_DISDATA 10 /* Set/Get disconnect data */ -#define DSO_CONACCESS 2 /* Set/Get connect access data */ -#define DSO_ACCEPTMODE 4 /* Set/Get accept mode */ -#define DSO_CONACCEPT 5 /* Accept deferred connection */ -#define DSO_CONREJECT 6 /* Reject deferred connection */ -#define DSO_LINKINFO 7 /* Set/Get link information */ -#define DSO_STREAM 8 /* Set socket type to stream */ -#define DSO_SEQPACKET 9 /* Set socket type to sequenced packet */ -#define DSO_MAXWINDOW 11 /* Maximum window size allowed */ -#define DSO_NODELAY 12 /* Turn off nagle */ -#define DSO_CORK 13 /* Wait for more data! */ -#define DSO_SERVICES 14 /* NSP Services field */ -#define DSO_INFO 15 /* NSP Info field */ -#define DSO_MAX 15 /* Maximum option number */ - - -/* LINK States */ -#define LL_INACTIVE 0 -#define LL_CONNECTING 1 -#define LL_RUNNING 2 -#define LL_DISCONNECTING 3 - -#define ACC_IMMED 0 -#define ACC_DEFER 1 - -#define SDF_WILD 1 /* Wild card object */ -#define SDF_PROXY 2 /* Addr eligible for proxy */ -#define SDF_UICPROXY 4 /* Use uic-based proxy */ - -/* Structures */ - - -struct dn_naddr { - __le16 a_len; - __u8 a_addr[DN_MAXADDL]; /* Two bytes little endian */ -}; - -struct sockaddr_dn { - __u16 sdn_family; - __u8 sdn_flags; - __u8 sdn_objnum; - __le16 sdn_objnamel; - __u8 sdn_objname[DN_MAXOBJL]; - struct dn_naddr sdn_add; -}; -#define sdn_nodeaddrl sdn_add.a_len /* Node address length */ -#define sdn_nodeaddr sdn_add.a_addr /* Node address */ - - - -/* - * DECnet set/get DSO_CONDATA, DSO_DISDATA (optional data) structure - */ -struct optdata_dn { - __le16 opt_status; /* Extended status return */ -#define opt_sts opt_status - __le16 opt_optl; /* Length of user data */ - __u8 opt_data[16]; /* User data */ -}; - -struct accessdata_dn { - __u8 acc_accl; - __u8 acc_acc[DN_MAXACCL]; - __u8 acc_passl; - __u8 acc_pass[DN_MAXACCL]; - __u8 acc_userl; - __u8 acc_user[DN_MAXACCL]; -}; - -/* - * DECnet logical link information structure - */ -struct linkinfo_dn { - __u16 idn_segsize; /* Segment size for link */ - __u8 idn_linkstate; /* Logical link state */ -}; - -/* - * Ethernet address format (for DECnet) - */ -union etheraddress { - __u8 dne_addr[ETH_ALEN]; /* Full ethernet address */ - struct { - __u8 dne_hiord[4]; /* DECnet HIORD prefix */ - __u8 dne_nodeaddr[2]; /* DECnet node address */ - } dne_remote; -}; - - -/* - * DECnet physical socket address format - */ -struct dn_addr { - __le16 dna_family; /* AF_DECnet */ - union etheraddress dna_netaddr; /* DECnet ethernet address */ -}; - -#define DECNET_IOCTL_BASE 0x89 /* PROTOPRIVATE range */ - -#define SIOCSNETADDR _IOW(DECNET_IOCTL_BASE, 0xe0, struct dn_naddr) -#define SIOCGNETADDR _IOR(DECNET_IOCTL_BASE, 0xe1, struct dn_naddr) -#define OSIOCSNETADDR _IOW(DECNET_IOCTL_BASE, 0xe0, int) -#define OSIOCGNETADDR _IOR(DECNET_IOCTL_BASE, 0xe1, int) - -#endif /* _LINUX_DN_H */ diff --git a/include/uapi/linux/in.h b/include/uapi/linux/in.h index 2a66ab49f14dd25b08b8d64ab8ee87e6f4e4a606..b4f95eb8cdcd2e477d3e40fa5097a08b4c906c3c 100644 --- a/include/uapi/linux/in.h +++ b/include/uapi/linux/in.h @@ -154,6 +154,8 @@ struct in_addr { #define MCAST_MSFILTER 48 #define IP_MULTICAST_ALL 49 #define IP_UNICAST_IF 50 +#define IP_LOCAL_PORT_RANGE 51 +#define IP_PROTOCOL 52 #define MCAST_EXCLUDE 0 #define MCAST_INCLUDE 1 diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h index d6a5a3bfe6c433abc6f9052fc3cfb3849f8ab605..be53a8c1a2dff1bcc4bdad5a42a6f491d932cff6 100644 --- a/include/uapi/linux/media-bus-format.h +++ b/include/uapi/linux/media-bus-format.h @@ -153,4 +153,12 @@ /* HSV - next is 0x6002 */ #define MEDIA_BUS_FMT_AHSV8888_1X32 0x6001 +/* + * This format should be used when the same driver handles + * both sides of the link and the bus format is a fixed + * metadata format that is not configurable from userspace. + * Width and height will be set to 0 for this format. + */ +#define MEDIA_BUS_FMT_METADATA_FIXED 0x7001 + #endif /* __LINUX_MEDIA_BUS_FORMAT_H */ diff --git a/include/uapi/linux/netfilter_decnet.h b/include/uapi/linux/netfilter_decnet.h deleted file mode 100644 index 61f1c7dfd03307728988812be50af14a35d5a5c7..0000000000000000000000000000000000000000 --- a/include/uapi/linux/netfilter_decnet.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef __LINUX_DECNET_NETFILTER_H -#define __LINUX_DECNET_NETFILTER_H - -/* DECnet-specific defines for netfilter. - * This file (C) Steve Whitehouse 1999 derived from the - * ipv4 netfilter header file which is - * (C)1998 Rusty Russell -- This code is GPL. - */ - -#include - -/* only for userspace compatibility */ -#ifndef __KERNEL__ - -#include /* for INT_MIN, INT_MAX */ - -/* IP Cache bits. */ -/* Src IP address. */ -#define NFC_DN_SRC 0x0001 -/* Dest IP address. */ -#define NFC_DN_DST 0x0002 -/* Input device. */ -#define NFC_DN_IF_IN 0x0004 -/* Output device. */ -#define NFC_DN_IF_OUT 0x0008 - -/* kernel define is in netfilter_defs.h */ -#define NF_DN_NUMHOOKS 7 -#endif /* ! __KERNEL__ */ - -/* DECnet Hooks */ -/* After promisc drops, checksum checks. */ -#define NF_DN_PRE_ROUTING 0 -/* If the packet is destined for this box. */ -#define NF_DN_LOCAL_IN 1 -/* If the packet is destined for another interface. */ -#define NF_DN_FORWARD 2 -/* Packets coming from a local process. */ -#define NF_DN_LOCAL_OUT 3 -/* Packets about to hit the wire. */ -#define NF_DN_POST_ROUTING 4 -/* Input Hello Packets */ -#define NF_DN_HELLO 5 -/* Input Routing Packets */ -#define NF_DN_ROUTE 6 - -enum nf_dn_hook_priorities { - NF_DN_PRI_FIRST = INT_MIN, - NF_DN_PRI_CONNTRACK = -200, - NF_DN_PRI_MANGLE = -150, - NF_DN_PRI_NAT_DST = -100, - NF_DN_PRI_FILTER = 0, - NF_DN_PRI_NAT_SRC = 100, - NF_DN_PRI_DNRTMSG = 200, - NF_DN_PRI_LAST = INT_MAX, -}; - -struct nf_dn_rtmsg { - int nfdn_ifindex; -}; - -#define NFDN_RTMSG(r) ((unsigned char *)(r) + NLMSG_ALIGN(sizeof(struct nf_dn_rtmsg))) - -#ifndef __KERNEL__ -/* backwards compatibility for userspace */ -#define DNRMG_L1_GROUP 0x01 -#define DNRMG_L2_GROUP 0x02 -#endif - -enum { - DNRNG_NLGRP_NONE, -#define DNRNG_NLGRP_NONE DNRNG_NLGRP_NONE - DNRNG_NLGRP_L1, -#define DNRNG_NLGRP_L1 DNRNG_NLGRP_L1 - DNRNG_NLGRP_L2, -#define DNRNG_NLGRP_L2 DNRNG_NLGRP_L2 - __DNRNG_NLGRP_MAX -}; -#define DNRNG_NLGRP_MAX (__DNRNG_NLGRP_MAX - 1) - -#endif /*__LINUX_DECNET_NETFILTER_H*/ diff --git a/include/uapi/linux/netlink.h b/include/uapi/linux/netlink.h index 9b15a400be6420af5b4a38c79b7427f197771932..9624bf9f1e87a805e13b28cd7d7ee8a952b9d231 100644 --- a/include/uapi/linux/netlink.h +++ b/include/uapi/linux/netlink.h @@ -21,7 +21,7 @@ #define NETLINK_CONNECTOR 11 #define NETLINK_NETFILTER 12 /* netfilter subsystem */ #define NETLINK_IP6_FW 13 -#define NETLINK_DNRTMSG 14 /* DECnet routing messages */ +#define NETLINK_DNRTMSG 14 /* DECnet routing messages (obsolete) */ #define NETLINK_KOBJECT_UEVENT 15 /* Kernel messages to userspace */ #define NETLINK_GENERIC 16 /* leave room for NETLINK_DM (DM Events) */ diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 8d2767140798b3f84d34c3149660c24ba1f5eab5..39c69235a384343d2a9b55ad49697faee2f6bd92 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* - * pci_regs.h - * * PCI standard defines * Copyright 1994, Drew Eckhardt * Copyright 1997--1999 Martin Mares @@ -15,7 +13,7 @@ * PCI System Design Guide * * For HyperTransport information, please consult the following manuals - * from http://www.hypertransport.org + * from http://www.hypertransport.org : * * The HyperTransport I/O Link Specification */ @@ -300,7 +298,7 @@ #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ -/* Message Signalled Interrupts registers */ +/* Message Signalled Interrupt registers */ #define PCI_MSI_FLAGS 2 /* Message Control */ #define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */ @@ -318,7 +316,7 @@ #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ #define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */ -/* MSI-X registers */ +/* MSI-X registers (in MSI-X capability) */ #define PCI_MSIX_FLAGS 2 /* Message Control */ #define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */ #define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */ @@ -332,13 +330,13 @@ #define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */ #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ -/* MSI-X Table entry format */ +/* MSI-X Table entry format (in memory mapped by a BAR) */ #define PCI_MSIX_ENTRY_SIZE 16 -#define PCI_MSIX_ENTRY_LOWER_ADDR 0 -#define PCI_MSIX_ENTRY_UPPER_ADDR 4 -#define PCI_MSIX_ENTRY_DATA 8 -#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 -#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 +#define PCI_MSIX_ENTRY_LOWER_ADDR 0 /* Message Address */ +#define PCI_MSIX_ENTRY_UPPER_ADDR 4 /* Message Upper Address */ +#define PCI_MSIX_ENTRY_DATA 8 /* Message Data */ +#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 /* Vector Control */ +#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001 /* CompactPCI Hotswap Register */ @@ -464,19 +462,19 @@ /* PCI Express capability registers */ #define PCI_EXP_FLAGS 2 /* Capabilities register */ -#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ -#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ -#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ -#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ -#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ -#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ -#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */ -#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ -#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ -#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ -#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ -#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ +#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ +#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ +#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ +#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ +#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */ +#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ +#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ +#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ +#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ +#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ #define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */ #define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */ @@ -529,6 +527,7 @@ #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ +#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */ #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ @@ -557,6 +556,7 @@ #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ #define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ +#define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */ #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ #define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ #define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ @@ -621,8 +621,8 @@ #define PCI_EXP_RTCAP 30 /* Root Capabilities */ #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ #define PCI_EXP_RTSTA 32 /* Root Status */ -#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ -#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ +#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ +#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ /* * The Device Capabilities 2, Device Status 2, Device Control 2, * Link Capabilities 2, Link Status 2, Link Control 2, @@ -642,13 +642,13 @@ #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ -#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */ +#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */ #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ -#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ -#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */ +#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ +#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */ #define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ #define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ #define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ @@ -662,13 +662,17 @@ #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */ #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ +#define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */ #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ -#define PCI_EXP_LNKCTL2_TLS 0x000f -#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ -#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ -#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ -#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ +#define PCI_EXP_LNKCTL2_TLS 0x000f +#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ +#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ +#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ +#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ +#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ +#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ +#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ @@ -757,18 +761,18 @@ #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ -#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */ -#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */ -#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */ +#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */ +#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */ +#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */ #define PCI_ERR_ROOT_STATUS 48 -#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ -#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */ -#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */ -#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */ -#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */ -#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ -#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ -#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ +#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ +#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */ +#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */ +#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */ +#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */ +#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ +#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ +#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ /* Virtual Channel */ @@ -879,12 +883,13 @@ /* Page Request Interface */ #define PCI_PRI_CTRL 0x04 /* PRI control register */ -#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */ -#define PCI_PRI_CTRL_RESET 0x02 /* Reset */ +#define PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */ +#define PCI_PRI_CTRL_RESET 0x0002 /* Reset */ #define PCI_PRI_STATUS 0x06 /* PRI status register */ -#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ -#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ -#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ +#define PCI_PRI_STATUS_RF 0x0001 /* Response Failure */ +#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */ +#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */ +#define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */ #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ #define PCI_EXT_CAP_PRI_SIZEOF 16 @@ -901,16 +906,16 @@ /* Single Root I/O Virtualization */ #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ -#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ +#define PCI_SRIOV_CAP_VFM 0x00000001 /* VF Migration Capable */ #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ -#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ -#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */ -#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */ -#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ -#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ +#define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */ +#define PCI_SRIOV_CTRL_VFM 0x0002 /* VF Migration Enable */ +#define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */ +#define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */ +#define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */ #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ -#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */ +#define PCI_SRIOV_STATUS_VFM 0x0001 /* VF Migration Status */ #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ @@ -940,13 +945,13 @@ /* Access Control Service */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ -#define PCI_ACS_SV 0x01 /* Source Validation */ -#define PCI_ACS_TB 0x02 /* Translation Blocking */ -#define PCI_ACS_RR 0x04 /* P2P Request Redirect */ -#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */ -#define PCI_ACS_UF 0x10 /* Upstream Forwarding */ -#define PCI_ACS_EC 0x20 /* P2P Egress Control */ -#define PCI_ACS_DT 0x40 /* Direct Translated P2P */ +#define PCI_ACS_SV 0x0001 /* Source Validation */ +#define PCI_ACS_TB 0x0002 /* Translation Blocking */ +#define PCI_ACS_RR 0x0004 /* P2P Request Redirect */ +#define PCI_ACS_CR 0x0008 /* P2P Completion Redirect */ +#define PCI_ACS_UF 0x0010 /* Upstream Forwarding */ +#define PCI_ACS_EC 0x0020 /* P2P Egress Control */ +#define PCI_ACS_DT 0x0040 /* Direct Translated P2P */ #define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ @@ -996,9 +1001,9 @@ #define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */ #define PCI_EXP_DPC_CTL 6 /* DPC control */ -#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */ -#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */ -#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */ +#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */ +#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */ +#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */ #define PCI_EXP_DPC_STATUS 8 /* DPC Status */ #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ diff --git a/include/uapi/linux/sync_file.h b/include/uapi/linux/sync_file.h index ee2dcfb3d66028993ccea134ea93e19f6d925314..d7f7c04a6e0c181b1a8983c82c89352733a2b832 100644 --- a/include/uapi/linux/sync_file.h +++ b/include/uapi/linux/sync_file.h @@ -52,7 +52,7 @@ struct sync_fence_info { * @name: name of fence * @status: status of fence. 1: signaled 0:active <0:error * @flags: sync_file_info flags - * @num_fences number of fences in the sync_file + * @num_fences: number of fences in the sync_file * @pad: padding for 64-bit alignment, should always be zero * @sync_fence_info: pointer to array of structs sync_fence_info with all * fences in the sync_file diff --git a/include/uapi/linux/usb/video.h b/include/uapi/linux/usb/video.h index b9cc53a94cab60a561a6d3bb643ff0b0091900de..21a16e44d7e109840be1f257d1c298f8f53764f0 100644 --- a/include/uapi/linux/usb/video.h +++ b/include/uapi/linux/usb/video.h @@ -181,6 +181,36 @@ #define UVC_CONTROL_CAP_AUTOUPDATE (1 << 3) #define UVC_CONTROL_CAP_ASYNCHRONOUS (1 << 4) +/* 3.9.2.6 Color Matching Descriptor Values */ +enum uvc_color_primaries_values { + UVC_COLOR_PRIMARIES_UNSPECIFIED, + UVC_COLOR_PRIMARIES_BT_709_SRGB, + UVC_COLOR_PRIMARIES_BT_470_2_M, + UVC_COLOR_PRIMARIES_BT_470_2_B_G, + UVC_COLOR_PRIMARIES_SMPTE_170M, + UVC_COLOR_PRIMARIES_SMPTE_240M, +}; + +enum uvc_transfer_characteristics_values { + UVC_TRANSFER_CHARACTERISTICS_UNSPECIFIED, + UVC_TRANSFER_CHARACTERISTICS_BT_709, + UVC_TRANSFER_CHARACTERISTICS_BT_470_2_M, + UVC_TRANSFER_CHARACTERISTICS_BT_470_2_B_G, + UVC_TRANSFER_CHARACTERISTICS_SMPTE_170M, + UVC_TRANSFER_CHARACTERISTICS_SMPTE_240M, + UVC_TRANSFER_CHARACTERISTICS_LINEAR, + UVC_TRANSFER_CHARACTERISTICS_SRGB, +}; + +enum uvc_matrix_coefficients { + UVC_MATRIX_COEFFICIENTS_UNSPECIFIED, + UVC_MATRIX_COEFFICIENTS_BT_709, + UVC_MATRIX_COEFFICIENTS_FCC, + UVC_MATRIX_COEFFICIENTS_BT_470_2_B_G, + UVC_MATRIX_COEFFICIENTS_SMPTE_170M, + UVC_MATRIX_COEFFICIENTS_SMPTE_240M, +}; + /* ------------------------------------------------------------------------ * UVC structures */ diff --git a/include/uapi/linux/uvcvideo.h b/include/uapi/linux/uvcvideo.h index f80f05b3c423f3b2a5b0372ab03ba41f3e173348..2140923661934d4ef7ffffd25a15eae92d1aca37 100644 --- a/include/uapi/linux/uvcvideo.h +++ b/include/uapi/linux/uvcvideo.h @@ -86,7 +86,7 @@ struct uvc_xu_control_query { * struct. The first two fields are added by the driver, they can be used for * clock synchronisation. The rest is an exact copy of a UVC payload header. * Only complete objects with complete buffers are included. Therefore it's - * always sizeof(meta->ts) + sizeof(meta->sof) + meta->length bytes large. + * always sizeof(meta->ns) + sizeof(meta->sof) + meta->length bytes large. */ struct uvc_meta_buf { __u64 ns; diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 835ea8fce3f95e5cc6880d1ff569fafed78aa8c1..115ea202b1ab844bb91e6582d9123a9f52c3a834 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -1635,7 +1635,7 @@ struct v4l2_input { __u8 name[32]; /* Label */ __u32 type; /* Type of input */ __u32 audioset; /* Associated audios (bitfield) */ - __u32 tuner; /* enum v4l2_tuner_type */ + __u32 tuner; /* Tuner index */ v4l2_std_id std; __u32 status; __u32 capabilities; diff --git a/include/uapi/sound/skl-tplg-interface.h b/include/uapi/sound/skl-tplg-interface.h index f39352cef38223e4b1b5ab70693ca3deb5eee451..2783253ba4731af931b93c769ab205fe39e8451a 100644 --- a/include/uapi/sound/skl-tplg-interface.h +++ b/include/uapi/sound/skl-tplg-interface.h @@ -64,7 +64,8 @@ enum skl_ch_cfg { SKL_CH_CFG_DUAL_MONO = 9, SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10, SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11, - SKL_CH_CFG_4_CHANNEL = 12, + SKL_CH_CFG_7_1 = 12, + SKL_CH_CFG_4_CHANNEL = SKL_CH_CFG_7_1, SKL_CH_CFG_INVALID }; diff --git a/init/main.c b/init/main.c index 8a6ffd0188ba2dee2d2c8bf89ac855752560f947..ed1555546cec7bd4ca4876b71c36c5fca18ccc6e 100644 --- a/init/main.c +++ b/init/main.c @@ -91,10 +91,8 @@ #include #include #include -#include #include -#include #include #include #include @@ -498,8 +496,6 @@ void __init __weak thread_stack_cache_init(void) } #endif -void __init __weak mem_encrypt_init(void) { } - bool initcall_debug; core_param(initcall_debug, initcall_debug, bool, 0644); @@ -716,14 +712,6 @@ asmlinkage __visible void __init start_kernel(void) */ locking_selftest(); - /* - * This needs to be called before any devices perform DMA - * operations that might use the SWIOTLB bounce buffers. It will - * mark the bounce buffers as decrypted so that their usage will - * not cause "plain-text" data to be decrypted when accessed. - */ - mem_encrypt_init(); - #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start && !initrd_below_start_ok && page_to_pfn(virt_to_page((void *)initrd_start)) < min_low_pfn) { @@ -742,6 +730,9 @@ asmlinkage __visible void __init start_kernel(void) late_time_init(); sched_clock_init(); calibrate_delay(); + + arch_cpu_finalize_init(); + pid_idr_init(); anon_vma_init(); #ifdef CONFIG_X86 @@ -772,7 +763,6 @@ asmlinkage __visible void __init start_kernel(void) if(phx_set_boot_stage) phx_set_boot_stage(KERNEL_DELAYACCT_INIT_DONE); #endif //OPLUS_FEATURE_PHOENIX - check_bugs(); acpi_subsystem_init(); arch_post_acpi_subsys_init(); diff --git a/kernel/async.c b/kernel/async.c index 4bf1b00a28d864628a9e284b3cb5f46aa85b4e4e..e59bd2240cb865c63b0e831448f5289f1c1fd6cb 100644 --- a/kernel/async.c +++ b/kernel/async.c @@ -115,7 +115,7 @@ static void async_run_entry_fn(struct work_struct *work) struct async_entry *entry = container_of(work, struct async_entry, work); unsigned long flags; - ktime_t uninitialized_var(calltime), delta, rettime; + ktime_t calltime, delta, rettime; /* 1) run (and print duration) */ if (initcall_debug && system_state < SYSTEM_RUNNING) { @@ -283,7 +283,7 @@ EXPORT_SYMBOL_GPL(async_synchronize_full_domain); */ void async_synchronize_cookie_domain(async_cookie_t cookie, struct async_domain *domain) { - ktime_t uninitialized_var(starttime), delta, endtime; + ktime_t starttime, delta, endtime; if (initcall_debug && system_state < SYSTEM_RUNNING) { pr_debug("async_waiting @ %i\n", task_pid_nr(current)); diff --git a/kernel/audit.c b/kernel/audit.c index 7dc14a4d9e3cf4b32de6e7b02352fdf0520af3c9..471d3ad910aa5a03d1479f429ece431a2b2d7ee4 100644 --- a/kernel/audit.c +++ b/kernel/audit.c @@ -1796,7 +1796,7 @@ struct audit_buffer *audit_log_start(struct audit_context *ctx, gfp_t gfp_mask, { struct audit_buffer *ab; struct timespec64 t; - unsigned int uninitialized_var(serial); + unsigned int serial; if (audit_initialized != AUDIT_INITIALIZED) return NULL; diff --git a/kernel/audit_watch.c b/kernel/audit_watch.c index 50952d6d81209f31ebd0be66bd0eb92c9a28d45f..ff33536ae1ad87f4e495bba2208e770494df2628 100644 --- a/kernel/audit_watch.c +++ b/kernel/audit_watch.c @@ -557,11 +557,18 @@ int audit_exe_compare(struct task_struct *tsk, struct audit_fsnotify_mark *mark) unsigned long ino; dev_t dev; - exe_file = get_task_exe_file(tsk); + /* only do exe filtering if we are recording @current events/records */ + if (tsk != current) + return 0; + + if (!current->mm) + return 0; + exe_file = get_mm_exe_file(current->mm); if (!exe_file) return 0; ino = file_inode(exe_file)->i_ino; dev = file_inode(exe_file)->i_sb->s_dev; fput(exe_file); + return audit_mark_compare(mark, ino, dev); } diff --git a/kernel/auditsc.c b/kernel/auditsc.c index 1513873e23bd12d956c4fbcaf05c979f14cd1303..e4de5b9d5d3f1b8f1969235ccc4276d894ee8804 100644 --- a/kernel/auditsc.c +++ b/kernel/auditsc.c @@ -1923,6 +1923,8 @@ void __audit_inode_child(struct inode *parent, } } + cond_resched(); + /* is there a matching child entry? */ list_for_each_entry(n, &context->names_list, list) { /* can only match entries that have a name */ diff --git a/kernel/bpf/bpf_lru_list.c b/kernel/bpf/bpf_lru_list.c index 9b5eeff72fd378167c38a038c763ad59ea82a304..39a0e768adc39c82f81a5cc4910655cb3389d068 100644 --- a/kernel/bpf/bpf_lru_list.c +++ b/kernel/bpf/bpf_lru_list.c @@ -44,7 +44,12 @@ static struct list_head *local_pending_list(struct bpf_lru_locallist *loc_l) /* bpf_lru_node helpers */ static bool bpf_lru_node_is_ref(const struct bpf_lru_node *node) { - return node->ref; + return READ_ONCE(node->ref); +} + +static void bpf_lru_node_clear_ref(struct bpf_lru_node *node) +{ + WRITE_ONCE(node->ref, 0); } static void bpf_lru_list_count_inc(struct bpf_lru_list *l, @@ -92,7 +97,7 @@ static void __bpf_lru_node_move_in(struct bpf_lru_list *l, bpf_lru_list_count_inc(l, tgt_type); node->type = tgt_type; - node->ref = 0; + bpf_lru_node_clear_ref(node); list_move(&node->list, &l->lists[tgt_type]); } @@ -113,7 +118,7 @@ static void __bpf_lru_node_move(struct bpf_lru_list *l, bpf_lru_list_count_inc(l, tgt_type); node->type = tgt_type; } - node->ref = 0; + bpf_lru_node_clear_ref(node); /* If the moving node is the next_inactive_rotation candidate, * move the next_inactive_rotation pointer also. @@ -356,7 +361,7 @@ static void __local_list_add_pending(struct bpf_lru *lru, *(u32 *)((void *)node + lru->hash_offset) = hash; node->cpu = cpu; node->type = BPF_LRU_LOCAL_LIST_T_PENDING; - node->ref = 0; + bpf_lru_node_clear_ref(node); list_add(&node->list, local_pending_list(loc_l)); } @@ -422,7 +427,7 @@ static struct bpf_lru_node *bpf_percpu_lru_pop_free(struct bpf_lru *lru, if (!list_empty(free_list)) { node = list_first_entry(free_list, struct bpf_lru_node, list); *(u32 *)((void *)node + lru->hash_offset) = hash; - node->ref = 0; + bpf_lru_node_clear_ref(node); __bpf_lru_node_move(l, node, BPF_LRU_LIST_T_INACTIVE); } @@ -525,7 +530,7 @@ static void bpf_common_lru_push_free(struct bpf_lru *lru, } node->type = BPF_LRU_LOCAL_LIST_T_FREE; - node->ref = 0; + bpf_lru_node_clear_ref(node); list_move(&node->list, local_free_list(loc_l)); raw_spin_unlock_irqrestore(&loc_l->lock, flags); @@ -571,7 +576,7 @@ static void bpf_common_lru_populate(struct bpf_lru *lru, void *buf, node = (struct bpf_lru_node *)(buf + node_offset); node->type = BPF_LRU_LIST_T_FREE; - node->ref = 0; + bpf_lru_node_clear_ref(node); list_add(&node->list, &l->lists[BPF_LRU_LIST_T_FREE]); buf += elem_size; } @@ -597,7 +602,7 @@ static void bpf_percpu_lru_populate(struct bpf_lru *lru, void *buf, node = (struct bpf_lru_node *)(buf + node_offset); node->cpu = cpu; node->type = BPF_LRU_LIST_T_FREE; - node->ref = 0; + bpf_lru_node_clear_ref(node); list_add(&node->list, &l->lists[BPF_LRU_LIST_T_FREE]); i++; buf += elem_size; diff --git a/kernel/bpf/bpf_lru_list.h b/kernel/bpf/bpf_lru_list.h index 7d4f89b7cb84167f9ca94b154ae32b3df77cf9f4..08da78b59f0b9d4976421b8a17e4cece051ceef0 100644 --- a/kernel/bpf/bpf_lru_list.h +++ b/kernel/bpf/bpf_lru_list.h @@ -66,11 +66,8 @@ struct bpf_lru { static inline void bpf_lru_node_set_ref(struct bpf_lru_node *node) { - /* ref is an approximation on access frequency. It does not - * have to be very accurate. Hence, no protection is used. - */ - if (!node->ref) - node->ref = 1; + if (!READ_ONCE(node->ref)) + WRITE_ONCE(node->ref, 1); } int bpf_lru_init(struct bpf_lru *lru, bool percpu, u32 hash_offset, diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c index 351bc1f884736483fc33cf758420681ec26c8845..14f453a768e63ef8ca6ecc20f63d577104137faf 100644 --- a/kernel/bpf/core.c +++ b/kernel/bpf/core.c @@ -603,7 +603,7 @@ static int __init bpf_jit_charge_init(void) { /* Only used as heuristic here to derive limit. */ bpf_jit_limit_max = bpf_jit_alloc_exec_limit(); - bpf_jit_limit = min_t(u64, round_up(bpf_jit_limit_max >> 2, + bpf_jit_limit = min_t(u64, round_up(bpf_jit_limit_max >> 1, PAGE_SIZE), LONG_MAX); return 0; } diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c index 61f3a31abc1ad90b0bbe31b433b5a8e1e8b1a90e..a48de55f5630e79e186d64637eb3e42717233eb1 100644 --- a/kernel/bpf/verifier.c +++ b/kernel/bpf/verifier.c @@ -5936,7 +5936,7 @@ static int convert_ctx_accesses(struct bpf_verifier_env *env) insn_buf[cnt++] = BPF_ALU64_IMM(BPF_RSH, insn->dst_reg, shift); - insn_buf[cnt++] = BPF_ALU64_IMM(BPF_AND, insn->dst_reg, + insn_buf[cnt++] = BPF_ALU32_IMM(BPF_AND, insn->dst_reg, (1ULL << size * 8) - 1); } } diff --git a/kernel/cgroup/cgroup-v1.c b/kernel/cgroup/cgroup-v1.c index d1eea9fecb0399d377d195e24f9fe5cce099790d..26fd0118a5ba906a3996bf0dfb129cddd7ab3547 100644 --- a/kernel/cgroup/cgroup-v1.c +++ b/kernel/cgroup/cgroup-v1.c @@ -13,6 +13,7 @@ #include #include #include +#include #include @@ -58,6 +59,7 @@ int cgroup_attach_task_all(struct task_struct *from, struct task_struct *tsk) int retval = 0; mutex_lock(&cgroup_mutex); + get_online_cpus(); percpu_down_write(&cgroup_threadgroup_rwsem); for_each_root(root) { struct cgroup *from_cgrp; @@ -74,6 +76,7 @@ int cgroup_attach_task_all(struct task_struct *from, struct task_struct *tsk) break; } percpu_up_write(&cgroup_threadgroup_rwsem); + put_online_cpus(); mutex_unlock(&cgroup_mutex); return retval; @@ -379,10 +382,9 @@ static int pidlist_array_load(struct cgroup *cgrp, enum cgroup_filetype type, } css_task_iter_end(&it); length = n; - /* now sort & (if procs) strip out duplicates */ + /* now sort & strip out duplicates (tgids or recycled thread PIDs) */ sort(array, length, sizeof(pid_t), cmppid, NULL); - if (type == CGROUP_FILE_PROCS) - length = pidlist_uniq(array, length); + length = pidlist_uniq(array, length); l = cgroup_pidlist_find_create(cgrp, type); if (!l) { diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c index 76fd282ab60af056dcac495ce03e8545caa69423..8540fcb4ac502778b757b0edac23bc1bff5f9213 100644 --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #define CREATE_TRACE_POINTS @@ -1701,7 +1702,7 @@ int rebind_subsystems(struct cgroup_root *dst_root, u16 ss_mask) { struct cgroup *dcgrp = &dst_root->cgrp; struct cgroup_subsys *ss; - int ssid, i, ret; + int ssid, ret; u16 dfl_disable_ss_mask = 0; lockdep_assert_held(&cgroup_mutex); @@ -1745,7 +1746,8 @@ int rebind_subsystems(struct cgroup_root *dst_root, u16 ss_mask) struct cgroup_root *src_root = ss->root; struct cgroup *scgrp = &src_root->cgrp; struct cgroup_subsys_state *css = cgroup_css(scgrp, ss); - struct css_set *cset; + struct css_set *cset, *cset_pos; + struct css_task_iter *it; WARN_ON(!css || cgroup_css(dcgrp, ss)); @@ -1763,9 +1765,22 @@ int rebind_subsystems(struct cgroup_root *dst_root, u16 ss_mask) css->cgroup = dcgrp; spin_lock_irq(&css_set_lock); - hash_for_each(css_set_table, i, cset, hlist) + WARN_ON(!list_empty(&dcgrp->e_csets[ss->id])); + list_for_each_entry_safe(cset, cset_pos, &scgrp->e_csets[ss->id], + e_cset_node[ss->id]) { list_move_tail(&cset->e_cset_node[ss->id], &dcgrp->e_csets[ss->id]); + /* + * all css_sets of scgrp together in same order to dcgrp, + * patch in-flight iterators to preserve correct iteration. + * since the iterator is always advanced right away and + * finished when it->cset_pos meets it->cset_head, so only + * update it->cset_head is enough here. + */ + list_for_each_entry(it, &cset->task_iters, iters_node) + if (it->cset_head == &scgrp->e_csets[ss->id]) + it->cset_head = &dcgrp->e_csets[ss->id]; + } spin_unlock_irq(&css_set_lock); /* default hierarchy doesn't enable controllers by default */ @@ -2257,6 +2272,45 @@ int task_cgroup_path(struct task_struct *task, char *buf, size_t buflen) } EXPORT_SYMBOL_GPL(task_cgroup_path); +/** + * cgroup_attach_lock - Lock for ->attach() + * @lock_threadgroup: whether to down_write cgroup_threadgroup_rwsem + * + * cgroup migration sometimes needs to stabilize threadgroups against forks and + * exits by write-locking cgroup_threadgroup_rwsem. However, some ->attach() + * implementations (e.g. cpuset), also need to disable CPU hotplug. + * Unfortunately, letting ->attach() operations acquire cpus_read_lock() can + * lead to deadlocks. + * + * Bringing up a CPU may involve creating and destroying tasks which requires + * read-locking threadgroup_rwsem, so threadgroup_rwsem nests inside + * cpus_read_lock(). If we call an ->attach() which acquires the cpus lock while + * write-locking threadgroup_rwsem, the locking order is reversed and we end up + * waiting for an on-going CPU hotplug operation which in turn is waiting for + * the threadgroup_rwsem to be released to create new tasks. For more details: + * + * http://lkml.kernel.org/r/20220711174629.uehfmqegcwn2lqzu@wubuntu + * + * Resolve the situation by always acquiring cpus_read_lock() before optionally + * write-locking cgroup_threadgroup_rwsem. This allows ->attach() to assume that + * CPU hotplug is disabled on entry. + */ +static void cgroup_attach_lock(void) +{ + get_online_cpus(); + percpu_down_write(&cgroup_threadgroup_rwsem); +} + +/** + * cgroup_attach_unlock - Undo cgroup_attach_lock() + * @lock_threadgroup: whether to up_write cgroup_threadgroup_rwsem + */ +static void cgroup_attach_unlock(void) +{ + percpu_up_write(&cgroup_threadgroup_rwsem); + put_online_cpus(); +} + /** * cgroup_migrate_add_task - add a migration target task to a migration context * @task: target task @@ -2746,7 +2800,7 @@ struct task_struct *cgroup_procs_write_start(char *buf, bool threadgroup) if (kstrtoint(strstrip(buf), 0, &pid) || pid < 0) return ERR_PTR(-EINVAL); - percpu_down_write(&cgroup_threadgroup_rwsem); + cgroup_attach_lock(); rcu_read_lock(); if (pid) { @@ -2777,7 +2831,7 @@ struct task_struct *cgroup_procs_write_start(char *buf, bool threadgroup) goto out_unlock_rcu; out_unlock_threadgroup: - percpu_up_write(&cgroup_threadgroup_rwsem); + cgroup_attach_unlock(); out_unlock_rcu: rcu_read_unlock(); return tsk; @@ -2792,7 +2846,7 @@ void cgroup_procs_write_finish(struct task_struct *task) /* release reference from cgroup_procs_write_start() */ put_task_struct(task); - percpu_up_write(&cgroup_threadgroup_rwsem); + cgroup_attach_unlock(); for_each_subsys(ss, ssid) if (ss->post_attach) ss->post_attach(); @@ -2851,7 +2905,7 @@ static int cgroup_update_dfl_csses(struct cgroup *cgrp) lockdep_assert_held(&cgroup_mutex); - percpu_down_write(&cgroup_threadgroup_rwsem); + cgroup_attach_lock(); /* look up all csses currently attached to @cgrp's subtree */ spin_lock_irq(&css_set_lock); @@ -2882,7 +2936,7 @@ static int cgroup_update_dfl_csses(struct cgroup *cgrp) ret = cgroup_migrate_execute(&mgctx); out_finish: cgroup_migrate_finish(&mgctx); - percpu_up_write(&cgroup_threadgroup_rwsem); + cgroup_attach_unlock(); return ret; } diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c index 908efe2094aa511663e71eca583a9089255247ee..f1dd4dd908c3b9774cb71368bad772136632451e 100644 --- a/kernel/cgroup/cpuset.c +++ b/kernel/cgroup/cpuset.c @@ -1837,7 +1837,9 @@ static void cpuset_cancel_attach(struct cgroup_taskset *tset) cs = css_cs(css); mutex_lock(&cpuset_mutex); - css_cs(css)->attach_in_progress--; + cs->attach_in_progress--; + if (!cs->attach_in_progress) + wake_up(&cpuset_attach_wq); mutex_unlock(&cpuset_mutex); } @@ -1861,13 +1863,9 @@ static void cpuset_attach(struct cgroup_taskset *tset) cgroup_taskset_first(tset, &css); cs = css_cs(css); + lockdep_assert_cpus_held(); /* see cgroup_attach_lock() */ mutex_lock(&cpuset_mutex); - /* - * It should hold cpus lock because a cpu offline event can - * cause set_cpus_allowed_ptr() failed. - */ - get_online_cpus(); /* prepare for attach */ if (cs == &top_cpuset) cpumask_copy(cpus_attach, cpu_possible_mask); @@ -1886,7 +1884,6 @@ static void cpuset_attach(struct cgroup_taskset *tset) cpuset_change_task_nodemask(task, &cpuset_attach_nodemask_to); cpuset_update_task_spread_flag(cs, task); } - put_online_cpus(); /* * Change mm for all threadgroup leaders. This is expensive and may diff --git a/kernel/cgroup/namespace.c b/kernel/cgroup/namespace.c index b05f1dd58a6220c5c4231465bee3f461078f171e..313e66b8c6622d47808b4906aa959cd20be32875 100644 --- a/kernel/cgroup/namespace.c +++ b/kernel/cgroup/namespace.c @@ -148,9 +148,3 @@ const struct proc_ns_operations cgroupns_operations = { .install = cgroupns_install, .owner = cgroupns_owner, }; - -static __init int cgroup_namespaces_init(void) -{ - return 0; -} -subsys_initcall(cgroup_namespaces_init); diff --git a/kernel/compat.c b/kernel/compat.c index e4548a9e9c52c9a126a297907904b05200ce7859..5f320b0db8d09f8fde0055800d8bb97ea6d1c07c 100644 --- a/kernel/compat.c +++ b/kernel/compat.c @@ -307,7 +307,7 @@ COMPAT_SYSCALL_DEFINE3(sched_getaffinity, compat_pid_t, pid, unsigned int, len, if (len & (sizeof(compat_ulong_t)-1)) return -EINVAL; - if (!alloc_cpumask_var(&mask, GFP_KERNEL)) + if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) return -ENOMEM; ret = sched_getaffinity(pid, mask); diff --git a/kernel/dma/debug.c b/kernel/dma/debug.c index 7c6cd00d0fca960de3cc424bb701030f1720380e..c345a6e2f7b7e551144951a6df4262febf26249a 100644 --- a/kernel/dma/debug.c +++ b/kernel/dma/debug.c @@ -963,7 +963,7 @@ static int device_dma_allocations(struct device *dev, struct dma_debug_entry **o static int dma_debug_device_change(struct notifier_block *nb, unsigned long action, void *data) { struct device *dev = data; - struct dma_debug_entry *uninitialized_var(entry); + struct dma_debug_entry *entry; int count; if (dma_debug_disabled()) diff --git a/kernel/events/core.c b/kernel/events/core.c index 3d035c7a717676de4fc8b0387041190576e25103..a21bf2d3cecd21d34914c32ba40bf6ca7a6c9359 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -1161,6 +1161,11 @@ static int perf_mux_hrtimer_restart(struct perf_cpu_context *cpuctx) return 0; } +static int perf_mux_hrtimer_restart_ipi(void *arg) +{ + return perf_mux_hrtimer_restart(arg); +} + void perf_pmu_disable(struct pmu *pmu) { int *count = this_cpu_ptr(pmu->pmu_disable_count); @@ -1871,6 +1876,7 @@ static void perf_group_attach(struct perf_event *event) list_add_tail(&event->sibling_list, &group_leader->sibling_list); group_leader->nr_siblings++; + group_leader->group_generation++; perf_event__header_size(group_leader); @@ -1941,6 +1947,7 @@ static void perf_group_detach(struct perf_event *event) if (event->group_leader != event) { list_del_init(&event->sibling_list); event->group_leader->nr_siblings--; + event->group_leader->group_generation++; if (event->shared) event->group_leader = event; @@ -4889,7 +4896,7 @@ static int __perf_read_group_add(struct perf_event *leader, u64 read_format, u64 *values) { struct perf_event_context *ctx = leader->ctx; - struct perf_event *sub; + struct perf_event *sub, *parent; unsigned long flags; int n = 1; /* skip @nr */ int ret; @@ -4899,6 +4906,33 @@ static int __perf_read_group_add(struct perf_event *leader, return ret; raw_spin_lock_irqsave(&ctx->lock, flags); + /* + * Verify the grouping between the parent and child (inherited) + * events is still in tact. + * + * Specifically: + * - leader->ctx->lock pins leader->sibling_list + * - parent->child_mutex pins parent->child_list + * - parent->ctx->mutex pins parent->sibling_list + * + * Because parent->ctx != leader->ctx (and child_list nests inside + * ctx->mutex), group destruction is not atomic between children, also + * see perf_event_release_kernel(). Additionally, parent can grow the + * group. + * + * Therefore it is possible to have parent and child groups in a + * different configuration and summing over such a beast makes no sense + * what so ever. + * + * Reject this. + */ + parent = leader->parent; + if (parent && + (parent->group_generation != leader->group_generation || + parent->nr_siblings != leader->nr_siblings)) { + ret = -ECHILD; + goto unlock; + } /* * Since we co-schedule groups, {enabled,running} times of siblings @@ -4928,8 +4962,9 @@ static int __perf_read_group_add(struct perf_event *leader, values[n++] = primary_event_id(sub); } +unlock: raw_spin_unlock_irqrestore(&ctx->lock, flags); - return 0; + return ret; } static int perf_read_group(struct perf_event *event, @@ -4948,10 +4983,6 @@ static int perf_read_group(struct perf_event *event, values[0] = 1 + leader->nr_siblings; - /* - * By locking the child_mutex of the leader we effectively - * lock the child list of all siblings.. XXX explain how. - */ mutex_lock(&leader->child_mutex); ret = __perf_read_group_add(leader, read_format, values); @@ -8004,8 +8035,8 @@ __perf_event_account_interrupt(struct perf_event *event, int throttle) hwc->interrupts = 1; } else { hwc->interrupts++; - if (unlikely(throttle - && hwc->interrupts >= max_samples_per_tick)) { + if (unlikely(throttle && + hwc->interrupts > max_samples_per_tick)) { __this_cpu_inc(perf_throttled_count); tick_dep_set_cpu(smp_processor_id(), TICK_DEP_BIT_PERF_EVENTS); hwc->interrupts = MAX_INTERRUPTS; @@ -9810,8 +9841,7 @@ perf_event_mux_interval_ms_store(struct device *dev, cpuctx = per_cpu_ptr(pmu->pmu_cpu_context, cpu); cpuctx->hrtimer_interval = ns_to_ktime(NSEC_PER_MSEC * timer); - cpu_function_call(cpu, - (remote_function_f)perf_mux_hrtimer_restart, cpuctx); + cpu_function_call(cpu, perf_mux_hrtimer_restart_ipi, cpuctx); } cpus_read_unlock(); mutex_unlock(&mux_interval_mutex); @@ -10367,7 +10397,6 @@ perf_event_alloc(struct perf_event_attr *attr, int cpu, if (!group_leader) group_leader = event; - mutex_init(&event->group_leader_mutex); mutex_init(&event->child_mutex); INIT_LIST_HEAD(&event->child_list); @@ -10697,7 +10726,7 @@ perf_event_set_output(struct perf_event *event, struct perf_event *output_event) /* * If its not a per-cpu rb, it must be the same task. */ - if (output_event->cpu == -1 && output_event->ctx != event->ctx) + if (output_event->cpu == -1 && output_event->hw.target != event->hw.target) goto out; /* @@ -10866,7 +10895,7 @@ SYSCALL_DEFINE5(perf_event_open, struct perf_event *group_leader = NULL, *output_event = NULL; struct perf_event *event = NULL, *sibling; struct perf_event_attr attr; - struct perf_event_context *ctx, *uninitialized_var(gctx); + struct perf_event_context *ctx, *gctx; struct file *event_file = NULL; struct fd group = {NULL, 0}; struct task_struct *task = NULL; @@ -10943,16 +10972,6 @@ SYSCALL_DEFINE5(perf_event_open, group_leader = NULL; } - /* - * Take the group_leader's group_leader_mutex before observing - * anything in the group leader that leads to changes in ctx, - * many of which may be changing on another thread. - * In particular, we want to take this lock before deciding - * whether we need to move_group. - */ - if (group_leader) - mutex_lock(&group_leader->group_leader_mutex); - if (pid != -1 && !(flags & PERF_FLAG_PID_CGROUP)) { task = find_lively_task_by_vpid(pid); if (IS_ERR(task)) { @@ -11268,8 +11287,6 @@ SYSCALL_DEFINE5(perf_event_open, if (move_group) perf_event_ctx_unlock(group_leader, gctx); mutex_unlock(&ctx->mutex); - if (group_leader) - mutex_unlock(&group_leader->group_leader_mutex); if (task) { mutex_unlock(&task->signal->cred_guard_mutex); @@ -11323,8 +11340,6 @@ SYSCALL_DEFINE5(perf_event_open, if (task) put_task_struct(task); err_group_fd: - if (group_leader) - mutex_unlock(&group_leader->group_leader_mutex); fdput(group); err_fd: put_unused_fd(event_fd); @@ -11915,6 +11930,8 @@ static int inherit_group(struct perf_event *parent_event, if (IS_ERR(child_ctr)) return PTR_ERR(child_ctr); } + if (leader) + leader->group_generation = parent_event->group_generation; return 0; } diff --git a/kernel/events/ring_buffer.c b/kernel/events/ring_buffer.c index 12f351b253bbb4b567dd7529d7d0f7db5b972d7c..2f6f77658eba22f9b786c5f4b9f4829e4641eaa7 100644 --- a/kernel/events/ring_buffer.c +++ b/kernel/events/ring_buffer.c @@ -639,6 +639,12 @@ int rb_alloc_aux(struct ring_buffer *rb, struct perf_event *event, } } + /* + * kcalloc_node() is unable to allocate buffer if the size is larger + * than: PAGE_SIZE << MAX_ORDER; directly bail out in this case. + */ + if (get_order((unsigned long)nr_pages * sizeof(void *)) > MAX_ORDER) + return -ENOMEM; rb->aux_pages = kcalloc_node(nr_pages, sizeof(void *), GFP_KERNEL, node); if (!rb->aux_pages) diff --git a/kernel/events/uprobes.c b/kernel/events/uprobes.c index 24342bca11f2f21cc5ac34a65e374966cb84e7a3..72ae05d650661ea1f6073122d16e45556d7eb4de 100644 --- a/kernel/events/uprobes.c +++ b/kernel/events/uprobes.c @@ -1887,7 +1887,7 @@ static void handle_swbp(struct pt_regs *regs) { struct uprobe *uprobe; unsigned long bp_vaddr; - int uninitialized_var(is_swbp); + int is_swbp; bp_vaddr = uprobe_get_swbp_addr(regs); if (bp_vaddr == get_trampoline_vaddr()) diff --git a/kernel/exit.c b/kernel/exit.c index 19a0e34ec33ec3220e427274e0927d986df84c4c..c04e172b25e9f49dbeb07f628ec489849c155374 100644 --- a/kernel/exit.c +++ b/kernel/exit.c @@ -159,7 +159,7 @@ static void __exit_signal(struct task_struct *tsk) struct signal_struct *sig = tsk->signal; bool group_dead = thread_group_leader(tsk); struct sighand_struct *sighand; - struct tty_struct *uninitialized_var(tty); + struct tty_struct *tty; u64 utime, stime; sighand = rcu_dereference_check(tsk->sighand, diff --git a/kernel/extable.c b/kernel/extable.c index 6a5b61ebc66c956e6eeee6537786f4161d98f2ef..b3ca75d6bf928534d488866e6f259bf10c554cc7 100644 --- a/kernel/extable.c +++ b/kernel/extable.c @@ -46,7 +46,8 @@ u32 __initdata __visible main_extable_sort_needed = 1; /* Sort the kernel's built-in exception table */ void __init sort_main_extable(void) { - if (main_extable_sort_needed && __stop___ex_table > __start___ex_table) { + if (main_extable_sort_needed && + &__stop___ex_table > &__start___ex_table) { pr_notice("Sorting __ex_table...\n"); sort_extable(__start___ex_table, __stop___ex_table); } diff --git a/kernel/futex.c b/kernel/futex.c index 5ec194dc34b4c314b203d4426fd45bd008906f02..9c5f82537476515f03006197179c3071d1009c32 100644 --- a/kernel/futex.c +++ b/kernel/futex.c @@ -1398,7 +1398,7 @@ static int lookup_pi_state(u32 __user *uaddr, u32 uval, static int lock_pi_update_atomic(u32 __user *uaddr, u32 uval, u32 newval) { int err; - u32 uninitialized_var(curval); + u32 curval; if (unlikely(should_fail_futex(true))) return -EFAULT; @@ -1569,7 +1569,7 @@ static void mark_wake_futex(struct wake_q_head *wake_q, struct futex_q *q) */ static int wake_futex_pi(u32 __user *uaddr, u32 uval, struct futex_pi_state *pi_state) { - u32 uninitialized_var(curval), newval; + u32 curval, newval; struct task_struct *new_owner; bool postunlock = false; DEFINE_WAKE_Q(wake_q); @@ -3095,7 +3095,7 @@ static int futex_lock_pi(u32 __user *uaddr, unsigned int flags, */ static int futex_unlock_pi(u32 __user *uaddr, unsigned int flags) { - u32 uninitialized_var(curval), uval, vpid = task_pid_vnr(current); + u32 curval, uval, vpid = task_pid_vnr(current); union futex_key key = FUTEX_KEY_INIT; struct futex_hash_bucket *hb; struct futex_q *top_waiter; @@ -3570,7 +3570,7 @@ SYSCALL_DEFINE3(get_robust_list, int, pid, static int handle_futex_death(u32 __user *uaddr, struct task_struct *curr, bool pi, bool pending_op) { - u32 uval, uninitialized_var(nval), mval; + u32 uval, nval, mval; int err; /* Futex address must be 32bit aligned */ @@ -3700,7 +3700,7 @@ static void exit_robust_list(struct task_struct *curr) struct robust_list_head __user *head = curr->robust_list; struct robust_list __user *entry, *next_entry, *pending; unsigned int limit = ROBUST_LIST_LIMIT, pi, pip; - unsigned int uninitialized_var(next_pi); + unsigned int next_pi; unsigned long futex_offset; int rc; @@ -3999,7 +3999,7 @@ static void compat_exit_robust_list(struct task_struct *curr) struct compat_robust_list_head __user *head = curr->compat_robust_list; struct robust_list __user *entry, *next_entry, *pending; unsigned int limit = ROBUST_LIST_LIMIT, pi, pip; - unsigned int uninitialized_var(next_pi); + unsigned int next_pi; compat_uptr_t uentry, next_uentry, upending; compat_long_t futex_offset; int rc; diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index e2999a070a99a2b9495d1406e7727b91f980a7ee..4195e7ad1ff2ffdf7de29e5522516842e278edec 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -537,21 +537,34 @@ EXPORT_SYMBOL_GPL(irq_setup_alt_chip); void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, unsigned int clr, unsigned int set) { - unsigned int i = gc->irq_base; + unsigned int i, virq; raw_spin_lock(&gc_lock); list_del(&gc->list); raw_spin_unlock(&gc_lock); - for (; msk; msk >>= 1, i++) { + for (i = 0; msk; msk >>= 1, i++) { if (!(msk & 0x01)) continue; + /* + * Interrupt domain based chips store the base hardware + * interrupt number in gc::irq_base. Otherwise gc::irq_base + * contains the base Linux interrupt number. + */ + if (gc->domain) { + virq = irq_find_mapping(gc->domain, gc->irq_base + i); + if (!virq) + continue; + } else { + virq = gc->irq_base + i; + } + /* Remove handler first. That will mask the irq line */ - irq_set_handler(i, NULL); - irq_set_chip(i, &no_irq_chip); - irq_set_chip_data(i, NULL); - irq_modify_status(i, clr, set); + irq_set_handler(virq, NULL); + irq_set_chip(virq, &no_irq_chip); + irq_set_chip_data(virq, NULL); + irq_modify_status(virq, clr, set); } } EXPORT_SYMBOL_GPL(irq_remove_generic_chip); diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index e3ac5a5a488729e35102841c9d28723cdf39e4bf..359f5f3d7b7e7da2566031900498b6373982331b 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -495,6 +495,9 @@ void irq_domain_disassociate(struct irq_domain *domain, unsigned int irq) return; hwirq = irq_data->hwirq; + + mutex_lock(&irq_domain_mutex); + irq_set_status_flags(irq, IRQ_NOREQUEST); /* remove chip and handler */ @@ -514,10 +517,12 @@ void irq_domain_disassociate(struct irq_domain *domain, unsigned int irq) /* Clear reverse map for this hwirq */ irq_domain_clear_mapping(domain, hwirq); + + mutex_unlock(&irq_domain_mutex); } -int irq_domain_associate(struct irq_domain *domain, unsigned int virq, - irq_hw_number_t hwirq) +static int irq_domain_associate_locked(struct irq_domain *domain, unsigned int virq, + irq_hw_number_t hwirq) { struct irq_data *irq_data = irq_get_irq_data(virq); int ret; @@ -530,7 +535,6 @@ int irq_domain_associate(struct irq_domain *domain, unsigned int virq, if (WARN(irq_data->domain, "error: virq%i is already associated", virq)) return -EINVAL; - mutex_lock(&irq_domain_mutex); irq_data->hwirq = hwirq; irq_data->domain = domain; if (domain->ops->map) { @@ -547,7 +551,6 @@ int irq_domain_associate(struct irq_domain *domain, unsigned int virq, } irq_data->domain = NULL; irq_data->hwirq = 0; - mutex_unlock(&irq_domain_mutex); return ret; } @@ -558,12 +561,23 @@ int irq_domain_associate(struct irq_domain *domain, unsigned int virq, domain->mapcount++; irq_domain_set_mapping(domain, hwirq, irq_data); - mutex_unlock(&irq_domain_mutex); irq_clear_status_flags(virq, IRQ_NOREQUEST); return 0; } + +int irq_domain_associate(struct irq_domain *domain, unsigned int virq, + irq_hw_number_t hwirq) +{ + int ret; + + mutex_lock(&irq_domain_mutex); + ret = irq_domain_associate_locked(domain, virq, hwirq); + mutex_unlock(&irq_domain_mutex); + + return ret; +} EXPORT_SYMBOL_GPL(irq_domain_associate); void irq_domain_associate_many(struct irq_domain *domain, unsigned int irq_base, @@ -819,13 +833,8 @@ unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec) } irq_data = irq_get_irq_data(virq); - if (!irq_data) { - if (irq_domain_is_hierarchy(domain)) - irq_domain_free_irqs(virq, 1); - else - irq_dispose_mapping(virq); + if (WARN_ON(!irq_data)) return 0; - } /* Store trigger type */ irqd_set_trigger_type(irq_data, type); diff --git a/kernel/irq/matrix.c b/kernel/irq/matrix.c index 8e586858bcf41f41d05b38ec1b08ea74a351d638..d25edbb87119fe8fbfec784eb0209410ce7a0b65 100644 --- a/kernel/irq/matrix.c +++ b/kernel/irq/matrix.c @@ -466,16 +466,16 @@ unsigned int irq_matrix_reserved(struct irq_matrix *m) } /** - * irq_matrix_allocated - Get the number of allocated irqs on the local cpu + * irq_matrix_allocated - Get the number of allocated non-managed irqs on the local CPU * @m: Pointer to the matrix to search * - * This returns number of allocated irqs + * This returns number of allocated non-managed interrupts. */ unsigned int irq_matrix_allocated(struct irq_matrix *m) { struct cpumap *cm = this_cpu_ptr(m->maps); - return cm->allocated; + return cm->allocated - cm->managed_allocated; } #ifdef CONFIG_GENERIC_IRQ_DEBUGFS diff --git a/kernel/kexec_core.c b/kernel/kexec_core.c index 6b3d7f7211dd6a2f749b246caf1ebed433ecda8e..3666d434a8f5937db3900047ed6fc38f9a778d35 100644 --- a/kernel/kexec_core.c +++ b/kernel/kexec_core.c @@ -1020,6 +1020,7 @@ int crash_shrink_memory(unsigned long new_size) start = crashk_res.start; end = crashk_res.end; old_size = (end == 0) ? 0 : end - start + 1; + new_size = roundup(new_size, KEXEC_CRASH_MEM_ALIGN); if (new_size >= old_size) { ret = (new_size == old_size) ? 0 : -EINVAL; goto unlock; @@ -1031,9 +1032,7 @@ int crash_shrink_memory(unsigned long new_size) goto unlock; } - start = roundup(start, KEXEC_CRASH_MEM_ALIGN); - end = roundup(start + new_size, KEXEC_CRASH_MEM_ALIGN); - + end = start + new_size; crash_free_reserved_phys_range(end, crashk_res.end); if ((start == end) && (crashk_res.parent != NULL)) diff --git a/kernel/kexec_file.c b/kernel/kexec_file.c index ab1934a2b2e6e90e201a287a13ad02c9085f5d8a..416c1e0fdc918befbea6fefb5cc4088015162a02 100644 --- a/kernel/kexec_file.c +++ b/kernel/kexec_file.c @@ -793,10 +793,22 @@ static int kexec_purgatory_setup_sechdrs(struct purgatory_info *pi, } offset = ALIGN(offset, align); + + /* + * Check if the segment contains the entry point, if so, + * calculate the value of image->start based on it. + * If the compiler has produced more than one .text section + * (Eg: .text.hot), they are generally after the main .text + * section, and they shall not be used to calculate + * image->start. So do not re-calculate image->start if it + * is not set to the initial value, and warn the user so they + * have a chance to fix their purgatory's linker script. + */ if (sechdrs[i].sh_flags & SHF_EXECINSTR && pi->ehdr->e_entry >= sechdrs[i].sh_addr && pi->ehdr->e_entry < (sechdrs[i].sh_addr - + sechdrs[i].sh_size)) { + + sechdrs[i].sh_size) && + !WARN_ON(kbuf->image->start != pi->ehdr->e_entry)) { kbuf->image->start -= sechdrs[i].sh_addr; kbuf->image->start += kbuf->mem + offset; } diff --git a/kernel/kprobes.c b/kernel/kprobes.c index 33aba4e2e3e3932c0dac30fa47c2c3c122c059d1..e1fb6453e8e95f3b014205e4de31ad22df32d459 100644 --- a/kernel/kprobes.c +++ b/kernel/kprobes.c @@ -418,8 +418,8 @@ static inline int kprobe_optready(struct kprobe *p) return 0; } -/* Return true(!0) if the kprobe is disarmed. Note: p must be on hash list */ -static inline int kprobe_disarmed(struct kprobe *p) +/* Return true if the kprobe is disarmed. Note: p must be on hash list */ +bool kprobe_disarmed(struct kprobe *p) { struct optimized_kprobe *op; @@ -626,7 +626,7 @@ void wait_for_kprobe_optimizer(void) mutex_unlock(&kprobe_mutex); } -static bool optprobe_queued_unopt(struct optimized_kprobe *op) +bool optprobe_queued_unopt(struct optimized_kprobe *op) { struct optimized_kprobe *_op; diff --git a/kernel/locking/lockdep.c b/kernel/locking/lockdep.c index d4a21d535592bdab8c160979df46ff0b79a56bdc..0d054afc38401b2a8599d9355f4e3760a2d37c60 100644 --- a/kernel/locking/lockdep.c +++ b/kernel/locking/lockdep.c @@ -1277,7 +1277,7 @@ static int noop_count(struct lock_list *entry, void *data) static unsigned long __lockdep_count_forward_deps(struct lock_list *this) { unsigned long count = 0; - struct lock_list *uninitialized_var(target_entry); + struct lock_list *target_entry; __bfs_forwards(this, (void *)&count, noop_count, &target_entry); @@ -1305,7 +1305,7 @@ unsigned long lockdep_count_forward_deps(struct lock_class *class) static unsigned long __lockdep_count_backward_deps(struct lock_list *this) { unsigned long count = 0; - struct lock_list *uninitialized_var(target_entry); + struct lock_list *target_entry; __bfs_backwards(this, (void *)&count, noop_count, &target_entry); @@ -2693,7 +2693,7 @@ check_usage_backwards(struct task_struct *curr, struct held_lock *this, { int ret; struct lock_list root; - struct lock_list *uninitialized_var(target_entry); + struct lock_list *target_entry; root.parent = NULL; root.class = hlock_class(this); diff --git a/kernel/locking/test-ww_mutex.c b/kernel/locking/test-ww_mutex.c index 65a3b7e55b9fcd2b289e09d194a179f1cc8accc5..4fd05d9d5d6d12e0ce78660a9212285a03b5335d 100644 --- a/kernel/locking/test-ww_mutex.c +++ b/kernel/locking/test-ww_mutex.c @@ -439,7 +439,6 @@ static void stress_inorder_work(struct work_struct *work) } while (!time_after(jiffies, stress->timeout)); kfree(order); - kfree(stress); } struct reorder_lock { @@ -504,7 +503,6 @@ static void stress_reorder_work(struct work_struct *work) list_for_each_entry_safe(ll, ln, &locks, link) kfree(ll); kfree(order); - kfree(stress); } static void stress_one_work(struct work_struct *work) @@ -525,8 +523,6 @@ static void stress_one_work(struct work_struct *work) break; } } while (!time_after(jiffies, stress->timeout)); - - kfree(stress); } #define STRESS_INORDER BIT(0) @@ -537,15 +533,24 @@ static void stress_one_work(struct work_struct *work) static int stress(int nlocks, int nthreads, unsigned int flags) { struct ww_mutex *locks; - int n; + struct stress *stress_array; + int n, count; locks = kmalloc_array(nlocks, sizeof(*locks), GFP_KERNEL); if (!locks) return -ENOMEM; + stress_array = kmalloc_array(nthreads, sizeof(*stress_array), + GFP_KERNEL); + if (!stress_array) { + kfree(locks); + return -ENOMEM; + } + for (n = 0; n < nlocks; n++) ww_mutex_init(&locks[n], &ww_class); + count = 0; for (n = 0; nthreads; n++) { struct stress *stress; void (*fn)(struct work_struct *work); @@ -569,9 +574,7 @@ static int stress(int nlocks, int nthreads, unsigned int flags) if (!fn) continue; - stress = kmalloc(sizeof(*stress), GFP_KERNEL); - if (!stress) - break; + stress = &stress_array[count++]; INIT_WORK(&stress->work, fn); stress->locks = locks; @@ -586,6 +589,7 @@ static int stress(int nlocks, int nthreads, unsigned int flags) for (n = 0; n < nlocks; n++) ww_mutex_destroy(&locks[n]); + kfree(stress_array); kfree(locks); return 0; diff --git a/kernel/module.c b/kernel/module.c index 0f2ccabca8dbf773be3ef68888fc75637534f4c6..b8c25c751586a6e69bf4196ff33ee782c5b4793a 100644 --- a/kernel/module.c +++ b/kernel/module.c @@ -2244,15 +2244,26 @@ static void free_module(struct module *mod) void *__symbol_get(const char *symbol) { struct module *owner; + enum mod_license license; const struct kernel_symbol *sym; preempt_disable(); - sym = find_symbol(symbol, &owner, NULL, NULL, true, true); - if (sym && strong_try_module_get(owner)) + sym = find_symbol(symbol, &owner, NULL, &license, true, true); + if (!sym) + goto fail; + if (license != GPL_ONLY) { + pr_warn("failing symbol_get of non-GPLONLY symbol %s.\n", + symbol); + goto fail; + } + if (strong_try_module_get(owner)) sym = NULL; preempt_enable(); return sym ? (void *)kernel_symbol_value(sym) : NULL; +fail: + preempt_enable(); + return NULL; } EXPORT_SYMBOL_GPL(__symbol_get); diff --git a/kernel/padata.c b/kernel/padata.c index 93e4fb2d9f2ee04e57604e1347c796f6e4446a97..848e40e3581b8095f6db6aee6cbd4b560ff2f818 100644 --- a/kernel/padata.c +++ b/kernel/padata.c @@ -121,7 +121,7 @@ int padata_do_parallel(struct padata_instance *pinst, if (!cpumask_test_cpu(cb_cpu, pd->cpumask.cbcpu)) goto out; - err = -EBUSY; + err = -EBUSY; if ((pinst->flags & PADATA_RESET)) goto out; diff --git a/kernel/panic.c b/kernel/panic.c index dbc7798af194bf0411156145987672b9945a7cc8..b75217a759a7bb043949ebec379a53e4ae4c6f04 100644 --- a/kernel/panic.c +++ b/kernel/panic.c @@ -205,20 +205,20 @@ void panic(const char *fmt, ...) int state = 0; int old_cpu, this_cpu; bool _crash_kexec_post_notifiers = crash_kexec_post_notifiers; - - if (panic_on_warn) { - /* - * This thread may hit another WARN() in the panic path. - * Resetting this prevents additional WARN() from panicking the - * system on this thread. Other threads are blocked by the - * panic_mutex in panic(). - */ - panic_on_warn = 0; - } - #ifdef OPLUS_FEATURE_AGINGTEST char *function_name; #endif /*OPLUS_FEATURE_AGINGTEST*/ + + if (panic_on_warn) { + /* + * This thread may hit another WARN() in the panic path. + * Resetting this prevents additional WARN() from panicking the + * system on this thread. Other threads are blocked by the + * panic_mutex in panic(). + */ + panic_on_warn = 0; + } + /* * Disable local interrupts. This will prevent panic_smp_self_stop * from deadlocking the first cpu that invokes the panic, since diff --git a/kernel/power/snapshot.c b/kernel/power/snapshot.c index 2505d25f89a1b10c9ad990485246806725302e5b..50174dd636c8764666f60128da9d10e7efc63e5f 100644 --- a/kernel/power/snapshot.c +++ b/kernel/power/snapshot.c @@ -2376,8 +2376,9 @@ static void *get_highmem_page_buffer(struct page *page, pbe->copy_page = tmp; } else { /* Copy of the page will be stored in normal memory */ - kaddr = safe_pages_list; - safe_pages_list = safe_pages_list->next; + kaddr = __get_safe_page(ca->gfp_mask); + if (!kaddr) + return ERR_PTR(-ENOMEM); pbe->copy_page = virt_to_page(kaddr); } pbe->next = highmem_pblist; @@ -2557,8 +2558,9 @@ static void *get_buffer(struct memory_bitmap *bm, struct chain_allocator *ca) return ERR_PTR(-ENOMEM); } pbe->orig_address = page_address(page); - pbe->address = safe_pages_list; - safe_pages_list = safe_pages_list->next; + pbe->address = __get_safe_page(ca->gfp_mask); + if (!pbe->address) + return ERR_PTR(-ENOMEM); pbe->next = restore_pblist; restore_pblist = pbe; return pbe->address; @@ -2589,8 +2591,6 @@ int snapshot_write_next(struct snapshot_handle *handle) if (handle->cur > 1 && handle->cur > nr_meta_pages + nr_copy_pages) return 0; - handle->sync_read = 1; - if (!handle->cur) { if (!buffer) /* This makes the buffer be freed by swsusp_free() */ @@ -2631,7 +2631,6 @@ int snapshot_write_next(struct snapshot_handle *handle) memory_bm_position_reset(&orig_bm); restore_pblist = NULL; handle->buffer = get_buffer(&orig_bm, &ca); - handle->sync_read = 0; if (IS_ERR(handle->buffer)) return PTR_ERR(handle->buffer); } @@ -2643,9 +2642,8 @@ int snapshot_write_next(struct snapshot_handle *handle) handle->buffer = get_buffer(&orig_bm, &ca); if (IS_ERR(handle->buffer)) return PTR_ERR(handle->buffer); - if (handle->buffer != buffer) - handle->sync_read = 0; } + handle->sync_read = (handle->buffer == buffer); handle->cur++; return PAGE_SIZE; } diff --git a/kernel/rcu/tree_exp.h b/kernel/rcu/tree_exp.h index 062d2788127fd0d3d60e5727c62ed41b55bf328a..ea4ea1c17e1a3ba7d1326cc9eede55c171569076 100644 --- a/kernel/rcu/tree_exp.h +++ b/kernel/rcu/tree_exp.h @@ -577,7 +577,9 @@ static void synchronize_sched_expedited_wait(struct rcu_state *rsp) mask = leaf_node_cpu_bit(rnp, cpu); if (!(rnp->expmask & mask)) continue; + preempt_disable(); // For smp_processor_id() in dump_cpu_task(). dump_cpu_task(cpu); + preempt_enable(); } } jiffies_stall = 3 * rcu_jiffies_till_stall_check() + 3; diff --git a/kernel/relay.c b/kernel/relay.c index b7aa7df43955bf651d9e98711f55dd5a48fd560a..e6f70f4c41a36ceeac4c50b7a08e46e8aab018fa 100644 --- a/kernel/relay.c +++ b/kernel/relay.c @@ -997,14 +997,14 @@ static void relay_file_read_consume(struct rchan_buf *buf, /* * relay_file_read_avail - boolean, are there unconsumed bytes available? */ -static int relay_file_read_avail(struct rchan_buf *buf, size_t read_pos) +static int relay_file_read_avail(struct rchan_buf *buf) { size_t subbuf_size = buf->chan->subbuf_size; size_t n_subbufs = buf->chan->n_subbufs; size_t produced = buf->subbufs_produced; size_t consumed = buf->subbufs_consumed; - relay_file_read_consume(buf, read_pos, 0); + relay_file_read_consume(buf, 0, 0); consumed = buf->subbufs_consumed; @@ -1065,23 +1065,21 @@ static size_t relay_file_read_subbuf_avail(size_t read_pos, /** * relay_file_read_start_pos - find the first available byte to read - * @read_pos: file read position * @buf: relay channel buffer * - * If the @read_pos is in the middle of padding, return the + * If the read_pos is in the middle of padding, return the * position of the first actually available byte, otherwise * return the original value. */ -static size_t relay_file_read_start_pos(size_t read_pos, - struct rchan_buf *buf) +static size_t relay_file_read_start_pos(struct rchan_buf *buf) { size_t read_subbuf, padding, padding_start, padding_end; size_t subbuf_size = buf->chan->subbuf_size; size_t n_subbufs = buf->chan->n_subbufs; size_t consumed = buf->subbufs_consumed % n_subbufs; + size_t read_pos = (consumed * subbuf_size + buf->bytes_consumed) + % (n_subbufs * subbuf_size); - if (!read_pos) - read_pos = consumed * subbuf_size + buf->bytes_consumed; read_subbuf = read_pos / subbuf_size; padding = buf->padding[read_subbuf]; padding_start = (read_subbuf + 1) * subbuf_size - padding; @@ -1137,10 +1135,10 @@ static ssize_t relay_file_read(struct file *filp, do { void *from; - if (!relay_file_read_avail(buf, *ppos)) + if (!relay_file_read_avail(buf)) break; - read_start = relay_file_read_start_pos(*ppos, buf); + read_start = relay_file_read_start_pos(buf); avail = relay_file_read_subbuf_avail(read_start, buf); if (!avail) break; diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 1bd0e70e1ec945a3f482c6607781e5635bfcadb5..5075d109559331cc216d10aa6f0f2772b8025bb2 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -1454,6 +1454,9 @@ static inline void dequeue_task(struct rq *rq, struct task_struct *p, int flags) void activate_task(struct rq *rq, struct task_struct *p, int flags) { + if (task_on_rq_migrating(p)) + flags |= ENQUEUE_MIGRATED; + if (task_contributes_to_load(p)) rq->nr_uninterruptible--; @@ -6006,14 +6009,14 @@ SYSCALL_DEFINE3(sched_getaffinity, pid_t, pid, unsigned int, len, if (len & (sizeof(unsigned long)-1)) return -EINVAL; - if (!alloc_cpumask_var(&mask, GFP_KERNEL)) + if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) return -ENOMEM; ret = sched_getaffinity(pid, mask); if (ret == 0) { unsigned int retlen = min(len, cpumask_size()); - if (copy_to_user(user_mask_ptr, mask, retlen)) + if (copy_to_user(user_mask_ptr, cpumask_bits(mask), retlen)) ret = -EFAULT; else ret = retlen; diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index b31d6e5b905d250b6b43cb55484cb6874273e8b8..423ed3eea7dad2620c99e97cc9244ed37c997ea3 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -4205,6 +4205,29 @@ static void check_spread(struct cfs_rq *cfs_rq, struct sched_entity *se) #endif } +static inline bool entity_is_long_sleeper(struct sched_entity *se) +{ + struct cfs_rq *cfs_rq; + u64 sleep_time; + + if (se->exec_start == 0) + return false; + + cfs_rq = cfs_rq_of(se); + + sleep_time = rq_clock_task(rq_of(cfs_rq)); + + /* Happen while migrating because of clock task divergence */ + if (sleep_time <= se->exec_start) + return false; + + sleep_time -= se->exec_start; + if (sleep_time > ((1ULL << 63) / scale_load_down(NICE_0_LOAD))) + return true; + + return false; +} + static void place_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int initial) { @@ -4255,10 +4278,31 @@ place_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int initial) #endif } - /* ensure we never gain time by being placed backwards. */ - se->vruntime = max_vruntime(se->vruntime, vruntime); + /* + * Pull vruntime of the entity being placed to the base level of + * cfs_rq, to prevent boosting it if placed backwards. + * However, min_vruntime can advance much faster than real time, with + * the extreme being when an entity with the minimal weight always runs + * on the cfs_rq. If the waking entity slept for a long time, its + * vruntime difference from min_vruntime may overflow s64 and their + * comparison may get inversed, so ignore the entity's original + * vruntime in that case. + * The maximal vruntime speedup is given by the ratio of normal to + * minimal weight: scale_load_down(NICE_0_LOAD) / MIN_SHARES. + * When placing a migrated waking entity, its exec_start has been set + * from a different rq. In order to take into account a possible + * divergence between new and prev rq's clocks task because of irq and + * stolen time, we take an additional margin. + * So, cutting off on the sleep time of + * 2^63 / scale_load_down(NICE_0_LOAD) ~ 104 days + * should be safe. + */ + if (entity_is_long_sleeper(se)) + se->vruntime = vruntime; + else + se->vruntime = max_vruntime(se->vruntime, vruntime); #ifdef OPLUS_FEATURE_SCHED_ASSIST - place_entity_adjust_ux_task(cfs_rq, se, initial); + place_entity_adjust_ux_task(cfs_rq, se, initial); #endif } @@ -4354,6 +4398,9 @@ enqueue_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags) if (flags & ENQUEUE_WAKEUP) place_entity(cfs_rq, se, 0); + /* Entity has migrated, no longer consider this task hot */ + if (flags & ENQUEUE_MIGRATED) + se->exec_start = 0; check_schedstat_required(); update_stats_enqueue(cfs_rq, se, flags); @@ -8302,9 +8349,6 @@ static void migrate_task_rq_fair(struct task_struct *p, int new_cpu) /* Tell new CPU we are migrated */ p->se.avg.last_update_time = 0; - /* We have migrated, no longer consider this task hot */ - p->se.exec_start = 0; - update_scan_period(p, new_cpu); } @@ -10998,7 +11042,7 @@ static int load_balance(int this_cpu, struct rq *this_rq, .sd = sd, .dst_cpu = this_cpu, .dst_rq = this_rq, - .dst_grpmask = sched_group_span(sd->groups), + .dst_grpmask = group_balance_mask(sd->groups), .idle = idle, .loop_break = sched_nr_migrate_break, .cpus = cpus, diff --git a/kernel/sched/idle.c b/kernel/sched/idle.c index aa67df67dd71c302dac8b959bf9569fe538fa1ba..684827bddfa2ad94d017d86b82a23365e2849f2e 100644 --- a/kernel/sched/idle.c +++ b/kernel/sched/idle.c @@ -54,18 +54,19 @@ __setup("hlt", cpu_idle_nopoll_setup); static noinline int __cpuidle cpu_idle_poll(void) { + trace_cpu_idle(0, smp_processor_id()); + stop_critical_timings(); rcu_idle_enter(); - trace_cpu_idle_rcuidle(0, smp_processor_id()); local_irq_enable(); - stop_critical_timings(); while (!tif_need_resched() && - (cpu_idle_force_poll || tick_check_broadcast_expired() || + (cpu_idle_force_poll || tick_check_broadcast_expired() || is_reserved(smp_processor_id()))) cpu_relax(); - start_critical_timings(); - trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); + rcu_idle_exit(); + start_critical_timings(); + trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); return 1; } @@ -92,7 +93,9 @@ void __cpuidle default_idle_call(void) local_irq_enable(); } else { stop_critical_timings(); + rcu_idle_enter(); arch_cpu_idle(); + rcu_idle_exit(); start_critical_timings(); } } @@ -150,7 +153,6 @@ static void cpuidle_idle_call(void) if (cpuidle_not_available(drv, dev)) { tick_nohz_idle_stop_tick(); - rcu_idle_enter(); default_idle_call(); goto exit_idle; @@ -168,19 +170,15 @@ static void cpuidle_idle_call(void) if (idle_should_enter_s2idle() || dev->use_deepest_state) { if (idle_should_enter_s2idle()) { - rcu_idle_enter(); entered_state = cpuidle_enter_s2idle(drv, dev); if (entered_state > 0) { local_irq_enable(); goto exit_idle; } - - rcu_idle_exit(); } tick_nohz_idle_stop_tick(); - rcu_idle_enter(); next_state = cpuidle_find_deepest_state(drv, dev); call_cpuidle(drv, dev, next_state); @@ -197,8 +195,6 @@ static void cpuidle_idle_call(void) else tick_nohz_idle_retain_tick(); - rcu_idle_enter(); - entered_state = call_cpuidle(drv, dev, next_state); /* * Give the governor an opportunity to reflect on the outcome @@ -214,8 +210,6 @@ static void cpuidle_idle_call(void) */ if (WARN_ON_ONCE(irqs_disabled())) local_irq_enable(); - - rcu_idle_exit(); } /* diff --git a/kernel/sched/rt.c b/kernel/sched/rt.c index 834390c56b50d1616db3e6bd67c9c941a9048e36..71c63fdbe6c1d7e614a3fef694343710ebab7b43 100644 --- a/kernel/sched/rt.c +++ b/kernel/sched/rt.c @@ -1640,6 +1640,8 @@ static struct sched_rt_entity *pick_next_rt_entity(struct rq *rq, BUG_ON(idx >= MAX_RT_PRIO); queue = array->queue + idx; + if (SCHED_WARN_ON(list_empty(queue))) + return NULL; next = list_entry(queue->next, struct sched_rt_entity, run_list); return next; @@ -1653,7 +1655,8 @@ static struct task_struct *_pick_next_task_rt(struct rq *rq) do { rt_se = pick_next_rt_entity(rq, rt_rq); - BUG_ON(!rt_se); + if (unlikely(!rt_se)) + return NULL; rt_rq = group_rt_rq(rt_se); } while (rt_rq); diff --git a/kernel/sched/walt.h b/kernel/sched/walt.h index 36eaff2613c69a0c681afe165a9cdb38681aa543..cc3f3fa7e9dfb5ac44c1358fff428b4e16175a8c 100644 --- a/kernel/sched/walt.h +++ b/kernel/sched/walt.h @@ -104,14 +104,34 @@ fixup_cumulative_runnable_avg(struct walt_sched_stats *stats, s64 demand_scaled_delta, s64 pred_demand_scaled_delta) { + s64 cumulative_runnable_avg_scaled; + s64 pred_demands_sum_scaled; + if (sched_disable_window_stats) return; - stats->cumulative_runnable_avg_scaled += demand_scaled_delta; - BUG_ON((s64)stats->cumulative_runnable_avg_scaled < 0); - - stats->pred_demands_sum_scaled += pred_demand_scaled_delta; - BUG_ON((s64)stats->pred_demands_sum_scaled < 0); + cumulative_runnable_avg_scaled = + (s64)stats->cumulative_runnable_avg_scaled + + demand_scaled_delta; + pred_demands_sum_scaled = + (s64)stats->pred_demands_sum_scaled + pred_demand_scaled_delta; + + if (cumulative_runnable_avg_scaled < 0) { + printk_deferred("WALT-BUG demand_scaled_delta=%lld cumulative_runnable_avg_scaled=%llu\n", + demand_scaled_delta, + stats->cumulative_runnable_avg_scaled); + cumulative_runnable_avg_scaled = 0; + } + stats->cumulative_runnable_avg_scaled = + (u64)cumulative_runnable_avg_scaled; + + if (pred_demands_sum_scaled < 0) { + printk_deferred("WALT-BUG task pred_demand_scaled_delta=%lld pred_demands_sum_scaled=%llu\n", + pred_demand_scaled_delta, + stats->pred_demands_sum_scaled); + pred_demands_sum_scaled = 0; + } + stats->pred_demands_sum_scaled = (u64)pred_demands_sum_scaled; } static inline void diff --git a/kernel/time/hrtimer.c b/kernel/time/hrtimer.c index c9e1378b4541c6ba91ee632fd29a60cf41d6c08e..1d07f277c936d4765ad5dfc437d747ca3c00df1c 100644 --- a/kernel/time/hrtimer.c +++ b/kernel/time/hrtimer.c @@ -1856,6 +1856,7 @@ SYSCALL_DEFINE2(nanosleep, struct __kernel_timespec __user *, rqtp, if (!timespec64_valid(&tu)) return -EINVAL; + current->restart_block.fn = do_no_restart_syscall; current->restart_block.nanosleep.type = rmtp ? TT_NATIVE : TT_NONE; current->restart_block.nanosleep.rmtp = rmtp; return hrtimer_nanosleep(&tu, HRTIMER_MODE_REL, CLOCK_MONOTONIC); @@ -1876,6 +1877,7 @@ COMPAT_SYSCALL_DEFINE2(nanosleep, struct compat_timespec __user *, rqtp, if (!timespec64_valid(&tu)) return -EINVAL; + current->restart_block.fn = do_no_restart_syscall; current->restart_block.nanosleep.type = rmtp ? TT_COMPAT : TT_NONE; current->restart_block.nanosleep.compat_rmtp = rmtp; return hrtimer_nanosleep(&tu, HRTIMER_MODE_REL, CLOCK_MONOTONIC); diff --git a/kernel/time/posix-stubs.c b/kernel/time/posix-stubs.c index 2c6847d5d69bae179291f1a6259f611e469dfb8c..362c159fb3f88c47652399d33b15e1747448542f 100644 --- a/kernel/time/posix-stubs.c +++ b/kernel/time/posix-stubs.c @@ -144,6 +144,7 @@ SYSCALL_DEFINE4(clock_nanosleep, const clockid_t, which_clock, int, flags, return -EINVAL; if (flags & TIMER_ABSTIME) rmtp = NULL; + current->restart_block.fn = do_no_restart_syscall; current->restart_block.nanosleep.type = rmtp ? TT_NATIVE : TT_NONE; current->restart_block.nanosleep.rmtp = rmtp; return hrtimer_nanosleep(&t, flags & TIMER_ABSTIME ? @@ -230,6 +231,7 @@ COMPAT_SYSCALL_DEFINE4(clock_nanosleep, clockid_t, which_clock, int, flags, return -EINVAL; if (flags & TIMER_ABSTIME) rmtp = NULL; + current->restart_block.fn = do_no_restart_syscall; current->restart_block.nanosleep.type = rmtp ? TT_COMPAT : TT_NONE; current->restart_block.nanosleep.compat_rmtp = rmtp; return hrtimer_nanosleep(&t, flags & TIMER_ABSTIME ? diff --git a/kernel/time/posix-timers.c b/kernel/time/posix-timers.c index 48758108e055cd8d89d310c82dd0ca91bc36875f..1234868b3b03ebef152352f3cb58fd16e856c188 100644 --- a/kernel/time/posix-timers.c +++ b/kernel/time/posix-timers.c @@ -1225,6 +1225,7 @@ SYSCALL_DEFINE4(clock_nanosleep, const clockid_t, which_clock, int, flags, return -EINVAL; if (flags & TIMER_ABSTIME) rmtp = NULL; + current->restart_block.fn = do_no_restart_syscall; current->restart_block.nanosleep.type = rmtp ? TT_NATIVE : TT_NONE; current->restart_block.nanosleep.rmtp = rmtp; @@ -1252,6 +1253,7 @@ COMPAT_SYSCALL_DEFINE4(clock_nanosleep, clockid_t, which_clock, int, flags, return -EINVAL; if (flags & TIMER_ABSTIME) rmtp = NULL; + current->restart_block.fn = do_no_restart_syscall; current->restart_block.nanosleep.type = rmtp ? TT_COMPAT : TT_NONE; current->restart_block.nanosleep.compat_rmtp = rmtp; diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c index cb91395ac46171b4d1fa0f8fbaae23e3e4936c76..2b9a12622f012d3ccef394e0c83366afbbca3389 100644 --- a/kernel/time/tick-sched.c +++ b/kernel/time/tick-sched.c @@ -205,6 +205,11 @@ static bool check_tick_dependency(atomic_t *dep) return true; } + if (val & TICK_DEP_MASK_RCU) { + trace_tick_stop(0, TICK_DEP_MASK_RCU); + return true; + } + return false; } @@ -331,6 +336,7 @@ void tick_nohz_dep_set_cpu(int cpu, enum tick_dep_bits bit) preempt_enable(); } } +EXPORT_SYMBOL_GPL(tick_nohz_dep_set_cpu); void tick_nohz_dep_clear_cpu(int cpu, enum tick_dep_bits bit) { @@ -338,6 +344,7 @@ void tick_nohz_dep_clear_cpu(int cpu, enum tick_dep_bits bit) atomic_andnot(BIT(bit), &ts->tick_dep_mask); } +EXPORT_SYMBOL_GPL(tick_nohz_dep_clear_cpu); /* * Set a per-task tick dependency. Posix CPU timers need this in order to elapse @@ -405,7 +412,7 @@ void __init tick_nohz_full_setup(cpumask_var_t cpumask) tick_nohz_full_running = true; } -static int tick_nohz_cpu_down(unsigned int cpu) +bool tick_nohz_cpu_hotpluggable(unsigned int cpu) { /* * The boot CPU handles housekeeping duty (unbound timers, @@ -413,8 +420,13 @@ static int tick_nohz_cpu_down(unsigned int cpu) * CPUs. It must remain online when nohz full is enabled. */ if (tick_nohz_full_running && tick_do_timer_cpu == cpu) - return -EBUSY; - return 0; + return false; + return true; +} + +static int tick_nohz_cpu_down(unsigned int cpu) +{ + return tick_nohz_cpu_hotpluggable(cpu) ? 0 : -EBUSY; } void __init tick_nohz_init(void) diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index 24f80992aebd8b4ac83b008adbd17066abda4f37..6317249a434fda353e3e5188a429c1a08aa1026c 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -1276,7 +1276,7 @@ int bpf_get_perf_event_info(const struct perf_event *event, u32 *prog_id, #ifdef CONFIG_UPROBE_EVENTS if (flags & TRACE_EVENT_FL_UPROBE) err = bpf_get_uprobe_info(event, fd_type, buf, - probe_offset, + probe_offset, probe_addr, event->attr.type == PERF_TYPE_TRACEPOINT); #endif } diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index 3f5f26173d331ba6482fc21bf318ad12b7baa7d0..3f5e914ed6b867f802d2a3c0d63b22f654dd77cb 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -1125,7 +1125,7 @@ struct ftrace_page { struct ftrace_page *next; struct dyn_ftrace *records; int index; - int size; + int order; }; #define ENTRY_SIZE sizeof(struct dyn_ftrace) @@ -1582,7 +1582,8 @@ unsigned long ftrace_location_range(unsigned long start, unsigned long end) key.flags = end; /* overload flags, as it is unsigned long */ for (pg = ftrace_pages_start; pg; pg = pg->next) { - if (end < pg->records[0].ip || + if (pg->index == 0 || + end < pg->records[0].ip || start >= (pg->records[pg->index - 1].ip + MCOUNT_INSN_SIZE)) continue; rec = bsearch(&key, pg->records, pg->index, @@ -2915,6 +2916,8 @@ static void ftrace_shutdown_sysctl(void) static u64 ftrace_update_time; unsigned long ftrace_update_tot_cnt; +unsigned long ftrace_number_of_pages; +unsigned long ftrace_number_of_groups; static inline int ops_traces_mod(struct ftrace_ops *ops) { @@ -3039,8 +3042,11 @@ static int ftrace_allocate_records(struct ftrace_page *pg, int count) goto again; } + ftrace_number_of_pages += 1 << order; + ftrace_number_of_groups++; + cnt = (PAGE_SIZE << order) / ENTRY_SIZE; - pg->size = cnt; + pg->order = order; if (cnt > count) cnt = count; @@ -3048,12 +3054,27 @@ static int ftrace_allocate_records(struct ftrace_page *pg, int count) return cnt; } +static void ftrace_free_pages(struct ftrace_page *pages) +{ + struct ftrace_page *pg = pages; + + while (pg) { + if (pg->records) { + free_pages((unsigned long)pg->records, pg->order); + ftrace_number_of_pages -= 1 << pg->order; + } + pages = pg->next; + kfree(pg); + pg = pages; + ftrace_number_of_groups--; + } +} + static struct ftrace_page * ftrace_allocate_pages(unsigned long num_to_init) { struct ftrace_page *start_pg; struct ftrace_page *pg; - int order; int cnt; if (!num_to_init) @@ -3087,14 +3108,7 @@ ftrace_allocate_pages(unsigned long num_to_init) return start_pg; free_pages: - pg = start_pg; - while (pg) { - order = get_count_order(pg->size / ENTRIES_PER_PAGE); - free_pages((unsigned long)pg->records, order); - start_pg = pg->next; - kfree(pg); - pg = start_pg; - } + ftrace_free_pages(start_pg); pr_info("ftrace: FAILED to allocate memory for functions\n"); return NULL; } @@ -5586,9 +5600,11 @@ static int __norecordmcount ftrace_process_locs(struct module *mod, unsigned long *start, unsigned long *end) { + struct ftrace_page *pg_unuse = NULL; struct ftrace_page *start_pg; struct ftrace_page *pg; struct dyn_ftrace *rec; + unsigned long skipped = 0; unsigned long count; unsigned long *p; unsigned long addr; @@ -5634,6 +5650,7 @@ static int __norecordmcount ftrace_process_locs(struct module *mod, p = start; pg = start_pg; while (p < end) { + unsigned long end_offset; addr = ftrace_call_adjust(*p++); /* * Some architecture linkers will pad between @@ -5641,10 +5658,13 @@ static int __norecordmcount ftrace_process_locs(struct module *mod, * object files to satisfy alignments. * Skip any NULL pointers. */ - if (!addr) + if (!addr) { + skipped++; continue; + } - if (pg->index == pg->size) { + end_offset = (pg->index+1) * sizeof(pg->records[0]); + if (end_offset > PAGE_SIZE << pg->order) { /* We should have allocated enough */ if (WARN_ON(!pg->next)) break; @@ -5655,8 +5675,10 @@ static int __norecordmcount ftrace_process_locs(struct module *mod, rec->ip = addr; } - /* We should have used all pages */ - WARN_ON(pg->next); + if (pg->next) { + pg_unuse = pg->next; + pg->next = NULL; + } /* Assign the last page to ftrace_pages */ ftrace_pages = pg; @@ -5678,6 +5700,11 @@ static int __norecordmcount ftrace_process_locs(struct module *mod, out: mutex_unlock(&ftrace_lock); + /* We should have used all pages unless we skipped some */ + if (pg_unuse) { + WARN_ON(!skipped); + ftrace_free_pages(pg_unuse); + } return ret; } @@ -5784,7 +5811,6 @@ void ftrace_release_mod(struct module *mod) struct ftrace_page **last_pg; struct ftrace_page *tmp_page = NULL; struct ftrace_page *pg; - int order; mutex_lock(&ftrace_lock); @@ -5835,10 +5861,13 @@ void ftrace_release_mod(struct module *mod) /* Needs to be called outside of ftrace_lock */ clear_mod_from_hashes(pg); - order = get_count_order(pg->size / ENTRIES_PER_PAGE); - free_pages((unsigned long)pg->records, order); + if (pg->records) { + free_pages((unsigned long)pg->records, pg->order); + ftrace_number_of_pages -= 1 << pg->order; + } tmp_page = pg->next; kfree(pg); + ftrace_number_of_groups--; } } @@ -6144,7 +6173,6 @@ void ftrace_free_mem(struct module *mod, void *start_ptr, void *end_ptr) struct ftrace_mod_map *mod_map = NULL; struct ftrace_init_func *func, *func_next; struct list_head clear_hash; - int order; INIT_LIST_HEAD(&clear_hash); @@ -6182,8 +6210,11 @@ void ftrace_free_mem(struct module *mod, void *start_ptr, void *end_ptr) ftrace_update_tot_cnt--; if (!pg->index) { *last_pg = pg->next; - order = get_count_order(pg->size / ENTRIES_PER_PAGE); - free_pages((unsigned long)pg->records, order); + if (pg->records) { + free_pages((unsigned long)pg->records, pg->order); + ftrace_number_of_pages -= 1 << pg->order; + } + ftrace_number_of_groups--; kfree(pg); pg = container_of(last_pg, struct ftrace_page, next); if (!(*last_pg)) @@ -6239,6 +6270,9 @@ void __init ftrace_init(void) __start_mcount_loc, __stop_mcount_loc); + pr_info("ftrace: allocated %ld pages with %ld groups\n", + ftrace_number_of_pages, ftrace_number_of_groups); + set_ftrace_early_filters(); return; diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index 5e5b0c067f61157a34ce0c2ee74da3c5e62b05ba..320aa60664dc9593a8a20b56b1f60e245e7420a5 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -493,6 +493,8 @@ struct ring_buffer_per_cpu { unsigned long read_bytes; u64 write_stamp; u64 read_stamp; + /* pages removed since last reset */ + unsigned long pages_removed; /* ring buffer pages to update, > 0 to add, < 0 to remove */ long nr_pages_to_update; struct list_head new_pages; /* new pages to add */ @@ -528,6 +530,7 @@ struct ring_buffer_iter { struct buffer_page *head_page; struct buffer_page *cache_reader_page; unsigned long cache_read; + unsigned long cache_pages_removed; u64 read_stamp; }; @@ -561,7 +564,7 @@ static void rb_wake_up_waiters(struct irq_work *work) */ int ring_buffer_wait(struct ring_buffer *buffer, int cpu, bool full) { - struct ring_buffer_per_cpu *uninitialized_var(cpu_buffer); + struct ring_buffer_per_cpu *cpu_buffer; DEFINE_WAIT(wait); struct rb_irq_work *work; int ret = 0; @@ -1326,6 +1329,8 @@ static void rb_free_cpu_buffer(struct ring_buffer_per_cpu *cpu_buffer) struct list_head *head = cpu_buffer->pages; struct buffer_page *bpage, *tmp; + irq_work_sync(&cpu_buffer->irq_work.work); + free_buffer_page(cpu_buffer->reader_page); if (head) { @@ -1431,6 +1436,8 @@ ring_buffer_free(struct ring_buffer *buffer) cpuhp_state_remove_instance(CPUHP_TRACE_RB_PREPARE, &buffer->node); + irq_work_sync(&buffer->irq_work.work); + for_each_buffer_cpu(buffer, cpu) rb_free_cpu_buffer(buffer->buffers[cpu]); @@ -1510,6 +1517,8 @@ rb_remove_pages(struct ring_buffer_per_cpu *cpu_buffer, unsigned long nr_pages) to_remove = rb_list_head(to_remove)->next; head_bit |= (unsigned long)to_remove & RB_PAGE_HEAD; } + /* Read iterators need to reset themselves when some pages removed */ + cpu_buffer->pages_removed += nr_removed; next_page = rb_list_head(to_remove)->next; @@ -1531,12 +1540,6 @@ rb_remove_pages(struct ring_buffer_per_cpu *cpu_buffer, unsigned long nr_pages) cpu_buffer->head_page = list_entry(next_page, struct buffer_page, list); - /* - * change read pointer to make sure any read iterators reset - * themselves - */ - cpu_buffer->read = 0; - /* pages are removed, resume tracing and then free the pages */ atomic_dec(&cpu_buffer->record_disabled); raw_spin_unlock_irq(&cpu_buffer->reader_lock); @@ -1750,6 +1753,8 @@ int ring_buffer_resize(struct ring_buffer *buffer, unsigned long size, err = -ENOMEM; goto out_err; } + + cond_resched(); } get_online_cpus(); @@ -2463,6 +2468,10 @@ rb_set_commit_to_write(struct ring_buffer_per_cpu *cpu_buffer) if (RB_WARN_ON(cpu_buffer, rb_is_reader_page(cpu_buffer->tail_page))) return; + /* + * No need for a memory barrier here, as the update + * of the tail_page did it for this page. + */ local_set(&cpu_buffer->commit_page->page->commit, rb_page_write(cpu_buffer->commit_page)); rb_inc_page(cpu_buffer, &cpu_buffer->commit_page); @@ -2476,6 +2485,8 @@ rb_set_commit_to_write(struct ring_buffer_per_cpu *cpu_buffer) while (rb_commit_index(cpu_buffer) != rb_page_write(cpu_buffer->commit_page)) { + /* Make sure the readers see the content of what is committed. */ + smp_wmb(); local_set(&cpu_buffer->commit_page->page->commit, rb_page_write(cpu_buffer->commit_page)); RB_WARN_ON(cpu_buffer, @@ -3572,6 +3583,7 @@ static void rb_iter_reset(struct ring_buffer_iter *iter) iter->cache_reader_page = iter->head_page; iter->cache_read = cpu_buffer->read; + iter->cache_pages_removed = cpu_buffer->pages_removed; if (iter->head) iter->read_stamp = cpu_buffer->read_stamp; @@ -3841,7 +3853,12 @@ rb_get_reader_page(struct ring_buffer_per_cpu *cpu_buffer) /* * Make sure we see any padding after the write update - * (see rb_reset_tail()) + * (see rb_reset_tail()). + * + * In addition, a writer may be writing on the reader page + * if the page has not been fully filled, so the read barrier + * is also needed to make sure we see the content of what is + * committed by the writer (see rb_set_commit_to_write()). */ smp_rmb(); @@ -4007,12 +4024,13 @@ rb_iter_peek(struct ring_buffer_iter *iter, u64 *ts) buffer = cpu_buffer->buffer; /* - * Check if someone performed a consuming read to - * the buffer. A consuming read invalidates the iterator - * and we need to reset the iterator in this case. + * Check if someone performed a consuming read to the buffer + * or removed some pages from the buffer. In these cases, + * iterator was invalidated and we need to reset it. */ if (unlikely(iter->cache_read != cpu_buffer->read || - iter->cache_reader_page != cpu_buffer->reader_page)) + iter->cache_reader_page != cpu_buffer->reader_page || + iter->cache_pages_removed != cpu_buffer->pages_removed)) rb_iter_reset(iter); again: @@ -4393,28 +4411,34 @@ unsigned long ring_buffer_size(struct ring_buffer *buffer, int cpu) } EXPORT_SYMBOL_GPL(ring_buffer_size); +static void rb_clear_buffer_page(struct buffer_page *page) +{ + local_set(&page->write, 0); + local_set(&page->entries, 0); + rb_init_page(page->page); + page->read = 0; +} + static void rb_reset_cpu(struct ring_buffer_per_cpu *cpu_buffer) { + struct buffer_page *page; + rb_head_page_deactivate(cpu_buffer); cpu_buffer->head_page = list_entry(cpu_buffer->pages, struct buffer_page, list); - local_set(&cpu_buffer->head_page->write, 0); - local_set(&cpu_buffer->head_page->entries, 0); - local_set(&cpu_buffer->head_page->page->commit, 0); - - cpu_buffer->head_page->read = 0; + rb_clear_buffer_page(cpu_buffer->head_page); + list_for_each_entry(page, cpu_buffer->pages, list) { + rb_clear_buffer_page(page); + } cpu_buffer->tail_page = cpu_buffer->head_page; cpu_buffer->commit_page = cpu_buffer->head_page; INIT_LIST_HEAD(&cpu_buffer->reader_page->list); INIT_LIST_HEAD(&cpu_buffer->new_pages); - local_set(&cpu_buffer->reader_page->write, 0); - local_set(&cpu_buffer->reader_page->entries, 0); - local_set(&cpu_buffer->reader_page->page->commit, 0); - cpu_buffer->reader_page->read = 0; + rb_clear_buffer_page(cpu_buffer->reader_page); local_set(&cpu_buffer->entries_bytes, 0); local_set(&cpu_buffer->overrun, 0); @@ -4433,6 +4457,7 @@ rb_reset_cpu(struct ring_buffer_per_cpu *cpu_buffer) cpu_buffer->last_overrun = 0; rb_head_page_activate(cpu_buffer); + cpu_buffer->pages_removed = 0; } /** @@ -4685,11 +4710,16 @@ EXPORT_SYMBOL_GPL(ring_buffer_alloc_read_page); */ void ring_buffer_free_read_page(struct ring_buffer *buffer, int cpu, void *data) { - struct ring_buffer_per_cpu *cpu_buffer = buffer->buffers[cpu]; + struct ring_buffer_per_cpu *cpu_buffer; struct buffer_data_page *bpage = data; struct page *page = virt_to_page(bpage); unsigned long flags; + if (!buffer || !buffer->buffers || !buffer->buffers[cpu]) + return; + + cpu_buffer = buffer->buffers[cpu]; + /* If the page is still in use someplace else, we can't reuse it */ if (page_ref_count(page) > 1) goto out; diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index 3861e7d1e25eae1a8c786a8eb7fc53ba07122938..a36e9f4dae3cd80c7f70b62d24c4e50e698858df 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -3283,8 +3283,15 @@ static void *s_start(struct seq_file *m, loff_t *pos) * will point to the same string as current_trace->name. */ mutex_lock(&trace_types_lock); - if (unlikely(tr->current_trace && iter->trace->name != tr->current_trace->name)) + if (unlikely(tr->current_trace && iter->trace->name != tr->current_trace->name)) { + /* Close iter->trace before switching to the new current tracer */ + if (iter->trace->close) + iter->trace->close(iter); *iter->trace = *tr->current_trace; + /* Reopen the new current tracer */ + if (iter->trace->open) + iter->trace->open(iter); + } mutex_unlock(&trace_types_lock); #ifdef CONFIG_TRACER_MAX_TRACE @@ -7118,14 +7125,23 @@ static ssize_t tracing_read_dyn_info(struct file *filp, char __user *ubuf, size_t cnt, loff_t *ppos) { - unsigned long *p = filp->private_data; - char buf[64]; /* Not too big for a shallow stack */ + ssize_t ret; + char *buf; int r; - r = scnprintf(buf, 63, "%ld", *p); - buf[r++] = '\n'; + /* 256 should be plenty to hold the amount needed */ + buf = kmalloc(256, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + r = scnprintf(buf, 256, "%ld pages:%ld groups: %ld\n", + ftrace_update_tot_cnt, + ftrace_number_of_pages, + ftrace_number_of_groups); - return simple_read_from_buffer(ubuf, cnt, ppos, buf, r); + ret = simple_read_from_buffer(ubuf, cnt, ppos, buf, r); + kfree(buf); + return ret; } static const struct file_operations tracing_dyn_info_fops = { @@ -8257,7 +8273,7 @@ static __init int tracer_init_tracefs(void) #ifdef CONFIG_DYNAMIC_FTRACE trace_create_file("dyn_ftrace_total_info", 0444, d_tracer, - &ftrace_update_tot_cnt, &tracing_dyn_info_fops); + NULL, &tracing_dyn_info_fops); #endif create_trace_instances(d_tracer); diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h index 0daab7c69fde1b1ea2fbc103b35f1cfba10df890..fb94a1c667f30d3eb1bbdf0b4581e59ef9a7e86e 100644 --- a/kernel/trace/trace.h +++ b/kernel/trace/trace.h @@ -748,6 +748,8 @@ extern void trace_event_follow_fork(struct trace_array *tr, bool enable); #ifdef CONFIG_DYNAMIC_FTRACE extern unsigned long ftrace_update_tot_cnt; +extern unsigned long ftrace_number_of_pages; +extern unsigned long ftrace_number_of_groups; void ftrace_init_trace_array(struct trace_array *tr); #else static inline void ftrace_init_trace_array(struct trace_array *tr) { } diff --git a/kernel/trace/trace_events.c b/kernel/trace/trace_events.c index ca91da10ce96770f48f16690a48d2a2d19907038..67da4a589ff6796ff11aa25ad0db256bc335f34b 100644 --- a/kernel/trace/trace_events.c +++ b/kernel/trace/trace_events.c @@ -372,7 +372,6 @@ static int __ftrace_event_enable_disable(struct trace_event_file *file, { struct trace_event_call *call = file->event_call; struct trace_array *tr = file->tr; - unsigned long file_flags = file->flags; int ret = 0; int disable; @@ -396,6 +395,8 @@ static int __ftrace_event_enable_disable(struct trace_event_file *file, break; disable = file->flags & EVENT_FILE_FL_SOFT_DISABLED; clear_bit(EVENT_FILE_FL_SOFT_MODE_BIT, &file->flags); + /* Disable use of trace_buffered_event */ + trace_buffered_event_disable(); } else disable = !(file->flags & EVENT_FILE_FL_SOFT_MODE); @@ -434,6 +435,8 @@ static int __ftrace_event_enable_disable(struct trace_event_file *file, if (atomic_inc_return(&file->sm_ref) > 1) break; set_bit(EVENT_FILE_FL_SOFT_MODE_BIT, &file->flags); + /* Enable use of trace_buffered_event */ + trace_buffered_event_enable(); } if (!(file->flags & EVENT_FILE_FL_ENABLED)) { @@ -473,15 +476,6 @@ static int __ftrace_event_enable_disable(struct trace_event_file *file, break; } - /* Enable or disable use of trace_buffered_event */ - if ((file_flags & EVENT_FILE_FL_SOFT_DISABLED) != - (file->flags & EVENT_FILE_FL_SOFT_DISABLED)) { - if (file->flags & EVENT_FILE_FL_SOFT_DISABLED) - trace_buffered_event_enable(); - else - trace_buffered_event_disable(); - } - return ret; } @@ -2248,6 +2242,7 @@ void trace_event_eval_update(struct trace_eval_map **map, int len) update_event_printk(call, map[i]); } } + cond_resched(); } up_write(&trace_event_sem); } diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c index ee163594a51521650785d5d6a48de857704d8434..4e8c3978c08835bdc47a671b089cf5e8fc5c70e9 100644 --- a/kernel/trace/trace_events_hist.c +++ b/kernel/trace/trace_events_hist.c @@ -1764,6 +1764,9 @@ static const char *hist_field_name(struct hist_field *field, { const char *field_name = ""; + if (WARN_ON_ONCE(!field)) + return field_name; + if (level > 1) return field_name; @@ -5784,13 +5787,16 @@ static int event_hist_trigger_func(struct event_command *cmd_ops, if (get_named_trigger_data(trigger_data)) goto enable; - if (has_hist_vars(hist_data)) - save_hist_vars(hist_data); - ret = create_actions(hist_data, file); if (ret) goto out_unreg; + if (has_hist_vars(hist_data) || hist_data->n_var_refs) { + ret = save_hist_vars(hist_data); + if (ret) + goto out_unreg; + } + ret = tracing_map_init(hist_data->map); if (ret) goto out_unreg; diff --git a/kernel/trace/trace_irqsoff.c b/kernel/trace/trace_irqsoff.c index c606f6a07bd0c3996c1c50b09df6d6966dc5c533..e4d9a0a76ff82fa895d1ac0dab54998d3cfed45c 100644 --- a/kernel/trace/trace_irqsoff.c +++ b/kernel/trace/trace_irqsoff.c @@ -225,7 +225,8 @@ static void irqsoff_trace_open(struct trace_iterator *iter) { if (is_graph(iter->tr)) graph_trace_open(iter); - + else + iter->private = NULL; } static void irqsoff_trace_close(struct trace_iterator *iter) diff --git a/kernel/trace/trace_sched_wakeup.c b/kernel/trace/trace_sched_wakeup.c index 11f4dbd9526b69c0600c292e374db725795dc1e6..8041bd5e42624268dc36cd4514ebb080da4b92ac 100644 --- a/kernel/trace/trace_sched_wakeup.c +++ b/kernel/trace/trace_sched_wakeup.c @@ -287,6 +287,8 @@ static void wakeup_trace_open(struct trace_iterator *iter) { if (is_graph(iter->tr)) graph_trace_open(iter); + else + iter->private = NULL; } static void wakeup_trace_close(struct trace_iterator *iter) diff --git a/kernel/trace/trace_uprobe.c b/kernel/trace/trace_uprobe.c index 1df8e3859e922ae20f442a54d88e75bc6faa4f5b..19777fdc1fe11a2ee4dbc24777b0bb04675fde87 100644 --- a/kernel/trace/trace_uprobe.c +++ b/kernel/trace/trace_uprobe.c @@ -1159,7 +1159,7 @@ static void uretprobe_perf_func(struct trace_uprobe *tu, unsigned long func, int bpf_get_uprobe_info(const struct perf_event *event, u32 *fd_type, const char **filename, u64 *probe_offset, - bool perf_type_tracepoint) + u64 *probe_addr, bool perf_type_tracepoint) { const char *pevent = trace_event_name(event->tp_event); const char *group = event->tp_event->class->system; @@ -1176,6 +1176,7 @@ int bpf_get_uprobe_info(const struct perf_event *event, u32 *fd_type, : BPF_FD_TYPE_UPROBE; *filename = tu->filename; *probe_offset = tu->offset; + *probe_addr = 0; return 0; } #endif /* CONFIG_PERF_EVENTS */ diff --git a/kernel/watchdog_hld.c b/kernel/watchdog_hld.c index 71381168dedef4e88382a1849412f554a4cb4a56..f8e460b4a59d54db4b5c5ece0f755e618b95002c 100644 --- a/kernel/watchdog_hld.c +++ b/kernel/watchdog_hld.c @@ -114,14 +114,14 @@ static void watchdog_overflow_callback(struct perf_event *event, /* Ensure the watchdog never gets throttled */ event->hw.interrupts = 0; + if (!watchdog_check_timestamp()) + return; + if (__this_cpu_read(watchdog_nmi_touch) == true) { __this_cpu_write(watchdog_nmi_touch, false); return; } - if (!watchdog_check_timestamp()) - return; - /* check for a hardlockup * This is done by making sure our timer interrupt * is incrementing. The timer interrupt should have diff --git a/kernel/workqueue.c b/kernel/workqueue.c index 4780010ba92c257927b4457eb761da6770635a62..d186897a2ae941ddf54170a63362fa04611f2c37 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -690,12 +690,17 @@ static void clear_work_data(struct work_struct *work) set_work_data(work, WORK_STRUCT_NO_POOL, 0); } +static inline struct pool_workqueue *work_struct_pwq(unsigned long data) +{ + return (struct pool_workqueue *)(data & WORK_STRUCT_WQ_DATA_MASK); +} + static struct pool_workqueue *get_work_pwq(struct work_struct *work) { unsigned long data = atomic_long_read(&work->data); if (data & WORK_STRUCT_PWQ) - return (void *)(data & WORK_STRUCT_WQ_DATA_MASK); + return work_struct_pwq(data); else return NULL; } @@ -723,8 +728,7 @@ static struct worker_pool *get_work_pool(struct work_struct *work) assert_rcu_or_pool_mutex(); if (data & WORK_STRUCT_PWQ) - return ((struct pool_workqueue *) - (data & WORK_STRUCT_WQ_DATA_MASK))->pool; + return work_struct_pwq(data)->pool; pool_id = data >> WORK_OFFQ_POOL_SHIFT; if (pool_id == WORK_OFFQ_POOL_NONE) @@ -745,8 +749,7 @@ static int get_work_pool_id(struct work_struct *work) unsigned long data = atomic_long_read(&work->data); if (data & WORK_STRUCT_PWQ) - return ((struct pool_workqueue *) - (data & WORK_STRUCT_WQ_DATA_MASK))->pool->id; + return work_struct_pwq(data)->pool->id; return data >> WORK_OFFQ_POOL_SHIFT; } @@ -5217,9 +5220,13 @@ static int workqueue_apply_unbound_cpumask(void) list_for_each_entry(wq, &workqueues, list) { if (!(wq->flags & WQ_UNBOUND)) continue; + /* creating multiple pwqs breaks ordering guarantee */ - if (wq->flags & __WQ_ORDERED) - continue; + if (!list_empty(&wq->pwqs)) { + if (wq->flags & __WQ_ORDERED_EXPLICIT) + continue; + wq->flags &= ~__WQ_ORDERED; + } ctx = apply_wqattrs_prepare(wq, wq->unbound_attrs); if (!ctx) { diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index 112272cb5df2a367d2400a5eb3f8177d19b12525..0e020e6a5ab957fac262ce96b4cc3d607b5f6a42 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -2124,6 +2124,16 @@ config PANIC_ON_DATA_CORRUPTION recoverable data corruption scenarios to system-halting panics, for easier detection and debug. +config CC_WERROR + bool "Treat all compile warnings as errors" + default n + help + Select this option to set compiler warnings as errors, + to prevent easily-fixable problems from creeping into + the codebase. + + If unsure, say N. + source "samples/Kconfig" source "lib/Kconfig.kgdb" diff --git a/lib/clz_ctz.c b/lib/clz_ctz.c index 2e11e48446abf1bf078163575e10a33a8028febc..ca0582d33532f599b0f5cbe3458ecf3ffbb3b22a 100644 --- a/lib/clz_ctz.c +++ b/lib/clz_ctz.c @@ -30,36 +30,16 @@ int __weak __clzsi2(int val) } EXPORT_SYMBOL(__clzsi2); -int __weak __clzdi2(long val); -int __weak __ctzdi2(long val); -#if BITS_PER_LONG == 32 - -int __weak __clzdi2(long val) +int __weak __clzdi2(u64 val); +int __weak __clzdi2(u64 val) { - return 32 - fls((int)val); + return 64 - fls64(val); } EXPORT_SYMBOL(__clzdi2); -int __weak __ctzdi2(long val) +int __weak __ctzdi2(u64 val); +int __weak __ctzdi2(u64 val) { - return __ffs((u32)val); + return __ffs64(val); } EXPORT_SYMBOL(__ctzdi2); - -#elif BITS_PER_LONG == 64 - -int __weak __clzdi2(long val) -{ - return 64 - fls64((u64)val); -} -EXPORT_SYMBOL(__clzdi2); - -int __weak __ctzdi2(long val) -{ - return __ffs64((u64)val); -} -EXPORT_SYMBOL(__ctzdi2); - -#else -#error BITS_PER_LONG not 32 or 64 -#endif diff --git a/lib/cpu_rmap.c b/lib/cpu_rmap.c index f610b2a10b3eda40c8e04f30f3779556502e9fe6..a0de1b2579f711917671765b7f7ae37a47a11b7c 100644 --- a/lib/cpu_rmap.c +++ b/lib/cpu_rmap.c @@ -235,7 +235,8 @@ void free_irq_cpu_rmap(struct cpu_rmap *rmap) for (index = 0; index < rmap->used; index++) { glue = rmap->obj[index]; - irq_set_affinity_notifier(glue->notify.irq, NULL); + if (glue) + irq_set_affinity_notifier(glue->notify.irq, NULL); } cpu_rmap_put(rmap); @@ -270,6 +271,7 @@ static void irq_cpu_rmap_release(struct kref *ref) struct irq_glue *glue = container_of(ref, struct irq_glue, notify.kref); + glue->rmap->obj[glue->index] = NULL; cpu_rmap_put(glue->rmap); kfree(glue); } @@ -300,6 +302,7 @@ int irq_cpu_rmap_add(struct cpu_rmap *rmap, int irq) rc = irq_set_affinity_notifier(irq, &glue->notify); if (rc) { cpu_rmap_put(glue->rmap); + rmap->obj[glue->index] = NULL; kfree(glue); } return rc; diff --git a/lib/debugobjects.c b/lib/debugobjects.c index 14afeeb7d6ef5b91929702af25f96ef4eeb711ec..62d095fd0c52a64f66b96301fdd3b120ae40345d 100644 --- a/lib/debugobjects.c +++ b/lib/debugobjects.c @@ -25,6 +25,7 @@ #define ODEBUG_POOL_SIZE 1024 #define ODEBUG_POOL_MIN_LEVEL 256 +#define ODEBUG_POOL_PERCPU_SIZE 64 #define ODEBUG_CHUNK_SHIFT PAGE_SHIFT #define ODEBUG_CHUNK_SIZE (1 << ODEBUG_CHUNK_SHIFT) @@ -35,6 +36,17 @@ struct debug_bucket { raw_spinlock_t lock; }; +/* + * Debug object percpu free list + * Access is protected by disabling irq + */ +struct debug_percpu_free { + struct hlist_head free_objs; + int obj_free; +}; + +static DEFINE_PER_CPU(struct debug_percpu_free, percpu_obj_pool); + static struct debug_bucket obj_hash[ODEBUG_HASH_SIZE]; static struct debug_obj obj_static_pool[ODEBUG_POOL_SIZE] __initdata; @@ -44,13 +56,19 @@ static DEFINE_RAW_SPINLOCK(pool_lock); static HLIST_HEAD(obj_pool); static HLIST_HEAD(obj_to_free); +/* + * Because of the presence of percpu free pools, obj_pool_free will + * under-count those in the percpu free pools. Similarly, obj_pool_used + * will over-count those in the percpu free pools. Adjustments will be + * made at debug_stats_show(). Both obj_pool_min_free and obj_pool_max_used + * can be off. + */ static int obj_pool_min_free = ODEBUG_POOL_SIZE; static int obj_pool_free = ODEBUG_POOL_SIZE; static int obj_pool_used; static int obj_pool_max_used; /* The number of objs on the global free list */ static int obj_nr_tofree; -static struct kmem_cache *obj_cache; static int debug_objects_maxchain __read_mostly; static int __maybe_unused debug_objects_maxchecked __read_mostly; @@ -63,6 +81,7 @@ static int debug_objects_pool_size __read_mostly static int debug_objects_pool_min_level __read_mostly = ODEBUG_POOL_MIN_LEVEL; static struct debug_obj_descr *descr_test __read_mostly; +static struct kmem_cache *obj_cache __read_mostly; /* * Track numbers of kmem_cache_alloc()/free() calls done. @@ -163,26 +182,38 @@ static struct debug_obj *lookup_object(void *addr, struct debug_bucket *b) } /* - * Allocate a new object. If the pool is empty, switch off the debugger. - * Must be called with interrupts disabled. + * Allocate a new object from the hlist */ -static struct debug_obj * -alloc_object(void *addr, struct debug_bucket *b, struct debug_obj_descr *descr) +static struct debug_obj *__alloc_object(struct hlist_head *list) { struct debug_obj *obj = NULL; - raw_spin_lock(&pool_lock); - if (obj_pool.first) { - obj = hlist_entry(obj_pool.first, typeof(*obj), node); - - obj->object = addr; - obj->descr = descr; - obj->state = ODEBUG_STATE_NONE; - obj->astate = 0; + if (list->first) { + obj = hlist_entry(list->first, typeof(*obj), node); hlist_del(&obj->node); + } - hlist_add_head(&obj->node, &b->list); + return obj; +} + +static struct debug_obj * +alloc_object(void *addr, struct debug_bucket *b, struct debug_obj_descr *descr) +{ + struct debug_percpu_free *percpu_pool; + struct debug_obj *obj; + + if (likely(obj_cache)) { + percpu_pool = this_cpu_ptr(&percpu_obj_pool); + obj = __alloc_object(&percpu_pool->free_objs); + if (obj) { + percpu_pool->obj_free--; + goto init_obj; + } + } + raw_spin_lock(&pool_lock); + obj = __alloc_object(&obj_pool); + if (obj) { obj_pool_used++; if (obj_pool_used > obj_pool_max_used) obj_pool_max_used = obj_pool_used; @@ -193,6 +224,14 @@ alloc_object(void *addr, struct debug_bucket *b, struct debug_obj_descr *descr) } raw_spin_unlock(&pool_lock); +init_obj: + if (obj) { + obj->object = addr; + obj->descr = descr; + obj->state = ODEBUG_STATE_NONE; + obj->astate = 0; + hlist_add_head(&obj->node, &b->list); + } return obj; } @@ -247,8 +286,21 @@ static bool __free_object(struct debug_obj *obj) { unsigned long flags; bool work; + struct debug_percpu_free *percpu_pool; - raw_spin_lock_irqsave(&pool_lock, flags); + local_irq_save(flags); + /* + * Try to free it into the percpu pool first. + */ + percpu_pool = this_cpu_ptr(&percpu_obj_pool); + if (obj_cache && percpu_pool->obj_free < ODEBUG_POOL_PERCPU_SIZE) { + hlist_add_head(&obj->node, &percpu_pool->free_objs); + percpu_pool->obj_free++; + local_irq_restore(flags); + return false; + } + + raw_spin_lock(&pool_lock); work = (obj_pool_free > debug_objects_pool_size) && obj_cache; obj_pool_used--; @@ -259,7 +311,8 @@ static bool __free_object(struct debug_obj *obj) obj_pool_free++; hlist_add_head(&obj->node, &obj_pool); } - raw_spin_unlock_irqrestore(&pool_lock, flags); + raw_spin_unlock(&pool_lock); + local_irq_restore(flags); return work; } @@ -318,6 +371,15 @@ static void debug_print_object(struct debug_obj *obj, char *msg) struct debug_obj_descr *descr = obj->descr; static int limit; + /* + * Don't report if lookup_object_or_alloc() by the current thread + * failed because lookup_object_or_alloc()/debug_objects_oom() by a + * concurrent thread turned off debug_objects_enabled and cleared + * the hash buckets. + */ + if (!debug_objects_enabled) + return; + if (limit < 5 && descr != descr_test) { void *hint = descr->debug_hint ? descr->debug_hint(obj->object) : NULL; @@ -368,6 +430,55 @@ static void debug_object_is_on_stack(void *addr, int onstack) WARN_ON(1); } +static struct debug_obj *lookup_object_or_alloc(void *addr, struct debug_bucket *b, + struct debug_obj_descr *descr, + bool onstack, bool alloc_ifstatic) +{ + struct debug_obj *obj = lookup_object(addr, b); + enum debug_obj_state state = ODEBUG_STATE_NONE; + + if (likely(obj)) + return obj; + + /* + * debug_object_init() unconditionally allocates untracked + * objects. It does not matter whether it is a static object or + * not. + * + * debug_object_assert_init() and debug_object_activate() allow + * allocation only if the descriptor callback confirms that the + * object is static and considered initialized. For non-static + * objects the allocation needs to be done from the fixup callback. + */ + if (unlikely(alloc_ifstatic)) { + if (!descr->is_static_object || !descr->is_static_object(addr)) + return ERR_PTR(-ENOENT); + /* Statically allocated objects are considered initialized */ + state = ODEBUG_STATE_INIT; + } + + obj = alloc_object(addr, b, descr); + if (likely(obj)) { + obj->state = state; + debug_object_is_on_stack(addr, onstack); + return obj; + } + + /* Out of memory. Do the cleanup outside of the locked region */ + debug_objects_enabled = 0; + return NULL; +} + +static void debug_objects_fill_pool(void) +{ + /* + * On RT enabled kernels the pool refill must happen in preemptible + * context: + */ + if (!IS_ENABLED(CONFIG_PREEMPT_RT) || preemptible()) + fill_pool(); +} + static void __debug_object_init(void *addr, struct debug_obj_descr *descr, int onstack) { @@ -376,22 +487,17 @@ __debug_object_init(void *addr, struct debug_obj_descr *descr, int onstack) struct debug_obj *obj; unsigned long flags; - fill_pool(); + debug_objects_fill_pool(); db = get_bucket((unsigned long) addr); raw_spin_lock_irqsave(&db->lock, flags); - obj = lookup_object(addr, db); - if (!obj) { - obj = alloc_object(addr, db, descr); - if (!obj) { - debug_objects_enabled = 0; - raw_spin_unlock_irqrestore(&db->lock, flags); - debug_objects_oom(); - return; - } - debug_object_is_on_stack(addr, onstack); + obj = lookup_object_or_alloc(addr, db, descr, onstack, false); + if (unlikely(!obj)) { + raw_spin_unlock_irqrestore(&db->lock, flags); + debug_objects_oom(); + return; } switch (obj->state) { @@ -402,15 +508,16 @@ __debug_object_init(void *addr, struct debug_obj_descr *descr, int onstack) break; case ODEBUG_STATE_ACTIVE: - debug_print_object(obj, "init"); state = obj->state; raw_spin_unlock_irqrestore(&db->lock, flags); + debug_print_object(obj, "init"); debug_object_fixup(descr->fixup_init, addr, state); return; case ODEBUG_STATE_DESTROYED: + raw_spin_unlock_irqrestore(&db->lock, flags); debug_print_object(obj, "init"); - break; + return; default: break; } @@ -455,24 +562,26 @@ EXPORT_SYMBOL_GPL(debug_object_init_on_stack); */ int debug_object_activate(void *addr, struct debug_obj_descr *descr) { + struct debug_obj o = { .object = addr, .state = ODEBUG_STATE_NOTAVAILABLE, .descr = descr }; enum debug_obj_state state; struct debug_bucket *db; struct debug_obj *obj; unsigned long flags; int ret; - struct debug_obj o = { .object = addr, - .state = ODEBUG_STATE_NOTAVAILABLE, - .descr = descr }; if (!debug_objects_enabled) return 0; + debug_objects_fill_pool(); + db = get_bucket((unsigned long) addr); raw_spin_lock_irqsave(&db->lock, flags); - obj = lookup_object(addr, db); - if (obj) { + obj = lookup_object_or_alloc(addr, db, descr, false, true); + if (likely(!IS_ERR_OR_NULL(obj))) { + bool print_object = false; + switch (obj->state) { case ODEBUG_STATE_INIT: case ODEBUG_STATE_INACTIVE: @@ -481,14 +590,14 @@ int debug_object_activate(void *addr, struct debug_obj_descr *descr) break; case ODEBUG_STATE_ACTIVE: - debug_print_object(obj, "activate"); state = obj->state; raw_spin_unlock_irqrestore(&db->lock, flags); + debug_print_object(obj, "activate"); ret = debug_object_fixup(descr->fixup_activate, addr, state); return ret ? 0 : -EINVAL; case ODEBUG_STATE_DESTROYED: - debug_print_object(obj, "activate"); + print_object = true; ret = -EINVAL; break; default: @@ -496,28 +605,23 @@ int debug_object_activate(void *addr, struct debug_obj_descr *descr) break; } raw_spin_unlock_irqrestore(&db->lock, flags); + if (print_object) + debug_print_object(obj, "activate"); return ret; } raw_spin_unlock_irqrestore(&db->lock, flags); - /* - * We are here when a static object is activated. We - * let the type specific code confirm whether this is - * true or not. if true, we just make sure that the - * static object is tracked in the object tracker. If - * not, this must be a bug, so we try to fix it up. - */ - if (descr->is_static_object && descr->is_static_object(addr)) { - /* track this static object */ - debug_object_init(addr, descr); - debug_object_activate(addr, descr); - } else { - debug_print_object(&o, "activate"); - ret = debug_object_fixup(descr->fixup_activate, addr, - ODEBUG_STATE_NOTAVAILABLE); - return ret ? 0 : -EINVAL; + + /* If NULL the allocation has hit OOM */ + if (!obj) { + debug_objects_oom(); + return 0; } - return 0; + + /* Object is neither static nor tracked. It's not initialized */ + debug_print_object(&o, "activate"); + ret = debug_object_fixup(descr->fixup_activate, addr, ODEBUG_STATE_NOTAVAILABLE); + return ret ? 0 : -EINVAL; } EXPORT_SYMBOL_GPL(debug_object_activate); @@ -531,6 +635,7 @@ void debug_object_deactivate(void *addr, struct debug_obj_descr *descr) struct debug_bucket *db; struct debug_obj *obj; unsigned long flags; + bool print_object = false; if (!debug_objects_enabled) return; @@ -548,24 +653,27 @@ void debug_object_deactivate(void *addr, struct debug_obj_descr *descr) if (!obj->astate) obj->state = ODEBUG_STATE_INACTIVE; else - debug_print_object(obj, "deactivate"); + print_object = true; break; case ODEBUG_STATE_DESTROYED: - debug_print_object(obj, "deactivate"); + print_object = true; break; default: break; } - } else { + } + + raw_spin_unlock_irqrestore(&db->lock, flags); + if (!obj) { struct debug_obj o = { .object = addr, .state = ODEBUG_STATE_NOTAVAILABLE, .descr = descr }; debug_print_object(&o, "deactivate"); + } else if (print_object) { + debug_print_object(obj, "deactivate"); } - - raw_spin_unlock_irqrestore(&db->lock, flags); } EXPORT_SYMBOL_GPL(debug_object_deactivate); @@ -580,6 +688,7 @@ void debug_object_destroy(void *addr, struct debug_obj_descr *descr) struct debug_bucket *db; struct debug_obj *obj; unsigned long flags; + bool print_object = false; if (!debug_objects_enabled) return; @@ -599,20 +708,22 @@ void debug_object_destroy(void *addr, struct debug_obj_descr *descr) obj->state = ODEBUG_STATE_DESTROYED; break; case ODEBUG_STATE_ACTIVE: - debug_print_object(obj, "destroy"); state = obj->state; raw_spin_unlock_irqrestore(&db->lock, flags); + debug_print_object(obj, "destroy"); debug_object_fixup(descr->fixup_destroy, addr, state); return; case ODEBUG_STATE_DESTROYED: - debug_print_object(obj, "destroy"); + print_object = true; break; default: break; } out_unlock: raw_spin_unlock_irqrestore(&db->lock, flags); + if (print_object) + debug_print_object(obj, "destroy"); } EXPORT_SYMBOL_GPL(debug_object_destroy); @@ -641,9 +752,9 @@ void debug_object_free(void *addr, struct debug_obj_descr *descr) switch (obj->state) { case ODEBUG_STATE_ACTIVE: - debug_print_object(obj, "free"); state = obj->state; raw_spin_unlock_irqrestore(&db->lock, flags); + debug_print_object(obj, "free"); debug_object_fixup(descr->fixup_free, addr, state); return; default: @@ -664,6 +775,7 @@ EXPORT_SYMBOL_GPL(debug_object_free); */ void debug_object_assert_init(void *addr, struct debug_obj_descr *descr) { + struct debug_obj o = { .object = addr, .state = ODEBUG_STATE_NOTAVAILABLE, .descr = descr }; struct debug_bucket *db; struct debug_obj *obj; unsigned long flags; @@ -671,34 +783,25 @@ void debug_object_assert_init(void *addr, struct debug_obj_descr *descr) if (!debug_objects_enabled) return; + debug_objects_fill_pool(); + db = get_bucket((unsigned long) addr); raw_spin_lock_irqsave(&db->lock, flags); + obj = lookup_object_or_alloc(addr, db, descr, false, true); + raw_spin_unlock_irqrestore(&db->lock, flags); + if (likely(!IS_ERR_OR_NULL(obj))) + return; - obj = lookup_object(addr, db); + /* If NULL the allocation has hit OOM */ if (!obj) { - struct debug_obj o = { .object = addr, - .state = ODEBUG_STATE_NOTAVAILABLE, - .descr = descr }; - - raw_spin_unlock_irqrestore(&db->lock, flags); - /* - * Maybe the object is static, and we let the type specific - * code confirm. Track this static object if true, else invoke - * fixup. - */ - if (descr->is_static_object && descr->is_static_object(addr)) { - /* Track this static object */ - debug_object_init(addr, descr); - } else { - debug_print_object(&o, "assert_init"); - debug_object_fixup(descr->fixup_assert_init, addr, - ODEBUG_STATE_NOTAVAILABLE); - } + debug_objects_oom(); return; } - raw_spin_unlock_irqrestore(&db->lock, flags); + /* Object is neither tracked nor static. It's not initialized. */ + debug_print_object(&o, "assert_init"); + debug_object_fixup(descr->fixup_assert_init, addr, ODEBUG_STATE_NOTAVAILABLE); } EXPORT_SYMBOL_GPL(debug_object_assert_init); @@ -716,6 +819,7 @@ debug_object_active_state(void *addr, struct debug_obj_descr *descr, struct debug_bucket *db; struct debug_obj *obj; unsigned long flags; + bool print_object = false; if (!debug_objects_enabled) return; @@ -731,22 +835,25 @@ debug_object_active_state(void *addr, struct debug_obj_descr *descr, if (obj->astate == expect) obj->astate = next; else - debug_print_object(obj, "active_state"); + print_object = true; break; default: - debug_print_object(obj, "active_state"); + print_object = true; break; } - } else { + } + + raw_spin_unlock_irqrestore(&db->lock, flags); + if (!obj) { struct debug_obj o = { .object = addr, .state = ODEBUG_STATE_NOTAVAILABLE, .descr = descr }; debug_print_object(&o, "active_state"); + } else if (print_object) { + debug_print_object(obj, "active_state"); } - - raw_spin_unlock_irqrestore(&db->lock, flags); } EXPORT_SYMBOL_GPL(debug_object_active_state); @@ -782,10 +889,10 @@ static void __debug_check_no_obj_freed(const void *address, unsigned long size) switch (obj->state) { case ODEBUG_STATE_ACTIVE: - debug_print_object(obj, "free"); descr = obj->descr; state = obj->state; raw_spin_unlock_irqrestore(&db->lock, flags); + debug_print_object(obj, "free"); debug_object_fixup(descr->fixup_free, (void *) oaddr, state); goto repeat; @@ -822,13 +929,19 @@ void debug_check_no_obj_freed(const void *address, unsigned long size) static int debug_stats_show(struct seq_file *m, void *v) { + int cpu, obj_percpu_free = 0; + + for_each_possible_cpu(cpu) + obj_percpu_free += per_cpu(percpu_obj_pool.obj_free, cpu); + seq_printf(m, "max_chain :%d\n", debug_objects_maxchain); seq_printf(m, "max_checked :%d\n", debug_objects_maxchecked); seq_printf(m, "warnings :%d\n", debug_objects_warnings); seq_printf(m, "fixups :%d\n", debug_objects_fixups); - seq_printf(m, "pool_free :%d\n", obj_pool_free); + seq_printf(m, "pool_free :%d\n", obj_pool_free + obj_percpu_free); + seq_printf(m, "pool_pcp_free :%d\n", obj_percpu_free); seq_printf(m, "pool_min_free :%d\n", obj_pool_min_free); - seq_printf(m, "pool_used :%d\n", obj_pool_used); + seq_printf(m, "pool_used :%d\n", obj_pool_used - obj_percpu_free); seq_printf(m, "pool_max_used :%d\n", obj_pool_max_used); seq_printf(m, "on_free_list :%d\n", obj_nr_tofree); seq_printf(m, "objs_allocated:%d\n", debug_objects_allocated); @@ -1177,9 +1290,20 @@ static int __init debug_objects_replace_static_objects(void) */ void __init debug_objects_mem_init(void) { + int cpu; + if (!debug_objects_enabled) return; + /* + * Initialize the percpu object pools + * + * Initialization is not strictly necessary, but was done for + * completeness. + */ + for_each_possible_cpu(cpu) + INIT_HLIST_HEAD(&per_cpu(percpu_obj_pool.free_objs, cpu)); + obj_cache = kmem_cache_create("debug_objects_cache", sizeof (struct debug_obj), 0, SLAB_DEBUG_OBJECTS | SLAB_NOLEAKTRACE, @@ -1191,11 +1315,4 @@ void __init debug_objects_mem_init(void) pr_warn("out of memory.\n"); } else debug_objects_selftest(); - - /* - * Increase the thresholds for allocating and freeing objects - * according to the number of possible CPUs available in the system. - */ - debug_objects_pool_size += num_possible_cpus() * 32; - debug_objects_pool_min_level += num_possible_cpus() * 4; } diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c index 75353bdbace085345a53737dfc9283b5f4b1bcc5..dca8309d3e36a866eb223c6abc753e9527d5ac3d 100644 --- a/lib/dynamic_debug.c +++ b/lib/dynamic_debug.c @@ -988,7 +988,7 @@ static int __init dynamic_debug_init(void) int n = 0, entries = 0, modct = 0; int verbose_bytes = 0; - if (__start___verbose == __stop___verbose) { + if (&__start___verbose == &__stop___verbose) { pr_warn("_ddebug table is empty in a CONFIG_DYNAMIC_DEBUG build\n"); return 1; } diff --git a/lib/idr.c b/lib/idr.c index 82c24a417dc65d599865e01ea16c4e2735c256b5..432a985bf772707f0ab4a4354b6a56d9b216cd17 100644 --- a/lib/idr.c +++ b/lib/idr.c @@ -103,7 +103,7 @@ EXPORT_SYMBOL_GPL(idr_alloc); * @end: The maximum ID (exclusive). * @gfp: Memory allocation flags. * - * Allocates an unused ID in the range specified by @nextid and @end. If + * Allocates an unused ID in the range specified by @start and @end. If * @end is <= 0, it is treated as one larger than %INT_MAX. This allows * callers to use @start + N as @end as long as N is within integer range. * The search for an unused ID will start at the last ID allocated and will diff --git a/lib/kobject.c b/lib/kobject.c index 97d86dc17c42bf09c94dcb5149ff669a7a6d49db..a45eb05c79fe2de4780477c50b0a680787d1057b 100644 --- a/lib/kobject.c +++ b/lib/kobject.c @@ -135,7 +135,7 @@ static int get_kobj_path_length(struct kobject *kobj) return length; } -static void fill_kobj_path(struct kobject *kobj, char *path, int length) +static int fill_kobj_path(struct kobject *kobj, char *path, int length) { struct kobject *parent; @@ -144,12 +144,16 @@ static void fill_kobj_path(struct kobject *kobj, char *path, int length) int cur = strlen(kobject_name(parent)); /* back up enough to print this name with '/' */ length -= cur; + if (length <= 0) + return -EINVAL; memcpy(path + length, kobject_name(parent), cur); *(path + --length) = '/'; } pr_debug("kobject: '%s' (%p): %s: path = '%s'\n", kobject_name(kobj), kobj, __func__, path); + + return 0; } /** @@ -165,13 +169,17 @@ char *kobject_get_path(struct kobject *kobj, gfp_t gfp_mask) char *path; int len; +retry: len = get_kobj_path_length(kobj); if (len == 0) return NULL; path = kzalloc(len, gfp_mask); if (!path) return NULL; - fill_kobj_path(kobj, path, len); + if (fill_kobj_path(kobj, path, len)) { + kfree(path); + goto retry; + } return path; } @@ -829,6 +837,11 @@ int kset_register(struct kset *k) if (!k) return -EINVAL; + if (!k->kobj.ktype) { + pr_err("must have a ktype to be initialized properly!\n"); + return -EINVAL; + } + kset_init(k); err = kobject_add_internal(&k->kobj); if (err) diff --git a/lib/mpi/longlong.h b/lib/mpi/longlong.h index 6c5229f98c9eb409370cd5d58b7afae8aa4cabf1..cac4e5aee7395c328a00b24796ed4747b39bae17 100644 --- a/lib/mpi/longlong.h +++ b/lib/mpi/longlong.h @@ -639,30 +639,12 @@ do { \ ************** MIPS ***************** ***************************************/ #if defined(__mips__) && W_TYPE_SIZE == 32 -#if (__GNUC__ >= 5) || (__GNUC__ >= 4 && __GNUC_MINOR__ >= 4) #define umul_ppmm(w1, w0, u, v) \ do { \ UDItype __ll = (UDItype)(u) * (v); \ w1 = __ll >> 32; \ w0 = __ll; \ } while (0) -#elif __GNUC__ > 2 || __GNUC_MINOR__ >= 7 -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("multu %2,%3" \ - : "=l" ((USItype)(w0)), \ - "=h" ((USItype)(w1)) \ - : "d" ((USItype)(u)), \ - "d" ((USItype)(v))) -#else -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("multu %2,%3\n" \ - "mflo %0\n" \ - "mfhi %1" \ - : "=d" ((USItype)(w0)), \ - "=d" ((USItype)(w1)) \ - : "d" ((USItype)(u)), \ - "d" ((USItype)(v))) -#endif #define UMUL_TIME 10 #define UDIV_TIME 100 #endif /* __mips__ */ @@ -687,7 +669,7 @@ do { \ : "d" ((UDItype)(u)), \ "d" ((UDItype)(v))); \ } while (0) -#elif (__GNUC__ >= 5) || (__GNUC__ >= 4 && __GNUC_MINOR__ >= 4) +#else #define umul_ppmm(w1, w0, u, v) \ do { \ typedef unsigned int __ll_UTItype __attribute__((mode(TI))); \ @@ -695,22 +677,6 @@ do { \ w1 = __ll >> 64; \ w0 = __ll; \ } while (0) -#elif __GNUC__ > 2 || __GNUC_MINOR__ >= 7 -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("dmultu %2,%3" \ - : "=l" ((UDItype)(w0)), \ - "=h" ((UDItype)(w1)) \ - : "d" ((UDItype)(u)), \ - "d" ((UDItype)(v))) -#else -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("dmultu %2,%3\n" \ - "mflo %0\n" \ - "mfhi %1" \ - : "=d" ((UDItype)(w0)), \ - "=d" ((UDItype)(w1)) \ - : "d" ((UDItype)(u)), \ - "d" ((UDItype)(v))) #endif #define UMUL_TIME 20 #define UDIV_TIME 140 diff --git a/lib/mpi/mpi-cmp.c b/lib/mpi/mpi-cmp.c index d25e9e96c310fc8aeeaff05213ac74b9f6280a96..ceaebe181cd7092f8918be6d7a8a0123fa4602ec 100644 --- a/lib/mpi/mpi-cmp.c +++ b/lib/mpi/mpi-cmp.c @@ -25,8 +25,12 @@ int mpi_cmp_ui(MPI u, unsigned long v) mpi_limb_t limb = v; mpi_normalize(u); - if (!u->nlimbs && !limb) - return 0; + if (u->nlimbs == 0) { + if (v == 0) + return 0; + else + return -1; + } if (u->sign) return -1; if (u->nlimbs > 1) diff --git a/lib/mpi/mpicoder.c b/lib/mpi/mpicoder.c index eead4b339466854f51db30a17f17ee0472ebe6d3..4f73db248009e8b867b413ba42bb6013c895c569 100644 --- a/lib/mpi/mpicoder.c +++ b/lib/mpi/mpicoder.c @@ -397,7 +397,8 @@ MPI mpi_read_raw_from_sgl(struct scatterlist *sgl, unsigned int nbytes) while (sg_miter_next(&miter)) { buff = miter.addr; - len = miter.length; + len = min_t(unsigned, miter.length, nbytes); + nbytes -= len; for (x = 0; x < len; x++) { a <<= 8; diff --git a/lib/radix-tree.c b/lib/radix-tree.c index e5cab5c4e383097436018a728e9ac78a6ad721ce..8d29fa5b269571d17d86ca29e97e0834ec757cef 100644 --- a/lib/radix-tree.c +++ b/lib/radix-tree.c @@ -1498,7 +1498,7 @@ void *radix_tree_tag_clear(struct radix_tree_root *root, { struct radix_tree_node *node, *parent; unsigned long maxindex; - int uninitialized_var(offset); + int offset; radix_tree_load_root(root, &node, &maxindex); if (index > maxindex) diff --git a/lib/test_firmware.c b/lib/test_firmware.c index f4cc874021da2e887a5a937058758bc768e74e70..be3baea88b61d2b0226fc9c3a8cdd2c40f4e8e7e 100644 --- a/lib/test_firmware.c +++ b/lib/test_firmware.c @@ -160,7 +160,7 @@ static int __kstrncpy(char **dst, const char *name, size_t count, gfp_t gfp) { *dst = kstrndup(name, count, gfp); if (!*dst) - return -ENOSPC; + return -ENOMEM; return count; } @@ -284,16 +284,26 @@ static ssize_t config_test_show_str(char *dst, return len; } -static int test_dev_config_update_bool(const char *buf, size_t size, - bool *cfg) +static inline int __test_dev_config_update_bool(const char *buf, size_t size, + bool *cfg) { int ret; - mutex_lock(&test_fw_mutex); if (strtobool(buf, cfg) < 0) ret = -EINVAL; else ret = size; + + return ret; +} + +static int test_dev_config_update_bool(const char *buf, size_t size, + bool *cfg) +{ + int ret; + + mutex_lock(&test_fw_mutex); + ret = __test_dev_config_update_bool(buf, size, cfg); mutex_unlock(&test_fw_mutex); return ret; @@ -323,7 +333,7 @@ static ssize_t test_dev_config_show_int(char *buf, int cfg) return snprintf(buf, PAGE_SIZE, "%d\n", val); } -static int test_dev_config_update_u8(const char *buf, size_t size, u8 *cfg) +static inline int __test_dev_config_update_u8(const char *buf, size_t size, u8 *cfg) { int ret; long new; @@ -335,14 +345,23 @@ static int test_dev_config_update_u8(const char *buf, size_t size, u8 *cfg) if (new > U8_MAX) return -EINVAL; - mutex_lock(&test_fw_mutex); *(u8 *)cfg = new; - mutex_unlock(&test_fw_mutex); /* Always return full write size even if we didn't consume all */ return size; } +static int test_dev_config_update_u8(const char *buf, size_t size, u8 *cfg) +{ + int ret; + + mutex_lock(&test_fw_mutex); + ret = __test_dev_config_update_u8(buf, size, cfg); + mutex_unlock(&test_fw_mutex); + + return ret; +} + static ssize_t test_dev_config_show_u8(char *buf, u8 cfg) { u8 val; @@ -375,10 +394,10 @@ static ssize_t config_num_requests_store(struct device *dev, mutex_unlock(&test_fw_mutex); goto out; } - mutex_unlock(&test_fw_mutex); - rc = test_dev_config_update_u8(buf, count, - &test_fw_config->num_requests); + rc = __test_dev_config_update_u8(buf, count, + &test_fw_config->num_requests); + mutex_unlock(&test_fw_mutex); out: return rc; @@ -456,7 +475,7 @@ static ssize_t trigger_request_store(struct device *dev, name = kstrndup(buf, count, GFP_KERNEL); if (!name) - return -ENOSPC; + return -ENOMEM; pr_info("loading '%s'\n", name); @@ -497,7 +516,7 @@ static ssize_t trigger_async_request_store(struct device *dev, name = kstrndup(buf, count, GFP_KERNEL); if (!name) - return -ENOSPC; + return -ENOMEM; pr_info("loading '%s'\n", name); @@ -540,7 +559,7 @@ static ssize_t trigger_custom_fallback_store(struct device *dev, name = kstrndup(buf, count, GFP_KERNEL); if (!name) - return -ENOSPC; + return -ENOMEM; pr_info("loading '%s' using custom fallback mechanism\n", name); @@ -618,6 +637,11 @@ static ssize_t trigger_batched_requests_store(struct device *dev, mutex_lock(&test_fw_mutex); + if (test_fw_config->reqs) { + rc = -EBUSY; + goto out_bail; + } + test_fw_config->reqs = vzalloc(array3_size(sizeof(struct test_batched_req), test_fw_config->num_requests, 2)); @@ -721,6 +745,11 @@ ssize_t trigger_batched_requests_async_store(struct device *dev, mutex_lock(&test_fw_mutex); + if (test_fw_config->reqs) { + rc = -EBUSY; + goto out_bail; + } + test_fw_config->reqs = vzalloc(array3_size(sizeof(struct test_batched_req), test_fw_config->num_requests, 2)); diff --git a/lib/ts_bm.c b/lib/ts_bm.c index 9e66ee4020e9085a5cde0c84bf18516335c691da..5de382e79a45a23c3f7458023bc3406f7f50bb28 100644 --- a/lib/ts_bm.c +++ b/lib/ts_bm.c @@ -64,10 +64,12 @@ static unsigned int bm_find(struct ts_config *conf, struct ts_state *state) struct ts_bm *bm = ts_config_priv(conf); unsigned int i, text_len, consumed = state->offset; const u8 *text; - int shift = bm->patlen - 1, bs; + int bs; const u8 icase = conf->flags & TS_IGNORECASE; for (;;) { + int shift = bm->patlen - 1; + text_len = conf->get_next_block(consumed, &text, conf, state); if (unlikely(text_len == 0)) diff --git a/mm/filemap.c b/mm/filemap.c index 780c9eb178e0917ba199f51ec9320269e1616a21..8b3e4d530361db2469e21b85eb32f012710bcecf 100644 --- a/mm/filemap.c +++ b/mm/filemap.c @@ -2633,7 +2633,9 @@ static struct file *do_async_mmap_readahead(struct vm_fault *vmf, * it in the page cache, and handles the special cases reasonably without * having a lot of duplicated code. * - * vma->vm_mm->mmap_sem must be held on entry (except FAULT_FLAG_SPECULATIVE). + * If FAULT_FLAG_SPECULATIVE is set, this function runs with elevated vma + * refcount and with mmap lock not held. + * Otherwise, vma->vm_mm->mmap_sem must be held on entry. * * If our return value has VM_FAULT_RETRY set, it's because * lock_page_or_retry() returned 0. @@ -2658,6 +2660,52 @@ vm_fault_t filemap_fault(struct vm_fault *vmf) struct page *page; vm_fault_t ret = 0; + if (vmf->flags & FAULT_FLAG_SPECULATIVE) { + page = find_get_page(mapping, offset); + if (unlikely(!page)) + return VM_FAULT_RETRY; + + if (unlikely(PageReadahead(page))) + goto page_put; + + if (!trylock_page(page)) + goto page_put; + + if (unlikely(compound_head(page)->mapping != mapping)) + goto page_unlock; + VM_BUG_ON_PAGE(page_to_pgoff(page) != offset, page); + if (unlikely(!PageUptodate(page))) + goto page_unlock; + + max_off = DIV_ROUND_UP(i_size_read(inode), PAGE_SIZE); + if (unlikely(offset >= max_off)) + goto page_unlock; + + /* + * Update readahead mmap_miss statistic. + * + * Note that we are not sure if finish_fault() will + * manage to complete the transaction. If it fails, + * we'll come back to filemap_fault() non-speculative + * case which will update mmap_miss a second time. + * This is not ideal, we would prefer to guarantee the + * update will happen exactly once. + */ + if (!(vmf->vma->vm_flags & VM_RAND_READ) && ra->ra_pages) { + unsigned int mmap_miss = READ_ONCE(ra->mmap_miss); + if (mmap_miss) + WRITE_ONCE(ra->mmap_miss, --mmap_miss); + } + + vmf->page = page; + return VM_FAULT_LOCKED; +page_unlock: + unlock_page(page); +page_put: + put_page(page); + return VM_FAULT_RETRY; + } + max_off = DIV_ROUND_UP(i_size_read(inode), PAGE_SIZE); if (unlikely(offset >= max_off)) return VM_FAULT_SIGBUS; diff --git a/mm/frontswap.c b/mm/frontswap.c index 157e5bf63504258e3d1be341854627d47d4b96d0..80bf870d881a04f944f196dbbeb67077c0984b18 100644 --- a/mm/frontswap.c +++ b/mm/frontswap.c @@ -447,7 +447,7 @@ static int __frontswap_shrink(unsigned long target_pages, void frontswap_shrink(unsigned long target_pages) { unsigned long pages_to_unuse = 0; - int uninitialized_var(type), ret; + int type, ret; /* * we don't want to hold swap_lock while doing a very diff --git a/mm/khugepaged.c b/mm/khugepaged.c index 77fff0c795e97e4fd185d57d2ae83e991767a956..53dadd777bb7ca3e7250a3d6f9a889a34827ce0a 100644 --- a/mm/khugepaged.c +++ b/mm/khugepaged.c @@ -1311,12 +1311,14 @@ static void retract_page_tables(struct address_space *mapping, pgoff_t pgoff) spinlock_t *ptl; unsigned long end = addr + HPAGE_PMD_SIZE; + vm_write_begin(vma); mmu_notifier_invalidate_range_start(mm, addr, end); ptl = pmd_lock(mm, pmd); /* assume page table is clear */ _pmd = pmdp_collapse_flush(vma, addr, pmd); spin_unlock(ptl); + vm_write_end(vma); mm_dec_nr_ptes(mm); tlb_remove_table_sync_one(); pte_free(mm, pmd_pgtable(_pmd)); diff --git a/mm/ksm.c b/mm/ksm.c index 9ee40e4f30614547a7389ed07c9f3d6fb58f13db..5d7dbfcc7e34bac14423b83b25d671f2444af4e3 100644 --- a/mm/ksm.c +++ b/mm/ksm.c @@ -2382,7 +2382,7 @@ static struct rmap_item *scan_get_next_rmap_item(struct page **page) static void ksm_do_scan(unsigned int scan_npages) { struct rmap_item *rmap_item; - struct page *uninitialized_var(page); + struct page *page; while (scan_npages-- && likely(!freezing(current))) { cond_resched(); diff --git a/mm/memcontrol.c b/mm/memcontrol.c index 5b5d100588315bade6484ad6c11d59fe6ad52b9c..bd2d8613f81bad5b4bfe162a59a126c041bf96bd 100644 --- a/mm/memcontrol.c +++ b/mm/memcontrol.c @@ -920,7 +920,7 @@ struct mem_cgroup *mem_cgroup_iter(struct mem_cgroup *root, struct mem_cgroup *prev, struct mem_cgroup_reclaim_cookie *reclaim) { - struct mem_cgroup_reclaim_iter *uninitialized_var(iter); + struct mem_cgroup_reclaim_iter *iter; struct cgroup_subsys_state *css = NULL; struct mem_cgroup *memcg = NULL; struct mem_cgroup *pos = NULL; diff --git a/mm/memory.c b/mm/memory.c index 5a5a92b0661de4e6213bdaad363de357ddced109..4e87ea752cc7a60c157c30eef691eb6ec3de9aec 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -1606,7 +1606,6 @@ void unmap_page_range(struct mmu_gather *tlb, unsigned long next; BUG_ON(addr >= end); - vm_write_begin(vma); tlb_start_vma(tlb, vma); pgd = pgd_offset(vma->vm_mm, addr); do { @@ -1616,7 +1615,6 @@ void unmap_page_range(struct mmu_gather *tlb, next = zap_p4d_range(tlb, vma, pgd, addr, next, details); } while (pgd++, addr = next, addr != end); tlb_end_vma(tlb, vma); - vm_write_end(vma); } @@ -3275,6 +3273,11 @@ vm_fault_t do_swap_page(struct vm_fault *vmf) int exclusive = 0; vm_fault_t ret; + if (vmf->flags & FAULT_FLAG_SPECULATIVE) { + pte_unmap(vmf->pte); + return VM_FAULT_RETRY; + } + ret = pte_unmap_same(vmf); if (ret) { /* @@ -3535,6 +3538,10 @@ static vm_fault_t do_anonymous_page(struct vm_fault *vmf) if (vmf->vma_flags & VM_SHARED) return VM_FAULT_SIGBUS; + /* Do not check unstable pmd, if it's changed will retry later */ + if (vmf->flags & FAULT_FLAG_SPECULATIVE) + goto skip_pmd_checks; + /* * Use pte_alloc() instead of pte_alloc_map(). We can't run * pte_offset_map() on pmds where a huge pmd might be created @@ -3552,6 +3559,7 @@ static vm_fault_t do_anonymous_page(struct vm_fault *vmf) if (unlikely(pmd_trans_unstable(vmf->pmd))) return 0; +skip_pmd_checks: /* Use the zero-page for reads */ if (!(vmf->flags & FAULT_FLAG_WRITE) && !mm_forbids_zeropage(vma->vm_mm)) { @@ -3656,6 +3664,10 @@ static vm_fault_t __do_fault(struct vm_fault *vmf) struct vm_area_struct *vma = vmf->vma; vm_fault_t ret; + /* Do not check unstable pmd, if it's changed will retry later */ + if (vmf->flags & FAULT_FLAG_SPECULATIVE) + goto skip_pmd_checks; + /* * Preallocate pte before we take page_lock because this might lead to * deadlocks for memcg reclaim which waits for pages under writeback: @@ -3679,6 +3691,7 @@ static vm_fault_t __do_fault(struct vm_fault *vmf) smp_wmb(); /* See comment in __pte_alloc() */ } +skip_pmd_checks: ret = vma->vm_ops->fault(vmf); if (unlikely(ret & (VM_FAULT_ERROR | VM_FAULT_NOPAGE | VM_FAULT_RETRY | VM_FAULT_DONE_COW))) @@ -4066,7 +4079,8 @@ static vm_fault_t do_fault_around(struct vm_fault *vmf) end_pgoff = min3(end_pgoff, vma_pages(vmf->vma) + vmf->vma->vm_pgoff - 1, start_pgoff + nr_pages - 1); - if (pmd_none(*vmf->pmd)) { + if (!(vmf->flags & FAULT_FLAG_SPECULATIVE) && + pmd_none(*vmf->pmd)) { vmf->prealloc_pte = pte_alloc_one(vmf->vma->vm_mm, vmf->address); if (!vmf->prealloc_pte) @@ -4434,16 +4448,11 @@ static vm_fault_t handle_pte_fault(struct vm_fault *vmf) pte_t entry; int ret = 0; + /* Do not check unstable pmd, if it's changed will retry later */ + if (vmf->flags & FAULT_FLAG_SPECULATIVE) + goto skip_pmd_checks; + if (unlikely(pmd_none(*vmf->pmd))) { - /* - * In the case of the speculative page fault handler we abort - * the speculative path immediately as the pmd is probably - * in the way to be converted in a huge one. We will try - * again holding the mmap_sem (which implies that the collapse - * operation is done). - */ - if (vmf->flags & FAULT_FLAG_SPECULATIVE) - return VM_FAULT_RETRY; /* * Leave __pte_alloc() until later: because vm_ops->fault may * want to allocate huge page, and if we expose page table @@ -4451,8 +4460,7 @@ static vm_fault_t handle_pte_fault(struct vm_fault *vmf) * concurrent faults and from rmap lookups. */ vmf->pte = NULL; - } else if (!(vmf->flags & FAULT_FLAG_SPECULATIVE)) { - /* See comment in pte_alloc_one_map() */ + } else { if (pmd_devmap_trans_unstable(vmf->pmd)) return 0; /* @@ -4482,6 +4490,7 @@ static vm_fault_t handle_pte_fault(struct vm_fault *vmf) } } +skip_pmd_checks: if (!vmf->pte) { if (vma_is_anonymous(vmf->vma)) return do_anonymous_page(vmf); @@ -4729,11 +4738,10 @@ int __handle_speculative_fault(struct mm_struct *mm, unsigned long address, pol = __get_vma_policy(vmf.vma, address); if (!pol) pol = get_task_policy(current); - if (!pol) - if (pol && pol->mode == MPOL_INTERLEAVE) { - trace_spf_vma_notsup(_RET_IP_, vmf.vma, address); - return VM_FAULT_RETRY; - } + if (pol && pol->mode == MPOL_INTERLEAVE) { + trace_spf_vma_notsup(_RET_IP_, vmf.vma, address); + return VM_FAULT_RETRY; + } #endif /* diff --git a/mm/mempolicy.c b/mm/mempolicy.c index 40b1dc09e13d4f95979b42f339542bac2470108e..c542f29a4d566d733e42b0ec1ec6ccd1d156b291 100644 --- a/mm/mempolicy.c +++ b/mm/mempolicy.c @@ -600,11 +600,9 @@ unsigned long change_prot_numa(struct vm_area_struct *vma, { int nr_updated; - vm_write_begin(vma); nr_updated = change_protection(vma, addr, end, PAGE_NONE, 0, 1); if (nr_updated) count_vm_numa_events(NUMA_PTE_UPDATES, nr_updated); - vm_write_end(vma); return nr_updated; } @@ -1160,7 +1158,7 @@ int do_migrate_pages(struct mm_struct *mm, const nodemask_t *from, static struct page *new_page(struct page *page, unsigned long start) { struct vm_area_struct *vma; - unsigned long uninitialized_var(address); + unsigned long address; vma = find_vma(current->mm, start); while (vma) { @@ -1559,7 +1557,7 @@ static int kernel_get_mempolicy(int __user *policy, unsigned long flags) { int err; - int uninitialized_var(pval); + int pval; nodemask_t nodes; addr = untagged_addr(addr); diff --git a/mm/mmap.c b/mm/mmap.c index f761de345e20532b9e4142261a35790d92ceb564..51b3595d0e11aea67d282fba423bf6975019cabb 100644 --- a/mm/mmap.c +++ b/mm/mmap.c @@ -2329,8 +2329,22 @@ struct vm_area_struct *get_vma(struct mm_struct *mm, unsigned long addr) read_lock(&mm->mm_rb_lock); vma = __find_vma(mm, addr); - if (vma) - atomic_inc(&vma->vm_ref_count); + + /* + * If there is a concurrent fast mremap, bail out since the entire + * PMD/PUD subtree may have been remapped. + * + * This is usually safe for conventional mremap since it takes the + * PTE locks as does SPF. However fast mremap only takes the lock + * at the PMD/PUD level which is ok as it is done with the mmap + * write lock held. But since SPF, as the term implies forgoes, + * taking the mmap read lock and also cannot take PTL lock at the + * larger PMD/PUD granualrity, since it would introduce huge + * contention in the page fault path; fall back to regular fault + * handling. + */ + if (vma && !atomic_inc_unless_negative(&vma->vm_ref_count)) + vma = NULL; read_unlock(&mm->mm_rb_lock); return vma; @@ -3203,10 +3217,9 @@ void exit_mmap(struct mm_struct *mm) (void)__oom_reap_task_mm(mm); set_bit(MMF_OOM_SKIP, &mm->flags); - down_write(&mm->mmap_sem); - up_write(&mm->mmap_sem); } + down_write(&mm->mmap_sem); if (mm->locked_vm) { vma = mm->mmap; while (vma) { @@ -3219,8 +3232,11 @@ void exit_mmap(struct mm_struct *mm) arch_exit_mmap(mm); vma = mm->mmap; - if (!vma) /* Can happen if dup_mmap() received an OOM */ + if (!vma) { + /* Can happen if dup_mmap() received an OOM */ + up_write(&mm->mmap_sem);; return; + } lru_add_drain(); flush_cache_mm(mm); @@ -3231,16 +3247,14 @@ void exit_mmap(struct mm_struct *mm) free_pgtables(&tlb, vma, FIRST_USER_ADDRESS, USER_PGTABLES_CEILING); tlb_finish_mmu(&tlb, 0, -1); - /* - * Walk the list again, actually closing and freeing it, - * with preemption enabled, without holding any MM locks. - */ + /* Walk the list again, actually closing and freeing it. */ while (vma) { if (vma->vm_flags & VM_ACCOUNT) nr_accounted += vma_pages(vma); vma = remove_vma(vma); cond_resched(); } + up_write(&mm->mmap_sem); vm_unacct_memory(nr_accounted); } diff --git a/mm/page_alloc.c b/mm/page_alloc.c index 0d72bdf5912b6ce8f0d349f6d9b4219dd1a3309c..ea82497aefaed8434720a3718432a1aa09bed8a8 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -3791,11 +3791,15 @@ static inline bool zone_watermark_fast(struct zone *z, unsigned int order, * need to be calculated. */ if (!order) { - long fast_free; + long usable_free; + long reserved; - fast_free = free_pages; - fast_free -= __zone_watermark_unusable_free(z, 0, alloc_flags); - if (fast_free > mark + z->lowmem_reserve[classzone_idx]) + usable_free = free_pages; + reserved = __zone_watermark_unusable_free(z, 0, alloc_flags); + + /* reserved may over estimate high-atomic reserves. */ + usable_free -= min(usable_free, reserved); + if (usable_free > mark + z->lowmem_reserve[classzone_idx]) return true; } @@ -6187,7 +6191,21 @@ static void __build_all_zonelists(void *data) int nid; int __maybe_unused cpu; pg_data_t *self = data; + unsigned long flags; + /* + * Explicitly disable this CPU's interrupts before taking seqlock + * to prevent any IRQ handler from calling into the page allocator + * (e.g. GFP_ATOMIC) that could hit zonelist_iter_begin and livelock. + */ + local_irq_save(flags); + /* + * Explicitly disable this CPU's synchronous printk() before taking + * seqlock to prevent any printk() from trying to hold port->lock, for + * tty_insert_flip_string_and_push_buffer() on other CPU might be + * calling kmalloc(GFP_ATOMIC | __GFP_NOWARN) with port->lock held. + */ + printk_deferred_enter(); write_seqlock(&zonelist_update_seq); #ifdef CONFIG_NUMA @@ -6222,6 +6240,8 @@ static void __build_all_zonelists(void *data) } write_sequnlock(&zonelist_update_seq); + printk_deferred_exit(); + local_irq_restore(flags); } static noinline void __init diff --git a/mm/percpu.c b/mm/percpu.c index 2bbae237a8e8055276ed1999408095e218233b49..e3f211c03a34783e8adec80485da2743d86a8ffe 100644 --- a/mm/percpu.c +++ b/mm/percpu.c @@ -2284,7 +2284,7 @@ static struct pcpu_alloc_info * __init pcpu_build_alloc_info( const size_t static_size = __per_cpu_end - __per_cpu_start; int nr_groups = 1, nr_units = 0; size_t size_sum, min_unit_size, alloc_size; - int upa, max_upa, uninitialized_var(best_upa); /* units_per_alloc */ + int upa, max_upa, best_upa; /* units_per_alloc */ int last_allocs, group, unit; unsigned int cpu, tcpu; struct pcpu_alloc_info *ai; diff --git a/mm/readahead.c b/mm/readahead.c index 4e630143a0ba8549c9a63f106c7dd18b7aaa4d18..96d0f652222a99f9139e3d0d8458eb9f1fb9ced8 100644 --- a/mm/readahead.c +++ b/mm/readahead.c @@ -593,7 +593,8 @@ ssize_t ksys_readahead(int fd, loff_t offset, size_t count) */ ret = -EINVAL; if (!f.file->f_mapping || !f.file->f_mapping->a_ops || - !S_ISREG(file_inode(f.file)->i_mode)) + (!S_ISREG(file_inode(f.file)->i_mode) && + !S_ISBLK(file_inode(f.file)->i_mode))) goto out; ret = vfs_fadvise(f.file, offset, count, POSIX_FADV_WILLNEED); diff --git a/mm/rmap.c b/mm/rmap.c index b5c0e2fd71b61711dfe13952c0940fb7a7a9442d..afab7fe9848760a1be05735199765718e7e36ea0 100644 --- a/mm/rmap.c +++ b/mm/rmap.c @@ -82,7 +82,8 @@ static inline struct anon_vma *anon_vma_alloc(void) anon_vma = kmem_cache_alloc(anon_vma_cachep, GFP_KERNEL); if (anon_vma) { atomic_set(&anon_vma->refcount, 1); - anon_vma->degree = 1; /* Reference for first vma */ + anon_vma->num_children = 0; + anon_vma->num_active_vmas = 0; anon_vma->parent = anon_vma; /* * Initialise the anon_vma root to point to itself. If called @@ -190,6 +191,7 @@ int __anon_vma_prepare(struct vm_area_struct *vma) anon_vma = anon_vma_alloc(); if (unlikely(!anon_vma)) goto out_enomem_free_avc; + anon_vma->num_children++; /* self-parent link for new root */ allocated = anon_vma; } @@ -199,8 +201,7 @@ int __anon_vma_prepare(struct vm_area_struct *vma) if (likely(!vma->anon_vma)) { vma->anon_vma = anon_vma; anon_vma_chain_link(vma, avc, anon_vma); - /* vma reference or self-parent link for new root */ - anon_vma->degree++; + anon_vma->num_active_vmas++; allocated = NULL; avc = NULL; } @@ -279,19 +280,19 @@ int anon_vma_clone(struct vm_area_struct *dst, struct vm_area_struct *src) anon_vma_chain_link(dst, avc, anon_vma); /* - * Reuse existing anon_vma if its degree lower than two, - * that means it has no vma and only one anon_vma child. + * Reuse existing anon_vma if it has no vma and only one + * anon_vma child. * - * Do not chose parent anon_vma, otherwise first child - * will always reuse it. Root anon_vma is never reused: + * Root anon_vma is never reused: * it has self-parent reference and at least one child. */ - if (!dst->anon_vma && anon_vma != src->anon_vma && - anon_vma->degree < 2) + if (!dst->anon_vma && src->anon_vma && + anon_vma->num_children < 2 && + anon_vma->num_active_vmas == 0) dst->anon_vma = anon_vma; } if (dst->anon_vma) - dst->anon_vma->degree++; + dst->anon_vma->num_active_vmas++; unlock_anon_vma_root(root); return 0; @@ -418,6 +419,7 @@ int anon_vma_fork(struct vm_area_struct *vma, struct vm_area_struct *pvma) anon_vma = anon_vma_alloc(); if (!anon_vma) goto out_error; + anon_vma->num_active_vmas++; avc = anon_vma_chain_alloc(GFP_KERNEL); if (!avc) goto out_error_free_anon_vma; @@ -438,7 +440,7 @@ int anon_vma_fork(struct vm_area_struct *vma, struct vm_area_struct *pvma) vma->anon_vma = anon_vma; anon_vma_lock_write(anon_vma); anon_vma_chain_link(vma, avc, anon_vma); - anon_vma->parent->degree++; + anon_vma->parent->num_children++; anon_vma_unlock_write(anon_vma); return 0; @@ -470,7 +472,7 @@ void unlink_anon_vmas(struct vm_area_struct *vma) * to free them outside the lock. */ if (RB_EMPTY_ROOT(&anon_vma->rb_root.rb_root)) { - anon_vma->parent->degree--; + anon_vma->parent->num_children--; continue; } @@ -478,7 +480,8 @@ void unlink_anon_vmas(struct vm_area_struct *vma) anon_vma_chain_free(avc); } if (vma->anon_vma) - vma->anon_vma->degree--; + vma->anon_vma->num_active_vmas--; + unlock_anon_vma_root(root); /* @@ -489,7 +492,8 @@ void unlink_anon_vmas(struct vm_area_struct *vma) list_for_each_entry_safe(avc, next, &vma->anon_vma_chain, same_vma) { struct anon_vma *anon_vma = avc->anon_vma; - VM_WARN_ON(anon_vma->degree); + VM_WARN_ON(anon_vma->num_children); + VM_WARN_ON(anon_vma->num_active_vmas); put_anon_vma(anon_vma); list_del(&avc->same_vma); diff --git a/mm/slub.c b/mm/slub.c index 315e8afd33f385dd715af086234a6c3c3272af4c..22de88eb9235f90b852edfb2be5de5ab5cddedef 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -1333,7 +1333,7 @@ static noinline int free_debug_processing( struct kmem_cache_node *n = get_node(s, page_to_nid(page)); void *object = head; int cnt = 0; - unsigned long uninitialized_var(flags); + unsigned long flags; int ret = 0; spin_lock_irqsave(&n->list_lock, flags); @@ -3040,7 +3040,7 @@ static void __slab_free(struct kmem_cache *s, struct page *page, struct page new; unsigned long counters; struct kmem_cache_node *n = NULL; - unsigned long uninitialized_var(flags); + unsigned long flags; stat(s, FREE_SLOWPATH); diff --git a/mm/swap.c b/mm/swap.c index c95d89c08475b52ef301da0f24ae0aa972e3d8f3..2bf3b4141211ccd33a757dc4351cd3de0d97404a 100644 --- a/mm/swap.c +++ b/mm/swap.c @@ -721,8 +721,8 @@ void release_pages(struct page **pages, int nr) LIST_HEAD(pages_to_free); struct pglist_data *locked_pgdat = NULL; struct lruvec *lruvec; - unsigned long uninitialized_var(flags); - unsigned int uninitialized_var(lock_batch); + unsigned long flags; + unsigned int lock_batch; for (i = 0; i < nr; i++) { struct page *page = pages[i]; diff --git a/mm/swapfile.c b/mm/swapfile.c index 5617d44f0e8271230f31606e21248c61ed8dbe76..48205531dcda1a064e58313473477c6c9aedcecc 100644 --- a/mm/swapfile.c +++ b/mm/swapfile.c @@ -630,6 +630,7 @@ static void __del_from_avail_list(struct swap_info_struct *p) { int nid; + assert_spin_locked(&p->lock); for_each_node(nid) plist_del(&p->avail_lists[nid], &swap_avail_heads[nid]); } @@ -2634,8 +2635,8 @@ SYSCALL_DEFINE1(swapoff, const char __user *, specialfile) spin_unlock(&swap_lock); goto out_dput; } - del_from_avail_list(p); spin_lock(&p->lock); + del_from_avail_list(p); if (p->prio < 0) { struct swap_info_struct *si = p; int nid; diff --git a/net/8021q/vlan_dev.c b/net/8021q/vlan_dev.c index 84ef837721141549c0e57bb5bdf2e917b6ec0cc6..ba9b8980f100d32f44bb251e66f93ddef83b894f 100644 --- a/net/8021q/vlan_dev.c +++ b/net/8021q/vlan_dev.c @@ -115,8 +115,8 @@ static netdev_tx_t vlan_dev_hard_start_xmit(struct sk_buff *skb, * NOTE: THIS ASSUMES DIX ETHERNET, SPECIFICALLY NOT SUPPORTING * OTHER THINGS LIKE FDDI/TokenRing/802.3 SNAPs... */ - if (veth->h_vlan_proto != vlan->vlan_proto || - vlan->flags & VLAN_FLAG_REORDER_HDR) { + if (vlan->flags & VLAN_FLAG_REORDER_HDR || + veth->h_vlan_proto != vlan->vlan_proto) { u16 vlan_tci; vlan_tci = vlan->vlan_id; vlan_tci |= vlan_dev_get_egress_qos_mask(dev, skb->priority); @@ -369,7 +369,7 @@ static int vlan_dev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) switch (cmd) { case SIOCSHWTSTAMP: - if (!net_eq(dev_net(dev), &init_net)) + if (!net_eq(dev_net(dev), dev_net(real_dev))) break; case SIOCGMIIPHY: case SIOCGMIIREG: diff --git a/net/9p/trans_rdma.c b/net/9p/trans_rdma.c index 119103bfa82eef579e53e60908812b33c1fea52f..4bbb8683d45187e2716b25d0f5db30038a55e41d 100644 --- a/net/9p/trans_rdma.c +++ b/net/9p/trans_rdma.c @@ -400,6 +400,7 @@ post_recv(struct p9_client *client, struct p9_rdma_context *c) struct p9_trans_rdma *rdma = client->trans; struct ib_recv_wr wr; struct ib_sge sge; + int ret; c->busa = ib_dma_map_single(rdma->cm_id->device, c->rc.sdata, client->msize, @@ -417,7 +418,12 @@ post_recv(struct p9_client *client, struct p9_rdma_context *c) wr.wr_cqe = &c->cqe; wr.sg_list = &sge; wr.num_sge = 1; - return ib_post_recv(rdma->qp, &wr, NULL); + + ret = ib_post_recv(rdma->qp, &wr, NULL); + if (ret) + ib_dma_unmap_single(rdma->cm_id->device, c->busa, + client->msize, DMA_FROM_DEVICE); + return ret; error: p9_debug(P9_DEBUG_ERROR, "EIO\n"); @@ -514,7 +520,7 @@ static int rdma_request(struct p9_client *client, struct p9_req_t *req) if (down_interruptible(&rdma->sq_sem)) { err = -EINTR; - goto send_error; + goto dma_unmap; } /* Mark request as `sent' *before* we actually send it, @@ -524,11 +530,14 @@ static int rdma_request(struct p9_client *client, struct p9_req_t *req) req->status = REQ_STATUS_SENT; err = ib_post_send(rdma->qp, &wr, NULL); if (err) - goto send_error; + goto dma_unmap; /* Success */ return 0; +dma_unmap: + ib_dma_unmap_single(rdma->cm_id->device, c->busa, + c->req->tc.size, DMA_TO_DEVICE); /* Handle errors that happened during or while preparing the send: */ send_error: req->status = REQ_STATUS_ERROR; diff --git a/net/9p/trans_virtio.c b/net/9p/trans_virtio.c index f7cd8e018bde0df750460e3d397190d52ae36bd7..6b3357a77d992dac0ef32325931070b9e1ecf1e4 100644 --- a/net/9p/trans_virtio.c +++ b/net/9p/trans_virtio.c @@ -409,7 +409,7 @@ p9_virtio_zc_request(struct p9_client *client, struct p9_req_t *req, struct page **in_pages = NULL, **out_pages = NULL; struct virtio_chan *chan = client->trans; struct scatterlist *sgs[4]; - size_t offs; + size_t offs = 0; int need_drop = 0; int kicked = 0; diff --git a/net/9p/trans_xen.c b/net/9p/trans_xen.c index 6459c2356ff9fa06fa4e0199cb70897f81d64ba0..c87146a496363eada3debfffebf0bab9b0534e00 100644 --- a/net/9p/trans_xen.c +++ b/net/9p/trans_xen.c @@ -299,6 +299,10 @@ static void xen_9pfs_front_free(struct xen_9pfs_front_priv *priv) write_unlock(&xen_9pfs_lock); for (i = 0; i < priv->num_rings; i++) { + struct xen_9pfs_dataring *ring = &priv->rings[i]; + + cancel_work_sync(&ring->work); + if (!priv->rings[i].intf) break; if (priv->rings[i].irq > 0) @@ -389,19 +393,24 @@ static int xen_9pfs_front_alloc_dataring(struct xenbus_device *dev, return ret; } -static int xen_9pfs_front_probe(struct xenbus_device *dev, - const struct xenbus_device_id *id) +static int xen_9pfs_front_init(struct xenbus_device *dev) { int ret, i; struct xenbus_transaction xbt; - struct xen_9pfs_front_priv *priv = NULL; - char *versions; + struct xen_9pfs_front_priv *priv = dev_get_drvdata(&dev->dev); + char *versions, *v; unsigned int max_rings, max_ring_order, len = 0; versions = xenbus_read(XBT_NIL, dev->otherend, "versions", &len); if (IS_ERR(versions)) return PTR_ERR(versions); - if (strcmp(versions, "1")) { + for (v = versions; *v; v++) { + if (simple_strtoul(v, &v, 10) == 1) { + v = NULL; + break; + } + } + if (v) { kfree(versions); return -EINVAL; } @@ -414,11 +423,6 @@ static int xen_9pfs_front_probe(struct xenbus_device *dev, if (max_ring_order < XEN_9PFS_RING_ORDER) return -EINVAL; - priv = kzalloc(sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->dev = dev; priv->num_rings = XEN_9PFS_NUM_RINGS; priv->rings = kcalloc(priv->num_rings, sizeof(*priv->rings), GFP_KERNEL); @@ -476,23 +480,35 @@ static int xen_9pfs_front_probe(struct xenbus_device *dev, goto error; } - write_lock(&xen_9pfs_lock); - list_add_tail(&priv->list, &xen_9pfs_devs); - write_unlock(&xen_9pfs_lock); - dev_set_drvdata(&dev->dev, priv); - xenbus_switch_state(dev, XenbusStateInitialised); - return 0; error_xenbus: xenbus_transaction_end(xbt, 1); xenbus_dev_fatal(dev, ret, "writing xenstore"); error: - dev_set_drvdata(&dev->dev, NULL); xen_9pfs_front_free(priv); return ret; } +static int xen_9pfs_front_probe(struct xenbus_device *dev, + const struct xenbus_device_id *id) +{ + struct xen_9pfs_front_priv *priv = NULL; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + dev_set_drvdata(&dev->dev, priv); + + write_lock(&xen_9pfs_lock); + list_add_tail(&priv->list, &xen_9pfs_devs); + write_unlock(&xen_9pfs_lock); + + return 0; +} + static int xen_9pfs_front_resume(struct xenbus_device *dev) { dev_warn(&dev->dev, "suspend/resume unsupported\n"); @@ -511,6 +527,8 @@ static void xen_9pfs_front_changed(struct xenbus_device *dev, break; case XenbusStateInitWait: + if (!xen_9pfs_front_init(dev)) + xenbus_switch_state(dev, XenbusStateInitialised); break; case XenbusStateConnected: diff --git a/net/Kconfig b/net/Kconfig index d93de46fc6d6fc86fc63cd7775f9b12ca1ab204d..b5bfb3bd937a18f44f9091b5058da7cef0db73c0 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -202,7 +202,6 @@ config BRIDGE_NETFILTER source "net/netfilter/Kconfig" source "net/ipv4/netfilter/Kconfig" source "net/ipv6/netfilter/Kconfig" -source "net/decnet/netfilter/Kconfig" source "net/bridge/netfilter/Kconfig" endif @@ -219,7 +218,6 @@ source "net/802/Kconfig" source "net/bridge/Kconfig" source "net/dsa/Kconfig" source "net/8021q/Kconfig" -source "net/decnet/Kconfig" source "net/llc/Kconfig" source "drivers/net/appletalk/Kconfig" source "net/x25/Kconfig" diff --git a/net/Makefile b/net/Makefile index ae2e1364f9df939744737de1971fdaca6d2b6c30..1c55dcd198bf87c769dedb496ce712beac4d9456 100644 --- a/net/Makefile +++ b/net/Makefile @@ -39,7 +39,6 @@ obj-$(CONFIG_AF_KCM) += kcm/ obj-$(CONFIG_STREAM_PARSER) += strparser/ obj-$(CONFIG_ATM) += atm/ obj-$(CONFIG_L2TP) += l2tp/ -obj-$(CONFIG_DECNET) += decnet/ obj-$(CONFIG_PHONET) += phonet/ ifneq ($(CONFIG_VLAN_8021Q),) obj-y += 8021q/ diff --git a/net/atm/resources.c b/net/atm/resources.c index bada395ecdb18f28c69414f019e2ad1b6bfe4531..9389080224f87d2b05c5f9136879c82abd69d028 100644 --- a/net/atm/resources.c +++ b/net/atm/resources.c @@ -447,6 +447,7 @@ int atm_dev_ioctl(unsigned int cmd, void __user *arg, int compat) return error; } +#ifdef CONFIG_PROC_FS void *atm_dev_seq_start(struct seq_file *seq, loff_t *pos) { mutex_lock(&atm_dev_mutex); @@ -462,3 +463,4 @@ void *atm_dev_seq_next(struct seq_file *seq, void *v, loff_t *pos) { return seq_list_next(v, &atm_devs, pos); } +#endif diff --git a/net/batman-adv/bat_v_elp.c b/net/batman-adv/bat_v_elp.c index af3da6cdfc798efd661770f9cb1712bc5f99e532..17100d9ceaf0bbc77544c7ce985bb9dbd0f73ba4 100644 --- a/net/batman-adv/bat_v_elp.c +++ b/net/batman-adv/bat_v_elp.c @@ -513,7 +513,7 @@ int batadv_v_elp_packet_recv(struct sk_buff *skb, struct batadv_priv *bat_priv = netdev_priv(if_incoming->soft_iface); struct batadv_elp_packet *elp_packet; struct batadv_hard_iface *primary_if; - struct ethhdr *ethhdr = (struct ethhdr *)skb_mac_header(skb); + struct ethhdr *ethhdr; bool res; int ret = NET_RX_DROP; @@ -521,6 +521,7 @@ int batadv_v_elp_packet_recv(struct sk_buff *skb, if (!res) goto free_skb; + ethhdr = eth_hdr(skb); if (batadv_is_my_mac(bat_priv, ethhdr->h_source)) goto free_skb; diff --git a/net/batman-adv/bat_v_ogm.c b/net/batman-adv/bat_v_ogm.c index 04a620fd13014463ed0c7c047f3a61a05d862e39..5d4232d8d65117315feb7dc626c49cf03f2cc3fd 100644 --- a/net/batman-adv/bat_v_ogm.c +++ b/net/batman-adv/bat_v_ogm.c @@ -119,8 +119,10 @@ static void batadv_v_ogm_send_to_if(struct sk_buff *skb, { struct batadv_priv *bat_priv = netdev_priv(hard_iface->soft_iface); - if (hard_iface->if_status != BATADV_IF_ACTIVE) + if (hard_iface->if_status != BATADV_IF_ACTIVE) { + kfree_skb(skb); return; + } batadv_inc_counter(bat_priv, BATADV_CNT_MGMT_TX); batadv_add_counter(bat_priv, BATADV_CNT_MGMT_TX_BYTES, @@ -832,7 +834,7 @@ int batadv_v_ogm_packet_recv(struct sk_buff *skb, { struct batadv_priv *bat_priv = netdev_priv(if_incoming->soft_iface); struct batadv_ogm2_packet *ogm_packet; - struct ethhdr *ethhdr = eth_hdr(skb); + struct ethhdr *ethhdr; int ogm_offset; u8 *packet_pos; int ret = NET_RX_DROP; @@ -846,6 +848,7 @@ int batadv_v_ogm_packet_recv(struct sk_buff *skb, if (!batadv_check_management_packet(skb, if_incoming, BATADV_OGM2_HLEN)) goto free_skb; + ethhdr = eth_hdr(skb); if (batadv_is_my_mac(bat_priv, ethhdr->h_source)) goto free_skb; diff --git a/net/batman-adv/distributed-arp-table.c b/net/batman-adv/distributed-arp-table.c index f2dc7499d266333d0ecb68c498e7c805de860794..af380dc877e3138f5f418d08ae11717ab1233038 100644 --- a/net/batman-adv/distributed-arp-table.c +++ b/net/batman-adv/distributed-arp-table.c @@ -68,7 +68,6 @@ static void batadv_dat_purge(struct work_struct *work); */ static void batadv_dat_start_timer(struct batadv_priv *bat_priv) { - INIT_DELAYED_WORK(&bat_priv->dat.work, batadv_dat_purge); queue_delayed_work(batadv_event_workqueue, &bat_priv->dat.work, msecs_to_jiffies(10000)); } @@ -783,6 +782,7 @@ int batadv_dat_init(struct batadv_priv *bat_priv) if (!bat_priv->dat.hash) return -ENOMEM; + INIT_DELAYED_WORK(&bat_priv->dat.work, batadv_dat_purge); batadv_dat_start_timer(bat_priv); batadv_tvlv_handler_register(bat_priv, batadv_dat_tvlv_ogm_handler_v1, diff --git a/net/batman-adv/hard-interface.c b/net/batman-adv/hard-interface.c index 6d68cdb9dd7736baa7aa10463df3502b9bb6875d..0d5519fcb4388f66f421ef1ff9e94b7cd4f5bf2b 100644 --- a/net/batman-adv/hard-interface.c +++ b/net/batman-adv/hard-interface.c @@ -643,7 +643,19 @@ int batadv_hardif_min_mtu(struct net_device *soft_iface) */ void batadv_update_min_mtu(struct net_device *soft_iface) { - soft_iface->mtu = batadv_hardif_min_mtu(soft_iface); + struct batadv_priv *bat_priv = netdev_priv(soft_iface); + int limit_mtu; + int mtu; + + mtu = batadv_hardif_min_mtu(soft_iface); + + if (bat_priv->mtu_set_by_user) + limit_mtu = bat_priv->mtu_set_by_user; + else + limit_mtu = ETH_DATA_LEN; + + mtu = min(mtu, limit_mtu); + dev_set_mtu(soft_iface, mtu); /* Check if the local translate table should be cleaned up to match a * new (and smaller) MTU. diff --git a/net/batman-adv/soft-interface.c b/net/batman-adv/soft-interface.c index 1003abb8cc35ed6da2a242bd7661910a041ac6f7..7447dbd305fc18c66120abcce51a4ca551c1e055 100644 --- a/net/batman-adv/soft-interface.c +++ b/net/batman-adv/soft-interface.c @@ -167,11 +167,14 @@ static int batadv_interface_set_mac_addr(struct net_device *dev, void *p) static int batadv_interface_change_mtu(struct net_device *dev, int new_mtu) { + struct batadv_priv *bat_priv = netdev_priv(dev); + /* check ranges */ if (new_mtu < 68 || new_mtu > batadv_hardif_min_mtu(dev)) return -EINVAL; dev->mtu = new_mtu; + bat_priv->mtu_set_by_user = new_mtu; return 0; } diff --git a/net/batman-adv/translation-table.c b/net/batman-adv/translation-table.c index 6bdb70c93e3fb0853f705620f88e547350c76f6b..c64d58c1b724fb1605812c564f4a261d229f480f 100644 --- a/net/batman-adv/translation-table.c +++ b/net/batman-adv/translation-table.c @@ -793,7 +793,6 @@ bool batadv_tt_local_add(struct net_device *soft_iface, const u8 *addr, if (roamed_back) { batadv_tt_global_free(bat_priv, tt_global, "Roaming canceled"); - tt_global = NULL; } else { /* The global entry has to be marked as ROAMING and * has to be kept for consistency purpose diff --git a/net/batman-adv/types.h b/net/batman-adv/types.h index 37598ae1d3f7a8dfcab26912489eef0545d15042..34c18f72a41ba81f56f06f5392503075a2139fd4 100644 --- a/net/batman-adv/types.h +++ b/net/batman-adv/types.h @@ -1514,6 +1514,12 @@ struct batadv_priv { /** @soft_iface: net device which holds this struct as private data */ struct net_device *soft_iface; + /** + * @mtu_set_by_user: MTU was set once by user + * protected by rtnl_lock + */ + int mtu_set_by_user; + /** * @bat_counters: mesh internal traffic statistic counters (see * batadv_counters) diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c index 1b50e4ef2c6833c7b8b2d34982b08d2460ae3a96..0e837feaa527e534ff9820a5218e69e21f2a5ad3 100644 --- a/net/bluetooth/hci_conn.c +++ b/net/bluetooth/hci_conn.c @@ -125,13 +125,11 @@ static void hci_conn_cleanup(struct hci_conn *conn) if (hdev->notify) hdev->notify(hdev, HCI_NOTIFY_CONN_DEL); - hci_conn_del_sysfs(conn); - debugfs_remove_recursive(conn->debugfs); - hci_dev_put(hdev); + hci_conn_del_sysfs(conn); - hci_conn_put(conn); + hci_dev_put(hdev); } static void le_scan_cleanup(struct work_struct *work) @@ -1204,6 +1202,15 @@ struct hci_conn *hci_connect_acl(struct hci_dev *hdev, bdaddr_t *dst, return ERR_PTR(-EOPNOTSUPP); } + /* Reject outgoing connection to device with same BD ADDR against + * CVE-2020-26555 + */ + if (!bacmp(&hdev->bdaddr, dst)) { + bt_dev_dbg(hdev, "Reject connection with same BD_ADDR %pMR\n", + dst); + return ERR_PTR(-ECONNREFUSED); + } + acl = hci_conn_hash_lookup_ba(hdev, ACL_LINK, dst); if (!acl) { acl = hci_conn_add(hdev, ACL_LINK, dst, HCI_ROLE_MASTER); @@ -1379,34 +1386,41 @@ int hci_conn_security(struct hci_conn *conn, __u8 sec_level, __u8 auth_type, if (!test_bit(HCI_CONN_AUTH, &conn->flags)) goto auth; - /* An authenticated FIPS approved combination key has sufficient - * security for security level 4. */ - if (conn->key_type == HCI_LK_AUTH_COMBINATION_P256 && - sec_level == BT_SECURITY_FIPS) - goto encrypt; - - /* An authenticated combination key has sufficient security for - security level 3. */ - if ((conn->key_type == HCI_LK_AUTH_COMBINATION_P192 || - conn->key_type == HCI_LK_AUTH_COMBINATION_P256) && - sec_level == BT_SECURITY_HIGH) - goto encrypt; - - /* An unauthenticated combination key has sufficient security for - security level 1 and 2. */ - if ((conn->key_type == HCI_LK_UNAUTH_COMBINATION_P192 || - conn->key_type == HCI_LK_UNAUTH_COMBINATION_P256) && - (sec_level == BT_SECURITY_MEDIUM || sec_level == BT_SECURITY_LOW)) - goto encrypt; - - /* A combination key has always sufficient security for the security - levels 1 or 2. High security level requires the combination key - is generated using maximum PIN code length (16). - For pre 2.1 units. */ - if (conn->key_type == HCI_LK_COMBINATION && - (sec_level == BT_SECURITY_MEDIUM || sec_level == BT_SECURITY_LOW || - conn->pin_length == 16)) - goto encrypt; + switch (conn->key_type) { + case HCI_LK_AUTH_COMBINATION_P256: + /* An authenticated FIPS approved combination key has + * sufficient security for security level 4 or lower. + */ + if (sec_level <= BT_SECURITY_FIPS) + goto encrypt; + break; + case HCI_LK_AUTH_COMBINATION_P192: + /* An authenticated combination key has sufficient security for + * security level 3 or lower. + */ + if (sec_level <= BT_SECURITY_HIGH) + goto encrypt; + break; + case HCI_LK_UNAUTH_COMBINATION_P192: + case HCI_LK_UNAUTH_COMBINATION_P256: + /* An unauthenticated combination key has sufficient security + * for security level 2 or lower. + */ + if (sec_level <= BT_SECURITY_MEDIUM) + goto encrypt; + break; + case HCI_LK_COMBINATION: + /* A combination key has always sufficient security for the + * security levels 2 or lower. High security level requires the + * combination key is generated using maximum PIN code length + * (16). For pre 2.1 units. + */ + if (sec_level <= BT_SECURITY_MEDIUM || conn->pin_length == 16) + goto encrypt; + break; + default: + break; + } auth: if (test_bit(HCI_CONN_ENCRYPT_PEND, &conn->flags)) diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c index 497c8ac140d13615d857d5755bead3fef35701af..9fdc772ab32eacb5da592655ff97ba7ae4bd9171 100644 --- a/net/bluetooth/hci_core.c +++ b/net/bluetooth/hci_core.c @@ -2517,10 +2517,10 @@ int hci_remove_link_key(struct hci_dev *hdev, bdaddr_t *bdaddr) int hci_remove_ltk(struct hci_dev *hdev, bdaddr_t *bdaddr, u8 bdaddr_type) { - struct smp_ltk *k; + struct smp_ltk *k, *tmp; int removed = 0; - list_for_each_entry_rcu(k, &hdev->long_term_keys, list) { + list_for_each_entry_safe(k, tmp, &hdev->long_term_keys, list) { if (bacmp(bdaddr, &k->bdaddr) || k->bdaddr_type != bdaddr_type) continue; @@ -2536,9 +2536,9 @@ int hci_remove_ltk(struct hci_dev *hdev, bdaddr_t *bdaddr, u8 bdaddr_type) void hci_remove_irk(struct hci_dev *hdev, bdaddr_t *bdaddr, u8 addr_type) { - struct smp_irk *k; + struct smp_irk *k, *tmp; - list_for_each_entry_rcu(k, &hdev->identity_resolving_keys, list) { + list_for_each_entry_safe(k, tmp, &hdev->identity_resolving_keys, list) { if (bacmp(bdaddr, &k->bdaddr) || k->addr_type != addr_type) continue; diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c index dd7bf437d88e0a7af0da586e74bdb7b75ed45298..8b59f7808628a2871d6d951ba167993119cf0c28 100644 --- a/net/bluetooth/hci_event.c +++ b/net/bluetooth/hci_event.c @@ -25,6 +25,8 @@ /* Bluetooth HCI event handling. */ #include +#include +#include #include #include @@ -2510,6 +2512,16 @@ static void hci_conn_request_evt(struct hci_dev *hdev, struct sk_buff *skb) BT_DBG("%s bdaddr %pMR type 0x%x", hdev->name, &ev->bdaddr, ev->link_type); + /* Reject incoming connection from device with same BD ADDR against + * CVE-2020-26555 + */ + if (hdev && !bacmp(&hdev->bdaddr, &ev->bdaddr)) { + bt_dev_dbg(hdev, "Reject connection with same BD_ADDR %pMR\n", + &ev->bdaddr); + hci_reject_conn(hdev, &ev->bdaddr); + return; + } + mask |= hci_proto_connect_ind(hdev, &ev->bdaddr, ev->link_type, &flags); @@ -3816,6 +3828,15 @@ static void hci_link_key_notify_evt(struct hci_dev *hdev, struct sk_buff *skb) if (!conn) goto unlock; + /* Ignore NULL link key against CVE-2020-26555 */ + if (!crypto_memneq(ev->link_key, ZERO_KEY, HCI_LINK_KEY_SIZE)) { + bt_dev_dbg(hdev, "Ignore NULL link key (ZERO KEY) for %pMR", + &ev->bdaddr); + hci_disconnect(conn, HCI_ERROR_AUTH_FAILURE); + hci_conn_drop(conn); + goto unlock; + } + hci_conn_hold(conn); conn->disc_timeout = HCI_DISCONN_TIMEOUT; hci_conn_drop(conn); @@ -4294,8 +4315,8 @@ static u8 bredr_oob_data_present(struct hci_conn *conn) * available, then do not declare that OOB data is * present. */ - if (!memcmp(data->rand256, ZERO_KEY, 16) || - !memcmp(data->hash256, ZERO_KEY, 16)) + if (!crypto_memneq(data->rand256, ZERO_KEY, 16) || + !crypto_memneq(data->hash256, ZERO_KEY, 16)) return 0x00; return 0x02; @@ -4305,8 +4326,8 @@ static u8 bredr_oob_data_present(struct hci_conn *conn) * not supported by the hardware, then check that if * P-192 data values are present. */ - if (!memcmp(data->rand192, ZERO_KEY, 16) || - !memcmp(data->hash192, ZERO_KEY, 16)) + if (!crypto_memneq(data->rand192, ZERO_KEY, 16) || + !crypto_memneq(data->hash192, ZERO_KEY, 16)) return 0x00; return 0x01; @@ -4322,7 +4343,7 @@ static void hci_io_capa_request_evt(struct hci_dev *hdev, struct sk_buff *skb) hci_dev_lock(hdev); conn = hci_conn_hash_lookup_ba(hdev, ACL_LINK, &ev->bdaddr); - if (!conn) + if (!conn || !hci_conn_ssp_enabled(conn)) goto unlock; hci_conn_hold(conn); @@ -4557,7 +4578,7 @@ static void hci_simple_pair_complete_evt(struct hci_dev *hdev, hci_dev_lock(hdev); conn = hci_conn_hash_lookup_ba(hdev, ACL_LINK, &ev->bdaddr); - if (!conn) + if (!conn || !hci_conn_ssp_enabled(conn)) goto unlock; /* Reset the authentication requirement to unknown */ diff --git a/net/bluetooth/hci_sock.c b/net/bluetooth/hci_sock.c index 3ba0c6df73ce9ebbc77b9a68e800626b0e9b0f73..a7e5bca9f7e4d602f194314cbe357d00b831e652 100644 --- a/net/bluetooth/hci_sock.c +++ b/net/bluetooth/hci_sock.c @@ -430,7 +430,8 @@ static struct sk_buff *create_monitor_event(struct hci_dev *hdev, int event) ni->type = hdev->dev_type; ni->bus = hdev->bus; bacpy(&ni->bdaddr, &hdev->bdaddr); - memcpy(ni->name, hdev->name, 8); + memcpy_and_pad(ni->name, sizeof(ni->name), hdev->name, + strnlen(hdev->name, sizeof(ni->name)), '\0'); opcode = cpu_to_le16(HCI_MON_NEW_INDEX); break; @@ -881,10 +882,6 @@ static int hci_sock_release(struct socket *sock) } sock_orphan(sk); - - skb_queue_purge(&sk->sk_receive_queue); - skb_queue_purge(&sk->sk_write_queue); - release_sock(sk); sock_put(sk); return 0; @@ -977,6 +974,34 @@ static int hci_sock_ioctl(struct socket *sock, unsigned int cmd, BT_DBG("cmd %x arg %lx", cmd, arg); + /* Make sure the cmd is valid before doing anything */ + switch (cmd) { + case HCIGETDEVLIST: + case HCIGETDEVINFO: + case HCIGETCONNLIST: + case HCIDEVUP: + case HCIDEVDOWN: + case HCIDEVRESET: + case HCIDEVRESTAT: + case HCISETSCAN: + case HCISETAUTH: + case HCISETENCRYPT: + case HCISETPTYPE: + case HCISETLINKPOL: + case HCISETLINKMODE: + case HCISETACLMTU: + case HCISETSCOMTU: + case HCIINQUIRY: + case HCISETRAW: + case HCIGETCONNINFO: + case HCIGETAUTHINFO: + case HCIBLOCKADDR: + case HCIUNBLOCKADDR: + break; + default: + return -ENOIOCTLCMD; + } + lock_sock(sk); if (hci_pi(sk)->channel != HCI_CHANNEL_RAW) { @@ -993,7 +1018,14 @@ static int hci_sock_ioctl(struct socket *sock, unsigned int cmd, if (hci_sock_gen_cookie(sk)) { struct sk_buff *skb; - if (capable(CAP_NET_ADMIN)) + /* Perform careful checks before setting the HCI_SOCK_TRUSTED + * flag. Make sure that not only the current task but also + * the socket opener has the required capability, since + * privileged programs can be tricked into making ioctl calls + * on HCI sockets, and the socket should not be marked as + * trusted simply because the ioctl caller is privileged. + */ + if (sk_capable(sk, CAP_NET_ADMIN)) hci_sock_set_flag(sk, HCI_SOCK_TRUSTED); /* Send event to monitor */ @@ -1985,6 +2017,12 @@ static int hci_sock_getsockopt(struct socket *sock, int level, int optname, return err; } +static void hci_sock_destruct(struct sock *sk) +{ + skb_queue_purge(&sk->sk_receive_queue); + skb_queue_purge(&sk->sk_write_queue); +} + static const struct proto_ops hci_sock_ops = { .family = PF_BLUETOOTH, .owner = THIS_MODULE, @@ -2035,6 +2073,7 @@ static int hci_sock_create(struct net *net, struct socket *sock, int protocol, sock->state = SS_UNCONNECTED; sk->sk_state = BT_OPEN; + sk->sk_destruct = hci_sock_destruct; bt_sock_link(&hci_sk_list, sk); return 0; diff --git a/net/bluetooth/hci_sysfs.c b/net/bluetooth/hci_sysfs.c index ccd2c377bf83c8788d5a97a1783779a00c42dcb6..266112c960ee80cd19bbe78411bfc44e71508657 100644 --- a/net/bluetooth/hci_sysfs.c +++ b/net/bluetooth/hci_sysfs.c @@ -33,7 +33,7 @@ void hci_conn_init_sysfs(struct hci_conn *conn) { struct hci_dev *hdev = conn->hdev; - BT_DBG("conn %p", conn); + bt_dev_dbg(hdev, "conn %p", conn); conn->dev.type = &bt_link; conn->dev.class = bt_class; @@ -46,27 +46,30 @@ void hci_conn_add_sysfs(struct hci_conn *conn) { struct hci_dev *hdev = conn->hdev; - BT_DBG("conn %p", conn); + bt_dev_dbg(hdev, "conn %p", conn); if (device_is_registered(&conn->dev)) return; dev_set_name(&conn->dev, "%s:%d", hdev->name, conn->handle); - if (device_add(&conn->dev) < 0) { + if (device_add(&conn->dev) < 0) bt_dev_err(hdev, "failed to register connection device"); - return; - } - - hci_dev_hold(hdev); } void hci_conn_del_sysfs(struct hci_conn *conn) { struct hci_dev *hdev = conn->hdev; - if (!device_is_registered(&conn->dev)) + bt_dev_dbg(hdev, "conn %p", conn); + + if (!device_is_registered(&conn->dev)) { + /* If device_add() has *not* succeeded, use *only* put_device() + * to drop the reference count. + */ + put_device(&conn->dev); return; + } while (1) { struct device *dev; @@ -78,9 +81,7 @@ void hci_conn_del_sysfs(struct hci_conn *conn) put_device(dev); } - device_del(&conn->dev); - - hci_dev_put(hdev); + device_unregister(&conn->dev); } static void bt_host_release(struct device *dev) diff --git a/net/bluetooth/hidp/core.c b/net/bluetooth/hidp/core.c index 0cbd0bca971ff1f4cca536f2a2809f59d8699a04..00dae8e875a2f64d5825944e0d9106b82a59f773 100644 --- a/net/bluetooth/hidp/core.c +++ b/net/bluetooth/hidp/core.c @@ -428,7 +428,7 @@ static void hidp_set_timer(struct hidp_session *session) static void hidp_del_timer(struct hidp_session *session) { if (session->idle_to > 0) - del_timer(&session->timer); + del_timer_sync(&session->timer); } static void hidp_process_report(struct hidp_session *session, int type, diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c index fd95631205a6a9a19d98bbba7af99f38e437ffed..9346fae5d664bda7e62e5af9d7c8957c498d366c 100644 --- a/net/bluetooth/l2cap_core.c +++ b/net/bluetooth/l2cap_core.c @@ -2517,14 +2517,6 @@ int l2cap_chan_send(struct l2cap_chan *chan, struct msghdr *msg, size_t len) if (IS_ERR(skb)) return PTR_ERR(skb); - /* Channel lock is released before requesting new skb and then - * reacquired thus we need to recheck channel state. - */ - if (chan->state != BT_CONNECTED) { - kfree_skb(skb); - return -ENOTCONN; - } - l2cap_do_send(chan, skb); return len; } @@ -2568,14 +2560,6 @@ int l2cap_chan_send(struct l2cap_chan *chan, struct msghdr *msg, size_t len) if (IS_ERR(skb)) return PTR_ERR(skb); - /* Channel lock is released before requesting new skb and then - * reacquired thus we need to recheck channel state. - */ - if (chan->state != BT_CONNECTED) { - kfree_skb(skb); - return -ENOTCONN; - } - l2cap_do_send(chan, skb); err = len; break; @@ -2596,14 +2580,6 @@ int l2cap_chan_send(struct l2cap_chan *chan, struct msghdr *msg, size_t len) */ err = l2cap_segment_sdu(chan, &seg_queue, msg, len); - /* The channel could have been closed while segmenting, - * check that it is still connected. - */ - if (chan->state != BT_CONNECTED) { - __skb_queue_purge(&seg_queue); - err = -ENOTCONN; - } - if (err) break; @@ -4031,6 +4007,10 @@ static int l2cap_connect_create_rsp(struct l2cap_conn *conn, result = __le16_to_cpu(rsp->result); status = __le16_to_cpu(rsp->status); + if (result == L2CAP_CR_SUCCESS && (dcid < L2CAP_CID_DYN_START || + dcid > L2CAP_CID_DYN_END)) + return -EPROTO; + BT_DBG("dcid 0x%4.4x scid 0x%4.4x result 0x%2.2x status 0x%2.2x", dcid, scid, result, status); @@ -4062,6 +4042,11 @@ static int l2cap_connect_create_rsp(struct l2cap_conn *conn, switch (result) { case L2CAP_CR_SUCCESS: + if (__l2cap_get_chan_by_dcid(conn, dcid)) { + err = -EBADSLT; + break; + } + l2cap_state_change(chan, BT_CONFIG); chan->ident = 0; chan->dcid = dcid; @@ -4374,33 +4359,29 @@ static inline int l2cap_disconnect_req(struct l2cap_conn *conn, BT_DBG("scid 0x%4.4x dcid 0x%4.4x", scid, dcid); - mutex_lock(&conn->chan_lock); - - chan = __l2cap_get_chan_by_scid(conn, dcid); + chan = l2cap_get_chan_by_scid(conn, dcid); if (!chan) { - mutex_unlock(&conn->chan_lock); cmd_reject_invalid_cid(conn, cmd->ident, dcid, scid); return 0; } - l2cap_chan_hold(chan); - l2cap_chan_lock(chan); - rsp.dcid = cpu_to_le16(chan->scid); rsp.scid = cpu_to_le16(chan->dcid); l2cap_send_cmd(conn, cmd->ident, L2CAP_DISCONN_RSP, sizeof(rsp), &rsp); chan->ops->set_shutdown(chan); + l2cap_chan_unlock(chan); + mutex_lock(&conn->chan_lock); + l2cap_chan_lock(chan); l2cap_chan_del(chan, ECONNRESET); + mutex_unlock(&conn->chan_lock); chan->ops->close(chan); l2cap_chan_unlock(chan); l2cap_chan_put(chan); - mutex_unlock(&conn->chan_lock); - return 0; } @@ -4420,33 +4401,28 @@ static inline int l2cap_disconnect_rsp(struct l2cap_conn *conn, BT_DBG("dcid 0x%4.4x scid 0x%4.4x", dcid, scid); - mutex_lock(&conn->chan_lock); - - chan = __l2cap_get_chan_by_scid(conn, scid); + chan = l2cap_get_chan_by_scid(conn, scid); if (!chan) { - mutex_unlock(&conn->chan_lock); return 0; } - l2cap_chan_hold(chan); - l2cap_chan_lock(chan); - if (chan->state != BT_DISCONN) { l2cap_chan_unlock(chan); l2cap_chan_put(chan); - mutex_unlock(&conn->chan_lock); return 0; } + l2cap_chan_unlock(chan); + mutex_lock(&conn->chan_lock); + l2cap_chan_lock(chan); l2cap_chan_del(chan, 0); + mutex_unlock(&conn->chan_lock); chan->ops->close(chan); l2cap_chan_unlock(chan); l2cap_chan_put(chan); - mutex_unlock(&conn->chan_lock); - return 0; } @@ -5729,9 +5705,14 @@ static inline int l2cap_le_command_rej(struct l2cap_conn *conn, if (!chan) goto done; + chan = l2cap_chan_hold_unless_zero(chan); + if (!chan) + goto done; + l2cap_chan_lock(chan); l2cap_chan_del(chan, ECONNREFUSED); l2cap_chan_unlock(chan); + l2cap_chan_put(chan); done: mutex_unlock(&conn->chan_lock); diff --git a/net/bluetooth/l2cap_sock.c b/net/bluetooth/l2cap_sock.c index d938311c58a8d839408d0edfc6b336afccd92451..b831e5fe3ebc12db4ad324e0bfb46f2741c01afd 100644 --- a/net/bluetooth/l2cap_sock.c +++ b/net/bluetooth/l2cap_sock.c @@ -45,6 +45,7 @@ static const struct proto_ops l2cap_sock_ops; static void l2cap_sock_init(struct sock *sk, struct sock *parent); static struct sock *l2cap_sock_alloc(struct net *net, struct socket *sock, int proto, gfp_t prio, int kern); +static void l2cap_sock_cleanup_listen(struct sock *parent); bool l2cap_is_socket(struct socket *sock) { @@ -1205,6 +1206,7 @@ static int l2cap_sock_release(struct socket *sock) if (!sk) return 0; + l2cap_sock_cleanup_listen(sk); bt_sock_unlink(&l2cap_sk_list, sk); err = l2cap_sock_shutdown(sock, 2); @@ -1414,6 +1416,14 @@ static struct sk_buff *l2cap_sock_alloc_skb_cb(struct l2cap_chan *chan, if (!skb) return ERR_PTR(err); + /* Channel lock is released before requesting new skb and then + * reacquired thus we need to recheck channel state. + */ + if (chan->state != BT_CONNECTED) { + kfree_skb(skb); + return ERR_PTR(-ENOTCONN); + } + skb->priority = sk->sk_priority; bt_cb(skb)->l2cap.chan = chan; diff --git a/net/bridge/br_if.c b/net/bridge/br_if.c index b5fb2b682e19168018cf5f5bdb10b9397e0b6df5..ab539551b7d3953af39e4d913ba3f7c01afdca20 100644 --- a/net/bridge/br_if.c +++ b/net/bridge/br_if.c @@ -161,8 +161,9 @@ void br_manage_promisc(struct net_bridge *br) * This lets us disable promiscuous mode and write * this config to hw. */ - if (br->auto_cnt == 0 || - (br->auto_cnt == 1 && br_auto_port(p))) + if ((p->dev->priv_flags & IFF_UNICAST_FLT) && + (br->auto_cnt == 0 || + (br->auto_cnt == 1 && br_auto_port(p)))) br_port_clear_promisc(p); else br_port_set_promisc(p); diff --git a/net/caif/caif_usb.c b/net/caif/caif_usb.c index 76d49a1bc6f685f8ae87efc95cb41623ef845b38..609c5793f45a033fdba19fadc5324b96544cc14a 100644 --- a/net/caif/caif_usb.c +++ b/net/caif/caif_usb.c @@ -135,6 +135,9 @@ static int cfusbl_device_notify(struct notifier_block *me, unsigned long what, struct usb_device *usbdev; int res; + if (what == NETDEV_UNREGISTER && dev->reg_state >= NETREG_UNREGISTERED) + return 0; + /* Check whether we have a NCM device, and find its VID/PID. */ if (!(dev->dev.parent && dev->dev.parent->driver && strcmp(dev->dev.parent->driver->name, "cdc_ncm") == 0)) diff --git a/net/can/bcm.c b/net/can/bcm.c index 74e555a22de757fd9a33245d0cfa649f6a98fd99..1c9953c68f095cff29886ced832342f856fab21f 100644 --- a/net/can/bcm.c +++ b/net/can/bcm.c @@ -935,6 +935,8 @@ static int bcm_tx_setup(struct bcm_msg_head *msg_head, struct msghdr *msg, cf = op->frames + op->cfsiz * i; err = memcpy_from_msg((u8 *)cf, msg, op->cfsiz); + if (err < 0) + goto free_op; if (op->flags & CAN_FD_FRAME) { if (cf->len > 64) @@ -944,12 +946,8 @@ static int bcm_tx_setup(struct bcm_msg_head *msg_head, struct msghdr *msg, err = -EINVAL; } - if (err < 0) { - if (op->frames != &op->sframe) - kfree(op->frames); - kfree(op); - return err; - } + if (err < 0) + goto free_op; if (msg_head->flags & TX_CP_CAN_ID) { /* copy can_id into frame */ @@ -1020,6 +1018,12 @@ static int bcm_tx_setup(struct bcm_msg_head *msg_head, struct msghdr *msg, bcm_tx_start_timer(op); return msg_head->nframes * op->cfsiz + MHSIZ; + +free_op: + if (op->frames != &op->sframe) + kfree(op->frames); + kfree(op); + return err; } /* @@ -1516,6 +1520,12 @@ static int bcm_release(struct socket *sock) lock_sock(sk); +#if IS_ENABLED(CONFIG_PROC_FS) + /* remove procfs entry */ + if (net->can.bcmproc_dir && bo->bcm_proc_read) + remove_proc_entry(bo->procname, net->can.bcmproc_dir); +#endif /* CONFIG_PROC_FS */ + list_for_each_entry_safe(op, next, &bo->tx_ops, list) bcm_remove_op(op); @@ -1551,12 +1561,6 @@ static int bcm_release(struct socket *sock) list_for_each_entry_safe(op, next, &bo->rx_ops, list) bcm_remove_op(op); -#if IS_ENABLED(CONFIG_PROC_FS) - /* remove procfs entry */ - if (net->can.bcmproc_dir && bo->bcm_proc_read) - remove_proc_entry(bo->procname, net->can.bcmproc_dir); -#endif /* CONFIG_PROC_FS */ - /* remove device reference */ if (bo->bound) { bo->bound = 0; diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c index 21bd37ec5511c0507cf9aa77f0f0a7d7a9e83306..7fd18e10755ec1fefc54f37e282d6c80c7ff6d44 100644 --- a/net/ceph/messenger.c +++ b/net/ceph/messenger.c @@ -462,7 +462,7 @@ static void set_sock_callbacks(struct socket *sock, */ static int ceph_tcp_connect(struct ceph_connection *con) { - struct sockaddr_storage *paddr = &con->peer_addr.in_addr; + struct sockaddr_storage ss = con->peer_addr.in_addr; /* align */ struct socket *sock; unsigned int noio_flag; int ret; @@ -471,7 +471,7 @@ static int ceph_tcp_connect(struct ceph_connection *con) /* sock_create_kern() allocates with GFP_KERNEL */ noio_flag = memalloc_noio_save(); - ret = sock_create_kern(read_pnet(&con->msgr->net), paddr->ss_family, + ret = sock_create_kern(read_pnet(&con->msgr->net), ss.ss_family, SOCK_STREAM, IPPROTO_TCP, &sock); memalloc_noio_restore(noio_flag); if (ret) @@ -487,8 +487,8 @@ static int ceph_tcp_connect(struct ceph_connection *con) dout("connect %s\n", ceph_pr_addr(&con->peer_addr.in_addr)); con_sock_state_connecting(con); - ret = sock->ops->connect(sock, (struct sockaddr *)paddr, sizeof(*paddr), - O_NONBLOCK); + ret = kernel_connect(sock, (struct sockaddr *)&ss, sizeof(ss), + O_NONBLOCK); if (ret == -EINPROGRESS) { dout("connect %s EINPROGRESS sk_state = %u\n", ceph_pr_addr(&con->peer_addr.in_addr), @@ -1824,14 +1824,15 @@ static int verify_hello(struct ceph_connection *con) return 0; } -static bool addr_is_blank(struct sockaddr_storage *ss) +static bool addr_is_blank(struct ceph_entity_addr *addr) { - struct in_addr *addr = &((struct sockaddr_in *)ss)->sin_addr; - struct in6_addr *addr6 = &((struct sockaddr_in6 *)ss)->sin6_addr; + struct sockaddr_storage ss = addr->in_addr; /* align */ + struct in_addr *addr4 = &((struct sockaddr_in *)&ss)->sin_addr; + struct in6_addr *addr6 = &((struct sockaddr_in6 *)&ss)->sin6_addr; - switch (ss->ss_family) { + switch (ss.ss_family) { case AF_INET: - return addr->s_addr == htonl(INADDR_ANY); + return addr4->s_addr == htonl(INADDR_ANY); case AF_INET6: return ipv6_addr_any(addr6); default: @@ -1839,25 +1840,25 @@ static bool addr_is_blank(struct sockaddr_storage *ss) } } -static int addr_port(struct sockaddr_storage *ss) +static int addr_port(struct ceph_entity_addr *addr) { - switch (ss->ss_family) { + switch (get_unaligned(&addr->in_addr.ss_family)) { case AF_INET: - return ntohs(((struct sockaddr_in *)ss)->sin_port); + return ntohs(get_unaligned(&((struct sockaddr_in *)&addr->in_addr)->sin_port)); case AF_INET6: - return ntohs(((struct sockaddr_in6 *)ss)->sin6_port); + return ntohs(get_unaligned(&((struct sockaddr_in6 *)&addr->in_addr)->sin6_port)); } return 0; } -static void addr_set_port(struct sockaddr_storage *ss, int p) +static void addr_set_port(struct ceph_entity_addr *addr, int p) { - switch (ss->ss_family) { + switch (get_unaligned(&addr->in_addr.ss_family)) { case AF_INET: - ((struct sockaddr_in *)ss)->sin_port = htons(p); + put_unaligned(htons(p), &((struct sockaddr_in *)&addr->in_addr)->sin_port); break; case AF_INET6: - ((struct sockaddr_in6 *)ss)->sin6_port = htons(p); + put_unaligned(htons(p), &((struct sockaddr_in6 *)&addr->in_addr)->sin6_port); break; } } @@ -1865,21 +1866,18 @@ static void addr_set_port(struct sockaddr_storage *ss, int p) /* * Unlike other *_pton function semantics, zero indicates success. */ -static int ceph_pton(const char *str, size_t len, struct sockaddr_storage *ss, +static int ceph_pton(const char *str, size_t len, struct ceph_entity_addr *addr, char delim, const char **ipend) { - struct sockaddr_in *in4 = (struct sockaddr_in *) ss; - struct sockaddr_in6 *in6 = (struct sockaddr_in6 *) ss; - - memset(ss, 0, sizeof(*ss)); + memset(&addr->in_addr, 0, sizeof(addr->in_addr)); - if (in4_pton(str, len, (u8 *)&in4->sin_addr.s_addr, delim, ipend)) { - ss->ss_family = AF_INET; + if (in4_pton(str, len, (u8 *)&((struct sockaddr_in *)&addr->in_addr)->sin_addr.s_addr, delim, ipend)) { + put_unaligned(AF_INET, &addr->in_addr.ss_family); return 0; } - if (in6_pton(str, len, (u8 *)&in6->sin6_addr.s6_addr, delim, ipend)) { - ss->ss_family = AF_INET6; + if (in6_pton(str, len, (u8 *)&((struct sockaddr_in6 *)&addr->in_addr)->sin6_addr.s6_addr, delim, ipend)) { + put_unaligned(AF_INET6, &addr->in_addr.ss_family); return 0; } @@ -1891,7 +1889,7 @@ static int ceph_pton(const char *str, size_t len, struct sockaddr_storage *ss, */ #ifdef CONFIG_CEPH_LIB_USE_DNS_RESOLVER static int ceph_dns_resolve_name(const char *name, size_t namelen, - struct sockaddr_storage *ss, char delim, const char **ipend) + struct ceph_entity_addr *addr, char delim, const char **ipend) { const char *end, *delim_p; char *colon_p, *ip_addr = NULL; @@ -1920,7 +1918,7 @@ static int ceph_dns_resolve_name(const char *name, size_t namelen, /* do dns_resolve upcall */ ip_len = dns_query(NULL, name, end - name, NULL, &ip_addr, NULL); if (ip_len > 0) - ret = ceph_pton(ip_addr, ip_len, ss, -1, NULL); + ret = ceph_pton(ip_addr, ip_len, addr, -1, NULL); else ret = -ESRCH; @@ -1929,13 +1927,13 @@ static int ceph_dns_resolve_name(const char *name, size_t namelen, *ipend = end; pr_info("resolve '%.*s' (ret=%d): %s\n", (int)(end - name), name, - ret, ret ? "failed" : ceph_pr_addr(ss)); + ret, ret ? "failed" : ceph_pr_addr(&addr->in_addr)); return ret; } #else static inline int ceph_dns_resolve_name(const char *name, size_t namelen, - struct sockaddr_storage *ss, char delim, const char **ipend) + struct ceph_entity_addr *addr, char delim, const char **ipend) { return -EINVAL; } @@ -1946,13 +1944,13 @@ static inline int ceph_dns_resolve_name(const char *name, size_t namelen, * then try to extract a hostname to resolve using userspace DNS upcall. */ static int ceph_parse_server_name(const char *name, size_t namelen, - struct sockaddr_storage *ss, char delim, const char **ipend) + struct ceph_entity_addr *addr, char delim, const char **ipend) { int ret; - ret = ceph_pton(name, namelen, ss, delim, ipend); + ret = ceph_pton(name, namelen, addr, delim, ipend); if (ret) - ret = ceph_dns_resolve_name(name, namelen, ss, delim, ipend); + ret = ceph_dns_resolve_name(name, namelen, addr, delim, ipend); return ret; } @@ -1971,7 +1969,6 @@ int ceph_parse_ips(const char *c, const char *end, dout("parse_ips on '%.*s'\n", (int)(end-c), c); for (i = 0; i < max_count; i++) { const char *ipend; - struct sockaddr_storage *ss = &addr[i].in_addr; int port; char delim = ','; @@ -1980,7 +1977,7 @@ int ceph_parse_ips(const char *c, const char *end, p++; } - ret = ceph_parse_server_name(p, end - p, ss, delim, &ipend); + ret = ceph_parse_server_name(p, end - p, &addr[i], delim, &ipend); if (ret) goto bad; ret = -EINVAL; @@ -2011,9 +2008,9 @@ int ceph_parse_ips(const char *c, const char *end, port = CEPH_MON_PORT; } - addr_set_port(ss, port); + addr_set_port(&addr[i], port); - dout("parse_ips got %s\n", ceph_pr_addr(ss)); + dout("parse_ips got %s\n", ceph_pr_addr(&addr[i].in_addr)); if (p == end) break; @@ -2052,7 +2049,7 @@ static int process_banner(struct ceph_connection *con) */ if (memcmp(&con->peer_addr, &con->actual_peer_addr, sizeof(con->peer_addr)) != 0 && - !(addr_is_blank(&con->actual_peer_addr.in_addr) && + !(addr_is_blank(&con->actual_peer_addr) && con->actual_peer_addr.nonce == con->peer_addr.nonce)) { pr_warn("wrong peer, want %s/%d, got %s/%d\n", ceph_pr_addr(&con->peer_addr.in_addr), @@ -2066,13 +2063,13 @@ static int process_banner(struct ceph_connection *con) /* * did we learn our address? */ - if (addr_is_blank(&con->msgr->inst.addr.in_addr)) { - int port = addr_port(&con->msgr->inst.addr.in_addr); + if (addr_is_blank(&con->msgr->inst.addr)) { + int port = addr_port(&con->msgr->inst.addr); memcpy(&con->msgr->inst.addr.in_addr, &con->peer_addr_for_me.in_addr, sizeof(con->peer_addr_for_me.in_addr)); - addr_set_port(&con->msgr->inst.addr.in_addr, port); + addr_set_port(&con->msgr->inst.addr, port); encode_my_addr(con->msgr); dout("process_banner learned my addr is %s\n", ceph_pr_addr(&con->msgr->inst.addr.in_addr)); diff --git a/net/ceph/osd_client.c b/net/ceph/osd_client.c index 713fe1fbcb181831a79a2cd64fdfe87ca1574ea3..90ebb0ba927cd993b8ec63f63ce5c898628eef56 100644 --- a/net/ceph/osd_client.c +++ b/net/ceph/osd_client.c @@ -3137,17 +3137,24 @@ static int linger_reg_commit_wait(struct ceph_osd_linger_request *lreq) int ret; dout("%s lreq %p linger_id %llu\n", __func__, lreq, lreq->linger_id); - ret = wait_for_completion_interruptible(&lreq->reg_commit_wait); + ret = wait_for_completion_killable(&lreq->reg_commit_wait); return ret ?: lreq->reg_commit_error; } -static int linger_notify_finish_wait(struct ceph_osd_linger_request *lreq) +static int linger_notify_finish_wait(struct ceph_osd_linger_request *lreq, + unsigned long timeout) { - int ret; + long left; dout("%s lreq %p linger_id %llu\n", __func__, lreq, lreq->linger_id); - ret = wait_for_completion_interruptible(&lreq->notify_finish_wait); - return ret ?: lreq->notify_finish_error; + left = wait_for_completion_killable_timeout(&lreq->notify_finish_wait, + ceph_timeout_jiffies(timeout)); + if (left <= 0) + left = left ?: -ETIMEDOUT; + else + left = lreq->notify_finish_error; /* completed */ + + return left; } /* @@ -4760,7 +4767,8 @@ int ceph_osdc_notify(struct ceph_osd_client *osdc, ret = linger_reg_commit_wait(lreq); if (!ret) - ret = linger_notify_finish_wait(lreq); + ret = linger_notify_finish_wait(lreq, + msecs_to_jiffies(2 * timeout * MSEC_PER_SEC)); else dout("lreq %p failed to initiate notify %d\n", lreq, ret); diff --git a/net/core/datagram.c b/net/core/datagram.c index 865a8cb7b0bdbab238c81077a15620232d8783b1..6ba82eb14b4650613b751c9d23698b5e99301bdf 100644 --- a/net/core/datagram.c +++ b/net/core/datagram.c @@ -837,18 +837,21 @@ __poll_t datagram_poll(struct file *file, struct socket *sock, { struct sock *sk = sock->sk; __poll_t mask; + u8 shutdown; sock_poll_wait(file, sock, wait); mask = 0; /* exceptional events? */ - if (sk->sk_err || !skb_queue_empty_lockless(&sk->sk_error_queue)) + if (READ_ONCE(sk->sk_err) || + !skb_queue_empty_lockless(&sk->sk_error_queue)) mask |= EPOLLERR | (sock_flag(sk, SOCK_SELECT_ERR_QUEUE) ? EPOLLPRI : 0); - if (sk->sk_shutdown & RCV_SHUTDOWN) + shutdown = READ_ONCE(sk->sk_shutdown); + if (shutdown & RCV_SHUTDOWN) mask |= EPOLLRDHUP | EPOLLIN | EPOLLRDNORM; - if (sk->sk_shutdown == SHUTDOWN_MASK) + if (shutdown == SHUTDOWN_MASK) mask |= EPOLLHUP; /* readable? */ @@ -857,10 +860,12 @@ __poll_t datagram_poll(struct file *file, struct socket *sock, /* Connection-based need to check for termination and startup */ if (connection_based(sk)) { - if (sk->sk_state == TCP_CLOSE) + int state = READ_ONCE(sk->sk_state); + + if (state == TCP_CLOSE) mask |= EPOLLHUP; /* connection hasn't started yet? */ - if (sk->sk_state == TCP_SYN_SENT) + if (state == TCP_SYN_SENT) return mask; } diff --git a/net/core/dev.c b/net/core/dev.c index 98e92a2e7d15d8989ded9c877f531604f994d1c5..8eca7be8b91a3bf7d8689c12b22777574514609d 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -2305,6 +2305,8 @@ int __netif_set_xps_queue(struct net_device *dev, const unsigned long *mask, bool active = false; unsigned int nr_ids; + WARN_ON_ONCE(index >= dev->num_tx_queues); + if (dev->num_tc) { /* Do not allow XPS on subordinate device directly */ num_tc = dev->num_tc; @@ -2794,8 +2796,10 @@ void __dev_kfree_skb_any(struct sk_buff *skb, enum skb_free_reason reason) { if (in_irq() || irqs_disabled()) __dev_kfree_skb_irq(skb, reason); + else if (unlikely(reason == SKB_REASON_DROPPED)) + kfree_skb(skb); else - dev_kfree_skb(skb); + consume_skb(skb); } EXPORT_SYMBOL(__dev_kfree_skb_any); @@ -4058,8 +4062,10 @@ static int get_rps_cpu(struct net_device *dev, struct sk_buff *skb, u32 next_cpu; u32 ident; - /* First check into global flow table if there is a match */ - ident = sock_flow_table->ents[hash & sock_flow_table->mask]; + /* First check into global flow table if there is a match. + * This READ_ONCE() pairs with WRITE_ONCE() from rps_record_sock_flow(). + */ + ident = READ_ONCE(sock_flow_table->ents[hash & sock_flow_table->mask]); if ((ident ^ hash) & ~rps_cpu_mask) goto try_rps; @@ -9026,9 +9032,7 @@ void netdev_run_todo(void) BUG_ON(!list_empty(&dev->ptype_specific)); WARN_ON(rcu_access_pointer(dev->ip_ptr)); WARN_ON(rcu_access_pointer(dev->ip6_ptr)); -#if IS_ENABLED(CONFIG_DECNET) - WARN_ON(dev->dn_ptr); -#endif + if (dev->priv_destructor) dev->priv_destructor(dev); if (dev->needs_free_netdev) diff --git a/net/core/neighbour.c b/net/core/neighbour.c index 6529ea1dd88f22606094c0fe98fc7bc2ede35fdf..4cedef60c061e1ad31af00dcc410dbd30014f9ca 100644 --- a/net/core/neighbour.c +++ b/net/core/neighbour.c @@ -476,37 +476,6 @@ struct neighbour *neigh_lookup(struct neigh_table *tbl, const void *pkey, } EXPORT_SYMBOL(neigh_lookup); -struct neighbour *neigh_lookup_nodev(struct neigh_table *tbl, struct net *net, - const void *pkey) -{ - struct neighbour *n; - unsigned int key_len = tbl->key_len; - u32 hash_val; - struct neigh_hash_table *nht; - - NEIGH_CACHE_STAT_INC(tbl, lookups); - - rcu_read_lock_bh(); - nht = rcu_dereference_bh(tbl->nht); - hash_val = tbl->hash(pkey, NULL, nht->hash_rnd) >> (32 - nht->hash_shift); - - for (n = rcu_dereference_bh(nht->hash_buckets[hash_val]); - n != NULL; - n = rcu_dereference_bh(n->next)) { - if (!memcmp(n->primary_key, pkey, key_len) && - net_eq(dev_net(n->dev), net)) { - if (!refcount_inc_not_zero(&n->refcnt)) - n = NULL; - NEIGH_CACHE_STAT_INC(tbl, hits); - break; - } - } - - rcu_read_unlock_bh(); - return n; -} -EXPORT_SYMBOL(neigh_lookup_nodev); - struct neighbour *__neigh_create(struct neigh_table *tbl, const void *pkey, struct net_device *dev, bool want_ref) { @@ -1661,9 +1630,6 @@ static struct neigh_table *neigh_find_table(int family) case AF_INET6: tbl = neigh_tables[NEIGH_ND_TABLE]; break; - case AF_DECnet: - tbl = neigh_tables[NEIGH_DN_TABLE]; - break; } return tbl; diff --git a/net/core/netpoll.c b/net/core/netpoll.c index 41e32a958d08d1f8402bf7f71c171df8d556a648..08f0da9e6a809dd024ef4b8545c5a8f0958ce722 100644 --- a/net/core/netpoll.c +++ b/net/core/netpoll.c @@ -136,6 +136,20 @@ static void queue_process(struct work_struct *work) } } +static int netif_local_xmit_active(struct net_device *dev) +{ + int i; + + for (i = 0; i < dev->num_tx_queues; i++) { + struct netdev_queue *txq = netdev_get_tx_queue(dev, i); + + if (READ_ONCE(txq->xmit_lock_owner) == smp_processor_id()) + return 1; + } + + return 0; +} + static void poll_one_napi(struct napi_struct *napi) { int work; @@ -182,7 +196,10 @@ void netpoll_poll_dev(struct net_device *dev) if (!ni || down_trylock(&ni->dev_lock)) return; - if (!netif_running(dev)) { + /* Some drivers will take the same locks in poll and xmit, + * we can't poll if local CPU is already in xmit. + */ + if (!netif_running(dev) || netif_local_xmit_active(dev)) { up(&ni->dev_lock); return; } diff --git a/net/core/pktgen.c b/net/core/pktgen.c index 3714cd9e3111f57aefbecb5d0829e4f77c72a41a..3ade60ec45128779215230270fd5023fee2477d7 100644 --- a/net/core/pktgen.c +++ b/net/core/pktgen.c @@ -651,19 +651,19 @@ static int pktgen_if_show(struct seq_file *seq, void *v) seq_puts(seq, " Flags: "); for (i = 0; i < NR_PKT_FLAGS; i++) { - if (i == F_FLOW_SEQ) + if (i == FLOW_SEQ_SHIFT) if (!pkt_dev->cflows) continue; - if (pkt_dev->flags & (1 << i)) + if (pkt_dev->flags & (1 << i)) { seq_printf(seq, "%s ", pkt_flag_names[i]); - else if (i == F_FLOW_SEQ) - seq_puts(seq, "FLOW_RND "); - #ifdef CONFIG_XFRM - if (i == F_IPSEC && pkt_dev->spi) - seq_printf(seq, "spi:%u", pkt_dev->spi); + if (i == IPSEC_SHIFT && pkt_dev->spi) + seq_printf(seq, "spi:%u ", pkt_dev->spi); #endif + } else if (i == FLOW_SEQ_SHIFT) { + seq_puts(seq, "FLOW_RND "); + } } seq_puts(seq, "\n"); diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c index 2837cc03f69e200068099d523855bfc38d1aed2d..0d3f724da78ba23c9667bf56d387e002f7995e57 100644 --- a/net/core/rtnetlink.c +++ b/net/core/rtnetlink.c @@ -2970,9 +2970,12 @@ static int rtnl_newlink(struct sk_buff *skb, struct nlmsghdr *nlh, ifname[0] = '\0'; ifm = nlmsg_data(nlh); - if (ifm->ifi_index > 0) + if (ifm->ifi_index > 0) { dev = __dev_get_by_index(net, ifm->ifi_index); - else { + } else if (ifm->ifi_index < 0) { + NL_SET_ERR_MSG(extack, "ifindex can't be negative"); + return -EINVAL; + } else { if (ifname[0]) dev = __dev_get_by_name(net, ifname); else @@ -3436,7 +3439,7 @@ static int nlmsg_populate_fdb_fill(struct sk_buff *skb, ndm->ndm_ifindex = dev->ifindex; ndm->ndm_state = ndm_state; - if (nla_put(skb, NDA_LLADDR, ETH_ALEN, addr)) + if (nla_put(skb, NDA_LLADDR, dev->addr_len, addr)) goto nla_put_failure; if (vid) if (nla_put(skb, NDA_VLAN, sizeof(u16), &vid)) @@ -3450,10 +3453,10 @@ static int nlmsg_populate_fdb_fill(struct sk_buff *skb, return -EMSGSIZE; } -static inline size_t rtnl_fdb_nlmsg_size(void) +static inline size_t rtnl_fdb_nlmsg_size(const struct net_device *dev) { return NLMSG_ALIGN(sizeof(struct ndmsg)) + - nla_total_size(ETH_ALEN) + /* NDA_LLADDR */ + nla_total_size(dev->addr_len) + /* NDA_LLADDR */ nla_total_size(sizeof(u16)) + /* NDA_VLAN */ 0; } @@ -3465,7 +3468,7 @@ static void rtnl_fdb_notify(struct net_device *dev, u8 *addr, u16 vid, int type, struct sk_buff *skb; int err = -ENOBUFS; - skb = nlmsg_new(rtnl_fdb_nlmsg_size(), GFP_ATOMIC); + skb = nlmsg_new(rtnl_fdb_nlmsg_size(dev), GFP_ATOMIC); if (!skb) goto errout; diff --git a/net/core/skbuff.c b/net/core/skbuff.c index 6dd4fbceb21520b093fa4ab5d8f7fd25ffb978c6..6b3a0d194d285a0c9ba4716aaba938d1e404f946 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -3550,21 +3550,20 @@ struct sk_buff *skb_segment(struct sk_buff *head_skb, struct sk_buff *segs = NULL; struct sk_buff *tail = NULL; struct sk_buff *list_skb = skb_shinfo(head_skb)->frag_list; - skb_frag_t *frag = skb_shinfo(head_skb)->frags; unsigned int mss = skb_shinfo(head_skb)->gso_size; unsigned int doffset = head_skb->data - skb_mac_header(head_skb); - struct sk_buff *frag_skb = head_skb; unsigned int offset = doffset; unsigned int tnl_hlen = skb_tnl_header_len(head_skb); unsigned int partial_segs = 0; unsigned int headroom; unsigned int len = head_skb->len; + struct sk_buff *frag_skb; + skb_frag_t *frag; __be16 proto; bool csum, sg; - int nfrags = skb_shinfo(head_skb)->nr_frags; int err = -ENOMEM; int i = 0; - int pos; + int nfrags, pos; int dummy; if ((skb_shinfo(head_skb)->gso_type & SKB_GSO_DODGY) && @@ -3642,6 +3641,13 @@ struct sk_buff *skb_segment(struct sk_buff *head_skb, headroom = skb_headroom(head_skb); pos = skb_headlen(head_skb); + if (skb_orphan_frags(head_skb, GFP_ATOMIC)) + return ERR_PTR(-ENOMEM); + + nfrags = skb_shinfo(head_skb)->nr_frags; + frag = skb_shinfo(head_skb)->frags; + frag_skb = head_skb; + do { struct sk_buff *nskb; skb_frag_t *nskb_frag; @@ -3666,6 +3672,10 @@ struct sk_buff *skb_segment(struct sk_buff *head_skb, (skb_headlen(list_skb) == len || sg)) { BUG_ON(skb_headlen(list_skb) > len); + nskb = skb_clone(list_skb, GFP_ATOMIC); + if (unlikely(!nskb)) + goto err; + i = 0; nfrags = skb_shinfo(list_skb)->nr_frags; frag = skb_shinfo(list_skb)->frags; @@ -3684,12 +3694,8 @@ struct sk_buff *skb_segment(struct sk_buff *head_skb, frag++; } - nskb = skb_clone(list_skb, GFP_ATOMIC); list_skb = list_skb->next; - if (unlikely(!nskb)) - goto err; - if (unlikely(pskb_trim(nskb, len))) { kfree_skb(nskb); goto err; @@ -3754,12 +3760,16 @@ struct sk_buff *skb_segment(struct sk_buff *head_skb, skb_shinfo(nskb)->tx_flags |= skb_shinfo(head_skb)->tx_flags & SKBTX_SHARED_FRAG; - if (skb_orphan_frags(frag_skb, GFP_ATOMIC) || - skb_zerocopy_clone(nskb, frag_skb, GFP_ATOMIC)) + if (skb_zerocopy_clone(nskb, frag_skb, GFP_ATOMIC)) goto err; while (pos < offset + len) { if (i >= nfrags) { + if (skb_orphan_frags(list_skb, GFP_ATOMIC) || + skb_zerocopy_clone(nskb, list_skb, + GFP_ATOMIC)) + goto err; + i = 0; nfrags = skb_shinfo(list_skb)->nr_frags; frag = skb_shinfo(list_skb)->frags; @@ -3773,10 +3783,6 @@ struct sk_buff *skb_segment(struct sk_buff *head_skb, i--; frag--; } - if (skb_orphan_frags(frag_skb, GFP_ATOMIC) || - skb_zerocopy_clone(nskb, frag_skb, - GFP_ATOMIC)) - goto err; list_skb = list_skb->next; } @@ -4449,6 +4455,11 @@ void __skb_tstamp_tx(struct sk_buff *orig_skb, skb = alloc_skb(0, GFP_ATOMIC); } else { skb = skb_clone(orig_skb, GFP_ATOMIC); + + if (skb_orphan_frags_rx(skb, GFP_ATOMIC)) { + kfree_skb(skb); + return; + } } if (!skb) return; diff --git a/net/core/sock.c b/net/core/sock.c index 26a14aa4a8b01341a1fb388fa3a7f34481a4b2b0..cbe5aa14b427d8cccdb14eec7a045ca84f8d70a4 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -496,7 +496,7 @@ struct dst_entry *__sk_dst_check(struct sock *sk, u32 cookie) if (dst && dst->obsolete && dst->ops->check(dst, cookie) == NULL) { sk_tx_queue_clear(sk); - sk->sk_dst_pending_confirm = 0; + WRITE_ONCE(sk->sk_dst_pending_confirm, 0); RCU_INIT_POINTER(sk->sk_dst_cache, NULL); dst_release(dst); return NULL; @@ -632,7 +632,8 @@ bool sk_mc_loop(struct sock *sk) return false; if (!sk) return true; - switch (sk->sk_family) { + /* IPV6_ADDRFORM can change sk->sk_family under us. */ + switch (READ_ONCE(sk->sk_family)) { case AF_INET: return inet_sk(sk)->mc_loop; #if IS_ENABLED(CONFIG_IPV6) @@ -1319,7 +1320,7 @@ int sock_getsockopt(struct socket *sock, int level, int optname, if (!sock->ops->set_peek_off) return -EOPNOTSUPP; - v.val = sk->sk_peek_off; + v.val = READ_ONCE(sk->sk_peek_off); break; case SO_NOFCS: v.val = sock_flag(sk, SOCK_NOFCS); @@ -1349,7 +1350,7 @@ int sock_getsockopt(struct socket *sock, int level, int optname, #ifdef CONFIG_NET_RX_BUSY_POLL case SO_BUSY_POLL: - v.val = sk->sk_ll_usec; + v.val = READ_ONCE(sk->sk_ll_usec); break; #endif @@ -1795,7 +1796,6 @@ void sk_setup_caps(struct sock *sk, struct dst_entry *dst) { u32 max_segs = 1; - sk_dst_set(sk, dst); sk->sk_route_caps = dst->dev->features | sk->sk_route_forced_caps; if (sk->sk_route_caps & NETIF_F_GSO) sk->sk_route_caps |= NETIF_F_GSO_SOFTWARE; @@ -1810,6 +1810,7 @@ void sk_setup_caps(struct sock *sk, struct dst_entry *dst) } } sk->sk_gso_max_segs = max_segs; + sk_dst_set(sk, dst); } EXPORT_SYMBOL_GPL(sk_setup_caps); @@ -1939,13 +1940,24 @@ kuid_t sock_i_uid(struct sock *sk) } EXPORT_SYMBOL(sock_i_uid); -unsigned long sock_i_ino(struct sock *sk) +unsigned long __sock_i_ino(struct sock *sk) { unsigned long ino; - read_lock_bh(&sk->sk_callback_lock); + read_lock(&sk->sk_callback_lock); ino = sk->sk_socket ? SOCK_INODE(sk->sk_socket)->i_ino : 0; - read_unlock_bh(&sk->sk_callback_lock); + read_unlock(&sk->sk_callback_lock); + return ino; +} +EXPORT_SYMBOL(__sock_i_ino); + +unsigned long sock_i_ino(struct sock *sk) +{ + unsigned long ino; + + local_bh_disable(); + ino = __sock_i_ino(sk); + local_bh_enable(); return ino; } EXPORT_SYMBOL(sock_i_ino); @@ -2060,9 +2072,9 @@ static long sock_wait_for_wmem(struct sock *sk, long timeo) prepare_to_wait(sk_sleep(sk), &wait, TASK_INTERRUPTIBLE); if (refcount_read(&sk->sk_wmem_alloc) < sk->sk_sndbuf) break; - if (sk->sk_shutdown & SEND_SHUTDOWN) + if (READ_ONCE(sk->sk_shutdown) & SEND_SHUTDOWN) break; - if (sk->sk_err) + if (READ_ONCE(sk->sk_err)) break; timeo = schedule_timeout(timeo); } @@ -2090,7 +2102,7 @@ struct sk_buff *sock_alloc_send_pskb(struct sock *sk, unsigned long header_len, goto failure; err = -EPIPE; - if (sk->sk_shutdown & SEND_SHUTDOWN) + if (READ_ONCE(sk->sk_shutdown) & SEND_SHUTDOWN) goto failure; if (sk_wmem_alloc_get(sk) < sk->sk_sndbuf) @@ -2527,7 +2539,7 @@ void __sk_mem_reduce_allocated(struct sock *sk, int amount) if (mem_cgroup_sockets_enabled && sk->sk_memcg) mem_cgroup_uncharge_skmem(sk->sk_memcg, amount); - if (sk_under_memory_pressure(sk) && + if (sk_under_global_memory_pressure(sk) && (sk_memory_allocated(sk) < sk_prot_mem_limits(sk, 0))) sk_leave_memory_pressure(sk); } @@ -2548,7 +2560,7 @@ EXPORT_SYMBOL(__sk_mem_reclaim); int sk_set_peek_off(struct sock *sk, int val) { - sk->sk_peek_off = val; + WRITE_ONCE(sk->sk_peek_off, val); return 0; } EXPORT_SYMBOL_GPL(sk_set_peek_off); @@ -2792,7 +2804,7 @@ void sk_stop_timer(struct sock *sk, struct timer_list* timer) } EXPORT_SYMBOL(sk_stop_timer); -void sock_init_data(struct socket *sock, struct sock *sk) +void sock_init_data_uid(struct socket *sock, struct sock *sk, kuid_t uid) { sk_init_common(sk); sk->sk_send_head = NULL; @@ -2811,11 +2823,10 @@ void sock_init_data(struct socket *sock, struct sock *sk) sk->sk_type = sock->type; sk->sk_wq = sock->wq; sock->sk = sk; - sk->sk_uid = SOCK_INODE(sock)->i_uid; } else { sk->sk_wq = NULL; - sk->sk_uid = make_kuid(sock_net(sk)->user_ns, 0); } + sk->sk_uid = uid; rwlock_init(&sk->sk_callback_lock); if (sk->sk_kern_sock) @@ -2873,6 +2884,16 @@ void sock_init_data(struct socket *sock, struct sock *sk) refcount_set(&sk->sk_refcnt, 1); atomic_set(&sk->sk_drops, 0); } +EXPORT_SYMBOL(sock_init_data_uid); + +void sock_init_data(struct socket *sock, struct sock *sk) +{ + kuid_t uid = sock ? + SOCK_INODE(sock)->i_uid : + make_kuid(sock_net(sk)->user_ns, 0); + + sock_init_data_uid(sock, sk, uid); +} EXPORT_SYMBOL(sock_init_data); void lock_sock_nested(struct sock *sk, int subclass) diff --git a/net/dccp/dccp.h b/net/dccp/dccp.h index aec3c724665f86421f215089c00d17b59caa34b1..579f39e0d02ecabb443363f1a92d687a561d9c67 100644 --- a/net/dccp/dccp.h +++ b/net/dccp/dccp.h @@ -291,6 +291,7 @@ int dccp_rcv_state_process(struct sock *sk, struct sk_buff *skb, int dccp_rcv_established(struct sock *sk, struct sk_buff *skb, const struct dccp_hdr *dh, const unsigned int len); +void dccp_destruct_common(struct sock *sk); int dccp_init_sock(struct sock *sk, const __u8 ctl_sock_initialized); void dccp_destroy_sock(struct sock *sk); diff --git a/net/dccp/ipv4.c b/net/dccp/ipv4.c index c021d5dde8f72f8c67c3adc863e9da04b8dd495b..5281ac3260f6ff2cec5fd3fea4bd331a0bb09a16 100644 --- a/net/dccp/ipv4.c +++ b/net/dccp/ipv4.c @@ -247,12 +247,12 @@ static void dccp_v4_err(struct sk_buff *skb, u32 info) int err; struct net *net = dev_net(skb->dev); - /* Only need dccph_dport & dccph_sport which are the first - * 4 bytes in dccp header. - * Our caller (icmp_socket_deliver()) already pulled 8 bytes for us. - */ - BUILD_BUG_ON(offsetofend(struct dccp_hdr, dccph_sport) > 8); - BUILD_BUG_ON(offsetofend(struct dccp_hdr, dccph_dport) > 8); + if (!pskb_may_pull(skb, offset + sizeof(*dh))) + return; + dh = (struct dccp_hdr *)(skb->data + offset); + if (!pskb_may_pull(skb, offset + __dccp_basic_hdr_len(dh))) + return; + iph = (struct iphdr *)skb->data; dh = (struct dccp_hdr *)(skb->data + offset); sk = __inet_lookup_established(net, &dccp_hashinfo, @@ -612,9 +612,6 @@ int dccp_v4_conn_request(struct sock *sk, struct sk_buff *skb) if (dccp_parse_options(sk, dreq, skb)) goto drop_and_free; - if (security_inet_conn_request(sk, skb, req)) - goto drop_and_free; - ireq = inet_rsk(req); sk_rcv_saddr_set(req_to_sk(req), ip_hdr(skb)->daddr); sk_daddr_set(req_to_sk(req), ip_hdr(skb)->saddr); @@ -622,6 +619,9 @@ int dccp_v4_conn_request(struct sock *sk, struct sk_buff *skb) ireq->ireq_family = AF_INET; ireq->ir_iif = sk->sk_bound_dev_if; + if (security_inet_conn_request(sk, skb, req)) + goto drop_and_free; + /* * Step 3: Process LISTEN state * diff --git a/net/dccp/ipv6.c b/net/dccp/ipv6.c index b2a26e41f932f2863987786bc2e1b1a963380b06..72ceefbf231205260af46fbf997fdd739895f56c 100644 --- a/net/dccp/ipv6.c +++ b/net/dccp/ipv6.c @@ -71,7 +71,7 @@ static inline __u64 dccp_v6_init_sequence(struct sk_buff *skb) static void dccp_v6_err(struct sk_buff *skb, struct inet6_skb_parm *opt, u8 type, u8 code, int offset, __be32 info) { - const struct ipv6hdr *hdr = (const struct ipv6hdr *)skb->data; + const struct ipv6hdr *hdr; const struct dccp_hdr *dh; struct dccp_sock *dp; struct ipv6_pinfo *np; @@ -80,12 +80,12 @@ static void dccp_v6_err(struct sk_buff *skb, struct inet6_skb_parm *opt, __u64 seq; struct net *net = dev_net(skb->dev); - /* Only need dccph_dport & dccph_sport which are the first - * 4 bytes in dccp header. - * Our caller (icmpv6_notify()) already pulled 8 bytes for us. - */ - BUILD_BUG_ON(offsetofend(struct dccp_hdr, dccph_sport) > 8); - BUILD_BUG_ON(offsetofend(struct dccp_hdr, dccph_dport) > 8); + if (!pskb_may_pull(skb, offset + sizeof(*dh))) + return; + dh = (struct dccp_hdr *)(skb->data + offset); + if (!pskb_may_pull(skb, offset + __dccp_basic_hdr_len(dh))) + return; + hdr = (const struct ipv6hdr *)skb->data; dh = (struct dccp_hdr *)(skb->data + offset); sk = __inet6_lookup_established(net, &dccp_hashinfo, @@ -349,15 +349,15 @@ static int dccp_v6_conn_request(struct sock *sk, struct sk_buff *skb) if (dccp_parse_options(sk, dreq, skb)) goto drop_and_free; - if (security_inet_conn_request(sk, skb, req)) - goto drop_and_free; - ireq = inet_rsk(req); ireq->ir_v6_rmt_addr = ipv6_hdr(skb)->saddr; ireq->ir_v6_loc_addr = ipv6_hdr(skb)->daddr; ireq->ireq_family = AF_INET6; ireq->ir_mark = inet_request_mark(sk, skb); + if (security_inet_conn_request(sk, skb, req)) + goto drop_and_free; + if (ipv6_opt_accepted(sk, skb, IP6CB(skb)) || np->rxopt.bits.rxinfo || np->rxopt.bits.rxoinfo || np->rxopt.bits.rxhlim || np->rxopt.bits.rxohlim) { @@ -1000,6 +1000,12 @@ static const struct inet_connection_sock_af_ops dccp_ipv6_mapped = { #endif }; +static void dccp_v6_sk_destruct(struct sock *sk) +{ + dccp_destruct_common(sk); + inet6_sock_destruct(sk); +} + /* NOTE: A lot of things set to zero explicitly by call to * sk_alloc() so need not be done here. */ @@ -1012,17 +1018,12 @@ static int dccp_v6_init_sock(struct sock *sk) if (unlikely(!dccp_v6_ctl_sock_initialized)) dccp_v6_ctl_sock_initialized = 1; inet_csk(sk)->icsk_af_ops = &dccp_ipv6_af_ops; + sk->sk_destruct = dccp_v6_sk_destruct; } return err; } -static void dccp_v6_destroy_sock(struct sock *sk) -{ - dccp_destroy_sock(sk); - inet6_destroy_sock(sk); -} - static struct timewait_sock_ops dccp6_timewait_sock_ops = { .twsk_obj_size = sizeof(struct dccp6_timewait_sock), }; @@ -1045,7 +1046,7 @@ static struct proto dccp_v6_prot = { .accept = inet_csk_accept, .get_port = inet_csk_get_port, .shutdown = dccp_shutdown, - .destroy = dccp_v6_destroy_sock, + .destroy = dccp_destroy_sock, .orphan_count = &dccp_orphan_count, .max_header = MAX_DCCP_HEADER, .obj_size = sizeof(struct dccp6_sock), diff --git a/net/dccp/options.c b/net/dccp/options.c index 4e40db017e198b15f74df56f02a66aa4cbe3f28e..3c464d63b0bb3ceb6d7924f065ef9a20a9015d38 100644 --- a/net/dccp/options.c +++ b/net/dccp/options.c @@ -60,7 +60,7 @@ int dccp_parse_options(struct sock *sk, struct dccp_request_sock *dreq, (dh->dccph_doff * 4); struct dccp_options_received *opt_recv = &dp->dccps_options_received; unsigned char opt, len; - unsigned char *uninitialized_var(value); + unsigned char *value; u32 elapsed_time; __be32 opt_val; int rc; diff --git a/net/dccp/output.c b/net/dccp/output.c index 91a15b3c4915a31c40ab4ea3901b4ee4d9cef1a0..d872dd1cfb5e07236c813ada86cec2cc691cbb6e 100644 --- a/net/dccp/output.c +++ b/net/dccp/output.c @@ -189,7 +189,7 @@ unsigned int dccp_sync_mss(struct sock *sk, u32 pmtu) /* And store cached results */ icsk->icsk_pmtu_cookie = pmtu; - dp->dccps_mss_cache = cur_mps; + WRITE_ONCE(dp->dccps_mss_cache, cur_mps); return cur_mps; } diff --git a/net/dccp/proto.c b/net/dccp/proto.c index dbbcf50aea35db79a409cf4b62f7ea73d3eeeceb..c4ea0159ce2e86bf09c10309416d11c9af00f5fd 100644 --- a/net/dccp/proto.c +++ b/net/dccp/proto.c @@ -174,12 +174,18 @@ const char *dccp_packet_name(const int type) EXPORT_SYMBOL_GPL(dccp_packet_name); -static void dccp_sk_destruct(struct sock *sk) +void dccp_destruct_common(struct sock *sk) { struct dccp_sock *dp = dccp_sk(sk); ccid_hc_tx_delete(dp->dccps_hc_tx_ccid, sk); dp->dccps_hc_tx_ccid = NULL; +} +EXPORT_SYMBOL_GPL(dccp_destruct_common); + +static void dccp_sk_destruct(struct sock *sk) +{ + dccp_destruct_common(sk); inet_sock_destruct(sk); } @@ -322,11 +328,15 @@ EXPORT_SYMBOL_GPL(dccp_disconnect); __poll_t dccp_poll(struct file *file, struct socket *sock, poll_table *wait) { - __poll_t mask; struct sock *sk = sock->sk; + __poll_t mask; + u8 shutdown; + int state; sock_poll_wait(file, sock, wait); - if (sk->sk_state == DCCP_LISTEN) + + state = inet_sk_state_load(sk); + if (state == DCCP_LISTEN) return inet_csk_listen_poll(sk); /* Socket is not locked. We are protected from async events @@ -335,20 +345,21 @@ __poll_t dccp_poll(struct file *file, struct socket *sock, */ mask = 0; - if (sk->sk_err) + if (READ_ONCE(sk->sk_err)) mask = EPOLLERR; + shutdown = READ_ONCE(sk->sk_shutdown); - if (sk->sk_shutdown == SHUTDOWN_MASK || sk->sk_state == DCCP_CLOSED) + if (shutdown == SHUTDOWN_MASK || state == DCCP_CLOSED) mask |= EPOLLHUP; - if (sk->sk_shutdown & RCV_SHUTDOWN) + if (shutdown & RCV_SHUTDOWN) mask |= EPOLLIN | EPOLLRDNORM | EPOLLRDHUP; /* Connected? */ - if ((1 << sk->sk_state) & ~(DCCPF_REQUESTING | DCCPF_RESPOND)) { + if ((1 << state) & ~(DCCPF_REQUESTING | DCCPF_RESPOND)) { if (atomic_read(&sk->sk_rmem_alloc) > 0) mask |= EPOLLIN | EPOLLRDNORM; - if (!(sk->sk_shutdown & SEND_SHUTDOWN)) { + if (!(shutdown & SEND_SHUTDOWN)) { if (sk_stream_is_writeable(sk)) { mask |= EPOLLOUT | EPOLLWRNORM; } else { /* send SIGIO later */ @@ -366,7 +377,6 @@ __poll_t dccp_poll(struct file *file, struct socket *sock, } return mask; } - EXPORT_SYMBOL_GPL(dccp_poll); int dccp_ioctl(struct sock *sk, int cmd, unsigned long arg) @@ -642,7 +652,7 @@ static int do_dccp_getsockopt(struct sock *sk, int level, int optname, return dccp_getsockopt_service(sk, len, (__be32 __user *)optval, optlen); case DCCP_SOCKOPT_GET_CUR_MPS: - val = dp->dccps_mss_cache; + val = READ_ONCE(dp->dccps_mss_cache); break; case DCCP_SOCKOPT_AVAILABLE_CCIDS: return ccid_getsockopt_builtin_ccids(sk, len, optval, optlen); @@ -764,7 +774,7 @@ int dccp_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) trace_dccp_probe(sk, len); - if (len > dp->dccps_mss_cache) + if (len > READ_ONCE(dp->dccps_mss_cache)) return -EMSGSIZE; lock_sock(sk); @@ -797,6 +807,12 @@ int dccp_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) goto out_discard; } + /* We need to check dccps_mss_cache after socket is locked. */ + if (len > dp->dccps_mss_cache) { + rc = -EMSGSIZE; + goto out_discard; + } + skb_reserve(skb, sk->sk_prot->max_header); rc = memcpy_from_msg(skb_put(skb, len), msg, len); if (rc != 0) diff --git a/net/decnet/Kconfig b/net/decnet/Kconfig deleted file mode 100644 index dcc74956badd93ca4b948f7b9fea2d540a7f9083..0000000000000000000000000000000000000000 --- a/net/decnet/Kconfig +++ /dev/null @@ -1,42 +0,0 @@ -# -# DECnet configuration -# -config DECNET - tristate "DECnet Support" - ---help--- - The DECnet networking protocol was used in many products made by - Digital (now Compaq). It provides reliable stream and sequenced - packet communications over which run a variety of services similar - to those which run over TCP/IP. - - To find some tools to use with the kernel layer support, please - look at Patrick Caulfield's web site: - . - - More detailed documentation is available in - . - - Be sure to say Y to "/proc file system support" and "Sysctl support" - below when using DECnet, since you will need sysctl support to aid - in configuration at run time. - - The DECnet code is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module is called decnet. - -config DECNET_ROUTER - bool "DECnet: router support" - depends on DECNET - select FIB_RULES - ---help--- - Add support for turning your DECnet Endnode into a level 1 or 2 - router. This is an experimental, but functional option. If you - do say Y here, then make sure that you also say Y to "Kernel/User - network link driver", "Routing messages" and "Network packet - filtering". The first two are required to allow configuration via - rtnetlink (you will need Alexey Kuznetsov's iproute2 package - from ). The "Network packet - filtering" option will be required for the forthcoming routing daemon - to work. - - See for more information. diff --git a/net/decnet/Makefile b/net/decnet/Makefile deleted file mode 100644 index 07b38e441b2d0f6a6fb54ad35b838e0311cce22f..0000000000000000000000000000000000000000 --- a/net/decnet/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -obj-$(CONFIG_DECNET) += decnet.o - -decnet-y := af_decnet.o dn_nsp_in.o dn_nsp_out.o \ - dn_route.o dn_dev.o dn_neigh.o dn_timer.o -decnet-$(CONFIG_DECNET_ROUTER) += dn_fib.o dn_rules.o dn_table.o -decnet-y += sysctl_net_decnet.o - -obj-$(CONFIG_NETFILTER) += netfilter/ diff --git a/net/decnet/README b/net/decnet/README deleted file mode 100644 index 60e7ec88c81fd14a7d1f14ce51b34681fe279f50..0000000000000000000000000000000000000000 --- a/net/decnet/README +++ /dev/null @@ -1,8 +0,0 @@ - Linux DECnet Project - ====================== - -The documentation for this kernel subsystem is available in the -Documentation/networking subdirectory of this distribution and also -on line at http://www.chygwyn.com/DECnet/ - -Steve Whitehouse diff --git a/net/decnet/af_decnet.c b/net/decnet/af_decnet.c deleted file mode 100644 index cc70771059698474bbd515b581cd3548bedce6ff..0000000000000000000000000000000000000000 --- a/net/decnet/af_decnet.c +++ /dev/null @@ -1,2408 +0,0 @@ - -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Socket Layer Interface - * - * Authors: Eduardo Marcelo Serrat - * Patrick Caulfield - * - * Changes: - * Steve Whitehouse: Copied from Eduardo Serrat and Patrick Caulfield's - * version of the code. Original copyright preserved - * below. - * Steve Whitehouse: Some bug fixes, cleaning up some code to make it - * compatible with my routing layer. - * Steve Whitehouse: Merging changes from Eduardo Serrat and Patrick - * Caulfield. - * Steve Whitehouse: Further bug fixes, checking module code still works - * with new routing layer. - * Steve Whitehouse: Additional set/get_sockopt() calls. - * Steve Whitehouse: Fixed TIOCINQ ioctl to be same as Eduardo's new - * code. - * Steve Whitehouse: recvmsg() changed to try and behave in a POSIX like - * way. Didn't manage it entirely, but its better. - * Steve Whitehouse: ditto for sendmsg(). - * Steve Whitehouse: A selection of bug fixes to various things. - * Steve Whitehouse: Added TIOCOUTQ ioctl. - * Steve Whitehouse: Fixes to username2sockaddr & sockaddr2username. - * Steve Whitehouse: Fixes to connect() error returns. - * Patrick Caulfield: Fixes to delayed acceptance logic. - * David S. Miller: New socket locking - * Steve Whitehouse: Socket list hashing/locking - * Arnaldo C. Melo: use capable, not suser - * Steve Whitehouse: Removed unused code. Fix to use sk->allocation - * when required. - * Patrick Caulfield: /proc/net/decnet now has object name/number - * Steve Whitehouse: Fixed local port allocation, hashed sk list - * Matthew Wilcox: Fixes for dn_ioctl() - * Steve Whitehouse: New connect/accept logic to allow timeouts and - * prepare for sendpage etc. - */ - - -/****************************************************************************** - (c) 1995-1998 E.M. Serrat emserrat@geocities.com - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - -HISTORY: - -Version Kernel Date Author/Comments -------- ------ ---- --------------- -Version 0.0.1 2.0.30 01-dic-97 Eduardo Marcelo Serrat - (emserrat@geocities.com) - - First Development of DECnet Socket La- - yer for Linux. Only supports outgoing - connections. - -Version 0.0.2 2.1.105 20-jun-98 Patrick J. Caulfield - (patrick@pandh.demon.co.uk) - - Port to new kernel development version. - -Version 0.0.3 2.1.106 25-jun-98 Eduardo Marcelo Serrat - (emserrat@geocities.com) - _ - Added support for incoming connections - so we can start developing server apps - on Linux. - - - Module Support -Version 0.0.4 2.1.109 21-jul-98 Eduardo Marcelo Serrat - (emserrat@geocities.com) - _ - Added support for X11R6.4. Now we can - use DECnet transport for X on Linux!!! - - -Version 0.0.5 2.1.110 01-aug-98 Eduardo Marcelo Serrat - (emserrat@geocities.com) - Removed bugs on flow control - Removed bugs on incoming accessdata - order - - -Version 0.0.6 2.1.110 07-aug-98 Eduardo Marcelo Serrat - dn_recvmsg fixes - - Patrick J. Caulfield - dn_bind fixes -*******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct dn_sock { - struct sock sk; - struct dn_scp scp; -}; - -static void dn_keepalive(struct sock *sk); - -#define DN_SK_HASH_SHIFT 8 -#define DN_SK_HASH_SIZE (1 << DN_SK_HASH_SHIFT) -#define DN_SK_HASH_MASK (DN_SK_HASH_SIZE - 1) - - -static const struct proto_ops dn_proto_ops; -static DEFINE_RWLOCK(dn_hash_lock); -static struct hlist_head dn_sk_hash[DN_SK_HASH_SIZE]; -static struct hlist_head dn_wild_sk; -static atomic_long_t decnet_memory_allocated; - -static int __dn_setsockopt(struct socket *sock, int level, int optname, char __user *optval, unsigned int optlen, int flags); -static int __dn_getsockopt(struct socket *sock, int level, int optname, char __user *optval, int __user *optlen, int flags); - -static struct hlist_head *dn_find_list(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - if (scp->addr.sdn_flags & SDF_WILD) - return hlist_empty(&dn_wild_sk) ? &dn_wild_sk : NULL; - - return &dn_sk_hash[le16_to_cpu(scp->addrloc) & DN_SK_HASH_MASK]; -} - -/* - * Valid ports are those greater than zero and not already in use. - */ -static int check_port(__le16 port) -{ - struct sock *sk; - - if (port == 0) - return -1; - - sk_for_each(sk, &dn_sk_hash[le16_to_cpu(port) & DN_SK_HASH_MASK]) { - struct dn_scp *scp = DN_SK(sk); - if (scp->addrloc == port) - return -1; - } - return 0; -} - -static unsigned short port_alloc(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); -static unsigned short port = 0x2000; - unsigned short i_port = port; - - while(check_port(cpu_to_le16(++port)) != 0) { - if (port == i_port) - return 0; - } - - scp->addrloc = cpu_to_le16(port); - - return 1; -} - -/* - * Since this is only ever called from user - * level, we don't need a write_lock() version - * of this. - */ -static int dn_hash_sock(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - struct hlist_head *list; - int rv = -EUSERS; - - BUG_ON(sk_hashed(sk)); - - write_lock_bh(&dn_hash_lock); - - if (!scp->addrloc && !port_alloc(sk)) - goto out; - - rv = -EADDRINUSE; - if ((list = dn_find_list(sk)) == NULL) - goto out; - - sk_add_node(sk, list); - rv = 0; -out: - write_unlock_bh(&dn_hash_lock); - return rv; -} - -static void dn_unhash_sock(struct sock *sk) -{ - write_lock(&dn_hash_lock); - sk_del_node_init(sk); - write_unlock(&dn_hash_lock); -} - -static void dn_unhash_sock_bh(struct sock *sk) -{ - write_lock_bh(&dn_hash_lock); - sk_del_node_init(sk); - write_unlock_bh(&dn_hash_lock); -} - -static struct hlist_head *listen_hash(struct sockaddr_dn *addr) -{ - int i; - unsigned int hash = addr->sdn_objnum; - - if (hash == 0) { - hash = addr->sdn_objnamel; - for(i = 0; i < le16_to_cpu(addr->sdn_objnamel); i++) { - hash ^= addr->sdn_objname[i]; - hash ^= (hash << 3); - } - } - - return &dn_sk_hash[hash & DN_SK_HASH_MASK]; -} - -/* - * Called to transform a socket from bound (i.e. with a local address) - * into a listening socket (doesn't need a local port number) and rehashes - * based upon the object name/number. - */ -static void dn_rehash_sock(struct sock *sk) -{ - struct hlist_head *list; - struct dn_scp *scp = DN_SK(sk); - - if (scp->addr.sdn_flags & SDF_WILD) - return; - - write_lock_bh(&dn_hash_lock); - sk_del_node_init(sk); - DN_SK(sk)->addrloc = 0; - list = listen_hash(&DN_SK(sk)->addr); - sk_add_node(sk, list); - write_unlock_bh(&dn_hash_lock); -} - -int dn_sockaddr2username(struct sockaddr_dn *sdn, unsigned char *buf, unsigned char type) -{ - int len = 2; - - *buf++ = type; - - switch (type) { - case 0: - *buf++ = sdn->sdn_objnum; - break; - case 1: - *buf++ = 0; - *buf++ = le16_to_cpu(sdn->sdn_objnamel); - memcpy(buf, sdn->sdn_objname, le16_to_cpu(sdn->sdn_objnamel)); - len = 3 + le16_to_cpu(sdn->sdn_objnamel); - break; - case 2: - memset(buf, 0, 5); - buf += 5; - *buf++ = le16_to_cpu(sdn->sdn_objnamel); - memcpy(buf, sdn->sdn_objname, le16_to_cpu(sdn->sdn_objnamel)); - len = 7 + le16_to_cpu(sdn->sdn_objnamel); - break; - } - - return len; -} - -/* - * On reception of usernames, we handle types 1 and 0 for destination - * addresses only. Types 2 and 4 are used for source addresses, but the - * UIC, GIC are ignored and they are both treated the same way. Type 3 - * is never used as I've no idea what its purpose might be or what its - * format is. - */ -int dn_username2sockaddr(unsigned char *data, int len, struct sockaddr_dn *sdn, unsigned char *fmt) -{ - unsigned char type; - int size = len; - int namel = 12; - - sdn->sdn_objnum = 0; - sdn->sdn_objnamel = cpu_to_le16(0); - memset(sdn->sdn_objname, 0, DN_MAXOBJL); - - if (len < 2) - return -1; - - len -= 2; - *fmt = *data++; - type = *data++; - - switch (*fmt) { - case 0: - sdn->sdn_objnum = type; - return 2; - case 1: - namel = 16; - break; - case 2: - len -= 4; - data += 4; - break; - case 4: - len -= 8; - data += 8; - break; - default: - return -1; - } - - len -= 1; - - if (len < 0) - return -1; - - sdn->sdn_objnamel = cpu_to_le16(*data++); - len -= le16_to_cpu(sdn->sdn_objnamel); - - if ((len < 0) || (le16_to_cpu(sdn->sdn_objnamel) > namel)) - return -1; - - memcpy(sdn->sdn_objname, data, le16_to_cpu(sdn->sdn_objnamel)); - - return size - len; -} - -struct sock *dn_sklist_find_listener(struct sockaddr_dn *addr) -{ - struct hlist_head *list = listen_hash(addr); - struct sock *sk; - - read_lock(&dn_hash_lock); - sk_for_each(sk, list) { - struct dn_scp *scp = DN_SK(sk); - if (sk->sk_state != TCP_LISTEN) - continue; - if (scp->addr.sdn_objnum) { - if (scp->addr.sdn_objnum != addr->sdn_objnum) - continue; - } else { - if (addr->sdn_objnum) - continue; - if (scp->addr.sdn_objnamel != addr->sdn_objnamel) - continue; - if (memcmp(scp->addr.sdn_objname, addr->sdn_objname, le16_to_cpu(addr->sdn_objnamel)) != 0) - continue; - } - sock_hold(sk); - read_unlock(&dn_hash_lock); - return sk; - } - - sk = sk_head(&dn_wild_sk); - if (sk) { - if (sk->sk_state == TCP_LISTEN) - sock_hold(sk); - else - sk = NULL; - } - - read_unlock(&dn_hash_lock); - return sk; -} - -struct sock *dn_find_by_skb(struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct sock *sk; - struct dn_scp *scp; - - read_lock(&dn_hash_lock); - sk_for_each(sk, &dn_sk_hash[le16_to_cpu(cb->dst_port) & DN_SK_HASH_MASK]) { - scp = DN_SK(sk); - if (cb->src != dn_saddr2dn(&scp->peer)) - continue; - if (cb->dst_port != scp->addrloc) - continue; - if (scp->addrrem && (cb->src_port != scp->addrrem)) - continue; - sock_hold(sk); - goto found; - } - sk = NULL; -found: - read_unlock(&dn_hash_lock); - return sk; -} - - - -static void dn_destruct(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - skb_queue_purge(&scp->data_xmit_queue); - skb_queue_purge(&scp->other_xmit_queue); - skb_queue_purge(&scp->other_receive_queue); - - dst_release(rcu_dereference_check(sk->sk_dst_cache, 1)); -} - -static unsigned long dn_memory_pressure; - -static void dn_enter_memory_pressure(struct sock *sk) -{ - if (!dn_memory_pressure) { - dn_memory_pressure = 1; - } -} - -static struct proto dn_proto = { - .name = "NSP", - .owner = THIS_MODULE, - .enter_memory_pressure = dn_enter_memory_pressure, - .memory_pressure = &dn_memory_pressure, - .memory_allocated = &decnet_memory_allocated, - .sysctl_mem = sysctl_decnet_mem, - .sysctl_wmem = sysctl_decnet_wmem, - .sysctl_rmem = sysctl_decnet_rmem, - .max_header = DN_MAX_NSP_DATA_HEADER + 64, - .obj_size = sizeof(struct dn_sock), -}; - -static struct sock *dn_alloc_sock(struct net *net, struct socket *sock, gfp_t gfp, int kern) -{ - struct dn_scp *scp; - struct sock *sk = sk_alloc(net, PF_DECnet, gfp, &dn_proto, kern); - - if (!sk) - goto out; - - if (sock) - sock->ops = &dn_proto_ops; - sock_init_data(sock, sk); - - sk->sk_backlog_rcv = dn_nsp_backlog_rcv; - sk->sk_destruct = dn_destruct; - sk->sk_no_check_tx = 1; - sk->sk_family = PF_DECnet; - sk->sk_protocol = 0; - sk->sk_allocation = gfp; - sk->sk_sndbuf = sysctl_decnet_wmem[1]; - sk->sk_rcvbuf = sysctl_decnet_rmem[1]; - - /* Initialization of DECnet Session Control Port */ - scp = DN_SK(sk); - scp->state = DN_O; /* Open */ - scp->numdat = 1; /* Next data seg to tx */ - scp->numoth = 1; /* Next oth data to tx */ - scp->ackxmt_dat = 0; /* Last data seg ack'ed */ - scp->ackxmt_oth = 0; /* Last oth data ack'ed */ - scp->ackrcv_dat = 0; /* Highest data ack recv*/ - scp->ackrcv_oth = 0; /* Last oth data ack rec*/ - scp->flowrem_sw = DN_SEND; - scp->flowloc_sw = DN_SEND; - scp->flowrem_dat = 0; - scp->flowrem_oth = 1; - scp->flowloc_dat = 0; - scp->flowloc_oth = 1; - scp->services_rem = 0; - scp->services_loc = 1 | NSP_FC_NONE; - scp->info_rem = 0; - scp->info_loc = 0x03; /* NSP version 4.1 */ - scp->segsize_rem = 230 - DN_MAX_NSP_DATA_HEADER; /* Default: Updated by remote segsize */ - scp->nonagle = 0; - scp->multi_ireq = 1; - scp->accept_mode = ACC_IMMED; - scp->addr.sdn_family = AF_DECnet; - scp->peer.sdn_family = AF_DECnet; - scp->accessdata.acc_accl = 5; - memcpy(scp->accessdata.acc_acc, "LINUX", 5); - - scp->max_window = NSP_MAX_WINDOW; - scp->snd_window = NSP_MIN_WINDOW; - scp->nsp_srtt = NSP_INITIAL_SRTT; - scp->nsp_rttvar = NSP_INITIAL_RTTVAR; - scp->nsp_rxtshift = 0; - - skb_queue_head_init(&scp->data_xmit_queue); - skb_queue_head_init(&scp->other_xmit_queue); - skb_queue_head_init(&scp->other_receive_queue); - - scp->persist = 0; - scp->persist_fxn = NULL; - scp->keepalive = 10 * HZ; - scp->keepalive_fxn = dn_keepalive; - - dn_start_slow_timer(sk); -out: - return sk; -} - -/* - * Keepalive timer. - * FIXME: Should respond to SO_KEEPALIVE etc. - */ -static void dn_keepalive(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - /* - * By checking the other_data transmit queue is empty - * we are double checking that we are not sending too - * many of these keepalive frames. - */ - if (skb_queue_empty(&scp->other_xmit_queue)) - dn_nsp_send_link(sk, DN_NOCHANGE, 0); -} - - -/* - * Timer for shutdown/destroyed sockets. - * When socket is dead & no packets have been sent for a - * certain amount of time, they are removed by this - * routine. Also takes care of sending out DI & DC - * frames at correct times. - */ -int dn_destroy_timer(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - scp->persist = dn_nsp_persist(sk); - - switch (scp->state) { - case DN_DI: - dn_nsp_send_disc(sk, NSP_DISCINIT, 0, GFP_ATOMIC); - if (scp->nsp_rxtshift >= decnet_di_count) - scp->state = DN_CN; - return 0; - - case DN_DR: - dn_nsp_send_disc(sk, NSP_DISCINIT, 0, GFP_ATOMIC); - if (scp->nsp_rxtshift >= decnet_dr_count) - scp->state = DN_DRC; - return 0; - - case DN_DN: - if (scp->nsp_rxtshift < decnet_dn_count) { - /* printk(KERN_DEBUG "dn_destroy_timer: DN\n"); */ - dn_nsp_send_disc(sk, NSP_DISCCONF, NSP_REASON_DC, - GFP_ATOMIC); - return 0; - } - } - - scp->persist = (HZ * decnet_time_wait); - - if (sk->sk_socket) - return 0; - - if (time_after_eq(jiffies, scp->stamp + HZ * decnet_time_wait)) { - dn_unhash_sock(sk); - sock_put(sk); - return 1; - } - - return 0; -} - -static void dn_destroy_sock(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - scp->nsp_rxtshift = 0; /* reset back off */ - - if (sk->sk_socket) { - if (sk->sk_socket->state != SS_UNCONNECTED) - sk->sk_socket->state = SS_DISCONNECTING; - } - - sk->sk_state = TCP_CLOSE; - - switch (scp->state) { - case DN_DN: - dn_nsp_send_disc(sk, NSP_DISCCONF, NSP_REASON_DC, - sk->sk_allocation); - scp->persist_fxn = dn_destroy_timer; - scp->persist = dn_nsp_persist(sk); - break; - case DN_CR: - scp->state = DN_DR; - goto disc_reject; - case DN_RUN: - scp->state = DN_DI; - /* fall through */ - case DN_DI: - case DN_DR: -disc_reject: - dn_nsp_send_disc(sk, NSP_DISCINIT, 0, sk->sk_allocation); - /* fall through */ - case DN_NC: - case DN_NR: - case DN_RJ: - case DN_DIC: - case DN_CN: - case DN_DRC: - case DN_CI: - case DN_CD: - scp->persist_fxn = dn_destroy_timer; - scp->persist = dn_nsp_persist(sk); - break; - default: - printk(KERN_DEBUG "DECnet: dn_destroy_sock passed socket in invalid state\n"); - /* fall through */ - case DN_O: - dn_stop_slow_timer(sk); - - dn_unhash_sock_bh(sk); - sock_put(sk); - - break; - } -} - -char *dn_addr2asc(__u16 addr, char *buf) -{ - unsigned short node, area; - - node = addr & 0x03ff; - area = addr >> 10; - sprintf(buf, "%hd.%hd", area, node); - - return buf; -} - - - -static int dn_create(struct net *net, struct socket *sock, int protocol, - int kern) -{ - struct sock *sk; - - if (protocol < 0 || protocol > SK_PROTOCOL_MAX) - return -EINVAL; - - if (!net_eq(net, &init_net)) - return -EAFNOSUPPORT; - - switch (sock->type) { - case SOCK_SEQPACKET: - if (protocol != DNPROTO_NSP) - return -EPROTONOSUPPORT; - break; - case SOCK_STREAM: - break; - default: - return -ESOCKTNOSUPPORT; - } - - - if ((sk = dn_alloc_sock(net, sock, GFP_KERNEL, kern)) == NULL) - return -ENOBUFS; - - sk->sk_protocol = protocol; - - return 0; -} - - -static int -dn_release(struct socket *sock) -{ - struct sock *sk = sock->sk; - - if (sk) { - sock_orphan(sk); - sock_hold(sk); - lock_sock(sk); - dn_destroy_sock(sk); - release_sock(sk); - sock_put(sk); - } - - return 0; -} - -static int dn_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - struct sockaddr_dn *saddr = (struct sockaddr_dn *)uaddr; - struct net_device *dev, *ldev; - int rv; - - if (addr_len != sizeof(struct sockaddr_dn)) - return -EINVAL; - - if (saddr->sdn_family != AF_DECnet) - return -EINVAL; - - if (le16_to_cpu(saddr->sdn_nodeaddrl) && (le16_to_cpu(saddr->sdn_nodeaddrl) != 2)) - return -EINVAL; - - if (le16_to_cpu(saddr->sdn_objnamel) > DN_MAXOBJL) - return -EINVAL; - - if (saddr->sdn_flags & ~SDF_WILD) - return -EINVAL; - - if (!capable(CAP_NET_BIND_SERVICE) && (saddr->sdn_objnum || - (saddr->sdn_flags & SDF_WILD))) - return -EACCES; - - if (!(saddr->sdn_flags & SDF_WILD)) { - if (le16_to_cpu(saddr->sdn_nodeaddrl)) { - rcu_read_lock(); - ldev = NULL; - for_each_netdev_rcu(&init_net, dev) { - if (!dev->dn_ptr) - continue; - if (dn_dev_islocal(dev, dn_saddr2dn(saddr))) { - ldev = dev; - break; - } - } - rcu_read_unlock(); - if (ldev == NULL) - return -EADDRNOTAVAIL; - } - } - - rv = -EINVAL; - lock_sock(sk); - if (sock_flag(sk, SOCK_ZAPPED)) { - memcpy(&scp->addr, saddr, addr_len); - sock_reset_flag(sk, SOCK_ZAPPED); - - rv = dn_hash_sock(sk); - if (rv) - sock_set_flag(sk, SOCK_ZAPPED); - } - release_sock(sk); - - return rv; -} - - -static int dn_auto_bind(struct socket *sock) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - int rv; - - sock_reset_flag(sk, SOCK_ZAPPED); - - scp->addr.sdn_flags = 0; - scp->addr.sdn_objnum = 0; - - /* - * This stuff is to keep compatibility with Eduardo's - * patch. I hope I can dispense with it shortly... - */ - if ((scp->accessdata.acc_accl != 0) && - (scp->accessdata.acc_accl <= 12)) { - - scp->addr.sdn_objnamel = cpu_to_le16(scp->accessdata.acc_accl); - memcpy(scp->addr.sdn_objname, scp->accessdata.acc_acc, le16_to_cpu(scp->addr.sdn_objnamel)); - - scp->accessdata.acc_accl = 0; - memset(scp->accessdata.acc_acc, 0, 40); - } - /* End of compatibility stuff */ - - scp->addr.sdn_add.a_len = cpu_to_le16(2); - rv = dn_dev_bind_default((__le16 *)scp->addr.sdn_add.a_addr); - if (rv == 0) { - rv = dn_hash_sock(sk); - if (rv) - sock_set_flag(sk, SOCK_ZAPPED); - } - - return rv; -} - -static int dn_confirm_accept(struct sock *sk, long *timeo, gfp_t allocation) -{ - struct dn_scp *scp = DN_SK(sk); - DEFINE_WAIT_FUNC(wait, woken_wake_function); - int err; - - if (scp->state != DN_CR) - return -EINVAL; - - scp->state = DN_CC; - scp->segsize_loc = dst_metric_advmss(__sk_dst_get(sk)); - dn_send_conn_conf(sk, allocation); - - add_wait_queue(sk_sleep(sk), &wait); - for(;;) { - release_sock(sk); - if (scp->state == DN_CC) - *timeo = wait_woken(&wait, TASK_INTERRUPTIBLE, *timeo); - lock_sock(sk); - err = 0; - if (scp->state == DN_RUN) - break; - err = sock_error(sk); - if (err) - break; - err = sock_intr_errno(*timeo); - if (signal_pending(current)) - break; - err = -EAGAIN; - if (!*timeo) - break; - } - remove_wait_queue(sk_sleep(sk), &wait); - if (err == 0) { - sk->sk_socket->state = SS_CONNECTED; - } else if (scp->state != DN_CC) { - sk->sk_socket->state = SS_UNCONNECTED; - } - return err; -} - -static int dn_wait_run(struct sock *sk, long *timeo) -{ - struct dn_scp *scp = DN_SK(sk); - DEFINE_WAIT_FUNC(wait, woken_wake_function); - int err = 0; - - if (scp->state == DN_RUN) - goto out; - - if (!*timeo) - return -EALREADY; - - add_wait_queue(sk_sleep(sk), &wait); - for(;;) { - release_sock(sk); - if (scp->state == DN_CI || scp->state == DN_CC) - *timeo = wait_woken(&wait, TASK_INTERRUPTIBLE, *timeo); - lock_sock(sk); - err = 0; - if (scp->state == DN_RUN) - break; - err = sock_error(sk); - if (err) - break; - err = sock_intr_errno(*timeo); - if (signal_pending(current)) - break; - err = -ETIMEDOUT; - if (!*timeo) - break; - } - remove_wait_queue(sk_sleep(sk), &wait); -out: - if (err == 0) { - sk->sk_socket->state = SS_CONNECTED; - } else if (scp->state != DN_CI && scp->state != DN_CC) { - sk->sk_socket->state = SS_UNCONNECTED; - } - return err; -} - -static int __dn_connect(struct sock *sk, struct sockaddr_dn *addr, int addrlen, long *timeo, int flags) -{ - struct socket *sock = sk->sk_socket; - struct dn_scp *scp = DN_SK(sk); - int err = -EISCONN; - struct flowidn fld; - struct dst_entry *dst; - - if (sock->state == SS_CONNECTED) - goto out; - - if (sock->state == SS_CONNECTING) { - err = 0; - if (scp->state == DN_RUN) { - sock->state = SS_CONNECTED; - goto out; - } - err = -ECONNREFUSED; - if (scp->state != DN_CI && scp->state != DN_CC) { - sock->state = SS_UNCONNECTED; - goto out; - } - return dn_wait_run(sk, timeo); - } - - err = -EINVAL; - if (scp->state != DN_O) - goto out; - - if (addr == NULL || addrlen != sizeof(struct sockaddr_dn)) - goto out; - if (addr->sdn_family != AF_DECnet) - goto out; - if (addr->sdn_flags & SDF_WILD) - goto out; - - if (sock_flag(sk, SOCK_ZAPPED)) { - err = dn_auto_bind(sk->sk_socket); - if (err) - goto out; - } - - memcpy(&scp->peer, addr, sizeof(struct sockaddr_dn)); - - err = -EHOSTUNREACH; - memset(&fld, 0, sizeof(fld)); - fld.flowidn_oif = sk->sk_bound_dev_if; - fld.daddr = dn_saddr2dn(&scp->peer); - fld.saddr = dn_saddr2dn(&scp->addr); - dn_sk_ports_copy(&fld, scp); - fld.flowidn_proto = DNPROTO_NSP; - if (dn_route_output_sock(&sk->sk_dst_cache, &fld, sk, flags) < 0) - goto out; - dst = __sk_dst_get(sk); - sk->sk_route_caps = dst->dev->features; - sock->state = SS_CONNECTING; - scp->state = DN_CI; - scp->segsize_loc = dst_metric_advmss(dst); - - dn_nsp_send_conninit(sk, NSP_CI); - err = -EINPROGRESS; - if (*timeo) { - err = dn_wait_run(sk, timeo); - } -out: - return err; -} - -static int dn_connect(struct socket *sock, struct sockaddr *uaddr, int addrlen, int flags) -{ - struct sockaddr_dn *addr = (struct sockaddr_dn *)uaddr; - struct sock *sk = sock->sk; - int err; - long timeo = sock_sndtimeo(sk, flags & O_NONBLOCK); - - lock_sock(sk); - err = __dn_connect(sk, addr, addrlen, &timeo, 0); - release_sock(sk); - - return err; -} - -static inline int dn_check_state(struct sock *sk, struct sockaddr_dn *addr, int addrlen, long *timeo, int flags) -{ - struct dn_scp *scp = DN_SK(sk); - - switch (scp->state) { - case DN_RUN: - return 0; - case DN_CR: - return dn_confirm_accept(sk, timeo, sk->sk_allocation); - case DN_CI: - case DN_CC: - return dn_wait_run(sk, timeo); - case DN_O: - return __dn_connect(sk, addr, addrlen, timeo, flags); - } - - return -EINVAL; -} - - -static void dn_access_copy(struct sk_buff *skb, struct accessdata_dn *acc) -{ - unsigned char *ptr = skb->data; - - acc->acc_userl = *ptr++; - memcpy(&acc->acc_user, ptr, acc->acc_userl); - ptr += acc->acc_userl; - - acc->acc_passl = *ptr++; - memcpy(&acc->acc_pass, ptr, acc->acc_passl); - ptr += acc->acc_passl; - - acc->acc_accl = *ptr++; - memcpy(&acc->acc_acc, ptr, acc->acc_accl); - - skb_pull(skb, acc->acc_accl + acc->acc_passl + acc->acc_userl + 3); - -} - -static void dn_user_copy(struct sk_buff *skb, struct optdata_dn *opt) -{ - unsigned char *ptr = skb->data; - u16 len = *ptr++; /* yes, it's 8bit on the wire */ - - BUG_ON(len > 16); /* we've checked the contents earlier */ - opt->opt_optl = cpu_to_le16(len); - opt->opt_status = 0; - memcpy(opt->opt_data, ptr, len); - skb_pull(skb, len + 1); -} - -static struct sk_buff *dn_wait_for_connect(struct sock *sk, long *timeo) -{ - DEFINE_WAIT_FUNC(wait, woken_wake_function); - struct sk_buff *skb = NULL; - int err = 0; - - add_wait_queue(sk_sleep(sk), &wait); - for(;;) { - release_sock(sk); - skb = skb_dequeue(&sk->sk_receive_queue); - if (skb == NULL) { - *timeo = wait_woken(&wait, TASK_INTERRUPTIBLE, *timeo); - skb = skb_dequeue(&sk->sk_receive_queue); - } - lock_sock(sk); - if (skb != NULL) - break; - err = -EINVAL; - if (sk->sk_state != TCP_LISTEN) - break; - err = sock_intr_errno(*timeo); - if (signal_pending(current)) - break; - err = -EAGAIN; - if (!*timeo) - break; - } - remove_wait_queue(sk_sleep(sk), &wait); - - return skb == NULL ? ERR_PTR(err) : skb; -} - -static int dn_accept(struct socket *sock, struct socket *newsock, int flags, - bool kern) -{ - struct sock *sk = sock->sk, *newsk; - struct sk_buff *skb = NULL; - struct dn_skb_cb *cb; - unsigned char menuver; - int err = 0; - unsigned char type; - long timeo = sock_rcvtimeo(sk, flags & O_NONBLOCK); - struct dst_entry *dst; - - lock_sock(sk); - - if (sk->sk_state != TCP_LISTEN || DN_SK(sk)->state != DN_O) { - release_sock(sk); - return -EINVAL; - } - - skb = skb_dequeue(&sk->sk_receive_queue); - if (skb == NULL) { - skb = dn_wait_for_connect(sk, &timeo); - if (IS_ERR(skb)) { - release_sock(sk); - return PTR_ERR(skb); - } - } - - cb = DN_SKB_CB(skb); - sk->sk_ack_backlog--; - newsk = dn_alloc_sock(sock_net(sk), newsock, sk->sk_allocation, kern); - if (newsk == NULL) { - release_sock(sk); - kfree_skb(skb); - return -ENOBUFS; - } - release_sock(sk); - - dst = skb_dst(skb); - sk_dst_set(newsk, dst); - skb_dst_set(skb, NULL); - - DN_SK(newsk)->state = DN_CR; - DN_SK(newsk)->addrrem = cb->src_port; - DN_SK(newsk)->services_rem = cb->services; - DN_SK(newsk)->info_rem = cb->info; - DN_SK(newsk)->segsize_rem = cb->segsize; - DN_SK(newsk)->accept_mode = DN_SK(sk)->accept_mode; - - if (DN_SK(newsk)->segsize_rem < 230) - DN_SK(newsk)->segsize_rem = 230; - - if ((DN_SK(newsk)->services_rem & NSP_FC_MASK) == NSP_FC_NONE) - DN_SK(newsk)->max_window = decnet_no_fc_max_cwnd; - - newsk->sk_state = TCP_LISTEN; - memcpy(&(DN_SK(newsk)->addr), &(DN_SK(sk)->addr), sizeof(struct sockaddr_dn)); - - /* - * If we are listening on a wild socket, we don't want - * the newly created socket on the wrong hash queue. - */ - DN_SK(newsk)->addr.sdn_flags &= ~SDF_WILD; - - skb_pull(skb, dn_username2sockaddr(skb->data, skb->len, &(DN_SK(newsk)->addr), &type)); - skb_pull(skb, dn_username2sockaddr(skb->data, skb->len, &(DN_SK(newsk)->peer), &type)); - *(__le16 *)(DN_SK(newsk)->peer.sdn_add.a_addr) = cb->src; - *(__le16 *)(DN_SK(newsk)->addr.sdn_add.a_addr) = cb->dst; - - menuver = *skb->data; - skb_pull(skb, 1); - - if (menuver & DN_MENUVER_ACC) - dn_access_copy(skb, &(DN_SK(newsk)->accessdata)); - - if (menuver & DN_MENUVER_USR) - dn_user_copy(skb, &(DN_SK(newsk)->conndata_in)); - - if (menuver & DN_MENUVER_PRX) - DN_SK(newsk)->peer.sdn_flags |= SDF_PROXY; - - if (menuver & DN_MENUVER_UIC) - DN_SK(newsk)->peer.sdn_flags |= SDF_UICPROXY; - - kfree_skb(skb); - - memcpy(&(DN_SK(newsk)->conndata_out), &(DN_SK(sk)->conndata_out), - sizeof(struct optdata_dn)); - memcpy(&(DN_SK(newsk)->discdata_out), &(DN_SK(sk)->discdata_out), - sizeof(struct optdata_dn)); - - lock_sock(newsk); - err = dn_hash_sock(newsk); - if (err == 0) { - sock_reset_flag(newsk, SOCK_ZAPPED); - dn_send_conn_ack(newsk); - - /* - * Here we use sk->sk_allocation since although the conn conf is - * for the newsk, the context is the old socket. - */ - if (DN_SK(newsk)->accept_mode == ACC_IMMED) - err = dn_confirm_accept(newsk, &timeo, - sk->sk_allocation); - } - release_sock(newsk); - return err; -} - - -static int dn_getname(struct socket *sock, struct sockaddr *uaddr,int peer) -{ - struct sockaddr_dn *sa = (struct sockaddr_dn *)uaddr; - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - - lock_sock(sk); - - if (peer) { - if ((sock->state != SS_CONNECTED && - sock->state != SS_CONNECTING) && - scp->accept_mode == ACC_IMMED) { - release_sock(sk); - return -ENOTCONN; - } - - memcpy(sa, &scp->peer, sizeof(struct sockaddr_dn)); - } else { - memcpy(sa, &scp->addr, sizeof(struct sockaddr_dn)); - } - - release_sock(sk); - - return sizeof(struct sockaddr_dn); -} - - -static __poll_t dn_poll(struct file *file, struct socket *sock, poll_table *wait) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - __poll_t mask = datagram_poll(file, sock, wait); - - if (!skb_queue_empty_lockless(&scp->other_receive_queue)) - mask |= EPOLLRDBAND; - - return mask; -} - -static int dn_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - int err = -EOPNOTSUPP; - long amount = 0; - struct sk_buff *skb; - int val; - - switch(cmd) - { - case SIOCGIFADDR: - case SIOCSIFADDR: - return dn_dev_ioctl(cmd, (void __user *)arg); - - case SIOCATMARK: - lock_sock(sk); - val = !skb_queue_empty(&scp->other_receive_queue); - if (scp->state != DN_RUN) - val = -ENOTCONN; - release_sock(sk); - return val; - - case TIOCOUTQ: - amount = sk->sk_sndbuf - sk_wmem_alloc_get(sk); - if (amount < 0) - amount = 0; - err = put_user(amount, (int __user *)arg); - break; - - case TIOCINQ: - lock_sock(sk); - skb = skb_peek(&scp->other_receive_queue); - if (skb) { - amount = skb->len; - } else { - skb_queue_walk(&sk->sk_receive_queue, skb) - amount += skb->len; - } - release_sock(sk); - err = put_user(amount, (int __user *)arg); - break; - - default: - err = -ENOIOCTLCMD; - break; - } - - return err; -} - -static int dn_listen(struct socket *sock, int backlog) -{ - struct sock *sk = sock->sk; - int err = -EINVAL; - - lock_sock(sk); - - if (sock_flag(sk, SOCK_ZAPPED)) - goto out; - - if ((DN_SK(sk)->state != DN_O) || (sk->sk_state == TCP_LISTEN)) - goto out; - - sk->sk_max_ack_backlog = backlog; - sk->sk_ack_backlog = 0; - sk->sk_state = TCP_LISTEN; - err = 0; - dn_rehash_sock(sk); - -out: - release_sock(sk); - - return err; -} - - -static int dn_shutdown(struct socket *sock, int how) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - int err = -ENOTCONN; - - lock_sock(sk); - - if (sock->state == SS_UNCONNECTED) - goto out; - - err = 0; - if (sock->state == SS_DISCONNECTING) - goto out; - - err = -EINVAL; - if (scp->state == DN_O) - goto out; - - if (how != SHUT_RDWR) - goto out; - - sk->sk_shutdown = SHUTDOWN_MASK; - dn_destroy_sock(sk); - err = 0; - -out: - release_sock(sk); - - return err; -} - -static int dn_setsockopt(struct socket *sock, int level, int optname, char __user *optval, unsigned int optlen) -{ - struct sock *sk = sock->sk; - int err; - - lock_sock(sk); - err = __dn_setsockopt(sock, level, optname, optval, optlen, 0); - release_sock(sk); -#ifdef CONFIG_NETFILTER - /* we need to exclude all possible ENOPROTOOPTs except default case */ - if (err == -ENOPROTOOPT && optname != DSO_LINKINFO && - optname != DSO_STREAM && optname != DSO_SEQPACKET) - err = nf_setsockopt(sk, PF_DECnet, optname, optval, optlen); -#endif - - return err; -} - -static int __dn_setsockopt(struct socket *sock, int level,int optname, char __user *optval, unsigned int optlen, int flags) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - long timeo; - union { - struct optdata_dn opt; - struct accessdata_dn acc; - int mode; - unsigned long win; - int val; - unsigned char services; - unsigned char info; - } u; - int err; - - if (optlen && !optval) - return -EINVAL; - - if (optlen > sizeof(u)) - return -EINVAL; - - if (copy_from_user(&u, optval, optlen)) - return -EFAULT; - - switch (optname) { - case DSO_CONDATA: - if (sock->state == SS_CONNECTED) - return -EISCONN; - if ((scp->state != DN_O) && (scp->state != DN_CR)) - return -EINVAL; - - if (optlen != sizeof(struct optdata_dn)) - return -EINVAL; - - if (le16_to_cpu(u.opt.opt_optl) > 16) - return -EINVAL; - - memcpy(&scp->conndata_out, &u.opt, optlen); - break; - - case DSO_DISDATA: - if (sock->state != SS_CONNECTED && - scp->accept_mode == ACC_IMMED) - return -ENOTCONN; - - if (optlen != sizeof(struct optdata_dn)) - return -EINVAL; - - if (le16_to_cpu(u.opt.opt_optl) > 16) - return -EINVAL; - - memcpy(&scp->discdata_out, &u.opt, optlen); - break; - - case DSO_CONACCESS: - if (sock->state == SS_CONNECTED) - return -EISCONN; - if (scp->state != DN_O) - return -EINVAL; - - if (optlen != sizeof(struct accessdata_dn)) - return -EINVAL; - - if ((u.acc.acc_accl > DN_MAXACCL) || - (u.acc.acc_passl > DN_MAXACCL) || - (u.acc.acc_userl > DN_MAXACCL)) - return -EINVAL; - - memcpy(&scp->accessdata, &u.acc, optlen); - break; - - case DSO_ACCEPTMODE: - if (sock->state == SS_CONNECTED) - return -EISCONN; - if (scp->state != DN_O) - return -EINVAL; - - if (optlen != sizeof(int)) - return -EINVAL; - - if ((u.mode != ACC_IMMED) && (u.mode != ACC_DEFER)) - return -EINVAL; - - scp->accept_mode = (unsigned char)u.mode; - break; - - case DSO_CONACCEPT: - if (scp->state != DN_CR) - return -EINVAL; - timeo = sock_rcvtimeo(sk, 0); - err = dn_confirm_accept(sk, &timeo, sk->sk_allocation); - return err; - - case DSO_CONREJECT: - if (scp->state != DN_CR) - return -EINVAL; - - scp->state = DN_DR; - sk->sk_shutdown = SHUTDOWN_MASK; - dn_nsp_send_disc(sk, 0x38, 0, sk->sk_allocation); - break; - - case DSO_MAXWINDOW: - if (optlen != sizeof(unsigned long)) - return -EINVAL; - if (u.win > NSP_MAX_WINDOW) - u.win = NSP_MAX_WINDOW; - if (u.win == 0) - return -EINVAL; - scp->max_window = u.win; - if (scp->snd_window > u.win) - scp->snd_window = u.win; - break; - - case DSO_NODELAY: - if (optlen != sizeof(int)) - return -EINVAL; - if (scp->nonagle == TCP_NAGLE_CORK) - return -EINVAL; - scp->nonagle = (u.val == 0) ? 0 : TCP_NAGLE_OFF; - /* if (scp->nonagle == 1) { Push pending frames } */ - break; - - case DSO_CORK: - if (optlen != sizeof(int)) - return -EINVAL; - if (scp->nonagle == TCP_NAGLE_OFF) - return -EINVAL; - scp->nonagle = (u.val == 0) ? 0 : TCP_NAGLE_CORK; - /* if (scp->nonagle == 0) { Push pending frames } */ - break; - - case DSO_SERVICES: - if (optlen != sizeof(unsigned char)) - return -EINVAL; - if ((u.services & ~NSP_FC_MASK) != 0x01) - return -EINVAL; - if ((u.services & NSP_FC_MASK) == NSP_FC_MASK) - return -EINVAL; - scp->services_loc = u.services; - break; - - case DSO_INFO: - if (optlen != sizeof(unsigned char)) - return -EINVAL; - if (u.info & 0xfc) - return -EINVAL; - scp->info_loc = u.info; - break; - - case DSO_LINKINFO: - case DSO_STREAM: - case DSO_SEQPACKET: - default: - return -ENOPROTOOPT; - } - - return 0; -} - -static int dn_getsockopt(struct socket *sock, int level, int optname, char __user *optval, int __user *optlen) -{ - struct sock *sk = sock->sk; - int err; - - lock_sock(sk); - err = __dn_getsockopt(sock, level, optname, optval, optlen, 0); - release_sock(sk); -#ifdef CONFIG_NETFILTER - if (err == -ENOPROTOOPT && optname != DSO_STREAM && - optname != DSO_SEQPACKET && optname != DSO_CONACCEPT && - optname != DSO_CONREJECT) { - int len; - - if (get_user(len, optlen)) - return -EFAULT; - - err = nf_getsockopt(sk, PF_DECnet, optname, optval, &len); - if (err >= 0) - err = put_user(len, optlen); - } -#endif - - return err; -} - -static int __dn_getsockopt(struct socket *sock, int level,int optname, char __user *optval,int __user *optlen, int flags) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - struct linkinfo_dn link; - unsigned int r_len; - void *r_data = NULL; - unsigned int val; - - if(get_user(r_len , optlen)) - return -EFAULT; - - switch (optname) { - case DSO_CONDATA: - if (r_len > sizeof(struct optdata_dn)) - r_len = sizeof(struct optdata_dn); - r_data = &scp->conndata_in; - break; - - case DSO_DISDATA: - if (r_len > sizeof(struct optdata_dn)) - r_len = sizeof(struct optdata_dn); - r_data = &scp->discdata_in; - break; - - case DSO_CONACCESS: - if (r_len > sizeof(struct accessdata_dn)) - r_len = sizeof(struct accessdata_dn); - r_data = &scp->accessdata; - break; - - case DSO_ACCEPTMODE: - if (r_len > sizeof(unsigned char)) - r_len = sizeof(unsigned char); - r_data = &scp->accept_mode; - break; - - case DSO_LINKINFO: - if (r_len > sizeof(struct linkinfo_dn)) - r_len = sizeof(struct linkinfo_dn); - - memset(&link, 0, sizeof(link)); - - switch (sock->state) { - case SS_CONNECTING: - link.idn_linkstate = LL_CONNECTING; - break; - case SS_DISCONNECTING: - link.idn_linkstate = LL_DISCONNECTING; - break; - case SS_CONNECTED: - link.idn_linkstate = LL_RUNNING; - break; - default: - link.idn_linkstate = LL_INACTIVE; - } - - link.idn_segsize = scp->segsize_rem; - r_data = &link; - break; - - case DSO_MAXWINDOW: - if (r_len > sizeof(unsigned long)) - r_len = sizeof(unsigned long); - r_data = &scp->max_window; - break; - - case DSO_NODELAY: - if (r_len > sizeof(int)) - r_len = sizeof(int); - val = (scp->nonagle == TCP_NAGLE_OFF); - r_data = &val; - break; - - case DSO_CORK: - if (r_len > sizeof(int)) - r_len = sizeof(int); - val = (scp->nonagle == TCP_NAGLE_CORK); - r_data = &val; - break; - - case DSO_SERVICES: - if (r_len > sizeof(unsigned char)) - r_len = sizeof(unsigned char); - r_data = &scp->services_rem; - break; - - case DSO_INFO: - if (r_len > sizeof(unsigned char)) - r_len = sizeof(unsigned char); - r_data = &scp->info_rem; - break; - - case DSO_STREAM: - case DSO_SEQPACKET: - case DSO_CONACCEPT: - case DSO_CONREJECT: - default: - return -ENOPROTOOPT; - } - - if (r_data) { - if (copy_to_user(optval, r_data, r_len)) - return -EFAULT; - if (put_user(r_len, optlen)) - return -EFAULT; - } - - return 0; -} - - -static int dn_data_ready(struct sock *sk, struct sk_buff_head *q, int flags, int target) -{ - struct sk_buff *skb; - int len = 0; - - if (flags & MSG_OOB) - return !skb_queue_empty(q) ? 1 : 0; - - skb_queue_walk(q, skb) { - struct dn_skb_cb *cb = DN_SKB_CB(skb); - len += skb->len; - - if (cb->nsp_flags & 0x40) { - /* SOCK_SEQPACKET reads to EOM */ - if (sk->sk_type == SOCK_SEQPACKET) - return 1; - /* so does SOCK_STREAM unless WAITALL is specified */ - if (!(flags & MSG_WAITALL)) - return 1; - } - - /* minimum data length for read exceeded */ - if (len >= target) - return 1; - } - - return 0; -} - - -static int dn_recvmsg(struct socket *sock, struct msghdr *msg, size_t size, - int flags) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - struct sk_buff_head *queue = &sk->sk_receive_queue; - size_t target = size > 1 ? 1 : 0; - size_t copied = 0; - int rv = 0; - struct sk_buff *skb, *n; - struct dn_skb_cb *cb = NULL; - unsigned char eor = 0; - long timeo = sock_rcvtimeo(sk, flags & MSG_DONTWAIT); - - lock_sock(sk); - - if (sock_flag(sk, SOCK_ZAPPED)) { - rv = -EADDRNOTAVAIL; - goto out; - } - - if (sk->sk_shutdown & RCV_SHUTDOWN) { - rv = 0; - goto out; - } - - rv = dn_check_state(sk, NULL, 0, &timeo, flags); - if (rv) - goto out; - - if (flags & ~(MSG_CMSG_COMPAT|MSG_PEEK|MSG_OOB|MSG_WAITALL|MSG_DONTWAIT|MSG_NOSIGNAL)) { - rv = -EOPNOTSUPP; - goto out; - } - - if (flags & MSG_OOB) - queue = &scp->other_receive_queue; - - if (flags & MSG_WAITALL) - target = size; - - - /* - * See if there is data ready to read, sleep if there isn't - */ - for(;;) { - DEFINE_WAIT_FUNC(wait, woken_wake_function); - - if (sk->sk_err) - goto out; - - if (!skb_queue_empty(&scp->other_receive_queue)) { - if (!(flags & MSG_OOB)) { - msg->msg_flags |= MSG_OOB; - if (!scp->other_report) { - scp->other_report = 1; - goto out; - } - } - } - - if (scp->state != DN_RUN) - goto out; - - if (signal_pending(current)) { - rv = sock_intr_errno(timeo); - goto out; - } - - if (dn_data_ready(sk, queue, flags, target)) - break; - - if (flags & MSG_DONTWAIT) { - rv = -EWOULDBLOCK; - goto out; - } - - add_wait_queue(sk_sleep(sk), &wait); - sk_set_bit(SOCKWQ_ASYNC_WAITDATA, sk); - sk_wait_event(sk, &timeo, dn_data_ready(sk, queue, flags, target), &wait); - sk_clear_bit(SOCKWQ_ASYNC_WAITDATA, sk); - remove_wait_queue(sk_sleep(sk), &wait); - } - - skb_queue_walk_safe(queue, skb, n) { - unsigned int chunk = skb->len; - cb = DN_SKB_CB(skb); - - if ((chunk + copied) > size) - chunk = size - copied; - - if (memcpy_to_msg(msg, skb->data, chunk)) { - rv = -EFAULT; - break; - } - copied += chunk; - - if (!(flags & MSG_PEEK)) - skb_pull(skb, chunk); - - eor = cb->nsp_flags & 0x40; - - if (skb->len == 0) { - skb_unlink(skb, queue); - kfree_skb(skb); - /* - * N.B. Don't refer to skb or cb after this point - * in loop. - */ - if ((scp->flowloc_sw == DN_DONTSEND) && !dn_congested(sk)) { - scp->flowloc_sw = DN_SEND; - dn_nsp_send_link(sk, DN_SEND, 0); - } - } - - if (eor) { - if (sk->sk_type == SOCK_SEQPACKET) - break; - if (!(flags & MSG_WAITALL)) - break; - } - - if (flags & MSG_OOB) - break; - - if (copied >= target) - break; - } - - rv = copied; - - - if (eor && (sk->sk_type == SOCK_SEQPACKET)) - msg->msg_flags |= MSG_EOR; - -out: - if (rv == 0) - rv = (flags & MSG_PEEK) ? -sk->sk_err : sock_error(sk); - - if ((rv >= 0) && msg->msg_name) { - __sockaddr_check_size(sizeof(struct sockaddr_dn)); - memcpy(msg->msg_name, &scp->peer, sizeof(struct sockaddr_dn)); - msg->msg_namelen = sizeof(struct sockaddr_dn); - } - - release_sock(sk); - - return rv; -} - - -static inline int dn_queue_too_long(struct dn_scp *scp, struct sk_buff_head *queue, int flags) -{ - unsigned char fctype = scp->services_rem & NSP_FC_MASK; - if (skb_queue_len(queue) >= scp->snd_window) - return 1; - if (fctype != NSP_FC_NONE) { - if (flags & MSG_OOB) { - if (scp->flowrem_oth == 0) - return 1; - } else { - if (scp->flowrem_dat == 0) - return 1; - } - } - return 0; -} - -/* - * The DECnet spec requires that the "routing layer" accepts packets which - * are at least 230 bytes in size. This excludes any headers which the NSP - * layer might add, so we always assume that we'll be using the maximal - * length header on data packets. The variation in length is due to the - * inclusion (or not) of the two 16 bit acknowledgement fields so it doesn't - * make much practical difference. - */ -unsigned int dn_mss_from_pmtu(struct net_device *dev, int mtu) -{ - unsigned int mss = 230 - DN_MAX_NSP_DATA_HEADER; - if (dev) { - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - mtu -= LL_RESERVED_SPACE(dev); - if (dn_db->use_long) - mtu -= 21; - else - mtu -= 6; - mtu -= DN_MAX_NSP_DATA_HEADER; - } else { - /* - * 21 = long header, 16 = guess at MAC header length - */ - mtu -= (21 + DN_MAX_NSP_DATA_HEADER + 16); - } - if (mtu > mss) - mss = mtu; - return mss; -} - -static inline unsigned int dn_current_mss(struct sock *sk, int flags) -{ - struct dst_entry *dst = __sk_dst_get(sk); - struct dn_scp *scp = DN_SK(sk); - int mss_now = min_t(int, scp->segsize_loc, scp->segsize_rem); - - /* Other data messages are limited to 16 bytes per packet */ - if (flags & MSG_OOB) - return 16; - - /* This works out the maximum size of segment we can send out */ - if (dst) { - u32 mtu = dst_mtu(dst); - mss_now = min_t(int, dn_mss_from_pmtu(dst->dev, mtu), mss_now); - } - - return mss_now; -} - -/* - * N.B. We get the timeout wrong here, but then we always did get it - * wrong before and this is another step along the road to correcting - * it. It ought to get updated each time we pass through the routine, - * but in practise it probably doesn't matter too much for now. - */ -static inline struct sk_buff *dn_alloc_send_pskb(struct sock *sk, - unsigned long datalen, int noblock, - int *errcode) -{ - struct sk_buff *skb = sock_alloc_send_skb(sk, datalen, - noblock, errcode); - if (skb) { - skb->protocol = htons(ETH_P_DNA_RT); - skb->pkt_type = PACKET_OUTGOING; - } - return skb; -} - -static int dn_sendmsg(struct socket *sock, struct msghdr *msg, size_t size) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - size_t mss; - struct sk_buff_head *queue = &scp->data_xmit_queue; - int flags = msg->msg_flags; - int err = 0; - size_t sent = 0; - int addr_len = msg->msg_namelen; - DECLARE_SOCKADDR(struct sockaddr_dn *, addr, msg->msg_name); - struct sk_buff *skb = NULL; - struct dn_skb_cb *cb; - size_t len; - unsigned char fctype; - long timeo; - - if (flags & ~(MSG_TRYHARD|MSG_OOB|MSG_DONTWAIT|MSG_EOR|MSG_NOSIGNAL|MSG_MORE|MSG_CMSG_COMPAT)) - return -EOPNOTSUPP; - - if (addr_len && (addr_len != sizeof(struct sockaddr_dn))) - return -EINVAL; - - lock_sock(sk); - timeo = sock_sndtimeo(sk, flags & MSG_DONTWAIT); - /* - * The only difference between stream sockets and sequenced packet - * sockets is that the stream sockets always behave as if MSG_EOR - * has been set. - */ - if (sock->type == SOCK_STREAM) { - if (flags & MSG_EOR) { - err = -EINVAL; - goto out; - } - flags |= MSG_EOR; - } - - - err = dn_check_state(sk, addr, addr_len, &timeo, flags); - if (err) - goto out_err; - - if (sk->sk_shutdown & SEND_SHUTDOWN) { - err = -EPIPE; - if (!(flags & MSG_NOSIGNAL)) - send_sig(SIGPIPE, current, 0); - goto out_err; - } - - if ((flags & MSG_TRYHARD) && sk->sk_dst_cache) - dst_negative_advice(sk); - - mss = scp->segsize_rem; - fctype = scp->services_rem & NSP_FC_MASK; - - mss = dn_current_mss(sk, flags); - - if (flags & MSG_OOB) { - queue = &scp->other_xmit_queue; - if (size > mss) { - err = -EMSGSIZE; - goto out; - } - } - - scp->persist_fxn = dn_nsp_xmit_timeout; - - while(sent < size) { - err = sock_error(sk); - if (err) - goto out; - - if (signal_pending(current)) { - err = sock_intr_errno(timeo); - goto out; - } - - /* - * Calculate size that we wish to send. - */ - len = size - sent; - - if (len > mss) - len = mss; - - /* - * Wait for queue size to go down below the window - * size. - */ - if (dn_queue_too_long(scp, queue, flags)) { - DEFINE_WAIT_FUNC(wait, woken_wake_function); - - if (flags & MSG_DONTWAIT) { - err = -EWOULDBLOCK; - goto out; - } - - add_wait_queue(sk_sleep(sk), &wait); - sk_set_bit(SOCKWQ_ASYNC_WAITDATA, sk); - sk_wait_event(sk, &timeo, - !dn_queue_too_long(scp, queue, flags), &wait); - sk_clear_bit(SOCKWQ_ASYNC_WAITDATA, sk); - remove_wait_queue(sk_sleep(sk), &wait); - continue; - } - - /* - * Get a suitably sized skb. - * 64 is a bit of a hack really, but its larger than any - * link-layer headers and has served us well as a good - * guess as to their real length. - */ - skb = dn_alloc_send_pskb(sk, len + 64 + DN_MAX_NSP_DATA_HEADER, - flags & MSG_DONTWAIT, &err); - - if (err) - break; - - if (!skb) - continue; - - cb = DN_SKB_CB(skb); - - skb_reserve(skb, 64 + DN_MAX_NSP_DATA_HEADER); - - if (memcpy_from_msg(skb_put(skb, len), msg, len)) { - err = -EFAULT; - goto out; - } - - if (flags & MSG_OOB) { - cb->nsp_flags = 0x30; - if (fctype != NSP_FC_NONE) - scp->flowrem_oth--; - } else { - cb->nsp_flags = 0x00; - if (scp->seg_total == 0) - cb->nsp_flags |= 0x20; - - scp->seg_total += len; - - if (((sent + len) == size) && (flags & MSG_EOR)) { - cb->nsp_flags |= 0x40; - scp->seg_total = 0; - if (fctype == NSP_FC_SCMC) - scp->flowrem_dat--; - } - if (fctype == NSP_FC_SRC) - scp->flowrem_dat--; - } - - sent += len; - dn_nsp_queue_xmit(sk, skb, sk->sk_allocation, flags & MSG_OOB); - skb = NULL; - - scp->persist = dn_nsp_persist(sk); - - } -out: - - kfree_skb(skb); - - release_sock(sk); - - return sent ? sent : err; - -out_err: - err = sk_stream_error(sk, flags, err); - release_sock(sk); - return err; -} - -static int dn_device_event(struct notifier_block *this, unsigned long event, - void *ptr) -{ - struct net_device *dev = netdev_notifier_info_to_dev(ptr); - - if (!net_eq(dev_net(dev), &init_net)) - return NOTIFY_DONE; - - switch (event) { - case NETDEV_UP: - dn_dev_up(dev); - break; - case NETDEV_DOWN: - dn_dev_down(dev); - break; - default: - break; - } - - return NOTIFY_DONE; -} - -static struct notifier_block dn_dev_notifier = { - .notifier_call = dn_device_event, -}; - -static struct packet_type dn_dix_packet_type __read_mostly = { - .type = cpu_to_be16(ETH_P_DNA_RT), - .func = dn_route_rcv, -}; - -#ifdef CONFIG_PROC_FS -struct dn_iter_state { - int bucket; -}; - -static struct sock *dn_socket_get_first(struct seq_file *seq) -{ - struct dn_iter_state *state = seq->private; - struct sock *n = NULL; - - for(state->bucket = 0; - state->bucket < DN_SK_HASH_SIZE; - ++state->bucket) { - n = sk_head(&dn_sk_hash[state->bucket]); - if (n) - break; - } - - return n; -} - -static struct sock *dn_socket_get_next(struct seq_file *seq, - struct sock *n) -{ - struct dn_iter_state *state = seq->private; - - n = sk_next(n); -try_again: - if (n) - goto out; - if (++state->bucket >= DN_SK_HASH_SIZE) - goto out; - n = sk_head(&dn_sk_hash[state->bucket]); - goto try_again; -out: - return n; -} - -static struct sock *socket_get_idx(struct seq_file *seq, loff_t *pos) -{ - struct sock *sk = dn_socket_get_first(seq); - - if (sk) { - while(*pos && (sk = dn_socket_get_next(seq, sk))) - --*pos; - } - return *pos ? NULL : sk; -} - -static void *dn_socket_get_idx(struct seq_file *seq, loff_t pos) -{ - void *rc; - read_lock_bh(&dn_hash_lock); - rc = socket_get_idx(seq, &pos); - if (!rc) { - read_unlock_bh(&dn_hash_lock); - } - return rc; -} - -static void *dn_socket_seq_start(struct seq_file *seq, loff_t *pos) -{ - return *pos ? dn_socket_get_idx(seq, *pos - 1) : SEQ_START_TOKEN; -} - -static void *dn_socket_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - void *rc; - - if (v == SEQ_START_TOKEN) { - rc = dn_socket_get_idx(seq, 0); - goto out; - } - - rc = dn_socket_get_next(seq, v); - if (rc) - goto out; - read_unlock_bh(&dn_hash_lock); -out: - ++*pos; - return rc; -} - -static void dn_socket_seq_stop(struct seq_file *seq, void *v) -{ - if (v && v != SEQ_START_TOKEN) - read_unlock_bh(&dn_hash_lock); -} - -#define IS_NOT_PRINTABLE(x) ((x) < 32 || (x) > 126) - -static void dn_printable_object(struct sockaddr_dn *dn, unsigned char *buf) -{ - int i; - - switch (le16_to_cpu(dn->sdn_objnamel)) { - case 0: - sprintf(buf, "%d", dn->sdn_objnum); - break; - default: - for (i = 0; i < le16_to_cpu(dn->sdn_objnamel); i++) { - buf[i] = dn->sdn_objname[i]; - if (IS_NOT_PRINTABLE(buf[i])) - buf[i] = '.'; - } - buf[i] = 0; - } -} - -static char *dn_state2asc(unsigned char state) -{ - switch (state) { - case DN_O: - return "OPEN"; - case DN_CR: - return " CR"; - case DN_DR: - return " DR"; - case DN_DRC: - return " DRC"; - case DN_CC: - return " CC"; - case DN_CI: - return " CI"; - case DN_NR: - return " NR"; - case DN_NC: - return " NC"; - case DN_CD: - return " CD"; - case DN_RJ: - return " RJ"; - case DN_RUN: - return " RUN"; - case DN_DI: - return " DI"; - case DN_DIC: - return " DIC"; - case DN_DN: - return " DN"; - case DN_CL: - return " CL"; - case DN_CN: - return " CN"; - } - - return "????"; -} - -static inline void dn_socket_format_entry(struct seq_file *seq, struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - char buf1[DN_ASCBUF_LEN]; - char buf2[DN_ASCBUF_LEN]; - char local_object[DN_MAXOBJL+3]; - char remote_object[DN_MAXOBJL+3]; - - dn_printable_object(&scp->addr, local_object); - dn_printable_object(&scp->peer, remote_object); - - seq_printf(seq, - "%6s/%04X %04d:%04d %04d:%04d %01d %-16s " - "%6s/%04X %04d:%04d %04d:%04d %01d %-16s %4s %s\n", - dn_addr2asc(le16_to_cpu(dn_saddr2dn(&scp->addr)), buf1), - scp->addrloc, - scp->numdat, - scp->numoth, - scp->ackxmt_dat, - scp->ackxmt_oth, - scp->flowloc_sw, - local_object, - dn_addr2asc(le16_to_cpu(dn_saddr2dn(&scp->peer)), buf2), - scp->addrrem, - scp->numdat_rcv, - scp->numoth_rcv, - scp->ackrcv_dat, - scp->ackrcv_oth, - scp->flowrem_sw, - remote_object, - dn_state2asc(scp->state), - ((scp->accept_mode == ACC_IMMED) ? "IMMED" : "DEFER")); -} - -static int dn_socket_seq_show(struct seq_file *seq, void *v) -{ - if (v == SEQ_START_TOKEN) { - seq_puts(seq, "Local Remote\n"); - } else { - dn_socket_format_entry(seq, v); - } - return 0; -} - -static const struct seq_operations dn_socket_seq_ops = { - .start = dn_socket_seq_start, - .next = dn_socket_seq_next, - .stop = dn_socket_seq_stop, - .show = dn_socket_seq_show, -}; -#endif - -static const struct net_proto_family dn_family_ops = { - .family = AF_DECnet, - .create = dn_create, - .owner = THIS_MODULE, -}; - -static const struct proto_ops dn_proto_ops = { - .family = AF_DECnet, - .owner = THIS_MODULE, - .release = dn_release, - .bind = dn_bind, - .connect = dn_connect, - .socketpair = sock_no_socketpair, - .accept = dn_accept, - .getname = dn_getname, - .poll = dn_poll, - .ioctl = dn_ioctl, - .listen = dn_listen, - .shutdown = dn_shutdown, - .setsockopt = dn_setsockopt, - .getsockopt = dn_getsockopt, - .sendmsg = dn_sendmsg, - .recvmsg = dn_recvmsg, - .mmap = sock_no_mmap, - .sendpage = sock_no_sendpage, -}; - -MODULE_DESCRIPTION("The Linux DECnet Network Protocol"); -MODULE_AUTHOR("Linux DECnet Project Team"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS_NETPROTO(PF_DECnet); - -static const char banner[] __initconst = KERN_INFO -"NET4: DECnet for Linux: V.2.5.68s (C) 1995-2003 Linux DECnet Project Team\n"; - -static int __init decnet_init(void) -{ - int rc; - - printk(banner); - - rc = proto_register(&dn_proto, 1); - if (rc != 0) - goto out; - - dn_neigh_init(); - dn_dev_init(); - dn_route_init(); - dn_fib_init(); - - sock_register(&dn_family_ops); - dev_add_pack(&dn_dix_packet_type); - register_netdevice_notifier(&dn_dev_notifier); - - proc_create_seq_private("decnet", 0444, init_net.proc_net, - &dn_socket_seq_ops, sizeof(struct dn_iter_state), - NULL); - dn_register_sysctl(); -out: - return rc; - -} -module_init(decnet_init); - -/* - * Prevent DECnet module unloading until its fixed properly. - * Requires an audit of the code to check for memory leaks and - * initialisation problems etc. - */ -#if 0 -static void __exit decnet_exit(void) -{ - sock_unregister(AF_DECnet); - rtnl_unregister_all(PF_DECnet); - dev_remove_pack(&dn_dix_packet_type); - - dn_unregister_sysctl(); - - unregister_netdevice_notifier(&dn_dev_notifier); - - dn_route_cleanup(); - dn_dev_cleanup(); - dn_neigh_cleanup(); - dn_fib_cleanup(); - - remove_proc_entry("decnet", init_net.proc_net); - - proto_unregister(&dn_proto); - - rcu_barrier_bh(); /* Wait for completion of call_rcu_bh()'s */ -} -module_exit(decnet_exit); -#endif diff --git a/net/decnet/dn_dev.c b/net/decnet/dn_dev.c deleted file mode 100644 index 3235540f6adff0a924a06c36c7b219e76e7167cb..0000000000000000000000000000000000000000 --- a/net/decnet/dn_dev.c +++ /dev/null @@ -1,1438 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Device Layer - * - * Authors: Steve Whitehouse - * Eduardo Marcelo Serrat - * - * Changes: - * Steve Whitehouse : Devices now see incoming frames so they - * can mark on who it came from. - * Steve Whitehouse : Fixed bug in creating neighbours. Each neighbour - * can now have a device specific setup func. - * Steve Whitehouse : Added /proc/sys/net/decnet/conf// - * Steve Whitehouse : Fixed bug which sometimes killed timer - * Steve Whitehouse : Multiple ifaddr support - * Steve Whitehouse : SIOCGIFCONF is now a compile time option - * Steve Whitehouse : /proc/sys/net/decnet/conf//forwarding - * Steve Whitehouse : Removed timer1 - it's a user space issue now - * Patrick Caulfield : Fixed router hello message format - * Steve Whitehouse : Got rid of constant sizes for blksize for - * devices. All mtu based now. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DN_IFREQ_SIZE (offsetof(struct ifreq, ifr_ifru) + sizeof(struct sockaddr_dn)) - -static char dn_rt_all_end_mcast[ETH_ALEN] = {0xAB,0x00,0x00,0x04,0x00,0x00}; -static char dn_rt_all_rt_mcast[ETH_ALEN] = {0xAB,0x00,0x00,0x03,0x00,0x00}; -static char dn_hiord[ETH_ALEN] = {0xAA,0x00,0x04,0x00,0x00,0x00}; -static unsigned char dn_eco_version[3] = {0x02,0x00,0x00}; - -extern struct neigh_table dn_neigh_table; - -/* - * decnet_address is kept in network order. - */ -__le16 decnet_address = 0; - -static DEFINE_SPINLOCK(dndev_lock); -static struct net_device *decnet_default_device; -static BLOCKING_NOTIFIER_HEAD(dnaddr_chain); - -static struct dn_dev *dn_dev_create(struct net_device *dev, int *err); -static void dn_dev_delete(struct net_device *dev); -static void dn_ifaddr_notify(int event, struct dn_ifaddr *ifa); - -static int dn_eth_up(struct net_device *); -static void dn_eth_down(struct net_device *); -static void dn_send_brd_hello(struct net_device *dev, struct dn_ifaddr *ifa); -static void dn_send_ptp_hello(struct net_device *dev, struct dn_ifaddr *ifa); - -static struct dn_dev_parms dn_dev_list[] = { -{ - .type = ARPHRD_ETHER, /* Ethernet */ - .mode = DN_DEV_BCAST, - .state = DN_DEV_S_RU, - .t2 = 1, - .t3 = 10, - .name = "ethernet", - .up = dn_eth_up, - .down = dn_eth_down, - .timer3 = dn_send_brd_hello, -}, -{ - .type = ARPHRD_IPGRE, /* DECnet tunneled over GRE in IP */ - .mode = DN_DEV_BCAST, - .state = DN_DEV_S_RU, - .t2 = 1, - .t3 = 10, - .name = "ipgre", - .timer3 = dn_send_brd_hello, -}, -#if 0 -{ - .type = ARPHRD_X25, /* Bog standard X.25 */ - .mode = DN_DEV_UCAST, - .state = DN_DEV_S_DS, - .t2 = 1, - .t3 = 120, - .name = "x25", - .timer3 = dn_send_ptp_hello, -}, -#endif -#if 0 -{ - .type = ARPHRD_PPP, /* DECnet over PPP */ - .mode = DN_DEV_BCAST, - .state = DN_DEV_S_RU, - .t2 = 1, - .t3 = 10, - .name = "ppp", - .timer3 = dn_send_brd_hello, -}, -#endif -{ - .type = ARPHRD_DDCMP, /* DECnet over DDCMP */ - .mode = DN_DEV_UCAST, - .state = DN_DEV_S_DS, - .t2 = 1, - .t3 = 120, - .name = "ddcmp", - .timer3 = dn_send_ptp_hello, -}, -{ - .type = ARPHRD_LOOPBACK, /* Loopback interface - always last */ - .mode = DN_DEV_BCAST, - .state = DN_DEV_S_RU, - .t2 = 1, - .t3 = 10, - .name = "loopback", - .timer3 = dn_send_brd_hello, -} -}; - -#define DN_DEV_LIST_SIZE ARRAY_SIZE(dn_dev_list) - -#define DN_DEV_PARMS_OFFSET(x) offsetof(struct dn_dev_parms, x) - -#ifdef CONFIG_SYSCTL - -static int min_t2[] = { 1 }; -static int max_t2[] = { 60 }; /* No max specified, but this seems sensible */ -static int min_t3[] = { 1 }; -static int max_t3[] = { 8191 }; /* Must fit in 16 bits when multiplied by BCT3MULT or T3MULT */ - -static int min_priority[1]; -static int max_priority[] = { 127 }; /* From DECnet spec */ - -static int dn_forwarding_proc(struct ctl_table *, int, - void __user *, size_t *, loff_t *); -static struct dn_dev_sysctl_table { - struct ctl_table_header *sysctl_header; - struct ctl_table dn_dev_vars[5]; -} dn_dev_sysctl = { - NULL, - { - { - .procname = "forwarding", - .data = (void *)DN_DEV_PARMS_OFFSET(forwarding), - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = dn_forwarding_proc, - }, - { - .procname = "priority", - .data = (void *)DN_DEV_PARMS_OFFSET(priority), - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_priority, - .extra2 = &max_priority - }, - { - .procname = "t2", - .data = (void *)DN_DEV_PARMS_OFFSET(t2), - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_t2, - .extra2 = &max_t2 - }, - { - .procname = "t3", - .data = (void *)DN_DEV_PARMS_OFFSET(t3), - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_t3, - .extra2 = &max_t3 - }, - { } - }, -}; - -static void dn_dev_sysctl_register(struct net_device *dev, struct dn_dev_parms *parms) -{ - struct dn_dev_sysctl_table *t; - int i; - - char path[sizeof("net/decnet/conf/") + IFNAMSIZ]; - - t = kmemdup(&dn_dev_sysctl, sizeof(*t), GFP_KERNEL); - if (t == NULL) - return; - - for(i = 0; i < ARRAY_SIZE(t->dn_dev_vars) - 1; i++) { - long offset = (long)t->dn_dev_vars[i].data; - t->dn_dev_vars[i].data = ((char *)parms) + offset; - } - - snprintf(path, sizeof(path), "net/decnet/conf/%s", - dev? dev->name : parms->name); - - t->dn_dev_vars[0].extra1 = (void *)dev; - - t->sysctl_header = register_net_sysctl(&init_net, path, t->dn_dev_vars); - if (t->sysctl_header == NULL) - kfree(t); - else - parms->sysctl = t; -} - -static void dn_dev_sysctl_unregister(struct dn_dev_parms *parms) -{ - if (parms->sysctl) { - struct dn_dev_sysctl_table *t = parms->sysctl; - parms->sysctl = NULL; - unregister_net_sysctl_table(t->sysctl_header); - kfree(t); - } -} - -static int dn_forwarding_proc(struct ctl_table *table, int write, - void __user *buffer, - size_t *lenp, loff_t *ppos) -{ -#ifdef CONFIG_DECNET_ROUTER - struct net_device *dev = table->extra1; - struct dn_dev *dn_db; - int err; - int tmp, old; - - if (table->extra1 == NULL) - return -EINVAL; - - dn_db = rcu_dereference_raw(dev->dn_ptr); - old = dn_db->parms.forwarding; - - err = proc_dointvec(table, write, buffer, lenp, ppos); - - if ((err >= 0) && write) { - if (dn_db->parms.forwarding < 0) - dn_db->parms.forwarding = 0; - if (dn_db->parms.forwarding > 2) - dn_db->parms.forwarding = 2; - /* - * What an ugly hack this is... its works, just. It - * would be nice if sysctl/proc were just that little - * bit more flexible so I don't have to write a special - * routine, or suffer hacks like this - SJW - */ - tmp = dn_db->parms.forwarding; - dn_db->parms.forwarding = old; - if (dn_db->parms.down) - dn_db->parms.down(dev); - dn_db->parms.forwarding = tmp; - if (dn_db->parms.up) - dn_db->parms.up(dev); - } - - return err; -#else - return -EINVAL; -#endif -} - -#else /* CONFIG_SYSCTL */ -static void dn_dev_sysctl_unregister(struct dn_dev_parms *parms) -{ -} -static void dn_dev_sysctl_register(struct net_device *dev, struct dn_dev_parms *parms) -{ -} - -#endif /* CONFIG_SYSCTL */ - -static inline __u16 mtu2blksize(struct net_device *dev) -{ - u32 blksize = dev->mtu; - if (blksize > 0xffff) - blksize = 0xffff; - - if (dev->type == ARPHRD_ETHER || - dev->type == ARPHRD_PPP || - dev->type == ARPHRD_IPGRE || - dev->type == ARPHRD_LOOPBACK) - blksize -= 2; - - return (__u16)blksize; -} - -static struct dn_ifaddr *dn_dev_alloc_ifa(void) -{ - struct dn_ifaddr *ifa; - - ifa = kzalloc(sizeof(*ifa), GFP_KERNEL); - - return ifa; -} - -static void dn_dev_free_ifa(struct dn_ifaddr *ifa) -{ - kfree_rcu(ifa, rcu); -} - -static void dn_dev_del_ifa(struct dn_dev *dn_db, struct dn_ifaddr __rcu **ifap, int destroy) -{ - struct dn_ifaddr *ifa1 = rtnl_dereference(*ifap); - unsigned char mac_addr[6]; - struct net_device *dev = dn_db->dev; - - ASSERT_RTNL(); - - *ifap = ifa1->ifa_next; - - if (dn_db->dev->type == ARPHRD_ETHER) { - if (ifa1->ifa_local != dn_eth2dn(dev->dev_addr)) { - dn_dn2eth(mac_addr, ifa1->ifa_local); - dev_mc_del(dev, mac_addr); - } - } - - dn_ifaddr_notify(RTM_DELADDR, ifa1); - blocking_notifier_call_chain(&dnaddr_chain, NETDEV_DOWN, ifa1); - if (destroy) { - dn_dev_free_ifa(ifa1); - - if (dn_db->ifa_list == NULL) - dn_dev_delete(dn_db->dev); - } -} - -static int dn_dev_insert_ifa(struct dn_dev *dn_db, struct dn_ifaddr *ifa) -{ - struct net_device *dev = dn_db->dev; - struct dn_ifaddr *ifa1; - unsigned char mac_addr[6]; - - ASSERT_RTNL(); - - /* Check for duplicates */ - for (ifa1 = rtnl_dereference(dn_db->ifa_list); - ifa1 != NULL; - ifa1 = rtnl_dereference(ifa1->ifa_next)) { - if (ifa1->ifa_local == ifa->ifa_local) - return -EEXIST; - } - - if (dev->type == ARPHRD_ETHER) { - if (ifa->ifa_local != dn_eth2dn(dev->dev_addr)) { - dn_dn2eth(mac_addr, ifa->ifa_local); - dev_mc_add(dev, mac_addr); - } - } - - ifa->ifa_next = dn_db->ifa_list; - rcu_assign_pointer(dn_db->ifa_list, ifa); - - dn_ifaddr_notify(RTM_NEWADDR, ifa); - blocking_notifier_call_chain(&dnaddr_chain, NETDEV_UP, ifa); - - return 0; -} - -static int dn_dev_set_ifa(struct net_device *dev, struct dn_ifaddr *ifa) -{ - struct dn_dev *dn_db = rtnl_dereference(dev->dn_ptr); - int rv; - - if (dn_db == NULL) { - int err; - dn_db = dn_dev_create(dev, &err); - if (dn_db == NULL) - return err; - } - - ifa->ifa_dev = dn_db; - - if (dev->flags & IFF_LOOPBACK) - ifa->ifa_scope = RT_SCOPE_HOST; - - rv = dn_dev_insert_ifa(dn_db, ifa); - if (rv) - dn_dev_free_ifa(ifa); - return rv; -} - - -int dn_dev_ioctl(unsigned int cmd, void __user *arg) -{ - char buffer[DN_IFREQ_SIZE]; - struct ifreq *ifr = (struct ifreq *)buffer; - struct sockaddr_dn *sdn = (struct sockaddr_dn *)&ifr->ifr_addr; - struct dn_dev *dn_db; - struct net_device *dev; - struct dn_ifaddr *ifa = NULL; - struct dn_ifaddr __rcu **ifap = NULL; - int ret = 0; - - if (copy_from_user(ifr, arg, DN_IFREQ_SIZE)) - return -EFAULT; - ifr->ifr_name[IFNAMSIZ-1] = 0; - - dev_load(&init_net, ifr->ifr_name); - - switch (cmd) { - case SIOCGIFADDR: - break; - case SIOCSIFADDR: - if (!capable(CAP_NET_ADMIN)) - return -EACCES; - if (sdn->sdn_family != AF_DECnet) - return -EINVAL; - break; - default: - return -EINVAL; - } - - rtnl_lock(); - - if ((dev = __dev_get_by_name(&init_net, ifr->ifr_name)) == NULL) { - ret = -ENODEV; - goto done; - } - - if ((dn_db = rtnl_dereference(dev->dn_ptr)) != NULL) { - for (ifap = &dn_db->ifa_list; - (ifa = rtnl_dereference(*ifap)) != NULL; - ifap = &ifa->ifa_next) - if (strcmp(ifr->ifr_name, ifa->ifa_label) == 0) - break; - } - - if (ifa == NULL && cmd != SIOCSIFADDR) { - ret = -EADDRNOTAVAIL; - goto done; - } - - switch (cmd) { - case SIOCGIFADDR: - *((__le16 *)sdn->sdn_nodeaddr) = ifa->ifa_local; - goto rarok; - - case SIOCSIFADDR: - if (!ifa) { - if ((ifa = dn_dev_alloc_ifa()) == NULL) { - ret = -ENOBUFS; - break; - } - memcpy(ifa->ifa_label, dev->name, IFNAMSIZ); - } else { - if (ifa->ifa_local == dn_saddr2dn(sdn)) - break; - dn_dev_del_ifa(dn_db, ifap, 0); - } - - ifa->ifa_local = ifa->ifa_address = dn_saddr2dn(sdn); - - ret = dn_dev_set_ifa(dev, ifa); - } -done: - rtnl_unlock(); - - return ret; -rarok: - if (copy_to_user(arg, ifr, DN_IFREQ_SIZE)) - ret = -EFAULT; - goto done; -} - -struct net_device *dn_dev_get_default(void) -{ - struct net_device *dev; - - spin_lock(&dndev_lock); - dev = decnet_default_device; - if (dev) { - if (dev->dn_ptr) - dev_hold(dev); - else - dev = NULL; - } - spin_unlock(&dndev_lock); - - return dev; -} - -int dn_dev_set_default(struct net_device *dev, int force) -{ - struct net_device *old = NULL; - int rv = -EBUSY; - if (!dev->dn_ptr) - return -ENODEV; - - spin_lock(&dndev_lock); - if (force || decnet_default_device == NULL) { - old = decnet_default_device; - decnet_default_device = dev; - rv = 0; - } - spin_unlock(&dndev_lock); - - if (old) - dev_put(old); - return rv; -} - -static void dn_dev_check_default(struct net_device *dev) -{ - spin_lock(&dndev_lock); - if (dev == decnet_default_device) { - decnet_default_device = NULL; - } else { - dev = NULL; - } - spin_unlock(&dndev_lock); - - if (dev) - dev_put(dev); -} - -/* - * Called with RTNL - */ -static struct dn_dev *dn_dev_by_index(int ifindex) -{ - struct net_device *dev; - struct dn_dev *dn_dev = NULL; - - dev = __dev_get_by_index(&init_net, ifindex); - if (dev) - dn_dev = rtnl_dereference(dev->dn_ptr); - - return dn_dev; -} - -static const struct nla_policy dn_ifa_policy[IFA_MAX+1] = { - [IFA_ADDRESS] = { .type = NLA_U16 }, - [IFA_LOCAL] = { .type = NLA_U16 }, - [IFA_LABEL] = { .type = NLA_STRING, - .len = IFNAMSIZ - 1 }, - [IFA_FLAGS] = { .type = NLA_U32 }, -}; - -static int dn_nl_deladdr(struct sk_buff *skb, struct nlmsghdr *nlh, - struct netlink_ext_ack *extack) -{ - struct net *net = sock_net(skb->sk); - struct nlattr *tb[IFA_MAX+1]; - struct dn_dev *dn_db; - struct ifaddrmsg *ifm; - struct dn_ifaddr *ifa; - struct dn_ifaddr __rcu **ifap; - int err = -EINVAL; - - if (!netlink_capable(skb, CAP_NET_ADMIN)) - return -EPERM; - - if (!net_eq(net, &init_net)) - goto errout; - - err = nlmsg_parse(nlh, sizeof(*ifm), tb, IFA_MAX, dn_ifa_policy, - extack); - if (err < 0) - goto errout; - - err = -ENODEV; - ifm = nlmsg_data(nlh); - if ((dn_db = dn_dev_by_index(ifm->ifa_index)) == NULL) - goto errout; - - err = -EADDRNOTAVAIL; - for (ifap = &dn_db->ifa_list; - (ifa = rtnl_dereference(*ifap)) != NULL; - ifap = &ifa->ifa_next) { - if (tb[IFA_LOCAL] && - nla_memcmp(tb[IFA_LOCAL], &ifa->ifa_local, 2)) - continue; - - if (tb[IFA_LABEL] && nla_strcmp(tb[IFA_LABEL], ifa->ifa_label)) - continue; - - dn_dev_del_ifa(dn_db, ifap, 1); - return 0; - } - -errout: - return err; -} - -static int dn_nl_newaddr(struct sk_buff *skb, struct nlmsghdr *nlh, - struct netlink_ext_ack *extack) -{ - struct net *net = sock_net(skb->sk); - struct nlattr *tb[IFA_MAX+1]; - struct net_device *dev; - struct dn_dev *dn_db; - struct ifaddrmsg *ifm; - struct dn_ifaddr *ifa; - int err; - - if (!netlink_capable(skb, CAP_NET_ADMIN)) - return -EPERM; - - if (!net_eq(net, &init_net)) - return -EINVAL; - - err = nlmsg_parse(nlh, sizeof(*ifm), tb, IFA_MAX, dn_ifa_policy, - extack); - if (err < 0) - return err; - - if (tb[IFA_LOCAL] == NULL) - return -EINVAL; - - ifm = nlmsg_data(nlh); - if ((dev = __dev_get_by_index(&init_net, ifm->ifa_index)) == NULL) - return -ENODEV; - - if ((dn_db = rtnl_dereference(dev->dn_ptr)) == NULL) { - dn_db = dn_dev_create(dev, &err); - if (!dn_db) - return err; - } - - if ((ifa = dn_dev_alloc_ifa()) == NULL) - return -ENOBUFS; - - if (tb[IFA_ADDRESS] == NULL) - tb[IFA_ADDRESS] = tb[IFA_LOCAL]; - - ifa->ifa_local = nla_get_le16(tb[IFA_LOCAL]); - ifa->ifa_address = nla_get_le16(tb[IFA_ADDRESS]); - ifa->ifa_flags = tb[IFA_FLAGS] ? nla_get_u32(tb[IFA_FLAGS]) : - ifm->ifa_flags; - ifa->ifa_scope = ifm->ifa_scope; - ifa->ifa_dev = dn_db; - - if (tb[IFA_LABEL]) - nla_strlcpy(ifa->ifa_label, tb[IFA_LABEL], IFNAMSIZ); - else - memcpy(ifa->ifa_label, dev->name, IFNAMSIZ); - - err = dn_dev_insert_ifa(dn_db, ifa); - if (err) - dn_dev_free_ifa(ifa); - - return err; -} - -static inline size_t dn_ifaddr_nlmsg_size(void) -{ - return NLMSG_ALIGN(sizeof(struct ifaddrmsg)) - + nla_total_size(IFNAMSIZ) /* IFA_LABEL */ - + nla_total_size(2) /* IFA_ADDRESS */ - + nla_total_size(2) /* IFA_LOCAL */ - + nla_total_size(4); /* IFA_FLAGS */ -} - -static int dn_nl_fill_ifaddr(struct sk_buff *skb, struct dn_ifaddr *ifa, - u32 portid, u32 seq, int event, unsigned int flags) -{ - struct ifaddrmsg *ifm; - struct nlmsghdr *nlh; - u32 ifa_flags = ifa->ifa_flags | IFA_F_PERMANENT; - - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*ifm), flags); - if (nlh == NULL) - return -EMSGSIZE; - - ifm = nlmsg_data(nlh); - ifm->ifa_family = AF_DECnet; - ifm->ifa_prefixlen = 16; - ifm->ifa_flags = ifa_flags; - ifm->ifa_scope = ifa->ifa_scope; - ifm->ifa_index = ifa->ifa_dev->dev->ifindex; - - if ((ifa->ifa_address && - nla_put_le16(skb, IFA_ADDRESS, ifa->ifa_address)) || - (ifa->ifa_local && - nla_put_le16(skb, IFA_LOCAL, ifa->ifa_local)) || - (ifa->ifa_label[0] && - nla_put_string(skb, IFA_LABEL, ifa->ifa_label)) || - nla_put_u32(skb, IFA_FLAGS, ifa_flags)) - goto nla_put_failure; - nlmsg_end(skb, nlh); - return 0; - -nla_put_failure: - nlmsg_cancel(skb, nlh); - return -EMSGSIZE; -} - -static void dn_ifaddr_notify(int event, struct dn_ifaddr *ifa) -{ - struct sk_buff *skb; - int err = -ENOBUFS; - - skb = alloc_skb(dn_ifaddr_nlmsg_size(), GFP_KERNEL); - if (skb == NULL) - goto errout; - - err = dn_nl_fill_ifaddr(skb, ifa, 0, 0, event, 0); - if (err < 0) { - /* -EMSGSIZE implies BUG in dn_ifaddr_nlmsg_size() */ - WARN_ON(err == -EMSGSIZE); - kfree_skb(skb); - goto errout; - } - rtnl_notify(skb, &init_net, 0, RTNLGRP_DECnet_IFADDR, NULL, GFP_KERNEL); - return; -errout: - if (err < 0) - rtnl_set_sk_err(&init_net, RTNLGRP_DECnet_IFADDR, err); -} - -static int dn_nl_dump_ifaddr(struct sk_buff *skb, struct netlink_callback *cb) -{ - struct net *net = sock_net(skb->sk); - int idx, dn_idx = 0, skip_ndevs, skip_naddr; - struct net_device *dev; - struct dn_dev *dn_db; - struct dn_ifaddr *ifa; - - if (!net_eq(net, &init_net)) - return 0; - - skip_ndevs = cb->args[0]; - skip_naddr = cb->args[1]; - - idx = 0; - rcu_read_lock(); - for_each_netdev_rcu(&init_net, dev) { - if (idx < skip_ndevs) - goto cont; - else if (idx > skip_ndevs) { - /* Only skip over addresses for first dev dumped - * in this iteration (idx == skip_ndevs) */ - skip_naddr = 0; - } - - if ((dn_db = rcu_dereference(dev->dn_ptr)) == NULL) - goto cont; - - for (ifa = rcu_dereference(dn_db->ifa_list), dn_idx = 0; ifa; - ifa = rcu_dereference(ifa->ifa_next), dn_idx++) { - if (dn_idx < skip_naddr) - continue; - - if (dn_nl_fill_ifaddr(skb, ifa, NETLINK_CB(cb->skb).portid, - cb->nlh->nlmsg_seq, RTM_NEWADDR, - NLM_F_MULTI) < 0) - goto done; - } -cont: - idx++; - } -done: - rcu_read_unlock(); - cb->args[0] = idx; - cb->args[1] = dn_idx; - - return skb->len; -} - -static int dn_dev_get_first(struct net_device *dev, __le16 *addr) -{ - struct dn_dev *dn_db; - struct dn_ifaddr *ifa; - int rv = -ENODEV; - - rcu_read_lock(); - dn_db = rcu_dereference(dev->dn_ptr); - if (dn_db == NULL) - goto out; - - ifa = rcu_dereference(dn_db->ifa_list); - if (ifa != NULL) { - *addr = ifa->ifa_local; - rv = 0; - } -out: - rcu_read_unlock(); - return rv; -} - -/* - * Find a default address to bind to. - * - * This is one of those areas where the initial VMS concepts don't really - * map onto the Linux concepts, and since we introduced multiple addresses - * per interface we have to cope with slightly odd ways of finding out what - * "our address" really is. Mostly it's not a problem; for this we just guess - * a sensible default. Eventually the routing code will take care of all the - * nasties for us I hope. - */ -int dn_dev_bind_default(__le16 *addr) -{ - struct net_device *dev; - int rv; - dev = dn_dev_get_default(); -last_chance: - if (dev) { - rv = dn_dev_get_first(dev, addr); - dev_put(dev); - if (rv == 0 || dev == init_net.loopback_dev) - return rv; - } - dev = init_net.loopback_dev; - dev_hold(dev); - goto last_chance; -} - -static void dn_send_endnode_hello(struct net_device *dev, struct dn_ifaddr *ifa) -{ - struct endnode_hello_message *msg; - struct sk_buff *skb = NULL; - __le16 *pktlen; - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - - if ((skb = dn_alloc_skb(NULL, sizeof(*msg), GFP_ATOMIC)) == NULL) - return; - - skb->dev = dev; - - msg = skb_put(skb, sizeof(*msg)); - - msg->msgflg = 0x0D; - memcpy(msg->tiver, dn_eco_version, 3); - dn_dn2eth(msg->id, ifa->ifa_local); - msg->iinfo = DN_RT_INFO_ENDN; - msg->blksize = cpu_to_le16(mtu2blksize(dev)); - msg->area = 0x00; - memset(msg->seed, 0, 8); - memcpy(msg->neighbor, dn_hiord, ETH_ALEN); - - if (dn_db->router) { - struct dn_neigh *dn = (struct dn_neigh *)dn_db->router; - dn_dn2eth(msg->neighbor, dn->addr); - } - - msg->timer = cpu_to_le16((unsigned short)dn_db->parms.t3); - msg->mpd = 0x00; - msg->datalen = 0x02; - memset(msg->data, 0xAA, 2); - - pktlen = skb_push(skb, 2); - *pktlen = cpu_to_le16(skb->len - 2); - - skb_reset_network_header(skb); - - dn_rt_finish_output(skb, dn_rt_all_rt_mcast, msg->id); -} - - -#define DRDELAY (5 * HZ) - -static int dn_am_i_a_router(struct dn_neigh *dn, struct dn_dev *dn_db, struct dn_ifaddr *ifa) -{ - /* First check time since device went up */ - if (time_before(jiffies, dn_db->uptime + DRDELAY)) - return 0; - - /* If there is no router, then yes... */ - if (!dn_db->router) - return 1; - - /* otherwise only if we have a higher priority or.. */ - if (dn->priority < dn_db->parms.priority) - return 1; - - /* if we have equal priority and a higher node number */ - if (dn->priority != dn_db->parms.priority) - return 0; - - if (le16_to_cpu(dn->addr) < le16_to_cpu(ifa->ifa_local)) - return 1; - - return 0; -} - -static void dn_send_router_hello(struct net_device *dev, struct dn_ifaddr *ifa) -{ - int n; - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - struct dn_neigh *dn = (struct dn_neigh *)dn_db->router; - struct sk_buff *skb; - size_t size; - unsigned char *ptr; - unsigned char *i1, *i2; - __le16 *pktlen; - char *src; - - if (mtu2blksize(dev) < (26 + 7)) - return; - - n = mtu2blksize(dev) - 26; - n /= 7; - - if (n > 32) - n = 32; - - size = 2 + 26 + 7 * n; - - if ((skb = dn_alloc_skb(NULL, size, GFP_ATOMIC)) == NULL) - return; - - skb->dev = dev; - ptr = skb_put(skb, size); - - *ptr++ = DN_RT_PKT_CNTL | DN_RT_PKT_ERTH; - *ptr++ = 2; /* ECO */ - *ptr++ = 0; - *ptr++ = 0; - dn_dn2eth(ptr, ifa->ifa_local); - src = ptr; - ptr += ETH_ALEN; - *ptr++ = dn_db->parms.forwarding == 1 ? - DN_RT_INFO_L1RT : DN_RT_INFO_L2RT; - *((__le16 *)ptr) = cpu_to_le16(mtu2blksize(dev)); - ptr += 2; - *ptr++ = dn_db->parms.priority; /* Priority */ - *ptr++ = 0; /* Area: Reserved */ - *((__le16 *)ptr) = cpu_to_le16((unsigned short)dn_db->parms.t3); - ptr += 2; - *ptr++ = 0; /* MPD: Reserved */ - i1 = ptr++; - memset(ptr, 0, 7); /* Name: Reserved */ - ptr += 7; - i2 = ptr++; - - n = dn_neigh_elist(dev, ptr, n); - - *i2 = 7 * n; - *i1 = 8 + *i2; - - skb_trim(skb, (27 + *i2)); - - pktlen = skb_push(skb, 2); - *pktlen = cpu_to_le16(skb->len - 2); - - skb_reset_network_header(skb); - - if (dn_am_i_a_router(dn, dn_db, ifa)) { - struct sk_buff *skb2 = skb_copy(skb, GFP_ATOMIC); - if (skb2) { - dn_rt_finish_output(skb2, dn_rt_all_end_mcast, src); - } - } - - dn_rt_finish_output(skb, dn_rt_all_rt_mcast, src); -} - -static void dn_send_brd_hello(struct net_device *dev, struct dn_ifaddr *ifa) -{ - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - - if (dn_db->parms.forwarding == 0) - dn_send_endnode_hello(dev, ifa); - else - dn_send_router_hello(dev, ifa); -} - -static void dn_send_ptp_hello(struct net_device *dev, struct dn_ifaddr *ifa) -{ - int tdlen = 16; - int size = dev->hard_header_len + 2 + 4 + tdlen; - struct sk_buff *skb = dn_alloc_skb(NULL, size, GFP_ATOMIC); - int i; - unsigned char *ptr; - char src[ETH_ALEN]; - - if (skb == NULL) - return ; - - skb->dev = dev; - skb_push(skb, dev->hard_header_len); - ptr = skb_put(skb, 2 + 4 + tdlen); - - *ptr++ = DN_RT_PKT_HELO; - *((__le16 *)ptr) = ifa->ifa_local; - ptr += 2; - *ptr++ = tdlen; - - for(i = 0; i < tdlen; i++) - *ptr++ = 0252; - - dn_dn2eth(src, ifa->ifa_local); - dn_rt_finish_output(skb, dn_rt_all_rt_mcast, src); -} - -static int dn_eth_up(struct net_device *dev) -{ - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - - if (dn_db->parms.forwarding == 0) - dev_mc_add(dev, dn_rt_all_end_mcast); - else - dev_mc_add(dev, dn_rt_all_rt_mcast); - - dn_db->use_long = 1; - - return 0; -} - -static void dn_eth_down(struct net_device *dev) -{ - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - - if (dn_db->parms.forwarding == 0) - dev_mc_del(dev, dn_rt_all_end_mcast); - else - dev_mc_del(dev, dn_rt_all_rt_mcast); -} - -static void dn_dev_set_timer(struct net_device *dev); - -static void dn_dev_timer_func(struct timer_list *t) -{ - struct dn_dev *dn_db = from_timer(dn_db, t, timer); - struct net_device *dev; - struct dn_ifaddr *ifa; - - rcu_read_lock(); - dev = dn_db->dev; - if (dn_db->t3 <= dn_db->parms.t2) { - if (dn_db->parms.timer3) { - for (ifa = rcu_dereference(dn_db->ifa_list); - ifa; - ifa = rcu_dereference(ifa->ifa_next)) { - if (!(ifa->ifa_flags & IFA_F_SECONDARY)) - dn_db->parms.timer3(dev, ifa); - } - } - dn_db->t3 = dn_db->parms.t3; - } else { - dn_db->t3 -= dn_db->parms.t2; - } - rcu_read_unlock(); - dn_dev_set_timer(dev); -} - -static void dn_dev_set_timer(struct net_device *dev) -{ - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - - if (dn_db->parms.t2 > dn_db->parms.t3) - dn_db->parms.t2 = dn_db->parms.t3; - - dn_db->timer.expires = jiffies + (dn_db->parms.t2 * HZ); - - add_timer(&dn_db->timer); -} - -static struct dn_dev *dn_dev_create(struct net_device *dev, int *err) -{ - int i; - struct dn_dev_parms *p = dn_dev_list; - struct dn_dev *dn_db; - - for(i = 0; i < DN_DEV_LIST_SIZE; i++, p++) { - if (p->type == dev->type) - break; - } - - *err = -ENODEV; - if (i == DN_DEV_LIST_SIZE) - return NULL; - - *err = -ENOBUFS; - if ((dn_db = kzalloc(sizeof(struct dn_dev), GFP_ATOMIC)) == NULL) - return NULL; - - memcpy(&dn_db->parms, p, sizeof(struct dn_dev_parms)); - - rcu_assign_pointer(dev->dn_ptr, dn_db); - dn_db->dev = dev; - timer_setup(&dn_db->timer, dn_dev_timer_func, 0); - - dn_db->uptime = jiffies; - - dn_db->neigh_parms = neigh_parms_alloc(dev, &dn_neigh_table); - if (!dn_db->neigh_parms) { - RCU_INIT_POINTER(dev->dn_ptr, NULL); - kfree(dn_db); - return NULL; - } - - if (dn_db->parms.up) { - if (dn_db->parms.up(dev) < 0) { - neigh_parms_release(&dn_neigh_table, dn_db->neigh_parms); - dev->dn_ptr = NULL; - kfree(dn_db); - return NULL; - } - } - - dn_dev_sysctl_register(dev, &dn_db->parms); - - dn_dev_set_timer(dev); - - *err = 0; - return dn_db; -} - - -/* - * This processes a device up event. We only start up - * the loopback device & ethernet devices with correct - * MAC addresses automatically. Others must be started - * specifically. - * - * FIXME: How should we configure the loopback address ? If we could dispense - * with using decnet_address here and for autobind, it will be one less thing - * for users to worry about setting up. - */ - -void dn_dev_up(struct net_device *dev) -{ - struct dn_ifaddr *ifa; - __le16 addr = decnet_address; - int maybe_default = 0; - struct dn_dev *dn_db = rtnl_dereference(dev->dn_ptr); - - if ((dev->type != ARPHRD_ETHER) && (dev->type != ARPHRD_LOOPBACK)) - return; - - /* - * Need to ensure that loopback device has a dn_db attached to it - * to allow creation of neighbours against it, even though it might - * not have a local address of its own. Might as well do the same for - * all autoconfigured interfaces. - */ - if (dn_db == NULL) { - int err; - dn_db = dn_dev_create(dev, &err); - if (dn_db == NULL) - return; - } - - if (dev->type == ARPHRD_ETHER) { - if (memcmp(dev->dev_addr, dn_hiord, 4) != 0) - return; - addr = dn_eth2dn(dev->dev_addr); - maybe_default = 1; - } - - if (addr == 0) - return; - - if ((ifa = dn_dev_alloc_ifa()) == NULL) - return; - - ifa->ifa_local = ifa->ifa_address = addr; - ifa->ifa_flags = 0; - ifa->ifa_scope = RT_SCOPE_UNIVERSE; - strcpy(ifa->ifa_label, dev->name); - - dn_dev_set_ifa(dev, ifa); - - /* - * Automagically set the default device to the first automatically - * configured ethernet card in the system. - */ - if (maybe_default) { - dev_hold(dev); - if (dn_dev_set_default(dev, 0)) - dev_put(dev); - } -} - -static void dn_dev_delete(struct net_device *dev) -{ - struct dn_dev *dn_db = rtnl_dereference(dev->dn_ptr); - - if (dn_db == NULL) - return; - - del_timer_sync(&dn_db->timer); - dn_dev_sysctl_unregister(&dn_db->parms); - dn_dev_check_default(dev); - neigh_ifdown(&dn_neigh_table, dev); - - if (dn_db->parms.down) - dn_db->parms.down(dev); - - dev->dn_ptr = NULL; - - neigh_parms_release(&dn_neigh_table, dn_db->neigh_parms); - neigh_ifdown(&dn_neigh_table, dev); - - if (dn_db->router) - neigh_release(dn_db->router); - if (dn_db->peer) - neigh_release(dn_db->peer); - - kfree(dn_db); -} - -void dn_dev_down(struct net_device *dev) -{ - struct dn_dev *dn_db = rtnl_dereference(dev->dn_ptr); - struct dn_ifaddr *ifa; - - if (dn_db == NULL) - return; - - while ((ifa = rtnl_dereference(dn_db->ifa_list)) != NULL) { - dn_dev_del_ifa(dn_db, &dn_db->ifa_list, 0); - dn_dev_free_ifa(ifa); - } - - dn_dev_delete(dev); -} - -void dn_dev_init_pkt(struct sk_buff *skb) -{ -} - -void dn_dev_veri_pkt(struct sk_buff *skb) -{ -} - -void dn_dev_hello(struct sk_buff *skb) -{ -} - -void dn_dev_devices_off(void) -{ - struct net_device *dev; - - rtnl_lock(); - for_each_netdev(&init_net, dev) - dn_dev_down(dev); - rtnl_unlock(); - -} - -void dn_dev_devices_on(void) -{ - struct net_device *dev; - - rtnl_lock(); - for_each_netdev(&init_net, dev) { - if (dev->flags & IFF_UP) - dn_dev_up(dev); - } - rtnl_unlock(); -} - -int register_dnaddr_notifier(struct notifier_block *nb) -{ - return blocking_notifier_chain_register(&dnaddr_chain, nb); -} - -int unregister_dnaddr_notifier(struct notifier_block *nb) -{ - return blocking_notifier_chain_unregister(&dnaddr_chain, nb); -} - -#ifdef CONFIG_PROC_FS -static inline int is_dn_dev(struct net_device *dev) -{ - return dev->dn_ptr != NULL; -} - -static void *dn_dev_seq_start(struct seq_file *seq, loff_t *pos) - __acquires(RCU) -{ - int i; - struct net_device *dev; - - rcu_read_lock(); - - if (*pos == 0) - return SEQ_START_TOKEN; - - i = 1; - for_each_netdev_rcu(&init_net, dev) { - if (!is_dn_dev(dev)) - continue; - - if (i++ == *pos) - return dev; - } - - return NULL; -} - -static void *dn_dev_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct net_device *dev; - - ++*pos; - - dev = v; - if (v == SEQ_START_TOKEN) - dev = net_device_entry(&init_net.dev_base_head); - - for_each_netdev_continue_rcu(&init_net, dev) { - if (!is_dn_dev(dev)) - continue; - - return dev; - } - - return NULL; -} - -static void dn_dev_seq_stop(struct seq_file *seq, void *v) - __releases(RCU) -{ - rcu_read_unlock(); -} - -static char *dn_type2asc(char type) -{ - switch (type) { - case DN_DEV_BCAST: - return "B"; - case DN_DEV_UCAST: - return "U"; - case DN_DEV_MPOINT: - return "M"; - } - - return "?"; -} - -static int dn_dev_seq_show(struct seq_file *seq, void *v) -{ - if (v == SEQ_START_TOKEN) - seq_puts(seq, "Name Flags T1 Timer1 T3 Timer3 BlkSize Pri State DevType Router Peer\n"); - else { - struct net_device *dev = v; - char peer_buf[DN_ASCBUF_LEN]; - char router_buf[DN_ASCBUF_LEN]; - struct dn_dev *dn_db = rcu_dereference(dev->dn_ptr); - - seq_printf(seq, "%-8s %1s %04u %04u %04lu %04lu" - " %04hu %03d %02x %-10s %-7s %-7s\n", - dev->name ? dev->name : "???", - dn_type2asc(dn_db->parms.mode), - 0, 0, - dn_db->t3, dn_db->parms.t3, - mtu2blksize(dev), - dn_db->parms.priority, - dn_db->parms.state, dn_db->parms.name, - dn_db->router ? dn_addr2asc(le16_to_cpu(*(__le16 *)dn_db->router->primary_key), router_buf) : "", - dn_db->peer ? dn_addr2asc(le16_to_cpu(*(__le16 *)dn_db->peer->primary_key), peer_buf) : ""); - } - return 0; -} - -static const struct seq_operations dn_dev_seq_ops = { - .start = dn_dev_seq_start, - .next = dn_dev_seq_next, - .stop = dn_dev_seq_stop, - .show = dn_dev_seq_show, -}; -#endif /* CONFIG_PROC_FS */ - -static int addr[2]; -module_param_array(addr, int, NULL, 0444); -MODULE_PARM_DESC(addr, "The DECnet address of this machine: area,node"); - -void __init dn_dev_init(void) -{ - if (addr[0] > 63 || addr[0] < 0) { - printk(KERN_ERR "DECnet: Area must be between 0 and 63"); - return; - } - - if (addr[1] > 1023 || addr[1] < 0) { - printk(KERN_ERR "DECnet: Node must be between 0 and 1023"); - return; - } - - decnet_address = cpu_to_le16((addr[0] << 10) | addr[1]); - - dn_dev_devices_on(); - - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_NEWADDR, - dn_nl_newaddr, NULL, 0); - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_DELADDR, - dn_nl_deladdr, NULL, 0); - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_GETADDR, - NULL, dn_nl_dump_ifaddr, 0); - - proc_create_seq("decnet_dev", 0444, init_net.proc_net, &dn_dev_seq_ops); - -#ifdef CONFIG_SYSCTL - { - int i; - for(i = 0; i < DN_DEV_LIST_SIZE; i++) - dn_dev_sysctl_register(NULL, &dn_dev_list[i]); - } -#endif /* CONFIG_SYSCTL */ -} - -void __exit dn_dev_cleanup(void) -{ -#ifdef CONFIG_SYSCTL - { - int i; - for(i = 0; i < DN_DEV_LIST_SIZE; i++) - dn_dev_sysctl_unregister(&dn_dev_list[i]); - } -#endif /* CONFIG_SYSCTL */ - - remove_proc_entry("decnet_dev", init_net.proc_net); - - dn_dev_devices_off(); -} diff --git a/net/decnet/dn_fib.c b/net/decnet/dn_fib.c deleted file mode 100644 index f78fe58eafc82dba194d16d0627608440003f545..0000000000000000000000000000000000000000 --- a/net/decnet/dn_fib.c +++ /dev/null @@ -1,799 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Routing Forwarding Information Base (Glue/Info List) - * - * Author: Steve Whitehouse - * - * - * Changes: - * Alexey Kuznetsov : SMP locking changes - * Steve Whitehouse : Rewrote it... Well to be more correct, I - * copied most of it from the ipv4 fib code. - * Steve Whitehouse : Updated it in style and fixed a few bugs - * which were fixed in the ipv4 code since - * this code was copied from it. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define RT_MIN_TABLE 1 - -#define for_fib_info() { struct dn_fib_info *fi;\ - for(fi = dn_fib_info_list; fi; fi = fi->fib_next) -#define endfor_fib_info() } - -#define for_nexthops(fi) { int nhsel; const struct dn_fib_nh *nh;\ - for(nhsel = 0, nh = (fi)->fib_nh; nhsel < (fi)->fib_nhs; nh++, nhsel++) - -#define change_nexthops(fi) { int nhsel; struct dn_fib_nh *nh;\ - for(nhsel = 0, nh = (struct dn_fib_nh *)((fi)->fib_nh); nhsel < (fi)->fib_nhs; nh++, nhsel++) - -#define endfor_nexthops(fi) } - -static DEFINE_SPINLOCK(dn_fib_multipath_lock); -static struct dn_fib_info *dn_fib_info_list; -static DEFINE_SPINLOCK(dn_fib_info_lock); - -static struct -{ - int error; - u8 scope; -} dn_fib_props[RTN_MAX+1] = { - [RTN_UNSPEC] = { .error = 0, .scope = RT_SCOPE_NOWHERE }, - [RTN_UNICAST] = { .error = 0, .scope = RT_SCOPE_UNIVERSE }, - [RTN_LOCAL] = { .error = 0, .scope = RT_SCOPE_HOST }, - [RTN_BROADCAST] = { .error = -EINVAL, .scope = RT_SCOPE_NOWHERE }, - [RTN_ANYCAST] = { .error = -EINVAL, .scope = RT_SCOPE_NOWHERE }, - [RTN_MULTICAST] = { .error = -EINVAL, .scope = RT_SCOPE_NOWHERE }, - [RTN_BLACKHOLE] = { .error = -EINVAL, .scope = RT_SCOPE_UNIVERSE }, - [RTN_UNREACHABLE] = { .error = -EHOSTUNREACH, .scope = RT_SCOPE_UNIVERSE }, - [RTN_PROHIBIT] = { .error = -EACCES, .scope = RT_SCOPE_UNIVERSE }, - [RTN_THROW] = { .error = -EAGAIN, .scope = RT_SCOPE_UNIVERSE }, - [RTN_NAT] = { .error = 0, .scope = RT_SCOPE_NOWHERE }, - [RTN_XRESOLVE] = { .error = -EINVAL, .scope = RT_SCOPE_NOWHERE }, -}; - -static int dn_fib_sync_down(__le16 local, struct net_device *dev, int force); -static int dn_fib_sync_up(struct net_device *dev); - -void dn_fib_free_info(struct dn_fib_info *fi) -{ - if (fi->fib_dead == 0) { - printk(KERN_DEBUG "DECnet: BUG! Attempt to free alive dn_fib_info\n"); - return; - } - - change_nexthops(fi) { - if (nh->nh_dev) - dev_put(nh->nh_dev); - nh->nh_dev = NULL; - } endfor_nexthops(fi); - kfree(fi); -} - -void dn_fib_release_info(struct dn_fib_info *fi) -{ - spin_lock(&dn_fib_info_lock); - if (fi && --fi->fib_treeref == 0) { - if (fi->fib_next) - fi->fib_next->fib_prev = fi->fib_prev; - if (fi->fib_prev) - fi->fib_prev->fib_next = fi->fib_next; - if (fi == dn_fib_info_list) - dn_fib_info_list = fi->fib_next; - fi->fib_dead = 1; - dn_fib_info_put(fi); - } - spin_unlock(&dn_fib_info_lock); -} - -static inline int dn_fib_nh_comp(const struct dn_fib_info *fi, const struct dn_fib_info *ofi) -{ - const struct dn_fib_nh *onh = ofi->fib_nh; - - for_nexthops(fi) { - if (nh->nh_oif != onh->nh_oif || - nh->nh_gw != onh->nh_gw || - nh->nh_scope != onh->nh_scope || - nh->nh_weight != onh->nh_weight || - ((nh->nh_flags^onh->nh_flags)&~RTNH_F_DEAD)) - return -1; - onh++; - } endfor_nexthops(fi); - return 0; -} - -static inline struct dn_fib_info *dn_fib_find_info(const struct dn_fib_info *nfi) -{ - for_fib_info() { - if (fi->fib_nhs != nfi->fib_nhs) - continue; - if (nfi->fib_protocol == fi->fib_protocol && - nfi->fib_prefsrc == fi->fib_prefsrc && - nfi->fib_priority == fi->fib_priority && - memcmp(nfi->fib_metrics, fi->fib_metrics, sizeof(fi->fib_metrics)) == 0 && - ((nfi->fib_flags^fi->fib_flags)&~RTNH_F_DEAD) == 0 && - (nfi->fib_nhs == 0 || dn_fib_nh_comp(fi, nfi) == 0)) - return fi; - } endfor_fib_info(); - return NULL; -} - -static int dn_fib_count_nhs(const struct nlattr *attr) -{ - struct rtnexthop *nhp = nla_data(attr); - int nhs = 0, nhlen = nla_len(attr); - - while (rtnh_ok(nhp, nhlen)) { - nhs++; - nhp = rtnh_next(nhp, &nhlen); - } - - /* leftover implies invalid nexthop configuration, discard it */ - return nhlen > 0 ? 0 : nhs; -} - -static int dn_fib_get_nhs(struct dn_fib_info *fi, const struct nlattr *attr, - const struct rtmsg *r) -{ - struct rtnexthop *nhp = nla_data(attr); - int nhlen = nla_len(attr); - - change_nexthops(fi) { - int attrlen; - - if (!rtnh_ok(nhp, nhlen)) - return -EINVAL; - - nh->nh_flags = (r->rtm_flags&~0xFF) | nhp->rtnh_flags; - nh->nh_oif = nhp->rtnh_ifindex; - nh->nh_weight = nhp->rtnh_hops + 1; - - attrlen = rtnh_attrlen(nhp); - if (attrlen > 0) { - struct nlattr *gw_attr; - - gw_attr = nla_find((struct nlattr *) (nhp + 1), attrlen, RTA_GATEWAY); - nh->nh_gw = gw_attr ? nla_get_le16(gw_attr) : 0; - } - - nhp = rtnh_next(nhp, &nhlen); - } endfor_nexthops(fi); - - return 0; -} - - -static int dn_fib_check_nh(const struct rtmsg *r, struct dn_fib_info *fi, struct dn_fib_nh *nh) -{ - int err; - - if (nh->nh_gw) { - struct flowidn fld; - struct dn_fib_res res; - - if (nh->nh_flags&RTNH_F_ONLINK) { - struct net_device *dev; - - if (r->rtm_scope >= RT_SCOPE_LINK) - return -EINVAL; - if (dnet_addr_type(nh->nh_gw) != RTN_UNICAST) - return -EINVAL; - if ((dev = __dev_get_by_index(&init_net, nh->nh_oif)) == NULL) - return -ENODEV; - if (!(dev->flags&IFF_UP)) - return -ENETDOWN; - nh->nh_dev = dev; - dev_hold(dev); - nh->nh_scope = RT_SCOPE_LINK; - return 0; - } - - memset(&fld, 0, sizeof(fld)); - fld.daddr = nh->nh_gw; - fld.flowidn_oif = nh->nh_oif; - fld.flowidn_scope = r->rtm_scope + 1; - - if (fld.flowidn_scope < RT_SCOPE_LINK) - fld.flowidn_scope = RT_SCOPE_LINK; - - if ((err = dn_fib_lookup(&fld, &res)) != 0) - return err; - - err = -EINVAL; - if (res.type != RTN_UNICAST && res.type != RTN_LOCAL) - goto out; - nh->nh_scope = res.scope; - nh->nh_oif = DN_FIB_RES_OIF(res); - nh->nh_dev = DN_FIB_RES_DEV(res); - if (nh->nh_dev == NULL) - goto out; - dev_hold(nh->nh_dev); - err = -ENETDOWN; - if (!(nh->nh_dev->flags & IFF_UP)) - goto out; - err = 0; -out: - dn_fib_res_put(&res); - return err; - } else { - struct net_device *dev; - - if (nh->nh_flags&(RTNH_F_PERVASIVE|RTNH_F_ONLINK)) - return -EINVAL; - - dev = __dev_get_by_index(&init_net, nh->nh_oif); - if (dev == NULL || dev->dn_ptr == NULL) - return -ENODEV; - if (!(dev->flags&IFF_UP)) - return -ENETDOWN; - nh->nh_dev = dev; - dev_hold(nh->nh_dev); - nh->nh_scope = RT_SCOPE_HOST; - } - - return 0; -} - - -struct dn_fib_info *dn_fib_create_info(const struct rtmsg *r, struct nlattr *attrs[], - const struct nlmsghdr *nlh, int *errp) -{ - int err; - struct dn_fib_info *fi = NULL; - struct dn_fib_info *ofi; - int nhs = 1; - - if (r->rtm_type > RTN_MAX) - goto err_inval; - - if (dn_fib_props[r->rtm_type].scope > r->rtm_scope) - goto err_inval; - - if (attrs[RTA_MULTIPATH] && - (nhs = dn_fib_count_nhs(attrs[RTA_MULTIPATH])) == 0) - goto err_inval; - - fi = kzalloc(sizeof(*fi)+nhs*sizeof(struct dn_fib_nh), GFP_KERNEL); - err = -ENOBUFS; - if (fi == NULL) - goto failure; - - fi->fib_protocol = r->rtm_protocol; - fi->fib_nhs = nhs; - fi->fib_flags = r->rtm_flags; - - if (attrs[RTA_PRIORITY]) - fi->fib_priority = nla_get_u32(attrs[RTA_PRIORITY]); - - if (attrs[RTA_METRICS]) { - struct nlattr *attr; - int rem; - - nla_for_each_nested(attr, attrs[RTA_METRICS], rem) { - int type = nla_type(attr); - - if (type) { - if (type > RTAX_MAX || type == RTAX_CC_ALGO || - nla_len(attr) < 4) - goto err_inval; - - fi->fib_metrics[type-1] = nla_get_u32(attr); - } - } - } - - if (attrs[RTA_PREFSRC]) - fi->fib_prefsrc = nla_get_le16(attrs[RTA_PREFSRC]); - - if (attrs[RTA_MULTIPATH]) { - if ((err = dn_fib_get_nhs(fi, attrs[RTA_MULTIPATH], r)) != 0) - goto failure; - - if (attrs[RTA_OIF] && - fi->fib_nh->nh_oif != nla_get_u32(attrs[RTA_OIF])) - goto err_inval; - - if (attrs[RTA_GATEWAY] && - fi->fib_nh->nh_gw != nla_get_le16(attrs[RTA_GATEWAY])) - goto err_inval; - } else { - struct dn_fib_nh *nh = fi->fib_nh; - - if (attrs[RTA_OIF]) - nh->nh_oif = nla_get_u32(attrs[RTA_OIF]); - - if (attrs[RTA_GATEWAY]) - nh->nh_gw = nla_get_le16(attrs[RTA_GATEWAY]); - - nh->nh_flags = r->rtm_flags; - nh->nh_weight = 1; - } - - if (r->rtm_type == RTN_NAT) { - if (!attrs[RTA_GATEWAY] || nhs != 1 || attrs[RTA_OIF]) - goto err_inval; - - fi->fib_nh->nh_gw = nla_get_le16(attrs[RTA_GATEWAY]); - goto link_it; - } - - if (dn_fib_props[r->rtm_type].error) { - if (attrs[RTA_GATEWAY] || attrs[RTA_OIF] || attrs[RTA_MULTIPATH]) - goto err_inval; - - goto link_it; - } - - if (r->rtm_scope > RT_SCOPE_HOST) - goto err_inval; - - if (r->rtm_scope == RT_SCOPE_HOST) { - struct dn_fib_nh *nh = fi->fib_nh; - - /* Local address is added */ - if (nhs != 1 || nh->nh_gw) - goto err_inval; - nh->nh_scope = RT_SCOPE_NOWHERE; - nh->nh_dev = dev_get_by_index(&init_net, fi->fib_nh->nh_oif); - err = -ENODEV; - if (nh->nh_dev == NULL) - goto failure; - } else { - change_nexthops(fi) { - if ((err = dn_fib_check_nh(r, fi, nh)) != 0) - goto failure; - } endfor_nexthops(fi) - } - - if (fi->fib_prefsrc) { - if (r->rtm_type != RTN_LOCAL || !attrs[RTA_DST] || - fi->fib_prefsrc != nla_get_le16(attrs[RTA_DST])) - if (dnet_addr_type(fi->fib_prefsrc) != RTN_LOCAL) - goto err_inval; - } - -link_it: - if ((ofi = dn_fib_find_info(fi)) != NULL) { - fi->fib_dead = 1; - dn_fib_free_info(fi); - ofi->fib_treeref++; - return ofi; - } - - fi->fib_treeref++; - refcount_set(&fi->fib_clntref, 1); - spin_lock(&dn_fib_info_lock); - fi->fib_next = dn_fib_info_list; - fi->fib_prev = NULL; - if (dn_fib_info_list) - dn_fib_info_list->fib_prev = fi; - dn_fib_info_list = fi; - spin_unlock(&dn_fib_info_lock); - return fi; - -err_inval: - err = -EINVAL; - -failure: - *errp = err; - if (fi) { - fi->fib_dead = 1; - dn_fib_free_info(fi); - } - - return NULL; -} - -int dn_fib_semantic_match(int type, struct dn_fib_info *fi, const struct flowidn *fld, struct dn_fib_res *res) -{ - int err = dn_fib_props[type].error; - - if (err == 0) { - if (fi->fib_flags & RTNH_F_DEAD) - return 1; - - res->fi = fi; - - switch (type) { - case RTN_NAT: - DN_FIB_RES_RESET(*res); - refcount_inc(&fi->fib_clntref); - return 0; - case RTN_UNICAST: - case RTN_LOCAL: - for_nexthops(fi) { - if (nh->nh_flags & RTNH_F_DEAD) - continue; - if (!fld->flowidn_oif || - fld->flowidn_oif == nh->nh_oif) - break; - } - if (nhsel < fi->fib_nhs) { - res->nh_sel = nhsel; - refcount_inc(&fi->fib_clntref); - return 0; - } - endfor_nexthops(fi); - res->fi = NULL; - return 1; - default: - net_err_ratelimited("DECnet: impossible routing event : dn_fib_semantic_match type=%d\n", - type); - res->fi = NULL; - return -EINVAL; - } - } - return err; -} - -void dn_fib_select_multipath(const struct flowidn *fld, struct dn_fib_res *res) -{ - struct dn_fib_info *fi = res->fi; - int w; - - spin_lock_bh(&dn_fib_multipath_lock); - if (fi->fib_power <= 0) { - int power = 0; - change_nexthops(fi) { - if (!(nh->nh_flags&RTNH_F_DEAD)) { - power += nh->nh_weight; - nh->nh_power = nh->nh_weight; - } - } endfor_nexthops(fi); - fi->fib_power = power; - if (power < 0) { - spin_unlock_bh(&dn_fib_multipath_lock); - res->nh_sel = 0; - return; - } - } - - w = jiffies % fi->fib_power; - - change_nexthops(fi) { - if (!(nh->nh_flags&RTNH_F_DEAD) && nh->nh_power) { - if ((w -= nh->nh_power) <= 0) { - nh->nh_power--; - fi->fib_power--; - res->nh_sel = nhsel; - spin_unlock_bh(&dn_fib_multipath_lock); - return; - } - } - } endfor_nexthops(fi); - res->nh_sel = 0; - spin_unlock_bh(&dn_fib_multipath_lock); -} - -static inline u32 rtm_get_table(struct nlattr *attrs[], u8 table) -{ - if (attrs[RTA_TABLE]) - table = nla_get_u32(attrs[RTA_TABLE]); - - return table; -} - -static int dn_fib_rtm_delroute(struct sk_buff *skb, struct nlmsghdr *nlh, - struct netlink_ext_ack *extack) -{ - struct net *net = sock_net(skb->sk); - struct dn_fib_table *tb; - struct rtmsg *r = nlmsg_data(nlh); - struct nlattr *attrs[RTA_MAX+1]; - int err; - - if (!netlink_capable(skb, CAP_NET_ADMIN)) - return -EPERM; - - if (!net_eq(net, &init_net)) - return -EINVAL; - - err = nlmsg_parse(nlh, sizeof(*r), attrs, RTA_MAX, rtm_dn_policy, - extack); - if (err < 0) - return err; - - tb = dn_fib_get_table(rtm_get_table(attrs, r->rtm_table), 0); - if (!tb) - return -ESRCH; - - return tb->delete(tb, r, attrs, nlh, &NETLINK_CB(skb)); -} - -static int dn_fib_rtm_newroute(struct sk_buff *skb, struct nlmsghdr *nlh, - struct netlink_ext_ack *extack) -{ - struct net *net = sock_net(skb->sk); - struct dn_fib_table *tb; - struct rtmsg *r = nlmsg_data(nlh); - struct nlattr *attrs[RTA_MAX+1]; - int err; - - if (!netlink_capable(skb, CAP_NET_ADMIN)) - return -EPERM; - - if (!net_eq(net, &init_net)) - return -EINVAL; - - err = nlmsg_parse(nlh, sizeof(*r), attrs, RTA_MAX, rtm_dn_policy, - extack); - if (err < 0) - return err; - - tb = dn_fib_get_table(rtm_get_table(attrs, r->rtm_table), 1); - if (!tb) - return -ENOBUFS; - - return tb->insert(tb, r, attrs, nlh, &NETLINK_CB(skb)); -} - -static void fib_magic(int cmd, int type, __le16 dst, int dst_len, struct dn_ifaddr *ifa) -{ - struct dn_fib_table *tb; - struct { - struct nlmsghdr nlh; - struct rtmsg rtm; - } req; - struct { - struct nlattr hdr; - __le16 dst; - } dst_attr = { - .dst = dst, - }; - struct { - struct nlattr hdr; - __le16 prefsrc; - } prefsrc_attr = { - .prefsrc = ifa->ifa_local, - }; - struct { - struct nlattr hdr; - u32 oif; - } oif_attr = { - .oif = ifa->ifa_dev->dev->ifindex, - }; - struct nlattr *attrs[RTA_MAX+1] = { - [RTA_DST] = (struct nlattr *) &dst_attr, - [RTA_PREFSRC] = (struct nlattr * ) &prefsrc_attr, - [RTA_OIF] = (struct nlattr *) &oif_attr, - }; - - memset(&req.rtm, 0, sizeof(req.rtm)); - - if (type == RTN_UNICAST) - tb = dn_fib_get_table(RT_MIN_TABLE, 1); - else - tb = dn_fib_get_table(RT_TABLE_LOCAL, 1); - - if (tb == NULL) - return; - - req.nlh.nlmsg_len = sizeof(req); - req.nlh.nlmsg_type = cmd; - req.nlh.nlmsg_flags = NLM_F_REQUEST|NLM_F_CREATE|NLM_F_APPEND; - req.nlh.nlmsg_pid = 0; - req.nlh.nlmsg_seq = 0; - - req.rtm.rtm_dst_len = dst_len; - req.rtm.rtm_table = tb->n; - req.rtm.rtm_protocol = RTPROT_KERNEL; - req.rtm.rtm_scope = (type != RTN_LOCAL ? RT_SCOPE_LINK : RT_SCOPE_HOST); - req.rtm.rtm_type = type; - - if (cmd == RTM_NEWROUTE) - tb->insert(tb, &req.rtm, attrs, &req.nlh, NULL); - else - tb->delete(tb, &req.rtm, attrs, &req.nlh, NULL); -} - -static void dn_fib_add_ifaddr(struct dn_ifaddr *ifa) -{ - - fib_magic(RTM_NEWROUTE, RTN_LOCAL, ifa->ifa_local, 16, ifa); - -#if 0 - if (!(dev->flags&IFF_UP)) - return; - /* In the future, we will want to add default routes here */ - -#endif -} - -static void dn_fib_del_ifaddr(struct dn_ifaddr *ifa) -{ - int found_it = 0; - struct net_device *dev; - struct dn_dev *dn_db; - struct dn_ifaddr *ifa2; - - ASSERT_RTNL(); - - /* Scan device list */ - rcu_read_lock(); - for_each_netdev_rcu(&init_net, dev) { - dn_db = rcu_dereference(dev->dn_ptr); - if (dn_db == NULL) - continue; - for (ifa2 = rcu_dereference(dn_db->ifa_list); - ifa2 != NULL; - ifa2 = rcu_dereference(ifa2->ifa_next)) { - if (ifa2->ifa_local == ifa->ifa_local) { - found_it = 1; - break; - } - } - } - rcu_read_unlock(); - - if (found_it == 0) { - fib_magic(RTM_DELROUTE, RTN_LOCAL, ifa->ifa_local, 16, ifa); - - if (dnet_addr_type(ifa->ifa_local) != RTN_LOCAL) { - if (dn_fib_sync_down(ifa->ifa_local, NULL, 0)) - dn_fib_flush(); - } - } -} - -static void dn_fib_disable_addr(struct net_device *dev, int force) -{ - if (dn_fib_sync_down(0, dev, force)) - dn_fib_flush(); - dn_rt_cache_flush(0); - neigh_ifdown(&dn_neigh_table, dev); -} - -static int dn_fib_dnaddr_event(struct notifier_block *this, unsigned long event, void *ptr) -{ - struct dn_ifaddr *ifa = (struct dn_ifaddr *)ptr; - - switch (event) { - case NETDEV_UP: - dn_fib_add_ifaddr(ifa); - dn_fib_sync_up(ifa->ifa_dev->dev); - dn_rt_cache_flush(-1); - break; - case NETDEV_DOWN: - dn_fib_del_ifaddr(ifa); - if (ifa->ifa_dev && ifa->ifa_dev->ifa_list == NULL) { - dn_fib_disable_addr(ifa->ifa_dev->dev, 1); - } else { - dn_rt_cache_flush(-1); - } - break; - } - return NOTIFY_DONE; -} - -static int dn_fib_sync_down(__le16 local, struct net_device *dev, int force) -{ - int ret = 0; - int scope = RT_SCOPE_NOWHERE; - - if (force) - scope = -1; - - for_fib_info() { - /* - * This makes no sense for DECnet.... we will almost - * certainly have more than one local address the same - * over all our interfaces. It needs thinking about - * some more. - */ - if (local && fi->fib_prefsrc == local) { - fi->fib_flags |= RTNH_F_DEAD; - ret++; - } else if (dev && fi->fib_nhs) { - int dead = 0; - - change_nexthops(fi) { - if (nh->nh_flags&RTNH_F_DEAD) - dead++; - else if (nh->nh_dev == dev && - nh->nh_scope != scope) { - spin_lock_bh(&dn_fib_multipath_lock); - nh->nh_flags |= RTNH_F_DEAD; - fi->fib_power -= nh->nh_power; - nh->nh_power = 0; - spin_unlock_bh(&dn_fib_multipath_lock); - dead++; - } - } endfor_nexthops(fi) - if (dead == fi->fib_nhs) { - fi->fib_flags |= RTNH_F_DEAD; - ret++; - } - } - } endfor_fib_info(); - return ret; -} - - -static int dn_fib_sync_up(struct net_device *dev) -{ - int ret = 0; - - if (!(dev->flags&IFF_UP)) - return 0; - - for_fib_info() { - int alive = 0; - - change_nexthops(fi) { - if (!(nh->nh_flags&RTNH_F_DEAD)) { - alive++; - continue; - } - if (nh->nh_dev == NULL || !(nh->nh_dev->flags&IFF_UP)) - continue; - if (nh->nh_dev != dev || dev->dn_ptr == NULL) - continue; - alive++; - spin_lock_bh(&dn_fib_multipath_lock); - nh->nh_power = 0; - nh->nh_flags &= ~RTNH_F_DEAD; - spin_unlock_bh(&dn_fib_multipath_lock); - } endfor_nexthops(fi); - - if (alive > 0) { - fi->fib_flags &= ~RTNH_F_DEAD; - ret++; - } - } endfor_fib_info(); - return ret; -} - -static struct notifier_block dn_fib_dnaddr_notifier = { - .notifier_call = dn_fib_dnaddr_event, -}; - -void __exit dn_fib_cleanup(void) -{ - dn_fib_table_cleanup(); - dn_fib_rules_cleanup(); - - unregister_dnaddr_notifier(&dn_fib_dnaddr_notifier); -} - - -void __init dn_fib_init(void) -{ - dn_fib_table_init(); - dn_fib_rules_init(); - - register_dnaddr_notifier(&dn_fib_dnaddr_notifier); - - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_NEWROUTE, - dn_fib_rtm_newroute, NULL, 0); - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_DELROUTE, - dn_fib_rtm_delroute, NULL, 0); -} diff --git a/net/decnet/dn_neigh.c b/net/decnet/dn_neigh.c deleted file mode 100644 index 94b306f6d5511b8fcd615c690c6e0dbf20a44f14..0000000000000000000000000000000000000000 --- a/net/decnet/dn_neigh.c +++ /dev/null @@ -1,605 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Neighbour Functions (Adjacency Database and - * On-Ethernet Cache) - * - * Author: Steve Whitehouse - * - * - * Changes: - * Steve Whitehouse : Fixed router listing routine - * Steve Whitehouse : Added error_report functions - * Steve Whitehouse : Added default router detection - * Steve Whitehouse : Hop counts in outgoing messages - * Steve Whitehouse : Fixed src/dst in outgoing messages so - * forwarding now stands a good chance of - * working. - * Steve Whitehouse : Fixed neighbour states (for now anyway). - * Steve Whitehouse : Made error_report functions dummies. This - * is not the right place to return skbs. - * Steve Whitehouse : Convert to seq_file - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static int dn_neigh_construct(struct neighbour *); -static void dn_neigh_error_report(struct neighbour *, struct sk_buff *); -static int dn_neigh_output(struct neighbour *neigh, struct sk_buff *skb); - -/* - * Operations for adding the link layer header. - */ -static const struct neigh_ops dn_neigh_ops = { - .family = AF_DECnet, - .error_report = dn_neigh_error_report, - .output = dn_neigh_output, - .connected_output = dn_neigh_output, -}; - -static u32 dn_neigh_hash(const void *pkey, - const struct net_device *dev, - __u32 *hash_rnd) -{ - return jhash_2words(*(__u16 *)pkey, 0, hash_rnd[0]); -} - -static bool dn_key_eq(const struct neighbour *neigh, const void *pkey) -{ - return neigh_key_eq16(neigh, pkey); -} - -struct neigh_table dn_neigh_table = { - .family = PF_DECnet, - .entry_size = NEIGH_ENTRY_SIZE(sizeof(struct dn_neigh)), - .key_len = sizeof(__le16), - .protocol = cpu_to_be16(ETH_P_DNA_RT), - .hash = dn_neigh_hash, - .key_eq = dn_key_eq, - .constructor = dn_neigh_construct, - .id = "dn_neigh_cache", - .parms ={ - .tbl = &dn_neigh_table, - .reachable_time = 30 * HZ, - .data = { - [NEIGH_VAR_MCAST_PROBES] = 0, - [NEIGH_VAR_UCAST_PROBES] = 0, - [NEIGH_VAR_APP_PROBES] = 0, - [NEIGH_VAR_RETRANS_TIME] = 1 * HZ, - [NEIGH_VAR_BASE_REACHABLE_TIME] = 30 * HZ, - [NEIGH_VAR_DELAY_PROBE_TIME] = 5 * HZ, - [NEIGH_VAR_GC_STALETIME] = 60 * HZ, - [NEIGH_VAR_QUEUE_LEN_BYTES] = SK_WMEM_MAX, - [NEIGH_VAR_PROXY_QLEN] = 0, - [NEIGH_VAR_ANYCAST_DELAY] = 0, - [NEIGH_VAR_PROXY_DELAY] = 0, - [NEIGH_VAR_LOCKTIME] = 1 * HZ, - }, - }, - .gc_interval = 30 * HZ, - .gc_thresh1 = 128, - .gc_thresh2 = 512, - .gc_thresh3 = 1024, -}; - -static int dn_neigh_construct(struct neighbour *neigh) -{ - struct net_device *dev = neigh->dev; - struct dn_neigh *dn = container_of(neigh, struct dn_neigh, n); - struct dn_dev *dn_db; - struct neigh_parms *parms; - - rcu_read_lock(); - dn_db = rcu_dereference(dev->dn_ptr); - if (dn_db == NULL) { - rcu_read_unlock(); - return -EINVAL; - } - - parms = dn_db->neigh_parms; - if (!parms) { - rcu_read_unlock(); - return -EINVAL; - } - - __neigh_parms_put(neigh->parms); - neigh->parms = neigh_parms_clone(parms); - rcu_read_unlock(); - - neigh->ops = &dn_neigh_ops; - neigh->nud_state = NUD_NOARP; - neigh->output = neigh->ops->connected_output; - - if ((dev->type == ARPHRD_IPGRE) || (dev->flags & IFF_POINTOPOINT)) - memcpy(neigh->ha, dev->broadcast, dev->addr_len); - else if ((dev->type == ARPHRD_ETHER) || (dev->type == ARPHRD_LOOPBACK)) - dn_dn2eth(neigh->ha, dn->addr); - else { - net_dbg_ratelimited("Trying to create neigh for hw %d\n", - dev->type); - return -EINVAL; - } - - /* - * Make an estimate of the remote block size by assuming that its - * two less then the device mtu, which it true for ethernet (and - * other things which support long format headers) since there is - * an extra length field (of 16 bits) which isn't part of the - * ethernet headers and which the DECnet specs won't admit is part - * of the DECnet routing headers either. - * - * If we over estimate here its no big deal, the NSP negotiations - * will prevent us from sending packets which are too large for the - * remote node to handle. In any case this figure is normally updated - * by a hello message in most cases. - */ - dn->blksize = dev->mtu - 2; - - return 0; -} - -static void dn_neigh_error_report(struct neighbour *neigh, struct sk_buff *skb) -{ - printk(KERN_DEBUG "dn_neigh_error_report: called\n"); - kfree_skb(skb); -} - -static int dn_neigh_output(struct neighbour *neigh, struct sk_buff *skb) -{ - struct dst_entry *dst = skb_dst(skb); - struct dn_route *rt = (struct dn_route *)dst; - struct net_device *dev = neigh->dev; - char mac_addr[ETH_ALEN]; - unsigned int seq; - int err; - - dn_dn2eth(mac_addr, rt->rt_local_src); - do { - seq = read_seqbegin(&neigh->ha_lock); - err = dev_hard_header(skb, dev, ntohs(skb->protocol), - neigh->ha, mac_addr, skb->len); - } while (read_seqretry(&neigh->ha_lock, seq)); - - if (err >= 0) - err = dev_queue_xmit(skb); - else { - kfree_skb(skb); - err = -EINVAL; - } - return err; -} - -static int dn_neigh_output_packet(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct dst_entry *dst = skb_dst(skb); - struct dn_route *rt = (struct dn_route *)dst; - struct neighbour *neigh = rt->n; - - return neigh->output(neigh, skb); -} - -/* - * For talking to broadcast devices: Ethernet & PPP - */ -static int dn_long_output(struct neighbour *neigh, struct sock *sk, - struct sk_buff *skb) -{ - struct net_device *dev = neigh->dev; - int headroom = dev->hard_header_len + sizeof(struct dn_long_packet) + 3; - unsigned char *data; - struct dn_long_packet *lp; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - - if (skb_headroom(skb) < headroom) { - struct sk_buff *skb2 = skb_realloc_headroom(skb, headroom); - if (skb2 == NULL) { - net_crit_ratelimited("dn_long_output: no memory\n"); - kfree_skb(skb); - return -ENOBUFS; - } - consume_skb(skb); - skb = skb2; - net_info_ratelimited("dn_long_output: Increasing headroom\n"); - } - - data = skb_push(skb, sizeof(struct dn_long_packet) + 3); - lp = (struct dn_long_packet *)(data+3); - - *((__le16 *)data) = cpu_to_le16(skb->len - 2); - *(data + 2) = 1 | DN_RT_F_PF; /* Padding */ - - lp->msgflg = DN_RT_PKT_LONG|(cb->rt_flags&(DN_RT_F_IE|DN_RT_F_RQR|DN_RT_F_RTS)); - lp->d_area = lp->d_subarea = 0; - dn_dn2eth(lp->d_id, cb->dst); - lp->s_area = lp->s_subarea = 0; - dn_dn2eth(lp->s_id, cb->src); - lp->nl2 = 0; - lp->visit_ct = cb->hops & 0x3f; - lp->s_class = 0; - lp->pt = 0; - - skb_reset_network_header(skb); - - return NF_HOOK(NFPROTO_DECNET, NF_DN_POST_ROUTING, - &init_net, sk, skb, NULL, neigh->dev, - dn_neigh_output_packet); -} - -/* - * For talking to pointopoint and multidrop devices: DDCMP and X.25 - */ -static int dn_short_output(struct neighbour *neigh, struct sock *sk, - struct sk_buff *skb) -{ - struct net_device *dev = neigh->dev; - int headroom = dev->hard_header_len + sizeof(struct dn_short_packet) + 2; - struct dn_short_packet *sp; - unsigned char *data; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - - if (skb_headroom(skb) < headroom) { - struct sk_buff *skb2 = skb_realloc_headroom(skb, headroom); - if (skb2 == NULL) { - net_crit_ratelimited("dn_short_output: no memory\n"); - kfree_skb(skb); - return -ENOBUFS; - } - consume_skb(skb); - skb = skb2; - net_info_ratelimited("dn_short_output: Increasing headroom\n"); - } - - data = skb_push(skb, sizeof(struct dn_short_packet) + 2); - *((__le16 *)data) = cpu_to_le16(skb->len - 2); - sp = (struct dn_short_packet *)(data+2); - - sp->msgflg = DN_RT_PKT_SHORT|(cb->rt_flags&(DN_RT_F_RQR|DN_RT_F_RTS)); - sp->dstnode = cb->dst; - sp->srcnode = cb->src; - sp->forward = cb->hops & 0x3f; - - skb_reset_network_header(skb); - - return NF_HOOK(NFPROTO_DECNET, NF_DN_POST_ROUTING, - &init_net, sk, skb, NULL, neigh->dev, - dn_neigh_output_packet); -} - -/* - * For talking to DECnet phase III nodes - * Phase 3 output is the same as short output, execpt that - * it clears the area bits before transmission. - */ -static int dn_phase3_output(struct neighbour *neigh, struct sock *sk, - struct sk_buff *skb) -{ - struct net_device *dev = neigh->dev; - int headroom = dev->hard_header_len + sizeof(struct dn_short_packet) + 2; - struct dn_short_packet *sp; - unsigned char *data; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - if (skb_headroom(skb) < headroom) { - struct sk_buff *skb2 = skb_realloc_headroom(skb, headroom); - if (skb2 == NULL) { - net_crit_ratelimited("dn_phase3_output: no memory\n"); - kfree_skb(skb); - return -ENOBUFS; - } - consume_skb(skb); - skb = skb2; - net_info_ratelimited("dn_phase3_output: Increasing headroom\n"); - } - - data = skb_push(skb, sizeof(struct dn_short_packet) + 2); - *((__le16 *)data) = cpu_to_le16(skb->len - 2); - sp = (struct dn_short_packet *)(data + 2); - - sp->msgflg = DN_RT_PKT_SHORT|(cb->rt_flags&(DN_RT_F_RQR|DN_RT_F_RTS)); - sp->dstnode = cb->dst & cpu_to_le16(0x03ff); - sp->srcnode = cb->src & cpu_to_le16(0x03ff); - sp->forward = cb->hops & 0x3f; - - skb_reset_network_header(skb); - - return NF_HOOK(NFPROTO_DECNET, NF_DN_POST_ROUTING, - &init_net, sk, skb, NULL, neigh->dev, - dn_neigh_output_packet); -} - -int dn_to_neigh_output(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct dst_entry *dst = skb_dst(skb); - struct dn_route *rt = (struct dn_route *) dst; - struct neighbour *neigh = rt->n; - struct dn_neigh *dn = container_of(neigh, struct dn_neigh, n); - struct dn_dev *dn_db; - bool use_long; - - rcu_read_lock(); - dn_db = rcu_dereference(neigh->dev->dn_ptr); - if (dn_db == NULL) { - rcu_read_unlock(); - return -EINVAL; - } - use_long = dn_db->use_long; - rcu_read_unlock(); - - if (dn->flags & DN_NDFLAG_P3) - return dn_phase3_output(neigh, sk, skb); - if (use_long) - return dn_long_output(neigh, sk, skb); - else - return dn_short_output(neigh, sk, skb); -} - -/* - * Unfortunately, the neighbour code uses the device in its hash - * function, so we don't get any advantage from it. This function - * basically does a neigh_lookup(), but without comparing the device - * field. This is required for the On-Ethernet cache - */ - -/* - * Pointopoint link receives a hello message - */ -void dn_neigh_pointopoint_hello(struct sk_buff *skb) -{ - kfree_skb(skb); -} - -/* - * Ethernet router hello message received - */ -int dn_neigh_router_hello(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct rtnode_hello_message *msg = (struct rtnode_hello_message *)skb->data; - - struct neighbour *neigh; - struct dn_neigh *dn; - struct dn_dev *dn_db; - __le16 src; - - src = dn_eth2dn(msg->id); - - neigh = __neigh_lookup(&dn_neigh_table, &src, skb->dev, 1); - - dn = container_of(neigh, struct dn_neigh, n); - - if (neigh) { - write_lock(&neigh->lock); - - neigh->used = jiffies; - dn_db = rcu_dereference(neigh->dev->dn_ptr); - - if (!(neigh->nud_state & NUD_PERMANENT)) { - neigh->updated = jiffies; - - if (neigh->dev->type == ARPHRD_ETHER) - memcpy(neigh->ha, ð_hdr(skb)->h_source, ETH_ALEN); - - dn->blksize = le16_to_cpu(msg->blksize); - dn->priority = msg->priority; - - dn->flags &= ~DN_NDFLAG_P3; - - switch (msg->iinfo & DN_RT_INFO_TYPE) { - case DN_RT_INFO_L1RT: - dn->flags &=~DN_NDFLAG_R2; - dn->flags |= DN_NDFLAG_R1; - break; - case DN_RT_INFO_L2RT: - dn->flags |= DN_NDFLAG_R2; - } - } - - /* Only use routers in our area */ - if ((le16_to_cpu(src)>>10) == (le16_to_cpu((decnet_address))>>10)) { - if (!dn_db->router) { - dn_db->router = neigh_clone(neigh); - } else { - if (msg->priority > ((struct dn_neigh *)dn_db->router)->priority) - neigh_release(xchg(&dn_db->router, neigh_clone(neigh))); - } - } - write_unlock(&neigh->lock); - neigh_release(neigh); - } - - kfree_skb(skb); - return 0; -} - -/* - * Endnode hello message received - */ -int dn_neigh_endnode_hello(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct endnode_hello_message *msg = (struct endnode_hello_message *)skb->data; - struct neighbour *neigh; - struct dn_neigh *dn; - __le16 src; - - src = dn_eth2dn(msg->id); - - neigh = __neigh_lookup(&dn_neigh_table, &src, skb->dev, 1); - - dn = container_of(neigh, struct dn_neigh, n); - - if (neigh) { - write_lock(&neigh->lock); - - neigh->used = jiffies; - - if (!(neigh->nud_state & NUD_PERMANENT)) { - neigh->updated = jiffies; - - if (neigh->dev->type == ARPHRD_ETHER) - memcpy(neigh->ha, ð_hdr(skb)->h_source, ETH_ALEN); - dn->flags &= ~(DN_NDFLAG_R1 | DN_NDFLAG_R2); - dn->blksize = le16_to_cpu(msg->blksize); - dn->priority = 0; - } - - write_unlock(&neigh->lock); - neigh_release(neigh); - } - - kfree_skb(skb); - return 0; -} - -static char *dn_find_slot(char *base, int max, int priority) -{ - int i; - unsigned char *min = NULL; - - base += 6; /* skip first id */ - - for(i = 0; i < max; i++) { - if (!min || (*base < *min)) - min = base; - base += 7; /* find next priority */ - } - - if (!min) - return NULL; - - return (*min < priority) ? (min - 6) : NULL; -} - -struct elist_cb_state { - struct net_device *dev; - unsigned char *ptr; - unsigned char *rs; - int t, n; -}; - -static void neigh_elist_cb(struct neighbour *neigh, void *_info) -{ - struct elist_cb_state *s = _info; - struct dn_neigh *dn; - - if (neigh->dev != s->dev) - return; - - dn = container_of(neigh, struct dn_neigh, n); - if (!(dn->flags & (DN_NDFLAG_R1|DN_NDFLAG_R2))) - return; - - if (s->t == s->n) - s->rs = dn_find_slot(s->ptr, s->n, dn->priority); - else - s->t++; - if (s->rs == NULL) - return; - - dn_dn2eth(s->rs, dn->addr); - s->rs += 6; - *(s->rs) = neigh->nud_state & NUD_CONNECTED ? 0x80 : 0x0; - *(s->rs) |= dn->priority; - s->rs++; -} - -int dn_neigh_elist(struct net_device *dev, unsigned char *ptr, int n) -{ - struct elist_cb_state state; - - state.dev = dev; - state.t = 0; - state.n = n; - state.ptr = ptr; - state.rs = ptr; - - neigh_for_each(&dn_neigh_table, neigh_elist_cb, &state); - - return state.t; -} - - -#ifdef CONFIG_PROC_FS - -static inline void dn_neigh_format_entry(struct seq_file *seq, - struct neighbour *n) -{ - struct dn_neigh *dn = container_of(n, struct dn_neigh, n); - char buf[DN_ASCBUF_LEN]; - - read_lock(&n->lock); - seq_printf(seq, "%-7s %s%s%s %02x %02d %07ld %-8s\n", - dn_addr2asc(le16_to_cpu(dn->addr), buf), - (dn->flags&DN_NDFLAG_R1) ? "1" : "-", - (dn->flags&DN_NDFLAG_R2) ? "2" : "-", - (dn->flags&DN_NDFLAG_P3) ? "3" : "-", - dn->n.nud_state, - refcount_read(&dn->n.refcnt), - dn->blksize, - (dn->n.dev) ? dn->n.dev->name : "?"); - read_unlock(&n->lock); -} - -static int dn_neigh_seq_show(struct seq_file *seq, void *v) -{ - if (v == SEQ_START_TOKEN) { - seq_puts(seq, "Addr Flags State Use Blksize Dev\n"); - } else { - dn_neigh_format_entry(seq, v); - } - - return 0; -} - -static void *dn_neigh_seq_start(struct seq_file *seq, loff_t *pos) -{ - return neigh_seq_start(seq, pos, &dn_neigh_table, - NEIGH_SEQ_NEIGH_ONLY); -} - -static const struct seq_operations dn_neigh_seq_ops = { - .start = dn_neigh_seq_start, - .next = neigh_seq_next, - .stop = neigh_seq_stop, - .show = dn_neigh_seq_show, -}; -#endif - -void __init dn_neigh_init(void) -{ - neigh_table_init(NEIGH_DN_TABLE, &dn_neigh_table); - proc_create_net("decnet_neigh", 0444, init_net.proc_net, - &dn_neigh_seq_ops, sizeof(struct neigh_seq_state)); -} - -void __exit dn_neigh_cleanup(void) -{ - remove_proc_entry("decnet_neigh", init_net.proc_net); - neigh_table_clear(NEIGH_DN_TABLE, &dn_neigh_table); -} diff --git a/net/decnet/dn_nsp_in.c b/net/decnet/dn_nsp_in.c deleted file mode 100644 index 2fb5e055ba25e6499cb0ce15c122220152af5a2d..0000000000000000000000000000000000000000 --- a/net/decnet/dn_nsp_in.c +++ /dev/null @@ -1,914 +0,0 @@ -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Network Services Protocol (Input) - * - * Author: Eduardo Marcelo Serrat - * - * Changes: - * - * Steve Whitehouse: Split into dn_nsp_in.c and dn_nsp_out.c from - * original dn_nsp.c. - * Steve Whitehouse: Updated to work with my new routing architecture. - * Steve Whitehouse: Add changes from Eduardo Serrat's patches. - * Steve Whitehouse: Put all ack handling code in a common routine. - * Steve Whitehouse: Put other common bits into dn_nsp_rx() - * Steve Whitehouse: More checks on skb->len to catch bogus packets - * Fixed various race conditions and possible nasties. - * Steve Whitehouse: Now handles returned conninit frames. - * David S. Miller: New socket locking - * Steve Whitehouse: Fixed lockup when socket filtering was enabled. - * Paul Koning: Fix to push CC sockets into RUN when acks are - * received. - * Steve Whitehouse: - * Patrick Caulfield: Checking conninits for correctness & sending of error - * responses. - * Steve Whitehouse: Added backlog congestion level return codes. - * Patrick Caulfield: - * Steve Whitehouse: Added flow control support (outbound) - * Steve Whitehouse: Prepare for nonlinear skbs - */ - -/****************************************************************************** - (c) 1995-1998 E.M. Serrat emserrat@geocities.com - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern int decnet_log_martians; - -static void dn_log_martian(struct sk_buff *skb, const char *msg) -{ - if (decnet_log_martians) { - char *devname = skb->dev ? skb->dev->name : "???"; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - net_info_ratelimited("DECnet: Martian packet (%s) dev=%s src=0x%04hx dst=0x%04hx srcport=0x%04hx dstport=0x%04hx\n", - msg, devname, - le16_to_cpu(cb->src), - le16_to_cpu(cb->dst), - le16_to_cpu(cb->src_port), - le16_to_cpu(cb->dst_port)); - } -} - -/* - * For this function we've flipped the cross-subchannel bit - * if the message is an otherdata or linkservice message. Thus - * we can use it to work out what to update. - */ -static void dn_ack(struct sock *sk, struct sk_buff *skb, unsigned short ack) -{ - struct dn_scp *scp = DN_SK(sk); - unsigned short type = ((ack >> 12) & 0x0003); - int wakeup = 0; - - switch (type) { - case 0: /* ACK - Data */ - if (dn_after(ack, scp->ackrcv_dat)) { - scp->ackrcv_dat = ack & 0x0fff; - wakeup |= dn_nsp_check_xmit_queue(sk, skb, - &scp->data_xmit_queue, - ack); - } - break; - case 1: /* NAK - Data */ - break; - case 2: /* ACK - OtherData */ - if (dn_after(ack, scp->ackrcv_oth)) { - scp->ackrcv_oth = ack & 0x0fff; - wakeup |= dn_nsp_check_xmit_queue(sk, skb, - &scp->other_xmit_queue, - ack); - } - break; - case 3: /* NAK - OtherData */ - break; - } - - if (wakeup && !sock_flag(sk, SOCK_DEAD)) - sk->sk_state_change(sk); -} - -/* - * This function is a universal ack processor. - */ -static int dn_process_ack(struct sock *sk, struct sk_buff *skb, int oth) -{ - __le16 *ptr = (__le16 *)skb->data; - int len = 0; - unsigned short ack; - - if (skb->len < 2) - return len; - - if ((ack = le16_to_cpu(*ptr)) & 0x8000) { - skb_pull(skb, 2); - ptr++; - len += 2; - if ((ack & 0x4000) == 0) { - if (oth) - ack ^= 0x2000; - dn_ack(sk, skb, ack); - } - } - - if (skb->len < 2) - return len; - - if ((ack = le16_to_cpu(*ptr)) & 0x8000) { - skb_pull(skb, 2); - len += 2; - if ((ack & 0x4000) == 0) { - if (oth) - ack ^= 0x2000; - dn_ack(sk, skb, ack); - } - } - - return len; -} - - -/** - * dn_check_idf - Check an image data field format is correct. - * @pptr: Pointer to pointer to image data - * @len: Pointer to length of image data - * @max: The maximum allowed length of the data in the image data field - * @follow_on: Check that this many bytes exist beyond the end of the image data - * - * Returns: 0 if ok, -1 on error - */ -static inline int dn_check_idf(unsigned char **pptr, int *len, unsigned char max, unsigned char follow_on) -{ - unsigned char *ptr = *pptr; - unsigned char flen = *ptr++; - - (*len)--; - if (flen > max) - return -1; - if ((flen + follow_on) > *len) - return -1; - - *len -= flen; - *pptr = ptr + flen; - return 0; -} - -/* - * Table of reason codes to pass back to node which sent us a badly - * formed message, plus text messages for the log. A zero entry in - * the reason field means "don't reply" otherwise a disc init is sent with - * the specified reason code. - */ -static struct { - unsigned short reason; - const char *text; -} ci_err_table[] = { - { 0, "CI: Truncated message" }, - { NSP_REASON_ID, "CI: Destination username error" }, - { NSP_REASON_ID, "CI: Destination username type" }, - { NSP_REASON_US, "CI: Source username error" }, - { 0, "CI: Truncated at menuver" }, - { 0, "CI: Truncated before access or user data" }, - { NSP_REASON_IO, "CI: Access data format error" }, - { NSP_REASON_IO, "CI: User data format error" } -}; - -/* - * This function uses a slightly different lookup method - * to find its sockets, since it searches on object name/number - * rather than port numbers. Various tests are done to ensure that - * the incoming data is in the correct format before it is queued to - * a socket. - */ -static struct sock *dn_find_listener(struct sk_buff *skb, unsigned short *reason) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct nsp_conn_init_msg *msg = (struct nsp_conn_init_msg *)skb->data; - struct sockaddr_dn dstaddr; - struct sockaddr_dn srcaddr; - unsigned char type = 0; - int dstlen; - int srclen; - unsigned char *ptr; - int len; - int err = 0; - unsigned char menuver; - - memset(&dstaddr, 0, sizeof(struct sockaddr_dn)); - memset(&srcaddr, 0, sizeof(struct sockaddr_dn)); - - /* - * 1. Decode & remove message header - */ - cb->src_port = msg->srcaddr; - cb->dst_port = msg->dstaddr; - cb->services = msg->services; - cb->info = msg->info; - cb->segsize = le16_to_cpu(msg->segsize); - - if (!pskb_may_pull(skb, sizeof(*msg))) - goto err_out; - - skb_pull(skb, sizeof(*msg)); - - len = skb->len; - ptr = skb->data; - - /* - * 2. Check destination end username format - */ - dstlen = dn_username2sockaddr(ptr, len, &dstaddr, &type); - err++; - if (dstlen < 0) - goto err_out; - - err++; - if (type > 1) - goto err_out; - - len -= dstlen; - ptr += dstlen; - - /* - * 3. Check source end username format - */ - srclen = dn_username2sockaddr(ptr, len, &srcaddr, &type); - err++; - if (srclen < 0) - goto err_out; - - len -= srclen; - ptr += srclen; - err++; - if (len < 1) - goto err_out; - - menuver = *ptr; - ptr++; - len--; - - /* - * 4. Check that optional data actually exists if menuver says it does - */ - err++; - if ((menuver & (DN_MENUVER_ACC | DN_MENUVER_USR)) && (len < 1)) - goto err_out; - - /* - * 5. Check optional access data format - */ - err++; - if (menuver & DN_MENUVER_ACC) { - if (dn_check_idf(&ptr, &len, 39, 1)) - goto err_out; - if (dn_check_idf(&ptr, &len, 39, 1)) - goto err_out; - if (dn_check_idf(&ptr, &len, 39, (menuver & DN_MENUVER_USR) ? 1 : 0)) - goto err_out; - } - - /* - * 6. Check optional user data format - */ - err++; - if (menuver & DN_MENUVER_USR) { - if (dn_check_idf(&ptr, &len, 16, 0)) - goto err_out; - } - - /* - * 7. Look up socket based on destination end username - */ - return dn_sklist_find_listener(&dstaddr); -err_out: - dn_log_martian(skb, ci_err_table[err].text); - *reason = ci_err_table[err].reason; - return NULL; -} - - -static void dn_nsp_conn_init(struct sock *sk, struct sk_buff *skb) -{ - if (sk_acceptq_is_full(sk)) { - kfree_skb(skb); - return; - } - - sk->sk_ack_backlog++; - skb_queue_tail(&sk->sk_receive_queue, skb); - sk->sk_state_change(sk); -} - -static void dn_nsp_conn_conf(struct sock *sk, struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct dn_scp *scp = DN_SK(sk); - unsigned char *ptr; - - if (skb->len < 4) - goto out; - - ptr = skb->data; - cb->services = *ptr++; - cb->info = *ptr++; - cb->segsize = le16_to_cpu(*(__le16 *)ptr); - - if ((scp->state == DN_CI) || (scp->state == DN_CD)) { - scp->persist = 0; - scp->addrrem = cb->src_port; - sk->sk_state = TCP_ESTABLISHED; - scp->state = DN_RUN; - scp->services_rem = cb->services; - scp->info_rem = cb->info; - scp->segsize_rem = cb->segsize; - - if ((scp->services_rem & NSP_FC_MASK) == NSP_FC_NONE) - scp->max_window = decnet_no_fc_max_cwnd; - - if (skb->len > 0) { - u16 dlen = *skb->data; - if ((dlen <= 16) && (dlen <= skb->len)) { - scp->conndata_in.opt_optl = cpu_to_le16(dlen); - skb_copy_from_linear_data_offset(skb, 1, - scp->conndata_in.opt_data, dlen); - } - } - dn_nsp_send_link(sk, DN_NOCHANGE, 0); - if (!sock_flag(sk, SOCK_DEAD)) - sk->sk_state_change(sk); - } - -out: - kfree_skb(skb); -} - -static void dn_nsp_conn_ack(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - - if (scp->state == DN_CI) { - scp->state = DN_CD; - scp->persist = 0; - } - - kfree_skb(skb); -} - -static void dn_nsp_disc_init(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - struct dn_skb_cb *cb = DN_SKB_CB(skb); - unsigned short reason; - - if (skb->len < 2) - goto out; - - reason = le16_to_cpu(*(__le16 *)skb->data); - skb_pull(skb, 2); - - scp->discdata_in.opt_status = cpu_to_le16(reason); - scp->discdata_in.opt_optl = 0; - memset(scp->discdata_in.opt_data, 0, 16); - - if (skb->len > 0) { - u16 dlen = *skb->data; - if ((dlen <= 16) && (dlen <= skb->len)) { - scp->discdata_in.opt_optl = cpu_to_le16(dlen); - skb_copy_from_linear_data_offset(skb, 1, scp->discdata_in.opt_data, dlen); - } - } - - scp->addrrem = cb->src_port; - sk->sk_state = TCP_CLOSE; - - switch (scp->state) { - case DN_CI: - case DN_CD: - scp->state = DN_RJ; - sk->sk_err = ECONNREFUSED; - break; - case DN_RUN: - sk->sk_shutdown |= SHUTDOWN_MASK; - scp->state = DN_DN; - break; - case DN_DI: - scp->state = DN_DIC; - break; - } - - if (!sock_flag(sk, SOCK_DEAD)) { - if (sk->sk_socket->state != SS_UNCONNECTED) - sk->sk_socket->state = SS_DISCONNECTING; - sk->sk_state_change(sk); - } - - /* - * It appears that its possible for remote machines to send disc - * init messages with no port identifier if we are in the CI and - * possibly also the CD state. Obviously we shouldn't reply with - * a message if we don't know what the end point is. - */ - if (scp->addrrem) { - dn_nsp_send_disc(sk, NSP_DISCCONF, NSP_REASON_DC, GFP_ATOMIC); - } - scp->persist_fxn = dn_destroy_timer; - scp->persist = dn_nsp_persist(sk); - -out: - kfree_skb(skb); -} - -/* - * disc_conf messages are also called no_resources or no_link - * messages depending upon the "reason" field. - */ -static void dn_nsp_disc_conf(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - unsigned short reason; - - if (skb->len != 2) - goto out; - - reason = le16_to_cpu(*(__le16 *)skb->data); - - sk->sk_state = TCP_CLOSE; - - switch (scp->state) { - case DN_CI: - scp->state = DN_NR; - break; - case DN_DR: - if (reason == NSP_REASON_DC) - scp->state = DN_DRC; - if (reason == NSP_REASON_NL) - scp->state = DN_CN; - break; - case DN_DI: - scp->state = DN_DIC; - break; - case DN_RUN: - sk->sk_shutdown |= SHUTDOWN_MASK; - /* fall through */ - case DN_CC: - scp->state = DN_CN; - } - - if (!sock_flag(sk, SOCK_DEAD)) { - if (sk->sk_socket->state != SS_UNCONNECTED) - sk->sk_socket->state = SS_DISCONNECTING; - sk->sk_state_change(sk); - } - - scp->persist_fxn = dn_destroy_timer; - scp->persist = dn_nsp_persist(sk); - -out: - kfree_skb(skb); -} - -static void dn_nsp_linkservice(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - unsigned short segnum; - unsigned char lsflags; - signed char fcval; - int wake_up = 0; - char *ptr = skb->data; - unsigned char fctype = scp->services_rem & NSP_FC_MASK; - - if (skb->len != 4) - goto out; - - segnum = le16_to_cpu(*(__le16 *)ptr); - ptr += 2; - lsflags = *(unsigned char *)ptr++; - fcval = *ptr; - - /* - * Here we ignore erronous packets which should really - * should cause a connection abort. It is not critical - * for now though. - */ - if (lsflags & 0xf8) - goto out; - - if (seq_next(scp->numoth_rcv, segnum)) { - seq_add(&scp->numoth_rcv, 1); - switch(lsflags & 0x04) { /* FCVAL INT */ - case 0x00: /* Normal Request */ - switch(lsflags & 0x03) { /* FCVAL MOD */ - case 0x00: /* Request count */ - if (fcval < 0) { - unsigned char p_fcval = -fcval; - if ((scp->flowrem_dat > p_fcval) && - (fctype == NSP_FC_SCMC)) { - scp->flowrem_dat -= p_fcval; - } - } else if (fcval > 0) { - scp->flowrem_dat += fcval; - wake_up = 1; - } - break; - case 0x01: /* Stop outgoing data */ - scp->flowrem_sw = DN_DONTSEND; - break; - case 0x02: /* Ok to start again */ - scp->flowrem_sw = DN_SEND; - dn_nsp_output(sk); - wake_up = 1; - } - break; - case 0x04: /* Interrupt Request */ - if (fcval > 0) { - scp->flowrem_oth += fcval; - wake_up = 1; - } - break; - } - if (wake_up && !sock_flag(sk, SOCK_DEAD)) - sk->sk_state_change(sk); - } - - dn_nsp_send_oth_ack(sk); - -out: - kfree_skb(skb); -} - -/* - * Copy of sock_queue_rcv_skb (from sock.h) without - * bh_lock_sock() (its already held when this is called) which - * also allows data and other data to be queued to a socket. - */ -static __inline__ int dn_queue_skb(struct sock *sk, struct sk_buff *skb, int sig, struct sk_buff_head *queue) -{ - int err; - - /* Cast skb->rcvbuf to unsigned... It's pointless, but reduces - number of warnings when compiling with -W --ANK - */ - if (atomic_read(&sk->sk_rmem_alloc) + skb->truesize >= - (unsigned int)sk->sk_rcvbuf) { - err = -ENOMEM; - goto out; - } - - err = sk_filter(sk, skb); - if (err) - goto out; - - skb_set_owner_r(skb, sk); - skb_queue_tail(queue, skb); - - if (!sock_flag(sk, SOCK_DEAD)) - sk->sk_data_ready(sk); -out: - return err; -} - -static void dn_nsp_otherdata(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - unsigned short segnum; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - int queued = 0; - - if (skb->len < 2) - goto out; - - cb->segnum = segnum = le16_to_cpu(*(__le16 *)skb->data); - skb_pull(skb, 2); - - if (seq_next(scp->numoth_rcv, segnum)) { - - if (dn_queue_skb(sk, skb, SIGURG, &scp->other_receive_queue) == 0) { - seq_add(&scp->numoth_rcv, 1); - scp->other_report = 0; - queued = 1; - } - } - - dn_nsp_send_oth_ack(sk); -out: - if (!queued) - kfree_skb(skb); -} - -static void dn_nsp_data(struct sock *sk, struct sk_buff *skb) -{ - int queued = 0; - unsigned short segnum; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct dn_scp *scp = DN_SK(sk); - - if (skb->len < 2) - goto out; - - cb->segnum = segnum = le16_to_cpu(*(__le16 *)skb->data); - skb_pull(skb, 2); - - if (seq_next(scp->numdat_rcv, segnum)) { - if (dn_queue_skb(sk, skb, SIGIO, &sk->sk_receive_queue) == 0) { - seq_add(&scp->numdat_rcv, 1); - queued = 1; - } - - if ((scp->flowloc_sw == DN_SEND) && dn_congested(sk)) { - scp->flowloc_sw = DN_DONTSEND; - dn_nsp_send_link(sk, DN_DONTSEND, 0); - } - } - - dn_nsp_send_data_ack(sk); -out: - if (!queued) - kfree_skb(skb); -} - -/* - * If one of our conninit messages is returned, this function - * deals with it. It puts the socket into the NO_COMMUNICATION - * state. - */ -static void dn_returned_conn_init(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - - if (scp->state == DN_CI) { - scp->state = DN_NC; - sk->sk_state = TCP_CLOSE; - if (!sock_flag(sk, SOCK_DEAD)) - sk->sk_state_change(sk); - } - - kfree_skb(skb); -} - -static int dn_nsp_no_socket(struct sk_buff *skb, unsigned short reason) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - int ret = NET_RX_DROP; - - /* Must not reply to returned packets */ - if (cb->rt_flags & DN_RT_F_RTS) - goto out; - - if ((reason != NSP_REASON_OK) && ((cb->nsp_flags & 0x0c) == 0x08)) { - switch (cb->nsp_flags & 0x70) { - case 0x10: - case 0x60: /* (Retransmitted) Connect Init */ - dn_nsp_return_disc(skb, NSP_DISCINIT, reason); - ret = NET_RX_SUCCESS; - break; - case 0x20: /* Connect Confirm */ - dn_nsp_return_disc(skb, NSP_DISCCONF, reason); - ret = NET_RX_SUCCESS; - break; - } - } - -out: - kfree_skb(skb); - return ret; -} - -static int dn_nsp_rx_packet(struct net *net, struct sock *sk2, - struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct sock *sk = NULL; - unsigned char *ptr = (unsigned char *)skb->data; - unsigned short reason = NSP_REASON_NL; - - if (!pskb_may_pull(skb, 2)) - goto free_out; - - skb_reset_transport_header(skb); - cb->nsp_flags = *ptr++; - - if (decnet_debug_level & 2) - printk(KERN_DEBUG "dn_nsp_rx: Message type 0x%02x\n", (int)cb->nsp_flags); - - if (cb->nsp_flags & 0x83) - goto free_out; - - /* - * Filter out conninits and useless packet types - */ - if ((cb->nsp_flags & 0x0c) == 0x08) { - switch (cb->nsp_flags & 0x70) { - case 0x00: /* NOP */ - case 0x70: /* Reserved */ - case 0x50: /* Reserved, Phase II node init */ - goto free_out; - case 0x10: - case 0x60: - if (unlikely(cb->rt_flags & DN_RT_F_RTS)) - goto free_out; - sk = dn_find_listener(skb, &reason); - goto got_it; - } - } - - if (!pskb_may_pull(skb, 3)) - goto free_out; - - /* - * Grab the destination address. - */ - cb->dst_port = *(__le16 *)ptr; - cb->src_port = 0; - ptr += 2; - - /* - * If not a connack, grab the source address too. - */ - if (pskb_may_pull(skb, 5)) { - cb->src_port = *(__le16 *)ptr; - ptr += 2; - skb_pull(skb, 5); - } - - /* - * Returned packets... - * Swap src & dst and look up in the normal way. - */ - if (unlikely(cb->rt_flags & DN_RT_F_RTS)) { - swap(cb->dst_port, cb->src_port); - swap(cb->dst, cb->src); - } - - /* - * Find the socket to which this skb is destined. - */ - sk = dn_find_by_skb(skb); -got_it: - if (sk != NULL) { - struct dn_scp *scp = DN_SK(sk); - - /* Reset backoff */ - scp->nsp_rxtshift = 0; - - /* - * We linearize everything except data segments here. - */ - if (cb->nsp_flags & ~0x60) { - if (unlikely(skb_linearize(skb))) - goto free_out; - } - - return sk_receive_skb(sk, skb, 0); - } - - return dn_nsp_no_socket(skb, reason); - -free_out: - kfree_skb(skb); - return NET_RX_DROP; -} - -int dn_nsp_rx(struct sk_buff *skb) -{ - return NF_HOOK(NFPROTO_DECNET, NF_DN_LOCAL_IN, - &init_net, NULL, skb, skb->dev, NULL, - dn_nsp_rx_packet); -} - -/* - * This is the main receive routine for sockets. It is called - * from the above when the socket is not busy, and also from - * sock_release() when there is a backlog queued up. - */ -int dn_nsp_backlog_rcv(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - if (cb->rt_flags & DN_RT_F_RTS) { - if (cb->nsp_flags == 0x18 || cb->nsp_flags == 0x68) - dn_returned_conn_init(sk, skb); - else - kfree_skb(skb); - return NET_RX_SUCCESS; - } - - /* - * Control packet. - */ - if ((cb->nsp_flags & 0x0c) == 0x08) { - switch (cb->nsp_flags & 0x70) { - case 0x10: - case 0x60: - dn_nsp_conn_init(sk, skb); - break; - case 0x20: - dn_nsp_conn_conf(sk, skb); - break; - case 0x30: - dn_nsp_disc_init(sk, skb); - break; - case 0x40: - dn_nsp_disc_conf(sk, skb); - break; - } - - } else if (cb->nsp_flags == 0x24) { - /* - * Special for connacks, 'cos they don't have - * ack data or ack otherdata info. - */ - dn_nsp_conn_ack(sk, skb); - } else { - int other = 1; - - /* both data and ack frames can kick a CC socket into RUN */ - if ((scp->state == DN_CC) && !sock_flag(sk, SOCK_DEAD)) { - scp->state = DN_RUN; - sk->sk_state = TCP_ESTABLISHED; - sk->sk_state_change(sk); - } - - if ((cb->nsp_flags & 0x1c) == 0) - other = 0; - if (cb->nsp_flags == 0x04) - other = 0; - - /* - * Read out ack data here, this applies equally - * to data, other data, link serivce and both - * ack data and ack otherdata. - */ - dn_process_ack(sk, skb, other); - - /* - * If we've some sort of data here then call a - * suitable routine for dealing with it, otherwise - * the packet is an ack and can be discarded. - */ - if ((cb->nsp_flags & 0x0c) == 0) { - - if (scp->state != DN_RUN) - goto free_out; - - switch (cb->nsp_flags) { - case 0x10: /* LS */ - dn_nsp_linkservice(sk, skb); - break; - case 0x30: /* OD */ - dn_nsp_otherdata(sk, skb); - break; - default: - dn_nsp_data(sk, skb); - } - - } else { /* Ack, chuck it out here */ -free_out: - kfree_skb(skb); - } - } - - return NET_RX_SUCCESS; -} diff --git a/net/decnet/dn_nsp_out.c b/net/decnet/dn_nsp_out.c deleted file mode 100644 index a1779de6bd9c315d504c342614068d77a058bfa6..0000000000000000000000000000000000000000 --- a/net/decnet/dn_nsp_out.c +++ /dev/null @@ -1,703 +0,0 @@ -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Network Services Protocol (Output) - * - * Author: Eduardo Marcelo Serrat - * - * Changes: - * - * Steve Whitehouse: Split into dn_nsp_in.c and dn_nsp_out.c from - * original dn_nsp.c. - * Steve Whitehouse: Updated to work with my new routing architecture. - * Steve Whitehouse: Added changes from Eduardo Serrat's patches. - * Steve Whitehouse: Now conninits have the "return" bit set. - * Steve Whitehouse: Fixes to check alloc'd skbs are non NULL! - * Moved output state machine into one function - * Steve Whitehouse: New output state machine - * Paul Koning: Connect Confirm message fix. - * Eduardo Serrat: Fix to stop dn_nsp_do_disc() sending malformed packets. - * Steve Whitehouse: dn_nsp_output() and friends needed a spring clean - * Steve Whitehouse: Moved dn_nsp_send() in here from route.h - */ - -/****************************************************************************** - (c) 1995-1998 E.M. Serrat emserrat@geocities.com - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -static int nsp_backoff[NSP_MAXRXTSHIFT + 1] = { 1, 2, 4, 8, 16, 32, 64, 64, 64, 64, 64, 64, 64 }; - -static void dn_nsp_send(struct sk_buff *skb) -{ - struct sock *sk = skb->sk; - struct dn_scp *scp = DN_SK(sk); - struct dst_entry *dst; - struct flowidn fld; - - skb_reset_transport_header(skb); - scp->stamp = jiffies; - - dst = sk_dst_check(sk, 0); - if (dst) { -try_again: - skb_dst_set(skb, dst); - dst_output(&init_net, skb->sk, skb); - return; - } - - memset(&fld, 0, sizeof(fld)); - fld.flowidn_oif = sk->sk_bound_dev_if; - fld.saddr = dn_saddr2dn(&scp->addr); - fld.daddr = dn_saddr2dn(&scp->peer); - dn_sk_ports_copy(&fld, scp); - fld.flowidn_proto = DNPROTO_NSP; - if (dn_route_output_sock(&sk->sk_dst_cache, &fld, sk, 0) == 0) { - dst = sk_dst_get(sk); - sk->sk_route_caps = dst->dev->features; - goto try_again; - } - - sk->sk_err = EHOSTUNREACH; - if (!sock_flag(sk, SOCK_DEAD)) - sk->sk_state_change(sk); -} - - -/* - * If sk == NULL, then we assume that we are supposed to be making - * a routing layer skb. If sk != NULL, then we are supposed to be - * creating an skb for the NSP layer. - * - * The eventual aim is for each socket to have a cached header size - * for its outgoing packets, and to set hdr from this when sk != NULL. - */ -struct sk_buff *dn_alloc_skb(struct sock *sk, int size, gfp_t pri) -{ - struct sk_buff *skb; - int hdr = 64; - - if ((skb = alloc_skb(size + hdr, pri)) == NULL) - return NULL; - - skb->protocol = htons(ETH_P_DNA_RT); - skb->pkt_type = PACKET_OUTGOING; - - if (sk) - skb_set_owner_w(skb, sk); - - skb_reserve(skb, hdr); - - return skb; -} - -/* - * Calculate persist timer based upon the smoothed round - * trip time and the variance. Backoff according to the - * nsp_backoff[] array. - */ -unsigned long dn_nsp_persist(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - unsigned long t = ((scp->nsp_srtt >> 2) + scp->nsp_rttvar) >> 1; - - t *= nsp_backoff[scp->nsp_rxtshift]; - - if (t < HZ) t = HZ; - if (t > (600*HZ)) t = (600*HZ); - - if (scp->nsp_rxtshift < NSP_MAXRXTSHIFT) - scp->nsp_rxtshift++; - - /* printk(KERN_DEBUG "rxtshift %lu, t=%lu\n", scp->nsp_rxtshift, t); */ - - return t; -} - -/* - * This is called each time we get an estimate for the rtt - * on the link. - */ -static void dn_nsp_rtt(struct sock *sk, long rtt) -{ - struct dn_scp *scp = DN_SK(sk); - long srtt = (long)scp->nsp_srtt; - long rttvar = (long)scp->nsp_rttvar; - long delta; - - /* - * If the jiffies clock flips over in the middle of timestamp - * gathering this value might turn out negative, so we make sure - * that is it always positive here. - */ - if (rtt < 0) - rtt = -rtt; - /* - * Add new rtt to smoothed average - */ - delta = ((rtt << 3) - srtt); - srtt += (delta >> 3); - if (srtt >= 1) - scp->nsp_srtt = (unsigned long)srtt; - else - scp->nsp_srtt = 1; - - /* - * Add new rtt varience to smoothed varience - */ - delta >>= 1; - rttvar += ((((delta>0)?(delta):(-delta)) - rttvar) >> 2); - if (rttvar >= 1) - scp->nsp_rttvar = (unsigned long)rttvar; - else - scp->nsp_rttvar = 1; - - /* printk(KERN_DEBUG "srtt=%lu rttvar=%lu\n", scp->nsp_srtt, scp->nsp_rttvar); */ -} - -/** - * dn_nsp_clone_and_send - Send a data packet by cloning it - * @skb: The packet to clone and transmit - * @gfp: memory allocation flag - * - * Clone a queued data or other data packet and transmit it. - * - * Returns: The number of times the packet has been sent previously - */ -static inline unsigned int dn_nsp_clone_and_send(struct sk_buff *skb, - gfp_t gfp) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct sk_buff *skb2; - int ret = 0; - - if ((skb2 = skb_clone(skb, gfp)) != NULL) { - ret = cb->xmit_count; - cb->xmit_count++; - cb->stamp = jiffies; - skb2->sk = skb->sk; - dn_nsp_send(skb2); - } - - return ret; -} - -/** - * dn_nsp_output - Try and send something from socket queues - * @sk: The socket whose queues are to be investigated - * - * Try and send the packet on the end of the data and other data queues. - * Other data gets priority over data, and if we retransmit a packet we - * reduce the window by dividing it in two. - * - */ -void dn_nsp_output(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - struct sk_buff *skb; - unsigned int reduce_win = 0; - - /* - * First we check for otherdata/linkservice messages - */ - if ((skb = skb_peek(&scp->other_xmit_queue)) != NULL) - reduce_win = dn_nsp_clone_and_send(skb, GFP_ATOMIC); - - /* - * If we may not send any data, we don't. - * If we are still trying to get some other data down the - * channel, we don't try and send any data. - */ - if (reduce_win || (scp->flowrem_sw != DN_SEND)) - goto recalc_window; - - if ((skb = skb_peek(&scp->data_xmit_queue)) != NULL) - reduce_win = dn_nsp_clone_and_send(skb, GFP_ATOMIC); - - /* - * If we've sent any frame more than once, we cut the - * send window size in half. There is always a minimum - * window size of one available. - */ -recalc_window: - if (reduce_win) { - scp->snd_window >>= 1; - if (scp->snd_window < NSP_MIN_WINDOW) - scp->snd_window = NSP_MIN_WINDOW; - } -} - -int dn_nsp_xmit_timeout(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - dn_nsp_output(sk); - - if (!skb_queue_empty(&scp->data_xmit_queue) || - !skb_queue_empty(&scp->other_xmit_queue)) - scp->persist = dn_nsp_persist(sk); - - return 0; -} - -static inline __le16 *dn_mk_common_header(struct dn_scp *scp, struct sk_buff *skb, unsigned char msgflag, int len) -{ - unsigned char *ptr = skb_push(skb, len); - - BUG_ON(len < 5); - - *ptr++ = msgflag; - *((__le16 *)ptr) = scp->addrrem; - ptr += 2; - *((__le16 *)ptr) = scp->addrloc; - ptr += 2; - return (__le16 __force *)ptr; -} - -static __le16 *dn_mk_ack_header(struct sock *sk, struct sk_buff *skb, unsigned char msgflag, int hlen, int other) -{ - struct dn_scp *scp = DN_SK(sk); - unsigned short acknum = scp->numdat_rcv & 0x0FFF; - unsigned short ackcrs = scp->numoth_rcv & 0x0FFF; - __le16 *ptr; - - BUG_ON(hlen < 9); - - scp->ackxmt_dat = acknum; - scp->ackxmt_oth = ackcrs; - acknum |= 0x8000; - ackcrs |= 0x8000; - - /* If this is an "other data/ack" message, swap acknum and ackcrs */ - if (other) - swap(acknum, ackcrs); - - /* Set "cross subchannel" bit in ackcrs */ - ackcrs |= 0x2000; - - ptr = dn_mk_common_header(scp, skb, msgflag, hlen); - - *ptr++ = cpu_to_le16(acknum); - *ptr++ = cpu_to_le16(ackcrs); - - return ptr; -} - -static __le16 *dn_nsp_mk_data_header(struct sock *sk, struct sk_buff *skb, int oth) -{ - struct dn_scp *scp = DN_SK(sk); - struct dn_skb_cb *cb = DN_SKB_CB(skb); - __le16 *ptr = dn_mk_ack_header(sk, skb, cb->nsp_flags, 11, oth); - - if (unlikely(oth)) { - cb->segnum = scp->numoth; - seq_add(&scp->numoth, 1); - } else { - cb->segnum = scp->numdat; - seq_add(&scp->numdat, 1); - } - *(ptr++) = cpu_to_le16(cb->segnum); - - return ptr; -} - -void dn_nsp_queue_xmit(struct sock *sk, struct sk_buff *skb, - gfp_t gfp, int oth) -{ - struct dn_scp *scp = DN_SK(sk); - struct dn_skb_cb *cb = DN_SKB_CB(skb); - unsigned long t = ((scp->nsp_srtt >> 2) + scp->nsp_rttvar) >> 1; - - cb->xmit_count = 0; - dn_nsp_mk_data_header(sk, skb, oth); - - /* - * Slow start: If we have been idle for more than - * one RTT, then reset window to min size. - */ - if ((jiffies - scp->stamp) > t) - scp->snd_window = NSP_MIN_WINDOW; - - if (oth) - skb_queue_tail(&scp->other_xmit_queue, skb); - else - skb_queue_tail(&scp->data_xmit_queue, skb); - - if (scp->flowrem_sw != DN_SEND) - return; - - dn_nsp_clone_and_send(skb, gfp); -} - - -int dn_nsp_check_xmit_queue(struct sock *sk, struct sk_buff *skb, struct sk_buff_head *q, unsigned short acknum) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct dn_scp *scp = DN_SK(sk); - struct sk_buff *skb2, *n, *ack = NULL; - int wakeup = 0; - int try_retrans = 0; - unsigned long reftime = cb->stamp; - unsigned long pkttime; - unsigned short xmit_count; - unsigned short segnum; - - skb_queue_walk_safe(q, skb2, n) { - struct dn_skb_cb *cb2 = DN_SKB_CB(skb2); - - if (dn_before_or_equal(cb2->segnum, acknum)) - ack = skb2; - - /* printk(KERN_DEBUG "ack: %s %04x %04x\n", ack ? "ACK" : "SKIP", (int)cb2->segnum, (int)acknum); */ - - if (ack == NULL) - continue; - - /* printk(KERN_DEBUG "check_xmit_queue: %04x, %d\n", acknum, cb2->xmit_count); */ - - /* Does _last_ packet acked have xmit_count > 1 */ - try_retrans = 0; - /* Remember to wake up the sending process */ - wakeup = 1; - /* Keep various statistics */ - pkttime = cb2->stamp; - xmit_count = cb2->xmit_count; - segnum = cb2->segnum; - /* Remove and drop ack'ed packet */ - skb_unlink(ack, q); - kfree_skb(ack); - ack = NULL; - - /* - * We don't expect to see acknowledgements for packets we - * haven't sent yet. - */ - WARN_ON(xmit_count == 0); - - /* - * If the packet has only been sent once, we can use it - * to calculate the RTT and also open the window a little - * further. - */ - if (xmit_count == 1) { - if (dn_equal(segnum, acknum)) - dn_nsp_rtt(sk, (long)(pkttime - reftime)); - - if (scp->snd_window < scp->max_window) - scp->snd_window++; - } - - /* - * Packet has been sent more than once. If this is the last - * packet to be acknowledged then we want to send the next - * packet in the send queue again (assumes the remote host does - * go-back-N error control). - */ - if (xmit_count > 1) - try_retrans = 1; - } - - if (try_retrans) - dn_nsp_output(sk); - - return wakeup; -} - -void dn_nsp_send_data_ack(struct sock *sk) -{ - struct sk_buff *skb = NULL; - - if ((skb = dn_alloc_skb(sk, 9, GFP_ATOMIC)) == NULL) - return; - - skb_reserve(skb, 9); - dn_mk_ack_header(sk, skb, 0x04, 9, 0); - dn_nsp_send(skb); -} - -void dn_nsp_send_oth_ack(struct sock *sk) -{ - struct sk_buff *skb = NULL; - - if ((skb = dn_alloc_skb(sk, 9, GFP_ATOMIC)) == NULL) - return; - - skb_reserve(skb, 9); - dn_mk_ack_header(sk, skb, 0x14, 9, 1); - dn_nsp_send(skb); -} - - -void dn_send_conn_ack (struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - struct sk_buff *skb = NULL; - struct nsp_conn_ack_msg *msg; - - if ((skb = dn_alloc_skb(sk, 3, sk->sk_allocation)) == NULL) - return; - - msg = skb_put(skb, 3); - msg->msgflg = 0x24; - msg->dstaddr = scp->addrrem; - - dn_nsp_send(skb); -} - -static int dn_nsp_retrans_conn_conf(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - if (scp->state == DN_CC) - dn_send_conn_conf(sk, GFP_ATOMIC); - - return 0; -} - -void dn_send_conn_conf(struct sock *sk, gfp_t gfp) -{ - struct dn_scp *scp = DN_SK(sk); - struct sk_buff *skb = NULL; - struct nsp_conn_init_msg *msg; - __u8 len = (__u8)le16_to_cpu(scp->conndata_out.opt_optl); - - if ((skb = dn_alloc_skb(sk, 50 + len, gfp)) == NULL) - return; - - msg = skb_put(skb, sizeof(*msg)); - msg->msgflg = 0x28; - msg->dstaddr = scp->addrrem; - msg->srcaddr = scp->addrloc; - msg->services = scp->services_loc; - msg->info = scp->info_loc; - msg->segsize = cpu_to_le16(scp->segsize_loc); - - skb_put_u8(skb, len); - - if (len > 0) - skb_put_data(skb, scp->conndata_out.opt_data, len); - - - dn_nsp_send(skb); - - scp->persist = dn_nsp_persist(sk); - scp->persist_fxn = dn_nsp_retrans_conn_conf; -} - - -static __inline__ void dn_nsp_do_disc(struct sock *sk, unsigned char msgflg, - unsigned short reason, gfp_t gfp, - struct dst_entry *dst, - int ddl, unsigned char *dd, __le16 rem, __le16 loc) -{ - struct sk_buff *skb = NULL; - int size = 7 + ddl + ((msgflg == NSP_DISCINIT) ? 1 : 0); - unsigned char *msg; - - if ((dst == NULL) || (rem == 0)) { - net_dbg_ratelimited("DECnet: dn_nsp_do_disc: BUG! Please report this to SteveW@ACM.org rem=%u dst=%p\n", - le16_to_cpu(rem), dst); - return; - } - - if ((skb = dn_alloc_skb(sk, size, gfp)) == NULL) - return; - - msg = skb_put(skb, size); - *msg++ = msgflg; - *(__le16 *)msg = rem; - msg += 2; - *(__le16 *)msg = loc; - msg += 2; - *(__le16 *)msg = cpu_to_le16(reason); - msg += 2; - if (msgflg == NSP_DISCINIT) - *msg++ = ddl; - - if (ddl) { - memcpy(msg, dd, ddl); - } - - /* - * This doesn't go via the dn_nsp_send() function since we need - * to be able to send disc packets out which have no socket - * associations. - */ - skb_dst_set(skb, dst_clone(dst)); - dst_output(&init_net, skb->sk, skb); -} - - -void dn_nsp_send_disc(struct sock *sk, unsigned char msgflg, - unsigned short reason, gfp_t gfp) -{ - struct dn_scp *scp = DN_SK(sk); - int ddl = 0; - - if (msgflg == NSP_DISCINIT) - ddl = le16_to_cpu(scp->discdata_out.opt_optl); - - if (reason == 0) - reason = le16_to_cpu(scp->discdata_out.opt_status); - - dn_nsp_do_disc(sk, msgflg, reason, gfp, __sk_dst_get(sk), ddl, - scp->discdata_out.opt_data, scp->addrrem, scp->addrloc); -} - - -void dn_nsp_return_disc(struct sk_buff *skb, unsigned char msgflg, - unsigned short reason) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - int ddl = 0; - gfp_t gfp = GFP_ATOMIC; - - dn_nsp_do_disc(NULL, msgflg, reason, gfp, skb_dst(skb), ddl, - NULL, cb->src_port, cb->dst_port); -} - - -void dn_nsp_send_link(struct sock *sk, unsigned char lsflags, char fcval) -{ - struct dn_scp *scp = DN_SK(sk); - struct sk_buff *skb; - unsigned char *ptr; - gfp_t gfp = GFP_ATOMIC; - - if ((skb = dn_alloc_skb(sk, DN_MAX_NSP_DATA_HEADER + 2, gfp)) == NULL) - return; - - skb_reserve(skb, DN_MAX_NSP_DATA_HEADER); - ptr = skb_put(skb, 2); - DN_SKB_CB(skb)->nsp_flags = 0x10; - *ptr++ = lsflags; - *ptr = fcval; - - dn_nsp_queue_xmit(sk, skb, gfp, 1); - - scp->persist = dn_nsp_persist(sk); - scp->persist_fxn = dn_nsp_xmit_timeout; -} - -static int dn_nsp_retrans_conninit(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - if (scp->state == DN_CI) - dn_nsp_send_conninit(sk, NSP_RCI); - - return 0; -} - -void dn_nsp_send_conninit(struct sock *sk, unsigned char msgflg) -{ - struct dn_scp *scp = DN_SK(sk); - struct nsp_conn_init_msg *msg; - unsigned char aux; - unsigned char menuver; - struct dn_skb_cb *cb; - unsigned char type = 1; - gfp_t allocation = (msgflg == NSP_CI) ? sk->sk_allocation : GFP_ATOMIC; - struct sk_buff *skb = dn_alloc_skb(sk, 200, allocation); - - if (!skb) - return; - - cb = DN_SKB_CB(skb); - msg = skb_put(skb, sizeof(*msg)); - - msg->msgflg = msgflg; - msg->dstaddr = 0x0000; /* Remote Node will assign it*/ - - msg->srcaddr = scp->addrloc; - msg->services = scp->services_loc; /* Requested flow control */ - msg->info = scp->info_loc; /* Version Number */ - msg->segsize = cpu_to_le16(scp->segsize_loc); /* Max segment size */ - - if (scp->peer.sdn_objnum) - type = 0; - - skb_put(skb, dn_sockaddr2username(&scp->peer, - skb_tail_pointer(skb), type)); - skb_put(skb, dn_sockaddr2username(&scp->addr, - skb_tail_pointer(skb), 2)); - - menuver = DN_MENUVER_ACC | DN_MENUVER_USR; - if (scp->peer.sdn_flags & SDF_PROXY) - menuver |= DN_MENUVER_PRX; - if (scp->peer.sdn_flags & SDF_UICPROXY) - menuver |= DN_MENUVER_UIC; - - skb_put_u8(skb, menuver); /* Menu Version */ - - aux = scp->accessdata.acc_userl; - skb_put_u8(skb, aux); - if (aux > 0) - skb_put_data(skb, scp->accessdata.acc_user, aux); - - aux = scp->accessdata.acc_passl; - skb_put_u8(skb, aux); - if (aux > 0) - skb_put_data(skb, scp->accessdata.acc_pass, aux); - - aux = scp->accessdata.acc_accl; - skb_put_u8(skb, aux); - if (aux > 0) - skb_put_data(skb, scp->accessdata.acc_acc, aux); - - aux = (__u8)le16_to_cpu(scp->conndata_out.opt_optl); - skb_put_u8(skb, aux); - if (aux > 0) - skb_put_data(skb, scp->conndata_out.opt_data, aux); - - scp->persist = dn_nsp_persist(sk); - scp->persist_fxn = dn_nsp_retrans_conninit; - - cb->rt_flags = DN_RT_F_RQR; - - dn_nsp_send(skb); -} diff --git a/net/decnet/dn_route.c b/net/decnet/dn_route.c deleted file mode 100644 index 658191fba94ece0ef994dd624ff35a85e0da37ea..0000000000000000000000000000000000000000 --- a/net/decnet/dn_route.c +++ /dev/null @@ -1,1929 +0,0 @@ -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Routing Functions (Endnode and Router) - * - * Authors: Steve Whitehouse - * Eduardo Marcelo Serrat - * - * Changes: - * Steve Whitehouse : Fixes to allow "intra-ethernet" and - * "return-to-sender" bits on outgoing - * packets. - * Steve Whitehouse : Timeouts for cached routes. - * Steve Whitehouse : Use dst cache for input routes too. - * Steve Whitehouse : Fixed error values in dn_send_skb. - * Steve Whitehouse : Rework routing functions to better fit - * DECnet routing design - * Alexey Kuznetsov : New SMP locking - * Steve Whitehouse : More SMP locking changes & dn_cache_dump() - * Steve Whitehouse : Prerouting NF hook, now really is prerouting. - * Fixed possible skb leak in rtnetlink funcs. - * Steve Whitehouse : Dave Miller's dynamic hash table sizing and - * Alexey Kuznetsov's finer grained locking - * from ipv4/route.c. - * Steve Whitehouse : Routing is now starting to look like a - * sensible set of code now, mainly due to - * my copying the IPv4 routing code. The - * hooks here are modified and will continue - * to evolve for a while. - * Steve Whitehouse : Real SMP at last :-) Also new netfilter - * stuff. Look out raw sockets your days - * are numbered! - * Steve Whitehouse : Added return-to-sender functions. Added - * backlog congestion level return codes. - * Steve Whitehouse : Fixed bug where routes were set up with - * no ref count on net devices. - * Steve Whitehouse : RCU for the route cache - * Steve Whitehouse : Preparations for the flow cache - * Steve Whitehouse : Prepare for nonlinear skbs - */ - -/****************************************************************************** - (c) 1995-1998 E.M. Serrat emserrat@geocities.com - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct dn_rt_hash_bucket -{ - struct dn_route __rcu *chain; - spinlock_t lock; -}; - -extern struct neigh_table dn_neigh_table; - - -static unsigned char dn_hiord_addr[6] = {0xAA,0x00,0x04,0x00,0x00,0x00}; - -static const int dn_rt_min_delay = 2 * HZ; -static const int dn_rt_max_delay = 10 * HZ; -static const int dn_rt_mtu_expires = 10 * 60 * HZ; - -static unsigned long dn_rt_deadline; - -static int dn_dst_gc(struct dst_ops *ops); -static struct dst_entry *dn_dst_check(struct dst_entry *, __u32); -static unsigned int dn_dst_default_advmss(const struct dst_entry *dst); -static unsigned int dn_dst_mtu(const struct dst_entry *dst); -static void dn_dst_destroy(struct dst_entry *); -static void dn_dst_ifdown(struct dst_entry *, struct net_device *dev, int how); -static struct dst_entry *dn_dst_negative_advice(struct dst_entry *); -static void dn_dst_link_failure(struct sk_buff *); -static void dn_dst_update_pmtu(struct dst_entry *dst, struct sock *sk, - struct sk_buff *skb , u32 mtu, - bool confirm_neigh); -static void dn_dst_redirect(struct dst_entry *dst, struct sock *sk, - struct sk_buff *skb); -static struct neighbour *dn_dst_neigh_lookup(const struct dst_entry *dst, - struct sk_buff *skb, - const void *daddr); -static int dn_route_input(struct sk_buff *); -static void dn_run_flush(struct timer_list *unused); - -static struct dn_rt_hash_bucket *dn_rt_hash_table; -static unsigned int dn_rt_hash_mask; - -static struct timer_list dn_route_timer; -static DEFINE_TIMER(dn_rt_flush_timer, dn_run_flush); -int decnet_dst_gc_interval = 2; - -static struct dst_ops dn_dst_ops = { - .family = PF_DECnet, - .gc_thresh = 128, - .gc = dn_dst_gc, - .check = dn_dst_check, - .default_advmss = dn_dst_default_advmss, - .mtu = dn_dst_mtu, - .cow_metrics = dst_cow_metrics_generic, - .destroy = dn_dst_destroy, - .ifdown = dn_dst_ifdown, - .negative_advice = dn_dst_negative_advice, - .link_failure = dn_dst_link_failure, - .update_pmtu = dn_dst_update_pmtu, - .redirect = dn_dst_redirect, - .neigh_lookup = dn_dst_neigh_lookup, -}; - -static void dn_dst_destroy(struct dst_entry *dst) -{ - struct dn_route *rt = (struct dn_route *) dst; - - if (rt->n) - neigh_release(rt->n); - dst_destroy_metrics_generic(dst); -} - -static void dn_dst_ifdown(struct dst_entry *dst, struct net_device *dev, int how) -{ - if (how) { - struct dn_route *rt = (struct dn_route *) dst; - struct neighbour *n = rt->n; - - if (n && n->dev == dev) { - n->dev = dev_net(dev)->loopback_dev; - dev_hold(n->dev); - dev_put(dev); - } - } -} - -static __inline__ unsigned int dn_hash(__le16 src, __le16 dst) -{ - __u16 tmp = (__u16 __force)(src ^ dst); - tmp ^= (tmp >> 3); - tmp ^= (tmp >> 5); - tmp ^= (tmp >> 10); - return dn_rt_hash_mask & (unsigned int)tmp; -} - -static void dn_dst_check_expire(struct timer_list *unused) -{ - int i; - struct dn_route *rt; - struct dn_route __rcu **rtp; - unsigned long now = jiffies; - unsigned long expire = 120 * HZ; - - for (i = 0; i <= dn_rt_hash_mask; i++) { - rtp = &dn_rt_hash_table[i].chain; - - spin_lock(&dn_rt_hash_table[i].lock); - while ((rt = rcu_dereference_protected(*rtp, - lockdep_is_held(&dn_rt_hash_table[i].lock))) != NULL) { - if (atomic_read(&rt->dst.__refcnt) > 1 || - (now - rt->dst.lastuse) < expire) { - rtp = &rt->dn_next; - continue; - } - *rtp = rt->dn_next; - rt->dn_next = NULL; - dst_dev_put(&rt->dst); - dst_release(&rt->dst); - } - spin_unlock(&dn_rt_hash_table[i].lock); - - if ((jiffies - now) > 0) - break; - } - - mod_timer(&dn_route_timer, now + decnet_dst_gc_interval * HZ); -} - -static int dn_dst_gc(struct dst_ops *ops) -{ - struct dn_route *rt; - struct dn_route __rcu **rtp; - int i; - unsigned long now = jiffies; - unsigned long expire = 10 * HZ; - - for (i = 0; i <= dn_rt_hash_mask; i++) { - - spin_lock_bh(&dn_rt_hash_table[i].lock); - rtp = &dn_rt_hash_table[i].chain; - - while ((rt = rcu_dereference_protected(*rtp, - lockdep_is_held(&dn_rt_hash_table[i].lock))) != NULL) { - if (atomic_read(&rt->dst.__refcnt) > 1 || - (now - rt->dst.lastuse) < expire) { - rtp = &rt->dn_next; - continue; - } - *rtp = rt->dn_next; - rt->dn_next = NULL; - dst_dev_put(&rt->dst); - dst_release(&rt->dst); - break; - } - spin_unlock_bh(&dn_rt_hash_table[i].lock); - } - - return 0; -} - -/* - * The decnet standards don't impose a particular minimum mtu, what they - * do insist on is that the routing layer accepts a datagram of at least - * 230 bytes long. Here we have to subtract the routing header length from - * 230 to get the minimum acceptable mtu. If there is no neighbour, then we - * assume the worst and use a long header size. - * - * We update both the mtu and the advertised mss (i.e. the segment size we - * advertise to the other end). - */ -static void dn_dst_update_pmtu(struct dst_entry *dst, struct sock *sk, - struct sk_buff *skb, u32 mtu, - bool confirm_neigh) -{ - struct dn_route *rt = (struct dn_route *) dst; - struct neighbour *n = rt->n; - u32 min_mtu = 230; - struct dn_dev *dn; - - dn = n ? rcu_dereference_raw(n->dev->dn_ptr) : NULL; - - if (dn && dn->use_long == 0) - min_mtu -= 6; - else - min_mtu -= 21; - - if (dst_metric(dst, RTAX_MTU) > mtu && mtu >= min_mtu) { - if (!(dst_metric_locked(dst, RTAX_MTU))) { - dst_metric_set(dst, RTAX_MTU, mtu); - dst_set_expires(dst, dn_rt_mtu_expires); - } - if (!(dst_metric_locked(dst, RTAX_ADVMSS))) { - u32 mss = mtu - DN_MAX_NSP_DATA_HEADER; - u32 existing_mss = dst_metric_raw(dst, RTAX_ADVMSS); - if (!existing_mss || existing_mss > mss) - dst_metric_set(dst, RTAX_ADVMSS, mss); - } - } -} - -static void dn_dst_redirect(struct dst_entry *dst, struct sock *sk, - struct sk_buff *skb) -{ -} - -/* - * When a route has been marked obsolete. (e.g. routing cache flush) - */ -static struct dst_entry *dn_dst_check(struct dst_entry *dst, __u32 cookie) -{ - return NULL; -} - -static struct dst_entry *dn_dst_negative_advice(struct dst_entry *dst) -{ - dst_release(dst); - return NULL; -} - -static void dn_dst_link_failure(struct sk_buff *skb) -{ -} - -static inline int compare_keys(struct flowidn *fl1, struct flowidn *fl2) -{ - return ((fl1->daddr ^ fl2->daddr) | - (fl1->saddr ^ fl2->saddr) | - (fl1->flowidn_mark ^ fl2->flowidn_mark) | - (fl1->flowidn_scope ^ fl2->flowidn_scope) | - (fl1->flowidn_oif ^ fl2->flowidn_oif) | - (fl1->flowidn_iif ^ fl2->flowidn_iif)) == 0; -} - -static int dn_insert_route(struct dn_route *rt, unsigned int hash, struct dn_route **rp) -{ - struct dn_route *rth; - struct dn_route __rcu **rthp; - unsigned long now = jiffies; - - rthp = &dn_rt_hash_table[hash].chain; - - spin_lock_bh(&dn_rt_hash_table[hash].lock); - while ((rth = rcu_dereference_protected(*rthp, - lockdep_is_held(&dn_rt_hash_table[hash].lock))) != NULL) { - if (compare_keys(&rth->fld, &rt->fld)) { - /* Put it first */ - *rthp = rth->dn_next; - rcu_assign_pointer(rth->dn_next, - dn_rt_hash_table[hash].chain); - rcu_assign_pointer(dn_rt_hash_table[hash].chain, rth); - - dst_hold_and_use(&rth->dst, now); - spin_unlock_bh(&dn_rt_hash_table[hash].lock); - - dst_release_immediate(&rt->dst); - *rp = rth; - return 0; - } - rthp = &rth->dn_next; - } - - rcu_assign_pointer(rt->dn_next, dn_rt_hash_table[hash].chain); - rcu_assign_pointer(dn_rt_hash_table[hash].chain, rt); - - dst_hold_and_use(&rt->dst, now); - spin_unlock_bh(&dn_rt_hash_table[hash].lock); - *rp = rt; - return 0; -} - -static void dn_run_flush(struct timer_list *unused) -{ - int i; - struct dn_route *rt, *next; - - for (i = 0; i < dn_rt_hash_mask; i++) { - spin_lock_bh(&dn_rt_hash_table[i].lock); - - if ((rt = xchg((struct dn_route **)&dn_rt_hash_table[i].chain, NULL)) == NULL) - goto nothing_to_declare; - - for(; rt; rt = next) { - next = rcu_dereference_raw(rt->dn_next); - RCU_INIT_POINTER(rt->dn_next, NULL); - dst_dev_put(&rt->dst); - dst_release(&rt->dst); - } - -nothing_to_declare: - spin_unlock_bh(&dn_rt_hash_table[i].lock); - } -} - -static DEFINE_SPINLOCK(dn_rt_flush_lock); - -void dn_rt_cache_flush(int delay) -{ - unsigned long now = jiffies; - int user_mode = !in_interrupt(); - - if (delay < 0) - delay = dn_rt_min_delay; - - spin_lock_bh(&dn_rt_flush_lock); - - if (del_timer(&dn_rt_flush_timer) && delay > 0 && dn_rt_deadline) { - long tmo = (long)(dn_rt_deadline - now); - - if (user_mode && tmo < dn_rt_max_delay - dn_rt_min_delay) - tmo = 0; - - if (delay > tmo) - delay = tmo; - } - - if (delay <= 0) { - spin_unlock_bh(&dn_rt_flush_lock); - dn_run_flush(NULL); - return; - } - - if (dn_rt_deadline == 0) - dn_rt_deadline = now + dn_rt_max_delay; - - dn_rt_flush_timer.expires = now + delay; - add_timer(&dn_rt_flush_timer); - spin_unlock_bh(&dn_rt_flush_lock); -} - -/** - * dn_return_short - Return a short packet to its sender - * @skb: The packet to return - * - */ -static int dn_return_short(struct sk_buff *skb) -{ - struct dn_skb_cb *cb; - unsigned char *ptr; - __le16 *src; - __le16 *dst; - - /* Add back headers */ - skb_push(skb, skb->data - skb_network_header(skb)); - - if ((skb = skb_unshare(skb, GFP_ATOMIC)) == NULL) - return NET_RX_DROP; - - cb = DN_SKB_CB(skb); - /* Skip packet length and point to flags */ - ptr = skb->data + 2; - *ptr++ = (cb->rt_flags & ~DN_RT_F_RQR) | DN_RT_F_RTS; - - dst = (__le16 *)ptr; - ptr += 2; - src = (__le16 *)ptr; - ptr += 2; - *ptr = 0; /* Zero hop count */ - - swap(*src, *dst); - - skb->pkt_type = PACKET_OUTGOING; - dn_rt_finish_output(skb, NULL, NULL); - return NET_RX_SUCCESS; -} - -/** - * dn_return_long - Return a long packet to its sender - * @skb: The long format packet to return - * - */ -static int dn_return_long(struct sk_buff *skb) -{ - struct dn_skb_cb *cb; - unsigned char *ptr; - unsigned char *src_addr, *dst_addr; - unsigned char tmp[ETH_ALEN]; - - /* Add back all headers */ - skb_push(skb, skb->data - skb_network_header(skb)); - - if ((skb = skb_unshare(skb, GFP_ATOMIC)) == NULL) - return NET_RX_DROP; - - cb = DN_SKB_CB(skb); - /* Ignore packet length and point to flags */ - ptr = skb->data + 2; - - /* Skip padding */ - if (*ptr & DN_RT_F_PF) { - char padlen = (*ptr & ~DN_RT_F_PF); - ptr += padlen; - } - - *ptr++ = (cb->rt_flags & ~DN_RT_F_RQR) | DN_RT_F_RTS; - ptr += 2; - dst_addr = ptr; - ptr += 8; - src_addr = ptr; - ptr += 6; - *ptr = 0; /* Zero hop count */ - - /* Swap source and destination */ - memcpy(tmp, src_addr, ETH_ALEN); - memcpy(src_addr, dst_addr, ETH_ALEN); - memcpy(dst_addr, tmp, ETH_ALEN); - - skb->pkt_type = PACKET_OUTGOING; - dn_rt_finish_output(skb, dst_addr, src_addr); - return NET_RX_SUCCESS; -} - -/** - * dn_route_rx_packet - Try and find a route for an incoming packet - * @skb: The packet to find a route for - * - * Returns: result of input function if route is found, error code otherwise - */ -static int dn_route_rx_packet(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct dn_skb_cb *cb; - int err; - - if ((err = dn_route_input(skb)) == 0) - return dst_input(skb); - - cb = DN_SKB_CB(skb); - if (decnet_debug_level & 4) { - char *devname = skb->dev ? skb->dev->name : "???"; - - printk(KERN_DEBUG - "DECnet: dn_route_rx_packet: rt_flags=0x%02x dev=%s len=%d src=0x%04hx dst=0x%04hx err=%d type=%d\n", - (int)cb->rt_flags, devname, skb->len, - le16_to_cpu(cb->src), le16_to_cpu(cb->dst), - err, skb->pkt_type); - } - - if ((skb->pkt_type == PACKET_HOST) && (cb->rt_flags & DN_RT_F_RQR)) { - switch (cb->rt_flags & DN_RT_PKT_MSK) { - case DN_RT_PKT_SHORT: - return dn_return_short(skb); - case DN_RT_PKT_LONG: - return dn_return_long(skb); - } - } - - kfree_skb(skb); - return NET_RX_DROP; -} - -static int dn_route_rx_long(struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - unsigned char *ptr = skb->data; - - if (!pskb_may_pull(skb, 21)) /* 20 for long header, 1 for shortest nsp */ - goto drop_it; - - skb_pull(skb, 20); - skb_reset_transport_header(skb); - - /* Destination info */ - ptr += 2; - cb->dst = dn_eth2dn(ptr); - if (memcmp(ptr, dn_hiord_addr, 4) != 0) - goto drop_it; - ptr += 6; - - - /* Source info */ - ptr += 2; - cb->src = dn_eth2dn(ptr); - if (memcmp(ptr, dn_hiord_addr, 4) != 0) - goto drop_it; - ptr += 6; - /* Other junk */ - ptr++; - cb->hops = *ptr++; /* Visit Count */ - - return NF_HOOK(NFPROTO_DECNET, NF_DN_PRE_ROUTING, - &init_net, NULL, skb, skb->dev, NULL, - dn_route_rx_packet); - -drop_it: - kfree_skb(skb); - return NET_RX_DROP; -} - - - -static int dn_route_rx_short(struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - unsigned char *ptr = skb->data; - - if (!pskb_may_pull(skb, 6)) /* 5 for short header + 1 for shortest nsp */ - goto drop_it; - - skb_pull(skb, 5); - skb_reset_transport_header(skb); - - cb->dst = *(__le16 *)ptr; - ptr += 2; - cb->src = *(__le16 *)ptr; - ptr += 2; - cb->hops = *ptr & 0x3f; - - return NF_HOOK(NFPROTO_DECNET, NF_DN_PRE_ROUTING, - &init_net, NULL, skb, skb->dev, NULL, - dn_route_rx_packet); - -drop_it: - kfree_skb(skb); - return NET_RX_DROP; -} - -static int dn_route_discard(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - /* - * I know we drop the packet here, but thats considered success in - * this case - */ - kfree_skb(skb); - return NET_RX_SUCCESS; -} - -static int dn_route_ptp_hello(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - dn_dev_hello(skb); - dn_neigh_pointopoint_hello(skb); - return NET_RX_SUCCESS; -} - -int dn_route_rcv(struct sk_buff *skb, struct net_device *dev, struct packet_type *pt, struct net_device *orig_dev) -{ - struct dn_skb_cb *cb; - unsigned char flags = 0; - __u16 len = le16_to_cpu(*(__le16 *)skb->data); - struct dn_dev *dn = rcu_dereference(dev->dn_ptr); - unsigned char padlen = 0; - - if (!net_eq(dev_net(dev), &init_net)) - goto dump_it; - - if (dn == NULL) - goto dump_it; - - if ((skb = skb_share_check(skb, GFP_ATOMIC)) == NULL) - goto out; - - if (!pskb_may_pull(skb, 3)) - goto dump_it; - - skb_pull(skb, 2); - - if (len > skb->len) - goto dump_it; - - skb_trim(skb, len); - - flags = *skb->data; - - cb = DN_SKB_CB(skb); - cb->stamp = jiffies; - cb->iif = dev->ifindex; - - /* - * If we have padding, remove it. - */ - if (flags & DN_RT_F_PF) { - padlen = flags & ~DN_RT_F_PF; - if (!pskb_may_pull(skb, padlen + 1)) - goto dump_it; - skb_pull(skb, padlen); - flags = *skb->data; - } - - skb_reset_network_header(skb); - - /* - * Weed out future version DECnet - */ - if (flags & DN_RT_F_VER) - goto dump_it; - - cb->rt_flags = flags; - - if (decnet_debug_level & 1) - printk(KERN_DEBUG - "dn_route_rcv: got 0x%02x from %s [%d %d %d]\n", - (int)flags, (dev) ? dev->name : "???", len, skb->len, - padlen); - - if (flags & DN_RT_PKT_CNTL) { - if (unlikely(skb_linearize(skb))) - goto dump_it; - - switch (flags & DN_RT_CNTL_MSK) { - case DN_RT_PKT_INIT: - dn_dev_init_pkt(skb); - break; - case DN_RT_PKT_VERI: - dn_dev_veri_pkt(skb); - break; - } - - if (dn->parms.state != DN_DEV_S_RU) - goto dump_it; - - switch (flags & DN_RT_CNTL_MSK) { - case DN_RT_PKT_HELO: - return NF_HOOK(NFPROTO_DECNET, NF_DN_HELLO, - &init_net, NULL, skb, skb->dev, NULL, - dn_route_ptp_hello); - - case DN_RT_PKT_L1RT: - case DN_RT_PKT_L2RT: - return NF_HOOK(NFPROTO_DECNET, NF_DN_ROUTE, - &init_net, NULL, skb, skb->dev, NULL, - dn_route_discard); - case DN_RT_PKT_ERTH: - return NF_HOOK(NFPROTO_DECNET, NF_DN_HELLO, - &init_net, NULL, skb, skb->dev, NULL, - dn_neigh_router_hello); - - case DN_RT_PKT_EEDH: - return NF_HOOK(NFPROTO_DECNET, NF_DN_HELLO, - &init_net, NULL, skb, skb->dev, NULL, - dn_neigh_endnode_hello); - } - } else { - if (dn->parms.state != DN_DEV_S_RU) - goto dump_it; - - skb_pull(skb, 1); /* Pull flags */ - - switch (flags & DN_RT_PKT_MSK) { - case DN_RT_PKT_LONG: - return dn_route_rx_long(skb); - case DN_RT_PKT_SHORT: - return dn_route_rx_short(skb); - } - } - -dump_it: - kfree_skb(skb); -out: - return NET_RX_DROP; -} - -static int dn_output(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct dst_entry *dst = skb_dst(skb); - struct dn_route *rt = (struct dn_route *)dst; - struct net_device *dev = dst->dev; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - int err = -EINVAL; - - if (rt->n == NULL) - goto error; - - skb->dev = dev; - - cb->src = rt->rt_saddr; - cb->dst = rt->rt_daddr; - - /* - * Always set the Intra-Ethernet bit on all outgoing packets - * originated on this node. Only valid flag from upper layers - * is return-to-sender-requested. Set hop count to 0 too. - */ - cb->rt_flags &= ~DN_RT_F_RQR; - cb->rt_flags |= DN_RT_F_IE; - cb->hops = 0; - - return NF_HOOK(NFPROTO_DECNET, NF_DN_LOCAL_OUT, - &init_net, sk, skb, NULL, dev, - dn_to_neigh_output); - -error: - net_dbg_ratelimited("dn_output: This should not happen\n"); - - kfree_skb(skb); - - return err; -} - -static int dn_forward(struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct dst_entry *dst = skb_dst(skb); - struct dn_dev *dn_db = rcu_dereference(dst->dev->dn_ptr); - struct dn_route *rt; - int header_len; - struct net_device *dev = skb->dev; - - if (skb->pkt_type != PACKET_HOST) - goto drop; - - /* Ensure that we have enough space for headers */ - rt = (struct dn_route *)skb_dst(skb); - header_len = dn_db->use_long ? 21 : 6; - if (skb_cow(skb, LL_RESERVED_SPACE(rt->dst.dev)+header_len)) - goto drop; - - /* - * Hop count exceeded. - */ - if (++cb->hops > 30) - goto drop; - - skb->dev = rt->dst.dev; - - /* - * If packet goes out same interface it came in on, then set - * the Intra-Ethernet bit. This has no effect for short - * packets, so we don't need to test for them here. - */ - cb->rt_flags &= ~DN_RT_F_IE; - if (rt->rt_flags & RTCF_DOREDIRECT) - cb->rt_flags |= DN_RT_F_IE; - - return NF_HOOK(NFPROTO_DECNET, NF_DN_FORWARD, - &init_net, NULL, skb, dev, skb->dev, - dn_to_neigh_output); - -drop: - kfree_skb(skb); - return NET_RX_DROP; -} - -/* - * Used to catch bugs. This should never normally get - * called. - */ -static int dn_rt_bug_out(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - net_dbg_ratelimited("dn_rt_bug: skb from:%04x to:%04x\n", - le16_to_cpu(cb->src), le16_to_cpu(cb->dst)); - - kfree_skb(skb); - - return NET_RX_DROP; -} - -static int dn_rt_bug(struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - net_dbg_ratelimited("dn_rt_bug: skb from:%04x to:%04x\n", - le16_to_cpu(cb->src), le16_to_cpu(cb->dst)); - - kfree_skb(skb); - - return NET_RX_DROP; -} - -static unsigned int dn_dst_default_advmss(const struct dst_entry *dst) -{ - return dn_mss_from_pmtu(dst->dev, dst_mtu(dst)); -} - -static unsigned int dn_dst_mtu(const struct dst_entry *dst) -{ - unsigned int mtu = dst_metric_raw(dst, RTAX_MTU); - - return mtu ? : dst->dev->mtu; -} - -static struct neighbour *dn_dst_neigh_lookup(const struct dst_entry *dst, - struct sk_buff *skb, - const void *daddr) -{ - return __neigh_lookup_errno(&dn_neigh_table, daddr, dst->dev); -} - -static int dn_rt_set_next_hop(struct dn_route *rt, struct dn_fib_res *res) -{ - struct dn_fib_info *fi = res->fi; - struct net_device *dev = rt->dst.dev; - unsigned int mss_metric; - struct neighbour *n; - - if (fi) { - if (DN_FIB_RES_GW(*res) && - DN_FIB_RES_NH(*res).nh_scope == RT_SCOPE_LINK) - rt->rt_gateway = DN_FIB_RES_GW(*res); - dst_init_metrics(&rt->dst, fi->fib_metrics, true); - } - rt->rt_type = res->type; - - if (dev != NULL && rt->n == NULL) { - n = __neigh_lookup_errno(&dn_neigh_table, &rt->rt_gateway, dev); - if (IS_ERR(n)) - return PTR_ERR(n); - rt->n = n; - } - - if (dst_metric(&rt->dst, RTAX_MTU) > rt->dst.dev->mtu) - dst_metric_set(&rt->dst, RTAX_MTU, rt->dst.dev->mtu); - mss_metric = dst_metric_raw(&rt->dst, RTAX_ADVMSS); - if (mss_metric) { - unsigned int mss = dn_mss_from_pmtu(dev, dst_mtu(&rt->dst)); - if (mss_metric > mss) - dst_metric_set(&rt->dst, RTAX_ADVMSS, mss); - } - return 0; -} - -static inline int dn_match_addr(__le16 addr1, __le16 addr2) -{ - __u16 tmp = le16_to_cpu(addr1) ^ le16_to_cpu(addr2); - int match = 16; - while(tmp) { - tmp >>= 1; - match--; - } - return match; -} - -static __le16 dnet_select_source(const struct net_device *dev, __le16 daddr, int scope) -{ - __le16 saddr = 0; - struct dn_dev *dn_db; - struct dn_ifaddr *ifa; - int best_match = 0; - int ret; - - rcu_read_lock(); - dn_db = rcu_dereference(dev->dn_ptr); - for (ifa = rcu_dereference(dn_db->ifa_list); - ifa != NULL; - ifa = rcu_dereference(ifa->ifa_next)) { - if (ifa->ifa_scope > scope) - continue; - if (!daddr) { - saddr = ifa->ifa_local; - break; - } - ret = dn_match_addr(daddr, ifa->ifa_local); - if (ret > best_match) - saddr = ifa->ifa_local; - if (best_match == 0) - saddr = ifa->ifa_local; - } - rcu_read_unlock(); - - return saddr; -} - -static inline __le16 __dn_fib_res_prefsrc(struct dn_fib_res *res) -{ - return dnet_select_source(DN_FIB_RES_DEV(*res), DN_FIB_RES_GW(*res), res->scope); -} - -static inline __le16 dn_fib_rules_map_destination(__le16 daddr, struct dn_fib_res *res) -{ - __le16 mask = dnet_make_mask(res->prefixlen); - return (daddr&~mask)|res->fi->fib_nh->nh_gw; -} - -static int dn_route_output_slow(struct dst_entry **pprt, const struct flowidn *oldflp, int try_hard) -{ - struct flowidn fld = { - .daddr = oldflp->daddr, - .saddr = oldflp->saddr, - .flowidn_scope = RT_SCOPE_UNIVERSE, - .flowidn_mark = oldflp->flowidn_mark, - .flowidn_iif = LOOPBACK_IFINDEX, - .flowidn_oif = oldflp->flowidn_oif, - }; - struct dn_route *rt = NULL; - struct net_device *dev_out = NULL, *dev; - struct neighbour *neigh = NULL; - unsigned int hash; - unsigned int flags = 0; - struct dn_fib_res res = { .fi = NULL, .type = RTN_UNICAST }; - int err; - int free_res = 0; - __le16 gateway = 0; - - if (decnet_debug_level & 16) - printk(KERN_DEBUG - "dn_route_output_slow: dst=%04x src=%04x mark=%d" - " iif=%d oif=%d\n", le16_to_cpu(oldflp->daddr), - le16_to_cpu(oldflp->saddr), - oldflp->flowidn_mark, LOOPBACK_IFINDEX, - oldflp->flowidn_oif); - - /* If we have an output interface, verify its a DECnet device */ - if (oldflp->flowidn_oif) { - dev_out = dev_get_by_index(&init_net, oldflp->flowidn_oif); - err = -ENODEV; - if (dev_out && dev_out->dn_ptr == NULL) { - dev_put(dev_out); - dev_out = NULL; - } - if (dev_out == NULL) - goto out; - } - - /* If we have a source address, verify that its a local address */ - if (oldflp->saddr) { - err = -EADDRNOTAVAIL; - - if (dev_out) { - if (dn_dev_islocal(dev_out, oldflp->saddr)) - goto source_ok; - dev_put(dev_out); - goto out; - } - rcu_read_lock(); - for_each_netdev_rcu(&init_net, dev) { - if (!dev->dn_ptr) - continue; - if (!dn_dev_islocal(dev, oldflp->saddr)) - continue; - if ((dev->flags & IFF_LOOPBACK) && - oldflp->daddr && - !dn_dev_islocal(dev, oldflp->daddr)) - continue; - - dev_out = dev; - break; - } - rcu_read_unlock(); - if (dev_out == NULL) - goto out; - dev_hold(dev_out); -source_ok: - ; - } - - /* No destination? Assume its local */ - if (!fld.daddr) { - fld.daddr = fld.saddr; - - if (dev_out) - dev_put(dev_out); - err = -EINVAL; - dev_out = init_net.loopback_dev; - if (!dev_out->dn_ptr) - goto out; - err = -EADDRNOTAVAIL; - dev_hold(dev_out); - if (!fld.daddr) { - fld.daddr = - fld.saddr = dnet_select_source(dev_out, 0, - RT_SCOPE_HOST); - if (!fld.daddr) - goto out; - } - fld.flowidn_oif = LOOPBACK_IFINDEX; - res.type = RTN_LOCAL; - goto make_route; - } - - if (decnet_debug_level & 16) - printk(KERN_DEBUG - "dn_route_output_slow: initial checks complete." - " dst=%04x src=%04x oif=%d try_hard=%d\n", - le16_to_cpu(fld.daddr), le16_to_cpu(fld.saddr), - fld.flowidn_oif, try_hard); - - /* - * N.B. If the kernel is compiled without router support then - * dn_fib_lookup() will evaluate to non-zero so this if () block - * will always be executed. - */ - err = -ESRCH; - if (try_hard || (err = dn_fib_lookup(&fld, &res)) != 0) { - struct dn_dev *dn_db; - if (err != -ESRCH) - goto out; - /* - * Here the fallback is basically the standard algorithm for - * routing in endnodes which is described in the DECnet routing - * docs - * - * If we are not trying hard, look in neighbour cache. - * The result is tested to ensure that if a specific output - * device/source address was requested, then we honour that - * here - */ - if (!try_hard) { - neigh = neigh_lookup_nodev(&dn_neigh_table, &init_net, &fld.daddr); - if (neigh) { - if ((oldflp->flowidn_oif && - (neigh->dev->ifindex != oldflp->flowidn_oif)) || - (oldflp->saddr && - (!dn_dev_islocal(neigh->dev, - oldflp->saddr)))) { - neigh_release(neigh); - neigh = NULL; - } else { - if (dev_out) - dev_put(dev_out); - if (dn_dev_islocal(neigh->dev, fld.daddr)) { - dev_out = init_net.loopback_dev; - res.type = RTN_LOCAL; - } else { - dev_out = neigh->dev; - } - dev_hold(dev_out); - goto select_source; - } - } - } - - /* Not there? Perhaps its a local address */ - if (dev_out == NULL) - dev_out = dn_dev_get_default(); - err = -ENODEV; - if (dev_out == NULL) - goto out; - dn_db = rcu_dereference_raw(dev_out->dn_ptr); - if (!dn_db) - goto e_inval; - /* Possible improvement - check all devices for local addr */ - if (dn_dev_islocal(dev_out, fld.daddr)) { - dev_put(dev_out); - dev_out = init_net.loopback_dev; - dev_hold(dev_out); - res.type = RTN_LOCAL; - goto select_source; - } - /* Not local either.... try sending it to the default router */ - neigh = neigh_clone(dn_db->router); - BUG_ON(neigh && neigh->dev != dev_out); - - /* Ok then, we assume its directly connected and move on */ -select_source: - if (neigh) - gateway = ((struct dn_neigh *)neigh)->addr; - if (gateway == 0) - gateway = fld.daddr; - if (fld.saddr == 0) { - fld.saddr = dnet_select_source(dev_out, gateway, - res.type == RTN_LOCAL ? - RT_SCOPE_HOST : - RT_SCOPE_LINK); - if (fld.saddr == 0 && res.type != RTN_LOCAL) - goto e_addr; - } - fld.flowidn_oif = dev_out->ifindex; - goto make_route; - } - free_res = 1; - - if (res.type == RTN_NAT) - goto e_inval; - - if (res.type == RTN_LOCAL) { - if (!fld.saddr) - fld.saddr = fld.daddr; - if (dev_out) - dev_put(dev_out); - dev_out = init_net.loopback_dev; - dev_hold(dev_out); - if (!dev_out->dn_ptr) - goto e_inval; - fld.flowidn_oif = dev_out->ifindex; - if (res.fi) - dn_fib_info_put(res.fi); - res.fi = NULL; - goto make_route; - } - - if (res.fi->fib_nhs > 1 && fld.flowidn_oif == 0) - dn_fib_select_multipath(&fld, &res); - - /* - * We could add some logic to deal with default routes here and - * get rid of some of the special casing above. - */ - - if (!fld.saddr) - fld.saddr = DN_FIB_RES_PREFSRC(res); - - if (dev_out) - dev_put(dev_out); - dev_out = DN_FIB_RES_DEV(res); - dev_hold(dev_out); - fld.flowidn_oif = dev_out->ifindex; - gateway = DN_FIB_RES_GW(res); - -make_route: - if (dev_out->flags & IFF_LOOPBACK) - flags |= RTCF_LOCAL; - - rt = dst_alloc(&dn_dst_ops, dev_out, 0, DST_OBSOLETE_NONE, DST_HOST); - if (rt == NULL) - goto e_nobufs; - - rt->dn_next = NULL; - memset(&rt->fld, 0, sizeof(rt->fld)); - rt->fld.saddr = oldflp->saddr; - rt->fld.daddr = oldflp->daddr; - rt->fld.flowidn_oif = oldflp->flowidn_oif; - rt->fld.flowidn_iif = 0; - rt->fld.flowidn_mark = oldflp->flowidn_mark; - - rt->rt_saddr = fld.saddr; - rt->rt_daddr = fld.daddr; - rt->rt_gateway = gateway ? gateway : fld.daddr; - rt->rt_local_src = fld.saddr; - - rt->rt_dst_map = fld.daddr; - rt->rt_src_map = fld.saddr; - - rt->n = neigh; - neigh = NULL; - - rt->dst.lastuse = jiffies; - rt->dst.output = dn_output; - rt->dst.input = dn_rt_bug; - rt->rt_flags = flags; - if (flags & RTCF_LOCAL) - rt->dst.input = dn_nsp_rx; - - err = dn_rt_set_next_hop(rt, &res); - if (err) - goto e_neighbour; - - hash = dn_hash(rt->fld.saddr, rt->fld.daddr); - /* dn_insert_route() increments dst->__refcnt */ - dn_insert_route(rt, hash, (struct dn_route **)pprt); - -done: - if (neigh) - neigh_release(neigh); - if (free_res) - dn_fib_res_put(&res); - if (dev_out) - dev_put(dev_out); -out: - return err; - -e_addr: - err = -EADDRNOTAVAIL; - goto done; -e_inval: - err = -EINVAL; - goto done; -e_nobufs: - err = -ENOBUFS; - goto done; -e_neighbour: - dst_release_immediate(&rt->dst); - goto e_nobufs; -} - - -/* - * N.B. The flags may be moved into the flowi at some future stage. - */ -static int __dn_route_output_key(struct dst_entry **pprt, const struct flowidn *flp, int flags) -{ - unsigned int hash = dn_hash(flp->saddr, flp->daddr); - struct dn_route *rt = NULL; - - if (!(flags & MSG_TRYHARD)) { - rcu_read_lock_bh(); - for (rt = rcu_dereference_bh(dn_rt_hash_table[hash].chain); rt; - rt = rcu_dereference_bh(rt->dn_next)) { - if ((flp->daddr == rt->fld.daddr) && - (flp->saddr == rt->fld.saddr) && - (flp->flowidn_mark == rt->fld.flowidn_mark) && - dn_is_output_route(rt) && - (rt->fld.flowidn_oif == flp->flowidn_oif)) { - dst_hold_and_use(&rt->dst, jiffies); - rcu_read_unlock_bh(); - *pprt = &rt->dst; - return 0; - } - } - rcu_read_unlock_bh(); - } - - return dn_route_output_slow(pprt, flp, flags); -} - -static int dn_route_output_key(struct dst_entry **pprt, struct flowidn *flp, int flags) -{ - int err; - - err = __dn_route_output_key(pprt, flp, flags); - if (err == 0 && flp->flowidn_proto) { - *pprt = xfrm_lookup(&init_net, *pprt, - flowidn_to_flowi(flp), NULL, 0); - if (IS_ERR(*pprt)) { - err = PTR_ERR(*pprt); - *pprt = NULL; - } - } - return err; -} - -int dn_route_output_sock(struct dst_entry __rcu **pprt, struct flowidn *fl, struct sock *sk, int flags) -{ - int err; - - err = __dn_route_output_key(pprt, fl, flags & MSG_TRYHARD); - if (err == 0 && fl->flowidn_proto) { - *pprt = xfrm_lookup(&init_net, *pprt, - flowidn_to_flowi(fl), sk, 0); - if (IS_ERR(*pprt)) { - err = PTR_ERR(*pprt); - *pprt = NULL; - } - } - return err; -} - -static int dn_route_input_slow(struct sk_buff *skb) -{ - struct dn_route *rt = NULL; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct net_device *in_dev = skb->dev; - struct net_device *out_dev = NULL; - struct dn_dev *dn_db; - struct neighbour *neigh = NULL; - unsigned int hash; - int flags = 0; - __le16 gateway = 0; - __le16 local_src = 0; - struct flowidn fld = { - .daddr = cb->dst, - .saddr = cb->src, - .flowidn_scope = RT_SCOPE_UNIVERSE, - .flowidn_mark = skb->mark, - .flowidn_iif = skb->dev->ifindex, - }; - struct dn_fib_res res = { .fi = NULL, .type = RTN_UNREACHABLE }; - int err = -EINVAL; - int free_res = 0; - - dev_hold(in_dev); - - if ((dn_db = rcu_dereference(in_dev->dn_ptr)) == NULL) - goto out; - - /* Zero source addresses are not allowed */ - if (fld.saddr == 0) - goto out; - - /* - * In this case we've just received a packet from a source - * outside ourselves pretending to come from us. We don't - * allow it any further to prevent routing loops, spoofing and - * other nasties. Loopback packets already have the dst attached - * so this only affects packets which have originated elsewhere. - */ - err = -ENOTUNIQ; - if (dn_dev_islocal(in_dev, cb->src)) - goto out; - - err = dn_fib_lookup(&fld, &res); - if (err) { - if (err != -ESRCH) - goto out; - /* - * Is the destination us ? - */ - if (!dn_dev_islocal(in_dev, cb->dst)) - goto e_inval; - - res.type = RTN_LOCAL; - } else { - __le16 src_map = fld.saddr; - free_res = 1; - - out_dev = DN_FIB_RES_DEV(res); - if (out_dev == NULL) { - net_crit_ratelimited("Bug in dn_route_input_slow() No output device\n"); - goto e_inval; - } - dev_hold(out_dev); - - if (res.r) - src_map = fld.saddr; /* no NAT support for now */ - - gateway = DN_FIB_RES_GW(res); - if (res.type == RTN_NAT) { - fld.daddr = dn_fib_rules_map_destination(fld.daddr, &res); - dn_fib_res_put(&res); - free_res = 0; - if (dn_fib_lookup(&fld, &res)) - goto e_inval; - free_res = 1; - if (res.type != RTN_UNICAST) - goto e_inval; - flags |= RTCF_DNAT; - gateway = fld.daddr; - } - fld.saddr = src_map; - } - - switch(res.type) { - case RTN_UNICAST: - /* - * Forwarding check here, we only check for forwarding - * being turned off, if you want to only forward intra - * area, its up to you to set the routing tables up - * correctly. - */ - if (dn_db->parms.forwarding == 0) - goto e_inval; - - if (res.fi->fib_nhs > 1 && fld.flowidn_oif == 0) - dn_fib_select_multipath(&fld, &res); - - /* - * Check for out_dev == in_dev. We use the RTCF_DOREDIRECT - * flag as a hint to set the intra-ethernet bit when - * forwarding. If we've got NAT in operation, we don't do - * this optimisation. - */ - if (out_dev == in_dev && !(flags & RTCF_NAT)) - flags |= RTCF_DOREDIRECT; - - local_src = DN_FIB_RES_PREFSRC(res); - - case RTN_BLACKHOLE: - case RTN_UNREACHABLE: - break; - case RTN_LOCAL: - flags |= RTCF_LOCAL; - fld.saddr = cb->dst; - fld.daddr = cb->src; - - /* Routing tables gave us a gateway */ - if (gateway) - goto make_route; - - /* Packet was intra-ethernet, so we know its on-link */ - if (cb->rt_flags & DN_RT_F_IE) { - gateway = cb->src; - goto make_route; - } - - /* Use the default router if there is one */ - neigh = neigh_clone(dn_db->router); - if (neigh) { - gateway = ((struct dn_neigh *)neigh)->addr; - goto make_route; - } - - /* Close eyes and pray */ - gateway = cb->src; - goto make_route; - default: - goto e_inval; - } - -make_route: - rt = dst_alloc(&dn_dst_ops, out_dev, 1, DST_OBSOLETE_NONE, DST_HOST); - if (rt == NULL) - goto e_nobufs; - - rt->dn_next = NULL; - memset(&rt->fld, 0, sizeof(rt->fld)); - rt->rt_saddr = fld.saddr; - rt->rt_daddr = fld.daddr; - rt->rt_gateway = fld.daddr; - if (gateway) - rt->rt_gateway = gateway; - rt->rt_local_src = local_src ? local_src : rt->rt_saddr; - - rt->rt_dst_map = fld.daddr; - rt->rt_src_map = fld.saddr; - - rt->fld.saddr = cb->src; - rt->fld.daddr = cb->dst; - rt->fld.flowidn_oif = 0; - rt->fld.flowidn_iif = in_dev->ifindex; - rt->fld.flowidn_mark = fld.flowidn_mark; - - rt->n = neigh; - rt->dst.lastuse = jiffies; - rt->dst.output = dn_rt_bug_out; - switch (res.type) { - case RTN_UNICAST: - rt->dst.input = dn_forward; - break; - case RTN_LOCAL: - rt->dst.output = dn_output; - rt->dst.input = dn_nsp_rx; - rt->dst.dev = in_dev; - flags |= RTCF_LOCAL; - break; - default: - case RTN_UNREACHABLE: - case RTN_BLACKHOLE: - rt->dst.input = dst_discard; - } - rt->rt_flags = flags; - - err = dn_rt_set_next_hop(rt, &res); - if (err) - goto e_neighbour; - - hash = dn_hash(rt->fld.saddr, rt->fld.daddr); - /* dn_insert_route() increments dst->__refcnt */ - dn_insert_route(rt, hash, &rt); - skb_dst_set(skb, &rt->dst); - -done: - if (neigh) - neigh_release(neigh); - if (free_res) - dn_fib_res_put(&res); - dev_put(in_dev); - if (out_dev) - dev_put(out_dev); -out: - return err; - -e_inval: - err = -EINVAL; - goto done; - -e_nobufs: - err = -ENOBUFS; - goto done; - -e_neighbour: - dst_release_immediate(&rt->dst); - goto done; -} - -static int dn_route_input(struct sk_buff *skb) -{ - struct dn_route *rt; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - unsigned int hash = dn_hash(cb->src, cb->dst); - - if (skb_dst(skb)) - return 0; - - rcu_read_lock(); - for(rt = rcu_dereference(dn_rt_hash_table[hash].chain); rt != NULL; - rt = rcu_dereference(rt->dn_next)) { - if ((rt->fld.saddr == cb->src) && - (rt->fld.daddr == cb->dst) && - (rt->fld.flowidn_oif == 0) && - (rt->fld.flowidn_mark == skb->mark) && - (rt->fld.flowidn_iif == cb->iif)) { - dst_hold_and_use(&rt->dst, jiffies); - rcu_read_unlock(); - skb_dst_set(skb, (struct dst_entry *)rt); - return 0; - } - } - rcu_read_unlock(); - - return dn_route_input_slow(skb); -} - -static int dn_rt_fill_info(struct sk_buff *skb, u32 portid, u32 seq, - int event, int nowait, unsigned int flags) -{ - struct dn_route *rt = (struct dn_route *)skb_dst(skb); - struct rtmsg *r; - struct nlmsghdr *nlh; - long expires; - - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*r), flags); - if (!nlh) - return -EMSGSIZE; - - r = nlmsg_data(nlh); - r->rtm_family = AF_DECnet; - r->rtm_dst_len = 16; - r->rtm_src_len = 0; - r->rtm_tos = 0; - r->rtm_table = RT_TABLE_MAIN; - r->rtm_type = rt->rt_type; - r->rtm_flags = (rt->rt_flags & ~0xFFFF) | RTM_F_CLONED; - r->rtm_scope = RT_SCOPE_UNIVERSE; - r->rtm_protocol = RTPROT_UNSPEC; - - if (rt->rt_flags & RTCF_NOTIFY) - r->rtm_flags |= RTM_F_NOTIFY; - - if (nla_put_u32(skb, RTA_TABLE, RT_TABLE_MAIN) < 0 || - nla_put_le16(skb, RTA_DST, rt->rt_daddr) < 0) - goto errout; - - if (rt->fld.saddr) { - r->rtm_src_len = 16; - if (nla_put_le16(skb, RTA_SRC, rt->fld.saddr) < 0) - goto errout; - } - if (rt->dst.dev && - nla_put_u32(skb, RTA_OIF, rt->dst.dev->ifindex) < 0) - goto errout; - - /* - * Note to self - change this if input routes reverse direction when - * they deal only with inputs and not with replies like they do - * currently. - */ - if (nla_put_le16(skb, RTA_PREFSRC, rt->rt_local_src) < 0) - goto errout; - - if (rt->rt_daddr != rt->rt_gateway && - nla_put_le16(skb, RTA_GATEWAY, rt->rt_gateway) < 0) - goto errout; - - if (rtnetlink_put_metrics(skb, dst_metrics_ptr(&rt->dst)) < 0) - goto errout; - - expires = rt->dst.expires ? rt->dst.expires - jiffies : 0; - if (rtnl_put_cacheinfo(skb, &rt->dst, 0, expires, - rt->dst.error) < 0) - goto errout; - - if (dn_is_input_route(rt) && - nla_put_u32(skb, RTA_IIF, rt->fld.flowidn_iif) < 0) - goto errout; - - nlmsg_end(skb, nlh); - return 0; - -errout: - nlmsg_cancel(skb, nlh); - return -EMSGSIZE; -} - -const struct nla_policy rtm_dn_policy[RTA_MAX + 1] = { - [RTA_DST] = { .type = NLA_U16 }, - [RTA_SRC] = { .type = NLA_U16 }, - [RTA_IIF] = { .type = NLA_U32 }, - [RTA_OIF] = { .type = NLA_U32 }, - [RTA_GATEWAY] = { .type = NLA_U16 }, - [RTA_PRIORITY] = { .type = NLA_U32 }, - [RTA_PREFSRC] = { .type = NLA_U16 }, - [RTA_METRICS] = { .type = NLA_NESTED }, - [RTA_MULTIPATH] = { .type = NLA_NESTED }, - [RTA_TABLE] = { .type = NLA_U32 }, - [RTA_MARK] = { .type = NLA_U32 }, -}; - -/* - * This is called by both endnodes and routers now. - */ -static int dn_cache_getroute(struct sk_buff *in_skb, struct nlmsghdr *nlh, - struct netlink_ext_ack *extack) -{ - struct net *net = sock_net(in_skb->sk); - struct rtmsg *rtm = nlmsg_data(nlh); - struct dn_route *rt = NULL; - struct dn_skb_cb *cb; - int err; - struct sk_buff *skb; - struct flowidn fld; - struct nlattr *tb[RTA_MAX+1]; - - if (!net_eq(net, &init_net)) - return -EINVAL; - - err = nlmsg_parse(nlh, sizeof(*rtm), tb, RTA_MAX, rtm_dn_policy, - extack); - if (err < 0) - return err; - - memset(&fld, 0, sizeof(fld)); - fld.flowidn_proto = DNPROTO_NSP; - - skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); - if (skb == NULL) - return -ENOBUFS; - skb_reset_mac_header(skb); - cb = DN_SKB_CB(skb); - - if (tb[RTA_SRC]) - fld.saddr = nla_get_le16(tb[RTA_SRC]); - - if (tb[RTA_DST]) - fld.daddr = nla_get_le16(tb[RTA_DST]); - - if (tb[RTA_IIF]) - fld.flowidn_iif = nla_get_u32(tb[RTA_IIF]); - - if (fld.flowidn_iif) { - struct net_device *dev; - dev = __dev_get_by_index(&init_net, fld.flowidn_iif); - if (!dev || !dev->dn_ptr) { - kfree_skb(skb); - return -ENODEV; - } - skb->protocol = htons(ETH_P_DNA_RT); - skb->dev = dev; - cb->src = fld.saddr; - cb->dst = fld.daddr; - local_bh_disable(); - err = dn_route_input(skb); - local_bh_enable(); - memset(cb, 0, sizeof(struct dn_skb_cb)); - rt = (struct dn_route *)skb_dst(skb); - if (!err && -rt->dst.error) - err = rt->dst.error; - } else { - if (tb[RTA_OIF]) - fld.flowidn_oif = nla_get_u32(tb[RTA_OIF]); - - err = dn_route_output_key((struct dst_entry **)&rt, &fld, 0); - } - - skb->dev = NULL; - if (err) - goto out_free; - skb_dst_set(skb, &rt->dst); - if (rtm->rtm_flags & RTM_F_NOTIFY) - rt->rt_flags |= RTCF_NOTIFY; - - err = dn_rt_fill_info(skb, NETLINK_CB(in_skb).portid, nlh->nlmsg_seq, RTM_NEWROUTE, 0, 0); - if (err < 0) { - err = -EMSGSIZE; - goto out_free; - } - - return rtnl_unicast(skb, &init_net, NETLINK_CB(in_skb).portid); - -out_free: - kfree_skb(skb); - return err; -} - -/* - * For routers, this is called from dn_fib_dump, but for endnodes its - * called directly from the rtnetlink dispatch table. - */ -int dn_cache_dump(struct sk_buff *skb, struct netlink_callback *cb) -{ - struct net *net = sock_net(skb->sk); - struct dn_route *rt; - int h, s_h; - int idx, s_idx; - struct rtmsg *rtm; - - if (!net_eq(net, &init_net)) - return 0; - - if (nlmsg_len(cb->nlh) < sizeof(struct rtmsg)) - return -EINVAL; - - rtm = nlmsg_data(cb->nlh); - if (!(rtm->rtm_flags & RTM_F_CLONED)) - return 0; - - s_h = cb->args[0]; - s_idx = idx = cb->args[1]; - for(h = 0; h <= dn_rt_hash_mask; h++) { - if (h < s_h) - continue; - if (h > s_h) - s_idx = 0; - rcu_read_lock_bh(); - for(rt = rcu_dereference_bh(dn_rt_hash_table[h].chain), idx = 0; - rt; - rt = rcu_dereference_bh(rt->dn_next), idx++) { - if (idx < s_idx) - continue; - skb_dst_set(skb, dst_clone(&rt->dst)); - if (dn_rt_fill_info(skb, NETLINK_CB(cb->skb).portid, - cb->nlh->nlmsg_seq, RTM_NEWROUTE, - 1, NLM_F_MULTI) < 0) { - skb_dst_drop(skb); - rcu_read_unlock_bh(); - goto done; - } - skb_dst_drop(skb); - } - rcu_read_unlock_bh(); - } - -done: - cb->args[0] = h; - cb->args[1] = idx; - return skb->len; -} - -#ifdef CONFIG_PROC_FS -struct dn_rt_cache_iter_state { - int bucket; -}; - -static struct dn_route *dn_rt_cache_get_first(struct seq_file *seq) -{ - struct dn_route *rt = NULL; - struct dn_rt_cache_iter_state *s = seq->private; - - for(s->bucket = dn_rt_hash_mask; s->bucket >= 0; --s->bucket) { - rcu_read_lock_bh(); - rt = rcu_dereference_bh(dn_rt_hash_table[s->bucket].chain); - if (rt) - break; - rcu_read_unlock_bh(); - } - return rt; -} - -static struct dn_route *dn_rt_cache_get_next(struct seq_file *seq, struct dn_route *rt) -{ - struct dn_rt_cache_iter_state *s = seq->private; - - rt = rcu_dereference_bh(rt->dn_next); - while (!rt) { - rcu_read_unlock_bh(); - if (--s->bucket < 0) - break; - rcu_read_lock_bh(); - rt = rcu_dereference_bh(dn_rt_hash_table[s->bucket].chain); - } - return rt; -} - -static void *dn_rt_cache_seq_start(struct seq_file *seq, loff_t *pos) -{ - struct dn_route *rt = dn_rt_cache_get_first(seq); - - if (rt) { - while(*pos && (rt = dn_rt_cache_get_next(seq, rt))) - --*pos; - } - return *pos ? NULL : rt; -} - -static void *dn_rt_cache_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct dn_route *rt = dn_rt_cache_get_next(seq, v); - ++*pos; - return rt; -} - -static void dn_rt_cache_seq_stop(struct seq_file *seq, void *v) -{ - if (v) - rcu_read_unlock_bh(); -} - -static int dn_rt_cache_seq_show(struct seq_file *seq, void *v) -{ - struct dn_route *rt = v; - char buf1[DN_ASCBUF_LEN], buf2[DN_ASCBUF_LEN]; - - seq_printf(seq, "%-8s %-7s %-7s %04d %04d %04d\n", - rt->dst.dev ? rt->dst.dev->name : "*", - dn_addr2asc(le16_to_cpu(rt->rt_daddr), buf1), - dn_addr2asc(le16_to_cpu(rt->rt_saddr), buf2), - atomic_read(&rt->dst.__refcnt), - rt->dst.__use, 0); - return 0; -} - -static const struct seq_operations dn_rt_cache_seq_ops = { - .start = dn_rt_cache_seq_start, - .next = dn_rt_cache_seq_next, - .stop = dn_rt_cache_seq_stop, - .show = dn_rt_cache_seq_show, -}; -#endif /* CONFIG_PROC_FS */ - -void __init dn_route_init(void) -{ - int i, goal, order; - - dn_dst_ops.kmem_cachep = - kmem_cache_create("dn_dst_cache", sizeof(struct dn_route), 0, - SLAB_HWCACHE_ALIGN|SLAB_PANIC, NULL); - dst_entries_init(&dn_dst_ops); - timer_setup(&dn_route_timer, dn_dst_check_expire, 0); - dn_route_timer.expires = jiffies + decnet_dst_gc_interval * HZ; - add_timer(&dn_route_timer); - - goal = totalram_pages >> (26 - PAGE_SHIFT); - - for(order = 0; (1UL << order) < goal; order++) - /* NOTHING */; - - /* - * Only want 1024 entries max, since the table is very, very unlikely - * to be larger than that. - */ - while(order && ((((1UL << order) * PAGE_SIZE) / - sizeof(struct dn_rt_hash_bucket)) >= 2048)) - order--; - - do { - dn_rt_hash_mask = (1UL << order) * PAGE_SIZE / - sizeof(struct dn_rt_hash_bucket); - while(dn_rt_hash_mask & (dn_rt_hash_mask - 1)) - dn_rt_hash_mask--; - dn_rt_hash_table = (struct dn_rt_hash_bucket *) - __get_free_pages(GFP_ATOMIC, order); - } while (dn_rt_hash_table == NULL && --order > 0); - - if (!dn_rt_hash_table) - panic("Failed to allocate DECnet route cache hash table\n"); - - printk(KERN_INFO - "DECnet: Routing cache hash table of %u buckets, %ldKbytes\n", - dn_rt_hash_mask, - (long)(dn_rt_hash_mask*sizeof(struct dn_rt_hash_bucket))/1024); - - dn_rt_hash_mask--; - for(i = 0; i <= dn_rt_hash_mask; i++) { - spin_lock_init(&dn_rt_hash_table[i].lock); - dn_rt_hash_table[i].chain = NULL; - } - - dn_dst_ops.gc_thresh = (dn_rt_hash_mask + 1); - - proc_create_seq_private("decnet_cache", 0444, init_net.proc_net, - &dn_rt_cache_seq_ops, - sizeof(struct dn_rt_cache_iter_state), NULL); - -#ifdef CONFIG_DECNET_ROUTER - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_GETROUTE, - dn_cache_getroute, dn_fib_dump, 0); -#else - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_GETROUTE, - dn_cache_getroute, dn_cache_dump, 0); -#endif -} - -void __exit dn_route_cleanup(void) -{ - del_timer(&dn_route_timer); - dn_run_flush(NULL); - - remove_proc_entry("decnet_cache", init_net.proc_net); - dst_entries_destroy(&dn_dst_ops); -} diff --git a/net/decnet/dn_rules.c b/net/decnet/dn_rules.c deleted file mode 100644 index 4a4e3c17740cbb765dd3d11d41d32ef82e860d94..0000000000000000000000000000000000000000 --- a/net/decnet/dn_rules.c +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Routing Forwarding Information Base (Rules) - * - * Author: Steve Whitehouse - * Mostly copied from Alexey Kuznetsov's ipv4/fib_rules.c - * - * - * Changes: - * Steve Whitehouse - * Updated for Thomas Graf's generic rules - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct fib_rules_ops *dn_fib_rules_ops; - -struct dn_fib_rule -{ - struct fib_rule common; - unsigned char dst_len; - unsigned char src_len; - __le16 src; - __le16 srcmask; - __le16 dst; - __le16 dstmask; - __le16 srcmap; - u8 flags; -}; - - -int dn_fib_lookup(struct flowidn *flp, struct dn_fib_res *res) -{ - struct fib_lookup_arg arg = { - .result = res, - }; - int err; - - err = fib_rules_lookup(dn_fib_rules_ops, - flowidn_to_flowi(flp), 0, &arg); - res->r = arg.rule; - - return err; -} - -static int dn_fib_rule_action(struct fib_rule *rule, struct flowi *flp, - int flags, struct fib_lookup_arg *arg) -{ - struct flowidn *fld = &flp->u.dn; - int err = -EAGAIN; - struct dn_fib_table *tbl; - - switch(rule->action) { - case FR_ACT_TO_TBL: - break; - - case FR_ACT_UNREACHABLE: - err = -ENETUNREACH; - goto errout; - - case FR_ACT_PROHIBIT: - err = -EACCES; - goto errout; - - case FR_ACT_BLACKHOLE: - default: - err = -EINVAL; - goto errout; - } - - tbl = dn_fib_get_table(rule->table, 0); - if (tbl == NULL) - goto errout; - - err = tbl->lookup(tbl, fld, (struct dn_fib_res *)arg->result); - if (err > 0) - err = -EAGAIN; -errout: - return err; -} - -static const struct nla_policy dn_fib_rule_policy[FRA_MAX+1] = { - FRA_GENERIC_POLICY, -}; - -static int dn_fib_rule_match(struct fib_rule *rule, struct flowi *fl, int flags) -{ - struct dn_fib_rule *r = (struct dn_fib_rule *)rule; - struct flowidn *fld = &fl->u.dn; - __le16 daddr = fld->daddr; - __le16 saddr = fld->saddr; - - if (((saddr ^ r->src) & r->srcmask) || - ((daddr ^ r->dst) & r->dstmask)) - return 0; - - return 1; -} - -static int dn_fib_rule_configure(struct fib_rule *rule, struct sk_buff *skb, - struct fib_rule_hdr *frh, - struct nlattr **tb, - struct netlink_ext_ack *extack) -{ - int err = -EINVAL; - struct dn_fib_rule *r = (struct dn_fib_rule *)rule; - - if (frh->tos) { - NL_SET_ERR_MSG(extack, "Invalid tos value"); - goto errout; - } - - if (rule->table == RT_TABLE_UNSPEC) { - if (rule->action == FR_ACT_TO_TBL) { - struct dn_fib_table *table; - - table = dn_fib_empty_table(); - if (table == NULL) { - err = -ENOBUFS; - goto errout; - } - - rule->table = table->n; - } - } - - if (frh->src_len) - r->src = nla_get_le16(tb[FRA_SRC]); - - if (frh->dst_len) - r->dst = nla_get_le16(tb[FRA_DST]); - - r->src_len = frh->src_len; - r->srcmask = dnet_make_mask(r->src_len); - r->dst_len = frh->dst_len; - r->dstmask = dnet_make_mask(r->dst_len); - err = 0; -errout: - return err; -} - -static int dn_fib_rule_compare(struct fib_rule *rule, struct fib_rule_hdr *frh, - struct nlattr **tb) -{ - struct dn_fib_rule *r = (struct dn_fib_rule *)rule; - - if (frh->src_len && (r->src_len != frh->src_len)) - return 0; - - if (frh->dst_len && (r->dst_len != frh->dst_len)) - return 0; - - if (frh->src_len && (r->src != nla_get_le16(tb[FRA_SRC]))) - return 0; - - if (frh->dst_len && (r->dst != nla_get_le16(tb[FRA_DST]))) - return 0; - - return 1; -} - -unsigned int dnet_addr_type(__le16 addr) -{ - struct flowidn fld = { .daddr = addr }; - struct dn_fib_res res; - unsigned int ret = RTN_UNICAST; - struct dn_fib_table *tb = dn_fib_get_table(RT_TABLE_LOCAL, 0); - - res.r = NULL; - - if (tb) { - if (!tb->lookup(tb, &fld, &res)) { - ret = res.type; - dn_fib_res_put(&res); - } - } - return ret; -} - -static int dn_fib_rule_fill(struct fib_rule *rule, struct sk_buff *skb, - struct fib_rule_hdr *frh) -{ - struct dn_fib_rule *r = (struct dn_fib_rule *)rule; - - frh->dst_len = r->dst_len; - frh->src_len = r->src_len; - frh->tos = 0; - - if ((r->dst_len && - nla_put_le16(skb, FRA_DST, r->dst)) || - (r->src_len && - nla_put_le16(skb, FRA_SRC, r->src))) - goto nla_put_failure; - return 0; - -nla_put_failure: - return -ENOBUFS; -} - -static void dn_fib_rule_flush_cache(struct fib_rules_ops *ops) -{ - dn_rt_cache_flush(-1); -} - -static const struct fib_rules_ops __net_initconst dn_fib_rules_ops_template = { - .family = AF_DECnet, - .rule_size = sizeof(struct dn_fib_rule), - .addr_size = sizeof(u16), - .action = dn_fib_rule_action, - .match = dn_fib_rule_match, - .configure = dn_fib_rule_configure, - .compare = dn_fib_rule_compare, - .fill = dn_fib_rule_fill, - .flush_cache = dn_fib_rule_flush_cache, - .nlgroup = RTNLGRP_DECnet_RULE, - .policy = dn_fib_rule_policy, - .owner = THIS_MODULE, - .fro_net = &init_net, -}; - -void __init dn_fib_rules_init(void) -{ - dn_fib_rules_ops = - fib_rules_register(&dn_fib_rules_ops_template, &init_net); - BUG_ON(IS_ERR(dn_fib_rules_ops)); - BUG_ON(fib_default_rule_add(dn_fib_rules_ops, 0x7fff, - RT_TABLE_MAIN, 0)); -} - -void __exit dn_fib_rules_cleanup(void) -{ - rtnl_lock(); - fib_rules_unregister(dn_fib_rules_ops); - rtnl_unlock(); - rcu_barrier(); -} diff --git a/net/decnet/dn_table.c b/net/decnet/dn_table.c deleted file mode 100644 index f0710b5d037d09d5e2e48cd842e7c999a9061fc7..0000000000000000000000000000000000000000 --- a/net/decnet/dn_table.c +++ /dev/null @@ -1,928 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Routing Forwarding Information Base (Routing Tables) - * - * Author: Steve Whitehouse - * Mostly copied from the IPv4 routing code - * - * - * Changes: - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include /* RTF_xxx */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct dn_zone -{ - struct dn_zone *dz_next; - struct dn_fib_node **dz_hash; - int dz_nent; - int dz_divisor; - u32 dz_hashmask; -#define DZ_HASHMASK(dz) ((dz)->dz_hashmask) - int dz_order; - __le16 dz_mask; -#define DZ_MASK(dz) ((dz)->dz_mask) -}; - -struct dn_hash -{ - struct dn_zone *dh_zones[17]; - struct dn_zone *dh_zone_list; -}; - -#define dz_key_0(key) ((key).datum = 0) - -#define for_nexthops(fi) { int nhsel; const struct dn_fib_nh *nh;\ - for(nhsel = 0, nh = (fi)->fib_nh; nhsel < (fi)->fib_nhs; nh++, nhsel++) - -#define endfor_nexthops(fi) } - -#define DN_MAX_DIVISOR 1024 -#define DN_S_ZOMBIE 1 -#define DN_S_ACCESSED 2 - -#define DN_FIB_SCAN(f, fp) \ -for( ; ((f) = *(fp)) != NULL; (fp) = &(f)->fn_next) - -#define DN_FIB_SCAN_KEY(f, fp, key) \ -for( ; ((f) = *(fp)) != NULL && dn_key_eq((f)->fn_key, (key)); (fp) = &(f)->fn_next) - -#define RT_TABLE_MIN 1 -#define DN_FIB_TABLE_HASHSZ 256 -static struct hlist_head dn_fib_table_hash[DN_FIB_TABLE_HASHSZ]; -static DEFINE_RWLOCK(dn_fib_tables_lock); - -static struct kmem_cache *dn_hash_kmem __read_mostly; -static int dn_fib_hash_zombies; - -static inline dn_fib_idx_t dn_hash(dn_fib_key_t key, struct dn_zone *dz) -{ - u16 h = le16_to_cpu(key.datum)>>(16 - dz->dz_order); - h ^= (h >> 10); - h ^= (h >> 6); - h &= DZ_HASHMASK(dz); - return *(dn_fib_idx_t *)&h; -} - -static inline dn_fib_key_t dz_key(__le16 dst, struct dn_zone *dz) -{ - dn_fib_key_t k; - k.datum = dst & DZ_MASK(dz); - return k; -} - -static inline struct dn_fib_node **dn_chain_p(dn_fib_key_t key, struct dn_zone *dz) -{ - return &dz->dz_hash[dn_hash(key, dz).datum]; -} - -static inline struct dn_fib_node *dz_chain(dn_fib_key_t key, struct dn_zone *dz) -{ - return dz->dz_hash[dn_hash(key, dz).datum]; -} - -static inline int dn_key_eq(dn_fib_key_t a, dn_fib_key_t b) -{ - return a.datum == b.datum; -} - -static inline int dn_key_leq(dn_fib_key_t a, dn_fib_key_t b) -{ - return a.datum <= b.datum; -} - -static inline void dn_rebuild_zone(struct dn_zone *dz, - struct dn_fib_node **old_ht, - int old_divisor) -{ - struct dn_fib_node *f, **fp, *next; - int i; - - for(i = 0; i < old_divisor; i++) { - for(f = old_ht[i]; f; f = next) { - next = f->fn_next; - for(fp = dn_chain_p(f->fn_key, dz); - *fp && dn_key_leq((*fp)->fn_key, f->fn_key); - fp = &(*fp)->fn_next) - /* NOTHING */; - f->fn_next = *fp; - *fp = f; - } - } -} - -static void dn_rehash_zone(struct dn_zone *dz) -{ - struct dn_fib_node **ht, **old_ht; - int old_divisor, new_divisor; - u32 new_hashmask; - - old_divisor = dz->dz_divisor; - - switch (old_divisor) { - case 16: - new_divisor = 256; - new_hashmask = 0xFF; - break; - default: - printk(KERN_DEBUG "DECnet: dn_rehash_zone: BUG! %d\n", - old_divisor); - /* fall through */ - case 256: - new_divisor = 1024; - new_hashmask = 0x3FF; - break; - } - - ht = kcalloc(new_divisor, sizeof(struct dn_fib_node*), GFP_KERNEL); - if (ht == NULL) - return; - - write_lock_bh(&dn_fib_tables_lock); - old_ht = dz->dz_hash; - dz->dz_hash = ht; - dz->dz_hashmask = new_hashmask; - dz->dz_divisor = new_divisor; - dn_rebuild_zone(dz, old_ht, old_divisor); - write_unlock_bh(&dn_fib_tables_lock); - kfree(old_ht); -} - -static void dn_free_node(struct dn_fib_node *f) -{ - dn_fib_release_info(DN_FIB_INFO(f)); - kmem_cache_free(dn_hash_kmem, f); -} - - -static struct dn_zone *dn_new_zone(struct dn_hash *table, int z) -{ - int i; - struct dn_zone *dz = kzalloc(sizeof(struct dn_zone), GFP_KERNEL); - if (!dz) - return NULL; - - if (z) { - dz->dz_divisor = 16; - dz->dz_hashmask = 0x0F; - } else { - dz->dz_divisor = 1; - dz->dz_hashmask = 0; - } - - dz->dz_hash = kcalloc(dz->dz_divisor, sizeof(struct dn_fib_node *), GFP_KERNEL); - if (!dz->dz_hash) { - kfree(dz); - return NULL; - } - - dz->dz_order = z; - dz->dz_mask = dnet_make_mask(z); - - for(i = z + 1; i <= 16; i++) - if (table->dh_zones[i]) - break; - - write_lock_bh(&dn_fib_tables_lock); - if (i>16) { - dz->dz_next = table->dh_zone_list; - table->dh_zone_list = dz; - } else { - dz->dz_next = table->dh_zones[i]->dz_next; - table->dh_zones[i]->dz_next = dz; - } - table->dh_zones[z] = dz; - write_unlock_bh(&dn_fib_tables_lock); - return dz; -} - - -static int dn_fib_nh_match(struct rtmsg *r, struct nlmsghdr *nlh, struct nlattr *attrs[], struct dn_fib_info *fi) -{ - struct rtnexthop *nhp; - int nhlen; - - if (attrs[RTA_PRIORITY] && - nla_get_u32(attrs[RTA_PRIORITY]) != fi->fib_priority) - return 1; - - if (attrs[RTA_OIF] || attrs[RTA_GATEWAY]) { - if ((!attrs[RTA_OIF] || nla_get_u32(attrs[RTA_OIF]) == fi->fib_nh->nh_oif) && - (!attrs[RTA_GATEWAY] || nla_get_le16(attrs[RTA_GATEWAY]) != fi->fib_nh->nh_gw)) - return 0; - return 1; - } - - if (!attrs[RTA_MULTIPATH]) - return 0; - - nhp = nla_data(attrs[RTA_MULTIPATH]); - nhlen = nla_len(attrs[RTA_MULTIPATH]); - - for_nexthops(fi) { - int attrlen = nhlen - sizeof(struct rtnexthop); - __le16 gw; - - if (attrlen < 0 || (nhlen -= nhp->rtnh_len) < 0) - return -EINVAL; - if (nhp->rtnh_ifindex && nhp->rtnh_ifindex != nh->nh_oif) - return 1; - if (attrlen) { - struct nlattr *gw_attr; - - gw_attr = nla_find((struct nlattr *) (nhp + 1), attrlen, RTA_GATEWAY); - gw = gw_attr ? nla_get_le16(gw_attr) : 0; - - if (gw && gw != nh->nh_gw) - return 1; - } - nhp = RTNH_NEXT(nhp); - } endfor_nexthops(fi); - - return 0; -} - -static inline size_t dn_fib_nlmsg_size(struct dn_fib_info *fi) -{ - size_t payload = NLMSG_ALIGN(sizeof(struct rtmsg)) - + nla_total_size(4) /* RTA_TABLE */ - + nla_total_size(2) /* RTA_DST */ - + nla_total_size(4) /* RTA_PRIORITY */ - + nla_total_size(TCP_CA_NAME_MAX); /* RTAX_CC_ALGO */ - - /* space for nested metrics */ - payload += nla_total_size((RTAX_MAX * nla_total_size(4))); - - if (fi->fib_nhs) { - /* Also handles the special case fib_nhs == 1 */ - - /* each nexthop is packed in an attribute */ - size_t nhsize = nla_total_size(sizeof(struct rtnexthop)); - - /* may contain a gateway attribute */ - nhsize += nla_total_size(4); - - /* all nexthops are packed in a nested attribute */ - payload += nla_total_size(fi->fib_nhs * nhsize); - } - - return payload; -} - -static int dn_fib_dump_info(struct sk_buff *skb, u32 portid, u32 seq, int event, - u32 tb_id, u8 type, u8 scope, void *dst, int dst_len, - struct dn_fib_info *fi, unsigned int flags) -{ - struct rtmsg *rtm; - struct nlmsghdr *nlh; - - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*rtm), flags); - if (!nlh) - return -EMSGSIZE; - - rtm = nlmsg_data(nlh); - rtm->rtm_family = AF_DECnet; - rtm->rtm_dst_len = dst_len; - rtm->rtm_src_len = 0; - rtm->rtm_tos = 0; - rtm->rtm_table = tb_id; - rtm->rtm_flags = fi->fib_flags; - rtm->rtm_scope = scope; - rtm->rtm_type = type; - rtm->rtm_protocol = fi->fib_protocol; - - if (nla_put_u32(skb, RTA_TABLE, tb_id) < 0) - goto errout; - - if (rtm->rtm_dst_len && - nla_put(skb, RTA_DST, 2, dst) < 0) - goto errout; - - if (fi->fib_priority && - nla_put_u32(skb, RTA_PRIORITY, fi->fib_priority) < 0) - goto errout; - - if (rtnetlink_put_metrics(skb, fi->fib_metrics) < 0) - goto errout; - - if (fi->fib_nhs == 1) { - if (fi->fib_nh->nh_gw && - nla_put_le16(skb, RTA_GATEWAY, fi->fib_nh->nh_gw) < 0) - goto errout; - - if (fi->fib_nh->nh_oif && - nla_put_u32(skb, RTA_OIF, fi->fib_nh->nh_oif) < 0) - goto errout; - } - - if (fi->fib_nhs > 1) { - struct rtnexthop *nhp; - struct nlattr *mp_head; - - if (!(mp_head = nla_nest_start(skb, RTA_MULTIPATH))) - goto errout; - - for_nexthops(fi) { - if (!(nhp = nla_reserve_nohdr(skb, sizeof(*nhp)))) - goto errout; - - nhp->rtnh_flags = nh->nh_flags & 0xFF; - nhp->rtnh_hops = nh->nh_weight - 1; - nhp->rtnh_ifindex = nh->nh_oif; - - if (nh->nh_gw && - nla_put_le16(skb, RTA_GATEWAY, nh->nh_gw) < 0) - goto errout; - - nhp->rtnh_len = skb_tail_pointer(skb) - (unsigned char *)nhp; - } endfor_nexthops(fi); - - nla_nest_end(skb, mp_head); - } - - nlmsg_end(skb, nlh); - return 0; - -errout: - nlmsg_cancel(skb, nlh); - return -EMSGSIZE; -} - - -static void dn_rtmsg_fib(int event, struct dn_fib_node *f, int z, u32 tb_id, - struct nlmsghdr *nlh, struct netlink_skb_parms *req) -{ - struct sk_buff *skb; - u32 portid = req ? req->portid : 0; - int err = -ENOBUFS; - - skb = nlmsg_new(dn_fib_nlmsg_size(DN_FIB_INFO(f)), GFP_KERNEL); - if (skb == NULL) - goto errout; - - err = dn_fib_dump_info(skb, portid, nlh->nlmsg_seq, event, tb_id, - f->fn_type, f->fn_scope, &f->fn_key, z, - DN_FIB_INFO(f), 0); - if (err < 0) { - /* -EMSGSIZE implies BUG in dn_fib_nlmsg_size() */ - WARN_ON(err == -EMSGSIZE); - kfree_skb(skb); - goto errout; - } - rtnl_notify(skb, &init_net, portid, RTNLGRP_DECnet_ROUTE, nlh, GFP_KERNEL); - return; -errout: - if (err < 0) - rtnl_set_sk_err(&init_net, RTNLGRP_DECnet_ROUTE, err); -} - -static __inline__ int dn_hash_dump_bucket(struct sk_buff *skb, - struct netlink_callback *cb, - struct dn_fib_table *tb, - struct dn_zone *dz, - struct dn_fib_node *f) -{ - int i, s_i; - - s_i = cb->args[4]; - for(i = 0; f; i++, f = f->fn_next) { - if (i < s_i) - continue; - if (f->fn_state & DN_S_ZOMBIE) - continue; - if (dn_fib_dump_info(skb, NETLINK_CB(cb->skb).portid, - cb->nlh->nlmsg_seq, - RTM_NEWROUTE, - tb->n, - (f->fn_state & DN_S_ZOMBIE) ? 0 : f->fn_type, - f->fn_scope, &f->fn_key, dz->dz_order, - f->fn_info, NLM_F_MULTI) < 0) { - cb->args[4] = i; - return -1; - } - } - cb->args[4] = i; - return skb->len; -} - -static __inline__ int dn_hash_dump_zone(struct sk_buff *skb, - struct netlink_callback *cb, - struct dn_fib_table *tb, - struct dn_zone *dz) -{ - int h, s_h; - - s_h = cb->args[3]; - for(h = 0; h < dz->dz_divisor; h++) { - if (h < s_h) - continue; - if (h > s_h) - memset(&cb->args[4], 0, sizeof(cb->args) - 4*sizeof(cb->args[0])); - if (dz->dz_hash == NULL || dz->dz_hash[h] == NULL) - continue; - if (dn_hash_dump_bucket(skb, cb, tb, dz, dz->dz_hash[h]) < 0) { - cb->args[3] = h; - return -1; - } - } - cb->args[3] = h; - return skb->len; -} - -static int dn_fib_table_dump(struct dn_fib_table *tb, struct sk_buff *skb, - struct netlink_callback *cb) -{ - int m, s_m; - struct dn_zone *dz; - struct dn_hash *table = (struct dn_hash *)tb->data; - - s_m = cb->args[2]; - read_lock(&dn_fib_tables_lock); - for(dz = table->dh_zone_list, m = 0; dz; dz = dz->dz_next, m++) { - if (m < s_m) - continue; - if (m > s_m) - memset(&cb->args[3], 0, sizeof(cb->args) - 3*sizeof(cb->args[0])); - - if (dn_hash_dump_zone(skb, cb, tb, dz) < 0) { - cb->args[2] = m; - read_unlock(&dn_fib_tables_lock); - return -1; - } - } - read_unlock(&dn_fib_tables_lock); - cb->args[2] = m; - - return skb->len; -} - -int dn_fib_dump(struct sk_buff *skb, struct netlink_callback *cb) -{ - struct net *net = sock_net(skb->sk); - unsigned int h, s_h; - unsigned int e = 0, s_e; - struct dn_fib_table *tb; - int dumped = 0; - - if (!net_eq(net, &init_net)) - return 0; - - if (nlmsg_len(cb->nlh) >= sizeof(struct rtmsg) && - ((struct rtmsg *)nlmsg_data(cb->nlh))->rtm_flags&RTM_F_CLONED) - return dn_cache_dump(skb, cb); - - s_h = cb->args[0]; - s_e = cb->args[1]; - - for (h = s_h; h < DN_FIB_TABLE_HASHSZ; h++, s_h = 0) { - e = 0; - hlist_for_each_entry(tb, &dn_fib_table_hash[h], hlist) { - if (e < s_e) - goto next; - if (dumped) - memset(&cb->args[2], 0, sizeof(cb->args) - - 2 * sizeof(cb->args[0])); - if (tb->dump(tb, skb, cb) < 0) - goto out; - dumped = 1; -next: - e++; - } - } -out: - cb->args[1] = e; - cb->args[0] = h; - - return skb->len; -} - -static int dn_fib_table_insert(struct dn_fib_table *tb, struct rtmsg *r, struct nlattr *attrs[], - struct nlmsghdr *n, struct netlink_skb_parms *req) -{ - struct dn_hash *table = (struct dn_hash *)tb->data; - struct dn_fib_node *new_f, *f, **fp, **del_fp; - struct dn_zone *dz; - struct dn_fib_info *fi; - int z = r->rtm_dst_len; - int type = r->rtm_type; - dn_fib_key_t key; - int err; - - if (z > 16) - return -EINVAL; - - dz = table->dh_zones[z]; - if (!dz && !(dz = dn_new_zone(table, z))) - return -ENOBUFS; - - dz_key_0(key); - if (attrs[RTA_DST]) { - __le16 dst = nla_get_le16(attrs[RTA_DST]); - if (dst & ~DZ_MASK(dz)) - return -EINVAL; - key = dz_key(dst, dz); - } - - if ((fi = dn_fib_create_info(r, attrs, n, &err)) == NULL) - return err; - - if (dz->dz_nent > (dz->dz_divisor << 2) && - dz->dz_divisor > DN_MAX_DIVISOR && - (z==16 || (1< dz->dz_divisor)) - dn_rehash_zone(dz); - - fp = dn_chain_p(key, dz); - - DN_FIB_SCAN(f, fp) { - if (dn_key_leq(key, f->fn_key)) - break; - } - - del_fp = NULL; - - if (f && (f->fn_state & DN_S_ZOMBIE) && - dn_key_eq(f->fn_key, key)) { - del_fp = fp; - fp = &f->fn_next; - f = *fp; - goto create; - } - - DN_FIB_SCAN_KEY(f, fp, key) { - if (fi->fib_priority <= DN_FIB_INFO(f)->fib_priority) - break; - } - - if (f && dn_key_eq(f->fn_key, key) && - fi->fib_priority == DN_FIB_INFO(f)->fib_priority) { - struct dn_fib_node **ins_fp; - - err = -EEXIST; - if (n->nlmsg_flags & NLM_F_EXCL) - goto out; - - if (n->nlmsg_flags & NLM_F_REPLACE) { - del_fp = fp; - fp = &f->fn_next; - f = *fp; - goto replace; - } - - ins_fp = fp; - err = -EEXIST; - - DN_FIB_SCAN_KEY(f, fp, key) { - if (fi->fib_priority != DN_FIB_INFO(f)->fib_priority) - break; - if (f->fn_type == type && - f->fn_scope == r->rtm_scope && - DN_FIB_INFO(f) == fi) - goto out; - } - - if (!(n->nlmsg_flags & NLM_F_APPEND)) { - fp = ins_fp; - f = *fp; - } - } - -create: - err = -ENOENT; - if (!(n->nlmsg_flags & NLM_F_CREATE)) - goto out; - -replace: - err = -ENOBUFS; - new_f = kmem_cache_zalloc(dn_hash_kmem, GFP_KERNEL); - if (new_f == NULL) - goto out; - - new_f->fn_key = key; - new_f->fn_type = type; - new_f->fn_scope = r->rtm_scope; - DN_FIB_INFO(new_f) = fi; - - new_f->fn_next = f; - write_lock_bh(&dn_fib_tables_lock); - *fp = new_f; - write_unlock_bh(&dn_fib_tables_lock); - dz->dz_nent++; - - if (del_fp) { - f = *del_fp; - write_lock_bh(&dn_fib_tables_lock); - *del_fp = f->fn_next; - write_unlock_bh(&dn_fib_tables_lock); - - if (!(f->fn_state & DN_S_ZOMBIE)) - dn_rtmsg_fib(RTM_DELROUTE, f, z, tb->n, n, req); - if (f->fn_state & DN_S_ACCESSED) - dn_rt_cache_flush(-1); - dn_free_node(f); - dz->dz_nent--; - } else { - dn_rt_cache_flush(-1); - } - - dn_rtmsg_fib(RTM_NEWROUTE, new_f, z, tb->n, n, req); - - return 0; -out: - dn_fib_release_info(fi); - return err; -} - - -static int dn_fib_table_delete(struct dn_fib_table *tb, struct rtmsg *r, struct nlattr *attrs[], - struct nlmsghdr *n, struct netlink_skb_parms *req) -{ - struct dn_hash *table = (struct dn_hash*)tb->data; - struct dn_fib_node **fp, **del_fp, *f; - int z = r->rtm_dst_len; - struct dn_zone *dz; - dn_fib_key_t key; - int matched; - - - if (z > 16) - return -EINVAL; - - if ((dz = table->dh_zones[z]) == NULL) - return -ESRCH; - - dz_key_0(key); - if (attrs[RTA_DST]) { - __le16 dst = nla_get_le16(attrs[RTA_DST]); - if (dst & ~DZ_MASK(dz)) - return -EINVAL; - key = dz_key(dst, dz); - } - - fp = dn_chain_p(key, dz); - - DN_FIB_SCAN(f, fp) { - if (dn_key_eq(f->fn_key, key)) - break; - if (dn_key_leq(key, f->fn_key)) - return -ESRCH; - } - - matched = 0; - del_fp = NULL; - DN_FIB_SCAN_KEY(f, fp, key) { - struct dn_fib_info *fi = DN_FIB_INFO(f); - - if (f->fn_state & DN_S_ZOMBIE) - return -ESRCH; - - matched++; - - if (del_fp == NULL && - (!r->rtm_type || f->fn_type == r->rtm_type) && - (r->rtm_scope == RT_SCOPE_NOWHERE || f->fn_scope == r->rtm_scope) && - (!r->rtm_protocol || - fi->fib_protocol == r->rtm_protocol) && - dn_fib_nh_match(r, n, attrs, fi) == 0) - del_fp = fp; - } - - if (del_fp) { - f = *del_fp; - dn_rtmsg_fib(RTM_DELROUTE, f, z, tb->n, n, req); - - if (matched != 1) { - write_lock_bh(&dn_fib_tables_lock); - *del_fp = f->fn_next; - write_unlock_bh(&dn_fib_tables_lock); - - if (f->fn_state & DN_S_ACCESSED) - dn_rt_cache_flush(-1); - dn_free_node(f); - dz->dz_nent--; - } else { - f->fn_state |= DN_S_ZOMBIE; - if (f->fn_state & DN_S_ACCESSED) { - f->fn_state &= ~DN_S_ACCESSED; - dn_rt_cache_flush(-1); - } - if (++dn_fib_hash_zombies > 128) - dn_fib_flush(); - } - - return 0; - } - - return -ESRCH; -} - -static inline int dn_flush_list(struct dn_fib_node **fp, int z, struct dn_hash *table) -{ - int found = 0; - struct dn_fib_node *f; - - while((f = *fp) != NULL) { - struct dn_fib_info *fi = DN_FIB_INFO(f); - - if (fi && ((f->fn_state & DN_S_ZOMBIE) || (fi->fib_flags & RTNH_F_DEAD))) { - write_lock_bh(&dn_fib_tables_lock); - *fp = f->fn_next; - write_unlock_bh(&dn_fib_tables_lock); - - dn_free_node(f); - found++; - continue; - } - fp = &f->fn_next; - } - - return found; -} - -static int dn_fib_table_flush(struct dn_fib_table *tb) -{ - struct dn_hash *table = (struct dn_hash *)tb->data; - struct dn_zone *dz; - int found = 0; - - dn_fib_hash_zombies = 0; - for(dz = table->dh_zone_list; dz; dz = dz->dz_next) { - int i; - int tmp = 0; - for(i = dz->dz_divisor-1; i >= 0; i--) - tmp += dn_flush_list(&dz->dz_hash[i], dz->dz_order, table); - dz->dz_nent -= tmp; - found += tmp; - } - - return found; -} - -static int dn_fib_table_lookup(struct dn_fib_table *tb, const struct flowidn *flp, struct dn_fib_res *res) -{ - int err; - struct dn_zone *dz; - struct dn_hash *t = (struct dn_hash *)tb->data; - - read_lock(&dn_fib_tables_lock); - for(dz = t->dh_zone_list; dz; dz = dz->dz_next) { - struct dn_fib_node *f; - dn_fib_key_t k = dz_key(flp->daddr, dz); - - for(f = dz_chain(k, dz); f; f = f->fn_next) { - if (!dn_key_eq(k, f->fn_key)) { - if (dn_key_leq(k, f->fn_key)) - break; - else - continue; - } - - f->fn_state |= DN_S_ACCESSED; - - if (f->fn_state&DN_S_ZOMBIE) - continue; - - if (f->fn_scope < flp->flowidn_scope) - continue; - - err = dn_fib_semantic_match(f->fn_type, DN_FIB_INFO(f), flp, res); - - if (err == 0) { - res->type = f->fn_type; - res->scope = f->fn_scope; - res->prefixlen = dz->dz_order; - goto out; - } - if (err < 0) - goto out; - } - } - err = 1; -out: - read_unlock(&dn_fib_tables_lock); - return err; -} - - -struct dn_fib_table *dn_fib_get_table(u32 n, int create) -{ - struct dn_fib_table *t; - unsigned int h; - - if (n < RT_TABLE_MIN) - return NULL; - - if (n > RT_TABLE_MAX) - return NULL; - - h = n & (DN_FIB_TABLE_HASHSZ - 1); - rcu_read_lock(); - hlist_for_each_entry_rcu(t, &dn_fib_table_hash[h], hlist) { - if (t->n == n) { - rcu_read_unlock(); - return t; - } - } - rcu_read_unlock(); - - if (!create) - return NULL; - - if (in_interrupt()) { - net_dbg_ratelimited("DECnet: BUG! Attempt to create routing table from interrupt\n"); - return NULL; - } - - t = kzalloc(sizeof(struct dn_fib_table) + sizeof(struct dn_hash), - GFP_KERNEL); - if (t == NULL) - return NULL; - - t->n = n; - t->insert = dn_fib_table_insert; - t->delete = dn_fib_table_delete; - t->lookup = dn_fib_table_lookup; - t->flush = dn_fib_table_flush; - t->dump = dn_fib_table_dump; - hlist_add_head_rcu(&t->hlist, &dn_fib_table_hash[h]); - - return t; -} - -struct dn_fib_table *dn_fib_empty_table(void) -{ - u32 id; - - for(id = RT_TABLE_MIN; id <= RT_TABLE_MAX; id++) - if (dn_fib_get_table(id, 0) == NULL) - return dn_fib_get_table(id, 1); - return NULL; -} - -void dn_fib_flush(void) -{ - int flushed = 0; - struct dn_fib_table *tb; - unsigned int h; - - for (h = 0; h < DN_FIB_TABLE_HASHSZ; h++) { - hlist_for_each_entry(tb, &dn_fib_table_hash[h], hlist) - flushed += tb->flush(tb); - } - - if (flushed) - dn_rt_cache_flush(-1); -} - -void __init dn_fib_table_init(void) -{ - dn_hash_kmem = kmem_cache_create("dn_fib_info_cache", - sizeof(struct dn_fib_info), - 0, SLAB_HWCACHE_ALIGN, - NULL); -} - -void __exit dn_fib_table_cleanup(void) -{ - struct dn_fib_table *t; - struct hlist_node *next; - unsigned int h; - - write_lock(&dn_fib_tables_lock); - for (h = 0; h < DN_FIB_TABLE_HASHSZ; h++) { - hlist_for_each_entry_safe(t, next, &dn_fib_table_hash[h], - hlist) { - hlist_del(&t->hlist); - kfree(t); - } - } - write_unlock(&dn_fib_tables_lock); -} diff --git a/net/decnet/dn_timer.c b/net/decnet/dn_timer.c deleted file mode 100644 index aa4155875ca84eabb75ab445c4f1adf2612eeac2..0000000000000000000000000000000000000000 --- a/net/decnet/dn_timer.c +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Socket Timer Functions - * - * Author: Steve Whitehouse - * - * - * Changes: - * Steve Whitehouse : Made keepalive timer part of the same - * timer idea. - * Steve Whitehouse : Added checks for sk->sock_readers - * David S. Miller : New socket locking - * Steve Whitehouse : Timer grabs socket ref. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Slow timer is for everything else (n * 500mS) - */ - -#define SLOW_INTERVAL (HZ/2) - -static void dn_slow_timer(struct timer_list *t); - -void dn_start_slow_timer(struct sock *sk) -{ - timer_setup(&sk->sk_timer, dn_slow_timer, 0); - sk_reset_timer(sk, &sk->sk_timer, jiffies + SLOW_INTERVAL); -} - -void dn_stop_slow_timer(struct sock *sk) -{ - sk_stop_timer(sk, &sk->sk_timer); -} - -static void dn_slow_timer(struct timer_list *t) -{ - struct sock *sk = from_timer(sk, t, sk_timer); - struct dn_scp *scp = DN_SK(sk); - - bh_lock_sock(sk); - - if (sock_owned_by_user(sk)) { - sk_reset_timer(sk, &sk->sk_timer, jiffies + HZ / 10); - goto out; - } - - /* - * The persist timer is the standard slow timer used for retransmits - * in both connection establishment and disconnection as well as - * in the RUN state. The different states are catered for by changing - * the function pointer in the socket. Setting the timer to a value - * of zero turns it off. We allow the persist_fxn to turn the - * timer off in a permant way by returning non-zero, so that - * timer based routines may remove sockets. This is why we have a - * sock_hold()/sock_put() around the timer to prevent the socket - * going away in the middle. - */ - if (scp->persist && scp->persist_fxn) { - if (scp->persist <= SLOW_INTERVAL) { - scp->persist = 0; - - if (scp->persist_fxn(sk)) - goto out; - } else { - scp->persist -= SLOW_INTERVAL; - } - } - - /* - * Check for keepalive timeout. After the other timer 'cos if - * the previous timer caused a retransmit, we don't need to - * do this. scp->stamp is the last time that we sent a packet. - * The keepalive function sends a link service packet to the - * other end. If it remains unacknowledged, the standard - * socket timers will eventually shut the socket down. Each - * time we do this, scp->stamp will be updated, thus - * we won't try and send another until scp->keepalive has passed - * since the last successful transmission. - */ - if (scp->keepalive && scp->keepalive_fxn && (scp->state == DN_RUN)) { - if (time_after_eq(jiffies, scp->stamp + scp->keepalive)) - scp->keepalive_fxn(sk); - } - - sk_reset_timer(sk, &sk->sk_timer, jiffies + SLOW_INTERVAL); -out: - bh_unlock_sock(sk); - sock_put(sk); -} diff --git a/net/decnet/netfilter/Kconfig b/net/decnet/netfilter/Kconfig deleted file mode 100644 index 8d7c109d5109d36ca4d532c8e118802907e3415a..0000000000000000000000000000000000000000 --- a/net/decnet/netfilter/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# DECnet netfilter configuration -# - -menu "DECnet: Netfilter Configuration" - depends on DECNET && NETFILTER - depends on NETFILTER_ADVANCED - -config DECNET_NF_GRABULATOR - tristate "Routing message grabulator (for userland routing daemon)" - help - Enable this module if you want to use the userland DECnet routing - daemon. You will also need to enable routing support for DECnet - unless you just want to monitor routing messages from other nodes. - -endmenu diff --git a/net/decnet/netfilter/Makefile b/net/decnet/netfilter/Makefile deleted file mode 100644 index b579e52130aa079a2ab6de08619bbc756b0db14b..0000000000000000000000000000000000000000 --- a/net/decnet/netfilter/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for DECnet netfilter modules -# - -obj-$(CONFIG_DECNET_NF_GRABULATOR) += dn_rtmsg.o diff --git a/net/decnet/netfilter/dn_rtmsg.c b/net/decnet/netfilter/dn_rtmsg.c deleted file mode 100644 index a4faacadd8a830b4f09eaa444e40b72a7e7807f8..0000000000000000000000000000000000000000 --- a/net/decnet/netfilter/dn_rtmsg.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Routing Message Grabulator - * - * (C) 2000 ChyGwyn Limited - http://www.chygwyn.com/ - * This code may be copied under the GPL v.2 or at your option - * any later version. - * - * Author: Steven Whitehouse - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -static struct sock *dnrmg = NULL; - - -static struct sk_buff *dnrmg_build_message(struct sk_buff *rt_skb, int *errp) -{ - struct sk_buff *skb = NULL; - size_t size; - sk_buff_data_t old_tail; - struct nlmsghdr *nlh; - unsigned char *ptr; - struct nf_dn_rtmsg *rtm; - - size = NLMSG_ALIGN(rt_skb->len) + - NLMSG_ALIGN(sizeof(struct nf_dn_rtmsg)); - skb = nlmsg_new(size, GFP_ATOMIC); - if (!skb) { - *errp = -ENOMEM; - return NULL; - } - old_tail = skb->tail; - nlh = nlmsg_put(skb, 0, 0, 0, size, 0); - if (!nlh) { - kfree_skb(skb); - *errp = -ENOMEM; - return NULL; - } - rtm = (struct nf_dn_rtmsg *)nlmsg_data(nlh); - rtm->nfdn_ifindex = rt_skb->dev->ifindex; - ptr = NFDN_RTMSG(rtm); - skb_copy_from_linear_data(rt_skb, ptr, rt_skb->len); - nlh->nlmsg_len = skb->tail - old_tail; - return skb; -} - -static void dnrmg_send_peer(struct sk_buff *skb) -{ - struct sk_buff *skb2; - int status = 0; - int group = 0; - unsigned char flags = *skb->data; - - switch (flags & DN_RT_CNTL_MSK) { - case DN_RT_PKT_L1RT: - group = DNRNG_NLGRP_L1; - break; - case DN_RT_PKT_L2RT: - group = DNRNG_NLGRP_L2; - break; - default: - return; - } - - skb2 = dnrmg_build_message(skb, &status); - if (skb2 == NULL) - return; - NETLINK_CB(skb2).dst_group = group; - netlink_broadcast(dnrmg, skb2, 0, group, GFP_ATOMIC); -} - - -static unsigned int dnrmg_hook(void *priv, - struct sk_buff *skb, - const struct nf_hook_state *state) -{ - dnrmg_send_peer(skb); - return NF_ACCEPT; -} - - -#define RCV_SKB_FAIL(err) do { netlink_ack(skb, nlh, (err), NULL); return; } while (0) - -static inline void dnrmg_receive_user_skb(struct sk_buff *skb) -{ - struct nlmsghdr *nlh = nlmsg_hdr(skb); - - if (skb->len < sizeof(*nlh) || - nlh->nlmsg_len < sizeof(*nlh) || - skb->len < nlh->nlmsg_len) - return; - - if (!netlink_capable(skb, CAP_NET_ADMIN)) - RCV_SKB_FAIL(-EPERM); - - /* Eventually we might send routing messages too */ - - RCV_SKB_FAIL(-EINVAL); -} - -static const struct nf_hook_ops dnrmg_ops = { - .hook = dnrmg_hook, - .pf = NFPROTO_DECNET, - .hooknum = NF_DN_ROUTE, - .priority = NF_DN_PRI_DNRTMSG, -}; - -static int __init dn_rtmsg_init(void) -{ - int rv = 0; - struct netlink_kernel_cfg cfg = { - .groups = DNRNG_NLGRP_MAX, - .input = dnrmg_receive_user_skb, - }; - - dnrmg = netlink_kernel_create(&init_net, NETLINK_DNRTMSG, &cfg); - if (dnrmg == NULL) { - printk(KERN_ERR "dn_rtmsg: Cannot create netlink socket"); - return -ENOMEM; - } - - rv = nf_register_net_hook(&init_net, &dnrmg_ops); - if (rv) { - netlink_kernel_release(dnrmg); - } - - return rv; -} - -static void __exit dn_rtmsg_fini(void) -{ - nf_unregister_net_hook(&init_net, &dnrmg_ops); - netlink_kernel_release(dnrmg); -} - - -MODULE_DESCRIPTION("DECnet Routing Message Grabulator"); -MODULE_AUTHOR("Steven Whitehouse "); -MODULE_LICENSE("GPL"); -MODULE_ALIAS_NET_PF_PROTO(PF_NETLINK, NETLINK_DNRTMSG); - -module_init(dn_rtmsg_init); -module_exit(dn_rtmsg_fini); diff --git a/net/decnet/sysctl_net_decnet.c b/net/decnet/sysctl_net_decnet.c deleted file mode 100644 index 55bf64a22b59339bdef582d2e7fd297c00d226fb..0000000000000000000000000000000000000000 --- a/net/decnet/sysctl_net_decnet.c +++ /dev/null @@ -1,373 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet sysctl support functions - * - * Author: Steve Whitehouse - * - * - * Changes: - * Steve Whitehouse - C99 changes and default device handling - * Steve Whitehouse - Memory buffer settings, like the tcp ones - * - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - - -int decnet_debug_level; -int decnet_time_wait = 30; -int decnet_dn_count = 1; -int decnet_di_count = 3; -int decnet_dr_count = 3; -int decnet_log_martians = 1; -int decnet_no_fc_max_cwnd = NSP_MIN_WINDOW; - -/* Reasonable defaults, I hope, based on tcp's defaults */ -long sysctl_decnet_mem[3] = { 768 << 3, 1024 << 3, 1536 << 3 }; -int sysctl_decnet_wmem[3] = { 4 * 1024, 16 * 1024, 128 * 1024 }; -int sysctl_decnet_rmem[3] = { 4 * 1024, 87380, 87380 * 2 }; - -#ifdef CONFIG_SYSCTL -extern int decnet_dst_gc_interval; -static int min_decnet_time_wait[] = { 5 }; -static int max_decnet_time_wait[] = { 600 }; -static int min_state_count[] = { 1 }; -static int max_state_count[] = { NSP_MAXRXTSHIFT }; -static int min_decnet_dst_gc_interval[] = { 1 }; -static int max_decnet_dst_gc_interval[] = { 60 }; -static int min_decnet_no_fc_max_cwnd[] = { NSP_MIN_WINDOW }; -static int max_decnet_no_fc_max_cwnd[] = { NSP_MAX_WINDOW }; -static char node_name[7] = "???"; - -static struct ctl_table_header *dn_table_header = NULL; - -/* - * ctype.h :-) - */ -#define ISNUM(x) (((x) >= '0') && ((x) <= '9')) -#define ISLOWER(x) (((x) >= 'a') && ((x) <= 'z')) -#define ISUPPER(x) (((x) >= 'A') && ((x) <= 'Z')) -#define ISALPHA(x) (ISLOWER(x) || ISUPPER(x)) -#define INVALID_END_CHAR(x) (ISNUM(x) || ISALPHA(x)) - -static void strip_it(char *str) -{ - for(;;) { - switch (*str) { - case ' ': - case '\n': - case '\r': - case ':': - *str = 0; - /* Fallthrough */ - case 0: - return; - } - str++; - } -} - -/* - * Simple routine to parse an ascii DECnet address - * into a network order address. - */ -static int parse_addr(__le16 *addr, char *str) -{ - __u16 area, node; - - while(*str && !ISNUM(*str)) str++; - - if (*str == 0) - return -1; - - area = (*str++ - '0'); - if (ISNUM(*str)) { - area *= 10; - area += (*str++ - '0'); - } - - if (*str++ != '.') - return -1; - - if (!ISNUM(*str)) - return -1; - - node = *str++ - '0'; - if (ISNUM(*str)) { - node *= 10; - node += (*str++ - '0'); - } - if (ISNUM(*str)) { - node *= 10; - node += (*str++ - '0'); - } - if (ISNUM(*str)) { - node *= 10; - node += (*str++ - '0'); - } - - if ((node > 1023) || (area > 63)) - return -1; - - if (INVALID_END_CHAR(*str)) - return -1; - - *addr = cpu_to_le16((area << 10) | node); - - return 0; -} - -static int dn_node_address_handler(struct ctl_table *table, int write, - void __user *buffer, - size_t *lenp, loff_t *ppos) -{ - char addr[DN_ASCBUF_LEN]; - size_t len; - __le16 dnaddr; - - if (!*lenp || (*ppos && !write)) { - *lenp = 0; - return 0; - } - - if (write) { - len = (*lenp < DN_ASCBUF_LEN) ? *lenp : (DN_ASCBUF_LEN-1); - - if (copy_from_user(addr, buffer, len)) - return -EFAULT; - - addr[len] = 0; - strip_it(addr); - - if (parse_addr(&dnaddr, addr)) - return -EINVAL; - - dn_dev_devices_off(); - - decnet_address = dnaddr; - - dn_dev_devices_on(); - - *ppos += len; - - return 0; - } - - dn_addr2asc(le16_to_cpu(decnet_address), addr); - len = strlen(addr); - addr[len++] = '\n'; - - if (len > *lenp) len = *lenp; - - if (copy_to_user(buffer, addr, len)) - return -EFAULT; - - *lenp = len; - *ppos += len; - - return 0; -} - -static int dn_def_dev_handler(struct ctl_table *table, int write, - void __user *buffer, - size_t *lenp, loff_t *ppos) -{ - size_t len; - struct net_device *dev; - char devname[17]; - - if (!*lenp || (*ppos && !write)) { - *lenp = 0; - return 0; - } - - if (write) { - if (*lenp > 16) - return -E2BIG; - - if (copy_from_user(devname, buffer, *lenp)) - return -EFAULT; - - devname[*lenp] = 0; - strip_it(devname); - - dev = dev_get_by_name(&init_net, devname); - if (dev == NULL) - return -ENODEV; - - if (dev->dn_ptr == NULL) { - dev_put(dev); - return -ENODEV; - } - - if (dn_dev_set_default(dev, 1)) { - dev_put(dev); - return -ENODEV; - } - *ppos += *lenp; - - return 0; - } - - dev = dn_dev_get_default(); - if (dev == NULL) { - *lenp = 0; - return 0; - } - - strcpy(devname, dev->name); - dev_put(dev); - len = strlen(devname); - devname[len++] = '\n'; - - if (len > *lenp) len = *lenp; - - if (copy_to_user(buffer, devname, len)) - return -EFAULT; - - *lenp = len; - *ppos += len; - - return 0; -} - -static struct ctl_table dn_table[] = { - { - .procname = "node_address", - .maxlen = 7, - .mode = 0644, - .proc_handler = dn_node_address_handler, - }, - { - .procname = "node_name", - .data = node_name, - .maxlen = 7, - .mode = 0644, - .proc_handler = proc_dostring, - }, - { - .procname = "default_device", - .maxlen = 16, - .mode = 0644, - .proc_handler = dn_def_dev_handler, - }, - { - .procname = "time_wait", - .data = &decnet_time_wait, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_decnet_time_wait, - .extra2 = &max_decnet_time_wait - }, - { - .procname = "dn_count", - .data = &decnet_dn_count, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_state_count, - .extra2 = &max_state_count - }, - { - .procname = "di_count", - .data = &decnet_di_count, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_state_count, - .extra2 = &max_state_count - }, - { - .procname = "dr_count", - .data = &decnet_dr_count, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_state_count, - .extra2 = &max_state_count - }, - { - .procname = "dst_gc_interval", - .data = &decnet_dst_gc_interval, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_decnet_dst_gc_interval, - .extra2 = &max_decnet_dst_gc_interval - }, - { - .procname = "no_fc_max_cwnd", - .data = &decnet_no_fc_max_cwnd, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_decnet_no_fc_max_cwnd, - .extra2 = &max_decnet_no_fc_max_cwnd - }, - { - .procname = "decnet_mem", - .data = &sysctl_decnet_mem, - .maxlen = sizeof(sysctl_decnet_mem), - .mode = 0644, - .proc_handler = proc_doulongvec_minmax - }, - { - .procname = "decnet_rmem", - .data = &sysctl_decnet_rmem, - .maxlen = sizeof(sysctl_decnet_rmem), - .mode = 0644, - .proc_handler = proc_dointvec, - }, - { - .procname = "decnet_wmem", - .data = &sysctl_decnet_wmem, - .maxlen = sizeof(sysctl_decnet_wmem), - .mode = 0644, - .proc_handler = proc_dointvec, - }, - { - .procname = "debug", - .data = &decnet_debug_level, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec, - }, - { } -}; - -void dn_register_sysctl(void) -{ - dn_table_header = register_net_sysctl(&init_net, "net/decnet", dn_table); -} - -void dn_unregister_sysctl(void) -{ - unregister_net_sysctl_table(dn_table_header); -} - -#else /* CONFIG_SYSCTL */ -void dn_unregister_sysctl(void) -{ -} -void dn_register_sysctl(void) -{ -} - -#endif diff --git a/net/ipv4/esp4.c b/net/ipv4/esp4.c index 203569500b91468ee957716446dccd7a448879bb..24cd5c9c78392124e81817124f0e7a2e989051e3 100644 --- a/net/ipv4/esp4.c +++ b/net/ipv4/esp4.c @@ -565,7 +565,9 @@ static inline int esp_remove_trailer(struct sk_buff *skb) skb->csum = csum_block_sub(skb->csum, csumdiff, skb->len - trimlen); } - pskb_trim(skb, skb->len - trimlen); + ret = pskb_trim(skb, skb->len - trimlen); + if (unlikely(ret)) + return ret; ret = nexthdr[1]; diff --git a/net/ipv4/esp4_offload.c b/net/ipv4/esp4_offload.c index 58834a10c0be77b3d301169f505dcdc7896dd3f4..93045373e44bdc01c35699b574c364d320c36647 100644 --- a/net/ipv4/esp4_offload.c +++ b/net/ipv4/esp4_offload.c @@ -237,6 +237,9 @@ static int esp_xmit(struct xfrm_state *x, struct sk_buff *skb, netdev_features_ secpath_reset(skb); + if (skb_needs_linearize(skb, skb->dev->features) && + __skb_linearize(skb)) + return -ENOMEM; return 0; } diff --git a/net/ipv4/fib_frontend.c b/net/ipv4/fib_frontend.c index 1885a2fbad86232602bbe8aeb99afd9071eb8b98..9aa48b4c40960a1a70000003e001a0895fb4a3e3 100644 --- a/net/ipv4/fib_frontend.c +++ b/net/ipv4/fib_frontend.c @@ -557,6 +557,9 @@ static int rtentry_to_fib_config(struct net *net, int cmd, struct rtentry *rt, cfg->fc_scope = RT_SCOPE_UNIVERSE; } + if (!cfg->fc_table) + cfg->fc_table = RT_TABLE_MAIN; + if (cmd == SIOCDELRT) return 0; diff --git a/net/ipv4/icmp.c b/net/ipv4/icmp.c index aa179e6461e179818e4cdfaa4261861527a56db9..af0ddaa55e431313d43635dc1b66288c0d1dfb69 100644 --- a/net/ipv4/icmp.c +++ b/net/ipv4/icmp.c @@ -759,6 +759,11 @@ void __icmp_send(struct sk_buff *skb_in, int type, int code, __be32 info, room = 576; room -= sizeof(struct iphdr) + icmp_param.replyopts.opt.opt.optlen; room -= sizeof(struct icmphdr); + /* Guard against tiny mtu. We need to include at least one + * IP network header for this message to make any sense. + */ + if (room <= (int)sizeof(struct iphdr)) + goto ende; icmp_param.data_len = skb_in->len - icmp_param.offset; if (icmp_param.data_len > room) diff --git a/net/ipv4/igmp.c b/net/ipv4/igmp.c index 45ac582ad2b0bd97d0576e4d8e0509678b2dcea4..04202d08313303796120153fe56047f2c4e77978 100644 --- a/net/ipv4/igmp.c +++ b/net/ipv4/igmp.c @@ -357,8 +357,9 @@ static struct sk_buff *igmpv3_newpack(struct net_device *dev, unsigned int mtu) struct flowi4 fl4; int hlen = LL_RESERVED_SPACE(dev); int tlen = dev->needed_tailroom; - unsigned int size = mtu; + unsigned int size; + size = min(mtu, IP_MAX_MTU); while (1) { skb = alloc_skb(size + hlen + tlen, GFP_ATOMIC | __GFP_NOWARN); diff --git a/net/ipv4/inet_connection_sock.c b/net/ipv4/inet_connection_sock.c index 70f1e78107db9a50b77feee2487b40752adad05d..9679553577c09133f2359505f6936a0f8ca76e9c 100644 --- a/net/ipv4/inet_connection_sock.c +++ b/net/ipv4/inet_connection_sock.c @@ -941,6 +941,7 @@ int inet_csk_listen_start(struct sock *sk, int backlog) * It is OK, because this socket enters to hash table only * after validation is complete. */ + err = -EADDRINUSE; inet_sk_state_store(sk, TCP_LISTEN); if (!sk->sk_prot->get_port(sk, inet->inet_num)) { inet->inet_sport = htons(inet->inet_num); diff --git a/net/ipv4/inet_hashtables.c b/net/ipv4/inet_hashtables.c index d64522af9c3a8e91ba199a4917aeb88dc37343cf..c6d670cd872f07f159d7e04ab526058cadc4e0b4 100644 --- a/net/ipv4/inet_hashtables.c +++ b/net/ipv4/inet_hashtables.c @@ -579,20 +579,8 @@ bool inet_ehash_insert(struct sock *sk, struct sock *osk, bool *found_dup_sk) spin_lock(lock); if (osk) { WARN_ON_ONCE(sk->sk_hash != osk->sk_hash); - ret = sk_hashed(osk); - if (ret) { - /* Before deleting the node, we insert a new one to make - * sure that the look-up-sk process would not miss either - * of them and that at least one node would exist in ehash - * table all the time. Otherwise there's a tiny chance - * that lookup process could find nothing in ehash table. - */ - __sk_nulls_add_node_tail_rcu(sk, list); - sk_nulls_del_node_init_rcu(osk); - } - goto unlock; - } - if (found_dup_sk) { + ret = sk_nulls_del_node_init_rcu(osk); + } else if (found_dup_sk) { *found_dup_sk = inet_ehash_lookup_by_sk(sk, list); if (*found_dup_sk) ret = false; @@ -601,7 +589,6 @@ bool inet_ehash_insert(struct sock *sk, struct sock *osk, bool *found_dup_sk) if (ret) __sk_nulls_add_node_rcu(sk, list); -unlock: spin_unlock(lock); return ret; @@ -756,17 +743,7 @@ int __inet_hash_connect(struct inet_timewait_death_row *death_row, u32 index; if (port) { - head = &hinfo->bhash[inet_bhashfn(net, port, - hinfo->bhash_size)]; - tb = inet_csk(sk)->icsk_bind_hash; - spin_lock_bh(&head->lock); - if (sk_head(&tb->owners) == sk && !sk->sk_bind_node.next) { - inet_ehash_nolisten(sk, NULL, NULL); - spin_unlock_bh(&head->lock); - return 0; - } - spin_unlock(&head->lock); - /* No definite answer... Walk to established hash table */ + local_bh_disable(); ret = check_established(death_row, sk, port, NULL); local_bh_enable(); return ret; diff --git a/net/ipv4/inet_timewait_sock.c b/net/ipv4/inet_timewait_sock.c index fedd19c22b39260420478e741cc1299bd8dcf79f..88c5069b5d20c74a63323a284f8346aa90efb865 100644 --- a/net/ipv4/inet_timewait_sock.c +++ b/net/ipv4/inet_timewait_sock.c @@ -80,10 +80,10 @@ void inet_twsk_put(struct inet_timewait_sock *tw) } EXPORT_SYMBOL_GPL(inet_twsk_put); -static void inet_twsk_add_node_tail_rcu(struct inet_timewait_sock *tw, - struct hlist_nulls_head *list) +static void inet_twsk_add_node_rcu(struct inet_timewait_sock *tw, + struct hlist_nulls_head *list) { - hlist_nulls_add_tail_rcu(&tw->tw_node, list); + hlist_nulls_add_head_rcu(&tw->tw_node, list); } static void inet_twsk_add_bind_node(struct inet_timewait_sock *tw, @@ -119,7 +119,7 @@ void inet_twsk_hashdance(struct inet_timewait_sock *tw, struct sock *sk, spin_lock(lock); - inet_twsk_add_node_tail_rcu(tw, &ehead->chain); + inet_twsk_add_node_rcu(tw, &ehead->chain); /* Step 3: Remove SK from hash chain */ if (__sk_nulls_del_node_init_rcu(sk)) diff --git a/net/ipv4/ip_gre.c b/net/ipv4/ip_gre.c index c72432ce9bf504c1284b034161f2b7fe15be4b37..e16373640f4c24069f915e7c560c771fad24aba0 100644 --- a/net/ipv4/ip_gre.c +++ b/net/ipv4/ip_gre.c @@ -440,7 +440,7 @@ static void __gre_xmit(struct sk_buff *skb, struct net_device *dev, /* Push GRE header. */ gre_build_header(skb, tunnel->tun_hlen, flags, proto, tunnel->parms.o_key, - (flags & TUNNEL_SEQ) ? htonl(tunnel->o_seqno++) : 0); + (flags & TUNNEL_SEQ) ? htonl(atomic_fetch_inc(&tunnel->o_seqno)) : 0); ip_tunnel_xmit(skb, dev, tnl_params, tnl_params->protocol); } @@ -546,7 +546,7 @@ static void gre_fb_xmit(struct sk_buff *skb, struct net_device *dev, (TUNNEL_CSUM | TUNNEL_KEY | TUNNEL_SEQ); gre_build_header(skb, tunnel_hlen, flags, proto, tunnel_id_to_key32(tun_info->key.tun_id), - (flags & TUNNEL_SEQ) ? htonl(tunnel->o_seqno++) : 0); + (flags & TUNNEL_SEQ) ? htonl(atomic_fetch_inc(&tunnel->o_seqno)) : 0); df = key->tun_flags & TUNNEL_DONT_FRAGMENT ? htons(IP_DF) : 0; @@ -603,7 +603,7 @@ static void erspan_fb_xmit(struct sk_buff *skb, struct net_device *dev) truncate = true; } - nhoff = skb_network_header(skb) - skb_mac_header(skb); + nhoff = skb_network_offset(skb); if (skb->protocol == htons(ETH_P_IP) && (ntohs(ip_hdr(skb)->tot_len) > skb->len - nhoff)) truncate = true; @@ -612,7 +612,7 @@ static void erspan_fb_xmit(struct sk_buff *skb, struct net_device *dev) int thoff; if (skb_transport_header_was_set(skb)) - thoff = skb_transport_header(skb) - skb_mac_header(skb); + thoff = skb_transport_offset(skb); else thoff = nhoff + sizeof(struct ipv6hdr); if (ntohs(ipv6_hdr(skb)->payload_len) > skb->len - thoff) @@ -635,7 +635,7 @@ static void erspan_fb_xmit(struct sk_buff *skb, struct net_device *dev) } gre_build_header(skb, 8, TUNNEL_SEQ, - proto, 0, htonl(tunnel->o_seqno++)); + proto, 0, htonl(atomic_fetch_inc(&tunnel->o_seqno))); df = key->tun_flags & TUNNEL_DONT_FRAGMENT ? htons(IP_DF) : 0; diff --git a/net/ipv4/ip_output.c b/net/ipv4/ip_output.c index 06a981676356c39a78970ff3b7d12c1995323323..6936f703758bba5f0428839daa9636f2b7f8cfc8 100644 --- a/net/ipv4/ip_output.c +++ b/net/ipv4/ip_output.c @@ -221,7 +221,7 @@ static int ip_finish_output2(struct net *net, struct sock *sk, struct sk_buff *s if (lwtunnel_xmit_redirect(dst->lwtstate)) { int res = lwtunnel_xmit(skb); - if (res < 0 || res == LWTUNNEL_XMIT_DONE) + if (res != LWTUNNEL_XMIT_CONTINUE) return res; } @@ -1443,9 +1443,19 @@ struct sk_buff *__ip_make_skb(struct sock *sk, cork->dst = NULL; skb_dst_set(skb, &rt->dst); - if (iph->protocol == IPPROTO_ICMP) - icmp_out_count(net, ((struct icmphdr *) - skb_transport_header(skb))->type); + if (iph->protocol == IPPROTO_ICMP) { + u8 icmp_type; + + /* For such sockets, transhdrlen is zero when do ip_append_data(), + * so icmphdr does not in skb linear region and can not get icmp_type + * by icmp_hdr(skb)->type. + */ + if (sk->sk_type == SOCK_RAW && !inet_sk(sk)->hdrincl) + icmp_type = fl4->fl4_icmp_type; + else + icmp_type = icmp_hdr(skb)->type; + icmp_out_count(net, icmp_type); + } ip_cork_release(cork); out: diff --git a/net/ipv4/ip_sockglue.c b/net/ipv4/ip_sockglue.c index 82f341e84faecf3d273ea87785ca98d42f648f67..fbf39077fc545bef8d3af365fdb759d5ce05c6d3 100644 --- a/net/ipv4/ip_sockglue.c +++ b/net/ipv4/ip_sockglue.c @@ -316,7 +316,14 @@ int ip_cmsg_send(struct sock *sk, struct msghdr *msg, struct ipcm_cookie *ipc, ipc->tos = val; ipc->priority = rt_tos2priority(ipc->tos); break; - + case IP_PROTOCOL: + if (cmsg->cmsg_len != CMSG_LEN(sizeof(int))) + return -EINVAL; + val = *(int *)CMSG_DATA(cmsg); + if (val < 1 || val > 255) + return -EINVAL; + ipc->protocol = val; + break; default: return -EINVAL; } @@ -1522,6 +1529,9 @@ static int do_ip_getsockopt(struct sock *sk, int level, int optname, case IP_MINTTL: val = inet->min_ttl; break; + case IP_PROTOCOL: + val = inet_sk(sk)->inet_num; + break; default: release_sock(sk); return -ENOPROTOOPT; diff --git a/net/ipv4/ip_tunnel.c b/net/ipv4/ip_tunnel.c index 30e93b4f831f61bea8870e4df62ca886cb5cd2db..9c2381cf675d647f92da35637bbb5a2d487711b8 100644 --- a/net/ipv4/ip_tunnel.c +++ b/net/ipv4/ip_tunnel.c @@ -609,10 +609,10 @@ void ip_md_tunnel_xmit(struct sk_buff *skb, struct net_device *dev, u8 proto) else if (skb->protocol == htons(ETH_P_IP)) df = inner_iph->frag_off & htons(IP_DF); headroom += LL_RESERVED_SPACE(rt->dst.dev) + rt->dst.header_len; - if (headroom > dev->needed_headroom) - dev->needed_headroom = headroom; + if (headroom > READ_ONCE(dev->needed_headroom)) + WRITE_ONCE(dev->needed_headroom, headroom); - if (skb_cow_head(skb, dev->needed_headroom)) { + if (skb_cow_head(skb, READ_ONCE(dev->needed_headroom))) { ip_rt_put(rt); goto tx_dropped; } @@ -777,10 +777,10 @@ void ip_tunnel_xmit(struct sk_buff *skb, struct net_device *dev, max_headroom = LL_RESERVED_SPACE(rt->dst.dev) + sizeof(struct iphdr) + rt->dst.header_len + ip_encap_hlen(&tunnel->encap); - if (max_headroom > dev->needed_headroom) - dev->needed_headroom = max_headroom; + if (max_headroom > READ_ONCE(dev->needed_headroom)) + WRITE_ONCE(dev->needed_headroom, max_headroom); - if (skb_cow_head(skb, dev->needed_headroom)) { + if (skb_cow_head(skb, READ_ONCE(dev->needed_headroom))) { ip_rt_put(rt); dev->stats.tx_dropped++; kfree_skb(skb); diff --git a/net/ipv4/ip_vti.c b/net/ipv4/ip_vti.c index 15c71b08c2df46024654c2832af9d0432679818e..a3536dfe9b16b1f77b1bc4d99a26bda16afee976 100644 --- a/net/ipv4/ip_vti.c +++ b/net/ipv4/ip_vti.c @@ -319,12 +319,12 @@ static netdev_tx_t vti_tunnel_xmit(struct sk_buff *skb, struct net_device *dev) switch (skb->protocol) { case htons(ETH_P_IP): - xfrm_decode_session(skb, &fl, AF_INET); memset(IPCB(skb), 0, sizeof(*IPCB(skb))); + xfrm_decode_session(skb, &fl, AF_INET); break; case htons(ETH_P_IPV6): - xfrm_decode_session(skb, &fl, AF_INET6); memset(IP6CB(skb), 0, sizeof(*IP6CB(skb))); + xfrm_decode_session(skb, &fl, AF_INET6); break; default: goto tx_err; diff --git a/net/ipv4/netfilter/nf_socket_ipv4.c b/net/ipv4/netfilter/nf_socket_ipv4.c index 4824b1e183a1dc61f5438bb1b56d6a465ca8bf00..bff2b85c5fd6ba8f26b9dca8ca5910c62db667e2 100644 --- a/net/ipv4/netfilter/nf_socket_ipv4.c +++ b/net/ipv4/netfilter/nf_socket_ipv4.c @@ -96,11 +96,11 @@ nf_socket_get_sock_v4(struct net *net, struct sk_buff *skb, const int doff, struct sock *nf_sk_lookup_slow_v4(struct net *net, const struct sk_buff *skb, const struct net_device *indev) { - __be32 uninitialized_var(daddr), uninitialized_var(saddr); - __be16 uninitialized_var(dport), uninitialized_var(sport); + __be32 daddr, saddr; + __be16 dport, sport; const struct iphdr *iph = ip_hdr(skb); struct sk_buff *data_skb = NULL; - u8 uninitialized_var(protocol); + u8 protocol; #if IS_ENABLED(CONFIG_NF_CONNTRACK) enum ip_conntrack_info ctinfo; struct nf_conn const *ct; diff --git a/net/ipv4/netfilter/nft_dup_ipv4.c b/net/ipv4/netfilter/nft_dup_ipv4.c index 0af3d8df70dd713bbe30d469987bab33c295cf99..157bca240edcedf352c55d792dcaa5217a8f5be2 100644 --- a/net/ipv4/netfilter/nft_dup_ipv4.c +++ b/net/ipv4/netfilter/nft_dup_ipv4.c @@ -16,8 +16,8 @@ #include struct nft_dup_ipv4 { - enum nft_registers sreg_addr:8; - enum nft_registers sreg_dev:8; + u8 sreg_addr; + u8 sreg_dev; }; static void nft_dup_ipv4_eval(const struct nft_expr *expr, @@ -43,16 +43,16 @@ static int nft_dup_ipv4_init(const struct nft_ctx *ctx, if (tb[NFTA_DUP_SREG_ADDR] == NULL) return -EINVAL; - priv->sreg_addr = nft_parse_register(tb[NFTA_DUP_SREG_ADDR]); - err = nft_validate_register_load(priv->sreg_addr, sizeof(struct in_addr)); + err = nft_parse_register_load(tb[NFTA_DUP_SREG_ADDR], &priv->sreg_addr, + sizeof(struct in_addr)); if (err < 0) return err; - if (tb[NFTA_DUP_SREG_DEV] != NULL) { - priv->sreg_dev = nft_parse_register(tb[NFTA_DUP_SREG_DEV]); - return nft_validate_register_load(priv->sreg_dev, sizeof(int)); - } - return 0; + if (tb[NFTA_DUP_SREG_DEV]) + err = nft_parse_register_load(tb[NFTA_DUP_SREG_DEV], + &priv->sreg_dev, sizeof(int)); + + return err; } static int nft_dup_ipv4_dump(struct sk_buff *skb, const struct nft_expr *expr) diff --git a/net/ipv4/raw.c b/net/ipv4/raw.c index 654f586fc0d7345f62ed3c6d5a6cbd7a2ad358fa..8ad120c070969d4e5433348c088c1bfe84318a37 100644 --- a/net/ipv4/raw.c +++ b/net/ipv4/raw.c @@ -563,6 +563,9 @@ static int raw_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) } ipcm_init_sk(&ipc, inet); + /* Keep backward compat */ + if (hdrincl) + ipc.protocol = IPPROTO_RAW; if (msg->msg_controllen) { err = ip_cmsg_send(sk, msg, &ipc, false); @@ -630,7 +633,7 @@ static int raw_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) flowi4_init_output(&fl4, ipc.oif, sk->sk_mark, tos, RT_SCOPE_UNIVERSE, - hdrincl ? IPPROTO_RAW : sk->sk_protocol, + hdrincl ? ipc.protocol : sk->sk_protocol, inet_sk_flowi_flags(sk) | (hdrincl ? FLOWI_FLAG_KNOWN_NH : 0), daddr, saddr, 0, 0, sk->sk_uid); diff --git a/net/ipv4/route.c b/net/ipv4/route.c index 57e2316529d00529848ec9f3d9a4a9da904ba0bb..9753d07bfc0bf1d4bb15835bf649b001362617f8 100644 --- a/net/ipv4/route.c +++ b/net/ipv4/route.c @@ -1215,6 +1215,7 @@ static struct dst_entry *ipv4_dst_check(struct dst_entry *dst, u32 cookie) static void ipv4_send_dest_unreach(struct sk_buff *skb) { + struct net_device *dev; struct ip_options opt; int res; @@ -1232,7 +1233,8 @@ static void ipv4_send_dest_unreach(struct sk_buff *skb) opt.optlen = ip_hdr(skb)->ihl * 4 - sizeof(struct iphdr); rcu_read_lock(); - res = __ip_options_compile(dev_net(skb->dev), &opt, skb, NULL); + dev = skb->dev ? skb->dev : skb_rtable(skb)->dst.dev; + res = __ip_options_compile(dev_net(dev), &opt, skb, NULL); rcu_read_unlock(); if (res) diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index aa4d4bf5db9106999e0425f24b1b7508e1e4391e..e5864770c6dff93018b81475f299e7db27ca2223 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -3002,18 +3002,18 @@ static int do_tcp_setsockopt(struct sock *sk, int level, case TCP_LINGER2: if (val < 0) - tp->linger2 = -1; - else if (val > net->ipv4.sysctl_tcp_fin_timeout / HZ) - tp->linger2 = 0; + WRITE_ONCE(tp->linger2, -1); + else if (val > TCP_FIN_TIMEOUT_MAX / HZ) + WRITE_ONCE(tp->linger2, TCP_FIN_TIMEOUT_MAX); else - tp->linger2 = val * HZ; + WRITE_ONCE(tp->linger2, val * HZ); break; case TCP_DEFER_ACCEPT: /* Translate value in seconds to number of retransmits */ - icsk->icsk_accept_queue.rskq_defer_accept = - secs_to_retrans(val, TCP_TIMEOUT_INIT / HZ, - TCP_RTO_MAX / HZ); + WRITE_ONCE(icsk->icsk_accept_queue.rskq_defer_accept, + secs_to_retrans(val, TCP_TIMEOUT_INIT / HZ, + TCP_RTO_MAX / HZ)); break; case TCP_WINDOW_CLAMP: @@ -3101,7 +3101,7 @@ static int do_tcp_setsockopt(struct sock *sk, int level, err = tcp_repair_set_window(tp, optval, optlen); break; case TCP_NOTSENT_LOWAT: - tp->notsent_lowat = val; + WRITE_ONCE(tp->notsent_lowat, val); sk->sk_write_space(sk); break; case TCP_INQ: @@ -3378,7 +3378,8 @@ static int do_tcp_getsockopt(struct sock *sk, int level, switch (optname) { case TCP_MAXSEG: val = tp->mss_cache; - if (!val && ((1 << sk->sk_state) & (TCPF_CLOSE | TCPF_LISTEN))) + if (tp->rx_opt.user_mss && + ((1 << sk->sk_state) & (TCPF_CLOSE | TCPF_LISTEN))) val = tp->rx_opt.user_mss; if (tp->repair) val = tp->rx_opt.mss_clamp; @@ -3402,13 +3403,14 @@ static int do_tcp_getsockopt(struct sock *sk, int level, val = icsk->icsk_syn_retries ? : net->ipv4.sysctl_tcp_syn_retries; break; case TCP_LINGER2: - val = tp->linger2; + val = READ_ONCE(tp->linger2); if (val >= 0) val = (val ? : READ_ONCE(net->ipv4.sysctl_tcp_fin_timeout)) / HZ; break; case TCP_DEFER_ACCEPT: - val = retrans_to_secs(icsk->icsk_accept_queue.rskq_defer_accept, - TCP_TIMEOUT_INIT / HZ, TCP_RTO_MAX / HZ); + val = READ_ONCE(icsk->icsk_accept_queue.rskq_defer_accept); + val = retrans_to_secs(val, TCP_TIMEOUT_INIT / HZ, + TCP_RTO_MAX / HZ); break; case TCP_WINDOW_CLAMP: val = tp->window_clamp; @@ -3554,7 +3556,7 @@ static int do_tcp_getsockopt(struct sock *sk, int level, break; case TCP_FASTOPEN: - val = icsk->icsk_accept_queue.fastopenq.max_qlen; + val = READ_ONCE(icsk->icsk_accept_queue.fastopenq.max_qlen); break; case TCP_FASTOPEN_CONNECT: @@ -3569,7 +3571,7 @@ static int do_tcp_getsockopt(struct sock *sk, int level, val = tcp_time_stamp_raw() + tp->tsoffset; break; case TCP_NOTSENT_LOWAT: - val = tp->notsent_lowat; + val = READ_ONCE(tp->notsent_lowat); break; case TCP_INQ: val = tp->recvmsg_inq; diff --git a/net/ipv4/tcp_fastopen.c b/net/ipv4/tcp_fastopen.c index f726591de7c7a34b086c2935daae529cc9ca328d..f7bb78b443fa94992605c24f28cdf97006451265 100644 --- a/net/ipv4/tcp_fastopen.c +++ b/net/ipv4/tcp_fastopen.c @@ -276,6 +276,7 @@ static struct sock *tcp_fastopen_create_child(struct sock *sk, static bool tcp_fastopen_queue_check(struct sock *sk) { struct fastopen_queue *fastopenq; + int max_qlen; /* Make sure the listener has enabled fastopen, and we don't * exceed the max # of pending TFO requests allowed before trying @@ -288,10 +289,11 @@ static bool tcp_fastopen_queue_check(struct sock *sk) * temporarily vs a server not supporting Fast Open at all. */ fastopenq = &inet_csk(sk)->icsk_accept_queue.fastopenq; - if (fastopenq->max_qlen == 0) + max_qlen = READ_ONCE(fastopenq->max_qlen); + if (max_qlen == 0) return false; - if (fastopenq->qlen >= fastopenq->max_qlen) { + if (fastopenq->qlen >= max_qlen) { struct request_sock *req1; spin_lock(&fastopenq->lock); req1 = fastopenq->rskq_rst_head; diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index b87fceef67f526dbd34bef0e911af7e4e7d16aeb..89a1ce4db7153a0f53c21c7fce24456ea9794793 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -177,6 +177,19 @@ static void tcp_measure_rcv_mss(struct sock *sk, const struct sk_buff *skb) if (unlikely(len > icsk->icsk_ack.rcv_mss + MAX_TCP_OPTION_SPACE)) tcp_gro_dev_warn(sk, skb, len); + /* If the skb has a len of exactly 1*MSS and has the PSH bit + * set then it is likely the end of an application write. So + * more data may not be arriving soon, and yet the data sender + * may be waiting for an ACK if cwnd-bound or using TX zero + * copy. So we set ICSK_ACK_PUSHED here so that + * tcp_cleanup_rbuf() will send an ACK immediately if the app + * reads all of the data and is not ping-pong. If len > MSS + * then this logic does not matter (and does not hurt) because + * tcp_cleanup_rbuf() will always ACK immediately if the app + * reads data and there is more than an MSS of unACKed data. + */ + if (TCP_SKB_CB(skb)->tcp_flags & TCPHDR_PSH) + icsk->icsk_ack.pending |= ICSK_ACK_PUSHED; } else { /* Otherwise, we make more careful check taking into account, * that SACKs block is variable. @@ -221,7 +234,7 @@ static void tcp_incr_quickack(struct sock *sk, unsigned int max_quickacks) icsk->icsk_ack.quick = quickacks; } -void tcp_enter_quickack_mode(struct sock *sk, unsigned int max_quickacks) +static void tcp_enter_quickack_mode(struct sock *sk, unsigned int max_quickacks) { struct inet_connection_sock *icsk = inet_csk(sk); @@ -229,7 +242,6 @@ void tcp_enter_quickack_mode(struct sock *sk, unsigned int max_quickacks) icsk->icsk_ack.pingpong = 0; icsk->icsk_ack.ato = TCP_ATO_MIN; } -EXPORT_SYMBOL(tcp_enter_quickack_mode); /* Send ACKs quickly, if "quick" count is not exhausted * and the session is not interactive. @@ -3444,8 +3456,11 @@ static int tcp_ack_update_window(struct sock *sk, const struct sk_buff *skb, u32 static bool __tcp_oow_rate_limited(struct net *net, int mib_idx, u32 *last_oow_ack_time) { - if (*last_oow_ack_time) { - s32 elapsed = (s32)(tcp_jiffies32 - *last_oow_ack_time); + /* Paired with the WRITE_ONCE() in this function. */ + u32 val = READ_ONCE(*last_oow_ack_time); + + if (val) { + s32 elapsed = (s32)(tcp_jiffies32 - val); if (0 <= elapsed && elapsed < READ_ONCE(net->ipv4.sysctl_tcp_invalid_ratelimit)) { @@ -3454,7 +3469,10 @@ static bool __tcp_oow_rate_limited(struct net *net, int mib_idx, } } - *last_oow_ack_time = tcp_jiffies32; + /* Paired with the prior READ_ONCE() and with itself, + * as we might be lockless. + */ + WRITE_ONCE(*last_oow_ack_time, tcp_jiffies32); return false; /* not rate-limited: go ahead, send dupack now! */ } diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c index 4960e2b6bd7f7247f1a8db977242149194790301..60619b1f4acdc9d9109dd40089b9a107adf88cb1 100644 --- a/net/ipv4/tcp_metrics.c +++ b/net/ipv4/tcp_metrics.c @@ -40,7 +40,7 @@ struct tcp_fastopen_metrics { struct tcp_metrics_block { struct tcp_metrics_block __rcu *tcpm_next; - possible_net_t tcpm_net; + struct net *tcpm_net; struct inetpeer_addr tcpm_saddr; struct inetpeer_addr tcpm_daddr; unsigned long tcpm_stamp; @@ -51,34 +51,38 @@ struct tcp_metrics_block { struct rcu_head rcu_head; }; -static inline struct net *tm_net(struct tcp_metrics_block *tm) +static inline struct net *tm_net(const struct tcp_metrics_block *tm) { - return read_pnet(&tm->tcpm_net); + /* Paired with the WRITE_ONCE() in tcpm_new() */ + return READ_ONCE(tm->tcpm_net); } static bool tcp_metric_locked(struct tcp_metrics_block *tm, enum tcp_metric_index idx) { - return tm->tcpm_lock & (1 << idx); + /* Paired with WRITE_ONCE() in tcpm_suck_dst() */ + return READ_ONCE(tm->tcpm_lock) & (1 << idx); } -static u32 tcp_metric_get(struct tcp_metrics_block *tm, +static u32 tcp_metric_get(const struct tcp_metrics_block *tm, enum tcp_metric_index idx) { - return tm->tcpm_vals[idx]; + /* Paired with WRITE_ONCE() in tcp_metric_set() */ + return READ_ONCE(tm->tcpm_vals[idx]); } static void tcp_metric_set(struct tcp_metrics_block *tm, enum tcp_metric_index idx, u32 val) { - tm->tcpm_vals[idx] = val; + /* Paired with READ_ONCE() in tcp_metric_get() */ + WRITE_ONCE(tm->tcpm_vals[idx], val); } static bool addr_same(const struct inetpeer_addr *a, const struct inetpeer_addr *b) { - return inetpeer_addr_cmp(a, b) == 0; + return (a->family == b->family) && !inetpeer_addr_cmp(a, b); } struct tcpm_hash_bucket { @@ -89,6 +93,7 @@ static struct tcpm_hash_bucket *tcp_metrics_hash __read_mostly; static unsigned int tcp_metrics_hash_log __read_mostly; static DEFINE_SPINLOCK(tcp_metrics_lock); +static DEFINE_SEQLOCK(fastopen_seqlock); static void tcpm_suck_dst(struct tcp_metrics_block *tm, const struct dst_entry *dst, @@ -97,7 +102,7 @@ static void tcpm_suck_dst(struct tcp_metrics_block *tm, u32 msval; u32 val; - tm->tcpm_stamp = jiffies; + WRITE_ONCE(tm->tcpm_stamp, jiffies); val = 0; if (dst_metric_locked(dst, RTAX_RTT)) @@ -110,30 +115,42 @@ static void tcpm_suck_dst(struct tcp_metrics_block *tm, val |= 1 << TCP_METRIC_CWND; if (dst_metric_locked(dst, RTAX_REORDERING)) val |= 1 << TCP_METRIC_REORDERING; - tm->tcpm_lock = val; + /* Paired with READ_ONCE() in tcp_metric_locked() */ + WRITE_ONCE(tm->tcpm_lock, val); msval = dst_metric_raw(dst, RTAX_RTT); - tm->tcpm_vals[TCP_METRIC_RTT] = msval * USEC_PER_MSEC; + tcp_metric_set(tm, TCP_METRIC_RTT, msval * USEC_PER_MSEC); msval = dst_metric_raw(dst, RTAX_RTTVAR); - tm->tcpm_vals[TCP_METRIC_RTTVAR] = msval * USEC_PER_MSEC; - tm->tcpm_vals[TCP_METRIC_SSTHRESH] = dst_metric_raw(dst, RTAX_SSTHRESH); - tm->tcpm_vals[TCP_METRIC_CWND] = dst_metric_raw(dst, RTAX_CWND); - tm->tcpm_vals[TCP_METRIC_REORDERING] = dst_metric_raw(dst, RTAX_REORDERING); + tcp_metric_set(tm, TCP_METRIC_RTTVAR, msval * USEC_PER_MSEC); + tcp_metric_set(tm, TCP_METRIC_SSTHRESH, + dst_metric_raw(dst, RTAX_SSTHRESH)); + tcp_metric_set(tm, TCP_METRIC_CWND, + dst_metric_raw(dst, RTAX_CWND)); + tcp_metric_set(tm, TCP_METRIC_REORDERING, + dst_metric_raw(dst, RTAX_REORDERING)); if (fastopen_clear) { + write_seqlock(&fastopen_seqlock); tm->tcpm_fastopen.mss = 0; tm->tcpm_fastopen.syn_loss = 0; tm->tcpm_fastopen.try_exp = 0; tm->tcpm_fastopen.cookie.exp = false; tm->tcpm_fastopen.cookie.len = 0; + write_sequnlock(&fastopen_seqlock); } } #define TCP_METRICS_TIMEOUT (60 * 60 * HZ) -static void tcpm_check_stamp(struct tcp_metrics_block *tm, struct dst_entry *dst) +static void tcpm_check_stamp(struct tcp_metrics_block *tm, + const struct dst_entry *dst) { - if (tm && unlikely(time_after(jiffies, tm->tcpm_stamp + TCP_METRICS_TIMEOUT))) + unsigned long limit; + + if (!tm) + return; + limit = READ_ONCE(tm->tcpm_stamp) + TCP_METRICS_TIMEOUT; + if (unlikely(time_after(jiffies, limit))) tcpm_suck_dst(tm, dst, false); } @@ -174,20 +191,23 @@ static struct tcp_metrics_block *tcpm_new(struct dst_entry *dst, oldest = deref_locked(tcp_metrics_hash[hash].chain); for (tm = deref_locked(oldest->tcpm_next); tm; tm = deref_locked(tm->tcpm_next)) { - if (time_before(tm->tcpm_stamp, oldest->tcpm_stamp)) + if (time_before(READ_ONCE(tm->tcpm_stamp), + READ_ONCE(oldest->tcpm_stamp))) oldest = tm; } tm = oldest; } else { - tm = kmalloc(sizeof(*tm), GFP_ATOMIC); + tm = kzalloc(sizeof(*tm), GFP_ATOMIC); if (!tm) goto out_unlock; } - write_pnet(&tm->tcpm_net, net); + /* Paired with the READ_ONCE() in tm_net() */ + WRITE_ONCE(tm->tcpm_net, net); + tm->tcpm_saddr = *saddr; tm->tcpm_daddr = *daddr; - tcpm_suck_dst(tm, dst, true); + tcpm_suck_dst(tm, dst, reclaim); if (likely(!reclaim)) { tm->tcpm_next = tcp_metrics_hash[hash].chain; @@ -431,7 +451,7 @@ void tcp_update_metrics(struct sock *sk) tp->reordering); } } - tm->tcpm_stamp = jiffies; + WRITE_ONCE(tm->tcpm_stamp, jiffies); out_unlock: rcu_read_unlock(); } @@ -446,11 +466,15 @@ void tcp_init_metrics(struct sock *sk) u32 val, crtt = 0; /* cached RTT scaled by 8 */ sk_dst_confirm(sk); + /* ssthresh may have been reduced unnecessarily during. + * 3WHS. Restore it back to its initial default. + */ + tp->snd_ssthresh = TCP_INFINITE_SSTHRESH; if (!dst) goto reset; rcu_read_lock(); - tm = tcp_get_metrics(sk, dst, true); + tm = tcp_get_metrics(sk, dst, false); if (!tm) { rcu_read_unlock(); goto reset; @@ -464,11 +488,6 @@ void tcp_init_metrics(struct sock *sk) tp->snd_ssthresh = val; if (tp->snd_ssthresh > tp->snd_cwnd_clamp) tp->snd_ssthresh = tp->snd_cwnd_clamp; - } else { - /* ssthresh may have been reduced unnecessarily during. - * 3WHS. Restore it back to its initial default. - */ - tp->snd_ssthresh = TCP_INFINITE_SSTHRESH; } val = tcp_metric_get(tm, TCP_METRIC_REORDERING); if (val && tp->reordering != val) @@ -544,8 +563,6 @@ bool tcp_peer_is_proven(struct request_sock *req, struct dst_entry *dst) return ret; } -static DEFINE_SEQLOCK(fastopen_seqlock); - void tcp_fastopen_cache_get(struct sock *sk, u16 *mss, struct tcp_fastopen_cookie *cookie) { @@ -652,7 +669,7 @@ static int tcp_metrics_fill_info(struct sk_buff *msg, } if (nla_put_msecs(msg, TCP_METRICS_ATTR_AGE, - jiffies - tm->tcpm_stamp, + jiffies - READ_ONCE(tm->tcpm_stamp), TCP_METRICS_ATTR_PAD) < 0) goto nla_put_failure; @@ -663,7 +680,7 @@ static int tcp_metrics_fill_info(struct sk_buff *msg, if (!nest) goto nla_put_failure; for (i = 0; i < TCP_METRIC_MAX_KERNEL + 1; i++) { - u32 val = tm->tcpm_vals[i]; + u32 val = tcp_metric_get(tm, i); if (!val) continue; @@ -895,7 +912,7 @@ static void tcp_metrics_flush_all(struct net *net) match = net ? net_eq(tm_net(tm), net) : !refcount_read(&tm_net(tm)->count); if (match) { - *pp = tm->tcpm_next; + rcu_assign_pointer(*pp, tm->tcpm_next); kfree_rcu(tm, rcu_head); } else { pp = &tm->tcpm_next; @@ -936,7 +953,7 @@ static int tcp_metrics_nl_cmd_del(struct sk_buff *skb, struct genl_info *info) if (addr_same(&tm->tcpm_daddr, &daddr) && (!src || addr_same(&tm->tcpm_saddr, &saddr)) && net_eq(tm_net(tm), net)) { - *pp = tm->tcpm_next; + rcu_assign_pointer(*pp, tm->tcpm_next); kfree_rcu(tm, rcu_head); found = true; } else { diff --git a/net/ipv4/tcp_minisocks.c b/net/ipv4/tcp_minisocks.c index 0fc238d79b03a71e15d5a5ebf02a0201474fca1b..bae0199a943bd1924587c482981aa6e39711b294 100644 --- a/net/ipv4/tcp_minisocks.c +++ b/net/ipv4/tcp_minisocks.c @@ -582,6 +582,9 @@ EXPORT_SYMBOL(tcp_create_openreq_child); * validation and inside tcp_v4_reqsk_send_ack(). Can we do better? * * We don't need to initialize tmp_opt.sack_ok as we don't use the results + * + * Note: If @fastopen is true, this can be called from process context. + * Otherwise, this is from BH context. */ struct sock *tcp_check_req(struct sock *sk, struct sk_buff *skb, @@ -734,7 +737,7 @@ struct sock *tcp_check_req(struct sock *sk, struct sk_buff *skb, &tcp_rsk(req)->last_oow_ack_time)) req->rsk_ops->send_ack(sk, skb, req); if (paws_reject) - __NET_INC_STATS(sock_net(sk), LINUX_MIB_PAWSESTABREJECTED); + NET_INC_STATS(sock_net(sk), LINUX_MIB_PAWSESTABREJECTED); return NULL; } @@ -753,7 +756,7 @@ struct sock *tcp_check_req(struct sock *sk, struct sk_buff *skb, * "fourth, check the SYN bit" */ if (flg & (TCP_FLAG_RST|TCP_FLAG_SYN)) { - __TCP_INC_STATS(sock_net(sk), TCP_MIB_ATTEMPTFAILS); + TCP_INC_STATS(sock_net(sk), TCP_MIB_ATTEMPTFAILS); goto embryonic_reset; } diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index e744c59388ba120d0fe218c58acdaf1b2b147a29..3db7f2bc79728c702aa3e18e9de2956c3a50aca0 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -176,8 +176,7 @@ static void tcp_event_data_sent(struct tcp_sock *tp, } /* Account for an ACK we sent. */ -static inline void tcp_event_ack_sent(struct sock *sk, unsigned int pkts, - u32 rcv_nxt) +static inline void tcp_event_ack_sent(struct sock *sk, u32 rcv_nxt) { struct tcp_sock *tp = tcp_sk(sk); @@ -191,7 +190,7 @@ static inline void tcp_event_ack_sent(struct sock *sk, unsigned int pkts, if (unlikely(rcv_nxt != tp->rcv_nxt)) return; /* Special ACK sent by DCTCP to reflect ECN */ - tcp_dec_quickack_mode(sk, pkts); + tcp_dec_quickack_mode(sk); inet_csk_clear_xmit_timer(sk, ICSK_TIME_DACK); } @@ -1103,7 +1102,7 @@ static int __tcp_transmit_skb(struct sock *sk, struct sk_buff *skb, skb_set_hash_from_sk(skb, sk); refcount_add(skb->truesize, &sk->sk_wmem_alloc); - skb_set_dst_pending_confirm(skb, sk->sk_dst_pending_confirm); + skb_set_dst_pending_confirm(skb, READ_ONCE(sk->sk_dst_pending_confirm)); /* Build TCP header and checksum it. */ th = (struct tcphdr *)skb->data; @@ -1151,7 +1150,7 @@ static int __tcp_transmit_skb(struct sock *sk, struct sk_buff *skb, icsk->icsk_af_ops->send_check(sk, skb); if (likely(tcb->tcp_flags & TCPHDR_ACK)) - tcp_event_ack_sent(sk, tcp_skb_pcount(skb), rcv_nxt); + tcp_event_ack_sent(sk, rcv_nxt); if (skb->len != tcp_header_size) { tcp_event_data_sent(tp, sk); @@ -2246,6 +2245,18 @@ static int tcp_mtu_probe(struct sock *sk) return -1; } +static bool tcp_rtx_queue_empty_or_single_skb(const struct sock *sk) +{ + const struct rb_node *node = sk->tcp_rtx_queue.rb_node; + + /* No skb in the rtx queue. */ + if (!node) + return true; + + /* Only one skb in rtx queue. */ + return !node->rb_left && !node->rb_right; +} + /* TCP Small Queues : * Control number of packets in qdisc/devices to two packets / or ~1 ms. * (These limits are doubled for retransmits) @@ -2268,12 +2279,12 @@ static bool tcp_small_queue_check(struct sock *sk, const struct sk_buff *skb, limit <<= factor; if (refcount_read(&sk->sk_wmem_alloc) > limit) { - /* Always send skb if rtx queue is empty. + /* Always send skb if rtx queue is empty or has one skb. * No need to wait for TX completion to call us back, * after softirq/tasklet schedule. * This helps when TX completions are delayed too much. */ - if (tcp_rtx_queue_empty(sk)) + if (tcp_rtx_queue_empty_or_single_skb(sk)) return false; set_bit(TSQ_THROTTLED, &sk->sk_tsq_flags); @@ -2475,7 +2486,7 @@ bool tcp_schedule_loss_probe(struct sock *sk, bool advancing_rto) { struct inet_connection_sock *icsk = inet_csk(sk); struct tcp_sock *tp = tcp_sk(sk); - u32 timeout, rto_delta_us; + u32 timeout, timeout_us, rto_delta_us; int early_retrans; /* Don't do any loss probe on a Fast Open connection before 3WHS @@ -2499,11 +2510,12 @@ bool tcp_schedule_loss_probe(struct sock *sk, bool advancing_rto) * sample is available then probe after TCP_TIMEOUT_INIT. */ if (tp->srtt_us) { - timeout = usecs_to_jiffies(tp->srtt_us >> 2); + timeout_us = tp->srtt_us >> 2; if (tp->packets_out == 1) - timeout += TCP_RTO_MIN; + timeout_us += tcp_rto_min_us(sk); else - timeout += TCP_TIMEOUT_MIN; + timeout_us += TCP_TIMEOUT_MIN_US; + timeout = usecs_to_jiffies(timeout_us); } else { timeout = TCP_TIMEOUT_INIT; } @@ -3341,7 +3353,7 @@ struct sk_buff *tcp_make_synack(const struct sock *sk, struct dst_entry *dst, th->window = htons(min(req->rsk_rcv_wnd, 65535U)); tcp_options_write((__be32 *)(th + 1), NULL, &opts); th->doff = (tcp_header_size >> 2); - __TCP_INC_STATS(sock_net(sk), TCP_MIB_OUTSEGS); + TCP_INC_STATS(sock_net(sk), TCP_MIB_OUTSEGS); #ifdef CONFIG_TCP_MD5SIG /* Okay, we have all we need - do the md5 hash if needed */ diff --git a/net/ipv4/tcp_recovery.c b/net/ipv4/tcp_recovery.c index 61969bb9395c71844703674e6382a3af559c5c1a..844ff390f7263ec061559d5ebd1396b59dae7fa6 100644 --- a/net/ipv4/tcp_recovery.c +++ b/net/ipv4/tcp_recovery.c @@ -122,7 +122,7 @@ bool tcp_rack_mark_lost(struct sock *sk) tp->rack.advanced = 0; tcp_rack_detect_loss(sk, &timeout); if (timeout) { - timeout = usecs_to_jiffies(timeout) + TCP_TIMEOUT_MIN; + timeout = usecs_to_jiffies(timeout + TCP_TIMEOUT_MIN_US); inet_csk_reset_xmit_timer(sk, ICSK_TIME_REO_TIMEOUT, timeout, inet_csk(sk)->icsk_rto); } diff --git a/net/ipv4/tcp_timer.c b/net/ipv4/tcp_timer.c index a8a1191f56e3baa6ad505c2e237a7f009b503dd0..15c6f54bd950a6cf0a1b8100c3f720b91cb7bc7f 100644 --- a/net/ipv4/tcp_timer.c +++ b/net/ipv4/tcp_timer.c @@ -596,7 +596,9 @@ void tcp_retransmit_timer(struct sock *sk) tcp_stream_is_thin(tp) && icsk->icsk_retransmits <= TCP_THIN_LINEAR_RETRIES) { icsk->icsk_backoff = 0; - icsk->icsk_rto = min(__tcp_set_rto(tp), TCP_RTO_MAX); + icsk->icsk_rto = clamp(__tcp_set_rto(tp), + tcp_rto_min(sk), + TCP_RTO_MAX); } else { /* Use normal (exponential) backoff */ icsk->icsk_rto = min(icsk->icsk_rto << 1, TCP_RTO_MAX); diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c index 0f3e86f6e1f932f5d33459d984abe10a340690b5..e12895ede7557d5e9f34e2e7fe6c710abd4bd2a5 100644 --- a/net/ipv4/udp.c +++ b/net/ipv4/udp.c @@ -1468,7 +1468,7 @@ int __udp_enqueue_schedule_skb(struct sock *sk, struct sk_buff *skb) } EXPORT_SYMBOL_GPL(__udp_enqueue_schedule_skb); -void udp_destruct_sock(struct sock *sk) +void udp_destruct_common(struct sock *sk) { /* reclaim completely the forward allocated memory */ struct udp_sock *up = udp_sk(sk); @@ -1481,10 +1481,14 @@ void udp_destruct_sock(struct sock *sk) kfree_skb(skb); } udp_rmem_release(sk, total, 0, true); +} +EXPORT_SYMBOL_GPL(udp_destruct_common); +static void udp_destruct_sock(struct sock *sk) +{ + udp_destruct_common(sk); inet_sock_destruct(sk); } -EXPORT_SYMBOL_GPL(udp_destruct_sock); int udp_init_sock(struct sock *sk) { @@ -1492,7 +1496,6 @@ int udp_init_sock(struct sock *sk) sk->sk_destruct = udp_destruct_sock; return 0; } -EXPORT_SYMBOL_GPL(udp_init_sock); void skb_consume_udp(struct sock *sk, struct sk_buff *skb, int len) { diff --git a/net/ipv4/udplite.c b/net/ipv4/udplite.c index 8545457752fb95e9239ff683efbdacfd08f8a004..27173549b0006d93ad2eb7b35d77b0b8b990e6ca 100644 --- a/net/ipv4/udplite.c +++ b/net/ipv4/udplite.c @@ -20,6 +20,14 @@ struct udp_table udplite_table __read_mostly; EXPORT_SYMBOL(udplite_table); +/* Designate sk as UDP-Lite socket */ +static int udplite_sk_init(struct sock *sk) +{ + udp_init_sock(sk); + udp_sk(sk)->pcflag = UDPLITE_BIT; + return 0; +} + static int udplite_rcv(struct sk_buff *skb) { return __udp4_lib_rcv(skb, &udplite_table, IPPROTO_UDPLITE); @@ -56,6 +64,8 @@ struct proto udplite_prot = { .get_port = udp_v4_get_port, .memory_allocated = &udp_memory_allocated, .sysctl_mem = sysctl_udp_mem, + .sysctl_wmem_offset = offsetof(struct net, ipv4.sysctl_udp_wmem_min), + .sysctl_rmem_offset = offsetof(struct net, ipv4.sysctl_udp_rmem_min), .obj_size = sizeof(struct udp_sock), .h.udp_table = &udplite_table, #ifdef CONFIG_COMPAT diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c index b7a2f1add7182186839c604493f33a995f532d98..792bc92c904a3e692cccc0fe207479c62342460a 100644 --- a/net/ipv6/addrconf.c +++ b/net/ipv6/addrconf.c @@ -318,9 +318,8 @@ static void addrconf_del_dad_work(struct inet6_ifaddr *ifp) static void addrconf_mod_rs_timer(struct inet6_dev *idev, unsigned long when) { - if (!timer_pending(&idev->rs_timer)) + if (!mod_timer(&idev->rs_timer, jiffies + when)) in6_dev_hold(idev); - mod_timer(&idev->rs_timer, jiffies + when); } static void addrconf_mod_dad_work(struct inet6_ifaddr *ifp, @@ -1324,7 +1323,7 @@ static int ipv6_create_tempaddr(struct inet6_ifaddr *ifp, * idev->desync_factor if it's larger */ cnf_temp_preferred_lft = READ_ONCE(idev->cnf.temp_prefered_lft); - max_desync_factor = min_t(__u32, + max_desync_factor = min_t(long, idev->cnf.max_desync_factor, cnf_temp_preferred_lft - regen_advance); @@ -2520,12 +2519,18 @@ static void manage_tempaddrs(struct inet6_dev *idev, ipv6_ifa_notify(0, ift); } - if ((create || list_empty(&idev->tempaddr_list)) && - idev->cnf.use_tempaddr > 0) { + /* Also create a temporary address if it's enabled but no temporary + * address currently exists. + * However, we get called with valid_lft == 0, prefered_lft == 0, create == false + * as part of cleanup (ie. deleting the mngtmpaddr). + * We don't want that to result in creating a new temporary ip address. + */ + if (list_empty(&idev->tempaddr_list) && (valid_lft || prefered_lft)) + create = true; + + if (create && idev->cnf.use_tempaddr > 0) { /* When a new public address is created as described * in [ADDRCONF], also create a new temporary address. - * Also create a temporary address if it's enabled but - * no temporary address currently exists. */ read_unlock_bh(&idev->lock); ipv6_create_tempaddr(ifp, NULL, false); diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c index c4594d92adf8f3c56aa01d6c35fbee5cffb96866..2776dc1346a0355223d680713f0b125dcd8c0a70 100644 --- a/net/ipv6/af_inet6.c +++ b/net/ipv6/af_inet6.c @@ -121,6 +121,13 @@ static __inline__ struct ipv6_pinfo *inet6_sk_generic(struct sock *sk) return (struct ipv6_pinfo *)(((u8 *)sk) + offset); } +void inet6_sock_destruct(struct sock *sk) +{ + inet6_cleanup_sock(sk); + inet_sock_destruct(sk); +} +EXPORT_SYMBOL_GPL(inet6_sock_destruct); + static int inet6_create(struct net *net, struct socket *sock, int protocol, int kern) { @@ -215,7 +222,7 @@ static int inet6_create(struct net *net, struct socket *sock, int protocol, inet->hdrincl = 1; } - sk->sk_destruct = inet_sock_destruct; + sk->sk_destruct = inet6_sock_destruct; sk->sk_family = PF_INET6; sk->sk_protocol = protocol; @@ -518,6 +525,12 @@ void inet6_destroy_sock(struct sock *sk) } EXPORT_SYMBOL_GPL(inet6_destroy_sock); +void inet6_cleanup_sock(struct sock *sk) +{ + inet6_destroy_sock(sk); +} +EXPORT_SYMBOL_GPL(inet6_cleanup_sock); + /* * This does both peername and sockname. */ diff --git a/net/ipv6/esp6.c b/net/ipv6/esp6.c index d847ffbe974519d943b6d8b19f39ce229c80188c..6529e46ad09147ab8300e2b9ec02cd68471903a4 100644 --- a/net/ipv6/esp6.c +++ b/net/ipv6/esp6.c @@ -517,7 +517,9 @@ static inline int esp_remove_trailer(struct sk_buff *skb) skb->csum = csum_block_sub(skb->csum, csumdiff, skb->len - trimlen); } - pskb_trim(skb, skb->len - trimlen); + ret = pskb_trim(skb, skb->len - trimlen); + if (unlikely(ret)) + return ret; ret = nexthdr[1]; diff --git a/net/ipv6/esp6_offload.c b/net/ipv6/esp6_offload.c index eeee64a8a72c2e8803562ebafd6c64f06829b183..69313ec24264ea2eec3fb87110251d4c48bcb594 100644 --- a/net/ipv6/esp6_offload.c +++ b/net/ipv6/esp6_offload.c @@ -272,6 +272,9 @@ static int esp6_xmit(struct xfrm_state *x, struct sk_buff *skb, netdev_features secpath_reset(skb); + if (skb_needs_linearize(skb, skb->dev->features) && + __skb_linearize(skb)) + return -ENOMEM; return 0; } diff --git a/net/ipv6/exthdrs_core.c b/net/ipv6/exthdrs_core.c index 1af240dcc50de4fc1bbb7fe8f8f0451f58b231bc..4590102deff3ce51fd5d3d8ac10b239eb5af8d1f 100644 --- a/net/ipv6/exthdrs_core.c +++ b/net/ipv6/exthdrs_core.c @@ -142,6 +142,8 @@ int ipv6_find_tlv(const struct sk_buff *skb, int offset, int type) optlen = 1; break; default: + if (len < 2) + goto bad; optlen = nh[offset + 1] + 2; if (optlen > len) goto bad; diff --git a/net/ipv6/icmp.c b/net/ipv6/icmp.c index fbc8746371b6dd043a2a34ca5fd8f2806825bb9e..bfafd7649ccb30fd7b9e85dbbd6d3100a2adb1b0 100644 --- a/net/ipv6/icmp.c +++ b/net/ipv6/icmp.c @@ -395,23 +395,31 @@ static struct dst_entry *icmpv6_route_lookup(struct net *net, return ERR_PTR(err); } -static int icmp6_iif(const struct sk_buff *skb) +static struct net_device *icmp6_dev(const struct sk_buff *skb) { - int iif = skb->dev->ifindex; + struct net_device *dev = skb->dev; /* for local traffic to local address, skb dev is the loopback * device. Check if there is a dst attached to the skb and if so * get the real device index. Same is needed for replies to a link * local address on a device enslaved to an L3 master device */ - if (unlikely(iif == LOOPBACK_IFINDEX || netif_is_l3_master(skb->dev))) { + if (unlikely(dev->ifindex == LOOPBACK_IFINDEX || netif_is_l3_master(skb->dev))) { const struct rt6_info *rt6 = skb_rt6_info(skb); - if (rt6) - iif = rt6->rt6i_idev->dev->ifindex; + /* The destination could be an external IP in Ext Hdr (SRv6, RPL, etc.), + * and ip6_null_entry could be set to skb if no route is found. + */ + if (rt6 && rt6->rt6i_idev) + dev = rt6->rt6i_idev->dev; } - return iif; + return dev; +} + +static int icmp6_iif(const struct sk_buff *skb) +{ + return icmp6_dev(skb)->ifindex; } /* @@ -800,7 +808,7 @@ void icmpv6_notify(struct sk_buff *skb, u8 type, u8 code, __be32 info) static int icmpv6_rcv(struct sk_buff *skb) { struct net *net = dev_net(skb->dev); - struct net_device *dev = skb->dev; + struct net_device *dev = icmp6_dev(skb); struct inet6_dev *idev = __in6_dev_get(dev); const struct in6_addr *saddr, *daddr; struct icmp6hdr *hdr; diff --git a/net/ipv6/ila/ila_xlat.c b/net/ipv6/ila/ila_xlat.c index 7858fa9ea103bc92c0c11adb8e6511721137e162..87744eb8d0c424ce12e8e1cf5a3f7321fa1f2e20 100644 --- a/net/ipv6/ila/ila_xlat.c +++ b/net/ipv6/ila/ila_xlat.c @@ -480,6 +480,7 @@ int ila_xlat_nl_cmd_get_mapping(struct sk_buff *skb, struct genl_info *info) rcu_read_lock(); + ret = -ESRCH; ila = ila_lookup_by_params(&xp, ilan); if (ila) { ret = ila_dump_info(ila, diff --git a/net/ipv6/ip6_flowlabel.c b/net/ipv6/ip6_flowlabel.c index f994f50e1516226c88101f901f71647514ad580b..1858cf783a4ff334fbe14355a811789af2dc1e32 100644 --- a/net/ipv6/ip6_flowlabel.c +++ b/net/ipv6/ip6_flowlabel.c @@ -518,7 +518,7 @@ int ipv6_flowlabel_opt_get(struct sock *sk, struct in6_flowlabel_req *freq, int ipv6_flowlabel_opt(struct sock *sk, char __user *optval, int optlen) { - int uninitialized_var(err); + int err; struct net *net = sock_net(sk); struct ipv6_pinfo *np = inet6_sk(sk); struct in6_flowlabel_req freq; diff --git a/net/ipv6/ip6_gre.c b/net/ipv6/ip6_gre.c index 00601bc4fdfa36de12d1faea748b027ee685a8e3..aa8ada354a399b9073a2a142a826da83f0ec1c4f 100644 --- a/net/ipv6/ip6_gre.c +++ b/net/ipv6/ip6_gre.c @@ -731,6 +731,7 @@ static netdev_tx_t __gre6_xmit(struct sk_buff *skb, { struct ip6_tnl *tunnel = netdev_priv(dev); __be16 protocol; + __be16 flags; if (dev->type == ARPHRD_ETHER) IPCB(skb)->flags = 0; @@ -740,16 +741,12 @@ static netdev_tx_t __gre6_xmit(struct sk_buff *skb, else fl6->daddr = tunnel->parms.raddr; - if (skb_cow_head(skb, dev->needed_headroom ?: tunnel->hlen)) - return -ENOMEM; - /* Push GRE header. */ protocol = (dev->type == ARPHRD_ETHER) ? htons(ETH_P_TEB) : proto; if (tunnel->parms.collect_md) { struct ip_tunnel_info *tun_info; const struct ip_tunnel_key *key; - __be16 flags; int tun_hlen; tun_info = skb_tunnel_info(skb); @@ -770,19 +767,25 @@ static netdev_tx_t __gre6_xmit(struct sk_buff *skb, (TUNNEL_CSUM | TUNNEL_KEY | TUNNEL_SEQ); tun_hlen = gre_calc_hlen(flags); + if (skb_cow_head(skb, dev->needed_headroom ?: tun_hlen + tunnel->encap_hlen)) + return -ENOMEM; + gre_build_header(skb, tun_hlen, flags, protocol, tunnel_id_to_key32(tun_info->key.tun_id), - (flags & TUNNEL_SEQ) ? htonl(tunnel->o_seqno++) + (flags & TUNNEL_SEQ) ? htonl(atomic_fetch_inc(&tunnel->o_seqno)) : 0); } else { - if (tunnel->parms.o_flags & TUNNEL_SEQ) - tunnel->o_seqno++; + if (skb_cow_head(skb, dev->needed_headroom ?: tunnel->hlen)) + return -ENOMEM; + + flags = tunnel->parms.o_flags; - gre_build_header(skb, tunnel->tun_hlen, tunnel->parms.o_flags, + gre_build_header(skb, tunnel->tun_hlen, flags, protocol, tunnel->parms.o_key, - htonl(tunnel->o_seqno)); + (flags & TUNNEL_SEQ) ? htonl(atomic_fetch_inc(&tunnel->o_seqno)) + : 0); } return ip6_tnl_xmit(skb, dev, dsfield, fl6, encap_limit, pmtu, @@ -957,11 +960,12 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb, goto tx_err; if (skb->len > dev->mtu + dev->hard_header_len) { - pskb_trim(skb, dev->mtu + dev->hard_header_len); + if (pskb_trim(skb, dev->mtu + dev->hard_header_len)) + goto tx_err; truncate = true; } - nhoff = skb_network_header(skb) - skb_mac_header(skb); + nhoff = skb_network_offset(skb); if (skb->protocol == htons(ETH_P_IP) && (ntohs(ip_hdr(skb)->tot_len) > skb->len - nhoff)) truncate = true; @@ -970,7 +974,7 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb, int thoff; if (skb_transport_header_was_set(skb)) - thoff = skb_transport_header(skb) - skb_mac_header(skb); + thoff = skb_transport_offset(skb); else thoff = nhoff + sizeof(struct ipv6hdr); if (ntohs(ipv6_hdr(skb)->payload_len) > skb->len - thoff) @@ -1018,12 +1022,14 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb, ntohl(tun_id), ntohl(md->u.index), truncate, false); + proto = htons(ETH_P_ERSPAN); } else if (md->version == 2) { erspan_build_header_v2(skb, ntohl(tun_id), md->u.md2.dir, get_hwid(&md->u.md2), truncate, false); + proto = htons(ETH_P_ERSPAN2); } else { goto tx_err; } @@ -1046,25 +1052,26 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb, break; } - if (t->parms.erspan_ver == 1) + if (t->parms.erspan_ver == 1) { erspan_build_header(skb, ntohl(t->parms.o_key), t->parms.index, truncate, false); - else if (t->parms.erspan_ver == 2) + proto = htons(ETH_P_ERSPAN); + } else if (t->parms.erspan_ver == 2) { erspan_build_header_v2(skb, ntohl(t->parms.o_key), t->parms.dir, t->parms.hwid, truncate, false); - else + proto = htons(ETH_P_ERSPAN2); + } else { goto tx_err; + } fl6.daddr = t->parms.raddr; } /* Push GRE header. */ - proto = (t->parms.erspan_ver == 1) ? htons(ETH_P_ERSPAN) - : htons(ETH_P_ERSPAN2); - gre_build_header(skb, 8, TUNNEL_SEQ, proto, 0, htonl(t->o_seqno++)); + gre_build_header(skb, 8, TUNNEL_SEQ, proto, 0, htonl(atomic_fetch_inc(&t->o_seqno))); /* TooBig packet may have updated dst->dev's mtu */ if (!t->parms.collect_md && dst && dst_mtu(dst) > dst->dev->mtu) diff --git a/net/ipv6/ip6_output.c b/net/ipv6/ip6_output.c index 70820d049b92a17df0e771aadbdc870a93482d27..0872df066a4e57596ba3748e09f8a5c8e86e362c 100644 --- a/net/ipv6/ip6_output.c +++ b/net/ipv6/ip6_output.c @@ -106,7 +106,7 @@ static int ip6_finish_output2(struct net *net, struct sock *sk, struct sk_buff * if (lwtunnel_xmit_redirect(dst->lwtstate)) { int res = lwtunnel_xmit(skb); - if (res < 0 || res == LWTUNNEL_XMIT_DONE) + if (res != LWTUNNEL_XMIT_CONTINUE) return res; } @@ -153,7 +153,13 @@ ip6_finish_output_gso_slowpath_drop(struct net *net, struct sock *sk, int err; skb_mark_not_on_list(segs); - err = ip6_fragment(net, sk, segs, ip6_finish_output2); + /* Last GSO segment can be smaller than gso_size (and MTU). + * Adding a fragment header would produce an "atomic fragment", + * which is considered harmful (RFC-8021). Avoid that. + */ + err = segs->len > mtu ? + ip6_fragment(net, sk, segs, ip6_finish_output2) : + ip6_finish_output2(net, sk, segs); if (err && ret == 0) ret = err; } @@ -1730,8 +1736,13 @@ struct sk_buff *__ip6_make_skb(struct sock *sk, IP6_UPD_PO_STATS(net, rt->rt6i_idev, IPSTATS_MIB_OUT, skb->len); if (proto == IPPROTO_ICMPV6) { struct inet6_dev *idev = ip6_dst_idev(skb_dst(skb)); + u8 icmp6_type; - ICMP6MSGOUT_INC_STATS(net, idev, icmp6_hdr(skb)->icmp6_type); + if (sk->sk_socket->type == SOCK_RAW && !inet_sk(sk)->hdrincl) + icmp6_type = fl6->fl6_icmp_type; + else + icmp6_type = icmp6_hdr(skb)->icmp6_type; + ICMP6MSGOUT_INC_STATS(net, idev, icmp6_type); ICMP6_INC_STATS(net, idev, ICMP6_MIB_OUTMSGS); } diff --git a/net/ipv6/ip6_tunnel.c b/net/ipv6/ip6_tunnel.c index 75a1ec2605fca6adc0a7f6630331d29b1b60d86a..48a658b541d75aab3d09de11d26fbde3ea4211ba 100644 --- a/net/ipv6/ip6_tunnel.c +++ b/net/ipv6/ip6_tunnel.c @@ -1206,8 +1206,8 @@ int ip6_tnl_xmit(struct sk_buff *skb, struct net_device *dev, __u8 dsfield, */ max_headroom = LL_RESERVED_SPACE(dst->dev) + sizeof(struct ipv6hdr) + dst->header_len + t->hlen; - if (max_headroom > dev->needed_headroom) - dev->needed_headroom = max_headroom; + if (max_headroom > READ_ONCE(dev->needed_headroom)) + WRITE_ONCE(dev->needed_headroom, max_headroom); err = ip6_tnl_encap(skb, t, &proto, fl6); if (err) diff --git a/net/ipv6/ip6_vti.c b/net/ipv6/ip6_vti.c index 866ce815625e553bd51b74ccd80155b7cd68c0a6..a64050e775882732e4a9c248521401fd9f506d4a 100644 --- a/net/ipv6/ip6_vti.c +++ b/net/ipv6/ip6_vti.c @@ -562,12 +562,12 @@ vti6_tnl_xmit(struct sk_buff *skb, struct net_device *dev) vti6_addr_conflict(t, ipv6_hdr(skb))) goto tx_err; - xfrm_decode_session(skb, &fl, AF_INET6); memset(IP6CB(skb), 0, sizeof(*IP6CB(skb))); + xfrm_decode_session(skb, &fl, AF_INET6); break; case htons(ETH_P_IP): - xfrm_decode_session(skb, &fl, AF_INET); memset(IPCB(skb), 0, sizeof(*IPCB(skb))); + xfrm_decode_session(skb, &fl, AF_INET); break; default: goto tx_err; diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index e9eb917342b85432597d8d524f451e7e117b6aab..329bad6cbb768cfb9d5e9e888214801c446a1528 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -1064,7 +1064,7 @@ static int ip6mr_cache_report(struct mr_table *mrt, struct sk_buff *pkt, And all this only to mangle msg->im6_msgtype and to set msg->im6_mbz to "mbz" :-) */ - skb_push(skb, -skb_network_offset(pkt)); + __skb_pull(skb, skb_network_offset(pkt)); skb_push(skb, sizeof(*msg)); skb_reset_transport_header(skb); diff --git a/net/ipv6/ipv6_sockglue.c b/net/ipv6/ipv6_sockglue.c index 4f958d24f9e4ab1d52654908cecf4805069ddc5b..1c155e610c06de6746e3ac879f62b4d49c9556d2 100644 --- a/net/ipv6/ipv6_sockglue.c +++ b/net/ipv6/ipv6_sockglue.c @@ -178,9 +178,6 @@ static int do_ipv6_setsockopt(struct sock *sk, int level, int optname, if (optlen < sizeof(int)) goto e_inval; if (val == PF_INET) { - struct ipv6_txoptions *opt; - struct sk_buff *pktopt; - if (sk->sk_type == SOCK_RAW) break; @@ -211,7 +208,6 @@ static int do_ipv6_setsockopt(struct sock *sk, int level, int optname, break; } - fl6_free_socklist(sk); __ipv6_sock_mc_close(sk); __ipv6_sock_ac_close(sk); @@ -246,14 +242,14 @@ static int do_ipv6_setsockopt(struct sock *sk, int level, int optname, sk->sk_socket->ops = &inet_dgram_ops; sk->sk_family = PF_INET; } - opt = xchg((__force struct ipv6_txoptions **)&np->opt, - NULL); - if (opt) { - atomic_sub(opt->tot_len, &sk->sk_omem_alloc); - txopt_put(opt); - } - pktopt = xchg(&np->pktoptions, NULL); - kfree_skb(pktopt); + + /* Disable all options not to allocate memory anymore, + * but there is still a race. See the lockless path + * in udpv6_sendmsg() and ipv6_local_rxpmtu(). + */ + np->rxopt.all = 0; + + inet6_cleanup_sock(sk); /* * ... and add it to the refcnt debug socks count diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c index 171c5273acdcc124111b414c42969f47c8af92c1..9bbbfb29b71b23325c003306d0ef7872ce05c0de 100644 --- a/net/ipv6/ndisc.c +++ b/net/ipv6/ndisc.c @@ -195,7 +195,8 @@ static struct nd_opt_hdr *ndisc_next_option(struct nd_opt_hdr *cur, static inline int ndisc_is_useropt(const struct net_device *dev, struct nd_opt_hdr *opt) { - return opt->nd_opt_type == ND_OPT_RDNSS || + return opt->nd_opt_type == ND_OPT_PREFIX_INFO || + opt->nd_opt_type == ND_OPT_RDNSS || opt->nd_opt_type == ND_OPT_DNSSL || opt->nd_opt_type == ND_OPT_CAPTIVE_PORTAL || opt->nd_opt_type == ND_OPT_PREF64 || diff --git a/net/ipv6/netfilter/nf_socket_ipv6.c b/net/ipv6/netfilter/nf_socket_ipv6.c index 58e839e2ce1d3e385093160515b90d36af8fcd56..5e5463459563ffa51e6a654a4eccb10152a3a7bd 100644 --- a/net/ipv6/netfilter/nf_socket_ipv6.c +++ b/net/ipv6/netfilter/nf_socket_ipv6.c @@ -102,7 +102,7 @@ nf_socket_get_sock_v6(struct net *net, struct sk_buff *skb, int doff, struct sock *nf_sk_lookup_slow_v6(struct net *net, const struct sk_buff *skb, const struct net_device *indev) { - __be16 uninitialized_var(dport), uninitialized_var(sport); + __be16 dport, sport; const struct in6_addr *daddr = NULL, *saddr = NULL; struct ipv6hdr *iph = ipv6_hdr(skb), ipv6_var; struct sk_buff *data_skb = NULL; diff --git a/net/ipv6/netfilter/nft_dup_ipv6.c b/net/ipv6/netfilter/nft_dup_ipv6.c index d8b5b60b7d5310d0bff6e16f9964b5a91c38a64f..d8bb7c85287cb69c5e19c2abb5a1baf1d9160784 100644 --- a/net/ipv6/netfilter/nft_dup_ipv6.c +++ b/net/ipv6/netfilter/nft_dup_ipv6.c @@ -16,8 +16,8 @@ #include struct nft_dup_ipv6 { - enum nft_registers sreg_addr:8; - enum nft_registers sreg_dev:8; + u8 sreg_addr; + u8 sreg_dev; }; static void nft_dup_ipv6_eval(const struct nft_expr *expr, @@ -41,16 +41,16 @@ static int nft_dup_ipv6_init(const struct nft_ctx *ctx, if (tb[NFTA_DUP_SREG_ADDR] == NULL) return -EINVAL; - priv->sreg_addr = nft_parse_register(tb[NFTA_DUP_SREG_ADDR]); - err = nft_validate_register_load(priv->sreg_addr, sizeof(struct in6_addr)); + err = nft_parse_register_load(tb[NFTA_DUP_SREG_ADDR], &priv->sreg_addr, + sizeof(struct in6_addr)); if (err < 0) return err; - if (tb[NFTA_DUP_SREG_DEV] != NULL) { - priv->sreg_dev = nft_parse_register(tb[NFTA_DUP_SREG_DEV]); - return nft_validate_register_load(priv->sreg_dev, sizeof(int)); - } - return 0; + if (tb[NFTA_DUP_SREG_DEV]) + err = nft_parse_register_load(tb[NFTA_DUP_SREG_DEV], + &priv->sreg_dev, sizeof(int)); + + return err; } static int nft_dup_ipv6_dump(struct sk_buff *skb, const struct nft_expr *expr) diff --git a/net/ipv6/ping.c b/net/ipv6/ping.c index 23ae01715e7b1346e1a0e405c78296aa0f85cf27..e065f49a4ae38f53c0b449105291ee4a34c0b077 100644 --- a/net/ipv6/ping.c +++ b/net/ipv6/ping.c @@ -27,11 +27,6 @@ #include #include -static void ping_v6_destroy(struct sock *sk) -{ - inet6_destroy_sock(sk); -} - /* Compatibility glue so we can support IPv6 when it's compiled as a module */ static int dummy_ipv6_recv_error(struct sock *sk, struct msghdr *msg, int len, int *addr_len) @@ -106,7 +101,8 @@ static int ping_v6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) addr_type = ipv6_addr_type(daddr); if ((__ipv6_addr_needs_scope_id(addr_type) && !oif) || (addr_type & IPV6_ADDR_MAPPED) || - (oif && sk->sk_bound_dev_if && oif != sk->sk_bound_dev_if)) + (oif && sk->sk_bound_dev_if && oif != sk->sk_bound_dev_if && + l3mdev_master_ifindex_by_index(sock_net(sk), oif) != sk->sk_bound_dev_if)) return -EINVAL; /* TODO: use ip6_datagram_send_ctl to get options from cmsg */ @@ -175,7 +171,6 @@ struct proto pingv6_prot = { .owner = THIS_MODULE, .init = ping_init_sock, .close = ping_close, - .destroy = ping_v6_destroy, .connect = ip6_datagram_connect_v6_only, .disconnect = __udp_disconnect, .setsockopt = ipv6_setsockopt, diff --git a/net/ipv6/raw.c b/net/ipv6/raw.c index 44e9a240d6070ffa0810820f14602d9ceb0aa77f..31aad22c59fc35f22e03ac35dd3c494cd45d16b0 100644 --- a/net/ipv6/raw.c +++ b/net/ipv6/raw.c @@ -832,7 +832,8 @@ static int rawv6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) if (!proto) proto = inet->inet_num; - else if (proto != inet->inet_num) + else if (proto != inet->inet_num && + inet->inet_num != IPPROTO_RAW) return -EINVAL; if (proto > 255) @@ -1259,8 +1260,6 @@ static void raw6_destroy(struct sock *sk) lock_sock(sk); ip6_flush_pending_frames(sk); release_sock(sk); - - inet6_destroy_sock(sk); } static int rawv6_init_sk(struct sock *sk) diff --git a/net/ipv6/reassembly.c b/net/ipv6/reassembly.c index 60dfd0d11851213fe5d2e50f7d9afed8d99a42f5..b596727f049785e16a8f1613f8e6a15750dca557 100644 --- a/net/ipv6/reassembly.c +++ b/net/ipv6/reassembly.c @@ -302,7 +302,7 @@ static int ip6_frag_reasm(struct frag_queue *fq, struct sk_buff *skb, skb_network_header_len(skb)); rcu_read_lock(); - __IP6_INC_STATS(net, __in6_dev_get(dev), IPSTATS_MIB_REASMOKS); + __IP6_INC_STATS(net, __in6_dev_stats_get(dev, skb), IPSTATS_MIB_REASMOKS); rcu_read_unlock(); fq->q.fragments = NULL; fq->q.rb_fragments = RB_ROOT; @@ -317,7 +317,7 @@ static int ip6_frag_reasm(struct frag_queue *fq, struct sk_buff *skb, net_dbg_ratelimited("ip6_frag_reasm: no memory for reassembly\n"); out_fail: rcu_read_lock(); - __IP6_INC_STATS(net, __in6_dev_get(dev), IPSTATS_MIB_REASMFAILS); + __IP6_INC_STATS(net, __in6_dev_stats_get(dev, skb), IPSTATS_MIB_REASMFAILS); rcu_read_unlock(); inet_frag_kill(&fq->q); return -1; diff --git a/net/ipv6/sit.c b/net/ipv6/sit.c index df734fe64d10afb6877ee27fe5aba5d73b079169..ec1de1e6b8e3c056bd3d6c53def3b5fd78a2c80b 100644 --- a/net/ipv6/sit.c +++ b/net/ipv6/sit.c @@ -1053,12 +1053,13 @@ static netdev_tx_t sit_tunnel_xmit(struct sk_buff *skb, static void ipip6_tunnel_bind_dev(struct net_device *dev) { + struct ip_tunnel *tunnel = netdev_priv(dev); + int t_hlen = tunnel->hlen + sizeof(struct iphdr); struct net_device *tdev = NULL; - struct ip_tunnel *tunnel; + int hlen = LL_MAX_HEADER; const struct iphdr *iph; struct flowi4 fl4; - tunnel = netdev_priv(dev); iph = &tunnel->parms.iph; if (iph->daddr) { @@ -1081,14 +1082,15 @@ static void ipip6_tunnel_bind_dev(struct net_device *dev) tdev = __dev_get_by_index(tunnel->net, tunnel->parms.link); if (tdev && !netif_is_l3_master(tdev)) { - int t_hlen = tunnel->hlen + sizeof(struct iphdr); int mtu; mtu = tdev->mtu - t_hlen; if (mtu < IPV6_MIN_MTU) mtu = IPV6_MIN_MTU; WRITE_ONCE(dev->mtu, mtu); + hlen = tdev->hard_header_len + tdev->needed_headroom; } + dev->needed_headroom = t_hlen + hlen; } static void ipip6_tunnel_update(struct ip_tunnel *t, struct ip_tunnel_parm *p, diff --git a/net/ipv6/syncookies.c b/net/ipv6/syncookies.c index ca291e342900c7fa4f1d108334a2734953b0bb10..ab073ac3d7ace67f39cc21e39b40be1ce3af725f 100644 --- a/net/ipv6/syncookies.c +++ b/net/ipv6/syncookies.c @@ -184,14 +184,15 @@ struct sock *cookie_v6_check(struct sock *sk, struct sk_buff *skb) treq->af_specific = &tcp_request_sock_ipv6_ops; treq->tfo_listener = false; - if (security_inet_conn_request(sk, skb, req)) - goto out_free; - req->mss = mss; ireq->ir_rmt_port = th->source; ireq->ir_num = ntohs(th->dest); ireq->ir_v6_rmt_addr = ipv6_hdr(skb)->saddr; ireq->ir_v6_loc_addr = ipv6_hdr(skb)->daddr; + + if (security_inet_conn_request(sk, skb, req)) + goto out_free; + if (ipv6_opt_accepted(sk, skb, &TCP_SKB_CB(skb)->header.h6) || np->rxopt.bits.rxinfo || np->rxopt.bits.rxoinfo || np->rxopt.bits.rxhlim || np->rxopt.bits.rxohlim) { diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c index dd5ceb3cb779ba443dbfde166dca64d9076dec85..7cab29cab50ff23a683b6429610a2b2969996a31 100644 --- a/net/ipv6/tcp_ipv6.c +++ b/net/ipv6/tcp_ipv6.c @@ -1807,12 +1807,6 @@ static int tcp_v6_init_sock(struct sock *sk) return 0; } -static void tcp_v6_destroy_sock(struct sock *sk) -{ - tcp_v4_destroy_sock(sk); - inet6_destroy_sock(sk); -} - #ifdef CONFIG_PROC_FS /* Proc filesystem TCPv6 sock list dumping. */ static void get_openreq6(struct seq_file *seq, @@ -2009,7 +2003,7 @@ struct proto tcpv6_prot = { .accept = inet_csk_accept, .ioctl = tcp_ioctl, .init = tcp_v6_init_sock, - .destroy = tcp_v6_destroy_sock, + .destroy = tcp_v4_destroy_sock, .shutdown = tcp_shutdown, .setsockopt = tcp_setsockopt, .getsockopt = tcp_getsockopt, diff --git a/net/ipv6/udp.c b/net/ipv6/udp.c index eb306282a221fc559aef13da1796c1622ed932d2..909c0d74d8cd7687cea11710f7bfd76ec5139203 100644 --- a/net/ipv6/udp.c +++ b/net/ipv6/udp.c @@ -67,6 +67,19 @@ static bool udp6_lib_exact_dif_match(struct net *net, struct sk_buff *skb) return false; } +static void udpv6_destruct_sock(struct sock *sk) +{ + udp_destruct_common(sk); + inet6_sock_destruct(sk); +} + +int udpv6_init_sock(struct sock *sk) +{ + skb_queue_head_init(&udp_sk(sk)->reader_queue); + sk->sk_destruct = udpv6_destruct_sock; + return 0; +} + static u32 udp6_ehashfn(const struct net *net, const struct in6_addr *laddr, const u16 lport, @@ -87,7 +100,7 @@ static u32 udp6_ehashfn(const struct net *net, fhash = __ipv6_addr_jhash(faddr, udp_ipv6_hash_secret); return __inet6_ehashfn(lhash, lport, fhash, fport, - udp_ipv6_hash_secret + net_hash_mix(net)); + udp6_ehash_secret + net_hash_mix(net)); } int udp_v6_get_port(struct sock *sk, unsigned short snum) @@ -1247,9 +1260,11 @@ int udpv6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) msg->msg_name = &sin; msg->msg_namelen = sizeof(sin); do_udp_sendmsg: - if (__ipv6_only_sock(sk)) - return -ENETUNREACH; - return udp_sendmsg(sk, msg, len); + err = __ipv6_only_sock(sk) ? + -ENETUNREACH : udp_sendmsg(sk, msg, len); + msg->msg_name = sin6; + msg->msg_namelen = addr_len; + return err; } } @@ -1520,8 +1535,6 @@ void udpv6_destroy_sock(struct sock *sk) if (up->encap_enabled) static_branch_dec(&udpv6_encap_needed_key); } - - inet6_destroy_sock(sk); } /* @@ -1630,7 +1643,7 @@ struct proto udpv6_prot = { .connect = ip6_datagram_connect, .disconnect = udp_disconnect, .ioctl = udp_ioctl, - .init = udp_init_sock, + .init = udpv6_init_sock, .destroy = udpv6_destroy_sock, .setsockopt = udpv6_setsockopt, .getsockopt = udpv6_getsockopt, diff --git a/net/ipv6/udp_impl.h b/net/ipv6/udp_impl.h index 7903e21c178b94f1a58faf4362609908b64e5fa3..e5d067b09ccfae013f3f71bc501655daa6f631e5 100644 --- a/net/ipv6/udp_impl.h +++ b/net/ipv6/udp_impl.h @@ -12,6 +12,7 @@ int __udp6_lib_rcv(struct sk_buff *, struct udp_table *, int); void __udp6_lib_err(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32, struct udp_table *); +int udpv6_init_sock(struct sock *sk); int udp_v6_get_port(struct sock *sk, unsigned short snum); int udpv6_getsockopt(struct sock *sk, int level, int optname, diff --git a/net/ipv6/udplite.c b/net/ipv6/udplite.c index 5000ad6878e6f7b8bfa3d4823f38ca8a9b0e7043..a26a4b5da09c39d6b9de3a7bcfa0420d83da7da2 100644 --- a/net/ipv6/udplite.c +++ b/net/ipv6/udplite.c @@ -15,6 +15,13 @@ #include #include "udp_impl.h" +static int udplitev6_sk_init(struct sock *sk) +{ + udpv6_init_sock(sk); + udp_sk(sk)->pcflag = UDPLITE_BIT; + return 0; +} + static int udplitev6_rcv(struct sk_buff *skb) { return __udp6_lib_rcv(skb, &udplite_table, IPPROTO_UDPLITE); @@ -40,7 +47,7 @@ struct proto udplitev6_prot = { .connect = ip6_datagram_connect, .disconnect = udp_disconnect, .ioctl = udp_ioctl, - .init = udplite_sk_init, + .init = udplitev6_sk_init, .destroy = udpv6_destroy_sock, .setsockopt = udpv6_setsockopt, .getsockopt = udpv6_getsockopt, @@ -51,6 +58,8 @@ struct proto udplitev6_prot = { .get_port = udp_v6_get_port, .memory_allocated = &udp_memory_allocated, .sysctl_mem = sysctl_udp_mem, + .sysctl_wmem_offset = offsetof(struct net, ipv4.sysctl_udp_wmem_min), + .sysctl_rmem_offset = offsetof(struct net, ipv4.sysctl_udp_rmem_min), .obj_size = sizeof(struct udp6_sock), .h.udp_table = &udplite_table, #ifdef CONFIG_COMPAT diff --git a/net/ipv6/xfrm6_policy.c b/net/ipv6/xfrm6_policy.c index 1925fb91e514a27ae81ee421bdb4475e8dc16f77..a1dfe4f5ed3a482ed8f4b31ba4433459075b5a7d 100644 --- a/net/ipv6/xfrm6_policy.c +++ b/net/ipv6/xfrm6_policy.c @@ -243,11 +243,11 @@ static void xfrm6_dst_destroy(struct dst_entry *dst) { struct xfrm_dst *xdst = (struct xfrm_dst *)dst; - if (likely(xdst->u.rt6.rt6i_idev)) - in6_dev_put(xdst->u.rt6.rt6i_idev); dst_destroy_metrics_generic(dst); if (xdst->u.rt6.rt6i_uncached_list) rt6_uncached_list_del(&xdst->u.rt6); + if (likely(xdst->u.rt6.rt6i_idev)) + in6_dev_put(xdst->u.rt6.rt6i_idev); xfrm_dst_destroy(xdst); } diff --git a/net/iucv/iucv.c b/net/iucv/iucv.c index eb502c6290c2ad1668897aedef08e1fc92e299e9..aacaa5119b456308c45ff8242884535f28341ea0 100644 --- a/net/iucv/iucv.c +++ b/net/iucv/iucv.c @@ -119,7 +119,7 @@ struct iucv_irq_data { u16 ippathid; u8 ipflags1; u8 iptype; - u32 res2[8]; + u32 res2[9]; }; struct iucv_irq_list { diff --git a/net/kcm/kcmsock.c b/net/kcm/kcmsock.c index 319d55c096b1b77f99096dd43e450e46c12938b6..cf798d80a12d06a417e9f1e1571484a0bc1f3201 100644 --- a/net/kcm/kcmsock.c +++ b/net/kcm/kcmsock.c @@ -1069,15 +1069,18 @@ static int kcm_sendmsg(struct socket *sock, struct msghdr *msg, size_t len) out_error: kcm_push(kcm); - if (copied && sock->type == SOCK_SEQPACKET) { + if (sock->type == SOCK_SEQPACKET) { /* Wrote some bytes before encountering an * error, return partial success. */ - goto partial_message; - } - - if (head != kcm->seq_skb) + if (copied) + goto partial_message; + if (head != kcm->seq_skb) + kfree_skb(head); + } else { kfree_skb(head); + kcm->seq_skb = NULL; + } err = sk_stream_error(sk, msg->msg_flags, err); @@ -1987,6 +1990,8 @@ static __net_exit void kcm_exit_net(struct net *net) * that all multiplexors and psocks have been destroyed. */ WARN_ON(!list_empty(&knet->mux_list)); + + mutex_destroy(&knet->mutex); } static struct pernet_operations kcm_net_ops = { diff --git a/net/key/af_key.c b/net/key/af_key.c index 976b67089ac15185c89f26ec20454906fbf44cbd..47ffa69ca6f67d56e175f3e102d3073d6182cdcc 100644 --- a/net/key/af_key.c +++ b/net/key/af_key.c @@ -1858,9 +1858,9 @@ static int pfkey_dump(struct sock *sk, struct sk_buff *skb, const struct sadb_ms if (ext_hdrs[SADB_X_EXT_FILTER - 1]) { struct sadb_x_filter *xfilter = ext_hdrs[SADB_X_EXT_FILTER - 1]; - if ((xfilter->sadb_x_filter_splen >= + if ((xfilter->sadb_x_filter_splen > (sizeof(xfrm_address_t) << 3)) || - (xfilter->sadb_x_filter_dplen >= + (xfilter->sadb_x_filter_dplen > (sizeof(xfrm_address_t) << 3))) { mutex_unlock(&pfk->dump_lock); return -EINVAL; @@ -1950,7 +1950,8 @@ static u32 gen_reqid(struct net *net) } static int -parse_ipsecrequest(struct xfrm_policy *xp, struct sadb_x_ipsecrequest *rq) +parse_ipsecrequest(struct xfrm_policy *xp, struct sadb_x_policy *pol, + struct sadb_x_ipsecrequest *rq) { struct net *net = xp_net(xp); struct xfrm_tmpl *t = xp->xfrm_vec + xp->xfrm_nr; @@ -1968,9 +1969,12 @@ parse_ipsecrequest(struct xfrm_policy *xp, struct sadb_x_ipsecrequest *rq) if ((mode = pfkey_mode_to_xfrm(rq->sadb_x_ipsecrequest_mode)) < 0) return -EINVAL; t->mode = mode; - if (rq->sadb_x_ipsecrequest_level == IPSEC_LEVEL_USE) + if (rq->sadb_x_ipsecrequest_level == IPSEC_LEVEL_USE) { + if ((mode == XFRM_MODE_TUNNEL || mode == XFRM_MODE_BEET) && + pol->sadb_x_policy_dir == IPSEC_DIR_OUTBOUND) + return -EINVAL; t->optional = 1; - else if (rq->sadb_x_ipsecrequest_level == IPSEC_LEVEL_UNIQUE) { + } else if (rq->sadb_x_ipsecrequest_level == IPSEC_LEVEL_UNIQUE) { t->reqid = rq->sadb_x_ipsecrequest_reqid; if (t->reqid > IPSEC_MANUAL_REQID_MAX) t->reqid = 0; @@ -2012,7 +2016,7 @@ parse_ipsecrequests(struct xfrm_policy *xp, struct sadb_x_policy *pol) rq->sadb_x_ipsecrequest_len < sizeof(*rq)) return -EINVAL; - if ((err = parse_ipsecrequest(xp, rq)) < 0) + if ((err = parse_ipsecrequest(xp, pol, rq)) < 0) return err; len -= rq->sadb_x_ipsecrequest_len; rq = (void*)((u8*)rq + rq->sadb_x_ipsecrequest_len); diff --git a/net/l2tp/l2tp_ip6.c b/net/l2tp/l2tp_ip6.c index 9dae10d8880cf8ec674c67cb62367ac902ee7906..7342344d99a9707bbea694d9b7a943769951d93e 100644 --- a/net/l2tp/l2tp_ip6.c +++ b/net/l2tp/l2tp_ip6.c @@ -272,8 +272,6 @@ static void l2tp_ip6_destroy_sock(struct sock *sk) if (tunnel) l2tp_tunnel_delete(tunnel); - - inet6_destroy_sock(sk); } static int l2tp_ip6_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len) @@ -527,7 +525,6 @@ static int l2tp_ip6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) */ if (len > INT_MAX - transhdrlen) return -EMSGSIZE; - ulen = len + transhdrlen; /* Mirror BSD error message compatibility */ if (msg->msg_flags & MSG_OOB) @@ -651,6 +648,7 @@ static int l2tp_ip6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) back_from_confirm: lock_sock(sk); + ulen = len + skb_queue_empty(&sk->sk_write_queue) ? transhdrlen : 0; err = ip6_append_data(sk, ip_generic_getfrag, msg, ulen, transhdrlen, &ipc6, &fl6, (struct rt6_info *)dst, diff --git a/net/llc/llc_input.c b/net/llc/llc_input.c index 82cb93f66b9bdd103b6900a5d1177751c5a01bc8..f4fb309185ced3eff04d6ac0b07ca21d4a41c5ad 100644 --- a/net/llc/llc_input.c +++ b/net/llc/llc_input.c @@ -127,8 +127,14 @@ static inline int llc_fixup_skb(struct sk_buff *skb) skb->transport_header += llc_len; skb_pull(skb, llc_len); if (skb->protocol == htons(ETH_P_802_2)) { - __be16 pdulen = eth_hdr(skb)->h_proto; - s32 data_size = ntohs(pdulen) - llc_len; + __be16 pdulen; + s32 data_size; + + if (skb->mac_len < ETH_HLEN) + return 0; + + pdulen = eth_hdr(skb)->h_proto; + data_size = ntohs(pdulen) - llc_len; if (data_size < 0 || !pskb_may_pull(skb, data_size)) @@ -162,9 +168,6 @@ int llc_rcv(struct sk_buff *skb, struct net_device *dev, void (*sta_handler)(struct sk_buff *skb); void (*sap_handler)(struct llc_sap *sap, struct sk_buff *skb); - if (!net_eq(dev_net(dev), &init_net)) - goto drop; - /* * When the interface is in promisc. mode, drop all the crap that it * receives, do not try to analyse it. diff --git a/net/llc/llc_s_ac.c b/net/llc/llc_s_ac.c index 9fa3342c7a829fec6ee374d2ee432d4cf25a1822..df26557a02448eec1a51447565f4859ef29608e3 100644 --- a/net/llc/llc_s_ac.c +++ b/net/llc/llc_s_ac.c @@ -153,6 +153,9 @@ int llc_sap_action_send_test_r(struct llc_sap *sap, struct sk_buff *skb) int rc = 1; u32 data_size; + if (skb->mac_len < ETH_HLEN) + return 1; + llc_pdu_decode_sa(skb, mac_da); llc_pdu_decode_da(skb, mac_sa); llc_pdu_decode_ssap(skb, &dsap); diff --git a/net/llc/llc_station.c b/net/llc/llc_station.c index c29170e767a8ca3964c8958cc99db5893302b4f1..64e2c67e16ba39a343c9a5dd42e92db2e79906c5 100644 --- a/net/llc/llc_station.c +++ b/net/llc/llc_station.c @@ -77,6 +77,9 @@ static int llc_station_ac_send_test_r(struct sk_buff *skb) u32 data_size; struct sk_buff *nskb; + if (skb->mac_len < ETH_HLEN) + goto out; + /* The test request command is type U (llc_len = 3) */ data_size = ntohs(eth_hdr(skb)->h_proto) - 3; nskb = llc_alloc_frame(NULL, skb->dev, LLC_PDU_TYPE_U, data_size); diff --git a/net/mac80211/cfg.c b/net/mac80211/cfg.c index 5659af1bec17943250f2e47b4a91f18e33790b84..77d8ed184c1c420e5b82694c67e93ed570d49337 100644 --- a/net/mac80211/cfg.c +++ b/net/mac80211/cfg.c @@ -2452,6 +2452,10 @@ static int ieee80211_get_tx_power(struct wiphy *wiphy, else *dbm = sdata->vif.bss_conf.txpower; + /* INT_MIN indicates no power level was set yet */ + if (*dbm == INT_MIN) + return -EINVAL; + return 0; } diff --git a/net/mac80211/sta_info.c b/net/mac80211/sta_info.c index 3a907ba7f76348bb06c5329ce791a240765760e7..5c209f72de70149c285173b286c63b1a3de27380 100644 --- a/net/mac80211/sta_info.c +++ b/net/mac80211/sta_info.c @@ -969,7 +969,8 @@ static int __must_check __sta_info_destroy_part1(struct sta_info *sta) list_del_rcu(&sta->list); sta->removed = true; - drv_sta_pre_rcu_remove(local, sta->sdata, sta); + if (sta->uploaded) + drv_sta_pre_rcu_remove(local, sta->sdata, sta); if (sdata->vif.type == NL80211_IFTYPE_AP_VLAN && rcu_access_pointer(sdata->u.vlan.sta) == sta) @@ -2047,7 +2048,7 @@ static void sta_stats_decode_rate(struct ieee80211_local *local, u32 rate, static int sta_set_rate_info_rx(struct sta_info *sta, struct rate_info *rinfo) { - u16 rate = READ_ONCE(sta_get_last_rx_stats(sta)->last_rate); + u32 rate = READ_ONCE(sta_get_last_rx_stats(sta)->last_rate); if (rate == STA_STATS_RATE_INVALID) return -EINVAL; diff --git a/net/mac80211/tx.c b/net/mac80211/tx.c index 3de260b0df7164b76b5a640ae7966153bfd49fe0..89f6b64cac21c5de60df9ec12192b77e01c08a49 100644 --- a/net/mac80211/tx.c +++ b/net/mac80211/tx.c @@ -655,7 +655,8 @@ ieee80211_tx_h_select_key(struct ieee80211_tx_data *tx) } if (unlikely(tx->key && tx->key->flags & KEY_FLAG_TAINTED && - !ieee80211_is_deauth(hdr->frame_control))) + !ieee80211_is_deauth(hdr->frame_control)) && + tx->skb->protocol != tx->sdata->control_port_protocol) return TX_DROP; if (!skip_hw && tx->key && diff --git a/net/netfilter/core.c b/net/netfilter/core.c index 722d1b057f616111bd756ab4b5901ff85e7b0913..0c6540780cb4c89b3b1c0197e1f337dad2c8e451 100644 --- a/net/netfilter/core.c +++ b/net/netfilter/core.c @@ -289,12 +289,6 @@ nf_hook_entry_head(struct net *net, int pf, unsigned int hooknum, if (WARN_ON_ONCE(ARRAY_SIZE(net->nf.hooks_ipv6) <= hooknum)) return NULL; return net->nf.hooks_ipv6 + hooknum; -#if IS_ENABLED(CONFIG_DECNET) - case NFPROTO_DECNET: - if (WARN_ON_ONCE(ARRAY_SIZE(net->nf.hooks_decnet) <= hooknum)) - return NULL; - return net->nf.hooks_decnet + hooknum; -#endif default: WARN_ON_ONCE(1); return NULL; @@ -646,10 +640,6 @@ static int __net_init netfilter_net_init(struct net *net) #ifdef CONFIG_NETFILTER_FAMILY_BRIDGE __netfilter_net_init(net->nf.hooks_bridge, ARRAY_SIZE(net->nf.hooks_bridge)); #endif -#if IS_ENABLED(CONFIG_DECNET) - __netfilter_net_init(net->nf.hooks_decnet, ARRAY_SIZE(net->nf.hooks_decnet)); -#endif - #ifdef CONFIG_PROC_FS net->nf.proc_netfilter = proc_net_mkdir(net, "netfilter", net->proc_net); diff --git a/net/netfilter/ipset/ip_set_core.c b/net/netfilter/ipset/ip_set_core.c index 0427e66bc47865170ae9c2b09dfc7e0cb990da5f..31756d1bf83e7485e0d612a57d8bb59e9d0d8e02 100644 --- a/net/netfilter/ipset/ip_set_core.c +++ b/net/netfilter/ipset/ip_set_core.c @@ -791,20 +791,9 @@ static struct nlmsghdr * start_msg(struct sk_buff *skb, u32 portid, u32 seq, unsigned int flags, enum ipset_cmd cmd) { - struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; - - nlh = nlmsg_put(skb, portid, seq, nfnl_msg_type(NFNL_SUBSYS_IPSET, cmd), - sizeof(*nfmsg), flags); - if (!nlh) - return NULL; - - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = NFPROTO_IPV4; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - - return nlh; + return nfnl_msg_put(skb, portid, seq, + nfnl_msg_type(NFNL_SUBSYS_IPSET, cmd), flags, + NFPROTO_IPV4, NFNETLINK_V0, 0); } /* Create a set */ diff --git a/net/netfilter/ipset/ip_set_hash_netportnet.c b/net/netfilter/ipset/ip_set_hash_netportnet.c index 613e18e720a44777754428666b9f021de952de9a..9290a4d7b862a3194c0f279b191880aab88b210e 100644 --- a/net/netfilter/ipset/ip_set_hash_netportnet.c +++ b/net/netfilter/ipset/ip_set_hash_netportnet.c @@ -39,6 +39,7 @@ MODULE_ALIAS("ip_set_hash:net,port,net"); #define IP_SET_HASH_WITH_PROTO #define IP_SET_HASH_WITH_NETS #define IPSET_NET_COUNT 2 +#define IP_SET_HASH_WITH_NET0 /* IPv4 variant */ diff --git a/net/netfilter/ipvs/ip_vs_ctl.c b/net/netfilter/ipvs/ip_vs_ctl.c index 3bf8d7f3cdc329e08cc4ef5a770e1445dc140ef3..0909f32eabfd13aef6ed14cd5ebf0c594b768444 100644 --- a/net/netfilter/ipvs/ip_vs_ctl.c +++ b/net/netfilter/ipvs/ip_vs_ctl.c @@ -1656,6 +1656,7 @@ static int ip_vs_zero_all(struct netns_ipvs *ipvs) #ifdef CONFIG_SYSCTL static int zero; +static int one = 1; static int three = 3; static int @@ -1667,12 +1668,18 @@ proc_do_defense_mode(struct ctl_table *table, int write, int val = *valp; int rc; - rc = proc_dointvec(table, write, buffer, lenp, ppos); + struct ctl_table tmp = { + .data = &val, + .maxlen = sizeof(int), + .mode = table->mode, + }; + + rc = proc_dointvec(&tmp, write, buffer, lenp, ppos); if (write && (*valp != val)) { - if ((*valp < 0) || (*valp > 3)) { - /* Restore the correct value */ - *valp = val; + if (val < 0 || val > 3) { + rc = -EINVAL; } else { + *valp = val; update_defense_level(ipvs); } } @@ -1683,37 +1690,27 @@ static int proc_do_sync_threshold(struct ctl_table *table, int write, void __user *buffer, size_t *lenp, loff_t *ppos) { + struct netns_ipvs *ipvs = table->extra2; int *valp = table->data; int val[2]; int rc; + struct ctl_table tmp = { + .data = &val, + .maxlen = table->maxlen, + .mode = table->mode, + }; - /* backup the value first */ + mutex_lock(&ipvs->sync_mutex); memcpy(val, valp, sizeof(val)); - - rc = proc_dointvec(table, write, buffer, lenp, ppos); - if (write && (valp[0] < 0 || valp[1] < 0 || - (valp[0] >= valp[1] && valp[1]))) { - /* Restore the correct value */ - memcpy(valp, val, sizeof(val)); - } - return rc; -} - -static int -proc_do_sync_mode(struct ctl_table *table, int write, - void __user *buffer, size_t *lenp, loff_t *ppos) -{ - int *valp = table->data; - int val = *valp; - int rc; - - rc = proc_dointvec(table, write, buffer, lenp, ppos); - if (write && (*valp != val)) { - if ((*valp < 0) || (*valp > 1)) { - /* Restore the correct value */ - *valp = val; - } + rc = proc_dointvec(&tmp, write, buffer, lenp, ppos); + if (write) { + if (val[0] < 0 || val[1] < 0 || + (val[0] >= val[1] && val[1])) + rc = -EINVAL; + else + memcpy(valp, val, sizeof(val)); } + mutex_unlock(&ipvs->sync_mutex); return rc; } @@ -1725,12 +1722,18 @@ proc_do_sync_ports(struct ctl_table *table, int write, int val = *valp; int rc; - rc = proc_dointvec(table, write, buffer, lenp, ppos); + struct ctl_table tmp = { + .data = &val, + .maxlen = sizeof(int), + .mode = table->mode, + }; + + rc = proc_dointvec(&tmp, write, buffer, lenp, ppos); if (write && (*valp != val)) { - if (*valp < 1 || !is_power_of_2(*valp)) { - /* Restore the correct value */ + if (val < 1 || !is_power_of_2(val)) + rc = -EINVAL; + else *valp = val; - } } return rc; } @@ -1790,7 +1793,9 @@ static struct ctl_table vs_vars[] = { .procname = "sync_version", .maxlen = sizeof(int), .mode = 0644, - .proc_handler = proc_do_sync_mode, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + .extra2 = &one, }, { .procname = "sync_ports", @@ -3942,6 +3947,7 @@ static int __net_init ip_vs_control_net_init_sysctl(struct netns_ipvs *ipvs) ipvs->sysctl_sync_threshold[0] = DEFAULT_SYNC_THRESHOLD; ipvs->sysctl_sync_threshold[1] = DEFAULT_SYNC_PERIOD; tbl[idx].data = &ipvs->sysctl_sync_threshold; + tbl[idx].extra2 = ipvs; tbl[idx++].maxlen = sizeof(ipvs->sysctl_sync_threshold); ipvs->sysctl_sync_refresh_period = DEFAULT_SYNC_REFRESH_PERIOD; tbl[idx++].data = &ipvs->sysctl_sync_refresh_period; diff --git a/net/netfilter/ipvs/ip_vs_sync.c b/net/netfilter/ipvs/ip_vs_sync.c index f6af13c16cf57cb5a311477531360256831436bc..c133ce825c2dd1fd4e7cd6866e47fe84ec33ac0d 100644 --- a/net/netfilter/ipvs/ip_vs_sync.c +++ b/net/netfilter/ipvs/ip_vs_sync.c @@ -1444,7 +1444,7 @@ static int bind_mcastif_addr(struct socket *sock, struct net_device *dev) sin.sin_addr.s_addr = addr; sin.sin_port = 0; - return sock->ops->bind(sock, (struct sockaddr*)&sin, sizeof(sin)); + return kernel_bind(sock, (struct sockaddr *)&sin, sizeof(sin)); } static void get_mcast_sockaddr(union ipvs_sockaddr *sa, int *salen, @@ -1510,8 +1510,8 @@ static int make_send_sock(struct netns_ipvs *ipvs, int id, } get_mcast_sockaddr(&mcast_addr, &salen, &ipvs->mcfg, id); - result = sock->ops->connect(sock, (struct sockaddr *) &mcast_addr, - salen, 0); + result = kernel_connect(sock, (struct sockaddr *)&mcast_addr, + salen, 0); if (result < 0) { pr_err("Error connecting to the multicast addr\n"); goto error; @@ -1551,7 +1551,7 @@ static int make_receive_sock(struct netns_ipvs *ipvs, int id, get_mcast_sockaddr(&mcast_addr, &salen, &ipvs->bcfg, id); sock->sk->sk_bound_dev_if = dev->ifindex; - result = sock->ops->bind(sock, (struct sockaddr *)&mcast_addr, salen); + result = kernel_bind(sock, (struct sockaddr *)&mcast_addr, salen); if (result < 0) { pr_err("Error binding to the multicast addr\n"); goto error; diff --git a/net/netfilter/nf_conntrack_ftp.c b/net/netfilter/nf_conntrack_ftp.c index efc14c7b4f8ef68f24ccce80395465c27cc7b289..c2fece0593eaa20f49cd46071af810e5b43ec714 100644 --- a/net/netfilter/nf_conntrack_ftp.c +++ b/net/netfilter/nf_conntrack_ftp.c @@ -383,7 +383,7 @@ static int help(struct sk_buff *skb, int ret; u32 seq; int dir = CTINFO2DIR(ctinfo); - unsigned int uninitialized_var(matchlen), uninitialized_var(matchoff); + unsigned int matchlen, matchoff; struct nf_ct_ftp_master *ct_ftp_info = nfct_help_data(ct); struct nf_conntrack_expect *exp; union nf_inet_addr *daddr; diff --git a/net/netfilter/nf_conntrack_helper.c b/net/netfilter/nf_conntrack_helper.c index e24b762ffa1d4457d6595d72ba3f3ded62bcaf85..06c70d4584cfef31e762dacdf746e848c682dda3 100644 --- a/net/netfilter/nf_conntrack_helper.c +++ b/net/netfilter/nf_conntrack_helper.c @@ -400,6 +400,9 @@ int nf_conntrack_helper_register(struct nf_conntrack_helper *me) BUG_ON(me->expect_class_max >= NF_CT_MAX_EXPECT_CLASSES); BUG_ON(strlen(me->name) > NF_CT_HELPER_NAME_LEN - 1); + if (!nf_ct_helper_hash) + return -ENOENT; + if (me->expect_policy->max_expected > NF_CT_EXPECT_MAX_CNT) return -EINVAL; @@ -570,4 +573,5 @@ void nf_conntrack_helper_fini(void) { nf_ct_extend_unregister(&helper_extend); kvfree(nf_ct_helper_hash); + nf_ct_helper_hash = NULL; } diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c index 2850a638401d5b82558fe57c58f837b0fd3731be..83e8566ec3f0562ecc3420821295be6f22616d04 100644 --- a/net/netfilter/nf_conntrack_netlink.c +++ b/net/netfilter/nf_conntrack_netlink.c @@ -517,20 +517,15 @@ ctnetlink_fill_info(struct sk_buff *skb, u32 portid, u32 seq, u32 type, { const struct nf_conntrack_zone *zone; struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; struct nlattr *nest_parms; unsigned int flags = portid ? NLM_F_MULTI : 0, event; event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK, IPCTNL_MSG_CT_NEW); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, nf_ct_l3num(ct), + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = nf_ct_l3num(ct); - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - zone = nf_ct_zone(ct); nest_parms = nla_nest_start(skb, CTA_TUPLE_ORIG | NLA_F_NESTED); @@ -687,7 +682,6 @@ ctnetlink_conntrack_event(unsigned int events, struct nf_ct_event *item) const struct nf_conntrack_zone *zone; struct net *net; struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; struct nlattr *nest_parms; struct nf_conn *ct = item->ct; struct sk_buff *skb; @@ -717,15 +711,11 @@ ctnetlink_conntrack_event(unsigned int events, struct nf_ct_event *item) goto errout; type = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK, type); - nlh = nlmsg_put(skb, item->portid, 0, type, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, item->portid, 0, type, flags, nf_ct_l3num(ct), + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = nf_ct_l3num(ct); - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - zone = nf_ct_zone(ct); nest_parms = nla_nest_start(skb, CTA_TUPLE_ORIG | NLA_F_NESTED); @@ -1216,9 +1206,6 @@ static const struct nla_policy ct_nla_policy[CTA_MAX+1] = { static int ctnetlink_flush_iterate(struct nf_conn *ct, void *data) { - if (test_bit(IPS_OFFLOAD_BIT, &ct->status)) - return 0; - return ctnetlink_filter_match(ct, data); } @@ -1280,11 +1267,6 @@ static int ctnetlink_del_conntrack(struct net *net, struct sock *ctnl, ct = nf_ct_tuplehash_to_ctrack(h); - if (test_bit(IPS_OFFLOAD_BIT, &ct->status)) { - nf_ct_put(ct); - return -EBUSY; - } - if (cda[CTA_ID]) { __be32 id = nla_get_be32(cda[CTA_ID]); @@ -2056,12 +2038,15 @@ ctnetlink_create_conntrack(struct net *net, err = nf_conntrack_hash_check_insert(ct); if (err < 0) - goto err2; + goto err3; rcu_read_unlock(); return ct; +err3: + if (ct->master) + nf_ct_put(ct->master); err2: rcu_read_unlock(); err1: @@ -2175,20 +2160,15 @@ ctnetlink_ct_stat_cpu_fill_info(struct sk_buff *skb, u32 portid, u32 seq, __u16 cpu, const struct ip_conntrack_stat *st) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0, event; event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK, IPCTNL_MSG_CT_GET_STATS_CPU); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, htons(cpu)); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(cpu); - if (nla_put_be32(skb, CTA_STATS_FOUND, htonl(st->found)) || nla_put_be32(skb, CTA_STATS_INVALID, htonl(st->invalid)) || nla_put_be32(skb, CTA_STATS_IGNORE, htonl(st->ignore)) || @@ -2259,20 +2239,15 @@ ctnetlink_stat_ct_fill_info(struct sk_buff *skb, u32 portid, u32 seq, u32 type, struct net *net) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0, event; unsigned int nr_conntracks = atomic_read(&net->ct.count); event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK, IPCTNL_MSG_CT_GET_STATS); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_be32(skb, CTA_STATS_GLOBAL_ENTRIES, htonl(nr_conntracks))) goto nla_put_failure; @@ -2686,7 +2661,9 @@ static int ctnetlink_exp_dump_mask(struct sk_buff *skb, return -1; } +#if IS_ENABLED(CONFIG_NF_NAT) static const union nf_inet_addr any_addr; +#endif static __be32 nf_expect_get_id(const struct nf_conntrack_expect *exp) { @@ -2783,19 +2760,14 @@ ctnetlink_exp_fill_info(struct sk_buff *skb, u32 portid, u32 seq, int event, const struct nf_conntrack_expect *exp) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0; event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK_EXP, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, + exp->tuple.src.l3num, NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = exp->tuple.src.l3num; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (ctnetlink_exp_dump_expect(skb, exp) < 0) goto nla_put_failure; @@ -2815,7 +2787,6 @@ ctnetlink_expect_event(unsigned int events, struct nf_exp_event *item) struct nf_conntrack_expect *exp = item->exp; struct net *net = nf_ct_exp_net(exp); struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; struct sk_buff *skb; unsigned int type, group; int flags = 0; @@ -2838,15 +2809,11 @@ ctnetlink_expect_event(unsigned int events, struct nf_exp_event *item) goto errout; type = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK_EXP, type); - nlh = nlmsg_put(skb, item->portid, 0, type, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, item->portid, 0, type, flags, + exp->tuple.src.l3num, NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = exp->tuple.src.l3num; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (ctnetlink_exp_dump_expect(skb, exp) < 0) goto nla_put_failure; @@ -3186,10 +3153,12 @@ ctnetlink_change_expect(struct nf_conntrack_expect *x, return 0; } +#if IS_ENABLED(CONFIG_NF_NAT) static const struct nla_policy exp_nat_nla_policy[CTA_EXPECT_NAT_MAX+1] = { [CTA_EXPECT_NAT_DIR] = { .type = NLA_U32 }, [CTA_EXPECT_NAT_TUPLE] = { .type = NLA_NESTED }, }; +#endif static int ctnetlink_parse_expect_nat(const struct nlattr *attr, @@ -3414,20 +3383,15 @@ ctnetlink_exp_stat_fill_info(struct sk_buff *skb, u32 portid, u32 seq, int cpu, const struct ip_conntrack_stat *st) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0, event; event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK, IPCTNL_MSG_EXP_GET_STATS_CPU); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, htons(cpu)); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(cpu); - if (nla_put_be32(skb, CTA_STATS_EXP_NEW, htonl(st->expect_new)) || nla_put_be32(skb, CTA_STATS_EXP_CREATE, htonl(st->expect_create)) || nla_put_be32(skb, CTA_STATS_EXP_DELETE, htonl(st->expect_delete))) diff --git a/net/netfilter/nf_conntrack_proto_sctp.c b/net/netfilter/nf_conntrack_proto_sctp.c index cadeb22a48f23dafddf21b609f9fd359cbfaceda..8453e92936ac9743b7b6bb9db998a0150beb132d 100644 --- a/net/netfilter/nf_conntrack_proto_sctp.c +++ b/net/netfilter/nf_conntrack_proto_sctp.c @@ -58,8 +58,8 @@ static const unsigned int sctp_timeouts[SCTP_CONNTRACK_MAX] = { [SCTP_CONNTRACK_COOKIE_WAIT] = 3 SECS, [SCTP_CONNTRACK_COOKIE_ECHOED] = 3 SECS, [SCTP_CONNTRACK_ESTABLISHED] = 5 DAYS, - [SCTP_CONNTRACK_SHUTDOWN_SENT] = 300 SECS / 1000, - [SCTP_CONNTRACK_SHUTDOWN_RECD] = 300 SECS / 1000, + [SCTP_CONNTRACK_SHUTDOWN_SENT] = 3 SECS, + [SCTP_CONNTRACK_SHUTDOWN_RECD] = 3 SECS, [SCTP_CONNTRACK_SHUTDOWN_ACK_SENT] = 3 SECS, [SCTP_CONNTRACK_HEARTBEAT_SENT] = 30 SECS, [SCTP_CONNTRACK_HEARTBEAT_ACKED] = 210 SECS, @@ -119,7 +119,7 @@ static const u8 sctp_conntracks[2][11][SCTP_CONNTRACK_MAX] = { { /* ORIGINAL */ /* sNO, sCL, sCW, sCE, sES, sSS, sSR, sSA, sHS, sHA */ -/* init */ {sCW, sCW, sCW, sCE, sES, sSS, sSR, sSA, sCW, sHA}, +/* init */ {sCW, sCW, sCW, sCE, sES, sCL, sCL, sSA, sCW, sHA}, /* init_ack */ {sCL, sCL, sCW, sCE, sES, sSS, sSR, sSA, sCL, sHA}, /* abort */ {sCL, sCL, sCL, sCL, sCL, sCL, sCL, sCL, sCL, sCL}, /* shutdown */ {sCL, sCL, sCW, sCE, sSS, sSS, sSR, sSA, sCL, sSS}, diff --git a/net/netfilter/nf_conntrack_sip.c b/net/netfilter/nf_conntrack_sip.c index 046f118dea06bd5244691b8c9644569b013c7635..d16aa43ebd4d69169f609885c5234d5c80327533 100644 --- a/net/netfilter/nf_conntrack_sip.c +++ b/net/netfilter/nf_conntrack_sip.c @@ -605,7 +605,7 @@ int ct_sip_parse_numerical_param(const struct nf_conn *ct, const char *dptr, start += strlen(name); *val = simple_strtoul(start, &end, 0); if (start == end) - return 0; + return -1; if (matchoff && matchlen) { *matchoff = start - dptr; *matchlen = end - start; diff --git a/net/netfilter/nf_queue.c b/net/netfilter/nf_queue.c index 84c59de2788222b4532fd3f602399726f064c97f..b3a0385290a15ac39c1bf710f5c9c15aa238e7c8 100644 --- a/net/netfilter/nf_queue.c +++ b/net/netfilter/nf_queue.c @@ -93,8 +93,6 @@ bool nf_queue_entry_get_refs(struct nf_queue_entry *entry) dev_hold(state->in); if (state->out) dev_hold(state->out); - if (state->sk) - sock_hold(state->sk); #if IS_ENABLED(CONFIG_BRIDGE_NETFILTER) if (entry->skb->nf_bridge) { struct net_device *physdev; diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 079f76849693785cc75df6d6c7464f6868f4ec29..3e3044116289638e9ee4b142123a91b5cda30f4e 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -22,10 +22,13 @@ #include #include #include +#include #include #define NFT_MODULE_AUTOLOAD_LIMIT (MODULE_NAME_LEN - sizeof("nft-expr-255-")) +unsigned int nf_tables_net_id __read_mostly; + static LIST_HEAD(nf_tables_expressions); static LIST_HEAD(nf_tables_objects); static LIST_HEAD(nf_tables_flowtables); @@ -53,7 +56,9 @@ static const struct rhashtable_params nft_chain_ht_params = { static void nft_validate_state_update(struct net *net, u8 new_validate_state) { - switch (net->nft.validate_state) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); + + switch (nft_net->validate_state) { case NFT_VALIDATE_SKIP: WARN_ON_ONCE(new_validate_state == NFT_VALIDATE_DO); break; @@ -64,7 +69,7 @@ static void nft_validate_state_update(struct net *net, u8 new_validate_state) return; } - net->nft.validate_state = new_validate_state; + nft_net->validate_state = new_validate_state; } static void nft_ctx_init(struct nft_ctx *ctx, @@ -97,6 +102,7 @@ static struct nft_trans *nft_trans_alloc_gfp(const struct nft_ctx *ctx, return NULL; INIT_LIST_HEAD(&trans->list); + INIT_LIST_HEAD(&trans->binding_list); trans->msg_type = msg_type; trans->ctx = *ctx; @@ -109,34 +115,68 @@ static struct nft_trans *nft_trans_alloc(const struct nft_ctx *ctx, return nft_trans_alloc_gfp(ctx, msg_type, size, GFP_KERNEL); } -static void nft_trans_destroy(struct nft_trans *trans) +static void nft_trans_list_del(struct nft_trans *trans) { list_del(&trans->list); + list_del(&trans->binding_list); +} + +static void nft_trans_destroy(struct nft_trans *trans) +{ + nft_trans_list_del(trans); kfree(trans); } -static void nft_set_trans_bind(const struct nft_ctx *ctx, struct nft_set *set) +static void __nft_set_trans_bind(const struct nft_ctx *ctx, struct nft_set *set, + bool bind) { + struct nftables_pernet *nft_net; struct net *net = ctx->net; struct nft_trans *trans; if (!nft_set_is_anonymous(set)) return; - list_for_each_entry_reverse(trans, &net->nft.commit_list, list) { + nft_net = net_generic(net, nf_tables_net_id); + list_for_each_entry_reverse(trans, &nft_net->commit_list, list) { switch (trans->msg_type) { case NFT_MSG_NEWSET: if (nft_trans_set(trans) == set) - nft_trans_set_bound(trans) = true; + nft_trans_set_bound(trans) = bind; break; case NFT_MSG_NEWSETELEM: if (nft_trans_elem_set(trans) == set) - nft_trans_elem_set_bound(trans) = true; + nft_trans_elem_set_bound(trans) = bind; break; } } } +static void nft_set_trans_bind(const struct nft_ctx *ctx, struct nft_set *set) +{ + return __nft_set_trans_bind(ctx, set, true); +} + +static void nft_set_trans_unbind(const struct nft_ctx *ctx, struct nft_set *set) +{ + return __nft_set_trans_bind(ctx, set, false); +} + +static void nft_trans_commit_list_add_tail(struct net *net, struct nft_trans *trans) +{ + struct nftables_pernet *nft_net; + + nft_net = net_generic(net, nf_tables_net_id); + switch (trans->msg_type) { + case NFT_MSG_NEWSET: + if (nft_set_is_anonymous(nft_trans_set(trans))) + list_add_tail(&trans->binding_list, &nft_net->binding_list); + break; + } + + list_add_tail(&trans->list, &nft_net->commit_list); +} + static int nf_tables_register_hook(struct net *net, const struct nft_table *table, struct nft_chain *chain) @@ -187,7 +227,7 @@ static int nft_trans_table_add(struct nft_ctx *ctx, int msg_type) if (msg_type == NFT_MSG_NEWTABLE) nft_activate_next(ctx->net, ctx->table); - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; } @@ -214,7 +254,7 @@ static int nft_trans_chain_add(struct nft_ctx *ctx, int msg_type) if (msg_type == NFT_MSG_NEWCHAIN) nft_activate_next(ctx->net, ctx->chain); - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; } @@ -226,7 +266,7 @@ static int nft_delchain(struct nft_ctx *ctx) if (err < 0) return err; - ctx->table->use--; + nft_use_dec(&ctx->table->use); nft_deactivate_next(ctx->net, ctx->chain); return err; @@ -267,7 +307,7 @@ nf_tables_delrule_deactivate(struct nft_ctx *ctx, struct nft_rule *rule) /* You cannot delete the same rule twice */ if (nft_is_active_next(ctx->net, rule)) { nft_deactivate_next(ctx->net, rule); - ctx->chain->use--; + nft_use_dec(&ctx->chain->use); return 0; } return -ENOENT; @@ -287,7 +327,7 @@ static struct nft_trans *nft_trans_rule_add(struct nft_ctx *ctx, int msg_type, ntohl(nla_get_be32(ctx->nla[NFTA_RULE_ID])); } nft_trans_rule(trans) = rule; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return trans; } @@ -342,7 +382,7 @@ static int nft_trans_set_add(const struct nft_ctx *ctx, int msg_type, nft_activate_next(ctx->net, set); } nft_trans_set(trans) = set; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; } @@ -356,7 +396,7 @@ static int nft_delset(const struct nft_ctx *ctx, struct nft_set *set) return err; nft_deactivate_next(ctx->net, set); - ctx->table->use--; + nft_use_dec(&ctx->table->use); return err; } @@ -374,7 +414,7 @@ static int nft_trans_obj_add(struct nft_ctx *ctx, int msg_type, nft_activate_next(ctx->net, obj); nft_trans_obj(trans) = obj; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; } @@ -388,7 +428,7 @@ static int nft_delobj(struct nft_ctx *ctx, struct nft_object *obj) return err; nft_deactivate_next(ctx->net, obj); - ctx->table->use--; + nft_use_dec(&ctx->table->use); return err; } @@ -407,7 +447,7 @@ static int nft_trans_flowtable_add(struct nft_ctx *ctx, int msg_type, nft_activate_next(ctx->net, flowtable); nft_trans_flowtable(trans) = flowtable; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; } @@ -422,7 +462,7 @@ static int nft_delflowtable(struct nft_ctx *ctx, return err; nft_deactivate_next(ctx->net, flowtable); - ctx->table->use--; + nft_use_dec(&ctx->table->use); return err; } @@ -435,12 +475,14 @@ static struct nft_table *nft_table_lookup(const struct net *net, const struct nlattr *nla, u8 family, u8 genmask) { + struct nftables_pernet *nft_net; struct nft_table *table; if (nla == NULL) return ERR_PTR(-EINVAL); - list_for_each_entry_rcu(table, &net->nft.tables, list) { + nft_net = net_generic(net, nf_tables_net_id); + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (!nla_strcmp(nla, table->name) && table->family == family && nft_active_genmask(table, genmask)) @@ -454,9 +496,11 @@ static struct nft_table *nft_table_lookup_byhandle(const struct net *net, const struct nlattr *nla, u8 genmask) { + struct nftables_pernet *nft_net; struct nft_table *table; - list_for_each_entry(table, &net->nft.tables, list) { + nft_net = net_generic(net, nf_tables_net_id); + list_for_each_entry(table, &nft_net->tables, list) { if (be64_to_cpu(nla_get_be64(nla)) == table->handle && nft_active_genmask(table, genmask)) return table; @@ -509,11 +553,13 @@ __nf_tables_chain_type_lookup(const struct nlattr *nla, u8 family) static void nft_request_module(struct net *net, const char *fmt, ...) { char module_name[MODULE_NAME_LEN]; + struct nftables_pernet *nft_net; LIST_HEAD(commit_list); va_list args; int ret; - list_splice_init(&net->nft.commit_list, &commit_list); + nft_net = net_generic(net, nf_tables_net_id); + list_splice_init(&nft_net->commit_list, &commit_list); va_start(args, fmt); ret = vsnprintf(module_name, MODULE_NAME_LEN, fmt, args); @@ -521,12 +567,12 @@ static void nft_request_module(struct net *net, const char *fmt, ...) if (ret >= MODULE_NAME_LEN) return; - mutex_unlock(&net->nft.commit_mutex); + mutex_unlock(&nft_net->commit_mutex); request_module("%s", module_name); - mutex_lock(&net->nft.commit_mutex); + mutex_lock(&nft_net->commit_mutex); - WARN_ON_ONCE(!list_empty(&net->nft.commit_list)); - list_splice(&commit_list, &net->nft.commit_list); + WARN_ON_ONCE(!list_empty(&nft_net->commit_list)); + list_splice(&commit_list, &nft_net->commit_list); } #endif @@ -561,6 +607,13 @@ nf_tables_chain_type_lookup(struct net *net, const struct nlattr *nla, return ERR_PTR(-ENOENT); } +static __be16 nft_base_seq(const struct net *net) +{ + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); + + return htons(nft_net->base_seq & 0xffff); +} + static const struct nla_policy nft_table_policy[NFTA_TABLE_MAX + 1] = { [NFTA_TABLE_NAME] = { .type = NLA_STRING, .len = NFT_TABLE_MAXNAMELEN - 1 }, @@ -573,18 +626,13 @@ static int nf_tables_fill_table_info(struct sk_buff *skb, struct net *net, int family, const struct nft_table *table) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, family, + NFNETLINK_V0, nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); - if (nla_put_string(skb, NFTA_TABLE_NAME, table->name) || nla_put_be32(skb, NFTA_TABLE_FLAGS, htonl(table->flags)) || nla_put_be32(skb, NFTA_TABLE_USE, htonl(table->use)) || @@ -631,15 +679,17 @@ static int nf_tables_dump_tables(struct sk_buff *skb, struct netlink_callback *cb) { const struct nfgenmsg *nfmsg = nlmsg_data(cb->nlh); + struct nftables_pernet *nft_net; const struct nft_table *table; unsigned int idx = 0, s_idx = cb->args[0]; struct net *net = sock_net(skb->sk); int family = nfmsg->nfgen_family; rcu_read_lock(); - cb->seq = net->nft.base_seq; + nft_net = net_generic(net, nf_tables_net_id); + cb->seq = nft_net->base_seq; - list_for_each_entry_rcu(table, &net->nft.tables, list) { + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) continue; @@ -743,7 +793,7 @@ static void nft_table_disable(struct net *net, struct nft_table *table, u32 cnt) if (cnt && i++ == cnt) break; - nf_unregister_net_hook(net, &nft_base_chain(chain)->ops); + nf_tables_unregister_hook(net, table, chain); } } @@ -758,7 +808,7 @@ static int nf_tables_table_enable(struct net *net, struct nft_table *table) if (!nft_is_base_chain(chain)) continue; - err = nf_register_net_hook(net, &nft_base_chain(chain)->ops); + err = nf_tables_register_hook(net, table, chain); if (err < 0) goto err; @@ -802,17 +852,18 @@ static int nf_tables_updtable(struct nft_ctx *ctx) nft_trans_table_enable(trans) = false; } else if (!(flags & NFT_TABLE_F_DORMANT) && ctx->table->flags & NFT_TABLE_F_DORMANT) { + ctx->table->flags &= ~NFT_TABLE_F_DORMANT; ret = nf_tables_table_enable(ctx->net, ctx->table); - if (ret >= 0) { - ctx->table->flags &= ~NFT_TABLE_F_DORMANT; + if (ret >= 0) nft_trans_table_enable(trans) = true; - } + else + ctx->table->flags |= NFT_TABLE_F_DORMANT; } if (ret < 0) goto err; nft_trans_table_update(trans) = true; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; err: nft_trans_destroy(trans); @@ -847,6 +898,7 @@ static int nf_tables_newtable(struct net *net, struct sock *nlsk, const struct nlattr * const nla[], struct netlink_ext_ack *extack) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); const struct nfgenmsg *nfmsg = nlmsg_data(nlh); u8 genmask = nft_genmask_next(net); int family = nfmsg->nfgen_family; @@ -856,7 +908,7 @@ static int nf_tables_newtable(struct net *net, struct sock *nlsk, struct nft_ctx ctx; int err; - lockdep_assert_held(&net->nft.commit_mutex); + lockdep_assert_held(&nft_net->commit_mutex); attr = nla[NFTA_TABLE_NAME]; table = nft_table_lookup(net, attr, family, genmask); if (IS_ERR(table)) { @@ -906,7 +958,7 @@ static int nf_tables_newtable(struct net *net, struct sock *nlsk, if (err < 0) goto err_trans; - list_add_tail_rcu(&table->list, &net->nft.tables); + list_add_tail_rcu(&table->list, &nft_net->tables); return 0; err_trans: rhltable_destroy(&table->chains_ht); @@ -941,8 +993,7 @@ static int nft_flush_table(struct nft_ctx *ctx) if (!nft_is_active_next(ctx->net, set)) continue; - if (nft_set_is_anonymous(set) && - !list_empty(&set->bindings)) + if (nft_set_is_anonymous(set)) continue; err = nft_delset(ctx, set); @@ -986,11 +1037,12 @@ static int nft_flush_table(struct nft_ctx *ctx) static int nft_flush(struct nft_ctx *ctx, int family) { + struct nftables_pernet *nft_net = net_generic(ctx->net, nf_tables_net_id); struct nft_table *table, *nt; const struct nlattr * const *nla = ctx->nla; int err = 0; - list_for_each_entry_safe(table, nt, &ctx->net->nft.tables, list) { + list_for_each_entry_safe(table, nt, &nft_net->tables, list) { if (family != AF_UNSPEC && table->family != family) continue; @@ -1104,7 +1156,9 @@ nft_chain_lookup_byhandle(const struct nft_table *table, u64 handle, u8 genmask) static bool lockdep_commit_lock_is_held(struct net *net) { #ifdef CONFIG_PROVE_LOCKING - return lockdep_is_held(&net->nft.commit_mutex); + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); + + return lockdep_is_held(&nft_net->commit_mutex); #else return true; #endif @@ -1207,18 +1261,13 @@ static int nf_tables_fill_chain_info(struct sk_buff *skb, struct net *net, const struct nft_chain *chain) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, family, + NFNETLINK_V0, nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); - if (nla_put_string(skb, NFTA_CHAIN_TABLE, table->name)) goto nla_put_failure; if (nla_put_be64(skb, NFTA_CHAIN_HANDLE, cpu_to_be64(chain->handle), @@ -1306,11 +1355,13 @@ static int nf_tables_dump_chains(struct sk_buff *skb, unsigned int idx = 0, s_idx = cb->args[0]; struct net *net = sock_net(skb->sk); int family = nfmsg->nfgen_family; + struct nftables_pernet *nft_net; rcu_read_lock(); - cb->seq = net->nft.base_seq; + nft_net = net_generic(net, nf_tables_net_id); + cb->seq = nft_net->base_seq; - list_for_each_entry_rcu(table, &net->nft.tables, list) { + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) continue; @@ -1503,12 +1554,13 @@ static int nft_chain_parse_hook(struct net *net, struct nft_chain_hook *hook, u8 family, bool autoload) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nlattr *ha[NFTA_HOOK_MAX + 1]; const struct nft_chain_type *type; struct net_device *dev; int err; - lockdep_assert_held(&net->nft.commit_mutex); + lockdep_assert_held(&nft_net->commit_mutex); lockdep_nfnl_nft_mutex_not_held(); err = nla_parse_nested(ha, NFTA_HOOK_MAX, nla[NFTA_CHAIN_HOOK], @@ -1607,9 +1659,6 @@ static int nf_tables_addchain(struct nft_ctx *ctx, u8 family, u8 genmask, struct nft_rule **rules; int err; - if (table->use == UINT_MAX) - return -EOVERFLOW; - if (nla[NFTA_CHAIN_HOOK]) { struct nft_chain_hook hook; struct nf_hook_ops *ops; @@ -1681,6 +1730,11 @@ static int nf_tables_addchain(struct nft_ctx *ctx, u8 family, u8 genmask, if (err < 0) goto err1; + if (!nft_use_inc(&table->use)) { + err = -EMFILE; + goto err_use; + } + err = rhltable_insert_key(&table->chains_ht, chain->name, &chain->rhlhead, nft_chain_ht_params); if (err) @@ -1693,11 +1747,12 @@ static int nf_tables_addchain(struct nft_ctx *ctx, u8 family, u8 genmask, goto err2; } - table->use++; list_add_tail_rcu(&chain->list, &table->chains); return 0; err2: + nft_use_dec_restore(&table->use); +err_use: nf_tables_unregister_hook(net, table, chain); err1: nf_tables_chain_destroy(ctx); @@ -1777,6 +1832,7 @@ static int nf_tables_updchain(struct nft_ctx *ctx, u8 genmask, u8 policy) if (nla[NFTA_CHAIN_HANDLE] && nla[NFTA_CHAIN_NAME]) { + struct nftables_pernet *nft_net = net_generic(ctx->net, nf_tables_net_id); struct nft_trans *tmp; char *name; @@ -1786,7 +1842,7 @@ static int nf_tables_updchain(struct nft_ctx *ctx, u8 genmask, u8 policy) goto err; err = -EEXIST; - list_for_each_entry(tmp, &ctx->net->nft.commit_list, list) { + list_for_each_entry(tmp, &nft_net->commit_list, list) { if (tmp->msg_type == NFT_MSG_NEWCHAIN && tmp->ctx.table == table && nft_trans_chain_update(tmp) && @@ -1799,7 +1855,7 @@ static int nf_tables_updchain(struct nft_ctx *ctx, u8 genmask, u8 policy) nft_trans_chain_name(trans) = name; } - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; err: @@ -1813,6 +1869,7 @@ static int nf_tables_newchain(struct net *net, struct sock *nlsk, const struct nlattr * const nla[], struct netlink_ext_ack *extack) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); const struct nfgenmsg *nfmsg = nlmsg_data(nlh); u8 genmask = nft_genmask_next(net); int family = nfmsg->nfgen_family; @@ -1823,7 +1880,7 @@ static int nf_tables_newchain(struct net *net, struct sock *nlsk, struct nft_ctx ctx; u64 handle = 0; - lockdep_assert_held(&net->nft.commit_mutex); + lockdep_assert_held(&nft_net->commit_mutex); table = nft_table_lookup(net, nla[NFTA_CHAIN_TABLE], family, genmask); if (IS_ERR(table)) { @@ -2251,21 +2308,16 @@ static int nf_tables_fill_rule_info(struct sk_buff *skb, struct net *net, const struct nft_rule *rule) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; const struct nft_expr *expr, *next; struct nlattr *list; const struct nft_rule *prule; u16 type = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, type, sizeof(struct nfgenmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, type, flags, family, NFNETLINK_V0, + nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); - if (nla_put_string(skb, NFTA_RULE_TABLE, table->name)) goto nla_put_failure; if (nla_put_string(skb, NFTA_RULE_CHAIN, chain->name)) @@ -2351,11 +2403,13 @@ static int nf_tables_dump_rules(struct sk_buff *skb, unsigned int idx = 0, s_idx = cb->args[0]; struct net *net = sock_net(skb->sk); int family = nfmsg->nfgen_family; + struct nftables_pernet *nft_net; rcu_read_lock(); - cb->seq = net->nft.base_seq; + nft_net = net_generic(net, nf_tables_net_id); + cb->seq = nft_net->base_seq; - list_for_each_entry_rcu(table, &net->nft.tables, list) { + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) continue; @@ -2508,7 +2562,6 @@ static void nf_tables_rule_destroy(const struct nft_ctx *ctx, { struct nft_expr *expr, *next; - lockdep_assert_held(&ctx->net->nft.commit_mutex); /* * Careful: some expressions might not be initialized in case this * is called on error from nf_tables_newrule(). @@ -2574,6 +2627,8 @@ static int nft_table_validate(struct net *net, const struct nft_table *table) err = nft_chain_validate(&ctx, chain); if (err < 0) return err; + + cond_resched(); } return 0; @@ -2586,6 +2641,7 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, const struct nlattr * const nla[], struct netlink_ext_ack *extack) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); const struct nfgenmsg *nfmsg = nlmsg_data(nlh); u8 genmask = nft_genmask_next(net); struct nft_expr_info *info = NULL; @@ -2602,7 +2658,7 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, int err, rem; u64 handle, pos_handle; - lockdep_assert_held(&net->nft.commit_mutex); + lockdep_assert_held(&nft_net->commit_mutex); table = nft_table_lookup(net, nla[NFTA_RULE_TABLE], family, genmask); if (IS_ERR(table)) { @@ -2638,9 +2694,6 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, return -EINVAL; handle = nf_tables_alloc_handle(table); - if (chain->use == UINT_MAX) - return -EOVERFLOW; - if (nla[NFTA_RULE_POSITION]) { pos_handle = be64_to_cpu(nla_get_be64(nla[NFTA_RULE_POSITION])); old_rule = __nft_rule_lookup(chain, pos_handle); @@ -2716,23 +2769,28 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, expr = nft_expr_next(expr); } + if (!nft_use_inc(&chain->use)) { + err = -EMFILE; + goto err2; + } + if (nlh->nlmsg_flags & NLM_F_REPLACE) { trans = nft_trans_rule_add(&ctx, NFT_MSG_NEWRULE, rule); if (trans == NULL) { err = -ENOMEM; - goto err2; + goto err_destroy_flow_rule; } err = nft_delrule(&ctx, old_rule); if (err < 0) { nft_trans_destroy(trans); - goto err2; + goto err_destroy_flow_rule; } list_add_tail_rcu(&rule->list, &old_rule->list); } else { if (nft_trans_rule_add(&ctx, NFT_MSG_NEWRULE, rule) == NULL) { err = -ENOMEM; - goto err2; + goto err_destroy_flow_rule; } if (nlh->nlmsg_flags & NLM_F_APPEND) { @@ -2748,14 +2806,17 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, } } kvfree(info); - chain->use++; - if (net->nft.validate_state == NFT_VALIDATE_DO) + if (nft_net->validate_state == NFT_VALIDATE_DO) return nft_table_validate(net, table); return 0; + +err_destroy_flow_rule: + nft_use_dec_restore(&chain->use); err2: - nf_tables_rule_release(&ctx, rule); + nft_rule_expr_deactivate(&ctx, rule, NFT_TRANS_PREPARE_ERROR); + nf_tables_rule_destroy(&ctx, rule); err1: for (i = 0; i < n; i++) { if (info[i].ops) { @@ -2769,15 +2830,18 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, } static struct nft_rule *nft_rule_lookup_byid(const struct net *net, + const struct nft_chain *chain, const struct nlattr *nla) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); u32 id = ntohl(nla_get_be32(nla)); struct nft_trans *trans; - list_for_each_entry(trans, &net->nft.commit_list, list) { + list_for_each_entry(trans, &nft_net->commit_list, list) { struct nft_rule *rule = nft_trans_rule(trans); if (trans->msg_type == NFT_MSG_NEWRULE && + trans->ctx.chain == chain && id == nft_trans_rule_id(trans)) return rule; } @@ -2824,7 +2888,7 @@ static int nf_tables_delrule(struct net *net, struct sock *nlsk, err = nft_delrule(&ctx, rule); } else if (nla[NFTA_RULE_ID]) { - rule = nft_rule_lookup_byid(net, nla[NFTA_RULE_ID]); + rule = nft_rule_lookup_byid(net, chain, nla[NFTA_RULE_ID]); if (IS_ERR(rule)) { NL_SET_BAD_ATTR(extack, nla[NFTA_RULE_ID]); return PTR_ERR(rule); @@ -2892,12 +2956,13 @@ nft_select_set_ops(const struct nft_ctx *ctx, const struct nft_set_desc *desc, enum nft_set_policies policy) { + struct nftables_pernet *nft_net = net_generic(ctx->net, nf_tables_net_id); const struct nft_set_ops *ops, *bops; struct nft_set_estimate est, best; const struct nft_set_type *type; u32 flags = 0; - lockdep_assert_held(&ctx->net->nft.commit_mutex); + lockdep_assert_held(&nft_net->commit_mutex); lockdep_nfnl_nft_mutex_not_held(); #ifdef CONFIG_MODULES if (list_empty(&nf_tables_set_types)) { @@ -3043,10 +3108,11 @@ static struct nft_set *nft_set_lookup_byid(const struct net *net, const struct nft_table *table, const struct nlattr *nla, u8 genmask) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nft_trans *trans; u32 id = ntohl(nla_get_be32(nla)); - list_for_each_entry(trans, &net->nft.commit_list, list) { + list_for_each_entry(trans, &nft_net->commit_list, list) { if (trans->msg_type == NFT_MSG_NEWSET) { struct nft_set *set = nft_trans_set(trans); @@ -3156,23 +3222,17 @@ static __be64 nf_jiffies64_to_msecs(u64 input) static int nf_tables_fill_set(struct sk_buff *skb, const struct nft_ctx *ctx, const struct nft_set *set, u16 event, u16 flags) { - struct nfgenmsg *nfmsg; struct nlmsghdr *nlh; struct nlattr *desc; u32 portid = ctx->portid; u32 seq = ctx->seq; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), - flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, ctx->family, + NFNETLINK_V0, nft_base_seq(ctx->net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = ctx->family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(ctx->net->nft.base_seq & 0xffff); - if (nla_put_string(skb, NFTA_SET_TABLE, ctx->table->name)) goto nla_put_failure; if (nla_put_string(skb, NFTA_SET_NAME, set->name)) @@ -3268,14 +3328,16 @@ static int nf_tables_dump_sets(struct sk_buff *skb, struct netlink_callback *cb) struct nft_table *table, *cur_table = (struct nft_table *)cb->args[2]; struct net *net = sock_net(skb->sk); struct nft_ctx *ctx = cb->data, ctx_set; + struct nftables_pernet *nft_net; if (cb->args[1]) return skb->len; rcu_read_lock(); - cb->seq = net->nft.base_seq; + nft_net = net_generic(net, nf_tables_net_id); + cb->seq = nft_net->base_seq; - list_for_each_entry_rcu(table, &net->nft.tables, list) { + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (ctx->family != NFPROTO_UNSPEC && ctx->family != table->family) continue; @@ -3569,10 +3631,15 @@ static int nf_tables_newset(struct net *net, struct sock *nlsk, if (ops->privsize != NULL) size = ops->privsize(nla, &desc); + if (!nft_use_inc(&table->use)) { + err = -EMFILE; + goto err1; + } + set = kvzalloc(sizeof(*set) + size + udlen, GFP_KERNEL); if (!set) { err = -ENOMEM; - goto err1; + goto err_alloc; } name = nla_strdup(nla[NFTA_SET_NAME], GFP_KERNEL); @@ -3619,7 +3686,7 @@ static int nf_tables_newset(struct net *net, struct sock *nlsk, goto err4; list_add_tail_rcu(&set->list, &table->sets); - table->use++; + return 0; err4: @@ -3628,6 +3695,8 @@ static int nf_tables_newset(struct net *net, struct sock *nlsk, kfree(set->name); err2: kvfree(set); +err_alloc: + nft_use_dec_restore(&table->use); err1: module_put(to_set_type(ops)->owner); return err; @@ -3687,6 +3756,12 @@ static int nf_tables_delset(struct net *net, struct sock *nlsk, return nft_delset(&ctx, set); } +static int nft_validate_register_store(const struct nft_ctx *ctx, + enum nft_registers reg, + const struct nft_data *data, + enum nft_data_types type, + unsigned int len); + static int nf_tables_bind_check_setelem(const struct nft_ctx *ctx, struct nft_set *set, const struct nft_set_iter *iter, @@ -3708,9 +3783,6 @@ int nf_tables_bind_set(const struct nft_ctx *ctx, struct nft_set *set, struct nft_set_binding *i; struct nft_set_iter iter; - if (set->use == UINT_MAX) - return -EOVERFLOW; - if (!list_empty(&set->bindings) && nft_set_is_anonymous(set)) return -EBUSY; @@ -3735,10 +3807,12 @@ int nf_tables_bind_set(const struct nft_ctx *ctx, struct nft_set *set, return iter.err; } bind: + if (!nft_use_inc(&set->use)) + return -EMFILE; + binding->chain = ctx->chain; list_add_tail_rcu(&binding->list, &set->bindings); nft_set_trans_bind(ctx, set); - set->use++; return 0; } @@ -3758,17 +3832,38 @@ void nf_tables_unbind_set(const struct nft_ctx *ctx, struct nft_set *set, } EXPORT_SYMBOL_GPL(nf_tables_unbind_set); +void nf_tables_activate_set(const struct nft_ctx *ctx, struct nft_set *set) +{ + if (nft_set_is_anonymous(set)) + nft_clear(ctx->net, set); + + nft_use_inc_restore(&set->use); +} +EXPORT_SYMBOL_GPL(nf_tables_activate_set); + void nf_tables_deactivate_set(const struct nft_ctx *ctx, struct nft_set *set, struct nft_set_binding *binding, enum nft_trans_phase phase) { switch (phase) { + case NFT_TRANS_PREPARE_ERROR: + nft_set_trans_unbind(ctx, set); + if (nft_set_is_anonymous(set)) + nft_deactivate_next(ctx->net, set); + else + list_del_rcu(&binding->list); + + nft_use_dec(&set->use); + break; case NFT_TRANS_PREPARE: - set->use--; + if (nft_set_is_anonymous(set)) + nft_deactivate_next(ctx->net, set); + + nft_use_dec(&set->use); return; case NFT_TRANS_ABORT: case NFT_TRANS_RELEASE: - set->use--; + nft_use_dec(&set->use); /* fall through */ default: nf_tables_unbind_set(ctx, set, binding, @@ -3964,18 +4059,19 @@ static int nf_tables_dump_set(struct sk_buff *skb, struct netlink_callback *cb) { struct nft_set_dump_ctx *dump_ctx = cb->data; struct net *net = sock_net(skb->sk); + struct nftables_pernet *nft_net; struct nft_table *table; struct nft_set *set; struct nft_set_dump_args args; bool set_found = false; - struct nfgenmsg *nfmsg; struct nlmsghdr *nlh; struct nlattr *nest; u32 portid, seq; int event; rcu_read_lock(); - list_for_each_entry_rcu(table, &net->nft.tables, list) { + nft_net = net_generic(net, nf_tables_net_id); + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (dump_ctx->ctx.family != NFPROTO_UNSPEC && dump_ctx->ctx.family != table->family) continue; @@ -4001,16 +4097,11 @@ static int nf_tables_dump_set(struct sk_buff *skb, struct netlink_callback *cb) portid = NETLINK_CB(cb->skb).portid; seq = cb->nlh->nlmsg_seq; - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), - NLM_F_MULTI); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, NLM_F_MULTI, + table->family, NFNETLINK_V0, nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = table->family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); - if (nla_put_string(skb, NFTA_SET_ELEM_LIST_TABLE, table->name)) goto nla_put_failure; if (nla_put_string(skb, NFTA_SET_ELEM_LIST_SET, set->name)) @@ -4067,22 +4158,16 @@ static int nf_tables_fill_setelem_info(struct sk_buff *skb, const struct nft_set *set, const struct nft_set_elem *elem) { - struct nfgenmsg *nfmsg; struct nlmsghdr *nlh; struct nlattr *nest; int err; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), - flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, ctx->family, + NFNETLINK_V0, nft_base_seq(ctx->net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = ctx->family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(ctx->net->nft.base_seq & 0xffff); - if (nla_put_string(skb, NFTA_SET_TABLE, ctx->table->name)) goto nla_put_failure; if (nla_put_string(skb, NFTA_SET_NAME, set->name)) @@ -4122,11 +4207,54 @@ static int nft_setelem_parse_flags(const struct nft_set *set, return 0; } +static int nft_setelem_parse_key(struct nft_ctx *ctx, struct nft_set *set, + struct nft_data *key, struct nlattr *attr) +{ + struct nft_data_desc desc; + int err; + + err = nft_data_init(ctx, key, NFT_DATA_VALUE_MAXLEN, &desc, attr); + if (err < 0) + return err; + + if (desc.type != NFT_DATA_VALUE || desc.len != set->klen) { + nft_data_release(key, desc.type); + return -EINVAL; + } + + return 0; +} + +static int nft_setelem_parse_data(struct nft_ctx *ctx, struct nft_set *set, + struct nft_data_desc *desc, + struct nft_data *data, + struct nlattr *attr) +{ + u32 dtype; + int err; + + err = nft_data_init(ctx, data, NFT_DATA_VALUE_MAXLEN, desc, attr); + if (err < 0) + return err; + + if (set->dtype == NFT_DATA_VERDICT) + dtype = NFT_DATA_VERDICT; + else + dtype = NFT_DATA_VALUE; + + if (dtype != desc->type || + set->dlen != desc->len) { + nft_data_release(data, desc->type); + return -EINVAL; + } + + return 0; +} + static int nft_get_set_elem(struct nft_ctx *ctx, struct nft_set *set, const struct nlattr *attr) { struct nlattr *nla[NFTA_SET_ELEM_MAX + 1]; - struct nft_data_desc desc; struct nft_set_elem elem; struct sk_buff *skb; uint32_t flags = 0; @@ -4145,17 +4273,11 @@ static int nft_get_set_elem(struct nft_ctx *ctx, struct nft_set *set, if (err < 0) return err; - err = nft_data_init(ctx, &elem.key.val, sizeof(elem.key), &desc, - nla[NFTA_SET_ELEM_KEY]); + err = nft_setelem_parse_key(ctx, set, &elem.key.val, + nla[NFTA_SET_ELEM_KEY]); if (err < 0) return err; - err = -EINVAL; - if (desc.type != NFT_DATA_VALUE || desc.len != set->klen) { - nft_data_release(&elem.key.val, desc.type); - return err; - } - priv = set->ops->get(ctx->net, set, &elem, flags); if (IS_ERR(priv)) return PTR_ERR(priv); @@ -4323,7 +4445,7 @@ void nft_set_elem_destroy(const struct nft_set *set, void *elem, } } if (nft_set_ext_exists(ext, NFT_SET_EXT_OBJREF)) - (*nft_set_ext_obj(ext))->use--; + nft_use_dec(&(*nft_set_ext_obj(ext))->use); kfree(elem); } EXPORT_SYMBOL_GPL(nft_set_elem_destroy); @@ -4346,14 +4468,13 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, { struct nlattr *nla[NFTA_SET_ELEM_MAX + 1]; u8 genmask = nft_genmask_next(ctx->net); - struct nft_data_desc d1, d2; struct nft_set_ext_tmpl tmpl; struct nft_set_ext *ext, *ext2; struct nft_set_elem elem; struct nft_set_binding *binding; struct nft_object *obj = NULL; struct nft_userdata *udata; - struct nft_data data; + struct nft_data_desc desc; enum nft_registers dreg; struct nft_trans *trans; u32 flags = 0; @@ -4386,6 +4507,15 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, return -EINVAL; } + if (set->flags & NFT_SET_OBJECT) { + if (!nla[NFTA_SET_ELEM_OBJREF] && + !(flags & NFT_SET_ELEM_INTERVAL_END)) + return -EINVAL; + } else { + if (nla[NFTA_SET_ELEM_OBJREF]) + return -EINVAL; + } + if ((flags & NFT_SET_ELEM_INTERVAL_END) && (nla[NFTA_SET_ELEM_DATA] || nla[NFTA_SET_ELEM_OBJREF] || @@ -4407,15 +4537,12 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, timeout = set->timeout; } - err = nft_data_init(ctx, &elem.key.val, sizeof(elem.key), &d1, - nla[NFTA_SET_ELEM_KEY]); + err = nft_setelem_parse_key(ctx, set, &elem.key.val, + nla[NFTA_SET_ELEM_KEY]); if (err < 0) goto err1; - err = -EINVAL; - if (d1.type != NFT_DATA_VALUE || d1.len != set->klen) - goto err2; - nft_set_ext_add_length(&tmpl, NFT_SET_EXT_KEY, d1.len); + nft_set_ext_add_length(&tmpl, NFT_SET_EXT_KEY, set->klen); if (timeout > 0) { nft_set_ext_add(&tmpl, NFT_SET_EXT_EXPIRATION); if (timeout != set->timeout) @@ -4423,29 +4550,29 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, } if (nla[NFTA_SET_ELEM_OBJREF] != NULL) { - if (!(set->flags & NFT_SET_OBJECT)) { - err = -EINVAL; - goto err2; - } obj = nft_obj_lookup(ctx->table, nla[NFTA_SET_ELEM_OBJREF], set->objtype, genmask); if (IS_ERR(obj)) { err = PTR_ERR(obj); + obj = NULL; + goto err2; + } + + if (!nft_use_inc(&obj->use)) { + err = -EMFILE; + obj = NULL; goto err2; } + nft_set_ext_add(&tmpl, NFT_SET_EXT_OBJREF); } if (nla[NFTA_SET_ELEM_DATA] != NULL) { - err = nft_data_init(ctx, &data, sizeof(data), &d2, - nla[NFTA_SET_ELEM_DATA]); + err = nft_setelem_parse_data(ctx, set, &desc, &elem.data.val, + nla[NFTA_SET_ELEM_DATA]); if (err < 0) goto err2; - err = -EINVAL; - if (set->dtype != NFT_DATA_VERDICT && d2.len != set->dlen) - goto err3; - dreg = nft_type_to_reg(set->dtype); list_for_each_entry(binding, &set->bindings, list) { struct nft_ctx bind_ctx = { @@ -4459,19 +4586,19 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, continue; err = nft_validate_register_store(&bind_ctx, dreg, - &data, - d2.type, d2.len); + &elem.data.val, + desc.type, desc.len); if (err < 0) goto err3; - if (d2.type == NFT_DATA_VERDICT && - (data.verdict.code == NFT_GOTO || - data.verdict.code == NFT_JUMP)) + if (desc.type == NFT_DATA_VERDICT && + (elem.data.val.verdict.code == NFT_GOTO || + elem.data.val.verdict.code == NFT_JUMP)) nft_validate_state_update(ctx->net, NFT_VALIDATE_NEED); } - nft_set_ext_add_length(&tmpl, NFT_SET_EXT_DATA, d2.len); + nft_set_ext_add_length(&tmpl, NFT_SET_EXT_DATA, desc.len); } /* The full maximum length of userdata can exceed the maximum @@ -4487,7 +4614,8 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, } err = -ENOMEM; - elem.priv = nft_set_elem_init(set, &tmpl, elem.key.val.data, data.data, + elem.priv = nft_set_elem_init(set, &tmpl, elem.key.val.data, + elem.data.val.data, timeout, GFP_KERNEL); if (elem.priv == NULL) goto err3; @@ -4500,10 +4628,8 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, udata->len = ulen - 1; nla_memcpy(&udata->data, nla[NFTA_SET_ELEM_USERDATA], ulen); } - if (obj) { + if (obj) *nft_set_ext_obj(ext) = obj; - obj->use++; - } trans = nft_trans_elem_alloc(ctx, NFT_MSG_NEWSETELEM, set); if (trans == NULL) @@ -4541,7 +4667,7 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, } nft_trans_elem(trans) = elem; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; err6: @@ -4549,14 +4675,15 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, err5: kfree(trans); err4: - if (obj) - obj->use--; kfree(elem.priv); err3: if (nla[NFTA_SET_ELEM_DATA] != NULL) - nft_data_release(&data, d2.type); + nft_data_release(&elem.data.val, desc.type); err2: - nft_data_release(&elem.key.val, d1.type); + if (obj) + nft_use_dec_restore(&obj->use); + + nft_data_release(&elem.key.val, NFT_DATA_VALUE); err1: return err; } @@ -4566,6 +4693,7 @@ static int nf_tables_newsetelem(struct net *net, struct sock *nlsk, const struct nlattr * const nla[], struct netlink_ext_ack *extack) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); u8 genmask = nft_genmask_next(net); const struct nlattr *attr; struct nft_set *set; @@ -4585,7 +4713,8 @@ static int nf_tables_newsetelem(struct net *net, struct sock *nlsk, if (IS_ERR(set)) return PTR_ERR(set); - if (!list_empty(&set->bindings) && set->flags & NFT_SET_CONSTANT) + if (!list_empty(&set->bindings) && + (set->flags & (NFT_SET_CONSTANT | NFT_SET_ANONYMOUS))) return -EBUSY; nla_for_each_nested(attr, nla[NFTA_SET_ELEM_LIST_ELEMENTS], rem) { @@ -4594,7 +4723,7 @@ static int nf_tables_newsetelem(struct net *net, struct sock *nlsk, return err; } - if (net->nft.validate_state == NFT_VALIDATE_DO) + if (nft_net->validate_state == NFT_VALIDATE_DO) return nft_table_validate(net, ctx.table); return 0; @@ -4613,11 +4742,14 @@ static int nf_tables_newsetelem(struct net *net, struct sock *nlsk, */ void nft_data_hold(const struct nft_data *data, enum nft_data_types type) { + struct nft_chain *chain; + if (type == NFT_DATA_VERDICT) { switch (data->verdict.code) { case NFT_JUMP: case NFT_GOTO: - data->verdict.chain->use++; + chain = data->verdict.chain; + nft_use_inc_restore(&chain->use); break; } } @@ -4632,7 +4764,7 @@ static void nft_set_elem_activate(const struct net *net, if (nft_set_ext_exists(ext, NFT_SET_EXT_DATA)) nft_data_hold(nft_set_ext_data(ext), set->dtype); if (nft_set_ext_exists(ext, NFT_SET_EXT_OBJREF)) - (*nft_set_ext_obj(ext))->use++; + nft_use_inc_restore(&(*nft_set_ext_obj(ext))->use); } static void nft_set_elem_deactivate(const struct net *net, @@ -4644,7 +4776,7 @@ static void nft_set_elem_deactivate(const struct net *net, if (nft_set_ext_exists(ext, NFT_SET_EXT_DATA)) nft_data_release(nft_set_ext_data(ext), set->dtype); if (nft_set_ext_exists(ext, NFT_SET_EXT_OBJREF)) - (*nft_set_ext_obj(ext))->use--; + nft_use_dec(&(*nft_set_ext_obj(ext))->use); } static int nft_del_setelem(struct nft_ctx *ctx, struct nft_set *set, @@ -4652,7 +4784,6 @@ static int nft_del_setelem(struct nft_ctx *ctx, struct nft_set *set, { struct nlattr *nla[NFTA_SET_ELEM_MAX + 1]; struct nft_set_ext_tmpl tmpl; - struct nft_data_desc desc; struct nft_set_elem elem; struct nft_set_ext *ext; struct nft_trans *trans; @@ -4663,11 +4794,10 @@ static int nft_del_setelem(struct nft_ctx *ctx, struct nft_set *set, err = nla_parse_nested(nla, NFTA_SET_ELEM_MAX, attr, nft_set_elem_policy, NULL); if (err < 0) - goto err1; + return err; - err = -EINVAL; if (nla[NFTA_SET_ELEM_KEY] == NULL) - goto err1; + return -EINVAL; nft_set_ext_prepare(&tmpl); @@ -4677,37 +4807,31 @@ static int nft_del_setelem(struct nft_ctx *ctx, struct nft_set *set, if (flags != 0) nft_set_ext_add(&tmpl, NFT_SET_EXT_FLAGS); - err = nft_data_init(ctx, &elem.key.val, sizeof(elem.key), &desc, - nla[NFTA_SET_ELEM_KEY]); + err = nft_setelem_parse_key(ctx, set, &elem.key.val, + nla[NFTA_SET_ELEM_KEY]); if (err < 0) - goto err1; - - err = -EINVAL; - if (desc.type != NFT_DATA_VALUE || desc.len != set->klen) - goto err2; + return err; - nft_set_ext_add_length(&tmpl, NFT_SET_EXT_KEY, desc.len); + nft_set_ext_add_length(&tmpl, NFT_SET_EXT_KEY, set->klen); err = -ENOMEM; elem.priv = nft_set_elem_init(set, &tmpl, elem.key.val.data, NULL, 0, GFP_KERNEL); if (elem.priv == NULL) - goto err2; + goto fail_elem; ext = nft_set_elem_ext(set, elem.priv); if (flags) *nft_set_ext_flags(ext) = flags; trans = nft_trans_elem_alloc(ctx, NFT_MSG_DELSETELEM, set); - if (trans == NULL) { - err = -ENOMEM; - goto err3; - } + if (trans == NULL) + goto fail_trans; priv = set->ops->deactivate(ctx->net, set, &elem); if (priv == NULL) { err = -ENOENT; - goto err4; + goto fail_ops; } kfree(elem.priv); elem.priv = priv; @@ -4715,16 +4839,15 @@ static int nft_del_setelem(struct nft_ctx *ctx, struct nft_set *set, nft_set_elem_deactivate(ctx->net, set, &elem); nft_trans_elem(trans) = elem; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; -err4: +fail_ops: kfree(trans); -err3: +fail_trans: kfree(elem.priv); -err2: - nft_data_release(&elem.key.val, desc.type); -err1: +fail_elem: + nft_data_release(&elem.key.val, NFT_DATA_VALUE); return err; } @@ -4750,7 +4873,7 @@ static int nft_flush_set(const struct nft_ctx *ctx, nft_set_elem_deactivate(ctx->net, set, elem); nft_trans_elem_set(trans) = set; nft_trans_elem(trans) = *elem; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; err1: @@ -4777,7 +4900,11 @@ static int nf_tables_delsetelem(struct net *net, struct sock *nlsk, set = nft_set_lookup(ctx.table, nla[NFTA_SET_ELEM_LIST_SET], genmask); if (IS_ERR(set)) return PTR_ERR(set); - if (!list_empty(&set->bindings) && set->flags & NFT_SET_CONSTANT) + + if (nft_set_is_anonymous(set)) + return -EOPNOTSUPP; + + if (!list_empty(&set->bindings) && (set->flags & NFT_SET_CONSTANT)) return -EBUSY; if (nla[NFTA_SET_ELEM_LIST_ELEMENTS] == NULL) { @@ -5048,9 +5175,14 @@ static int nf_tables_newobj(struct net *net, struct sock *nlsk, nft_ctx_init(&ctx, net, skb, nlh, family, table, NULL, nla); + if (!nft_use_inc(&table->use)) + return -EMFILE; + type = nft_obj_type_get(net, objtype); - if (IS_ERR(type)) - return PTR_ERR(type); + if (IS_ERR(type)) { + err = PTR_ERR(type); + goto err_type; + } obj = nft_obj_init(&ctx, type, nla[NFTA_OBJ_DATA]); if (IS_ERR(obj)) { @@ -5071,7 +5203,7 @@ static int nf_tables_newobj(struct net *net, struct sock *nlsk, goto err3; list_add_tail_rcu(&obj->list, &table->objects); - table->use++; + return 0; err3: kfree(obj->name); @@ -5081,6 +5213,9 @@ static int nf_tables_newobj(struct net *net, struct sock *nlsk, kfree(obj); err1: module_put(type->owner); +err_type: + nft_use_dec_restore(&table->use); + return err; } @@ -5089,19 +5224,14 @@ static int nf_tables_fill_obj_info(struct sk_buff *skb, struct net *net, int family, const struct nft_table *table, struct nft_object *obj, bool reset) { - struct nfgenmsg *nfmsg; struct nlmsghdr *nlh; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, family, + NFNETLINK_V0, nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); - if (nla_put_string(skb, NFTA_OBJ_TABLE, table->name) || nla_put_string(skb, NFTA_OBJ_NAME, obj->name) || nla_put_be32(skb, NFTA_OBJ_TYPE, htonl(obj->ops->type->type)) || @@ -5132,6 +5262,7 @@ static int nf_tables_dump_obj(struct sk_buff *skb, struct netlink_callback *cb) struct nft_obj_filter *filter = cb->data; struct net *net = sock_net(skb->sk); int family = nfmsg->nfgen_family; + struct nftables_pernet *nft_net; struct nft_object *obj; bool reset = false; @@ -5139,9 +5270,10 @@ static int nf_tables_dump_obj(struct sk_buff *skb, struct netlink_callback *cb) reset = true; rcu_read_lock(); - cb->seq = net->nft.base_seq; + nft_net = net_generic(net, nf_tables_net_id); + cb->seq = nft_net->base_seq; - list_for_each_entry_rcu(table, &net->nft.tables, list) { + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) continue; @@ -5419,6 +5551,23 @@ struct nft_flowtable *nft_flowtable_lookup(const struct nft_table *table, } EXPORT_SYMBOL_GPL(nft_flowtable_lookup); +void nf_tables_deactivate_flowtable(const struct nft_ctx *ctx, + struct nft_flowtable *flowtable, + enum nft_trans_phase phase) +{ + switch (phase) { + case NFT_TRANS_PREPARE_ERROR: + case NFT_TRANS_PREPARE: + case NFT_TRANS_ABORT: + case NFT_TRANS_RELEASE: + nft_use_dec(&flowtable->use); + /* fall through */ + default: + return; + } +} +EXPORT_SYMBOL_GPL(nf_tables_deactivate_flowtable); + static struct nft_flowtable * nft_flowtable_lookup_byhandle(const struct nft_table *table, const struct nlattr *nla, u8 genmask) @@ -5618,9 +5767,14 @@ static int nf_tables_newflowtable(struct net *net, struct sock *nlsk, nft_ctx_init(&ctx, net, skb, nlh, family, table, NULL, nla); + if (!nft_use_inc(&table->use)) + return -EMFILE; + flowtable = kzalloc(sizeof(*flowtable), GFP_KERNEL); - if (!flowtable) - return -ENOMEM; + if (!flowtable) { + err = -ENOMEM; + goto flowtable_alloc; + } flowtable->table = table; flowtable->handle = nf_tables_alloc_handle(table); @@ -5674,7 +5828,6 @@ static int nf_tables_newflowtable(struct net *net, struct sock *nlsk, goto err6; list_add_tail_rcu(&flowtable->list, &table->flowtables); - table->use++; return 0; err6: @@ -5692,6 +5845,9 @@ static int nf_tables_newflowtable(struct net *net, struct sock *nlsk, kfree(flowtable->name); err1: kfree(flowtable); +flowtable_alloc: + nft_use_dec_restore(&table->use); + return err; } @@ -5749,20 +5905,15 @@ static int nf_tables_fill_flowtable_info(struct sk_buff *skb, struct net *net, struct nft_flowtable *flowtable) { struct nlattr *nest, *nest_devs; - struct nfgenmsg *nfmsg; struct nlmsghdr *nlh; int i; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, family, + NFNETLINK_V0, nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); - if (nla_put_string(skb, NFTA_FLOWTABLE_TABLE, flowtable->table->name) || nla_put_string(skb, NFTA_FLOWTABLE_NAME, flowtable->name) || nla_put_be32(skb, NFTA_FLOWTABLE_USE, htonl(flowtable->use)) || @@ -5812,12 +5963,14 @@ static int nf_tables_dump_flowtable(struct sk_buff *skb, struct net *net = sock_net(skb->sk); int family = nfmsg->nfgen_family; struct nft_flowtable *flowtable; + struct nftables_pernet *nft_net; const struct nft_table *table; rcu_read_lock(); - cb->seq = net->nft.base_seq; + nft_net = net_generic(net, nf_tables_net_id); + cb->seq = nft_net->base_seq; - list_for_each_entry_rcu(table, &net->nft.tables, list) { + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) continue; @@ -5987,21 +6140,17 @@ static void nf_tables_flowtable_destroy(struct nft_flowtable *flowtable) static int nf_tables_fill_gen_info(struct sk_buff *skb, struct net *net, u32 portid, u32 seq) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; char buf[TASK_COMM_LEN]; int event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, NFT_MSG_NEWGEN); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), 0); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, 0, AF_UNSPEC, + NFNETLINK_V0, nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); - - if (nla_put_be32(skb, NFTA_GEN_ID, htonl(net->nft.base_seq)) || + if (nla_put_be32(skb, NFTA_GEN_ID, htonl(nft_net->base_seq)) || nla_put_be32(skb, NFTA_GEN_PROC_PID, htonl(task_pid_nr(current))) || nla_put_string(skb, NFTA_GEN_PROC_NAME, get_task_comm(buf, current))) goto nla_put_failure; @@ -6034,6 +6183,7 @@ static int nf_tables_flowtable_event(struct notifier_block *this, { struct net_device *dev = netdev_notifier_info_to_dev(ptr); struct nft_flowtable *flowtable; + struct nftables_pernet *nft_net; struct nft_table *table; struct net *net; @@ -6041,13 +6191,14 @@ static int nf_tables_flowtable_event(struct notifier_block *this, return 0; net = dev_net(dev); - mutex_lock(&net->nft.commit_mutex); - list_for_each_entry(table, &net->nft.tables, list) { + nft_net = net_generic(net, nf_tables_net_id); + mutex_lock(&nft_net->commit_mutex); + list_for_each_entry(table, &nft_net->tables, list) { list_for_each_entry(flowtable, &table->flowtables, list) { nft_flowtable_event(event, dev, flowtable); } } - mutex_unlock(&net->nft.commit_mutex); + mutex_unlock(&nft_net->commit_mutex); return NOTIFY_DONE; } @@ -6228,19 +6379,22 @@ static const struct nfnl_callback nf_tables_cb[NFT_MSG_MAX] = { static int nf_tables_validate(struct net *net) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nft_table *table; - switch (net->nft.validate_state) { + switch (nft_net->validate_state) { case NFT_VALIDATE_SKIP: break; case NFT_VALIDATE_NEED: nft_validate_state_update(net, NFT_VALIDATE_DO); /* fall through */ case NFT_VALIDATE_DO: - list_for_each_entry(table, &net->nft.tables, list) { + list_for_each_entry(table, &nft_net->tables, list) { if (nft_table_validate(net, table) < 0) return -EAGAIN; } + + nft_validate_state_update(net, NFT_VALIDATE_SKIP); break; } @@ -6312,15 +6466,16 @@ static void nft_commit_release(struct nft_trans *trans) static void nf_tables_commit_release(struct net *net) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nft_trans *trans, *next; - if (list_empty(&net->nft.commit_list)) + if (list_empty(&nft_net->commit_list)) return; synchronize_rcu(); - list_for_each_entry_safe(trans, next, &net->nft.commit_list, list) { - list_del(&trans->list); + list_for_each_entry_safe(trans, next, &nft_net->commit_list, list) { + nft_trans_list_del(trans); nft_commit_release(trans); } } @@ -6358,9 +6513,10 @@ static int nf_tables_commit_chain_prepare(struct net *net, struct nft_chain *cha static void nf_tables_commit_chain_prepare_cancel(struct net *net) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nft_trans *trans, *next; - list_for_each_entry_safe(trans, next, &net->nft.commit_list, list) { + list_for_each_entry_safe(trans, next, &nft_net->commit_list, list) { struct nft_chain *chain = trans->ctx.chain; if (trans->msg_type == NFT_MSG_NEWRULE || @@ -6452,17 +6608,30 @@ static void nft_chain_del(struct nft_chain *chain) static int nf_tables_commit(struct net *net, struct sk_buff *skb) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nft_trans *trans, *next; struct nft_trans_elem *te; struct nft_chain *chain; struct nft_table *table; + list_for_each_entry(trans, &nft_net->binding_list, binding_list) { + switch (trans->msg_type) { + case NFT_MSG_NEWSET: + if (nft_set_is_anonymous(nft_trans_set(trans)) && + !nft_trans_set_bound(trans)) { + pr_warn_once("nftables ruleset with unbound set\n"); + return -EINVAL; + } + break; + } + } + /* 0. Validate ruleset, otherwise roll back for error reporting. */ if (nf_tables_validate(net) < 0) return -EAGAIN; /* 1. Allocate space for next generation rules_gen_X[] */ - list_for_each_entry_safe(trans, next, &net->nft.commit_list, list) { + list_for_each_entry_safe(trans, next, &nft_net->commit_list, list) { int ret; if (trans->msg_type == NFT_MSG_NEWRULE || @@ -6478,7 +6647,7 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) } /* step 2. Make rules_gen_X visible to packet path */ - list_for_each_entry(table, &net->nft.tables, list) { + list_for_each_entry(table, &nft_net->tables, list) { list_for_each_entry(chain, &table->chains, list) nf_tables_commit_chain(net, chain); } @@ -6487,12 +6656,13 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) * Bump generation counter, invalidate any dump in progress. * Cannot fail after this point. */ - while (++net->nft.base_seq == 0); + while (++nft_net->base_seq == 0) + ; /* step 3. Start new generation, rules_gen_X now in use. */ net->nft.gencursor = nft_gencursor_next(net); - list_for_each_entry_safe(trans, next, &net->nft.commit_list, list) { + list_for_each_entry_safe(trans, next, &nft_net->commit_list, list) { switch (trans->msg_type) { case NFT_MSG_NEWTABLE: if (nft_trans_table_update(trans)) { @@ -6552,7 +6722,7 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) */ if (nft_set_is_anonymous(nft_trans_set(trans)) && !list_empty(&nft_trans_set(trans)->bindings)) - trans->ctx.table->use--; + nft_use_dec(&trans->ctx.table->use); nf_tables_set_notify(&trans->ctx, nft_trans_set(trans), NFT_MSG_NEWSET, GFP_KERNEL); @@ -6613,7 +6783,7 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) nf_tables_commit_release(net); nf_tables_gen_notify(net, skb, NFT_MSG_NEWGEN); - mutex_unlock(&net->nft.commit_mutex); + mutex_unlock(&nft_net->commit_mutex); return 0; } @@ -6649,10 +6819,11 @@ static void nf_tables_abort_release(struct nft_trans *trans) static int __nf_tables_abort(struct net *net) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nft_trans *trans, *next; struct nft_trans_elem *te; - list_for_each_entry_safe_reverse(trans, next, &net->nft.commit_list, + list_for_each_entry_safe_reverse(trans, next, &nft_net->commit_list, list) { switch (trans->msg_type) { case NFT_MSG_NEWTABLE: @@ -6677,7 +6848,7 @@ static int __nf_tables_abort(struct net *net) kfree(nft_trans_chain_name(trans)); nft_trans_destroy(trans); } else { - trans->ctx.table->use--; + nft_use_dec_restore(&trans->ctx.table->use); nft_chain_del(trans->ctx.chain); nf_tables_unregister_hook(trans->ctx.net, trans->ctx.table, @@ -6685,25 +6856,25 @@ static int __nf_tables_abort(struct net *net) } break; case NFT_MSG_DELCHAIN: - trans->ctx.table->use++; + nft_use_inc_restore(&trans->ctx.table->use); nft_clear(trans->ctx.net, trans->ctx.chain); nft_trans_destroy(trans); break; case NFT_MSG_NEWRULE: - trans->ctx.chain->use--; + nft_use_dec_restore(&trans->ctx.chain->use); list_del_rcu(&nft_trans_rule(trans)->list); nft_rule_expr_deactivate(&trans->ctx, nft_trans_rule(trans), NFT_TRANS_ABORT); break; case NFT_MSG_DELRULE: - trans->ctx.chain->use++; + nft_use_inc_restore(&trans->ctx.chain->use); nft_clear(trans->ctx.net, nft_trans_rule(trans)); nft_rule_expr_activate(&trans->ctx, nft_trans_rule(trans)); nft_trans_destroy(trans); break; case NFT_MSG_NEWSET: - trans->ctx.table->use--; + nft_use_dec_restore(&trans->ctx.table->use); if (nft_trans_set_bound(trans)) { nft_trans_destroy(trans); break; @@ -6711,7 +6882,7 @@ static int __nf_tables_abort(struct net *net) list_del_rcu(&nft_trans_set(trans)->list); break; case NFT_MSG_DELSET: - trans->ctx.table->use++; + nft_use_inc_restore(&trans->ctx.table->use); nft_clear(trans->ctx.net, nft_trans_set(trans)); nft_trans_destroy(trans); break; @@ -6734,22 +6905,22 @@ static int __nf_tables_abort(struct net *net) nft_trans_destroy(trans); break; case NFT_MSG_NEWOBJ: - trans->ctx.table->use--; + nft_use_dec_restore(&trans->ctx.table->use); list_del_rcu(&nft_trans_obj(trans)->list); break; case NFT_MSG_DELOBJ: - trans->ctx.table->use++; + nft_use_inc_restore(&trans->ctx.table->use); nft_clear(trans->ctx.net, nft_trans_obj(trans)); nft_trans_destroy(trans); break; case NFT_MSG_NEWFLOWTABLE: - trans->ctx.table->use--; + nft_use_dec_restore(&trans->ctx.table->use); list_del_rcu(&nft_trans_flowtable(trans)->list); nft_unregister_flowtable_net_hooks(net, nft_trans_flowtable(trans)); break; case NFT_MSG_DELFLOWTABLE: - trans->ctx.table->use++; + nft_use_inc_restore(&trans->ctx.table->use); nft_clear(trans->ctx.net, nft_trans_flowtable(trans)); nft_trans_destroy(trans); break; @@ -6759,37 +6930,34 @@ static int __nf_tables_abort(struct net *net) synchronize_rcu(); list_for_each_entry_safe_reverse(trans, next, - &net->nft.commit_list, list) { - list_del(&trans->list); + &nft_net->commit_list, list) { + nft_trans_list_del(trans); nf_tables_abort_release(trans); } return 0; } -static void nf_tables_cleanup(struct net *net) -{ - nft_validate_state_update(net, NFT_VALIDATE_SKIP); -} - static int nf_tables_abort(struct net *net, struct sk_buff *skb) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); int ret = __nf_tables_abort(net); - mutex_unlock(&net->nft.commit_mutex); + mutex_unlock(&nft_net->commit_mutex); return ret; } static bool nf_tables_valid_genid(struct net *net, u32 genid) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); bool genid_ok; - mutex_lock(&net->nft.commit_mutex); + mutex_lock(&nft_net->commit_mutex); - genid_ok = genid == 0 || net->nft.base_seq == genid; + genid_ok = genid == 0 || nft_net->base_seq == genid; if (!genid_ok) - mutex_unlock(&net->nft.commit_mutex); + mutex_unlock(&nft_net->commit_mutex); /* else, commit mutex has to be released by commit or abort function */ return genid_ok; @@ -6802,7 +6970,6 @@ static const struct nfnetlink_subsystem nf_tables_subsys = { .cb = nf_tables_cb, .commit = nf_tables_commit, .abort = nf_tables_abort, - .cleanup = nf_tables_cleanup, .valid_genid = nf_tables_valid_genid, .owner = THIS_MODULE, }; @@ -6964,28 +7131,24 @@ int nft_parse_u32_check(const struct nlattr *attr, int max, u32 *dest) } EXPORT_SYMBOL_GPL(nft_parse_u32_check); -/** - * nft_parse_register - parse a register value from a netlink attribute - * - * @attr: netlink attribute - * - * Parse and translate a register value from a netlink attribute. - * Registers used to be 128 bit wide, these register numbers will be - * mapped to the corresponding 32 bit register numbers. - */ -unsigned int nft_parse_register(const struct nlattr *attr) +static int nft_parse_register(const struct nlattr *attr, u32 *preg) { unsigned int reg; reg = ntohl(nla_get_be32(attr)); switch (reg) { case NFT_REG_VERDICT...NFT_REG_4: - return reg * NFT_REG_SIZE / NFT_REG32_SIZE; + *preg = reg * NFT_REG_SIZE / NFT_REG32_SIZE; + break; + case NFT_REG32_00...NFT_REG32_15: + *preg = reg + NFT_REG_SIZE / NFT_REG32_SIZE - NFT_REG32_00; + break; default: - return reg + NFT_REG_SIZE / NFT_REG32_SIZE - NFT_REG32_00; + return -ERANGE; } + + return 0; } -EXPORT_SYMBOL_GPL(nft_parse_register); /** * nft_dump_register - dump a register value to a netlink attribute @@ -7018,7 +7181,7 @@ EXPORT_SYMBOL_GPL(nft_dump_register); * Validate that the input register is one of the general purpose * registers and that the length of the load is within the bounds. */ -int nft_validate_register_load(enum nft_registers reg, unsigned int len) +static int nft_validate_register_load(enum nft_registers reg, unsigned int len) { if (reg < NFT_REG_1 * NFT_REG_SIZE / NFT_REG32_SIZE) return -EINVAL; @@ -7029,7 +7192,24 @@ int nft_validate_register_load(enum nft_registers reg, unsigned int len) return 0; } -EXPORT_SYMBOL_GPL(nft_validate_register_load); + +int nft_parse_register_load(const struct nlattr *attr, u8 *sreg, u32 len) +{ + u32 reg; + int err; + + err = nft_parse_register(attr, ®); + if (err < 0) + return err; + + err = nft_validate_register_load(reg, len); + if (err < 0) + return err; + + *sreg = reg; + return 0; +} +EXPORT_SYMBOL_GPL(nft_parse_register_load); /** * nft_validate_register_store - validate an expressions' register store @@ -7045,10 +7225,11 @@ EXPORT_SYMBOL_GPL(nft_validate_register_load); * A value of NULL for the data means that its runtime gathered * data. */ -int nft_validate_register_store(const struct nft_ctx *ctx, - enum nft_registers reg, - const struct nft_data *data, - enum nft_data_types type, unsigned int len) +static int nft_validate_register_store(const struct nft_ctx *ctx, + enum nft_registers reg, + const struct nft_data *data, + enum nft_data_types type, + unsigned int len) { int err; @@ -7080,7 +7261,27 @@ int nft_validate_register_store(const struct nft_ctx *ctx, return 0; } } -EXPORT_SYMBOL_GPL(nft_validate_register_store); + +int nft_parse_register_store(const struct nft_ctx *ctx, + const struct nlattr *attr, u8 *dreg, + const struct nft_data *data, + enum nft_data_types type, unsigned int len) +{ + int err; + u32 reg; + + err = nft_parse_register(attr, ®); + if (err < 0) + return err; + + err = nft_validate_register_store(ctx, reg, data, type, len); + if (err < 0) + return err; + + *dreg = reg; + return 0; +} +EXPORT_SYMBOL_GPL(nft_parse_register_store); static const struct nla_policy nft_verdict_policy[NFTA_VERDICT_MAX + 1] = { [NFTA_VERDICT_CODE] = { .type = NLA_U32 }, @@ -7103,6 +7304,9 @@ static int nft_verdict_init(const struct nft_ctx *ctx, struct nft_data *data, if (!tb[NFTA_VERDICT_CODE]) return -EINVAL; + + /* zero padding hole for memcmp */ + memset(data, 0, sizeof(*data)); data->verdict.code = ntohl(nla_get_be32(tb[NFTA_VERDICT_CODE])); switch (data->verdict.code) { @@ -7130,8 +7334,9 @@ static int nft_verdict_init(const struct nft_ctx *ctx, struct nft_data *data, return PTR_ERR(chain); if (nft_is_base_chain(chain)) return -EOPNOTSUPP; + if (!nft_use_inc(&chain->use)) + return -EMFILE; - chain->use++; data->verdict.chain = chain; break; } @@ -7143,10 +7348,13 @@ static int nft_verdict_init(const struct nft_ctx *ctx, struct nft_data *data, static void nft_verdict_uninit(const struct nft_data *data) { + struct nft_chain *chain; + switch (data->verdict.code) { case NFT_JUMP: case NFT_GOTO: - data->verdict.chain->use--; + chain = data->verdict.chain; + nft_use_dec(&chain->use); break; } } @@ -7299,21 +7507,20 @@ int __nft_release_basechain(struct nft_ctx *ctx) nf_tables_unregister_hook(ctx->net, ctx->chain->table, ctx->chain); list_for_each_entry_safe(rule, nr, &ctx->chain->rules, list) { list_del(&rule->list); - ctx->chain->use--; + nft_use_dec(&ctx->chain->use); nf_tables_rule_release(ctx, rule); } nft_chain_del(ctx->chain); - ctx->table->use--; + nft_use_dec(&ctx->table->use); nf_tables_chain_destroy(ctx); return 0; } EXPORT_SYMBOL_GPL(__nft_release_basechain); -static void __nft_release_tables(struct net *net) +static void __nft_release_table(struct net *net, struct nft_table *table) { struct nft_flowtable *flowtable, *nf; - struct nft_table *table, *nt; struct nft_chain *chain, *nc; struct nft_object *obj, *ne; struct nft_rule *rule, *nr; @@ -7323,71 +7530,85 @@ static void __nft_release_tables(struct net *net) .family = NFPROTO_NETDEV, }; - list_for_each_entry_safe(table, nt, &net->nft.tables, list) { - ctx.family = table->family; + ctx.family = table->family; - list_for_each_entry(chain, &table->chains, list) - nf_tables_unregister_hook(net, table, chain); - /* No packets are walking on these chains anymore. */ - ctx.table = table; - list_for_each_entry(chain, &table->chains, list) { - ctx.chain = chain; - list_for_each_entry_safe(rule, nr, &chain->rules, list) { - list_del(&rule->list); - chain->use--; - nf_tables_rule_release(&ctx, rule); - } - } - list_for_each_entry_safe(flowtable, nf, &table->flowtables, list) { - list_del(&flowtable->list); - table->use--; - nf_tables_flowtable_destroy(flowtable); - } - list_for_each_entry_safe(set, ns, &table->sets, list) { - list_del(&set->list); - table->use--; - nft_set_destroy(set); - } - list_for_each_entry_safe(obj, ne, &table->objects, list) { - list_del(&obj->list); - table->use--; - nft_obj_destroy(&ctx, obj); - } - list_for_each_entry_safe(chain, nc, &table->chains, list) { - ctx.chain = chain; - nft_chain_del(chain); - table->use--; - nf_tables_chain_destroy(&ctx); + list_for_each_entry(chain, &table->chains, list) + nf_tables_unregister_hook(net, table, chain); + /* No packets are walking on these chains anymore. */ + ctx.table = table; + list_for_each_entry(chain, &table->chains, list) { + ctx.chain = chain; + list_for_each_entry_safe(rule, nr, &chain->rules, list) { + list_del(&rule->list); + nft_use_dec(&chain->use); + nf_tables_rule_release(&ctx, rule); } - list_del(&table->list); - nf_tables_table_destroy(&ctx); } + list_for_each_entry_safe(flowtable, nf, &table->flowtables, list) { + list_del(&flowtable->list); + nft_use_dec(&table->use); + nf_tables_flowtable_destroy(flowtable); + } + list_for_each_entry_safe(set, ns, &table->sets, list) { + list_del(&set->list); + nft_use_dec(&table->use); + nft_set_destroy(set); + } + list_for_each_entry_safe(obj, ne, &table->objects, list) { + list_del(&obj->list); + nft_use_dec(&table->use); + nft_obj_destroy(&ctx, obj); + } + list_for_each_entry_safe(chain, nc, &table->chains, list) { + ctx.chain = chain; + nft_chain_del(chain); + nft_use_dec(&table->use); + nf_tables_chain_destroy(&ctx); + } + list_del(&table->list); + nf_tables_table_destroy(&ctx); +} + +static void __nft_release_tables(struct net *net) +{ + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); + struct nft_table *table, *nt; + + list_for_each_entry_safe(table, nt, &nft_net->tables, list) + __nft_release_table(net, table); } static int __net_init nf_tables_init_net(struct net *net) { - INIT_LIST_HEAD(&net->nft.tables); - INIT_LIST_HEAD(&net->nft.commit_list); - mutex_init(&net->nft.commit_mutex); - net->nft.base_seq = 1; - net->nft.validate_state = NFT_VALIDATE_SKIP; + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); + + INIT_LIST_HEAD(&nft_net->tables); + INIT_LIST_HEAD(&nft_net->commit_list); + INIT_LIST_HEAD(&nft_net->binding_list); + mutex_init(&nft_net->commit_mutex); + nft_net->base_seq = 1; + nft_net->validate_state = NFT_VALIDATE_SKIP; return 0; } static void __net_exit nf_tables_exit_net(struct net *net) { - mutex_lock(&net->nft.commit_mutex); - if (!list_empty(&net->nft.commit_list)) + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); + + mutex_lock(&nft_net->commit_mutex); + if (!list_empty(&nft_net->commit_list)) __nf_tables_abort(net); __nft_release_tables(net); - mutex_unlock(&net->nft.commit_mutex); - WARN_ON_ONCE(!list_empty(&net->nft.tables)); + mutex_unlock(&nft_net->commit_mutex); + WARN_ON_ONCE(!list_empty(&nft_net->tables)); } static struct pernet_operations nf_tables_net_ops = { .init = nf_tables_init_net, .exit = nf_tables_exit_net, + .id = &nf_tables_net_id, + .size = sizeof(struct nftables_pernet), }; static int __init nf_tables_module_init(void) diff --git a/net/netfilter/nf_tables_trace.c b/net/netfilter/nf_tables_trace.c index e1dc527a493b8ba38b9fbea1a20d9a405613d50c..7a19c517b19184003c8f0592b3f2cc3da5be52d2 100644 --- a/net/netfilter/nf_tables_trace.c +++ b/net/netfilter/nf_tables_trace.c @@ -186,7 +186,6 @@ static bool nft_trace_have_verdict_chain(struct nft_traceinfo *info) void nft_trace_notify(struct nft_traceinfo *info) { const struct nft_pktinfo *pkt = info->pkt; - struct nfgenmsg *nfmsg; struct nlmsghdr *nlh; struct sk_buff *skb; unsigned int size; @@ -222,15 +221,11 @@ void nft_trace_notify(struct nft_traceinfo *info) return; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, NFT_MSG_TRACE); - nlh = nlmsg_put(skb, 0, 0, event, sizeof(struct nfgenmsg), 0); + nlh = nfnl_msg_put(skb, 0, 0, event, 0, info->basechain->type->family, + NFNETLINK_V0, 0); if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = info->basechain->type->family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_be32(skb, NFTA_TRACE_NFPROTO, htonl(nft_pf(pkt)))) goto nla_put_failure; diff --git a/net/netfilter/nfnetlink.c b/net/netfilter/nfnetlink.c index 9bacddc761ba42560c43e452fffb4657ff2f97be..0267be2e9cfe887cf5e1565aaa77f7e1320e60e7 100644 --- a/net/netfilter/nfnetlink.c +++ b/net/netfilter/nfnetlink.c @@ -452,7 +452,8 @@ static void nfnetlink_rcv_batch(struct sk_buff *skb, struct nlmsghdr *nlh, * processed, this avoids that the same error is * reported several times when replaying the batch. */ - if (nfnl_err_add(&err_list, nlh, err, &extack) < 0) { + if (err == -ENOMEM || + nfnl_err_add(&err_list, nlh, err, &extack) < 0) { /* We failed to enqueue an error, reset the * list of errors and send OOM to userspace * pointing to the batch header. @@ -495,8 +496,6 @@ static void nfnetlink_rcv_batch(struct sk_buff *skb, struct nlmsghdr *nlh, } else { ss->abort(net, oskb); } - if (ss->cleanup) - ss->cleanup(net); nfnl_err_deliver(&err_list, oskb); kfree_skb(skb); diff --git a/net/netfilter/nfnetlink_acct.c b/net/netfilter/nfnetlink_acct.c index 8fa8bf7c48e642344af5c695f998457aae1c6e7c..7c5f428dc5c91d18c9e9ddf2022b1d9c5999db3c 100644 --- a/net/netfilter/nfnetlink_acct.c +++ b/net/netfilter/nfnetlink_acct.c @@ -135,21 +135,16 @@ nfnl_acct_fill_info(struct sk_buff *skb, u32 portid, u32 seq, u32 type, int event, struct nf_acct *acct) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0; u64 pkts, bytes; u32 old_flags; event = nfnl_msg_type(NFNL_SUBSYS_ACCT, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_string(skb, NFACCT_NAME, acct->name)) goto nla_put_failure; diff --git a/net/netfilter/nfnetlink_cthelper.c b/net/netfilter/nfnetlink_cthelper.c index c8b0f1122c44d43293cae94ad5225d52c00c3480..720177721e3c0432252a438ab5eb79c5e8c26fda 100644 --- a/net/netfilter/nfnetlink_cthelper.c +++ b/net/netfilter/nfnetlink_cthelper.c @@ -532,20 +532,15 @@ nfnl_cthelper_fill_info(struct sk_buff *skb, u32 portid, u32 seq, u32 type, int event, struct nf_conntrack_helper *helper) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0; int status; event = nfnl_msg_type(NFNL_SUBSYS_CTHELPER, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_string(skb, NFCTH_NAME, helper->name)) goto nla_put_failure; diff --git a/net/netfilter/nfnetlink_cttimeout.c b/net/netfilter/nfnetlink_cttimeout.c index 70a7382b9787ce980d3a7cca3d1e8271a1cb747c..ae01e9ad5546465e68c6419530f6aced290e92d3 100644 --- a/net/netfilter/nfnetlink_cttimeout.c +++ b/net/netfilter/nfnetlink_cttimeout.c @@ -164,20 +164,15 @@ ctnl_timeout_fill_info(struct sk_buff *skb, u32 portid, u32 seq, u32 type, int event, struct ctnl_timeout *timeout) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0; const struct nf_conntrack_l4proto *l4proto = timeout->timeout.l4proto; event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK_TIMEOUT, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_string(skb, CTA_TIMEOUT_NAME, timeout->name) || nla_put_be16(skb, CTA_TIMEOUT_L3PROTO, htons(timeout->timeout.l3num)) || @@ -396,19 +391,14 @@ cttimeout_default_fill_info(struct net *net, struct sk_buff *skb, u32 portid, const unsigned int *timeouts) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0; event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK_TIMEOUT, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_be16(skb, CTA_TIMEOUT_L3PROTO, htons(l4proto->l3proto)) || nla_put_u8(skb, CTA_TIMEOUT_L4PROTO, l4proto->l4proto)) goto nla_put_failure; diff --git a/net/netfilter/nfnetlink_log.c b/net/netfilter/nfnetlink_log.c index 17ca9a681d47bbefa9334df9bed56f44fb22c6f6..1735bcb07381c739d3b3784d0aa98b8775e24b55 100644 --- a/net/netfilter/nfnetlink_log.c +++ b/net/netfilter/nfnetlink_log.c @@ -404,20 +404,15 @@ __build_packet_message(struct nfnl_log_net *log, { struct nfulnl_msg_packet_hdr pmsg; struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; sk_buff_data_t old_tail = inst->skb->tail; struct sock *sk; const unsigned char *hwhdrp; - nlh = nlmsg_put(inst->skb, 0, 0, - nfnl_msg_type(NFNL_SUBSYS_ULOG, NFULNL_MSG_PACKET), - sizeof(struct nfgenmsg), 0); + nlh = nfnl_msg_put(inst->skb, 0, 0, + nfnl_msg_type(NFNL_SUBSYS_ULOG, NFULNL_MSG_PACKET), + 0, pf, NFNETLINK_V0, htons(inst->group_num)); if (!nlh) return -1; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = pf; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(inst->group_num); memset(&pmsg, 0, sizeof(pmsg)); pmsg.hw_protocol = skb->protocol; @@ -636,8 +631,8 @@ nfulnl_log_packet(struct net *net, unsigned int plen = 0; struct nfnl_log_net *log = nfnl_log_pernet(net); const struct nfnl_ct_hook *nfnl_ct = NULL; + enum ip_conntrack_info ctinfo = 0; struct nf_conn *ct = NULL; - enum ip_conntrack_info uninitialized_var(ctinfo); if (li_user && li_user->type == NF_LOG_TYPE_ULOG) li = li_user; diff --git a/net/netfilter/nfnetlink_osf.c b/net/netfilter/nfnetlink_osf.c index 917f06110c823bdaa6c6420c6ebea04b6f163ed9..f3676238e64f2c45a7a7447b3f719cf4070bb3bb 100644 --- a/net/netfilter/nfnetlink_osf.c +++ b/net/netfilter/nfnetlink_osf.c @@ -318,6 +318,14 @@ static int nfnl_osf_add_callback(struct net *net, struct sock *ctnl, f = nla_data(osf_attrs[OSF_ATTR_FINGER]); + if (f->opt_num > ARRAY_SIZE(f->opt)) + return -EINVAL; + + if (!memchr(f->genre, 0, MAXGENRELEN) || + !memchr(f->subtype, 0, MAXGENRELEN) || + !memchr(f->version, 0, MAXGENRELEN)) + return -EINVAL; + kf = kmalloc(sizeof(struct nf_osf_finger), GFP_KERNEL); if (!kf) return -ENOMEM; @@ -442,3 +450,4 @@ module_init(nfnl_osf_init); module_exit(nfnl_osf_fini); MODULE_LICENSE("GPL"); +MODULE_ALIAS_NFNL_SUBSYS(NFNL_SUBSYS_OSF); diff --git a/net/netfilter/nfnetlink_queue.c b/net/netfilter/nfnetlink_queue.c index cd496b074a71bd9aed9d787c8d5449978113c2d5..1aacc31a6bf926fc7c054d3533f6619edfb4c5c6 100644 --- a/net/netfilter/nfnetlink_queue.c +++ b/net/netfilter/nfnetlink_queue.c @@ -387,12 +387,11 @@ nfqnl_build_packet_message(struct net *net, struct nfqnl_instance *queue, struct nlattr *nla; struct nfqnl_msg_packet_hdr *pmsg; struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; struct sk_buff *entskb = entry->skb; struct net_device *indev; struct net_device *outdev; struct nf_conn *ct = NULL; - enum ip_conntrack_info uninitialized_var(ctinfo); + enum ip_conntrack_info ctinfo; struct nfnl_ct_hook *nfnl_ct; bool csum_verify; char *secdata = NULL; @@ -473,18 +472,15 @@ nfqnl_build_packet_message(struct net *net, struct nfqnl_instance *queue, goto nlmsg_failure; } - nlh = nlmsg_put(skb, 0, 0, - nfnl_msg_type(NFNL_SUBSYS_QUEUE, NFQNL_MSG_PACKET), - sizeof(struct nfgenmsg), 0); + nlh = nfnl_msg_put(skb, 0, 0, + nfnl_msg_type(NFNL_SUBSYS_QUEUE, NFQNL_MSG_PACKET), + 0, entry->state.pf, NFNETLINK_V0, + htons(queue->queue_num)); if (!nlh) { skb_tx_error(entskb); kfree_skb(skb); goto nlmsg_failure; } - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = entry->state.pf; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(queue->queue_num); nla = __nla_reserve(skb, NFQA_PACKET_HDR, sizeof(*pmsg)); pmsg = nla_data(nla); @@ -1191,7 +1187,7 @@ static int nfqnl_recv_verdict(struct net *net, struct sock *ctnl, struct nfqnl_instance *queue; unsigned int verdict; struct nf_queue_entry *entry; - enum ip_conntrack_info uninitialized_var(ctinfo); + enum ip_conntrack_info ctinfo; struct nfnl_ct_hook *nfnl_ct; struct nf_conn *ct = NULL; struct nfnl_queue_net *q = nfnl_queue_pernet(net); diff --git a/net/netfilter/nft_bitwise.c b/net/netfilter/nft_bitwise.c index 058ee84ea531bddc3b6049a964ea76da33a4f6a7..c1055251ebdebf0f7414a715e3a0286e53f1069e 100644 --- a/net/netfilter/nft_bitwise.c +++ b/net/netfilter/nft_bitwise.c @@ -18,8 +18,8 @@ #include struct nft_bitwise { - enum nft_registers sreg:8; - enum nft_registers dreg:8; + u8 sreg; + u8 dreg; u8 len; struct nft_data mask; struct nft_data xor; @@ -68,14 +68,14 @@ static int nft_bitwise_init(const struct nft_ctx *ctx, priv->len = len; - priv->sreg = nft_parse_register(tb[NFTA_BITWISE_SREG]); - err = nft_validate_register_load(priv->sreg, priv->len); + err = nft_parse_register_load(tb[NFTA_BITWISE_SREG], &priv->sreg, + priv->len); if (err < 0) return err; - priv->dreg = nft_parse_register(tb[NFTA_BITWISE_DREG]); - err = nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, priv->len); + err = nft_parse_register_store(ctx, tb[NFTA_BITWISE_DREG], + &priv->dreg, NULL, NFT_DATA_VALUE, + priv->len); if (err < 0) return err; diff --git a/net/netfilter/nft_byteorder.c b/net/netfilter/nft_byteorder.c index 13d4e421a6b33ccc44ff3c70ab6bb9c38d256822..dba16126c7eec9758f6416b1e1e5d6cd0e3e1f66 100644 --- a/net/netfilter/nft_byteorder.c +++ b/net/netfilter/nft_byteorder.c @@ -19,8 +19,8 @@ #include struct nft_byteorder { - enum nft_registers sreg:8; - enum nft_registers dreg:8; + u8 sreg; + u8 dreg; enum nft_byteorder_ops op:8; u8 len; u8 size; @@ -33,11 +33,11 @@ static void nft_byteorder_eval(const struct nft_expr *expr, const struct nft_byteorder *priv = nft_expr_priv(expr); u32 *src = ®s->data[priv->sreg]; u32 *dst = ®s->data[priv->dreg]; - union { u32 u32; u16 u16; } *s, *d; + u16 *s16, *d16; unsigned int i; - s = (void *)src; - d = (void *)dst; + s16 = (void *)src; + d16 = (void *)dst; switch (priv->size) { case 8: { @@ -63,11 +63,11 @@ static void nft_byteorder_eval(const struct nft_expr *expr, switch (priv->op) { case NFT_BYTEORDER_NTOH: for (i = 0; i < priv->len / 4; i++) - d[i].u32 = ntohl((__force __be32)s[i].u32); + dst[i] = ntohl((__force __be32)src[i]); break; case NFT_BYTEORDER_HTON: for (i = 0; i < priv->len / 4; i++) - d[i].u32 = (__force __u32)htonl(s[i].u32); + dst[i] = (__force __u32)htonl(src[i]); break; } break; @@ -75,11 +75,11 @@ static void nft_byteorder_eval(const struct nft_expr *expr, switch (priv->op) { case NFT_BYTEORDER_NTOH: for (i = 0; i < priv->len / 2; i++) - d[i].u16 = ntohs((__force __be16)s[i].u16); + d16[i] = ntohs((__force __be16)s16[i]); break; case NFT_BYTEORDER_HTON: for (i = 0; i < priv->len / 2; i++) - d[i].u16 = (__force __u16)htons(s[i].u16); + d16[i] = (__force __u16)htons(s16[i]); break; } break; @@ -133,20 +133,20 @@ static int nft_byteorder_init(const struct nft_ctx *ctx, return -EINVAL; } - priv->sreg = nft_parse_register(tb[NFTA_BYTEORDER_SREG]); err = nft_parse_u32_check(tb[NFTA_BYTEORDER_LEN], U8_MAX, &len); if (err < 0) return err; priv->len = len; - err = nft_validate_register_load(priv->sreg, priv->len); + err = nft_parse_register_load(tb[NFTA_BYTEORDER_SREG], &priv->sreg, + priv->len); if (err < 0) return err; - priv->dreg = nft_parse_register(tb[NFTA_BYTEORDER_DREG]); - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, priv->len); + return nft_parse_register_store(ctx, tb[NFTA_BYTEORDER_DREG], + &priv->dreg, NULL, NFT_DATA_VALUE, + priv->len); } static int nft_byteorder_dump(struct sk_buff *skb, const struct nft_expr *expr) diff --git a/net/netfilter/nft_chain_filter.c b/net/netfilter/nft_chain_filter.c index 3fd540b2c6baf0cdf934d5b3ac12e140651e1e56..a308d45ee95e119691ede1697cef379c2e910ceb 100644 --- a/net/netfilter/nft_chain_filter.c +++ b/net/netfilter/nft_chain_filter.c @@ -2,6 +2,7 @@ #include #include #include +#include #include #include #include @@ -10,6 +11,8 @@ #include #include +extern unsigned int nf_tables_net_id; + #ifdef CONFIG_NF_TABLES_IPV4 static unsigned int nft_do_chain_ipv4(void *priv, struct sk_buff *skb, @@ -315,6 +318,7 @@ static int nf_tables_netdev_event(struct notifier_block *this, unsigned long event, void *ptr) { struct net_device *dev = netdev_notifier_info_to_dev(ptr); + struct nftables_pernet *nft_net; struct nft_table *table; struct nft_chain *chain, *nr; struct nft_ctx ctx = { @@ -325,8 +329,9 @@ static int nf_tables_netdev_event(struct notifier_block *this, event != NETDEV_CHANGENAME) return NOTIFY_DONE; - mutex_lock(&ctx.net->nft.commit_mutex); - list_for_each_entry(table, &ctx.net->nft.tables, list) { + nft_net = net_generic(ctx.net, nf_tables_net_id); + mutex_lock(&nft_net->commit_mutex); + list_for_each_entry(table, &nft_net->tables, list) { if (table->family != NFPROTO_NETDEV) continue; @@ -340,7 +345,7 @@ static int nf_tables_netdev_event(struct notifier_block *this, nft_netdev_event(event, dev, &ctx); } } - mutex_unlock(&ctx.net->nft.commit_mutex); + mutex_unlock(&nft_net->commit_mutex); return NOTIFY_DONE; } diff --git a/net/netfilter/nft_cmp.c b/net/netfilter/nft_cmp.c index 7007045c08498d887d761add943033d8d26c0672..36bf64ebc89262b9b180fc87f3815ab23e515f01 100644 --- a/net/netfilter/nft_cmp.c +++ b/net/netfilter/nft_cmp.c @@ -19,7 +19,7 @@ struct nft_cmp_expr { struct nft_data data; - enum nft_registers sreg:8; + u8 sreg; u8 len; enum nft_cmp_ops op:8; }; @@ -88,8 +88,7 @@ static int nft_cmp_init(const struct nft_ctx *ctx, const struct nft_expr *expr, return err; } - priv->sreg = nft_parse_register(tb[NFTA_CMP_SREG]); - err = nft_validate_register_load(priv->sreg, desc.len); + err = nft_parse_register_load(tb[NFTA_CMP_SREG], &priv->sreg, desc.len); if (err < 0) return err; @@ -139,8 +138,7 @@ static int nft_cmp_fast_init(const struct nft_ctx *ctx, if (err < 0) return err; - priv->sreg = nft_parse_register(tb[NFTA_CMP_SREG]); - err = nft_validate_register_load(priv->sreg, desc.len); + err = nft_parse_register_load(tb[NFTA_CMP_SREG], &priv->sreg, desc.len); if (err < 0) return err; diff --git a/net/netfilter/nft_compat.c b/net/netfilter/nft_compat.c index 469f9da5073bf61ea7ac50ea02deeea4b4400d15..2846d64659f2fe3afaae5c2c799c2f4ddecba228 100644 --- a/net/netfilter/nft_compat.c +++ b/net/netfilter/nft_compat.c @@ -575,19 +575,14 @@ nfnl_compat_fill_info(struct sk_buff *skb, u32 portid, u32 seq, u32 type, int rev, int target) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0; event = nfnl_msg_type(NFNL_SUBSYS_NFT_COMPAT, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, family, + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_string(skb, NFTA_COMPAT_NAME, name) || nla_put_be32(skb, NFTA_COMPAT_REV, htonl(rev)) || nla_put_be32(skb, NFTA_COMPAT_TYPE, htonl(target))) diff --git a/net/netfilter/nft_ct.c b/net/netfilter/nft_ct.c index 5dd87748afa8a9185de95c439881f72d3f96e798..f29f02805bcc0a4709574eb9af2cf59d11dcc6dd 100644 --- a/net/netfilter/nft_ct.c +++ b/net/netfilter/nft_ct.c @@ -29,8 +29,8 @@ struct nft_ct { enum nft_ct_keys key:8; enum ip_conntrack_dir dir:8; union { - enum nft_registers dreg:8; - enum nft_registers sreg:8; + u8 dreg; + u8 sreg; }; }; @@ -486,9 +486,8 @@ static int nft_ct_get_init(const struct nft_ctx *ctx, } } - priv->dreg = nft_parse_register(tb[NFTA_CT_DREG]); - err = nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, len); + err = nft_parse_register_store(ctx, tb[NFTA_CT_DREG], &priv->dreg, NULL, + NFT_DATA_VALUE, len); if (err < 0) return err; @@ -581,8 +580,7 @@ static int nft_ct_set_init(const struct nft_ctx *ctx, } } - priv->sreg = nft_parse_register(tb[NFTA_CT_SREG]); - err = nft_validate_register_load(priv->sreg, len); + err = nft_parse_register_load(tb[NFTA_CT_SREG], &priv->sreg, len); if (err < 0) goto err1; diff --git a/net/netfilter/nft_dup_netdev.c b/net/netfilter/nft_dup_netdev.c index 2cc1e0ef56e88f0ac960cc4ae891bda7e93da8c8..e862f916efa096a54cee05ea8351fa1c971637bf 100644 --- a/net/netfilter/nft_dup_netdev.c +++ b/net/netfilter/nft_dup_netdev.c @@ -16,7 +16,7 @@ #include struct nft_dup_netdev { - enum nft_registers sreg_dev:8; + u8 sreg_dev; }; static void nft_dup_netdev_eval(const struct nft_expr *expr, @@ -42,8 +42,8 @@ static int nft_dup_netdev_init(const struct nft_ctx *ctx, if (tb[NFTA_DUP_SREG_DEV] == NULL) return -EINVAL; - priv->sreg_dev = nft_parse_register(tb[NFTA_DUP_SREG_DEV]); - return nft_validate_register_load(priv->sreg_dev, sizeof(int)); + return nft_parse_register_load(tb[NFTA_DUP_SREG_DEV], &priv->sreg_dev, + sizeof(int)); } static const struct nft_expr_ops nft_dup_netdev_ingress_ops; diff --git a/net/netfilter/nft_dynset.c b/net/netfilter/nft_dynset.c index cc076d535e145db2ce2401748adb00d4c24fad42..a4c6aba7da7ee03fc38b886688dc1fbc6c254958 100644 --- a/net/netfilter/nft_dynset.c +++ b/net/netfilter/nft_dynset.c @@ -15,13 +15,16 @@ #include #include #include +#include + +extern unsigned int nf_tables_net_id; struct nft_dynset { struct nft_set *set; struct nft_set_ext_tmpl tmpl; enum nft_dynset_ops op:8; - enum nft_registers sreg_key:8; - enum nft_registers sreg_data:8; + u8 sreg_key; + u8 sreg_data; bool invert; u64 timeout; struct nft_expr *expr; @@ -112,13 +115,14 @@ static int nft_dynset_init(const struct nft_ctx *ctx, const struct nft_expr *expr, const struct nlattr * const tb[]) { + struct nftables_pernet *nft_net = net_generic(ctx->net, nf_tables_net_id); struct nft_dynset *priv = nft_expr_priv(expr); u8 genmask = nft_genmask_next(ctx->net); struct nft_set *set; u64 timeout; int err; - lockdep_assert_held(&ctx->net->nft.commit_mutex); + lockdep_assert_held(&nft_net->commit_mutex); if (tb[NFTA_DYNSET_SET_NAME] == NULL || tb[NFTA_DYNSET_OP] == NULL || @@ -140,6 +144,9 @@ static int nft_dynset_init(const struct nft_ctx *ctx, if (IS_ERR(set)) return PTR_ERR(set); + if (set->flags & NFT_SET_OBJECT) + return -EOPNOTSUPP; + if (set->ops->update == NULL) return -EOPNOTSUPP; @@ -166,8 +173,8 @@ static int nft_dynset_init(const struct nft_ctx *ctx, tb[NFTA_DYNSET_TIMEOUT]))); } - priv->sreg_key = nft_parse_register(tb[NFTA_DYNSET_SREG_KEY]); - err = nft_validate_register_load(priv->sreg_key, set->klen); + err = nft_parse_register_load(tb[NFTA_DYNSET_SREG_KEY], &priv->sreg_key, + set->klen); if (err < 0) return err; @@ -177,8 +184,8 @@ static int nft_dynset_init(const struct nft_ctx *ctx, if (set->dtype == NFT_DATA_VERDICT) return -EOPNOTSUPP; - priv->sreg_data = nft_parse_register(tb[NFTA_DYNSET_SREG_DATA]); - err = nft_validate_register_load(priv->sreg_data, set->dlen); + err = nft_parse_register_load(tb[NFTA_DYNSET_SREG_DATA], + &priv->sreg_data, set->dlen); if (err < 0) return err; } else if (set->flags & NFT_SET_MAP) @@ -248,7 +255,7 @@ static void nft_dynset_activate(const struct nft_ctx *ctx, { struct nft_dynset *priv = nft_expr_priv(expr); - priv->set->use++; + nf_tables_activate_set(ctx, priv->set); } static void nft_dynset_destroy(const struct nft_ctx *ctx, diff --git a/net/netfilter/nft_exthdr.c b/net/netfilter/nft_exthdr.c index 93fee410601924ebcd48c92587bd03f3166f8b67..8d0f14cd7cc3eea12bbacc31b4d907788505dbb1 100644 --- a/net/netfilter/nft_exthdr.c +++ b/net/netfilter/nft_exthdr.c @@ -22,8 +22,8 @@ struct nft_exthdr { u8 offset; u8 len; u8 op; - enum nft_registers dreg:8; - enum nft_registers sreg:8; + u8 dreg; + u8 sreg; u8 flags; }; @@ -258,12 +258,12 @@ static int nft_exthdr_init(const struct nft_ctx *ctx, priv->type = nla_get_u8(tb[NFTA_EXTHDR_TYPE]); priv->offset = offset; priv->len = len; - priv->dreg = nft_parse_register(tb[NFTA_EXTHDR_DREG]); priv->flags = flags; priv->op = op; - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, priv->len); + return nft_parse_register_store(ctx, tb[NFTA_EXTHDR_DREG], + &priv->dreg, NULL, NFT_DATA_VALUE, + priv->len); } static int nft_exthdr_tcp_set_init(const struct nft_ctx *ctx, @@ -308,11 +308,11 @@ static int nft_exthdr_tcp_set_init(const struct nft_ctx *ctx, priv->type = nla_get_u8(tb[NFTA_EXTHDR_TYPE]); priv->offset = offset; priv->len = len; - priv->sreg = nft_parse_register(tb[NFTA_EXTHDR_SREG]); priv->flags = flags; priv->op = op; - return nft_validate_register_load(priv->sreg, priv->len); + return nft_parse_register_load(tb[NFTA_EXTHDR_SREG], &priv->sreg, + priv->len); } static int nft_exthdr_dump_common(struct sk_buff *skb, const struct nft_exthdr *priv) diff --git a/net/netfilter/nft_fib.c b/net/netfilter/nft_fib.c index 21df8cccea6582e56d7bfbb6fba21f821b7c56d9..ce6891337304d01dd94eb4ed24d103a5ffded4ba 100644 --- a/net/netfilter/nft_fib.c +++ b/net/netfilter/nft_fib.c @@ -88,7 +88,6 @@ int nft_fib_init(const struct nft_ctx *ctx, const struct nft_expr *expr, return -EINVAL; priv->result = ntohl(nla_get_be32(tb[NFTA_FIB_RESULT])); - priv->dreg = nft_parse_register(tb[NFTA_FIB_DREG]); switch (priv->result) { case NFT_FIB_RESULT_OIF: @@ -108,8 +107,8 @@ int nft_fib_init(const struct nft_ctx *ctx, const struct nft_expr *expr, return -EINVAL; } - err = nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, len); + err = nft_parse_register_store(ctx, tb[NFTA_FIB_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, len); if (err < 0) return err; diff --git a/net/netfilter/nft_flow_offload.c b/net/netfilter/nft_flow_offload.c index 166edea0e45273b91d8a6cd6298c685de285bf86..ec35a41c7262405b5b86393dbcf0350f2f24fea4 100644 --- a/net/netfilter/nft_flow_offload.c +++ b/net/netfilter/nft_flow_offload.c @@ -169,18 +169,34 @@ static int nft_flow_offload_init(const struct nft_ctx *ctx, if (IS_ERR(flowtable)) return PTR_ERR(flowtable); + if (!nft_use_inc(&flowtable->use)) + return -EMFILE; + priv->flowtable = flowtable; - flowtable->use++; return nf_ct_netns_get(ctx->net, ctx->family); } -static void nft_flow_offload_destroy(const struct nft_ctx *ctx, - const struct nft_expr *expr) +static void nft_flow_offload_deactivate(const struct nft_ctx *ctx, + const struct nft_expr *expr, + enum nft_trans_phase phase) { struct nft_flow_offload *priv = nft_expr_priv(expr); - priv->flowtable->use--; + nf_tables_deactivate_flowtable(ctx, priv->flowtable, phase); +} + +static void nft_flow_offload_activate(const struct nft_ctx *ctx, + const struct nft_expr *expr) +{ + struct nft_flow_offload *priv = nft_expr_priv(expr); + + nft_use_inc_restore(&priv->flowtable->use); +} + +static void nft_flow_offload_destroy(const struct nft_ctx *ctx, + const struct nft_expr *expr) +{ nf_ct_netns_put(ctx->net, ctx->family); } @@ -203,6 +219,8 @@ static const struct nft_expr_ops nft_flow_offload_ops = { .size = NFT_EXPR_SIZE(sizeof(struct nft_flow_offload)), .eval = nft_flow_offload_eval, .init = nft_flow_offload_init, + .activate = nft_flow_offload_activate, + .deactivate = nft_flow_offload_deactivate, .destroy = nft_flow_offload_destroy, .validate = nft_flow_offload_validate, .dump = nft_flow_offload_dump, diff --git a/net/netfilter/nft_fwd_netdev.c b/net/netfilter/nft_fwd_netdev.c index 10a12e0949299aac433531370d67eb8748c63fee..2efbe78de3b223aa4e65ec4e728528a0d7f4b9a4 100644 --- a/net/netfilter/nft_fwd_netdev.c +++ b/net/netfilter/nft_fwd_netdev.c @@ -20,7 +20,7 @@ #include struct nft_fwd_netdev { - enum nft_registers sreg_dev:8; + u8 sreg_dev; }; static void nft_fwd_netdev_eval(const struct nft_expr *expr, @@ -49,8 +49,8 @@ static int nft_fwd_netdev_init(const struct nft_ctx *ctx, if (tb[NFTA_FWD_SREG_DEV] == NULL) return -EINVAL; - priv->sreg_dev = nft_parse_register(tb[NFTA_FWD_SREG_DEV]); - return nft_validate_register_load(priv->sreg_dev, sizeof(int)); + return nft_parse_register_load(tb[NFTA_FWD_SREG_DEV], &priv->sreg_dev, + sizeof(int)); } static const struct nft_expr_ops nft_fwd_netdev_ingress_ops; @@ -69,8 +69,8 @@ static int nft_fwd_netdev_dump(struct sk_buff *skb, const struct nft_expr *expr) } struct nft_fwd_neigh { - enum nft_registers sreg_dev:8; - enum nft_registers sreg_addr:8; + u8 sreg_dev; + u8 sreg_addr; u8 nfproto; }; @@ -148,8 +148,6 @@ static int nft_fwd_neigh_init(const struct nft_ctx *ctx, !tb[NFTA_FWD_NFPROTO]) return -EINVAL; - priv->sreg_dev = nft_parse_register(tb[NFTA_FWD_SREG_DEV]); - priv->sreg_addr = nft_parse_register(tb[NFTA_FWD_SREG_ADDR]); priv->nfproto = ntohl(nla_get_be32(tb[NFTA_FWD_NFPROTO])); switch (priv->nfproto) { @@ -163,11 +161,13 @@ static int nft_fwd_neigh_init(const struct nft_ctx *ctx, return -EOPNOTSUPP; } - err = nft_validate_register_load(priv->sreg_dev, sizeof(int)); + err = nft_parse_register_load(tb[NFTA_FWD_SREG_DEV], &priv->sreg_dev, + sizeof(int)); if (err < 0) return err; - return nft_validate_register_load(priv->sreg_addr, addr_len); + return nft_parse_register_load(tb[NFTA_FWD_SREG_ADDR], &priv->sreg_addr, + addr_len); } static const struct nft_expr_ops nft_fwd_netdev_ingress_ops; diff --git a/net/netfilter/nft_hash.c b/net/netfilter/nft_hash.c index b8f23f75aea6cbe96bf627c030d39e50539596ad..513419aca9c66bc2b5a65939b724e5f30ce88f1e 100644 --- a/net/netfilter/nft_hash.c +++ b/net/netfilter/nft_hash.c @@ -18,8 +18,8 @@ #include struct nft_jhash { - enum nft_registers sreg:8; - enum nft_registers dreg:8; + u8 sreg; + u8 dreg; u8 len; bool autogen_seed:1; u32 modulus; @@ -65,7 +65,7 @@ static void nft_jhash_map_eval(const struct nft_expr *expr, } struct nft_symhash { - enum nft_registers dreg:8; + u8 dreg; u32 modulus; u32 offset; struct nft_set *map; @@ -136,9 +136,6 @@ static int nft_jhash_init(const struct nft_ctx *ctx, if (tb[NFTA_HASH_OFFSET]) priv->offset = ntohl(nla_get_be32(tb[NFTA_HASH_OFFSET])); - priv->sreg = nft_parse_register(tb[NFTA_HASH_SREG]); - priv->dreg = nft_parse_register(tb[NFTA_HASH_DREG]); - err = nft_parse_u32_check(tb[NFTA_HASH_LEN], U8_MAX, &len); if (err < 0) return err; @@ -147,6 +144,10 @@ static int nft_jhash_init(const struct nft_ctx *ctx, priv->len = len; + err = nft_parse_register_load(tb[NFTA_HASH_SREG], &priv->sreg, len); + if (err < 0) + return err; + priv->modulus = ntohl(nla_get_be32(tb[NFTA_HASH_MODULUS])); if (priv->modulus < 1) return -ERANGE; @@ -161,9 +162,8 @@ static int nft_jhash_init(const struct nft_ctx *ctx, get_random_bytes(&priv->seed, sizeof(priv->seed)); } - return nft_validate_register_load(priv->sreg, len) && - nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, sizeof(u32)); + return nft_parse_register_store(ctx, tb[NFTA_HASH_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, sizeof(u32)); } static int nft_jhash_map_init(const struct nft_ctx *ctx, @@ -193,8 +193,6 @@ static int nft_symhash_init(const struct nft_ctx *ctx, if (tb[NFTA_HASH_OFFSET]) priv->offset = ntohl(nla_get_be32(tb[NFTA_HASH_OFFSET])); - priv->dreg = nft_parse_register(tb[NFTA_HASH_DREG]); - priv->modulus = ntohl(nla_get_be32(tb[NFTA_HASH_MODULUS])); if (priv->modulus < 1) return -ERANGE; @@ -202,8 +200,9 @@ static int nft_symhash_init(const struct nft_ctx *ctx, if (priv->offset + priv->modulus - 1 < priv->offset) return -EOVERFLOW; - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, sizeof(u32)); + return nft_parse_register_store(ctx, tb[NFTA_HASH_DREG], + &priv->dreg, NULL, NFT_DATA_VALUE, + sizeof(u32)); } static int nft_symhash_map_init(const struct nft_ctx *ctx, diff --git a/net/netfilter/nft_immediate.c b/net/netfilter/nft_immediate.c index 3f6d1d2a628186c964e79727bbb62fb59370b919..af4e2a4bce93ef9aa5132d2633a71c5148236739 100644 --- a/net/netfilter/nft_immediate.c +++ b/net/netfilter/nft_immediate.c @@ -50,9 +50,9 @@ static int nft_immediate_init(const struct nft_ctx *ctx, priv->dlen = desc.len; - priv->dreg = nft_parse_register(tb[NFTA_IMMEDIATE_DREG]); - err = nft_validate_register_store(ctx, priv->dreg, &priv->data, - desc.type, desc.len); + err = nft_parse_register_store(ctx, tb[NFTA_IMMEDIATE_DREG], + &priv->dreg, &priv->data, desc.type, + desc.len); if (err < 0) goto err1; diff --git a/net/netfilter/nft_lookup.c b/net/netfilter/nft_lookup.c index 55754d9939b50a3e8e3829c165d9911a75c9e275..3c380fb32651148f9b4eab338df093f1fd3623d2 100644 --- a/net/netfilter/nft_lookup.c +++ b/net/netfilter/nft_lookup.c @@ -20,8 +20,8 @@ struct nft_lookup { struct nft_set *set; - enum nft_registers sreg:8; - enum nft_registers dreg:8; + u8 sreg; + u8 dreg; bool invert; struct nft_set_binding binding; }; @@ -76,8 +76,8 @@ static int nft_lookup_init(const struct nft_ctx *ctx, if (IS_ERR(set)) return PTR_ERR(set); - priv->sreg = nft_parse_register(tb[NFTA_LOOKUP_SREG]); - err = nft_validate_register_load(priv->sreg, set->klen); + err = nft_parse_register_load(tb[NFTA_LOOKUP_SREG], &priv->sreg, + set->klen); if (err < 0) return err; @@ -100,9 +100,9 @@ static int nft_lookup_init(const struct nft_ctx *ctx, if (!(set->flags & NFT_SET_MAP)) return -EINVAL; - priv->dreg = nft_parse_register(tb[NFTA_LOOKUP_DREG]); - err = nft_validate_register_store(ctx, priv->dreg, NULL, - set->dtype, set->dlen); + err = nft_parse_register_store(ctx, tb[NFTA_LOOKUP_DREG], + &priv->dreg, NULL, set->dtype, + set->dlen); if (err < 0) return err; } else if (set->flags & NFT_SET_MAP) @@ -132,7 +132,7 @@ static void nft_lookup_activate(const struct nft_ctx *ctx, { struct nft_lookup *priv = nft_expr_priv(expr); - priv->set->use++; + nf_tables_activate_set(ctx, priv->set); } static void nft_lookup_destroy(const struct nft_ctx *ctx, diff --git a/net/netfilter/nft_masq.c b/net/netfilter/nft_masq.c index 9d8655bc1bea6cde7c029477b4a974499dba4d82..4ecfebc2fdc4a808c829025e798e37da5b54ac40 100644 --- a/net/netfilter/nft_masq.c +++ b/net/netfilter/nft_masq.c @@ -53,19 +53,15 @@ int nft_masq_init(const struct nft_ctx *ctx, } if (tb[NFTA_MASQ_REG_PROTO_MIN]) { - priv->sreg_proto_min = - nft_parse_register(tb[NFTA_MASQ_REG_PROTO_MIN]); - - err = nft_validate_register_load(priv->sreg_proto_min, plen); + err = nft_parse_register_load(tb[NFTA_MASQ_REG_PROTO_MIN], + &priv->sreg_proto_min, plen); if (err < 0) return err; if (tb[NFTA_MASQ_REG_PROTO_MAX]) { - priv->sreg_proto_max = - nft_parse_register(tb[NFTA_MASQ_REG_PROTO_MAX]); - - err = nft_validate_register_load(priv->sreg_proto_max, - plen); + err = nft_parse_register_load(tb[NFTA_MASQ_REG_PROTO_MAX], + &priv->sreg_proto_max, + plen); if (err < 0) return err; } else { diff --git a/net/netfilter/nft_meta.c b/net/netfilter/nft_meta.c index 297fe7d97c182ffbcbfb15c94f10bdec633f1149..061a29bd3066194959507226786384b6da540aa3 100644 --- a/net/netfilter/nft_meta.c +++ b/net/netfilter/nft_meta.c @@ -30,8 +30,8 @@ struct nft_meta { enum nft_meta_keys key:8; union { - enum nft_registers dreg:8; - enum nft_registers sreg:8; + u8 dreg; + u8 sreg; }; }; @@ -358,9 +358,8 @@ static int nft_meta_get_init(const struct nft_ctx *ctx, return -EOPNOTSUPP; } - priv->dreg = nft_parse_register(tb[NFTA_META_DREG]); - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, len); + return nft_parse_register_store(ctx, tb[NFTA_META_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, len); } static int nft_meta_get_validate(const struct nft_ctx *ctx, @@ -448,8 +447,7 @@ static int nft_meta_set_init(const struct nft_ctx *ctx, return -EOPNOTSUPP; } - priv->sreg = nft_parse_register(tb[NFTA_META_SREG]); - err = nft_validate_register_load(priv->sreg, len); + err = nft_parse_register_load(tb[NFTA_META_SREG], &priv->sreg, len); if (err < 0) return err; diff --git a/net/netfilter/nft_nat.c b/net/netfilter/nft_nat.c index 2c3d7ff6f58a73dd897efebd0cbf60362384a131..aa6149cc8c87c383513912fcb76893bf14daaf15 100644 --- a/net/netfilter/nft_nat.c +++ b/net/netfilter/nft_nat.c @@ -27,10 +27,10 @@ #include struct nft_nat { - enum nft_registers sreg_addr_min:8; - enum nft_registers sreg_addr_max:8; - enum nft_registers sreg_proto_min:8; - enum nft_registers sreg_proto_max:8; + u8 sreg_addr_min; + u8 sreg_addr_max; + u8 sreg_proto_min; + u8 sreg_proto_max; enum nf_nat_manip_type type:8; u8 family; u16 flags; @@ -160,18 +160,15 @@ static int nft_nat_init(const struct nft_ctx *ctx, const struct nft_expr *expr, priv->family = family; if (tb[NFTA_NAT_REG_ADDR_MIN]) { - priv->sreg_addr_min = - nft_parse_register(tb[NFTA_NAT_REG_ADDR_MIN]); - err = nft_validate_register_load(priv->sreg_addr_min, alen); + err = nft_parse_register_load(tb[NFTA_NAT_REG_ADDR_MIN], + &priv->sreg_addr_min, alen); if (err < 0) return err; if (tb[NFTA_NAT_REG_ADDR_MAX]) { - priv->sreg_addr_max = - nft_parse_register(tb[NFTA_NAT_REG_ADDR_MAX]); - - err = nft_validate_register_load(priv->sreg_addr_max, - alen); + err = nft_parse_register_load(tb[NFTA_NAT_REG_ADDR_MAX], + &priv->sreg_addr_max, + alen); if (err < 0) return err; } else { @@ -181,19 +178,15 @@ static int nft_nat_init(const struct nft_ctx *ctx, const struct nft_expr *expr, plen = FIELD_SIZEOF(struct nf_nat_range, min_addr.all); if (tb[NFTA_NAT_REG_PROTO_MIN]) { - priv->sreg_proto_min = - nft_parse_register(tb[NFTA_NAT_REG_PROTO_MIN]); - - err = nft_validate_register_load(priv->sreg_proto_min, plen); + err = nft_parse_register_load(tb[NFTA_NAT_REG_PROTO_MIN], + &priv->sreg_proto_min, plen); if (err < 0) return err; if (tb[NFTA_NAT_REG_PROTO_MAX]) { - priv->sreg_proto_max = - nft_parse_register(tb[NFTA_NAT_REG_PROTO_MAX]); - - err = nft_validate_register_load(priv->sreg_proto_max, - plen); + err = nft_parse_register_load(tb[NFTA_NAT_REG_PROTO_MAX], + &priv->sreg_proto_max, + plen); if (err < 0) return err; } else { diff --git a/net/netfilter/nft_numgen.c b/net/netfilter/nft_numgen.c index 3cc1b3dc3c3cdb2508cef7825f3bd9c485679fdb..8ff82f17ecba9a849a9ce1b597cb3278c73700d5 100644 --- a/net/netfilter/nft_numgen.c +++ b/net/netfilter/nft_numgen.c @@ -20,7 +20,7 @@ static DEFINE_PER_CPU(struct rnd_state, nft_numgen_prandom_state); struct nft_ng_inc { - enum nft_registers dreg:8; + u8 dreg; u32 modulus; atomic_t counter; u32 offset; @@ -70,11 +70,10 @@ static int nft_ng_inc_init(const struct nft_ctx *ctx, if (priv->offset + priv->modulus - 1 < priv->offset) return -EOVERFLOW; - priv->dreg = nft_parse_register(tb[NFTA_NG_DREG]); atomic_set(&priv->counter, priv->modulus - 1); - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, sizeof(u32)); + return nft_parse_register_store(ctx, tb[NFTA_NG_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, sizeof(u32)); } static int nft_ng_dump(struct sk_buff *skb, enum nft_registers dreg, @@ -104,7 +103,7 @@ static int nft_ng_inc_dump(struct sk_buff *skb, const struct nft_expr *expr) } struct nft_ng_random { - enum nft_registers dreg:8; + u8 dreg; u32 modulus; u32 offset; }; @@ -144,10 +143,8 @@ static int nft_ng_random_init(const struct nft_ctx *ctx, prandom_init_once(&nft_numgen_prandom_state); - priv->dreg = nft_parse_register(tb[NFTA_NG_DREG]); - - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, sizeof(u32)); + return nft_parse_register_store(ctx, tb[NFTA_NG_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, sizeof(u32)); } static int nft_ng_random_dump(struct sk_buff *skb, const struct nft_expr *expr) diff --git a/net/netfilter/nft_objref.c b/net/netfilter/nft_objref.c index bf92a40dd1b2dc62cf027424453c2b7baee84904..2401e9fa17c4fb3f4cb60760c5ff289bbda6d706 100644 --- a/net/netfilter/nft_objref.c +++ b/net/netfilter/nft_objref.c @@ -43,8 +43,10 @@ static int nft_objref_init(const struct nft_ctx *ctx, if (IS_ERR(obj)) return -ENOENT; + if (!nft_use_inc(&obj->use)) + return -EMFILE; + nft_objref_priv(expr) = obj; - obj->use++; return 0; } @@ -73,7 +75,7 @@ static void nft_objref_deactivate(const struct nft_ctx *ctx, if (phase == NFT_TRANS_COMMIT) return; - obj->use--; + nft_use_dec(&obj->use); } static void nft_objref_activate(const struct nft_ctx *ctx, @@ -81,7 +83,7 @@ static void nft_objref_activate(const struct nft_ctx *ctx, { struct nft_object *obj = nft_objref_priv(expr); - obj->use++; + nft_use_inc_restore(&obj->use); } static struct nft_expr_type nft_objref_type; @@ -97,7 +99,7 @@ static const struct nft_expr_ops nft_objref_ops = { struct nft_objref_map { struct nft_set *set; - enum nft_registers sreg:8; + u8 sreg; struct nft_set_binding binding; }; @@ -139,8 +141,8 @@ static int nft_objref_map_init(const struct nft_ctx *ctx, if (!(set->flags & NFT_SET_OBJECT)) return -EINVAL; - priv->sreg = nft_parse_register(tb[NFTA_OBJREF_SET_SREG]); - err = nft_validate_register_load(priv->sreg, set->klen); + err = nft_parse_register_load(tb[NFTA_OBJREF_SET_SREG], &priv->sreg, + set->klen); if (err < 0) return err; @@ -182,7 +184,7 @@ static void nft_objref_map_activate(const struct nft_ctx *ctx, { struct nft_objref_map *priv = nft_expr_priv(expr); - priv->set->use++; + nf_tables_activate_set(ctx, priv->set); } static void nft_objref_map_destroy(const struct nft_ctx *ctx, diff --git a/net/netfilter/nft_osf.c b/net/netfilter/nft_osf.c index 4fac2d9a4b8858a10e1316d15f851e0d2b18dad2..af2ce7a8c5877d512be08ddc34c4ceceedea8ba2 100644 --- a/net/netfilter/nft_osf.c +++ b/net/netfilter/nft_osf.c @@ -5,7 +5,7 @@ #include struct nft_osf { - enum nft_registers dreg:8; + u8 dreg; }; static const struct nla_policy nft_osf_policy[NFTA_OSF_MAX + 1] = { @@ -55,9 +55,9 @@ static int nft_osf_init(const struct nft_ctx *ctx, if (!tb[NFTA_OSF_DREG]) return -EINVAL; - priv->dreg = nft_parse_register(tb[NFTA_OSF_DREG]); - err = nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, NFT_OSF_MAXGENRELEN); + err = nft_parse_register_store(ctx, tb[NFTA_OSF_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, + NFT_OSF_MAXGENRELEN); if (err < 0) return err; diff --git a/net/netfilter/nft_payload.c b/net/netfilter/nft_payload.c index 5732b32ab9320075f3dd92a223eed537c9d02074..0ef51c81ec94cf79a9fd58c849f3532070b7cf2e 100644 --- a/net/netfilter/nft_payload.c +++ b/net/netfilter/nft_payload.c @@ -84,7 +84,7 @@ static void nft_payload_eval(const struct nft_expr *expr, switch (priv->base) { case NFT_PAYLOAD_LL_HEADER: - if (!skb_mac_header_was_set(skb)) + if (!skb_mac_header_was_set(skb) || skb_mac_header_len(skb) == 0) goto err; if (skb_vlan_tag_present(skb)) { @@ -135,10 +135,10 @@ static int nft_payload_init(const struct nft_ctx *ctx, priv->base = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_BASE])); priv->offset = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_OFFSET])); priv->len = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_LEN])); - priv->dreg = nft_parse_register(tb[NFTA_PAYLOAD_DREG]); - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, priv->len); + return nft_parse_register_store(ctx, tb[NFTA_PAYLOAD_DREG], + &priv->dreg, NULL, NFT_DATA_VALUE, + priv->len); } static int nft_payload_dump(struct sk_buff *skb, const struct nft_expr *expr) @@ -338,7 +338,6 @@ static int nft_payload_set_init(const struct nft_ctx *ctx, priv->base = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_BASE])); priv->offset = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_OFFSET])); priv->len = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_LEN])); - priv->sreg = nft_parse_register(tb[NFTA_PAYLOAD_SREG]); if (tb[NFTA_PAYLOAD_CSUM_TYPE]) csum_type = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_CSUM_TYPE])); @@ -369,7 +368,8 @@ static int nft_payload_set_init(const struct nft_ctx *ctx, } priv->csum_type = csum_type; - return nft_validate_register_load(priv->sreg, priv->len); + return nft_parse_register_load(tb[NFTA_PAYLOAD_SREG], &priv->sreg, + priv->len); } static int nft_payload_set_dump(struct sk_buff *skb, const struct nft_expr *expr) diff --git a/net/netfilter/nft_queue.c b/net/netfilter/nft_queue.c index 98613658d4ac5ce359e946efca4c93d9df216817..de5f1bda9d6f1dd60e3303e055418bdc6d30c72f 100644 --- a/net/netfilter/nft_queue.c +++ b/net/netfilter/nft_queue.c @@ -22,10 +22,10 @@ static u32 jhash_initval __read_mostly; struct nft_queue { - enum nft_registers sreg_qnum:8; - u16 queuenum; - u16 queues_total; - u16 flags; + u8 sreg_qnum; + u16 queuenum; + u16 queues_total; + u16 flags; }; static void nft_queue_eval(const struct nft_expr *expr, @@ -114,8 +114,8 @@ static int nft_queue_sreg_init(const struct nft_ctx *ctx, struct nft_queue *priv = nft_expr_priv(expr); int err; - priv->sreg_qnum = nft_parse_register(tb[NFTA_QUEUE_SREG_QNUM]); - err = nft_validate_register_load(priv->sreg_qnum, sizeof(u32)); + err = nft_parse_register_load(tb[NFTA_QUEUE_SREG_QNUM], + &priv->sreg_qnum, sizeof(u32)); if (err < 0) return err; diff --git a/net/netfilter/nft_range.c b/net/netfilter/nft_range.c index 2e1d2ec2f52a486c392c714bd24c4ab0e1b8f5b9..a5f74e5b8184f1935ad009f94c5c42f3fd374f4e 100644 --- a/net/netfilter/nft_range.c +++ b/net/netfilter/nft_range.c @@ -18,7 +18,7 @@ struct nft_range_expr { struct nft_data data_from; struct nft_data data_to; - enum nft_registers sreg:8; + u8 sreg; u8 len; enum nft_range_ops op:8; }; @@ -90,8 +90,8 @@ static int nft_range_init(const struct nft_ctx *ctx, const struct nft_expr *expr goto err2; } - priv->sreg = nft_parse_register(tb[NFTA_RANGE_SREG]); - err = nft_validate_register_load(priv->sreg, desc_from.len); + err = nft_parse_register_load(tb[NFTA_RANGE_SREG], &priv->sreg, + desc_from.len); if (err < 0) goto err2; diff --git a/net/netfilter/nft_redir.c b/net/netfilter/nft_redir.c index c64cbe78dee7bcb5b0036c6cd8fe66aceb3e004a..08a05bd1e817822f91d5e502114b7794170907f6 100644 --- a/net/netfilter/nft_redir.c +++ b/net/netfilter/nft_redir.c @@ -49,19 +49,15 @@ int nft_redir_init(const struct nft_ctx *ctx, plen = FIELD_SIZEOF(struct nf_nat_range, min_addr.all); if (tb[NFTA_REDIR_REG_PROTO_MIN]) { - priv->sreg_proto_min = - nft_parse_register(tb[NFTA_REDIR_REG_PROTO_MIN]); - - err = nft_validate_register_load(priv->sreg_proto_min, plen); + err = nft_parse_register_load(tb[NFTA_REDIR_REG_PROTO_MIN], + &priv->sreg_proto_min, plen); if (err < 0) return err; if (tb[NFTA_REDIR_REG_PROTO_MAX]) { - priv->sreg_proto_max = - nft_parse_register(tb[NFTA_REDIR_REG_PROTO_MAX]); - - err = nft_validate_register_load(priv->sreg_proto_max, - plen); + err = nft_parse_register_load(tb[NFTA_REDIR_REG_PROTO_MAX], + &priv->sreg_proto_max, + plen); if (err < 0) return err; } else { diff --git a/net/netfilter/nft_rt.c b/net/netfilter/nft_rt.c index 76dba9f6b6f627de7de1ada08320cc2ed5a12b24..edce109ef4b01ed0589d0609fdad2acd98dadf06 100644 --- a/net/netfilter/nft_rt.c +++ b/net/netfilter/nft_rt.c @@ -18,7 +18,7 @@ struct nft_rt { enum nft_rt_keys key:8; - enum nft_registers dreg:8; + u8 dreg; }; static u16 get_tcpmss(const struct nft_pktinfo *pkt, const struct dst_entry *skbdst) @@ -134,9 +134,8 @@ static int nft_rt_get_init(const struct nft_ctx *ctx, return -EOPNOTSUPP; } - priv->dreg = nft_parse_register(tb[NFTA_RT_DREG]); - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, len); + return nft_parse_register_store(ctx, tb[NFTA_RT_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, len); } static int nft_rt_get_dump(struct sk_buff *skb, diff --git a/net/netfilter/nft_set_rbtree.c b/net/netfilter/nft_set_rbtree.c index 78a0f428378703128b8b3106bb23fa2e45a28194..9c7ec2ec1fcfea416674d5be70c0848ab95b117f 100644 --- a/net/netfilter/nft_set_rbtree.c +++ b/net/netfilter/nft_set_rbtree.c @@ -326,6 +326,8 @@ static void *nft_rbtree_deactivate(const struct net *net, nft_rbtree_interval_end(this)) { parent = parent->rb_right; continue; + } else if (nft_set_elem_expired(&rbe->ext)) { + break; } else if (!nft_set_elem_active(&rbe->ext, genmask)) { parent = parent->rb_left; continue; diff --git a/net/netfilter/nft_socket.c b/net/netfilter/nft_socket.c index 4026ec38526f69e4902c6ad3a38e8e6983ce3b42..7e4f7063f4811d83b065cbba34fe5504917db2bf 100644 --- a/net/netfilter/nft_socket.c +++ b/net/netfilter/nft_socket.c @@ -10,7 +10,7 @@ struct nft_socket { enum nft_socket_keys key:8; union { - enum nft_registers dreg:8; + u8 dreg; }; }; @@ -119,9 +119,8 @@ static int nft_socket_init(const struct nft_ctx *ctx, return -EOPNOTSUPP; } - priv->dreg = nft_parse_register(tb[NFTA_SOCKET_DREG]); - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, len); + return nft_parse_register_store(ctx, tb[NFTA_SOCKET_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, len); } static int nft_socket_dump(struct sk_buff *skb, diff --git a/net/netfilter/nft_tproxy.c b/net/netfilter/nft_tproxy.c index a0e30bf4a845c0dc0eb9795dfd02987a61a7df5d..db780b5985abc9b5c75c1fff342f7e059b074e61 100644 --- a/net/netfilter/nft_tproxy.c +++ b/net/netfilter/nft_tproxy.c @@ -13,9 +13,9 @@ #endif struct nft_tproxy { - enum nft_registers sreg_addr:8; - enum nft_registers sreg_port:8; - u8 family; + u8 sreg_addr; + u8 sreg_port; + u8 family; }; static void nft_tproxy_eval_v4(const struct nft_expr *expr, @@ -254,15 +254,15 @@ static int nft_tproxy_init(const struct nft_ctx *ctx, } if (tb[NFTA_TPROXY_REG_ADDR]) { - priv->sreg_addr = nft_parse_register(tb[NFTA_TPROXY_REG_ADDR]); - err = nft_validate_register_load(priv->sreg_addr, alen); + err = nft_parse_register_load(tb[NFTA_TPROXY_REG_ADDR], + &priv->sreg_addr, alen); if (err < 0) return err; } if (tb[NFTA_TPROXY_REG_PORT]) { - priv->sreg_port = nft_parse_register(tb[NFTA_TPROXY_REG_PORT]); - err = nft_validate_register_load(priv->sreg_port, sizeof(u16)); + err = nft_parse_register_load(tb[NFTA_TPROXY_REG_PORT], + &priv->sreg_port, sizeof(u16)); if (err < 0) return err; } diff --git a/net/netfilter/nft_tunnel.c b/net/netfilter/nft_tunnel.c index 3fc55c81f16ac8b3be9aa199e8962e73bfc914db..ab69a34210a8dbc1e385e54e3470faa2dfc64834 100644 --- a/net/netfilter/nft_tunnel.c +++ b/net/netfilter/nft_tunnel.c @@ -14,7 +14,7 @@ struct nft_tunnel { enum nft_tunnel_keys key:8; - enum nft_registers dreg:8; + u8 dreg; }; static void nft_tunnel_get_eval(const struct nft_expr *expr, @@ -72,10 +72,8 @@ static int nft_tunnel_get_init(const struct nft_ctx *ctx, return -EOPNOTSUPP; } - priv->dreg = nft_parse_register(tb[NFTA_TUNNEL_DREG]); - - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, len); + return nft_parse_register_store(ctx, tb[NFTA_TUNNEL_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, len); } static int nft_tunnel_get_dump(struct sk_buff *skb, diff --git a/net/netfilter/xt_osf.c b/net/netfilter/xt_osf.c index bf7bba80e24c1a22704b74457425f6bbd1f6a5e8..226a317d52a0de19d98dccb63f30d36a00373c1d 100644 --- a/net/netfilter/xt_osf.c +++ b/net/netfilter/xt_osf.c @@ -90,4 +90,3 @@ MODULE_AUTHOR("Evgeniy Polyakov "); MODULE_DESCRIPTION("Passive OS fingerprint matching."); MODULE_ALIAS("ipt_osf"); MODULE_ALIAS("ip6t_osf"); -MODULE_ALIAS_NFNL_SUBSYS(NFNL_SUBSYS_OSF); diff --git a/net/netfilter/xt_recent.c b/net/netfilter/xt_recent.c index cb58bc7ae30d34053324c8e0102f9d54c7b2f56b..2dbf92346a7e51a4666b4c944d7420f1f59115d4 100644 --- a/net/netfilter/xt_recent.c +++ b/net/netfilter/xt_recent.c @@ -566,7 +566,7 @@ recent_mt_proc_write(struct file *file, const char __user *input, { struct recent_table *t = PDE_DATA(file_inode(file)); struct recent_entry *e; - char buf[sizeof("+b335:1d35:1e55:dead:c0de:1715:5afe:c0de")]; + char buf[sizeof("+b335:1d35:1e55:dead:c0de:1715:255.255.255.255")]; const char *c = buf; union nf_inet_addr addr = {}; u_int16_t family; diff --git a/net/netfilter/xt_sctp.c b/net/netfilter/xt_sctp.c index 2d2fa1d53ea6b3487a474d360a7043e60438e131..05495d3f47b87bae2d52923eb91f636bbfe6f565 100644 --- a/net/netfilter/xt_sctp.c +++ b/net/netfilter/xt_sctp.c @@ -149,6 +149,8 @@ static int sctp_mt_check(const struct xt_mtchk_param *par) { const struct xt_sctp_info *info = par->matchinfo; + if (info->flag_count > ARRAY_SIZE(info->flag_info)) + return -EINVAL; if (info->flags & ~XT_SCTP_VALID_FLAGS) return -EINVAL; if (info->invflags & ~XT_SCTP_VALID_FLAGS) diff --git a/net/netfilter/xt_u32.c b/net/netfilter/xt_u32.c index a95b50342dbb1d1f1a43663e46104e031f4f295a..58ba402bc0b0a05ff3b31102ee904925caeb343a 100644 --- a/net/netfilter/xt_u32.c +++ b/net/netfilter/xt_u32.c @@ -95,11 +95,32 @@ static bool u32_mt(const struct sk_buff *skb, struct xt_action_param *par) return ret ^ data->invert; } +static int u32_mt_checkentry(const struct xt_mtchk_param *par) +{ + const struct xt_u32 *data = par->matchinfo; + const struct xt_u32_test *ct; + unsigned int i; + + if (data->ntests > ARRAY_SIZE(data->tests)) + return -EINVAL; + + for (i = 0; i < data->ntests; ++i) { + ct = &data->tests[i]; + + if (ct->nnums > ARRAY_SIZE(ct->location) || + ct->nvalues > ARRAY_SIZE(ct->value)) + return -EINVAL; + } + + return 0; +} + static struct xt_match xt_u32_mt_reg __read_mostly = { .name = "u32", .revision = 0, .family = NFPROTO_UNSPEC, .match = u32_mt, + .checkentry = u32_mt_checkentry, .matchsize = sizeof(struct xt_u32), .me = THIS_MODULE, }; diff --git a/net/netlabel/netlabel_kapi.c b/net/netlabel/netlabel_kapi.c index 15fe2120b31096983071f36ff2e066a8fb7d4443..14c3d640f94b9ed65950952d1c55436e6e80e5d8 100644 --- a/net/netlabel/netlabel_kapi.c +++ b/net/netlabel/netlabel_kapi.c @@ -871,7 +871,8 @@ int netlbl_catmap_setlong(struct netlbl_lsm_catmap **catmap, offset -= iter->startbit; idx = offset / NETLBL_CATMAP_MAPSIZE; - iter->bitmap[idx] |= bitmap << (offset % NETLBL_CATMAP_MAPSIZE); + iter->bitmap[idx] |= (NETLBL_CATMAP_MAPTYPE)bitmap + << (offset % NETLBL_CATMAP_MAPSIZE); return 0; } diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c index 6a49c0aa55bda22bb1497ada0874060f03d4f70d..35ecaa93f213a110ee9eebd9b5518a1e2cc0c780 100644 --- a/net/netlink/af_netlink.c +++ b/net/netlink/af_netlink.c @@ -1603,6 +1603,7 @@ static int do_one_set_err(struct sock *sk, struct netlink_set_err_data *p) int netlink_set_err(struct sock *ssk, u32 portid, u32 group, int code) { struct netlink_set_err_data info; + unsigned long flags; struct sock *sk; int ret = 0; @@ -1612,12 +1613,12 @@ int netlink_set_err(struct sock *ssk, u32 portid, u32 group, int code) /* sk->sk_err wants a positive error value */ info.code = -code; - read_lock(&nl_table_lock); + read_lock_irqsave(&nl_table_lock, flags); sk_for_each_bound(sk, &nl_table[ssk->sk_protocol].mc_list) ret += do_one_set_err(sk, &info); - read_unlock(&nl_table_lock); + read_unlock_irqrestore(&nl_table_lock, flags); return ret; } EXPORT_SYMBOL(netlink_set_err); @@ -1738,7 +1739,8 @@ static int netlink_getsockopt(struct socket *sock, int level, int optname, { struct sock *sk = sock->sk; struct netlink_sock *nlk = nlk_sk(sk); - int len, val, err; + unsigned int flag; + int len, val; if (level != SOL_NETLINK) return -ENOPROTOOPT; @@ -1750,39 +1752,17 @@ static int netlink_getsockopt(struct socket *sock, int level, int optname, switch (optname) { case NETLINK_PKTINFO: - if (len < sizeof(int)) - return -EINVAL; - len = sizeof(int); - val = nlk->flags & NETLINK_F_RECV_PKTINFO ? 1 : 0; - if (put_user(len, optlen) || - put_user(val, optval)) - return -EFAULT; - err = 0; + flag = NETLINK_F_RECV_PKTINFO; break; case NETLINK_BROADCAST_ERROR: - if (len < sizeof(int)) - return -EINVAL; - len = sizeof(int); - val = nlk->flags & NETLINK_F_BROADCAST_SEND_ERROR ? 1 : 0; - if (put_user(len, optlen) || - put_user(val, optval)) - return -EFAULT; - err = 0; + flag = NETLINK_F_BROADCAST_SEND_ERROR; break; case NETLINK_NO_ENOBUFS: - if (len < sizeof(int)) - return -EINVAL; - len = sizeof(int); - val = nlk->flags & NETLINK_F_RECV_NO_ENOBUFS ? 1 : 0; - if (put_user(len, optlen) || - put_user(val, optval)) - return -EFAULT; - err = 0; + flag = NETLINK_F_RECV_NO_ENOBUFS; break; case NETLINK_LIST_MEMBERSHIPS: { - int pos, idx, shift; + int pos, idx, shift, err = 0; - err = 0; netlink_lock_table(); for (pos = 0; pos * 8 < nlk->ngroups; pos += sizeof(u32)) { if (len - pos < sizeof(u32)) @@ -1796,34 +1776,32 @@ static int netlink_getsockopt(struct socket *sock, int level, int optname, break; } } - if (put_user(ALIGN(nlk->ngroups / 8, sizeof(u32)), optlen)) + if (put_user(ALIGN(BITS_TO_BYTES(nlk->ngroups), sizeof(u32)), optlen)) err = -EFAULT; netlink_unlock_table(); - break; + return err; } case NETLINK_CAP_ACK: - if (len < sizeof(int)) - return -EINVAL; - len = sizeof(int); - val = nlk->flags & NETLINK_F_CAP_ACK ? 1 : 0; - if (put_user(len, optlen) || - put_user(val, optval)) - return -EFAULT; - err = 0; + flag = NETLINK_F_CAP_ACK; break; case NETLINK_EXT_ACK: - if (len < sizeof(int)) - return -EINVAL; - len = sizeof(int); - val = nlk->flags & NETLINK_F_EXT_ACK ? 1 : 0; - if (put_user(len, optlen) || put_user(val, optval)) - return -EFAULT; - err = 0; + flag = NETLINK_F_EXT_ACK; break; default: - err = -ENOPROTOOPT; + return -ENOPROTOOPT; } - return err; + + if (len < sizeof(int)) + return -EINVAL; + + len = sizeof(int); + val = nlk->flags & flag ? 1 : 0; + + if (put_user(len, optlen) || + copy_to_user(optval, &val, len)) + return -EFAULT; + + return 0; } static void netlink_cmsg_recv_pktinfo(struct msghdr *msg, struct sk_buff *skb) @@ -2006,7 +1984,7 @@ static int netlink_recvmsg(struct socket *sock, struct msghdr *msg, size_t len, skb_free_datagram(sk, skb); - if (nlk->cb_running && + if (READ_ONCE(nlk->cb_running) && atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf / 2) { ret = netlink_dump(sk); if (ret) { @@ -2288,7 +2266,7 @@ static int netlink_dump(struct sock *sk) if (cb->done) cb->done(cb); - nlk->cb_running = false; + WRITE_ONCE(nlk->cb_running, false); module = cb->module; skb = cb->skb; mutex_unlock(nlk->cb_mutex); @@ -2348,7 +2326,7 @@ int __netlink_dump_start(struct sock *ssk, struct sk_buff *skb, goto error_put; } - nlk->cb_running = true; + WRITE_ONCE(nlk->cb_running, true); nlk->dump_done_errno = INT_MAX; mutex_unlock(nlk->cb_mutex); @@ -2654,7 +2632,7 @@ static int netlink_seq_show(struct seq_file *seq, void *v) nlk->groups ? (u32)nlk->groups[0] : 0, sk_rmem_alloc_get(s), sk_wmem_alloc_get(s), - nlk->cb_running, + READ_ONCE(nlk->cb_running), refcount_read(&s->sk_refcnt), atomic_read(&s->sk_drops), sock_i_ino(s) diff --git a/net/netlink/diag.c b/net/netlink/diag.c index 7dda33b9b78491aa568c0ae99682d34c0bc056dd..85ee4891c2c7ff7a5e67cf1952dc5958a4fd70c2 100644 --- a/net/netlink/diag.c +++ b/net/netlink/diag.c @@ -93,6 +93,7 @@ static int __netlink_diag_dump(struct sk_buff *skb, struct netlink_callback *cb, struct net *net = sock_net(skb->sk); struct netlink_diag_req *req; struct netlink_sock *nlsk; + unsigned long flags; struct sock *sk; int num = 2; int ret = 0; @@ -151,7 +152,7 @@ static int __netlink_diag_dump(struct sk_buff *skb, struct netlink_callback *cb, num++; mc_list: - read_lock(&nl_table_lock); + read_lock_irqsave(&nl_table_lock, flags); sk_for_each_bound(sk, &tbl->mc_list) { if (sk_hashed(sk)) continue; @@ -166,13 +167,13 @@ static int __netlink_diag_dump(struct sk_buff *skb, struct netlink_callback *cb, NETLINK_CB(cb->skb).portid, cb->nlh->nlmsg_seq, NLM_F_MULTI, - sock_i_ino(sk)) < 0) { + __sock_i_ino(sk)) < 0) { ret = 1; break; } num++; } - read_unlock(&nl_table_lock); + read_unlock_irqrestore(&nl_table_lock, flags); done: cb->args[0] = num; diff --git a/net/netrom/af_netrom.c b/net/netrom/af_netrom.c index a5d819fa7c8995d7b9ed3d0562edb1fae78948a1..146550ce0ac6f5e742983fd834a496188189f63d 100644 --- a/net/netrom/af_netrom.c +++ b/net/netrom/af_netrom.c @@ -663,6 +663,11 @@ static int nr_connect(struct socket *sock, struct sockaddr *uaddr, goto out_release; } + if (sock->state == SS_CONNECTING) { + err = -EALREADY; + goto out_release; + } + sk->sk_state = TCP_CLOSE; sock->state = SS_UNCONNECTED; diff --git a/net/netrom/nr_subr.c b/net/netrom/nr_subr.c index 029c8bb90f4c3dd470c56e5c29ebcfc05afb7b4d..a7d3a265befb92f51225e6eb8f26a2742541ef46 100644 --- a/net/netrom/nr_subr.c +++ b/net/netrom/nr_subr.c @@ -126,7 +126,7 @@ void nr_write_internal(struct sock *sk, int frametype) unsigned char *dptr; int len, timeout; - len = NR_NETWORK_LEN + NR_TRANSPORT_LEN; + len = NR_TRANSPORT_LEN; switch (frametype & 0x0F) { case NR_CONNREQ: @@ -144,7 +144,8 @@ void nr_write_internal(struct sock *sk, int frametype) return; } - if ((skb = alloc_skb(len, GFP_ATOMIC)) == NULL) + skb = alloc_skb(NR_NETWORK_LEN + len, GFP_ATOMIC); + if (!skb) return; /* @@ -152,7 +153,7 @@ void nr_write_internal(struct sock *sk, int frametype) */ skb_reserve(skb, NR_NETWORK_LEN); - dptr = skb_put(skb, skb_tailroom(skb)); + dptr = skb_put(skb, len); switch (frametype & 0x0F) { case NR_CONNREQ: diff --git a/net/nfc/core.c b/net/nfc/core.c index a84f824da051d315e15d1091273f0b02d1815c86..dd12ee46ac7301cc6b79059165c5f5da5d26f8e7 100644 --- a/net/nfc/core.c +++ b/net/nfc/core.c @@ -646,7 +646,7 @@ int nfc_disable_se(struct nfc_dev *dev, u32 se_idx) return rc; } -int nfc_set_remote_general_bytes(struct nfc_dev *dev, u8 *gb, u8 gb_len) +int nfc_set_remote_general_bytes(struct nfc_dev *dev, const u8 *gb, u8 gb_len) { pr_debug("dev_name=%s gb_len=%d\n", dev_name(&dev->dev), gb_len); @@ -675,7 +675,7 @@ int nfc_tm_data_received(struct nfc_dev *dev, struct sk_buff *skb) EXPORT_SYMBOL(nfc_tm_data_received); int nfc_tm_activated(struct nfc_dev *dev, u32 protocol, u8 comm_mode, - u8 *gb, size_t gb_len) + const u8 *gb, size_t gb_len) { int rc; diff --git a/net/nfc/hci/llc_shdlc.c b/net/nfc/hci/llc_shdlc.c index fe988936ad923ae7fac6355a3204ad9c127704d4..e6863c71f566ddd103d62972ed9f07e68d3d60f5 100644 --- a/net/nfc/hci/llc_shdlc.c +++ b/net/nfc/hci/llc_shdlc.c @@ -134,7 +134,7 @@ static bool llc_shdlc_x_lteq_y_lt_z(int x, int y, int z) return ((y >= x) || (y < z)) ? true : false; } -static struct sk_buff *llc_shdlc_alloc_skb(struct llc_shdlc *shdlc, +static struct sk_buff *llc_shdlc_alloc_skb(const struct llc_shdlc *shdlc, int payload_len) { struct sk_buff *skb; @@ -148,7 +148,7 @@ static struct sk_buff *llc_shdlc_alloc_skb(struct llc_shdlc *shdlc, } /* immediately sends an S frame. */ -static int llc_shdlc_send_s_frame(struct llc_shdlc *shdlc, +static int llc_shdlc_send_s_frame(const struct llc_shdlc *shdlc, enum sframe_type sframe_type, int nr) { int r; @@ -170,7 +170,7 @@ static int llc_shdlc_send_s_frame(struct llc_shdlc *shdlc, } /* immediately sends an U frame. skb may contain optional payload */ -static int llc_shdlc_send_u_frame(struct llc_shdlc *shdlc, +static int llc_shdlc_send_u_frame(const struct llc_shdlc *shdlc, struct sk_buff *skb, enum uframe_modifier uframe_modifier) { @@ -372,7 +372,7 @@ static void llc_shdlc_connect_complete(struct llc_shdlc *shdlc, int r) wake_up(shdlc->connect_wq); } -static int llc_shdlc_connect_initiate(struct llc_shdlc *shdlc) +static int llc_shdlc_connect_initiate(const struct llc_shdlc *shdlc) { struct sk_buff *skb; @@ -388,7 +388,7 @@ static int llc_shdlc_connect_initiate(struct llc_shdlc *shdlc) return llc_shdlc_send_u_frame(shdlc, skb, U_FRAME_RSET); } -static int llc_shdlc_connect_send_ua(struct llc_shdlc *shdlc) +static int llc_shdlc_connect_send_ua(const struct llc_shdlc *shdlc) { struct sk_buff *skb; diff --git a/net/nfc/llcp.h b/net/nfc/llcp.h index 1f68724d44d3bad684382afc04b38a01bff9bd3b..a070a57fc15164f225dbb7be0908b87ef466ebad 100644 --- a/net/nfc/llcp.h +++ b/net/nfc/llcp.h @@ -233,15 +233,15 @@ struct sock *nfc_llcp_accept_dequeue(struct sock *sk, struct socket *newsock); /* TLV API */ int nfc_llcp_parse_gb_tlv(struct nfc_llcp_local *local, - u8 *tlv_array, u16 tlv_array_len); + const u8 *tlv_array, u16 tlv_array_len); int nfc_llcp_parse_connection_tlv(struct nfc_llcp_sock *sock, - u8 *tlv_array, u16 tlv_array_len); + const u8 *tlv_array, u16 tlv_array_len); /* Commands API */ void nfc_llcp_recv(void *data, struct sk_buff *skb, int err); -u8 *nfc_llcp_build_tlv(u8 type, u8 *value, u8 value_length, u8 *tlv_length); +u8 *nfc_llcp_build_tlv(u8 type, const u8 *value, u8 value_length, u8 *tlv_length); struct nfc_llcp_sdp_tlv *nfc_llcp_build_sdres_tlv(u8 tid, u8 sap); -struct nfc_llcp_sdp_tlv *nfc_llcp_build_sdreq_tlv(u8 tid, char *uri, +struct nfc_llcp_sdp_tlv *nfc_llcp_build_sdreq_tlv(u8 tid, const char *uri, size_t uri_len); void nfc_llcp_free_sdp_tlv(struct nfc_llcp_sdp_tlv *sdp); void nfc_llcp_free_sdp_tlv_list(struct hlist_head *sdp_head); diff --git a/net/nfc/llcp_commands.c b/net/nfc/llcp_commands.c index d1fc019e932e0c92caccab7d2ef3dc43e12880f0..737c7aa384f447d263c24c8a764072072cdb64b2 100644 --- a/net/nfc/llcp_commands.c +++ b/net/nfc/llcp_commands.c @@ -27,7 +27,7 @@ #include "nfc.h" #include "llcp.h" -static u8 llcp_tlv_length[LLCP_TLV_MAX] = { +static const u8 llcp_tlv_length[LLCP_TLV_MAX] = { 0, 1, /* VERSION */ 2, /* MIUX */ @@ -41,7 +41,7 @@ static u8 llcp_tlv_length[LLCP_TLV_MAX] = { }; -static u8 llcp_tlv8(u8 *tlv, u8 type) +static u8 llcp_tlv8(const u8 *tlv, u8 type) { if (tlv[0] != type || tlv[1] != llcp_tlv_length[tlv[0]]) return 0; @@ -49,7 +49,7 @@ static u8 llcp_tlv8(u8 *tlv, u8 type) return tlv[2]; } -static u16 llcp_tlv16(u8 *tlv, u8 type) +static u16 llcp_tlv16(const u8 *tlv, u8 type) { if (tlv[0] != type || tlv[1] != llcp_tlv_length[tlv[0]]) return 0; @@ -58,37 +58,37 @@ static u16 llcp_tlv16(u8 *tlv, u8 type) } -static u8 llcp_tlv_version(u8 *tlv) +static u8 llcp_tlv_version(const u8 *tlv) { return llcp_tlv8(tlv, LLCP_TLV_VERSION); } -static u16 llcp_tlv_miux(u8 *tlv) +static u16 llcp_tlv_miux(const u8 *tlv) { return llcp_tlv16(tlv, LLCP_TLV_MIUX) & 0x7ff; } -static u16 llcp_tlv_wks(u8 *tlv) +static u16 llcp_tlv_wks(const u8 *tlv) { return llcp_tlv16(tlv, LLCP_TLV_WKS); } -static u16 llcp_tlv_lto(u8 *tlv) +static u16 llcp_tlv_lto(const u8 *tlv) { return llcp_tlv8(tlv, LLCP_TLV_LTO); } -static u8 llcp_tlv_opt(u8 *tlv) +static u8 llcp_tlv_opt(const u8 *tlv) { return llcp_tlv8(tlv, LLCP_TLV_OPT); } -static u8 llcp_tlv_rw(u8 *tlv) +static u8 llcp_tlv_rw(const u8 *tlv) { return llcp_tlv8(tlv, LLCP_TLV_RW) & 0xf; } -u8 *nfc_llcp_build_tlv(u8 type, u8 *value, u8 value_length, u8 *tlv_length) +u8 *nfc_llcp_build_tlv(u8 type, const u8 *value, u8 value_length, u8 *tlv_length) { u8 *tlv, length; @@ -142,7 +142,7 @@ struct nfc_llcp_sdp_tlv *nfc_llcp_build_sdres_tlv(u8 tid, u8 sap) return sdres; } -struct nfc_llcp_sdp_tlv *nfc_llcp_build_sdreq_tlv(u8 tid, char *uri, +struct nfc_llcp_sdp_tlv *nfc_llcp_build_sdreq_tlv(u8 tid, const char *uri, size_t uri_len) { struct nfc_llcp_sdp_tlv *sdreq; @@ -202,9 +202,10 @@ void nfc_llcp_free_sdp_tlv_list(struct hlist_head *head) } int nfc_llcp_parse_gb_tlv(struct nfc_llcp_local *local, - u8 *tlv_array, u16 tlv_array_len) + const u8 *tlv_array, u16 tlv_array_len) { - u8 *tlv = tlv_array, type, length, offset = 0; + const u8 *tlv = tlv_array; + u8 type, length, offset = 0; pr_debug("TLV array length %d\n", tlv_array_len); @@ -251,9 +252,10 @@ int nfc_llcp_parse_gb_tlv(struct nfc_llcp_local *local, } int nfc_llcp_parse_connection_tlv(struct nfc_llcp_sock *sock, - u8 *tlv_array, u16 tlv_array_len) + const u8 *tlv_array, u16 tlv_array_len) { - u8 *tlv = tlv_array, type, length, offset = 0; + const u8 *tlv = tlv_array; + u8 type, length, offset = 0; pr_debug("TLV array length %d\n", tlv_array_len); @@ -307,7 +309,7 @@ static struct sk_buff *llcp_add_header(struct sk_buff *pdu, return pdu; } -static struct sk_buff *llcp_add_tlv(struct sk_buff *pdu, u8 *tlv, +static struct sk_buff *llcp_add_tlv(struct sk_buff *pdu, const u8 *tlv, u8 tlv_length) { /* XXX Add an skb length check */ @@ -401,9 +403,11 @@ int nfc_llcp_send_connect(struct nfc_llcp_sock *sock) { struct nfc_llcp_local *local; struct sk_buff *skb; - u8 *service_name_tlv = NULL, service_name_tlv_length; - u8 *miux_tlv = NULL, miux_tlv_length; - u8 *rw_tlv = NULL, rw_tlv_length, rw; + const u8 *service_name_tlv = NULL; + const u8 *miux_tlv = NULL; + const u8 *rw_tlv = NULL; + u8 service_name_tlv_length = 0; + u8 miux_tlv_length, rw_tlv_length, rw; int err; u16 size = 0; __be16 miux; @@ -477,8 +481,9 @@ int nfc_llcp_send_cc(struct nfc_llcp_sock *sock) { struct nfc_llcp_local *local; struct sk_buff *skb; - u8 *miux_tlv = NULL, miux_tlv_length; - u8 *rw_tlv = NULL, rw_tlv_length, rw; + const u8 *miux_tlv = NULL; + const u8 *rw_tlv = NULL; + u8 miux_tlv_length, rw_tlv_length, rw; int err; u16 size = 0; __be16 miux; diff --git a/net/nfc/llcp_core.c b/net/nfc/llcp_core.c index 3290f2275b857ab704c7f806dbddc84559dd4f57..c30b28465e6449a35bde60cd8bf159e530159020 100644 --- a/net/nfc/llcp_core.c +++ b/net/nfc/llcp_core.c @@ -216,17 +216,13 @@ static struct nfc_llcp_sock *nfc_llcp_sock_get(struct nfc_llcp_local *local, if (tmp_sock->ssap == ssap && tmp_sock->dsap == dsap) { llcp_sock = tmp_sock; + sock_hold(&llcp_sock->sk); break; } } read_unlock(&local->sockets.lock); - if (llcp_sock == NULL) - return NULL; - - sock_hold(&llcp_sock->sk); - return llcp_sock; } @@ -314,7 +310,7 @@ static char *wks[] = { "urn:nfc:sn:snep", }; -static int nfc_llcp_wks_sap(char *service_name, size_t service_name_len) +static int nfc_llcp_wks_sap(const char *service_name, size_t service_name_len) { int sap, num_wks; @@ -338,7 +334,8 @@ static int nfc_llcp_wks_sap(char *service_name, size_t service_name_len) static struct nfc_llcp_sock *nfc_llcp_sock_from_sn(struct nfc_llcp_local *local, - u8 *sn, size_t sn_len) + const u8 *sn, size_t sn_len, + bool needref) { struct sock *sk; struct nfc_llcp_sock *llcp_sock, *tmp_sock; @@ -374,6 +371,8 @@ struct nfc_llcp_sock *nfc_llcp_sock_from_sn(struct nfc_llcp_local *local, if (memcmp(sn, tmp_sock->service_name, sn_len) == 0) { llcp_sock = tmp_sock; + if (needref) + sock_hold(&llcp_sock->sk); break; } } @@ -415,7 +414,8 @@ u8 nfc_llcp_get_sdp_ssap(struct nfc_llcp_local *local, * to this service name. */ if (nfc_llcp_sock_from_sn(local, sock->service_name, - sock->service_name_len) != NULL) { + sock->service_name_len, + false) != NULL) { mutex_unlock(&local->sdp_lock); return LLCP_SAP_MAX; @@ -535,7 +535,7 @@ static int nfc_llcp_build_gb(struct nfc_llcp_local *local) { u8 *gb_cur, version, version_length; u8 lto_length, wks_length, miux_length; - u8 *version_tlv = NULL, *lto_tlv = NULL, + const u8 *version_tlv = NULL, *lto_tlv = NULL, *wks_tlv = NULL, *miux_tlv = NULL; __be16 wks = cpu_to_be16(local->local_wks); u8 gb_len = 0; @@ -625,7 +625,7 @@ u8 *nfc_llcp_general_bytes(struct nfc_dev *dev, size_t *general_bytes_len) return local->gb; } -int nfc_llcp_set_remote_gb(struct nfc_dev *dev, u8 *gb, u8 gb_len) +int nfc_llcp_set_remote_gb(struct nfc_dev *dev, const u8 *gb, u8 gb_len) { struct nfc_llcp_local *local; @@ -652,27 +652,27 @@ int nfc_llcp_set_remote_gb(struct nfc_dev *dev, u8 *gb, u8 gb_len) local->remote_gb_len - 3); } -static u8 nfc_llcp_dsap(struct sk_buff *pdu) +static u8 nfc_llcp_dsap(const struct sk_buff *pdu) { return (pdu->data[0] & 0xfc) >> 2; } -static u8 nfc_llcp_ptype(struct sk_buff *pdu) +static u8 nfc_llcp_ptype(const struct sk_buff *pdu) { return ((pdu->data[0] & 0x03) << 2) | ((pdu->data[1] & 0xc0) >> 6); } -static u8 nfc_llcp_ssap(struct sk_buff *pdu) +static u8 nfc_llcp_ssap(const struct sk_buff *pdu) { return pdu->data[1] & 0x3f; } -static u8 nfc_llcp_ns(struct sk_buff *pdu) +static u8 nfc_llcp_ns(const struct sk_buff *pdu) { return pdu->data[2] >> 4; } -static u8 nfc_llcp_nr(struct sk_buff *pdu) +static u8 nfc_llcp_nr(const struct sk_buff *pdu) { return pdu->data[2] & 0xf; } @@ -814,23 +814,15 @@ static struct nfc_llcp_sock *nfc_llcp_connecting_sock_get(struct nfc_llcp_local } static struct nfc_llcp_sock *nfc_llcp_sock_get_sn(struct nfc_llcp_local *local, - u8 *sn, size_t sn_len) + const u8 *sn, size_t sn_len) { - struct nfc_llcp_sock *llcp_sock; - - llcp_sock = nfc_llcp_sock_from_sn(local, sn, sn_len); - - if (llcp_sock == NULL) - return NULL; - - sock_hold(&llcp_sock->sk); - - return llcp_sock; + return nfc_llcp_sock_from_sn(local, sn, sn_len, true); } -static u8 *nfc_llcp_connect_sn(struct sk_buff *skb, size_t *sn_len) +static const u8 *nfc_llcp_connect_sn(const struct sk_buff *skb, size_t *sn_len) { - u8 *tlv = &skb->data[2], type, length; + u8 type, length; + const u8 *tlv = &skb->data[2]; size_t tlv_array_len = skb->len - LLCP_HEADER_SIZE, offset = 0; while (offset < tlv_array_len) { @@ -888,7 +880,7 @@ static void nfc_llcp_recv_ui(struct nfc_llcp_local *local, } static void nfc_llcp_recv_connect(struct nfc_llcp_local *local, - struct sk_buff *skb) + const struct sk_buff *skb) { struct sock *new_sk, *parent; struct nfc_llcp_sock *sock, *new_sock; @@ -906,7 +898,7 @@ static void nfc_llcp_recv_connect(struct nfc_llcp_local *local, goto fail; } } else { - u8 *sn; + const u8 *sn; size_t sn_len; sn = nfc_llcp_connect_sn(skb, &sn_len); @@ -1125,7 +1117,7 @@ static void nfc_llcp_recv_hdlc(struct nfc_llcp_local *local, } static void nfc_llcp_recv_disc(struct nfc_llcp_local *local, - struct sk_buff *skb) + const struct sk_buff *skb) { struct nfc_llcp_sock *llcp_sock; struct sock *sk; @@ -1168,7 +1160,8 @@ static void nfc_llcp_recv_disc(struct nfc_llcp_local *local, nfc_llcp_sock_put(llcp_sock); } -static void nfc_llcp_recv_cc(struct nfc_llcp_local *local, struct sk_buff *skb) +static void nfc_llcp_recv_cc(struct nfc_llcp_local *local, + const struct sk_buff *skb) { struct nfc_llcp_sock *llcp_sock; struct sock *sk; @@ -1201,7 +1194,8 @@ static void nfc_llcp_recv_cc(struct nfc_llcp_local *local, struct sk_buff *skb) nfc_llcp_sock_put(llcp_sock); } -static void nfc_llcp_recv_dm(struct nfc_llcp_local *local, struct sk_buff *skb) +static void nfc_llcp_recv_dm(struct nfc_llcp_local *local, + const struct sk_buff *skb) { struct nfc_llcp_sock *llcp_sock; struct sock *sk; @@ -1239,12 +1233,13 @@ static void nfc_llcp_recv_dm(struct nfc_llcp_local *local, struct sk_buff *skb) } static void nfc_llcp_recv_snl(struct nfc_llcp_local *local, - struct sk_buff *skb) + const struct sk_buff *skb) { struct nfc_llcp_sock *llcp_sock; - u8 dsap, ssap, *tlv, type, length, tid, sap; + u8 dsap, ssap, type, length, tid, sap; + const u8 *tlv; u16 tlv_len, offset; - char *service_name; + const char *service_name; size_t service_name_len; struct nfc_llcp_sdp_tlv *sdp; HLIST_HEAD(llc_sdres_list); @@ -1286,7 +1281,8 @@ static void nfc_llcp_recv_snl(struct nfc_llcp_local *local, } llcp_sock = nfc_llcp_sock_from_sn(local, service_name, - service_name_len); + service_name_len, + true); if (!llcp_sock) { sap = 0; goto add_snl; @@ -1306,6 +1302,7 @@ static void nfc_llcp_recv_snl(struct nfc_llcp_local *local, if (sap == LLCP_SAP_MAX) { sap = 0; + nfc_llcp_sock_put(llcp_sock); goto add_snl; } @@ -1323,6 +1320,7 @@ static void nfc_llcp_recv_snl(struct nfc_llcp_local *local, pr_debug("%p %d\n", llcp_sock, sap); + nfc_llcp_sock_put(llcp_sock); add_snl: sdp = nfc_llcp_build_sdres_tlv(tid, sap); if (sdp == NULL) diff --git a/net/nfc/nci/core.c b/net/nfc/nci/core.c index 66608e6c5b0ec4236f5aedf3ad613cbb5bc443c9..33723d843e4727bc2437cbc971f1a4735d754422 100644 --- a/net/nfc/nci/core.c +++ b/net/nfc/nci/core.c @@ -906,6 +906,11 @@ static int nci_activate_target(struct nfc_dev *nfc_dev, return -EINVAL; } + if (protocol >= NFC_PROTO_MAX) { + pr_err("the requested nfc protocol is invalid\n"); + return -EINVAL; + } + if (!(nci_target->supported_protocols & (1 << protocol))) { pr_err("target does not support the requested protocol 0x%x\n", protocol); diff --git a/net/nfc/nci/spi.c b/net/nfc/nci/spi.c index 452f4c16b7a9a032f278c9c8541e4c646b3efc84..d2de7fc226f04f9d5a2446ec8054c6718e16e049 100644 --- a/net/nfc/nci/spi.c +++ b/net/nfc/nci/spi.c @@ -163,6 +163,8 @@ static int send_acknowledge(struct nci_spi *nspi, u8 acknowledge) int ret; skb = nci_skb_alloc(nspi->ndev, 0, GFP_KERNEL); + if (!skb) + return -ENOMEM; /* add the NCI SPI header to the start of the buffer */ hdr = skb_push(skb, NCI_SPI_HDR_LEN); diff --git a/net/nfc/netlink.c b/net/nfc/netlink.c index 8953b03d5a529e120d8f80c14eaa2a1a7f14becc..f705800b224887fe1168b0ff6817a97df1b10177 100644 --- a/net/nfc/netlink.c +++ b/net/nfc/netlink.c @@ -1460,8 +1460,12 @@ static int nfc_se_io(struct nfc_dev *dev, u32 se_idx, rc = dev->ops->se_io(dev, se_idx, apdu, apdu_length, cb, cb_context); + device_unlock(&dev->dev); + return rc; + error: device_unlock(&dev->dev); + kfree(cb_context); return rc; } diff --git a/net/nfc/nfc.h b/net/nfc/nfc.h index 6c6f76b370b1e7955bcb4aa780a388719eb76b2d..c792165f523f1eb01a63520007962b524b746fea 100644 --- a/net/nfc/nfc.h +++ b/net/nfc/nfc.h @@ -60,7 +60,7 @@ void nfc_llcp_mac_is_up(struct nfc_dev *dev, u32 target_idx, u8 comm_mode, u8 rf_mode); int nfc_llcp_register_device(struct nfc_dev *dev); void nfc_llcp_unregister_device(struct nfc_dev *dev); -int nfc_llcp_set_remote_gb(struct nfc_dev *dev, u8 *gb, u8 gb_len); +int nfc_llcp_set_remote_gb(struct nfc_dev *dev, const u8 *gb, u8 gb_len); u8 *nfc_llcp_general_bytes(struct nfc_dev *dev, size_t *general_bytes_len); int nfc_llcp_data_received(struct nfc_dev *dev, struct sk_buff *skb); struct nfc_llcp_local *nfc_llcp_find_local(struct nfc_dev *dev); diff --git a/net/nsh/nsh.c b/net/nsh/nsh.c index 1a30e165eeb4fd1b884a0d5cd79c6823a5de9feb..a5fa25555d7ebf71f76c21ac8fd1e5b11d47a666 100644 --- a/net/nsh/nsh.c +++ b/net/nsh/nsh.c @@ -80,13 +80,12 @@ static struct sk_buff *nsh_gso_segment(struct sk_buff *skb, netdev_features_t features) { struct sk_buff *segs = ERR_PTR(-EINVAL); + u16 mac_offset = skb->mac_header; unsigned int nsh_len, mac_len; __be16 proto; - int nhoff; skb_reset_network_header(skb); - nhoff = skb->network_header - skb->mac_header; mac_len = skb->mac_len; if (unlikely(!pskb_may_pull(skb, NSH_BASE_HDR_LEN))) @@ -111,15 +110,14 @@ static struct sk_buff *nsh_gso_segment(struct sk_buff *skb, segs = skb_mac_gso_segment(skb, features); if (IS_ERR_OR_NULL(segs)) { skb_gso_error_unwind(skb, htons(ETH_P_NSH), nsh_len, - skb->network_header - nhoff, - mac_len); + mac_offset, mac_len); goto out; } for (skb = segs; skb; skb = skb->next) { skb->protocol = htons(ETH_P_NSH); __skb_push(skb, nsh_len); - skb_set_mac_header(skb, -nhoff); + skb->mac_header = mac_offset; skb->network_header = skb->mac_header + mac_len; skb->mac_len = mac_len; } diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index 4fc6bbce8e43692abbd6eaffa4d849d2633c7aad..e0faa74714537c01082441cc3f0519a2a99a5736 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -374,18 +374,20 @@ static void __packet_set_status(struct packet_sock *po, void *frame, int status) { union tpacket_uhdr h; + /* WRITE_ONCE() are paired with READ_ONCE() in __packet_get_status */ + h.raw = frame; switch (po->tp_version) { case TPACKET_V1: - h.h1->tp_status = status; + WRITE_ONCE(h.h1->tp_status, status); flush_dcache_page(pgv_to_page(&h.h1->tp_status)); break; case TPACKET_V2: - h.h2->tp_status = status; + WRITE_ONCE(h.h2->tp_status, status); flush_dcache_page(pgv_to_page(&h.h2->tp_status)); break; case TPACKET_V3: - h.h3->tp_status = status; + WRITE_ONCE(h.h3->tp_status, status); flush_dcache_page(pgv_to_page(&h.h3->tp_status)); break; default: @@ -402,17 +404,19 @@ static int __packet_get_status(struct packet_sock *po, void *frame) smp_rmb(); + /* READ_ONCE() are paired with WRITE_ONCE() in __packet_set_status */ + h.raw = frame; switch (po->tp_version) { case TPACKET_V1: flush_dcache_page(pgv_to_page(&h.h1->tp_status)); - return h.h1->tp_status; + return READ_ONCE(h.h1->tp_status); case TPACKET_V2: flush_dcache_page(pgv_to_page(&h.h2->tp_status)); - return h.h2->tp_status; + return READ_ONCE(h.h2->tp_status); case TPACKET_V3: flush_dcache_page(pgv_to_page(&h.h3->tp_status)); - return h.h3->tp_status; + return READ_ONCE(h.h3->tp_status); default: WARN(1, "TPACKET version not supported.\n"); BUG(); @@ -1959,7 +1963,7 @@ static int packet_sendmsg_spkt(struct socket *sock, struct msghdr *msg, goto retry; } - if (!dev_validate_header(dev, skb->data, len)) { + if (!dev_validate_header(dev, skb->data, len) || !skb->len) { err = -EINVAL; goto out_unlock; } @@ -2109,7 +2113,7 @@ static int packet_rcv(struct sk_buff *skb, struct net_device *dev, sll = &PACKET_SKB_CB(skb)->sa.ll; sll->sll_hatype = dev->type; sll->sll_pkttype = skb->pkt_type; - if (unlikely(po->origdev)) + if (unlikely(packet_sock_flag(po, PACKET_SOCK_ORIGDEV))) sll->sll_ifindex = orig_dev->ifindex; else sll->sll_ifindex = dev->ifindex; @@ -2382,7 +2386,7 @@ static int tpacket_rcv(struct sk_buff *skb, struct net_device *dev, sll->sll_hatype = dev->type; sll->sll_protocol = skb->protocol; sll->sll_pkttype = skb->pkt_type; - if (unlikely(po->origdev)) + if (unlikely(packet_sock_flag(po, PACKET_SOCK_ORIGDEV))) sll->sll_ifindex = orig_dev->ifindex; else sll->sll_ifindex = dev->ifindex; @@ -3128,6 +3132,9 @@ static int packet_do_bind(struct sock *sk, const char *name, int ifindex, lock_sock(sk); spin_lock(&po->bind_lock); + if (!proto) + proto = po->num; + rcu_read_lock(); if (po->fanout) { @@ -3230,7 +3237,7 @@ static int packet_bind_spkt(struct socket *sock, struct sockaddr *uaddr, memcpy(name, uaddr->sa_data, sizeof(uaddr->sa_data)); name[sizeof(uaddr->sa_data)] = 0; - return packet_do_bind(sk, name, 0, pkt_sk(sk)->num); + return packet_do_bind(sk, name, 0, 0); } static int packet_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len) @@ -3247,8 +3254,7 @@ static int packet_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len if (sll->sll_family != AF_PACKET) return -EINVAL; - return packet_do_bind(sk, NULL, sll->sll_ifindex, - sll->sll_protocol ? : pkt_sk(sk)->num); + return packet_do_bind(sk, NULL, sll->sll_ifindex, sll->sll_protocol); } static struct proto packet_proto = { @@ -3455,7 +3461,7 @@ static int packet_recvmsg(struct socket *sock, struct msghdr *msg, size_t len, memcpy(msg->msg_name, &PACKET_SKB_CB(skb)->sa, copy_len); } - if (pkt_sk(sk)->auxdata) { + if (packet_sock_flag(pkt_sk(sk), PACKET_SOCK_AUXDATA)) { struct tpacket_auxdata aux; aux.tp_status = TP_STATUS_USER; @@ -3838,9 +3844,7 @@ packet_setsockopt(struct socket *sock, int level, int optname, char __user *optv if (copy_from_user(&val, optval, sizeof(val))) return -EFAULT; - lock_sock(sk); - po->auxdata = !!val; - release_sock(sk); + packet_sock_flag_set(po, PACKET_SOCK_AUXDATA, val); return 0; } case PACKET_ORIGDEV: @@ -3852,9 +3856,7 @@ packet_setsockopt(struct socket *sock, int level, int optname, char __user *optv if (copy_from_user(&val, optval, sizeof(val))) return -EFAULT; - lock_sock(sk); - po->origdev = !!val; - release_sock(sk); + packet_sock_flag_set(po, PACKET_SOCK_ORIGDEV, val); return 0; } case PACKET_VNET_HDR: @@ -3984,10 +3986,10 @@ static int packet_getsockopt(struct socket *sock, int level, int optname, break; case PACKET_AUXDATA: - val = po->auxdata; + val = packet_sock_flag(po, PACKET_SOCK_AUXDATA); break; case PACKET_ORIGDEV: - val = po->origdev; + val = packet_sock_flag(po, PACKET_SOCK_ORIGDEV); break; case PACKET_VNET_HDR: val = po->has_vnet_hdr; diff --git a/net/packet/diag.c b/net/packet/diag.c index 7ef1c881ae7417e500630df398a900dddd598092..ecabf78d29b8e5843b64c0489ab2ebf7c1fef2e0 100644 --- a/net/packet/diag.c +++ b/net/packet/diag.c @@ -22,9 +22,9 @@ static int pdiag_put_info(const struct packet_sock *po, struct sk_buff *nlskb) pinfo.pdi_flags = 0; if (po->running) pinfo.pdi_flags |= PDI_RUNNING; - if (po->auxdata) + if (packet_sock_flag(po, PACKET_SOCK_AUXDATA)) pinfo.pdi_flags |= PDI_AUXDATA; - if (po->origdev) + if (packet_sock_flag(po, PACKET_SOCK_ORIGDEV)) pinfo.pdi_flags |= PDI_ORIGDEV; if (po->has_vnet_hdr) pinfo.pdi_flags |= PDI_VNETHDR; @@ -142,7 +142,7 @@ static int sk_diag_fill(struct sock *sk, struct sk_buff *skb, rp = nlmsg_data(nlh); rp->pdiag_family = AF_PACKET; rp->pdiag_type = sk->sk_type; - rp->pdiag_num = ntohs(po->num); + rp->pdiag_num = ntohs(READ_ONCE(po->num)); rp->pdiag_ino = sk_ino; sock_diag_save_cookie(sk, rp->pdiag_cookie); diff --git a/net/packet/internal.h b/net/packet/internal.h index f10294800aafb3673083acd87c21944e313d9a6a..3d871cae85b8c86e3dea8e253d251697ea02ea65 100644 --- a/net/packet/internal.h +++ b/net/packet/internal.h @@ -115,10 +115,9 @@ struct packet_sock { int copy_thresh; spinlock_t bind_lock; struct mutex pg_vec_lock; + unsigned long flags; unsigned int running; /* bind_lock must be held */ - unsigned int auxdata:1, /* writer must hold sock lock */ - origdev:1, - has_vnet_hdr:1, + unsigned int has_vnet_hdr:1, /* writer must hold sock lock */ tp_loss:1, tp_tx_has_off:1; int pressure; @@ -142,4 +141,25 @@ static struct packet_sock *pkt_sk(struct sock *sk) return (struct packet_sock *)sk; } +enum packet_sock_flags { + PACKET_SOCK_ORIGDEV, + PACKET_SOCK_AUXDATA, +}; + +static inline void packet_sock_flag_set(struct packet_sock *po, + enum packet_sock_flags flag, + bool val) +{ + if (val) + set_bit(flag, &po->flags); + else + clear_bit(flag, &po->flags); +} + +static inline bool packet_sock_flag(const struct packet_sock *po, + enum packet_sock_flags flag) +{ + return test_bit(flag, &po->flags); +} + #endif diff --git a/net/rds/message.c b/net/rds/message.c index 309b54cc62ae317a0253a9122ff69438fb015142..29f67ad483ea654d14e54dfb4c06d3bad2805200 100644 --- a/net/rds/message.c +++ b/net/rds/message.c @@ -118,7 +118,7 @@ static void rds_rm_zerocopy_callback(struct rds_sock *rs, ck = &info->zcookies; memset(ck, 0, sizeof(*ck)); WARN_ON(!rds_zcookie_add(info, cookie)); - list_add_tail(&q->zcookie_head, &info->rs_zcookie_next); + list_add_tail(&info->rs_zcookie_next, &q->zcookie_head); spin_unlock_irqrestore(&q->lock, flags); /* caller invokes rds_wake_sk_sleep() */ diff --git a/net/rds/tcp_connect.c b/net/rds/tcp_connect.c index 008f50fb25dd24f572aba43a8d9c58e9c7bd8cea..63efe60fda1fe5a79a9c4e8863b3871d1dc5a623 100644 --- a/net/rds/tcp_connect.c +++ b/net/rds/tcp_connect.c @@ -141,7 +141,7 @@ int rds_tcp_conn_path_connect(struct rds_conn_path *cp) addrlen = sizeof(sin); } - ret = sock->ops->bind(sock, addr, addrlen); + ret = kernel_bind(sock, addr, addrlen); if (ret) { rdsdebug("bind failed with %d at address %pI6c\n", ret, &conn->c_laddr); @@ -169,7 +169,7 @@ int rds_tcp_conn_path_connect(struct rds_conn_path *cp) * own the socket */ rds_tcp_set_callbacks(sock, cp); - ret = sock->ops->connect(sock, addr, addrlen, O_NONBLOCK); + ret = kernel_connect(sock, addr, addrlen, O_NONBLOCK); rdsdebug("connect to address %pI6c returned %d\n", &conn->c_faddr, ret); if (ret == -EINPROGRESS) diff --git a/net/rds/tcp_listen.c b/net/rds/tcp_listen.c index 0d095d3f5feecfdfddb9e58574a548ec4936c193..37f4a8ca3ac8788449bf53fbc9c0322bc668463a 100644 --- a/net/rds/tcp_listen.c +++ b/net/rds/tcp_listen.c @@ -332,7 +332,7 @@ struct socket *rds_tcp_listen_init(struct net *net, bool isv6) addr_len = sizeof(*sin); } - ret = sock->ops->bind(sock, (struct sockaddr *)&ss, addr_len); + ret = kernel_bind(sock, (struct sockaddr *)&ss, addr_len); if (ret < 0) { rdsdebug("could not bind %s listener socket: %d\n", isv6 ? "IPv6" : "IPv4", ret); diff --git a/net/rfkill/rfkill-gpio.c b/net/rfkill/rfkill-gpio.c index 0f846585225431c6ae903bd8308884729c99bb3c..af0842744fc8117f72c1e4ac6816ba8fe5129dc5 100644 --- a/net/rfkill/rfkill-gpio.c +++ b/net/rfkill/rfkill-gpio.c @@ -112,13 +112,13 @@ static int rfkill_gpio_probe(struct platform_device *pdev) rfkill->clk = devm_clk_get(&pdev->dev, NULL); - gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); + gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_ASIS); if (IS_ERR(gpio)) return PTR_ERR(gpio); rfkill->reset_gpio = gpio; - gpio = devm_gpiod_get_optional(&pdev->dev, "shutdown", GPIOD_OUT_LOW); + gpio = devm_gpiod_get_optional(&pdev->dev, "shutdown", GPIOD_ASIS); if (IS_ERR(gpio)) return PTR_ERR(gpio); diff --git a/net/rxrpc/sendmsg.c b/net/rxrpc/sendmsg.c index a7a09eb04d93bcce9892a37823d89a313f16d5d9..eaa032c498c96e24bbbb7ab4c56ae6c64fe19e29 100644 --- a/net/rxrpc/sendmsg.c +++ b/net/rxrpc/sendmsg.c @@ -709,7 +709,7 @@ int rxrpc_do_sendmsg(struct rxrpc_sock *rx, struct msghdr *msg, size_t len) /* Fall through */ case 1: if (p.call.timeouts.hard > 0) { - j = msecs_to_jiffies(p.call.timeouts.hard); + j = p.call.timeouts.hard * HZ; now = jiffies; j += now; WRITE_ONCE(call->expect_term_by, j); diff --git a/net/sched/Kconfig b/net/sched/Kconfig index e9574138831116a59db2c39aaa2cd4ee4f28e06b..7698a8974a4778e0cb1b62f244c917c6039bcfa5 100644 --- a/net/sched/Kconfig +++ b/net/sched/Kconfig @@ -458,17 +458,6 @@ config NET_CLS_BASIC To compile this code as a module, choose M here: the module will be called cls_basic. -config NET_CLS_TCINDEX - tristate "Traffic-Control Index (TCINDEX)" - select NET_CLS - ---help--- - Say Y here if you want to be able to classify packets based on - traffic control indices. You will want this feature if you want - to implement Differentiated Services together with DSMARK. - - To compile this code as a module, choose M here: the - module will be called cls_tcindex. - config NET_CLS_ROUTE4 tristate "Routing decision (ROUTE)" depends on INET @@ -514,34 +503,6 @@ config CLS_U32_MARK ---help--- Say Y here to be able to use netfilter marks as u32 key. -config NET_CLS_RSVP - tristate "IPv4 Resource Reservation Protocol (RSVP)" - select NET_CLS - ---help--- - The Resource Reservation Protocol (RSVP) permits end systems to - request a minimum and maximum data flow rate for a connection; this - is important for real time data such as streaming sound or video. - - Say Y here if you want to be able to classify outgoing packets based - on their RSVP requests. - - To compile this code as a module, choose M here: the - module will be called cls_rsvp. - -config NET_CLS_RSVP6 - tristate "IPv6 Resource Reservation Protocol (RSVP6)" - select NET_CLS - ---help--- - The Resource Reservation Protocol (RSVP) permits end systems to - request a minimum and maximum data flow rate for a connection; this - is important for real time data such as streaming sound or video. - - Say Y here if you want to be able to classify outgoing packets based - on their RSVP requests and you are using the IPv6 protocol. - - To compile this code as a module, choose M here: the - module will be called cls_rsvp6. - config NET_CLS_FLOW tristate "Flow classifier" select NET_CLS diff --git a/net/sched/Makefile b/net/sched/Makefile index f0403f49edcbd50e27d9ea450c2e46b5b4727b8e..3139c32e194782059b75286e90b9563fab7e74c4 100644 --- a/net/sched/Makefile +++ b/net/sched/Makefile @@ -61,9 +61,6 @@ obj-$(CONFIG_NET_SCH_ETF) += sch_etf.o obj-$(CONFIG_NET_CLS_U32) += cls_u32.o obj-$(CONFIG_NET_CLS_ROUTE4) += cls_route.o obj-$(CONFIG_NET_CLS_FW) += cls_fw.o -obj-$(CONFIG_NET_CLS_RSVP) += cls_rsvp.o -obj-$(CONFIG_NET_CLS_TCINDEX) += cls_tcindex.o -obj-$(CONFIG_NET_CLS_RSVP6) += cls_rsvp6.o obj-$(CONFIG_NET_CLS_BASIC) += cls_basic.o obj-$(CONFIG_NET_CLS_FLOW) += cls_flow.o obj-$(CONFIG_NET_CLS_CGROUP) += cls_cgroup.o diff --git a/net/sched/act_mirred.c b/net/sched/act_mirred.c index a30c17a282819f4ba29783d085eca2d33948b200..9aad86e4a0fb99541d3ee9519a2506e9d2a0b3c6 100644 --- a/net/sched/act_mirred.c +++ b/net/sched/act_mirred.c @@ -220,7 +220,7 @@ static int tcf_mirred_act(struct sk_buff *skb, const struct tc_action *a, goto out; } - if (unlikely(!(dev->flags & IFF_UP))) { + if (unlikely(!(dev->flags & IFF_UP)) || !netif_carrier_ok(dev)) { net_notice_ratelimited("tc mirred to Houston: device %s is down\n", dev->name); goto out; diff --git a/net/sched/act_pedit.c b/net/sched/act_pedit.c index aeb8f84cbd9e2ae1148e0b0f8eb9ff30f9eb16c6..255d4ecf62522af3d38b1e30049542f49b5658cd 100644 --- a/net/sched/act_pedit.c +++ b/net/sched/act_pedit.c @@ -29,6 +29,7 @@ static struct tc_action_ops act_pedit_ops; static const struct nla_policy pedit_policy[TCA_PEDIT_MAX + 1] = { [TCA_PEDIT_PARMS] = { .len = sizeof(struct tc_pedit) }, + [TCA_PEDIT_PARMS_EX] = { .len = sizeof(struct tc_pedit) }, [TCA_PEDIT_KEYS_EX] = { .type = NLA_NESTED }, }; diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c index 435911dc9f16ab4054393925f1348de7cdf40a45..6166bbad97536b279bd29cd7139db1c128547b92 100644 --- a/net/sched/cls_api.c +++ b/net/sched/cls_api.c @@ -31,8 +31,6 @@ #include #include -extern const struct nla_policy rtm_tca_policy[TCA_MAX + 1]; - /* The list of all installed classifier types */ static LIST_HEAD(tcf_proto_base); @@ -1840,6 +1838,7 @@ static int tc_chain_tmplt_add(struct tcf_chain *chain, struct net *net, return PTR_ERR(ops); if (!ops->tmplt_create || !ops->tmplt_destroy || !ops->tmplt_dump) { NL_SET_ERR_MSG(extack, "Chain templates are not supported with specified classifier"); + module_put(ops->owner); return -EOPNOTSUPP; } diff --git a/net/sched/cls_flow.c b/net/sched/cls_flow.c index 55bf75cb1f16b88c23556de0c9902e34db5e3f0d..164049d20f4d3df99191b889c018777909b1f06b 100644 --- a/net/sched/cls_flow.c +++ b/net/sched/cls_flow.c @@ -229,7 +229,7 @@ static u32 flow_get_skgid(const struct sk_buff *skb) static u32 flow_get_vlan_tag(const struct sk_buff *skb) { - u16 uninitialized_var(tag); + u16 tag; if (vlan_get_tag(skb, &tag) < 0) return 0; diff --git a/net/sched/cls_flower.c b/net/sched/cls_flower.c index 6163648145c1998aab138ae455f480e9d7749319..7ffa28a98d743499518245801f1c4105da6d74ef 100644 --- a/net/sched/cls_flower.c +++ b/net/sched/cls_flower.c @@ -640,6 +640,9 @@ static int fl_set_geneve_opt(const struct nlattr *nla, struct fl_flow_key *key, if (option_len > sizeof(struct geneve_opt)) data_len = option_len - sizeof(struct geneve_opt); + if (key->enc_opts.len > FLOW_DIS_TUN_OPTS_MAX - 4) + return -ERANGE; + opt = (struct geneve_opt *)&key->enc_opts.data[key->enc_opts.len]; memset(opt, 0xff, option_len); opt->length = data_len / 4; diff --git a/net/sched/cls_fw.c b/net/sched/cls_fw.c index cb2c62605fc764dc3cae9eb4c87ed6b56b03e9db..f15089c24a32de8cf1b6e80e01872ecc77704ff5 100644 --- a/net/sched/cls_fw.c +++ b/net/sched/cls_fw.c @@ -221,11 +221,6 @@ static int fw_set_parms(struct net *net, struct tcf_proto *tp, if (err < 0) return err; - if (tb[TCA_FW_CLASSID]) { - f->res.classid = nla_get_u32(tb[TCA_FW_CLASSID]); - tcf_bind_filter(tp, &f->res, base); - } - #ifdef CONFIG_NET_CLS_IND if (tb[TCA_FW_INDEV]) { int ret; @@ -244,6 +239,11 @@ static int fw_set_parms(struct net *net, struct tcf_proto *tp, } else if (head->mask != 0xFFFFFFFF) return err; + if (tb[TCA_FW_CLASSID]) { + f->res.classid = nla_get_u32(tb[TCA_FW_CLASSID]); + tcf_bind_filter(tp, &f->res, base); + } + return 0; } @@ -277,7 +277,6 @@ static int fw_change(struct net *net, struct sk_buff *in_skb, return -ENOBUFS; fnew->id = f->id; - fnew->res = f->res; #ifdef CONFIG_NET_CLS_IND fnew->ifindex = f->ifindex; #endif /* CONFIG_NET_CLS_IND */ diff --git a/net/sched/cls_route.c b/net/sched/cls_route.c index 4c7fa1cfd8e381acb8f9ac28f44914d943d29197..a924292623ecfa2e63e81afa76351eff7297bd8b 100644 --- a/net/sched/cls_route.c +++ b/net/sched/cls_route.c @@ -513,7 +513,6 @@ static int route4_change(struct net *net, struct sk_buff *in_skb, if (fold) { f->id = fold->id; f->iif = fold->iif; - f->res = fold->res; f->handle = fold->handle; f->tp = fold->tp; diff --git a/net/sched/cls_rsvp.c b/net/sched/cls_rsvp.c deleted file mode 100644 index cbb5e0d600f32951cf4cadb1a080352064869cc8..0000000000000000000000000000000000000000 --- a/net/sched/cls_rsvp.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * net/sched/cls_rsvp.c Special RSVP packet classifier for IPv4. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Authors: Alexey Kuznetsov, - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define RSVP_DST_LEN 1 -#define RSVP_ID "rsvp" -#define RSVP_OPS cls_rsvp_ops - -#include "cls_rsvp.h" -MODULE_LICENSE("GPL"); diff --git a/net/sched/cls_rsvp.h b/net/sched/cls_rsvp.h deleted file mode 100644 index eb1dd2afc5a129473d05b571ff3d181b13cc4bd5..0000000000000000000000000000000000000000 --- a/net/sched/cls_rsvp.h +++ /dev/null @@ -1,775 +0,0 @@ -/* - * net/sched/cls_rsvp.h Template file for RSVPv[46] classifiers. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Authors: Alexey Kuznetsov, - */ - -/* - Comparing to general packet classification problem, - RSVP needs only sevaral relatively simple rules: - - * (dst, protocol) are always specified, - so that we are able to hash them. - * src may be exact, or may be wildcard, so that - we can keep a hash table plus one wildcard entry. - * source port (or flow label) is important only if src is given. - - IMPLEMENTATION. - - We use a two level hash table: The top level is keyed by - destination address and protocol ID, every bucket contains a list - of "rsvp sessions", identified by destination address, protocol and - DPI(="Destination Port ID"): triple (key, mask, offset). - - Every bucket has a smaller hash table keyed by source address - (cf. RSVP flowspec) and one wildcard entry for wildcard reservations. - Every bucket is again a list of "RSVP flows", selected by - source address and SPI(="Source Port ID" here rather than - "security parameter index"): triple (key, mask, offset). - - - NOTE 1. All the packets with IPv6 extension headers (but AH and ESP) - and all fragmented packets go to the best-effort traffic class. - - - NOTE 2. Two "port id"'s seems to be redundant, rfc2207 requires - only one "Generalized Port Identifier". So that for classic - ah, esp (and udp,tcp) both *pi should coincide or one of them - should be wildcard. - - At first sight, this redundancy is just a waste of CPU - resources. But DPI and SPI add the possibility to assign different - priorities to GPIs. Look also at note 4 about tunnels below. - - - NOTE 3. One complication is the case of tunneled packets. - We implement it as following: if the first lookup - matches a special session with "tunnelhdr" value not zero, - flowid doesn't contain the true flow ID, but the tunnel ID (1...255). - In this case, we pull tunnelhdr bytes and restart lookup - with tunnel ID added to the list of keys. Simple and stupid 8)8) - It's enough for PIMREG and IPIP. - - - NOTE 4. Two GPIs make it possible to parse even GRE packets. - F.e. DPI can select ETH_P_IP (and necessary flags to make - tunnelhdr correct) in GRE protocol field and SPI matches - GRE key. Is it not nice? 8)8) - - - Well, as result, despite its simplicity, we get a pretty - powerful classification engine. */ - - -struct rsvp_head { - u32 tmap[256/32]; - u32 hgenerator; - u8 tgenerator; - struct rsvp_session __rcu *ht[256]; - struct rcu_head rcu; -}; - -struct rsvp_session { - struct rsvp_session __rcu *next; - __be32 dst[RSVP_DST_LEN]; - struct tc_rsvp_gpi dpi; - u8 protocol; - u8 tunnelid; - /* 16 (src,sport) hash slots, and one wildcard source slot */ - struct rsvp_filter __rcu *ht[16 + 1]; - struct rcu_head rcu; -}; - - -struct rsvp_filter { - struct rsvp_filter __rcu *next; - __be32 src[RSVP_DST_LEN]; - struct tc_rsvp_gpi spi; - u8 tunnelhdr; - - struct tcf_result res; - struct tcf_exts exts; - - u32 handle; - struct rsvp_session *sess; - struct rcu_work rwork; -}; - -static inline unsigned int hash_dst(__be32 *dst, u8 protocol, u8 tunnelid) -{ - unsigned int h = (__force __u32)dst[RSVP_DST_LEN - 1]; - - h ^= h>>16; - h ^= h>>8; - return (h ^ protocol ^ tunnelid) & 0xFF; -} - -static inline unsigned int hash_src(__be32 *src) -{ - unsigned int h = (__force __u32)src[RSVP_DST_LEN-1]; - - h ^= h>>16; - h ^= h>>8; - h ^= h>>4; - return h & 0xF; -} - -#define RSVP_APPLY_RESULT() \ -{ \ - int r = tcf_exts_exec(skb, &f->exts, res); \ - if (r < 0) \ - continue; \ - else if (r > 0) \ - return r; \ -} - -static int rsvp_classify(struct sk_buff *skb, const struct tcf_proto *tp, - struct tcf_result *res) -{ - struct rsvp_head *head = rcu_dereference_bh(tp->root); - struct rsvp_session *s; - struct rsvp_filter *f; - unsigned int h1, h2; - __be32 *dst, *src; - u8 protocol; - u8 tunnelid = 0; - u8 *xprt; -#if RSVP_DST_LEN == 4 - struct ipv6hdr *nhptr; - - if (!pskb_network_may_pull(skb, sizeof(*nhptr))) - return -1; - nhptr = ipv6_hdr(skb); -#else - struct iphdr *nhptr; - - if (!pskb_network_may_pull(skb, sizeof(*nhptr))) - return -1; - nhptr = ip_hdr(skb); -#endif -restart: - -#if RSVP_DST_LEN == 4 - src = &nhptr->saddr.s6_addr32[0]; - dst = &nhptr->daddr.s6_addr32[0]; - protocol = nhptr->nexthdr; - xprt = ((u8 *)nhptr) + sizeof(struct ipv6hdr); -#else - src = &nhptr->saddr; - dst = &nhptr->daddr; - protocol = nhptr->protocol; - xprt = ((u8 *)nhptr) + (nhptr->ihl<<2); - if (ip_is_fragment(nhptr)) - return -1; -#endif - - h1 = hash_dst(dst, protocol, tunnelid); - h2 = hash_src(src); - - for (s = rcu_dereference_bh(head->ht[h1]); s; - s = rcu_dereference_bh(s->next)) { - if (dst[RSVP_DST_LEN-1] == s->dst[RSVP_DST_LEN - 1] && - protocol == s->protocol && - !(s->dpi.mask & - (*(u32 *)(xprt + s->dpi.offset) ^ s->dpi.key)) && -#if RSVP_DST_LEN == 4 - dst[0] == s->dst[0] && - dst[1] == s->dst[1] && - dst[2] == s->dst[2] && -#endif - tunnelid == s->tunnelid) { - - for (f = rcu_dereference_bh(s->ht[h2]); f; - f = rcu_dereference_bh(f->next)) { - if (src[RSVP_DST_LEN-1] == f->src[RSVP_DST_LEN - 1] && - !(f->spi.mask & (*(u32 *)(xprt + f->spi.offset) ^ f->spi.key)) -#if RSVP_DST_LEN == 4 - && - src[0] == f->src[0] && - src[1] == f->src[1] && - src[2] == f->src[2] -#endif - ) { - *res = f->res; - RSVP_APPLY_RESULT(); - -matched: - if (f->tunnelhdr == 0) - return 0; - - tunnelid = f->res.classid; - nhptr = (void *)(xprt + f->tunnelhdr - sizeof(*nhptr)); - goto restart; - } - } - - /* And wildcard bucket... */ - for (f = rcu_dereference_bh(s->ht[16]); f; - f = rcu_dereference_bh(f->next)) { - *res = f->res; - RSVP_APPLY_RESULT(); - goto matched; - } - return -1; - } - } - return -1; -} - -static void rsvp_replace(struct tcf_proto *tp, struct rsvp_filter *n, u32 h) -{ - struct rsvp_head *head = rtnl_dereference(tp->root); - struct rsvp_session *s; - struct rsvp_filter __rcu **ins; - struct rsvp_filter *pins; - unsigned int h1 = h & 0xFF; - unsigned int h2 = (h >> 8) & 0xFF; - - for (s = rtnl_dereference(head->ht[h1]); s; - s = rtnl_dereference(s->next)) { - for (ins = &s->ht[h2], pins = rtnl_dereference(*ins); ; - ins = &pins->next, pins = rtnl_dereference(*ins)) { - if (pins->handle == h) { - RCU_INIT_POINTER(n->next, pins->next); - rcu_assign_pointer(*ins, n); - return; - } - } - } - - /* Something went wrong if we are trying to replace a non-existant - * node. Mind as well halt instead of silently failing. - */ - BUG_ON(1); -} - -static void *rsvp_get(struct tcf_proto *tp, u32 handle) -{ - struct rsvp_head *head = rtnl_dereference(tp->root); - struct rsvp_session *s; - struct rsvp_filter *f; - unsigned int h1 = handle & 0xFF; - unsigned int h2 = (handle >> 8) & 0xFF; - - if (h2 > 16) - return NULL; - - for (s = rtnl_dereference(head->ht[h1]); s; - s = rtnl_dereference(s->next)) { - for (f = rtnl_dereference(s->ht[h2]); f; - f = rtnl_dereference(f->next)) { - if (f->handle == handle) - return f; - } - } - return NULL; -} - -static int rsvp_init(struct tcf_proto *tp) -{ - struct rsvp_head *data; - - data = kzalloc(sizeof(struct rsvp_head), GFP_KERNEL); - if (data) { - rcu_assign_pointer(tp->root, data); - return 0; - } - return -ENOBUFS; -} - -static void __rsvp_delete_filter(struct rsvp_filter *f) -{ - tcf_exts_destroy(&f->exts); - tcf_exts_put_net(&f->exts); - kfree(f); -} - -static void rsvp_delete_filter_work(struct work_struct *work) -{ - struct rsvp_filter *f = container_of(to_rcu_work(work), - struct rsvp_filter, - rwork); - rtnl_lock(); - __rsvp_delete_filter(f); - rtnl_unlock(); -} - -static void rsvp_delete_filter(struct tcf_proto *tp, struct rsvp_filter *f) -{ - tcf_unbind_filter(tp, &f->res); - /* all classifiers are required to call tcf_exts_destroy() after rcu - * grace period, since converted-to-rcu actions are relying on that - * in cleanup() callback - */ - if (tcf_exts_get_net(&f->exts)) - tcf_queue_work(&f->rwork, rsvp_delete_filter_work); - else - __rsvp_delete_filter(f); -} - -static void rsvp_destroy(struct tcf_proto *tp, struct netlink_ext_ack *extack) -{ - struct rsvp_head *data = rtnl_dereference(tp->root); - int h1, h2; - - if (data == NULL) - return; - - for (h1 = 0; h1 < 256; h1++) { - struct rsvp_session *s; - - while ((s = rtnl_dereference(data->ht[h1])) != NULL) { - RCU_INIT_POINTER(data->ht[h1], s->next); - - for (h2 = 0; h2 <= 16; h2++) { - struct rsvp_filter *f; - - while ((f = rtnl_dereference(s->ht[h2])) != NULL) { - rcu_assign_pointer(s->ht[h2], f->next); - rsvp_delete_filter(tp, f); - } - } - kfree_rcu(s, rcu); - } - } - kfree_rcu(data, rcu); -} - -static int rsvp_delete(struct tcf_proto *tp, void *arg, bool *last, - struct netlink_ext_ack *extack) -{ - struct rsvp_head *head = rtnl_dereference(tp->root); - struct rsvp_filter *nfp, *f = arg; - struct rsvp_filter __rcu **fp; - unsigned int h = f->handle; - struct rsvp_session __rcu **sp; - struct rsvp_session *nsp, *s = f->sess; - int i, h1; - - fp = &s->ht[(h >> 8) & 0xFF]; - for (nfp = rtnl_dereference(*fp); nfp; - fp = &nfp->next, nfp = rtnl_dereference(*fp)) { - if (nfp == f) { - RCU_INIT_POINTER(*fp, f->next); - rsvp_delete_filter(tp, f); - - /* Strip tree */ - - for (i = 0; i <= 16; i++) - if (s->ht[i]) - goto out; - - /* OK, session has no flows */ - sp = &head->ht[h & 0xFF]; - for (nsp = rtnl_dereference(*sp); nsp; - sp = &nsp->next, nsp = rtnl_dereference(*sp)) { - if (nsp == s) { - RCU_INIT_POINTER(*sp, s->next); - kfree_rcu(s, rcu); - goto out; - } - } - - break; - } - } - -out: - *last = true; - for (h1 = 0; h1 < 256; h1++) { - if (rcu_access_pointer(head->ht[h1])) { - *last = false; - break; - } - } - - return 0; -} - -static unsigned int gen_handle(struct tcf_proto *tp, unsigned salt) -{ - struct rsvp_head *data = rtnl_dereference(tp->root); - int i = 0xFFFF; - - while (i-- > 0) { - u32 h; - - if ((data->hgenerator += 0x10000) == 0) - data->hgenerator = 0x10000; - h = data->hgenerator|salt; - if (!rsvp_get(tp, h)) - return h; - } - return 0; -} - -static int tunnel_bts(struct rsvp_head *data) -{ - int n = data->tgenerator >> 5; - u32 b = 1 << (data->tgenerator & 0x1F); - - if (data->tmap[n] & b) - return 0; - data->tmap[n] |= b; - return 1; -} - -static void tunnel_recycle(struct rsvp_head *data) -{ - struct rsvp_session __rcu **sht = data->ht; - u32 tmap[256/32]; - int h1, h2; - - memset(tmap, 0, sizeof(tmap)); - - for (h1 = 0; h1 < 256; h1++) { - struct rsvp_session *s; - for (s = rtnl_dereference(sht[h1]); s; - s = rtnl_dereference(s->next)) { - for (h2 = 0; h2 <= 16; h2++) { - struct rsvp_filter *f; - - for (f = rtnl_dereference(s->ht[h2]); f; - f = rtnl_dereference(f->next)) { - if (f->tunnelhdr == 0) - continue; - data->tgenerator = f->res.classid; - tunnel_bts(data); - } - } - } - } - - memcpy(data->tmap, tmap, sizeof(tmap)); -} - -static u32 gen_tunnel(struct rsvp_head *data) -{ - int i, k; - - for (k = 0; k < 2; k++) { - for (i = 255; i > 0; i--) { - if (++data->tgenerator == 0) - data->tgenerator = 1; - if (tunnel_bts(data)) - return data->tgenerator; - } - tunnel_recycle(data); - } - return 0; -} - -static const struct nla_policy rsvp_policy[TCA_RSVP_MAX + 1] = { - [TCA_RSVP_CLASSID] = { .type = NLA_U32 }, - [TCA_RSVP_DST] = { .len = RSVP_DST_LEN * sizeof(u32) }, - [TCA_RSVP_SRC] = { .len = RSVP_DST_LEN * sizeof(u32) }, - [TCA_RSVP_PINFO] = { .len = sizeof(struct tc_rsvp_pinfo) }, -}; - -static int rsvp_change(struct net *net, struct sk_buff *in_skb, - struct tcf_proto *tp, unsigned long base, - u32 handle, - struct nlattr **tca, - void **arg, bool ovr, struct netlink_ext_ack *extack) -{ - struct rsvp_head *data = rtnl_dereference(tp->root); - struct rsvp_filter *f, *nfp; - struct rsvp_filter __rcu **fp; - struct rsvp_session *nsp, *s; - struct rsvp_session __rcu **sp; - struct tc_rsvp_pinfo *pinfo = NULL; - struct nlattr *opt = tca[TCA_OPTIONS]; - struct nlattr *tb[TCA_RSVP_MAX + 1]; - struct tcf_exts e; - unsigned int h1, h2; - __be32 *dst; - int err; - - if (opt == NULL) - return handle ? -EINVAL : 0; - - err = nla_parse_nested(tb, TCA_RSVP_MAX, opt, rsvp_policy, NULL); - if (err < 0) - return err; - - err = tcf_exts_init(&e, TCA_RSVP_ACT, TCA_RSVP_POLICE); - if (err < 0) - return err; - err = tcf_exts_validate(net, tp, tb, tca[TCA_RATE], &e, ovr, extack); - if (err < 0) - goto errout2; - - f = *arg; - if (f) { - /* Node exists: adjust only classid */ - struct rsvp_filter *n; - - if (f->handle != handle && handle) - goto errout2; - - n = kmemdup(f, sizeof(*f), GFP_KERNEL); - if (!n) { - err = -ENOMEM; - goto errout2; - } - - err = tcf_exts_init(&n->exts, TCA_RSVP_ACT, TCA_RSVP_POLICE); - if (err < 0) { - kfree(n); - goto errout2; - } - - if (tb[TCA_RSVP_CLASSID]) { - n->res.classid = nla_get_u32(tb[TCA_RSVP_CLASSID]); - tcf_bind_filter(tp, &n->res, base); - } - - tcf_exts_change(&n->exts, &e); - rsvp_replace(tp, n, handle); - return 0; - } - - /* Now more serious part... */ - err = -EINVAL; - if (handle) - goto errout2; - if (tb[TCA_RSVP_DST] == NULL) - goto errout2; - - err = -ENOBUFS; - f = kzalloc(sizeof(struct rsvp_filter), GFP_KERNEL); - if (f == NULL) - goto errout2; - - err = tcf_exts_init(&f->exts, TCA_RSVP_ACT, TCA_RSVP_POLICE); - if (err < 0) - goto errout; - h2 = 16; - if (tb[TCA_RSVP_SRC]) { - memcpy(f->src, nla_data(tb[TCA_RSVP_SRC]), sizeof(f->src)); - h2 = hash_src(f->src); - } - if (tb[TCA_RSVP_PINFO]) { - pinfo = nla_data(tb[TCA_RSVP_PINFO]); - f->spi = pinfo->spi; - f->tunnelhdr = pinfo->tunnelhdr; - } - if (tb[TCA_RSVP_CLASSID]) - f->res.classid = nla_get_u32(tb[TCA_RSVP_CLASSID]); - - dst = nla_data(tb[TCA_RSVP_DST]); - h1 = hash_dst(dst, pinfo ? pinfo->protocol : 0, pinfo ? pinfo->tunnelid : 0); - - err = -ENOMEM; - if ((f->handle = gen_handle(tp, h1 | (h2<<8))) == 0) - goto errout; - - if (f->tunnelhdr) { - err = -EINVAL; - if (f->res.classid > 255) - goto errout; - - err = -ENOMEM; - if (f->res.classid == 0 && - (f->res.classid = gen_tunnel(data)) == 0) - goto errout; - } - - for (sp = &data->ht[h1]; - (s = rtnl_dereference(*sp)) != NULL; - sp = &s->next) { - if (dst[RSVP_DST_LEN-1] == s->dst[RSVP_DST_LEN-1] && - pinfo && pinfo->protocol == s->protocol && - memcmp(&pinfo->dpi, &s->dpi, sizeof(s->dpi)) == 0 && -#if RSVP_DST_LEN == 4 - dst[0] == s->dst[0] && - dst[1] == s->dst[1] && - dst[2] == s->dst[2] && -#endif - pinfo->tunnelid == s->tunnelid) { - -insert: - /* OK, we found appropriate session */ - - fp = &s->ht[h2]; - - f->sess = s; - if (f->tunnelhdr == 0) - tcf_bind_filter(tp, &f->res, base); - - tcf_exts_change(&f->exts, &e); - - fp = &s->ht[h2]; - for (nfp = rtnl_dereference(*fp); nfp; - fp = &nfp->next, nfp = rtnl_dereference(*fp)) { - __u32 mask = nfp->spi.mask & f->spi.mask; - - if (mask != f->spi.mask) - break; - } - RCU_INIT_POINTER(f->next, nfp); - rcu_assign_pointer(*fp, f); - - *arg = f; - return 0; - } - } - - /* No session found. Create new one. */ - - err = -ENOBUFS; - s = kzalloc(sizeof(struct rsvp_session), GFP_KERNEL); - if (s == NULL) - goto errout; - memcpy(s->dst, dst, sizeof(s->dst)); - - if (pinfo) { - s->dpi = pinfo->dpi; - s->protocol = pinfo->protocol; - s->tunnelid = pinfo->tunnelid; - } - sp = &data->ht[h1]; - for (nsp = rtnl_dereference(*sp); nsp; - sp = &nsp->next, nsp = rtnl_dereference(*sp)) { - if ((nsp->dpi.mask & s->dpi.mask) != s->dpi.mask) - break; - } - RCU_INIT_POINTER(s->next, nsp); - rcu_assign_pointer(*sp, s); - - goto insert; - -errout: - tcf_exts_destroy(&f->exts); - kfree(f); -errout2: - tcf_exts_destroy(&e); - return err; -} - -static void rsvp_walk(struct tcf_proto *tp, struct tcf_walker *arg) -{ - struct rsvp_head *head = rtnl_dereference(tp->root); - unsigned int h, h1; - - if (arg->stop) - return; - - for (h = 0; h < 256; h++) { - struct rsvp_session *s; - - for (s = rtnl_dereference(head->ht[h]); s; - s = rtnl_dereference(s->next)) { - for (h1 = 0; h1 <= 16; h1++) { - struct rsvp_filter *f; - - for (f = rtnl_dereference(s->ht[h1]); f; - f = rtnl_dereference(f->next)) { - if (arg->count < arg->skip) { - arg->count++; - continue; - } - if (arg->fn(tp, f, arg) < 0) { - arg->stop = 1; - return; - } - arg->count++; - } - } - } - } -} - -static int rsvp_dump(struct net *net, struct tcf_proto *tp, void *fh, - struct sk_buff *skb, struct tcmsg *t) -{ - struct rsvp_filter *f = fh; - struct rsvp_session *s; - struct nlattr *nest; - struct tc_rsvp_pinfo pinfo; - - if (f == NULL) - return skb->len; - s = f->sess; - - t->tcm_handle = f->handle; - - nest = nla_nest_start(skb, TCA_OPTIONS); - if (nest == NULL) - goto nla_put_failure; - - if (nla_put(skb, TCA_RSVP_DST, sizeof(s->dst), &s->dst)) - goto nla_put_failure; - pinfo.dpi = s->dpi; - pinfo.spi = f->spi; - pinfo.protocol = s->protocol; - pinfo.tunnelid = s->tunnelid; - pinfo.tunnelhdr = f->tunnelhdr; - pinfo.pad = 0; - if (nla_put(skb, TCA_RSVP_PINFO, sizeof(pinfo), &pinfo)) - goto nla_put_failure; - if (f->res.classid && - nla_put_u32(skb, TCA_RSVP_CLASSID, f->res.classid)) - goto nla_put_failure; - if (((f->handle >> 8) & 0xFF) != 16 && - nla_put(skb, TCA_RSVP_SRC, sizeof(f->src), f->src)) - goto nla_put_failure; - - if (tcf_exts_dump(skb, &f->exts) < 0) - goto nla_put_failure; - - nla_nest_end(skb, nest); - - if (tcf_exts_dump_stats(skb, &f->exts) < 0) - goto nla_put_failure; - return skb->len; - -nla_put_failure: - nla_nest_cancel(skb, nest); - return -1; -} - -static void rsvp_bind_class(void *fh, u32 classid, unsigned long cl, void *q, - unsigned long base) -{ - struct rsvp_filter *f = fh; - - if (f && f->res.classid == classid) { - if (cl) - __tcf_bind_filter(q, &f->res, base); - else - __tcf_unbind_filter(q, &f->res); - } -} - -static struct tcf_proto_ops RSVP_OPS __read_mostly = { - .kind = RSVP_ID, - .classify = rsvp_classify, - .init = rsvp_init, - .destroy = rsvp_destroy, - .get = rsvp_get, - .change = rsvp_change, - .delete = rsvp_delete, - .walk = rsvp_walk, - .dump = rsvp_dump, - .bind_class = rsvp_bind_class, - .owner = THIS_MODULE, -}; - -static int __init init_rsvp(void) -{ - return register_tcf_proto_ops(&RSVP_OPS); -} - -static void __exit exit_rsvp(void) -{ - unregister_tcf_proto_ops(&RSVP_OPS); -} - -module_init(init_rsvp) -module_exit(exit_rsvp) diff --git a/net/sched/cls_rsvp6.c b/net/sched/cls_rsvp6.c deleted file mode 100644 index dd08aea2aee524b0f7ecddea5be17b72ceba20be..0000000000000000000000000000000000000000 --- a/net/sched/cls_rsvp6.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * net/sched/cls_rsvp6.c Special RSVP packet classifier for IPv6. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Authors: Alexey Kuznetsov, - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define RSVP_DST_LEN 4 -#define RSVP_ID "rsvp6" -#define RSVP_OPS cls_rsvp6_ops - -#include "cls_rsvp.h" -MODULE_LICENSE("GPL"); diff --git a/net/sched/cls_tcindex.c b/net/sched/cls_tcindex.c deleted file mode 100644 index 4070197f95439ce4921de1f9e6ab976679d05c30..0000000000000000000000000000000000000000 --- a/net/sched/cls_tcindex.c +++ /dev/null @@ -1,698 +0,0 @@ -/* - * net/sched/cls_tcindex.c Packet classifier for skb->tc_index - * - * Written 1998,1999 by Werner Almesberger, EPFL ICA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Passing parameters to the root seems to be done more awkwardly than really - * necessary. At least, u32 doesn't seem to use such dirty hacks. To be - * verified. FIXME. - */ - -#define PERFECT_HASH_THRESHOLD 64 /* use perfect hash if not bigger */ -#define DEFAULT_HASH_SIZE 64 /* optimized for diffserv */ - - -struct tcindex_filter_result { - struct tcf_exts exts; - struct tcf_result res; - struct rcu_work rwork; -}; - -struct tcindex_filter { - u16 key; - struct tcindex_filter_result result; - struct tcindex_filter __rcu *next; - struct rcu_work rwork; -}; - - -struct tcindex_data { - struct tcindex_filter_result *perfect; /* perfect hash; NULL if none */ - struct tcindex_filter __rcu **h; /* imperfect hash; */ - struct tcf_proto *tp; - u16 mask; /* AND key with mask */ - u32 shift; /* shift ANDed key to the right */ - u32 hash; /* hash table size; 0 if undefined */ - u32 alloc_hash; /* allocated size */ - u32 fall_through; /* 0: only classify if explicit match */ - struct rcu_work rwork; -}; - -static inline int tcindex_filter_is_set(struct tcindex_filter_result *r) -{ - return tcf_exts_has_actions(&r->exts) || r->res.classid; -} - -static struct tcindex_filter_result *tcindex_lookup(struct tcindex_data *p, - u16 key) -{ - if (p->perfect) { - struct tcindex_filter_result *f = p->perfect + key; - - return tcindex_filter_is_set(f) ? f : NULL; - } else if (p->h) { - struct tcindex_filter __rcu **fp; - struct tcindex_filter *f; - - fp = &p->h[key % p->hash]; - for (f = rcu_dereference_bh_rtnl(*fp); - f; - fp = &f->next, f = rcu_dereference_bh_rtnl(*fp)) - if (f->key == key) - return &f->result; - } - - return NULL; -} - - -static int tcindex_classify(struct sk_buff *skb, const struct tcf_proto *tp, - struct tcf_result *res) -{ - struct tcindex_data *p = rcu_dereference_bh(tp->root); - struct tcindex_filter_result *f; - int key = (skb->tc_index & p->mask) >> p->shift; - - pr_debug("tcindex_classify(skb %p,tp %p,res %p),p %p\n", - skb, tp, res, p); - - f = tcindex_lookup(p, key); - if (!f) { - struct Qdisc *q = tcf_block_q(tp->chain->block); - - if (!p->fall_through) - return -1; - res->classid = TC_H_MAKE(TC_H_MAJ(q->handle), key); - res->class = 0; - pr_debug("alg 0x%x\n", res->classid); - return 0; - } - *res = f->res; - pr_debug("map 0x%x\n", res->classid); - - return tcf_exts_exec(skb, &f->exts, res); -} - - -static void *tcindex_get(struct tcf_proto *tp, u32 handle) -{ - struct tcindex_data *p = rtnl_dereference(tp->root); - struct tcindex_filter_result *r; - - pr_debug("tcindex_get(tp %p,handle 0x%08x)\n", tp, handle); - if (p->perfect && handle >= p->alloc_hash) - return NULL; - r = tcindex_lookup(p, handle); - return r && tcindex_filter_is_set(r) ? r : NULL; -} - -static int tcindex_init(struct tcf_proto *tp) -{ - struct tcindex_data *p; - - pr_debug("tcindex_init(tp %p)\n", tp); - p = kzalloc(sizeof(struct tcindex_data), GFP_KERNEL); - if (!p) - return -ENOMEM; - - p->mask = 0xffff; - p->hash = DEFAULT_HASH_SIZE; - p->fall_through = 1; - - rcu_assign_pointer(tp->root, p); - return 0; -} - -static void __tcindex_destroy_rexts(struct tcindex_filter_result *r) -{ - tcf_exts_destroy(&r->exts); - tcf_exts_put_net(&r->exts); -} - -static void tcindex_destroy_rexts_work(struct work_struct *work) -{ - struct tcindex_filter_result *r; - - r = container_of(to_rcu_work(work), - struct tcindex_filter_result, - rwork); - rtnl_lock(); - __tcindex_destroy_rexts(r); - rtnl_unlock(); -} - -static void __tcindex_destroy_fexts(struct tcindex_filter *f) -{ - tcf_exts_destroy(&f->result.exts); - tcf_exts_put_net(&f->result.exts); - kfree(f); -} - -static void tcindex_destroy_fexts_work(struct work_struct *work) -{ - struct tcindex_filter *f = container_of(to_rcu_work(work), - struct tcindex_filter, - rwork); - - rtnl_lock(); - __tcindex_destroy_fexts(f); - rtnl_unlock(); -} - -static int tcindex_delete(struct tcf_proto *tp, void *arg, bool *last, - struct netlink_ext_ack *extack) -{ - struct tcindex_data *p = rtnl_dereference(tp->root); - struct tcindex_filter_result *r = arg; - struct tcindex_filter __rcu **walk; - struct tcindex_filter *f = NULL; - - pr_debug("tcindex_delete(tp %p,arg %p),p %p\n", tp, arg, p); - if (p->perfect) { - if (!r->res.class) - return -ENOENT; - } else { - int i; - - for (i = 0; i < p->hash; i++) { - walk = p->h + i; - for (f = rtnl_dereference(*walk); f; - walk = &f->next, f = rtnl_dereference(*walk)) { - if (&f->result == r) - goto found; - } - } - return -ENOENT; - -found: - rcu_assign_pointer(*walk, rtnl_dereference(f->next)); - } - tcf_unbind_filter(tp, &r->res); - /* all classifiers are required to call tcf_exts_destroy() after rcu - * grace period, since converted-to-rcu actions are relying on that - * in cleanup() callback - */ - if (f) { - if (tcf_exts_get_net(&f->result.exts)) - tcf_queue_work(&f->rwork, tcindex_destroy_fexts_work); - else - __tcindex_destroy_fexts(f); - } else { - if (tcf_exts_get_net(&r->exts)) - tcf_queue_work(&r->rwork, tcindex_destroy_rexts_work); - else - __tcindex_destroy_rexts(r); - } - - *last = false; - return 0; -} - -static void tcindex_destroy_work(struct work_struct *work) -{ - struct tcindex_data *p = container_of(to_rcu_work(work), - struct tcindex_data, - rwork); - - kfree(p->perfect); - kfree(p->h); - kfree(p); -} - -static inline int -valid_perfect_hash(struct tcindex_data *p) -{ - return p->hash > (p->mask >> p->shift); -} - -static const struct nla_policy tcindex_policy[TCA_TCINDEX_MAX + 1] = { - [TCA_TCINDEX_HASH] = { .type = NLA_U32 }, - [TCA_TCINDEX_MASK] = { .type = NLA_U16 }, - [TCA_TCINDEX_SHIFT] = { .type = NLA_U32 }, - [TCA_TCINDEX_FALL_THROUGH] = { .type = NLA_U32 }, - [TCA_TCINDEX_CLASSID] = { .type = NLA_U32 }, -}; - -static int tcindex_filter_result_init(struct tcindex_filter_result *r) -{ - memset(r, 0, sizeof(*r)); - return tcf_exts_init(&r->exts, TCA_TCINDEX_ACT, TCA_TCINDEX_POLICE); -} - -static void tcindex_partial_destroy_work(struct work_struct *work) -{ - struct tcindex_data *p = container_of(to_rcu_work(work), - struct tcindex_data, - rwork); - - kfree(p->perfect); - kfree(p); -} - -static void tcindex_free_perfect_hash(struct tcindex_data *cp) -{ - int i; - - for (i = 0; i < cp->hash; i++) - tcf_exts_destroy(&cp->perfect[i].exts); - kfree(cp->perfect); -} - -static int tcindex_alloc_perfect_hash(struct net *net, struct tcindex_data *cp) -{ - int i, err = 0; - - cp->perfect = kcalloc(cp->hash, sizeof(struct tcindex_filter_result), - GFP_KERNEL | __GFP_NOWARN); - if (!cp->perfect) - return -ENOMEM; - - for (i = 0; i < cp->hash; i++) { - err = tcf_exts_init(&cp->perfect[i].exts, - TCA_TCINDEX_ACT, TCA_TCINDEX_POLICE); - if (err < 0) - goto errout; -#ifdef CONFIG_NET_CLS_ACT - cp->perfect[i].exts.net = net; -#endif - } - - return 0; - -errout: - tcindex_free_perfect_hash(cp); - return err; -} - -static int -tcindex_set_parms(struct net *net, struct tcf_proto *tp, unsigned long base, - u32 handle, struct tcindex_data *p, - struct tcindex_filter_result *r, struct nlattr **tb, - struct nlattr *est, bool ovr, struct netlink_ext_ack *extack) -{ - struct tcindex_filter_result new_filter_result, *old_r = r; - struct tcindex_data *cp = NULL, *oldp; - struct tcindex_filter *f = NULL; /* make gcc behave */ - struct tcf_result cr = {}; - int err, balloc = 0; - struct tcf_exts e; - - err = tcf_exts_init(&e, TCA_TCINDEX_ACT, TCA_TCINDEX_POLICE); - if (err < 0) - return err; - err = tcf_exts_validate(net, tp, tb, est, &e, ovr, extack); - if (err < 0) - goto errout; - - err = -ENOMEM; - /* tcindex_data attributes must look atomic to classifier/lookup so - * allocate new tcindex data and RCU assign it onto root. Keeping - * perfect hash and hash pointers from old data. - */ - cp = kzalloc(sizeof(*cp), GFP_KERNEL); - if (!cp) - goto errout; - - cp->mask = p->mask; - cp->shift = p->shift; - cp->hash = p->hash; - cp->alloc_hash = p->alloc_hash; - cp->fall_through = p->fall_through; - cp->tp = tp; - - if (tb[TCA_TCINDEX_HASH]) - cp->hash = nla_get_u32(tb[TCA_TCINDEX_HASH]); - - if (tb[TCA_TCINDEX_MASK]) - cp->mask = nla_get_u16(tb[TCA_TCINDEX_MASK]); - - if (tb[TCA_TCINDEX_SHIFT]) { - cp->shift = nla_get_u32(tb[TCA_TCINDEX_SHIFT]); - if (cp->shift > 16) { - err = -EINVAL; - goto errout; - } - } - if (!cp->hash) { - /* Hash not specified, use perfect hash if the upper limit - * of the hashing index is below the threshold. - */ - if ((cp->mask >> cp->shift) < PERFECT_HASH_THRESHOLD) - cp->hash = (cp->mask >> cp->shift) + 1; - else - cp->hash = DEFAULT_HASH_SIZE; - } - - if (p->perfect) { - int i; - - if (tcindex_alloc_perfect_hash(net, cp) < 0) - goto errout; - cp->alloc_hash = cp->hash; - for (i = 0; i < min(cp->hash, p->hash); i++) - cp->perfect[i].res = p->perfect[i].res; - balloc = 1; - } - cp->h = p->h; - - err = tcindex_filter_result_init(&new_filter_result); - if (err < 0) - goto errout_alloc; - if (old_r) - cr = r->res; - - err = -EBUSY; - - /* Hash already allocated, make sure that we still meet the - * requirements for the allocated hash. - */ - if (cp->perfect) { - if (!valid_perfect_hash(cp) || - cp->hash > cp->alloc_hash) - goto errout_alloc; - } else if (cp->h && cp->hash != cp->alloc_hash) { - goto errout_alloc; - } - - err = -EINVAL; - if (tb[TCA_TCINDEX_FALL_THROUGH]) - cp->fall_through = nla_get_u32(tb[TCA_TCINDEX_FALL_THROUGH]); - - if (!cp->perfect && !cp->h) - cp->alloc_hash = cp->hash; - - /* Note: this could be as restrictive as if (handle & ~(mask >> shift)) - * but then, we'd fail handles that may become valid after some future - * mask change. While this is extremely unlikely to ever matter, - * the check below is safer (and also more backwards-compatible). - */ - if (cp->perfect || valid_perfect_hash(cp)) - if (handle >= cp->alloc_hash) - goto errout_alloc; - - - err = -ENOMEM; - if (!cp->perfect && !cp->h) { - if (valid_perfect_hash(cp)) { - if (tcindex_alloc_perfect_hash(net, cp) < 0) - goto errout_alloc; - balloc = 1; - } else { - struct tcindex_filter __rcu **hash; - - hash = kcalloc(cp->hash, - sizeof(struct tcindex_filter *), - GFP_KERNEL); - - if (!hash) - goto errout_alloc; - - cp->h = hash; - balloc = 2; - } - } - - if (cp->perfect) - r = cp->perfect + handle; - else - r = tcindex_lookup(cp, handle) ? : &new_filter_result; - - if (r == &new_filter_result) { - f = kzalloc(sizeof(*f), GFP_KERNEL); - if (!f) - goto errout_alloc; - f->key = handle; - f->next = NULL; - err = tcindex_filter_result_init(&f->result); - if (err < 0) { - kfree(f); - goto errout_alloc; - } - } - - if (tb[TCA_TCINDEX_CLASSID]) { - cr.classid = nla_get_u32(tb[TCA_TCINDEX_CLASSID]); - tcf_bind_filter(tp, &cr, base); - } - - if (old_r && old_r != r) { - err = tcindex_filter_result_init(old_r); - if (err < 0) { - kfree(f); - goto errout_alloc; - } - } - - oldp = p; - r->res = cr; - tcf_exts_change(&r->exts, &e); - - rcu_assign_pointer(tp->root, cp); - - if (r == &new_filter_result) { - struct tcindex_filter *nfp; - struct tcindex_filter __rcu **fp; - - f->result.res = r->res; - tcf_exts_change(&f->result.exts, &r->exts); - - fp = cp->h + (handle % cp->hash); - for (nfp = rtnl_dereference(*fp); - nfp; - fp = &nfp->next, nfp = rtnl_dereference(*fp)) - ; /* nothing */ - - rcu_assign_pointer(*fp, f); - } else { - tcf_exts_destroy(&new_filter_result.exts); - } - - if (oldp) - tcf_queue_work(&oldp->rwork, tcindex_partial_destroy_work); - return 0; - -errout_alloc: - if (balloc == 1) - tcindex_free_perfect_hash(cp); - else if (balloc == 2) - kfree(cp->h); - tcf_exts_destroy(&new_filter_result.exts); -errout: - kfree(cp); - tcf_exts_destroy(&e); - return err; -} - -static int -tcindex_change(struct net *net, struct sk_buff *in_skb, - struct tcf_proto *tp, unsigned long base, u32 handle, - struct nlattr **tca, void **arg, bool ovr, - struct netlink_ext_ack *extack) -{ - struct nlattr *opt = tca[TCA_OPTIONS]; - struct nlattr *tb[TCA_TCINDEX_MAX + 1]; - struct tcindex_data *p = rtnl_dereference(tp->root); - struct tcindex_filter_result *r = *arg; - int err; - - pr_debug("tcindex_change(tp %p,handle 0x%08x,tca %p,arg %p),opt %p," - "p %p,r %p,*arg %p\n", - tp, handle, tca, arg, opt, p, r, arg ? *arg : NULL); - - if (!opt) - return 0; - - err = nla_parse_nested(tb, TCA_TCINDEX_MAX, opt, tcindex_policy, NULL); - if (err < 0) - return err; - - return tcindex_set_parms(net, tp, base, handle, p, r, tb, - tca[TCA_RATE], ovr, extack); -} - -static void tcindex_walk(struct tcf_proto *tp, struct tcf_walker *walker) -{ - struct tcindex_data *p = rtnl_dereference(tp->root); - struct tcindex_filter *f, *next; - int i; - - pr_debug("tcindex_walk(tp %p,walker %p),p %p\n", tp, walker, p); - if (p->perfect) { - for (i = 0; i < p->hash; i++) { - if (!p->perfect[i].res.class) - continue; - if (walker->count >= walker->skip) { - if (walker->fn(tp, p->perfect + i, walker) < 0) { - walker->stop = 1; - return; - } - } - walker->count++; - } - } - if (!p->h) - return; - for (i = 0; i < p->hash; i++) { - for (f = rtnl_dereference(p->h[i]); f; f = next) { - next = rtnl_dereference(f->next); - if (walker->count >= walker->skip) { - if (walker->fn(tp, &f->result, walker) < 0) { - walker->stop = 1; - return; - } - } - walker->count++; - } - } -} - -static void tcindex_destroy(struct tcf_proto *tp, - struct netlink_ext_ack *extack) -{ - struct tcindex_data *p = rtnl_dereference(tp->root); - int i; - - pr_debug("tcindex_destroy(tp %p),p %p\n", tp, p); - - if (p->perfect) { - for (i = 0; i < p->hash; i++) { - struct tcindex_filter_result *r = p->perfect + i; - - tcf_unbind_filter(tp, &r->res); - if (tcf_exts_get_net(&r->exts)) - tcf_queue_work(&r->rwork, - tcindex_destroy_rexts_work); - else - __tcindex_destroy_rexts(r); - } - } - - for (i = 0; p->h && i < p->hash; i++) { - struct tcindex_filter *f, *next; - bool last; - - for (f = rtnl_dereference(p->h[i]); f; f = next) { - next = rtnl_dereference(f->next); - tcindex_delete(tp, &f->result, &last, NULL); - } - } - - tcf_queue_work(&p->rwork, tcindex_destroy_work); -} - - -static int tcindex_dump(struct net *net, struct tcf_proto *tp, void *fh, - struct sk_buff *skb, struct tcmsg *t) -{ - struct tcindex_data *p = rtnl_dereference(tp->root); - struct tcindex_filter_result *r = fh; - struct nlattr *nest; - - pr_debug("tcindex_dump(tp %p,fh %p,skb %p,t %p),p %p,r %p\n", - tp, fh, skb, t, p, r); - pr_debug("p->perfect %p p->h %p\n", p->perfect, p->h); - - nest = nla_nest_start(skb, TCA_OPTIONS); - if (nest == NULL) - goto nla_put_failure; - - if (!fh) { - t->tcm_handle = ~0; /* whatever ... */ - if (nla_put_u32(skb, TCA_TCINDEX_HASH, p->hash) || - nla_put_u16(skb, TCA_TCINDEX_MASK, p->mask) || - nla_put_u32(skb, TCA_TCINDEX_SHIFT, p->shift) || - nla_put_u32(skb, TCA_TCINDEX_FALL_THROUGH, p->fall_through)) - goto nla_put_failure; - nla_nest_end(skb, nest); - } else { - if (p->perfect) { - t->tcm_handle = r - p->perfect; - } else { - struct tcindex_filter *f; - struct tcindex_filter __rcu **fp; - int i; - - t->tcm_handle = 0; - for (i = 0; !t->tcm_handle && i < p->hash; i++) { - fp = &p->h[i]; - for (f = rtnl_dereference(*fp); - !t->tcm_handle && f; - fp = &f->next, f = rtnl_dereference(*fp)) { - if (&f->result == r) - t->tcm_handle = f->key; - } - } - } - pr_debug("handle = %d\n", t->tcm_handle); - if (r->res.class && - nla_put_u32(skb, TCA_TCINDEX_CLASSID, r->res.classid)) - goto nla_put_failure; - - if (tcf_exts_dump(skb, &r->exts) < 0) - goto nla_put_failure; - nla_nest_end(skb, nest); - - if (tcf_exts_dump_stats(skb, &r->exts) < 0) - goto nla_put_failure; - } - - return skb->len; - -nla_put_failure: - nla_nest_cancel(skb, nest); - return -1; -} - -static void tcindex_bind_class(void *fh, u32 classid, unsigned long cl, - void *q, unsigned long base) -{ - struct tcindex_filter_result *r = fh; - - if (r && r->res.classid == classid) { - if (cl) - __tcf_bind_filter(q, &r->res, base); - else - __tcf_unbind_filter(q, &r->res); - } -} - -static struct tcf_proto_ops cls_tcindex_ops __read_mostly = { - .kind = "tcindex", - .classify = tcindex_classify, - .init = tcindex_init, - .destroy = tcindex_destroy, - .get = tcindex_get, - .change = tcindex_change, - .delete = tcindex_delete, - .walk = tcindex_walk, - .dump = tcindex_dump, - .bind_class = tcindex_bind_class, - .owner = THIS_MODULE, -}; - -static int __init init_tcindex(void) -{ - return register_tcf_proto_ops(&cls_tcindex_ops); -} - -static void __exit exit_tcindex(void) -{ - unregister_tcf_proto_ops(&cls_tcindex_ops); -} - -module_init(init_tcindex) -module_exit(exit_tcindex) -MODULE_LICENSE("GPL"); diff --git a/net/sched/cls_u32.c b/net/sched/cls_u32.c index d30256ac35372e359a906243cfcf8f19baa1156a..1e71ff093c91d6cc4108547b558acd5e0dd1d5a4 100644 --- a/net/sched/cls_u32.c +++ b/net/sched/cls_u32.c @@ -778,11 +778,22 @@ static int u32_set_parms(struct net *net, struct tcf_proto *tp, struct netlink_ext_ack *extack) { int err; +#ifdef CONFIG_NET_CLS_IND + int ifindex = -1; +#endif err = tcf_exts_validate(net, tp, tb, est, &n->exts, ovr, extack); if (err < 0) return err; +#ifdef CONFIG_NET_CLS_IND + if (tb[TCA_U32_INDEV]) { + ifindex = tcf_change_indev(net, tb[TCA_U32_INDEV], extack); + if (ifindex < 0) + return -EINVAL; + } +#endif + if (tb[TCA_U32_LINK]) { u32 handle = nla_get_u32(tb[TCA_U32_LINK]); struct tc_u_hnode *ht_down = NULL, *ht_old; @@ -814,13 +825,8 @@ static int u32_set_parms(struct net *net, struct tcf_proto *tp, } #ifdef CONFIG_NET_CLS_IND - if (tb[TCA_U32_INDEV]) { - int ret; - ret = tcf_change_indev(net, tb[TCA_U32_INDEV], extack); - if (ret < 0) - return -EINVAL; - n->ifindex = ret; - } + if (ifindex >= 0) + n->ifindex = ifindex; #endif return 0; } @@ -873,7 +879,6 @@ static struct tc_u_knode *u32_init_knode(struct tcf_proto *tp, new->ifindex = n->ifindex; #endif new->fshift = n->fshift; - new->res = n->res; new->flags = n->flags; RCU_INIT_POINTER(new->ht_down, ht); @@ -1061,18 +1066,62 @@ static int u32_change(struct net *net, struct sk_buff *in_skb, return -EINVAL; } + /* At this point, we need to derive the new handle that will be used to + * uniquely map the identity of this table match entry. The + * identity of the entry that we need to construct is 32 bits made of: + * htid(12b):bucketid(8b):node/entryid(12b) + * + * At this point _we have the table(ht)_ in which we will insert this + * entry. We carry the table's id in variable "htid". + * Note that earlier code picked the ht selection either by a) the user + * providing the htid specified via TCA_U32_HASH attribute or b) when + * no such attribute is passed then the root ht, is default to at ID + * 0x[800][00][000]. Rule: the root table has a single bucket with ID 0. + * If OTOH the user passed us the htid, they may also pass a bucketid of + * choice. 0 is fine. For example a user htid is 0x[600][01][000] it is + * indicating hash bucketid of 1. Rule: the entry/node ID _cannot_ be + * passed via the htid, so even if it was non-zero it will be ignored. + * + * We may also have a handle, if the user passed one. The handle also + * carries the same addressing of htid(12b):bucketid(8b):node/entryid(12b). + * Rule: the bucketid on the handle is ignored even if one was passed; + * rather the value on "htid" is always assumed to be the bucketid. + */ if (handle) { + /* Rule: The htid from handle and tableid from htid must match */ if (TC_U32_HTID(handle) && TC_U32_HTID(handle ^ htid)) { NL_SET_ERR_MSG_MOD(extack, "Handle specified hash table address mismatch"); return -EINVAL; } - handle = htid | TC_U32_NODE(handle); - err = idr_alloc_u32(&ht->handle_idr, NULL, &handle, handle, - GFP_KERNEL); - if (err) - return err; - } else + /* Ok, so far we have a valid htid(12b):bucketid(8b) but we + * need to finalize the table entry identification with the last + * part - the node/entryid(12b)). Rule: Nodeid _cannot be 0_ for + * entries. Rule: nodeid of 0 is reserved only for tables(see + * earlier code which processes TC_U32_DIVISOR attribute). + * Rule: The nodeid can only be derived from the handle (and not + * htid). + * Rule: if the handle specified zero for the node id example + * 0x60000000, then pick a new nodeid from the pool of IDs + * this hash table has been allocating from. + * If OTOH it is specified (i.e for example the user passed a + * handle such as 0x60000123), then we use it generate our final + * handle which is used to uniquely identify the match entry. + */ + if (!TC_U32_NODE(handle)) { + handle = gen_new_kid(ht, htid); + } else { + handle = htid | TC_U32_NODE(handle); + err = idr_alloc_u32(&ht->handle_idr, NULL, &handle, + handle, GFP_KERNEL); + if (err) + return err; + } + } else { + /* The user did not give us a handle; lets just generate one + * from the table's pool of nodeids. + */ handle = gen_new_kid(ht, htid); + } if (tb[TCA_U32_SEL] == NULL) { NL_SET_ERR_MSG_MOD(extack, "Selector not specified"); diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c index 912c7abbd2236bf5df10ccb56d08c6c91079c5f3..30bd2f97f5309a9fabb6fb450128516779694027 100644 --- a/net/sched/sch_api.c +++ b/net/sched/sch_api.c @@ -1004,12 +1004,13 @@ static int qdisc_graft(struct net_device *dev, struct Qdisc *parent, skip: if (!ingress) { - notify_and_destroy(net, skb, n, classid, - dev->qdisc, new); + old = dev->qdisc; if (new && !new->ops->attach) qdisc_refcount_inc(new); dev->qdisc = new ? : &noop_qdisc; + notify_and_destroy(net, skb, n, classid, old, new); + if (new && new->ops->attach) new->ops->attach(new); } else { @@ -1148,7 +1149,12 @@ static struct Qdisc *qdisc_create(struct net_device *dev, sch->parent = parent; if (handle == TC_H_INGRESS) { - sch->flags |= TCQ_F_INGRESS; + if (!(sch->flags & TCQ_F_INGRESS)) { + NL_SET_ERR_MSG(extack, + "Specified parent ID is reserved for ingress and clsact Qdiscs"); + err = -EINVAL; + goto err_out3; + } handle = TC_H_MAKE(TC_H_INGRESS, 0); lockdep_set_class(qdisc_lock(sch), &qdisc_rx_lock); } else { @@ -1433,6 +1439,25 @@ static int tc_get_qdisc(struct sk_buff *skb, struct nlmsghdr *n, return 0; } +static bool req_create_or_replace(struct nlmsghdr *n) +{ + return (n->nlmsg_flags & NLM_F_CREATE && + n->nlmsg_flags & NLM_F_REPLACE); +} + +static bool req_create_exclusive(struct nlmsghdr *n) +{ + return (n->nlmsg_flags & NLM_F_CREATE && + n->nlmsg_flags & NLM_F_EXCL); +} + +static bool req_change(struct nlmsghdr *n) +{ + return (!(n->nlmsg_flags & NLM_F_CREATE) && + !(n->nlmsg_flags & NLM_F_REPLACE) && + !(n->nlmsg_flags & NLM_F_EXCL)); +} + /* * enable/disable flow on qdisc. */ @@ -1470,7 +1495,6 @@ EXPORT_SYMBOL(tc_qdisc_flow_control); /* * Create/change qdisc. */ - static int tc_modify_qdisc(struct sk_buff *skb, struct nlmsghdr *n, struct netlink_ext_ack *extack) { @@ -1543,11 +1567,20 @@ static int tc_modify_qdisc(struct sk_buff *skb, struct nlmsghdr *n, NL_SET_ERR_MSG(extack, "Invalid qdisc name"); return -EINVAL; } + if (q->flags & TCQ_F_INGRESS) { + NL_SET_ERR_MSG(extack, + "Cannot regraft ingress or clsact Qdiscs"); + return -EINVAL; + } if (q == p || (p && check_loop(q, p, 0))) { NL_SET_ERR_MSG(extack, "Qdisc parent/child loop detected"); return -ELOOP; } + if (clid == TC_H_INGRESS) { + NL_SET_ERR_MSG(extack, "Ingress cannot graft directly"); + return -EINVAL; + } qdisc_refcount_inc(q); goto graft; } else { @@ -1558,27 +1591,35 @@ static int tc_modify_qdisc(struct sk_buff *skb, struct nlmsghdr *n, * * We know, that some child q is already * attached to this parent and have choice: - * either to change it or to create/graft new one. + * 1) change it or 2) create/graft new one. + * If the requested qdisc kind is different + * than the existing one, then we choose graft. + * If they are the same then this is "change" + * operation - just let it fallthrough.. * * 1. We are allowed to create/graft only - * if CREATE and REPLACE flags are set. + * if the request is explicitly stating + * "please create if it doesn't exist". * - * 2. If EXCL is set, requestor wanted to say, - * that qdisc tcm_handle is not expected + * 2. If the request is to exclusive create + * then the qdisc tcm_handle is not expected * to exist, so that we choose create/graft too. * * 3. The last case is when no flags are set. + * This will happen when for example tc + * utility issues a "change" command. * Alas, it is sort of hole in API, we * cannot decide what to do unambiguously. - * For now we select create/graft, if - * user gave KIND, which does not match existing. + * For now we select create/graft. */ - if ((n->nlmsg_flags & NLM_F_CREATE) && - (n->nlmsg_flags & NLM_F_REPLACE) && - ((n->nlmsg_flags & NLM_F_EXCL) || - (tca[TCA_KIND] && - nla_strcmp(tca[TCA_KIND], q->ops->id)))) - goto create_n_graft; + if (tca[TCA_KIND] && + nla_strcmp(tca[TCA_KIND], q->ops->id)) { + if (req_create_or_replace(n) || + req_create_exclusive(n)) + goto create_n_graft; + else if (req_change(n)) + goto create_n_graft2; + } } } } else { @@ -1612,6 +1653,7 @@ static int tc_modify_qdisc(struct sk_buff *skb, struct nlmsghdr *n, NL_SET_ERR_MSG(extack, "Qdisc not found. To create specify NLM_F_CREATE flag"); return -ENOENT; } +create_n_graft2: if (clid == TC_H_INGRESS) { if (dev_ingress_queue(dev)) { q = qdisc_create(dev, dev_ingress_queue(dev), p, diff --git a/net/sched/sch_cake.c b/net/sched/sch_cake.c index 01a177cfa5333711671bb20c03175d242eb035c7..d91665ea7b14da1796bdfcfdfc29a17dd2a688bb 100644 --- a/net/sched/sch_cake.c +++ b/net/sched/sch_cake.c @@ -1649,7 +1649,7 @@ static s32 cake_enqueue(struct sk_buff *skb, struct Qdisc *sch, { struct cake_sched_data *q = qdisc_priv(sch); int len = qdisc_pkt_len(skb); - int uninitialized_var(ret); + int ret; struct sk_buff *ack = NULL; ktime_t now = ktime_get(); struct cake_tin_data *b; diff --git a/net/sched/sch_cbq.c b/net/sched/sch_cbq.c index 0a76ad05e5ae58cb988fbbe5e951b0a48e352b3e..7f0a5d22deaf66b63b142d618bcff8ff2c7859a6 100644 --- a/net/sched/sch_cbq.c +++ b/net/sched/sch_cbq.c @@ -236,6 +236,8 @@ cbq_classify(struct sk_buff *skb, struct Qdisc *sch, int *qerr) result = tcf_classify(skb, fl, &res, true); if (!fl || result < 0) goto fallback; + if (result == TC_ACT_SHOT) + return NULL; cl = (void *)res.class; if (!cl) { @@ -256,8 +258,6 @@ cbq_classify(struct sk_buff *skb, struct Qdisc *sch, int *qerr) case TC_ACT_TRAP: *qerr = NET_XMIT_SUCCESS | __NET_XMIT_STOLEN; /* fall through */ - case TC_ACT_SHOT: - return NULL; case TC_ACT_RECLASSIFY: return cbq_reclassify(skb, cl); } @@ -365,7 +365,7 @@ cbq_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) { struct cbq_sched_data *q = qdisc_priv(sch); - int uninitialized_var(ret); + int ret; struct cbq_class *cl = cbq_classify(skb, sch, &ret); #ifdef CONFIG_NET_CLS_ACT diff --git a/net/sched/sch_fq_codel.c b/net/sched/sch_fq_codel.c index e4f69c779b8cfd619fe79aa2df942a74d9d8c152..7a4777ee0536e98eedd7694e7367825998c7f44a 100644 --- a/net/sched/sch_fq_codel.c +++ b/net/sched/sch_fq_codel.c @@ -192,7 +192,7 @@ static int fq_codel_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct fq_codel_sched_data *q = qdisc_priv(sch); unsigned int idx, prev_backlog, prev_qlen; struct fq_codel_flow *flow; - int uninitialized_var(ret); + int ret; unsigned int pkt_len; bool memory_limited; diff --git a/net/sched/sch_hfsc.c b/net/sched/sch_hfsc.c index b18ec1f6de60cf584f8a2f421c5cbabfca188ff1..e71443623d679e797c215b06e12611b84ec8ff28 100644 --- a/net/sched/sch_hfsc.c +++ b/net/sched/sch_hfsc.c @@ -913,6 +913,14 @@ hfsc_change_usc(struct hfsc_class *cl, struct tc_service_curve *usc, cl->cl_flags |= HFSC_USC; } +static void +hfsc_upgrade_rt(struct hfsc_class *cl) +{ + cl->cl_fsc = cl->cl_rsc; + rtsc_init(&cl->cl_virtual, &cl->cl_fsc, cl->cl_vt, cl->cl_total); + cl->cl_flags |= HFSC_FSC; +} + static const struct nla_policy hfsc_policy[TCA_HFSC_MAX + 1] = { [TCA_HFSC_RSC] = { .len = sizeof(struct tc_service_curve) }, [TCA_HFSC_FSC] = { .len = sizeof(struct tc_service_curve) }, @@ -1073,6 +1081,12 @@ hfsc_change_class(struct Qdisc *sch, u32 classid, u32 parentid, cl->cf_tree = RB_ROOT; sch_tree_lock(sch); + /* Check if the inner class is a misconfigured 'rt' */ + if (!(parent->cl_flags & HFSC_FSC) && parent != &q->root) { + NL_SET_ERR_MSG(extack, + "Forced curve change on parent 'rt' to 'sc'"); + hfsc_upgrade_rt(parent); + } qdisc_class_hash_insert(&q->clhash, &cl->cl_common); list_add_tail(&cl->siblings, &parent->children); if (parent->level == 0) diff --git a/net/sched/sch_ingress.c b/net/sched/sch_ingress.c index ce3f55259d0d1a9024e0d553f0a0b3e101697430..834960cc755e22616a3a68f738cfee031f380981 100644 --- a/net/sched/sch_ingress.c +++ b/net/sched/sch_ingress.c @@ -83,6 +83,9 @@ static int ingress_init(struct Qdisc *sch, struct nlattr *opt, struct ingress_sched_data *q = qdisc_priv(sch); struct net_device *dev = qdisc_dev(sch); + if (sch->parent != TC_H_INGRESS) + return -EOPNOTSUPP; + net_inc_ingress_queue(); mini_qdisc_pair_init(&q->miniqp, sch, &dev->miniq_ingress); @@ -98,6 +101,9 @@ static void ingress_destroy(struct Qdisc *sch) { struct ingress_sched_data *q = qdisc_priv(sch); + if (sch->parent != TC_H_INGRESS) + return; + tcf_block_put_ext(q->block, sch, &q->block_info); net_dec_ingress_queue(); } @@ -130,7 +136,7 @@ static struct Qdisc_ops ingress_qdisc_ops __read_mostly = { .cl_ops = &ingress_class_ops, .id = "ingress", .priv_size = sizeof(struct ingress_sched_data), - .static_flags = TCQ_F_CPUSTATS, + .static_flags = TCQ_F_INGRESS | TCQ_F_CPUSTATS, .init = ingress_init, .destroy = ingress_destroy, .dump = ingress_dump, @@ -215,6 +221,9 @@ static int clsact_init(struct Qdisc *sch, struct nlattr *opt, struct net_device *dev = qdisc_dev(sch); int err; + if (sch->parent != TC_H_CLSACT) + return -EOPNOTSUPP; + net_inc_ingress_queue(); net_inc_egress_queue(); @@ -242,6 +251,9 @@ static void clsact_destroy(struct Qdisc *sch) { struct clsact_sched_data *q = qdisc_priv(sch); + if (sch->parent != TC_H_CLSACT) + return; + tcf_block_put_ext(q->egress_block, sch, &q->egress_block_info); tcf_block_put_ext(q->ingress_block, sch, &q->ingress_block_info); @@ -262,7 +274,7 @@ static struct Qdisc_ops clsact_qdisc_ops __read_mostly = { .cl_ops = &clsact_class_ops, .id = "clsact", .priv_size = sizeof(struct clsact_sched_data), - .static_flags = TCQ_F_CPUSTATS, + .static_flags = TCQ_F_INGRESS | TCQ_F_CPUSTATS, .init = clsact_init, .destroy = clsact_destroy, .dump = ingress_dump, diff --git a/net/sched/sch_mqprio.c b/net/sched/sch_mqprio.c index 69fd70554786e5b26512add21851654365f0ada7..c776a89ba137a53ae9a921b23a998362e0b67b84 100644 --- a/net/sched/sch_mqprio.c +++ b/net/sched/sch_mqprio.c @@ -132,6 +132,97 @@ static int parse_attr(struct nlattr *tb[], int maxtype, struct nlattr *nla, return 0; } +static int mqprio_parse_nlattr(struct Qdisc *sch, struct tc_mqprio_qopt *qopt, + struct nlattr *opt, + struct netlink_ext_ack *extack) +{ + struct mqprio_sched *priv = qdisc_priv(sch); + struct nlattr *tb[TCA_MQPRIO_MAX + 1]; + struct nlattr *attr; + int i, rem, err; + + err = parse_attr(tb, TCA_MQPRIO_MAX, opt, mqprio_policy, + sizeof(*qopt)); + if (err < 0) + return err; + + if (!qopt->hw) { + NL_SET_ERR_MSG(extack, + "mqprio TCA_OPTIONS can only contain netlink attributes in hardware mode"); + return -EINVAL; + } + + if (tb[TCA_MQPRIO_MODE]) { + priv->flags |= TC_MQPRIO_F_MODE; + priv->mode = *(u16 *)nla_data(tb[TCA_MQPRIO_MODE]); + } + + if (tb[TCA_MQPRIO_SHAPER]) { + priv->flags |= TC_MQPRIO_F_SHAPER; + priv->shaper = *(u16 *)nla_data(tb[TCA_MQPRIO_SHAPER]); + } + + if (tb[TCA_MQPRIO_MIN_RATE64]) { + if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) { + NL_SET_ERR_MSG_ATTR(extack, tb[TCA_MQPRIO_MIN_RATE64], + "min_rate accepted only when shaper is in bw_rlimit mode"); + return -EINVAL; + } + i = 0; + nla_for_each_nested(attr, tb[TCA_MQPRIO_MIN_RATE64], + rem) { + if (nla_type(attr) != TCA_MQPRIO_MIN_RATE64) { + NL_SET_ERR_MSG_ATTR(extack, attr, + "Attribute type expected to be TCA_MQPRIO_MIN_RATE64"); + return -EINVAL; + } + + if (nla_len(attr) != sizeof(u64)) { + NL_SET_ERR_MSG_ATTR(extack, attr, + "Attribute TCA_MQPRIO_MIN_RATE64 expected to have 8 bytes length"); + return -EINVAL; + } + + if (i >= qopt->num_tc) + break; + priv->min_rate[i] = *(u64 *)nla_data(attr); + i++; + } + priv->flags |= TC_MQPRIO_F_MIN_RATE; + } + + if (tb[TCA_MQPRIO_MAX_RATE64]) { + if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) { + NL_SET_ERR_MSG_ATTR(extack, tb[TCA_MQPRIO_MAX_RATE64], + "max_rate accepted only when shaper is in bw_rlimit mode"); + return -EINVAL; + } + i = 0; + nla_for_each_nested(attr, tb[TCA_MQPRIO_MAX_RATE64], + rem) { + if (nla_type(attr) != TCA_MQPRIO_MAX_RATE64) { + NL_SET_ERR_MSG_ATTR(extack, attr, + "Attribute type expected to be TCA_MQPRIO_MAX_RATE64"); + return -EINVAL; + } + + if (nla_len(attr) != sizeof(u64)) { + NL_SET_ERR_MSG_ATTR(extack, attr, + "Attribute TCA_MQPRIO_MAX_RATE64 expected to have 8 bytes length"); + return -EINVAL; + } + + if (i >= qopt->num_tc) + break; + priv->max_rate[i] = *(u64 *)nla_data(attr); + i++; + } + priv->flags |= TC_MQPRIO_F_MAX_RATE; + } + + return 0; +} + static int mqprio_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) { @@ -141,9 +232,6 @@ static int mqprio_init(struct Qdisc *sch, struct nlattr *opt, struct Qdisc *qdisc; int i, err = -EOPNOTSUPP; struct tc_mqprio_qopt *qopt = NULL; - struct nlattr *tb[TCA_MQPRIO_MAX + 1]; - struct nlattr *attr; - int rem; int len; BUILD_BUG_ON(TC_MAX_QUEUE != TC_QOPT_MAX_QUEUE); @@ -168,55 +256,9 @@ static int mqprio_init(struct Qdisc *sch, struct nlattr *opt, len = nla_len(opt) - NLA_ALIGN(sizeof(*qopt)); if (len > 0) { - err = parse_attr(tb, TCA_MQPRIO_MAX, opt, mqprio_policy, - sizeof(*qopt)); - if (err < 0) + err = mqprio_parse_nlattr(sch, qopt, opt, extack); + if (err) return err; - - if (!qopt->hw) - return -EINVAL; - - if (tb[TCA_MQPRIO_MODE]) { - priv->flags |= TC_MQPRIO_F_MODE; - priv->mode = *(u16 *)nla_data(tb[TCA_MQPRIO_MODE]); - } - - if (tb[TCA_MQPRIO_SHAPER]) { - priv->flags |= TC_MQPRIO_F_SHAPER; - priv->shaper = *(u16 *)nla_data(tb[TCA_MQPRIO_SHAPER]); - } - - if (tb[TCA_MQPRIO_MIN_RATE64]) { - if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) - return -EINVAL; - i = 0; - nla_for_each_nested(attr, tb[TCA_MQPRIO_MIN_RATE64], - rem) { - if (nla_type(attr) != TCA_MQPRIO_MIN_RATE64) - return -EINVAL; - if (i >= qopt->num_tc) - break; - priv->min_rate[i] = *(u64 *)nla_data(attr); - i++; - } - priv->flags |= TC_MQPRIO_F_MIN_RATE; - } - - if (tb[TCA_MQPRIO_MAX_RATE64]) { - if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) - return -EINVAL; - i = 0; - nla_for_each_nested(attr, tb[TCA_MQPRIO_MAX_RATE64], - rem) { - if (nla_type(attr) != TCA_MQPRIO_MAX_RATE64) - return -EINVAL; - if (i >= qopt->num_tc) - break; - priv->max_rate[i] = *(u64 *)nla_data(attr); - i++; - } - priv->flags |= TC_MQPRIO_F_MAX_RATE; - } } /* pre-allocate qdisc, attachment can't fail */ diff --git a/net/sched/sch_netem.c b/net/sched/sch_netem.c index 31793af1a77bde3d272e0b478a3ebb81d76cc136..cf93dbe3d040c883ce45683e65999946fd53d4fa 100644 --- a/net/sched/sch_netem.c +++ b/net/sched/sch_netem.c @@ -748,12 +748,10 @@ static void dist_free(struct disttable *d) * signed 16 bit values. */ -static int get_dist_table(struct Qdisc *sch, struct disttable **tbl, - const struct nlattr *attr) +static int get_dist_table(struct disttable **tbl, const struct nlattr *attr) { size_t n = nla_len(attr)/sizeof(__s16); const __s16 *data = nla_data(attr); - spinlock_t *root_lock; struct disttable *d; int i; @@ -768,13 +766,7 @@ static int get_dist_table(struct Qdisc *sch, struct disttable **tbl, for (i = 0; i < n; i++) d->table[i] = data[i]; - root_lock = qdisc_root_sleeping_lock(sch); - - spin_lock_bh(root_lock); - swap(*tbl, d); - spin_unlock_bh(root_lock); - - dist_free(d); + *tbl = d; return 0; } @@ -930,6 +922,8 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, { struct netem_sched_data *q = qdisc_priv(sch); struct nlattr *tb[TCA_NETEM_MAX + 1]; + struct disttable *delay_dist = NULL; + struct disttable *slot_dist = NULL; struct tc_netem_qopt *qopt; struct clgstate old_clg; int old_loss_model = CLG_RANDOM; @@ -943,6 +937,19 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, if (ret < 0) return ret; + if (tb[TCA_NETEM_DELAY_DIST]) { + ret = get_dist_table(&delay_dist, tb[TCA_NETEM_DELAY_DIST]); + if (ret) + goto table_free; + } + + if (tb[TCA_NETEM_SLOT_DIST]) { + ret = get_dist_table(&slot_dist, tb[TCA_NETEM_SLOT_DIST]); + if (ret) + goto table_free; + } + + sch_tree_lock(sch); /* backup q->clg and q->loss_model */ old_clg = q->clg; old_loss_model = q->loss_model; @@ -951,26 +958,17 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, ret = get_loss_clg(q, tb[TCA_NETEM_LOSS]); if (ret) { q->loss_model = old_loss_model; - return ret; + q->clg = old_clg; + goto unlock; } } else { q->loss_model = CLG_RANDOM; } - if (tb[TCA_NETEM_DELAY_DIST]) { - ret = get_dist_table(sch, &q->delay_dist, - tb[TCA_NETEM_DELAY_DIST]); - if (ret) - goto get_table_failure; - } - - if (tb[TCA_NETEM_SLOT_DIST]) { - ret = get_dist_table(sch, &q->slot_dist, - tb[TCA_NETEM_SLOT_DIST]); - if (ret) - goto get_table_failure; - } - + if (delay_dist) + swap(q->delay_dist, delay_dist); + if (slot_dist) + swap(q->slot_dist, slot_dist); sch->limit = qopt->limit; q->latency = PSCHED_TICKS2NS(qopt->latency); @@ -1018,15 +1016,12 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, /* capping jitter to the range acceptable by tabledist() */ q->jitter = min_t(s64, abs(q->jitter), INT_MAX); - return ret; +unlock: + sch_tree_unlock(sch); -get_table_failure: - /* recover clg and loss_model, in case of - * q->clg and q->loss_model were modified - * in get_loss_clg() - */ - q->clg = old_clg; - q->loss_model = old_loss_model; +table_free: + dist_free(delay_dist); + dist_free(slot_dist); return ret; } diff --git a/net/sched/sch_plug.c b/net/sched/sch_plug.c index 5619d2eb17b690d5e73907ff958bb76f608130fa..4ddb4af61d103f1bbde518d3e0632e131a3e8ab0 100644 --- a/net/sched/sch_plug.c +++ b/net/sched/sch_plug.c @@ -214,7 +214,7 @@ static struct Qdisc_ops plug_qdisc_ops __read_mostly = { .priv_size = sizeof(struct plug_sched_data), .enqueue = plug_enqueue, .dequeue = plug_dequeue, - .peek = qdisc_peek_head, + .peek = qdisc_peek_dequeued, .init = plug_init, .change = plug_change, .reset = qdisc_reset_queue, diff --git a/net/sched/sch_qfq.c b/net/sched/sch_qfq.c index 20dc1851d4ffe185f1e3cbe7beb965f8c9c6b809..4f246599734eb6cf078ad9b7ce3232de42aeb9ee 100644 --- a/net/sched/sch_qfq.c +++ b/net/sched/sch_qfq.c @@ -387,8 +387,13 @@ static int qfq_change_agg(struct Qdisc *sch, struct qfq_class *cl, u32 weight, u32 lmax) { struct qfq_sched *q = qdisc_priv(sch); - struct qfq_aggregate *new_agg = qfq_find_agg(q, lmax, weight); + struct qfq_aggregate *new_agg; + /* 'lmax' can range from [QFQ_MIN_LMAX, pktlen + stab overhead] */ + if (lmax > (1UL << QFQ_MTU_SHIFT)) + return -EINVAL; + + new_agg = qfq_find_agg(q, lmax, weight); if (new_agg == NULL) { /* create new aggregate */ new_agg = kzalloc(sizeof(*new_agg), GFP_ATOMIC); if (new_agg == NULL) @@ -433,15 +438,16 @@ static int qfq_change_class(struct Qdisc *sch, u32 classid, u32 parentid, } else weight = 1; - if (tb[TCA_QFQ_LMAX]) { + if (tb[TCA_QFQ_LMAX]) lmax = nla_get_u32(tb[TCA_QFQ_LMAX]); - if (lmax < QFQ_MIN_LMAX || lmax > (1UL << QFQ_MTU_SHIFT)) { - pr_notice("qfq: invalid max length %u\n", lmax); - return -EINVAL; - } - } else + else lmax = psched_mtu(qdisc_dev(sch)); + if (lmax < QFQ_MIN_LMAX || lmax > (1UL << QFQ_MTU_SHIFT)) { + pr_notice("qfq: invalid max length %u\n", lmax); + return -EINVAL; + } + inv_w = ONE_FP / weight; weight = ONE_FP / inv_w; @@ -982,10 +988,13 @@ static void qfq_update_eligible(struct qfq_sched *q) } /* Dequeue head packet of the head class in the DRR queue of the aggregate. */ -static void agg_dequeue(struct qfq_aggregate *agg, - struct qfq_class *cl, unsigned int len) +static struct sk_buff *agg_dequeue(struct qfq_aggregate *agg, + struct qfq_class *cl, unsigned int len) { - qdisc_dequeue_peeked(cl->qdisc); + struct sk_buff *skb = qdisc_dequeue_peeked(cl->qdisc); + + if (!skb) + return NULL; cl->deficit -= (int) len; @@ -995,6 +1004,8 @@ static void agg_dequeue(struct qfq_aggregate *agg, cl->deficit += agg->lmax; list_move_tail(&cl->alist, &agg->active); } + + return skb; } static inline struct sk_buff *qfq_peek_skb(struct qfq_aggregate *agg, @@ -1140,11 +1151,18 @@ static struct sk_buff *qfq_dequeue(struct Qdisc *sch) if (!skb) return NULL; - qdisc_qstats_backlog_dec(sch, skb); sch->q.qlen--; + + skb = agg_dequeue(in_serv_agg, cl, len); + + if (!skb) { + sch->q.qlen++; + return NULL; + } + + qdisc_qstats_backlog_dec(sch, skb); qdisc_bstats_update(sch, skb); - agg_dequeue(in_serv_agg, cl, len); /* If lmax is lowered, through qfq_change_class, for a class * owning pending packets with larger size than the new value * of lmax, then the following condition may hold. diff --git a/net/sched/sch_sfq.c b/net/sched/sch_sfq.c index 1bfdf90fa0cce8d9d0bd28634fbf4bf24fc3817e..07721a1e98d8a7054b04f8f581317cc20fb848b0 100644 --- a/net/sched/sch_sfq.c +++ b/net/sched/sch_sfq.c @@ -353,7 +353,7 @@ sfq_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) unsigned int hash, dropped; sfq_index x, qlen; struct sfq_slot *slot; - int uninitialized_var(ret); + int ret; struct sk_buff *head; int delta; diff --git a/net/sctp/associola.c b/net/sctp/associola.c index d17708800652a38b442b162cff4435470013554b..78c1429d1301c63b009e2856e356d0b6d6e3c8e1 100644 --- a/net/sctp/associola.c +++ b/net/sctp/associola.c @@ -1181,8 +1181,7 @@ int sctp_assoc_update(struct sctp_association *asoc, /* Add any peer addresses from the new association. */ list_for_each_entry(trans, &new->peer.transport_addr_list, transports) - if (!sctp_assoc_lookup_paddr(asoc, &trans->ipaddr) && - !sctp_assoc_add_peer(asoc, &trans->ipaddr, + if (!sctp_assoc_add_peer(asoc, &trans->ipaddr, GFP_ATOMIC, trans->state)) return -ENOMEM; diff --git a/net/sctp/sm_sideeffect.c b/net/sctp/sm_sideeffect.c index 82d96441e64d6167038b85fe4a44b2cca1d558e5..c4a2d647e6cc7484d4a538124af790333c40d964 100644 --- a/net/sctp/sm_sideeffect.c +++ b/net/sctp/sm_sideeffect.c @@ -1255,7 +1255,10 @@ static int sctp_side_effects(enum sctp_event event_type, default: pr_err("impossible disposition %d in state %d, event_type %d, event_id %d\n", status, state, event_type, subtype.chunk); - BUG(); + error = status; + if (error >= 0) + error = -EINVAL; + WARN_ON_ONCE(1); break; } diff --git a/net/sctp/sm_statefuns.c b/net/sctp/sm_statefuns.c index 3d52431dea9bfba744aaab0d07eb6ee5dcd0131e..8298f27e8de0dbe49e862b982767613b78346cb1 100644 --- a/net/sctp/sm_statefuns.c +++ b/net/sctp/sm_statefuns.c @@ -4392,7 +4392,7 @@ enum sctp_disposition sctp_sf_eat_auth(struct net *net, SCTP_AUTH_NEW_KEY, GFP_ATOMIC); if (!ev) - return -ENOMEM; + return SCTP_DISPOSITION_NOMEM; sctp_add_cmd_sf(commands, SCTP_CMD_EVENT_ULP, SCTP_ULPEVENT(ev)); diff --git a/net/sctp/socket.c b/net/sctp/socket.c index 8901bb7afa2be66bffa69ba1c823dc6c518fe421..f954d3c8876db0b2bbce73df24f88e53875c6e61 100644 --- a/net/sctp/socket.c +++ b/net/sctp/socket.c @@ -112,7 +112,7 @@ struct percpu_counter sctp_sockets_allocated; static void sctp_enter_memory_pressure(struct sock *sk) { - sctp_memory_pressure = 1; + WRITE_ONCE(sctp_memory_pressure, 1); } @@ -380,9 +380,9 @@ static void sctp_auto_asconf_init(struct sctp_sock *sp) struct net *net = sock_net(&sp->inet.sk); if (net->sctp.default_auto_asconf) { - spin_lock(&net->sctp.addr_wq_lock); + spin_lock_bh(&net->sctp.addr_wq_lock); list_add_tail(&sp->auto_asconf_list, &net->sctp.auto_asconf_splist); - spin_unlock(&net->sctp.addr_wq_lock); + spin_unlock_bh(&net->sctp.addr_wq_lock); sp->do_auto_asconf = 1; } } @@ -1953,6 +1953,10 @@ static int sctp_sendmsg_to_asoc(struct sctp_association *asoc, err = sctp_wait_for_sndbuf(asoc, &timeo, msg_len); if (err) goto err; + if (unlikely(sinfo->sinfo_stream >= asoc->stream.outcnt)) { + err = -EINVAL; + goto err; + } } if (sctp_state(asoc, CLOSED)) { @@ -2574,6 +2578,7 @@ static int sctp_apply_peer_addr_params(struct sctp_paddrparams *params, if (trans) { trans->hbinterval = msecs_to_jiffies(params->spp_hbinterval); + sctp_transport_reset_hb_timer(trans); } else if (asoc) { asoc->hbinterval = msecs_to_jiffies(params->spp_hbinterval); @@ -4824,13 +4829,17 @@ static void sctp_destroy_sock(struct sock *sk) } /* Triggered when there are no references on the socket anymore */ -static void sctp_destruct_sock(struct sock *sk) +static void sctp_destruct_common(struct sock *sk) { struct sctp_sock *sp = sctp_sk(sk); /* Free up the HMAC transform. */ crypto_free_shash(sp->hmac); +} +static void sctp_destruct_sock(struct sock *sk) +{ + sctp_destruct_common(sk); inet_sock_destruct(sk); } @@ -8760,7 +8769,7 @@ void sctp_copy_sock(struct sock *newsk, struct sock *sk, sctp_sk(newsk)->reuse = sp->reuse; newsk->sk_shutdown = sk->sk_shutdown; - newsk->sk_destruct = sctp_destruct_sock; + newsk->sk_destruct = sk->sk_destruct; newsk->sk_family = sk->sk_family; newsk->sk_protocol = IPPROTO_SCTP; newsk->sk_backlog_rcv = sk->sk_prot->backlog_rcv; @@ -8980,11 +8989,20 @@ struct proto sctp_prot = { #if IS_ENABLED(CONFIG_IPV6) -#include -static void sctp_v6_destroy_sock(struct sock *sk) +static void sctp_v6_destruct_sock(struct sock *sk) { - sctp_destroy_sock(sk); - inet6_destroy_sock(sk); + sctp_destruct_common(sk); + inet6_sock_destruct(sk); +} + +static int sctp_v6_init_sock(struct sock *sk) +{ + int ret = sctp_init_sock(sk); + + if (!ret) + sk->sk_destruct = sctp_v6_destruct_sock; + + return ret; } struct proto sctpv6_prot = { @@ -8994,8 +9012,8 @@ struct proto sctpv6_prot = { .disconnect = sctp_disconnect, .accept = sctp_accept, .ioctl = sctp_ioctl, - .init = sctp_init_sock, - .destroy = sctp_v6_destroy_sock, + .init = sctp_v6_init_sock, + .destroy = sctp_destroy_sock, .shutdown = sctp_shutdown, .setsockopt = sctp_setsockopt, .getsockopt = sctp_getsockopt, diff --git a/net/sctp/stream_interleave.c b/net/sctp/stream_interleave.c index 0a78cdf864633eb68af1520fe5e09484dd8ef76f..3290e6f5b6c6c02a35e7c65339997c546165a9bb 100644 --- a/net/sctp/stream_interleave.c +++ b/net/sctp/stream_interleave.c @@ -1151,7 +1151,8 @@ static void sctp_generate_iftsn(struct sctp_outq *q, __u32 ctsn) #define _sctp_walk_ifwdtsn(pos, chunk, end) \ for (pos = chunk->subh.ifwdtsn_hdr->skip; \ - (void *)pos < (void *)chunk->subh.ifwdtsn_hdr->skip + (end); pos++) + (void *)pos <= (void *)chunk->subh.ifwdtsn_hdr->skip + (end) - \ + sizeof(struct sctp_ifwdtsn_skip); pos++) #define sctp_walk_ifwdtsn(pos, ch) \ _sctp_walk_ifwdtsn((pos), (ch), ntohs((ch)->chunk_hdr->length) - \ diff --git a/net/smc/af_smc.c b/net/smc/af_smc.c index dcd00b514c3f946132f32eabd6f8e2960a5eb053..ad0ac657fe12cf393b8f177ca85c09e28be4cf9f 100644 --- a/net/smc/af_smc.c +++ b/net/smc/af_smc.c @@ -141,34 +141,34 @@ static int smc_release(struct socket *sock) if (!smc->use_fallback) { rc = smc_close_active(smc); - sock_set_flag(sk, SOCK_DEAD); + smc_sock_set_flag(sk, SOCK_DEAD); sk->sk_shutdown |= SHUTDOWN_MASK; - } - - sk->sk_prot->unhash(sk); - - if (smc->clcsock) { - if (smc->use_fallback && sk->sk_state == SMC_LISTEN) { + } else { + if (sk->sk_state != SMC_LISTEN && sk->sk_state != SMC_INIT) + sock_put(sk); /* passive closing */ + if (sk->sk_state == SMC_LISTEN) { /* wake up clcsock accept */ rc = kernel_sock_shutdown(smc->clcsock, SHUT_RDWR); } - mutex_lock(&smc->clcsock_release_lock); - sock_release(smc->clcsock); - smc->clcsock = NULL; - mutex_unlock(&smc->clcsock_release_lock); - } - if (smc->use_fallback) { - if (sk->sk_state != SMC_LISTEN && sk->sk_state != SMC_INIT) - sock_put(sk); /* passive closing */ sk->sk_state = SMC_CLOSED; sk->sk_state_change(sk); } + sk->sk_prot->unhash(sk); + + if (sk->sk_state == SMC_CLOSED) { + if (smc->clcsock) { + release_sock(sk); + smc_clcsock_release(smc); + lock_sock(sk); + } + if (!smc->use_fallback) + smc_conn_free(&smc->conn); + } + /* detach socket */ sock_orphan(sk); sock->sk = NULL; - if (!smc->use_fallback && sk->sk_state == SMC_CLOSED) - smc_conn_free(&smc->conn); release_sock(sk); sock_put(sk); /* final sock_put */ @@ -852,7 +852,7 @@ static int smc_clcsock_accept(struct smc_sock *lsmc, struct smc_sock **new_smc) if (new_clcsock) sock_release(new_clcsock); new_sk->sk_state = SMC_CLOSED; - sock_set_flag(new_sk, SOCK_DEAD); + smc_sock_set_flag(new_sk, SOCK_DEAD); sock_put(new_sk); /* final */ *new_smc = NULL; goto out; @@ -1013,13 +1013,13 @@ static void smc_listen_out(struct smc_sock *new_smc) struct smc_sock *lsmc = new_smc->listen_smc; struct sock *newsmcsk = &new_smc->sk; - lock_sock_nested(&lsmc->sk, SINGLE_DEPTH_NESTING); if (lsmc->sk.sk_state == SMC_LISTEN) { + lock_sock_nested(&lsmc->sk, SINGLE_DEPTH_NESTING); smc_accept_enqueue(&lsmc->sk, newsmcsk); + release_sock(&lsmc->sk); } else { /* no longer listening */ smc_close_non_accepted(newsmcsk); } - release_sock(&lsmc->sk); /* Wake up accept */ lsmc->sk.sk_data_ready(&lsmc->sk); @@ -1215,6 +1215,9 @@ static void smc_listen_work(struct work_struct *work) int rc = 0; u8 ibport; + if (new_smc->listen_smc->sk.sk_state != SMC_LISTEN) + return smc_listen_out_err(new_smc); + if (new_smc->use_fallback) { smc_listen_out_connected(new_smc); return; diff --git a/net/smc/smc.h b/net/smc/smc.h index adbdf195eb085f5507444340fb1f8ddcb69548d5..c3b0e1e3f505de65445a66e8a1d9697d17b80cae 100644 --- a/net/smc/smc.h +++ b/net/smc/smc.h @@ -268,4 +268,9 @@ static inline bool using_ipsec(struct smc_sock *smc) struct sock *smc_accept_dequeue(struct sock *parent, struct socket *new_sock); void smc_close_non_accepted(struct sock *sk); +static inline void smc_sock_set_flag(struct sock *sk, enum sock_flags flag) +{ + set_bit(flag, &sk->sk_flags); +} + #endif /* __SMC_H */ diff --git a/net/smc/smc_cdc.c b/net/smc/smc_cdc.c index 333e4353498f8d3b8fb91377568618d1fe359e9f..c657fd29ff5d05de7bb12f5525d378b2c16d7060 100644 --- a/net/smc/smc_cdc.c +++ b/net/smc/smc_cdc.c @@ -304,7 +304,7 @@ static void smc_cdc_msg_recv_action(struct smc_sock *smc, smc->sk.sk_shutdown |= RCV_SHUTDOWN; if (smc->clcsock && smc->clcsock->sk) smc->clcsock->sk->sk_shutdown |= RCV_SHUTDOWN; - sock_set_flag(&smc->sk, SOCK_DONE); + smc_sock_set_flag(&smc->sk, SOCK_DONE); sock_hold(&smc->sk); /* sock_put in close_work */ if (!schedule_work(&conn->close_work)) sock_put(&smc->sk); diff --git a/net/smc/smc_close.c b/net/smc/smc_close.c index 092696d738c00d88675c8b7e3241f5fa8b133ed0..4ea28ec7ad135903a7191f52e89c170bf2d7d8f2 100644 --- a/net/smc/smc_close.c +++ b/net/smc/smc_close.c @@ -21,6 +21,22 @@ #define SMC_CLOSE_WAIT_LISTEN_CLCSOCK_TIME (5 * HZ) +/* release the clcsock that is assigned to the smc_sock */ +void smc_clcsock_release(struct smc_sock *smc) +{ + struct socket *tcp; + + if (smc->listen_smc && current_work() != &smc->smc_listen_work) + cancel_work_sync(&smc->smc_listen_work); + mutex_lock(&smc->clcsock_release_lock); + if (smc->clcsock) { + tcp = smc->clcsock; + smc->clcsock = NULL; + sock_release(tcp); + } + mutex_unlock(&smc->clcsock_release_lock); +} + static void smc_close_cleanup_listen(struct sock *parent) { struct sock *sk; @@ -148,7 +164,7 @@ static void smc_close_active_abort(struct smc_sock *smc) break; } - sock_set_flag(sk, SOCK_DEAD); + smc_sock_set_flag(sk, SOCK_DEAD); sk->sk_state_change(sk); } @@ -331,6 +347,7 @@ static void smc_close_passive_work(struct work_struct *work) close_work); struct smc_sock *smc = container_of(conn, struct smc_sock, conn); struct smc_cdc_conn_state_flags *rxflags; + bool release_clcsock = false; struct sock *sk = &smc->sk; int old_state; @@ -415,10 +432,15 @@ static void smc_close_passive_work(struct work_struct *work) if (old_state != sk->sk_state) { sk->sk_state_change(sk); if ((sk->sk_state == SMC_CLOSED) && - (sock_flag(sk, SOCK_DEAD) || !sk->sk_socket)) + (sock_flag(sk, SOCK_DEAD) || !sk->sk_socket)) { smc_conn_free(conn); + if (smc->clcsock) + release_clcsock = true; + } } release_sock(sk); + if (release_clcsock) + smc_clcsock_release(smc); sock_put(sk); /* sock_hold done by schedulers of close_work */ } diff --git a/net/smc/smc_close.h b/net/smc/smc_close.h index 19eb6a211c23cd12fad8f5077a26209bb05c3d33..e0e3b5df25d2474b8aadd2e7639d07e0c8c631ef 100644 --- a/net/smc/smc_close.h +++ b/net/smc/smc_close.h @@ -23,5 +23,6 @@ void smc_close_wake_tx_prepared(struct smc_sock *smc); int smc_close_active(struct smc_sock *smc); int smc_close_shutdown_write(struct smc_sock *smc); void smc_close_init(struct smc_sock *smc); +void smc_clcsock_release(struct smc_sock *smc); #endif /* SMC_CLOSE_H */ diff --git a/net/socket.c b/net/socket.c index 263a657573a902d663a72b402f8dc22e2c100e96..dae9d6c9d4464a35a592114c7df7ed28ace2cc9d 100644 --- a/net/socket.c +++ b/net/socket.c @@ -90,6 +90,7 @@ #include #include #include +#include #include #include @@ -111,6 +112,13 @@ #include //#endif /* OPLUS_FEATURE_NWPOWER_NETCONTROLLER */ +/* proto_ops for ipv4 and ipv6 use the same {recv,send}msg function */ +#if IS_ENABLED(CONFIG_INET) +#define INDIRECT_CALL_INET4(f, f1, ...) INDIRECT_CALL_1(f, f1, __VA_ARGS__) +#else +#define INDIRECT_CALL_INET4(f, f1, ...) f(__VA_ARGS__) +#endif + #ifdef CONFIG_NET_RX_BUSY_POLL unsigned int sysctl_net_busy_read __read_mostly; unsigned int sysctl_net_busy_poll __read_mostly; @@ -673,29 +681,48 @@ void __sock_tx_timestamp(__u16 tsflags, __u8 *tx_flags) } EXPORT_SYMBOL(__sock_tx_timestamp); -/** - * sock_sendmsg - send a message through @sock - * @sock: socket - * @msg: message to send - * - * Sends @msg through @sock, passing through LSM. - * Returns the number of bytes sent, or an error code. - */ - +INDIRECT_CALLABLE_DECLARE(int inet_sendmsg(struct socket *, struct msghdr *, + size_t)); static inline int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg) { - int ret = sock->ops->sendmsg(sock, msg, msg_data_left(msg)); + int ret = INDIRECT_CALL_INET4(sock->ops->sendmsg, inet_sendmsg, sock, + msg, msg_data_left(msg)); BUG_ON(ret == -EIOCBQUEUED); return ret; } -int sock_sendmsg(struct socket *sock, struct msghdr *msg) +static int __sock_sendmsg(struct socket *sock, struct msghdr *msg) { int err = security_socket_sendmsg(sock, msg, msg_data_left(msg)); return err ?: sock_sendmsg_nosec(sock, msg); } + +/** + * sock_sendmsg - send a message through @sock + * @sock: socket + * @msg: message to send + * + * Sends @msg through @sock, passing through LSM. + * Returns the number of bytes sent, or an error code. + */ +int sock_sendmsg(struct socket *sock, struct msghdr *msg) +{ + struct sockaddr_storage *save_addr = (struct sockaddr_storage *)msg->msg_name; + struct sockaddr_storage address; + int ret; + + if (msg->msg_name) { + memcpy(&address, msg->msg_name, msg->msg_namelen); + msg->msg_name = &address; + } + + ret = __sock_sendmsg(sock, msg); + msg->msg_name = save_addr; + + return ret; +} EXPORT_SYMBOL(sock_sendmsg); /** @@ -879,6 +906,15 @@ void __sock_recv_ts_and_drops(struct msghdr *msg, struct sock *sk, } EXPORT_SYMBOL_GPL(__sock_recv_ts_and_drops); +INDIRECT_CALLABLE_DECLARE(int inet_recvmsg(struct socket *, struct msghdr *, + size_t , int )); +static inline int sock_recvmsg_nosec(struct socket *sock, struct msghdr *msg, + int flags) +{ + return INDIRECT_CALL_INET4(sock->ops->recvmsg, inet_recvmsg, sock, msg, + msg_data_left(msg), flags); +} + /** * sock_recvmsg - receive a message from @sock * @sock: socket @@ -888,13 +924,6 @@ EXPORT_SYMBOL_GPL(__sock_recv_ts_and_drops); * Receives @msg from @sock, passing through LSM. Returns the total number * of bytes received, or an error. */ - -static inline int sock_recvmsg_nosec(struct socket *sock, struct msghdr *msg, - int flags) -{ - return sock->ops->recvmsg(sock, msg, msg_data_left(msg), flags); -} - int sock_recvmsg(struct socket *sock, struct msghdr *msg, int flags) { int err = security_socket_recvmsg(sock, msg, msg_data_left(msg), flags); @@ -999,7 +1028,7 @@ static ssize_t sock_write_iter(struct kiocb *iocb, struct iov_iter *from) if (sock->type == SOCK_SEQPACKET) msg.msg_flags |= MSG_EOR; - res = sock_sendmsg(sock, &msg); + res = __sock_sendmsg(sock, &msg); *from = msg.msg_iter; return res; } @@ -1954,7 +1983,7 @@ int __sys_sendto(int fd, void __user *buff, size_t len, unsigned int flags, if (sock->file->f_flags & O_NONBLOCK) flags |= MSG_DONTWAIT; msg.msg_flags = flags; - err = sock_sendmsg(sock, &msg); + err = __sock_sendmsg(sock, &msg); out_put: fput_light(sock->file, fput_needed); @@ -2288,7 +2317,7 @@ static int ___sys_sendmsg(struct socket *sock, struct user_msghdr __user *msg, err = sock_sendmsg_nosec(sock, msg_sys); goto out_freectl; } - err = sock_sendmsg(sock, msg_sys); + err = __sock_sendmsg(sock, msg_sys); /* * If this is sendmmsg() and sending to current destination address was * successful, remember it. @@ -2645,7 +2674,7 @@ int __sys_recvmmsg(int fd, struct mmsghdr __user *mmsg, unsigned int vlen, * error to return on the next call or if the * app asks about it using getsockopt(SO_ERROR). */ - sock->sk->sk_err = -err; + WRITE_ONCE(sock->sk->sk_err, -err); } out_put: fput_light(sock->file, fput_needed); @@ -3488,7 +3517,11 @@ static long compat_sock_ioctl(struct file *file, unsigned int cmd, int kernel_bind(struct socket *sock, struct sockaddr *addr, int addrlen) { - return sock->ops->bind(sock, addr, addrlen); + struct sockaddr_storage address; + + memcpy(&address, addr, addrlen); + + return sock->ops->bind(sock, (struct sockaddr *)&address, addrlen); } EXPORT_SYMBOL(kernel_bind); @@ -3558,7 +3591,11 @@ EXPORT_SYMBOL(kernel_accept); int kernel_connect(struct socket *sock, struct sockaddr *addr, int addrlen, int flags) { - return sock->ops->connect(sock, addr, addrlen, flags); + struct sockaddr_storage address; + + memcpy(&address, addr, addrlen); + + return sock->ops->connect(sock, (struct sockaddr *)&address, addrlen, flags); } EXPORT_SYMBOL(kernel_connect); diff --git a/net/sunrpc/clnt.c b/net/sunrpc/clnt.c index 1946bd13d5df70ba96ce1e32f3cafaf3739f963b..e5498253ad93bad784df7f56e75713d062327fae 100644 --- a/net/sunrpc/clnt.c +++ b/net/sunrpc/clnt.c @@ -1814,9 +1814,6 @@ call_bind_status(struct rpc_task *task) status = -EOPNOTSUPP; break; } - if (task->tk_rebind_retry == 0) - break; - task->tk_rebind_retry--; rpc_delay(task, 3*HZ); goto retry_timeout; case -ETIMEDOUT: diff --git a/net/sunrpc/sched.c b/net/sunrpc/sched.c index e36ae4d4b540c54c3c447b21ee9d3277faa94f50..9af919364a0010754e801b397ad325ef7d766358 100644 --- a/net/sunrpc/sched.c +++ b/net/sunrpc/sched.c @@ -709,7 +709,6 @@ rpc_init_task_statistics(struct rpc_task *task) /* Initialize retry counters */ task->tk_garb_retry = 2; task->tk_cred_retry = 2; - task->tk_rebind_retry = 2; /* starting timestamp */ task->tk_start = ktime_get(); diff --git a/net/sunrpc/svcsock.c b/net/sunrpc/svcsock.c index d0b5a1c47a32445801b2931156c9057c49ae4cdf..b5ee21d5d1f3ad902ca058f61601389ef757d225 100644 --- a/net/sunrpc/svcsock.c +++ b/net/sunrpc/svcsock.c @@ -757,12 +757,6 @@ static void svc_tcp_listen_data_ready(struct sock *sk) dprintk("svc: socket %p TCP (listen) state change %d\n", sk, sk->sk_state); - if (svsk) { - /* Refer to svc_setup_socket() for details. */ - rmb(); - svsk->sk_odata(sk); - } - /* * This callback may called twice when a new connection * is established as a child socket inherits everything @@ -771,15 +765,20 @@ static void svc_tcp_listen_data_ready(struct sock *sk) * when one of child sockets become ESTABLISHED. * 2) data_ready method of the child socket may be called * when it receives data before the socket is accepted. - * In case of 2, we should ignore it silently. + * In case of 2, we should ignore it silently and DO NOT + * dereference svsk. */ - if (sk->sk_state == TCP_LISTEN) { - if (svsk) { - set_bit(XPT_CONN, &svsk->sk_xprt.xpt_flags); - svc_xprt_enqueue(&svsk->sk_xprt); - } else - printk("svc: socket %p: no user data\n", sk); - } + if (sk->sk_state != TCP_LISTEN) + return; + + if (svsk) { + /* Refer to svc_setup_socket() for details. */ + rmb(); + svsk->sk_odata(sk); + set_bit(XPT_CONN, &svsk->sk_xprt.xpt_flags); + svc_xprt_enqueue(&svsk->sk_xprt); + } else + printk("svc: socket %p: no user data\n", sk); } /* diff --git a/net/tipc/bearer.c b/net/tipc/bearer.c index 0f970259d0d5a28ffbbb9012d10c0e757d8bb989..4353968bc5a5c20eead60ce2f0fcf962071f8019 100644 --- a/net/tipc/bearer.c +++ b/net/tipc/bearer.c @@ -1128,7 +1128,7 @@ int tipc_nl_media_get(struct sk_buff *skb, struct genl_info *info) struct tipc_nl_msg msg; struct tipc_media *media; struct sk_buff *rep; - struct nlattr *attrs[TIPC_NLA_BEARER_MAX + 1]; + struct nlattr *attrs[TIPC_NLA_MEDIA_MAX + 1]; if (!info->attrs[TIPC_NLA_MEDIA]) return -EINVAL; @@ -1177,7 +1177,7 @@ int __tipc_nl_media_set(struct sk_buff *skb, struct genl_info *info) int err; char *name; struct tipc_media *m; - struct nlattr *attrs[TIPC_NLA_BEARER_MAX + 1]; + struct nlattr *attrs[TIPC_NLA_MEDIA_MAX + 1]; if (!info->attrs[TIPC_NLA_MEDIA]) return -EINVAL; diff --git a/net/tipc/netlink.c b/net/tipc/netlink.c index 9b36163d951eba6a5ff1f92a4d65fcae5fb26221..bf11d57ef3aeab91051e6b683a8697a0aca7c1c0 100644 --- a/net/tipc/netlink.c +++ b/net/tipc/netlink.c @@ -87,7 +87,7 @@ const struct nla_policy tipc_nl_net_policy[TIPC_NLA_NET_MAX + 1] = { const struct nla_policy tipc_nl_link_policy[TIPC_NLA_LINK_MAX + 1] = { [TIPC_NLA_LINK_UNSPEC] = { .type = NLA_UNSPEC }, - [TIPC_NLA_LINK_NAME] = { .type = NLA_STRING, + [TIPC_NLA_LINK_NAME] = { .type = NLA_NUL_STRING, .len = TIPC_MAX_LINK_NAME }, [TIPC_NLA_LINK_MTU] = { .type = NLA_U32 }, [TIPC_NLA_LINK_BROADCAST] = { .type = NLA_FLAG }, @@ -116,7 +116,7 @@ const struct nla_policy tipc_nl_prop_policy[TIPC_NLA_PROP_MAX + 1] = { const struct nla_policy tipc_nl_bearer_policy[TIPC_NLA_BEARER_MAX + 1] = { [TIPC_NLA_BEARER_UNSPEC] = { .type = NLA_UNSPEC }, - [TIPC_NLA_BEARER_NAME] = { .type = NLA_STRING, + [TIPC_NLA_BEARER_NAME] = { .type = NLA_NUL_STRING, .len = TIPC_MAX_BEARER_NAME }, [TIPC_NLA_BEARER_PROP] = { .type = NLA_NESTED }, [TIPC_NLA_BEARER_DOMAIN] = { .type = NLA_U32 } diff --git a/net/tipc/netlink_compat.c b/net/tipc/netlink_compat.c index 59e8e17d8da9c6d6f8230f338cc4b8bf06e1f26d..2276a0704a6357115ad05f1adf9e0bbc4f675f41 100644 --- a/net/tipc/netlink_compat.c +++ b/net/tipc/netlink_compat.c @@ -101,6 +101,7 @@ static int tipc_add_tlv(struct sk_buff *skb, u16 type, void *data, u16 len) return -EMSGSIZE; skb_put(skb, TLV_SPACE(len)); + memset(tlv, 0, TLV_SPACE(len)); tlv->tlv_type = htons(type); tlv->tlv_len = htons(TLV_LENGTH(len)); if (len && data) diff --git a/net/tipc/socket.c b/net/tipc/socket.c index 8266452c143b473212e9c1c8996b4b41d231ab13..c83eaa71836966c616685b845e841e1478fe334f 100644 --- a/net/tipc/socket.c +++ b/net/tipc/socket.c @@ -388,7 +388,7 @@ static int tipc_sk_sock_err(struct socket *sock, long *timeout) rc_ = tipc_sk_sock_err((sock_), timeo_); \ if (rc_) \ break; \ - prepare_to_wait(sk_sleep(sk_), &wait_, TASK_INTERRUPTIBLE); \ + add_wait_queue(sk_sleep(sk_), &wait_); \ release_sock(sk_); \ *(timeo_) = wait_woken(&wait_, TASK_INTERRUPTIBLE, *(timeo_)); \ sched_annotate_sleep(); \ diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c index e79c329427964d689522dc20c0e109e362f19650..0632b494d329bc93432ec148b09590fb42149062 100644 --- a/net/unix/af_unix.c +++ b/net/unix/af_unix.c @@ -536,7 +536,7 @@ static void unix_release_sock(struct sock *sk, int embrion) /* Clear state */ unix_state_lock(sk); sock_orphan(sk); - sk->sk_shutdown = SHUTDOWN_MASK; + WRITE_ONCE(sk->sk_shutdown, SHUTDOWN_MASK); path = u->path; u->path.dentry = NULL; u->path.mnt = NULL; @@ -554,7 +554,7 @@ static void unix_release_sock(struct sock *sk, int embrion) if (sk->sk_type == SOCK_STREAM || sk->sk_type == SOCK_SEQPACKET) { unix_state_lock(skpair); /* No more writes */ - skpair->sk_shutdown = SHUTDOWN_MASK; + WRITE_ONCE(skpair->sk_shutdown, SHUTDOWN_MASK); if (!skb_queue_empty(&sk->sk_receive_queue) || embrion) skpair->sk_err = ECONNRESET; unix_state_unlock(skpair); @@ -594,7 +594,7 @@ static void unix_release_sock(struct sock *sk, int embrion) * What the above comment does talk about? --ANK(980817) */ - if (unix_tot_inflight) + if (READ_ONCE(unix_tot_inflight)) unix_gc(); /* Garbage collect fds */ } @@ -706,7 +706,7 @@ static int unix_set_peek_off(struct sock *sk, int val) if (mutex_lock_interruptible(&u->iolock)) return -EINTR; - sk->sk_peek_off = val; + WRITE_ONCE(sk->sk_peek_off, val); mutex_unlock(&u->iolock); return 0; @@ -1232,7 +1232,7 @@ static long unix_wait_for_peer(struct sock *other, long timeo) sched = !sock_flag(other, SOCK_DEAD) && !(other->sk_shutdown & RCV_SHUTDOWN) && - unix_recvq_full(other); + unix_recvq_full_lockless(other); unix_state_unlock(other); @@ -1984,6 +1984,7 @@ static ssize_t unix_stream_sendpage(struct socket *socket, struct page *page, if (false) { alloc_skb: + spin_unlock(&other->sk_receive_queue.lock); unix_state_unlock(other); mutex_unlock(&unix_sk(other)->iolock); newskb = sock_alloc_send_pskb(sk, 0, 0, flags & MSG_DONTWAIT, @@ -2023,6 +2024,7 @@ static ssize_t unix_stream_sendpage(struct socket *socket, struct page *page, init_scm = false; } + spin_lock(&other->sk_receive_queue.lock); skb = skb_peek_tail(&other->sk_receive_queue); if (tail && tail == skb) { skb = newskb; @@ -2053,14 +2055,11 @@ static ssize_t unix_stream_sendpage(struct socket *socket, struct page *page, refcount_add(size, &sk->sk_wmem_alloc); if (newskb) { - err = unix_scm_to_skb(&scm, skb, false); - if (err) - goto err_state_unlock; - spin_lock(&other->sk_receive_queue.lock); + unix_scm_to_skb(&scm, skb, false); __skb_queue_tail(&other->sk_receive_queue, newskb); - spin_unlock(&other->sk_receive_queue.lock); } + spin_unlock(&other->sk_receive_queue.lock); unix_state_unlock(other); mutex_unlock(&unix_sk(other)->iolock); @@ -2551,7 +2550,7 @@ static int unix_shutdown(struct socket *sock, int mode) ++mode; unix_state_lock(sk); - sk->sk_shutdown |= mode; + WRITE_ONCE(sk->sk_shutdown, sk->sk_shutdown | mode); other = unix_peer(sk); if (other) sock_hold(other); @@ -2568,7 +2567,7 @@ static int unix_shutdown(struct socket *sock, int mode) if (mode&SEND_SHUTDOWN) peer_mode |= RCV_SHUTDOWN; unix_state_lock(other); - other->sk_shutdown |= peer_mode; + WRITE_ONCE(other->sk_shutdown, other->sk_shutdown | peer_mode); unix_state_unlock(other); other->sk_state_change(other); if (peer_mode == SHUTDOWN_MASK) @@ -2687,16 +2686,18 @@ static __poll_t unix_poll(struct file *file, struct socket *sock, poll_table *wa { struct sock *sk = sock->sk; __poll_t mask; + u8 shutdown; sock_poll_wait(file, sock, wait); mask = 0; + shutdown = READ_ONCE(sk->sk_shutdown); /* exceptional events? */ if (sk->sk_err) mask |= EPOLLERR; - if (sk->sk_shutdown == SHUTDOWN_MASK) + if (shutdown == SHUTDOWN_MASK) mask |= EPOLLHUP; - if (sk->sk_shutdown & RCV_SHUTDOWN) + if (shutdown & RCV_SHUTDOWN) mask |= EPOLLRDHUP | EPOLLIN | EPOLLRDNORM; /* readable? */ @@ -2724,18 +2725,20 @@ static __poll_t unix_dgram_poll(struct file *file, struct socket *sock, struct sock *sk = sock->sk, *other; unsigned int writable; __poll_t mask; + u8 shutdown; sock_poll_wait(file, sock, wait); mask = 0; + shutdown = READ_ONCE(sk->sk_shutdown); /* exceptional events? */ if (sk->sk_err || !skb_queue_empty_lockless(&sk->sk_error_queue)) mask |= EPOLLERR | (sock_flag(sk, SOCK_SELECT_ERR_QUEUE) ? EPOLLPRI : 0); - if (sk->sk_shutdown & RCV_SHUTDOWN) + if (shutdown & RCV_SHUTDOWN) mask |= EPOLLRDHUP | EPOLLIN | EPOLLRDNORM; - if (sk->sk_shutdown == SHUTDOWN_MASK) + if (shutdown == SHUTDOWN_MASK) mask |= EPOLLHUP; /* readable? */ diff --git a/net/unix/scm.c b/net/unix/scm.c index a07b2efbf8b5e3981c8e8cced6b74b161bbb19fa..ac206bfdbbe3c0aa00d6c32da7c522a7619fac88 100644 --- a/net/unix/scm.c +++ b/net/unix/scm.c @@ -59,7 +59,7 @@ void unix_inflight(struct user_struct *user, struct file *fp) /* Paired with READ_ONCE() in wait_for_unix_gc() */ WRITE_ONCE(unix_tot_inflight, unix_tot_inflight + 1); } - user->unix_inflight++; + WRITE_ONCE(user->unix_inflight, user->unix_inflight + 1); spin_unlock(&unix_gc_lock); } @@ -80,7 +80,7 @@ void unix_notinflight(struct user_struct *user, struct file *fp) /* Paired with READ_ONCE() in wait_for_unix_gc() */ WRITE_ONCE(unix_tot_inflight, unix_tot_inflight - 1); } - user->unix_inflight--; + WRITE_ONCE(user->unix_inflight, user->unix_inflight - 1); spin_unlock(&unix_gc_lock); } @@ -94,7 +94,7 @@ static inline bool too_many_unix_fds(struct task_struct *p) { struct user_struct *user = current_user(); - if (unlikely(user->unix_inflight > task_rlimit(p, RLIMIT_NOFILE))) + if (unlikely(READ_ONCE(user->unix_inflight) > task_rlimit(p, RLIMIT_NOFILE))) return !capable(CAP_SYS_RESOURCE) && !capable(CAP_SYS_ADMIN); return false; } diff --git a/net/vmw_vsock/af_vsock.c b/net/vmw_vsock/af_vsock.c index d55a47858d6d3c70202aa7d12e70a89506e2c4cf..0dfa2dfcb4bcbc3582ecddc57d6101abeb313059 100644 --- a/net/vmw_vsock/af_vsock.c +++ b/net/vmw_vsock/af_vsock.c @@ -1240,7 +1240,7 @@ static int vsock_stream_connect(struct socket *sock, struct sockaddr *addr, vsock_transport_cancel_pkt(vsk); vsock_remove_connected(vsk); goto out_wait; - } else if (timeout == 0) { + } else if ((sk->sk_state != TCP_ESTABLISHED) && (timeout == 0)) { err = -ETIMEDOUT; sk->sk_state = TCP_CLOSE; sock->state = SS_UNCONNECTED; diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c index 8f01cc67bfbec3c0fde244e8ee3e9406aa19b2a1..f7b545416ff6850e8c208e352573d5e0b2819217 100644 --- a/net/wireless/nl80211.c +++ b/net/wireless/nl80211.c @@ -6655,7 +6655,7 @@ static int nl80211_update_mesh_config(struct sk_buff *skb, struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; struct wireless_dev *wdev = dev->ieee80211_ptr; - struct mesh_config cfg; + struct mesh_config cfg = {}; u32 mask; int err; diff --git a/net/wireless/sme.c b/net/wireless/sme.c index d5d9d7612cb56ca1724be5d02988b290b4f74d6f..7b80e6e35683efd7eb7624b46722e1100a004b57 100644 --- a/net/wireless/sme.c +++ b/net/wireless/sme.c @@ -269,6 +269,15 @@ void cfg80211_conn_work(struct work_struct *work) rtnl_unlock(); } +static void cfg80211_step_auth_next(struct cfg80211_conn *conn, + struct cfg80211_bss *bss) +{ + memcpy(conn->bssid, bss->bssid, ETH_ALEN); + conn->params.bssid = conn->bssid; + conn->params.channel = bss->channel; + conn->state = CFG80211_CONN_AUTHENTICATE_NEXT; +} + /* Returned bss is reference counted and must be cleaned up appropriately. */ static struct cfg80211_bss *cfg80211_get_conn_bss(struct wireless_dev *wdev) { @@ -286,10 +295,7 @@ static struct cfg80211_bss *cfg80211_get_conn_bss(struct wireless_dev *wdev) if (!bss) return NULL; - memcpy(wdev->conn->bssid, bss->bssid, ETH_ALEN); - wdev->conn->params.bssid = wdev->conn->bssid; - wdev->conn->params.channel = bss->channel; - wdev->conn->state = CFG80211_CONN_AUTHENTICATE_NEXT; + cfg80211_step_auth_next(wdev->conn, bss); schedule_work(&rdev->conn_work); return bss; @@ -568,7 +574,12 @@ static int cfg80211_sme_connect(struct wireless_dev *wdev, wdev->conn->params.ssid_len = wdev->ssid_len; /* see if we have the bss already */ - bss = cfg80211_get_conn_bss(wdev); + bss = cfg80211_get_bss(wdev->wiphy, wdev->conn->params.channel, + wdev->conn->params.bssid, + wdev->conn->params.ssid, + wdev->conn->params.ssid_len, + wdev->conn_bss_type, + IEEE80211_PRIVACY(wdev->conn->params.privacy)); if (prev_bssid) { memcpy(wdev->conn->prev_bssid, prev_bssid, ETH_ALEN); @@ -579,6 +590,7 @@ static int cfg80211_sme_connect(struct wireless_dev *wdev, if (bss) { enum nl80211_timeout_reason treason; + cfg80211_step_auth_next(wdev->conn, bss); err = cfg80211_conn_do_work(wdev, &treason); cfg80211_put_bss(wdev->wiphy, bss); } else { @@ -1214,6 +1226,13 @@ int cfg80211_connect(struct cfg80211_registered_device *rdev, } else { if (WARN_ON(connkeys)) return -EINVAL; + + /* connect can point to wdev->wext.connect which + * can hold key data from a previous connection + */ + connect->key = NULL; + connect->key_len = 0; + connect->key_idx = 0; } wdev->connect_keys = connkeys; diff --git a/net/wireless/wext-core.c b/net/wireless/wext-core.c index 76a80a41615befda05f5e62a8b5f2ba1a2253d04..a57f54bc0e1a778f4755b5e10bd53348f6ff1d9c 100644 --- a/net/wireless/wext-core.c +++ b/net/wireless/wext-core.c @@ -796,6 +796,12 @@ static int ioctl_standard_iw_point(struct iw_point *iwp, unsigned int cmd, } } + /* Sanity-check to ensure we never end up _allocating_ zero + * bytes of data for extra. + */ + if (extra_size <= 0) + return -EFAULT; + /* kzalloc() ensures NULL-termination for essid_compat. */ extra = kzalloc(extra_size, GFP_KERNEL); if (!extra) diff --git a/net/xfrm/Makefile b/net/xfrm/Makefile index f32511588d5612a7a5509b59282a53d9d4861d6f..199184d8815f5efa0af29521a5e3c2fbd8e1cf5a 100644 --- a/net/xfrm/Makefile +++ b/net/xfrm/Makefile @@ -3,6 +3,8 @@ # Makefile for the XFRM subsystem. # +xfrm_interface-$(CONFIG_XFRM_INTERFACE) += xfrm_interface_core.o + obj-$(CONFIG_XFRM) := xfrm_policy.o xfrm_state.o xfrm_hash.o \ xfrm_input.o xfrm_output.o \ xfrm_sysctl.o xfrm_replay.o xfrm_device.o diff --git a/net/xfrm/xfrm_interface.c b/net/xfrm/xfrm_interface_core.c similarity index 100% rename from net/xfrm/xfrm_interface.c rename to net/xfrm/xfrm_interface_core.c index 3c642328a117c53c48205f0d3d9c817a8ab48288..40081af62b68ff3844241e1dd4ad0786e902ff3a 100644 --- a/net/xfrm/xfrm_interface.c +++ b/net/xfrm/xfrm_interface_core.c @@ -354,8 +354,8 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev) switch (skb->protocol) { case htons(ETH_P_IPV6): - xfrm_decode_session(skb, &fl, AF_INET6); memset(IP6CB(skb), 0, sizeof(*IP6CB(skb))); + xfrm_decode_session(skb, &fl, AF_INET6); if (!dst) { fl.u.ip6.flowi6_oif = dev->ifindex; fl.u.ip6.flowi6_flags |= FLOWI_FLAG_ANYSRC; @@ -369,8 +369,8 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev) } break; case htons(ETH_P_IP): - xfrm_decode_session(skb, &fl, AF_INET); memset(IPCB(skb), 0, sizeof(*IPCB(skb))); + xfrm_decode_session(skb, &fl, AF_INET); if (!dst) { struct rtable *rt; diff --git a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c index 1cd21a8c4deac0423e8eb3afb570cda8c43732b4..6fe578773a51dfc965f1d1a0d7c2f2891846cdec 100644 --- a/net/xfrm/xfrm_policy.c +++ b/net/xfrm/xfrm_policy.c @@ -2240,7 +2240,7 @@ xfrm_secpath_reject(int idx, struct sk_buff *skb, const struct flowi *fl) static inline int xfrm_state_ok(const struct xfrm_tmpl *tmpl, const struct xfrm_state *x, - unsigned short family) + unsigned short family, u32 if_id) { if (xfrm_state_kern(x)) return tmpl->optional && !xfrm_state_addr_cmp(tmpl, x, tmpl->encap_family); @@ -2251,7 +2251,8 @@ xfrm_state_ok(const struct xfrm_tmpl *tmpl, const struct xfrm_state *x, (tmpl->allalgs || (tmpl->aalgos & (1<props.aalgo)) || !(xfrm_id_proto_match(tmpl->id.proto, IPSEC_PROTO_ANY))) && !(x->props.mode != XFRM_MODE_TRANSPORT && - xfrm_state_addr_cmp(tmpl, x, family)); + xfrm_state_addr_cmp(tmpl, x, family)) && + (if_id == 0 || if_id == x->if_id); } /* @@ -2263,7 +2264,7 @@ xfrm_state_ok(const struct xfrm_tmpl *tmpl, const struct xfrm_state *x, */ static inline int xfrm_policy_ok(const struct xfrm_tmpl *tmpl, const struct sec_path *sp, int start, - unsigned short family) + unsigned short family, u32 if_id) { int idx = start; @@ -2273,7 +2274,7 @@ xfrm_policy_ok(const struct xfrm_tmpl *tmpl, const struct sec_path *sp, int star } else start = -1; for (; idx < sp->len; idx++) { - if (xfrm_state_ok(tmpl, sp->xvec[idx], family)) + if (xfrm_state_ok(tmpl, sp->xvec[idx], family, if_id)) return ++idx; if (sp->xvec[idx]->props.mode != XFRM_MODE_TRANSPORT) { if (start == -1) @@ -2450,7 +2451,7 @@ int __xfrm_policy_check(struct sock *sk, int dir, struct sk_buff *skb, * are implied between each two transformations. */ for (i = xfrm_nr-1, k = 0; i >= 0; i--) { - k = xfrm_policy_ok(tpp[i], sp, k, family); + k = xfrm_policy_ok(tpp[i], sp, k, family, if_id); if (k < 0) { if (k < -1) /* "-2 - errored_index" returned */ diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c index 9eac35eff4a008b43f4f4a758dfbf73a124f1d64..1f6c9c688ffc298375321fdaa513ef8d09249f0a 100644 --- a/net/xfrm/xfrm_user.c +++ b/net/xfrm/xfrm_user.c @@ -521,7 +521,7 @@ static void xfrm_update_ae_params(struct xfrm_state *x, struct nlattr **attrs, struct nlattr *et = attrs[XFRMA_ETIMER_THRESH]; struct nlattr *rt = attrs[XFRMA_REPLAY_THRESH]; - if (re) { + if (re && x->replay_esn && x->preplay_esn) { struct xfrm_replay_state_esn *replay_esn; replay_esn = nla_data(re); memcpy(x->replay_esn, replay_esn, @@ -1048,6 +1048,15 @@ static int xfrm_dump_sa(struct sk_buff *skb, struct netlink_callback *cb) sizeof(*filter), GFP_KERNEL); if (filter == NULL) return -ENOMEM; + + /* see addr_match(), (prefix length >> 5) << 2 + * will be used to compare xfrm_address_t + */ + if (filter->splen > (sizeof(xfrm_address_t) << 3) || + filter->dplen > (sizeof(xfrm_address_t) << 3)) { + kfree(filter); + return -EINVAL; + } } if (attrs[XFRMA_PROTO]) @@ -2623,7 +2632,7 @@ const struct nla_policy xfrma_policy[XFRMA_MAX+1] = { [XFRMA_ALG_COMP] = { .len = sizeof(struct xfrm_algo) }, [XFRMA_ENCAP] = { .len = sizeof(struct xfrm_encap_tmpl) }, [XFRMA_TMPL] = { .len = sizeof(struct xfrm_user_tmpl) }, - [XFRMA_SEC_CTX] = { .len = sizeof(struct xfrm_sec_ctx) }, + [XFRMA_SEC_CTX] = { .len = sizeof(struct xfrm_user_sec_ctx) }, [XFRMA_LTIME_VAL] = { .len = sizeof(struct xfrm_lifetime_cur) }, [XFRMA_REPLAY_VAL] = { .len = sizeof(struct xfrm_replay_state) }, [XFRMA_REPLAY_THRESH] = { .type = NLA_U32 }, diff --git a/samples/bpf/tcp_basertt_kern.c b/samples/bpf/tcp_basertt_kern.c index 4bf4fc597db9a616da5f21669201357b293e542c..653d233714ad087bc315177556b4d1ad9a4524b1 100644 --- a/samples/bpf/tcp_basertt_kern.c +++ b/samples/bpf/tcp_basertt_kern.c @@ -54,7 +54,7 @@ int bpf_basertt(struct bpf_sock_ops *skops) case BPF_SOCK_OPS_BASE_RTT: n = bpf_getsockopt(skops, SOL_TCP, TCP_CONGESTION, cong, sizeof(cong)); - if (!n && !__builtin_memcmp(cong, nv, sizeof(nv)+1)) { + if (!n && !__builtin_memcmp(cong, nv, sizeof(nv))) { /* Set base_rtt to 80us */ rv = 80; } else if (n) { diff --git a/scripts/Makefile.build b/scripts/Makefile.build index 862a11c0ca101b246444a57af157e78dcbca5f71..6eeab4f1f3fcb0c80ce9ebc6b6648f1db834de71 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -639,7 +639,9 @@ targets += $(call intermediate_targets, .asn1.o, .asn1.c .asn1.h) \ PHONY += $(subdir-ym) $(subdir-ym): - $(Q)$(MAKE) $(build)=$@ need-builtin=$(if $(findstring $@,$(subdir-obj-y)),1) + $(Q)$(MAKE) $(build)=$@ \ + need-builtin=$(if $(filter $@/built-in.a, $(subdir-obj-y)),1) \ + need-modorder=$(if $(need-modorder),$(if $(filter $@/modules.order, $(modorder)),1)) # Add FORCE to the prequisites of a target to force it to be always rebuilt. # --------------------------------------------------------------------------- diff --git a/scripts/asn1_compiler.c b/scripts/asn1_compiler.c index c146020fc7838d1a3304c21152026f6563a7f5a0..f14d70768cf4ab0c7d7adc0b9fafa168fbf95d45 100644 --- a/scripts/asn1_compiler.c +++ b/scripts/asn1_compiler.c @@ -629,7 +629,7 @@ int main(int argc, char **argv) p = strrchr(argv[1], '/'); p = p ? p + 1 : argv[1]; grammar_name = strdup(p); - if (!p) { + if (!grammar_name) { perror(NULL); exit(1); } diff --git a/scripts/gcc-plugins/randomize_layout_plugin.c b/scripts/gcc-plugins/randomize_layout_plugin.c index bd29e4e7a5241b738b2d531c1f7803ca413feb1d..c7ff92b4189cb5ed93361a578c46fc73dcfed8d9 100644 --- a/scripts/gcc-plugins/randomize_layout_plugin.c +++ b/scripts/gcc-plugins/randomize_layout_plugin.c @@ -209,12 +209,14 @@ static void partition_struct(tree *fields, unsigned long length, struct partitio static void performance_shuffle(tree *newtree, unsigned long length, ranctx *prng_state) { - unsigned long i, x; + unsigned long i, x, index; struct partition_group size_group[length]; unsigned long num_groups = 0; unsigned long randnum; partition_struct(newtree, length, (struct partition_group *)&size_group, &num_groups); + + /* FIXME: this group shuffle is currently a no-op. */ for (i = num_groups - 1; i > 0; i--) { struct partition_group tmp; randnum = ranval(prng_state) % (i + 1); @@ -224,11 +226,14 @@ static void performance_shuffle(tree *newtree, unsigned long length, ranctx *prn } for (x = 0; x < num_groups; x++) { - for (i = size_group[x].start + size_group[x].length - 1; i > size_group[x].start; i--) { + for (index = size_group[x].length - 1; index > 0; index--) { tree tmp; + + i = size_group[x].start + index; if (DECL_BIT_FIELD_TYPE(newtree[i])) continue; - randnum = ranval(prng_state) % (i + 1); + randnum = ranval(prng_state) % (index + 1); + randnum += size_group[x].start; // we could handle this case differently if desired if (DECL_BIT_FIELD_TYPE(newtree[randnum])) continue; diff --git a/scripts/kconfig/preprocess.c b/scripts/kconfig/preprocess.c index 8c7e51a6273cc7429c7786e96cd0b9c95d1ee64c..0b0d6ed3eeb910d0b2551c34ad7fdfe3cfa02cc6 100644 --- a/scripts/kconfig/preprocess.c +++ b/scripts/kconfig/preprocess.c @@ -393,6 +393,9 @@ static char *eval_clause(const char *str, size_t len, int argc, char *argv[]) p++; } + + if (new_argc >= FUNCTION_MAX_ARGS) + pperror("too many function arguments"); new_argv[new_argc++] = prev; /* diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c index 7f40b6aab689b6deaa2272e318b36c0fed26900d..90868df7865e3b522842f76902dba6943eafcb43 100644 --- a/scripts/mod/file2alias.c +++ b/scripts/mod/file2alias.c @@ -1395,7 +1395,7 @@ void handle_moddevtable(struct module *mod, struct elf_info *info, /* First handle the "special" cases */ if (sym_is(name, namelen, "usb")) do_usb_table(symval, sym->st_size, mod); - if (sym_is(name, namelen, "of")) + else if (sym_is(name, namelen, "of")) do_of_table(symval, sym->st_size, mod); else if (sym_is(name, namelen, "pnp")) do_pnp_device_entry(symval, sym->st_size, mod); diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c index 70f45895391cd7ae94553bb0b37b276cc45fb562..7ec4480e9ca8bfde9d804a59fe532665c8a09c5e 100644 --- a/scripts/mod/modpost.c +++ b/scripts/mod/modpost.c @@ -1281,6 +1281,10 @@ static Elf_Sym *find_elf_symbol(struct elf_info *elf, Elf64_Sword addr, if (relsym->st_name != 0) return relsym; + /* + * Strive to find a better symbol name, but the resulting name may not + * match the symbol referenced in the original code. + */ relsym_secindex = get_secindex(elf, relsym); for (sym = elf->symtab_start; sym < elf->symtab_stop; sym++) { if (get_secindex(elf, sym) != relsym_secindex) @@ -1768,19 +1772,33 @@ static int addend_386_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) #define R_ARM_THM_JUMP19 51 #endif +static int32_t sign_extend32(int32_t value, int index) +{ + uint8_t shift = 31 - index; + + return (int32_t)(value << shift) >> shift; +} + static int addend_arm_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) { unsigned int r_typ = ELF_R_TYPE(r->r_info); + Elf_Sym *sym = elf->symtab_start + ELF_R_SYM(r->r_info); + void *loc = reloc_location(elf, sechdr, r); + uint32_t inst; + int32_t offset; switch (r_typ) { case R_ARM_ABS32: - /* From ARM ABI: (S + A) | T */ - r->r_addend = (int)(long) - (elf->symtab_start + ELF_R_SYM(r->r_info)); + inst = TO_NATIVE(*(uint32_t *)loc); + r->r_addend = inst + sym->st_value; break; case R_ARM_PC24: case R_ARM_CALL: case R_ARM_JUMP24: + inst = TO_NATIVE(*(uint32_t *)loc); + offset = sign_extend32((inst & 0x00ffffff) << 2, 25); + r->r_addend = offset + sym->st_value + 8; + break; case R_ARM_THM_CALL: case R_ARM_THM_JUMP24: case R_ARM_THM_JUMP19: diff --git a/scripts/recordmcount.c b/scripts/recordmcount.c index a073837a3fd4f03ef81bee7f003edf3e39cca0ec..d361cef240b5dd5e5ed83cf7adc35cacdb02ee39 100644 --- a/scripts/recordmcount.c +++ b/scripts/recordmcount.c @@ -132,6 +132,7 @@ uwrite(int const fd, void const *const buf, size_t const count) { size_t cnt = count; off_t idx = 0; + void *p = NULL; file_updated = 1; @@ -139,7 +140,10 @@ uwrite(int const fd, void const *const buf, size_t const count) off_t aoffset = (file_ptr + count) - file_end; if (aoffset > file_append_size) { - file_append = realloc(file_append, aoffset); + p = realloc(file_append, aoffset); + if (!p) + free(file_append); + file_append = p; file_append_size = aoffset; } if (!file_append) { diff --git a/scripts/tags.sh b/scripts/tags.sh index 26de7d5aa5c89a5fd4f051c67029341f4f8849fa..de02c44549f7315b891d712610d22ebddc882770 100755 --- a/scripts/tags.sh +++ b/scripts/tags.sh @@ -28,6 +28,13 @@ fi # ignore userspace tools ignore="$ignore ( -path ${tree}tools ) -prune -o" +# gtags(1) refuses to index any file outside of its current working dir. +# If gtags indexing is requested and the build output directory is not +# the kernel source tree, index all files in absolute-path form. +if [[ "$1" == "gtags" && -n "${tree}" ]]; then + tree=$(realpath "$tree")/ +fi + # Detect if ALLSOURCE_ARCHS is set. If not, we assume SRCARCH if [ "${ALLSOURCE_ARCHS}" = "" ]; then ALLSOURCE_ARCHS=${SRCARCH} @@ -136,7 +143,7 @@ docscope() dogtags() { - all_target_sources | gtags -i -f - + all_target_sources | gtags -i -C "${tree:-.}" -f - "$PWD" } # Basic regular expressions with an optional /kind-spec/ for ctags and diff --git a/security/integrity/evm/evm_main.c b/security/integrity/evm/evm_main.c index 6d1efe1359f17afcb5b2e1fd4a9b7fa76551b104..9c036a41e7347ab1e78a524c93b49c62bd8bbbb6 100644 --- a/security/integrity/evm/evm_main.c +++ b/security/integrity/evm/evm_main.c @@ -474,7 +474,9 @@ void evm_inode_post_removexattr(struct dentry *dentry, const char *xattr_name) /** * evm_inode_setattr - prevent updating an invalid EVM extended attribute + * @idmap: idmap of the mount * @dentry: pointer to the affected dentry + * @attr: iattr structure containing the new file attributes * * Permit update of file attributes when files have a valid EVM signature, * except in the case of them having an immutable portable signature. diff --git a/security/integrity/iint.c b/security/integrity/iint.c index 5a6810041e5c0aa957da3519c6bc227987f24a16..d5b9253ebd12bfb6b36dab421178a730b79fa1d0 100644 --- a/security/integrity/iint.c +++ b/security/integrity/iint.c @@ -46,12 +46,10 @@ static struct integrity_iint_cache *__integrity_iint_find(struct inode *inode) else if (inode > iint->inode) n = n->rb_right; else - break; + return iint; } - if (!n) - return NULL; - return iint; + return NULL; } /* @@ -116,10 +114,15 @@ struct integrity_iint_cache *integrity_inode_get(struct inode *inode) parent = *p; test_iint = rb_entry(parent, struct integrity_iint_cache, rb_node); - if (inode < test_iint->inode) + if (inode < test_iint->inode) { p = &(*p)->rb_left; - else + } else if (inode > test_iint->inode) { p = &(*p)->rb_right; + } else { + write_unlock(&integrity_iint_lock); + kmem_cache_free(iint_cache, iint); + return test_iint; + } } iint->inode = inode; diff --git a/security/integrity/ima/Kconfig b/security/integrity/ima/Kconfig index 3ec45028a8c54d7b95babdde0243f518116404f4..cd32fe3311afeae440f51408f1bd8ba4c61ac588 100644 --- a/security/integrity/ima/Kconfig +++ b/security/integrity/ima/Kconfig @@ -7,7 +7,7 @@ config IMA select CRYPTO_HMAC select CRYPTO_SHA1 select CRYPTO_HASH_INFO - select TCG_TPM if HAS_IOMEM && !UML + select TCG_TPM if HAS_IOMEM select TCG_TIS if TCG_TPM && X86 select TCG_CRB if TCG_TPM && ACPI select TCG_IBMVTPM if TCG_TPM && PPC_PSERIES diff --git a/security/integrity/ima/ima_main.c b/security/integrity/ima/ima_main.c index 2d31921fbda4a340f0a65cfd3d4532d8d77f9d82..c85aab3bd398b0ae17f0be17d2de6550e568c3fd 100644 --- a/security/integrity/ima/ima_main.c +++ b/security/integrity/ima/ima_main.c @@ -323,7 +323,9 @@ static int process_measurement(struct file *file, const struct cred *cred, /** * ima_file_mmap - based on policy, collect/store measurement. * @file: pointer to the file to be measured (May be NULL) - * @prot: contains the protection that will be applied by the kernel. + * @reqprot: protection requested by the application + * @prot: protection that will be applied by the kernel + * @flags: operational flags * * Measure files being mmapped executable based on the ima_must_measure() * policy decision. @@ -331,7 +333,8 @@ static int process_measurement(struct file *file, const struct cred *cred, * On success return 0. On integrity appraisal error, assuming the file * is in policy and IMA-appraisal is in enforcing mode, return -EACCES. */ -int ima_file_mmap(struct file *file, unsigned long prot) +int ima_file_mmap(struct file *file, unsigned long reqprot, + unsigned long prot, unsigned long flags) { u32 secid; diff --git a/security/keys/keyctl.c b/security/keys/keyctl.c index 9394d72a77e80a9115aa60e6ba374f7bb1bdf339..9e52a3e0fc6727d4d088bfab8cd8d4b82a1cbbbd 100644 --- a/security/keys/keyctl.c +++ b/security/keys/keyctl.c @@ -922,14 +922,19 @@ long keyctl_chown_key(key_serial_t id, uid_t user, gid_t group) ret = -EACCES; down_write(&key->sem); - if (!capable(CAP_SYS_ADMIN)) { + { + bool is_privileged_op = false; + /* only the sysadmin can chown a key to some other UID */ if (user != (uid_t) -1 && !uid_eq(key->uid, uid)) - goto error_put; + is_privileged_op = true; /* only the sysadmin can set the key's GID to a group other * than one of those that the current process subscribes to */ if (group != (gid_t) -1 && !gid_eq(gid, key->gid) && !in_group_p(gid)) + is_privileged_op = true; + + if (is_privileged_op && !capable(CAP_SYS_ADMIN)) goto error_put; } @@ -1029,7 +1034,7 @@ long keyctl_setperm_key(key_serial_t id, key_perm_t perm) down_write(&key->sem); /* if we're not the sysadmin, we can only change a key that we own */ - if (capable(CAP_SYS_ADMIN) || uid_eq(key->uid, current_fsuid())) { + if (uid_eq(key->uid, current_fsuid()) || capable(CAP_SYS_ADMIN)) { key->perm = perm; ret = 0; } diff --git a/security/security.c b/security/security.c index a71f280b6bb6d2ba043bbcb309fa87b939109f30..d7a4019d8be90396841eb70b4807f29dcf10070c 100644 --- a/security/security.c +++ b/security/security.c @@ -927,12 +927,13 @@ static inline unsigned long mmap_prot(struct file *file, unsigned long prot) int security_mmap_file(struct file *file, unsigned long prot, unsigned long flags) { + unsigned long prot_adj = mmap_prot(file, prot); int ret; - ret = call_int_hook(mmap_file, 0, file, prot, - mmap_prot(file, prot), flags); + + ret = call_int_hook(mmap_file, 0, file, prot, prot_adj, flags); if (ret) return ret; - return ima_file_mmap(file, prot); + return ima_file_mmap(file, prot, prot_adj, flags); } int security_mmap_addr(unsigned long addr) diff --git a/security/selinux/Makefile b/security/selinux/Makefile index ef0f184119b39134263aa7c61436f9a4abd9b565..15318bd0470371b86d8986e4b63e2f3dd9788398 100644 --- a/security/selinux/Makefile +++ b/security/selinux/Makefile @@ -21,8 +21,12 @@ ccflags-y := -I$(srctree)/security/selinux -I$(srctree)/security/selinux/include $(addprefix $(obj)/,$(selinux-y)): $(obj)/flask.h quiet_cmd_flask = GEN $(obj)/flask.h $(obj)/av_permissions.h - cmd_flask = scripts/selinux/genheaders/genheaders $(obj)/flask.h $(obj)/av_permissions.h + cmd_flask = $< $(obj)/flask.h $(obj)/av_permissions.h targets += flask.h av_permissions.h -$(obj)/flask.h: $(src)/include/classmap.h FORCE +# once make >= 4.3 is required, we can use grouped targets in the rule below, +# which basically involves adding both headers and a '&' before the colon, see +# the example below: +# $(obj)/flask.h $(obj)/av_permissions.h &: scripts/selinux/... +$(obj)/flask.h: scripts/selinux/genheaders/genheaders FORCE $(call if_changed,flask) diff --git a/security/smack/smack.h b/security/smack/smack.h index f7db791fb5660ad14479af3d4b48e104d8bc37ed..62aa4bc25426c4e2d96bae57c27a69d8d6878be8 100644 --- a/security/smack/smack.h +++ b/security/smack/smack.h @@ -120,6 +120,7 @@ struct inode_smack { struct task_smack { struct smack_known *smk_task; /* label for access control */ struct smack_known *smk_forked; /* label when forked */ + struct smack_known *smk_transmuted;/* label when transmuted */ struct list_head smk_rules; /* per task access rules */ struct mutex smk_rules_lock; /* lock for the rules */ struct list_head smk_relabel; /* transit allowed labels */ diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c index 4f65d953fe318165f824cc9a779f23621baad5de..266eb8ca3381863427670dbdab4ab593ab6a1c5b 100644 --- a/security/smack/smack_lsm.c +++ b/security/smack/smack_lsm.c @@ -1032,8 +1032,9 @@ static int smack_inode_init_security(struct inode *inode, struct inode *dir, const struct qstr *qstr, const char **name, void **value, size_t *len) { + struct task_smack *tsp = current_security(); struct inode_smack *issp = inode->i_security; - struct smack_known *skp = smk_of_current(); + struct smack_known *skp = smk_of_task(tsp); struct smack_known *isp = smk_of_inode(inode); struct smack_known *dsp = smk_of_inode(dir); int may; @@ -1042,20 +1043,34 @@ static int smack_inode_init_security(struct inode *inode, struct inode *dir, *name = XATTR_SMACK_SUFFIX; if (value && len) { - rcu_read_lock(); - may = smk_access_entry(skp->smk_known, dsp->smk_known, - &skp->smk_rules); - rcu_read_unlock(); + /* + * If equal, transmuting already occurred in + * smack_dentry_create_files_as(). No need to check again. + */ + if (tsp->smk_task != tsp->smk_transmuted) { + rcu_read_lock(); + may = smk_access_entry(skp->smk_known, dsp->smk_known, + &skp->smk_rules); + rcu_read_unlock(); + } /* - * If the access rule allows transmutation and - * the directory requests transmutation then - * by all means transmute. + * In addition to having smk_task equal to smk_transmuted, + * if the access rule allows transmutation and the directory + * requests transmutation then by all means transmute. * Mark the inode as changed. */ - if (may > 0 && ((may & MAY_TRANSMUTE) != 0) && - smk_inode_transmutable(dir)) { - isp = dsp; + if ((tsp->smk_task == tsp->smk_transmuted) || + (may > 0 && ((may & MAY_TRANSMUTE) != 0) && + smk_inode_transmutable(dir))) { + /* + * The caller of smack_dentry_create_files_as() + * should have overridden the current cred, so the + * inode label was already set correctly in + * smack_inode_alloc_security(). + */ + if (tsp->smk_task != tsp->smk_transmuted) + isp = dsp; issp->smk_flags |= SMK_INODE_CHANGED; } @@ -1490,10 +1505,19 @@ static int smack_inode_getsecurity(struct inode *inode, struct super_block *sbp; struct inode *ip = (struct inode *)inode; struct smack_known *isp; + struct inode_smack *ispp; + size_t label_len; + char *label = NULL; - if (strcmp(name, XATTR_SMACK_SUFFIX) == 0) + if (strcmp(name, XATTR_SMACK_SUFFIX) == 0) { isp = smk_of_inode(inode); - else { + } else if (strcmp(name, XATTR_SMACK_TRANSMUTE) == 0) { + ispp = inode->i_security; + if (ispp->smk_flags & SMK_INODE_TRANSMUTE) + label = TRANS_TRUE; + else + label = ""; + } else { /* * The rest of the Smack xattrs are only on sockets. */ @@ -1515,13 +1539,18 @@ static int smack_inode_getsecurity(struct inode *inode, return -EOPNOTSUPP; } + if (!label) + label = isp->smk_known; + + label_len = strlen(label); + if (alloc) { - *buffer = kstrdup(isp->smk_known, GFP_KERNEL); + *buffer = kstrdup(label, GFP_KERNEL); if (*buffer == NULL) return -ENOMEM; } - return strlen(isp->smk_known); + return label_len; } @@ -4612,7 +4641,7 @@ static int smack_inode_copy_up(struct dentry *dentry, struct cred **new) /* * Get label from overlay inode and set it in create_sid */ - isp = d_inode(dentry->d_parent)->i_security; + isp = d_inode(dentry)->i_security; skp = isp->smk_inode; tsp->smk_task = skp; *new = new_creds; @@ -4663,8 +4692,10 @@ static int smack_dentry_create_files_as(struct dentry *dentry, int mode, * providing access is transmuting use the containing * directory label instead of the process label. */ - if (may > 0 && (may & MAY_TRANSMUTE)) + if (may > 0 && (may & MAY_TRANSMUTE)) { ntsp->smk_task = isp->smk_inode; + ntsp->smk_transmuted = ntsp->smk_task; + } } return 0; } diff --git a/security/smack/smackfs.c b/security/smack/smackfs.c index a9c516362170ac26746c29ce9e226f5484ff688e..61e734baa332aa9c0c24d137345f2dbb9a2b540a 100644 --- a/security/smack/smackfs.c +++ b/security/smack/smackfs.c @@ -923,7 +923,7 @@ static ssize_t smk_set_cipso(struct file *file, const char __user *buf, } ret = sscanf(rule, "%d", &catlen); - if (ret != 1 || catlen > SMACK_CIPSO_MAXCATNUM) + if (ret != 1 || catlen < 0 || catlen > SMACK_CIPSO_MAXCATNUM) goto out; if (format == SMK_FIXED24_FMT && diff --git a/sound/Kconfig b/sound/Kconfig index 1140e9988fc5039c7e798c629578ead709a23d97..76febc37862de749bc0831925db7c8a876ec9bfd 100644 --- a/sound/Kconfig +++ b/sound/Kconfig @@ -1,6 +1,6 @@ menuconfig SOUND tristate "Sound card support" - depends on HAS_IOMEM + depends on HAS_IOMEM || UML help If you have a sound card in your computer, i.e. if it can say more than an occasional beep, say Y. diff --git a/sound/core/control_compat.c b/sound/core/control_compat.c index 00d826b048c4af142f52bdcf7831321dc699f292..eb6735f16b93331cc31af1a05ad270354973a816 100644 --- a/sound/core/control_compat.c +++ b/sound/core/control_compat.c @@ -236,7 +236,7 @@ static int copy_ctl_value_from_user(struct snd_card *card, { struct snd_ctl_elem_value32 __user *data32 = userdata; int i, type, size; - int uninitialized_var(count); + int count; unsigned int indirect; if (copy_from_user(&data->id, &data32->id, sizeof(data->id))) diff --git a/sound/core/info.c b/sound/core/info.c index e762180b14905ee9b03338dd652498f176aed3b7..06437b617b08b0a0aff454e4955fae6502f19923 100644 --- a/sound/core/info.c +++ b/sound/core/info.c @@ -72,7 +72,7 @@ struct snd_info_private_data { }; static int snd_info_version_init(void); -static void snd_info_disconnect(struct snd_info_entry *entry); +static void snd_info_clear_entries(struct snd_info_entry *entry); /* @@ -610,11 +610,16 @@ void snd_info_card_disconnect(struct snd_card *card) { if (!card) return; - mutex_lock(&info_mutex); + proc_remove(card->proc_root_link); - card->proc_root_link = NULL; if (card->proc_root) - snd_info_disconnect(card->proc_root); + proc_remove(card->proc_root->p); + + mutex_lock(&info_mutex); + if (card->proc_root) + snd_info_clear_entries(card->proc_root); + card->proc_root_link = NULL; + card->proc_root = NULL; mutex_unlock(&info_mutex); } @@ -787,15 +792,14 @@ struct snd_info_entry *snd_info_create_card_entry(struct snd_card *card, } EXPORT_SYMBOL(snd_info_create_card_entry); -static void snd_info_disconnect(struct snd_info_entry *entry) +static void snd_info_clear_entries(struct snd_info_entry *entry) { struct snd_info_entry *p; if (!entry->p) return; list_for_each_entry(p, &entry->children, list) - snd_info_disconnect(p); - proc_remove(entry->p); + snd_info_clear_entries(p); entry->p = NULL; } @@ -812,8 +816,9 @@ void snd_info_free_entry(struct snd_info_entry * entry) if (!entry) return; if (entry->p) { + proc_remove(entry->p); mutex_lock(&info_mutex); - snd_info_disconnect(entry); + snd_info_clear_entries(entry); mutex_unlock(&info_mutex); } diff --git a/sound/core/oss/pcm_plugin.h b/sound/core/oss/pcm_plugin.h index c9cd29d86efda71b4e1a5d8ddc03a4a9e943fbac..64a2057aa06106d118de4b8f0c0a0b2cc88686ad 100644 --- a/sound/core/oss/pcm_plugin.h +++ b/sound/core/oss/pcm_plugin.h @@ -156,6 +156,14 @@ int snd_pcm_area_copy(const struct snd_pcm_channel_area *src_channel, void *snd_pcm_plug_buf_alloc(struct snd_pcm_substream *plug, snd_pcm_uframes_t size); void snd_pcm_plug_buf_unlock(struct snd_pcm_substream *plug, void *ptr); +#else + +static inline snd_pcm_sframes_t snd_pcm_plug_client_size(struct snd_pcm_substream *handle, snd_pcm_uframes_t drv_size) { return drv_size; } +static inline snd_pcm_sframes_t snd_pcm_plug_slave_size(struct snd_pcm_substream *handle, snd_pcm_uframes_t clt_size) { return clt_size; } +static inline int snd_pcm_plug_slave_format(int format, const struct snd_mask *format_mask) { return format; } + +#endif + snd_pcm_sframes_t snd_pcm_oss_write3(struct snd_pcm_substream *substream, const char *ptr, snd_pcm_uframes_t size, int in_kernel); @@ -166,14 +174,6 @@ snd_pcm_sframes_t snd_pcm_oss_writev3(struct snd_pcm_substream *substream, snd_pcm_sframes_t snd_pcm_oss_readv3(struct snd_pcm_substream *substream, void **bufs, snd_pcm_uframes_t frames); -#else - -static inline snd_pcm_sframes_t snd_pcm_plug_client_size(struct snd_pcm_substream *handle, snd_pcm_uframes_t drv_size) { return drv_size; } -static inline snd_pcm_sframes_t snd_pcm_plug_slave_size(struct snd_pcm_substream *handle, snd_pcm_uframes_t clt_size) { return clt_size; } -static inline int snd_pcm_plug_slave_format(int format, const struct snd_mask *format_mask) { return format; } - -#endif - #ifdef PLUGIN_DEBUG #define pdprintf(fmt, args...) printk(KERN_DEBUG "plugin: " fmt, ##args) #else diff --git a/sound/core/pcm_compat.c b/sound/core/pcm_compat.c index b6cf173bee68c1a05be6a650f58fc649cb6c9b85..c1412a32bf7e402f7e0b3539d0c0a75b333995f8 100644 --- a/sound/core/pcm_compat.c +++ b/sound/core/pcm_compat.c @@ -329,10 +329,14 @@ static int snd_pcm_ioctl_hw_params_compat(struct snd_pcm_substream *substream, goto error; } - if (refine) + if (refine) { err = snd_pcm_hw_refine(substream, data); - else + if (err < 0) + goto error; + err = fixup_unreferenced_params(substream, data); + } else { err = snd_pcm_hw_params(substream, data); + } if (err < 0) goto error; if (copy_to_user(data32, data, sizeof(*data32)) || diff --git a/sound/core/seq/oss/seq_oss_midi.c b/sound/core/seq/oss/seq_oss_midi.c index 838c3c8b403cb37e15ffc51b9e2bb294aa21cdb8..2ddfd6fed122ea186022c693daaf89cc4d24bd1f 100644 --- a/sound/core/seq/oss/seq_oss_midi.c +++ b/sound/core/seq/oss/seq_oss_midi.c @@ -50,6 +50,7 @@ struct seq_oss_midi { struct snd_midi_event *coder; /* MIDI event coder */ struct seq_oss_devinfo *devinfo; /* assigned OSSseq device */ snd_use_lock_t use_lock; + struct mutex open_mutex; }; @@ -184,6 +185,7 @@ snd_seq_oss_midi_check_new_port(struct snd_seq_port_info *pinfo) mdev->flags = pinfo->capability; mdev->opened = 0; snd_use_lock_init(&mdev->use_lock); + mutex_init(&mdev->open_mutex); /* copy and truncate the name of synth device */ strlcpy(mdev->name, pinfo->name, sizeof(mdev->name)); @@ -332,14 +334,16 @@ snd_seq_oss_midi_open(struct seq_oss_devinfo *dp, int dev, int fmode) int perm; struct seq_oss_midi *mdev; struct snd_seq_port_subscribe subs; + int err; if ((mdev = get_mididev(dp, dev)) == NULL) return -ENODEV; + mutex_lock(&mdev->open_mutex); /* already used? */ if (mdev->opened && mdev->devinfo != dp) { - snd_use_lock_free(&mdev->use_lock); - return -EBUSY; + err = -EBUSY; + goto unlock; } perm = 0; @@ -349,14 +353,14 @@ snd_seq_oss_midi_open(struct seq_oss_devinfo *dp, int dev, int fmode) perm |= PERM_READ; perm &= mdev->flags; if (perm == 0) { - snd_use_lock_free(&mdev->use_lock); - return -ENXIO; + err = -ENXIO; + goto unlock; } /* already opened? */ if ((mdev->opened & perm) == perm) { - snd_use_lock_free(&mdev->use_lock); - return 0; + err = 0; + goto unlock; } perm &= ~mdev->opened; @@ -381,13 +385,17 @@ snd_seq_oss_midi_open(struct seq_oss_devinfo *dp, int dev, int fmode) } if (! mdev->opened) { - snd_use_lock_free(&mdev->use_lock); - return -ENXIO; + err = -ENXIO; + goto unlock; } mdev->devinfo = dp; + err = 0; + + unlock: + mutex_unlock(&mdev->open_mutex); snd_use_lock_free(&mdev->use_lock); - return 0; + return err; } /* @@ -401,10 +409,9 @@ snd_seq_oss_midi_close(struct seq_oss_devinfo *dp, int dev) if ((mdev = get_mididev(dp, dev)) == NULL) return -ENODEV; - if (! mdev->opened || mdev->devinfo != dp) { - snd_use_lock_free(&mdev->use_lock); - return 0; - } + mutex_lock(&mdev->open_mutex); + if (!mdev->opened || mdev->devinfo != dp) + goto unlock; memset(&subs, 0, sizeof(subs)); if (mdev->opened & PERM_WRITE) { @@ -423,6 +430,8 @@ snd_seq_oss_midi_close(struct seq_oss_devinfo *dp, int dev) mdev->opened = 0; mdev->devinfo = NULL; + unlock: + mutex_unlock(&mdev->open_mutex); snd_use_lock_free(&mdev->use_lock); return 0; } diff --git a/sound/hda/hdac_stream.c b/sound/hda/hdac_stream.c index eee422390d8e260fae1e784262598133254f023c..2569f82b6fa0212c18d53de03df98edc63356abd 100644 --- a/sound/hda/hdac_stream.c +++ b/sound/hda/hdac_stream.c @@ -241,8 +241,10 @@ struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, struct hdac_stream *res = NULL; /* make a non-zero unique key for the substream */ - int key = (substream->pcm->device << 16) | (substream->number << 2) | - (substream->stream + 1); + int key = (substream->number << 2) | (substream->stream + 1); + + if (substream->pcm) + key |= (substream->pcm->device << 16); list_for_each_entry(azx_dev, &bus->stream_list, list) { if (azx_dev->direction != substream->stream) diff --git a/sound/i2c/cs8427.c b/sound/i2c/cs8427.c index 8afa2f8884660fe186b682c984387e80dda8b759..ef40501cf8988e20ae161f4100236fd1e9650c1a 100644 --- a/sound/i2c/cs8427.c +++ b/sound/i2c/cs8427.c @@ -568,10 +568,13 @@ int snd_cs8427_iec958_active(struct snd_i2c_device *cs8427, int active) if (snd_BUG_ON(!cs8427)) return -ENXIO; chip = cs8427->private_data; - if (active) + if (active) { memcpy(chip->playback.pcm_status, chip->playback.def_status, 24); - chip->playback.pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; + chip->playback.pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; + } else { + chip->playback.pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; + } snd_ctl_notify(cs8427->bus->card, SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, &chip->playback.pcm_ctl->id); diff --git a/sound/isa/sb/sb16_csp.c b/sound/isa/sb/sb16_csp.c index c16c8151160c386431b7bc443bda9994ba98257e..970aef2cf513aa3446dbbeaf86ae967413abff5b 100644 --- a/sound/isa/sb/sb16_csp.c +++ b/sound/isa/sb/sb16_csp.c @@ -116,7 +116,7 @@ static void info_read(struct snd_info_entry *entry, struct snd_info_buffer *buff int snd_sb_csp_new(struct snd_sb *chip, int device, struct snd_hwdep ** rhwdep) { struct snd_sb_csp *p; - int uninitialized_var(version); + int version; int err; struct snd_hwdep *hw; diff --git a/sound/pci/ac97/ac97_codec.c b/sound/pci/ac97/ac97_codec.c index a276c4283c7bb4f6e364bb6078ead5d9487893eb..64a1bd42063791ca00e474c25f396150796504d0 100644 --- a/sound/pci/ac97/ac97_codec.c +++ b/sound/pci/ac97/ac97_codec.c @@ -2026,10 +2026,9 @@ int snd_ac97_mixer(struct snd_ac97_bus *bus, struct snd_ac97_template *template, .dev_disconnect = snd_ac97_dev_disconnect, }; - if (rac97) - *rac97 = NULL; - if (snd_BUG_ON(!bus || !template)) + if (snd_BUG_ON(!bus || !template || !rac97)) return -EINVAL; + *rac97 = NULL; if (snd_BUG_ON(template->num >= 4)) return -EINVAL; if (bus->codec[template->num]) diff --git a/sound/pci/asihpi/hpi6205.c b/sound/pci/asihpi/hpi6205.c index 2864698436a5ff6eb53165e9f95ef3849d519d46..6a49f897c4d91dbd69f2997e1ff2ada8b77172a5 100644 --- a/sound/pci/asihpi/hpi6205.c +++ b/sound/pci/asihpi/hpi6205.c @@ -441,7 +441,7 @@ void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) pao = hpi_find_adapter(phm->adapter_index); } else { /* subsys messages don't address an adapter */ - _HPI_6205(NULL, phm, phr); + phr->error = HPI_ERROR_INVALID_OBJ_INDEX; return; } diff --git a/sound/pci/emu10k1/emufx.c b/sound/pci/emu10k1/emufx.c index 1f25e6d029d82db67c195acf228c33e9ab5208fb..84d98c098b744e4bdb3a8be00ec97846adfd8b27 100644 --- a/sound/pci/emu10k1/emufx.c +++ b/sound/pci/emu10k1/emufx.c @@ -1550,14 +1550,8 @@ A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input)) gpr += 2; /* Master volume (will be renamed later) */ - A_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS)); + for (z = 0; z < 8; z++) + A_OP(icode, &ptr, iMAC0, A_GPR(playback+z+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+z+SND_EMU10K1_PLAYBACK_CHANNELS)); snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0); gpr += 2; @@ -1641,102 +1635,14 @@ A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input)) dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n", gpr, tmp); */ - /* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */ - /* A_P16VIN(0) is delayed by one sample, - * so all other A_P16VIN channels will need to also be delayed - */ - /* Left ADC in. 1 of 2 */ snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) ); - /* Right ADC in 1 of 2 */ - gpr_map[gpr++] = 0x00000000; - /* Delaying by one sample: instead of copying the input - * value A_P16VIN to output A_FXBUS2 as in the first channel, - * we use an auxiliary register, delaying the value by one - * sample - */ - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000); - /* For 96kHz mode */ - /* Left ADC in. 2 of 2 */ - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000); - /* Right ADC in 2 of 2 */ - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000); - /* Pavel Hofman - we still have voices, A_FXBUS2s, and - * A_P16VINs available - - * let's add 8 more capture channels - total of 16 - */ - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x10)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x12)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x14)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x16)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x18)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x1a)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x1c)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x1e)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf), - A_C_00000000, A_C_00000000); + /* A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels + * will need to also be delayed; we use an auxiliary register for that. */ + for (z = 1; z < 0x10; z++) { + snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr), A_FXBUS2(z * 2) ); + A_OP(icode, &ptr, iACC3, A_GPR(gpr), A_P16VIN(z), A_C_00000000, A_C_00000000); + gpr_map[gpr++] = 0x00000000; + } } #if 0 diff --git a/sound/pci/emu10k1/emupcm.c b/sound/pci/emu10k1/emupcm.c index 623776b13f8dae3babe21c358b5b7872ddc90c5a..54f09fbd786fd623a02bee0fa5405a9bf433ddf3 100644 --- a/sound/pci/emu10k1/emupcm.c +++ b/sound/pci/emu10k1/emupcm.c @@ -1258,7 +1258,7 @@ static int snd_emu10k1_capture_mic_close(struct snd_pcm_substream *substream) { struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream); - emu->capture_interrupt = NULL; + emu->capture_mic_interrupt = NULL; emu->pcm_capture_mic_substream = NULL; return 0; } @@ -1366,7 +1366,7 @@ static int snd_emu10k1_capture_efx_close(struct snd_pcm_substream *substream) { struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream); - emu->capture_interrupt = NULL; + emu->capture_efx_interrupt = NULL; emu->pcm_capture_efx_substream = NULL; return 0; } diff --git a/sound/pci/hda/hda_generic.c b/sound/pci/hda/hda_generic.c index ff263ad19230aa07b30c9097599da7d496b150d3..f4b07dc6f1cc185d77697763ca2c70e90b27aa1e 100644 --- a/sound/pci/hda/hda_generic.c +++ b/sound/pci/hda/hda_generic.c @@ -1159,8 +1159,8 @@ static bool path_has_mixer(struct hda_codec *codec, int path_idx, int ctl_type) return path && path->ctls[ctl_type]; } -static const char * const channel_name[4] = { - "Front", "Surround", "CLFE", "Side" +static const char * const channel_name[] = { + "Front", "Surround", "CLFE", "Side", "Back", }; /* give some appropriate ctl name prefix for the given line out channel */ @@ -1186,7 +1186,7 @@ static const char *get_line_out_pfx(struct hda_codec *codec, int ch, /* multi-io channels */ if (ch >= cfg->line_outs) - return channel_name[ch]; + goto fixed_name; switch (cfg->line_out_type) { case AUTO_PIN_SPEAKER_OUT: @@ -1238,6 +1238,7 @@ static const char *get_line_out_pfx(struct hda_codec *codec, int ch, if (cfg->line_outs == 1 && !spec->multi_ios) return "Line Out"; + fixed_name: if (ch >= ARRAY_SIZE(channel_name)) { snd_BUG(); return "PCM"; diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 40d596248fab8204eb899a303a603784751dfa00..aaca36250dda642960e410647dcde0a0ab614aae 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -2364,6 +2364,7 @@ static struct snd_pci_quirk power_save_blacklist[] = { SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), + SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0), /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index 23f00ba993cb77c9f7516d2ed39111100996b8d4..ca3c9f161829477fdf371ccb53168f9a878dc993 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -1070,6 +1070,7 @@ static const struct snd_pci_quirk ca0132_quirks[] = { SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), + SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI), SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI), SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), {} @@ -1917,7 +1918,7 @@ static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id, static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) { int status = 0; - unsigned int size = sizeof(dma_chan); + unsigned int size = sizeof(*dma_chan); codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); status = dspio_scp(codec, MASTERCONTROL, 0x20, @@ -3620,8 +3621,10 @@ static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, for (i = 0; i < TUNING_CTLS_COUNT; i++) if (nid == ca0132_tuning_ctls[i].nid) - break; + goto found; + return -EINVAL; +found: snd_hda_power_up(codec); dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, ca0132_tuning_ctls[i].req, diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c index 69f88d3abf50fdc3809cf6da7124255be794d3bf..cfa958dc2dd5fa3a89cafdfb1fe659c9984b4cca 100644 --- a/sound/pci/hda/patch_conexant.c +++ b/sound/pci/hda/patch_conexant.c @@ -952,7 +952,10 @@ static const struct snd_pci_quirk cxt5066_fixups[] = { SND_PCI_QUIRK(0x17aa, 0x3905, "Lenovo G50-30", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x390b, "Lenovo G50-80", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x3975, "Lenovo U300s", CXT_FIXUP_STEREO_DMIC), - SND_PCI_QUIRK(0x17aa, 0x3977, "Lenovo IdeaPad U310", CXT_PINCFG_LENOVO_NOTEBOOK), + /* NOTE: we'd need to extend the quirk for 17aa:3977 as the same + * PCI SSID is used on multiple Lenovo models + */ + SND_PCI_QUIRK(0x17aa, 0x3977, "Lenovo IdeaPad U310", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x3978, "Lenovo G50-70", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x397b, "Lenovo S205", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK_VENDOR(0x17aa, "Thinkpad", CXT_FIXUP_THINKPAD_ACPI), @@ -974,6 +977,7 @@ static const struct hda_model_fixup cxt5066_fixup_models[] = { { .id = CXT_FIXUP_HP_DOCK, .name = "hp-dock" }, { .id = CXT_FIXUP_MUTE_LED_GPIO, .name = "mute-led-gpio" }, { .id = CXT_FIXUP_HP_MIC_NO_PRESENCE, .name = "hp-mic-fix" }, + { .id = CXT_PINCFG_LENOVO_NOTEBOOK, .name = "lenovo-20149" }, {} }; diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c index be9f1c4295cde831a286beabf220d900ea89ed7c..e3f0326d81c28562876181a8f0e82040903bde71 100644 --- a/sound/pci/hda/patch_hdmi.c +++ b/sound/pci/hda/patch_hdmi.c @@ -3937,6 +3937,11 @@ HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), +HDA_CODEC_ENTRY(0x10de00a3, "GPU a3 HDMI/DP", patch_nvhdmi), +HDA_CODEC_ENTRY(0x10de00a4, "GPU a4 HDMI/DP", patch_nvhdmi), +HDA_CODEC_ENTRY(0x10de00a5, "GPU a5 HDMI/DP", patch_nvhdmi), +HDA_CODEC_ENTRY(0x10de00a6, "GPU a6 HDMI/DP", patch_nvhdmi), +HDA_CODEC_ENTRY(0x10de00a7, "GPU a7 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 9cedb78bffe7637d80eece1136017ef7fc3174b0..184f6af9c21046d054cfe7b3c2962749905a8986 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -956,7 +956,7 @@ struct alc_codec_rename_pci_table { const char *name; }; -static struct alc_codec_rename_table rename_tbl[] = { +static const struct alc_codec_rename_table rename_tbl[] = { { 0x10ec0221, 0xf00f, 0x1003, "ALC231" }, { 0x10ec0269, 0xfff0, 0x3010, "ALC277" }, { 0x10ec0269, 0xf0f0, 0x2010, "ALC259" }, @@ -977,7 +977,7 @@ static struct alc_codec_rename_table rename_tbl[] = { { } /* terminator */ }; -static struct alc_codec_rename_pci_table rename_pci_tbl[] = { +static const struct alc_codec_rename_pci_table rename_pci_tbl[] = { { 0x10ec0280, 0x1028, 0, "ALC3220" }, { 0x10ec0282, 0x1028, 0, "ALC3221" }, { 0x10ec0283, 0x1028, 0, "ALC3223" }, @@ -2556,6 +2556,7 @@ static const struct snd_pci_quirk alc882_fixup_tbl[] = { SND_PCI_QUIRK(0x1462, 0xda57, "MSI Z270-Gaming", ALC1220_FIXUP_GB_DUAL_CODECS), SND_PCI_QUIRK_VENDOR(0x1462, "MSI", ALC882_FIXUP_GPIO3), SND_PCI_QUIRK(0x147b, 0x107a, "Abit AW9D-MAX", ALC882_FIXUP_ABIT_AW9D_MAX), + SND_PCI_QUIRK(0x1558, 0x3702, "Clevo X370SN[VW]", ALC1220_FIXUP_CLEVO_PB51ED_PINS), SND_PCI_QUIRK(0x1558, 0x50d3, "Clevo PC50[ER][CDF]", ALC1220_FIXUP_CLEVO_PB51ED_PINS), SND_PCI_QUIRK(0x1558, 0x65d1, "Clevo PB51[ER][CDF]", ALC1220_FIXUP_CLEVO_PB51ED_PINS), SND_PCI_QUIRK(0x1558, 0x65d2, "Clevo PB51R[CDF]", ALC1220_FIXUP_CLEVO_PB51ED_PINS), @@ -3115,7 +3116,7 @@ static void alc269_shutup(struct hda_codec *codec) alc_shutup_pins(codec); } -static struct coef_fw alc282_coefs[] = { +static const struct coef_fw alc282_coefs[] = { WRITE_COEF(0x03, 0x0002), /* Power Down Control */ UPDATE_COEF(0x05, 0xff3f, 0x0700), /* FIFO and filter clock */ WRITE_COEF(0x07, 0x0200), /* DMIC control */ @@ -3227,7 +3228,7 @@ static void alc282_shutup(struct hda_codec *codec) alc_write_coef_idx(codec, 0x78, coef78); } -static struct coef_fw alc283_coefs[] = { +static const struct coef_fw alc283_coefs[] = { WRITE_COEF(0x03, 0x0002), /* Power Down Control */ UPDATE_COEF(0x05, 0xff3f, 0x0700), /* FIFO and filter clock */ WRITE_COEF(0x07, 0x0200), /* DMIC control */ @@ -4234,7 +4235,7 @@ static void alc269_fixup_hp_line1_mic1_led(struct hda_codec *codec, } } -static struct coef_fw alc225_pre_hsmode[] = { +static const struct coef_fw alc225_pre_hsmode[] = { UPDATE_COEF(0x4a, 1<<8, 0), UPDATE_COEFEX(0x57, 0x05, 1<<14, 0), UPDATE_COEF(0x63, 3<<14, 3<<14), @@ -4247,7 +4248,7 @@ static struct coef_fw alc225_pre_hsmode[] = { static void alc_headset_mode_unplugged(struct hda_codec *codec) { - static struct coef_fw coef0255[] = { + static const struct coef_fw coef0255[] = { WRITE_COEF(0x1b, 0x0c0b), /* LDO and MISC control */ WRITE_COEF(0x45, 0xd089), /* UAJ function set to menual mode */ UPDATE_COEFEX(0x57, 0x05, 1<<14, 0), /* Direct Drive HP Amp control(Set to verb control)*/ @@ -4255,7 +4256,7 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec) WRITE_COEFEX(0x57, 0x03, 0x8aa6), /* Direct Drive HP Amp control */ {} }; - static struct coef_fw coef0256[] = { + static const struct coef_fw coef0256[] = { WRITE_COEF(0x1b, 0x0c4b), /* LDO and MISC control */ WRITE_COEF(0x45, 0xd089), /* UAJ function set to menual mode */ WRITE_COEF(0x06, 0x6104), /* Set MIC2 Vref gate with HP */ @@ -4263,7 +4264,7 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec) UPDATE_COEFEX(0x57, 0x05, 1<<14, 0), /* Direct Drive HP Amp control(Set to verb control)*/ {} }; - static struct coef_fw coef0233[] = { + static const struct coef_fw coef0233[] = { WRITE_COEF(0x1b, 0x0c0b), WRITE_COEF(0x45, 0xc429), UPDATE_COEF(0x35, 0x4000, 0), @@ -4273,7 +4274,7 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec) WRITE_COEF(0x32, 0x42a3), {} }; - static struct coef_fw coef0288[] = { + static const struct coef_fw coef0288[] = { UPDATE_COEF(0x4f, 0xfcc0, 0xc400), UPDATE_COEF(0x50, 0x2000, 0x2000), UPDATE_COEF(0x56, 0x0006, 0x0006), @@ -4281,18 +4282,18 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec) UPDATE_COEF(0x67, 0x2000, 0), {} }; - static struct coef_fw coef0298[] = { + static const struct coef_fw coef0298[] = { UPDATE_COEF(0x19, 0x1300, 0x0300), {} }; - static struct coef_fw coef0292[] = { + static const struct coef_fw coef0292[] = { WRITE_COEF(0x76, 0x000e), WRITE_COEF(0x6c, 0x2400), WRITE_COEF(0x18, 0x7308), WRITE_COEF(0x6b, 0xc429), {} }; - static struct coef_fw coef0293[] = { + static const struct coef_fw coef0293[] = { UPDATE_COEF(0x10, 7<<8, 6<<8), /* SET Line1 JD to 0 */ UPDATE_COEFEX(0x57, 0x05, 1<<15|1<<13, 0x0), /* SET charge pump by verb */ UPDATE_COEFEX(0x57, 0x03, 1<<10, 1<<10), /* SET EN_OSW to 1 */ @@ -4301,16 +4302,16 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec) UPDATE_COEF(0x4a, 0x000f, 0x000e), /* Combo Jack auto detect */ {} }; - static struct coef_fw coef0668[] = { + static const struct coef_fw coef0668[] = { WRITE_COEF(0x15, 0x0d40), WRITE_COEF(0xb7, 0x802b), {} }; - static struct coef_fw coef0225[] = { + static const struct coef_fw coef0225[] = { UPDATE_COEF(0x63, 3<<14, 0), {} }; - static struct coef_fw coef0274[] = { + static const struct coef_fw coef0274[] = { UPDATE_COEF(0x4a, 0x0100, 0), UPDATE_COEFEX(0x57, 0x05, 0x4000, 0), UPDATE_COEF(0x6b, 0xf000, 0x5000), @@ -4375,25 +4376,25 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec) static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin, hda_nid_t mic_pin) { - static struct coef_fw coef0255[] = { + static const struct coef_fw coef0255[] = { WRITE_COEFEX(0x57, 0x03, 0x8aa6), WRITE_COEF(0x06, 0x6100), /* Set MIC2 Vref gate to normal */ {} }; - static struct coef_fw coef0256[] = { + static const struct coef_fw coef0256[] = { UPDATE_COEFEX(0x57, 0x05, 1<<14, 1<<14), /* Direct Drive HP Amp control(Set to verb control)*/ WRITE_COEFEX(0x57, 0x03, 0x09a3), WRITE_COEF(0x06, 0x6100), /* Set MIC2 Vref gate to normal */ {} }; - static struct coef_fw coef0233[] = { + static const struct coef_fw coef0233[] = { UPDATE_COEF(0x35, 0, 1<<14), WRITE_COEF(0x06, 0x2100), WRITE_COEF(0x1a, 0x0021), WRITE_COEF(0x26, 0x008c), {} }; - static struct coef_fw coef0288[] = { + static const struct coef_fw coef0288[] = { UPDATE_COEF(0x4f, 0x00c0, 0), UPDATE_COEF(0x50, 0x2000, 0), UPDATE_COEF(0x56, 0x0006, 0), @@ -4402,30 +4403,30 @@ static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin, UPDATE_COEF(0x67, 0x2000, 0x2000), {} }; - static struct coef_fw coef0292[] = { + static const struct coef_fw coef0292[] = { WRITE_COEF(0x19, 0xa208), WRITE_COEF(0x2e, 0xacf0), {} }; - static struct coef_fw coef0293[] = { + static const struct coef_fw coef0293[] = { UPDATE_COEFEX(0x57, 0x05, 0, 1<<15|1<<13), /* SET charge pump by verb */ UPDATE_COEFEX(0x57, 0x03, 1<<10, 0), /* SET EN_OSW to 0 */ UPDATE_COEF(0x1a, 1<<3, 0), /* Combo JD gating without LINE1-VREFO */ {} }; - static struct coef_fw coef0688[] = { + static const struct coef_fw coef0688[] = { WRITE_COEF(0xb7, 0x802b), WRITE_COEF(0xb5, 0x1040), UPDATE_COEF(0xc3, 0, 1<<12), {} }; - static struct coef_fw coef0225[] = { + static const struct coef_fw coef0225[] = { UPDATE_COEFEX(0x57, 0x05, 1<<14, 1<<14), UPDATE_COEF(0x4a, 3<<4, 2<<4), UPDATE_COEF(0x63, 3<<14, 0), {} }; - static struct coef_fw coef0274[] = { + static const struct coef_fw coef0274[] = { UPDATE_COEFEX(0x57, 0x05, 0x4000, 0x4000), UPDATE_COEF(0x4a, 0x0010, 0), UPDATE_COEF(0x6b, 0xf000, 0), @@ -4511,7 +4512,7 @@ static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin, static void alc_headset_mode_default(struct hda_codec *codec) { - static struct coef_fw coef0225[] = { + static const struct coef_fw coef0225[] = { UPDATE_COEF(0x45, 0x3f<<10, 0x30<<10), UPDATE_COEF(0x45, 0x3f<<10, 0x31<<10), UPDATE_COEF(0x49, 3<<8, 0<<8), @@ -4520,14 +4521,14 @@ static void alc_headset_mode_default(struct hda_codec *codec) UPDATE_COEF(0x67, 0xf000, 0x3000), {} }; - static struct coef_fw coef0255[] = { + static const struct coef_fw coef0255[] = { WRITE_COEF(0x45, 0xc089), WRITE_COEF(0x45, 0xc489), WRITE_COEFEX(0x57, 0x03, 0x8ea6), WRITE_COEF(0x49, 0x0049), {} }; - static struct coef_fw coef0256[] = { + static const struct coef_fw coef0256[] = { WRITE_COEF(0x45, 0xc489), WRITE_COEFEX(0x57, 0x03, 0x0da3), WRITE_COEF(0x49, 0x0049), @@ -4535,12 +4536,12 @@ static void alc_headset_mode_default(struct hda_codec *codec) WRITE_COEF(0x06, 0x6100), {} }; - static struct coef_fw coef0233[] = { + static const struct coef_fw coef0233[] = { WRITE_COEF(0x06, 0x2100), WRITE_COEF(0x32, 0x4ea3), {} }; - static struct coef_fw coef0288[] = { + static const struct coef_fw coef0288[] = { UPDATE_COEF(0x4f, 0xfcc0, 0xc400), /* Set to TRS type */ UPDATE_COEF(0x50, 0x2000, 0x2000), UPDATE_COEF(0x56, 0x0006, 0x0006), @@ -4548,26 +4549,26 @@ static void alc_headset_mode_default(struct hda_codec *codec) UPDATE_COEF(0x67, 0x2000, 0), {} }; - static struct coef_fw coef0292[] = { + static const struct coef_fw coef0292[] = { WRITE_COEF(0x76, 0x000e), WRITE_COEF(0x6c, 0x2400), WRITE_COEF(0x6b, 0xc429), WRITE_COEF(0x18, 0x7308), {} }; - static struct coef_fw coef0293[] = { + static const struct coef_fw coef0293[] = { UPDATE_COEF(0x4a, 0x000f, 0x000e), /* Combo Jack auto detect */ WRITE_COEF(0x45, 0xC429), /* Set to TRS type */ UPDATE_COEF(0x1a, 1<<3, 0), /* Combo JD gating without LINE1-VREFO */ {} }; - static struct coef_fw coef0688[] = { + static const struct coef_fw coef0688[] = { WRITE_COEF(0x11, 0x0041), WRITE_COEF(0x15, 0x0d40), WRITE_COEF(0xb7, 0x802b), {} }; - static struct coef_fw coef0274[] = { + static const struct coef_fw coef0274[] = { WRITE_COEF(0x45, 0x4289), UPDATE_COEF(0x4a, 0x0010, 0x0010), UPDATE_COEF(0x6b, 0x0f00, 0), @@ -4630,53 +4631,53 @@ static void alc_headset_mode_ctia(struct hda_codec *codec) { int val; - static struct coef_fw coef0255[] = { + static const struct coef_fw coef0255[] = { WRITE_COEF(0x45, 0xd489), /* Set to CTIA type */ WRITE_COEF(0x1b, 0x0c2b), WRITE_COEFEX(0x57, 0x03, 0x8ea6), {} }; - static struct coef_fw coef0256[] = { + static const struct coef_fw coef0256[] = { WRITE_COEF(0x45, 0xd489), /* Set to CTIA type */ WRITE_COEF(0x1b, 0x0e6b), {} }; - static struct coef_fw coef0233[] = { + static const struct coef_fw coef0233[] = { WRITE_COEF(0x45, 0xd429), WRITE_COEF(0x1b, 0x0c2b), WRITE_COEF(0x32, 0x4ea3), {} }; - static struct coef_fw coef0288[] = { + static const struct coef_fw coef0288[] = { UPDATE_COEF(0x50, 0x2000, 0x2000), UPDATE_COEF(0x56, 0x0006, 0x0006), UPDATE_COEF(0x66, 0x0008, 0), UPDATE_COEF(0x67, 0x2000, 0), {} }; - static struct coef_fw coef0292[] = { + static const struct coef_fw coef0292[] = { WRITE_COEF(0x6b, 0xd429), WRITE_COEF(0x76, 0x0008), WRITE_COEF(0x18, 0x7388), {} }; - static struct coef_fw coef0293[] = { + static const struct coef_fw coef0293[] = { WRITE_COEF(0x45, 0xd429), /* Set to ctia type */ UPDATE_COEF(0x10, 7<<8, 7<<8), /* SET Line1 JD to 1 */ {} }; - static struct coef_fw coef0688[] = { + static const struct coef_fw coef0688[] = { WRITE_COEF(0x11, 0x0001), WRITE_COEF(0x15, 0x0d60), WRITE_COEF(0xc3, 0x0000), {} }; - static struct coef_fw coef0225_1[] = { + static const struct coef_fw coef0225_1[] = { UPDATE_COEF(0x45, 0x3f<<10, 0x35<<10), UPDATE_COEF(0x63, 3<<14, 2<<14), {} }; - static struct coef_fw coef0225_2[] = { + static const struct coef_fw coef0225_2[] = { UPDATE_COEF(0x45, 0x3f<<10, 0x35<<10), UPDATE_COEF(0x63, 3<<14, 1<<14), {} @@ -4748,48 +4749,48 @@ static void alc_headset_mode_ctia(struct hda_codec *codec) /* Nokia type */ static void alc_headset_mode_omtp(struct hda_codec *codec) { - static struct coef_fw coef0255[] = { + static const struct coef_fw coef0255[] = { WRITE_COEF(0x45, 0xe489), /* Set to OMTP Type */ WRITE_COEF(0x1b, 0x0c2b), WRITE_COEFEX(0x57, 0x03, 0x8ea6), {} }; - static struct coef_fw coef0256[] = { + static const struct coef_fw coef0256[] = { WRITE_COEF(0x45, 0xe489), /* Set to OMTP Type */ WRITE_COEF(0x1b, 0x0e6b), {} }; - static struct coef_fw coef0233[] = { + static const struct coef_fw coef0233[] = { WRITE_COEF(0x45, 0xe429), WRITE_COEF(0x1b, 0x0c2b), WRITE_COEF(0x32, 0x4ea3), {} }; - static struct coef_fw coef0288[] = { + static const struct coef_fw coef0288[] = { UPDATE_COEF(0x50, 0x2000, 0x2000), UPDATE_COEF(0x56, 0x0006, 0x0006), UPDATE_COEF(0x66, 0x0008, 0), UPDATE_COEF(0x67, 0x2000, 0), {} }; - static struct coef_fw coef0292[] = { + static const struct coef_fw coef0292[] = { WRITE_COEF(0x6b, 0xe429), WRITE_COEF(0x76, 0x0008), WRITE_COEF(0x18, 0x7388), {} }; - static struct coef_fw coef0293[] = { + static const struct coef_fw coef0293[] = { WRITE_COEF(0x45, 0xe429), /* Set to omtp type */ UPDATE_COEF(0x10, 7<<8, 7<<8), /* SET Line1 JD to 1 */ {} }; - static struct coef_fw coef0688[] = { + static const struct coef_fw coef0688[] = { WRITE_COEF(0x11, 0x0001), WRITE_COEF(0x15, 0x0d50), WRITE_COEF(0xc3, 0x0000), {} }; - static struct coef_fw coef0225[] = { + static const struct coef_fw coef0225[] = { UPDATE_COEF(0x45, 0x3f<<10, 0x39<<10), UPDATE_COEF(0x63, 3<<14, 2<<14), {} @@ -4849,17 +4850,17 @@ static void alc_determine_headset_type(struct hda_codec *codec) int val; bool is_ctia = false; struct alc_spec *spec = codec->spec; - static struct coef_fw coef0255[] = { + static const struct coef_fw coef0255[] = { WRITE_COEF(0x45, 0xd089), /* combo jack auto switch control(Check type)*/ WRITE_COEF(0x49, 0x0149), /* combo jack auto switch control(Vref conteol) */ {} }; - static struct coef_fw coef0288[] = { + static const struct coef_fw coef0288[] = { UPDATE_COEF(0x4f, 0xfcc0, 0xd400), /* Check Type */ {} }; - static struct coef_fw coef0298[] = { + static const struct coef_fw coef0298[] = { UPDATE_COEF(0x50, 0x2000, 0x2000), UPDATE_COEF(0x56, 0x0006, 0x0006), UPDATE_COEF(0x66, 0x0008, 0), @@ -4867,19 +4868,19 @@ static void alc_determine_headset_type(struct hda_codec *codec) UPDATE_COEF(0x19, 0x1300, 0x1300), {} }; - static struct coef_fw coef0293[] = { + static const struct coef_fw coef0293[] = { UPDATE_COEF(0x4a, 0x000f, 0x0008), /* Combo Jack auto detect */ WRITE_COEF(0x45, 0xD429), /* Set to ctia type */ {} }; - static struct coef_fw coef0688[] = { + static const struct coef_fw coef0688[] = { WRITE_COEF(0x11, 0x0001), WRITE_COEF(0xb7, 0x802b), WRITE_COEF(0x15, 0x0d60), WRITE_COEF(0xc3, 0x0c00), {} }; - static struct coef_fw coef0274[] = { + static const struct coef_fw coef0274[] = { UPDATE_COEF(0x4a, 0x0010, 0), UPDATE_COEF(0x4a, 0x8000, 0), WRITE_COEF(0x45, 0xd289), @@ -5164,7 +5165,7 @@ static void alc_fixup_headset_mode_no_hp_mic(struct hda_codec *codec, static void alc255_set_default_jack_type(struct hda_codec *codec) { /* Set to iphone type */ - static struct coef_fw alc255fw[] = { + static const struct coef_fw alc255fw[] = { WRITE_COEF(0x1b, 0x880b), WRITE_COEF(0x45, 0xd089), WRITE_COEF(0x1b, 0x080b), @@ -5172,7 +5173,7 @@ static void alc255_set_default_jack_type(struct hda_codec *codec) WRITE_COEF(0x1b, 0x0c0b), {} }; - static struct coef_fw alc256fw[] = { + static const struct coef_fw alc256fw[] = { WRITE_COEF(0x1b, 0x884b), WRITE_COEF(0x45, 0xd089), WRITE_COEF(0x1b, 0x084b), @@ -7167,6 +7168,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x1043, 0x10a1, "ASUS UX391UA", ALC294_FIXUP_ASUS_SPK), SND_PCI_QUIRK(0x1043, 0x10c0, "ASUS X540SA", ALC256_FIXUP_ASUS_MIC), SND_PCI_QUIRK(0x1043, 0x10d0, "ASUS X540LA/X540LJ", ALC255_FIXUP_ASUS_MIC_NO_PRESENCE), + SND_PCI_QUIRK(0x1043, 0x10d3, "ASUS K6500ZC", ALC294_FIXUP_ASUS_SPK), SND_PCI_QUIRK(0x1043, 0x115d, "Asus 1015E", ALC269_FIXUP_LIMIT_INT_MIC_BOOST), SND_PCI_QUIRK(0x1043, 0x11c0, "ASUS X556UR", ALC255_FIXUP_ASUS_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1043, 0x1271, "ASUS X430UN", ALC256_FIXUP_ASUS_MIC_NO_PRESENCE), @@ -8510,7 +8512,92 @@ static void alc662_fixup_usi_headset_mic(struct hda_codec *codec, } } -static struct coef_fw alc668_coefs[] = { +static void alc662_aspire_ethos_mute_speakers(struct hda_codec *codec, + struct hda_jack_callback *cb) +{ + /* surround speakers at 0x1b already get muted automatically when + * headphones are plugged in, but we have to mute/unmute the remaining + * channels manually: + * 0x15 - front left/front right + * 0x18 - front center/ LFE + */ + if (snd_hda_jack_detect_state(codec, 0x1b) == HDA_JACK_PRESENT) { + snd_hda_set_pin_ctl_cache(codec, 0x15, 0); + snd_hda_set_pin_ctl_cache(codec, 0x18, 0); + } else { + snd_hda_set_pin_ctl_cache(codec, 0x15, PIN_OUT); + snd_hda_set_pin_ctl_cache(codec, 0x18, PIN_OUT); + } +} + +static void alc662_fixup_aspire_ethos_hp(struct hda_codec *codec, + const struct hda_fixup *fix, int action) +{ + /* Pin 0x1b: shared headphones jack and surround speakers */ + if (!is_jack_detectable(codec, 0x1b)) + return; + + switch (action) { + case HDA_FIXUP_ACT_PRE_PROBE: + snd_hda_jack_detect_enable_callback(codec, 0x1b, + alc662_aspire_ethos_mute_speakers); + /* subwoofer needs an extra GPIO setting to become audible */ + alc_setup_gpio(codec, 0x02); + break; + case HDA_FIXUP_ACT_INIT: + /* Make sure to start in a correct state, i.e. if + * headphones have been plugged in before powering up the system + */ + alc662_aspire_ethos_mute_speakers(codec, NULL); + break; + } +} + +static void alc671_fixup_hp_headset_mic2(struct hda_codec *codec, + const struct hda_fixup *fix, int action) +{ + struct alc_spec *spec = codec->spec; + + static const struct hda_pintbl pincfgs[] = { + { 0x19, 0x02a11040 }, /* use as headset mic, with its own jack detect */ + { 0x1b, 0x0181304f }, + { } + }; + + switch (action) { + case HDA_FIXUP_ACT_PRE_PROBE: + spec->gen.mixer_nid = 0; + spec->parse_flags |= HDA_PINCFG_HEADSET_MIC; + snd_hda_apply_pincfgs(codec, pincfgs); + break; + case HDA_FIXUP_ACT_INIT: + alc_write_coef_idx(codec, 0x19, 0xa054); + break; + } +} + +static void alc897_hp_automute_hook(struct hda_codec *codec, + struct hda_jack_callback *jack) +{ + struct alc_spec *spec = codec->spec; + int vref; + + snd_hda_gen_hp_automute(codec, jack); + vref = spec->gen.hp_jack_present ? (PIN_HP | AC_PINCTL_VREF_100) : PIN_HP; + snd_hda_codec_write(codec, 0x1b, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, + vref); +} + +static void alc897_fixup_lenovo_headset_mic(struct hda_codec *codec, + const struct hda_fixup *fix, int action) +{ + struct alc_spec *spec = codec->spec; + if (action == HDA_FIXUP_ACT_PRE_PROBE) { + spec->gen.hp_automute_hook = alc897_hp_automute_hook; + } +} + +static const struct coef_fw alc668_coefs[] = { WRITE_COEF(0x01, 0xbebe), WRITE_COEF(0x02, 0xaaaa), WRITE_COEF(0x03, 0x0), WRITE_COEF(0x04, 0x0180), WRITE_COEF(0x06, 0x0), WRITE_COEF(0x07, 0x0f80), WRITE_COEF(0x08, 0x0031), WRITE_COEF(0x0a, 0x0060), WRITE_COEF(0x0b, 0x0), @@ -8581,6 +8668,17 @@ enum { ALC662_FIXUP_USI_FUNC, ALC662_FIXUP_USI_HEADSET_MODE, ALC662_FIXUP_LENOVO_MULTI_CODECS, + ALC669_FIXUP_ACER_ASPIRE_ETHOS, + ALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET, + ALC671_FIXUP_HP_HEADSET_MIC2, + ALC662_FIXUP_ACER_X2660G_HEADSET_MODE, + ALC662_FIXUP_ACER_NITRO_HEADSET_MODE, + ALC668_FIXUP_ASUS_NO_HEADSET_MIC, + ALC668_FIXUP_HEADSET_MIC, + ALC668_FIXUP_MIC_DET_COEF, + ALC897_FIXUP_LENOVO_HEADSET_MIC, + ALC897_FIXUP_HEADSET_MIC_PIN, + ALC897_FIXUP_HP_HSMIC_VERB, }; static const struct hda_fixup alc662_fixups[] = { @@ -8907,6 +9005,87 @@ static const struct hda_fixup alc662_fixups[] = { .type = HDA_FIXUP_FUNC, .v.func = alc233_alc662_fixup_lenovo_dual_codecs, }, + [ALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET] = { + .type = HDA_FIXUP_FUNC, + .v.func = alc662_fixup_aspire_ethos_hp, + }, + [ALC669_FIXUP_ACER_ASPIRE_ETHOS] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x15, 0x92130110 }, /* front speakers */ + { 0x18, 0x99130111 }, /* center/subwoofer */ + { 0x1b, 0x11130012 }, /* surround plus jack for HP */ + { } + }, + .chained = true, + .chain_id = ALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET + }, + [ALC671_FIXUP_HP_HEADSET_MIC2] = { + .type = HDA_FIXUP_FUNC, + .v.func = alc671_fixup_hp_headset_mic2, + }, + [ALC662_FIXUP_ACER_X2660G_HEADSET_MODE] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x1a, 0x02a1113c }, /* use as headset mic, without its own jack detect */ + { } + }, + .chained = true, + .chain_id = ALC662_FIXUP_USI_FUNC + }, + [ALC662_FIXUP_ACER_NITRO_HEADSET_MODE] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x1a, 0x01a11140 }, /* use as headset mic, without its own jack detect */ + { 0x1b, 0x0221144f }, + { } + }, + .chained = true, + .chain_id = ALC662_FIXUP_USI_FUNC + }, + [ALC668_FIXUP_ASUS_NO_HEADSET_MIC] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x1b, 0x04a1112c }, + { } + }, + .chained = true, + .chain_id = ALC668_FIXUP_HEADSET_MIC + }, + [ALC668_FIXUP_HEADSET_MIC] = { + .type = HDA_FIXUP_FUNC, + .v.func = alc269_fixup_headset_mic, + .chained = true, + .chain_id = ALC668_FIXUP_MIC_DET_COEF + }, + [ALC668_FIXUP_MIC_DET_COEF] = { + .type = HDA_FIXUP_VERBS, + .v.verbs = (const struct hda_verb[]) { + { 0x20, AC_VERB_SET_COEF_INDEX, 0x15 }, + { 0x20, AC_VERB_SET_PROC_COEF, 0x0d60 }, + {} + }, + }, + [ALC897_FIXUP_LENOVO_HEADSET_MIC] = { + .type = HDA_FIXUP_FUNC, + .v.func = alc897_fixup_lenovo_headset_mic, + }, + [ALC897_FIXUP_HEADSET_MIC_PIN] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x1a, 0x03a11050 }, + { } + }, + .chained = true, + .chain_id = ALC897_FIXUP_LENOVO_HEADSET_MIC + }, + [ALC897_FIXUP_HP_HSMIC_VERB] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x19, 0x01a1913c }, /* use as headset mic, without its own jack detect */ + { } + }, + }, }; static const struct snd_pci_quirk alc662_fixup_tbl[] = { @@ -8918,6 +9097,8 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = { SND_PCI_QUIRK(0x1025, 0x0349, "eMachines eM250", ALC662_FIXUP_INV_DMIC), SND_PCI_QUIRK(0x1025, 0x034a, "Gateway LT27", ALC662_FIXUP_INV_DMIC), SND_PCI_QUIRK(0x1025, 0x038b, "Acer Aspire 8943G", ALC662_FIXUP_ASPIRE), + SND_PCI_QUIRK(0x1025, 0x123c, "Acer Nitro N50-600", ALC662_FIXUP_ACER_NITRO_HEADSET_MODE), + SND_PCI_QUIRK(0x1025, 0x124e, "Acer 2660G", ALC662_FIXUP_ACER_X2660G_HEADSET_MODE), SND_PCI_QUIRK(0x1028, 0x05d8, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1028, 0x05db, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1028, 0x05fe, "Dell XPS 15", ALC668_FIXUP_DELL_XPS13), @@ -8929,6 +9110,9 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = { SND_PCI_QUIRK(0x1028, 0x0698, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1028, 0x069f, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x103c, 0x1632, "HP RP5800", ALC662_FIXUP_HP_RP5800), + SND_PCI_QUIRK(0x103c, 0x8719, "HP", ALC897_FIXUP_HP_HSMIC_VERB), + SND_PCI_QUIRK(0x103c, 0x872b, "HP", ALC897_FIXUP_HP_HSMIC_VERB), + SND_PCI_QUIRK(0x103c, 0x873e, "HP", ALC671_FIXUP_HP_HEADSET_MIC2), SND_PCI_QUIRK(0x1043, 0x1080, "Asus UX501VW", ALC668_FIXUP_HEADSET_MODE), SND_PCI_QUIRK(0x1043, 0x11cd, "Asus N550", ALC662_FIXUP_ASUS_Nx50), SND_PCI_QUIRK(0x1043, 0x13df, "Asus N550JX", ALC662_FIXUP_BASS_1A), @@ -8938,6 +9122,7 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = { SND_PCI_QUIRK(0x1043, 0x15a7, "ASUS UX51VZH", ALC662_FIXUP_BASS_16), SND_PCI_QUIRK(0x1043, 0x177d, "ASUS N551", ALC668_FIXUP_ASUS_Nx51), SND_PCI_QUIRK(0x1043, 0x17bd, "ASUS N751", ALC668_FIXUP_ASUS_Nx51), + SND_PCI_QUIRK(0x1043, 0x185d, "ASUS G551JW", ALC668_FIXUP_ASUS_NO_HEADSET_MIC), SND_PCI_QUIRK(0x1043, 0x1963, "ASUS X71SL", ALC662_FIXUP_ASUS_MODE8), SND_PCI_QUIRK(0x1043, 0x1b73, "ASUS N55SF", ALC662_FIXUP_BASS_16), SND_PCI_QUIRK(0x1043, 0x1bf3, "ASUS N76VZ", ALC662_FIXUP_BASS_MODE4_CHMAP), @@ -8946,12 +9131,17 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = { SND_PCI_QUIRK(0x144d, 0xc051, "Samsung R720", ALC662_FIXUP_IDEAPAD), SND_PCI_QUIRK(0x14cd, 0x5003, "USI", ALC662_FIXUP_USI_HEADSET_MODE), SND_PCI_QUIRK(0x17aa, 0x1036, "Lenovo P520", ALC662_FIXUP_LENOVO_MULTI_CODECS), + SND_PCI_QUIRK(0x17aa, 0x32ca, "Lenovo ThinkCentre M80", ALC897_FIXUP_HEADSET_MIC_PIN), + SND_PCI_QUIRK(0x17aa, 0x32cb, "Lenovo ThinkCentre M70", ALC897_FIXUP_HEADSET_MIC_PIN), + SND_PCI_QUIRK(0x17aa, 0x32cf, "Lenovo ThinkCentre M950", ALC897_FIXUP_HEADSET_MIC_PIN), + SND_PCI_QUIRK(0x17aa, 0x32f7, "Lenovo ThinkCentre M90", ALC897_FIXUP_HEADSET_MIC_PIN), SND_PCI_QUIRK(0x17aa, 0x38af, "Lenovo Ideapad Y550P", ALC662_FIXUP_IDEAPAD), SND_PCI_QUIRK(0x17aa, 0x3a0d, "Lenovo Ideapad Y550", ALC662_FIXUP_IDEAPAD), SND_PCI_QUIRK(0x1849, 0x5892, "ASRock B150M", ALC892_FIXUP_ASROCK_MOBO), SND_PCI_QUIRK(0x19da, 0xa130, "Zotac Z68", ALC662_FIXUP_ZOTAC_Z68), SND_PCI_QUIRK(0x1b0a, 0x01b8, "ACER Veriton", ALC662_FIXUP_ACER_VERITON), SND_PCI_QUIRK(0x1b35, 0x2206, "CZC P10T", ALC662_FIXUP_CZC_P10T), + SND_PCI_QUIRK(0x1025, 0x0566, "Acer Aspire Ethos 8951G", ALC669_FIXUP_ACER_ASPIRE_ETHOS), #if 0 /* Below is a quirk table taken from the old code. @@ -9044,6 +9234,7 @@ static const struct hda_model_fixup alc662_fixup_models[] = { {.id = ALC892_FIXUP_ASROCK_MOBO, .name = "asrock-mobo"}, {.id = ALC662_FIXUP_USI_HEADSET_MODE, .name = "usi-headset"}, {.id = ALC662_FIXUP_LENOVO_MULTI_CODECS, .name = "dual-codecs"}, + {.id = ALC669_FIXUP_ACER_ASPIRE_ETHOS, .name = "aspire-ethos"}, {} }; @@ -9086,6 +9277,23 @@ static const struct snd_hda_pin_quirk alc662_pin_fixup_tbl[] = { {0x12, 0x90a60130}, {0x14, 0x90170110}, {0x15, 0x0321101f}), + SND_HDA_PIN_QUIRK(0x10ec0671, 0x103c, "HP cPC", ALC671_FIXUP_HP_HEADSET_MIC2, + {0x14, 0x01014010}, + {0x17, 0x90170150}, + {0x19, 0x02a11060}, + {0x1b, 0x01813030}, + {0x21, 0x02211020}), + SND_HDA_PIN_QUIRK(0x10ec0671, 0x103c, "HP cPC", ALC671_FIXUP_HP_HEADSET_MIC2, + {0x14, 0x01014010}, + {0x18, 0x01a19040}, + {0x1b, 0x01813030}, + {0x21, 0x02211020}), + SND_HDA_PIN_QUIRK(0x10ec0671, 0x103c, "HP cPC", ALC671_FIXUP_HP_HEADSET_MIC2, + {0x14, 0x01014020}, + {0x17, 0x90170110}, + {0x18, 0x01a19050}, + {0x1b, 0x01813040}, + {0x21, 0x02211030}), {} }; diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c index 8d09312b2e42899f279146bba5553158558e96da..e91df1152612d1e5672d63b08bc37f2856744e33 100644 --- a/sound/pci/hda/patch_sigmatel.c +++ b/sound/pci/hda/patch_sigmatel.c @@ -1723,6 +1723,7 @@ static const struct snd_pci_quirk stac925x_fixup_tbl[] = { }; static const struct hda_pintbl ref92hd73xx_pin_configs[] = { + // Port A-H { 0x0a, 0x02214030 }, { 0x0b, 0x02a19040 }, { 0x0c, 0x01a19020 }, @@ -1731,9 +1732,12 @@ static const struct hda_pintbl ref92hd73xx_pin_configs[] = { { 0x0f, 0x01014010 }, { 0x10, 0x01014020 }, { 0x11, 0x01014030 }, + // CD in { 0x12, 0x02319040 }, + // Digial Mic ins { 0x13, 0x90a000f0 }, { 0x14, 0x90a000f0 }, + // Digital outs { 0x22, 0x01452050 }, { 0x23, 0x01452050 }, {} @@ -1774,6 +1778,7 @@ static const struct hda_pintbl alienware_m17x_pin_configs[] = { }; static const struct hda_pintbl intel_dg45id_pin_configs[] = { + // Analog outputs { 0x0a, 0x02214230 }, { 0x0b, 0x02A19240 }, { 0x0c, 0x01013214 }, @@ -1781,6 +1786,9 @@ static const struct hda_pintbl intel_dg45id_pin_configs[] = { { 0x0e, 0x01A19250 }, { 0x0f, 0x01011212 }, { 0x10, 0x01016211 }, + // Digital output + { 0x22, 0x01451380 }, + { 0x23, 0x40f000f0 }, {} }; @@ -1971,6 +1979,8 @@ static const struct snd_pci_quirk stac92hd73xx_fixup_tbl[] = { "DFI LanParty", STAC_92HD73XX_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, "DFI LanParty", STAC_92HD73XX_REF), + SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5001, + "Intel DP45SG", STAC_92HD73XX_INTEL), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5002, "Intel DG45ID", STAC_92HD73XX_INTEL), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5003, diff --git a/sound/pci/ice1712/aureon.c b/sound/pci/ice1712/aureon.c index c9411dfff5a4deee94bad34e6da4b0b9d7ca1479..3473f1040d92d7f56c6a630b6ba3ba2a28338544 100644 --- a/sound/pci/ice1712/aureon.c +++ b/sound/pci/ice1712/aureon.c @@ -1906,6 +1906,7 @@ static int aureon_add_controls(struct snd_ice1712 *ice) unsigned char id; snd_ice1712_save_gpio_status(ice); id = aureon_cs8415_get(ice, CS8415_ID); + snd_ice1712_restore_gpio_status(ice); if (id != 0x41) dev_info(ice->card->dev, "No CS8415 chip. Skipping CS8415 controls.\n"); @@ -1923,7 +1924,6 @@ static int aureon_add_controls(struct snd_ice1712 *ice) kctl->id.device = ice->pcm->device; } } - snd_ice1712_restore_gpio_status(ice); } return 0; diff --git a/sound/soc/atmel/atmel-i2s.c b/sound/soc/atmel/atmel-i2s.c index 99cc731505769be597a138689ce1803ed7430e18..ab7f7611747425d1469a27a7b8d55f2902cca2e4 100644 --- a/sound/soc/atmel/atmel-i2s.c +++ b/sound/soc/atmel/atmel-i2s.c @@ -174,11 +174,14 @@ struct atmel_i2s_gck_param { #define I2S_MCK_12M288 12288000UL #define I2S_MCK_11M2896 11289600UL +#define I2S_MCK_6M144 6144000UL /* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */ static const struct atmel_i2s_gck_param gck_params[] = { + /* mck = 6.144Mhz */ + { 8000, I2S_MCK_6M144, 1, 47}, /* mck = 768 fs */ + /* mck = 12.288MHz */ - { 8000, I2S_MCK_12M288, 0, 47}, /* mck = 1536 fs */ { 16000, I2S_MCK_12M288, 1, 47}, /* mck = 768 fs */ { 24000, I2S_MCK_12M288, 3, 63}, /* mck = 512 fs */ { 32000, I2S_MCK_12M288, 3, 47}, /* mck = 384 fs */ diff --git a/sound/soc/codecs/cs42l51-i2c.c b/sound/soc/codecs/cs42l51-i2c.c index 4b5731a4187622ceeddf24d7b6f3969536ef45fe..cd93e93a598321d1052215e7cf2c2d5566447235 100644 --- a/sound/soc/codecs/cs42l51-i2c.c +++ b/sound/soc/codecs/cs42l51-i2c.c @@ -23,6 +23,12 @@ static struct i2c_device_id cs42l51_i2c_id[] = { }; MODULE_DEVICE_TABLE(i2c, cs42l51_i2c_id); +const struct of_device_id cs42l51_of_match[] = { + { .compatible = "cirrus,cs42l51", }, + { } +}; +MODULE_DEVICE_TABLE(of, cs42l51_of_match); + static int cs42l51_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c index 5080d7a3c27982a4e619f75bc2069c1e2bfbf6ac..662f1f85ba36f6292bae63f976703881ff35f6ab 100644 --- a/sound/soc/codecs/cs42l51.c +++ b/sound/soc/codecs/cs42l51.c @@ -563,13 +563,6 @@ int cs42l51_probe(struct device *dev, struct regmap *regmap) } EXPORT_SYMBOL_GPL(cs42l51_probe); -const struct of_device_id cs42l51_of_match[] = { - { .compatible = "cirrus,cs42l51", }, - { } -}; -MODULE_DEVICE_TABLE(of, cs42l51_of_match); -EXPORT_SYMBOL_GPL(cs42l51_of_match); - MODULE_AUTHOR("Arnaud Patard "); MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver"); MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/cs42l51.h b/sound/soc/codecs/cs42l51.h index 0ca805492ac4b77d110dc24b378845fb5b3768a6..8c55bf384bc65189545807d9ce9278d6c66670f2 100644 --- a/sound/soc/codecs/cs42l51.h +++ b/sound/soc/codecs/cs42l51.h @@ -22,7 +22,6 @@ struct device; extern const struct regmap_config cs42l51_regmap; int cs42l51_probe(struct device *dev, struct regmap *regmap); -extern const struct of_device_id cs42l51_of_match[]; #define CS42L51_CHIP_ID 0x1B #define CS42L51_CHIP_REV_A 0x00 diff --git a/sound/soc/codecs/da7219-aad.c b/sound/soc/codecs/da7219-aad.c index 2c7d5088e6f2759aba90e469be2b3b8eb8b07dcb..7e18e007a639fc683d1c5a2eb66e0b14875516af 100644 --- a/sound/soc/codecs/da7219-aad.c +++ b/sound/soc/codecs/da7219-aad.c @@ -351,11 +351,15 @@ static irqreturn_t da7219_aad_irq_thread(int irq, void *data) struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component); u8 events[DA7219_AAD_IRQ_REG_MAX]; u8 statusa; - int i, report = 0, mask = 0; + int i, ret, report = 0, mask = 0; /* Read current IRQ events */ - regmap_bulk_read(da7219->regmap, DA7219_ACCDET_IRQ_EVENT_A, - events, DA7219_AAD_IRQ_REG_MAX); + ret = regmap_bulk_read(da7219->regmap, DA7219_ACCDET_IRQ_EVENT_A, + events, DA7219_AAD_IRQ_REG_MAX); + if (ret) { + dev_warn_ratelimited(component->dev, "Failed to read IRQ events: %d\n", ret); + return IRQ_NONE; + } if (!events[DA7219_AAD_IRQ_REG_A] && !events[DA7219_AAD_IRQ_REG_B]) return IRQ_NONE; @@ -859,6 +863,8 @@ void da7219_aad_suspend(struct snd_soc_component *component) } } } + + synchronize_irq(da7219_aad->irq); } void da7219_aad_resume(struct snd_soc_component *component) diff --git a/sound/soc/codecs/es8316.c b/sound/soc/codecs/es8316.c index 57130edaf3aba6a79140855be390a6b9052ed049..0fc4755fd0d9d8515a8329b982d031bde6197ee6 100644 --- a/sound/soc/codecs/es8316.c +++ b/sound/soc/codecs/es8316.c @@ -45,7 +45,12 @@ static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dac_vol_tlv, -9600, 50, 1); static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9600, 50, 1); static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(alc_max_gain_tlv, -650, 150, 0); static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(alc_min_gain_tlv, -1200, 150, 0); -static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(alc_target_tlv, -1650, 150, 0); + +static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(alc_target_tlv, + 0, 10, TLV_DB_SCALE_ITEM(-1650, 150, 0), + 11, 11, TLV_DB_SCALE_ITEM(-150, 0, 0), +); + static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(hpmixer_gain_tlv, 0, 4, TLV_DB_SCALE_ITEM(-1200, 150, 0), 8, 11, TLV_DB_SCALE_ITEM(-450, 150, 0), @@ -107,7 +112,7 @@ static const struct snd_kcontrol_new es8316_snd_controls[] = { alc_max_gain_tlv), SOC_SINGLE_TLV("ALC Capture Min Volume", ES8316_ADC_ALC2, 0, 28, 0, alc_min_gain_tlv), - SOC_SINGLE_TLV("ALC Capture Target Volume", ES8316_ADC_ALC3, 4, 10, 0, + SOC_SINGLE_TLV("ALC Capture Target Volume", ES8316_ADC_ALC3, 4, 11, 0, alc_target_tlv), SOC_SINGLE("ALC Capture Hold Time", ES8316_ADC_ALC3, 0, 10, 0), SOC_SINGLE("ALC Capture Decay Time", ES8316_ADC_ALC4, 4, 10, 0), @@ -140,7 +145,7 @@ static const char * const es8316_dmic_txt[] = { "dmic data at high level", "dmic data at low level", }; -static const unsigned int es8316_dmic_values[] = { 0, 1, 2 }; +static const unsigned int es8316_dmic_values[] = { 0, 2, 3 }; static const struct soc_enum es8316_dmic_src_enum = SOC_VALUE_ENUM_SINGLE(ES8316_ADC_DMIC, 0, 3, ARRAY_SIZE(es8316_dmic_txt), diff --git a/sound/soc/codecs/nau8824.c b/sound/soc/codecs/nau8824.c index 4f18bb272e9294b3e7884235f7131819f8c4f15d..0ecea65a80b46720258554a8dfd3fbc78779c2d4 100644 --- a/sound/soc/codecs/nau8824.c +++ b/sound/soc/codecs/nau8824.c @@ -1899,6 +1899,30 @@ static const struct dmi_system_id nau8824_quirk_table[] = { }, .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH), }, + { + /* Positivo CW14Q01P */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"), + DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P"), + }, + .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH), + }, + { + /* Positivo K1424G */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"), + DMI_MATCH(DMI_BOARD_NAME, "K1424G"), + }, + .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH), + }, + { + /* Positivo N14ZP74G */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"), + DMI_MATCH(DMI_BOARD_NAME, "N14ZP74G"), + }, + .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH), + }, {} }; diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c index d34000182f67961d6d33ec736690eaa498ff80e9..a713e9649b56bb58167200ab853a530c08e9e6d7 100644 --- a/sound/soc/codecs/rt5645.c +++ b/sound/soc/codecs/rt5645.c @@ -3278,6 +3278,8 @@ int rt5645_set_jack_detect(struct snd_soc_component *component, RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1, RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); + regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1, + RT5645_HP_CB_MASK, RT5645_HP_CB_PU); } rt5645_irq(0, rt5645); diff --git a/sound/soc/codecs/rt5665.c b/sound/soc/codecs/rt5665.c index 6ba99f5ed3f42e54e52af662b6fbe647f25b6f0a..a7ed2a19c3ec255770cf401d4e93b13263e0e9fa 100644 --- a/sound/soc/codecs/rt5665.c +++ b/sound/soc/codecs/rt5665.c @@ -4475,6 +4475,8 @@ static void rt5665_remove(struct snd_soc_component *component) struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); regmap_write(rt5665->regmap, RT5665_RESET, 0); + + regulator_bulk_disable(ARRAY_SIZE(rt5665->supplies), rt5665->supplies); } #ifdef CONFIG_PM diff --git a/sound/soc/codecs/ssm2602.c b/sound/soc/codecs/ssm2602.c index 501a4e73b185ba9c1143a4de11da56626e7f3790..06f382c794b265ce349e79898edff855a6349aad 100644 --- a/sound/soc/codecs/ssm2602.c +++ b/sound/soc/codecs/ssm2602.c @@ -67,6 +67,18 @@ static const struct reg_default ssm2602_reg[SSM2602_CACHEREGNUM] = { { .reg = 0x09, .def = 0x0000 } }; +/* + * ssm2602 register patch + * Workaround for playback distortions after power up: activates digital + * core, and then powers on output, DAC, and whole chip at the same time + */ + +static const struct reg_sequence ssm2602_patch[] = { + { SSM2602_ACTIVE, 0x01 }, + { SSM2602_PWR, 0x07 }, + { SSM2602_RESET, 0x00 }, +}; + /*Appending several "None"s just for OSS mixer use*/ static const char *ssm2602_input_select[] = { @@ -577,6 +589,9 @@ static int ssm260x_component_probe(struct snd_soc_component *component) return ret; } + regmap_register_patch(ssm2602->regmap, ssm2602_patch, + ARRAY_SIZE(ssm2602_patch)); + /* set the update bits */ regmap_update_bits(ssm2602->regmap, SSM2602_LINVOL, LINVOL_LRIN_BOTH, LINVOL_LRIN_BOTH); diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c index d14e851b916058ad97bdcd5376ace19b80047c55..03d3b0f17f87778e2d87280bf2efff229d6fb4fe 100644 --- a/sound/soc/codecs/wm8904.c +++ b/sound/soc/codecs/wm8904.c @@ -2264,6 +2264,9 @@ static int wm8904_i2c_probe(struct i2c_client *i2c, regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0, WM8904_POBCTRL, 0); + /* Fill the cache for the ADC test register */ + regmap_read(wm8904->regmap, WM8904_ADC_TEST_0, &val); + /* Can leave the device powered off until we need it */ regcache_cache_only(wm8904->regmap, true); regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); diff --git a/sound/soc/dwc/dwc-i2s.c b/sound/soc/dwc/dwc-i2s.c index 65112b9d8588ae75995e618741e6c88ec87d0abf..90b8814d7506ac622606ff5e2479580f4ae409ff 100644 --- a/sound/soc/dwc/dwc-i2s.c +++ b/sound/soc/dwc/dwc-i2s.c @@ -132,13 +132,13 @@ static irqreturn_t i2s_irq_handler(int irq, void *dev_id) /* Error Handling: TX */ if (isr[i] & ISR_TXFO) { - dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i); + dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i); irq_valid = true; } /* Error Handling: TX */ if (isr[i] & ISR_RXFO) { - dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i); + dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i); irq_valid = true; } } diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c index 740b90df44bb5108a29d05ab14cdb7bd2d281849..0a1ba64ed63cfbc900b13511aa72a6b12f92d732 100644 --- a/sound/soc/fsl/fsl_spdif.c +++ b/sound/soc/fsl/fsl_spdif.c @@ -614,6 +614,8 @@ static int fsl_spdif_trigger(struct snd_pcm_substream *substream, case SNDRV_PCM_TRIGGER_PAUSE_PUSH: regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); + regmap_write(regmap, REG_SPDIF_STL, 0x0); + regmap_write(regmap, REG_SPDIF_STR, 0x0); break; default: return -EINVAL; diff --git a/sound/soc/generic/simple-card.c b/sound/soc/generic/simple-card.c index 64bf3560c1d1c4af58e6191a4dd22fe93bccac49..7567ee380283e8185678b4a806e00af5e990ae47 100644 --- a/sound/soc/generic/simple-card.c +++ b/sound/soc/generic/simple-card.c @@ -404,10 +404,12 @@ static int asoc_simple_card_probe(struct platform_device *pdev) } else { struct asoc_simple_card_info *cinfo; + ret = -EINVAL; + cinfo = dev->platform_data; if (!cinfo) { dev_err(dev, "no info for asoc-simple-card\n"); - return -EINVAL; + goto err; } if (!cinfo->name || @@ -416,7 +418,7 @@ static int asoc_simple_card_probe(struct platform_device *pdev) !cinfo->platform || !cinfo->cpu_dai.name) { dev_err(dev, "insufficient asoc_simple_card_info settings\n"); - return -EINVAL; + goto err; } card->name = (cinfo->card) ? cinfo->card : cinfo->name; diff --git a/sound/soc/intel/boards/bytcr_rt5640.c b/sound/soc/intel/boards/bytcr_rt5640.c index 2001bc774c643e8449f460329002b2ff2c1ff23d..d27dd170bedafbd75d180a0320828b09a6b2fd86 100644 --- a/sound/soc/intel/boards/bytcr_rt5640.c +++ b/sound/soc/intel/boards/bytcr_rt5640.c @@ -400,6 +400,18 @@ static int byt_rt5640_aif1_hw_params(struct snd_pcm_substream *substream, /* Please keep this list alphabetically sorted */ static const struct dmi_system_id byt_rt5640_quirk_table[] = { + { /* Acer Iconia One 7 B1-750 */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Insyde"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "VESPA2"), + }, + .driver_data = (void *)(BYT_RT5640_DMIC1_MAP | + BYT_RT5640_JD_SRC_JD1_IN4P | + BYT_RT5640_OVCD_TH_1500UA | + BYT_RT5640_OVCD_SF_0P75 | + BYT_RT5640_SSP0_AIF1 | + BYT_RT5640_MCLK_EN), + }, { /* Acer Iconia Tab 8 W1-810 */ .matches = { DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Acer"), diff --git a/sound/soc/intel/skylake/skl-sst-utils.c b/sound/soc/intel/skylake/skl-sst-utils.c index 2ae405617876281749525db63dad5fffd0e8305d..9e1e9bac17905f8590b29bf0d364306b71d7ff5c 100644 --- a/sound/soc/intel/skylake/skl-sst-utils.c +++ b/sound/soc/intel/skylake/skl-sst-utils.c @@ -317,6 +317,7 @@ int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw, module->instance_id = devm_kzalloc(ctx->dev, size, GFP_KERNEL); if (!module->instance_id) { ret = -ENOMEM; + kfree(module); goto free_uuid_list; } diff --git a/sound/soc/kirkwood/kirkwood-dma.c b/sound/soc/kirkwood/kirkwood-dma.c index 255cc45905b814a60df398a2779fd327f3b7df18..51f75523b691a765bb8ea9a0c9e30c0cd717596e 100644 --- a/sound/soc/kirkwood/kirkwood-dma.c +++ b/sound/soc/kirkwood/kirkwood-dma.c @@ -90,7 +90,7 @@ kirkwood_dma_conf_mbus_windows(void __iomem *base, int win, /* try to find matching cs for current dma address */ for (i = 0; i < dram->num_cs; i++) { - const struct mbus_dram_window *cs = dram->cs + i; + const struct mbus_dram_window *cs = &dram->cs[i]; if ((cs->base & 0xffff0000) < (dma & 0xffff0000)) { writel(cs->base & 0xffff0000, base + KIRKWOOD_AUDIO_WIN_BASE_REG(win)); diff --git a/sound/soc/meson/axg-tdm-formatter.c b/sound/soc/meson/axg-tdm-formatter.c index 43e390f9358a46da3959c36f30870135f4fd3acf..a195160b68208f7674515dbf924ede925e267260 100644 --- a/sound/soc/meson/axg-tdm-formatter.c +++ b/sound/soc/meson/axg-tdm-formatter.c @@ -28,27 +28,32 @@ int axg_tdm_formatter_set_channel_masks(struct regmap *map, struct axg_tdm_stream *ts, unsigned int offset) { - unsigned int val, ch = ts->channels; - unsigned long mask; - int i, j; + unsigned int ch = ts->channels; + u32 val[AXG_TDM_NUM_LANES]; + int i, j, k; + + /* + * We need to mimick the slot distribution used by the HW to keep the + * channel placement consistent regardless of the number of channel + * in the stream. This is why the odd algorithm below is used. + */ + memset(val, 0, sizeof(*val) * AXG_TDM_NUM_LANES); /* * Distribute the channels of the stream over the available slots - * of each TDM lane + * of each TDM lane. We need to go over the 32 slots ... */ - for (i = 0; i < AXG_TDM_NUM_LANES; i++) { - val = 0; - mask = ts->mask[i]; - - for (j = find_first_bit(&mask, 32); - (j < 32) && ch; - j = find_next_bit(&mask, 32, j + 1)) { - val |= 1 << j; - ch -= 1; + for (i = 0; (i < 32) && ch; i += 2) { + /* ... of all the lanes ... */ + for (j = 0; j < AXG_TDM_NUM_LANES; j++) { + /* ... then distribute the channels in pairs */ + for (k = 0; k < 2; k++) { + if ((BIT(i + k) & ts->mask[j]) && ch) { + val[j] |= BIT(i + k); + ch -= 1; + } + } } - - regmap_write(map, offset, val); - offset += regmap_get_reg_stride(map); } /* @@ -61,6 +66,11 @@ int axg_tdm_formatter_set_channel_masks(struct regmap *map, return -EINVAL; } + for (i = 0; i < AXG_TDM_NUM_LANES; i++) { + regmap_write(map, offset, val[i]); + offset += regmap_get_reg_stride(map); + } + return 0; } EXPORT_SYMBOL_GPL(axg_tdm_formatter_set_channel_masks); diff --git a/sound/soc/omap/ams-delta.c b/sound/soc/omap/ams-delta.c index 4dce494dfbd3e6c3e6cb3126cb0dfe4db13907eb..ef9fda16ce131d89137f4413da9ed9d51e57c8ec 100644 --- a/sound/soc/omap/ams-delta.c +++ b/sound/soc/omap/ams-delta.c @@ -300,7 +300,7 @@ static int cx81801_open(struct tty_struct *tty) static void cx81801_close(struct tty_struct *tty) { struct snd_soc_component *component = tty->disc_data; - struct snd_soc_dapm_context *dapm = &component->card->dapm; + struct snd_soc_dapm_context *dapm; del_timer_sync(&cx81801_timer); @@ -312,6 +312,8 @@ static void cx81801_close(struct tty_struct *tty) v253_ops.close(tty); + dapm = &component->card->dapm; + /* Revert back to default audio input/output constellation */ snd_soc_dapm_mutex_lock(dapm); diff --git a/sound/soc/pxa/pxa-ssp.c b/sound/soc/pxa/pxa-ssp.c index 69033e1a84e6ad52ef7c01b395af3a8f48a91c15..49481dadb9230873e9d02089aa016724b9877312 100644 --- a/sound/soc/pxa/pxa-ssp.c +++ b/sound/soc/pxa/pxa-ssp.c @@ -795,7 +795,7 @@ static int pxa_ssp_probe(struct snd_soc_dai *dai) if (IS_ERR(priv->extclk)) { ret = PTR_ERR(priv->extclk); if (ret == -EPROBE_DEFER) - return ret; + goto err_priv; priv->extclk = NULL; } diff --git a/sound/soc/soc-compress.c b/sound/soc/soc-compress.c index ea7f079acf3ab6433f70f3122c12b8d9ead6ae68..48e546e6393ade57e3ddc295e00bdcb78d01a1ae 100644 --- a/sound/soc/soc-compress.c +++ b/sound/soc/soc-compress.c @@ -1114,7 +1114,7 @@ int snd_soc_new_compress(struct snd_soc_pcm_runtime *rtd, int num) rtd->fe_compr = 1; if (rtd->dai_link->dpcm_playback) be_pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->private_data = rtd; - else if (rtd->dai_link->dpcm_capture) + if (rtd->dai_link->dpcm_capture) be_pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->private_data = rtd; memcpy(compr->ops, &soc_compr_dyn_ops, sizeof(soc_compr_dyn_ops)); } else { diff --git a/sound/usb/caiaq/input.c b/sound/usb/caiaq/input.c index e883659ea6e77b92493bd607acb18378f8bd3594..19951e1dbbb019c767ab8db247d274637507c840 100644 --- a/sound/usb/caiaq/input.c +++ b/sound/usb/caiaq/input.c @@ -817,6 +817,7 @@ int snd_usb_caiaq_input_init(struct snd_usb_caiaqdev *cdev) default: /* no input methods supported on this device */ + ret = -EINVAL; goto exit_free_idev; } diff --git a/sound/usb/endpoint.c b/sound/usb/endpoint.c index e428d8b36c00a4413fcf05750f01a771f3fa1e2d..56119a96d350907eccab8f53a80d0381ccdafb65 100644 --- a/sound/usb/endpoint.c +++ b/sound/usb/endpoint.c @@ -324,7 +324,7 @@ static void queue_pending_output_urbs(struct snd_usb_endpoint *ep) while (test_bit(EP_FLAG_RUNNING, &ep->flags)) { unsigned long flags; - struct snd_usb_packet_info *uninitialized_var(packet); + struct snd_usb_packet_info *packet; struct snd_urb_ctx *ctx = NULL; int err, i; diff --git a/sound/usb/format.c b/sound/usb/format.c index 01ba7a939ac4b8eaeb311725cbde1e05a9c8c375..342d6edb06adf039a3b909d514b3212efc9bc21e 100644 --- a/sound/usb/format.c +++ b/sound/usb/format.c @@ -53,8 +53,12 @@ static u64 parse_audio_format_i_type(struct snd_usb_audio *chip, case UAC_VERSION_1: default: { struct uac_format_type_i_discrete_descriptor *fmt = _fmt; - if (format >= 64) - return 0; /* invalid format */ + if (format >= 64) { + usb_audio_info(chip, + "%u:%d: invalid format type 0x%llx is detected, processed as PCM\n", + fp->iface, fp->altsetting, format); + format = UAC_FORMAT_TYPE_I_PCM; + } sample_width = fmt->bBitResolution; sample_bytes = fmt->bSubframeSize; format = 1ULL << format; diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h index e72f744bc305d0fb7fcce57fd3386f2cc0f81ef6..6c546f520f9945c6cee605ae4a5badf560c6bed6 100644 --- a/sound/usb/quirks-table.h +++ b/sound/usb/quirks-table.h @@ -3677,5 +3677,34 @@ ALC1220_VB_DESKTOP(0x26ce, 0x0a01), /* Asrock TRX40 Creator */ } } }, +{ + /* Advanced modes of the Mythware XA001AU. + * For the standard mode, Mythware XA001AU has ID ffad:a001 + */ + USB_DEVICE_VENDOR_SPEC(0xffad, 0xa001), + .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) { + .vendor_name = "Mythware", + .product_name = "XA001AU", + .ifnum = QUIRK_ANY_INTERFACE, + .type = QUIRK_COMPOSITE, + .data = (const struct snd_usb_audio_quirk[]) { + { + .ifnum = 0, + .type = QUIRK_IGNORE_INTERFACE, + }, + { + .ifnum = 1, + .type = QUIRK_AUDIO_STANDARD_INTERFACE, + }, + { + .ifnum = 2, + .type = QUIRK_AUDIO_STANDARD_INTERFACE, + }, + { + .ifnum = -1 + } + } + } +}, #undef USB_DEVICE_VENDOR_SPEC diff --git a/techpack/audio/Android.mk b/techpack/audio/Android.mk index 9b875d9701dd4c96bfd4b6170ca26f35e8137468..ab2e37355beaf6a6016bd3aeddbe8e14ee01a540 100644 --- a/techpack/audio/Android.mk +++ b/techpack/audio/Android.mk @@ -3,7 +3,7 @@ MY_LOCAL_PATH := $(call my-dir) UAPI_OUT := $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/include -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) $(shell mkdir -p $(UAPI_OUT)/linux;) $(shell mkdir -p $(UAPI_OUT)/sound;) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers) @@ -12,6 +12,9 @@ $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/codecs $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers) +ifeq ($(call is-board-platform-in-list, msm8953 msm8937),true) +$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd934x/Module.symvers) +endif include $(MY_LOCAL_PATH)/include/uapi/Android.mk include $(MY_LOCAL_PATH)/ipc/Android.mk @@ -66,12 +69,12 @@ $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codec include $(MY_LOCAL_PATH)/asoc/codecs/wcd937x/Android.mk endif -ifeq ($(call is-board-platform-in-list, lito),true) +ifeq ($(call is-board-platform-in-list, kona lito),true) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wsa883x/Module.symvers) include $(MY_LOCAL_PATH)/asoc/codecs/wsa883x/Android.mk endif -ifeq ($(call is-board-platform-in-list, sdm660),true) +ifeq ($(call is-board-platform-in-list, sdm660 msm8953 msm8937),true) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/sdm660_cdc/Module.symvers) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/msm_sdw/Module.symvers) include $(MY_LOCAL_PATH)/asoc/codecs/sdm660_cdc/Android.mk diff --git a/techpack/audio/Makefile.am b/techpack/audio/Makefile.am index b5f37d28bf74510eee61d615be50c8567dd1dfb7..b10cd8720b23308a5150e1c175c215c859a0a31d 100644 --- a/techpack/audio/Makefile.am +++ b/techpack/audio/Makefile.am @@ -20,6 +20,9 @@ endif ifeq ($(TARGET_SUPPORT),sdm660) KBUILD_OPTIONS += CONFIG_ARCH_SDM660=y endif +ifeq ($(TARGET_SUPPORT),apq8053 msm8953 msm8937) +KBUILD_OPTIONS += CONFIG_ARCH_SDM450=y +endif obj-m := ipc/ obj-m += dsp/ @@ -40,12 +43,13 @@ obj-m += asoc/codecs/bolero/ obj-m += asoc/codecs/wcd937x/ endif -ifeq ($(TARGET_SUPPORT), qrb5165) +ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qrb5165 sxr2130)) obj-m += asoc/codecs/bolero/ obj-m += asoc/codecs/wcd938x/ +obj-m += asoc/codecs/wsa883x/ endif -ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sdm660)) +ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), apq8053 sdm660 msm8953 msm8937)) obj-m += asoc/codecs/sdm660_cdc/ endif @@ -61,7 +65,7 @@ endif ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sa6155)) KBUILD_OPTIONS += CONFIG_SND_SOC_SA6155=m endif -ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qrb5165)) +ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qrb5165 sxr2130)) KBUILD_OPTIONS += CONFIG_SND_SOC_KONA=m endif endif diff --git a/techpack/audio/asoc/Android.mk b/techpack/audio/asoc/Android.mk index c6e5a354f0caad9b22ed03b88974531456d3514c..b2cac8fe7e0591a0d07fa046a077e043965052c1 100644 --- a/techpack/audio/asoc/Android.mk +++ b/techpack/audio/asoc/Android.mk @@ -46,9 +46,15 @@ TARGET := sdm660 AUDIO_SELECT := CONFIG_SND_SOC_SDM660=m endif +ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) +TARGET := sdm450 +AUDIO_SELECT += CONFIG_SND_SOC_SDM450=m +AUDIO_SELECT += CONFIG_SND_SOC_EXT_CODEC_SDM450=m +endif + AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) @@ -83,7 +89,7 @@ LOCAL_MODULE_DEBUG_ENABLE := true LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk ########################################################### -ifeq ($(call is-board-platform-in-list, ),true) +ifeq ($(call is-board-platform-in-list, sdm660 msm8953 msm8937),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_cpe_lsm.ko LOCAL_MODULE_KBUILD_NAME := cpe_lsm_dlkm.ko @@ -101,6 +107,16 @@ LOCAL_MODULE_DEBUG_ENABLE := true LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk ########################################################### +ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) +include $(CLEAR_VARS) +LOCAL_MODULE := $(AUDIO_CHIPSET)_machine_ext_$(TARGET).ko +LOCAL_MODULE_KBUILD_NAME := machine_ext_dlkm.ko +LOCAL_MODULE_TAGS := optional +LOCAL_MODULE_DEBUG_ENABLE := true +LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) +include $(DLKM_DIR)/AndroidKernelModule.mk +endif +########################################################### endif # DLKM check endif # supported target check diff --git a/techpack/audio/asoc/Kbuild b/techpack/audio/asoc/Kbuild index a0d8de1f66e7b29d03e9c67b9c7bf2884bf89ef3..dddfd1440a834149accec249a2702f95dd6b5565 100644 --- a/techpack/audio/asoc/Kbuild +++ b/techpack/audio/asoc/Kbuild @@ -81,6 +81,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: @@ -170,6 +185,17 @@ ifdef CONFIG_SND_SOC_CPE CPE_LSM_OBJS += msm-cpe-lsm.o endif +# for SDM450 internal codec sound card driver +ifdef CONFIG_SND_SOC_SDM450 + MACHINE_OBJS += msm8952.o +endif + +# for SDM450 external codec sound card driver +ifdef CONFIG_SND_SOC_EXT_CODEC_SDM450 + MACHINE_EXT_OBJS += msm8952-slimbus.o + MACHINE_EXT_OBJS += msm8952-dai-links.o +endif + ifdef CONFIG_SND_SOC_QDSP6V2 PLATFORM_OBJS += msm-audio-effects-q6-v2.o PLATFORM_OBJS += msm-compress-q6-v2.o @@ -254,6 +280,12 @@ endif obj-$(CONFIG_SND_SOC_QDSP6V2) += platform_dlkm.o platform_dlkm-y := $(PLATFORM_OBJS) +obj-$(CONFIG_SND_SOC_SDM450) += machine_dlkm.o +machine_dlkm-y := $(MACHINE_OBJS) + +obj-$(CONFIG_SND_SOC_EXT_CODEC_SDM450) += machine_ext_dlkm.o +machine_ext_dlkm-y := $(MACHINE_EXT_OBJS) + obj-$(CONFIG_SND_SOC_SM8150) += machine_dlkm.o machine_dlkm-y := $(MACHINE_OBJS) @@ -286,6 +318,3 @@ machine_dlkm-y := $(MACHINE_OBJS) obj-$(CONFIG_SND_SOC_CPE) += cpe_lsm_dlkm.o cpe_lsm_dlkm-y := $(CPE_LSM_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/bengal-port-config.h b/techpack/audio/asoc/bengal-port-config.h index 37d4f740aac65b15155781be7a1ff81dde809582..19e3d6fcc88b913e8f2b71ca385ccd5ea9e6aa86 100644 --- a/techpack/audio/asoc/bengal-port-config.h +++ b/techpack/audio/asoc/bengal-port-config.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #ifndef _BENGAL_PORT_CONFIG @@ -38,6 +38,14 @@ static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = { {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0}, }; +static struct port_params rx_frame_params_khaje[SWR_MSTR_PORT_LEN] = { + {3, 1, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0}, + {31, 0, 0, 3, 6, 7, 0, 0xFF, 0}, + {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0}, + {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, + {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0}, +}; + /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX1 */ @@ -56,4 +64,10 @@ static struct swr_mstr_port_map sm_port_map_rouleur[] = { {RX_MACRO, SWR_UC0, rx_frame_params_rouleur}, {RX_MACRO, SWR_UC1, rx_frame_params_dsd}, }; + +static struct swr_mstr_port_map sm_port_map_khaje[] = { + {VA_MACRO, SWR_UC0, tx_frame_params_default}, + {RX_MACRO, SWR_UC0, rx_frame_params_khaje}, + {RX_MACRO, SWR_UC1, rx_frame_params_dsd}, +}; #endif /* _BENGAL_PORT_CONFIG */ diff --git a/techpack/audio/asoc/bengal.c b/techpack/audio/asoc/bengal.c index 15c2104922b230a767308ceecaf726802888d8b9..f3e50ef42c4f8de2ff4c44d161b383570c1e3b53 100644 --- a/techpack/audio/asoc/bengal.c +++ b/techpack/audio/asoc/bengal.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */ #include @@ -555,6 +555,7 @@ static struct snd_soc_codec_conf *msm_codec_conf; static struct snd_soc_card snd_soc_card_bengal_msm; static int dmic_0_1_gpio_cnt; static int dmic_2_3_gpio_cnt; +static u32 wcd_datalane_mismatch; static void *def_wcd_mbhc_cal(void); static void *def_rouleur_mbhc_cal(void); @@ -4330,7 +4331,11 @@ static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd) data = (char*) of_device_get_match_data( &pdev->dev); if (data != NULL) { - if (!strncmp(data, "wcd937x", + if (wcd_datalane_mismatch) { + bolero_set_port_map(component, + ARRAY_SIZE(sm_port_map_khaje), + sm_port_map_khaje); + } else if (!strncmp(data, "wcd937x", sizeof("wcd937x"))) { bolero_set_port_map(component, ARRAY_SIZE(sm_port_map), @@ -6735,6 +6740,10 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) if (ret) goto err; + ret = of_property_read_u32(pdev->dev.of_node, + "qcom,wcd-datalane-mismatch", + &wcd_datalane_mismatch); + ret = devm_snd_soc_register_card(&pdev->dev, card); if (ret == -EPROBE_DEFER) { if (codec_reg_done) diff --git a/techpack/audio/asoc/codecs/Android.mk b/techpack/audio/asoc/codecs/Android.mk index 7fb175426afd0500833a8a8e5b5bb796b4e3da71..08c555b53a13eff572053c54e09799c1f7bcea88 100644 --- a/techpack/audio/asoc/codecs/Android.mk +++ b/techpack/audio/asoc/codecs/Android.mk @@ -39,9 +39,14 @@ ifeq ($(call is-board-platform,sdm660),true) AUDIO_SELECT := CONFIG_SND_SOC_SDM660=m endif +ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) +AUDIO_SELECT += CONFIG_SND_SOC_SDM450=m +AUDIO_SELECT += CONFIG_SND_SOC_EXT_CODEC_SDM450=m +endif + AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) @@ -85,7 +90,7 @@ LOCAL_MODULE_DEBUG_ENABLE := true LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk ########################################################### -ifeq ($(call is-board-platform-in-list, ),true) +ifeq ($(call is-board-platform-in-list, sdm660 msm8953 msm8937),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd_cpe.ko LOCAL_MODULE_KBUILD_NAME := wcd_cpe_dlkm.ko @@ -95,7 +100,7 @@ LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk endif ########################################################### -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) sdmshrike),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) sdmshrike sdm660),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd_spi.ko LOCAL_MODULE_KBUILD_NAME := wcd_spi_dlkm.ko @@ -105,7 +110,7 @@ LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk endif ########################################################### -ifeq ($(call is-board-platform-in-list, sdm660),true) +ifeq ($(call is-board-platform-in-list, sdm660 msm8953 msm8937),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd9335.ko LOCAL_MODULE_KBUILD_NAME := wcd9335_dlkm.ko @@ -125,7 +130,7 @@ LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk endif ########################################################### -ifeq ($(call is-board-platform-in-list, bengal),true) +ifeq ($(call is-board-platform-in-list, bengal msm8953 msm8937),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_wsa881x_analog.ko LOCAL_MODULE_KBUILD_NAME := wsa881x_analog_dlkm.ko diff --git a/techpack/audio/asoc/codecs/Kbuild b/techpack/audio/asoc/codecs/Kbuild index 20b92625088cc4679aa161786a301d6605135d61..d9803200bddbc34639ec604b24eb9d932c0a3f04 100644 --- a/techpack/audio/asoc/codecs/Kbuild +++ b/techpack/audio/asoc/codecs/Kbuild @@ -75,6 +75,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: @@ -152,8 +167,10 @@ ifdef CONFIG_SND_SOC_WSA881X_ANALOG WSA881X_ANALOG_OBJS += wsa881x-analog.o WSA881X_ANALOG_OBJS += wsa881x-tables-analog.o WSA881X_ANALOG_OBJS += wsa881x-regmap-analog.o +ifdef CONFIG_SND_SOC_BENGAL WSA881X_ANALOG_OBJS += wsa881x-temp-sensor.o endif +endif ifdef CONFIG_SND_SOC_MSM_STUB STUB_OBJS += msm_stub.o endif @@ -203,6 +220,7 @@ CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \ -DPTT_SOCK_SVC_ENABLE \ -Wall\ -Werror\ + -Wno-enum-conversion \ -D__linux__ KBUILD_CPPFLAGS += $(CDEFINES) @@ -274,6 +292,3 @@ mbhc_dlkm-y := $(MBHC_OBJS) obj-$(CONFIG_SND_SOC_MSM_HDMI_CODEC_RX) += hdmi_dlkm.o hdmi_dlkm-y := $(HDMICODEC_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/aqt1000/Kbuild b/techpack/audio/asoc/codecs/aqt1000/Kbuild index d83955f0ad374d30f3ebaf26f70e1158a7e8f837..c7f8b895c6c602e78ab8dcf375e2d5dad6d06c20 100644 --- a/techpack/audio/asoc/codecs/aqt1000/Kbuild +++ b/techpack/audio/asoc/codecs/aqt1000/Kbuild @@ -115,6 +115,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_SND_SOC_AQT1000) += aqt1000_cdc_dlkm.o aqt1000_cdc_dlkm-y := $(AQT1000_CDC_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/audio-ext-clk-up.c b/techpack/audio/asoc/codecs/audio-ext-clk-up.c index fc3cb386f42c91abfcec61a04e5ede3b47cbb1dd..3da8c1928a00db83f3af33bf4693ca06e072c377 100644 --- a/techpack/audio/asoc/codecs/audio-ext-clk-up.c +++ b/techpack/audio/asoc/codecs/audio-ext-clk-up.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ #include @@ -9,6 +10,8 @@ #include #include #include +#include +#include #include "../../../drivers/clk/qcom/common.h" #include #include @@ -29,6 +32,8 @@ enum { AUDIO_EXT_CLK_LPASS_CORE_HW_VOTE, AUDIO_EXT_CLK_LPASS8, AUDIO_EXT_CLK_LPASS_AUDIO_HW_VOTE, + AUDIO_EXT_CLK_PM660_PMI, + AUDIO_EXT_CLK_DIV_CLK2, AUDIO_EXT_CLK_LPASS_MAX, AUDIO_EXT_CLK_EXTERNAL_PLL = AUDIO_EXT_CLK_LPASS_MAX, AUDIO_EXT_CLK_MAX, @@ -44,6 +49,7 @@ struct pinctrl_info { struct audio_ext_clk { struct pinctrl_info pnctrl_info; struct clk_fixed_factor fact; + int gpio; }; struct audio_ext_clk_priv { @@ -105,7 +111,7 @@ static void audio_ext_clk_unprepare(struct clk_hw *hw) ret = pinctrl_select_state(pnctrl_info->pinctrl, pnctrl_info->sleep); if (ret) { - pr_err("%s: active state select failed with %d\n", + pr_err("%s: sleep state select failed with %d\n", __func__, ret); return; } @@ -387,6 +393,32 @@ static struct audio_ext_clk audio_clk_array[] = { }, }, }, + { + .gpio = -EINVAL, + .fact = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "audio_ext_pm660_pmi_clk", + .parent_names = (const char *[]){ "div_clk1" }, + .num_parents = 1, + .ops = &audio_ext_clk_dummy_ops, + }, + }, + }, + { + .pnctrl_info = {NULL}, + .fact = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "audio_ext_div_clk2", + .parent_names = (const char *[]){ "div_clk2" }, + .num_parents = 1, + .ops = &audio_ext_clk_ops, + }, + }, + }, }; static int audio_get_pinctrl(struct platform_device *pdev) @@ -510,6 +542,7 @@ static int audio_ref_clk_probe(struct platform_device *pdev) int ret; struct audio_ext_clk_priv *clk_priv; u32 clk_freq = 0, clk_id = 0, clk_src = 0, use_pinctrl = 0; + int clk_gpio; clk_priv = devm_kzalloc(&pdev->dev, sizeof(*clk_priv), GFP_KERNEL); if (!clk_priv) @@ -581,11 +614,30 @@ static int audio_ref_clk_probe(struct platform_device *pdev) } } + clk_gpio = of_get_named_gpio(pdev->dev.of_node, + "qcom,audio-ref-clk-gpio", 0); + if (clk_gpio > 0) { + ret = gpio_request(clk_gpio, "EXT_CLK"); + if (ret) { + dev_err(&pdev->dev, + "Request ext clk gpio failed %d, err:%d\n", + clk_gpio, ret); + return ret; + } + if (of_property_read_bool(pdev->dev.of_node, + "qcom,node_has_rpm_clock")) { + clk_priv->audio_clk.gpio = clk_gpio; + } + } + ret = audio_get_clk_data(pdev); if (ret) { dev_err(&pdev->dev, "%s: clk_init is failed\n", __func__); - audio_put_pinctrl(pdev); + if (use_pinctrl) + audio_put_pinctrl(pdev); + if (clk_priv->audio_clk.gpio > 0) + gpio_free(clk_priv->audio_clk.gpio); return ret; } return 0; @@ -593,7 +645,11 @@ static int audio_ref_clk_probe(struct platform_device *pdev) static int audio_ref_clk_remove(struct platform_device *pdev) { + struct audio_ext_clk_priv *clk_priv = platform_get_drvdata(pdev); + audio_put_pinctrl(pdev); + if (clk_priv->audio_clk.gpio > 0) + gpio_free(clk_priv->audio_clk.gpio); return 0; } diff --git a/techpack/audio/asoc/codecs/bolero/Kbuild b/techpack/audio/asoc/codecs/bolero/Kbuild index 15e5dc576da344de5ed3c32f1c76b3c674f0866a..9042ebfa8e1e05a00dfd40aa61e1353ae79c0708 100644 --- a/techpack/audio/asoc/codecs/bolero/Kbuild +++ b/techpack/audio/asoc/codecs/bolero/Kbuild @@ -154,6 +154,3 @@ tx_macro_dlkm-y := $(TX_OBJS) obj-$(CONFIG_RX_MACRO) += rx_macro_dlkm.o rx_macro_dlkm-y := $(RX_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/bolero/rx-macro.c b/techpack/audio/asoc/codecs/bolero/rx-macro.c index 0297cde4f4df1bb552fd3cec62baedfde3fc9e5e..10a382620f5bcd435e48e91891c8889b0543e74c 100644 --- a/techpack/audio/asoc/codecs/bolero/rx-macro.c +++ b/techpack/audio/asoc/codecs/bolero/rx-macro.c @@ -2605,7 +2605,8 @@ static void rx_macro_hphdelay_lutbypass(struct snd_soc_component *component, } if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) { - snd_soc_component_update_bits(component, + if (!rx_priv->is_ear_mode_on) + snd_soc_component_update_bits(component, BOLERO_CDC_RX_RX0_RX_PATH_CFG1, 0x02, 0x00); snd_soc_component_update_bits(component, hph_lut_bypass_reg, diff --git a/techpack/audio/asoc/codecs/bolero/tx-macro.c b/techpack/audio/asoc/codecs/bolero/tx-macro.c index ba628fc3d36e1faba3b6cb094fc3cd9ed48478ef..e456d36444fd04be2815681cc92b59c0181a0154 100644 --- a/techpack/audio/asoc/codecs/bolero/tx-macro.c +++ b/techpack/audio/asoc/codecs/bolero/tx-macro.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include @@ -183,7 +183,7 @@ struct tx_macro_priv { int dec_mode[NUM_DECIMATORS]; bool bcs_clk_en; bool hs_slow_insert_complete; - int amic_sample_rate; + int pcm_rate[NUM_DECIMATORS]; }; static bool tx_macro_get_data(struct snd_soc_component *component, @@ -510,7 +510,7 @@ static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) 0x03, 0x02); /* Add delay between toggle hpf gate based on sample rate */ #ifdef OPLUS_ARCH_EXTENDS - switch(tx_priv->amic_sample_rate) { + switch(tx_priv->pcm_rate[hpf_work->decimator]) { case 0: usleep_range(125, 130); break; @@ -533,23 +533,23 @@ static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) usleep_range(125, 130); } #else - switch(tx_priv->amic_sample_rate) { - case 8000: + switch (tx_priv->pcm_rate[hpf_work->decimator]) { + case 0: usleep_range(125, 130); break; - case 16000: + case 1: usleep_range(62, 65); break; - case 32000: + case 3: usleep_range(31, 32); break; - case 48000: + case 4: usleep_range(20, 21); break; - case 96000: + case 5: usleep_range(10, 11); break; - case 192000: + case 6: usleep_range(5, 6); break; default: @@ -986,7 +986,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, tx_fs_reg = BOLERO_CDC_TX0_TX_PATH_CTL + TX_MACRO_TX_PATH_OFFSET * decimator; - tx_priv->amic_sample_rate = (snd_soc_component_read32(component, + tx_priv->pcm_rate[decimator] = (snd_soc_component_read32(component, tx_fs_reg) & 0x0F); switch (event) { diff --git a/techpack/audio/asoc/codecs/bolero/va-macro.c b/techpack/audio/asoc/codecs/bolero/va-macro.c index 178d66c0a751f35e0fca044a052fd10c201f6689..977f32dcec52fd6def65796638567c8b3211c333 100644 --- a/techpack/audio/asoc/codecs/bolero/va-macro.c +++ b/techpack/audio/asoc/codecs/bolero/va-macro.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include @@ -176,6 +176,7 @@ struct va_macro_priv { bool lpi_enable; bool register_event_listener; int dec_mode[VA_MACRO_NUM_DECIMATORS]; + int pcm_rate[VA_MACRO_NUM_DECIMATORS]; }; static bool va_macro_get_data(struct snd_soc_component *component, @@ -840,8 +841,29 @@ static void va_macro_tx_hpf_corner_freq_callback(struct work_struct *work) hpf_cut_off_freq << 5); snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x02); - /* Minimum 1 clk cycle delay is required as per HW spec */ - usleep_range(1000, 1010); + /* Add delay between toggle hpf gate based on sample rate */ + switch (va_priv->pcm_rate[hpf_work->decimator]) { + case 0: + usleep_range(125, 130); + break; + case 1: + usleep_range(62, 65); + break; + case 3: + usleep_range(31, 32); + break; + case 4: + usleep_range(20, 21); + break; + case 5: + usleep_range(10, 11); + break; + case 6: + usleep_range(5, 6); + break; + default: + usleep_range(125, 130); + } snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x01); } else { @@ -1097,6 +1119,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg; u16 tx_gain_ctl_reg; u8 hpf_cut_off_freq; + u16 tx_fs_reg = 0; struct device *va_dev = NULL; struct va_macro_priv *va_priv = NULL; int hpf_delay = BOLERO_CDC_VA_TX_DMIC_HPF_DELAY_MS; @@ -1118,6 +1141,10 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, VA_MACRO_TX_PATH_OFFSET * decimator; tx_gain_ctl_reg = BOLERO_CDC_VA_TX0_TX_VOL_CTL + VA_MACRO_TX_PATH_OFFSET * decimator; + tx_fs_reg = BOLERO_CDC_VA_TX0_TX_PATH_CTL + + VA_MACRO_TX_PATH_OFFSET * decimator; + va_priv->pcm_rate[decimator] = (snd_soc_component_read32(component, + tx_fs_reg) & 0x0F); switch (event) { case SND_SOC_DAPM_PRE_PMU: diff --git a/techpack/audio/asoc/codecs/csra66x0/Kbuild b/techpack/audio/asoc/codecs/csra66x0/Kbuild index ef599622dd258db0f665a76a95e8c5a00c50f2d9..fe77d62718f8a5dd0da6df1dc5085076a6e51ec5 100644 --- a/techpack/audio/asoc/codecs/csra66x0/Kbuild +++ b/techpack/audio/asoc/codecs/csra66x0/Kbuild @@ -100,6 +100,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_SND_SOC_CSRA66X0) += csra66x0_dlkm.o csra66x0_dlkm-y := $(CSRA66X0_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/ep92/Kbuild b/techpack/audio/asoc/codecs/ep92/Kbuild index fc46a72f775d0dfabb36309326c4bb1b9817c5d8..ee4db7f39caf64ba320eef149c94d1443c9e7a78 100644 --- a/techpack/audio/asoc/codecs/ep92/Kbuild +++ b/techpack/audio/asoc/codecs/ep92/Kbuild @@ -101,6 +101,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_SND_SOC_EP92) += ep92_dlkm.o ep92_dlkm-y := $(EP92_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/ep92/ep92.c b/techpack/audio/asoc/codecs/ep92/ep92.c index 07a328189331c81b6cf858da01779242c960f5b5..54cf45137a4fbb779352a5d028193a195c67f51a 100644 --- a/techpack/audio/asoc/codecs/ep92/ep92.c +++ b/techpack/audio/asoc/codecs/ep92/ep92.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include @@ -44,6 +44,61 @@ static const unsigned int ep92_dsd_freq_table[4] = { 64, 128, 256, 0 }; +/* EP92 register default values */ +static struct reg_default ep92_reg_defaults[] = { + {EP92_BI_VENDOR_ID_0, 0x17}, + {EP92_BI_VENDOR_ID_1, 0x7A}, + {EP92_BI_DEVICE_ID_0, 0x94}, + {EP92_BI_DEVICE_ID_1, 0xA3}, + {EP92_BI_VERSION_NUM, 0x10}, + {EP92_BI_VERSION_YEAR, 0x09}, + {EP92_BI_VERSION_MONTH, 0x07}, + {EP92_BI_VERSION_DATE, 0x06}, + {EP92_BI_GENERAL_INFO_0, 0x00}, + {EP92_BI_GENERAL_INFO_1, 0x00}, + {EP92_BI_GENERAL_INFO_2, 0x00}, + {EP92_BI_GENERAL_INFO_3, 0x00}, + {EP92_BI_GENERAL_INFO_4, 0x00}, + {EP92_BI_GENERAL_INFO_5, 0x00}, + {EP92_BI_GENERAL_INFO_6, 0x00}, + {EP92_ISP_MODE_ENTER_ISP, 0x00}, + {EP92_GENERAL_CONTROL_0, 0x20}, + {EP92_GENERAL_CONTROL_1, 0x00}, + {EP92_GENERAL_CONTROL_2, 0x00}, + {EP92_GENERAL_CONTROL_3, 0x10}, + {EP92_GENERAL_CONTROL_4, 0x00}, + {EP92_CEC_EVENT_CODE, 0x00}, + {EP92_CEC_EVENT_PARAM_1, 0x00}, + {EP92_CEC_EVENT_PARAM_2, 0x00}, + {EP92_CEC_EVENT_PARAM_3, 0x00}, + {EP92_CEC_EVENT_PARAM_4, 0x00}, + {EP92_AUDIO_INFO_SYSTEM_STATUS_0, 0x00}, + {EP92_AUDIO_INFO_SYSTEM_STATUS_1, 0x00}, + {EP92_AUDIO_INFO_AUDIO_STATUS, 0x00}, + {EP92_AUDIO_INFO_CHANNEL_STATUS_0, 0x00}, + {EP92_AUDIO_INFO_CHANNEL_STATUS_1, 0x00}, + {EP92_AUDIO_INFO_CHANNEL_STATUS_2, 0x00}, + {EP92_AUDIO_INFO_CHANNEL_STATUS_3, 0x00}, + {EP92_AUDIO_INFO_CHANNEL_STATUS_4, 0x00}, + {EP92_AUDIO_INFO_ADO_INFO_FRAME_0, 0x00}, + {EP92_AUDIO_INFO_ADO_INFO_FRAME_1, 0x00}, + {EP92_AUDIO_INFO_ADO_INFO_FRAME_2, 0x00}, + {EP92_AUDIO_INFO_ADO_INFO_FRAME_3, 0x00}, + {EP92_AUDIO_INFO_ADO_INFO_FRAME_4, 0x00}, + {EP92_AUDIO_INFO_ADO_INFO_FRAME_5, 0x00}, + {EP92_OTHER_PACKETS_HDMI_VS_0, 0x00}, + {EP92_OTHER_PACKETS_HDMI_VS_1, 0x00}, + {EP92_OTHER_PACKETS_ACP_PACKET, 0x00}, + {EP92_OTHER_PACKETS_AVI_INFO_FRAME_0, 0x00}, + {EP92_OTHER_PACKETS_AVI_INFO_FRAME_1, 0x00}, + {EP92_OTHER_PACKETS_AVI_INFO_FRAME_2, 0x00}, + {EP92_OTHER_PACKETS_AVI_INFO_FRAME_3, 0x00}, + {EP92_OTHER_PACKETS_AVI_INFO_FRAME_4, 0x00}, + {EP92_OTHER_PACKETS_GC_PACKET_0, 0x00}, + {EP92_OTHER_PACKETS_GC_PACKET_1, 0x00}, + {EP92_OTHER_PACKETS_GC_PACKET_2, 0x00}, +}; + static bool ep92_volatile_register(struct device *dev, unsigned int reg) { /* do not cache register state in regmap */ @@ -115,6 +170,77 @@ struct ep92_pdata { #endif /* CONFIG_DEBUG_FS */ }; +struct ep92_mclk_cfg_info { + uint32_t in_sample_rate; + uint32_t out_mclk_freq; + uint8_t mul_val; +}; + +#define EP92_MCLK_MUL_512 0x3 +#define EP92_MCLK_MUL_384 0x2 +#define EP92_MCLK_MUL_256 0x1 +#define EP92_MCLK_MUL_128 0x0 +#define EP92_MCLK_MUL_MASK 0x3 + +/** + * ep92_set_ext_mclk - Configure the mclk based on sample freq + * + * @codec: handle pointer to ep92 codec + * @mclk_freq: mclk frequency to be set + * + * Returns 0 for success or appropriate negative error code + */ +int ep92_set_ext_mclk(struct snd_soc_codec *codec, uint32_t mclk_freq) +{ + unsigned int samp_freq = 0; + struct ep92_pdata *ep92 = NULL; + uint8_t value = 0; + int ret = 0; + + if (!codec) + return -EINVAL; + + ep92 = snd_soc_codec_get_drvdata(codec); + + samp_freq = ep92_samp_freq_table[(ep92->ai.audio_status) & + EP92_AI_RATE_MASK]; + + if (!mclk_freq || (mclk_freq % samp_freq)) { + pr_err("%s incompatbile mclk:%u and sample freq:%u\n", + __func__, mclk_freq, samp_freq); + return -EINVAL; + } + + switch (mclk_freq / samp_freq) { + case 512: + value = EP92_MCLK_MUL_512; + break; + case 384: + value = EP92_MCLK_MUL_384; + break; + case 256: + value = EP92_MCLK_MUL_256; + break; + case 128: + value = EP92_MCLK_MUL_128; + break; + default: + dev_err(codec->dev, "unsupported mclk:%u for sample freq:%u\n", + mclk_freq, samp_freq); + return -EINVAL; + } + + pr_debug("%s mclk:%u, in sample freq:%u, write reg:0x%02x val:0x%02x\n", + __func__, mclk_freq, samp_freq, + EP92_GENERAL_CONTROL_2, EP92_MCLK_MUL_MASK & value); + + ret = snd_soc_update_bits(codec, EP92_GENERAL_CONTROL_2, + EP92_MCLK_MUL_MASK, value); + + return (((ret == 0) || (ret == 1)) ? 0 : ret); +} +EXPORT_SYMBOL(ep92_set_ext_mclk); + #if IS_ENABLED(CONFIG_DEBUG_FS) static int debugfs_codec_open_op(struct inode *inode, struct file *file) { diff --git a/techpack/audio/asoc/codecs/ep92/ep92.h b/techpack/audio/asoc/codecs/ep92/ep92.h index 22384fbb6783ceb04d8369dc67b2c7d9c679bd1d..2274f4048f58e0c8939e03f8352c5068d14d272c 100644 --- a/techpack/audio/asoc/codecs/ep92/ep92.h +++ b/techpack/audio/asoc/codecs/ep92/ep92.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #ifndef __EP92_H__ @@ -69,63 +69,6 @@ #define EP92_MAX_REGISTER_ADDR EP92_OTHER_PACKETS_GC_PACKET_2 - -/* EP92 register default values */ -static struct reg_default ep92_reg_defaults[] = { - {EP92_BI_VENDOR_ID_0, 0x17}, - {EP92_BI_VENDOR_ID_1, 0x7A}, - {EP92_BI_DEVICE_ID_0, 0x94}, - {EP92_BI_DEVICE_ID_1, 0xA3}, - {EP92_BI_VERSION_NUM, 0x10}, - {EP92_BI_VERSION_YEAR, 0x09}, - {EP92_BI_VERSION_MONTH, 0x07}, - {EP92_BI_VERSION_DATE, 0x06}, - {EP92_BI_GENERAL_INFO_0, 0x00}, - {EP92_BI_GENERAL_INFO_1, 0x00}, - {EP92_BI_GENERAL_INFO_2, 0x00}, - {EP92_BI_GENERAL_INFO_3, 0x00}, - {EP92_BI_GENERAL_INFO_4, 0x00}, - {EP92_BI_GENERAL_INFO_5, 0x00}, - {EP92_BI_GENERAL_INFO_6, 0x00}, - {EP92_ISP_MODE_ENTER_ISP, 0x00}, - {EP92_GENERAL_CONTROL_0, 0x20}, - {EP92_GENERAL_CONTROL_1, 0x00}, - {EP92_GENERAL_CONTROL_2, 0x00}, - {EP92_GENERAL_CONTROL_3, 0x10}, - {EP92_GENERAL_CONTROL_4, 0x00}, - {EP92_CEC_EVENT_CODE, 0x00}, - {EP92_CEC_EVENT_PARAM_1, 0x00}, - {EP92_CEC_EVENT_PARAM_2, 0x00}, - {EP92_CEC_EVENT_PARAM_3, 0x00}, - {EP92_CEC_EVENT_PARAM_4, 0x00}, - {EP92_AUDIO_INFO_SYSTEM_STATUS_0, 0x00}, - {EP92_AUDIO_INFO_SYSTEM_STATUS_1, 0x00}, - {EP92_AUDIO_INFO_AUDIO_STATUS, 0x00}, - {EP92_AUDIO_INFO_CHANNEL_STATUS_0, 0x00}, - {EP92_AUDIO_INFO_CHANNEL_STATUS_1, 0x00}, - {EP92_AUDIO_INFO_CHANNEL_STATUS_2, 0x00}, - {EP92_AUDIO_INFO_CHANNEL_STATUS_3, 0x00}, - {EP92_AUDIO_INFO_CHANNEL_STATUS_4, 0x00}, - {EP92_AUDIO_INFO_ADO_INFO_FRAME_0, 0x00}, - {EP92_AUDIO_INFO_ADO_INFO_FRAME_1, 0x00}, - {EP92_AUDIO_INFO_ADO_INFO_FRAME_2, 0x00}, - {EP92_AUDIO_INFO_ADO_INFO_FRAME_3, 0x00}, - {EP92_AUDIO_INFO_ADO_INFO_FRAME_4, 0x00}, - {EP92_AUDIO_INFO_ADO_INFO_FRAME_5, 0x00}, - {EP92_OTHER_PACKETS_HDMI_VS_0, 0x00}, - {EP92_OTHER_PACKETS_HDMI_VS_1, 0x00}, - {EP92_OTHER_PACKETS_ACP_PACKET, 0x00}, - {EP92_OTHER_PACKETS_AVI_INFO_FRAME_0, 0x00}, - {EP92_OTHER_PACKETS_AVI_INFO_FRAME_1, 0x00}, - {EP92_OTHER_PACKETS_AVI_INFO_FRAME_2, 0x00}, - {EP92_OTHER_PACKETS_AVI_INFO_FRAME_3, 0x00}, - {EP92_OTHER_PACKETS_AVI_INFO_FRAME_4, 0x00}, - {EP92_OTHER_PACKETS_GC_PACKET_0, 0x00}, - {EP92_OTHER_PACKETS_GC_PACKET_1, 0x00}, - {EP92_OTHER_PACKETS_GC_PACKET_2, 0x00}, -}; - - /* shift/masks for register bits * GI = General Info * GC = General Control @@ -211,4 +154,6 @@ enum { EP92_KCTL_MAX }; +int ep92_set_ext_mclk(struct snd_soc_codec *codec, uint32_t mclk_freq); + #endif /* __EP92_H__ */ diff --git a/techpack/audio/asoc/codecs/msm_hdmi_codec_rx.c b/techpack/audio/asoc/codecs/msm_hdmi_codec_rx.c old mode 100644 new mode 100755 index 609dd45ea3188b766bd69a6b631d3184ee5d548b..f75e9e9e6d99c137934426da1161079a84b964e2 --- a/techpack/audio/asoc/codecs/msm_hdmi_codec_rx.c +++ b/techpack/audio/asoc/codecs/msm_hdmi_codec_rx.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include #include @@ -222,9 +222,9 @@ static int msm_ext_disp_audio_type_get(struct snd_kcontrol *kcontrol, rc = msm_ext_disp_select_audio_codec(codec_data->ext_disp_core_pdev, &codec_info); - if (!codec_data->ext_disp_ops.get_audio_edid_blk || + if (!codec_data->ext_disp_ops.cable_status || !codec_data->ext_disp_ops.get_intf_id || rc) { - dev_err(component->dev, "%s: get_audio_edid_blk() or get_intf_id is NULL\n", + dev_err(component->dev, "%s: cable_status() or get_intf_id is NULL\n", __func__); rc = -EINVAL; goto cable_err; @@ -735,6 +735,10 @@ static int msm_ext_disp_audio_codec_rx_probe( { struct msm_ext_disp_audio_codec_rx_data *codec_data; struct device_node *of_node_parent = NULL; + struct msm_ext_disp_codec_id codec_info; + int dai_id = DP_DAI1; + int type; + int rc = 0; codec_data = kzalloc(sizeof(struct msm_ext_disp_audio_codec_rx_data), GFP_KERNEL); @@ -775,6 +779,31 @@ static int msm_ext_disp_audio_codec_rx_probe( dev_dbg(component->dev, "%s(): registered %s with ext disp core\n", __func__, component->name); + mutex_lock(&codec_data->dp_ops_lock); + + /*Find a connected ext device to notify DisPlay*/ + for (dai_id = DP_DAI1; dai_id < DP_DAI_MAX; dai_id++) + { + if (dai_id == HDMI_MS_DAI) + type = EXT_DISPLAY_TYPE_HDMI; + else + type = EXT_DISPLAY_TYPE_DP; + + SWITCH_DP_CODEC(codec_info, codec_data, dai_id, type); + + rc = msm_ext_disp_select_audio_codec(codec_data->ext_disp_core_pdev, + &codec_info); + if (!rc) { + if(codec_data->ext_disp_ops.ready) { + rc = codec_data->ext_disp_ops.ready(codec_data->ext_disp_core_pdev); + if(!rc) + break; + } + } + } + + mutex_unlock(&codec_data->dp_ops_lock); + return 0; } diff --git a/techpack/audio/asoc/codecs/msm_sdw/Kbuild b/techpack/audio/asoc/codecs/msm_sdw/Kbuild index ccd515d085eb85273e8af97bd62fcdfd3ae8540a..c23ed2aa543ab5891d2b5e43bc404b9484088567 100644 --- a/techpack/audio/asoc/codecs/msm_sdw/Kbuild +++ b/techpack/audio/asoc/codecs/msm_sdw/Kbuild @@ -20,6 +20,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: @@ -104,6 +119,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_SND_SOC_MSM_SDW) += msm_sdw_dlkm.o msm_sdw_dlkm-y := $(MSM_SDW_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/msm_sdw/msm_sdw_cdc.c b/techpack/audio/asoc/codecs/msm_sdw/msm_sdw_cdc.c index 2b39e35c2ce56ce1e867d2ab29c50bbed6735675..917778240d437b6bd997e4e3853cb82c10800746 100644 --- a/techpack/audio/asoc/codecs/msm_sdw/msm_sdw_cdc.c +++ b/techpack/audio/asoc/codecs/msm_sdw/msm_sdw_cdc.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2016-2018, 2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2018, 2020-2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1811,7 +1811,9 @@ static int msm_sdw_notifier_service_cb(struct notifier_block *nb, initial_boot = false; break; } + mutex_lock(&msm_sdw->cdc_int_mclk1_mutex); msm_sdw->int_mclk1_enabled = false; + mutex_unlock(&msm_sdw->cdc_int_mclk1_mutex); msm_sdw->dev_up = false; for (i = 0; i < msm_sdw->nr; i++) swrm_wcd_notify(msm_sdw->sdw_ctrl_data[i].sdw_pdev, @@ -2002,7 +2004,8 @@ static int msm_sdw_probe(struct platform_device *pdev) int adsp_state; adsp_state = apr_get_subsys_state(); - if (adsp_state != APR_SUBSYS_LOADED) { + if (adsp_state != APR_SUBSYS_LOADED || + !q6core_is_adsp_ready()) { dev_err(&pdev->dev, "Adsp is not loaded yet %d\n", adsp_state); return -EPROBE_DEFER; diff --git a/techpack/audio/asoc/codecs/rouleur/Kbuild b/techpack/audio/asoc/codecs/rouleur/Kbuild index b59bcb1194efa1a529ad9c7f69adfd4509589507..97965788b5e689595b5115cc4020ab18e3803998 100644 --- a/techpack/audio/asoc/codecs/rouleur/Kbuild +++ b/techpack/audio/asoc/codecs/rouleur/Kbuild @@ -115,6 +115,3 @@ rouleur_slave_dlkm-y := $(ROULEUR_SLAVE_OBJS) obj-$(CONFIG_PM2250_SPMI) += pm2250_spmi_dlkm.o pm2250_spmi_dlkm-y := $(PM2250_SPMI_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/rouleur/rouleur-mbhc.c b/techpack/audio/asoc/codecs/rouleur/rouleur-mbhc.c index c7ba03cd2b1aad94bd8cb3563f2fcdd42e8f6924..db0f23b8465d2388c8fbcf124c79202d9843d34c 100644 --- a/techpack/audio/asoc/codecs/rouleur/rouleur-mbhc.c +++ b/techpack/audio/asoc/codecs/rouleur/rouleur-mbhc.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -36,6 +37,8 @@ #define ROULEUR_HPHL_CROSS_CONN_THRESHOLD 350 #define ROULEUR_HPHR_CROSS_CONN_THRESHOLD 350 +#define IMPED_NUM_RETRY 5 + static struct wcd_mbhc_register wcd_mbhc_registers[WCD_MBHC_REG_FUNC_MAX] = { WCD_MBHC_REGISTER("WCD_MBHC_L_DET_EN", @@ -457,6 +460,10 @@ static void rouleur_mbhc_get_result_params(struct rouleur_priv *rouleur, __func__, *zdet); /* Start discharge */ regmap_update_bits(rouleur->regmap, ROULEUR_ANA_MBHC_ZDET, 0x20, 0x00); + /* Discharge operation takes time for the HPH PA to ramp down to 0V. + * Add finite amunt of delay to complete ramp down. + */ + usleep_range(40000, 40010); } static void rouleur_mbhc_zdet_start(struct snd_soc_component *component, @@ -471,9 +478,6 @@ static void rouleur_mbhc_zdet_start(struct snd_soc_component *component, /* HPHL pull down switch to force OFF */ regmap_update_bits(rouleur->regmap, ROULEUR_ANA_HPHPA_CNP_CTL_2, 0x30, 0x00); - /* Averaging enable for reliable results */ - regmap_update_bits(rouleur->regmap, - ROULEUR_ANA_MBHC_ZDET_ANA_CTL, 0x80, 0x80); /* ZDET left measurement enable */ regmap_update_bits(rouleur->regmap, ROULEUR_ANA_MBHC_ZDET, 0x80, 0x80); @@ -482,8 +486,6 @@ static void rouleur_mbhc_zdet_start(struct snd_soc_component *component, regmap_update_bits(rouleur->regmap, ROULEUR_ANA_MBHC_ZDET, 0x80, 0x00); - regmap_update_bits(rouleur->regmap, - ROULEUR_ANA_MBHC_ZDET_ANA_CTL, 0x80, 0x00); regmap_update_bits(rouleur->regmap, ROULEUR_ANA_HPHPA_CNP_CTL_2, 0x30, 0x20); @@ -495,9 +497,6 @@ static void rouleur_mbhc_zdet_start(struct snd_soc_component *component, /* HPHR pull down switch to force OFF */ regmap_update_bits(rouleur->regmap, ROULEUR_ANA_HPHPA_CNP_CTL_2, 0x0C, 0x00); - /* Averaging enable for reliable results */ - regmap_update_bits(rouleur->regmap, - ROULEUR_ANA_MBHC_ZDET_ANA_CTL, 0x80, 0x80); /* ZDET right measurement enable */ regmap_update_bits(rouleur->regmap, ROULEUR_ANA_MBHC_ZDET, 0x40, 0x40); @@ -507,14 +506,58 @@ static void rouleur_mbhc_zdet_start(struct snd_soc_component *component, regmap_update_bits(rouleur->regmap, ROULEUR_ANA_MBHC_ZDET, 0x40, 0x00); - regmap_update_bits(rouleur->regmap, - ROULEUR_ANA_MBHC_ZDET_ANA_CTL, 0x80, 0x00); regmap_update_bits(rouleur->regmap, ROULEUR_ANA_HPHPA_CNP_CTL_2, 0x0C, 0x08); *zr = zdet; } +static void rouleur_mbhc_impedance_fn(struct snd_soc_component *component, + int32_t *z1L, int32_t *z1R, + int32_t *zl, int32_t *zr) +{ + int i; + bool is_zl_calculted = false; + bool is_zr_calculted = false; + + /* + * Calculate impedance for multiple times until IMPED_NUM_RETRY + * stop calculating if the result is within the threshold + */ + for (i = 0; i < IMPED_NUM_RETRY; i++) { + if (!is_zl_calculted) { + /* Start of left ch impedance calculation */ + rouleur_mbhc_zdet_start(component, z1L, NULL); + if ((*z1L == ROULEUR_ZDET_FLOATING_IMPEDANCE) || + (*z1L > ROULEUR_ZDET_VAL_100K)) + *zl = ROULEUR_ZDET_FLOATING_IMPEDANCE; + else { + *zl = *z1L/1000; + is_zl_calculted = true; + } + } + if (!is_zr_calculted) { + /* Start of right ch impedance calculation */ + rouleur_mbhc_zdet_start(component, NULL, z1R); + if ((*z1R == ROULEUR_ZDET_FLOATING_IMPEDANCE) || + (*z1R > ROULEUR_ZDET_VAL_100K)) + *zr = ROULEUR_ZDET_FLOATING_IMPEDANCE; + else { + *zr = *z1R/1000; + is_zr_calculted = true; + } + } + + if (is_zl_calculted && is_zr_calculted) + break; + } + + dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", + __func__, *zl); + dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", + __func__, *zr); +} + static void rouleur_wcd_mbhc_calc_impedance(struct wcd_mbhc *mbhc, uint32_t *zl, uint32_t *zr) { @@ -564,27 +607,15 @@ static void rouleur_wcd_mbhc_calc_impedance(struct wcd_mbhc *mbhc, uint32_t *zl, /* 1ms delay needed after disable surge protection */ usleep_range(1000, 1010); - /* Start of left ch impedance calculation */ - rouleur_mbhc_zdet_start(component, &z1L, NULL); - if ((z1L == ROULEUR_ZDET_FLOATING_IMPEDANCE) || - (z1L > ROULEUR_ZDET_VAL_100K)) - *zl = ROULEUR_ZDET_FLOATING_IMPEDANCE; - else - *zl = z1L/1000; - - dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", - __func__, *zl); + /* Averaging enable for reliable impedance results */ + regmap_update_bits(rouleur->regmap, + ROULEUR_ANA_MBHC_ZDET_ANA_CTL, 0x80, 0x80); - /* Start of right ch impedance calculation */ - rouleur_mbhc_zdet_start(component, NULL, &z1R); - if ((z1R == ROULEUR_ZDET_FLOATING_IMPEDANCE) || - (z1R > ROULEUR_ZDET_VAL_100K)) - *zr = ROULEUR_ZDET_FLOATING_IMPEDANCE; - else - *zr = z1R/1000; + rouleur_mbhc_impedance_fn(component, &z1L, &z1R, zl, zr); - dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", - __func__, *zr); + /* Disable averaging after impedance calculation */ + regmap_update_bits(rouleur->regmap, + ROULEUR_ANA_MBHC_ZDET_ANA_CTL, 0x80, 0x00); /* Mono/stereo detection */ if ((*zl == ROULEUR_ZDET_FLOATING_IMPEDANCE) && diff --git a/techpack/audio/asoc/codecs/rouleur/rouleur_slave.c b/techpack/audio/asoc/codecs/rouleur/rouleur_slave.c index 8fac8a6fbf25236b61902a333d5b9b632e01f008..5ea4fe4522e6f99fa8a803f3fa7809c00d343687 100644 --- a/techpack/audio/asoc/codecs/rouleur/rouleur_slave.c +++ b/techpack/audio/asoc/codecs/rouleur/rouleur_slave.c @@ -11,15 +11,276 @@ #include #include +#ifdef CONFIG_DEBUG_FS +#include +#include + +#define SWR_SLV_MAX_REG_ADDR 0x2009 +#define SWR_SLV_START_REG_ADDR 0x40 +#define SWR_SLV_MAX_BUF_LEN 20 +#define BYTES_PER_LINE 12 +#define SWR_SLV_RD_BUF_LEN 8 +#define SWR_SLV_WR_BUF_LEN 32 +#define SWR_SLV_MAX_DEVICES 2 +#endif /* CONFIG_DEBUG_FS */ + struct rouleur_slave_priv { struct swr_device *swr_slave; +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_rouleur_dent; + struct dentry *debugfs_peek; + struct dentry *debugfs_poke; + struct dentry *debugfs_reg_dump; + unsigned int read_data; +#endif +}; + +#ifdef CONFIG_DEBUG_FS +static int codec_debug_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static int get_parameters(char *buf, u32 *param1, int num_of_par) +{ + char *token = NULL; + int base = 0, cnt = 0; + + token = strsep(&buf, " "); + for (cnt = 0; cnt < num_of_par; cnt++) { + if (token) { + if ((token[1] == 'x') || (token[1] == 'X')) + base = 16; + else + base = 10; + + if (kstrtou32(token, base, ¶m1[cnt]) != 0) + return -EINVAL; + + token = strsep(&buf, " "); + } else { + return -EINVAL; + } + } + return 0; +} + +static bool is_swr_slv_reg_readable(int reg) +{ + int ret = true; + + if (((reg > 0x46) && (reg < 0x4A)) || + ((reg > 0x4A) && (reg < 0x50)) || + ((reg > 0x55) && (reg < 0xD0)) || + ((reg > 0xD0) && (reg < 0xE0)) || + ((reg > 0xE0) && (reg < 0xF0)) || + ((reg > 0xF0) && (reg < 0x100)) || + ((reg > 0x105) && (reg < 0x120)) || + ((reg > 0x205) && (reg < 0x220)) || + ((reg > 0x305) && (reg < 0x320)) || + ((reg > 0x405) && (reg < 0x420)) || + ((reg > 0x128) && (reg < 0x130)) || + ((reg > 0x228) && (reg < 0x230)) || + ((reg > 0x328) && (reg < 0x330)) || + ((reg > 0x428) && (reg < 0x430)) || + ((reg > 0x138) && (reg < 0x205)) || + ((reg > 0x238) && (reg < 0x305)) || + ((reg > 0x338) && (reg < 0x405)) || + ((reg > 0x405) && (reg < 0xF00)) || + ((reg > 0xF05) && (reg < 0xF20)) || + ((reg > 0xF25) && (reg < 0xF30)) || + ((reg > 0xF35) && (reg < 0x2000))) + ret = false; + + return ret; +} + +static ssize_t rouleur_swrslave_reg_show(struct swr_device *pdev, + char __user *ubuf, + size_t count, loff_t *ppos) +{ + int i, reg_val, len; + ssize_t total = 0; + char tmp_buf[SWR_SLV_MAX_BUF_LEN]; + + if (!ubuf || !ppos) + return 0; + + for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR); + i <= SWR_SLV_MAX_REG_ADDR; i++) { + if (!is_swr_slv_reg_readable(i)) + continue; + swr_read(pdev, pdev->dev_num, i, ®_val, 1); + len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i, + (reg_val & 0xFF)); + if (len < 0) { + pr_err("%s: fail to fill the buffer\n", __func__); + total = -EFAULT; + goto copy_err; + } + if (((total + len) >= count - 1) || (len < 0)) + break; + if (copy_to_user((ubuf + total), tmp_buf, len)) { + pr_err("%s: fail to copy reg dump\n", __func__); + total = -EFAULT; + goto copy_err; + } + total += len; + *ppos += len; + } + +copy_err: + *ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE; + return total; +} + +static ssize_t codec_debug_dump(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct swr_device *pdev; + + if (!count || !file || !ppos || !ubuf) + return -EINVAL; + + pdev = file->private_data; + if (!pdev) + return -EINVAL; + + if (*ppos < 0) + return -EINVAL; + + return rouleur_swrslave_reg_show(pdev, ubuf, count, ppos); +} + +static ssize_t codec_debug_read(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char lbuf[SWR_SLV_RD_BUF_LEN]; + struct swr_device *pdev = NULL; + struct rouleur_slave_priv *rouleur_slave = NULL; + + if (!count || !file || !ppos || !ubuf) + return -EINVAL; + + pdev = file->private_data; + if (!pdev) + return -EINVAL; + + rouleur_slave = swr_get_dev_data(pdev); + if (!rouleur_slave) + return -EINVAL; + + if (*ppos < 0) + return -EINVAL; + + snprintf(lbuf, sizeof(lbuf), "0x%x\n", + (rouleur_slave->read_data & 0xFF)); + + return simple_read_from_buffer(ubuf, count, ppos, lbuf, + strnlen(lbuf, 7)); +} + +static ssize_t codec_debug_peek_write(struct file *file, + const char __user *ubuf, size_t cnt, loff_t *ppos) +{ + char lbuf[SWR_SLV_WR_BUF_LEN]; + int rc = 0; + u32 param[5]; + struct swr_device *pdev = NULL; + struct rouleur_slave_priv *rouleur_slave = NULL; + + if (!cnt || !file || !ppos || !ubuf) + return -EINVAL; + + pdev = file->private_data; + if (!pdev) + return -EINVAL; + + rouleur_slave = swr_get_dev_data(pdev); + if (!rouleur_slave) + return -EINVAL; + + if (*ppos < 0) + return -EINVAL; + + if (cnt > sizeof(lbuf) - 1) + return -EINVAL; + + rc = copy_from_user(lbuf, ubuf, cnt); + if (rc) + return -EFAULT; + + lbuf[cnt] = '\0'; + rc = get_parameters(lbuf, param, 1); + if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0))) + return -EINVAL; + swr_read(pdev, pdev->dev_num, param[0], &rouleur_slave->read_data, 1); + if (rc == 0) + rc = cnt; + else + pr_err("%s: rc = %d\n", __func__, rc); + + return rc; +} + +static ssize_t codec_debug_write(struct file *file, + const char __user *ubuf, size_t cnt, loff_t *ppos) +{ + char lbuf[SWR_SLV_WR_BUF_LEN]; + int rc = 0; + u32 param[5]; + struct swr_device *pdev; + + if (!file || !ppos || !ubuf) + return -EINVAL; + + pdev = file->private_data; + if (!pdev) + return -EINVAL; + + if (cnt > sizeof(lbuf) - 1) + return -EINVAL; + + rc = copy_from_user(lbuf, ubuf, cnt); + if (rc) + return -EFAULT; + + lbuf[cnt] = '\0'; + rc = get_parameters(lbuf, param, 2); + if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && + (param[1] <= 0xFF) && (rc == 0))) + return -EINVAL; + swr_write(pdev, pdev->dev_num, param[0], ¶m[1]); + if (rc == 0) + rc = cnt; + else + pr_err("%s: rc = %d\n", __func__, rc); + + return rc; +} + +static const struct file_operations codec_debug_write_ops = { + .open = codec_debug_open, + .write = codec_debug_write, }; +static const struct file_operations codec_debug_read_ops = { + .open = codec_debug_open, + .read = codec_debug_read, + .write = codec_debug_peek_write, +}; + +static const struct file_operations codec_debug_dump_ops = { + .open = codec_debug_open, + .read = codec_debug_dump, +}; +#endif + static int rouleur_slave_bind(struct device *dev, struct device *master, void *data) { int ret = 0; - struct rouleur_slave_priv *rouleur_slave = NULL; uint8_t devnum = 0; struct swr_device *pdev = to_swr_device(dev); @@ -28,15 +289,6 @@ static int rouleur_slave_bind(struct device *dev, return -EINVAL; } - rouleur_slave = devm_kzalloc(&pdev->dev, - sizeof(struct rouleur_slave_priv), GFP_KERNEL); - if (!rouleur_slave) - return -ENOMEM; - - swr_set_dev_data(pdev, rouleur_slave); - - rouleur_slave->swr_slave = pdev; - ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum); if (ret) { dev_dbg(&pdev->dev, @@ -67,7 +319,6 @@ static void rouleur_slave_unbind(struct device *dev, return; } - swr_set_dev_data(pdev, NULL); } static const struct swr_device_id rouleur_swr_id[] = { @@ -104,12 +355,61 @@ static int rouleur_swr_reset(struct swr_device *pdev) static int rouleur_swr_probe(struct swr_device *pdev) { + struct rouleur_slave_priv *rouleur_slave = NULL; + + rouleur_slave = devm_kzalloc(&pdev->dev, + sizeof(struct rouleur_slave_priv), GFP_KERNEL); + if (!rouleur_slave) + return -ENOMEM; + + swr_set_dev_data(pdev, rouleur_slave); + + rouleur_slave->swr_slave = pdev; +#ifdef CONFIG_DEBUG_FS + if (!rouleur_slave->debugfs_rouleur_dent) { + rouleur_slave->debugfs_rouleur_dent = debugfs_create_dir( + dev_name(&pdev->dev), 0); + if (!IS_ERR(rouleur_slave->debugfs_rouleur_dent)) { + rouleur_slave->debugfs_peek = + debugfs_create_file("swrslave_peek", + S_IFREG | 0444, + rouleur_slave->debugfs_rouleur_dent, + (void *) pdev, + &codec_debug_read_ops); + + rouleur_slave->debugfs_poke = + debugfs_create_file("swrslave_poke", + S_IFREG | 0444, + rouleur_slave->debugfs_rouleur_dent, + (void *) pdev, + &codec_debug_write_ops); + + rouleur_slave->debugfs_reg_dump = + debugfs_create_file( + "swrslave_reg_dump", + S_IFREG | 0444, + rouleur_slave->debugfs_rouleur_dent, + (void *) pdev, + &codec_debug_dump_ops); + } + } +#endif return component_add(&pdev->dev, &rouleur_slave_comp_ops); } static int rouleur_swr_remove(struct swr_device *pdev) { +#ifdef CONFIG_DEBUG_FS + struct rouleur_slave_priv *rouleur_slave = swr_get_dev_data(pdev); + + if (rouleur_slave) { + debugfs_remove_recursive(rouleur_slave->debugfs_rouleur_dent); + rouleur_slave->debugfs_rouleur_dent = NULL; + } +#endif component_del(&pdev->dev, &rouleur_slave_comp_ops); + swr_set_dev_data(pdev, NULL); + swr_remove_device(pdev); return 0; } @@ -140,5 +440,5 @@ static void __exit rouleur_slave_exit(void) module_init(rouleur_slave_init); module_exit(rouleur_slave_exit); -MODULE_DESCRIPTION("WCD937X Swr Slave driver"); +MODULE_DESCRIPTION("Rouleur Swr Slave driver"); MODULE_LICENSE("GPL v2"); diff --git a/techpack/audio/asoc/codecs/sdm660_cdc/Android.mk b/techpack/audio/asoc/codecs/sdm660_cdc/Android.mk index ced40f4b3a8b9626df1a58599b4188b8e8425478..739ddfa5fc4430a96a2b13452cd9182a7af395a5 100644 --- a/techpack/audio/asoc/codecs/sdm660_cdc/Android.mk +++ b/techpack/audio/asoc/codecs/sdm660_cdc/Android.mk @@ -4,7 +4,7 @@ AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list, sdm660),true) +ifeq ($(call is-board-platform-in-list, sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) diff --git a/techpack/audio/asoc/codecs/sdm660_cdc/Kbuild b/techpack/audio/asoc/codecs/sdm660_cdc/Kbuild index c6cf4b705617395646ce6b29e8603c80b9e2c12f..45d983038dc186f4b88f54aac9550c7546e015c4 100644 --- a/techpack/audio/asoc/codecs/sdm660_cdc/Kbuild +++ b/techpack/audio/asoc/codecs/sdm660_cdc/Kbuild @@ -20,6 +20,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: @@ -58,6 +73,10 @@ ifdef CONFIG_SND_SOC_DIGITAL_CDC DIGITAL_CDC_OBJS += msm-digital-cdc.o DIGITAL_CDC_OBJS += msm-digital-cdc-regmap.o endif +ifdef CONFIG_SND_SOC_DIGITAL_CDC_LEGACY + DIGITAL_CDC_OBJS += msm-digital-cdc-legacy.o + DIGITAL_CDC_OBJS += msm-digital-cdc-legacy-regmap.o +endif LINUX_INC += -Iinclude/linux INCS += $(COMMON_INC) \ @@ -111,5 +130,5 @@ analog_cdc_dlkm-y := $(ANALOG_CDC_OBJS) obj-$(CONFIG_SND_SOC_DIGITAL_CDC) += digital_cdc_dlkm.o digital_cdc_dlkm-y := $(DIGITAL_CDC_OBJS) -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" +obj-$(CONFIG_SND_SOC_DIGITAL_CDC_LEGACY) += digital_cdc_dlkm.o +digital_cdc_dlkm-y := $(DIGITAL_CDC_OBJS) diff --git a/techpack/audio/asoc/codecs/sdm660_cdc/msm-analog-cdc.c b/techpack/audio/asoc/codecs/sdm660_cdc/msm-analog-cdc.c index 4caed82a22362b832c9ef324a83539b504f1e473..51e80868fdf41f036b89d92e4e1841bedc618ce7 100644 --- a/techpack/audio/asoc/codecs/sdm660_cdc/msm-analog-cdc.c +++ b/techpack/audio/asoc/codecs/sdm660_cdc/msm-analog-cdc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2018, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2018, 2020-2021, The Linux Foundation. All rights reserved. */ #include #include @@ -3931,13 +3931,15 @@ static int sdm660_cdc_notifier_service_cb(struct notifier_block *nb, bool timedout; unsigned long timeout; static bool initial_boot = true; + struct audio_notifier_cb_data *cb_data = ptr; component = sdm660_cdc_priv->component; dev_dbg(component->dev, "%s: Service opcode 0x%lx\n", __func__, opcode); switch (opcode) { case AUDIO_NOTIFIER_SERVICE_DOWN: - if (initial_boot) { + if (initial_boot && + cb_data->service == AUDIO_NOTIFIER_PDR_SERVICE) { initial_boot = false; break; } @@ -3946,7 +3948,8 @@ static int sdm660_cdc_notifier_service_cb(struct notifier_block *nb, msm_anlg_cdc_device_down(component); break; case AUDIO_NOTIFIER_SERVICE_UP: - if (initial_boot) + if (initial_boot && + cb_data->service == AUDIO_NOTIFIER_PDR_SERVICE) initial_boot = false; dev_dbg(component->dev, "ADSP is about to power up. bring up codec\n"); @@ -4653,7 +4656,8 @@ static int msm_anlg_cdc_probe(struct platform_device *pdev) int adsp_state; adsp_state = apr_get_subsys_state(); - if (adsp_state != APR_SUBSYS_LOADED) { + if (adsp_state != APR_SUBSYS_LOADED || + !q6core_is_adsp_ready()) { dev_err(&pdev->dev, "Adsp is not loaded yet %d\n", adsp_state); return -EPROBE_DEFER; diff --git a/techpack/audio/asoc/codecs/sdm660_cdc/msm-analog-cdc.h b/techpack/audio/asoc/codecs/sdm660_cdc/msm-analog-cdc.h index dbeb76706e3172b124965cff35350fc7d8bffbcd..2f3c8e17fe935d231bd7fc3869f642132bee6114 100644 --- a/techpack/audio/asoc/codecs/sdm660_cdc/msm-analog-cdc.h +++ b/techpack/audio/asoc/codecs/sdm660_cdc/msm-analog-cdc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2015-2018, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2018, 2020-2021, The Linux Foundation. All rights reserved. */ #ifndef MSM_ANALOG_CDC_H #define MSM_ANALOG_CDC_H @@ -227,7 +227,7 @@ extern int msm_anlg_cdc_mclk_enable(struct snd_soc_component *component, extern int msm_anlg_cdc_hs_detect(struct snd_soc_component *component, struct wcd_mbhc_config *mbhc_cfg); extern void msm_anlg_cdc_hs_detect_exit(struct snd_soc_component *component); -extern void sdm660_cdc_update_int_spk_boost(bool enable); +extern void msm_anlg_cdc_update_int_spk_boost(bool enable); extern void msm_anlg_cdc_spk_ext_pa_cb( int (*codec_spk_ext_pa)(struct snd_soc_component *component, int enable), struct snd_soc_component *component); @@ -249,7 +249,7 @@ static inline void msm_anlg_cdc_hs_detect_exit( { } -static inline void sdm660_cdc_update_int_spk_boost(bool enable) +static inline void msm_anlg_cdc_update_int_spk_boost(bool enable) { } diff --git a/techpack/audio/asoc/codecs/sdm660_cdc/msm-cdc-common.h b/techpack/audio/asoc/codecs/sdm660_cdc/msm-cdc-common.h index ca66de9821f0050c1063aba46248b56aea2f8b7e..6f57af4427ef87ed4a48efc67484df33921fab07 100644 --- a/techpack/audio/asoc/codecs/sdm660_cdc/msm-cdc-common.h +++ b/techpack/audio/asoc/codecs/sdm660_cdc/msm-cdc-common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2016-2017, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017, 2020-2021, The Linux Foundation. All rights reserved. */ #include @@ -56,5 +56,6 @@ enum dig_cdc_notify_event { DIG_CDC_EVENT_POST_RX2_INT_OFF, DIG_CDC_EVENT_SSR_DOWN, DIG_CDC_EVENT_SSR_UP, + DIG_CDC_EVENT_CAP_CONFIGURE, DIG_CDC_EVENT_LAST, }; diff --git a/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy-regmap.c b/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy-regmap.c new file mode 100644 index 0000000000000000000000000000000000000000..2a3fd873a1311094f3a001d1cc53ff3e955e1f03 --- /dev/null +++ b/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy-regmap.c @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2015-2018, 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include "msm-cdc-common.h" +#include "sdm660-cdc-registers.h" + +/* + * Default register reset values that are common across different versions + * are defined here. If a register reset value is changed based on version + * then remove it from this structure and add it in version specific + * structures. + */ +struct reg_default + msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE] = { + {MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x13}, + {MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 0x13}, + {MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_OTHR_CTL, 0x04}, + {MSM89XX_CDC_CORE_CLK_RX_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_SD_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B5_CTL, 0x68}, + {MSM89XX_CDC_CORE_RX2_B5_CTL, 0x68}, + {MSM89XX_CDC_CORE_RX3_B5_CTL, 0x68}, + {MSM89XX_CDC_CORE_RX1_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_TOP_GAIN_UPDATE, 0x00}, + {MSM89XX_CDC_CORE_TOP_CTL, 0x01}, + {MSM89XX_CDC_CORE_COMP0_B1_CTL, 0x30}, + {MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xB5}, + {MSM89XX_CDC_CORE_COMP0_B3_CTL, 0x28}, + {MSM89XX_CDC_CORE_COMP0_B4_CTL, 0x37}, + {MSM89XX_CDC_CORE_COMP0_B5_CTL, 0x7F}, + {MSM89XX_CDC_CORE_COMP0_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS, 0x03}, + {MSM89XX_CDC_CORE_COMP0_FS_CFG, 0x03}, + {MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL, 0x02}, + {MSM89XX_CDC_CORE_DEBUG_DESER1_CTL, 0x00}, + {MSM89XX_CDC_CORE_DEBUG_DESER2_CTL, 0x00}, + {MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_CTL, 0x40}, + {MSM89XX_CDC_CORE_IIR2_CTL, 0x40}, + {MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX2_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX3_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_TX_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_TX_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER, 0x00}, + {MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER, 0x00}, + {MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER, 0x00}, + {MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER, 0x00}, + {MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, 0x00}, + {MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, 0x00}, + {MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, 0x00}, + {MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, 0x00}, + {MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_TX1_MUX_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX2_MUX_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX3_MUX_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX4_MUX_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX1_CLK_FS_CTL, 0x03}, + {MSM89XX_CDC_CORE_TX2_CLK_FS_CTL, 0x03}, + {MSM89XX_CDC_CORE_TX3_CLK_FS_CTL, 0x03}, + {MSM89XX_CDC_CORE_TX4_CLK_FS_CTL, 0x03}, + {MSM89XX_CDC_CORE_TX1_DMIC_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX2_DMIC_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX3_DMIC_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX4_DMIC_CTL, 0x00}, +}; + +static const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE] = { + [MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_SD_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1, + [MSM89XX_CDC_CORE_TOP_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B1_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B2_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B3_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B4_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B5_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B6_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS] = 1, + [MSM89XX_CDC_CORE_COMP0_FS_CFG] = 1, + [MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1, +}; + +static const u8 msm89xx_cdc_core_reg_writeable[MSM89XX_CDC_CORE_CACHE_SIZE] = { + [MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_SD_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1, + [MSM89XX_CDC_CORE_TOP_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B1_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B2_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B3_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B4_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B5_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B6_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_FS_CFG] = 1, + [MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1, +}; + +bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg) +{ + return msm89xx_cdc_core_reg_readable[reg]; +} + +bool msm89xx_cdc_core_writeable_reg(struct device *dev, unsigned int reg) +{ + return msm89xx_cdc_core_reg_writeable[reg]; +} + +bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MSM89XX_CDC_CORE_RX1_B1_CTL: + case MSM89XX_CDC_CORE_RX2_B1_CTL: + case MSM89XX_CDC_CORE_RX3_B1_CTL: + case MSM89XX_CDC_CORE_RX1_B6_CTL: + case MSM89XX_CDC_CORE_RX2_B6_CTL: + case MSM89XX_CDC_CORE_RX3_B6_CTL: + case MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG: + case MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG: + case MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG: + case MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG: + case MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL: + case MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL: + case MSM89XX_CDC_CORE_CLK_MCLK_CTL: + case MSM89XX_CDC_CORE_CLK_PDM_CTL: + return true; + default: + return false; + } +} diff --git a/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy.c b/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy.c new file mode 100644 index 0000000000000000000000000000000000000000..03feb888e1d9d191349ebb03b58662ef07d7820f --- /dev/null +++ b/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy.c @@ -0,0 +1,2640 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sdm660-cdc-registers.h" +#include "msm-digital-cdc.h" +#include "msm-cdc-common.h" +#include "../../msm8952.h" + +#define DRV_NAME "msm_digital_codec" +#define MCLK_RATE_9P6MHZ 9600000 +#define MCLK_RATE_12P288MHZ 12288000 +#define TX_MUX_CTL_CUT_OFF_FREQ_MASK 0x30 +#define CF_MIN_3DB_4HZ 0x0 +#define CF_MIN_3DB_75HZ 0x1 +#define CF_MIN_3DB_150HZ 0x2 + +#define MSM_DIG_CDC_VERSION_ENTRY_SIZE 32 +#define MAX_ON_DEMAND_DIG_SUPPLY_NAME_LENGTH 64 +#define CODEC_DT_MAX_PROP_SIZE 40 + +/* + * 200 Milliseconds sufficient for DSP bring up in the lpass + * after Sub System Restart + */ +#define ADSP_STATE_READY_TIMEOUT_MS 200 + +static unsigned long rx_digital_gain_reg[] = { + MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, + MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, + MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, +}; + +static unsigned long tx_digital_gain_reg[] = { + MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, + MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, + MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, + MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, +}; + +#define SDM660_TX_UNMUTE_DELAY_MS 40 +static int tx_unmute_delay = SDM660_TX_UNMUTE_DELAY_MS; +module_param(tx_unmute_delay, int, 0664); +MODULE_PARM_DESC(tx_unmute_delay, "delay to unmute the tx path"); + +static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0); + +struct snd_soc_component *registered_digcodec; +struct hpf_work tx_hpf_work[NUM_DECIMATORS]; + +static int msm_dig_cdc_enable_on_demand_supply( + struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +static char on_demand_supply_name[][MAX_ON_DEMAND_DIG_SUPPLY_NAME_LENGTH] = { + "cdc-vdd-digital", +}; +/* Codec supports 2 IIR filters */ +enum { + IIR1 = 0, + IIR2, + IIR_MAX, +}; + +/* + * msm_digcdc_mclk_enable - add mclk support in digital codec + * @codec: codec instance + * @mclk_enable: mclk enable/disable + * @dapm: check for dapm widget + */ +int msm_digcdc_mclk_enable(struct snd_soc_component *component, + int mclk_enable, bool dapm) +{ + dev_dbg(component->dev, "%s: mclk_enable = %u, dapm = %d\n", + __func__, mclk_enable, dapm); + if (mclk_enable) { + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x01); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TOP_CTL, 0x01, 0x01); + } else { + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TOP_CTL, 0x01, 0x00); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x00); + } + + return 0; +} +EXPORT_SYMBOL(msm_digcdc_mclk_enable); + +static int msm_digcdc_clock_control(bool flag) +{ + int ret = -EINVAL; + struct msm_asoc_mach_data *pdata = NULL; + struct msm_dig_priv *msm_dig_cdc = + snd_soc_component_get_drvdata(registered_digcodec); + + pdata = snd_soc_card_get_drvdata(registered_digcodec->card); + + if (flag) { + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if (atomic_read(&pdata->int_mclk0_enabled) == false) { + if (msm_dig_cdc->regmap->cache_only == true) + return ret; + pdata->digital_cdc_core_clk.clk_freq_in_hz = + DEFAULT_MCLK_RATE; + pdata->digital_cdc_core_clk.enable = 1; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s:failed to enable the MCLK\n", + __func__); + /* + * Avoid access to lpass register + * as clock enable failed during SSR. + */ + msm_dig_cdc->regmap->cache_only = true; + return ret; + } + pr_debug("enabled digital codec core clk\n"); + atomic_set(&pdata->int_mclk0_enabled, true); + schedule_delayed_work(&pdata->disable_int_mclk0_work, + 50); + } + } else { + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + dev_dbg(registered_digcodec->dev, + "disable MCLK, workq to disable set already\n"); + } + return 0; +} + +static void enable_digital_callback(void *flag) +{ + msm_digcdc_clock_control(true); +} + +static void disable_digital_callback(void *flag) +{ + msm_digcdc_clock_control(false); + pr_debug("disable mclk happens in workq\n"); +} + +static int msm_dig_cdc_put_dec_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol); + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int dec_mux, decimator; + char *dec_name = NULL; + char *widget_name = NULL; + char *temp; + u16 tx_mux_ctl_reg; + u8 adc_dmic_sel = 0x0; + int ret = 0; + char *dec_num; + + if (ucontrol->value.enumerated.item[0] > e->items) { + dev_err(component->dev, "%s: Invalid enum value: %d\n", + __func__, ucontrol->value.enumerated.item[0]); + return -EINVAL; + } + dec_mux = ucontrol->value.enumerated.item[0]; + + widget_name = kstrndup(w->name, 15, GFP_KERNEL); + if (!widget_name) { + dev_err(component->dev, "%s: failed to copy string\n", + __func__); + return -ENOMEM; + } + temp = widget_name; + + dec_name = strsep(&widget_name, " "); + widget_name = temp; + if (!dec_name) { + dev_err(component->dev, "%s: Invalid decimator = %s\n", + __func__, w->name); + ret = -EINVAL; + goto out; + } + + dec_num = strpbrk(dec_name, "12"); + if (dec_num == NULL) { + dev_err(component->dev, "%s: Invalid DEC selected\n", __func__); + ret = -EINVAL; + goto out; + } + + ret = kstrtouint(dec_num, 10, &decimator); + if (ret < 0) { + dev_err(component->dev, "%s: Invalid decimator = %s\n", + __func__, dec_name); + ret = -EINVAL; + goto out; + } + + dev_dbg(w->dapm->dev, "%s(): widget = %s decimator = %u dec_mux = %u\n" + , __func__, w->name, decimator, dec_mux); + + switch (decimator) { + case 1: + case 2: + if ((dec_mux == 4) || (dec_mux == 5)) + adc_dmic_sel = 0x1; + else + adc_dmic_sel = 0x0; + break; + default: + dev_err(component->dev, "%s: Invalid Decimator = %u\n", + __func__, decimator); + ret = -EINVAL; + goto out; + } + + tx_mux_ctl_reg = + MSM89XX_CDC_CORE_TX1_MUX_CTL + 32 * (decimator - 1); + + snd_soc_component_update_bits(component, tx_mux_ctl_reg, 0x1, + adc_dmic_sel); + + ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); + +out: + kfree(widget_name); + return ret; +} + + +static int msm_dig_cdc_codec_config_compander( + struct snd_soc_component *component, + int interp_n, int event) +{ + struct msm_dig_priv *dig_cdc = snd_soc_component_get_drvdata(component); + int comp_ch_bits_set = 0x03; + int comp_ch_value; + + dev_dbg(component->dev, "%s: event %d shift %d, enabled %d\n", + __func__, event, interp_n, + dig_cdc->comp_enabled[interp_n]); + + /* compander is invalid */ + if (dig_cdc->comp_enabled[interp_n] != COMPANDER_1 && + dig_cdc->comp_enabled[interp_n]) { + dev_dbg(component->dev, "%s: Invalid compander %d\n", __func__, + dig_cdc->comp_enabled[interp_n]); + return 0; + } + + if (SND_SOC_DAPM_EVENT_ON(event)) { + /* compander is not enabled */ + if (!dig_cdc->comp_enabled[interp_n]) { + dig_cdc->set_compander_mode(dig_cdc->handle, 0x00); + return 0; + }; + comp_ch_value = snd_soc_component_read32(component, + MSM89XX_CDC_CORE_COMP0_B1_CTL); + if (interp_n == 0) { + if (comp_ch_value & 0x02) { + dev_dbg(component->dev, + "%s comp ch 1 already enabled\n", + __func__); + return 0; + } + } + if (interp_n == 1) { + if (comp_ch_value & 0x01) { + dev_dbg(component->dev, + "%s comp ch 0 already enabled\n", + __func__); + return 0; + } + } + dig_cdc->set_compander_mode(dig_cdc->handle, 0x08); + /* Enable Compander Clock */ + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B2_CTL, 0x0F, 0x09); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x01, 0x01); + if (dig_cdc->comp_enabled[MSM89XX_RX1]) { + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B1_CTL, + 0x02, 0x02); + } + if (dig_cdc->comp_enabled[MSM89XX_RX2]) { + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B1_CTL, + 0x01, 0x01); + } + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B3_CTL, 0xFF, 0x01); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xF0, 0x50); + /* add sleep for compander to settle */ + usleep_range(1000, 1100); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B3_CTL, 0xFF, 0x28); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xF0, 0xB0); + + /* Enable Compander GPIO */ + if (dig_cdc->codec_hph_comp_gpio) + dig_cdc->codec_hph_comp_gpio(1, component); + } else if (SND_SOC_DAPM_EVENT_OFF(event)) { + /* Disable Compander GPIO */ + if (dig_cdc->codec_hph_comp_gpio) + dig_cdc->codec_hph_comp_gpio(0, component); + + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B1_CTL, + 1 << interp_n, 0); + comp_ch_bits_set = snd_soc_component_read32(component, + MSM89XX_CDC_CORE_COMP0_B1_CTL); + if ((comp_ch_bits_set & 0x03) == 0x00) { + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B2_CTL, 0x0F, 0x05); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x01, 0x00); + } + } + return 0; +} + +/** + * msm_dig_cdc_hph_comp_cb - registers callback to codec by machine driver. + * + * @codec_hph_comp_gpio: function pointer to set comp gpio at machine driver + * @codec: codec pointer + * + */ +void msm_dig_cdc_hph_comp_cb(int (*codec_hph_comp_gpio)(bool enable, + struct snd_soc_component *component), + struct snd_soc_component *component) +{ + struct msm_dig_priv *dig_cdc = snd_soc_component_get_drvdata(component); + + pr_debug("%s: Enter\n", __func__); + dig_cdc->codec_hph_comp_gpio = codec_hph_comp_gpio; +} +EXPORT_SYMBOL(msm_dig_cdc_hph_comp_cb); + +static int msm_dig_cdc_codec_enable_interpolator(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct msm_dig_priv *msm_dig_cdc = + snd_soc_component_get_drvdata(component); + + dev_dbg(component->dev, "%s %d %s\n", __func__, event, w->name); + + if (w->shift >= MSM89XX_RX_MAX || w->shift < 0) { + dev_err(component->dev, "%s: wrong RX index: %d\n", + __func__, w->shift); + return -EINVAL; + } + switch (event) { + case SND_SOC_DAPM_POST_PMU: + msm_dig_cdc_codec_config_compander(component, w->shift, event); + /* apply the digital gain after the interpolator is enabled*/ + if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg)) + snd_soc_component_write(component, + rx_digital_gain_reg[w->shift], + snd_soc_component_read32(component, + rx_digital_gain_reg[w->shift]) + ); + break; + case SND_SOC_DAPM_POST_PMD: + msm_dig_cdc_codec_config_compander(component, w->shift, event); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, + 1 << w->shift, 1 << w->shift); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, + 1 << w->shift, 0x0); + /* + * disable the mute enabled during the PMD of this device + */ + if ((w->shift == 0) && + (msm_dig_cdc->mute_mask & HPHL_PA_DISABLE)) { + pr_debug("disabling HPHL mute\n"); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= ~(HPHL_PA_DISABLE); + } else if ((w->shift == 1) && + (msm_dig_cdc->mute_mask & HPHR_PA_DISABLE)) { + pr_debug("disabling HPHR mute\n"); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= ~(HPHR_PA_DISABLE); + } else if ((w->shift == 2) && + (msm_dig_cdc->mute_mask & SPKR_PA_DISABLE)) { + pr_debug("disabling SPKR mute\n"); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= ~(SPKR_PA_DISABLE); + } + } + return 0; +} + +static int msm_dig_cdc_get_iir_enable_audio_mixer( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + int iir_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int band_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + + ucontrol->value.integer.value[0] = + (snd_soc_component_read32(component, + (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx)) & + (1 << band_idx)) != 0; + + dev_dbg(component->dev, "%s: IIR #%d band #%d enable %d\n", __func__, + iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_dig_cdc_put_iir_enable_audio_mixer( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + int iir_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int band_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + int value = ucontrol->value.integer.value[0]; + + /* Mask first 5 bits, 6-8 are reserved */ + snd_soc_component_update_bits(component, + (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx), + (1 << band_idx), (value << band_idx)); + + dev_dbg(component->dev, "%s: IIR #%d band #%d enable %d\n", __func__, + iir_idx, band_idx, + ((snd_soc_component_read32(component, + (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx)) & + (1 << band_idx)) != 0)); + + return 0; +} + +static uint32_t get_iir_band_coeff(struct snd_soc_component *component, + int iir_idx, int band_idx, + int coeff_idx) +{ + uint32_t value = 0; + + /* Address does not automatically update if reading */ + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + ((band_idx * BAND_MAX + coeff_idx) + * sizeof(uint32_t)) & 0x7F); + + value |= snd_soc_component_read32(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)); + + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + ((band_idx * BAND_MAX + coeff_idx) + * sizeof(uint32_t) + 1) & 0x7F); + + value |= (snd_soc_component_read32(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 8); + + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + ((band_idx * BAND_MAX + coeff_idx) + * sizeof(uint32_t) + 2) & 0x7F); + + value |= (snd_soc_component_read32(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 16); + + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + ((band_idx * BAND_MAX + coeff_idx) + * sizeof(uint32_t) + 3) & 0x7F); + + /* Mask bits top 2 bits since they are reserved */ + value |= ((snd_soc_component_read32(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)) & 0x3f) + << 24); + + return value; + +} + +static void set_iir_band_coeff(struct snd_soc_component *component, + int iir_idx, int band_idx, + uint32_t value) +{ + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), + (value & 0xFF)); + + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), + (value >> 8) & 0xFF); + + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), + (value >> 16) & 0xFF); + + /* Mask top 2 bits, 7-8 are reserved */ + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), + (value >> 24) & 0x3F); + +} + +static int msm_dig_cdc_get_iir_band_audio_mixer( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + int iir_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int band_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + + ucontrol->value.integer.value[0] = + get_iir_band_coeff(component, iir_idx, band_idx, 0); + ucontrol->value.integer.value[1] = + get_iir_band_coeff(component, iir_idx, band_idx, 1); + ucontrol->value.integer.value[2] = + get_iir_band_coeff(component, iir_idx, band_idx, 2); + ucontrol->value.integer.value[3] = + get_iir_band_coeff(component, iir_idx, band_idx, 3); + ucontrol->value.integer.value[4] = + get_iir_band_coeff(component, iir_idx, band_idx, 4); + + dev_dbg(component->dev, "%s: IIR #%d band #%d b0 = 0x%x\n" + "%s: IIR #%d band #%d b1 = 0x%x\n" + "%s: IIR #%d band #%d b2 = 0x%x\n" + "%s: IIR #%d band #%d a1 = 0x%x\n" + "%s: IIR #%d band #%d a2 = 0x%x\n", + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[0], + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[1], + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[2], + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[3], + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[4]); + return 0; +} + +static int msm_dig_cdc_put_iir_band_audio_mixer( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + int iir_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int band_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + + /* Mask top bit it is reserved */ + /* Updates addr automatically for each B2 write */ + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F); + + + set_iir_band_coeff(component, iir_idx, band_idx, + ucontrol->value.integer.value[0]); + set_iir_band_coeff(component, iir_idx, band_idx, + ucontrol->value.integer.value[1]); + set_iir_band_coeff(component, iir_idx, band_idx, + ucontrol->value.integer.value[2]); + set_iir_band_coeff(component, iir_idx, band_idx, + ucontrol->value.integer.value[3]); + set_iir_band_coeff(component, iir_idx, band_idx, + ucontrol->value.integer.value[4]); + + dev_dbg(component->dev, "%s: IIR #%d band #%d b0 = 0x%x\n" + "%s: IIR #%d band #%d b1 = 0x%x\n" + "%s: IIR #%d band #%d b2 = 0x%x\n" + "%s: IIR #%d band #%d a1 = 0x%x\n" + "%s: IIR #%d band #%d a2 = 0x%x\n", + __func__, iir_idx, band_idx, + get_iir_band_coeff(component, iir_idx, band_idx, 0), + __func__, iir_idx, band_idx, + get_iir_band_coeff(component, iir_idx, band_idx, 1), + __func__, iir_idx, band_idx, + get_iir_band_coeff(component, iir_idx, band_idx, 2), + __func__, iir_idx, band_idx, + get_iir_band_coeff(component, iir_idx, band_idx, 3), + __func__, iir_idx, band_idx, + get_iir_band_coeff(component, iir_idx, band_idx, 4)); + return 0; +} + +static void tx_hpf_corner_freq_callback(struct work_struct *work) +{ + struct delayed_work *hpf_delayed_work; + struct hpf_work *hpf_work; + struct snd_soc_component *component; + struct msm_dig_priv *msm_dig_cdc; + u16 tx_mux_ctl_reg; + u8 hpf_cut_of_freq; + + hpf_delayed_work = to_delayed_work(work); + hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork); + component = hpf_work->dig_cdc->component; + msm_dig_cdc = hpf_work->dig_cdc; + hpf_cut_of_freq = hpf_work->tx_hpf_cut_of_freq; + + tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX1_MUX_CTL + + (hpf_work->decimator - 1) * 32; + + dev_dbg(component->dev, "%s(): decimator %u hpf_cut_of_freq 0x%x\n", + __func__, hpf_work->decimator, (unsigned int)hpf_cut_of_freq); + if (msm_dig_cdc->update_clkdiv) + msm_dig_cdc->update_clkdiv(msm_dig_cdc->handle, 0x51); + + snd_soc_component_update_bits(component, + tx_mux_ctl_reg, 0x30, hpf_cut_of_freq << 4); +} + +static int msm_dig_cdc_codec_set_iir_gain(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + int value = 0, reg; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + if (w->shift == 0) + reg = MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL; + else if (w->shift == 1) + reg = MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL; + else + goto ret; + value = snd_soc_component_read32(component, reg); + snd_soc_component_write(component, reg, value); + break; + default: + pr_err("%s: event = %d not expected\n", __func__, event); + } +ret: + return 0; +} + +static int msm_dig_cdc_compander_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct msm_dig_priv *dig_cdc = + snd_soc_component_get_drvdata(component); + int comp_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int rx_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + + dev_dbg(component->dev, "%s: msm_dig_cdc->comp[%d]_enabled[%d] = %d\n", + __func__, comp_idx, rx_idx, + dig_cdc->comp_enabled[rx_idx]); + + ucontrol->value.integer.value[0] = dig_cdc->comp_enabled[rx_idx]; + + dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + + return 0; +} + +static int msm_dig_cdc_compander_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct msm_dig_priv *dig_cdc = snd_soc_component_get_drvdata(component); + int comp_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int rx_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + int value = ucontrol->value.integer.value[0]; + + dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + + if (dig_cdc->version >= DIANGU) { + if (!value) + dig_cdc->comp_enabled[rx_idx] = 0; + else + dig_cdc->comp_enabled[rx_idx] = comp_idx; + } + + dev_dbg(component->dev, "%s: msm_dig_cdc->comp[%d]_enabled[%d] = %d\n", + __func__, comp_idx, rx_idx, + dig_cdc->comp_enabled[rx_idx]); + + return 0; +} + +static const struct snd_kcontrol_new compander_kcontrols[] = { + SOC_SINGLE_EXT("COMP0 RX1", COMPANDER_1, MSM89XX_RX1, 1, 0, + msm_dig_cdc_compander_get, msm_dig_cdc_compander_set), + + SOC_SINGLE_EXT("COMP0 RX2", COMPANDER_1, MSM89XX_RX2, 1, 0, + msm_dig_cdc_compander_get, msm_dig_cdc_compander_set), + +}; + +static int msm_dig_cdc_set_interpolator_rate(struct snd_soc_dai *dai, + u8 rx_fs_rate_reg_val, + u32 sample_rate) +{ + snd_soc_component_update_bits(dai->component, + MSM89XX_CDC_CORE_RX1_B5_CTL, 0xF0, rx_fs_rate_reg_val); + snd_soc_component_update_bits(dai->component, + MSM89XX_CDC_CORE_RX2_B5_CTL, 0xF0, rx_fs_rate_reg_val); + return 0; +} + +static int msm_dig_cdc_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + u8 tx_fs_rate, rx_fs_rate, rx_clk_fs_rate; + int ret; + + dev_dbg(dai->component->dev, + "%s: dai_name = %s DAI-ID %x rate %d num_ch %d format %d\n", + __func__, dai->name, dai->id, params_rate(params), + params_channels(params), params_format(params)); + + switch (params_rate(params)) { + case 8000: + tx_fs_rate = 0x00; + rx_fs_rate = 0x00; + rx_clk_fs_rate = 0x00; + break; + case 16000: + tx_fs_rate = 0x20; + rx_fs_rate = 0x20; + rx_clk_fs_rate = 0x01; + break; + case 32000: + tx_fs_rate = 0x40; + rx_fs_rate = 0x40; + rx_clk_fs_rate = 0x02; + break; + case 44100: + case 48000: + tx_fs_rate = 0x60; + rx_fs_rate = 0x60; + rx_clk_fs_rate = 0x03; + break; + case 96000: + tx_fs_rate = 0x80; + rx_fs_rate = 0x80; + rx_clk_fs_rate = 0x04; + break; + case 192000: + tx_fs_rate = 0xA0; + rx_fs_rate = 0xA0; + rx_clk_fs_rate = 0x05; + break; + default: + dev_err(dai->component->dev, + "%s: Invalid sampling rate %d\n", __func__, + params_rate(params)); + return -EINVAL; + } + + snd_soc_component_update_bits(dai->component, + MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x0F, rx_clk_fs_rate); + + switch (substream->stream) { + case SNDRV_PCM_STREAM_CAPTURE: + break; + case SNDRV_PCM_STREAM_PLAYBACK: + ret = msm_dig_cdc_set_interpolator_rate(dai, rx_fs_rate, + params_rate(params)); + if (ret < 0) { + dev_err(dai->component->dev, + "%s: set decimator rate failed %d\n", __func__, + ret); + return ret; + } + break; + default: + dev_err(dai->component->dev, + "%s: Invalid stream type %d\n", __func__, + substream->stream); + return -EINVAL; + } + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + snd_soc_component_update_bits(dai->component, + MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x20, 0x20); + break; + case SNDRV_PCM_FORMAT_S24_LE: + case SNDRV_PCM_FORMAT_S24_3LE: + snd_soc_component_update_bits(dai->component, + MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x20, 0x00); + break; + default: + dev_err(dai->component->dev, "%s: wrong format selected\n", + __func__); + return -EINVAL; + } + return 0; +} + +static int msm_dig_cdc_codec_enable_dmic(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct msm_dig_priv *dig_cdc = snd_soc_component_get_drvdata(component); + u8 dmic_clk_en; + u16 dmic_clk_reg; + s32 *dmic_clk_cnt; + unsigned int dmic; + int ret; + char *dmic_num = strpbrk(w->name, "12"); + + if (dmic_num == NULL) { + dev_err(component->dev, "%s: Invalid DMIC\n", __func__); + return -EINVAL; + } + + ret = kstrtouint(dmic_num, 10, &dmic); + if (ret < 0) { + dev_err(component->dev, + "%s: Invalid DMIC line on the codec\n", __func__); + return -EINVAL; + } + + switch (dmic) { + case 1: + case 2: + dmic_clk_en = 0x01; + dmic_clk_cnt = &(dig_cdc->dmic_1_2_clk_cnt); + dmic_clk_reg = MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL; + dev_dbg(component->dev, + "%s() event %d DMIC%d dmic_1_2_clk_cnt %d\n", + __func__, event, dmic, *dmic_clk_cnt); + break; + default: + dev_err(component->dev, + "%s: Invalid DMIC Selection\n", __func__); + return -EINVAL; + } + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + (*dmic_clk_cnt)++; + if (*dmic_clk_cnt == 1) { + snd_soc_component_update_bits(component, dmic_clk_reg, + 0x0E, 0x04); + snd_soc_component_update_bits(component, dmic_clk_reg, + dmic_clk_en, dmic_clk_en); + } + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TX1_DMIC_CTL + (dmic - 1) * 0x20, + 0x07, 0x02); + break; + case SND_SOC_DAPM_POST_PMD: + (*dmic_clk_cnt)--; + if (*dmic_clk_cnt == 0) + snd_soc_component_update_bits(component, dmic_clk_reg, + dmic_clk_en, 0); + break; + } + return 0; +} + +static int msm_dig_cdc_codec_enable_dec(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct msm_asoc_mach_data *pdata = NULL; + unsigned int decimator; + struct msm_dig_priv *msm_dig_cdc = + snd_soc_component_get_drvdata(component); + char *dec_name = NULL; + char *widget_name = NULL; + char *temp; + int ret = 0, i; + u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg; + u8 dec_hpf_cut_of_freq; + int offset; + char *dec_num; + + pdata = snd_soc_card_get_drvdata(component->card); + dev_dbg(component->dev, "%s %d\n", __func__, event); + + widget_name = kstrndup(w->name, 15, GFP_KERNEL); + if (!widget_name) + return -ENOMEM; + temp = widget_name; + + dec_name = strsep(&widget_name, " "); + widget_name = temp; + if (!dec_name) { + dev_err(component->dev, + "%s: Invalid decimator = %s\n", __func__, w->name); + ret = -EINVAL; + goto out; + } + + dec_num = strpbrk(dec_name, "1234"); + if (dec_num == NULL) { + dev_err(component->dev, "%s: Invalid Decimator\n", __func__); + ret = -EINVAL; + goto out; + } + + ret = kstrtouint(dec_num, 10, &decimator); + if (ret < 0) { + dev_err(component->dev, + "%s: Invalid decimator = %s\n", __func__, dec_name); + ret = -EINVAL; + goto out; + } + + dev_dbg(component->dev, + "%s(): widget = %s dec_name = %s decimator = %u\n", __func__, + w->name, dec_name, decimator); + + if (w->reg == MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL) { + dec_reset_reg = MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL; + offset = 0; + } else { + dev_err(component->dev, "%s: Error, incorrect dec\n", __func__); + ret = -EINVAL; + goto out; + } + + tx_vol_ctl_reg = MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG + + 32 * (decimator - 1); + tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX1_MUX_CTL + + 32 * (decimator - 1); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (decimator == 3 || decimator == 4) { + /* for WSA_VI */ + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL, + 0xFF, 0x5); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TX1_DMIC_CTL + + (decimator - 1) * 0x20, 0x7, 0x2); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TX1_DMIC_CTL + + (decimator - 1) * 0x20, 0x7, 0x2); + } + /* Enableable TX digital mute */ + snd_soc_component_update_bits(component, + tx_vol_ctl_reg, 0x01, 0x01); + for (i = 0; i < NUM_DECIMATORS; i++) { + if (decimator == i + 1) + msm_dig_cdc->dec_active[i] = true; + } + + dec_hpf_cut_of_freq = snd_soc_component_read32(component, + tx_mux_ctl_reg); + + dec_hpf_cut_of_freq = (dec_hpf_cut_of_freq & 0x30) >> 4; + + tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq = + dec_hpf_cut_of_freq; + + if (dec_hpf_cut_of_freq != CF_MIN_3DB_150HZ) { + + /* set cut of freq to CF_MIN_3DB_150HZ (0x1); */ + snd_soc_component_update_bits(component, + tx_mux_ctl_reg, 0x30, CF_MIN_3DB_150HZ << 4); + } + if (msm_dig_cdc->update_clkdiv) + msm_dig_cdc->update_clkdiv(msm_dig_cdc->handle, 0x42); + break; + case SND_SOC_DAPM_POST_PMU: + /* enable HPF */ + snd_soc_component_update_bits(component, tx_mux_ctl_reg, + 0x08, 0x00); + + schedule_delayed_work( + &msm_dig_cdc->tx_mute_dwork[decimator - 1].dwork, + msecs_to_jiffies(tx_unmute_delay)); + if (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq != + CF_MIN_3DB_150HZ) { + + schedule_delayed_work(&tx_hpf_work[decimator - 1].dwork, + msecs_to_jiffies(300)); + } + /* apply the digital gain after the decimator is enabled*/ + if ((w->shift) < ARRAY_SIZE(tx_digital_gain_reg)) + snd_soc_component_write(component, + tx_digital_gain_reg[w->shift + offset], + snd_soc_component_read32(component, + tx_digital_gain_reg[w->shift + offset]) + ); + break; + case SND_SOC_DAPM_PRE_PMD: + snd_soc_component_update_bits(component, tx_vol_ctl_reg, + 0x01, 0x01); + msleep(20); + snd_soc_component_update_bits(component, tx_mux_ctl_reg, + 0x08, 0x08); + cancel_delayed_work_sync(&tx_hpf_work[decimator - 1].dwork); + cancel_delayed_work_sync( + &msm_dig_cdc->tx_mute_dwork[decimator - 1].dwork); + break; + case SND_SOC_DAPM_POST_PMD: + snd_soc_component_update_bits(component, + dec_reset_reg, 1 << w->shift, 1 << w->shift); + snd_soc_component_update_bits(component, + dec_reset_reg, 1 << w->shift, 0x0); + snd_soc_component_update_bits(component, + tx_mux_ctl_reg, 0x08, 0x08); + snd_soc_component_update_bits(component, tx_mux_ctl_reg, 0x30, + (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq) << 4); + snd_soc_component_update_bits(component, tx_vol_ctl_reg, + 0x01, 0x00); + for (i = 0; i < NUM_DECIMATORS; i++) { + if (decimator == i + 1) + msm_dig_cdc->dec_active[i] = false; + } + if (decimator == 3 || decimator == 4) { + /* for WSA_VI */ + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL, + 0xFF, 0x0); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TX1_DMIC_CTL + + (decimator - 1) * 0x20, 0x7, 0x0); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TX1_DMIC_CTL + + (decimator - 1) * 0x20, 0x7, 0x0); + } + break; + } +out: + kfree(widget_name); + return ret; +} + +static int msm_dig_cdc_event_notify(struct notifier_block *block, + unsigned long val, + void *data) +{ + enum dig_cdc_notify_event event = (enum dig_cdc_notify_event)val; + struct snd_soc_component *component = registered_digcodec; + struct msm_dig_priv *msm_dig_cdc = + snd_soc_component_get_drvdata(component); + struct msm_asoc_mach_data *pdata = NULL; + int ret = -EINVAL; + struct msm_cap_mode *capmode = NULL; + + pdata = snd_soc_card_get_drvdata(component->card); + + switch (event) { + case DIG_CDC_EVENT_CLK_ON: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x03, 0x03); + if (pdata->mclk_freq == MCLK_RATE_9P6MHZ) + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TOP_CTL, 0x01, 0x01); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x01); + break; + case DIG_CDC_EVENT_CLK_OFF: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x03, 0x00); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x00); + break; + case DIG_CDC_EVENT_RX1_MUTE_ON: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x01); + msm_dig_cdc->mute_mask |= HPHL_PA_DISABLE; + break; + case DIG_CDC_EVENT_RX1_MUTE_OFF: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= (~HPHL_PA_DISABLE); + break; + case DIG_CDC_EVENT_RX2_MUTE_ON: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x01); + msm_dig_cdc->mute_mask |= HPHR_PA_DISABLE; + break; + case DIG_CDC_EVENT_RX2_MUTE_OFF: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= (~HPHR_PA_DISABLE); + break; + case DIG_CDC_EVENT_RX3_MUTE_ON: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x01); + msm_dig_cdc->mute_mask |= SPKR_PA_DISABLE; + break; + case DIG_CDC_EVENT_RX3_MUTE_OFF: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= (~SPKR_PA_DISABLE); + break; + case DIG_CDC_EVENT_PRE_RX1_INT_ON: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B3_CTL, 0x3C, 0x28); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B4_CTL, 0x18, 0x10); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B3_CTL, 0x80, 0x80); + break; + case DIG_CDC_EVENT_PRE_RX2_INT_ON: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B3_CTL, 0x3C, 0x28); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B4_CTL, 0x18, 0x10); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B3_CTL, 0x80, 0x80); + break; + case DIG_CDC_EVENT_POST_RX1_INT_OFF: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B3_CTL, 0x3C, 0x00); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B4_CTL, 0x18, 0xFF); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B3_CTL, 0x80, 0x00); + break; + case DIG_CDC_EVENT_POST_RX2_INT_OFF: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B3_CTL, 0x3C, 0x00); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B4_CTL, 0x18, 0xFF); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B3_CTL, 0x80, 0x00); + break; + case DIG_CDC_EVENT_SSR_DOWN: + regcache_cache_only(msm_dig_cdc->regmap, true); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + atomic_set(&pdata->int_mclk0_enabled, false); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + break; + case DIG_CDC_EVENT_SSR_UP: + regcache_cache_only(msm_dig_cdc->regmap, false); + regcache_mark_dirty(msm_dig_cdc->regmap); + + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pdata->digital_cdc_core_clk.enable = 1; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s:failed to enable the MCLK\n", + __func__); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + break; + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + + regcache_sync(msm_dig_cdc->regmap); + + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pdata->digital_cdc_core_clk.enable = 0; + afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + break; + case DIG_CDC_EVENT_CAP_CONFIGURE: + capmode = (struct msm_cap_mode *)data; + capmode->micbias1_cap_mode = pdata->micbias1_cap_mode; + capmode->micbias2_cap_mode = pdata->micbias2_cap_mode; + break; + case DIG_CDC_EVENT_INVALID: + default: + break; + } + return 0; +} + +static ssize_t msm_dig_codec_version_read(struct snd_info_entry *entry, + void *file_private_data, + struct file *file, + char __user *buf, size_t count, + loff_t pos) +{ + struct msm_dig_priv *msm_dig; + char buffer[MSM_DIG_CDC_VERSION_ENTRY_SIZE]; + int len = 0; + + msm_dig = (struct msm_dig_priv *) entry->private_data; + if (!msm_dig) { + pr_err("%s: msm_dig priv is null\n", __func__); + return -EINVAL; + } + + switch (msm_dig->version) { + case DRAX_CDC: + case DIANGU: + case CAJON_2_0: + case CAJON: + case CONGA: + case TOMBAK_2_0: + case TOMBAK_1_0: + len = snprintf(buffer, sizeof(buffer), "SDM660-CDC_1_0\n"); + break; + default: + len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n"); + } + + return simple_read_from_buffer(buf, count, &pos, buffer, len); +} + +static struct snd_info_entry_ops msm_dig_codec_info_ops = { + .read = msm_dig_codec_version_read, +}; + +static int digt_cdc_notifer_service_cb(struct notifier_block *nb, + unsigned long opcode, void *ptr) +{ + struct msm_dig_priv *dig_cdc_priv = container_of(nb, + struct msm_dig_priv, + service_nb); + struct snd_soc_component *component = dig_cdc_priv->component; + bool adsp_ready = false; + unsigned long timeout; + int ret; + static bool initial_boot = true; + struct msm_asoc_mach_data *pdata = NULL; + struct audio_notifier_cb_data *cb_data = ptr; + struct msm_dig_priv *msm_dig_cdc = + snd_soc_component_get_drvdata(component); + + pdata = snd_soc_card_get_drvdata(component->card); + pr_debug("%s: opcode 0x%lx, service=%d\n", __func__, opcode, + cb_data->service); + + switch (opcode) { + case AUDIO_NOTIFIER_SERVICE_DOWN: + if (initial_boot && + cb_data->service == AUDIO_NOTIFIER_PDR_SERVICE) { + initial_boot = false; + break; + } + dev_dbg(component->dev, + "ADSP is about to power down. teardown/reset codec\n"); + + regcache_cache_only(msm_dig_cdc->regmap, true); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + atomic_set(&pdata->int_mclk0_enabled, false); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + snd_soc_card_change_online_state(component->card, 0); + break; + + case AUDIO_NOTIFIER_SERVICE_UP: + if (initial_boot && + cb_data->service == AUDIO_NOTIFIER_PDR_SERVICE) + initial_boot = false; + dev_dbg(component->dev, + "ADSP is about to power up. bring up codec\n"); + + adsp_ready = q6core_is_adsp_ready(); + if (!adsp_ready) { + timeout = jiffies + + msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS); + do { + if (!q6core_is_adsp_ready()) + continue; + adsp_ready = true; + } while (!adsp_ready && time_after(timeout, jiffies)); + } + + if (!adsp_ready) { + dev_err(component->dev, + "%s: DSP isn't ready\n", __func__); + break; + } + + dev_dbg(component->dev, "%s: DSP is ready\n", __func__); + + regcache_cache_only(msm_dig_cdc->regmap, false); + regcache_mark_dirty(msm_dig_cdc->regmap); + + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pdata->digital_cdc_core_clk.enable = 1; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s: failed to enable the MCLK\n", + __func__); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + break; + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + regcache_sync(msm_dig_cdc->regmap); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pdata->digital_cdc_core_clk.enable = 0; + afe_set_lpass_clock_v2(AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + snd_soc_card_change_online_state(component->card, 1); + break; + + default: + break; + } + return NOTIFY_OK; +} + +/* + * msm_dig_codec_info_create_codec_entry - creates msm_dig module + * @codec_root: The parent directory + * @component: Component instance + * + * Creates msm_dig module and version entry under the given + * parent directory. + * + * Return: 0 on success or negative error code on failure. + */ +int msm_dig_codec_info_create_codec_entry(struct snd_info_entry *codec_root, + struct snd_soc_component *component) +{ + struct snd_info_entry *version_entry; + struct msm_dig_priv *msm_dig; + struct snd_soc_card *card; + + if (!codec_root || !component) + return -EINVAL; + + msm_dig = snd_soc_component_get_drvdata(component); + card = component->card; + msm_dig->entry = snd_info_create_subdir(codec_root->module, + "msm_digital_codec", + codec_root); + if (!msm_dig->entry) { + dev_dbg(component->dev, "%s: failed to create msm_digital entry\n", + __func__); + return -ENOMEM; + } + + version_entry = snd_info_create_card_entry(card->snd_card, + "version", + msm_dig->entry); + if (!version_entry) { + dev_dbg(component->dev, "%s: failed to create msm_digital version entry\n", + __func__); + return -ENOMEM; + } + + version_entry->private_data = msm_dig; + version_entry->size = MSM_DIG_CDC_VERSION_ENTRY_SIZE; + version_entry->content = SNDRV_INFO_CONTENT_DATA; + version_entry->c.ops = &msm_dig_codec_info_ops; + + if (snd_info_register(version_entry) < 0) { + snd_info_free_entry(version_entry); + return -ENOMEM; + } + msm_dig->version_entry = version_entry; + if (msm_dig->get_cdc_version) + msm_dig->version = msm_dig->get_cdc_version(msm_dig->handle); + else + msm_dig->version = DRAX_CDC; + + return 0; +} +EXPORT_SYMBOL(msm_dig_codec_info_create_codec_entry); + +static void msm_dig_cdc_update_micbias_regulator( + const struct msm_dig_priv *dig_cdc, + const char *name, + struct on_demand_dig_supply *micbias_supply) +{ + int i; + + for (i = 0; i < dig_cdc->num_of_supplies; i++) { + if (dig_cdc->supplies[i].supply && + !strcmp(dig_cdc->supplies[i].supply, name)) { + micbias_supply->supply = + dig_cdc->supplies[i].consumer; + micbias_supply->min_uv = dig_cdc->regulator[i].min_uv; + micbias_supply->max_uv = dig_cdc->regulator[i].max_uv; + micbias_supply->optimum_ua = + dig_cdc->regulator[i].optimum_ua; + return; + } + } + + dev_dbg(dig_cdc->dev, "Error: regulator not found:%s\n", name); +} + +static void sdm660_tx_mute_update_callback(struct work_struct *work) +{ + struct tx_mute_work *tx_mute_dwork; + struct snd_soc_component *component = NULL; + struct msm_dig_priv *dig_cdc; + struct delayed_work *delayed_work; + u16 tx_vol_ctl_reg = 0; + u8 decimator = 0, i; + + delayed_work = to_delayed_work(work); + tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork); + dig_cdc = tx_mute_dwork->dig_cdc; + component = dig_cdc->component; + + for (i = 0; i < (NUM_DECIMATORS - 1); i++) { + if (dig_cdc->dec_active[i]) + decimator = i + 1; + if (decimator && decimator < NUM_DECIMATORS) { + /* unmute decimators corresponding to Tx DAI's*/ + tx_vol_ctl_reg = + MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG + + 32 * (decimator - 1); + snd_soc_component_update_bits(component, + tx_vol_ctl_reg, 0x01, 0x00); + } + decimator = 0; + } +} + +static int msm_dig_cdc_soc_probe(struct snd_soc_component *component) +{ + struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(component->dev); + struct snd_soc_dapm_context *dapm = + snd_soc_component_get_dapm(component); + int i, ret; + + msm_dig_cdc->component = component; + snd_soc_add_component_controls(component, compander_kcontrols, + ARRAY_SIZE(compander_kcontrols)); + + for (i = 0; i < NUM_DECIMATORS; i++) { + tx_hpf_work[i].dig_cdc = msm_dig_cdc; + tx_hpf_work[i].decimator = i + 1; + INIT_DELAYED_WORK(&tx_hpf_work[i].dwork, + tx_hpf_corner_freq_callback); + msm_dig_cdc->tx_mute_dwork[i].dig_cdc = msm_dig_cdc; + msm_dig_cdc->tx_mute_dwork[i].decimator = i + 1; + INIT_DELAYED_WORK(&msm_dig_cdc->tx_mute_dwork[i].dwork, + sdm660_tx_mute_update_callback); + } + + for (i = 0; i < MSM89XX_RX_MAX; i++) + msm_dig_cdc->comp_enabled[i] = COMPANDER_NONE; + + /* Register event notifier */ + msm_dig_cdc->nblock.notifier_call = msm_dig_cdc_event_notify; + if (msm_dig_cdc->register_notifier) { + ret = msm_dig_cdc->register_notifier(msm_dig_cdc->handle, + &msm_dig_cdc->nblock, + true); + if (ret) { + pr_err("%s: Failed to register notifier %d\n", + __func__, ret); + return ret; + } + } + + /* no_analog_codec, i.e, only digital codec is enabled, need to + * register notifier to monitor the adsp status + */ + if (msm_dig_cdc->no_analog_codec) { + msm_dig_cdc->service_nb.notifier_call = + digt_cdc_notifer_service_cb; + ret = audio_notifier_register("msm_digit_cdc", + AUDIO_NOTIFIER_ADSP_DOMAIN, + &msm_dig_cdc->service_nb); + if (ret < 0) { + pr_err("%s: Audio notifier register failed ret = %d\n", + __func__, ret); + return ret; + } + } + + msm_dig_cdc_update_micbias_regulator( + msm_dig_cdc, + on_demand_supply_name[ON_DEMAND_DIGITAL], + &msm_dig_cdc->on_demand_list[ON_DEMAND_DIGITAL]); + atomic_set(&msm_dig_cdc->on_demand_list[ON_DEMAND_DIGITAL].ref, 0); + registered_digcodec = component; + + snd_soc_dapm_ignore_suspend(dapm, "AIF1 Playback"); + snd_soc_dapm_ignore_suspend(dapm, "AIF1 Capture"); + snd_soc_dapm_ignore_suspend(dapm, "ADC1_IN"); + snd_soc_dapm_ignore_suspend(dapm, "ADC2_IN"); + snd_soc_dapm_ignore_suspend(dapm, "ADC3_IN"); + snd_soc_dapm_ignore_suspend(dapm, "PDM_OUT_RX1"); + snd_soc_dapm_ignore_suspend(dapm, "PDM_OUT_RX2"); + snd_soc_dapm_ignore_suspend(dapm, "PDM_OUT_RX3"); + + snd_soc_dapm_sync(dapm); + + return 0; +} + +static void msm_dig_cdc_soc_remove(struct snd_soc_component *component) +{ + struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(component->dev); + + if (msm_dig_cdc->register_notifier) + msm_dig_cdc->register_notifier(msm_dig_cdc->handle, + &msm_dig_cdc->nblock, + false); + iounmap(msm_dig_cdc->dig_base); +} + +static const struct snd_soc_dapm_route audio_dig_map[] = { + {"RX_I2S_CLK", NULL, "CDC_CONN"}, + {"I2S RX1", NULL, "RX_I2S_CLK"}, + {"I2S RX2", NULL, "RX_I2S_CLK"}, + {"I2S RX3", NULL, "RX_I2S_CLK"}, + + {"I2S TX1", NULL, "TX_I2S_CLK"}, + {"I2S TX2", NULL, "TX_I2S_CLK"}, + {"AIF2 VI", NULL, "TX_I2S_CLK"}, + + {"I2S TX1", NULL, "DEC1 MUX"}, + {"I2S TX2", NULL, "DEC2 MUX"}, + {"AIF2 VI", NULL, "DEC3 MUX"}, + {"AIF2 VI", NULL, "DEC4 MUX"}, + + {"PDM_OUT_RX1", NULL, "RX1 CHAIN"}, + {"PDM_OUT_RX2", NULL, "RX2 CHAIN"}, + {"PDM_OUT_RX3", NULL, "RX3 CHAIN"}, + + {"RX1 CHAIN", NULL, "RX1 MIX2"}, + {"RX2 CHAIN", NULL, "RX2 MIX2"}, + {"RX3 CHAIN", NULL, "RX3 MIX1"}, + + {"RX1 MIX1", NULL, "RX1 MIX1 INP1"}, + {"RX1 MIX1", NULL, "RX1 MIX1 INP2"}, + {"RX1 MIX1", NULL, "RX1 MIX1 INP3"}, + {"RX2 MIX1", NULL, "RX2 MIX1 INP1"}, + {"RX2 MIX1", NULL, "RX2 MIX1 INP2"}, + {"RX3 MIX1", NULL, "RX3 MIX1 INP1"}, + {"RX3 MIX1", NULL, "RX3 MIX1 INP2"}, + {"RX1 MIX2", NULL, "RX1 MIX1"}, + {"RX1 MIX2", NULL, "RX1 MIX2 INP1"}, + {"RX2 MIX2", NULL, "RX2 MIX1"}, + {"RX2 MIX2", NULL, "RX2 MIX2 INP1"}, + + {"RX1 MIX1 INP1", "RX1", "I2S RX1"}, + {"RX1 MIX1 INP1", "RX2", "I2S RX2"}, + {"RX1 MIX1 INP1", "RX3", "I2S RX3"}, + {"RX1 MIX1 INP1", "IIR1", "IIR1"}, + {"RX1 MIX1 INP1", "IIR2", "IIR2"}, + {"RX1 MIX1 INP2", "RX1", "I2S RX1"}, + {"RX1 MIX1 INP2", "RX2", "I2S RX2"}, + {"RX1 MIX1 INP2", "RX3", "I2S RX3"}, + {"RX1 MIX1 INP2", "IIR1", "IIR1"}, + {"RX1 MIX1 INP2", "IIR2", "IIR2"}, + {"RX1 MIX1 INP3", "RX1", "I2S RX1"}, + {"RX1 MIX1 INP3", "RX2", "I2S RX2"}, + {"RX1 MIX1 INP3", "RX3", "I2S RX3"}, + + {"RX2 MIX1 INP1", "RX1", "I2S RX1"}, + {"RX2 MIX1 INP1", "RX2", "I2S RX2"}, + {"RX2 MIX1 INP1", "RX3", "I2S RX3"}, + {"RX2 MIX1 INP1", "IIR1", "IIR1"}, + {"RX2 MIX1 INP1", "IIR2", "IIR2"}, + {"RX2 MIX1 INP2", "RX1", "I2S RX1"}, + {"RX2 MIX1 INP2", "RX2", "I2S RX2"}, + {"RX2 MIX1 INP2", "RX3", "I2S RX3"}, + {"RX2 MIX1 INP2", "IIR1", "IIR1"}, + {"RX2 MIX1 INP2", "IIR2", "IIR2"}, + {"RX2 MIX1 INP3", "RX1", "I2S RX1"}, + {"RX2 MIX1 INP3", "RX2", "I2S RX2"}, + {"RX2 MIX1 INP3", "RX3", "I2S RX3"}, + + {"RX3 MIX1 INP1", "RX1", "I2S RX1"}, + {"RX3 MIX1 INP1", "RX2", "I2S RX2"}, + {"RX3 MIX1 INP1", "RX3", "I2S RX3"}, + {"RX3 MIX1 INP1", "IIR1", "IIR1"}, + {"RX3 MIX1 INP1", "IIR2", "IIR2"}, + {"RX3 MIX1 INP2", "RX1", "I2S RX1"}, + {"RX3 MIX1 INP2", "RX2", "I2S RX2"}, + {"RX3 MIX1 INP2", "RX3", "I2S RX3"}, + {"RX3 MIX1 INP2", "IIR1", "IIR1"}, + {"RX3 MIX1 INP2", "IIR2", "IIR2"}, + {"RX3 MIX1 INP3", "RX1", "I2S RX1"}, + {"RX3 MIX1 INP3", "RX2", "I2S RX2"}, + {"RX3 MIX1 INP3", "RX3", "I2S RX3"}, + + {"RX1 MIX2 INP1", "IIR1", "IIR1"}, + {"RX2 MIX2 INP1", "IIR1", "IIR1"}, + {"RX1 MIX2 INP1", "IIR2", "IIR2"}, + {"RX2 MIX2 INP1", "IIR2", "IIR2"}, + + /* Decimator Inputs */ + {"DEC1 MUX", "DMIC1", "DMIC1"}, + {"DEC1 MUX", "DMIC2", "DMIC2"}, + {"DEC1 MUX", "ADC1", "ADC1_IN"}, + {"DEC1 MUX", "ADC2", "ADC2_IN"}, + {"DEC1 MUX", "ADC3", "ADC3_IN"}, + {"DEC1 MUX", NULL, "CDC_CONN"}, + + {"DEC2 MUX", "DMIC1", "DMIC1"}, + {"DEC2 MUX", "DMIC2", "DMIC2"}, + {"DEC2 MUX", "ADC1", "ADC1_IN"}, + {"DEC2 MUX", "ADC2", "ADC2_IN"}, + {"DEC2 MUX", "ADC3", "ADC3_IN"}, + {"DEC2 MUX", NULL, "CDC_CONN"}, + + {"DEC3 MUX", "DMIC3", "DMIC3"}, + {"DEC4 MUX", "DMIC4", "DMIC4"}, + {"DEC3 MUX", NULL, "CDC_CONN"}, + {"DEC4 MUX", NULL, "CDC_CONN"}, + + {"IIR1", NULL, "IIR1 INP1 MUX"}, + {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"}, + {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"}, + {"IIR2", NULL, "IIR2 INP1 MUX"}, + {"IIR2 INP1 MUX", "DEC1", "DEC1 MUX"}, + {"IIR2 INP1 MUX", "DEC2", "DEC2 MUX"}, +}; + +static const char * const rx_mix1_text[] = { + "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3" +}; + +static const char * const rx_mix2_text[] = { + "ZERO", "IIR1", "IIR2" +}; + +static const char * const dec_mux_text[] = { + "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2" +}; + +static const char * const dec3_mux_text[] = { + "ZERO", "DMIC3" +}; + +static const char * const dec4_mux_text[] = { + "ZERO", "DMIC4" +}; + +static const char * const iir_inp1_text[] = { + "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3" +}; + +/* RX1 MIX1 */ +static const struct soc_enum rx_mix1_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, + 0, 6, rx_mix1_text); + +static const struct soc_enum rx_mix1_inp2_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, + 3, 6, rx_mix1_text); + +static const struct soc_enum rx_mix1_inp3_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, + 0, 6, rx_mix1_text); + +/* RX1 MIX2 */ +static const struct soc_enum rx_mix2_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, + 0, 3, rx_mix2_text); + +/* RX2 MIX1 */ +static const struct soc_enum rx2_mix1_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, + 0, 6, rx_mix1_text); + +static const struct soc_enum rx2_mix1_inp2_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, + 3, 6, rx_mix1_text); + +static const struct soc_enum rx2_mix1_inp3_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, + 0, 6, rx_mix1_text); + +/* RX2 MIX2 */ +static const struct soc_enum rx2_mix2_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, + 0, 3, rx_mix2_text); + +/* RX3 MIX1 */ +static const struct soc_enum rx3_mix1_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, + 0, 6, rx_mix1_text); + +static const struct soc_enum rx3_mix1_inp2_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, + 3, 6, rx_mix1_text); + +static const struct soc_enum rx3_mix1_inp3_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, + 0, 6, rx_mix1_text); + +/* DEC */ +static const struct soc_enum dec1_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B1_CTL, + 0, 6, dec_mux_text); + +static const struct soc_enum dec2_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B1_CTL, + 3, 6, dec_mux_text); + +static const struct soc_enum dec3_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX3_MUX_CTL, + 0, ARRAY_SIZE(dec3_mux_text), dec3_mux_text); + +static const struct soc_enum dec4_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX4_MUX_CTL, + 0, ARRAY_SIZE(dec4_mux_text), dec4_mux_text); + +static const struct soc_enum iir1_inp1_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, + 0, 6, iir_inp1_text); + +static const struct soc_enum iir2_inp1_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, + 0, 6, iir_inp1_text); + +/*cut of frequency for high pass filter*/ +static const char * const cf_text[] = { + "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz" +}; + +static const struct soc_enum cf_rxmix1_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX1_B4_CTL, 0, 3, cf_text); + +static const struct soc_enum cf_rxmix2_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX2_B4_CTL, 0, 3, cf_text); + +static const struct soc_enum cf_rxmix3_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX3_B4_CTL, 0, 3, cf_text); + +static const struct snd_kcontrol_new rx3_mix1_inp1_mux = + SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum); + +#define MSM89XX_DEC_ENUM(xname, xenum) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_enum_double, \ + .get = snd_soc_dapm_get_enum_double, \ + .put = msm_dig_cdc_put_dec_enum, \ + .private_value = (unsigned long)&xenum } + +static const struct snd_kcontrol_new dec1_mux = + MSM89XX_DEC_ENUM("DEC1 MUX Mux", dec1_mux_enum); + +static const struct snd_kcontrol_new dec2_mux = + MSM89XX_DEC_ENUM("DEC2 MUX Mux", dec2_mux_enum); + +static const struct snd_kcontrol_new dec3_mux = + SOC_DAPM_ENUM("DEC3 MUX Mux", dec3_mux_enum); + +static const struct snd_kcontrol_new dec4_mux = + SOC_DAPM_ENUM("DEC4 MUX Mux", dec4_mux_enum); + +static const struct snd_kcontrol_new iir1_inp1_mux = + SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum); + +static const struct snd_kcontrol_new iir2_inp1_mux = + SOC_DAPM_ENUM("IIR2 INP1 Mux", iir2_inp1_mux_enum); + +static const struct snd_kcontrol_new rx_mix1_inp1_mux = + SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum); + +static const struct snd_kcontrol_new rx_mix1_inp2_mux = + SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum); + +static const struct snd_kcontrol_new rx_mix1_inp3_mux = + SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum); + +static const struct snd_kcontrol_new rx2_mix1_inp1_mux = + SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum); + +static const struct snd_kcontrol_new rx2_mix1_inp2_mux = + SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum); + +static const struct snd_kcontrol_new rx2_mix1_inp3_mux = + SOC_DAPM_ENUM("RX2 MIX1 INP3 Mux", rx2_mix1_inp3_chain_enum); + +static const struct snd_kcontrol_new rx3_mix1_inp2_mux = + SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum); + +static const struct snd_kcontrol_new rx3_mix1_inp3_mux = + SOC_DAPM_ENUM("RX3 MIX1 INP3 Mux", rx3_mix1_inp3_chain_enum); + +static const struct snd_kcontrol_new rx1_mix2_inp1_mux = + SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx_mix2_inp1_chain_enum); + +static const struct snd_kcontrol_new rx2_mix2_inp1_mux = + SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum); + +static const struct snd_soc_dapm_widget msm_dig_dapm_widgets[] = { + SND_SOC_DAPM_AIF_IN("I2S RX1", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("I2S RX2", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("I2S RX3", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_AIF_OUT("I2S TX1", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("I2S TX2", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("AIF2 VI", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_MIXER_E("RX1 MIX2", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, + MSM89XX_RX1, 0, NULL, 0, + msm_dig_cdc_codec_enable_interpolator, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIXER_E("RX2 MIX2", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, + MSM89XX_RX2, 0, NULL, 0, + msm_dig_cdc_codec_enable_interpolator, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIXER_E("RX3 MIX1", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, + MSM89XX_RX3, 0, NULL, 0, + msm_dig_cdc_codec_enable_interpolator, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_MIXER("RX1 CHAIN", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("RX2 CHAIN", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("RX3 CHAIN", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0, + &rx_mix1_inp1_mux), + SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0, + &rx_mix1_inp2_mux), + SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0, + &rx_mix1_inp3_mux), + + SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0, + &rx2_mix1_inp1_mux), + SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0, + &rx2_mix1_inp2_mux), + SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0, + &rx2_mix1_inp3_mux), + + SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0, + &rx3_mix1_inp1_mux), + SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0, + &rx3_mix1_inp2_mux), + SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0, + &rx3_mix1_inp3_mux), + + SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0, + &rx1_mix2_inp1_mux), + SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0, + &rx2_mix2_inp1_mux), + + SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, MSM89XX_CDC_CORE_CLK_OTHR_CTL, + 2, 0, NULL, 0), + + SND_SOC_DAPM_MUX_E("DEC1 MUX", + MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0, 0, + &dec1_mux, msm_dig_cdc_codec_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("DEC2 MUX", + MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 1, 0, + &dec2_mux, msm_dig_cdc_codec_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("DEC3 MUX", + MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 2, 0, + &dec3_mux, msm_dig_cdc_codec_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("DEC4 MUX", + MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 3, 0, + &dec4_mux, msm_dig_cdc_codec_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + /* Sidetone */ + SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), + SND_SOC_DAPM_PGA_E("IIR1", MSM89XX_CDC_CORE_CLK_SD_CTL, 0, 0, NULL, 0, + msm_dig_cdc_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU), + + SND_SOC_DAPM_MUX("IIR2 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir2_inp1_mux), + SND_SOC_DAPM_PGA_E("IIR2", MSM89XX_CDC_CORE_CLK_SD_CTL, 1, 0, NULL, 0, + msm_dig_cdc_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU), + + SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", + MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 4, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", + MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 4, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("DIGITAL_REGULATOR", SND_SOC_NOPM, + ON_DEMAND_DIGITAL, 0, + msm_dig_cdc_enable_on_demand_supply, + SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMD), + + /* Digital Mic Inputs */ + SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, + msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, + msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_INPUT("DMIC3"), + SND_SOC_DAPM_INPUT("DMIC4"), + SND_SOC_DAPM_INPUT("ADC1_IN"), + SND_SOC_DAPM_INPUT("ADC2_IN"), + SND_SOC_DAPM_INPUT("ADC3_IN"), + SND_SOC_DAPM_OUTPUT("PDM_OUT_RX1"), + SND_SOC_DAPM_OUTPUT("PDM_OUT_RX2"), + SND_SOC_DAPM_OUTPUT("PDM_OUT_RX3"), +}; + +static const struct soc_enum cf_dec1_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX1_MUX_CTL, 4, 3, cf_text); + +static const struct soc_enum cf_dec2_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX2_MUX_CTL, 4, 3, cf_text); + +static const struct soc_enum cf_dec3_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX3_MUX_CTL, 4, 3, cf_text); + +static const struct soc_enum cf_dec4_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX4_MUX_CTL, 4, 3, cf_text); + +static const struct snd_kcontrol_new msm_dig_snd_controls[] = { + SOC_SINGLE_SX_TLV("DEC1 Volume", + MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("DEC2 Volume", + MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("DEC3 Volume", + MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("DEC4 Volume", + MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, + 0, -84, 40, digital_gain), + + SOC_SINGLE_SX_TLV("IIR1 INP1 Volume", + MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("IIR1 INP2 Volume", + MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("IIR1 INP3 Volume", + MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("IIR1 INP4 Volume", + MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("IIR2 INP1 Volume", + MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, + 0, -84, 40, digital_gain), + + SOC_SINGLE_SX_TLV("RX1 Digital Volume", + MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("RX2 Digital Volume", + MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("RX3 Digital Volume", + MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, + 0, -84, 40, digital_gain), + + SOC_SINGLE_EXT("IIR1 Enable Band1", IIR1, BAND1, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR1 Enable Band2", IIR1, BAND2, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR1 Enable Band3", IIR1, BAND3, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR1 Enable Band4", IIR1, BAND4, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR1 Enable Band5", IIR1, BAND5, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + + SOC_SINGLE_EXT("IIR2 Enable Band1", IIR2, BAND1, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR2 Enable Band2", IIR2, BAND2, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR2 Enable Band3", IIR2, BAND3, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR2 Enable Band4", IIR2, BAND4, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR2 Enable Band5", IIR2, BAND5, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + + SOC_SINGLE_MULTI_EXT("IIR1 Band1", IIR1, BAND1, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR1 Band2", IIR1, BAND2, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR1 Band3", IIR1, BAND3, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR1 Band4", IIR1, BAND4, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR1 Band5", IIR1, BAND5, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + + SOC_SINGLE_MULTI_EXT("IIR2 Band1", IIR2, BAND1, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR2 Band2", IIR2, BAND2, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR2 Band3", IIR2, BAND3, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR2 Band4", IIR2, BAND4, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR2 Band5", IIR2, BAND5, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + + SOC_SINGLE("RX1 HPF Switch", + MSM89XX_CDC_CORE_RX1_B5_CTL, 2, 1, 0), + SOC_SINGLE("RX2 HPF Switch", + MSM89XX_CDC_CORE_RX2_B5_CTL, 2, 1, 0), + SOC_SINGLE("RX3 HPF Switch", + MSM89XX_CDC_CORE_RX3_B5_CTL, 2, 1, 0), + + SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum), + SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum), + SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum), + + SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), + SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), + SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), + SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), + SOC_SINGLE("TX1 HPF Switch", + MSM89XX_CDC_CORE_TX1_MUX_CTL, 3, 1, 0), + SOC_SINGLE("TX2 HPF Switch", + MSM89XX_CDC_CORE_TX2_MUX_CTL, 3, 1, 0), + SOC_SINGLE("TX3 HPF Switch", + MSM89XX_CDC_CORE_TX3_MUX_CTL, 3, 1, 0), + SOC_SINGLE("TX4 HPF Switch", + MSM89XX_CDC_CORE_TX4_MUX_CTL, 3, 1, 0), +}; + +static int msm_dig_cdc_enable_on_demand_supply( + struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + int ret = 0; + const char *err_msg = "failed for micbias with err ="; + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct msm_dig_priv *msm_dig_cdc = + snd_soc_component_get_drvdata(component); + struct on_demand_dig_supply *supply; + + if (w->shift >= ON_DEMAND_DIG_SUPPLIES_MAX) { + dev_err(component->dev, + "%s: error index >= MAX on demand supplies", __func__); + ret = -EINVAL; + goto out; + } + dev_dbg(component->dev, "%s: supply: %s event: %d ref: %d\n", + __func__, on_demand_supply_name[w->shift], event, + atomic_read(&msm_dig_cdc->on_demand_list[w->shift].ref)); + + supply = &msm_dig_cdc->on_demand_list[w->shift]; + if (!supply->supply) { + dev_err(component->dev, "%s: err supply not present ond for %d", + __func__, w->shift); + goto out; + } + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (atomic_inc_return(&supply->ref) == 1) { + ret = regulator_set_voltage(supply->supply, + supply->min_uv, + supply->max_uv); + if (ret) { + dev_err(component->dev, + "Setting regulator voltage(en) %s %d\n", + err_msg, ret); + goto out; + } + ret = regulator_set_load(supply->supply, + supply->optimum_ua); + if (ret < 0) { + dev_err(component->dev, + "Setting regulator optimum mode(en) %s %d\n", + err_msg, ret); + goto out; + } + ret = regulator_enable(supply->supply); + if (ret) + dev_err(component->dev, + "%s: Failed to enable %s\n", __func__, + on_demand_supply_name[w->shift]); + } + break; + case SND_SOC_DAPM_POST_PMD: + if (atomic_read(&supply->ref) == 0) { + dev_dbg(component->dev, + "%s: %s supply has been disabled.\n", + __func__, on_demand_supply_name[w->shift]); + goto out; + } + if (atomic_dec_return(&supply->ref) == 0) { + ret = regulator_disable(supply->supply); + if (ret) + dev_err(component->dev, + "%s: Failed to disable %s\n", + __func__, + on_demand_supply_name[w->shift]); + ret = regulator_set_voltage(supply->supply, + 0, + supply->max_uv); + if (ret) { + dev_err(component->dev, + "Setting regulator voltage(dis) %s %d\n", + err_msg, ret); + goto out; + } + ret = regulator_set_load(supply->supply, 0); + if (ret < 0) + dev_err(component->dev, + "Setting regulator optimum mode(dis) %s %d\n", + err_msg, ret); + } + break; + default: + break; + } +out: + return ret; +} + +static int msm_digital_cdc_init_supplies(struct msm_dig_priv *msm_cdc) +{ + int ret; + int i; + const char *err_msg1 = "Setting regulator voltage"; + const char *err_msg2 = "Setting regulator optimum mode"; + + msm_cdc->supplies = devm_kzalloc(msm_cdc->dev, + sizeof(struct regulator_bulk_data) * + ARRAY_SIZE(msm_cdc->regulator), + GFP_KERNEL); + if (!msm_cdc->supplies) { + ret = -ENOMEM; + goto err; + } + + msm_cdc->num_of_supplies = 0; + + if (ARRAY_SIZE(msm_cdc->regulator) > MAX_REGULATOR) { + dev_err(msm_cdc->dev, "%s: Array Size out of bound\n", + __func__); + ret = -EINVAL; + goto err; + } + + for (i = 0; i < ARRAY_SIZE(msm_cdc->regulator); i++) { + if (msm_cdc->regulator[i].name) { + msm_cdc->supplies[i].supply = + msm_cdc->regulator[i].name; + msm_cdc->num_of_supplies++; + } + } + + ret = devm_regulator_bulk_get(msm_cdc->dev, + msm_cdc->num_of_supplies, + msm_cdc->supplies); + if (ret != 0) { + dev_err(msm_cdc->dev, + "Failed to get supplies: err = %d\n", + ret); + goto err_supplies; + } + + for (i = 0; i < msm_cdc->num_of_supplies; i++) { + if (regulator_count_voltages( + msm_cdc->supplies[i].consumer) <= 0) + continue; + ret = regulator_set_voltage( + msm_cdc->supplies[i].consumer, + msm_cdc->regulator[i].min_uv, + msm_cdc->regulator[i].max_uv); + if (ret) { + dev_err(msm_cdc->dev, + "%s failed for regulator %s err = %d\n", + err_msg1, msm_cdc->supplies[i].supply, ret); + goto err_supplies; + } + ret = regulator_set_load(msm_cdc->supplies[i].consumer, + msm_cdc->regulator[i].optimum_ua); + if (ret < 0) { + dev_err(msm_cdc->dev, + "%s failed for regulator %s err = %d\n", + err_msg2, msm_cdc->supplies[i].supply, ret); + goto err_supplies; + } else { + ret = 0; + } + } + + return ret; + +err_supplies: +err: + return ret; +} + +static int msm_digital_cdc_dt_parse_vreg_info(struct device *dev, + struct dig_cdc_regulator *vreg, const char *vreg_name) +{ + int len, ret = 0; + const __be32 *prop; + char prop_name[CODEC_DT_MAX_PROP_SIZE]; + struct device_node *regnode = NULL; + u32 prop_val; + + snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "%s-supply", + vreg_name); + regnode = of_parse_phandle(dev->of_node, prop_name, 0); + + if (!regnode) { + dev_err(dev, "Looking up %s property in node %s failed\n", + prop_name, dev->of_node->full_name); + return -ENODEV; + } + + dev_dbg(dev, "Looking up %s property in node %s\n", + prop_name, dev->of_node->full_name); + + vreg->name = vreg_name; + + snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, + "qcom,%s-voltage", vreg_name); + prop = of_get_property(dev->of_node, prop_name, &len); + + if (!prop || (len != (2 * sizeof(__be32)))) { + dev_err(dev, "%s %s property\n", + prop ? "invalid format" : "no", prop_name); + return -EINVAL; + } + vreg->min_uv = be32_to_cpup(&prop[0]); + vreg->max_uv = be32_to_cpup(&prop[1]); + + snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, + "qcom,%s-current", vreg_name); + + ret = of_property_read_u32(dev->of_node, prop_name, &prop_val); + if (ret) { + dev_err(dev, "Looking up %s property in node %s failed", + prop_name, dev->of_node->full_name); + return -EFAULT; + } + vreg->optimum_ua = prop_val; + dev_dbg(dev, "%s: vol=[%d %d]uV, curr=[%d]uA\n", vreg->name, + vreg->min_uv, vreg->max_uv, vreg->optimum_ua); + return 0; +} + +static struct snd_soc_dai_ops msm_dig_dai_ops = { + .hw_params = msm_dig_cdc_hw_params, +}; + + +static struct snd_soc_dai_driver msm_codec_dais[] = { + { + .name = "msm_dig_cdc_dai_rx1", + .id = AIF1_PB, + .playback = { /* Support maximum range */ + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .rate_max = 192000, + .rate_min = 8000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S24_3LE, + }, + .ops = &msm_dig_dai_ops, + }, + { + .name = "msm_dig_cdc_dai_tx1", + .id = AIF1_CAP, + .capture = { /* Support maximum range */ + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 4, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &msm_dig_dai_ops, + }, + { + .name = "msm_dig_cdc_dai_vifeed", + .id = AIF2_VIFEED, + .capture = { /* Support maximum range */ + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &msm_dig_dai_ops, + }, +}; + +static int msm_dig_cdc_suspend(struct snd_soc_component *component) +{ + struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(component->dev); + + msm_dig_cdc->dapm_bias_off = 1; + return 0; +} + +static int msm_dig_cdc_resume(struct snd_soc_component *component) +{ + struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(component->dev); + + msm_dig_cdc->dapm_bias_off = 0; + return 0; +} + +const struct snd_soc_component_driver soc_msm_dig_codec = { + .name = DRV_NAME, + .probe = msm_dig_cdc_soc_probe, + .remove = msm_dig_cdc_soc_remove, + .suspend = msm_dig_cdc_suspend, + .resume = msm_dig_cdc_resume, + .controls = msm_dig_snd_controls, + .num_controls = ARRAY_SIZE(msm_dig_snd_controls), + .dapm_widgets = msm_dig_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(msm_dig_dapm_widgets), + .dapm_routes = audio_dig_map, + .num_dapm_routes = ARRAY_SIZE(audio_dig_map), +}; + +const struct regmap_config msm_digital_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 8, + .lock = enable_digital_callback, + .unlock = disable_digital_callback, + .cache_type = REGCACHE_FLAT, + .reg_defaults = msm89xx_cdc_core_defaults, + .num_reg_defaults = MSM89XX_CDC_CORE_MAX_REGISTER, + .writeable_reg = msm89xx_cdc_core_writeable_reg, + .readable_reg = msm89xx_cdc_core_readable_reg, + .volatile_reg = msm89xx_cdc_core_volatile_reg, + .reg_format_endian = REGMAP_ENDIAN_NATIVE, + .val_format_endian = REGMAP_ENDIAN_NATIVE, + .max_register = MSM89XX_CDC_CORE_MAX_REGISTER, +}; + +static bool msm_digital_cdc_populate_dt_pdata( + struct device *dev, + struct msm_dig_priv *dig_priv) +{ + int ret, ond_cnt, i, idx = 0; + const char *name = NULL; + const char *ond_prop_name = "qcom,cdc-on-demand-supplies"; + + ond_cnt = of_property_count_strings(dev->of_node, ond_prop_name); + if (ond_cnt < 0) + ond_cnt = 0; + + if (ond_cnt > ARRAY_SIZE(dig_priv->regulator)) { + ret = -EINVAL; + goto err; + } + + for (i = 0; i < ond_cnt; i++, idx++) { + ret = of_property_read_string_index(dev->of_node, ond_prop_name, + i, &name); + if (ret) { + dev_err(dev, "%s: err parsing on_demand for %s idx %d\n", + __func__, ond_prop_name, i); + goto err; + } + + dev_dbg(dev, "%s: Found on-demand cdc supply %s\n", __func__, + name); + ret = msm_digital_cdc_dt_parse_vreg_info(dev, + &dig_priv->regulator[idx], + name); + if (ret) { + dev_err(dev, "%s: err parsing vreg on_demand for %s idx %d\n", + __func__, name, idx); + goto err; + } + } + + return true; +err: + dev_err(dev, "%s: Failed to populate DT data ret = %d\n", + __func__, ret); + return false; +} + +static void msm_digital_cdc_disable_supplies(struct msm_dig_priv *msm_cdc) +{ + int i; + + if (!msm_cdc->supplies) + return; + + regulator_bulk_disable(msm_cdc->num_of_supplies, + msm_cdc->supplies); + for (i = 0; i < msm_cdc->num_of_supplies; i++) { + if (regulator_count_voltages( + msm_cdc->supplies[i].consumer) <= 0) + continue; + regulator_set_voltage(msm_cdc->supplies[i].consumer, 0, + msm_cdc->regulator[i].max_uv); + regulator_set_load(msm_cdc->supplies[i].consumer, 0); + } + regulator_bulk_free(msm_cdc->num_of_supplies, + msm_cdc->supplies); + devm_kfree(msm_cdc->dev, msm_cdc->supplies); +} + +static int msm_dig_cdc_probe(struct platform_device *pdev) +{ + int ret = -EINVAL; + u32 dig_cdc_addr; + struct msm_dig_priv *msm_dig_cdc; + struct dig_ctrl_platform_data *pdata = NULL; + int adsp_state = 0; + + adsp_state = apr_get_subsys_state(); + if ((adsp_state != APR_SUBSYS_LOADED) || (!q6core_is_adsp_ready())) { + dev_err(&pdev->dev, "Adsp is not loaded yet %d\n", + adsp_state); + return -EPROBE_DEFER; + } + device_init_wakeup(&pdev->dev, true); + + msm_dig_cdc = devm_kzalloc(&pdev->dev, sizeof(struct msm_dig_priv), + GFP_KERNEL); + if (!msm_dig_cdc) + return -ENOMEM; + msm_dig_cdc->dev = &pdev->dev; + if (pdev->dev.of_node == NULL) + return -EINVAL; + + if (pdev->dev.of_node) + msm_dig_cdc->no_analog_codec = of_property_read_bool( + pdev->dev.of_node, + "qcom,no-analog-codec"); + if (msm_dig_cdc->no_analog_codec) { + dev_dbg(&pdev->dev, "%s:Platform data from device tree\n", + __func__); + if (msm_digital_cdc_populate_dt_pdata(&pdev->dev, + msm_dig_cdc)) { + ret = msm_digital_cdc_init_supplies( + msm_dig_cdc); + if (ret) { + dev_err(&pdev->dev, + "%s: Fail to enable Codec supplies\n", + __func__); + goto rtn; + } + } + } else { + pdata = dev_get_platdata(&pdev->dev); + if (!pdata) { + dev_err(&pdev->dev, "%s: pdata from parent is NULL\n", + __func__); + ret = -EINVAL; + goto err_supplies; + } + msm_dig_cdc->update_clkdiv = pdata->update_clkdiv; + msm_dig_cdc->set_compander_mode = pdata->set_compander_mode; + msm_dig_cdc->get_cdc_version = pdata->get_cdc_version; + msm_dig_cdc->handle = pdata->handle; + msm_dig_cdc->register_notifier = pdata->register_notifier; + } + + ret = of_property_read_u32(pdev->dev.of_node, "reg", + &dig_cdc_addr); + if (ret) { + dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", + __func__, "reg"); + goto err_supplies; + } + + msm_dig_cdc->dig_base = ioremap(dig_cdc_addr, + MSM89XX_CDC_CORE_MAX_REGISTER); + if (msm_dig_cdc->dig_base == NULL) { + dev_err(&pdev->dev, "%s ioremap failed\n", __func__); + ret = -ENOMEM; + goto err_supplies; + } + msm_dig_cdc->regmap = + devm_regmap_init_mmio_clk(&pdev->dev, NULL, + msm_dig_cdc->dig_base, &msm_digital_regmap_config); + + + dev_set_drvdata(&pdev->dev, msm_dig_cdc); + ret = snd_soc_register_component(&pdev->dev, &soc_msm_dig_codec, + msm_codec_dais, ARRAY_SIZE(msm_codec_dais)); + if (ret) { + dev_err(&pdev->dev, + "%s:snd_soc_register_component failed with error %d\n", + __func__, ret); + goto err_supplies; + } + dev_dbg(&pdev->dev, "%s: registered DIG CODEC 0x%x\n", + __func__, dig_cdc_addr); + return ret; +err_supplies: + if (msm_dig_cdc->no_analog_codec) + msm_digital_cdc_disable_supplies(msm_dig_cdc); +rtn: + return ret; +} + +static int msm_dig_cdc_remove(struct platform_device *pdev) +{ + struct msm_dig_priv *msm_cdc = dev_get_drvdata(&pdev->dev); + + snd_soc_unregister_component(&pdev->dev); + msm_digital_cdc_disable_supplies(msm_cdc); + return 0; +} + +#ifdef CONFIG_PM +static int msm_dig_suspend(struct device *dev) +{ + struct msm_asoc_mach_data *pdata; + struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(dev); + + if (!registered_digcodec || !msm_dig_cdc) { + pr_debug("%s:digcodec not initialized, return\n", __func__); + return 0; + } + pdata = snd_soc_card_get_drvdata(registered_digcodec->card); + if (!pdata) { + pr_debug("%s:card not initialized, return\n", __func__); + return 0; + } + if (msm_dig_cdc->dapm_bias_off) { + pr_debug("%s: mclk cnt = %d, mclk_enabled = %d\n", + __func__, atomic_read(&pdata->int_mclk0_rsc_ref), + atomic_read(&pdata->int_mclk0_enabled)); + + if (atomic_read(&pdata->int_mclk0_enabled) == true) { + cancel_delayed_work_sync( + &pdata->disable_int_mclk0_work); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pdata->digital_cdc_core_clk.enable = 0; + afe_set_lpass_clock_v2(AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + atomic_set(&pdata->int_mclk0_enabled, false); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + } + } + + return 0; +} + +static int msm_dig_resume(struct device *dev) +{ + return 0; +} + +static const struct dev_pm_ops msm_dig_pm_ops = { + .suspend_late = msm_dig_suspend, + .resume_early = msm_dig_resume, +}; +#endif + +static const struct of_device_id msm_dig_cdc_of_match[] = { + {.compatible = "qcom,msm-digital-codec"}, + {}, +}; + +static struct platform_driver msm_digcodec_driver = { + .driver = { + .owner = THIS_MODULE, + .name = DRV_NAME, + .of_match_table = msm_dig_cdc_of_match, +#ifdef CONFIG_PM + .pm = &msm_dig_pm_ops, +#endif + }, + .probe = msm_dig_cdc_probe, + .remove = msm_dig_cdc_remove, +}; +module_platform_driver(msm_digcodec_driver); + +MODULE_DESCRIPTION("MSM Audio Digital codec driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc.c b/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc.c index 42f67b142ee63fd6c73dfe583970b76b49e35963..11dce64e6f13fb896e4125ccdc2e2fe488600e20 100644 --- a/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc.c +++ b/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc.c @@ -93,11 +93,12 @@ static int msm_digcdc_clock_control(bool flag) __func__); /* * Avoid access to lpass register - * as clock enable failed during SSR. + * as clock enable failed during SSR/PDR. */ - if (ret == -ENODEV) - msm_dig_cdc->regmap->cache_only = true; + msm_dig_cdc->regmap->cache_only = true; return ret; + } else { + msm_dig_cdc->regmap->cache_only = false; } pr_debug("enabled digital codec core clk\n"); atomic_set(&pdata->int_mclk0_enabled, true); diff --git a/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc.h b/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc.h index a6178cd20419017f1a27d71636e125202f1240b4..3d2b34275c663e41c710f04d35644ec6a2bc2143 100644 --- a/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc.h +++ b/techpack/audio/asoc/codecs/sdm660_cdc/msm-digital-cdc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2016-2017, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017, 2020-2021, The Linux Foundation. All rights reserved. */ #ifndef MSM_DIGITAL_CDC_H #define MSM_DIGITAL_CDC_H @@ -8,7 +8,7 @@ #define HPHL_PA_DISABLE (0x01 << 1) #define HPHR_PA_DISABLE (0x01 << 2) #define SPKR_PA_DISABLE (0x01 << 3) - +#define MAX_REGULATOR 7 #define NUM_DECIMATORS 5 /* Codec supports 1 compander */ enum { @@ -25,30 +25,62 @@ enum { MSM89XX_RX_MAX, }; +enum { + ON_DEMAND_DIGITAL = 0, + ON_DEMAND_DIG_SUPPLIES_MAX, +}; + +struct on_demand_dig_supply { + struct regulator *supply; + atomic_t ref; + int min_uv; + int max_uv; + int optimum_ua; +}; + +struct dig_cdc_regulator { + const char *name; + int min_uv; + int max_uv; + int optimum_ua; + struct regulator *regulator; +}; + struct tx_mute_work { struct msm_dig_priv *dig_cdc; u32 decimator; struct delayed_work dwork; }; +struct msm_cap_mode { + u8 micbias1_cap_mode; + u8 micbias2_cap_mode; +}; + struct msm_dig_priv { struct snd_soc_component *component; + struct device *dev; u32 comp_enabled[MSM89XX_RX_MAX]; int (*codec_hph_comp_gpio)(bool enable, - struct snd_soc_component *component); + struct snd_soc_component *component); s32 dmic_1_2_clk_cnt; s32 dmic_3_4_clk_cnt; bool dec_active[NUM_DECIMATORS]; int version; + /* cal info for codec */ + struct fw_info *fw_data; + bool no_analog_codec; /* Entry for version info */ struct snd_info_entry *entry; struct snd_info_entry *version_entry; char __iomem *dig_base; struct regmap *regmap; struct notifier_block nblock; + struct notifier_block service_nb; u32 mute_mask; int dapm_bias_off; void *handle; + struct on_demand_dig_supply on_demand_list[ON_DEMAND_DIG_SUPPLIES_MAX]; void (*set_compander_mode)(void *handle, int val); void (*update_clkdiv)(void *handle, int val); int (*get_cdc_version)(void *handle); @@ -56,6 +88,9 @@ struct msm_dig_priv { struct notifier_block *nblock, bool enable); struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS]; + u32 num_of_supplies; + struct regulator_bulk_data *supplies; + struct dig_cdc_regulator regulator[MAX_REGULATOR]; }; struct dig_ctrl_platform_data { @@ -85,13 +120,16 @@ enum { BAND_MAX, }; -#if IS_ENABLED(CONFIG_SND_SOC_DIGITAL_CDC) +#if (IS_ENABLED(CONFIG_SND_SOC_DIGITAL_CDC) || \ + IS_ENABLED(CONFIG_SND_SOC_DIGITAL_CDC_LEGACY)) extern void msm_dig_cdc_hph_comp_cb( int (*codec_hph_comp_gpio)( bool enable, struct snd_soc_component *component), struct snd_soc_component *component); int msm_dig_codec_info_create_codec_entry(struct snd_info_entry *codec_root, struct snd_soc_component *component); +extern int msm_digcdc_mclk_enable(struct snd_soc_component *component, + int mclk_enable, bool dapm); #else /* CONFIG_SND_SOC_DIGITAL_CDC */ static inline void msm_dig_cdc_hph_comp_cb( int (*codec_hph_comp_gpio)( @@ -106,5 +144,10 @@ static inline int msm_dig_codec_info_create_codec_entry( { return 0; } +static inline int msm_digcdc_mclk_enable(struct snd_soc_component *component, + int mclk_enable, bool dapm) +{ + return 0; +} #endif /* CONFIG_SND_SOC_DIGITAL_CDC */ #endif diff --git a/techpack/audio/asoc/codecs/wcd-spi.c b/techpack/audio/asoc/codecs/wcd-spi.c index 4c7a85338ed48e1ed42154fc8af264f891f541fd..3834374a65a8d9bcb2d6e9cf53794259ae736545 100644 --- a/techpack/audio/asoc/codecs/wcd-spi.c +++ b/techpack/audio/asoc/codecs/wcd-spi.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #include @@ -1531,6 +1531,17 @@ static const struct component_ops wcd_spi_component_ops = { .unbind = wcd_spi_component_unbind, }; +#ifdef CONFIG_WCD_SPI_DMA_MASKING +static void arch_setup_spi_archdata(struct spi_device *spi) +{ + if (spi->dev.coherent_dma_mask == DMA_MASK_NONE && + spi->dev.dma_mask == NULL) { + spi->dev.coherent_dma_mask = DMA_BIT_MASK(sizeof(dma_addr_t) * 8); + spi->dev.dma_mask = &spi->dev.coherent_dma_mask; + } +} +#endif + static int wcd_spi_probe(struct spi_device *spi) { struct wcd_spi_priv *wcd_spi; @@ -1557,8 +1568,11 @@ static int wcd_spi_probe(struct spi_device *spi) mutex_init(&wcd_spi->xfer_mutex); INIT_DELAYED_WORK(&wcd_spi->clk_dwork, wcd_spi_clk_work); init_completion(&wcd_spi->resume_comp); - arch_setup_dma_ops(&spi->dev, 0, 0, NULL, true); +#ifdef CONFIG_WCD_SPI_DMA_MASKING + arch_setup_spi_archdata(spi); +#endif + arch_setup_dma_ops(&spi->dev, 0, 0, NULL, true); wcd_spi->spi = spi; spi_set_drvdata(spi, wcd_spi); diff --git a/techpack/audio/asoc/codecs/wcd9335.c b/techpack/audio/asoc/codecs/wcd9335.c index 009e614d0eac9ad001d88cac81e50d4bc741c743..7248c3ff6cc519760235401047d91895306dbb82 100644 --- a/techpack/audio/asoc/codecs/wcd9335.c +++ b/techpack/audio/asoc/codecs/wcd9335.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, 2021, The Linux Foundation. All rights reserved. */ #include #include @@ -2430,9 +2430,9 @@ static int slim_tx_mixer_put(struct snd_kcontrol *kcontrol, mutex_lock(&tasha_p->codec_mutex); if (tasha_p->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS) { - if (dai_id != AIF1_CAP) { - dev_err(component->dev, "%s: invalid AIF for I2C mode\n", - __func__); + if (dai_id >= ARRAY_SIZE(vport_slim_check_table)) { + dev_err(component->dev, "%s: dai_id: %d, out of bounds\n", + __func__, dai_id); mutex_unlock(&tasha_p->codec_mutex); return -EINVAL; } @@ -2441,6 +2441,7 @@ static int slim_tx_mixer_put(struct snd_kcontrol *kcontrol, if (dai_id >= ARRAY_SIZE(vport_i2s_check_table)) { dev_err(component->dev, "%s: dai_id: %d, out of bounds\n", __func__, dai_id); + mutex_unlock(&tasha_p->codec_mutex); return -EINVAL; } vtable = vport_i2s_check_table[dai_id]; @@ -13287,9 +13288,11 @@ static int tasha_handle_pdata(struct tasha_priv *tasha, static struct wcd_cpe_core *tasha_codec_get_cpe_core( struct snd_soc_component *component) { - struct tasha_priv *priv = snd_soc_component_get_drvdata(component); - - return priv->cpe_core; + struct tasha_priv *priv = NULL; + priv = dev_get_drvdata(component->dev); + if (priv) + return priv->cpe_core; + return NULL; } static int tasha_codec_cpe_fll_update_divider( diff --git a/techpack/audio/asoc/codecs/wcd934x/Kbuild b/techpack/audio/asoc/codecs/wcd934x/Kbuild index d372ed762cef3fc6ee7193fa86426d63bf9e74bc..404cc8dca141e1d346540439b2465cb895cf5ed1 100644 --- a/techpack/audio/asoc/codecs/wcd934x/Kbuild +++ b/techpack/audio/asoc/codecs/wcd934x/Kbuild @@ -121,6 +121,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_SND_SOC_WCD934X) += wcd934x_dlkm.o wcd934x_dlkm-y := $(WCD934X_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/wcd937x/Kbuild b/techpack/audio/asoc/codecs/wcd937x/Kbuild index 5bbbad7cbdf58257627d0c5829a0a63a1b532162..b81fed3efd343bc1d2b331859774d21c43f91fe1 100644 --- a/techpack/audio/asoc/codecs/wcd937x/Kbuild +++ b/techpack/audio/asoc/codecs/wcd937x/Kbuild @@ -123,6 +123,3 @@ wcd937x_dlkm-y := $(WCD937X_OBJS) obj-$(CONFIG_SND_SOC_WCD937X_SLAVE) += wcd937x_slave_dlkm.o wcd937x_slave_dlkm-y := $(WCD937X_SLAVE_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/wcd937x/wcd937x.c b/techpack/audio/asoc/codecs/wcd937x/wcd937x.c index 428c9814335610b85d31743a93369a5628d30d1a..7641146db392b598dafd42c05b0975a40fbea32b 100644 --- a/techpack/audio/asoc/codecs/wcd937x/wcd937x.c +++ b/techpack/audio/asoc/codecs/wcd937x/wcd937x.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -49,6 +50,8 @@ enum { HPH_COMP_DELAY, HPH_PA_DELAY, AMIC2_BCS_ENABLE, + WCD_HPHL_EN, + WCD_EAR_EN, }; static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); @@ -113,8 +116,19 @@ static int wcd937x_handle_post_irq(void *data) static int wcd937x_init_reg(struct snd_soc_component *component) { - snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL, + u32 val =0; + + val = snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_29) + & 0x0F; + if (snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_16) + == 0x02 || snd_soc_component_read32(component, + WCD937X_DIGITAL_EFUSE_REG_17) > 0x09) { + snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL, + 0x0E, val); + } else { + snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL, 0x0E, 0x0E); + } snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL, 0x80, 0x80); usleep_range(1000, 1010); @@ -141,6 +155,28 @@ static int wcd937x_init_reg(struct snd_soc_component *component) 0xFF, 0xFA); snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1, 0xFF, 0xFA); + snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_2, + 0x38, 0x00); + snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_2, + 0x38, 0x00); + snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_2, + 0x38, 0x00); + /* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */ + if (snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_16) + == 0x01) { + snd_soc_component_update_bits(component, + WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); + } else if (snd_soc_component_read32(component, + WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) { + snd_soc_component_update_bits(component, + WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04); + snd_soc_component_update_bits(component, + WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04); + snd_soc_component_update_bits(component, + WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); + snd_soc_component_update_bits(component, + WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL , 0xF0, 0x50); + } return 0; } @@ -425,6 +461,12 @@ static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); break; case SND_SOC_DAPM_POST_PMU: + if ((snd_soc_component_read32(component, + WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) && + ((snd_soc_component_read32(component, + WCD937X_ANA_HPH) & 0x0C) == 0x0C)) + snd_soc_component_update_bits(component, + WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x90); if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) snd_soc_component_update_bits(component, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, @@ -466,6 +508,12 @@ static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00); break; case SND_SOC_DAPM_POST_PMD: + if ((snd_soc_component_read32(component, + WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) && + ((snd_soc_component_read32(component, + WCD937X_ANA_HPH) & 0x0C) == 0x0C)) + snd_soc_component_update_bits(component, + WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x80); snd_soc_component_update_bits(component, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x01); @@ -499,6 +547,12 @@ static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); break; case SND_SOC_DAPM_POST_PMU: + if ((snd_soc_component_read32(component, + WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) && + ((snd_soc_component_read32(component, + WCD937X_ANA_HPH) & 0x0C) == 0x0C)) + snd_soc_component_update_bits(component, + WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x90); if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) snd_soc_component_update_bits(component, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, @@ -540,6 +594,12 @@ static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00); break; case SND_SOC_DAPM_POST_PMD: + if ((snd_soc_component_read32(component, + WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) && + ((snd_soc_component_read32(component, + WCD937X_ANA_HPH) & 0x0C) == 0x0C)) + snd_soc_component_update_bits(component, + WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x80); snd_soc_component_update_bits(component, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x01); @@ -777,6 +837,7 @@ static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, set_bit(HPH_PA_DELAY, &wcd937x->status_mask); snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13); + set_bit(WCD_HPHL_EN, &wcd937x->status_mask); break; case SND_SOC_DAPM_POST_PMU: /* @@ -807,12 +868,14 @@ static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, WCD937X_IRQ_HPHL_PDM_WD_INT); break; case SND_SOC_DAPM_PRE_PMD: - wcd_disable_irq(&wcd937x->irq_info, + if (!test_bit(WCD_EAR_EN, &wcd937x->status_mask)) { + wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT); if (wcd937x->update_wcd_event) wcd937x->update_wcd_event(wcd937x->handle, WCD_BOLERO_EVT_RX_MUTE, (WCD_RX1 << 0x10 | 0x1)); + } blocking_notifier_call_chain(&wcd937x->mbhc->notifier, WCD_EVENT_PRE_HPHL_PA_OFF, &wcd937x->mbhc->wcd_mbhc); @@ -843,6 +906,7 @@ static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, WCD_CLSH_EVENT_POST_PA, WCD_CLSH_STATE_HPHL, hph_mode); + clear_bit(WCD_HPHL_EN, &wcd937x->status_mask); break; }; return ret; @@ -931,10 +995,12 @@ static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05); - else + else { snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13); + set_bit(WCD_EAR_EN, &wcd937x->status_mask); + } if (!wcd937x->comp1_enable) snd_soc_component_update_bits(component, WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80); @@ -957,16 +1023,24 @@ static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, WCD937X_IRQ_HPHL_PDM_WD_INT); break; case SND_SOC_DAPM_PRE_PMD: - if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) + if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) { wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT); - else - wcd_disable_irq(&wcd937x->irq_info, + if (wcd937x->update_wcd_event) + wcd937x->update_wcd_event(wcd937x->handle, + WCD_BOLERO_EVT_RX_MUTE, + (WCD_RX1 << 0x10 | 0x1)); + } + else { + if(!test_bit(WCD_HPHL_EN, &wcd937x->status_mask)) { + wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT); - if (wcd937x->update_wcd_event) - wcd937x->update_wcd_event(wcd937x->handle, + if (wcd937x->update_wcd_event) + wcd937x->update_wcd_event(wcd937x->handle, WCD_BOLERO_EVT_RX_MUTE, (WCD_RX1 << 0x10 | 0x1)); + } + } break; case SND_SOC_DAPM_POST_PMD: if (!wcd937x->comp1_enable) @@ -983,10 +1057,12 @@ static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00); - else + else { snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00); + clear_bit(WCD_EAR_EN, &wcd937x->status_mask); + } usleep_range(10000, 10010); /* disable EAR CnP FSM */ snd_soc_component_update_bits(component, @@ -1052,13 +1128,16 @@ static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w, wcd937x_rx_connect_port(component, COMP_L, true); break; case SND_SOC_DAPM_POST_PMD: - wcd937x_rx_connect_port(component, HPH_L, false); - if (wcd937x->comp1_enable) - wcd937x_rx_connect_port(component, COMP_L, false); - wcd937x_rx_clk_disable(component); - snd_soc_component_update_bits(component, + if (!test_bit(WCD_HPHL_EN, &wcd937x->status_mask) && + !test_bit(WCD_EAR_EN, &wcd937x->status_mask)) { + wcd937x_rx_connect_port(component, HPH_L, false); + if (wcd937x->comp1_enable) + wcd937x_rx_connect_port(component, COMP_L, false); + wcd937x_rx_clk_disable(component); + snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00); + } break; }; return 0; diff --git a/techpack/audio/asoc/codecs/wcd938x/Kbuild b/techpack/audio/asoc/codecs/wcd938x/Kbuild index 3dfe142bcfc281df749b800bc4d13dc300a44e79..bc5284355db20d724f72986f02c890e20e673685 100644 --- a/techpack/audio/asoc/codecs/wcd938x/Kbuild +++ b/techpack/audio/asoc/codecs/wcd938x/Kbuild @@ -111,6 +111,3 @@ wcd938x_dlkm-y := $(WCD938X_OBJS) obj-$(CONFIG_SND_SOC_WCD938X_SLAVE) += wcd938x_slave_dlkm.o wcd938x_slave_dlkm-y := $(WCD938X_SLAVE_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/wcd9xxx-core.c b/techpack/audio/asoc/codecs/wcd9xxx-core.c index 9736c43c365bf09b2363ca26143dfa64adcd8e9b..5e441f1ee4c80af35e8ff07baad405f040417c0b 100644 --- a/techpack/audio/asoc/codecs/wcd9xxx-core.c +++ b/techpack/audio/asoc/codecs/wcd9xxx-core.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2011-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2011-2021, The Linux Foundation. All rights reserved. */ #include @@ -1197,9 +1197,12 @@ static int wcd9xxx_i2c_probe(struct i2c_client *client, wcd9xxx_set_intf_type(WCD9XXX_INTERFACE_TYPE_I2C); return ret; + } else { + ret = -EINVAL; + pr_err("%s: I2C probe in wrong state, ret %d\n", __func__, ret); + goto fail; } - pr_err("%s: I2C probe in wrong state\n", __func__); err_device_init: diff --git a/techpack/audio/asoc/codecs/wcd_cpe_core.c b/techpack/audio/asoc/codecs/wcd_cpe_core.c index 5b5291f8a603d9197335db8e6b2a6eec193f1466..8f09e6b880f6fdaaac429abb8d5210189531ed65 100644 --- a/techpack/audio/asoc/codecs/wcd_cpe_core.c +++ b/techpack/audio/asoc/codecs/wcd_cpe_core.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2019, 2021, The Linux Foundation. All rights reserved. */ #include @@ -18,7 +18,7 @@ #include #include #include -#include "cpe_core.h" +#include #include "cpe_err.h" #include "cpe_cmi.h" #include "wcd_cpe_core.h" @@ -116,6 +116,8 @@ struct wcd_cpe_attribute { ssize_t count); }; +static u64 wcd_cpe_dma_mask = DMA_BIT_MASK(32); + #define WCD_CPE_ATTR(_name, _mode, _show, _store) \ static struct wcd_cpe_attribute cpe_attr_##_name = { \ .attr = {.name = __stringify(_name), .mode = _mode}, \ @@ -639,7 +641,7 @@ void *wcd_cpe_get_core_handle( goto done; } - core = wcd_get_cpe_core(component); + core = wcd_get_cpe_core(core_d->component); if (!core) dev_err(component->dev, @@ -2034,6 +2036,8 @@ struct wcd_cpe_core *wcd_cpe_init(const char *img_fname, __func__); goto schedule_dload_work; } + core->dev->coherent_dma_mask = DMA_BIT_MASK(32); + core->dev->dma_mask = &wcd_cpe_dma_mask; arch_setup_dma_ops(core->dev, 0, 0, NULL, 0); core->cpe_dump_v_addr = dma_alloc_coherent(core->dev, diff --git a/techpack/audio/asoc/codecs/wcd_cpe_services.c b/techpack/audio/asoc/codecs/wcd_cpe_services.c index 96e2bb1945a4b7d32f35d422fb3ae9ed5694638e..0a8e73dc7ff3b4bea5a7aadcfafa8766b59e47d1 100644 --- a/techpack/audio/asoc/codecs/wcd_cpe_services.c +++ b/techpack/audio/asoc/codecs/wcd_cpe_services.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2018, 2021, The Linux Foundation. All rights reserved. */ #include @@ -283,7 +283,7 @@ static enum cpe_svc_result cpe_is_command_valid( static int cpe_register_read(u32 reg, u8 *val) { - *(val) = snd_soc_read(cpe_d.cdc_priv, reg); + *(val) = snd_soc_component_read32(cpe_d.cdc_priv, reg); return 0; } @@ -292,7 +292,7 @@ static enum cpe_svc_result cpe_update_bits(u32 reg, { int ret = 0; - ret = snd_soc_update_bits(cpe_d.cdc_priv, reg, + ret = snd_soc_component_update_bits(cpe_d.cdc_priv, reg, mask, value); if (ret < 0) return CPE_SVC_FAILED; @@ -308,7 +308,7 @@ static int cpe_register_write(u32 reg, u32 val) pr_debug("%s: reg = 0x%x, value = 0x%x\n", __func__, reg, val); - ret = snd_soc_write(cpe_d.cdc_priv, reg, val); + ret = snd_soc_component_write(cpe_d.cdc_priv, reg, val); if (ret < 0) return CPE_SVC_FAILED; @@ -317,8 +317,9 @@ static int cpe_register_write(u32 reg, u32 val) static int cpe_register_write_repeat(u32 reg, u8 *ptr, u32 to_write) { - struct snd_soc_codec *codec = cpe_d.cdc_priv; - struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent); + struct snd_soc_component *component = cpe_d.cdc_priv; + struct wcd9xxx *wcd9xxx = + dev_get_drvdata(component->dev->parent); int ret = 0; ret = wcd9xxx_slim_write_repeat(wcd9xxx, reg, to_write, ptr); diff --git a/techpack/audio/asoc/codecs/wsa881x-analog.c b/techpack/audio/asoc/codecs/wsa881x-analog.c index fe8a5b9c9d3083e3ba03c8c074063d038987b5df..cb8ff542bd81505fa765118ccc53bff5f92d7f85 100644 --- a/techpack/audio/asoc/codecs/wsa881x-analog.c +++ b/techpack/audio/asoc/codecs/wsa881x-analog.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2016, 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2016, 2018-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -60,6 +61,7 @@ struct wsa881x_pdata { int clk_cnt; int enable_cnt; int version; + int wsa881x_id; struct mutex bg_lock; struct mutex res_lock; struct delayed_work ocp_ctl_work; @@ -73,6 +75,10 @@ enum { WSA881X_STATUS_I2C, }; +enum { + WSA8810, + WSA8815, +}; #define WSA881X_OCP_CTL_TIMER_SEC 2 #define WSA881X_OCP_CTL_TEMP_CELSIUS 25 #define WSA881X_OCP_CTL_POLL_TIMER_SEC 60 @@ -101,9 +107,14 @@ static int wsa881x_i2c_addr = -1; static int wsa881x_probing_count; static int wsa881x_presence_count; +/* Gain value "POS_12_DB", "POS_10P5_DB", and "POS_15_DB" + * only support on WSA8815 + */ static const char * const wsa881x_spk_pa_gain_text[] = { -"POS_13P5_DB", "POS_12_DB", "POS_10P5_DB", "POS_9_DB", "POS_7P5_DB", -"POS_6_DB", "POS_4P5_DB", "POS_3_DB", "POS_1P5_DB", "POS_0_DB"}; +"POS_18_DB", "POS_16P5_DB", "POS_15_DB", "POS_13P5_DB", +"POS_12_DB", "POS_10P5_DB", "POS_9_DB", "POS_7P5_DB", +"POS_6_DB", "POS_4P5_DB", "POS_3_DB", "POS_1P5_DB", +"POS_0_DB"}; static const struct soc_enum wsa881x_spk_pa_gain_enum[] = { SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa881x_spk_pa_gain_text), @@ -140,6 +151,12 @@ static int wsa881x_spk_pa_gain_put(struct snd_kcontrol *kcontrol, __func__, ucontrol->value.integer.value[0]); return -EINVAL; } + if (ucontrol->value.integer.value[0] < 3 && + wsa881x->wsa881x_id == WSA8810) { + dev_err(component->dev, "%s: Unsupported gain val %ld for WSA8810\n", + __func__, ucontrol->value.integer.value[0]); + return -EINVAL; + } wsa881x->spk_pa_gain = ucontrol->value.integer.value[0]; dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", __func__, ucontrol->value.integer.value[0]); @@ -1454,6 +1471,14 @@ static int wsa881x_i2c_probe(struct i2c_client *client, pdata->regmap[WSA881X_DIGITAL_SLAVE], WSA881X_DIGITAL_SLAVE); } + pdata->wsa881x_id = wsa881x_i2c_read_device(pdata, + WSA881X_OTP_REG_0); + if (pdata->wsa881x_id & 0x01) { + pdata->wsa881x_id = WSA8815; + } else { + pdata->wsa881x_id = WSA8810; + } + pr_debug("%s: wsa881x_id : %d\n", __func__, pdata->wsa881x_id); wsa881x_presence_count++; wsa881x_probing_count++; ret = snd_soc_register_component(&client->dev, diff --git a/techpack/audio/asoc/codecs/wsa883x/Android.mk b/techpack/audio/asoc/codecs/wsa883x/Android.mk index 42ad517106c7f59dad50e04cc676a4e1bb7f38d1..80b4969bbe3f75099db88a91c42fde69f378eea0 100644 --- a/techpack/audio/asoc/codecs/wsa883x/Android.mk +++ b/techpack/audio/asoc/codecs/wsa883x/Android.mk @@ -6,10 +6,13 @@ ifeq ($(call is-board-platform,lahaina),true) AUDIO_SELECT := CONFIG_SND_SOC_LAHAINA=m endif +ifeq ($(call is-board-platform,kona),true) +AUDIO_SELECT := CONFIG_SND_SOC_KONA=m +endif AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,lahaina lito),true) +ifeq ($(call is-board-platform-in-list, kona lahaina lito),true) LOCAL_PATH := $(call my-dir) diff --git a/techpack/audio/asoc/codecs/wsa883x/Kbuild b/techpack/audio/asoc/codecs/wsa883x/Kbuild index ac608b46c6a3854c343590bd22fc62e7ccc54427..5393dbca973a802f8e8deea3e65615669d53de86 100644 --- a/techpack/audio/asoc/codecs/wsa883x/Kbuild +++ b/techpack/audio/asoc/codecs/wsa883x/Kbuild @@ -22,6 +22,10 @@ ifeq ($(KERNEL_BUILD), 0) include $(AUDIO_ROOT)/config/litoauto.conf INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h endif + ifeq ($(CONFIG_ARCH_KONA), y) + include $(AUDIO_ROOT)/config/konaauto.conf + INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h + endif endif # As per target team, build is done as follows: @@ -102,6 +106,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_SND_SOC_WSA883X) += wsa883x_dlkm.o wsa883x_dlkm-y := $(WSA883X_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/wsa883x/wsa883x.c b/techpack/audio/asoc/codecs/wsa883x/wsa883x.c index 31ba5ba75d10c2f487dd4dc163f07f15d49743d0..bb01a8e56a66dc2077b29a3786ac7baa63f8bc48 100644 --- a/techpack/audio/asoc/codecs/wsa883x/wsa883x.c +++ b/techpack/audio/asoc/codecs/wsa883x/wsa883x.c @@ -1557,7 +1557,7 @@ static int wsa883x_swr_probe(struct swr_device *pdev) ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum); if (ret) { dev_err(&pdev->dev, - "%s get devnum %d for dev addr %lx failed\n", + "%s get devnum %d for dev addr %llx failed\n", __func__, devnum, pdev->addr); goto dev_err; } diff --git a/techpack/audio/asoc/msm-audio-effects-q6-v2.c b/techpack/audio/asoc/msm-audio-effects-q6-v2.c index db3bd87ebc0e237101a9b89141bf3c0116d8bfbe..f415e699fb433aca2001a2fe144b585906a2ab97 100644 --- a/techpack/audio/asoc/msm-audio-effects-q6-v2.c +++ b/techpack/audio/asoc/msm-audio-effects-q6-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1002,6 +1003,14 @@ int msm_audio_effects_pbe_handler(struct audio_client *ac, pbe->config.reserved = GET_NEXT(values, param_max_offset, rc); + if ((pbe->config.bandpass_filter_order > 3) || + (pbe->config.bandpass_filter_order < 1)) { + pr_err("%s: Invalid BPF order\n", + __func__); + rc = -EINVAL; + goto invalid_config; + } + p_coeffs = &pbe->config.p1LowPassCoeffs[0]; lpf_len = (pbe->config.xover_filter_order == 3) ? 10 : 5; hpf_len = (pbe->config.xover_filter_order == 3) ? 10 : 5; diff --git a/techpack/audio/asoc/msm-compress-q6-v2.c b/techpack/audio/asoc/msm-compress-q6-v2.c index b34202cb1d13ea717a6b46bc0ed617e2496cacd8..9db6e5c4e4e4e168c3e008cd7e09022fd68e0a70 100644 --- a/techpack/audio/asoc/msm-compress-q6-v2.c +++ b/techpack/audio/asoc/msm-compress-q6-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ @@ -2907,18 +2908,18 @@ static int msm_compr_pointer(struct snd_compr_stream *cstream, spin_lock_irqsave(&prtd->lock, flags); tstamp.sampling_rate = prtd->sample_rate; tstamp.byte_offset = prtd->byte_offset; - if (cstream->direction == SND_COMPRESS_PLAYBACK) + if (cstream->direction == SND_COMPRESS_PLAYBACK) { + runtime->total_bytes_transferred = prtd->copied_total; tstamp.copied_total = prtd->copied_total; - else if (cstream->direction == SND_COMPRESS_CAPTURE) + } + else if (cstream->direction == SND_COMPRESS_CAPTURE) { + runtime->total_bytes_available = prtd->received_total; tstamp.copied_total = prtd->received_total; + } first_buffer = prtd->first_buffer; if (atomic_read(&prtd->error)) { pr_err_ratelimited("%s Got RESET EVENTS notification, return error\n", __func__); - if (cstream->direction == SND_COMPRESS_PLAYBACK) - runtime->total_bytes_transferred = tstamp.copied_total; - else - runtime->total_bytes_available = tstamp.copied_total; tstamp.pcm_io_frames = 0; memcpy(arg, &tstamp, sizeof(struct snd_compr_tstamp)); spin_unlock_irqrestore(&prtd->lock, flags); diff --git a/techpack/audio/asoc/msm-cpe-lsm.c b/techpack/audio/asoc/msm-cpe-lsm.c index 0f98192a083e740e14e7d7e0db86b069918abda6..15f2cee9e823048fa3d395dda62398be496935cd 100644 --- a/techpack/audio/asoc/msm-cpe-lsm.c +++ b/techpack/audio/asoc/msm-cpe-lsm.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2019, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2019, 2020-2021, The Linux Foundation. All rights reserved. */ #include @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -129,7 +130,7 @@ struct cpe_lsm_lab { struct cpe_priv { void *core_handle; - struct snd_soc_codec *codec; + struct snd_soc_component *component; struct wcd_cpe_lsm_ops lsm_ops; struct wcd_cpe_afe_ops afe_ops; bool afe_mad_ctl; @@ -186,6 +187,7 @@ static struct cpe_priv *cpe_get_private_data( struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd; + struct snd_soc_component *component = NULL; if (!substream || !substream->private_data) { pr_err("%s: %s is invalid\n", @@ -196,14 +198,19 @@ static struct cpe_priv *cpe_get_private_data( rtd = substream->private_data; - if (!rtd || !rtd->platform) { + if (!rtd) { pr_err("%s: %s is invalid\n", __func__, (!rtd) ? "runtime" : "platform"); goto err_ret; } - return snd_soc_platform_get_drvdata(rtd->platform); + component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); + if (!component) { + pr_err("%s: invalid component\n", __func__); + goto err_ret; + } + return snd_soc_component_get_drvdata(component); err_ret: return NULL; @@ -756,7 +763,7 @@ static int msm_cpe_lsm_open(struct snd_pcm_substream *substream) struct wcd_cpe_lsm_ops *lsm_ops; int rc = 0; - if (!cpe || !cpe->codec) { + if (!cpe || !cpe->component) { dev_err(rtd->dev, "%s: Invalid private data\n", __func__); @@ -792,11 +799,11 @@ static int msm_cpe_lsm_open(struct snd_pcm_substream *substream) return -EINVAL; } - cpe->core_handle = wcd_cpe_get_core_handle(cpe->codec); + cpe->core_handle = wcd_cpe_get_core_handle(cpe->component); if (!cpe->core_handle) { dev_err(rtd->dev, - "%s: Invalid handle to codec core\n", + "%s: Invalid handle to component core\n", __func__); return -EINVAL; } @@ -3215,7 +3222,6 @@ static int msm_asoc_cpe_lsm_probe(struct snd_soc_component *component) { struct snd_soc_card *card; struct snd_soc_pcm_runtime *rtd; - struct snd_soc_codec *codec; struct cpe_priv *cpe_priv; struct snd_soc_component *component_rtd = NULL; const struct snd_kcontrol_new *kcontrol; @@ -3259,14 +3265,12 @@ static int msm_asoc_cpe_lsm_probe(struct snd_soc_component *component) port_id = 1; } - codec = rtd->codec; - cpe_priv = kzalloc(sizeof(struct cpe_priv), GFP_KERNEL); if (!cpe_priv) return -ENOMEM; - cpe_priv->codec = codec; + cpe_priv->component = component; cpe_priv->input_port_id = port_id; wcd_cpe_get_lsm_ops(&cpe_priv->lsm_ops); wcd_cpe_get_afe_ops(&cpe_priv->afe_ops); @@ -3317,7 +3321,7 @@ static int msm_cpe_lsm_probe(struct platform_device *pdev) */ static int msm_cpe_lsm_remove(struct platform_device *pdev) { - snd_soc_unregister_commponent(&pdev->dev); + snd_soc_unregister_component(&pdev->dev); return 0; } diff --git a/techpack/audio/asoc/msm-dai-q6-v2.c b/techpack/audio/asoc/msm-dai-q6-v2.c index 883d8d87dff8320c73231e5ffea83eade34ac2e6..1effeceeabaf0fb0d04b78f583804fc54733dddc 100644 --- a/techpack/audio/asoc/msm-dai-q6-v2.c +++ b/techpack/audio/asoc/msm-dai-q6-v2.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include @@ -3896,20 +3896,20 @@ static const struct snd_kcontrol_new rt_proxy_config_controls[] = { }; static const struct snd_kcontrol_new usb_audio_cfg_controls[] = { - SOC_SINGLE_EXT("USB_AUDIO_RX dev_token", 0, 0, UINT_MAX, 0, + SOC_SINGLE_EXT("USB_AUDIO_RX dev_token", 0, 0, INT_MAX, 0, msm_dai_q6_usb_audio_cfg_get, msm_dai_q6_usb_audio_cfg_put), SOC_SINGLE_EXT("USB_AUDIO_RX endian", 0, 0, 1, 0, msm_dai_q6_usb_audio_endian_cfg_get, msm_dai_q6_usb_audio_endian_cfg_put), - SOC_SINGLE_EXT("USB_AUDIO_TX dev_token", 0, 0, UINT_MAX, 0, + SOC_SINGLE_EXT("USB_AUDIO_TX dev_token", 0, 0, INT_MAX, 0, msm_dai_q6_usb_audio_cfg_get, msm_dai_q6_usb_audio_cfg_put), SOC_SINGLE_EXT("USB_AUDIO_TX endian", 0, 0, 1, 0, msm_dai_q6_usb_audio_endian_cfg_get, msm_dai_q6_usb_audio_endian_cfg_put), SOC_SINGLE_EXT("USB_AUDIO_RX service_interval", SND_SOC_NOPM, 0, - UINT_MAX, 0, + INT_MAX, 0, msm_dai_q6_usb_audio_svc_interval_get, msm_dai_q6_usb_audio_svc_interval_put), }; @@ -6877,6 +6877,10 @@ static int msm_dai_q6_meta_mi2s_hw_params(struct snd_pcm_substream *substream, port_cfg->bit_width = 24; dai_data->bitwidth = 24; break; + case SNDRV_PCM_FORMAT_S32_LE: + port_cfg->bit_width = 32; + dai_data->bitwidth = 32; + break; default: pr_err("%s: format %d\n", __func__, params_format(params)); @@ -11649,7 +11653,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11670,7 +11674,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11691,7 +11695,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11712,7 +11716,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11733,7 +11737,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11754,7 +11758,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11775,7 +11779,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11796,7 +11800,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11817,7 +11821,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11838,7 +11842,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11859,7 +11863,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11880,7 +11884,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11901,7 +11905,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11922,7 +11926,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11943,7 +11947,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11964,7 +11968,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, diff --git a/techpack/audio/asoc/msm-lsm-client.c b/techpack/audio/asoc/msm-lsm-client.c index 77b25de138c19aa89fd8c4047eb9bbe4020f452e..f4a8dbdce4fd209418eeec5093af4e9d33515260 100644 --- a/techpack/audio/asoc/msm-lsm-client.c +++ b/techpack/audio/asoc/msm-lsm-client.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -2112,6 +2113,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, case SNDRV_LSM_GET_MODULE_PARAMS_32: { struct lsm_params_get_info_32 p_info_32, *param_info_rsp = NULL; struct lsm_params_get_info *p_info = NULL; + prtd->lsm_client->get_param_payload = NULL; memset(&p_info_32, 0 , sizeof(p_info_32)); if (!prtd->lsm_client->use_topology) { @@ -2162,6 +2164,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, __func__, err); kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; goto done; } @@ -2172,6 +2175,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, err = -ENOMEM; kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; goto done; } @@ -2196,6 +2200,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, kfree(p_info); kfree(param_info_rsp); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; break; } case SNDRV_LSM_REG_SND_MODEL_V2: @@ -2407,6 +2412,7 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, case SNDRV_LSM_GET_MODULE_PARAMS: { struct lsm_params_get_info temp_p_info, *p_info = NULL; + prtd->lsm_client->get_param_payload = NULL; memset(&temp_p_info, 0, sizeof(temp_p_info)); if (!prtd->lsm_client->use_topology) { @@ -2425,6 +2431,15 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, err = -EFAULT; goto done; } + + if (temp_p_info.param_size > 0 && + ((INT_MAX - sizeof(temp_p_info)) < + temp_p_info.param_size)) { + pr_err("%s: Integer overflow\n", __func__); + err = -EINVAL; + goto done; + } + size = sizeof(temp_p_info) + temp_p_info.param_size; p_info = kzalloc(size, GFP_KERNEL); @@ -2478,6 +2493,7 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, free: kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; break; } case SNDRV_LSM_EVENT_STATUS: diff --git a/techpack/audio/asoc/msm-pcm-host-voice-v2.c b/techpack/audio/asoc/msm-pcm-host-voice-v2.c index 41c3982dd3434ae9e179e0fe94d1b263aa050ace..0f5ec2399d9becb9da578e7a6594801f9ab1ffc4 100644 --- a/techpack/audio/asoc/msm-pcm-host-voice-v2.c +++ b/techpack/audio/asoc/msm-pcm-host-voice-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -626,6 +627,12 @@ static int hpcm_start_vocpcm(char *pcm_id, struct hpcm_drv *prtd, } } + if (*no_of_tp != no_of_tp_req && *no_of_tp > 2) { + pr_err("%s:: Invalid hpcm start request\n", __func__); + memset(&prtd->start_cmd, 0, sizeof(struct start_cmd)); + return -EINVAL; + } + if ((prtd->mixer_conf.tx.enable || prtd->mixer_conf.rx.enable) && *no_of_tp == no_of_tp_req) { voc_send_cvp_start_vocpcm(voc_get_session_id(sess_name), @@ -656,6 +663,11 @@ static void hpcm_copy_playback_data_from_queue(struct dai_data *dai_data, struct hpcm_buf_node, list); list_del(&buf_node->list); *len = buf_node->frame.len; + if (*len > HPCM_MAX_VOC_PKT_SIZE) { + pr_err("%s: Playback data len %d overflow\n", + __func__, *len); + return; + } memcpy((u8 *)dai_data->vocpcm_ion_buffer.kvaddr, &buf_node->frame.voc_pkt[0], buf_node->frame.len); @@ -683,6 +695,12 @@ static void hpcm_copy_capture_data_to_queue(struct dai_data *dai_data, if (dai_data->substream == NULL) return; + if (len > HPCM_MAX_VOC_PKT_SIZE) { + pr_err("%s: Copy capture data len %d overflow\n", + __func__, len); + return; + } + /* Copy out buffer packet into free_queue */ spin_lock_irqsave(&dai_data->dsp_lock, dsp_flags); @@ -725,6 +743,13 @@ void hpcm_notify_evt_processing(uint8_t *data, char *session, return; } + if (prtd->mixer_conf.sess_indx < VOICE_INDEX || + prtd->mixer_conf.sess_indx >= MAX_SESSION) { + pr_err("%s:: Invalid session idx %d\n", + __func__, prtd->mixer_conf.sess_indx); + return; + } + if (notify_evt->tap_point == VSS_IVPCM_TAP_POINT_TX_DEFAULT) { tp = &prtd->session[prtd->mixer_conf.sess_indx].tx_tap_point; tmd = &prtd->mixer_conf.tx; diff --git a/techpack/audio/asoc/msm-pcm-q6-noirq.c b/techpack/audio/asoc/msm-pcm-q6-noirq.c index 7338013c7e7c296f643ae0c6353ac72727d6df04..8d9aee8d91d7b94b427c7b3e34e7ace917c78a76 100644 --- a/techpack/audio/asoc/msm-pcm-q6-noirq.c +++ b/techpack/audio/asoc/msm-pcm-q6-noirq.c @@ -153,6 +153,8 @@ static const struct soc_enum msm_pcm_fe_topology_enum[] = { static void event_handler(uint32_t opcode, uint32_t token, uint32_t *payload, void *priv) { + struct msm_audio *prtd = priv; + struct snd_pcm_substream *substream; uint32_t *ptrmem = (uint32_t *)payload; switch (opcode) { @@ -171,6 +173,18 @@ static void event_handler(uint32_t opcode, break; } break; + case RESET_EVENTS: + if (!prtd || !prtd->substream) { + pr_err("%s: prtd or substream is NULL\n", __func__); + return; + } + substream = prtd->substream; + if (!substream->runtime || !substream->runtime->status) { + pr_err("%s: runtime or runtime->status is NULL\n", __func__); + return; + } + substream->runtime->status->state = SNDRV_PCM_STATE_DISCONNECTED; + break; default: pr_debug("Not Supported Event opcode[0x%x]\n", opcode); break; diff --git a/techpack/audio/asoc/msm-pcm-q6-v2.c b/techpack/audio/asoc/msm-pcm-q6-v2.c index bd5001a4683f6403730f3e0388ab1dcbc06d779e..abdc5b23426174e0860506a4aea728c68941a16a 100644 --- a/techpack/audio/asoc/msm-pcm-q6-v2.c +++ b/techpack/audio/asoc/msm-pcm-q6-v2.c @@ -1016,7 +1016,7 @@ static int msm_pcm_capture_copy(struct snd_pcm_substream *substream, goto fail; } - if (size == 0 || size < prtd->pcm_count) { + if ((size == 0 || size < prtd->pcm_count) && ((offset + size) < prtd->pcm_count)) { memset(bufptr + offset + size, 0, prtd->pcm_count - size); if (fbytes > prtd->pcm_count) size = xfer = prtd->pcm_count; diff --git a/techpack/audio/asoc/msm-pcm-routing-v2.c b/techpack/audio/asoc/msm-pcm-routing-v2.c index 41a83e92e3855d3d1f9092be32aecc98e1b7de88..f08bec6a5a46c813422e225a71ae76f0c6598665 100644 --- a/techpack/audio/asoc/msm-pcm-routing-v2.c +++ b/techpack/audio/asoc/msm-pcm-routing-v2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1166,10 +1166,13 @@ int msm_pcm_routing_get_stream_app_type_cfg( EXPORT_SYMBOL(msm_pcm_routing_get_stream_app_type_cfg); static struct cal_block_data *msm_routing_find_topology_by_path(int path, - int cal_index) + int cal_index, + int app_type, + int acdb_id) { struct list_head *ptr, *next; struct cal_block_data *cal_block = NULL; + struct audio_cal_info_adm_top *cal_info; pr_debug("%s\n", __func__); list_for_each_safe(ptr, next, @@ -1180,9 +1183,11 @@ static struct cal_block_data *msm_routing_find_topology_by_path(int path, if (cal_utils_is_cal_stale(cal_block)) continue; - - if (((struct audio_cal_info_adm_top *)cal_block - ->cal_info)->path == path) { + cal_info = (struct audio_cal_info_adm_top *) + cal_block->cal_info; + if ((cal_info->path == path) && + (cal_info->app_type == app_type) && + (cal_info->acdb_id == acdb_id)) { return cal_block; } } @@ -1223,7 +1228,9 @@ static struct cal_block_data *msm_routing_find_topology(int path, "acdb_id %d %s\n", __func__, path, app_type, acdb_id, exact ? "fail" : "defaulting to search by path"); return exact ? NULL : msm_routing_find_topology_by_path(path, - cal_index); + cal_index, + app_type, + acdb_id); } static int msm_routing_find_topology_on_index(int session_type, int app_type, @@ -3487,6 +3494,7 @@ static int msm_pcm_put_out_chs(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { u16 fe_id = 0, out_ch = 0; + fe_id = ((struct soc_multi_mixer_control *) kcontrol->private_value)->shift; out_ch = ucontrol->value.integer.value[0]; @@ -5566,6 +5574,14 @@ static int get_ec_ref_port_id(int value, int *index) *index = 40; port_id = AFE_PORT_ID_QUINARY_TDM_TX; break; + case 41: + *index = 41; + port_id = AFE_PORT_ID_PRIMARY_TDM_RX; + break; + case 42: + *index = 42; + port_id = AFE_PORT_ID_PRIMARY_TDM_TX; + break; default: *index = 0; /* NONE */ pr_err("%s: Invalid value %d\n", __func__, value); @@ -5625,6 +5641,7 @@ static const char *const ec_ref_rx[] = { "None", "SLIM_RX", "I2S_RX", "SLIM_7_RX", "RX_CDC_DMA_RX_0", "RX_CDC_DMA_RX_1", "RX_CDC_DMA_RX_2", "RX_CDC_DMA_RX_3", "TX_CDC_DMA_TX_0", "TERT_TDM_RX_2", "SEC_TDM_TX_0", "DISPLAY_PORT1", "SEN_MI2S_RX", "SENARY_MI2S_TX", "QUIN_TDM_TX_0", + "PRI_TDM_RX_0", "PRI_TDM_TX_0", }; #else #ifndef OPLUS_FEATURE_PLATFORM_LITO @@ -8414,6 +8431,7 @@ static const struct snd_kcontrol_new slimbus_6_rx_mixer_controls[] = { msm_routing_put_audio_mixer), }; +#ifndef CONFIG_CDC_DMA_DISABLE static const struct snd_kcontrol_new wsa_cdc_dma_rx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, @@ -9123,6 +9141,7 @@ static const struct snd_kcontrol_new rx_cdc_dma_rx_7_mixer_controls[] = { MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; +#endif static const struct snd_kcontrol_new slimbus_7_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, @@ -11701,6 +11720,14 @@ static const struct snd_kcontrol_new quat_tdm_tx_0_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, @@ -11713,6 +11740,14 @@ static const struct snd_kcontrol_new quat_tdm_tx_0_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_1_mixer_controls[] = { @@ -11780,6 +11815,14 @@ static const struct snd_kcontrol_new quat_tdm_rx_1_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -11804,6 +11847,14 @@ static const struct snd_kcontrol_new quat_tdm_rx_1_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_2_mixer_controls[] = { @@ -11871,6 +11922,14 @@ static const struct snd_kcontrol_new quat_tdm_rx_2_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -11895,6 +11954,14 @@ static const struct snd_kcontrol_new quat_tdm_rx_2_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_3_mixer_controls[] = { @@ -11962,6 +12029,14 @@ static const struct snd_kcontrol_new quat_tdm_rx_3_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -11986,6 +12061,14 @@ static const struct snd_kcontrol_new quat_tdm_rx_3_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quin_tdm_rx_0_mixer_controls[] = { @@ -12697,6 +12780,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_0_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -12705,6 +12796,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_0_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sen_tdm_tx_0_mixer_controls[] = { @@ -12772,6 +12871,22 @@ static const struct snd_kcontrol_new sen_tdm_tx_0_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sen_tdm_rx_1_mixer_controls[] = { @@ -12839,6 +12954,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_1_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -12847,6 +12970,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_1_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sen_tdm_rx_2_mixer_controls[] = { @@ -12914,6 +13045,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_2_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -12922,6 +13061,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_2_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sen_tdm_rx_3_mixer_controls[] = { @@ -12989,6 +13136,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_3_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -12997,6 +13152,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_3_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_2_voice_mixer_controls[] = { @@ -17802,6 +17965,10 @@ static const struct snd_kcontrol_new mmul8_mixer_controls[] = { MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, @@ -18682,6 +18849,38 @@ static const struct snd_kcontrol_new mmul18_mixer_controls[] = { MSM_BACKEND_DAI_AFE_LOOPBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul19_mixer_controls[] = { @@ -18801,6 +19000,38 @@ static const struct snd_kcontrol_new mmul19_mixer_controls[] = { MSM_BACKEND_DAI_AFE_LOOPBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul20_mixer_controls[] = { @@ -19677,6 +19908,38 @@ static const struct snd_kcontrol_new mmul28_mixer_controls[] = { MSM_BACKEND_DAI_AFE_LOOPBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul29_mixer_controls[] = { @@ -19796,6 +20059,38 @@ static const struct snd_kcontrol_new mmul29_mixer_controls[] = { MSM_BACKEND_DAI_AFE_LOOPBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul30_mixer_controls[] = { @@ -21616,6 +21911,10 @@ static const struct snd_kcontrol_new wsa_cdc_dma_rx_0_port_mixer_controls[] = { MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, @@ -24194,6 +24493,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("SLIM0_UL_HL", "SLIMBUS0_HOSTLESS Capture", 0, 0, 0, 0), +#ifndef CONFIG_CDC_DMA_DISABLE SND_SOC_DAPM_AIF_IN("CDC_DMA_DL_HL", "CDC_DMA_HOSTLESS Playback", 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("CDC_DMA_UL_HL", "CDC_DMA_HOSTLESS Capture", @@ -24210,6 +24510,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_AIF_OUT("TX4_CDC_DMA_UL_HL", "TX4_CDC_DMA_HOSTLESS Capture", 0, 0, 0, 0), #endif /* OPLUS_FEATURE_AUDIO_FTM */ +#endif SND_SOC_DAPM_AIF_OUT("CPE_LSM_UL_HL", "CPE LSM capture", 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("SLIM1_DL_HL", "SLIMBUS1_HOSTLESS Playback", @@ -24303,6 +24604,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("PCM_TX", "AFE Capture", 0, 0, 0, 0), +#ifndef CONFIG_CDC_DMA_DISABLE SND_SOC_DAPM_AIF_OUT("WSA_CDC_DMA_RX_0", "WSA CDC DMA0 Playback", 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("WSA_CDC_DMA_TX_0", "WSA CDC DMA0 Capture", @@ -24347,6 +24649,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("RX_CDC_DMA_RX_7", "RX CDC DMA7 Playback", 0, 0, 0, 0), +#endif /* incall */ SND_SOC_DAPM_AIF_OUT("VOICE_PLAYBACK_TX", "Voice Farend Playback", 0, 0, 0, 0), @@ -24422,12 +24725,14 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { &usb_switch_mixer_controls), SND_SOC_DAPM_SWITCH("A2DP_SLIM7_UL_HL", SND_SOC_NOPM, 0, 0, &a2dp_slim7_switch_mixer_controls), +#ifndef CONFIG_CDC_DMA_DISABLE SND_SOC_DAPM_SWITCH("WSA_CDC_DMA_RX_0_DL_HL", SND_SOC_NOPM, 0, 0, &cdc_dma_wsa_switch_mixer_controls), SND_SOC_DAPM_SWITCH("RX_CDC_DMA_RX_0_DL_HL", SND_SOC_NOPM, 0, 0, &cdc_dma_rx_switch_mixer_controls), SND_SOC_DAPM_SWITCH("RX_CDC_DMA_RX_1_DL_HL", SND_SOC_NOPM, 0, 0, &cdc_dma_rx_1_switch_mixer_controls), +#endif /* Mixer definitions */ SND_SOC_DAPM_MIXER("SLIMBUS_0_RX Audio Mixer", SND_SOC_NOPM, 0, 0, @@ -24452,7 +24757,8 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { pri_spdif_rx_mixer_controls, ARRAY_SIZE(pri_spdif_rx_mixer_controls)), SND_SOC_DAPM_MIXER("SEC_SPDIF_RX Audio Mixer", SND_SOC_NOPM, 0, 0, sec_spdif_rx_mixer_controls, ARRAY_SIZE(sec_spdif_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, +#ifndef CONFIG_CDC_DMA_DISABLE + SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, wsa_cdc_dma_rx_0_mixer_controls, ARRAY_SIZE(wsa_cdc_dma_rx_0_mixer_controls)), SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, @@ -24482,6 +24788,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0, rx_cdc_dma_rx_7_mixer_controls, ARRAY_SIZE(rx_cdc_dma_rx_7_mixer_controls)), +#endif SND_SOC_DAPM_MIXER("MultiMedia1 Mixer", SND_SOC_NOPM, 0, 0, mmul1_mixer_controls, ARRAY_SIZE(mmul1_mixer_controls)), SND_SOC_DAPM_MIXER("MultiMedia2 Mixer", SND_SOC_NOPM, 0, 0, @@ -24561,14 +24868,17 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_NOPM, 0, 0, hdmi_rx_voice_mixer_controls, ARRAY_SIZE(hdmi_rx_voice_mixer_controls)), +#ifndef CONFIG_CDC_DMA_DISABLE SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0_Voice Mixer", SND_SOC_NOPM, 0, 0, wsa_cdc_dma_rx_0_voice_mixer_controls, ARRAY_SIZE(wsa_cdc_dma_rx_0_voice_mixer_controls)), +#endif SND_SOC_DAPM_MIXER("PROXY_RX_Voice Mixer", SND_SOC_NOPM, 0, 0, proxy_rx_voice_mixer_controls, ARRAY_SIZE(proxy_rx_voice_mixer_controls)), +#ifndef CONFIG_CDC_DMA_DISABLE SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_0_Voice Mixer", SND_SOC_NOPM, 0, 0, rx_cdc_dma_rx_0_voice_mixer_controls, @@ -24577,6 +24887,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_NOPM, 0, 0, rx_cdc_dma_rx_1_voice_mixer_controls, ARRAY_SIZE(rx_cdc_dma_rx_1_voice_mixer_controls)), +#endif SND_SOC_DAPM_MIXER("Voip_Tx Mixer", SND_SOC_NOPM, 0, 0, tx_voip_mixer_controls, ARRAY_SIZE(tx_voip_mixer_controls)), @@ -24649,6 +24960,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_MIXER("SLIMBUS_6_RX Port Mixer", SND_SOC_NOPM, 0, 0, sbus_6_rx_port_mixer_controls, ARRAY_SIZE(sbus_6_rx_port_mixer_controls)), +#ifndef CONFIG_CDC_DMA_DISABLE SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, wsa_cdc_dma_rx_0_port_mixer_controls, ARRAY_SIZE(wsa_cdc_dma_rx_0_port_mixer_controls)), @@ -24658,6 +24970,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, rx_cdc_dma_rx_1_port_mixer_controls, ARRAY_SIZE(rx_cdc_dma_rx_1_port_mixer_controls)), +#endif SND_SOC_DAPM_MIXER("QCHAT_Tx Mixer", SND_SOC_NOPM, 0, 0, tx_qchat_mixer_controls, ARRAY_SIZE(tx_qchat_mixer_controls)), @@ -25067,6 +25380,10 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets_mi2s[] = { SND_SOC_NOPM, 0, 0, quin_mi2s_rx_voice_mixer_controls, ARRAY_SIZE(quin_mi2s_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("SEN_MI2S_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + sen_mi2s_rx_voice_mixer_controls, + ARRAY_SIZE(sen_mi2s_rx_voice_mixer_controls)), /* port mixer */ SND_SOC_DAPM_MIXER("SEC_I2S_RX Port Mixer", SND_SOC_NOPM, 0, 0, sec_i2s_rx_port_mixer_controls, @@ -25726,10 +26043,6 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets_tdm[] = { SND_SOC_NOPM, 0, 0, pri_tdm_rx_3_voice_mixer_controls, ARRAY_SIZE(pri_tdm_rx_3_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("SEN_MI2S_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - sen_mi2s_rx_voice_mixer_controls, - ARRAY_SIZE(sen_mi2s_rx_voice_mixer_controls)), SND_SOC_DAPM_MIXER("QUAT_TDM_RX_2_Voice Mixer", SND_SOC_NOPM, 0, 0, quat_tdm_rx_2_voice_mixer_controls, @@ -25904,6 +26217,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"SLIMBUS_5_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, {"SLIMBUS_5_RX", NULL, "SLIMBUS_5_RX Audio Mixer"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, @@ -26093,6 +26407,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia16", "MM_DL16"}, {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia26", "MM_DL26"}, {"RX_CDC_DMA_RX_7", NULL, "RX_CDC_DMA_RX_7 Audio Mixer"}, +#endif {"HDMI Mixer", "MultiMedia1", "MM_DL1"}, {"HDMI Mixer", "MultiMedia2", "MM_DL2"}, @@ -26317,6 +26632,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia1 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, {"MultiMedia8 Mixer", "SLIM_6_TX", "SLIMBUS_6_TX"}, {"MultiMedia8 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"MultiMedia8 Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, {"MultiMedia8 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, {"MultiMedia4 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, {"MultiMedia4 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, @@ -26373,6 +26689,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia6 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, {"MultiMedia1 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia1 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia1 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia1 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26385,10 +26702,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia1 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia1 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia2 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia2 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia2 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia2 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26401,10 +26720,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia2 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia2 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia3 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia3 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia3 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia3 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26417,10 +26738,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia3 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia3 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia4 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia4 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia4 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia4 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26433,10 +26756,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia4 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia4 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia5 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia5 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia5 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia5 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26449,10 +26774,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia5 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia5 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia6 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia6 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia6 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia6 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26465,10 +26792,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia6 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia6 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia8 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia8 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia8 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia8 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26481,10 +26810,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia8 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia8 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia9 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia9 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia9 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia9 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26497,16 +26828,19 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia9 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia9 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia9 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia10 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia20 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, @@ -26515,6 +26849,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia20 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, {"MultiMedia20 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, {"MultiMedia20 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia20 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia20 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia20 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26527,10 +26862,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia20 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia20 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia20 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia21 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia21 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia21 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26543,6 +26880,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia21 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia21 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia21 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, @@ -26570,6 +26908,7 @@ static const struct snd_soc_dapm_route intercon[] = { #endif /* OPLUS_ARCH_EXTENDS */ {"MultiMedia16 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia16 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia16 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia16 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26582,67 +26921,125 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia16 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia16 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia16 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia17 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia18 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia18 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia18 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, +#endif + {"MultiMedia18 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + +#ifndef CONFIG_TDM_DISABLE + {"MultiMedia18 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia18 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia18 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia18 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia18 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia18 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia18 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia18 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, +#endif +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia19 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"MultiMedia19 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia19 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, +#endif + {"MultiMedia19 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + +#ifndef CONFIG_TDM_DISABLE + {"MultiMedia19 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia19 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia19 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia19 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia19 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia19 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia19 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia19 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, +#endif +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia28 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia28 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia28 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, +#endif + {"MultiMedia28 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + +#ifndef CONFIG_TDM_DISABLE + {"MultiMedia28 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia28 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia28 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia28 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia28 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia28 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia28 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia28 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, +#endif +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia29 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia29 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia29 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, +#endif + {"MultiMedia29 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + +#ifndef CONFIG_TDM_DISABLE + {"MultiMedia29 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia29 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia29 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia29 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia29 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia29 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia29 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia29 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, +#endif +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia30 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia30 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia30 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, +#endif + {"MultiMedia30 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, @@ -26840,10 +27237,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"HDMI", NULL, "HDMI_RX_Voice Mixer"}, {"HDMI", NULL, "HDMI_DL_HL"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"WSA_CDC_DMA_RX_0_Voice Mixer", "Voip", "VOIP_DL"}, {"WSA_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, {"WSA_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0_Voice Mixer"}, +#endif {"PROXY_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, {"PROXY_RX", NULL, "PROXY_RX_Voice Mixer"}, @@ -26851,6 +27250,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"PROXY_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, {"PROXY_RX", NULL, "PROXY_RX_Voice Mixer"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"RX_CDC_DMA_RX_0_Voice Mixer", "Voip", "VOIP_DL"}, {"RX_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, {"RX_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, @@ -26860,6 +27260,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"RX_CDC_DMA_RX_1_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, {"RX_CDC_DMA_RX_1_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1_Voice Mixer"}, +#endif {"VOC_EXT_EC MUX", "SLIM_1_TX", "SLIMBUS_1_TX"}, {"VOIP_UL", NULL, "VOC_EXT_EC MUX"}, @@ -26901,12 +27302,14 @@ static const struct snd_soc_dapm_route intercon[] = { {"VoiceMMode1_Tx Mixer", "USB_AUDIO_TX_MMode1", "USB_AUDIO_TX"}, {"VoiceMMode1_Tx Mixer", "INT_BT_SCO_TX_MMode1", "INT_BT_SCO_TX"}, {"VoiceMMode1_Tx Mixer", "AFE_PCM_TX_MMode1", "PCM_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_0_MMode1", "TX_CDC_DMA_TX_0"}, {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_1_MMode1", "TX_CDC_DMA_TX_1"}, {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_2_MMode1", "TX_CDC_DMA_TX_2"}, {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_3_MMode1", "TX_CDC_DMA_TX_3"}, {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_4_MMode1", "TX_CDC_DMA_TX_4"}, {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_5_MMode1", "TX_CDC_DMA_TX_5"}, +#endif {"VoiceMMode1_Tx Mixer", "PROXY_TX_MMode1", "PROXY_TX"}, {"VOICEMMODE1_UL", NULL, "VoiceMMode1_Tx Mixer"}, @@ -26917,12 +27320,14 @@ static const struct snd_soc_dapm_route intercon[] = { {"VoiceMMode2_Tx Mixer", "INT_BT_SCO_TX_MMode2", "INT_BT_SCO_TX"}, {"VoiceMMode2_Tx Mixer", "AFE_PCM_TX_MMode2", "PCM_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_0_MMode2", "TX_CDC_DMA_TX_0"}, {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_1_MMode2", "TX_CDC_DMA_TX_1"}, {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_2_MMode2", "TX_CDC_DMA_TX_2"}, {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_3_MMode2", "TX_CDC_DMA_TX_3"}, {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_4_MMode2", "TX_CDC_DMA_TX_4"}, {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_5_MMode2", "TX_CDC_DMA_TX_5"}, +#endif {"VoiceMMode2_Tx Mixer", "PROXY_TX_MMode2", "PROXY_TX"}, {"VOICEMMODE2_UL", NULL, "VoiceMMode2_Tx Mixer"}, @@ -26934,13 +27339,17 @@ static const struct snd_soc_dapm_route intercon[] = { {"Voip_Tx Mixer", "AFE_PCM_TX_Voip", "PCM_TX"}, {"Voip_Tx Mixer", "PRI_MI2S_TX_Voip", "PRI_MI2S_TX"}, +#ifndef CONFIG_TDM_DISABLE {"Voip_Tx Mixer", "PRI_TDM_TX_3_Voip", "PRI_TDM_TX_3"}, +#endif +#ifndef CONFIG_CDC_DMA_DISABLE {"Voip_Tx Mixer", "TX_CDC_DMA_TX_0_Voip", "TX_CDC_DMA_TX_0"}, {"Voip_Tx Mixer", "TX_CDC_DMA_TX_1_Voip", "TX_CDC_DMA_TX_1"}, {"Voip_Tx Mixer", "TX_CDC_DMA_TX_2_Voip", "TX_CDC_DMA_TX_2"}, {"Voip_Tx Mixer", "TX_CDC_DMA_TX_3_Voip", "TX_CDC_DMA_TX_3"}, {"Voip_Tx Mixer", "TX_CDC_DMA_TX_4_Voip", "TX_CDC_DMA_TX_4"}, {"Voip_Tx Mixer", "TX_CDC_DMA_TX_5_Voip", "TX_CDC_DMA_TX_5"}, +#endif {"VOIP_UL", NULL, "Voip_Tx Mixer"}, {"SLIMBUS_DL_HL", "Switch", "SLIM0_DL_HL"}, @@ -26960,6 +27369,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"SLIM3_UL_HL", NULL, "SLIMBUS_3_TX"}, {"SLIM4_UL_HL", NULL, "SLIMBUS_4_TX"}, {"SLIM8_UL_HL", NULL, "SLIMBUS_8_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"WSA_CDC_DMA_RX_0_DL_HL", "Switch", "CDC_DMA_DL_HL"}, {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0_DL_HL"}, {"CDC_DMA_UL_HL", NULL, "VA_CDC_DMA_TX_0"}, @@ -26971,15 +27381,18 @@ static const struct snd_soc_dapm_route intercon[] = { #ifdef OPLUS_FEATURE_AUDIO_FTM {"TX4_CDC_DMA_UL_HL", NULL, "TX_CDC_DMA_TX_4"}, #endif /* OPLUS_FEATURE_AUDIO_FTM */ +#endif {"LSM1 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, {"LSM1 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, {"LSM1 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM1 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM1 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM1 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM1 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM1 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM1 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM1_UL_HL", NULL, "LSM1 Mixer"}, {"LSM2 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, @@ -26987,10 +27400,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM2 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM2 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM2 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM2 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM2 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM2 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM2 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM2_UL_HL", NULL, "LSM2 Mixer"}, @@ -26999,10 +27414,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM3 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM3 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM3 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM3 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM3 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM3 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM3 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM3_UL_HL", NULL, "LSM3 Mixer"}, @@ -27011,10 +27428,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM4 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM4 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM4 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM4 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM4 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM4 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM4 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM4_UL_HL", NULL, "LSM4 Mixer"}, {"LSM5 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, @@ -27022,10 +27441,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM5 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM5 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM5 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM5 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM5 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM5 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM5 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM5_UL_HL", NULL, "LSM5 Mixer"}, {"LSM6 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, @@ -27033,10 +27454,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM6 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM6 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM6 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM6 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM6 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM6 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM6 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM6_UL_HL", NULL, "LSM6 Mixer"}, {"LSM7 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, @@ -27044,10 +27467,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM7 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM7 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM7 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM7 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM7 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM7 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM7 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM7_UL_HL", NULL, "LSM7 Mixer"}, {"LSM8 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, @@ -27055,10 +27480,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM8 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM8 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM8 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM8 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM8 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM8 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM8 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM8_UL_HL", NULL, "LSM8 Mixer"}, @@ -27083,10 +27510,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"PCM_RX_DL_HL", "Switch", "SLIM0_DL_HL"}, {"PCM_RX", NULL, "PCM_RX_DL_HL"}, +#ifndef CONFIG_CDC_DMA_DISABLE /* connect to INT4_MI2S_DL_HL since same pcm_id */ {"WSA_CDC_DMA_RX_0 Port Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"WSA_CDC_DMA_RX_0 Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"WSA_CDC_DMA_RX_0 Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"WSA_CDC_DMA_RX_0 Port Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0 Port Mixer"}, {"RX_CDC_DMA_RX_0 Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, @@ -27097,6 +27526,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"RX_CDC_DMA_RX_1 Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"RX_CDC_DMA_RX_1 Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1 Port Mixer"}, +#endif {"SLIMBUS_0_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, {"SLIMBUS_0_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, @@ -27130,7 +27560,9 @@ static const struct snd_soc_dapm_route intercon[] = { {"VoLTE Stub Tx Mixer", "STUB_TX_HL", "STUB_TX"}, {"VoLTE Stub Tx Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, {"VoLTE Stub Tx Mixer", "STUB_1_TX_HL", "STUB_1_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE {"VoLTE Stub Tx Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, +#endif {"VoLTE Stub Tx Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, {"VoLTE Stub Tx Mixer", "SLIM_3_TX", "SLIMBUS_3_TX"}, {"VoLTE Stub Tx Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, @@ -27236,6 +27668,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"BE_OUT", NULL, "SLIMBUS_3_RX"}, {"BE_OUT", NULL, "VOICE_PLAYBACK_TX"}, {"BE_OUT", NULL, "VOICE2_PLAYBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"BE_OUT", NULL, "WSA_CDC_DMA_RX_0"}, {"BE_OUT", NULL, "WSA_CDC_DMA_RX_1"}, {"BE_OUT", NULL, "RX_CDC_DMA_RX_0"}, @@ -27246,6 +27679,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"BE_OUT", NULL, "RX_CDC_DMA_RX_5"}, {"BE_OUT", NULL, "RX_CDC_DMA_RX_6"}, {"BE_OUT", NULL, "RX_CDC_DMA_RX_7"}, +#endif {"BE_OUT", NULL, "PROXY_RX"}, {"SLIMBUS_0_TX", NULL, "BE_IN" }, @@ -27265,15 +27699,20 @@ static const struct snd_soc_dapm_route intercon[] = { {"BE_OUT", NULL, "STUB_RX"}, {"STUB_TX", NULL, "BE_IN"}, {"STUB_1_TX", NULL, "BE_IN"}, +#ifndef CONFIG_AUXPCM_DISABLE {"BE_OUT", NULL, "AUX_PCM_RX"}, +#endif {"INCALL_RECORD_TX", NULL, "BE_IN"}, {"INCALL_RECORD_RX", NULL, "BE_IN"}, {"SLIM0_RX_VI_FB_LCH_MUX", "SLIM4_TX", "SLIMBUS_4_TX"}, {"SLIM0_RX_VI_FB_RCH_MUX", "SLIM4_TX", "SLIMBUS_4_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"WSA_RX_0_VI_FB_LCH_MUX", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"WSA_RX_0_VI_FB_RCH_MUX", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, +#endif {"SLIMBUS_0_RX", NULL, "SLIM0_RX_VI_FB_LCH_MUX"}, {"SLIMBUS_0_RX", NULL, "SLIM0_RX_VI_FB_RCH_MUX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"WSA_CDC_DMA_RX_0", NULL, "WSA_RX_0_VI_FB_LCH_MUX"}, {"WSA_CDC_DMA_RX_0", NULL, "WSA_RX_0_VI_FB_RCH_MUX"}, {"WSA_CDC_DMA_TX_0", NULL, "BE_IN"}, @@ -27288,6 +27727,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"TX_CDC_DMA_TX_3", NULL, "BE_IN"}, {"TX_CDC_DMA_TX_4", NULL, "BE_IN"}, {"TX_CDC_DMA_TX_5", NULL, "BE_IN"}, +#endif {"PRI_SPDIF_TX", NULL, "BE_IN"}, {"SEC_SPDIF_TX", NULL, "BE_IN"}, {"PROXY_TX", NULL, "BE_IN"}, @@ -29472,6 +29912,8 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"AUDIO_REF_EC_UL1 MUX", "TERT_MI2S_RX", "TERT_MI2S_RX"}, {"AUDIO_REF_EC_UL1 MUX", "PRI_MI2S_RX", "PRI_MI2S_RX"}, #endif /*OPLUS_ARCH_EXTENDS*/ + {"AUDIO_REF_EC_UL1 MUX", "PRI_TDM_RX_0", "PRI_TDM_RX_0"}, + {"AUDIO_REF_EC_UL1 MUX", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_RX_0", "QUAT_TDM_RX_0"}, @@ -29487,6 +29929,8 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { /* add routing control for AUDIO_REF_EC_UL10 MUX with TERT_MI2S_RX */ {"AUDIO_REF_EC_UL10 MUX", "TERT_MI2S_RX", "TERT_MI2S_RX"}, #endif /* OPLUS_ARCH_EXTENDS */ + {"AUDIO_REF_EC_UL10 MUX", "PRI_TDM_RX_0", "PRI_TDM_RX_0"}, + {"AUDIO_REF_EC_UL10 MUX", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, {"LSM1 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, {"LSM1 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, @@ -30126,12 +30570,14 @@ static const struct snd_soc_dapm_route intercon_mi2s[] = { {"MI2S_UL_HL", NULL, "MI2S_TX"}, /* connect to INT4_MI2S_DL_HL since same pcm_id */ +#ifndef CONFIG_CDC_DMA_DISABLE {"WSA_CDC_DMA_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, {"RX_CDC_DMA_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, #ifdef OPLUS_FEATURE_AUDIO_FTM {"RX_CDC_DMA_RX_0 Port Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, #endif /* OPLUS_FEATURE_AUDIO_FTM */ {"RX_CDC_DMA_RX_1 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif {"SLIMBUS_0_RX Port Mixer", "MI2S_TX", "MI2S_TX"}, {"SLIMBUS_0_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, @@ -31060,6 +31506,50 @@ static const struct snd_kcontrol_new }, }; +static int msm_routing_put_mclk_src_cfg(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + u16 port_id = 0; + int32_t mclk_src_id = 0; + uint32_t mclk_freq = 0; + int be_idx, ret = -EINVAL; + + be_idx = ucontrol->value.integer.value[0]; + mclk_src_id = ucontrol->value.integer.value[1]; + mclk_freq = ucontrol->value.integer.value[2]; + + if (be_idx < 0 || be_idx >= MSM_BACKEND_DAI_MAX) { + pr_err("%s: Invalid be id %d\n", __func__, be_idx); + return -EINVAL; + } + + if (mclk_src_id < MCLK_SRC_INT || mclk_src_id >= MCLK_SRC_MAX) { + pr_err("%s: Invalid MCLK src %d\n", __func__, mclk_src_id); + return -EINVAL; + } + + if (msm_bedais[be_idx].active) { + pr_err("%s:BE is active %d, cannot set mclk clock src\n", + __func__, be_idx); + return -EINVAL; + } + + port_id = msm_bedais[be_idx].port_id; + pr_debug("%s: be idx %d mclk_src id %d mclk_freq %d port id 0x%x\n", + __func__, be_idx, mclk_src_id, mclk_freq, port_id); + ret = afe_set_mclk_src_cfg(port_id, mclk_src_id, mclk_freq); + if (ret < 0) + pr_err("%s: failed to set mclk src cfg\n", __func__); + + return ret; + +} + +static const struct snd_kcontrol_new mclk_src_controls[] = { + SOC_SINGLE_MULTI_EXT("MCLK_SRC CFG", SND_SOC_NOPM, 0, 24576000, 0, 3, + NULL, msm_routing_put_mclk_src_cfg), +}; + static int msm_routing_stereo_channel_reverse_control_get( struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) @@ -31355,6 +31845,8 @@ static int msm_routing_probe(struct snd_soc_component *component) snd_soc_add_component_controls(component, pll_clk_drift_controls, ARRAY_SIZE(pll_clk_drift_controls)); + snd_soc_add_component_controls(component, mclk_src_controls, + ARRAY_SIZE(mclk_src_controls)); return 0; } diff --git a/techpack/audio/asoc/msm-pcm-routing-v2.h b/techpack/audio/asoc/msm-pcm-routing-v2.h index dc761b67fe476d30dc02ac919ddde547f776bcb4..c30cdb54411a05f7910335a6472358420be756d8 100644 --- a/techpack/audio/asoc/msm-pcm-routing-v2.h +++ b/techpack/audio/asoc/msm-pcm-routing-v2.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #ifndef _MSM_PCM_ROUTING_H #define _MSM_PCM_ROUTING_H @@ -212,6 +212,7 @@ #define LPASS_BE_WSA_CDC_DMA_RX_0 "WSA_CDC_DMA_RX_0" #define LPASS_BE_WSA_CDC_DMA_TX_0 "WSA_CDC_DMA_TX_0" +#define LPASS_BE_WSA_CDC_DMA_TX_0_VI "WSA_CDC_DMA_TX_0_VI" #define LPASS_BE_WSA_CDC_DMA_RX_1 "WSA_CDC_DMA_RX_1" #define LPASS_BE_WSA_CDC_DMA_TX_1 "WSA_CDC_DMA_TX_1" #define LPASS_BE_WSA_CDC_DMA_TX_2 "WSA_CDC_DMA_TX_2" diff --git a/techpack/audio/asoc/msm-pcm-voice-v2.c b/techpack/audio/asoc/msm-pcm-voice-v2.c index 5a25b3e860bdb68fc6c9e7e10d86976e12ebd45b..4e7e3da013a1351cd87dc3ac4ce5c708c56863ad 100644 --- a/techpack/audio/asoc/msm-pcm-voice-v2.c +++ b/techpack/audio/asoc/msm-pcm-voice-v2.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, 2021, The Linux Foundation. All rights reserved. */ #include @@ -29,6 +29,8 @@ static struct msm_voice voice_info[VOICE_SESSION_INDEX_MAX]; +static int voice_probe_done; + static struct snd_pcm_hardware msm_pcm_hardware = { .info = (SNDRV_PCM_INFO_INTERLEAVED | @@ -778,6 +780,7 @@ static int msm_pcm_probe(struct platform_device *pdev) bool destroy_cvd = false; const char *is_destroy_cvd = "qcom,destroy-cvd"; + voice_probe_done = 0; if (!is_voc_initialized()) { pr_debug("%s: voice module not initialized yet, deferring probe()\n", __func__); @@ -806,11 +809,31 @@ static int msm_pcm_probe(struct platform_device *pdev) rc = snd_soc_register_component(&pdev->dev, &msm_soc_component, NULL, 0); + if (!rc) { + pr_debug("%s msm_pcm_voice probe success! \n", __func__); + voice_probe_done = 1; + } done: return rc; } +/** + * msm_voice_get_probe_status - Returns the probe + * status of msm-pcm-voice. + * + * Function that returns the probe status of msm-pcm-voice + * driver. + * + * Returns: 1 on probe success, 0 otherwise. + */ +int msm_voice_get_probe_status(void) +{ + return voice_probe_done; +} + +EXPORT_SYMBOL(msm_voice_get_probe_status); + static int msm_pcm_remove(struct platform_device *pdev) { snd_soc_unregister_component(&pdev->dev); diff --git a/techpack/audio/asoc/msm-pcm-voice-v2.h b/techpack/audio/asoc/msm-pcm-voice-v2.h index d300abf9b15bbc08c5ca730d168bdd0a510130ba..7efcad62e27910cce5f7790bed077262ea34b9e0 100644 --- a/techpack/audio/asoc/msm-pcm-voice-v2.h +++ b/techpack/audio/asoc/msm-pcm-voice-v2.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2015, 2021, The Linux Foundation. All rights reserved. */ #ifndef _MSM_PCM_VOICE_H #define _MSM_PCM_VOICE_H @@ -31,4 +31,6 @@ struct msm_voice { int capture_start; }; +int msm_voice_get_probe_status(void); + #endif /*_MSM_PCM_VOICE_H*/ diff --git a/techpack/audio/asoc/msm-pcm-voip-v2.c b/techpack/audio/asoc/msm-pcm-voip-v2.c index e2ad13b4cc6c8b7151d4c1f52b0fbe758dc2d4d7..d2f4e0b654d7659a3c7e24967e535dac72e837b4 100644 --- a/techpack/audio/asoc/msm-pcm-voip-v2.c +++ b/techpack/audio/asoc/msm-pcm-voip-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -365,6 +366,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, switch (prtd->mode) { case MODE_AMR_WB: case MODE_AMR: { + if (pkt_len <= DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* Remove the DSP frame info header. Header format: * Bits 0-3: Frame rate * Bits 4-7: Frame type @@ -385,6 +393,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, case MODE_4GV_NB: case MODE_4GV_WB: case MODE_4GV_NW: { + if (pkt_len <= DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* Remove the DSP frame info header. * Header format: * Bits 0-3: frame rate @@ -422,6 +437,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, buf_node->frame.frm_hdr.timestamp = timestamp; voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN; + if (pkt_len <= 2 * DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* There are two frames in the buffer. Length of the * first frame: */ @@ -457,6 +479,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, buf_node->frame.frm_hdr.timestamp = timestamp; voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN; + if (pkt_len <= 2 * DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* There are two frames in the buffer. Length * of the second frame: */ diff --git a/techpack/audio/asoc/msm8952-dai-links.c b/techpack/audio/asoc/msm8952-dai-links.c new file mode 100644 index 0000000000000000000000000000000000000000..462564d5a835c3a32bb1642623d9947f32f56cc1 --- /dev/null +++ b/techpack/audio/asoc/msm8952-dai-links.c @@ -0,0 +1,1679 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2015-2018, 2020-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "msm8952-slimbus.h" +#include "msm-pcm-routing-v2.h" +#include "codecs/wcd9335.h" + +#define DEV_NAME_STR_LEN 32 + +/* dummy definition of below deprecated FE DAI's*/ +enum { + MSM_FRONTEND_DAI_CS_VOICE = 39, + MSM_FRONTEND_DAI_VOICE2, + MSM_FRONTEND_DAI_VOLTE, + MSM_FRONTEND_DAI_VOWLAN, +}; + +enum TASHA_LITE_DEVICE { + MSM8952_TASHA_LITE = 0, + MSM8953_TASHA_LITE, + NUM_OF_TASHA_LITE_DEVICE, +}; + +static struct snd_soc_card snd_soc_card_msm_card; + +static struct snd_soc_ops msm8952_quat_mi2s_be_ops = { + .startup = msm_quat_mi2s_snd_startup, + .hw_params = msm_mi2s_snd_hw_params, + .shutdown = msm_quat_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm8952_quin_mi2s_be_ops = { + .startup = msm_quin_mi2s_snd_startup, + .hw_params = msm_mi2s_snd_hw_params, + .shutdown = msm_quin_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm_pri_auxpcm_be_ops = { + .startup = msm_prim_auxpcm_startup, + .shutdown = msm_prim_auxpcm_shutdown, +}; + +static struct snd_soc_ops msm8952_slimbus_be_ops = { + .hw_params = msm_snd_hw_params, +}; + + +static struct snd_soc_ops msm8952_cpe_ops = { + .hw_params = msm_snd_cpe_hw_params, +}; + +static struct snd_soc_ops msm8952_slimbus_2_be_ops = { + .hw_params = msm8952_slimbus_2_hw_params, +}; + +static struct snd_soc_ops msm_tdm_be_ops = { + .startup = msm_tdm_startup, + .hw_params = msm_tdm_snd_hw_params, + .shutdown = msm_tdm_shutdown, +}; + +static struct snd_soc_dai_link msm8952_tasha_fe_dai[] = { + /* tasha_vifeedback for speaker protection */ + { + .name = LPASS_BE_SLIMBUS_4_TX, + .stream_name = "Slimbus4 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16393", + .platform_name = "msm-pcm-hostless", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_vifeedback", + .id = MSM_BACKEND_DAI_SLIMBUS_4_TX, + .be_hw_params_fixup = msm_slim_4_tx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + }, + /* Ultrasound RX DAI Link */ + { + .name = "SLIMBUS_2 Hostless Playback", + .stream_name = "SLIMBUS_2 Hostless Playback", + .cpu_dai_name = "msm-dai-q6-dev.16388", + .platform_name = "msm-pcm-hostless", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_rx2", + .ignore_suspend = 1, + .dpcm_playback = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ops = &msm8952_slimbus_2_be_ops, + }, + /* Ultrasound TX DAI Link */ + { + .name = "SLIMBUS_2 Hostless Capture", + .stream_name = "SLIMBUS_2 Hostless Capture", + .cpu_dai_name = "msm-dai-q6-dev.16389", + .platform_name = "msm-pcm-hostless", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_tx2", + .ignore_suspend = 1, + .dpcm_capture = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ops = &msm8952_slimbus_2_be_ops, + }, + /* CPE LSM direct dai-link */ + { + .name = "CPE Listen service", + .stream_name = "CPE Listen Audio Service", + .cpu_dai_name = "msm-dai-slim", + .platform_name = "msm-cpe-lsm", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .dpcm_capture = 1, + .codec_dai_name = "tasha_mad1", + .codec_name = "tasha_codec", + .ops = &msm8952_cpe_ops, + }, + /* slimbus rx 6 hostless */ + { + .name = "SLIMBUS_6 Hostless Playback", + .stream_name = "SLIMBUS_6 Hostless", + .cpu_dai_name = "SLIMBUS6_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dailink has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + /* QCHAT */ + {/* hw:x,42 */ + .name = "QCHAT", + .stream_name = "QCHAT", + .cpu_dai_name = "QCHAT", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_QCHAT, + }, +}; + +static struct snd_soc_dai_link msm8952_tasha_be_dai[] = { + /* Backend DAI Links */ + { + .name = LPASS_BE_SLIMBUS_0_RX, + .stream_name = "Slimbus Playback", + .cpu_dai_name = "msm-dai-q6-dev.16384", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_0_RX, + .init = &msm_audrx_init, + .be_hw_params_fixup = msm_slim_0_rx_be_hw_params_fixup, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm8952_slimbus_be_ops, + }, + { + .name = LPASS_BE_SLIMBUS_0_TX, + .stream_name = "Slimbus Capture", + .cpu_dai_name = "msm-dai-q6-dev.16385", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_tx1", + .dynamic_be = 1, + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_0_TX, + .be_hw_params_fixup = msm_slim_0_tx_be_hw_params_fixup, + .ignore_suspend = 1, + .ops = &msm8952_slimbus_be_ops, + }, + { + .name = LPASS_BE_SLIMBUS_1_RX, + .stream_name = "Slimbus1 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16386", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_1_RX, + .be_hw_params_fixup = msm_slim_0_rx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_1_TX, + .stream_name = "Slimbus1 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16387", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_tx3", + .dynamic_be = 1, + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_1_TX, + .be_hw_params_fixup = msm_slim_1_tx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_3_RX, + .stream_name = "Slimbus3 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16390", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_3_RX, + .be_hw_params_fixup = msm_slim_0_rx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_3_TX, + .stream_name = "Slimbus3 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16391", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_tx1", + .dynamic_be = 1, + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_3_TX, + .be_hw_params_fixup = msm_slim_0_tx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_4_RX, + .stream_name = "Slimbus4 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16392", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_4_RX, + .be_hw_params_fixup = msm_slim_4_rx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_5_RX, + .stream_name = "Slimbus5 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16394", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_rx3", + .dynamic_be = 1, + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_5_RX, + .be_hw_params_fixup = msm_slim_5_rx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + /* MAD BE */ + { + .name = LPASS_BE_SLIMBUS_5_TX, + .stream_name = "Slimbus5 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16395", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mad1", + .dynamic_be = 1, + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_5_TX, + .be_hw_params_fixup = msm_slim_5_tx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_6_RX, + .stream_name = "Slimbus6 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16396", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_rx4", + .dynamic_be = 1, + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_6_RX, + .be_hw_params_fixup = msm_slim_6_rx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm8952_common_fe_dai[] = { + /* FrontEnd DAI Links */ + {/* hw:x,0 */ + .name = "MSM8X16 Media1", + .stream_name = "MultiMedia1", + .cpu_dai_name = "MultiMedia1", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA1 + }, + {/* hw:x,1 */ + .name = "MSM8X16 Media2", + .stream_name = "MultiMedia2", + .cpu_dai_name = "MultiMedia2", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA2, + }, + {/* hw:x,2 */ + .name = "Circuit-Switch Voice", + .stream_name = "CS-Voice", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_CS_VOICE, + }, + {/* hw:x,3 */ + .name = "MSM VoIP", + .stream_name = "VoIP", + .cpu_dai_name = "VoIP", + .platform_name = "msm-voip-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_VOIP, + }, + {/* hw:x,4 */ + .name = "MSM8X16 ULL", + .stream_name = "ULL", + .cpu_dai_name = "MultiMedia3", + .platform_name = "msm-pcm-dsp.2", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA3, + }, + /* Hostless PCM purpose */ + {/* hw:x,5 */ + .name = "SLIMBUS_0 Hostless", + .stream_name = "SLIMBUS_0 Hostless", + .cpu_dai_name = "SLIMBUS0_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* This dai link has MI2S support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,6 */ + .name = "INT_FM Hostless", + .stream_name = "INT_FM Hostless", + .cpu_dai_name = "INT_FM_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,7 */ + .name = "MSM AFE-PCM RX", + .stream_name = "AFE-PROXY RX", + .cpu_dai_name = "msm-dai-q6-dev.241", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .platform_name = "msm-pcm-afe", + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + }, + {/* hw:x,8 */ + .name = "MSM AFE-PCM TX", + .stream_name = "AFE-PROXY TX", + .cpu_dai_name = "msm-dai-q6-dev.240", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .platform_name = "msm-pcm-afe", + .ignore_suspend = 1, + }, + {/* hw:x,9 */ + .name = "MSM8X16 Compress1", + .stream_name = "Compress1", + .cpu_dai_name = "MultiMedia4", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA4, + }, + {/* hw:x,10 */ + .name = "AUXPCM Hostless", + .stream_name = "AUXPCM Hostless", + .cpu_dai_name = "AUXPCM_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,11 */ + .name = "SLIMBUS_1 Hostless", + .stream_name = "SLIMBUS_1 Hostless", + .cpu_dai_name = "SLIMBUS1_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,12 */ + .name = "MSM8952 LowLatency", + .stream_name = "MultiMedia5", + .cpu_dai_name = "MultiMedia5", + .platform_name = "msm-pcm-dsp.1", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA5, + }, + {/* hw:x,13 */ + .name = "Voice2", + .stream_name = "Voice2", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOICE2, + }, + {/* hw:x,14 */ + .name = "MSM8952 Media9", + .stream_name = "MultiMedia9", + .cpu_dai_name = "MultiMedia9", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* This dailink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA9, + }, + { /* hw:x,15 */ + .name = "VoLTE", + .stream_name = "VoLTE", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOLTE, + }, + { /* hw:x,16 */ + .name = "VoWLAN", + .stream_name = "VoWLAN", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOWLAN, + }, + {/* hw:x,17 */ + .name = "INT_HFP_BT Hostless", + .stream_name = "INT_HFP_BT Hostless", + .cpu_dai_name = "INT_HFP_BT_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,18 */ + .name = "MSM8916 HFP", + .stream_name = "MultiMedia6", + .cpu_dai_name = "MultiMedia6", + .platform_name = "msm-pcm-loopback", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA6, + }, + /* LSM FE */ + {/* hw:x,19 */ + .name = "Listen 1 Audio Service", + .stream_name = "Listen 1 Audio Service", + .cpu_dai_name = "LSM1", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM1, + }, + {/* hw:x,20 */ + .name = "Listen 2 Audio Service", + .stream_name = "Listen 2 Audio Service", + .cpu_dai_name = "LSM2", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM2, + }, + {/* hw:x,21 */ + .name = "Listen 3 Audio Service", + .stream_name = "Listen 3 Audio Service", + .cpu_dai_name = "LSM3", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM3, + }, + {/* hw:x,22 */ + .name = "Listen 4 Audio Service", + .stream_name = "Listen 4 Audio Service", + .cpu_dai_name = "LSM4", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM4, + }, + {/* hw:x,23 */ + .name = "Listen 5 Audio Service", + .stream_name = "Listen 5 Audio Service", + .cpu_dai_name = "LSM5", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM5, + }, + {/* hw:x,24 */ + .name = "MSM8X16 Compress2", + .stream_name = "Compress2", + .cpu_dai_name = "MultiMedia7", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA7, + }, + {/* hw:x,25 */ + .name = "SLIMBUS_3 Hostless", + .stream_name = "SLIMBUS_3 Hostless", + .cpu_dai_name = "SLIMBUS3_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,26 */ + .name = "SLIMBUS_4 Hostless", + .stream_name = "SLIMBUS_4 Hostless", + .cpu_dai_name = "SLIMBUS4_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + { /* hw:x,27 */ + .name = "QUAT_MI2S Hostless", + .stream_name = "QUAT_MI2S Hostless", + .cpu_dai_name = "QUAT_MI2S_RX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,28 */ + .name = "MSM8X16 MultiMedia10", + .stream_name = "MultiMedia10", + .cpu_dai_name = "MultiMedia10", + .platform_name = "msm-pcm-dsp.1", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA10, + }, + {/* hw:x,29 */ + .name = "MSM8X16 Compress4", + .stream_name = "Compress4", + .cpu_dai_name = "MultiMedia11", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA11, + }, + {/* hw:x,30 */ + .name = "MSM8X16 Compress5", + .stream_name = "Compress5", + .cpu_dai_name = "MultiMedia12", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA12, + }, + {/* hw:x,31 */ + .name = "MSM8X16 Compress6", + .stream_name = "Compress6", + .cpu_dai_name = "MultiMedia13", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA13, + }, + {/* hw:x,32 */ + .name = "MSM8X16 Compress7", + .stream_name = "Compress7", + .cpu_dai_name = "MultiMedia14", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA14, + }, + {/* hw:x,33 */ + .name = "MSM8X16 Compress8", + .stream_name = "Compress8", + .cpu_dai_name = "MultiMedia15", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA15, + }, + {/* hw:x,34 */ + .name = "MSM8X16 Compress9", + .stream_name = "Compress9", + .cpu_dai_name = "MultiMedia16", + .platform_name = "msm-pcm-dsp-noirq", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA16, + }, + {/* hw:x,35 */ + .name = "VoiceMMode1", + .stream_name = "VoiceMMode1", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOICEMMODE1, + }, + {/* hw:x,36 */ + .name = "VoiceMMode2", + .stream_name = "VoiceMMode2", + .cpu_dai_name = "VoiceMMode2", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOICEMMODE2, + }, + {/* hw:x,37 */ + .name = "MSM8X16 Compress10", + .stream_name = "Compress10", + .cpu_dai_name = "MultiMedia17", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA17, + }, + {/* hw:x,38 */ + .name = "MSM8X16 Compress11", + .stream_name = "Compress11", + .cpu_dai_name = "MultiMedia18", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA18, + }, + {/* hw:x,39 */ + .name = "MSM8X16 Compress12", + .stream_name = "Compress12", + .cpu_dai_name = "MultiMedia19", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA19, + }, +}; + +static struct snd_soc_dai_link msm8952_tdm_fe_dai[] = { + /* FE TDM DAI links */ + { + .name = "Primary TDM RX 0 Hostless", + .stream_name = "Primary TDM RX 0 Hostless", + .cpu_dai_name = "PRI_TDM_RX_0_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + { + .name = "Primary TDM TX 0 Hostless", + .stream_name = "Primary TDM TX 0 Hostless", + .cpu_dai_name = "PRI_TDM_TX_0_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + { + .name = "Secondary TDM RX 0 Hostless", + .stream_name = "Secondary TDM RX 0 Hostless", + .cpu_dai_name = "SEC_TDM_RX_0_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + { + .name = "Secondary TDM TX 0 Hostless", + .stream_name = "Secondary TDM TX 0 Hostless", + .cpu_dai_name = "SEC_TDM_TX_0_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, +}; + +static struct snd_soc_dai_link msm8952_common_be_dai[] = { + /* Backend I2S DAI Links */ + { + .name = LPASS_BE_QUAT_MI2S_RX, + .stream_name = "Quaternary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm8952_quat_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, + /* Primary AUX PCM Backend DAI Links */ + { + .name = LPASS_BE_AUXPCM_RX, + .stream_name = "AUX PCM Playback", + .cpu_dai_name = "msm-dai-q6-auxpcm.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_AUXPCM_RX, + .be_hw_params_fixup = msm_auxpcm_be_params_fixup, + .ops = &msm_pri_auxpcm_be_ops, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AUXPCM_TX, + .stream_name = "AUX PCM Capture", + .cpu_dai_name = "msm-dai-q6-auxpcm.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_AUXPCM_TX, + .be_hw_params_fixup = msm_auxpcm_be_params_fixup, + .ops = &msm_pri_auxpcm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_QUAT_MI2S_TX, + .stream_name = "Quaternary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm8952_quat_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_BT_SCO_RX, + .stream_name = "Internal BT-SCO Playback", + .cpu_dai_name = "msm-dai-q6-dev.12288", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_INT_BT_SCO_RX, + .be_hw_params_fixup = msm_btsco_be_hw_params_fixup, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_BT_SCO_TX, + .stream_name = "Internal BT-SCO Capture", + .cpu_dai_name = "msm-dai-q6-dev.12289", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INT_BT_SCO_TX, + .be_hw_params_fixup = msm_btsco_be_hw_params_fixup, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_FM_RX, + .stream_name = "Internal FM Playback", + .cpu_dai_name = "msm-dai-q6-dev.12292", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_INT_FM_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_FM_TX, + .stream_name = "Internal FM Capture", + .cpu_dai_name = "msm-dai-q6-dev.12293", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INT_FM_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AFE_PCM_RX, + .stream_name = "AFE Playback", + .cpu_dai_name = "msm-dai-q6-dev.224", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_AFE_PCM_RX, + .be_hw_params_fixup = msm_proxy_rx_be_hw_params_fixup, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AFE_PCM_TX, + .stream_name = "AFE Capture", + .cpu_dai_name = "msm-dai-q6-dev.225", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_AFE_PCM_TX, + .be_hw_params_fixup = msm_proxy_tx_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Record Uplink BACK END DAI Link */ + { + .name = LPASS_BE_INCALL_RECORD_TX, + .stream_name = "Voice Uplink Capture", + .cpu_dai_name = "msm-dai-q6-dev.32772", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INCALL_RECORD_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Record Downlink BACK END DAI Link */ + { + .name = LPASS_BE_INCALL_RECORD_RX, + .stream_name = "Voice Downlink Capture", + .cpu_dai_name = "msm-dai-q6-dev.32771", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INCALL_RECORD_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Music BACK END DAI Link */ + { + .name = LPASS_BE_VOICE_PLAYBACK_TX, + .stream_name = "Voice Farend Playback", + .cpu_dai_name = "msm-dai-q6-dev.32773", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + /* Incall Music 2 BACK END DAI Link */ + { + .name = LPASS_BE_VOICE2_PLAYBACK_TX, + .stream_name = "Voice2 Farend Playback", + .cpu_dai_name = "msm-dai-q6-dev.32770", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + + { + .name = LPASS_BE_QUIN_MI2S_TX, + .stream_name = "Quinary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.5", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm8952_quin_mi2s_be_ops, + .ignore_suspend = 1, + }, + /* Proxy Tx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_TX, + .stream_name = "Proxy Capture", + .cpu_dai_name = "msm-dai-q6-dev.8195", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_PROXY_TX, + .ignore_suspend = 1, + }, + /* Proxy Rx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_RX, + .stream_name = "Proxy Playback", + .cpu_dai_name = "msm-dai-q6-dev.8194", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_PROXY_RX, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm8952_hdmi_dba_dai_link[] = { + { + .name = LPASS_BE_QUIN_MI2S_RX, + .stream_name = "Quinary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.5", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "msm_hdmi_dba_codec_rx_dai", + .codec_name = "msm-hdmi-dba-codec-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX, + .be_hw_params_fixup = msm_quin_be_hw_params_fixup, + .ops = &msm8952_quin_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm8952_quin_dai_link[] = { + { + .name = LPASS_BE_QUIN_MI2S_RX, + .stream_name = "Quinary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.5", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX, + .be_hw_params_fixup = msm_quin_be_hw_params_fixup, + .ops = &msm8952_quin_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm8952_tdm_be_dai_link[] = { + /* TDM be dai links */ + { + .name = LPASS_BE_PRI_TDM_RX_0, + .stream_name = "Primary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36864", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_PRI_TDM_RX_0, + .be_hw_params_fixup = msm_tdm_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_PRI_TDM_TX_0, + .stream_name = "Primary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36865", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_PRI_TDM_TX_0, + .be_hw_params_fixup = msm_tdm_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SEC_TDM_RX_0, + .stream_name = "Secondary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36880", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SEC_TDM_RX_0, + .be_hw_params_fixup = msm_tdm_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SEC_TDM_TX_0, + .stream_name = "Secondary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36881", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_SEC_TDM_TX_0, + .be_hw_params_fixup = msm_tdm_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, +}; + +struct msm895x_wsa881x_dev_info { + struct device_node *of_node; + u32 index; +}; + +static struct snd_soc_aux_dev *msm895x_aux_dev; +static struct snd_soc_codec_conf *msm895x_codec_conf; + +static struct snd_soc_dai_link msm8952_tasha_dai_links[ +ARRAY_SIZE(msm8952_common_fe_dai) + +ARRAY_SIZE(msm8952_tasha_fe_dai) + +ARRAY_SIZE(msm8952_tdm_fe_dai) + +ARRAY_SIZE(msm8952_common_be_dai) + +ARRAY_SIZE(msm8952_tasha_be_dai) + +ARRAY_SIZE(msm8952_hdmi_dba_dai_link) + +ARRAY_SIZE(msm8952_tdm_be_dai_link)]; + +int msm8952_init_wsa_dev(struct platform_device *pdev, + struct snd_soc_card *card) +{ + struct device_node *wsa_of_node; + u32 wsa_max_devs; + u32 wsa_dev_cnt; + char *dev_name_str = NULL; + struct msm895x_wsa881x_dev_info *wsa881x_dev_info; + const char *wsa_auxdev_name_prefix[1]; + int found = 0; + int i; + int ret; + + /* Get maximum WSA device count for this platform */ + ret = of_property_read_u32(pdev->dev.of_node, + "qcom,wsa-max-devs", &wsa_max_devs); + if (ret) { + dev_dbg(&pdev->dev, + "%s: wsa-max-devs property missing in DT %s, ret = %d\n", + __func__, pdev->dev.of_node->full_name, ret); + card->num_aux_devs = 0; + return 0; + } + if (wsa_max_devs == 0) { + dev_warn(&pdev->dev, + "%s: Max WSA devices is 0 for this target?\n", + __func__); + card->num_aux_devs = 0; + return 0; + } + + /* Get count of WSA device phandles for this platform */ + wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node, + "qcom,wsa-devs", NULL); + if (wsa_dev_cnt == -ENOENT) { + dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n", + __func__); + return 0; + } else if (wsa_dev_cnt <= 0) { + dev_err(&pdev->dev, + "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n", + __func__, wsa_dev_cnt); + return -EINVAL; + } + + /* + * Expect total phandles count to be NOT less than maximum possible + * WSA count. However, if it is less, then assign same value to + * max count as well. + */ + + if (wsa_dev_cnt < wsa_max_devs) { + dev_dbg(&pdev->dev, + "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n", + __func__, wsa_max_devs, wsa_dev_cnt); + wsa_max_devs = wsa_dev_cnt; + } + + /* Make sure prefix string passed for each WSA device */ + ret = of_property_count_strings(pdev->dev.of_node, + "qcom,wsa-aux-dev-prefix"); + if (ret != wsa_dev_cnt) { + dev_err(&pdev->dev, + "%s: expecting %d wsa prefix. Defined only %d in DT\n", + __func__, wsa_dev_cnt, ret); + return -EINVAL; + } + + /* + * Alloc mem to store phandle and index info of WSA device, if already + * registered with ALSA core + */ + wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs, + sizeof(struct msm895x_wsa881x_dev_info), + GFP_KERNEL); + if (!wsa881x_dev_info) + return -ENOMEM; + + /* + * search and check whether all WSA devices are already + * registered with ALSA core or not. If found a node, store + * the node and the index in a local array of struct for later + * use. + */ + for (i = 0; i < wsa_dev_cnt; i++) { + wsa_of_node = of_parse_phandle(pdev->dev.of_node, + "qcom,wsa-devs", i); + if (unlikely(!wsa_of_node)) { + /* we should not be here */ + dev_err(&pdev->dev, + "%s: wsa dev node is not present\n", + __func__); + ret = -EINVAL; + goto err_free_dev_info; + } + if (soc_find_component(wsa_of_node, NULL)) { + /* WSA device registered with ALSA core */ + wsa881x_dev_info[found].of_node = wsa_of_node; + wsa881x_dev_info[found].index = i; + found++; + if (found == wsa_max_devs) + break; + } + } + + if (found < wsa_max_devs) { + dev_dbg(&pdev->dev, + "%s: failed to find %d components. Found only %d\n", + __func__, wsa_max_devs, found); + return -EPROBE_DEFER; + } + dev_info(&pdev->dev, + "%s: found %d wsa881x devices registered with ALSA core\n", + __func__, found); + + card->num_aux_devs = wsa_max_devs; + card->num_configs = wsa_max_devs; + + /* Alloc array of AUX devs struct */ + msm895x_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs, + sizeof(struct snd_soc_aux_dev), + GFP_KERNEL); + if (!msm895x_aux_dev) { + ret = -ENOMEM; + goto err_free_dev_info; + } + + /* Alloc array of codec conf struct */ + msm895x_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs, + sizeof(struct snd_soc_codec_conf), + GFP_KERNEL); + if (!msm895x_codec_conf) { + ret = -ENOMEM; + goto err_free_aux_dev; + } + + for (i = 0; i < card->num_aux_devs; i++) { + dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN, + GFP_KERNEL); + if (!dev_name_str) { + ret = -ENOMEM; + goto err_free_cdc_conf; + } + + ret = of_property_read_string_index(pdev->dev.of_node, + "qcom,wsa-aux-dev-prefix", + wsa881x_dev_info[i].index, + wsa_auxdev_name_prefix); + if (ret) { + dev_err(&pdev->dev, + "%s: failed to read wsa aux dev prefix, ret = %d\n", + __func__, ret); + ret = -EINVAL; + goto err_free_dev_name_str; + } + + snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i); + msm895x_aux_dev[i].name = dev_name_str; + msm895x_aux_dev[i].codec_name = NULL; + msm895x_aux_dev[i].codec_of_node = + wsa881x_dev_info[i].of_node; + msm895x_aux_dev[i].init = msm895x_wsa881x_init; + msm895x_codec_conf[i].dev_name = NULL; + msm895x_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0]; + msm895x_codec_conf[i].of_node = + wsa881x_dev_info[i].of_node; + } + card->codec_conf = msm895x_codec_conf; + card->aux_dev = msm895x_aux_dev; + + return 0; +err_free_dev_name_str: + devm_kfree(&pdev->dev, dev_name_str); +err_free_cdc_conf: + devm_kfree(&pdev->dev, msm895x_codec_conf); +err_free_aux_dev: + devm_kfree(&pdev->dev, msm895x_aux_dev); +err_free_dev_info: + devm_kfree(&pdev->dev, wsa881x_dev_info); + + return ret; +} + +struct snd_soc_card *populate_snd_card_dailinks(struct device *dev) +{ + struct snd_soc_card *card = &snd_soc_card_msm_card; + struct snd_soc_dai_link *msm8952_dai_links = NULL; + int num_links, ret, len1, len2, len3, len4, len5 = 0; + enum codec_variant codec_ver = 0; + const char *tasha_lite[NUM_OF_TASHA_LITE_DEVICE] = { + "msm8952-tashalite-snd-card", + "msm8953-tashalite-snd-card" + }; + + card->dev = dev; + ret = snd_soc_of_parse_card_name(card, "qcom,model"); + if (ret) { + dev_err(dev, "%s: parse card name failed, err:%d\n", + __func__, ret); + return NULL; + } + if (strnstr(card->name, "tasha", strlen(card->name))) { + codec_ver = tasha_codec_ver(); + if (codec_ver == WCD9XXX) + return NULL; + if (codec_ver == WCD9326) { + if (!strcmp(card->name, "msm8952-tasha-snd-card")) + card->name = tasha_lite[MSM8952_TASHA_LITE]; + else if (!strcmp(card->name, "msm8953-tasha-snd-card")) + card->name = tasha_lite[MSM8953_TASHA_LITE]; + } + + len1 = ARRAY_SIZE(msm8952_common_fe_dai); + len2 = len1 + ARRAY_SIZE(msm8952_tasha_fe_dai); + len3 = len2 + ARRAY_SIZE(msm8952_tdm_fe_dai); + len4 = len3 + ARRAY_SIZE(msm8952_common_be_dai); + len5 = len4 + ARRAY_SIZE(msm8952_tasha_be_dai); + snd_soc_card_msm_card.name = card->name; + card = &snd_soc_card_msm_card; + num_links = ARRAY_SIZE(msm8952_tasha_dai_links); + memcpy(msm8952_tasha_dai_links, msm8952_common_fe_dai, + sizeof(msm8952_common_fe_dai)); + memcpy(msm8952_tasha_dai_links + len1, + msm8952_tasha_fe_dai, sizeof(msm8952_tasha_fe_dai)); + memcpy(msm8952_tasha_dai_links + len2, + msm8952_tdm_fe_dai, sizeof(msm8952_tdm_fe_dai)); + memcpy(msm8952_tasha_dai_links + len3, + msm8952_common_be_dai, sizeof(msm8952_common_be_dai)); + memcpy(msm8952_tasha_dai_links + len4, + msm8952_tasha_be_dai, sizeof(msm8952_tasha_be_dai)); + msm8952_dai_links = msm8952_tasha_dai_links; + } + if (of_property_read_bool(dev->of_node, "qcom,hdmi-dba-codec-rx")) { + dev_dbg(dev, "%s(): hdmi dba audio support present\n", + __func__); + memcpy(msm8952_dai_links + len5, msm8952_hdmi_dba_dai_link, + sizeof(msm8952_hdmi_dba_dai_link)); + len5 += ARRAY_SIZE(msm8952_hdmi_dba_dai_link); + } else { + dev_dbg(dev, "%s(): No hdmi dba present, add quin dai\n", + __func__); + memcpy(msm8952_dai_links + len5, msm8952_quin_dai_link, + sizeof(msm8952_quin_dai_link)); + len5 += ARRAY_SIZE(msm8952_quin_dai_link); + } + if (of_property_read_bool(dev->of_node, "qcom,tdm-audio-intf")) { + dev_dbg(dev, "%s(): TDM support present\n", + __func__); + memcpy(msm8952_dai_links + len5, msm8952_tdm_be_dai_link, + sizeof(msm8952_tdm_be_dai_link)); + len5 += ARRAY_SIZE(msm8952_tdm_be_dai_link); + } + card->dai_link = msm8952_dai_links; + card->num_links = len5; + card->dev = dev; + return card; +} + +void msm895x_free_auxdev_mem(struct platform_device *pdev) +{ + struct snd_soc_card *card = platform_get_drvdata(pdev); + int i; + + if (card->num_aux_devs > 0) { + for (i = 0; i < card->num_aux_devs; i++) { + kfree(msm895x_aux_dev[i].codec_name); + kfree(msm895x_codec_conf[i].dev_name); + kfree(msm895x_codec_conf[i].name_prefix); + } + } +} diff --git a/techpack/audio/asoc/msm8952-slimbus.c b/techpack/audio/asoc/msm8952-slimbus.c new file mode 100644 index 0000000000000000000000000000000000000000..9fa6d6af53e70ea550c3e45e4621e03911f46f86 --- /dev/null +++ b/techpack/audio/asoc/msm8952-slimbus.c @@ -0,0 +1,3845 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2015-2018, 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "msm-pcm-routing-v2.h" +#include +#include "codecs/wcd9335.h" +#include +#include "codecs/wsa881x.h" +#include "msm8952-slimbus.h" + +#define DRV_NAME "msm8952-slimbus-wcd" + +#define BTSCO_RATE_8KHZ 8000 +#define BTSCO_RATE_16KHZ 16000 +#define SAMPLING_RATE_8KHZ 8000 +#define SAMPLING_RATE_16KHZ 16000 +#define SAMPLING_RATE_32KHZ 32000 +#define SAMPLING_RATE_48KHZ 48000 +#define SAMPLING_RATE_96KHZ 96000 +#define SAMPLING_RATE_192KHZ 192000 +#define SAMPLING_RATE_44P1KHZ 44100 + +#define MSM8952_SPK_ON 1 +#define MSM8952_SPK_OFF 0 + +#define WCD9XXX_MBHC_DEF_BUTTONS 8 +#define WCD9XXX_MBHC_DEF_RLOADS 5 +#define CODEC_EXT_CLK_RATE 9600000 + +#define PRI_MI2S_ID (1 << 0) +#define SEC_MI2S_ID (1 << 1) +#define TER_MI2S_ID (1 << 2) +#define QUAT_MI2S_ID (1 << 3) +#define QUIN_MI2S_ID (1 << 4) + +#define HS_STARTWORK_TIMEOUT 4000 + +#define Q6AFE_LPASS_OSR_CLK_9_P600_MHZ 0x927C00 +#define MAX_AUX_CODECS 4 + +#define WSA8810_NAME_1 "wsa881x.20170211" +#define WSA8810_NAME_2 "wsa881x.20170212" + +#define TDM_SLOT_OFFSET_MAX 8 + +enum btsco_rates { + RATE_8KHZ_ID, + RATE_16KHZ_ID, +}; + +enum { + PRIMARY_TDM_RX_0, + PRIMARY_TDM_TX_0, + SECONDARY_TDM_RX_0, + SECONDARY_TDM_TX_0, + TDM_MAX, +}; + +static int slim0_rx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim0_tx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim1_tx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim2_tx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim0_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int slim0_tx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int slim1_tx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int slim2_tx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int msm_slim_0_rx_ch = 1; +static int msm_slim_0_tx_ch = 1; +static int msm_slim_1_tx_ch = 1; +static int msm_slim_2_tx_ch = 1; +static int msm_vi_feed_tx_ch = 2; +static int msm_slim_5_rx_ch = 1; +static int msm_slim_6_rx_ch = 1; +static int slim5_rx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim5_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int slim6_rx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim6_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int msm8952_auxpcm_rate = SAMPLING_RATE_8KHZ; +static int slim4_rx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim4_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int msm_slim_4_rx_ch = 1; +static int msm_btsco_rate = SAMPLING_RATE_8KHZ; +static int msm_btsco_ch = 1; +static int msm8952_spk_control = 1; + +static bool codec_reg_done; + +static int mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + +static int msm_proxy_rx_ch = 2; +static void *adsp_state_notifier; + +/* TDM default channels */ +static int msm_pri_tdm_rx_0_ch = 8; +static int msm_pri_tdm_tx_0_ch = 8; + +static int msm_sec_tdm_rx_0_ch = 8; +static int msm_sec_tdm_tx_0_ch = 8; + +/* TDM default bit format */ +static int msm_pri_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int msm_pri_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; + +static int msm_sec_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int msm_sec_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; + +/* TDM default sampling rate */ +static int msm_pri_tdm_rx_0_sample_rate = SAMPLING_RATE_48KHZ; +static int msm_pri_tdm_tx_0_sample_rate = SAMPLING_RATE_48KHZ; + +static int msm_sec_tdm_rx_0_sample_rate = SAMPLING_RATE_48KHZ; +static int msm_sec_tdm_tx_0_sample_rate = SAMPLING_RATE_48KHZ; + +static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", "Eight"}; +static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE", + "S32_LE"}; +static char const *tdm_sample_rate_text[] = {"KHZ_16", "KHZ_48"}; + +/* TDM default offset */ +static unsigned int tdm_slot_offset[TDM_MAX][TDM_SLOT_OFFSET_MAX] = { + /* PRI_TDM_RX */ + {0, 4, 8, 12, 16, 20, 24, 28}, + /* PRI_TDM_TX */ + {0, 4, 8, 12, 16, 20, 24, 28}, + /* SEC_TDM_RX */ + {0, 4, 8, 12, 16, 20, 24, 28}, + /* SEC_TDM_TX */ + {0, 4, 8, 12, 16, 20, 24, 28}, +}; + +static int msm8952_enable_codec_mclk(struct snd_soc_component *component, + int enable, bool dapm); + +static struct wcd_mbhc_config wcd_mbhc_cfg = { + .read_fw_bin = false, + .calibration = NULL, + .detect_extn_cable = true, + .mono_stero_detection = false, + .swap_gnd_mic = NULL, + .hs_ext_micbias = true, + .key_code[0] = KEY_MEDIA, + .key_code[1] = KEY_VOICECOMMAND, + .key_code[2] = KEY_VOLUMEUP, + .key_code[3] = KEY_VOLUMEDOWN, + .key_code[4] = 0, + .key_code[5] = 0, + .key_code[6] = 0, + .key_code[7] = 0, + .linein_th = 5000, +}; + +static void *def_tasha_mbhc_cal(void) +{ + void *tasha_wcd_cal; + struct wcd_mbhc_btn_detect_cfg *btn_cfg; + u16 *btn_high; + + tasha_wcd_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS, + WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL); + if (!tasha_wcd_cal) + return NULL; + +#define S(X, Y) ((WCD_MBHC_CAL_PLUG_TYPE_PTR(tasha_wcd_cal)->X) = (Y)) + S(v_hs_max, 1500); +#undef S +#define S(X, Y) ((WCD_MBHC_CAL_BTN_DET_PTR(tasha_wcd_cal)->X) = (Y)) + S(num_btn, WCD_MBHC_DEF_BUTTONS); +#undef S + + btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(tasha_wcd_cal); + btn_high = ((void *)&btn_cfg->_v_btn_low) + + (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn); + + btn_high[0] = 75; + btn_high[1] = 150; + btn_high[2] = 237; + btn_high[3] = 450; + btn_high[4] = 450; + btn_high[5] = 450; + btn_high[6] = 450; + btn_high[7] = 450; + + return tasha_wcd_cal; +} + +static struct afe_clk_set mi2s_tx_clk = { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, +}; + +static struct afe_clk_set mi2s_rx_clk = { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, +}; + +struct msm895x_auxcodec_prefix_map { + char codec_name[50]; + char codec_prefix[25]; +}; + +static inline int param_is_mask(int p) +{ + return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) && + (p <= SNDRV_PCM_HW_PARAM_LAST_MASK); +} + +static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p, int n) +{ + return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]); +} + +int msm895x_wsa881x_init(struct snd_soc_component *component) +{ + u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {100, 101, 102, 106}; + u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {103, 104, 105, 107}; + unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200}; + unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3}; + struct msm8952_asoc_mach_data *pdata; + struct snd_soc_dapm_context *dapm; + + if (!component) { + pr_err("%s component is NULL\n", __func__); + return -EINVAL; + } + dapm = snd_soc_component_get_dapm(component); + + if (!strcmp(component->name_prefix, "SpkrLeft")) { + dev_dbg(component->dev, "%s: setting left ch map to codec %s\n", + __func__, component->name); + wsa881x_set_channel_map(component, &spkleft_ports[0], + WSA881X_MAX_SWR_PORTS, &ch_mask[0], + &ch_rate[0], NULL); + if (dapm->component) { + snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN"); + snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR"); + } + } else if (!strcmp(component->name_prefix, "SpkrRight")) { + dev_dbg(component->dev, "%s: setting right ch map to codec %s\n", + __func__, component->name); + wsa881x_set_channel_map(component, &spkright_ports[0], + WSA881X_MAX_SWR_PORTS, &ch_mask[0], + &ch_rate[0], NULL); + if (dapm->component) { + snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN"); + snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR"); + } + } else { + dev_err(component->dev, "%s: wrong codec name %s\n", __func__, + component->name); + return -EINVAL; + } + + + pdata = snd_soc_card_get_drvdata(component->card); + if (pdata && pdata->codec_root) + wsa881x_codec_info_create_codec_entry(pdata->codec_root, + component); + return 0; +} + +static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned int bit) +{ + if (bit >= SNDRV_MASK_MAX) + return; + if (param_is_mask(n)) { + struct snd_mask *m = param_to_mask(p, n); + + m->bits[0] = 0; + m->bits[1] = 0; + m->bits[bit >> 5] |= (1 << (bit & 31)); + } +} + +static void msm8952_ext_control(struct snd_soc_component *codec) +{ + struct snd_soc_dapm_context *dapm = + snd_soc_component_get_dapm(codec); + + pr_debug("%s: msm8952_spk_control = %d\n", + __func__, msm8952_spk_control); + if (msm8952_spk_control == MSM8952_SPK_ON) { + snd_soc_dapm_enable_pin(dapm, "Lineout_1 amp"); + snd_soc_dapm_enable_pin(dapm, "Lineout_3 amp"); + } else { + snd_soc_dapm_disable_pin(dapm, "Lineout_1 amp"); + snd_soc_dapm_disable_pin(dapm, "Lineout_3 amp"); + } + snd_soc_dapm_sync(dapm); +} + +static int msm8952_get_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm8952_spk_control = %d\n", + __func__, msm8952_spk_control); + ucontrol->value.integer.value[0] = msm8952_spk_control; + return 0; +} + +static int msm8952_set_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + + pr_debug("%s()\n", __func__); + if (msm8952_spk_control == ucontrol->value.integer.value[0]) + return 0; + + msm8952_spk_control = ucontrol->value.integer.value[0]; + msm8952_ext_control(component); + return 1; +} + + +static int msm8952_enable_codec_mclk(struct snd_soc_component *component, + int enable, bool dapm) +{ + int ret; + + pr_debug("%s: enable = %d\n", __func__, enable); + if (!strcmp(dev_name(component->dev), "tasha_codec")) + ret = tasha_cdc_mclk_enable(component, enable, dapm); + else { + dev_err(component->dev, "%s: unknown codec to enable ext clk\n", + __func__); + ret = -EINVAL; + } + return ret; +} + +static int slim5_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (slim5_rx_sample_rate) { + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 3; + break; + + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: slim5_rx_sample_rate = %d\n", __func__, + slim5_rx_sample_rate); + + return 0; +} + +static int slim5_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: ucontrol value = %ld\n", __func__, + ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 3: + slim5_rx_sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 2: + slim5_rx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 1: + slim5_rx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 0: + default: + slim5_rx_sample_rate = SAMPLING_RATE_48KHZ; + } + + pr_debug("%s: slim5_rx_sample_rate = %d\n", __func__, + slim5_rx_sample_rate); + + return 0; +} + +static int mi2s_rx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + + switch (mi2s_rx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: mi2s_rx_bit_format = %d, ucontrol value = %ld\n", + __func__, mi2s_rx_bit_format, + ucontrol->value.integer.value[0]); + + return 0; +} + +static int mi2s_rx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 2: + mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + return 0; +} + +static int msm_slim_1_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_1_tx_ch = %d\n", __func__, + msm_slim_1_tx_ch); + ucontrol->value.integer.value[0] = msm_slim_1_tx_ch - 1; + return 0; +} + +static int msm_slim_1_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_1_tx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_slim_1_tx_ch = %d\n", __func__, msm_slim_1_tx_ch); + return 1; +} + +static int slim0_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (slim0_rx_sample_rate) { + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 3; + break; + + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: slim0_rx_sample_rate = %d\n", __func__, + slim0_rx_sample_rate); + + return 0; +} + +static int slim0_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: ucontrol value = %ld\n", __func__, + ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 3: + slim0_rx_sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 2: + slim0_rx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 1: + slim0_rx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 0: + default: + slim0_rx_sample_rate = SAMPLING_RATE_48KHZ; + } + + pr_debug("%s: slim0_rx_sample_rate = %d\n", __func__, + slim0_rx_sample_rate); + + return 0; +} + +static int slim4_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (slim4_rx_sample_rate) { + case SAMPLING_RATE_16KHZ: + sample_rate_val = 4; + break; + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 3; + break; + + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: slim4_rx_sample_rate = %d\n", __func__, + slim4_rx_sample_rate); + + return 0; +} + +static int slim4_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: ucontrol value = %ld\n", __func__, + ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 4: + slim4_rx_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 3: + slim4_rx_sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 2: + slim4_rx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 1: + slim4_rx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 0: + default: + slim4_rx_sample_rate = SAMPLING_RATE_48KHZ; + } + + pr_debug("%s: slim4_rx_sample_rate = %d\n", __func__, + slim4_rx_sample_rate); + + return 0; +} + +static int slim5_rx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + + switch (slim5_rx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: slim5_rx_bit_format = %d, ucontrol value = %ld\n", + __func__, slim5_rx_bit_format, + ucontrol->value.integer.value[0]); + + return 0; +} + +static int slim5_rx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 2: + slim5_rx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + slim5_rx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + slim5_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + return 0; +} +static int slim6_rx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + + switch (slim6_rx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: slim6_rx_bit_format = %d, ucontrol value = %ld\n", + __func__, slim6_rx_bit_format, + ucontrol->value.integer.value[0]); + + return 0; +} + +static int slim6_rx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 2: + slim6_rx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + slim6_rx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + slim6_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + return 1; +} +static int slim6_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (slim6_rx_sample_rate) { + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 3; + break; + + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: slim6_rx_sample_rate = %d\n", __func__, + slim6_rx_sample_rate); + + return 0; +} + +static int slim6_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 3: + slim6_rx_sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 2: + slim6_rx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 1: + slim6_rx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 0: + default: + slim6_rx_sample_rate = SAMPLING_RATE_48KHZ; + break; + } + + pr_debug("%s: ucontrol value = %ld, slim6_rx_sample_rate = %d\n", + __func__, ucontrol->value.integer.value[0], + slim6_rx_sample_rate); + + return 1; +} + +static int slim0_rx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + + switch (slim0_rx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: slim0_rx_bit_format = %d, ucontrol value = %ld\n", + __func__, slim0_rx_bit_format, + ucontrol->value.integer.value[0]); + + return 0; +} + +static int slim0_rx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 2: + slim0_rx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + slim0_rx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + slim0_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + return 0; +} + +static int slim4_rx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + + switch (slim4_rx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: slim4_rx_bit_format = %d, ucontrol value = %ld\n", + __func__, slim4_rx_bit_format, + ucontrol->value.integer.value[0]); + + return 0; +} + +static int slim4_rx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 2: + slim4_rx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + slim4_rx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + slim4_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + return 0; +} + +static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + + if (!strcmp(dev_name(component->dev), "tasha_codec")) + ucontrol->value.integer.value[0] = + (msm_vi_feed_tx_ch - 1); + else + ucontrol->value.integer.value[0] = + (msm_vi_feed_tx_ch/2 - 1); + + pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__, + ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + + if (!strcmp(dev_name(component->dev), "tasha_codec")) + msm_vi_feed_tx_ch = + ucontrol->value.integer.value[0] + 1; + else + msm_vi_feed_tx_ch = + roundup_pow_of_two( + ucontrol->value.integer.value[0] + 2); + + pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch); + return 1; +} + +static int msm_slim_0_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_0_rx_ch = %d\n", __func__, + msm_slim_0_rx_ch); + ucontrol->value.integer.value[0] = msm_slim_0_rx_ch - 1; + return 0; +} + +static int msm_slim_0_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_0_rx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_slim_0_rx_ch = %d\n", __func__, + msm_slim_0_rx_ch); + return 1; +} + +static int msm_slim_4_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_4_rx_ch = %d\n", __func__, + msm_slim_4_rx_ch); + ucontrol->value.integer.value[0] = msm_slim_4_rx_ch - 1; + return 0; +} + +static int msm_slim_4_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_4_rx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_slim_4_rx_ch = %d\n", __func__, + msm_slim_4_rx_ch); + return 1; +} + +static int slim0_tx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (slim0_tx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: slim0_tx_bit_format = %d, ucontrol value = %ld\n", + __func__, slim0_tx_bit_format, + ucontrol->value.integer.value[0]); + return 0; +} + +static int slim0_tx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int rc = 0; + + switch (ucontrol->value.integer.value[0]) { + case 2: + slim0_tx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + slim0_tx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + slim0_tx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + default: + pr_err("%s: invalid value %ld\n", __func__, + ucontrol->value.integer.value[0]); + rc = -EINVAL; + break; + } + return rc; +} + +static int slim2_tx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (slim2_tx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: slim2_tx_bit_format = %d, ucontrol value = %ld\n", + __func__, slim2_tx_bit_format, + ucontrol->value.integer.value[0]); + return 0; +} + +static int slim2_tx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int rc = 0; + + switch (ucontrol->value.integer.value[0]) { + case 2: + slim2_tx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + slim2_tx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + slim2_tx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + default: + pr_err("%s: invalid value %ld\n", __func__, + ucontrol->value.integer.value[0]); + rc = -EINVAL; + break; + } + return rc; +} + +static int msm_slim_5_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_5_rx_ch = %d\n", __func__, + msm_slim_5_rx_ch); + ucontrol->value.integer.value[0] = msm_slim_5_rx_ch - 1; + return 0; +} + +static int msm_slim_5_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_5_rx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_slim_0_rx_ch = %d\n", __func__, + msm_slim_5_rx_ch); + return 0; +} +static int msm_slim_6_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_6_rx_ch = %d\n", __func__, + msm_slim_6_rx_ch); + ucontrol->value.integer.value[0] = msm_slim_6_rx_ch - 1; + return 0; +} + +static int msm_slim_6_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_6_rx_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_slim_6_rx_ch = %d\n", __func__, + msm_slim_6_rx_ch); + return 1; +} + +static int msm_slim_0_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_0_tx_ch = %d\n", __func__, + msm_slim_0_tx_ch); + ucontrol->value.integer.value[0] = msm_slim_0_tx_ch - 1; + return 0; +} + +static int msm_slim_0_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_0_tx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_slim_0_tx_ch = %d\n", __func__, msm_slim_0_tx_ch); + return 1; +} + +static int msm_slim_2_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_2_tx_ch = %d\n", __func__, + msm_slim_2_tx_ch); + ucontrol->value.integer.value[0] = msm_slim_2_tx_ch - 1; + return 0; +} + +static int msm_slim_2_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_2_tx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_slim_2_tx_ch = %d\n", __func__, msm_slim_2_tx_ch); + return 1; +} + +static int slim0_tx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (slim0_tx_sample_rate) { + case SAMPLING_RATE_16KHZ: + sample_rate_val = 4; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: slim0_tx_sample_rate = %d\n", __func__, + slim0_tx_sample_rate); + return 0; + +} + +static int slim0_tx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int rc = 0; + + pr_debug("%s: ucontrol value = %ld\n", __func__, + ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 4: + slim0_tx_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 2: + slim0_tx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 1: + slim0_tx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 0: + slim0_tx_sample_rate = SAMPLING_RATE_48KHZ; + break; + default: + rc = -EINVAL; + pr_err("%s: invalid sample rate being passed\n", __func__); + break; + } + pr_debug("%s: slim0_tx_sample_rate = %d\n", __func__, + slim0_tx_sample_rate); + return rc; +} + +static int slim2_tx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (slim2_tx_sample_rate) { + case SAMPLING_RATE_16KHZ: + sample_rate_val = 4; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: slim2_tx_sample_rate = %d\n", __func__, + slim2_tx_sample_rate); + return 0; + +} + +static int slim2_tx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int rc = 0; + + pr_debug("%s: ucontrol value = %ld\n", __func__, + ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 4: + slim2_tx_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 2: + slim2_tx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 1: + slim2_tx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 0: + slim2_tx_sample_rate = SAMPLING_RATE_48KHZ; + break; + default: + rc = -EINVAL; + pr_err("%s: invalid sample rate being passed\n", __func__); + break; + } + pr_debug("%s: slim2_tx_sample_rate = %d\n", __func__, + slim2_tx_sample_rate); + return rc; +} + +static int msm_btsco_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_btsco_rate = %d", __func__, msm_btsco_rate); + ucontrol->value.integer.value[0] = msm_btsco_rate; + return 0; +} + +static int msm_btsco_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case RATE_8KHZ_ID: + msm_btsco_rate = BTSCO_RATE_8KHZ; + break; + case RATE_16KHZ_ID: + msm_btsco_rate = BTSCO_RATE_16KHZ; + break; + default: + msm_btsco_rate = BTSCO_RATE_8KHZ; + break; + } + + pr_debug("%s: msm_btsco_rate = %d\n", __func__, msm_btsco_rate); + return 0; +} + +static int msm_auxpcm_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_auxpcm_rate = %d", __func__, msm8952_auxpcm_rate); + ucontrol->value.integer.value[0] = msm8952_auxpcm_rate; + return 0; +} + +static int msm_auxpcm_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case RATE_8KHZ_ID: + msm8952_auxpcm_rate = SAMPLING_RATE_8KHZ; + break; + case RATE_16KHZ_ID: + msm8952_auxpcm_rate = SAMPLING_RATE_16KHZ; + break; + default: + msm8952_auxpcm_rate = SAMPLING_RATE_8KHZ; + break; + } + + pr_debug("%s: msm_auxpcm_rate = %d\n", __func__, msm8952_auxpcm_rate); + return 0; +} + +static int msm_proxy_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_proxy_rx_ch = %d\n", __func__, + msm_proxy_rx_ch); + ucontrol->value.integer.value[0] = msm_proxy_rx_ch - 1; + return 0; +} + +static int msm_proxy_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_proxy_rx_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_proxy_rx_ch = %d\n", __func__, + msm_proxy_rx_ch); + return 1; +} + +static int msm_pri_tdm_rx_0_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_pri_tdm_rx_0_ch = %d\n", __func__, + msm_pri_tdm_rx_0_ch); + ucontrol->value.integer.value[0] = msm_pri_tdm_rx_0_ch - 1; + return 0; +} + +static int msm_pri_tdm_rx_0_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_pri_tdm_rx_0_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_pri_tdm_rx_0_ch = %d\n", __func__, + msm_pri_tdm_rx_0_ch); + return 0; +} + +static int msm_pri_tdm_tx_0_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_pri_tdm_tx_0_ch = %d\n", __func__, + msm_pri_tdm_tx_0_ch); + ucontrol->value.integer.value[0] = msm_pri_tdm_tx_0_ch - 1; + return 0; +} + +static int msm_pri_tdm_tx_0_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_pri_tdm_tx_0_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_pri_tdm_tx_0_ch = %d\n", __func__, + msm_pri_tdm_tx_0_ch); + return 0; +} + +static int msm_sec_tdm_rx_0_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_sec_tdm_rx_0_ch = %d\n", __func__, + msm_sec_tdm_rx_0_ch); + ucontrol->value.integer.value[0] = msm_sec_tdm_rx_0_ch - 1; + return 0; +} + +static int msm_sec_tdm_rx_0_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_sec_tdm_rx_0_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_sec_tdm_rx_0_ch = %d\n", __func__, + msm_sec_tdm_rx_0_ch); + return 0; +} + +static int msm_sec_tdm_tx_0_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_sec_tdm_tx_0_ch = %d\n", __func__, + msm_sec_tdm_tx_0_ch); + ucontrol->value.integer.value[0] = msm_sec_tdm_tx_0_ch - 1; + return 0; +} + +static int msm_sec_tdm_tx_0_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_sec_tdm_tx_0_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_sec_tdm_tx_0_ch = %d\n", __func__, + msm_sec_tdm_tx_0_ch); + return 0; +} + +static int msm_pri_tdm_rx_0_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_pri_tdm_rx_0_bit_format) { + case SNDRV_PCM_FORMAT_S32_LE: + ucontrol->value.integer.value[0] = 3; + break; + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: msm_pri_tdm_rx_0_bit_format = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_pri_tdm_rx_0_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 3: + msm_pri_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S32_LE; + break; + case 2: + msm_pri_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + msm_pri_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + msm_pri_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + pr_debug("%s: msm_pri_tdm_rx_0_bit_format = %d\n", + __func__, msm_pri_tdm_rx_0_bit_format); + return 0; +} + +static int msm_pri_tdm_tx_0_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_pri_tdm_tx_0_bit_format) { + case SNDRV_PCM_FORMAT_S32_LE: + ucontrol->value.integer.value[0] = 3; + break; + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: msm_pri_tdm_tx_0_bit_format = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_pri_tdm_tx_0_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 3: + msm_pri_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S32_LE; + break; + case 2: + msm_pri_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + msm_pri_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + msm_pri_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + pr_debug("%s: msm_pri_tdm_tx_0_bit_format = %d\n", + __func__, msm_pri_tdm_tx_0_bit_format); + return 0; +} + +static int msm_sec_tdm_rx_0_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_sec_tdm_rx_0_bit_format) { + case SNDRV_PCM_FORMAT_S32_LE: + ucontrol->value.integer.value[0] = 3; + break; + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: msm_sec_tdm_rx_0_bit_format = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_sec_tdm_rx_0_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 3: + msm_sec_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S32_LE; + break; + case 2: + msm_sec_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + msm_sec_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + msm_sec_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + pr_debug("%s: msm_sec_tdm_rx_0_bit_format = %d\n", + __func__, msm_sec_tdm_rx_0_bit_format); + return 0; +} + +static int msm_sec_tdm_tx_0_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_sec_tdm_tx_0_bit_format) { + case SNDRV_PCM_FORMAT_S32_LE: + ucontrol->value.integer.value[0] = 3; + break; + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: msm_sec_tdm_tx_0_bit_format = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_sec_tdm_tx_0_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 3: + msm_sec_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S32_LE; + break; + case 2: + msm_sec_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + msm_sec_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + msm_sec_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + pr_debug("%s: msm_sec_tdm_tx_0_bit_format = %d\n", + __func__, msm_sec_tdm_tx_0_bit_format); + return 0; +} + +static int msm_pri_tdm_rx_0_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_pri_tdm_rx_0_sample_rate) { + case SAMPLING_RATE_16KHZ: + ucontrol->value.integer.value[0] = 0; + break; + case SAMPLING_RATE_48KHZ: + default: + ucontrol->value.integer.value[0] = 1; + break; + } + pr_debug("%s: msm_pri_tdm_rx_0_sample_rate = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_pri_tdm_rx_0_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 0: + msm_pri_tdm_rx_0_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 1: + default: + msm_pri_tdm_rx_0_sample_rate = SAMPLING_RATE_48KHZ; + break; + } + pr_debug("%s: msm_pri_tdm_rx_0_sample_rate = %d\n", + __func__, msm_pri_tdm_rx_0_sample_rate); + return 0; +} + +static int msm_sec_tdm_rx_0_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_sec_tdm_rx_0_sample_rate) { + case SAMPLING_RATE_16KHZ: + ucontrol->value.integer.value[0] = 0; + break; + case SAMPLING_RATE_48KHZ: + default: + ucontrol->value.integer.value[0] = 1; + break; + } + pr_debug("%s: msm_sec_tdm_rx_0_sample_rate = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_sec_tdm_rx_0_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 0: + msm_sec_tdm_rx_0_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 1: + default: + msm_sec_tdm_rx_0_sample_rate = SAMPLING_RATE_48KHZ; + break; + } + pr_debug("%s: msm_sec_tdm_rx_0_sample_rate = %d\n", + __func__, msm_sec_tdm_rx_0_sample_rate); + return 0; +} + +static int msm_pri_tdm_tx_0_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_pri_tdm_tx_0_sample_rate) { + case SAMPLING_RATE_16KHZ: + ucontrol->value.integer.value[0] = 0; + break; + case SAMPLING_RATE_48KHZ: + default: + ucontrol->value.integer.value[0] = 1; + break; + } + pr_debug("%s: msm_pri_tdm_tx_0_sample_rate = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_pri_tdm_tx_0_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 0: + msm_pri_tdm_tx_0_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 1: + default: + msm_pri_tdm_tx_0_sample_rate = SAMPLING_RATE_48KHZ; + break; + } + pr_debug("%s: msm_pri_tdm_tx_0_sample_rate = %d\n", + __func__, msm_pri_tdm_tx_0_sample_rate); + return 0; +} + +static int msm_sec_tdm_tx_0_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_sec_tdm_tx_0_sample_rate) { + case SAMPLING_RATE_16KHZ: + ucontrol->value.integer.value[0] = 0; + break; + case SAMPLING_RATE_48KHZ: + default: + ucontrol->value.integer.value[0] = 1; + break; + } + pr_debug("%s: msm_sec_tdm_tx_0_sample_rate = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_sec_tdm_tx_0_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 0: + msm_sec_tdm_tx_0_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 1: + default: + msm_sec_tdm_tx_0_sample_rate = SAMPLING_RATE_48KHZ; + break; + } + pr_debug("%s: msm_sec_tdm_tx_0_sample_rate = %d\n", + __func__, msm_sec_tdm_tx_0_sample_rate); + return 0; +} + +static const char *const spk_function[] = {"Off", "On"}; +static const char *const slim0_rx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static const char *const slim4_rx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static const char *const slim0_tx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static const char *const slim2_tx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static const char *const slim4_tx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static const char *const vi_feed_ch_text[] = {"One", "Two"}; +static char const *rx_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; +static char const *slim0_rx_sample_rate_text[] = {"KHZ_48", "KHZ_96", + "KHZ_192", "KHZ_44P1", "KHZ_16"}; +static char const *slim4_rx_sample_rate_text[] = {"KHZ_48", "KHZ_96", + "KHZ_192", "KHZ_44P1", "KHZ_16"}; +static const char *const slim5_rx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static const char *const slim6_rx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static char const *slim5_rx_sample_rate_text[] = {"KHZ_48", "KHZ_96", + "KHZ_192", "KHZ_44P1"}; +static char const *slim6_rx_sample_rate_text[] = {"KHZ_48", "KHZ_96", + "KHZ_192", "KHZ_44P1"}; +static char const *slim4_rx_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; +static char const *slim5_rx_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; +static const char *const proxy_rx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", "Eight"}; +static char const *slim6_rx_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; + +static const struct soc_enum msm_snd_enum[] = { + SOC_ENUM_SINGLE_EXT(2, spk_function), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim0_rx_ch_text), slim0_rx_ch_text), + SOC_ENUM_SINGLE_EXT(8, slim0_tx_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_bit_format_text), + rx_bit_format_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim0_rx_sample_rate_text), + slim0_rx_sample_rate_text), + SOC_ENUM_SINGLE_EXT(2, vi_feed_ch_text), + SOC_ENUM_SINGLE_EXT(4, slim5_rx_sample_rate_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim5_rx_bit_format_text), + slim5_rx_bit_format_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim5_rx_ch_text), slim5_rx_ch_text), + SOC_ENUM_SINGLE_EXT(8, proxy_rx_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim6_rx_sample_rate_text), + slim6_rx_sample_rate_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim6_rx_bit_format_text), + slim6_rx_bit_format_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim6_rx_ch_text), slim6_rx_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tdm_ch_text), + tdm_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tdm_bit_format_text), + tdm_bit_format_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tdm_sample_rate_text), + tdm_sample_rate_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim4_rx_ch_text), slim4_rx_ch_text), + SOC_ENUM_SINGLE_EXT(8, slim2_tx_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim4_rx_sample_rate_text), + slim4_rx_sample_rate_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim4_rx_bit_format_text), + slim4_rx_bit_format_text), +}; + +static const char *const btsco_rate_text[] = {"BTSCO_RATE_8KHZ", + "BTSCO_RATE_16KHZ"}; +static const struct soc_enum msm_btsco_enum[] = { + SOC_ENUM_SINGLE_EXT(2, btsco_rate_text), +}; + +static const char *const auxpcm_rate_text[] = {"SAMPLING_RATE_8KHZ", + "SAMPLING_RATE_16KHZ"}; +static const struct soc_enum msm_auxpcm_enum[] = { + SOC_ENUM_SINGLE_EXT(2, auxpcm_rate_text), +}; + +static const struct snd_kcontrol_new msm_snd_controls[] = { + SOC_ENUM_EXT("Speaker Function", msm_snd_enum[0], msm8952_get_spk, + msm8952_set_spk), + SOC_ENUM_EXT("SLIM_0_RX Channels", msm_snd_enum[1], + msm_slim_0_rx_ch_get, msm_slim_0_rx_ch_put), + SOC_ENUM_EXT("SLIM_4_RX Channels", msm_snd_enum[16], + msm_slim_4_rx_ch_get, msm_slim_4_rx_ch_put), + SOC_ENUM_EXT("SLIM_5_RX Channels", msm_snd_enum[8], + msm_slim_5_rx_ch_get, msm_slim_5_rx_ch_put), + SOC_ENUM_EXT("SLIM_6_RX Channels", msm_snd_enum[12], + msm_slim_6_rx_ch_get, msm_slim_6_rx_ch_put), + SOC_ENUM_EXT("SLIM_0_TX Channels", msm_snd_enum[2], + msm_slim_0_tx_ch_get, msm_slim_0_tx_ch_put), + SOC_ENUM_EXT("SLIM_1_TX Channels", msm_snd_enum[2], + msm_slim_1_tx_ch_get, msm_slim_1_tx_ch_put), + SOC_ENUM_EXT("SLIM_2_TX Channels", msm_snd_enum[17], + msm_slim_2_tx_ch_get, msm_slim_2_tx_ch_put), + SOC_ENUM_EXT("MI2S_RX Format", msm_snd_enum[3], + mi2s_rx_bit_format_get, mi2s_rx_bit_format_put), + SOC_ENUM_EXT("SLIM_0_RX Format", msm_snd_enum[3], + slim0_rx_bit_format_get, slim0_rx_bit_format_put), + SOC_ENUM_EXT("SLIM_4_RX Format", msm_snd_enum[19], + slim4_rx_bit_format_get, slim4_rx_bit_format_put), + SOC_ENUM_EXT("SLIM_5_RX Format", msm_snd_enum[7], + slim5_rx_bit_format_get, slim5_rx_bit_format_put), + SOC_ENUM_EXT("SLIM_6_RX Format", msm_snd_enum[11], + slim6_rx_bit_format_get, slim6_rx_bit_format_put), + SOC_ENUM_EXT("SLIM_0_RX SampleRate", msm_snd_enum[4], + slim0_rx_sample_rate_get, slim0_rx_sample_rate_put), + SOC_ENUM_EXT("SLIM_4_RX SampleRate", msm_snd_enum[18], + slim4_rx_sample_rate_get, slim4_rx_sample_rate_put), + SOC_ENUM_EXT("SLIM_5_RX SampleRate", msm_snd_enum[6], + slim5_rx_sample_rate_get, slim5_rx_sample_rate_put), + SOC_ENUM_EXT("SLIM_6_RX SampleRate", msm_snd_enum[10], + slim6_rx_sample_rate_get, slim6_rx_sample_rate_put), + SOC_ENUM_EXT("VI_FEED_TX Channels", msm_snd_enum[5], + msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put), + SOC_ENUM_EXT("SLIM_0_TX SampleRate", msm_snd_enum[4], + slim0_tx_sample_rate_get, slim0_tx_sample_rate_put), + SOC_ENUM_EXT("SLIM_0_TX Format", msm_snd_enum[3], + slim0_tx_bit_format_get, slim0_tx_bit_format_put), + SOC_ENUM_EXT("SLIM_2_TX SampleRate", msm_snd_enum[4], + slim2_tx_sample_rate_get, slim2_tx_sample_rate_put), + SOC_ENUM_EXT("SLIM_2_TX Format", msm_snd_enum[3], + slim2_tx_bit_format_get, slim2_tx_bit_format_put), + SOC_ENUM_EXT("Internal BTSCO SampleRate", msm_btsco_enum[0], + msm_btsco_rate_get, msm_btsco_rate_put), + SOC_ENUM_EXT("AUXPCM SampleRate", msm_auxpcm_enum[0], + msm_auxpcm_rate_get, msm_auxpcm_rate_put), + SOC_ENUM_EXT("PROXY_RX Channels", msm_snd_enum[9], + msm_proxy_rx_ch_get, msm_proxy_rx_ch_put), + SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", msm_snd_enum[13], + msm_pri_tdm_rx_0_ch_get, msm_pri_tdm_rx_0_ch_put), + SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", msm_snd_enum[13], + msm_pri_tdm_tx_0_ch_get, msm_pri_tdm_tx_0_ch_put), + SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", msm_snd_enum[13], + msm_sec_tdm_rx_0_ch_get, msm_sec_tdm_rx_0_ch_put), + SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", msm_snd_enum[13], + msm_sec_tdm_tx_0_ch_get, msm_sec_tdm_tx_0_ch_put), + SOC_ENUM_EXT("PRI_TDM_RX_0 Bit Format", msm_snd_enum[14], + msm_pri_tdm_rx_0_bit_format_get, + msm_pri_tdm_rx_0_bit_format_put), + SOC_ENUM_EXT("PRI_TDM_TX_0 Bit Format", msm_snd_enum[14], + msm_pri_tdm_tx_0_bit_format_get, + msm_pri_tdm_tx_0_bit_format_put), + SOC_ENUM_EXT("SEC_TDM_RX_0 Bit Format", msm_snd_enum[14], + msm_sec_tdm_rx_0_bit_format_get, + msm_sec_tdm_rx_0_bit_format_put), + SOC_ENUM_EXT("SEC_TDM_TX_0 Bit Format", msm_snd_enum[14], + msm_sec_tdm_tx_0_bit_format_get, + msm_sec_tdm_tx_0_bit_format_put), + SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", msm_snd_enum[15], + msm_pri_tdm_rx_0_sample_rate_get, + msm_pri_tdm_rx_0_sample_rate_put), + SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", msm_snd_enum[15], + msm_pri_tdm_tx_0_sample_rate_get, + msm_pri_tdm_tx_0_sample_rate_put), + SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", msm_snd_enum[15], + msm_sec_tdm_rx_0_sample_rate_get, + msm_sec_tdm_rx_0_sample_rate_put), + SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", msm_snd_enum[15], + msm_sec_tdm_tx_0_sample_rate_get, + msm_sec_tdm_tx_0_sample_rate_put), +}; + +int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + rate->min = rate->max = 48000; + channels->min = channels->max = 2; + + return 0; +} + +int msm_quin_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + rate->min = rate->max = 48000; + channels->min = channels->max = 2; + + return 0; +} + +int msm_auxpcm_be_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + rate->min = rate->max = msm8952_auxpcm_rate; + channels->min = channels->max = 1; + + return 0; +} + +int msm_btsco_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + rate->min = rate->max = msm_btsco_rate; + channels->min = channels->max = msm_btsco_ch; + + return 0; +} + +int msm_proxy_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s: msm_proxy_rx_ch =%d\n", __func__, msm_proxy_rx_ch); + + if (channels->max < 2) + channels->min = channels->max = 2; + channels->min = channels->max = msm_proxy_rx_ch; + rate->min = rate->max = 48000; + return 0; +} + +int msm_proxy_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + rate->min = rate->max = 48000; + return 0; +} + +int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + switch (cpu_dai->id) { + case AFE_PORT_ID_PRIMARY_TDM_RX: + channels->min = channels->max = msm_pri_tdm_rx_0_ch; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + msm_pri_tdm_rx_0_bit_format); + rate->min = rate->max = msm_pri_tdm_rx_0_sample_rate; + break; + case AFE_PORT_ID_PRIMARY_TDM_TX: + channels->min = channels->max = msm_pri_tdm_tx_0_ch; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + msm_pri_tdm_tx_0_bit_format); + rate->min = rate->max = msm_pri_tdm_tx_0_sample_rate; + break; + case AFE_PORT_ID_SECONDARY_TDM_RX: + channels->min = channels->max = msm_sec_tdm_rx_0_ch; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + msm_sec_tdm_rx_0_bit_format); + rate->min = rate->max = msm_sec_tdm_rx_0_sample_rate; + break; + case AFE_PORT_ID_SECONDARY_TDM_TX: + channels->min = channels->max = msm_sec_tdm_tx_0_ch; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + msm_sec_tdm_tx_0_bit_format); + rate->min = rate->max = msm_sec_tdm_tx_0_sample_rate; + break; + default: + pr_err("%s: dai id 0x%x not supported\n", + __func__, cpu_dai->id); + return -EINVAL; + } + + pr_debug("%s: dai id = 0x%x channels = %d rate = %d\n", + __func__, cpu_dai->id, channels->max, rate->max); + + return 0; +} + +static unsigned int tdm_param_set_slot_mask(u16 port_id, + int slot_width, int slots) +{ + unsigned int slot_mask = 0; + int upper, lower, i, j; + unsigned int *slot_offset; + + switch (port_id) { + case AFE_PORT_ID_PRIMARY_TDM_RX: + lower = PRIMARY_TDM_RX_0; + upper = PRIMARY_TDM_RX_0; + break; + case AFE_PORT_ID_PRIMARY_TDM_TX: + lower = PRIMARY_TDM_TX_0; + upper = PRIMARY_TDM_TX_0; + break; + case AFE_PORT_ID_SECONDARY_TDM_RX: + lower = SECONDARY_TDM_RX_0; + upper = SECONDARY_TDM_RX_0; + break; + case AFE_PORT_ID_SECONDARY_TDM_TX: + lower = SECONDARY_TDM_TX_0; + upper = SECONDARY_TDM_TX_0; + break; + default: + return slot_mask; + } + + for (i = lower; i <= upper; i++) { + slot_offset = tdm_slot_offset[i]; + for (j = 0; j < TDM_SLOT_OFFSET_MAX; j++) { + if (slot_offset[j] != AFE_SLOT_MAPPING_OFFSET_INVALID) + /* + * set the mask of active slot according to + * the offset table for the group of devices + */ + slot_mask |= + (1 << ((slot_offset[j] * 8) / slot_width)); + else + break; + } + } + + return slot_mask; +} + +int msm_tdm_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret = 0; + int channels, slot_width, slots; + unsigned int slot_mask; + unsigned int *slot_offset; + int offset_channels = 0; + int i; + + pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id); + + channels = params_channels(params); + switch (channels) { + case 1: + case 2: + case 3: + case 4: + case 6: + case 8: + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S32_LE: + case SNDRV_PCM_FORMAT_S24_LE: + case SNDRV_PCM_FORMAT_S16_LE: + /* + * up to 8 channel HW configuration should + * use 32 bit slot width for max support of + * stream bit width. (slot_width > bit_width) + */ + slot_width = 32; + break; + default: + pr_err("%s: invalid param format 0x%x\n", + __func__, params_format(params)); + return -EINVAL; + } + slots = 8; + slot_mask = tdm_param_set_slot_mask(cpu_dai->id, + slot_width, slots); + if (!slot_mask) { + pr_err("%s: invalid slot_mask 0x%x\n", + __func__, slot_mask); + return -EINVAL; + } + break; + default: + pr_err("%s: invalid param channels %d\n", + __func__, channels); + return -EINVAL; + } + + switch (cpu_dai->id) { + case AFE_PORT_ID_PRIMARY_TDM_RX: + slot_offset = tdm_slot_offset[PRIMARY_TDM_RX_0]; + break; + case AFE_PORT_ID_PRIMARY_TDM_TX: + slot_offset = tdm_slot_offset[PRIMARY_TDM_TX_0]; + break; + case AFE_PORT_ID_SECONDARY_TDM_RX: + slot_offset = tdm_slot_offset[SECONDARY_TDM_RX_0]; + break; + case AFE_PORT_ID_SECONDARY_TDM_TX: + slot_offset = tdm_slot_offset[SECONDARY_TDM_TX_0]; + break; + default: + pr_err("%s: dai id 0x%x not supported\n", + __func__, cpu_dai->id); + return -EINVAL; + } + + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID) + offset_channels++; + else + break; + } + + if (offset_channels == 0) { + pr_err("%s: slot offset not supported, offset_channels %d\n", + __func__, offset_channels); + return -EINVAL; + } + + if (channels > offset_channels) { + pr_err("%s: channels %d exceed offset_channels %d\n", + __func__, channels, offset_channels); + return -EINVAL; + } + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask, + slots, slot_width); + if (ret < 0) { + pr_err("%s: failed to set tdm slot, err:%d\n", + __func__, ret); + goto end; + } + + ret = snd_soc_dai_set_channel_map(cpu_dai, + 0, NULL, channels, slot_offset); + if (ret < 0) { + pr_err("%s: failed to set channel map, err:%d\n", + __func__, ret); + goto end; + } + } else { + ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0, + slots, slot_width); + if (ret < 0) { + pr_err("%s: failed to set tdm slot, err:%d\n", + __func__, ret); + goto end; + } + + ret = snd_soc_dai_set_channel_map(cpu_dai, + channels, slot_offset, 0, NULL); + if (ret < 0) { + pr_err("%s: failed to set channel map, err:%d\n", + __func__, ret); + goto end; + } + } + +end: + return ret; +} + +int msm_mi2s_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, mi2s_rx_bit_format); + return 0; +} + +int msm_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_dai_link *dai_link = rtd->dai_link; + + int ret = 0; + u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS]; + u32 rx_ch_cnt = 0, tx_ch_cnt = 0; + u32 user_set_tx_ch = 0; + u32 rx_ch_count; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret < 0) { + pr_err("%s: failed to get codec chan map, err:%d\n", + __func__, ret); + goto end; + } + if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_RX) { + pr_debug("%s: rx_4_ch=%d\n", __func__, + msm_slim_4_rx_ch); + rx_ch_count = msm_slim_4_rx_ch; + } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) { + pr_debug("%s: rx_5_ch=%d\n", __func__, + msm_slim_5_rx_ch); + rx_ch_count = msm_slim_5_rx_ch; + } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) { + pr_debug("%s: rx_6_ch=%d\n", __func__, + msm_slim_6_rx_ch); + rx_ch_count = msm_slim_6_rx_ch; + } else { + pr_debug("%s: rx_0_ch=%d\n", __func__, + msm_slim_0_rx_ch); + rx_ch_count = msm_slim_0_rx_ch; + } + ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0, + rx_ch_count, rx_ch); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto end; + } + } else { + pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__, + codec_dai->name, codec_dai->id, user_set_tx_ch); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret < 0) { + pr_err("%s: failed to get codec chan map\n, err:%d\n", + __func__, ret); + goto end; + } + /* For _tx1 case */ + if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX) + user_set_tx_ch = msm_slim_0_tx_ch; + /* For _tx2 case */ + else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX) + user_set_tx_ch = msm_slim_1_tx_ch; + else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_TX) + user_set_tx_ch = msm_slim_2_tx_ch; + else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_3_TX) + /* DAI 5 is used for external EC reference from codec. + * Since Rx is fed as reference for EC, the config of + * this DAI is based on that of the Rx path. + */ + user_set_tx_ch = msm_slim_0_rx_ch; + else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX) + user_set_tx_ch = msm_vi_feed_tx_ch; + else + user_set_tx_ch = tx_ch_cnt; + + pr_debug( + "%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d)\n", + __func__, msm_slim_0_tx_ch, user_set_tx_ch, tx_ch_cnt); + + ret = snd_soc_dai_set_channel_map(cpu_dai, + user_set_tx_ch, tx_ch, 0, 0); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto end; + } + } +end: + return ret; +} + +int msm8952_slimbus_2_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret = 0; + unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS]; + unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0; + unsigned int num_tx_ch = 0; + unsigned int num_rx_ch = 0; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + num_rx_ch = params_channels(params); + pr_debug("%s: %s rx_dai_id = %d num_ch = %d\n", __func__, + codec_dai->name, codec_dai->id, num_rx_ch); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret < 0) { + pr_err("%s: failed to get codec chan map, err:%d\n", + __func__, ret); + goto end; + } + ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0, + num_rx_ch, rx_ch); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto end; + } + } else { + num_tx_ch = params_channels(params); + pr_debug("%s: %s tx_dai_id = %d num_ch = %d\n", __func__, + codec_dai->name, codec_dai->id, num_tx_ch); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret < 0) { + pr_err("%s: failed to get codec chan map, err:%d\n", + __func__, ret); + goto end; + } + ret = snd_soc_dai_set_channel_map(cpu_dai, + num_tx_ch, tx_ch, 0, 0); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto end; + } + } +end: + return ret; +} + +int msm_slim_0_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = + hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim0_rx_bit_format); + rate->min = rate->max = slim0_rx_sample_rate; + channels->min = channels->max = msm_slim_0_rx_ch; + + pr_debug("%s: format = %d, rate = %d, channels = %d\n", + __func__, params_format(params), params_rate(params), + msm_slim_0_rx_ch); + + return 0; +} + +int msm_slim_0_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim0_tx_bit_format); + rate->min = rate->max = slim0_tx_sample_rate; + channels->min = channels->max = msm_slim_0_tx_ch; + + return 0; +} + +int msm_slim_1_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim1_tx_bit_format); + rate->min = rate->max = slim1_tx_sample_rate; + channels->min = channels->max = msm_slim_1_tx_ch; + + return 0; +} + +int msm_slim_2_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim2_tx_bit_format); + rate->min = rate->max = slim2_tx_sample_rate; + channels->min = channels->max = msm_slim_2_tx_ch; + + return 0; +} + +int msm_slim_4_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = + hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim4_rx_bit_format); + rate->min = rate->max = slim4_rx_sample_rate; + channels->min = channels->max = msm_slim_4_rx_ch; + + pr_debug("%s: format = %d, rate = %d, channels = %d\n", + __func__, params_format(params), params_rate(params), + msm_slim_4_rx_ch); + + return 0; +} + +int msm_slim_4_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + struct snd_soc_dai *codec_dai = rtd->codec_dai; + + pr_debug("%s: codec name: %s", __func__, codec_dai->name); + if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) { + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + SNDRV_PCM_FORMAT_S32_LE); + rate->min = rate->max = SAMPLING_RATE_8KHZ; + channels->min = channels->max = msm_vi_feed_tx_ch; + pr_debug("%s: tasha vi sample rate = %d\n", + __func__, rate->min); + } else { + rate->min = rate->max = SAMPLING_RATE_48KHZ; + channels->min = channels->max = msm_vi_feed_tx_ch; + pr_debug("%s: default sample rate = %d\n", + __func__, rate->min); + } + + pr_debug("%s: %d\n", __func__, msm_vi_feed_tx_ch); + return 0; +} + +int msm_slim_5_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim5_rx_bit_format); + rate->min = rate->max = slim5_rx_sample_rate; + channels->min = channels->max = msm_slim_5_rx_ch; + + pr_debug("%s: format = %d, rate = %d, channels = %d\n", + __func__, params_format(params), params_rate(params), + msm_slim_5_rx_ch); + + return 0; +} + +int msm_slim_6_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim6_rx_bit_format); + rate->min = rate->max = slim6_rx_sample_rate; + channels->min = channels->max = msm_slim_6_rx_ch; + + pr_debug("%s: format = %d, rate = %d, channels = %d\n", + __func__, params_format(params), params_rate(params), + msm_slim_6_rx_ch); + + return 0; +} + +int msm_slim_5_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + int rc; + void *config; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_component *component; + struct snd_interval *rate = + hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = + hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); + struct msm8952_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(rtd->card); + + pr_debug("%s enter\n", __func__); + if (!strcmp(dev_name(codec_dai->dev), "tavil_codec")) + component = snd_soc_rtdcom_lookup(rtd, "tavil_codec"); + else if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) + component = snd_soc_rtdcom_lookup(rtd, "tasha_codec"); + + rate->min = rate->max = 16000; + channels->min = channels->max = 1; + config = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_SLIMBUS_SLAVE_PORT_CONFIG); + rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG, config, + SLIMBUS_5_TX); + if (rc) { + pr_err("%s: Failed to set slimbus slave port config %d\n", + __func__, rc); + return rc; + } + return 0; +} + +int msm_snd_cpe_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_dai_link *dai_link = rtd->dai_link; + int ret = 0; + u32 tx_ch[SLIM_MAX_TX_PORTS]; + u32 tx_ch_cnt = 0; + u32 user_set_tx_ch = 0; + + if (substream->stream != SNDRV_PCM_STREAM_CAPTURE) { + pr_err("%s: Invalid stream type %d\n", + __func__, substream->stream); + ret = -EINVAL; + goto end; + } + + pr_debug("%s: %s_tx_dai_id_%d\n", __func__, + codec_dai->name, codec_dai->id); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, NULL, NULL); + if (ret < 0) { + pr_err("%s: failed to get codec chan map\n, err:%d\n", + __func__, ret); + goto end; + } + + user_set_tx_ch = tx_ch_cnt; + + pr_debug("%s: tx_ch_cnt(%d) id %d\n", + __func__, tx_ch_cnt, dai_link->id); + + ret = snd_soc_dai_set_channel_map(cpu_dai, + user_set_tx_ch, tx_ch, 0, 0); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto end; + } +end: + return ret; +} + +static int msm_afe_set_config(struct snd_soc_component *component) +{ + int rc; + void *config_data; + struct snd_soc_card *card = component->card; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + pr_debug("%s: enter\n", __func__); + + if (!pdata->msm8952_codec_fn.get_afe_config_fn) { + dev_err(component->dev, "%s: codec get afe config not init'ed\n", + __func__); + return -EINVAL; + } + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_CDC_REGISTERS_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0); + if (rc) { + pr_err("%s: Failed to set codec registers config %d\n", + __func__, rc); + return rc; + } + } + + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_CDC_REGISTER_PAGE_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data, + 0); + if (rc) + pr_err("%s: Failed to set cdc register page config\n", + __func__); + } + + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_SLIMBUS_SLAVE_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0); + if (rc) { + pr_err("%s: Failed to set slimbus slave config %d\n", + __func__, rc); + return rc; + } + } + + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_AANC_VERSION); + if (config_data) { + rc = afe_set_config(AFE_AANC_VERSION, config_data, 0); + if (rc) { + pr_err("%s: Failed to set AANC version %d\n", + __func__, rc); + return rc; + } + } + + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_CDC_CLIP_REGISTERS_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_CDC_CLIP_REGISTERS_CONFIG, + config_data, 0); + if (rc) { + pr_err("%s: Failed to set clip registers %d\n", + __func__, rc); + return rc; + } + } + + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_CLIP_BANK_SEL); + if (config_data) { + rc = afe_set_config(AFE_CLIP_BANK_SEL, + config_data, 0); + if (rc) { + pr_err("%s: Failed to set AFE bank selection %d\n", + __func__, rc); + return rc; + } + } + + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_CDC_REGISTER_PAGE_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data, + 0); + if (rc) + pr_err("%s: Failed to set cdc register page config\n", + __func__); + } + + return 0; +} + +static void msm_afe_clear_config(void) +{ + afe_clear_config(AFE_CDC_REGISTERS_CONFIG); + afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG); +} + +static int quat_mi2s_clk_ctl(struct snd_pcm_substream *substream, bool enable) +{ + int ret = 0; + + if (enable) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mi2s_rx_clk.enable = enable; + mi2s_rx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT; + if ((mi2s_rx_bit_format == SNDRV_PCM_FORMAT_S24_LE) || + (mi2s_rx_bit_format == + SNDRV_PCM_FORMAT_S24_3LE)) + mi2s_rx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_3_P072_MHZ; + else + mi2s_rx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUATERNARY_MI2S_RX, + &mi2s_rx_clk); + } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + mi2s_tx_clk.enable = enable; + mi2s_tx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT; + mi2s_tx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUATERNARY_MI2S_TX, + &mi2s_tx_clk); + } else { + pr_err("%s:Not valid substream.\n", __func__); + } + + if (ret < 0) + pr_err("%s:afe_set_lpass_clock failed %d\n", + __func__, ret); + } else { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mi2s_rx_clk.enable = enable; + mi2s_rx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUATERNARY_MI2S_RX, + &mi2s_rx_clk); + } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + mi2s_tx_clk.enable = enable; + mi2s_tx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUATERNARY_MI2S_TX, + &mi2s_tx_clk); + } else + pr_err("%s:Not valid substream %d\n", __func__, + substream->stream); + + if (ret < 0) + pr_err("%s:afe_set_lpass_clock failed ret=%d\n", + __func__, ret); + } + return ret; +} + +static int quin_mi2s_sclk_ctl(struct snd_pcm_substream *substream, bool enable) +{ + int ret = 0; + + if (enable) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mi2s_rx_clk.enable = enable; + mi2s_rx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT; + if ((mi2s_rx_bit_format == SNDRV_PCM_FORMAT_S24_LE) || + (mi2s_rx_bit_format == + SNDRV_PCM_FORMAT_S24_3LE)) + mi2s_rx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_3_P072_MHZ; + else + mi2s_rx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUINARY_MI2S_RX, + &mi2s_rx_clk); + } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + mi2s_tx_clk.enable = enable; + mi2s_tx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT; + mi2s_tx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUINARY_MI2S_TX, + &mi2s_tx_clk); + } else { + pr_err("%s:Not valid substream.\n", __func__); + } + + if (ret < 0) + pr_err("%s:afe_set_lpass_clock failed\n", __func__); + } else { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mi2s_rx_clk.enable = enable; + mi2s_rx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUINARY_MI2S_RX, + &mi2s_rx_clk); + } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + mi2s_tx_clk.enable = enable; + mi2s_tx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUINARY_MI2S_TX, + &mi2s_tx_clk); + } else + pr_err("%s:Not valid substream %d\n", __func__, + substream->stream); + + if (ret < 0) + pr_err("%s:afe_set_lpass_clock failed ret=%d\n", + __func__, ret); + } + return ret; +} + +static int msm8952_adsp_state_callback(struct notifier_block *nb, + unsigned long value, void *priv) +{ + if (value == SUBSYS_BEFORE_SHUTDOWN) { + pr_debug("%s: ADSP is about to shutdown. Clearing AFE config\n", + __func__); + msm_afe_clear_config(); + } else if (value == SUBSYS_AFTER_POWERUP) { + pr_debug("%s: ADSP is up\n", __func__); + } + + return NOTIFY_OK; +} + +static struct notifier_block adsp_state_notifier_block = { + .notifier_call = msm8952_adsp_state_callback, + .priority = -INT_MAX, +}; + +void msm_quat_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + int ret = 0; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + pr_debug("%s(): substream = %s stream = %d, ext_pa = %d\n", __func__, + substream->name, substream->stream, pdata->ext_pa); + + ret = quat_mi2s_clk_ctl(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed\n", __func__); + if (atomic_read(&pdata->clk_ref.quat_mi2s_clk_ref) > 0) + atomic_dec(&pdata->clk_ref.quat_mi2s_clk_ref); + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) { + pr_err("%s: failed to disable quat gpio's state\n", + __func__); + return; + } + } +} + +int msm_prim_auxpcm_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s\n", + __func__, substream->name); + + /* mux config to route the AUX MI2S */ + if (pdata->vaddr_gpio_mux_mic_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ctl); + val = val | 0x2; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ctl); + } + if (pdata->vaddr_gpio_mux_pcm_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_pcm_ctl); + val = val | 0x1; + iowrite32(val, pdata->vaddr_gpio_mux_pcm_ctl); + } + atomic_inc(&pdata->clk_ref.auxpcm_mi2s_clk_ref); + + /* enable the gpio's used for the external AUXPCM interface */ + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) + pr_err("%s(): configure gpios failed = %s\n", + __func__, "quat_i2s"); + } + return ret; +} + +void msm_prim_auxpcm_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret; + + pr_debug("%s(): substream = %s\n", + __func__, substream->name); + if (atomic_read(&pdata->clk_ref.auxpcm_mi2s_clk_ref) > 0) + atomic_dec(&pdata->clk_ref.auxpcm_mi2s_clk_ref); + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) + pr_err("%s(): configure gpios failed = %s\n", + __func__, "quat_i2s"); + } +} + +int msm_quat_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret = 0, val; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + /* Configure mux for quaternary i2s */ + if (pdata->vaddr_gpio_mux_mic_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ctl); + val = val | 0x02020002; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ctl); + } + ret = quat_mi2s_clk_ctl(substream, true); + if (ret < 0) { + pr_err("%s: failed to enable bit clock\n", + __func__); + return ret; + } + + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) { + pr_err("%s: failed to actiavte the quat gpio's state\n", + __func__); + goto err; + } + } + + if (atomic_inc_return(&pdata->clk_ref.quat_mi2s_clk_ref) == 1) { + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) + pr_err("%s: set fmt cpu dai failed\n", __func__); + } + return ret; + +err: + ret = quat_mi2s_clk_ctl(substream, false); + if (ret < 0) + pr_err("%s:failed to disable sclk\n", __func__); + return ret; +} + +int msm_quin_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct msm8952_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + if (pdata->vaddr_gpio_mux_quin_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_quin_ctl); + val = val | 0x00000001; + iowrite32(val, pdata->vaddr_gpio_mux_quin_ctl); + } else { + return -EINVAL; + } + ret = quin_mi2s_sclk_ctl(substream, true); + if (ret < 0) { + pr_err("failed to enable sclk\n"); + return ret; + } + if (pdata->mi2s_gpio_p[QUIN_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUIN_MI2S]); + if (ret < 0) { + pr_err("failed to enable codec gpios\n"); + goto err; + } + } + + if (atomic_inc_return(&pdata->clk_ref.quin_mi2s_clk_ref) == 1) { + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) + pr_debug("%s: set fmt cpu dai failed\n", __func__); + } + return ret; +err: + ret = quin_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("failed to disable sclk\n"); + return ret; +} + +void msm_quin_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + int ret; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + ret = quin_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed\n", __func__); + if (atomic_read(&pdata->clk_ref.quin_mi2s_clk_ref) > 0) + atomic_dec(&pdata->clk_ref.quin_mi2s_clk_ref); + if (pdata->mi2s_gpio_p[QUIN_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUIN_MI2S]); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "quin_i2s"); + return; + } + } +} + +int msm_tdm_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm8952_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id); + + switch (cpu_dai->id) { + case AFE_PORT_ID_PRIMARY_TDM_RX: + case AFE_PORT_ID_PRIMARY_TDM_RX_1: + case AFE_PORT_ID_PRIMARY_TDM_RX_2: + case AFE_PORT_ID_PRIMARY_TDM_RX_3: + case AFE_PORT_ID_PRIMARY_TDM_RX_4: + case AFE_PORT_ID_PRIMARY_TDM_RX_5: + case AFE_PORT_ID_PRIMARY_TDM_RX_6: + case AFE_PORT_ID_PRIMARY_TDM_RX_7: + case AFE_PORT_ID_PRIMARY_TDM_TX: + case AFE_PORT_ID_PRIMARY_TDM_TX_1: + case AFE_PORT_ID_PRIMARY_TDM_TX_2: + case AFE_PORT_ID_PRIMARY_TDM_TX_3: + case AFE_PORT_ID_PRIMARY_TDM_TX_4: + case AFE_PORT_ID_PRIMARY_TDM_TX_5: + case AFE_PORT_ID_PRIMARY_TDM_TX_6: + case AFE_PORT_ID_PRIMARY_TDM_TX_7: + /* Configure mux for Primary TDM */ + if (pdata->vaddr_gpio_mux_pcm_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_pcm_ctl); + val = val | 0x00000001; + iowrite32(val, pdata->vaddr_gpio_mux_pcm_ctl); + } else { + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_mic_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ctl); + val = val | 0x00000002; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ctl); + } else { + return -EINVAL; + } + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) + pr_err("%s: failed to activate pri TDM gpio\n", + __func__); + } + break; + case AFE_PORT_ID_SECONDARY_TDM_RX: + case AFE_PORT_ID_SECONDARY_TDM_RX_1: + case AFE_PORT_ID_SECONDARY_TDM_RX_2: + case AFE_PORT_ID_SECONDARY_TDM_RX_3: + case AFE_PORT_ID_SECONDARY_TDM_RX_4: + case AFE_PORT_ID_SECONDARY_TDM_RX_5: + case AFE_PORT_ID_SECONDARY_TDM_RX_6: + case AFE_PORT_ID_SECONDARY_TDM_RX_7: + case AFE_PORT_ID_SECONDARY_TDM_TX: + case AFE_PORT_ID_SECONDARY_TDM_TX_1: + case AFE_PORT_ID_SECONDARY_TDM_TX_2: + case AFE_PORT_ID_SECONDARY_TDM_TX_3: + case AFE_PORT_ID_SECONDARY_TDM_TX_4: + case AFE_PORT_ID_SECONDARY_TDM_TX_5: + case AFE_PORT_ID_SECONDARY_TDM_TX_6: + case AFE_PORT_ID_SECONDARY_TDM_TX_7: + /* Configure mux for Secondary TDM */ + if (pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl) { + val = ioread32( + pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl); + val = val | 0x00000001; + iowrite32(val, + pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl); + } else { + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_quin_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_quin_ctl); + val = val | 0x00000001; + iowrite32(val, pdata->vaddr_gpio_mux_quin_ctl); + } else { + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_mic_ext_clk_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ext_clk_ctl); + val = val | 0x00000001; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ext_clk_ctl); + } else { + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_sec_tlmm_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_sec_tlmm_ctl); + val = val | 0x00000002; + iowrite32(val, pdata->vaddr_gpio_mux_sec_tlmm_ctl); + } else { + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_spkr_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_spkr_ctl); + val = val | 0x00000002; + iowrite32(val, pdata->vaddr_gpio_mux_spkr_ctl); + } else { + return -EINVAL; + } + if (pdata->mi2s_gpio_p[QUIN_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUIN_MI2S]); + if (ret < 0) + pr_err("%s: failed to activate sec TDM gpio\n", + __func__); + } + break; + default: + pr_err("%s: dai id 0x%x not supported\n", + __func__, cpu_dai->id); + break; + return -EINVAL; + } + return ret; +} + +void msm_tdm_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_card *card = rtd->card; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret; + + switch (cpu_dai->id) { + case AFE_PORT_ID_PRIMARY_TDM_RX: + case AFE_PORT_ID_PRIMARY_TDM_RX_1: + case AFE_PORT_ID_PRIMARY_TDM_RX_2: + case AFE_PORT_ID_PRIMARY_TDM_RX_3: + case AFE_PORT_ID_PRIMARY_TDM_RX_4: + case AFE_PORT_ID_PRIMARY_TDM_RX_5: + case AFE_PORT_ID_PRIMARY_TDM_RX_6: + case AFE_PORT_ID_PRIMARY_TDM_RX_7: + case AFE_PORT_ID_PRIMARY_TDM_TX: + case AFE_PORT_ID_PRIMARY_TDM_TX_1: + case AFE_PORT_ID_PRIMARY_TDM_TX_2: + case AFE_PORT_ID_PRIMARY_TDM_TX_3: + case AFE_PORT_ID_PRIMARY_TDM_TX_4: + case AFE_PORT_ID_PRIMARY_TDM_TX_5: + case AFE_PORT_ID_PRIMARY_TDM_TX_6: + case AFE_PORT_ID_PRIMARY_TDM_TX_7: + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) { + pr_err("%s: gpio cannot be de-activated %s\n", + __func__, "pri_tdm"); + return; + } + } + break; + case AFE_PORT_ID_SECONDARY_TDM_RX: + case AFE_PORT_ID_SECONDARY_TDM_RX_1: + case AFE_PORT_ID_SECONDARY_TDM_RX_2: + case AFE_PORT_ID_SECONDARY_TDM_RX_3: + case AFE_PORT_ID_SECONDARY_TDM_RX_4: + case AFE_PORT_ID_SECONDARY_TDM_RX_5: + case AFE_PORT_ID_SECONDARY_TDM_RX_6: + case AFE_PORT_ID_SECONDARY_TDM_RX_7: + case AFE_PORT_ID_SECONDARY_TDM_TX: + case AFE_PORT_ID_SECONDARY_TDM_TX_1: + case AFE_PORT_ID_SECONDARY_TDM_TX_2: + case AFE_PORT_ID_SECONDARY_TDM_TX_3: + case AFE_PORT_ID_SECONDARY_TDM_TX_4: + case AFE_PORT_ID_SECONDARY_TDM_TX_5: + case AFE_PORT_ID_SECONDARY_TDM_TX_6: + case AFE_PORT_ID_SECONDARY_TDM_TX_7: + if (pdata->mi2s_gpio_p[QUIN_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUIN_MI2S]); + if (ret < 0) { + pr_err("%s: gpio cannot be de-activated %s", + __func__, "sec_tdm"); + return; + } + } + break; + } +} + +static int msm8952_mclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + pr_debug("%s: event = %d\n", __func__, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + return msm8952_enable_codec_mclk(component, 1, true); + case SND_SOC_DAPM_POST_PMD: + return msm8952_enable_codec_mclk(component, 0, true); + } + return 0; +} + +static const struct snd_soc_dapm_widget msm8952_tasha_dapm_widgets[] = { + + SND_SOC_DAPM_SUPPLY_S("MCLK", -1, SND_SOC_NOPM, 0, 0, + msm8952_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_SPK("Lineout_1 amp", NULL), + SND_SOC_DAPM_SPK("Lineout_3 amp", NULL), + SND_SOC_DAPM_SPK("Lineout_2 amp", NULL), + SND_SOC_DAPM_SPK("Lineout_4 amp", NULL), + SND_SOC_DAPM_MIC("Handset Mic", NULL), + SND_SOC_DAPM_MIC("Headset Mic", NULL), + SND_SOC_DAPM_MIC("Secondary Mic", NULL), + SND_SOC_DAPM_MIC("ANCRight Headset Mic", NULL), + SND_SOC_DAPM_MIC("ANCLeft Headset Mic", NULL), + SND_SOC_DAPM_MIC("Analog Mic4", NULL), + SND_SOC_DAPM_MIC("Analog Mic6", NULL), + SND_SOC_DAPM_MIC("Analog Mic7", NULL), + SND_SOC_DAPM_MIC("Analog Mic8", NULL), + + SND_SOC_DAPM_MIC("Digital Mic0", NULL), + SND_SOC_DAPM_MIC("Digital Mic1", NULL), + SND_SOC_DAPM_MIC("Digital Mic2", NULL), + SND_SOC_DAPM_MIC("Digital Mic3", NULL), + SND_SOC_DAPM_MIC("Digital Mic4", NULL), + SND_SOC_DAPM_MIC("Digital Mic5", NULL), + SND_SOC_DAPM_MIC("Digital Mic6", NULL), +}; + +static struct snd_soc_dapm_route wcd9335_audio_paths[] = { + {"MIC BIAS1", NULL, "MCLK"}, + {"MIC BIAS2", NULL, "MCLK"}, + {"MIC BIAS3", NULL, "MCLK"}, + {"MIC BIAS4", NULL, "MCLK"}, +}; + +int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) +{ + int ret = -EINVAL; + int err; + struct snd_soc_component *component; + struct snd_soc_dapm_context *dapm; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_card *card; + struct snd_soc_component *aux_comp; + struct snd_info_entry *entry; + struct msm8952_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(rtd->card); + + /* Codec SLIMBUS configuration + * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8, RX9, RX10, RX11, RX12, RX13 + * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13 + * TX14, TX15, TX16 + */ + unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150, + 151, 152, 153, 154, 155, 156}; + unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133, + 134, 135, 136, 137, 138, 139, + 140, 141, 142, 143}; + + pr_debug("%s: dev_name%s\n", __func__, dev_name(cpu_dai->dev)); + + component = snd_soc_rtdcom_lookup(rtd, "tasha_codec"); + if (!component) { + pr_err("%s: could not find component for tasha_codec\n", + __func__); + return ret; + } + dapm = snd_soc_component_get_dapm(component); + rtd->pmdown_time = 0; + + err = snd_soc_add_component_controls(component, msm_snd_controls, + ARRAY_SIZE(msm_snd_controls)); + if (err < 0) { + pr_err("%s: add_component_controls failed, err%d\n", + __func__, err); + return err; + } + + if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) { + pdata->msm8952_codec_fn.get_afe_config_fn = + tasha_get_afe_config; + snd_soc_dapm_new_controls(dapm, msm8952_tasha_dapm_widgets, + ARRAY_SIZE(msm8952_tasha_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, wcd9335_audio_paths, + ARRAY_SIZE(wcd9335_audio_paths)); + } + + snd_soc_dapm_enable_pin(dapm, "Lineout_1 amp"); + snd_soc_dapm_enable_pin(dapm, "Lineout_3 amp"); + snd_soc_dapm_enable_pin(dapm, "Lineout_2 amp"); + snd_soc_dapm_enable_pin(dapm, "Lineout_4 amp"); + + snd_soc_dapm_ignore_suspend(dapm, "MADINPUT"); + snd_soc_dapm_ignore_suspend(dapm, "MAD_CPE_INPUT"); + snd_soc_dapm_ignore_suspend(dapm, "Handset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Secondary Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2"); + snd_soc_dapm_ignore_suspend(dapm, "Lineout_1 amp"); + snd_soc_dapm_ignore_suspend(dapm, "Lineout_3 amp"); + snd_soc_dapm_ignore_suspend(dapm, "Lineout_2 amp"); + snd_soc_dapm_ignore_suspend(dapm, "Lineout_4 amp"); + snd_soc_dapm_ignore_suspend(dapm, "Handset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "ANCRight Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "ANCLeft Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5"); + snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4"); + snd_soc_dapm_ignore_suspend(dapm, "Analog Mic6"); + snd_soc_dapm_ignore_suspend(dapm, "Analog Mic7"); + snd_soc_dapm_ignore_suspend(dapm, "Analog Mic8"); + snd_soc_dapm_ignore_suspend(dapm, "MADINPUT"); + snd_soc_dapm_ignore_suspend(dapm, "MAD_CPE_INPUT"); + + snd_soc_dapm_ignore_suspend(dapm, "EAR"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT3"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT4"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC2"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC3"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC4"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC5"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC6"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC2"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC3"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC4"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC5"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC6"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6"); + snd_soc_dapm_ignore_suspend(dapm, "ANC EAR"); + snd_soc_dapm_ignore_suspend(dapm, "ANC HEADPHONE"); + if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) { + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC0"); + snd_soc_dapm_ignore_suspend(dapm, "SPK1 OUT"); + snd_soc_dapm_ignore_suspend(dapm, "SPK2 OUT"); + snd_soc_dapm_ignore_suspend(dapm, "HPHL"); + snd_soc_dapm_ignore_suspend(dapm, "HPHR"); + snd_soc_dapm_ignore_suspend(dapm, "ANC HPHL"); + snd_soc_dapm_ignore_suspend(dapm, "ANC HPHR"); + snd_soc_dapm_ignore_suspend(dapm, "ANC LINEOUT1"); + snd_soc_dapm_ignore_suspend(dapm, "ANC LINEOUT2"); + snd_soc_dapm_ignore_suspend(dapm, "AIF4 VI"); + snd_soc_dapm_ignore_suspend(dapm, "VIINPUT"); + + } + + snd_soc_dapm_sync(dapm); + snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch), + tx_ch, ARRAY_SIZE(rx_ch), rx_ch); + + err = msm_afe_set_config(component); + if (err) { + pr_err("%s: Failed to set AFE config %d\n", __func__, err); + goto out; + } + + adsp_state_notifier = + subsys_notif_register_notifier("adsp", + &adsp_state_notifier_block); + if (!adsp_state_notifier) { + pr_err("%s: Failed to register adsp state notifier\n", + __func__); + err = -EFAULT; + goto out; + } + + if (rtd->card->num_aux_devs && + !list_empty(&rtd->card->aux_comp_list)) { + aux_comp = list_first_entry(&rtd->card->aux_comp_list, + struct snd_soc_component, card_aux_list); + if (!strcmp(aux_comp->name, WSA8810_NAME_1) || + !strcmp(aux_comp->name, WSA8810_NAME_2)) { + tasha_set_spkr_mode(component, SPKR_MODE_1); + tasha_set_spkr_gain_offset(component, + RX_GAIN_OFFSET_M1P5_DB); + } + } + + if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) { + wcd_mbhc_cfg.calibration = def_tasha_mbhc_cal(); + if (wcd_mbhc_cfg.calibration) { + //pdata->codec = codec; + err = tasha_mbhc_hs_detect(component, &wcd_mbhc_cfg); + if (err < 0) + pr_err("%s: Failed to initialise mbhc %d\n", + __func__, err); + } else { + pr_err("%s: wcd_mbhc_cfg calibration is NULL\n", + __func__); + err = -ENOMEM; + goto out; + } + + } + + codec_reg_done = true; + + if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) { + card = rtd->card->snd_card; + entry = snd_info_create_subdir(card->module, + "codecs", + card->proc_root); + if (!entry) { + pr_debug("%s: Cannot create codecs module entry\n", + __func__); + err = 0; + goto out; + } + pdata->codec_root = entry; + tasha_codec_info_create_codec_entry(pdata->codec_root, + component); + } + return 0; +out: + return err; +} + +static bool msm8952_swap_gnd_mic(struct snd_soc_component *component, + bool active) +{ + struct snd_soc_card *card = component->card; + struct msm8952_asoc_mach_data *pdata = NULL; + int value = 0; + int ret = 0; + + pdata = snd_soc_card_get_drvdata(card); + if (!gpio_is_valid(pdata->us_euro_gpio)) { + pr_err("%s: Invalid gpio: %d", __func__, pdata->us_euro_gpio); + return false; + } + value = gpio_get_value_cansleep(pdata->us_euro_gpio); + if (pdata->us_euro_gpio_p) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->us_euro_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be activated %sd", + __func__, "us_eu_gpio"); + return false; + } + } + gpio_set_value_cansleep(pdata->us_euro_gpio, !value); + pr_debug("%s: swap select switch %d to %d\n", __func__, value, !value); + if (pdata->us_euro_gpio_p) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->us_euro_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "us_eu_gpio"); + return false; + } + } + return true; +} + +static int is_us_eu_switch_gpio_support(struct platform_device *pdev, + struct msm8952_asoc_mach_data *pdata) +{ + pr_debug("%s\n", __func__); + + /* check if US-EU GPIO is supported */ + pdata->us_euro_gpio = of_get_named_gpio(pdev->dev.of_node, + "qcom,cdc-us-euro-gpios", 0); + if (pdata->us_euro_gpio < 0) { + dev_err(&pdev->dev, + "property %s in node %s not found %d\n", + "qcom,cdc-us-euro-gpios", pdev->dev.of_node->full_name, + pdata->us_euro_gpio); + } else { + if (!gpio_is_valid(pdata->us_euro_gpio)) { + pr_err("%s: Invalid gpio: %d", __func__, + pdata->us_euro_gpio); + return -EINVAL; + } + pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,cdc-us-eu-gpios", 0); + wcd_mbhc_cfg.swap_gnd_mic = msm8952_swap_gnd_mic; + } + return 0; +} + +static int msm8952_populate_dai_link_component_of_node( + struct snd_soc_card *card) +{ + int i, index, ret = 0; + struct device *cdev = card->dev; + struct snd_soc_dai_link *dai_link = card->dai_link; + struct device_node *phandle; + + if (!cdev) { + pr_err("%s: Sound card device memory NULL\n", __func__); + return -ENODEV; + } + + for (i = 0; i < card->num_links; i++) { + if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node) + continue; + /* populate platform_of_node for snd card dai links */ + if (dai_link[i].platform_name && + !dai_link[i].platform_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-platform-names", + dai_link[i].platform_name); + if (index < 0) { + pr_err("%s: No match found for platform name: %s\n", + __func__, dai_link[i].platform_name); + ret = index; + goto cpu_dai; + } + phandle = of_parse_phandle(cdev->of_node, + "asoc-platform", + index); + if (!phandle) { + pr_err("%s: retrieving phandle for platform %s, index %d failed\n", + __func__, dai_link[i].platform_name, + index); + ret = -ENODEV; + goto err; + } + dai_link[i].platform_of_node = phandle; + dai_link[i].platform_name = NULL; + } +cpu_dai: + /* populate cpu_of_node for snd card dai links */ + if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-cpu-names", + dai_link[i].cpu_dai_name); + if (index < 0) { + pr_debug("cpu-names not found index = %d\n", i); + goto codec_dai; + } + phandle = of_parse_phandle(cdev->of_node, "asoc-cpu", + index); + if (!phandle) { + pr_err("%s: phandle for cpu dai %s failed\n", + __func__, dai_link[i].cpu_dai_name); + ret = -ENODEV; + goto err; + } + dai_link[i].cpu_of_node = phandle; + dai_link[i].cpu_dai_name = NULL; + } +codec_dai: + /* populate codec_of_node for snd card dai links */ + if (dai_link[i].codec_name && !dai_link[i].codec_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-codec-names", + dai_link[i].codec_name); + if (index < 0) + continue; + phandle = of_parse_phandle(cdev->of_node, "asoc-codec", + index); + if (!phandle) { + pr_err("%s: retrieving phandle for codec dai %s failed\n", + __func__, dai_link[i].codec_name); + ret = -ENODEV; + goto err; + } + dai_link[i].codec_of_node = phandle; + dai_link[i].codec_name = NULL; + } + } +err: + return ret; +} + +static int msm8952_asoc_machine_probe(struct platform_device *pdev) +{ + struct snd_soc_card *card; + struct msm8952_asoc_mach_data *pdata = NULL; + const char *ext_pa = "qcom,msm-ext-pa"; + const char *ext_pa_str = NULL; + int num_strings = 0; + int ret, i; + struct resource *muxsel; + + pdata = devm_kzalloc(&pdev->dev, + sizeof(struct msm8952_asoc_mach_data), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_mic_ctl"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for MIC CTL\n"); + ret = -ENODEV; + goto err; + } + pdata->vaddr_gpio_mux_mic_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_mic_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for QUAT I2S\n"); + ret = -ENODEV; + goto err; + } + pdata->vaddr_gpio_mux_pcm_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_pcm_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_spkr_ctl"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for SPKR CTL\n"); + ret = -ENODEV; + goto err; + } + pdata->vaddr_gpio_mux_spkr_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_spkr_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_quin_ctl"); + if (!muxsel) { + dev_dbg(&pdev->dev, "MUX addr invalid for QUIN I2S\n"); + ret = -ENODEV; + } else { + pdata->vaddr_gpio_mux_quin_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_quin_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_lpaif_qui_pcm_sec_mode_muxsel"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for QUIN PCM\n"); + ret = -ENODEV; + } else { + pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_mic_ext_clk_ctl"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for EXT CLK CTL\n"); + ret = -ENODEV; + } else { + pdata->vaddr_gpio_mux_mic_ext_clk_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_mic_ext_clk_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_sec_tlmm_ctl"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for SEC TLMM CTL\n"); + ret = -ENODEV; + } else { + pdata->vaddr_gpio_mux_sec_tlmm_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_sec_tlmm_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + } + + pdev->id = 0; + + atomic_set(&pdata->clk_ref.quat_mi2s_clk_ref, 0); + atomic_set(&pdata->clk_ref.auxpcm_mi2s_clk_ref, 0); + card = populate_snd_card_dailinks(&pdev->dev); + if (!card) { + ret = -EPROBE_DEFER; + goto err; + } + card->dev = &pdev->dev; + platform_set_drvdata(pdev, card); + snd_soc_card_set_drvdata(card, pdata); + + ret = snd_soc_of_parse_audio_routing(card, + "qcom,audio-routing"); + if (ret) + goto err; + + ret = msm8952_populate_dai_link_component_of_node(card); + if (ret) { + ret = -EPROBE_DEFER; + goto err; + } + + ret = msm8952_init_wsa_dev(pdev, card); + if (ret) + goto err; + + ret = devm_snd_soc_register_card(&pdev->dev, card); + if (ret) { + if (codec_reg_done) + ret = -EINVAL; + dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", + ret); + goto err; + } + num_strings = of_property_count_strings(pdev->dev.of_node, + ext_pa); + if (num_strings < 0) { + dev_err(&pdev->dev, + "%s: missing %s in dt node or length is incorrect\n", + __func__, ext_pa); + pdata->ext_pa = 0; + } + for (i = 0; i < num_strings; i++) { + of_property_read_string_index(pdev->dev.of_node, + ext_pa, i, &ext_pa_str); + if (!strcmp(ext_pa_str, "primary")) + pdata->ext_pa = (pdata->ext_pa | PRI_MI2S_ID); + else if (!strcmp(ext_pa_str, "secondary")) + pdata->ext_pa = (pdata->ext_pa | SEC_MI2S_ID); + else if (!strcmp(ext_pa_str, "tertiary")) + pdata->ext_pa = (pdata->ext_pa | TER_MI2S_ID); + else if (!strcmp(ext_pa_str, "quaternary")) + pdata->ext_pa = (pdata->ext_pa | QUAT_MI2S_ID); + else if (!strcmp(ext_pa_str, "quinary")) + pdata->ext_pa = (pdata->ext_pa | QUIN_MI2S_ID); + } + + /* Parse US-Euro gpio info from DT. Report no error if us-euro + * entry is not found in DT file as some targets do not support + * US-Euro detection + */ + ret = is_us_eu_switch_gpio_support(pdev, pdata); + if (ret < 0) { + pr_err("%s: failed to is_us_eu_switch_gpio_support %d\n", + __func__, ret); + goto err; + } + pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,quat-mi2s-gpios", 0); + pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,quin-mi2s-gpios", 0); + + return 0; +err: + if (pdata->us_euro_gpio > 0) { + dev_dbg(&pdev->dev, "%s free us_euro gpio %d\n", + __func__, pdata->us_euro_gpio); + gpio_free(pdata->us_euro_gpio); + pdata->us_euro_gpio = 0; + } + if (pdata->vaddr_gpio_mux_spkr_ctl) + iounmap(pdata->vaddr_gpio_mux_spkr_ctl); + if (pdata->vaddr_gpio_mux_mic_ctl) + iounmap(pdata->vaddr_gpio_mux_mic_ctl); + if (pdata->vaddr_gpio_mux_pcm_ctl) + iounmap(pdata->vaddr_gpio_mux_pcm_ctl); + if (pdata->vaddr_gpio_mux_quin_ctl) + iounmap(pdata->vaddr_gpio_mux_quin_ctl); + if (pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl) + iounmap(pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl); + if (pdata->vaddr_gpio_mux_mic_ext_clk_ctl) + iounmap(pdata->vaddr_gpio_mux_mic_ext_clk_ctl); + if (pdata->vaddr_gpio_mux_sec_tlmm_ctl) + iounmap(pdata->vaddr_gpio_mux_sec_tlmm_ctl); + devm_kfree(&pdev->dev, pdata); + return ret; +} + +static int msm8952_asoc_machine_remove(struct platform_device *pdev) +{ + struct snd_soc_card *card = platform_get_drvdata(pdev); + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + if (pdata->us_euro_gpio > 0) { + dev_dbg(&pdev->dev, "%s free us_euro gpio %d\n", + __func__, pdata->us_euro_gpio); + gpio_free(pdata->us_euro_gpio); + pdata->us_euro_gpio = 0; + } + if (pdata->vaddr_gpio_mux_spkr_ctl) + iounmap(pdata->vaddr_gpio_mux_spkr_ctl); + if (pdata->vaddr_gpio_mux_mic_ctl) + iounmap(pdata->vaddr_gpio_mux_mic_ctl); + if (pdata->vaddr_gpio_mux_pcm_ctl) + iounmap(pdata->vaddr_gpio_mux_pcm_ctl); + if (pdata->vaddr_gpio_mux_quin_ctl) + iounmap(pdata->vaddr_gpio_mux_quin_ctl); + if (pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl) + iounmap(pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl); + if (pdata->vaddr_gpio_mux_mic_ext_clk_ctl) + iounmap(pdata->vaddr_gpio_mux_mic_ext_clk_ctl); + if (pdata->vaddr_gpio_mux_sec_tlmm_ctl) + iounmap(pdata->vaddr_gpio_mux_sec_tlmm_ctl); + msm895x_free_auxdev_mem(pdev); + + snd_soc_unregister_card(card); + return 0; +} + +static const struct of_device_id msm8952_asoc_machine_of_match[] = { + { .compatible = "qcom,msm8952-audio-slim-codec", }, + {}, +}; + +static struct platform_driver msm8952_asoc_machine_driver = { + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .pm = &snd_soc_pm_ops, + .of_match_table = msm8952_asoc_machine_of_match, + }, + .probe = msm8952_asoc_machine_probe, + .remove = msm8952_asoc_machine_remove, +}; + +static int __init msm8952_slim_machine_init(void) +{ + return platform_driver_register(&msm8952_asoc_machine_driver); +} +module_init(msm8952_slim_machine_init); + +static void __exit msm8952_slim_machine_exit(void) +{ + return platform_driver_unregister(&msm8952_asoc_machine_driver); +} +module_exit(msm8952_slim_machine_exit); + +MODULE_DESCRIPTION("ALSA SoC msm"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); +MODULE_DEVICE_TABLE(of, msm8952_asoc_machine_of_match); diff --git a/techpack/audio/asoc/msm8952-slimbus.h b/techpack/audio/asoc/msm8952-slimbus.h new file mode 100644 index 0000000000000000000000000000000000000000..12fab94bf10b12de27aa6affc916a3f78a03cf98 --- /dev/null +++ b/techpack/audio/asoc/msm8952-slimbus.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2015-2018, 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __MSM8952_SLIMBUS_AUDIO +#define __MSM8952_SLIMBUS_AUDIO + +#include + +struct ext_intf_cfg { + atomic_t quat_mi2s_clk_ref; + atomic_t quin_mi2s_clk_ref; + atomic_t auxpcm_mi2s_clk_ref; +}; + +enum { + PRIM_MI2S = 0, + SEC_MI2S, + TERT_MI2S, + QUAT_MI2S, + QUIN_MI2S, + MI2S_MAX, +}; + +struct msm8952_codec { + void* (*get_afe_config_fn)(struct snd_soc_component *component, + enum afe_config_type config_type); +}; + +struct msm8952_asoc_mach_data { + int ext_pa; + int us_euro_gpio; + struct delayed_work hs_detect_dwork; + struct snd_soc_codec *codec; + struct msm8952_codec msm8952_codec_fn; + struct ext_intf_cfg clk_ref; + struct snd_info_entry *codec_root; + void __iomem *vaddr_gpio_mux_spkr_ctl; + void __iomem *vaddr_gpio_mux_mic_ctl; + void __iomem *vaddr_gpio_mux_pcm_ctl; + void __iomem *vaddr_gpio_mux_quin_ctl; + void __iomem *vaddr_gpio_mux_qui_pcm_sec_mode_ctl; + void __iomem *vaddr_gpio_mux_mic_ext_clk_ctl; + void __iomem *vaddr_gpio_mux_sec_tlmm_ctl; + struct device_node *us_euro_gpio_p; + struct device_node *mi2s_gpio_p[MI2S_MAX]; +}; + +int msm_slim_0_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_0_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_1_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_2_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_4_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_4_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_5_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_6_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_5_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int msm8952_slimbus_2_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_quin_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_btsco_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_proxy_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_proxy_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_audrx_init(struct snd_soc_pcm_runtime *rtd); +int msm_mi2s_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int msm_snd_cpe_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int msm_tdm_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int msm_quat_mi2s_snd_startup(struct snd_pcm_substream *substream); +void msm_quat_mi2s_snd_shutdown(struct snd_pcm_substream *substream); + +int msm_quin_mi2s_snd_startup(struct snd_pcm_substream *substream); +void msm_quin_mi2s_snd_shutdown(struct snd_pcm_substream *substream); + +int msm_auxpcm_be_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_prim_auxpcm_startup(struct snd_pcm_substream *substream); +void msm_prim_auxpcm_shutdown(struct snd_pcm_substream *substream); + +int msm_tdm_startup(struct snd_pcm_substream *substream); +void msm_tdm_shutdown(struct snd_pcm_substream *substream); + +struct snd_soc_card *populate_snd_card_dailinks(struct device *dev); +int msm_slim_4_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm895x_wsa881x_init(struct snd_soc_component *component); +int msm8952_init_wsa_dev(struct platform_device *pdev, + struct snd_soc_card *card); +void msm895x_free_auxdev_mem(struct platform_device *pdev); +#endif diff --git a/techpack/audio/asoc/msm8952.c b/techpack/audio/asoc/msm8952.c new file mode 100644 index 0000000000000000000000000000000000000000..51047fd0f976555467800dbc3d19a31ce9ab90e1 --- /dev/null +++ b/techpack/audio/asoc/msm8952.c @@ -0,0 +1,3666 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2015-2016, 2018, 2020-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "msm-pcm-routing-v2.h" +#include +#include "msm8952.h" +#include "msm-pcm-voice-v2.h" + +#define DRV_NAME "msm8952-asoc-wcd" + +#define MSM_INT_DIGITAL_CODEC "msm-dig-codec" +#define PMIC_INT_ANALOG_CODEC "analog-codec" +#define EXT_SMART_PA "ext-smart-pa" + +enum btsco_rates { + RATE_8KHZ_ID, + RATE_16KHZ_ID, +}; + +/* dummy definition of deprecated FE DAI's*/ +enum { + MSM_FRONTEND_DAI_CS_VOICE = 39, + MSM_FRONTEND_DAI_VOICE2, + MSM_FRONTEND_DAI_VOLTE, + MSM_FRONTEND_DAI_VOWLAN, +}; + +static int msm8952_auxpcm_rate = 8000; +static int msm_btsco_rate = BTSCO_RATE_8KHZ; +static int msm_btsco_ch = 1; +static int msm_ter_mi2s_tx_ch = 1; +static int msm_pri_mi2s_rx_ch = 1; +static int msm_proxy_rx_ch = 2; +static int msm_vi_feed_tx_ch = 2; +static int mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int mi2s_rx_bits_per_sample = 16; +static int mi2s_rx_sample_rate = SAMPLING_RATE_48KHZ; + +static atomic_t quat_mi2s_clk_ref; +static atomic_t quin_mi2s_clk_ref; +static atomic_t auxpcm_mi2s_clk_ref; +static struct snd_info_entry *codec_root; + +static int msm8952_enable_dig_cdc_clk(struct snd_soc_component *component, + int enable, bool dapm); +static bool msm8952_swap_gnd_mic(struct snd_soc_component *component, + bool active); +static int msm8952_mclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +static int msm8952_dig_mclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +static int msm8952_wsa_switch_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +static int msm_dmic_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +/* + * Android L spec + * Need to report LINEIN + * if R/L channel impedance is larger than 5K ohm + */ +static struct wcd_mbhc_config mbhc_cfg = { + .read_fw_bin = false, + .calibration = NULL, + .detect_extn_cable = true, + .mono_stero_detection = false, + .swap_gnd_mic = NULL, + .hs_ext_micbias = false, + .key_code[0] = KEY_MEDIA, + .key_code[1] = KEY_VOICECOMMAND, + .key_code[2] = KEY_VOLUMEUP, + .key_code[3] = KEY_VOLUMEDOWN, + .key_code[4] = 0, + .key_code[5] = 0, + .key_code[6] = 0, + .key_code[7] = 0, + .linein_th = 5000, + .moisture_en = false, + .mbhc_micbias = 0, + .anc_micbias = 0, + .enable_anc_mic_detect = false, +}; + +static struct afe_clk_set mi2s_tx_clk = { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, +}; + +static struct afe_clk_set mi2s_rx_clk = { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, +}; + +static struct afe_clk_set wsa_ana_clk = { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_MCLK_1, + Q6AFE_LPASS_OSR_CLK_9_P600_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, +}; + +static char const *rx_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; +static const char *const mi2s_ch_text[] = {"One", "Two"}; +static const char *const loopback_mclk_text[] = {"DISABLE", "ENABLE"}; +static const char *const btsco_rate_text[] = {"BTSCO_RATE_8KHZ", + "BTSCO_RATE_16KHZ"}; +static const char *const proxy_rx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", "Eight"}; +static const char *const vi_feed_ch_text[] = {"One", "Two"}; +static char const *mi2s_rx_sample_rate_text[] = {"KHZ_48", + "KHZ_96", "KHZ_192"}; + +static inline int param_is_mask(int p) +{ + return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) && + (p <= SNDRV_PCM_HW_PARAM_LAST_MASK); +} + +static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p, int n) +{ + return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]); +} + +static void param_set_mask(struct snd_pcm_hw_params *p, int n, + unsigned int bit) +{ + if (bit >= SNDRV_MASK_MAX) + return; + if (param_is_mask(n)) { + struct snd_mask *m = param_to_mask(p, n); + + m->bits[0] = 0; + m->bits[1] = 0; + m->bits[bit >> 5] |= (1 << (bit & 31)); + } +} + +static int msm8952_mclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct msm_asoc_mach_data *pdata = NULL; + int ret = 0; + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + pdata = snd_soc_card_get_drvdata(component->card); + pr_debug("%s: event = %d\n", __func__, event); + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (pdata->mi2s_gpio_p[PRIM_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[PRIM_MI2S]); + if (ret) { + pr_err("%s: failed to enable pri gpios: %d\n", + __func__, ret); + break; + } + } + msm8952_enable_dig_cdc_clk(component, 1, true); + msm_anlg_cdc_mclk_enable(component, 1, true); + break; + case SND_SOC_DAPM_POST_PMD: + pr_debug("%s: mclk_res_ref = %d\n", + __func__, atomic_read(&pdata->int_mclk0_rsc_ref)); + if (pdata->mi2s_gpio_p[PRIM_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[PRIM_MI2S]); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %s", + __func__, "pri_i2s"); + return ret; + } + } + pr_debug("%s: disabling MCLK\n", __func__); + /* disable the codec mclk config*/ + msm_anlg_cdc_mclk_enable(component, 0, true); + msm8952_enable_dig_cdc_clk(component, 0, true); + break; + default: + pr_err("%s: invalid DAPM event %d\n", __func__, event); + return -EINVAL; + } + return 0; +} + +static int msm8952_dig_mclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct msm_asoc_mach_data *pdata = NULL; + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + pdata = snd_soc_card_get_drvdata(component->card); + pr_debug("%s: event = %d\n", __func__, event); + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + msm_digcdc_mclk_enable(component, 1, true); + msm8952_enable_dig_cdc_clk(component, 1, true); + break; + case SND_SOC_DAPM_POST_PMD: + /* disable the codec mclk config*/ + msm_digcdc_mclk_enable(component, 0, true); + msm8952_enable_dig_cdc_clk(component, 0, true); + break; + default: + pr_err("%s: invalid DAPM event %d\n", __func__, event); + return -EINVAL; + } + return 0; +} + +static int msm8952_wsa_switch_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + int ret = 0; + struct msm_asoc_mach_data *pdata = NULL; + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct on_demand_supply *supply; + + pdata = snd_soc_card_get_drvdata(component->card); + supply = &pdata->wsa_switch_supply; + if (!supply->supply) { + dev_err(component->card->dev, "%s: no wsa switch supply", + __func__); + return ret; + } + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (atomic_inc_return(&supply->ref) == 1) + ret = regulator_enable(supply->supply); + if (ret) + dev_err(component->card->dev, + "%s: Failed to enable wsa switch supply\n", + __func__); + break; + case SND_SOC_DAPM_POST_PMD: + if (atomic_read(&supply->ref) == 0) { + dev_dbg(component->card->dev, + "%s: wsa switch supply has been disabled.\n", + __func__); + return ret; + } + if (atomic_dec_return(&supply->ref) == 0) { + ret = regulator_disable(supply->supply); + if (ret) + dev_err(component->card->dev, + "%s: Failed to disable wsa switch supply\n", + __func__); + } + break; + default: + break; + } + + return ret; +} + +static int msm_dmic_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct msm_asoc_mach_data *pdata = NULL; + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + int ret = 0; + + pdata = snd_soc_card_get_drvdata(component->card); + pr_debug("%s: event = %d\n", __func__, event); + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + ret = msm_cdc_pinctrl_select_active_state(pdata->dmic_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be activated %sd", + __func__, "dmic_gpio"); + return ret; + } + break; + case SND_SOC_DAPM_POST_PMD: + ret = msm_cdc_pinctrl_select_sleep_state(pdata->dmic_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "dmic_gpio"); + return ret; + } + break; + default: + pr_err("%s: invalid DAPM event %d\n", __func__, event); + return -EINVAL; + } + return 0; +} + + +static const struct snd_soc_dapm_widget msm8952_dapm_widgets[] = { + + SND_SOC_DAPM_SUPPLY_S("MCLK", -1, SND_SOC_NOPM, 0, 0, + msm8952_mclk_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIC("Handset Mic", NULL), + SND_SOC_DAPM_MIC("Headset Mic", NULL), + SND_SOC_DAPM_MIC("Secondary Mic", NULL), + SND_SOC_DAPM_MIC("Digital Mic1", NULL), + SND_SOC_DAPM_MIC("Digital Mic2", NULL), + SND_SOC_DAPM_SUPPLY("VDD_WSA_SWITCH", SND_SOC_NOPM, 0, 0, + msm8952_wsa_switch_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), +}; + +static const struct snd_soc_dapm_widget msm8952_dig_dapm_widgets[] = { + SND_SOC_DAPM_SUPPLY_S("MCLK", -1, SND_SOC_NOPM, 0, 0, + msm8952_dig_mclk_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event), + SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event), +}; + +static int config_hph_compander_gpio(bool enable, + struct snd_soc_component *component) +{ + int ret = 0; + struct snd_soc_card *card = component->card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + pr_debug("%s: %s HPH Compander\n", __func__, + enable ? "Enable" : "Disable"); + + if (pdata->comp_gpio_p) { + if (enable) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->comp_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be activated %s\n", + __func__, "comp_gpio"); + goto done; + } + } else { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->comp_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be de-activated %s\n", + __func__, "comp_gpio"); + goto done; + } + } + } + +done: + return ret; +} + +int is_ext_spk_gpio_support(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata) +{ + const char *spk_ext_pa = "qcom,msm-spk-ext-pa"; + + pr_debug("%s:Enter\n", __func__); + + pdata->spk_ext_pa_gpio = of_get_named_gpio(pdev->dev.of_node, + spk_ext_pa, 0); + + if (pdata->spk_ext_pa_gpio < 0) { + dev_err(&pdev->dev, + "%s: missing %s in dt node\n", __func__, spk_ext_pa); + } else { + if (!gpio_is_valid(pdata->spk_ext_pa_gpio)) { + pr_err("%s: Invalid external speaker gpio: %d", + __func__, pdata->spk_ext_pa_gpio); + return -EINVAL; + } + } + return 0; +} + +static int enable_spk_ext_pa(struct snd_soc_component *component, int enable) +{ + struct snd_soc_card *card = component->card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret; + + if (!gpio_is_valid(pdata->spk_ext_pa_gpio)) { + pr_err("%s: Invalid gpio: %d\n", __func__, + pdata->spk_ext_pa_gpio); + return false; + } + + pr_debug("%s: %s external speaker PA\n", __func__, + enable ? "Enable" : "Disable"); + + if (enable) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->spk_ext_pa_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be de-activated %s\n", + __func__, "ext_spk_gpio"); + return ret; + } + gpio_set_value_cansleep(pdata->spk_ext_pa_gpio, enable); + } else { + gpio_set_value_cansleep(pdata->spk_ext_pa_gpio, enable); + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->spk_ext_pa_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be de-activated %s\n", + __func__, "ext_spk_gpio"); + return ret; + } + } + return 0; +} + +static bool msm8952_swap_gnd_mic(struct snd_soc_component *component, + bool active) +{ + struct snd_soc_card *card = component->card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int value = 0, ret = 0; + + pr_debug("%s: configure gpios for US_EU\n", __func__); + + if (!gpio_is_valid(pdata->us_euro_gpio)) { + pr_err("%s: Invalid gpio: %d", __func__, pdata->us_euro_gpio); + return false; + } + value = gpio_get_value_cansleep(pdata->us_euro_gpio); + if (pdata->us_euro_gpio_p) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->us_euro_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be activated %sd", + __func__, "us_eu_gpio"); + return false; + } + } + gpio_set_value_cansleep(pdata->us_euro_gpio, !value); + if (pdata->us_euro_gpio_p) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->us_euro_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "us_eu_gpio"); + return false; + } + } + pr_debug("%s: swap select switch %d to %d\n", __func__, value, !value); + return true; +} + +/* Validate whether US EU switch is present or not */ +int is_us_eu_switch_gpio_support(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata) +{ + /* check if US-EU GPIO is supported */ + pdata->us_euro_gpio = of_get_named_gpio(pdev->dev.of_node, + "qcom,cdc-us-euro-gpios", 0); + if (pdata->us_euro_gpio < 0) { + dev_err(&pdev->dev, + "property %s in node %s not found %d\n", + "qcom,cdc-us-euro-gpios", pdev->dev.of_node->full_name, + pdata->us_euro_gpio); + } else { + if (!gpio_is_valid(pdata->us_euro_gpio)) { + pr_err("%s: Invalid gpio: %d", __func__, + pdata->us_euro_gpio); + return -EINVAL; + } + pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,cdc-us-eu-gpios", 0); + mbhc_cfg.swap_gnd_mic = msm8952_swap_gnd_mic; + } + return 0; +} + +static int msm_proxy_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_proxy_rx_ch = %d\n", __func__, + msm_proxy_rx_ch); + ucontrol->value.integer.value[0] = msm_proxy_rx_ch - 1; + return 0; +} + +static int msm_proxy_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_proxy_rx_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_proxy_rx_ch = %d\n", __func__, + msm_proxy_rx_ch); + return 0; +} + +static int msm_auxpcm_be_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = + hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = + hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); + + rate->min = rate->max = msm8952_auxpcm_rate; + channels->min = channels->max = 1; + + return 0; +} + +static int msm_mi2s_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s: Num of channels = %d Sample rate = %d\n", __func__, + msm_pri_mi2s_rx_ch, mi2s_rx_sample_rate); + rate->min = rate->max = mi2s_rx_sample_rate; + channels->min = channels->max = msm_pri_mi2s_rx_ch; + + return 0; +} + +static int msm_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s(), channel:%d\n", __func__, msm_ter_mi2s_tx_ch); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + SNDRV_PCM_FORMAT_S16_LE); + rate->min = rate->max = 48000; + channels->min = channels->max = msm_ter_mi2s_tx_ch; + + return 0; +} + +static int msm_senary_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + rate->min = rate->max = 48000; + channels->min = channels->max = 2; + + return 0; +} + +static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + rate->min = rate->max = 48000; + channels->min = channels->max = 2; + + return 0; +} + +static int msm_btsco_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + rate->min = rate->max = msm_btsco_rate; + channels->min = channels->max = msm_btsco_ch; + + return 0; +} + +static int msm_proxy_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s: msm_proxy_rx_ch =%d\n", __func__, msm_proxy_rx_ch); + + if (channels->max < 2) + channels->min = channels->max = 2; + channels->min = channels->max = msm_proxy_rx_ch; + rate->min = rate->max = 48000; + return 0; +} + +static int msm_proxy_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + rate->min = rate->max = 48000; + return 0; +} + +static int msm_mi2s_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + mi2s_rx_bit_format); + else + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + SNDRV_PCM_FORMAT_S16_LE); + return 0; +} +static int msm8952_get_clk_id(int port_id) +{ + switch (port_id) { + case AFE_PORT_ID_PRIMARY_MI2S_RX: + return Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT; + case AFE_PORT_ID_SECONDARY_MI2S_RX: + return Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT; + case AFE_PORT_ID_TERTIARY_MI2S_TX: + return Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT; + case AFE_PORT_ID_QUATERNARY_MI2S_RX: + case AFE_PORT_ID_QUATERNARY_MI2S_TX: + return Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT; + case AFE_PORT_ID_QUINARY_MI2S_RX: + case AFE_PORT_ID_QUINARY_MI2S_TX: + return Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT; + case AFE_PORT_ID_SENARY_MI2S_TX: + return Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT; + default: + pr_err("%s: invalid port_id: 0x%x\n", __func__, port_id); + return -EINVAL; + } +} + +static int msm8952_get_port_id(int be_id) +{ + switch (be_id) { + case MSM_BACKEND_DAI_PRI_MI2S_RX: + return AFE_PORT_ID_PRIMARY_MI2S_RX; + case MSM_BACKEND_DAI_SECONDARY_MI2S_RX: + return AFE_PORT_ID_SECONDARY_MI2S_RX; + case MSM_BACKEND_DAI_TERTIARY_MI2S_TX: + return AFE_PORT_ID_TERTIARY_MI2S_TX; + case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX: + return AFE_PORT_ID_QUATERNARY_MI2S_RX; + case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX: + return AFE_PORT_ID_QUATERNARY_MI2S_TX; + case MSM_BACKEND_DAI_QUINARY_MI2S_RX: + return AFE_PORT_ID_QUINARY_MI2S_RX; + case MSM_BACKEND_DAI_QUINARY_MI2S_TX: + return AFE_PORT_ID_QUINARY_MI2S_TX; + case MSM_BACKEND_DAI_SENARY_MI2S_TX: + return AFE_PORT_ID_SENARY_MI2S_TX; + default: + pr_err("%s: Invalid.id: %d\n", __func__, be_id); + return -EINVAL; + } +} + +static bool is_mi2s_rx_port(int port_id) +{ + bool ret = false; + + switch (port_id) { + case AFE_PORT_ID_PRIMARY_MI2S_RX: + case AFE_PORT_ID_SECONDARY_MI2S_RX: + case AFE_PORT_ID_QUATERNARY_MI2S_RX: + case AFE_PORT_ID_QUINARY_MI2S_RX: + ret = true; + break; + default: + break; + } + return ret; +} + +static uint32_t get_mi2s_rx_clk_val(int port_id) +{ + uint32_t clk_val = 0; + + /* + * Derive clock value based on sample rate, bits per sample and + * channel count is used as 2 + */ + if (is_mi2s_rx_port(port_id)) + clk_val = (mi2s_rx_sample_rate * mi2s_rx_bits_per_sample * 2); + + pr_debug("%s: MI2S Rx bit clock value: 0x%0x\n", __func__, clk_val); + return clk_val; +} + +static int msm_mi2s_sclk_ctl(struct snd_pcm_substream *substream, bool enable) +{ + int ret = 0; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int port_id = 0; + + port_id = msm8952_get_port_id(rtd->dai_link->id); + if (port_id < 0) { + pr_err("%s: Invalid port_id\n", __func__); + return -EINVAL; + } + if (enable) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mi2s_rx_clk.enable = enable; + mi2s_rx_clk.clk_id = + msm8952_get_clk_id(port_id); + mi2s_rx_clk.clk_freq_in_hz = + get_mi2s_rx_clk_val(port_id); + ret = afe_set_lpass_clock_v2(port_id, + &mi2s_rx_clk); + } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + mi2s_tx_clk.enable = enable; + mi2s_tx_clk.clk_id = + msm8952_get_clk_id(port_id); + mi2s_tx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ; + ret = afe_set_lpass_clock_v2(port_id, + &mi2s_tx_clk); + } else { + pr_err("%s:Not valid substream.\n", __func__); + } + + if (ret < 0) + pr_err("%s:afe_set_lpass_clock_v2 failed\n", __func__); + } else { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mi2s_rx_clk.enable = enable; + mi2s_rx_clk.clk_id = + msm8952_get_clk_id(port_id); + ret = afe_set_lpass_clock_v2(port_id, + &mi2s_rx_clk); + } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + mi2s_tx_clk.enable = enable; + mi2s_tx_clk.clk_id = + msm8952_get_clk_id(port_id); + ret = afe_set_lpass_clock_v2(port_id, + &mi2s_tx_clk); + } else { + pr_err("%s:Not valid substream.\n", __func__); + } + + if (ret < 0) + pr_err("%s:afe_set_lpass_clock_v2 failed\n", __func__); + } + return ret; +} + +static int msm8952_enable_dig_cdc_clk(struct snd_soc_component *component, + int enable, bool dapm) +{ + int ret = 0; + struct msm_asoc_mach_data *pdata = NULL; + + pdata = snd_soc_card_get_drvdata(component->card); + pr_debug("%s: enable %d mclk ref counter %d\n", + __func__, enable, + atomic_read(&pdata->int_mclk0_rsc_ref)); + if (enable) { + if (!atomic_read(&pdata->int_mclk0_rsc_ref)) { + cancel_delayed_work_sync( + &pdata->disable_int_mclk0_work); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if (atomic_read(&pdata->int_mclk0_enabled) == false) { + pdata->digital_cdc_core_clk.enable = 1; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s: failed to enable CCLK\n", + __func__); + mutex_unlock( + &pdata->cdc_int_mclk0_mutex); + return ret; + } + pr_debug("enabled digital codec core clk\n"); + atomic_set(&pdata->int_mclk0_enabled, true); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + } + atomic_inc(&pdata->int_mclk0_rsc_ref); + } else { + cancel_delayed_work_sync(&pdata->disable_int_mclk0_work); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if (atomic_read(&pdata->int_mclk0_enabled) == true) { + pdata->digital_cdc_core_clk.clk_freq_in_hz = + DEFAULT_MCLK_RATE; + pdata->digital_cdc_core_clk.enable = 0; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) + pr_err("%s: failed to disable CCLK\n", + __func__); + atomic_set(&pdata->int_mclk0_enabled, false); + atomic_set(&pdata->int_mclk0_rsc_ref, 0); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + } + return ret; +} + +static int msm_btsco_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_btsco_rate = %d", __func__, msm_btsco_rate); + ucontrol->value.integer.value[0] = msm_btsco_rate; + return 0; +} + +static int msm_btsco_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case RATE_8KHZ_ID: + msm_btsco_rate = BTSCO_RATE_8KHZ; + break; + case RATE_16KHZ_ID: + msm_btsco_rate = BTSCO_RATE_16KHZ; + break; + default: + msm_btsco_rate = BTSCO_RATE_8KHZ; + break; + } + + pr_debug("%s: msm_btsco_rate = %d\n", __func__, msm_btsco_rate); + return 0; +} + +static int mi2s_rx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + + switch (mi2s_rx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: mi2s_rx_bit_format = %d, ucontrol value = %ld\n", + __func__, mi2s_rx_bit_format, + ucontrol->value.integer.value[0]); + + return 0; +} + +static int mi2s_rx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 2: + mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + mi2s_rx_bits_per_sample = 32; + break; + case 1: + mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + mi2s_rx_bits_per_sample = 32; + break; + case 0: + default: + mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + mi2s_rx_bits_per_sample = 16; + break; + } + return 0; +} + +static int loopback_mclk_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s\n", __func__); + return 0; +} + +static int loopback_mclk_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = -EINVAL; + struct msm_asoc_mach_data *pdata = NULL; + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + + pdata = snd_soc_card_get_drvdata(component->card); + pr_debug("%s: int_mclk0_rsc_ref %d enable %ld\n", + __func__, atomic_read(&pdata->int_mclk0_rsc_ref), + ucontrol->value.integer.value[0]); + switch (ucontrol->value.integer.value[0]) { + case 1: + if (pdata->mi2s_gpio_p[PRIM_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[PRIM_MI2S]); + if (ret) { + pr_err("%s: failed to enable pri gpios: %d\n", + __func__, ret); + break; + } + } + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if ((!atomic_read(&pdata->int_mclk0_rsc_ref)) && + (!atomic_read(&pdata->int_mclk0_enabled))) { + pdata->digital_cdc_core_clk.enable = 1; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s: failed to enable the MCLK: %d\n", + __func__, ret); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + if (pdata->mi2s_gpio_p[PRIM_MI2S]) { + ret = + msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[PRIM_MI2S]); + if (ret) + pr_err("%s disable gpio fail\n", + __func__); + } + break; + } + atomic_set(&pdata->int_mclk0_enabled, true); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + atomic_inc(&pdata->int_mclk0_rsc_ref); + msm_anlg_cdc_mclk_enable(component, 1, true); + break; + case 0: + if (atomic_read(&pdata->int_mclk0_rsc_ref) <= 0) + break; + msm_anlg_cdc_mclk_enable(component, 0, true); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if ((!atomic_dec_return(&pdata->int_mclk0_rsc_ref)) && + (atomic_read(&pdata->int_mclk0_enabled))) { + pdata->digital_cdc_core_clk.enable = 0; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s: failed to disable the CCLK: %d\n", + __func__, ret); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + break; + } + atomic_set(&pdata->int_mclk0_enabled, false); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + if (pdata->mi2s_gpio_p[PRIM_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[PRIM_MI2S]); + if (ret) + pr_err("%s: failed to disable pri gpios: %d\n", + __func__, ret); + } + break; + default: + pr_err("%s: Unexpected input value\n", __func__); + break; + } + return ret; +} + +static int msm_pri_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_pri_mi2s_rx_ch = %d\n", __func__, + msm_pri_mi2s_rx_ch); + ucontrol->value.integer.value[0] = msm_pri_mi2s_rx_ch - 1; + return 0; +} + +static int msm_pri_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_pri_mi2s_rx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_pri_mi2s_rx_ch = %d\n", __func__, msm_pri_mi2s_rx_ch); + return 1; +} + +static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (mi2s_rx_sample_rate) { + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: sample_rate_val = %d\n", __func__, + sample_rate_val); + + return 0; +} + +static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 1: + mi2s_rx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 2: + mi2s_rx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 0: + default: + mi2s_rx_sample_rate = SAMPLING_RATE_48KHZ; + break; + } + pr_debug("%s: mi2s_rx_sample_rate = %d\n", __func__, + mi2s_rx_sample_rate); + return 0; +} + +static int msm_ter_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_ter_mi2s_tx_ch = %d\n", __func__, + msm_ter_mi2s_tx_ch); + ucontrol->value.integer.value[0] = msm_ter_mi2s_tx_ch - 1; + return 0; +} + +static int msm_ter_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_ter_mi2s_tx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_ter_mi2s_tx_ch = %d\n", __func__, msm_ter_mi2s_tx_ch); + return 1; +} + +static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = (msm_vi_feed_tx_ch/2 - 1); + pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__, + ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_vi_feed_tx_ch = + roundup_pow_of_two(ucontrol->value.integer.value[0] + 2); + + pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch); + return 1; +} + +static const struct soc_enum msm_snd_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_bit_format_text), + rx_bit_format_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mi2s_ch_text), + mi2s_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(loopback_mclk_text), + loopback_mclk_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(btsco_rate_text), + btsco_rate_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(proxy_rx_ch_text), + proxy_rx_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vi_feed_ch_text), + vi_feed_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mi2s_rx_sample_rate_text), + mi2s_rx_sample_rate_text), +}; + +static const struct snd_kcontrol_new msm_snd_controls[] = { + SOC_ENUM_EXT("MI2S_RX Format", msm_snd_enum[0], + mi2s_rx_bit_format_get, mi2s_rx_bit_format_put), + SOC_ENUM_EXT("MI2S_TX Channels", msm_snd_enum[1], + msm_ter_mi2s_tx_ch_get, msm_ter_mi2s_tx_ch_put), + SOC_ENUM_EXT("MI2S_RX Channels", msm_snd_enum[1], + msm_pri_mi2s_rx_ch_get, msm_pri_mi2s_rx_ch_put), + SOC_ENUM_EXT("Loopback MCLK", msm_snd_enum[2], + loopback_mclk_get, loopback_mclk_put), + SOC_ENUM_EXT("Internal BTSCO SampleRate", msm_snd_enum[3], + msm_btsco_rate_get, msm_btsco_rate_put), + SOC_ENUM_EXT("PROXY_RX Channels", msm_snd_enum[4], + msm_proxy_rx_ch_get, msm_proxy_rx_ch_put), + SOC_ENUM_EXT("VI_FEED_TX Channels", msm_snd_enum[5], + msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put), + SOC_ENUM_EXT("MI2S_RX SampleRate", msm_snd_enum[6], + mi2s_rx_sample_rate_get, mi2s_rx_sample_rate_put), +}; + +static int msm8952_enable_wsa_mclk(struct snd_soc_card *card, bool enable) +{ + int ret = 0; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + mutex_lock(&pdata->wsa_mclk_mutex); + if (enable) { + if (!atomic_read(&pdata->wsa_int_mclk0_rsc_ref)) { + wsa_ana_clk.enable = enable; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &wsa_ana_clk); + if (ret < 0) { + pr_err("%s: failed to enable mclk %d\n", + __func__, ret); + goto done; + } + } + atomic_inc(&pdata->wsa_int_mclk0_rsc_ref); + } else { + if (!atomic_read(&pdata->wsa_int_mclk0_rsc_ref)) + goto done; + if (!atomic_dec_return(&pdata->wsa_int_mclk0_rsc_ref)) { + wsa_ana_clk.enable = enable; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &wsa_ana_clk); + if (ret < 0) { + pr_err("%s: failed to disable mclk %d\n", + __func__, ret); + goto done; + } + } + } + +done: + mutex_unlock(&pdata->wsa_mclk_mutex); + return ret; +} + +static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + if (!q6core_is_adsp_ready()) { + pr_err("%s(): adsp not ready\n", __func__); + return -EINVAL; + } + + /* + * configure the slave select to + * invalid state for internal codec + */ + if (pdata->vaddr_gpio_mux_spkr_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_spkr_ctl); + val = val | 0x00010000; + iowrite32(val, pdata->vaddr_gpio_mux_spkr_ctl); + } + + if (pdata->vaddr_gpio_mux_mic_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ctl); + val = val | 0x00200000; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ctl); + } + + ret = msm_mi2s_sclk_ctl(substream, true); + if (ret < 0) { + pr_err("%s: failed to enable sclk %d\n", + __func__, ret); + return ret; + } + if (card->aux_dev && substream->stream == + SNDRV_PCM_STREAM_PLAYBACK) { + ret = msm8952_enable_wsa_mclk(card, true); + if (ret < 0) { + pr_err("%s: failed to enable mclk for wsa %d\n", + __func__, ret); + return ret; + } + } + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) + pr_err("%s: set fmt cpu dai failed; ret=%d\n", __func__, ret); + + return ret; +} + +static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + int ret; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed; ret=%d\n", __func__, + ret); + if (card->aux_dev && substream->stream == + SNDRV_PCM_STREAM_PLAYBACK) { + ret = msm8952_enable_wsa_mclk(card, false); + if (ret < 0) { + pr_err("%s: failed to disable mclk for wsa %d\n", + __func__, ret); + } + } +} + +static int msm_prim_auxpcm_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_component *dig_cdc = NULL; + struct snd_soc_card *card = rtd->card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s\n", + __func__, substream->name); + + if (!q6core_is_adsp_ready()) { + pr_err("%s(): adsp not ready\n", __func__); + return -EINVAL; + } + + if (pdata->snd_card_val == INT_DIG_SND_CARD) + dig_cdc = snd_soc_rtdcom_lookup(rtd, "msm_digital_codec"); + else + dig_cdc = rtd->codec_dais[DIG_CDC]->component; + + /* mux config to route the AUX MI2S */ + if (pdata->vaddr_gpio_mux_mic_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ctl); + val = val | 0x2; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ctl); + } + if (pdata->vaddr_gpio_mux_pcm_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_pcm_ctl); + val = val | 0x1; + iowrite32(val, pdata->vaddr_gpio_mux_pcm_ctl); + } + msm8952_enable_dig_cdc_clk(dig_cdc, 1, true); + atomic_inc(&auxpcm_mi2s_clk_ref); + + /* enable the gpio's used for the external AUXPCM interface */ + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) + pr_err("%s(): configure gpios failed = %s\n", + __func__, "quat_i2s"); + } + return ret; +} + +static void msm_prim_auxpcm_shutdown(struct snd_pcm_substream *substream) +{ + int ret; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_component *dig_cdc = NULL; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + pr_debug("%s(): substream = %s\n", + __func__, substream->name); + + if (pdata->snd_card_val == INT_DIG_SND_CARD) + dig_cdc = snd_soc_rtdcom_lookup(rtd, "msm_digital_codec"); + else + dig_cdc = rtd->codec_dais[DIG_CDC]->component; + + if (atomic_read(&pdata->int_mclk0_rsc_ref) > 0) { + atomic_dec(&pdata->int_mclk0_rsc_ref); + pr_debug("%s: decrementing mclk_res_ref %d\n", + __func__, atomic_read(&pdata->int_mclk0_rsc_ref)); + } + if (atomic_read(&auxpcm_mi2s_clk_ref) > 0) + atomic_dec(&auxpcm_mi2s_clk_ref); + if ((atomic_read(&auxpcm_mi2s_clk_ref) == 0) && + (atomic_read(&pdata->int_mclk0_rsc_ref) == 0)) { + msm8952_enable_dig_cdc_clk(dig_cdc, 0, true); + } + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) + pr_err("%s(): configure gpios failed = %s\n", + __func__, "quat_i2s"); + } +} + +static int msm_sec_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + pr_info("%s: Secondary Mi2s does not support capture\n", + __func__); + return 0; + } + + if (!q6core_is_adsp_ready()) { + pr_err("%s(): adsp not ready\n", __func__); + return -EINVAL; + } + + if ((pdata->ext_pa & SEC_MI2S_ID) == SEC_MI2S_ID) { + if (pdata->vaddr_gpio_mux_spkr_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_spkr_ctl); + val = val | 0x0004835c; + iowrite32(val, pdata->vaddr_gpio_mux_spkr_ctl); + } + ret = msm_mi2s_sclk_ctl(substream, true); + if (ret < 0) { + pr_err("failed to enable sclk\n"); + return ret; + } + pr_debug("%s(): SEC I2S gpios turned on = %s\n", __func__, + "sec_i2s"); + if (pdata->mi2s_gpio_p[SEC_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[SEC_MI2S]); + if (ret < 0) { + pr_err("%s: gpio set cannot be activated %sd", + __func__, "sec_i2s"); + goto err; + } + } + } else { + pr_err("%s: error codec type\n", __func__); + } + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) { + pr_err("%s: set fmt cpu dai failed\n", __func__); + if (pdata->mi2s_gpio_p[SEC_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[SEC_MI2S]); + if (ret < 0) { + pr_err("%s: gpio de-activate error %s", + __func__, "sec_i2s"); + goto err; + } + } + } + return ret; +err: + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("failed to disable sclk\n"); + return ret; +} + +static void msm_sec_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + int ret; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + if ((pdata->ext_pa & SEC_MI2S_ID) == SEC_MI2S_ID) { + if (pdata->mi2s_gpio_p[SEC_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[SEC_MI2S]); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated: %sd", + __func__, "sec_i2s"); + return; + } + } + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed\n", __func__); + } +} + +static int msm_quat_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + if (!q6core_is_adsp_ready()) { + pr_err("%s(): adsp not ready\n", __func__); + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_mic_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ctl); + val = val | 0x02020002; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ctl); + } + ret = msm_mi2s_sclk_ctl(substream, true); + if (ret < 0) { + pr_err("failed to enable sclk\n"); + return ret; + } + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) { + pr_err("failed to enable codec gpios\n"); + goto err; + } + } + if (atomic_inc_return(&quat_mi2s_clk_ref) == 1) { + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) + pr_err("%s: set fmt cpu dai failed\n", __func__); + } + return ret; +err: + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("failed to disable sclk\n"); + return ret; +} + +static void msm_quat_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int ret = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed\n", __func__); + if (atomic_read(&quat_mi2s_clk_ref) > 0) + atomic_dec(&quat_mi2s_clk_ref); + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "quat_i2s"); + return; + } + } +} + +static int msm_quin_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + if (!q6core_is_adsp_ready()) { + pr_err("%s(): adsp not ready\n", __func__); + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_quin_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_quin_ctl); + val = val | 0x00000001; + iowrite32(val, pdata->vaddr_gpio_mux_quin_ctl); + } else { + return -EINVAL; + } + ret = msm_mi2s_sclk_ctl(substream, true); + if (ret < 0) { + pr_err("failed to enable sclk\n"); + return ret; + } + if (pdata->mi2s_gpio_p[QUIN_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUIN_MI2S]); + if (ret < 0) { + pr_err("failed to enable codec gpios\n"); + goto err; + } + } + if (atomic_inc_return(&quin_mi2s_clk_ref) == 1) { + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) + pr_err("%s: set fmt cpu dai failed\n", __func__); + } + return ret; +err: + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("failed to disable sclk\n"); + return ret; +} + +static void msm_quin_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int ret = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed\n", __func__); + if (atomic_read(&quin_mi2s_clk_ref) > 0) + atomic_dec(&quin_mi2s_clk_ref); + if (pdata->mi2s_gpio_p[QUIN_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUIN_MI2S]); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "quin_i2s"); + return; + } + } +} + +static void *def_msm8952_wcd_mbhc_cal(void) +{ + void *msm8952_wcd_cal; + struct wcd_mbhc_btn_detect_cfg *btn_cfg; + u16 *btn_low, *btn_high; + + msm8952_wcd_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS, + WCD_MBHC_DEF_RLOADS), GFP_KERNEL); + if (!msm8952_wcd_cal) + return NULL; + +#define S(X, Y) ((WCD_MBHC_CAL_PLUG_TYPE_PTR(msm8952_wcd_cal)->X) = (Y)) + S(v_hs_max, 1500); +#undef S +#define S(X, Y) ((WCD_MBHC_CAL_BTN_DET_PTR(msm8952_wcd_cal)->X) = (Y)) + S(num_btn, WCD_MBHC_DEF_BUTTONS); +#undef S + + + btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(msm8952_wcd_cal); + btn_low = btn_cfg->_v_btn_low; + btn_high = ((void *)&btn_cfg->_v_btn_low) + + (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn); + + /* + * In SW we are maintaining two sets of threshold register + * one for current source and another for Micbias. + * all btn_low corresponds to threshold for current source + * all bt_high corresponds to threshold for Micbias + * Below thresholds are based on following resistances + * 0-70 == Button 0 + * 110-180 == Button 1 + * 210-290 == Button 2 + * 360-680 == Button 3 + */ + btn_low[0] = 75; + btn_high[0] = 75; + btn_low[1] = 150; + btn_high[1] = 150; + btn_low[2] = 225; + btn_high[2] = 225; + btn_low[3] = 450; + btn_high[3] = 450; + btn_low[4] = 500; + btn_high[4] = 500; + + return msm8952_wcd_cal; +} + +static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_component *dig_cdc = + snd_soc_rtdcom_lookup(rtd, "msm_digital_codec"); + struct snd_soc_component *ana_cdc = + snd_soc_rtdcom_lookup(rtd, "pmic_analog_codec"); + struct snd_soc_dapm_context *dapm; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(rtd->card); + struct snd_card *card; + int ret = -ENOMEM; + + if (!dig_cdc || !ana_cdc) { + pr_err("%s: component is NULL\n", __func__); + return -EINVAL; + } + dapm = snd_soc_component_get_dapm(ana_cdc); + ret = snd_soc_add_component_controls(ana_cdc, msm_snd_controls, + ARRAY_SIZE(msm_snd_controls)); + if (ret < 0) { + pr_err("%s: add_codec_controls failed: %d\n", + __func__, ret); + return ret; + } + + snd_soc_dapm_new_controls(dapm, msm8952_dapm_widgets, + ARRAY_SIZE(msm8952_dapm_widgets)); + + snd_soc_dapm_ignore_suspend(dapm, "Handset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Secondary Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2"); + + snd_soc_dapm_ignore_suspend(dapm, "EAR"); + snd_soc_dapm_ignore_suspend(dapm, "HEADPHONE"); + snd_soc_dapm_ignore_suspend(dapm, "SPK_OUT"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC2"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC3"); + snd_soc_dapm_sync(dapm); + + dapm = snd_soc_component_get_dapm(dig_cdc); + snd_soc_dapm_ignore_suspend(dapm, "DMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC2"); + snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK OUT"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT"); + + snd_soc_dapm_sync(dapm); + + msm_anlg_cdc_spk_ext_pa_cb(enable_spk_ext_pa, ana_cdc); + msm_dig_cdc_hph_comp_cb(config_hph_compander_gpio, dig_cdc); + + mbhc_cfg.calibration = def_msm8952_wcd_mbhc_cal(); + if (mbhc_cfg.calibration) { + ret = msm_anlg_cdc_hs_detect(ana_cdc, &mbhc_cfg); + if (ret) { + kfree(mbhc_cfg.calibration); + return ret; + } + } + card = rtd->card->snd_card; + if (!codec_root) + codec_root = snd_info_create_subdir(card->module, "codecs", + card->proc_root); + if (!codec_root) { + pr_debug("%s: Cannot create codecs module entry\n", __func__); + goto done; + } + pdata->codec_root = codec_root; + msm_dig_codec_info_create_codec_entry(codec_root, dig_cdc); + msm_anlg_codec_info_create_codec_entry(codec_root, ana_cdc); +done: + return 0; +} + +static int msm_dig_audrx_init(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_component *dig_cdc = + snd_soc_rtdcom_lookup(rtd, "msm_digital_codec"); + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(rtd->card); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dig_cdc); + struct snd_card *card = NULL; + + snd_soc_add_component_controls(dig_cdc, msm_snd_controls, + ARRAY_SIZE(msm_snd_controls)); + snd_soc_dapm_new_controls(dapm, msm8952_dig_dapm_widgets, + ARRAY_SIZE(msm8952_dig_dapm_widgets)); + + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2"); + + snd_soc_dapm_ignore_suspend(dapm, "DMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC2"); + + snd_soc_dapm_sync(dapm); + + card = rtd->card->snd_card; + if (!codec_root) { + codec_root = snd_info_create_subdir(card->module, "codecs", + card->proc_root); + pr_debug("%s: Cannot create codecs module entry\n", __func__); + goto done; + } + pdata->codec_root = codec_root; + msm_dig_codec_info_create_codec_entry(codec_root, dig_cdc); +done: + return 0; +} + +static struct snd_soc_ops msm8952_quat_mi2s_be_ops = { + .startup = msm_quat_mi2s_snd_startup, + .hw_params = msm_mi2s_snd_hw_params, + .shutdown = msm_quat_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm8952_quin_mi2s_be_ops = { + .startup = msm_quin_mi2s_snd_startup, + .hw_params = msm_mi2s_snd_hw_params, + .shutdown = msm_quin_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm8952_sec_mi2s_be_ops = { + .startup = msm_sec_mi2s_snd_startup, + .hw_params = msm_mi2s_snd_hw_params, + .shutdown = msm_sec_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm8952_mi2s_be_ops = { + .startup = msm_mi2s_snd_startup, + .hw_params = msm_mi2s_snd_hw_params, + .shutdown = msm_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm_pri_auxpcm_be_ops = { + .startup = msm_prim_auxpcm_startup, + .shutdown = msm_prim_auxpcm_shutdown, +}; + +struct snd_soc_dai_link_component dlc_rx1[] = { + { + .of_node = NULL, + .dai_name = "msm_dig_cdc_dai_rx1", + }, + { + .of_node = NULL, + .dai_name = "msm_anlg_cdc_i2s_rx1", + }, +}; + +struct snd_soc_dai_link_component dlc_tx1[] = { + { + .of_node = NULL, + .dai_name = "msm_dig_cdc_dai_tx1", + }, + { + .of_node = NULL, + .dai_name = "msm_anlg_cdc_i2s_tx1", + }, +}; + +struct snd_soc_dai_link_component dlc_vifeed[] = { + { + .of_node = NULL, + .dai_name = "msm_dig_cdc_dai_vifeed", + }, + { + .of_node = NULL, + .dai_name = "msm_anlg_vifeedback", + }, +}; + +/* Digital audio interface glue - connects codec <---> CPU */ +static struct snd_soc_dai_link msm8952_dai[] = { + /* FrontEnd DAI Links */ + {/* hw:x,0 */ + .name = "MSM8952 Media1", + .stream_name = "MultiMedia1", + .cpu_dai_name = "MultiMedia1", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA1 + }, + {/* hw:x,1 */ + .name = "MSM8952 Media2", + .stream_name = "MultiMedia2", + .cpu_dai_name = "MultiMedia2", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA2, + }, + {/* hw:x,2 */ + .name = "Circuit-Switch Voice", + .stream_name = "CS-Voice", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_CS_VOICE, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,3 */ + .name = "MSM VoIP", + .stream_name = "VoIP", + .cpu_dai_name = "VoIP", + .platform_name = "msm-voip-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_VOIP, + }, + {/* hw:x,4 */ + .name = "MSM8X16 ULL", + .stream_name = "ULL", + .cpu_dai_name = "MultiMedia3", + .platform_name = "msm-pcm-dsp.2", + .dynamic = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA3, + }, + /* Hostless PCM purpose */ + {/* hw:x,5 */ + .name = "Primary MI2S_RX Hostless", + .stream_name = "Primary MI2S_RX Hostless", + .cpu_dai_name = "PRI_MI2S_RX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dailink has playback support */ + .ignore_pmdown_time = 1, + /* This dainlink has MI2S support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,6 */ + .name = "INT_FM Hostless", + .stream_name = "INT_FM Hostless", + .cpu_dai_name = "INT_FM_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,7 */ + .name = "MSM AFE-PCM RX", + .stream_name = "AFE-PROXY RX", + .cpu_dai_name = "msm-dai-q6-dev.241", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .platform_name = "msm-pcm-afe", + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + }, + {/* hw:x,8 */ + .name = "MSM AFE-PCM TX", + .stream_name = "AFE-PROXY TX", + .cpu_dai_name = "msm-dai-q6-dev.240", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .platform_name = "msm-pcm-afe", + .ignore_suspend = 1, + }, + {/* hw:x,9 */ + .name = "MSM8952 Compress1", + .stream_name = "Compress1", + .cpu_dai_name = "MultiMedia4", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dainlink has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA4, + }, + {/* hw:x,10 */ + .name = "AUXPCM Hostless", + .stream_name = "AUXPCM Hostless", + .cpu_dai_name = "AUXPCM_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,11 */ + .name = "Tertiary MI2S_TX Hostless", + .stream_name = "Tertiary MI2S_TX Hostless", + .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,12 */ + .name = "MSM8x16 LowLatency", + .stream_name = "MultiMedia5", + .cpu_dai_name = "MultiMedia5", + .platform_name = "msm-pcm-dsp.1", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | + ASYNC_DPCM_SND_SOC_HW_PARAMS, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA5, + }, + {/* hw:x,13 */ + .name = "Voice2", + .stream_name = "Voice2", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOICE2, + }, + {/* hw:x,14 */ + .name = "MSM8x16 Media9", + .stream_name = "MultiMedia9", + .cpu_dai_name = "MultiMedia9", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* This dailink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA9, + }, + { /* hw:x,15 */ + .name = "VoLTE", + .stream_name = "VoLTE", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOLTE, + }, + { /* hw:x,16 */ + .name = "VoWLAN", + .stream_name = "VoWLAN", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOWLAN, + }, + {/* hw:x,17 */ + .name = "INT_HFP_BT Hostless", + .stream_name = "INT_HFP_BT Hostless", + .cpu_dai_name = "INT_HFP_BT_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,18 */ + .name = "MSM8916 HFP", + .stream_name = "MultiMedia6", + .cpu_dai_name = "MultiMedia6", + .platform_name = "msm-pcm-loopback", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA6, + }, + /* LSM FE */ + {/* hw:x,19 */ + .name = "Listen 1 Audio Service", + .stream_name = "Listen 1 Audio Service", + .cpu_dai_name = "LSM1", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM1, + }, + {/* hw:x,20 */ + .name = "Listen 2 Audio Service", + .stream_name = "Listen 2 Audio Service", + .cpu_dai_name = "LSM2", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM2, + }, + {/* hw:x,21 */ + .name = "Listen 3 Audio Service", + .stream_name = "Listen 3 Audio Service", + .cpu_dai_name = "LSM3", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM3, + }, + {/* hw:x,22 */ + .name = "Listen 4 Audio Service", + .stream_name = "Listen 4 Audio Service", + .cpu_dai_name = "LSM4", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM4, + }, + {/* hw:x,23 */ + .name = "Listen 5 Audio Service", + .stream_name = "Listen 5 Audio Service", + .cpu_dai_name = "LSM5", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM5, + }, + { /* hw:x,24 */ + .name = "MSM8X16 Compress2", + .stream_name = "Compress2", + .cpu_dai_name = "MultiMedia7", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA7, + }, + { /* hw:x,25 */ + .name = "Quaternary MI2S_RX Hostless", + .stream_name = "Quaternary MI2S_RX Hostless", + .cpu_dai_name = "QUAT_MI2S_RX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,26 */ + .name = LPASS_BE_SENARY_MI2S_TX, + .stream_name = "Senary_mi2s Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.6", + .platform_name = "msm-pcm-hostless", + .codecs = dlc_vifeed, + .num_codecs = CODECS_MAX, + .id = MSM_BACKEND_DAI_SENARY_MI2S_TX, + .be_hw_params_fixup = msm_senary_tx_be_hw_params_fixup, + .ops = &msm8952_mi2s_be_ops, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .dpcm_capture = 1, + .ignore_pmdown_time = 1, + }, + {/* hw:x,27 */ + .name = "MSM8X16 MultiMedia10", + .stream_name = "MultiMedia10", + .cpu_dai_name = "MultiMedia10", + .platform_name = "msm-pcm-dsp.1", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA10, + }, + {/* hw:x,28 */ + .name = "MSM8X16 Compress4", + .stream_name = "Compress4", + .cpu_dai_name = "MultiMedia11", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA11, + }, + {/* hw:x,29 */ + .name = "MSM8X16 Compress5", + .stream_name = "Compress5", + .cpu_dai_name = "MultiMedia12", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA12, + }, + {/* hw:x,30 */ + .name = "MSM8X16 Compress6", + .stream_name = "Compress6", + .cpu_dai_name = "MultiMedia13", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA13, + }, + {/* hw:x,31 */ + .name = "MSM8X16 Compress7", + .stream_name = "Compress7", + .cpu_dai_name = "MultiMedia14", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA14, + }, + {/* hw:x,32 */ + .name = "MSM8X16 Compress8", + .stream_name = "Compress8", + .cpu_dai_name = "MultiMedia15", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA15, + }, + { /*hw:x,33 */ + .name = "MSM8X16 Compress9", + .stream_name = "Compress9", + .cpu_dai_name = "MultiMedia16", + .platform_name = "msm-pcm-dsp-noirq", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /*this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA16, + }, + {/* hw:x,34 */ + .name = "VoiceMMode1", + .stream_name = "VoiceMMode1", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOICEMMODE1, + }, + {/* hw:x,35 */ + .name = "VoiceMMode2", + .stream_name = "VoiceMMode2", + .cpu_dai_name = "VoiceMMode2", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOICEMMODE2, + }, + {/* hw:x,36 */ + .name = "MSM8916 HFP Loopback2", + .stream_name = "MultiMedia8", + .cpu_dai_name = "MultiMedia8", + .platform_name = "msm-pcm-loopback", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA8, + }, + {/* hw:x,37 */ + .name = "QCHAT", + .stream_name = "QCHAT", + .cpu_dai_name = "QCHAT", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_QCHAT, + }, + {/* hw:x,38 */ + .name = "MSM8X16 Compress10", + .stream_name = "Compress10", + .cpu_dai_name = "MultiMedia17", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA17, + }, + {/* hw:x,39 */ + .name = "MSM8X16 Compress11", + .stream_name = "Compress11", + .cpu_dai_name = "MultiMedia18", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA18, + }, + {/* hw:x,40 */ + .name = "MSM8X16 Compress12", + .stream_name = "Compress12", + .cpu_dai_name = "MultiMedia19", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA19, + }, + { + .name = LPASS_BE_SEC_MI2S_RX, + .stream_name = "Secondary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_sec_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_QUAT_MI2S_TX, + .stream_name = "Quaternary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm8952_quat_mi2s_be_ops, + .ignore_suspend = 1, + }, + /* Primary AUX PCM Backend DAI Links */ + { + .name = LPASS_BE_AUXPCM_RX, + .stream_name = "AUX PCM Playback", + .cpu_dai_name = "msm-dai-q6-auxpcm.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_AUXPCM_RX, + .be_hw_params_fixup = msm_auxpcm_be_params_fixup, + .ops = &msm_pri_auxpcm_be_ops, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AUXPCM_TX, + .stream_name = "AUX PCM Capture", + .cpu_dai_name = "msm-dai-q6-auxpcm.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_AUXPCM_TX, + .be_hw_params_fixup = msm_auxpcm_be_params_fixup, + .ops = &msm_pri_auxpcm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_BT_SCO_RX, + .stream_name = "Internal BT-SCO Playback", + .cpu_dai_name = "msm-dai-q6-dev.12288", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_INT_BT_SCO_RX, + .be_hw_params_fixup = msm_btsco_be_hw_params_fixup, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_BT_SCO_TX, + .stream_name = "Internal BT-SCO Capture", + .cpu_dai_name = "msm-dai-q6-dev.12289", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INT_BT_SCO_TX, + .be_hw_params_fixup = msm_btsco_be_hw_params_fixup, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_FM_RX, + .stream_name = "Internal FM Playback", + .cpu_dai_name = "msm-dai-q6-dev.12292", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_INT_FM_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_FM_TX, + .stream_name = "Internal FM Capture", + .cpu_dai_name = "msm-dai-q6-dev.12293", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INT_FM_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AFE_PCM_RX, + .stream_name = "AFE Playback", + .cpu_dai_name = "msm-dai-q6-dev.224", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_AFE_PCM_RX, + .be_hw_params_fixup = msm_proxy_rx_be_hw_params_fixup, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AFE_PCM_TX, + .stream_name = "AFE Capture", + .cpu_dai_name = "msm-dai-q6-dev.225", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_AFE_PCM_TX, + .be_hw_params_fixup = msm_proxy_tx_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Record Uplink BACK END DAI Link */ + { + .name = LPASS_BE_INCALL_RECORD_TX, + .stream_name = "Voice Uplink Capture", + .cpu_dai_name = "msm-dai-q6-dev.32772", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INCALL_RECORD_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Record Downlink BACK END DAI Link */ + { + .name = LPASS_BE_INCALL_RECORD_RX, + .stream_name = "Voice Downlink Capture", + .cpu_dai_name = "msm-dai-q6-dev.32771", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INCALL_RECORD_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Music BACK END DAI Link */ + { + .name = LPASS_BE_VOICE_PLAYBACK_TX, + .stream_name = "Voice Farend Playback", + .cpu_dai_name = "msm-dai-q6-dev.32773", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Music 2 BACK END DAI Link */ + { + .name = LPASS_BE_VOICE2_PLAYBACK_TX, + .stream_name = "Voice2 Farend Playback", + .cpu_dai_name = "msm-dai-q6-dev.32770", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + + { + .name = LPASS_BE_QUIN_MI2S_TX, + .stream_name = "Quinary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.4", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm8952_quin_mi2s_be_ops, + .ignore_suspend = 1, + }, + /* Proxy Tx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_TX, + .stream_name = "Proxy Capture", + .cpu_dai_name = "msm-dai-q6-dev.8195", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_PROXY_TX, + .ignore_suspend = 1, + }, + /* Proxy Rx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_RX, + .stream_name = "Proxy Playback", + .cpu_dai_name = "msm-dai-q6-dev.8194", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_PROXY_RX, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, +}; +static struct snd_soc_dai_link msm8952_hdmi_dba_dai_link[] = { + { + .name = LPASS_BE_QUIN_MI2S_RX, + .stream_name = "Quinary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.4", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "msm_hdmi_audio_codec_rx_dai", + .codec_name = "msm-ext-disp-audio-codec-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_quin_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; +static struct snd_soc_dai_link msm8952_quin_dai_link[] = { + { + .name = LPASS_BE_QUIN_MI2S_RX, + .stream_name = "Quinary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.4", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_quin_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm8952_split_a2dp_dai_link[] = { + { + .name = LPASS_BE_INT_BT_A2DP_RX, + .stream_name = "Internal BT-A2DP Playback", + .cpu_dai_name = "msm-dai-q6-dev.12290", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "msm-stub-rx", + .codec_name = "msm-stub-codec.1", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_INT_BT_A2DP_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_int_be_dai[] = { + /* Backend I2S DAI Links */ + { + .name = LPASS_BE_PRI_MI2S_RX, + .stream_name = "Primary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.0", + .platform_name = "msm-pcm-routing", + .codecs = dlc_rx1, + .num_codecs = CODECS_MAX, + .no_pcm = 1, + .dpcm_playback = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | + ASYNC_DPCM_SND_SOC_HW_PARAMS, + .id = MSM_BACKEND_DAI_PRI_MI2S_RX, + .init = &msm_audrx_init, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_TERT_MI2S_TX, + .stream_name = "Tertiary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.2", + .platform_name = "msm-pcm-routing", + .codecs = dlc_tx1, + .num_codecs = CODECS_MAX, + .no_pcm = 1, + .dpcm_capture = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | + ASYNC_DPCM_SND_SOC_HW_PARAMS, + .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + .be_hw_params_fixup = msm_tx_be_hw_params_fixup, + .ops = &msm8952_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_QUAT_MI2S_RX, + .stream_name = "Quaternary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_quat_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_int_dig_be_dai[] = { + /* DIG Codec Backend DAI Links */ + { + .name = LPASS_BE_PRI_MI2S_RX, + .stream_name = "Primary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.0", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "msm_dig_cdc_dai_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | + ASYNC_DPCM_SND_SOC_HW_PARAMS, + .id = MSM_BACKEND_DAI_PRI_MI2S_RX, + .init = &msm_dig_audrx_init, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_TERT_MI2S_TX, + .stream_name = "Tertiary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.2", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "msm_dig_cdc_dai_tx1", + .no_pcm = 1, + .dpcm_capture = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | + ASYNC_DPCM_SND_SOC_HW_PARAMS, + .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + .be_hw_params_fixup = msm_tx_be_hw_params_fixup, + .ops = &msm8952_mi2s_be_ops, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_tfa98xx_dig_be_dai_link[] = { + { + .name = LPASS_BE_QUAT_MI2S_RX, + .stream_name = "Quaternary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "tfa98xx-aif-2-34", + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS, + .dpcm_playback = 1, + .no_pcm = 1, + .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_quat_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm8952_dai_links[ +ARRAY_SIZE(msm8952_dai) + +ARRAY_SIZE(msm_int_be_dai) + +ARRAY_SIZE(msm8952_hdmi_dba_dai_link) + +ARRAY_SIZE(msm8952_split_a2dp_dai_link) + +ARRAY_SIZE(msm_tfa98xx_dig_be_dai_link)]; + +static int msm8952_wsa881x_init(struct snd_soc_component *component) +{ + return 0; +} + +static struct snd_soc_aux_dev msm8952_aux_dev[] = { + { + .name = "wsa881x.0", + .codec_name = NULL, + .init = msm8952_wsa881x_init, + }, + { + .name = "wsa881x.0", + .codec_name = NULL, + .init = msm8952_wsa881x_init, + }, +}; + +static struct snd_soc_codec_conf msm8952_codec_conf[] = { + { + .dev_name = NULL, + .name_prefix = NULL, + }, + { + .dev_name = NULL, + .name_prefix = NULL, + }, +}; +static struct snd_soc_card bear_card = { + /* snd_soc_card_msm8952 */ + .name = "msm8952-snd-card", + .dai_link = msm8952_dai, + .num_links = ARRAY_SIZE(msm8952_dai), +}; + +void msm8952_disable_mclk(struct work_struct *work) +{ + struct msm_asoc_mach_data *pdata = NULL; + struct delayed_work *dwork; + int ret = 0; + + dwork = to_delayed_work(work); + pdata = container_of(dwork, struct msm_asoc_mach_data, + disable_int_mclk0_work); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pr_debug("%s: int_mclk0_enabled %d int_mclk0_rsc_ref %d\n", __func__, + atomic_read(&pdata->int_mclk0_enabled), + atomic_read(&pdata->int_mclk0_rsc_ref)); + + if (atomic_read(&pdata->int_mclk0_enabled) == true + && atomic_read(&pdata->int_mclk0_rsc_ref) == 0) { + pr_debug("Disable the mclk\n"); + pdata->digital_cdc_core_clk.enable = 0; + pdata->digital_cdc_core_clk.clk_freq_in_hz = + DEFAULT_MCLK_RATE; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) + pr_err("%s failed to disable the CCLK\n", __func__); + atomic_set(&pdata->int_mclk0_enabled, false); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); +} + +static void msm8952_dt_parse_cap_info(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata) +{ + const char *ext1_cap = "qcom,msm-micbias1-ext-cap"; + const char *ext2_cap = "qcom,msm-micbias2-ext-cap"; + + pdata->micbias1_cap_mode = + (of_property_read_bool(pdev->dev.of_node, ext1_cap) ? + MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP); + + pdata->micbias2_cap_mode = + (of_property_read_bool(pdev->dev.of_node, ext2_cap) ? + MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP); +} + +static int msm8952_populate_dai_link_component_of_node( + struct msm_asoc_mach_data *pdata, + struct snd_soc_card *card) +{ + int i, index, ret = 0; + struct device *cdev = card->dev; + struct snd_soc_dai_link *dai_link = card->dai_link; + struct device_node *phandle; + + if (!cdev) { + pr_err("%s: Sound card device memory NULL\n", __func__); + return -ENODEV; + } + + for (i = 0; i < card->num_links; i++) { + if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node) + continue; + + /* populate platform_of_node for snd card dai links */ + if (dai_link[i].platform_name && + !dai_link[i].platform_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-platform-names", + dai_link[i].platform_name); + if (index < 0) { + pr_err("%s: No match found for platform name: %s\n", + __func__, dai_link[i].platform_name); + ret = index; + goto cpu_dai; + } + phandle = of_parse_phandle(cdev->of_node, + "asoc-platform", + index); + if (!phandle) { + pr_err("%s: retrieving phandle for platform %s, index %d failed\n", + __func__, dai_link[i].platform_name, + index); + ret = -ENODEV; + goto err; + } + dai_link[i].platform_of_node = phandle; + dai_link[i].platform_name = NULL; + } +cpu_dai: + /* populate cpu_of_node for snd card dai links */ + if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-cpu-names", + dai_link[i].cpu_dai_name); + if (index < 0) + goto codec_dai; + phandle = of_parse_phandle(cdev->of_node, "asoc-cpu", + index); + if (!phandle) { + pr_err("%s: retrieving phandle for cpu dai %s failed\n", + __func__, dai_link[i].cpu_dai_name); + ret = -ENODEV; + goto err; + } + dai_link[i].cpu_of_node = phandle; + dai_link[i].cpu_dai_name = NULL; + } +codec_dai: + /* populate codec_of_node for snd card dai links */ + if (dai_link[i].codec_name && !dai_link[i].codec_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-codec-names", + dai_link[i].codec_name); + if (index < 0) + continue; + phandle = of_parse_phandle(cdev->of_node, "asoc-codec", + index); + if (!phandle) { + pr_err("%s: retrieving phandle for codec dai %s failed\n", + __func__, dai_link[i].codec_name); + ret = -ENODEV; + goto err; + } + dai_link[i].codec_of_node = phandle; + dai_link[i].codec_name = NULL; + } + if ((dai_link[i].id == MSM_BACKEND_DAI_PRI_MI2S_RX) || + (dai_link[i].id == MSM_BACKEND_DAI_TERTIARY_MI2S_TX) || + (dai_link[i].id == MSM_BACKEND_DAI_SENARY_MI2S_TX)) { + if (pdata->snd_card_val == INT_SND_CARD) { + index = of_property_match_string( + cdev->of_node, + "asoc-codec-names", + MSM_INT_DIGITAL_CODEC); + + phandle = of_parse_phandle( + cdev->of_node, + "asoc-codec", index); + dai_link[i].codecs[DIG_CDC].of_node = phandle; + + index = of_property_match_string( + cdev->of_node, + "asoc-codec-names", + PMIC_INT_ANALOG_CODEC); + + phandle = of_parse_phandle( + cdev->of_node, + "asoc-codec", index); + dai_link[i].codecs[ANA_CDC].of_node = phandle; + } + if (pdata->snd_card_val == INT_DIG_SND_CARD) { + /* + * When only digital codec is enabled it results in + * crash due to NULL ptr exception as senary DAI has + * both analog and digital DAI info. Update + * codec_dai_name for digital codec to avoid the crash + */ + if (dai_link[i].id == + MSM_BACKEND_DAI_SENARY_MI2S_TX) { + dai_link[i].codecs = NULL; + dai_link[i].num_codecs = 1; + dai_link[i].codec_dai_name = + "msm_dig_cdc_dai_vifeed"; + } + index = of_property_match_string( + cdev->of_node, + "asoc-codec-names", + MSM_INT_DIGITAL_CODEC); + + phandle = of_parse_phandle( + cdev->of_node, + "asoc-codec", index); + dai_link[i].codec_of_node = phandle; + } + } + if ((dai_link[i].id == MSM_BACKEND_DAI_QUATERNARY_MI2S_RX) && + (of_property_read_bool( + cdev->of_node, "ext_pa_tfa98xx"))) { + index = of_property_match_string( + cdev->of_node, + "asoc-codec-names", + EXT_SMART_PA); + + phandle = of_parse_phandle( + cdev->of_node, + "asoc-codec", index); + dai_link[i].codec_of_node = phandle; + } + } +err: + return ret; +} + +int msm8952_init_wsa_switch_supply(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata) +{ + const char *switch_supply_str = "msm-vdd-wsa-switch"; + char prop_name[MSM_DT_MAX_PROP_SIZE]; + struct device_node *regnode = NULL; + struct device *dev = &pdev->dev; + u32 prop_val; + int ret = 0; + + snprintf(prop_name, MSM_DT_MAX_PROP_SIZE, "%s-supply", + switch_supply_str); + regnode = of_parse_phandle(dev->of_node, prop_name, 0); + if (!regnode) { + dev_err(dev, "Looking up %s property in node %s failed\n", + prop_name, dev->of_node->full_name); + return -ENODEV; + } + + pdata->wsa_switch_supply.supply = devm_regulator_get(dev, + switch_supply_str); + if (IS_ERR(pdata->wsa_switch_supply.supply)) { + ret = PTR_ERR(pdata->wsa_switch_supply.supply); + dev_err(dev, "Failed to get wsa switch supply: err = %d\n", + ret); + return ret; + } + + snprintf(prop_name, MSM_DT_MAX_PROP_SIZE, + "qcom,%s-voltage", switch_supply_str); + ret = of_property_read_u32(dev->of_node, prop_name, + &prop_val); + if (ret) { + dev_err(dev, "Looking up %s property in node %s failed", + prop_name, dev->of_node->full_name); + return -EFAULT; + } + ret = regulator_set_voltage(pdata->wsa_switch_supply.supply, + prop_val, prop_val); + if (ret) { + dev_err(dev, "Setting voltage failed for %s err = %d\n", + switch_supply_str, ret); + pdata->wsa_switch_supply.supply = NULL; + return ret; + } + ret = regulator_set_load(pdata->wsa_switch_supply.supply, + prop_val); + if (ret < 0) { + dev_err(dev, "Setting voltage failed for %s err = %d\n", + switch_supply_str, ret); + pdata->wsa_switch_supply.supply = NULL; + return ret; + } + + snprintf(prop_name, MSM_DT_MAX_PROP_SIZE, + "qcom,%s-current", switch_supply_str); + ret = of_property_read_u32(dev->of_node, prop_name, + &prop_val); + if (ret) { + dev_err(dev, "Looking up %s property in node %s failed", + prop_name, dev->of_node->full_name); + return -EFAULT; + } + atomic_set(&pdata->wsa_switch_supply.ref, 0); + return ret; +} + +static struct snd_soc_card *msm8952_populate_sndcard_dailinks( + struct device *dev, int snd_card_val) +{ + struct snd_soc_card *card = &bear_card; + struct snd_soc_dai_link *dailink; + int len1; + + card->name = dev_name(dev); + len1 = ARRAY_SIZE(msm8952_dai); + memcpy(msm8952_dai_links, msm8952_dai, sizeof(msm8952_dai)); + dailink = msm8952_dai_links; + + if (snd_card_val == INT_SND_CARD) { + memcpy(dailink + len1, msm_int_be_dai, sizeof(msm_int_be_dai)); + len1 += ARRAY_SIZE(msm_int_be_dai); + } else { + memcpy(dailink + len1, msm_int_dig_be_dai, + sizeof(msm_int_dig_be_dai)); + len1 += ARRAY_SIZE(msm_int_dig_be_dai); + } + + if (of_property_read_bool(dev->of_node, + "qcom,hdmi-dba-codec-rx")) { + dev_dbg(dev, "%s(): hdmi audio support present\n", + __func__); + memcpy(dailink + len1, msm8952_hdmi_dba_dai_link, + sizeof(msm8952_hdmi_dba_dai_link)); + len1 += ARRAY_SIZE(msm8952_hdmi_dba_dai_link); + } else { + dev_dbg(dev, "%s(): No hdmi dba present, add quin dai\n", + __func__); + memcpy(dailink + len1, msm8952_quin_dai_link, + sizeof(msm8952_quin_dai_link)); + len1 += ARRAY_SIZE(msm8952_quin_dai_link); + } + if (of_property_read_bool(dev->of_node, + "qcom,split-a2dp")) { + dev_dbg(dev, "%s(): split a2dp support present\n", + __func__); + memcpy(dailink + len1, msm8952_split_a2dp_dai_link, + sizeof(msm8952_split_a2dp_dai_link)); + len1 += ARRAY_SIZE(msm8952_split_a2dp_dai_link); + } + + if (of_property_read_bool(dev->of_node, + "ext_pa_tfa98xx")) { + memcpy(dailink + len1, msm_tfa98xx_dig_be_dai_link, + sizeof(msm_tfa98xx_dig_be_dai_link)); + len1 += ARRAY_SIZE(msm_tfa98xx_dig_be_dai_link); + } + + card->dai_link = dailink; + card->num_links = len1; + return card; +} + +static const struct of_device_id msm8952_asoc_machine_of_match[] = { + { .compatible = "qcom,msm8952-audio-codec", + .data = "internal_codec"}, + { .compatible = "qcom,msm8952-dig-asoc-snd", + .data = "digital_codec"}, + {}, +}; + +static int msm8952_asoc_machine_probe(struct platform_device *pdev) +{ + struct snd_soc_card *card; + struct msm_asoc_mach_data *pdata = NULL; + const char *hs_micbias_type = "qcom,msm-hs-micbias-type"; + const char *ext_pa = "qcom,msm-ext-pa"; + const char *mclk = "qcom,msm-mclk-freq"; + const char *wsa = "asoc-wsa-codec-names"; + const char *wsa_prefix = "asoc-wsa-codec-prefixes"; + const char *type = NULL; + const char *ext_pa_str = NULL; + const char *wsa_str = NULL; + const char *wsa_prefix_str = NULL; + const char *spk_ext_pa = "qcom,msm-spk-ext-pa"; + int num_strings; + int id, i, val; + int ret = 0; + struct resource *muxsel; + char *temp_str = NULL; + const struct of_device_id *match; + + pdata = devm_kzalloc(&pdev->dev, + sizeof(struct msm_asoc_mach_data), + GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + match = of_match_node(msm8952_asoc_machine_of_match, + pdev->dev.of_node); + if (!match) + goto err1; + + if (!strcmp(match->data, "internal_codec")) { + pdata->snd_card_val = INT_SND_CARD; + } else if (!strcmp(match->data, "digital_codec")) { + pdata->snd_card_val = INT_DIG_SND_CARD; + } else { + dev_err(&pdev->dev, + "%s: Not a matching DT sound node\n", __func__); + goto err1; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_mic_ctl"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for MI2S\n"); + ret = -ENODEV; + goto err1; + } + pdata->vaddr_gpio_mux_mic_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_mic_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err1; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_spkr_ctl"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for MI2S\n"); + ret = -ENODEV; + goto err; + } + pdata->vaddr_gpio_mux_spkr_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_spkr_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for MI2S\n"); + ret = -ENODEV; + goto err; + } + pdata->vaddr_gpio_mux_pcm_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_pcm_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_quin_ctl"); + if (!muxsel) { + dev_dbg(&pdev->dev, "MUX addr invalid for MI2S\n"); + goto parse_mclk_freq; + } + pdata->vaddr_gpio_mux_quin_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_quin_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } +parse_mclk_freq: + ret = of_property_read_u32(pdev->dev.of_node, mclk, &id); + if (ret) { + dev_err(&pdev->dev, + "%s: missing %s in dt node\n", __func__, mclk); + id = DEFAULT_MCLK_RATE; + } + pdata->mclk_freq = id; + + /*reading the gpio configurations from dtsi file*/ + num_strings = of_property_count_strings(pdev->dev.of_node, + wsa); + + if (num_strings > 0) { + if (wsa881x_get_probing_count() < 2) { + ret = -EPROBE_DEFER; + goto err; + } else if (wsa881x_get_presence_count() == num_strings) { + bear_card.aux_dev = msm8952_aux_dev; + bear_card.num_aux_devs = num_strings; + bear_card.codec_conf = msm8952_codec_conf; + bear_card.num_configs = num_strings; + + for (i = 0; i < num_strings; i++) { + ret = of_property_read_string_index( + pdev->dev.of_node, wsa, + i, &wsa_str); + if (ret) { + dev_err(&pdev->dev, + "%s:of read string %s i %d error %d\n", + __func__, wsa, i, ret); + goto err; + } + temp_str = kstrdup(wsa_str, GFP_KERNEL); + if (!temp_str) { + ret = -ENOMEM; + goto err; + } + msm8952_aux_dev[i].codec_name = temp_str; + temp_str = NULL; + + temp_str = kstrdup(wsa_str, GFP_KERNEL); + if (!temp_str) { + ret = -ENOMEM; + goto err; + } + msm8952_codec_conf[i].dev_name = temp_str; + temp_str = NULL; + + ret = of_property_read_string_index( + pdev->dev.of_node, wsa_prefix, + i, &wsa_prefix_str); + if (ret) { + dev_err(&pdev->dev, + "%s:of read string %s i %d error %d\n", + __func__, wsa_prefix, i, ret); + goto err; + } + temp_str = kstrdup(wsa_prefix_str, GFP_KERNEL); + if (!temp_str) { + ret = -ENOMEM; + goto err; + } + msm8952_codec_conf[i].name_prefix = temp_str; + temp_str = NULL; + } + + ret = msm8952_init_wsa_switch_supply(pdev, pdata); + if (ret < 0) { + pr_err("%s: failed to init wsa_switch vdd supply %d\n", + __func__, ret); + goto err; + } + /* update the internal speaker boost usage */ + msm_anlg_cdc_update_int_spk_boost(false); + } + } + + /* Check if voice probe done, defer otherwise */ + ret = msm_voice_get_probe_status(); + if (!ret) { + pr_debug("%s msm-pcm-voice probe status %d \n", __func__, ret); + ret = -EPROBE_DEFER; + goto err; + } + + card = msm8952_populate_sndcard_dailinks(&pdev->dev, + pdata->snd_card_val); + dev_dbg(&pdev->dev, "default codec configured\n"); + num_strings = of_property_count_strings(pdev->dev.of_node, + ext_pa); + if (num_strings < 0) { + dev_err(&pdev->dev, + "%s: missing %s in dt node or length is incorrect\n", + __func__, ext_pa); + goto err; + } + for (i = 0; i < num_strings; i++) { + ret = of_property_read_string_index(pdev->dev.of_node, + ext_pa, i, &ext_pa_str); + if (ret) { + dev_err(&pdev->dev, "%s:of read string %s i %d error %d\n", + __func__, ext_pa, i, ret); + goto err; + } + dev_err(&pdev->dev, "%s:of read string %s i %d ret %d\n", + __func__, ext_pa, i, ret); + if (!strcmp(ext_pa_str, "primary")) + pdata->ext_pa = (pdata->ext_pa | PRI_MI2S_ID); + else if (!strcmp(ext_pa_str, "secondary")) + pdata->ext_pa = (pdata->ext_pa | SEC_MI2S_ID); + else if (!strcmp(ext_pa_str, "tertiary")) + pdata->ext_pa = (pdata->ext_pa | TER_MI2S_ID); + else if (!strcmp(ext_pa_str, "quaternary")) + pdata->ext_pa = (pdata->ext_pa | QUAT_MI2S_ID); + else if (!strcmp(ext_pa_str, "quinary")) + pdata->ext_pa = (pdata->ext_pa | QUIN_MI2S_ID); + } + pr_debug("%s: ext_pa = %d\n", __func__, pdata->ext_pa); + pdata->spk_ext_pa_gpio = of_get_named_gpio(pdev->dev.of_node, + spk_ext_pa, 0); + if (pdata->spk_ext_pa_gpio < 0) { + dev_err(&pdev->dev, "%s: missing %s in dt node\n", + __func__, spk_ext_pa); + } + + pdata->spk_ext_pa_gpio_p = of_parse_phandle(pdev->dev.of_node, + spk_ext_pa, 0); + ret = is_us_eu_switch_gpio_support(pdev, pdata); + if (ret < 0) { + pr_err("%s: failed to is_us_eu_switch_gpio_support %d\n", + __func__, ret); + goto err; + } + + pdata->dmic_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,cdc-dmic-gpios", 0); + + ret = is_ext_spk_gpio_support(pdev, pdata); + if (ret < 0) + pr_err("%s: doesn't support external speaker pa\n", + __func__); + + pdata->comp_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,cdc-comp-gpios", 0); + + pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,pri-mi2s-gpios", 0); + pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,sec-mi2s-gpios", 0); + pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,tert-mi2s-gpios", 0); + pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,quat-mi2s-gpios", 0); + pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,quin-mi2s-gpios", 0); + + ret = of_property_read_string(pdev->dev.of_node, + hs_micbias_type, &type); + if (ret) { + dev_err(&pdev->dev, "%s: missing %s in dt node\n", + __func__, hs_micbias_type); + goto err; + } + if (!strcmp(type, "external")) { + dev_err(&pdev->dev, "Headset is using external micbias\n"); + mbhc_cfg.hs_ext_micbias = true; + } else { + dev_err(&pdev->dev, "Headset is using internal micbias\n"); + mbhc_cfg.hs_ext_micbias = false; + } + + ret = of_property_read_u32(pdev->dev.of_node, + "qcom,msm-afe-clk-ver", &val); + if (ret) + pdata->afe_clk_ver = AFE_CLK_VERSION_V2; + else + pdata->afe_clk_ver = val; + /* initialize the mclk */ + pdata->digital_cdc_clk.i2s_cfg_minor_version = + AFE_API_VERSION_I2S_CONFIG; + pdata->digital_cdc_clk.clk_val = pdata->mclk_freq; + pdata->digital_cdc_clk.clk_root = 5; + pdata->digital_cdc_clk.reserved = 0; + /* initialize the digital codec core clk */ + pdata->digital_cdc_core_clk.clk_set_minor_version = + AFE_API_VERSION_I2S_CONFIG; + pdata->digital_cdc_core_clk.clk_id = + Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE; + pdata->digital_cdc_core_clk.clk_freq_in_hz = + pdata->mclk_freq; + pdata->digital_cdc_core_clk.clk_attri = + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO; + pdata->digital_cdc_core_clk.clk_root = + Q6AFE_LPASS_CLK_ROOT_DEFAULT; + pdata->digital_cdc_core_clk.enable = 1; + + /* Initialize loopback mode to false */ + pdata->lb_mode = false; + msm8952_dt_parse_cap_info(pdev, pdata); + + card->dev = &pdev->dev; + platform_set_drvdata(pdev, card); + snd_soc_card_set_drvdata(card, pdata); + ret = snd_soc_of_parse_card_name(card, "qcom,model"); + if (ret) + goto err; + /* initialize timer */ + INIT_DELAYED_WORK(&pdata->disable_int_mclk0_work, msm8952_disable_mclk); + mutex_init(&pdata->cdc_int_mclk0_mutex); + atomic_set(&pdata->int_mclk0_rsc_ref, 0); + if (card->aux_dev) { + mutex_init(&pdata->wsa_mclk_mutex); + atomic_set(&pdata->wsa_int_mclk0_rsc_ref, 0); + } + atomic_set(&pdata->int_mclk0_enabled, false); + atomic_set(&quat_mi2s_clk_ref, 0); + atomic_set(&quin_mi2s_clk_ref, 0); + atomic_set(&auxpcm_mi2s_clk_ref, 0); + + ret = snd_soc_of_parse_audio_routing(card, + "qcom,audio-routing"); + if (ret) + goto err; + + ret = msm8952_populate_dai_link_component_of_node(pdata, card); + if (ret) { + ret = -EPROBE_DEFER; + goto err; + } + + ret = devm_snd_soc_register_card(&pdev->dev, card); + if (ret) { + dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", + ret); + goto err; + } + + return 0; +err: + if (pdata->vaddr_gpio_mux_spkr_ctl) + iounmap(pdata->vaddr_gpio_mux_spkr_ctl); + if (pdata->vaddr_gpio_mux_mic_ctl) + iounmap(pdata->vaddr_gpio_mux_mic_ctl); + if (pdata->vaddr_gpio_mux_pcm_ctl) + iounmap(pdata->vaddr_gpio_mux_pcm_ctl); + if (pdata->vaddr_gpio_mux_quin_ctl) + iounmap(pdata->vaddr_gpio_mux_quin_ctl); + if (bear_card.num_aux_devs > 0) { + for (i = 0; i < bear_card.num_aux_devs; i++) { + kfree(msm8952_aux_dev[i].codec_name); + kfree(msm8952_codec_conf[i].dev_name); + kfree(msm8952_codec_conf[i].name_prefix); + } + } +err1: + devm_kfree(&pdev->dev, pdata); + return ret; +} + +static int msm8952_asoc_machine_remove(struct platform_device *pdev) +{ + int i; + struct snd_soc_card *card = platform_get_drvdata(pdev); + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + if (pdata->vaddr_gpio_mux_spkr_ctl) + iounmap(pdata->vaddr_gpio_mux_spkr_ctl); + if (pdata->vaddr_gpio_mux_mic_ctl) + iounmap(pdata->vaddr_gpio_mux_mic_ctl); + if (pdata->vaddr_gpio_mux_pcm_ctl) + iounmap(pdata->vaddr_gpio_mux_pcm_ctl); + if (pdata->vaddr_gpio_mux_quin_ctl) + iounmap(pdata->vaddr_gpio_mux_quin_ctl); + if (bear_card.num_aux_devs > 0) { + for (i = 0; i < bear_card.num_aux_devs; i++) { + kfree(msm8952_aux_dev[i].codec_name); + kfree(msm8952_codec_conf[i].dev_name); + kfree(msm8952_codec_conf[i].name_prefix); + } + mutex_destroy(&pdata->wsa_mclk_mutex); + } + snd_soc_unregister_card(card); + mutex_destroy(&pdata->cdc_int_mclk0_mutex); + return 0; +} + + +static struct platform_driver msm8952_asoc_machine_driver = { + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .pm = &snd_soc_pm_ops, + .of_match_table = msm8952_asoc_machine_of_match, + }, + .probe = msm8952_asoc_machine_probe, + .remove = msm8952_asoc_machine_remove, +}; + +static int __init msm8952_machine_init(void) +{ + return platform_driver_register(&msm8952_asoc_machine_driver); +} +module_init(msm8952_machine_init); + +static void __exit msm8952_machine_exit(void) +{ + return platform_driver_unregister(&msm8952_asoc_machine_driver); +} +module_exit(msm8952_machine_exit); + +MODULE_DESCRIPTION("ALSA SoC msm"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); +MODULE_DEVICE_TABLE(of, msm8952_asoc_machine_of_match); diff --git a/techpack/audio/asoc/msm8952.h b/techpack/audio/asoc/msm8952.h new file mode 100644 index 0000000000000000000000000000000000000000..0cc692e089675273699b8352c8085856e3a87c45 --- /dev/null +++ b/techpack/audio/asoc/msm8952.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2018-2019, 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __MSM8953_H +#define __MSM8953_H + +#include +#include +#include +#include "codecs/sdm660_cdc/msm-analog-cdc.h" +#include "codecs/sdm660_cdc/msm-digital-cdc.h" +#include "codecs/wsa881x-analog.h" +#include +#include + + +#define BTSCO_RATE_8KHZ 8000 +#define BTSCO_RATE_16KHZ 16000 + +#define SAMPLING_RATE_48KHZ 48000 +#define SAMPLING_RATE_96KHZ 96000 +#define SAMPLING_RATE_192KHZ 192000 + +#define PRI_MI2S_ID (1 << 0) +#define SEC_MI2S_ID (1 << 1) +#define TER_MI2S_ID (1 << 2) +#define QUAT_MI2S_ID (1 << 3) +#define QUIN_MI2S_ID (1 << 4) + +#define DEFAULT_MCLK_RATE 9600000 + +#define WCD_MBHC_DEF_RLOADS 5 +#define MAX_WSA_CODEC_NAME_LENGTH 80 +#define MSM_DT_MAX_PROP_SIZE 80 + +enum { + DIG_CDC, + ANA_CDC, + CODECS_MAX, +}; + +enum { + PRIM_MI2S = 0, + SEC_MI2S, + TERT_MI2S, + QUAT_MI2S, + QUIN_MI2S, + MI2S_MAX, +}; + +enum { + INT_SND_CARD, + INT_DIG_SND_CARD, + INT_MAX_SND_CARD = INT_DIG_SND_CARD, + EXT_SND_CARD_TASHA, + EXT_SND_CARD_TAVIL, +}; + +struct msm_asoc_mach_data { + int codec_type; + int ext_pa; + int us_euro_gpio; + int spk_ext_pa_gpio; + int mclk_freq; + bool native_clk_set; + int lb_mode; + int afe_clk_ver; + int snd_card_val; + u8 micbias1_cap_mode; + u8 micbias2_cap_mode; + atomic_t int_mclk0_rsc_ref; + atomic_t int_mclk0_enabled; + atomic_t wsa_int_mclk0_rsc_ref; + struct mutex cdc_int_mclk0_mutex; + struct mutex wsa_mclk_mutex; + struct delayed_work disable_int_mclk0_work; + struct afe_digital_clk_cfg digital_cdc_clk; + struct afe_clk_set digital_cdc_core_clk; + void __iomem *vaddr_gpio_mux_spkr_ctl; + void __iomem *vaddr_gpio_mux_mic_ctl; + void __iomem *vaddr_gpio_mux_quin_ctl; + void __iomem *vaddr_gpio_mux_pcm_ctl; + struct on_demand_supply wsa_switch_supply; + struct device_node *spk_ext_pa_gpio_p; + struct device_node *us_euro_gpio_p; + struct device_node *comp_gpio_p; + struct device_node *mi2s_gpio_p[MI2S_MAX]; + struct device_node *dmic_gpio_p; /* used by pinctrl API */ + struct snd_soc_codec *codec; + struct snd_info_entry *codec_root; +}; + +#endif/*__MSM8953_H*/ diff --git a/techpack/audio/asoc/qcs405.c b/techpack/audio/asoc/qcs405.c index 80ac564ec3f534ed39a27df8fb4ed848fefd13ea..c83b06795a956e9a23d6e036713598ff0aafe1ce 100644 --- a/techpack/audio/asoc/qcs405.c +++ b/techpack/audio/asoc/qcs405.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include #include @@ -34,6 +34,7 @@ #include #include "codecs/bolero/bolero-cdc.h" #include "codecs/bolero/wsa-macro.h" +#include "codecs/ep92/ep92.h" #define DRV_NAME "qcs405-asoc-snd" @@ -64,7 +65,9 @@ #define WSA8810_NAME_2 "wsa881x.20170212" #define WCN_CDC_SLIM_RX_CH_MAX 2 #define WCN_CDC_SLIM_TX_CH_MAX 4 -#define TDM_CHANNEL_MAX 8 +#define TDM_CHANNEL_MAX 32 +#define TDM_SLOT_OFFSET_MAX 32 +#define TDM_MAX_CLK_FREQ 24576000 #define BT_SLIM_TX SLIM_TX_9 #define ADSP_STATE_READY_TIMEOUT_MS 3000 @@ -182,6 +185,24 @@ struct dev_config { u32 data_format; }; +struct ext_mclk_cfg { + u32 clk_freq; + u32 div2x; + u32 m; + u32 n; + u32 d; + u32 clk_root; +}; + +#define MCLK_CFG_CELLS 6 + +struct ext_mclk_cfg_info { + u32 mclk_freq; + const char *prop; + struct ext_mclk_cfg *mclk_cfg; + u32 num_mclk_cfg; +}; + struct msm_wsa881x_dev_info { struct device_node *of_node; u32 index; @@ -200,6 +221,8 @@ struct msm_asoc_mach_data { struct device_node *dmic_67_gpio_p; /* used by pinctrl API */ struct device_node *lineout_booster_gpio_p; /* used by pinctrl API */ struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */ + struct device_node *ext_mclk_gpio_p; /* used by pinctrl API */ + u32 ext_mclk_en_count; int dmic_01_gpio_cnt; int dmic_23_gpio_cnt; int dmic_45_gpio_cnt; @@ -219,6 +242,8 @@ struct msm_asoc_wcd93xx_codec { static const char *const pin_states[] = {"sleep", "i2s-active", "tdm-active"}; +const char *clk_src_name[CLK_SRC_MAX]; + enum { TDM_0 = 0, TDM_1, @@ -237,6 +262,7 @@ enum { TDM_TERT, TDM_QUAT, TDM_QUIN, + TDM_SEN, TDM_INTERFACE_MAX, }; @@ -296,6 +322,16 @@ static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = { {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */ {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */ {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */ + }, + { /* SEN TDM */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */ } }; @@ -350,8 +386,19 @@ static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = { {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */ {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */ {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */ + }, + { /* SEN TDM */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */ } }; + static struct dev_config ext_hdmi_rx_cfg[] = { [HDMI_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, }; @@ -473,6 +520,59 @@ static struct dev_config afe_lb_tx_cfg = { .channels = 2, }; +/* TDM default slot config */ +struct tdm_slot_cfg { + u32 width; + u32 num; +}; + +static struct tdm_slot_cfg tdm_slot[TDM_INTERFACE_MAX] = { + /* PRI TDM */ + {32, 8}, + /* SEC TDM */ + {32, 8}, + /* TERT TDM */ + {32, 8}, + /* QUAT TDM */ + {32, 8}, + /* QUIN TDM */ + {32, 8}, + /* SEN TDM*/ + {32, 8} +}; + +static unsigned int tdm_rx_slot_offset + [TDM_INTERFACE_MAX][TDM_SLOT_OFFSET_MAX] = { + /* PRI TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* SEC TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* TERT TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* QUAT TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* QUIN TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* SEN TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF} +}; + +static unsigned int tdm_tx_slot_offset + [TDM_INTERFACE_MAX][TDM_SLOT_OFFSET_MAX] = { + /* PRI TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* SEC TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* TERT TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* QUAT TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* QUIN TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* SEN TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF} +}; + static int msm_vi_feed_tx_ch = 2; static const char *const slim_rx_ch_text[] = {"One", "Two"}; static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four", @@ -517,12 +617,23 @@ static char const *ext_hdmi_sample_rate_text[] = {"KHZ_48", "KHZ_96", static char const *ext_hdmi_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; -static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four", - "Five", "Six", "Seven", "Eight"}; +static char const *tdm_ch_text[] = { + "One", "Two", "Three", "Four", "Five", "Six", "Seven", + "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen", + "Fourteen", "Fifteen", "Sixteen", "Seventeen", "Eighteen", + "Nineteen", "Twenty", "TwentyOne", "TwentyTwo", "TwentyThree", + "TwentyFour", "TwentyFive", "TwentySix", "TwentySeven", + "TwentyEight", "TwentyNine", "Thirty", "ThirtyOne", "ThirtyTwo" +}; static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"}; -static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32", - "KHZ_48", "KHZ_176P4", - "KHZ_352P8"}; +static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_11P025", + "KHZ_16", "KHZ_22P05", + "KHZ_32", "KHZ_44P1", "KHZ_48", + "KHZ_88P2", "KHZ_96", "KHZ_176P4", + "KHZ_192", "KHZ_352P8", "KHZ_384"}; +static const char *const tdm_slot_num_text[] = {"One", "Two", "Four", + "Eight", "Sixteen", "ThirtyTwo"}; +static const char *const tdm_slot_width_text[] = {"16", "24", "32"}; static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"}; static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16", "KHZ_22P05", "KHZ_32", "KHZ_44P1", @@ -594,6 +705,8 @@ static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_num, tdm_slot_num_text); +static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_width, tdm_slot_width_text); static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text); @@ -757,6 +870,136 @@ static struct mi2s_conf mi2s_intf_conf[MI2S_MAX]; static struct meta_mi2s_conf meta_mi2s_intf_conf[META_MI2S_MAX]; +static struct ext_mclk_cfg_info msm_ext_mclk_cfg[MCLK_FREQ_MAX] = { + [MCLK_FREQ_11P2896_MHZ] = {11289600, "ext-mclk-1-cfg-11p2896", NULL, 0}, + [MCLK_FREQ_12P288_MHZ] = {12288000, "ext-mclk-1-cfg-12p288", NULL, 0}, + [MCLK_FREQ_16P384_MHZ] = {16384000, "ext-mclk-1-cfg-16p384", NULL, 0}, + [MCLK_FREQ_22P5792_MHZ] = {22579200, "ext-mclk-1-cfg-22p5792", NULL, 0}, + [MCLK_FREQ_24P576_MHZ] = {24576000, "ext-mclk-1-cfg-24p576", NULL, 0}, +}; + +static int qcs405_start_stop_mclk(void *private_data, uint32_t start, + uint32_t mclk_freq) +{ + int ret = 0; + struct snd_soc_card *card = (struct snd_soc_card *)private_data; + struct msm_asoc_mach_data *data = NULL; + struct snd_soc_component *component = NULL; + struct device_node *np = NULL; + + if (!card) + return -EINVAL; + + data = snd_soc_card_get_drvdata(card); + if (!data || !data->ext_mclk_gpio_p) + return -EINVAL; + + pr_debug("%s: ep92 clock: %d\n", __func__, start); + if (start) { + if (data->ext_mclk_en_count == 0) { + np = of_parse_phandle(card->dev->of_node, + "qcom,ext-mclk-src", 0); + if (!np) { + pr_err("%s: no external mclk source found\n", + __func__); + return -EINVAL; + } + + component = soc_find_component(np, NULL); + if (!component) { + pr_err("%s: inalid external mclk source\n", + __func__); + return -EINVAL; + } + + ret = ep92_set_ext_mclk(component->codec, mclk_freq); + if (ret) + return ret; + + np = data->ext_mclk_gpio_p; + ret = msm_cdc_pinctrl_select_active_state(np); + if (ret) { + pr_err("%s: coundn't set active mclk pinctrl\n", + __func__); + return ret; + } + } + data->ext_mclk_en_count++; + } else { + if (data->ext_mclk_en_count == 1) { + np = data->ext_mclk_gpio_p; + msm_cdc_pinctrl_select_sleep_state(np); + data->ext_mclk_en_count = 0; + } else if (data->ext_mclk_en_count > 1) { + data->ext_mclk_en_count--; + } + } + + return ret; +} + +static int qcs405_enable_and_get_mclk_cfg(void *private_data, uint32_t enable, + uint32_t mclk_freq, + struct afe_param_id_clock_set_v2_t *dyn_mclk_cfg) +{ + struct ext_mclk_cfg *mclk_cfg = NULL; + uint32_t mclk_cfg_entries = 0; + enum afe_mclk_freq freq = MCLK_FREQ_MIN; + int i = 0; + int ret = 0; + + if (!dyn_mclk_cfg) + return -EINVAL; + + for (freq = MCLK_FREQ_MIN; freq < MCLK_FREQ_MAX; freq++) { + if (msm_ext_mclk_cfg[freq].mclk_freq == mclk_freq) + break; + } + + if (freq == MCLK_FREQ_MAX) { + pr_err("%s: Unsupported mclk freq: %u\n", __func__, mclk_freq); + return -EINVAL; + } + + if (!msm_ext_mclk_cfg[freq].mclk_cfg || + !msm_ext_mclk_cfg[freq].num_mclk_cfg) { + pr_err("%s: Freq table unavailable for mclk: %u\n", + __func__, mclk_freq); + return -EINVAL; + } + + mclk_cfg = msm_ext_mclk_cfg[freq].mclk_cfg; + mclk_cfg_entries = msm_ext_mclk_cfg[freq].num_mclk_cfg; + + for (i = 0; i < mclk_cfg_entries; i++) { + if (mclk_cfg[i].clk_freq == dyn_mclk_cfg->clk_freq_in_hz) { + dyn_mclk_cfg->divider_2x = mclk_cfg[i].div2x; + dyn_mclk_cfg->m = mclk_cfg[i].m; + dyn_mclk_cfg->n = mclk_cfg[i].n; + dyn_mclk_cfg->d = mclk_cfg[i].d; + dyn_mclk_cfg->clk_root = + (uint16_t) (mclk_cfg[i].clk_root); + break; + } + } + + if (i == mclk_cfg_entries) { + pr_err("%s: Requested BCLK freq is not supported\n", __func__); + return -EINVAL; + } + + ret = qcs405_start_stop_mclk(private_data, enable, mclk_freq); + if (ret) { + dyn_mclk_cfg->divider_2x = 0; + dyn_mclk_cfg->m = 0; + dyn_mclk_cfg->n = 0; + dyn_mclk_cfg->d = 0; + dyn_mclk_cfg->clk_root = 0; + } + + return ret; +} + static int msm_island_vad_get_portid_from_beid(int32_t be_id, int *port_id) { *port_id = 0xFFFF; @@ -2359,20 +2602,41 @@ static int tdm_get_sample_rate(int value) sample_rate = SAMPLING_RATE_8KHZ; break; case 1: - sample_rate = SAMPLING_RATE_16KHZ; + sample_rate = SAMPLING_RATE_11P025KHZ; break; case 2: - sample_rate = SAMPLING_RATE_32KHZ; + sample_rate = SAMPLING_RATE_16KHZ; break; case 3: - sample_rate = SAMPLING_RATE_48KHZ; + sample_rate = SAMPLING_RATE_22P05KHZ; break; case 4: - sample_rate = SAMPLING_RATE_176P4KHZ; + sample_rate = SAMPLING_RATE_32KHZ; break; case 5: + sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 6: + sample_rate = SAMPLING_RATE_48KHZ; + break; + case 7: + sample_rate = SAMPLING_RATE_88P2KHZ; + break; + case 8: + sample_rate = SAMPLING_RATE_96KHZ; + break; + case 9: + sample_rate = SAMPLING_RATE_176P4KHZ; + break; + case 10: + sample_rate = SAMPLING_RATE_192KHZ; + break; + case 11: sample_rate = SAMPLING_RATE_352P8KHZ; break; + case 12: + sample_rate = SAMPLING_RATE_384KHZ; + break; default: sample_rate = SAMPLING_RATE_48KHZ; break; @@ -2404,23 +2668,44 @@ static int tdm_get_sample_rate_val(int sample_rate) case SAMPLING_RATE_8KHZ: sample_rate_val = 0; break; - case SAMPLING_RATE_16KHZ: + case SAMPLING_RATE_11P025KHZ: sample_rate_val = 1; break; - case SAMPLING_RATE_32KHZ: + case SAMPLING_RATE_16KHZ: sample_rate_val = 2; break; - case SAMPLING_RATE_48KHZ: + case SAMPLING_RATE_22P05KHZ: sample_rate_val = 3; break; - case SAMPLING_RATE_176P4KHZ: + case SAMPLING_RATE_32KHZ: sample_rate_val = 4; break; - case SAMPLING_RATE_352P8KHZ: + case SAMPLING_RATE_44P1KHZ: sample_rate_val = 5; break; + case SAMPLING_RATE_48KHZ: + sample_rate_val = 6; + break; + case SAMPLING_RATE_88P2KHZ: + sample_rate_val = 7; + break; + case SAMPLING_RATE_96KHZ: + sample_rate_val = 8; + break; + case SAMPLING_RATE_176P4KHZ: + sample_rate_val = 9; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 10; + break; + case SAMPLING_RATE_352P8KHZ: + sample_rate_val = 11; + break; + case SAMPLING_RATE_384KHZ: + sample_rate_val = 12; + break; default: - sample_rate_val = 3; + sample_rate_val = 6; break; } return sample_rate_val; @@ -2442,31 +2727,43 @@ static int aux_pcm_get_sample_rate_val(int sample_rate) return sample_rate_val; } +static int tdm_get_mode(struct snd_kcontrol *kcontrol) +{ + int mode; + + if (strnstr(kcontrol->id.name, "PRI", + sizeof(kcontrol->id.name))) { + mode = TDM_PRI; + } else if (strnstr(kcontrol->id.name, "SEC", + sizeof(kcontrol->id.name))) { + mode = TDM_SEC; + } else if (strnstr(kcontrol->id.name, "TERT", + sizeof(kcontrol->id.name))) { + mode = TDM_TERT; + } else if (strnstr(kcontrol->id.name, "QUAT", + sizeof(kcontrol->id.name))) { + mode = TDM_QUAT; + } else if (strnstr(kcontrol->id.name, "QUIN", + sizeof(kcontrol->id.name))) { + mode = TDM_QUIN; + } else if (strnstr(kcontrol->id.name, "SEN", + sizeof(kcontrol->id.name))) { + mode = TDM_SEN; + } else { + pr_err("%s: unsupported mode in: %s\n", + __func__, kcontrol->id.name); + return -EINVAL; + } + return mode; +} + static int tdm_get_port_idx(struct snd_kcontrol *kcontrol, struct tdm_port *port) { if (port) { - if (strnstr(kcontrol->id.name, "PRI", - sizeof(kcontrol->id.name))) { - port->mode = TDM_PRI; - } else if (strnstr(kcontrol->id.name, "SEC", - sizeof(kcontrol->id.name))) { - port->mode = TDM_SEC; - } else if (strnstr(kcontrol->id.name, "TERT", - sizeof(kcontrol->id.name))) { - port->mode = TDM_TERT; - } else if (strnstr(kcontrol->id.name, "QUAT", - sizeof(kcontrol->id.name))) { - port->mode = TDM_QUAT; - } else if (strnstr(kcontrol->id.name, "QUIN", - sizeof(kcontrol->id.name))) { - port->mode = TDM_QUIN; - } else { - pr_err("%s: unsupported mode in: %s", - __func__, kcontrol->id.name); - return -EINVAL; - } - + port->mode = tdm_get_mode(kcontrol); + if (port->mode < 0) + return port->mode; if (strnstr(kcontrol->id.name, "RX_0", sizeof(kcontrol->id.name)) || strnstr(kcontrol->id.name, "TX_0", @@ -2508,7 +2805,7 @@ static int tdm_get_port_idx(struct snd_kcontrol *kcontrol, sizeof(kcontrol->id.name))) { port->channel = TDM_7; } else { - pr_err("%s: unsupported channel in: %s", + pr_err("%s: unsupported channel in: %s\n", __func__, kcontrol->id.name); return -EINVAL; } @@ -2800,6 +3097,264 @@ static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol, return ret; } +static int tdm_get_slot_num_val(int slot_num) +{ + int slot_num_val; + + switch (slot_num) { + case 1: + slot_num_val = 0; + break; + case 2: + slot_num_val = 1; + break; + case 4: + slot_num_val = 2; + break; + case 8: + slot_num_val = 3; + break; + case 16: + slot_num_val = 4; + break; + case 32: + slot_num_val = 5; + break; + default: + slot_num_val = 5; + break; + } + return slot_num_val; +} + +static int tdm_get_slot_num(int value) +{ + int slot_num; + + switch (value) { + case 0: + slot_num = 1; + break; + case 1: + slot_num = 2; + break; + case 2: + slot_num = 4; + break; + case 3: + slot_num = 8; + break; + case 4: + slot_num = 16; + break; + case 5: + slot_num = 32; + break; + default: + slot_num = 8; + break; + } + return slot_num; +} + +static int tdm_slot_num_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + ucontrol->value.enumerated.item[0] = + tdm_get_slot_num_val(tdm_slot[mode].num); + pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__, + mode, tdm_slot[mode].num, + ucontrol->value.enumerated.item[0]); + return 0; +} + +static int tdm_slot_num_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + tdm_slot[mode].num = + tdm_get_slot_num(ucontrol->value.enumerated.item[0]); + pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__, + mode, tdm_slot[mode].num, + ucontrol->value.enumerated.item[0]); + return 0; +} + +static int tdm_get_slot_width_val(int slot_width) +{ + int slot_width_val; + + switch (slot_width) { + case 16: + slot_width_val = 0; + break; + case 24: + slot_width_val = 1; + break; + case 32: + slot_width_val = 2; + break; + default: + slot_width_val = 2; + break; + } + return slot_width_val; +} + +static int tdm_slot_width_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + ucontrol->value.enumerated.item[0] = + tdm_get_slot_width_val(tdm_slot[mode].width); + pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__, + mode, tdm_slot[mode].width, + ucontrol->value.enumerated.item[0]); + return 0; +} + +static int tdm_get_slot_width(int value) +{ + int slot_width; + + switch (value) { + case 0: + slot_width = 16; + break; + case 1: + slot_width = 24; + break; + case 2: + slot_width = 32; + break; + default: + slot_width = 32; + break; + } + return slot_width; +} + +static int tdm_slot_width_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + tdm_slot[mode].width = + tdm_get_slot_width(ucontrol->value.enumerated.item[0]); + pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__, + mode, tdm_slot[mode].width, + ucontrol->value.enumerated.item[0]); + return 0; +} + +static int tdm_rx_slot_mapping_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int *slot_offset; + int i; + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + slot_offset = tdm_rx_slot_offset[mode]; + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + ucontrol->value.integer.value[i] = slot_offset[i]; + pr_debug("%s: offset %d, value %d\n", + __func__, i, slot_offset[i]); + } + return 0; +} + +static int tdm_rx_slot_mapping_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int *slot_offset; + int i; + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + slot_offset = tdm_rx_slot_offset[mode]; + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + slot_offset[i] = ucontrol->value.integer.value[i]; + pr_debug("%s: offset %d, value %d\n", + __func__, i, slot_offset[i]); + } + return 0; +} + +static int tdm_tx_slot_mapping_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int *slot_offset; + int i; + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + slot_offset = tdm_tx_slot_offset[mode]; + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + ucontrol->value.integer.value[i] = slot_offset[i]; + pr_debug("%s: offset %d, value %d\n", + __func__, i, slot_offset[i]); + } + return 0; +} + +static int tdm_tx_slot_mapping_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int *slot_offset; + int i; + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + slot_offset = tdm_tx_slot_offset[mode]; + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + slot_offset[i] = ucontrol->value.integer.value[i]; + pr_debug("%s: offset %d, value %d\n", + __func__, i, slot_offset[i]); + } + return 0; +} + static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol) { int idx; @@ -4329,6 +4884,85 @@ static const struct snd_kcontrol_new msm_snd_controls[] = { SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs, tdm_tx_ch_get, tdm_tx_ch_put), + SOC_ENUM_EXT("SEN_TDM_RX_0 SampleRate", tdm_rx_sample_rate, + tdm_rx_sample_rate_get, + tdm_rx_sample_rate_put), + SOC_ENUM_EXT("SEN_TDM_TX_0 SampleRate", tdm_tx_sample_rate, + tdm_tx_sample_rate_get, + tdm_tx_sample_rate_put), + SOC_ENUM_EXT("SEN_TDM_RX_0 Format", tdm_rx_format, + tdm_rx_format_get, + tdm_rx_format_put), + SOC_ENUM_EXT("SEN_TDM_TX_0 Format", tdm_tx_format, + tdm_tx_format_get, + tdm_tx_format_put), + SOC_ENUM_EXT("SEN_TDM_RX_0 Channels", tdm_rx_chs, + tdm_rx_ch_get, + tdm_rx_ch_put), + SOC_ENUM_EXT("SEN_TDM_TX_0 Channels", tdm_tx_chs, + tdm_tx_ch_get, + tdm_tx_ch_put), + SOC_ENUM_EXT("PRI_TDM SlotNumber", tdm_slot_num, + tdm_slot_num_get, tdm_slot_num_put), + SOC_ENUM_EXT("PRI_TDM SlotWidth", tdm_slot_width, + tdm_slot_width_get, tdm_slot_width_put), + SOC_ENUM_EXT("SEC_TDM SlotNumber", tdm_slot_num, + tdm_slot_num_get, tdm_slot_num_put), + SOC_ENUM_EXT("SEC_TDM SlotWidth", tdm_slot_width, + tdm_slot_width_get, tdm_slot_width_put), + SOC_ENUM_EXT("TERT_TDM SlotNumber", tdm_slot_num, + tdm_slot_num_get, tdm_slot_num_put), + SOC_ENUM_EXT("TERT_TDM SlotWidth", tdm_slot_width, + tdm_slot_width_get, tdm_slot_width_put), + SOC_ENUM_EXT("QUAT_TDM SlotNumber", tdm_slot_num, + tdm_slot_num_get, tdm_slot_num_put), + SOC_ENUM_EXT("QUAT_TDM SlotWidth", tdm_slot_width, + tdm_slot_width_get, tdm_slot_width_put), + SOC_ENUM_EXT("QUIN_TDM SlotNumber", tdm_slot_num, + tdm_slot_num_get, tdm_slot_num_put), + SOC_ENUM_EXT("QUIN_TDM SlotWidth", tdm_slot_width, + tdm_slot_width_get, tdm_slot_width_put), + SOC_ENUM_EXT("SEN_TDM SlotNumber", tdm_slot_num, + tdm_slot_num_get, tdm_slot_num_put), + SOC_ENUM_EXT("SEN_TDM SlotWidth", tdm_slot_width, + tdm_slot_width_get, tdm_slot_width_put), + SOC_SINGLE_MULTI_EXT("PRI_TDM_RX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("SEC_TDM_RX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("TERT_TDM_RX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("SEN_TDM_RX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("PRI_TDM_TX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("SEC_TDM_TX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("TERT_TDM_TX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("SEN_TDM_TX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put), + SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate, aux_pcm_rx_sample_rate_get, aux_pcm_rx_sample_rate_put), @@ -5074,6 +5708,22 @@ static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate; break; + case MSM_BACKEND_DAI_SEN_TDM_RX_0: + channels->min = channels->max = + tdm_rx_cfg[TDM_SEN][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_rx_cfg[TDM_SEN][TDM_0].bit_format); + rate->min = rate->max = tdm_rx_cfg[TDM_SEN][TDM_0].sample_rate; + break; + + case MSM_BACKEND_DAI_SEN_TDM_TX_0: + channels->min = channels->max = + tdm_tx_cfg[TDM_SEN][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_tx_cfg[TDM_SEN][TDM_0].bit_format); + rate->min = rate->max = tdm_tx_cfg[TDM_SEN][TDM_0].sample_rate; + break; + case MSM_BACKEND_DAI_AUXPCM_RX: param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format); @@ -6166,6 +6816,13 @@ static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format); rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate; + } else if (cpu_dai->id == AFE_PORT_ID_SENARY_TDM_RX) { + channels->min = channels->max = + tdm_rx_cfg[TDM_SEN][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_rx_cfg[TDM_SEN][TDM_0].bit_format); + rate->min = rate->max = + tdm_rx_cfg[TDM_SEN][TDM_0].sample_rate; } else { pr_err("%s: dai id 0x%x not supported\n", __func__, cpu_dai->id); @@ -6188,7 +6845,9 @@ static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream, int slot_width = 32; int channels, slots = 8; unsigned int slot_mask, rate, clk_freq; - unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28}; + unsigned int *slot_offset; + int offset_channels = 0; + int i; pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id); @@ -6196,33 +6855,75 @@ static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream, switch (cpu_dai->id) { case AFE_PORT_ID_PRIMARY_TDM_RX: channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels; + slots = tdm_slot[TDM_PRI].num; + slot_width = tdm_slot[TDM_PRI].width; + slot_offset = tdm_rx_slot_offset[TDM_PRI]; break; case AFE_PORT_ID_SECONDARY_TDM_RX: channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels; + slots = tdm_slot[TDM_SEC].num; + slot_width = tdm_slot[TDM_SEC].width; + slot_offset = tdm_rx_slot_offset[TDM_SEC]; break; case AFE_PORT_ID_TERTIARY_TDM_RX: channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels; + slots = tdm_slot[TDM_TERT].num; + slot_width = tdm_slot[TDM_TERT].width; + slot_offset = tdm_rx_slot_offset[TDM_TERT]; break; case AFE_PORT_ID_QUATERNARY_TDM_RX: channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels; + slots = tdm_slot[TDM_QUAT].num; + slot_width = tdm_slot[TDM_QUAT].width; + slot_offset = tdm_rx_slot_offset[TDM_QUAT]; break; case AFE_PORT_ID_QUINARY_TDM_RX: channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels; + slots = tdm_slot[TDM_QUIN].num; + slot_width = tdm_slot[TDM_QUIN].width; + slot_offset = tdm_rx_slot_offset[TDM_QUIN]; + break; + case AFE_PORT_ID_SENARY_TDM_RX: + channels = tdm_rx_cfg[TDM_SEN][TDM_0].channels; + slots = tdm_slot[TDM_SEN].num; + slot_width = tdm_slot[TDM_SEN].width; + slot_offset = tdm_rx_slot_offset[TDM_SEN]; break; case AFE_PORT_ID_PRIMARY_TDM_TX: channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels; + slots = tdm_slot[TDM_PRI].num; + slot_width = tdm_slot[TDM_PRI].width; + slot_offset = tdm_tx_slot_offset[TDM_PRI]; break; case AFE_PORT_ID_SECONDARY_TDM_TX: channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels; + slots = tdm_slot[TDM_SEC].num; + slot_width = tdm_slot[TDM_SEC].width; + slot_offset = tdm_tx_slot_offset[TDM_SEC]; break; case AFE_PORT_ID_TERTIARY_TDM_TX: channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels; + slots = tdm_slot[TDM_TERT].num; + slot_width = tdm_slot[TDM_TERT].width; + slot_offset = tdm_tx_slot_offset[TDM_TERT]; break; case AFE_PORT_ID_QUATERNARY_TDM_TX: channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels; + slots = tdm_slot[TDM_QUAT].num; + slot_width = tdm_slot[TDM_QUAT].width; + slot_offset = tdm_tx_slot_offset[TDM_QUAT]; break; case AFE_PORT_ID_QUINARY_TDM_TX: channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels; + slots = tdm_slot[TDM_QUIN].num; + slot_width = tdm_slot[TDM_QUIN].width; + slot_offset = tdm_tx_slot_offset[TDM_QUIN]; + break; + case AFE_PORT_ID_SENARY_TDM_TX: + channels = tdm_tx_cfg[TDM_SEN][TDM_0].channels; + slots = tdm_slot[TDM_SEN].num; + slot_width = tdm_slot[TDM_SEN].width; + slot_offset = tdm_tx_slot_offset[TDM_SEN]; break; default: pr_err("%s: dai id 0x%x not supported\n", @@ -6230,9 +6931,28 @@ static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID) + offset_channels++; + else + break; + } + + if (offset_channels == 0) { + pr_err("%s: invalid offset_channels %d\n", + __func__, offset_channels); + return -EINVAL; + } + + if (channels > offset_channels) { + pr_err("%s: channels %d exceed offset_channels %d\n", + __func__, channels, offset_channels); + return -EINVAL; + } + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { /*2 slot config - bits 0 and 1 set for the first two slots */ - slot_mask = 0x0000FFFF >> (16-channels); + slot_mask = 0xFFFFFFFF >> (32 - channels); pr_debug("%s: tdm rx slot_width %d slots %d\n", __func__, slot_width, slots); @@ -6254,7 +6974,7 @@ static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream, } } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { /*2 slot config - bits 0 and 1 set for the first two slots */ - slot_mask = 0x0000FFFF >> (16-channels); + slot_mask = 0xFFFFFFFF >> (32 - channels); pr_debug("%s: tdm tx slot_width %d slots %d\n", __func__, slot_width, slots); @@ -6283,6 +7003,12 @@ static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream, rate = params_rate(params); clk_freq = rate * slot_width * slots; + if (clk_freq > TDM_MAX_CLK_FREQ) { + ret = -EINVAL; + pr_err("%s: clk frequency > 24.576MHz %d\n", + __func__, clk_freq); + goto end; + } ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT); if (ret < 0) pr_err("%s: failed to set tdm clk, err:%d\n", @@ -6317,6 +7043,10 @@ static int msm_get_tdm_mode(u32 port_id) case AFE_PORT_ID_QUINARY_TDM_TX: tdm_mode = TDM_QUIN; break; + case AFE_PORT_ID_SENARY_TDM_RX: + case AFE_PORT_ID_SENARY_TDM_TX: + tdm_mode = TDM_SEN; + break; default: pr_err("%s: Invalid port id: %d\n", __func__, port_id); tdm_mode = -EINVAL; @@ -6742,10 +7472,17 @@ static int msm_meta_mi2s_snd_startup(struct snd_pcm_substream *substream) if (i == 0) { port_id = msm_get_port_id(rtd->dai_link->id); - ret = afe_set_clk_id(port_id, - mi2s_clk[member_port].clk_id); + if (meta_mi2s_rx_cfg[index].sample_rate + % SAMPLING_RATE_8KHZ) { + if (clk_src_name[CLK_SRC_FRACT] != NULL) + ret = afe_set_source_clk(port_id, + clk_src_name[CLK_SRC_FRACT]); + } else if (clk_src_name[CLK_SRC_INTEGRAL] != NULL) { + ret = afe_set_source_clk(port_id, + clk_src_name[CLK_SRC_INTEGRAL]); + } if (ret < 0) - pr_err("%s: afe_set_clk_id fail %d\n", + pr_err("%s: afe_set_source_name fail %d\n", __func__, ret); ret = snd_soc_dai_set_fmt(cpu_dai, fmt); @@ -8013,6 +8750,35 @@ static struct snd_soc_dai_link msm_common_be_dai_links[] = { .ops = &qcs405_tdm_be_ops, .ignore_suspend = 1, }, + { + .name = LPASS_BE_SEN_TDM_RX_0, + .stream_name = "Senary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36944", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SEN_TDM_RX_0, + .be_hw_params_fixup = msm_tdm_be_hw_params_fixup, + .ops = &qcs405_tdm_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, + { + .name = LPASS_BE_SEN_TDM_TX_0, + .stream_name = "Senary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36945", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_SEN_TDM_TX_0, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &qcs405_tdm_be_ops, + .ignore_suspend = 1, + }, }; static struct snd_soc_dai_link msm_tasha_be_dai_links[] = { @@ -9896,6 +10662,132 @@ static int msm_detect_ep92_dev(struct platform_device *pdev, return 0; } +static int msm_parse_ext_mclk_cfg_one(struct snd_soc_card *card, + enum afe_mclk_freq freq) +{ + int ret = 0; + struct ext_mclk_cfg *mclk_cfg = NULL; + uint32_t len = 0; + uint32_t num_cfg = 0; + uint32_t cells = 0; + int i = 0; + struct device_node *np = NULL; + uint32_t *array = NULL; + + if (!card || !card->dev || !card->dev->of_node) + return -EINVAL; + + np = card->dev->of_node; + + if (!of_get_property(np, msm_ext_mclk_cfg[freq].prop, &len)) { + pr_debug("External MCLK cfg not found in DT\n"); + return 0; + } + + ret = of_property_read_u32(np, "#ext-mclk-1-cfg-cells", &cells); + if (ret) { + pr_err("%s: External MCLK cfg cells not found in DT\n", + __func__); + return ret; + } + + if (!len || (len % (cells * sizeof(uint32_t))) || + (cells != MCLK_CFG_CELLS)) { + pr_err("%s: invalid mclk configuration in DT\n", + __func__); + return -EINVAL; + }; + + num_cfg = len / (cells * sizeof(uint32_t)); + mclk_cfg = devm_kzalloc(card->dev, + num_cfg * sizeof(struct ext_mclk_cfg), GFP_KERNEL); + if (!mclk_cfg) + return -ENOMEM; + + array = devm_kzalloc(card->dev, + cells * num_cfg * sizeof(uint32_t), GFP_KERNEL); + if (!array) { + ret = -ENOMEM; + goto free_mclk_cfg; + } + + ret = of_property_read_u32_array(np, msm_ext_mclk_cfg[freq].prop, + array, cells * num_cfg); + if (ret) + goto free_array; + + dev_dbg(card->dev, "table for %u freq\n", + msm_ext_mclk_cfg[freq].mclk_freq); + for (i = 0; i < num_cfg; i++) { + memcpy(&mclk_cfg[i], &array[i * cells], + sizeof(uint32_t) * cells); + dev_dbg(card->dev, + "clk:%u, div2x:%u, m:%u, n:%u, d:%u, clk_root:%u\n", + mclk_cfg[i].clk_freq, mclk_cfg[i].div2x, mclk_cfg[i].m, + mclk_cfg[i].n, mclk_cfg[i].d, mclk_cfg[i].clk_root); + } + + msm_ext_mclk_cfg[freq].mclk_cfg = mclk_cfg; + msm_ext_mclk_cfg[freq].num_mclk_cfg = num_cfg; + + devm_kfree(card->dev, array); + array = NULL; + + return 0; +free_array: + devm_kfree(card->dev, array); + array = NULL; +free_mclk_cfg: + devm_kfree(card->dev, mclk_cfg); + mclk_cfg = NULL; + + return ret; +} + +static void qcs405_ext_mclk_cfg_deinit(struct snd_soc_card *card) +{ + enum afe_mclk_freq i = MCLK_FREQ_MIN; + + if (!card || !card->dev) + return; + + for (i = MCLK_FREQ_MIN; i < MCLK_FREQ_MAX; i++) { + if (msm_ext_mclk_cfg[i].mclk_cfg) { + devm_kfree(card->dev, + msm_ext_mclk_cfg[i].mclk_cfg); + msm_ext_mclk_cfg[i].mclk_cfg = NULL; + msm_ext_mclk_cfg[i].num_mclk_cfg = 0; + } + } + + afe_unregister_ext_mclk_cb(); +} + +static int qcs405_ext_mclk_cfg_init(struct snd_soc_card *card) +{ + int ret = 0; + enum afe_mclk_freq i = MCLK_FREQ_MIN; + + ret = afe_register_ext_mclk_cb(qcs405_enable_and_get_mclk_cfg, + (void *)card); + if (ret) { + pr_err("%s: Could not register afe ext mclk cb ret: %d\n", + __func__, ret); + return ret; + } + + for (i = MCLK_FREQ_MIN; i < MCLK_FREQ_MAX; i++) { + ret = msm_parse_ext_mclk_cfg_one(card, i); + if (ret < 0) + goto err; + } + + return 0; +err: + qcs405_ext_mclk_cfg_deinit(card); + return ret; +} + static int msm_asoc_machine_probe(struct platform_device *pdev) { struct snd_soc_card *card; @@ -9906,6 +10798,8 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) const char *micb_supply_str1 = "tdm-vdd-micb"; const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage"; const char *micb_current_str = "qcom,tdm-vdd-micb-current"; + const char *clk_src_name_str_integ = "qcom,clk-src-name-integ"; + const char *clk_src_name_str_fract = "qcom,clk-src-name-fract"; u32 v_base_addr; if (!pdev->dev.of_node) { @@ -9918,6 +10812,23 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) if (!pdata) return -ENOMEM; + ret = of_property_read_string_index(pdev->dev.of_node, + clk_src_name_str_integ, 0, + &clk_src_name[CLK_SRC_INTEGRAL]); + if (ret) + dev_err(&pdev->dev, + "No clk src name[%d] from device tree\n", + CLK_SRC_INTEGRAL); + ret = of_property_read_string_index(pdev->dev.of_node, + clk_src_name_str_fract, 0, + &clk_src_name[CLK_SRC_FRACT]); + if (ret) + dev_err(&pdev->dev, + "No clk src name[%d] from device tree\n", + CLK_SRC_FRACT); + if (clk_src_name[CLK_SRC_INTEGRAL] != NULL && + clk_src_name[CLK_SRC_FRACT] != NULL) + afe_set_clk_src_array(clk_src_name); ret = of_property_read_u32( pdev->dev.of_node, "tcsr_i2s_dsd_prim", &v_base_addr); if (ret) { @@ -10019,6 +10930,8 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) "qcom,quat-mi2s-gpios", 0); pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node, "qcom,quin-mi2s-gpios", 0); + pdata->mi2s_gpio_p[SEN_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,sen-mi2s-gpios", 0); if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) { pdata->tdm_micb_supply = devm_regulator_get(&pdev->dev, @@ -10049,6 +10962,15 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) } } + ret = qcs405_ext_mclk_cfg_init(card); + if (ret) { + dev_err(&pdev->dev, "mclk cfg from DT failed: %d\n", ret); + qcs405_ext_mclk_cfg_deinit(card); + } + + pdata->ext_mclk_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,ext-mclk-gpio", 0); + ret = devm_snd_soc_register_card(&pdev->dev, card); if (ret == -EPROBE_DEFER) { if (codec_reg_done) @@ -10079,6 +11001,11 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) static int msm_asoc_machine_remove(struct platform_device *pdev) { + struct snd_soc_card *card = NULL; + + card = (struct snd_soc_card *)platform_get_drvdata(pdev); + qcs405_ext_mclk_cfg_deinit(card); + audio_notifier_deregister("qcs405"); msm_i2s_auxpcm_deinit(); msm_mdf_mem_deinit(); diff --git a/techpack/audio/asoc/sdm660-ext-dai-links.c b/techpack/audio/asoc/sdm660-ext-dai-links.c index 534585fca485b0cc23e7013323b46748877474cf..521162e5473f1a9576c2c0c994f4052bfec6136e 100644 --- a/techpack/audio/asoc/sdm660-ext-dai-links.c +++ b/techpack/audio/asoc/sdm660-ext-dai-links.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2019, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, 2021, The Linux Foundation. All rights reserved. */ #include @@ -275,6 +275,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_0_RX, @@ -292,6 +293,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_tx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_0_TX, @@ -306,6 +308,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_1_RX, @@ -322,6 +325,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_tx3", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_1_TX, @@ -336,6 +340,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_3_RX, @@ -352,6 +357,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_tx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .dpcm_playback = 1, @@ -367,6 +373,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_4_RX, @@ -383,6 +390,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_rx3", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_5_RX, @@ -400,6 +408,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mad1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_5_TX, @@ -414,6 +423,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_rx4", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_6_RX, @@ -433,6 +443,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_0_RX, @@ -450,6 +461,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_tx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_0_TX, @@ -464,6 +476,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_1_RX, @@ -480,6 +493,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_tx3", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_1_TX, @@ -494,6 +508,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx2", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_2_RX, @@ -509,6 +524,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_3_RX, @@ -525,6 +541,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_tx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_3_TX, @@ -539,6 +556,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_4_RX, @@ -555,6 +573,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx3", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_5_RX, @@ -572,6 +591,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_mad1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_5_TX, @@ -586,6 +606,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx4", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_6_RX, @@ -1282,6 +1303,33 @@ static struct snd_soc_dai_link msm_ext_common_be_dai[] = { .ignore_suspend = 1, .ignore_pmdown_time = 1, }, + /* Proxy Tx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_TX, + .stream_name = "Proxy Capture", + .cpu_dai_name = "msm-dai-q6-dev.8195", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_PROXY_TX, + .ignore_suspend = 1, + }, + /* Proxy Rx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_RX, + .stream_name = "Proxy Playback", + .cpu_dai_name = "msm-dai-q6-dev.8194", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_PROXY_RX, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, { .name = LPASS_BE_USB_AUDIO_RX, .stream_name = "USB Audio Playback", @@ -1289,6 +1337,7 @@ static struct snd_soc_dai_link msm_ext_common_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "msm-stub-codec.1", .codec_dai_name = "msm-stub-rx", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_USB_RX, @@ -1769,6 +1818,7 @@ static struct snd_soc_dai_link msm_wcn_be_dai_links[] = { * supported usecase information */ .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_7_RX, @@ -1785,6 +1835,7 @@ static struct snd_soc_dai_link msm_wcn_be_dai_links[] = { .platform_name = "msm-pcm-routing", .codec_name = "btfmslim_slave", .codec_dai_name = "btfm_bt_sco_slim_tx", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_7_TX, @@ -1799,6 +1850,7 @@ static struct snd_soc_dai_link msm_wcn_be_dai_links[] = { .platform_name = "msm-pcm-routing", .codec_name = "btfmslim_slave", .codec_dai_name = "btfm_fm_slim_tx", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_8_TX, @@ -1814,7 +1866,7 @@ static struct snd_soc_dai_link ext_disp_be_dai_link[] = { { .name = LPASS_BE_DISPLAY_PORT, .stream_name = "Display Port Playback", - .cpu_dai_name = "msm-dai-q6-dp.24608", + .cpu_dai_name = "msm-dai-q6-dp.0", .platform_name = "msm-pcm-routing", .codec_name = "msm-ext-disp-audio-codec-rx", .codec_dai_name = "msm_dp_audio_codec_rx_dai", diff --git a/techpack/audio/asoc/sdm660-external.c b/techpack/audio/asoc/sdm660-external.c index 6edec14d2b8cb7a2ddc70cae43b6f5c9e11f719d..41995f45adea67cb5139533a1251d8ff03e1d1e2 100644 --- a/techpack/audio/asoc/sdm660-external.c +++ b/techpack/audio/asoc/sdm660-external.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2018, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2018, 2020-2021, The Linux Foundation. All rights reserved. */ #include @@ -48,6 +48,8 @@ #define WSA8810_NAME_1 "wsa881x.20170211" #define WSA8810_NAME_2 "wsa881x.20170212" #define SDM660_SOC_MSM_ID 0x13D +#define SDM660_SOC_SDA_ID 0x144 + static int msm_ext_spk_control = 1; static struct wcd_mbhc_config *wcd_mbhc_cfg_ptr; @@ -1294,9 +1296,10 @@ static int msm_adsp_power_up_config(struct snd_soc_component *component, goto err_fail; } - if (socinfo_get_id() == SDM660_SOC_MSM_ID) + if (socinfo_get_id() == SDM660_SOC_MSM_ID || + socinfo_get_id() == SDM660_SOC_SDA_ID) { msm_snd_interrupt_config(pdata); - + } ret = msm_afe_set_config(component); if (ret) pr_err("%s: Failed to set AFE config. err %d\n", diff --git a/techpack/audio/asoc/sdm660-internal.c b/techpack/audio/asoc/sdm660-internal.c index f1ae71951e9ed953174d61d24c2119b2568790f3..68b2636ee4d5d85d1bbaf986085fc081c4c940ff 100644 --- a/techpack/audio/asoc/sdm660-internal.c +++ b/techpack/audio/asoc/sdm660-internal.c @@ -2422,6 +2422,33 @@ static struct snd_soc_dai_link msm_int_be_dai[] = { .ignore_suspend = 1, .ignore_pmdown_time = 1, }, + /* Proxy Tx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_TX, + .stream_name = "Proxy Capture", + .cpu_dai_name = "msm-dai-q6-dev.8195", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_PROXY_TX, + .ignore_suspend = 1, + }, + /* Proxy Rx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_RX, + .stream_name = "Proxy Playback", + .cpu_dai_name = "msm-dai-q6-dev.8194", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_PROXY_RX, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, { .name = LPASS_BE_USB_AUDIO_RX, .stream_name = "USB Audio Playback", @@ -2973,7 +3000,7 @@ static struct snd_soc_dai_link ext_disp_be_dai_link[] = { { .name = LPASS_BE_DISPLAY_PORT, .stream_name = "Display Port Playback", - .cpu_dai_name = "msm-dai-q6-dp.24608", + .cpu_dai_name = "msm-dai-q6-dp.0", .platform_name = "msm-pcm-routing", .codec_name = "msm-ext-disp-audio-codec-rx", .codec_dai_name = "msm_dp_audio_codec_rx_dai", diff --git a/techpack/audio/config/konaauto.conf b/techpack/audio/config/konaauto.conf index 787528f2914cfdc9104cb165548ce71d1f623495..9310ce5e6f39607f6cf53a5726e162ed1dbe672a 100644 --- a/techpack/audio/config/konaauto.conf +++ b/techpack/audio/config/konaauto.conf @@ -4,6 +4,7 @@ export CONFIG_AUDIO_EXT_CLK=m export CONFIG_SND_SOC_WCD9XXX_V2=m export CONFIG_SND_SOC_WCD_MBHC=m export CONFIG_SND_SOC_WSA881X=m +export CONFIG_SND_SOC_WSA883X=m export CONFIG_WCD9XXX_CODEC_CORE_V2=m export CONFIG_MSM_CDC_PINCTRL=m export CONFIG_MSM_QDSP6V2_CODECS=m diff --git a/techpack/audio/config/konaautoconf.h b/techpack/audio/config/konaautoconf.h index 680359e26527e4d81a7af12d658fe7e822611746..4b031439140e553f3b17709e2d47784231a59cde 100644 --- a/techpack/audio/config/konaautoconf.h +++ b/techpack/audio/config/konaautoconf.h @@ -8,6 +8,7 @@ #define CONFIG_SND_SOC_WCD9XXX_V2 1 #define CONFIG_SND_SOC_WCD_MBHC 1 #define CONFIG_SND_SOC_WSA881X 1 +#define CONFIG_SND_SOC_WSA883X 1 #define CONFIG_WCD9XXX_CODEC_CORE_V2 1 #define CONFIG_MSM_CDC_PINCTRL 1 #define CONFIG_MSM_QDSP6V2_CODECS 1 diff --git a/techpack/audio/config/sdm450auto.conf b/techpack/audio/config/sdm450auto.conf new file mode 100644 index 0000000000000000000000000000000000000000..ddd9deac94eb7ec370fbea048567a201c35332d1 --- /dev/null +++ b/techpack/audio/config/sdm450auto.conf @@ -0,0 +1,43 @@ +CONFIG_PINCTRL_WCD=m +CONFIG_AUDIO_EXT_CLK=m +CONFIG_SND_SOC_WCD9XXX_V2=m +CONFIG_SND_SOC_WCD_MBHC=m +CONFIG_SND_SOC_WCD_CPE=m +CONFIG_SND_SOC_CPE=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_WSA881X_ANALOG=m +CONFIG_SND_SOC_WCD9335=m +CONFIG_MSM_QDSP6V2_CODECS=m +CONFIG_MSM_ULTRASOUND=m +CONFIG_MSM_QDSP6_APRV2_RPMSG=m +CONFIG_MSM_ADSP_LOADER=m +CONFIG_REGMAP_SWR=m +CONFIG_MSM_QDSP6_SSR=m +CONFIG_MSM_QDSP6_NOTIFIER=m +CONFIG_SND_SOC_MSM_HOSTLESS_PCM=m +CONFIG_SND_SOC_MSM_QDSP6V2_INTF=m +CONFIG_SND_SOC_SDM450=m +CONFIG_SND_SOC_EXT_CODEC_SDM450=m +CONFIG_SOUNDWIRE=m +CONFIG_SOUNDWIRE_WCD_CTRL=m +CONFIG_SND_SOC_QDSP6V2=m +CONFIG_SND_SOC_MSM_QDSP6V2_INTF=m +CONFIG_WCD9XXX_CODEC_CORE=m +CONFIG_MSM_CDC_PINCTRL=m +CONFIG_SND_SOC_WCD_MBHC_LEGACY=m +CONFIG_QTI_PP=m +CONFIG_QTI_PP_AUDIOSPHERE=m +CONFIG_SND_HWDEP_ROUTING=m +CONFIG_DTS_EAGLE=m +CONFIG_DOLBY_DS2=m +CONFIG_DOLBY_LICENSE=m +CONFIG_DTS_SRS_TM=m +CONFIG_SND_SOC_MSM_STUB=m +CONFIG_SND_SOC_SDM660_CDC=m +CONFIG_SND_SOC_ANALOG_CDC=m +CONFIG_SND_SOC_DIGITAL_CDC_LEGACY=m +CONFIG_SND_SOC_MSM_HDMI_CODEC_RX=m +CONFIG_WCD_DSP_GLINK=m +CONFIG_TDM_DISABLE=m +CONFIG_AUXPCM_DISABLE=m +CONFIG_CDC_DMA_DISABLE=m diff --git a/techpack/audio/config/sdm450autoconf.h b/techpack/audio/config/sdm450autoconf.h new file mode 100644 index 0000000000000000000000000000000000000000..777f9261c28f011797cf4463de153ea77f82cbfd --- /dev/null +++ b/techpack/audio/config/sdm450autoconf.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2018, 2020-2021, The Linux Foundation. All rights reserved. + */ + +#define CONFIG_PINCTRL_WCD 1 +#define CONFIG_AUDIO_EXT_CLK 1 +#define CONFIG_SND_SOC_WCD9XXX_V2 1 +#define CONFIG_SND_SOC_WCD_CPE 1 +#define CONFIG_SND_SOC_CPE 1 +#define CONFIG_SND_SOC_WCD_MBHC 1 +#define CONFIG_SND_SOC_WSA881X 1 +#define CONFIG_SND_SOC_WSA881X_ANALOG 1 +#define CONFIG_SND_SOC_WCD9335 1 +#define CONFIG_MSM_QDSP6V2_CODECS 1 +#define CONFIG_MSM_ULTRASOUND 1 +#define CONFIG_MSM_QDSP6_APRV2_RPMSG 1 +#define CONFIG_MSM_ADSP_LOADER 1 +#define CONFIG_REGMAP_SWR 1 +#define CONFIG_MSM_QDSP6_SSR 1 +#define CONFIG_MSM_QDSP6_NOTIFIER 1 +#define CONFIG_SND_SOC_MSM_HOSTLESS_PCM 1 +#define CONFIG_SND_SOC_MSM_QDSP6V2_INTF 1 +#define CONFIG_SND_SOC_SDM450 1 +#define CONFIG_SND_SOC_EXT_CODEC_SDM450 1 +#define CONFIG_SOUNDWIRE 1 +#define CONFIG_SOUNDWIRE_WCD_CTRL 1 +#define CONFIG_SND_SOC_WCD_MBHC_LEGACY 1 +#define CONFIG_SND_SOC_QDSP6V2 1 +#define CONFIG_QTI_PP 1 +#define CONFIG_QTI_PP_AUDIOSPHERE 1 +#define CONFIG_SND_HWDEP_ROUTING 1 +#define CONFIG_DTS_EAGLE 1 +#define CONFIG_DOLBY_DS2 1 +#define CONFIG_DOLBY_LICENSE 1 +#define CONFIG_DTS_SRS_TM 1 +#define CONFIG_WCD9XXX_CODEC_CORE 1 +#define CONFIG_MSM_CDC_PINCTRL 1 +#define CONFIG_SND_SOC_MSM_STUB 1 +#define CONFIG_SND_SOC_EXT_CODEC 1 +#define CONFIG_SND_SOC_INT_CODEC 1 +#define CONFIG_SND_SOC_SDM660_CDC 1 +#define CONFIG_SND_SOC_ANALOG_CDC 1 +#define CONFIG_SND_SOC_DIGITAL_CDC_LEGACY 1 +#define CONFIG_SND_SOC_MSM_HDMI_CODEC_RX 1 +#define CONFIG_COMMON_CLK 1 +#define CONFIG_WCD_DSP_GLINK 1 +#define CONFIG_TDM_DISABLE 1 +#define CONFIG_AUXPCM_DISABLE 1 +#define CONFIG_CDC_DMA_DISABLE 1 diff --git a/techpack/audio/config/sdm660auto.conf b/techpack/audio/config/sdm660auto.conf index 7f0d1d7e6dbd1fc1c34430b14c7c6cadf7aadd18..241ca05814d4918758fd24fb8737ea0be2e649b0 100644 --- a/techpack/audio/config/sdm660auto.conf +++ b/techpack/audio/config/sdm660auto.conf @@ -6,6 +6,8 @@ CONFIG_SND_SOC_WCD_MBHC=m CONFIG_SND_SOC_WSA881X=m CONFIG_SND_SOC_WCD_DSP_MGR=m CONFIG_SND_SOC_WCD_SPI=m +CONFIG_SND_SOC_WCD_CPE=m +CONFIG_SND_SOC_CPE=m CONFIG_SND_SOC_WCD9335=m CONFIG_SND_SOC_WCD934X=m CONFIG_SND_SOC_WCD934X_MBHC=m diff --git a/techpack/audio/config/sdm660autoconf.h b/techpack/audio/config/sdm660autoconf.h index d55918be1235eed052521ffb4f19703eab500151..81c28e6d3debdadb80dad03b777037c9404ec3ca 100644 --- a/techpack/audio/config/sdm660autoconf.h +++ b/techpack/audio/config/sdm660autoconf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -15,6 +15,7 @@ #define CONFIG_PINCTRL_WCD 1 #define CONFIG_AUDIO_EXT_CLK 1 #define CONFIG_SND_SOC_WCD9XXX_V2 1 +#define CONFIG_SND_SOC_WCD_CPE 1 #define CONFIG_SND_SOC_WCD_MBHC 1 #define CONFIG_SND_SOC_WSA881X 1 #define CONFIG_SND_SOC_WCD_DSP_MGR 1 @@ -54,8 +55,10 @@ #define CONFIG_MSM_AVTIMER 1 #define CONFIG_SND_SOC_EXT_CODEC 1 #define CONFIG_SND_SOC_INT_CODEC 1 +#define CONFIG_SND_SOC_CPE 1 #define CONFIG_SND_SOC_SDM660_CDC 1 #define CONFIG_SND_SOC_ANALOG_CDC 1 #define CONFIG_SND_SOC_DIGITAL_CDC 1 #define CONFIG_SND_SOC_MSM_SDW 1 #define CONFIG_SND_SOC_MSM_HDMI_CODEC_RX 1 +#define CONFIG_WCD_SPI_DMA_MASKING 1 diff --git a/techpack/audio/dsp/Android.mk b/techpack/audio/dsp/Android.mk index 90a486e46fc7180ce06d05bd5c5c63eb64022f24..699b1c91b5cbb910207d0dcfc3def0c248e7be91 100644 --- a/techpack/audio/dsp/Android.mk +++ b/techpack/audio/dsp/Android.mk @@ -35,9 +35,13 @@ ifeq ($(call is-board-platform,sdm660),true) AUDIO_SELECT := CONFIG_SND_SOC_SDM660=m endif +ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) +AUDIO_SELECT := CONFIG_SND_SOC_SDM450=m +endif + AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) @@ -98,6 +102,7 @@ LOCAL_MODULE_DEBUG_ENABLE := true LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk ########################################################### +ifneq ($(call is-board-platform-in-list, msm8937 msm8953),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_q6_pdr.ko LOCAL_MODULE_KBUILD_NAME := q6_pdr_dlkm.ko @@ -105,6 +110,7 @@ LOCAL_MODULE_TAGS := optional LOCAL_MODULE_DEBUG_ENABLE := true LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk +endif ########################################################### endif # target specific build endif # DLKM check diff --git a/techpack/audio/dsp/Kbuild b/techpack/audio/dsp/Kbuild index 490b458bfc2b12674837954ab6ab7fc05f1fe41e..aaa293697ad15647bdda4141530aab10a244e889 100644 --- a/techpack/audio/dsp/Kbuild +++ b/techpack/audio/dsp/Kbuild @@ -81,6 +81,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif @@ -262,6 +277,3 @@ q6_pdr_dlkm-y := $(QDSP6_PDR_OBJS) obj-$(CONFIG_MSM_QDSP6_NOTIFIER) += q6_notifier_dlkm.o q6_notifier_dlkm-y := $(QDSP6_NOTIFIER_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/dsp/audio_notifier.c b/techpack/audio/dsp/audio_notifier.c index 7a8249dc3d0aa472c8945d518d36a9d3aac915b1..cdb80fbdcf5ec5bd10939888bf13871addb4ec30 100644 --- a/techpack/audio/dsp/audio_notifier.c +++ b/techpack/audio/dsp/audio_notifier.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017, 2021, The Linux Foundation. All rights reserved. */ #include @@ -629,7 +629,7 @@ static int __init audio_notifier_init(void) static int __init audio_notifier_init(void) { audio_notifier_subsys_init(); - audio_notifier_disable_service(AUDIO_NOTIFIER_PDR_SERVICE); + audio_notifer_disable_service(AUDIO_NOTIFIER_PDR_SERVICE); audio_notifier_late_init(); diff --git a/techpack/audio/dsp/avtimer.c b/techpack/audio/dsp/avtimer.c index e1d032d53661cae4ea0bfd6de746566c7cdaddbb..283eee57e7250b05391e15cbdf7f733f161815c9 100644 --- a/techpack/audio/dsp/avtimer.c +++ b/techpack/audio/dsp/avtimer.c @@ -336,11 +336,6 @@ int avcs_core_query_timer_offset(int64_t *av_offset, int32_t clock_id) uint64_t avtimer_tick_temp, avtimer_tick, sys_time = 0; struct timespec ts; - if (!atomic_read(&avtimer.adsp_ready)) { - pr_debug("%s:In SSR, return\n", __func__); - return -ENETRESET; - } - if ((avtimer.p_avtimer_lsw == NULL) || (avtimer.p_avtimer_msw == NULL)) { return -EINVAL; diff --git a/techpack/audio/dsp/codecs/Android.mk b/techpack/audio/dsp/codecs/Android.mk index a27f1b06d5a691e5c00b52548011fb3a47708501..ceb1c8f2490b5314ac99802822990acca9d82f0c 100644 --- a/techpack/audio/dsp/codecs/Android.mk +++ b/techpack/audio/dsp/codecs/Android.mk @@ -27,9 +27,13 @@ ifeq ($(call is-board-platform,sdm660),true) AUDIO_SELECT := CONFIG_SND_SOC_SDM660=m endif +ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) +AUDIO_SELECT := CONFIG_SND_SOC_SDM450=m +endif + AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) diff --git a/techpack/audio/dsp/codecs/Kbuild b/techpack/audio/dsp/codecs/Kbuild index 808bfe22a076f2f5fd93bc7e19b3cfa9752e6b3a..89aeab7fdcd33895ebfb075a90e97ae4e0c2e0b2 100644 --- a/techpack/audio/dsp/codecs/Kbuild +++ b/techpack/audio/dsp/codecs/Kbuild @@ -63,6 +63,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: @@ -161,6 +176,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_MSM_QDSP6V2_CODECS) += native_dlkm.o native_dlkm-y := $(NATIVE_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/dsp/msm_audio_ion.c b/techpack/audio/dsp/msm_audio_ion.c index 2bf02fcad7bbc8d9e6163fa4c42d42e6c17224ae..e97d35194b509cdcb2cde7ba02445f81db0bb140 100644 --- a/techpack/audio/dsp/msm_audio_ion.c +++ b/techpack/audio/dsp/msm_audio_ion.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2019, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -63,6 +64,7 @@ static void msm_audio_ion_add_allocation( mutex_unlock(&(msm_audio_ion_data->list_mutex)); } +/* This function is called with ion_data list mutex lock */ static int msm_audio_dma_buf_map(struct dma_buf *dma_buf, dma_addr_t *addr, size_t *len) { @@ -151,7 +153,6 @@ static int msm_audio_dma_buf_unmap(struct dma_buf *dma_buf) * should be explicitly acquired to avoid race condition * on adding elements to the list. */ - mutex_lock(&(msm_audio_ion_data.list_mutex)); list_for_each_safe(ptr, next, &(msm_audio_ion_data.alloc_list)) { @@ -175,7 +176,6 @@ static int msm_audio_dma_buf_unmap(struct dma_buf *dma_buf) break; } } - mutex_unlock(&(msm_audio_ion_data.list_mutex)); if (!found) { dev_err(cb_dev, @@ -230,6 +230,7 @@ int msm_audio_ion_get_smmu_info(struct device **cb_dev, return 0; } +/* This function is called with ion_data list mutex lock */ static void *msm_audio_ion_map_kernel(struct dma_buf *dma_buf) { int rc = 0; @@ -278,7 +279,6 @@ static int msm_audio_ion_unmap_kernel(struct dma_buf *dma_buf) * TBD: remove the below section once new API * for unmapping kernel virtual address is available. */ - mutex_lock(&(msm_audio_ion_data.list_mutex)); list_for_each_entry(alloc_data, &(msm_audio_ion_data.alloc_list), list) { if (alloc_data->dma_buf == dma_buf) { @@ -286,7 +286,6 @@ static int msm_audio_ion_unmap_kernel(struct dma_buf *dma_buf) break; } } - mutex_unlock(&(msm_audio_ion_data.list_mutex)); if (!vaddr) { dev_err(cb_dev, @@ -309,7 +308,8 @@ static int msm_audio_ion_unmap_kernel(struct dma_buf *dma_buf) return rc; } -static int msm_audio_ion_map_buf(struct dma_buf *dma_buf, dma_addr_t *paddr, +/* This function is called with ion_data list mutex lock */ +static int msm_audio_ion_buf_map(struct dma_buf *dma_buf, dma_addr_t *paddr, size_t *plen, void **vaddr) { int rc = 0; @@ -331,7 +331,10 @@ static int msm_audio_ion_map_buf(struct dma_buf *dma_buf, dma_addr_t *paddr, if (IS_ERR_OR_NULL(*vaddr)) { pr_err("%s: ION memory mapping for AUDIO failed\n", __func__); rc = -ENOMEM; + mutex_lock(&(msm_audio_ion_data.list_mutex)); msm_audio_dma_buf_unmap(dma_buf); + mutex_unlock(&(msm_audio_ion_data.list_mutex)); + goto err; } @@ -390,7 +393,7 @@ int msm_audio_ion_alloc(struct dma_buf **dma_buf, size_t bufsz, goto err; } - rc = msm_audio_ion_map_buf(*dma_buf, paddr, plen, vaddr); + rc = msm_audio_ion_buf_map(*dma_buf, paddr, plen, vaddr); if (rc) { pr_err("%s: failed to map ION buf, rc = %d\n", __func__, rc); goto err; @@ -490,7 +493,7 @@ int msm_audio_ion_import(struct dma_buf **dma_buf, int fd, } } - rc = msm_audio_ion_map_buf(*dma_buf, paddr, plen, vaddr); + rc = msm_audio_ion_buf_map(*dma_buf, paddr, plen, vaddr); if (rc) { pr_err("%s: failed to map ION buf, rc = %d\n", __func__, rc); goto err; @@ -516,6 +519,7 @@ EXPORT_SYMBOL(msm_audio_ion_import); * * Returns 0 on success or error on failure */ +/* This funtion is called with ion_data list mutex lock */ int msm_audio_ion_free(struct dma_buf *dma_buf) { int ret = 0; @@ -525,11 +529,15 @@ int msm_audio_ion_free(struct dma_buf *dma_buf) return -EINVAL; } + mutex_lock(&(msm_audio_ion_data.list_mutex)); ret = msm_audio_ion_unmap_kernel(dma_buf); - if (ret) + if (ret) { + mutex_unlock(&(msm_audio_ion_data.list_mutex)); return ret; + } msm_audio_dma_buf_unmap(dma_buf); + mutex_unlock(&(msm_audio_ion_data.list_mutex)); return 0; } diff --git a/techpack/audio/dsp/q6adm.c b/techpack/audio/dsp/q6adm.c index 0db7f63fcc20a5d0579cebcd42406a57151c4751..0e98ac51c689c5d95bdcfa0d43517d598d2d631d 100644 --- a/techpack/audio/dsp/q6adm.c +++ b/techpack/audio/dsp/q6adm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -1712,7 +1713,7 @@ static int32_t adm_callback(struct apr_client_data *data, void *priv) { uint32_t *payload; int port_idx, copp_idx, idx, client_id; - int num_modules; + uint32_t num_modules; int ret; if (data == NULL) { diff --git a/techpack/audio/dsp/q6afe.c b/techpack/audio/dsp/q6afe.c index 0b891d1de5af4ffa1311613cf9395ae6ee064944..1882aee497cc4cd9d1ca023758db954fb3e94ccc 100644 --- a/techpack/audio/dsp/q6afe.c +++ b/techpack/audio/dsp/q6afe.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -312,45 +313,74 @@ struct afe_ctl { struct afe_clkinfo_per_port { u16 port_id; /* AFE port ID */ - uint32_t clk_id; /* Clock ID */ + uint32_t mclk_src_id; /* MCLK SRC ID */ + uint32_t mclk_freq; /* MCLK_FREQ */ + char clk_src_name[CLK_SRC_NAME_MAX]; }; -struct afe_clkinfo_per_port clkinfo_per_port[] = { - { AFE_PORT_ID_PRIMARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT}, - { AFE_PORT_ID_SECONDARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT}, - { AFE_PORT_ID_TERTIARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT}, - { AFE_PORT_ID_QUATERNARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT}, - { AFE_PORT_ID_QUINARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT}, - { AFE_PORT_ID_SENARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT}, - { AFE_PORT_ID_PRIMARY_PCM_RX, Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT}, - { AFE_PORT_ID_SECONDARY_PCM_RX, Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT}, - { AFE_PORT_ID_TERTIARY_PCM_RX, Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT}, - { AFE_PORT_ID_QUATERNARY_PCM_RX, Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT}, - { AFE_PORT_ID_QUINARY_PCM_RX, Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT}, - { AFE_PORT_ID_SENARY_PCM_RX, Q6AFE_LPASS_CLK_ID_SEN_PCM_IBIT}, - { AFE_PORT_ID_PRIMARY_TDM_RX, Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT}, - { AFE_PORT_ID_SECONDARY_TDM_RX, Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT}, - { AFE_PORT_ID_TERTIARY_TDM_RX, Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT}, - { AFE_PORT_ID_QUATERNARY_TDM_RX, Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT}, - { AFE_PORT_ID_QUINARY_TDM_RX, Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT}, +struct afe_ext_mclk_cb_info { + afe_enable_mclk_and_get_info_cb_func ext_mclk_cb; + void *private_data; +}; + +static struct afe_clkinfo_per_port clkinfo_per_port[] = { + { AFE_PORT_ID_PRIMARY_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_SECONDARY_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_TERTIARY_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_QUATERNARY_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_QUINARY_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_SENARY_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_PRIMARY_PCM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_SECONDARY_PCM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_TERTIARY_PCM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_QUATERNARY_PCM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_QUINARY_PCM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_SENARY_PCM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_PRIMARY_TDM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_SECONDARY_TDM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_TERTIARY_TDM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_QUATERNARY_TDM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_QUINARY_TDM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_SENARY_TDM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, { AFE_PORT_ID_PRIMARY_SPDIF_RX, - AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE}, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, { AFE_PORT_ID_PRIMARY_SPDIF_TX, - AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE}, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, { AFE_PORT_ID_SECONDARY_SPDIF_RX, - AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE}, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, { AFE_PORT_ID_SECONDARY_SPDIF_TX, - AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE}, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, { AFE_PORT_ID_PRIMARY_META_MI2S_RX, - Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT}, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, { AFE_PORT_ID_SECONDARY_META_MI2S_RX, - Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT}, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, }; +static struct afe_ext_mclk_cb_info afe_ext_mclk; + static atomic_t afe_ports_mad_type[SLIMBUS_PORT_LAST - SLIMBUS_0_RX]; static unsigned long afe_configured_cmd; static struct afe_ctl this_afe; +static char clk_src_name[CLK_SRC_MAX][CLK_SRC_NAME_MAX]; #define TIMEOUT_MS 1000 #define Q6AFE_MAX_VOLUME 0x3FFF @@ -549,6 +579,37 @@ int adsp_subsystem_restart(const char *name) EXPORT_SYMBOL(adsp_subsystem_restart); #endif /* OPLUS_FEATURE_ADSP_RECOVERY */ +/** + * afe_register_ext_mclk_cb - register callback for external mclk + * + * @fn - external mclk callback function + * @private_data - external mclk callback specific data + * + * Returns 0 in case of success and -EINVAL for failure + */ +int afe_register_ext_mclk_cb(afe_enable_mclk_and_get_info_cb_func fn, + void *private_data) +{ + if (fn && private_data) { + afe_ext_mclk.ext_mclk_cb = fn; + afe_ext_mclk.private_data = private_data; + return 0; + } + + return -EINVAL; +} +EXPORT_SYMBOL(afe_register_ext_mclk_cb); + +/** + * afe_unregister_ext_mclk_cb - unregister external mclk callback + */ +void afe_unregister_ext_mclk_cb(void) +{ + afe_ext_mclk.ext_mclk_cb = NULL; + afe_ext_mclk.private_data = NULL; +} +EXPORT_SYMBOL(afe_unregister_ext_mclk_cb); + int afe_get_spk_initial_cal(void) { return this_afe.initial_cal; @@ -805,23 +866,48 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, switch (param_hdr.param_id) { case AFE_PARAM_ID_CALIB_RES_CFG_V2: expected_size += sizeof(struct asm_calib_res_cfg); + if (param_hdr.param_size != sizeof(struct asm_calib_res_cfg)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.calib_data; break; case AFE_PARAM_ID_SP_V2_TH_VI_FTM_PARAMS: expected_size += sizeof(struct afe_sp_th_vi_ftm_params); + if (param_hdr.param_size != sizeof(struct afe_sp_th_vi_ftm_params)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.th_vi_resp; break; case AFE_PARAM_ID_SP_V2_TH_VI_V_VALI_PARAMS: expected_size += sizeof(struct afe_sp_th_vi_v_vali_params); + if (param_hdr.param_size != sizeof(struct afe_sp_th_vi_v_vali_params)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.th_vi_v_vali_resp; break; case AFE_PARAM_ID_SP_V2_EX_VI_FTM_PARAMS: expected_size += sizeof(struct afe_sp_ex_vi_ftm_params); + if (param_hdr.param_size != sizeof(struct afe_sp_ex_vi_ftm_params)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.ex_vi_resp; break; case AFE_PARAM_ID_SP_RX_TMAX_XMAX_LOGGING: expected_size += sizeof( struct afe_sp_rx_tmax_xmax_logging_param); + if (param_hdr.param_size != sizeof(struct afe_sp_rx_tmax_xmax_logging_param)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.xt_logging_resp; break; #ifdef OPLUS_ARCH_EXTENDS @@ -840,10 +926,27 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, case AFE_PARAM_ID_SP_V4_CALIB_RES_CFG: expected_size += sizeof( struct afe_sp_v4_param_th_vi_calib_res_cfg); + if (param_hdr.param_size != sizeof( + struct afe_sp_v4_param_th_vi_calib_res_cfg)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.spv4_calib_data; break; case AFE_PARAM_ID_SP_V4_TH_VI_FTM_PARAMS: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_th_vi_ftm_params) + + (num_ch * sizeof(struct afe_sp_v4_channel_ftm_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_th_vi_ftm_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_th_vi_ftm_resp; expected_size += @@ -852,6 +955,18 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_TH_VI_V_VALI_PARAMS: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_th_vi_v_vali_params) + + (num_ch * + sizeof(struct afe_sp_v4_channel_v_vali_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_v_vali_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_v_vali_resp; expected_size += @@ -861,6 +976,18 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_EX_VI_FTM_PARAMS: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_ex_vi_ftm_params) + + (num_ch * + sizeof(struct afe_sp_v4_channel_ex_vi_ftm_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_ex_vi_ftm_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_ex_vi_ftm_resp; expected_size += @@ -869,6 +996,18 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_RX_TMAX_XMAX_LOGGING: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_tmax_xmax_logging) + + (num_ch * + sizeof(struct afe_sp_v4_channel_tmax_xmax_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_max_log_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_max_log_resp; expected_size += @@ -1026,6 +1165,19 @@ static int32_t afe_callback(struct apr_client_data *data, void *priv) mutex_lock(&this_afe.afe_cmd_lock); for (i = 0; i < AFE_LPASS_CORE_HW_VOTE_MAX; i++) this_afe.lpass_hw_core_client_hdl[i] = 0; + + /* + * Free the port mapping structures used for AVCS module + * load/unload. + */ + for (i = 0; i < MAX_ALLOWED_USE_CASES; i++) { + if (pm[i]) { + kfree(pm[i]->payload); + pm[i]->payload = NULL; + kfree(pm[i]); + pm[i] = NULL; + } + } mutex_unlock(&this_afe.afe_cmd_lock); /* @@ -1298,6 +1450,9 @@ static int32_t afe_callback(struct apr_client_data *data, void *priv) sizeof(struct afe_port_mod_evt_rsp_hdr)); uint32_t *dc_presence_flag = num_channels + 1; + if (*num_channels < 1 || *num_channels > 4) + return -EINVAL; + for (i = 0; i < *num_channels; i++) { if (dc_presence_flag[i] == 1) dc_detected = true; @@ -3439,6 +3594,54 @@ static int afe_get_cal_topology_id(u16 port_id, u32 *topology_id, return ret; } +static int afe_port_topology_deregister(u16 port_id) +{ + struct param_hdr_v3 param_info; + int ret = 0; + uint32_t build_major_version = 0; + uint32_t build_minor_version = 0; + uint32_t build_branch_version = 0; + uint32_t afe_api_version = 0; + + ret = q6core_get_avcs_avs_build_version_info( + &build_major_version, &build_minor_version, + &build_branch_version); + if (ret < 0) + goto done; + + ret = q6core_get_avcs_api_version_per_service( + APRV2_IDS_SERVICE_ID_ADSP_AFE_V); + if (ret < 0) + goto done; + afe_api_version = ret; + pr_debug("%s: mjor: %u, mnor: %u, brnch: %u, afe_api: %u\n", + __func__, build_major_version, build_minor_version, + build_branch_version, afe_api_version); + if ((build_major_version != AVS_BUILD_MAJOR_VERSION_V2) || + (build_minor_version != AVS_BUILD_MINOR_VERSION_V9) || + (build_branch_version != + AVS_BUILD_BRANCH_VERSION_V3) || + (afe_api_version < AFE_API_VERSION_V9)) { + ret = 0; + goto done; + } + + memset(¶m_info, 0, sizeof(param_info)); + param_info.module_id = AFE_MODULE_AUDIO_DEV_INTERFACE; + param_info.instance_id = INSTANCE_ID_0; + param_info.param_id = AFE_PARAM_ID_DEREGISTER_TOPOLOGY; + param_info.param_size = 0; + ret = q6afe_pack_and_set_param_in_band(port_id, + q6audio_get_port_index(port_id), + param_info, NULL); + + return ret; +done: + pr_debug("%s build ver mismatch - leaving function %d\n", + __func__, ret); + return ret; +} + static int afe_send_port_topology_id(u16 port_id) { struct afe_param_id_set_topology_cfg topology; @@ -3447,6 +3650,13 @@ static int afe_send_port_topology_id(u16 port_id) int index = 0; int ret = 0; + ret = afe_port_topology_deregister(port_id); + if (ret < 0) { + pr_err("%s: AFE deregister topology for port 0x%x failed %d\n", + __func__, port_id, ret); + goto done; + } + memset(&topology, 0, sizeof(topology)); memset(¶m_info, 0, sizeof(param_info)); index = q6audio_get_port_index(port_id); @@ -5701,10 +5911,11 @@ static int __afe_port_start(u16 port_id, union afe_port_config *afe_config, union afe_port_config port_cfg; struct param_hdr_v3 param_hdr; int ret = 0; - int cfg_type; + int cfg_type = 0; int index = 0; enum afe_mad_type mad_type; uint16_t port_index; + u16 i; memset(¶m_hdr, 0, sizeof(param_hdr)); memset(&port_cfg, 0, sizeof(port_cfg)); @@ -6091,6 +6302,20 @@ static int __afe_port_start(u16 port_id, union afe_port_config *afe_config, ret = afe_send_cmd_port_start(port_id); fail_cmd: + if (ret) { + if ((codec_format != ASM_MEDIA_FMT_NONE) && + (cfg_type == AFE_PARAM_ID_SLIMBUS_CONFIG)) { + if ((q6core_get_avcs_api_version_per_service( + APRV2_IDS_SERVICE_ID_ADSP_CORE_V) >= AVCS_API_VERSION_V5)) { + for (i = 0; i < MAX_ALLOWED_USE_CASES; i++) { + if (pm[i] && pm[i]->port_id == port_id) { + q6afe_unload_avcs_modules(port_id, i); + break; + } + } + } + } + } mutex_unlock(&this_afe.afe_cmd_lock); return ret; } @@ -8264,6 +8489,14 @@ static int afe_sidetone_iir(u16 tx_port_id) pr_debug("%s: adding 2 to size:%d\n", __func__, size); size = size + 2; } + + if (size > MAX_SIDETONE_IIR_DATA_SIZE) { + pr_err("%s: iir_config size is out of bounds:%d\n", __func__, size); + mutex_unlock(&this_afe.cal_data[cal_index]->lock); + ret = -EINVAL; + goto done; + } + memcpy(&filter_data.iir_config, &st_iir_cal_info->iir_config, size); mutex_unlock(&this_afe.cal_data[cal_index]->lock); @@ -8854,8 +9087,7 @@ int afe_close(int port_id) (port_id == RT_PROXY_DAI_001_TX)) proxy_afe_instance[port_id & 0x1] = 0; afe_close_done[port_id & 0x1] = true; - ret = -EINVAL; - goto fail_cmd; + return -EINVAL; } pr_info("%s: port_id = 0x%x\n", __func__, port_id); if ((port_id == RT_PROXY_DAI_001_RX) || @@ -9109,53 +9341,73 @@ static int afe_get_port_idx(u16 port_id) return -EINVAL; } -static int afe_get_clk_id(u16 port_id) +static int afe_get_clk_src(u16 port_id, char *clk_src) { - u16 afe_port = 0; - uint32_t clk_id = -EINVAL; int idx = 0; idx = afe_get_port_idx(port_id); if (idx < 0) { pr_err("%s: cannot get clock id for port id 0x%x\n", __func__, - afe_port); + idx); return -EINVAL; } - clk_id = clkinfo_per_port[idx].clk_id; - pr_debug("%s: clk id 0x%x port id 0x%x\n", __func__, clk_id, - afe_port); + if (clkinfo_per_port[idx].clk_src_name == NULL) + return -EINVAL; + strlcpy(clk_src, clkinfo_per_port[idx].clk_src_name, + CLK_SRC_NAME_MAX); + pr_debug("%s: clk src name %s port id 0x%x\n", __func__, clk_src, + idx); - return clk_id; + return 0; } /** - * afe_set_clk_id - Update clock id for AFE port + * afe_set_source_clk - Set audio interface PLL clock source * * @port_id: AFE port id - * @clk_id: CLock ID + * @clk_src: Clock source name for port id * * Returns 0 on success, appropriate error code otherwise */ -int afe_set_clk_id(u16 port_id, uint32_t clk_id) +int afe_set_source_clk(u16 port_id, const char *clk_src) { - u16 afe_port = 0; int idx = 0; idx = afe_get_port_idx(port_id); if (idx < 0) { pr_debug("%s: cannot set clock id for port id 0x%x\n", __func__, - afe_port); + idx); return -EINVAL; } - clkinfo_per_port[idx].clk_id = clk_id; - pr_debug("%s: updated clk id 0x%x port id 0x%x\n", __func__, - clkinfo_per_port[idx].clk_id, afe_port); + if (clk_src == NULL) + return -EINVAL; + strlcpy(clkinfo_per_port[idx].clk_src_name, clk_src, CLK_SRC_NAME_MAX); + pr_debug("%s: updated clk src name %s port id 0x%x\n", __func__, + clkinfo_per_port[idx].clk_src_name, idx); return 0; } -EXPORT_SYMBOL(afe_set_clk_id); +EXPORT_SYMBOL(afe_set_source_clk); + +/** + * afe_set_clk_src_array - Set afe clk src array from machine driver + * + * @clk_src_array: clk src array for integral and fract clk src + * + */ +void afe_set_clk_src_array(const char *clk_src_array[CLK_SRC_MAX]) +{ + int i; + + for (i = 0; i < CLK_SRC_MAX; i++) { + if (clk_src_array[i] != NULL) + strlcpy(clk_src_name[i], clk_src_array[i], + CLK_SRC_NAME_MAX); + } +} +EXPORT_SYMBOL(afe_set_clk_src_array); /** * afe_set_pll_clk_drift - Set audio interface PLL clock drift @@ -9171,8 +9423,33 @@ int afe_set_pll_clk_drift(u16 port_id, int32_t set_clk_drift, { struct afe_set_clk_drift clk_drift; struct param_hdr_v3 param_hdr; - uint32_t clk_id; + char clk_src_name[CLK_SRC_NAME_MAX]; int index = 0, ret = 0; + uint32_t build_major_version = 0; + uint32_t build_minor_version = 0; + uint32_t build_branch_version = 0; + int afe_api_version = 0; + + ret = q6core_get_avcs_avs_build_version_info( + &build_major_version, &build_minor_version, + &build_branch_version); + if (ret < 0) { + pr_err("%s error in retrieving avs build version %d\n", + __func__, ret); + return ret; + } + + afe_api_version = q6core_get_avcs_api_version_per_service( + APRV2_IDS_SERVICE_ID_ADSP_AFE_V); + if (afe_api_version < 0) { + pr_err("%s error in retrieving afe api version %d\n", + __func__, afe_api_version); + return afe_api_version; + } + + pr_debug("%s: mjor: %u, mnor: %u, brnch: %u, afe_api: %u\n", + __func__, build_major_version, build_minor_version, + build_branch_version, afe_api_version); memset(¶m_hdr, 0, sizeof(param_hdr)); memset(&clk_drift, 0, sizeof(clk_drift)); @@ -9190,24 +9467,18 @@ int afe_set_pll_clk_drift(u16 port_id, int32_t set_clk_drift, return ret; } - clk_id = afe_get_clk_id(port_id); - if (clk_id < 0) { - pr_err("%s: cannot get clk id for port id 0x%x\n", + ret = afe_get_clk_src(port_id, clk_src_name); + if (ret) { + pr_err("%s: cannot get clk src name for port id 0x%x\n", __func__, port_id); return -EINVAL; } - if (clk_id & 0x01) { - pr_err("%s: cannot adjust clock drift for external clock id 0x%x\n", - __func__, clk_id); - return -EINVAL; - } - clk_drift.clk_drift = set_clk_drift; clk_drift.clk_reset = clk_reset; - clk_drift.clk_id = clk_id; - pr_debug("%s: clk id = 0x%x clk drift = %d clk reset = %d port id 0x%x\n", - __func__, clk_drift.clk_id, clk_drift.clk_drift, + strlcpy(clk_drift.clk_src_name, clk_src_name, CLK_SRC_NAME_MAX); + pr_debug("%s: clk src= %s clkdrft= %d clkrst= %d port id 0x%x\n", + __func__, clk_drift.clk_src_name, clk_drift.clk_drift, clk_drift.clk_reset, port_id); mutex_lock(&this_afe.afe_clk_lock); @@ -9216,17 +9487,110 @@ int afe_set_pll_clk_drift(u16 port_id, int32_t set_clk_drift, param_hdr.param_id = AFE_PARAM_ID_CLOCK_ADJUST; param_hdr.param_size = sizeof(struct afe_set_clk_drift); - ret = q6afe_svc_pack_and_set_param_in_band(index, param_hdr, + if ((build_major_version == AVS_BUILD_MAJOR_VERSION_V2) && + (build_minor_version == AVS_BUILD_MINOR_VERSION_V9) && + (build_branch_version == AVS_BUILD_BRANCH_VERSION_V3) && + (afe_api_version >= AFE_API_VERSION_V10)) { + + param_hdr.param_size = sizeof(struct afe_set_clk_drift); + ret = q6afe_svc_pack_and_set_param_in_band(index, param_hdr, (u8 *) &clk_drift); - if (ret < 0) - pr_err_ratelimited("%s: AFE PLL clk drift failed with ret %d\n", + if (ret < 0) + pr_err_ratelimited("%s: AFE PLL clk drift failed with ret %d\n", __func__, ret); - + } else { + ret = -EINVAL; + pr_err_ratelimited("%s: AFE PLL clk drift failed ver mismatch %d\n", + __func__, ret); + } mutex_unlock(&this_afe.afe_clk_lock); return ret; } EXPORT_SYMBOL(afe_set_pll_clk_drift); +static int afe_set_lpass_clk_cfg_ext_mclk(int index, struct afe_clk_set *cfg, + uint32_t mclk_freq) +{ + struct param_hdr_v3 param_hdr; + struct afe_param_id_clock_set_v2_t dyn_mclk_cfg; + int ret = 0; + + if (!cfg) { + pr_err("%s: clock cfg is NULL\n", __func__); + ret = -EINVAL; + return ret; + } + + if (index < 0 || index >= AFE_MAX_PORTS) { + pr_err("%s: index[%d] invalid!\n", __func__, index); + return -EINVAL; + } + + memset(¶m_hdr, 0, sizeof(param_hdr)); + param_hdr.module_id = AFE_MODULE_CLOCK_SET; + param_hdr.instance_id = INSTANCE_ID_0; + param_hdr.param_id = AFE_PARAM_ID_CLOCK_SET_V2; + param_hdr.param_size = sizeof(struct afe_param_id_clock_set_v2_t); + + memset(&dyn_mclk_cfg, 0, sizeof(dyn_mclk_cfg)); + dyn_mclk_cfg.clk_freq_in_hz = cfg->clk_freq_in_hz; + if (afe_ext_mclk.ext_mclk_cb) { + ret = afe_ext_mclk.ext_mclk_cb(afe_ext_mclk.private_data, + cfg->enable, mclk_freq, &dyn_mclk_cfg); + if (ret) { + pr_err_ratelimited("%s: get mclk cfg failed %d\n", + __func__, ret); + return ret; + } + } else { + pr_err_ratelimited("%s: mclk callback not registered\n", + __func__); + return -EINVAL; + } + + dyn_mclk_cfg.clk_set_minor_version = 1; + dyn_mclk_cfg.clk_id = cfg->clk_id; + dyn_mclk_cfg.clk_attri = cfg->clk_attri; + dyn_mclk_cfg.enable = cfg->enable; + + pr_debug("%s: Minor version =0x%x clk id = %d\n", __func__, + dyn_mclk_cfg.clk_set_minor_version, dyn_mclk_cfg.clk_id); + pr_debug("%s: clk freq (Hz) = %d, clk attri = 0x%x\n", __func__, + dyn_mclk_cfg.clk_freq_in_hz, dyn_mclk_cfg.clk_attri); + pr_debug("%s: clk root = 0x%x clk enable = 0x%x\n", __func__, + dyn_mclk_cfg.clk_root, dyn_mclk_cfg.enable); + pr_debug("%s: divider_2x =%d m = %d n = %d, d =%d\n", __func__, + dyn_mclk_cfg.divider_2x, dyn_mclk_cfg.m, dyn_mclk_cfg.n, + dyn_mclk_cfg.d); + + ret = afe_q6_interface_prepare(); + if (ret != 0) { + pr_err_ratelimited("%s: Q6 interface prepare failed %d\n", + __func__, ret); + goto stop_mclk; + } + + mutex_lock(&this_afe.afe_cmd_lock); + ret = q6afe_svc_pack_and_set_param_in_band(index, param_hdr, + (u8 *) &dyn_mclk_cfg); + if (ret < 0) + pr_err_ratelimited("%s: ext MCLK clk cfg failed with ret %d\n", + __func__, ret); + + mutex_unlock(&this_afe.afe_cmd_lock); + + if (ret >= 0) + return ret; + +stop_mclk: + if (afe_ext_mclk.ext_mclk_cb && cfg->enable) { + afe_ext_mclk.ext_mclk_cb(afe_ext_mclk.private_data, + cfg->enable, mclk_freq, &dyn_mclk_cfg); + } + + return ret; +} + /** * afe_set_lpass_clk_cfg - Set AFE clk config * @@ -9309,6 +9673,11 @@ int afe_set_lpass_clock_v2(u16 port_id, struct afe_clk_set *cfg) { int index = 0; int ret = 0; + int idx = 0; + uint32_t build_major_version = 0; + uint32_t build_minor_version = 0; + uint32_t build_branch_version = 0; + int afe_api_version = 0; index = q6audio_get_port_index(port_id); if (index < 0 || index >= AFE_MAX_PORTS) { @@ -9323,11 +9692,59 @@ int afe_set_lpass_clock_v2(u16 port_id, struct afe_clk_set *cfg) return -EINVAL; } - ret = afe_set_clk_id(port_id, cfg->clk_id); - if (ret < 0) - pr_debug("%s: afe_set_clk_id fail %d\n", __func__, ret); + if (clk_src_name != NULL) { + if (cfg->clk_freq_in_hz % AFE_SAMPLING_RATE_8KHZ) { + if (clk_src_name[CLK_SRC_FRACT] != NULL) + ret = afe_set_source_clk(port_id, + clk_src_name[CLK_SRC_FRACT]); + } else if (clk_src_name[CLK_SRC_INTEGRAL] != NULL) { + ret = afe_set_source_clk(port_id, + clk_src_name[CLK_SRC_INTEGRAL]); + } + if (ret < 0) + pr_err("%s: afe_set_source_clk fail %d\n", + __func__, ret); + } + idx = afe_get_port_idx(port_id); + if (idx < 0) { + pr_debug("%s: cannot get clock id for port id 0x%x\n", __func__, + port_id); + } else if (clkinfo_per_port[idx].mclk_src_id != MCLK_SRC_INT) { + pr_debug("%s: ext MCLK src %d\n", + __func__, clkinfo_per_port[idx].mclk_src_id); + + ret = q6core_get_avcs_avs_build_version_info( + &build_major_version, &build_minor_version, + &build_branch_version); + if (ret < 0) + return ret; + + ret = q6core_get_avcs_api_version_per_service( + APRV2_IDS_SERVICE_ID_ADSP_AFE_V); + if (ret < 0) + return ret; + + afe_api_version = ret; + + pr_debug("%s: mjor: %u, mnor: %u, brnch: %u, afe_api: %u\n", + __func__, build_major_version, build_minor_version, + build_branch_version, afe_api_version); + if ((build_major_version != AVS_BUILD_MAJOR_VERSION_V2) || + (build_minor_version != AVS_BUILD_MINOR_VERSION_V9) || + (build_branch_version != AVS_BUILD_BRANCH_VERSION_V3) || + (afe_api_version < AFE_API_VERSION_V8)) { + pr_err("%s: ext mclk not supported by AVS\n", __func__); + return -EINVAL; + } + + ret = afe_set_lpass_clk_cfg_ext_mclk(index, cfg, + clkinfo_per_port[idx].mclk_freq); + goto done; + } ret = afe_set_lpass_clk_cfg(index, cfg); + +done: if (ret) pr_err("%s: afe_set_lpass_clk_cfg_v2 failed %d\n", __func__, ret); @@ -9336,6 +9753,36 @@ int afe_set_lpass_clock_v2(u16 port_id, struct afe_clk_set *cfg) } EXPORT_SYMBOL(afe_set_lpass_clock_v2); +/** + * afe_set_mclk_src_cfg - Set audio interface MCLK source configuration + * + * @port_id: AFE port id + * @mclk_src_id: mclk id to represent internal or one of external MCLK + * @mclk_freq: frequency of the MCLK + * + * Returns 0 on success, appropriate error code otherwise + */ +int afe_set_mclk_src_cfg(u16 port_id, uint32_t mclk_src_id, uint32_t mclk_freq) +{ + int idx = 0; + + idx = afe_get_port_idx(port_id); + if (idx < 0) { + pr_err("%s: cannot get clock id for port id 0x%x\n", + __func__, port_id); + return -EINVAL; + } + + clkinfo_per_port[idx].mclk_src_id = mclk_src_id; + clkinfo_per_port[idx].mclk_freq = mclk_freq; + + pr_debug("%s: mclk src id 0x%x mclk_freq %d port id 0x%x\n", + __func__, mclk_src_id, mclk_freq, port_id); + + return 0; +} +EXPORT_SYMBOL(afe_set_mclk_src_cfg); + int afe_set_lpass_internal_digital_codec_clock(u16 port_id, struct afe_digital_clk_cfg *cfg) { @@ -9973,6 +10420,7 @@ static int afe_spv4_get_calib_data( struct param_hdr_v3 param_hdr; int port = SLIMBUS_4_TX; int ret = -EINVAL; + uint32_t th_vi_ca_state; if (!calib_resp) { pr_err("%s: Invalid params\n", __func__); @@ -9994,6 +10442,12 @@ static int afe_spv4_get_calib_data( __func__, port, param_hdr.param_id, ret); goto get_params_fail; } + th_vi_ca_state = this_afe.spv4_calib_data.res_cfg.th_vi_ca_state; + if (th_vi_ca_state < FBSP_INCORRECT_OP_MODE || + th_vi_ca_state > MAX_FBSP_STATE) { + pr_err("%s: invalid fbsp state %d\n", __func__, th_vi_ca_state); + goto get_params_fail; + } memcpy(&calib_resp->res_cfg, &this_afe.spv4_calib_data.res_cfg, sizeof(this_afe.calib_data.res_cfg)); pr_info("%s: state %s resistance %d %d\n", __func__, @@ -10012,6 +10466,7 @@ int afe_spk_prot_get_calib_data(struct afe_spkr_prot_get_vi_calib *calib_resp) struct param_hdr_v3 param_hdr; int port = SLIMBUS_4_TX; int ret = -EINVAL; + uint32_t th_vi_ca_state; if (!calib_resp) { pr_err("%s: Invalid params\n", __func__); @@ -10033,6 +10488,12 @@ int afe_spk_prot_get_calib_data(struct afe_spkr_prot_get_vi_calib *calib_resp) __func__, port, param_hdr.param_id, ret); goto get_params_fail; } + th_vi_ca_state = this_afe.calib_data.res_cfg.th_vi_ca_state; + if (th_vi_ca_state < FBSP_INCORRECT_OP_MODE || + th_vi_ca_state > MAX_FBSP_STATE) { + pr_err("%s: invalid fbsp state %d\n", __func__, th_vi_ca_state); + goto get_params_fail; + } memcpy(&calib_resp->res_cfg, &this_afe.calib_data.res_cfg, sizeof(this_afe.calib_data.res_cfg)); pr_info("%s: state %s resistance %d %d\n", __func__, diff --git a/techpack/audio/dsp/q6asm.c b/techpack/audio/dsp/q6asm.c index 75d8e6e77764809f9e37881bf0ddb50abfbcc57e..56b21a591f1d00d15d72d8c38933198f7758343f 100644 --- a/techpack/audio/dsp/q6asm.c +++ b/techpack/audio/dsp/q6asm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Author: Brian Swetland * * This software is licensed under the terms of the GNU General Public @@ -2297,6 +2298,15 @@ static int32_t q6asm_callback(struct apr_client_data *data, void *priv) config_debug_fs_read_cb(); + if (data->payload_size != (READDONE_IDX_SEQ_ID + 1) * sizeof(uint32_t)) { + pr_err("%s: payload size of %d is less than expected %ld.\n", + __func__, data->payload_size, + ((READDONE_IDX_SEQ_ID + 1) * sizeof(uint32_t))); + spin_unlock_irqrestore( + &(session[session_id].session_lock), + flags); + return -EINVAL; + } dev_vdbg(ac->dev, "%s: ReadDone: status=%d buff_add=0x%x act_size=%d offset=%d\n", __func__, payload[READDONE_IDX_STATUS], payload[READDONE_IDX_BUFADD_LSW], @@ -2403,7 +2413,16 @@ static int32_t q6asm_callback(struct apr_client_data *data, void *priv) __func__, data->payload_size); break; case ASM_SESSION_CMDRSP_GET_MTMX_STRTR_PARAMS_V2: - q6asm_process_mtmx_get_param_rsp(ac, (void *) payload); + payload_size = sizeof(struct asm_mtmx_strtr_get_params_cmdrsp); + if (data->payload_size < payload_size) { + pr_err("%s: insufficient payload size = %d\n", + __func__, data->payload_size); + spin_unlock_irqrestore( + &(session[session_id].session_lock), flags); + return -EINVAL; + } + q6asm_process_mtmx_get_param_rsp(ac, + (struct asm_mtmx_strtr_get_params_cmdrsp *) payload); break; case ASM_STREAM_PP_EVENT: case ASM_STREAM_CMD_ENCDEC_EVENTS: diff --git a/techpack/audio/dsp/q6core.c b/techpack/audio/dsp/q6core.c index 1e168e8ecc5fdfc30b17e6a465682a213363b403..426e02a7fddb504239529d81d6fae23cb7ab04a8 100644 --- a/techpack/audio/dsp/q6core.c +++ b/techpack/audio/dsp/q6core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -204,7 +205,7 @@ EXPORT_SYMBOL(q6core_send_uevent); static int parse_fwk_version_info(uint32_t *payload, uint16_t payload_size) { size_t ver_size; - int num_services; + uint16_t num_services; pr_debug("%s: Payload info num services %d\n", __func__, payload[4]); @@ -474,6 +475,14 @@ static int32_t aprv2_core_fn_q(struct apr_client_data *data, void *priv) case AVCS_CMD_RSP_LOAD_MODULES: pr_debug("%s: Received AVCS_CMD_RSP_LOAD_MODULES\n", __func__); + if (!rsp_payload) + return -EINVAL; + if (data->payload_size != ((sizeof(struct avcs_load_unload_modules_sec_payload) + * rsp_payload->num_modules) + sizeof(uint32_t))) { + pr_err("%s: payload size greater than expected size %d\n", + __func__,data->payload_size); + return -EINVAL; + } memcpy(rsp_payload, data->payload, data->payload_size); q6core_lcl.avcs_module_resp_received = 1; wake_up(&q6core_lcl.avcs_module_load_unload_wait); @@ -739,6 +748,44 @@ int q6core_get_avcs_api_version_per_service(uint32_t service_id) } EXPORT_SYMBOL(q6core_get_avcs_api_version_per_service); +/** + * q6core_get_avcs_avs_build_version_info - Get AVS build version information + * + * @build_major_version - pointer to build major version + * @build_minor_version - pointer to build minor version + * @build_branch_version - pointer to build branch version + * + * Returns 0 on success and error on failure + */ +int q6core_get_avcs_avs_build_version_info( + uint32_t *build_major_version, uint32_t *build_minor_version, + uint32_t *build_branch_version) +{ + + struct avcs_fwk_ver_info *cached_ver_info = NULL; + int ret = 0; + + if (!build_major_version || !build_minor_version || + !build_branch_version) + return -EINVAL; + + ret = q6core_get_avcs_fwk_version(); + if (ret < 0) + return ret; + + cached_ver_info = q6core_lcl.q6core_avcs_ver_info.ver_info; + + *build_major_version = + cached_ver_info->avcs_fwk_version.build_major_version; + *build_minor_version = + cached_ver_info->avcs_fwk_version.build_minor_version; + *build_branch_version = + cached_ver_info->avcs_fwk_version.build_branch_version; + + return ret; +} +EXPORT_SYMBOL(q6core_get_avcs_avs_build_version_info); + /** * core_set_license - * command to set license for module @@ -998,6 +1045,8 @@ int32_t q6core_avcs_load_unload_modules(struct avcs_load_unload_modules_payload return -ENOMEM; } + rsp_payload->num_modules = num_modules; + memcpy((uint8_t *)mod + sizeof(struct apr_hdr) + sizeof(struct avcs_load_unload_modules_meminfo), payload, payload_size); @@ -1052,6 +1101,7 @@ int32_t q6core_avcs_load_unload_modules(struct avcs_load_unload_modules_payload done: kfree(mod); kfree(rsp_payload); + rsp_payload = NULL; mutex_unlock(&(q6core_lcl.cmd_lock)); return ret; } diff --git a/techpack/audio/dsp/q6lsm.c b/techpack/audio/dsp/q6lsm.c index 857dad3f9c5dbc746efe414d592343517757027c..ce0b9e3f5b26f53862a49e4f3e0506f07ff0e09a 100644 --- a/techpack/audio/dsp/q6lsm.c +++ b/techpack/audio/dsp/q6lsm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2020, Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -229,12 +230,17 @@ static int q6lsm_callback(struct apr_client_data *data, void *priv) } if (client->param_size != param_size) { - pr_err("%s: response payload size %d mismatched with user requested %d\n", + pr_err("%s: response payload size %d mismatched with user requested %zu\n", __func__, param_size, client->param_size); ret = -EINVAL; goto done; } + if (!client->get_param_payload) { + pr_err("%s: invalid get_param_payload buffer ptr\n", __func__); + ret = -EINVAL; + goto done; + } memcpy((u8 *)client->get_param_payload, (u8 *)payload + payload_min_size_expected, param_size); done: @@ -472,6 +478,10 @@ static int q6lsm_apr_send_pkt(struct lsm_client *client, void *handle, } pr_debug("%s: enter wait %d\n", __func__, wait); + if (mmap_handle_p) { + pr_debug("%s: Invalid mmap_handle\n", __func__); + return -EINVAL; + } if (wait) mutex_lock(&lsm_common.apr_lock); if (mmap_p) { @@ -517,6 +527,7 @@ static int q6lsm_apr_send_pkt(struct lsm_client *client, void *handle, if (mmap_p && *mmap_p == 0) ret = -ENOMEM; + mmap_handle_p = NULL; pr_debug("%s: leave ret %d\n", __func__, ret); return ret; } @@ -2040,7 +2051,8 @@ static int q6lsm_mmapcallback(struct apr_client_data *data, void *priv) case LSM_SESSION_CMDRSP_SHARED_MEM_MAP_REGIONS: if (atomic_read(&client->cmd_state) == CMD_STATE_WAIT_RESP) { spin_lock_irqsave(&mmap_lock, flags); - *mmap_handle_p = command; + if (mmap_handle_p) + *mmap_handle_p = command; /* spin_unlock_irqrestore implies barrier */ spin_unlock_irqrestore(&mmap_lock, flags); atomic_set(&client->cmd_state, CMD_STATE_CLEARED); diff --git a/techpack/audio/dsp/q6voice.c b/techpack/audio/dsp/q6voice.c index 305d917d55ea3b85726b9e31389572d80aa06b07..62a1eca465d323c112545b4bbb547e131f940a29 100644 --- a/techpack/audio/dsp/q6voice.c +++ b/techpack/audio/dsp/q6voice.c @@ -2772,6 +2772,13 @@ static int voice_send_cvs_register_cal_cmd(struct voice_data *v) goto unlock; } + if (col_data->cal_data.size >= MAX_COL_INFO_SIZE) { + pr_err("%s: Invalid cal data size %ld!\n", + __func__, col_data->cal_data.size); + ret = -EINVAL; + goto unlock; + } + memcpy(&cvs_reg_cal_cmd.cvs_cal_data.column_info[0], (void *) &((struct audio_cal_info_voc_col *) col_data->cal_info)->data, diff --git a/techpack/audio/include/asoc/sdm660-common.h b/techpack/audio/include/asoc/sdm660-common.h index a8c815c330f1b57e7a52519b8099e083356fe96e..36abdb2a9543cafb513921c3e3b17c78f847e0ad 100644 --- a/techpack/audio/include/asoc/sdm660-common.h +++ b/techpack/audio/include/asoc/sdm660-common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2015-2019, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, 2020-2021, The Linux Foundation. All rights reserved. */ #ifndef __MSM_COMMON @@ -86,6 +86,8 @@ struct sdm660_codec { enum { INT_SND_CARD, + INT_DIG_SND_CARD, + INT_MAX_SND_CARD = INT_DIG_SND_CARD, EXT_SND_CARD_TASHA, EXT_SND_CARD_TAVIL, }; diff --git a/techpack/audio/include/dsp/apr_audio-v2.h b/techpack/audio/include/dsp/apr_audio-v2.h index 2450daf6347e721c636081d5710c7164a42a1087..eb3c844e86f57a544bef847e329d1f36dbb46dd7 100644 --- a/techpack/audio/include/dsp/apr_audio-v2.h +++ b/techpack/audio/include/dsp/apr_audio-v2.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ @@ -3990,6 +3990,7 @@ struct afe_param_id_device_hw_delay_cfg { } __packed; #define AFE_PARAM_ID_SET_TOPOLOGY 0x0001025A +#define AFE_PARAM_ID_DEREGISTER_TOPOLOGY 0x000102E8 #define AFE_API_VERSION_TOPOLOGY_V1 0x1 struct afe_param_id_set_topology_cfg { @@ -12223,6 +12224,27 @@ struct afe_clk_set { uint32_t enable; }; +#define AVS_BUILD_MAJOR_VERSION_V2 2 +#define AVS_BUILD_MINOR_VERSION_V9 9 +#define AVS_BUILD_BRANCH_VERSION_V3 3 + +#define AFE_PARAM_ID_CLOCK_SET_V2 0x000102E6 + +#define AFE_API_VERSION_CLOCK_SET_V2 0x1 + +struct afe_param_id_clock_set_v2_t { + uint32_t clk_set_minor_version; + uint32_t clk_id; + uint32_t clk_freq_in_hz; + uint16_t clk_attri; + uint16_t clk_root; + uint32_t enable; + uint32_t divider_2x; + uint32_t m; + uint32_t n; + uint32_t d; +}; + struct afe_clk_cfg { /* Minor version used for tracking the version of the I2S * configuration interface. @@ -12263,16 +12285,15 @@ struct afe_clk_cfg { #define AFE_MODULE_CLOCK_SET 0x0001028F #define AFE_PARAM_ID_CLOCK_SET 0x00010290 -struct afe_set_clk_drift { - /* - * Clock ID - * @values - * - 0x100 to 0x10E - * - 0x200 to 0x20C - * - 0x500 to 0x505 - */ - uint32_t clk_id; +#define CLK_SRC_NAME_MAX 32 + +enum { + CLK_SRC_INTEGRAL, + CLK_SRC_FRACT, + CLK_SRC_MAX +}; +struct afe_set_clk_drift { /* * Clock drift (in PPB) to be set. * @values @@ -12281,12 +12302,20 @@ struct afe_set_clk_drift { int32_t clk_drift; /* - * Clock rest. + * Clock reset. * @values * - 1 -- Reset PLL with the original frequency * - 0 -- Adjust the clock with the clk drift value */ uint32_t clk_reset; + /* + * Clock src name. + * @values + * - values to be set from machine driver + * - LPAPLL0 -- integral clk src + * - LPAPLL2 -- fractional clk src + */ + char clk_src_name[CLK_SRC_NAME_MAX]; } __packed; /* This param id is used to adjust audio interface PLL*/ diff --git a/techpack/audio/include/dsp/q6afe-v2.h b/techpack/audio/include/dsp/q6afe-v2.h index fbb4350e35b7280c8ef8ac1e41738c33e22ca24d..57d8c5986d378c644a4b158a8969272e25747e78 100644 --- a/techpack/audio/include/dsp/q6afe-v2.h +++ b/techpack/audio/include/dsp/q6afe-v2.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #ifndef __Q6AFE_V2_H__ #define __Q6AFE_V2_H__ @@ -45,8 +45,13 @@ #define AFE_API_VERSION_V4 4 /* for VAD enable */ #define AFE_API_VERSION_V6 6 +/* for external mclk dynamic switch */ +#define AFE_API_VERSION_V8 8 /* for Speaker Protection V4 */ #define AFE_API_VERSION_V9 9 +#define AFE_API_VERSION_V10 10 + +#define AFE_SAMPLING_RATE_8KHZ 8000 typedef int (*routing_cb)(int port); @@ -316,6 +321,24 @@ struct vad_config { u32 pre_roll; }; +enum afe_mclk_src_id { + MCLK_SRC_INT = 0x00, + MCLK_SRC_EXT_0 = 0x01, + MCLK_SRC_MAX, +}; + +enum afe_mclk_freq { + MCLK_FREQ_MIN = 0, + MCLK_FREQ_11P2896_MHZ = MCLK_FREQ_MIN, + MCLK_FREQ_12P288_MHZ, + MCLK_FREQ_16P384_MHZ, + MCLK_FREQ_22P5792_MHZ, + MCLK_FREQ_24P576_MHZ, + MCLK_FREQ_MAX, +}; + +#define Q6AFE_EXT_MCLK_FREQ_DEFAULT 0 + struct afe_audio_buffer { dma_addr_t phys; void *data; @@ -510,6 +533,22 @@ enum { AFE_LPASS_CORE_HW_VOTE_MAX }; +int afe_set_source_clk(u16 port_id, const char *clk_src); +void afe_set_clk_src_array(const char *clk_src[CLK_SRC_MAX]); +int afe_set_mclk_src_cfg(u16 port_id, uint32_t mclk_src_id, uint32_t mclk_freq); + +typedef int (*afe_enable_mclk_and_get_info_cb_func) (void *private_data, + uint32_t enable, uint32_t mclk_freq, + struct afe_param_id_clock_set_v2_t *dyn_mclk_cfg); + +int afe_register_ext_mclk_cb(afe_enable_mclk_and_get_info_cb_func fn1, + void *private_data); +void afe_unregister_ext_mclk_cb(void); + +#define AFE_LPASS_CORE_HW_BLOCK_ID_NONE 0 +#define AFE_LPASS_CORE_HW_BLOCK_ID_AVTIMER 2 +#define AFE_LPASS_CORE_HW_MACRO_BLOCK 3 + /* Handles audio-video timer (avtimer) and BTSC vote requests from clients. */ #define AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f4 diff --git a/techpack/audio/include/dsp/q6core.h b/techpack/audio/include/dsp/q6core.h index adfb83e861902033172937cc7116aff1b213531a..fae1420de685e1e6b8b15728986be6be3239254e 100644 --- a/techpack/audio/include/dsp/q6core.h +++ b/techpack/audio/include/dsp/q6core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #ifndef __Q6CORE_H__ @@ -428,4 +428,7 @@ int q6core_destroy_lpass_npa_client(uint32_t client_handle); int q6core_request_island_transition(uint32_t client_handle, uint32_t island_allow_mode); +int q6core_get_avcs_avs_build_version_info( + uint32_t *build_major_version, uint32_t *build_minor_version, + uint32_t *build_branch_version); #endif /* __Q6CORE_H__ */ diff --git a/techpack/audio/ipc/Android.mk b/techpack/audio/ipc/Android.mk index 99ffc3076a1cecc2a7bcb411919a6b554657bf07..6364ed7d8102a45aa524376cfa6cb1f2963bf8bc 100644 --- a/techpack/audio/ipc/Android.mk +++ b/techpack/audio/ipc/Android.mk @@ -35,9 +35,13 @@ ifeq ($(call is-board-platform,sdm660),true) AUDIO_SELECT := CONFIG_SND_SOC_SDM660=m endif +ifeq ($(call is-board-platform-in-list, msm8953 msm8937),true) +AUDIO_SELECT := CONFIG_SND_SOC_SDM450=m +endif + AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) diff --git a/techpack/audio/ipc/Kbuild b/techpack/audio/ipc/Kbuild index 755d6d8eacd5a9b05e2eac693d78824cf0026379..14c53d97279bbc9090c40f124685a2d75ca5174d 100644 --- a/techpack/audio/ipc/Kbuild +++ b/techpack/audio/ipc/Kbuild @@ -82,6 +82,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: @@ -190,6 +205,3 @@ apr_dlkm-y := $(APRV_GLINK) obj-$(CONFIG_WCD_DSP_GLINK) += wglink_dlkm.o wglink_dlkm-y := $(WDSP_GLINK) - -# inject some build related information -CDEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/soc/Android.mk b/techpack/audio/soc/Android.mk index d6a1203c1c755ef3018c0ca689e8bc0fb523e1c3..858be88c455b1353c1c2f87429cc7cc0cdd83dce 100644 --- a/techpack/audio/soc/Android.mk +++ b/techpack/audio/soc/Android.mk @@ -35,9 +35,13 @@ ifeq ($(call is-board-platform,sdm660),true) AUDIO_SELECT := CONFIG_SND_SOC_SDM660=m endif +ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) +AUDIO_SELECT := CONFIG_SND_SOC_SDM450=m +endif + AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) @@ -76,7 +80,7 @@ include $(DLKM_DIR)/AndroidKernelModule.mk endif endif ########################################################### -ifeq ($(call is-board-platform-in-list,$(MSMSTEPPE) $(TRINKET) kona sdm660), true) +ifeq ($(call is-board-platform-in-list,$(MSMSTEPPE) $(TRINKET) kona sdm660 msm8953 msm8937), true) ifneq ($(TARGET_BOARD_AUTO),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_pinctrl_wcd.ko diff --git a/techpack/audio/soc/Kbuild b/techpack/audio/soc/Kbuild index 4fedbddcf460e35da8e2a90b4904274d36361e6f..9beb8e839cc3b96d42e53ad2d79319be43489c74 100644 --- a/techpack/audio/soc/Kbuild +++ b/techpack/audio/soc/Kbuild @@ -81,6 +81,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: @@ -211,6 +226,3 @@ swr_ctrl_dlkm-y := $(SWR_CTRL_OBJS) obj-$(CONFIG_WCD_SPI_AC) += wcd_spi_acc_ctl_dlkm.o wcd_spi_acc_ctl_dlkm-y := $(WCD_SPI_ACC_CTL_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/soc/pinctrl-lpi-legacy.c b/techpack/audio/soc/pinctrl-lpi-legacy.c index 5bf64966d9ee8bc0bd6a6f9bd3d70dc4cd39b586..fb0e957dd3df521d5f23762604b606d0ee16953e 100644 --- a/techpack/audio/soc/pinctrl-lpi-legacy.c +++ b/techpack/audio/soc/pinctrl-lpi-legacy.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -95,6 +96,7 @@ struct lpi_gpio_state { char __iomem *base; struct clk *lpass_core_hw_vote; bool core_hw_vote_status; + struct mutex lpi_mutex; }; static const char *const lpi_gpio_groups[] = { @@ -120,12 +122,16 @@ static const char *const lpi_gpio_functions[] = { static int lpi_gpio_read(struct lpi_gpio_pad *pad, unsigned int addr) { int ret; + struct lpi_gpio_state *state = dev_get_drvdata(lpi_dev); + mutex_lock(&state->lpi_mutex); if (!lpi_dev_up) { pr_err_ratelimited("%s: ADSP is down due to SSR, return\n", __func__); + mutex_unlock(&state->lpi_mutex); return 0; } + pm_runtime_get_sync(lpi_dev); ret = ioread32(pad->base + pad->offset + addr); @@ -134,15 +140,20 @@ static int lpi_gpio_read(struct lpi_gpio_pad *pad, unsigned int addr) pm_runtime_mark_last_busy(lpi_dev); pm_runtime_put_autosuspend(lpi_dev); + mutex_unlock(&state->lpi_mutex); return ret; } static int lpi_gpio_write(struct lpi_gpio_pad *pad, unsigned int addr, unsigned int val) { + struct lpi_gpio_state *state = dev_get_drvdata(lpi_dev); + + mutex_lock(&state->lpi_mutex); if (!lpi_dev_up) { pr_err_ratelimited("%s: ADSP is down due to SSR, return\n", __func__); + mutex_unlock(&state->lpi_mutex); return 0; } pm_runtime_get_sync(lpi_dev); @@ -151,6 +162,7 @@ static int lpi_gpio_write(struct lpi_gpio_pad *pad, unsigned int addr, pm_runtime_mark_last_busy(lpi_dev); pm_runtime_put_autosuspend(lpi_dev); + mutex_unlock(&state->lpi_mutex); return 0; } @@ -213,12 +225,14 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, pad = pctldev->desc->pins[pin].drv_data; - pad->function = function; + if (pad != NULL) { + pad->function = function; - val = lpi_gpio_read(pad, LPI_GPIO_REG_VAL_CTL); - val &= ~(LPI_GPIO_REG_FUNCTION_MASK); - val |= pad->function << LPI_GPIO_REG_FUNCTION_SHIFT; - lpi_gpio_write(pad, LPI_GPIO_REG_VAL_CTL, val); + val = lpi_gpio_read(pad, LPI_GPIO_REG_VAL_CTL); + val &= ~(LPI_GPIO_REG_FUNCTION_MASK); + val |= pad->function << LPI_GPIO_REG_FUNCTION_SHIFT; + lpi_gpio_write(pad, LPI_GPIO_REG_VAL_CTL, val); + } return 0; } @@ -382,8 +396,10 @@ static int lpi_notifier_service_cb(struct notifier_block *this, unsigned long opcode, void *ptr) { static bool initial_boot = true; + struct lpi_gpio_state *state = dev_get_drvdata(lpi_dev); pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode); + mutex_lock(&state->lpi_mutex); switch (opcode) { case AUDIO_NOTIFIER_SERVICE_DOWN: @@ -403,6 +419,7 @@ static int lpi_notifier_service_cb(struct notifier_block *this, default: break; } + mutex_unlock(&state->lpi_mutex); return NOTIFY_OK; } @@ -643,6 +660,7 @@ static int lpi_pinctrl_probe(struct platform_device *pdev) pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); pm_runtime_enable(&pdev->dev); + mutex_init(&state->lpi_mutex); return 0; @@ -658,6 +676,7 @@ static int lpi_pinctrl_remove(struct platform_device *pdev) { struct lpi_gpio_state *state = platform_get_drvdata(pdev); + mutex_destroy(&state->lpi_mutex); pm_runtime_disable(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); diff --git a/techpack/audio/soc/swr-mstr-ctrl.c b/techpack/audio/soc/swr-mstr-ctrl.c index b3aa1019abd7902625311bd2f05f373383e432c0..9d36c1c43d406621c27598bce7c480a5fc6fb87c 100644 --- a/techpack/audio/soc/swr-mstr-ctrl.c +++ b/techpack/audio/soc/swr-mstr-ctrl.c @@ -833,6 +833,11 @@ static int swrm_cmd_fifo_rd_cmd(struct swr_mstr_ctrl *swrm, int *cmd_data, u32 val; u32 retry_attempt = 0; + if (!dev_addr) { + dev_err(swrm->dev, "%s: invalid slave dev num\n", __func__); + return -EINVAL; + } + mutex_lock(&swrm->iolock); val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr); if (swrm->read) { @@ -862,7 +867,6 @@ static int swrm_cmd_fifo_rd_cmd(struct swr_mstr_ctrl *swrm, int *cmd_data, /* wait 500 us before retry on fifo read failure */ usleep_range(500, 505); if (retry_attempt == (MAX_FIFO_RD_FAIL_RETRY - 1)) { - swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); swr_master_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); } retry_attempt++; @@ -888,6 +892,11 @@ static int swrm_cmd_fifo_wr_cmd(struct swr_mstr_ctrl *swrm, u8 cmd_data, u32 val; int ret = 0; + if (!dev_addr) { + dev_err(swrm->dev, "%s: invalid slave dev num\n", __func__); + return -EINVAL; + } + mutex_lock(&swrm->iolock); if (!cmd_id) val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data, @@ -2153,7 +2162,6 @@ static irqreturn_t swr_mstr_interrupt_v2(int irq, void *dev) dev_err(swrm->dev, "%s: SWR write FIFO overflow fifo status %x\n", __func__, value); - swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); break; case SWRM_INTERRUPT_STATUS_CMD_ERROR: value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS); @@ -2895,6 +2903,10 @@ static int swrm_probe(struct platform_device *pdev) dev_info(&pdev->dev, "%s: version specified in dtsi: 0x%x not match with HW read version 0x%x\n", __func__, swrm->version, swrm_hw_ver); + swrm->rd_fifo_depth = ((swr_master_read(swrm, SWRM_COMP_PARAMS) + & SWRM_COMP_PARAMS_RD_FIFO_DEPTH) >> 15); + swrm->wr_fifo_depth = ((swr_master_read(swrm, SWRM_COMP_PARAMS) + & SWRM_COMP_PARAMS_WR_FIFO_DEPTH) >> 10); ret = swrm_master_init(swrm); if (ret < 0) { dev_err(&pdev->dev, @@ -2911,11 +2923,6 @@ static int swrm_probe(struct platform_device *pdev) if (pdev->dev.of_node) of_register_swr_devices(&swrm->master); - swrm->rd_fifo_depth = ((swr_master_read(swrm, SWRM_COMP_PARAMS) - & SWRM_COMP_PARAMS_RD_FIFO_DEPTH) >> 15); - swrm->wr_fifo_depth = ((swr_master_read(swrm, SWRM_COMP_PARAMS) - & SWRM_COMP_PARAMS_WR_FIFO_DEPTH) >> 10); - #ifdef CONFIG_DEBUG_FS swrm->debugfs_swrm_dent = debugfs_create_dir(dev_name(&pdev->dev), 0); if (!IS_ERR(swrm->debugfs_swrm_dent)) { @@ -3181,6 +3188,7 @@ static int swrm_runtime_suspend(struct device *dev) struct swr_master *mstr = &swrm->master; struct swr_device *swr_dev; int current_state = 0; + struct irq_data *irq_data = NULL; trace_printk("%s: pm_runtime: suspend state: %d\n", __func__, swrm->state); @@ -3289,7 +3297,9 @@ static int swrm_runtime_suspend(struct device *dev) if (swrm->clk_stop_mode0_supp) { if (swrm->wake_irq > 0) { - enable_irq(swrm->wake_irq); + irq_data = irq_get_irq_data(swrm->wake_irq); + if (irq_data && irqd_irq_disabled(irq_data)) + enable_irq(swrm->wake_irq); } else if (swrm->ipc_wakeup) { msm_aud_evt_blocking_notifier_call_chain( SWR_WAKE_IRQ_REGISTER, (void *)swrm); diff --git a/techpack/camera-bengal/Makefile b/techpack/camera-bengal/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..2c8115903a54edfc510b84e6f2691b687ea10d00 --- /dev/null +++ b/techpack/camera-bengal/Makefile @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# auto-detect subdirs +ifeq ($(CONFIG_ARCH_BENGAL), y) +include $(srctree)/techpack/camera-bengal/config/bengalcamera.conf +endif + +ifeq ($(CONFIG_ARCH_KHAJE), y) +include $(srctree)/techpack/camera-bengal/config/khajecamera.conf +endif + +ifeq ($(CONFIG_ARCH_BENGAL), y) +LINUXINCLUDE += \ + -include $(srctree)/techpack/camera-bengal/config/bengalcameraconf.h +endif + +ifeq ($(CONFIG_ARCH_KHAJE), y) +LINUXINCLUDE += \ + -include $(srctree)/techpack/camera-bengal/config/khajecameraconf.h +endif + +ifdef CONFIG_SPECTRA_CAMERA_BENGAL +# Use USERINCLUDE when you must reference the UAPI directories only. +USERINCLUDE += \ + -I$(srctree)/techpack/camera-bengal/include/uapi + +# Use LINUXINCLUDE when you must reference the include/ directory. +# Needed to be compatible with the O= option +LINUXINCLUDE += \ + -I$(srctree)/techpack/camera-bengal/include/uapi \ + -I$(srctree)/techpack/camera-bengal/include +obj-y += drivers/ +endif diff --git a/techpack/camera-bengal/config/bengalcamera.conf b/techpack/camera-bengal/config/bengalcamera.conf new file mode 100644 index 0000000000000000000000000000000000000000..5cf8d37a139b2680a54a255c86fe8d76bc783a1d --- /dev/null +++ b/techpack/camera-bengal/config/bengalcamera.conf @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (c) 2019, The Linux Foundation. All rights reserved. + +export CONFIG_SPECTRA_CAMERA_BENGAL=y +export CONFIG_SPECTRA_CAMERA=y +export CONFIG_SPECTRA_CAMERA_OPE=y +export CONFIG_SPECTRA_CAMERA_TFE=y diff --git a/techpack/camera-bengal/config/bengalcameraconf.h b/techpack/camera-bengal/config/bengalcameraconf.h new file mode 100644 index 0000000000000000000000000000000000000000..6aff3a93624e7b2ac587f36cbbaa5bc57b905599 --- /dev/null +++ b/techpack/camera-bengal/config/bengalcameraconf.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#define CONFIG_SPECTRA_CAMERA_BENGAL 1 +#define CONFIG_SPECTRA_CAMERA 1 +#define CONFIG_SPECTRA_CAMERA_OPE 1 +#define CONFIG_SPECTRA_CAMERA_TFE 1 diff --git a/techpack/camera-bengal/config/khajecamera.conf b/techpack/camera-bengal/config/khajecamera.conf new file mode 100644 index 0000000000000000000000000000000000000000..0354fe1dee303856e44a477f675d2b8a04b79e56 --- /dev/null +++ b/techpack/camera-bengal/config/khajecamera.conf @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (c) 2021, The Linux Foundation. All rights reserved. + +export CONFIG_SPECTRA_CAMERA_BENGAL=y +export CONFIG_SPECTRA_CAMERA_OPE=y +export CONFIG_SPECTRA_CAMERA_TFE=y +export CONFIG_SPECTRA_CAMERA_SENSOR=y diff --git a/techpack/camera-bengal/config/khajecameraconf.h b/techpack/camera-bengal/config/khajecameraconf.h new file mode 100644 index 0000000000000000000000000000000000000000..dbe4ea40a59997011e1ab6380e010c52d234497b --- /dev/null +++ b/techpack/camera-bengal/config/khajecameraconf.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#define CONFIG_SPECTRA_CAMERA_BENGAL 1 +#define CONFIG_SPECTRA_CAMERA 1 +#define CONFIG_SPECTRA_CAMERA_OPE 1 +#define CONFIG_SPECTRA_CAMERA_TFE 1 diff --git a/techpack/camera-bengal/config/konacamera.conf b/techpack/camera-bengal/config/konacamera.conf new file mode 100644 index 0000000000000000000000000000000000000000..a50077b2eb62b53c794f025fd9b8bce061fb1511 --- /dev/null +++ b/techpack/camera-bengal/config/konacamera.conf @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (c) 2019, The Linux Foundation. All rights reserved. + +export CONFIG_SPECTRA_CAMERA=y +export CONFIG_SPECTRA_CAMERA_CUST=y +export CONFIG_SPECTRA_CAMERA_FD=y +export CONFIG_SPECTRA_CAMERA_ICP=y +export CONFIG_SPECTRA_CAMERA_JPEG=y +export CONFIG_SPECTRA_CAMERA_IFE=y +export CONFIG_SPECTRA_CAMERA_LRME=y diff --git a/techpack/camera-bengal/config/konacameraconf.h b/techpack/camera-bengal/config/konacameraconf.h new file mode 100644 index 0000000000000000000000000000000000000000..412dfa5d83805898b206d2b45f72e39d251a3688 --- /dev/null +++ b/techpack/camera-bengal/config/konacameraconf.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#define CONFIG_SPECTRA_CAMERA 1 +#define CONFIG_SPECTRA_CAMERA_CUST 1 +#define CONFIG_SPECTRA_CAMERA_FD 1 +#define CONFIG_SPECTRA_CAMERA_ICP 1 +#define CONFIG_SPECTRA_CAMERA_JPEG 1 +#define CONFIG_SPECTRA_CAMERA_IFE 1 +#define CONFIG_SPECTRA_CAMERA_LRME 1 diff --git a/techpack/camera-bengal/config/litocamera.conf b/techpack/camera-bengal/config/litocamera.conf new file mode 100644 index 0000000000000000000000000000000000000000..dc68ff8bba86e3a6814c9ff96cc2693cc55d25ff --- /dev/null +++ b/techpack/camera-bengal/config/litocamera.conf @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (c) 2019, The Linux Foundation. All rights reserved. + +export CONFIG_SPECTRA_CAMERA=y +export CONFIG_SPECTRA_CAMERA_FD=y +export CONFIG_SPECTRA_CAMERA_ICP=y +export CONFIG_SPECTRA_CAMERA_JPEG=y +export CONFIG_SPECTRA_CAMERA_IFE=y +export CONFIG_SPECTRA_CAMERA_LRME=y diff --git a/techpack/camera-bengal/config/litocameraconf.h b/techpack/camera-bengal/config/litocameraconf.h new file mode 100644 index 0000000000000000000000000000000000000000..412ff016195c801897f9074774984c9e97076d06 --- /dev/null +++ b/techpack/camera-bengal/config/litocameraconf.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#define CONFIG_SPECTRA_CAMERA 1 +#define CONFIG_SPECTRA_CAMERA_FD 1 +#define CONFIG_SPECTRA_CAMERA_ICP 1 +#define CONFIG_SPECTRA_CAMERA_JPEG 1 +#define CONFIG_SPECTRA_CAMERA_IFE 1 +#define CONFIG_SPECTRA_CAMERA_LRME 1 diff --git a/techpack/camera-bengal/drivers/Makefile b/techpack/camera-bengal/drivers/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..0004fce1ef9ea8f9b7e88a5ff4a0d3c6cbb42b60 --- /dev/null +++ b/techpack/camera-bengal/drivers/Makefile @@ -0,0 +1,15 @@ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_req_mgr/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_utils/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_core/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_sync/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_smmu/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_cpas/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_cdm/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_isp/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_module/ +obj-$(CONFIG_SPECTRA_CAMERA_ICP) += cam_icp/ +obj-$(CONFIG_SPECTRA_CAMERA_JPEG) += cam_jpeg/ +obj-$(CONFIG_SPECTRA_CAMERA_FD) += cam_fd/ +obj-$(CONFIG_SPECTRA_CAMERA_LRME) += cam_lrme/ +obj-$(CONFIG_SPECTRA_CAMERA_CUST) += cam_cust/ +obj-$(CONFIG_SPECTRA_CAMERA_OPE) += cam_ope/ \ No newline at end of file diff --git a/techpack/camera-bengal/drivers/cam_cdm/Makefile b/techpack/camera-bengal/drivers/cam_cdm/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..5b44602c29ccddc281c9e7336685669c98596f07 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_cdm_soc.o cam_cdm_util.o cam_cdm_intf.o\ + cam_cdm_core_common.o cam_cdm_virtual_core.o \ + cam_cdm_hw_core.o diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm.h b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm.h new file mode 100644 index 0000000000000000000000000000000000000000..8c8e6a4bd2d6a9c1c971e00c2547f66ebadc46fd --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm.h @@ -0,0 +1,566 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CDM_H_ +#define _CAM_CDM_H_ + +#include +#include +#include +#include +#include +#include +#include + +#include "cam_cdm_intf_api.h" +#include "cam_soc_util.h" +#include "cam_cpas_api.h" +#include "cam_hw_intf.h" +#include "cam_hw.h" +#include "cam_debug_util.h" + +#define CAM_MAX_SW_CDM_VERSION_SUPPORTED 1 +#define CAM_SW_CDM_INDEX 0 +#define CAM_CDM_INFLIGHT_WORKS 5 +#define CAM_CDM_HW_RESET_TIMEOUT 300 + +/* + * Macros to get prepare and get information + * from client CDM handles. + */ + +#define CAM_CDM_HW_ID_MASK 0xF +#define CAM_CDM_HW_ID_SHIFT 0x10 + +#define CAM_CDM_CLIENTS_ID_MASK 0xFF + +#define CAM_CDM_BL_FIFO_ID_MASK 0xF +#define CAM_CDM_BL_FIFO_ID_SHIFT 0x8 + +#define CAM_CDM_GET_HW_IDX(x) (((x) >> CAM_CDM_HW_ID_SHIFT) & \ + CAM_CDM_HW_ID_MASK) + +#define CAM_CDM_GET_BLFIFO_IDX(x) (((x) >> CAM_CDM_BL_FIFO_ID_SHIFT) & \ + CAM_CDM_BL_FIFO_ID_MASK) + +#define CAM_CDM_CREATE_CLIENT_HANDLE(hw_idx, priority, client_idx) \ + ((((hw_idx) & CAM_CDM_HW_ID_MASK) << CAM_CDM_HW_ID_SHIFT) | \ + (((priority) & CAM_CDM_BL_FIFO_ID_MASK) << CAM_CDM_BL_FIFO_ID_SHIFT)| \ + ((client_idx) & CAM_CDM_CLIENTS_ID_MASK)) +#define CAM_CDM_GET_CLIENT_IDX(x) ((x) & CAM_CDM_CLIENTS_ID_MASK) +#define CAM_PER_CDM_MAX_REGISTERED_CLIENTS (CAM_CDM_CLIENTS_ID_MASK + 1) +#define CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM (CAM_CDM_HW_ID_MASK + 1) + +/* Number of FIFO supported on CDM */ +#define CAM_CDM_NUM_BL_FIFO 0x4 + +/* Max number of register set for different CDM */ +#define CAM_CDM_BL_FIFO_REG_NUM 0x4 +#define CAM_CDM_BL_FIFO_IRQ_REG_NUM 0x4 +#define CAM_CDM_BL_FIFO_PENDING_REQ_REG_NUM 0x2 +#define CAM_CDM_SCRATCH_REG_NUM 0xc +#define CAM_CDM_COMP_WAIT_STATUS_REG_NUM 0x2 +#define CAM_CDM_PERF_MON_REG_NUM 0x2 + +/* BL_FIFO configurations*/ +#define CAM_CDM_BL_FIFO_LENGTH_MAX_DEFAULT 0x40 +#define CAM_CDM_BL_FIFO_LENGTH_CFG_SHIFT 0x10 +#define CAM_CDM_BL_FIFO_FLUSH_SHIFT 0x3 + +#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX 0x00 +#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX_DIV2 0x01 +#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX_DIV4 0x10 +#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX_DIV8 0x11 + +/* CDM core status bitmap */ +#define CAM_CDM_HW_INIT_STATUS 0x0 +#define CAM_CDM_FIFO_0_BLDONE_STATUS 0x0 +#define CAM_CDM_FIFO_1_BLDONE_STATUS 0x1 +#define CAM_CDM_FIFO_2_BLDONE_STATUS 0x2 +#define CAM_CDM_FIFO_3_BLDONE_STATUS 0x3 +#define CAM_CDM_RESET_HW_STATUS 0x4 +#define CAM_CDM_ERROR_HW_STATUS 0x5 +#define CAM_CDM_FLUSH_HW_STATUS 0x6 +#define CAM_CDM_RESET_ERR_STATUS 0x7 + +/* Curent BL command masks and shifts */ +#define CAM_CDM_CURRENT_BL_LEN 0xFFFFF +#define CAM_CDM_CURRENT_BL_ARB 0x100000 +#define CAM_CDM_CURRENT_BL_FIFO 0xC00000 +#define CAM_CDM_CURRENT_BL_TAG 0xFF000000 + +#define CAM_CDM_CURRENT_BL_ARB_SHIFT 0x14 +#define CAM_CDM_CURRENT_BL_FIFO_SHIFT 0x16 +#define CAM_CDM_CURRENT_BL_TAG_SHIFT 0x18 + +/* IRQ bit-masks */ +#define CAM_CDM_IRQ_STATUS_RST_DONE_MASK 0x1 +#define CAM_CDM_IRQ_STATUS_INLINE_IRQ_MASK 0x2 +#define CAM_CDM_IRQ_STATUS_BL_DONE_MASK 0x4 +#define CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK 0x10000 +#define CAM_CDM_IRQ_STATUS_ERROR_OVER_FLOW_MASK 0x20000 +#define CAM_CDM_IRQ_STATUS_ERROR_AHB_BUS_MASK 0x40000 +#define CAM_CDM_IRQ_STATUS_USR_DATA_MASK 0xFF + +#define CAM_CDM_IRQ_STATUS_ERRORS \ + (CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK | \ + CAM_CDM_IRQ_STATUS_ERROR_OVER_FLOW_MASK | \ + CAM_CDM_IRQ_STATUS_ERROR_AHB_BUS_MASK) + +/* Structure to store hw version info */ +struct cam_version_reg { + uint32_t hw_version; +}; + +/** + * struct cam_cdm_irq_regs - CDM IRQ registers + * + * @irq_mask: register offset for irq_mask + * @irq_clear: register offset for irq_clear + * @irq_clear_cmd: register offset to initiate irq clear + * @irq_set: register offset to set irq + * @irq_set_cmd: register offset to issue set_irq from irq_set + * @irq_status: register offset to look which irq is received + */ +struct cam_cdm_irq_regs { + uint32_t irq_mask; + uint32_t irq_clear; + uint32_t irq_clear_cmd; + uint32_t irq_set; + uint32_t irq_set_cmd; + uint32_t irq_status; +}; + +/** + * struct cam_cdm_bl_fifo_regs - BL_FIFO registers + * + * @bl_fifo_base: register offset to write bl_cmd base address + * @bl_fifo_len: register offset to write bl_cmd length + * @bl_fifo_store: register offset to commit the BL cmd + * @bl_fifo_cfg: register offset to config BL_FIFO depth, etc. + */ +struct cam_cdm_bl_fifo_regs { + uint32_t bl_fifo_base; + uint32_t bl_fifo_len; + uint32_t bl_fifo_store; + uint32_t bl_fifo_cfg; +}; + +/** + * struct cam_cdm_bl_pending_req_reg_params - BL_FIFO pending registers + * + * @rb_offset: register offset pending bl request in BL_FIFO + * @rb_mask: mask to get number of pending BLs in BL_FIFO + * @rb_num_fifo: number of BL_FIFO's information in the register + * @rb_next_fifo_shift: shift to get next fifo's pending BLs. + */ +struct cam_cdm_bl_pending_req_reg_params { + uint32_t rb_offset; + uint32_t rb_mask; + uint32_t rb_num_fifo; + uint32_t rb_next_fifo_shift; +}; + +/** + * struct cam_cdm_scratch_reg - scratch register + * + * @scratch_reg: offset of scratch register + */ +struct cam_cdm_scratch_reg { + uint32_t scratch_reg; +}; + +/* struct cam_cdm_perf_mon_regs - perf_mon registers */ +struct cam_cdm_perf_mon_regs { + uint32_t perf_mon_ctrl; + uint32_t perf_mon_0; + uint32_t perf_mon_1; + uint32_t perf_mon_2; +}; + +/** + * struct cam_cdm_perf_mon_regs - perf mon counter's registers + * + * @count_cfg_0: register offset to configure perf measures + * @always_count_val: register offset for always count value + * @busy_count_val: register offset to get busy count + * @stall_axi_count_val: register offset to get axi stall counts + * @count_status: register offset to know if count status finished + * for stall, busy and always. + */ +struct cam_cdm_perf_regs { + uint32_t count_cfg_0; + uint32_t always_count_val; + uint32_t busy_count_val; + uint32_t stall_axi_count_val; + uint32_t count_status; +}; + +/** + * struct cam_cdm_icl_data_regs - CDM icl data registers + * + * @icl_last_data_0: register offset to log last known good command + * @icl_last_data_1: register offset to log last known good command 1 + * @icl_last_data_2: register offset to log last known good command 2 + * @icl_inv_data: register offset to log CDM cmd that triggered + * invalid command. + */ +struct cam_cdm_icl_data_regs { + uint32_t icl_last_data_0; + uint32_t icl_last_data_1; + uint32_t icl_last_data_2; + uint32_t icl_inv_data; +}; + +/** + * struct cam_cdm_icl_misc_regs - CDM icl misc registers + * + * @icl_inv_bl_addr: register offset to give address of bl_cmd that + * gave invalid command + * @icl_status: register offset for context that gave good BL + * command and invalid command. + */ +struct cam_cdm_icl_misc_regs { + uint32_t icl_inv_bl_addr; + uint32_t icl_status; +}; + +/** + * struct cam_cdm_icl_regs - CDM icl registers + * + * @data_regs: structure with registers of all cdm good and invalid + * BL command information. + * @misc_regs: structure with registers for invalid command address + * and context + */ +struct cam_cdm_icl_regs { + struct cam_cdm_icl_data_regs *data_regs; + struct cam_cdm_icl_misc_regs *misc_regs; +}; + +/** + * struct cam_cdm_comp_wait_status - BL_FIFO comp_event status register + * + * @comp_wait_status: register offset to give information on whether the + * CDM is waiting for an event from another module + */ +struct cam_cdm_comp_wait_status { + uint32_t comp_wait_status; +}; + +/** + * struct cam_cdm_common_reg_data - structure for register data + * + * @num_bl_fifo: number of FIFO are there in CDM + * @num_bl_fifo_irq: number of FIFO irqs in CDM + * @num_bl_pending_req_reg: number of pending_requests register in CDM + * @num_scratch_reg: number of scratch registers in CDM + */ +struct cam_cdm_common_reg_data { + uint32_t num_bl_fifo; + uint32_t num_bl_fifo_irq; + uint32_t num_bl_pending_req_reg; + uint32_t num_scratch_reg; +}; + +/** + * struct cam_cdm_common_regs - common structure to get common registers + * of CDM + * + * @cdm_hw_version: offset to read cdm_hw_version + * @cam_version: offset to read the camera Titan architecture version + * @rst_cmd: offset to reset the CDM + * @cgc_cfg: offset to configure CDM CGC logic + * @core_cfg: offset to configure CDM core with ARB_SEL, implicit + * wait, etc. + * @core_en: offset to pause/enable CDM + * @fe_cfg: offset to configure CDM fetch engine + * @irq_context_status offset to read back irq context status + * @bl_fifo_rb: offset to set BL_FIFO read back + * @bl_fifo_base_rb: offset to read back base address on offset set by + * bl_fifo_rb + * @bl_fifo_len_rb: offset to read back base len and tag on offset set by + * bl_fifo_rb + * @usr_data: offset to read user data from GEN_IRQ commands + * @wait_status: offset to read status for last WAIT command + * @last_ahb_addr: offset to read back last AHB address generated by CDM + * @last_ahb_data: offset to read back last AHB data generated by CDM + * @core_debug: offset to configure CDM debug bus and debug features + * @last_ahb_err_addr: offset to read back last AHB Error address generated + * by CDM + * @last_ahb_err_data: offset to read back last AHB Error data generated + * by CDM + * @current_bl_base: offset to read back current command buffer BASE address + * value out of BL_FIFO + * @current_bl_len: offset to read back current command buffer len, TAG, + * context ID ARB value out of BL_FIFO + * @current_used_ahb_base: offset to read back current base address used by + * CDM to access camera register + * @debug_status: offset to read back current CDM status + * @bus_misr_cfg0: offset to enable bus MISR and configure sampling mode + * @bus_misr_cfg1: offset to select from one of the six MISR's for reading + * signature value + * @bus_misr_rd_val: offset to read MISR signature + * @pending_req: registers to read pending request in FIFO + * @comp_wait: registers to read comp_event CDM is waiting for + * @perf_mon: registers to read perf_mon information + * @scratch: registers to read scratch register value + * @perf_reg: registers to read performance counters value + * @icl_reg: registers to read information related to good + * and invalid commands in FIFO + * @spare: spare register + * + */ +struct cam_cdm_common_regs { + uint32_t cdm_hw_version; + const struct cam_version_reg *cam_version; + uint32_t rst_cmd; + uint32_t cgc_cfg; + uint32_t core_cfg; + uint32_t core_en; + uint32_t fe_cfg; + uint32_t irq_context_status; + uint32_t bl_fifo_rb; + uint32_t bl_fifo_base_rb; + uint32_t bl_fifo_len_rb; + uint32_t usr_data; + uint32_t wait_status; + uint32_t last_ahb_addr; + uint32_t last_ahb_data; + uint32_t core_debug; + uint32_t last_ahb_err_addr; + uint32_t last_ahb_err_data; + uint32_t current_bl_base; + uint32_t current_bl_len; + uint32_t current_used_ahb_base; + uint32_t debug_status; + uint32_t bus_misr_cfg0; + uint32_t bus_misr_cfg1; + uint32_t bus_misr_rd_val; + const struct cam_cdm_bl_pending_req_reg_params + *pending_req[CAM_CDM_BL_FIFO_PENDING_REQ_REG_NUM]; + const struct cam_cdm_comp_wait_status + *comp_wait[CAM_CDM_COMP_WAIT_STATUS_REG_NUM]; + const struct cam_cdm_perf_mon_regs + *perf_mon[CAM_CDM_PERF_MON_REG_NUM]; + const struct cam_cdm_scratch_reg + *scratch[CAM_CDM_SCRATCH_REG_NUM]; + const struct cam_cdm_perf_regs *perf_reg; + const struct cam_cdm_icl_regs *icl_reg; + uint32_t spare; +}; + +/** + * struct cam_cdm_hw_reg_offset - BL_FIFO comp_event status register + * + * @cmn_reg: pointer to structure to get common registers of a CDM + * @bl_fifo_reg: pointer to structure to get BL_FIFO registers of a CDM + * @irq_reg: pointer to structure to get IRQ registers of a CDM + * @reg_data: pointer to structure to reg_data related to CDM + * registers + */ +struct cam_cdm_hw_reg_offset { + const struct cam_cdm_common_regs *cmn_reg; + const struct cam_cdm_bl_fifo_regs *bl_fifo_reg[CAM_CDM_BL_FIFO_REG_NUM]; + const struct cam_cdm_irq_regs *irq_reg[CAM_CDM_BL_FIFO_IRQ_REG_NUM]; + const struct cam_cdm_common_reg_data *reg_data; +}; + +/* enum cam_cdm_hw_process_intf_cmd - interface commands.*/ +enum cam_cdm_hw_process_intf_cmd { + CAM_CDM_HW_INTF_CMD_ACQUIRE, + CAM_CDM_HW_INTF_CMD_RELEASE, + CAM_CDM_HW_INTF_CMD_SUBMIT_BL, + CAM_CDM_HW_INTF_CMD_RESET_HW, + CAM_CDM_HW_INTF_CMD_FLUSH_HW, + CAM_CDM_HW_INTF_CMD_HANDLE_ERROR, + CAM_CDM_HW_INTF_CMD_HANG_DETECT, + CAM_CDM_HW_INTF_DUMP_DBG_REGS, + CAM_CDM_HW_INTF_CMD_INVALID, +}; + +/* enum cam_cdm_flags - Bit fields for CDM flags used */ +enum cam_cdm_flags { + CAM_CDM_FLAG_SHARED_CDM, + CAM_CDM_FLAG_PRIVATE_CDM, +}; + +/* enum cam_cdm_type - Enum for possible CAM CDM types */ +enum cam_cdm_type { + CAM_VIRTUAL_CDM, + CAM_HW_CDM, +}; + +/* enum cam_cdm_mem_base_index - Enum for possible CAM CDM types */ +enum cam_cdm_mem_base_index { + CAM_HW_CDM_BASE_INDEX, + CAM_HW_CDM_MAX_INDEX = CAM_SOC_MAX_BLOCK, +}; + +/* enum cam_cdm_bl_cb_type - Enum for possible CAM CDM cb request types */ +enum cam_cdm_bl_cb_type { + CAM_HW_CDM_BL_CB_CLIENT = 1, + CAM_HW_CDM_BL_CB_INTERNAL, +}; + +/* enum cam_cdm_arbitration - Enum type of arbitration */ +enum cam_cdm_arbitration { + CAM_CDM_ARBITRATION_NONE, + CAM_CDM_ARBITRATION_ROUND_ROBIN, + CAM_CDM_ARBITRATION_PRIORITY_BASED, + CAM_CDM_ARBITRATION_MAX, +}; + +enum cam_cdm_hw_version { + CAM_CDM_VERSION = 0, + CAM_CDM_VERSION_1_0 = 0x10000000, + CAM_CDM_VERSION_1_1 = 0x10010000, + CAM_CDM_VERSION_1_2 = 0x10020000, + CAM_CDM_VERSION_2_0 = 0x20000000, + CAM_CDM_VERSION_2_1 = 0x20010000, + CAM_CDM_VERSION_MAX, +}; + +/* struct cam_cdm_client - struct for cdm clients data.*/ +struct cam_cdm_client { + struct cam_cdm_acquire_data data; + void __iomem *changebase_addr; + uint32_t stream_on; + uint32_t refcount; + struct mutex lock; + uint32_t handle; +}; + +/* struct cam_cdm_work_payload - struct for cdm work payload data.*/ +struct cam_cdm_work_payload { + struct cam_hw_info *hw; + uint32_t irq_status; + uint32_t irq_data; + int fifo_idx; + ktime_t workq_scheduled_ts; + struct work_struct work; +}; + +/* struct cam_cdm_bl_cb_request_entry - callback entry for work to process.*/ +struct cam_cdm_bl_cb_request_entry { + uint8_t bl_tag; + enum cam_cdm_bl_cb_type request_type; + uint32_t client_hdl; + void *userdata; + uint32_t cookie; + struct list_head entry; +}; + +/* struct cam_cdm_hw_intf_cmd_submit_bl - cdm interface submit command.*/ +struct cam_cdm_hw_intf_cmd_submit_bl { + uint32_t handle; + struct cam_cdm_bl_request *data; +}; + +/* struct cam_cdm_hw_mem - CDM hw memory struct */ +struct cam_cdm_hw_mem { + int32_t handle; + uint32_t vaddr; + uintptr_t kmdvaddr; + size_t size; +}; + +/* struct cam_cdm_bl_fifo - CDM hw memory struct */ +struct cam_cdm_bl_fifo { + struct completion bl_complete; + struct workqueue_struct *work_queue; + struct list_head bl_request_list; + struct mutex fifo_lock; + uint8_t bl_tag; + uint32_t bl_depth; + uint8_t last_bl_tag_done; + atomic_t work_record; +}; + +/** + * struct cam_cdm - CDM hw device struct + * + * @index: index of CDM hardware + * @name: cdm_name + * @id: enum for possible CDM hardwares + * @flags: enum to tell if CDM is private of shared + * @reset_complete: completion event to make CDM wait for reset + * @work_queue: workqueue to schedule work for virtual CDM + * @bl_request_list: bl_request list for submitted commands in + * virtual CDM + * @version: CDM version with major, minor, incr and reserved + * @hw_version: CDM version as read from the cdm_version register + * @hw_family_version: version of hw family the CDM belongs to + * @iommu_hdl: CDM iommu handle + * @offsets: pointer to structure of CDM registers + * @ops: CDM ops for generating cdm commands + * @clients: CDM clients array currently active on CDM + * @bl_fifo: structure with per fifo related attributes + * @cdm_status: bitfield with bits assigned for different cdm status + * @bl_tag: slot value at which the next bl cmd will be written + * in case of virtual CDM + * @gen_irq: memory region in which gen_irq command will be written + * @cpas_handle: handle for cpas driver + * @arbitration: type of arbitration to be used for the CDM + * @rst_done_cnt: CMD reset done count + */ +struct cam_cdm { + uint32_t index; + char name[128]; + enum cam_cdm_id id; + enum cam_cdm_flags flags; + struct completion reset_complete; + struct workqueue_struct *work_queue; + struct list_head bl_request_list; + struct cam_hw_version version; + uint32_t hw_version; + uint32_t hw_family_version; + struct cam_iommu_handle iommu_hdl; + struct cam_cdm_hw_reg_offset *offsets; + struct cam_cdm_utils_ops *ops; + struct cam_cdm_client *clients[CAM_PER_CDM_MAX_REGISTERED_CLIENTS]; + struct cam_cdm_bl_fifo bl_fifo[CAM_CDM_BL_FIFO_MAX]; + unsigned long cdm_status; + uint8_t bl_tag; + struct cam_cdm_hw_mem gen_irq[CAM_CDM_BL_FIFO_MAX]; + uint32_t cpas_handle; + enum cam_cdm_arbitration arbitration; + uint32_t rst_done_cnt; +}; + +/* struct cam_cdm_private_dt_data - CDM hw custom dt data */ +struct cam_cdm_private_dt_data { + bool dt_cdm_shared; + uint32_t dt_num_supported_clients; + const char *dt_cdm_client_name[CAM_PER_CDM_MAX_REGISTERED_CLIENTS]; + bool config_fifo; + uint32_t fifo_depth[CAM_CDM_BL_FIFO_MAX]; +}; + +/* struct cam_cdm_intf_devices - CDM mgr interface devices */ +struct cam_cdm_intf_devices { + struct mutex lock; + uint32_t refcount; + struct cam_hw_intf *device; + struct cam_cdm_private_dt_data *data; +}; + +/* struct cam_cdm_intf_mgr - CDM mgr interface device struct */ +struct cam_cdm_intf_mgr { + bool probe_done; + struct cam_cdm_intf_devices nodes[CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM]; + uint32_t cdm_count; + uint32_t dt_supported_hw_cdm; + int32_t refcount; +}; + +int cam_cdm_intf_register_hw_cdm(struct cam_hw_intf *hw, + struct cam_cdm_private_dt_data *data, enum cam_cdm_type type, + uint32_t *index); +int cam_cdm_intf_deregister_hw_cdm(struct cam_hw_intf *hw, + struct cam_cdm_private_dt_data *data, enum cam_cdm_type type, + uint32_t index); + +#endif /* _CAM_CDM_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_core_common.c b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_core_common.c new file mode 100644 index 0000000000000000000000000000000000000000..7d5f21af9f694835a7304c2ea9fd0cfd1a931735 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_core_common.c @@ -0,0 +1,843 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "cam_soc_util.h" +#include "cam_smmu_api.h" +#include "cam_io_util.h" +#include "cam_cdm_intf_api.h" +#include "cam_cdm.h" +#include "cam_cdm_soc.h" +#include "cam_cdm_core_common.h" + +static void cam_cdm_get_client_refcount(struct cam_cdm_client *client) +{ + mutex_lock(&client->lock); + CAM_DBG(CAM_CDM, "CDM client get refcount=%d", + client->refcount); + client->refcount++; + mutex_unlock(&client->lock); +} + +static void cam_cdm_put_client_refcount(struct cam_cdm_client *client) +{ + mutex_lock(&client->lock); + CAM_DBG(CAM_CDM, "CDM client put refcount=%d", + client->refcount); + if (client->refcount > 0) { + client->refcount--; + } else { + CAM_ERR(CAM_CDM, "Refcount put when zero"); + WARN_ON(1); + } + mutex_unlock(&client->lock); +} + +bool cam_cdm_set_cam_hw_version( + uint32_t ver, struct cam_hw_version *cam_version) +{ + switch (ver) { + case CAM_CDM100_VERSION: + case CAM_CDM110_VERSION: + case CAM_CDM120_VERSION: + case CAM_CDM200_VERSION: + case CAM_CDM210_VERSION: + cam_version->major = (ver & 0xF0000000); + cam_version->minor = (ver & 0xFFF0000); + cam_version->incr = (ver & 0xFFFF); + cam_version->reserved = 0; + return true; + default: + CAM_ERR(CAM_CDM, "CDM Version=%x not supported in util", ver); + break; + } + return false; +} + +bool cam_cdm_cpas_cb(uint32_t client_handle, void *userdata, + struct cam_cpas_irq_data *irq_data) +{ + if (!irq_data) + return false; + + CAM_DBG(CAM_CDM, "CPAS error callback type=%d", irq_data->irq_type); + + return false; +} + +struct cam_cdm_utils_ops *cam_cdm_get_ops( + uint32_t ver, struct cam_hw_version *cam_version, bool by_cam_version) +{ + if (by_cam_version == false) { + switch (ver) { + case CAM_CDM100_VERSION: + case CAM_CDM110_VERSION: + case CAM_CDM120_VERSION: + case CAM_CDM200_VERSION: + case CAM_CDM210_VERSION: + return &CDM170_ops; + default: + CAM_ERR(CAM_CDM, "CDM Version=%x not supported in util", + ver); + } + } else if (cam_version) { + if (((cam_version->major == 1) && + (cam_version->minor == 0) && + (cam_version->incr == 0)) || + ((cam_version->major == 1) && + (cam_version->minor == 1) && + (cam_version->incr == 0)) || + ((cam_version->major == 1) && + (cam_version->minor == 2) && + (cam_version->incr == 0))) { + + CAM_DBG(CAM_CDM, + "cam_hw_version=%x:%x:%x supported", + cam_version->major, cam_version->minor, + cam_version->incr); + return &CDM170_ops; + } + + CAM_ERR(CAM_CDM, "cam_hw_version=%x:%x:%x not supported", + cam_version->major, cam_version->minor, + cam_version->incr); + } + + return NULL; +} + +struct cam_cdm_bl_cb_request_entry *cam_cdm_find_request_by_bl_tag( + uint32_t tag, struct list_head *bl_list) +{ + struct cam_cdm_bl_cb_request_entry *node; + + list_for_each_entry(node, bl_list, entry) { + if (node->bl_tag == tag) + return node; + } + CAM_ERR(CAM_CDM, "Could not find the bl request for tag=%x", tag); + + return NULL; +} + +int cam_cdm_get_caps(void *hw_priv, + void *get_hw_cap_args, uint32_t arg_size) +{ + struct cam_hw_info *cdm_hw = hw_priv; + struct cam_cdm *cdm_core; + + if ((cdm_hw) && (cdm_hw->core_info) && (get_hw_cap_args) && + (sizeof(struct cam_iommu_handle) == arg_size)) { + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + *((struct cam_iommu_handle *)get_hw_cap_args) = + cdm_core->iommu_hdl; + return 0; + } + + return -EINVAL; +} + +int cam_cdm_find_free_client_slot(struct cam_cdm *hw) +{ + int i; + + for (i = 0; i < CAM_PER_CDM_MAX_REGISTERED_CLIENTS; i++) { + if (hw->clients[i] == NULL) { + CAM_DBG(CAM_CDM, "Found client slot %d", i); + return i; + } + } + CAM_ERR(CAM_CDM, "No more client slots"); + + return -EBUSY; +} + + +void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, + enum cam_cdm_cb_status status, void *data) +{ + int i; + struct cam_cdm *core = NULL; + struct cam_cdm_client *client = NULL; + + if (!cdm_hw) { + CAM_ERR(CAM_CDM, "CDM Notify called with NULL hw info"); + return; + } + core = (struct cam_cdm *)cdm_hw->core_info; + + if (status == CAM_CDM_CB_STATUS_BL_SUCCESS) { + int client_idx; + struct cam_cdm_bl_cb_request_entry *node = + (struct cam_cdm_bl_cb_request_entry *)data; + + client_idx = CAM_CDM_GET_CLIENT_IDX(node->client_hdl); + client = core->clients[client_idx]; + if ((!client) || (client->handle != node->client_hdl)) { + CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client, + node->client_hdl); + return; + } + cam_cdm_get_client_refcount(client); + mutex_lock(&client->lock); + if (client->data.cam_cdm_callback) { + CAM_DBG(CAM_CDM, "Calling client=%s cb cookie=%d", + client->data.identifier, node->cookie); + client->data.cam_cdm_callback(node->client_hdl, + node->userdata, CAM_CDM_CB_STATUS_BL_SUCCESS, + node->cookie); + CAM_DBG(CAM_CDM, "Exit client cb cookie=%d", + node->cookie); + } else { + CAM_ERR(CAM_CDM, "No cb registered for client hdl=%x", + node->client_hdl); + } + mutex_unlock(&client->lock); + cam_cdm_put_client_refcount(client); + return; + } else if (status == CAM_CDM_CB_STATUS_HW_RESET_DONE || + status == CAM_CDM_CB_STATUS_HW_FLUSH || + status == CAM_CDM_CB_STATUS_HW_RESUBMIT || + status == CAM_CDM_CB_STATUS_INVALID_BL_CMD || + status == CAM_CDM_CB_STATUS_HW_ERROR) { + int client_idx; + struct cam_cdm_bl_cb_request_entry *node = + (struct cam_cdm_bl_cb_request_entry *)data; + + client_idx = CAM_CDM_GET_CLIENT_IDX(node->client_hdl); + client = core->clients[client_idx]; + if ((!client) || (client->handle != node->client_hdl)) { + CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client, + node->client_hdl); + return; + } + cam_cdm_get_client_refcount(client); + mutex_lock(&client->lock); + if (client->data.cam_cdm_callback) { + client->data.cam_cdm_callback( + client->handle, + client->data.userdata, + status, + node->cookie); + } else { + CAM_ERR(CAM_CDM, + "No cb registered for client: name %s, hdl=%x", + client->data.identifier, client->handle); + } + mutex_unlock(&client->lock); + cam_cdm_put_client_refcount(client); + return; + } + + for (i = 0; i < CAM_PER_CDM_MAX_REGISTERED_CLIENTS; i++) { + if (core->clients[i] != NULL) { + client = core->clients[i]; + cam_cdm_get_client_refcount(client); + mutex_lock(&client->lock); + CAM_DBG(CAM_CDM, "Found client slot %d", i); + if (client->data.cam_cdm_callback) { + if (status == CAM_CDM_CB_STATUS_PAGEFAULT) { + unsigned long iova = + (unsigned long)data; + + client->data.cam_cdm_callback( + client->handle, + client->data.userdata, + CAM_CDM_CB_STATUS_PAGEFAULT, + (iova & 0xFFFFFFFF)); + } + } else { + CAM_ERR(CAM_CDM, + "No cb registered for client hdl=%x", + client->handle); + } + mutex_unlock(&client->lock); + cam_cdm_put_client_refcount(client); + } + } +} + +static int cam_cdm_stream_handle_init(void *hw_priv, bool init) +{ + struct cam_hw_info *cdm_hw = hw_priv; + struct cam_cdm *core = NULL; + int rc = -EPERM; + + core = (struct cam_cdm *)cdm_hw->core_info; + + if (init) { + rc = cam_hw_cdm_init(hw_priv, NULL, 0); + if (rc) { + CAM_ERR(CAM_CDM, "CDM HW init failed"); + return rc; + } + + if (core->arbitration != + CAM_CDM_ARBITRATION_PRIORITY_BASED) { + rc = cam_hw_cdm_alloc_genirq_mem( + hw_priv); + if (rc) { + CAM_ERR(CAM_CDM, + "Genirqalloc failed"); + cam_hw_cdm_deinit(hw_priv, + NULL, 0); + } + } + } else { + rc = cam_hw_cdm_deinit(hw_priv, NULL, 0); + if (rc) + CAM_ERR(CAM_CDM, "Deinit failed in streamoff"); + + if (core->arbitration != + CAM_CDM_ARBITRATION_PRIORITY_BASED) { + if (cam_hw_cdm_release_genirq_mem(hw_priv)) + CAM_ERR(CAM_CDM, "Genirq release fail"); + } + } + + return rc; +} + +int cam_cdm_stream_ops_internal(void *hw_priv, + void *start_args, bool operation) +{ + struct cam_hw_info *cdm_hw = hw_priv; + struct cam_cdm *core = NULL; + int rc = -EPERM; + int client_idx; + struct cam_cdm_client *client; + uint32_t *handle = start_args; + + if (!hw_priv) + return -EINVAL; + + core = (struct cam_cdm *)cdm_hw->core_info; + mutex_lock(&cdm_hw->hw_mutex); + client_idx = CAM_CDM_GET_CLIENT_IDX(*handle); + client = core->clients[client_idx]; + if (!client) { + CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client, *handle); + mutex_unlock(&cdm_hw->hw_mutex); + return -EINVAL; + } + cam_cdm_get_client_refcount(client); + if (*handle != client->handle) { + CAM_ERR(CAM_CDM, "client id given handle=%x invalid", *handle); + rc = -EINVAL; + goto end; + } + if (operation == true) { + if (true == client->stream_on) { + CAM_ERR(CAM_CDM, + "Invalid CDM client is already streamed ON"); + goto end; + } + } else { + if (client->stream_on == false) { + CAM_ERR(CAM_CDM, + "Invalid CDM client is already streamed Off"); + goto end; + } + } + + if (operation == true) { + if (!cdm_hw->open_count) { + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_LOWSVS_VOTE; + axi_vote.num_paths = 1; + axi_vote.axi_path[0].path_data_type = + CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = + CAM_AXI_TRANSACTION_READ; + axi_vote.axi_path[0].camnoc_bw = + CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + + rc = cam_cpas_start(core->cpas_handle, + &ahb_vote, &axi_vote); + if (rc != 0) { + CAM_ERR(CAM_CDM, "CPAS start failed"); + goto end; + } + CAM_DBG(CAM_CDM, "CDM init first time"); + if (core->id == CAM_CDM_VIRTUAL) { + CAM_DBG(CAM_CDM, + "Virtual CDM HW init first time"); + rc = 0; + } else { + CAM_DBG(CAM_CDM, "CDM HW init first time"); + rc = cam_cdm_stream_handle_init(hw_priv, true); + } + if (rc == 0) { + cdm_hw->open_count++; + client->stream_on = true; + } else { + if (cam_cpas_stop(core->cpas_handle)) + CAM_ERR(CAM_CDM, "CPAS stop failed"); + } + } else { + cdm_hw->open_count++; + CAM_DBG(CAM_CDM, "CDM HW already ON count=%d", + cdm_hw->open_count); + rc = 0; + client->stream_on = true; + } + } else { + if (cdm_hw->open_count) { + cdm_hw->open_count--; + CAM_DBG(CAM_CDM, "stream OFF CDM %d", + cdm_hw->open_count); + if (!cdm_hw->open_count) { + CAM_DBG(CAM_CDM, "CDM Deinit now"); + if (core->id == CAM_CDM_VIRTUAL) { + CAM_DBG(CAM_CDM, + "Virtual CDM HW Deinit"); + rc = 0; + } else { + CAM_DBG(CAM_CDM, "CDM HW Deinit now"); + rc = cam_cdm_stream_handle_init(hw_priv, + false); + } + if (rc == 0) { + client->stream_on = false; + rc = cam_cpas_stop(core->cpas_handle); + if (rc) + CAM_ERR(CAM_CDM, + "CPAS stop failed"); + } + } else { + client->stream_on = false; + rc = 0; + CAM_DBG(CAM_CDM, + "Client stream off success =%d", + cdm_hw->open_count); + } + } else { + CAM_DBG(CAM_CDM, "stream OFF CDM Invalid %d", + cdm_hw->open_count); + rc = -ENXIO; + } + } +end: + cam_cdm_put_client_refcount(client); + mutex_unlock(&cdm_hw->hw_mutex); + return rc; +} + +int cam_cdm_stream_start(void *hw_priv, + void *start_args, uint32_t size) +{ + int rc = 0; + + if (!hw_priv) + return -EINVAL; + + rc = cam_cdm_stream_ops_internal(hw_priv, start_args, true); + return rc; + +} + +int cam_cdm_stream_stop(void *hw_priv, + void *start_args, uint32_t size) +{ + int rc = 0; + + if (!hw_priv) + return -EINVAL; + + rc = cam_cdm_stream_ops_internal(hw_priv, start_args, false); + return rc; + +} + +int cam_cdm_process_cmd(void *hw_priv, + uint32_t cmd, void *cmd_args, uint32_t arg_size) +{ + struct cam_hw_info *cdm_hw = hw_priv; + struct cam_hw_soc_info *soc_data = NULL; + struct cam_cdm *core = NULL; + int rc = -EINVAL; + + if ((!hw_priv) || (!cmd_args) || + (cmd >= CAM_CDM_HW_INTF_CMD_INVALID)) + return rc; + + soc_data = &cdm_hw->soc_info; + core = (struct cam_cdm *)cdm_hw->core_info; + switch (cmd) { + case CAM_CDM_HW_INTF_CMD_SUBMIT_BL: { + struct cam_cdm_hw_intf_cmd_submit_bl *req; + int idx; + struct cam_cdm_client *client; + + if (sizeof(struct cam_cdm_hw_intf_cmd_submit_bl) != arg_size) { + CAM_ERR(CAM_CDM, "Invalid CDM cmd %d arg size=%x", cmd, + arg_size); + break; + } + req = (struct cam_cdm_hw_intf_cmd_submit_bl *)cmd_args; + if ((req->data->type < 0) || + (req->data->type > CAM_CDM_BL_CMD_TYPE_KERNEL_IOVA)) { + CAM_ERR(CAM_CDM, "Invalid req bl cmd addr type=%d", + req->data->type); + break; + } + idx = CAM_CDM_GET_CLIENT_IDX(req->handle); + client = core->clients[idx]; + if ((!client) || (req->handle != client->handle)) { + CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client, + req->handle); + break; + } + cam_cdm_get_client_refcount(client); + if ((req->data->flag == true) && + (!client->data.cam_cdm_callback)) { + CAM_ERR(CAM_CDM, + "CDM request cb without registering cb"); + cam_cdm_put_client_refcount(client); + break; + } + if (client->stream_on != true) { + CAM_ERR(CAM_CDM, + "Invalid CDM needs to be streamed ON first"); + cam_cdm_put_client_refcount(client); + break; + } + if (core->id == CAM_CDM_VIRTUAL) + rc = cam_virtual_cdm_submit_bl(cdm_hw, req, client); + else + rc = cam_hw_cdm_submit_bl(cdm_hw, req, client); + + cam_cdm_put_client_refcount(client); + break; + } + case CAM_CDM_HW_INTF_CMD_ACQUIRE: { + struct cam_cdm_acquire_data *data; + int idx; + struct cam_cdm_client *client; + + if (sizeof(struct cam_cdm_acquire_data) != arg_size) { + CAM_ERR(CAM_CDM, "Invalid CDM cmd %d arg size=%x", cmd, + arg_size); + break; + } + + mutex_lock(&cdm_hw->hw_mutex); + data = (struct cam_cdm_acquire_data *)cmd_args; + CAM_DBG(CAM_CDM, "Trying to acquire client=%s in hw idx=%d", + data->identifier, core->index); + + if (data->priority >= CAM_CDM_BL_FIFO_MAX) { + mutex_unlock(&cdm_hw->hw_mutex); + CAM_ERR(CAM_CDM, + "Invalid priority requested %d", + data->priority); + rc = -EINVAL; + break; + } + + if (core->id != CAM_CDM_VIRTUAL && + core->bl_fifo[data->priority].bl_depth == 0) { + mutex_unlock(&cdm_hw->hw_mutex); + CAM_ERR(CAM_CDM, + "FIFO %d not supported for core %d", + data->priority, + core->id); + rc = -EINVAL; + break; + } + + idx = cam_cdm_find_free_client_slot(core); + if ((idx < 0) || (core->clients[idx])) { + mutex_unlock(&cdm_hw->hw_mutex); + CAM_ERR(CAM_CDM, + "Fail to client slots, client=%s in hw idx=%d", + data->identifier, core->index); + break; + } + core->clients[idx] = kzalloc(sizeof(struct cam_cdm_client), + GFP_KERNEL); + if (!core->clients[idx]) { + mutex_unlock(&cdm_hw->hw_mutex); + rc = -ENOMEM; + break; + } + + mutex_unlock(&cdm_hw->hw_mutex); + client = core->clients[idx]; + mutex_init(&client->lock); + data->ops = core->ops; + if (core->id == CAM_CDM_VIRTUAL) { + data->cdm_version.major = 1; + data->cdm_version.minor = 0; + data->cdm_version.incr = 0; + data->cdm_version.reserved = 0; + data->ops = cam_cdm_get_ops(0, + &data->cdm_version, true); + if (!data->ops) { + mutex_destroy(&client->lock); + mutex_lock(&cdm_hw->hw_mutex); + kfree(core->clients[idx]); + core->clients[idx] = NULL; + mutex_unlock( + &cdm_hw->hw_mutex); + rc = -EPERM; + CAM_ERR(CAM_CDM, "Invalid ops for virtual cdm"); + break; + } + } else { + data->cdm_version = core->version; + } + + cam_cdm_get_client_refcount(client); + mutex_lock(&client->lock); + memcpy(&client->data, data, + sizeof(struct cam_cdm_acquire_data)); + client->handle = CAM_CDM_CREATE_CLIENT_HANDLE( + core->index, + data->priority, + idx); + client->stream_on = false; + data->handle = client->handle; + CAM_DBG(CAM_CDM, "Acquired client=%s in hwidx=%d", + data->identifier, core->index); + mutex_unlock(&client->lock); + rc = 0; + break; + } + case CAM_CDM_HW_INTF_CMD_RELEASE: { + uint32_t *handle = cmd_args; + int idx; + struct cam_cdm_client *client; + + if (sizeof(uint32_t) != arg_size) { + CAM_ERR(CAM_CDM, + "Invalid CDM cmd %d size=%x for handle=%x", + cmd, arg_size, *handle); + return -EINVAL; + } + idx = CAM_CDM_GET_CLIENT_IDX(*handle); + mutex_lock(&cdm_hw->hw_mutex); + client = core->clients[idx]; + if ((!client) || (*handle != client->handle)) { + CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", + client, *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + cam_cdm_put_client_refcount(client); + mutex_lock(&client->lock); + if (client->refcount != 0) { + CAM_ERR(CAM_CDM, "CDM Client refcount not zero %d", + client->refcount); + rc = -EPERM; + mutex_unlock(&client->lock); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + core->clients[idx] = NULL; + mutex_unlock(&client->lock); + mutex_destroy(&client->lock); + kfree(client); + mutex_unlock(&cdm_hw->hw_mutex); + rc = 0; + break; + } + case CAM_CDM_HW_INTF_CMD_RESET_HW: { + uint32_t *handle = cmd_args; + int idx; + struct cam_cdm_client *client; + + if (sizeof(uint32_t) != arg_size) { + CAM_ERR(CAM_CDM, + "Invalid CDM cmd %d size=%x for handle=%x", + cmd, arg_size, *handle); + return -EINVAL; + } + idx = CAM_CDM_GET_CLIENT_IDX(*handle); + mutex_lock(&cdm_hw->hw_mutex); + client = core->clients[idx]; + if (!client) { + CAM_ERR(CAM_CDM, + "Client not present for handle %d", + *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + + if (*handle != client->handle) { + CAM_ERR(CAM_CDM, + "handle mismatch, client handle %d index %d received handle %d", + client->handle, idx, *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + rc = cam_hw_cdm_reset_hw(cdm_hw, *handle); + if (rc) { + CAM_ERR(CAM_CDM, + "CDM HW reset failed for handle 0x%x rc = %d", + *handle, rc); + } else { + CAM_INFO_RATE_LIMIT(CAM_CDM, + "CDM HW reset done for handle 0x%x", + *handle); + } + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + case CAM_CDM_HW_INTF_CMD_FLUSH_HW: { + uint32_t *handle = cmd_args; + int idx; + struct cam_cdm_client *client; + + if (sizeof(uint32_t) != arg_size) { + CAM_ERR(CAM_CDM, + "Invalid CDM cmd %d size=%x for handle=%x", + cmd, arg_size, *handle); + return -EINVAL; + } + idx = CAM_CDM_GET_CLIENT_IDX(*handle); + mutex_lock(&cdm_hw->hw_mutex); + client = core->clients[idx]; + if (!client) { + CAM_ERR(CAM_CDM, + "Client not present for handle %d", + *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + + if (*handle != client->handle) { + CAM_ERR(CAM_CDM, + "handle mismatch, client handle %d index %d received handle %d", + client->handle, idx, *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + + rc = cam_hw_cdm_flush_hw(cdm_hw, *handle); + if (rc) { + CAM_ERR(CAM_CDM, + "CDM HW flush failed for handle 0x%x rc = %d", + *handle, rc); + } else { + CAM_INFO_RATE_LIMIT(CAM_CDM, + "CDM HW flush done for handle 0x%x", + *handle); + } + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + case CAM_CDM_HW_INTF_CMD_HANDLE_ERROR: { + uint32_t *handle = cmd_args; + int idx; + struct cam_cdm_client *client; + + if (sizeof(uint32_t) != arg_size) { + CAM_ERR(CAM_CDM, + "Invalid CDM cmd %d size=%x for handle=%x", + cmd, arg_size, *handle); + return -EINVAL; + } + + idx = CAM_CDM_GET_CLIENT_IDX(*handle); + mutex_lock(&cdm_hw->hw_mutex); + client = core->clients[idx]; + if (!client) { + CAM_ERR(CAM_CDM, + "Client not present for handle %d", + *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + + if (*handle != client->handle) { + CAM_ERR(CAM_CDM, + "handle mismatch, client handle %d index %d received handle %d", + client->handle, idx, *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + + rc = cam_hw_cdm_handle_error(cdm_hw, *handle); + if (rc) { + CAM_ERR(CAM_CDM, + "CDM HW handle error failed for handle 0x%x rc = %d", + *handle, rc); + } else { + CAM_INFO_RATE_LIMIT(CAM_CDM, + "CDM HW handle error done for handle 0x%x", + *handle); + } + + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + case CAM_CDM_HW_INTF_CMD_HANG_DETECT: { + uint32_t *handle = cmd_args; + int idx; + struct cam_cdm_client *client; + + if (sizeof(uint32_t) != arg_size) { + CAM_ERR(CAM_CDM, + "Invalid CDM cmd %d size=%x for handle=%x", + cmd, arg_size, *handle); + return -EINVAL; + } + + idx = CAM_CDM_GET_CLIENT_IDX(*handle); + client = core->clients[idx]; + if (!client) { + CAM_ERR(CAM_CDM, + "Client not present for handle %d", + *handle); + break; + } + + if (*handle != client->handle) { + CAM_ERR(CAM_CDM, + "handle mismatch, client handle %d index %d received handle %d", + client->handle, idx, *handle); + break; + } + + rc = cam_hw_cdm_hang_detect(cdm_hw, *handle); + break; + } + case CAM_CDM_HW_INTF_DUMP_DBG_REGS: + { + uint32_t *handle = cmd_args; + + if (sizeof(uint32_t) != arg_size) { + CAM_ERR(CAM_CDM, + "Invalid CDM cmd %d size=%x for handle=0x%x", + cmd, arg_size, *handle); + return -EINVAL; + } + + mutex_lock(&cdm_hw->hw_mutex); + cam_hw_cdm_dump_core_debug_registers(cdm_hw, true); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + default: + CAM_ERR(CAM_CDM, "CDM HW intf command not valid =%d", cmd); + break; + } + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_core_common.h b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_core_common.h new file mode 100644 index 0000000000000000000000000000000000000000..96fd8b36d0372133fa95258b5aa930cfa9b3f6df --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_core_common.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CDM_CORE_COMMON_H_ +#define _CAM_CDM_CORE_COMMON_H_ + +#include "cam_mem_mgr.h" + +#define CAM_CDM100_VERSION 0x10000000 +#define CAM_CDM110_VERSION 0x10010000 +#define CAM_CDM120_VERSION 0x10020000 +#define CAM_CDM200_VERSION 0x20000000 +#define CAM_CDM210_VERSION 0x20010000 + +#define CAM_CDM_AHB_BURST_LEN_1 (BIT(1) - 1) +#define CAM_CDM_AHB_BURST_LEN_4 (BIT(2) - 1) +#define CAM_CDM_AHB_BURST_LEN_8 (BIT(3) - 1) +#define CAM_CDM_AHB_BURST_LEN_16 (BIT(4) - 1) +#define CAM_CDM_AHB_BURST_EN BIT(4) +#define CAM_CDM_AHB_STOP_ON_ERROR BIT(8) +#define CAM_CDM_ARB_SEL_RR BIT(16) +#define CAM_CDM_IMPLICIT_WAIT_EN BIT(17) + +extern struct cam_cdm_utils_ops CDM170_ops; + +int cam_hw_cdm_init(void *hw_priv, void *init_hw_args, uint32_t arg_size); +int cam_hw_cdm_deinit(void *hw_priv, void *init_hw_args, uint32_t arg_size); +int cam_hw_cdm_alloc_genirq_mem(void *hw_priv); +int cam_hw_cdm_release_genirq_mem(void *hw_priv); +int cam_cdm_get_caps(void *hw_priv, void *get_hw_cap_args, uint32_t arg_size); +int cam_cdm_stream_ops_internal(void *hw_priv, void *start_args, + bool operation); +int cam_cdm_stream_start(void *hw_priv, void *start_args, uint32_t size); +int cam_cdm_stream_stop(void *hw_priv, void *start_args, uint32_t size); +int cam_cdm_process_cmd(void *hw_priv, uint32_t cmd, void *cmd_args, + uint32_t arg_size); +bool cam_cdm_set_cam_hw_version( + uint32_t ver, struct cam_hw_version *cam_version); +bool cam_cdm_cpas_cb(uint32_t client_handle, void *userdata, + struct cam_cpas_irq_data *irq_data); +struct cam_cdm_utils_ops *cam_cdm_get_ops( + uint32_t ver, struct cam_hw_version *cam_version, bool by_cam_version); +int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, + struct cam_cdm_hw_intf_cmd_submit_bl *req, + struct cam_cdm_client *client); +int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, + struct cam_cdm_hw_intf_cmd_submit_bl *req, + struct cam_cdm_client *client); +int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle); +int cam_hw_cdm_flush_hw(struct cam_hw_info *cdm_hw, uint32_t handle); +int cam_hw_cdm_handle_error(struct cam_hw_info *cdm_hw, uint32_t handle); +int cam_hw_cdm_hang_detect(struct cam_hw_info *cdm_hw, uint32_t handle); +struct cam_cdm_bl_cb_request_entry *cam_cdm_find_request_by_bl_tag( + uint32_t tag, struct list_head *bl_list); +void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, + enum cam_cdm_cb_status status, void *data); +void cam_hw_cdm_dump_core_debug_registers( + struct cam_hw_info *cdm_hw, bool pause_core); + +#endif /* _CAM_CDM_CORE_COMMON_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_core.c b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_core.c new file mode 100644 index 0000000000000000000000000000000000000000..0739bd25e98354afff46e7c61cd30a7ee6431118 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_core.c @@ -0,0 +1,2399 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include "cam_soc_util.h" +#include "cam_smmu_api.h" +#include "cam_cdm_intf_api.h" +#include "cam_cdm.h" +#include "cam_cdm_core_common.h" +#include "cam_cdm_soc.h" +#include "cam_io_util.h" +#include "cam_cdm_hw_reg_1_0.h" +#include "cam_cdm_hw_reg_1_1.h" +#include "cam_cdm_hw_reg_1_2.h" +#include "cam_cdm_hw_reg_2_0.h" +#include "cam_cdm_hw_reg_2_1.h" +#include "cam_trace.h" +#include "cam_req_mgr_workq.h" + +#define CAM_CDM_BL_FIFO_WAIT_TIMEOUT 2000 +#define CAM_CDM_DBG_GEN_IRQ_USR_DATA 0xff + +static void cam_hw_cdm_work(struct work_struct *work); + +/* DT match table entry for all CDM variants*/ +static const struct of_device_id msm_cam_hw_cdm_dt_match[] = { + { + .compatible = CAM_HW_CDM_CPAS_0_NAME, + .data = &cam_cdm_1_0_reg_offset, + }, + { + .compatible = CAM_HW_CDM_CPAS_NAME_1_0, + .data = &cam_cdm_1_0_reg_offset, + }, + { + .compatible = CAM_HW_CDM_CPAS_NAME_1_1, + .data = &cam_cdm_1_1_reg_offset, + }, + { + .compatible = CAM_HW_CDM_CPAS_NAME_1_2, + .data = &cam_cdm_1_2_reg_offset, + }, + { + .compatible = CAM_HW_CDM_IFE_NAME_1_2, + .data = &cam_cdm_1_2_reg_offset, + }, + { + .compatible = CAM_HW_CDM_CPAS_NAME_2_0, + .data = &cam_cdm_2_0_reg_offset, + }, + { + .compatible = CAM_HW_CDM_OPE_NAME_2_0, + .data = &cam_cdm_2_0_reg_offset, + }, + { + .compatible = CAM_HW_CDM_CPAS_NAME_2_1, + .data = &cam_cdm_2_1_reg_offset, + }, + { + .compatible = CAM_HW_CDM_OPE_NAME_2_1, + .data = &cam_cdm_2_1_reg_offset, + }, + { + .compatible = CAM_HW_CDM_IFE_NAME_2_1, + .data = &cam_cdm_2_1_reg_offset, + }, + {}, +}; + +static enum cam_cdm_id cam_hw_cdm_get_id_by_name(char *name) +{ + if (strnstr(name, CAM_HW_CDM_CPAS_0_NAME, + strlen(CAM_HW_CDM_CPAS_0_NAME))) + return CAM_CDM_CPAS; + if (strnstr(name, CAM_HW_CDM_CPAS_NAME_1_0, + strlen(CAM_HW_CDM_CPAS_NAME_1_0))) + return CAM_CDM_CPAS; + if (strnstr(name, CAM_HW_CDM_CPAS_NAME_1_1, + strlen(CAM_HW_CDM_CPAS_NAME_1_1))) + return CAM_CDM_CPAS; + if (strnstr(name, CAM_HW_CDM_CPAS_NAME_1_2, + strlen(CAM_HW_CDM_CPAS_NAME_1_2))) + return CAM_CDM_CPAS; + if (strnstr(name, CAM_HW_CDM_IFE_NAME_1_2, + strlen(CAM_HW_CDM_CPAS_NAME_1_2))) + return CAM_CDM_IFE; + if (strnstr(name, CAM_HW_CDM_CPAS_NAME_2_0, + strlen(CAM_HW_CDM_CPAS_NAME_2_0))) + return CAM_CDM_CPAS; + if (strnstr(name, CAM_HW_CDM_OPE_NAME_2_0, + strlen(CAM_HW_CDM_CPAS_NAME_2_0))) + return CAM_CDM_OPE; + if (strnstr(name, CAM_HW_CDM_CPAS_NAME_2_1, + strlen(CAM_HW_CDM_CPAS_NAME_2_1))) + return CAM_CDM_CPAS; + if (strnstr(name, CAM_HW_CDM_OPE_NAME_2_1, + strlen(CAM_HW_CDM_OPE_NAME_2_1))) + return CAM_CDM_OPE; + if (strnstr(name, CAM_HW_CDM_IFE_NAME_2_1, + strlen(CAM_HW_CDM_IFE_NAME_2_1))) + return CAM_CDM_IFE; + + return CAM_CDM_MAX; +} + +static int cam_hw_cdm_enable_bl_done_irq(struct cam_hw_info *cdm_hw, + bool enable, uint32_t fifo_idx) +{ + int rc = -EIO; + uint32_t irq_mask = 0; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + + if (cam_cdm_read_hw_reg(cdm_hw, + core->offsets->irq_reg[fifo_idx]->irq_mask, + &irq_mask)) { + CAM_ERR(CAM_CDM, "Failed to read CDM IRQ mask"); + return rc; + } + + if (enable == true) { + if (cam_cdm_write_hw_reg(cdm_hw, + core->offsets->irq_reg[fifo_idx]->irq_mask, + (irq_mask | 0x4))) { + CAM_ERR(CAM_CDM, "Write failed to enable BL done irq"); + } else { + set_bit(fifo_idx, &core->cdm_status); + rc = 0; + CAM_DBG(CAM_CDM, "BL done irq enabled =%d", + test_bit(fifo_idx, &core->cdm_status)); + } + } else { + if (cam_cdm_write_hw_reg(cdm_hw, + core->offsets->irq_reg[fifo_idx]->irq_mask, + (irq_mask & 0x70003))) { + CAM_ERR(CAM_CDM, "Write failed to disable BL done irq"); + } else { + clear_bit(fifo_idx, &core->cdm_status); + rc = 0; + CAM_DBG(CAM_CDM, "BL done irq disable =%d", + test_bit(fifo_idx, &core->cdm_status)); + } + } + return rc; +} + +static int cam_hw_cdm_pause_core(struct cam_hw_info *cdm_hw, bool pause) +{ + int rc = 0; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + uint32_t val = 0x1; + + if (pause) + val |= 0x2; + + if (cam_cdm_write_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_en, val)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW core_en"); + rc = -EIO; + } + + return rc; +} + +int cam_hw_cdm_enable_core_dbg(struct cam_hw_info *cdm_hw, uint32_t value) +{ + int rc = 0; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + + if (cam_cdm_write_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_debug, + value)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW core debug"); + rc = -EIO; + } + + return rc; +} + +int cam_hw_cdm_disable_core_dbg(struct cam_hw_info *cdm_hw) +{ + int rc = 0; + struct cam_cdm *cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->core_debug, 0)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW core debug"); + rc = -EIO; + } + + return rc; +} + +void cam_hw_cdm_dump_scratch_registors(struct cam_hw_info *cdm_hw) +{ + uint32_t dump_reg = 0; + int i; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_en, &dump_reg); + CAM_ERR(CAM_CDM, "dump core en=%x", dump_reg); + + for (i = 0; i < core->offsets->reg_data->num_scratch_reg; i++) { + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->scratch[i]->scratch_reg, + &dump_reg); + CAM_ERR(CAM_CDM, "dump scratch%d=%x", i, dump_reg); + } +} + +int cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo( + struct cam_hw_info *cdm_hw, + uint32_t fifo_idx, + uint32_t *pending_bl_req) +{ + int rc = 0; + uint32_t fifo_reg; + uint32_t fifo_id; + + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + + if (fifo_idx >= CAM_CDM_BL_FIFO_REG_NUM) { + CAM_ERR(CAM_CDM, + "BL_FIFO index is wrong. fifo_idx %d", + fifo_idx); + rc = -EINVAL; + goto end; + } + + fifo_reg = fifo_idx / 2; + fifo_id = fifo_idx % 2; + + if (core->offsets->cmn_reg->pending_req[fifo_reg]) { + if (cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->pending_req + [fifo_reg]->rb_offset, + pending_bl_req)) { + CAM_ERR(CAM_CDM, "Error reading CDM register"); + rc = -EIO; + goto end; + } + + *pending_bl_req = (*pending_bl_req >> ( + core->offsets->cmn_reg->pending_req + [fifo_reg]->rb_next_fifo_shift * + fifo_id)) & core->offsets->cmn_reg->pending_req + [fifo_reg]->rb_mask; + rc = 0; + } + + CAM_DBG(CAM_CDM, "pending_bl_req %d fifo_reg %d, fifo_id %d", + *pending_bl_req, fifo_reg, fifo_id); + +end: + return rc; +} + +static void cam_hw_cdm_dump_bl_fifo_data(struct cam_hw_info *cdm_hw) +{ + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + int i, j; + uint32_t num_pending_req = 0, dump_reg; + + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) { + cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo(cdm_hw, + i, &num_pending_req); + for (j = 0; j < num_pending_req ; j++) { + cam_cdm_write_hw_reg(cdm_hw, + core->offsets->cmn_reg->bl_fifo_rb, j); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->bl_fifo_base_rb, + &dump_reg); + CAM_INFO(CAM_CDM, "BL(%d) base addr =%x", j, dump_reg); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->bl_fifo_len_rb, + &dump_reg); + CAM_INFO(CAM_CDM, + "CDM HW current BL len=%d ARB %d tag=%d, ", + (dump_reg & CAM_CDM_CURRENT_BL_LEN), + (dump_reg & CAM_CDM_CURRENT_BL_ARB) >> + CAM_CDM_CURRENT_BL_ARB_SHIFT, + (dump_reg & CAM_CDM_CURRENT_BL_TAG) >> + CAM_CDM_CURRENT_BL_TAG_SHIFT); + } + } +} + +void cam_hw_cdm_dump_core_debug_registers(struct cam_hw_info *cdm_hw, + bool pause_core) +{ + uint32_t dump_reg[4], core_dbg = 0x100; + int i; + bool is_core_paused_already; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + const struct cam_cdm_icl_regs *inv_cmd_log = + core->offsets->cmn_reg->icl_reg; + + cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->core_en, + &dump_reg[0]); + + if (pause_core) { + cam_hw_cdm_pause_core(cdm_hw, true); + usleep_range(1000, 1010); + } + cam_hw_cdm_enable_core_dbg(cdm_hw, core_dbg); + + cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->usr_data, + &dump_reg[1]); + + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->debug_status, + &dump_reg[2]); + + CAM_INFO(CAM_CDM, "Core stat 0x%x udata 0x%x dbg_stat 0x%x", + dump_reg[0], dump_reg[1], dump_reg[2]); + + if (core_dbg & 0x100) { + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->last_ahb_addr, + &dump_reg[0]); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->last_ahb_data, + &dump_reg[1]); + CAM_INFO(CAM_CDM, "AHB dump lastaddr=0x%x lastdata=0x%x", + dump_reg[0], dump_reg[1]); + } else { + CAM_INFO(CAM_CDM, "CDM HW AHB dump not enable"); + } + + if (inv_cmd_log) { + if (inv_cmd_log->misc_regs) { + cam_cdm_read_hw_reg(cdm_hw, + inv_cmd_log->misc_regs->icl_status, + &dump_reg[0]); + cam_cdm_read_hw_reg(cdm_hw, + inv_cmd_log->misc_regs->icl_inv_bl_addr, + &dump_reg[1]); + CAM_INFO(CAM_CDM, + "Last Inv Cmd Log(ICL)Status: 0x%x bl_addr: 0x%x", + dump_reg[0], dump_reg[1]); + } + if (inv_cmd_log->data_regs) { + cam_cdm_read_hw_reg(cdm_hw, + inv_cmd_log->data_regs->icl_inv_data, + &dump_reg[0]); + CAM_INFO(CAM_CDM, "First word of Last Inv cmd: 0x%x", + dump_reg[0]); + + cam_cdm_read_hw_reg(cdm_hw, + inv_cmd_log->data_regs->icl_last_data_0, + &dump_reg[0]); + cam_cdm_read_hw_reg(cdm_hw, + inv_cmd_log->data_regs->icl_last_data_1, + &dump_reg[1]); + cam_cdm_read_hw_reg(cdm_hw, + inv_cmd_log->data_regs->icl_last_data_2, + &dump_reg[2]); + + + CAM_INFO(CAM_CDM, "Last good cmd word 0x%x 0x%x 0x%x", + dump_reg[0], dump_reg[1], dump_reg[2]); + } + } + + if (core_dbg & 0x10000) { + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_en, &dump_reg[0]); + is_core_paused_already = (bool)(dump_reg[0] & 0x20); + if (!is_core_paused_already) { + cam_hw_cdm_pause_core(cdm_hw, true); + usleep_range(1000, 1010); + } + + cam_hw_cdm_dump_bl_fifo_data(cdm_hw); + + if (!is_core_paused_already) + cam_hw_cdm_pause_core(cdm_hw, false); + } + + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_cfg, &dump_reg[0]); + CAM_INFO(CAM_CDM, "CDM HW core cfg=0x%x", dump_reg[0]); + + for (i = 0; i < + core->offsets->reg_data->num_bl_fifo_irq; + i++) { + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->irq_reg[i]->irq_status, &dump_reg[0]); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->irq_reg[i]->irq_set, &dump_reg[1]); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->irq_reg[i]->irq_mask, &dump_reg[2]); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->irq_reg[i]->irq_clear, &dump_reg[3]); + + CAM_INFO(CAM_CDM, + "cnt %d irq status 0x%x set 0x%x mask 0x%x clear 0x%x", + i, dump_reg[0], dump_reg[1], dump_reg[2], dump_reg[3]); + } + + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->current_bl_base, &dump_reg[0]); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->current_used_ahb_base, &dump_reg[1]); + CAM_INFO(CAM_CDM, "curr BL base 0x%x AHB base 0x%x", + dump_reg[0], dump_reg[1]); + + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->wait_status, &dump_reg[0]); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->comp_wait[0]->comp_wait_status, + &dump_reg[1]); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->comp_wait[1]->comp_wait_status, + &dump_reg[2]); + CAM_INFO(CAM_CDM, "wait status 0x%x comp wait status 0x%x: 0x%x", + dump_reg[0], dump_reg[1], dump_reg[2]); + + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->current_bl_len, &dump_reg[0]); + CAM_INFO(CAM_CDM, + "CDM HW current BL len=%d ARB %d FIFO %d tag=%d, ", + (dump_reg[0] & CAM_CDM_CURRENT_BL_LEN), + (dump_reg[0] & CAM_CDM_CURRENT_BL_ARB) >> + CAM_CDM_CURRENT_BL_ARB_SHIFT, + (dump_reg[0] & CAM_CDM_CURRENT_BL_FIFO) >> + CAM_CDM_CURRENT_BL_FIFO_SHIFT, + (dump_reg[0] & CAM_CDM_CURRENT_BL_TAG) >> + CAM_CDM_CURRENT_BL_TAG_SHIFT); + + cam_hw_cdm_disable_core_dbg(cdm_hw); + if (pause_core) + cam_hw_cdm_pause_core(cdm_hw, false); +} + +enum cam_cdm_arbitration cam_cdm_get_arbitration_type( + uint32_t cdm_version, + enum cam_cdm_id id) +{ + enum cam_cdm_arbitration arbitration; + + if (cdm_version < CAM_CDM_VERSION_2_0) { + arbitration = CAM_CDM_ARBITRATION_NONE; + goto end; + } + + switch (id) { + case CAM_CDM_CPAS: + arbitration = CAM_CDM_ARBITRATION_ROUND_ROBIN; + break; + default: + arbitration = CAM_CDM_ARBITRATION_PRIORITY_BASED; + break; + } +end: + return arbitration; +} + +int cam_hw_cdm_set_cdm_blfifo_cfg(struct cam_hw_info *cdm_hw) +{ + uint32_t blfifo_cfg_mask = 0; + int rc = 0, i; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + + blfifo_cfg_mask = blfifo_cfg_mask | + CAM_CDM_BL_FIFO_REQ_SIZE_MAX; + + for (i = 0; i < core->offsets->reg_data->num_bl_fifo_irq; i++) { + rc = cam_cdm_write_hw_reg(cdm_hw, + core->offsets->irq_reg[i]->irq_mask, 0x70003); + if (rc) { + CAM_ERR(CAM_CDM, + "Unable to write to cdm irq mask register"); + rc = -EIO; + goto end; + } + } + + if (core->hw_version >= CAM_CDM_VERSION_2_0) { + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) { + blfifo_cfg_mask = blfifo_cfg_mask | + (core->bl_fifo[i].bl_depth + << CAM_CDM_BL_FIFO_LENGTH_CFG_SHIFT); + rc = cam_cdm_write_hw_reg(cdm_hw, + core->offsets->bl_fifo_reg[i]->bl_fifo_cfg, + blfifo_cfg_mask); + if (rc) { + CAM_ERR(CAM_CDM, + "Unable to write to cdm irq mask register"); + rc = -EIO; + goto end; + } + } + } else { + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) { + rc = cam_cdm_write_hw_reg(cdm_hw, + core->offsets->bl_fifo_reg[i]->bl_fifo_cfg, + blfifo_cfg_mask); + if (rc) { + CAM_ERR(CAM_CDM, + "Unable to write to cdm irq mask register"); + rc = -EIO; + goto end; + } + } + } +end: + return rc; +} + +int cam_hw_cdm_set_cdm_core_cfg(struct cam_hw_info *cdm_hw) +{ + uint32_t cdm_version; + uint32_t cfg_mask = 0; + int rc; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + + cfg_mask = cfg_mask | + CAM_CDM_AHB_STOP_ON_ERROR| + CAM_CDM_AHB_BURST_EN| + CAM_CDM_AHB_BURST_LEN_16; + + /* use version from cdm_core structure. */ + if (cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->cdm_hw_version, + &cdm_version)) { + CAM_ERR(CAM_CDM, "Error reading CDM register"); + rc = -EIO; + goto end; + } + + if (cdm_version < CAM_CDM_VERSION_2_0) { + rc = cam_cdm_write_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_cfg, cfg_mask); + if (rc) { + CAM_ERR(CAM_CDM, "Error writing cdm core cfg"); + rc = -EIO; + goto end; + } + } else { + if (core->id != CAM_CDM_CPAS) + cfg_mask = cfg_mask | CAM_CDM_IMPLICIT_WAIT_EN; + + if (core->arbitration == CAM_CDM_ARBITRATION_ROUND_ROBIN) + cfg_mask = cfg_mask | CAM_CDM_ARB_SEL_RR; + + rc = cam_cdm_write_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_cfg, cfg_mask); + if (rc) { + CAM_ERR(CAM_CDM, "Error writing cdm core cfg"); + rc = -EIO; + goto end; + } + } + +end: + return rc; +} + +int cam_hw_cdm_wait_for_bl_fifo( + struct cam_hw_info *cdm_hw, + uint32_t bl_count, + uint32_t fifo_idx) +{ + uint32_t pending_bl = 0; + int32_t available_bl_slots = 0; + int rc = -EIO; + long time_left; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + struct cam_cdm_bl_fifo *bl_fifo = NULL; + + if (fifo_idx >= CAM_CDM_BL_FIFO_MAX) { + rc = -EINVAL; + CAM_ERR(CAM_CDM, + "Invalid fifo index %d rc = %d", + fifo_idx, rc); + goto end; + } + + bl_fifo = &core->bl_fifo[fifo_idx]; + + do { + if (cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo( + cdm_hw, fifo_idx, &pending_bl)) { + CAM_ERR(CAM_CDM, "Failed to read CDM pending BL's"); + rc = -EIO; + break; + } + available_bl_slots = bl_fifo->bl_depth - pending_bl; + if (available_bl_slots < 0) { + CAM_ERR(CAM_CDM, "Invalid available slots %d:%d:%d", + available_bl_slots, bl_fifo->bl_depth, + pending_bl); + break; + } + if (bl_count < (available_bl_slots - 1)) { + CAM_DBG(CAM_CDM, + "BL slot available_cnt=%d requested=%d", + (available_bl_slots - 1), bl_count); + rc = available_bl_slots - 1; + break; + } else if (0 == (available_bl_slots - 1)) { + rc = cam_hw_cdm_enable_bl_done_irq(cdm_hw, + true, fifo_idx); + if (rc) { + CAM_ERR(CAM_CDM, "Enable BL done irq failed"); + break; + } + time_left = wait_for_completion_timeout( + &core->bl_fifo[fifo_idx].bl_complete, + msecs_to_jiffies( + CAM_CDM_BL_FIFO_WAIT_TIMEOUT)); + if (time_left <= 0) { + CAM_ERR(CAM_CDM, + "CDM HW BL Wait timed out failed"); + if (cam_hw_cdm_enable_bl_done_irq(cdm_hw, + false, fifo_idx)) + CAM_ERR(CAM_CDM, + "Disable BL done irq failed"); + rc = -EIO; + break; + } + if (cam_hw_cdm_enable_bl_done_irq(cdm_hw, + false, fifo_idx)) + CAM_ERR(CAM_CDM, "Disable BL done irq failed"); + rc = 1; + CAM_DBG(CAM_CDM, "CDM HW is ready for data"); + } else { + rc = (bl_count - (available_bl_slots - 1)); + break; + } + } while (1); + +end: + + return rc; +} + +bool cam_hw_cdm_bl_write( + struct cam_hw_info *cdm_hw, uint32_t src, + uint32_t len, uint32_t tag, bool set_arb, + uint32_t fifo_idx) +{ + struct cam_cdm *cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->bl_fifo_reg[fifo_idx]->bl_fifo_base, + src)) { + CAM_ERR(CAM_CDM, "Failed to write CDM base to BL base"); + return true; + } + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->bl_fifo_reg[fifo_idx]->bl_fifo_len, + ((len & 0xFFFFF) | ((tag & 0xFF) << 24)) | + ((set_arb) ? (1 << 20) : (0)))) { + CAM_ERR(CAM_CDM, "Failed to write CDM BL len"); + return true; + } + return false; +} + +bool cam_hw_cdm_commit_bl_write(struct cam_hw_info *cdm_hw, uint32_t fifo_idx) +{ + struct cam_cdm *cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->bl_fifo_reg[fifo_idx]->bl_fifo_store, + 1)) { + CAM_ERR(CAM_CDM, "Failed to write CDM commit BL"); + return true; + } + return false; +} + +int cam_hw_cdm_submit_gen_irq( + struct cam_hw_info *cdm_hw, + struct cam_cdm_hw_intf_cmd_submit_bl *req, + uint32_t fifo_idx, bool set_arb) +{ + struct cam_cdm_bl_cb_request_entry *node; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + uint32_t len; + int rc; + bool bit_wr_enable = false; + + if (core->bl_fifo[fifo_idx].bl_tag > + (core->bl_fifo[fifo_idx].bl_depth - 1)) { + CAM_ERR(CAM_CDM, + "Invalid bl_tag=%d bl_depth=%d fifo_idx=%d", + core->bl_fifo[fifo_idx].bl_tag, + core->bl_fifo[fifo_idx].bl_depth, + fifo_idx); + rc = -EINVAL; + goto end; + } + CAM_DBG(CAM_CDM, "CDM write BL last cmd tag=%x total=%d cookie=%d", + core->bl_fifo[fifo_idx].bl_tag, + req->data->cmd_arrary_count, + req->data->cookie); + + node = kzalloc(sizeof(struct cam_cdm_bl_cb_request_entry), + GFP_KERNEL); + if (!node) { + rc = -ENOMEM; + goto end; + } + + if (core->offsets->reg_data->num_bl_fifo > 1) + bit_wr_enable = true; + + node->request_type = CAM_HW_CDM_BL_CB_CLIENT; + node->client_hdl = req->handle; + node->cookie = req->data->cookie; + node->bl_tag = core->bl_fifo[fifo_idx].bl_tag; + node->userdata = req->data->userdata; + list_add_tail(&node->entry, &core->bl_fifo[fifo_idx].bl_request_list); + len = core->ops->cdm_required_size_genirq() * + core->bl_fifo[fifo_idx].bl_tag; + core->ops->cdm_write_genirq( + ((uint32_t *)core->gen_irq[fifo_idx].kmdvaddr + len), + core->bl_fifo[fifo_idx].bl_tag, + bit_wr_enable, fifo_idx); + rc = cam_hw_cdm_bl_write(cdm_hw, + (core->gen_irq[fifo_idx].vaddr + (4*len)), + ((4 * core->ops->cdm_required_size_genirq()) - 1), + core->bl_fifo[fifo_idx].bl_tag, + set_arb, fifo_idx); + if (rc) { + CAM_ERR(CAM_CDM, "CDM hw bl write failed for gen irq bltag=%d", + core->bl_fifo[fifo_idx].bl_tag); + list_del_init(&node->entry); + kfree(node); + node = NULL; + rc = -EIO; + goto end; + } + + if (cam_hw_cdm_commit_bl_write(cdm_hw, fifo_idx)) { + CAM_ERR(CAM_CDM, + "Cannot commit the genirq BL with tag tag=%d", + core->bl_fifo[fifo_idx].bl_tag); + list_del_init(&node->entry); + kfree(node); + node = NULL; + rc = -EIO; + } + + trace_cam_log_event("CDM_START", "CDM_START_IRQ", req->data->cookie, 0); + +end: + return rc; +} + +int cam_hw_cdm_submit_debug_gen_irq( + struct cam_hw_info *cdm_hw, + uint32_t fifo_idx) +{ + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + uint32_t len; + int rc; + bool bit_wr_enable = false; + + CAM_DBG(CAM_CDM, + "CDM write BL last cmd tag=0x%x", + core->bl_fifo[fifo_idx].bl_tag); + + if (core->offsets->reg_data->num_bl_fifo > 1) + bit_wr_enable = true; + + len = core->ops->cdm_required_size_genirq() * + core->bl_fifo[fifo_idx].bl_tag; + core->ops->cdm_write_genirq( + ((uint32_t *)core->gen_irq[fifo_idx].kmdvaddr + len), + CAM_CDM_DBG_GEN_IRQ_USR_DATA, bit_wr_enable, fifo_idx); + rc = cam_hw_cdm_bl_write(cdm_hw, + (core->gen_irq[fifo_idx].vaddr + (4*len)), + ((4 * core->ops->cdm_required_size_genirq()) - 1), + core->bl_fifo[fifo_idx].bl_tag, + false, fifo_idx); + if (rc) { + CAM_ERR(CAM_CDM, + "CDM hw bl write failed for dbggenirq USRdata=%d tag 0x%x", + CAM_CDM_DBG_GEN_IRQ_USR_DATA, + core->bl_fifo[fifo_idx].bl_tag); + rc = -EIO; + goto end; + } + if (cam_hw_cdm_commit_bl_write(cdm_hw, fifo_idx)) { + CAM_ERR(CAM_CDM, + "Cannot commit the dbggenirq BL with tag tag=0x%x", + core->bl_fifo[fifo_idx].bl_tag); + rc = -EIO; + goto end; + } + +end: + return rc; +} + +static int cam_hw_cdm_arb_submit_bl(struct cam_hw_info *cdm_hw, + struct cam_cdm_hw_intf_cmd_submit_bl *req, int i, + uint32_t fifo_idx, dma_addr_t hw_vaddr_ptr) +{ + struct cam_cdm_bl_request *cdm_cmd = req->data; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + uintptr_t cpu_addr; + struct cam_cdm_bl_cb_request_entry *node; + int rc = 0; + size_t len = 0; + + node = kzalloc(sizeof( + struct cam_cdm_bl_cb_request_entry), + GFP_KERNEL); + if (!node) + return -ENOMEM; + + node->request_type = CAM_HW_CDM_BL_CB_CLIENT; + node->client_hdl = req->handle; + node->cookie = req->data->cookie; + node->bl_tag = core->bl_fifo[fifo_idx].bl_tag - + 1; + node->userdata = req->data->userdata; + list_add_tail(&node->entry, + &core->bl_fifo[fifo_idx] + .bl_request_list); + cdm_cmd->cmd[i].arbitrate = 1; + rc = cam_mem_get_cpu_buf( + cdm_cmd->cmd[i].bl_addr.mem_handle, + &cpu_addr, &len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buffailed %x", + cdm_cmd->cmd[i].bl_addr + .mem_handle); + return rc; + } + core->ops->cdm_write_genirq( + ((uint32_t *)cpu_addr + + cdm_cmd->cmd[i].offset / 4 + + cdm_cmd->cmd[i].len / 4), + core->bl_fifo[fifo_idx].bl_tag - 1, + 1, fifo_idx); + rc = cam_hw_cdm_bl_write(cdm_hw, + (uint32_t)hw_vaddr_ptr + + cdm_cmd->cmd[i].offset, + cdm_cmd->cmd[i].len + 7, + core->bl_fifo[fifo_idx].bl_tag - 1, + 1, fifo_idx); + if (rc) { + CAM_ERR(CAM_CDM, + "CDM hw bl write failed tag=%d", + core->bl_fifo[fifo_idx].bl_tag - + 1); + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); + list_del_init(&node->entry); + kfree(node); + return -EIO; + } + rc = cam_hw_cdm_commit_bl_write(cdm_hw, + fifo_idx); + if (rc) { + CAM_ERR(CAM_CDM, + "CDM hw commit failed tag=%d", + core->bl_fifo[fifo_idx].bl_tag - + 1); + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); + list_del_init(&node->entry); + kfree(node); + return -EIO; + } + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); + return 0; +} + +int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, + struct cam_cdm_hw_intf_cmd_submit_bl *req, + struct cam_cdm_client *client) +{ + int i, rc; + struct cam_cdm_bl_request *cdm_cmd = req->data; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + struct cam_cdm_bl_fifo *bl_fifo = NULL; + uint32_t pending_bl = 0, fifo_idx = 0; + int write_count = 0; + + fifo_idx = CAM_CDM_GET_BLFIFO_IDX(client->handle); + + if (fifo_idx >= CAM_CDM_BL_FIFO_MAX) { + rc = -EINVAL; + CAM_ERR(CAM_CDM, "Invalid handle 0x%x, rc = %d", + client->handle, rc); + goto end; + } + + bl_fifo = &core->bl_fifo[fifo_idx]; + + if (req->data->cmd_arrary_count > bl_fifo->bl_depth) { + CAM_INFO(CAM_CDM, + "requested BL more than max size, cnt=%d max=%d", + req->data->cmd_arrary_count, + bl_fifo->bl_depth); + } + + + mutex_lock(&core->bl_fifo[fifo_idx].fifo_lock); + mutex_lock(&client->lock); + + if (test_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status) || + test_bit(CAM_CDM_RESET_HW_STATUS, &core->cdm_status)) { + mutex_unlock(&client->lock); + mutex_unlock(&core->bl_fifo[fifo_idx].fifo_lock); + return -EAGAIN; + } + + rc = cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo(cdm_hw, + fifo_idx, &pending_bl); + + if (rc) { + CAM_ERR(CAM_CDM, "Cannot read the current BL depth"); + mutex_unlock(&client->lock); + mutex_unlock(&core->bl_fifo[fifo_idx].fifo_lock); + return rc; + } + + for (i = 0; i < req->data->cmd_arrary_count ; i++) { + dma_addr_t hw_vaddr_ptr = 0; + size_t len = 0; + + if ((!cdm_cmd->cmd[i].len) && + (cdm_cmd->cmd[i].len > 0x100000)) { + CAM_ERR(CAM_CDM, + "cmd len(%d) is invalid cnt=%d total cnt=%d", + cdm_cmd->cmd[i].len, i, + req->data->cmd_arrary_count); + rc = -EINVAL; + break; + } + if (test_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status) || + test_bit(CAM_CDM_RESET_HW_STATUS, + &core->cdm_status)) { + CAM_ERR_RATE_LIMIT(CAM_CDM, + "In error/reset state cnt=%d total cnt=%d cdm_status 0x%x", + i, req->data->cmd_arrary_count, + core->cdm_status); + rc = -EAGAIN; + break; + } + if (write_count == 0) { + write_count = cam_hw_cdm_wait_for_bl_fifo(cdm_hw, + (req->data->cmd_arrary_count - i), fifo_idx); + if (write_count < 0) { + CAM_ERR(CAM_CDM, + "wait for bl fifo failed %d:%d", + i, req->data->cmd_arrary_count); + rc = -EIO; + break; + } + } + + if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) { + rc = cam_mem_get_io_buf( + cdm_cmd->cmd[i].bl_addr.mem_handle, + core->iommu_hdl.non_secure, &hw_vaddr_ptr, + &len); + } else if (req->data->type == CAM_CDM_BL_CMD_TYPE_HW_IOVA) { + if (!cdm_cmd->cmd[i].bl_addr.hw_iova) { + CAM_ERR(CAM_CDM, + "Hw bl hw_iova is invalid %d:%d", + i, req->data->cmd_arrary_count); + rc = -EINVAL; + break; + } + rc = 0; + hw_vaddr_ptr = + (uint64_t)cdm_cmd->cmd[i].bl_addr.hw_iova; + len = cdm_cmd->cmd[i].len + cdm_cmd->cmd[i].offset; + } else { + CAM_ERR(CAM_CDM, + "Only mem hdl/hw va type is supported %d", + req->data->type); + rc = -EINVAL; + break; + } + + if ((!rc) && (hw_vaddr_ptr) && (len) && + (len >= cdm_cmd->cmd[i].offset)) { + + if ((len - cdm_cmd->cmd[i].offset) < + cdm_cmd->cmd[i].len) { + CAM_ERR(CAM_CDM, + "Not enough buffer cmd offset: %u cmd length: %u", + cdm_cmd->cmd[i].offset, + cdm_cmd->cmd[i].len); + rc = -EINVAL; + break; + } + + CAM_DBG(CAM_CDM, "Got the HW VA"); + if (core->bl_fifo[fifo_idx].bl_tag >= + (bl_fifo->bl_depth - 1)) + core->bl_fifo[fifo_idx].bl_tag = 0; + if (core->arbitration == + CAM_CDM_ARBITRATION_PRIORITY_BASED && + (req->data->flag == true) && + (i == (req->data->cmd_arrary_count - + 1))) { + CAM_DBG(CAM_CDM, + "GenIRQ in same bl, will sumbit later"); + } else { + rc = cam_hw_cdm_bl_write(cdm_hw, + ((uint32_t)hw_vaddr_ptr + + cdm_cmd->cmd[i].offset), + (cdm_cmd->cmd[i].len - 1), + core->bl_fifo[fifo_idx].bl_tag, + cdm_cmd->cmd[i].arbitrate, + fifo_idx); + if (rc) { + CAM_ERR(CAM_CDM, + "Hw bl write failed %d:%d", + i, req->data->cmd_arrary_count); + rc = -EIO; + break; + } + } + } else { + CAM_ERR(CAM_CDM, + "Sanity check failed for hdl=%x len=%zu:%d", + cdm_cmd->cmd[i].bl_addr.mem_handle, len, + cdm_cmd->cmd[i].offset); + CAM_ERR(CAM_CDM, "Sanity check failed for %d:%d", + i, req->data->cmd_arrary_count); + rc = -EINVAL; + break; + } + + if (!rc) { + CAM_DBG(CAM_CDM, + "write BL done cnt=%d with tag=%d total_cnt=%d", + i, core->bl_fifo[fifo_idx].bl_tag, + req->data->cmd_arrary_count); + + if (core->arbitration == + CAM_CDM_ARBITRATION_PRIORITY_BASED && + (req->data->flag == true) && + (i == (req->data->cmd_arrary_count - + 1))) { + CAM_DBG(CAM_CDM, + "GenIRQ in same blcommit later"); + } else { + CAM_DBG(CAM_CDM, "Now commit the BL"); + if (cam_hw_cdm_commit_bl_write(cdm_hw, + fifo_idx)) { + CAM_ERR(CAM_CDM, + "commit failed BL %d tag=%d", + i, core->bl_fifo[fifo_idx] + .bl_tag); + rc = -EIO; + break; + } + write_count--; + CAM_DBG(CAM_CDM, "commit success BL %d tag=%d", + i, core->bl_fifo[fifo_idx].bl_tag); + } + core->bl_fifo[fifo_idx].bl_tag++; + + if (cdm_cmd->cmd[i].enable_debug_gen_irq) { + if (write_count == 0) { + write_count = + cam_hw_cdm_wait_for_bl_fifo( + cdm_hw, 1, fifo_idx); + if (write_count < 0) { + CAM_ERR(CAM_CDM, + "wait for bl fifo failed %d:%d", + i, req->data->cmd_arrary_count); + rc = -EIO; + break; + } + } + + rc = cam_hw_cdm_submit_debug_gen_irq(cdm_hw, + fifo_idx); + if (rc == 0) { + write_count--; + core->bl_fifo[fifo_idx].bl_tag++; + } + if (core->bl_fifo[fifo_idx].bl_tag >= + (bl_fifo->bl_depth - + 1)) + core->bl_fifo[fifo_idx].bl_tag = 0; + } + + if ((!rc) && (req->data->flag == true) && + (i == (req->data->cmd_arrary_count - + 1))) { + + if (write_count == 0) { + write_count = + cam_hw_cdm_wait_for_bl_fifo( + cdm_hw, 1, fifo_idx); + if (write_count < 0) { + CAM_ERR(CAM_CDM, + "wait for bl fifo failed %d:%d", + i, req->data->cmd_arrary_count); + rc = -EIO; + break; + } + } + + if (core->arbitration != + CAM_CDM_ARBITRATION_PRIORITY_BASED) { + + rc = cam_hw_cdm_submit_gen_irq( + cdm_hw, req, fifo_idx, + cdm_cmd->gen_irq_arb); + if (rc == 0) + core->bl_fifo[fifo_idx] + .bl_tag++; + break; + } + + rc = cam_hw_cdm_arb_submit_bl(cdm_hw, req, i, + fifo_idx, hw_vaddr_ptr); + if (rc) + break; + } + } + } + mutex_unlock(&client->lock); + mutex_unlock(&core->bl_fifo[fifo_idx].fifo_lock); + +end: + return rc; + +} + +static void cam_hw_cdm_reset_cleanup( + struct cam_hw_info *cdm_hw, + uint32_t handle) +{ + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + int i; + struct cam_cdm_bl_cb_request_entry *node, *tnode; + bool flush_hw = false; + bool reset_err = false; + + if (test_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status) || + test_bit(CAM_CDM_FLUSH_HW_STATUS, &core->cdm_status)) + flush_hw = true; + + if (test_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status)) + reset_err = true; + + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) { + list_for_each_entry_safe(node, tnode, + &core->bl_fifo[i].bl_request_list, entry) { + if (node->request_type == + CAM_HW_CDM_BL_CB_CLIENT) { + CAM_DBG(CAM_CDM, + "Notifying client %d for tag %d", + node->client_hdl, node->bl_tag); + if (flush_hw) { + enum cam_cdm_cb_status status; + + status = reset_err ? + CAM_CDM_CB_STATUS_HW_ERROR : + CAM_CDM_CB_STATUS_HW_RESUBMIT; + + cam_cdm_notify_clients(cdm_hw, + (node->client_hdl == handle) ? + CAM_CDM_CB_STATUS_HW_FLUSH : + status, + (void *)node); + } + else + cam_cdm_notify_clients(cdm_hw, + CAM_CDM_CB_STATUS_HW_RESET_DONE, + (void *)node); + } + list_del_init(&node->entry); + kfree(node); + node = NULL; + } + core->bl_fifo[i].bl_tag = 0; + core->bl_fifo[i].last_bl_tag_done = -1; + atomic_set(&core->bl_fifo[i].work_record, 0); + } +} + +static void cam_hw_cdm_work(struct work_struct *work) +{ + struct cam_cdm_work_payload *payload; + struct cam_hw_info *cdm_hw; + struct cam_cdm *core; + int i, fifo_idx; + struct cam_cdm_bl_cb_request_entry *tnode = NULL; + struct cam_cdm_bl_cb_request_entry *node = NULL; + + payload = container_of(work, struct cam_cdm_work_payload, work); + if (!payload) { + CAM_ERR(CAM_CDM, "NULL payload"); + return; + } + + cdm_hw = payload->hw; + core = (struct cam_cdm *)cdm_hw->core_info; + fifo_idx = payload->fifo_idx; + if (fifo_idx >= core->offsets->reg_data->num_bl_fifo) { + CAM_ERR(CAM_CDM, "Invalid fifo idx %d", + fifo_idx); + kfree(payload); + payload = NULL; + return; + } + + cam_req_mgr_thread_switch_delay_detect( + payload->workq_scheduled_ts); + + CAM_DBG(CAM_CDM, "IRQ status=0x%x", payload->irq_status); + if (payload->irq_status & + CAM_CDM_IRQ_STATUS_INLINE_IRQ_MASK) { + CAM_DBG(CAM_CDM, "inline IRQ data=0x%x last tag: 0x%x", + payload->irq_data, + core->bl_fifo[payload->fifo_idx] + .last_bl_tag_done); + + if (payload->irq_data == 0xff) { + CAM_INFO(CAM_CDM, "Debug genirq received"); + kfree(payload); + payload = NULL; + return; + } + + mutex_lock(&cdm_hw->hw_mutex); + mutex_lock(&core->bl_fifo[fifo_idx].fifo_lock); + + if (atomic_read(&core->bl_fifo[fifo_idx].work_record)) + atomic_dec( + &core->bl_fifo[fifo_idx].work_record); + + if (list_empty(&core->bl_fifo[fifo_idx] + .bl_request_list)) { + CAM_INFO(CAM_CDM, + "Fifo list empty, idx %d tag %d arb %d", + fifo_idx, payload->irq_data, + core->arbitration); + mutex_unlock(&core->bl_fifo[fifo_idx] + .fifo_lock); + mutex_unlock(&cdm_hw->hw_mutex); + return; + } + + if (core->bl_fifo[fifo_idx] + .last_bl_tag_done != + payload->irq_data) { + core->bl_fifo[fifo_idx] + .last_bl_tag_done = + payload->irq_data; + list_for_each_entry_safe(node, tnode, + &core->bl_fifo[fifo_idx] + .bl_request_list, + entry) { + if (node->request_type == + CAM_HW_CDM_BL_CB_CLIENT) { + cam_cdm_notify_clients(cdm_hw, + CAM_CDM_CB_STATUS_BL_SUCCESS, + (void *)node); + } else if (node->request_type == + CAM_HW_CDM_BL_CB_INTERNAL) { + CAM_ERR(CAM_CDM, + "Invalid node=%pK %d", + node, + node->request_type); + } + list_del_init(&node->entry); + if (node->bl_tag == payload->irq_data) { + kfree(node); + node = NULL; + break; + } + kfree(node); + node = NULL; + } + } else { + CAM_INFO(CAM_CDM, + "Skip GenIRQ, tag 0x%x fifo %d", + payload->irq_data, payload->fifo_idx); + } + mutex_unlock(&core->bl_fifo[payload->fifo_idx] + .fifo_lock); + mutex_unlock(&cdm_hw->hw_mutex); + } + + if (payload->irq_status & + CAM_CDM_IRQ_STATUS_BL_DONE_MASK) { + if (test_bit(payload->fifo_idx, &core->cdm_status)) { + CAM_DBG(CAM_CDM, "CDM HW BL done IRQ"); + complete(&core->bl_fifo[payload->fifo_idx] + .bl_complete); + } + } + if (payload->irq_status & + CAM_CDM_IRQ_STATUS_ERRORS) { + int reset_hw_hdl = 0x0; + + CAM_ERR_RATE_LIMIT(CAM_CDM, + "CDM Error IRQ status %d\n", + payload->irq_status); + set_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status); + mutex_lock(&cdm_hw->hw_mutex); + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; + i++) + mutex_lock(&core->bl_fifo[i].fifo_lock); + /* + * First pause CDM, If it fails still proceed + * to dump debug info + */ + cam_hw_cdm_pause_core(cdm_hw, true); + cam_hw_cdm_dump_core_debug_registers(cdm_hw, true); + + if (payload->irq_status & + CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK) { + node = list_first_entry_or_null( + &core->bl_fifo[payload->fifo_idx].bl_request_list, + struct cam_cdm_bl_cb_request_entry, entry); + + if (node != NULL) { + if (node->request_type == + CAM_HW_CDM_BL_CB_CLIENT) { + cam_cdm_notify_clients(cdm_hw, + CAM_CDM_CB_STATUS_INVALID_BL_CMD, + (void *)node); + } else if (node->request_type == + CAM_HW_CDM_BL_CB_INTERNAL) { + CAM_ERR(CAM_CDM, + "Invalid node=%pK %d", node, + node->request_type); + } + list_del_init(&node->entry); + kfree(node); + } + } + /* Resume CDM back */ + cam_hw_cdm_pause_core(cdm_hw, false); + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; + i++) + mutex_unlock(&core->bl_fifo[i].fifo_lock); + + if (payload->irq_status & + CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK) + cam_hw_cdm_reset_hw(cdm_hw, reset_hw_hdl); + + mutex_unlock(&cdm_hw->hw_mutex); + if (!(payload->irq_status & + CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK)) + clear_bit(CAM_CDM_ERROR_HW_STATUS, + &core->cdm_status); + } else { + CAM_ERR(CAM_CDM, "NULL payload"); + } + kfree(payload); + payload = NULL; + +} + +static void cam_hw_cdm_iommu_fault_handler(struct iommu_domain *domain, + struct device *dev, unsigned long iova, int flags, void *token, + uint32_t buf_info) +{ + struct cam_hw_info *cdm_hw = NULL; + struct cam_cdm *core = NULL; + int i; + + if (token) { + cdm_hw = (struct cam_hw_info *)token; + core = (struct cam_cdm *)cdm_hw->core_info; + set_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status); + mutex_lock(&cdm_hw->hw_mutex); + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) + mutex_lock(&core->bl_fifo[i].fifo_lock); + if (cdm_hw->hw_state == CAM_HW_STATE_POWER_UP) { + cam_hw_cdm_dump_core_debug_registers(cdm_hw, true); + } else + CAM_INFO(CAM_CDM, "CDM hw is power in off state"); + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) + mutex_unlock(&core->bl_fifo[i].fifo_lock); + + CAM_ERR_RATE_LIMIT(CAM_CDM, "Page fault iova addr %pK", + (void *)iova); + cam_cdm_notify_clients(cdm_hw, CAM_CDM_CB_STATUS_PAGEFAULT, + (void *)iova); + mutex_unlock(&cdm_hw->hw_mutex); + clear_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status); + } else { + CAM_ERR(CAM_CDM, "Invalid token"); + } + +} + +irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) +{ + struct cam_hw_info *cdm_hw = data; + struct cam_cdm *cdm_core = cdm_hw->core_info; + struct cam_cdm_work_payload *payload[CAM_CDM_BL_FIFO_MAX] = {0}; + uint32_t user_data = 0; + uint32_t irq_status[CAM_CDM_BL_FIFO_MAX] = {0}; + uint32_t irq_context_summary = 0xF; + bool work_status; + int i; + + CAM_DBG(CAM_CDM, "Got irq hw_version 0x%x", cdm_core->hw_version); + spin_lock(&cdm_hw->hw_lock); + if (cdm_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_DBG(CAM_CDM, "CDM is in power down state"); + spin_unlock(&cdm_hw->hw_lock); + return IRQ_HANDLED; + } + if (cdm_core->hw_version >= CAM_CDM_VERSION_2_1) { + if (cam_cdm_read_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->irq_context_status, + &irq_context_summary)) { + CAM_ERR(CAM_CDM, "Failed to read CDM HW IRQ status"); + } + } + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo_irq; i++) { + if (!(BIT(i) & irq_context_summary)) + continue; + + if (cam_cdm_read_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_status, + &irq_status[i])) { + CAM_ERR(CAM_CDM, "Failed to read CDM HW IRQ status"); + } + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_clear, + irq_status[i])) { + CAM_ERR(CAM_CDM, "Failed to write CDM HW IRQ clear"); + } + } + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[0]->irq_clear_cmd, + 0x01)) + CAM_ERR(CAM_CDM, "Failed to Write CDM HW IRQ clr cmd"); + if (cam_cdm_read_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->usr_data, + &user_data)) + CAM_ERR(CAM_CDM, "Failed to read CDM HW IRQ data"); + spin_unlock(&cdm_hw->hw_lock); + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo_irq; i++) { + if (!irq_status[i]) + continue; + + if (irq_status[i] & CAM_CDM_IRQ_STATUS_RST_DONE_MASK) { + cdm_core->rst_done_cnt++; + continue; + } + + payload[i] = kzalloc(sizeof(struct cam_cdm_work_payload), + GFP_ATOMIC); + + if (!payload[i]) { + CAM_ERR(CAM_CDM, + "failed to allocate memory for fifo %d payload", + i); + continue; + } + if (irq_status[i] & + CAM_CDM_IRQ_STATUS_INLINE_IRQ_MASK) { + payload[i]->irq_data = (user_data >> (i * 0x8)) & + CAM_CDM_IRQ_STATUS_USR_DATA_MASK; + } + + CAM_DBG(CAM_CDM, + "Rcvd of fifo %d userdata 0x%x tag 0x%x irq_stat 0x%x", + i, user_data, payload[i]->irq_data, irq_status[i]); + + payload[i]->fifo_idx = i; + payload[i]->irq_status = irq_status[i]; + payload[i]->hw = cdm_hw; + + INIT_WORK((struct work_struct *)&payload[i]->work, + cam_hw_cdm_work); + + trace_cam_log_event("CDM_DONE", "CDM_DONE_IRQ", + payload[i]->irq_status, + cdm_hw->soc_info.index); + + atomic_inc(&cdm_core->bl_fifo[i].work_record); + payload[i]->workq_scheduled_ts = ktime_get(); + + work_status = queue_work( + cdm_core->bl_fifo[i].work_queue, + &payload[i]->work); + + if (work_status == false) { + CAM_ERR(CAM_CDM, + "Failed to queue work for FIFO: %d irq=0x%x", + i, payload[i]->irq_status); + kfree(payload[i]); + payload[i] = NULL; + } + } + if (cdm_core->rst_done_cnt == + cdm_core->offsets->reg_data->num_bl_fifo_irq) { + CAM_DBG(CAM_CDM, "CDM HW reset done IRQ"); + complete(&cdm_core->reset_complete); + } + if (cdm_core->rst_done_cnt && + cdm_core->rst_done_cnt != + cdm_core->offsets->reg_data->num_bl_fifo_irq) + CAM_INFO(CAM_CDM, + "Reset IRQ received for %d fifos instead of %d", + cdm_core->rst_done_cnt, + cdm_core->offsets->reg_data->num_bl_fifo_irq); + return IRQ_HANDLED; +} + +int cam_hw_cdm_alloc_genirq_mem(void *hw_priv) +{ + struct cam_hw_info *cdm_hw = hw_priv; + struct cam_mem_mgr_request_desc genirq_alloc_cmd; + struct cam_mem_mgr_memory_desc genirq_alloc_out; + struct cam_cdm *cdm_core = NULL; + int rc = -EINVAL, i; + + if (!hw_priv) + return rc; + + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + genirq_alloc_cmd.align = 0; + genirq_alloc_cmd.smmu_hdl = cdm_core->iommu_hdl.non_secure; + genirq_alloc_cmd.flags = CAM_MEM_FLAG_HW_READ_WRITE; + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + genirq_alloc_cmd.size = (8 * + cdm_core->bl_fifo[i].bl_depth); + rc = cam_mem_mgr_request_mem(&genirq_alloc_cmd, + &genirq_alloc_out); + if (rc) { + CAM_ERR(CAM_CDM, + "Failed to get genirq cmd space rc=%d", + rc); + goto end; + } + cdm_core->gen_irq[i].handle = genirq_alloc_out.mem_handle; + cdm_core->gen_irq[i].vaddr = (genirq_alloc_out.iova & + 0xFFFFFFFF); + cdm_core->gen_irq[i].kmdvaddr = genirq_alloc_out.kva; + cdm_core->gen_irq[i].size = genirq_alloc_out.len; + } +end: + return rc; +} + +int cam_hw_cdm_release_genirq_mem(void *hw_priv) +{ + struct cam_hw_info *cdm_hw = hw_priv; + struct cam_cdm *cdm_core = NULL; + struct cam_mem_mgr_memory_desc genirq_release_cmd; + int rc = -EINVAL, i; + + if (!hw_priv) + return rc; + + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + genirq_release_cmd.mem_handle = cdm_core->gen_irq[i].handle; + rc = cam_mem_mgr_release_mem(&genirq_release_cmd); + if (rc) + CAM_ERR(CAM_CDM, + "Failed to put genirq cmd space for hw rc %d", + rc); + } + + return rc; +} + +int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle) +{ + struct cam_cdm *cdm_core = NULL; + long time_left; + int i, rc = -EIO; + int reset_val = 1; + + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); + + set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + cdm_core->rst_done_cnt = 0; + reinit_completion(&cdm_core->reset_complete); + + /* First pause CDM, If it fails still proceed to reset CDM HW */ + cam_hw_cdm_pause_core(cdm_hw, true); + usleep_range(1000, 1010); + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + reset_val = reset_val | + (1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT)); + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_mask, + 0x70003)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW IRQ mask"); + goto end; + } + } + + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->rst_cmd, reset_val)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW reset"); + goto end; + } + + CAM_DBG(CAM_CDM, "Waiting for CDM HW reset done"); + time_left = wait_for_completion_timeout(&cdm_core->reset_complete, + msecs_to_jiffies(CAM_CDM_HW_RESET_TIMEOUT)); + + if (time_left <= 0) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_CDM, "CDM HW reset Wait failed rc=%d", rc); + goto end; + } + + rc = cam_hw_cdm_set_cdm_core_cfg(cdm_hw); + if (rc) { + CAM_ERR(CAM_CDM, "Failed to configure CDM rc=%d", rc); + goto end; + } + + rc = cam_hw_cdm_set_cdm_blfifo_cfg(cdm_hw); + if (rc) { + CAM_ERR(CAM_CDM, "Failed to configure CDM fifo rc=%d", rc); + goto end; + } + + cam_hw_cdm_reset_cleanup(cdm_hw, handle); +end: + clear_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_unlock(&cdm_core->bl_fifo[i].fifo_lock); + + return rc; +} + +int cam_hw_cdm_handle_error_info( + struct cam_hw_info *cdm_hw, + uint32_t handle) +{ + struct cam_cdm *cdm_core = NULL; + struct cam_cdm_bl_cb_request_entry *node = NULL; + long time_left; + int i, rc = -EIO, reset_hw_hdl = 0x0; + uint32_t current_bl_data = 0, current_fifo = 0, current_tag = 0; + int reset_val = 1; + + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); + + cdm_core->rst_done_cnt = 0; + reinit_completion(&cdm_core->reset_complete); + set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + set_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); + + if (cdm_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_WARN(CAM_CDM, "CDM is in power down state"); + goto end; + } + + /* First pause CDM, If it fails still proceed to dump debug info */ + cam_hw_cdm_pause_core(cdm_hw, true); + + rc = cam_cdm_read_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->current_bl_len, + ¤t_bl_data); + + current_fifo = ((CAM_CDM_CURRENT_BL_FIFO & current_bl_data) + >> CAM_CDM_CURRENT_BL_FIFO_SHIFT); + current_tag = ((CAM_CDM_CURRENT_BL_TAG & current_bl_data) + >> CAM_CDM_CURRENT_BL_TAG_SHIFT); + + if (current_fifo >= CAM_CDM_BL_FIFO_MAX) { + rc = -EFAULT; + goto end; + } + + CAM_ERR(CAM_CDM, "Hang detected for fifo %d with tag 0x%x", + current_fifo, current_tag); + + /* dump cdm registers for further debug */ + cam_hw_cdm_dump_core_debug_registers(cdm_hw, false); + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + reset_val = reset_val | + (1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT)); + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_mask, + 0x70003)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW IRQ mask"); + goto end; + } + } + + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->rst_cmd, reset_val)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW reset"); + goto end; + } + + CAM_DBG(CAM_CDM, "Waiting for CDM HW resetdone"); + time_left = wait_for_completion_timeout(&cdm_core->reset_complete, + msecs_to_jiffies(CAM_CDM_HW_RESET_TIMEOUT)); + + if (time_left <= 0) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_CDM, "CDM HW reset Wait failed rc=%d", rc); + set_bit(CAM_CDM_RESET_ERR_STATUS, &cdm_core->cdm_status); + } + + rc = cam_hw_cdm_set_cdm_core_cfg(cdm_hw); + + if (rc) { + CAM_ERR(CAM_CDM, "Failed to configure CDM rc=%d", rc); + goto end; + } + + rc = cam_hw_cdm_set_cdm_blfifo_cfg(cdm_hw); + + if (rc) { + CAM_ERR(CAM_CDM, "Failed to configure CDM fifo rc=%d", rc); + goto end; + } + + node = list_first_entry_or_null( + &cdm_core->bl_fifo[current_fifo].bl_request_list, + struct cam_cdm_bl_cb_request_entry, entry); + + if (node != NULL) { + if (node->request_type == CAM_HW_CDM_BL_CB_CLIENT) { + cam_cdm_notify_clients(cdm_hw, + CAM_CDM_CB_STATUS_HW_ERROR, + (void *)node); + } else if (node->request_type == CAM_HW_CDM_BL_CB_INTERNAL) { + CAM_ERR(CAM_CDM, "Invalid node=%pK %d", node, + node->request_type); + } + list_del_init(&node->entry); + kfree(node); + node = NULL; + } + + cam_hw_cdm_reset_cleanup(cdm_hw, reset_hw_hdl); +end: + clear_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); + clear_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + clear_bit(CAM_CDM_RESET_ERR_STATUS, &cdm_core->cdm_status); + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_unlock(&cdm_core->bl_fifo[i].fifo_lock); + + return rc; +} + +int cam_hw_cdm_flush_hw(struct cam_hw_info *cdm_hw, uint32_t handle) +{ + struct cam_cdm *cdm_core = NULL; + int rc = 0; + + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + set_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); + rc = cam_hw_cdm_reset_hw(cdm_hw, handle); + clear_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); + + return rc; +} + +int cam_hw_cdm_handle_error( + struct cam_hw_info *cdm_hw, + uint32_t handle) +{ + struct cam_cdm *cdm_core = NULL; + int rc = 0; + + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + rc = cam_hw_cdm_handle_error_info(cdm_hw, handle); + + return rc; +} + +int cam_hw_cdm_hang_detect( + struct cam_hw_info *cdm_hw, + uint32_t handle) +{ + struct cam_cdm *cdm_core = NULL; + int i, rc = -1; + + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + if (atomic_read(&cdm_core->bl_fifo[i].work_record)) { + CAM_WARN(CAM_CDM, + "workqueue got delayed, work_record :%u", + atomic_read(&cdm_core->bl_fifo[i].work_record)); + rc = 0; + break; + } + + return rc; +} + +int cam_hw_cdm_get_cdm_config(struct cam_hw_info *cdm_hw) +{ + struct cam_hw_soc_info *soc_info = NULL; + struct cam_cdm *core = NULL; + int rc = 0; + + core = (struct cam_cdm *)cdm_hw->core_info; + soc_info = &cdm_hw->soc_info; + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_SVS_VOTE, true); + if (rc) { + CAM_ERR(CAM_CDM, "Enable platform failed for dev %s", + soc_info->dev_name); + goto end; + } else { + CAM_DBG(CAM_CDM, "CDM init success"); + cdm_hw->hw_state = CAM_HW_STATE_POWER_UP; + } + + if (cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->cdm_hw_version, + &core->hw_version)) { + CAM_ERR(CAM_CDM, "Failed to read CDM HW Version"); + rc = -EIO; + goto disable_platform_resource; + } + + if (core->offsets->cmn_reg->cam_version) { + if (cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->cam_version->hw_version, + &core->hw_family_version)) { + CAM_ERR(CAM_CDM, "Failed to read CDM family Version"); + rc = -EIO; + goto disable_platform_resource; + } + } + + CAM_DBG(CAM_CDM, + "CDM Hw version read success family =%x hw =%x", + core->hw_family_version, core->hw_version); + + core->ops = cam_cdm_get_ops(core->hw_version, NULL, + false); + + if (!core->ops) { + CAM_ERR(CAM_CDM, "Failed to util ops for cdm hw name %s", + core->name); + rc = -EINVAL; + goto disable_platform_resource; + } + +disable_platform_resource: + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + + if (rc) { + CAM_ERR(CAM_CDM, "disable platform failed for dev %s", + soc_info->dev_name); + } else { + CAM_DBG(CAM_CDM, "CDM Deinit success"); + cdm_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + } +end: + return rc; +} + +int cam_hw_cdm_init(void *hw_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *cdm_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_cdm *cdm_core = NULL; + int rc, i, reset_hw_hdl = 0x0; + unsigned long flags; + + if (!hw_priv) + return -EINVAL; + + soc_info = &cdm_hw->soc_info; + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_SVS_VOTE, true); + if (rc) { + CAM_ERR(CAM_CDM, "Enable platform failed"); + goto end; + } + spin_lock_irqsave(&cdm_hw->hw_lock, flags); + cdm_hw->hw_state = CAM_HW_STATE_POWER_UP; + spin_unlock_irqrestore(&cdm_hw->hw_lock, flags); + + CAM_DBG(CAM_CDM, "Enable soc done"); + +/* Before triggering the reset to HW, clear the reset complete */ + clear_bit(CAM_CDM_ERROR_HW_STATUS, &cdm_core->cdm_status); + + for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) { + clear_bit(i, &cdm_core->cdm_status); + reinit_completion(&cdm_core->bl_fifo[i].bl_complete); + } + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + cdm_core->bl_fifo[i].last_bl_tag_done = -1; + atomic_set(&cdm_core->bl_fifo[i].work_record, 0); + } + + rc = cam_hw_cdm_reset_hw(cdm_hw, reset_hw_hdl); + + if (rc) { + CAM_ERR(CAM_CDM, "CDM HW reset Wait failed rc=%d", rc); + goto disable_return; + } else { + CAM_DBG(CAM_CDM, "CDM Init success"); + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_mask, + 0x70003); + rc = 0; + goto end; + } + +disable_return: + rc = -EIO; + spin_lock_irqsave(&cdm_hw->hw_lock, flags); + cdm_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + spin_unlock_irqrestore(&cdm_hw->hw_lock, flags); + cam_soc_util_disable_platform_resource(soc_info, true, true); +end: + return rc; +} + +int cam_hw_cdm_deinit(void *hw_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *cdm_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_cdm *cdm_core = NULL; + struct cam_cdm_bl_cb_request_entry *node, *tnode; + int rc = 0, i; + uint32_t reset_val = 1; + long time_left; + unsigned long flags; + + if (!hw_priv) + return -EINVAL; + + soc_info = &cdm_hw->soc_info; + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); + + /*clear bl request */ + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + list_for_each_entry_safe(node, tnode, + &cdm_core->bl_fifo[i].bl_request_list, entry) { + list_del_init(&node->entry); + kfree(node); + node = NULL; + } + } + + set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + cdm_core->rst_done_cnt = 0; + reinit_completion(&cdm_core->reset_complete); + + /* First pause CDM, If it fails still proceed to reset CDM HW */ + cam_hw_cdm_pause_core(cdm_hw, true); + usleep_range(1000, 1010); + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + reset_val = reset_val | + (1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT)); + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_mask, + 0x70003)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW IRQ mask"); + } + } + + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->rst_cmd, reset_val)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW reset"); + } + + CAM_DBG(CAM_CDM, "Waiting for CDM HW reset done"); + time_left = wait_for_completion_timeout(&cdm_core->reset_complete, + msecs_to_jiffies(CAM_CDM_HW_RESET_TIMEOUT)); + + if (time_left <= 0) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_CDM, "CDM HW reset Wait failed rc=%d", rc); + } + + clear_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_unlock(&cdm_core->bl_fifo[i].fifo_lock); + + spin_lock_irqsave(&cdm_hw->hw_lock, flags); + cdm_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + spin_unlock_irqrestore(&cdm_hw->hw_lock, flags); + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) { + CAM_ERR(CAM_CDM, "disable platform failed"); + } else { + CAM_DBG(CAM_CDM, "CDM Deinit success"); + } + + return rc; +} + +int cam_hw_cdm_probe(struct platform_device *pdev) +{ + int rc, len = 0, i, j; + struct cam_hw_info *cdm_hw = NULL; + struct cam_hw_intf *cdm_hw_intf = NULL; + struct cam_cdm *cdm_core = NULL; + struct cam_cdm_private_dt_data *soc_private = NULL; + struct cam_cpas_register_params cpas_parms; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + char cdm_name[128], work_q_name[128]; + + cdm_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!cdm_hw_intf) + return -ENOMEM; + + cdm_hw = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!cdm_hw) { + kfree(cdm_hw_intf); + cdm_hw_intf = NULL; + return -ENOMEM; + } + + cdm_hw->core_info = kzalloc(sizeof(struct cam_cdm), GFP_KERNEL); + if (!cdm_hw->core_info) { + kfree(cdm_hw); + cdm_hw = NULL; + kfree(cdm_hw_intf); + cdm_hw_intf = NULL; + return -ENOMEM; + } + + cdm_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + cdm_hw->soc_info.pdev = pdev; + cdm_hw->soc_info.dev = &pdev->dev; + cdm_hw->soc_info.dev_name = pdev->name; + cdm_hw_intf->hw_type = CAM_HW_CDM; + cdm_hw->open_count = 0; + mutex_init(&cdm_hw->hw_mutex); + spin_lock_init(&cdm_hw->hw_lock); + init_completion(&cdm_hw->hw_complete); + + rc = cam_hw_cdm_soc_get_dt_properties(cdm_hw, msm_cam_hw_cdm_dt_match); + if (rc) { + CAM_ERR(CAM_CDM, "Failed to get dt properties"); + goto release_mem; + } + cdm_hw_intf->hw_idx = cdm_hw->soc_info.index; + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + soc_private = (struct cam_cdm_private_dt_data *) + cdm_hw->soc_info.soc_private; + if (soc_private->dt_cdm_shared == true) + cdm_core->flags = CAM_CDM_FLAG_SHARED_CDM; + else + cdm_core->flags = CAM_CDM_FLAG_PRIVATE_CDM; + + cdm_core->id = cam_hw_cdm_get_id_by_name(cdm_core->name); + + CAM_DBG(CAM_CDM, "cdm_name %s", cdm_core->name); + + if (cdm_core->id >= CAM_CDM_MAX) { + CAM_ERR(CAM_CDM, "Failed to get CDM HW name for %s", + cdm_core->name); + goto release_private_mem; + } + + cdm_core->rst_done_cnt = 0; + init_completion(&cdm_core->reset_complete); + cdm_hw_intf->hw_priv = cdm_hw; + cdm_hw_intf->hw_ops.get_hw_caps = cam_cdm_get_caps; + cdm_hw_intf->hw_ops.init = cam_hw_cdm_init; + cdm_hw_intf->hw_ops.deinit = cam_hw_cdm_deinit; + cdm_hw_intf->hw_ops.start = cam_cdm_stream_start; + cdm_hw_intf->hw_ops.stop = cam_cdm_stream_stop; + cdm_hw_intf->hw_ops.read = NULL; + cdm_hw_intf->hw_ops.write = NULL; + cdm_hw_intf->hw_ops.process_cmd = cam_cdm_process_cmd; + mutex_lock(&cdm_hw->hw_mutex); + + CAM_DBG(CAM_CDM, "type %d index %d", cdm_hw_intf->hw_type, + cdm_hw_intf->hw_idx); + + platform_set_drvdata(pdev, cdm_hw_intf); + + snprintf(cdm_name, sizeof(cdm_name), "%s%d", + cdm_hw->soc_info.label_name, cdm_hw->soc_info.index); + + rc = cam_smmu_get_handle(cdm_name, &cdm_core->iommu_hdl.non_secure); + if (rc < 0) { + if (rc != -EALREADY) { + CAM_ERR(CAM_CDM, + "%s get iommu handle failed, rc = %d", + cdm_name, rc); + goto unlock_release_mem; + } + rc = 0; + } + + cam_smmu_set_client_page_fault_handler(cdm_core->iommu_hdl.non_secure, + cam_hw_cdm_iommu_fault_handler, cdm_hw); + + cdm_core->iommu_hdl.secure = -1; + + for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) { + INIT_LIST_HEAD(&cdm_core->bl_fifo[i].bl_request_list); + + mutex_init(&cdm_core->bl_fifo[i].fifo_lock); + + init_completion(&cdm_core->bl_fifo[i].bl_complete); + + len = strlcpy(work_q_name, cdm_core->name, + sizeof(cdm_core->name)); + snprintf(work_q_name + len, sizeof(work_q_name) - len, "%d", i); + cdm_core->bl_fifo[i].work_queue = alloc_workqueue(work_q_name, + WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, + CAM_CDM_INFLIGHT_WORKS); + if (!cdm_core->bl_fifo[i].work_queue) { + CAM_ERR(CAM_CDM, + "Workqueue allocation failed for FIFO %d, cdm %s", + i, cdm_core->name); + goto failed_workq_create; + } + + CAM_DBG(CAM_CDM, "wq %s", work_q_name); + } + + rc = cam_soc_util_request_platform_resource(&cdm_hw->soc_info, + cam_hw_cdm_irq, cdm_hw); + if (rc) { + CAM_ERR(CAM_CDM, "Failed to request platform resource"); + goto destroy_non_secure_hdl; + } + cpas_parms.cam_cpas_client_cb = cam_cdm_cpas_cb; + cpas_parms.cell_index = cdm_hw->soc_info.index; + cpas_parms.dev = &pdev->dev; + cpas_parms.userdata = cdm_hw_intf; + strlcpy(cpas_parms.identifier, cdm_hw->soc_info.label_name, + CAM_HW_IDENTIFIER_LENGTH); + rc = cam_cpas_register_client(&cpas_parms); + if (rc) { + CAM_ERR(CAM_CDM, "Virtual CDM CPAS registration failed"); + goto release_platform_resource; + } + CAM_DBG(CAM_CDM, "CPAS registration successful handle=%d", + cpas_parms.client_handle); + cdm_core->cpas_handle = cpas_parms.client_handle; + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_LOWSVS_VOTE; + axi_vote.num_paths = 1; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_READ; + axi_vote.axi_path[0].camnoc_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ab_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW; + + rc = cam_cpas_start(cdm_core->cpas_handle, &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_CDM, "CPAS start failed"); + goto cpas_unregister; + } + + rc = cam_hw_cdm_get_cdm_config(cdm_hw); + if (rc) { + CAM_ERR(CAM_CDM, "Failed to get cdm configuration rc = %d", rc); + goto cpas_stop; + } + + if (cdm_core->hw_version < CAM_CDM_VERSION_2_0) { + for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) { + cdm_core->bl_fifo[i].bl_depth = + CAM_CDM_BL_FIFO_LENGTH_MAX_DEFAULT; + CAM_DBG(CAM_CDM, "Setting FIFO%d length to %d", + i, cdm_core->bl_fifo[i].bl_depth); + } + } else { + for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) { + cdm_core->bl_fifo[i].bl_depth = + soc_private->fifo_depth[i]; + CAM_DBG(CAM_CDM, "Setting FIFO%d length to %d", + i, cdm_core->bl_fifo[i].bl_depth); + } + } + + cdm_core->arbitration = cam_cdm_get_arbitration_type( + cdm_core->hw_version, cdm_core->id); + + cdm_core->cdm_status = CAM_CDM_HW_INIT_STATUS; + + rc = cam_hw_cdm_init(cdm_hw, NULL, 0); + if (rc) { + CAM_ERR(CAM_CDM, "Failed to Init CDM HW"); + goto cpas_stop; + } + cdm_hw->open_count++; + + if (!cam_cdm_set_cam_hw_version(cdm_core->hw_version, + &cdm_core->version)) { + CAM_ERR(CAM_CDM, "Failed to set cam hw version for hw"); + rc = -EINVAL; + goto deinit; + } + + rc = cam_hw_cdm_deinit(cdm_hw, NULL, 0); + if (rc) { + CAM_ERR(CAM_CDM, "Failed to Deinit CDM HW"); + cdm_hw->open_count--; + goto cpas_stop; + } + + rc = cam_cpas_stop(cdm_core->cpas_handle); + if (rc) { + CAM_ERR(CAM_CDM, "CPAS stop failed"); + cdm_hw->open_count--; + goto cpas_unregister; + } + + rc = cam_cdm_intf_register_hw_cdm(cdm_hw_intf, + soc_private, CAM_HW_CDM, &cdm_core->index); + if (rc) { + CAM_ERR(CAM_CDM, "HW CDM Interface registration failed"); + cdm_hw->open_count--; + goto cpas_unregister; + } + cdm_hw->open_count--; + mutex_unlock(&cdm_hw->hw_mutex); + + CAM_DBG(CAM_CDM, "%s probe successful", cdm_core->name); + + return rc; + +deinit: + if (cam_hw_cdm_deinit(cdm_hw, NULL, 0)) + CAM_ERR(CAM_CDM, "Deinit failed for hw"); + cdm_hw->open_count--; +cpas_stop: + if (cam_cpas_stop(cdm_core->cpas_handle)) + CAM_ERR(CAM_CDM, "CPAS stop failed"); +cpas_unregister: + if (cam_cpas_unregister_client(cdm_core->cpas_handle)) + CAM_ERR(CAM_CDM, "CPAS unregister failed"); +release_platform_resource: + if (cam_soc_util_release_platform_resource(&cdm_hw->soc_info)) + CAM_ERR(CAM_CDM, "Release platform resource failed"); +failed_workq_create: + for (j = 0; j < i; j++) { + flush_workqueue(cdm_core->bl_fifo[j].work_queue); + destroy_workqueue(cdm_core->bl_fifo[j].work_queue); + } +destroy_non_secure_hdl: + cam_smmu_set_client_page_fault_handler(cdm_core->iommu_hdl.non_secure, + NULL, cdm_hw); + if (cam_smmu_destroy_handle(cdm_core->iommu_hdl.non_secure)) + CAM_ERR(CAM_CDM, "Release iommu secure hdl failed"); +unlock_release_mem: + mutex_unlock(&cdm_hw->hw_mutex); +release_private_mem: + kfree(cdm_hw->soc_info.soc_private); + cdm_hw->soc_info.soc_private = NULL; +release_mem: + mutex_destroy(&cdm_hw->hw_mutex); + kfree(cdm_hw_intf); + cdm_hw_intf = NULL; + kfree(cdm_hw->core_info); + cdm_hw->core_info = NULL; + kfree(cdm_hw); + cdm_hw = NULL; + return rc; +} + +int cam_hw_cdm_remove(struct platform_device *pdev) +{ + int rc = -EBUSY, i; + struct cam_hw_info *cdm_hw = NULL; + struct cam_hw_intf *cdm_hw_intf = NULL; + struct cam_cdm *cdm_core = NULL; + + cdm_hw_intf = platform_get_drvdata(pdev); + if (!cdm_hw_intf) { + CAM_ERR(CAM_CDM, "Failed to get dev private data"); + return rc; + } + + cdm_hw = cdm_hw_intf->hw_priv; + if (!cdm_hw) { + CAM_ERR(CAM_CDM, + "Failed to get hw private data for type=%d idx=%d", + cdm_hw_intf->hw_type, cdm_hw_intf->hw_idx); + return rc; + } + + cdm_core = cdm_hw->core_info; + if (!cdm_core) { + CAM_ERR(CAM_CDM, + "Failed to get hw core data for type=%d idx=%d", + cdm_hw_intf->hw_type, cdm_hw_intf->hw_idx); + return rc; + } + + if (cdm_hw->open_count != 0) { + CAM_ERR(CAM_CDM, "Hw open count invalid type=%d idx=%d cnt=%d", + cdm_hw_intf->hw_type, cdm_hw_intf->hw_idx, + cdm_hw->open_count); + return rc; + } + + rc = cam_hw_cdm_deinit(cdm_hw, NULL, 0); + if (rc) { + CAM_ERR(CAM_CDM, "Deinit failed for hw"); + return rc; + } + + rc = cam_cpas_unregister_client(cdm_core->cpas_handle); + if (rc) { + CAM_ERR(CAM_CDM, "CPAS unregister failed"); + return rc; + } + + if (cam_soc_util_release_platform_resource(&cdm_hw->soc_info)) + CAM_ERR(CAM_CDM, "Release platform resource failed"); + + for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) { + flush_workqueue(cdm_core->bl_fifo[i].work_queue); + destroy_workqueue(cdm_core->bl_fifo[i].work_queue); + } + + if (cam_smmu_destroy_handle(cdm_core->iommu_hdl.non_secure)) + CAM_ERR(CAM_CDM, "Release iommu secure hdl failed"); + cam_smmu_unset_client_page_fault_handler( + cdm_core->iommu_hdl.non_secure, cdm_hw); + + mutex_destroy(&cdm_hw->hw_mutex); + kfree(cdm_hw->soc_info.soc_private); + cdm_hw->soc_info.soc_private = NULL; + kfree(cdm_hw_intf); + cdm_hw_intf = NULL; + kfree(cdm_hw->core_info); + cdm_hw->core_info = NULL; + kfree(cdm_hw); + cdm_hw = NULL; + + return 0; +} + +static struct platform_driver cam_hw_cdm_driver = { + .probe = cam_hw_cdm_probe, + .remove = cam_hw_cdm_remove, + .driver = { + .name = "msm_cam_cdm", + .owner = THIS_MODULE, + .of_match_table = msm_cam_hw_cdm_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_hw_cdm_init_module(void) +{ + return platform_driver_register(&cam_hw_cdm_driver); +} + +static void __exit cam_hw_cdm_exit_module(void) +{ + platform_driver_unregister(&cam_hw_cdm_driver); +} + +module_init(cam_hw_cdm_init_module); +module_exit(cam_hw_cdm_exit_module); +MODULE_DESCRIPTION("MSM Camera HW CDM driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_1_0.h b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_1_0.h new file mode 100644 index 0000000000000000000000000000000000000000..ad0e9d62731d77ef76ae5542b98b0c65ac7dbd6e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_1_0.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_cdm.h" + +static struct cam_version_reg cdm_hw_1_0_titan_version = { + .hw_version = 0x4, +}; + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_1_0_bl_pending_req0 = { + .rb_offset = 0x6c, + .rb_mask = 0x7F, + .rb_num_fifo = 0x1, + .rb_next_fifo_shift = 0x0, +}; + +static struct cam_cdm_irq_regs cdm_hw_1_0_irq0 = { + .irq_mask = 0x30, + .irq_clear = 0x34, + .irq_clear_cmd = 0x38, + .irq_set = 0x3c, + .irq_set_cmd = 0x40, + .irq_status = 0x44, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_1_0_bl_fifo0 = { + .bl_fifo_base = 0x50, + .bl_fifo_len = 0x54, + .bl_fifo_store = 0x58, + .bl_fifo_cfg = 0x5c, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg0 = { + .scratch_reg = 0x90, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg1 = { + .scratch_reg = 0x94, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg2 = { + .scratch_reg = 0x98, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg3 = { + .scratch_reg = 0x9c, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg4 = { + .scratch_reg = 0xa0, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg5 = { + .scratch_reg = 0xa4, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg6 = { + .scratch_reg = 0xa8, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg7 = { + .scratch_reg = 0xac, +}; + +static struct cam_cdm_perf_mon_regs cdm_1_0_perf_mon0 = { + .perf_mon_ctrl = 0x110, + .perf_mon_0 = 0x114, + .perf_mon_1 = 0x118, + .perf_mon_2 = 0x11c, +}; + +static struct cam_cdm_common_regs cdm_hw_1_0_cmn_reg_offset = { + .cdm_hw_version = 0x0, + .cam_version = &cdm_hw_1_0_titan_version, + .rst_cmd = 0x10, + .cgc_cfg = 0x14, + .core_cfg = 0x18, + .core_en = 0x1c, + .fe_cfg = 0x20, + .bl_fifo_rb = 0x60, + .bl_fifo_base_rb = 0x64, + .bl_fifo_len_rb = 0x68, + .usr_data = 0x80, + .wait_status = 0x84, + .last_ahb_addr = 0xd0, + .last_ahb_data = 0xd4, + .core_debug = 0xd8, + .last_ahb_err_addr = 0xe0, + .last_ahb_err_data = 0xe4, + .current_bl_base = 0xe8, + .current_bl_len = 0xec, + .current_used_ahb_base = 0xf0, + .debug_status = 0xf4, + .bus_misr_cfg0 = 0x100, + .bus_misr_cfg1 = 0x104, + .bus_misr_rd_val = 0x108, + .pending_req = { + &cdm_hw_1_0_bl_pending_req0, + NULL, + }, + .comp_wait = { NULL, NULL }, + .perf_mon = { + &cdm_1_0_perf_mon0, + NULL, + }, + .scratch = { + &cdm_1_0_scratch_reg0, + &cdm_1_0_scratch_reg1, + &cdm_1_0_scratch_reg2, + &cdm_1_0_scratch_reg3, + &cdm_1_0_scratch_reg4, + &cdm_1_0_scratch_reg5, + &cdm_1_0_scratch_reg6, + &cdm_1_0_scratch_reg7, + NULL, + NULL, + NULL, + NULL, + }, + .perf_reg = NULL, + .icl_reg = NULL, + .spare = 0x200, +}; + +static struct cam_cdm_common_reg_data cdm_hw_1_0_cmn_reg_data = { + .num_bl_fifo = 0x1, + .num_bl_fifo_irq = 0x1, + .num_bl_pending_req_reg = 0x1, + .num_scratch_reg = 0x8, +}; + +static struct cam_cdm_hw_reg_offset cam_cdm_1_0_reg_offset = { + .cmn_reg = &cdm_hw_1_0_cmn_reg_offset, + .bl_fifo_reg = { + &cdm_hw_1_0_bl_fifo0, + NULL, + NULL, + NULL, + }, + .irq_reg = { + &cdm_hw_1_0_irq0, + NULL, + NULL, + NULL, + }, + .reg_data = &cdm_hw_1_0_cmn_reg_data, +}; diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_1_1.h b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_1_1.h new file mode 100644 index 0000000000000000000000000000000000000000..c2345df725bc66da0641ccbcc5d4032db1a611ef --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_1_1.h @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_cdm.h" + +static struct cam_version_reg cdm_hw_1_1_titan_version = { + .hw_version = 0x4, +}; + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_1_1_bl_pending_req0 = { + .rb_offset = 0x6c, + .rb_mask = 0x7f, + .rb_num_fifo = 0x1, + .rb_next_fifo_shift = 0x0, +}; + +static struct cam_cdm_irq_regs cdm_hw_1_1_irq0 = { + .irq_mask = 0x30, + .irq_clear = 0x34, + .irq_clear_cmd = 0x38, + .irq_set = 0x3c, + .irq_set_cmd = 0x40, + .irq_status = 0x44, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_1_1_bl_fifo0 = { + .bl_fifo_base = 0x50, + .bl_fifo_len = 0x54, + .bl_fifo_store = 0x58, + .bl_fifo_cfg = 0x5c, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg0 = { + .scratch_reg = 0x90, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg1 = { + .scratch_reg = 0x94, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg2 = { + .scratch_reg = 0x98, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg3 = { + .scratch_reg = 0x9c, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg4 = { + .scratch_reg = 0xa0, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg5 = { + .scratch_reg = 0xa4, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg6 = { + .scratch_reg = 0xa8, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg7 = { + .scratch_reg = 0xac, +}; + +static struct cam_cdm_perf_mon_regs cdm_1_1_perf_mon0 = { + .perf_mon_ctrl = 0x110, + .perf_mon_0 = 0x114, + .perf_mon_1 = 0x118, + .perf_mon_2 = 0x11c, +}; + +static struct cam_cdm_comp_wait_status cdm_1_1_comp_wait_status0 = { + .comp_wait_status = 0x88, +}; + +static struct cam_cdm_comp_wait_status cdm_1_1_comp_wait_status1 = { + .comp_wait_status = 0x8c, +}; + +static struct cam_cdm_common_regs cdm_hw_1_1_cmn_reg_offset = { + .cdm_hw_version = 0x0, + .cam_version = &cdm_hw_1_1_titan_version, + .rst_cmd = 0x10, + .cgc_cfg = 0x14, + .core_cfg = 0x18, + .core_en = 0x1c, + .fe_cfg = 0x20, + .bl_fifo_rb = 0x60, + .bl_fifo_base_rb = 0x64, + .bl_fifo_len_rb = 0x68, + .usr_data = 0x80, + .wait_status = 0x84, + .last_ahb_addr = 0xd0, + .last_ahb_data = 0xd4, + .core_debug = 0xd8, + .last_ahb_err_addr = 0xe0, + .last_ahb_err_data = 0xe4, + .current_bl_base = 0xe8, + .current_bl_len = 0xec, + .current_used_ahb_base = 0xf0, + .debug_status = 0xf4, + .bus_misr_cfg0 = 0x100, + .bus_misr_cfg1 = 0x104, + .bus_misr_rd_val = 0x108, + .pending_req = { + &cdm_hw_1_1_bl_pending_req0, + NULL, + }, + .comp_wait = { + &cdm_1_1_comp_wait_status0, + &cdm_1_1_comp_wait_status1, + }, + .perf_mon = { + &cdm_1_1_perf_mon0, + NULL, + }, + .scratch = { + &cdm_1_1_scratch_reg0, + &cdm_1_1_scratch_reg1, + &cdm_1_1_scratch_reg2, + &cdm_1_1_scratch_reg3, + &cdm_1_1_scratch_reg4, + &cdm_1_1_scratch_reg5, + &cdm_1_1_scratch_reg6, + &cdm_1_1_scratch_reg7, + NULL, + NULL, + NULL, + NULL, + }, + .perf_reg = NULL, + .icl_reg = NULL, + .spare = 0x1fc, +}; + +static struct cam_cdm_common_reg_data cdm_hw_1_1_cmn_reg_data = { + .num_bl_fifo = 0x1, + .num_bl_fifo_irq = 0x1, + .num_bl_pending_req_reg = 0x1, + .num_scratch_reg = 0x8, +}; + +struct cam_cdm_hw_reg_offset cam_cdm_1_1_reg_offset = { + .cmn_reg = &cdm_hw_1_1_cmn_reg_offset, + .bl_fifo_reg = { + &cdm_hw_1_1_bl_fifo0, + NULL, + NULL, + NULL, + }, + .irq_reg = { + &cdm_hw_1_1_irq0, + NULL, + NULL, + NULL, + }, + .reg_data = &cdm_hw_1_1_cmn_reg_data, +}; diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_1_2.h b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_1_2.h new file mode 100644 index 0000000000000000000000000000000000000000..63d1410eaff2003a6f162d8e126fbbb53d92d2e8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_1_2.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_cdm.h" + +static struct cam_version_reg cdm_hw_1_2_titan_version = { + .hw_version = 0x4, +}; + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_1_2_bl_pending_req0 = { + .rb_offset = 0x6c, + .rb_mask = 0x7f, + .rb_num_fifo = 0x1, + .rb_next_fifo_shift = 0x0, +}; + +static struct cam_cdm_irq_regs cdm_hw_1_2_irq0 = { + .irq_mask = 0x30, + .irq_clear = 0x34, + .irq_clear_cmd = 0x38, + .irq_set = 0x3c, + .irq_set_cmd = 0x40, + .irq_status = 0x44, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_1_2_bl_fifo0 = { + .bl_fifo_base = 0x50, + .bl_fifo_len = 0x54, + .bl_fifo_store = 0x58, + .bl_fifo_cfg = 0x5c, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg0 = { + .scratch_reg = 0x90, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg1 = { + .scratch_reg = 0x94, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg2 = { + .scratch_reg = 0x98, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg3 = { + .scratch_reg = 0x9c, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg4 = { + .scratch_reg = 0xa0, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg5 = { + .scratch_reg = 0xa4, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg6 = { + .scratch_reg = 0xa8, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg7 = { + .scratch_reg = 0xac, +}; + +static struct cam_cdm_perf_mon_regs cdm_1_2_perf_mon0 = { + .perf_mon_ctrl = 0x110, + .perf_mon_0 = 0x114, + .perf_mon_1 = 0x118, + .perf_mon_2 = 0x11c, +}; + +static struct cam_cdm_comp_wait_status cdm_1_2_comp_wait_status0 = { + .comp_wait_status = 0x88, +}; + +static struct cam_cdm_comp_wait_status cdm_1_2_comp_wait_status1 = { + .comp_wait_status = 0x8c, +}; + +static struct cam_cdm_perf_regs cdm_1_2_perf = { + .count_cfg_0 = 0x180, + .always_count_val = 0x184, + .busy_count_val = 0x188, + .stall_axi_count_val = 0x18c, + .count_status = 0x190, +}; + +static struct cam_cdm_icl_data_regs cdm_1_2_icl_data = { + .icl_last_data_0 = 0x1c0, + .icl_last_data_1 = 0x1c4, + .icl_last_data_2 = 0x1c8, + .icl_inv_data = 0x1cc, +}; + +static struct cam_cdm_icl_regs cdm_1_2_icl = { + .data_regs = &cdm_1_2_icl_data, + .misc_regs = NULL, +}; + +static struct cam_cdm_common_regs cdm_hw_1_2_cmn_reg_offset = { + .cdm_hw_version = 0x0, + .cam_version = &cdm_hw_1_2_titan_version, + .rst_cmd = 0x10, + .cgc_cfg = 0x14, + .core_cfg = 0x18, + .core_en = 0x1c, + .fe_cfg = 0x20, + .bl_fifo_rb = 0x60, + .bl_fifo_base_rb = 0x64, + .bl_fifo_len_rb = 0x68, + .usr_data = 0x80, + .wait_status = 0x84, + .last_ahb_addr = 0xd0, + .last_ahb_data = 0xd4, + .core_debug = 0xd8, + .last_ahb_err_addr = 0xe0, + .last_ahb_err_data = 0xe4, + .current_bl_base = 0xe8, + .current_bl_len = 0xec, + .current_used_ahb_base = 0xf0, + .debug_status = 0xf4, + .bus_misr_cfg0 = 0x100, + .bus_misr_cfg1 = 0x104, + .bus_misr_rd_val = 0x108, + .pending_req = { + &cdm_hw_1_2_bl_pending_req0, + NULL, + }, + .comp_wait = { + &cdm_1_2_comp_wait_status0, + &cdm_1_2_comp_wait_status1, + }, + .perf_mon = { + &cdm_1_2_perf_mon0, + NULL, + }, + .scratch = { + &cdm_1_2_scratch_reg0, + &cdm_1_2_scratch_reg1, + &cdm_1_2_scratch_reg2, + &cdm_1_2_scratch_reg3, + &cdm_1_2_scratch_reg4, + &cdm_1_2_scratch_reg5, + &cdm_1_2_scratch_reg6, + &cdm_1_2_scratch_reg7, + NULL, + NULL, + NULL, + NULL, + }, + .perf_reg = &cdm_1_2_perf, + .icl_reg = &cdm_1_2_icl, + .spare = 0x1fc, +}; + +static struct cam_cdm_common_reg_data cdm_hw_1_2_cmn_reg_data = { + .num_bl_fifo = 0x1, + .num_bl_fifo_irq = 0x1, + .num_bl_pending_req_reg = 0x1, + .num_scratch_reg = 0x8, +}; + +struct cam_cdm_hw_reg_offset cam_cdm_1_2_reg_offset = { + .cmn_reg = &cdm_hw_1_2_cmn_reg_offset, + .bl_fifo_reg = { + &cdm_hw_1_2_bl_fifo0, + NULL, + NULL, + NULL, + }, + .irq_reg = { + &cdm_hw_1_2_irq0, + NULL, + NULL, + NULL, + }, + .reg_data = &cdm_hw_1_2_cmn_reg_data, +}; diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_2_0.h b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_2_0.h new file mode 100644 index 0000000000000000000000000000000000000000..bd5a7963e1bae5b6cc601ef8305bc13406ffb79d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_2_0.h @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_cdm.h" + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_0_bl_pending_req0 = { + .rb_offset = 0x6c, + .rb_mask = 0x1ff, + .rb_num_fifo = 0x2, + .rb_next_fifo_shift = 0x10, +}; + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_0_bl_pending_req1 = { + .rb_offset = 0x70, + .rb_mask = 0x1ff, + .rb_num_fifo = 0x2, + .rb_next_fifo_shift = 0x10, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_0_irq0 = { + .irq_mask = 0x30, + .irq_clear = 0x34, + .irq_clear_cmd = 0x38, + .irq_set = 0x3c, + .irq_set_cmd = 0x40, + .irq_status = 0x44, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_0_irq1 = { + .irq_mask = 0x130, + .irq_clear = 0x134, + .irq_clear_cmd = 0x138, + .irq_set = 0x13c, + .irq_set_cmd = 0x140, + .irq_status = 0x144, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_0_irq2 = { + .irq_mask = 0x230, + .irq_clear = 0x234, + .irq_clear_cmd = 0x238, + .irq_set = 0x23c, + .irq_set_cmd = 0x240, + .irq_status = 0x244, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_0_irq3 = { + .irq_mask = 0x330, + .irq_clear = 0x334, + .irq_clear_cmd = 0x338, + .irq_set = 0x33c, + .irq_set_cmd = 0x340, + .irq_status = 0x344, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_0_bl_fifo0 = { + .bl_fifo_base = 0x50, + .bl_fifo_len = 0x54, + .bl_fifo_store = 0x58, + .bl_fifo_cfg = 0x5c, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_0_bl_fifo1 = { + .bl_fifo_base = 0x150, + .bl_fifo_len = 0x154, + .bl_fifo_store = 0x158, + .bl_fifo_cfg = 0x15c, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_0_bl_fifo2 = { + .bl_fifo_base = 0x250, + .bl_fifo_len = 0x254, + .bl_fifo_store = 0x258, + .bl_fifo_cfg = 0x25c, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_0_bl_fifo3 = { + .bl_fifo_base = 0x350, + .bl_fifo_len = 0x354, + .bl_fifo_store = 0x358, + .bl_fifo_cfg = 0x35c, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg0 = { + .scratch_reg = 0x90, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg1 = { + .scratch_reg = 0x94, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg2 = { + .scratch_reg = 0x98, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg3 = { + .scratch_reg = 0x9c, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg4 = { + .scratch_reg = 0xa0, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg5 = { + .scratch_reg = 0xa4, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg6 = { + .scratch_reg = 0xa8, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg7 = { + .scratch_reg = 0xac, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg8 = { + .scratch_reg = 0xb0, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg9 = { + .scratch_reg = 0xb4, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg10 = { + .scratch_reg = 0xb8, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg11 = { + .scratch_reg = 0xbc, +}; + +static struct cam_cdm_perf_mon_regs cdm_2_0_perf_mon0 = { + .perf_mon_ctrl = 0x110, + .perf_mon_0 = 0x114, + .perf_mon_1 = 0x118, + .perf_mon_2 = 0x11c, +}; + +static struct cam_cdm_perf_mon_regs cdm_2_0_perf_mon1 = { + .perf_mon_ctrl = 0x120, + .perf_mon_0 = 0x124, + .perf_mon_1 = 0x128, + .perf_mon_2 = 0x12c, +}; + +static struct cam_cdm_comp_wait_status cdm_2_0_comp_wait_status0 = { + .comp_wait_status = 0x88, +}; + +static struct cam_cdm_comp_wait_status cdm_2_0_comp_wait_status1 = { + .comp_wait_status = 0x8c, +}; + +static struct cam_cdm_icl_data_regs cdm_2_0_icl_data = { + .icl_last_data_0 = 0x1c0, + .icl_last_data_1 = 0x1c4, + .icl_last_data_2 = 0x1c8, + .icl_inv_data = 0x1cc, +}; + +static struct cam_cdm_icl_misc_regs cdm_2_0_icl_misc = { + .icl_inv_bl_addr = 0x1d0, + .icl_status = 0x1d4, +}; + +static struct cam_cdm_icl_regs cdm_2_0_icl = { + .data_regs = &cdm_2_0_icl_data, + .misc_regs = &cdm_2_0_icl_misc, +}; + +static struct cam_cdm_common_regs cdm_hw_2_0_cmn_reg_offset = { + .cdm_hw_version = 0x0, + .cam_version = NULL, + .rst_cmd = 0x10, + .cgc_cfg = 0x14, + .core_cfg = 0x18, + .core_en = 0x1c, + .fe_cfg = 0x20, + .bl_fifo_rb = 0x60, + .bl_fifo_base_rb = 0x64, + .bl_fifo_len_rb = 0x68, + .usr_data = 0x80, + .wait_status = 0x84, + .last_ahb_addr = 0xd0, + .last_ahb_data = 0xd4, + .core_debug = 0xd8, + .last_ahb_err_addr = 0xe0, + .last_ahb_err_data = 0xe4, + .current_bl_base = 0xe8, + .current_bl_len = 0xec, + .current_used_ahb_base = 0xf0, + .debug_status = 0xf4, + .bus_misr_cfg0 = 0x100, + .bus_misr_cfg1 = 0x104, + .bus_misr_rd_val = 0x108, + .pending_req = { + &cdm_hw_2_0_bl_pending_req0, + &cdm_hw_2_0_bl_pending_req1, + }, + .comp_wait = { + &cdm_2_0_comp_wait_status0, + &cdm_2_0_comp_wait_status1, + }, + .perf_mon = { + &cdm_2_0_perf_mon0, + &cdm_2_0_perf_mon1, + }, + .scratch = { + &cdm_2_0_scratch_reg0, + &cdm_2_0_scratch_reg1, + &cdm_2_0_scratch_reg2, + &cdm_2_0_scratch_reg3, + &cdm_2_0_scratch_reg4, + &cdm_2_0_scratch_reg5, + &cdm_2_0_scratch_reg6, + &cdm_2_0_scratch_reg7, + &cdm_2_0_scratch_reg8, + &cdm_2_0_scratch_reg9, + &cdm_2_0_scratch_reg10, + &cdm_2_0_scratch_reg11, + }, + .perf_reg = NULL, + .icl_reg = &cdm_2_0_icl, + .spare = 0x1fc, +}; + +static struct cam_cdm_common_reg_data cdm_hw_2_0_cmn_reg_data = { + .num_bl_fifo = 0x4, + .num_bl_fifo_irq = 0x4, + .num_bl_pending_req_reg = 0x2, + .num_scratch_reg = 0xc, +}; + +struct cam_cdm_hw_reg_offset cam_cdm_2_0_reg_offset = { + .cmn_reg = &cdm_hw_2_0_cmn_reg_offset, + .bl_fifo_reg = { + &cdm_hw_2_0_bl_fifo0, + &cdm_hw_2_0_bl_fifo1, + &cdm_hw_2_0_bl_fifo2, + &cdm_hw_2_0_bl_fifo3, + }, + .irq_reg = { + &cdm_hw_2_0_irq0, + &cdm_hw_2_0_irq1, + &cdm_hw_2_0_irq2, + &cdm_hw_2_0_irq3, + }, + .reg_data = &cdm_hw_2_0_cmn_reg_data, +}; diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_2_1.h b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_2_1.h new file mode 100644 index 0000000000000000000000000000000000000000..a12be17a3c4aadd06d7d0696ec352c45da11338b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_hw_reg_2_1.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include "cam_cdm.h" + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_1_bl_pending_req0 = { + .rb_offset = 0x6c, + .rb_mask = 0x1ff, + .rb_num_fifo = 0x2, + .rb_next_fifo_shift = 0x10, +}; + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_1_bl_pending_req1 = { + .rb_offset = 0x70, + .rb_mask = 0x1ff, + .rb_num_fifo = 0x2, + .rb_next_fifo_shift = 0x10, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_1_irq0 = { + .irq_mask = 0x30, + .irq_clear = 0x34, + .irq_clear_cmd = 0x38, + .irq_set = 0x3c, + .irq_set_cmd = 0x40, + .irq_status = 0x44, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_1_irq1 = { + .irq_mask = 0x130, + .irq_clear = 0x134, + .irq_clear_cmd = 0x138, + .irq_set = 0x13c, + .irq_set_cmd = 0x140, + .irq_status = 0x144, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_1_irq2 = { + .irq_mask = 0x230, + .irq_clear = 0x234, + .irq_clear_cmd = 0x238, + .irq_set = 0x23c, + .irq_set_cmd = 0x240, + .irq_status = 0x244, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_1_irq3 = { + .irq_mask = 0x330, + .irq_clear = 0x334, + .irq_clear_cmd = 0x338, + .irq_set = 0x33c, + .irq_set_cmd = 0x340, + .irq_status = 0x344, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_1_bl_fifo0 = { + .bl_fifo_base = 0x50, + .bl_fifo_len = 0x54, + .bl_fifo_store = 0x58, + .bl_fifo_cfg = 0x5c, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_1_bl_fifo1 = { + .bl_fifo_base = 0x150, + .bl_fifo_len = 0x154, + .bl_fifo_store = 0x158, + .bl_fifo_cfg = 0x15c, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_1_bl_fifo2 = { + .bl_fifo_base = 0x250, + .bl_fifo_len = 0x254, + .bl_fifo_store = 0x258, + .bl_fifo_cfg = 0x25c, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_1_bl_fifo3 = { + .bl_fifo_base = 0x350, + .bl_fifo_len = 0x354, + .bl_fifo_store = 0x358, + .bl_fifo_cfg = 0x35c, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg0 = { + .scratch_reg = 0x90, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg1 = { + .scratch_reg = 0x94, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg2 = { + .scratch_reg = 0x98, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg3 = { + .scratch_reg = 0x9c, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg4 = { + .scratch_reg = 0xa0, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg5 = { + .scratch_reg = 0xa4, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg6 = { + .scratch_reg = 0xa8, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg7 = { + .scratch_reg = 0xac, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg8 = { + .scratch_reg = 0xb0, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg9 = { + .scratch_reg = 0xb4, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg10 = { + .scratch_reg = 0xb8, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg11 = { + .scratch_reg = 0xbc, +}; + +static struct cam_cdm_perf_mon_regs cdm_2_1_perf_mon0 = { + .perf_mon_ctrl = 0x110, + .perf_mon_0 = 0x114, + .perf_mon_1 = 0x118, + .perf_mon_2 = 0x11c, +}; + +static struct cam_cdm_perf_mon_regs cdm_2_1_perf_mon1 = { + .perf_mon_ctrl = 0x120, + .perf_mon_0 = 0x124, + .perf_mon_1 = 0x128, + .perf_mon_2 = 0x12c, +}; + +static struct cam_cdm_comp_wait_status cdm_2_1_comp_wait_status0 = { + .comp_wait_status = 0x88, +}; + +static struct cam_cdm_comp_wait_status cdm_2_1_comp_wait_status1 = { + .comp_wait_status = 0x8c, +}; + +static struct cam_cdm_icl_data_regs cdm_2_1_icl_data = { + .icl_last_data_0 = 0x1c0, + .icl_last_data_1 = 0x1c4, + .icl_last_data_2 = 0x1c8, + .icl_inv_data = 0x1cc, +}; + +static struct cam_cdm_icl_misc_regs cdm_2_1_icl_misc = { + .icl_inv_bl_addr = 0x1d0, + .icl_status = 0x1d8, +}; + +static struct cam_cdm_icl_regs cdm_2_1_icl = { + .data_regs = &cdm_2_1_icl_data, + .misc_regs = &cdm_2_1_icl_misc, +}; + +static struct cam_cdm_common_regs cdm_hw_2_1_cmn_reg_offset = { + .cdm_hw_version = 0x0, + .cam_version = NULL, + .rst_cmd = 0x10, + .cgc_cfg = 0x14, + .core_cfg = 0x18, + .core_en = 0x1c, + .fe_cfg = 0x20, + .irq_context_status = 0x2c, + .bl_fifo_rb = 0x60, + .bl_fifo_base_rb = 0x64, + .bl_fifo_len_rb = 0x68, + .usr_data = 0x80, + .wait_status = 0x84, + .last_ahb_addr = 0xd0, + .last_ahb_data = 0xd4, + .core_debug = 0xd8, + .last_ahb_err_addr = 0xe0, + .last_ahb_err_data = 0xe4, + .current_bl_base = 0xe8, + .current_bl_len = 0xec, + .current_used_ahb_base = 0xf0, + .debug_status = 0xf4, + .bus_misr_cfg0 = 0x100, + .bus_misr_cfg1 = 0x104, + .bus_misr_rd_val = 0x108, + .pending_req = { + &cdm_hw_2_1_bl_pending_req0, + &cdm_hw_2_1_bl_pending_req1, + }, + .comp_wait = { + &cdm_2_1_comp_wait_status0, + &cdm_2_1_comp_wait_status1, + }, + .perf_mon = { + &cdm_2_1_perf_mon0, + &cdm_2_1_perf_mon1, + }, + .scratch = { + &cdm_2_1_scratch_reg0, + &cdm_2_1_scratch_reg1, + &cdm_2_1_scratch_reg2, + &cdm_2_1_scratch_reg3, + &cdm_2_1_scratch_reg4, + &cdm_2_1_scratch_reg5, + &cdm_2_1_scratch_reg6, + &cdm_2_1_scratch_reg7, + &cdm_2_1_scratch_reg8, + &cdm_2_1_scratch_reg9, + &cdm_2_1_scratch_reg10, + &cdm_2_1_scratch_reg11, + }, + .perf_reg = NULL, + .icl_reg = &cdm_2_1_icl, + .spare = 0x3fc, +}; + +static struct cam_cdm_common_reg_data cdm_hw_2_1_cmn_reg_data = { + .num_bl_fifo = 0x4, + .num_bl_fifo_irq = 0x4, + .num_bl_pending_req_reg = 0x2, + .num_scratch_reg = 0xc, +}; + +struct cam_cdm_hw_reg_offset cam_cdm_2_1_reg_offset = { + .cmn_reg = &cdm_hw_2_1_cmn_reg_offset, + .bl_fifo_reg = { + &cdm_hw_2_1_bl_fifo0, + &cdm_hw_2_1_bl_fifo1, + &cdm_hw_2_1_bl_fifo2, + &cdm_hw_2_1_bl_fifo3, + }, + .irq_reg = { + &cdm_hw_2_1_irq0, + &cdm_hw_2_1_irq1, + &cdm_hw_2_1_irq2, + &cdm_hw_2_1_irq3, + }, + .reg_data = &cdm_hw_2_1_cmn_reg_data, +}; + diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_intf.c b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_intf.c new file mode 100644 index 0000000000000000000000000000000000000000..4beeb71d218120c1f8c9d0caccf32388659fee29 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_intf.c @@ -0,0 +1,726 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "cam_cdm_intf_api.h" +#include "cam_cdm.h" +#include "cam_cdm_virtual.h" +#include "cam_soc_util.h" +#include "cam_cdm_soc.h" +#include "cam_cdm_core_common.h" + +static struct cam_cdm_intf_mgr cdm_mgr; +static DEFINE_MUTEX(cam_cdm_mgr_lock); + +static const struct of_device_id msm_cam_cdm_intf_dt_match[] = { + { .compatible = "qcom,cam-cdm-intf", }, + {} +}; + +static int get_cdm_mgr_refcount(void) +{ + int rc = 0; + + mutex_lock(&cam_cdm_mgr_lock); + if (cdm_mgr.probe_done == false) { + CAM_ERR(CAM_CDM, "CDM intf mgr not probed yet"); + rc = -EPERM; + } else { + CAM_DBG(CAM_CDM, "CDM intf mgr get refcount=%d", + cdm_mgr.refcount); + cdm_mgr.refcount++; + } + mutex_unlock(&cam_cdm_mgr_lock); + return rc; +} + +static void put_cdm_mgr_refcount(void) +{ + mutex_lock(&cam_cdm_mgr_lock); + if (cdm_mgr.probe_done == false) { + CAM_ERR(CAM_CDM, "CDM intf mgr not probed yet"); + } else { + CAM_DBG(CAM_CDM, "CDM intf mgr put refcount=%d", + cdm_mgr.refcount); + if (cdm_mgr.refcount > 0) { + cdm_mgr.refcount--; + } else { + CAM_ERR(CAM_CDM, "Refcount put when zero"); + WARN_ON(1); + } + } + mutex_unlock(&cam_cdm_mgr_lock); +} + +static int get_cdm_iommu_handle(struct cam_iommu_handle *cdm_handles, + uint32_t hw_idx) +{ + int rc = -EPERM; + struct cam_hw_intf *hw = cdm_mgr.nodes[hw_idx].device; + + if (hw->hw_ops.get_hw_caps) { + rc = hw->hw_ops.get_hw_caps(hw->hw_priv, cdm_handles, + sizeof(struct cam_iommu_handle)); + } + + return rc; +} + +static int get_cdm_index_by_id(char *identifier, + uint32_t cell_index, uint32_t *hw_index) +{ + int rc = -EPERM, i, j; + char client_name[128], name_index[160]; + + snprintf(client_name, sizeof(client_name), "%s", identifier); + snprintf(name_index, sizeof(name_index), "%s%d", + identifier, cell_index); + + CAM_DBG(CAM_CDM, + "Looking for HW id of =%s or %s and index=%d cdm_count %d", + identifier, name_index, cell_index, cdm_mgr.cdm_count); + mutex_lock(&cam_cdm_mgr_lock); + for (i = 0; i < cdm_mgr.cdm_count; i++) { + mutex_lock(&cdm_mgr.nodes[i].lock); + CAM_DBG(CAM_CDM, "dt_num_supported_clients=%d", + cdm_mgr.nodes[i].data->dt_num_supported_clients); + + for (j = 0; j < + cdm_mgr.nodes[i].data->dt_num_supported_clients; j++) { + CAM_DBG(CAM_CDM, "client name:%s dev Index: %d", + cdm_mgr.nodes[i].data->dt_cdm_client_name[j], + i); + if (!strcmp( + cdm_mgr.nodes[i].data->dt_cdm_client_name[j], + client_name) || !strcmp( + cdm_mgr.nodes[i].data->dt_cdm_client_name[j], + name_index)) { + rc = 0; + *hw_index = i; + break; + } + } + mutex_unlock(&cdm_mgr.nodes[i].lock); + if (rc == 0) + break; + } + mutex_unlock(&cam_cdm_mgr_lock); + + return rc; +} + +int cam_cdm_get_iommu_handle(char *identifier, + struct cam_iommu_handle *cdm_handles) +{ + int i, j, rc = -EPERM; + + if ((!identifier) || (!cdm_handles)) + return -EINVAL; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + return rc; + } + CAM_DBG(CAM_CDM, "Looking for Iommu handle of %s", identifier); + + for (i = 0; i < cdm_mgr.cdm_count; i++) { + mutex_lock(&cdm_mgr.nodes[i].lock); + if (!cdm_mgr.nodes[i].data) { + mutex_unlock(&cdm_mgr.nodes[i].lock); + continue; + } + CAM_DBG(CAM_CDM, "dt_num_supported_clients=%d", + cdm_mgr.nodes[i].data->dt_num_supported_clients); + for (j = 0; j < + cdm_mgr.nodes[i].data->dt_num_supported_clients; + j++) { + CAM_DBG(CAM_CDM, "client name:%s dev Index: %d", + cdm_mgr.nodes[i].data->dt_cdm_client_name[j], + i); + if (!strcmp( + cdm_mgr.nodes[i].data->dt_cdm_client_name[j], + identifier)) { + rc = get_cdm_iommu_handle(cdm_handles, i); + break; + } + } + mutex_unlock(&cdm_mgr.nodes[i].lock); + if (rc == 0) + break; + } + put_cdm_mgr_refcount(); + + return rc; +} +EXPORT_SYMBOL(cam_cdm_get_iommu_handle); + +int cam_cdm_acquire(struct cam_cdm_acquire_data *data) +{ + int rc = -EPERM; + struct cam_hw_intf *hw; + struct cam_hw_info *cdm_hw; + struct cam_cdm *core = NULL; + uint32_t hw_index = 0; + + if ((!data) || (!data->base_array_cnt)) + return -EINVAL; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + return rc; + } + + if (data->id > CAM_CDM_HW_ANY) { + CAM_ERR(CAM_CDM, + "only CAM_CDM_VIRTUAL/CAM_CDM_HW_ANY is supported"); + rc = -EPERM; + goto end; + } + rc = get_cdm_index_by_id(data->identifier, data->cell_index, + &hw_index); + if ((rc < 0) && (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM)) { + CAM_ERR(CAM_CDM, "Failed to identify associated hw id"); + goto end; + } else { + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.process_cmd) { + cdm_hw = hw->hw_priv; + core = (struct cam_cdm *)cdm_hw->core_info; + data->id = core->id; + CAM_DBG(CAM_CDM, + "Device = %s, hw_index = %d, CDM id = %d", + data->identifier, hw_index, data->id); + rc = hw->hw_ops.process_cmd(hw->hw_priv, + CAM_CDM_HW_INTF_CMD_ACQUIRE, data, + sizeof(struct cam_cdm_acquire_data)); + if (rc < 0) { + CAM_ERR(CAM_CDM, "CDM hw acquire failed"); + goto end; + } + } else { + CAM_ERR(CAM_CDM, "idx %d doesn't have acquire ops", + hw_index); + rc = -EPERM; + } + } +end: + if (rc < 0) { + CAM_ERR(CAM_CDM, "CDM acquire failed for id=%d name=%s, idx=%d", + data->id, data->identifier, data->cell_index); + put_cdm_mgr_refcount(); + } + return rc; +} +EXPORT_SYMBOL(cam_cdm_acquire); + +struct cam_cdm_utils_ops *cam_cdm_publish_ops(void) +{ + struct cam_hw_version cdm_version; + + cdm_version.major = 1; + cdm_version.minor = 0; + cdm_version.incr = 0; + cdm_version.reserved = 0; + + return cam_cdm_get_ops(0, &cdm_version, true); +} +EXPORT_SYMBOL(cam_cdm_publish_ops); + +int cam_cdm_release(uint32_t handle) +{ + uint32_t hw_index; + int rc = -EPERM; + struct cam_hw_intf *hw; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + return rc; + } + + hw_index = CAM_CDM_GET_HW_IDX(handle); + if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) { + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.process_cmd) { + rc = hw->hw_ops.process_cmd(hw->hw_priv, + CAM_CDM_HW_INTF_CMD_RELEASE, &handle, + sizeof(handle)); + if (rc < 0) + CAM_ERR(CAM_CDM, + "hw release failed for handle=%x", + handle); + } else + CAM_ERR(CAM_CDM, "hw idx %d doesn't have release ops", + hw_index); + } + put_cdm_mgr_refcount(); + if (rc == 0) + put_cdm_mgr_refcount(); + + return rc; +} +EXPORT_SYMBOL(cam_cdm_release); + + +int cam_cdm_submit_bls(uint32_t handle, struct cam_cdm_bl_request *data) +{ + uint32_t hw_index; + int rc = -EINVAL; + struct cam_hw_intf *hw; + + if (!data) + return rc; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + rc = -EPERM; + return rc; + } + + hw_index = CAM_CDM_GET_HW_IDX(handle); + if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) { + struct cam_cdm_hw_intf_cmd_submit_bl req; + + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.process_cmd) { + req.data = data; + req.handle = handle; + rc = hw->hw_ops.process_cmd(hw->hw_priv, + CAM_CDM_HW_INTF_CMD_SUBMIT_BL, &req, + sizeof(struct cam_cdm_hw_intf_cmd_submit_bl)); + if (rc < 0) + CAM_ERR(CAM_CDM, + "hw submit bl failed for handle=%x", + handle); + } else { + CAM_ERR(CAM_CDM, "hw idx %d doesn't have submit ops", + hw_index); + } + } + put_cdm_mgr_refcount(); + + return rc; +} +EXPORT_SYMBOL(cam_cdm_submit_bls); + +int cam_cdm_stream_on(uint32_t handle) +{ + uint32_t hw_index; + int rc = -EINVAL; + struct cam_hw_intf *hw; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + rc = -EPERM; + return rc; + } + + hw_index = CAM_CDM_GET_HW_IDX(handle); + if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) { + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.start) { + rc = hw->hw_ops.start(hw->hw_priv, &handle, + sizeof(uint32_t)); + if (rc < 0) + CAM_ERR(CAM_CDM, + "hw start failed handle=%x", + handle); + } else { + CAM_ERR(CAM_CDM, + "hw idx %d doesn't have start ops", + hw_index); + } + } + put_cdm_mgr_refcount(); + + return rc; +} +EXPORT_SYMBOL(cam_cdm_stream_on); + +int cam_cdm_stream_off(uint32_t handle) +{ + uint32_t hw_index; + int rc = -EINVAL; + struct cam_hw_intf *hw; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + rc = -EPERM; + return rc; + } + + hw_index = CAM_CDM_GET_HW_IDX(handle); + if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) { + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.stop) { + rc = hw->hw_ops.stop(hw->hw_priv, &handle, + sizeof(uint32_t)); + if (rc < 0) + CAM_ERR(CAM_CDM, "hw stop failed handle=%x", + handle); + } else { + CAM_ERR(CAM_CDM, "hw idx %d doesn't have stop ops", + hw_index); + } + } + put_cdm_mgr_refcount(); + + return rc; +} +EXPORT_SYMBOL(cam_cdm_stream_off); + +int cam_cdm_reset_hw(uint32_t handle) +{ + uint32_t hw_index; + int rc = -EINVAL; + struct cam_hw_intf *hw; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + rc = -EPERM; + return rc; + } + + hw_index = CAM_CDM_GET_HW_IDX(handle); + if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) { + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.process_cmd) { + rc = hw->hw_ops.process_cmd(hw->hw_priv, + CAM_CDM_HW_INTF_CMD_RESET_HW, &handle, + sizeof(handle)); + if (rc < 0) + CAM_ERR(CAM_CDM, + "CDM hw release failed for handle=%x", + handle); + } else { + CAM_ERR(CAM_CDM, "hw idx %d doesn't have release ops", + hw_index); + } + } + put_cdm_mgr_refcount(); + + return rc; +} +EXPORT_SYMBOL(cam_cdm_reset_hw); + +int cam_cdm_flush_hw(uint32_t handle) +{ + uint32_t hw_index; + int rc = -EINVAL; + struct cam_hw_intf *hw; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + rc = -EPERM; + return rc; + } + + hw_index = CAM_CDM_GET_HW_IDX(handle); + if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) { + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.process_cmd) { + rc = hw->hw_ops.process_cmd(hw->hw_priv, + CAM_CDM_HW_INTF_CMD_FLUSH_HW, &handle, + sizeof(handle)); + if (rc < 0) + CAM_ERR(CAM_CDM, + "CDM hw release failed for handle=%x", + handle); + } else { + CAM_ERR(CAM_CDM, "hw idx %d doesn't have release ops", + hw_index); + } + } + put_cdm_mgr_refcount(); + + return rc; +} +EXPORT_SYMBOL(cam_cdm_flush_hw); + +int cam_cdm_handle_error(uint32_t handle) +{ + uint32_t hw_index; + int rc = -EINVAL; + struct cam_hw_intf *hw; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + rc = -EPERM; + return rc; + } + + hw_index = CAM_CDM_GET_HW_IDX(handle); + if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) { + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.process_cmd) { + rc = hw->hw_ops.process_cmd(hw->hw_priv, + CAM_CDM_HW_INTF_CMD_HANDLE_ERROR, + &handle, + sizeof(handle)); + if (rc < 0) + CAM_ERR(CAM_CDM, + "CDM hw release failed for handle=%x", + handle); + } else { + CAM_ERR(CAM_CDM, "hw idx %d doesn't have release ops", + hw_index); + } + } + put_cdm_mgr_refcount(); + + return rc; +} +EXPORT_SYMBOL(cam_cdm_handle_error); + +int cam_cdm_detect_hang_error(uint32_t handle) +{ + uint32_t hw_index; + int rc = -EINVAL; + struct cam_hw_intf *hw; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + rc = -EPERM; + return rc; + } + + hw_index = CAM_CDM_GET_HW_IDX(handle); + if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) { + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.process_cmd) + rc = hw->hw_ops.process_cmd(hw->hw_priv, + CAM_CDM_HW_INTF_CMD_HANG_DETECT, + &handle, + sizeof(handle)); + } + put_cdm_mgr_refcount(); + + return rc; +} +EXPORT_SYMBOL(cam_cdm_detect_hang_error); + +int cam_cdm_dump_debug_registers(uint32_t handle) +{ + uint32_t hw_index; + int rc = -EINVAL; + struct cam_hw_intf *hw; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + rc = -EPERM; + return rc; + } + + hw_index = CAM_CDM_GET_HW_IDX(handle); + if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) { + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.process_cmd) + rc = hw->hw_ops.process_cmd(hw->hw_priv, + CAM_CDM_HW_INTF_DUMP_DBG_REGS, + &handle, + sizeof(handle)); + } + put_cdm_mgr_refcount(); + + return rc; +} + +int cam_cdm_intf_register_hw_cdm(struct cam_hw_intf *hw, + struct cam_cdm_private_dt_data *data, enum cam_cdm_type type, + uint32_t *index) +{ + int rc = -EINVAL; + + if ((!hw) || (!data) || (!index)) + return rc; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + return rc; + } + + mutex_lock(&cam_cdm_mgr_lock); + if ((type == CAM_VIRTUAL_CDM) && + (!cdm_mgr.nodes[CAM_SW_CDM_INDEX].device)) { + mutex_lock(&cdm_mgr.nodes[CAM_SW_CDM_INDEX].lock); + cdm_mgr.nodes[CAM_SW_CDM_INDEX].device = hw; + cdm_mgr.nodes[CAM_SW_CDM_INDEX].data = data; + *index = cdm_mgr.cdm_count; + mutex_unlock(&cdm_mgr.nodes[CAM_SW_CDM_INDEX].lock); + cdm_mgr.cdm_count++; + rc = 0; + } else if ((type == CAM_HW_CDM) && (cdm_mgr.cdm_count > 0)) { + mutex_lock(&cdm_mgr.nodes[cdm_mgr.cdm_count].lock); + cdm_mgr.nodes[cdm_mgr.cdm_count].device = hw; + cdm_mgr.nodes[cdm_mgr.cdm_count].data = data; + *index = cdm_mgr.cdm_count; + mutex_unlock(&cdm_mgr.nodes[cdm_mgr.cdm_count].lock); + cdm_mgr.cdm_count++; + rc = 0; + } else { + CAM_ERR(CAM_CDM, "CDM registration failed type=%d count=%d", + type, cdm_mgr.cdm_count); + } + mutex_unlock(&cam_cdm_mgr_lock); + put_cdm_mgr_refcount(); + + return rc; +} + +int cam_cdm_intf_deregister_hw_cdm(struct cam_hw_intf *hw, + struct cam_cdm_private_dt_data *data, enum cam_cdm_type type, + uint32_t index) +{ + int rc = -EINVAL; + + if ((!hw) || (!data)) + return rc; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + rc = -EPERM; + return rc; + } + + mutex_lock(&cam_cdm_mgr_lock); + if ((type == CAM_VIRTUAL_CDM) && + (hw == cdm_mgr.nodes[CAM_SW_CDM_INDEX].device) && + (index == CAM_SW_CDM_INDEX)) { + mutex_lock(&cdm_mgr.nodes[cdm_mgr.cdm_count].lock); + cdm_mgr.nodes[CAM_SW_CDM_INDEX].device = NULL; + cdm_mgr.nodes[CAM_SW_CDM_INDEX].data = NULL; + mutex_unlock(&cdm_mgr.nodes[cdm_mgr.cdm_count].lock); + rc = 0; + } else if ((type == CAM_HW_CDM) && + (hw == cdm_mgr.nodes[index].device)) { + mutex_lock(&cdm_mgr.nodes[index].lock); + cdm_mgr.nodes[index].device = NULL; + cdm_mgr.nodes[index].data = NULL; + mutex_unlock(&cdm_mgr.nodes[index].lock); + cdm_mgr.cdm_count--; + rc = 0; + } else { + CAM_ERR(CAM_CDM, "CDM Deregistration failed type=%d index=%d", + type, index); + } + mutex_unlock(&cam_cdm_mgr_lock); + put_cdm_mgr_refcount(); + + return rc; +} + +static int cam_cdm_intf_probe(struct platform_device *pdev) +{ + int i, rc; + + rc = cam_cdm_intf_mgr_soc_get_dt_properties(pdev, &cdm_mgr); + if (rc) { + CAM_ERR(CAM_CDM, "Failed to get dt properties"); + return rc; + } + mutex_lock(&cam_cdm_mgr_lock); + for (i = 0 ; i < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM; i++) { + mutex_init(&cdm_mgr.nodes[i].lock); + cdm_mgr.nodes[i].device = NULL; + cdm_mgr.nodes[i].data = NULL; + cdm_mgr.nodes[i].refcount = 0; + } + cdm_mgr.probe_done = true; + cdm_mgr.refcount = 0; + mutex_unlock(&cam_cdm_mgr_lock); + rc = cam_virtual_cdm_probe(pdev); + if (rc) { + mutex_lock(&cam_cdm_mgr_lock); + cdm_mgr.probe_done = false; + for (i = 0 ; i < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM; i++) { + if (cdm_mgr.nodes[i].device || cdm_mgr.nodes[i].data || + (cdm_mgr.nodes[i].refcount != 0)) + CAM_ERR(CAM_CDM, + "Valid node present in index=%d", i); + mutex_destroy(&cdm_mgr.nodes[i].lock); + cdm_mgr.nodes[i].device = NULL; + cdm_mgr.nodes[i].data = NULL; + cdm_mgr.nodes[i].refcount = 0; + } + mutex_unlock(&cam_cdm_mgr_lock); + } + + CAM_DBG(CAM_CDM, "CDM Intf probe done"); + + return rc; +} + +static int cam_cdm_intf_remove(struct platform_device *pdev) +{ + int i, rc = -EBUSY; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + return rc; + } + + if (cam_virtual_cdm_remove(pdev)) { + CAM_ERR(CAM_CDM, "Virtual CDM remove failed"); + goto end; + } + put_cdm_mgr_refcount(); + + mutex_lock(&cam_cdm_mgr_lock); + if (cdm_mgr.refcount != 0) { + CAM_ERR(CAM_CDM, "cdm manger refcount not zero %d", + cdm_mgr.refcount); + goto end; + } + + for (i = 0 ; i < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM; i++) { + if (cdm_mgr.nodes[i].device || cdm_mgr.nodes[i].data || + (cdm_mgr.nodes[i].refcount != 0)) { + CAM_ERR(CAM_CDM, "Valid node present in index=%d", i); + mutex_unlock(&cam_cdm_mgr_lock); + goto end; + } + mutex_destroy(&cdm_mgr.nodes[i].lock); + cdm_mgr.nodes[i].device = NULL; + cdm_mgr.nodes[i].data = NULL; + cdm_mgr.nodes[i].refcount = 0; + } + cdm_mgr.probe_done = false; + rc = 0; + +end: + mutex_unlock(&cam_cdm_mgr_lock); + return rc; +} + +static struct platform_driver cam_cdm_intf_driver = { + .probe = cam_cdm_intf_probe, + .remove = cam_cdm_intf_remove, + .driver = { + .name = "msm_cam_cdm_intf", + .owner = THIS_MODULE, + .of_match_table = msm_cam_cdm_intf_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_cdm_intf_init_module(void) +{ + return platform_driver_register(&cam_cdm_intf_driver); +} + +static void __exit cam_cdm_intf_exit_module(void) +{ + platform_driver_unregister(&cam_cdm_intf_driver); +} + +module_init(cam_cdm_intf_init_module); +module_exit(cam_cdm_intf_exit_module); +MODULE_DESCRIPTION("MSM Camera CDM Intf driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_intf_api.h b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_intf_api.h new file mode 100644 index 0000000000000000000000000000000000000000..1e9cc3455a0f5259e7579537c224dfc93a34f6f3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_intf_api.h @@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CDM_API_H_ +#define _CAM_CDM_API_H_ + +#include +#include "cam_cdm_util.h" +#include "cam_soc_util.h" + +#define CAM_CDM_BL_CMD_MAX 25 + +/* enum cam_cdm_id - Enum for possible CAM CDM hardwares */ +enum cam_cdm_id { + CAM_CDM_VIRTUAL, + CAM_CDM_HW_ANY, + CAM_CDM_CPAS, + CAM_CDM_IFE, + CAM_CDM_TFE, + CAM_CDM_OPE, + CAM_CDM_IPE0, + CAM_CDM_IPE1, + CAM_CDM_BPS, + CAM_CDM_VFE, + CAM_CDM_MAX +}; + +/* enum cam_cdm_cb_status - Enum for possible CAM CDM callback */ +enum cam_cdm_cb_status { + CAM_CDM_CB_STATUS_BL_SUCCESS, + CAM_CDM_CB_STATUS_INVALID_BL_CMD, + CAM_CDM_CB_STATUS_PAGEFAULT, + CAM_CDM_CB_STATUS_HW_RESET_ONGOING, + CAM_CDM_CB_STATUS_HW_RESET_DONE, + CAM_CDM_CB_STATUS_HW_FLUSH, + CAM_CDM_CB_STATUS_HW_RESUBMIT, + CAM_CDM_CB_STATUS_HW_ERROR, + CAM_CDM_CB_STATUS_UNKNOWN_ERROR, +}; + +/* enum cam_cdm_bl_cmd_addr_type - Enum for possible CDM bl cmd addr types */ +enum cam_cdm_bl_cmd_addr_type { + CAM_CDM_BL_CMD_TYPE_MEM_HANDLE, + CAM_CDM_BL_CMD_TYPE_HW_IOVA, + CAM_CDM_BL_CMD_TYPE_KERNEL_IOVA, +}; + +/* enum cam_cdm_bl_fifo - interface commands.*/ +enum cam_cdm_bl_fifo_queue { + CAM_CDM_BL_FIFO_0, + CAM_CDM_BL_FIFO_1, + CAM_CDM_BL_FIFO_2, + CAM_CDM_BL_FIFO_3, + CAM_CDM_BL_FIFO_MAX, +}; + +/** + * struct cam_cdm_acquire_data - Cam CDM acquire data structure + * + * @identifier : Input identifier string which is the device label from dt + * like vfe, ife, jpeg etc + * @cell_index : Input integer identifier pointing to the cell index from dt + * of the device. This can be used to form a unique string + * with @identifier like vfe0, ife1, jpeg0 etc + * @id : ID of a specific or any CDM HW which needs to be acquired. + * @userdata : Input private data which will be returned as part + * of callback. + * @cam_cdm_callback : Input callback pointer for triggering the + * callbacks from CDM driver + * @handle : CDM Client handle + * @userdata : Private data given at the time of acquire + * @status : Callback status + * @cookie : Cookie if the callback is gen irq status + * @base_array_cnt : Input number of ioremapped address pair pointing + * in base_array, needed only if selected cdm is a virtual. + * @base_array : Input pointer to ioremapped address pair arrary + * needed only if selected cdm is a virtual. + * @priority : Priority of the client. + * @cdm_version : CDM version is output while acquiring HW cdm and + * it is Input while acquiring virtual cdm. + * Currently fixing it to one version below + * acquire API. + * @ops : Output pointer updated by cdm driver to the CDM + * util ops for this HW version of CDM acquired. + * @handle : Output Unique handle generated for this acquire + * + */ +struct cam_cdm_acquire_data { + char identifier[128]; + uint32_t cell_index; + enum cam_cdm_id id; + void *userdata; + void (*cam_cdm_callback)(uint32_t handle, void *userdata, + enum cam_cdm_cb_status status, uint64_t cookie); + uint32_t base_array_cnt; + struct cam_soc_reg_map *base_array[CAM_SOC_MAX_BLOCK]; + enum cam_cdm_bl_fifo_queue priority; + struct cam_hw_version cdm_version; + struct cam_cdm_utils_ops *ops; + uint32_t handle; +}; + +/** + * struct cam_cdm_bl_cmd - Cam CDM HW bl command + * + * @bl_addr : Union of all three type for CDM BL commands + * @mem_handle : Input mem handle of bl cmd + * @offset : Input offset of the actual bl cmd in the memory pointed + * by mem_handle + * @len : Input length of the BL command, Cannot be more than 1MB and + * this is will be validated with offset+size of the memory pointed + * by mem_handle + * @enable_debug_gen_irq : bool flag to submit extra gen_irq afteR bl_command + * @arbitrate : bool flag to arbitrate on submitted BL boundary + */ +struct cam_cdm_bl_cmd { + union { + int32_t mem_handle; + uint32_t *hw_iova; + uintptr_t kernel_iova; + } bl_addr; + uint32_t offset; + uint32_t len; + bool enable_debug_gen_irq; + bool arbitrate; +}; + +/** + * struct cam_cdm_bl_request - Cam CDM HW base & length (BL) request + * + * @flag : 1 for callback needed and 0 for no callback when this BL + * request is done + * @userdata :Input private data which will be returned as part + * of callback if request for this bl request in flags. + * @cookie : Cookie if the callback is gen irq status + * @type : type of the submitted bl cmd address. + * @cmd_arrary_count : Input number of BL commands to be submitted to CDM + * @gen_irq_arb : enum for setting arbitration in gen_irq + * @bl_cmd_array : Input payload holding the BL cmd's arrary + * to be sumbitted. + * + */ +struct cam_cdm_bl_request { + int flag; + void *userdata; + uint64_t cookie; + enum cam_cdm_bl_cmd_addr_type type; + uint32_t cmd_arrary_count; + bool gen_irq_arb; + struct cam_cdm_bl_cmd cmd[1]; +}; + +/** + * struct cam_cdm_bl_data - last submiited CDM BL data + * + * @mem_handle : Input mem handle of bl cmd + * @hw_addr : Hw address of submitted Bl command + * @offset : Input offset of the actual bl cmd in the memory pointed + * by mem_handle + * @len : length of submitted Bl command to CDM. + * @input_len : Input length of the BL command, Cannot be more than 1MB and + * this is will be validated with offset+size of the memory pointed + * by mem_handle + * @type : CDM bl cmd addr types. + */ +struct cam_cdm_bl_data { + int32_t mem_handle; + dma_addr_t hw_addr; + uint32_t offset; + size_t len; + uint32_t input_len; + enum cam_cdm_bl_cmd_addr_type type; +}; + +/** + * struct cam_cdm_bl_info + * + * @bl_count : No. of Bl commands submiited to CDM. + * @cmd : payload holding the BL cmd's arrary + * that is sumbitted. + * + */ +struct cam_cdm_bl_info { + int32_t bl_count; + struct cam_cdm_bl_data cmd[CAM_CDM_BL_CMD_MAX]; +}; + +/** + * @brief : API to get the CDM capabilities for a camera device type + * + * @identifier : Input pointer to a string which is the device label from dt + * like vfe, ife, jpeg etc, We do not need cell index + * assuming all devices of a single type maps to one SMMU + * client + * @cdm_handles : Input iommu handle memory pointer to update handles + * + * @return 0 on success + */ +int cam_cdm_get_iommu_handle(char *identifier, + struct cam_iommu_handle *cdm_handles); + +/** + * @brief : API to acquire a CDM + * + * @data : Input data for the CDM to be acquired + * + * @return 0 on success + */ +int cam_cdm_acquire(struct cam_cdm_acquire_data *data); + +/** + * @brief : API to release a previously acquired CDM + * + * @handle : Input handle for the CDM to be released + * + * @return 0 on success + */ +int cam_cdm_release(uint32_t handle); + +/** + * @brief : API to submit the base & length (BL's) for acquired CDM + * + * @handle : Input cdm handle to which the BL's needs to be sumbitted. + * @data : Input pointer to the BL's to be sumbitted + * + * @return 0 on success + */ +int cam_cdm_submit_bls(uint32_t handle, struct cam_cdm_bl_request *data); + +/** + * @brief : API to stream ON a previously acquired CDM, + * during this we turn on/off clocks/power based on active clients. + * + * @handle : Input handle for the CDM to be released + * + * @return 0 on success + */ +int cam_cdm_stream_on(uint32_t handle); + +/** + * @brief : API to stream OFF a previously acquired CDM, + * during this we turn on/off clocks/power based on active clients. + * + * @handle : Input handle for the CDM to be released + * + * @return 0 on success + */ +int cam_cdm_stream_off(uint32_t handle); + +/** + * @brief : API to reset previously acquired CDM, + * this should be only performed only if the CDM is private. + * + * @handle : Input handle of the CDM to reset + * + * @return 0 on success + */ +int cam_cdm_reset_hw(uint32_t handle); + +/** + * @brief : API to flush previously acquired CDM, + * this should be only performed only if the CDM is private. + * + * @handle : Input handle of the CDM to reset + * + * @return 0 on success + */ +int cam_cdm_flush_hw(uint32_t handle); + +/** + * @brief : API to detect culprit bl_tag in previously acquired CDM, + * this should be only performed only if the CDM is private. + * + * @handle : Input handle of the CDM to reset + * + * @return 0 on success + */ +int cam_cdm_handle_error(uint32_t handle); + +/** + * @brief : API get CDM ops + * + * @return : CDM operations + * + */ +struct cam_cdm_utils_ops *cam_cdm_publish_ops(void); + +/** + * @brief : API to detect hang in previously acquired CDM, + * this should be only performed only if the CDM is private. + * + * @handle : Input handle of the CDM to detect hang + * + * @return 0 on success + */ +int cam_cdm_detect_hang_error(uint32_t handle); + +/** + * @brief : API to dump the CDM Debug registers + * + * @handle : Input handle of the CDM to dump the registers + * + * @return 0 on success + */ +int cam_cdm_dump_debug_registers(uint32_t handle); +#endif /* _CAM_CDM_API_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_soc.c b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..11d2d0b10e5960f53d07ddb63732ddc411949cde --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_soc.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "cam_soc_util.h" +#include "cam_smmu_api.h" +#include "cam_cdm.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_cdm_soc.h" + +#define CAM_CDM_OFFSET_FROM_REG(x, y) ((x)->offsets[y].offset) +#define CAM_CDM_ATTR_FROM_REG(x, y) ((x)->offsets[y].attribute) + +bool cam_cdm_read_hw_reg(struct cam_hw_info *cdm_hw, + uint32_t reg, uint32_t *value) +{ + void __iomem *reg_addr; + void __iomem *base = + cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].mem_base; + resource_size_t mem_len = + cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].size; + + CAM_DBG(CAM_CDM, "E: b=%pK blen=%d off=%x", (void __iomem *)base, + (int)mem_len, reg); + + reg_addr = (base + reg); + if (reg_addr > (base + mem_len)) { + CAM_ERR_RATE_LIMIT(CAM_CDM, + "Invalid mapped region %d", reg); + goto permission_error; + } + *value = cam_io_r_mb(reg_addr); + CAM_DBG(CAM_CDM, "X b=%pK off=%x val=%x", + (void __iomem *)base, reg, + *value); + return false; + +permission_error: + *value = 0; + return true; + +} + +bool cam_cdm_write_hw_reg(struct cam_hw_info *cdm_hw, + uint32_t reg, uint32_t value) +{ + void __iomem *reg_addr; + void __iomem *base = + cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].mem_base; + resource_size_t mem_len = + cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].size; + + CAM_DBG(CAM_CDM, "E: b=%pK off=%x val=%x", (void __iomem *)base, + reg, value); + + reg_addr = (base + reg); + if (reg_addr > (base + mem_len)) { + CAM_ERR_RATE_LIMIT(CAM_CDM, + "Accessing invalid region:%d\n", + reg); + goto permission_error; + } + cam_io_w_mb(value, reg_addr); + return false; + +permission_error: + return true; + +} + +int cam_cdm_soc_load_dt_private(struct platform_device *pdev, + struct cam_cdm_private_dt_data *ptr) +{ + int i, rc = -EINVAL, num_fifo_entries = 0; + + ptr->dt_num_supported_clients = of_property_count_strings( + pdev->dev.of_node, + "cdm-client-names"); + CAM_DBG(CAM_CDM, "Num supported cdm_client = %d", + ptr->dt_num_supported_clients); + if (ptr->dt_num_supported_clients > + CAM_PER_CDM_MAX_REGISTERED_CLIENTS) { + CAM_ERR(CAM_CDM, "Invalid count of client names count=%d", + ptr->dt_num_supported_clients); + rc = -EINVAL; + goto end; + } + if (ptr->dt_num_supported_clients < 0) { + CAM_DBG(CAM_CDM, "No cdm client names found"); + ptr->dt_num_supported_clients = 0; + ptr->dt_cdm_shared = false; + } else { + ptr->dt_cdm_shared = true; + } + for (i = 0; i < ptr->dt_num_supported_clients; i++) { + rc = of_property_read_string_index(pdev->dev.of_node, + "cdm-client-names", i, &(ptr->dt_cdm_client_name[i])); + CAM_DBG(CAM_CDM, "cdm-client-names[%d] = %s", i, + ptr->dt_cdm_client_name[i]); + if (rc < 0) { + CAM_ERR(CAM_CDM, "Reading cdm-client-names failed"); + goto end; + } + } + + ptr->config_fifo = of_property_read_bool(pdev->dev.of_node, + "config-fifo"); + if (ptr->config_fifo) { + num_fifo_entries = of_property_count_u32_elems( + pdev->dev.of_node, + "fifo-depths"); + if (num_fifo_entries != CAM_CDM_NUM_BL_FIFO) { + CAM_ERR(CAM_CDM, + "Wrong number of configurable FIFOs %d", + num_fifo_entries); + rc = -EINVAL; + goto end; + } + for (i = 0; i < num_fifo_entries; i++) { + rc = of_property_read_u32_index(pdev->dev.of_node, + "fifo-depths", i, &ptr->fifo_depth[i]); + if (rc < 0) { + CAM_ERR(CAM_CDM, + "Unable to read fifo-depth rc %d", + rc); + goto end; + } + CAM_DBG(CAM_CDM, "FIFO%d depth is %d", + i, ptr->fifo_depth[i]); + } + } else { + for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) { + ptr->fifo_depth[i] = CAM_CDM_BL_FIFO_LENGTH_MAX_DEFAULT; + CAM_DBG(CAM_CDM, "FIFO%d depth is %d", + i, ptr->fifo_depth[i]); + } + } +end: + return rc; +} + +int cam_hw_cdm_soc_get_dt_properties(struct cam_hw_info *cdm_hw, + const struct of_device_id *table) +{ + int rc; + struct cam_hw_soc_info *soc_ptr; + const struct of_device_id *id; + struct cam_cdm *cdm_core = cdm_hw->core_info; + + if (!cdm_hw || (cdm_hw->soc_info.soc_private) + || !(cdm_hw->soc_info.pdev)) + return -EINVAL; + + soc_ptr = &cdm_hw->soc_info; + + rc = cam_soc_util_get_dt_properties(soc_ptr); + if (rc != 0) { + CAM_ERR(CAM_CDM, "Failed to retrieve the CDM dt properties"); + goto end; + } + + soc_ptr->soc_private = kzalloc( + sizeof(struct cam_cdm_private_dt_data), + GFP_KERNEL); + if (!soc_ptr->soc_private) + return -ENOMEM; + + rc = cam_cdm_soc_load_dt_private(soc_ptr->pdev, + soc_ptr->soc_private); + if (rc != 0) { + CAM_ERR(CAM_CDM, "Failed to load CDM dt private data"); + goto error; + } + + id = of_match_node(table, soc_ptr->pdev->dev.of_node); + if ((!id) || !(id->data)) { + CAM_ERR(CAM_CDM, "Failed to retrieve the CDM id table"); + goto error; + } + cdm_core->offsets = + (struct cam_cdm_hw_reg_offset *)id->data; + + CAM_DBG(CAM_CDM, "name %s", cdm_core->name); + + snprintf(cdm_core->name, sizeof(cdm_core->name) + 1, "%s%d", + id->compatible, soc_ptr->index); + + CAM_DBG(CAM_CDM, "name %s", cdm_core->name); + + goto end; + +error: + rc = -EINVAL; + kfree(soc_ptr->soc_private); + soc_ptr->soc_private = NULL; +end: + return rc; +} + +int cam_cdm_intf_mgr_soc_get_dt_properties( + struct platform_device *pdev, struct cam_cdm_intf_mgr *mgr) +{ + int rc; + + rc = of_property_read_u32(pdev->dev.of_node, + "num-hw-cdm", &mgr->dt_supported_hw_cdm); + CAM_DBG(CAM_CDM, "Number of HW cdm supported =%d", + mgr->dt_supported_hw_cdm); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_soc.h b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..320c406feac3ae2023217b5ca19b822211abe507 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_soc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CDM_SOC_H_ +#define _CAM_CDM_SOC_H_ + +#define CAM_HW_CDM_CPAS_0_NAME "qcom,cam170-cpas-cdm0" +#define CAM_HW_CDM_CPAS_NAME_1_0 "qcom,cam-cpas-cdm1_0" +#define CAM_HW_CDM_CPAS_NAME_1_1 "qcom,cam-cpas-cdm1_1" +#define CAM_HW_CDM_CPAS_NAME_1_2 "qcom,cam-cpas-cdm1_2" +#define CAM_HW_CDM_IFE_NAME_1_2 "qcom,cam-ife-cdm1_2" +#define CAM_HW_CDM_CPAS_NAME_2_0 "qcom,cam-cpas-cdm2_0" +#define CAM_HW_CDM_OPE_NAME_2_0 "qcom,cam-ope-cdm2_0" +#define CAM_HW_CDM_CPAS_NAME_2_1 "qcom,cam-cpas-cdm2_1" +#define CAM_HW_CDM_OPE_NAME_2_1 "qcom,cam-ope-cdm2_1" +#define CAM_HW_CDM_IFE_NAME_2_1 "qcom,cam-ife-cdm2_1" + +int cam_hw_cdm_soc_get_dt_properties(struct cam_hw_info *cdm_hw, + const struct of_device_id *table); +bool cam_cdm_read_hw_reg(struct cam_hw_info *cdm_hw, + uint32_t reg, uint32_t *value); +bool cam_cdm_write_hw_reg(struct cam_hw_info *cdm_hw, + uint32_t reg, uint32_t value); +int cam_cdm_intf_mgr_soc_get_dt_properties( + struct platform_device *pdev, + struct cam_cdm_intf_mgr *mgr); +int cam_cdm_soc_load_dt_private(struct platform_device *pdev, + struct cam_cdm_private_dt_data *ptr); + +#endif /* _CAM_CDM_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_util.c b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_util.c new file mode 100644 index 0000000000000000000000000000000000000000..d56ab6db35558a23e5260367a1a9ef7150162d9c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_util.c @@ -0,0 +1,1078 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "cam_cdm_intf_api.h" +#include "cam_cdm_util.h" +#include "cam_cdm.h" +#include "cam_io_util.h" + +#define CAM_CDM_DWORD 4 + +#define CAM_CDM_SW_CMD_COUNT 2 +#define CAM_CMD_LENGTH_MASK 0xFFFF +#define CAM_CDM_COMMAND_OFFSET 24 +#define CAM_CDM_REG_OFFSET_MASK 0x00FFFFFF + +#define CAM_CDM_DMI_DATA_HI_OFFSET 8 +#define CAM_CDM_DMI_DATA_OFFSET 8 +#define CAM_CDM_DMI_DATA_LO_OFFSET 12 + +static unsigned int CDMCmdHeaderSizes[ + CAM_CDM_CMD_PRIVATE_BASE + CAM_CDM_SW_CMD_COUNT] = { + 0, /* UNUSED*/ + 3, /* DMI*/ + 0, /* UNUSED*/ + 2, /* RegContinuous*/ + 1, /* RegRandom*/ + 2, /* BUFFER_INDIREC*/ + 2, /* GenerateIRQ*/ + 3, /* WaitForEvent*/ + 1, /* ChangeBase*/ + 1, /* PERF_CONTROL*/ + 3, /* DMI32*/ + 3, /* DMI64*/ + 3, /* WaitCompEvent*/ + 3, /* ClearCompEvent*/ + 3, /* WaitPrefetchDisable*/ +}; + +/** + * struct cdm_regrandom_cmd - Definition for CDM random register command. + * @count: Number of register writes + * @reserved: reserved bits + * @cmd: Command ID (CDMCmd) + */ +struct cdm_regrandom_cmd { + unsigned int count : 16; + unsigned int reserved : 8; + unsigned int cmd : 8; +} __attribute__((__packed__)); + +/** + * struct cdm_regcontinuous_cmd - Definition for a CDM register range command. + * @count: Number of register writes + * @reserved0: reserved bits + * @cmd: Command ID (CDMCmd) + * @offset: Start address of the range of registers + * @reserved1: reserved bits + */ +struct cdm_regcontinuous_cmd { + unsigned int count : 16; + unsigned int reserved0 : 8; + unsigned int cmd : 8; + unsigned int offset : 24; + unsigned int reserved1 : 8; +} __attribute__((__packed__)); + +/** + * struct cdm_dmi_cmd - Definition for a CDM DMI command. + * @length: Number of bytes in LUT - 1 + * @reserved: reserved bits + * @cmd: Command ID (CDMCmd) + * @addr: Address of the LUT in memory + * @DMIAddr: Address of the target DMI config register + * @DMISel: DMI identifier + */ +struct cdm_dmi_cmd { + unsigned int length : 16; + unsigned int reserved : 8; + unsigned int cmd : 8; + unsigned int addr; + unsigned int DMIAddr : 24; + unsigned int DMISel : 8; +} __attribute__((__packed__)); + +/** + * struct cdm_indirect_cmd - Definition for a CDM indirect buffer command. + * @length: Number of bytes in buffer - 1 + * @reserved: reserved bits + * @cmd: Command ID (CDMCmd) + * @addr: Device address of the indirect buffer + */ +struct cdm_indirect_cmd { + unsigned int length : 16; + unsigned int reserved : 8; + unsigned int cmd : 8; + unsigned int addr; +} __attribute__((__packed__)); + +/** + * struct cdm_changebase_cmd - Definition for CDM base address change command. + * @base: Base address to be changed to + * @cmd:Command ID (CDMCmd) + */ +struct cdm_changebase_cmd { + unsigned int base : 24; + unsigned int cmd : 8; +} __attribute__((__packed__)); + +/** + * struct cdm_wait_event_cmd - Definition for a CDM Gen IRQ command. + * @mask: Mask for the events + * @id: ID to read back for debug + * @iw_reserved: reserved bits + * @iw: iw AHB write bit + * @cmd:Command ID (CDMCmd) + * @offset: Offset to where data is written + * @offset_reserved: reserved bits + * @data: data returned in IRQ_USR_DATA + */ +struct cdm_wait_event_cmd { + unsigned int mask : 8; + unsigned int id : 8; + unsigned int iw_reserved : 7; + unsigned int iw : 1; + unsigned int cmd : 8; + unsigned int offset : 24; + unsigned int offset_reserved : 8; + unsigned int data; +} __attribute__((__packed__)); + +/** + * struct cdm_genirq_cmd - Definition for a CDM Wait event command. + * @reserved: reserved bits + * @cmd:Command ID (CDMCmd) + * @userdata: userdata returned in IRQ_USR_DATA + */ +struct cdm_genirq_cmd { + unsigned int reserved : 24; + unsigned int cmd : 8; + unsigned int userdata; +} __attribute__((__packed__)); + +/** + * struct cdm_perf_ctrl_cmd_t - Definition for CDM perf control command. + * @perf: perf command + * @reserved: reserved bits + * @cmd:Command ID (CDMCmd) + */ +struct cdm_perf_ctrl_cmd { + unsigned int perf : 2; + unsigned int reserved : 22; + unsigned int cmd : 8; +} __attribute__((__packed__)); + +struct cdm_wait_comp_event_cmd { + unsigned int reserved : 8; + unsigned int id : 8; + unsigned int id_reserved: 8; + unsigned int cmd : 8; + unsigned int mask1; + unsigned int mask2; +} __attribute__((__packed__)); + +struct cdm_clear_comp_event_cmd { + unsigned int reserved : 8; + unsigned int id : 8; + unsigned int id_reserved: 8; + unsigned int cmd : 8; + unsigned int mask1; + unsigned int mask2; +} __attribute__((__packed__)); + +struct cdm_prefetch_disable_event_cmd { + unsigned int reserved : 8; + unsigned int id : 8; + unsigned int id_reserved: 8; + unsigned int cmd : 8; + unsigned int mask1; + unsigned int mask2; +} __attribute__((__packed__)); + +uint32_t cdm_get_cmd_header_size(unsigned int command) +{ + return CDMCmdHeaderSizes[command]; +} + +uint32_t cdm_required_size_dmi(void) +{ + return cdm_get_cmd_header_size(CAM_CDM_CMD_DMI); +} + +uint32_t cdm_required_size_reg_continuous(uint32_t numVals) +{ + return cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT) + numVals; +} + +uint32_t cdm_required_size_reg_random(uint32_t numRegVals) +{ + return cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM) + + (2 * numRegVals); +} + +uint32_t cdm_required_size_indirect(void) +{ + return cdm_get_cmd_header_size(CAM_CDM_CMD_BUFF_INDIRECT); +} + +uint32_t cdm_required_size_genirq(void) +{ + return cdm_get_cmd_header_size(CAM_CDM_CMD_GEN_IRQ); +} + +uint32_t cdm_required_size_wait_event(void) +{ + return cdm_get_cmd_header_size(CAM_CDM_CMD_WAIT_EVENT); +} + +uint32_t cdm_required_size_changebase(void) +{ + return cdm_get_cmd_header_size(CAM_CDM_CMD_CHANGE_BASE); +} + +uint32_t cdm_required_size_comp_wait(void) +{ + return cdm_get_cmd_header_size(CAM_CDM_COMP_WAIT); +} + +uint32_t cdm_required_size_clear_comp_event(void) +{ + return cdm_get_cmd_header_size(CAM_CDM_CLEAR_COMP_WAIT); +} + +uint32_t cdm_required_size_prefetch_disable(void) +{ + return cdm_get_cmd_header_size(CAM_CDM_WAIT_PREFETCH_DISABLE); +} + +uint32_t cdm_offsetof_dmi_addr(void) +{ + return offsetof(struct cdm_dmi_cmd, addr); +} + +uint32_t cdm_offsetof_indirect_addr(void) +{ + return offsetof(struct cdm_indirect_cmd, addr); +} + +uint32_t *cdm_write_dmi(uint32_t *pCmdBuffer, uint8_t dmiCmd, + uint32_t DMIAddr, uint8_t DMISel, uint32_t dmiBufferAddr, + uint32_t length) +{ + struct cdm_dmi_cmd *pHeader = (struct cdm_dmi_cmd *)pCmdBuffer; + + pHeader->cmd = CAM_CDM_CMD_DMI; + pHeader->addr = dmiBufferAddr; + pHeader->length = length; + pHeader->DMIAddr = DMIAddr; + pHeader->DMISel = DMISel; + + pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_DMI); + + return pCmdBuffer; +} + +uint32_t *cdm_write_regcontinuous(uint32_t *pCmdBuffer, uint32_t reg, + uint32_t numVals, uint32_t *pVals) +{ + uint32_t i; + struct cdm_regcontinuous_cmd *pHeader = + (struct cdm_regcontinuous_cmd *)pCmdBuffer; + + pHeader->count = numVals; + pHeader->cmd = CAM_CDM_CMD_REG_CONT; + pHeader->reserved0 = 0; + pHeader->reserved1 = 0; + pHeader->offset = reg; + + pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT); + + for (i = 0; i < numVals; i++) + (((uint32_t *)pCmdBuffer)[i]) = (((uint32_t *)pVals)[i]); + + pCmdBuffer += numVals; + + return pCmdBuffer; +} + +uint32_t *cdm_write_regrandom(uint32_t *pCmdBuffer, uint32_t numRegVals, + uint32_t *pRegVals) +{ + uint32_t i; + uint32_t *dst, *src; + struct cdm_regrandom_cmd *pHeader = + (struct cdm_regrandom_cmd *)pCmdBuffer; + + pHeader->count = numRegVals; + pHeader->cmd = CAM_CDM_CMD_REG_RANDOM; + pHeader->reserved = 0; + + pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM); + dst = pCmdBuffer; + src = pRegVals; + for (i = 0; i < numRegVals; i++) { + *dst++ = *src++; + *dst++ = *src++; + } + + return dst; +} + +uint32_t *cdm_write_indirect(uint32_t *pCmdBuffer, uint32_t indirectBufAddr, + uint32_t length) +{ + struct cdm_indirect_cmd *pHeader = + (struct cdm_indirect_cmd *)pCmdBuffer; + + pHeader->cmd = CAM_CDM_CMD_BUFF_INDIRECT; + pHeader->addr = indirectBufAddr; + pHeader->length = length - 1; + + pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_BUFF_INDIRECT); + + return pCmdBuffer; +} + +void cdm_write_genirq(uint32_t *pCmdBuffer, uint32_t userdata, + bool bit_wr_enable, uint32_t fifo_idx) +{ + struct cdm_genirq_cmd *pHeader = (struct cdm_genirq_cmd *)pCmdBuffer; + + CAM_DBG(CAM_CDM, "userdata 0x%x, fifo_idx %d", + userdata, fifo_idx); + + if (bit_wr_enable) + pHeader->reserved = (unsigned int)((fifo_idx << 1) + | (unsigned int)(bit_wr_enable)); + + pHeader->cmd = CAM_CDM_CMD_GEN_IRQ; + pHeader->userdata = (userdata << (8 * fifo_idx)); +} + +uint32_t *cdm_write_wait_event(uint32_t *pcmdbuffer, uint32_t iw, + uint32_t id, uint32_t mask, + uint32_t offset, uint32_t data) +{ + struct cdm_wait_event_cmd *pheader = + (struct cdm_wait_event_cmd *)pcmdbuffer; + + pheader->cmd = CAM_CDM_CMD_WAIT_EVENT; + pheader->mask = mask; + pheader->data = data; + pheader->id = id; + pheader->iw = iw; + pheader->offset = offset; + pheader->iw_reserved = 0; + pheader->offset_reserved = 0; + + pcmdbuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_WAIT_EVENT); + + return pcmdbuffer; +} + +uint32_t *cdm_write_changebase(uint32_t *pCmdBuffer, uint32_t base) +{ + struct cdm_changebase_cmd *pHeader = + (struct cdm_changebase_cmd *)pCmdBuffer; + + CAM_DBG(CAM_CDM, "Change to base 0x%x", base); + + pHeader->cmd = CAM_CDM_CMD_CHANGE_BASE; + pHeader->base = base; + pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_CHANGE_BASE); + + return pCmdBuffer; +} + +uint32_t *cdm_write_wait_comp_event( + uint32_t *pCmdBuffer, uint32_t mask1, uint32_t mask2) +{ + struct cdm_wait_comp_event_cmd *pHeader = + (struct cdm_wait_comp_event_cmd *)pCmdBuffer; + + pHeader->cmd = CAM_CDM_COMP_WAIT; + pHeader->mask1 = mask1; + pHeader->mask2 = mask2; + + pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_COMP_WAIT); + + return pCmdBuffer; +} + +uint32_t *cdm_write_clear_comp_event( + uint32_t *pCmdBuffer, uint32_t mask1, uint32_t mask2) +{ + struct cdm_clear_comp_event_cmd *pHeader = + (struct cdm_clear_comp_event_cmd *)pCmdBuffer; + + pHeader->cmd = CAM_CDM_CLEAR_COMP_WAIT; + pHeader->mask1 = mask1; + pHeader->mask2 = mask2; + + pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CLEAR_COMP_WAIT); + + return pCmdBuffer; +} + +uint32_t *cdm_write_wait_prefetch_disable( + uint32_t *pCmdBuffer, + uint32_t id, + uint32_t mask1, + uint32_t mask2) +{ + struct cdm_prefetch_disable_event_cmd *pHeader = + (struct cdm_prefetch_disable_event_cmd *)pCmdBuffer; + + pHeader->cmd = CAM_CDM_WAIT_PREFETCH_DISABLE; + pHeader->id = id; + pHeader->mask1 = mask1; + pHeader->mask2 = mask2; + + pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_WAIT_PREFETCH_DISABLE); + + return pCmdBuffer; +} + + +struct cam_cdm_utils_ops CDM170_ops = { + cdm_get_cmd_header_size, + cdm_required_size_dmi, + cdm_required_size_reg_continuous, + cdm_required_size_reg_random, + cdm_required_size_indirect, + cdm_required_size_genirq, + cdm_required_size_wait_event, + cdm_required_size_changebase, + cdm_required_size_comp_wait, + cdm_required_size_clear_comp_event, + cdm_required_size_prefetch_disable, + cdm_offsetof_dmi_addr, + cdm_offsetof_indirect_addr, + cdm_write_dmi, + cdm_write_regcontinuous, + cdm_write_regrandom, + cdm_write_indirect, + cdm_write_genirq, + cdm_write_wait_event, + cdm_write_changebase, + cdm_write_wait_comp_event, + cdm_write_clear_comp_event, + cdm_write_wait_prefetch_disable, +}; + +int cam_cdm_get_ioremap_from_base(uint32_t hw_base, + uint32_t base_array_size, + struct cam_soc_reg_map *base_table[CAM_SOC_MAX_BLOCK], + void __iomem **device_base) +{ + int ret = -EINVAL, i; + + for (i = 0; i < base_array_size; i++) { + if (base_table[i]) + CAM_DBG(CAM_CDM, "In loop %d ioremap for %x addr=%x", + i, (base_table[i])->mem_cam_base, hw_base); + if ((base_table[i]) && + ((base_table[i])->mem_cam_base == hw_base)) { + *device_base = (base_table[i])->mem_base; + ret = 0; + break; + } + } + + return ret; +} + +static int cam_cdm_util_reg_cont_write(void __iomem *base_addr, + uint32_t *cmd_buf, uint32_t cmd_buf_size, uint32_t *used_bytes) +{ + int ret = 0; + uint32_t *data; + struct cdm_regcontinuous_cmd *reg_cont; + + if ((cmd_buf_size < cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT)) || + (!base_addr)) { + CAM_ERR(CAM_CDM, "invalid base addr and data length %d %pK", + cmd_buf_size, base_addr); + return -EINVAL; + } + + reg_cont = (struct cdm_regcontinuous_cmd *)cmd_buf; + if ((!reg_cont->count) || (reg_cont->count > 0x10000) || + (((reg_cont->count * sizeof(uint32_t)) + + cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT)) > + cmd_buf_size)) { + CAM_ERR(CAM_CDM, "buffer size %d is not sufficient for count%d", + cmd_buf_size, reg_cont->count); + return -EINVAL; + } + data = cmd_buf + cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT); + cam_io_memcpy(base_addr + reg_cont->offset, data, + reg_cont->count * sizeof(uint32_t)); + + *used_bytes = (reg_cont->count * sizeof(uint32_t)) + + (4 * cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT)); + + return ret; +} + +static int cam_cdm_util_reg_random_write(void __iomem *base_addr, + uint32_t *cmd_buf, uint32_t cmd_buf_size, uint32_t *used_bytes) +{ + uint32_t i; + struct cdm_regrandom_cmd *reg_random; + uint32_t *data; + + if (!base_addr) { + CAM_ERR(CAM_CDM, "invalid base address"); + return -EINVAL; + } + + reg_random = (struct cdm_regrandom_cmd *) cmd_buf; + if ((!reg_random->count) || (reg_random->count > 0x10000) || + (((reg_random->count * (sizeof(uint32_t) * 2)) + + cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM)) > + cmd_buf_size)) { + CAM_ERR(CAM_CDM, "invalid reg_count %d cmd_buf_size %d", + reg_random->count, cmd_buf_size); + return -EINVAL; + } + data = cmd_buf + cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM); + + for (i = 0; i < reg_random->count; i++) { + CAM_DBG(CAM_CDM, "reg random: offset %pK, value 0x%x", + ((void __iomem *)(base_addr + data[0])), + data[1]); + cam_io_w(data[1], base_addr + data[0]); + data += 2; + } + + *used_bytes = ((reg_random->count * (sizeof(uint32_t) * 2)) + + (4 * cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM))); + + return 0; +} + +static int cam_cdm_util_swd_dmi_write(uint32_t cdm_cmd_type, + void __iomem *base_addr, uint32_t *cmd_buf, uint32_t cmd_buf_size, + uint32_t *used_bytes) +{ + uint32_t i; + struct cdm_dmi_cmd *swd_dmi; + uint32_t *data; + + swd_dmi = (struct cdm_dmi_cmd *)cmd_buf; + + if (cmd_buf_size < (cdm_required_size_dmi() + swd_dmi->length + 1)) { + CAM_ERR(CAM_CDM, "invalid CDM_SWD_DMI length %d", + swd_dmi->length + 1); + return -EINVAL; + } + data = cmd_buf + cdm_required_size_dmi(); + + if (cdm_cmd_type == CAM_CDM_CMD_SWD_DMI_64) { + for (i = 0; i < (swd_dmi->length + 1)/8; i++) { + cam_io_w_mb(data[0], base_addr + + swd_dmi->DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET); + cam_io_w_mb(data[1], base_addr + + swd_dmi->DMIAddr + CAM_CDM_DMI_DATA_HI_OFFSET); + data += 2; + } + } else if (cdm_cmd_type == CAM_CDM_CMD_DMI) { + for (i = 0; i < (swd_dmi->length + 1)/4; i++) { + cam_io_w_mb(data[0], base_addr + + swd_dmi->DMIAddr + CAM_CDM_DMI_DATA_OFFSET); + data += 1; + } + } else { + for (i = 0; i < (swd_dmi->length + 1)/4; i++) { + cam_io_w_mb(data[0], base_addr + + swd_dmi->DMIAddr + CAM_CDM_DMI_DATA_LO_OFFSET); + data += 1; + } + } + *used_bytes = (4 * cdm_required_size_dmi()) + swd_dmi->length + 1; + + return 0; +} + +int cam_cdm_util_cmd_buf_write(void __iomem **current_device_base, + uint32_t *cmd_buf, uint32_t cmd_buf_size, + struct cam_soc_reg_map *base_table[CAM_SOC_MAX_BLOCK], + uint32_t base_array_size, uint8_t bl_tag) +{ + int ret = 0; + uint32_t cdm_cmd_type = 0, total_cmd_buf_size = 0; + uint32_t used_bytes = 0; + + total_cmd_buf_size = cmd_buf_size; + + while (cmd_buf_size > 0) { + CAM_DBG(CAM_CDM, "cmd data=%x", *cmd_buf); + cdm_cmd_type = (*cmd_buf >> CAM_CDM_COMMAND_OFFSET); + switch (cdm_cmd_type) { + case CAM_CDM_CMD_REG_CONT: { + ret = cam_cdm_util_reg_cont_write(*current_device_base, + cmd_buf, cmd_buf_size, &used_bytes); + if (ret) + break; + + if (used_bytes > 0) { + cmd_buf_size -= used_bytes; + cmd_buf += used_bytes/4; + } + } + break; + case CAM_CDM_CMD_REG_RANDOM: { + ret = cam_cdm_util_reg_random_write( + *current_device_base, cmd_buf, cmd_buf_size, + &used_bytes); + if (ret) + break; + + if (used_bytes > 0) { + cmd_buf_size -= used_bytes; + cmd_buf += used_bytes / 4; + } + } + break; + case CAM_CDM_CMD_DMI: + case CAM_CDM_CMD_SWD_DMI_32: + case CAM_CDM_CMD_SWD_DMI_64: { + if (*current_device_base == 0) { + CAM_ERR(CAM_CDM, + "Got SWI DMI cmd =%d for invalid hw", + cdm_cmd_type); + ret = -EINVAL; + break; + } + ret = cam_cdm_util_swd_dmi_write(cdm_cmd_type, + *current_device_base, cmd_buf, cmd_buf_size, + &used_bytes); + if (ret) + break; + + if (used_bytes > 0) { + cmd_buf_size -= used_bytes; + cmd_buf += used_bytes / 4; + } + } + break; + case CAM_CDM_CMD_CHANGE_BASE: { + struct cdm_changebase_cmd *change_base_cmd = + (struct cdm_changebase_cmd *)cmd_buf; + + ret = cam_cdm_get_ioremap_from_base( + change_base_cmd->base, base_array_size, + base_table, current_device_base); + if (ret != 0) { + CAM_ERR(CAM_CDM, + "Get ioremap change base failed %x", + change_base_cmd->base); + break; + } + CAM_DBG(CAM_CDM, "Got ioremap for %x addr=%pK", + change_base_cmd->base, + current_device_base); + cmd_buf_size -= (4 * + cdm_required_size_changebase()); + cmd_buf += cdm_required_size_changebase(); + } + break; + default: + CAM_ERR(CAM_CDM, "unsupported cdm_cmd_type type 0%x", + cdm_cmd_type); + ret = -EINVAL; + break; + } + + if (ret < 0) + break; + } + + return ret; +} + +static long cam_cdm_util_dump_dmi_cmd(uint32_t *cmd_buf_addr, + uint32_t *cmd_buf_addr_end) +{ + long ret = 0; + struct cdm_dmi_cmd *p_dmi_cmd; + uint32_t *temp_ptr = cmd_buf_addr; + + p_dmi_cmd = (struct cdm_dmi_cmd *)cmd_buf_addr; + temp_ptr += CDMCmdHeaderSizes[CAM_CDM_CMD_DMI]; + ret += CDMCmdHeaderSizes[CAM_CDM_CMD_DMI]; + + if (temp_ptr > cmd_buf_addr_end) + CAM_ERR(CAM_CDM, + "Invalid cmd start addr:%pK end addr:%pK", + temp_ptr, cmd_buf_addr_end); + + CAM_INFO(CAM_CDM, + "DMI: LEN: %u DMIAddr: 0x%X DMISel: 0x%X LUT_addr: 0x%X", + p_dmi_cmd->length, p_dmi_cmd->DMIAddr, + p_dmi_cmd->DMISel, p_dmi_cmd->addr); + return ret; +} + +static long cam_cdm_util_dump_buff_indirect(uint32_t *cmd_buf_addr, + uint32_t *cmd_buf_addr_end) +{ + long ret = 0; + struct cdm_indirect_cmd *p_indirect_cmd; + uint32_t *temp_ptr = cmd_buf_addr; + + p_indirect_cmd = (struct cdm_indirect_cmd *)cmd_buf_addr; + temp_ptr += CDMCmdHeaderSizes[CAM_CDM_CMD_BUFF_INDIRECT]; + ret += CDMCmdHeaderSizes[CAM_CDM_CMD_BUFF_INDIRECT]; + + if (temp_ptr > cmd_buf_addr_end) + CAM_ERR(CAM_CDM, + "Invalid cmd start addr:%pK end addr:%pK", + temp_ptr, cmd_buf_addr_end); + + CAM_INFO(CAM_CDM, + "Buff Indirect: LEN: %u addr: 0x%X", + p_indirect_cmd->length, p_indirect_cmd->addr); + return ret; +} + +static long cam_cdm_util_dump_reg_cont_cmd(uint32_t *cmd_buf_addr, + uint32_t *cmd_buf_addr_end) +{ + long ret = 0; + struct cdm_regcontinuous_cmd *p_regcont_cmd; + uint32_t *temp_ptr = cmd_buf_addr; + int i = 0; + + p_regcont_cmd = (struct cdm_regcontinuous_cmd *)temp_ptr; + temp_ptr += CDMCmdHeaderSizes[CAM_CDM_CMD_REG_CONT]; + ret += CDMCmdHeaderSizes[CAM_CDM_CMD_REG_CONT]; + + CAM_INFO(CAM_CDM, "REG_CONT: COUNT: %u OFFSET: 0x%X", + p_regcont_cmd->count, p_regcont_cmd->offset); + + for (i = 0; i < p_regcont_cmd->count; i++) { + if (temp_ptr > cmd_buf_addr_end) { + CAM_ERR(CAM_CDM, + "Invalid cmd(%d) start addr:%pK end addr:%pK", + i, temp_ptr, cmd_buf_addr_end); + break; + } + CAM_INFO(CAM_CDM, "DATA_%d: 0x%X", i, + *temp_ptr); + temp_ptr++; + ret++; + } + + return ret; +} + +static long cam_cdm_util_dump_reg_random_cmd(uint32_t *cmd_buf_addr, + uint32_t *cmd_buf_addr_end) +{ + struct cdm_regrandom_cmd *p_regrand_cmd; + uint32_t *temp_ptr = cmd_buf_addr; + long ret = 0; + int i = 0; + + p_regrand_cmd = (struct cdm_regrandom_cmd *)temp_ptr; + temp_ptr += CDMCmdHeaderSizes[CAM_CDM_CMD_REG_RANDOM]; + ret += CDMCmdHeaderSizes[CAM_CDM_CMD_REG_RANDOM]; + + CAM_INFO(CAM_CDM, "REG_RAND: COUNT: %u", + p_regrand_cmd->count); + + for (i = 0; i < p_regrand_cmd->count; i++) { + if (temp_ptr > cmd_buf_addr_end) { + CAM_ERR(CAM_CDM, + "Invalid cmd(%d) start addr:%pK end addr:%pK", + i, temp_ptr, cmd_buf_addr_end); + break; + } + CAM_INFO(CAM_CDM, "OFFSET_%d: 0x%X DATA_%d: 0x%X", + i, *temp_ptr & CAM_CDM_REG_OFFSET_MASK, i, + *(temp_ptr + 1)); + temp_ptr += 2; + ret += 2; + } + + return ret; +} + +static long cam_cdm_util_dump_gen_irq_cmd(uint32_t *cmd_buf_addr) +{ + long ret = 0; + + ret += CDMCmdHeaderSizes[CAM_CDM_CMD_GEN_IRQ]; + + CAM_INFO(CAM_CDM, "GEN_IRQ"); + + return ret; +} + +static long cam_cdm_util_dump_wait_event_cmd(uint32_t *cmd_buf_addr) +{ + long ret = 0; + + ret += CDMCmdHeaderSizes[CAM_CDM_CMD_WAIT_EVENT]; + + CAM_INFO(CAM_CDM, "WAIT_EVENT"); + + return ret; +} + +static long cam_cdm_util_dump_change_base_cmd(uint32_t *cmd_buf_addr, + uint32_t *cmd_buf_addr_end) +{ + long ret = 0; + struct cdm_changebase_cmd *p_cbase_cmd; + uint32_t *temp_ptr = cmd_buf_addr; + + p_cbase_cmd = (struct cdm_changebase_cmd *)temp_ptr; + temp_ptr += CDMCmdHeaderSizes[CAM_CDM_CMD_CHANGE_BASE]; + ret += CDMCmdHeaderSizes[CAM_CDM_CMD_CHANGE_BASE]; + + if (temp_ptr > cmd_buf_addr_end) + CAM_ERR(CAM_CDM, + "Invalid cmd start addr:%pK end addr:%pK", + temp_ptr, cmd_buf_addr_end); + + CAM_INFO(CAM_CDM, "CHANGE_BASE: 0x%X", + p_cbase_cmd->base); + + return ret; +} + +static long cam_cdm_util_dump_perf_ctrl_cmd(uint32_t *cmd_buf_addr) +{ + long ret = 0; + + ret += CDMCmdHeaderSizes[CAM_CDM_CMD_PERF_CTRL]; + + CAM_INFO(CAM_CDM, "PERF_CTRL"); + + return ret; +} + +void cam_cdm_util_dump_cmd_buf( + uint32_t *cmd_buf_start, uint32_t *cmd_buf_end) +{ + uint32_t *buf_now = cmd_buf_start; + uint32_t *buf_end = cmd_buf_end; + uint32_t cmd = 0; + + if (!cmd_buf_start || !cmd_buf_end) { + CAM_ERR(CAM_CDM, "Invalid args"); + return; + } + + do { + cmd = *buf_now; + cmd = cmd >> CAM_CDM_COMMAND_OFFSET; + + switch (cmd) { + case CAM_CDM_CMD_DMI: + case CAM_CDM_CMD_DMI_32: + case CAM_CDM_CMD_DMI_64: + buf_now += cam_cdm_util_dump_dmi_cmd(buf_now, + buf_end); + break; + case CAM_CDM_CMD_REG_CONT: + buf_now += cam_cdm_util_dump_reg_cont_cmd(buf_now, + buf_end); + break; + case CAM_CDM_CMD_REG_RANDOM: + buf_now += cam_cdm_util_dump_reg_random_cmd(buf_now, + buf_end); + break; + case CAM_CDM_CMD_BUFF_INDIRECT: + buf_now += cam_cdm_util_dump_buff_indirect(buf_now, + buf_end); + break; + case CAM_CDM_CMD_GEN_IRQ: + buf_now += cam_cdm_util_dump_gen_irq_cmd(buf_now); + break; + case CAM_CDM_CMD_WAIT_EVENT: + buf_now += cam_cdm_util_dump_wait_event_cmd(buf_now); + break; + case CAM_CDM_CMD_CHANGE_BASE: + buf_now += cam_cdm_util_dump_change_base_cmd(buf_now, + buf_end); + break; + case CAM_CDM_CMD_PERF_CTRL: + buf_now += cam_cdm_util_dump_perf_ctrl_cmd(buf_now); + break; + default: + CAM_ERR(CAM_CDM, "Invalid CMD: 0x%x buf 0x%x", + cmd, *buf_now); + buf_now++; + break; + } + } while (buf_now <= cmd_buf_end); +} + +static uint32_t cam_cdm_util_dump_reg_cont_cmd_v2( + uint32_t *cmd_buf_addr, + struct cam_cdm_cmd_buf_dump_info *dump_info) +{ + int i; + long ret; + uint8_t *dst; + size_t remain_len; + uint32_t *temp_ptr = cmd_buf_addr; + uint32_t *addr, *start; + uint32_t min_len; + struct cdm_regcontinuous_cmd *p_regcont_cmd; + struct cam_cdm_cmd_dump_header *hdr; + + p_regcont_cmd = (struct cdm_regcontinuous_cmd *)temp_ptr; + temp_ptr += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT); + ret = cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT); + + min_len = (sizeof(uint32_t) * p_regcont_cmd->count) + + sizeof(struct cam_cdm_cmd_dump_header) + + (2 * sizeof(uint32_t)); + remain_len = dump_info->dst_max_size - dump_info->dst_offset; + + if (remain_len < min_len) { + CAM_WARN_RATE_LIMIT(CAM_CDM, + "Dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return ret; + } + + dst = (char *)dump_info->dst_start + dump_info->dst_offset; + hdr = (struct cam_cdm_cmd_dump_header *)dst; + scnprintf(hdr->tag, CAM_CDM_CMD_TAG_MAX_LEN, "CDM_REG_CONT:"); + hdr->word_size = sizeof(uint32_t); + addr = (uint32_t *)(dst + sizeof(struct cam_cdm_cmd_dump_header)); + start = addr; + *addr++ = p_regcont_cmd->offset; + *addr++ = p_regcont_cmd->count; + for (i = 0; i < p_regcont_cmd->count; i++) { + *addr = *temp_ptr; + temp_ptr++; + addr++; + ret++; + } + hdr->size = hdr->word_size * (addr - start); + dump_info->dst_offset += hdr->size + + sizeof(struct cam_cdm_cmd_dump_header); + + return ret; +} + +static uint32_t cam_cdm_util_dump_reg_random_cmd_v2( + uint32_t *cmd_buf_addr, + struct cam_cdm_cmd_buf_dump_info *dump_info) +{ + int i; + long ret; + uint8_t *dst; + uint32_t *temp_ptr = cmd_buf_addr; + uint32_t *addr, *start; + size_t remain_len; + uint32_t min_len; + struct cdm_regrandom_cmd *p_regrand_cmd; + struct cam_cdm_cmd_dump_header *hdr; + + p_regrand_cmd = (struct cdm_regrandom_cmd *)temp_ptr; + temp_ptr += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM); + ret = cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM); + + min_len = (2 * sizeof(uint32_t) * p_regrand_cmd->count) + + sizeof(struct cam_cdm_cmd_dump_header) + sizeof(uint32_t); + remain_len = dump_info->dst_max_size - dump_info->dst_offset; + + if (remain_len < min_len) { + CAM_WARN_RATE_LIMIT(CAM_CDM, + "Dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return ret; + } + + dst = (char *)dump_info->dst_start + dump_info->dst_offset; + hdr = (struct cam_cdm_cmd_dump_header *)dst; + scnprintf(hdr->tag, CAM_CDM_CMD_TAG_MAX_LEN, "CDM_REG_RANDOM:"); + hdr->word_size = sizeof(uint32_t); + addr = (uint32_t *)(dst + sizeof(struct cam_cdm_cmd_dump_header)); + start = addr; + *addr++ = p_regrand_cmd->count; + for (i = 0; i < p_regrand_cmd->count; i++) { + addr[0] = temp_ptr[0] & CAM_CDM_REG_OFFSET_MASK; + addr[1] = temp_ptr[1]; + temp_ptr += 2; + addr += 2; + ret += 2; + } + hdr->size = hdr->word_size * (addr - start); + dump_info->dst_offset += hdr->size + + sizeof(struct cam_cdm_cmd_dump_header); + return ret; +} + +int cam_cdm_util_dump_cmd_bufs_v2( + struct cam_cdm_cmd_buf_dump_info *dump_info) +{ + uint32_t cmd; + uint32_t *buf_now; + int rc = 0; + + if (!dump_info || !dump_info->src_start || !dump_info->src_end || + !dump_info->dst_start) { + CAM_INFO(CAM_CDM, "Invalid args"); + return -EINVAL; + } + + buf_now = dump_info->src_start; + do { + if (dump_info->dst_offset >= dump_info->dst_max_size) { + CAM_WARN(CAM_CDM, + "Dump overshoot offset %zu size %zu", + dump_info->dst_offset, + dump_info->dst_max_size); + return -ENOSPC; + } + cmd = *buf_now; + cmd = cmd >> CAM_CDM_COMMAND_OFFSET; + + switch (cmd) { + case CAM_CDM_CMD_DMI: + case CAM_CDM_CMD_DMI_32: + case CAM_CDM_CMD_DMI_64: + buf_now += cdm_get_cmd_header_size(CAM_CDM_CMD_DMI); + break; + case CAM_CDM_CMD_REG_CONT: + buf_now += cam_cdm_util_dump_reg_cont_cmd_v2(buf_now, + dump_info); + break; + case CAM_CDM_CMD_REG_RANDOM: + buf_now += cam_cdm_util_dump_reg_random_cmd_v2(buf_now, + dump_info); + break; + case CAM_CDM_CMD_BUFF_INDIRECT: + buf_now += cdm_get_cmd_header_size( + CAM_CDM_CMD_BUFF_INDIRECT); + break; + case CAM_CDM_CMD_GEN_IRQ: + buf_now += cdm_get_cmd_header_size( + CAM_CDM_CMD_GEN_IRQ); + break; + case CAM_CDM_CMD_WAIT_EVENT: + buf_now += cdm_get_cmd_header_size( + CAM_CDM_CMD_WAIT_EVENT); + break; + case CAM_CDM_CMD_CHANGE_BASE: + buf_now += cdm_get_cmd_header_size( + CAM_CDM_CMD_CHANGE_BASE); + break; + case CAM_CDM_CMD_PERF_CTRL: + buf_now += cdm_get_cmd_header_size( + CAM_CDM_CMD_PERF_CTRL); + break; + default: + CAM_ERR(CAM_CDM, "Invalid CMD: 0x%x", cmd); + buf_now++; + break; + } + } while (buf_now <= dump_info->src_end); + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_util.h b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_util.h new file mode 100644 index 0000000000000000000000000000000000000000..750a98a6de0537ad2c2a2b8ec6f0b692a8cebef3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_util.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CDM_UTIL_H_ +#define _CAM_CDM_UTIL_H_ + +/* Max len for tag name for header while dumping cmd buffer*/ +#define CAM_CDM_CMD_TAG_MAX_LEN 32 + +enum cam_cdm_command { + CAM_CDM_CMD_UNUSED = 0x0, + CAM_CDM_CMD_DMI = 0x1, + CAM_CDM_CMD_NOT_DEFINED = 0x2, + CAM_CDM_CMD_REG_CONT = 0x3, + CAM_CDM_CMD_REG_RANDOM = 0x4, + CAM_CDM_CMD_BUFF_INDIRECT = 0x5, + CAM_CDM_CMD_GEN_IRQ = 0x6, + CAM_CDM_CMD_WAIT_EVENT = 0x7, + CAM_CDM_CMD_CHANGE_BASE = 0x8, + CAM_CDM_CMD_PERF_CTRL = 0x9, + CAM_CDM_CMD_DMI_32 = 0xa, + CAM_CDM_CMD_DMI_64 = 0xb, + CAM_CDM_COMP_WAIT = 0xc, + CAM_CDM_CLEAR_COMP_WAIT = 0xd, + CAM_CDM_WAIT_PREFETCH_DISABLE = 0xe, + CAM_CDM_CMD_PRIVATE_BASE = 0xf, + CAM_CDM_CMD_SWD_DMI_32 = (CAM_CDM_CMD_PRIVATE_BASE + 0x64), + CAM_CDM_CMD_SWD_DMI_64 = (CAM_CDM_CMD_PRIVATE_BASE + 0x65), + CAM_CDM_CMD_PRIVATE_BASE_MAX = 0x7F, +}; + +/** + * struct cam_cdm_utils_ops - Camera CDM util ops + * + * @cdm_get_cmd_header_size: Returns the size of the given command header + * in DWORDs. + * @command Command ID + * @return Size of the command in DWORDs + * + * @cdm_required_size_reg_continuous: Calculates the size of a reg-continuous + * command in dwords. + * @numVals Number of continuous values + * @return Size in dwords + * + * @cdm_required_size_reg_random: Calculates the size of a reg-random command + * in dwords. + * @numRegVals Number of register/value pairs + * @return Size in dwords + * + * @cdm_required_size_dmi: Calculates the size of a DMI command in dwords. + * @return Size in dwords + * + * @cdm_required_size_genirq: Calculates size of a Genirq command in dwords. + * @return Size in dwords + * + * @cdm_required_size_indirect: Calculates the size of an indirect command + * in dwords. + * @return Size in dwords + * + * @cdm_required_size_comp_wait: Calculates the size of a comp-wait command + * in dwords. + * @return Size in dwords + * + * @cdm_required_size_clear_comp_event: Calculates the size of clear-comp-event + * command in dwords. + * @return Size in dwords + * + * @cdm_required_size_changebase: Calculates the size of a change-base command + * in dwords. + * @return Size in dwords + * + * @cdm_offsetof_dmi_addr: Returns the offset of address field in the DMI + * command header. + * @return Offset of addr field + * + * @cdm_offsetof_indirect_addr: Returns the offset of address field in the + * indirect command header. + * @return Offset of addr field + * + * @cdm_write_regcontinuous: Writes a command into the command buffer. + * @pCmdBuffer: Pointer to command buffer + * @reg: Beginning of the register address range where + * values will be written. + * @numVals: Number of values (registers) that will be written + * @pVals : An array of values that will be written + * @return Pointer in command buffer pointing past the written commands + * + * @cdm_write_regrandom: Writes a command into the command buffer in + * register/value pairs. + * @pCmdBuffer: Pointer to command buffer + * @numRegVals: Number of register/value pairs that will be written + * @pRegVals: An array of register/value pairs that will be written + * The even indices are registers and the odd indices + * arevalues, e.g., {reg1, val1, reg2, val2, ...}. + * @return Pointer in command buffer pointing past the written commands + * + * @cdm_write_dmi: Writes a DMI command into the command bufferM. + * @pCmdBuffer: Pointer to command buffer + * @dmiCmd: DMI command + * @DMIAddr: Address of the DMI + * @DMISel: Selected bank that the DMI will write to + * @length: Size of data in bytes + * @return Pointer in command buffer pointing past the written commands + * + * @cdm_write_indirect: Writes a indirect command into the command buffer. + * @pCmdBuffer: Pointer to command buffer + * @indirectBufferAddr: Device address of the indirect cmd buffer. + * @length: Size of data in bytes + * @return Pointer in command buffer pointing past the written commands + * + * @cdm_write_changebase: Writes a changing CDM (address) base command into + * the command buffer. + * @pCmdBuffer: Pointer to command buffer + * @base: New base (device) address + * @return Pointer in command buffer pointing past the written commands + * + * @cdm_write_genirq: Writes a gen irq command into the command buffer. + * @pCmdBuffer: Pointer to command buffer + * @userdata: userdata or cookie return by hardware during irq. + * + * @cdm_write_wait_comp_event: Writes a wait comp event cmd into the + * command buffer. + * @pCmdBuffer: Pointer to command buffer + * @mask1: This value decides which comp events to wait (0 - 31). + * @mask2: This value decides which comp events to wait (32 - 65). + * + * @cdm_write_clear_comp_event: Writes a clear comp event cmd into the + * command buffer. + * @pCmdBuffer: Pointer to command buffer + * @mask1: This value decides which comp events to clear (0 - 31). + * @mask2: This value decides which comp events to clear (32 - 65). + */ +struct cam_cdm_utils_ops { +uint32_t (*cdm_get_cmd_header_size)(unsigned int command); +uint32_t (*cdm_required_size_dmi)(void); +uint32_t (*cdm_required_size_reg_continuous)(uint32_t numVals); +uint32_t (*cdm_required_size_reg_random)(uint32_t numRegVals); +uint32_t (*cdm_required_size_indirect)(void); +uint32_t (*cdm_required_size_genirq)(void); +uint32_t (*cdm_required_size_wait_event)(void); +uint32_t (*cdm_required_size_changebase)(void); +uint32_t (*cdm_required_size_comp_wait)(void); +uint32_t (*cdm_required_size_clear_comp_event)(void); +uint32_t (*cdm_required_size_prefetch_disable)(void); +uint32_t (*cdm_offsetof_dmi_addr)(void); +uint32_t (*cdm_offsetof_indirect_addr)(void); +uint32_t *(*cdm_write_dmi)( + uint32_t *pCmdBuffer, + uint8_t dmiCmd, + uint32_t DMIAddr, + uint8_t DMISel, + uint32_t dmiBufferAddr, + uint32_t length); +uint32_t* (*cdm_write_regcontinuous)( + uint32_t *pCmdBuffer, + uint32_t reg, + uint32_t numVals, + uint32_t *pVals); +uint32_t *(*cdm_write_regrandom)( + uint32_t *pCmdBuffer, + uint32_t numRegVals, + uint32_t *pRegVals); +uint32_t *(*cdm_write_indirect)( + uint32_t *pCmdBuffer, + uint32_t indirectBufferAddr, + uint32_t length); +void (*cdm_write_genirq)( + uint32_t *pCmdBuffer, + uint32_t userdata, + bool bit_wr_enable, + uint32_t fifo_idx); +uint32_t *(*cdm_write_wait_event)( + uint32_t *pCmdBuffer, + uint32_t iw, + uint32_t id, + uint32_t mask, + uint32_t offset, + uint32_t data); +uint32_t *(*cdm_write_changebase)( + uint32_t *pCmdBuffer, + uint32_t base); +uint32_t *(*cdm_write_wait_comp_event)( + uint32_t *pCmdBuffer, + uint32_t mask1, + uint32_t mask2); +uint32_t *(*cdm_write_clear_comp_event)( + uint32_t *pCmdBuffer, + uint32_t mask1, + uint32_t mask2); +uint32_t *(*cdm_write_wait_prefetch_disable)( + uint32_t *pCmdBuffer, + uint32_t id, + uint32_t mask1, + uint32_t mask2); +}; + +/** + * struct cam_cdm_cmd_buf_dump_info; - Camera CDM dump info + * @dst_offset: dst offset + * @dst_max_size max size of destination buffer + * @src_start: source start address + * @src_end: source end address + * @dst_start: dst start address + */ +struct cam_cdm_cmd_buf_dump_info { + size_t dst_offset; + size_t dst_max_size; + uint32_t *src_start; + uint32_t *src_end; + uintptr_t dst_start; +}; + +/** + * struct cam_cdm_cmd_dump_header- Camera CDM dump header + * @tag: tag name for header + * @size: size of data + * @word_size: size of each word + */ +struct cam_cdm_cmd_dump_header { + uint8_t tag[CAM_CDM_CMD_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + +/** + * cam_cdm_util_log_cmd_bufs() + * + * @brief: Util function to log cdm command buffers + * + * @cmd_buffer_start: Pointer to start of cmd buffer + * @cmd_buffer_end: Pointer to end of cmd buffer + * + */ +void cam_cdm_util_dump_cmd_buf( + uint32_t *cmd_buffer_start, uint32_t *cmd_buffer_end); + +/** + * cam_cdm_util_dump_cmd_bufs_v2() + * + * @brief: Util function to cdm command buffers + * to a buffer + * + * @dump_info: Information about source and destination buffers + * + * return SUCCESS/FAILURE + */ +int cam_cdm_util_dump_cmd_bufs_v2( + struct cam_cdm_cmd_buf_dump_info *dump_info); + + +#endif /* _CAM_CDM_UTIL_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_virtual.h b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_virtual.h new file mode 100644 index 0000000000000000000000000000000000000000..193e01be4796c9c0c52bac0c367b81e07a182a7b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_virtual.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CDM_VIRTUAL_H_ +#define _CAM_CDM_VIRTUAL_H_ + +#include "cam_cdm_intf_api.h" + +int cam_virtual_cdm_probe(struct platform_device *pdev); +int cam_virtual_cdm_remove(struct platform_device *pdev); +int cam_cdm_util_cmd_buf_write(void __iomem **current_device_base, + uint32_t *cmd_buf, uint32_t cmd_buf_size, + struct cam_soc_reg_map *base_table[CAM_SOC_MAX_BLOCK], + uint32_t base_array_size, uint8_t bl_tag); + +#endif /* _CAM_CDM_VIRTUAL_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_virtual_core.c b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_virtual_core.c new file mode 100644 index 0000000000000000000000000000000000000000..dde67a410c7175149de89047276d1c75caad287b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cdm/cam_cdm_virtual_core.c @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "cam_soc_util.h" +#include "cam_smmu_api.h" +#include "cam_cdm_intf_api.h" +#include "cam_cdm.h" +#include "cam_cdm_util.h" +#include "cam_cdm_virtual.h" +#include "cam_cdm_core_common.h" +#include "cam_cdm_soc.h" +#include "cam_io_util.h" +#include "cam_req_mgr_workq.h" + +#define CAM_CDM_VIRTUAL_NAME "qcom,cam_virtual_cdm" + +static void cam_virtual_cdm_work(struct work_struct *work) +{ + struct cam_cdm_work_payload *payload; + struct cam_hw_info *cdm_hw; + struct cam_cdm *core; + + payload = container_of(work, struct cam_cdm_work_payload, work); + if (payload) { + cdm_hw = payload->hw; + core = (struct cam_cdm *)cdm_hw->core_info; + + cam_req_mgr_thread_switch_delay_detect( + payload->workq_scheduled_ts); + + if (payload->irq_status & 0x2) { + struct cam_cdm_bl_cb_request_entry *node; + + CAM_DBG(CAM_CDM, "CDM HW Gen/inline IRQ with data=%x", + payload->irq_data); + mutex_lock(&cdm_hw->hw_mutex); + node = cam_cdm_find_request_by_bl_tag( + payload->irq_data, + &core->bl_request_list); + if (node) { + if (node->request_type == + CAM_HW_CDM_BL_CB_CLIENT) { + cam_cdm_notify_clients(cdm_hw, + CAM_CDM_CB_STATUS_BL_SUCCESS, + (void *)node); + } else if (node->request_type == + CAM_HW_CDM_BL_CB_INTERNAL) { + CAM_ERR(CAM_CDM, "Invalid node=%pK %d", + node, node->request_type); + } + list_del_init(&node->entry); + kfree(node); + } else { + CAM_ERR(CAM_CDM, "Invalid node for inline irq"); + } + mutex_unlock(&cdm_hw->hw_mutex); + } + if (payload->irq_status & 0x1) { + CAM_DBG(CAM_CDM, "CDM HW reset done IRQ"); + complete(&core->reset_complete); + } + kfree(payload); + } + +} + +int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, + struct cam_cdm_hw_intf_cmd_submit_bl *req, + struct cam_cdm_client *client) +{ + int i, rc = -EINVAL; + struct cam_cdm_bl_request *cdm_cmd = req->data; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + + mutex_lock(&client->lock); + for (i = 0; i < req->data->cmd_arrary_count ; i++) { + uintptr_t vaddr_ptr = 0; + size_t len = 0; + + if ((!cdm_cmd->cmd[i].len) && + (cdm_cmd->cmd[i].len > 0x100000)) { + CAM_ERR(CAM_CDM, + "len(%d) is invalid count=%d total cnt=%d", + cdm_cmd->cmd[i].len, i, + req->data->cmd_arrary_count); + rc = -EINVAL; + break; + } + if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) { + rc = cam_mem_get_cpu_buf( + cdm_cmd->cmd[i].bl_addr.mem_handle, &vaddr_ptr, + &len); + } else if (req->data->type == + CAM_CDM_BL_CMD_TYPE_KERNEL_IOVA) { + rc = 0; + vaddr_ptr = cdm_cmd->cmd[i].bl_addr.kernel_iova; + len = cdm_cmd->cmd[i].offset + cdm_cmd->cmd[i].len; + } else { + CAM_ERR(CAM_CDM, + "Only mem hdl/Kernel va type is supported %d", + req->data->type); + rc = -EINVAL; + break; + } + + if ((!rc) && (vaddr_ptr) && (len) && + (len >= cdm_cmd->cmd[i].offset)) { + + + if ((len - cdm_cmd->cmd[i].offset) < + cdm_cmd->cmd[i].len) { + CAM_ERR(CAM_CDM, "Not enough buffer"); + rc = -EINVAL; + goto end; + } + CAM_DBG(CAM_CDM, + "hdl=%x vaddr=%pK offset=%d cmdlen=%d:%zu", + cdm_cmd->cmd[i].bl_addr.mem_handle, + (void *)vaddr_ptr, cdm_cmd->cmd[i].offset, + cdm_cmd->cmd[i].len, len); + rc = cam_cdm_util_cmd_buf_write( + &client->changebase_addr, + ((uint32_t *)vaddr_ptr + + ((cdm_cmd->cmd[i].offset)/4)), + cdm_cmd->cmd[i].len, client->data.base_array, + client->data.base_array_cnt, core->bl_tag); + if (rc) { + CAM_ERR(CAM_CDM, + "write failed for cnt=%d:%d len %u", + i, req->data->cmd_arrary_count, + cdm_cmd->cmd[i].len); + goto end; + } + } else { + CAM_ERR(CAM_CDM, + "Sanity check failed for hdl=%x len=%zu:%d", + cdm_cmd->cmd[i].bl_addr.mem_handle, len, + cdm_cmd->cmd[i].offset); + CAM_ERR(CAM_CDM, + "Sanity check failed for cmd_count=%d cnt=%d", + i, req->data->cmd_arrary_count); + rc = -EINVAL; + goto end; + } + if (!rc) { + struct cam_cdm_work_payload *payload; + + CAM_DBG(CAM_CDM, + "write BL success for cnt=%d with tag=%d", + i, core->bl_tag); + if ((true == req->data->flag) && + (i == req->data->cmd_arrary_count)) { + struct cam_cdm_bl_cb_request_entry *node; + + node = kzalloc(sizeof( + struct cam_cdm_bl_cb_request_entry), + GFP_KERNEL); + if (!node) { + rc = -ENOMEM; + goto end; + } + node->request_type = CAM_HW_CDM_BL_CB_CLIENT; + node->client_hdl = req->handle; + node->cookie = req->data->cookie; + node->bl_tag = core->bl_tag; + node->userdata = req->data->userdata; + mutex_lock(&cdm_hw->hw_mutex); + list_add_tail(&node->entry, + &core->bl_request_list); + mutex_unlock(&cdm_hw->hw_mutex); + + payload = kzalloc(sizeof( + struct cam_cdm_work_payload), + GFP_ATOMIC); + if (payload) { + payload->irq_status = 0x2; + payload->irq_data = core->bl_tag; + payload->hw = cdm_hw; + INIT_WORK((struct work_struct *) + &payload->work, + cam_virtual_cdm_work); + payload->workq_scheduled_ts = + ktime_get(); + queue_work(core->work_queue, + &payload->work); + } + } + core->bl_tag++; + CAM_DBG(CAM_CDM, + "Now commit the BL nothing for virtual"); + if (!rc && (core->bl_tag == 63)) + core->bl_tag = 0; + } + + if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); + } + mutex_unlock(&client->lock); + return rc; + +end: + if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); + + mutex_unlock(&client->lock); + return rc; + +} + +int cam_virtual_cdm_probe(struct platform_device *pdev) +{ + struct cam_hw_info *cdm_hw = NULL; + struct cam_hw_intf *cdm_hw_intf = NULL; + struct cam_cdm *cdm_core = NULL; + struct cam_cdm_private_dt_data *soc_private = NULL; + int rc; + struct cam_cpas_register_params cpas_parms; + + cdm_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!cdm_hw_intf) + return -ENOMEM; + + cdm_hw = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!cdm_hw) { + kfree(cdm_hw_intf); + return -ENOMEM; + } + + cdm_hw->core_info = kzalloc(sizeof(struct cam_cdm), GFP_KERNEL); + if (!cdm_hw->core_info) { + kfree(cdm_hw); + kfree(cdm_hw_intf); + return -ENOMEM; + } + cdm_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + cdm_hw->soc_info.pdev = pdev; + cdm_hw_intf->hw_type = CAM_VIRTUAL_CDM; + cdm_hw->soc_info.soc_private = kzalloc( + sizeof(struct cam_cdm_private_dt_data), GFP_KERNEL); + if (!cdm_hw->soc_info.soc_private) { + rc = -ENOMEM; + goto soc_load_failed; + } + + rc = cam_cdm_soc_load_dt_private(pdev, cdm_hw->soc_info.soc_private); + if (rc) { + CAM_ERR(CAM_CDM, "Failed to load CDM dt private data"); + kfree(cdm_hw->soc_info.soc_private); + cdm_hw->soc_info.soc_private = NULL; + goto soc_load_failed; + } + + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + soc_private = (struct cam_cdm_private_dt_data *) + cdm_hw->soc_info.soc_private; + if (soc_private->dt_cdm_shared == true) + cdm_core->flags = CAM_CDM_FLAG_SHARED_CDM; + else + cdm_core->flags = CAM_CDM_FLAG_PRIVATE_CDM; + + cdm_core->bl_tag = 0; + INIT_LIST_HEAD(&cdm_core->bl_request_list); + init_completion(&cdm_core->reset_complete); + cdm_hw_intf->hw_priv = cdm_hw; + cdm_hw_intf->hw_ops.get_hw_caps = cam_cdm_get_caps; + cdm_hw_intf->hw_ops.init = NULL; + cdm_hw_intf->hw_ops.deinit = NULL; + cdm_hw_intf->hw_ops.start = cam_cdm_stream_start; + cdm_hw_intf->hw_ops.stop = cam_cdm_stream_stop; + cdm_hw_intf->hw_ops.read = NULL; + cdm_hw_intf->hw_ops.write = NULL; + cdm_hw_intf->hw_ops.process_cmd = cam_cdm_process_cmd; + + CAM_DBG(CAM_CDM, "type %d index %d", cdm_hw_intf->hw_type, + cdm_hw_intf->hw_idx); + + platform_set_drvdata(pdev, cdm_hw_intf); + + cdm_hw->open_count = 0; + cdm_core->iommu_hdl.non_secure = -1; + cdm_core->iommu_hdl.secure = -1; + mutex_init(&cdm_hw->hw_mutex); + spin_lock_init(&cdm_hw->hw_lock); + init_completion(&cdm_hw->hw_complete); + mutex_lock(&cdm_hw->hw_mutex); + cdm_core->id = CAM_CDM_VIRTUAL; + memcpy(cdm_core->name, CAM_CDM_VIRTUAL_NAME, + sizeof(CAM_CDM_VIRTUAL_NAME)); + cdm_core->work_queue = alloc_workqueue(cdm_core->name, + WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, + CAM_CDM_INFLIGHT_WORKS); + cdm_core->ops = NULL; + + cpas_parms.cam_cpas_client_cb = cam_cdm_cpas_cb; + cpas_parms.cell_index = cdm_hw->soc_info.index; + cpas_parms.dev = &pdev->dev; + cpas_parms.userdata = cdm_hw_intf; + strlcpy(cpas_parms.identifier, "cam-cdm-intf", + CAM_HW_IDENTIFIER_LENGTH); + rc = cam_cpas_register_client(&cpas_parms); + if (rc) { + CAM_ERR(CAM_CDM, "Virtual CDM CPAS registration failed"); + goto cpas_registration_failed; + } + CAM_DBG(CAM_CDM, "CPAS registration successful handle=%d", + cpas_parms.client_handle); + cdm_core->cpas_handle = cpas_parms.client_handle; + + CAM_DBG(CAM_CDM, "CDM%d probe successful", cdm_hw_intf->hw_idx); + + rc = cam_cdm_intf_register_hw_cdm(cdm_hw_intf, + soc_private, CAM_VIRTUAL_CDM, &cdm_core->index); + if (rc) { + CAM_ERR(CAM_CDM, "Virtual CDM Interface registration failed"); + goto intf_registration_failed; + } + CAM_DBG(CAM_CDM, "CDM%d registered to intf successful", + cdm_hw_intf->hw_idx); + mutex_unlock(&cdm_hw->hw_mutex); + + return 0; +intf_registration_failed: + cam_cpas_unregister_client(cdm_core->cpas_handle); +cpas_registration_failed: + kfree(cdm_hw->soc_info.soc_private); + flush_workqueue(cdm_core->work_queue); + destroy_workqueue(cdm_core->work_queue); + mutex_unlock(&cdm_hw->hw_mutex); + mutex_destroy(&cdm_hw->hw_mutex); +soc_load_failed: + kfree(cdm_hw->core_info); + kfree(cdm_hw); + kfree(cdm_hw_intf); + return rc; +} + +int cam_virtual_cdm_remove(struct platform_device *pdev) +{ + struct cam_hw_info *cdm_hw = NULL; + struct cam_hw_intf *cdm_hw_intf = NULL; + struct cam_cdm *cdm_core = NULL; + int rc = -EBUSY; + + cdm_hw_intf = platform_get_drvdata(pdev); + if (!cdm_hw_intf) { + CAM_ERR(CAM_CDM, "Failed to get dev private data"); + return rc; + } + + cdm_hw = cdm_hw_intf->hw_priv; + if (!cdm_hw) { + CAM_ERR(CAM_CDM, + "Failed to get virtual private data for type=%d idx=%d", + cdm_hw_intf->hw_type, cdm_hw_intf->hw_idx); + return rc; + } + + cdm_core = cdm_hw->core_info; + if (!cdm_core) { + CAM_ERR(CAM_CDM, + "Failed to get virtual core data for type=%d idx=%d", + cdm_hw_intf->hw_type, cdm_hw_intf->hw_idx); + return rc; + } + + rc = cam_cpas_unregister_client(cdm_core->cpas_handle); + if (rc) { + CAM_ERR(CAM_CDM, "CPAS unregister failed"); + return rc; + } + + rc = cam_cdm_intf_deregister_hw_cdm(cdm_hw_intf, + cdm_hw->soc_info.soc_private, CAM_VIRTUAL_CDM, + cdm_core->index); + if (rc) { + CAM_ERR(CAM_CDM, + "Virtual CDM Interface de-registration failed"); + return rc; + } + + flush_workqueue(cdm_core->work_queue); + destroy_workqueue(cdm_core->work_queue); + mutex_destroy(&cdm_hw->hw_mutex); + kfree(cdm_hw->soc_info.soc_private); + kfree(cdm_hw->core_info); + kfree(cdm_hw); + kfree(cdm_hw_intf); + rc = 0; + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_core/Makefile b/techpack/camera-bengal/drivers/cam_core/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..b4c39494c4e7d1ae82eae3970b49b4c21f2058db --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_core/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(src) + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_context.o cam_context_utils.o cam_node.o cam_subdev.o diff --git a/techpack/camera-bengal/drivers/cam_core/cam_context.c b/techpack/camera-bengal/drivers/cam_core/cam_context.c new file mode 100644 index 0000000000000000000000000000000000000000..267b23dafa724a23410b0df337f2027afe61c5c2 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_core/cam_context.c @@ -0,0 +1,687 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include + +#include "cam_context.h" +#include "cam_debug_util.h" +#include "cam_node.h" + +static int cam_context_handle_hw_event(void *context, uint32_t evt_id, + void *evt_data) +{ + int rc = 0; + struct cam_context *ctx = (struct cam_context *)context; + + if (!ctx || !ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if (ctx->state_machine[ctx->state].irq_ops) + rc = ctx->state_machine[ctx->state].irq_ops(ctx, evt_id, + evt_data); + else + CAM_DBG(CAM_CORE, + "No function to handle event %d in dev %d, state %d", + evt_id, ctx->dev_hdl, ctx->state); + return rc; +} + +int cam_context_shutdown(struct cam_context *ctx) +{ + int rc = 0; + struct cam_release_dev_cmd cmd; + + if (ctx->state > CAM_CTX_AVAILABLE && ctx->state < CAM_CTX_STATE_MAX) { + cmd.session_handle = ctx->session_hdl; + cmd.dev_handle = ctx->dev_hdl; + rc = cam_context_handle_release_dev(ctx, &cmd); + if (rc) + CAM_ERR(CAM_CORE, + "context release failed for dev_name %s", + ctx->dev_name); + else + cam_context_putref(ctx); + } else { + CAM_WARN(CAM_CORE, + "dev %s context id %u state %d invalid to release hdl", + ctx->dev_name, ctx->ctx_id, ctx->state); + rc = -EINVAL; + } + + if (ctx->dev_hdl != -1) { + rc = cam_destroy_device_hdl(ctx->dev_hdl); + if (rc) + CAM_ERR(CAM_CORE, + "destroy device hdl failed for node %s", + ctx->dev_name); + else + ctx->dev_hdl = -1; + } + + return rc; +} + +int cam_context_handle_crm_get_dev_info(struct cam_context *ctx, + struct cam_req_mgr_device_info *info) +{ + int rc; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if (!info) { + CAM_ERR(CAM_CORE, "Invalid get device info payload"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].crm_ops.get_dev_info) { + rc = ctx->state_machine[ctx->state].crm_ops.get_dev_info( + ctx, info); + } else { + CAM_ERR(CAM_CORE, "No get device info in dev %d, state %d", + ctx->dev_hdl, ctx->state); + rc = -EPROTO; + } + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_crm_link(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *link) +{ + int rc; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if (!link) { + CAM_ERR(CAM_CORE, "Invalid link payload"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].crm_ops.link) { + rc = ctx->state_machine[ctx->state].crm_ops.link(ctx, link); + } else { + CAM_ERR(CAM_CORE, "No crm link in dev %d, state %d", + ctx->dev_hdl, ctx->state); + rc = -EPROTO; + } + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_crm_unlink(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *unlink) +{ + int rc; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if (!unlink) { + CAM_ERR(CAM_CORE, "Invalid unlink payload"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].crm_ops.unlink) { + rc = ctx->state_machine[ctx->state].crm_ops.unlink( + ctx, unlink); + } else { + CAM_ERR(CAM_CORE, "No crm unlink in dev %d, name %s, state %d", + ctx->dev_hdl, ctx->dev_name, ctx->state); + rc = -EPROTO; + } + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_crm_apply_req(struct cam_context *ctx, + struct cam_req_mgr_apply_request *apply) +{ + int rc; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if (!apply) { + CAM_ERR(CAM_CORE, "Invalid apply request payload"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].crm_ops.apply_req) { + rc = ctx->state_machine[ctx->state].crm_ops.apply_req(ctx, + apply); + } else { + CAM_ERR(CAM_CORE, "No crm apply req in dev %d, state %d", + ctx->dev_hdl, ctx->state); + rc = -EPROTO; + } + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_crm_flush_req(struct cam_context *ctx, + struct cam_req_mgr_flush_request *flush) +{ + int rc; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].crm_ops.flush_req) { + rc = ctx->state_machine[ctx->state].crm_ops.flush_req(ctx, + flush); + } else { + CAM_ERR(CAM_CORE, "No crm flush req in dev %d, state %d", + ctx->dev_hdl, ctx->state); + rc = -EPROTO; + } + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_crm_process_evt(struct cam_context *ctx, + struct cam_req_mgr_link_evt_data *process_evt) +{ + int rc = 0; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].crm_ops.process_evt) { + rc = ctx->state_machine[ctx->state].crm_ops.process_evt(ctx, + process_evt); + } else { + /* handling of this message is optional */ + CAM_DBG(CAM_CORE, "No crm process evt in dev %d, state %d", + ctx->dev_hdl, ctx->state); + } + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_crm_dump_req(struct cam_context *ctx, + struct cam_req_mgr_dump_info *dump) +{ + int rc = 0; + + if (!ctx) { + CAM_ERR(CAM_CORE, "Invalid Context"); + return -EINVAL; + } + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context %s ctx_id %d is not ready", + ctx->dev_name, ctx->ctx_id); + return -EINVAL; + } + mutex_lock(&ctx->ctx_mutex); + + if (ctx->state_machine[ctx->state].crm_ops.dump_req) + rc = ctx->state_machine[ctx->state].crm_ops.dump_req(ctx, + dump); + else + CAM_ERR(CAM_CORE, "No crm dump req for %s dev %d, state %d", + ctx->dev_name, ctx->dev_hdl, ctx->state); + + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_dump_pf_info(struct cam_context *ctx, unsigned long iova, + uint32_t buf_info) +{ + int rc = 0; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if ((ctx->state > CAM_CTX_AVAILABLE) && + (ctx->state < CAM_CTX_STATE_MAX)) { + if (ctx->state_machine[ctx->state].pagefault_ops) { + rc = ctx->state_machine[ctx->state].pagefault_ops( + ctx, iova, buf_info); + } else { + CAM_WARN(CAM_CORE, "No dump ctx in dev %d, state %d", + ctx->dev_hdl, ctx->state); + } + } + + return rc; +} + +int cam_context_handle_acquire_dev(struct cam_context *ctx, + struct cam_acquire_dev_cmd *cmd) +{ + int rc; + int i; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if (!cmd) { + CAM_ERR(CAM_CORE, "Invalid acquire device command payload"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].ioctl_ops.acquire_dev) { + rc = ctx->state_machine[ctx->state].ioctl_ops.acquire_dev( + ctx, cmd); + } else { + CAM_ERR(CAM_CORE, "No acquire device in dev %d, state %d", + cmd->dev_handle, ctx->state); + rc = -EPROTO; + } + + INIT_LIST_HEAD(&ctx->active_req_list); + INIT_LIST_HEAD(&ctx->wait_req_list); + INIT_LIST_HEAD(&ctx->pending_req_list); + INIT_LIST_HEAD(&ctx->free_req_list); + + for (i = 0; i < ctx->req_size; i++) { + INIT_LIST_HEAD(&ctx->req_list[i].list); + list_add_tail(&ctx->req_list[i].list, &ctx->free_req_list); + } + + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_acquire_hw(struct cam_context *ctx, + void *args) +{ + int rc; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if (!args) { + CAM_ERR(CAM_CORE, "Invalid acquire device hw command payload"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].ioctl_ops.acquire_hw) { + rc = ctx->state_machine[ctx->state].ioctl_ops.acquire_hw( + ctx, args); + } else { + CAM_ERR(CAM_CORE, "No acquire hw for dev %s, state %d", + ctx->dev_name, ctx->state); + rc = -EPROTO; + } + + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_release_dev(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if (!cmd) { + CAM_ERR(CAM_CORE, "Invalid release device command payload"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].ioctl_ops.release_dev) { + rc = ctx->state_machine[ctx->state].ioctl_ops.release_dev( + ctx, cmd); + } else { + CAM_ERR(CAM_CORE, "No release device in dev %d, state %d", + ctx->dev_hdl, ctx->state); + rc = -EPROTO; + } + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_release_hw(struct cam_context *ctx, + void *args) +{ + int rc; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if (!args) { + CAM_ERR(CAM_CORE, "Invalid release HW command payload"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].ioctl_ops.release_hw) { + rc = ctx->state_machine[ctx->state].ioctl_ops.release_hw( + ctx, args); + } else { + CAM_ERR(CAM_CORE, "No release hw for dev %s, state %d", + ctx->dev_name, ctx->state); + rc = -EPROTO; + } + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_flush_dev(struct cam_context *ctx, + struct cam_flush_dev_cmd *cmd) +{ + int rc = 0; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if (!cmd) { + CAM_ERR(CAM_CORE, "Invalid flush device command payload"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].ioctl_ops.flush_dev) { + rc = ctx->state_machine[ctx->state].ioctl_ops.flush_dev( + ctx, cmd); + } else { + CAM_WARN(CAM_CORE, "No flush device in dev %d, state %d", + ctx->dev_hdl, ctx->state); + } + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_config_dev(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + int rc; + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "context is not ready"); + return -EINVAL; + } + + if (!cmd) { + CAM_ERR(CAM_CORE, "Invalid config device command payload"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].ioctl_ops.config_dev) { + rc = ctx->state_machine[ctx->state].ioctl_ops.config_dev( + ctx, cmd); + } else { + CAM_ERR(CAM_CORE, "No config device in dev %d, state %d", + ctx->dev_hdl, ctx->state); + rc = -EPROTO; + } + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_start_dev(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc = 0; + + if (!ctx || !ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if (!cmd) { + CAM_ERR(CAM_CORE, "Invalid start device command payload"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].ioctl_ops.start_dev) + rc = ctx->state_machine[ctx->state].ioctl_ops.start_dev( + ctx, cmd); + else + /* start device can be optional for some driver */ + CAM_DBG(CAM_CORE, "No start device in dev %d, state %d", + ctx->dev_hdl, ctx->state); + + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_stop_dev(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc = 0; + + if (!ctx || !ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + if (!cmd) { + CAM_ERR(CAM_CORE, "Invalid stop device command payload"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].ioctl_ops.stop_dev) + rc = ctx->state_machine[ctx->state].ioctl_ops.stop_dev( + ctx, cmd); + else + /* stop device can be optional for some driver */ + CAM_WARN(CAM_CORE, "No stop device in dev %d, name %s state %d", + ctx->dev_hdl, ctx->dev_name, ctx->state); + + ctx->last_flush_req = 0; + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_handle_info_dump(void *context, + enum cam_context_dump_id id) +{ + int rc = 0; + struct cam_context *ctx = (struct cam_context *)context; + + if (!ctx || !ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context is not ready"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state_machine[ctx->state].dumpinfo_ops) + rc = ctx->state_machine[ctx->state].dumpinfo_ops(ctx, + id); + mutex_unlock(&ctx->ctx_mutex); + + if (rc) + CAM_WARN(CAM_CORE, + "Dump for id %u failed on ctx_id %u name %s state %d", + id, ctx->ctx_id, ctx->dev_name, ctx->state); + + return rc; +} + +int cam_context_handle_dump_dev(struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc = 0; + + if (!ctx) { + CAM_ERR(CAM_CORE, "Invalid Context"); + return -EINVAL; + } + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context %s ctx_id %d is not ready", + ctx->dev_name, ctx->ctx_id); + return -EINVAL; + } + + if (!cmd) { + CAM_ERR(CAM_CORE, + "Context %s ctx_id %d Invalid dump command payload", + ctx->dev_name, ctx->ctx_id); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + CAM_DBG(CAM_CORE, "dump device in dev %d, name %s state %d", + ctx->dev_hdl, ctx->dev_name, ctx->state); + if (ctx->state_machine[ctx->state].ioctl_ops.dump_dev) + rc = ctx->state_machine[ctx->state].ioctl_ops.dump_dev( + ctx, cmd); + else + CAM_WARN(CAM_CORE, "No dump device in dev %d, name %s state %d", + ctx->dev_hdl, ctx->dev_name, ctx->state); + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + +int cam_context_init(struct cam_context *ctx, + const char *dev_name, + uint64_t dev_id, + uint32_t ctx_id, + struct cam_req_mgr_kmd_ops *crm_node_intf, + struct cam_hw_mgr_intf *hw_mgr_intf, + struct cam_ctx_request *req_list, + uint32_t req_size) +{ + int i; + + /* crm_node_intf is optinal */ + if (!ctx || !hw_mgr_intf || !req_list) { + CAM_ERR(CAM_CORE, "Invalid input parameters"); + return -EINVAL; + } + + memset(ctx, 0, sizeof(*ctx)); + ctx->dev_hdl = -1; + ctx->link_hdl = -1; + ctx->session_hdl = -1; + INIT_LIST_HEAD(&ctx->list); + mutex_init(&ctx->ctx_mutex); + mutex_init(&ctx->sync_mutex); + spin_lock_init(&ctx->lock); + + strlcpy(ctx->dev_name, dev_name, CAM_CTX_DEV_NAME_MAX_LENGTH); + ctx->dev_id = dev_id; + ctx->ctx_id = ctx_id; + ctx->last_flush_req = 0; + ctx->ctx_crm_intf = NULL; + ctx->crm_ctx_intf = crm_node_intf; + ctx->hw_mgr_intf = hw_mgr_intf; + ctx->irq_cb_intf = cam_context_handle_hw_event; + + INIT_LIST_HEAD(&ctx->active_req_list); + INIT_LIST_HEAD(&ctx->wait_req_list); + INIT_LIST_HEAD(&ctx->pending_req_list); + INIT_LIST_HEAD(&ctx->free_req_list); + ctx->req_list = req_list; + ctx->req_size = req_size; + for (i = 0; i < req_size; i++) { + INIT_LIST_HEAD(&ctx->req_list[i].list); + list_add_tail(&ctx->req_list[i].list, &ctx->free_req_list); + ctx->req_list[i].ctx = ctx; + } + ctx->state = CAM_CTX_AVAILABLE; + ctx->state_machine = NULL; + ctx->ctx_priv = NULL; + + return 0; +} + +int cam_context_deinit(struct cam_context *ctx) +{ + if (!ctx) + return -EINVAL; + + /** + * This is called from platform device remove. + * Everyting should be released at this moment. + * so we just free the memory for the context + */ + if (ctx->state != CAM_CTX_AVAILABLE) + CAM_ERR(CAM_CORE, "Device did not shutdown cleanly"); + + memset(ctx, 0, sizeof(*ctx)); + + return 0; +} + +void cam_context_putref(struct cam_context *ctx) +{ + if (kref_read(&ctx->refcount)) + kref_put(&ctx->refcount, cam_node_put_ctxt_to_free_list); + else + WARN(1, "ctx %s %d state %d devhdl %X\n", ctx->dev_name, + ctx->ctx_id, ctx->state, ctx->dev_hdl); + + CAM_DBG(CAM_CORE, + "ctx device hdl %ld, ref count %d, dev_name %s", + ctx->dev_hdl, refcount_read(&(ctx->refcount.refcount)), + ctx->dev_name); +} + +void cam_context_getref(struct cam_context *ctx) +{ + if (kref_get_unless_zero(&ctx->refcount) == 0) { + /* should never happen */ + WARN(1, "%s fail\n", __func__); + } + CAM_DBG(CAM_CORE, + "ctx device hdl %ld, ref count %d, dev_name %s", + ctx->dev_hdl, refcount_read(&(ctx->refcount.refcount)), + ctx->dev_name); +} diff --git a/techpack/camera-bengal/drivers/cam_core/cam_context.h b/techpack/camera-bengal/drivers/cam_core/cam_context.h new file mode 100644 index 0000000000000000000000000000000000000000..770451faadf2e3f9dcdf71c5df44f008c8d70a6c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_core/cam_context.h @@ -0,0 +1,529 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CONTEXT_H_ +#define _CAM_CONTEXT_H_ + +#include +#include +#include +#include "cam_req_mgr_interface.h" +#include "cam_hw_mgr_intf.h" + +/* Forward declarations */ +struct cam_context; + +/* max device name string length*/ +#define CAM_CTX_DEV_NAME_MAX_LENGTH 20 + +/* max request number */ +#define CAM_CTX_REQ_MAX 20 +#define CAM_CTX_CFG_MAX 20 +#define CAM_CTX_RES_MAX 20 + +/* max tag dump header string length*/ +#define CAM_CTXT_DUMP_TAG_MAX_LEN 32 + +/* Number of words to be dumped for context*/ +#define CAM_CTXT_DUMP_NUM_WORDS 10 + +/** + * enum cam_ctx_state - context top level states + * + */ +enum cam_context_state { + CAM_CTX_UNINIT = 0, + CAM_CTX_AVAILABLE = 1, + CAM_CTX_ACQUIRED = 2, + CAM_CTX_READY = 3, + CAM_CTX_FLUSHED = 4, + CAM_CTX_ACTIVATED = 5, + CAM_CTX_STATE_MAX = 6, +}; + +/** + * struct cam_ctx_request - Common request structure for the context + * + * @list: Link list entry + * @status: Request status + * @request_id: Request id + * @req_priv: Derived request object + * @hw_update_entries: Hardware update entries + * @num_hw_update_entries: Number of hardware update entries + * @in_map_entries: Entries for in fences + * @num_in_map_entries: Number of in map entries + * @out_map_entries: Entries for out fences + * @num_out_map_entries: Number of out map entries + * @num_in_acked: Number of in fence acked + * @num_out_acked: Number of out fence acked + * @flushed: Request is flushed + * @ctx: The context to which this request belongs + * @pf_data page fault debug data + * + */ +struct cam_ctx_request { + struct list_head list; + uint32_t status; + uint64_t request_id; + void *req_priv; + struct cam_hw_update_entry hw_update_entries[CAM_CTX_CFG_MAX]; + uint32_t num_hw_update_entries; + struct cam_hw_fence_map_entry in_map_entries[CAM_CTX_CFG_MAX]; + uint32_t num_in_map_entries; + struct cam_hw_fence_map_entry out_map_entries[CAM_CTX_CFG_MAX]; + uint32_t num_out_map_entries; + atomic_t num_in_acked; + uint32_t num_out_acked; + int flushed; + struct cam_context *ctx; + struct cam_hw_mgr_dump_pf_data pf_data; +}; + +/** + * struct cam_ctx_ioctl_ops - Function table for handling IOCTL calls + * + * @acquire_dev: Function pointer for acquire device + * @release_dev: Function pointer for release device + * @config_dev: Function pointer for config device + * @start_dev: Function pointer for start device + * @stop_dev: Function pointer for stop device + * @flush_dev: Function pointer for flush device + * @acquire_hw: Function pointer for acquire hw + * @release_hw: Function pointer for release hw + * @dump_dev: Function pointer for dump dev + * + */ +struct cam_ctx_ioctl_ops { + int (*acquire_dev)(struct cam_context *ctx, + struct cam_acquire_dev_cmd *cmd); + int (*release_dev)(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd); + int (*config_dev)(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd); + int (*start_dev)(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd); + int (*stop_dev)(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd); + int (*flush_dev)(struct cam_context *ctx, + struct cam_flush_dev_cmd *cmd); + int (*acquire_hw)(struct cam_context *ctx, void *args); + int (*release_hw)(struct cam_context *ctx, void *args); + int (*dump_dev)(struct cam_context *ctx, + struct cam_dump_req_cmd *cmd); +}; + +/** + * struct cam_ctx_crm_ops - Function table for handling CRM to context calls + * + * @get_dev_info: Get device informaiton + * @link: Link the context + * @unlink: Unlink the context + * @apply_req: Apply setting for the context + * @flush_req: Flush request to remove request ids + * @process_evt: Handle event notification from CRM.(optional) + * @dump_req: Dump information for the issue request + * + */ +struct cam_ctx_crm_ops { + int (*get_dev_info)(struct cam_context *ctx, + struct cam_req_mgr_device_info *device_info); + int (*link)(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *link); + int (*unlink)(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *unlink); + int (*apply_req)(struct cam_context *ctx, + struct cam_req_mgr_apply_request *apply); + int (*flush_req)(struct cam_context *ctx, + struct cam_req_mgr_flush_request *flush); + int (*process_evt)(struct cam_context *ctx, + struct cam_req_mgr_link_evt_data *evt_data); + int (*dump_req)(struct cam_context *ctx, + struct cam_req_mgr_dump_info *dump); +}; + + +/** + * struct cam_ctx_ops - Collection of the interface funciton tables + * + * @ioctl_ops: Ioctl funciton table + * @crm_ops: CRM to context interface function table + * @irq_ops: Hardware event handle function + * @pagefault_ops: Function to be called on page fault + * @dumpinfo_ops: Function to be invoked for dumping any + * context info + * + */ +struct cam_ctx_ops { + struct cam_ctx_ioctl_ops ioctl_ops; + struct cam_ctx_crm_ops crm_ops; + cam_hw_event_cb_func irq_ops; + cam_hw_pagefault_cb_func pagefault_ops; + cam_ctx_info_dump_cb_func dumpinfo_ops; +}; + +/** + * struct cam_context - camera context object for the subdevice node + * + * @dev_name: String giving name of device associated + * @dev_id: ID of device associated + * @ctx_id: ID for this context + * @list: Link list entry + * @sessoin_hdl: Session handle + * @dev_hdl: Device handle + * @link_hdl: Link handle + * @ctx_mutex: Mutex for ioctl calls + * @lock: Spin lock + * @active_req_list: Requests pending for done event + * @pending_req_list: Requests pending for reg upd event + * @wait_req_list: Requests waiting for apply + * @free_req_list: Requests that are free + * @req_list: Reference to the request storage + * @req_size: Size of the request storage + * @hw_mgr_intf: Context to HW interface + * @ctx_crm_intf: Context to CRM interface + * @crm_ctx_intf: CRM to context interface + * @irq_cb_intf: HW to context callback interface + * @state: Current state for top level state machine + * @state_machine: Top level state machine + * @ctx_priv: Private context pointer + * @ctxt_to_hw_map: Context to hardware mapping pointer + * @refcount: Context object refcount + * @node: The main node to which this context belongs + * @sync_mutex: mutex to sync with sync cb thread + * @last_flush_req: Last request to flush + * + */ +struct cam_context { + char dev_name[CAM_CTX_DEV_NAME_MAX_LENGTH]; + uint64_t dev_id; + uint32_t ctx_id; + struct list_head list; + int32_t session_hdl; + int32_t dev_hdl; + int32_t link_hdl; + + struct mutex ctx_mutex; + spinlock_t lock; + + struct list_head active_req_list; + struct list_head pending_req_list; + struct list_head wait_req_list; + struct list_head free_req_list; + struct cam_ctx_request *req_list; + uint32_t req_size; + + struct cam_hw_mgr_intf *hw_mgr_intf; + struct cam_req_mgr_crm_cb *ctx_crm_intf; + struct cam_req_mgr_kmd_ops *crm_ctx_intf; + cam_hw_event_cb_func irq_cb_intf; + + enum cam_context_state state; + struct cam_ctx_ops *state_machine; + + void *ctx_priv; + void *ctxt_to_hw_map; + + struct kref refcount; + void *node; + struct mutex sync_mutex; + uint32_t last_flush_req; +}; + +/** + * struct cam_context_dump_header - Function for context dump header + * + * @tag : Tag for context dump header + * @size : Size of data + * @word_size : Word size of data + */ +struct cam_context_dump_header { + uint8_t tag[CAM_CTXT_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + +/** + * cam_context_shutdown() + * + * @brief: Calls while device close or shutdown + * + * @ctx: Object pointer for cam_context + * + */ +int cam_context_shutdown(struct cam_context *ctx); + +/** + * cam_context_handle_crm_get_dev_info() + * + * @brief: Handle get device information command + * + * @ctx: Object pointer for cam_context + * @info: Device information returned + * + */ +int cam_context_handle_crm_get_dev_info(struct cam_context *ctx, + struct cam_req_mgr_device_info *info); + +/** + * cam_context_handle_crm_link() + * + * @brief: Handle link command + * + * @ctx: Object pointer for cam_context + * @link: Link command payload + * + */ +int cam_context_handle_crm_link(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *link); + +/** + * cam_context_handle_crm_unlink() + * + * @brief: Handle unlink command + * + * @ctx: Object pointer for cam_context + * @unlink: Unlink command payload + * + */ +int cam_context_handle_crm_unlink(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *unlink); + +/** + * cam_context_handle_crm_apply_req() + * + * @brief: Handle apply request command + * + * @ctx: Object pointer for cam_context + * @apply: Apply request command payload + * + */ +int cam_context_handle_crm_apply_req(struct cam_context *ctx, + struct cam_req_mgr_apply_request *apply); + +/** + * cam_context_handle_crm_flush_req() + * + * @brief: Handle flush request command + * + * @ctx: Object pointer for cam_context + * @apply: Flush request command payload + * + */ +int cam_context_handle_crm_flush_req(struct cam_context *ctx, + struct cam_req_mgr_flush_request *apply); + +/** + * cam_context_handle_crm_process_evt() + * + * @brief: Handle process event command + * + * @ctx: Object pointer for cam_context + * @process_evt: process event command payload + * + */ +int cam_context_handle_crm_process_evt(struct cam_context *ctx, + struct cam_req_mgr_link_evt_data *process_evt); + +/** + * cam_context_handle_crm_dump_req() + * + * @brief: Handle CRM dump request + * + * @ctx: Object pointer for cam_context + * @dump: Dump request command payload + * + */ +int cam_context_handle_crm_dump_req(struct cam_context *ctx, + struct cam_req_mgr_dump_info *dump); + +/** + * cam_context_dump_pf_info() + * + * @brief: Handle dump active request request command + * + * @ctx: Object pointer for cam_context + * @iova: Page fault address + * @buf_info: Information about closest memory handle + * + */ +int cam_context_dump_pf_info(struct cam_context *ctx, unsigned long iova, + uint32_t buf_info); + +/** + * cam_context_handle_acquire_dev() + * + * @brief: Handle acquire device command + * + * @ctx: Object pointer for cam_context + * @cmd: Acquire device command payload + * + */ +int cam_context_handle_acquire_dev(struct cam_context *ctx, + struct cam_acquire_dev_cmd *cmd); + +/** + * cam_context_handle_acquire_hw() + * + * @brief: Handle acquire HW command + * + * @ctx: Object pointer for cam_context + * @cmd: Acquire HW command payload + * + */ +int cam_context_handle_acquire_hw(struct cam_context *ctx, + void *cmd); + +/** + * cam_context_handle_release_dev() + * + * @brief: Handle release device command + * + * @ctx: Object pointer for cam_context + * @cmd: Release device command payload + * + */ +int cam_context_handle_release_dev(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd); + +/** + * cam_context_handle_release_hw() + * + * @brief: Handle release HW command + * + * @ctx: Object pointer for cam_context + * @cmd: Release HW command payload + * + */ +int cam_context_handle_release_hw(struct cam_context *ctx, + void *cmd); + +/** + * cam_context_handle_config_dev() + * + * @brief: Handle config device command + * + * @ctx: Object pointer for cam_context + * @cmd: Config device command payload + * + */ +int cam_context_handle_config_dev(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd); + +/** + * cam_context_handle_flush_dev() + * + * @brief: Handle flush device command + * + * @ctx: Object pointer for cam_context + * @cmd: Flush device command payload + * + */ +int cam_context_handle_flush_dev(struct cam_context *ctx, + struct cam_flush_dev_cmd *cmd); + +/** + * cam_context_handle_start_dev() + * + * @brief: Handle start device command + * + * @ctx: Object pointer for cam_context + * @cmd: Start device command payload + * + */ +int cam_context_handle_start_dev(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd); + +/** + * cam_context_handle_stop_dev() + * + * @brief: Handle stop device command + * + * @ctx: Object pointer for cam_context + * @cmd: Stop device command payload + * + */ +int cam_context_handle_stop_dev(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd); + +/** + * cam_context_handle_dump_dev() + * + * @brief: Handle dump device command + * + * @ctx: Object pointer for cam_context + * @cmd: Dump device command payload + * + */ +int cam_context_handle_dump_dev(struct cam_context *ctx, + struct cam_dump_req_cmd *cmd); + +/** + * cam_context_handle_info_dump() + * + * @brief: Handle any dump info for the context + * + * @ctx: Object pointer for cam_context + * @id: To indicate which info pertaining + * to that ctx needs to be dumped + * + */ +int cam_context_handle_info_dump(void *context, + enum cam_context_dump_id id); + +/** + * cam_context_deinit() + * + * @brief: Camera context deinitialize function + * + * @ctx: Object pointer for cam_context + * + */ +int cam_context_deinit(struct cam_context *ctx); + +/** + * cam_context_init() + * + * @brief: Camera context initialize function + * + * @ctx: Object pointer for cam_context + * @dev_name: String giving name of device associated + * @dev_id: ID of the device associated + * @ctx_id: ID for this context + * @crm_node_intf: Function table for crm to context interface + * @hw_mgr_intf: Function table for context to hw interface + * @req_list: Requests storage + * @req_size: Size of the request storage + * + */ +int cam_context_init(struct cam_context *ctx, + const char *dev_name, + uint64_t dev_id, + uint32_t ctx_id, + struct cam_req_mgr_kmd_ops *crm_node_intf, + struct cam_hw_mgr_intf *hw_mgr_intf, + struct cam_ctx_request *req_list, + uint32_t req_size); + +/** + * cam_context_putref() + * + * @brief: Put back context reference. + * + * @ctx: Context for which ref is returned + * + */ +void cam_context_putref(struct cam_context *ctx); + +/** + * cam_context_getref() + * + * @brief: Get back context reference. + * + * @ctx: Context for which ref is taken + * + */ +void cam_context_getref(struct cam_context *ctx); + +#endif /* _CAM_CONTEXT_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_core/cam_context_utils.c b/techpack/camera-bengal/drivers/cam_core/cam_context_utils.c new file mode 100644 index 0000000000000000000000000000000000000000..72330fdf30d1d4384785a8267ed585d23f7fb6c0 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_core/cam_context_utils.c @@ -0,0 +1,1191 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "cam_context.h" +#include "cam_context_utils.h" +#include "cam_mem_mgr.h" +#include "cam_node.h" +#include "cam_req_mgr_util.h" +#include "cam_sync_api.h" +#include "cam_trace.h" +#include "cam_debug_util.h" + +static uint cam_debug_ctx_req_list; +module_param(cam_debug_ctx_req_list, uint, 0644); + +static inline int cam_context_validate_thread(void) +{ + if (in_interrupt()) { + WARN(1, "Invalid execution context\n"); + return -EINVAL; + } + return 0; +} + +int cam_context_buf_done_from_hw(struct cam_context *ctx, + void *done_event_data, uint32_t bubble_state) +{ + int j; + int result; + struct cam_ctx_request *req; + struct cam_hw_done_event_data *done = + (struct cam_hw_done_event_data *)done_event_data; + int rc; + + if (!ctx || !done) { + CAM_ERR(CAM_CTXT, "Invalid input params %pK %pK", ctx, done); + return -EINVAL; + } + + rc = cam_context_validate_thread(); + if (rc) + return rc; + + spin_lock(&ctx->lock); + if (list_empty(&ctx->active_req_list)) { + CAM_ERR(CAM_CTXT, "[%s][%d] no active request", + ctx->dev_name, ctx->ctx_id); + spin_unlock(&ctx->lock); + return -EIO; + } + req = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + + trace_cam_buf_done("UTILS", ctx, req); + + if (done->request_id != req->request_id) { + CAM_ERR(CAM_CTXT, + "[%s][%d] mismatch: done req[%lld], active req[%lld]", + ctx->dev_name, ctx->ctx_id, + done->request_id, req->request_id); + spin_unlock(&ctx->lock); + return -EIO; + } + + if (!req->num_out_map_entries) { + CAM_ERR(CAM_CTXT, "[%s][%d] no output fence to signal", + ctx->dev_name, ctx->ctx_id); + spin_unlock(&ctx->lock); + return -EIO; + } + + /* + * since another thread may be adding/removing from active + * list, so hold the lock + */ + list_del_init(&req->list); + spin_unlock(&ctx->lock); + if (!bubble_state) { + result = CAM_SYNC_STATE_SIGNALED_SUCCESS; + } else { + CAM_DBG(CAM_REQ, + "[%s][ctx_id %d] : req[%llu] is done with error", + ctx->dev_name, ctx->ctx_id, req->request_id); + + for (j = 0; j < req->num_out_map_entries; j++) + CAM_DBG(CAM_REQ, "fence %d signaled with error", + req->out_map_entries[j].sync_id); + + result = CAM_SYNC_STATE_SIGNALED_ERROR; + } + + for (j = 0; j < req->num_out_map_entries; j++) { + cam_sync_signal(req->out_map_entries[j].sync_id, result); + req->out_map_entries[j].sync_id = -1; + } + + if (cam_debug_ctx_req_list & ctx->dev_id) + CAM_INFO(CAM_CTXT, + "[%s][%d] : Moving req[%llu] from active_list to free_list", + ctx->dev_name, ctx->ctx_id, req->request_id); + + /* + * another thread may be adding/removing from free list, + * so hold the lock + */ + spin_lock(&ctx->lock); + list_add_tail(&req->list, &ctx->free_req_list); + req->ctx = NULL; + spin_unlock(&ctx->lock); + + return 0; +} + +static int cam_context_apply_req_to_hw(struct cam_ctx_request *req, + struct cam_req_mgr_apply_request *apply) +{ + int rc = 0; + struct cam_context *ctx = req->ctx; + struct cam_hw_config_args cfg; + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", + ctx->dev_name, ctx->ctx_id); + rc = -EFAULT; + goto end; + } + + spin_lock(&ctx->lock); + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->active_req_list); + spin_unlock(&ctx->lock); + + if (cam_debug_ctx_req_list & ctx->dev_id) + CAM_INFO(CAM_CTXT, + "[%s][%d] : Moving req[%llu] from pending_list to active_list", + ctx->dev_name, ctx->ctx_id, req->request_id); + + cfg.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + cfg.request_id = req->request_id; + cfg.hw_update_entries = req->hw_update_entries; + cfg.num_hw_update_entries = req->num_hw_update_entries; + cfg.out_map_entries = req->out_map_entries; + cfg.num_out_map_entries = req->num_out_map_entries; + cfg.priv = req->req_priv; + + rc = ctx->hw_mgr_intf->hw_config(ctx->hw_mgr_intf->hw_mgr_priv, &cfg); + if (rc) { + spin_lock(&ctx->lock); + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->free_req_list); + spin_unlock(&ctx->lock); + + if (cam_debug_ctx_req_list & ctx->dev_id) + CAM_INFO(CAM_CTXT, + "[%s][%d] : Moving req[%llu] from active_list to free_list", + ctx->dev_name, ctx->ctx_id, req->request_id); + } + +end: + return rc; +} + +static void cam_context_sync_callback(int32_t sync_obj, int status, void *data) +{ + struct cam_ctx_request *req = data; + struct cam_context *ctx = NULL; + struct cam_flush_dev_cmd flush_cmd; + struct cam_req_mgr_apply_request apply; + int rc; + + if (!req) { + CAM_ERR(CAM_CTXT, "Invalid input param"); + return; + } + rc = cam_context_validate_thread(); + if (rc) + return; + + ctx = req->ctx; + if (!ctx) { + CAM_ERR(CAM_CTXT, "Invalid ctx for req %llu", req->request_id); + return; + } + + if (atomic_inc_return(&req->num_in_acked) == req->num_in_map_entries) { + apply.request_id = req->request_id; + /* + * take mutex to ensure that another thread does + * not flush the request while this + * thread is submitting it to h/w. The submit to + * h/w and adding to the active list should happen + * in a critical section which is provided by this + * mutex. + */ + if (status == CAM_SYNC_STATE_SIGNALED_ERROR) { + CAM_DBG(CAM_CTXT, "fence error: %d", sync_obj); + flush_cmd.req_id = req->request_id; + cam_context_flush_req_to_hw(ctx, &flush_cmd); + } + + mutex_lock(&ctx->sync_mutex); + if (!req->flushed) { + cam_context_apply_req_to_hw(req, &apply); + mutex_unlock(&ctx->sync_mutex); + } else { + req->flushed = 0; + req->ctx = NULL; + mutex_unlock(&ctx->sync_mutex); + spin_lock(&ctx->lock); + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->free_req_list); + spin_unlock(&ctx->lock); + + if (cam_debug_ctx_req_list & ctx->dev_id) + CAM_INFO(CAM_CTXT, + "[%s][%d] : Moving req[%llu] from pending_list to free_list", + ctx->dev_name, ctx->ctx_id, + req->request_id); + } + } + cam_context_putref(ctx); +} + +int32_t cam_context_release_dev_to_hw(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + struct cam_hw_release_args arg; + + if (!ctx) { + CAM_ERR(CAM_CTXT, "Invalid input param"); + return -EINVAL; + } + + if ((!ctx->hw_mgr_intf) || (!ctx->hw_mgr_intf->hw_release)) { + CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", + ctx->dev_name, ctx->ctx_id); + return -EINVAL; + } + + arg.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + arg.active_req = false; + + ctx->hw_mgr_intf->hw_release(ctx->hw_mgr_intf->hw_mgr_priv, &arg); + ctx->ctxt_to_hw_map = NULL; + + ctx->session_hdl = -1; + ctx->dev_hdl = -1; + ctx->link_hdl = -1; + + return 0; +} + +int32_t cam_context_config_dev_to_hw( + struct cam_context *ctx, struct cam_config_dev_cmd *cmd) +{ + int rc = 0; + size_t len; + struct cam_hw_stream_setttings cfg; + uintptr_t packet_addr; + struct cam_packet *packet; + + if (!ctx || !cmd) { + CAM_ERR(CAM_CTXT, "Invalid input params %pK %pK", ctx, cmd); + return -EINVAL; + } + + if (!ctx->hw_mgr_intf->hw_config_stream_settings) { + CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", + ctx->dev_name, ctx->ctx_id); + rc = -EFAULT; + return rc; + } + + rc = cam_context_validate_thread(); + if (rc) { + CAM_ERR(CAM_CTXT, + "Not executing in the right context"); + return rc; + } + + rc = cam_mem_get_cpu_buf((int32_t) cmd->packet_handle, + &packet_addr, &len); + if (rc) { + CAM_ERR(CAM_CTXT, "[%s][%d] Can not get packet address", + ctx->dev_name, ctx->ctx_id); + rc = -EINVAL; + return rc; + } + + packet = (struct cam_packet *) ((uint8_t *)packet_addr + + (uint32_t)cmd->offset); + + memset(&cfg, 0, sizeof(cfg)); + cfg.packet = packet; + cfg.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + cfg.priv = NULL; + + CAM_DBG(CAM_CTXT, "Processing config settings"); + rc = ctx->hw_mgr_intf->hw_config_stream_settings( + ctx->hw_mgr_intf->hw_mgr_priv, &cfg); + if (rc) { + CAM_ERR(CAM_CTXT, + "[%s][%d] Config failed stream settings", + ctx->dev_name, ctx->ctx_id); + rc = -EFAULT; + } + + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); + return rc; +} + +int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + int rc = 0; + struct cam_ctx_request *req = NULL; + struct cam_hw_prepare_update_args cfg; + uintptr_t packet_addr; + struct cam_packet *packet; + size_t len = 0; + size_t remain_len = 0; + int32_t i = 0, j = 0; + + if (!ctx || !cmd) { + CAM_ERR(CAM_CTXT, "Invalid input params %pK %pK", ctx, cmd); + return -EINVAL; + } + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", + ctx->dev_name, ctx->ctx_id); + return -EFAULT; + } + rc = cam_context_validate_thread(); + if (rc) + return rc; + + spin_lock(&ctx->lock); + if (!list_empty(&ctx->free_req_list)) { + req = list_first_entry(&ctx->free_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + } + spin_unlock(&ctx->lock); + + if (!req) { + CAM_ERR(CAM_CTXT, "[%s][%d] No more request obj free", + ctx->dev_name, ctx->ctx_id); + return -ENOMEM; + } + + memset(req, 0, sizeof(*req)); + INIT_LIST_HEAD(&req->list); + req->ctx = ctx; + + /* for config dev, only memory handle is supported */ + /* map packet from the memhandle */ + rc = cam_mem_get_cpu_buf((int32_t) cmd->packet_handle, + &packet_addr, &len); + if (rc != 0) { + CAM_ERR(CAM_CTXT, "[%s][%d] Can not get packet address", + ctx->dev_name, ctx->ctx_id); + rc = -EINVAL; + goto free_req; + } + + if ((len < sizeof(struct cam_packet)) || + (cmd->offset >= (len - sizeof(struct cam_packet)))) { + CAM_ERR(CAM_CTXT, "Not enough buf"); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); + return -EINVAL; + + } + remain_len = len; + if ((len < sizeof(struct cam_packet)) || + ((size_t)cmd->offset >= len - sizeof(struct cam_packet))) { + CAM_ERR(CAM_CTXT, "invalid buff length: %zu or offset", len); + rc = -EINVAL; + goto free_req; + } + + remain_len -= (size_t)cmd->offset; + packet = (struct cam_packet *) ((uint8_t *)packet_addr + + (uint32_t)cmd->offset); + + if (packet->header.request_id <= ctx->last_flush_req) { + CAM_ERR(CAM_CORE, + "request %lld has been flushed, reject packet", + packet->header.request_id); + rc = -EINVAL; + goto free_req; + } + + if (packet->header.request_id > ctx->last_flush_req) + ctx->last_flush_req = 0; + + /* preprocess the configuration */ + memset(&cfg, 0, sizeof(cfg)); + cfg.packet = packet; + cfg.remain_len = remain_len; + cfg.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + cfg.max_hw_update_entries = CAM_CTX_CFG_MAX; + cfg.num_hw_update_entries = req->num_hw_update_entries; + cfg.hw_update_entries = req->hw_update_entries; + cfg.max_out_map_entries = CAM_CTX_CFG_MAX; + cfg.out_map_entries = req->out_map_entries; + cfg.max_in_map_entries = CAM_CTX_CFG_MAX; + cfg.in_map_entries = req->in_map_entries; + cfg.pf_data = &(req->pf_data); + + rc = ctx->hw_mgr_intf->hw_prepare_update( + ctx->hw_mgr_intf->hw_mgr_priv, &cfg); + if (rc != 0) { + CAM_ERR(CAM_CTXT, + "[%s][%d] Prepare config packet failed in HW layer", + ctx->dev_name, ctx->ctx_id); + rc = -EFAULT; + goto free_req; + } + req->num_hw_update_entries = cfg.num_hw_update_entries; + req->num_out_map_entries = cfg.num_out_map_entries; + req->num_in_map_entries = cfg.num_in_map_entries; + atomic_set(&req->num_in_acked, 0); + req->request_id = packet->header.request_id; + req->status = 1; + req->req_priv = cfg.priv; + + for (i = 0; i < req->num_out_map_entries; i++) { + rc = cam_sync_get_obj_ref(req->out_map_entries[i].sync_id); + if (rc) { + CAM_ERR(CAM_CTXT, "Can't get ref for sync %d", + req->out_map_entries[i].sync_id); + goto put_ref; + } + } + + if (req->num_in_map_entries > 0) { + spin_lock(&ctx->lock); + list_add_tail(&req->list, &ctx->pending_req_list); + spin_unlock(&ctx->lock); + + if (cam_debug_ctx_req_list & ctx->dev_id) + CAM_INFO(CAM_CTXT, + "[%s][%d] : Moving req[%llu] from free_list to pending_list", + ctx->dev_name, ctx->ctx_id, req->request_id); + + for (j = 0; j < req->num_in_map_entries; j++) { + rc = cam_sync_check_valid( + req->in_map_entries[j].sync_id); + if (rc) { + CAM_ERR(CAM_CTXT, + "invalid in map sync object %d", + req->in_map_entries[j].sync_id); + goto put_ref; + } + } + + for (j = 0; j < req->num_in_map_entries; j++) { + cam_context_getref(ctx); + rc = cam_sync_register_callback( + cam_context_sync_callback, + (void *)req, + req->in_map_entries[j].sync_id); + if (rc) { + CAM_ERR(CAM_CTXT, + "[%s][%d] Failed register fence cb: %d ret = %d", + ctx->dev_name, ctx->ctx_id, + req->in_map_entries[j].sync_id, rc); + spin_lock(&ctx->lock); + list_del_init(&req->list); + spin_unlock(&ctx->lock); + + if (cam_debug_ctx_req_list & ctx->dev_id) + CAM_INFO(CAM_CTXT, + "[%s][%d] : Moving req[%llu] from pending_list to free_list", + ctx->dev_name, ctx->ctx_id, + req->request_id); + + cam_context_putref(ctx); + goto put_ref; + } + CAM_DBG(CAM_CTXT, "register in fence cb: %d ret = %d", + req->in_map_entries[j].sync_id, rc); + } + } + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); + return rc; +put_ref: + for (--i; i >= 0; i--) { + if (cam_sync_put_obj_ref(req->out_map_entries[i].sync_id)) + CAM_ERR(CAM_CTXT, "Failed to put ref of fence %d", + req->out_map_entries[i].sync_id); + } +free_req: + spin_lock(&ctx->lock); + list_add_tail(&req->list, &ctx->free_req_list); + req->ctx = NULL; + spin_unlock(&ctx->lock); + + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); + return rc; +} + +int32_t cam_context_acquire_dev_to_hw(struct cam_context *ctx, + struct cam_acquire_dev_cmd *cmd) +{ + int rc; + struct cam_hw_acquire_args param; + struct cam_create_dev_hdl req_hdl_param; + struct cam_hw_release_args release; + + if (!ctx || !cmd) { + CAM_ERR(CAM_CTXT, "Invalid input params %pK %pK", ctx, cmd); + rc = -EINVAL; + goto end; + } + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", + ctx->dev_name, ctx->ctx_id); + rc = -EFAULT; + goto end; + } + + CAM_DBG(CAM_CTXT, "ses hdl: %x, num_res: %d, type: %d, res: %lld", + cmd->session_handle, cmd->num_resources, cmd->handle_type, + cmd->resource_hdl); + + if (cmd->num_resources > CAM_CTX_RES_MAX) { + CAM_ERR(CAM_CTXT, "[%s][%d] resource limit exceeded", + ctx->dev_name, ctx->ctx_id); + rc = -ENOMEM; + goto end; + } + + /* for now we only support user pointer */ + if (cmd->handle_type != 1) { + CAM_ERR(CAM_CTXT, "[%s][%d] Only user pointer is supported", + ctx->dev_name, ctx->ctx_id); + rc = -EINVAL; + goto end; + } + + /* fill in parameters */ + param.context_data = ctx; + param.event_cb = ctx->irq_cb_intf; + param.num_acq = cmd->num_resources; + param.acquire_info = cmd->resource_hdl; + + /* call HW manager to reserve the resource */ + rc = ctx->hw_mgr_intf->hw_acquire(ctx->hw_mgr_intf->hw_mgr_priv, + ¶m); + if (rc != 0) { + CAM_ERR(CAM_CTXT, "[%s][%d] Acquire device failed", + ctx->dev_name, ctx->ctx_id); + goto end; + } + + ctx->ctxt_to_hw_map = param.ctxt_to_hw_map; + + /* if hw resource acquire successful, acquire dev handle */ + req_hdl_param.session_hdl = cmd->session_handle; + /* bridge is not ready for these flags. so false for now */ + req_hdl_param.v4l2_sub_dev_flag = 0; + req_hdl_param.media_entity_flag = 0; + req_hdl_param.priv = ctx; + req_hdl_param.ops = ctx->crm_ctx_intf; + req_hdl_param.dev_id = ctx->dev_id; + ctx->dev_hdl = cam_create_device_hdl(&req_hdl_param); + if (ctx->dev_hdl <= 0) { + rc = -EFAULT; + CAM_ERR(CAM_CTXT, "[%s][%d] Can not create device handle", + ctx->dev_name, ctx->ctx_id); + goto free_hw; + } + cmd->dev_handle = ctx->dev_hdl; + + /* store session information */ + ctx->session_hdl = cmd->session_handle; + + return rc; + +free_hw: + release.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + ctx->hw_mgr_intf->hw_release(ctx->hw_mgr_intf->hw_mgr_priv, &release); + ctx->ctxt_to_hw_map = NULL; + ctx->dev_hdl = -1; +end: + return rc; +} + +int32_t cam_context_flush_ctx_to_hw(struct cam_context *ctx) +{ + struct cam_hw_flush_args flush_args; + struct list_head temp_list; + struct cam_ctx_request *req; + uint32_t i; + int rc = 0; + bool free_req; + + CAM_DBG(CAM_CTXT, "[%s] E: NRT flush ctx", ctx->dev_name); + memset(&flush_args, 0, sizeof(flush_args)); + + /* + * flush pending requests, take the sync lock to synchronize with the + * sync callback thread so that the sync cb thread does not try to + * submit request to h/w while the request is being flushed + */ + mutex_lock(&ctx->sync_mutex); + INIT_LIST_HEAD(&temp_list); + spin_lock(&ctx->lock); + list_splice_init(&ctx->pending_req_list, &temp_list); + spin_unlock(&ctx->lock); + + if (cam_debug_ctx_req_list & ctx->dev_id) + CAM_INFO(CAM_CTXT, + "[%s][%d] : Moving all pending requests from pending_list to temp_list", + ctx->dev_name, ctx->ctx_id); + + flush_args.num_req_pending = 0; + flush_args.last_flush_req = ctx->last_flush_req; + while (true) { + spin_lock(&ctx->lock); + if (list_empty(&temp_list)) { + spin_unlock(&ctx->lock); + break; + } + + req = list_first_entry(&temp_list, + struct cam_ctx_request, list); + + list_del_init(&req->list); + spin_unlock(&ctx->lock); + req->flushed = 1; + + flush_args.flush_req_pending[flush_args.num_req_pending++] = + req->req_priv; + + free_req = false; + for (i = 0; i < req->num_in_map_entries; i++) { + rc = cam_sync_deregister_callback( + cam_context_sync_callback, + (void *)req, + req->in_map_entries[i].sync_id); + if (!rc) { + cam_context_putref(ctx); + if (atomic_inc_return(&req->num_in_acked) == + req->num_in_map_entries) + free_req = true; + } + } + + for (i = 0; i < req->num_out_map_entries; i++) { + if (req->out_map_entries[i].sync_id != -1) { + rc = cam_sync_signal( + req->out_map_entries[i].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + if (rc == -EALREADY) { + CAM_ERR(CAM_CTXT, + "Req: %llu already signalled, sync_id:%d", + req->request_id, + req->out_map_entries[i].sync_id); + break; + } + } + } + + /* + * If we have deregistered the last sync callback, req will + * not be put on the free list. So put it on the free list here + */ + if (free_req) { + req->ctx = NULL; + spin_lock(&ctx->lock); + list_add_tail(&req->list, &ctx->free_req_list); + spin_unlock(&ctx->lock); + } + + if (cam_debug_ctx_req_list & ctx->dev_id) + CAM_INFO(CAM_CTXT, + "[%s][%d] : Deleting req[%llu] from temp_list", + ctx->dev_name, ctx->ctx_id, req->request_id); + } + mutex_unlock(&ctx->sync_mutex); + + if (ctx->hw_mgr_intf->hw_flush) { + flush_args.num_req_active = 0; + spin_lock(&ctx->lock); + list_for_each_entry(req, &ctx->active_req_list, list) { + flush_args.flush_req_active[flush_args.num_req_active++] + = req->req_priv; + } + spin_unlock(&ctx->lock); + + if (flush_args.num_req_pending || flush_args.num_req_active) { + flush_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + flush_args.flush_type = CAM_FLUSH_TYPE_ALL; + ctx->hw_mgr_intf->hw_flush( + ctx->hw_mgr_intf->hw_mgr_priv, &flush_args); + } + } + + INIT_LIST_HEAD(&temp_list); + spin_lock(&ctx->lock); + list_splice_init(&ctx->active_req_list, &temp_list); + INIT_LIST_HEAD(&ctx->active_req_list); + spin_unlock(&ctx->lock); + + if (cam_debug_ctx_req_list & ctx->dev_id) + CAM_INFO(CAM_CTXT, + "[%s][%d] : Moving all requests from active_list to temp_list", + ctx->dev_name, ctx->ctx_id); + + while (true) { + spin_lock(&ctx->lock); + if (list_empty(&temp_list)) { + spin_unlock(&ctx->lock); + break; + } + req = list_first_entry(&temp_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + spin_unlock(&ctx->lock); + + for (i = 0; i < req->num_out_map_entries; i++) { + if (req->out_map_entries[i].sync_id != -1) { + rc = cam_sync_signal( + req->out_map_entries[i].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + if (rc == -EALREADY) { + CAM_ERR(CAM_CTXT, + "Req: %llu already signalled ctx: %pK dev_name: %s dev_handle: %d ctx_state: %d", + req->request_id, req->ctx, + req->ctx->dev_name, + req->ctx->dev_hdl, + req->ctx->state); + break; + } + } + } + + spin_lock(&ctx->lock); + list_add_tail(&req->list, &ctx->free_req_list); + spin_unlock(&ctx->lock); + req->ctx = NULL; + + if (cam_debug_ctx_req_list & ctx->dev_id) + CAM_INFO(CAM_CTXT, + "[%s][%d] : Moving req[%llu] from temp_list to free_list", + ctx->dev_name, ctx->ctx_id, req->request_id); + } + + CAM_DBG(CAM_CTXT, "[%s] X: NRT flush ctx", ctx->dev_name); + + return 0; +} + +int32_t cam_context_flush_req_to_hw(struct cam_context *ctx, + struct cam_flush_dev_cmd *cmd) +{ + struct cam_ctx_request *req = NULL; + struct cam_hw_flush_args flush_args; + uint32_t i; + int32_t sync_id = 0; + int rc = 0; + bool free_req = false; + + CAM_DBG(CAM_CTXT, "[%s] E: NRT flush req", ctx->dev_name); + + memset(&flush_args, 0, sizeof(flush_args)); + flush_args.num_req_pending = 0; + flush_args.num_req_active = 0; + mutex_lock(&ctx->sync_mutex); + spin_lock(&ctx->lock); + list_for_each_entry(req, &ctx->pending_req_list, list) { + if (req->request_id != cmd->req_id) + continue; + + if (cam_debug_ctx_req_list & ctx->dev_id) + CAM_INFO(CAM_CTXT, + "[%s][%d] : Deleting req[%llu] from pending_list", + ctx->dev_name, ctx->ctx_id, req->request_id); + + list_del_init(&req->list); + req->flushed = 1; + + flush_args.flush_req_pending[flush_args.num_req_pending++] = + req->req_priv; + break; + } + spin_unlock(&ctx->lock); + mutex_unlock(&ctx->sync_mutex); + + if (ctx->hw_mgr_intf->hw_flush) { + if (!flush_args.num_req_pending) { + spin_lock(&ctx->lock); + list_for_each_entry(req, &ctx->active_req_list, list) { + if (req->request_id != cmd->req_id) + continue; + + list_del_init(&req->list); + + flush_args.flush_req_active[ + flush_args.num_req_active++] = + req->req_priv; + break; + } + spin_unlock(&ctx->lock); + } + + if (flush_args.num_req_pending || flush_args.num_req_active) { + flush_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + flush_args.flush_type = CAM_FLUSH_TYPE_REQ; + ctx->hw_mgr_intf->hw_flush( + ctx->hw_mgr_intf->hw_mgr_priv, &flush_args); + } + } + + if (req) { + if (flush_args.num_req_pending) { + for (i = 0; i < req->num_in_map_entries; i++) { + rc = cam_sync_deregister_callback( + cam_context_sync_callback, + (void *)req, + req->in_map_entries[i].sync_id); + if (rc) + continue; + + cam_context_putref(ctx); + if (atomic_inc_return(&req->num_in_acked) == + req->num_in_map_entries) + free_req = true; + } + } + + if (flush_args.num_req_pending || flush_args.num_req_active) { + for (i = 0; i < req->num_out_map_entries; i++) { + sync_id = + req->out_map_entries[i].sync_id; + if (sync_id != -1) { + rc = cam_sync_signal(sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + if (rc == -EALREADY) { + CAM_ERR(CAM_CTXT, + "Req: %llu already signalled, sync_id:%d", + req->request_id, sync_id); + break; + } + } + } + if (flush_args.num_req_active || free_req) { + req->ctx = NULL; + spin_lock(&ctx->lock); + list_add_tail(&req->list, &ctx->free_req_list); + spin_unlock(&ctx->lock); + + if (cam_debug_ctx_req_list & ctx->dev_id) + CAM_INFO(CAM_CTXT, + "[%s][%d] : Moving req[%llu] from %s to free_list", + ctx->dev_name, ctx->ctx_id, + req->request_id, + flush_args.num_req_active ? + "active_list" : + "pending_list"); + } + } + } + CAM_DBG(CAM_CTXT, "[%s] X: NRT flush req", ctx->dev_name); + + return 0; +} + +int32_t cam_context_flush_dev_to_hw(struct cam_context *ctx, + struct cam_flush_dev_cmd *cmd) +{ + + int rc = 0; + + if (!ctx || !cmd) { + CAM_ERR(CAM_CTXT, "Invalid input params %pK %pK", ctx, cmd); + rc = -EINVAL; + goto end; + } + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", + ctx->dev_name, ctx->ctx_id); + rc = -EFAULT; + goto end; + } + + if (cmd->flush_type == CAM_FLUSH_TYPE_ALL) { + ctx->last_flush_req = cmd->req_id; + rc = cam_context_flush_ctx_to_hw(ctx); + } else if (cmd->flush_type == CAM_FLUSH_TYPE_REQ) + rc = cam_context_flush_req_to_hw(ctx, cmd); + else { + rc = -EINVAL; + CAM_ERR(CAM_CORE, "[%s][%d] Invalid flush type %d", + ctx->dev_name, ctx->ctx_id, cmd->flush_type); + } + +end: + return rc; +} + +int32_t cam_context_start_dev_to_hw(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc = 0; + struct cam_hw_start_args arg; + + if (!ctx || !cmd) { + CAM_ERR(CAM_CTXT, "Invalid input params %pK %pK", ctx, cmd); + rc = -EINVAL; + goto end; + } + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", + ctx->dev_name, ctx->ctx_id); + rc = -EFAULT; + goto end; + } + + if ((cmd->session_handle != ctx->session_hdl) || + (cmd->dev_handle != ctx->dev_hdl)) { + CAM_ERR(CAM_CTXT, + "[%s][%d] Invalid session hdl[%d], dev_handle[%d]", + ctx->dev_name, ctx->ctx_id, + cmd->session_handle, cmd->dev_handle); + rc = -EPERM; + goto end; + } + + if (ctx->hw_mgr_intf->hw_start) { + arg.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + rc = ctx->hw_mgr_intf->hw_start(ctx->hw_mgr_intf->hw_mgr_priv, + &arg); + if (rc) { + /* HW failure. user need to clean up the resource */ + CAM_ERR(CAM_CTXT, "[%s][%d] Start HW failed", + ctx->dev_name, ctx->ctx_id); + goto end; + } + } + +end: + return rc; +} + +int32_t cam_context_stop_dev_to_hw(struct cam_context *ctx) +{ + int rc = 0; + struct cam_hw_stop_args stop; + + if (!ctx) { + CAM_ERR(CAM_CTXT, "Invalid input param"); + rc = -EINVAL; + goto end; + } + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", + ctx->dev_name, ctx->ctx_id); + rc = -EFAULT; + goto end; + } + + rc = cam_context_validate_thread(); + if (rc) + goto end; + + rc = cam_context_flush_ctx_to_hw(ctx); + if (rc) + goto end; + + /* stop hw first */ + if (ctx->hw_mgr_intf->hw_stop) { + stop.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + ctx->hw_mgr_intf->hw_stop(ctx->hw_mgr_intf->hw_mgr_priv, + &stop); + } + +end: + return rc; +} + +int32_t cam_context_dump_pf_info_to_hw(struct cam_context *ctx, + struct cam_packet *packet, unsigned long iova, uint32_t buf_info, + bool *mem_found) +{ + int rc = 0; + struct cam_hw_cmd_args cmd_args; + + if (!ctx) { + CAM_ERR(CAM_CTXT, "Invalid input params %pK ", ctx); + rc = -EINVAL; + goto end; + } + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", + ctx->dev_name, ctx->ctx_id); + rc = -EFAULT; + goto end; + } + + if (ctx->hw_mgr_intf->hw_cmd) { + cmd_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + cmd_args.cmd_type = CAM_HW_MGR_CMD_DUMP_PF_INFO; + cmd_args.u.pf_args.pf_data.packet = packet; + cmd_args.u.pf_args.iova = iova; + cmd_args.u.pf_args.buf_info = buf_info; + cmd_args.u.pf_args.mem_found = mem_found; + ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &cmd_args); + } + +end: + return rc; +} + +int32_t cam_context_dump_hw_acq_info(struct cam_context *ctx) +{ + int rc = 0; + struct cam_hw_cmd_args cmd_args; + + if (!ctx) { + CAM_ERR(CAM_CTXT, "Invalid input params"); + rc = -EINVAL; + goto end; + } + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", + ctx->dev_name, ctx->ctx_id); + rc = -EFAULT; + goto end; + } + + if (ctx->hw_mgr_intf->hw_cmd) { + cmd_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + cmd_args.cmd_type = CAM_HW_MGR_CMD_DUMP_ACQ_INFO; + ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &cmd_args); + } + +end: + return rc; +} + +static int cam_context_dump_context(struct cam_context *ctx, + struct cam_hw_dump_args *dump_args) +{ + int rc; + int i; + size_t buf_len; + size_t remain_len; + uint8_t *dst; + uint64_t *addr, *start; + uint32_t min_len; + uintptr_t cpu_addr; + struct cam_ctx_request *req; + struct cam_context_dump_header *hdr; + + if (!ctx || !dump_args) { + CAM_ERR(CAM_CORE, "Invalid parameters %pK %pK", + ctx, dump_args); + return -EINVAL; + } + + spin_lock_bh(&ctx->lock); + if (list_empty(&ctx->active_req_list)) { + CAM_ERR(CAM_CTXT, "[%s][%d] no active request", + ctx->dev_name, ctx->ctx_id); + spin_unlock_bh(&ctx->lock); + return -EIO; + } + req = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + spin_unlock_bh(&ctx->lock); + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &cpu_addr, &buf_len); + if (rc) { + CAM_ERR(CAM_CTXT, "Invalid hdl %u rc %d", + dump_args->buf_handle, rc); + return rc; + } + if (dump_args->offset >= buf_len) { + CAM_WARN(CAM_CTXT, "dump buffer overshoot offset %zu len %zu", + dump_args->offset, buf_len); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return -ENOSPC; + } + + remain_len = buf_len - dump_args->offset; + min_len = sizeof(struct cam_context_dump_header) + + (CAM_CTXT_DUMP_NUM_WORDS + req->num_in_map_entries + + (req->num_out_map_entries * 2)) * sizeof(uint64_t); + + if (remain_len < min_len) { + CAM_WARN(CAM_CTXT, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return -ENOSPC; + } + dst = (uint8_t *)cpu_addr + dump_args->offset; + hdr = (struct cam_context_dump_header *)dst; + scnprintf(hdr->tag, CAM_CTXT_DUMP_TAG_MAX_LEN, + "%s_CTXT_DUMP:", ctx->dev_name); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + sizeof(struct cam_context_dump_header)); + start = addr; + *addr++ = ctx->ctx_id; + *addr++ = refcount_read(&(ctx->refcount.refcount)); + *addr++ = ctx->last_flush_req; + *addr++ = ctx->state; + *addr++ = req->num_out_map_entries; + for (i = 0; i < req->num_out_map_entries; i++) { + *addr++ = req->out_map_entries[i].resource_handle; + *addr++ = req->out_map_entries[i].sync_id; + } + *addr++ = req->num_in_map_entries; + for (i = 0; i < req->num_in_map_entries; i++) + *addr++ = req->in_map_entries[i].sync_id; + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_context_dump_header); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return 0; +} + +int32_t cam_context_dump_dev_to_hw(struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc = 0; + struct cam_hw_dump_args dump_args; + + if (!ctx || !cmd) { + CAM_ERR(CAM_CTXT, "Invalid input params %pK %pK", ctx, cmd); + return -EINVAL; + } + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", + ctx->dev_name, ctx->ctx_id); + return -EFAULT; + } + memset(&dump_args, 0, sizeof(dump_args)); + if (ctx->hw_mgr_intf->hw_dump) { + dump_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + dump_args.buf_handle = cmd->buf_handle; + dump_args.offset = cmd->offset; + dump_args.request_id = cmd->issue_req_id; + dump_args.error_type = cmd->error_type; + rc = ctx->hw_mgr_intf->hw_dump( + ctx->hw_mgr_intf->hw_mgr_priv, + &dump_args); + if (rc) { + CAM_ERR(CAM_CTXT, "[%s][%d] handle[%u] failed", + ctx->dev_name, ctx->ctx_id, dump_args.buf_handle); + return rc; + } + /* Offset will change if the issue request id is found with + * the hw and has been lying with it beyond threshold time. + * If offset does not change, do not dump the context + * information as the current context has no problem with + * the provided request id. + */ + if (dump_args.offset > cmd->offset) { + cam_context_dump_context(ctx, &dump_args); + CAM_INFO(CAM_CTXT, "[%s] ctx: %d Filled Length %u", + ctx->dev_name, ctx->ctx_id, + dump_args.offset - cmd->offset); + cmd->offset = dump_args.offset; + } + } else { + CAM_DBG(CAM_CTXT, "%s hw dump not registered", ctx->dev_name); + } + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_core/cam_context_utils.h b/techpack/camera-bengal/drivers/cam_core/cam_context_utils.h new file mode 100644 index 0000000000000000000000000000000000000000..79dec3142e8ac179a7283cb1b3d2b68e4b7153c2 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_core/cam_context_utils.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CONTEXT_UTILS_H_ +#define _CAM_CONTEXT_UTILS_H_ + +#include + +int cam_context_buf_done_from_hw(struct cam_context *ctx, + void *done_event_data, uint32_t bubble_state); +int32_t cam_context_release_dev_to_hw(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd); +int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd); +int32_t cam_context_config_dev_to_hw( + struct cam_context *ctx, struct cam_config_dev_cmd *cmd); +int32_t cam_context_acquire_dev_to_hw(struct cam_context *ctx, + struct cam_acquire_dev_cmd *cmd); +int32_t cam_context_start_dev_to_hw(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd); +int32_t cam_context_stop_dev_to_hw(struct cam_context *ctx); +int32_t cam_context_flush_dev_to_hw(struct cam_context *ctx, + struct cam_flush_dev_cmd *cmd); +int32_t cam_context_flush_ctx_to_hw(struct cam_context *ctx); +int32_t cam_context_flush_req_to_hw(struct cam_context *ctx, + struct cam_flush_dev_cmd *cmd); +int32_t cam_context_dump_pf_info_to_hw(struct cam_context *ctx, + struct cam_packet *packet, unsigned long iova, uint32_t buf_info, + bool *mem_found); +int32_t cam_context_dump_hw_acq_info(struct cam_context *ctx); +int32_t cam_context_dump_dev_to_hw(struct cam_context *ctx, + struct cam_dump_req_cmd *cmd); +#endif /* _CAM_CONTEXT_UTILS_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_core/cam_hw.h b/techpack/camera-bengal/drivers/cam_core/cam_hw.h new file mode 100644 index 0000000000000000000000000000000000000000..8ee889fcffb93eb70e47e1e6e4508e7a09609a4c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_core/cam_hw.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_HW_H_ +#define _CAM_HW_H_ + +#include "cam_soc_util.h" + +/* + * This file declares Enums, Structures and APIs to be used as template + * when writing any HW driver in the camera subsystem. + */ + +/* Hardware state enum */ +enum cam_hw_state { + CAM_HW_STATE_POWER_DOWN, + CAM_HW_STATE_POWER_UP, +}; + +/** + * struct cam_hw_info - Common hardware information + * + * @hw_mutex: Hardware mutex + * @hw_lock: Hardware spinlock + * @hw_complete: Hardware Completion + * @open_count: Count to track the HW enable from the client + * @hw_state: Hardware state + * @soc_info: Platform SOC properties for hardware + * @node_info: Private HW data related to nodes + * @core_info: Private HW data related to core logic + * + */ +struct cam_hw_info { + struct mutex hw_mutex; + spinlock_t hw_lock; + struct completion hw_complete; + uint32_t open_count; + enum cam_hw_state hw_state; + struct cam_hw_soc_info soc_info; + void *node_info; + void *core_info; +}; + +#endif /* _CAM_HW_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_core/cam_hw_intf.h b/techpack/camera-bengal/drivers/cam_core/cam_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..63e88dd24aeab74c22f8c023cb9cfadeb01f4833 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_core/cam_hw_intf.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_HW_INTF_H_ +#define _CAM_HW_INTF_H_ + +#include + +/* + * This file declares Constants, Enums, Structures and APIs to be used as + * Interface between HW driver and HW Manager. + */ + +/** + * struct cam_hw_ops - Hardware layer interface functions + * + * @get_hw_caps: Function pointer for get hw caps + * @init: Function poniter for initialize hardware + * @deinit: Function pointer for deinitialize hardware + * @reset: Function pointer for reset hardware + * @reserve: Function pointer for reserve hardware + * @release: Function pointer for release hardware + * @start: Function pointer for start hardware + * @stop: Function pointer for stop hardware + * @read: Function pointer for read hardware registers + * @write: Function pointer for Write hardware registers + * @process_cmd: Function pointer for additional hardware controls + * @flush_cmd: Function pointer for flush requests + * + */ +struct cam_hw_ops { + int (*get_hw_caps)(void *hw_priv, + void *get_hw_cap_args, uint32_t arg_size); + int (*init)(void *hw_priv, + void *init_hw_args, uint32_t arg_size); + int (*deinit)(void *hw_priv, + void *init_hw_args, uint32_t arg_size); + int (*reset)(void *hw_priv, + void *reset_core_args, uint32_t arg_size); + int (*reserve)(void *hw_priv, + void *reserve_args, uint32_t arg_size); + int (*release)(void *hw_priv, + void *release_args, uint32_t arg_size); + int (*start)(void *hw_priv, + void *start_args, uint32_t arg_size); + int (*stop)(void *hw_priv, + void *stop_args, uint32_t arg_size); + int (*read)(void *hw_priv, + void *read_args, uint32_t arg_size); + int (*write)(void *hw_priv, + void *write_args, uint32_t arg_size); + int (*process_cmd)(void *hw_priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size); + int (*flush)(void *hw_priv, + void *flush_args, uint32_t arg_size); +}; + +/** + * struct cam_hw_intf - Common hardware node + * + * @hw_type: Hardware type + * @hw_idx: Hardware ID + * @hw_ops: Hardware interface function table + * @hw_priv: Private hardware node pointer + * + */ +struct cam_hw_intf { + uint32_t hw_type; + uint32_t hw_idx; + struct cam_hw_ops hw_ops; + void *hw_priv; +}; + +/* hardware event callback function type */ +typedef int (*cam_hw_mgr_event_cb_func)(void *priv, uint32_t evt_id, + void *evt_data); + +#endif /* _CAM_HW_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_core/cam_hw_mgr_intf.h b/techpack/camera-bengal/drivers/cam_core/cam_hw_mgr_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..1e2c1f7a70089da35087f77d1a23c0617f019ee3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_core/cam_hw_mgr_intf.h @@ -0,0 +1,400 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_HW_MGR_INTF_H_ +#define _CAM_HW_MGR_INTF_H_ + +#include +#include +#include +/* + * This file declares Constants, Enums, Structures and APIs to be used as + * Interface between HW Manager and Context. + */ + + +/* maximum context numbers */ +#define CAM_CTX_MAX 8 + +/* maximum buf done irqs */ +#define CAM_NUM_OUT_PER_COMP_IRQ_MAX 12 + +/* Maximum reg dump cmd buffer entries in a context */ +#define CAM_REG_DUMP_MAX_BUF_ENTRIES 10 + +/** + * enum cam_context_dump_id - + * context dump type + * + */ +enum cam_context_dump_id { + CAM_CTX_DUMP_TYPE_NONE, + CAM_CTX_DUMP_ACQ_INFO, + CAM_CTX_DUMP_TYPE_MAX, +}; + +/* hardware event callback function type */ +typedef int (*cam_hw_event_cb_func)(void *context, uint32_t evt_id, + void *evt_data); + +/* hardware page fault callback function type */ +typedef int (*cam_hw_pagefault_cb_func)(void *context, unsigned long iova, + uint32_t buf_info); + +/* ctx dump callback function type */ +typedef int (*cam_ctx_info_dump_cb_func)(void *context, + enum cam_context_dump_id dump_id); + +/** + * struct cam_hw_update_entry - Entry for hardware config + * + * @handle: Memory handle for the configuration + * @offset: Memory offset + * @len: Size of the configuration + * @flags: Flags for the config entry(eg. DMI) + * @addr: Address of hardware update entry + * + */ +struct cam_hw_update_entry { + int handle; + uint32_t offset; + uint32_t len; + uint32_t flags; + uintptr_t addr; +}; + +/** + * struct cam_hw_fence_map_entry - Entry for the resource to sync id map + * + * @resrouce_handle: Resource port id for the buffer + * @sync_id: Sync id + * + */ +struct cam_hw_fence_map_entry { + uint32_t resource_handle; + int32_t sync_id; +}; + +/** + * struct cam_hw_done_event_data - Payload for hw done event + * + * @num_handles: number of handles in the event + * @resrouce_handle: list of the resource handle + * @timestamp: time stamp + * @request_id: request identifier + * + */ +struct cam_hw_done_event_data { + uint32_t num_handles; + uint32_t resource_handle[CAM_NUM_OUT_PER_COMP_IRQ_MAX]; + struct timeval timestamp; + uint64_t request_id; +}; + +/** + * struct cam_hw_acquire_args - Payload for acquire command + * + * @context_data: Context data pointer for the callback function + * @event_cb: Callback function array + * @num_acq: Total number of acquire in the payload + * @acquire_info: Acquired resource array pointer + * @ctxt_to_hw_map: HW context (returned) + * @acquired_hw_id: Acquired hardware mask + * @acquired_hw_path: Acquired path mask for an input + * if input splits into multiple paths, + * its updated per hardware + * valid_acquired_hw: Valid num of acquired hardware + * + */ +struct cam_hw_acquire_args { + void *context_data; + cam_hw_event_cb_func event_cb; + uint32_t num_acq; + uint32_t acquire_info_size; + uintptr_t acquire_info; + void *ctxt_to_hw_map; + + uint32_t acquired_hw_id[CAM_MAX_ACQ_RES]; + uint32_t acquired_hw_path[CAM_MAX_ACQ_RES][CAM_MAX_HW_SPLIT]; + uint32_t valid_acquired_hw; +}; + +/** + * struct cam_hw_release_args - Payload for release command + * + * @ctxt_to_hw_map: HW context from the acquire + * @active_req: Active request flag + * + */ +struct cam_hw_release_args { + void *ctxt_to_hw_map; + bool active_req; +}; + +/** + * struct cam_hw_start_args - Payload for start command + * + * @ctxt_to_hw_map: HW context from the acquire + * @num_hw_update_entries: Number of Hardware configuration + * @hw_update_entries: Hardware configuration list + * + */ +struct cam_hw_start_args { + void *ctxt_to_hw_map; + uint32_t num_hw_update_entries; + struct cam_hw_update_entry *hw_update_entries; +}; + +/** + * struct cam_hw_stop_args - Payload for stop command + * + * @ctxt_to_hw_map: HW context from the acquire + * @args: Arguments to pass for stop + * + */ +struct cam_hw_stop_args { + void *ctxt_to_hw_map; + void *args; +}; + + +/** + * struct cam_hw_mgr_dump_pf_data - page fault debug data + * + * packet: pointer to packet + */ +struct cam_hw_mgr_dump_pf_data { + void *packet; +}; + +/** + * struct cam_hw_prepare_update_args - Payload for prepare command + * + * @packet: CSL packet from user mode driver + * @remain_len Remaining length of CPU buffer after config offset + * @ctxt_to_hw_map: HW context from the acquire + * @max_hw_update_entries: Maximum hardware update entries supported + * @hw_update_entries: Actual hardware update configuration (returned) + * @num_hw_update_entries: Number of actual hardware update entries (returned) + * @max_out_map_entries: Maximum output fence mapping supported + * @out_map_entries: Actual output fence mapping list (returned) + * @num_out_map_entries: Number of actual output fence mapping (returned) + * @max_in_map_entries: Maximum input fence mapping supported + * @in_map_entries: Actual input fence mapping list (returned) + * @num_in_map_entries: Number of acutal input fence mapping (returned) + * @reg_dump_buf_desc: cmd buffer descriptors for reg dump + * @num_reg_dump_buf: Count of descriptors in reg_dump_buf_desc + * @priv: Private pointer of hw update + * @pf_data: Debug data for page fault + * + */ +struct cam_hw_prepare_update_args { + struct cam_packet *packet; + size_t remain_len; + void *ctxt_to_hw_map; + uint32_t max_hw_update_entries; + struct cam_hw_update_entry *hw_update_entries; + uint32_t num_hw_update_entries; + uint32_t max_out_map_entries; + struct cam_hw_fence_map_entry *out_map_entries; + uint32_t num_out_map_entries; + uint32_t max_in_map_entries; + struct cam_hw_fence_map_entry *in_map_entries; + uint32_t num_in_map_entries; + struct cam_cmd_buf_desc reg_dump_buf_desc[ + CAM_REG_DUMP_MAX_BUF_ENTRIES]; + uint32_t num_reg_dump_buf; + void *priv; + struct cam_hw_mgr_dump_pf_data *pf_data; +}; + +/** + * struct cam_hw_stream_setttings - Payload for config stream command + * + * @packet: CSL packet from user mode driver + * @ctxt_to_hw_map: HW context from the acquire + * @priv: Private pointer of hw update + * + */ +struct cam_hw_stream_setttings { + struct cam_packet *packet; + void *ctxt_to_hw_map; + void *priv; +}; + +/** + * struct cam_hw_config_args - Payload for config command + * + * @ctxt_to_hw_map: HW context from the acquire + * @num_hw_update_entries: Number of hardware update entries + * @hw_update_entries: Hardware update list + * @out_map_entries: Out map info + * @num_out_map_entries: Number of out map entries + * @priv: Private pointer + * @request_id: Request ID + * @reapply True if reapplying after bubble + * + */ +struct cam_hw_config_args { + void *ctxt_to_hw_map; + uint32_t num_hw_update_entries; + struct cam_hw_update_entry *hw_update_entries; + struct cam_hw_fence_map_entry *out_map_entries; + uint32_t num_out_map_entries; + void *priv; + uint64_t request_id; + bool init_packet; + bool reapply; +}; + +/** + * struct cam_hw_flush_args - Flush arguments + * + * @ctxt_to_hw_map: HW context from the acquire + * @num_req_pending: Num request to flush, valid when flush type is REQ + * @flush_req_pending: Request pending pointers to flush + * @num_req_active: Num request to flush, valid when flush type is REQ + * @flush_req_active: Request active pointers to flush + * @flush_type: The flush type + * @last_flush_req: last flush req_id notified to hw_mgr for the + * given stream + * + */ +struct cam_hw_flush_args { + void *ctxt_to_hw_map; + uint32_t num_req_pending; + void *flush_req_pending[20]; + uint32_t num_req_active; + void *flush_req_active[20]; + enum flush_type_t flush_type; + uint32_t last_flush_req; +}; + +/** + * struct cam_hw_dump_pf_args - Payload for dump pf info command + * + * @pf_data: Debug data for page fault + * @iova: Page fault address + * @buf_info: Info about memory buffer where page + * fault occurred + * @mem_found: If fault memory found in current + * request + * + */ +struct cam_hw_dump_pf_args { + struct cam_hw_mgr_dump_pf_data pf_data; + unsigned long iova; + uint32_t buf_info; + bool *mem_found; +}; + +/** + * struct cam_hw_reset_args -hw reset arguments + * + * @ctxt_to_hw_map: HW context from the acquire + * + */ +struct cam_hw_reset_args { + void *ctxt_to_hw_map; +}; + +/** + * struct cam_hw_dump_args - Dump arguments + * + * @request_id: request_id + * @offset: Buffer offset. This is updated by the drivers. + * @buf_handle: Buffer handle + * @error_type: Error type, to be used to extend dump information + * @ctxt_to_hw_map: HW context from the acquire + */ +struct cam_hw_dump_args { + uint64_t request_id; + size_t offset; + uint32_t buf_handle; + uint32_t error_type; + void *ctxt_to_hw_map; +}; + +/* enum cam_hw_mgr_command - Hardware manager command type */ +enum cam_hw_mgr_command { + CAM_HW_MGR_CMD_INTERNAL, + CAM_HW_MGR_CMD_DUMP_PF_INFO, + CAM_HW_MGR_CMD_REG_DUMP_ON_FLUSH, + CAM_HW_MGR_CMD_REG_DUMP_ON_ERROR, + CAM_HW_MGR_CMD_DUMP_ACQ_INFO, +}; + +/** + * struct cam_hw_cmd_args - Payload for hw manager command + * + * @ctxt_to_hw_map: HW context from the acquire + * @cmd_type HW command type + * @internal_args Arguments for internal command + * @pf_args Arguments for Dump PF info command + * + */ +struct cam_hw_cmd_args { + void *ctxt_to_hw_map; + uint32_t cmd_type; + union { + void *internal_args; + struct cam_hw_dump_pf_args pf_args; + } u; +}; + +/** + * cam_hw_mgr_intf - HW manager interface + * + * @hw_mgr_priv: HW manager object + * @hw_get_caps: Function pointer for get hw caps + * args = cam_query_cap_cmd + * @hw_acquire: Function poniter for acquire hw resources + * args = cam_hw_acquire_args + * @hw_release: Function pointer for release hw device resource + * args = cam_hw_release_args + * @hw_start: Function pointer for start hw devices + * args = cam_hw_start_args + * @hw_stop: Function pointer for stop hw devices + * args = cam_hw_stop_args + * @hw_prepare_update: Function pointer for prepare hw update for hw + * devices args = cam_hw_prepare_update_args + * @hw_config_stream_settings: Function pointer for configure stream for hw + * devices args = cam_hw_stream_setttings + * @hw_config: Function pointer for configure hw devices + * args = cam_hw_config_args + * @hw_read: Function pointer for read hardware registers + * @hw_write: Function pointer for Write hardware registers + * @hw_cmd: Function pointer for any customized commands for + * the hardware manager + * @hw_open: Function pointer for HW init + * @hw_close: Function pointer for HW deinit + * @hw_flush: Function pointer for HW flush + * @hw_reset: Function pointer for HW reset + * @hw_dump: Function pointer for HW dump + * + */ +struct cam_hw_mgr_intf { + void *hw_mgr_priv; + + int (*hw_get_caps)(void *hw_priv, void *hw_caps_args); + int (*hw_acquire)(void *hw_priv, void *hw_acquire_args); + int (*hw_release)(void *hw_priv, void *hw_release_args); + int (*hw_start)(void *hw_priv, void *hw_start_args); + int (*hw_stop)(void *hw_priv, void *hw_stop_args); + int (*hw_prepare_update)(void *hw_priv, void *hw_prepare_update_args); + int (*hw_config_stream_settings)(void *hw_priv, + void *hw_stream_settings); + int (*hw_config)(void *hw_priv, void *hw_config_args); + int (*hw_read)(void *hw_priv, void *read_args); + int (*hw_write)(void *hw_priv, void *write_args); + int (*hw_cmd)(void *hw_priv, void *write_args); + int (*hw_open)(void *hw_priv, void *fw_download_args); + int (*hw_close)(void *hw_priv, void *hw_close_args); + int (*hw_flush)(void *hw_priv, void *hw_flush_args); + int (*hw_reset)(void *hw_priv, void *hw_reset_args); + int (*hw_dump)(void *hw_priv, void *hw_dump_args); +}; + +#endif /* _CAM_HW_MGR_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_core/cam_node.c b/techpack/camera-bengal/drivers/cam_core/cam_node.c new file mode 100644 index 0000000000000000000000000000000000000000..4ad93c7f5537ab99c5b4631457c393d669549e3a --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_core/cam_node.c @@ -0,0 +1,964 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include + +#include "cam_node.h" +#include "cam_trace.h" +#include "cam_debug_util.h" + +static void cam_node_print_ctx_state( + struct cam_node *node) +{ + int i; + struct cam_context *ctx; + + CAM_INFO(CAM_CORE, "[%s] state=%d, ctx_size %d", + node->name, node->state, node->ctx_size); + + mutex_lock(&node->list_mutex); + for (i = 0; i < node->ctx_size; i++) { + ctx = &node->ctx_list[i]; + + spin_lock_bh(&ctx->lock); + CAM_INFO(CAM_CORE, + "[%s][%d] : state=%d, refcount=%d, active_req_list=%d, pending_req_list=%d, wait_req_list=%d, free_req_list=%d", + ctx->dev_name, + i, ctx->state, + atomic_read(&(ctx->refcount.refcount.refs)), + list_empty(&ctx->active_req_list), + list_empty(&ctx->pending_req_list), + list_empty(&ctx->wait_req_list), + list_empty(&ctx->free_req_list)); + spin_unlock_bh(&ctx->lock); + } + mutex_unlock(&node->list_mutex); +} + +static struct cam_context *cam_node_get_ctxt_from_free_list( + struct cam_node *node) +{ + struct cam_context *ctx = NULL; + + mutex_lock(&node->list_mutex); + if (!list_empty(&node->free_ctx_list)) { + ctx = list_first_entry(&node->free_ctx_list, + struct cam_context, list); + list_del_init(&ctx->list); + } + mutex_unlock(&node->list_mutex); + if (ctx) + kref_init(&ctx->refcount); + return ctx; +} + +void cam_node_put_ctxt_to_free_list(struct kref *ref) +{ + struct cam_context *ctx = + container_of(ref, struct cam_context, refcount); + struct cam_node *node = ctx->node; + + mutex_lock(&node->list_mutex); + list_add_tail(&ctx->list, &node->free_ctx_list); + mutex_unlock(&node->list_mutex); +} + +static int __cam_node_handle_query_cap(struct cam_node *node, + struct cam_query_cap_cmd *query) +{ + int rc = -EFAULT; + + if (!query) { + CAM_ERR(CAM_CORE, "Invalid params"); + return -EINVAL; + } + + if (node->hw_mgr_intf.hw_get_caps) { + rc = node->hw_mgr_intf.hw_get_caps( + node->hw_mgr_intf.hw_mgr_priv, query); + } + + return rc; +} + +static int __cam_node_handle_acquire_dev(struct cam_node *node, + struct cam_acquire_dev_cmd *acquire) +{ + int rc = 0; + struct cam_context *ctx = NULL; + + if (!acquire) + return -EINVAL; + + ctx = cam_node_get_ctxt_from_free_list(node); + if (!ctx) { + CAM_ERR(CAM_CORE, + "No free ctx in free list node %s with size:%d", + node->name, node->ctx_size); + cam_node_print_ctx_state(node); + + rc = -ENOMEM; + goto err; + } + + ctx->last_flush_req = 0; + rc = cam_context_handle_acquire_dev(ctx, acquire); + if (rc) { + CAM_ERR(CAM_CORE, "Acquire device failed for node %s", + node->name); + goto free_ctx; + } + + CAM_DBG(CAM_CORE, "[%s] Acquire ctx_id %d", + node->name, ctx->ctx_id); + + return 0; +free_ctx: + cam_context_putref(ctx); +err: + return rc; +} + +static void __cam_node_handle_acquired_hw_dump( + struct cam_node *node) +{ + int i; + + for (i = 0; i < node->ctx_size; i++) + cam_context_handle_info_dump(&(node->ctx_list[i]), + CAM_CTX_DUMP_ACQ_INFO); +} + +static int __cam_node_handle_acquire_hw_v1(struct cam_node *node, + struct cam_acquire_hw_cmd_v1 *acquire) +{ + int rc = 0; + struct cam_context *ctx = NULL; + + if (!acquire) + return -EINVAL; + + if (acquire->dev_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid device handle for context"); + return -EINVAL; + } + + if (acquire->session_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid session handle for context"); + return -EINVAL; + } + + ctx = (struct cam_context *)cam_get_device_priv(acquire->dev_handle); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + acquire->dev_handle); + return -EINVAL; + } + + if (strcmp(node->name, ctx->dev_name)) { + CAM_ERR(CAM_CORE, "node name %s dev name:%s not matching", + node->name, ctx->dev_name); + return -EINVAL; + } + + rc = cam_context_handle_acquire_hw(ctx, acquire); + if (rc) { + CAM_ERR(CAM_CORE, "Acquire device failed for node %s", + node->name); + __cam_node_handle_acquired_hw_dump(node); + return rc; + } + + CAM_DBG(CAM_CORE, "[%s] Acquire ctx_id %d", + node->name, ctx->ctx_id); + + return 0; +} + +static int __cam_node_handle_acquire_hw_v2(struct cam_node *node, + struct cam_acquire_hw_cmd_v2 *acquire) +{ + int rc = 0; + struct cam_context *ctx = NULL; + + if (!acquire) + return -EINVAL; + + if (acquire->dev_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid device handle for context"); + return -EINVAL; + } + + if (acquire->session_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid session handle for context"); + return -EINVAL; + } + + ctx = (struct cam_context *)cam_get_device_priv(acquire->dev_handle); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + acquire->dev_handle); + return -EINVAL; + } + + rc = cam_context_handle_acquire_hw(ctx, acquire); + if (rc) { + CAM_ERR(CAM_CORE, "Acquire device failed for node %s", + node->name); + __cam_node_handle_acquired_hw_dump(node); + return rc; + } + + CAM_DBG(CAM_CORE, "[%s] Acquire ctx_id %d", + node->name, ctx->ctx_id); + + return 0; +} + +static int __cam_node_handle_start_dev(struct cam_node *node, + struct cam_start_stop_dev_cmd *start) +{ + struct cam_context *ctx = NULL; + int rc; + + if (!start) + return -EINVAL; + + if (start->dev_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid device handle for context"); + return -EINVAL; + } + + if (start->session_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid session handle for context"); + return -EINVAL; + } + + ctx = (struct cam_context *)cam_get_device_priv(start->dev_handle); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + start->dev_handle); + return -EINVAL; + } + + if (strcmp(node->name, ctx->dev_name)) { + CAM_ERR(CAM_CORE, "node name %s dev name:%s not matching", + node->name, ctx->dev_name); + return -EINVAL; + } + + rc = cam_context_handle_start_dev(ctx, start); + if (rc) + CAM_ERR(CAM_CORE, "Start failure for node %s", node->name); + + return rc; +} + +static int __cam_node_handle_stop_dev(struct cam_node *node, + struct cam_start_stop_dev_cmd *stop) +{ + struct cam_context *ctx = NULL; + int rc; + + if (!stop) + return -EINVAL; + + if (stop->dev_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid device handle for context"); + return -EINVAL; + } + + if (stop->session_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid session handle for context"); + return -EINVAL; + } + + ctx = (struct cam_context *)cam_get_device_priv(stop->dev_handle); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + stop->dev_handle); + return -EINVAL; + } + + if (strcmp(node->name, ctx->dev_name)) { + CAM_ERR(CAM_CORE, "node name %s dev name:%s not matching", + node->name, ctx->dev_name); + return -EINVAL; + } + + rc = cam_context_handle_stop_dev(ctx, stop); + if (rc) + CAM_ERR(CAM_CORE, "Stop failure for node %s", node->name); + + return rc; +} + +static int __cam_node_handle_config_dev(struct cam_node *node, + struct cam_config_dev_cmd *config) +{ + struct cam_context *ctx = NULL; + int rc; + + if (!config) + return -EINVAL; + + if (config->dev_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid device handle for context"); + return -EINVAL; + } + + if (config->session_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid session handle for context"); + return -EINVAL; + } + + ctx = (struct cam_context *)cam_get_device_priv(config->dev_handle); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + config->dev_handle); + return -EINVAL; + } + + if (strcmp(node->name, ctx->dev_name)) { + CAM_ERR(CAM_CORE, "node name %s dev name:%s not matching", + node->name, ctx->dev_name); + return -EINVAL; + } + + rc = cam_context_handle_config_dev(ctx, config); + if (rc) + CAM_ERR(CAM_CORE, "Config failure for node %s", node->name); + + return rc; +} + +static int __cam_node_handle_flush_dev(struct cam_node *node, + struct cam_flush_dev_cmd *flush) +{ + struct cam_context *ctx = NULL; + int rc; + + if (!flush) + return -EINVAL; + + if (flush->dev_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid device handle for context"); + return -EINVAL; + } + + if (flush->session_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid session handle for context"); + return -EINVAL; + } + + ctx = (struct cam_context *)cam_get_device_priv(flush->dev_handle); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + flush->dev_handle); + return -EINVAL; + } + + if (strcmp(node->name, ctx->dev_name)) { + CAM_ERR(CAM_CORE, "node name %s dev name:%s not matching", + node->name, ctx->dev_name); + return -EINVAL; + } + + rc = cam_context_handle_flush_dev(ctx, flush); + if (rc) + CAM_ERR(CAM_CORE, "Flush failure for node %s", node->name); + + return rc; +} + +static int __cam_node_handle_release_dev(struct cam_node *node, + struct cam_release_dev_cmd *release) +{ + int rc = 0; + struct cam_context *ctx = NULL; + + if (!release) + return -EINVAL; + + if (release->dev_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid device handle for context"); + return -EINVAL; + } + + if (release->session_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid session handle for context"); + return -EINVAL; + } + + ctx = (struct cam_context *)cam_get_device_priv(release->dev_handle); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d node %s", + release->dev_handle, node->name); + return -EINVAL; + } + + if (strcmp(node->name, ctx->dev_name)) { + CAM_ERR(CAM_CORE, "node name %s dev name:%s not matching", + node->name, ctx->dev_name); + return -EINVAL; + } + + if (ctx->state > CAM_CTX_UNINIT && ctx->state < CAM_CTX_STATE_MAX) { + rc = cam_context_handle_release_dev(ctx, release); + if (rc) + CAM_ERR(CAM_CORE, "context release failed for node %s", + node->name); + } else { + CAM_WARN(CAM_CORE, + "node %s context id %u state %d invalid to release hdl", + node->name, ctx->ctx_id, ctx->state); + goto destroy_dev_hdl; + } + + cam_context_putref(ctx); + +destroy_dev_hdl: + rc = cam_destroy_device_hdl(release->dev_handle); + if (rc) + CAM_ERR(CAM_CORE, "destroy device hdl failed for node %s", + node->name); + else + ctx->dev_hdl = -1; + + CAM_DBG(CAM_CORE, "[%s] Release ctx_id=%d, refcount=%d", + node->name, ctx->ctx_id, + atomic_read(&(ctx->refcount.refcount.refs))); + + return rc; +} + +static int __cam_node_handle_dump_dev(struct cam_node *node, + struct cam_dump_req_cmd *dump) +{ + int rc; + struct cam_context *ctx = NULL; + + if (!dump) + return -EINVAL; + + if (dump->dev_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid device handle for context"); + return -EINVAL; + } + + if (dump->session_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid session handle for context"); + return -EINVAL; + } + + ctx = (struct cam_context *)cam_get_device_priv(dump->dev_handle); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + dump->dev_handle); + return -EINVAL; + } + + rc = cam_context_handle_dump_dev(ctx, dump); + if (rc) + CAM_ERR(CAM_CORE, "Dump failure for node %s", node->name); + + return rc; +} + +static int __cam_node_handle_release_hw_v1(struct cam_node *node, + struct cam_release_hw_cmd_v1 *release) +{ + int rc = 0; + struct cam_context *ctx = NULL; + + if (!release) + return -EINVAL; + + if (release->dev_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid device handle for context"); + return -EINVAL; + } + + if (release->session_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid session handle for context"); + return -EINVAL; + } + + ctx = (struct cam_context *)cam_get_device_priv(release->dev_handle); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d node %s", + release->dev_handle, node->name); + return -EINVAL; + } + + if (strcmp(node->name, ctx->dev_name)) { + CAM_ERR(CAM_CORE, "node name %s dev name:%s not matching", + node->name, ctx->dev_name); + return -EINVAL; + } + + rc = cam_context_handle_release_hw(ctx, release); + if (rc) + CAM_ERR(CAM_CORE, "context release failed node %s", node->name); + + CAM_DBG(CAM_CORE, "[%s] Release ctx_id=%d, refcount=%d", + node->name, ctx->ctx_id, + atomic_read(&(ctx->refcount.refcount.refs))); + + return rc; +} + +static int __cam_node_crm_get_dev_info(struct cam_req_mgr_device_info *info) +{ + struct cam_context *ctx = NULL; + + if (!info) + return -EINVAL; + + ctx = (struct cam_context *) cam_get_device_priv(info->dev_hdl); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + info->dev_hdl); + return -EINVAL; + } + return cam_context_handle_crm_get_dev_info(ctx, info); +} + +static int __cam_node_crm_link_setup( + struct cam_req_mgr_core_dev_link_setup *setup) +{ + int rc; + struct cam_context *ctx = NULL; + + if (!setup) + return -EINVAL; + + ctx = (struct cam_context *) cam_get_device_priv(setup->dev_hdl); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + setup->dev_hdl); + return -EINVAL; + } + + if (setup->link_enable) + rc = cam_context_handle_crm_link(ctx, setup); + else + rc = cam_context_handle_crm_unlink(ctx, setup); + + return rc; +} + +static int __cam_node_crm_apply_req(struct cam_req_mgr_apply_request *apply) +{ + struct cam_context *ctx = NULL; + + if (!apply) + return -EINVAL; + + ctx = (struct cam_context *) cam_get_device_priv(apply->dev_hdl); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + apply->dev_hdl); + return -EINVAL; + } + + trace_cam_apply_req("Node", apply->request_id); + + return cam_context_handle_crm_apply_req(ctx, apply); +} + +static int __cam_node_crm_flush_req(struct cam_req_mgr_flush_request *flush) +{ + struct cam_context *ctx = NULL; + + if (!flush) { + CAM_ERR(CAM_CORE, "Invalid flush request payload"); + return -EINVAL; + } + + ctx = (struct cam_context *) cam_get_device_priv(flush->dev_hdl); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + flush->dev_hdl); + return -EINVAL; + } + + return cam_context_handle_crm_flush_req(ctx, flush); +} + +static int __cam_node_crm_process_evt( + struct cam_req_mgr_link_evt_data *evt_data) +{ + struct cam_context *ctx = NULL; + + if (!evt_data) { + CAM_ERR(CAM_CORE, "Invalid process event request payload"); + return -EINVAL; + } + + ctx = (struct cam_context *) cam_get_device_priv(evt_data->dev_hdl); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + evt_data->dev_hdl); + return -EINVAL; + } + return cam_context_handle_crm_process_evt(ctx, evt_data); +} + +static int __cam_node_crm_dump_req(struct cam_req_mgr_dump_info *dump) +{ + struct cam_context *ctx = NULL; + + if (!dump) { + CAM_ERR(CAM_CORE, "Invalid dump request payload"); + return -EINVAL; + } + + ctx = (struct cam_context *) cam_get_device_priv(dump->dev_hdl); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + dump->dev_hdl); + return -EINVAL; + } + + return cam_context_handle_crm_dump_req(ctx, dump); +} + +int cam_node_deinit(struct cam_node *node) +{ + if (node) + memset(node, 0, sizeof(*node)); + + CAM_DBG(CAM_CORE, "deinit complete"); + + return 0; +} + +int cam_node_shutdown(struct cam_node *node) +{ + int i = 0; + int rc = 0; + + if (!node) + return -EINVAL; + + for (i = 0; i < node->ctx_size; i++) { + if (node->ctx_list[i].dev_hdl > 0) { + CAM_DBG(CAM_CORE, + "Node [%s] invoking shutdown on context [%d]", + node->name, i); + rc = cam_context_shutdown(&(node->ctx_list[i])); + } + } + + if (node->hw_mgr_intf.hw_close) + node->hw_mgr_intf.hw_close(node->hw_mgr_intf.hw_mgr_priv, + NULL); + + return 0; +} + +int cam_node_init(struct cam_node *node, struct cam_hw_mgr_intf *hw_mgr_intf, + struct cam_context *ctx_list, uint32_t ctx_size, char *name) +{ + int rc = 0; + int i; + + if (!node || !hw_mgr_intf || + sizeof(node->hw_mgr_intf) != sizeof(*hw_mgr_intf)) { + return -EINVAL; + } + + memset(node, 0, sizeof(*node)); + + strlcpy(node->name, name, sizeof(node->name)); + + memcpy(&node->hw_mgr_intf, hw_mgr_intf, sizeof(node->hw_mgr_intf)); + node->crm_node_intf.apply_req = __cam_node_crm_apply_req; + node->crm_node_intf.get_dev_info = __cam_node_crm_get_dev_info; + node->crm_node_intf.link_setup = __cam_node_crm_link_setup; + node->crm_node_intf.flush_req = __cam_node_crm_flush_req; + node->crm_node_intf.process_evt = __cam_node_crm_process_evt; + node->crm_node_intf.dump_req = __cam_node_crm_dump_req; + + mutex_init(&node->list_mutex); + INIT_LIST_HEAD(&node->free_ctx_list); + node->ctx_list = ctx_list; + node->ctx_size = ctx_size; + for (i = 0; i < ctx_size; i++) { + if (!ctx_list[i].state_machine) { + CAM_ERR(CAM_CORE, + "camera context %d is not initialized", i); + rc = -1; + goto err; + } + INIT_LIST_HEAD(&ctx_list[i].list); + list_add_tail(&ctx_list[i].list, &node->free_ctx_list); + ctx_list[i].node = node; + } + + node->state = CAM_NODE_STATE_INIT; +err: + CAM_DBG(CAM_CORE, "Exit. (rc = %d)", rc); + return rc; +} + +int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) +{ + int rc = 0; + + if (!cmd) + return -EINVAL; + + CAM_DBG(CAM_CORE, "handle cmd %d", cmd->op_code); + + switch (cmd->op_code) { + case CAM_QUERY_CAP: { + struct cam_query_cap_cmd query; + + if (copy_from_user(&query, u64_to_user_ptr(cmd->handle), + sizeof(query))) { + rc = -EFAULT; + break; + } + + rc = __cam_node_handle_query_cap(node, &query); + if (rc) { + CAM_ERR(CAM_CORE, "querycap is failed(rc = %d)", + rc); + break; + } + + if (copy_to_user(u64_to_user_ptr(cmd->handle), &query, + sizeof(query))) + rc = -EFAULT; + + break; + } + case CAM_ACQUIRE_DEV: { + struct cam_acquire_dev_cmd acquire; + + if (copy_from_user(&acquire, u64_to_user_ptr(cmd->handle), + sizeof(acquire))) { + rc = -EFAULT; + break; + } + rc = __cam_node_handle_acquire_dev(node, &acquire); + if (rc) { + CAM_ERR(CAM_CORE, "acquire device failed(rc = %d)", + rc); + break; + } + if (copy_to_user(u64_to_user_ptr(cmd->handle), &acquire, + sizeof(acquire))) + rc = -EFAULT; + break; + } + case CAM_ACQUIRE_HW: { + uint32_t api_version; + void *acquire_ptr = NULL; + size_t acquire_size; + + if (copy_from_user(&api_version, (void __user *)cmd->handle, + sizeof(api_version))) { + rc = -EFAULT; + break; + } + + if (api_version == 1) { + acquire_size = sizeof(struct cam_acquire_hw_cmd_v1); + } else if (api_version == 2) { + acquire_size = sizeof(struct cam_acquire_hw_cmd_v2); + } else { + CAM_ERR(CAM_CORE, "Unsupported api version %d", + api_version); + rc = -EINVAL; + break; + } + + acquire_ptr = kzalloc(acquire_size, GFP_KERNEL); + if (!acquire_ptr) { + CAM_ERR(CAM_CORE, "No memory for acquire HW"); + rc = -ENOMEM; + break; + } + + if (copy_from_user(acquire_ptr, (void __user *)cmd->handle, + acquire_size)) { + rc = -EFAULT; + goto acquire_kfree; + } + + if (api_version == 1) { + rc = __cam_node_handle_acquire_hw_v1(node, acquire_ptr); + if (rc) { + CAM_ERR(CAM_CORE, + "acquire hw failed(rc = %d)", rc); + goto acquire_kfree; + } + } else if (api_version == 2) { + rc = __cam_node_handle_acquire_hw_v2(node, acquire_ptr); + if (rc) { + CAM_ERR(CAM_CORE, + "acquire hw failed(rc = %d)", rc); + goto acquire_kfree; + } + } + + if (copy_to_user((void __user *)cmd->handle, acquire_ptr, + acquire_size)) + rc = -EFAULT; + +acquire_kfree: + kfree(acquire_ptr); + break; + } + case CAM_START_DEV: { + struct cam_start_stop_dev_cmd start; + + if (copy_from_user(&start, u64_to_user_ptr(cmd->handle), + sizeof(start))) + rc = -EFAULT; + else { + rc = __cam_node_handle_start_dev(node, &start); + if (rc) + CAM_ERR(CAM_CORE, + "start device failed(rc = %d)", rc); + } + break; + } + case CAM_STOP_DEV: { + struct cam_start_stop_dev_cmd stop; + + if (copy_from_user(&stop, u64_to_user_ptr(cmd->handle), + sizeof(stop))) + rc = -EFAULT; + else { + rc = __cam_node_handle_stop_dev(node, &stop); + if (rc) + CAM_ERR(CAM_CORE, + "stop device failed(rc = %d)", rc); + } + break; + } + case CAM_CONFIG_DEV: { + struct cam_config_dev_cmd config; + + if (copy_from_user(&config, u64_to_user_ptr(cmd->handle), + sizeof(config))) + rc = -EFAULT; + else { + rc = __cam_node_handle_config_dev(node, &config); + if (rc) + CAM_ERR(CAM_CORE, + "config device failed(rc = %d)", rc); + } + break; + } + case CAM_RELEASE_DEV: { + struct cam_release_dev_cmd release; + + if (copy_from_user(&release, u64_to_user_ptr(cmd->handle), + sizeof(release))) + rc = -EFAULT; + else { + rc = __cam_node_handle_release_dev(node, &release); + if (rc) + CAM_ERR(CAM_CORE, + "release device failed(rc = %d)", rc); + } + break; + } + case CAM_RELEASE_HW: { + uint32_t api_version; + size_t release_size; + void *release_ptr = NULL; + + if (copy_from_user(&api_version, (void __user *)cmd->handle, + sizeof(api_version))) { + rc = -EFAULT; + break; + } + + if (api_version == 1) { + release_size = sizeof(struct cam_release_hw_cmd_v1); + } else { + CAM_ERR(CAM_CORE, "Unsupported api version %d", + api_version); + rc = -EINVAL; + break; + } + + release_ptr = kzalloc(release_size, GFP_KERNEL); + if (!release_ptr) { + CAM_ERR(CAM_CORE, "No memory for release HW"); + rc = -ENOMEM; + break; + } + + if (copy_from_user(release_ptr, (void __user *)cmd->handle, + release_size)) { + rc = -EFAULT; + goto release_kfree; + } + + if (api_version == 1) { + rc = __cam_node_handle_release_hw_v1(node, release_ptr); + if (rc) + CAM_ERR(CAM_CORE, + "release device failed(rc = %d)", rc); + } + +release_kfree: + kfree(release_ptr); + break; + } + case CAM_FLUSH_REQ: { + struct cam_flush_dev_cmd flush; + + if (copy_from_user(&flush, u64_to_user_ptr(cmd->handle), + sizeof(flush))) + rc = -EFAULT; + else { + rc = __cam_node_handle_flush_dev(node, &flush); + if (rc) + CAM_ERR(CAM_CORE, + "flush device failed(rc = %d)", rc); + } + break; + } + case CAM_DUMP_REQ: { + struct cam_dump_req_cmd dump; + + if (copy_from_user(&dump, u64_to_user_ptr(cmd->handle), + sizeof(dump))) { + rc = -EFAULT; + break; + } + rc = __cam_node_handle_dump_dev(node, &dump); + if (rc) { + CAM_ERR(CAM_CORE, + "Dump device %s failed(rc = %d) ", + node->name, rc); + break; + } + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &dump, sizeof(dump))) { + CAM_ERR(CAM_CORE, + "Dump device %s copy_to_user fail", + node->name); + rc = -EFAULT; + } + break; + } + default: + CAM_ERR(CAM_CORE, "Unknown op code %d", cmd->op_code); + rc = -EINVAL; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_core/cam_node.h b/techpack/camera-bengal/drivers/cam_core/cam_node.h new file mode 100644 index 0000000000000000000000000000000000000000..062d0213115c94fd888067f717b49de949908db0 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_core/cam_node.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_NODE_H_ +#define _CAM_NODE_H_ + +#include +#include "cam_context.h" +#include "cam_hw_mgr_intf.h" +#include "cam_req_mgr_interface.h" + + +#define CAM_NODE_STATE_UNINIT 0 +#define CAM_NODE_STATE_INIT 1 + +/** + * struct cam_node - Singleton Node for camera HW devices + * + * @name: Name for struct cam_node + * @state: Node state: + * 0 = uninitialized, 1 = initialized + * @list_mutex: Mutex for the context pool + * @free_ctx_list: Free context pool list + * @ctx_list: Context list + * @ctx_size: Context list size + * @hw_mgr_intf: Interface for cam_node to HW + * @crm_node_intf: Interface for the CRM to cam_node + * + */ +struct cam_node { + char name[CAM_CTX_DEV_NAME_MAX_LENGTH]; + uint32_t state; + + /* context pool */ + struct mutex list_mutex; + struct list_head free_ctx_list; + struct cam_context *ctx_list; + uint32_t ctx_size; + + /* interfaces */ + struct cam_hw_mgr_intf hw_mgr_intf; + struct cam_req_mgr_kmd_ops crm_node_intf; +}; + +/** + * cam_node_handle_ioctl() + * + * @brief: Handle ioctl commands + * + * @node: Node handle + * @cmd: IOCTL command + * + */ +int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd); + +/** + * cam_node_deinit() + * + * @brief: Deinitialization function for the Node interface + * + * @node: Node handle + * + */ +int cam_node_deinit(struct cam_node *node); + +/** + * cam_node_shutdown() + * + * @brief: Shutdowns/Closes the cam node. + * + * @node: Cam_node pointer + * + */ +int cam_node_shutdown(struct cam_node *node); + +/** + * cam_node_init() + * + * @brief: Initialization function for the Node interface. + * + * @node: Cam_node pointer + * @hw_mgr_intf: HW manager interface blob + * @ctx_list: List of cam_contexts to be added + * @ctx_size: Size of the cam_context + * @name: Name for the node + * + */ +int cam_node_init(struct cam_node *node, struct cam_hw_mgr_intf *hw_mgr_intf, + struct cam_context *ctx_list, uint32_t ctx_size, char *name); + +/** + * cam_node_put_ctxt_to_free_list() + * + * @brief: Put context in node free list. + * + * @ref: Context's kref object + * + */ +void cam_node_put_ctxt_to_free_list(struct kref *ref); + +#endif /* _CAM_NODE_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_core/cam_subdev.c b/techpack/camera-bengal/drivers/cam_core/cam_subdev.c new file mode 100644 index 0000000000000000000000000000000000000000..15b5fd84bbc45298cef18d0ff78e97f6cdd921fc --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_core/cam_subdev.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#include "cam_subdev.h" +#include "cam_node.h" +#include "cam_debug_util.h" + +/** + * cam_subdev_subscribe_event() + * + * @brief: function to subscribe to v4l2 events + * + * @sd: Pointer to struct v4l2_subdev. + * @fh: Pointer to struct v4l2_fh. + * @sub: Pointer to struct v4l2_event_subscription. + */ +static int cam_subdev_subscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_subscribe(fh, sub, CAM_SUBDEVICE_EVENT_MAX, NULL); +} + +/** + * cam_subdev_unsubscribe_event() + * + * @brief: function to unsubscribe from v4l2 events + * + * @sd: Pointer to struct v4l2_subdev. + * @fh: Pointer to struct v4l2_fh. + * @sub: Pointer to struct v4l2_event_subscription. + */ +static int cam_subdev_unsubscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_unsubscribe(fh, sub); +} + +static long cam_subdev_ioctl(struct v4l2_subdev *sd, unsigned int cmd, + void *arg) +{ + long rc; + struct cam_node *node = + (struct cam_node *) v4l2_get_subdevdata(sd); + + if (!node || node->state == CAM_NODE_STATE_UNINIT) { + rc = -EINVAL; + goto end; + } + + switch (cmd) { + case VIDIOC_CAM_CONTROL: + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); + rc = cam_node_handle_ioctl(node, + (struct cam_control *) arg); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); + break; + default: + CAM_ERR(CAM_CORE, "Invalid command %d for %s", cmd, + node->name); + rc = -EINVAL; + } +end: + return rc; +} + +#ifdef CONFIG_COMPAT +static long cam_subdev_compat_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + struct cam_control cmd_data; + int rc; + + if (copy_from_user(&cmd_data, (void __user *)arg, + sizeof(cmd_data))) { + CAM_ERR(CAM_CORE, "Failed to copy from user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + return -EFAULT; + } + rc = cam_subdev_ioctl(sd, cmd, &cmd_data); + if (!rc) { + if (copy_to_user((void __user *)arg, &cmd_data, + sizeof(cmd_data))) { + CAM_ERR(CAM_CORE, + "Failed to copy to user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + rc = -EFAULT; + } + } + + return rc; +} +#endif + +const struct v4l2_subdev_core_ops cam_subdev_core_ops = { + .ioctl = cam_subdev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = cam_subdev_compat_ioctl, +#endif + .subscribe_event = cam_subdev_subscribe_event, + .unsubscribe_event = cam_subdev_unsubscribe_event, +}; + +static const struct v4l2_subdev_ops cam_subdev_ops = { + .core = &cam_subdev_core_ops, +}; + +int cam_subdev_remove(struct cam_subdev *sd) +{ + if (!sd) + return -EINVAL; + + cam_unregister_subdev(sd); + cam_node_deinit((struct cam_node *)sd->token); + kfree(sd->token); + + return 0; +} + +int cam_subdev_probe(struct cam_subdev *sd, struct platform_device *pdev, + char *name, uint32_t dev_type) +{ + int rc; + struct cam_node *node = NULL; + + if (!sd || !pdev || !name) + return -EINVAL; + + node = kzalloc(sizeof(*node), GFP_KERNEL); + if (!node) + return -ENOMEM; + + /* Setup camera v4l2 subdevice */ + sd->pdev = pdev; + sd->name = name; + sd->ops = &cam_subdev_ops; + sd->token = node; + sd->sd_flags = + V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; + sd->ent_function = dev_type; + + rc = cam_register_subdev(sd); + if (rc) { + CAM_ERR(CAM_CORE, "cam_register_subdev() failed for dev: %s", + sd->name); + goto err; + } + platform_set_drvdata(sd->pdev, sd); + return rc; +err: + kfree(node); + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_cpas/Makefile b/techpack/camera-bengal/drivers/cam_cpas/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..ec2e8ad895a74f6484e176865dd2bba6959a91db --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +#ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/cpas_top +#ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/camss_top +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree) + +obj-$(CONFIG_SPECTRA_CAMERA) += cpas_top/ +obj-$(CONFIG_SPECTRA_CAMERA) += camss_top/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_cpas_soc.o cam_cpas_intf.o cam_cpas_hw.o \ No newline at end of file diff --git a/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_hw.c b/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_hw.c new file mode 100644 index 0000000000000000000000000000000000000000..c2c7f07f0734962d1ca73c51e8674ea324896cc4 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_hw.c @@ -0,0 +1,2211 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "cam_cpas_hw.h" +#include "cam_cpas_hw_intf.h" +#include "cam_cpas_soc.h" + +static uint cam_min_camnoc_ib_bw; +module_param(cam_min_camnoc_ib_bw, uint, 0644); + + +int cam_cpas_util_reg_update(struct cam_hw_info *cpas_hw, + enum cam_cpas_reg_base reg_base, struct cam_cpas_reg *reg_info) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; + uint32_t value; + int reg_base_index; + + if (reg_info->enable == false) + return 0; + + reg_base_index = cpas_core->regbase_index[reg_base]; + if (reg_base_index == -1) + return -EINVAL; + + if (reg_info->masked_value) { + value = cam_io_r_mb( + soc_info->reg_map[reg_base_index].mem_base + + reg_info->offset); + value = value & (~reg_info->mask); + value = value | (reg_info->value << reg_info->shift); + } else { + value = reg_info->value; + } + + CAM_DBG(CAM_CPAS, "Base[%d] Offset[0x%08x] Value[0x%08x]", + reg_base, reg_info->offset, value); + + cam_io_w_mb(value, soc_info->reg_map[reg_base_index].mem_base + + reg_info->offset); + + return 0; +} + +static int cam_cpas_util_vote_bus_client_level( + struct cam_cpas_bus_client *bus_client, unsigned int level) +{ + if (!bus_client->valid || (bus_client->dyn_vote == true)) { + CAM_ERR(CAM_CPAS, "Invalid params %d %d", bus_client->valid, + bus_client->dyn_vote); + return -EINVAL; + } + + if (level >= CAM_MAX_VOTE) { + CAM_ERR(CAM_CPAS, + "Invalid votelevel=%d,usecases=%d,Bus client=[%d][%s]", + level, bus_client->num_usecases, + bus_client->client_id, bus_client->name); + return -EINVAL; + } + + if (level == bus_client->curr_vote_level) + return 0; + + CAM_DBG(CAM_CPAS, "Bus client=[%d][%s] index[%d]", + bus_client->client_id, bus_client->name, level); + msm_bus_scale_client_update_request(bus_client->client_id, level); + bus_client->curr_vote_level = level; + + return 0; +} + +static int cam_cpas_util_vote_bus_client_bw( + struct cam_cpas_bus_client *bus_client, uint64_t ab, uint64_t ib, + bool camnoc_bw, uint64_t *applied_ab, uint64_t *applied_ib) +{ + struct msm_bus_paths *path; + struct msm_bus_scale_pdata *pdata; + int idx = 0; + uint64_t min_camnoc_ib_bw = CAM_CPAS_AXI_MIN_CAMNOC_IB_BW; + + if (cam_min_camnoc_ib_bw > 0) + min_camnoc_ib_bw = (uint64_t)cam_min_camnoc_ib_bw * 1000000L; + + CAM_DBG(CAM_CPAS, "cam_min_camnoc_ib_bw = %d, min_camnoc_ib_bw=%llu", + cam_min_camnoc_ib_bw, min_camnoc_ib_bw); + + if (!bus_client->valid) { + CAM_ERR(CAM_CPAS, "bus client not valid"); + return -EINVAL; + } + + if ((bus_client->num_usecases != 2) || + (bus_client->num_paths != 1) || + (bus_client->dyn_vote != true)) { + CAM_ERR(CAM_CPAS, "dynamic update not allowed %d %d %d", + bus_client->num_usecases, bus_client->num_paths, + bus_client->dyn_vote); + return -EINVAL; + } + + mutex_lock(&bus_client->lock); + + if (bus_client->curr_vote_level > 1) { + CAM_ERR(CAM_CPAS, "curr_vote_level %d cannot be greater than 1", + bus_client->curr_vote_level); + mutex_unlock(&bus_client->lock); + return -EINVAL; + } + + idx = bus_client->curr_vote_level; + idx = 1 - idx; + bus_client->curr_vote_level = idx; + mutex_unlock(&bus_client->lock); + + if (camnoc_bw == true) { + if ((ab > 0) && (ab < CAM_CPAS_AXI_MIN_CAMNOC_AB_BW)) + ab = CAM_CPAS_AXI_MIN_CAMNOC_AB_BW; + + if ((ib > 0) && (ib < min_camnoc_ib_bw)) + ib = min_camnoc_ib_bw; + } else { + if ((ab > 0) && (ab < CAM_CPAS_AXI_MIN_MNOC_AB_BW)) + ab = CAM_CPAS_AXI_MIN_MNOC_AB_BW; + + if ((ib > 0) && (ib < CAM_CPAS_AXI_MIN_MNOC_IB_BW)) + ib = CAM_CPAS_AXI_MIN_MNOC_IB_BW; + } + + pdata = bus_client->pdata; + path = &(pdata->usecase[idx]); + path->vectors[0].ab = ab; + path->vectors[0].ib = ib; + + CAM_DBG(CAM_CPAS, "Bus client=[%d][%s] :ab[%llu] ib[%llu], index[%d]", + bus_client->client_id, bus_client->name, ab, ib, idx); + msm_bus_scale_client_update_request(bus_client->client_id, idx); + if (applied_ab) + *applied_ab = ab; + if (applied_ib) + *applied_ib = ib; + + return 0; +} + +static int cam_cpas_util_register_bus_client( + struct cam_hw_soc_info *soc_info, struct device_node *dev_node, + struct cam_cpas_bus_client *bus_client) +{ + struct msm_bus_scale_pdata *pdata = NULL; + uint32_t client_id; + int rc; + + pdata = msm_bus_pdata_from_node(soc_info->pdev, + dev_node); + if (!pdata) { + CAM_ERR(CAM_CPAS, "failed get_pdata"); + return -EINVAL; + } + + if ((pdata->num_usecases == 0) || + (pdata->usecase[0].num_paths == 0)) { + CAM_ERR(CAM_CPAS, "usecase=%d", pdata->num_usecases); + rc = -EINVAL; + goto error; + } + + client_id = msm_bus_scale_register_client(pdata); + if (!client_id) { + CAM_ERR(CAM_CPAS, "failed in register ahb bus client"); + rc = -EINVAL; + goto error; + } + + bus_client->dyn_vote = of_property_read_bool(dev_node, + "qcom,msm-bus-vector-dyn-vote"); + + if (bus_client->dyn_vote && (pdata->num_usecases != 2)) { + CAM_ERR(CAM_CPAS, "Excess or less vectors %d", + pdata->num_usecases); + rc = -EINVAL; + goto fail_unregister_client; + } + + msm_bus_scale_client_update_request(client_id, 0); + + bus_client->src = pdata->usecase[0].vectors[0].src; + bus_client->dst = pdata->usecase[0].vectors[0].dst; + bus_client->pdata = pdata; + bus_client->client_id = client_id; + bus_client->num_usecases = pdata->num_usecases; + bus_client->num_paths = pdata->usecase[0].num_paths; + bus_client->curr_vote_level = 0; + bus_client->valid = true; + bus_client->name = pdata->name; + mutex_init(&bus_client->lock); + + CAM_DBG(CAM_CPAS, "Bus Client=[%d][%s] : src=%d, dst=%d", + bus_client->client_id, bus_client->name, + bus_client->src, bus_client->dst); + + return 0; +fail_unregister_client: + msm_bus_scale_unregister_client(bus_client->client_id); +error: + return rc; + +} + +static int cam_cpas_util_unregister_bus_client( + struct cam_cpas_bus_client *bus_client) +{ + if (!bus_client->valid) + return -EINVAL; + + if (bus_client->dyn_vote) + cam_cpas_util_vote_bus_client_bw(bus_client, 0, 0, false, + NULL, NULL); + else + cam_cpas_util_vote_bus_client_level(bus_client, 0); + + msm_bus_scale_unregister_client(bus_client->client_id); + bus_client->valid = false; + + mutex_destroy(&bus_client->lock); + + return 0; +} + +static int cam_cpas_util_axi_cleanup(struct cam_cpas *cpas_core, + struct cam_hw_soc_info *soc_info) +{ + int i = 0; + + if (cpas_core->num_axi_ports > CAM_CPAS_MAX_AXI_PORTS) { + CAM_ERR(CAM_CPAS, "Invalid num_axi_ports: %d", + cpas_core->num_axi_ports); + return -EINVAL; + } + + if (cpas_core->num_camnoc_axi_ports > CAM_CPAS_MAX_AXI_PORTS) { + CAM_ERR(CAM_CPAS, "Invalid num_camnoc_axi_ports: %d", + cpas_core->num_camnoc_axi_ports); + return -EINVAL; + } + + for (i = 0; i < cpas_core->num_axi_ports; i++) { + cam_cpas_util_unregister_bus_client( + &cpas_core->axi_port[i].bus_client); + of_node_put(cpas_core->axi_port[i].axi_port_node); + cpas_core->axi_port[i].axi_port_node = NULL; + } + + for (i = 0; i < cpas_core->num_camnoc_axi_ports; i++) { + cam_cpas_util_unregister_bus_client( + &cpas_core->camnoc_axi_port[i].bus_client); + of_node_put(cpas_core->camnoc_axi_port[i].axi_port_node); + cpas_core->camnoc_axi_port[i].axi_port_node = NULL; + } + + return 0; +} + +static int cam_cpas_util_axi_setup(struct cam_cpas *cpas_core, + struct cam_hw_soc_info *soc_info) +{ + int i = 0, rc = 0; + struct device_node *axi_port_mnoc_node = NULL; + struct device_node *axi_port_camnoc_node = NULL; + + if (cpas_core->num_axi_ports > CAM_CPAS_MAX_AXI_PORTS) { + CAM_ERR(CAM_CPAS, "Invalid num_axi_ports: %d", + cpas_core->num_axi_ports); + return -EINVAL; + } + + for (i = 0; i < cpas_core->num_axi_ports; i++) { + axi_port_mnoc_node = cpas_core->axi_port[i].axi_port_node; + rc = cam_cpas_util_register_bus_client(soc_info, + axi_port_mnoc_node, &cpas_core->axi_port[i].bus_client); + if (rc) + goto bus_register_fail; + } + for (i = 0; i < cpas_core->num_camnoc_axi_ports; i++) { + axi_port_camnoc_node = + cpas_core->camnoc_axi_port[i].axi_port_node; + rc = cam_cpas_util_register_bus_client(soc_info, + axi_port_camnoc_node, + &cpas_core->camnoc_axi_port[i].bus_client); + if (rc) + goto bus_register_fail; + } + + return 0; +bus_register_fail: + of_node_put(cpas_core->axi_port[i].axi_port_node); + return rc; +} + +static int cam_cpas_util_vote_default_ahb_axi(struct cam_hw_info *cpas_hw, + int enable) +{ + int rc, i = 0; + struct cam_cpas *cpas_core = (struct cam_cpas *)cpas_hw->core_info; + uint64_t ab_bw, ib_bw; + uint64_t applied_ab_bw = 0, applied_ib_bw = 0; + + rc = cam_cpas_util_vote_bus_client_level(&cpas_core->ahb_bus_client, + (enable == true) ? CAM_SVS_VOTE : CAM_SUSPEND_VOTE); + if (rc) { + CAM_ERR(CAM_CPAS, "Failed in AHB vote, enable=%d, rc=%d", + enable, rc); + return rc; + } + + if (enable) { + ab_bw = CAM_CPAS_DEFAULT_AXI_BW; + ib_bw = CAM_CPAS_DEFAULT_AXI_BW; + } else { + ab_bw = 0; + ib_bw = 0; + } + + for (i = 0; i < cpas_core->num_axi_ports; i++) { + rc = cam_cpas_util_vote_bus_client_bw( + &cpas_core->axi_port[i].bus_client, + ab_bw, ib_bw, false, &applied_ab_bw, &applied_ib_bw); + if (rc) { + CAM_ERR(CAM_CPAS, + "Failed in mnoc vote, enable=%d, rc=%d", + enable, rc); + goto remove_ahb_vote; + } + cpas_core->axi_port[i].applied_ab_bw = applied_ab_bw; + cpas_core->axi_port[i].applied_ib_bw = applied_ib_bw; + } + + return 0; +remove_ahb_vote: + cam_cpas_util_vote_bus_client_level(&cpas_core->ahb_bus_client, + CAM_SUSPEND_VOTE); + return rc; +} + +static int cam_cpas_hw_reg_write(struct cam_hw_info *cpas_hw, + uint32_t client_handle, enum cam_cpas_reg_base reg_base, + uint32_t offset, bool mb, uint32_t value) +{ + struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_client *cpas_client = NULL; + int reg_base_index = cpas_core->regbase_index[reg_base]; + uint32_t client_indx = CAM_CPAS_GET_CLIENT_IDX(client_handle); + int rc = 0; + + if (reg_base_index < 0 || reg_base_index >= soc_info->num_reg_map) { + CAM_ERR(CAM_CPAS, + "Invalid reg_base=%d, reg_base_index=%d, num_map=%d", + reg_base, reg_base_index, soc_info->num_reg_map); + return -EINVAL; + } + + if (!CAM_CPAS_CLIENT_VALID(client_indx)) + return -EINVAL; + + mutex_lock(&cpas_core->client_mutex[client_indx]); + cpas_client = cpas_core->cpas_client[client_indx]; + + if (!CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) { + CAM_ERR(CAM_CPAS, "client=[%d][%s][%d] has not started", + client_indx, cpas_client->data.identifier, + cpas_client->data.cell_index); + rc = -EPERM; + goto unlock_client; + } + + if (mb) + cam_io_w_mb(value, + soc_info->reg_map[reg_base_index].mem_base + offset); + else + cam_io_w(value, + soc_info->reg_map[reg_base_index].mem_base + offset); + +unlock_client: + mutex_unlock(&cpas_core->client_mutex[client_indx]); + return rc; +} + +static int cam_cpas_hw_reg_read(struct cam_hw_info *cpas_hw, + uint32_t client_handle, enum cam_cpas_reg_base reg_base, + uint32_t offset, bool mb, uint32_t *value) +{ + struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_client *cpas_client = NULL; + int reg_base_index = cpas_core->regbase_index[reg_base]; + uint32_t reg_value; + uint32_t client_indx = CAM_CPAS_GET_CLIENT_IDX(client_handle); + int rc = 0; + + if (!value) + return -EINVAL; + + if (reg_base_index < 0 || reg_base_index >= soc_info->num_reg_map) { + CAM_ERR(CAM_CPAS, + "Invalid reg_base=%d, reg_base_index=%d, num_map=%d", + reg_base, reg_base_index, soc_info->num_reg_map); + return -EINVAL; + } + + if (!CAM_CPAS_CLIENT_VALID(client_indx)) + return -EINVAL; + + cpas_client = cpas_core->cpas_client[client_indx]; + + if (!CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) { + CAM_ERR(CAM_CPAS, "client=[%d][%s][%d] has not started", + client_indx, cpas_client->data.identifier, + cpas_client->data.cell_index); + return -EPERM; + } + + if (mb) + reg_value = cam_io_r_mb( + soc_info->reg_map[reg_base_index].mem_base + offset); + else + reg_value = cam_io_r( + soc_info->reg_map[reg_base_index].mem_base + offset); + + *value = reg_value; + + return rc; +} + +static int cam_cpas_util_set_camnoc_axi_clk_rate( + struct cam_hw_info *cpas_hw) +{ + struct cam_cpas_private_soc *soc_private = + (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private; + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_tree_node *tree_node = NULL; + int rc = 0, i = 0; + + CAM_DBG(CAM_CPAS, "control_camnoc_axi_clk=%d", + soc_private->control_camnoc_axi_clk); + + if (soc_private->control_camnoc_axi_clk) { + struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; + uint64_t required_camnoc_bw = 0, intermediate_result = 0; + int64_t clk_rate = 0; + + for (i = 0; i < CAM_CPAS_MAX_TREE_NODES; i++) { + tree_node = soc_private->tree_node[i]; + if (!tree_node || + !tree_node->camnoc_max_needed) + continue; + + if (required_camnoc_bw < (tree_node->camnoc_bw * + tree_node->bus_width_factor)) { + required_camnoc_bw = tree_node->camnoc_bw * + tree_node->bus_width_factor; + } + } + + intermediate_result = required_camnoc_bw * + soc_private->camnoc_axi_clk_bw_margin; + do_div(intermediate_result, 100); + required_camnoc_bw += intermediate_result; + + if ((required_camnoc_bw > 0) && + (required_camnoc_bw < + soc_private->camnoc_axi_min_ib_bw)) + required_camnoc_bw = soc_private->camnoc_axi_min_ib_bw; + + intermediate_result = required_camnoc_bw; + do_div(intermediate_result, soc_private->camnoc_bus_width); + clk_rate = intermediate_result; + + CAM_DBG(CAM_CPAS, "Setting camnoc axi clk rate : %llu %lld", + required_camnoc_bw, clk_rate); + + /* + * CPAS hw is not powered on for the first client. + * Also, clk_rate will be overwritten with default + * value while power on. So, skipping this for first + * client. + */ + if (cpas_core->streamon_clients) { + rc = cam_soc_util_set_src_clk_rate(soc_info, clk_rate); + if (rc) + CAM_ERR(CAM_CPAS, + "Failed in setting camnoc axi clk %llu %lld %d", + required_camnoc_bw, clk_rate, rc); + + cpas_core->applied_camnoc_axi_rate = clk_rate; + } + } + + return rc; +} + +static int cam_cpas_util_translate_client_paths( + struct cam_axi_vote *axi_vote) +{ + int i; + uint32_t *path_data_type = NULL; + + if (!axi_vote) + return -EINVAL; + + for (i = 0; i < axi_vote->num_paths; i++) { + path_data_type = &axi_vote->axi_path[i].path_data_type; + /* Update path_data_type from UAPI value to internal value */ + if (*path_data_type >= CAM_CPAS_PATH_DATA_CONSO_OFFSET) + *path_data_type = CAM_CPAS_MAX_GRAN_PATHS_PER_CLIENT + + (*path_data_type % + CAM_CPAS_MAX_GRAN_PATHS_PER_CLIENT); + else + *path_data_type %= CAM_CPAS_MAX_GRAN_PATHS_PER_CLIENT; + + if (*path_data_type >= CAM_CPAS_PATH_DATA_MAX) { + CAM_ERR(CAM_CPAS, "index Invalid: %d", path_data_type); + return -EINVAL; + } + } + + return 0; +} + +static int cam_cpas_axi_consolidate_path_votes( + struct cam_cpas_client *cpas_client, + struct cam_axi_vote *axi_vote) +{ + int rc = 0, i, k, l; + struct cam_axi_vote *con_axi_vote = &cpas_client->axi_vote; + bool path_found = false, cons_entry_found; + struct cam_cpas_tree_node *curr_tree_node = NULL; + struct cam_cpas_tree_node *sum_tree_node = NULL; + uint32_t transac_type; + uint32_t path_data_type; + struct cam_axi_per_path_bw_vote *axi_path; + + con_axi_vote->num_paths = 0; + + for (i = 0; i < axi_vote->num_paths; i++) { + path_found = false; + path_data_type = axi_vote->axi_path[i].path_data_type; + transac_type = axi_vote->axi_path[i].transac_type; + + if ((path_data_type >= CAM_CPAS_PATH_DATA_MAX) || + (transac_type >= CAM_CPAS_TRANSACTION_MAX)) { + CAM_ERR(CAM_CPAS, "Invalid path or transac type: %d %d", + path_data_type, transac_type); + return -EINVAL; + } + + axi_path = &con_axi_vote->axi_path[con_axi_vote->num_paths]; + + curr_tree_node = + cpas_client->tree_node[path_data_type][transac_type]; + if (curr_tree_node) { + path_found = true; + memcpy(axi_path, &axi_vote->axi_path[i], + sizeof(struct cam_axi_per_path_bw_vote)); + con_axi_vote->num_paths++; + continue; + } + + for (k = 0; k < CAM_CPAS_PATH_DATA_MAX; k++) { + sum_tree_node = cpas_client->tree_node[k][transac_type]; + + if (!sum_tree_node) + continue; + + if (sum_tree_node->constituent_paths[path_data_type]) { + path_found = true; + /* + * Check if corresponding consolidated path + * entry is already added into consolidated list + */ + cons_entry_found = false; + for (l = 0; l < con_axi_vote->num_paths; l++) { + if ((con_axi_vote->axi_path[l] + .path_data_type == k) && + (con_axi_vote->axi_path[l] + .transac_type == transac_type)) { + cons_entry_found = true; + con_axi_vote->axi_path[l] + .camnoc_bw += + axi_vote->axi_path[i] + .camnoc_bw; + + con_axi_vote->axi_path[l] + .mnoc_ab_bw += + axi_vote->axi_path[i] + .mnoc_ab_bw; + + con_axi_vote->axi_path[l] + .mnoc_ib_bw += + axi_vote->axi_path[i] + .mnoc_ib_bw; + break; + } + } + + /* If not found, add a new entry */ + if (!cons_entry_found) { + axi_path->path_data_type = k; + axi_path->transac_type = transac_type; + axi_path->camnoc_bw = + axi_vote->axi_path[i].camnoc_bw; + axi_path->mnoc_ab_bw = + axi_vote->axi_path[i].mnoc_ab_bw; + axi_path->mnoc_ib_bw = + axi_vote->axi_path[i].mnoc_ib_bw; + con_axi_vote->num_paths++; + } + break; + } + } + + if (!path_found) { + CAM_ERR(CAM_CPAS, + "Client [%s][%d] Consolidated path not found for path=%d, transac=%d", + cpas_client->data.identifier, + cpas_client->data.cell_index, + path_data_type, transac_type); + return -EINVAL; + } + } + + return rc; +} + +static int cam_cpas_update_axi_vote_bw( + struct cam_hw_info *cpas_hw, + struct cam_cpas_tree_node *cpas_tree_node, + bool *mnoc_axi_port_updated, + bool *camnoc_axi_port_updated) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_private_soc *soc_private = + (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private; + + if (cpas_tree_node->axi_port_idx >= CAM_CPAS_MAX_AXI_PORTS) { + CAM_ERR(CAM_CPAS, "Invalid axi_port_idx: %d", + cpas_tree_node->axi_port_idx); + return -EINVAL; + } + + cpas_core->axi_port[cpas_tree_node->axi_port_idx].ab_bw = + cpas_tree_node->mnoc_ab_bw; + cpas_core->axi_port[cpas_tree_node->axi_port_idx].ib_bw = + cpas_tree_node->mnoc_ib_bw; + mnoc_axi_port_updated[cpas_tree_node->axi_port_idx] = true; + + if (soc_private->control_camnoc_axi_clk) + return 0; + + cpas_core->camnoc_axi_port[cpas_tree_node->axi_port_idx].camnoc_bw = + cpas_tree_node->camnoc_bw; + camnoc_axi_port_updated[cpas_tree_node->camnoc_axi_port_idx] = true; + return 0; +} + +static int cam_cpas_camnoc_set_vote_axi_clk_rate( + struct cam_hw_info *cpas_hw, + bool *camnoc_axi_port_updated) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_private_soc *soc_private = + (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private; + int i; + int rc = 0; + struct cam_cpas_axi_port *camnoc_axi_port = NULL; + uint64_t camnoc_bw; + uint64_t applied_ab = 0, applied_ib = 0; + + if (soc_private->control_camnoc_axi_clk) { + rc = cam_cpas_util_set_camnoc_axi_clk_rate(cpas_hw); + if (rc) + CAM_ERR(CAM_CPAS, + "Failed in setting axi clk rate rc=%d", rc); + return rc; + } + + /* Below code is executed if we just vote and do not set the clk rate + * for camnoc + */ + + if (cpas_core->num_camnoc_axi_ports > CAM_CPAS_MAX_AXI_PORTS) { + CAM_ERR(CAM_CPAS, "Invalid num_camnoc_axi_ports: %d", + cpas_core->num_camnoc_axi_ports); + return -EINVAL; + } + + for (i = 0; i < cpas_core->num_camnoc_axi_ports; i++) { + if (camnoc_axi_port_updated[i]) + camnoc_axi_port = &cpas_core->camnoc_axi_port[i]; + else + continue; + + CAM_DBG(CAM_PERF, "Port[%s] : camnoc_bw=%lld", + camnoc_axi_port->axi_port_name, + camnoc_axi_port->camnoc_bw); + + if (camnoc_axi_port->camnoc_bw) + camnoc_bw = camnoc_axi_port->camnoc_bw; + else + camnoc_bw = camnoc_axi_port->additional_bw; + + rc = cam_cpas_util_vote_bus_client_bw( + &camnoc_axi_port->bus_client, + 0, camnoc_bw, true, &applied_ab, &applied_ib); + + CAM_DBG(CAM_CPAS, + "camnoc vote camnoc_bw[%llu] rc=%d %s", + camnoc_bw, rc, camnoc_axi_port->axi_port_name); + if (rc) { + CAM_ERR(CAM_CPAS, + "Failed in camnoc vote camnoc_bw[%llu] rc=%d", + camnoc_bw, rc); + break; + } + camnoc_axi_port->applied_ab_bw = applied_ab; + camnoc_axi_port->applied_ib_bw = applied_ib; + } + return rc; +} + +static int cam_cpas_util_apply_client_axi_vote( + struct cam_hw_info *cpas_hw, + struct cam_cpas_client *cpas_client, + struct cam_axi_vote *axi_vote) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_axi_vote *con_axi_vote = NULL; + struct cam_cpas_axi_port *mnoc_axi_port = NULL; + struct cam_cpas_tree_node *curr_tree_node = NULL; + struct cam_cpas_tree_node *par_tree_node = NULL; + uint32_t transac_type; + uint32_t path_data_type; + bool mnoc_axi_port_updated[CAM_CPAS_MAX_AXI_PORTS] = {false}; + bool camnoc_axi_port_updated[CAM_CPAS_MAX_AXI_PORTS] = {false}; + uint64_t mnoc_ab_bw = 0, mnoc_ib_bw = 0, + curr_camnoc_old = 0, curr_mnoc_ab_old = 0, curr_mnoc_ib_old = 0, + par_camnoc_old = 0, par_mnoc_ab_old = 0, par_mnoc_ib_old = 0; + int rc = 0, i = 0; + uint64_t applied_ab = 0, applied_ib = 0; + + mutex_lock(&cpas_core->tree_lock); + if (!cpas_client->tree_node_valid) { + /* + * This is by assuming apply_client_axi_vote is called + * for these clients from only cpas_start, cpas_stop. + * not called from hw_update_axi_vote + */ + for (i = 0; i < cpas_core->num_axi_ports; i++) { + if (axi_vote->axi_path[0].mnoc_ab_bw) { + /* start case */ + cpas_core->axi_port[i].additional_bw += + CAM_CPAS_DEFAULT_AXI_BW; + } else { + /* stop case */ + cpas_core->axi_port[i].additional_bw -= + CAM_CPAS_DEFAULT_AXI_BW; + } + mnoc_axi_port_updated[i] = true; + } + goto vote_start_clients; + } + + rc = cam_cpas_axi_consolidate_path_votes(cpas_client, axi_vote); + if (rc) { + CAM_ERR(CAM_PERF, "Failed in bw consolidation, Client [%s][%d]", + cpas_client->data.identifier, + cpas_client->data.cell_index); + goto unlock_tree; + } + + con_axi_vote = &cpas_client->axi_vote; + + cam_cpas_dump_axi_vote_info(cpas_client, "Consolidated Vote", + con_axi_vote); + + /* Traverse through node tree and update bw vote values */ + for (i = 0; i < con_axi_vote->num_paths; i++) { + path_data_type = + con_axi_vote->axi_path[i].path_data_type; + transac_type = + con_axi_vote->axi_path[i].transac_type; + curr_tree_node = cpas_client->tree_node[path_data_type] + [transac_type]; + + if (con_axi_vote->axi_path[i].mnoc_ab_bw == 0) + con_axi_vote->axi_path[i].mnoc_ab_bw = + con_axi_vote->axi_path[i].camnoc_bw; + + if (con_axi_vote->axi_path[i].camnoc_bw == 0) + con_axi_vote->axi_path[i].camnoc_bw = + con_axi_vote->axi_path[i].mnoc_ab_bw; + + if ((curr_tree_node->camnoc_bw == + con_axi_vote->axi_path[i].camnoc_bw) && + (curr_tree_node->mnoc_ab_bw == + con_axi_vote->axi_path[i].mnoc_ab_bw) && + (curr_tree_node->mnoc_ib_bw == + con_axi_vote->axi_path[i].mnoc_ib_bw)) + continue; + + curr_camnoc_old = curr_tree_node->camnoc_bw; + curr_mnoc_ab_old = curr_tree_node->mnoc_ab_bw; + curr_mnoc_ib_old = curr_tree_node->mnoc_ib_bw; + curr_tree_node->camnoc_bw = + con_axi_vote->axi_path[i].camnoc_bw; + curr_tree_node->mnoc_ab_bw = + con_axi_vote->axi_path[i].mnoc_ab_bw; + curr_tree_node->mnoc_ib_bw = + con_axi_vote->axi_path[i].mnoc_ib_bw; + + while (curr_tree_node->parent_node) { + par_tree_node = curr_tree_node->parent_node; + par_camnoc_old = par_tree_node->camnoc_bw; + par_mnoc_ab_old = par_tree_node->mnoc_ab_bw; + par_mnoc_ib_old = par_tree_node->mnoc_ib_bw; + par_tree_node->mnoc_ab_bw -= curr_mnoc_ab_old; + par_tree_node->mnoc_ab_bw += curr_tree_node->mnoc_ab_bw; + par_tree_node->mnoc_ib_bw -= curr_mnoc_ib_old; + par_tree_node->mnoc_ib_bw += curr_tree_node->mnoc_ib_bw; + + if (par_tree_node->merge_type == + CAM_CPAS_TRAFFIC_MERGE_SUM) { + par_tree_node->camnoc_bw -= + curr_camnoc_old; + par_tree_node->camnoc_bw += + curr_tree_node->camnoc_bw; + } else if (par_tree_node->merge_type == + CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE) { + par_tree_node->camnoc_bw -= + (curr_camnoc_old / 2); + par_tree_node->camnoc_bw += + (curr_tree_node->camnoc_bw / 2); + } else { + CAM_ERR(CAM_CPAS, "Invalid Merge type"); + rc = -EINVAL; + goto unlock_tree; + } + + if (!par_tree_node->parent_node) { + if ((par_tree_node->axi_port_idx < 0) || + (par_tree_node->axi_port_idx >= + CAM_CPAS_MAX_AXI_PORTS)) { + CAM_ERR(CAM_CPAS, + "AXI port index invalid"); + rc = -EINVAL; + goto unlock_tree; + } + rc = cam_cpas_update_axi_vote_bw(cpas_hw, + par_tree_node, + mnoc_axi_port_updated, + camnoc_axi_port_updated); + if (rc) { + CAM_ERR(CAM_CPAS, + "Update Vote failed"); + goto unlock_tree; + } + } + + curr_tree_node = par_tree_node; + curr_camnoc_old = par_camnoc_old; + curr_mnoc_ab_old = par_mnoc_ab_old; + curr_mnoc_ib_old = par_mnoc_ib_old; + } + } + + if (!par_tree_node) { + CAM_DBG(CAM_CPAS, "No change in BW for all paths"); + rc = 0; + goto unlock_tree; + } + +vote_start_clients: + for (i = 0; i < cpas_core->num_axi_ports; i++) { + if (mnoc_axi_port_updated[i]) + mnoc_axi_port = &cpas_core->axi_port[i]; + else + continue; + + CAM_DBG(CAM_PERF, "Port[%s] : ab=%lld ib=%lld additional=%lld", + mnoc_axi_port->axi_port_name, mnoc_axi_port->ab_bw, + mnoc_axi_port->ib_bw, mnoc_axi_port->additional_bw); + + if (mnoc_axi_port->ab_bw) + mnoc_ab_bw = mnoc_axi_port->ab_bw; + else + mnoc_ab_bw = mnoc_axi_port->additional_bw; + + if (cpas_core->axi_port[i].ib_bw_voting_needed) + mnoc_ib_bw = mnoc_axi_port->ib_bw; + else + mnoc_ib_bw = 0; + + rc = cam_cpas_util_vote_bus_client_bw( + &mnoc_axi_port->bus_client, + mnoc_ab_bw, mnoc_ib_bw, false, &applied_ab, + &applied_ib); + if (rc) { + CAM_ERR(CAM_CPAS, + "Failed in mnoc vote ab[%llu] ib[%llu] rc=%d", + mnoc_ab_bw, mnoc_ib_bw, rc); + goto unlock_tree; + } + mnoc_axi_port->applied_ab_bw = applied_ab; + mnoc_axi_port->applied_ib_bw = applied_ib; + } + rc = cam_cpas_camnoc_set_vote_axi_clk_rate( + cpas_hw, camnoc_axi_port_updated); + if (rc) + CAM_ERR(CAM_CPAS, "Failed in setting axi clk rate rc=%d", rc); + +unlock_tree: + mutex_unlock(&cpas_core->tree_lock); + return rc; +} + +static int cam_cpas_util_apply_default_axi_vote( + struct cam_hw_info *cpas_hw, bool enable) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_axi_port *axi_port = NULL; + uint64_t mnoc_ab_bw = 0, mnoc_ib_bw = 0; + uint64_t applied_ab_bw = 0, applied_ib_bw = 0; + int rc = 0, i = 0; + + mutex_lock(&cpas_core->tree_lock); + for (i = 0; i < cpas_core->num_axi_ports; i++) { + if (!cpas_core->axi_port[i].ab_bw || + !cpas_core->axi_port[i].ib_bw) + axi_port = &cpas_core->axi_port[i]; + else + continue; + + if (enable) + mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW; + else + mnoc_ib_bw = 0; + + CAM_DBG(CAM_CPAS, "Port=[%s] :ab[%llu] ib[%llu]", + axi_port->axi_port_name, mnoc_ab_bw, mnoc_ib_bw); + + rc = cam_cpas_util_vote_bus_client_bw(&axi_port->bus_client, + mnoc_ab_bw, mnoc_ib_bw, false, &applied_ab_bw, + &applied_ib_bw); + if (rc) { + CAM_ERR(CAM_CPAS, + "Failed in mnoc vote ab[%llu] ib[%llu] rc=%d", + mnoc_ab_bw, mnoc_ib_bw, rc); + goto unlock_tree; + } + cpas_core->axi_port[i].applied_ab_bw = applied_ab_bw; + cpas_core->axi_port[i].applied_ib_bw = applied_ib_bw; + } + +unlock_tree: + mutex_unlock(&cpas_core->tree_lock); + return rc; +} + +static int cam_cpas_hw_update_axi_vote(struct cam_hw_info *cpas_hw, + uint32_t client_handle, struct cam_axi_vote *client_axi_vote) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_client *cpas_client = NULL; + struct cam_axi_vote *axi_vote = NULL; + uint32_t client_indx = CAM_CPAS_GET_CLIENT_IDX(client_handle); + int rc = 0; + + if (!client_axi_vote) { + CAM_ERR(CAM_CPAS, "Invalid arg, client_handle=%d", + client_handle); + return -EINVAL; + } + + if (!CAM_CPAS_CLIENT_VALID(client_indx)) + return -EINVAL; + + mutex_lock(&cpas_hw->hw_mutex); + mutex_lock(&cpas_core->client_mutex[client_indx]); + + axi_vote = kmemdup(client_axi_vote, sizeof(struct cam_axi_vote), + GFP_KERNEL); + if (!axi_vote) { + CAM_ERR(CAM_CPAS, "Out of memory"); + mutex_unlock(&cpas_core->client_mutex[client_indx]); + mutex_unlock(&cpas_hw->hw_mutex); + return -ENOMEM; + } + + cam_cpas_dump_axi_vote_info(cpas_core->cpas_client[client_indx], + "Incoming Vote", axi_vote); + + cpas_client = cpas_core->cpas_client[client_indx]; + + if (!CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) { + CAM_ERR(CAM_CPAS, "client=[%d][%s][%d] has not started", + client_indx, cpas_client->data.identifier, + cpas_client->data.cell_index); + rc = -EPERM; + goto unlock_client; + } + + rc = cam_cpas_util_translate_client_paths(axi_vote); + if (rc) { + CAM_ERR(CAM_CPAS, + "Unable to translate per path votes rc: %d", rc); + goto unlock_client; + } + + cam_cpas_dump_axi_vote_info(cpas_core->cpas_client[client_indx], + "Translated Vote", axi_vote); + + rc = cam_cpas_util_apply_client_axi_vote(cpas_hw, + cpas_core->cpas_client[client_indx], axi_vote); + +unlock_client: + kzfree(axi_vote); + axi_vote = NULL; + mutex_unlock(&cpas_core->client_mutex[client_indx]); + mutex_unlock(&cpas_hw->hw_mutex); + return rc; +} + +static int cam_cpas_util_get_ahb_level(struct cam_hw_info *cpas_hw, + struct device *dev, unsigned long freq, enum cam_vote_level *req_level) +{ + struct cam_cpas_private_soc *soc_private = + (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private; + struct dev_pm_opp *opp; + unsigned int corner; + enum cam_vote_level level = CAM_SVS_VOTE; + unsigned long corner_freq = freq; + int i; + + if (!dev || !req_level) { + CAM_ERR(CAM_CPAS, "Invalid params %pK, %pK", dev, req_level); + return -EINVAL; + } + + opp = dev_pm_opp_find_freq_ceil(dev, &corner_freq); + if (IS_ERR(opp)) { + CAM_DBG(CAM_CPAS, "OPP Ceil not available for freq :%ld, %pK", + corner_freq, opp); + *req_level = CAM_TURBO_VOTE; + return 0; + } + + corner = dev_pm_opp_get_voltage(opp); + + for (i = 0; i < soc_private->num_vdd_ahb_mapping; i++) + if (corner == soc_private->vdd_ahb[i].vdd_corner) + level = soc_private->vdd_ahb[i].ahb_level; + + CAM_DBG(CAM_CPAS, + "From OPP table : freq=[%ld][%ld], corner=%d, level=%d", + freq, corner_freq, corner, level); + + *req_level = level; + + return 0; +} + +static int cam_cpas_util_apply_client_ahb_vote(struct cam_hw_info *cpas_hw, + struct cam_cpas_client *cpas_client, struct cam_ahb_vote *ahb_vote, + enum cam_vote_level *applied_level) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_bus_client *ahb_bus_client = &cpas_core->ahb_bus_client; + enum cam_vote_level required_level; + enum cam_vote_level highest_level; + int i, rc = 0; + + if (!ahb_bus_client->valid) { + CAM_ERR(CAM_CPAS, "AHB Bus client not valid"); + return -EINVAL; + } + + if (ahb_vote->type == CAM_VOTE_DYNAMIC) { + rc = cam_cpas_util_get_ahb_level(cpas_hw, cpas_client->data.dev, + ahb_vote->vote.freq, &required_level); + if (rc) + return rc; + } else { + required_level = ahb_vote->vote.level; + } + + if (cpas_client->ahb_level == required_level) + return 0; + + mutex_lock(&ahb_bus_client->lock); + cpas_client->ahb_level = required_level; + + CAM_DBG(CAM_CPAS, "Client=[%d][%s] required level[%d], curr_level[%d]", + ahb_bus_client->client_id, ahb_bus_client->name, + required_level, ahb_bus_client->curr_vote_level); + + if (required_level == ahb_bus_client->curr_vote_level) + goto unlock_bus_client; + + highest_level = required_level; + for (i = 0; i < cpas_core->num_clients; i++) { + if (cpas_core->cpas_client[i] && (highest_level < + cpas_core->cpas_client[i]->ahb_level)) + highest_level = cpas_core->cpas_client[i]->ahb_level; + } + + CAM_DBG(CAM_CPAS, "Required highest_level[%d]", highest_level); + + if (!cpas_core->ahb_bus_scaling_disable) { + rc = cam_cpas_util_vote_bus_client_level(ahb_bus_client, + highest_level); + if (rc) { + CAM_ERR(CAM_CPAS, "Failed in ahb vote, level=%d, rc=%d", + highest_level, rc); + goto unlock_bus_client; + } + } + + rc = cam_soc_util_set_clk_rate_level(&cpas_hw->soc_info, highest_level); + if (rc) { + CAM_ERR(CAM_CPAS, + "Failed in scaling clock rate level %d for AHB", + highest_level); + goto unlock_bus_client; + } + + if (applied_level) + *applied_level = highest_level; + +unlock_bus_client: + mutex_unlock(&ahb_bus_client->lock); + return rc; +} + +static int cam_cpas_hw_update_ahb_vote(struct cam_hw_info *cpas_hw, + uint32_t client_handle, struct cam_ahb_vote *client_ahb_vote) +{ + struct cam_ahb_vote ahb_vote; + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_client *cpas_client = NULL; + uint32_t client_indx = CAM_CPAS_GET_CLIENT_IDX(client_handle); + int rc = 0; + + if (!client_ahb_vote) { + CAM_ERR(CAM_CPAS, "Invalid input arg"); + return -EINVAL; + } + + ahb_vote = *client_ahb_vote; + + if (ahb_vote.vote.level == 0) { + CAM_DBG(CAM_CPAS, "0 ahb vote from client %d", + client_handle); + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_SVS_VOTE; + } + + if (!CAM_CPAS_CLIENT_VALID(client_indx)) + return -EINVAL; + + mutex_lock(&cpas_hw->hw_mutex); + mutex_lock(&cpas_core->client_mutex[client_indx]); + cpas_client = cpas_core->cpas_client[client_indx]; + + if (!CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) { + CAM_ERR(CAM_CPAS, "client=[%d][%s][%d] has not started", + client_indx, cpas_client->data.identifier, + cpas_client->data.cell_index); + rc = -EPERM; + goto unlock_client; + } + + CAM_DBG(CAM_PERF, + "client=[%d][%s][%d] : type[%d], level[%d], freq[%ld], applied[%d]", + client_indx, cpas_client->data.identifier, + cpas_client->data.cell_index, ahb_vote.type, + ahb_vote.vote.level, ahb_vote.vote.freq, + cpas_core->cpas_client[client_indx]->ahb_level); + + rc = cam_cpas_util_apply_client_ahb_vote(cpas_hw, + cpas_core->cpas_client[client_indx], &ahb_vote, NULL); + +unlock_client: + mutex_unlock(&cpas_core->client_mutex[client_indx]); + mutex_unlock(&cpas_hw->hw_mutex); + return rc; +} + +static int cam_cpas_util_create_vote_all_paths( + struct cam_cpas_client *cpas_client, + struct cam_axi_vote *axi_vote) +{ + int i, j; + uint64_t camnoc_bw, mnoc_ab_bw, mnoc_ib_bw; + struct cam_axi_per_path_bw_vote *axi_path; + + if (!cpas_client || !axi_vote) + return -EINVAL; + + camnoc_bw = axi_vote->axi_path[0].camnoc_bw; + mnoc_ab_bw = axi_vote->axi_path[0].mnoc_ab_bw; + mnoc_ib_bw = axi_vote->axi_path[0].mnoc_ib_bw; + + axi_vote->num_paths = 0; + + for (i = 0; i < CAM_CPAS_TRANSACTION_MAX; i++) { + for (j = 0; j < CAM_CPAS_PATH_DATA_MAX; j++) { + if (cpas_client->tree_node[j][i]) { + axi_path = + &axi_vote->axi_path[axi_vote->num_paths]; + + axi_path->path_data_type = j; + axi_path->transac_type = i; + axi_path->camnoc_bw = camnoc_bw; + axi_path->mnoc_ab_bw = mnoc_ab_bw; + axi_path->mnoc_ib_bw = mnoc_ib_bw; + + axi_vote->num_paths++; + } + } + } + + return 0; +} + +static int cam_cpas_hw_start(void *hw_priv, void *start_args, + uint32_t arg_size) +{ + struct cam_hw_info *cpas_hw; + struct cam_cpas *cpas_core; + uint32_t client_indx; + struct cam_cpas_hw_cmd_start *cmd_hw_start; + struct cam_cpas_client *cpas_client; + struct cam_ahb_vote *ahb_vote; + struct cam_ahb_vote remove_ahb; + struct cam_axi_vote axi_vote = {0}; + enum cam_vote_level applied_level = CAM_SVS_VOTE; + int rc, rc_eh, i = 0; + struct cam_cpas_private_soc *soc_private = NULL; + bool invalid_start = true; + + if (!hw_priv || !start_args) { + CAM_ERR(CAM_CPAS, "Invalid arguments %pK %pK", + hw_priv, start_args); + return -EINVAL; + } + + if (sizeof(struct cam_cpas_hw_cmd_start) != arg_size) { + CAM_ERR(CAM_CPAS, "HW_CAPS size mismatch %zd %d", + sizeof(struct cam_cpas_hw_cmd_start), arg_size); + return -EINVAL; + } + + cpas_hw = (struct cam_hw_info *)hw_priv; + cpas_core = (struct cam_cpas *) cpas_hw->core_info; + soc_private = (struct cam_cpas_private_soc *) + cpas_hw->soc_info.soc_private; + cmd_hw_start = (struct cam_cpas_hw_cmd_start *)start_args; + client_indx = CAM_CPAS_GET_CLIENT_IDX(cmd_hw_start->client_handle); + ahb_vote = cmd_hw_start->ahb_vote; + + if (!ahb_vote || !cmd_hw_start->axi_vote) + return -EINVAL; + + if (!ahb_vote->vote.level) { + CAM_ERR(CAM_CPAS, "Invalid vote ahb[%d]", + ahb_vote->vote.level); + return -EINVAL; + } + + memcpy(&axi_vote, cmd_hw_start->axi_vote, sizeof(struct cam_axi_vote)); + for (i = 0; i < axi_vote.num_paths; i++) { + if ((axi_vote.axi_path[i].camnoc_bw != 0) || + (axi_vote.axi_path[i].mnoc_ab_bw != 0) || + (axi_vote.axi_path[i].mnoc_ib_bw != 0)) { + invalid_start = false; + break; + } + } + + if (invalid_start) { + CAM_ERR(CAM_CPAS, "Zero start vote"); + return -EINVAL; + } + + if (!CAM_CPAS_CLIENT_VALID(client_indx)) + return -EINVAL; + + mutex_lock(&cpas_hw->hw_mutex); + mutex_lock(&cpas_core->client_mutex[client_indx]); + cpas_client = cpas_core->cpas_client[client_indx]; + + if (!CAM_CPAS_CLIENT_REGISTERED(cpas_core, client_indx)) { + CAM_ERR(CAM_CPAS, "client=[%d] is not registered", + client_indx); + rc = -EPERM; + goto error; + } + + if (CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) { + CAM_ERR(CAM_CPAS, "client=[%d][%s][%d] is in start state", + client_indx, cpas_client->data.identifier, + cpas_client->data.cell_index); + rc = -EPERM; + goto error; + } + + CAM_DBG(CAM_CPAS, + "AHB :client=[%d][%s][%d] type[%d], level[%d], applied[%d]", + client_indx, cpas_client->data.identifier, + cpas_client->data.cell_index, + ahb_vote->type, ahb_vote->vote.level, cpas_client->ahb_level); + rc = cam_cpas_util_apply_client_ahb_vote(cpas_hw, cpas_client, + ahb_vote, &applied_level); + if (rc) + goto error; + + cam_cpas_dump_axi_vote_info(cpas_client, "CPAS Start Vote", + &axi_vote); + + /* + * If client has indicated start bw to be applied on all paths + * of client, apply that otherwise apply whatever the client supplies + * for specific paths + */ + if (axi_vote.axi_path[0].path_data_type == + CAM_CPAS_API_PATH_DATA_STD_START) { + rc = cam_cpas_util_create_vote_all_paths(cpas_client, + &axi_vote); + } else { + rc = cam_cpas_util_translate_client_paths(&axi_vote); + } + + if (rc) { + CAM_ERR(CAM_CPAS, "Unable to create or translate paths rc: %d", + rc); + goto remove_ahb_vote; + } + + cam_cpas_dump_axi_vote_info(cpas_client, "CPAS Start Translated Vote", + &axi_vote); + + rc = cam_cpas_util_apply_client_axi_vote(cpas_hw, + cpas_client, &axi_vote); + if (rc) + goto remove_ahb_vote; + + if ((soc_private->cx_ipeak_gpu_limit) && + (!cpas_core->streamon_clients)) { + soc_private->gpu_pwr_limit = + kgsl_pwr_limits_add(KGSL_DEVICE_3D0); + if (soc_private->gpu_pwr_limit) { + rc = kgsl_pwr_limits_set_gpu_fmax( + soc_private->gpu_pwr_limit, + soc_private->cx_ipeak_gpu_limit); + if (rc) { + kgsl_pwr_limits_del( + soc_private->gpu_pwr_limit); + soc_private->gpu_pwr_limit = NULL; + CAM_ERR(CAM_CPAS, + "set cx_ipeak_gpu_limit failed, rc %d", + rc); + goto remove_axi_vote; + } + } + } + + if (cpas_core->streamon_clients == 0) { + rc = cam_cpas_util_apply_default_axi_vote(cpas_hw, true); + if (rc) + goto remove_axi_vote; + + atomic_set(&cpas_core->irq_count, 1); + rc = cam_cpas_soc_enable_resources(&cpas_hw->soc_info, + applied_level); + if (rc) { + atomic_set(&cpas_core->irq_count, 0); + CAM_ERR(CAM_CPAS, "enable_resorce failed, rc=%d", rc); + goto remove_axi_vote; + } + + if (cpas_core->internal_ops.power_on) { + rc = cpas_core->internal_ops.power_on(cpas_hw); + if (rc) { + atomic_set(&cpas_core->irq_count, 0); + cam_cpas_soc_disable_resources( + &cpas_hw->soc_info, true, true); + CAM_ERR(CAM_CPAS, + "failed in power_on settings rc=%d", + rc); + goto remove_axi_vote; + } + } + CAM_DBG(CAM_CPAS, "irq_count=%d\n", + atomic_read(&cpas_core->irq_count)); + cpas_hw->hw_state = CAM_HW_STATE_POWER_UP; + } + + cpas_client->started = true; + cpas_core->streamon_clients++; + + CAM_DBG(CAM_CPAS, "client=[%d][%s][%d] streamon_clients=%d", + client_indx, cpas_client->data.identifier, + cpas_client->data.cell_index, cpas_core->streamon_clients); + + mutex_unlock(&cpas_core->client_mutex[client_indx]); + mutex_unlock(&cpas_hw->hw_mutex); + return rc; + +remove_axi_vote: + memset(&axi_vote, 0x0, sizeof(struct cam_axi_vote)); + rc_eh = cam_cpas_util_create_vote_all_paths(cpas_client, &axi_vote); + if (rc_eh) + CAM_ERR(CAM_CPAS, + "Unable to create per path votes rc_eh: %d", rc_eh); + + cam_cpas_dump_axi_vote_info(cpas_client, "CPAS Start fail Vote", + &axi_vote); + + rc_eh = cam_cpas_util_apply_client_axi_vote(cpas_hw, + cpas_client, &axi_vote); + if (rc_eh) + CAM_ERR(CAM_CPAS, "Unable remove votes rc_eh: %d", rc_eh); + +remove_ahb_vote: + remove_ahb.type = CAM_VOTE_ABSOLUTE; + remove_ahb.vote.level = CAM_SUSPEND_VOTE; + rc_eh = cam_cpas_util_apply_client_ahb_vote(cpas_hw, cpas_client, + &remove_ahb, NULL); + if (rc_eh) + CAM_ERR(CAM_CPAS, "Removing AHB vote failed, rc_eh=%d", rc_eh); + +error: + mutex_unlock(&cpas_core->client_mutex[client_indx]); + mutex_unlock(&cpas_hw->hw_mutex); + return rc; +} + +static int _check_irq_count(struct cam_cpas *cpas_core) +{ + return (atomic_read(&cpas_core->irq_count) > 0) ? 0 : 1; +} + +static int cam_cpas_hw_stop(void *hw_priv, void *stop_args, + uint32_t arg_size) +{ + struct cam_hw_info *cpas_hw; + struct cam_cpas *cpas_core; + uint32_t client_indx; + struct cam_cpas_hw_cmd_stop *cmd_hw_stop; + struct cam_cpas_client *cpas_client; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + struct cam_cpas_private_soc *soc_private = NULL; + int rc = 0; + long result; + + if (!hw_priv || !stop_args) { + CAM_ERR(CAM_CPAS, "Invalid arguments %pK %pK", + hw_priv, stop_args); + return -EINVAL; + } + + if (sizeof(struct cam_cpas_hw_cmd_stop) != arg_size) { + CAM_ERR(CAM_CPAS, "HW_CAPS size mismatch %zd %d", + sizeof(struct cam_cpas_hw_cmd_stop), arg_size); + return -EINVAL; + } + + cpas_hw = (struct cam_hw_info *)hw_priv; + cpas_core = (struct cam_cpas *) cpas_hw->core_info; + soc_private = (struct cam_cpas_private_soc *) + cpas_hw->soc_info.soc_private; + cmd_hw_stop = (struct cam_cpas_hw_cmd_stop *)stop_args; + client_indx = CAM_CPAS_GET_CLIENT_IDX(cmd_hw_stop->client_handle); + + if (!CAM_CPAS_CLIENT_VALID(client_indx)) + return -EINVAL; + + mutex_lock(&cpas_hw->hw_mutex); + mutex_lock(&cpas_core->client_mutex[client_indx]); + cpas_client = cpas_core->cpas_client[client_indx]; + + CAM_DBG(CAM_CPAS, "Client=[%d][%s][%d] streamon_clients=%d", + client_indx, cpas_client->data.identifier, + cpas_client->data.cell_index, cpas_core->streamon_clients); + + if (!CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) { + CAM_ERR(CAM_CPAS, "Client=[%d][%s][%d] is not started", + client_indx, cpas_client->data.identifier, + cpas_client->data.cell_index); + rc = -EPERM; + goto done; + } + + cpas_client->started = false; + cpas_core->streamon_clients--; + + if (cpas_core->streamon_clients == 0) { + if (cpas_core->internal_ops.power_off) { + rc = cpas_core->internal_ops.power_off(cpas_hw); + if (rc) { + CAM_ERR(CAM_CPAS, + "failed in power_off settings rc=%d", + rc); + /* Do not return error, passthrough */ + } + } + + rc = cam_cpas_soc_disable_irq(&cpas_hw->soc_info); + if (rc) { + CAM_ERR(CAM_CPAS, "disable_irq failed, rc=%d", rc); + goto done; + } + + /* Wait for any IRQs still being handled */ + atomic_dec(&cpas_core->irq_count); + result = wait_event_timeout(cpas_core->irq_count_wq, + _check_irq_count(cpas_core), HZ); + if (result == 0) { + CAM_ERR(CAM_CPAS, "Wait failed: irq_count=%d", + atomic_read(&cpas_core->irq_count)); + } + + rc = cam_cpas_soc_disable_resources(&cpas_hw->soc_info, + true, false); + if (rc) { + CAM_ERR(CAM_CPAS, "disable_resorce failed, rc=%d", rc); + goto done; + } + CAM_DBG(CAM_CPAS, "Disabled all the resources: irq_count=%d\n", + atomic_read(&cpas_core->irq_count)); + cpas_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + + if (soc_private->cx_ipeak_gpu_limit && + soc_private->gpu_pwr_limit) { + kgsl_pwr_limits_set_default( + soc_private->gpu_pwr_limit); + kgsl_pwr_limits_del(soc_private->gpu_pwr_limit); + soc_private->gpu_pwr_limit = NULL; + } + } + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_SUSPEND_VOTE; + rc = cam_cpas_util_apply_client_ahb_vote(cpas_hw, cpas_client, + &ahb_vote, NULL); + if (rc) + goto done; + + rc = cam_cpas_util_create_vote_all_paths(cpas_client, &axi_vote); + if (rc) { + CAM_ERR(CAM_CPAS, "Unable to create per path votes rc: %d", rc); + goto done; + } + + cam_cpas_dump_axi_vote_info(cpas_client, "CPAS Stop Vote", &axi_vote); + + rc = cam_cpas_util_apply_client_axi_vote(cpas_hw, + cpas_client, &axi_vote); + if (rc) + goto done; + + if (cpas_core->streamon_clients == 0) + rc = cam_cpas_util_apply_default_axi_vote(cpas_hw, false); +done: + mutex_unlock(&cpas_core->client_mutex[client_indx]); + mutex_unlock(&cpas_hw->hw_mutex); + return rc; +} + +static int cam_cpas_hw_init(void *hw_priv, void *init_hw_args, + uint32_t arg_size) +{ + struct cam_hw_info *cpas_hw; + struct cam_cpas *cpas_core; + int rc = 0; + + if (!hw_priv || !init_hw_args) { + CAM_ERR(CAM_CPAS, "Invalid arguments %pK %pK", + hw_priv, init_hw_args); + return -EINVAL; + } + + if (sizeof(struct cam_cpas_hw_caps) != arg_size) { + CAM_ERR(CAM_CPAS, "INIT HW size mismatch %zd %d", + sizeof(struct cam_cpas_hw_caps), arg_size); + return -EINVAL; + } + + cpas_hw = (struct cam_hw_info *)hw_priv; + cpas_core = (struct cam_cpas *)cpas_hw->core_info; + + if (cpas_core->internal_ops.init_hw_version) { + rc = cpas_core->internal_ops.init_hw_version(cpas_hw, + (struct cam_cpas_hw_caps *)init_hw_args); + } + + return rc; +} + +static int cam_cpas_hw_register_client(struct cam_hw_info *cpas_hw, + struct cam_cpas_register_params *register_params) +{ + int rc; + char client_name[CAM_HW_IDENTIFIER_LENGTH + 3]; + int32_t client_indx = -1; + struct cam_cpas *cpas_core = (struct cam_cpas *)cpas_hw->core_info; + struct cam_cpas_private_soc *soc_private = + (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private; + + if ((!register_params) || + (strlen(register_params->identifier) < 1)) { + CAM_ERR(CAM_CPAS, "Invalid cpas client identifier"); + return -EINVAL; + } + + CAM_DBG(CAM_CPAS, "Register params : identifier=%s, cell_index=%d", + register_params->identifier, register_params->cell_index); + + if (soc_private->client_id_based) + snprintf(client_name, sizeof(client_name), "%s%d", + register_params->identifier, + register_params->cell_index); + else + snprintf(client_name, sizeof(client_name), "%s", + register_params->identifier); + + mutex_lock(&cpas_hw->hw_mutex); + + rc = cam_common_util_get_string_index(soc_private->client_name, + soc_private->num_clients, client_name, &client_indx); + + mutex_lock(&cpas_core->client_mutex[client_indx]); + + if (rc || !CAM_CPAS_CLIENT_VALID(client_indx) || + CAM_CPAS_CLIENT_REGISTERED(cpas_core, client_indx)) { + CAM_ERR(CAM_CPAS, + "Inval client %s %d : %d %d %pK %d", + register_params->identifier, + register_params->cell_index, + CAM_CPAS_CLIENT_VALID(client_indx), + CAM_CPAS_CLIENT_REGISTERED(cpas_core, client_indx), + cpas_core->cpas_client[client_indx], rc); + mutex_unlock(&cpas_core->client_mutex[client_indx]); + mutex_unlock(&cpas_hw->hw_mutex); + return -EPERM; + } + + register_params->client_handle = + CAM_CPAS_GET_CLIENT_HANDLE(client_indx); + memcpy(&cpas_core->cpas_client[client_indx]->data, register_params, + sizeof(struct cam_cpas_register_params)); + cpas_core->registered_clients++; + cpas_core->cpas_client[client_indx]->registered = true; + + CAM_DBG(CAM_CPAS, "client=[%d][%s][%d], registered_clients=%d", + client_indx, + cpas_core->cpas_client[client_indx]->data.identifier, + cpas_core->cpas_client[client_indx]->data.cell_index, + cpas_core->registered_clients); + + mutex_unlock(&cpas_core->client_mutex[client_indx]); + mutex_unlock(&cpas_hw->hw_mutex); + + return 0; +} + +static int cam_cpas_hw_unregister_client(struct cam_hw_info *cpas_hw, + uint32_t client_handle) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + uint32_t client_indx = CAM_CPAS_GET_CLIENT_IDX(client_handle); + int rc = 0; + + if (!CAM_CPAS_CLIENT_VALID(client_indx)) + return -EINVAL; + + mutex_lock(&cpas_hw->hw_mutex); + mutex_lock(&cpas_core->client_mutex[client_indx]); + + if (!CAM_CPAS_CLIENT_REGISTERED(cpas_core, client_indx)) { + CAM_ERR(CAM_CPAS, "Client=[%d][%s][%d] not registered", + client_indx, + cpas_core->cpas_client[client_indx]->data.identifier, + cpas_core->cpas_client[client_indx]->data.cell_index); + rc = -EPERM; + goto done; + } + + if (CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) { + CAM_ERR(CAM_CPAS, "Client=[%d][%s][%d] is not stopped", + client_indx, + cpas_core->cpas_client[client_indx]->data.identifier, + cpas_core->cpas_client[client_indx]->data.cell_index); + + rc = -EPERM; + goto done; + } + + CAM_DBG(CAM_CPAS, "client=[%d][%s][%d], registered_clients=%d", + client_indx, + cpas_core->cpas_client[client_indx]->data.identifier, + cpas_core->cpas_client[client_indx]->data.cell_index, + cpas_core->registered_clients); + + cpas_core->cpas_client[client_indx]->registered = false; + cpas_core->registered_clients--; +done: + mutex_unlock(&cpas_core->client_mutex[client_indx]); + mutex_unlock(&cpas_hw->hw_mutex); + return rc; +} + +static int cam_cpas_hw_get_hw_info(void *hw_priv, + void *get_hw_cap_args, uint32_t arg_size) +{ + struct cam_hw_info *cpas_hw; + struct cam_cpas *cpas_core; + struct cam_cpas_hw_caps *hw_caps; + + if (!hw_priv || !get_hw_cap_args) { + CAM_ERR(CAM_CPAS, "Invalid arguments %pK %pK", + hw_priv, get_hw_cap_args); + return -EINVAL; + } + + if (sizeof(struct cam_cpas_hw_caps) != arg_size) { + CAM_ERR(CAM_CPAS, "HW_CAPS size mismatch %zd %d", + sizeof(struct cam_cpas_hw_caps), arg_size); + return -EINVAL; + } + + cpas_hw = (struct cam_hw_info *)hw_priv; + cpas_core = (struct cam_cpas *) cpas_hw->core_info; + hw_caps = (struct cam_cpas_hw_caps *)get_hw_cap_args; + + *hw_caps = cpas_core->hw_caps; + + return 0; +} + +static int cam_cpas_log_vote(struct cam_hw_info *cpas_hw) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_private_soc *soc_private = + (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private; + int rc = 0; + uint32_t i; + + for (i = 0; i < cpas_core->num_axi_ports; i++) { + CAM_INFO(CAM_CPAS, + "[%s] ab_bw[%lld] ib_bw[%lld] additional_bw[%lld] applied_ab[%lld] applied_ib[%lld]", + cpas_core->axi_port[i].axi_port_name, + cpas_core->axi_port[i].ab_bw, + cpas_core->axi_port[i].ib_bw, + cpas_core->axi_port[i].additional_bw, + cpas_core->axi_port[i].applied_ab_bw, + cpas_core->axi_port[i].applied_ib_bw); + } + + if (soc_private->control_camnoc_axi_clk) { + CAM_INFO(CAM_CPAS, "applied camnoc axi clk[%lld]", + cpas_core->applied_camnoc_axi_rate); + } else { + for (i = 0; i < cpas_core->num_camnoc_axi_ports; i++) { + CAM_INFO(CAM_CPAS, + "[%s] ab_bw[%lld] ib_bw[%lld] additional_bw[%lld] applied_ab[%lld] applied_ib[%lld]", + cpas_core->camnoc_axi_port[i].axi_port_name, + cpas_core->camnoc_axi_port[i].ab_bw, + cpas_core->camnoc_axi_port[i].ib_bw, + cpas_core->camnoc_axi_port[i].additional_bw, + cpas_core->camnoc_axi_port[i].applied_ab_bw, + cpas_core->camnoc_axi_port[i].applied_ib_bw); + } + } + + CAM_INFO(CAM_CPAS, "ahb client curr vote level[%d]", + cpas_core->ahb_bus_client.curr_vote_level); + + return rc; +} + +static int cam_cpas_hw_process_cmd(void *hw_priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = -EINVAL; + + if (!hw_priv || !cmd_args || + (cmd_type >= CAM_CPAS_HW_CMD_INVALID)) { + CAM_ERR(CAM_CPAS, "Invalid arguments %pK %pK %d", + hw_priv, cmd_args, cmd_type); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_CPAS_HW_CMD_REGISTER_CLIENT: { + struct cam_cpas_register_params *register_params; + + if (sizeof(struct cam_cpas_register_params) != arg_size) { + CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d", + cmd_type, arg_size); + break; + } + + register_params = (struct cam_cpas_register_params *)cmd_args; + rc = cam_cpas_hw_register_client(hw_priv, register_params); + break; + } + case CAM_CPAS_HW_CMD_UNREGISTER_CLIENT: { + uint32_t *client_handle; + + if (sizeof(uint32_t) != arg_size) { + CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d", + cmd_type, arg_size); + break; + } + + client_handle = (uint32_t *)cmd_args; + rc = cam_cpas_hw_unregister_client(hw_priv, *client_handle); + break; + } + case CAM_CPAS_HW_CMD_REG_WRITE: { + struct cam_cpas_hw_cmd_reg_read_write *reg_write; + + if (sizeof(struct cam_cpas_hw_cmd_reg_read_write) != + arg_size) { + CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d", + cmd_type, arg_size); + break; + } + + reg_write = + (struct cam_cpas_hw_cmd_reg_read_write *)cmd_args; + rc = cam_cpas_hw_reg_write(hw_priv, reg_write->client_handle, + reg_write->reg_base, reg_write->offset, reg_write->mb, + reg_write->value); + break; + } + case CAM_CPAS_HW_CMD_REG_READ: { + struct cam_cpas_hw_cmd_reg_read_write *reg_read; + + if (sizeof(struct cam_cpas_hw_cmd_reg_read_write) != + arg_size) { + CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d", + cmd_type, arg_size); + break; + } + + reg_read = + (struct cam_cpas_hw_cmd_reg_read_write *)cmd_args; + rc = cam_cpas_hw_reg_read(hw_priv, + reg_read->client_handle, reg_read->reg_base, + reg_read->offset, reg_read->mb, ®_read->value); + + break; + } + case CAM_CPAS_HW_CMD_AHB_VOTE: { + struct cam_cpas_hw_cmd_ahb_vote *cmd_ahb_vote; + + if (sizeof(struct cam_cpas_hw_cmd_ahb_vote) != arg_size) { + CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d", + cmd_type, arg_size); + break; + } + + cmd_ahb_vote = (struct cam_cpas_hw_cmd_ahb_vote *)cmd_args; + rc = cam_cpas_hw_update_ahb_vote(hw_priv, + cmd_ahb_vote->client_handle, cmd_ahb_vote->ahb_vote); + break; + } + case CAM_CPAS_HW_CMD_AXI_VOTE: { + struct cam_cpas_hw_cmd_axi_vote *cmd_axi_vote; + + if (sizeof(struct cam_cpas_hw_cmd_axi_vote) != arg_size) { + CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d", + cmd_type, arg_size); + break; + } + + cmd_axi_vote = (struct cam_cpas_hw_cmd_axi_vote *)cmd_args; + rc = cam_cpas_hw_update_axi_vote(hw_priv, + cmd_axi_vote->client_handle, cmd_axi_vote->axi_vote); + break; + } + case CAM_CPAS_HW_CMD_LOG_VOTE: { + rc = cam_cpas_log_vote(hw_priv); + break; + } + default: + CAM_ERR(CAM_CPAS, "CPAS HW command not valid =%d", cmd_type); + break; + } + + return rc; +} + +static int cam_cpas_util_client_setup(struct cam_hw_info *cpas_hw) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + int i; + + for (i = 0; i < CAM_CPAS_MAX_CLIENTS; i++) { + mutex_init(&cpas_core->client_mutex[i]); + } + + return 0; +} + +int cam_cpas_util_client_cleanup(struct cam_hw_info *cpas_hw) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + int i; + + for (i = 0; i < CAM_CPAS_MAX_CLIENTS; i++) { + if (cpas_core->cpas_client[i] && + cpas_core->cpas_client[i]->registered) { + cam_cpas_hw_unregister_client(cpas_hw, i); + } + kfree(cpas_core->cpas_client[i]); + cpas_core->cpas_client[i] = NULL; + mutex_destroy(&cpas_core->client_mutex[i]); + } + + return 0; +} + +static int cam_cpas_util_get_internal_ops(struct platform_device *pdev, + struct cam_hw_intf *hw_intf, struct cam_cpas_internal_ops *internal_ops) +{ + struct device_node *of_node = pdev->dev.of_node; + int rc; + const char *compat_str = NULL; + + rc = of_property_read_string_index(of_node, "arch-compat", 0, + (const char **)&compat_str); + if (rc) { + CAM_ERR(CAM_CPAS, "failed to get arch-compat rc=%d", rc); + return -EINVAL; + } + + if (strnstr(compat_str, "camss_top", strlen(compat_str))) { + hw_intf->hw_type = CAM_HW_CAMSSTOP; + rc = cam_camsstop_get_internal_ops(internal_ops); + } else if (strnstr(compat_str, "cpas_top", strlen(compat_str))) { + hw_intf->hw_type = CAM_HW_CPASTOP; + rc = cam_cpastop_get_internal_ops(internal_ops); + } else { + CAM_ERR(CAM_CPAS, "arch-compat %s not supported", compat_str); + rc = -EINVAL; + } + + return rc; +} + +static int cam_cpas_util_create_debugfs( + struct cam_cpas *cpas_core) +{ + int rc = 0; + + cpas_core->dentry = debugfs_create_dir("camera_cpas", NULL); + if (!cpas_core->dentry) + return -ENOMEM; + + if (!debugfs_create_bool("ahb_bus_scaling_disable", + 0644, + cpas_core->dentry, + &cpas_core->ahb_bus_scaling_disable)) { + CAM_ERR(CAM_CPAS, + "failed to create ahb_bus_scaling_disable entry"); + rc = -ENOMEM; + goto err; + } + + return 0; + +err: + debugfs_remove_recursive(cpas_core->dentry); + cpas_core->dentry = NULL; + return rc; +} + +int cam_cpas_hw_probe(struct platform_device *pdev, + struct cam_hw_intf **hw_intf) +{ + int rc = 0; + int i; + struct cam_hw_info *cpas_hw = NULL; + struct cam_hw_intf *cpas_hw_intf = NULL; + struct cam_cpas *cpas_core = NULL; + struct cam_cpas_private_soc *soc_private; + struct cam_cpas_internal_ops *internal_ops; + + cpas_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!cpas_hw_intf) + return -ENOMEM; + + cpas_hw = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!cpas_hw) { + kfree(cpas_hw_intf); + return -ENOMEM; + } + + cpas_core = kzalloc(sizeof(struct cam_cpas), GFP_KERNEL); + if (!cpas_core) { + kfree(cpas_hw); + kfree(cpas_hw_intf); + return -ENOMEM; + } + + for (i = 0; i < CAM_CPAS_REG_MAX; i++) + cpas_core->regbase_index[i] = -1; + + cpas_hw_intf->hw_priv = cpas_hw; + cpas_hw->core_info = cpas_core; + + cpas_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + cpas_hw->soc_info.pdev = pdev; + cpas_hw->soc_info.dev = &pdev->dev; + cpas_hw->soc_info.dev_name = pdev->name; + cpas_hw->open_count = 0; + cpas_core->ahb_bus_scaling_disable = false; + mutex_init(&cpas_hw->hw_mutex); + spin_lock_init(&cpas_hw->hw_lock); + init_completion(&cpas_hw->hw_complete); + + cpas_hw_intf->hw_ops.get_hw_caps = cam_cpas_hw_get_hw_info; + cpas_hw_intf->hw_ops.init = cam_cpas_hw_init; + cpas_hw_intf->hw_ops.deinit = NULL; + cpas_hw_intf->hw_ops.reset = NULL; + cpas_hw_intf->hw_ops.reserve = NULL; + cpas_hw_intf->hw_ops.release = NULL; + cpas_hw_intf->hw_ops.start = cam_cpas_hw_start; + cpas_hw_intf->hw_ops.stop = cam_cpas_hw_stop; + cpas_hw_intf->hw_ops.read = NULL; + cpas_hw_intf->hw_ops.write = NULL; + cpas_hw_intf->hw_ops.process_cmd = cam_cpas_hw_process_cmd; + + cpas_core->work_queue = alloc_workqueue("cam-cpas", + WQ_UNBOUND | WQ_MEM_RECLAIM, CAM_CPAS_INFLIGHT_WORKS); + if (!cpas_core->work_queue) { + rc = -ENOMEM; + goto release_mem; + } + + internal_ops = &cpas_core->internal_ops; + rc = cam_cpas_util_get_internal_ops(pdev, cpas_hw_intf, internal_ops); + if (rc) + goto release_workq; + + rc = cam_cpas_soc_init_resources(&cpas_hw->soc_info, + internal_ops->handle_irq, cpas_hw); + if (rc) + goto release_workq; + + soc_private = (struct cam_cpas_private_soc *) + cpas_hw->soc_info.soc_private; + cpas_core->num_clients = soc_private->num_clients; + atomic_set(&cpas_core->irq_count, 0); + init_waitqueue_head(&cpas_core->irq_count_wq); + + if (internal_ops->setup_regbase) { + rc = internal_ops->setup_regbase(&cpas_hw->soc_info, + cpas_core->regbase_index, CAM_CPAS_REG_MAX); + if (rc) + goto deinit_platform_res; + } + + rc = cam_cpas_util_client_setup(cpas_hw); + if (rc) { + CAM_ERR(CAM_CPAS, "failed in client setup, rc=%d", rc); + goto deinit_platform_res; + } + + rc = cam_cpas_util_register_bus_client(&cpas_hw->soc_info, + cpas_hw->soc_info.pdev->dev.of_node, + &cpas_core->ahb_bus_client); + if (rc) { + CAM_ERR(CAM_CPAS, "failed in ahb setup, rc=%d", rc); + goto client_cleanup; + } + + rc = cam_cpas_util_axi_setup(cpas_core, &cpas_hw->soc_info); + if (rc) { + CAM_ERR(CAM_CPAS, "failed in axi setup, rc=%d", rc); + goto ahb_cleanup; + } + + /* Need to vote first before enabling clocks */ + rc = cam_cpas_util_vote_default_ahb_axi(cpas_hw, true); + if (rc) + goto axi_cleanup; + + rc = cam_cpas_soc_enable_resources(&cpas_hw->soc_info, CAM_SVS_VOTE); + if (rc) { + CAM_ERR(CAM_CPAS, "failed in soc_enable_resources, rc=%d", rc); + goto remove_default_vote; + } + + if (internal_ops->get_hw_info) { + rc = internal_ops->get_hw_info(cpas_hw, &cpas_core->hw_caps); + if (rc) { + CAM_ERR(CAM_CPAS, "failed in get_hw_info, rc=%d", rc); + goto disable_soc_res; + } + } else { + CAM_ERR(CAM_CPAS, "Invalid get_hw_info"); + goto disable_soc_res; + } + + rc = cam_cpas_hw_init(cpas_hw_intf->hw_priv, + &cpas_core->hw_caps, sizeof(struct cam_cpas_hw_caps)); + if (rc) + goto disable_soc_res; + + rc = cam_cpas_soc_disable_resources(&cpas_hw->soc_info, true, true); + if (rc) { + CAM_ERR(CAM_CPAS, "failed in soc_disable_resources, rc=%d", rc); + goto remove_default_vote; + } + + rc = cam_cpas_util_vote_default_ahb_axi(cpas_hw, false); + if (rc) + goto axi_cleanup; + + rc = cam_cpas_util_create_debugfs(cpas_core); + if (rc) + CAM_WARN(CAM_CPAS, "Failed to create dentry"); + + *hw_intf = cpas_hw_intf; + return 0; + +disable_soc_res: + cam_cpas_soc_disable_resources(&cpas_hw->soc_info, true, true); +remove_default_vote: + cam_cpas_util_vote_default_ahb_axi(cpas_hw, false); +axi_cleanup: + cam_cpas_util_axi_cleanup(cpas_core, &cpas_hw->soc_info); +ahb_cleanup: + cam_cpas_util_unregister_bus_client(&cpas_core->ahb_bus_client); +client_cleanup: + cam_cpas_util_client_cleanup(cpas_hw); + cam_cpas_node_tree_cleanup(cpas_core, cpas_hw->soc_info.soc_private); +deinit_platform_res: + cam_cpas_soc_deinit_resources(&cpas_hw->soc_info); +release_workq: + flush_workqueue(cpas_core->work_queue); + destroy_workqueue(cpas_core->work_queue); +release_mem: + mutex_destroy(&cpas_hw->hw_mutex); + kfree(cpas_core); + kfree(cpas_hw); + kfree(cpas_hw_intf); + CAM_ERR(CAM_CPAS, "failed in hw probe"); + return rc; +} + +int cam_cpas_hw_remove(struct cam_hw_intf *cpas_hw_intf) +{ + struct cam_hw_info *cpas_hw; + struct cam_cpas *cpas_core; + + if (!cpas_hw_intf) { + CAM_ERR(CAM_CPAS, "cpas interface not initialized"); + return -EINVAL; + } + + cpas_hw = (struct cam_hw_info *)cpas_hw_intf->hw_priv; + cpas_core = (struct cam_cpas *)cpas_hw->core_info; + + if (cpas_hw->hw_state == CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_CPAS, "cpas hw is in power up state"); + return -EINVAL; + } + + cam_cpas_util_axi_cleanup(cpas_core, &cpas_hw->soc_info); + cam_cpas_node_tree_cleanup(cpas_core, cpas_hw->soc_info.soc_private); + cam_cpas_util_unregister_bus_client(&cpas_core->ahb_bus_client); + cam_cpas_util_client_cleanup(cpas_hw); + cam_cpas_soc_deinit_resources(&cpas_hw->soc_info); + debugfs_remove_recursive(cpas_core->dentry); + cpas_core->dentry = NULL; + flush_workqueue(cpas_core->work_queue); + destroy_workqueue(cpas_core->work_queue); + mutex_destroy(&cpas_hw->hw_mutex); + kfree(cpas_core); + kfree(cpas_hw); + kfree(cpas_hw_intf); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_hw.h b/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_hw.h new file mode 100644 index 0000000000000000000000000000000000000000..acad4ba44b17ef71fdf056720d634c25b029039a --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_hw.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CPAS_HW_H_ +#define _CAM_CPAS_HW_H_ + +#include +#include "cam_cpas_api.h" +#include "cam_cpas_hw_intf.h" +#include "cam_common_util.h" + +#define CAM_CPAS_INFLIGHT_WORKS 5 +#define CAM_CPAS_MAX_CLIENTS 40 +#define CAM_CPAS_MAX_AXI_PORTS 6 +#define CAM_CPAS_MAX_TREE_LEVELS 4 +#define CAM_CPAS_MAX_GRAN_PATHS_PER_CLIENT 32 +#define CAM_CPAS_PATH_DATA_MAX 38 +#define CAM_CPAS_TRANSACTION_MAX 2 + +#define CAM_CPAS_AXI_MIN_MNOC_AB_BW (2048 * 1024) +#define CAM_CPAS_AXI_MIN_MNOC_IB_BW (2048 * 1024) +#define CAM_CPAS_AXI_MIN_CAMNOC_AB_BW (2048 * 1024) +#define CAM_CPAS_AXI_MIN_CAMNOC_IB_BW (3000000000UL) + +#define CAM_CPAS_GET_CLIENT_IDX(handle) (handle) +#define CAM_CPAS_GET_CLIENT_HANDLE(indx) (indx) + +#define CAM_CPAS_CLIENT_VALID(indx) \ + ((indx >= 0) && (indx < CAM_CPAS_MAX_CLIENTS)) +#define CAM_CPAS_CLIENT_REGISTERED(cpas_core, indx) \ + ((CAM_CPAS_CLIENT_VALID(indx)) && \ + (cpas_core->cpas_client[indx]->registered)) +#define CAM_CPAS_CLIENT_STARTED(cpas_core, indx) \ + ((CAM_CPAS_CLIENT_REGISTERED(cpas_core, indx)) && \ + (cpas_core->cpas_client[indx]->started)) + +/** + * enum cam_cpas_access_type - Enum for Register access type + */ +enum cam_cpas_access_type { + CAM_REG_TYPE_READ, + CAM_REG_TYPE_WRITE, + CAM_REG_TYPE_READ_WRITE, +}; + +/** + * struct cam_cpas_internal_ops - CPAS Hardware layer internal ops + * + * @get_hw_info: Function pointer for get hw info + * @init_hw_version: Function pointer for hw init based on version + * @handle_irq: Function poniter for irq handling + * @setup_regbase: Function pointer for setup rebase indices + * @power_on: Function pointer for hw core specific power on settings + * @power_off: Function pointer for hw core specific power off settings + * + */ +struct cam_cpas_internal_ops { + int (*get_hw_info)(struct cam_hw_info *cpas_hw, + struct cam_cpas_hw_caps *hw_caps); + int (*init_hw_version)(struct cam_hw_info *cpas_hw, + struct cam_cpas_hw_caps *hw_caps); + irqreturn_t (*handle_irq)(int irq_num, void *data); + int (*setup_regbase)(struct cam_hw_soc_info *soc_info, + int32_t regbase_index[], int32_t num_reg_map); + int (*power_on)(struct cam_hw_info *cpas_hw); + int (*power_off)(struct cam_hw_info *cpas_hw); +}; + +/** + * struct cam_cpas_reg : CPAS register info + * + * @enable: Whether this reg info need to be enabled + * @access_type: Register access type + * @masked_value: Whether this register write/read is based on mask, shift + * @mask: Mask for this register value + * @shift: Shift for this register value + * @value: Register value + * + */ +struct cam_cpas_reg { + bool enable; + enum cam_cpas_access_type access_type; + bool masked_value; + uint32_t offset; + uint32_t mask; + uint32_t shift; + uint32_t value; +}; + +/** + * struct cam_cpas_client : CPAS Client structure info + * + * @data: Client register params + * @registered: Whether client has registered with cpas + * @started: Whether client has streamed on + * @tree_node_valid: Indicates whether tree node has at least one valid node + * @ahb_level: Determined/Applied ahb level for the client + * @axi_vote: Determined/Applied axi vote for the client + * @axi_port: Client's parent axi port + * @tree_node: All granular path voting nodes for the client + * + */ +struct cam_cpas_client { + struct cam_cpas_register_params data; + bool registered; + bool started; + bool tree_node_valid; + enum cam_vote_level ahb_level; + struct cam_axi_vote axi_vote; + struct cam_cpas_axi_port *axi_port; + struct cam_cpas_tree_node *tree_node[CAM_CPAS_PATH_DATA_MAX] + [CAM_CPAS_TRANSACTION_MAX]; +}; + +/** + * struct cam_cpas_bus_client : Bus client information + * + * @src: Bus master/src id + * @dst: Bus slave/dst id + * @pdata: Bus pdata information + * @client_id: Bus client id + * @num_usecases: Number of use cases for this client + * @num_paths: Number of paths for this client + * @curr_vote_level: current voted index + * @dyn_vote: Whether dynamic voting enabled + * @lock: Mutex lock used while voting on this client + * @valid: Whether bus client is valid + * @name: Name of the bus client + * + */ +struct cam_cpas_bus_client { + int src; + int dst; + struct msm_bus_scale_pdata *pdata; + uint32_t client_id; + int num_usecases; + int num_paths; + unsigned int curr_vote_level; + bool dyn_vote; + struct mutex lock; + bool valid; + const char *name; +}; + +/** + * struct cam_cpas_axi_port : AXI port information + * + * @axi_port_name: Name of this AXI port + * @bus_client: bus client info for this port + * @ib_bw_voting_needed: if this port can update ib bw dynamically + * @axi_port_node: Node representing AXI Port info in device tree + * @ab_bw: AB bw value for this port + * @ib_bw: IB bw value for this port + * @camnoc_bw: CAMNOC bw value for this port + * @additional_bw: Additional bandwidth to cover non-hw cpas clients + * @applied_ab_bw: applied ab bw for this port + * @applied_ib_bw: applied ib bw for this port + */ +struct cam_cpas_axi_port { + const char *axi_port_name; + struct cam_cpas_bus_client bus_client; + bool ib_bw_voting_needed; + struct device_node *axi_port_node; + uint64_t ab_bw; + uint64_t ib_bw; + uint64_t camnoc_bw; + uint64_t additional_bw; + uint64_t applied_ab_bw; + uint64_t applied_ib_bw; +}; + +/** + * struct cam_cpas : CPAS core data structure info + * + * @hw_caps: CPAS hw capabilities + * @cpas_client: Array of pointers to CPAS clients info + * @client_mutex: Mutex for accessing client info + * @tree_lock: Mutex lock for accessing CPAS node tree + * @num_clients: Total number of clients that CPAS supports + * @num_axi_ports: Total number of axi ports found in device tree + * @num_camnoc_axi_ports: Total number of camnoc axi ports found in device tree + * @registered_clients: Number of Clients registered currently + * @streamon_clients: Number of Clients that are in start state currently + * @regbase_index: Register base indices for CPAS register base IDs + * @ahb_bus_client: AHB Bus client info + * @axi_port: AXI port info for a specific axi index + * @camnoc_axi_port: CAMNOC AXI port info for a specific camnoc axi index + * @internal_ops: CPAS HW internal ops + * @work_queue: Work queue handle + * @irq_count: atomic irq count + * @irq_count_wq: wait variable to ensure all irq's are handled + * @dentry: debugfs file entry + * @ahb_bus_scaling_disable: ahb scaling based on src clk corner for bus + * @applied_camnoc_axi_rate: applied camnoc axi clock rate + */ +struct cam_cpas { + struct cam_cpas_hw_caps hw_caps; + struct cam_cpas_client *cpas_client[CAM_CPAS_MAX_CLIENTS]; + struct mutex client_mutex[CAM_CPAS_MAX_CLIENTS]; + struct mutex tree_lock; + uint32_t num_clients; + uint32_t num_axi_ports; + uint32_t num_camnoc_axi_ports; + uint32_t registered_clients; + uint32_t streamon_clients; + int32_t regbase_index[CAM_CPAS_REG_MAX]; + struct cam_cpas_bus_client ahb_bus_client; + struct cam_cpas_axi_port axi_port[CAM_CPAS_MAX_AXI_PORTS]; + struct cam_cpas_axi_port camnoc_axi_port[CAM_CPAS_MAX_AXI_PORTS]; + struct cam_cpas_internal_ops internal_ops; + struct workqueue_struct *work_queue; + atomic_t irq_count; + wait_queue_head_t irq_count_wq; + struct dentry *dentry; + bool ahb_bus_scaling_disable; + uint64_t applied_camnoc_axi_rate; +}; + +int cam_camsstop_get_internal_ops(struct cam_cpas_internal_ops *internal_ops); +int cam_cpastop_get_internal_ops(struct cam_cpas_internal_ops *internal_ops); + +int cam_cpas_util_reg_update(struct cam_hw_info *cpas_hw, + enum cam_cpas_reg_base reg_base, struct cam_cpas_reg *reg_info); + +int cam_cpas_util_client_cleanup(struct cam_hw_info *cpas_hw); + +#endif /* _CAM_CPAS_HW_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_hw_intf.h b/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..3f644363062c431b99b81926e9b8dd72747f997e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_hw_intf.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CPAS_HW_INTF_H_ +#define _CAM_CPAS_HW_INTF_H_ + +#include + +#include "cam_cpas_api.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "cam_debug_util.h" + +/* Number of times to retry while polling */ +#define CAM_CPAS_POLL_RETRY_CNT 5 +/* Minimum usecs to sleep while polling */ +#define CAM_CPAS_POLL_MIN_USECS 200 +/* Maximum usecs to sleep while polling */ +#define CAM_CPAS_POLL_MAX_USECS 250 + +/** + * enum cam_cpas_hw_type - Enum for CPAS HW type + */ +enum cam_cpas_hw_type { + CAM_HW_CPASTOP, + CAM_HW_CAMSSTOP, +}; + +/** + * enum cam_cpas_hw_cmd_process - Enum for CPAS HW process command type + */ +enum cam_cpas_hw_cmd_process { + CAM_CPAS_HW_CMD_REGISTER_CLIENT, + CAM_CPAS_HW_CMD_UNREGISTER_CLIENT, + CAM_CPAS_HW_CMD_REG_WRITE, + CAM_CPAS_HW_CMD_REG_READ, + CAM_CPAS_HW_CMD_AHB_VOTE, + CAM_CPAS_HW_CMD_AXI_VOTE, + CAM_CPAS_HW_CMD_LOG_VOTE, + CAM_CPAS_HW_CMD_INVALID, +}; + +/** + * struct cam_cpas_hw_cmd_reg_read_write : CPAS cmd struct for reg read, write + * + * @client_handle: Client handle + * @reg_base: Register base type + * @offset: Register offset + * @value: Register value + * @mb: Whether to do operation with memory barrier + * + */ +struct cam_cpas_hw_cmd_reg_read_write { + uint32_t client_handle; + enum cam_cpas_reg_base reg_base; + uint32_t offset; + uint32_t value; + bool mb; +}; + +/** + * struct cam_cpas_hw_cmd_ahb_vote : CPAS cmd struct for AHB vote + * + * @client_handle: Client handle + * @ahb_vote: AHB voting info + * + */ +struct cam_cpas_hw_cmd_ahb_vote { + uint32_t client_handle; + struct cam_ahb_vote *ahb_vote; +}; + +/** + * struct cam_cpas_hw_cmd_axi_vote : CPAS cmd struct for AXI vote + * + * @client_handle: Client handle + * @axi_vote: axi bandwidth vote + * + */ +struct cam_cpas_hw_cmd_axi_vote { + uint32_t client_handle; + struct cam_axi_vote *axi_vote; +}; + +/** + * struct cam_cpas_hw_cmd_start : CPAS cmd struct for start + * + * @client_handle: Client handle + * + */ +struct cam_cpas_hw_cmd_start { + uint32_t client_handle; + struct cam_ahb_vote *ahb_vote; + struct cam_axi_vote *axi_vote; +}; + +/** + * struct cam_cpas_hw_cmd_stop : CPAS cmd struct for stop + * + * @client_handle: Client handle + * + */ +struct cam_cpas_hw_cmd_stop { + uint32_t client_handle; +}; + +/** + * struct cam_cpas_hw_caps : CPAS HW capabilities + * + * @camera_family: Camera family type + * @camera_version: Camera version + * @cpas_version: CPAS version + * @camera_capability: Camera hw capabilities + * + */ +struct cam_cpas_hw_caps { + uint32_t camera_family; + struct cam_hw_version camera_version; + struct cam_hw_version cpas_version; + uint32_t camera_capability; +}; + +int cam_cpas_hw_probe(struct platform_device *pdev, + struct cam_hw_intf **hw_intf); +int cam_cpas_hw_remove(struct cam_hw_intf *cpas_hw_intf); + +#endif /* _CAM_CPAS_HW_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_intf.c b/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_intf.c new file mode 100644 index 0000000000000000000000000000000000000000..ce649c06b32945cd8a82883838301a213cf97bb3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_intf.c @@ -0,0 +1,797 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cam_subdev.h" +#include "cam_cpas_hw_intf.h" +#include "cam_cpas_soc.h" + +#define CAM_CPAS_DEV_NAME "cam-cpas" +#define CAM_CPAS_INTF_INITIALIZED() (g_cpas_intf && g_cpas_intf->probe_done) + +/** + * struct cam_cpas_intf : CPAS interface + * + * @pdev: Platform device + * @subdev: Subdev info + * @hw_intf: CPAS HW interface + * @hw_caps: CPAS HW capabilities + * @intf_lock: CPAS interface mutex + * @open_cnt: CPAS subdev open count + * @probe_done: Whether CPAS prove completed + * + */ +struct cam_cpas_intf { + struct platform_device *pdev; + struct cam_subdev subdev; + struct cam_hw_intf *hw_intf; + struct cam_cpas_hw_caps hw_caps; + struct mutex intf_lock; + uint32_t open_cnt; + bool probe_done; +}; + +static struct cam_cpas_intf *g_cpas_intf; + +const char *cam_cpas_axi_util_path_type_to_string( + uint32_t path_data_type) +{ + switch (path_data_type) { + /* IFE Paths */ + case CAM_AXI_PATH_DATA_IFE_LINEAR: + return "IFE_LINEAR"; + case CAM_AXI_PATH_DATA_IFE_VID: + return "IFE_VID"; + case CAM_AXI_PATH_DATA_IFE_DISP: + return "IFE_DISP"; + case CAM_AXI_PATH_DATA_IFE_STATS: + return "IFE_STATS"; + case CAM_AXI_PATH_DATA_IFE_RDI0: + return "IFE_RDI0"; + case CAM_AXI_PATH_DATA_IFE_RDI1: + return "IFE_RDI1"; + case CAM_AXI_PATH_DATA_IFE_RDI2: + return "IFE_RDI2"; + case CAM_AXI_PATH_DATA_IFE_RDI3: + return "IFE_RDI3"; + case CAM_AXI_PATH_DATA_IFE_PDAF: + return "IFE_PDAF"; + case CAM_AXI_PATH_DATA_IFE_PIXEL_RAW: + return "IFE_PIXEL_RAW"; + + /* IPE Paths */ + case CAM_AXI_PATH_DATA_IPE_RD_IN: + return "IPE_RD_IN"; + case CAM_AXI_PATH_DATA_IPE_RD_REF: + return "IPE_RD_REF"; + case CAM_AXI_PATH_DATA_IPE_WR_VID: + return "IPE_WR_VID"; + case CAM_AXI_PATH_DATA_IPE_WR_DISP: + return "IPE_WR_DISP"; + case CAM_AXI_PATH_DATA_IPE_WR_REF: + return "IPE_WR_REF"; + + /* OPE Paths */ + case CAM_AXI_PATH_DATA_OPE_RD_IN: + return "OPE_RD_IN"; + case CAM_AXI_PATH_DATA_OPE_RD_REF: + return "OPE_RD_REF"; + case CAM_AXI_PATH_DATA_OPE_WR_VID: + return "OPE_WR_VID"; + case CAM_AXI_PATH_DATA_OPE_WR_DISP: + return "OPE_WR_DISP"; + case CAM_AXI_PATH_DATA_OPE_WR_REF: + return "OPE_WR_REF"; + + /* Common Paths */ + case CAM_AXI_PATH_DATA_ALL: + return "DATA_ALL"; + default: + return "IFE_PATH_INVALID"; + } +} +EXPORT_SYMBOL(cam_cpas_axi_util_path_type_to_string); + +const char *cam_cpas_axi_util_trans_type_to_string( + uint32_t transac_type) +{ + switch (transac_type) { + case CAM_AXI_TRANSACTION_READ: + return "TRANSAC_READ"; + case CAM_AXI_TRANSACTION_WRITE: + return "TRANSAC_WRITE"; + default: + return "TRANSAC_INVALID"; + } +} +EXPORT_SYMBOL(cam_cpas_axi_util_trans_type_to_string); + +bool cam_cpas_is_feature_supported(uint32_t flag, + uint32_t hw_id) +{ + struct cam_hw_info *cpas_hw = NULL; + struct cam_cpas_private_soc *soc_private = NULL; + uint32_t i; + bool supported = true; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return false; + } + + cpas_hw = (struct cam_hw_info *) g_cpas_intf->hw_intf->hw_priv; + soc_private = + (struct cam_cpas_private_soc *)cpas_hw->soc_info.soc_private; + + if (flag >= CAM_CPAS_FUSE_FEATURE_MAX) { + CAM_ERR(CAM_CPAS, "Unknown feature flag %x", flag); + return false; + } + + for (i = 0; i < soc_private->num_feature_entries; i++) { + if ((soc_private->feature_info[i].feature == flag) && + (soc_private->feature_info[i].hw_id == hw_id)) { + supported = soc_private->feature_info[i].enable; + break; + } + } + + return supported; +} +EXPORT_SYMBOL(cam_cpas_is_feature_supported); + +int cam_cpas_get_cpas_hw_version(uint32_t *hw_version) +{ + struct cam_hw_info *cpas_hw = NULL; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return -ENODEV; + } + + if (!hw_version) { + CAM_ERR(CAM_CPAS, "invalid input %pK", hw_version); + return -EINVAL; + } + + cpas_hw = (struct cam_hw_info *) g_cpas_intf->hw_intf->hw_priv; + + *hw_version = cpas_hw->soc_info.hw_version; + + if (*hw_version == CAM_CPAS_TITAN_NONE) { + CAM_DBG(CAM_CPAS, "Didn't find a valid HW Version %d", + *hw_version); + } + + return 0; +} + +int cam_cpas_get_hw_info(uint32_t *camera_family, + struct cam_hw_version *camera_version, + struct cam_hw_version *cpas_version, + uint32_t *cam_caps) +{ + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return -ENODEV; + } + + if (!camera_family || !camera_version || !cpas_version || !cam_caps) { + CAM_ERR(CAM_CPAS, "invalid input %pK %pK %pK %pK", + camera_family, camera_version, cpas_version, cam_caps); + return -EINVAL; + } + + *camera_family = g_cpas_intf->hw_caps.camera_family; + *camera_version = g_cpas_intf->hw_caps.camera_version; + *cpas_version = g_cpas_intf->hw_caps.cpas_version; + *cam_caps = g_cpas_intf->hw_caps.camera_capability; + + return 0; +} +EXPORT_SYMBOL(cam_cpas_get_hw_info); + +int cam_cpas_reg_write(uint32_t client_handle, + enum cam_cpas_reg_base reg_base, uint32_t offset, bool mb, + uint32_t value) +{ + int rc; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return -ENODEV; + } + + if (g_cpas_intf->hw_intf->hw_ops.process_cmd) { + struct cam_cpas_hw_cmd_reg_read_write cmd_reg_write; + + cmd_reg_write.client_handle = client_handle; + cmd_reg_write.reg_base = reg_base; + cmd_reg_write.offset = offset; + cmd_reg_write.value = value; + cmd_reg_write.mb = mb; + + rc = g_cpas_intf->hw_intf->hw_ops.process_cmd( + g_cpas_intf->hw_intf->hw_priv, + CAM_CPAS_HW_CMD_REG_WRITE, &cmd_reg_write, + sizeof(struct cam_cpas_hw_cmd_reg_read_write)); + if (rc) + CAM_ERR(CAM_CPAS, "Failed in process_cmd, rc=%d", rc); + } else { + CAM_ERR(CAM_CPAS, "Invalid process_cmd ops"); + rc = -EINVAL; + } + + return rc; +} +EXPORT_SYMBOL(cam_cpas_reg_write); + +int cam_cpas_reg_read(uint32_t client_handle, + enum cam_cpas_reg_base reg_base, uint32_t offset, bool mb, + uint32_t *value) +{ + int rc; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return -ENODEV; + } + + if (!value) { + CAM_ERR(CAM_CPAS, "Invalid arg value"); + return -EINVAL; + } + + if (g_cpas_intf->hw_intf->hw_ops.process_cmd) { + struct cam_cpas_hw_cmd_reg_read_write cmd_reg_read; + + cmd_reg_read.client_handle = client_handle; + cmd_reg_read.reg_base = reg_base; + cmd_reg_read.offset = offset; + cmd_reg_read.mb = mb; + cmd_reg_read.value = 0; + + rc = g_cpas_intf->hw_intf->hw_ops.process_cmd( + g_cpas_intf->hw_intf->hw_priv, + CAM_CPAS_HW_CMD_REG_READ, &cmd_reg_read, + sizeof(struct cam_cpas_hw_cmd_reg_read_write)); + if (rc) { + CAM_ERR(CAM_CPAS, "Failed in process_cmd, rc=%d", rc); + return rc; + } + + *value = cmd_reg_read.value; + } else { + CAM_ERR(CAM_CPAS, "Invalid process_cmd ops"); + rc = -EINVAL; + } + + return rc; +} +EXPORT_SYMBOL(cam_cpas_reg_read); + +int cam_cpas_update_axi_vote(uint32_t client_handle, + struct cam_axi_vote *axi_vote) +{ + int rc; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return -ENODEV; + } + + if (!axi_vote) { + CAM_ERR(CAM_CPAS, "NULL axi vote"); + return -EINVAL; + } + + if (g_cpas_intf->hw_intf->hw_ops.process_cmd) { + struct cam_cpas_hw_cmd_axi_vote cmd_axi_vote; + + cmd_axi_vote.client_handle = client_handle; + cmd_axi_vote.axi_vote = axi_vote; + + rc = g_cpas_intf->hw_intf->hw_ops.process_cmd( + g_cpas_intf->hw_intf->hw_priv, + CAM_CPAS_HW_CMD_AXI_VOTE, &cmd_axi_vote, + sizeof(struct cam_cpas_hw_cmd_axi_vote)); + if (rc) + CAM_ERR(CAM_CPAS, "Failed in process_cmd, rc=%d", rc); + } else { + CAM_ERR(CAM_CPAS, "Invalid process_cmd ops"); + rc = -EINVAL; + } + + return rc; +} +EXPORT_SYMBOL(cam_cpas_update_axi_vote); + +int cam_cpas_update_ahb_vote(uint32_t client_handle, + struct cam_ahb_vote *ahb_vote) +{ + int rc; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return -ENODEV; + } + + if (g_cpas_intf->hw_intf->hw_ops.process_cmd) { + struct cam_cpas_hw_cmd_ahb_vote cmd_ahb_vote; + + cmd_ahb_vote.client_handle = client_handle; + cmd_ahb_vote.ahb_vote = ahb_vote; + + rc = g_cpas_intf->hw_intf->hw_ops.process_cmd( + g_cpas_intf->hw_intf->hw_priv, + CAM_CPAS_HW_CMD_AHB_VOTE, &cmd_ahb_vote, + sizeof(struct cam_cpas_hw_cmd_ahb_vote)); + if (rc) + CAM_ERR(CAM_CPAS, "Failed in process_cmd, rc=%d", rc); + } else { + CAM_ERR(CAM_CPAS, "Invalid process_cmd ops"); + rc = -EINVAL; + } + + return rc; +} +EXPORT_SYMBOL(cam_cpas_update_ahb_vote); + +int cam_cpas_stop(uint32_t client_handle) +{ + int rc; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return -ENODEV; + } + + if (g_cpas_intf->hw_intf->hw_ops.stop) { + struct cam_cpas_hw_cmd_stop cmd_hw_stop; + + cmd_hw_stop.client_handle = client_handle; + + rc = g_cpas_intf->hw_intf->hw_ops.stop( + g_cpas_intf->hw_intf->hw_priv, &cmd_hw_stop, + sizeof(struct cam_cpas_hw_cmd_stop)); + if (rc) + CAM_ERR(CAM_CPAS, "Failed in stop, rc=%d", rc); + } else { + CAM_ERR(CAM_CPAS, "Invalid stop ops"); + rc = -EINVAL; + } + + return rc; +} +EXPORT_SYMBOL(cam_cpas_stop); + +int cam_cpas_start(uint32_t client_handle, + struct cam_ahb_vote *ahb_vote, struct cam_axi_vote *axi_vote) +{ + int rc; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return -ENODEV; + } + + if (!axi_vote) { + CAM_ERR(CAM_CPAS, "NULL axi vote"); + return -EINVAL; + } + + if (g_cpas_intf->hw_intf->hw_ops.start) { + struct cam_cpas_hw_cmd_start cmd_hw_start; + + cmd_hw_start.client_handle = client_handle; + cmd_hw_start.ahb_vote = ahb_vote; + cmd_hw_start.axi_vote = axi_vote; + + rc = g_cpas_intf->hw_intf->hw_ops.start( + g_cpas_intf->hw_intf->hw_priv, &cmd_hw_start, + sizeof(struct cam_cpas_hw_cmd_start)); + if (rc) + CAM_ERR(CAM_CPAS, "Failed in start, rc=%d", rc); + } else { + CAM_ERR(CAM_CPAS, "Invalid start ops"); + rc = -EINVAL; + } + + return rc; +} +EXPORT_SYMBOL(cam_cpas_start); + +void cam_cpas_log_votes(void) +{ + uint32_t dummy_args; + int rc; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return; + } + + if (g_cpas_intf->hw_intf->hw_ops.process_cmd) { + rc = g_cpas_intf->hw_intf->hw_ops.process_cmd( + g_cpas_intf->hw_intf->hw_priv, + CAM_CPAS_HW_CMD_LOG_VOTE, &dummy_args, + sizeof(dummy_args)); + if (rc) + CAM_ERR(CAM_CPAS, "Failed in process_cmd, rc=%d", rc); + } else { + CAM_ERR(CAM_CPAS, "Invalid process_cmd ops"); + } + +} +EXPORT_SYMBOL(cam_cpas_log_votes); + +int cam_cpas_unregister_client(uint32_t client_handle) +{ + int rc; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return -ENODEV; + } + + if (g_cpas_intf->hw_intf->hw_ops.process_cmd) { + rc = g_cpas_intf->hw_intf->hw_ops.process_cmd( + g_cpas_intf->hw_intf->hw_priv, + CAM_CPAS_HW_CMD_UNREGISTER_CLIENT, + &client_handle, sizeof(uint32_t)); + if (rc) + CAM_ERR(CAM_CPAS, "Failed in process_cmd, rc=%d", rc); + } else { + CAM_ERR(CAM_CPAS, "Invalid process_cmd ops"); + rc = -EINVAL; + } + + return rc; +} +EXPORT_SYMBOL(cam_cpas_unregister_client); + +int cam_cpas_register_client( + struct cam_cpas_register_params *register_params) +{ + int rc; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return -ENODEV; + } + + if (g_cpas_intf->hw_intf->hw_ops.process_cmd) { + rc = g_cpas_intf->hw_intf->hw_ops.process_cmd( + g_cpas_intf->hw_intf->hw_priv, + CAM_CPAS_HW_CMD_REGISTER_CLIENT, register_params, + sizeof(struct cam_cpas_register_params)); + if (rc) + CAM_ERR(CAM_CPAS, "Failed in process_cmd, rc=%d", rc); + } else { + CAM_ERR(CAM_CPAS, "Invalid process_cmd ops"); + rc = -EINVAL; + } + + return rc; +} +EXPORT_SYMBOL(cam_cpas_register_client); + +int cam_cpas_subdev_cmd(struct cam_cpas_intf *cpas_intf, + struct cam_control *cmd) +{ + int rc = 0; + + if (!cmd) { + CAM_ERR(CAM_CPAS, "Invalid input cmd"); + return -EINVAL; + } + + switch (cmd->op_code) { + case CAM_QUERY_CAP: { + struct cam_cpas_query_cap query; + + rc = copy_from_user(&query, u64_to_user_ptr(cmd->handle), + sizeof(query)); + if (rc) { + CAM_ERR(CAM_CPAS, "Failed in copy from user, rc=%d", + rc); + break; + } + + rc = cam_cpas_get_hw_info(&query.camera_family, + &query.camera_version, &query.cpas_version, + &query.reserved); + if (rc) + break; + + rc = copy_to_user(u64_to_user_ptr(cmd->handle), &query, + sizeof(query)); + if (rc) + CAM_ERR(CAM_CPAS, "Failed in copy to user, rc=%d", rc); + + break; + } + case CAM_SD_SHUTDOWN: + break; + default: + CAM_ERR(CAM_CPAS, "Unknown op code %d for CPAS", cmd->op_code); + rc = -EINVAL; + break; + } + + return rc; +} + +static int cam_cpas_subdev_open(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct cam_cpas_intf *cpas_intf = v4l2_get_subdevdata(sd); + + if (!cpas_intf || !cpas_intf->probe_done) { + CAM_ERR(CAM_CPAS, "CPAS not initialized"); + return -ENODEV; + } + + mutex_lock(&cpas_intf->intf_lock); + cpas_intf->open_cnt++; + CAM_DBG(CAM_CPAS, "CPAS Subdev open count %d", cpas_intf->open_cnt); + mutex_unlock(&cpas_intf->intf_lock); + + return 0; +} + +static int cam_cpas_subdev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct cam_cpas_intf *cpas_intf = v4l2_get_subdevdata(sd); + + if (!cpas_intf || !cpas_intf->probe_done) { + CAM_ERR(CAM_CPAS, "CPAS not initialized"); + return -ENODEV; + } + + mutex_lock(&cpas_intf->intf_lock); + cpas_intf->open_cnt--; + CAM_DBG(CAM_CPAS, "CPAS Subdev close count %d", cpas_intf->open_cnt); + mutex_unlock(&cpas_intf->intf_lock); + + return 0; +} + +static long cam_cpas_subdev_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + int32_t rc; + struct cam_cpas_intf *cpas_intf = v4l2_get_subdevdata(sd); + + if (!cpas_intf || !cpas_intf->probe_done) { + CAM_ERR(CAM_CPAS, "CPAS not initialized"); + return -ENODEV; + } + + switch (cmd) { + case VIDIOC_CAM_CONTROL: + rc = cam_cpas_subdev_cmd(cpas_intf, (struct cam_control *) arg); + break; + default: + CAM_ERR(CAM_CPAS, "Invalid command %d for CPAS!", cmd); + rc = -EINVAL; + break; + } + + return rc; +} + +#ifdef CONFIG_COMPAT +static long cam_cpas_subdev_compat_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + struct cam_control cmd_data; + int32_t rc; + struct cam_cpas_intf *cpas_intf = v4l2_get_subdevdata(sd); + + if (!cpas_intf || !cpas_intf->probe_done) { + CAM_ERR(CAM_CPAS, "CPAS not initialized"); + return -ENODEV; + } + + if (copy_from_user(&cmd_data, (void __user *)arg, + sizeof(cmd_data))) { + CAM_ERR(CAM_CPAS, "Failed to copy from user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + return -EFAULT; + } + + switch (cmd) { + case VIDIOC_CAM_CONTROL: + rc = cam_cpas_subdev_cmd(cpas_intf, &cmd_data); + break; + default: + CAM_ERR(CAM_CPAS, "Invalid command %d for CPAS!", cmd); + rc = -EINVAL; + break; + } + + if (!rc) { + if (copy_to_user((void __user *)arg, &cmd_data, + sizeof(cmd_data))) { + CAM_ERR(CAM_CPAS, + "Failed to copy to user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + rc = -EFAULT; + } + } + + return rc; +} +#endif + +static struct v4l2_subdev_core_ops cpas_subdev_core_ops = { + .ioctl = cam_cpas_subdev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = cam_cpas_subdev_compat_ioctl, +#endif +}; + +static const struct v4l2_subdev_ops cpas_subdev_ops = { + .core = &cpas_subdev_core_ops, +}; + +static const struct v4l2_subdev_internal_ops cpas_subdev_intern_ops = { + .open = cam_cpas_subdev_open, + .close = cam_cpas_subdev_close, +}; + +static int cam_cpas_subdev_register(struct platform_device *pdev) +{ + int rc; + struct cam_subdev *subdev; + + if (!g_cpas_intf) + return -EINVAL; + + subdev = &g_cpas_intf->subdev; + + subdev->name = CAM_CPAS_DEV_NAME; + subdev->pdev = pdev; + subdev->ops = &cpas_subdev_ops; + subdev->internal_ops = &cpas_subdev_intern_ops; + subdev->token = g_cpas_intf; + subdev->sd_flags = + V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; + subdev->ent_function = CAM_CPAS_DEVICE_TYPE; + + rc = cam_register_subdev(subdev); + if (rc) { + CAM_ERR(CAM_CPAS, "failed register subdev: %s!", + CAM_CPAS_DEV_NAME); + return rc; + } + + platform_set_drvdata(g_cpas_intf->pdev, g_cpas_intf); + return rc; +} + +static int cam_cpas_dev_probe(struct platform_device *pdev) +{ + struct cam_cpas_hw_caps *hw_caps; + struct cam_hw_intf *hw_intf; + int rc; + + if (g_cpas_intf) { + CAM_ERR(CAM_CPAS, "cpas dev proble already done"); + return -EALREADY; + } + + g_cpas_intf = kzalloc(sizeof(*g_cpas_intf), GFP_KERNEL); + if (!g_cpas_intf) + return -ENOMEM; + + mutex_init(&g_cpas_intf->intf_lock); + g_cpas_intf->pdev = pdev; + + rc = cam_cpas_hw_probe(pdev, &g_cpas_intf->hw_intf); + if (rc || (g_cpas_intf->hw_intf == NULL)) { + CAM_ERR(CAM_CPAS, "Failed in hw probe, rc=%d", rc); + goto error_destroy_mem; + } + + hw_intf = g_cpas_intf->hw_intf; + hw_caps = &g_cpas_intf->hw_caps; + if (hw_intf->hw_ops.get_hw_caps) { + rc = hw_intf->hw_ops.get_hw_caps(hw_intf->hw_priv, + hw_caps, sizeof(struct cam_cpas_hw_caps)); + if (rc) { + CAM_ERR(CAM_CPAS, "Failed in get_hw_caps, rc=%d", rc); + goto error_hw_remove; + } + } else { + CAM_ERR(CAM_CPAS, "Invalid get_hw_caps ops"); + goto error_hw_remove; + } + + rc = cam_cpas_subdev_register(pdev); + if (rc) + goto error_hw_remove; + + g_cpas_intf->probe_done = true; + CAM_DBG(CAM_CPAS, + "CPAS INTF Probe success %d, %d.%d.%d, %d.%d.%d, 0x%x", + hw_caps->camera_family, hw_caps->camera_version.major, + hw_caps->camera_version.minor, hw_caps->camera_version.incr, + hw_caps->cpas_version.major, hw_caps->cpas_version.minor, + hw_caps->cpas_version.incr, hw_caps->camera_capability); + + return rc; + +error_hw_remove: + cam_cpas_hw_remove(g_cpas_intf->hw_intf); +error_destroy_mem: + mutex_destroy(&g_cpas_intf->intf_lock); + kfree(g_cpas_intf); + g_cpas_intf = NULL; + CAM_ERR(CAM_CPAS, "CPAS probe failed"); + return rc; +} + +static int cam_cpas_dev_remove(struct platform_device *dev) +{ + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return -ENODEV; + } + + mutex_lock(&g_cpas_intf->intf_lock); + g_cpas_intf->probe_done = false; + cam_unregister_subdev(&g_cpas_intf->subdev); + cam_cpas_hw_remove(g_cpas_intf->hw_intf); + mutex_unlock(&g_cpas_intf->intf_lock); + mutex_destroy(&g_cpas_intf->intf_lock); + kfree(g_cpas_intf); + g_cpas_intf = NULL; + + return 0; +} + +static const struct of_device_id cam_cpas_dt_match[] = { + {.compatible = "qcom,cam-cpas"}, + {} +}; + +static struct platform_driver cam_cpas_driver = { + .probe = cam_cpas_dev_probe, + .remove = cam_cpas_dev_remove, + .driver = { + .name = CAM_CPAS_DEV_NAME, + .owner = THIS_MODULE, + .of_match_table = cam_cpas_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_cpas_dev_init_module(void) +{ + return platform_driver_register(&cam_cpas_driver); +} + +static void __exit cam_cpas_dev_exit_module(void) +{ + platform_driver_unregister(&cam_cpas_driver); +} + +module_init(cam_cpas_dev_init_module); +module_exit(cam_cpas_dev_exit_module); +MODULE_DESCRIPTION("MSM CPAS driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_soc.c b/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..2694c5ebaa1dac66cf81b90e982b64b55fbed8bc --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_soc.c @@ -0,0 +1,772 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "cam_cpas_api.h" +#include "cam_cpas_hw_intf.h" +#include "cam_cpas_hw.h" +#include "cam_cpas_soc.h" + +static uint cpas_dump; +module_param(cpas_dump, uint, 0644); + + +void cam_cpas_dump_axi_vote_info( + const struct cam_cpas_client *cpas_client, + const char *identifier, + struct cam_axi_vote *axi_vote) +{ + int i; + + if (!cpas_dump) + return; + + if (!axi_vote || (axi_vote->num_paths > + CAM_CPAS_MAX_PATHS_PER_CLIENT)) { + CAM_ERR(CAM_PERF, "Invalid num_paths %d", + axi_vote ? axi_vote->num_paths : -1); + return; + } + + for (i = 0; i < axi_vote->num_paths; i++) { + CAM_INFO(CAM_PERF, + "Client [%s][%d] : [%s], Path=[%d] [%d], camnoc[%llu], mnoc_ab[%llu], mnoc_ib[%llu]", + cpas_client->data.identifier, cpas_client->data.cell_index, + identifier, + axi_vote->axi_path[i].path_data_type, + axi_vote->axi_path[i].transac_type, + axi_vote->axi_path[i].camnoc_bw, + axi_vote->axi_path[i].mnoc_ab_bw, + axi_vote->axi_path[i].mnoc_ib_bw); + } + +} + +void cam_cpas_util_debug_parse_data( + struct cam_cpas_private_soc *soc_private) +{ + int i, j; + struct cam_cpas_tree_node *curr_node = NULL; + + if (!cpas_dump) + return; + + for (i = 0; i < CAM_CPAS_MAX_TREE_NODES; i++) { + if (!soc_private->tree_node[i]) + break; + + curr_node = soc_private->tree_node[i]; + CAM_INFO(CAM_CPAS, + "NODE cell_idx: %d, level: %d, name: %s, axi_port_idx: %d, merge_type: %d, parent_name: %s", + curr_node->cell_idx, curr_node->level_idx, + curr_node->node_name, curr_node->axi_port_idx, + curr_node->merge_type, curr_node->parent_node ? + curr_node->parent_node->node_name : "no parent"); + + if (curr_node->level_idx) + continue; + + CAM_INFO(CAM_CPAS, "path_type: %d, transac_type: %s", + curr_node->path_data_type, + cam_cpas_axi_util_trans_type_to_string( + curr_node->path_trans_type)); + + for (j = 0; j < CAM_CPAS_PATH_DATA_MAX; j++) { + CAM_INFO(CAM_CPAS, "Constituent path: %d", + curr_node->constituent_paths[j] ? j : -1); + } + } + + CAM_INFO(CAM_CPAS, "NUMBER OF NODES PARSED: %d", i); +} + +int cam_cpas_node_tree_cleanup(struct cam_cpas *cpas_core, + struct cam_cpas_private_soc *soc_private) +{ + int i = 0; + + for (i = 0; i < CAM_CPAS_MAX_TREE_NODES; i++) { + if (soc_private->tree_node[i]) { + of_node_put(soc_private->tree_node[i]->tree_dev_node); + kfree(soc_private->tree_node[i]); + soc_private->tree_node[i] = NULL; + } + } + + for (i = 0; i < CAM_CPAS_MAX_TREE_LEVELS; i++) { + if (soc_private->level_node[i]) { + of_node_put(soc_private->level_node[i]); + soc_private->level_node[i] = NULL; + } + } + + if (soc_private->camera_bus_node) { + of_node_put(soc_private->camera_bus_node); + soc_private->camera_bus_node = NULL; + } + + mutex_destroy(&cpas_core->tree_lock); + + return 0; +} + +static int cam_cpas_util_path_type_to_idx(uint32_t *path_data_type) +{ + if (*path_data_type >= CAM_CPAS_PATH_DATA_CONSO_OFFSET) + *path_data_type = CAM_CPAS_MAX_GRAN_PATHS_PER_CLIENT + + (*path_data_type % CAM_CPAS_MAX_GRAN_PATHS_PER_CLIENT); + else + *path_data_type %= CAM_CPAS_MAX_GRAN_PATHS_PER_CLIENT; + + if (*path_data_type >= CAM_CPAS_PATH_DATA_MAX) { + CAM_ERR(CAM_CPAS, "index Invalid: %d", path_data_type); + return -EINVAL; + } + + return 0; +} + +static int cam_cpas_update_camnoc_node(struct cam_cpas *cpas_core, + struct device_node *curr_node, + struct cam_cpas_tree_node *cpas_node_ptr, + int *camnoc_idx) + +{ + struct device_node *camnoc_node; + int rc; + + camnoc_node = of_find_node_by_name(curr_node, + "qcom,axi-port-camnoc"); + if (camnoc_node) { + + if (*camnoc_idx >= + CAM_CPAS_MAX_AXI_PORTS) { + CAM_ERR(CAM_CPAS, "CAMNOC axi index overshoot %d", + *camnoc_idx); + return -EINVAL; + } + + cpas_core->camnoc_axi_port[*camnoc_idx] + .axi_port_node = camnoc_node; + rc = of_property_read_string( + curr_node, + "qcom,axi-port-name", + &cpas_core->camnoc_axi_port[*camnoc_idx] + .axi_port_name); + + if (rc) { + CAM_ERR(CAM_CPAS, + "fail to read camnoc-port-name rc=%d", + rc); + return rc; + } + cpas_node_ptr->camnoc_axi_port_idx = *camnoc_idx; + cpas_core->num_camnoc_axi_ports++; + (*camnoc_idx)++; + } + return 0; +} + +static int cam_cpas_parse_node_tree(struct cam_cpas *cpas_core, + struct device_node *of_node, struct cam_cpas_private_soc *soc_private) +{ + struct device_node *camera_bus_node; + struct device_node *level_node; + struct device_node *curr_node; + struct device_node *parent_node; + struct device_node *mnoc_node; + int mnoc_idx = 0, camnoc_idx = 0; + uint32_t path_idx; + bool camnoc_max_needed = false; + struct cam_cpas_tree_node *curr_node_ptr = NULL; + struct cam_cpas_client *curr_client = NULL; + const char *client_name = NULL; + uint32_t client_idx = 0, cell_idx = 0, level_idx = 0; + int rc = 0, count = 0, i; + + camera_bus_node = of_find_node_by_name(of_node, "camera-bus-nodes"); + if (!camera_bus_node) { + CAM_ERR(CAM_CPAS, "Camera Bus node not found in cpas DT node"); + return -EINVAL; + } + + soc_private->camera_bus_node = camera_bus_node; + + for_each_available_child_of_node(camera_bus_node, level_node) { + rc = of_property_read_u32(level_node, "level-index", + &level_idx); + if (rc) { + CAM_ERR(CAM_CPAS, "Error raeding level idx rc: %d", rc); + return rc; + } + if (level_idx >= CAM_CPAS_MAX_TREE_LEVELS) { + CAM_ERR(CAM_CPAS, "Invalid level idx: %d", level_idx); + return -EINVAL; + } + + soc_private->level_node[level_idx] = level_node; + camnoc_max_needed = of_property_read_bool(level_node, + "camnoc-max-needed"); + + for_each_available_child_of_node(level_node, curr_node) { + curr_node_ptr = + kzalloc(sizeof(struct cam_cpas_tree_node), + GFP_KERNEL); + if (!curr_node_ptr) + return -ENOMEM; + + curr_node_ptr->tree_dev_node = curr_node; + rc = of_property_read_u32(curr_node, "cell-index", + &curr_node_ptr->cell_idx); + if (rc) { + CAM_ERR(CAM_CPAS, "Node index not found"); + return rc; + } + + if (curr_node_ptr->cell_idx >= + CAM_CPAS_MAX_TREE_NODES) { + CAM_ERR(CAM_CPAS, "Invalid cell idx: %d", + cell_idx); + return -EINVAL; + } + + soc_private->tree_node[curr_node_ptr->cell_idx] = + curr_node_ptr; + curr_node_ptr->level_idx = level_idx; + + rc = of_property_read_string(curr_node, "node-name", + &curr_node_ptr->node_name); + if (rc) { + CAM_ERR(CAM_CPAS, + "failed to read node-name rc=%d", + rc); + return rc; + } + + curr_node_ptr->camnoc_max_needed = camnoc_max_needed; + rc = of_property_read_u32(curr_node, "bus-width-factor", + &curr_node_ptr->bus_width_factor); + if (rc) + curr_node_ptr->bus_width_factor = 1; + + rc = of_property_read_u32(curr_node, + "traffic-merge-type", + &curr_node_ptr->merge_type); + + curr_node_ptr->axi_port_idx = -1; + mnoc_node = of_find_node_by_name(curr_node, + "qcom,axi-port-mnoc"); + if (mnoc_node) { + if (mnoc_idx >= CAM_CPAS_MAX_AXI_PORTS) + return -EINVAL; + + cpas_core->axi_port[mnoc_idx].axi_port_node + = mnoc_node; + rc = of_property_read_string( + curr_node, "qcom,axi-port-name", + &cpas_core->axi_port[mnoc_idx] + .axi_port_name); + if (rc) { + CAM_ERR(CAM_CPAS, + "failed to read mnoc-port-name rc=%d", + rc); + return rc; + } + cpas_core->axi_port + [mnoc_idx].ib_bw_voting_needed + = of_property_read_bool(curr_node, + "ib-bw-voting-needed"); + curr_node_ptr->axi_port_idx = mnoc_idx; + mnoc_idx++; + cpas_core->num_axi_ports++; + } + + if (!soc_private->control_camnoc_axi_clk) { + rc = cam_cpas_update_camnoc_node( + cpas_core, curr_node, curr_node_ptr, + &camnoc_idx); + if (rc) { + CAM_ERR(CAM_CPAS, + "Parse Camnoc port fail"); + return rc; + } + } + + rc = of_property_read_string(curr_node, + "client-name", &client_name); + if (!rc) { + rc = of_property_read_u32(curr_node, + "traffic-data", &curr_node_ptr->path_data_type); + if (rc) { + CAM_ERR(CAM_CPAS, + "Path Data type not found"); + return rc; + } + + rc = cam_cpas_util_path_type_to_idx( + &curr_node_ptr->path_data_type); + if (rc) + return rc; + + rc = of_property_read_u32(curr_node, + "traffic-transaction-type", + &curr_node_ptr->path_trans_type); + if (rc) { + CAM_ERR(CAM_CPAS, + "Path Transac type not found"); + return rc; + } + + if (curr_node_ptr->path_trans_type >= + CAM_CPAS_TRANSACTION_MAX) { + CAM_ERR(CAM_CPAS, + "Invalid transac type: %d", + curr_node_ptr->path_trans_type); + return -EINVAL; + } + + count = of_property_count_u32_elems(curr_node, + "constituent-paths"); + for (i = 0; i < count; i++) { + rc = of_property_read_u32_index( + curr_node, "constituent-paths", + i, &path_idx); + if (rc) { + CAM_ERR(CAM_CPAS, + "No constituent path at %d", i); + return rc; + } + + rc = cam_cpas_util_path_type_to_idx( + &path_idx); + if (rc) + return rc; + + curr_node_ptr->constituent_paths + [path_idx] = true; + } + + rc = cam_common_util_get_string_index( + soc_private->client_name, + soc_private->num_clients, + client_name, &client_idx); + if (rc) { + CAM_ERR(CAM_CPAS, + "client name not found in list: %s", + client_name); + return rc; + } + + if (client_idx >= CAM_CPAS_MAX_CLIENTS) + return -EINVAL; + + curr_client = + cpas_core->cpas_client[client_idx]; + curr_client->tree_node_valid = true; + curr_client->tree_node + [curr_node_ptr->path_data_type] + [curr_node_ptr->path_trans_type] = + curr_node_ptr; + CAM_DBG(CAM_CPAS, + "CLIENT NODE ADDED: %d %d %s", + curr_node_ptr->path_data_type, + curr_node_ptr->path_trans_type, + client_name); + } + + parent_node = of_parse_phandle(curr_node, + "parent-node", 0); + if (parent_node) { + of_property_read_u32(parent_node, "cell-index", + &cell_idx); + curr_node_ptr->parent_node = + soc_private->tree_node[cell_idx]; + } else { + CAM_DBG(CAM_CPAS, + "no parent node at this level"); + } + } + } + mutex_init(&cpas_core->tree_lock); + cam_cpas_util_debug_parse_data(soc_private); + + return 0; +} + +int cam_cpas_get_hw_features(struct platform_device *pdev, + struct cam_cpas_private_soc *soc_private) +{ + struct device_node *of_node; + void *fuse; + uint32_t fuse_addr, fuse_bit; + uint32_t fuse_val = 0, feature; + uint32_t enable_type = 0, hw_id = 0; + int count = 0, i = 0, num_feature = 0; + + of_node = pdev->dev.of_node; + count = of_property_count_u32_elems(of_node, "cam_hw_fuse"); + + CAM_DBG(CAM_CPAS, "fuse info elements count %d", count); + + if (count <= 0) + goto end; + + for (i = 0; (i + 5) <= count; i = i + 5) { + of_property_read_u32_index(of_node, "cam_hw_fuse", i, + &feature); + of_property_read_u32_index(of_node, "cam_hw_fuse", i + 1, + &fuse_addr); + of_property_read_u32_index(of_node, "cam_hw_fuse", i + 2, + &fuse_bit); + of_property_read_u32_index(of_node, "cam_hw_fuse", i + 3, + &enable_type); + of_property_read_u32_index(of_node, "cam_hw_fuse", i + 4, + &hw_id); + CAM_INFO(CAM_CPAS, + "feature 0x%x addr 0x%x, bit %d enable type:%d hw_id=%d", + feature, fuse_addr, fuse_bit, + enable_type, hw_id); + + fuse = ioremap(fuse_addr, 4); + if (fuse) { + fuse_val = cam_io_r(fuse); + } else { + /* if fuse ioremap is failed, disable the feature */ + CAM_ERR(CAM_CPAS, + "fuse register io remap failed fuse_addr:0x%x feature0x%x ", + fuse_addr, feature); + + if (enable_type) + fuse_val = ~BIT(fuse_bit); + else + fuse_val = BIT(fuse_bit); + } + + soc_private->feature_info[num_feature].feature = + feature; + soc_private->feature_info[num_feature].hw_id = hw_id; + + if (enable_type) { + /* + * fuse is for enable feature + * if fust bit is set means feature is enabled or + * HW is enabled + */ + if (fuse_val & BIT(fuse_bit)) + soc_private->feature_info[num_feature].enable = + true; + else + soc_private->feature_info[num_feature].enable = + false; + } else { + /* + * fuse is for disable feature + * if fust bit is set means feature is disabled or + * HW is disabled + */ + if (fuse_val & BIT(fuse_bit)) + soc_private->feature_info[num_feature].enable = + false; + else + soc_private->feature_info[num_feature].enable = + true; + } + CAM_INFO(CAM_CPAS, + "num entries:%d feature 0x%x enable=%d hw id=%d", + num_feature, + soc_private->feature_info[num_feature].feature, + soc_private->feature_info[num_feature].enable, + soc_private->feature_info[num_feature].hw_id); + num_feature++; + } + +end: + soc_private->num_feature_entries = num_feature; + return 0; +} + +int cam_cpas_get_custom_dt_info(struct cam_hw_info *cpas_hw, + struct platform_device *pdev, struct cam_cpas_private_soc *soc_private) +{ + struct device_node *of_node; + int count = 0, i = 0, rc = 0; + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + + if (!soc_private || !pdev) { + CAM_ERR(CAM_CPAS, "invalid input arg %pK %pK", + soc_private, pdev); + return -EINVAL; + } + + of_node = pdev->dev.of_node; + soc_private->num_feature_entries = 0; + rc = of_property_read_string(of_node, "arch-compat", + &soc_private->arch_compat); + if (rc) { + CAM_ERR(CAM_CPAS, "device %s failed to read arch-compat", + pdev->name); + return rc; + } + + cam_cpas_get_hw_features(pdev, soc_private); + + soc_private->camnoc_axi_min_ib_bw = 0; + rc = of_property_read_u64(of_node, + "camnoc-axi-min-ib-bw", + &soc_private->camnoc_axi_min_ib_bw); + if (rc == -EOVERFLOW) { + soc_private->camnoc_axi_min_ib_bw = 0; + rc = of_property_read_u32(of_node, + "camnoc-axi-min-ib-bw", + (u32 *)&soc_private->camnoc_axi_min_ib_bw); + } + + soc_private->custom_id = 0; + rc = of_property_read_u32(of_node, + "custom-id", + &soc_private->custom_id); + if (rc) { + CAM_DBG(CAM_CPAS, + "failed to read camnoc-axi-min-ib-bw rc:%d", rc); + soc_private->camnoc_axi_min_ib_bw = + CAM_CPAS_AXI_MIN_CAMNOC_IB_BW; + } + + CAM_DBG(CAM_CPAS, "camnoc-axi-min-ib-bw = %llu", + soc_private->camnoc_axi_min_ib_bw); + + soc_private->client_id_based = of_property_read_bool(of_node, + "client-id-based"); + + count = of_property_count_strings(of_node, "client-names"); + if (count <= 0) { + CAM_ERR(CAM_CPAS, "no client-names found"); + count = 0; + return -EINVAL; + } else if (count > CAM_CPAS_MAX_CLIENTS) { + CAM_ERR(CAM_CPAS, "Number of clients %d greater than max %d", + count, CAM_CPAS_MAX_CLIENTS); + count = 0; + return -EINVAL; + } + + soc_private->num_clients = count; + CAM_DBG(CAM_CPAS, + "arch-compat=%s, client_id_based = %d, num_clients=%d", + soc_private->arch_compat, soc_private->client_id_based, + soc_private->num_clients); + + for (i = 0; i < soc_private->num_clients; i++) { + rc = of_property_read_string_index(of_node, + "client-names", i, &soc_private->client_name[i]); + if (rc) { + CAM_ERR(CAM_CPAS, "no client-name at cnt=%d", i); + return -EINVAL; + } + + cpas_core->cpas_client[i] = + kzalloc(sizeof(struct cam_cpas_client), GFP_KERNEL); + if (!cpas_core->cpas_client[i]) { + rc = -ENOMEM; + goto cleanup_clients; + } + + CAM_DBG(CAM_CPAS, "Client[%d] : %s", i, + soc_private->client_name[i]); + } + + soc_private->control_camnoc_axi_clk = of_property_read_bool(of_node, + "control-camnoc-axi-clk"); + + if (soc_private->control_camnoc_axi_clk == true) { + rc = of_property_read_u32(of_node, "camnoc-bus-width", + &soc_private->camnoc_bus_width); + if (rc || (soc_private->camnoc_bus_width == 0)) { + CAM_ERR(CAM_CPAS, "Bus width not found rc=%d, %d", + rc, soc_private->camnoc_bus_width); + goto cleanup_clients; + } + + rc = of_property_read_u32(of_node, + "camnoc-axi-clk-bw-margin-perc", + &soc_private->camnoc_axi_clk_bw_margin); + + if (rc) { + /* this is not fatal, overwrite rc */ + rc = 0; + soc_private->camnoc_axi_clk_bw_margin = 0; + } + } + + CAM_DBG(CAM_CPAS, + "control_camnoc_axi_clk=%d, width=%d, margin=%d", + soc_private->control_camnoc_axi_clk, + soc_private->camnoc_bus_width, + soc_private->camnoc_axi_clk_bw_margin); + + count = of_property_count_u32_elems(of_node, "vdd-corners"); + if ((count > 0) && (count <= CAM_REGULATOR_LEVEL_MAX) && + (of_property_count_strings(of_node, "vdd-corner-ahb-mapping") == + count)) { + const char *ahb_string; + + for (i = 0; i < count; i++) { + rc = of_property_read_u32_index(of_node, "vdd-corners", + i, &soc_private->vdd_ahb[i].vdd_corner); + if (rc) { + CAM_ERR(CAM_CPAS, + "vdd-corners failed at index=%d", i); + rc = -ENODEV; + goto cleanup_clients; + } + + rc = of_property_read_string_index(of_node, + "vdd-corner-ahb-mapping", i, &ahb_string); + if (rc) { + CAM_ERR(CAM_CPAS, + "no ahb-mapping at index=%d", i); + rc = -ENODEV; + goto cleanup_clients; + } + + rc = cam_soc_util_get_level_from_string(ahb_string, + &soc_private->vdd_ahb[i].ahb_level); + if (rc) { + CAM_ERR(CAM_CPAS, + "invalid ahb-string at index=%d", i); + rc = -EINVAL; + goto cleanup_clients; + } + + CAM_DBG(CAM_CPAS, + "Vdd-AHB mapping [%d] : [%d] [%s] [%d]", i, + soc_private->vdd_ahb[i].vdd_corner, + ahb_string, soc_private->vdd_ahb[i].ahb_level); + } + + soc_private->num_vdd_ahb_mapping = count; + } + + rc = cam_cpas_parse_node_tree(cpas_core, of_node, soc_private); + if (rc) { + CAM_ERR(CAM_CPAS, "Node tree parsing failed rc: %d", rc); + goto cleanup_tree; + } + + of_property_read_u32(of_node, "qcom,cx-ipeak-gpu-limit", + &soc_private->cx_ipeak_gpu_limit); + + return 0; + +cleanup_tree: + cam_cpas_node_tree_cleanup(cpas_core, soc_private); +cleanup_clients: + cam_cpas_util_client_cleanup(cpas_hw); + return rc; +} + +int cam_cpas_soc_init_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t irq_handler, struct cam_hw_info *cpas_hw) +{ + int rc = 0; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc) { + CAM_ERR(CAM_CPAS, "failed in get_dt_properties, rc=%d", rc); + return rc; + } + + if (soc_info->irq_line && !irq_handler) { + CAM_ERR(CAM_CPAS, "Invalid IRQ handler"); + return -EINVAL; + } + + rc = cam_soc_util_request_platform_resource(soc_info, irq_handler, + cpas_hw); + if (rc) { + CAM_ERR(CAM_CPAS, "failed in request_platform_resource, rc=%d", + rc); + return rc; + } + + soc_info->soc_private = kzalloc(sizeof(struct cam_cpas_private_soc), + GFP_KERNEL); + if (!soc_info->soc_private) { + rc = -ENOMEM; + goto release_res; + } + + rc = cam_cpas_get_custom_dt_info(cpas_hw, soc_info->pdev, + soc_info->soc_private); + if (rc) { + CAM_ERR(CAM_CPAS, "failed in get_custom_info, rc=%d", rc); + goto free_soc_private; + } + + return rc; + +free_soc_private: + kfree(soc_info->soc_private); +release_res: + cam_soc_util_release_platform_resource(soc_info); + return rc; +} + +int cam_cpas_soc_deinit_resources(struct cam_hw_soc_info *soc_info) +{ + int rc; + + rc = cam_soc_util_release_platform_resource(soc_info); + if (rc) + CAM_ERR(CAM_CPAS, "release platform failed, rc=%d", rc); + + kfree(soc_info->soc_private); + soc_info->soc_private = NULL; + + return rc; +} + +int cam_cpas_soc_enable_resources(struct cam_hw_soc_info *soc_info, + enum cam_vote_level default_level) +{ + int rc = 0; + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + default_level, true); + if (rc) + CAM_ERR(CAM_CPAS, "enable platform resource failed, rc=%d", rc); + + return rc; +} + +int cam_cpas_soc_disable_resources(struct cam_hw_soc_info *soc_info, + bool disable_clocks, bool disable_irq) +{ + int rc = 0; + + rc = cam_soc_util_disable_platform_resource(soc_info, + disable_clocks, disable_irq); + if (rc) + CAM_ERR(CAM_CPAS, "disable platform failed, rc=%d", rc); + + return rc; +} + +int cam_cpas_soc_disable_irq(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + + rc = cam_soc_util_irq_disable(soc_info); + if (rc) + CAM_ERR(CAM_CPAS, "disable irq failed, rc=%d", rc); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_soc.h b/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..c1e65803aff851a1c398bed501fa63fd94a2bf83 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cam_cpas_soc.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CPAS_SOC_H_ +#define _CAM_CPAS_SOC_H_ + +#include +#include "cam_soc_util.h" +#include "cam_cpas_hw.h" + +#define CAM_REGULATOR_LEVEL_MAX 16 +#define CAM_CPAS_MAX_TREE_NODES 50 +#define CAM_CPAS_MAX_FUSE_FEATURE 10 +/** + * struct cam_cpas_vdd_ahb_mapping : Voltage to ahb level mapping + * + * @vdd_corner : Voltage corner value + * @ahb_level : AHB vote level corresponds to this vdd_corner + * + */ +struct cam_cpas_vdd_ahb_mapping { + unsigned int vdd_corner; + enum cam_vote_level ahb_level; +}; + +/** + * struct cpas_tree_node: Generic cpas tree node for BW voting + * + * @cell_idx: Index to identify node from device tree and its parent + * @level_idx: Index to identify at what level the node is present + * @axi_port_idx: Index to identify which axi port to vote the consolidated bw + * @camnoc_axi_port_idx: Index to find which axi port to vote consolidated bw + * @path_data_type: Traffic type info from device tree (ife-vid, ife-disp etc) + * @path_trans_type: Transaction type info from device tree (rd, wr) + * @merge_type: Traffic merge type (calculation info) from device tree + * @bus_width_factor: Factor for accounting bus width in CAMNOC bw calculation + * @camnoc_bw: CAMNOC bw value at current node + * @mnoc_ab_bw: MNOC AB bw value at current node + * @mnoc_ib_bw: MNOC IB bw value at current node + * @ddr_ab_bw: DDR AB bw value at current node + * @ddr_ib_bw: DDR IB bw value at current node + * @camnoc_max_needed: If node is needed for CAMNOC BW calculation then true + * @constituent_paths: Constituent paths presence info from device tree + * Ex: For CAM_CPAS_PATH_DATA_IFE_UBWC_STATS, index corresponding to + * CAM_CPAS_PATH_DATA_IFE_VID, CAM_CPAS_PATH_DATA_IFE_DISP and + * CAM_CPAS_PATH_DATA_IFE_STATS + * @tree_dev_node: Device node from devicetree for current tree node + * @parent_node: Pointer to node one or more level above the current level + * (starting from end node of cpas client) + * + */ +struct cam_cpas_tree_node { + uint32_t cell_idx; + uint32_t level_idx; + int axi_port_idx; + int camnoc_axi_port_idx; + const char *node_name; + uint32_t path_data_type; + uint32_t path_trans_type; + uint32_t merge_type; + uint32_t bus_width_factor; + uint64_t camnoc_bw; + uint64_t mnoc_ab_bw; + uint64_t mnoc_ib_bw; + uint64_t ddr_ab_bw; + uint64_t ddr_ib_bw; + bool camnoc_max_needed; + bool constituent_paths[CAM_CPAS_PATH_DATA_MAX]; + struct device_node *tree_dev_node; + struct cam_cpas_tree_node *parent_node; +}; + +/** + * struct cam_cpas_feature_info : Fuse feature information + * + * @feature : feature + * @enable : feature is enabled or disabled + * @hw_id : hw id for this feature, it will be zero + * if not applicable + * + */ +struct cam_cpas_feature_info { + uint32_t feature; + uint32_t enable; + uint32_t hw_id; +}; + +/** + * struct cam_cpas_private_soc : CPAS private DT info + * + * @arch_compat: ARCH compatible string + * @client_id_based: Whether clients are id based + * @num_clients: Number of clients supported + * @client_name: Client names + * @tree_node: Array of pointers to all tree nodes required to calculate + * axi bw, arranged with help of cell index in device tree + * @camera_bus_node: Device tree node from cpas node + * @level_node: Device tree node for each level in camera_bus_node + * @num_vdd_ahb_mapping : Number of vdd to ahb level mapping supported + * @vdd_ahb : AHB level mapping info for the supported vdd levels + * @control_camnoc_axi_clk : Whether CPAS driver need to set camnoc axi clk freq + * @camnoc_bus_width : CAMNOC Bus width + * @camnoc_axi_clk_bw_margin : BW Margin in percentage to add while calculating + * camnoc axi clock + * @camnoc_axi_min_ib_bw: Min camnoc BW which varies based on target + * @num_feature_entries: number of feature entries + * @feature_info: fuse based feature info for hw supported features + * @cx_ipeak_gpu_limit: Flag for Cx Ipeak GPU mitigation + * @gpu_pwr_limit: Handle for Cx Ipeak GPU Mitigation + * @custom_id: Custom id to differentiate between target if + * cpas version is same + * + */ +struct cam_cpas_private_soc { + const char *arch_compat; + bool client_id_based; + uint32_t num_clients; + const char *client_name[CAM_CPAS_MAX_CLIENTS]; + struct cam_cpas_tree_node *tree_node[CAM_CPAS_MAX_TREE_NODES]; + struct device_node *camera_bus_node; + struct device_node *level_node[CAM_CPAS_MAX_TREE_LEVELS]; + uint32_t num_vdd_ahb_mapping; + struct cam_cpas_vdd_ahb_mapping vdd_ahb[CAM_REGULATOR_LEVEL_MAX]; + bool control_camnoc_axi_clk; + uint32_t camnoc_bus_width; + uint32_t camnoc_axi_clk_bw_margin; + uint64_t camnoc_axi_min_ib_bw; + uint32_t num_feature_entries; + struct cam_cpas_feature_info feature_info[CAM_CPAS_MAX_FUSE_FEATURE]; + uint32_t cx_ipeak_gpu_limit; + struct kgsl_pwr_limit *gpu_pwr_limit; + uint32_t custom_id; +}; + +void cam_cpas_util_debug_parse_data(struct cam_cpas_private_soc *soc_private); +void cam_cpas_dump_axi_vote_info( + const struct cam_cpas_client *cpas_client, + const char *identifier, + struct cam_axi_vote *axi_vote); +int cam_cpas_node_tree_cleanup(struct cam_cpas *cpas_core, + struct cam_cpas_private_soc *soc_private); +int cam_cpas_soc_init_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t vfe_irq_handler, struct cam_hw_info *cpas_hw); +int cam_cpas_soc_deinit_resources(struct cam_hw_soc_info *soc_info); +int cam_cpas_soc_enable_resources(struct cam_hw_soc_info *soc_info, + enum cam_vote_level default_level); +int cam_cpas_soc_disable_resources(struct cam_hw_soc_info *soc_info, + bool disable_clocks, bool disable_irq); +int cam_cpas_soc_disable_irq(struct cam_hw_soc_info *soc_info); +#endif /* _CAM_CPAS_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/camss_top/Makefile b/techpack/camera-bengal/drivers/cam_cpas/camss_top/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..6affe66e32da8f217d9617177332b7a49102fc6e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/camss_top/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_camsstop_hw.o diff --git a/techpack/camera-bengal/drivers/cam_cpas/camss_top/cam_camsstop_hw.c b/techpack/camera-bengal/drivers/cam_cpas/camss_top/cam_camsstop_hw.c new file mode 100644 index 0000000000000000000000000000000000000000..b7f3550bc6324d9f8f444ecf4711c88a86acef9f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/camss_top/cam_camsstop_hw.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#include "cam_cpas_hw_intf.h" +#include "cam_cpas_hw.h" +#include "cam_cpas_soc.h" + +int cam_camsstop_get_hw_info(struct cam_hw_info *cpas_hw, + struct cam_cpas_hw_caps *hw_caps) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; + int32_t reg_indx = cpas_core->regbase_index[CAM_CPAS_REG_CAMSS]; + uint32_t reg_value; + + if (reg_indx == -1) + return -EINVAL; + + hw_caps->camera_family = CAM_FAMILY_CAMERA_SS; + + reg_value = cam_io_r_mb(soc_info->reg_map[reg_indx].mem_base + 0x0); + hw_caps->camera_version.major = + CAM_BITS_MASK_SHIFT(reg_value, 0xf0000000, 0x1c); + hw_caps->camera_version.minor = + CAM_BITS_MASK_SHIFT(reg_value, 0xfff0000, 0x10); + hw_caps->camera_version.incr = + CAM_BITS_MASK_SHIFT(reg_value, 0xffff, 0x0); + + CAM_DBG(CAM_FD, "Family %d, version %d.%d.%d", + hw_caps->camera_family, hw_caps->camera_version.major, + hw_caps->camera_version.minor, hw_caps->camera_version.incr); + + return 0; +} + +int cam_camsstop_setup_regbase_indices(struct cam_hw_soc_info *soc_info, + int32_t regbase_index[], int32_t num_reg_map) +{ + uint32_t index; + int rc; + + if (num_reg_map > CAM_CPAS_REG_MAX) { + CAM_ERR(CAM_CPAS, "invalid num_reg_map=%d", num_reg_map); + return -EINVAL; + } + + if (soc_info->num_mem_block > CAM_SOC_MAX_BLOCK) { + CAM_ERR(CAM_CPAS, "invalid num_mem_block=%d", + soc_info->num_mem_block); + return -EINVAL; + } + + rc = cam_common_util_get_string_index(soc_info->mem_block_name, + soc_info->num_mem_block, "cam_camss", &index); + if ((rc == 0) && (index < num_reg_map)) { + regbase_index[CAM_CPAS_REG_CAMSS] = index; + } else { + CAM_ERR(CAM_CPAS, "regbase not found for CAM_CPAS_REG_CAMSS"); + return -EINVAL; + } + + return 0; +} + +int cam_camsstop_get_internal_ops(struct cam_cpas_internal_ops *internal_ops) +{ + if (!internal_ops) { + CAM_ERR(CAM_CPAS, "invalid NULL param"); + return -EINVAL; + } + + internal_ops->get_hw_info = cam_camsstop_get_hw_info; + internal_ops->init_hw_version = NULL; + internal_ops->handle_irq = NULL; + internal_ops->setup_regbase = cam_camsstop_setup_regbase_indices; + internal_ops->power_on = NULL; + internal_ops->power_off = NULL; + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/Makefile b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..69d905c01d866966d75068c1aeaffd7592936c6d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_cpastop_hw.o diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c new file mode 100644 index 0000000000000000000000000000000000000000..c8d96bd3672efe03fe79830a7d9d9dcf4fe671a2 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c @@ -0,0 +1,693 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include + +#include + +#include "cam_cpas_hw_intf.h" +#include "cam_cpas_hw.h" +#include "cam_cpastop_hw.h" +#include "cam_io_util.h" +#include "cam_cpas_soc.h" +#include "cpastop100.h" +#include "cpastop_v150_100.h" +#include "cpastop_v170_110.h" +#include "cpastop_v175_100.h" +#include "cpastop_v175_101.h" +#include "cpastop_v175_120.h" +#include "cpastop_v175_130.h" +#include "cpastop_v480_100.h" +#include "cpastop_v540_100.h" +#include "cpastop_v520_100.h" +#include "cpastop_v545_110_518.h" +#include "cam_req_mgr_workq.h" + +struct cam_camnoc_info *camnoc_info; + +#define CAMNOC_SLAVE_MAX_ERR_CODE 7 +static const char * const camnoc_salve_err_code[] = { + "Target Error", /* err code 0 */ + "Address decode error", /* err code 1 */ + "Unsupported request", /* err code 2 */ + "Disconnected target", /* err code 3 */ + "Security violation", /* err code 4 */ + "Hidden security violation", /* err code 5 */ + "Timeout Error", /* err code 6 */ + "Unknown Error", /* unknown err code */ +}; + +static int cam_cpastop_get_hw_info(struct cam_hw_info *cpas_hw, + struct cam_cpas_hw_caps *hw_caps) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; + int32_t reg_indx = cpas_core->regbase_index[CAM_CPAS_REG_CPASTOP]; + uint32_t reg_value; + + if (reg_indx == -1) + return -EINVAL; + + hw_caps->camera_family = CAM_FAMILY_CPAS_SS; + + reg_value = cam_io_r_mb(soc_info->reg_map[reg_indx].mem_base + 0x0); + hw_caps->camera_version.major = + CAM_BITS_MASK_SHIFT(reg_value, 0xff0000, 0x10); + hw_caps->camera_version.minor = + CAM_BITS_MASK_SHIFT(reg_value, 0xff00, 0x8); + hw_caps->camera_version.incr = + CAM_BITS_MASK_SHIFT(reg_value, 0xff, 0x0); + + reg_value = cam_io_r_mb(soc_info->reg_map[reg_indx].mem_base + 0x4); + hw_caps->cpas_version.major = + CAM_BITS_MASK_SHIFT(reg_value, 0xf0000000, 0x1c); + hw_caps->cpas_version.minor = + CAM_BITS_MASK_SHIFT(reg_value, 0xfff0000, 0x10); + hw_caps->cpas_version.incr = + CAM_BITS_MASK_SHIFT(reg_value, 0xffff, 0x0); + + reg_value = cam_io_r_mb(soc_info->reg_map[reg_indx].mem_base + 0x8); + hw_caps->camera_capability = reg_value; + + CAM_DBG(CAM_FD, "Family %d, version %d.%d.%d, cpas %d.%d.%d, cap 0x%x", + hw_caps->camera_family, hw_caps->camera_version.major, + hw_caps->camera_version.minor, hw_caps->camera_version.incr, + hw_caps->cpas_version.major, hw_caps->cpas_version.minor, + hw_caps->cpas_version.incr, hw_caps->camera_capability); + + soc_info->hw_version = CAM_CPAS_TITAN_NONE; + + if ((hw_caps->camera_version.major == 1) && + (hw_caps->camera_version.minor == 7) && + (hw_caps->camera_version.incr == 0)) { + if ((hw_caps->cpas_version.major == 1) && + (hw_caps->cpas_version.minor == 0) && + (hw_caps->cpas_version.incr == 0)) + soc_info->hw_version = CAM_CPAS_TITAN_170_V100; + else if ((hw_caps->cpas_version.major == 1) && + (hw_caps->cpas_version.minor == 1) && + (hw_caps->cpas_version.incr == 0)) + soc_info->hw_version = CAM_CPAS_TITAN_170_V110; + else if ((hw_caps->cpas_version.major == 1) && + (hw_caps->cpas_version.minor == 2) && + (hw_caps->cpas_version.incr == 0)) + soc_info->hw_version = CAM_CPAS_TITAN_170_V120; + } else if ((hw_caps->camera_version.major == 1) && + (hw_caps->camera_version.minor == 7) && + (hw_caps->camera_version.incr == 5)) { + if ((hw_caps->cpas_version.major == 1) && + (hw_caps->cpas_version.minor == 0) && + (hw_caps->cpas_version.incr == 0)) + soc_info->hw_version = CAM_CPAS_TITAN_175_V100; + else if ((hw_caps->cpas_version.major == 1) && + (hw_caps->cpas_version.minor == 0) && + (hw_caps->cpas_version.incr == 1)) + soc_info->hw_version = CAM_CPAS_TITAN_175_V101; + else if ((hw_caps->cpas_version.major == 1) && + (hw_caps->cpas_version.minor == 2) && + (hw_caps->cpas_version.incr == 0)) + soc_info->hw_version = CAM_CPAS_TITAN_175_V120; + else if ((hw_caps->cpas_version.major == 1) && + (hw_caps->cpas_version.minor == 3) && + (hw_caps->cpas_version.incr == 0)) + soc_info->hw_version = CAM_CPAS_TITAN_175_V130; + } else if ((hw_caps->camera_version.major == 1) && + (hw_caps->camera_version.minor == 5) && + (hw_caps->camera_version.incr == 0)) { + if ((hw_caps->cpas_version.major == 1) && + (hw_caps->cpas_version.minor == 0) && + (hw_caps->cpas_version.incr == 0)) + soc_info->hw_version = CAM_CPAS_TITAN_150_V100; + } else if ((hw_caps->camera_version.major == 4) && + (hw_caps->camera_version.minor == 8) && + (hw_caps->camera_version.incr == 0)) { + soc_info->hw_version = CAM_CPAS_TITAN_480_V100; + } else if ((hw_caps->camera_version.major == 5) && + (hw_caps->camera_version.minor == 4) && + (hw_caps->camera_version.incr == 0)) { + soc_info->hw_version = CAM_CPAS_TITAN_540_V100; + } else if ((hw_caps->camera_version.major == 5) && + (hw_caps->camera_version.minor == 2) && + (hw_caps->camera_version.incr == 0)) { + soc_info->hw_version = CAM_CPAS_TITAN_520_V100; + } else if ((hw_caps->camera_version.major == 5) && + (hw_caps->camera_version.minor == 4) && + (hw_caps->camera_version.incr == 5)) { + if ((hw_caps->cpas_version.major == 1) && + (hw_caps->cpas_version.minor == 1) && + (hw_caps->cpas_version.incr == 0)) { + soc_info->hw_version = CAM_CPAS_TITAN_545_V110; + } + } + + CAM_DBG(CAM_CPAS, "CPAS HW VERSION %x", soc_info->hw_version); + + return 0; +} + +static int cam_cpastop_setup_regbase_indices(struct cam_hw_soc_info *soc_info, + int32_t regbase_index[], int32_t num_reg_map) +{ + uint32_t index; + int rc; + + if (num_reg_map > CAM_CPAS_REG_MAX) { + CAM_ERR(CAM_CPAS, "invalid num_reg_map=%d", num_reg_map); + return -EINVAL; + } + + if (soc_info->num_mem_block > CAM_SOC_MAX_BLOCK) { + CAM_ERR(CAM_CPAS, "invalid num_mem_block=%d", + soc_info->num_mem_block); + return -EINVAL; + } + + rc = cam_common_util_get_string_index(soc_info->mem_block_name, + soc_info->num_mem_block, "cam_cpas_top", &index); + if ((rc == 0) && (index < num_reg_map)) { + regbase_index[CAM_CPAS_REG_CPASTOP] = index; + } else { + CAM_ERR(CAM_CPAS, "regbase not found for CPASTOP, rc=%d, %d %d", + rc, index, num_reg_map); + return -EINVAL; + } + + rc = cam_common_util_get_string_index(soc_info->mem_block_name, + soc_info->num_mem_block, "cam_camnoc", &index); + if ((rc == 0) && (index < num_reg_map)) { + regbase_index[CAM_CPAS_REG_CAMNOC] = index; + } else { + CAM_ERR(CAM_CPAS, "regbase not found for CAMNOC, rc=%d, %d %d", + rc, index, num_reg_map); + return -EINVAL; + } + + return 0; +} + +static int cam_cpastop_handle_errlogger(struct cam_cpas *cpas_core, + struct cam_hw_soc_info *soc_info, + struct cam_camnoc_irq_slave_err_data *slave_err) +{ + int camnoc_index = cpas_core->regbase_index[CAM_CPAS_REG_CAMNOC]; + int err_code_index = 0; + + if (!camnoc_info->err_logger) { + CAM_ERR_RATE_LIMIT(CAM_CPAS, "Invalid err logger info"); + return -EINVAL; + } + + slave_err->mainctrl.value = cam_io_r_mb( + soc_info->reg_map[camnoc_index].mem_base + + camnoc_info->err_logger->mainctrl); + + slave_err->errvld.value = cam_io_r_mb( + soc_info->reg_map[camnoc_index].mem_base + + camnoc_info->err_logger->errvld); + + slave_err->errlog0_low.value = cam_io_r_mb( + soc_info->reg_map[camnoc_index].mem_base + + camnoc_info->err_logger->errlog0_low); + + slave_err->errlog0_high.value = cam_io_r_mb( + soc_info->reg_map[camnoc_index].mem_base + + camnoc_info->err_logger->errlog0_high); + + slave_err->errlog1_low.value = cam_io_r_mb( + soc_info->reg_map[camnoc_index].mem_base + + camnoc_info->err_logger->errlog1_low); + + slave_err->errlog1_high.value = cam_io_r_mb( + soc_info->reg_map[camnoc_index].mem_base + + camnoc_info->err_logger->errlog1_high); + + slave_err->errlog2_low.value = cam_io_r_mb( + soc_info->reg_map[camnoc_index].mem_base + + camnoc_info->err_logger->errlog2_low); + + slave_err->errlog2_high.value = cam_io_r_mb( + soc_info->reg_map[camnoc_index].mem_base + + camnoc_info->err_logger->errlog2_high); + + slave_err->errlog3_low.value = cam_io_r_mb( + soc_info->reg_map[camnoc_index].mem_base + + camnoc_info->err_logger->errlog3_low); + + slave_err->errlog3_high.value = cam_io_r_mb( + soc_info->reg_map[camnoc_index].mem_base + + camnoc_info->err_logger->errlog3_high); + + CAM_ERR_RATE_LIMIT(CAM_CPAS, + "Possible memory configuration issue, fault at SMMU raised as CAMNOC SLAVE_IRQ"); + + CAM_ERR_RATE_LIMIT(CAM_CPAS, + "mainctrl[0x%x 0x%x] errvld[0x%x 0x%x] stall_en=%d, fault_en=%d, err_vld=%d", + camnoc_info->err_logger->mainctrl, + slave_err->mainctrl.value, + camnoc_info->err_logger->errvld, + slave_err->errvld.value, + slave_err->mainctrl.stall_en, + slave_err->mainctrl.fault_en, + slave_err->errvld.err_vld); + + err_code_index = slave_err->errlog0_low.err_code; + if (err_code_index > CAMNOC_SLAVE_MAX_ERR_CODE) + err_code_index = CAMNOC_SLAVE_MAX_ERR_CODE; + + CAM_ERR_RATE_LIMIT(CAM_CPAS, + "errlog0 low[0x%x 0x%x] high[0x%x 0x%x] loginfo_vld=%d, word_error=%d, non_secure=%d, device=%d, opc=%d, err_code=%d(%s) sizef=%d, addr_space=%d, len1=%d", + camnoc_info->err_logger->errlog0_low, + slave_err->errlog0_low.value, + camnoc_info->err_logger->errlog0_high, + slave_err->errlog0_high.value, + slave_err->errlog0_low.loginfo_vld, + slave_err->errlog0_low.word_error, + slave_err->errlog0_low.non_secure, + slave_err->errlog0_low.device, + slave_err->errlog0_low.opc, + slave_err->errlog0_low.err_code, + camnoc_salve_err_code[err_code_index], + slave_err->errlog0_low.sizef, + slave_err->errlog0_low.addr_space, + slave_err->errlog0_high.len1); + + CAM_ERR_RATE_LIMIT(CAM_CPAS, + "errlog1_low[0x%x 0x%x] errlog1_high[0x%x 0x%x] errlog2_low[0x%x 0x%x] errlog2_high[0x%x 0x%x] errlog3_low[0x%x 0x%x] errlog3_high[0x%x 0x%x]", + camnoc_info->err_logger->errlog1_low, + slave_err->errlog1_low.value, + camnoc_info->err_logger->errlog1_high, + slave_err->errlog1_high.value, + camnoc_info->err_logger->errlog2_low, + slave_err->errlog2_low.value, + camnoc_info->err_logger->errlog2_high, + slave_err->errlog2_high.value, + camnoc_info->err_logger->errlog3_low, + slave_err->errlog3_low.value, + camnoc_info->err_logger->errlog3_high, + slave_err->errlog3_high.value); + + return 0; +} + +static int cam_cpastop_handle_ubwc_enc_err(struct cam_cpas *cpas_core, + struct cam_hw_soc_info *soc_info, int i, + struct cam_camnoc_irq_ubwc_enc_data *enc_err) +{ + int camnoc_index = cpas_core->regbase_index[CAM_CPAS_REG_CAMNOC]; + + enc_err->encerr_status.value = + cam_io_r_mb(soc_info->reg_map[camnoc_index].mem_base + + camnoc_info->irq_err[i].err_status.offset); + + /* Let clients handle the UBWC errors */ + CAM_DBG(CAM_CPAS, + "ubwc enc err [%d]: offset[0x%x] value[0x%x]", + i, camnoc_info->irq_err[i].err_status.offset, + enc_err->encerr_status.value); + + return 0; +} + +static int cam_cpastop_handle_ubwc_dec_err(struct cam_cpas *cpas_core, + struct cam_hw_soc_info *soc_info, int i, + struct cam_camnoc_irq_ubwc_dec_data *dec_err) +{ + int camnoc_index = cpas_core->regbase_index[CAM_CPAS_REG_CAMNOC]; + + dec_err->decerr_status.value = + cam_io_r_mb(soc_info->reg_map[camnoc_index].mem_base + + camnoc_info->irq_err[i].err_status.offset); + + /* Let clients handle the UBWC errors */ + CAM_DBG(CAM_CPAS, + "ubwc dec err status [%d]: offset[0x%x] value[0x%x] thr_err=%d, fcl_err=%d, len_md_err=%d, format_err=%d", + i, camnoc_info->irq_err[i].err_status.offset, + dec_err->decerr_status.value, + dec_err->decerr_status.thr_err, + dec_err->decerr_status.fcl_err, + dec_err->decerr_status.len_md_err, + dec_err->decerr_status.format_err); + + return 0; +} + +static int cam_cpastop_handle_ahb_timeout_err(struct cam_hw_info *cpas_hw, + struct cam_camnoc_irq_ahb_timeout_data *ahb_err) +{ + CAM_ERR_RATE_LIMIT(CAM_CPAS, "ahb timeout error"); + + return 0; +} + +static int cam_cpastop_disable_test_irq(struct cam_hw_info *cpas_hw) +{ + camnoc_info->irq_sbm->sbm_clear.value &= ~0x4; + camnoc_info->irq_sbm->sbm_enable.value &= ~0x100; + camnoc_info->irq_err[CAM_CAMNOC_HW_IRQ_CAMNOC_TEST].enable = false; + + return 0; +} + +static int cam_cpastop_reset_irq(struct cam_hw_info *cpas_hw) +{ + int i; + + if (camnoc_info->irq_sbm->sbm_enable.enable == false) + return 0; + + cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC, + &camnoc_info->irq_sbm->sbm_clear); + for (i = 0; i < camnoc_info->irq_err_size; i++) { + if (camnoc_info->irq_err[i].enable) + cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC, + &camnoc_info->irq_err[i].err_clear); + } + + cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC, + &camnoc_info->irq_sbm->sbm_enable); + for (i = 0; i < camnoc_info->irq_err_size; i++) { + if (camnoc_info->irq_err[i].enable) + cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC, + &camnoc_info->irq_err[i].err_enable); + } + + return 0; +} + +static void cam_cpastop_notify_clients(struct cam_cpas *cpas_core, + struct cam_cpas_irq_data *irq_data) +{ + int i; + struct cam_cpas_client *cpas_client; + bool error_handled = false; + + CAM_DBG(CAM_CPAS, + "Notify CB : num_clients=%d, registered=%d, started=%d", + cpas_core->num_clients, cpas_core->registered_clients, + cpas_core->streamon_clients); + + for (i = 0; i < cpas_core->num_clients; i++) { + if (CAM_CPAS_CLIENT_STARTED(cpas_core, i)) { + cpas_client = cpas_core->cpas_client[i]; + if (cpas_client->data.cam_cpas_client_cb) { + CAM_DBG(CAM_CPAS, + "Calling client CB %d : %d", + i, irq_data->irq_type); + error_handled = + cpas_client->data.cam_cpas_client_cb( + cpas_client->data.client_handle, + cpas_client->data.userdata, + irq_data); + if (error_handled) + break; + } + } + } +} + +static void cam_cpastop_work(struct work_struct *work) +{ + struct cam_cpas_work_payload *payload; + struct cam_hw_info *cpas_hw; + struct cam_cpas *cpas_core; + struct cam_hw_soc_info *soc_info; + int i; + enum cam_camnoc_hw_irq_type irq_type; + struct cam_cpas_irq_data irq_data; + + payload = container_of(work, struct cam_cpas_work_payload, work); + if (!payload) { + CAM_ERR(CAM_CPAS, "NULL payload"); + return; + } + + cam_req_mgr_thread_switch_delay_detect( + payload->workq_scheduled_ts); + + cpas_hw = payload->hw; + cpas_core = (struct cam_cpas *) cpas_hw->core_info; + soc_info = &cpas_hw->soc_info; + + if (!atomic_inc_not_zero(&cpas_core->irq_count)) { + CAM_ERR(CAM_CPAS, "CPAS off"); + return; + } + + for (i = 0; i < camnoc_info->irq_err_size; i++) { + if ((payload->irq_status & camnoc_info->irq_err[i].sbm_port) && + (camnoc_info->irq_err[i].enable)) { + irq_type = camnoc_info->irq_err[i].irq_type; + CAM_ERR_RATE_LIMIT(CAM_CPAS, + "Error occurred, type=%d", irq_type); + memset(&irq_data, 0x0, sizeof(irq_data)); + irq_data.irq_type = (enum cam_camnoc_irq_type)irq_type; + + switch (irq_type) { + case CAM_CAMNOC_HW_IRQ_SLAVE_ERROR: + cam_cpastop_handle_errlogger( + cpas_core, soc_info, + &irq_data.u.slave_err); + break; + case CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR: + case CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR: + case CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR: + case CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR: + cam_cpastop_handle_ubwc_enc_err( + cpas_core, soc_info, i, + &irq_data.u.enc_err); + break; + case CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR: + case CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR: + case CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR: + cam_cpastop_handle_ubwc_dec_err( + cpas_core, soc_info, i, + &irq_data.u.dec_err); + break; + case CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT: + cam_cpastop_handle_ahb_timeout_err( + cpas_hw, &irq_data.u.ahb_err); + break; + case CAM_CAMNOC_HW_IRQ_CAMNOC_TEST: + CAM_DBG(CAM_CPAS, "TEST IRQ"); + break; + default: + CAM_ERR(CAM_CPAS, "Invalid IRQ type"); + break; + } + + cam_cpastop_notify_clients(cpas_core, &irq_data); + + payload->irq_status &= + ~camnoc_info->irq_err[i].sbm_port; + } + } + atomic_dec(&cpas_core->irq_count); + wake_up(&cpas_core->irq_count_wq); + CAM_DBG(CAM_CPAS, "irq_count=%d\n", atomic_read(&cpas_core->irq_count)); + + if (payload->irq_status) + CAM_ERR(CAM_CPAS, "IRQ not handled irq_status=0x%x", + payload->irq_status); + + kfree(payload); +} + +static irqreturn_t cam_cpastop_handle_irq(int irq_num, void *data) +{ + struct cam_hw_info *cpas_hw = (struct cam_hw_info *)data; + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; + int camnoc_index = cpas_core->regbase_index[CAM_CPAS_REG_CAMNOC]; + struct cam_cpas_work_payload *payload; + + if (!atomic_inc_not_zero(&cpas_core->irq_count)) { + CAM_ERR(CAM_CPAS, "CPAS off"); + return IRQ_HANDLED; + } + + payload = kzalloc(sizeof(struct cam_cpas_work_payload), GFP_ATOMIC); + if (!payload) + goto done; + + payload->irq_status = cam_io_r_mb( + soc_info->reg_map[camnoc_index].mem_base + + camnoc_info->irq_sbm->sbm_status.offset); + + CAM_DBG(CAM_CPAS, "IRQ callback, irq_status=0x%x", payload->irq_status); + + payload->hw = cpas_hw; + INIT_WORK((struct work_struct *)&payload->work, cam_cpastop_work); + + if (TEST_IRQ_ENABLE) + cam_cpastop_disable_test_irq(cpas_hw); + + cam_cpastop_reset_irq(cpas_hw); + + payload->workq_scheduled_ts = ktime_get(); + queue_work(cpas_core->work_queue, &payload->work); +done: + atomic_dec(&cpas_core->irq_count); + wake_up(&cpas_core->irq_count_wq); + + return IRQ_HANDLED; +} + +static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw) +{ + int i, reg_val; + struct cam_cpas_hw_errata_wa_list *errata_wa_list = + camnoc_info->errata_wa_list; + struct cam_cpas_hw_errata_wa *errata_wa; + + cam_cpastop_reset_irq(cpas_hw); + for (i = 0; i < camnoc_info->specific_size; i++) { + if (camnoc_info->specific[i].enable) { + cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC, + &camnoc_info->specific[i].priority_lut_low); + cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC, + &camnoc_info->specific[i].priority_lut_high); + cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC, + &camnoc_info->specific[i].urgency); + cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC, + &camnoc_info->specific[i].danger_lut); + cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC, + &camnoc_info->specific[i].safe_lut); + cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC, + &camnoc_info->specific[i].ubwc_ctl); + cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC, + &camnoc_info->specific[i].flag_out_set0_low); + } + } + + if (errata_wa_list) { + errata_wa = &errata_wa_list->tcsr_camera_hf_sf_ares_glitch; + if (errata_wa->enable) { + reg_val = scm_io_read(errata_wa->data.reg_info.offset); + reg_val |= errata_wa->data.reg_info.value; + scm_io_write(errata_wa->data.reg_info.offset, reg_val); + } + } + + return 0; +} + +static int cam_cpastop_poweroff(struct cam_hw_info *cpas_hw) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; + int camnoc_index = cpas_core->regbase_index[CAM_CPAS_REG_CAMNOC]; + int rc = 0; + struct cam_cpas_hw_errata_wa_list *errata_wa_list = + camnoc_info->errata_wa_list; + + if (!errata_wa_list) + return 0; + + if (errata_wa_list->camnoc_flush_slave_pending_trans.enable) { + struct cam_cpas_hw_errata_wa *errata_wa = + &errata_wa_list->camnoc_flush_slave_pending_trans; + + rc = cam_io_poll_value_wmask( + soc_info->reg_map[camnoc_index].mem_base + + errata_wa->data.reg_info.offset, + errata_wa->data.reg_info.value, + errata_wa->data.reg_info.mask, + CAM_CPAS_POLL_RETRY_CNT, + CAM_CPAS_POLL_MIN_USECS, CAM_CPAS_POLL_MAX_USECS); + if (rc) { + CAM_DBG(CAM_CPAS, + "camnoc flush slave pending trans failed"); + /* Do not return error, passthrough */ + rc = 0; + } + } + + return rc; +} + +static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, + struct cam_cpas_hw_caps *hw_caps) +{ + int rc = 0; + struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; + struct cam_cpas_private_soc *soc_private; + + CAM_DBG(CAM_CPAS, + "hw_version=0x%x Camera Version %d.%d.%d, cpas version %d.%d.%d", + soc_info->hw_version, + hw_caps->camera_version.major, + hw_caps->camera_version.minor, + hw_caps->camera_version.incr, + hw_caps->cpas_version.major, + hw_caps->cpas_version.minor, + hw_caps->cpas_version.incr); + + switch (soc_info->hw_version) { + case CAM_CPAS_TITAN_170_V100: + camnoc_info = &cam170_cpas100_camnoc_info; + break; + case CAM_CPAS_TITAN_170_V110: + camnoc_info = &cam170_cpas110_camnoc_info; + break; + case CAM_CPAS_TITAN_175_V100: + camnoc_info = &cam175_cpas100_camnoc_info; + break; + case CAM_CPAS_TITAN_175_V101: + camnoc_info = &cam175_cpas101_camnoc_info; + break; + case CAM_CPAS_TITAN_175_V120: + camnoc_info = &cam175_cpas120_camnoc_info; + break; + case CAM_CPAS_TITAN_175_V130: + camnoc_info = &cam175_cpas130_camnoc_info; + break; + case CAM_CPAS_TITAN_150_V100: + camnoc_info = &cam150_cpas100_camnoc_info; + break; + case CAM_CPAS_TITAN_480_V100: + camnoc_info = &cam480_cpas100_camnoc_info; + break; + case CAM_CPAS_TITAN_540_V100: + camnoc_info = &cam540_cpas100_camnoc_info; + break; + case CAM_CPAS_TITAN_520_V100: + camnoc_info = &cam520_cpas100_camnoc_info; + break; + case CAM_CPAS_TITAN_545_V110: + soc_private = (struct cam_cpas_private_soc *) + soc_info->soc_private; + if (soc_private->custom_id == CAM_CPAS_TITAN_SOC_ID_518) + camnoc_info = &cam545_cpas110_socid518_camnoc_info; + break; + default: + CAM_ERR(CAM_CPAS, "Camera Version not supported %d.%d.%d", + hw_caps->camera_version.major, + hw_caps->camera_version.minor, + hw_caps->camera_version.incr); + rc = -EINVAL; + break; + } + + return 0; +} + +int cam_cpastop_get_internal_ops(struct cam_cpas_internal_ops *internal_ops) +{ + if (!internal_ops) { + CAM_ERR(CAM_CPAS, "invalid NULL param"); + return -EINVAL; + } + + internal_ops->get_hw_info = cam_cpastop_get_hw_info; + internal_ops->init_hw_version = cam_cpastop_init_hw_version; + internal_ops->handle_irq = cam_cpastop_handle_irq; + internal_ops->setup_regbase = cam_cpastop_setup_regbase_indices; + internal_ops->power_on = cam_cpastop_poweron; + internal_ops->power_off = cam_cpastop_poweroff; + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h new file mode 100644 index 0000000000000000000000000000000000000000..6a13d35b3e39e309cc6d8405da9fbd8807806b7c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h @@ -0,0 +1,295 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CPASTOP_HW_H_ +#define _CAM_CPASTOP_HW_H_ + +#include "cam_cpas_api.h" +#include "cam_cpas_hw.h" + +/** + * enum cam_camnoc_hw_irq_type - Enum for camnoc error types + * + * @CAM_CAMNOC_HW_IRQ_SLAVE_ERROR: Each slave port in CAMNOC (3 QSB ports and + * 1 QHB port) has an error logger. The error + * observed at any slave port is logged into + * the error logger register and an IRQ is + * triggered + * @CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR: Triggered if any error + * detected in the IFE UBWC- + * Stats encoder instance + * @CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR : Triggered if any error + * detected in the IFE0 UBWC + * encoder instance + * @CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR : Triggered if any error + * detected in the IFE1 or IFE3 + * UBWC encoder instance + * @CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR: Triggered if any error + * detected in the IPE1/BPS read + * path decoder instance + * @CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR : Triggered if any error detected + * in the IPE0 read path decoder + * instance + * @CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR: Triggered if any error + * detected in the IPE/BPS + * UBWC decoder instance + * @CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR: Triggered if any error + * detected in the IPE/BPS UBWC + * encoder instance + * @CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR: Triggered if any UBWC error + * is detected in IFE0 write path + * @CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR: Triggered if any UBWC error + * is detected in IFE1 write path + * @CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT : Triggered when the QHS_ICP + * slave times out after 4000 + * AHB cycles + * @CAM_CAMNOC_HW_IRQ_RESERVED1 : Reserved + * @CAM_CAMNOC_HW_IRQ_RESERVED2 : Reserved + * @CAM_CAMNOC_HW_IRQ_CAMNOC_TEST : To test the IRQ logic + */ +enum cam_camnoc_hw_irq_type { + CAM_CAMNOC_HW_IRQ_SLAVE_ERROR = + CAM_CAMNOC_IRQ_SLAVE_ERROR, + CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR = + CAM_CAMNOC_IRQ_IFE_UBWC_STATS_ENCODE_ERROR, + CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR = + CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR, + CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR = + CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR, + CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR = + CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR, + CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR = + CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR, + CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR = + CAM_CAMNOC_IRQ_IPE1_BPS_UBWC_DECODE_ERROR, + CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR = + CAM_CAMNOC_IRQ_IPE0_UBWC_DECODE_ERROR, + CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR = + CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR, + CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR = + CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR, + CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT = + CAM_CAMNOC_IRQ_AHB_TIMEOUT, + CAM_CAMNOC_HW_IRQ_RESERVED1, + CAM_CAMNOC_HW_IRQ_RESERVED2, + CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, +}; + +/** + * enum cam_camnoc_port_type - Enum for different camnoc hw ports. All CAMNOC + * settings like QoS, LUT mappings need to be configured for + * each of these ports. + * + * @CAM_CAMNOC_CDM: Indicates CDM HW connection to camnoc + * @CAM_CAMNOC_IFE02: Indicates IFE0, IFE2 HW connection to camnoc + * @CAM_CAMNOC_IFE13: Indicates IFE1, IFE3 HW connection to camnoc + * @CAM_CAMNOC_IFE_LINEAR: Indicates linear data from all IFEs to cammnoc + * @CAM_CAMNOC_IFE_UBWC_STATS: Indicates ubwc+stats from all IFEs to cammnoc + * @CAM_CAMNOC_IFE_RDI_WR: Indicates RDI write data from all IFEs to cammnoc + * @CAM_CAMNOC_IFE_RDI_RD: Indicates RDI read data from all IFEs to cammnoc + * @CAM_CAMNOC_IFE0123_RDI_WRITE: RDI write only for all IFEx + * @CAM_CAMNOC_IFE0_NRDI_WRITE: IFE0 non-RDI write + * @CAM_CAMNOC_IFE01_RDI_READ: IFE0/1 RDI READ + * @CAM_CAMNOC_IFE1_NRDI_WRITE: IFE1 non-RDI write + * @CAM_CAMNOC_IPE_BPS_LRME_READ: Indicates IPE, BPS, LRME Read HW + * connection to camnoc + * @CAM_CAMNOC_IPE_BPS_LRME_WRITE: Indicates IPE, BPS, LRME Write HW + * connection to camnoc + * @CAM_CAMNOC_IPE_VID_DISP_WRITE: Indicates IPE's VID/DISP Wrire HW + * connection to camnoc + * @CAM_CAMNOC_IPE0_RD: Indicates IPE's Read0 HW connection to camnoc + * @CAM_CAMNOC_IPE1_BPS_RD: Indicates IPE's Read1 + BPS Read HW connection + * to camnoc + * @CAM_CAMNOC_IPE_BPS_WR: Indicates IPE+BPS Write HW connection to camnoc + * @CAM_CAMNOC_JPEG: Indicates JPEG HW connection to camnoc + * @CAM_CAMNOC_FD: Indicates FD HW connection to camnoc + * @CAM_CAMNOC_ICP: Indicates ICP HW connection to camnoc + * @CAM_CAMNOC_TFE: Indicates TFE HW connection to camnoc + * @CAM_CAMNOC_TFE_1 : Indicates TFE1 HW connection to camnoc + * @CAM_CAMNOC_TFE_2 : Indicates TFE2 HW connection to camnoc + * @CAM_CAMNOC_OPE: Indicates OPE HW connection to camnoc + */ +enum cam_camnoc_port_type { + CAM_CAMNOC_CDM, + CAM_CAMNOC_IFE02, + CAM_CAMNOC_IFE13, + CAM_CAMNOC_IFE_LINEAR, + CAM_CAMNOC_IFE_UBWC_STATS, + CAM_CAMNOC_IFE_RDI_WR, + CAM_CAMNOC_IFE_RDI_RD, + CAM_CAMNOC_IFE0123_RDI_WRITE, + CAM_CAMNOC_IFE0_NRDI_WRITE, + CAM_CAMNOC_IFE01_RDI_READ, + CAM_CAMNOC_IFE1_NRDI_WRITE, + CAM_CAMNOC_IPE_BPS_LRME_READ, + CAM_CAMNOC_IPE_BPS_LRME_WRITE, + CAM_CAMNOC_IPE_VID_DISP_WRITE, + CAM_CAMNOC_IPE0_RD, + CAM_CAMNOC_IPE1_BPS_RD, + CAM_CAMNOC_IPE_BPS_WR, + CAM_CAMNOC_JPEG, + CAM_CAMNOC_FD, + CAM_CAMNOC_ICP, + CAM_CAMNOC_TFE, + CAM_CAMNOC_TFE_1, + CAM_CAMNOC_TFE_2, + CAM_CAMNOC_OPE, +}; + +/** + * struct cam_camnoc_specific : CPAS camnoc specific settings + * + * @port_type: Port type + * @enable: Whether to enable settings for this connection + * @priority_lut_low: Priority Low LUT mapping for this connection + * @priority_lut_high: Priority High LUT mapping for this connection + * @urgency: Urgency (QoS) settings for this connection + * @danger_lut: Danger LUT mapping for this connection + * @safe_lut: Safe LUT mapping for this connection + * @ubwc_ctl: UBWC control settings for this connection + * + */ +struct cam_camnoc_specific { + enum cam_camnoc_port_type port_type; + bool enable; + struct cam_cpas_reg priority_lut_low; + struct cam_cpas_reg priority_lut_high; + struct cam_cpas_reg urgency; + struct cam_cpas_reg danger_lut; + struct cam_cpas_reg safe_lut; + struct cam_cpas_reg ubwc_ctl; + struct cam_cpas_reg flag_out_set0_low; +}; + +/** + * struct cam_camnoc_irq_sbm : Sideband manager settings for all CAMNOC IRQs + * + * @sbm_enable: SBM settings for IRQ enable + * @sbm_status: SBM settings for IRQ status + * @sbm_clear: SBM settings for IRQ clear + * + */ +struct cam_camnoc_irq_sbm { + struct cam_cpas_reg sbm_enable; + struct cam_cpas_reg sbm_status; + struct cam_cpas_reg sbm_clear; +}; + +/** + * struct cam_camnoc_irq_err : Error settings specific to each CAMNOC IRQ + * + * @irq_type: Type of IRQ + * @enable: Whether to enable error settings for this IRQ + * @sbm_port: Corresponding SBM port for this IRQ + * @err_enable: Error enable settings for this IRQ + * @err_status: Error status settings for this IRQ + * @err_clear: Error clear settings for this IRQ + * + */ +struct cam_camnoc_irq_err { + enum cam_camnoc_hw_irq_type irq_type; + bool enable; + uint32_t sbm_port; + struct cam_cpas_reg err_enable; + struct cam_cpas_reg err_status; + struct cam_cpas_reg err_clear; +}; + +/** + * struct cam_cpas_hw_errata_wa : Struct for HW errata workaround info + * + * @enable: Whether to enable this errata workround + * @data: HW Errata workaround data + * + */ +struct cam_cpas_hw_errata_wa { + bool enable; + union { + struct cam_cpas_reg reg_info; + } data; +}; + +/** + * struct cam_cpas_hw_errata_wa_list : List of HW Errata workaround info + * + * @camnoc_flush_slave_pending_trans: Errata workaround info for flushing + * camnoc slave pending transactions before turning off CPAS_TOP gdsc + * @tcsr_camera_hf_sf_ares_glitch: Errata workaround info from ignoring + * erroneous signals at camera start + */ +struct cam_cpas_hw_errata_wa_list { + struct cam_cpas_hw_errata_wa camnoc_flush_slave_pending_trans; + struct cam_cpas_hw_errata_wa tcsr_camera_hf_sf_ares_glitch; +}; + +/** + * struct cam_camnoc_err_logger_info : CAMNOC error logger register offsets + * + * @mainctrl: Register offset for mainctrl + * @errvld: Register offset for errvld + * @errlog0_low: Register offset for errlog0_low + * @errlog0_high: Register offset for errlog0_high + * @errlog1_low: Register offset for errlog1_low + * @errlog1_high: Register offset for errlog1_high + * @errlog2_low: Register offset for errlog2_low + * @errlog2_high: Register offset for errlog2_high + * @errlog3_low: Register offset for errlog3_low + * @errlog3_high: Register offset for errlog3_high + * + */ +struct cam_camnoc_err_logger_info { + uint32_t mainctrl; + uint32_t errvld; + uint32_t errlog0_low; + uint32_t errlog0_high; + uint32_t errlog1_low; + uint32_t errlog1_high; + uint32_t errlog2_low; + uint32_t errlog2_high; + uint32_t errlog3_low; + uint32_t errlog3_high; +}; + +/** + * struct cam_camnoc_info : Overall CAMNOC settings info + * + * @specific: Pointer to CAMNOC SPECIFICTONTTPTR settings + * @specific_size: Array size of SPECIFICTONTTPTR settings + * @irq_sbm: Pointer to CAMNOC IRQ SBM settings + * @irq_err: Pointer to CAMNOC IRQ Error settings + * @irq_err_size: Array size of IRQ Error settings + * @err_logger: Pointer to CAMNOC IRQ Error logger read registers + * @errata_wa_list: HW Errata workaround info + * + */ +struct cam_camnoc_info { + struct cam_camnoc_specific *specific; + int specific_size; + struct cam_camnoc_irq_sbm *irq_sbm; + struct cam_camnoc_irq_err *irq_err; + int irq_err_size; + struct cam_camnoc_err_logger_info *err_logger; + struct cam_cpas_hw_errata_wa_list *errata_wa_list; +}; + +/** + * struct cam_cpas_work_payload : Struct for cpas work payload data + * + * @hw: Pointer to HW info + * @irq_status: IRQ status value + * @irq_data: IRQ data + * @workq_scheduled_ts: workqueue scheduled timestamp + * @work: Work handle + * + */ +struct cam_cpas_work_payload { + struct cam_hw_info *hw; + uint32_t irq_status; + uint32_t irq_data; + ktime_t workq_scheduled_ts; + struct work_struct work; +}; + +#endif /* _CAM_CPASTOP_HW_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop100.h b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop100.h new file mode 100644 index 0000000000000000000000000000000000000000..2f444710e9f4c6e4120f5250a9ff551c927dc9d1 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop100.h @@ -0,0 +1,531 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP100_H_ +#define _CPASTOP100_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas100_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2040, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + (TEST_IRQ_ENABLE ? + 0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x6 : 0x2, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas100_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x1190, + /* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = true, + .sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x5, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + +static struct cam_camnoc_specific + cam_cpas100_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */ + .mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */ + .shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */ + .value = 0, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE02, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */ + /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */ + .value = 0x3, + }, + .ubwc_ctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IFE13, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */ + /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */ + .value = 0x3, + }, + .ubwc_ctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_READ, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */ + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */ + .mask = 0x7, + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */ + .shift = 0x0, + .value = 3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */ + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_JPEG, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */ + .value = 0x22, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_FD, + .enable = false, + }, + { + .port_type = CAM_CAMNOC_ICP, + .enable = false, + } +}; + +static struct cam_camnoc_err_logger_info cam170_cpas100_err_logger_offsets = { + .mainctrl = 0x2708, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0x2710, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0x2720, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0x2724, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0x2728, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0x272c, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0x2730, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0x2734, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0x2738, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0x273c, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam170_cpas100_errata_wa_list = { + .camnoc_flush_slave_pending_trans = { + .enable = true, + .data.reg_info = { + .access_type = CAM_REG_TYPE_READ, + .offset = 0x2100, /* SidebandManager_SenseIn0_Low */ + .mask = 0xE0000, /* Bits 17, 18, 19 */ + .value = 0, /* expected to be 0 */ + }, + }, +}; + +struct cam_camnoc_info cam170_cpas100_camnoc_info = { + .specific = &cam_cpas100_camnoc_specific[0], + .specific_size = sizeof(cam_cpas100_camnoc_specific) / + sizeof(cam_cpas100_camnoc_specific[0]), + .irq_sbm = &cam_cpas100_irq_sbm, + .irq_err = &cam_cpas100_irq_err[0], + .irq_err_size = sizeof(cam_cpas100_irq_err) / + sizeof(cam_cpas100_irq_err[0]), + .err_logger = &cam170_cpas100_err_logger_offsets, + .errata_wa_list = &cam170_cpas100_errata_wa_list, +}; + +#endif /* _CPASTOP100_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v150_100.h b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v150_100.h new file mode 100644 index 0000000000000000000000000000000000000000..df9711e74379e7cc92b6e3fe6eb9a9ad6c4f2522 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v150_100.h @@ -0,0 +1,530 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V150_100_H_ +#define _CPASTOP_V150_100_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v150_100_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2040, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + (TEST_IRQ_ENABLE ? + 0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x6 : 0x2, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v150_100_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x1190, + /* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = true, + .sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x5, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + +static struct cam_camnoc_specific + cam_cpas_v150_100_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */ + .mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */ + .shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */ + .value = 0x2, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE02, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */ + /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */ + .value = 0x1, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE13, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */ + /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */ + .value = 0x1, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_READ, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */ + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */ + .mask = 0x7, + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */ + .shift = 0x0, + .value = 3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */ + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ + .value = 0x5, + }, + }, + { + .port_type = CAM_CAMNOC_JPEG, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */ + .value = 0x22, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_FD, + .enable = false, + }, + { + .port_type = CAM_CAMNOC_ICP, + .enable = true, + .flag_out_set0_low = { + .enable = true, + .access_type = CAM_REG_TYPE_WRITE, + .masked_value = 0, + .offset = 0x2088, + .value = 0x100000, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam150_cpas100_err_logger_offsets = { + .mainctrl = 0x2708, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0x2710, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0x2720, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0x2724, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0x2728, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0x272c, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0x2730, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0x2734, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0x2738, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0x273c, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam150_cpas100_errata_wa_list = { + .camnoc_flush_slave_pending_trans = { + .enable = false, + .data.reg_info = { + .access_type = CAM_REG_TYPE_READ, + .offset = 0x2100, /* SidebandManager_SenseIn0_Low */ + .mask = 0xE0000, /* Bits 17, 18, 19 */ + .value = 0, /* expected to be 0 */ + }, + }, +}; + +static struct cam_camnoc_info cam150_cpas100_camnoc_info = { + .specific = &cam_cpas_v150_100_camnoc_specific[0], + .specific_size = sizeof(cam_cpas_v150_100_camnoc_specific) / + sizeof(cam_cpas_v150_100_camnoc_specific[0]), + .irq_sbm = &cam_cpas_v150_100_irq_sbm, + .irq_err = &cam_cpas_v150_100_irq_err[0], + .irq_err_size = sizeof(cam_cpas_v150_100_irq_err) / + sizeof(cam_cpas_v150_100_irq_err[0]), + .err_logger = &cam150_cpas100_err_logger_offsets, + .errata_wa_list = &cam150_cpas100_errata_wa_list, +}; + +#endif /* _CPASTOP_V150_100_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v170_110.h b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v170_110.h new file mode 100644 index 0000000000000000000000000000000000000000..788f571a3a1343d083a87649c89d60005421749d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v170_110.h @@ -0,0 +1,538 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V170_110_H_ +#define _CPASTOP_V170_110_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas110_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2040, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + (TEST_IRQ_ENABLE ? + 0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x6 : 0x2, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas110_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x1190, + /* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = true, + .sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x5, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + +static struct cam_camnoc_specific + cam_cpas110_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */ + .mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */ + .shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */ + .value = 0x2, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE02, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */ + .value = 0x66666543, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */ + /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */ + .value = 0x1, + }, + .ubwc_ctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IFE13, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */ + .value = 0x66666543, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */ + /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */ + .value = 0x1, + }, + .ubwc_ctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_READ, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */ + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */ + .mask = 0x7, + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */ + .shift = 0x0, + .value = 3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */ + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_JPEG, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */ + .value = 0x22, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_FD, + .enable = false, + }, + { + .port_type = CAM_CAMNOC_ICP, + .enable = true, + .flag_out_set0_low = { + .enable = true, + .access_type = CAM_REG_TYPE_WRITE, + .masked_value = 0, + .offset = 0x2088, + .value = 0x100000, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam170_cpas110_err_logger_offsets = { + .mainctrl = 0x2708, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0x2710, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0x2720, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0x2724, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0x2728, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0x272c, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0x2730, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0x2734, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0x2738, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0x273c, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam170_cpas110_errata_wa_list = { + .camnoc_flush_slave_pending_trans = { + .enable = false, + .data.reg_info = { + .access_type = CAM_REG_TYPE_READ, + .offset = 0x2100, /* SidebandManager_SenseIn0_Low */ + .mask = 0xE0000, /* Bits 17, 18, 19 */ + .value = 0, /* expected to be 0 */ + }, + }, +}; + +static struct cam_camnoc_info cam170_cpas110_camnoc_info = { + .specific = &cam_cpas110_camnoc_specific[0], + .specific_size = sizeof(cam_cpas110_camnoc_specific) / + sizeof(cam_cpas110_camnoc_specific[0]), + .irq_sbm = &cam_cpas110_irq_sbm, + .irq_err = &cam_cpas110_irq_err[0], + .irq_err_size = sizeof(cam_cpas110_irq_err) / + sizeof(cam_cpas110_irq_err[0]), + .err_logger = &cam170_cpas110_err_logger_offsets, + .errata_wa_list = &cam170_cpas110_errata_wa_list, +}; + +#endif /* _CPASTOP_V170_110_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v175_100.h b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v175_100.h new file mode 100644 index 0000000000000000000000000000000000000000..aae26b5a91789b73d4cddcc2f5846d34292786be --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v175_100.h @@ -0,0 +1,558 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V175_100_H_ +#define _CPASTOP_V175_100_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v175_100_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2040, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + (TEST_IRQ_ENABLE ? + 0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x6 : 0x2, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v175_100_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x1190, + /* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = true, + .sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x5, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + +static struct cam_camnoc_specific + cam_cpas_v175_100_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */ + .mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */ + .shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */ + .value = 0x2, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE02, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */ + .value = 0x66666543, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */ + /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */ + .value = 0x1, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IFE13, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */ + .value = 0x66666543, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */ + /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */ + .value = 0x1, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_READ, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */ + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */ + .mask = 0x7, + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */ + .shift = 0x0, + .value = 3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */ + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_JPEG, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */ + .value = 0x22, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_FD, + .enable = false, + }, + { + .port_type = CAM_CAMNOC_ICP, + .enable = true, + .flag_out_set0_low = { + .enable = true, + .access_type = CAM_REG_TYPE_WRITE, + .masked_value = 0, + .offset = 0x2088, + .value = 0x100000, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam175_cpas100_err_logger_offsets = { + .mainctrl = 0x2708, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0x2710, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0x2720, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0x2724, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0x2728, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0x272c, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0x2730, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0x2734, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0x2738, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0x273c, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam175_cpas100_errata_wa_list = { + .camnoc_flush_slave_pending_trans = { + .enable = false, + .data.reg_info = { + .access_type = CAM_REG_TYPE_READ, + .offset = 0x2100, /* SidebandManager_SenseIn0_Low */ + .mask = 0xE0000, /* Bits 17, 18, 19 */ + .value = 0, /* expected to be 0 */ + }, + }, +}; + +static struct cam_camnoc_info cam175_cpas100_camnoc_info = { + .specific = &cam_cpas_v175_100_camnoc_specific[0], + .specific_size = sizeof(cam_cpas_v175_100_camnoc_specific) / + sizeof(cam_cpas_v175_100_camnoc_specific[0]), + .irq_sbm = &cam_cpas_v175_100_irq_sbm, + .irq_err = &cam_cpas_v175_100_irq_err[0], + .irq_err_size = sizeof(cam_cpas_v175_100_irq_err) / + sizeof(cam_cpas_v175_100_irq_err[0]), + .err_logger = &cam175_cpas100_err_logger_offsets, + .errata_wa_list = &cam175_cpas100_errata_wa_list, +}; + +#endif /* _CPASTOP_V175_100_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v175_101.h b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v175_101.h new file mode 100644 index 0000000000000000000000000000000000000000..7ec9bec36fd1f8c99980bfb0fa0cbe13079657c5 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v175_101.h @@ -0,0 +1,558 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V175_101_H_ +#define _CPASTOP_V175_101_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v175_101_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2040, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + (TEST_IRQ_ENABLE ? + 0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x6 : 0x2, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v175_101_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x1190, + /* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = true, + .sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x5, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + +static struct cam_camnoc_specific + cam_cpas_v175_101_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */ + .mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */ + .shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */ + .value = 0x2, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE02, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */ + .value = 0x66666543, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */ + /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */ + .value = 0x1, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IFE13, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */ + .value = 0x66666543, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */ + /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */ + .value = 0x1, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_READ, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */ + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */ + .mask = 0x7, + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */ + .shift = 0x0, + .value = 3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */ + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_JPEG, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */ + .value = 0x22, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_FD, + .enable = false, + }, + { + .port_type = CAM_CAMNOC_ICP, + .enable = true, + .flag_out_set0_low = { + .enable = true, + .access_type = CAM_REG_TYPE_WRITE, + .masked_value = 0, + .offset = 0x2088, + .value = 0x100000, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam175_cpas101_err_logger_offsets = { + .mainctrl = 0x2708, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0x2710, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0x2720, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0x2724, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0x2728, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0x272c, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0x2730, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0x2734, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0x2738, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0x273c, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam175_cpas101_errata_wa_list = { + .camnoc_flush_slave_pending_trans = { + .enable = false, + .data.reg_info = { + .access_type = CAM_REG_TYPE_READ, + .offset = 0x2100, /* SidebandManager_SenseIn0_Low */ + .mask = 0xE0000, /* Bits 17, 18, 19 */ + .value = 0, /* expected to be 0 */ + }, + }, +}; + +static struct cam_camnoc_info cam175_cpas101_camnoc_info = { + .specific = &cam_cpas_v175_101_camnoc_specific[0], + .specific_size = sizeof(cam_cpas_v175_101_camnoc_specific) / + sizeof(cam_cpas_v175_101_camnoc_specific[0]), + .irq_sbm = &cam_cpas_v175_101_irq_sbm, + .irq_err = &cam_cpas_v175_101_irq_err[0], + .irq_err_size = sizeof(cam_cpas_v175_101_irq_err) / + sizeof(cam_cpas_v175_101_irq_err[0]), + .err_logger = &cam175_cpas101_err_logger_offsets, + .errata_wa_list = &cam175_cpas101_errata_wa_list, +}; + +#endif /* _CPASTOP_V175_101_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v175_120.h b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v175_120.h new file mode 100644 index 0000000000000000000000000000000000000000..5844c38ae52cf45282db8dcd018869b994d7129f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v175_120.h @@ -0,0 +1,760 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V175_120_H_ +#define _CPASTOP_V175_120_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v175_120_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2240, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + (TEST_IRQ_ENABLE ? + 0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2248, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2280, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x6 : 0x2, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v175_120_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x4F08, /* ERRORLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x4F10, /* ERRORLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x4F18, /* ERRORLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x3BA0, /* SPECIFIC_IFE02_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x3B90, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x3B98, /* SPECIFIC_IFE02_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x55a0, /* SPECIFIC_IFE13_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x5590, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x5598, /* SPECIFIC_IFE13_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2F20, /* SPECIFIC_IBL_RD_DECERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2F10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2F18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2Ba0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2B90, + /* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2B98, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = true, + .sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2288, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2290, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2288, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x5, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2290, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + +static struct cam_camnoc_specific + cam_cpas_v175_120_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4230, /* SPECIFIC_CDM_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4234, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + /* cdm_main_SpecificToNttpTr_Urgency_Low */ + .offset = 0x4238, + .mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */ + .shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */ + .value = 0x2, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4240, /* SPECIFIC_CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4248, /* SPECIFIC_CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE0123_RDI_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IFE0123_PRIORITYLUT_LOW */ + .offset = 0x3630, + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IFE0123_PRIORITYLUT_HIGH */ + .offset = 0x3634, + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x3638, /* SPECIFIC_IFE0123_URGENCY_LOW */ + /* SPECIFIC_IFE0123_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE0123_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3640, /* SPECIFIC_IFE0123_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3648, /* SPECIFIC_IFE0123_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE0_NRDI_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3A30, /* SPECIFIC_IFE0_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3A34, /* SPECIFIC_IFE0_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x3A38, /* SPECIFIC_IFE0_URGENCY_LOW */ + /* SPECIFIC_IFE0_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE0_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3A40, /* SPECIFIC_IFE0_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3A48, /* SPECIFIC_IFE0_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3B88, /* SPECIFIC_IFE0_ENCCTL_LOW */ + .value = 1, + }, + }, + { + /* IFE0/1 RDI READ PATH */ + .port_type = CAM_CAMNOC_IFE01_RDI_READ, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3230, /* SPECIFIC_IFE1_PRIORITYLUT_LOW */ + .value = 0x44443333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3234, /* SPECIFIC_IFE1_PRIORITYLUT_HIGH */ + .value = 0x66665555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x3238, /* SPECIFIC_IFE1_URGENCY_LOW */ + /* SPECIFIC_IFE1_URGENCY_LOW_WRITE_MASK */ + .mask = 0x7, + /* SPECIFIC_IFE1_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x0, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3240, /* SPECIFIC_IFE1_DANGERLUT_LOW */ + .value = 0x00000000, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3248, /* SPECIFIC_IFE1_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE1_NRDI_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5430, /* SPECIFIC_IFE1_WR_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IFE1_WR_PRIORITYLUT_HIGH */ + .offset = 0x5434, + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x5438, /* SPECIFIC_IFE1_WR_URGENCY_LOW */ + /* SPECIFIC_IFE1_WR_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE1_WR_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x5440, /* SPECIFIC_IFE1_WR_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x5448, /* SPECIFIC_IFE1_WR_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5588, /* SPECIFIC_IFE1_WR_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_READ, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x2E38, /* SPECIFIC_IBL_RD_URGENCY_LOW */ + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */ + .mask = 0x7, + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */ + .shift = 0x0, + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2F08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2A30, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2A34, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x2A38, /* SPECIFIC_IBL_WR_URGENCY_LOW */ + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2A40, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2A48, /* SPECIFIC_IBL_WR_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2B88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ + .value = 0, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_VID_DISP_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IPE_VID_DISP_PRIORITYLUT_LOW */ + .offset = 0x5E30, + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IPE_VID_DISP_PRIORITYLUT_HIGH */ + .offset = 0x5E34, + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + /* SPECIFIC_IPE_VID_DISP_URGENCY_LOW */ + .offset = 0x5E38, + /* SPECIFIC_IPE_VID_DISP_URGENCY_LOW_READ_MASK */ + .mask = 0x70, + /* SPECIFIC_IPE_VID_DISP_URGENCY_LOW_READ_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC__IPE_VID_DISP_DANGERLUT_LOW */ + .offset = 0x5E40, + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IPE_VID_DISP_SAFELUT_LOW */ + .offset = 0x5E48, + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5F88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ + .value = 1, + }, + }, + + { + .port_type = CAM_CAMNOC_JPEG, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2630, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2634, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2638, /* SPECIFIC_JPEG_URGENCY_LOW */ + .value = 0x22, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2640, /* SPECIFIC_JPEG_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2648, /* SPECIFIC_JPEG_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_FD, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3E30, /* SPECIFIC_FD_PRIORITYLUT_LOW */ + .value = 0x44444444, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3E34, /* SPECIFIC_FD_PRIORITYLUT_HIGH */ + .value = 0x44444444, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3E38, /* SPECIFIC_FD_URGENCY_LOW */ + .value = 0x44, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3E40, /* SPECIFIC_FD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3E48, /* SPECIFIC_FD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + + }, + { + /*SidebandManager_main_SidebandManager_FlagOutSet0_Low*/ + .port_type = CAM_CAMNOC_ICP, + .enable = true, + .flag_out_set0_low = { + .enable = true, + .access_type = CAM_REG_TYPE_WRITE, + .masked_value = 0, + .offset = 0x2288, + .value = 0x100000, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam175_cpas120_err_logger_offsets = { + .mainctrl = 0x4F08, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0x4F10, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0x4F20, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0x4F24, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0x4F28, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0x4F2c, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0x4F30, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0x4F34, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0x4F38, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0x4F3c, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam175_cpas120_errata_wa_list = { + .camnoc_flush_slave_pending_trans = { + .enable = false, + .data.reg_info = { + .access_type = CAM_REG_TYPE_READ, + .offset = 0x2300, /* SidebandManager_SenseIn0_Low */ + .mask = 0xE0000, /* Bits 17, 18, 19 */ + .value = 0, /* expected to be 0 */ + }, + }, +}; + +static struct cam_camnoc_info cam175_cpas120_camnoc_info = { + .specific = &cam_cpas_v175_120_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v175_120_camnoc_specific), + .irq_sbm = &cam_cpas_v175_120_irq_sbm, + .irq_err = &cam_cpas_v175_120_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v175_120_irq_err), + .err_logger = &cam175_cpas120_err_logger_offsets, + .errata_wa_list = &cam175_cpas120_errata_wa_list, +}; + +#endif /* _CPASTOP_V175_120_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v175_130.h b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v175_130.h new file mode 100644 index 0000000000000000000000000000000000000000..769e77fc3d6bf460964e3cea293d176cb80d95bf --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v175_130.h @@ -0,0 +1,773 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V175_130_H_ +#define _CPASTOP_V175_130_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v175_130_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2240, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + (TEST_IRQ_ENABLE ? + 0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2248, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2280, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x6 : 0x2, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v175_130_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x4F08, /* ERRORLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x4F10, /* ERRORLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x4F18, /* ERRORLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x3BA0, /* SPECIFIC_IFE0_MAIN_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + /* SPECIFIC_IFE0_MAIN_ENCERRSTATUS_LOW */ + .offset = 0x3B90, + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x3B98, /* SPECIFIC_IFE0_MAIN_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x55A0, /* SPECIFIC_IFE1_WR_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + /* SPECIFIC_IFE1_WR_ENCERRSTATUS_LOW */ + .offset = 0x5590, + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x5598, /* SPECIFIC_IFE1_WR_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2F20, /* SPECIFIC_IBL_RD_DECERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2F10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2F18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2BA0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2B90, + /* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2B98, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = true, + .sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2288, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2290, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2288, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x5, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2290, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + +static struct cam_camnoc_specific + cam_cpas_v175_130_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4230, /* SPECIFIC_CDM_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4234, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + /* cdm_main_SpecificToNttpTr_Urgency_Low */ + .offset = 0x4238, + .mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */ + .shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */ + .value = 0x2, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4240, /* SPECIFIC_CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4248, /* SPECIFIC_CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE0123_RDI_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IFE0123_PRIORITYLUT_LOW */ + .offset = 0x3630, + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IFE0123_PRIORITYLUT_HIGH */ + .offset = 0x3634, + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x3638, /* SPECIFIC_IFE0123_URGENCY_LOW */ + /* SPECIFIC_IFE0123_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE0123_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3640, /* SPECIFIC_IFE0123_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3648, /* SPECIFIC_IFE0123_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE0_NRDI_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3A30, /* SPECIFIC_IFE0_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3A34, /* SPECIFIC_IFE0_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x3A38, /* SPECIFIC_IFE0_URGENCY_LOW */ + /* SPECIFIC_IFE0_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE0_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3A40, /* SPECIFIC_IFE0_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3A48, /* SPECIFIC_IFE0_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3B88, /* SPECIFIC_IFE0_ENCCTL_LOW */ + .value = 1, + }, + }, + { + /* IFE0/1 RDI READ PATH */ + .port_type = CAM_CAMNOC_IFE01_RDI_READ, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3230, /* SPECIFIC_IFE1_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3234, /* SPECIFIC_IFE1_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x3238, /* SPECIFIC_IFE1_URGENCY_LOW */ + /* SPECIFIC_IFE1_URGENCY_LOW_WRITE_MASK */ + .mask = 0x7, + /* SPECIFIC_IFE1_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x0, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3240, /* SPECIFIC_IFE1_DANGERLUT_LOW */ + .value = 0x00000000, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x3248, /* SPECIFIC_IFE1_SAFELUT_LOW */ + .value = 0xFFFFFFFF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE1_NRDI_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5430, /* SPECIFIC_IFE1_WR_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IFE1_WR_PRIORITYLUT_HIGH */ + .offset = 0x5434, + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x5438, /* SPECIFIC_IFE1_WR_URGENCY_LOW */ + /* SPECIFIC_IFE1_WR_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IFE1_WR_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x5440, /* SPECIFIC_IFE1_WR_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x5448, /* SPECIFIC_IFE1_WR_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5588, /* SPECIFIC_IFE1_WR_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_READ, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x2E38, /* SPECIFIC_IBL_RD_URGENCY_LOW */ + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */ + .mask = 0x7, + /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */ + .shift = 0x0, + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2F08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2A30, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2A34, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + .offset = 0x2A38, /* SPECIFIC_IBL_WR_URGENCY_LOW */ + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */ + .mask = 0x70, + /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */ + .shift = 0x4, + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2A40, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2A48, /* SPECIFIC_IBL_WR_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2B88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ + .value = 0, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_VID_DISP_WRITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IPE_VID_DISP_PRIORITYLUT_LOW */ + .offset = 0x5E30, + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IPE_VID_DISP_PRIORITYLUT_HIGH */ + .offset = 0x5E34, + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 1, + /* SPECIFIC_IPE_VID_DISP_URGENCY_LOW */ + .offset = 0x5E38, + /* SPECIFIC_IPE_VID_DISP_URGENCY_LOW_READ_MASK */ + .mask = 0x70, + /* SPECIFIC_IPE_VID_DISP_URGENCY_LOW_READ_SHIFT */ + .shift = 0x4, + .value = 3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC__IPE_VID_DISP_DANGERLUT_LOW */ + .offset = 0x5E40, + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* SPECIFIC_IPE_VID_DISP_SAFELUT_LOW */ + .offset = 0x5E48, + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5F88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ + .value = 1, + }, + }, + + { + .port_type = CAM_CAMNOC_JPEG, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2630, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2634, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2638, /* SPECIFIC_JPEG_URGENCY_LOW */ + .value = 0x22, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2640, /* SPECIFIC_JPEG_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2648, /* SPECIFIC_JPEG_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_FD, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3E30, /* SPECIFIC_FD_PRIORITYLUT_LOW */ + .value = 0x44444444, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3E34, /* SPECIFIC_FD_PRIORITYLUT_HIGH */ + .value = 0x44444444, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3E38, /* SPECIFIC_FD_URGENCY_LOW */ + .value = 0x44, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3E40, /* SPECIFIC_FD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3E48, /* SPECIFIC_FD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + + }, + { + /*SidebandManager_main_SidebandManager_FlagOutSet0_Low*/ + .port_type = CAM_CAMNOC_ICP, + .enable = true, + .flag_out_set0_low = { + .enable = true, + .access_type = CAM_REG_TYPE_WRITE, + .masked_value = 0, + .offset = 0x2288, + .value = 0x100000, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam175_cpas130_err_logger_offsets = { + .mainctrl = 0x4F08, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0x4F10, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0x4F20, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0x4F24, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0x4F28, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0x4F2c, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0x4F30, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0x4F34, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0x4F38, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0x4F3c, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam175_cpas130_errata_wa_list = { + .camnoc_flush_slave_pending_trans = { + .enable = false, + .data.reg_info = { + .access_type = CAM_REG_TYPE_READ, + .offset = 0x2300, /* SidebandManager_SenseIn0_Low */ + .mask = 0xE0000, /* Bits 17, 18, 19 */ + .value = 0, /* expected to be 0 */ + }, + }, + /* TZ owned register */ + .tcsr_camera_hf_sf_ares_glitch = { + .enable = true, + .data.reg_info = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + /* TCSR_CAMERA_HF_SF_ARES_GLITCH_MASK */ + .offset = 0x01FCA08C, + .value = 0x4, /* set bit[2] to 1 */ + }, + }, +}; + +static struct cam_camnoc_info cam175_cpas130_camnoc_info = { + .specific = &cam_cpas_v175_130_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v175_130_camnoc_specific), + .irq_sbm = &cam_cpas_v175_130_irq_sbm, + .irq_err = &cam_cpas_v175_130_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v175_130_irq_err), + .err_logger = &cam175_cpas130_err_logger_offsets, + .errata_wa_list = &cam175_cpas130_errata_wa_list, +}; + +#endif /* _CPASTOP_V175_130_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v480_100.h b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v480_100.h new file mode 100644 index 0000000000000000000000000000000000000000..0d46e0ddcc2001112c696f6b1374f5a23c77ff82 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v480_100.h @@ -0,0 +1,711 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V480_100_H_ +#define _CPASTOP_V480_100_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v480_100_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x3840, /* SBM_FAULTINEN0_LOW */ + .value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + (TEST_IRQ_ENABLE ? + 0x40 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x3848, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x3880, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x5 : 0x1, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v480_100_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = false, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x7008, /* ERL_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x7010, /* ERL_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x7018, /* ERL_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x1BA0, /* IFE_UBWC_STATS_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x1B90, /* IFE_UBWC_STATS_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x1B98, /* IFE_UBWC_STATS_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2520, /* IPE1_BPS_RD_DECERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2510, /* IPE1_BPS_RD_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2518, /* IPE1_BPS_RD_DECERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x1F20, /* IPE0_RD_DECERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x1F10, /* IPE0_RD_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x1F18, /* IPE0_RD_DECERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x29A0, /* IPE_BPS_WR_ENCERREN_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2990, + /* IPE_BPS_WR_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2998, /* IPE_BPS_WR_ENCERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = false, + .sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x3888, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x3890, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x3888, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x5, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x3890, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + +static struct cam_camnoc_specific + cam_cpas_v480_100_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x30, /* CDM_PRIORITYLUT_LOW */ + .value = 0x0, + }, + .priority_lut_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x34, /* CDM_PRIORITYLUT_HIGH */ + .value = 0x0, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x38, /* CDM_URGENCY_LOW */ + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x40, /* CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x48, /* CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_FD, + .enable = true, + .priority_lut_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x630, /* FD_PRIORITYLUT_LOW */ + .value = 0x0, + }, + .priority_lut_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x634, /* FD_PRIORITYLUT_HIGH */ + .value = 0x0, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x638, /* FD_URGENCY_LOW */ + .value = 0x33, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x640, /* FD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x648, /* FD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE_LINEAR, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xA30, /* IFE_LINEAR_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xA34, /* IFE_LINEAR_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xA38, /* IFE_LINEAR_URGENCY_LOW */ + .value = 0x1030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0xA40, /* IFE_LINEAR_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0xA48, /* IFE_LINEAR_SAFELUT_LOW */ + .value = 0x000F, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE_RDI_RD, + .enable = true, + .priority_lut_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1030, /* IFE_RDI_RD_PRIORITYLUT_LOW */ + .value = 0x0, + }, + .priority_lut_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1034, /* IFE_RDI_RD_PRIORITYLUT_HIGH */ + .value = 0x0, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1038, /* IFE_RDI_RD_URGENCY_LOW */ + .value = 0x3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x1040, /* IFE_RDI_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x1048, /* IFE_RDI_RD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE_RDI_WR, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1430, /* IFE_RDI_WR_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1434, /* IFE_RDI_WR_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1438, /* IFE_RDI_WR_URGENCY_LOW */ + .value = 0x1030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x1440, /* IFE_RDI_WR_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x1448, /* IFE_RDI_WR_SAFELUT_LOW */ + .value = 0x000F, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_IFE_UBWC_STATS, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1A30, /* IFE_UBWC_STATS_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1A34, /* IFE_UBWC_STATS_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1A38, /* IFE_UBWC_STATS_URGENCY_LOW */ + .value = 0x1030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x1A40, /* IFE_UBWC_STATS_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x1A48, /* IFE_UBWC_STATS_SAFELUT_LOW */ + .value = 0x000F, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1B88, /* IFE_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE0_RD, + .enable = true, + .priority_lut_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1E30, /* IPE0_RD_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1E34, /* IPE0_RD_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1E38, /* IPE0_RD_URGENCY_LOW */ + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1E40, /* IPE0_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1E48, /* IPE0_RD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x1F08, /* IPE0_RD_DECCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE1_BPS_RD, + .enable = true, + .priority_lut_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2430, /* IPE1_BPS_RD_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2434, /* IPE1_BPS_RD_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2438, /* IPE1_BPS_RD_URGENCY_LOW */ + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2440, /* IPE1_BPS_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2448, /* IPE1_BPS_RD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2508, /* IPE1_BPS_RD_DECCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_BPS_WR, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2830, /* IPE_BPS_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2834, /* IPE_BPS_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2838, /* IPE_BPS_WR_URGENCY_LOW */ + .value = 0x30, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2840, /* IPE_BPS_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2848, /* IPE_BPS_WR_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2988, /* IPE_BPS_WR_ENCCTL_LOW */ + .value = 1, + }, + }, + { + .port_type = CAM_CAMNOC_JPEG, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E30, /* JPEG_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E34, /* JPEG_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E38, /* JPEG_URGENCY_LOW */ + .value = 0x22, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E40, /* JPEG_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x2E48, /* JPEG_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_ICP, + .enable = true, + .flag_out_set0_low = { + .enable = true, + .access_type = CAM_REG_TYPE_WRITE, + .masked_value = 0, + .offset = 0x2088, + .value = 0x100000, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam480_cpas100_err_logger_offsets = { + .mainctrl = 0x7008, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0x7010, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0x7020, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0x7024, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0x7028, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0x702c, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0x7030, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0x7034, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0x7038, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0x703c, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam480_cpas100_errata_wa_list = { + .camnoc_flush_slave_pending_trans = { + .enable = false, + .data.reg_info = { + .access_type = CAM_REG_TYPE_READ, + .offset = 0x2100, /* SidebandManager_SenseIn0_Low */ + .mask = 0xE0000, /* Bits 17, 18, 19 */ + .value = 0, /* expected to be 0 */ + }, + }, +}; + +static struct cam_camnoc_info cam480_cpas100_camnoc_info = { + .specific = &cam_cpas_v480_100_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v480_100_camnoc_specific), + .irq_sbm = &cam_cpas_v480_100_irq_sbm, + .irq_err = &cam_cpas_v480_100_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v480_100_irq_err), + .err_logger = &cam480_cpas100_err_logger_offsets, + .errata_wa_list = &cam480_cpas100_errata_wa_list, +}; + +#endif /* _CPASTOP_V480_100_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v520_100.h b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v520_100.h new file mode 100644 index 0000000000000000000000000000000000000000..ec99574ebf10ef72754486e23ff90cbaf0ad60f7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v520_100.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V520_100_H_ +#define _CPASTOP_V520_100_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v520_100_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA40, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + (TEST_IRQ_ENABLE ? + 0x2 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */ + 0x0) /* SBM_FAULTINEN0_LOW_PORT1_MASK */, + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA48, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x3 : 0x1, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v520_100_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xD08, /* ERRORLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xD10, /* ERRORLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xD18, /* ERRORLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA88, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA90, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + + +static struct cam_camnoc_specific + cam_cpas_v520_100_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE30, /* CDM_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE34, /* CDM_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE38, /* CDM_URGENCY_LOW */ + .value = 0x00000003, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE40, /* CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE48, /* CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_TFE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_LOW */ + .offset = 0x30, + .value = 0x44443333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_HIGH */ + .offset = 0x34, + .value = 0x66665555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x38, /* TFE_URGENCY_LOW */ + .value = 0x00001030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x40, /* TFE_DANGERLUT_LOW */ + .value = 0xffff0000, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x48, /* TFE_SAFELUT_LOW */ + .value = 0x00000003, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_OPE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x430, /* OPE_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x434, /* OPE_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x438, /* OPE_URGENCY_LOW */ + .value = 0x00000033, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x440, /* OPE_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x448, /* OPE_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam520_cpas100_err_logger_offsets = { + .mainctrl = 0xD08, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0xD10, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0xD20, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0xD24, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0xD28, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0xD2C, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0xD30, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0xD34, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0xD38, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0xD3C, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_camnoc_info cam520_cpas100_camnoc_info = { + .specific = &cam_cpas_v520_100_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v520_100_camnoc_specific), + .irq_sbm = &cam_cpas_v520_100_irq_sbm, + .irq_err = &cam_cpas_v520_100_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v520_100_irq_err), + .err_logger = &cam520_cpas100_err_logger_offsets, + .errata_wa_list = NULL, +}; + +#endif /* _CPASTOP_V520_100_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v540_100.h b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v540_100.h new file mode 100644 index 0000000000000000000000000000000000000000..1357e586d26f7cb7ac0dff40482abf435cd8892d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v540_100.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V540_100_H_ +#define _CPASTOP_V540_100_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v540_100_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA40, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + (TEST_IRQ_ENABLE ? + 0x2 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */ + 0x0) /* SBM_FAULTINEN0_LOW_PORT1_MASK */, + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA48, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x3 : 0x1, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v540_100_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xD08, /* ERRORLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xD10, /* ERRORLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xD18, /* ERRORLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA88, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA90, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + + +// TODO: Need to update cam_cpas_v540_100_camnoc_specific values based on QoS +static struct cam_camnoc_specific + cam_cpas_v540_100_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE30, /* CDM_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE34, /* CDM_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE38, /* CDM_URGENCY_LOW */ + .value = 0x00000003, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE40, /* CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE48, /* CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_TFE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_LOW */ + .offset = 0x30, + .value = 0x44443333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_HIGH */ + .offset = 0x34, + .value = 0x66665555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x38, /* TFE_URGENCY_LOW */ + .value = 0x00001030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x40, /* TFE_DANGERLUT_LOW */ + .value = 0xffff0000, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x48, /* TFE_SAFELUT_LOW */ + .value = 0x00000003, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_OPE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x430, /* OPE_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x434, /* OPE_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x438, /* OPE_URGENCY_LOW */ + .value = 0x00000033, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x440, /* OPE_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x448, /* OPE_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam540_cpas100_err_logger_offsets = { + .mainctrl = 0xD08, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0xD10, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0xD20, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0xD24, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0xD28, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0xD2C, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0xD30, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0xD34, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0xD38, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0xD3C, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_camnoc_info cam540_cpas100_camnoc_info = { + .specific = &cam_cpas_v540_100_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v540_100_camnoc_specific), + .irq_sbm = &cam_cpas_v540_100_irq_sbm, + .irq_err = &cam_cpas_v540_100_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v540_100_irq_err), + .err_logger = &cam540_cpas100_err_logger_offsets, + .errata_wa_list = NULL, +}; + +#endif /* _CPASTOP_V540_100_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v545_110_518.h b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v545_110_518.h new file mode 100644 index 0000000000000000000000000000000000000000..2948f42178782ec31800030931f72cd32da6440d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/cpastop_v545_110_518.h @@ -0,0 +1,320 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V545_110_518_H_ +#define _CPASTOP_V545_110_518_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v545_110_socid518_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA40, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + (TEST_IRQ_ENABLE ? + 0x2 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */ + 0x0) /* SBM_FAULTINEN0_LOW_PORT1_MASK */, + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA48, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x3 : 0x1, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v545_110_socid518_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xD08, /* ERRORLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xD10, /* ERRORLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xD18, /* ERRORLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA88, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA90, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + + +static struct cam_camnoc_specific + cam_cpas_v545_110_socid518_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE30, /* CDM_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE34, /* CDM_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE38, /* CDM_URGENCY_LOW */ + .value = 0x00000003, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE40, /* CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE48, /* CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_TFE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_LOW */ + .offset = 0x30, + .value = 0x44443333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_HIGH */ + .offset = 0x34, + .value = 0x66665555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x38, /* TFE_URGENCY_LOW */ + .value = 0x00001030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x40, /* TFE_DANGERLUT_LOW */ + .value = 0xFFFF0000, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x48, /* TFE_SAFELUT_LOW */ + .value = 0x00000003, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_TFE_1, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_LOW */ + .offset = 0x4030, + .value = 0x44443333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_HIGH */ + .offset = 0x4034, + .value = 0x66665555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4038, /* TFE_URGENCY_LOW */ + .value = 0x00001030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x4040, /* TFE_DANGERLUT_LOW */ + .value = 0xFFFF0000, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x4048, /* TFE_SAFELUT_LOW */ + .value = 0x00000003, + }, + }, + { + .port_type = CAM_CAMNOC_TFE_2, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_LOW */ + .offset = 0x5030, + .value = 0x44443333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_HIGH */ + .offset = 0x5034, + .value = 0x66665555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5038, /* TFE_URGENCY_LOW */ + .value = 0x00001030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x5040, /* TFE_DANGERLUT_LOW */ + .value = 0xFFFF0000, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x5048, /* TFE_SAFELUT_LOW */ + .value = 0x00000003, + }, + }, + { + .port_type = CAM_CAMNOC_OPE, + .enable = true, + .priority_lut_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x430, /* OPE_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x434, /* OPE_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x438, /* OPE_URGENCY_LOW */ + .value = 0x00000033, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x440, /* OPE_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x448, /* OPE_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, +}; + +static struct cam_camnoc_err_logger_info + cam545_cpas110_socid518_err_logger_offsets = { + .mainctrl = 0xD08, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0xD10, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0xD20, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0xD24, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0xD28, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0xD2C, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0xD30, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0xD34, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0xD38, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0xD3C, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_camnoc_info cam545_cpas110_socid518_camnoc_info = { + .specific = &cam_cpas_v545_110_socid518_camnoc_specific[0], + .specific_size = + ARRAY_SIZE(cam_cpas_v545_110_socid518_camnoc_specific), + .irq_sbm = &cam_cpas_v545_110_socid518_irq_sbm, + .irq_err = &cam_cpas_v545_110_socid518_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v545_110_socid518_irq_err), + .err_logger = &cam545_cpas110_socid518_err_logger_offsets, + .errata_wa_list = NULL, +}; + +#endif /* _CPASTOP_V545_110_518_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cpas/include/cam_cpas_api.h b/techpack/camera-bengal/drivers/cam_cpas/include/cam_cpas_api.h new file mode 100644 index 0000000000000000000000000000000000000000..4c1a51119693497762383e646fc4469360d5e1ac --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cpas/include/cam_cpas_api.h @@ -0,0 +1,593 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CPAS_API_H_ +#define _CAM_CPAS_API_H_ + +#include +#include + +#include +#include "cam_soc_util.h" + +#define CAM_HW_IDENTIFIER_LENGTH 128 + +/* Default AXI Bandwidth vote */ +#define CAM_CPAS_DEFAULT_AXI_BW 1024 + +#define CAM_CPAS_MAX_PATHS_PER_CLIENT 15 +#define CAM_CPAS_API_PATH_DATA_STD_START 512 + +/** + * enum cam_cpas_reg_base - Enum for register base identifier. These + * are the identifiers used in generic register + * write/read APIs provided by cpas driver. + */ +enum cam_cpas_reg_base { + CAM_CPAS_REG_CPASTOP, + CAM_CPAS_REG_CAMNOC, + CAM_CPAS_REG_CAMSS, + CAM_CPAS_REG_MAX +}; + +/** + * enum cam_cpas_hw_version - Enum for Titan CPAS HW Versions + */ +enum cam_cpas_hw_version { + CAM_CPAS_TITAN_NONE = 0, + CAM_CPAS_TITAN_150_V100 = 0x150100, + CAM_CPAS_TITAN_170_V100 = 0x170100, + CAM_CPAS_TITAN_170_V110 = 0x170110, + CAM_CPAS_TITAN_170_V120 = 0x170120, + CAM_CPAS_TITAN_175_V100 = 0x175100, + CAM_CPAS_TITAN_175_V101 = 0x175101, + CAM_CPAS_TITAN_175_V120 = 0x175120, + CAM_CPAS_TITAN_175_V130 = 0x175130, + CAM_CPAS_TITAN_480_V100 = 0x480100, + CAM_CPAS_TITAN_540_V100 = 0x540100, + CAM_CPAS_TITAN_520_V100 = 0x520100, + CAM_CPAS_TITAN_545_V110 = 0x545110, + CAM_CPAS_TITAN_MAX +}; + +/** + * enum cam_cpas_hw_soc_id - Enum for Titan soc id + */ +enum cam_cpas_hw_soc_id { + CAM_CPAS_TITAN_SOC_ID_507 = 507, + CAM_CPAS_TITAN_SOC_ID_518 = 518, + CAM_CPAS_TITAN_SOC_ID_MAX +}; + +/** + * enum cam_camnoc_irq_type - Enum for camnoc irq types + * + * @CAM_CAMNOC_IRQ_SLAVE_ERROR: Each slave port in CAMNOC (3 QSB ports and + * 1 QHB port) has an error logger. The error + * observed at any slave port is logged into + * the error logger register and an IRQ is + * triggered + * @CAM_CAMNOC_IRQ_IFE_UBWC_STATS_ENCODE_ERROR: Triggered if any error detected + * in the IFE UBWC-Stats encoder + * instance + * @CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR : Triggered if any error detected + * in the IFE0 UBWC encoder instance + * @CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR : Triggered if any error detected + * in the IFE1 or IFE3 UBWC encoder + * instance + * @CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR : Triggered if any error detected + * in the IFE0 UBWC encoder instance + * @CAM_CAMNOC_IRQ_IFE1_WR_UBWC_ENCODE_ERROR : Triggered if any error detected + * in the IFE1 UBWC encoder + * instance + * @CAM_CAMNOC_IRQ_IPE1_BPS_UBWC_DECODE_ERROR: Triggered if any error detected + * in the IPE1/BPS read path decoder + * instance + * @CAM_CAMNOC_IRQ_IPE0_UBWC_DECODE_ERROR : Triggered if any error detected + * in the IPE0 read path decoder + * instance + * @CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR: Triggered if any error detected + * in the IPE/BPS UBWC decoder + * instance + * @CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR: Triggered if any error detected + * in the IPE/BPS UBWC encoder + * instance + * @CAM_CAMNOC_IRQ_AHB_TIMEOUT : Triggered when the QHS_ICP slave + * times out after 4000 AHB cycles + */ +enum cam_camnoc_irq_type { + CAM_CAMNOC_IRQ_SLAVE_ERROR, + CAM_CAMNOC_IRQ_IFE_UBWC_STATS_ENCODE_ERROR, + CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR, + CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR, + CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR, + CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR, + CAM_CAMNOC_IRQ_IPE1_BPS_UBWC_DECODE_ERROR, + CAM_CAMNOC_IRQ_IPE0_UBWC_DECODE_ERROR, + CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR, + CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR, + CAM_CAMNOC_IRQ_AHB_TIMEOUT, +}; + +/** + * struct cam_camnoc_irq_slave_err_data : Data for Slave error. + * + * @mainctrl : Err logger mainctrl info + * @errvld : Err logger errvld info + * @errlog0_low : Err logger errlog0_low info + * @errlog0_high : Err logger errlog0_high info + * @errlog1_low : Err logger errlog1_low info + * @errlog1_high : Err logger errlog1_high info + * @errlog2_low : Err logger errlog2_low info + * @errlog2_high : Err logger errlog2_high info + * @errlog3_low : Err logger errlog3_low info + * @errlog3_high : Err logger errlog3_high info + * + */ +struct cam_camnoc_irq_slave_err_data { + union { + struct { + uint32_t stall_en : 1; /* bit 0 */ + uint32_t fault_en : 1; /* bit 1 */ + uint32_t rsv : 30; /* bits 2-31 */ + }; + uint32_t value; + } mainctrl; + union { + struct { + uint32_t err_vld : 1; /* bit 0 */ + uint32_t rsv : 31; /* bits 1-31 */ + }; + uint32_t value; + } errvld; + union { + struct { + uint32_t loginfo_vld : 1; /* bit 0 */ + uint32_t word_error : 1; /* bit 1 */ + uint32_t non_secure : 1; /* bit 2 */ + uint32_t device : 1; /* bit 3 */ + uint32_t opc : 3; /* bits 4 - 6 */ + uint32_t rsv0 : 1; /* bit 7 */ + uint32_t err_code : 3; /* bits 8 - 10 */ + uint32_t sizef : 3; /* bits 11 - 13 */ + uint32_t rsv1 : 2; /* bits 14 - 15 */ + uint32_t addr_space : 6; /* bits 16 - 21 */ + uint32_t rsv2 : 10; /* bits 22 - 31 */ + }; + uint32_t value; + } errlog0_low; + union { + struct { + uint32_t len1 : 10; /* bits 0 - 9 */ + uint32_t rsv : 22; /* bits 10 - 31 */ + }; + uint32_t value; + } errlog0_high; + union { + struct { + uint32_t path : 16; /* bits 0 - 15 */ + uint32_t rsv : 16; /* bits 16 - 31 */ + }; + uint32_t value; + } errlog1_low; + union { + struct { + uint32_t extid : 18; /* bits 0 - 17 */ + uint32_t rsv : 14; /* bits 18 - 31 */ + }; + uint32_t value; + } errlog1_high; + union { + struct { + uint32_t errlog2_lsb : 32; /* bits 0 - 31 */ + }; + uint32_t value; + } errlog2_low; + union { + struct { + uint32_t errlog2_msb : 16; /* bits 0 - 16 */ + uint32_t rsv : 16; /* bits 16 - 31 */ + }; + uint32_t value; + } errlog2_high; + union { + struct { + uint32_t errlog3_lsb : 32; /* bits 0 - 31 */ + }; + uint32_t value; + } errlog3_low; + union { + struct { + uint32_t errlog3_msb : 32; /* bits 0 - 31 */ + }; + uint32_t value; + } errlog3_high; +}; + +/** + * struct cam_camnoc_irq_ubwc_enc_data : Data for UBWC Encode error. + * + * @encerr_status : Encode error status + * + */ +struct cam_camnoc_irq_ubwc_enc_data { + union { + struct { + uint32_t encerrstatus : 3; /* bits 0 - 2 */ + uint32_t rsv : 29; /* bits 3 - 31 */ + }; + uint32_t value; + } encerr_status; +}; + +/** + * struct cam_camnoc_irq_ubwc_dec_data : Data for UBWC Decode error. + * + * @decerr_status : Decoder error status + * @thr_err : Set to 1 if + * At least one of the bflc_len fields in the bit steam exceeds + * its threshold value. This error is possible only for + * RGBA1010102, TP10, and RGB565 formats + * @fcl_err : Set to 1 if + * Fast clear with a legal non-RGB format + * @len_md_err : Set to 1 if + * The calculated burst length does not match burst length + * specified by the metadata value + * @format_err : Set to 1 if + * Illegal format + * 1. bad format :2,3,6 + * 2. For 32B MAL, metadata=6 + * 3. For 32B MAL RGB565, Metadata != 0,1,7 + * 4. For 64B MAL RGB565, metadata[3:1] == 1,2 + * + */ +struct cam_camnoc_irq_ubwc_dec_data { + union { + struct { + uint32_t thr_err : 1; /* bit 0 */ + uint32_t fcl_err : 1; /* bit 1 */ + uint32_t len_md_err : 1; /* bit 2 */ + uint32_t format_err : 1; /* bit 3 */ + uint32_t rsv : 28; /* bits 4 - 31 */ + }; + uint32_t value; + } decerr_status; +}; + +struct cam_camnoc_irq_ahb_timeout_data { + uint32_t data; +}; + +/** + * struct cam_cpas_irq_data : CAMNOC IRQ data + * + * @irq_type : To identify the type of IRQ + * @u : Union of irq err data information + * @slave_err : Data for Slave error. + * Valid if type is CAM_CAMNOC_IRQ_SLAVE_ERROR + * @enc_err : Data for UBWC Encode error. + * Valid if type is one of below: + * CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR + * CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR + * CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR + * @dec_err : Data for UBWC Decode error. + * Valid if type is CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR + * @ahb_err : Data for Slave error. + * Valid if type is CAM_CAMNOC_IRQ_AHB_TIMEOUT + * + */ +struct cam_cpas_irq_data { + enum cam_camnoc_irq_type irq_type; + union { + struct cam_camnoc_irq_slave_err_data slave_err; + struct cam_camnoc_irq_ubwc_enc_data enc_err; + struct cam_camnoc_irq_ubwc_dec_data dec_err; + struct cam_camnoc_irq_ahb_timeout_data ahb_err; + } u; +}; + +/** + * struct cam_cpas_register_params : Register params for cpas client + * + * @identifier : Input identifier string which is the device label + * from dt like vfe, ife, jpeg etc + * @cell_index : Input integer identifier pointing to the cell index + * from dt of the device. This can be used to form a + * unique string with @identifier like vfe0, ife1, + * jpeg0, etc + * @dev : device handle + * @userdata : Input private data which will be passed as + * an argument while callback. + * @cam_cpas_callback : Input callback pointer for triggering the + * callbacks from CPAS driver. + * @client_handle : CPAS client handle + * @userdata : User data given at the time of register + * @event_type : event type + * @event_data : event data + * @client_handle : Output Unique handle generated for this register + * + */ +struct cam_cpas_register_params { + char identifier[CAM_HW_IDENTIFIER_LENGTH]; + uint32_t cell_index; + struct device *dev; + void *userdata; + bool (*cam_cpas_client_cb)( + uint32_t client_handle, + void *userdata, + struct cam_cpas_irq_data *irq_data); + uint32_t client_handle; +}; + +/** + * enum cam_vote_type - Enum for voting type + * + * @CAM_VOTE_ABSOLUTE : Absolute vote + * @CAM_VOTE_DYNAMIC : Dynamic vote + */ +enum cam_vote_type { + CAM_VOTE_ABSOLUTE, + CAM_VOTE_DYNAMIC, +}; + +/** + * struct cam_ahb_vote : AHB vote + * + * @type : AHB voting type. + * CAM_VOTE_ABSOLUTE : vote based on the value 'level' is set + * CAM_VOTE_DYNAMIC : vote calculated dynamically using 'freq' + * and 'dev' handle is set + * @level : AHB vote level + * @freq : AHB vote dynamic frequency + * + */ +struct cam_ahb_vote { + enum cam_vote_type type; + union { + enum cam_vote_level level; + unsigned long freq; + } vote; +}; + +/** + * struct cam_axi_vote : AXI vote + * + * @num_paths: Number of paths on which BW vote is sent to CPAS + * @axi_path: Per path BW vote info + * + */ +struct cam_axi_vote { + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[CAM_CPAS_MAX_PATHS_PER_CLIENT]; +}; + +/** + * cam_cpas_register_client() + * + * @brief: API to register cpas client + * + * @register_params: Input params to register as a client to CPAS + * + * @return 0 on success. + * + */ +int cam_cpas_register_client( + struct cam_cpas_register_params *register_params); + +/** + * cam_cpas_unregister_client() + * + * @brief: API to unregister cpas client + * + * @client_handle: Client handle to be unregistered + * + * @return 0 on success. + * + */ +int cam_cpas_unregister_client(uint32_t client_handle); + +/** + * cam_cpas_start() + * + * @brief: API to start cpas client hw. Clients have to vote for minimal + * bandwidth requirements for AHB, AXI. Use cam_cpas_update_ahb_vote + * to scale bandwidth after start. + * + * @client_handle: client cpas handle + * @ahb_vote : Pointer to ahb vote info + * @axi_vote : Pointer to axi bandwidth vote info + * + * If AXI vote is not applicable to a particular client, use the value exposed + * by CAM_CPAS_DEFAULT_AXI_BW as the default vote request. + * + * @return 0 on success. + * + */ +int cam_cpas_start( + uint32_t client_handle, + struct cam_ahb_vote *ahb_vote, + struct cam_axi_vote *axi_vote); + +/** + * cam_cpas_stop() + * + * @brief: API to stop cpas client hw. Bandwidth for AHB, AXI votes + * would be removed for this client on this call. Clients should not + * use cam_cpas_update_ahb_vote or cam_cpas_update_axi_vote + * to remove their bandwidth vote. + * + * @client_handle: client cpas handle + * + * @return 0 on success. + * + */ +int cam_cpas_stop(uint32_t client_handle); + +/** + * cam_cpas_update_ahb_vote() + * + * @brief: API to update AHB vote requirement. Use this function only + * between cam_cpas_start and cam_cpas_stop in case clients wants + * to scale to different vote level. Do not use this function to de-vote, + * removing client's vote is implicit on cam_cpas_stop + * + * @client_handle : Client cpas handle + * @ahb_vote : Pointer to ahb vote info + * + * @return 0 on success. + * + */ +int cam_cpas_update_ahb_vote( + uint32_t client_handle, + struct cam_ahb_vote *ahb_vote); + +/** + * cam_cpas_update_axi_vote() + * + * @brief: API to update AXI vote requirement. Use this function only + * between cam_cpas_start and cam_cpas_stop in case clients wants + * to scale to different vote level. Do not use this function to de-vote, + * removing client's vote is implicit on cam_cpas_stop + * + * @client_handle : Client cpas handle + * @axi_vote : Pointer to axi bandwidth vote info + * + * @return 0 on success. + * + */ +int cam_cpas_update_axi_vote( + uint32_t client_handle, + struct cam_axi_vote *axi_vote); + +/** + * cam_cpas_reg_write() + * + * @brief: API to write a register value in CPAS register space + * + * @client_handle : Client cpas handle + * @reg_base : Register base identifier + * @offset : Offset from the register base address + * @mb : Whether to do reg write with memory barrier + * @value : Value to be written in register + * + * @return 0 on success. + * + */ +int cam_cpas_reg_write( + uint32_t client_handle, + enum cam_cpas_reg_base reg_base, + uint32_t offset, + bool mb, + uint32_t value); + +/** + * cam_cpas_reg_read() + * + * @brief: API to read a register value from CPAS register space + * + * @client_handle : Client cpas handle + * @reg_base : Register base identifier + * @offset : Offset from the register base address + * @mb : Whether to do reg read with memory barrier + * @value : Value to be red from register + * + * @return 0 on success. + * + */ +int cam_cpas_reg_read( + uint32_t client_handle, + enum cam_cpas_reg_base reg_base, + uint32_t offset, + bool mb, + uint32_t *value); + +/** + * cam_cpas_get_hw_info() + * + * @brief: API to get camera hw information + * + * @camera_family : Camera family type. One of + * CAM_FAMILY_CAMERA_SS + * CAM_FAMILY_CPAS_SS + * @camera_version : Camera platform version + * @cpas_version : Camera cpas version + * @cam_caps : Camera capability + * + * @return 0 on success. + * + */ +int cam_cpas_get_hw_info( + uint32_t *camera_family, + struct cam_hw_version *camera_version, + struct cam_hw_version *cpas_version, + uint32_t *cam_caps); + +/** + * cam_cpas_get_cpas_hw_version() + * + * @brief: API to get camera cpas hw version + * + * @hw_version : Camera cpas hw version + * + * @return 0 on success. + * + */ +int cam_cpas_get_cpas_hw_version( + uint32_t *hw_version); + +/** + * cam_cpas_is_feature_supported() + * + * @brief: API to get camera features + * + * @flag : Camera hw features to check + * + * @hw_id : HW id index, if hw id is not valid feature, send zero + * + * @return true if feature is supported + * false if feature is not supported + * + */ +bool cam_cpas_is_feature_supported(uint32_t flag, + uint32_t hw_id); + +/** + * cam_cpas_axi_util_path_type_to_string() + * + * @brief: API to get string for given path type + * + * @path_data_type : Path type + * + * @return string. + * + */ +const char *cam_cpas_axi_util_path_type_to_string( + uint32_t path_data_type); + +/** + * cam_cpas_axi_util_trans_type_to_string() + * + * @brief: API to get string for given transaction type + * + * @path_data_type : Transaction type + * + * @return string. + * + */ +const char *cam_cpas_axi_util_trans_type_to_string( + uint32_t path_data_type); + +/** + * cam_cpas_log_votes() + * + * @brief: API to print the all bw votes of axi client. It also print the + * applied camnoc axi clock vote value and ahb vote value + * + * @return 0 on success. + * + */ +void cam_cpas_log_votes(void); + +#endif /* _CAM_CPAS_API_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cust/Makefile b/techpack/camera-bengal/drivers/cam_cust/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..a3d6b43e2823107c948b2c41a4bc99a2808d9237 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_custom_hw_mgr/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_custom_dev.o cam_custom_context.o diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_context.c b/techpack/camera-bengal/drivers/cam_cust/cam_custom_context.c new file mode 100644 index 0000000000000000000000000000000000000000..25e092841cefccd5519bf3bac2ccdd549729e052 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_context.c @@ -0,0 +1,1253 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "cam_mem_mgr.h" +#include "cam_sync_api.h" +#include "cam_req_mgr_dev.h" +#include "cam_trace.h" +#include "cam_debug_util.h" +#include "cam_packet_util.h" +#include "cam_context_utils.h" +#include "cam_custom_context.h" +#include "cam_common_util.h" + +static const char custom_dev_name[] = "cam-custom"; + +static int __cam_custom_ctx_handle_irq_in_activated( + void *context, uint32_t evt_id, void *evt_data); + +static int __cam_custom_ctx_start_dev_in_ready( + struct cam_context *ctx, struct cam_start_stop_dev_cmd *cmd); + + +static int __cam_custom_ctx_enqueue_request_in_order( + struct cam_context *ctx, struct cam_ctx_request *req) +{ + struct cam_ctx_request *req_current; + struct cam_ctx_request *req_prev; + struct list_head temp_list; + + INIT_LIST_HEAD(&temp_list); + spin_lock_bh(&ctx->lock); + if (list_empty(&ctx->pending_req_list)) { + list_add_tail(&req->list, &ctx->pending_req_list); + } else { + list_for_each_entry_safe_reverse( + req_current, req_prev, &ctx->pending_req_list, list) { + if (req->request_id < req_current->request_id) { + list_del_init(&req_current->list); + list_add(&req_current->list, &temp_list); + continue; + } else if (req->request_id == req_current->request_id) { + CAM_WARN(CAM_CUSTOM, + "Received duplicated request %lld", + req->request_id); + } + break; + } + list_add_tail(&req->list, &ctx->pending_req_list); + + if (!list_empty(&temp_list)) { + list_for_each_entry_safe( + req_current, req_prev, &temp_list, list) { + list_del_init(&req_current->list); + list_add_tail(&req_current->list, + &ctx->pending_req_list); + } + } + } + spin_unlock_bh(&ctx->lock); + return 0; +} + +static int __cam_custom_ctx_flush_req(struct cam_context *ctx, + struct list_head *req_list, struct cam_req_mgr_flush_request *flush_req) +{ + int i, rc; + uint32_t cancel_req_id_found = 0; + struct cam_ctx_request *req; + struct cam_ctx_request *req_temp; + struct cam_custom_dev_ctx_req *req_custom; + struct list_head flush_list; + + INIT_LIST_HEAD(&flush_list); + if (list_empty(req_list)) { + CAM_DBG(CAM_CUSTOM, "request list is empty"); + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ) { + CAM_ERR(CAM_CUSTOM, "no request to cancel"); + return -EINVAL; + } else { + return 0; + } + } + + CAM_DBG(CAM_CUSTOM, "Flush [%u] in progress for req_id %llu", + flush_req->type, flush_req->req_id); + list_for_each_entry_safe(req, req_temp, req_list, list) { + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ) { + if (req->request_id != flush_req->req_id) { + continue; + } else { + list_del_init(&req->list); + list_add_tail(&req->list, &flush_list); + cancel_req_id_found = 1; + break; + } + } + list_del_init(&req->list); + list_add_tail(&req->list, &flush_list); + } + + list_for_each_entry_safe(req, req_temp, &flush_list, list) { + req_custom = (struct cam_custom_dev_ctx_req *) req->req_priv; + for (i = 0; i < req_custom->num_fence_map_out; i++) { + if (req_custom->fence_map_out[i].sync_id != -1) { + CAM_DBG(CAM_CUSTOM, + "Flush req 0x%llx, fence %d", + req->request_id, + req_custom->fence_map_out[i].sync_id); + rc = cam_sync_signal( + req_custom->fence_map_out[i].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + if (rc) + CAM_ERR_RATE_LIMIT(CAM_CUSTOM, + "signal fence failed\n"); + req_custom->fence_map_out[i].sync_id = -1; + } + } + list_add_tail(&req->list, &ctx->free_req_list); + } + + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ && + !cancel_req_id_found) + CAM_DBG(CAM_CUSTOM, + "Flush request id:%lld is not found in the list", + flush_req->req_id); + + return 0; +} + +static int __cam_custom_ctx_unlink_in_acquired(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *unlink) +{ + ctx->link_hdl = -1; + ctx->ctx_crm_intf = NULL; + + return 0; +} + +static int __cam_custom_ctx_unlink_in_ready(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *unlink) +{ + ctx->link_hdl = -1; + ctx->ctx_crm_intf = NULL; + ctx->state = CAM_CTX_ACQUIRED; + + return 0; +} + +static int __cam_custom_ctx_get_dev_info_in_acquired(struct cam_context *ctx, + struct cam_req_mgr_device_info *dev_info) +{ + dev_info->dev_hdl = ctx->dev_hdl; + strlcpy(dev_info->name, CAM_CUSTOM_DEV_NAME, sizeof(dev_info->name)); + dev_info->dev_id = CAM_REQ_MGR_DEVICE_CUSTOM_HW; + dev_info->p_delay = 1; + dev_info->trigger = CAM_TRIGGER_POINT_SOF; + + return 0; +} + +static int __cam_custom_ctx_flush_req_in_top_state( + struct cam_context *ctx, + struct cam_req_mgr_flush_request *flush_req) +{ + int rc = 0; + struct cam_custom_context *custom_ctx; + struct cam_hw_reset_args reset_args; + struct cam_hw_stop_args stop_args; + struct cam_custom_stop_args custom_stop; + + custom_ctx = + (struct cam_custom_context *) ctx->ctx_priv; + + CAM_DBG(CAM_CUSTOM, "Flushing pending list"); + spin_lock_bh(&ctx->lock); + __cam_custom_ctx_flush_req(ctx, &ctx->pending_req_list, flush_req); + spin_unlock_bh(&ctx->lock); + + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) { + if (ctx->state <= CAM_CTX_READY) { + ctx->state = CAM_CTX_ACQUIRED; + goto end; + } + + spin_lock_bh(&ctx->lock); + ctx->state = CAM_CTX_FLUSHED; + spin_unlock_bh(&ctx->lock); + + CAM_INFO(CAM_CUSTOM, "Last request id to flush is %lld", + flush_req->req_id); + ctx->last_flush_req = flush_req->req_id; + + /* stop hw first */ + if (ctx->hw_mgr_intf->hw_stop) { + custom_stop.stop_only = true; + stop_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + stop_args.args = (void *) &custom_stop; + rc = ctx->hw_mgr_intf->hw_stop( + ctx->hw_mgr_intf->hw_mgr_priv, &stop_args); + if (rc) + CAM_ERR(CAM_CUSTOM, + "HW stop failed in flush rc %d", rc); + } + + spin_lock_bh(&ctx->lock); + if (!list_empty(&ctx->wait_req_list)) + __cam_custom_ctx_flush_req(ctx, &ctx->wait_req_list, + flush_req); + + if (!list_empty(&ctx->active_req_list)) + __cam_custom_ctx_flush_req(ctx, &ctx->active_req_list, + flush_req); + + custom_ctx->active_req_cnt = 0; + spin_unlock_bh(&ctx->lock); + + reset_args.ctxt_to_hw_map = custom_ctx->hw_ctx; + rc = ctx->hw_mgr_intf->hw_reset(ctx->hw_mgr_intf->hw_mgr_priv, + &reset_args); + if (rc) + CAM_ERR(CAM_CUSTOM, + "Reset HW failed in flush rc %d", rc); + + custom_ctx->init_received = false; + } + +end: + return rc; +} + +static int __cam_custom_ctx_flush_req_in_ready( + struct cam_context *ctx, + struct cam_req_mgr_flush_request *flush_req) +{ + int rc = 0; + + CAM_DBG(CAM_CUSTOM, "try to flush pending list"); + spin_lock_bh(&ctx->lock); + rc = __cam_custom_ctx_flush_req(ctx, &ctx->pending_req_list, flush_req); + + /* if nothing is in pending req list, change state to acquire */ + if (list_empty(&ctx->pending_req_list)) + ctx->state = CAM_CTX_ACQUIRED; + spin_unlock_bh(&ctx->lock); + + CAM_DBG(CAM_CUSTOM, "Flush request in ready state. next state %d", + ctx->state); + return rc; +} + +static int __cam_custom_stop_dev_core( + struct cam_context *ctx, struct cam_start_stop_dev_cmd *stop_cmd) +{ + int rc = 0; + uint32_t i; + struct cam_custom_context *ctx_custom = + (struct cam_custom_context *) ctx->ctx_priv; + struct cam_ctx_request *req; + struct cam_custom_dev_ctx_req *req_custom; + struct cam_hw_stop_args stop; + struct cam_custom_stop_args custom_stop; + + if ((ctx->state != CAM_CTX_FLUSHED) && (ctx_custom->hw_ctx) && + (ctx->hw_mgr_intf->hw_stop)) { + custom_stop.stop_only = false; + stop.ctxt_to_hw_map = ctx_custom->hw_ctx; + stop.args = (void *) &custom_stop; + rc = ctx->hw_mgr_intf->hw_stop(ctx->hw_mgr_intf->hw_mgr_priv, + &stop); + if (rc) + CAM_ERR(CAM_CUSTOM, "HW stop failed rc %d", rc); + } + + while (!list_empty(&ctx->pending_req_list)) { + req = list_first_entry(&ctx->pending_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + req_custom = (struct cam_custom_dev_ctx_req *) req->req_priv; + CAM_DBG(CAM_CUSTOM, + "signal fence in pending list. fence num %d", + req_custom->num_fence_map_out); + for (i = 0; i < req_custom->num_fence_map_out; i++) + if (req_custom->fence_map_out[i].sync_id != -1) { + cam_sync_signal( + req_custom->fence_map_out[i].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + } + list_add_tail(&req->list, &ctx->free_req_list); + } + + while (!list_empty(&ctx->wait_req_list)) { + req = list_first_entry(&ctx->wait_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + req_custom = (struct cam_custom_dev_ctx_req *) req->req_priv; + CAM_DBG(CAM_CUSTOM, "signal fence in wait list. fence num %d", + req_custom->num_fence_map_out); + for (i = 0; i < req_custom->num_fence_map_out; i++) + if (req_custom->fence_map_out[i].sync_id != -1) { + cam_sync_signal( + req_custom->fence_map_out[i].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + } + list_add_tail(&req->list, &ctx->free_req_list); + } + + while (!list_empty(&ctx->active_req_list)) { + req = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + req_custom = (struct cam_custom_dev_ctx_req *) req->req_priv; + CAM_DBG(CAM_CUSTOM, "signal fence in active list. fence num %d", + req_custom->num_fence_map_out); + for (i = 0; i < req_custom->num_fence_map_out; i++) + if (req_custom->fence_map_out[i].sync_id != -1) { + cam_sync_signal( + req_custom->fence_map_out[i].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + } + list_add_tail(&req->list, &ctx->free_req_list); + } + ctx_custom->frame_id = 0; + ctx_custom->active_req_cnt = 0; + + CAM_DBG(CAM_CUSTOM, "Stop device success next state %d on ctx %u", + ctx->state, ctx->ctx_id); + + if (!stop_cmd) { + rc = __cam_custom_ctx_unlink_in_ready(ctx, NULL); + if (rc) + CAM_ERR(CAM_CUSTOM, "Unlink failed rc=%d", rc); + } + return rc; +} + +static int __cam_custom_stop_dev_in_activated(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + struct cam_custom_context *ctx_custom = + (struct cam_custom_context *)ctx->ctx_priv; + + __cam_custom_stop_dev_core(ctx, cmd); + ctx_custom->init_received = false; + ctx->state = CAM_CTX_ACQUIRED; + + return 0; +} + +static int __cam_custom_ctx_release_hw_in_top_state( + struct cam_context *ctx, void *cmd) +{ + int rc = 0; + struct cam_hw_release_args rel_arg; + struct cam_req_mgr_flush_request flush_req; + struct cam_custom_context *custom_ctx = + (struct cam_custom_context *) ctx->ctx_priv; + + if (custom_ctx->hw_ctx) { + rel_arg.ctxt_to_hw_map = custom_ctx->hw_ctx; + rc = ctx->hw_mgr_intf->hw_release(ctx->hw_mgr_intf->hw_mgr_priv, + &rel_arg); + custom_ctx->hw_ctx = NULL; + if (rc) + CAM_ERR(CAM_CUSTOM, + "Failed to release HW for ctx:%u", ctx->ctx_id); + } else { + CAM_ERR(CAM_CUSTOM, "No HW resources acquired for this ctx"); + } + + ctx->last_flush_req = 0; + custom_ctx->frame_id = 0; + custom_ctx->active_req_cnt = 0; + custom_ctx->hw_acquired = false; + custom_ctx->init_received = false; + + /* check for active requests as well */ + flush_req.type = CAM_REQ_MGR_FLUSH_TYPE_ALL; + flush_req.link_hdl = ctx->link_hdl; + flush_req.dev_hdl = ctx->dev_hdl; + + CAM_DBG(CAM_CUSTOM, "try to flush pending list"); + spin_lock_bh(&ctx->lock); + rc = __cam_custom_ctx_flush_req(ctx, &ctx->pending_req_list, + &flush_req); + spin_unlock_bh(&ctx->lock); + ctx->state = CAM_CTX_ACQUIRED; + + CAM_DBG(CAM_CUSTOM, "Release HW success[%u] next state %d", + ctx->ctx_id, ctx->state); + + return rc; +} + +static int __cam_custom_ctx_release_hw_in_activated_state( + struct cam_context *ctx, void *cmd) +{ + int rc = 0; + + rc = __cam_custom_stop_dev_in_activated(ctx, NULL); + if (rc) + CAM_ERR(CAM_CUSTOM, "Stop device failed rc=%d", rc); + + rc = __cam_custom_ctx_release_hw_in_top_state(ctx, cmd); + if (rc) + CAM_ERR(CAM_CUSTOM, "Release hw failed rc=%d", rc); + + return rc; +} + +static int __cam_custom_release_dev_in_acquired(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc; + struct cam_custom_context *ctx_custom = + (struct cam_custom_context *) ctx->ctx_priv; + struct cam_req_mgr_flush_request flush_req; + + if (cmd && ctx_custom->hw_ctx) { + CAM_ERR(CAM_CUSTOM, "releasing hw"); + __cam_custom_ctx_release_hw_in_top_state(ctx, NULL); + } + + ctx->ctx_crm_intf = NULL; + ctx->last_flush_req = 0; + ctx_custom->frame_id = 0; + ctx_custom->active_req_cnt = 0; + ctx_custom->hw_acquired = false; + ctx_custom->init_received = false; + + if (!list_empty(&ctx->active_req_list)) + CAM_ERR(CAM_CUSTOM, "Active list is not empty"); + + /* Flush all the pending request list */ + flush_req.type = CAM_REQ_MGR_FLUSH_TYPE_ALL; + flush_req.link_hdl = ctx->link_hdl; + flush_req.dev_hdl = ctx->dev_hdl; + + CAM_DBG(CAM_CUSTOM, "try to flush pending list"); + spin_lock_bh(&ctx->lock); + rc = __cam_custom_ctx_flush_req(ctx, &ctx->pending_req_list, + &flush_req); + spin_unlock_bh(&ctx->lock); + ctx->state = CAM_CTX_AVAILABLE; + + CAM_DBG(CAM_CUSTOM, "Release device success[%u] next state %d", + ctx->ctx_id, ctx->state); + + return rc; +} + +static int __cam_custom_ctx_apply_req_in_activated_state( + struct cam_context *ctx, struct cam_req_mgr_apply_request *apply) +{ + int rc = 0; + struct cam_ctx_request *req; + struct cam_custom_dev_ctx_req *req_custom; + struct cam_custom_context *custom_ctx = NULL; + struct cam_hw_config_args cfg; + + if (list_empty(&ctx->pending_req_list)) { + CAM_ERR(CAM_CUSTOM, "No available request for Apply id %lld", + apply->request_id); + rc = -EFAULT; + goto end; + } + + custom_ctx = (struct cam_custom_context *) ctx->ctx_priv; + spin_lock_bh(&ctx->lock); + req = list_first_entry(&ctx->pending_req_list, struct cam_ctx_request, + list); + spin_unlock_bh(&ctx->lock); + + /* + * Check whether the request id is matching the tip + */ + if (req->request_id != apply->request_id) { + CAM_ERR_RATE_LIMIT(CAM_CUSTOM, + "Invalid Request Id asking %llu existing %llu", + apply->request_id, req->request_id); + rc = -EFAULT; + goto end; + } + + req_custom = (struct cam_custom_dev_ctx_req *) req->req_priv; + + cfg.ctxt_to_hw_map = custom_ctx->hw_ctx; + cfg.request_id = req->request_id; + cfg.hw_update_entries = req_custom->cfg; + cfg.num_hw_update_entries = req_custom->num_cfg; + cfg.priv = &req_custom->hw_update_data; + cfg.init_packet = 0; + + rc = ctx->hw_mgr_intf->hw_config(ctx->hw_mgr_intf->hw_mgr_priv, &cfg); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_CUSTOM, + "Can not apply the configuration"); + } else { + spin_lock_bh(&ctx->lock); + list_del_init(&req->list); + if (!req->num_out_map_entries) { + list_add_tail(&req->list, &ctx->free_req_list); + spin_unlock_bh(&ctx->lock); + } else { + list_add_tail(&req->list, &ctx->active_req_list); + spin_unlock_bh(&ctx->lock); + /* + * for test purposes only-this should be + * triggered based on irq + */ + __cam_custom_ctx_handle_irq_in_activated(ctx, 0, NULL); + } + } + +end: + return rc; +} + +static int __cam_custom_ctx_acquire_hw_v1( + struct cam_context *ctx, void *args) +{ + int rc = 0; + struct cam_acquire_hw_cmd_v1 *cmd = + (struct cam_acquire_hw_cmd_v1 *)args; + struct cam_hw_acquire_args param; + struct cam_custom_context *ctx_custom = + (struct cam_custom_context *) ctx->ctx_priv; + struct cam_custom_acquire_hw_info *acquire_hw_info = NULL; + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CUSTOM, "HW interface is not ready"); + rc = -EFAULT; + goto end; + } + + CAM_DBG(CAM_CUSTOM, + "session_hdl 0x%x, hdl type %d, res %lld", + cmd->session_handle, cmd->handle_type, cmd->resource_hdl); + + if (cmd->handle_type != 1) { + CAM_ERR(CAM_CUSTOM, "Only user pointer is supported"); + rc = -EINVAL; + goto end; + } + + if (cmd->data_size < sizeof(*acquire_hw_info)) { + CAM_ERR(CAM_CUSTOM, "data_size is not a valid value"); + goto end; + } + + acquire_hw_info = kzalloc(cmd->data_size, GFP_KERNEL); + if (!acquire_hw_info) { + rc = -ENOMEM; + goto end; + } + + CAM_DBG(CAM_CUSTOM, "start copy resources from user"); + + if (copy_from_user(acquire_hw_info, (void __user *)cmd->resource_hdl, + cmd->data_size)) { + rc = -EFAULT; + goto free_res; + } + + memset(¶m, 0, sizeof(param)); + param.context_data = ctx; + param.event_cb = ctx->irq_cb_intf; + param.acquire_info_size = cmd->data_size; + param.acquire_info = (uint64_t) acquire_hw_info; + + /* call HW manager to reserve the resource */ + rc = ctx->hw_mgr_intf->hw_acquire(ctx->hw_mgr_intf->hw_mgr_priv, + ¶m); + if (rc != 0) { + CAM_ERR(CAM_CUSTOM, "Acquire HW failed"); + goto free_res; + } + + ctx_custom->hw_ctx = param.ctxt_to_hw_map; + ctx_custom->hw_acquired = true; + ctx->ctxt_to_hw_map = param.ctxt_to_hw_map; + + CAM_DBG(CAM_CUSTOM, + "Acquire HW success on session_hdl 0x%xs for ctx_id %u", + ctx->session_hdl, ctx->ctx_id); + + kfree(acquire_hw_info); + return rc; + +free_res: + kfree(acquire_hw_info); +end: + return rc; +} + +static int __cam_custom_ctx_acquire_dev_in_available( + struct cam_context *ctx, struct cam_acquire_dev_cmd *cmd) +{ + int rc = 0; + struct cam_create_dev_hdl req_hdl_param; + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CUSTOM, "HW interface is not ready"); + rc = -EFAULT; + return rc; + } + + CAM_DBG(CAM_CUSTOM, + "session_hdl 0x%x, num_resources %d, hdl type %d, res %lld", + cmd->session_handle, cmd->num_resources, + cmd->handle_type, cmd->resource_hdl); + + if (cmd->num_resources != CAM_API_COMPAT_CONSTANT) { + CAM_ERR(CAM_CUSTOM, "Invalid num_resources 0x%x", + cmd->num_resources); + return -EINVAL; + } + + req_hdl_param.session_hdl = cmd->session_handle; + req_hdl_param.v4l2_sub_dev_flag = 0; + req_hdl_param.media_entity_flag = 0; + req_hdl_param.ops = ctx->crm_ctx_intf; + req_hdl_param.priv = ctx; + + CAM_DBG(CAM_CUSTOM, "get device handle from bridge"); + ctx->dev_hdl = cam_create_device_hdl(&req_hdl_param); + if (ctx->dev_hdl <= 0) { + rc = -EFAULT; + CAM_ERR(CAM_CUSTOM, "Can not create device handle"); + return rc; + } + + cmd->dev_handle = ctx->dev_hdl; + ctx->session_hdl = cmd->session_handle; + ctx->state = CAM_CTX_ACQUIRED; + + CAM_DBG(CAM_CUSTOM, + "Acquire dev success on session_hdl 0x%x for ctx %u", + cmd->session_handle, ctx->ctx_id); + + return rc; +} + +static int __cam_custom_ctx_enqueue_init_request( + struct cam_context *ctx, struct cam_ctx_request *req) +{ + int rc = 0; + struct cam_ctx_request *req_old; + struct cam_custom_dev_ctx_req *req_custom_old; + struct cam_custom_dev_ctx_req *req_custom_new; + + spin_lock_bh(&ctx->lock); + if (list_empty(&ctx->pending_req_list)) { + list_add_tail(&req->list, &ctx->pending_req_list); + goto end; + } + + req_old = list_first_entry(&ctx->pending_req_list, + struct cam_ctx_request, list); + req_custom_old = (struct cam_custom_dev_ctx_req *) req_old->req_priv; + req_custom_new = (struct cam_custom_dev_ctx_req *) req->req_priv; + if (req_custom_old->hw_update_data.packet_opcode_type == + CAM_CUSTOM_PACKET_INIT_DEV) { + if ((req_custom_old->num_cfg + req_custom_new->num_cfg) >= + CAM_CUSTOM_CTX_CFG_MAX) { + CAM_WARN(CAM_CUSTOM, "Can not merge INIT pkt"); + rc = -ENOMEM; + } + + if (req_custom_old->num_fence_map_out != 0 || + req_custom_old->num_fence_map_in != 0) { + CAM_WARN(CAM_CUSTOM, "Invalid INIT pkt sequence"); + rc = -EINVAL; + } + + if (!rc) { + memcpy(req_custom_old->fence_map_out, + req_custom_new->fence_map_out, + sizeof(req_custom_new->fence_map_out[0])* + req_custom_new->num_fence_map_out); + req_custom_old->num_fence_map_out = + req_custom_new->num_fence_map_out; + + memcpy(req_custom_old->fence_map_in, + req_custom_new->fence_map_in, + sizeof(req_custom_new->fence_map_in[0])* + req_custom_new->num_fence_map_in); + req_custom_old->num_fence_map_in = + req_custom_new->num_fence_map_in; + + memcpy(&req_custom_old->cfg[req_custom_old->num_cfg], + req_custom_new->cfg, + sizeof(req_custom_new->cfg[0])* + req_custom_new->num_cfg); + req_custom_old->num_cfg += req_custom_new->num_cfg; + + req_old->request_id = req->request_id; + + list_add_tail(&req->list, &ctx->free_req_list); + } + } else { + CAM_WARN(CAM_CUSTOM, + "Received Update pkt before INIT pkt. req_id= %lld", + req->request_id); + rc = -EINVAL; + } +end: + spin_unlock_bh(&ctx->lock); + return rc; +} + +static int __cam_custom_ctx_config_dev(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + int rc = 0, i; + struct cam_ctx_request *req = NULL; + struct cam_custom_dev_ctx_req *req_custom; + uintptr_t packet_addr; + struct cam_packet *packet; + size_t len = 0; + struct cam_hw_prepare_update_args cfg; + struct cam_req_mgr_add_request add_req; + struct cam_custom_context *ctx_custom = + (struct cam_custom_context *) ctx->ctx_priv; + + /* get free request */ + spin_lock_bh(&ctx->lock); + if (!list_empty(&ctx->free_req_list)) { + req = list_first_entry(&ctx->free_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + } + spin_unlock_bh(&ctx->lock); + + if (!req) { + CAM_ERR(CAM_CUSTOM, "No more request obj free"); + return -ENOMEM; + } + + req_custom = (struct cam_custom_dev_ctx_req *) req->req_priv; + + /* for config dev, only memory handle is supported */ + /* map packet from the memhandle */ + rc = cam_mem_get_cpu_buf((int32_t) cmd->packet_handle, + &packet_addr, &len); + if (rc != 0) { + CAM_ERR(CAM_CUSTOM, "Can not get packet address"); + rc = -EINVAL; + goto free_req; + } + + packet = (struct cam_packet *)(packet_addr + (uint32_t)cmd->offset); + CAM_DBG(CAM_CUSTOM, "pack_handle %llx", cmd->packet_handle); + CAM_DBG(CAM_CUSTOM, "packet address is 0x%zx", packet_addr); + CAM_DBG(CAM_CUSTOM, "packet with length %zu, offset 0x%llx", + len, cmd->offset); + CAM_DBG(CAM_CUSTOM, "Packet request id %lld", + packet->header.request_id); + CAM_DBG(CAM_CUSTOM, "Packet size 0x%x", packet->header.size); + CAM_DBG(CAM_CUSTOM, "packet op %d", packet->header.op_code); + + if ((((packet->header.op_code) & 0xF) == + CAM_CUSTOM_PACKET_UPDATE_DEV) + && (packet->header.request_id <= ctx->last_flush_req)) { + CAM_DBG(CAM_CUSTOM, + "request %lld has been flushed, reject packet", + packet->header.request_id); + rc = -EINVAL; + goto free_req; + } + + /* preprocess the configuration */ + memset(&cfg, 0, sizeof(cfg)); + cfg.packet = packet; + cfg.ctxt_to_hw_map = ctx_custom->hw_ctx; + cfg.out_map_entries = req_custom->fence_map_out; + cfg.in_map_entries = req_custom->fence_map_in; + cfg.priv = &req_custom->hw_update_data; + cfg.pf_data = &(req->pf_data); + + rc = ctx->hw_mgr_intf->hw_prepare_update( + ctx->hw_mgr_intf->hw_mgr_priv, &cfg); + if (rc != 0) { + CAM_ERR(CAM_CUSTOM, "Prepare config packet failed in HW layer"); + rc = -EFAULT; + goto free_req; + } + + req_custom->num_cfg = cfg.num_hw_update_entries; + req_custom->num_fence_map_out = cfg.num_out_map_entries; + req_custom->num_fence_map_in = cfg.num_in_map_entries; + req_custom->num_acked = 0; + + for (i = 0; i < req_custom->num_fence_map_out; i++) { + rc = cam_sync_get_obj_ref(req_custom->fence_map_out[i].sync_id); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Can't get ref for fence %d", + req_custom->fence_map_out[i].sync_id); + goto put_ref; + } + } + + CAM_DBG(CAM_CUSTOM, + "num_entry: %d, num fence out: %d, num fence in: %d", + req_custom->num_cfg, req_custom->num_fence_map_out, + req_custom->num_fence_map_in); + + req->request_id = packet->header.request_id; + req->status = 1; + + CAM_DBG(CAM_CUSTOM, "Packet request id %lld packet opcode:%d", + packet->header.request_id, + req_custom->hw_update_data.packet_opcode_type); + + if (req_custom->hw_update_data.packet_opcode_type == + CAM_CUSTOM_PACKET_INIT_DEV) { + if (ctx->state < CAM_CTX_ACTIVATED) { + rc = __cam_custom_ctx_enqueue_init_request(ctx, req); + if (rc) + CAM_ERR(CAM_CUSTOM, "Enqueue INIT pkt failed"); + ctx_custom->init_received = true; + } else { + rc = -EINVAL; + CAM_ERR(CAM_CUSTOM, "Recevied INIT pkt in wrong state"); + } + } else { + if ((ctx->state != CAM_CTX_FLUSHED) && + (ctx->state >= CAM_CTX_READY) && + (ctx->ctx_crm_intf->add_req)) { + add_req.link_hdl = ctx->link_hdl; + add_req.dev_hdl = ctx->dev_hdl; + add_req.req_id = req->request_id; + add_req.skip_before_applying = 0; + rc = ctx->ctx_crm_intf->add_req(&add_req); + if (rc) { + CAM_ERR(CAM_CUSTOM, + "Add req failed: req id=%llu", + req->request_id); + } else { + __cam_custom_ctx_enqueue_request_in_order( + ctx, req); + } + } else { + rc = -EINVAL; + CAM_ERR(CAM_CUSTOM, "Recevied Update in wrong state"); + } + } + + if (rc) + goto put_ref; + + CAM_DBG(CAM_CUSTOM, + "Preprocessing Config req_id %lld successful on ctx %u", + req->request_id, ctx->ctx_id); + + return rc; + +put_ref: + for (--i; i >= 0; i--) { + if (cam_sync_put_obj_ref(req_custom->fence_map_out[i].sync_id)) + CAM_ERR(CAM_CUSTOM, "Failed to put ref of fence %d", + req_custom->fence_map_out[i].sync_id); + } +free_req: + spin_lock_bh(&ctx->lock); + list_add_tail(&req->list, &ctx->free_req_list); + spin_unlock_bh(&ctx->lock); + + return rc; + +} + +static int __cam_custom_ctx_config_dev_in_flushed(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + int rc = 0; + struct cam_start_stop_dev_cmd start_cmd; + struct cam_custom_context *custom_ctx = + (struct cam_custom_context *) ctx->ctx_priv; + + if (!custom_ctx->hw_acquired) { + CAM_ERR(CAM_CUSTOM, "HW is not acquired, reject packet"); + rc = -EINVAL; + goto end; + } + + rc = __cam_custom_ctx_config_dev(ctx, cmd); + if (rc) + goto end; + + if (!custom_ctx->init_received) { + CAM_WARN(CAM_CUSTOM, + "Received update packet in flushed state, skip start"); + goto end; + } + + start_cmd.dev_handle = cmd->dev_handle; + start_cmd.session_handle = cmd->session_handle; + rc = __cam_custom_ctx_start_dev_in_ready(ctx, &start_cmd); + if (rc) + CAM_ERR(CAM_CUSTOM, + "Failed to re-start HW after flush rc: %d", rc); + else + CAM_INFO(CAM_CUSTOM, + "Received init after flush. Re-start HW complete."); + +end: + return rc; +} + +static int __cam_custom_ctx_config_dev_in_acquired(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + int rc = 0; + struct cam_custom_context *ctx_custom = + (struct cam_custom_context *) ctx->ctx_priv; + + if (!ctx_custom->hw_acquired) { + CAM_ERR(CAM_CUSTOM, "HW not acquired, reject config packet"); + return -EAGAIN; + } + + rc = __cam_custom_ctx_config_dev(ctx, cmd); + + if (!rc && (ctx->link_hdl >= 0)) + ctx->state = CAM_CTX_READY; + + return rc; +} + +static int __cam_custom_ctx_link_in_acquired(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *link) +{ + struct cam_custom_context *ctx_custom = + (struct cam_custom_context *) ctx->ctx_priv; + + ctx->link_hdl = link->link_hdl; + ctx->ctx_crm_intf = link->crm_cb; + ctx_custom->subscribe_event = link->subscribe_event; + + /* change state only if we had the init config */ + if (ctx_custom->init_received) + ctx->state = CAM_CTX_READY; + + CAM_DBG(CAM_CUSTOM, "next state %d", ctx->state); + + return 0; +} + +static int __cam_custom_ctx_start_dev_in_ready(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc = 0; + struct cam_custom_start_args custom_start; + struct cam_ctx_request *req; + struct cam_custom_dev_ctx_req *req_custom; + struct cam_custom_context *ctx_custom = + (struct cam_custom_context *) ctx->ctx_priv; + + if (cmd->session_handle != ctx->session_hdl || + cmd->dev_handle != ctx->dev_hdl) { + rc = -EPERM; + goto end; + } + + if (list_empty(&ctx->pending_req_list)) { + /* should never happen */ + CAM_ERR(CAM_CUSTOM, "Start device with empty configuration"); + rc = -EFAULT; + goto end; + } else { + req = list_first_entry(&ctx->pending_req_list, + struct cam_ctx_request, list); + } + req_custom = (struct cam_custom_dev_ctx_req *) req->req_priv; + + if (!ctx_custom->hw_ctx) { + CAM_ERR(CAM_CUSTOM, "Wrong hw context pointer."); + rc = -EFAULT; + goto end; + } + + custom_start.hw_config.ctxt_to_hw_map = ctx_custom->hw_ctx; + custom_start.hw_config.request_id = req->request_id; + custom_start.hw_config.hw_update_entries = req_custom->cfg; + custom_start.hw_config.num_hw_update_entries = req_custom->num_cfg; + custom_start.hw_config.priv = &req_custom->hw_update_data; + custom_start.hw_config.init_packet = 1; + if (ctx->state == CAM_CTX_FLUSHED) + custom_start.start_only = true; + else + custom_start.start_only = false; + + ctx->state = CAM_CTX_ACTIVATED; + rc = ctx->hw_mgr_intf->hw_start(ctx->hw_mgr_intf->hw_mgr_priv, + &custom_start); + if (rc) { + /* HW failure. User need to clean up the resource */ + CAM_ERR(CAM_CUSTOM, "Start HW failed"); + ctx->state = CAM_CTX_READY; + goto end; + } + + CAM_DBG(CAM_CUSTOM, "start device success ctx %u", + ctx->ctx_id); + + spin_lock_bh(&ctx->lock); + list_del_init(&req->list); + if (req_custom->num_fence_map_out) + list_add_tail(&req->list, &ctx->active_req_list); + else + list_add_tail(&req->list, &ctx->free_req_list); + spin_unlock_bh(&ctx->lock); + +end: + return rc; +} + +static int __cam_custom_ctx_release_dev_in_activated(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc = 0; + + rc = __cam_custom_stop_dev_core(ctx, NULL); + if (rc) + CAM_ERR(CAM_CUSTOM, "Stop device failed rc=%d", rc); + + rc = __cam_custom_release_dev_in_acquired(ctx, cmd); + if (rc) + CAM_ERR(CAM_CUSTOM, "Release device failed rc=%d", rc); + + return rc; +} + +static int __cam_custom_ctx_unlink_in_activated(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *unlink) +{ + int rc = 0; + + CAM_WARN(CAM_CUSTOM, + "Received unlink in activated state. It's unexpected"); + + rc = __cam_custom_stop_dev_in_activated(ctx, NULL); + if (rc) + CAM_WARN(CAM_CUSTOM, "Stop device failed rc=%d", rc); + + rc = __cam_custom_ctx_unlink_in_ready(ctx, unlink); + if (rc) + CAM_ERR(CAM_CUSTOM, "Unlink failed rc=%d", rc); + + return rc; +} + +static int __cam_custom_ctx_process_evt(struct cam_context *ctx, + struct cam_req_mgr_link_evt_data *link_evt_data) +{ + switch (link_evt_data->evt_type) { + case CAM_REQ_MGR_LINK_EVT_ERR: + /* Handle error/bubble related issues */ + break; + default: + CAM_WARN(CAM_CUSTOM, "Unknown event from CRM"); + break; + } + + return 0; +} + +static int __cam_custom_ctx_handle_irq_in_activated(void *context, + uint32_t evt_id, void *evt_data) +{ + int rc; + struct cam_context *ctx = + (struct cam_context *)context; + + CAM_DBG(CAM_CUSTOM, "Enter %d", ctx->ctx_id); + + /* + * handle based on different irq's currently + * triggering only buf done if there are fences + */ + rc = cam_context_buf_done_from_hw(ctx, evt_data, 0); + if (rc) + CAM_ERR(CAM_CUSTOM, "Failed in buf done, rc=%d", rc); + + return rc; +} + +static int __cam_custom_ctx_acquire_hw_in_acquired( + struct cam_context *ctx, void *args) +{ + int rc = -EINVAL; + uint32_t api_version; + + if (!ctx || !args) { + CAM_ERR(CAM_CUSTOM, "Invalid input pointer"); + return rc; + } + + api_version = *((uint32_t *)args); + if (api_version == 1) + rc = __cam_custom_ctx_acquire_hw_v1(ctx, args); + else + CAM_ERR(CAM_CUSTOM, "Unsupported api version %d", + api_version); + + return rc; +} + +/* top state machine */ +static struct cam_ctx_ops + cam_custom_dev_ctx_top_state_machine[CAM_CTX_STATE_MAX] = { + /* Uninit */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Available */ + { + .ioctl_ops = { + .acquire_dev = + __cam_custom_ctx_acquire_dev_in_available, + }, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Acquired */ + { + .ioctl_ops = { + .acquire_hw = __cam_custom_ctx_acquire_hw_in_acquired, + .release_dev = __cam_custom_release_dev_in_acquired, + .config_dev = __cam_custom_ctx_config_dev_in_acquired, + .release_hw = __cam_custom_ctx_release_hw_in_top_state, + }, + .crm_ops = { + .link = __cam_custom_ctx_link_in_acquired, + .unlink = __cam_custom_ctx_unlink_in_acquired, + .get_dev_info = + __cam_custom_ctx_get_dev_info_in_acquired, + .flush_req = __cam_custom_ctx_flush_req_in_top_state, + }, + .irq_ops = NULL, + .pagefault_ops = NULL, + }, + /* Ready */ + { + .ioctl_ops = { + .start_dev = __cam_custom_ctx_start_dev_in_ready, + .release_dev = __cam_custom_release_dev_in_acquired, + .config_dev = __cam_custom_ctx_config_dev, + .release_hw = __cam_custom_ctx_release_hw_in_top_state, + }, + .crm_ops = { + .unlink = __cam_custom_ctx_unlink_in_ready, + .flush_req = __cam_custom_ctx_flush_req_in_ready, + }, + .irq_ops = NULL, + .pagefault_ops = NULL, + }, + /* Flushed */ + { + .ioctl_ops = { + .stop_dev = __cam_custom_stop_dev_in_activated, + .release_dev = + __cam_custom_ctx_release_dev_in_activated, + .config_dev = __cam_custom_ctx_config_dev_in_flushed, + .release_hw = + __cam_custom_ctx_release_hw_in_activated_state, + }, + .crm_ops = { + .unlink = __cam_custom_ctx_unlink_in_ready, + }, + .irq_ops = NULL, + }, + /* Activated */ + { + .ioctl_ops = { + .stop_dev = __cam_custom_stop_dev_in_activated, + .release_dev = + __cam_custom_ctx_release_dev_in_activated, + .config_dev = __cam_custom_ctx_config_dev, + .release_hw = + __cam_custom_ctx_release_hw_in_activated_state, + }, + .crm_ops = { + .unlink = __cam_custom_ctx_unlink_in_activated, + .apply_req = + __cam_custom_ctx_apply_req_in_activated_state, + .flush_req = __cam_custom_ctx_flush_req_in_top_state, + .process_evt = __cam_custom_ctx_process_evt, + }, + .irq_ops = __cam_custom_ctx_handle_irq_in_activated, + .pagefault_ops = NULL, + }, +}; + +int cam_custom_dev_context_init(struct cam_custom_context *ctx, + struct cam_context *ctx_base, + struct cam_req_mgr_kmd_ops *crm_node_intf, + struct cam_hw_mgr_intf *hw_intf, + uint32_t ctx_id) +{ + int rc = -1, i = 0; + + if (!ctx || !ctx_base) { + CAM_ERR(CAM_CUSTOM, "Invalid Context"); + return -EINVAL; + } + + /* Custom HW context setup */ + memset(ctx, 0, sizeof(*ctx)); + + ctx->base = ctx_base; + ctx->frame_id = 0; + ctx->active_req_cnt = 0; + ctx->hw_ctx = NULL; + + for (i = 0; i < CAM_CTX_REQ_MAX; i++) { + ctx->req_base[i].req_priv = &ctx->req_custom[i]; + ctx->req_custom[i].base = &ctx->req_base[i]; + } + + /* camera context setup */ + rc = cam_context_init(ctx_base, custom_dev_name, CAM_CUSTOM, ctx_id, + crm_node_intf, hw_intf, ctx->req_base, CAM_CTX_REQ_MAX); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Camera Context Base init failed"); + return rc; + } + + /* link camera context with custom HW context */ + ctx_base->state_machine = cam_custom_dev_ctx_top_state_machine; + ctx_base->ctx_priv = ctx; + + return rc; +} + +int cam_custom_dev_context_deinit(struct cam_custom_context *ctx) +{ + if (ctx->base) + cam_context_deinit(ctx->base); + + memset(ctx, 0, sizeof(*ctx)); + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_context.h b/techpack/camera-bengal/drivers/cam_cust/cam_custom_context.h new file mode 100644 index 0000000000000000000000000000000000000000..27268b20c526cbfa769467a7b4013881b96fa8c4 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_context.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CUSTOM_CONTEXT_H_ +#define _CAM_CUSTOM_CONTEXT_H_ + +#include +#include +#include + +#include "cam_context.h" +#include "cam_custom_hw_mgr_intf.h" + +/* + * Maximum hw resource - This number is based on the maximum + * output port resource. The current maximum resource number + * is 2. + */ +#define CAM_CUSTOM_DEV_CTX_RES_MAX 2 + +#define CAM_CUSTOM_CTX_CFG_MAX 8 + +/* forward declaration */ +struct cam_custom_context; + +/** + * struct cam_custom_dev_ctx_req - Custom context request object + * + * @base: Common request object pointer + * @cfg: Custom hardware configuration array + * @num_cfg: Number of custom hardware configuration entries + * @fence_map_out: Output fence mapping array + * @num_fence_map_out: Number of the output fence map + * @fence_map_in: Input fence mapping array + * @num_fence_map_in: Number of input fence map + * @num_acked: Count to track acked entried for output. + * If count equals the number of fence out, it means + * the request has been completed. + * @hw_update_data: HW update data for this request + * + */ +struct cam_custom_dev_ctx_req { + struct cam_ctx_request *base; + struct cam_hw_update_entry cfg + [CAM_CUSTOM_CTX_CFG_MAX]; + uint32_t num_cfg; + struct cam_hw_fence_map_entry fence_map_out + [CAM_CUSTOM_DEV_CTX_RES_MAX]; + uint32_t num_fence_map_out; + struct cam_hw_fence_map_entry fence_map_in + [CAM_CUSTOM_DEV_CTX_RES_MAX]; + uint32_t num_fence_map_in; + uint32_t num_acked; + struct cam_custom_prepare_hw_update_data hw_update_data; +}; + +/** + * struct cam_custom_context - Custom device context + * @base: custom device context object + * @state_machine: state machine for Custom device context + * @state: Common context state + * @hw_ctx: HW object returned by the acquire device command + * @init_received: Indicate whether init config packet is received + * @subscribe_event: The irq event mask that CRM subscribes to, + * custom HW will invoke CRM cb at those event. + * @active_req_cnt: Counter for the active request + * @frame_id: Frame id tracking for the custom context + * @hw_acquired: Flag to indicate if HW is acquired for this context + * @req_base: common request structure + * @req_custom: custom request structure + * + */ +struct cam_custom_context { + struct cam_context *base; + struct cam_ctx_ops *state_machine; + uint32_t state; + void *hw_ctx; + bool init_received; + uint32_t subscribe_event; + uint32_t active_req_cnt; + int64_t frame_id; + bool hw_acquired; + struct cam_ctx_request req_base[CAM_CTX_REQ_MAX]; + struct cam_custom_dev_ctx_req req_custom[CAM_CTX_REQ_MAX]; +}; + + +/** + * cam_custom_dev_context_init() + * + * @brief: Initialization function for the custom context + * + * @ctx: Custom context obj to be initialized + * @bridge_ops: Bridge call back funciton + * @hw_intf: Cust hw manager interface + * @ctx_id: ID for this context + * + */ +int cam_custom_dev_context_init(struct cam_custom_context *ctx, + struct cam_context *ctx_base, + struct cam_req_mgr_kmd_ops *bridge_ops, + struct cam_hw_mgr_intf *hw_intf, + uint32_t ctx_id); + +/** + * cam_custom_dev_context_deinit() + * + * @brief: Deinitialize function for the Custom context + * + * @ctx: Custom context obj to be deinitialized + * + */ +int cam_custom_dev_context_deinit(struct cam_custom_context *ctx); + +#endif /* _CAM_CUSTOM_CONTEXT_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_dev.c b/techpack/camera-bengal/drivers/cam_cust/cam_custom_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..76d4a7d0e17bd43fbb04f348f87f93a63f6749a1 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_dev.c @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "cam_custom_dev.h" +#include "cam_hw_mgr_intf.h" +#include "cam_custom_hw_mgr_intf.h" +#include "cam_node.h" +#include "cam_debug_util.h" +#include "cam_smmu_api.h" + +static struct cam_custom_dev g_custom_dev; + +static void cam_custom_dev_iommu_fault_handler( + struct iommu_domain *domain, struct device *dev, unsigned long iova, + int flags, void *token, uint32_t buf_info) +{ + int i = 0; + struct cam_node *node = NULL; + + if (!token) { + CAM_ERR(CAM_CUSTOM, "invalid token in page handler cb"); + return; + } + + node = (struct cam_node *)token; + + for (i = 0; i < node->ctx_size; i++) + cam_context_dump_pf_info(&(node->ctx_list[i]), iova, + buf_info); +} + +static const struct of_device_id cam_custom_dt_match[] = { + { + .compatible = "qcom,cam-custom" + }, + {} +}; + +static int cam_custom_subdev_open(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + mutex_lock(&g_custom_dev.custom_dev_mutex); + g_custom_dev.open_cnt++; + mutex_unlock(&g_custom_dev.custom_dev_mutex); + + return 0; +} + +static int cam_custom_subdev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + int rc = 0; + struct cam_node *node = v4l2_get_subdevdata(sd); + + mutex_lock(&g_custom_dev.custom_dev_mutex); + if (g_custom_dev.open_cnt <= 0) { + CAM_DBG(CAM_CUSTOM, "Custom subdev is already closed"); + rc = -EINVAL; + goto end; + } + + g_custom_dev.open_cnt--; + if (!node) { + CAM_ERR(CAM_CUSTOM, "Node ptr is NULL"); + rc = -EINVAL; + goto end; + } + + if (g_custom_dev.open_cnt == 0) + cam_node_shutdown(node); + +end: + mutex_unlock(&g_custom_dev.custom_dev_mutex); + return rc; +} + +static const struct v4l2_subdev_internal_ops cam_custom_subdev_internal_ops = { + .close = cam_custom_subdev_close, + .open = cam_custom_subdev_open, +}; + +static int cam_custom_dev_remove(struct platform_device *pdev) +{ + int rc = 0; + int i; + + /* clean up resources */ + for (i = 0; i < CAM_CUSTOM_HW_MAX_INSTANCES; i++) { + rc = cam_custom_dev_context_deinit(&g_custom_dev.ctx_custom[i]); + if (rc) + CAM_ERR(CAM_CUSTOM, + "Custom context %d deinit failed", i); + } + + rc = cam_subdev_remove(&g_custom_dev.sd); + if (rc) + CAM_ERR(CAM_CUSTOM, "Unregister failed"); + + memset(&g_custom_dev, 0, sizeof(g_custom_dev)); + return 0; +} + +static int cam_custom_dev_probe(struct platform_device *pdev) +{ + int rc = -EINVAL; + int i; + struct cam_hw_mgr_intf hw_mgr_intf; + struct cam_node *node; + int iommu_hdl = -1; + + g_custom_dev.sd.internal_ops = &cam_custom_subdev_internal_ops; + + rc = cam_subdev_probe(&g_custom_dev.sd, pdev, CAM_CUSTOM_DEV_NAME, + CAM_CUSTOM_DEVICE_TYPE); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Custom device cam_subdev_probe failed!"); + goto err; + } + node = (struct cam_node *) g_custom_dev.sd.token; + + memset(&hw_mgr_intf, 0, sizeof(hw_mgr_intf)); + rc = cam_custom_hw_mgr_init(pdev->dev.of_node, + &hw_mgr_intf, &iommu_hdl); + if (rc != 0) { + CAM_ERR(CAM_CUSTOM, "Can not initialized Custom HW manager!"); + goto unregister; + } + + for (i = 0; i < CAM_CUSTOM_HW_MAX_INSTANCES; i++) { + rc = cam_custom_dev_context_init(&g_custom_dev.ctx_custom[i], + &g_custom_dev.ctx[i], + &node->crm_node_intf, + &node->hw_mgr_intf, + i); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Custom context init failed!"); + goto unregister; + } + } + + rc = cam_node_init(node, &hw_mgr_intf, g_custom_dev.ctx, + CAM_CUSTOM_HW_MAX_INSTANCES, CAM_CUSTOM_DEV_NAME); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Custom HW node init failed!"); + goto unregister; + } + + cam_smmu_set_client_page_fault_handler(iommu_hdl, + cam_custom_dev_iommu_fault_handler, node); + + mutex_init(&g_custom_dev.custom_dev_mutex); + + CAM_DBG(CAM_CUSTOM, "Camera custom HW probe complete"); + + return 0; +unregister: + rc = cam_subdev_remove(&g_custom_dev.sd); +err: + return rc; +} + + +static struct platform_driver custom_driver = { + .probe = cam_custom_dev_probe, + .remove = cam_custom_dev_remove, + .driver = { + .name = "cam_custom", + .of_match_table = cam_custom_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_custom_dev_init_module(void) +{ + return platform_driver_register(&custom_driver); +} + +static void __exit cam_custom_dev_exit_module(void) +{ + platform_driver_unregister(&custom_driver); +} + +module_init(cam_custom_dev_init_module); +module_exit(cam_custom_dev_exit_module); +MODULE_DESCRIPTION("MSM CUSTOM driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_dev.h b/techpack/camera-bengal/drivers/cam_cust/cam_custom_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..77ea6badfe942d6d3fd37fd786098bd479726541 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_dev.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CUSTOM_DEV_H_ +#define _CAM_CUSTOM_DEV_H_ + +#include "cam_subdev.h" +#include "cam_hw_mgr_intf.h" +#include "cam_custom_hw_mgr.h" +#include "cam_context.h" +#include "cam_custom_context.h" + +#define CAM_CUSTOM_HW_MAX_INSTANCES 3 + +/** + * struct cam_custom_dev - Camera Custom V4l2 device node + * + * @sd: Common camera subdevice node + * @ctx: Custom base context storage + * @ctx_custom: Custom private context storage + * @custom_dev_mutex: Custom dev mutex + * @open_cnt: Open device count + */ +struct cam_custom_dev { + struct cam_subdev sd; + struct cam_context ctx[CAM_CUSTOM_HW_MAX_INSTANCES]; + struct cam_custom_context ctx_custom[CAM_CUSTOM_HW_MAX_INSTANCES]; + struct mutex custom_dev_mutex; + int32_t open_cnt; +}; + +#endif /* _CAM_CUSTOM_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/Makefile b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..22b1f17c6900c43768179de4bfe205840513adb6 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/Makefile @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_custom_hw1/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_custom_hw1/ cam_custom_csid/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_custom_hw_mgr.o + diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/Makefile b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..dbc3c5c5dfb8a8e27205c71cd65cca2dfd058cca --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_custom_csid_dev.o diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid480.h b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid480.h new file mode 100644 index 0000000000000000000000000000000000000000..da98ebf104c7786355c5293e4afbfdd28169d885 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid480.h @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CUSTOM_CSID_480_H_ +#define _CAM_CUSTOM_CSID_480_H_ + +#include "cam_ife_csid_core.h" + +#define CAM_CSID_VERSION_V480 0x40080000 + +static struct cam_ife_csid_udi_reg_offset + cam_custom_csid_480_udi_0_reg_offset = { + .csid_udi_irq_status_addr = 0x30, + .csid_udi_irq_mask_addr = 0x34, + .csid_udi_irq_clear_addr = 0x38, + .csid_udi_irq_set_addr = 0x3c, + .csid_udi_cfg0_addr = 0x200, + .csid_udi_cfg1_addr = 0x204, + .csid_udi_ctrl_addr = 0x208, + .csid_udi_frm_drop_pattern_addr = 0x20c, + .csid_udi_frm_drop_period_addr = 0x210, + .csid_udi_irq_subsample_pattern_addr = 0x214, + .csid_udi_irq_subsample_period_addr = 0x218, + .csid_udi_rpp_hcrop_addr = 0x21c, + .csid_udi_rpp_vcrop_addr = 0x220, + .csid_udi_rpp_pix_drop_pattern_addr = 0x224, + .csid_udi_rpp_pix_drop_period_addr = 0x228, + .csid_udi_rpp_line_drop_pattern_addr = 0x22c, + .csid_udi_rpp_line_drop_period_addr = 0x230, + .csid_udi_rst_strobes_addr = 0x240, + .csid_udi_status_addr = 0x250, + .csid_udi_misr_val0_addr = 0x254, + .csid_udi_misr_val1_addr = 0x258, + .csid_udi_misr_val2_addr = 0x25c, + .csid_udi_misr_val3_addr = 0x260, + .csid_udi_format_measure_cfg0_addr = 0x270, + .csid_udi_format_measure_cfg1_addr = 0x274, + .csid_udi_format_measure0_addr = 0x278, + .csid_udi_format_measure1_addr = 0x27c, + .csid_udi_format_measure2_addr = 0x280, + .csid_udi_timestamp_curr0_sof_addr = 0x290, + .csid_udi_timestamp_curr1_sof_addr = 0x294, + .csid_udi_timestamp_prev0_sof_addr = 0x298, + .csid_udi_timestamp_prev1_sof_addr = 0x29c, + .csid_udi_timestamp_curr0_eof_addr = 0x2a0, + .csid_udi_timestamp_curr1_eof_addr = 0x2a4, + .csid_udi_timestamp_prev0_eof_addr = 0x2a8, + .csid_udi_timestamp_prev1_eof_addr = 0x2ac, + .csid_udi_err_recovery_cfg0_addr = 0x2b0, + .csid_udi_err_recovery_cfg1_addr = 0x2b4, + .csid_udi_err_recovery_cfg2_addr = 0x2b8, + .csid_udi_multi_vcdt_cfg0_addr = 0x2bc, + .csid_udi_byte_cntr_ping_addr = 0x2e0, + .csid_udi_byte_cntr_pong_addr = 0x2e4, + /* configurations */ + .ccif_violation_en = 1, + .overflow_ctrl_en = 0, +}; + +static struct cam_ife_csid_udi_reg_offset + cam_custom_csid_480_udi_1_reg_offset = { + .csid_udi_irq_status_addr = 0x40, + .csid_udi_irq_mask_addr = 0x44, + .csid_udi_irq_clear_addr = 0x48, + .csid_udi_irq_set_addr = 0x4c, + .csid_udi_cfg0_addr = 0x300, + .csid_udi_cfg1_addr = 0x304, + .csid_udi_ctrl_addr = 0x308, + .csid_udi_frm_drop_pattern_addr = 0x30c, + .csid_udi_frm_drop_period_addr = 0x310, + .csid_udi_irq_subsample_pattern_addr = 0x314, + .csid_udi_irq_subsample_period_addr = 0x318, + .csid_udi_rpp_hcrop_addr = 0x31c, + .csid_udi_rpp_vcrop_addr = 0x320, + .csid_udi_rpp_pix_drop_pattern_addr = 0x324, + .csid_udi_rpp_pix_drop_period_addr = 0x328, + .csid_udi_rpp_line_drop_pattern_addr = 0x32c, + .csid_udi_rpp_line_drop_period_addr = 0x330, + .csid_udi_rst_strobes_addr = 0x340, + .csid_udi_status_addr = 0x350, + .csid_udi_misr_val0_addr = 0x354, + .csid_udi_misr_val1_addr = 0x358, + .csid_udi_misr_val2_addr = 0x35c, + .csid_udi_misr_val3_addr = 0x360, + .csid_udi_format_measure_cfg0_addr = 0x370, + .csid_udi_format_measure_cfg1_addr = 0x374, + .csid_udi_format_measure0_addr = 0x378, + .csid_udi_format_measure1_addr = 0x37c, + .csid_udi_format_measure2_addr = 0x380, + .csid_udi_timestamp_curr0_sof_addr = 0x390, + .csid_udi_timestamp_curr1_sof_addr = 0x394, + .csid_udi_timestamp_prev0_sof_addr = 0x398, + .csid_udi_timestamp_prev1_sof_addr = 0x39c, + .csid_udi_timestamp_curr0_eof_addr = 0x3a0, + .csid_udi_timestamp_curr1_eof_addr = 0x3a4, + .csid_udi_timestamp_prev0_eof_addr = 0x3a8, + .csid_udi_timestamp_prev1_eof_addr = 0x3ac, + .csid_udi_err_recovery_cfg0_addr = 0x3b0, + .csid_udi_err_recovery_cfg1_addr = 0x3b4, + .csid_udi_err_recovery_cfg2_addr = 0x3b8, + .csid_udi_multi_vcdt_cfg0_addr = 0x3bc, + .csid_udi_byte_cntr_ping_addr = 0x3e0, + .csid_udi_byte_cntr_pong_addr = 0x3e4, + /* configurations */ + .ccif_violation_en = 1, + .overflow_ctrl_en = 0, +}; + +static struct cam_ife_csid_udi_reg_offset + cam_custom_csid_480_udi_2_reg_offset = { + .csid_udi_irq_status_addr = 0x50, + .csid_udi_irq_mask_addr = 0x54, + .csid_udi_irq_clear_addr = 0x58, + .csid_udi_irq_set_addr = 0x5c, + .csid_udi_cfg0_addr = 0x400, + .csid_udi_cfg1_addr = 0x404, + .csid_udi_ctrl_addr = 0x408, + .csid_udi_frm_drop_pattern_addr = 0x40c, + .csid_udi_frm_drop_period_addr = 0x410, + .csid_udi_irq_subsample_pattern_addr = 0x414, + .csid_udi_irq_subsample_period_addr = 0x418, + .csid_udi_rpp_hcrop_addr = 0x41c, + .csid_udi_rpp_vcrop_addr = 0x420, + .csid_udi_rpp_pix_drop_pattern_addr = 0x424, + .csid_udi_rpp_pix_drop_period_addr = 0x428, + .csid_udi_rpp_line_drop_pattern_addr = 0x42c, + .csid_udi_rpp_line_drop_period_addr = 0x430, + .csid_udi_yuv_chroma_conversion_addr = 0x434, + .csid_udi_rst_strobes_addr = 0x440, + .csid_udi_status_addr = 0x450, + .csid_udi_misr_val0_addr = 0x454, + .csid_udi_misr_val1_addr = 0x458, + .csid_udi_misr_val2_addr = 0x45c, + .csid_udi_misr_val3_addr = 0x460, + .csid_udi_format_measure_cfg0_addr = 0x470, + .csid_udi_format_measure_cfg1_addr = 0x474, + .csid_udi_format_measure0_addr = 0x478, + .csid_udi_format_measure1_addr = 0x47c, + .csid_udi_format_measure2_addr = 0x480, + .csid_udi_timestamp_curr0_sof_addr = 0x490, + .csid_udi_timestamp_curr1_sof_addr = 0x494, + .csid_udi_timestamp_prev0_sof_addr = 0x498, + .csid_udi_timestamp_prev1_sof_addr = 0x49c, + .csid_udi_timestamp_curr0_eof_addr = 0x4a0, + .csid_udi_timestamp_curr1_eof_addr = 0x4a4, + .csid_udi_timestamp_prev0_eof_addr = 0x4a8, + .csid_udi_timestamp_prev1_eof_addr = 0x4ac, + .csid_udi_err_recovery_cfg0_addr = 0x4b0, + .csid_udi_err_recovery_cfg1_addr = 0x4b4, + .csid_udi_err_recovery_cfg2_addr = 0x4b8, + .csid_udi_multi_vcdt_cfg0_addr = 0x4bc, + .csid_udi_byte_cntr_ping_addr = 0x4e0, + .csid_udi_byte_cntr_pong_addr = 0x4e4, + /* configurations */ + .ccif_violation_en = 1, + .overflow_ctrl_en = 0, +}; + +static struct cam_ife_csid_csi2_rx_reg_offset + cam_custom_csid_480_csi2_reg_offset = { + .csid_csi2_rx_irq_status_addr = 0x20, + .csid_csi2_rx_irq_mask_addr = 0x24, + .csid_csi2_rx_irq_clear_addr = 0x28, + .csid_csi2_rx_irq_set_addr = 0x2c, + + /*CSI2 rx control */ + .csid_csi2_rx_cfg0_addr = 0x100, + .csid_csi2_rx_cfg1_addr = 0x104, + .csid_csi2_rx_capture_ctrl_addr = 0x108, + .csid_csi2_rx_rst_strobes_addr = 0x110, + .csid_csi2_rx_de_scramble_cfg0_addr = 0x114, + .csid_csi2_rx_de_scramble_cfg1_addr = 0x118, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, + .csid_csi2_rx_captured_short_pkt_0_addr = 0x128, + .csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, + .csid_csi2_rx_captured_long_pkt_0_addr = 0x130, + .csid_csi2_rx_captured_long_pkt_1_addr = 0x134, + .csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, + .csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, + .csid_csi2_rx_lane0_misr_addr = 0x150, + .csid_csi2_rx_lane1_misr_addr = 0x154, + .csid_csi2_rx_lane2_misr_addr = 0x158, + .csid_csi2_rx_lane3_misr_addr = 0x15c, + .csid_csi2_rx_total_pkts_rcvd_addr = 0x160, + .csid_csi2_rx_stats_ecc_addr = 0x164, + .csid_csi2_rx_total_crc_err_addr = 0x168, + + .csi2_rst_srb_all = 0x3FFF, + .csi2_rst_done_shift_val = 27, + .csi2_irq_mask_all = 0xFFFFFFF, + .csi2_misr_enable_shift_val = 6, + .csi2_vc_mode_shift_val = 2, + .csi2_capture_long_pkt_en_shift = 0, + .csi2_capture_short_pkt_en_shift = 1, + .csi2_capture_cphy_pkt_en_shift = 2, + .csi2_capture_long_pkt_dt_shift = 4, + .csi2_capture_long_pkt_vc_shift = 10, + .csi2_capture_short_pkt_vc_shift = 15, + .csi2_capture_cphy_pkt_dt_shift = 20, + .csi2_capture_cphy_pkt_vc_shift = 26, + .csi2_rx_phy_num_mask = 0x3, +}; + +static struct cam_ife_csid_common_reg_offset + cam_custom_csid_480_cmn_reg_offset = { + .csid_hw_version_addr = 0x0, + .csid_cfg0_addr = 0x4, + .csid_ctrl_addr = 0x8, + .csid_reset_addr = 0xc, + .csid_rst_strobes_addr = 0x10, + + .csid_test_bus_ctrl_addr = 0x14, + .csid_top_irq_status_addr = 0x70, + .csid_top_irq_mask_addr = 0x74, + .csid_top_irq_clear_addr = 0x78, + .csid_top_irq_set_addr = 0x7c, + .csid_irq_cmd_addr = 0x80, + + /*configurations */ + .major_version = 1, + .minor_version = 7, + .version_incr = 0, + .num_udis = 3, + .num_rdis = 0, + .num_pix = 0, + .num_ppp = 0, + .csid_reg_rst_stb = 1, + .csid_rst_stb = 0x1e, + .csid_rst_stb_sw_all = 0x1f, + .path_rst_stb_all = 0x7f, + .path_rst_done_shift_val = 1, + .path_en_shift_val = 31, + .dt_id_shift_val = 27, + .vc_shift_val = 22, + .dt_shift_val = 16, + .fmt_shift_val = 12, + .plain_fmt_shit_val = 10, + .crop_v_en_shift_val = 6, + .crop_h_en_shift_val = 5, + .crop_shift = 16, + .ipp_irq_mask_all = 0, + .rdi_irq_mask_all = 0, + .ppp_irq_mask_all = 0, + .udi_irq_mask_all = 0x7FFF, + .measure_en_hbi_vbi_cnt_mask = 0xC, + .format_measure_en_val = 1, + .num_bytes_out_shift_val = 3, +}; + +static struct cam_ife_csid_reg_offset cam_custom_csid_480_reg_offset = { + .cmn_reg = &cam_custom_csid_480_cmn_reg_offset, + .csi2_reg = &cam_custom_csid_480_csi2_reg_offset, + .ipp_reg = NULL, + .ppp_reg = NULL, + .rdi_reg = { + NULL, + NULL, + NULL, + NULL, + }, + .udi_reg = { + &cam_custom_csid_480_udi_0_reg_offset, + &cam_custom_csid_480_udi_1_reg_offset, + &cam_custom_csid_480_udi_2_reg_offset, + }, + .tpg_reg = NULL, +}; + +#endif /*_CAM_IFE_CSID_480_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid_dev.c b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..be472372aeb04a272c6a75322bcd8e2dc4de8c63 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid_dev.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include "linux/module.h" +#include "cam_custom_csid_dev.h" +#include "cam_ife_csid_core.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "cam_custom_csid480.h" +#include "cam_debug_util.h" + +#define CAM_CUSTOM_CSID_DRV_NAME "custom_csid" + +static struct cam_hw_intf *cam_custom_csid_hw_list[CAM_IFE_CSID_HW_NUM_MAX] = { + 0, 0, 0, 0}; + +static char csid_dev_name[16]; + +static struct cam_ife_csid_hw_info cam_custom_csid480_hw_info = { + .csid_reg = &cam_custom_csid_480_reg_offset, + .hw_dts_version = CAM_CSID_VERSION_V480, +}; + +static int cam_custom_csid_probe(struct platform_device *pdev) +{ + + struct cam_hw_intf *csid_hw_intf; + struct cam_hw_info *csid_hw_info; + struct cam_ife_csid_hw *csid_dev = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_ife_csid_hw_info *csid_hw_data = NULL; + uint32_t csid_dev_idx; + int rc = 0; + + csid_hw_intf = kzalloc(sizeof(*csid_hw_intf), GFP_KERNEL); + if (!csid_hw_intf) { + rc = -ENOMEM; + goto err; + } + + csid_hw_info = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!csid_hw_info) { + rc = -ENOMEM; + goto free_hw_intf; + } + + csid_dev = kzalloc(sizeof(struct cam_ife_csid_hw), GFP_KERNEL); + if (!csid_dev) { + rc = -ENOMEM; + goto free_hw_info; + } + + /* get custom csid hw index */ + of_property_read_u32(pdev->dev.of_node, "cell-index", &csid_dev_idx); + /* get custom csid hw information */ + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_CUSTOM, + "No matching table for the CUSTOM CSID HW!"); + rc = -EINVAL; + goto free_dev; + } + + memset(csid_dev_name, 0, sizeof(csid_dev_name)); + snprintf(csid_dev_name, sizeof(csid_dev_name), + "csid-custom%1u", csid_dev_idx); + + csid_hw_intf->hw_idx = csid_dev_idx; + csid_hw_intf->hw_type = CAM_ISP_HW_TYPE_IFE_CSID; + csid_hw_intf->hw_priv = csid_hw_info; + + csid_hw_info->core_info = csid_dev; + csid_hw_info->soc_info.pdev = pdev; + csid_hw_info->soc_info.dev = &pdev->dev; + csid_hw_info->soc_info.dev_name = csid_dev_name; + csid_hw_info->soc_info.index = csid_dev_idx; + + csid_hw_data = (struct cam_ife_csid_hw_info *)match_dev->data; + csid_dev->csid_info = csid_hw_data; + + rc = cam_ife_csid_hw_probe_init(csid_hw_intf, csid_dev_idx, true); + if (rc) + goto free_dev; + + platform_set_drvdata(pdev, csid_dev); + CAM_DBG(CAM_CUSTOM, "CSID:%d probe successful for dev %s", + csid_hw_intf->hw_idx, csid_dev_name); + + if (csid_hw_intf->hw_idx < CAM_IFE_CSID_HW_NUM_MAX) + cam_custom_csid_hw_list[csid_hw_intf->hw_idx] = csid_hw_intf; + else + goto free_dev; + + return 0; + +free_dev: + kfree(csid_dev); +free_hw_info: + kfree(csid_hw_info); +free_hw_intf: + kfree(csid_hw_intf); +err: + return rc; +} + +static int cam_custom_csid_remove(struct platform_device *pdev) +{ + struct cam_ife_csid_hw *csid_dev = NULL; + struct cam_hw_intf *csid_hw_intf; + struct cam_hw_info *csid_hw_info; + + csid_dev = (struct cam_ife_csid_hw *)platform_get_drvdata(pdev); + csid_hw_intf = csid_dev->hw_intf; + csid_hw_info = csid_dev->hw_info; + + CAM_DBG(CAM_CUSTOM, "CSID:%d remove", + csid_dev->hw_intf->hw_idx); + + cam_ife_csid_hw_deinit(csid_dev); + + /*release the csid device memory */ + kfree(csid_dev); + kfree(csid_hw_info); + kfree(csid_hw_intf); + return 0; +} + +static const struct of_device_id cam_custom_csid_dt_match[] = { + { + .compatible = "qcom,csid-custom480", + .data = &cam_custom_csid480_hw_info + }, + {} +}; + +MODULE_DEVICE_TABLE(of, cam_custom_csid_dt_match); + +static struct platform_driver cam_custom_csid_driver = { + .probe = cam_custom_csid_probe, + .driver = { + .name = "qcom,custom-csid", + .of_match_table = cam_custom_csid_dt_match, + .suppress_bind_attrs = true, + }, + .remove = cam_custom_csid_remove, +}; + +static int __init cam_custom_csid_driver_init(void) +{ + int32_t rc = 0; + + rc = platform_driver_register(&cam_custom_csid_driver); + if (rc < 0) + CAM_ERR(CAM_CUSTOM, "platform_driver_register Failed: rc = %d", + rc); + + return rc; +} + +int cam_custom_csid_hw_init(struct cam_hw_intf **custom_csid_hw, + uint32_t hw_idx) +{ + int rc = 0; + + if (cam_custom_csid_hw_list[hw_idx]) { + *custom_csid_hw = cam_custom_csid_hw_list[hw_idx]; + } else { + *custom_csid_hw = NULL; + rc = -1; + } + + return rc; +} + +static void __exit cam_custom_csid_driver_exit(void) +{ + platform_driver_unregister(&cam_custom_csid_driver); +} + +module_init(cam_custom_csid_driver_init); +module_exit(cam_custom_csid_driver_exit); +MODULE_DESCRIPTION("cam_custom_csid_driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid_dev.h b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..f0c086ccab181fc30d973e2b18c045176c2bbc1e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid_dev.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_IFE_CSID_DEV_H_ +#define _CAM_IFE_CSID_DEV_H_ + +#include "cam_debug_util.h" +#include "cam_custom_hw_mgr_intf.h" + +#endif /*_CAM_IFE_CSID_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/Makefile b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..89ad5d03366c76129b8b5623e65f487a49399a0b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1 + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_custom_sub_mod_soc.o cam_custom_sub_mod_dev.o cam_custom_sub_mod_core.o diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_core.c b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_core.c new file mode 100644 index 0000000000000000000000000000000000000000..9ac5da25571e9b9c7e366f08426dacd044aa4e3f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_core.c @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "cam_custom_sub_mod_core.h" + +int cam_custom_hw_sub_mod_get_hw_caps(void *hw_priv, + void *get_hw_cap_args, uint32_t arg_size) +{ + int rc = 0; + + if (!hw_priv) { + CAM_ERR(CAM_CUSTOM, "Invalid arguments"); + return -EINVAL; + } + /* Add HW Capabilities to be published */ + return rc; +} + +int cam_custom_hw_sub_mod_init_hw(void *hw_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *custom_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_custom_resource_node *custom_res = NULL; + int rc = 0; + + if (!hw_priv) { + CAM_ERR(CAM_CUSTOM, "Invalid arguments"); + return -EINVAL; + } + + mutex_lock(&custom_hw->hw_mutex); + custom_hw->open_count++; + if (custom_hw->open_count > 1) { + mutex_unlock(&custom_hw->hw_mutex); + CAM_DBG(CAM_CUSTOM, + "Cam Custom has already been initialized cnt %d", + custom_hw->open_count); + return 0; + } + mutex_unlock(&custom_hw->hw_mutex); + + soc_info = &custom_hw->soc_info; + + /* Turn ON Regulators, Clocks and other SOC resources */ + rc = cam_custom_hw_sub_mod_enable_soc_resources(soc_info); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Enable SOC failed"); + rc = -EFAULT; + goto decrement_open_cnt; + } + + custom_res = (struct cam_custom_resource_node *)init_hw_args; + if (custom_res && custom_res->init) { + rc = custom_res->init(custom_res, NULL, 0); + if (rc) { + CAM_ERR(CAM_CUSTOM, "init Failed rc=%d", rc); + goto decrement_open_cnt; + } + } + + rc = cam_custom_hw_sub_mod_reset(hw_priv, NULL, 0); + if (rc < 0) { + CAM_ERR(CAM_CUSTOM, "Custom HW reset failed : %d", rc); + goto decrement_open_cnt; + } + /* Initialize all resources here */ + custom_hw->hw_state = CAM_HW_STATE_POWER_UP; + return rc; + +decrement_open_cnt: + mutex_lock(&custom_hw->hw_mutex); + custom_hw->open_count--; + mutex_unlock(&custom_hw->hw_mutex); + return rc; +} + +int cam_custom_hw_sub_mod_deinit_hw(void *hw_priv, + void *deinit_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *custom_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_custom_resource_node *custom_res = NULL; + int rc = 0; + + if (!hw_priv) { + CAM_ERR(CAM_CUSTOM, "Invalid arguments"); + return -EINVAL; + } + + mutex_lock(&custom_hw->hw_mutex); + if (!custom_hw->open_count) { + mutex_unlock(&custom_hw->hw_mutex); + CAM_ERR(CAM_CUSTOM, "Error! Unbalanced deinit"); + return -EFAULT; + } + custom_hw->open_count--; + if (custom_hw->open_count) { + mutex_unlock(&custom_hw->hw_mutex); + CAM_DBG(CAM_CUSTOM, + "open_cnt non-zero =%d", custom_hw->open_count); + return 0; + } + mutex_unlock(&custom_hw->hw_mutex); + + soc_info = &custom_hw->soc_info; + + custom_res = (struct cam_custom_resource_node *)deinit_hw_args; + if (custom_res && custom_res->deinit) { + rc = custom_res->deinit(custom_res, NULL, 0); + if (rc) + CAM_ERR(CAM_CUSTOM, "deinit failed"); + } + + rc = cam_custom_hw_sub_mod_reset(hw_priv, NULL, 0); + + /* Turn OFF Regulators, Clocks and other SOC resources */ + CAM_DBG(CAM_CUSTOM, "Disable SOC resource"); + rc = cam_custom_hw_sub_mod_disable_soc_resources(soc_info); + if (rc) + CAM_ERR(CAM_CUSTOM, "Disable SOC failed"); + + custom_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + + return rc; +} + +int cam_custom_hw_sub_mod_reset(void *hw_priv, + void *reserve_args, uint32_t arg_size) +{ + struct cam_hw_info *custom_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + int rc = 0; + + if (!hw_priv) { + CAM_ERR(CAM_CUSTOM, "Invalid input arguments"); + return -EINVAL; + } + + soc_info = &custom_hw->soc_info; + /* Do Reset of HW */ + return rc; +} + +int cam_custom_hw_sub_mod_reserve(void *hw_priv, + void *reserve_args, uint32_t arg_size) +{ + int rc = 0; + + if (!hw_priv || !reserve_args) { + CAM_ERR(CAM_CUSTOM, "Invalid input arguments"); + return -EINVAL; + } + + /*Reserve Args */ + return rc; +} + + +int cam_custom_hw_sub_mod_release(void *hw_priv, + void *release_args, uint32_t arg_size) +{ + struct cam_hw_info *custom_hw = hw_priv; + int rc = 0; + + if (!hw_priv || !release_args) { + CAM_ERR(CAM_CUSTOM, "Invalid input arguments"); + return -EINVAL; + } + + mutex_lock(&custom_hw->hw_mutex); + /* Release Resources */ + mutex_unlock(&custom_hw->hw_mutex); + + return rc; +} + + +int cam_custom_hw_sub_mod_start(void *hw_priv, + void *start_args, uint32_t arg_size) +{ + struct cam_hw_info *custom_hw = hw_priv; + int rc = 0; + + if (!hw_priv || !start_args) { + CAM_ERR(CAM_CUSTOM, "Invalid input arguments"); + return -EINVAL; + } + + mutex_lock(&custom_hw->hw_mutex); + /* Start HW -- Stream On*/ + mutex_unlock(&custom_hw->hw_mutex); + + return rc; +} + +int cam_custom_hw_sub_mod_stop(void *hw_priv, + void *stop_args, uint32_t arg_size) +{ + struct cam_hw_info *custom_hw = hw_priv; + int rc = 0; + + if (!hw_priv || !stop_args) { + CAM_ERR(CAM_CUSTOM, "Invalid input arguments"); + return -EINVAL; + } + + mutex_lock(&custom_hw->hw_mutex); + /* Stop HW */ + mutex_unlock(&custom_hw->hw_mutex); + + return rc; +} + +int cam_custom_hw_sub_mod_read(void *hw_priv, + void *read_args, uint32_t arg_size) +{ + return -EPERM; +} + +int cam_custom_hw_sub_mod_write(void *hw_priv, + void *write_args, uint32_t arg_size) +{ + return -EPERM; +} + +int cam_custom_hw_submit_req(void *hw_priv, void *hw_submit_args, + uint32_t arg_size) +{ + struct cam_hw_info *custom_dev = hw_priv; + struct cam_custom_sub_mod_req_to_dev *submit_req = + (struct cam_custom_sub_mod_req_to_dev *)hw_submit_args; + struct cam_custom_sub_mod_core_info *core_info = NULL; + + core_info = + (struct cam_custom_sub_mod_core_info *)custom_dev->core_info; + + spin_lock(&custom_dev->hw_lock); + if (core_info->curr_req) { + CAM_WARN(CAM_CUSTOM, "Req %lld still processed by %s", + core_info->curr_req->req_id, + custom_dev->soc_info.dev_name); + spin_unlock(&custom_dev->hw_lock); + return -EAGAIN; + } + + core_info->curr_req = submit_req; + spin_unlock(&custom_dev->hw_lock); + + /* Do other submit procedures */ + return 0; +} + +irqreturn_t cam_custom_hw_sub_mod_irq(int irq_num, void *data) +{ + struct cam_hw_info *custom_dev = data; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_custom_hw_cb_args cb_args; + struct cam_custom_sub_mod_core_info *core_info = NULL; + uint32_t irq_status = 0; + + if (!data) { + CAM_ERR(CAM_CUSTOM, "Invalid custom_dev_info"); + return IRQ_HANDLED; + } + + soc_info = &custom_dev->soc_info; + core_info = + (struct cam_custom_sub_mod_core_info *)custom_dev->core_info; + + irq_status = cam_io_r_mb(soc_info->reg_map[0].mem_base + + core_info->device_hw_info->irq_status); + + cam_io_w_mb(irq_status, + soc_info->reg_map[0].mem_base + + core_info->device_hw_info->irq_clear); + + spin_lock(&custom_dev->hw_lock); + cb_args.irq_status = irq_status; + cb_args.req_info = core_info->curr_req; + core_info->curr_req = NULL; + if (core_info->irq_cb.custom_hw_mgr_cb) + core_info->irq_cb.custom_hw_mgr_cb( + core_info->irq_cb.data, &cb_args); + spin_unlock(&custom_dev->hw_lock); + + return IRQ_HANDLED; +} + +int cam_custom_hw_sub_mod_process_cmd(void *hw_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + struct cam_hw_info *hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_custom_sub_mod_core_info *core_info = NULL; + unsigned long flag = 0; + int rc = 0; + + if (!hw_priv || !cmd_args) { + CAM_ERR(CAM_CUSTOM, "Invalid arguments"); + return -EINVAL; + } + + soc_info = &hw->soc_info; + core_info = hw->core_info; + /* Handle any custom process cmds */ + + switch (cmd_type) { + case CAM_CUSTOM_SET_IRQ_CB: { + struct cam_custom_sub_mod_set_irq_cb *irq_cb = cmd_args; + + CAM_DBG(CAM_CUSTOM, "Setting irq cb"); + spin_lock_irqsave(&hw->hw_lock, flag); + core_info->irq_cb.custom_hw_mgr_cb = irq_cb->custom_hw_mgr_cb; + core_info->irq_cb.data = irq_cb->data; + spin_unlock_irqrestore(&hw->hw_lock, flag); + break; + } + case CAM_CUSTOM_SUBMIT_REQ: { + rc = cam_custom_hw_submit_req(hw_priv, cmd_args, arg_size); + break; + } + default: + break; + } + + return rc; +} + + diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_core.h b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_core.h new file mode 100644 index 0000000000000000000000000000000000000000..d27d578f6c8d9352e0ada24f9fb1bc093c55fa64 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_core.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CUSTOM_SUB_MOD_CORE_H_ +#define _CAM_CUSTOM_SUB_MOD_CORE_H_ + +#include "cam_debug_util.h" +#include "cam_custom_hw.h" +#include "cam_custom_sub_mod_soc.h" +#include "cam_custom_hw_mgr_intf.h" + +struct cam_custom_sub_mod_set_irq_cb { + int32_t (*custom_hw_mgr_cb)(void *data, + struct cam_custom_hw_cb_args *cb_args); + void *data; +}; + +struct cam_custom_sub_mod_req_to_dev { + uint64_t req_id; + uint32_t ctx_idx; + uint32_t dev_idx; +}; + +struct cam_custom_device_hw_info { + uint32_t hw_ver; + uint32_t irq_status; + uint32_t irq_mask; + uint32_t irq_clear; +}; + +struct cam_custom_sub_mod_core_info { + uint32_t cpas_handle; + bool cpas_start; + bool clk_enable; + struct cam_custom_sub_mod_set_irq_cb irq_cb; + struct cam_custom_sub_mod_req_to_dev *curr_req; + struct cam_custom_device_hw_info *device_hw_info; + struct cam_hw_info *custom_hw_info; +}; + +enum cam_custom_hw_resource_type { + CAM_CUSTOM_HW_RESOURCE_UNINT, + CAM_CUSTOM_HW_RESOURCE_SRC, + CAM_CUSTOM_HW_RESOURCE_MAX, +}; + +struct cam_custom_sub_mod_acq { + enum cam_custom_hw_resource_type rsrc_type; + int32_t acq; + struct cam_custom_resource_node *rsrc_node; +}; + +int cam_custom_hw_sub_mod_get_hw_caps(void *hw_priv, + void *get_hw_cap_args, uint32_t arg_size); +int cam_custom_hw_sub_mod_init_hw(void *hw_priv, + void *init_hw_args, uint32_t arg_size); +int cam_custom_hw_sub_mod_deinit_hw(void *hw_priv, + void *deinit_hw_args, uint32_t arg_size); +int cam_custom_hw_sub_mod_reset(void *hw_priv, + void *deinit_hw_args, uint32_t arg_size); +int cam_custom_hw_sub_mod_reserve(void *hw_priv, + void *reserve_args, uint32_t arg_size); +int cam_custom_hw_sub_mod_release(void *hw_priv, + void *release_args, uint32_t arg_size); +int cam_custom_hw_sub_mod_start(void *hw_priv, + void *start_args, uint32_t arg_size); +int cam_custom_hw_sub_mod_stop(void *hw_priv, + void *stop_args, uint32_t arg_size); +int cam_custom_hw_sub_mod_read(void *hw_priv, + void *read_args, uint32_t arg_size); +int cam_custom_hw_sub_mod_write(void *hw_priv, + void *write_args, uint32_t arg_size); +int cam_custom_hw_sub_mod_process_cmd(void *hw_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size); +irqreturn_t cam_custom_hw_sub_mod_irq(int irq_num, void *data); + +#endif /* _CAM_CUSTOM_SUB_MOD_CORE_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_dev.c b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..bd7d659136498fa29cec341e43e1cdf4889eaf7d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_dev.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include "cam_custom_sub_mod_dev.h" +#include "cam_custom_sub_mod_core.h" +#include "cam_custom_sub_mod_soc.h" +#include "cam_debug_util.h" + +static struct cam_hw_intf *cam_custom_hw_sub_mod_list + [CAM_CUSTOM_SUB_MOD_MAX_INSTANCES] = {0, 0}; + +static char cam_custom_hw_sub_mod_name[8]; + +struct cam_custom_device_hw_info cam_custom_hw_info = { + .hw_ver = 0x0, + .irq_status = 0x0, + .irq_mask = 0x0, + .irq_clear = 0x0, +}; +EXPORT_SYMBOL(cam_custom_hw_info); + +int cam_custom_hw_sub_mod_init(struct cam_hw_intf **custom_hw, uint32_t hw_idx) +{ + int rc = 0; + + if (cam_custom_hw_sub_mod_list[hw_idx]) { + *custom_hw = cam_custom_hw_sub_mod_list[hw_idx]; + rc = 0; + } else { + *custom_hw = NULL; + rc = -ENODEV; + } + return 0; +} + +int cam_custom_hw_sub_mod_probe(struct platform_device *pdev) +{ + struct cam_hw_info *hw = NULL; + struct cam_hw_intf *hw_intf = NULL; + struct cam_custom_sub_mod_core_info *core_info = NULL; + int rc = 0; + + hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!hw_intf) + return -ENOMEM; + + of_property_read_u32(pdev->dev.of_node, + "cell-index", &hw_intf->hw_idx); + + hw = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!hw) { + rc = -ENOMEM; + goto free_hw_intf; + } + + memset(cam_custom_hw_sub_mod_name, 0, + sizeof(cam_custom_hw_sub_mod_name)); + snprintf(cam_custom_hw_sub_mod_name, sizeof(cam_custom_hw_sub_mod_name), + "custom_hw%1u", hw_intf->hw_idx); + + hw->soc_info.pdev = pdev; + hw->soc_info.dev = &pdev->dev; + hw->soc_info.dev_name = cam_custom_hw_sub_mod_name; + hw_intf->hw_priv = hw; + hw_intf->hw_ops.get_hw_caps = cam_custom_hw_sub_mod_get_hw_caps; + hw_intf->hw_ops.init = cam_custom_hw_sub_mod_init_hw; + hw_intf->hw_ops.deinit = cam_custom_hw_sub_mod_deinit_hw; + hw_intf->hw_ops.reset = cam_custom_hw_sub_mod_reset; + hw_intf->hw_ops.reserve = cam_custom_hw_sub_mod_reserve; + hw_intf->hw_ops.release = cam_custom_hw_sub_mod_release; + hw_intf->hw_ops.start = cam_custom_hw_sub_mod_start; + hw_intf->hw_ops.stop = cam_custom_hw_sub_mod_stop; + hw_intf->hw_ops.read = cam_custom_hw_sub_mod_read; + hw_intf->hw_ops.write = cam_custom_hw_sub_mod_write; + hw_intf->hw_ops.process_cmd = cam_custom_hw_sub_mod_process_cmd; + hw_intf->hw_type = CAM_CUSTOM_HW_TYPE_1; + + platform_set_drvdata(pdev, hw_intf); + + hw->core_info = kzalloc(sizeof(struct cam_custom_sub_mod_core_info), + GFP_KERNEL); + if (!hw->core_info) { + CAM_DBG(CAM_CUSTOM, "Failed to alloc for core"); + rc = -ENOMEM; + goto free_hw; + } + core_info = (struct cam_custom_sub_mod_core_info *)hw->core_info; + + core_info->custom_hw_info = hw; + + rc = cam_custom_hw_sub_mod_init_soc_resources(&hw->soc_info, + cam_custom_hw_sub_mod_irq, hw); + if (rc < 0) { + CAM_ERR(CAM_CUSTOM, "Failed to init soc rc=%d", rc); + goto free_core_info; + } + + /* Initialize HW */ + + hw->hw_state = CAM_HW_STATE_POWER_DOWN; + mutex_init(&hw->hw_mutex); + spin_lock_init(&hw->hw_lock); + init_completion(&hw->hw_complete); + + if (hw_intf->hw_idx < CAM_CUSTOM_HW_SUB_MOD_MAX) + cam_custom_hw_sub_mod_list[hw_intf->hw_idx] = hw_intf; + + /* needs to be invoked when custom hw is in place */ + //cam_custom_hw_sub_mod_init_hw(hw, NULL, 0); + + CAM_DBG(CAM_CUSTOM, "Custom hw_idx[%d] probe successful", + hw_intf->hw_idx); + return rc; + +free_core_info: + kfree(hw->core_info); +free_hw: + kfree(hw); +free_hw_intf: + kfree(hw_intf); + return rc; +} + +static const struct of_device_id cam_custom_hw_sub_mod_dt_match[] = { + { + .compatible = "qcom,cam_custom_hw_sub_mod", + .data = &cam_custom_hw_info, + }, + {} +}; + +MODULE_DEVICE_TABLE(of, cam_custom_hw_sub_mod_dt_match); + +static struct platform_driver cam_custom_hw_sub_mod_driver = { + .probe = cam_custom_hw_sub_mod_probe, + .driver = { + .name = CAM_CUSTOM_SUB_MOD_NAME, + .of_match_table = cam_custom_hw_sub_mod_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_custom_hw_sub_module_init(void) +{ + return platform_driver_register(&cam_custom_hw_sub_mod_driver); +} + +static void __exit cam_custom_hw_sub_module_exit(void) +{ + platform_driver_unregister(&cam_custom_hw_sub_mod_driver); +} + +module_init(cam_custom_hw_sub_module_init); +module_exit(cam_custom_hw_sub_module_exit); +MODULE_DESCRIPTION("CAM CUSTOM HW SUB MODULE driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_dev.h b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..1da630ed5ec236b9866bd2893773c7f65f3da60c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_dev.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CUSTOM_SUB_MOD_DEV_H_ +#define _CAM_CUSTOM_SUB_MOD_DEV_H_ + +#include "cam_custom_hw_mgr_intf.h" + +#define CAM_CUSTOM_SUB_MOD_NAME "cam_custom_sub_mod" + +#define CAM_CUSTOM_SUB_MOD_MAX_INSTANCES 2 + +#endif /* _CAM_CUSTOM_SUB_MOD_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_soc.c b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..9011ac9d5291e1884f08277012129e3a274f1dd2 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_soc.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_cpas_api.h" +#include "cam_custom_sub_mod_soc.h" +#include "cam_debug_util.h" + +int cam_custom_hw_sub_mod_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t irq_handler, void *irq_data) +{ + int rc = 0; + struct cam_custom_hw_soc_private *soc_private = NULL; + struct cam_cpas_register_params cpas_register_param; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) { + CAM_ERR(CAM_CUSTOM, + "Error! Get DT properties failed rc=%d", rc); + /* For Test Purposes */ + return 0; + } + + soc_private = kzalloc(sizeof(struct cam_custom_hw_soc_private), + GFP_KERNEL); + if (!soc_private) { + CAM_DBG(CAM_CUSTOM, "Error! soc_private Alloc Failed"); + return -ENOMEM; + } + soc_info->soc_private = soc_private; + + rc = cam_soc_util_request_platform_resource(soc_info, irq_handler, + irq_data); + if (rc < 0) { + CAM_ERR(CAM_CUSTOM, + "Error! Request platform resources failed rc=%d", rc); + return rc; + } + + memset(&cpas_register_param, 0, sizeof(cpas_register_param)); + + strlcpy(cpas_register_param.identifier, "custom", + CAM_HW_IDENTIFIER_LENGTH); + cpas_register_param.cell_index = soc_info->index; + cpas_register_param.dev = soc_info->dev; + cpas_register_param.cam_cpas_client_cb = NULL; + cpas_register_param.userdata = soc_info; + + rc = cam_cpas_register_client(&cpas_register_param); + if (rc < 0) + goto release_soc; + + soc_private->cpas_handle = + cpas_register_param.client_handle; + + return rc; + +release_soc: + cam_soc_util_release_platform_resource(soc_info); + return rc; +} + +int cam_custom_hw_sub_mod_deinit_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_custom_hw_soc_private *soc_private = NULL; + + if (!soc_info) { + CAM_ERR(CAM_CUSTOM, "Error! soc_info NULL"); + return -ENODEV; + } + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_CUSTOM, "Error! soc_private NULL"); + return -ENODEV; + } + rc = cam_cpas_unregister_client(soc_private->cpas_handle); + if (rc) + CAM_ERR(CAM_CUSTOM, "CPAS0 unregistration failed rc=%d", rc); + + rc = cam_soc_util_release_platform_resource(soc_info); + if (rc < 0) + CAM_ERR(CAM_CUSTOM, + "Error! Release platform resources failed rc=%d", rc); + + kfree(soc_private); + + return rc; +} + +int cam_custom_hw_sub_mod_enable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_custom_hw_soc_private *soc_private = soc_info->soc_private; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_LOWSVS_VOTE; + axi_vote.num_paths = 2; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_READ; + axi_vote.axi_path[0].camnoc_bw = 7200000; + axi_vote.axi_path[0].mnoc_ab_bw = 7200000; + axi_vote.axi_path[0].mnoc_ib_bw = 7200000; + axi_vote.axi_path[1].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[1].transac_type = CAM_AXI_TRANSACTION_WRITE; + axi_vote.axi_path[1].camnoc_bw = 512000000; + axi_vote.axi_path[1].mnoc_ab_bw = 512000000; + axi_vote.axi_path[1].mnoc_ib_bw = 512000000; + + rc = cam_cpas_start(soc_private->cpas_handle, &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Error! CPAS0 start failed rc=%d", rc); + rc = -EFAULT; + goto end; + } + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_TURBO_VOTE, true); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Error! enable platform failed rc=%d", rc); + goto stop_cpas; + } + + return 0; + +stop_cpas: + cam_cpas_stop(soc_private->cpas_handle); +end: + return rc; +} + +int cam_custom_hw_sub_mod_disable_soc_resources( + struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_custom_hw_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_CUSTOM, "Error! Invalid params"); + rc = -EINVAL; + return rc; + } + soc_private = soc_info->soc_private; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Disable platform failed rc=%d", rc); + return rc; + } + + rc = cam_cpas_stop(soc_private->cpas_handle); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Error! CPAS stop failed rc=%d", rc); + return rc; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_soc.h b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..e9c95d43d366d23af678bf837e531e19d65893b7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/cam_custom_sub_mod_soc.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CUSTOM_HW_SUB_MOD_SOC_H_ +#define _CAM_CUSTOM_HW_SUB_MOD_SOC_H_ + +#include "cam_soc_util.h" +/* + * struct cam_custom_hw_soc_private: + * + * @Brief: Private SOC data specific to Custom HW Driver + * + * @cpas_handle: Handle returned on registering with CPAS driver. + * This handle is used for all further interface + * with CPAS. + */ +struct cam_custom_hw_soc_private { + uint32_t cpas_handle; +}; + +int cam_custom_hw_sub_mod_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t irq_handler, void *irq_data); + +int cam_custom_hw_sub_mod_deinit_soc_resources( + struct cam_hw_soc_info *soc_info); + +int cam_custom_hw_sub_mod_enable_soc_resources( + struct cam_hw_soc_info *soc_info); + +int cam_custom_hw_sub_mod_disable_soc_resources( + struct cam_hw_soc_info *soc_info); + +#endif /* _CAM_CUSTOM_HW_SUB_MOD_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c new file mode 100644 index 0000000000000000000000000000000000000000..d9c349f0b7ddde1c1741a2a120359aab987347b7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c @@ -0,0 +1,1385 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "cam_sync_api.h" +#include "cam_smmu_api.h" +#include "cam_req_mgr_workq.h" +#include "cam_custom_hw_mgr.h" +#include "cam_packet_util.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" +#include "cam_mem_mgr_api.h" +#include "cam_common_util.h" +#include "cam_hw.h" + +static struct cam_custom_hw_mgr g_custom_hw_mgr; + +static int cam_custom_mgr_get_hw_caps(void *hw_mgr_priv, + void *hw_caps_args) +{ + int rc = 0; + struct cam_custom_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_query_cap_cmd *query = hw_caps_args; + struct cam_custom_query_cap_cmd custom_hw_cap; + struct cam_hw_info *cam_custom_hw; + struct cam_hw_soc_info *soc_info_hw; + + cam_custom_hw = (struct cam_hw_info *) + g_custom_hw_mgr.custom_hw[0]->hw_priv; + if (cam_custom_hw) + soc_info_hw = &cam_custom_hw->soc_info; + + CAM_DBG(CAM_CUSTOM, "enter"); + + if (query->handle_type != CAM_HANDLE_USER_POINTER) + CAM_ERR(CAM_CUSTOM, "Wrong Args"); + + if (copy_from_user(&custom_hw_cap, + u64_to_user_ptr(query->caps_handle), + sizeof(struct cam_custom_query_cap_cmd))) { + rc = -EFAULT; + return rc; + } + + custom_hw_cap.device_iommu.non_secure = hw_mgr->img_iommu_hdl; + custom_hw_cap.device_iommu.secure = -1; + + /* Initializing cdm handles to -1 */ + custom_hw_cap.cdm_iommu.non_secure = -1; + custom_hw_cap.cdm_iommu.secure = -1; + + custom_hw_cap.num_dev = 1; + custom_hw_cap.dev_caps[0].hw_type = 0; + custom_hw_cap.dev_caps[0].hw_version = 0; + + if (copy_to_user(u64_to_user_ptr(query->caps_handle), + &custom_hw_cap, sizeof(struct cam_custom_query_cap_cmd))) + rc = -EFAULT; + + CAM_DBG(CAM_CUSTOM, "exit rc :%d", rc); + return rc; +} + +enum cam_custom_hw_resource_state + cam_custom_hw_mgr_get_custom_res_state( + uint32_t in_rsrc_state) +{ + enum cam_custom_hw_resource_state rsrc_state; + + CAM_DBG(CAM_CUSTOM, "rsrc_state %x", in_rsrc_state); + + switch (in_rsrc_state) { + case CAM_ISP_RESOURCE_STATE_UNAVAILABLE: + rsrc_state = CAM_CUSTOM_HW_RESOURCE_STATE_UNAVAILABLE; + break; + case CAM_ISP_RESOURCE_STATE_AVAILABLE: + rsrc_state = CAM_CUSTOM_HW_RESOURCE_STATE_AVAILABLE; + break; + case CAM_ISP_RESOURCE_STATE_RESERVED: + rsrc_state = CAM_CUSTOM_HW_RESOURCE_STATE_RESERVED; + break; + case CAM_ISP_RESOURCE_STATE_INIT_HW: + rsrc_state = CAM_CUSTOM_HW_RESOURCE_STATE_INIT_HW; + break; + case CAM_ISP_RESOURCE_STATE_STREAMING: + rsrc_state = CAM_CUSTOM_HW_RESOURCE_STATE_STREAMING; + break; + default: + rsrc_state = CAM_CUSTOM_HW_RESOURCE_STATE_UNAVAILABLE; + CAM_DBG(CAM_CUSTOM, "invalid rsrc type"); + break; + } + + return rsrc_state; +} + +enum cam_isp_resource_state + cam_custom_hw_mgr_get_isp_res_state( + uint32_t in_rsrc_state) +{ + enum cam_isp_resource_state rsrc_state; + + CAM_DBG(CAM_CUSTOM, "rsrc_state %x", in_rsrc_state); + + switch (in_rsrc_state) { + case CAM_CUSTOM_HW_RESOURCE_STATE_UNAVAILABLE: + rsrc_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + break; + case CAM_CUSTOM_HW_RESOURCE_STATE_AVAILABLE: + rsrc_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + break; + case CAM_CUSTOM_HW_RESOURCE_STATE_RESERVED: + rsrc_state = CAM_ISP_RESOURCE_STATE_RESERVED; + break; + case CAM_CUSTOM_HW_RESOURCE_STATE_INIT_HW: + rsrc_state = CAM_ISP_RESOURCE_STATE_INIT_HW; + break; + case CAM_CUSTOM_HW_RESOURCE_STATE_STREAMING: + rsrc_state = CAM_ISP_RESOURCE_STATE_STREAMING; + break; + default: + rsrc_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + CAM_DBG(CAM_CUSTOM, "invalid rsrc type"); + break; + } + + return rsrc_state; +} + +enum cam_isp_resource_type + cam_custom_hw_mgr_get_isp_res_type( + enum cam_custom_hw_mgr_res_type res_type) +{ + switch (res_type) { + case CAM_CUSTOM_CID_HW: + return CAM_ISP_RESOURCE_CID; + case CAM_CUSTOM_CSID_HW: + return CAM_ISP_RESOURCE_PIX_PATH; + default: + return CAM_ISP_RESOURCE_MAX; + } +} + +static int cam_custom_hw_mgr_deinit_hw_res( + struct cam_custom_hw_mgr_res *hw_mgr_res) +{ + int rc = -1; + struct cam_isp_resource_node *isp_rsrc_node = NULL; + struct cam_hw_intf *hw_intf = NULL; + + isp_rsrc_node = + (struct cam_isp_resource_node *)hw_mgr_res->rsrc_node; + if (!isp_rsrc_node) { + CAM_ERR(CAM_CUSTOM, "Invalid args"); + return -EINVAL; + } + + hw_intf = isp_rsrc_node->hw_intf; + if (hw_intf->hw_ops.deinit) { + CAM_DBG(CAM_CUSTOM, "DEINIT HW for res_id:%u", + hw_mgr_res->res_id); + rc = hw_intf->hw_ops.deinit(hw_intf->hw_priv, + isp_rsrc_node, sizeof(struct cam_isp_resource_node)); + if (rc) + goto err; + } + + return 0; + +err: + CAM_DBG(CAM_CUSTOM, "DEINIT HW failed for res_id:%u", + hw_mgr_res->res_id); + return rc; +} + +static int cam_custom_hw_mgr_stop_hw_res( + struct cam_custom_hw_mgr_res *hw_mgr_res) +{ + int rc = -1; + struct cam_csid_hw_stop_args stop_cmd; + struct cam_isp_resource_node *isp_rsrc_node = NULL; + struct cam_hw_intf *hw_intf = NULL; + + isp_rsrc_node = + (struct cam_isp_resource_node *)hw_mgr_res->rsrc_node; + if (!isp_rsrc_node) { + CAM_ERR(CAM_CUSTOM, "Invalid args"); + return -EINVAL; + } + + hw_intf = isp_rsrc_node->hw_intf; + if (hw_intf->hw_ops.stop) { + CAM_DBG(CAM_CUSTOM, "STOP HW for res_id:%u", + hw_mgr_res->res_id); + stop_cmd.num_res = 1; + stop_cmd.node_res = &isp_rsrc_node; + stop_cmd.stop_cmd = CAM_CSID_HALT_AT_FRAME_BOUNDARY; + rc = hw_intf->hw_ops.stop(hw_intf->hw_priv, + &stop_cmd, sizeof(struct cam_csid_hw_stop_args)); + if (rc) + goto err; + } + + return 0; + +err: + CAM_DBG(CAM_CUSTOM, "STOP HW failed for res_id:%u", + hw_mgr_res->res_id); + return rc; +} + +static int cam_custom_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) +{ + int rc = 0; + struct cam_custom_stop_args *custom_args; + struct cam_hw_stop_args *stop_args = stop_hw_args; + struct cam_custom_hw_mgr_res *hw_mgr_res; + struct cam_custom_hw_mgr_ctx *ctx; + + if (!hw_mgr_priv || !stop_hw_args) { + CAM_ERR(CAM_CUSTOM, "Invalid arguments"); + return -EINVAL; + } + + custom_args = (struct cam_custom_stop_args *)stop_args->args; + ctx = (struct cam_custom_hw_mgr_ctx *) + stop_args->ctxt_to_hw_map; + + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_CUSTOM, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_CUSTOM, " Enter...ctx id:%d", ctx->ctx_index); + + /* Stop custom cid here */ + list_for_each_entry(hw_mgr_res, + &ctx->res_list_custom_cid, list) { + rc = cam_custom_hw_mgr_stop_hw_res(hw_mgr_res); + if (rc) + CAM_ERR(CAM_CUSTOM, "failed to stop hw %d", + hw_mgr_res->res_id); + } + + /* Stop custom csid here */ + list_for_each_entry(hw_mgr_res, + &ctx->res_list_custom_csid, list) { + rc = cam_custom_hw_mgr_stop_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_CUSTOM, "failed to stop hw %d", + hw_mgr_res->res_id); + } + } + + + /* stop custom hw here */ + + if (custom_args->stop_only) + goto end; + + /* Deinit custom cid here */ + list_for_each_entry(hw_mgr_res, + &ctx->res_list_custom_cid, list) { + rc = cam_custom_hw_mgr_deinit_hw_res(hw_mgr_res); + if (rc) + CAM_ERR(CAM_CUSTOM, "failed to stop hw %d", + hw_mgr_res->res_id); + } + + /* Deinit custom csid here */ + list_for_each_entry(hw_mgr_res, + &ctx->res_list_custom_csid, list) { + rc = cam_custom_hw_mgr_deinit_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_CUSTOM, "failed to stop hw %d", + hw_mgr_res->res_id); + } + } + + /* deinit custom rsrc */ + +end: + return rc; +} + +static int cam_custom_hw_mgr_init_hw_res( + struct cam_custom_hw_mgr_res *hw_mgr_res) +{ + int rc = -1; + struct cam_isp_resource_node *isp_rsrc_node = NULL; + struct cam_hw_intf *hw_intf = NULL; + + isp_rsrc_node = + (struct cam_isp_resource_node *)hw_mgr_res->rsrc_node; + if (!isp_rsrc_node) { + CAM_ERR(CAM_CUSTOM, "Invalid args"); + return -EINVAL; + } + + hw_intf = isp_rsrc_node->hw_intf; + if (hw_intf->hw_ops.init) { + CAM_DBG(CAM_CUSTOM, "INIT HW for res_id:%u", + hw_mgr_res->res_id); + rc = hw_intf->hw_ops.init(hw_intf->hw_priv, + isp_rsrc_node, sizeof(struct cam_isp_resource_node)); + if (rc) + goto err; + } + + return 0; + +err: + CAM_DBG(CAM_CUSTOM, "INIT HW failed for res_id:%u", + hw_mgr_res->res_id); + return rc; +} + +static int cam_custom_hw_mgr_start_hw_res( + struct cam_custom_hw_mgr_res *hw_mgr_res) +{ + int rc = -1; + struct cam_isp_resource_node *isp_rsrc_node = NULL; + struct cam_hw_intf *hw_intf = NULL; + + isp_rsrc_node = + (struct cam_isp_resource_node *)hw_mgr_res->rsrc_node; + if (!isp_rsrc_node) { + CAM_ERR(CAM_CUSTOM, "Invalid args"); + return -EINVAL; + } + + hw_intf = isp_rsrc_node->hw_intf; + if (hw_intf->hw_ops.start) { + CAM_DBG(CAM_CUSTOM, "Start HW for res_id:%u", + hw_mgr_res->res_id); + rc = hw_intf->hw_ops.start(hw_intf->hw_priv, + isp_rsrc_node, sizeof(struct cam_isp_resource_node)); + if (rc) + goto err; + } + + return 0; + +err: + CAM_DBG(CAM_CUSTOM, "START HW failed for res_id:%u", + hw_mgr_res->res_id); + return rc; +} + +static int cam_custom_mgr_start_hw(void *hw_mgr_priv, + void *start_hw_args) +{ + int rc = 0; + struct cam_hw_config_args *hw_config; + struct cam_hw_stop_args stop_args; + struct cam_custom_hw_mgr_res *hw_mgr_res; + struct cam_custom_hw_mgr_ctx *ctx; + struct cam_custom_stop_args custom_stop_args; + struct cam_custom_start_args *custom_args; + + if (!hw_mgr_priv || !start_hw_args) { + CAM_ERR(CAM_CUSTOM, "Invalid arguments"); + return -EINVAL; + } + + custom_args = + (struct cam_custom_start_args *)start_hw_args; + + hw_config = (struct cam_hw_config_args *) + &custom_args->hw_config; + + ctx = (struct cam_custom_hw_mgr_ctx *) + hw_config->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_CUSTOM, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_CUSTOM, "Enter... ctx id:%d", + ctx->ctx_index); + + if (custom_args->start_only) + goto start_only; + + /* Init custom cid */ + list_for_each_entry(hw_mgr_res, + &ctx->res_list_custom_cid, list) { + rc = cam_custom_hw_mgr_init_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Can not INIT CID(id :%d)", + hw_mgr_res->res_id); + goto deinit_hw; + } + } + + /* Init custom csid */ + list_for_each_entry(hw_mgr_res, + &ctx->res_list_custom_csid, list) { + rc = cam_custom_hw_mgr_init_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Can not INIT CSID(id :%d)", + hw_mgr_res->res_id); + goto deinit_hw; + } + } + + + /* Init custom hw here */ + + /* Apply init config */ + +start_only: + + /* Start custom HW first */ + if (rc < 0) + goto err; + + /* Start custom csid */ + list_for_each_entry(hw_mgr_res, + &ctx->res_list_custom_csid, list) { + rc = cam_custom_hw_mgr_start_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Can not START CSID(id :%d)", + hw_mgr_res->res_id); + goto err; + } + } + + /* Start custom cid */ + list_for_each_entry(hw_mgr_res, + &ctx->res_list_custom_cid, list) { + rc = cam_custom_hw_mgr_start_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Can not START CID(id :%d)", + hw_mgr_res->res_id); + goto err; + } + } + + CAM_DBG(CAM_CUSTOM, "Start success for ctx id:%d", ctx->ctx_index); + return 0; + +err: + custom_stop_args.stop_only = false; + stop_args.args = (void *) &custom_stop_args; + stop_args.ctxt_to_hw_map = hw_config->ctxt_to_hw_map; + cam_custom_mgr_stop_hw(hw_mgr_priv, &stop_args); +deinit_hw: + /* deinit the hw previously initialized */ + CAM_DBG(CAM_CUSTOM, "Exit...(rc=%d)", rc); + return rc; +} + +static int cam_custom_mgr_read(void *hw_mgr_priv, void *read_args) +{ + return -EPERM; +} + +static int cam_custom_mgr_write(void *hw_mgr_priv, void *write_args) +{ + return -EPERM; +} + +static int cam_custom_hw_mgr_put_ctx( + struct list_head *src_list, + struct cam_custom_hw_mgr_ctx **custom_ctx) +{ + struct cam_custom_hw_mgr_ctx *ctx_ptr = NULL; + + ctx_ptr = *custom_ctx; + if (ctx_ptr) + list_add_tail(&ctx_ptr->list, src_list); + *custom_ctx = NULL; + return 0; +} + +static int cam_custom_hw_mgr_get_ctx( + struct list_head *src_list, + struct cam_custom_hw_mgr_ctx **custom_ctx) +{ + struct cam_custom_hw_mgr_ctx *ctx_ptr = NULL; + + if (!list_empty(src_list)) { + ctx_ptr = list_first_entry(src_list, + struct cam_custom_hw_mgr_ctx, list); + list_del_init(&ctx_ptr->list); + } else { + CAM_ERR(CAM_CUSTOM, "No more free custom hw mgr ctx"); + return -EINVAL; + } + *custom_ctx = ctx_ptr; + memset(ctx_ptr->sub_hw_list, 0, + sizeof(struct cam_custom_hw_mgr_res) * + CAM_CUSTOM_HW_RES_MAX); + + return 0; +} + +static int cam_custom_hw_mgr_put_res( + struct list_head *src_list, + struct cam_custom_hw_mgr_res **res) +{ + struct cam_custom_hw_mgr_res *res_ptr = NULL; + + res_ptr = *res; + if (res_ptr) + list_add_tail(&res_ptr->list, src_list); + + return 0; +} + +static int cam_custom_hw_mgr_get_res( + struct list_head *src_list, + struct cam_custom_hw_mgr_res **res) +{ + int rc = 0; + struct cam_custom_hw_mgr_res *res_ptr = NULL; + + if (!list_empty(src_list)) { + res_ptr = list_first_entry(src_list, + struct cam_custom_hw_mgr_res, list); + list_del_init(&res_ptr->list); + } else { + CAM_ERR(CAM_CUSTOM, "No more free custom ctx rsrc"); + rc = -1; + } + *res = res_ptr; + + return rc; +} + +static enum cam_ife_pix_path_res_id + cam_custom_hw_mgr_get_csid_res_type( + uint32_t out_port_type) +{ + enum cam_ife_pix_path_res_id path_id; + + CAM_DBG(CAM_CUSTOM, "out_port_type %x", out_port_type); + + switch (out_port_type) { + case CAM_CUSTOM_OUT_RES_UDI_0: + path_id = CAM_IFE_PIX_PATH_RES_UDI_0; + break; + case CAM_CUSTOM_OUT_RES_UDI_1: + path_id = CAM_IFE_PIX_PATH_RES_UDI_1; + break; + case CAM_CUSTOM_OUT_RES_UDI_2: + path_id = CAM_IFE_PIX_PATH_RES_UDI_2; + break; + default: + path_id = CAM_IFE_PIX_PATH_RES_MAX; + CAM_DBG(CAM_CUSTOM, "maximum rdi output type exceeded"); + break; + } + + CAM_DBG(CAM_CUSTOM, "out_port %x path_id %d", out_port_type, path_id); + + return path_id; +} + +static int cam_custom_hw_mgr_acquire_cid_res( + struct cam_custom_hw_mgr_ctx *custom_ctx, + struct cam_isp_in_port_generic_info *in_port, + struct cam_custom_hw_mgr_res **cid_res, + enum cam_ife_pix_path_res_id path_res_id, + struct cam_isp_resource_node **cid_rsrc_node) +{ + int rc = -1; + int i; + struct cam_custom_hw_mgr *custom_hw_mgr; + struct cam_hw_intf *hw_intf; + struct cam_custom_hw_mgr_res *cid_res_temp; + struct cam_csid_hw_reserve_resource_args csid_acquire; + struct cam_isp_resource_node *isp_rsrc_node; + struct cam_isp_out_port_generic_info *out_port = NULL; + + custom_hw_mgr = custom_ctx->hw_mgr; + *cid_res = NULL; + + rc = cam_custom_hw_mgr_get_res( + &custom_ctx->free_res_list, cid_res); + if (rc) { + CAM_ERR(CAM_CUSTOM, "No more free hw mgr resource"); + goto end; + } + + memset(&csid_acquire, 0, sizeof(csid_acquire)); + cid_res_temp = *cid_res; + csid_acquire.res_type = CAM_ISP_RESOURCE_CID; + csid_acquire.in_port = in_port; + csid_acquire.res_id = path_res_id; + csid_acquire.node_res = NULL; + CAM_DBG(CAM_CUSTOM, "path_res_id %d", path_res_id); + + if (in_port->num_out_res) + out_port = &(in_port->data[0]); + + for (i = 0; i < CAM_CUSTOM_CSID_HW_MAX; i++) { + if (!custom_hw_mgr->csid_devices[i]) + continue; + + hw_intf = custom_hw_mgr->csid_devices[i]; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + /* since there is a need of 1 cid at this stage */ + if (rc) + continue; + else + break; + + } + + if (!csid_acquire.node_res) { + CAM_ERR(CAM_CUSTOM, + "Can not acquire custom cid resource for path %d", + path_res_id); + rc = -EAGAIN; + goto put_res; + } + + *cid_rsrc_node = csid_acquire.node_res; + isp_rsrc_node = csid_acquire.node_res; + cid_res_temp->rsrc_node = isp_rsrc_node; + cid_res_temp->res_type = CAM_CUSTOM_CID_HW; + cid_res_temp->res_id = isp_rsrc_node->res_id; + cam_custom_hw_mgr_put_res(&custom_ctx->res_list_custom_cid, + &cid_res_temp); + + CAM_DBG(CAM_CUSTOM, "CID acquired successfully %u", + isp_rsrc_node->res_id); + + return 0; + +put_res: + cam_custom_hw_mgr_put_res(&custom_ctx->free_res_list, cid_res); +end: + return rc; + +} + +static int cam_custom_hw_mgr_acquire_csid_res( + struct cam_custom_hw_mgr_ctx *custom_ctx, + struct cam_isp_in_port_generic_info *in_port_info) +{ + int rc = 0, i = 0; + struct cam_custom_hw_mgr *custom_hw_mgr; + struct cam_isp_out_port_generic_info *out_port; + struct cam_custom_hw_mgr_res *custom_csid_res; + struct cam_custom_hw_mgr_res *custom_cid_res; + struct cam_hw_intf *hw_intf; + struct cam_csid_hw_reserve_resource_args custom_csid_acquire; + enum cam_ife_pix_path_res_id path_res_id; + struct cam_isp_resource_node *isp_rsrc_node; + struct cam_isp_resource_node *cid_rsrc_node = NULL; + + custom_hw_mgr = custom_ctx->hw_mgr; + + for (i = 0; i < in_port_info->num_out_res; i++) { + out_port = &in_port_info->data[i]; + path_res_id = cam_custom_hw_mgr_get_csid_res_type( + out_port->res_type); + + if (path_res_id == CAM_IFE_PIX_PATH_RES_MAX) { + CAM_WARN(CAM_CUSTOM, "Invalid out port res_type %u", + out_port->res_type); + continue; + } + + rc = cam_custom_hw_mgr_acquire_cid_res(custom_ctx, in_port_info, + &custom_cid_res, path_res_id, &cid_rsrc_node); + if (rc) { + CAM_ERR(CAM_CUSTOM, "No free cid rsrc %d", rc); + goto end; + } + + rc = cam_custom_hw_mgr_get_res(&custom_ctx->free_res_list, + &custom_csid_res); + if (rc) { + CAM_ERR(CAM_CUSTOM, "No more free hw mgr rsrc"); + goto end; + } + + memset(&custom_csid_acquire, 0, sizeof(custom_csid_acquire)); + custom_csid_acquire.res_id = path_res_id; + custom_csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH; + custom_csid_acquire.cid = cid_rsrc_node->res_id; + custom_csid_acquire.in_port = in_port_info; + custom_csid_acquire.out_port = out_port; + custom_csid_acquire.sync_mode = 0; + custom_csid_acquire.node_res = NULL; + + hw_intf = cid_rsrc_node->hw_intf; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &custom_csid_acquire, sizeof(custom_csid_acquire)); + if (rc) { + CAM_ERR(CAM_CUSTOM, + "Custom csid acquire failed for hw_idx %u rc %d", + hw_intf->hw_idx, rc); + goto put_res; + } + + if (custom_csid_acquire.node_res == NULL) { + CAM_ERR(CAM_CUSTOM, "Acquire custom csid failed"); + rc = -EAGAIN; + goto put_res; + } + + isp_rsrc_node = custom_csid_acquire.node_res; + custom_csid_res->rsrc_node = isp_rsrc_node; + custom_csid_res->res_type = CAM_CUSTOM_CSID_HW; + custom_csid_res->res_id = custom_csid_acquire.res_id; + cam_custom_hw_mgr_put_res( + &custom_ctx->res_list_custom_csid, + &custom_csid_res); + CAM_DBG(CAM_CUSTOM, "Custom CSID acquired for path %d", + path_res_id); + } + + return 0; + +put_res: + cam_custom_hw_mgr_put_res(&custom_ctx->free_res_list, + &custom_csid_res); +end: + return rc; +} + +static int cam_custom_hw_mgr_free_hw_res( + struct cam_custom_hw_mgr_res *hw_mgr_res) +{ + int rc = 0; + struct cam_isp_resource_node *isp_rsrc_node = NULL; + struct cam_hw_intf *hw_intf = NULL; + + isp_rsrc_node = + (struct cam_isp_resource_node *)hw_mgr_res->rsrc_node; + if (!isp_rsrc_node) { + CAM_ERR(CAM_CUSTOM, "Invalid args"); + return -EINVAL; + } + + hw_intf = isp_rsrc_node->hw_intf; + if (hw_intf->hw_ops.release) { + CAM_DBG(CAM_CUSTOM, "RELEASE HW for res_id:%u", + hw_mgr_res->res_id); + rc = hw_intf->hw_ops.release(hw_intf->hw_priv, + isp_rsrc_node, sizeof(struct cam_isp_resource_node)); + if (rc) + CAM_ERR(CAM_CUSTOM, + "Release HW failed for hw_idx %d", + hw_intf->hw_idx); + } + + /* caller should make sure the resource is in a list */ + list_del_init(&hw_mgr_res->list); + memset(hw_mgr_res, 0, sizeof(*hw_mgr_res)); + INIT_LIST_HEAD(&hw_mgr_res->list); + + return 0; +} + +static int cam_custom_hw_mgr_release_hw_for_ctx( + struct cam_custom_hw_mgr_ctx *custom_ctx) +{ + int rc = -1; + struct cam_custom_hw_mgr_res *hw_mgr_res; + struct cam_custom_hw_mgr_res *hw_mgr_res_temp; + + /* Release custom cid */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &custom_ctx->res_list_custom_cid, list) { + rc = cam_custom_hw_mgr_free_hw_res(hw_mgr_res); + if (rc) + CAM_ERR(CAM_CUSTOM, "Can not release CID(id :%d)", + hw_mgr_res->res_id); + cam_custom_hw_mgr_put_res( + &custom_ctx->free_res_list, &hw_mgr_res); + } + + /* Release custom csid */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &custom_ctx->res_list_custom_csid, list) { + rc = cam_custom_hw_mgr_free_hw_res(hw_mgr_res); + if (rc) + CAM_ERR(CAM_CUSTOM, "Can not release CSID(id :%d)", + hw_mgr_res->res_id); + cam_custom_hw_mgr_put_res( + &custom_ctx->free_res_list, &hw_mgr_res); + } + + /* Release custom HW Here */ + + return 0; +} +static int cam_custom_mgr_release_hw(void *hw_mgr_priv, + void *release_hw_args) +{ + int rc = 0; + struct cam_hw_release_args *release_args = release_hw_args; + struct cam_custom_hw_mgr_ctx *custom_ctx; + + if (!hw_mgr_priv || !release_hw_args) { + CAM_ERR(CAM_CUSTOM, "Invalid arguments"); + return -EINVAL; + } + + custom_ctx = + (struct cam_custom_hw_mgr_ctx *)release_args->ctxt_to_hw_map; + if (!custom_ctx || !custom_ctx->ctx_in_use) { + CAM_ERR(CAM_CUSTOM, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_CUSTOM, "Enter...ctx id:%d", + custom_ctx->ctx_index); + + cam_custom_hw_mgr_release_hw_for_ctx(custom_ctx); + list_del_init(&custom_ctx->list); + custom_ctx->ctx_in_use = 0; + cam_custom_hw_mgr_put_ctx(&g_custom_hw_mgr.free_ctx_list, &custom_ctx); + CAM_DBG(CAM_CUSTOM, "Release Exit.."); + return rc; +} + +static int cam_custom_hw_mgr_acquire_get_unified_dev_str( + struct cam_custom_acquire_hw_info *acquire_hw_info, + uint32_t *input_size, + struct cam_isp_in_port_generic_info **gen_port_info) +{ + int32_t rc = 0, i; + uint32_t in_port_length = 0; + struct cam_custom_in_port_info *in = NULL; + struct cam_isp_in_port_generic_info *port_info = NULL; + + in = (struct cam_custom_in_port_info *) + ((uint8_t *)&acquire_hw_info->data + + acquire_hw_info->input_info_offset + *input_size); + + in_port_length = sizeof(struct cam_custom_in_port_info) + + (in->num_out_res - 1) * + sizeof(struct cam_custom_out_port_info); + + *input_size += in_port_length; + + if ((*input_size) > acquire_hw_info->input_info_size) { + CAM_ERR(CAM_CUSTOM, "Input is not proper"); + rc = -EINVAL; + return rc; + } + + port_info = kzalloc( + sizeof(struct cam_isp_in_port_generic_info), GFP_KERNEL); + + if (!port_info) + return -ENOMEM; + + port_info->res_type = in->res_type + + CAM_ISP_IFE_IN_RES_BASE - CAM_CUSTOM_IN_RES_BASE; + port_info->lane_type = in->lane_type; + port_info->lane_num = in->lane_num; + port_info->lane_cfg = in->lane_cfg; + port_info->vc[0] = in->vc[0]; + port_info->dt[0] = in->dt[0]; + port_info->num_valid_vc_dt = in->num_valid_vc_dt; + port_info->format = in->format; + port_info->test_pattern = in->test_pattern; + port_info->usage_type = in->usage_type; + port_info->left_start = in->left_start; + port_info->left_stop = in->left_stop; + port_info->left_width = in->left_width; + port_info->right_start = in->right_start; + port_info->right_stop = in->right_stop; + port_info->right_width = in->right_width; + port_info->line_start = in->line_start; + port_info->line_stop = in->line_stop; + port_info->height = in->height; + port_info->pixel_clk = in->pixel_clk; + port_info->cust_node = 1; + port_info->num_out_res = in->num_out_res; + port_info->num_bytes_out = in->num_bytes_out; + + port_info->data = kcalloc(in->num_out_res, + sizeof(struct cam_isp_out_port_generic_info), + GFP_KERNEL); + if (port_info->data == NULL) { + rc = -ENOMEM; + goto release_port_mem; + } + + for (i = 0; i < in->num_out_res; i++) { + port_info->data[i].res_type = in->data[i].res_type; + port_info->data[i].format = in->data[i].format; + } + + *gen_port_info = port_info; + return 0; + +release_port_mem: + kfree(port_info); + return rc; +} + +static int cam_custom_mgr_acquire_hw_for_ctx( + struct cam_custom_hw_mgr_ctx *custom_ctx, + struct cam_isp_in_port_generic_info *in_port_info, + uint32_t *acquired_hw_id, uint32_t *acquired_hw_path) +{ + int rc = 0, i = 0; + struct cam_hw_intf *hw_intf; + struct cam_custom_hw_mgr *custom_hw_mgr; + struct cam_custom_sub_mod_acq acq; + + custom_hw_mgr = custom_ctx->hw_mgr; + + /* Acquire custom csid */ + rc = cam_custom_hw_mgr_acquire_csid_res(custom_ctx, in_port_info); + if (rc) { + CAM_ERR(CAM_CUSTOM, "Custom csid acquire failed rc %d"); + goto err; + } + + /* Acquire custom hw */ + for (i = 0; i < CAM_CUSTOM_HW_SUB_MOD_MAX; i++) { + hw_intf = custom_hw_mgr->custom_hw[i]; + if (!hw_intf) + continue; + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &acq, sizeof(acq)); + if (rc) { + CAM_DBG(CAM_CUSTOM, + "No custom resource from hw %d", + hw_intf->hw_idx); + continue; + } + /* need to be set in reserve based on HW being acquired */ + //custom_ctx->sub_hw_list[i].hw_res = acq.rsrc_node; + //custom_ctx->sub_hw_list[i].res_type = + //custom_ctx->sub_hw_list[i].res_id = ; + break; + } + +err: + return rc; +} + +static int cam_custom_mgr_acquire_hw( + void *hw_mgr_priv, + void *acquire_hw_args) +{ + int rc = -1, i; + uint32_t input_size = 0; + struct cam_custom_hw_mgr_ctx *custom_ctx; + struct cam_custom_hw_mgr *custom_hw_mgr; + struct cam_custom_acquire_hw_info *acquire_hw_info = NULL; + struct cam_isp_in_port_generic_info *gen_port_info = NULL; + struct cam_hw_acquire_args *acquire_args = + (struct cam_hw_acquire_args *)acquire_hw_args; + + if (!hw_mgr_priv || !acquire_args) { + CAM_ERR(CAM_CUSTOM, "Invalid params"); + return -EINVAL; + } + + custom_hw_mgr = (struct cam_custom_hw_mgr *) hw_mgr_priv; + mutex_lock(&g_custom_hw_mgr.ctx_mutex); + rc = cam_custom_hw_mgr_get_ctx( + &custom_hw_mgr->free_ctx_list, &custom_ctx); + if (rc || !custom_ctx) { + CAM_ERR(CAM_CUSTOM, "Get custom hw context failed"); + mutex_unlock(&g_custom_hw_mgr.ctx_mutex); + goto err; + } + mutex_unlock(&g_custom_hw_mgr.ctx_mutex); + + custom_ctx->hw_mgr = custom_hw_mgr; + custom_ctx->cb_priv = acquire_args->context_data; + custom_ctx->event_cb = acquire_args->event_cb; + + acquire_hw_info = + (struct cam_custom_acquire_hw_info *)acquire_args->acquire_info; + + for (i = 0; i < acquire_hw_info->num_inputs; i++) { + rc = cam_custom_hw_mgr_acquire_get_unified_dev_str( + acquire_hw_info, &input_size, &gen_port_info); + + if (rc < 0) { + CAM_ERR(CAM_CUSTOM, "Failed in parsing: %d", rc); + goto free_res; + } + + CAM_DBG(CAM_CUSTOM, "in_res_type %x", gen_port_info->res_type); + rc = cam_custom_mgr_acquire_hw_for_ctx(custom_ctx, + gen_port_info, &acquire_args->acquired_hw_id[i], + acquire_args->acquired_hw_path[i]); + if (rc) { + CAM_ERR(CAM_CUSTOM, "can not acquire resource"); + goto free_mem; + } + + kfree(gen_port_info->data); + kfree(gen_port_info); + gen_port_info = NULL; + } + + custom_ctx->ctx_in_use = 1; + acquire_args->ctxt_to_hw_map = custom_ctx; + cam_custom_hw_mgr_put_ctx(&custom_hw_mgr->used_ctx_list, &custom_ctx); + CAM_DBG(CAM_CUSTOM, "Exit...(success)"); + return 0; + +free_mem: + kfree(gen_port_info->data); + kfree(gen_port_info); +free_res: + cam_custom_hw_mgr_release_hw_for_ctx(custom_ctx); + cam_custom_hw_mgr_put_ctx(&custom_hw_mgr->free_ctx_list, &custom_ctx); +err: + CAM_DBG(CAM_CUSTOM, "Exit...(rc=%d)", rc); + return rc; +} + +static int cam_custom_add_io_buffers( + int iommu_hdl, + struct cam_hw_prepare_update_args *prepare) +{ + int rc = 0, i = 0; + int32_t hdl; + uint32_t plane_id; + struct cam_buf_io_cfg *io_cfg; + + io_cfg = (struct cam_buf_io_cfg *)((uint8_t *) + &prepare->packet->payload + + prepare->packet->io_configs_offset); + + /* Validate hw update entries */ + + for (i = 0; i < prepare->packet->num_io_configs; i++) { + CAM_DBG(CAM_CUSTOM, "======= io config idx %d ============", i); + CAM_DBG(CAM_CUSTOM, + "i %d req_id %llu resource_type:%d fence:%d direction %d", + i, prepare->packet->header.request_id, + io_cfg[i].resource_type, io_cfg[i].fence, + io_cfg[i].direction); + + CAM_DBG(CAM_CUSTOM, "format: %d", io_cfg[i].format); + + if (io_cfg[i].direction == CAM_BUF_OUTPUT) { + CAM_DBG(CAM_CUSTOM, + "output fence 0x%x", io_cfg[i].fence); + } else if (io_cfg[i].direction == CAM_BUF_INPUT) { + CAM_DBG(CAM_CUSTOM, + "input fence 0x%x", io_cfg[i].fence); + } else { + CAM_ERR(CAM_CUSTOM, "Invalid io config direction :%d", + io_cfg[i].direction); + return -EINVAL; + } + + for (plane_id = 0; plane_id < CAM_PACKET_MAX_PLANES; + plane_id++) { + if (!io_cfg[i].mem_handle[plane_id]) + continue; + + hdl = io_cfg[i].mem_handle[plane_id]; + CAM_DBG(CAM_CUSTOM, "handle 0x%x for plane %d", + hdl, plane_id); + /* Use cam_mem_get_io_buf() to retrieve iova */ + } + + /* Do other I/O config operations */ + } + + return rc; +} + +static int cam_custom_mgr_prepare_hw_update(void *hw_mgr_priv, + void *prepare_hw_update_args) +{ + int rc = 0; + struct cam_hw_prepare_update_args *prepare; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct cam_custom_prepare_hw_update_data *prepare_hw_data; + struct cam_custom_hw_mgr *hw_mgr; + struct cam_custom_hw_mgr_ctx *ctx = NULL; + uint32_t *ptr; + size_t len; + struct cam_custom_cmd_buf_type_1 *custom_buf_type1; + + if (!hw_mgr_priv || !prepare_hw_update_args) { + CAM_ERR(CAM_CUSTOM, "Invalid args"); + return -EINVAL; + } + + hw_mgr = (struct cam_custom_hw_mgr *) hw_mgr_priv; + prepare = + (struct cam_hw_prepare_update_args *) prepare_hw_update_args; + + CAM_DBG(CAM_CUSTOM, "Enter for req_id %lld", + prepare->packet->header.request_id); + + /* Prepare packet */ + prepare_hw_data = + (struct cam_custom_prepare_hw_update_data *)prepare->priv; + prepare_hw_data->packet_opcode_type = + (prepare->packet->header.op_code & 0xFFF); + ctx = (struct cam_custom_hw_mgr_ctx *) prepare->ctxt_to_hw_map; + + /* Test purposes-check the data in cmd buffer */ + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint8_t *)&prepare->packet->payload + + prepare->packet->cmd_buf_offset); + rc = cam_packet_util_get_cmd_mem_addr( + cmd_desc->mem_handle, &ptr, &len); + if (!rc) { + ptr += (cmd_desc->offset / 4); + custom_buf_type1 = + (struct cam_custom_cmd_buf_type_1 *)ptr; + CAM_DBG(CAM_CUSTOM, "frame num %u", + custom_buf_type1->custom_info); + } + + cam_custom_add_io_buffers(hw_mgr->img_iommu_hdl, prepare); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + return 0; +} + +static int cam_custom_hw_mgr_reset_csid_res( + struct cam_custom_hw_mgr_res *hw_mgr_res) +{ + int rc = -1; + struct cam_csid_reset_cfg_args csid_reset_args; + struct cam_isp_resource_node *custom_rsrc_node = NULL; + struct cam_hw_intf *hw_intf = NULL; + + custom_rsrc_node = + (struct cam_isp_resource_node *)hw_mgr_res->rsrc_node; + if (!custom_rsrc_node) { + CAM_ERR(CAM_CUSTOM, "Invalid args"); + return -EINVAL; + } + + csid_reset_args.reset_type = CAM_IFE_CSID_RESET_PATH; + csid_reset_args.node_res = custom_rsrc_node; + hw_intf = custom_rsrc_node->hw_intf; + if (hw_intf->hw_ops.reset) { + CAM_DBG(CAM_CUSTOM, "RESET HW for res_id:%u", + hw_mgr_res->res_id); + rc = hw_intf->hw_ops.reset(hw_intf->hw_priv, + &csid_reset_args, + sizeof(struct cam_csid_reset_cfg_args)); + if (rc) + goto err; + } + + return 0; + +err: + CAM_ERR(CAM_CUSTOM, + "RESET HW failed for res_id:%u", + hw_mgr_res->res_id); + return rc; +} + +static int cam_custom_hw_mgr_reset( + void *hw_mgr_priv, void *hw_reset_args) +{ + struct cam_hw_reset_args *reset_args = + hw_reset_args; + struct cam_custom_hw_mgr_ctx *ctx; + struct cam_custom_hw_mgr_res *hw_mgr_res; + int rc = 0; + + if (!hw_mgr_priv || !hw_reset_args) { + CAM_ERR(CAM_CUSTOM, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_custom_hw_mgr_ctx *) + reset_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_CUSTOM, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_CUSTOM, "Reset SBI CSID and SBI core"); + list_for_each_entry(hw_mgr_res, &ctx->res_list_custom_csid, list) { + rc = cam_custom_hw_mgr_reset_csid_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_CUSTOM, + "Failed to reset CSID:%d rc: %d", + hw_mgr_res->res_id, rc); + goto end; + } + } + + /* Reset SBI HW */ + +end: + return rc; +} + +static int cam_custom_mgr_config_hw(void *hw_mgr_priv, + void *hw_config_args) +{ + int rc = 0; + int i = 0; + struct cam_custom_hw_mgr_ctx *custom_ctx; + struct cam_custom_hw_mgr_res *res; + struct cam_hw_config_args *cfg; + struct cam_hw_intf *hw_intf = NULL; + + CAM_DBG(CAM_CUSTOM, "Enter"); + if (!hw_mgr_priv || !hw_config_args) { + CAM_ERR(CAM_CUSTOM, "Invalid arguments"); + return -EINVAL; + } + + cfg = + (struct cam_hw_config_args *)hw_config_args; + custom_ctx = cfg->ctxt_to_hw_map; + + if (!custom_ctx->ctx_in_use) { + CAM_ERR(CAM_CUSTOM, "Invalid context parameters"); + return -EPERM; + } + + for (i = 0; i < CAM_CUSTOM_HW_SUB_MOD_MAX; i++) { + res = &custom_ctx->sub_hw_list[i]; + if (res->hw_res) { + hw_intf = res->hw_res->hw_intf; + if (hw_intf->hw_ops.process_cmd) { + struct cam_custom_sub_mod_req_to_dev req_to_dev; + + req_to_dev.ctx_idx = custom_ctx->ctx_index; + req_to_dev.dev_idx = i; + req_to_dev.req_id = cfg->request_id; + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_CUSTOM_SUBMIT_REQ, + &req_to_dev, sizeof(req_to_dev)); + } + } + } + + return rc; +} + +static int cam_custom_hw_mgr_irq_cb(void *data, + struct cam_custom_hw_cb_args *cb_args) +{ + struct cam_custom_sub_mod_req_to_dev *proc_req; + struct cam_hw_done_event_data evt_data; + struct cam_custom_hw_mgr_ctx *custom_ctx; + uint32_t ctx_idx; + + proc_req = cb_args->req_info; + ctx_idx = proc_req->ctx_idx; + custom_ctx = &g_custom_hw_mgr.ctx_pool[ctx_idx]; + + if (!custom_ctx->ctx_in_use) { + CAM_ERR(CAM_CUSTOM, "ctx %u not in use", ctx_idx); + return 0; + } + + /* Based on irq status notify success/failure */ + + evt_data.request_id = proc_req->req_id; + custom_ctx->event_cb(custom_ctx->cb_priv, + CAM_CUSTOM_EVENT_BUF_DONE, &evt_data); + + return 0; +} + +int cam_custom_hw_mgr_init(struct device_node *of_node, + struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) +{ + int rc = 0; + int i, j; + struct cam_custom_hw_mgr_ctx *ctx_pool; + struct cam_custom_sub_mod_set_irq_cb irq_cb_args; + struct cam_hw_intf *hw_intf = NULL; + + memset(&g_custom_hw_mgr, 0, sizeof(g_custom_hw_mgr)); + mutex_init(&g_custom_hw_mgr.ctx_mutex); + + /* fill custom hw intf information */ + for (i = 0; i < CAM_CUSTOM_HW_SUB_MOD_MAX; i++) { + /* Initialize sub modules */ + rc = cam_custom_hw_sub_mod_init( + &g_custom_hw_mgr.custom_hw[i], i); + + /* handle in case init fails */ + if (g_custom_hw_mgr.custom_hw[i]) { + hw_intf = g_custom_hw_mgr.custom_hw[i]; + if (hw_intf->hw_ops.process_cmd) { + irq_cb_args.custom_hw_mgr_cb = + cam_custom_hw_mgr_irq_cb; + irq_cb_args.data = + g_custom_hw_mgr.custom_hw[i]->hw_priv; + hw_intf->hw_ops.process_cmd(hw_intf->hw_priv, + CAM_CUSTOM_SET_IRQ_CB, &irq_cb_args, + sizeof(irq_cb_args)); + } + } + } + + for (i = 0; i < CAM_CUSTOM_CSID_HW_MAX; i++) { + /* Initialize csid custom modules */ + rc = cam_custom_csid_hw_init( + &g_custom_hw_mgr.csid_devices[i], i); + } + + INIT_LIST_HEAD(&g_custom_hw_mgr.free_ctx_list); + INIT_LIST_HEAD(&g_custom_hw_mgr.used_ctx_list); + + /* + * for now, we only support one iommu handle. later + * we will need to setup more iommu handle for other + * use cases. + * Also, we have to release them once we have the + * deinit support + */ + if (cam_smmu_get_handle("custom", + &g_custom_hw_mgr.img_iommu_hdl)) { + CAM_ERR(CAM_CUSTOM, "Can not get iommu handle"); + return -EINVAL; + } + + for (i = 0; i < CAM_CTX_MAX; i++) { + memset(&g_custom_hw_mgr.ctx_pool[i], 0, + sizeof(g_custom_hw_mgr.ctx_pool[i])); + INIT_LIST_HEAD(&g_custom_hw_mgr.ctx_pool[i].list); + + ctx_pool = &g_custom_hw_mgr.ctx_pool[i]; + + /* init context pool */ + INIT_LIST_HEAD(&g_custom_hw_mgr.ctx_pool[i].free_res_list); + INIT_LIST_HEAD( + &g_custom_hw_mgr.ctx_pool[i].res_list_custom_csid); + INIT_LIST_HEAD( + &g_custom_hw_mgr.ctx_pool[i].res_list_custom_cid); + for (j = 0; j < CAM_CUSTOM_HW_RES_MAX; j++) { + INIT_LIST_HEAD( + &g_custom_hw_mgr.ctx_pool[i].res_pool[j].list); + list_add_tail( + &g_custom_hw_mgr.ctx_pool[i].res_pool[j].list, + &g_custom_hw_mgr.ctx_pool[i].free_res_list); + } + + g_custom_hw_mgr.ctx_pool[i].ctx_index = i; + g_custom_hw_mgr.ctx_pool[i].hw_mgr = &g_custom_hw_mgr; + + list_add_tail(&g_custom_hw_mgr.ctx_pool[i].list, + &g_custom_hw_mgr.free_ctx_list); + } + + /* fill return structure */ + hw_mgr_intf->hw_mgr_priv = &g_custom_hw_mgr; + hw_mgr_intf->hw_get_caps = cam_custom_mgr_get_hw_caps; + hw_mgr_intf->hw_acquire = cam_custom_mgr_acquire_hw; + hw_mgr_intf->hw_start = cam_custom_mgr_start_hw; + hw_mgr_intf->hw_stop = cam_custom_mgr_stop_hw; + hw_mgr_intf->hw_read = cam_custom_mgr_read; + hw_mgr_intf->hw_write = cam_custom_mgr_write; + hw_mgr_intf->hw_release = cam_custom_mgr_release_hw; + hw_mgr_intf->hw_prepare_update = cam_custom_mgr_prepare_hw_update; + hw_mgr_intf->hw_config = cam_custom_mgr_config_hw; + hw_mgr_intf->hw_reset = cam_custom_hw_mgr_reset; + + if (iommu_hdl) + *iommu_hdl = g_custom_hw_mgr.img_iommu_hdl; + + CAM_DBG(CAM_CUSTOM, "HW manager initialized"); + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.h b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.h new file mode 100644 index 0000000000000000000000000000000000000000..64f4555528bf6eb1e88d91a0a7fce1a6d1e11e21 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CUSTOM_HW_MGR_H_ +#define _CAM_CUSTOM_HW_MGR_H_ + +#include +#include "cam_custom_hw_mgr_intf.h" +#include "cam_custom_sub_mod_core.h" +#include "cam_ife_csid_hw_intf.h" +#include "cam_isp_hw.h" +#include "cam_custom_hw.h" +#include +#include + +enum cam_custom_hw_mgr_res_type { + CAM_CUSTOM_HW_SUB_MODULE, + CAM_CUSTOM_CID_HW, + CAM_CUSTOM_CSID_HW, + CAM_CUSTOM_HW_MAX, +}; + +/* Needs to be suitably defined */ +#define CAM_CUSTOM_HW_OUT_RES_MAX 1 + +/** + * struct cam_custom_hw_mgr_res - HW resources for the Custom manager + * + * @list: used by the resource list + * @res_type: Custom manager resource type + * @res_id: resource id based on the resource type for root or + * leaf resource, it matches the KMD interface port id. + * For branch resource, it is defined by the Custom HW + * layer + * @rsrc_node: isp hw layer resource for csid/cid + * @hw_res: hw layer resource array. + */ +struct cam_custom_hw_mgr_res { + struct list_head list; + enum cam_custom_hw_mgr_res_type res_type; + uint32_t res_id; + void *rsrc_node; + struct cam_custom_resource_node *hw_res; +}; + + +/** + * struct ctx_base_info - Base hardware information for the context + * + * @idx: Base resource index + * + */ +struct ctx_base_info { + uint32_t idx; +}; + + +/** + * struct cam_custom_hw_mgr_ctx - Custom HW manager ctx object + * + * @list: used by the ctx list. + * @ctx_index: acquired context id. + * @hw_mgr: Custom hw mgr which owns this context + * @ctx_in_use: flag to tell whether context is active + * @res_list_custom_csid: custom csid modules for this context + * @res_list_custom_cid: custom cid modules for this context + * @sub_hw_list: HW submodules for this context + * @free_res_list: Free resources list for the branch node + * @res_pool: memory storage for the free resource list + * @base: device base index array contain the all + * Custom HW instance associated with this ctx. + * @num_base: number of valid base data in the base array + * @init_done: indicate whether init hw is done + * @event_cb: event_cb to ctx + * @cb_priv: data sent back with event_cb + * + */ +struct cam_custom_hw_mgr_ctx { + struct list_head list; + + uint32_t ctx_index; + struct cam_custom_hw_mgr *hw_mgr; + uint32_t ctx_in_use; + + struct list_head res_list_custom_csid; + struct list_head res_list_custom_cid; + struct cam_custom_hw_mgr_res sub_hw_list[ + CAM_CUSTOM_HW_RES_MAX]; + + struct list_head free_res_list; + struct cam_custom_hw_mgr_res res_pool[CAM_CUSTOM_HW_RES_MAX]; + struct ctx_base_info base[CAM_CUSTOM_HW_SUB_MOD_MAX]; + uint32_t num_base; + bool init_done; + cam_hw_event_cb_func event_cb; + void *cb_priv; +}; + +/** + * struct cam_custom_hw_mgr - Custom HW Manager + * + * @img_iommu_hdl: iommu handle + * @custom_hw: Custom device instances array. This will be filled by + * HW layer during initialization + * @csid_devices: Custom csid device instance array + * @ctx_mutex: mutex for the hw context pool + * @free_ctx_list: free hw context list + * @used_ctx_list: used hw context list + * @ctx_pool: context storage + * + */ +struct cam_custom_hw_mgr { + int img_iommu_hdl; + struct cam_hw_intf *custom_hw[CAM_CUSTOM_HW_SUB_MOD_MAX]; + struct cam_hw_intf *csid_devices[CAM_CUSTOM_CSID_HW_MAX]; + struct mutex ctx_mutex; + struct list_head free_ctx_list; + struct list_head used_ctx_list; + struct cam_custom_hw_mgr_ctx ctx_pool[CAM_CTX_MAX]; +}; + +/** + * cam_custom_hw_mgr_init() + * + * @brief: Initialize the Custom hardware manger. This is the + * etnry functinon for the Cust HW manager. + * + * @of_node: Device node + * @hw_mgr_intf: Custom hardware manager object returned + * @iommu_hdl: Iommu handle to be returned + * + */ +int cam_custom_hw_mgr_init(struct device_node *of_node, + struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl); + + +/* Utility APIs */ + +/** + * cam_custom_hw_mgr_get_custom_res_state() + * + * @brief: Obtain equivalent custom rsrc state + * from isp rsrc state + * + * @in_rsrc_state: isp rsrc state + * + */ +enum cam_custom_hw_resource_state + cam_custom_hw_mgr_get_custom_res_state( + uint32_t in_rsrc_state); + +/** + * cam_custom_hw_mgr_get_isp_res_state() + * + * @brief: Obtain equivalent isp rsrc state + * from custom rsrc state + * + * @in_rsrc_state: custom rsrc state + * + */ +enum cam_isp_resource_state + cam_custom_hw_mgr_get_isp_res_state( + uint32_t in_rsrc_state); + +/** + * cam_custom_hw_mgr_get_isp_res_type() + * + * @brief: Obtain equivalent isp rsrc type + * from custom rsrc type + * + * @res_type: custom rsrc type + * + */ +enum cam_isp_resource_type + cam_custom_hw_mgr_get_isp_res_type( + enum cam_custom_hw_mgr_res_type res_type); + +#endif /* _CAM_CUSTOM_HW_MGR_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include/cam_custom_hw.h b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include/cam_custom_hw.h new file mode 100644 index 0000000000000000000000000000000000000000..0fd557c14052b362bbb98348b6952d73d4583761 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include/cam_custom_hw.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CUSTOM_HW_H_ +#define _CAM_CUSTOM_HW_H_ + +#include +#include +#include +#include + +enum cam_custom_hw_resource_state { + CAM_CUSTOM_HW_RESOURCE_STATE_UNAVAILABLE = 0, + CAM_CUSTOM_HW_RESOURCE_STATE_AVAILABLE = 1, + CAM_CUSTOM_HW_RESOURCE_STATE_RESERVED = 2, + CAM_CUSTOM_HW_RESOURCE_STATE_INIT_HW = 3, + CAM_CUSTOM_HW_RESOURCE_STATE_STREAMING = 4, +}; + +/* + * struct cam_custom_resource_node: + * + * @Brief: Structure representing HW resource object + * + * @res_id: Unique resource ID within res_type objects + * for a particular HW + * @res_state: State of the resource + * @hw_intf: HW Interface of HW to which this resource + * belongs + * @res_priv: Private data of the resource + * @irq_handle: handle returned on subscribing for IRQ event + * @init: function pointer to init the HW resource + * @deinit: function pointer to deinit the HW resource + * @start: function pointer to start the HW resource + * @stop: function pointer to stop the HW resource + * @process_cmd: function pointer for processing commands + * specific to the resource + */ +struct cam_custom_resource_node { + uint32_t res_id; + enum cam_custom_hw_resource_state res_state; + struct cam_hw_intf *hw_intf; + void *res_priv; + int irq_handle; + + int (*init)(struct cam_custom_resource_node *rsrc_node, + void *init_args, uint32_t arg_size); + int (*deinit)(struct cam_custom_resource_node *rsrc_node, + void *deinit_args, uint32_t arg_size); + int (*start)(struct cam_custom_resource_node *rsrc_node); + int (*stop)(struct cam_custom_resource_node *rsrc_node); + int (*process_cmd)(struct cam_custom_resource_node *rsrc_node, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size); +}; +#endif /* _CAM_CUSTOM_HW_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include/cam_custom_hw_mgr_intf.h b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include/cam_custom_hw_mgr_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..b1fb1cb42913c7cac1c6bbf9a928251f7f9bf981 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include/cam_custom_hw_mgr_intf.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CUSTOM_HW_MGR_INTF_H_ +#define _CAM_CUSTOM_HW_MGR_INTF_H_ + +#include +#include +#include +#include +#include "cam_hw.h" +#include "cam_hw_mgr_intf.h" +#include "cam_hw_intf.h" + +#define CAM_CUSTOM_HW_TYPE_1 1 + +#define CAM_CUSTOM_HW_RES_MAX 32 + +#define CAM_CUSTOM_HW_SUB_MOD_MAX 1 +#define CAM_CUSTOM_CSID_HW_MAX 1 + +enum cam_custom_hw_event_type { + CAM_CUSTOM_EVENT_TYPE_ERROR, + CAM_CUSTOM_EVENT_BUF_DONE, +}; + +enum cam_custom_cmd_types { + CAM_CUSTOM_CMD_NONE, + CAM_CUSTOM_SET_IRQ_CB, + CAM_CUSTOM_SUBMIT_REQ, +}; + +/** + * struct cam_custom_stop_args - hardware stop arguments + * + * @stop_only Send stop only to hw drivers. No Deinit to be + * done. + */ +struct cam_custom_stop_args { + bool stop_only; +}; + +/** + * struct cam_custom_start_args - custom hardware start arguments + * + * @hw_config: Hardware configuration commands. + * @start_only Send start only to hw drivers. No init to + * be done. + * + */ +struct cam_custom_start_args { + struct cam_hw_config_args hw_config; + bool start_only; +}; + +/** + * struct cam_custom_prepare_hw_update_data - hw prepare data + * + * @packet_opcode_type: Packet header opcode in the packet header + * this opcode defines, packet is init packet or + * update packet + * + */ +struct cam_custom_prepare_hw_update_data { + uint32_t packet_opcode_type; +}; + +/** + * struct cam_custom_hw_cb_args : HW manager callback args + * + * @irq_status : irq status + * @req_info : Pointer to the request info associated with the cb + */ +struct cam_custom_hw_cb_args { + uint32_t irq_status; + struct cam_custom_sub_mod_req_to_dev *req_info; +}; + +/** + * cam_custom_hw_sub_mod_init() + * + * @Brief: Initialize Custom HW device + * + * @custom_hw: cust_hw interface to fill in and return on + * successful initialization + * @hw_idx: Index of Custom HW + */ +int cam_custom_hw_sub_mod_init(struct cam_hw_intf **custom_hw, uint32_t hw_idx); + +/** + * cam_custom_csid_hw_init() + * + * @Brief: Initialize Custom HW device + * + * @custom_hw: cust_hw interface to fill in and return on + * successful initialization + * @hw_idx: Index of Custom HW + */ +int cam_custom_csid_hw_init( + struct cam_hw_intf **custom_hw, uint32_t hw_idx); + +#endif /* _CAM_CUSTOM_HW_MGR_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_fd/Makefile b/techpack/camera-bengal/drivers/cam_fd/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..10103b34a0ff5ca2ec848b33a0a5cf68c256a507 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += fd_hw_mgr/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_fd_dev.o cam_fd_context.o diff --git a/techpack/camera-bengal/drivers/cam_fd/cam_fd_context.c b/techpack/camera-bengal/drivers/cam_fd/cam_fd_context.c new file mode 100644 index 0000000000000000000000000000000000000000..99887d30242d4b052921b20546b2e774b9a49083 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/cam_fd_context.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include + +#include "cam_debug_util.h" +#include "cam_fd_context.h" +#include "cam_trace.h" + +static const char fd_dev_name[] = "cam-fd"; + +/* Functions in Available state */ +static int __cam_fd_ctx_acquire_dev_in_available(struct cam_context *ctx, + struct cam_acquire_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_acquire_dev_to_hw(ctx, cmd); + if (rc) { + CAM_ERR(CAM_FD, "Failed in Acquire dev, rc=%d", rc); + return rc; + } + + ctx->state = CAM_CTX_ACQUIRED; + trace_cam_context_state("FD", ctx); + + return rc; +} + +/* Functions in Acquired state */ +static int __cam_fd_ctx_release_dev_in_acquired(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_release_dev_to_hw(ctx, cmd); + if (rc) { + CAM_ERR(CAM_FD, "Failed in Release dev, rc=%d", rc); + return rc; + } + + ctx->state = CAM_CTX_AVAILABLE; + trace_cam_context_state("FD", ctx); + + return rc; +} + +static int __cam_fd_ctx_config_dev_in_acquired(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_prepare_dev_to_hw(ctx, cmd); + if (rc) { + CAM_ERR(CAM_FD, "Failed in Prepare dev, rc=%d", rc); + return rc; + } + + return rc; +} + +static int __cam_fd_ctx_start_dev_in_acquired(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_start_dev_to_hw(ctx, cmd); + if (rc) { + CAM_ERR(CAM_FD, "Failed in Start dev, rc=%d", rc); + return rc; + } + + ctx->state = CAM_CTX_ACTIVATED; + trace_cam_context_state("FD", ctx); + + return rc; +} + +/* Functions in Activated state */ +static int __cam_fd_ctx_stop_dev_in_activated(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_stop_dev_to_hw(ctx); + if (rc) { + CAM_ERR(CAM_FD, "Failed in Stop dev, rc=%d", rc); + return rc; + } + + ctx->state = CAM_CTX_ACQUIRED; + trace_cam_context_state("FD", ctx); + + return rc; +} + +static int __cam_fd_ctx_release_dev_in_activated(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc; + + rc = __cam_fd_ctx_stop_dev_in_activated(ctx, NULL); + if (rc) { + CAM_ERR(CAM_FD, "Failed in Stop dev, rc=%d", rc); + return rc; + } + + rc = __cam_fd_ctx_release_dev_in_acquired(ctx, cmd); + if (rc) { + CAM_ERR(CAM_FD, "Failed in Release dev, rc=%d", rc); + return rc; + } + + return rc; +} + +static int __cam_fd_ctx_dump_dev_in_activated( + struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc; + + rc = cam_context_dump_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_FD, "Failed to dump device, rc=%d", rc); + + return rc; +} + +static int __cam_fd_ctx_flush_dev_in_activated(struct cam_context *ctx, + struct cam_flush_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_flush_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_ICP, "Failed to flush device, rc=%d", rc); + + return rc; +} +static int __cam_fd_ctx_config_dev_in_activated( + struct cam_context *ctx, struct cam_config_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_prepare_dev_to_hw(ctx, cmd); + if (rc) { + CAM_ERR(CAM_FD, "Failed in Prepare dev, rc=%d", rc); + return rc; + } + + return rc; +} + +static int __cam_fd_ctx_handle_irq_in_activated(void *context, + uint32_t evt_id, void *evt_data) +{ + int rc; + + rc = cam_context_buf_done_from_hw(context, evt_data, evt_id); + if (rc) { + CAM_ERR(CAM_FD, "Failed in buf done, rc=%d", rc); + return rc; + } + + return rc; +} + +/* top state machine */ +static struct cam_ctx_ops + cam_fd_ctx_state_machine[CAM_CTX_STATE_MAX] = { + /* Uninit */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Available */ + { + .ioctl_ops = { + .acquire_dev = __cam_fd_ctx_acquire_dev_in_available, + }, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Acquired */ + { + .ioctl_ops = { + .release_dev = __cam_fd_ctx_release_dev_in_acquired, + .config_dev = __cam_fd_ctx_config_dev_in_acquired, + .start_dev = __cam_fd_ctx_start_dev_in_acquired, + }, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Ready */ + { + .ioctl_ops = { }, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Flushed */ + {}, + /* Activated */ + { + .ioctl_ops = { + .stop_dev = __cam_fd_ctx_stop_dev_in_activated, + .release_dev = __cam_fd_ctx_release_dev_in_activated, + .config_dev = __cam_fd_ctx_config_dev_in_activated, + .flush_dev = __cam_fd_ctx_flush_dev_in_activated, + .dump_dev = __cam_fd_ctx_dump_dev_in_activated, + }, + .crm_ops = {}, + .irq_ops = __cam_fd_ctx_handle_irq_in_activated, + }, +}; + + +int cam_fd_context_init(struct cam_fd_context *fd_ctx, + struct cam_context *base_ctx, struct cam_hw_mgr_intf *hw_intf, + uint32_t ctx_id) +{ + int rc; + + if (!base_ctx || !fd_ctx) { + CAM_ERR(CAM_FD, "Invalid Context %pK %pK", base_ctx, fd_ctx); + return -EINVAL; + } + + memset(fd_ctx, 0, sizeof(*fd_ctx)); + + rc = cam_context_init(base_ctx, fd_dev_name, CAM_FD, ctx_id, + NULL, hw_intf, fd_ctx->req_base, CAM_CTX_REQ_MAX); + if (rc) { + CAM_ERR(CAM_FD, "Camera Context Base init failed, rc=%d", rc); + return rc; + } + + fd_ctx->base = base_ctx; + base_ctx->ctx_priv = fd_ctx; + base_ctx->state_machine = cam_fd_ctx_state_machine; + + return rc; +} + +int cam_fd_context_deinit(struct cam_fd_context *fd_ctx) +{ + int rc = 0; + + if (!fd_ctx || !fd_ctx->base) { + CAM_ERR(CAM_FD, "Invalid inputs %pK", fd_ctx); + return -EINVAL; + } + + rc = cam_context_deinit(fd_ctx->base); + if (rc) + CAM_ERR(CAM_FD, "Error in base deinit, rc=%d", rc); + + memset(fd_ctx, 0, sizeof(*fd_ctx)); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_fd/cam_fd_context.h b/techpack/camera-bengal/drivers/cam_fd/cam_fd_context.h new file mode 100644 index 0000000000000000000000000000000000000000..ab0fa92b43f2894fbf9d7b4e76635883d1102005 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/cam_fd_context.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_FD_CONTEXT_H_ +#define _CAM_FD_CONTEXT_H_ + +#include "cam_context.h" +#include "cam_context_utils.h" +#include "cam_hw_mgr_intf.h" +#include "cam_req_mgr_interface.h" + +/** + * struct cam_fd_context - Face Detection context information + * + * @base : Base context pointer for this FD context + * @req_base : List of base requests for this FD context + */ +struct cam_fd_context { + struct cam_context *base; + struct cam_ctx_request req_base[CAM_CTX_REQ_MAX]; +}; + +int cam_fd_context_init(struct cam_fd_context *fd_ctx, + struct cam_context *base_ctx, struct cam_hw_mgr_intf *hw_intf, + uint32_t ctx_id); +int cam_fd_context_deinit(struct cam_fd_context *ctx); + +#endif /* _CAM_FD_CONTEXT_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_fd/cam_fd_dev.c b/techpack/camera-bengal/drivers/cam_fd/cam_fd_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..f492696ae3a34899b461db5eab51e62bfa4e2475 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/cam_fd_dev.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "cam_subdev.h" +#include "cam_node.h" +#include "cam_fd_context.h" +#include "cam_fd_hw_mgr.h" +#include "cam_fd_hw_mgr_intf.h" + +#define CAM_FD_DEV_NAME "cam-fd" + +/** + * struct cam_fd_dev - FD device information + * + * @sd: Subdev information + * @base_ctx: List of base contexts + * @fd_ctx: List of FD contexts + * @lock: Mutex handle + * @open_cnt: FD subdev open count + * @probe_done: Whether FD probe is completed + */ +struct cam_fd_dev { + struct cam_subdev sd; + struct cam_context base_ctx[CAM_CTX_MAX]; + struct cam_fd_context fd_ctx[CAM_CTX_MAX]; + struct mutex lock; + uint32_t open_cnt; + bool probe_done; +}; + +static struct cam_fd_dev g_fd_dev; + +static int cam_fd_dev_open(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct cam_fd_dev *fd_dev = &g_fd_dev; + + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); + + if (!fd_dev->probe_done) { + CAM_ERR(CAM_FD, "FD Dev not initialized, fd_dev=%pK", fd_dev); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); + return -ENODEV; + } + + mutex_lock(&fd_dev->lock); + fd_dev->open_cnt++; + CAM_DBG(CAM_FD, "FD Subdev open count %d", fd_dev->open_cnt); + mutex_unlock(&fd_dev->lock); + + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); + + return 0; +} + +static int cam_fd_dev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct cam_fd_dev *fd_dev = &g_fd_dev; + struct cam_node *node = v4l2_get_subdevdata(sd); + + if (!fd_dev->probe_done) { + CAM_ERR(CAM_FD, "FD Dev not initialized, fd_dev=%pK", fd_dev); + return -ENODEV; + } + + mutex_lock(&fd_dev->lock); + fd_dev->open_cnt--; + CAM_DBG(CAM_FD, "FD Subdev open count %d", fd_dev->open_cnt); + mutex_unlock(&fd_dev->lock); + + if (!node) { + CAM_ERR(CAM_FD, "Node ptr is NULL"); + return -EINVAL; + } + + cam_node_shutdown(node); + + return 0; +} + +static const struct v4l2_subdev_internal_ops cam_fd_subdev_internal_ops = { + .open = cam_fd_dev_open, + .close = cam_fd_dev_close, +}; + +static int cam_fd_dev_probe(struct platform_device *pdev) +{ + int rc; + int i; + struct cam_hw_mgr_intf hw_mgr_intf; + struct cam_node *node; + + g_fd_dev.sd.internal_ops = &cam_fd_subdev_internal_ops; + + /* Initialize the v4l2 subdevice first. (create cam_node) */ + rc = cam_subdev_probe(&g_fd_dev.sd, pdev, CAM_FD_DEV_NAME, + CAM_FD_DEVICE_TYPE); + if (rc) { + CAM_ERR(CAM_FD, "FD cam_subdev_probe failed, rc=%d", rc); + return rc; + } + node = (struct cam_node *) g_fd_dev.sd.token; + + rc = cam_fd_hw_mgr_init(pdev->dev.of_node, &hw_mgr_intf); + if (rc) { + CAM_ERR(CAM_FD, "Failed in initializing FD HW manager, rc=%d", + rc); + goto unregister_subdev; + } + + for (i = 0; i < CAM_CTX_MAX; i++) { + rc = cam_fd_context_init(&g_fd_dev.fd_ctx[i], + &g_fd_dev.base_ctx[i], &node->hw_mgr_intf, i); + if (rc) { + CAM_ERR(CAM_FD, "FD context init failed i=%d, rc=%d", + i, rc); + goto deinit_ctx; + } + } + + rc = cam_node_init(node, &hw_mgr_intf, g_fd_dev.base_ctx, CAM_CTX_MAX, + CAM_FD_DEV_NAME); + if (rc) { + CAM_ERR(CAM_FD, "FD node init failed, rc=%d", rc); + goto deinit_ctx; + } + + mutex_init(&g_fd_dev.lock); + g_fd_dev.probe_done = true; + + CAM_DBG(CAM_FD, "Camera FD probe complete"); + + return 0; + +deinit_ctx: + for (--i; i >= 0; i--) { + if (cam_fd_context_deinit(&g_fd_dev.fd_ctx[i])) + CAM_ERR(CAM_FD, "FD context %d deinit failed", i); + } +unregister_subdev: + if (cam_subdev_remove(&g_fd_dev.sd)) + CAM_ERR(CAM_FD, "Failed in subdev remove"); + + return rc; +} + +static int cam_fd_dev_remove(struct platform_device *pdev) +{ + int i, rc; + + for (i = 0; i < CAM_CTX_MAX; i++) { + rc = cam_fd_context_deinit(&g_fd_dev.fd_ctx[i]); + if (rc) + CAM_ERR(CAM_FD, "FD context %d deinit failed, rc=%d", + i, rc); + } + + rc = cam_fd_hw_mgr_deinit(pdev->dev.of_node); + if (rc) + CAM_ERR(CAM_FD, "Failed in hw mgr deinit, rc=%d", rc); + + rc = cam_subdev_remove(&g_fd_dev.sd); + if (rc) + CAM_ERR(CAM_FD, "Unregister failed, rc=%d", rc); + + mutex_destroy(&g_fd_dev.lock); + g_fd_dev.probe_done = false; + + return rc; +} + +static const struct of_device_id cam_fd_dt_match[] = { + { + .compatible = "qcom,cam-fd" + }, + {} +}; + +static struct platform_driver cam_fd_driver = { + .probe = cam_fd_dev_probe, + .remove = cam_fd_dev_remove, + .driver = { + .name = "cam_fd", + .owner = THIS_MODULE, + .of_match_table = cam_fd_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_fd_dev_init_module(void) +{ + return platform_driver_register(&cam_fd_driver); +} + +static void __exit cam_fd_dev_exit_module(void) +{ + platform_driver_unregister(&cam_fd_driver); +} + +module_init(cam_fd_dev_init_module); +module_exit(cam_fd_dev_exit_module); +MODULE_DESCRIPTION("MSM FD driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/Makefile b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..c4a8d7033fe3642692cb529d76bfdb9f287c8cc3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += fd_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_fd_hw_mgr.o diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c new file mode 100644 index 0000000000000000000000000000000000000000..d3110ba5ae89d02cee174c38e730e66b599054bc --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c @@ -0,0 +1,2141 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include "cam_io_util.h" +#include "cam_soc_util.h" +#include "cam_mem_mgr_api.h" +#include "cam_smmu_api.h" +#include "cam_packet_util.h" +#include "cam_fd_context.h" +#include "cam_fd_hw_intf.h" +#include "cam_fd_hw_core.h" +#include "cam_fd_hw_soc.h" +#include "cam_fd_hw_mgr_intf.h" +#include "cam_fd_hw_mgr.h" +#include "cam_trace.h" + +static struct cam_fd_hw_mgr g_fd_hw_mgr; + +static int cam_fd_mgr_util_packet_validate(struct cam_packet *packet, + size_t remain_len) +{ + struct cam_cmd_buf_desc *cmd_desc = NULL; + int i, rc; + + if (!packet) + return -EINVAL; + + CAM_DBG(CAM_FD, "Packet request=%d, op_code=0x%x, size=%d, flags=%d", + packet->header.request_id, packet->header.op_code, + packet->header.size, packet->header.flags); + CAM_DBG(CAM_FD, + "Packet cmdbuf(offset=%d, num=%d) io(offset=%d, num=%d)", + packet->cmd_buf_offset, packet->num_cmd_buf, + packet->io_configs_offset, packet->num_io_configs); + CAM_DBG(CAM_FD, + "Packet Patch(offset=%d, num=%d) kmd(offset=%d, num=%d)", + packet->patch_offset, packet->num_patches, + packet->kmd_cmd_buf_offset, packet->kmd_cmd_buf_index); + + if (cam_packet_util_validate_packet(packet, remain_len)) { + CAM_ERR(CAM_FD, "invalid packet:%d %d %d %d %d", + packet->kmd_cmd_buf_index, + packet->num_cmd_buf, packet->cmd_buf_offset, + packet->io_configs_offset, packet->header.size); + return -EINVAL; + } + + /* All buffers must come through io config, do not support patching */ + if (packet->num_patches || !packet->num_io_configs) { + CAM_ERR(CAM_FD, "wrong number of cmd/patch info: %u %u", + packet->num_cmd_buf, packet->num_patches); + return -EINVAL; + } + + /* KMD Buf index can never be greater than or equal to num cmd bufs */ + if (packet->kmd_cmd_buf_index >= packet->num_cmd_buf) { + CAM_ERR(CAM_FD, "Invalid kmd index %d (%d)", + packet->kmd_cmd_buf_index, packet->num_cmd_buf); + return -EINVAL; + } + + if ((packet->header.op_code & 0xff) != + CAM_PACKET_OPCODES_FD_FRAME_UPDATE) { + CAM_ERR(CAM_FD, "Invalid op_code %u", + packet->header.op_code & 0xff); + return -EINVAL; + } + + cmd_desc = (struct cam_cmd_buf_desc *) ((uint8_t *)&packet->payload + + packet->cmd_buf_offset); + + for (i = 0; i < packet->num_cmd_buf; i++) { + /* + * We can allow 0 length cmd buffer. This can happen in case + * umd gives an empty cmd buffer as kmd buffer + */ + if (!cmd_desc[i].length) + continue; + + if ((cmd_desc[i].meta_data != CAM_FD_CMD_BUFFER_ID_GENERIC) && + (cmd_desc[i].meta_data != CAM_FD_CMD_BUFFER_ID_CDM)) { + CAM_ERR(CAM_FD, "Invalid meta_data [%d] %u", i, + cmd_desc[i].meta_data); + return -EINVAL; + } + + CAM_DBG(CAM_FD, + "CmdBuf[%d] hdl=%d, offset=%d, size=%d, len=%d, type=%d, meta_data=%d", + i, + cmd_desc[i].mem_handle, cmd_desc[i].offset, + cmd_desc[i].size, cmd_desc[i].length, cmd_desc[i].type, + cmd_desc[i].meta_data); + + rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]); + if (rc) { + CAM_ERR(CAM_FD, "Invalid cmd buffer %d", i); + return rc; + } + } + + return 0; +} + +static int cam_fd_mgr_util_put_ctx( + struct list_head *src_list, + struct cam_fd_hw_mgr_ctx **fd_ctx) +{ + int rc = 0; + struct cam_fd_hw_mgr_ctx *ctx_ptr = NULL; + + mutex_lock(&g_fd_hw_mgr.ctx_mutex); + ctx_ptr = *fd_ctx; + if (ctx_ptr) + list_add_tail(&ctx_ptr->list, src_list); + *fd_ctx = NULL; + mutex_unlock(&g_fd_hw_mgr.ctx_mutex); + + return rc; +} + +static int cam_fd_mgr_util_get_ctx( + struct list_head *src_list, + struct cam_fd_hw_mgr_ctx **fd_ctx) +{ + int rc = 0; + struct cam_fd_hw_mgr_ctx *ctx_ptr = NULL; + + mutex_lock(&g_fd_hw_mgr.ctx_mutex); + if (!list_empty(src_list)) { + ctx_ptr = list_first_entry(src_list, + struct cam_fd_hw_mgr_ctx, list); + list_del_init(&ctx_ptr->list); + } else { + CAM_ERR(CAM_FD, "No more free fd hw mgr ctx"); + rc = -1; + } + *fd_ctx = ctx_ptr; + mutex_unlock(&g_fd_hw_mgr.ctx_mutex); + + return rc; +} + +static int cam_fd_mgr_util_put_frame_req( + struct list_head *src_list, + struct cam_fd_mgr_frame_request **frame_req) +{ + int rc = 0; + struct cam_fd_mgr_frame_request *req_ptr = NULL; + + mutex_lock(&g_fd_hw_mgr.frame_req_mutex); + req_ptr = *frame_req; + if (req_ptr) { + list_del_init(&req_ptr->list); + list_add_tail(&req_ptr->list, src_list); + } + *frame_req = NULL; + mutex_unlock(&g_fd_hw_mgr.frame_req_mutex); + + return rc; +} + +static int cam_fd_mgr_util_get_frame_req( + struct list_head *src_list, + struct cam_fd_mgr_frame_request **frame_req) +{ + int rc = 0; + struct cam_fd_mgr_frame_request *req_ptr = NULL; + + mutex_lock(&g_fd_hw_mgr.frame_req_mutex); + if (!list_empty(src_list)) { + req_ptr = list_first_entry(src_list, + struct cam_fd_mgr_frame_request, list); + list_del_init(&req_ptr->list); + } else { + CAM_DBG(CAM_FD, "Frame req not available"); + rc = -EPERM; + } + *frame_req = req_ptr; + mutex_unlock(&g_fd_hw_mgr.frame_req_mutex); + + return rc; +} + +static int cam_fd_mgr_util_get_device(struct cam_fd_hw_mgr *hw_mgr, + struct cam_fd_hw_mgr_ctx *hw_ctx, struct cam_fd_device **hw_device) +{ + if (!hw_mgr || !hw_ctx || !hw_device) { + CAM_ERR(CAM_FD, "Invalid input %pK %pK %pK", hw_mgr, hw_ctx, + hw_device); + return -EINVAL; + } + + if ((hw_ctx->device_index < 0) || + (hw_ctx->device_index >= CAM_FD_HW_MAX)) { + CAM_ERR(CAM_FD, "Invalid device indx %d", hw_ctx->device_index); + return -EINVAL; + } + + CAM_DBG(CAM_FD, "ctx_index=%u, hw_ctx=%d", hw_ctx->ctx_index, + hw_ctx->device_index); + + *hw_device = &hw_mgr->hw_device[hw_ctx->device_index]; + + return 0; +} + +static int cam_fd_mgr_util_release_device(struct cam_fd_hw_mgr *hw_mgr, + struct cam_fd_hw_mgr_ctx *hw_ctx) +{ + struct cam_fd_device *hw_device; + struct cam_fd_hw_release_args hw_release_args; + int rc; + + rc = cam_fd_mgr_util_get_device(hw_mgr, hw_ctx, &hw_device); + if (rc) { + CAM_ERR(CAM_FD, "Error in getting device %d", rc); + return rc; + } + + if (hw_device->hw_intf->hw_ops.release) { + hw_release_args.hw_ctx = hw_ctx; + hw_release_args.ctx_hw_private = hw_ctx->ctx_hw_private; + rc = hw_device->hw_intf->hw_ops.release( + hw_device->hw_intf->hw_priv, &hw_release_args, + sizeof(hw_release_args)); + if (rc) { + CAM_ERR(CAM_FD, "Failed in HW release %d", rc); + return rc; + } + } else { + CAM_ERR(CAM_FD, "Invalid release function"); + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + hw_device->num_ctxts--; + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + hw_ctx->device_index = -1; + + return rc; +} + +static int cam_fd_mgr_util_select_device(struct cam_fd_hw_mgr *hw_mgr, + struct cam_fd_hw_mgr_ctx *hw_ctx, + struct cam_fd_acquire_dev_info *fd_acquire_args) +{ + int i, rc; + struct cam_fd_hw_reserve_args hw_reserve_args; + struct cam_fd_device *hw_device = NULL; + + if (!hw_mgr || !hw_ctx || !fd_acquire_args) { + CAM_ERR(CAM_FD, "Invalid input %pK %pK %pK", hw_mgr, hw_ctx, + fd_acquire_args); + return -EINVAL; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + + /* Check if a device is free which can satisfy the requirements */ + for (i = 0; i < hw_mgr->num_devices; i++) { + hw_device = &hw_mgr->hw_device[i]; + CAM_DBG(CAM_FD, + "[%d] : num_ctxts=%d, modes=%d, raw_results=%d", + i, hw_device->num_ctxts, + hw_device->hw_caps.supported_modes, + hw_device->hw_caps.raw_results_available); + if ((hw_device->num_ctxts == 0) && + (fd_acquire_args->mode & + hw_device->hw_caps.supported_modes) && + (!fd_acquire_args->get_raw_results || + hw_device->hw_caps.raw_results_available)) { + CAM_DBG(CAM_FD, "Found dedicated HW Index=%d", i); + hw_device->num_ctxts++; + break; + } + } + + /* + * We couldn't find a free HW which meets requirement, now check if + * there is a HW which meets acquire requirements + */ + if (i == hw_mgr->num_devices) { + for (i = 0; i < hw_mgr->num_devices; i++) { + hw_device = &hw_mgr->hw_device[i]; + if ((fd_acquire_args->mode & + hw_device->hw_caps.supported_modes) && + (!fd_acquire_args->get_raw_results || + hw_device->hw_caps.raw_results_available)) { + hw_device->num_ctxts++; + CAM_DBG(CAM_FD, "Found sharing HW Index=%d", i); + break; + } + } + } + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + if ((i == hw_mgr->num_devices) || !hw_device) { + CAM_ERR(CAM_FD, "Couldn't acquire HW %d %d", + fd_acquire_args->mode, + fd_acquire_args->get_raw_results); + return -EBUSY; + } + + CAM_DBG(CAM_FD, "Device index %d selected for this acquire", i); + + /* Check if we can reserve this HW */ + if (hw_device->hw_intf->hw_ops.reserve) { + hw_reserve_args.hw_ctx = hw_ctx; + hw_reserve_args.mode = fd_acquire_args->mode; + rc = hw_device->hw_intf->hw_ops.reserve( + hw_device->hw_intf->hw_priv, &hw_reserve_args, + sizeof(hw_reserve_args)); + if (rc) { + CAM_ERR(CAM_FD, "Failed in HW reserve %d", rc); + return rc; + } + hw_ctx->ctx_hw_private = hw_reserve_args.ctx_hw_private; + } else { + CAM_ERR(CAM_FD, "Invalid reserve function"); + return -EPERM; + } + + /* Update required info in hw context */ + hw_ctx->device_index = i; + + CAM_DBG(CAM_FD, "ctx index=%u, device_index=%d", hw_ctx->ctx_index, + hw_ctx->device_index); + + return 0; +} + +static int cam_fd_mgr_util_pdev_get_hw_intf(struct device_node *of_node, + int i, struct cam_hw_intf **device_hw_intf) +{ + struct device_node *device_node = NULL; + struct platform_device *child_pdev = NULL; + struct cam_hw_intf *hw_intf = NULL; + const char *name = NULL; + int rc; + + rc = of_property_read_string_index(of_node, "compat-hw-name", i, &name); + if (rc) { + CAM_ERR(CAM_FD, "Getting dev object name failed %d %d", i, rc); + goto put_node; + } + + device_node = of_find_node_by_name(NULL, name); + if (!device_node) { + CAM_ERR(CAM_FD, "Cannot find node in dtsi %s", name); + return -ENODEV; + } + + child_pdev = of_find_device_by_node(device_node); + if (!child_pdev) { + CAM_ERR(CAM_FD, "Failed to find device on bus %s", + device_node->name); + rc = -ENODEV; + goto put_node; + } + + hw_intf = (struct cam_hw_intf *)platform_get_drvdata(child_pdev); + if (!hw_intf) { + CAM_ERR(CAM_FD, "No driver data for child device"); + rc = -ENODEV; + goto put_node; + } + + CAM_DBG(CAM_FD, "child type %d index %d child_intf %pK", + hw_intf->hw_type, hw_intf->hw_idx, hw_intf); + + if (hw_intf->hw_idx >= CAM_FD_HW_MAX) { + CAM_ERR(CAM_FD, "hw_idx invalid %d", hw_intf->hw_idx); + rc = -ENODEV; + goto put_node; + } + + rc = 0; + *device_hw_intf = hw_intf; + +put_node: + of_node_put(device_node); + + return rc; +} + +static int cam_fd_packet_generic_blob_handler(void *user_data, + uint32_t blob_type, uint32_t blob_size, uint8_t *blob_data) +{ + struct cam_fd_hw_cmd_prestart_args *prestart_args = + (struct cam_fd_hw_cmd_prestart_args *)user_data; + + if (!blob_data || (blob_size == 0)) { + CAM_ERR(CAM_FD, "Invalid blob info %pK %u", blob_data, + blob_size); + return -EINVAL; + } + + if (!prestart_args) { + CAM_ERR(CAM_FD, "Invalid user data"); + return -EINVAL; + } + + switch (blob_type) { + case CAM_FD_BLOB_TYPE_RAW_RESULTS_REQUIRED: { + uint32_t *get_raw_results = (uint32_t *)blob_data; + + if (sizeof(uint32_t) != blob_size) { + CAM_ERR(CAM_FD, "Invalid blob size %zu %u", + sizeof(uint32_t), blob_size); + return -EINVAL; + } + + prestart_args->get_raw_results = *get_raw_results; + break; + } + case CAM_FD_BLOB_TYPE_SOC_CLOCK_BW_REQUEST: { + struct cam_fd_soc_clock_bw_request *clk_req = + (struct cam_fd_soc_clock_bw_request *)blob_data; + + if (sizeof(struct cam_fd_soc_clock_bw_request) != blob_size) { + CAM_ERR(CAM_FD, "Invalid blob size %zu %u", + sizeof(struct cam_fd_soc_clock_bw_request), + blob_size); + return -EINVAL; + } + + CAM_DBG(CAM_FD, "SOC Clk Request clock=%lld, bw=%lld", + clk_req->clock_rate, clk_req->bandwidth); + + break; + } + default: + CAM_WARN(CAM_FD, "Unknown blob type %d", blob_type); + break; + } + + return 0; +} + +static int cam_fd_mgr_util_parse_generic_cmd_buffer( + struct cam_fd_hw_mgr_ctx *hw_ctx, struct cam_packet *packet, + struct cam_fd_hw_cmd_prestart_args *prestart_args) +{ + struct cam_cmd_buf_desc *cmd_desc = NULL; + int i, rc = 0; + + cmd_desc = (struct cam_cmd_buf_desc *) ((uint8_t *)&packet->payload + + packet->cmd_buf_offset); + + for (i = 0; i < packet->num_cmd_buf; i++) { + if (!cmd_desc[i].length) + continue; + + if (cmd_desc[i].meta_data == CAM_FD_CMD_BUFFER_ID_CDM) + continue; + + rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]); + if (rc) + return rc; + + rc = cam_packet_util_process_generic_cmd_buffer(&cmd_desc[i], + cam_fd_packet_generic_blob_handler, prestart_args); + if (rc) + CAM_ERR(CAM_FD, "Failed in processing blobs %d", rc); + + break; + } + + return rc; +} + +static int cam_fd_mgr_util_get_buf_map_requirement(uint32_t direction, + uint32_t resource_type, bool *need_io_map, bool *need_cpu_map) +{ + if (!need_io_map || !need_cpu_map) { + CAM_ERR(CAM_FD, "Invalid input pointers %pK %pK", need_io_map, + need_cpu_map); + return -EINVAL; + } + + if (direction == CAM_BUF_INPUT) { + switch (resource_type) { + case CAM_FD_INPUT_PORT_ID_IMAGE: + *need_io_map = true; + *need_cpu_map = false; + break; + default: + CAM_WARN(CAM_FD, "Invalid port: dir %d, id %d", + direction, resource_type); + return -EINVAL; + } + } else if (direction == CAM_BUF_OUTPUT) { + switch (resource_type) { + case CAM_FD_OUTPUT_PORT_ID_RESULTS: + *need_io_map = true; + *need_cpu_map = true; + break; + case CAM_FD_OUTPUT_PORT_ID_RAW_RESULTS: + *need_io_map = true; + *need_cpu_map = true; + break; + case CAM_FD_OUTPUT_PORT_ID_WORK_BUFFER: + *need_io_map = true; + *need_cpu_map = false; + break; + default: + CAM_WARN(CAM_FD, "Invalid port: dir %d, id %d", + direction, resource_type); + return -EINVAL; + } + } else { + CAM_WARN(CAM_FD, "Invalid direction %d", direction); + return -EINVAL; + } + + return 0; +} + +static int cam_fd_mgr_put_cpu_buf(struct cam_hw_prepare_update_args *prepare) +{ + int i, rc; + uint32_t plane; + bool need_io_map, need_cpu_map; + struct cam_buf_io_cfg *io_cfg; + + io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) + &prepare->packet->payload + prepare->packet->io_configs_offset); + + if (!io_cfg) + return -EINVAL; + + for (i = 0; i < prepare->packet->num_io_configs; i++) { + rc = cam_fd_mgr_util_get_buf_map_requirement( + io_cfg[i].direction, io_cfg[i].resource_type, + &need_io_map, &need_cpu_map); + + if (rc || !need_cpu_map) + continue; + + for (plane = 0; plane < CAM_PACKET_MAX_PLANES; plane++) + cam_mem_put_cpu_buf(io_cfg[i].mem_handle[plane]); + } + return 0; +} + +static int cam_fd_mgr_util_prepare_io_buf_info(int32_t iommu_hdl, + struct cam_hw_prepare_update_args *prepare, + struct cam_fd_hw_io_buffer *input_buf, + struct cam_fd_hw_io_buffer *output_buf, uint32_t io_buf_size) +{ + int rc = -EINVAL; + uint32_t plane, num_out_buf, num_in_buf; + int i, j; + struct cam_buf_io_cfg *io_cfg; + dma_addr_t io_addr[CAM_PACKET_MAX_PLANES]; + uintptr_t cpu_addr[CAM_PACKET_MAX_PLANES]; + size_t size; + bool need_io_map, need_cpu_map; + + /* Get IO Buf information */ + num_out_buf = 0; + num_in_buf = 0; + io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) + &prepare->packet->payload + prepare->packet->io_configs_offset); + + for (i = 0; i < prepare->packet->num_io_configs; i++) { + CAM_DBG(CAM_FD, + "IOConfig[%d] : handle[%d] Dir[%d] Res[%d] Fence[%d], Format[%d]", + i, io_cfg[i].mem_handle[0], io_cfg[i].direction, + io_cfg[i].resource_type, + io_cfg[i].fence, io_cfg[i].format); + + if ((num_in_buf >= io_buf_size) || + (num_out_buf >= io_buf_size)) { + CAM_ERR(CAM_FD, "Invalid number of buffers %d %d %d", + num_in_buf, num_out_buf, io_buf_size); + return -EINVAL; + } + + rc = cam_fd_mgr_util_get_buf_map_requirement( + io_cfg[i].direction, io_cfg[i].resource_type, + &need_io_map, &need_cpu_map); + if (rc) { + CAM_WARN(CAM_FD, "Invalid io buff [%d] : %d %d %d", + i, io_cfg[i].direction, + io_cfg[i].resource_type, rc); + continue; + } + + memset(io_addr, 0x0, sizeof(io_addr)); + for (plane = 0; plane < CAM_PACKET_MAX_PLANES; plane++) { + if (!io_cfg[i].mem_handle[plane]) + break; + + io_addr[plane] = 0x0; + cpu_addr[plane] = 0x0; + + if (need_io_map) { + rc = cam_mem_get_io_buf( + io_cfg[i].mem_handle[plane], + iommu_hdl, &io_addr[plane], &size); + if (rc) { + CAM_ERR(CAM_FD, + "Failed to get io buf %u %u %u %d", + io_cfg[i].direction, + io_cfg[i].resource_type, plane, + rc); + return -ENOMEM; + } + + if (io_cfg[i].offsets[plane] >= size) { + CAM_ERR(CAM_FD, + "Invalid io buf %u %u %u %d %u %zu", + io_cfg[i].direction, + io_cfg[i].resource_type, plane, + i, io_cfg[i].offsets[plane], + size); + return -EINVAL; + } + + io_addr[plane] += io_cfg[i].offsets[plane]; + } + + if (need_cpu_map) { + rc = cam_mem_get_cpu_buf( + io_cfg[i].mem_handle[plane], + &cpu_addr[plane], &size); + if (rc || ((io_addr[plane] & 0xFFFFFFFF) + != io_addr[plane])) { + CAM_ERR(CAM_FD, + "Invalid cpu buf %d %d %d %d", + io_cfg[i].direction, + io_cfg[i].resource_type, plane, + rc); + return rc; + } + if (io_cfg[i].offsets[plane] >= size) { + CAM_ERR(CAM_FD, + "Invalid cpu buf %d %d %d", + io_cfg[i].direction, + io_cfg[i].resource_type, plane); + cam_mem_put_cpu_buf( + io_cfg[i].mem_handle[plane]); + rc = -EINVAL; + return rc; + } + cpu_addr[plane] += io_cfg[i].offsets[plane]; + } + + CAM_DBG(CAM_FD, "IO Address[%d][%d] : %pK, %pK", + io_cfg[i].direction, plane, io_addr[plane], + cpu_addr[plane]); + } + + switch (io_cfg[i].direction) { + case CAM_BUF_INPUT: { + prepare->in_map_entries[num_in_buf].resource_handle = + io_cfg[i].resource_type; + prepare->in_map_entries[num_in_buf].sync_id = + io_cfg[i].fence; + + input_buf[num_in_buf].valid = true; + for (j = 0; j < plane; j++) { + input_buf[num_in_buf].io_addr[j] = io_addr[j]; + input_buf[num_in_buf].cpu_addr[j] = cpu_addr[j]; + } + input_buf[num_in_buf].num_buf = plane; + input_buf[num_in_buf].io_cfg = &io_cfg[i]; + + num_in_buf++; + break; + } + case CAM_BUF_OUTPUT: { + prepare->out_map_entries[num_out_buf].resource_handle = + io_cfg[i].resource_type; + prepare->out_map_entries[num_out_buf].sync_id = + io_cfg[i].fence; + + output_buf[num_out_buf].valid = true; + for (j = 0; j < plane; j++) { + output_buf[num_out_buf].io_addr[j] = io_addr[j]; + output_buf[num_out_buf].cpu_addr[j] = + cpu_addr[j]; + } + output_buf[num_out_buf].num_buf = plane; + output_buf[num_out_buf].io_cfg = &io_cfg[i]; + + num_out_buf++; + break; + } + default: + CAM_ERR(CAM_FD, "Unsupported io direction %d", + io_cfg[i].direction); + rc = -EINVAL; + break; + } + } + + prepare->num_in_map_entries = num_in_buf; + prepare->num_out_map_entries = num_out_buf; + return rc; +} + +static int cam_fd_mgr_util_prepare_hw_update_entries( + struct cam_fd_hw_mgr *hw_mgr, + struct cam_hw_prepare_update_args *prepare, + struct cam_fd_hw_cmd_prestart_args *prestart_args, + struct cam_kmd_buf_info *kmd_buf_info) +{ + int i, rc; + struct cam_hw_update_entry *hw_entry; + uint32_t num_ent; + struct cam_fd_hw_mgr_ctx *hw_ctx = + (struct cam_fd_hw_mgr_ctx *)prepare->ctxt_to_hw_map; + struct cam_fd_device *hw_device; + uint32_t kmd_buf_max_size, kmd_buf_used_bytes = 0; + uint32_t *kmd_buf_addr; + struct cam_cmd_buf_desc *cmd_desc = NULL; + + rc = cam_fd_mgr_util_get_device(hw_mgr, hw_ctx, &hw_device); + if (rc) { + CAM_ERR(CAM_FD, "Error in getting device %d", rc); + return rc; + } + + kmd_buf_addr = (uint32_t *)((uint8_t *)kmd_buf_info->cpu_addr + + kmd_buf_info->used_bytes); + kmd_buf_max_size = kmd_buf_info->size - kmd_buf_info->used_bytes; + + prestart_args->cmd_buf_addr = kmd_buf_addr; + prestart_args->size = kmd_buf_max_size; + prestart_args->pre_config_buf_size = 0; + prestart_args->post_config_buf_size = 0; + + if (hw_device->hw_intf->hw_ops.process_cmd) { + rc = hw_device->hw_intf->hw_ops.process_cmd( + hw_device->hw_intf->hw_priv, CAM_FD_HW_CMD_PRESTART, + prestart_args, + sizeof(struct cam_fd_hw_cmd_prestart_args)); + if (rc) { + CAM_ERR(CAM_FD, "Failed in CMD_PRESTART %d", rc); + return rc; + } + } + + kmd_buf_used_bytes += prestart_args->pre_config_buf_size; + kmd_buf_used_bytes += prestart_args->post_config_buf_size; + + /* HW layer is expected to add commands */ + if (!kmd_buf_used_bytes || (kmd_buf_used_bytes > kmd_buf_max_size)) { + CAM_ERR(CAM_FD, "Invalid kmd used bytes %d (%d)", + kmd_buf_used_bytes, kmd_buf_max_size); + return -ENOMEM; + } + + hw_entry = prepare->hw_update_entries; + num_ent = 0; + + if (prestart_args->pre_config_buf_size) { + if ((num_ent + 1) >= prepare->max_hw_update_entries) { + CAM_ERR(CAM_FD, "Insufficient HW entries :%d %d", + num_ent, prepare->max_hw_update_entries); + return -EINVAL; + } + + hw_entry[num_ent].handle = kmd_buf_info->handle; + hw_entry[num_ent].len = prestart_args->pre_config_buf_size; + hw_entry[num_ent].offset = kmd_buf_info->offset; + + kmd_buf_info->used_bytes += prestart_args->pre_config_buf_size; + kmd_buf_info->offset += prestart_args->pre_config_buf_size; + num_ent++; + } + + /* + * set the cmd_desc to point the first command descriptor in the + * packet and update hw entries with CDM command buffers + */ + cmd_desc = (struct cam_cmd_buf_desc *)((uint8_t *) + &prepare->packet->payload + prepare->packet->cmd_buf_offset); + + for (i = 0; i < prepare->packet->num_cmd_buf; i++) { + if (!cmd_desc[i].length) + continue; + + if (cmd_desc[i].meta_data != CAM_FD_CMD_BUFFER_ID_CDM) + continue; + + if (num_ent + 1 >= prepare->max_hw_update_entries) { + CAM_ERR(CAM_FD, "Insufficient HW entries :%d %d", + num_ent, prepare->max_hw_update_entries); + return -EINVAL; + } + + hw_entry[num_ent].handle = cmd_desc[i].mem_handle; + hw_entry[num_ent].len = cmd_desc[i].length; + hw_entry[num_ent].offset = cmd_desc[i].offset; + num_ent++; + } + + if (prestart_args->post_config_buf_size) { + if (num_ent + 1 >= prepare->max_hw_update_entries) { + CAM_ERR(CAM_FD, "Insufficient HW entries :%d %d", + num_ent, prepare->max_hw_update_entries); + return -EINVAL; + } + + hw_entry[num_ent].handle = kmd_buf_info->handle; + hw_entry[num_ent].len = prestart_args->post_config_buf_size; + hw_entry[num_ent].offset = kmd_buf_info->offset; + + kmd_buf_info->used_bytes += prestart_args->post_config_buf_size; + kmd_buf_info->offset += prestart_args->post_config_buf_size; + + num_ent++; + } + + prepare->num_hw_update_entries = num_ent; + + CAM_DBG(CAM_FD, "FinalConfig : hw_entries=%d, Sync(in=%d, out=%d)", + prepare->num_hw_update_entries, prepare->num_in_map_entries, + prepare->num_out_map_entries); + + return rc; +} + +static int cam_fd_mgr_util_submit_frame(void *priv, void *data) +{ + struct cam_fd_device *hw_device; + struct cam_fd_hw_mgr *hw_mgr; + struct cam_fd_mgr_frame_request *frame_req; + struct cam_fd_hw_mgr_ctx *hw_ctx; + struct cam_fd_hw_cmd_start_args start_args; + int rc; + + if (!priv) { + CAM_ERR(CAM_FD, "Invalid data"); + return -EINVAL; + } + + hw_mgr = (struct cam_fd_hw_mgr *)priv; + mutex_lock(&hw_mgr->frame_req_mutex); + + /* Check if we have any frames pending in high priority list */ + if (!list_empty(&hw_mgr->frame_pending_list_high)) { + CAM_DBG(CAM_FD, "Pending frames in high priority list"); + frame_req = list_first_entry(&hw_mgr->frame_pending_list_high, + struct cam_fd_mgr_frame_request, list); + } else if (!list_empty(&hw_mgr->frame_pending_list_normal)) { + CAM_DBG(CAM_FD, "Pending frames in normal priority list"); + frame_req = list_first_entry(&hw_mgr->frame_pending_list_normal, + struct cam_fd_mgr_frame_request, list); + } else { + mutex_unlock(&hw_mgr->frame_req_mutex); + CAM_DBG(CAM_FD, "No pending frames"); + return 0; + } + + CAM_DBG(CAM_FD, "FrameSubmit : Frame[%lld]", frame_req->request_id); + hw_ctx = frame_req->hw_ctx; + rc = cam_fd_mgr_util_get_device(hw_mgr, hw_ctx, &hw_device); + if (rc) { + mutex_unlock(&hw_mgr->frame_req_mutex); + CAM_ERR(CAM_FD, "Error in getting device %d", rc); + return rc; + } + + mutex_lock(&hw_device->lock); + if (hw_device->ready_to_process == false) { + mutex_unlock(&hw_device->lock); + mutex_unlock(&hw_mgr->frame_req_mutex); + return -EBUSY; + } + + trace_cam_submit_to_hw("FD", frame_req->request_id); + + list_del_init(&frame_req->list); + mutex_unlock(&hw_mgr->frame_req_mutex); + + if (hw_device->hw_intf->hw_ops.start) { + start_args.hw_ctx = hw_ctx; + start_args.ctx_hw_private = hw_ctx->ctx_hw_private; + start_args.hw_req_private = &frame_req->hw_req_private; + start_args.hw_update_entries = frame_req->hw_update_entries; + start_args.num_hw_update_entries = + frame_req->num_hw_update_entries; + + rc = hw_device->hw_intf->hw_ops.start( + hw_device->hw_intf->hw_priv, &start_args, + sizeof(start_args)); + if (rc) { + CAM_ERR(CAM_FD, "Failed in HW Start %d", rc); + mutex_unlock(&hw_device->lock); + goto put_req_into_free_list; + } + } else { + CAM_ERR(CAM_FD, "Invalid hw_ops.start"); + mutex_unlock(&hw_device->lock); + rc = -EPERM; + goto put_req_into_free_list; + } + + hw_device->ready_to_process = false; + hw_device->cur_hw_ctx = hw_ctx; + hw_device->req_id = frame_req->request_id; + mutex_unlock(&hw_device->lock); + frame_req->submit_timestamp = ktime_get(); + + rc = cam_fd_mgr_util_put_frame_req( + &hw_mgr->frame_processing_list, &frame_req); + if (rc) { + CAM_ERR(CAM_FD, + "Failed in putting frame req in processing list"); + goto stop_unlock; + } + + return rc; + +stop_unlock: + if (hw_device->hw_intf->hw_ops.stop) { + struct cam_fd_hw_stop_args stop_args; + + stop_args.hw_ctx = hw_ctx; + stop_args.ctx_hw_private = hw_ctx->ctx_hw_private; + stop_args.hw_req_private = &frame_req->hw_req_private; + if (hw_device->hw_intf->hw_ops.stop( + hw_device->hw_intf->hw_priv, &stop_args, + sizeof(stop_args))) + CAM_ERR(CAM_FD, "Failed in HW Stop %d", rc); + } +put_req_into_free_list: + cam_fd_mgr_util_put_frame_req(&hw_mgr->frame_free_list, &frame_req); + + return rc; +} + +static int cam_fd_mgr_util_schedule_frame_worker_task( + struct cam_fd_hw_mgr *hw_mgr) +{ + int32_t rc = 0; + struct crm_workq_task *task; + struct cam_fd_mgr_work_data *work_data; + + task = cam_req_mgr_workq_get_task(hw_mgr->work); + if (!task) { + CAM_ERR(CAM_FD, "no empty task available"); + return -ENOMEM; + } + + work_data = (struct cam_fd_mgr_work_data *)task->payload; + work_data->type = CAM_FD_WORK_FRAME; + + task->process_cb = cam_fd_mgr_util_submit_frame; + rc = cam_req_mgr_workq_enqueue_task(task, hw_mgr, CRM_TASK_PRIORITY_0); + + return rc; +} + +static int32_t cam_fd_mgr_workq_irq_cb(void *priv, void *data) +{ + struct cam_fd_device *hw_device = NULL; + struct cam_fd_hw_mgr *hw_mgr; + struct cam_fd_mgr_work_data *work_data; + struct cam_fd_mgr_frame_request *frame_req = NULL; + enum cam_fd_hw_irq_type irq_type; + bool frame_abort = true; + int rc; + + if (!data || !priv) { + CAM_ERR(CAM_FD, "Invalid data %pK %pK", data, priv); + return -EINVAL; + } + + hw_mgr = (struct cam_fd_hw_mgr *)priv; + work_data = (struct cam_fd_mgr_work_data *)data; + irq_type = work_data->irq_type; + + CAM_DBG(CAM_FD, "FD IRQ type=%d", irq_type); + + if (irq_type == CAM_FD_IRQ_HALT_DONE) { + /* HALT would be followed by a RESET, ignore this */ + CAM_DBG(CAM_FD, "HALT IRQ callback"); + return 0; + } + + /* Get the frame from processing list */ + rc = cam_fd_mgr_util_get_frame_req(&hw_mgr->frame_processing_list, + &frame_req); + if (rc || !frame_req) { + /* + * This can happen if reset is triggered while no frames + * were pending, so not an error, just continue to check if + * there are any pending frames and submit + */ + CAM_DBG(CAM_FD, "No Frame in processing list, rc=%d", rc); + goto submit_next_frame; + } + + if (!frame_req->hw_ctx) { + CAM_ERR(CAM_FD, "Invalid Frame request %lld", + frame_req->request_id); + goto put_req_in_free_list; + } + + rc = cam_fd_mgr_util_get_device(hw_mgr, frame_req->hw_ctx, &hw_device); + if (rc) { + CAM_ERR(CAM_FD, "Error in getting device %d", rc); + goto put_req_in_free_list; + } + + /* Read frame results first */ + if (irq_type == CAM_FD_IRQ_FRAME_DONE) { + struct cam_fd_hw_frame_done_args frame_done_args; + + CAM_DBG(CAM_FD, "FrameDone : Frame[%lld]", + frame_req->request_id); + + frame_done_args.hw_ctx = frame_req->hw_ctx; + frame_done_args.ctx_hw_private = + frame_req->hw_ctx->ctx_hw_private; + frame_done_args.request_id = frame_req->request_id; + frame_done_args.hw_req_private = &frame_req->hw_req_private; + + if (hw_device->hw_intf->hw_ops.process_cmd) { + rc = hw_device->hw_intf->hw_ops.process_cmd( + hw_device->hw_intf->hw_priv, + CAM_FD_HW_CMD_FRAME_DONE, + &frame_done_args, sizeof(frame_done_args)); + if (rc) { + CAM_ERR(CAM_FD, "Failed in CMD_PRESTART %d", + rc); + frame_abort = true; + goto notify_context; + } + } + + frame_abort = false; + } + + trace_cam_irq_handled("FD", irq_type); + +notify_context: + /* Do a callback to inform frame done or stop done */ + if (frame_req->hw_ctx->event_cb) { + struct cam_hw_done_event_data buf_data; + + CAM_DBG(CAM_FD, "FrameHALT : Frame[%lld]", + frame_req->request_id); + + buf_data.num_handles = frame_req->num_hw_update_entries; + buf_data.request_id = frame_req->request_id; + + rc = frame_req->hw_ctx->event_cb(frame_req->hw_ctx->cb_priv, + frame_abort, &buf_data); + if (rc) + CAM_ERR(CAM_FD, "Error in event cb handling %d", rc); + } + + /* + * Now we can set hw device is free to process further frames. + * Note - Do not change state to IDLE until we read the frame results, + * Otherwise, other thread may schedule frame processing before + * reading current frame's results. Also, we need to set to IDLE state + * in case some error happens after getting this irq callback + */ + mutex_lock(&hw_device->lock); + hw_device->ready_to_process = true; + hw_device->req_id = -1; + hw_device->cur_hw_ctx = NULL; + CAM_DBG(CAM_FD, "ready_to_process=%d", hw_device->ready_to_process); + mutex_unlock(&hw_device->lock); + +put_req_in_free_list: + rc = cam_fd_mgr_util_put_frame_req(&hw_mgr->frame_free_list, + &frame_req); + if (rc) { + CAM_ERR(CAM_FD, "Failed in putting frame req in free list"); + /* continue */ + } + +submit_next_frame: + /* Check if there are any frames pending for processing and submit */ + rc = cam_fd_mgr_util_submit_frame(hw_mgr, NULL); + if (rc) { + CAM_ERR(CAM_FD, "Error while submit frame, rc=%d", rc); + return rc; + } + + return rc; +} + +static int cam_fd_mgr_irq_cb(void *data, enum cam_fd_hw_irq_type irq_type) +{ + struct cam_fd_hw_mgr *hw_mgr = &g_fd_hw_mgr; + int rc = 0; + unsigned long flags; + struct crm_workq_task *task; + struct cam_fd_mgr_work_data *work_data; + + spin_lock_irqsave(&hw_mgr->hw_mgr_slock, flags); + task = cam_req_mgr_workq_get_task(hw_mgr->work); + if (!task) { + CAM_ERR(CAM_FD, "no empty task available"); + spin_unlock_irqrestore(&hw_mgr->hw_mgr_slock, flags); + return -ENOMEM; + } + + work_data = (struct cam_fd_mgr_work_data *)task->payload; + work_data->type = CAM_FD_WORK_IRQ; + work_data->irq_type = irq_type; + + task->process_cb = cam_fd_mgr_workq_irq_cb; + rc = cam_req_mgr_workq_enqueue_task(task, hw_mgr, CRM_TASK_PRIORITY_0); + if (rc) + CAM_ERR(CAM_FD, "Failed in enqueue work task, rc=%d", rc); + + spin_unlock_irqrestore(&hw_mgr->hw_mgr_slock, flags); + + return rc; +} + +static int cam_fd_mgr_hw_get_caps(void *hw_mgr_priv, void *hw_get_caps_args) +{ + int rc = 0; + struct cam_fd_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_query_cap_cmd *query = hw_get_caps_args; + struct cam_fd_query_cap_cmd query_fd; + void __user *caps_handle = + u64_to_user_ptr(query->caps_handle); + + if (copy_from_user(&query_fd, caps_handle, + sizeof(struct cam_fd_query_cap_cmd))) { + CAM_ERR(CAM_FD, "Failed in copy from user, rc=%d", rc); + return -EFAULT; + } + + query_fd = hw_mgr->fd_caps; + + CAM_DBG(CAM_FD, + "IOMMU device(%d, %d), CDM(%d, %d), versions %d.%d, %d.%d", + query_fd.device_iommu.secure, query_fd.device_iommu.non_secure, + query_fd.cdm_iommu.secure, query_fd.cdm_iommu.non_secure, + query_fd.hw_caps.core_version.major, + query_fd.hw_caps.core_version.minor, + query_fd.hw_caps.wrapper_version.major, + query_fd.hw_caps.wrapper_version.minor); + + if (copy_to_user(caps_handle, &query_fd, + sizeof(struct cam_fd_query_cap_cmd))) + rc = -EFAULT; + + return rc; +} + +static int cam_fd_mgr_hw_acquire(void *hw_mgr_priv, void *hw_acquire_args) +{ + struct cam_fd_hw_mgr *hw_mgr = (struct cam_fd_hw_mgr *)hw_mgr_priv; + struct cam_hw_acquire_args *acquire_args = + (struct cam_hw_acquire_args *)hw_acquire_args; + struct cam_fd_hw_mgr_ctx *hw_ctx; + struct cam_fd_acquire_dev_info fd_acquire_args; + int rc; + + if (!acquire_args || acquire_args->num_acq <= 0) { + CAM_ERR(CAM_FD, "Invalid acquire args %pK", acquire_args); + return -EINVAL; + } + + if (copy_from_user(&fd_acquire_args, + (void __user *)acquire_args->acquire_info, + sizeof(struct cam_fd_acquire_dev_info))) { + CAM_ERR(CAM_FD, "Copy from user failed"); + return -EFAULT; + } + + CAM_DBG(CAM_FD, "Acquire : mode=%d, get_raw_results=%d, priority=%d", + fd_acquire_args.mode, fd_acquire_args.get_raw_results, + fd_acquire_args.priority); + + /* get a free fd hw mgr ctx */ + rc = cam_fd_mgr_util_get_ctx(&hw_mgr->free_ctx_list, &hw_ctx); + if (rc || !hw_ctx) { + CAM_ERR(CAM_FD, "Get hw context failed, rc=%d, hw_ctx=%pK", + rc, hw_ctx); + return -EINVAL; + } + + if (fd_acquire_args.get_raw_results && !hw_mgr->raw_results_available) { + CAM_ERR(CAM_FD, "HW cannot support raw results %d (%d)", + fd_acquire_args.get_raw_results, + hw_mgr->raw_results_available); + goto put_ctx; + } + + if (!(fd_acquire_args.mode & hw_mgr->supported_modes)) { + CAM_ERR(CAM_FD, "HW cannot support requested mode 0x%x (0x%x)", + fd_acquire_args.mode, hw_mgr->supported_modes); + rc = -EPERM; + goto put_ctx; + } + + rc = cam_fd_mgr_util_select_device(hw_mgr, hw_ctx, &fd_acquire_args); + if (rc) { + CAM_ERR(CAM_FD, "Failed in selecting device, rc=%d", rc); + goto put_ctx; + } + + hw_ctx->ctx_in_use = true; + hw_ctx->hw_mgr = hw_mgr; + hw_ctx->get_raw_results = fd_acquire_args.get_raw_results; + hw_ctx->mode = fd_acquire_args.mode; + + /* Save incoming cam core info into hw ctx*/ + hw_ctx->cb_priv = acquire_args->context_data; + hw_ctx->event_cb = acquire_args->event_cb; + + /* Update out args */ + acquire_args->ctxt_to_hw_map = hw_ctx; + + cam_fd_mgr_util_put_ctx(&hw_mgr->used_ctx_list, &hw_ctx); + + return 0; +put_ctx: + list_del_init(&hw_ctx->list); + cam_fd_mgr_util_put_ctx(&hw_mgr->free_ctx_list, &hw_ctx); + return rc; +} + +static int cam_fd_mgr_hw_release(void *hw_mgr_priv, void *hw_release_args) +{ + struct cam_fd_hw_mgr *hw_mgr = (struct cam_fd_hw_mgr *)hw_mgr_priv; + struct cam_hw_release_args *release_args = hw_release_args; + struct cam_fd_hw_mgr_ctx *hw_ctx; + int rc; + + if (!hw_mgr_priv || !hw_release_args) { + CAM_ERR(CAM_FD, "Invalid arguments %pK, %pK", + hw_mgr_priv, hw_release_args); + return -EINVAL; + } + + hw_ctx = (struct cam_fd_hw_mgr_ctx *)release_args->ctxt_to_hw_map; + if (!hw_ctx || !hw_ctx->ctx_in_use) { + CAM_ERR(CAM_FD, "Invalid context is used, hw_ctx=%pK", hw_ctx); + return -EPERM; + } + + rc = cam_fd_mgr_util_release_device(hw_mgr, hw_ctx); + if (rc) + CAM_ERR(CAM_FD, "Failed in release device, rc=%d", rc); + + hw_ctx->ctx_in_use = false; + list_del_init(&hw_ctx->list); + cam_fd_mgr_util_put_ctx(&hw_mgr->free_ctx_list, &hw_ctx); + + return 0; +} + +static int cam_fd_mgr_hw_start(void *hw_mgr_priv, void *mgr_start_args) +{ + int rc = 0; + struct cam_fd_hw_mgr *hw_mgr = (struct cam_fd_hw_mgr *)hw_mgr_priv; + struct cam_hw_start_args *hw_mgr_start_args = + (struct cam_hw_start_args *)mgr_start_args; + struct cam_fd_hw_mgr_ctx *hw_ctx; + struct cam_fd_device *hw_device; + struct cam_fd_hw_init_args hw_init_args; + struct cam_hw_info *fd_hw; + struct cam_fd_core *fd_core; + + if (!hw_mgr_priv || !hw_mgr_start_args) { + CAM_ERR(CAM_FD, "Invalid arguments %pK %pK", + hw_mgr_priv, hw_mgr_start_args); + return -EINVAL; + } + + hw_ctx = (struct cam_fd_hw_mgr_ctx *)hw_mgr_start_args->ctxt_to_hw_map; + if (!hw_ctx || !hw_ctx->ctx_in_use) { + CAM_ERR(CAM_FD, "Invalid context is used, hw_ctx=%pK", hw_ctx); + return -EPERM; + } + + CAM_DBG(CAM_FD, "ctx index=%u, device_index=%d", hw_ctx->ctx_index, + hw_ctx->device_index); + + rc = cam_fd_mgr_util_get_device(hw_mgr, hw_ctx, &hw_device); + if (rc) { + CAM_ERR(CAM_FD, "Error in getting device %d", rc); + return rc; + } + + fd_hw = (struct cam_hw_info *)hw_device->hw_intf->hw_priv; + fd_core = (struct cam_fd_core *)fd_hw->core_info; + + if (hw_device->hw_intf->hw_ops.init) { + hw_init_args.hw_ctx = hw_ctx; + hw_init_args.ctx_hw_private = hw_ctx->ctx_hw_private; + if (fd_core->hw_static_info->enable_errata_wa.skip_reset) + hw_init_args.reset_required = false; + else + hw_init_args.reset_required = true; + + rc = hw_device->hw_intf->hw_ops.init( + hw_device->hw_intf->hw_priv, &hw_init_args, + sizeof(hw_init_args)); + if (rc) { + CAM_ERR(CAM_FD, "Failed in HW Init %d", rc); + return rc; + } + } else { + CAM_ERR(CAM_FD, "Invalid init function"); + return -EINVAL; + } + + return rc; +} + +static int cam_fd_mgr_hw_flush_req(void *hw_mgr_priv, + struct cam_hw_flush_args *flush_args) +{ + int rc = 0; + struct cam_fd_mgr_frame_request *frame_req, *req_temp, *flush_req; + struct cam_fd_hw_mgr *hw_mgr = (struct cam_fd_hw_mgr *)hw_mgr_priv; + struct cam_fd_device *hw_device; + struct cam_fd_hw_stop_args hw_stop_args; + struct cam_fd_hw_mgr_ctx *hw_ctx; + uint32_t i = 0; + + hw_ctx = (struct cam_fd_hw_mgr_ctx *)flush_args->ctxt_to_hw_map; + + if (!hw_ctx || !hw_ctx->ctx_in_use) { + CAM_ERR(CAM_FD, "Invalid context is used, hw_ctx=%pK", hw_ctx); + return -EPERM; + } + CAM_DBG(CAM_FD, "ctx index=%u, hw_ctx=%d", hw_ctx->ctx_index, + hw_ctx->device_index); + + rc = cam_fd_mgr_util_get_device(hw_mgr, hw_ctx, &hw_device); + if (rc) { + CAM_ERR(CAM_FD, "Error in getting device %d", rc); + return rc; + } + + mutex_lock(&hw_mgr->frame_req_mutex); + for (i = 0; i < flush_args->num_req_active; i++) { + flush_req = (struct cam_fd_mgr_frame_request *) + flush_args->flush_req_active[i]; + + list_for_each_entry_safe(frame_req, req_temp, + &hw_mgr->frame_pending_list_high, list) { + if (frame_req->hw_ctx != hw_ctx) + continue; + + if (frame_req->request_id != flush_req->request_id) + continue; + + list_del_init(&frame_req->list); + break; + } + + list_for_each_entry_safe(frame_req, req_temp, + &hw_mgr->frame_pending_list_normal, list) { + if (frame_req->hw_ctx != hw_ctx) + continue; + + if (frame_req->request_id != flush_req->request_id) + continue; + + list_del_init(&frame_req->list); + break; + } + + list_for_each_entry_safe(frame_req, req_temp, + &hw_mgr->frame_processing_list, list) { + if (frame_req->hw_ctx != hw_ctx) + continue; + + if (frame_req->request_id != flush_req->request_id) + continue; + + list_del_init(&frame_req->list); + + mutex_lock(&hw_device->lock); + if ((hw_device->ready_to_process == true) || + (hw_device->cur_hw_ctx != hw_ctx)) + goto unlock_dev_flush_req; + + if (hw_device->hw_intf->hw_ops.stop) { + hw_stop_args.hw_ctx = hw_ctx; + rc = hw_device->hw_intf->hw_ops.stop( + hw_device->hw_intf->hw_priv, + &hw_stop_args, + sizeof(hw_stop_args)); + if (rc) { + CAM_ERR(CAM_FD, + "Failed in HW Stop %d", rc); + goto unlock_dev_flush_req; + } + hw_device->ready_to_process = true; + } + +unlock_dev_flush_req: + mutex_unlock(&hw_device->lock); + break; + } + } + mutex_unlock(&hw_mgr->frame_req_mutex); + + for (i = 0; i < flush_args->num_req_pending; i++) { + flush_req = (struct cam_fd_mgr_frame_request *) + flush_args->flush_req_pending[i]; + cam_fd_mgr_util_put_frame_req(&hw_mgr->frame_free_list, + &flush_req); + } + + return rc; +} + +static int cam_fd_mgr_hw_flush_ctx(void *hw_mgr_priv, + struct cam_hw_flush_args *flush_args) +{ + int rc = 0; + struct cam_fd_mgr_frame_request *frame_req, *req_temp, *flush_req; + struct cam_fd_hw_mgr *hw_mgr = (struct cam_fd_hw_mgr *)hw_mgr_priv; + struct cam_fd_device *hw_device; + struct cam_fd_hw_stop_args hw_stop_args; + struct cam_fd_hw_mgr_ctx *hw_ctx; + uint32_t i = 0; + + hw_ctx = (struct cam_fd_hw_mgr_ctx *)flush_args->ctxt_to_hw_map; + + if (!hw_ctx || !hw_ctx->ctx_in_use) { + CAM_ERR(CAM_FD, "Invalid context is used, hw_ctx=%pK", hw_ctx); + return -EPERM; + } + CAM_DBG(CAM_FD, "ctx index=%u, hw_ctx=%d", hw_ctx->ctx_index, + hw_ctx->device_index); + + rc = cam_fd_mgr_util_get_device(hw_mgr, hw_ctx, &hw_device); + if (rc) { + CAM_ERR(CAM_FD, "Error in getting device %d", rc); + return rc; + } + + mutex_lock(&hw_mgr->frame_req_mutex); + list_for_each_entry_safe(frame_req, req_temp, + &hw_mgr->frame_pending_list_high, list) { + if (frame_req->hw_ctx != hw_ctx) + continue; + + list_del_init(&frame_req->list); + } + + list_for_each_entry_safe(frame_req, req_temp, + &hw_mgr->frame_pending_list_normal, list) { + if (frame_req->hw_ctx != hw_ctx) + continue; + + list_del_init(&frame_req->list); + } + + list_for_each_entry_safe(frame_req, req_temp, + &hw_mgr->frame_processing_list, list) { + if (frame_req->hw_ctx != hw_ctx) + continue; + + list_del_init(&frame_req->list); + mutex_lock(&hw_device->lock); + if ((hw_device->ready_to_process == true) || + (hw_device->cur_hw_ctx != hw_ctx)) + goto unlock_dev_flush_ctx; + + if (hw_device->hw_intf->hw_ops.stop) { + hw_stop_args.hw_ctx = hw_ctx; + rc = hw_device->hw_intf->hw_ops.stop( + hw_device->hw_intf->hw_priv, &hw_stop_args, + sizeof(hw_stop_args)); + if (rc) { + CAM_ERR(CAM_FD, "Failed in HW Stop %d", rc); + goto unlock_dev_flush_ctx; + } + hw_device->ready_to_process = true; + } + +unlock_dev_flush_ctx: + mutex_unlock(&hw_device->lock); + } + mutex_unlock(&hw_mgr->frame_req_mutex); + + for (i = 0; i < flush_args->num_req_pending; i++) { + flush_req = (struct cam_fd_mgr_frame_request *) + flush_args->flush_req_pending[i]; + CAM_DBG(CAM_FD, "flush pending req %llu", + flush_req->request_id); + cam_fd_mgr_util_put_frame_req(&hw_mgr->frame_free_list, + &flush_req); + } + + for (i = 0; i < flush_args->num_req_active; i++) { + flush_req = (struct cam_fd_mgr_frame_request *) + flush_args->flush_req_active[i]; + CAM_DBG(CAM_FD, "flush active req %llu", flush_req->request_id); + cam_fd_mgr_util_put_frame_req(&hw_mgr->frame_free_list, + &flush_req); + } + + return rc; +} + +static int cam_fd_mgr_hw_flush(void *hw_mgr_priv, + void *hw_flush_args) +{ + int rc = 0; + struct cam_hw_flush_args *flush_args = + (struct cam_hw_flush_args *)hw_flush_args; + + if (!hw_mgr_priv || !hw_flush_args) { + CAM_ERR(CAM_FD, "Invalid arguments %pK %pK", + hw_mgr_priv, hw_flush_args); + return -EINVAL; + } + + switch (flush_args->flush_type) { + case CAM_FLUSH_TYPE_REQ: + rc = cam_fd_mgr_hw_flush_req(hw_mgr_priv, flush_args); + break; + case CAM_FLUSH_TYPE_ALL: + rc = cam_fd_mgr_hw_flush_ctx(hw_mgr_priv, flush_args); + break; + default: + rc = -EINVAL; + CAM_ERR(CAM_FD, "Invalid flush type %d", + flush_args->flush_type); + break; + } + return rc; +} + +static int cam_fd_mgr_hw_dump( + void *hw_mgr_priv, + void *hw_dump_args) +{ + int rc; + uint8_t *dst; + ktime_t cur_time; + size_t remain_len; + uint32_t min_len; + uint64_t diff; + uint64_t *addr, *start; + struct timespec64 cur_ts; + struct timespec64 req_ts; + struct cam_fd_hw_mgr *hw_mgr; + struct cam_hw_dump_args *dump_args; + struct cam_fd_hw_mgr_ctx *hw_ctx; + struct cam_fd_device *hw_device; + struct cam_fd_hw_dump_args fd_dump_args; + struct cam_fd_hw_dump_header *hdr; + struct cam_fd_mgr_frame_request *frame_req, *req_temp; + + hw_mgr = (struct cam_fd_hw_mgr *)hw_mgr_priv; + dump_args = (struct cam_hw_dump_args *)hw_dump_args; + if (!hw_mgr || !dump_args) { + CAM_ERR(CAM_FD, "Invalid args %pK %pK", + hw_mgr, dump_args); + return -EINVAL; + } + + hw_ctx = (struct cam_fd_hw_mgr_ctx *)dump_args->ctxt_to_hw_map; + + if (!hw_ctx) { + CAM_ERR(CAM_FD, "Invalid ctx"); + return -EINVAL; + } + + rc = cam_fd_mgr_util_get_device(hw_mgr, hw_ctx, &hw_device); + + if (rc) { + CAM_ERR(CAM_FD, "Error in getting device %d", rc); + return rc; + } + + list_for_each_entry_safe(frame_req, req_temp, + &hw_mgr->frame_processing_list, list) { + if (frame_req->request_id == dump_args->request_id) + goto hw_dump; + } + + CAM_DBG(CAM_FD, "fd dump cannot find req %llu", + dump_args->request_id); + return rc; +hw_dump: + cur_time = ktime_get(); + diff = ktime_us_delta(frame_req->submit_timestamp, cur_time); + cur_ts = ktime_to_timespec64(cur_time); + req_ts = ktime_to_timespec64(frame_req->submit_timestamp); + if (diff < CAM_FD_RESPONSE_TIME_THRESHOLD) { + CAM_INFO(CAM_FD, "No Error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + return 0; + } + CAM_INFO(CAM_FD, "Error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &fd_dump_args.cpu_addr, &fd_dump_args.buf_len); + if (rc) { + CAM_ERR(CAM_FD, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + return rc; + } + if (fd_dump_args.buf_len <= dump_args->offset) { + CAM_WARN(CAM_FD, "dump offset overshoot len %zu offset %zu", + fd_dump_args.buf_len, dump_args->offset); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return -ENOSPC; + } + remain_len = fd_dump_args.buf_len - dump_args->offset; + min_len = sizeof(struct cam_fd_hw_dump_header) + + (CAM_FD_HW_DUMP_NUM_WORDS * sizeof(uint64_t)); + + if (remain_len < min_len) { + CAM_WARN(CAM_FD, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return -ENOSPC; + } + + dst = (uint8_t *)fd_dump_args.cpu_addr + dump_args->offset; + hdr = (struct cam_fd_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_FD_HW_DUMP_TAG_MAX_LEN, + "FD_REQ:"); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + sizeof(struct cam_fd_hw_dump_header)); + start = addr; + *addr++ = frame_req->request_id; + *addr++ = req_ts.tv_sec; + *addr++ = req_ts.tv_nsec/NSEC_PER_USEC; + *addr++ = cur_ts.tv_sec; + *addr++ = cur_ts.tv_nsec/NSEC_PER_USEC; + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_fd_hw_dump_header); + + fd_dump_args.request_id = dump_args->request_id; + fd_dump_args.offset = dump_args->offset; + if (hw_device->hw_intf->hw_ops.process_cmd) { + rc = hw_device->hw_intf->hw_ops.process_cmd( + hw_device->hw_intf->hw_priv, + CAM_FD_HW_CMD_HW_DUMP, + &fd_dump_args, + sizeof(struct + cam_fd_hw_dump_args)); + if (rc) { + CAM_ERR(CAM_FD, "Hw Dump cmd fails req %lld rc %d", + frame_req->request_id, rc); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return rc; + } + } + CAM_DBG(CAM_FD, "Offset before %zu after %zu", + dump_args->offset, fd_dump_args.offset); + dump_args->offset = fd_dump_args.offset; + cam_mem_put_cpu_buf(dump_args->buf_handle); + return rc; +} + +static int cam_fd_mgr_hw_stop(void *hw_mgr_priv, void *mgr_stop_args) +{ + struct cam_fd_hw_mgr *hw_mgr = (struct cam_fd_hw_mgr *)hw_mgr_priv; + struct cam_hw_stop_args *hw_mgr_stop_args = + (struct cam_hw_stop_args *)mgr_stop_args; + struct cam_fd_hw_mgr_ctx *hw_ctx; + struct cam_fd_device *hw_device; + struct cam_fd_hw_deinit_args hw_deinit_args; + int rc = 0; + + if (!hw_mgr_priv || !hw_mgr_stop_args) { + CAM_ERR(CAM_FD, "Invalid arguments %pK %pK", + hw_mgr_priv, hw_mgr_stop_args); + return -EINVAL; + } + + hw_ctx = (struct cam_fd_hw_mgr_ctx *)hw_mgr_stop_args->ctxt_to_hw_map; + if (!hw_ctx || !hw_ctx->ctx_in_use) { + CAM_ERR(CAM_FD, "Invalid context is used, hw_ctx=%pK", hw_ctx); + return -EPERM; + } + CAM_DBG(CAM_FD, "ctx index=%u, hw_ctx=%d", hw_ctx->ctx_index, + hw_ctx->device_index); + + rc = cam_fd_mgr_util_get_device(hw_mgr, hw_ctx, &hw_device); + if (rc) { + CAM_ERR(CAM_FD, "Error in getting device %d", rc); + return rc; + } + + CAM_DBG(CAM_FD, "FD Device ready_to_process = %d", + hw_device->ready_to_process); + + if (hw_device->hw_intf->hw_ops.deinit) { + hw_deinit_args.hw_ctx = hw_ctx; + hw_deinit_args.ctx_hw_private = hw_ctx->ctx_hw_private; + rc = hw_device->hw_intf->hw_ops.deinit( + hw_device->hw_intf->hw_priv, &hw_deinit_args, + sizeof(hw_deinit_args)); + if (rc) { + CAM_ERR(CAM_FD, "Failed in HW DeInit %d", rc); + return rc; + } + } + + return rc; +} + +static int cam_fd_mgr_hw_prepare_update(void *hw_mgr_priv, + void *hw_prepare_update_args) +{ + struct cam_fd_hw_mgr *hw_mgr = (struct cam_fd_hw_mgr *)hw_mgr_priv; + struct cam_hw_prepare_update_args *prepare = + (struct cam_hw_prepare_update_args *) hw_prepare_update_args; + struct cam_fd_hw_mgr_ctx *hw_ctx; + struct cam_fd_device *hw_device; + struct cam_kmd_buf_info kmd_buf; + int rc; + struct cam_fd_hw_cmd_prestart_args prestart_args; + struct cam_fd_mgr_frame_request *frame_req; + + if (!hw_mgr_priv || !hw_prepare_update_args) { + CAM_ERR(CAM_FD, "Invalid args %pK %pK", + hw_mgr_priv, hw_prepare_update_args); + return -EINVAL; + } + + hw_ctx = (struct cam_fd_hw_mgr_ctx *)prepare->ctxt_to_hw_map; + if (!hw_ctx || !hw_ctx->ctx_in_use) { + CAM_ERR(CAM_FD, "Invalid context is used, hw_ctx=%pK", hw_ctx); + return -EPERM; + } + + rc = cam_fd_mgr_util_get_device(hw_mgr, hw_ctx, &hw_device); + if (rc) { + CAM_ERR(CAM_FD, "Error in getting device %d", rc); + goto error; + } + + rc = cam_fd_mgr_util_packet_validate(prepare->packet, + prepare->remain_len); + if (rc) { + CAM_ERR(CAM_FD, "Error in packet validation %d", rc); + goto error; + } + + rc = cam_packet_util_get_kmd_buffer(prepare->packet, &kmd_buf); + if (rc) { + CAM_ERR(CAM_FD, "Error in get kmd buf buffer %d", rc); + goto error; + } + + CAM_DBG(CAM_FD, + "KMD Buf : hdl=%d, cpu_addr=%pK, offset=%d, size=%d, used=%d", + kmd_buf.handle, kmd_buf.cpu_addr, kmd_buf.offset, + kmd_buf.size, kmd_buf.used_bytes); + + /* We do not expect any patching, but just do it anyway */ + rc = cam_packet_util_process_patches(prepare->packet, + hw_mgr->device_iommu.non_secure, -1); + if (rc) { + CAM_ERR(CAM_FD, "Patch FD packet failed, rc=%d", rc); + return rc; + } + + memset(&prestart_args, 0x0, sizeof(prestart_args)); + prestart_args.ctx_hw_private = hw_ctx->ctx_hw_private; + prestart_args.hw_ctx = hw_ctx; + prestart_args.request_id = prepare->packet->header.request_id; + + rc = cam_fd_mgr_util_parse_generic_cmd_buffer(hw_ctx, prepare->packet, + &prestart_args); + if (rc) { + CAM_ERR(CAM_FD, "Error in parsing gerneric cmd buffer %d", rc); + goto error; + } + + rc = cam_fd_mgr_util_prepare_io_buf_info( + hw_mgr->device_iommu.non_secure, prepare, + prestart_args.input_buf, prestart_args.output_buf, + CAM_FD_MAX_IO_BUFFERS); + if (rc) { + CAM_ERR(CAM_FD, "Error in prepare IO Buf %d", rc); + goto error; + } + + rc = cam_fd_mgr_util_prepare_hw_update_entries(hw_mgr, prepare, + &prestart_args, &kmd_buf); + if (rc) { + CAM_ERR(CAM_FD, "Error in hw update entries %d", rc); + goto put_cpu_buf; + } + + /* get a free frame req from free list */ + rc = cam_fd_mgr_util_get_frame_req(&hw_mgr->frame_free_list, + &frame_req); + if (rc || !frame_req) { + CAM_ERR(CAM_FD, "Get frame_req failed, rc=%d, hw_ctx=%pK", + rc, hw_ctx); + rc = -ENOMEM; + goto put_cpu_buf; + } + + /* Setup frame request info and queue to pending list */ + frame_req->hw_ctx = hw_ctx; + frame_req->request_id = prepare->packet->header.request_id; + /* This has to be passed to HW while calling hw_ops->start */ + frame_req->hw_req_private = prestart_args.hw_req_private; + + /* + * Save the current frame_req into priv, + * this will come as priv while hw_config + */ + prepare->priv = frame_req; + + cam_fd_mgr_put_cpu_buf(prepare); + CAM_DBG(CAM_FD, "FramePrepare : Frame[%lld]", frame_req->request_id); + + return 0; + +put_cpu_buf: + cam_fd_mgr_put_cpu_buf(prepare); +error: + return rc; +} + +static int cam_fd_mgr_hw_config(void *hw_mgr_priv, void *hw_config_args) +{ + struct cam_fd_hw_mgr *hw_mgr = (struct cam_fd_hw_mgr *)hw_mgr_priv; + struct cam_hw_config_args *config = + (struct cam_hw_config_args *) hw_config_args; + struct cam_fd_hw_mgr_ctx *hw_ctx; + struct cam_fd_mgr_frame_request *frame_req; + int rc; + int i; + + if (!hw_mgr || !config) { + CAM_ERR(CAM_FD, "Invalid arguments %pK %pK", hw_mgr, config); + return -EINVAL; + } + + if (!config->num_hw_update_entries) { + CAM_ERR(CAM_FD, "No hw update enteries are available"); + return -EINVAL; + } + + hw_ctx = (struct cam_fd_hw_mgr_ctx *)config->ctxt_to_hw_map; + if (!hw_ctx || !hw_ctx->ctx_in_use) { + CAM_ERR(CAM_FD, "Invalid context is used, hw_ctx=%pK", hw_ctx); + return -EPERM; + } + + frame_req = config->priv; + + trace_cam_apply_req("FD", frame_req->request_id); + CAM_DBG(CAM_FD, "FrameHWConfig : Frame[%lld]", frame_req->request_id); + + frame_req->num_hw_update_entries = config->num_hw_update_entries; + for (i = 0; i < config->num_hw_update_entries; i++) { + frame_req->hw_update_entries[i] = config->hw_update_entries[i]; + CAM_DBG(CAM_FD, "PreStart HWEntry[%d] : %d %d %d %d %pK", + frame_req->hw_update_entries[i].handle, + frame_req->hw_update_entries[i].offset, + frame_req->hw_update_entries[i].len, + frame_req->hw_update_entries[i].flags, + frame_req->hw_update_entries[i].addr); + } + + if (hw_ctx->priority == CAM_FD_PRIORITY_HIGH) { + CAM_DBG(CAM_FD, "Insert frame into prio0 queue"); + rc = cam_fd_mgr_util_put_frame_req( + &hw_mgr->frame_pending_list_high, &frame_req); + } else { + CAM_DBG(CAM_FD, "Insert frame into prio1 queue"); + rc = cam_fd_mgr_util_put_frame_req( + &hw_mgr->frame_pending_list_normal, &frame_req); + } + if (rc) { + CAM_ERR(CAM_FD, "Failed in queuing frame req, rc=%d", rc); + goto put_free_list; + } + + rc = cam_fd_mgr_util_schedule_frame_worker_task(hw_mgr); + if (rc) { + CAM_ERR(CAM_FD, "Worker task scheduling failed %d", rc); + goto remove_and_put_free_list; + } + + return 0; + +remove_and_put_free_list: + + if (hw_ctx->priority == CAM_FD_PRIORITY_HIGH) { + CAM_DBG(CAM_FD, "Removing frame into prio0 queue"); + cam_fd_mgr_util_get_frame_req( + &hw_mgr->frame_pending_list_high, &frame_req); + } else { + CAM_DBG(CAM_FD, "Removing frame into prio1 queue"); + cam_fd_mgr_util_get_frame_req( + &hw_mgr->frame_pending_list_normal, &frame_req); + } +put_free_list: + cam_fd_mgr_util_put_frame_req(&hw_mgr->frame_free_list, + &frame_req); + + return rc; +} + +int cam_fd_hw_mgr_deinit(struct device_node *of_node) +{ + CAM_DBG(CAM_FD, "HW Mgr Deinit"); + + cam_req_mgr_workq_destroy(&g_fd_hw_mgr.work); + + cam_smmu_destroy_handle(g_fd_hw_mgr.device_iommu.non_secure); + g_fd_hw_mgr.device_iommu.non_secure = -1; + + mutex_destroy(&g_fd_hw_mgr.ctx_mutex); + mutex_destroy(&g_fd_hw_mgr.frame_req_mutex); + mutex_destroy(&g_fd_hw_mgr.hw_mgr_mutex); + + return 0; +} + +int cam_fd_hw_mgr_init(struct device_node *of_node, + struct cam_hw_mgr_intf *hw_mgr_intf) +{ + int count, i, rc = 0; + struct cam_hw_intf *hw_intf = NULL; + struct cam_fd_hw_mgr_ctx *hw_mgr_ctx; + struct cam_fd_device *hw_device; + struct cam_fd_mgr_frame_request *frame_req; + + if (!of_node || !hw_mgr_intf) { + CAM_ERR(CAM_FD, "Invalid args of_node %pK hw_mgr_intf %pK", + of_node, hw_mgr_intf); + return -EINVAL; + } + + memset(&g_fd_hw_mgr, 0x0, sizeof(g_fd_hw_mgr)); + memset(hw_mgr_intf, 0x0, sizeof(*hw_mgr_intf)); + + mutex_init(&g_fd_hw_mgr.ctx_mutex); + mutex_init(&g_fd_hw_mgr.frame_req_mutex); + mutex_init(&g_fd_hw_mgr.hw_mgr_mutex); + spin_lock_init(&g_fd_hw_mgr.hw_mgr_slock); + + count = of_property_count_strings(of_node, "compat-hw-name"); + if (!count || (count > CAM_FD_HW_MAX)) { + CAM_ERR(CAM_FD, "Invalid compat names in dev tree %d", count); + return -EINVAL; + } + g_fd_hw_mgr.num_devices = count; + + g_fd_hw_mgr.raw_results_available = false; + g_fd_hw_mgr.supported_modes = 0; + + for (i = 0; i < count; i++) { + hw_device = &g_fd_hw_mgr.hw_device[i]; + + rc = cam_fd_mgr_util_pdev_get_hw_intf(of_node, i, &hw_intf); + if (rc) { + CAM_ERR(CAM_FD, "hw intf from pdev failed, rc=%d", rc); + return rc; + } + + mutex_init(&hw_device->lock); + + hw_device->valid = true; + hw_device->hw_intf = hw_intf; + hw_device->ready_to_process = true; + + if (hw_device->hw_intf->hw_ops.process_cmd) { + struct cam_fd_hw_cmd_set_irq_cb irq_cb_args; + + irq_cb_args.cam_fd_hw_mgr_cb = cam_fd_mgr_irq_cb; + irq_cb_args.data = hw_device; + + rc = hw_device->hw_intf->hw_ops.process_cmd( + hw_device->hw_intf->hw_priv, + CAM_FD_HW_CMD_REGISTER_CALLBACK, + &irq_cb_args, sizeof(irq_cb_args)); + if (rc) { + CAM_ERR(CAM_FD, + "Failed in REGISTER_CALLBACK %d", rc); + return rc; + } + } + + if (hw_device->hw_intf->hw_ops.get_hw_caps) { + rc = hw_device->hw_intf->hw_ops.get_hw_caps( + hw_intf->hw_priv, &hw_device->hw_caps, + sizeof(hw_device->hw_caps)); + if (rc) { + CAM_ERR(CAM_FD, "Failed in get_hw_caps %d", rc); + return rc; + } + + g_fd_hw_mgr.raw_results_available |= + hw_device->hw_caps.raw_results_available; + g_fd_hw_mgr.supported_modes |= + hw_device->hw_caps.supported_modes; + + CAM_DBG(CAM_FD, + "Device[mode=%d, raw=%d], Mgr[mode=%d, raw=%d]", + hw_device->hw_caps.supported_modes, + hw_device->hw_caps.raw_results_available, + g_fd_hw_mgr.supported_modes, + g_fd_hw_mgr.raw_results_available); + } + } + + INIT_LIST_HEAD(&g_fd_hw_mgr.free_ctx_list); + INIT_LIST_HEAD(&g_fd_hw_mgr.used_ctx_list); + INIT_LIST_HEAD(&g_fd_hw_mgr.frame_free_list); + INIT_LIST_HEAD(&g_fd_hw_mgr.frame_pending_list_high); + INIT_LIST_HEAD(&g_fd_hw_mgr.frame_pending_list_normal); + INIT_LIST_HEAD(&g_fd_hw_mgr.frame_processing_list); + + g_fd_hw_mgr.device_iommu.non_secure = -1; + g_fd_hw_mgr.device_iommu.secure = -1; + g_fd_hw_mgr.cdm_iommu.non_secure = -1; + g_fd_hw_mgr.cdm_iommu.secure = -1; + + rc = cam_smmu_get_handle("fd", + &g_fd_hw_mgr.device_iommu.non_secure); + if (rc) { + CAM_ERR(CAM_FD, "Get iommu handle failed, rc=%d", rc); + goto destroy_mutex; + } + + rc = cam_cdm_get_iommu_handle("fd", &g_fd_hw_mgr.cdm_iommu); + if (rc) + CAM_DBG(CAM_FD, "Failed to acquire the CDM iommu handles"); + + CAM_DBG(CAM_FD, "iommu handles : device(%d, %d), cdm(%d, %d)", + g_fd_hw_mgr.device_iommu.non_secure, + g_fd_hw_mgr.device_iommu.secure, + g_fd_hw_mgr.cdm_iommu.non_secure, + g_fd_hw_mgr.cdm_iommu.secure); + + /* Init hw mgr contexts and add to free list */ + for (i = 0; i < CAM_CTX_MAX; i++) { + hw_mgr_ctx = &g_fd_hw_mgr.ctx_pool[i]; + + memset(hw_mgr_ctx, 0x0, sizeof(*hw_mgr_ctx)); + INIT_LIST_HEAD(&hw_mgr_ctx->list); + + hw_mgr_ctx->ctx_index = i; + hw_mgr_ctx->device_index = -1; + hw_mgr_ctx->hw_mgr = &g_fd_hw_mgr; + + list_add_tail(&hw_mgr_ctx->list, &g_fd_hw_mgr.free_ctx_list); + } + + /* Init hw mgr frame requests and add to free list */ + for (i = 0; i < CAM_CTX_REQ_MAX; i++) { + frame_req = &g_fd_hw_mgr.frame_req[i]; + + memset(frame_req, 0x0, sizeof(*frame_req)); + INIT_LIST_HEAD(&frame_req->list); + + list_add_tail(&frame_req->list, &g_fd_hw_mgr.frame_free_list); + } + + rc = cam_req_mgr_workq_create("cam_fd_worker", CAM_FD_WORKQ_NUM_TASK, + &g_fd_hw_mgr.work, CRM_WORKQ_USAGE_IRQ, 0); + if (rc) { + CAM_ERR(CAM_FD, "Unable to create a worker, rc=%d", rc); + goto detach_smmu; + } + + for (i = 0; i < CAM_FD_WORKQ_NUM_TASK; i++) + g_fd_hw_mgr.work->task.pool[i].payload = + &g_fd_hw_mgr.work_data[i]; + + /* Setup hw cap so that we can just return the info when requested */ + memset(&g_fd_hw_mgr.fd_caps, 0, sizeof(g_fd_hw_mgr.fd_caps)); + g_fd_hw_mgr.fd_caps.device_iommu = g_fd_hw_mgr.device_iommu; + g_fd_hw_mgr.fd_caps.cdm_iommu = g_fd_hw_mgr.cdm_iommu; + g_fd_hw_mgr.fd_caps.hw_caps = g_fd_hw_mgr.hw_device[0].hw_caps; + + CAM_DBG(CAM_FD, + "IOMMU device(%d, %d), CDM(%d, %d) versions core[%d.%d], wrapper[%d.%d]", + g_fd_hw_mgr.fd_caps.device_iommu.secure, + g_fd_hw_mgr.fd_caps.device_iommu.non_secure, + g_fd_hw_mgr.fd_caps.cdm_iommu.secure, + g_fd_hw_mgr.fd_caps.cdm_iommu.non_secure, + g_fd_hw_mgr.fd_caps.hw_caps.core_version.major, + g_fd_hw_mgr.fd_caps.hw_caps.core_version.minor, + g_fd_hw_mgr.fd_caps.hw_caps.wrapper_version.major, + g_fd_hw_mgr.fd_caps.hw_caps.wrapper_version.minor); + + hw_mgr_intf->hw_mgr_priv = &g_fd_hw_mgr; + hw_mgr_intf->hw_get_caps = cam_fd_mgr_hw_get_caps; + hw_mgr_intf->hw_acquire = cam_fd_mgr_hw_acquire; + hw_mgr_intf->hw_release = cam_fd_mgr_hw_release; + hw_mgr_intf->hw_start = cam_fd_mgr_hw_start; + hw_mgr_intf->hw_stop = cam_fd_mgr_hw_stop; + hw_mgr_intf->hw_prepare_update = cam_fd_mgr_hw_prepare_update; + hw_mgr_intf->hw_config = cam_fd_mgr_hw_config; + hw_mgr_intf->hw_read = NULL; + hw_mgr_intf->hw_write = NULL; + hw_mgr_intf->hw_close = NULL; + hw_mgr_intf->hw_flush = cam_fd_mgr_hw_flush; + hw_mgr_intf->hw_dump = cam_fd_mgr_hw_dump; + + return rc; + +detach_smmu: + cam_smmu_destroy_handle(g_fd_hw_mgr.device_iommu.non_secure); + g_fd_hw_mgr.device_iommu.non_secure = -1; +destroy_mutex: + mutex_destroy(&g_fd_hw_mgr.ctx_mutex); + mutex_destroy(&g_fd_hw_mgr.frame_req_mutex); + mutex_destroy(&g_fd_hw_mgr.hw_mgr_mutex); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.h b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.h new file mode 100644 index 0000000000000000000000000000000000000000..bbbc77bef6a381d7658db90934144047d2dba39c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_FD_HW_MGR_H_ +#define _CAM_FD_HW_MGR_H_ + +#include +#include + +#include +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "cam_hw_mgr_intf.h" +#include "cam_req_mgr_workq.h" +#include "cam_fd_hw_intf.h" + +#define CAM_FD_HW_MAX 1 +#define CAM_FD_WORKQ_NUM_TASK 10 + +/* + * Response time threshold in ms beyond which a request is not expected to be + * with FD hw + */ +#define CAM_FD_RESPONSE_TIME_THRESHOLD 100000 + +struct cam_fd_hw_mgr; + +/** + * enum cam_fd_mgr_work_type - Type of worker task + * + * @CAM_FD_WORK_FRAME : Work type indicating frame task + * @CAM_FD_WORK_IRQ : Work type indicating irq task + */ +enum cam_fd_mgr_work_type { + CAM_FD_WORK_FRAME, + CAM_FD_WORK_IRQ, +}; + +/** + * struct cam_fd_hw_mgr_ctx : FD HW Mgr context + * + * @list : List pointer used to maintain this context + * in free, used list + * @ctx_index : Index of this context + * @ctx_in_use : Whether this context is in use + * @event_cb : Event callback pointer to notify cam core context + * @cb_priv : Event callback private pointer + * @hw_mgr : Pointer to hw manager + * @get_raw_results : Whether this context needs raw results + * @mode : Mode in which this context runs + * @device_index : HW Device used by this context + * @ctx_hw_private : HW layer's private context pointer for this context + * @priority : Priority of this context + */ +struct cam_fd_hw_mgr_ctx { + struct list_head list; + uint32_t ctx_index; + bool ctx_in_use; + cam_hw_event_cb_func event_cb; + void *cb_priv; + struct cam_fd_hw_mgr *hw_mgr; + bool get_raw_results; + enum cam_fd_hw_mode mode; + int32_t device_index; + void *ctx_hw_private; + uint32_t priority; +}; + +/** + * struct cam_fd_device : FD HW Device + * + * @hw_caps : This FD device's capabilities + * @hw_intf : FD device's interface information + * @ready_to_process : Whether this device is ready to process next frame + * @num_ctxts : Number of context currently running on this device + * @valid : Whether this device is valid + * @lock : Lock used for protectin + * @cur_hw_ctx : current hw context running in the device + * @req_id : current processing req id + */ +struct cam_fd_device { + struct cam_fd_hw_caps hw_caps; + struct cam_hw_intf *hw_intf; + bool ready_to_process; + uint32_t num_ctxts; + bool valid; + struct mutex lock; + struct cam_fd_hw_mgr_ctx *cur_hw_ctx; + int64_t req_id; +}; + +/** + * struct cam_fd_mgr_frame_request : Frame request information maintained + * in HW Mgr layer + * + * @list : List pointer used to maintain this request in + * free, pending, processing request lists + * @request_id : Request ID corresponding to this request + * @hw_ctx : HW context from which this request is coming + * @hw_req_private : HW layer's private information specific to + * this request + * @hw_update_entries : HW update entries corresponding to this request + * which needs to be submitted to HW through CDM + * @num_hw_update_entries : Number of HW update entries + * @submit_timestamp : Time stamp for submit req with hw + */ +struct cam_fd_mgr_frame_request { + struct list_head list; + uint64_t request_id; + struct cam_fd_hw_mgr_ctx *hw_ctx; + struct cam_fd_hw_req_private hw_req_private; + struct cam_hw_update_entry hw_update_entries[CAM_FD_MAX_HW_ENTRIES]; + uint32_t num_hw_update_entries; + ktime_t submit_timestamp; +}; + +/** + * struct cam_fd_mgr_work_data : HW Mgr work data information + * + * @type : Type of work + * @irq_type : IRQ type when this work is queued because of irq callback + */ +struct cam_fd_mgr_work_data { + enum cam_fd_mgr_work_type type; + enum cam_fd_hw_irq_type irq_type; +}; + +/** + * struct cam_fd_hw_mgr : FD HW Mgr information + * + * @free_ctx_list : List of free contexts available for acquire + * @used_ctx_list : List of contexts that are acquired + * @frame_free_list : List of free frame requests available + * @frame_pending_list_high : List of high priority frame requests pending + * for processing + * @frame_pending_list_normal : List of normal priority frame requests pending + * for processing + * @frame_processing_list : List of frame requests currently being + * processed currently. Generally maximum one + * request would be present in this list + * @hw_mgr_mutex : Mutex to protect hw mgr data when accessed + * from multiple threads + * @hw_mgr_slock : Spin lock to protect hw mgr data when accessed + * from multiple threads + * @ctx_mutex : Mutex to protect context list + * @frame_req_mutex : Mutex to protect frame request list + * @device_iommu : Device IOMMU information + * @cdm_iommu : CDM IOMMU information + * @hw_device : Underlying HW device information + * @num_devices : Number of HW devices available + * @raw_results_available : Whether raw results available in this driver + * @supported_modes : Supported modes by this driver + * @ctx_pool : List of context + * @frame_req : List of frame requests + * @work : Worker handle + * @work_data : Worker data + * @fd_caps : FD driver capabilities + */ +struct cam_fd_hw_mgr { + struct list_head free_ctx_list; + struct list_head used_ctx_list; + struct list_head frame_free_list; + struct list_head frame_pending_list_high; + struct list_head frame_pending_list_normal; + struct list_head frame_processing_list; + struct mutex hw_mgr_mutex; + spinlock_t hw_mgr_slock; + struct mutex ctx_mutex; + struct mutex frame_req_mutex; + struct cam_iommu_handle device_iommu; + struct cam_iommu_handle cdm_iommu; + struct cam_fd_device hw_device[CAM_FD_HW_MAX]; + uint32_t num_devices; + bool raw_results_available; + uint32_t supported_modes; + struct cam_fd_hw_mgr_ctx ctx_pool[CAM_CTX_MAX]; + struct cam_fd_mgr_frame_request frame_req[CAM_CTX_REQ_MAX]; + struct cam_req_mgr_core_workq *work; + struct cam_fd_mgr_work_data work_data[CAM_FD_WORKQ_NUM_TASK]; + struct cam_fd_query_cap_cmd fd_caps; +}; + +#endif /* _CAM_FD_HW_MGR_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr_intf.h b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..81ed464e400a7cafb6788cf6c899df2a2bd287c7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr_intf.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_FD_HW_MGR_INTF_H_ +#define _CAM_FD_HW_MGR_INTF_H_ + +#include + +#include "cam_debug_util.h" +#include "cam_hw_mgr_intf.h" + +int cam_fd_hw_mgr_init(struct device_node *of_node, + struct cam_hw_mgr_intf *hw_mgr_intf); +int cam_fd_hw_mgr_deinit(struct device_node *of_node); + +#endif /* _CAM_FD_HW_MGR_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/Makefile b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..2d833feda99659c3311f6fef9db7dbcfa3127bd7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_fd_hw_dev.o cam_fd_hw_core.o cam_fd_hw_soc.o diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c new file mode 100644 index 0000000000000000000000000000000000000000..80e30ad6c64ebe6a467268700292222fd54f1092 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c @@ -0,0 +1,1248 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include "cam_fd_hw_core.h" +#include "cam_fd_hw_soc.h" +#include "cam_trace.h" + +#define CAM_FD_REG_VAL_PAIR_SIZE 256 + +static uint32_t cam_fd_cdm_write_reg_val_pair(uint32_t *buffer, + uint32_t index, uint32_t reg_offset, uint32_t reg_value) +{ + buffer[index++] = reg_offset; + buffer[index++] = reg_value; + + CAM_DBG(CAM_FD, "FD_CDM_CMD: Base[FD_CORE] Offset[0x%8x] Value[0x%8x]", + reg_offset, reg_value); + + return index; +} + +static void cam_fd_hw_util_cdm_callback(uint32_t handle, void *userdata, + enum cam_cdm_cb_status status, uint64_t cookie) +{ + trace_cam_cdm_cb("FD", status); + CAM_DBG(CAM_FD, "CDM hdl=%x, udata=%pK, status=%d, cookie=%llu", + handle, userdata, status, cookie); +} + +static void cam_fd_hw_util_enable_power_on_settings(struct cam_hw_info *fd_hw) +{ + struct cam_hw_soc_info *soc_info = &fd_hw->soc_info; + struct cam_fd_hw_static_info *hw_static_info = + ((struct cam_fd_core *)fd_hw->core_info)->hw_static_info; + + if (hw_static_info->enable_errata_wa.single_irq_only == false) { + /* Enable IRQs here */ + cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.irq_mask, + hw_static_info->irq_mask); + } + + /* QoS settings */ + cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.vbif_req_priority, + hw_static_info->qos_priority); + cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.vbif_priority_level, + hw_static_info->qos_priority_level); +} + +int cam_fd_hw_util_get_hw_caps(struct cam_hw_info *fd_hw, + struct cam_fd_hw_caps *hw_caps) +{ + struct cam_hw_soc_info *soc_info = &fd_hw->soc_info; + struct cam_fd_hw_static_info *hw_static_info = + ((struct cam_fd_core *)fd_hw->core_info)->hw_static_info; + uint32_t reg_value; + + if (!hw_static_info) { + CAM_ERR(CAM_FD, "Invalid hw info data"); + return -EINVAL; + } + + reg_value = cam_fd_soc_register_read(soc_info, CAM_FD_REG_CORE, + hw_static_info->core_regs.version); + hw_caps->core_version.major = + CAM_BITS_MASK_SHIFT(reg_value, 0xf00, 0x8); + hw_caps->core_version.minor = + CAM_BITS_MASK_SHIFT(reg_value, 0xf0, 0x4); + hw_caps->core_version.incr = + CAM_BITS_MASK_SHIFT(reg_value, 0xf, 0x0); + + reg_value = cam_fd_soc_register_read(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.wrapper_version); + hw_caps->wrapper_version.major = + CAM_BITS_MASK_SHIFT(reg_value, 0xf0000000, 0x1c); + hw_caps->wrapper_version.minor = + CAM_BITS_MASK_SHIFT(reg_value, 0xfff0000, 0x10); + hw_caps->wrapper_version.incr = + CAM_BITS_MASK_SHIFT(reg_value, 0xffff, 0x0); + + hw_caps->raw_results_available = + hw_static_info->results.raw_results_available; + hw_caps->supported_modes = hw_static_info->supported_modes; + + CAM_DBG(CAM_FD, "core:%d.%d.%d wrapper:%d.%d.%d intermediate:%d", + hw_caps->core_version.major, hw_caps->core_version.minor, + hw_caps->core_version.incr, hw_caps->wrapper_version.major, + hw_caps->wrapper_version.minor, hw_caps->wrapper_version.incr, + hw_caps->raw_results_available); + + return 0; +} + +static int cam_fd_hw_util_fdwrapper_sync_reset(struct cam_hw_info *fd_hw) +{ + struct cam_fd_core *fd_core = (struct cam_fd_core *)fd_hw->core_info; + struct cam_fd_hw_static_info *hw_static_info = fd_core->hw_static_info; + struct cam_hw_soc_info *soc_info = &fd_hw->soc_info; + long time_left; + + /* Before triggering reset to HW, clear the reset complete */ + reinit_completion(&fd_core->reset_complete); + + cam_fd_soc_register_write(soc_info, CAM_FD_REG_CORE, + hw_static_info->core_regs.control, 0x1); + + if (hw_static_info->enable_errata_wa.single_irq_only) { + cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.irq_mask, + CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_RESET_DONE)); + } + + cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.sw_reset, 0x1); + + time_left = wait_for_completion_timeout(&fd_core->reset_complete, + msecs_to_jiffies(CAM_FD_HW_HALT_RESET_TIMEOUT)); + if (time_left <= 0) + CAM_WARN(CAM_FD, "HW reset timeout time_left=%ld", time_left); + + CAM_DBG(CAM_FD, "FD Wrapper SW Sync Reset complete"); + + return 0; +} + + +static int cam_fd_hw_util_fdwrapper_halt(struct cam_hw_info *fd_hw) +{ + struct cam_fd_core *fd_core = (struct cam_fd_core *)fd_hw->core_info; + struct cam_fd_hw_static_info *hw_static_info = fd_core->hw_static_info; + struct cam_hw_soc_info *soc_info = &fd_hw->soc_info; + long time_left; + + /* Before triggering halt to HW, clear halt complete */ + reinit_completion(&fd_core->halt_complete); + + if (hw_static_info->enable_errata_wa.single_irq_only) { + cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.irq_mask, + CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_HALT_DONE)); + } + + cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.hw_stop, 0x1); + + time_left = wait_for_completion_timeout(&fd_core->halt_complete, + msecs_to_jiffies(CAM_FD_HW_HALT_RESET_TIMEOUT)); + if (time_left <= 0) + CAM_WARN(CAM_FD, "HW halt timeout time_left=%ld", time_left); + + CAM_DBG(CAM_FD, "FD Wrapper Halt complete"); + + return 0; +} + +static int cam_fd_hw_util_processcmd_prestart(struct cam_hw_info *fd_hw, + struct cam_fd_hw_cmd_prestart_args *prestart_args) +{ + struct cam_hw_soc_info *soc_info = &fd_hw->soc_info; + struct cam_fd_hw_static_info *hw_static_info = + ((struct cam_fd_core *)fd_hw->core_info)->hw_static_info; + struct cam_fd_ctx_hw_private *ctx_hw_private = + prestart_args->ctx_hw_private; + uint32_t size, size_required = 0; + uint32_t mem_base; + uint32_t *cmd_buf_addr = prestart_args->cmd_buf_addr; + uint32_t reg_val_pair[CAM_FD_REG_VAL_PAIR_SIZE]; + uint32_t num_cmds = 0; + int i; + struct cam_fd_hw_io_buffer *io_buf; + struct cam_fd_hw_req_private *req_private; + uint32_t available_size = prestart_args->size; + bool work_buffer_configured = false; + + if (!ctx_hw_private || !cmd_buf_addr) { + CAM_ERR(CAM_FD, "Invalid input prestart args %pK %pK", + ctx_hw_private, cmd_buf_addr); + return -EINVAL; + } + + if (prestart_args->get_raw_results && + !hw_static_info->results.raw_results_available) { + CAM_ERR(CAM_FD, "Raw results not supported %d %d", + prestart_args->get_raw_results, + hw_static_info->results.raw_results_available); + return -EINVAL; + } + + req_private = &prestart_args->hw_req_private; + req_private->ctx_hw_private = prestart_args->ctx_hw_private; + req_private->request_id = prestart_args->request_id; + req_private->get_raw_results = prestart_args->get_raw_results; + req_private->fd_results = NULL; + req_private->raw_results = NULL; + + /* Start preparing CDM register values that KMD has to insert */ + num_cmds = cam_fd_cdm_write_reg_val_pair(reg_val_pair, num_cmds, + hw_static_info->core_regs.control, 0x1); + num_cmds = cam_fd_cdm_write_reg_val_pair(reg_val_pair, num_cmds, + hw_static_info->core_regs.control, 0x0); + + for (i = 0; i < CAM_FD_MAX_IO_BUFFERS; i++) { + io_buf = &prestart_args->input_buf[i]; + + if (io_buf->valid == false) + break; + + if (io_buf->io_cfg->direction != CAM_BUF_INPUT) { + CAM_ERR(CAM_FD, "Incorrect direction %d %d", + io_buf->io_cfg->direction, CAM_BUF_INPUT); + return -EINVAL; + } + + switch (io_buf->io_cfg->resource_type) { + case CAM_FD_INPUT_PORT_ID_IMAGE: { + if ((num_cmds + 2) > CAM_FD_REG_VAL_PAIR_SIZE) { + CAM_ERR(CAM_FD, + "Invalid reg_val pair size %d, %d", + num_cmds, CAM_FD_REG_VAL_PAIR_SIZE); + return -EINVAL; + } + + num_cmds = cam_fd_cdm_write_reg_val_pair( + reg_val_pair, num_cmds, + hw_static_info->core_regs.image_addr, + io_buf->io_addr[0]); + break; + } + default: + CAM_ERR(CAM_FD, "Invalid resource type %d", + io_buf->io_cfg->resource_type); + return -EINVAL; + } + } + + for (i = 0; i < CAM_FD_MAX_IO_BUFFERS; i++) { + io_buf = &prestart_args->output_buf[i]; + + if (io_buf->valid == false) + break; + + if (io_buf->io_cfg->direction != CAM_BUF_OUTPUT) { + CAM_ERR(CAM_FD, "Incorrect direction %d %d", + io_buf->io_cfg->direction, CAM_BUF_INPUT); + return -EINVAL; + } + + switch (io_buf->io_cfg->resource_type) { + case CAM_FD_OUTPUT_PORT_ID_RESULTS: { + uint32_t face_results_offset; + + size_required = hw_static_info->results.max_faces * + hw_static_info->results.per_face_entries * 4; + + if (io_buf->io_cfg->planes[0].plane_stride < + size_required) { + CAM_ERR(CAM_FD, "Invalid results size %d %d", + io_buf->io_cfg->planes[0].plane_stride, + size_required); + return -EINVAL; + } + + req_private->fd_results = + (struct cam_fd_results *)io_buf->cpu_addr[0]; + + face_results_offset = + (uint8_t *)&req_private->fd_results->faces[0] - + (uint8_t *)req_private->fd_results; + + if (hw_static_info->ro_mode_supported) { + if ((num_cmds + 4) > CAM_FD_REG_VAL_PAIR_SIZE) { + CAM_ERR(CAM_FD, + "Invalid reg_val size %d, %d", + num_cmds, + CAM_FD_REG_VAL_PAIR_SIZE); + return -EINVAL; + } + /* + * Face data actually starts 16bytes later in + * the io buffer Check cam_fd_results. + */ + num_cmds = cam_fd_cdm_write_reg_val_pair( + reg_val_pair, num_cmds, + hw_static_info->core_regs.result_addr, + io_buf->io_addr[0] + + face_results_offset); + num_cmds = cam_fd_cdm_write_reg_val_pair( + reg_val_pair, num_cmds, + hw_static_info->core_regs.ro_mode, + 0x1); + + req_private->ro_mode_enabled = true; + } else { + req_private->ro_mode_enabled = false; + } + break; + } + case CAM_FD_OUTPUT_PORT_ID_RAW_RESULTS: { + size_required = + hw_static_info->results.raw_results_entries * + sizeof(uint32_t); + + if (io_buf->io_cfg->planes[0].plane_stride < + size_required) { + CAM_ERR(CAM_FD, "Invalid results size %d %d", + io_buf->io_cfg->planes[0].plane_stride, + size_required); + return -EINVAL; + } + + req_private->raw_results = + (uint32_t *)io_buf->cpu_addr[0]; + break; + } + case CAM_FD_OUTPUT_PORT_ID_WORK_BUFFER: { + if ((num_cmds + 2) > CAM_FD_REG_VAL_PAIR_SIZE) { + CAM_ERR(CAM_FD, + "Invalid reg_val pair size %d, %d", + num_cmds, CAM_FD_REG_VAL_PAIR_SIZE); + return -EINVAL; + } + + num_cmds = cam_fd_cdm_write_reg_val_pair( + reg_val_pair, num_cmds, + hw_static_info->core_regs.work_addr, + io_buf->io_addr[0]); + + work_buffer_configured = true; + break; + } + default: + CAM_ERR(CAM_FD, "Invalid resource type %d", + io_buf->io_cfg->resource_type); + return -EINVAL; + } + } + + if (!req_private->fd_results || !work_buffer_configured) { + CAM_ERR(CAM_FD, "Invalid IO Buffers results=%pK work=%d", + req_private->fd_results, work_buffer_configured); + return -EINVAL; + } + + /* First insert CHANGE_BASE command */ + size = ctx_hw_private->cdm_ops->cdm_required_size_changebase(); + /* since cdm returns dwords, we need to convert it into bytes */ + if ((size * 4) > available_size) { + CAM_ERR(CAM_FD, "buf size:%d is not sufficient, expected: %d", + prestart_args->size, size); + return -EINVAL; + } + + mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE(soc_info, + ((struct cam_fd_soc_private *)soc_info->soc_private)-> + regbase_index[CAM_FD_REG_CORE]); + + ctx_hw_private->cdm_ops->cdm_write_changebase(cmd_buf_addr, mem_base); + cmd_buf_addr += size; + available_size -= (size * 4); + + size = ctx_hw_private->cdm_ops->cdm_required_size_reg_random( + num_cmds/2); + /* cdm util returns dwords, need to convert to bytes */ + if ((size * 4) > available_size) { + CAM_ERR(CAM_FD, "Insufficient size:%d , expected size:%d", + available_size, size); + return -ENOMEM; + } + ctx_hw_private->cdm_ops->cdm_write_regrandom(cmd_buf_addr, num_cmds/2, + reg_val_pair); + cmd_buf_addr += size; + available_size -= (size * 4); + + /* Update pre_config_buf_size in bytes */ + prestart_args->pre_config_buf_size = + prestart_args->size - available_size; + + /* Insert start trigger command into CDM as post config commands. */ + num_cmds = cam_fd_cdm_write_reg_val_pair(reg_val_pair, 0, + hw_static_info->core_regs.control, 0x2); + size = ctx_hw_private->cdm_ops->cdm_required_size_reg_random( + num_cmds/2); + if ((size * 4) > available_size) { + CAM_ERR(CAM_FD, "Insufficient size:%d , expected size:%d", + available_size, size); + return -ENOMEM; + } + ctx_hw_private->cdm_ops->cdm_write_regrandom(cmd_buf_addr, num_cmds/2, + reg_val_pair); + cmd_buf_addr += size; + available_size -= (size * 4); + + prestart_args->post_config_buf_size = size * 4; + + CAM_DBG(CAM_FD, "PreConfig [%pK %d], PostConfig[%pK %d]", + prestart_args->cmd_buf_addr, prestart_args->pre_config_buf_size, + cmd_buf_addr, prestart_args->post_config_buf_size); + + for (i = 0; i < (prestart_args->pre_config_buf_size + + prestart_args->post_config_buf_size) / 4; i++) + CAM_DBG(CAM_FD, "CDM KMD Commands [%d] : [%pK] [0x%x]", i, + &prestart_args->cmd_buf_addr[i], + prestart_args->cmd_buf_addr[i]); + + return 0; +} + +static int cam_fd_hw_util_processcmd_frame_done(struct cam_hw_info *fd_hw, + struct cam_fd_hw_frame_done_args *frame_done_args) +{ + struct cam_fd_core *fd_core = (struct cam_fd_core *)fd_hw->core_info; + struct cam_fd_hw_static_info *hw_static_info = fd_core->hw_static_info; + struct cam_fd_hw_req_private *req_private; + uint32_t base, face_cnt; + uint32_t *buffer; + unsigned long flags; + int i; + + mutex_lock(&fd_hw->hw_mutex); + spin_lock_irqsave(&fd_core->spin_lock, flags); + if ((fd_core->core_state != CAM_FD_CORE_STATE_IDLE) || + (fd_core->results_valid == false) || + !fd_core->hw_req_private) { + CAM_ERR(CAM_FD, + "Invalid state for results state=%d, results=%d %pK", + fd_core->core_state, fd_core->results_valid, + fd_core->hw_req_private); + spin_unlock_irqrestore(&fd_core->spin_lock, flags); + mutex_unlock(&fd_hw->hw_mutex); + return -EINVAL; + } + fd_core->core_state = CAM_FD_CORE_STATE_READING_RESULTS; + req_private = fd_core->hw_req_private; + spin_unlock_irqrestore(&fd_core->spin_lock, flags); + + /* + * Copy the register value as is into output buffers. + * Wehter we are copying the output data by reading registers or + * programming output buffer directly to HW must be transparent to UMD. + * In case HW supports writing face count value directly into + * DDR memory in future, these values should match. + */ + req_private->fd_results->face_count = + cam_fd_soc_register_read(&fd_hw->soc_info, CAM_FD_REG_CORE, + hw_static_info->core_regs.result_cnt); + + face_cnt = req_private->fd_results->face_count & 0x3F; + + if (face_cnt > hw_static_info->results.max_faces) { + CAM_WARN(CAM_FD, "Face count greater than max %d %d", + face_cnt, hw_static_info->results.max_faces); + face_cnt = hw_static_info->results.max_faces; + } + + CAM_DBG(CAM_FD, "ReqID[%lld] Faces Detected = %d", + req_private->request_id, face_cnt); + + /* + * We need to read the face data information from registers only + * if one of below is true + * 1. RO mode is not set. i.e FD HW doesn't write face data into + * DDR memory + * 2. On the current chipset, results written into DDR memory by FD HW + * are not gauranteed to be correct + */ + if (!req_private->ro_mode_enabled || + hw_static_info->enable_errata_wa.ro_mode_results_invalid) { + buffer = (uint32_t *)&req_private->fd_results->faces[0]; + base = hw_static_info->core_regs.results_reg_base; + + /* + * Write register values as is into face data buffer. Its UMD + * driver responsibility to interpret the data and extract face + * properties from output buffer. Think in case output buffer + * is directly programmed to HW, then KMD has no control to + * extract the face properties and UMD anyway has to extract + * face properties. So we follow the same approach and keep + * this transparent to UMD. + */ + for (i = 0; + i < (face_cnt * + hw_static_info->results.per_face_entries); i++) { + *buffer = cam_fd_soc_register_read(&fd_hw->soc_info, + CAM_FD_REG_CORE, base + (i * 0x4)); + CAM_DBG(CAM_FD, "FaceData[%d] : 0x%x", i / 4, *buffer); + buffer++; + } + } + + if (req_private->get_raw_results && + req_private->raw_results && + hw_static_info->results.raw_results_available) { + buffer = req_private->raw_results; + base = hw_static_info->core_regs.raw_results_reg_base; + + for (i = 0; + i < hw_static_info->results.raw_results_entries; + i++) { + *buffer = cam_fd_soc_register_read(&fd_hw->soc_info, + CAM_FD_REG_CORE, base + (i * 0x4)); + CAM_DBG(CAM_FD, "RawData[%d] : 0x%x", i, *buffer); + buffer++; + } + } + + spin_lock_irqsave(&fd_core->spin_lock, flags); + fd_core->hw_req_private = NULL; + fd_core->core_state = CAM_FD_CORE_STATE_IDLE; + spin_unlock_irqrestore(&fd_core->spin_lock, flags); + mutex_unlock(&fd_hw->hw_mutex); + + return 0; +} + +static int cam_fd_hw_util_processcmd_hw_dump( + struct cam_hw_info *fd_hw, + void *args) +{ + int i, j; + uint8_t *dst; + uint32_t *addr, *start; + uint32_t num_reg, min_len; + uint64_t remain_len; + struct cam_hw_soc_info *soc_info; + struct cam_fd_hw_dump_header *hdr; + struct cam_fd_hw_dump_args *dump_args; + + if (!fd_hw || !args) { + CAM_ERR(CAM_FD, "Invalid args %pK %pK", + fd_hw, args); + return -EINVAL; + } + + mutex_lock(&fd_hw->hw_mutex); + + if (fd_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_INFO(CAM_FD, "power off state"); + mutex_unlock(&fd_hw->hw_mutex); + return 0; + } + + dump_args = (struct cam_fd_hw_dump_args *)args; + soc_info = &fd_hw->soc_info; + + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_FD, "dump offset overshoot len %zu offset %zu", + dump_args->buf_len, dump_args->offset); + mutex_unlock(&fd_hw->hw_mutex); + return -ENOSPC; + } + + remain_len = dump_args->buf_len - dump_args->offset; + min_len = sizeof(struct cam_fd_hw_dump_header) + + soc_info->reg_map[0].size + sizeof(uint32_t); + + if (remain_len < min_len) { + CAM_WARN(CAM_FD, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + mutex_unlock(&fd_hw->hw_mutex); + return -ENOSPC; + } + + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_fd_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_FD_HW_DUMP_TAG_MAX_LEN, + "FD_REG:"); + hdr->word_size = sizeof(uint32_t); + addr = (uint32_t *)(dst + sizeof(struct cam_fd_hw_dump_header)); + start = addr; + *addr++ = soc_info->index; + + for (j = 0; j < soc_info->num_reg_map; j++) { + num_reg = soc_info->reg_map[j].size/4; + for (i = 0; i < num_reg; i++) { + *addr++ = soc_info->mem_block[j]->start + i*4; + *addr++ = cam_io_r(soc_info->reg_map[j].mem_base + + (i*4)); + } + } + + mutex_unlock(&fd_hw->hw_mutex); + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_fd_hw_dump_header); + CAM_DBG(CAM_FD, "%zu", dump_args->offset); + return 0; +} + +irqreturn_t cam_fd_hw_irq(int irq_num, void *data) +{ + struct cam_hw_info *fd_hw = (struct cam_hw_info *)data; + struct cam_fd_core *fd_core; + struct cam_hw_soc_info *soc_info; + struct cam_fd_hw_static_info *hw_static_info; + uint32_t reg_value; + enum cam_fd_hw_irq_type irq_type = CAM_FD_IRQ_FRAME_DONE; + uint32_t num_irqs = 0; + + if (!fd_hw) { + CAM_ERR(CAM_FD, "Invalid data in IRQ callback"); + return IRQ_NONE; + } + + fd_core = (struct cam_fd_core *) fd_hw->core_info; + soc_info = &fd_hw->soc_info; + hw_static_info = fd_core->hw_static_info; + + reg_value = cam_fd_soc_register_read(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.irq_status); + + CAM_DBG(CAM_FD, "FD IRQ status 0x%x", reg_value); + + cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.irq_clear, + reg_value); + + if (reg_value & CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_HALT_DONE)) { + complete_all(&fd_core->halt_complete); + irq_type = CAM_FD_IRQ_HALT_DONE; + num_irqs++; + } + + if (reg_value & CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_RESET_DONE)) { + complete_all(&fd_core->reset_complete); + irq_type = CAM_FD_IRQ_RESET_DONE; + num_irqs++; + } + + if (reg_value & CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_FRAME_DONE)) { + complete_all(&fd_core->processing_complete); + irq_type = CAM_FD_IRQ_FRAME_DONE; + num_irqs++; + } + + /* + * We should never get an IRQ callback with no or more than one mask. + * Validate first to make sure nothing going wrong. + */ + if (num_irqs != 1) { + CAM_ERR(CAM_FD, + "Invalid number of IRQs, value=0x%x, num_irqs=%d", + reg_value, num_irqs); + return IRQ_NONE; + } + + trace_cam_irq_activated("FD", irq_type); + + if (irq_type == CAM_FD_IRQ_HALT_DONE) { + /* + * Do not send HALT IRQ callback to Hw Mgr, + * a reset would always follow + */ + return IRQ_HANDLED; + } + + spin_lock(&fd_core->spin_lock); + /* Do not change state to IDLE on HALT IRQ. Reset must follow halt */ + if ((irq_type == CAM_FD_IRQ_RESET_DONE) || + (irq_type == CAM_FD_IRQ_FRAME_DONE)) { + + fd_core->core_state = CAM_FD_CORE_STATE_IDLE; + if (irq_type == CAM_FD_IRQ_FRAME_DONE) + fd_core->results_valid = true; + + CAM_DBG(CAM_FD, "FD IRQ type %d, state=%d", + irq_type, fd_core->core_state); + } + spin_unlock(&fd_core->spin_lock); + + if (fd_core->irq_cb.cam_fd_hw_mgr_cb) + fd_core->irq_cb.cam_fd_hw_mgr_cb(fd_core->irq_cb.data, + irq_type); + + return IRQ_HANDLED; +} + +int cam_fd_hw_get_hw_caps(void *hw_priv, void *get_hw_cap_args, + uint32_t arg_size) +{ + struct cam_hw_info *fd_hw = (struct cam_hw_info *)hw_priv; + struct cam_fd_core *fd_core; + struct cam_fd_hw_caps *fd_hw_caps = + (struct cam_fd_hw_caps *)get_hw_cap_args; + + if (!hw_priv || !get_hw_cap_args) { + CAM_ERR(CAM_FD, "Invalid input pointers %pK %pK", + hw_priv, get_hw_cap_args); + return -EINVAL; + } + + fd_core = (struct cam_fd_core *)fd_hw->core_info; + *fd_hw_caps = fd_core->hw_caps; + + CAM_DBG(CAM_FD, "core:%d.%d wrapper:%d.%d mode:%d, raw:%d", + fd_hw_caps->core_version.major, + fd_hw_caps->core_version.minor, + fd_hw_caps->wrapper_version.major, + fd_hw_caps->wrapper_version.minor, + fd_hw_caps->supported_modes, + fd_hw_caps->raw_results_available); + + return 0; +} + +int cam_fd_hw_init(void *hw_priv, void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *fd_hw = (struct cam_hw_info *)hw_priv; + struct cam_fd_core *fd_core; + struct cam_fd_hw_init_args *init_args = + (struct cam_fd_hw_init_args *)init_hw_args; + int rc = 0; + unsigned long flags; + + if (!fd_hw || !init_args) { + CAM_ERR(CAM_FD, "Invalid argument %pK %pK", fd_hw, init_args); + return -EINVAL; + } + + if (arg_size != sizeof(struct cam_fd_hw_init_args)) { + CAM_ERR(CAM_FD, "Invalid arg size %u, %zu", arg_size, + sizeof(struct cam_fd_hw_init_args)); + return -EINVAL; + } + + fd_core = (struct cam_fd_core *)fd_hw->core_info; + + mutex_lock(&fd_hw->hw_mutex); + CAM_DBG(CAM_FD, "FD HW Init ref count before %d", fd_hw->open_count); + + if (fd_hw->open_count > 0) { + rc = 0; + goto cdm_streamon; + } + + rc = cam_fd_soc_enable_resources(&fd_hw->soc_info); + if (rc) { + CAM_ERR(CAM_FD, "Enable SOC failed, rc=%d", rc); + goto unlock_return; + } + + spin_lock_irqsave(&fd_core->spin_lock, flags); + fd_hw->hw_state = CAM_HW_STATE_POWER_UP; + fd_core->core_state = CAM_FD_CORE_STATE_IDLE; + spin_unlock_irqrestore(&fd_core->spin_lock, flags); + + if (init_args->reset_required) { + rc = cam_fd_hw_reset(hw_priv, NULL, 0); + if (rc) { + CAM_ERR(CAM_FD, "Reset Failed, rc=%d", rc); + goto disable_soc; + } + } + + cam_fd_hw_util_enable_power_on_settings(fd_hw); + +cdm_streamon: + fd_hw->open_count++; + CAM_DBG(CAM_FD, "FD HW Init ref count after %d", fd_hw->open_count); + + if (init_args->ctx_hw_private) { + struct cam_fd_ctx_hw_private *ctx_hw_private = + init_args->ctx_hw_private; + + rc = cam_cdm_stream_on(ctx_hw_private->cdm_handle); + if (rc) { + CAM_ERR(CAM_FD, "CDM StreamOn fail :handle=0x%x, rc=%d", + ctx_hw_private->cdm_handle, rc); + fd_hw->open_count--; + if (!fd_hw->open_count) + goto disable_soc; + } + } + + mutex_unlock(&fd_hw->hw_mutex); + + return rc; + +disable_soc: + if (cam_fd_soc_disable_resources(&fd_hw->soc_info)) + CAM_ERR(CAM_FD, "Error in disable soc resources"); + + spin_lock_irqsave(&fd_core->spin_lock, flags); + fd_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + fd_core->core_state = CAM_FD_CORE_STATE_POWERDOWN; + spin_unlock_irqrestore(&fd_core->spin_lock, flags); +unlock_return: + mutex_unlock(&fd_hw->hw_mutex); + return rc; +} + +int cam_fd_hw_deinit(void *hw_priv, void *deinit_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *fd_hw = hw_priv; + struct cam_fd_core *fd_core = NULL; + struct cam_fd_hw_deinit_args *deinit_args = + (struct cam_fd_hw_deinit_args *)deinit_hw_args; + int rc = 0; + unsigned long flags; + + if (!fd_hw || !deinit_hw_args) { + CAM_ERR(CAM_FD, "Invalid argument"); + return -EINVAL; + } + + if (arg_size != sizeof(struct cam_fd_hw_deinit_args)) { + CAM_ERR(CAM_FD, "Invalid arg size %u, %zu", arg_size, + sizeof(struct cam_fd_hw_deinit_args)); + return -EINVAL; + } + + mutex_lock(&fd_hw->hw_mutex); + if (fd_hw->open_count == 0) { + mutex_unlock(&fd_hw->hw_mutex); + CAM_ERR(CAM_FD, "Error Unbalanced deinit"); + return -EFAULT; + } + + fd_hw->open_count--; + CAM_DBG(CAM_FD, "FD HW ref count=%d", fd_hw->open_count); + + if (fd_hw->open_count > 0) { + rc = 0; + goto positive_ref_cnt; + } + + rc = cam_fd_soc_disable_resources(&fd_hw->soc_info); + if (rc) + CAM_ERR(CAM_FD, "Failed in Disable SOC, rc=%d", rc); + + fd_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + fd_core = (struct cam_fd_core *)fd_hw->core_info; + + /* With the ref_cnt correct, this should never happen */ + WARN_ON(!fd_core); + + spin_lock_irqsave(&fd_core->spin_lock, flags); + fd_core->core_state = CAM_FD_CORE_STATE_POWERDOWN; + spin_unlock_irqrestore(&fd_core->spin_lock, flags); +positive_ref_cnt: + if (deinit_args->ctx_hw_private) { + struct cam_fd_ctx_hw_private *ctx_hw_private = + deinit_args->ctx_hw_private; + + rc = cam_cdm_stream_off(ctx_hw_private->cdm_handle); + if (rc) { + CAM_ERR(CAM_FD, + "Failed in CDM StreamOff, handle=0x%x, rc=%d", + ctx_hw_private->cdm_handle, rc); + } + } + + mutex_unlock(&fd_hw->hw_mutex); + return rc; +} + +int cam_fd_hw_reset(void *hw_priv, void *reset_core_args, uint32_t arg_size) +{ + struct cam_hw_info *fd_hw = (struct cam_hw_info *)hw_priv; + struct cam_fd_core *fd_core; + struct cam_fd_hw_static_info *hw_static_info; + struct cam_hw_soc_info *soc_info; + unsigned long flags; + int rc; + + if (!fd_hw) { + CAM_ERR(CAM_FD, "Invalid input handle"); + return -EINVAL; + } + + fd_core = (struct cam_fd_core *)fd_hw->core_info; + hw_static_info = fd_core->hw_static_info; + soc_info = &fd_hw->soc_info; + + spin_lock_irqsave(&fd_core->spin_lock, flags); + if ((fd_core->core_state == CAM_FD_CORE_STATE_POWERDOWN) || + (fd_core->core_state == CAM_FD_CORE_STATE_RESET_PROGRESS)) { + CAM_ERR(CAM_FD, "Reset not allowed in %d state", + fd_core->core_state); + spin_unlock_irqrestore(&fd_core->spin_lock, flags); + return -EINVAL; + } + + fd_core->results_valid = false; + fd_core->core_state = CAM_FD_CORE_STATE_RESET_PROGRESS; + spin_unlock_irqrestore(&fd_core->spin_lock, flags); + + cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.cgc_disable, 0x1); + + rc = cam_fd_hw_util_fdwrapper_halt(fd_hw); + if (rc) { + CAM_ERR(CAM_FD, "Failed in HALT rc=%d", rc); + return rc; + } + + rc = cam_fd_hw_util_fdwrapper_sync_reset(fd_hw); + if (rc) { + CAM_ERR(CAM_FD, "Failed in RESET rc=%d", rc); + return rc; + } + + cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.cgc_disable, 0x0); + + spin_lock_irqsave(&fd_core->spin_lock, flags); + fd_core->core_state = CAM_FD_CORE_STATE_IDLE; + spin_unlock_irqrestore(&fd_core->spin_lock, flags); + + return rc; +} + +int cam_fd_hw_start(void *hw_priv, void *hw_start_args, uint32_t arg_size) +{ + struct cam_hw_info *fd_hw = (struct cam_hw_info *)hw_priv; + struct cam_fd_core *fd_core; + struct cam_fd_hw_static_info *hw_static_info; + struct cam_fd_hw_cmd_start_args *start_args = + (struct cam_fd_hw_cmd_start_args *)hw_start_args; + struct cam_fd_ctx_hw_private *ctx_hw_private; + unsigned long flags; + int rc; + + if (!hw_priv || !start_args) { + CAM_ERR(CAM_FD, "Invalid input args %pK %pK", hw_priv, + start_args); + return -EINVAL; + } + + if (arg_size != sizeof(struct cam_fd_hw_cmd_start_args)) { + CAM_ERR(CAM_FD, "Invalid arg size %u, %zu", arg_size, + sizeof(struct cam_fd_hw_cmd_start_args)); + return -EINVAL; + } + + fd_core = (struct cam_fd_core *)fd_hw->core_info; + hw_static_info = fd_core->hw_static_info; + + spin_lock_irqsave(&fd_core->spin_lock, flags); + if (fd_core->core_state != CAM_FD_CORE_STATE_IDLE) { + CAM_ERR(CAM_FD, "Cannot start in %d state", + fd_core->core_state); + spin_unlock_irqrestore(&fd_core->spin_lock, flags); + return -EINVAL; + } + + /* + * We are about to start FD HW processing, save the request + * private data which is being processed by HW. Once the frame + * processing is finished, process_cmd(FRAME_DONE) should be called + * with same hw_req_private as input. + */ + fd_core->hw_req_private = start_args->hw_req_private; + fd_core->core_state = CAM_FD_CORE_STATE_PROCESSING; + fd_core->results_valid = false; + spin_unlock_irqrestore(&fd_core->spin_lock, flags); + + ctx_hw_private = start_args->ctx_hw_private; + + /* Before starting HW process, clear processing complete */ + reinit_completion(&fd_core->processing_complete); + + if (hw_static_info->enable_errata_wa.single_irq_only) { + cam_fd_soc_register_write(&fd_hw->soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.irq_mask, + CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_FRAME_DONE)); + } + + if (start_args->num_hw_update_entries > 0) { + struct cam_cdm_bl_request *cdm_cmd = ctx_hw_private->cdm_cmd; + struct cam_hw_update_entry *cmd; + int i; + + cdm_cmd->cmd_arrary_count = start_args->num_hw_update_entries; + cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE; + cdm_cmd->flag = false; + cdm_cmd->userdata = NULL; + cdm_cmd->cookie = 0; + cdm_cmd->gen_irq_arb = false; + + for (i = 0 ; i <= start_args->num_hw_update_entries; i++) { + cmd = (start_args->hw_update_entries + i); + cdm_cmd->cmd[i].bl_addr.mem_handle = cmd->handle; + cdm_cmd->cmd[i].offset = cmd->offset; + cdm_cmd->cmd[i].len = cmd->len; + cdm_cmd->cmd[i].arbitrate = false; + } + + rc = cam_cdm_submit_bls(ctx_hw_private->cdm_handle, cdm_cmd); + if (rc) { + CAM_ERR(CAM_FD, + "Failed to submit cdm commands, rc=%d", rc); + goto error; + } + } else { + CAM_ERR(CAM_FD, "Invalid number of hw update entries"); + rc = -EINVAL; + goto error; + } + + return 0; +error: + spin_lock_irqsave(&fd_core->spin_lock, flags); + fd_core->core_state = CAM_FD_CORE_STATE_IDLE; + spin_unlock_irqrestore(&fd_core->spin_lock, flags); + + return rc; +} + +int cam_fd_hw_halt_reset(void *hw_priv, void *stop_args, uint32_t arg_size) +{ + struct cam_hw_info *fd_hw = (struct cam_hw_info *)hw_priv; + struct cam_fd_core *fd_core; + struct cam_fd_hw_static_info *hw_static_info; + struct cam_hw_soc_info *soc_info; + unsigned long flags; + int rc; + + if (!fd_hw) { + CAM_ERR(CAM_FD, "Invalid input handle"); + return -EINVAL; + } + + fd_core = (struct cam_fd_core *)fd_hw->core_info; + hw_static_info = fd_core->hw_static_info; + soc_info = &fd_hw->soc_info; + + spin_lock_irqsave(&fd_core->spin_lock, flags); + if ((fd_core->core_state == CAM_FD_CORE_STATE_POWERDOWN) || + (fd_core->core_state == CAM_FD_CORE_STATE_RESET_PROGRESS)) { + CAM_ERR(CAM_FD, "Reset not allowed in %d state", + fd_core->core_state); + spin_unlock_irqrestore(&fd_core->spin_lock, flags); + return -EINVAL; + } + + fd_core->results_valid = false; + fd_core->core_state = CAM_FD_CORE_STATE_RESET_PROGRESS; + spin_unlock_irqrestore(&fd_core->spin_lock, flags); + + cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.cgc_disable, 0x1); + + rc = cam_fd_hw_util_fdwrapper_halt(fd_hw); + if (rc) { + CAM_ERR(CAM_FD, "Failed in HALT rc=%d", rc); + return rc; + } + + /* HALT must be followed by RESET */ + rc = cam_fd_hw_util_fdwrapper_sync_reset(fd_hw); + if (rc) { + CAM_ERR(CAM_FD, "Failed in RESET rc=%d", rc); + return rc; + } + + cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER, + hw_static_info->wrapper_regs.cgc_disable, 0x0); + + spin_lock_irqsave(&fd_core->spin_lock, flags); + fd_core->core_state = CAM_FD_CORE_STATE_IDLE; + spin_unlock_irqrestore(&fd_core->spin_lock, flags); + + return rc; +} + +int cam_fd_hw_reserve(void *hw_priv, void *hw_reserve_args, uint32_t arg_size) +{ + struct cam_hw_info *fd_hw = (struct cam_hw_info *)hw_priv; + int rc = -EINVAL; + struct cam_fd_ctx_hw_private *ctx_hw_private; + struct cam_fd_hw_reserve_args *reserve_args = + (struct cam_fd_hw_reserve_args *)hw_reserve_args; + struct cam_cdm_acquire_data cdm_acquire; + struct cam_cdm_bl_request *cdm_cmd; + int i; + + if (!fd_hw || !reserve_args) { + CAM_ERR(CAM_FD, "Invalid input %pK, %pK", fd_hw, reserve_args); + return -EINVAL; + } + + if (arg_size != sizeof(struct cam_fd_hw_reserve_args)) { + CAM_ERR(CAM_FD, "Invalid arg size %u, %zu", arg_size, + sizeof(struct cam_fd_hw_reserve_args)); + return -EINVAL; + } + + cdm_cmd = kzalloc(((sizeof(struct cam_cdm_bl_request)) + + ((CAM_FD_MAX_HW_ENTRIES - 1) * + sizeof(struct cam_cdm_bl_cmd))), GFP_KERNEL); + if (!cdm_cmd) + return -ENOMEM; + + ctx_hw_private = kzalloc(sizeof(struct cam_fd_ctx_hw_private), + GFP_KERNEL); + if (!ctx_hw_private) { + kfree(cdm_cmd); + return -ENOMEM; + } + + memset(&cdm_acquire, 0, sizeof(cdm_acquire)); + strlcpy(cdm_acquire.identifier, "fd", sizeof("fd")); + cdm_acquire.cell_index = fd_hw->soc_info.index; + cdm_acquire.handle = 0; + cdm_acquire.userdata = ctx_hw_private; + cdm_acquire.cam_cdm_callback = cam_fd_hw_util_cdm_callback; + cdm_acquire.id = CAM_CDM_VIRTUAL; + cdm_acquire.base_array_cnt = fd_hw->soc_info.num_reg_map; + cdm_acquire.priority = CAM_CDM_BL_FIFO_0; + for (i = 0; i < fd_hw->soc_info.num_reg_map; i++) + cdm_acquire.base_array[i] = &fd_hw->soc_info.reg_map[i]; + + rc = cam_cdm_acquire(&cdm_acquire); + if (rc) { + CAM_ERR(CAM_FD, "Failed to acquire the CDM HW"); + goto error; + } + + ctx_hw_private->hw_ctx = reserve_args->hw_ctx; + ctx_hw_private->fd_hw = fd_hw; + ctx_hw_private->mode = reserve_args->mode; + ctx_hw_private->cdm_handle = cdm_acquire.handle; + ctx_hw_private->cdm_ops = cdm_acquire.ops; + ctx_hw_private->cdm_cmd = cdm_cmd; + + reserve_args->ctx_hw_private = ctx_hw_private; + + CAM_DBG(CAM_FD, "private=%pK, hw_ctx=%pK, mode=%d, cdm_handle=0x%x", + ctx_hw_private, ctx_hw_private->hw_ctx, ctx_hw_private->mode, + ctx_hw_private->cdm_handle); + + return 0; +error: + kfree(ctx_hw_private); + kfree(cdm_cmd); + return rc; +} + +int cam_fd_hw_release(void *hw_priv, void *hw_release_args, uint32_t arg_size) +{ + struct cam_hw_info *fd_hw = (struct cam_hw_info *)hw_priv; + int rc = -EINVAL; + struct cam_fd_ctx_hw_private *ctx_hw_private; + struct cam_fd_hw_release_args *release_args = + (struct cam_fd_hw_release_args *)hw_release_args; + + if (!fd_hw || !release_args) { + CAM_ERR(CAM_FD, "Invalid input %pK, %pK", fd_hw, release_args); + return -EINVAL; + } + + if (arg_size != sizeof(struct cam_fd_hw_release_args)) { + CAM_ERR(CAM_FD, "Invalid arg size %u, %zu", arg_size, + sizeof(struct cam_fd_hw_release_args)); + return -EINVAL; + } + + ctx_hw_private = + (struct cam_fd_ctx_hw_private *)release_args->ctx_hw_private; + + rc = cam_cdm_release(ctx_hw_private->cdm_handle); + if (rc) + CAM_ERR(CAM_FD, "Release cdm handle failed, handle=0x%x, rc=%d", + ctx_hw_private->cdm_handle, rc); + + kfree(ctx_hw_private->cdm_cmd); + kfree(ctx_hw_private); + release_args->ctx_hw_private = NULL; + + return 0; +} + +int cam_fd_hw_process_cmd(void *hw_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + struct cam_hw_info *fd_hw = (struct cam_hw_info *)hw_priv; + int rc = -EINVAL; + + if (!hw_priv || !cmd_args || + (cmd_type >= CAM_FD_HW_CMD_MAX)) { + CAM_ERR(CAM_FD, "Invalid arguments %pK %pK %d", hw_priv, + cmd_args, cmd_type); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_FD_HW_CMD_REGISTER_CALLBACK: { + struct cam_fd_hw_cmd_set_irq_cb *irq_cb_args; + struct cam_fd_core *fd_core = + (struct cam_fd_core *)fd_hw->core_info; + + if (sizeof(struct cam_fd_hw_cmd_set_irq_cb) != arg_size) { + CAM_ERR(CAM_FD, "cmd_type %d, size mismatch %d", + cmd_type, arg_size); + break; + } + + irq_cb_args = (struct cam_fd_hw_cmd_set_irq_cb *)cmd_args; + fd_core->irq_cb.cam_fd_hw_mgr_cb = + irq_cb_args->cam_fd_hw_mgr_cb; + fd_core->irq_cb.data = irq_cb_args->data; + rc = 0; + break; + } + case CAM_FD_HW_CMD_PRESTART: { + struct cam_fd_hw_cmd_prestart_args *prestart_args; + + if (sizeof(struct cam_fd_hw_cmd_prestart_args) != arg_size) { + CAM_ERR(CAM_FD, "cmd_type %d, size mismatch %d", + cmd_type, arg_size); + break; + } + + prestart_args = (struct cam_fd_hw_cmd_prestart_args *)cmd_args; + rc = cam_fd_hw_util_processcmd_prestart(fd_hw, prestart_args); + break; + } + case CAM_FD_HW_CMD_FRAME_DONE: { + struct cam_fd_hw_frame_done_args *cmd_frame_results; + + if (sizeof(struct cam_fd_hw_frame_done_args) != + arg_size) { + CAM_ERR(CAM_FD, "cmd_type %d, size mismatch %d", + cmd_type, arg_size); + break; + } + + cmd_frame_results = + (struct cam_fd_hw_frame_done_args *)cmd_args; + rc = cam_fd_hw_util_processcmd_frame_done(fd_hw, + cmd_frame_results); + break; + } + case CAM_FD_HW_CMD_HW_DUMP: { + rc = cam_fd_hw_util_processcmd_hw_dump(fd_hw, + cmd_args); + break; + } + default: + break; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h new file mode 100644 index 0000000000000000000000000000000000000000..22bcdf6fc7330de7e372608e59778fb6592be9eb --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_FD_HW_CORE_H_ +#define _CAM_FD_HW_CORE_H_ + +#include +#include +#include +#include +#include + +#include "cam_common_util.h" +#include "cam_debug_util.h" +#include "cam_io_util.h" +#include "cam_cpas_api.h" +#include "cam_cdm_intf_api.h" +#include "cam_fd_hw_intf.h" +#include "cam_fd_hw_soc.h" + +#define CAM_FD_IRQ_TO_MASK(irq) (1 << (irq)) +#define CAM_FD_MASK_TO_IRQ(mask, irq) ((mask) >> (irq)) + +#define CAM_FD_HW_HALT_RESET_TIMEOUT 750 + +/** + * enum cam_fd_core_state - FD Core internal states + * + * @CAM_FD_CORE_STATE_POWERDOWN : Indicates FD core is powered down + * @CAM_FD_CORE_STATE_IDLE : Indicates FD HW is in idle state. + * Core can be in this state when it is + * ready to process frames or when + * processing is finished and results are + * available + * @CAM_FD_CORE_STATE_PROCESSING : Indicates FD core is processing frame + * @CAM_FD_CORE_STATE_READING_RESULTS : Indicates results are being read from + * FD core + * @CAM_FD_CORE_STATE_RESET_PROGRESS : Indicates FD Core is in reset state + */ +enum cam_fd_core_state { + CAM_FD_CORE_STATE_POWERDOWN, + CAM_FD_CORE_STATE_IDLE, + CAM_FD_CORE_STATE_PROCESSING, + CAM_FD_CORE_STATE_READING_RESULTS, + CAM_FD_CORE_STATE_RESET_PROGRESS, +}; + +/** + * struct cam_fd_ctx_hw_private : HW private information for a specific hw ctx. + * This information is populated by HW layer on + * reserve() and given back to HW Mgr as private + * data for the hw context. This private_data + * has to be passed by HW Mgr layer while + * further HW layer calls + * + * @hw_ctx : Corresponding hw_ctx pointer + * @fd_hw : FD HW info pointer + * @cdm_handle : CDM Handle for this context + * @cdm_ops : CDM Ops + * @cdm_cmd : CDM command pointer + * @mode : Mode this context is running + * @curr_req_private : Current Request information + * + */ +struct cam_fd_ctx_hw_private { + void *hw_ctx; + struct cam_hw_info *fd_hw; + uint32_t cdm_handle; + struct cam_cdm_utils_ops *cdm_ops; + struct cam_cdm_bl_request *cdm_cmd; + enum cam_fd_hw_mode mode; + struct cam_fd_hw_req_private *curr_req_private; +}; + +/** + * struct cam_fd_core_regs : FD HW Core register offsets info + * + * @version : Offset of version register + * @control : Offset of control register + * @result_cnt : Offset of result count register + * @result_addr : Offset of results address register + * @image_addr : Offset of image address register + * @work_addr : Offset of work address register + * @ro_mode : Offset of ro_mode register + * @results_reg_base : Offset of results_reg_base register + * @raw_results_reg_base : Offset of raw_results_reg_base register + * + */ +struct cam_fd_core_regs { + uint32_t version; + uint32_t control; + uint32_t result_cnt; + uint32_t result_addr; + uint32_t image_addr; + uint32_t work_addr; + uint32_t ro_mode; + uint32_t results_reg_base; + uint32_t raw_results_reg_base; +}; + +/** + * struct cam_fd_core_regs : FD HW Wrapper register offsets info + * + * @wrapper_version : Offset of wrapper_version register + * @cgc_disable : Offset of cgc_disable register + * @hw_stop : Offset of hw_stop register + * @sw_reset : Offset of sw_reset register + * @vbif_req_priority : Offset of vbif_req_priority register + * @vbif_priority_level : Offset of vbif_priority_level register + * @vbif_done_status : Offset of vbif_done_status register + * @irq_mask : Offset of irq mask register + * @irq_status : Offset of irq status register + * @irq_clear : Offset of irq clear register + * + */ +struct cam_fd_wrapper_regs { + uint32_t wrapper_version; + uint32_t cgc_disable; + uint32_t hw_stop; + uint32_t sw_reset; + uint32_t vbif_req_priority; + uint32_t vbif_priority_level; + uint32_t vbif_done_status; + uint32_t irq_mask; + uint32_t irq_status; + uint32_t irq_clear; +}; + +/** + * struct cam_fd_hw_errata_wa : FD HW Errata workaround enable/dsiable info + * + * @single_irq_only : Whether to enable only one irq at any time + * @ro_mode_enable_always : Whether to enable ro mode always + * @ro_mode_results_invalid : Whether results written directly into output + * memory by HW are valid or not + * @skip_reset : Whether to skip reset during init + */ +struct cam_fd_hw_errata_wa { + bool single_irq_only; + bool ro_mode_enable_always; + bool ro_mode_results_invalid; + bool skip_reset; +}; + +/** + * struct cam_fd_hw_results_prop : FD HW Results properties + * + * @max_faces : Maximum number of faces supported + * @per_face_entries : Number of register with properties for each face + * @raw_results_entries : Number of raw results entries for the full search + * @raw_results_available : Whether raw results available on this HW + * + */ +struct cam_fd_hw_results_prop { + uint32_t max_faces; + uint32_t per_face_entries; + uint32_t raw_results_entries; + bool raw_results_available; +}; + +/** + * struct cam_fd_hw_static_info : FD HW information based on HW version + * + * @core_version : Core version of FD HW + * @wrapper_version : Wrapper version of FD HW + * @core_regs : Register offset information for core registers + * @wrapper_regs : Register offset information for wrapper registers + * @results : Information about results available on this HW + * @enable_errata_wa : Errata workaround information + * @irq_mask : IRQ mask to enable + * @qos_priority : QoS priority setting for this chipset + * @qos_priority_level : QoS priority level setting for this chipset + * @supported_modes : Supported HW modes on this HW version + * @ro_mode_supported : Whether RO mode is supported on this HW + * + */ +struct cam_fd_hw_static_info { + struct cam_hw_version core_version; + struct cam_hw_version wrapper_version; + struct cam_fd_core_regs core_regs; + struct cam_fd_wrapper_regs wrapper_regs; + struct cam_fd_hw_results_prop results; + struct cam_fd_hw_errata_wa enable_errata_wa; + uint32_t irq_mask; + uint32_t qos_priority; + uint32_t qos_priority_level; + uint32_t supported_modes; + bool ro_mode_supported; +}; + +/** + * struct cam_fd_core : FD HW core data structure + * + * @hw_static_info : HW information specific to version + * @hw_caps : HW capabilities + * @core_state : Current HW state + * @processing_complete : Whether processing is complete + * @reset_complete : Whether reset is complete + * @halt_complete : Whether halt is complete + * @hw_req_private : Request that is being currently processed by HW + * @results_valid : Whether HW frame results are available to get + * @spin_lock : Mutex to protect shared data in hw layer + * @irq_cb : HW Manager callback information + * + */ +struct cam_fd_core { + struct cam_fd_hw_static_info *hw_static_info; + struct cam_fd_hw_caps hw_caps; + enum cam_fd_core_state core_state; + struct completion processing_complete; + struct completion reset_complete; + struct completion halt_complete; + struct cam_fd_hw_req_private *hw_req_private; + bool results_valid; + spinlock_t spin_lock; + struct cam_fd_hw_cmd_set_irq_cb irq_cb; +}; + +int cam_fd_hw_util_get_hw_caps(struct cam_hw_info *fd_hw, + struct cam_fd_hw_caps *hw_caps); +irqreturn_t cam_fd_hw_irq(int irq_num, void *data); + +int cam_fd_hw_get_hw_caps(void *hw_priv, void *get_hw_cap_args, + uint32_t arg_size); +int cam_fd_hw_init(void *hw_priv, void *init_hw_args, uint32_t arg_size); +int cam_fd_hw_deinit(void *hw_priv, void *deinit_hw_args, uint32_t arg_size); +int cam_fd_hw_reset(void *hw_priv, void *reset_core_args, uint32_t arg_size); +int cam_fd_hw_reserve(void *hw_priv, void *hw_reserve_args, uint32_t arg_size); +int cam_fd_hw_release(void *hw_priv, void *hw_release_args, uint32_t arg_size); +int cam_fd_hw_start(void *hw_priv, void *hw_start_args, uint32_t arg_size); +int cam_fd_hw_halt_reset(void *hw_priv, void *stop_args, uint32_t arg_size); +int cam_fd_hw_read(void *hw_priv, void *read_args, uint32_t arg_size); +int cam_fd_hw_write(void *hw_priv, void *write_args, uint32_t arg_size); +int cam_fd_hw_process_cmd(void *hw_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size); + +#endif /* _CAM_FD_HW_CORE_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_dev.c b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..7a42379512be0cbbff37ecd048e1eebdb302cfb1 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_dev.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "cam_subdev.h" +#include "cam_fd_hw_intf.h" +#include "cam_fd_hw_core.h" +#include "cam_fd_hw_soc.h" +#include "cam_fd_hw_v41.h" +#include "cam_fd_hw_v501.h" +#include "cam_fd_hw_v600.h" + +static char fd_dev_name[8]; + +static int cam_fd_hw_dev_probe(struct platform_device *pdev) +{ + struct cam_hw_info *fd_hw; + struct cam_hw_intf *fd_hw_intf; + struct cam_fd_core *fd_core; + const struct of_device_id *match_dev = NULL; + struct cam_fd_hw_static_info *hw_static_info = NULL; + int rc = 0; + uint32_t hw_idx; + struct cam_fd_hw_init_args init_args; + struct cam_fd_hw_deinit_args deinit_args; + + fd_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!fd_hw_intf) + return -ENOMEM; + + fd_hw = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!fd_hw) { + kfree(fd_hw_intf); + return -ENOMEM; + } + + fd_core = kzalloc(sizeof(struct cam_fd_core), GFP_KERNEL); + if (!fd_core) { + kfree(fd_hw); + kfree(fd_hw_intf); + return -ENOMEM; + } + of_property_read_u32(pdev->dev.of_node, + "cell-index", &hw_idx); + + fd_hw_intf->hw_priv = fd_hw; + fd_hw->core_info = fd_core; + fd_hw_intf->hw_idx = hw_idx; + + memset(fd_dev_name, 0, sizeof(fd_dev_name)); + snprintf(fd_dev_name, sizeof(fd_dev_name), + "fd%1u", fd_hw_intf->hw_idx); + + fd_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + fd_hw->soc_info.pdev = pdev; + fd_hw->soc_info.dev = &pdev->dev; + fd_hw->soc_info.dev_name = fd_dev_name; + fd_hw->open_count = 0; + mutex_init(&fd_hw->hw_mutex); + spin_lock_init(&fd_hw->hw_lock); + init_completion(&fd_hw->hw_complete); + + spin_lock_init(&fd_core->spin_lock); + init_completion(&fd_core->processing_complete); + init_completion(&fd_core->halt_complete); + init_completion(&fd_core->reset_complete); + + fd_hw_intf->hw_ops.get_hw_caps = cam_fd_hw_get_hw_caps; + fd_hw_intf->hw_ops.init = cam_fd_hw_init; + fd_hw_intf->hw_ops.deinit = cam_fd_hw_deinit; + fd_hw_intf->hw_ops.reset = cam_fd_hw_reset; + fd_hw_intf->hw_ops.reserve = cam_fd_hw_reserve; + fd_hw_intf->hw_ops.release = cam_fd_hw_release; + fd_hw_intf->hw_ops.start = cam_fd_hw_start; + fd_hw_intf->hw_ops.stop = cam_fd_hw_halt_reset; + fd_hw_intf->hw_ops.read = NULL; + fd_hw_intf->hw_ops.write = NULL; + fd_hw_intf->hw_ops.process_cmd = cam_fd_hw_process_cmd; + fd_hw_intf->hw_type = CAM_HW_FD; + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev || !match_dev->data) { + CAM_ERR(CAM_FD, "No Of_match data, %pK", match_dev); + rc = -EINVAL; + goto free_memory; + } + hw_static_info = (struct cam_fd_hw_static_info *)match_dev->data; + fd_core->hw_static_info = hw_static_info; + + CAM_DBG(CAM_FD, "HW Static Info : version core[%d.%d] wrapper[%d.%d]", + hw_static_info->core_version.major, + hw_static_info->core_version.minor, + hw_static_info->wrapper_version.major, + hw_static_info->wrapper_version.minor); + + rc = cam_fd_soc_init_resources(&fd_hw->soc_info, cam_fd_hw_irq, fd_hw); + if (rc) { + CAM_ERR(CAM_FD, "Failed to init soc, rc=%d", rc); + goto free_memory; + } + + memset(&init_args, 0x0, sizeof(init_args)); + memset(&deinit_args, 0x0, sizeof(deinit_args)); + init_args.reset_required = true; + rc = cam_fd_hw_init(fd_hw, &init_args, sizeof(init_args)); + if (rc) { + CAM_ERR(CAM_FD, "Failed to hw init, rc=%d", rc); + goto deinit_platform_res; + } + + rc = cam_fd_hw_util_get_hw_caps(fd_hw, &fd_core->hw_caps); + if (rc) { + CAM_ERR(CAM_FD, "Failed to get hw caps, rc=%d", rc); + goto deinit_hw; + } + + rc = cam_fd_hw_deinit(fd_hw, &deinit_args, sizeof(deinit_args)); + if (rc) { + CAM_ERR(CAM_FD, "Failed to deinit hw, rc=%d", rc); + goto deinit_platform_res; + } + + platform_set_drvdata(pdev, fd_hw_intf); + CAM_DBG(CAM_FD, "FD-%d probe successful", fd_hw_intf->hw_idx); + + return rc; + +deinit_hw: + if (cam_fd_hw_deinit(fd_hw, &deinit_args, sizeof(deinit_args))) + CAM_ERR(CAM_FD, "Failed in hw deinit"); +deinit_platform_res: + if (cam_fd_soc_deinit_resources(&fd_hw->soc_info)) + CAM_ERR(CAM_FD, "Failed in soc deinit"); + mutex_destroy(&fd_hw->hw_mutex); +free_memory: + kfree(fd_hw); + kfree(fd_hw_intf); + kfree(fd_core); + + return rc; +} + +static int cam_fd_hw_dev_remove(struct platform_device *pdev) +{ + int rc = 0; + struct cam_hw_intf *fd_hw_intf; + struct cam_hw_info *fd_hw; + struct cam_fd_core *fd_core; + + fd_hw_intf = platform_get_drvdata(pdev); + if (!fd_hw_intf) { + CAM_ERR(CAM_FD, "Invalid fd_hw_intf from pdev"); + return -EINVAL; + } + + fd_hw = fd_hw_intf->hw_priv; + if (!fd_hw) { + CAM_ERR(CAM_FD, "Invalid fd_hw from fd_hw_intf"); + rc = -ENODEV; + goto free_fd_hw_intf; + } + + fd_core = (struct cam_fd_core *)fd_hw->core_info; + if (!fd_core) { + CAM_ERR(CAM_FD, "Invalid fd_core from fd_hw"); + rc = -EINVAL; + goto deinit_platform_res; + } + + kfree(fd_core); + +deinit_platform_res: + rc = cam_fd_soc_deinit_resources(&fd_hw->soc_info); + if (rc) + CAM_ERR(CAM_FD, "Error in FD soc deinit, rc=%d", rc); + + mutex_destroy(&fd_hw->hw_mutex); + kfree(fd_hw); + +free_fd_hw_intf: + kfree(fd_hw_intf); + + return rc; +} + +static const struct of_device_id cam_fd_hw_dt_match[] = { + { + .compatible = "qcom,fd41", + .data = &cam_fd_wrapper120_core410_info, + }, + { + .compatible = "qcom,fd501", + .data = &cam_fd_wrapper200_core501_info, + }, + { + .compatible = "qcom,fd600", + .data = &cam_fd_wrapper200_core600_info, + }, + {} +}; +MODULE_DEVICE_TABLE(of, cam_fd_hw_dt_match); + +static struct platform_driver cam_fd_hw_driver = { + .probe = cam_fd_hw_dev_probe, + .remove = cam_fd_hw_dev_remove, + .driver = { + .name = "cam_fd_hw", + .owner = THIS_MODULE, + .of_match_table = cam_fd_hw_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_fd_hw_init_module(void) +{ + return platform_driver_register(&cam_fd_hw_driver); +} + +static void __exit cam_fd_hw_exit_module(void) +{ + platform_driver_unregister(&cam_fd_hw_driver); +} + +module_init(cam_fd_hw_init_module); +module_exit(cam_fd_hw_exit_module); +MODULE_DESCRIPTION("CAM FD HW driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_intf.h b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..85ec6fa390fff8ebafda9a282a16fb681e1f8047 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_intf.h @@ -0,0 +1,316 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_FD_HW_INTF_H_ +#define _CAM_FD_HW_INTF_H_ + +#include +#include +#include +#include +#include +#include + +#include "cam_io_util.h" +#include "cam_soc_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "cam_subdev.h" +#include "cam_cpas_api.h" +#include "cam_hw_mgr_intf.h" +#include "cam_debug_util.h" + +#define CAM_FD_MAX_IO_BUFFERS 5 +#define CAM_FD_MAX_HW_ENTRIES 5 +#define CAM_FD_HW_DUMP_TAG_MAX_LEN 32 +#define CAM_FD_HW_DUMP_NUM_WORDS 5 + +/** + * enum cam_fd_hw_type - Enum for FD HW type + * + * @CAM_HW_FD : FaceDetection HW type + */ +enum cam_fd_hw_type { + CAM_HW_FD, +}; + +/** + * enum cam_fd_hw_mode - Mode in which HW can run + * + * @CAM_FD_MODE_FACEDETECTION : Face Detection mode in which face search + * is done on the given frame + * @CAM_FD_MODE_PYRAMID : Pyramid mode where a pyramid image is generated + * from an input image + */ +enum cam_fd_hw_mode { + CAM_FD_MODE_FACEDETECTION = 0x1, + CAM_FD_MODE_PYRAMID = 0x2, +}; + +/** + * enum cam_fd_priority - FD priority levels + * + * @CAM_FD_PRIORITY_HIGH : Indicates high priority client, driver prioritizes + * frame requests coming from contexts with HIGH + * priority compared to context with normal priority + * @CAM_FD_PRIORITY_NORMAL : Indicates normal priority client + */ +enum cam_fd_priority { + CAM_FD_PRIORITY_HIGH = 0x0, + CAM_FD_PRIORITY_NORMAL, +}; + +/** + * enum cam_fd_hw_irq_type - FD HW IRQ types + * + * @CAM_FD_IRQ_FRAME_DONE : Indicates frame processing is finished + * @CAM_FD_IRQ_HALT_DONE : Indicates HW halt is finished + * @CAM_FD_IRQ_RESET_DONE : Indicates HW reset is finished + */ +enum cam_fd_hw_irq_type { + CAM_FD_IRQ_FRAME_DONE, + CAM_FD_IRQ_HALT_DONE, + CAM_FD_IRQ_RESET_DONE, +}; + +/** + * enum cam_fd_hw_cmd_type - FD HW layer custom commands + * + * @CAM_FD_HW_CMD_PRESTART : Command to process pre-start settings + * @CAM_FD_HW_CMD_FRAME_DONE : Command to process frame done settings + * @CAM_FD_HW_CMD_UPDATE_SOC : Command to process soc update + * @CAM_FD_HW_CMD_REGISTER_CALLBACK : Command to set hw mgr callback + * @CAM_FD_HW_CMD_MAX : Indicates max cmd + * @CAM_FD_HW_CMD_HW_DUMP : Command to dump fd hw information + */ +enum cam_fd_hw_cmd_type { + CAM_FD_HW_CMD_PRESTART, + CAM_FD_HW_CMD_FRAME_DONE, + CAM_FD_HW_CMD_UPDATE_SOC, + CAM_FD_HW_CMD_REGISTER_CALLBACK, + CAM_FD_HW_CMD_HW_DUMP, + CAM_FD_HW_CMD_MAX, +}; + +/** + * struct cam_fd_hw_io_buffer : FD HW IO Buffer information + * + * @valid : Whether this IO Buf configuration is valid + * @io_cfg : IO Configuration information + * @num_buf : Number planes in io_addr, cpu_addr array + * @io_addr : Array of IO address information for planes + * @cpu_addr : Array of CPU address information for planes + */ +struct cam_fd_hw_io_buffer { + bool valid; + struct cam_buf_io_cfg *io_cfg; + uint32_t num_buf; + uint64_t io_addr[CAM_PACKET_MAX_PLANES]; + uintptr_t cpu_addr[CAM_PACKET_MAX_PLANES]; +}; + +/** + * struct cam_fd_hw_req_private : FD HW layer's private information + * specific to a request + * + * @ctx_hw_private : FD HW layer's ctx specific private data + * @request_id : Request ID corresponding to this private information + * @get_raw_results : Whether to get raw results for this request + * @ro_mode_enabled : Whether RO mode is enabled for this request + * @fd_results : Pointer to save face detection results + * @raw_results : Pointer to save face detection raw results + */ +struct cam_fd_hw_req_private { + void *ctx_hw_private; + uint64_t request_id; + bool get_raw_results; + bool ro_mode_enabled; + struct cam_fd_results *fd_results; + uint32_t *raw_results; +}; + +/** + * struct cam_fd_hw_reserve_args : Reserve args for this HW context + * + * @hw_ctx : HW context for which reserve is requested + * @mode : Mode for which this reserve is requested + * @ctx_hw_private : Pointer to save HW layer's private information specific + * to this hw context. This has to be passed while calling + * further HW layer calls + */ +struct cam_fd_hw_reserve_args { + void *hw_ctx; + enum cam_fd_hw_mode mode; + void *ctx_hw_private; +}; + +/** + * struct cam_fd_hw_release_args : Release args for this HW context + * + * @hw_ctx : HW context for which release is requested + * @ctx_hw_private : HW layer's private information specific to this hw context + */ +struct cam_fd_hw_release_args { + void *hw_ctx; + void *ctx_hw_private; +}; + +/** + * struct cam_fd_hw_init_args : Init args for this HW context + * + * @hw_ctx : HW context for which init is requested + * @ctx_hw_private : HW layer's private information specific to this hw context + * @reset_required : Indicates if the reset is required during init or not + */ +struct cam_fd_hw_init_args { + void *hw_ctx; + void *ctx_hw_private; + bool reset_required; +}; + +/** + * struct cam_fd_hw_deinit_args : Deinit args for this HW context + * + * @hw_ctx : HW context for which deinit is requested + * @ctx_hw_private : HW layer's private information specific to this hw context + */ +struct cam_fd_hw_deinit_args { + void *hw_ctx; + void *ctx_hw_private; +}; + +/** + * struct cam_fd_hw_cmd_prestart_args : Prestart command args + * + * @hw_ctx : HW context which submitted this prestart + * @ctx_hw_private : HW layer's private information specific to + * this hw context + * @request_id : Request ID corresponds to this pre-start command + * @get_raw_results : Whether to get raw results for this request + * @input_buf : Input IO Buffer information for this request + * @output_buf : Output IO Buffer information for this request + * @cmd_buf_addr : Command buffer address to fill kmd commands + * @size : Size available in command buffer + * @pre_config_buf_size : Buffer size filled with commands by KMD that has + * to be inserted before umd commands + * @post_config_buf_size : Buffer size filled with commands by KMD that has + * to be inserted after umd commands + * @hw_req_private : HW layer's private information specific to + * this request + */ +struct cam_fd_hw_cmd_prestart_args { + void *hw_ctx; + void *ctx_hw_private; + uint64_t request_id; + bool get_raw_results; + struct cam_fd_hw_io_buffer input_buf[CAM_FD_MAX_IO_BUFFERS]; + struct cam_fd_hw_io_buffer output_buf[CAM_FD_MAX_IO_BUFFERS]; + uint32_t *cmd_buf_addr; + uint32_t size; + uint32_t pre_config_buf_size; + uint32_t post_config_buf_size; + struct cam_fd_hw_req_private hw_req_private; +}; + +/** + * struct cam_fd_hw_cmd_start_args : Start command args + * + * @hw_ctx : HW context which submitting start command + * @ctx_hw_private : HW layer's private information specific to + * this hw context + * @hw_req_private : HW layer's private information specific to + * this request + * @hw_update_entries : HW update entries corresponds to this request + * @num_hw_update_entries : Number of hw update entries + */ +struct cam_fd_hw_cmd_start_args { + void *hw_ctx; + void *ctx_hw_private; + struct cam_fd_hw_req_private *hw_req_private; + struct cam_hw_update_entry *hw_update_entries; + uint32_t num_hw_update_entries; +}; + +/** + * struct cam_fd_hw_stop_args : Stop command args + * + * @hw_ctx : HW context which submitting stop command + * @ctx_hw_private : HW layer's private information specific to this hw context + * @request_id : Request ID that need to be stopped + * @hw_req_private : HW layer's private information specific to this request + */ +struct cam_fd_hw_stop_args { + void *hw_ctx; + void *ctx_hw_private; + uint64_t request_id; + struct cam_fd_hw_req_private *hw_req_private; +}; + +/** + * struct cam_fd_hw_frame_done_args : Frame done command args + * + * @hw_ctx : HW context which submitting frame done request + * @ctx_hw_private : HW layer's private information specific to this hw context + * @request_id : Request ID that need to be stopped + * @hw_req_private : HW layer's private information specific to this request + */ +struct cam_fd_hw_frame_done_args { + void *hw_ctx; + void *ctx_hw_private; + uint64_t request_id; + struct cam_fd_hw_req_private *hw_req_private; +}; + +/** + * struct cam_fd_hw_reset_args : Reset command args + * + * @hw_ctx : HW context which submitting reset command + * @ctx_hw_private : HW layer's private information specific to this hw context + */ +struct cam_fd_hw_reset_args { + void *hw_ctx; + void *ctx_hw_private; +}; + +/** + * struct cam_fd_hw_cmd_set_irq_cb : Set IRQ callback command args + * + * @cam_fd_hw_mgr_cb : HW Mgr's callback pointer + * @data : HW Mgr's private data + */ +struct cam_fd_hw_cmd_set_irq_cb { + int (*cam_fd_hw_mgr_cb)(void *data, enum cam_fd_hw_irq_type irq_type); + void *data; +}; + +/** + * struct cam_fd_hw_dump_args : Args for dump request + * + * @request_id : Issue request id + * @offset : offset of the buffer + * @buf_len : Length of target buffer + * @cpu_addr : start address of the target buffer + */ +struct cam_fd_hw_dump_args { + uint64_t request_id; + size_t offset; + size_t buf_len; + uintptr_t cpu_addr; +}; + +/** + * struct cam_fd_hw_dump_header : fd hw dump header + * + * @tag : fd hw dump header tag + * @size : Size of data + * @word_size : size of each word + */ +struct cam_fd_hw_dump_header { + uint8_t tag[CAM_FD_HW_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + +#endif /* _CAM_FD_HW_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_soc.c b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..c3d5a68c69105a2b3456e335abf6e50cff5c606b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_soc.c @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "cam_fd_hw_core.h" +#include "cam_fd_hw_soc.h" + +static bool cam_fd_hw_util_cpas_callback(uint32_t handle, void *userdata, + struct cam_cpas_irq_data *irq_data) +{ + if (!irq_data) + return false; + + CAM_DBG(CAM_FD, "CPAS hdl=%d, udata=%pK, irq_type=%d", + handle, userdata, irq_data->irq_type); + + return false; +} + +static int cam_fd_hw_soc_util_setup_regbase_indices( + struct cam_hw_soc_info *soc_info) +{ + struct cam_fd_soc_private *soc_private = + (struct cam_fd_soc_private *)soc_info->soc_private; + uint32_t index; + int rc, i; + + for (i = 0; i < CAM_FD_REG_MAX; i++) + soc_private->regbase_index[i] = -1; + + if ((soc_info->num_mem_block > CAM_SOC_MAX_BLOCK) || + (soc_info->num_mem_block != CAM_FD_REG_MAX)) { + CAM_ERR(CAM_FD, "Invalid num_mem_block=%d", + soc_info->num_mem_block); + return -EINVAL; + } + + rc = cam_common_util_get_string_index(soc_info->mem_block_name, + soc_info->num_mem_block, "fd_core", &index); + if ((rc == 0) && (index < CAM_FD_REG_MAX)) { + soc_private->regbase_index[CAM_FD_REG_CORE] = index; + } else { + CAM_ERR(CAM_FD, "regbase not found for FD_CORE, rc=%d, %d %d", + rc, index, CAM_FD_REG_MAX); + return -EINVAL; + } + + rc = cam_common_util_get_string_index(soc_info->mem_block_name, + soc_info->num_mem_block, "fd_wrapper", &index); + if ((rc == 0) && (index < CAM_FD_REG_MAX)) { + soc_private->regbase_index[CAM_FD_REG_WRAPPER] = index; + } else { + CAM_ERR(CAM_FD, "regbase not found FD_WRAPPER, rc=%d, %d %d", + rc, index, CAM_FD_REG_MAX); + return -EINVAL; + } + + CAM_DBG(CAM_FD, "Reg indices : CORE=%d, WRAPPER=%d", + soc_private->regbase_index[CAM_FD_REG_CORE], + soc_private->regbase_index[CAM_FD_REG_WRAPPER]); + + return 0; +} + +void cam_fd_soc_register_write(struct cam_hw_soc_info *soc_info, + enum cam_fd_reg_base reg_base, uint32_t reg_offset, uint32_t reg_value) +{ + struct cam_fd_soc_private *soc_private = + (struct cam_fd_soc_private *)soc_info->soc_private; + int32_t reg_index = soc_private->regbase_index[reg_base]; + + CAM_DBG(CAM_FD, "FD_REG_WRITE: Base[%d] Offset[0x%8x] Value[0x%8x]", + reg_base, reg_offset, reg_value); + + cam_io_w_mb(reg_value, + soc_info->reg_map[reg_index].mem_base + reg_offset); +} + +uint32_t cam_fd_soc_register_read(struct cam_hw_soc_info *soc_info, + enum cam_fd_reg_base reg_base, uint32_t reg_offset) +{ + struct cam_fd_soc_private *soc_private = + (struct cam_fd_soc_private *)soc_info->soc_private; + int32_t reg_index = soc_private->regbase_index[reg_base]; + uint32_t reg_value; + + reg_value = cam_io_r_mb( + soc_info->reg_map[reg_index].mem_base + reg_offset); + + CAM_DBG(CAM_FD, "FD_REG_READ: Base[%d] Offset[0x%8x] Value[0x%8x]", + reg_base, reg_offset, reg_value); + + return reg_value; +} + +int cam_fd_soc_enable_resources(struct cam_hw_soc_info *soc_info) +{ + struct cam_fd_soc_private *soc_private = soc_info->soc_private; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + int rc; + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_LOWSVS_VOTE; + axi_vote.num_paths = 2; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_READ; + axi_vote.axi_path[0].camnoc_bw = 7200000; + axi_vote.axi_path[0].mnoc_ab_bw = 7200000; + axi_vote.axi_path[0].mnoc_ib_bw = 7200000; + axi_vote.axi_path[1].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[1].transac_type = CAM_AXI_TRANSACTION_WRITE; + axi_vote.axi_path[1].camnoc_bw = 7200000; + axi_vote.axi_path[1].mnoc_ab_bw = 7200000; + axi_vote.axi_path[1].mnoc_ib_bw = 7200000; + + + rc = cam_cpas_start(soc_private->cpas_handle, &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_FD, "Error in CPAS START, rc=%d", rc); + return -EFAULT; + } + + rc = cam_soc_util_enable_platform_resource(soc_info, true, CAM_SVS_VOTE, + true); + if (rc) { + CAM_ERR(CAM_FD, "Error enable platform failed, rc=%d", rc); + goto stop_cpas; + } + + return rc; + +stop_cpas: + if (cam_cpas_stop(soc_private->cpas_handle)) + CAM_ERR(CAM_FD, "Error in CPAS STOP"); + + return rc; +} + + +int cam_fd_soc_disable_resources(struct cam_hw_soc_info *soc_info) +{ + struct cam_fd_soc_private *soc_private; + int rc = 0; + + if (!soc_info) { + CAM_ERR(CAM_FD, "Invalid soc_info param"); + return -EINVAL; + } + soc_private = soc_info->soc_private; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) { + CAM_ERR(CAM_FD, "disable platform resources failed, rc=%d", rc); + return rc; + } + + rc = cam_cpas_stop(soc_private->cpas_handle); + if (rc) { + CAM_ERR(CAM_FD, "Error in CPAS STOP, handle=0x%x, rc=%d", + soc_private->cpas_handle, rc); + return rc; + } + + return rc; +} + +int cam_fd_soc_init_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t irq_handler, void *private_data) +{ + struct cam_fd_soc_private *soc_private; + struct cam_cpas_register_params cpas_register_param; + int rc; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc) { + CAM_ERR(CAM_FD, "Failed in get_dt_properties, rc=%d", rc); + return rc; + } + + rc = cam_soc_util_request_platform_resource(soc_info, irq_handler, + private_data); + if (rc) { + CAM_ERR(CAM_FD, "Failed in request_platform_resource rc=%d", + rc); + return rc; + } + + soc_private = kzalloc(sizeof(struct cam_fd_soc_private), GFP_KERNEL); + if (!soc_private) { + rc = -ENOMEM; + goto release_res; + } + soc_info->soc_private = soc_private; + + rc = cam_fd_hw_soc_util_setup_regbase_indices(soc_info); + if (rc) { + CAM_ERR(CAM_FD, "Failed in setup regbase, rc=%d", rc); + goto free_soc_private; + } + + memset(&cpas_register_param, 0, sizeof(cpas_register_param)); + strlcpy(cpas_register_param.identifier, "fd", CAM_HW_IDENTIFIER_LENGTH); + cpas_register_param.cell_index = soc_info->index; + cpas_register_param.dev = &soc_info->pdev->dev; + cpas_register_param.userdata = private_data; + cpas_register_param.cam_cpas_client_cb = cam_fd_hw_util_cpas_callback; + + rc = cam_cpas_register_client(&cpas_register_param); + if (rc) { + CAM_ERR(CAM_FD, "CPAS registration failed"); + goto free_soc_private; + } + soc_private->cpas_handle = cpas_register_param.client_handle; + CAM_DBG(CAM_FD, "CPAS handle=%d", soc_private->cpas_handle); + + return rc; + +free_soc_private: + kfree(soc_info->soc_private); + soc_info->soc_private = NULL; +release_res: + cam_soc_util_release_platform_resource(soc_info); + + return rc; +} + +int cam_fd_soc_deinit_resources(struct cam_hw_soc_info *soc_info) +{ + struct cam_fd_soc_private *soc_private = + (struct cam_fd_soc_private *)soc_info->soc_private; + int rc; + + rc = cam_cpas_unregister_client(soc_private->cpas_handle); + if (rc) + CAM_ERR(CAM_FD, "Unregister cpas failed, handle=%d, rc=%d", + soc_private->cpas_handle, rc); + + rc = cam_soc_util_release_platform_resource(soc_info); + if (rc) + CAM_ERR(CAM_FD, "release platform failed, rc=%d", rc); + + kfree(soc_info->soc_private); + soc_info->soc_private = NULL; + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_soc.h b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..b27ce09e36e65495cc7db304b72bff7b8b1dca3a --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_soc.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_FD_HW_SOC_H_ +#define _CAM_FD_HW_SOC_H_ + +#include "cam_soc_util.h" + +/** + * enum cam_fd_reg_base - Enum for FD register sets + * + * @CAM_FD_REG_CORE : Indicates FD Core register space + * @CAM_FD_REG_WRAPPER : Indicates FD Wrapper register space + * @CAM_FD_REG_MAX : Max number of register sets supported + */ +enum cam_fd_reg_base { + CAM_FD_REG_CORE, + CAM_FD_REG_WRAPPER, + CAM_FD_REG_MAX +}; + +/** + * struct cam_fd_soc_private : FD private SOC information + * + * @regbase_index : Mapping between Register base enum to register index in SOC + * @cpas_handle : CPAS handle + * + */ +struct cam_fd_soc_private { + int32_t regbase_index[CAM_FD_REG_MAX]; + uint32_t cpas_handle; +}; + +int cam_fd_soc_init_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t irq_handler, void *private_data); +int cam_fd_soc_deinit_resources(struct cam_hw_soc_info *soc_info); +int cam_fd_soc_enable_resources(struct cam_hw_soc_info *soc_info); +int cam_fd_soc_disable_resources(struct cam_hw_soc_info *soc_info); +uint32_t cam_fd_soc_register_read(struct cam_hw_soc_info *soc_info, + enum cam_fd_reg_base reg_base, uint32_t reg_offset); +void cam_fd_soc_register_write(struct cam_hw_soc_info *soc_info, + enum cam_fd_reg_base reg_base, uint32_t reg_offset, uint32_t reg_value); + +#endif /* _CAM_FD_HW_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v41.h b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v41.h new file mode 100644 index 0000000000000000000000000000000000000000..ad1fb0bc573717c7c07cafaeab17ba2c08de294e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v41.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_FD_HW_V41_H_ +#define _CAM_FD_HW_V41_H_ + +static struct cam_fd_hw_static_info cam_fd_wrapper120_core410_info = { + .core_version = { + .major = 4, + .minor = 1, + .incr = 0, + }, + .wrapper_version = { + .major = 1, + .minor = 2, + .incr = 0, + }, + .core_regs = { + .version = 0x38, + .control = 0x0, + .result_cnt = 0x4, + .result_addr = 0x20, + .image_addr = 0x24, + .work_addr = 0x28, + .ro_mode = 0x34, + .results_reg_base = 0x400, + .raw_results_reg_base = 0x800, + }, + .wrapper_regs = { + .wrapper_version = 0x0, + .cgc_disable = 0x4, + .hw_stop = 0x8, + .sw_reset = 0x10, + .vbif_req_priority = 0x20, + .vbif_priority_level = 0x24, + .vbif_done_status = 0x34, + .irq_mask = 0x50, + .irq_status = 0x54, + .irq_clear = 0x58, + }, + .results = { + .max_faces = 35, + .per_face_entries = 4, + .raw_results_available = true, + .raw_results_entries = 512, + }, + .enable_errata_wa = { + .single_irq_only = true, + .ro_mode_enable_always = true, + .ro_mode_results_invalid = true, + }, + .irq_mask = CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_FRAME_DONE) | + CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_HALT_DONE) | + CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_RESET_DONE), + .qos_priority = 4, + .qos_priority_level = 4, + .supported_modes = CAM_FD_MODE_FACEDETECTION | CAM_FD_MODE_PYRAMID, + .ro_mode_supported = true, +}; + +#endif /* _CAM_FD_HW_V41_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v501.h b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v501.h new file mode 100644 index 0000000000000000000000000000000000000000..d8b78d6e441466d86128a98b924c7ffce2dda457 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v501.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_FD_HW_V501_H_ +#define _CAM_FD_HW_V501_H_ + +static struct cam_fd_hw_static_info cam_fd_wrapper200_core501_info = { + .core_version = { + .major = 5, + .minor = 0, + .incr = 1, + }, + .wrapper_version = { + .major = 2, + .minor = 0, + .incr = 0, + }, + .core_regs = { + .version = 0x38, + .control = 0x0, + .result_cnt = 0x4, + .result_addr = 0x20, + .image_addr = 0x24, + .work_addr = 0x28, + .ro_mode = 0x34, + .results_reg_base = 0x400, + .raw_results_reg_base = 0x800, + }, + .wrapper_regs = { + .wrapper_version = 0x0, + .cgc_disable = 0x4, + .hw_stop = 0x8, + .sw_reset = 0x10, + .vbif_req_priority = 0x20, + .vbif_priority_level = 0x24, + .vbif_done_status = 0x34, + .irq_mask = 0x50, + .irq_status = 0x54, + .irq_clear = 0x58, + }, + .results = { + .max_faces = 35, + .per_face_entries = 4, + .raw_results_available = true, + .raw_results_entries = 512, + }, + .enable_errata_wa = { + .single_irq_only = true, + .ro_mode_enable_always = true, + .ro_mode_results_invalid = true, + .skip_reset = true, + }, + .irq_mask = CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_FRAME_DONE) | + CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_HALT_DONE) | + CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_RESET_DONE), + .qos_priority = 4, + .qos_priority_level = 4, + .supported_modes = CAM_FD_MODE_FACEDETECTION | CAM_FD_MODE_PYRAMID, + .ro_mode_supported = true, +}; + +#endif /* _CAM_FD_HW_V501_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v600.h b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v600.h new file mode 100644 index 0000000000000000000000000000000000000000..0c81cb642930acb58925b1b834da7bcc15ba48b7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v600.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_FD_HW_V600_H_ +#define _CAM_FD_HW_V600_H_ + +static struct cam_fd_hw_static_info cam_fd_wrapper200_core600_info = { + .core_version = { + .major = 6, + .minor = 0, + .incr = 0, + }, + .wrapper_version = { + .major = 2, + .minor = 0, + .incr = 0, + }, + .core_regs = { + .version = 0x38, + .control = 0x0, + .result_cnt = 0x4, + .result_addr = 0x20, + .image_addr = 0x24, + .work_addr = 0x28, + .ro_mode = 0x34, + .results_reg_base = 0x400, + }, + .wrapper_regs = { + .wrapper_version = 0x0, + .cgc_disable = 0x4, + .hw_stop = 0x8, + .sw_reset = 0x10, + .vbif_req_priority = 0x20, + .vbif_priority_level = 0x24, + .vbif_done_status = 0x34, + .irq_mask = 0x50, + .irq_status = 0x54, + .irq_clear = 0x58, + }, + .results = { + .max_faces = 35, + .per_face_entries = 4, + .raw_results_available = false, + }, + .enable_errata_wa = { + .single_irq_only = true, + .ro_mode_enable_always = true, + .ro_mode_results_invalid = true, + }, + .irq_mask = CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_FRAME_DONE) | + CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_HALT_DONE) | + CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_RESET_DONE), + .qos_priority = 4, + .qos_priority_level = 4, + .supported_modes = CAM_FD_MODE_FACEDETECTION | CAM_FD_MODE_PYRAMID, + .ro_mode_supported = true, +}; + +#endif /* _CAM_FD_HW_V600_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_icp/Makefile b/techpack/camera-bengal/drivers/cam_icp/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..fbf2e7df5a7de4b4fd6a16f44b8d312c76593f67 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/fw_inc +ccflags-y += -I$(srctree)/techpack/camera-bengal +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += icp_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_icp_subdev.o cam_icp_context.o hfi.o diff --git a/techpack/camera-bengal/drivers/cam_icp/cam_icp_context.c b/techpack/camera-bengal/drivers/cam_icp/cam_icp_context.c new file mode 100644 index 0000000000000000000000000000000000000000..4d6e0ab352a12cd519366e3a46d9ab382896ca65 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/cam_icp_context.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "cam_node.h" +#include "cam_context.h" +#include "cam_context_utils.h" +#include "cam_icp_context.h" +#include "cam_req_mgr_util.h" +#include "cam_mem_mgr.h" +#include "cam_trace.h" +#include "cam_debug_util.h" +#include "cam_packet_util.h" + +static const char icp_dev_name[] = "cam-icp"; + +static int cam_icp_context_dump_active_request(void *data, unsigned long iova, + uint32_t buf_info) +{ + struct cam_context *ctx = (struct cam_context *)data; + struct cam_ctx_request *req = NULL; + struct cam_ctx_request *req_temp = NULL; + struct cam_hw_mgr_dump_pf_data *pf_dbg_entry = NULL; + int rc = 0; + bool b_mem_found = false; + + if (!ctx) { + CAM_ERR(CAM_ICP, "Invalid ctx"); + return -EINVAL; + } + + if (ctx->state < CAM_CTX_ACQUIRED || ctx->state > CAM_CTX_ACTIVATED) { + CAM_ERR(CAM_ICP, "Invalid state icp ctx %d state %d", + ctx->ctx_id, ctx->state); + goto end; + } + + CAM_INFO(CAM_ICP, "iommu fault for icp ctx %d state %d", + ctx->ctx_id, ctx->state); + + list_for_each_entry_safe(req, req_temp, + &ctx->active_req_list, list) { + pf_dbg_entry = &(req->pf_data); + CAM_INFO(CAM_ICP, "req_id : %lld", req->request_id); + + rc = cam_context_dump_pf_info_to_hw(ctx, pf_dbg_entry->packet, + iova, buf_info, &b_mem_found); + if (rc) + CAM_ERR(CAM_ICP, "Failed to dump pf info"); + + if (b_mem_found) + CAM_ERR(CAM_ICP, "Found page fault in req %lld %d", + req->request_id, rc); + } + +end: + return rc; +} + +static int __cam_icp_acquire_dev_in_available(struct cam_context *ctx, + struct cam_acquire_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_acquire_dev_to_hw(ctx, cmd); + if (!rc) { + ctx->state = CAM_CTX_ACQUIRED; + trace_cam_context_state("ICP", ctx); + } + + return rc; +} + +static int __cam_icp_release_dev_in_acquired(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_release_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_ICP, "Unable to release device"); + + ctx->state = CAM_CTX_AVAILABLE; + trace_cam_context_state("ICP", ctx); + return rc; +} + +static int __cam_icp_start_dev_in_acquired(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_start_dev_to_hw(ctx, cmd); + if (!rc) { + ctx->state = CAM_CTX_READY; + trace_cam_context_state("ICP", ctx); + } + + return rc; +} + +static int __cam_icp_dump_dev_in_ready( + struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc; + + rc = cam_context_dump_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_ICP, "Failed to dump device"); + + return rc; +} + +static int __cam_icp_flush_dev_in_ready(struct cam_context *ctx, + struct cam_flush_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_flush_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_ICP, "Failed to flush device"); + + return rc; +} + +static int __cam_icp_config_dev_in_ready(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + int rc; + size_t len; + uintptr_t packet_addr; + struct cam_packet *packet; + size_t remain_len = 0; + + rc = cam_mem_get_cpu_buf((int32_t) cmd->packet_handle, + &packet_addr, &len); + if (rc) { + CAM_ERR(CAM_ICP, "[%s][%d] Can not get packet address", + ctx->dev_name, ctx->ctx_id); + rc = -EINVAL; + return rc; + } + + remain_len = len; + if ((len < sizeof(struct cam_packet)) || + (cmd->offset >= (len - sizeof(struct cam_packet)))) { + CAM_ERR(CAM_CTXT, + "Invalid offset, len: %zu cmd offset: %llu sizeof packet: %zu", + len, cmd->offset, sizeof(struct cam_packet)); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); + return -EINVAL; + } + + remain_len -= (size_t)cmd->offset; + packet = (struct cam_packet *) ((uint8_t *)packet_addr + + (uint32_t)cmd->offset); + + rc = cam_packet_util_validate_packet(packet, remain_len); + if (rc) { + CAM_ERR(CAM_CTXT, "Invalid packet params, remain length: %zu", + remain_len); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); + return rc; + } + + if (((packet->header.op_code & 0xff) == + CAM_ICP_OPCODE_IPE_SETTINGS) || + ((packet->header.op_code & 0xff) == + CAM_ICP_OPCODE_BPS_SETTINGS)) + rc = cam_context_config_dev_to_hw(ctx, cmd); + else + rc = cam_context_prepare_dev_to_hw(ctx, cmd); + + if (rc) + CAM_ERR(CAM_ICP, "Failed to prepare device"); + + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); + return rc; +} + +static int __cam_icp_stop_dev_in_ready(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_stop_dev_to_hw(ctx); + if (rc) + CAM_ERR(CAM_ICP, "Failed to stop device"); + + ctx->state = CAM_CTX_ACQUIRED; + trace_cam_context_state("ICP", ctx); + return rc; +} + +static int __cam_icp_release_dev_in_ready(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc; + + rc = __cam_icp_stop_dev_in_ready(ctx, NULL); + if (rc) + CAM_ERR(CAM_ICP, "Failed to stop device"); + + rc = __cam_icp_release_dev_in_acquired(ctx, cmd); + if (rc) + CAM_ERR(CAM_ICP, "Failed to release device"); + + return rc; +} + +static int __cam_icp_handle_buf_done_in_ready(void *ctx, + uint32_t evt_id, void *done) +{ + return cam_context_buf_done_from_hw(ctx, done, evt_id); +} + +static struct cam_ctx_ops + cam_icp_ctx_state_machine[CAM_CTX_STATE_MAX] = { + /* Uninit */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Available */ + { + .ioctl_ops = { + .acquire_dev = __cam_icp_acquire_dev_in_available, + }, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Acquired */ + { + .ioctl_ops = { + .release_dev = __cam_icp_release_dev_in_acquired, + .start_dev = __cam_icp_start_dev_in_acquired, + .config_dev = __cam_icp_config_dev_in_ready, + .flush_dev = __cam_icp_flush_dev_in_ready, + .dump_dev = __cam_icp_dump_dev_in_ready, + }, + .crm_ops = {}, + .irq_ops = __cam_icp_handle_buf_done_in_ready, + .pagefault_ops = cam_icp_context_dump_active_request, + }, + /* Ready */ + { + .ioctl_ops = { + .stop_dev = __cam_icp_stop_dev_in_ready, + .release_dev = __cam_icp_release_dev_in_ready, + .config_dev = __cam_icp_config_dev_in_ready, + .flush_dev = __cam_icp_flush_dev_in_ready, + .dump_dev = __cam_icp_dump_dev_in_ready, + }, + .crm_ops = {}, + .irq_ops = __cam_icp_handle_buf_done_in_ready, + .pagefault_ops = cam_icp_context_dump_active_request, + }, + /* Flushed */ + {}, + /* Activated */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + .pagefault_ops = cam_icp_context_dump_active_request, + }, +}; + +int cam_icp_context_init(struct cam_icp_context *ctx, + struct cam_hw_mgr_intf *hw_intf, uint32_t ctx_id) +{ + int rc; + + if ((!ctx) || (!ctx->base) || (!hw_intf)) { + CAM_ERR(CAM_ICP, "Invalid params: %pK %pK", ctx, hw_intf); + rc = -EINVAL; + goto err; + } + + rc = cam_context_init(ctx->base, icp_dev_name, CAM_ICP, ctx_id, + NULL, hw_intf, ctx->req_base, CAM_CTX_REQ_MAX); + if (rc) { + CAM_ERR(CAM_ICP, "Camera Context Base init failed"); + goto err; + } + + ctx->base->state_machine = cam_icp_ctx_state_machine; + ctx->base->ctx_priv = ctx; + ctx->ctxt_to_hw_map = NULL; + +err: + return rc; +} + +int cam_icp_context_deinit(struct cam_icp_context *ctx) +{ + if ((!ctx) || (!ctx->base)) { + CAM_ERR(CAM_ICP, "Invalid params: %pK", ctx); + return -EINVAL; + } + + cam_context_deinit(ctx->base); + memset(ctx, 0, sizeof(*ctx)); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_icp/cam_icp_context.h b/techpack/camera-bengal/drivers/cam_icp/cam_icp_context.h new file mode 100644 index 0000000000000000000000000000000000000000..edd8bd5617c9208fbd7f4aee574238cf49c40008 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/cam_icp_context.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_ICP_CONTEXT_H_ +#define _CAM_ICP_CONTEXT_H_ + +#include "cam_context.h" + +/** + * struct cam_icp_context - icp context + * @base: icp context object + * @state_machine: state machine for ICP context + * @req_base: common request structure + * @state: icp context state + * @ctxt_to_hw_map: context to FW handle mapping + */ +struct cam_icp_context { + struct cam_context *base; + struct cam_ctx_ops *state_machine; + struct cam_ctx_request req_base[CAM_CTX_REQ_MAX]; + uint32_t state; + void *ctxt_to_hw_map; +}; + +/** + * cam_icp_context_init() - ICP context init + * @ctx: Pointer to context + * @hw_intf: Pointer to ICP hardware interface + * @ctx_id: ID for this context + */ +int cam_icp_context_init(struct cam_icp_context *ctx, + struct cam_hw_mgr_intf *hw_intf, uint32_t ctx_id); + +/** + * cam_icp_context_deinit() - ICP context deinit + * @ctx: Pointer to context + */ +int cam_icp_context_deinit(struct cam_icp_context *ctx); + +#endif /* _CAM_ICP_CONTEXT_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_icp/cam_icp_subdev.c b/techpack/camera-bengal/drivers/cam_icp/cam_icp_subdev.c new file mode 100644 index 0000000000000000000000000000000000000000..128b171f8659fe9d0019b923516f279c7e594190 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/cam_icp_subdev.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_req_mgr_dev.h" +#include "cam_subdev.h" +#include "cam_node.h" +#include "cam_context.h" +#include "cam_icp_context.h" +#include "cam_hw_mgr_intf.h" +#include "cam_icp_hw_mgr_intf.h" +#include "cam_debug_util.h" +#include "cam_smmu_api.h" + +#define CAM_ICP_DEV_NAME "cam-icp" + +struct cam_icp_subdev { + struct cam_subdev sd; + struct cam_node *node; + struct cam_context ctx[CAM_ICP_CTX_MAX]; + struct cam_icp_context ctx_icp[CAM_ICP_CTX_MAX]; + struct mutex icp_lock; + int32_t open_cnt; + int32_t reserved; +}; + +static struct cam_icp_subdev g_icp_dev; + +static const struct of_device_id cam_icp_dt_match[] = { + {.compatible = "qcom,cam-icp"}, + {} +}; + +static void cam_icp_dev_iommu_fault_handler( + struct iommu_domain *domain, struct device *dev, unsigned long iova, + int flags, void *token, uint32_t buf_info) +{ + int i = 0; + struct cam_node *node = NULL; + + if (!token) { + CAM_ERR(CAM_ICP, "invalid token in page handler cb"); + return; + } + + node = (struct cam_node *)token; + + for (i = 0; i < node->ctx_size; i++) + cam_context_dump_pf_info(&(node->ctx_list[i]), iova, + buf_info); +} + +static int cam_icp_subdev_open(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct cam_hw_mgr_intf *hw_mgr_intf = NULL; + struct cam_node *node = v4l2_get_subdevdata(sd); + int rc = 0; + + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); + + mutex_lock(&g_icp_dev.icp_lock); + if (g_icp_dev.open_cnt >= 1) { + CAM_ERR(CAM_ICP, "ICP subdev is already opened"); + rc = -EALREADY; + goto end; + } + + if (!node) { + CAM_ERR(CAM_ICP, "Invalid args"); + rc = -EINVAL; + goto end; + } + + hw_mgr_intf = &node->hw_mgr_intf; + rc = hw_mgr_intf->hw_open(hw_mgr_intf->hw_mgr_priv, NULL); + if (rc < 0) { + CAM_ERR(CAM_ICP, "FW download failed"); + goto end; + } + g_icp_dev.open_cnt++; +end: + mutex_unlock(&g_icp_dev.icp_lock); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); + return rc; +} + +static int cam_icp_subdev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + int rc = 0; + struct cam_hw_mgr_intf *hw_mgr_intf = NULL; + struct cam_node *node = v4l2_get_subdevdata(sd); + + mutex_lock(&g_icp_dev.icp_lock); + if (g_icp_dev.open_cnt <= 0) { + CAM_DBG(CAM_ICP, "ICP subdev is already closed"); + rc = -EINVAL; + goto end; + } + g_icp_dev.open_cnt--; + if (!node) { + CAM_ERR(CAM_ICP, "Invalid args"); + rc = -EINVAL; + goto end; + } + + hw_mgr_intf = &node->hw_mgr_intf; + if (!hw_mgr_intf) { + CAM_ERR(CAM_ICP, "hw_mgr_intf is not initialized"); + rc = -EINVAL; + goto end; + } + + rc = cam_node_shutdown(node); + if (rc < 0) { + CAM_ERR(CAM_ICP, "HW close failed"); + goto end; + } + +end: + mutex_unlock(&g_icp_dev.icp_lock); + return 0; +} + +const struct v4l2_subdev_internal_ops cam_icp_subdev_internal_ops = { + .open = cam_icp_subdev_open, + .close = cam_icp_subdev_close, +}; + +static int cam_icp_probe(struct platform_device *pdev) +{ + int rc = 0, i = 0; + struct cam_node *node; + struct cam_hw_mgr_intf *hw_mgr_intf; + int iommu_hdl = -1; + + if (!pdev) { + CAM_ERR(CAM_ICP, "pdev is NULL"); + return -EINVAL; + } + + g_icp_dev.sd.pdev = pdev; + g_icp_dev.sd.internal_ops = &cam_icp_subdev_internal_ops; + rc = cam_subdev_probe(&g_icp_dev.sd, pdev, CAM_ICP_DEV_NAME, + CAM_ICP_DEVICE_TYPE); + if (rc) { + CAM_ERR(CAM_ICP, "ICP cam_subdev_probe failed"); + goto probe_fail; + } + + node = (struct cam_node *) g_icp_dev.sd.token; + + hw_mgr_intf = kzalloc(sizeof(*hw_mgr_intf), GFP_KERNEL); + if (!hw_mgr_intf) { + rc = -EINVAL; + goto hw_alloc_fail; + } + + rc = cam_icp_hw_mgr_init(pdev->dev.of_node, (uint64_t *)hw_mgr_intf, + &iommu_hdl); + if (rc) { + CAM_ERR(CAM_ICP, "ICP HW manager init failed: %d", rc); + goto hw_init_fail; + } + + for (i = 0; i < CAM_ICP_CTX_MAX; i++) { + g_icp_dev.ctx_icp[i].base = &g_icp_dev.ctx[i]; + rc = cam_icp_context_init(&g_icp_dev.ctx_icp[i], + hw_mgr_intf, i); + if (rc) { + CAM_ERR(CAM_ICP, "ICP context init failed"); + goto ctx_fail; + } + } + + rc = cam_node_init(node, hw_mgr_intf, g_icp_dev.ctx, + CAM_ICP_CTX_MAX, CAM_ICP_DEV_NAME); + if (rc) { + CAM_ERR(CAM_ICP, "ICP node init failed"); + goto ctx_fail; + } + + cam_smmu_set_client_page_fault_handler(iommu_hdl, + cam_icp_dev_iommu_fault_handler, node); + + g_icp_dev.open_cnt = 0; + mutex_init(&g_icp_dev.icp_lock); + + CAM_DBG(CAM_ICP, "ICP probe complete"); + + return rc; + +ctx_fail: + for (--i; i >= 0; i--) + cam_icp_context_deinit(&g_icp_dev.ctx_icp[i]); +hw_init_fail: + kfree(hw_mgr_intf); +hw_alloc_fail: + cam_subdev_remove(&g_icp_dev.sd); +probe_fail: + return rc; +} + +static int cam_icp_remove(struct platform_device *pdev) +{ + int i; + struct v4l2_subdev *sd; + struct cam_subdev *subdev; + + if (!pdev) { + CAM_ERR(CAM_ICP, "pdev is NULL"); + return -ENODEV; + } + + sd = platform_get_drvdata(pdev); + if (!sd) { + CAM_ERR(CAM_ICP, "V4l2 subdev is NULL"); + return -ENODEV; + } + + subdev = v4l2_get_subdevdata(sd); + if (!subdev) { + CAM_ERR(CAM_ICP, "cam subdev is NULL"); + return -ENODEV; + } + + for (i = 0; i < CAM_ICP_CTX_MAX; i++) + cam_icp_context_deinit(&g_icp_dev.ctx_icp[i]); + cam_node_deinit(g_icp_dev.node); + cam_subdev_remove(&g_icp_dev.sd); + mutex_destroy(&g_icp_dev.icp_lock); + + return 0; +} + +static struct platform_driver cam_icp_driver = { + .probe = cam_icp_probe, + .remove = cam_icp_remove, + .driver = { + .name = "cam_icp", + .owner = THIS_MODULE, + .of_match_table = cam_icp_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_icp_init_module(void) +{ + return platform_driver_register(&cam_icp_driver); +} + +static void __exit cam_icp_exit_module(void) +{ + platform_driver_unregister(&cam_icp_driver); +} +module_init(cam_icp_init_module); +module_exit(cam_icp_exit_module); +MODULE_DESCRIPTION("MSM ICP driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_icp/fw_inc/hfi_intf.h b/techpack/camera-bengal/drivers/cam_icp/fw_inc/hfi_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..afd42d23b9fb43bd4e2070864da07efd3078df13 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/fw_inc/hfi_intf.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _HFI_INTF_H_ +#define _HFI_INTF_H_ + +#include + +/** + * struct hfi_mem + * @len: length of memory + * @kva: kernel virtual address + * @iova: IO virtual address + * @reserved: reserved field + */ +struct hfi_mem { + uint64_t len; + uintptr_t kva; + uint32_t iova; + uint32_t reserved; +}; + +/** + * struct hfi_mem_info + * @qtbl: qtable hfi memory + * @cmd_q: command queue hfi memory for host to firmware communication + * @msg_q: message queue hfi memory for firmware to host communication + * @dbg_q: debug queue hfi memory for firmware debug information + * @sfr_buf: buffer for subsystem failure reason[SFR] + * @sec_heap: secondary heap hfi memory for firmware + * @qdss: qdss mapped memory for fw + * @io_mem: io memory info + * @io_mem2: 2nd io memory info + * @icp_base: icp base address + */ +struct hfi_mem_info { + struct hfi_mem qtbl; + struct hfi_mem cmd_q; + struct hfi_mem msg_q; + struct hfi_mem dbg_q; + struct hfi_mem sfr_buf; + struct hfi_mem sec_heap; + struct hfi_mem shmem; + struct hfi_mem qdss; + struct hfi_mem io_mem; + struct hfi_mem io_mem2; + void __iomem *icp_base; +}; + +/** + * hfi_write_cmd() - function for hfi write + * @cmd_ptr: pointer to command data for hfi write + * + * Returns success(zero)/failure(non zero) + */ +int hfi_write_cmd(void *cmd_ptr); + +/** + * hfi_read_message() - function for hfi read + * @pmsg: buffer to place read message for hfi queue + * @q_id: queue id + * @words_read: total number of words read from the queue + * returned as output to the caller + * + * Returns success(zero)/failure(non zero) + */ +int hfi_read_message(uint32_t *pmsg, uint8_t q_id, uint32_t *words_read); + +/** + * hfi_init() - function initialize hfi after firmware download + * @event_driven_mode: event mode + * @hfi_mem: hfi memory info + * @icp_base: icp base address + * @debug: debug flag + * + * Returns success(zero)/failure(non zero) + */ +int cam_hfi_init(uint8_t event_driven_mode, struct hfi_mem_info *hfi_mem, + void *__iomem icp_base, bool debug); + +/** + * hfi_get_hw_caps() - hardware capabilities from firmware + * @query_caps: holds query information from hfi + * + * Returns success(zero)/failure(non zero) + */ +int hfi_get_hw_caps(void *query_caps); + +/** + * hfi_send_system_cmd() - send hfi system command to firmware + * @type: type of system command + * @data: command data + * @size: size of command data + */ +void hfi_send_system_cmd(uint32_t type, uint64_t data, uint32_t size); + +/** + * cam_hfi_enable_cpu() - enable A5 CPU + * @icp_base: icp base address + */ +void cam_hfi_enable_cpu(void __iomem *icp_base); + +/** + * cam_hfi_disable_cpu() - disable A5 CPU + * @icp_base: icp base address + */ +void cam_hfi_disable_cpu(void __iomem *icp_base); + +/** + * cam_hfi_deinit() - cleanup HFI + */ +void cam_hfi_deinit(void __iomem *icp_base); +/** + * hfi_set_debug_level() - set debug level + * @a5_dbg_type: 1 for debug_q & 2 for qdss + * @lvl: FW debug message level + */ +int hfi_set_debug_level(u64 a5_dbg_type, uint32_t lvl); + +/** + * hfi_set_fw_dump_level() - set firmware dump level + * @lvl: level of firmware dump level + */ +int hfi_set_fw_dump_level(uint32_t lvl); + +/** + * hfi_enable_ipe_bps_pc() - Enable interframe pc + * Host sends a command to firmware to enable interframe + * power collapse for IPE and BPS hardware. + * + * @enable: flag to enable/disable + * @core_info: Core information to firmware + */ +int hfi_enable_ipe_bps_pc(bool enable, uint32_t core_info); + +/** + * hfi_cmd_ubwc_config_ext() - UBWC configuration to firmware + * @ubwc_ipe_cfg: UBWC ipe fetch/write configuration params + * @ubwc_bps_cfg: UBWC bps fetch/write configuration params + */ +int hfi_cmd_ubwc_config_ext(uint32_t *ubwc_ipe_cfg, + uint32_t *ubwc_bps_cfg); + +/** + * hfi_cmd_ubwc_config() - UBWC configuration to firmware + * for older targets + * @ubwc_cfg: UBWC configuration parameters + */ +int hfi_cmd_ubwc_config(uint32_t *ubwc_cfg); + +/** + * cam_hfi_resume() - function to resume + * @hfi_mem: hfi memory info + * @icp_base: icp base address + * @debug: debug flag + * + * Returns success(zero)/failure(non zero) + */ +int cam_hfi_resume(struct hfi_mem_info *hfi_mem, + void __iomem *icp_base, bool debug); + +/** + * cam_hfi_queue_dump() - utility function to dump hfi queues + */ +void cam_hfi_queue_dump(void); + + +#endif /* _HFI_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_icp/fw_inc/hfi_reg.h b/techpack/camera-bengal/drivers/cam_icp/fw_inc/hfi_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..df4ae01d7ef2a440e112649de288cb2f598cad1c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/fw_inc/hfi_reg.h @@ -0,0 +1,338 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_HFI_REG_H_ +#define _CAM_HFI_REG_H_ + +#include +#include "hfi_intf.h" + + +/* start of ICP CSR registers */ +#define HFI_REG_A5_HW_VERSION 0x0 +#define HFI_REG_A5_CSR_NSEC_RESET 0x4 +#define HFI_REG_A5_CSR_A5_CONTROL 0x8 +#define HFI_REG_A5_CSR_ETM 0xC +#define HFI_REG_A5_CSR_A2HOSTINTEN 0x10 +#define HFI_REG_A5_CSR_A2HOSTINT 0x14 +#define HFI_REG_A5_CSR_A2HOSTINTCLR 0x18 +#define HFI_REG_A5_CSR_A2HOSTINTSTATUS 0x1C +#define HFI_REG_A5_CSR_A2HOSTINTSET 0x20 +#define HFI_REG_A5_CSR_HOST2ICPINT 0x30 +#define HFI_REG_A5_CSR_A5_STATUS 0x200 +#define HFI_REG_A5_QGIC2_LM_ID 0x204 +#define HFI_REG_A5_SPARE 0x400 + +/* general purpose registers from */ +#define HFI_REG_FW_VERSION 0x44 +#define HFI_REG_HOST_ICP_INIT_REQUEST 0x48 +#define HFI_REG_ICP_HOST_INIT_RESPONSE 0x4C +#define HFI_REG_SHARED_MEM_PTR 0x50 +#define HFI_REG_SHARED_MEM_SIZE 0x54 +#define HFI_REG_QTBL_PTR 0x58 +#define HFI_REG_UNCACHED_HEAP_PTR 0x5C +#define HFI_REG_UNCACHED_HEAP_SIZE 0x60 +#define HFI_REG_QDSS_IOVA 0x6C +#define HFI_REG_SFR_PTR 0x68 +#define HFI_REG_QDSS_IOVA_SIZE 0x70 +#define HFI_REG_IO_REGION_IOVA 0x74 +#define HFI_REG_IO_REGION_SIZE 0x78 +#define HFI_REG_IO2_REGION_IOVA 0x7C +#define HFI_REG_IO2_REGION_SIZE 0x80 + +/* end of ICP CSR registers */ + +/* flags for ICP CSR registers */ +#define ICP_FLAG_CSR_WAKE_UP_EN (1 << 4) +#define ICP_FLAG_CSR_A5_EN (1 << 9) +#define ICP_CSR_EN_CLKGATE_WFI (1 << 12) +#define ICP_CSR_EDBGRQ (1 << 14) +#define ICP_CSR_DBGSWENABLE (1 << 22) +#define ICP_CSR_A5_STATUS_WFI (1 << 7) + +#define ICP_FLAG_A5_CTRL_DBG_EN (ICP_FLAG_CSR_WAKE_UP_EN|\ + ICP_FLAG_CSR_A5_EN|\ + ICP_CSR_EDBGRQ|\ + ICP_CSR_DBGSWENABLE) + +#define ICP_FLAG_A5_CTRL_EN (ICP_FLAG_CSR_WAKE_UP_EN|\ + ICP_FLAG_CSR_A5_EN|\ + ICP_CSR_EN_CLKGATE_WFI) + +/* start of Queue table and queues */ +#define MAX_ICP_HFI_QUEUES 4 +#define ICP_QHDR_TX_TYPE_MASK 0xFF000000 +#define ICP_QHDR_RX_TYPE_MASK 0x00FF0000 +#define ICP_QHDR_PRI_TYPE_MASK 0x0000FF00 +#define ICP_QHDR_Q_ID_MASK 0x000000FF + +#define ICP_CMD_Q_SIZE_IN_BYTES 4096 +#define ICP_MSG_Q_SIZE_IN_BYTES 4096 +#define ICP_DBG_Q_SIZE_IN_BYTES 102400 +#define ICP_MSG_SFR_SIZE_IN_BYTES 4096 + +#define ICP_SHARED_MEM_IN_BYTES (1024 * 1024) +#define ICP_UNCACHED_HEAP_SIZE_IN_BYTES (2 * 1024 * 1024) +#define ICP_HFI_MAX_PKT_SIZE_IN_WORDS 25600 +#define ICP_HFI_MAX_PKT_SIZE_MSGQ_IN_WORDS 1024 + +#define ICP_HFI_QTBL_HOSTID1 0x01000000 +#define ICP_HFI_QTBL_STATUS_ENABLED 0x00000001 +#define ICP_HFI_NUMBER_OF_QS 3 +#define ICP_HFI_NUMBER_OF_ACTIVE_QS 3 +#define ICP_HFI_QTBL_OFFSET 0 +#define ICP_HFI_VAR_SIZE_PKT 0 +#define ICP_HFI_MAX_MSG_SIZE_IN_WORDS 128 + + +/* Queue Header type masks. Use these to access bitfields in qhdr_type */ +#define HFI_MASK_QHDR_TX_TYPE 0xFF000000 +#define HFI_MASK_QHDR_RX_TYPE 0x00FF0000 +#define HFI_MASK_QHDR_PRI_TYPE 0x0000FF00 +#define HFI_MASK_QHDR_Q_ID_TYPE 0x000000FF + + +#define TX_EVENT_DRIVEN_MODE_1 0 +#define RX_EVENT_DRIVEN_MODE_1 0 +#define TX_EVENT_DRIVEN_MODE_2 0x01000000 +#define RX_EVENT_DRIVEN_MODE_2 0x00010000 +#define TX_EVENT_POLL_MODE_2 0x02000000 +#define RX_EVENT_POLL_MODE_2 0x00020000 +#define U32_OFFSET 0x1 +#define BYTE_WORD_SHIFT 2 + +/** + * @INVALID: Invalid state + * @HFI_DEINIT: HFI is not initialized yet + * @HFI_INIT: HFI is initialized + * @HFI_READY: HFI is ready to send/receive commands/messages + */ +enum hfi_state { + HFI_DEINIT, + HFI_INIT, + HFI_READY +}; + +/** + * @RESET: init success + * @SET: init failed + */ +enum reg_settings { + RESET, + SET, + SET_WM = 1024 +}; + +/** + * @INTR_DISABLE: Disable interrupt + * @INTR_ENABLE: Enable interrupt + * @INTR_ENABLE_WD0: Enable WD0 + * @INTR_ENABLE_WD1: Enable WD1 + */ +enum intr_status { + INTR_DISABLE, + INTR_ENABLE, + INTR_ENABLE_WD0, + INTR_ENABLE_WD1 = 0x4 +}; + +/** + * @ICP_INIT_RESP_RESET: reset init state + * @ICP_INIT_RESP_SUCCESS: init success + * @ICP_INIT_RESP_FAILED: init failed + */ +enum host_init_resp { + ICP_INIT_RESP_RESET, + ICP_INIT_RESP_SUCCESS, + ICP_INIT_RESP_FAILED +}; + +/** + * @ICP_INIT_REQUEST_RESET: reset init request + * @ICP_INIT_REQUEST_SET: set init request + */ +enum host_init_request { + ICP_INIT_REQUEST_RESET, + ICP_INIT_REQUEST_SET +}; + +/** + * @QHDR_INACTIVE: Queue is inactive + * @QHDR_ACTIVE: Queue is active + */ +enum qhdr_status { + QHDR_INACTIVE, + QHDR_ACTIVE +}; + +/** + * @INTR_MODE: event driven mode 1, each send and receive generates interrupt + * @WM_MODE: event driven mode 2, interrupts based on watermark mechanism + * @POLL_MODE: poll method + */ +enum qhdr_event_drv_type { + INTR_MODE, + WM_MODE, + POLL_MODE +}; + +/** + * @TX_INT: event driven mode 1, each send and receive generates interrupt + * @TX_INT_WM: event driven mode 2, interrupts based on watermark mechanism + * @TX_POLL: poll method + * @ICP_QHDR_TX_TYPE_MASK defines position in qhdr_type + */ +enum qhdr_tx_type { + TX_INT, + TX_INT_WM, + TX_POLL +}; + +/** + * @RX_INT: event driven mode 1, each send and receive generates interrupt + * @RX_INT_WM: event driven mode 2, interrupts based on watermark mechanism + * @RX_POLL: poll method + * @ICP_QHDR_RX_TYPE_MASK defines position in qhdr_type + */ +enum qhdr_rx_type { + RX_INT, + RX_INT_WM, + RX_POLL +}; + +/** + * @Q_CMD: Host to FW command queue + * @Q_MSG: FW to Host message queue + * @Q_DEBUG: FW to Host debug queue + * @ICP_QHDR_Q_ID_MASK defines position in qhdr_type + */ +enum qhdr_q_id { + Q_CMD, + Q_MSG, + Q_DBG +}; + +/** + * struct hfi_qtbl_hdr + * @qtbl_version: Queue table version number + * Higher 16 bits: Major version + * Lower 16 bits: Minor version + * @qtbl_size: Queue table size from version to last parametr in qhdr entry + * @qtbl_qhdr0_offset: Offset to the start of first qhdr + * @qtbl_qhdr_size: Queue header size in bytes + * @qtbl_num_q: Total number of queues in Queue table + * @qtbl_num_active_q: Total number of active queues + */ +struct hfi_qtbl_hdr { + uint32_t qtbl_version; + uint32_t qtbl_size; + uint32_t qtbl_qhdr0_offset; + uint32_t qtbl_qhdr_size; + uint32_t qtbl_num_q; + uint32_t qtbl_num_active_q; +} __packed; + +/** + * struct hfi_q_hdr + * @qhdr_status: Queue status, qhdr_state define possible status + * @qhdr_start_addr: Queue start address in non cached memory + * @qhdr_type: qhdr_tx, qhdr_rx, qhdr_q_id and priority defines qhdr type + * @qhdr_q_size: Queue size + * Number of queue packets if qhdr_pkt_size is non-zero + * Queue size in bytes if qhdr_pkt_size is zero + * @qhdr_pkt_size: Size of queue packet entries + * 0x0: variable queue packet size + * non zero: size of queue packet entry, fixed + * @qhdr_pkt_drop_cnt: Number of packets dropped by sender + * @qhdr_rx_wm: Receiver watermark, applicable in event driven mode + * @qhdr_tx_wm: Sender watermark, applicable in event driven mode + * @qhdr_rx_req: Receiver sets this bit if queue is empty + * @qhdr_tx_req: Sender sets this bit if queue is full + * @qhdr_rx_irq_status: Receiver sets this bit and triggers an interrupt to + * the sender after packets are dequeued. Sender clears this bit + * @qhdr_tx_irq_status: Sender sets this bit and triggers an interrupt to + * the receiver after packets are queued. Receiver clears this bit + * @qhdr_read_idx: Read index + * @qhdr_write_idx: Write index + */ +struct hfi_q_hdr { + uint32_t dummy[15]; + uint32_t qhdr_status; + uint32_t dummy1[15]; + uint32_t qhdr_start_addr; + uint32_t dummy2[15]; + uint32_t qhdr_type; + uint32_t dummy3[15]; + uint32_t qhdr_q_size; + uint32_t dummy4[15]; + uint32_t qhdr_pkt_size; + uint32_t dummy5[15]; + uint32_t qhdr_pkt_drop_cnt; + uint32_t dummy6[15]; + uint32_t qhdr_rx_wm; + uint32_t dummy7[15]; + uint32_t qhdr_tx_wm; + uint32_t dummy8[15]; + uint32_t qhdr_rx_req; + uint32_t dummy9[15]; + uint32_t qhdr_tx_req; + uint32_t dummy10[15]; + uint32_t qhdr_rx_irq_status; + uint32_t dummy11[15]; + uint32_t qhdr_tx_irq_status; + uint32_t dummy12[15]; + uint32_t qhdr_read_idx; + uint32_t dummy13[15]; + uint32_t qhdr_write_idx; + uint32_t dummy14[15]; +}; + +/** + * struct sfr_buf + * @size: Number of characters + * @msg : Subsystem failure reason + */ +struct sfr_buf { + uint32_t size; + char msg[ICP_MSG_SFR_SIZE_IN_BYTES]; +}; + +/** + * struct hfi_q_tbl + * @q_tbl_hdr: Queue table header + * @q_hdr: Queue header info, it holds info of cmd, msg and debug queues + */ +struct hfi_qtbl { + struct hfi_qtbl_hdr q_tbl_hdr; + struct hfi_q_hdr q_hdr[MAX_ICP_HFI_QUEUES]; +}; + +/** + * struct hfi_info + * @map: Hfi shared memory info + * @smem_size: Shared memory size + * @uncachedheap_size: uncached heap size + * @msgpacket_buf: message buffer + * @hfi_state: State machine for hfi + * @cmd_q_lock: Lock for command queue + * @cmd_q_state: State of command queue + * @mutex msg_q_lock: Lock for message queue + * @msg_q_state: State of message queue + * @csr_base: CSR base address + */ +struct hfi_info { + struct hfi_mem_info map; + uint32_t smem_size; + uint32_t uncachedheap_size; + uint32_t msgpacket_buf[ICP_HFI_MAX_MSG_SIZE_IN_WORDS]; + uint8_t hfi_state; + struct mutex cmd_q_lock; + bool cmd_q_state; + struct mutex msg_q_lock; + bool msg_q_state; + void __iomem *csr_base; +}; + +#endif /* _CAM_HFI_REG_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_icp/fw_inc/hfi_session_defs.h b/techpack/camera-bengal/drivers/cam_icp/fw_inc/hfi_session_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..9ba7803d4f44bb801f229cc8e00d36abdf0c5660 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/fw_inc/hfi_session_defs.h @@ -0,0 +1,578 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_HFI_SESSION_DEFS_H +#define _CAM_HFI_SESSION_DEFS_H + +#include + +#define HFI_IPEBPS_CMD_OPCODE_BPS_CONFIG_IO 0x1 +#define HFI_IPEBPS_CMD_OPCODE_BPS_FRAME_PROCESS 0x2 +#define HFI_IPEBPS_CMD_OPCODE_BPS_ABORT 0x3 +#define HFI_IPEBPS_CMD_OPCODE_BPS_DESTROY 0x4 + +#define HFI_IPEBPS_CMD_OPCODE_IPE_CONFIG_IO 0x5 +#define HFI_IPEBPS_CMD_OPCODE_IPE_FRAME_PROCESS 0x6 +#define HFI_IPEBPS_CMD_OPCODE_IPE_ABORT 0x7 +#define HFI_IPEBPS_CMD_OPCODE_IPE_DESTROY 0x8 + +#define HFI_IPEBPS_CMD_OPCODE_BPS_WAIT_FOR_IPE 0x9 +#define HFI_IPEBPS_CMD_OPCODE_BPS_WAIT_FOR_BPS 0xa +#define HFI_IPEBPS_CMD_OPCODE_IPE_WAIT_FOR_BPS 0xb +#define HFI_IPEBPS_CMD_OPCODE_IPE_WAIT_FOR_IPE 0xc + +#define HFI_IPEBPS_CMD_OPCODE_MEM_MAP 0xe +#define HFI_IPEBPS_CMD_OPCODE_MEM_UNMAP 0xf + +#define HFI_IPEBPS_HANDLE_TYPE_BPS 0x1 +#define HFI_IPEBPS_HANDLE_TYPE_IPE_RT 0x2 +#define HFI_IPEBPS_HANDLE_TYPE_IPE_NON_RT 0x3 + +/** + * struct mem_map_region_data + * @start_addr: cmd buffer region start addr + * @len : length of the region + * + * create mem_map_region_data + */ +struct mem_map_region_data { + uint32_t start_addr; + uint32_t len; +}; + +/** + * struct hfi_cmd_ipe_bps_map + * @user_data : user arg + * @mem_map_request_num: number of mappings + * @mem_map_region_sets: array of all map/unmap info + * + * create hfi_cmd_ipe_bps_map + */ +struct hfi_cmd_ipe_bps_map { + uint64_t user_data; + uint32_t mem_map_request_num; + struct mem_map_region_data mem_map_region_sets[1]; +} __packed; + +/** + * struct hfi_cmd_ipe_bps_map_ack + * @rc : Async return code + * @user_data: user_arg + * + * create hfi_cmd_ipe_bps_map_ack + */ +struct hfi_cmd_ipe_bps_map_ack { + uint32_t rc; + uint64_t user_data; +}; + +/** + * struct abort_data + * @num_req_ids: Number of req ids + * @num_req_id: point to specific req id + * + * create abort data + */ +struct abort_data { + uint32_t num_req_ids; + uint32_t num_req_id[1]; +}; + +/** + * struct hfi_cmd_data + * @abort: abort data + * @user data: user supplied argument + * + * create session abort data + */ +struct hfi_cmd_abort { + struct abort_data abort; + uint64_t user_data; +} __packed; + +/** + * struct hfi_cmd_abort_destroy + * @user_data: user supplied data + * + * IPE/BPS destroy/abort command + * @HFI_IPEBPS_CMD_OPCODE_IPE_ABORT + * @HFI_IPEBPS_CMD_OPCODE_BPS_ABORT + * @HFI_IPEBPS_CMD_OPCODE_IPE_DESTROY + * @HFI_IPEBPS_CMD_OPCODE_BPS_DESTROY + */ +struct hfi_cmd_abort_destroy { + uint64_t user_data; +} __packed; + +/** + * struct hfi_cmd_chaining_ops + * @wait_hdl: current session handle waits on wait_hdl to complete operation + * @user_data: user supplied argument + * + * this structure for chaining opcodes + * BPS_WAITS_FOR_IPE + * BPS_WAITS_FOR_BPS + * IPE_WAITS_FOR_BPS + * IPE_WAITS_FOR_IPE + */ +struct hfi_cmd_chaining_ops { + uint32_t wait_hdl; + uint64_t user_data; +} __packed; + +/** + * struct hfi_cmd_create_handle + * @size: packet size in bytes + * @pkt_type: opcode of a packet + * @handle_type: IPE/BPS firmware session handle type + * @user_data1: caller provided data1 + * @user_data2: caller provided data2 + * + * create firmware session handle + */ +struct hfi_cmd_create_handle { + uint32_t size; + uint32_t pkt_type; + uint32_t handle_type; + uint64_t user_data1; + uint64_t user_data2; +} __packed; + +/** + * struct hfi_cmd_ipebps_async + * @size: packet size in bytes + * @pkt_type: opcode of a packet + * @opcode: opcode for IPE/BPS async operation + * CONFIG_IO: configures I/O for IPE/BPS handle + * FRAME_PROCESS: image frame to be processed by IPE/BPS + * ABORT: abort all processing frames of IPE/BPS handle + * DESTROY: destroy earlier created IPE/BPS handle + * BPS_WAITS_FOR_IPE: sync for BPS to wait for IPE + * BPS_WAITS_FOR_BPS: sync for BPS to wait for BPS + * IPE_WAITS_FOR_IPE: sync for IPE to wait for IPE + * IPE_WAITS_FOR_BPS: sync for IPE to wait for BPS + * @num_fw_handles: number of IPE/BPS firmware handles in fw_handles array + * @fw_handles: IPE/BPS handles array + * @payload: command payload for IPE/BPS opcodes + * @direct: points to actual payload + * @indirect: points to address of payload + * + * sends async command to the earlier created IPE or BPS handle + * for asynchronous operation. + */ +struct hfi_cmd_ipebps_async { + uint32_t size; + uint32_t pkt_type; + uint32_t opcode; + uint64_t user_data1; + uint64_t user_data2; + uint32_t num_fw_handles; + uint32_t fw_handles[1]; + union { + uint32_t direct[1]; + uint32_t indirect; + } payload; +} __packed; + +/** + * struct hfi_msg_create_handle_ack + * @size: packet size in bytes + * @pkt_type: opcode of a packet + * @err_type: error code + * @fw_handle: output param for IPE/BPS handle + * @user_data1: user provided data1 + * @user_data2: user provided data2 + * + * ack for create handle command of IPE/BPS + * @HFI_MSG_IPEBPS_CREATE_HANDLE_ACK + */ +struct hfi_msg_create_handle_ack { + uint32_t size; + uint32_t pkt_type; + uint32_t err_type; + uint32_t fw_handle; + uint64_t user_data1; + uint64_t user_data2; +} __packed; + +/** + * struct hfi_msg_ipebps_async + * @size: packet size in bytes + * @pkt_type: opcode of a packet + * @opcode: opcode of IPE/BPS async operation + * @user_data1: user provided data1 + * @user_data2: user provided data2 + * @err_type: error code + * @msg_data: IPE/BPS async done message data + * + * result of IPE/BPS async command + * @HFI_MSG_IPEBPS_ASYNC_COMMAND_ACK + */ +struct hfi_msg_ipebps_async_ack { + uint32_t size; + uint32_t pkt_type; + uint32_t opcode; + uint64_t user_data1; + uint64_t user_data2; + uint32_t err_type; + uint32_t msg_data[1]; +} __packed; + +/** + * struct hfi_msg_frame_process_done + * @result: result of frame process command + * @scratch_buffer_address: address of scratch buffer + */ +struct hfi_msg_frame_process_done { + uint32_t result; + uint32_t scratch_buffer_address; +}; + +/** + * struct hfi_msg_chaining_op + * @status: return status + * @user_data: user data provided as part of chaining ops + * + * IPE/BPS wait response + */ +struct hfi_msg_chaining_op { + uint32_t status; + uint64_t user_data; +} __packed; + +/** + * struct hfi_msg_abort_destroy + * @status: return status + * @user_data: user data provided as part of abort/destroy ops + * + * IPE/BPS abort/destroy response + */ +struct hfi_msg_abort_destroy { + uint32_t status; + uint64_t user_data; +} __packed; + +#define MAX_NUM_OF_IMAGE_PLANES 2 +#define MAX_HFR_GROUP 16 + +enum hfi_ipe_io_images { + IPE_INPUT_IMAGE_FULL, + IPE_INPUT_IMAGE_DS4, + IPE_INPUT_IMAGE_DS16, + IPE_INPUT_IMAGE_DS64, + IPE_INPUT_IMAGE_FULL_REF, + IPE_INPUT_IMAGE_DS4_REF, + IPE_INPUT_IMAGE_DS16_REF, + IPE_INPUT_IMAGE_DS64_REF, + IPE_OUTPUT_IMAGE_DISPLAY, + IPE_OUTPUT_IMAGE_VIDEO, + IPE_OUTPUT_IMAGE_FULL_REF, + IPE_OUTPUT_IMAGE_DS4_REF, + IPE_OUTPUT_IMAGE_DS16_REF, + IPE_OUTPUT_IMAGE_DS64_REF, + IPE_INPUT2_IMAGE_FULL, + IPE_INPUT2_IMAGE_DSX, + IPE_INPUT_OUTPUT_SCRATCHBUFFER, + IPE_INPUT_IMAGE_FIRST = IPE_INPUT_IMAGE_FULL, + IPE_INPUT_IMAGE_LAST = IPE_INPUT_IMAGE_DS64_REF, + IPE_INPUT_IMAGE_REF_FIRST = IPE_INPUT_IMAGE_FULL_REF, + IPE_INPUT_IMAGE_REF_LAST = IPE_INPUT_IMAGE_DS64_REF, + IPE_OUTPUT_IMAGE_FIRST = IPE_OUTPUT_IMAGE_DISPLAY, + IPE_OUTPUT_IMAGE_LAST = IPE_OUTPUT_IMAGE_DS64_REF, + IPE_OUTPUT_IMAGE_REF_FIRST = IPE_OUTPUT_IMAGE_FULL_REF, + IPE_OUTPUT_IMAGE_REF_LAST = IPE_OUTPUT_IMAGE_DS64_REF, + IPE_INPUT2_IMAGE_FIRST = IPE_INPUT2_IMAGE_FULL, + IPE_INPUT2_IMAGE_LAST = IPE_INPUT2_IMAGE_DSX, + IPE_INPUT_OUTPUT_IMAGE_LAST = IPE_INPUT_OUTPUT_SCRATCHBUFFER, + IPE_IO_IMAGES_MAX +}; + +enum bps_io_images { + BPS_INPUT_IMAGE, + BPS_OUTPUT_IMAGE_FULL, + BPS_OUTPUT_IMAGE_DS4, + BPS_OUTPUT_IMAGE_DS16, + BPS_OUTPUT_IMAGE_DS64, + BPS_OUTPUT_IMAGE_STATS_BG, + BPS_OUTPUT_IMAGE_STATS_BHIST, + BPS_OUTPUT_IMAGE_REG1, + BPS_OUTPUT_IMAGE_REG2, + BPS_OUTPUT_IMAGE_FIRST = BPS_OUTPUT_IMAGE_FULL, + BPS_OUTPUT_IMAGE_LAST = BPS_OUTPUT_IMAGE_REG2, + BPS_IO_IMAGES_MAX +}; + +struct frame_buffer { + uint32_t buf_ptr[MAX_NUM_OF_IMAGE_PLANES]; + uint32_t meta_buf_ptr[MAX_NUM_OF_IMAGE_PLANES]; +} __packed; + +struct bps_frame_process_data { + uint32_t max_num_cores; + uint32_t target_time; + uint32_t ubwc_stats_buffer_addr; + uint32_t ubwc_stats_buffer_size; + uint32_t cdm_buffer_addr; + uint32_t cdm_buffer_size; + uint32_t iq_settings_addr; + uint32_t strip_lib_out_addr; + uint32_t cdm_prog_addr; + uint32_t request_id; + struct frame_buffer buffers[BPS_IO_IMAGES_MAX]; +}; + +enum hfi_ipe_image_format { + IMAGE_FORMAT_INVALID, + IMAGE_FORMAT_MIPI_8, + IMAGE_FORMAT_MIPI_10, + IMAGE_FORMAT_MIPI_12, + IMAGE_FORMAT_MIPI_14, + IMAGE_FORMAT_BAYER_8, + IMAGE_FORMAT_BAYER_10, + IMAGE_FORMAT_BAYER_12, + IMAGE_FORMAT_BAYER_14, + IMAGE_FORMAT_PDI_10, + IMAGE_FORMAT_PD_10, + IMAGE_FORMAT_PD_8, + IMAGE_FORMAT_INDICATIONS, + IMAGE_FORMAT_REFINEMENT, + IMAGE_FORMAT_UBWC_TP_10, + IMAGE_FORMAT_UBWC_NV_12, + IMAGE_FORMAT_UBWC_NV12_4R, + IMAGE_FORMAT_UBWC_P010, + IMAGE_FORMAT_LINEAR_TP_10, + IMAGE_FORMAT_LINEAR_P010, + IMAGE_FORMAT_LINEAR_NV12, + IMAGE_FORMAT_LINEAR_PLAIN_16, + IMAGE_FORMAT_YUV422_8, + IMAGE_FORMAT_YUV422_10, + IMAGE_FORMAT_STATISTICS_BAYER_GRID, + IMAGE_FORMAT_STATISTICS_BAYER_HISTOGRAM, + IMAGE_FORMAT_MAX +}; + +enum hfi_ipe_plane_format { + PLANE_FORMAT_INVALID = 0, + PLANE_FORMAT_MIPI_8, + PLANE_FORMAT_MIPI_10, + PLANE_FORMAT_MIPI_12, + PLANE_FORMAT_MIPI_14, + PLANE_FORMAT_BAYER_8, + PLANE_FORMAT_BAYER_10, + PLANE_FORMAT_BAYER_12, + PLANE_FORMAT_BAYER_14, + PLANE_FORMAT_PDI_10, + PLANE_FORMAT_PD_10, + PLANE_FORMAT_PD_8, + PLANE_FORMAT_INDICATIONS, + PLANE_FORMAT_REFINEMENT, + PLANE_FORMAT_UBWC_TP_10_Y, + PLANE_FORMAT_UBWC_TP_10_C, + PLANE_FORMAT_UBWC_NV_12_Y, + PLANE_FORMAT_UBWC_NV_12_C, + PLANE_FORMAT_UBWC_NV_12_4R_Y, + PLANE_FORMAT_UBWC_NV_12_4R_C, + PLANE_FORMAT_UBWC_P010_Y, + PLANE_FORMAT_UBWC_P010_C, + PLANE_FORMAT_LINEAR_TP_10_Y, + PLANE_FORMAT_LINEAR_TP_10_C, + PLANE_FORMAT_LINEAR_P010_Y, + PLANE_FORMAT_LINEAR_P010_C, + PLANE_FORMAT_LINEAR_NV12_Y, + PLANE_FORMAT_LINEAR_NV12_C, + PLANE_FORMAT_LINEAR_PLAIN_16_Y, + PLANE_FORMAT_LINEAR_PLAIN_16_C, + PLANE_FORMAT_YUV422_8, + PLANE_FORMAT_YUV422_10, + PLANE_FORMAT_STATISTICS_BAYER_GRID, + PLANE_FORMAT_STATISTICS_BAYER_HISTOGRAM, + PLANE_FORMAT_MAX +}; + +enum hfi_ipe_bayer_pixel_order { + FIRST_PIXEL_R, + FIRST_PIXEL_GR, + FIRST_PIXEL_B, + FIRST_PIXEL_GB, + FIRST_PIXEL_MAX +}; + +enum hfi_ipe_pixel_pack_alignment { + PIXEL_LSB_ALIGNED, + PIXEL_MSB_ALIGNED, +}; + +enum hfi_ipe_yuv_422_order { + PIXEL_ORDER_Y_U_Y_V, + PIXEL_ORDER_Y_V_Y_U, + PIXEL_ORDER_U_Y_V_Y, + PIXEL_ORDER_V_Y_U_Y, + PIXEL_ORDER_YUV422_MAX +}; + +enum ubwc_write_client { + IPE_WR_CLIENT_0 = 0, + IPE_WR_CLIENT_1, + IPE_WR_CLIENT_5, + IPE_WR_CLIENT_6, + IPE_WR_CLIENT_7, + IPE_WR_CLIENT_8, + IPE_WR_CLIENT_MAX +}; + +/** + * struct image_info + * @format: image format + * @img_width: image width + * @img_height: image height + * @bayer_order: pixel order + * @pix_align: alignment + * @yuv422_order: YUV order + * @byte_swap: byte swap + */ +struct image_info { + enum hfi_ipe_image_format format; + uint32_t img_width; + uint32_t img_height; + enum hfi_ipe_bayer_pixel_order bayer_order; + enum hfi_ipe_pixel_pack_alignment pix_align; + enum hfi_ipe_yuv_422_order yuv422_order; + uint32_t byte_swap; +} __packed; + +/** + * struct buffer_layout + * @buf_stride: buffer stride + * @buf_height: buffer height + */ +struct buffer_layout { + uint32_t buf_stride; + uint32_t buf_height; +} __packed; + +/** + * struct image_desc + * @info: image info + * @buf_layout: buffer layout + * @meta_buf_layout: meta buffer layout + */ +struct image_desc { + struct image_info info; + struct buffer_layout buf_layout[MAX_NUM_OF_IMAGE_PLANES]; + struct buffer_layout meta_buf_layout[MAX_NUM_OF_IMAGE_PLANES]; +} __packed; + +struct ica_stab_coeff { + uint32_t coeffs[8]; +} __packed; + +struct ica_stab_params { + uint32_t mode; + struct ica_stab_coeff transforms[3]; +} __packed; + +struct frame_set { + struct frame_buffer buffers[IPE_IO_IMAGES_MAX]; + uint32_t cdm_ica1_addr; + uint32_t cdm_ica2_addr; +} __packed; + +struct ipe_frame_process_data { + uint32_t strip_lib_out_addr; + uint32_t iq_settings_addr; + uint32_t scratch_buffer_addr; + uint32_t scratch_buffer_size; + uint32_t ubwc_stats_buffer_addr; + uint32_t ubwc_stats_buffer_size; + uint32_t cdm_buffer_addr; + uint32_t cdm_buffer_size; + uint32_t max_num_cores; + uint32_t target_time; + uint32_t cdm_prog_base; + uint32_t cdm_pre_ltm; + uint32_t cdm_post_ltm; + uint32_t cdm_anr_full_pass; + uint32_t cdm_anr_ds4; + uint32_t cdm_anr_ds16; + uint32_t cdm_anr_ds64; + uint32_t cdm_tf_full_pass; + uint32_t cdm_tf_ds4; + uint32_t cdm_tf_ds16; + uint32_t cdm_tf_ds64; + uint32_t cdm_dsx_dc4; + uint32_t cdm_dsx_dc16; + uint32_t cdm_dsz_dc64; + uint32_t cdm_mfhdr_full_pass; + uint32_t cdm_mfhdr_dcx; + uint32_t request_id; + uint32_t frames_in_batch; + struct frame_set framesets[MAX_HFR_GROUP]; +} __packed; + +/** + * struct hfi_cmd_ipe_config + * @images: images descreptions + * @user_data: user supplied data + * + * payload for IPE async command + */ +struct hfi_cmd_ipe_config { + struct image_desc images[IPE_IO_IMAGES_MAX]; + uint64_t user_data; +} __packed; + +/** + * struct frame_buffers + * @buf_ptr: buffer pointers for all planes + * @meta_buf_ptr: meta buffer pointers for all planes + */ +struct frame_buffers { + uint32_t buf_ptr[MAX_NUM_OF_IMAGE_PLANES]; + uint32_t meta_buf_ptr[MAX_NUM_OF_IMAGE_PLANES]; +} __packed; + +/** + * struct hfi_msg_ipe_config + * @rc: result of ipe config command + * @scratch_mem_size: scratch mem size for a config + * @user_data: user data + */ +struct hfi_msg_ipe_config { + uint32_t rc; + uint32_t scratch_mem_size; + uint64_t user_data; +} __packed; + +/** + * struct hfi_msg_bps_common + * @rc: result of ipe config command + * @user_data: user data + */ +struct hfi_msg_bps_common { + uint32_t rc; + uint64_t user_data; +} __packed; + +/** + * struct ipe_bps_destroy + * @user_data: user data + */ +struct ipe_bps_destroy { + uint64_t userdata; +}; + +/** + * struct hfi_msg_ipe_frame_process + * @status: result of ipe frame process command + * @scratch_buf_addr: address of scratch buffer + * @user_data: user data + */ +struct hfi_msg_ipe_frame_process { + uint32_t status; + uint32_t scratch_buf_addr; + uint64_t user_data; +} __packed; + +#endif /* _CAM_HFI_SESSION_DEFS_H */ diff --git a/techpack/camera-bengal/drivers/cam_icp/fw_inc/hfi_sys_defs.h b/techpack/camera-bengal/drivers/cam_icp/fw_inc/hfi_sys_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..f62e8cc9943013edad9aad532db1bdcdbec90723 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/fw_inc/hfi_sys_defs.h @@ -0,0 +1,561 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _HFI_DEFS_H_ +#define _HFI_DEFS_H_ + +#include + +/* + * Following base acts as common starting points + * for all enumerations. + */ +#define HFI_COMMON_BASE 0x0 + +/* HFI Domain base offset for commands and messages */ +#define HFI_DOMAIN_SHFT (24) +#define HFI_DOMAIN_BMSK (0x7 << HFI_DOMAIN_SHFT) +#define HFI_DOMAIN_BASE_ICP (0x0 << HFI_DOMAIN_SHFT) +#define HFI_DOMAIN_BASE_IPE_BPS (0x1 << HFI_DOMAIN_SHFT) +#define HFI_DOMAIN_BASE_CDM (0x2 << HFI_DOMAIN_SHFT) +#define HFI_DOMAIN_BASE_DBG (0x3 << HFI_DOMAIN_SHFT) + +/* Command base offset for commands */ +#define HFI_CMD_START_OFFSET 0x10000 + +/* Command base offset for messages */ +#define HFI_MSG_START_OFFSET 0x20000 + +/* System Level Error types */ +#define HFI_ERR_SYS_NONE (HFI_COMMON_BASE) +#define HFI_ERR_SYS_FATAL (HFI_COMMON_BASE + 0x1) +#define HFI_ERR_SYS_VERSION_MISMATCH (HFI_COMMON_BASE + 0x2) +#define HFI_ERR_SYS_UNSUPPORTED_DOMAIN (HFI_COMMON_BASE + 0x3) +#define HFI_ERR_SYS_UNSUPPORT_CMD (HFI_COMMON_BASE + 0x4) +#define HFI_ERR_SYS_CMDFAILED (HFI_COMMON_BASE + 0x5) +#define HFI_ERR_SYS_CMDSIZE (HFI_COMMON_BASE + 0x6) + +/* System Level Event types */ +#define HFI_EVENT_SYS_ERROR (HFI_COMMON_BASE + 0x1) +#define HFI_EVENT_ICP_ERROR (HFI_COMMON_BASE + 0x2) +#define HFI_EVENT_IPE_BPS_ERROR (HFI_COMMON_BASE + 0x3) +#define HFI_EVENT_CDM_ERROR (HFI_COMMON_BASE + 0x4) +#define HFI_EVENT_DBG_ERROR (HFI_COMMON_BASE + 0x5) + +/* Core level start Ranges for errors */ +#define HFI_ERR_ICP_START (HFI_COMMON_BASE + 0x64) +#define HFI_ERR_IPE_BPS_START (HFI_ERR_ICP_START + 0x64) +#define HFI_ERR_CDM_START (HFI_ERR_IPE_BPS_START + 0x64) +#define HFI_ERR_DBG_START (HFI_ERR_CDM_START + 0x64) + +/*ICP Core level error messages */ +#define HFI_ERR_NO_RES (HFI_ERR_ICP_START + 0x1) +#define HFI_ERR_UNSUPPORTED_RES (HFI_ERR_ICP_START + 0x2) +#define HFI_ERR_UNSUPPORTED_PROP (HFI_ERR_ICP_START + 0x3) +#define HFI_ERR_INIT_EXPECTED (HFI_ERR_ICP_START + 0x4) +#define HFI_ERR_INIT_IGNORED (HFI_ERR_ICP_START + 0x5) + +/* System level commands */ +#define HFI_CMD_COMMON_START \ + (HFI_DOMAIN_BASE_ICP + HFI_CMD_START_OFFSET + 0x0) +#define HFI_CMD_SYS_INIT (HFI_CMD_COMMON_START + 0x1) +#define HFI_CMD_SYS_PC_PREP (HFI_CMD_COMMON_START + 0x2) +#define HFI_CMD_SYS_SET_PROPERTY (HFI_CMD_COMMON_START + 0x3) +#define HFI_CMD_SYS_GET_PROPERTY (HFI_CMD_COMMON_START + 0x4) +#define HFI_CMD_SYS_PING (HFI_CMD_COMMON_START + 0x5) +#define HFI_CMD_SYS_RESET (HFI_CMD_COMMON_START + 0x6) + +/* General Frame process errors */ +#define CAMERAICP_SUCCESS 0 +#define CAMERAICP_EFAILED 1 +#define CAMERAICP_ENOMEMORY 2 +#define CAMERAICP_EBADSTATE 3 +#define CAMERAICP_EBADPARM 4 +#define CAMERAICP_EBADITEM 5 +#define CAMERAICP_EINVALIDFORMAT 6 +#define CAMERAICP_EUNSUPPORTED 7 +#define CAMERAICP_EOUTOFBOUND 8 +#define CAMERAICP_ETIMEDOUT 9 +#define CAMERAICP_EABORTED 10 +#define CAMERAICP_EHWVIOLATION 11 +#define CAMERAICP_ECDMERROR 12 + +/* HFI Specific errors. */ +#define CAMERAICP_HFI_ERR_COMMAND_SIZE 1000 +#define CAMERAICP_HFI_ERR_MESSAGE_SIZE 1001 +#define CAMERAICP_HFI_QUEUE_EMPTY 1002 +#define CAMERAICP_HFI_QUEUE_FULL 1003 + +/* Core level commands */ +/* IPE/BPS core Commands */ +#define HFI_CMD_IPE_BPS_COMMON_START \ + (HFI_DOMAIN_BASE_IPE_BPS + HFI_CMD_START_OFFSET + 0x0) +#define HFI_CMD_IPEBPS_CREATE_HANDLE \ + (HFI_CMD_IPE_BPS_COMMON_START + 0x8) +#define HFI_CMD_IPEBPS_ASYNC_COMMAND_DIRECT \ + (HFI_CMD_IPE_BPS_COMMON_START + 0xa) +#define HFI_CMD_IPEBPS_ASYNC_COMMAND_INDIRECT \ + (HFI_CMD_IPE_BPS_COMMON_START + 0xe) + +/* CDM core Commands */ +#define HFI_CMD_CDM_COMMON_START \ + (HFI_DOMAIN_BASE_CDM + HFI_CMD_START_OFFSET + 0x0) +#define HFI_CMD_CDM_TEST_START (HFI_CMD_CDM_COMMON_START + 0x800) +#define HFI_CMD_CDM_END (HFI_CMD_CDM_COMMON_START + 0xFFF) + +/* Debug/Test Commands */ +#define HFI_CMD_DBG_COMMON_START \ + (HFI_DOMAIN_BASE_DBG + HFI_CMD_START_OFFSET + 0x0) +#define HFI_CMD_DBG_TEST_START (HFI_CMD_DBG_COMMON_START + 0x800) +#define HFI_CMD_DBG_END (HFI_CMD_DBG_COMMON_START + 0xFFF) + +/* System level messages */ +#define HFI_MSG_ICP_COMMON_START \ + (HFI_DOMAIN_BASE_ICP + HFI_MSG_START_OFFSET + 0x0) +#define HFI_MSG_SYS_INIT_DONE (HFI_MSG_ICP_COMMON_START + 0x1) +#define HFI_MSG_SYS_PC_PREP_DONE (HFI_MSG_ICP_COMMON_START + 0x2) +#define HFI_MSG_SYS_DEBUG (HFI_MSG_ICP_COMMON_START + 0x3) +#define HFI_MSG_SYS_IDLE (HFI_MSG_ICP_COMMON_START + 0x4) +#define HFI_MSG_SYS_PROPERTY_INFO (HFI_MSG_ICP_COMMON_START + 0x5) +#define HFI_MSG_SYS_PING_ACK (HFI_MSG_ICP_COMMON_START + 0x6) +#define HFI_MSG_SYS_RESET_ACK (HFI_MSG_ICP_COMMON_START + 0x7) +#define HFI_MSG_EVENT_NOTIFY (HFI_MSG_ICP_COMMON_START + 0x8) + +/* Core level Messages */ +/* IPE/BPS core Messages */ +#define HFI_MSG_IPE_BPS_COMMON_START \ + (HFI_DOMAIN_BASE_IPE_BPS + HFI_MSG_START_OFFSET + 0x0) +#define HFI_MSG_IPEBPS_CREATE_HANDLE_ACK \ + (HFI_MSG_IPE_BPS_COMMON_START + 0x08) +#define HFI_MSG_IPEBPS_ASYNC_COMMAND_DIRECT_ACK \ + (HFI_MSG_IPE_BPS_COMMON_START + 0x0a) +#define HFI_MSG_IPEBPS_ASYNC_COMMAND_INDIRECT_ACK \ + (HFI_MSG_IPE_BPS_COMMON_START + 0x0e) +#define HFI_MSG_IPE_BPS_TEST_START \ + (HFI_MSG_IPE_BPS_COMMON_START + 0x800) +#define HFI_MSG_IPE_BPS_END \ + (HFI_MSG_IPE_BPS_COMMON_START + 0xFFF) + +/* CDM core Messages */ +#define HFI_MSG_CDM_COMMON_START \ + (HFI_DOMAIN_BASE_CDM + HFI_MSG_START_OFFSET + 0x0) +#define HFI_MSG_PRI_CDM_PAYLOAD_ACK (HFI_MSG_CDM_COMMON_START + 0xa) +#define HFI_MSG_PRI_LLD_PAYLOAD_ACK (HFI_MSG_CDM_COMMON_START + 0xb) +#define HFI_MSG_CDM_TEST_START (HFI_MSG_CDM_COMMON_START + 0x800) +#define HFI_MSG_CDM_END (HFI_MSG_CDM_COMMON_START + 0xFFF) + +/* core level test command ranges */ +/* ICP core level test command range */ +#define HFI_CMD_ICP_TEST_START (HFI_CMD_ICP_COMMON_START + 0x800) +#define HFI_CMD_ICP_END (HFI_CMD_ICP_COMMON_START + 0xFFF) + +/* IPE/BPS core level test command range */ +#define HFI_CMD_IPE_BPS_TEST_START \ + (HFI_CMD_IPE_BPS_COMMON_START + 0x800) +#define HFI_CMD_IPE_BPS_END (HFI_CMD_IPE_BPS_COMMON_START + 0xFFF) + +/* ICP core level test message range */ +#define HFI_MSG_ICP_TEST_START (HFI_MSG_ICP_COMMON_START + 0x800) +#define HFI_MSG_ICP_END (HFI_MSG_ICP_COMMON_START + 0xFFF) + +/* ICP core level Debug test message range */ +#define HFI_MSG_DBG_COMMON_START \ + (HFI_DOMAIN_BASE_DBG + 0x0) +#define HFI_MSG_DBG_TEST_START (HFI_MSG_DBG_COMMON_START + 0x800) +#define HFI_MSG_DBG_END (HFI_MSG_DBG_COMMON_START + 0xFFF) + +/* System level property base offset */ +#define HFI_PROPERTY_ICP_COMMON_START (HFI_DOMAIN_BASE_ICP + 0x0) + +#define HFI_PROP_SYS_DEBUG_CFG (HFI_PROPERTY_ICP_COMMON_START + 0x1) +#define HFI_PROP_SYS_UBWC_CFG (HFI_PROPERTY_ICP_COMMON_START + 0x2) +#define HFI_PROP_SYS_IMAGE_VER (HFI_PROPERTY_ICP_COMMON_START + 0x3) +#define HFI_PROP_SYS_SUPPORTED (HFI_PROPERTY_ICP_COMMON_START + 0x4) +#define HFI_PROP_SYS_IPEBPS_PC (HFI_PROPERTY_ICP_COMMON_START + 0x5) +#define HFI_PROP_SYS_FW_DUMP_CFG (HFI_PROPERTY_ICP_COMMON_START + 0x8) +#define HFI_PROPERTY_SYS_UBWC_CONFIG_EX (HFI_PROPERTY_ICP_COMMON_START + 0x9) + +/* Capabilities reported at sys init */ +#define HFI_CAPS_PLACEHOLDER_1 (HFI_COMMON_BASE + 0x1) +#define HFI_CAPS_PLACEHOLDER_2 (HFI_COMMON_BASE + 0x2) + +/* Section describes different debug levels (HFI_DEBUG_MSG_X) + * available for debug messages from FW + */ +#define HFI_DEBUG_MSG_LOW 0x00000001 +#define HFI_DEBUG_MSG_MEDIUM 0x00000002 +#define HFI_DEBUG_MSG_HIGH 0x00000004 +#define HFI_DEBUG_MSG_ERROR 0x00000008 +#define HFI_DEBUG_MSG_FATAL 0x00000010 +/* Messages containing performance data */ +#define HFI_DEBUG_MSG_PERF 0x00000020 +/* Disable ARM9 WFI in low power mode. */ +#define HFI_DEBUG_CFG_WFI 0x01000000 +/* Disable ARM9 watchdog. */ +#define HFI_DEBUG_CFG_ARM9WD 0x10000000 + + +/* + * HFI_FW_DUMP levels + * HFI_FW_DUMP_xx + */ +#define HFI_FW_DUMP_DISABLED 0x00000000 +#define HFI_FW_DUMP_ON_FAILURE 0x00000001 +#define HFI_FW_DUMP_ALWAYS 0x00000002 + +/* Number of available dump levels. */ +#define NUM_HFI_DUMP_LVL 0x00000003 + +/* Debug Msg Communication types: + * Section describes different modes (HFI_DEBUG_MODE_X) + * available to communicate the debug messages + */ + /* Debug message output through the interface debug queue. */ +#define HFI_DEBUG_MODE_QUEUE 0x00000001 + /* Debug message output through QDSS. */ +#define HFI_DEBUG_MODE_QDSS 0x00000002 + /* Number of debug modes available. */ +#define NUM_HFI_DEBUG_MODE 0x00000002 + +#define HFI_DEBUG_MSG_LOW 0x00000001 +#define HFI_DEBUG_MSG_MEDIUM 0x00000002 +#define HFI_DEBUG_MSG_HIGH 0x00000004 +#define HFI_DEBUG_MSG_ERROR 0x00000008 +#define HFI_DEBUG_MSG_FATAL 0x00000010 +#define HFI_DEBUG_MSG_PERF 0x00000020 +#define HFI_DEBUG_CFG_WFI 0x01000000 +#define HFI_DEBUG_CFG_ARM9WD 0x10000000 + +#define HFI_DEV_VERSION_MAX 0x5 + +/** + * start of sys command packet types + * These commands are used to get system level information + * from firmware + */ + +/** + * struct hfi_caps_support + * payload to report caps through HFI_PROPERTY_PARAM_CAPABILITY_SUPPORTED + * @type: capability type + * @min: minimum supported value for the capability + * @max: maximum supported value for the capability + * @step_size: supported steps between min-max + */ +struct hfi_caps_support { + uint32_t type; + uint32_t min; + uint32_t max; + uint32_t step_size; +} __packed; + +/** + * struct hfi_caps_support_info + * capability report through HFI_PROPERTY_PARAM_CAPABILITY_SUPPORTED + * @num_caps: number of capabilities listed + * @caps_data: capabilities info array + */ +struct hfi_caps_support_info { + uint32_t num_caps; + struct hfi_caps_support caps_data[1]; +} __packed; + +/** + * struct hfi_debug + * payload structure to configure HFI_PROPERTY_SYS_DEBUG_CONFIG + * @debug_config: it is a result of HFI_DEBUG_MSG_X values that + * are OR-ed together to specify the debug message types + * to otput + * @debug_mode: debug message output through debug queue/qdss + * @HFI_PROPERTY_SYS_DEBUG_CONFIG + */ +struct hfi_debug { + uint32_t debug_config; + uint32_t debug_mode; +} __packed; + +/** + * struct hfi_ipe_bps_pc + * payload structure to configure HFI_PROPERTY_SYS_IPEBPS_PC + * @enable: Flag to enable IPE, BPS interfrane power collapse + * @core_info: Core information to firmware + */ +struct hfi_ipe_bps_pc { + uint32_t enable; + uint32_t core_info; +} __packed; + +/** + * struct hfi_cmd_ubwc_cfg + * Payload structure to configure HFI_PROP_SYS_UBWC_CFG + * @ubwc_fetch_cfg: UBWC configuration for fecth + * @ubwc_write_cfg: UBWC configuration for write + */ +struct hfi_cmd_ubwc_cfg { + uint32_t ubwc_fetch_cfg; + uint32_t ubwc_write_cfg; +} __packed; + +/** + * struct hfi_cmd_ubwc_cfg_ext + * Payload structure to configure HFI_UBWC_CFG_TYPE_EXT + * @bps: UBWC configuration for bps + * @ipe: UBWC configuration for ipe + */ +struct hfi_cmd_ubwc_cfg_ext { + struct hfi_cmd_ubwc_cfg bps; + struct hfi_cmd_ubwc_cfg ipe; +} __packed; + +/** + * struct hfi_cmd_sys_init + * command to initialization of system session + * @size: packet size in bytes + * @pkt_type: opcode of a packet + * @HFI_CMD_SYS_INIT + */ +struct hfi_cmd_sys_init { + uint32_t size; + uint32_t pkt_type; +} __packed; + +/** + * struct hfi_cmd_pc_prep + * command to firmware to prepare for power collapse + * @eize: packet size in bytes + * @pkt_type: opcode of a packet + * @HFI_CMD_SYS_PC_PREP + */ +struct hfi_cmd_pc_prep { + uint32_t size; + uint32_t pkt_type; +} __packed; + +/** + * struct hfi_cmd_prop + * command to get/set properties of firmware + * @size: packet size in bytes + * @pkt_type: opcode of a packet + * @num_prop: number of properties queried/set + * @prop_data: array of property IDs being queried. size depends on num_prop + * array of property IDs and associated structure pairs in set + * @HFI_CMD_SYS_GET_PROPERTY + * @HFI_CMD_SYS_SET_PROPERTY + */ +struct hfi_cmd_prop { + uint32_t size; + uint32_t pkt_type; + uint32_t num_prop; + uint32_t prop_data[1]; +} __packed; + +/** + * struct hfi_cmd_ping_pkt + * ping command pings the firmware to confirm whether + * it is alive. + * @size: packet size in bytes + * @pkt_type: opcode of a packet + * @user_data: client data, firmware returns this data + * as part of HFI_MSG_SYS_PING_ACK + * @HFI_CMD_SYS_PING + */ +struct hfi_cmd_ping_pkt { + uint32_t size; + uint32_t pkt_type; + uint64_t user_data; +} __packed; + +/** + * struct hfi_cmd_sys_reset_pkt + * sends the reset command to FW. FW responds in the same type + * of packet. so can be used for reset_ack_pkt type also + * @size: packet size in bytes + * @pkt_type: opcode of a packet + * @user_data: client data, firmware returns this data + * as part of HFI_MSG_SYS_RESET_ACK + * @HFI_CMD_SYS_RESET + */ + +struct hfi_cmd_sys_reset_pkt { + uint32_t size; + uint32_t pkt_type; + uint64_t user_data; +} __packed; + +/* end of sys command packet types */ + +/* start of sys message packet types */ + +/** + * struct hfi_prop + * structure to report maximum supported features of firmware. + */ +struct hfi_sys_support { + uint32_t place_holder; +} __packed; + +/** + * struct hfi_supported_prop + * structure to report HFI_PROPERTY_PARAM_PROPERTIES_SUPPORTED + * for a session + * @num_prop: number of properties supported + * @prop_data: array of supported property IDs + */ +struct hfi_supported_prop { + uint32_t num_prop; + uint32_t prop_data[1]; +} __packed; + +/** + * struct hfi_image_version + * system image version + * @major: major version number + * @minor: minor version number + * @ver_name_size: size of version name + * @ver_name: image version name + */ +struct hfi_image_version { + uint32_t major; + uint32_t minor; + uint32_t ver_name_size; + uint8_t ver_name[1]; +} __packed; + +/** + * struct hfi_msg_init_done_data + * @api_ver: Firmware API version + * @dev_ver: Device version + * @num_icp_hw: Number of ICP hardware information + * @dev_hw_ver: Supported hardware version information + * @reserved: Reserved field + */ +struct hfi_msg_init_done_data { + uint32_t api_ver; + uint32_t dev_ver; + uint32_t num_icp_hw; + uint32_t dev_hw_ver[HFI_DEV_VERSION_MAX]; + uint32_t reserved; +}; + +/** + * struct hfi_msg_init_done + * system init done message from firmware. Many system level properties + * are returned with the packet + * @size: Packet size in bytes + * @pkt_type: Opcode of a packet + * @err_type: Error code associated with response + * @num_prop: Number of default capability info + * @prop_data: Array of property ids and corresponding structure pairs + */ +struct hfi_msg_init_done { + uint32_t size; + uint32_t pkt_type; + uint32_t err_type; + uint32_t num_prop; + uint32_t prop_data[1]; +} __packed; + +/** + * struct hfi_msg_pc_prep_done + * system power collapse preparation done message + * @size: packet size in bytes + * @pkt_type: opcode of a packet + * @err_type: error code associated with the response + */ +struct hfi_msg_pc_prep_done { + uint32_t size; + uint32_t pkt_type; + uint32_t err_type; +} __packed; + +/** + * struct hfi_msg_prop + * system property info from firmware + * @size: packet size in bytes + * @pkt_type: opcode of a packet + * @num_prop: number of property info structures + * @prop_data: array of property IDs and associated structure pairs + */ +struct hfi_msg_prop { + uint32_t size; + uint32_t pkt_type; + uint32_t num_prop; + uint32_t prop_data[1]; +} __packed; + +/** + * struct hfi_msg_idle + * system idle message from firmware + * @size: packet size in bytes + * @pkt_type: opcode of a packet + */ +struct hfi_msg_idle { + uint32_t size; + uint32_t pkt_type; +} __packed; + +/** + * struct hfi_msg_ping_ack + * system ping ack message + * @size: packet size in bytes + * @pkt_type: opcode of a packet + * @user_data: this data is sent as part of ping command from host + */ +struct hfi_msg_ping_ack { + uint32_t size; + uint32_t pkt_type; + uint64_t user_data; +} __packed; + +/** + * struct hfi_msg_debug + * system debug message defination + * @size: packet size in bytes + * @pkt_type: opcode of a packet + * @msg_type: debug message type + * @msg_size: size of debug message in bytes + * @timestamp_hi: most significant 32 bits of the 64 bit timestamp field. + * timestamp shall be interpreted as a signed 64-bit value + * representing microseconds. + * @timestamp_lo: least significant 32 bits of the 64 bit timestamp field. + * timestamp shall be interpreted as a signed 64-bit value + * representing microseconds. + * @msg_data: message data in string form + */ +struct hfi_msg_debug { + uint32_t size; + uint32_t pkt_type; + uint32_t msg_type; + uint32_t msg_size; + uint32_t timestamp_hi; + uint32_t timestamp_lo; + uint8_t msg_data[1]; +} __packed; +/** + * struct hfi_msg_event_notify + * event notify message + * @size: packet size in bytes + * @pkt_type: opcode of a packet + * @fw_handle: firmware session handle + * @event_id: session event id + * @event_data1: event data corresponding to event ID + * @event_data2: event data corresponding to event ID + * @ext_event_data: info array, interpreted based on event_data1 + * and event_data2 + */ +struct hfi_msg_event_notify { + uint32_t size; + uint32_t pkt_type; + uint32_t fw_handle; + uint32_t event_id; + uint32_t event_data1; + uint32_t event_data2; + uint32_t ext_event_data[1]; +} __packed; +/** + * end of sys message packet types + */ + +#endif /* _HFI_DEFS_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_icp/hfi.c b/techpack/camera-bengal/drivers/cam_icp/hfi.c new file mode 100644 index 0000000000000000000000000000000000000000..89a95aca62e1259f93f259a57b0e3e9080d58dc5 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/hfi.c @@ -0,0 +1,956 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cam_io_util.h" +#include "hfi_reg.h" +#include "hfi_sys_defs.h" +#include "hfi_session_defs.h" +#include "hfi_intf.h" +#include "cam_icp_hw_mgr_intf.h" +#include "cam_debug_util.h" + +#define HFI_VERSION_INFO_MAJOR_VAL 1 +#define HFI_VERSION_INFO_MINOR_VAL 1 +#define HFI_VERSION_INFO_STEP_VAL 0 +#define HFI_VERSION_INFO_STEP_VAL 0 +#define HFI_VERSION_INFO_MAJOR_BMSK 0xFF000000 +#define HFI_VERSION_INFO_MAJOR_SHFT 24 +#define HFI_VERSION_INFO_MINOR_BMSK 0xFFFF00 +#define HFI_VERSION_INFO_MINOR_SHFT 8 +#define HFI_VERSION_INFO_STEP_BMSK 0xFF +#define HFI_VERSION_INFO_STEP_SHFT 0 + +#define HFI_MAX_POLL_TRY 5 + +#define HFI_MAX_PC_POLL_TRY 150 +#define HFI_POLL_TRY_SLEEP 1 + +static struct hfi_info *g_hfi; +unsigned int g_icp_mmu_hdl; +static DEFINE_MUTEX(hfi_cmd_q_mutex); +static DEFINE_MUTEX(hfi_msg_q_mutex); + +void cam_hfi_queue_dump(void) +{ + struct hfi_qtbl *qtbl; + struct hfi_qtbl_hdr *qtbl_hdr; + struct hfi_q_hdr *cmd_q_hdr, *msg_q_hdr; + struct hfi_mem_info *hfi_mem = NULL; + uint32_t *read_q, *read_ptr; + int i; + + hfi_mem = &g_hfi->map; + if (!hfi_mem) { + CAM_ERR(CAM_HFI, "Unable to dump queues hfi memory is NULL"); + return; + } + + qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva; + qtbl_hdr = &qtbl->q_tbl_hdr; + CAM_DBG(CAM_HFI, + "qtbl: version = %x size = %u num q = %u qhdr_size = %u", + qtbl_hdr->qtbl_version, qtbl_hdr->qtbl_size, + qtbl_hdr->qtbl_num_q, qtbl_hdr->qtbl_qhdr_size); + + cmd_q_hdr = &qtbl->q_hdr[Q_CMD]; + CAM_DBG(CAM_HFI, "cmd: size = %u r_idx = %u w_idx = %u addr = %x", + cmd_q_hdr->qhdr_q_size, cmd_q_hdr->qhdr_read_idx, + cmd_q_hdr->qhdr_write_idx, hfi_mem->cmd_q.iova); + read_q = (uint32_t *)g_hfi->map.cmd_q.kva; + read_ptr = (uint32_t *)(read_q + 0); + CAM_DBG(CAM_HFI, "CMD Q START"); + for (i = 0; i < ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT; i++) + CAM_DBG(CAM_HFI, "Word: %d Data: 0x%08x ", i, read_ptr[i]); + + msg_q_hdr = &qtbl->q_hdr[Q_MSG]; + CAM_DBG(CAM_HFI, "msg: size = %u r_idx = %u w_idx = %u addr = %x", + msg_q_hdr->qhdr_q_size, msg_q_hdr->qhdr_read_idx, + msg_q_hdr->qhdr_write_idx, hfi_mem->msg_q.iova); + read_q = (uint32_t *)g_hfi->map.msg_q.kva; + read_ptr = (uint32_t *)(read_q + 0); + CAM_DBG(CAM_HFI, "MSG Q START"); + for (i = 0; i < ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT; i++) + CAM_DBG(CAM_HFI, "Word: %d Data: 0x%08x ", i, read_ptr[i]); +} + +int hfi_write_cmd(void *cmd_ptr) +{ + uint32_t size_in_words, empty_space, new_write_idx, read_idx, temp; + uint32_t *write_q, *write_ptr; + struct hfi_qtbl *q_tbl; + struct hfi_q_hdr *q; + int rc = 0; + + if (!cmd_ptr) { + CAM_ERR(CAM_HFI, "command is null"); + return -EINVAL; + } + + mutex_lock(&hfi_cmd_q_mutex); + if (!g_hfi) { + CAM_ERR(CAM_HFI, "HFI interface not setup"); + rc = -ENODEV; + goto err; + } + + if (g_hfi->hfi_state != HFI_READY || + !g_hfi->cmd_q_state) { + CAM_ERR(CAM_HFI, "HFI state: %u, cmd q state: %u", + g_hfi->hfi_state, g_hfi->cmd_q_state); + rc = -ENODEV; + goto err; + } + + q_tbl = (struct hfi_qtbl *)g_hfi->map.qtbl.kva; + q = &q_tbl->q_hdr[Q_CMD]; + + write_q = (uint32_t *)g_hfi->map.cmd_q.kva; + + size_in_words = (*(uint32_t *)cmd_ptr) >> BYTE_WORD_SHIFT; + if (!size_in_words) { + CAM_DBG(CAM_HFI, "failed"); + rc = -EINVAL; + goto err; + } + + read_idx = q->qhdr_read_idx; + empty_space = (q->qhdr_write_idx >= read_idx) ? + (q->qhdr_q_size - (q->qhdr_write_idx - read_idx)) : + (read_idx - q->qhdr_write_idx); + if (empty_space <= size_in_words) { + CAM_ERR(CAM_HFI, "failed: empty space %u, size_in_words %u", + empty_space, size_in_words); + rc = -EIO; + goto err; + } + + new_write_idx = q->qhdr_write_idx + size_in_words; + write_ptr = (uint32_t *)(write_q + q->qhdr_write_idx); + + if (new_write_idx < q->qhdr_q_size) { + memcpy(write_ptr, (uint8_t *)cmd_ptr, + size_in_words << BYTE_WORD_SHIFT); + } else { + new_write_idx -= q->qhdr_q_size; + temp = (size_in_words - new_write_idx) << BYTE_WORD_SHIFT; + memcpy(write_ptr, (uint8_t *)cmd_ptr, temp); + memcpy(write_q, (uint8_t *)cmd_ptr + temp, + new_write_idx << BYTE_WORD_SHIFT); + } + + /* + * To make sure command data in a command queue before + * updating write index + */ + wmb(); + + q->qhdr_write_idx = new_write_idx; + + /* + * Before raising interrupt make sure command data is ready for + * firmware to process + */ + wmb(); + cam_io_w_mb((uint32_t)INTR_ENABLE, + g_hfi->csr_base + HFI_REG_A5_CSR_HOST2ICPINT); +err: + mutex_unlock(&hfi_cmd_q_mutex); + return rc; +} + +int hfi_read_message(uint32_t *pmsg, uint8_t q_id, + uint32_t *words_read) +{ + struct hfi_qtbl *q_tbl_ptr; + struct hfi_q_hdr *q; + uint32_t new_read_idx, size_in_words, word_diff, temp; + uint32_t *read_q, *read_ptr, *write_ptr; + uint32_t size_upper_bound = 0; + int rc = 0; + + if (!pmsg) { + CAM_ERR(CAM_HFI, "Invalid msg"); + return -EINVAL; + } + + if (q_id > Q_DBG) { + CAM_ERR(CAM_HFI, "Invalid q :%u", q_id); + return -EINVAL; + } + + mutex_lock(&hfi_msg_q_mutex); + if (!g_hfi) { + CAM_ERR(CAM_HFI, "hfi not set up yet"); + rc = -ENODEV; + goto err; + } + + if ((g_hfi->hfi_state != HFI_READY) || + !g_hfi->msg_q_state) { + CAM_ERR(CAM_HFI, "hfi state: %u, msg q state: %u", + g_hfi->hfi_state, g_hfi->msg_q_state); + rc = -ENODEV; + goto err; + } + + q_tbl_ptr = (struct hfi_qtbl *)g_hfi->map.qtbl.kva; + q = &q_tbl_ptr->q_hdr[q_id]; + + if (q->qhdr_read_idx == q->qhdr_write_idx) { + CAM_DBG(CAM_HFI, "Q not ready, state:%u, r idx:%u, w idx:%u", + g_hfi->hfi_state, q->qhdr_read_idx, q->qhdr_write_idx); + rc = -EIO; + goto err; + } + + if (q_id == Q_MSG) { + read_q = (uint32_t *)g_hfi->map.msg_q.kva; + size_upper_bound = ICP_HFI_MAX_PKT_SIZE_MSGQ_IN_WORDS; + } else { + read_q = (uint32_t *)g_hfi->map.dbg_q.kva; + size_upper_bound = ICP_HFI_MAX_PKT_SIZE_IN_WORDS; + } + + read_ptr = (uint32_t *)(read_q + q->qhdr_read_idx); + write_ptr = (uint32_t *)(read_q + q->qhdr_write_idx); + + if (write_ptr > read_ptr) + size_in_words = write_ptr - read_ptr; + else { + word_diff = read_ptr - write_ptr; + if (q_id == Q_MSG) + size_in_words = (ICP_MSG_Q_SIZE_IN_BYTES >> + BYTE_WORD_SHIFT) - word_diff; + else + size_in_words = (ICP_DBG_Q_SIZE_IN_BYTES >> + BYTE_WORD_SHIFT) - word_diff; + } + + if ((size_in_words == 0) || + (size_in_words > size_upper_bound)) { + CAM_ERR(CAM_HFI, "invalid HFI message packet size - 0x%08x", + size_in_words << BYTE_WORD_SHIFT); + q->qhdr_read_idx = q->qhdr_write_idx; + rc = -EIO; + goto err; + } + + new_read_idx = q->qhdr_read_idx + size_in_words; + + if (new_read_idx < q->qhdr_q_size) { + memcpy(pmsg, read_ptr, size_in_words << BYTE_WORD_SHIFT); + } else { + new_read_idx -= q->qhdr_q_size; + temp = (size_in_words - new_read_idx) << BYTE_WORD_SHIFT; + memcpy(pmsg, read_ptr, temp); + memcpy((uint8_t *)pmsg + temp, read_q, + new_read_idx << BYTE_WORD_SHIFT); + } + + q->qhdr_read_idx = new_read_idx; + *words_read = size_in_words; + /* Memory Barrier to make sure message + * queue parameters are updated after read + */ + wmb(); +err: + mutex_unlock(&hfi_msg_q_mutex); + return rc; +} + +int hfi_cmd_ubwc_config(uint32_t *ubwc_cfg) +{ + uint8_t *prop; + struct hfi_cmd_prop *dbg_prop; + uint32_t size = 0; + + size = sizeof(struct hfi_cmd_prop) + + sizeof(struct hfi_cmd_ubwc_cfg); + + CAM_DBG(CAM_HFI, + "size of ubwc %u, ubwc_cfg [rd-0x%x,wr-0x%x]", + size, ubwc_cfg[0], ubwc_cfg[1]); + + prop = kzalloc(size, GFP_KERNEL); + if (!prop) + return -ENOMEM; + + dbg_prop = (struct hfi_cmd_prop *)prop; + dbg_prop->size = size; + dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY; + dbg_prop->num_prop = 1; + dbg_prop->prop_data[0] = HFI_PROP_SYS_UBWC_CFG; + dbg_prop->prop_data[1] = ubwc_cfg[0]; + dbg_prop->prop_data[2] = ubwc_cfg[1]; + + hfi_write_cmd(prop); + kfree(prop); + + return 0; +} + +int hfi_cmd_ubwc_config_ext(uint32_t *ubwc_ipe_cfg, + uint32_t *ubwc_bps_cfg) +{ + uint8_t *prop; + struct hfi_cmd_prop *dbg_prop; + uint32_t size = 0; + + size = sizeof(struct hfi_cmd_prop) + + sizeof(struct hfi_cmd_ubwc_cfg_ext); + + CAM_DBG(CAM_HFI, + "size of ubwc %u, ubwc_ipe_cfg[rd-0x%x,wr-0x%x] ubwc_bps_cfg[rd-0x%x,wr-0x%x]", + size, ubwc_ipe_cfg[0], ubwc_ipe_cfg[1], + ubwc_bps_cfg[0], ubwc_bps_cfg[1]); + + prop = kzalloc(size, GFP_KERNEL); + if (!prop) + return -ENOMEM; + + dbg_prop = (struct hfi_cmd_prop *)prop; + dbg_prop->size = size; + dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY; + dbg_prop->num_prop = 1; + dbg_prop->prop_data[0] = HFI_PROPERTY_SYS_UBWC_CONFIG_EX; + dbg_prop->prop_data[1] = ubwc_bps_cfg[0]; + dbg_prop->prop_data[2] = ubwc_bps_cfg[1]; + dbg_prop->prop_data[3] = ubwc_ipe_cfg[0]; + dbg_prop->prop_data[4] = ubwc_ipe_cfg[1]; + + hfi_write_cmd(prop); + kfree(prop); + + return 0; +} + + +int hfi_enable_ipe_bps_pc(bool enable, uint32_t core_info) +{ + uint8_t *prop; + struct hfi_cmd_prop *dbg_prop; + uint32_t size = 0; + + size = sizeof(struct hfi_cmd_prop) + + sizeof(struct hfi_ipe_bps_pc); + + prop = kzalloc(size, GFP_KERNEL); + if (!prop) + return -ENOMEM; + + dbg_prop = (struct hfi_cmd_prop *)prop; + dbg_prop->size = size; + dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY; + dbg_prop->num_prop = 1; + dbg_prop->prop_data[0] = HFI_PROP_SYS_IPEBPS_PC; + dbg_prop->prop_data[1] = enable; + dbg_prop->prop_data[2] = core_info; + + hfi_write_cmd(prop); + kfree(prop); + + return 0; +} + +int hfi_set_debug_level(u64 a5_dbg_type, uint32_t lvl) +{ + uint8_t *prop; + struct hfi_cmd_prop *dbg_prop; + uint32_t size = 0, val; + + val = HFI_DEBUG_MSG_LOW | + HFI_DEBUG_MSG_MEDIUM | + HFI_DEBUG_MSG_HIGH | + HFI_DEBUG_MSG_ERROR | + HFI_DEBUG_MSG_FATAL | + HFI_DEBUG_MSG_PERF | + HFI_DEBUG_CFG_WFI | + HFI_DEBUG_CFG_ARM9WD; + + if (lvl > val) + return -EINVAL; + + size = sizeof(struct hfi_cmd_prop) + + sizeof(struct hfi_debug); + + prop = kzalloc(size, GFP_KERNEL); + if (!prop) + return -ENOMEM; + + dbg_prop = (struct hfi_cmd_prop *)prop; + dbg_prop->size = size; + dbg_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY; + dbg_prop->num_prop = 1; + dbg_prop->prop_data[0] = HFI_PROP_SYS_DEBUG_CFG; + dbg_prop->prop_data[1] = lvl; + dbg_prop->prop_data[2] = a5_dbg_type; + hfi_write_cmd(prop); + + kfree(prop); + + return 0; +} + +int hfi_set_fw_dump_level(uint32_t lvl) +{ + uint8_t *prop = NULL; + struct hfi_cmd_prop *fw_dump_level_switch_prop = NULL; + uint32_t size = 0; + + CAM_DBG(CAM_HFI, "fw dump ENTER"); + + size = sizeof(struct hfi_cmd_prop) + sizeof(lvl); + prop = kzalloc(size, GFP_KERNEL); + if (!prop) + return -ENOMEM; + + fw_dump_level_switch_prop = (struct hfi_cmd_prop *)prop; + fw_dump_level_switch_prop->size = size; + fw_dump_level_switch_prop->pkt_type = HFI_CMD_SYS_SET_PROPERTY; + fw_dump_level_switch_prop->num_prop = 1; + fw_dump_level_switch_prop->prop_data[0] = HFI_PROP_SYS_FW_DUMP_CFG; + fw_dump_level_switch_prop->prop_data[1] = lvl; + + CAM_DBG(CAM_HFI, "prop->size = %d\n" + "prop->pkt_type = %d\n" + "prop->num_prop = %d\n" + "prop->prop_data[0] = %d\n" + "prop->prop_data[1] = %d\n", + fw_dump_level_switch_prop->size, + fw_dump_level_switch_prop->pkt_type, + fw_dump_level_switch_prop->num_prop, + fw_dump_level_switch_prop->prop_data[0], + fw_dump_level_switch_prop->prop_data[1]); + + hfi_write_cmd(prop); + kfree(prop); + return 0; +} + +void hfi_send_system_cmd(uint32_t type, uint64_t data, uint32_t size) +{ + switch (type) { + case HFI_CMD_SYS_INIT: { + struct hfi_cmd_sys_init init; + + memset(&init, 0, sizeof(init)); + + init.size = sizeof(struct hfi_cmd_sys_init); + init.pkt_type = type; + hfi_write_cmd(&init); + } + break; + case HFI_CMD_SYS_PC_PREP: { + struct hfi_cmd_pc_prep prep; + + prep.size = sizeof(struct hfi_cmd_pc_prep); + prep.pkt_type = type; + hfi_write_cmd(&prep); + } + break; + case HFI_CMD_SYS_SET_PROPERTY: { + struct hfi_cmd_prop prop; + + if ((uint32_t)data == (uint32_t)HFI_PROP_SYS_DEBUG_CFG) { + prop.size = sizeof(struct hfi_cmd_prop); + prop.pkt_type = type; + prop.num_prop = 1; + prop.prop_data[0] = HFI_PROP_SYS_DEBUG_CFG; + hfi_write_cmd(&prop); + } + } + break; + case HFI_CMD_SYS_GET_PROPERTY: + break; + case HFI_CMD_SYS_PING: { + struct hfi_cmd_ping_pkt ping; + + ping.size = sizeof(struct hfi_cmd_ping_pkt); + ping.pkt_type = type; + ping.user_data = (uint64_t)data; + hfi_write_cmd(&ping); + } + break; + case HFI_CMD_SYS_RESET: { + struct hfi_cmd_sys_reset_pkt reset; + + reset.size = sizeof(struct hfi_cmd_sys_reset_pkt); + reset.pkt_type = type; + reset.user_data = (uint64_t)data; + hfi_write_cmd(&reset); + } + break; + case HFI_CMD_IPEBPS_CREATE_HANDLE: { + struct hfi_cmd_create_handle handle; + + handle.size = sizeof(struct hfi_cmd_create_handle); + handle.pkt_type = type; + handle.handle_type = (uint32_t)data; + handle.user_data1 = 0; + hfi_write_cmd(&handle); + } + break; + case HFI_CMD_IPEBPS_ASYNC_COMMAND_INDIRECT: + break; + default: + CAM_ERR(CAM_HFI, "command not supported :%d", type); + break; + } +} + + +int hfi_get_hw_caps(void *query_buf) +{ + int i = 0; + struct cam_icp_query_cap_cmd *query_cmd = NULL; + + if (!query_buf) { + CAM_ERR(CAM_HFI, "query buf is NULL"); + return -EINVAL; + } + + query_cmd = (struct cam_icp_query_cap_cmd *)query_buf; + query_cmd->fw_version.major = 0x12; + query_cmd->fw_version.minor = 0x12; + query_cmd->fw_version.revision = 0x12; + + query_cmd->api_version.major = 0x13; + query_cmd->api_version.minor = 0x13; + query_cmd->api_version.revision = 0x13; + + query_cmd->num_ipe = 2; + query_cmd->num_bps = 1; + + for (i = 0; i < CAM_ICP_DEV_TYPE_MAX; i++) { + query_cmd->dev_ver[i].dev_type = i; + query_cmd->dev_ver[i].hw_ver.major = 0x34 + i; + query_cmd->dev_ver[i].hw_ver.minor = 0x34 + i; + query_cmd->dev_ver[i].hw_ver.incr = 0x34 + i; + } + return 0; +} + +void cam_hfi_disable_cpu(void __iomem *icp_base) +{ + uint32_t data; + uint32_t val; + uint32_t try = 0; + + while (try < HFI_MAX_PC_POLL_TRY) { + data = cam_io_r_mb(icp_base + HFI_REG_A5_CSR_A5_STATUS); + CAM_DBG(CAM_HFI, "wfi status = %x\n", (int)data); + + if (data & ICP_CSR_A5_STATUS_WFI) + break; + /* Need to poll here to confirm that FW is going trigger wfi + * and Host can the proceed. No interrupt is expected from FW + * at this time. + */ + usleep_range(HFI_POLL_TRY_SLEEP * 1000, + (HFI_POLL_TRY_SLEEP * 1000) + 1000); + try++; + } + + val = cam_io_r(icp_base + HFI_REG_A5_CSR_A5_CONTROL); + val &= ~(ICP_FLAG_CSR_A5_EN | ICP_FLAG_CSR_WAKE_UP_EN); + cam_io_w_mb(val, icp_base + HFI_REG_A5_CSR_A5_CONTROL); + + val = cam_io_r(icp_base + HFI_REG_A5_CSR_NSEC_RESET); + cam_io_w_mb(val, icp_base + HFI_REG_A5_CSR_NSEC_RESET); + + cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_RESET, + icp_base + HFI_REG_HOST_ICP_INIT_REQUEST); + cam_io_w_mb((uint32_t)INTR_DISABLE, + icp_base + HFI_REG_A5_CSR_A2HOSTINTEN); +} + +void cam_hfi_enable_cpu(void __iomem *icp_base) +{ + cam_io_w_mb((uint32_t)ICP_FLAG_CSR_A5_EN, + icp_base + HFI_REG_A5_CSR_A5_CONTROL); + cam_io_w_mb((uint32_t)0x10, icp_base + HFI_REG_A5_CSR_NSEC_RESET); +} + +int cam_hfi_resume(struct hfi_mem_info *hfi_mem, + void __iomem *icp_base, bool debug) +{ + int rc = 0; + uint32_t data; + uint32_t fw_version, status = 0; + uint32_t retry_cnt = 0; + + cam_hfi_enable_cpu(icp_base); + g_hfi->csr_base = icp_base; + + if (debug) { + cam_io_w_mb(ICP_FLAG_A5_CTRL_DBG_EN, + (icp_base + HFI_REG_A5_CSR_A5_CONTROL)); + + /* Barrier needed as next write should be done after + * sucessful previous write. Next write enable clock + * gating + */ + wmb(); + + cam_io_w_mb((uint32_t)ICP_FLAG_A5_CTRL_EN, + icp_base + HFI_REG_A5_CSR_A5_CONTROL); + + } else { + cam_io_w_mb((uint32_t)ICP_FLAG_A5_CTRL_EN, + icp_base + HFI_REG_A5_CSR_A5_CONTROL); + } + + while (retry_cnt < HFI_MAX_POLL_TRY) { + readw_poll_timeout((icp_base + HFI_REG_ICP_HOST_INIT_RESPONSE), + status, (status == ICP_INIT_RESP_SUCCESS), 100, 10000); + + CAM_DBG(CAM_HFI, "1: status = %u", status); + status = cam_io_r_mb(icp_base + HFI_REG_ICP_HOST_INIT_RESPONSE); + CAM_DBG(CAM_HFI, "2: status = %u", status); + if (status == ICP_INIT_RESP_SUCCESS) + break; + + if (status == ICP_INIT_RESP_FAILED) { + CAM_ERR(CAM_HFI, "ICP Init Failed. status = %u", + status); + fw_version = cam_io_r(icp_base + HFI_REG_FW_VERSION); + CAM_ERR(CAM_HFI, "fw version : [%x]", fw_version); + return -EINVAL; + } + retry_cnt++; + } + + if ((retry_cnt == HFI_MAX_POLL_TRY) && + (status == ICP_INIT_RESP_RESET)) { + CAM_ERR(CAM_HFI, "Reached Max retries. status = %u", + status); + fw_version = cam_io_r(icp_base + HFI_REG_FW_VERSION); + CAM_ERR(CAM_HFI, "fw version : [%x]", fw_version); + return -EINVAL; + } + + cam_io_w_mb((uint32_t)(INTR_ENABLE|INTR_ENABLE_WD0), + icp_base + HFI_REG_A5_CSR_A2HOSTINTEN); + + fw_version = cam_io_r(icp_base + HFI_REG_FW_VERSION); + CAM_DBG(CAM_HFI, "fw version : [%x]", fw_version); + + data = cam_io_r(icp_base + HFI_REG_A5_CSR_A5_STATUS); + CAM_DBG(CAM_HFI, "wfi status = %x", (int)data); + + cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova, icp_base + HFI_REG_QTBL_PTR); + cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova, + icp_base + HFI_REG_SFR_PTR); + cam_io_w_mb((uint32_t)hfi_mem->shmem.iova, + icp_base + HFI_REG_SHARED_MEM_PTR); + cam_io_w_mb((uint32_t)hfi_mem->shmem.len, + icp_base + HFI_REG_SHARED_MEM_SIZE); + cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova, + icp_base + HFI_REG_UNCACHED_HEAP_PTR); + cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len, + icp_base + HFI_REG_UNCACHED_HEAP_SIZE); + cam_io_w_mb((uint32_t)hfi_mem->qdss.iova, + icp_base + HFI_REG_QDSS_IOVA); + cam_io_w_mb((uint32_t)hfi_mem->qdss.len, + icp_base + HFI_REG_QDSS_IOVA_SIZE); + cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova, + icp_base + HFI_REG_IO_REGION_IOVA); + cam_io_w_mb((uint32_t)hfi_mem->io_mem.len, + icp_base + HFI_REG_IO_REGION_SIZE); + + cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova, + icp_base + HFI_REG_IO2_REGION_IOVA); + cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len, + icp_base + HFI_REG_IO2_REGION_SIZE); + + CAM_INFO(CAM_HFI, "Resume IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]", + hfi_mem->io_mem.iova, hfi_mem->io_mem.len, + hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len); + + return rc; +} + +int cam_hfi_init(uint8_t event_driven_mode, struct hfi_mem_info *hfi_mem, + void __iomem *icp_base, bool debug) +{ + int rc = 0; + struct hfi_qtbl *qtbl; + struct hfi_qtbl_hdr *qtbl_hdr; + struct hfi_q_hdr *cmd_q_hdr, *msg_q_hdr, *dbg_q_hdr; + uint32_t hw_version, fw_version, status = 0; + uint32_t retry_cnt = 0; + struct sfr_buf *sfr_buffer; + + mutex_lock(&hfi_cmd_q_mutex); + mutex_lock(&hfi_msg_q_mutex); + + if (!g_hfi) { + g_hfi = kzalloc(sizeof(struct hfi_info), GFP_KERNEL); + if (!g_hfi) { + rc = -ENOMEM; + goto alloc_fail; + } + } + + if (g_hfi->hfi_state != HFI_DEINIT) { + CAM_ERR(CAM_HFI, "hfi_init: invalid state"); + return -EINVAL; + } + + memcpy(&g_hfi->map, hfi_mem, sizeof(g_hfi->map)); + g_hfi->hfi_state = HFI_DEINIT; + if (debug) { + cam_io_w_mb( + (uint32_t)(ICP_FLAG_CSR_A5_EN | ICP_FLAG_CSR_WAKE_UP_EN | + ICP_CSR_EDBGRQ | ICP_CSR_DBGSWENABLE), + icp_base + HFI_REG_A5_CSR_A5_CONTROL); + msleep(100); + cam_io_w_mb((uint32_t)(ICP_FLAG_CSR_A5_EN | + ICP_FLAG_CSR_WAKE_UP_EN | ICP_CSR_EN_CLKGATE_WFI), + icp_base + HFI_REG_A5_CSR_A5_CONTROL); + } else { + /* Due to hardware bug in V1 ICP clock gating has to be + * disabled, this is supposed to be fixed in V-2. But enabling + * the clock gating is causing the firmware hang, hence + * disabling the clock gating on both V1 and V2 until the + * hardware team root causes this + */ + cam_io_w_mb((uint32_t)ICP_FLAG_CSR_A5_EN | + ICP_FLAG_CSR_WAKE_UP_EN | + ICP_CSR_EN_CLKGATE_WFI, + icp_base + HFI_REG_A5_CSR_A5_CONTROL); + } + + qtbl = (struct hfi_qtbl *)hfi_mem->qtbl.kva; + qtbl_hdr = &qtbl->q_tbl_hdr; + qtbl_hdr->qtbl_version = 0xFFFFFFFF; + qtbl_hdr->qtbl_size = sizeof(struct hfi_qtbl); + qtbl_hdr->qtbl_qhdr0_offset = sizeof(struct hfi_qtbl_hdr); + qtbl_hdr->qtbl_qhdr_size = sizeof(struct hfi_q_hdr); + qtbl_hdr->qtbl_num_q = ICP_HFI_NUMBER_OF_QS; + qtbl_hdr->qtbl_num_active_q = ICP_HFI_NUMBER_OF_QS; + + /* setup host-to-firmware command queue */ + cmd_q_hdr = &qtbl->q_hdr[Q_CMD]; + cmd_q_hdr->qhdr_status = QHDR_ACTIVE; + cmd_q_hdr->qhdr_start_addr = hfi_mem->cmd_q.iova; + cmd_q_hdr->qhdr_q_size = ICP_CMD_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT; + cmd_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT; + cmd_q_hdr->qhdr_pkt_drop_cnt = RESET; + cmd_q_hdr->qhdr_read_idx = RESET; + cmd_q_hdr->qhdr_write_idx = RESET; + + /* setup firmware-to-Host message queue */ + msg_q_hdr = &qtbl->q_hdr[Q_MSG]; + msg_q_hdr->qhdr_status = QHDR_ACTIVE; + msg_q_hdr->qhdr_start_addr = hfi_mem->msg_q.iova; + msg_q_hdr->qhdr_q_size = ICP_MSG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT; + msg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT; + msg_q_hdr->qhdr_pkt_drop_cnt = RESET; + msg_q_hdr->qhdr_read_idx = RESET; + msg_q_hdr->qhdr_write_idx = RESET; + + /* setup firmware-to-Host message queue */ + dbg_q_hdr = &qtbl->q_hdr[Q_DBG]; + dbg_q_hdr->qhdr_status = QHDR_ACTIVE; + dbg_q_hdr->qhdr_start_addr = hfi_mem->dbg_q.iova; + dbg_q_hdr->qhdr_q_size = ICP_DBG_Q_SIZE_IN_BYTES >> BYTE_WORD_SHIFT; + dbg_q_hdr->qhdr_pkt_size = ICP_HFI_VAR_SIZE_PKT; + dbg_q_hdr->qhdr_pkt_drop_cnt = RESET; + dbg_q_hdr->qhdr_read_idx = RESET; + dbg_q_hdr->qhdr_write_idx = RESET; + + sfr_buffer = (struct sfr_buf *)hfi_mem->sfr_buf.kva; + sfr_buffer->size = ICP_MSG_SFR_SIZE_IN_BYTES; + + switch (event_driven_mode) { + case INTR_MODE: + cmd_q_hdr->qhdr_type = Q_CMD; + cmd_q_hdr->qhdr_rx_wm = SET; + cmd_q_hdr->qhdr_tx_wm = SET; + cmd_q_hdr->qhdr_rx_req = SET; + cmd_q_hdr->qhdr_tx_req = RESET; + cmd_q_hdr->qhdr_rx_irq_status = RESET; + cmd_q_hdr->qhdr_tx_irq_status = RESET; + + msg_q_hdr->qhdr_type = Q_MSG; + msg_q_hdr->qhdr_rx_wm = SET; + msg_q_hdr->qhdr_tx_wm = SET; + msg_q_hdr->qhdr_rx_req = SET; + msg_q_hdr->qhdr_tx_req = RESET; + msg_q_hdr->qhdr_rx_irq_status = RESET; + msg_q_hdr->qhdr_tx_irq_status = RESET; + + dbg_q_hdr->qhdr_type = Q_DBG; + dbg_q_hdr->qhdr_rx_wm = SET; + dbg_q_hdr->qhdr_tx_wm = SET_WM; + dbg_q_hdr->qhdr_rx_req = RESET; + dbg_q_hdr->qhdr_tx_req = RESET; + dbg_q_hdr->qhdr_rx_irq_status = RESET; + dbg_q_hdr->qhdr_tx_irq_status = RESET; + + break; + + case POLL_MODE: + cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_POLL_MODE_2 | + RX_EVENT_POLL_MODE_2; + msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_POLL_MODE_2 | + RX_EVENT_POLL_MODE_2; + dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_POLL_MODE_2 | + RX_EVENT_POLL_MODE_2; + break; + + case WM_MODE: + cmd_q_hdr->qhdr_type = Q_CMD | TX_EVENT_DRIVEN_MODE_2 | + RX_EVENT_DRIVEN_MODE_2; + cmd_q_hdr->qhdr_rx_wm = SET; + cmd_q_hdr->qhdr_tx_wm = SET; + cmd_q_hdr->qhdr_rx_req = RESET; + cmd_q_hdr->qhdr_tx_req = SET; + cmd_q_hdr->qhdr_rx_irq_status = RESET; + cmd_q_hdr->qhdr_tx_irq_status = RESET; + + msg_q_hdr->qhdr_type = Q_MSG | TX_EVENT_DRIVEN_MODE_2 | + RX_EVENT_DRIVEN_MODE_2; + msg_q_hdr->qhdr_rx_wm = SET; + msg_q_hdr->qhdr_tx_wm = SET; + msg_q_hdr->qhdr_rx_req = SET; + msg_q_hdr->qhdr_tx_req = RESET; + msg_q_hdr->qhdr_rx_irq_status = RESET; + msg_q_hdr->qhdr_tx_irq_status = RESET; + + dbg_q_hdr->qhdr_type = Q_DBG | TX_EVENT_DRIVEN_MODE_2 | + RX_EVENT_DRIVEN_MODE_2; + dbg_q_hdr->qhdr_rx_wm = SET; + dbg_q_hdr->qhdr_tx_wm = SET_WM; + dbg_q_hdr->qhdr_rx_req = RESET; + dbg_q_hdr->qhdr_tx_req = RESET; + dbg_q_hdr->qhdr_rx_irq_status = RESET; + dbg_q_hdr->qhdr_tx_irq_status = RESET; + break; + + default: + CAM_ERR(CAM_HFI, "Invalid event driven mode :%u", + event_driven_mode); + break; + } + + cam_io_w_mb((uint32_t)hfi_mem->qtbl.iova, + icp_base + HFI_REG_QTBL_PTR); + cam_io_w_mb((uint32_t)hfi_mem->sfr_buf.iova, + icp_base + HFI_REG_SFR_PTR); + cam_io_w_mb((uint32_t)hfi_mem->shmem.iova, + icp_base + HFI_REG_SHARED_MEM_PTR); + cam_io_w_mb((uint32_t)hfi_mem->shmem.len, + icp_base + HFI_REG_SHARED_MEM_SIZE); + cam_io_w_mb((uint32_t)hfi_mem->sec_heap.iova, + icp_base + HFI_REG_UNCACHED_HEAP_PTR); + cam_io_w_mb((uint32_t)hfi_mem->sec_heap.len, + icp_base + HFI_REG_UNCACHED_HEAP_SIZE); + cam_io_w_mb((uint32_t)ICP_INIT_REQUEST_SET, + icp_base + HFI_REG_HOST_ICP_INIT_REQUEST); + cam_io_w_mb((uint32_t)hfi_mem->qdss.iova, + icp_base + HFI_REG_QDSS_IOVA); + cam_io_w_mb((uint32_t)hfi_mem->qdss.len, + icp_base + HFI_REG_QDSS_IOVA_SIZE); + cam_io_w_mb((uint32_t)hfi_mem->io_mem.iova, + icp_base + HFI_REG_IO_REGION_IOVA); + cam_io_w_mb((uint32_t)hfi_mem->io_mem.len, + icp_base + HFI_REG_IO_REGION_SIZE); + cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova, + icp_base + HFI_REG_IO2_REGION_IOVA); + cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len, + icp_base + HFI_REG_IO2_REGION_SIZE); + + CAM_INFO(CAM_HFI, "Init IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]", + hfi_mem->io_mem.iova, hfi_mem->io_mem.len, + hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len); + + hw_version = cam_io_r(icp_base + HFI_REG_A5_HW_VERSION); + + while (retry_cnt < HFI_MAX_POLL_TRY) { + readw_poll_timeout((icp_base + HFI_REG_ICP_HOST_INIT_RESPONSE), + status, (status == ICP_INIT_RESP_SUCCESS), 100, 10000); + + CAM_DBG(CAM_HFI, "1: status = %u rc = %d", status, rc); + status = cam_io_r_mb(icp_base + HFI_REG_ICP_HOST_INIT_RESPONSE); + CAM_DBG(CAM_HFI, "2: status = %u rc = %d", status, rc); + if (status == ICP_INIT_RESP_SUCCESS) + break; + + if (status == ICP_INIT_RESP_FAILED) { + CAM_ERR(CAM_HFI, "ICP Init Failed. status = %u", + status); + fw_version = cam_io_r(icp_base + HFI_REG_FW_VERSION); + CAM_ERR(CAM_HFI, "fw version : [%x]", fw_version); + goto regions_fail; + } + retry_cnt++; + } + + if ((retry_cnt == HFI_MAX_POLL_TRY) && + (status == ICP_INIT_RESP_RESET)) { + CAM_ERR(CAM_HFI, "Reached Max retries. status = %u", + status); + fw_version = cam_io_r(icp_base + HFI_REG_FW_VERSION); + CAM_ERR(CAM_HFI, + "hw version : : [%x], fw version : [%x]", + hw_version, fw_version); + goto regions_fail; + } + + fw_version = cam_io_r(icp_base + HFI_REG_FW_VERSION); + CAM_DBG(CAM_HFI, "hw version : : [%x], fw version : [%x]", + hw_version, fw_version); + + g_hfi->csr_base = icp_base; + g_hfi->hfi_state = HFI_READY; + g_hfi->cmd_q_state = true; + g_hfi->msg_q_state = true; + cam_io_w_mb((uint32_t)(INTR_ENABLE|INTR_ENABLE_WD0), + icp_base + HFI_REG_A5_CSR_A2HOSTINTEN); + + mutex_unlock(&hfi_cmd_q_mutex); + mutex_unlock(&hfi_msg_q_mutex); + + return rc; +regions_fail: + kfree(g_hfi); + g_hfi = NULL; +alloc_fail: + mutex_unlock(&hfi_cmd_q_mutex); + mutex_unlock(&hfi_msg_q_mutex); + return rc; +} + +void cam_hfi_deinit(void __iomem *icp_base) +{ + mutex_lock(&hfi_cmd_q_mutex); + mutex_lock(&hfi_msg_q_mutex); + + if (!g_hfi) { + CAM_ERR(CAM_HFI, "hfi path not established yet"); + goto err; + } + + g_hfi->cmd_q_state = false; + g_hfi->msg_q_state = false; + + kzfree(g_hfi); + g_hfi = NULL; + +err: + mutex_unlock(&hfi_cmd_q_mutex); + mutex_unlock(&hfi_msg_q_mutex); +} diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/Makefile b/techpack/camera-bengal/drivers/cam_icp/icp_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..e73069ba78c9bc68d8ed960515ef47c6f2953f0c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += icp_hw_mgr/ a5_hw/ ipe_hw/ bps_hw/ diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/Makefile b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..e9bcc6a6b80453df687f3ac914940a4bf848b835 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/fw_inc +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += a5_dev.o a5_core.o a5_soc.o diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_core.c b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_core.c new file mode 100644 index 0000000000000000000000000000000000000000..1ac27511f7ac9c8633ea8a24b2875734382eaa69 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_core.c @@ -0,0 +1,604 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_io_util.h" +#include "cam_a5_hw_intf.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "a5_core.h" +#include "a5_soc.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "hfi_intf.h" +#include "hfi_sys_defs.h" +#include "cam_icp_hw_mgr_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" + +static int cam_a5_cpas_vote(struct cam_a5_device_core_info *core_info, + struct cam_icp_cpas_vote *cpas_vote) +{ + int rc = 0; + + if (cpas_vote->ahb_vote_valid) + rc = cam_cpas_update_ahb_vote(core_info->cpas_handle, + &cpas_vote->ahb_vote); + + if (cpas_vote->axi_vote_valid) + rc = cam_cpas_update_axi_vote(core_info->cpas_handle, + &cpas_vote->axi_vote); + + if (rc) + CAM_ERR(CAM_ICP, "cpas vote is failed: %d", rc); + + return rc; +} + +static int32_t cam_icp_validate_fw(const uint8_t *elf) +{ + struct elf32_hdr *elf_hdr; + + if (!elf) { + CAM_ERR(CAM_ICP, "Invalid params"); + return -EINVAL; + } + + elf_hdr = (struct elf32_hdr *)elf; + + if (memcmp(elf_hdr->e_ident, ELFMAG, SELFMAG)) { + CAM_ERR(CAM_ICP, "ICP elf identifier is failed"); + return -EINVAL; + } + + /* check architecture */ + if (elf_hdr->e_machine != EM_ARM) { + CAM_ERR(CAM_ICP, "unsupported arch"); + return -EINVAL; + } + + /* check elf bit format */ + if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32) { + CAM_ERR(CAM_ICP, "elf doesn't support 32 bit format"); + return -EINVAL; + } + + return 0; +} + +static int32_t cam_icp_get_fw_size(const uint8_t *elf, uint32_t *fw_size) +{ + int32_t rc = 0; + int32_t i = 0; + uint32_t num_prg_hdrs; + unsigned char *icp_prg_hdr_tbl; + uint32_t seg_mem_size = 0; + struct elf32_hdr *elf_hdr; + struct elf32_phdr *prg_hdr; + + if (!elf || !fw_size) { + CAM_ERR(CAM_ICP, "invalid args"); + return -EINVAL; + } + + *fw_size = 0; + + elf_hdr = (struct elf32_hdr *)elf; + num_prg_hdrs = elf_hdr->e_phnum; + icp_prg_hdr_tbl = (unsigned char *)elf + elf_hdr->e_phoff; + prg_hdr = (struct elf32_phdr *)&icp_prg_hdr_tbl[0]; + + if (!prg_hdr) { + CAM_ERR(CAM_ICP, "failed to get elf program header attr"); + return -EINVAL; + } + + CAM_DBG(CAM_ICP, "num_prg_hdrs = %d", num_prg_hdrs); + for (i = 0; i < num_prg_hdrs; i++, prg_hdr++) { + if (prg_hdr->p_flags == 0) + continue; + + seg_mem_size = (prg_hdr->p_memsz + prg_hdr->p_align - 1) & + ~(prg_hdr->p_align - 1); + seg_mem_size += prg_hdr->p_vaddr; + CAM_DBG(CAM_ICP, "memsz:%x align:%x addr:%x seg_mem_size:%x", + (int)prg_hdr->p_memsz, (int)prg_hdr->p_align, + (int)prg_hdr->p_vaddr, (int)seg_mem_size); + if (*fw_size < seg_mem_size) + *fw_size = seg_mem_size; + + } + + if (*fw_size == 0) { + CAM_ERR(CAM_ICP, "invalid elf fw file"); + return -EINVAL; + } + + return rc; +} + +static int32_t cam_icp_program_fw(const uint8_t *elf, + struct cam_a5_device_core_info *core_info) +{ + int32_t rc = 0; + uint32_t num_prg_hdrs; + unsigned char *icp_prg_hdr_tbl; + int32_t i = 0; + u8 *dest; + u8 *src; + struct elf32_hdr *elf_hdr; + struct elf32_phdr *prg_hdr; + + elf_hdr = (struct elf32_hdr *)elf; + num_prg_hdrs = elf_hdr->e_phnum; + icp_prg_hdr_tbl = (unsigned char *)elf + elf_hdr->e_phoff; + prg_hdr = (struct elf32_phdr *)&icp_prg_hdr_tbl[0]; + + if (!prg_hdr) { + CAM_ERR(CAM_ICP, "failed to get elf program header attr"); + return -EINVAL; + } + + for (i = 0; i < num_prg_hdrs; i++, prg_hdr++) { + if (prg_hdr->p_flags == 0) + continue; + + CAM_DBG(CAM_ICP, "Loading FW header size: %u", + prg_hdr->p_filesz); + if (prg_hdr->p_filesz != 0) { + src = (u8 *)((u8 *)elf + prg_hdr->p_offset); + dest = (u8 *)(((u8 *)core_info->fw_kva_addr) + + prg_hdr->p_vaddr); + + memcpy_toio(dest, src, prg_hdr->p_filesz); + } + } + + return rc; +} + +static int32_t cam_a5_download_fw(void *device_priv) +{ + int32_t rc = 0; + uint32_t fw_size; + const uint8_t *fw_start = NULL; + struct cam_hw_info *a5_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_a5_device_core_info *core_info = NULL; + struct cam_a5_device_hw_info *hw_info = NULL; + struct platform_device *pdev = NULL; + struct a5_soc_info *cam_a5_soc_info = NULL; + + if (!device_priv) { + CAM_ERR(CAM_ICP, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &a5_dev->soc_info; + core_info = (struct cam_a5_device_core_info *)a5_dev->core_info; + hw_info = core_info->a5_hw_info; + pdev = soc_info->pdev; + cam_a5_soc_info = soc_info->soc_private; + + rc = request_firmware(&core_info->fw_elf, "CAMERA_ICP.elf", &pdev->dev); + if (rc) { + CAM_ERR(CAM_ICP, "Failed to locate fw: %d", rc); + return rc; + } + + if (!core_info->fw_elf) { + CAM_ERR(CAM_ICP, "Invalid elf size"); + rc = -EINVAL; + goto fw_download_failed; + } + + fw_start = core_info->fw_elf->data; + rc = cam_icp_validate_fw(fw_start); + if (rc) { + CAM_ERR(CAM_ICP, "fw elf validation failed"); + goto fw_download_failed; + } + + rc = cam_icp_get_fw_size(fw_start, &fw_size); + if (rc) { + CAM_ERR(CAM_ICP, "unable to get fw size"); + goto fw_download_failed; + } + + if (core_info->fw_buf_len < fw_size) { + CAM_ERR(CAM_ICP, "mismatch in fw size: %u %llu", + fw_size, core_info->fw_buf_len); + rc = -EINVAL; + goto fw_download_failed; + } + + rc = cam_icp_program_fw(fw_start, core_info); + if (rc) { + CAM_ERR(CAM_ICP, "fw program is failed"); + goto fw_download_failed; + } + +fw_download_failed: + release_firmware(core_info->fw_elf); + return rc; +} + +static int cam_a5_fw_dump( + struct cam_icp_hw_dump_args *dump_args, + struct cam_a5_device_core_info *core_info) +{ + u8 *dest; + u8 *src; + uint64_t size_required; + struct cam_icp_dump_header *hdr; + + if (!core_info || !dump_args) { + CAM_ERR(CAM_ICP, "invalid params %pK %pK", + core_info, dump_args); + return -EINVAL; + } + if (!core_info->fw_kva_addr || !dump_args->cpu_addr) { + CAM_ERR(CAM_ICP, "invalid params %pK, 0x%zx", + core_info->fw_kva_addr, dump_args->cpu_addr); + return -EINVAL; + } + + size_required = core_info->fw_buf_len + + sizeof(struct cam_icp_dump_header); + + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_ICP, "Dump offset overshoot len %zu offset %zu", + dump_args->buf_len, dump_args->offset); + return -ENOSPC; + } + + if ((dump_args->buf_len - dump_args->offset) < size_required) { + CAM_WARN(CAM_ICP, "Dump buffer exhaust required %llu len %llu", + size_required, core_info->fw_buf_len); + return -ENOSPC; + } + + dest = (u8 *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_icp_dump_header *)dest; + scnprintf(hdr->tag, CAM_ICP_DUMP_TAG_MAX_LEN, "ICP_FW:"); + hdr->word_size = sizeof(u8); + hdr->size = core_info->fw_buf_len; + src = (u8 *)core_info->fw_kva_addr; + dest = (u8 *)dest + sizeof(struct cam_icp_dump_header); + memcpy_fromio(dest, src, core_info->fw_buf_len); + dump_args->offset += hdr->size + sizeof(struct cam_icp_dump_header); + return 0; +} + +int cam_a5_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *a5_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_a5_device_core_info *core_info = NULL; + struct a5_soc_info *a5_soc_info; + struct cam_icp_cpas_vote cpas_vote; + int rc = 0; + + if (!device_priv) { + CAM_ERR(CAM_ICP, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &a5_dev->soc_info; + core_info = (struct cam_a5_device_core_info *)a5_dev->core_info; + + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_ICP, "soc_info: %pK core_info: %pK", + soc_info, core_info); + return -EINVAL; + } + + a5_soc_info = soc_info->soc_private; + + cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE; + cpas_vote.ahb_vote.vote.level = CAM_LOWSVS_VOTE; + cpas_vote.axi_vote.num_paths = 1; + cpas_vote.axi_vote.axi_path[0].path_data_type = + CAM_ICP_DEFAULT_AXI_PATH; + cpas_vote.axi_vote.axi_path[0].transac_type = + CAM_ICP_DEFAULT_AXI_TRANSAC; + cpas_vote.axi_vote.axi_path[0].camnoc_bw = + CAM_ICP_A5_BW_BYTES_VOTE; + cpas_vote.axi_vote.axi_path[0].mnoc_ab_bw = + CAM_ICP_A5_BW_BYTES_VOTE; + cpas_vote.axi_vote.axi_path[0].mnoc_ib_bw = + CAM_ICP_A5_BW_BYTES_VOTE; + cpas_vote.axi_vote.axi_path[0].ddr_ab_bw = + CAM_ICP_A5_BW_BYTES_VOTE; + cpas_vote.axi_vote.axi_path[0].ddr_ib_bw = + CAM_ICP_A5_BW_BYTES_VOTE; + + rc = cam_cpas_start(core_info->cpas_handle, + &cpas_vote.ahb_vote, &cpas_vote.axi_vote); + if (rc) { + CAM_ERR(CAM_ICP, "cpas start failed: %d", rc); + goto error; + } + core_info->cpas_start = true; + + rc = cam_a5_enable_soc_resources(soc_info); + if (rc) { + CAM_ERR(CAM_ICP, "soc enable is failed: %d", rc); + if (cam_cpas_stop(core_info->cpas_handle)) + CAM_ERR(CAM_ICP, "cpas stop is failed"); + else + core_info->cpas_start = false; + } else { + CAM_DBG(CAM_ICP, "a5_qos %d", a5_soc_info->a5_qos_val); + if (a5_soc_info->a5_qos_val) + cam_io_w_mb(a5_soc_info->a5_qos_val, + soc_info->reg_map[A5_SIERRA_BASE].mem_base + + ICP_SIERRA_A5_CSR_ACCESS); + } + +error: + return rc; +} + +int cam_a5_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *a5_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_a5_device_core_info *core_info = NULL; + int rc = 0; + + if (!device_priv) { + CAM_ERR(CAM_ICP, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &a5_dev->soc_info; + core_info = (struct cam_a5_device_core_info *)a5_dev->core_info; + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_ICP, "soc_info = %pK core_info = %pK", + soc_info, core_info); + return -EINVAL; + } + + rc = cam_a5_disable_soc_resources(soc_info); + if (rc) + CAM_ERR(CAM_ICP, "soc disable is failed: %d", rc); + + if (core_info->cpas_start) { + if (cam_cpas_stop(core_info->cpas_handle)) + CAM_ERR(CAM_ICP, "cpas stop is failed"); + else + core_info->cpas_start = false; + } + + return rc; +} + +irqreturn_t cam_a5_irq(int irq_num, void *data) +{ + struct cam_hw_info *a5_dev = data; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_a5_device_core_info *core_info = NULL; + struct cam_a5_device_hw_info *hw_info = NULL; + uint32_t irq_status = 0; + + if (!data) { + CAM_ERR(CAM_ICP, "Invalid cam_dev_info or query_cap args"); + return IRQ_HANDLED; + } + + soc_info = &a5_dev->soc_info; + core_info = (struct cam_a5_device_core_info *)a5_dev->core_info; + hw_info = core_info->a5_hw_info; + + irq_status = cam_io_r_mb(soc_info->reg_map[A5_SIERRA_BASE].mem_base + + core_info->a5_hw_info->a5_host_int_status); + + cam_io_w_mb(irq_status, + soc_info->reg_map[A5_SIERRA_BASE].mem_base + + core_info->a5_hw_info->a5_host_int_clr); + + if ((irq_status & A5_WDT_0) || + (irq_status & A5_WDT_1)) { + CAM_ERR_RATE_LIMIT(CAM_ICP, "watch dog interrupt from A5"); + } + + spin_lock(&a5_dev->hw_lock); + if (core_info->irq_cb.icp_hw_mgr_cb) + core_info->irq_cb.icp_hw_mgr_cb(irq_status, + core_info->irq_cb.data); + spin_unlock(&a5_dev->hw_lock); + + return IRQ_HANDLED; +} + +int cam_a5_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + struct cam_hw_info *a5_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_a5_device_core_info *core_info = NULL; + struct cam_a5_device_hw_info *hw_info = NULL; + struct a5_soc_info *a5_soc = NULL; + unsigned long flags; + uint32_t ubwc_ipe_cfg[ICP_UBWC_MAX] = {0}; + uint32_t ubwc_bps_cfg[ICP_UBWC_MAX] = {0}; + uint32_t index = 0; + int rc = 0, ddr_type = 0; + + if (!device_priv) { + CAM_ERR(CAM_ICP, "Invalid arguments"); + return -EINVAL; + } + + if (cmd_type >= CAM_ICP_A5_CMD_MAX) { + CAM_ERR(CAM_ICP, "Invalid command : %x", cmd_type); + return -EINVAL; + } + + soc_info = &a5_dev->soc_info; + core_info = (struct cam_a5_device_core_info *)a5_dev->core_info; + hw_info = core_info->a5_hw_info; + + switch (cmd_type) { + case CAM_ICP_A5_CMD_FW_DOWNLOAD: + rc = cam_a5_download_fw(device_priv); + break; + case CAM_ICP_A5_CMD_SET_FW_BUF: { + struct cam_icp_a5_set_fw_buf_info *fw_buf_info = cmd_args; + + if (!cmd_args) { + CAM_ERR(CAM_ICP, "cmd args NULL"); + return -EINVAL; + } + + core_info->fw_buf = fw_buf_info->iova; + core_info->fw_kva_addr = fw_buf_info->kva; + core_info->fw_buf_len = fw_buf_info->len; + + CAM_DBG(CAM_ICP, "fw buf info = %x %llx %lld", + core_info->fw_buf, core_info->fw_kva_addr, + core_info->fw_buf_len); + break; + } + case CAM_ICP_A5_SET_IRQ_CB: { + struct cam_icp_a5_set_irq_cb *irq_cb = cmd_args; + + if (!cmd_args) { + CAM_ERR(CAM_ICP, "cmd args NULL"); + return -EINVAL; + } + + spin_lock_irqsave(&a5_dev->hw_lock, flags); + core_info->irq_cb.icp_hw_mgr_cb = irq_cb->icp_hw_mgr_cb; + core_info->irq_cb.data = irq_cb->data; + spin_unlock_irqrestore(&a5_dev->hw_lock, flags); + break; + } + + case CAM_ICP_A5_SEND_INIT: + hfi_send_system_cmd(HFI_CMD_SYS_INIT, 0, 0); + break; + + case CAM_ICP_A5_CMD_PC_PREP: + hfi_send_system_cmd(HFI_CMD_SYS_PC_PREP, 0, 0); + break; + + case CAM_ICP_A5_CMD_VOTE_CPAS: { + struct cam_icp_cpas_vote *cpas_vote = cmd_args; + + if (!cmd_args) { + CAM_ERR(CAM_ICP, "cmd args NULL"); + return -EINVAL; + } + + cam_a5_cpas_vote(core_info, cpas_vote); + break; + } + + case CAM_ICP_A5_CMD_CPAS_START: { + struct cam_icp_cpas_vote *cpas_vote = cmd_args; + + if (!cmd_args) { + CAM_ERR(CAM_ICP, "cmd args NULL"); + return -EINVAL; + } + + if (!core_info->cpas_start) { + rc = cam_cpas_start(core_info->cpas_handle, + &cpas_vote->ahb_vote, + &cpas_vote->axi_vote); + core_info->cpas_start = true; + } + break; + } + + case CAM_ICP_A5_CMD_CPAS_STOP: + if (core_info->cpas_start) { + cam_cpas_stop(core_info->cpas_handle); + core_info->cpas_start = false; + } + break; + case CAM_ICP_A5_CMD_UBWC_CFG: { + struct a5_ubwc_cfg_ext *ubwc_cfg_ext = NULL; + + a5_soc = soc_info->soc_private; + if (!a5_soc) { + CAM_ERR(CAM_ICP, "A5 private soc info is NULL"); + return -EINVAL; + } + + if (a5_soc->ubwc_config_ext) { + /* Invoke kernel API to determine DDR type */ + ddr_type = of_fdt_get_ddrtype(); + if ((ddr_type == DDR_TYPE_LPDDR5) || + (ddr_type == DDR_TYPE_LPDDR5X)) + index = 1; + + ubwc_cfg_ext = &a5_soc->uconfig.ubwc_cfg_ext; + ubwc_ipe_cfg[0] = + ubwc_cfg_ext->ubwc_ipe_fetch_cfg[index]; + ubwc_ipe_cfg[1] = + ubwc_cfg_ext->ubwc_ipe_write_cfg[index]; + ubwc_bps_cfg[0] = + ubwc_cfg_ext->ubwc_bps_fetch_cfg[index]; + ubwc_bps_cfg[1] = + ubwc_cfg_ext->ubwc_bps_write_cfg[index]; + rc = hfi_cmd_ubwc_config_ext(&ubwc_ipe_cfg[0], + &ubwc_bps_cfg[0]); + } else { + rc = hfi_cmd_ubwc_config(a5_soc->uconfig.ubwc_cfg); + } + + break; + } + case CAM_ICP_A5_CMD_CLK_UPDATE: { + int32_t clk_level = 0; + struct cam_ahb_vote ahb_vote; + + if (!cmd_args) { + CAM_ERR(CAM_ICP, "Invalid args"); + return -EINVAL; + } + + clk_level = *((int32_t *)cmd_args); + CAM_DBG(CAM_ICP, + "Update ICP clock to level [%d]", clk_level); + rc = cam_a5_update_clk_rate(soc_info, clk_level); + if (rc) + CAM_ERR(CAM_ICP, + "Failed to update clk to level: %d rc: %d", + clk_level, rc); + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = clk_level; + cam_cpas_update_ahb_vote( + core_info->cpas_handle, &ahb_vote); + break; + } + case CAM_ICP_A5_CMD_HW_DUMP: { + struct cam_icp_hw_dump_args *dump_args = cmd_args; + + rc = cam_a5_fw_dump(dump_args, core_info); + break; + } + default: + break; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_core.h b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_core.h new file mode 100644 index 0000000000000000000000000000000000000000..6c46b3ac8784f21393b4c09b6673898caf9dd37b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_core.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_A5_CORE_H +#define CAM_A5_CORE_H + +#include +#include +#include +#include +#include "cam_a5_hw_intf.h" + +#define A5_QGIC_BASE 0 +#define A5_SIERRA_BASE 1 +#define A5_CSR_BASE 2 + +#define A5_HOST_INT 0x1 +#define A5_WDT_0 0x2 +#define A5_WDT_1 0x4 + +#define ICP_SIERRA_A5_CSR_ACCESS 0x3C + +#define ELF_GUARD_PAGE (2 * 1024 * 1024) + +struct cam_a5_device_hw_info { + uint32_t hw_ver; + uint32_t nsec_reset; + uint32_t a5_control; + uint32_t a5_host_int_en; + uint32_t a5_host_int; + uint32_t a5_host_int_clr; + uint32_t a5_host_int_status; + uint32_t a5_host_int_set; + uint32_t host_a5_int; + uint32_t fw_version; + uint32_t init_req; + uint32_t init_response; + uint32_t shared_mem_ptr; + uint32_t shared_mem_size; + uint32_t qtbl_ptr; + uint32_t uncached_heap_ptr; + uint32_t uncached_heap_size; + uint32_t a5_status; +}; + +/** + * struct cam_a5_device_hw_info + * @a5_hw_info: A5 hardware info + * @fw_elf: start address of fw start with elf header + * @fw: start address of fw blob + * @fw_buf: smmu alloc/mapped fw buffer + * @fw_buf_len: fw buffer length + * @query_cap: A5 query info from firmware + * @a5_acquire: Acquire information of A5 + * @irq_cb: IRQ callback + * @cpas_handle: CPAS handle for A5 + * @cpast_start: state variable for cpas + */ +struct cam_a5_device_core_info { + struct cam_a5_device_hw_info *a5_hw_info; + const struct firmware *fw_elf; + void *fw; + uint32_t fw_buf; + uintptr_t fw_kva_addr; + uint64_t fw_buf_len; + struct cam_icp_a5_query_cap query_cap; + struct cam_icp_a5_acquire_dev a5_acquire[8]; + struct cam_icp_a5_set_irq_cb irq_cb; + uint32_t cpas_handle; + bool cpas_start; +}; + +int cam_a5_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_a5_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_a5_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size); + +irqreturn_t cam_a5_irq(int irq_num, void *data); +#endif /* CAM_A5_CORE_H */ diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_dev.c b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..b4f33d3e4dd358e8a194f8731f04610c7f87e774 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_dev.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "a5_core.h" +#include "a5_soc.h" +#include "cam_io_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "cam_a5_hw_intf.h" +#include "cam_icp_hw_mgr_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" + +struct a5_soc_info cam_a5_soc_info; +EXPORT_SYMBOL(cam_a5_soc_info); + +struct cam_a5_device_hw_info cam_a5_hw_info = { + .hw_ver = 0x0, + .nsec_reset = 0x4, + .a5_control = 0x8, + .a5_host_int_en = 0x10, + .a5_host_int = 0x14, + .a5_host_int_clr = 0x18, + .a5_host_int_status = 0x1c, + .a5_host_int_set = 0x20, + .host_a5_int = 0x30, + .fw_version = 0x44, + .init_req = 0x48, + .init_response = 0x4c, + .shared_mem_ptr = 0x50, + .shared_mem_size = 0x54, + .qtbl_ptr = 0x58, + .uncached_heap_ptr = 0x5c, + .uncached_heap_size = 0x60, + .a5_status = 0x200, +}; +EXPORT_SYMBOL(cam_a5_hw_info); + +static bool cam_a5_cpas_cb(uint32_t client_handle, void *userdata, + struct cam_cpas_irq_data *irq_data) +{ + bool error_handled = false; + + if (!irq_data) + return error_handled; + + switch (irq_data->irq_type) { + case CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR: + CAM_ERR_RATE_LIMIT(CAM_ICP, + "IPE/BPS UBWC Decode error type=%d status=%x thr_err=%d, fcl_err=%d, len_md_err=%d, format_err=%d", + irq_data->irq_type, + irq_data->u.dec_err.decerr_status.value, + irq_data->u.dec_err.decerr_status.thr_err, + irq_data->u.dec_err.decerr_status.fcl_err, + irq_data->u.dec_err.decerr_status.len_md_err, + irq_data->u.dec_err.decerr_status.format_err); + error_handled = true; + break; + case CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR: + CAM_ERR_RATE_LIMIT(CAM_ICP, + "IPE/BPS UBWC Encode error type=%d status=%x", + irq_data->irq_type, + irq_data->u.enc_err.encerr_status.value); + error_handled = true; + break; + default: + break; + } + + return error_handled; +} + +int cam_a5_register_cpas(struct cam_hw_soc_info *soc_info, + struct cam_a5_device_core_info *core_info, + uint32_t hw_idx) +{ + struct cam_cpas_register_params cpas_register_params; + int rc; + + cpas_register_params.dev = &soc_info->pdev->dev; + memcpy(cpas_register_params.identifier, "icp", sizeof("icp")); + cpas_register_params.cam_cpas_client_cb = cam_a5_cpas_cb; + cpas_register_params.cell_index = hw_idx; + cpas_register_params.userdata = NULL; + + rc = cam_cpas_register_client(&cpas_register_params); + if (rc < 0) { + CAM_ERR(CAM_ICP, "failed: %d", rc); + return rc; + } + + core_info->cpas_handle = cpas_register_params.client_handle; + return rc; +} + +int cam_a5_probe(struct platform_device *pdev) +{ + int rc = 0; + struct cam_hw_info *a5_dev = NULL; + struct cam_hw_intf *a5_dev_intf = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_a5_device_core_info *core_info = NULL; + struct cam_a5_device_hw_info *hw_info = NULL; + + a5_dev_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!a5_dev_intf) + return -ENOMEM; + + of_property_read_u32(pdev->dev.of_node, + "cell-index", &a5_dev_intf->hw_idx); + + a5_dev = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!a5_dev) { + rc = -ENOMEM; + goto a5_dev_alloc_failure; + } + + a5_dev->soc_info.pdev = pdev; + a5_dev->soc_info.dev = &pdev->dev; + a5_dev->soc_info.dev_name = pdev->name; + a5_dev_intf->hw_priv = a5_dev; + a5_dev_intf->hw_ops.init = cam_a5_init_hw; + a5_dev_intf->hw_ops.deinit = cam_a5_deinit_hw; + a5_dev_intf->hw_ops.process_cmd = cam_a5_process_cmd; + a5_dev_intf->hw_type = CAM_ICP_DEV_A5; + + CAM_DBG(CAM_ICP, "type %d index %d", + a5_dev_intf->hw_type, + a5_dev_intf->hw_idx); + + platform_set_drvdata(pdev, a5_dev_intf); + + a5_dev->core_info = kzalloc(sizeof(struct cam_a5_device_core_info), + GFP_KERNEL); + if (!a5_dev->core_info) { + rc = -ENOMEM; + goto core_info_alloc_failure; + } + core_info = (struct cam_a5_device_core_info *)a5_dev->core_info; + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_ICP, "No a5 hardware info"); + rc = -EINVAL; + goto match_err; + } + hw_info = (struct cam_a5_device_hw_info *)match_dev->data; + core_info->a5_hw_info = hw_info; + + a5_dev->soc_info.soc_private = &cam_a5_soc_info; + + rc = cam_a5_init_soc_resources(&a5_dev->soc_info, cam_a5_irq, + a5_dev); + if (rc < 0) { + CAM_ERR(CAM_ICP, "failed to init_soc"); + goto init_soc_failure; + } + + CAM_DBG(CAM_ICP, "soc info : %pK", + (void *)&a5_dev->soc_info); + rc = cam_a5_register_cpas(&a5_dev->soc_info, + core_info, a5_dev_intf->hw_idx); + if (rc < 0) { + CAM_ERR(CAM_ICP, "a5 cpas registration failed"); + goto cpas_reg_failed; + } + a5_dev->hw_state = CAM_HW_STATE_POWER_DOWN; + mutex_init(&a5_dev->hw_mutex); + spin_lock_init(&a5_dev->hw_lock); + init_completion(&a5_dev->hw_complete); + + CAM_DBG(CAM_ICP, "A5%d probe successful", + a5_dev_intf->hw_idx); + return 0; + +cpas_reg_failed: +init_soc_failure: +match_err: + kfree(a5_dev->core_info); +core_info_alloc_failure: + kfree(a5_dev); +a5_dev_alloc_failure: + kfree(a5_dev_intf); + + return rc; +} + +static const struct of_device_id cam_a5_dt_match[] = { + { + .compatible = "qcom,cam-a5", + .data = &cam_a5_hw_info, + }, + {} +}; +MODULE_DEVICE_TABLE(of, cam_a5_dt_match); + +static struct platform_driver cam_a5_driver = { + .probe = cam_a5_probe, + .driver = { + .name = "cam-a5", + .owner = THIS_MODULE, + .of_match_table = cam_a5_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_a5_init_module(void) +{ + return platform_driver_register(&cam_a5_driver); +} + +static void __exit cam_a5_exit_module(void) +{ + platform_driver_unregister(&cam_a5_driver); +} + +module_init(cam_a5_init_module); +module_exit(cam_a5_exit_module); +MODULE_DESCRIPTION("CAM A5 driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_soc.c b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..d0629612193ab1cf3cb9609ca850bd2334a770f3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_soc.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "a5_soc.h" +#include "cam_soc_util.h" +#include "cam_debug_util.h" + +static int cam_a5_get_dt_properties(struct cam_hw_soc_info *soc_info) +{ + int rc = 0, i; + const char *fw_name; + struct a5_soc_info *a5_soc_info; + struct device_node *of_node = NULL; + struct platform_device *pdev = NULL; + struct a5_ubwc_cfg_ext *ubwc_cfg_ext = NULL; + int num_ubwc_cfg; + + pdev = soc_info->pdev; + of_node = pdev->dev.of_node; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) { + CAM_ERR(CAM_ICP, "get a5 dt prop is failed"); + return rc; + } + + a5_soc_info = soc_info->soc_private; + fw_name = a5_soc_info->fw_name; + + rc = of_property_read_string(of_node, "fw_name", &fw_name); + if (rc < 0) { + CAM_ERR(CAM_ICP, "fw_name read failed"); + goto end; + } + + rc = of_property_read_u32(of_node, "qos-val", + &a5_soc_info->a5_qos_val); + if (rc < 0) { + CAM_WARN(CAM_ICP, "QoS need not be set"); + a5_soc_info->a5_qos_val = 0; + } + + ubwc_cfg_ext = &a5_soc_info->uconfig.ubwc_cfg_ext; + num_ubwc_cfg = of_property_count_u32_elems(of_node, + "ubwc-ipe-fetch-cfg"); + if ((num_ubwc_cfg < 0) || (num_ubwc_cfg > ICP_UBWC_MAX)) { + CAM_DBG(CAM_ICP, "wrong ubwc_ipe_fetch_cfg: %d", num_ubwc_cfg); + rc = num_ubwc_cfg; + goto ubwc_ex_cfg; + } + + for (i = 0; i < num_ubwc_cfg; i++) { + rc = of_property_read_u32_index(of_node, "ubwc-ipe-fetch-cfg", + i, &ubwc_cfg_ext->ubwc_ipe_fetch_cfg[i]); + if (rc < 0) { + CAM_ERR(CAM_ICP, + "unable to read ubwc_ipe_fetch_cfg values"); + goto end; + } + } + + num_ubwc_cfg = of_property_count_u32_elems(of_node, + "ubwc-ipe-write-cfg"); + if ((num_ubwc_cfg < 0) || (num_ubwc_cfg > ICP_UBWC_MAX)) { + CAM_ERR(CAM_ICP, "wrong ubwc_ipe_write_cfg: %d", num_ubwc_cfg); + rc = num_ubwc_cfg; + goto end; + } + + for (i = 0; i < num_ubwc_cfg; i++) { + rc = of_property_read_u32_index(of_node, "ubwc-ipe-write-cfg", + i, &ubwc_cfg_ext->ubwc_ipe_write_cfg[i]); + if (rc < 0) { + CAM_ERR(CAM_ICP, + "unable to read ubwc_ipe_write_cfg values"); + goto end; + } + } + + num_ubwc_cfg = of_property_count_u32_elems(of_node, + "ubwc-bps-fetch-cfg"); + if ((num_ubwc_cfg < 0) || (num_ubwc_cfg > ICP_UBWC_MAX)) { + CAM_ERR(CAM_ICP, "wrong ubwc_bps_fetch_cfg: %d", num_ubwc_cfg); + rc = num_ubwc_cfg; + goto end; + } + + for (i = 0; i < num_ubwc_cfg; i++) { + rc = of_property_read_u32_index(of_node, "ubwc-bps-fetch-cfg", + i, &ubwc_cfg_ext->ubwc_bps_fetch_cfg[i]); + if (rc < 0) { + CAM_ERR(CAM_ICP, + "unable to read ubwc_bps_fetch_cfg values"); + goto end; + } + } + + num_ubwc_cfg = of_property_count_u32_elems(of_node, + "ubwc-bps-write-cfg"); + if ((num_ubwc_cfg < 0) || (num_ubwc_cfg > ICP_UBWC_MAX)) { + CAM_ERR(CAM_ICP, "wrong ubwc_bps_write_cfg: %d", num_ubwc_cfg); + rc = num_ubwc_cfg; + goto end; + } + + for (i = 0; i < num_ubwc_cfg; i++) { + rc = of_property_read_u32_index(of_node, "ubwc-bps-write-cfg", + i, &ubwc_cfg_ext->ubwc_bps_write_cfg[i]); + if (rc < 0) { + CAM_ERR(CAM_ICP, + "unable to read ubwc_bps_write_cfg values"); + goto end; + } + } + + a5_soc_info->ubwc_config_ext = true; + CAM_DBG(CAM_ICP, "read ubwc_cfg_ext for ipe/bps"); + return rc; + +ubwc_ex_cfg: + num_ubwc_cfg = of_property_count_u32_elems(of_node, "ubwc-cfg"); + if ((num_ubwc_cfg < 0) || (num_ubwc_cfg > ICP_UBWC_MAX)) { + CAM_ERR(CAM_ICP, "wrong ubwc_cfg: %d", num_ubwc_cfg); + rc = num_ubwc_cfg; + goto end; + } + + for (i = 0; i < num_ubwc_cfg; i++) { + rc = of_property_read_u32_index(of_node, "ubwc-cfg", + i, &a5_soc_info->uconfig.ubwc_cfg[i]); + if (rc < 0) { + CAM_ERR(CAM_ICP, "unable to read ubwc_cfg values"); + break; + } + } + +end: + return rc; +} + +static int cam_a5_request_platform_resource( + struct cam_hw_soc_info *soc_info, + irq_handler_t a5_irq_handler, void *irq_data) +{ + int rc = 0; + + rc = cam_soc_util_request_platform_resource(soc_info, a5_irq_handler, + irq_data); + + return rc; +} + +int cam_a5_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t a5_irq_handler, void *irq_data) +{ + int rc = 0; + + rc = cam_a5_get_dt_properties(soc_info); + if (rc < 0) + return rc; + + rc = cam_a5_request_platform_resource(soc_info, a5_irq_handler, + irq_data); + if (rc < 0) + return rc; + + return rc; +} + +int cam_a5_enable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_SVS_VOTE, true); + if (rc) + CAM_ERR(CAM_ICP, "enable platform failed"); + + return rc; +} + +int cam_a5_disable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) + CAM_ERR(CAM_ICP, "disable platform failed"); + + return rc; +} + +int cam_a5_update_clk_rate(struct cam_hw_soc_info *soc_info, + int32_t clk_level) +{ + int32_t src_clk_idx = 0; + int32_t clk_rate = 0; + + if (!soc_info) { + CAM_ERR(CAM_ICP, "Invalid args"); + return -EINVAL; + } + + if ((clk_level < 0) || (clk_level >= CAM_MAX_VOTE)) { + CAM_ERR(CAM_ICP, "clock level %d is not valid", + clk_level); + return -EINVAL; + } + + if (!soc_info->clk_level_valid[clk_level]) { + CAM_ERR(CAM_ICP, + "Clock level %d not supported", + clk_level); + return -EINVAL; + } + + src_clk_idx = soc_info->src_clk_idx; + if ((src_clk_idx < 0) || (src_clk_idx >= CAM_SOC_MAX_CLK)) { + CAM_WARN(CAM_ICP, "src_clk not defined for %s", + soc_info->dev_name); + return -EINVAL; + } + + clk_rate = soc_info->clk_rate[clk_level][src_clk_idx]; + if ((soc_info->clk_level_valid[CAM_TURBO_VOTE]) && + (soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx] != 0) && + (clk_rate > soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx])) { + CAM_DBG(CAM_ICP, "clk_rate %d greater than max, reset to %d", + clk_rate, + soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]); + clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]; + } + + return cam_soc_util_set_src_clk_rate(soc_info, clk_rate); +} diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_soc.h b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..480364df1fd626099d431dd296997552593f54b9 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/a5_soc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_A5_SOC_H +#define CAM_A5_SOC_H + +#include "cam_soc_util.h" + +#define ICP_UBWC_MAX 2 + +struct a5_ubwc_cfg_ext { + uint32_t ubwc_ipe_fetch_cfg[ICP_UBWC_MAX]; + uint32_t ubwc_ipe_write_cfg[ICP_UBWC_MAX]; + uint32_t ubwc_bps_fetch_cfg[ICP_UBWC_MAX]; + uint32_t ubwc_bps_write_cfg[ICP_UBWC_MAX]; +}; + +struct a5_soc_info { + char *fw_name; + bool ubwc_config_ext; + uint32_t a5_qos_val; + union { + uint32_t ubwc_cfg[ICP_UBWC_MAX]; + struct a5_ubwc_cfg_ext ubwc_cfg_ext; + } uconfig; +}; + +int cam_a5_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t a5_irq_handler, void *irq_data); + +int cam_a5_enable_soc_resources(struct cam_hw_soc_info *soc_info); + +int cam_a5_disable_soc_resources(struct cam_hw_soc_info *soc_info); + +int cam_a5_update_clk_rate(struct cam_hw_soc_info *soc_info, + int32_t clk_level); +#endif diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/Makefile b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..76947649f7e345568edd7f8bc9388f664c25bc90 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/fw_inc +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += bps_dev.o bps_core.o bps_soc.o diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_core.c b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_core.c new file mode 100644 index 0000000000000000000000000000000000000000..8a079bd1420208dce97a0a9172a478ae1d67cf99 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_core.c @@ -0,0 +1,430 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_io_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "bps_core.h" +#include "bps_soc.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_bps_hw_intf.h" +#include "cam_icp_hw_intf.h" +#include "cam_icp_hw_mgr_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "hfi_reg.h" + +#define HFI_MAX_POLL_TRY 5 + +static int cam_bps_cpas_vote(struct cam_bps_device_core_info *core_info, + struct cam_icp_cpas_vote *cpas_vote) +{ + int rc = 0; + + if (cpas_vote->ahb_vote_valid) + rc = cam_cpas_update_ahb_vote(core_info->cpas_handle, + &cpas_vote->ahb_vote); + if (cpas_vote->axi_vote_valid) + rc = cam_cpas_update_axi_vote(core_info->cpas_handle, + &cpas_vote->axi_vote); + + if (rc < 0) + CAM_ERR(CAM_PERF, "cpas vote is failed: %d", rc); + + return rc; +} + + +int cam_bps_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *bps_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_bps_device_core_info *core_info = NULL; + struct cam_icp_cpas_vote cpas_vote; + int rc = 0; + + if (!device_priv) { + CAM_ERR(CAM_ICP, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &bps_dev->soc_info; + core_info = (struct cam_bps_device_core_info *)bps_dev->core_info; + + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_ICP, "soc_info = %pK core_info = %pK", + soc_info, core_info); + return -EINVAL; + } + + cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE; + cpas_vote.ahb_vote.vote.level = CAM_LOWSVS_VOTE; + cpas_vote.axi_vote.num_paths = 1; + cpas_vote.axi_vote.axi_path[0].path_data_type = + CAM_BPS_DEFAULT_AXI_PATH; + cpas_vote.axi_vote.axi_path[0].transac_type = + CAM_BPS_DEFAULT_AXI_TRANSAC; + cpas_vote.axi_vote.axi_path[0].camnoc_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].mnoc_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].mnoc_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].ddr_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].ddr_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + + rc = cam_cpas_start(core_info->cpas_handle, + &cpas_vote.ahb_vote, &cpas_vote.axi_vote); + if (rc) { + CAM_ERR(CAM_ICP, "cpas start failed: %d", rc); + goto error; + } + core_info->cpas_start = true; + + rc = cam_bps_enable_soc_resources(soc_info); + if (rc) { + CAM_ERR(CAM_ICP, "soc enable is failed: %d", rc); + if (cam_cpas_stop(core_info->cpas_handle)) + CAM_ERR(CAM_ICP, "cpas stop is failed"); + else + core_info->cpas_start = false; + } else { + core_info->clk_enable = true; + } + +error: + return rc; +} + +int cam_bps_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *bps_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_bps_device_core_info *core_info = NULL; + int rc = 0; + + if (!device_priv) { + CAM_ERR(CAM_ICP, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &bps_dev->soc_info; + core_info = (struct cam_bps_device_core_info *)bps_dev->core_info; + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_ICP, "soc_info = %pK core_info = %pK", + soc_info, core_info); + return -EINVAL; + } + + rc = cam_bps_disable_soc_resources(soc_info, core_info->clk_enable); + if (rc) + CAM_ERR(CAM_ICP, "soc disable is failed: %d", rc); + core_info->clk_enable = false; + + if (core_info->cpas_start) { + if (cam_cpas_stop(core_info->cpas_handle)) + CAM_ERR(CAM_ICP, "cpas stop is failed"); + else + core_info->cpas_start = false; + } + + return rc; +} + +static int cam_bps_handle_pc(struct cam_hw_info *bps_dev) +{ + struct cam_hw_soc_info *soc_info = NULL; + struct cam_bps_device_core_info *core_info = NULL; + struct cam_bps_device_hw_info *hw_info = NULL; + int pwr_ctrl; + int pwr_status; + + soc_info = &bps_dev->soc_info; + core_info = (struct cam_bps_device_core_info *)bps_dev->core_info; + hw_info = core_info->bps_hw_info; + + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, + true, &pwr_ctrl); + if (!(pwr_ctrl & BPS_COLLAPSE_MASK)) { + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, + true, &pwr_status); + + cam_cpas_reg_write(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, + hw_info->pwr_ctrl, true, 0x1); + + if ((pwr_status >> BPS_PWR_ON_MASK)) + CAM_WARN(CAM_PERF, "BPS: pwr_status(%x):pwr_ctrl(%x)", + pwr_status, pwr_ctrl); + } + cam_bps_get_gdsc_control(soc_info); + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, + &pwr_ctrl); + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, + true, &pwr_status); + CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x", + pwr_ctrl, pwr_status); + + return 0; +} + +static int cam_bps_handle_resume(struct cam_hw_info *bps_dev) +{ + struct cam_hw_soc_info *soc_info = NULL; + struct cam_bps_device_core_info *core_info = NULL; + struct cam_bps_device_hw_info *hw_info = NULL; + int pwr_ctrl; + int pwr_status; + int rc = 0; + + soc_info = &bps_dev->soc_info; + core_info = (struct cam_bps_device_core_info *)bps_dev->core_info; + hw_info = core_info->bps_hw_info; + + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl); + if (pwr_ctrl & BPS_COLLAPSE_MASK) { + CAM_DBG(CAM_PERF, "BPS: pwr_ctrl set(%x)", pwr_ctrl); + cam_cpas_reg_write(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, + hw_info->pwr_ctrl, true, 0); + } + + rc = cam_bps_transfer_gdsc_control(soc_info); + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl); + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, true, &pwr_status); + CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x", + pwr_ctrl, pwr_status); + + return rc; +} + +static int cam_bps_cmd_reset(struct cam_hw_soc_info *soc_info, + struct cam_bps_device_core_info *core_info) +{ + uint32_t retry_cnt = 0; + uint32_t status = 0; + int pwr_ctrl, pwr_status, rc = 0; + bool reset_bps_cdm_fail = false; + bool reset_bps_top_fail = false; + + CAM_DBG(CAM_ICP, "CAM_ICP_BPS_CMD_RESET"); + + if (!core_info->clk_enable || !core_info->cpas_start) { + CAM_ERR(CAM_ICP, "BPS reset failed. clk_en %d cpas_start %d", + core_info->clk_enable, core_info->cpas_start); + return -EINVAL; + } + + /* Reset BPS CDM core*/ + cam_io_w_mb((uint32_t)0xF, + soc_info->reg_map[0].mem_base + BPS_CDM_RST_CMD); + while (retry_cnt < HFI_MAX_POLL_TRY) { + readw_poll_timeout((soc_info->reg_map[0].mem_base + + BPS_CDM_IRQ_STATUS), + status, ((status & BPS_RST_DONE_IRQ_STATUS_BIT) == 0x1), + 100, 10000); + + CAM_DBG(CAM_ICP, "bps_cdm_irq_status = %u", status); + + if ((status & BPS_RST_DONE_IRQ_STATUS_BIT) == 0x1) + break; + retry_cnt++; + } + status = cam_io_r_mb(soc_info->reg_map[0].mem_base + + BPS_CDM_IRQ_STATUS); + if ((status & BPS_RST_DONE_IRQ_STATUS_BIT) != 0x1) { + CAM_ERR(CAM_ICP, "BPS CDM rst failed status 0x%x", status); + reset_bps_cdm_fail = true; + } + + /* Reset BPS core*/ + status = 0; + cam_io_w_mb((uint32_t)0x3, + soc_info->reg_map[0].mem_base + BPS_TOP_RST_CMD); + while (retry_cnt < HFI_MAX_POLL_TRY) { + readw_poll_timeout((soc_info->reg_map[0].mem_base + + BPS_TOP_IRQ_STATUS), + status, ((status & BPS_RST_DONE_IRQ_STATUS_BIT) == 0x1), + 100, 10000); + + CAM_DBG(CAM_ICP, "bps_top_irq_status = %u", status); + + if ((status & BPS_RST_DONE_IRQ_STATUS_BIT) == 0x1) + break; + retry_cnt++; + } + status = cam_io_r_mb(soc_info->reg_map[0].mem_base + + BPS_TOP_IRQ_STATUS); + if ((status & BPS_RST_DONE_IRQ_STATUS_BIT) != 0x1) { + CAM_ERR(CAM_ICP, "BPS top rst failed status 0x%x", status); + reset_bps_top_fail = true; + } + + cam_bps_get_gdsc_control(soc_info); + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, core_info->bps_hw_info->pwr_ctrl, + true, &pwr_ctrl); + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, core_info->bps_hw_info->pwr_status, + true, &pwr_status); + CAM_DBG(CAM_ICP, "(After) pwr_ctrl = %x pwr_status = %x", + pwr_ctrl, pwr_status); + + if (reset_bps_cdm_fail || reset_bps_top_fail) + rc = -EAGAIN; + + return rc; +} + +int cam_bps_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + struct cam_hw_info *bps_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_bps_device_core_info *core_info = NULL; + struct cam_bps_device_hw_info *hw_info = NULL; + int rc = 0; + + if (!device_priv) { + CAM_ERR(CAM_ICP, "Invalid arguments"); + return -EINVAL; + } + + if (cmd_type >= CAM_ICP_BPS_CMD_MAX) { + CAM_ERR(CAM_ICP, "Invalid command : %x", cmd_type); + return -EINVAL; + } + + soc_info = &bps_dev->soc_info; + core_info = (struct cam_bps_device_core_info *)bps_dev->core_info; + hw_info = core_info->bps_hw_info; + + switch (cmd_type) { + case CAM_ICP_BPS_CMD_VOTE_CPAS: { + struct cam_icp_cpas_vote *cpas_vote = cmd_args; + + if (!cmd_args) { + CAM_ERR(CAM_ICP, "cmd args NULL"); + return -EINVAL; + } + + cam_bps_cpas_vote(core_info, cpas_vote); + break; + } + + case CAM_ICP_BPS_CMD_CPAS_START: { + struct cam_icp_cpas_vote *cpas_vote = cmd_args; + + if (!cmd_args) { + CAM_ERR(CAM_ICP, "cmd args NULL"); + return -EINVAL; + } + + if (!core_info->cpas_start) { + rc = cam_cpas_start(core_info->cpas_handle, + &cpas_vote->ahb_vote, + &cpas_vote->axi_vote); + core_info->cpas_start = true; + } + break; + } + + case CAM_ICP_BPS_CMD_CPAS_STOP: + if (core_info->cpas_start) { + cam_cpas_stop(core_info->cpas_handle); + core_info->cpas_start = false; + } + break; + case CAM_ICP_BPS_CMD_POWER_COLLAPSE: + rc = cam_bps_handle_pc(bps_dev); + break; + case CAM_ICP_BPS_CMD_POWER_RESUME: + rc = cam_bps_handle_resume(bps_dev); + break; + case CAM_ICP_BPS_CMD_UPDATE_CLK: { + struct cam_a5_clk_update_cmd *clk_upd_cmd = + (struct cam_a5_clk_update_cmd *)cmd_args; + struct cam_ahb_vote ahb_vote; + uint32_t clk_rate = clk_upd_cmd->curr_clk_rate; + int32_t clk_level = 0, err = 0; + + CAM_DBG(CAM_PERF, "bps_src_clk rate = %d", (int)clk_rate); + + if (!core_info->clk_enable) { + if (clk_upd_cmd->ipe_bps_pc_enable) { + cam_bps_handle_pc(bps_dev); + cam_cpas_reg_write(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, + hw_info->pwr_ctrl, true, 0x0); + } + rc = cam_bps_toggle_clk(soc_info, true); + if (rc) + CAM_ERR(CAM_ICP, "Enable failed"); + else + core_info->clk_enable = true; + if (clk_upd_cmd->ipe_bps_pc_enable) { + rc = cam_bps_handle_resume(bps_dev); + if (rc) + CAM_ERR(CAM_ICP, "BPS resume failed"); + } + } + CAM_DBG(CAM_PERF, "clock rate %d", clk_rate); + rc = cam_bps_update_clk_rate(soc_info, clk_rate); + if (rc) + CAM_ERR(CAM_PERF, "Failed to update clk %d", clk_rate); + + err = cam_soc_util_get_clk_level(soc_info, + clk_rate, soc_info->src_clk_idx, + &clk_level); + + if (!err) { + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = clk_level; + cam_cpas_update_ahb_vote( + core_info->cpas_handle, + &ahb_vote); + } + break; + } + case CAM_ICP_BPS_CMD_DISABLE_CLK: + if (core_info->clk_enable == true) + cam_bps_toggle_clk(soc_info, false); + core_info->clk_enable = false; + break; + case CAM_ICP_BPS_CMD_RESET: + rc = cam_bps_cmd_reset(soc_info, core_info); + break; + default: + CAM_ERR(CAM_ICP, "Invalid Cmd Type:%u", cmd_type); + rc = -EINVAL; + break; + } + return rc; +} + +irqreturn_t cam_bps_irq(int irq_num, void *data) +{ + return IRQ_HANDLED; +} diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_core.h b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_core.h new file mode 100644 index 0000000000000000000000000000000000000000..162c5e65530c45948c23c2b3cc7c6c77b5b09b3c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_core.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_BPS_CORE_H +#define CAM_BPS_CORE_H + +#include +#include +#include +#include + +#define BPS_COLLAPSE_MASK 0x1 +#define BPS_PWR_ON_MASK 0x2 + +struct cam_bps_device_hw_info { + uint32_t hw_idx; + uint32_t pwr_ctrl; + uint32_t pwr_status; + uint32_t reserved; +}; + +struct cam_bps_device_core_info { + struct cam_bps_device_hw_info *bps_hw_info; + uint32_t cpas_handle; + bool cpas_start; + bool clk_enable; +}; + +int cam_bps_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_bps_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_bps_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size); + +irqreturn_t cam_bps_irq(int irq_num, void *data); +#endif /* CAM_BPS_CORE_H */ diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_dev.c b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..a80c27325b727ee9e62a541a4839c40f2be1ed15 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_dev.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "bps_core.h" +#include "bps_soc.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "cam_io_util.h" +#include "cam_icp_hw_intf.h" +#include "cam_icp_hw_mgr_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" + +static struct cam_bps_device_hw_info cam_bps_hw_info = { + .hw_idx = 0, + .pwr_ctrl = 0x5c, + .pwr_status = 0x58, + .reserved = 0, +}; +EXPORT_SYMBOL(cam_bps_hw_info); + +static char bps_dev_name[8]; + +static bool cam_bps_cpas_cb(uint32_t client_handle, void *userdata, + struct cam_cpas_irq_data *irq_data) +{ + bool error_handled = false; + + if (!irq_data) + return error_handled; + + switch (irq_data->irq_type) { + case CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR: + CAM_ERR_RATE_LIMIT(CAM_ICP, + "IPE/BPS UBWC Decode error type=%d status=%x thr_err=%d, fcl_err=%d, len_md_err=%d, format_err=%d", + irq_data->irq_type, + irq_data->u.dec_err.decerr_status.value, + irq_data->u.dec_err.decerr_status.thr_err, + irq_data->u.dec_err.decerr_status.fcl_err, + irq_data->u.dec_err.decerr_status.len_md_err, + irq_data->u.dec_err.decerr_status.format_err); + error_handled = true; + break; + case CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR: + CAM_ERR_RATE_LIMIT(CAM_ICP, + "IPE/BPS UBWC Encode error type=%d status=%x", + irq_data->irq_type, + irq_data->u.enc_err.encerr_status.value); + error_handled = true; + break; + default: + break; + } + + return error_handled; +} + +int cam_bps_register_cpas(struct cam_hw_soc_info *soc_info, + struct cam_bps_device_core_info *core_info, + uint32_t hw_idx) +{ + struct cam_cpas_register_params cpas_register_params; + int rc; + + cpas_register_params.dev = &soc_info->pdev->dev; + memcpy(cpas_register_params.identifier, "bps", sizeof("bps")); + cpas_register_params.cam_cpas_client_cb = cam_bps_cpas_cb; + cpas_register_params.cell_index = hw_idx; + cpas_register_params.userdata = NULL; + + rc = cam_cpas_register_client(&cpas_register_params); + if (rc < 0) { + CAM_ERR(CAM_ICP, "failed: %d", rc); + return rc; + } + core_info->cpas_handle = cpas_register_params.client_handle; + + return rc; +} + +int cam_bps_probe(struct platform_device *pdev) +{ + struct cam_hw_info *bps_dev = NULL; + struct cam_hw_intf *bps_dev_intf = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_bps_device_core_info *core_info = NULL; + struct cam_bps_device_hw_info *hw_info = NULL; + int rc = 0; + + bps_dev_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!bps_dev_intf) + return -ENOMEM; + + of_property_read_u32(pdev->dev.of_node, + "cell-index", &bps_dev_intf->hw_idx); + + bps_dev = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!bps_dev) { + kfree(bps_dev_intf); + return -ENOMEM; + } + + memset(bps_dev_name, 0, sizeof(bps_dev_name)); + snprintf(bps_dev_name, sizeof(bps_dev_name), + "bps%1u", bps_dev_intf->hw_idx); + + bps_dev->soc_info.pdev = pdev; + bps_dev->soc_info.dev = &pdev->dev; + bps_dev->soc_info.dev_name = bps_dev_name; + bps_dev_intf->hw_priv = bps_dev; + bps_dev_intf->hw_ops.init = cam_bps_init_hw; + bps_dev_intf->hw_ops.deinit = cam_bps_deinit_hw; + bps_dev_intf->hw_ops.process_cmd = cam_bps_process_cmd; + bps_dev_intf->hw_type = CAM_ICP_DEV_BPS; + platform_set_drvdata(pdev, bps_dev_intf); + bps_dev->core_info = kzalloc(sizeof(struct cam_bps_device_core_info), + GFP_KERNEL); + if (!bps_dev->core_info) { + kfree(bps_dev); + kfree(bps_dev_intf); + return -ENOMEM; + } + core_info = (struct cam_bps_device_core_info *)bps_dev->core_info; + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_ICP, "No bps hardware info"); + kfree(bps_dev->core_info); + kfree(bps_dev); + kfree(bps_dev_intf); + rc = -EINVAL; + return rc; + } + hw_info = &cam_bps_hw_info; + core_info->bps_hw_info = hw_info; + + rc = cam_bps_init_soc_resources(&bps_dev->soc_info, cam_bps_irq, + bps_dev); + if (rc < 0) { + CAM_ERR(CAM_ICP, "failed to init_soc"); + kfree(bps_dev->core_info); + kfree(bps_dev); + kfree(bps_dev_intf); + return rc; + } + CAM_DBG(CAM_ICP, "soc info : %pK", + (void *)&bps_dev->soc_info); + + rc = cam_bps_register_cpas(&bps_dev->soc_info, + core_info, bps_dev_intf->hw_idx); + if (rc < 0) { + kfree(bps_dev->core_info); + kfree(bps_dev); + kfree(bps_dev_intf); + return rc; + } + bps_dev->hw_state = CAM_HW_STATE_POWER_DOWN; + mutex_init(&bps_dev->hw_mutex); + spin_lock_init(&bps_dev->hw_lock); + init_completion(&bps_dev->hw_complete); + CAM_DBG(CAM_ICP, "BPS%d probe successful", + bps_dev_intf->hw_idx); + + return rc; +} + +static const struct of_device_id cam_bps_dt_match[] = { + { + .compatible = "qcom,cam-bps", + .data = &cam_bps_hw_info, + }, + {} +}; +MODULE_DEVICE_TABLE(of, cam_bps_dt_match); + +static struct platform_driver cam_bps_driver = { + .probe = cam_bps_probe, + .driver = { + .name = "cam-bps", + .owner = THIS_MODULE, + .of_match_table = cam_bps_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_bps_init_module(void) +{ + return platform_driver_register(&cam_bps_driver); +} + +static void __exit cam_bps_exit_module(void) +{ + platform_driver_unregister(&cam_bps_driver); +} + +module_init(cam_bps_init_module); +module_exit(cam_bps_exit_module); +MODULE_DESCRIPTION("CAM BPS driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_soc.c b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..481eeafdb0b2a23d19a0297152bd9fa93ff6dcd6 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_soc.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "bps_soc.h" +#include "cam_soc_util.h" +#include "cam_debug_util.h" + +static int cam_bps_get_dt_properties(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) + CAM_ERR(CAM_ICP, "get bps dt prop is failed"); + + return rc; +} + +static int cam_bps_request_platform_resource( + struct cam_hw_soc_info *soc_info, + irq_handler_t bps_irq_handler, void *irq_data) +{ + int rc = 0; + + rc = cam_soc_util_request_platform_resource(soc_info, bps_irq_handler, + irq_data); + + return rc; +} + +int cam_bps_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t bps_irq_handler, void *irq_data) +{ + int rc = 0; + + rc = cam_bps_get_dt_properties(soc_info); + if (rc < 0) + return rc; + + rc = cam_bps_request_platform_resource(soc_info, bps_irq_handler, + irq_data); + if (rc < 0) + return rc; + + return rc; +} + +int cam_bps_enable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_SVS_VOTE, false); + if (rc) + CAM_ERR(CAM_ICP, "enable platform failed"); + + return rc; +} + +int cam_bps_disable_soc_resources(struct cam_hw_soc_info *soc_info, + bool disable_clk) +{ + int rc = 0; + + rc = cam_soc_util_disable_platform_resource(soc_info, disable_clk, + false); + if (rc) + CAM_ERR(CAM_ICP, "disable platform failed"); + + return rc; +} + +int cam_bps_transfer_gdsc_control(struct cam_hw_soc_info *soc_info) +{ + int i; + int rc; + + for (i = 0; i < soc_info->num_rgltr; i++) { + rc = regulator_set_mode(soc_info->rgltr[i], + REGULATOR_MODE_FAST); + if (rc) { + CAM_ERR(CAM_ICP, "Regulator set mode %s failed", + soc_info->rgltr_name[i]); + goto rgltr_set_mode_failed; + } + } + return 0; + +rgltr_set_mode_failed: + for (i = i - 1; i >= 0; i--) + if (soc_info->rgltr[i]) + regulator_set_mode(soc_info->rgltr[i], + REGULATOR_MODE_NORMAL); + + return rc; +} + +int cam_bps_get_gdsc_control(struct cam_hw_soc_info *soc_info) +{ + int i; + int rc; + + for (i = 0; i < soc_info->num_rgltr; i++) { + rc = regulator_set_mode(soc_info->rgltr[i], + REGULATOR_MODE_NORMAL); + if (rc) { + CAM_ERR(CAM_ICP, "Regulator set mode %s failed", + soc_info->rgltr_name[i]); + goto rgltr_set_mode_failed; + } + } + return 0; + +rgltr_set_mode_failed: + for (i = i - 1; i >= 0; i--) + if (soc_info->rgltr[i]) + regulator_set_mode(soc_info->rgltr[i], + REGULATOR_MODE_FAST); + + return rc; +} + +int cam_bps_update_clk_rate(struct cam_hw_soc_info *soc_info, + uint32_t clk_rate) +{ + int32_t src_clk_idx; + + if (!soc_info) + return -EINVAL; + + src_clk_idx = soc_info->src_clk_idx; + + if ((soc_info->clk_level_valid[CAM_TURBO_VOTE] == true) && + (soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx] != 0) && + (clk_rate > soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx])) { + CAM_DBG(CAM_PERF, "clk_rate %d greater than max, reset to %d", + clk_rate, + soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]); + clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]; + } + + return cam_soc_util_set_src_clk_rate(soc_info, clk_rate); +} + +int cam_bps_toggle_clk(struct cam_hw_soc_info *soc_info, bool clk_enable) +{ + int rc = 0; + + if (clk_enable) + rc = cam_soc_util_clk_enable_default(soc_info, CAM_SVS_VOTE); + else + cam_soc_util_clk_disable_default(soc_info); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_soc.h b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..da4feac909e40592c4c5addee522d98418da2984 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/bps_soc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_BPS_SOC_H_ +#define _CAM_BPS_SOC_H_ + +#include "cam_soc_util.h" + +int cam_bps_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t bps_irq_handler, void *irq_data); + +int cam_bps_enable_soc_resources(struct cam_hw_soc_info *soc_info); + +int cam_bps_disable_soc_resources(struct cam_hw_soc_info *soc_info, + bool disable_clk); + +int cam_bps_get_gdsc_control(struct cam_hw_soc_info *soc_info); + +int cam_bps_transfer_gdsc_control(struct cam_hw_soc_info *soc_info); + +int cam_bps_update_clk_rate(struct cam_hw_soc_info *soc_info, + uint32_t clk_rate); +int cam_bps_toggle_clk(struct cam_hw_soc_info *soc_info, bool clk_enable); +#endif /* _CAM_BPS_SOC_H_*/ diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/Makefile b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..8ad76910083c26ce4594aa15a455be3e7c2822b4 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/isp/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/isp/isp_hw/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/isp/isp_hw/isp_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/fw_inc/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_icp_hw_mgr.o diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c new file mode 100644 index 0000000000000000000000000000000000000000..fc3f73be380a396a63ca2edfc749ecdcbf353ce9 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -0,0 +1,6094 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cam_sync_api.h" +#include "cam_packet_util.h" +#include "cam_hw.h" +#include "cam_hw_mgr_intf.h" +#include "cam_icp_hw_mgr_intf.h" +#include "cam_icp_hw_mgr.h" +#include "cam_a5_hw_intf.h" +#include "cam_bps_hw_intf.h" +#include "cam_ipe_hw_intf.h" +#include "cam_smmu_api.h" +#include "cam_mem_mgr.h" +#include "hfi_intf.h" +#include "hfi_reg.h" +#include "hfi_session_defs.h" +#include "hfi_sys_defs.h" +#include "cam_req_mgr_workq.h" +#include "cam_mem_mgr.h" +#include "a5_core.h" +#include "hfi_sys_defs.h" +#include "cam_debug_util.h" +#include "cam_soc_util.h" +#include "cam_trace.h" +#include "cam_cpas_api.h" +#include "cam_common_util.h" + +#define ICP_WORKQ_TASK_CMD_TYPE 1 +#define ICP_WORKQ_TASK_MSG_TYPE 2 + +#define ICP_DEV_TYPE_TO_CLK_TYPE(dev_type) \ + ((dev_type == CAM_ICP_RES_TYPE_BPS) ? ICP_CLK_HW_BPS : ICP_CLK_HW_IPE) + +#define ICP_DEVICE_IDLE_TIMEOUT 400 + +static struct cam_icp_hw_mgr icp_hw_mgr; + +static void cam_icp_mgr_process_dbg_buf(unsigned int debug_lvl); + +static int cam_icp_dump_io_cfg(struct cam_icp_hw_ctx_data *ctx_data, + int32_t buf_handle) +{ + uintptr_t vaddr_ptr; + uint32_t *ptr; + size_t len; + int rc, i; + char buf[512]; + int used = 0; + + rc = cam_mem_get_cpu_buf(buf_handle, &vaddr_ptr, &len); + if (rc) { + CAM_ERR(CAM_ICP, "Unable to get io_cfg buf address for %d", + ctx_data->ctx_id); + return rc; + } + + len = len / sizeof(uint32_t); + ptr = (uint32_t *)vaddr_ptr; + for (i = 0; i < len; i++) { + used += snprintf(buf + used, + sizeof(buf) - used, "0X%08X-", ptr[i]); + if (!(i % 8)) { + CAM_INFO(CAM_ICP, "%s: %s", __func__, buf); + used = 0; + } + } + cam_mem_put_cpu_buf(buf_handle); + return rc; +} + +static const char *cam_icp_dev_type_to_name( + uint32_t dev_type) +{ + switch (dev_type) { + case CAM_ICP_RES_TYPE_BPS: + return "BPS"; + case CAM_ICP_RES_TYPE_IPE_RT: + return "IPE_RT"; + case CAM_ICP_RES_TYPE_IPE: + return "IPE"; + default: + return "Invalid dev type"; + } +} + +static int cam_icp_send_ubwc_cfg(struct cam_icp_hw_mgr *hw_mgr) +{ + struct cam_hw_intf *a5_dev_intf = NULL; + int rc; + + a5_dev_intf = hw_mgr->a5_dev_intf; + if (!a5_dev_intf) { + CAM_ERR(CAM_ICP, "a5_dev_intf is NULL"); + return -EINVAL; + } + + rc = a5_dev_intf->hw_ops.process_cmd( + a5_dev_intf->hw_priv, + CAM_ICP_A5_CMD_UBWC_CFG, NULL, 0); + if (rc) + CAM_ERR(CAM_ICP, "CAM_ICP_A5_CMD_UBWC_CFG is failed"); + + return rc; +} + +static void cam_icp_hw_mgr_clk_info_update(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data) +{ + struct cam_icp_clk_info *hw_mgr_clk_info; + + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) + hw_mgr_clk_info = &hw_mgr->clk_info[ICP_CLK_HW_BPS]; + else + hw_mgr_clk_info = &hw_mgr->clk_info[ICP_CLK_HW_IPE]; + + if (hw_mgr_clk_info->base_clk >= ctx_data->clk_info.base_clk) + hw_mgr_clk_info->base_clk -= ctx_data->clk_info.base_clk; +} + +static void cam_icp_hw_mgr_reset_clk_info(struct cam_icp_hw_mgr *hw_mgr) +{ + int i; + + for (i = 0; i < ICP_CLK_HW_MAX; i++) { + hw_mgr->clk_info[i].base_clk = 0; + hw_mgr->clk_info[i].curr_clk = ICP_CLK_SVS_HZ; + hw_mgr->clk_info[i].threshold = ICP_OVER_CLK_THRESHOLD; + hw_mgr->clk_info[i].over_clked = 0; + hw_mgr->clk_info[i].uncompressed_bw = CAM_CPAS_DEFAULT_AXI_BW; + hw_mgr->clk_info[i].compressed_bw = CAM_CPAS_DEFAULT_AXI_BW; + } + hw_mgr->icp_default_clk = ICP_CLK_SVS_HZ; +} + +static int cam_icp_get_actual_clk_rate_idx( + struct cam_icp_hw_ctx_data *ctx_data, uint32_t base_clk) +{ + int i; + + for (i = 0; i < CAM_MAX_VOTE; i++) + if (ctx_data->clk_info.clk_rate[i] >= base_clk) + return i; + + /* + * Caller has to ensure returned index is within array + * size bounds while accessing that index. + */ + + return i; +} + +static bool cam_icp_is_over_clk(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, + struct cam_icp_clk_info *hw_mgr_clk_info) +{ + int base_clk_idx; + int curr_clk_idx; + + base_clk_idx = cam_icp_get_actual_clk_rate_idx(ctx_data, + hw_mgr_clk_info->base_clk); + + curr_clk_idx = cam_icp_get_actual_clk_rate_idx(ctx_data, + hw_mgr_clk_info->curr_clk); + + CAM_DBG(CAM_PERF, "bc_idx = %d cc_idx = %d %d %d", + base_clk_idx, curr_clk_idx, hw_mgr_clk_info->base_clk, + hw_mgr_clk_info->curr_clk); + + if (curr_clk_idx > base_clk_idx) + return true; + + return false; +} + +static int cam_icp_get_lower_clk_rate(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, uint32_t base_clk) +{ + int i; + + i = cam_icp_get_actual_clk_rate_idx(ctx_data, base_clk); + + if (i > 0) + return ctx_data->clk_info.clk_rate[i - 1]; + + CAM_DBG(CAM_PERF, "Already clk at lower level"); + return base_clk; +} + +static int cam_icp_get_next_clk_rate(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, uint32_t base_clk) +{ + int i; + + i = cam_icp_get_actual_clk_rate_idx(ctx_data, base_clk); + + if (i < CAM_MAX_VOTE - 1) + return ctx_data->clk_info.clk_rate[i + 1]; + + CAM_DBG(CAM_PERF, "Already clk at higher level"); + + return base_clk; +} + +static int cam_icp_get_actual_clk_rate(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, uint32_t base_clk) +{ + int i; + + for (i = 0; i < CAM_MAX_VOTE; i++) + if (ctx_data->clk_info.clk_rate[i] >= base_clk) + return ctx_data->clk_info.clk_rate[i]; + + return base_clk; +} + +static int cam_icp_supported_clk_rates(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data) +{ + int i; + struct cam_hw_soc_info *soc_info; + struct cam_hw_intf *dev_intf = NULL; + struct cam_hw_info *dev = NULL; + + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) + dev_intf = hw_mgr->bps_dev_intf; + else + dev_intf = hw_mgr->ipe0_dev_intf; + + if (!dev_intf) { + CAM_ERR(CAM_ICP, "dev_intf is invalid"); + return -EINVAL; + } + dev = (struct cam_hw_info *)dev_intf->hw_priv; + soc_info = &dev->soc_info; + + for (i = 0; i < CAM_MAX_VOTE; i++) { + ctx_data->clk_info.clk_rate[i] = + soc_info->clk_rate[i][soc_info->src_clk_idx]; + CAM_DBG(CAM_PERF, "clk_info[%d] = %d", + i, ctx_data->clk_info.clk_rate[i]); + } + + return 0; +} + +static int cam_icp_clk_idx_from_req_id(struct cam_icp_hw_ctx_data *ctx_data, + uint64_t req_id) +{ + struct hfi_frame_process_info *frame_process; + int i; + + frame_process = &ctx_data->hfi_frame_process; + + for (i = 0; i < CAM_FRAME_CMD_MAX; i++) + if (frame_process->request_id[i] == req_id) + return i; + + return 0; +} + +static int cam_icp_ctx_clk_info_init(struct cam_icp_hw_ctx_data *ctx_data) +{ + int i; + + ctx_data->clk_info.curr_fc = 0; + ctx_data->clk_info.base_clk = 0; + ctx_data->clk_info.uncompressed_bw = 0; + ctx_data->clk_info.compressed_bw = 0; + for (i = 0; i < CAM_ICP_MAX_PER_PATH_VOTES; i++) { + ctx_data->clk_info.axi_path[i].camnoc_bw = 0; + ctx_data->clk_info.axi_path[i].mnoc_ab_bw = 0; + ctx_data->clk_info.axi_path[i].mnoc_ib_bw = 0; + } + + cam_icp_supported_clk_rates(&icp_hw_mgr, ctx_data); + + return 0; +} + +static bool cam_icp_frame_pending(struct cam_icp_hw_ctx_data *ctx_data) +{ + return !bitmap_empty(ctx_data->hfi_frame_process.bitmap, + CAM_FRAME_CMD_MAX); +} + +static int cam_icp_ctx_timer_reset(struct cam_icp_hw_ctx_data *ctx_data) +{ + if (ctx_data && ctx_data->watch_dog) { + ctx_data->watch_dog_reset_counter++; + CAM_DBG(CAM_PERF, "reset timer : ctx_id = %d, counter=%d", + ctx_data->ctx_id, ctx_data->watch_dog_reset_counter); + crm_timer_reset(ctx_data->watch_dog); + } + + return 0; +} + +static void cam_icp_device_timer_reset(struct cam_icp_hw_mgr *hw_mgr, + int device_index) +{ + if ((device_index >= ICP_CLK_HW_MAX) || (!hw_mgr)) + return; + + if (hw_mgr->clk_info[device_index].watch_dog) { + CAM_DBG(CAM_PERF, "reset timer : device_index = %d", + device_index); + crm_timer_reset(hw_mgr->clk_info[device_index].watch_dog); + hw_mgr->clk_info[device_index].watch_dog_reset_counter++; + } +} + +static int32_t cam_icp_deinit_idle_clk(void *priv, void *data) +{ + struct cam_icp_hw_mgr *hw_mgr = (struct cam_icp_hw_mgr *)priv; + struct clk_work_data *task_data = (struct clk_work_data *)data; + struct cam_icp_clk_info *clk_info = + (struct cam_icp_clk_info *)task_data->data; + uint32_t id; + uint32_t i; + struct cam_icp_hw_ctx_data *ctx_data; + struct cam_hw_intf *ipe0_dev_intf = NULL; + struct cam_hw_intf *ipe1_dev_intf = NULL; + struct cam_hw_intf *bps_dev_intf = NULL; + struct cam_hw_intf *dev_intf = NULL; + struct cam_a5_clk_update_cmd clk_upd_cmd; + int rc = 0; + bool busy = false; + + ipe0_dev_intf = hw_mgr->ipe0_dev_intf; + ipe1_dev_intf = hw_mgr->ipe1_dev_intf; + bps_dev_intf = hw_mgr->bps_dev_intf; + + clk_info->base_clk = 0; + clk_info->curr_clk = 0; + clk_info->over_clked = 0; + + mutex_lock(&hw_mgr->hw_mgr_mutex); + + for (i = 0; i < CAM_ICP_CTX_MAX; i++) { + ctx_data = &hw_mgr->ctx_data[i]; + mutex_lock(&ctx_data->ctx_mutex); + if ((ctx_data->state == CAM_ICP_CTX_STATE_ACQUIRED) && + (ICP_DEV_TYPE_TO_CLK_TYPE( + ctx_data->icp_dev_acquire_info->dev_type) + == clk_info->hw_type)) { + busy = cam_icp_frame_pending(ctx_data); + if (busy) { + mutex_unlock(&ctx_data->ctx_mutex); + break; + } + cam_icp_ctx_clk_info_init(ctx_data); + } + mutex_unlock(&ctx_data->ctx_mutex); + } + + if (busy) { + cam_icp_device_timer_reset(hw_mgr, clk_info->hw_type); + rc = -EBUSY; + goto done; + } + + if ((!ipe0_dev_intf) || (!bps_dev_intf)) { + CAM_ERR(CAM_ICP, "dev intfs are wrong, failed to update clk"); + rc = -EINVAL; + goto done; + } + + if (clk_info->hw_type == ICP_CLK_HW_BPS) { + dev_intf = bps_dev_intf; + id = CAM_ICP_BPS_CMD_DISABLE_CLK; + } else if (clk_info->hw_type == ICP_CLK_HW_IPE) { + dev_intf = ipe0_dev_intf; + id = CAM_ICP_IPE_CMD_DISABLE_CLK; + } else { + CAM_ERR(CAM_ICP, "Error"); + goto done; + } + + CAM_DBG(CAM_PERF, "Disable %d", clk_info->hw_type); + + clk_upd_cmd.ipe_bps_pc_enable = icp_hw_mgr.ipe_bps_pc_flag; + + dev_intf->hw_ops.process_cmd(dev_intf->hw_priv, id, + &clk_upd_cmd, sizeof(struct cam_a5_clk_update_cmd)); + + if (clk_info->hw_type != ICP_CLK_HW_BPS) + if (ipe1_dev_intf) + ipe1_dev_intf->hw_ops.process_cmd( + ipe1_dev_intf->hw_priv, id, + &clk_upd_cmd, + sizeof(struct cam_a5_clk_update_cmd)); + +done: + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static int32_t cam_icp_ctx_timer(void *priv, void *data) +{ + struct clk_work_data *task_data = (struct clk_work_data *)data; + struct cam_icp_hw_ctx_data *ctx_data = + (struct cam_icp_hw_ctx_data *)task_data->data; + struct cam_icp_hw_mgr *hw_mgr = &icp_hw_mgr; + uint32_t id; + uint64_t temp; + struct cam_hw_intf *ipe0_dev_intf = NULL; + struct cam_hw_intf *ipe1_dev_intf = NULL; + struct cam_hw_intf *bps_dev_intf = NULL; + struct cam_hw_intf *dev_intf = NULL; + struct cam_icp_clk_info *clk_info; + struct cam_icp_cpas_vote clk_update; + int i = 0; + int device_share_ratio = 1; + uint64_t total_ab_bw = 0; + + if (!ctx_data) { + CAM_ERR(CAM_ICP, "ctx_data is NULL, failed to update clk"); + return -EINVAL; + } + + mutex_lock(&ctx_data->ctx_mutex); + if ((ctx_data->state != CAM_ICP_CTX_STATE_ACQUIRED) || + (ctx_data->watch_dog_reset_counter == 0)) { + CAM_DBG(CAM_PERF, "state %d, counter=%d", + ctx_data->state, ctx_data->watch_dog_reset_counter); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + + if (cam_icp_frame_pending(ctx_data)) { + cam_icp_ctx_timer_reset(ctx_data); + mutex_unlock(&ctx_data->ctx_mutex); + return -EBUSY; + } + + CAM_DBG(CAM_PERF, + "E :ctx_id = %d ubw = %lld cbw = %lld curr_fc = %u bc = %u", + ctx_data->ctx_id, + ctx_data->clk_info.uncompressed_bw, + ctx_data->clk_info.compressed_bw, + ctx_data->clk_info.curr_fc, ctx_data->clk_info.base_clk); + + ipe0_dev_intf = hw_mgr->ipe0_dev_intf; + ipe1_dev_intf = hw_mgr->ipe1_dev_intf; + bps_dev_intf = hw_mgr->bps_dev_intf; + + if ((!ipe0_dev_intf) || (!bps_dev_intf)) { + CAM_ERR(CAM_ICP, "dev intfs are wrong, failed to update clk"); + mutex_unlock(&ctx_data->ctx_mutex); + return -EINVAL; + } + + if (!ctx_data->icp_dev_acquire_info) { + CAM_WARN(CAM_ICP, "NULL acquire info"); + mutex_unlock(&ctx_data->ctx_mutex); + return -EINVAL; + } + + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) { + dev_intf = bps_dev_intf; + clk_info = &hw_mgr->clk_info[ICP_CLK_HW_BPS]; + id = CAM_ICP_BPS_CMD_VOTE_CPAS; + } else { + dev_intf = ipe0_dev_intf; + clk_info = &hw_mgr->clk_info[ICP_CLK_HW_IPE]; + id = CAM_ICP_IPE_CMD_VOTE_CPAS; + } + + /* + * Since there are 2 devices, we assume the load is evenly shared + * between HWs and corresponding AXI paths. So divide total bw by half + * to vote on each device + */ + if ((ctx_data->icp_dev_acquire_info->dev_type != + CAM_ICP_RES_TYPE_BPS) && (ipe1_dev_intf)) + device_share_ratio = 2; + + if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_V1) { + clk_update.axi_vote.num_paths = 1; + if (ctx_data->icp_dev_acquire_info->dev_type == + CAM_ICP_RES_TYPE_BPS) { + clk_update.axi_vote.axi_path[0].path_data_type = + CAM_BPS_DEFAULT_AXI_PATH; + clk_update.axi_vote.axi_path[0].transac_type = + CAM_BPS_DEFAULT_AXI_TRANSAC; + } else { + clk_update.axi_vote.axi_path[0].path_data_type = + CAM_IPE_DEFAULT_AXI_PATH; + clk_update.axi_vote.axi_path[0].transac_type = + CAM_IPE_DEFAULT_AXI_TRANSAC; + } + + clk_info->compressed_bw -= ctx_data->clk_info.compressed_bw; + clk_info->uncompressed_bw -= ctx_data->clk_info.uncompressed_bw; + + total_ab_bw = clk_info->compressed_bw; + + ctx_data->clk_info.uncompressed_bw = 0; + ctx_data->clk_info.compressed_bw = 0; + ctx_data->clk_info.curr_fc = 0; + ctx_data->clk_info.base_clk = 0; + + clk_update.axi_vote.num_paths = 1; + + temp = clk_info->uncompressed_bw; + do_div(temp, device_share_ratio); + clk_update.axi_vote.axi_path[0].camnoc_bw = temp; + + temp = clk_info->compressed_bw; + do_div(temp, device_share_ratio); + clk_update.axi_vote.axi_path[0].mnoc_ab_bw = temp; + clk_update.axi_vote.axi_path[0].mnoc_ib_bw = temp; + clk_update.axi_vote.axi_path[0].ddr_ab_bw = temp; + clk_update.axi_vote.axi_path[0].ddr_ib_bw = temp; + } else { + int path_index; + + /* + * Remove previous vote of this context from hw mgr first. + * hw_mgr_clk_info has all valid paths, with each path in its + * own index. BW that we wanted to vote now is after removing + * current context's vote from hw mgr consolidated vote + */ + for (i = 0; i < ctx_data->clk_info.num_paths; i++) { + if (ctx_data->icp_dev_acquire_info->dev_type == + CAM_ICP_RES_TYPE_BPS) { + /* + * By assuming BPS has Read-All, Write-All + * votes only. + */ + path_index = + ctx_data->clk_info.axi_path[i] + .transac_type - + CAM_AXI_TRANSACTION_READ; + } else { + path_index = + ctx_data->clk_info.axi_path[i] + .path_data_type - + CAM_AXI_PATH_DATA_IPE_START_OFFSET; + } + + if (path_index >= CAM_ICP_MAX_PER_PATH_VOTES) { + CAM_WARN(CAM_PERF, + "Invalid path %d, start offset=%d, max=%d", + ctx_data->clk_info.axi_path[i] + .path_data_type, + CAM_AXI_PATH_DATA_IPE_START_OFFSET, + CAM_ICP_MAX_PER_PATH_VOTES); + continue; + } + + clk_info->axi_path[path_index].camnoc_bw -= + ctx_data->clk_info.axi_path[i].camnoc_bw; + clk_info->axi_path[path_index].mnoc_ab_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ab_bw; + clk_info->axi_path[path_index].mnoc_ib_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ib_bw; + clk_info->axi_path[path_index].ddr_ab_bw -= + ctx_data->clk_info.axi_path[i].ddr_ab_bw; + clk_info->axi_path[path_index].ddr_ib_bw -= + ctx_data->clk_info.axi_path[i].ddr_ib_bw; + + total_ab_bw += + clk_info->axi_path[path_index].mnoc_ab_bw; + } + + memset(&ctx_data->clk_info.axi_path[0], 0, + CAM_ICP_MAX_PER_PATH_VOTES * + sizeof(struct cam_axi_per_path_bw_vote)); + ctx_data->clk_info.curr_fc = 0; + ctx_data->clk_info.base_clk = 0; + + clk_update.axi_vote.num_paths = clk_info->num_paths; + memcpy(&clk_update.axi_vote.axi_path[0], + &clk_info->axi_path[0], + clk_update.axi_vote.num_paths * + sizeof(struct cam_axi_per_path_bw_vote)); + + if (device_share_ratio > 1) { + for (i = 0; i < clk_update.axi_vote.num_paths; i++) { + do_div( + clk_update.axi_vote.axi_path[i].camnoc_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].mnoc_ab_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].mnoc_ib_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].ddr_ab_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].ddr_ib_bw, + device_share_ratio); + } + } + } + + clk_update.axi_vote_valid = true; + + if (total_ab_bw == 0) { + /* If no more contexts are active, reduce AHB vote to minimum */ + clk_update.ahb_vote.type = CAM_VOTE_ABSOLUTE; + clk_update.ahb_vote.vote.level = CAM_LOWSVS_VOTE; + clk_update.ahb_vote_valid = true; + } else { + clk_update.ahb_vote_valid = false; + } + + dev_intf->hw_ops.process_cmd(dev_intf->hw_priv, id, + &clk_update, sizeof(clk_update)); + + /* + * Vote half bandwidth each on both devices. + * Total bw at mnoc - CPAS will take care of adding up. + * camnoc clk calculate is more accurate this way. + */ + if ((ctx_data->icp_dev_acquire_info->dev_type != + CAM_ICP_RES_TYPE_BPS) && (ipe1_dev_intf)) + ipe1_dev_intf->hw_ops.process_cmd(ipe1_dev_intf->hw_priv, id, + &clk_update, sizeof(clk_update)); + + CAM_DBG(CAM_PERF, "X :ctx_id = %d curr_fc = %u bc = %u", + ctx_data->ctx_id, ctx_data->clk_info.curr_fc, + ctx_data->clk_info.base_clk); + mutex_unlock(&ctx_data->ctx_mutex); + + return 0; +} + +static void cam_icp_ctx_timer_cb(struct timer_list *timer_data) +{ + unsigned long flags; + struct crm_workq_task *task; + struct clk_work_data *task_data; + struct cam_req_mgr_timer *timer = + container_of(timer_data, struct cam_req_mgr_timer, sys_timer); + + spin_lock_irqsave(&icp_hw_mgr.hw_mgr_lock, flags); + task = cam_req_mgr_workq_get_task(icp_hw_mgr.timer_work); + if (!task) { + CAM_ERR(CAM_ICP, "no empty task"); + spin_unlock_irqrestore(&icp_hw_mgr.hw_mgr_lock, flags); + return; + } + + task_data = (struct clk_work_data *)task->payload; + task_data->data = timer->parent; + task_data->type = ICP_WORKQ_TASK_MSG_TYPE; + task->process_cb = cam_icp_ctx_timer; + cam_req_mgr_workq_enqueue_task(task, &icp_hw_mgr, + CRM_TASK_PRIORITY_0); + spin_unlock_irqrestore(&icp_hw_mgr.hw_mgr_lock, flags); +} + +static void cam_icp_device_timer_cb(struct timer_list *timer_data) +{ + unsigned long flags; + struct crm_workq_task *task; + struct clk_work_data *task_data; + struct cam_req_mgr_timer *timer = + container_of(timer_data, struct cam_req_mgr_timer, sys_timer); + + spin_lock_irqsave(&icp_hw_mgr.hw_mgr_lock, flags); + task = cam_req_mgr_workq_get_task(icp_hw_mgr.timer_work); + if (!task) { + CAM_ERR(CAM_ICP, "no empty task"); + spin_unlock_irqrestore(&icp_hw_mgr.hw_mgr_lock, flags); + return; + } + + task_data = (struct clk_work_data *)task->payload; + task_data->data = timer->parent; + task_data->type = ICP_WORKQ_TASK_MSG_TYPE; + task->process_cb = cam_icp_deinit_idle_clk; + cam_req_mgr_workq_enqueue_task(task, &icp_hw_mgr, + CRM_TASK_PRIORITY_0); + spin_unlock_irqrestore(&icp_hw_mgr.hw_mgr_lock, flags); +} + +static int cam_icp_clk_info_init(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data) +{ + int i, j; + + for (i = 0; i < ICP_CLK_HW_MAX; i++) { + hw_mgr->clk_info[i].base_clk = ICP_CLK_SVS_HZ; + hw_mgr->clk_info[i].curr_clk = ICP_CLK_SVS_HZ; + hw_mgr->clk_info[i].threshold = ICP_OVER_CLK_THRESHOLD; + hw_mgr->clk_info[i].over_clked = 0; + hw_mgr->clk_info[i].uncompressed_bw = CAM_CPAS_DEFAULT_AXI_BW; + hw_mgr->clk_info[i].compressed_bw = CAM_CPAS_DEFAULT_AXI_BW; + for (j = 0; j < CAM_ICP_MAX_PER_PATH_VOTES; j++) { + hw_mgr->clk_info[i].axi_path[j].path_data_type = 0; + hw_mgr->clk_info[i].axi_path[j].transac_type = 0; + hw_mgr->clk_info[i].axi_path[j].camnoc_bw = 0; + hw_mgr->clk_info[i].axi_path[j].mnoc_ab_bw = 0; + hw_mgr->clk_info[i].axi_path[j].mnoc_ib_bw = 0; + } + + hw_mgr->clk_info[i].hw_type = i; + hw_mgr->clk_info[i].watch_dog_reset_counter = 0; + } + + hw_mgr->icp_default_clk = ICP_CLK_SVS_HZ; + + return 0; +} + +static int cam_icp_ctx_timer_start(struct cam_icp_hw_ctx_data *ctx_data) +{ + int rc = 0; + + rc = crm_timer_init(&ctx_data->watch_dog, + 200, ctx_data, &cam_icp_ctx_timer_cb); + if (rc) + CAM_ERR(CAM_ICP, "Failed to start timer"); + + ctx_data->watch_dog_reset_counter = 0; + + CAM_DBG(CAM_PERF, "start timer : ctx_id = %d", ctx_data->ctx_id); + return rc; +} + +static int cam_icp_device_timer_start(struct cam_icp_hw_mgr *hw_mgr) +{ + int rc = 0; + int i; + + for (i = 0; i < ICP_CLK_HW_MAX; i++) { + if (!hw_mgr->clk_info[i].watch_dog) { + rc = crm_timer_init(&hw_mgr->clk_info[i].watch_dog, + ICP_DEVICE_IDLE_TIMEOUT, &hw_mgr->clk_info[i], + &cam_icp_device_timer_cb); + + if (rc) + CAM_ERR(CAM_ICP, "Failed to start timer %d", i); + + hw_mgr->clk_info[i].watch_dog_reset_counter = 0; + } + } + + return rc; +} + +static int cam_icp_ctx_timer_stop(struct cam_icp_hw_ctx_data *ctx_data) +{ + if (ctx_data->watch_dog) { + CAM_DBG(CAM_PERF, "stop timer : ctx_id = %d", ctx_data->ctx_id); + ctx_data->watch_dog_reset_counter = 0; + crm_timer_exit(&ctx_data->watch_dog); + ctx_data->watch_dog = NULL; + } + + return 0; +} + +static void cam_icp_device_timer_stop(struct cam_icp_hw_mgr *hw_mgr) +{ + if (!hw_mgr->bps_ctxt_cnt && + hw_mgr->clk_info[ICP_CLK_HW_BPS].watch_dog) { + hw_mgr->clk_info[ICP_CLK_HW_BPS].watch_dog_reset_counter = 0; + crm_timer_exit(&hw_mgr->clk_info[ICP_CLK_HW_BPS].watch_dog); + hw_mgr->clk_info[ICP_CLK_HW_BPS].watch_dog = NULL; + } + + if (!hw_mgr->ipe_ctxt_cnt && + hw_mgr->clk_info[ICP_CLK_HW_IPE].watch_dog) { + hw_mgr->clk_info[ICP_CLK_HW_IPE].watch_dog_reset_counter = 0; + crm_timer_exit(&hw_mgr->clk_info[ICP_CLK_HW_IPE].watch_dog); + hw_mgr->clk_info[ICP_CLK_HW_IPE].watch_dog = NULL; + } +} + +static uint32_t cam_icp_mgr_calc_base_clk(uint32_t frame_cycles, + uint64_t budget) +{ + uint64_t base_clk; + uint64_t mul = 1000000000; + + base_clk = frame_cycles * mul; + do_div(base_clk, budget); + + CAM_DBG(CAM_PERF, "budget = %lld fc = %d ib = %lld base_clk = %lld", + budget, frame_cycles, + (long long)(frame_cycles * mul), base_clk); + + return base_clk; +} + +static bool cam_icp_busy_prev_reqs(struct hfi_frame_process_info *frm_process, + uint64_t req_id) +{ + int i; + int cnt; + + for (i = 0, cnt = 0; i < CAM_FRAME_CMD_MAX; i++) { + if (frm_process->request_id[i]) { + if (frm_process->fw_process_flag[i]) { + CAM_DBG(CAM_PERF, "r id = %lld busy = %d", + frm_process->request_id[i], + frm_process->fw_process_flag[i]); + cnt++; + } + } + } + if (cnt > 1) + return true; + + return false; +} + +static int cam_icp_calc_total_clk(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_clk_info *hw_mgr_clk_info, uint32_t dev_type) +{ + int i; + struct cam_icp_hw_ctx_data *ctx_data; + + hw_mgr_clk_info->base_clk = 0; + for (i = 0; i < CAM_ICP_CTX_MAX; i++) { + ctx_data = &hw_mgr->ctx_data[i]; + if (ctx_data->state == CAM_ICP_CTX_STATE_ACQUIRED && + ICP_DEV_TYPE_TO_CLK_TYPE( + ctx_data->icp_dev_acquire_info->dev_type) == + ICP_DEV_TYPE_TO_CLK_TYPE(dev_type)) + hw_mgr_clk_info->base_clk += + ctx_data->clk_info.base_clk; + } + + return 0; +} + +static bool cam_icp_update_clk_busy(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, + struct cam_icp_clk_info *hw_mgr_clk_info, + struct cam_icp_clk_bw_request *clk_info, + uint32_t base_clk) +{ + uint32_t next_clk_level; + uint32_t actual_clk; + bool rc = false; + + /* 1. if current request frame cycles(fc) are more than previous + * frame fc + * Calculate the new base clock. + * if sum of base clocks are more than next available clk level + * Update clock rate, change curr_clk_rate to sum of base clock + * rates and make over_clked to zero + * else + * Update clock rate to next level, update curr_clk_rate and make + * overclked cnt to zero + * 2. if current fc is less than or equal to previous frame fc + * Still Bump up the clock to next available level + * if it is available, then update clock, make overclk cnt to + * zero. If the clock is already at highest clock rate then + * no need to update the clock + */ + ctx_data->clk_info.base_clk = base_clk; + hw_mgr_clk_info->over_clked = 0; + if (clk_info->frame_cycles > ctx_data->clk_info.curr_fc) { + cam_icp_calc_total_clk(hw_mgr, hw_mgr_clk_info, + ctx_data->icp_dev_acquire_info->dev_type); + actual_clk = cam_icp_get_actual_clk_rate(hw_mgr, + ctx_data, base_clk); + if (hw_mgr_clk_info->base_clk > actual_clk) { + hw_mgr_clk_info->curr_clk = hw_mgr_clk_info->base_clk; + } else { + next_clk_level = cam_icp_get_next_clk_rate(hw_mgr, + ctx_data, hw_mgr_clk_info->curr_clk); + hw_mgr_clk_info->curr_clk = next_clk_level; + } + rc = true; + } else { + next_clk_level = + cam_icp_get_next_clk_rate(hw_mgr, ctx_data, + hw_mgr_clk_info->curr_clk); + if (hw_mgr_clk_info->curr_clk < next_clk_level) { + hw_mgr_clk_info->curr_clk = next_clk_level; + rc = true; + } + } + ctx_data->clk_info.curr_fc = clk_info->frame_cycles; + + return rc; +} + +static bool cam_icp_update_clk_overclk_free(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, + struct cam_icp_clk_info *hw_mgr_clk_info, + struct cam_icp_clk_bw_request *clk_info, + uint32_t base_clk) +{ + int rc = false; + + /* + * In caseof no pending packets case + * 1. In caseof overclk cnt is less than threshold, increase + * overclk count and no update in the clock rate + * 2. In caseof overclk cnt is greater than or equal to threshold + * then lower clock rate by one level and update hw_mgr current + * clock value. + * a. In case of new clock rate greater than sum of clock + * rates, reset overclk count value to zero if it is + * overclock + * b. if it is less than sum of base clocks then go to next + * level of clock and make overclk count to zero + * c. if it is same as sum of base clock rates update overclock + * cnt to 0 + */ + if (hw_mgr_clk_info->over_clked < hw_mgr_clk_info->threshold) { + hw_mgr_clk_info->over_clked++; + rc = false; + } else { + hw_mgr_clk_info->curr_clk = + cam_icp_get_lower_clk_rate(hw_mgr, ctx_data, + hw_mgr_clk_info->curr_clk); + if (hw_mgr_clk_info->curr_clk > hw_mgr_clk_info->base_clk) { + if (cam_icp_is_over_clk(hw_mgr, ctx_data, + hw_mgr_clk_info)) + hw_mgr_clk_info->over_clked = 0; + } else if (hw_mgr_clk_info->curr_clk < + hw_mgr_clk_info->base_clk) { + hw_mgr_clk_info->curr_clk = + cam_icp_get_next_clk_rate(hw_mgr, ctx_data, + hw_mgr_clk_info->curr_clk); + hw_mgr_clk_info->over_clked = 0; + } else if (hw_mgr_clk_info->curr_clk == + hw_mgr_clk_info->base_clk) { + hw_mgr_clk_info->over_clked = 0; + } + rc = true; + } + + return rc; +} + +static bool cam_icp_update_clk_free(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, + struct cam_icp_clk_info *hw_mgr_clk_info, + struct cam_icp_clk_bw_request *clk_info, + uint32_t base_clk) +{ + int rc = false; + bool over_clocked = false; + + ctx_data->clk_info.curr_fc = clk_info->frame_cycles; + ctx_data->clk_info.base_clk = base_clk; + cam_icp_calc_total_clk(hw_mgr, hw_mgr_clk_info, + ctx_data->icp_dev_acquire_info->dev_type); + + /* + * Current clock is not always sum of base clocks, due to + * clock scales update to next higher or lower levels, it + * equals to one of discrete clock values supported by hardware. + * So even current clock is higher than sum of base clocks, we + * can not consider it is over clocked. if it is greater than + * discrete clock level then only it is considered as over clock. + * 1. Handle over clock case + * 2. If current clock is less than sum of base clocks + * update current clock + * 3. If current clock is same as sum of base clocks no action + */ + + over_clocked = cam_icp_is_over_clk(hw_mgr, ctx_data, + hw_mgr_clk_info); + + if (hw_mgr_clk_info->curr_clk > hw_mgr_clk_info->base_clk && + over_clocked) { + rc = cam_icp_update_clk_overclk_free(hw_mgr, ctx_data, + hw_mgr_clk_info, clk_info, base_clk); + } else if (hw_mgr_clk_info->curr_clk > hw_mgr_clk_info->base_clk) { + hw_mgr_clk_info->over_clked = 0; + rc = false; + } else if (hw_mgr_clk_info->curr_clk < hw_mgr_clk_info->base_clk) { + hw_mgr_clk_info->curr_clk = cam_icp_get_actual_clk_rate(hw_mgr, + ctx_data, hw_mgr_clk_info->base_clk); + rc = true; + } + + return rc; +} + +static bool cam_icp_debug_clk_update(struct cam_icp_clk_info *hw_mgr_clk_info) +{ + if (icp_hw_mgr.icp_debug_clk < ICP_CLK_TURBO_HZ && + icp_hw_mgr.icp_debug_clk && + icp_hw_mgr.icp_debug_clk != hw_mgr_clk_info->curr_clk) { + hw_mgr_clk_info->base_clk = icp_hw_mgr.icp_debug_clk; + hw_mgr_clk_info->curr_clk = icp_hw_mgr.icp_debug_clk; + hw_mgr_clk_info->uncompressed_bw = icp_hw_mgr.icp_debug_clk; + hw_mgr_clk_info->compressed_bw = icp_hw_mgr.icp_debug_clk; + CAM_DBG(CAM_PERF, "bc = %d cc = %d", + hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk); + return true; + } + + return false; +} + +static bool cam_icp_default_clk_update(struct cam_icp_clk_info *hw_mgr_clk_info) +{ + if (icp_hw_mgr.icp_default_clk != hw_mgr_clk_info->curr_clk) { + hw_mgr_clk_info->base_clk = icp_hw_mgr.icp_default_clk; + hw_mgr_clk_info->curr_clk = icp_hw_mgr.icp_default_clk; + hw_mgr_clk_info->uncompressed_bw = icp_hw_mgr.icp_default_clk; + hw_mgr_clk_info->compressed_bw = icp_hw_mgr.icp_default_clk; + CAM_DBG(CAM_PERF, "bc = %d cc = %d", + hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk); + return true; + } + + return false; +} + +static bool cam_icp_update_bw_v2(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, + struct cam_icp_clk_info *hw_mgr_clk_info, + struct cam_icp_clk_bw_req_internal_v2 *clk_info, + bool busy) +{ + int i, path_index; + bool update_required = true; + + /* + * If current request bandwidth is different from previous frames, then + * recalculate bandwidth of all contexts of same hardware and update + * voting of bandwidth + */ + + for (i = 0; i < clk_info->num_paths; i++) + CAM_DBG(CAM_PERF, "clk_info camnoc = %lld busy = %d", + clk_info->axi_path[i].camnoc_bw, busy); + + if (clk_info->num_paths == ctx_data->clk_info.num_paths) { + update_required = false; + for (i = 0; i < clk_info->num_paths; i++) { + if ((clk_info->axi_path[i].transac_type == + ctx_data->clk_info.axi_path[i].transac_type) && + (clk_info->axi_path[i].path_data_type == + ctx_data->clk_info.axi_path[i].path_data_type) && + (clk_info->axi_path[i].camnoc_bw == + ctx_data->clk_info.axi_path[i].camnoc_bw) && + (clk_info->axi_path[i].mnoc_ab_bw == + ctx_data->clk_info.axi_path[i].mnoc_ab_bw)) { + continue; + } else { + update_required = true; + break; + } + } + } + + if (!update_required) { + CAM_DBG(CAM_PERF, + "Incoming BW hasn't changed, no update required, num_paths=%d", + clk_info->num_paths); + return false; + } + + if (busy) { + for (i = 0; i < clk_info->num_paths; i++) { + if (ctx_data->clk_info.axi_path[i].camnoc_bw > + clk_info->axi_path[i].camnoc_bw) + return false; + } + } + + /* + * Remove previous vote of this context from hw mgr first. + * hw_mgr_clk_info has all valid paths, with each path in its own index + */ + for (i = 0; i < ctx_data->clk_info.num_paths; i++) { + if (ctx_data->icp_dev_acquire_info->dev_type == + CAM_ICP_RES_TYPE_BPS) { + /* By assuming BPS has Read-All, Write-All votes only */ + path_index = + ctx_data->clk_info.axi_path[i].transac_type - + CAM_AXI_TRANSACTION_READ; + } else { + path_index = + ctx_data->clk_info.axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_IPE_START_OFFSET; + } + + if (path_index >= CAM_ICP_MAX_PER_PATH_VOTES) { + CAM_WARN(CAM_PERF, + "Invalid path %d, start offset=%d, max=%d", + ctx_data->clk_info.axi_path[i].path_data_type, + CAM_AXI_PATH_DATA_IPE_START_OFFSET, + CAM_ICP_MAX_PER_PATH_VOTES); + continue; + } + + hw_mgr_clk_info->axi_path[path_index].camnoc_bw -= + ctx_data->clk_info.axi_path[i].camnoc_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ab_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ab_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ib_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw -= + ctx_data->clk_info.axi_path[i].ddr_ab_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw -= + ctx_data->clk_info.axi_path[i].ddr_ib_bw; + } + + ctx_data->clk_info.num_paths = clk_info->num_paths; + + memcpy(&ctx_data->clk_info.axi_path[0], + &clk_info->axi_path[0], + clk_info->num_paths * sizeof(struct cam_axi_per_path_bw_vote)); + + /* + * Add new vote of this context in hw mgr. + * hw_mgr_clk_info has all paths, with each path in its own index + */ + for (i = 0; i < ctx_data->clk_info.num_paths; i++) { + if (ctx_data->icp_dev_acquire_info->dev_type == + CAM_ICP_RES_TYPE_BPS) { + /* By assuming BPS has Read-All, Write-All votes only */ + path_index = + ctx_data->clk_info.axi_path[i].transac_type - + CAM_AXI_TRANSACTION_READ; + } else { + path_index = + ctx_data->clk_info.axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_IPE_START_OFFSET; + } + + if (path_index >= CAM_ICP_MAX_PER_PATH_VOTES) { + CAM_WARN(CAM_PERF, + "Invalid path %d, start offset=%d, max=%d", + ctx_data->clk_info.axi_path[i].path_data_type, + CAM_AXI_PATH_DATA_IPE_START_OFFSET, + CAM_ICP_MAX_PER_PATH_VOTES); + continue; + } + + hw_mgr_clk_info->axi_path[path_index].path_data_type = + ctx_data->clk_info.axi_path[i].path_data_type; + hw_mgr_clk_info->axi_path[path_index].transac_type = + ctx_data->clk_info.axi_path[i].transac_type; + hw_mgr_clk_info->axi_path[path_index].camnoc_bw += + ctx_data->clk_info.axi_path[i].camnoc_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ab_bw += + ctx_data->clk_info.axi_path[i].mnoc_ab_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw += + ctx_data->clk_info.axi_path[i].mnoc_ib_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw += + ctx_data->clk_info.axi_path[i].ddr_ab_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw += + ctx_data->clk_info.axi_path[i].ddr_ib_bw; + + CAM_DBG(CAM_PERF, + "Consolidate Path Vote : Dev[%s] i[%d] path_idx[%d] : [%s %s] [%lld %lld]", + cam_icp_dev_type_to_name( + ctx_data->icp_dev_acquire_info->dev_type), + i, path_index, + cam_cpas_axi_util_trans_type_to_string( + hw_mgr_clk_info->axi_path[path_index].transac_type), + cam_cpas_axi_util_path_type_to_string( + hw_mgr_clk_info->axi_path[path_index].path_data_type), + hw_mgr_clk_info->axi_path[path_index].camnoc_bw, + hw_mgr_clk_info->axi_path[path_index].mnoc_ab_bw); + } + + if (hw_mgr_clk_info->num_paths < ctx_data->clk_info.num_paths) + hw_mgr_clk_info->num_paths = ctx_data->clk_info.num_paths; + + return true; +} + +static bool cam_icp_update_bw(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, + struct cam_icp_clk_info *hw_mgr_clk_info, + struct cam_icp_clk_bw_request *clk_info, + bool busy) +{ + int i; + struct cam_icp_hw_ctx_data *ctx; + + /* + * If current request bandwidth is different from previous frames, then + * recalculate bandwidth of all contexts of same hardware and update + * voting of bandwidth + */ + CAM_DBG(CAM_PERF, "ubw ctx = %lld clk_info ubw = %lld busy = %d", + ctx_data->clk_info.uncompressed_bw, + clk_info->uncompressed_bw, busy); + + if ((clk_info->uncompressed_bw == ctx_data->clk_info.uncompressed_bw) && + (ctx_data->clk_info.uncompressed_bw == + hw_mgr_clk_info->uncompressed_bw)) { + CAM_DBG(CAM_PERF, "Update not required bw=%lld", + ctx_data->clk_info.uncompressed_bw); + return false; + } + + if (busy && + (ctx_data->clk_info.uncompressed_bw > + clk_info->uncompressed_bw)) { + CAM_DBG(CAM_PERF, + "Busy, Update not req existing=%lld, new=%lld", + ctx_data->clk_info.uncompressed_bw, + clk_info->uncompressed_bw); + return false; + } + + ctx_data->clk_info.uncompressed_bw = clk_info->uncompressed_bw; + ctx_data->clk_info.compressed_bw = clk_info->compressed_bw; + hw_mgr_clk_info->uncompressed_bw = 0; + hw_mgr_clk_info->compressed_bw = 0; + for (i = 0; i < CAM_ICP_CTX_MAX; i++) { + ctx = &hw_mgr->ctx_data[i]; + if (ctx->state == CAM_ICP_CTX_STATE_ACQUIRED && + ICP_DEV_TYPE_TO_CLK_TYPE( + ctx->icp_dev_acquire_info->dev_type) == + ICP_DEV_TYPE_TO_CLK_TYPE( + ctx_data->icp_dev_acquire_info->dev_type)) { + hw_mgr_clk_info->uncompressed_bw += + ctx->clk_info.uncompressed_bw; + hw_mgr_clk_info->compressed_bw += + ctx->clk_info.compressed_bw; + CAM_DBG(CAM_PERF, + "Current context=[%lld %lld] Total=[%lld %lld]", + ctx->clk_info.uncompressed_bw, + ctx->clk_info.compressed_bw, + hw_mgr_clk_info->uncompressed_bw, + hw_mgr_clk_info->compressed_bw); + } + } + + return true; +} + +static bool cam_icp_check_clk_update(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, int idx) +{ + bool busy, rc = false; + uint32_t base_clk; + struct cam_icp_clk_bw_request *clk_info; + struct hfi_frame_process_info *frame_info; + uint64_t req_id; + struct cam_icp_clk_info *hw_mgr_clk_info; + + cam_icp_ctx_timer_reset(ctx_data); + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) { + cam_icp_device_timer_reset(hw_mgr, ICP_CLK_HW_BPS); + hw_mgr_clk_info = &hw_mgr->clk_info[ICP_CLK_HW_BPS]; + CAM_DBG(CAM_PERF, "Reset bps timer"); + } else { + cam_icp_device_timer_reset(hw_mgr, ICP_CLK_HW_IPE); + hw_mgr_clk_info = &hw_mgr->clk_info[ICP_CLK_HW_IPE]; + CAM_DBG(CAM_PERF, "Reset ipe timer"); + } + + if (icp_hw_mgr.icp_debug_clk) + return cam_icp_debug_clk_update(hw_mgr_clk_info); + + /* Check is there any pending frames in this context */ + frame_info = &ctx_data->hfi_frame_process; + req_id = frame_info->request_id[idx]; + busy = cam_icp_busy_prev_reqs(frame_info, req_id); + CAM_DBG(CAM_PERF, "busy = %d req_id = %lld", busy, req_id); + + clk_info = &ctx_data->hfi_frame_process.clk_info[idx]; + if (!clk_info->frame_cycles) + return cam_icp_default_clk_update(hw_mgr_clk_info); + + /* Calculate base clk rate */ + base_clk = cam_icp_mgr_calc_base_clk( + clk_info->frame_cycles, clk_info->budget_ns); + ctx_data->clk_info.rt_flag = clk_info->rt_flag; + + if (busy) + rc = cam_icp_update_clk_busy(hw_mgr, ctx_data, + hw_mgr_clk_info, clk_info, base_clk); + else + rc = cam_icp_update_clk_free(hw_mgr, ctx_data, + hw_mgr_clk_info, clk_info, base_clk); + + CAM_DBG(CAM_PERF, "bc = %d cc = %d busy = %d overclk = %d uc = %d", + hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk, + busy, hw_mgr_clk_info->over_clked, rc); + + return rc; +} + +static bool cam_icp_check_bw_update(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, int idx) +{ + bool busy, bw_updated = false; + int i; + struct cam_icp_clk_bw_request *clk_info; + struct cam_icp_clk_bw_req_internal_v2 *clk_info_v2; + struct cam_icp_clk_info *hw_mgr_clk_info; + struct hfi_frame_process_info *frame_info; + uint64_t req_id; + + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) + hw_mgr_clk_info = &hw_mgr->clk_info[ICP_CLK_HW_BPS]; + else + hw_mgr_clk_info = &hw_mgr->clk_info[ICP_CLK_HW_IPE]; + + frame_info = &ctx_data->hfi_frame_process; + req_id = frame_info->request_id[idx]; + busy = cam_icp_busy_prev_reqs(frame_info, req_id); + + if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_V1) { + clk_info = &ctx_data->hfi_frame_process.clk_info[idx]; + + CAM_DBG(CAM_PERF, + "Ctx[%pK][%d] Req[%lld] Current camno=%lld, mnoc=%lld", + ctx_data, ctx_data->ctx_id, req_id, + hw_mgr_clk_info->uncompressed_bw, + hw_mgr_clk_info->compressed_bw); + + bw_updated = cam_icp_update_bw(hw_mgr, ctx_data, + hw_mgr_clk_info, clk_info, busy); + } else if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_V2) { + clk_info_v2 = &ctx_data->hfi_frame_process.clk_info_v2[idx]; + + CAM_DBG(CAM_PERF, "index=%d, num_paths=%d, ctx_data=%pK", + idx, clk_info_v2->num_paths, ctx_data); + + bw_updated = cam_icp_update_bw_v2(hw_mgr, ctx_data, + hw_mgr_clk_info, clk_info_v2, busy); + + for (i = 0; i < hw_mgr_clk_info->num_paths; i++) { + CAM_DBG(CAM_PERF, + "Final path_type: %s, transac_type: %s, camnoc_bw = %lld mnoc_ab_bw = %lld, mnoc_ib_bw = %lld, device: %s", + cam_cpas_axi_util_path_type_to_string( + hw_mgr_clk_info->axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + hw_mgr_clk_info->axi_path[i].transac_type), + hw_mgr_clk_info->axi_path[i].camnoc_bw, + hw_mgr_clk_info->axi_path[i].mnoc_ab_bw, + hw_mgr_clk_info->axi_path[i].mnoc_ib_bw, + cam_icp_dev_type_to_name( + ctx_data->icp_dev_acquire_info->dev_type)); + } + } else { + CAM_ERR(CAM_PERF, "Invalid bw config version: %d", + ctx_data->bw_config_version); + return false; + } + + return bw_updated; +} + +static int cam_icp_update_clk_rate(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data) +{ + uint32_t id; + uint32_t curr_clk_rate; + struct cam_hw_intf *ipe0_dev_intf = NULL; + struct cam_hw_intf *ipe1_dev_intf = NULL; + struct cam_hw_intf *bps_dev_intf = NULL; + struct cam_hw_intf *a5_dev_intf = NULL; + struct cam_hw_intf *dev_intf = NULL; + struct cam_a5_clk_update_cmd clk_upd_cmd; + + ipe0_dev_intf = hw_mgr->ipe0_dev_intf; + ipe1_dev_intf = hw_mgr->ipe1_dev_intf; + bps_dev_intf = hw_mgr->bps_dev_intf; + a5_dev_intf = hw_mgr->a5_dev_intf; + + + if ((!ipe0_dev_intf) || (!bps_dev_intf)) { + CAM_ERR(CAM_ICP, "dev intfs are wrong, failed to update clk"); + return -EINVAL; + } + + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) { + dev_intf = bps_dev_intf; + curr_clk_rate = hw_mgr->clk_info[ICP_CLK_HW_BPS].curr_clk; + id = CAM_ICP_BPS_CMD_UPDATE_CLK; + } else { + dev_intf = ipe0_dev_intf; + curr_clk_rate = hw_mgr->clk_info[ICP_CLK_HW_IPE].curr_clk; + id = CAM_ICP_IPE_CMD_UPDATE_CLK; + } + + CAM_DBG(CAM_PERF, "clk_rate %u for dev_type %d", curr_clk_rate, + ctx_data->icp_dev_acquire_info->dev_type); + clk_upd_cmd.curr_clk_rate = curr_clk_rate; + clk_upd_cmd.ipe_bps_pc_enable = icp_hw_mgr.ipe_bps_pc_flag; + clk_upd_cmd.clk_level = -1; + + dev_intf->hw_ops.process_cmd(dev_intf->hw_priv, id, + &clk_upd_cmd, sizeof(struct cam_a5_clk_update_cmd)); + + if (ctx_data->icp_dev_acquire_info->dev_type != CAM_ICP_RES_TYPE_BPS) { + if (ipe1_dev_intf) { + ipe1_dev_intf->hw_ops.process_cmd( + ipe1_dev_intf->hw_priv, id, + &clk_upd_cmd, + sizeof(struct cam_a5_clk_update_cmd)); + } + + /* update a5 clock */ + CAM_DBG(CAM_PERF, "Update ICP clk to level [%d]", + clk_upd_cmd.clk_level); + a5_dev_intf->hw_ops.process_cmd(a5_dev_intf->hw_priv, + CAM_ICP_A5_CMD_CLK_UPDATE, &clk_upd_cmd.clk_level, + sizeof(clk_upd_cmd.clk_level)); + } + + return 0; +} + +static int cam_icp_update_cpas_vote(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data) +{ + uint32_t id; + uint64_t temp; + int i = 0; + struct cam_hw_intf *ipe0_dev_intf = NULL; + struct cam_hw_intf *ipe1_dev_intf = NULL; + struct cam_hw_intf *bps_dev_intf = NULL; + struct cam_hw_intf *dev_intf = NULL; + struct cam_icp_clk_info *clk_info; + struct cam_icp_cpas_vote clk_update = {{0}, {0}, 0, 0}; + int device_share_ratio = 1; + + ipe0_dev_intf = hw_mgr->ipe0_dev_intf; + ipe1_dev_intf = hw_mgr->ipe1_dev_intf; + bps_dev_intf = hw_mgr->bps_dev_intf; + + if ((!ipe0_dev_intf) || (!bps_dev_intf)) { + CAM_ERR(CAM_ICP, "dev intfs are wrong, failed to update clk"); + return -EINVAL; + } + + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) { + dev_intf = bps_dev_intf; + clk_info = &hw_mgr->clk_info[ICP_CLK_HW_BPS]; + id = CAM_ICP_BPS_CMD_VOTE_CPAS; + } else { + dev_intf = ipe0_dev_intf; + clk_info = &hw_mgr->clk_info[ICP_CLK_HW_IPE]; + id = CAM_ICP_IPE_CMD_VOTE_CPAS; + } + + /* + * Since there are 2 devices, we assume the load is evenly shared + * between HWs and corresponding AXI paths. So divide total bw by half + * to vote on each device + */ + if ((ctx_data->icp_dev_acquire_info->dev_type != + CAM_ICP_RES_TYPE_BPS) && (ipe1_dev_intf)) + device_share_ratio = 2; + + clk_update.ahb_vote.type = CAM_VOTE_DYNAMIC; + clk_update.ahb_vote.vote.freq = 0; + clk_update.ahb_vote_valid = false; + + if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_V1) { + clk_update.axi_vote.num_paths = 1; + if (ctx_data->icp_dev_acquire_info->dev_type == + CAM_ICP_RES_TYPE_BPS) { + clk_update.axi_vote.axi_path[0].path_data_type = + CAM_BPS_DEFAULT_AXI_PATH; + clk_update.axi_vote.axi_path[0].transac_type = + CAM_BPS_DEFAULT_AXI_TRANSAC; + } else { + clk_update.axi_vote.axi_path[0].path_data_type = + CAM_IPE_DEFAULT_AXI_PATH; + clk_update.axi_vote.axi_path[0].transac_type = + CAM_IPE_DEFAULT_AXI_TRANSAC; + } + + temp = clk_info->uncompressed_bw; + do_div(temp, device_share_ratio); + clk_update.axi_vote.axi_path[0].camnoc_bw = temp; + + temp = clk_info->compressed_bw; + do_div(temp, device_share_ratio); + clk_update.axi_vote.axi_path[0].mnoc_ab_bw = temp; + clk_update.axi_vote.axi_path[0].mnoc_ib_bw = temp; + clk_update.axi_vote.axi_path[0].ddr_ab_bw = temp; + clk_update.axi_vote.axi_path[0].ddr_ib_bw = temp; + } else { + clk_update.axi_vote.num_paths = clk_info->num_paths; + memcpy(&clk_update.axi_vote.axi_path[0], + &clk_info->axi_path[0], + clk_update.axi_vote.num_paths * + sizeof(struct cam_axi_per_path_bw_vote)); + + if (device_share_ratio > 1) { + for (i = 0; i < clk_update.axi_vote.num_paths; i++) { + do_div( + clk_update.axi_vote.axi_path[i].camnoc_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].mnoc_ab_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].mnoc_ib_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].ddr_ab_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].ddr_ib_bw, + device_share_ratio); + } + } + } + + clk_update.axi_vote_valid = true; + dev_intf->hw_ops.process_cmd(dev_intf->hw_priv, id, + &clk_update, sizeof(clk_update)); + + /* + * Vote half bandwidth each on both devices. + * Total bw at mnoc - CPAS will take care of adding up. + * camnoc clk calculate is more accurate this way. + */ + if ((ctx_data->icp_dev_acquire_info->dev_type != + CAM_ICP_RES_TYPE_BPS) && (ipe1_dev_intf)) + ipe1_dev_intf->hw_ops.process_cmd(ipe1_dev_intf->hw_priv, id, + &clk_update, sizeof(clk_update)); + + return 0; +} + +static int cam_icp_mgr_ipe_bps_clk_update(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, int idx) +{ + int rc = 0; + + if (cam_icp_check_clk_update(hw_mgr, ctx_data, idx)) + rc = cam_icp_update_clk_rate(hw_mgr, ctx_data); + + if (cam_icp_check_bw_update(hw_mgr, ctx_data, idx)) + rc |= cam_icp_update_cpas_vote(hw_mgr, ctx_data); + + return rc; +} + +static int cam_icp_mgr_ipe_bps_resume(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data) +{ + struct cam_hw_intf *ipe0_dev_intf = NULL; + struct cam_hw_intf *ipe1_dev_intf = NULL; + struct cam_hw_intf *bps_dev_intf = NULL; + uint32_t core_info_mask = 0; + int rc = 0; + + ipe0_dev_intf = hw_mgr->ipe0_dev_intf; + ipe1_dev_intf = hw_mgr->ipe1_dev_intf; + bps_dev_intf = hw_mgr->bps_dev_intf; + + if ((!ipe0_dev_intf) || (!bps_dev_intf)) { + CAM_ERR(CAM_ICP, "dev intfs are wrong, failed to close"); + return -EINVAL; + } + + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) { + if (hw_mgr->bps_ctxt_cnt++) + goto end; + if (!hw_mgr->bps_clk_state) { + bps_dev_intf->hw_ops.init( + bps_dev_intf->hw_priv, NULL, 0); + hw_mgr->bps_clk_state = true; + } + if (icp_hw_mgr.ipe_bps_pc_flag) { + bps_dev_intf->hw_ops.process_cmd( + bps_dev_intf->hw_priv, + CAM_ICP_BPS_CMD_POWER_RESUME, NULL, 0); + } + core_info_mask = ICP_PWR_CLP_BPS; + } else { + if (hw_mgr->ipe_ctxt_cnt++) + goto end; + if (!hw_mgr->ipe_clk_state) + ipe0_dev_intf->hw_ops.init( + ipe0_dev_intf->hw_priv, NULL, 0); + if (icp_hw_mgr.ipe_bps_pc_flag) { + ipe0_dev_intf->hw_ops.process_cmd( + ipe0_dev_intf->hw_priv, + CAM_ICP_IPE_CMD_POWER_RESUME, NULL, 0); + } + + if ((icp_hw_mgr.ipe1_enable) && + (ipe1_dev_intf) && + (!hw_mgr->ipe_clk_state)) { + ipe1_dev_intf->hw_ops.init(ipe1_dev_intf->hw_priv, + NULL, 0); + + if (icp_hw_mgr.ipe_bps_pc_flag) { + ipe1_dev_intf->hw_ops.process_cmd( + ipe1_dev_intf->hw_priv, + CAM_ICP_IPE_CMD_POWER_RESUME, + NULL, 0); + } + } + hw_mgr->ipe_clk_state = true; + + if ((icp_hw_mgr.ipe1_enable) && + (ipe1_dev_intf)) + core_info_mask = (ICP_PWR_CLP_IPE0 | + ICP_PWR_CLP_IPE1); + else + core_info_mask = ICP_PWR_CLP_IPE0; + } + + CAM_DBG(CAM_PERF, "core_info %X", core_info_mask); + if (icp_hw_mgr.ipe_bps_pc_flag) + rc = hfi_enable_ipe_bps_pc(true, core_info_mask); + else + rc = hfi_enable_ipe_bps_pc(false, core_info_mask); +end: + return rc; +} + +static int cam_icp_mgr_ipe_bps_power_collapse(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, int dev_type) +{ + int rc = 0, dev; + struct cam_hw_intf *ipe0_dev_intf = NULL; + struct cam_hw_intf *ipe1_dev_intf = NULL; + struct cam_hw_intf *bps_dev_intf = NULL; + + ipe0_dev_intf = hw_mgr->ipe0_dev_intf; + ipe1_dev_intf = hw_mgr->ipe1_dev_intf; + bps_dev_intf = hw_mgr->bps_dev_intf; + + if ((!ipe0_dev_intf) || (!bps_dev_intf)) { + CAM_ERR(CAM_ICP, "dev intfs are wrong, failed to close"); + return -EINVAL; + } + + if (!ctx_data) + dev = dev_type; + else + dev = ctx_data->icp_dev_acquire_info->dev_type; + + if (dev == CAM_ICP_RES_TYPE_BPS) { + CAM_DBG(CAM_PERF, "bps ctx cnt %d", hw_mgr->bps_ctxt_cnt); + if (ctx_data) + --hw_mgr->bps_ctxt_cnt; + + if (hw_mgr->bps_ctxt_cnt) + goto end; + + if (icp_hw_mgr.ipe_bps_pc_flag && + !atomic_read(&hw_mgr->recovery)) { + rc = bps_dev_intf->hw_ops.process_cmd( + bps_dev_intf->hw_priv, + CAM_ICP_BPS_CMD_POWER_COLLAPSE, + NULL, 0); + } + + if (hw_mgr->bps_clk_state) { + bps_dev_intf->hw_ops.deinit + (bps_dev_intf->hw_priv, NULL, 0); + hw_mgr->bps_clk_state = false; + } + } else { + CAM_DBG(CAM_PERF, "ipe ctx cnt %d", hw_mgr->ipe_ctxt_cnt); + if (ctx_data) + --hw_mgr->ipe_ctxt_cnt; + + if (hw_mgr->ipe_ctxt_cnt) + goto end; + + if (icp_hw_mgr.ipe_bps_pc_flag && + !atomic_read(&hw_mgr->recovery)) { + rc = ipe0_dev_intf->hw_ops.process_cmd( + ipe0_dev_intf->hw_priv, + CAM_ICP_IPE_CMD_POWER_COLLAPSE, NULL, 0); + } + + if (hw_mgr->ipe_clk_state) + ipe0_dev_intf->hw_ops.deinit( + ipe0_dev_intf->hw_priv, NULL, 0); + + if (ipe1_dev_intf) { + if (icp_hw_mgr.ipe_bps_pc_flag && + !atomic_read(&hw_mgr->recovery)) { + rc = ipe1_dev_intf->hw_ops.process_cmd( + ipe1_dev_intf->hw_priv, + CAM_ICP_IPE_CMD_POWER_COLLAPSE, + NULL, 0); + } + + if (hw_mgr->ipe_clk_state) + ipe1_dev_intf->hw_ops.deinit(ipe1_dev_intf->hw_priv, + NULL, 0); + } + + hw_mgr->ipe_clk_state = false; + } + +end: + return rc; +} + +static int cam_icp_mgr_ipe_bps_get_gdsc_control( + struct cam_icp_hw_mgr *hw_mgr) +{ + int rc = 0; + struct cam_hw_intf *ipe0_dev_intf = NULL; + struct cam_hw_intf *ipe1_dev_intf = NULL; + struct cam_hw_intf *bps_dev_intf = NULL; + + ipe0_dev_intf = hw_mgr->ipe0_dev_intf; + ipe1_dev_intf = hw_mgr->ipe1_dev_intf; + bps_dev_intf = hw_mgr->bps_dev_intf; + + if ((!ipe0_dev_intf) || (!bps_dev_intf)) { + CAM_ERR(CAM_ICP, "dev intfs are wrong"); + return -EINVAL; + } + + if (icp_hw_mgr.ipe_bps_pc_flag) { + rc = bps_dev_intf->hw_ops.process_cmd( + bps_dev_intf->hw_priv, + CAM_ICP_BPS_CMD_POWER_COLLAPSE, + NULL, 0); + + rc = ipe0_dev_intf->hw_ops.process_cmd( + ipe0_dev_intf->hw_priv, + CAM_ICP_IPE_CMD_POWER_COLLAPSE, NULL, 0); + + if (ipe1_dev_intf) { + rc = ipe1_dev_intf->hw_ops.process_cmd( + ipe1_dev_intf->hw_priv, + CAM_ICP_IPE_CMD_POWER_COLLAPSE, + NULL, 0); + } + } + + return rc; +} + +static int cam_icp_set_dbg_default_clk(void *data, u64 val) +{ + icp_hw_mgr.icp_debug_clk = val; + return 0; +} + +static int cam_icp_get_dbg_default_clk(void *data, u64 *val) +{ + *val = icp_hw_mgr.icp_debug_clk; + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(cam_icp_debug_default_clk, + cam_icp_get_dbg_default_clk, + cam_icp_set_dbg_default_clk, "%16llu"); + +static int cam_icp_set_a5_dbg_lvl(void *data, u64 val) +{ + icp_hw_mgr.a5_dbg_lvl = val; + return 0; +} + +static int cam_icp_get_a5_dbg_lvl(void *data, u64 *val) +{ + *val = icp_hw_mgr.a5_dbg_lvl; + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(cam_icp_debug_fs, cam_icp_get_a5_dbg_lvl, + cam_icp_set_a5_dbg_lvl, "%08llu"); + +static int cam_icp_set_a5_dbg_type(void *data, u64 val) +{ + if (val <= NUM_HFI_DEBUG_MODE) + icp_hw_mgr.a5_debug_type = val; + return 0; +} + +static int cam_icp_get_a5_dbg_type(void *data, u64 *val) +{ + *val = icp_hw_mgr.a5_debug_type; + return 0; +} + + +DEFINE_SIMPLE_ATTRIBUTE(cam_icp_debug_type_fs, cam_icp_get_a5_dbg_type, + cam_icp_set_a5_dbg_type, "%08llu"); + +static int cam_icp_set_a5_fw_dump_lvl(void *data, u64 val) +{ + if (val < NUM_HFI_DUMP_LVL) + icp_hw_mgr.a5_fw_dump_lvl = val; + return 0; +} + +static int cam_icp_get_a5_fw_dump_lvl(void *data, u64 *val) +{ + *val = icp_hw_mgr.a5_fw_dump_lvl; + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(cam_icp_debug_fw_dump, cam_icp_get_a5_fw_dump_lvl, + cam_icp_set_a5_fw_dump_lvl, "%08llu"); + +static int cam_icp_hw_mgr_create_debugfs_entry(void) +{ + int rc = 0; + + icp_hw_mgr.dentry = debugfs_create_dir("camera_icp", NULL); + if (!icp_hw_mgr.dentry) + return -ENOMEM; + + if (!debugfs_create_bool("icp_pc", + 0644, + icp_hw_mgr.dentry, + &icp_hw_mgr.icp_pc_flag)) { + CAM_ERR(CAM_ICP, "failed to create icp_pc entry"); + rc = -ENOMEM; + goto err; + } + + if (!debugfs_create_bool("ipe_bps_pc", + 0644, + icp_hw_mgr.dentry, + &icp_hw_mgr.ipe_bps_pc_flag)) { + CAM_ERR(CAM_ICP, "failed to create ipe_bps_pc entry"); + rc = -ENOMEM; + goto err; + } + + if (!debugfs_create_file("icp_debug_clk", + 0644, + icp_hw_mgr.dentry, NULL, + &cam_icp_debug_default_clk)) { + CAM_ERR(CAM_ICP, "failed to create icp_debug_clk entry"); + rc = -ENOMEM; + goto err; + } + + if (!debugfs_create_bool("a5_jtag_debug", + 0644, + icp_hw_mgr.dentry, + &icp_hw_mgr.a5_jtag_debug)) { + rc = -ENOMEM; + goto err; + } + + if (!debugfs_create_file("a5_debug_type", + 0644, + icp_hw_mgr.dentry, + NULL, &cam_icp_debug_type_fs)) { + CAM_ERR(CAM_ICP, "failed to create a5_debug_type"); + rc = -ENOMEM; + goto err; + } + + if (!debugfs_create_file("a5_debug_lvl", + 0644, + icp_hw_mgr.dentry, + NULL, &cam_icp_debug_fs)) { + CAM_ERR(CAM_ICP, "failed to create a5_dbg_lvl"); + rc = -ENOMEM; + goto err; + } + + if (!debugfs_create_file("a5_fw_dump_lvl", + 0644, + icp_hw_mgr.dentry, + NULL, &cam_icp_debug_fw_dump)) { + CAM_ERR(CAM_ICP, "failed to create a5_fw_dump_lvl"); + rc = -ENOMEM; + goto err; + } + + /* Set default hang dump lvl */ + icp_hw_mgr.a5_fw_dump_lvl = HFI_FW_DUMP_ON_FAILURE; + return rc; +err: + debugfs_remove_recursive(icp_hw_mgr.dentry); + icp_hw_mgr.dentry = NULL; + return rc; +} + +static int cam_icp_mgr_process_cmd(void *priv, void *data) +{ + int rc; + struct hfi_cmd_work_data *task_data = NULL; + struct cam_icp_hw_mgr *hw_mgr; + + if (!data || !priv) { + CAM_ERR(CAM_ICP, "Invalid params%pK %pK", data, priv); + return -EINVAL; + } + + hw_mgr = priv; + task_data = (struct hfi_cmd_work_data *)data; + + rc = hfi_write_cmd(task_data->data); + + return rc; +} + +static int cam_icp_mgr_cleanup_ctx(struct cam_icp_hw_ctx_data *ctx_data) +{ + int i; + struct hfi_frame_process_info *hfi_frame_process; + struct cam_hw_done_event_data buf_data; + + hfi_frame_process = &ctx_data->hfi_frame_process; + for (i = 0; i < CAM_FRAME_CMD_MAX; i++) { + if (!hfi_frame_process->request_id[i]) + continue; + buf_data.request_id = hfi_frame_process->request_id[i]; + ctx_data->ctxt_event_cb(ctx_data->context_priv, + false, &buf_data); + hfi_frame_process->request_id[i] = 0; + if (ctx_data->hfi_frame_process.in_resource[i] > 0) { + CAM_DBG(CAM_ICP, "Delete merged sync in object: %d", + ctx_data->hfi_frame_process.in_resource[i]); + cam_sync_destroy( + ctx_data->hfi_frame_process.in_resource[i]); + ctx_data->hfi_frame_process.in_resource[i] = 0; + } + hfi_frame_process->fw_process_flag[i] = false; + clear_bit(i, ctx_data->hfi_frame_process.bitmap); + } + + for (i = 0; i < CAM_FRAME_CMD_MAX; i++) { + if (!hfi_frame_process->in_free_resource[i]) + continue; + + CAM_DBG(CAM_ICP, "Delete merged sync in object: %d", + ctx_data->hfi_frame_process.in_free_resource[i]); + cam_sync_destroy( + ctx_data->hfi_frame_process.in_free_resource[i]); + ctx_data->hfi_frame_process.in_free_resource[i] = 0; + } + + return 0; +} + +static const char *cam_icp_error_handle_id_to_type( + uint32_t error_handle) +{ + const char *name = NULL; + + switch (error_handle) { + case CAMERAICP_SUCCESS: + name = "SUCCESS"; + break; + case CAMERAICP_EFAILED: + name = "EFAILED"; + break; + case CAMERAICP_ENOMEMORY: + name = "ENOMEMORY"; + break; + case CAMERAICP_EBADSTATE: + name = "EBADSTATE"; + break; + case CAMERAICP_EBADPARM: + name = "EBADPARM"; + break; + case CAMERAICP_EBADITEM: + name = "EBADITEM"; + break; + case CAMERAICP_EINVALIDFORMAT: + name = "EINVALIDFORMAT"; + break; + case CAMERAICP_EUNSUPPORTED: + name = "EUNSUPPORTED"; + break; + case CAMERAICP_EOUTOFBOUND: + name = "EOUTOFBOUND"; + break; + case CAMERAICP_ETIMEDOUT: + name = "ETIMEDOUT"; + break; + case CAMERAICP_EABORTED: + name = "EABORTED"; + break; + case CAMERAICP_EHWVIOLATION: + name = "EHWVIOLATION"; + break; + case CAMERAICP_ECDMERROR: + name = "ECDMERROR"; + break; + case CAMERAICP_HFI_ERR_COMMAND_SIZE: + name = "HFI_ERR_COMMAND_SIZE"; + break; + case CAMERAICP_HFI_ERR_MESSAGE_SIZE: + name = "HFI_ERR_MESSAGE_SIZE"; + break; + case CAMERAICP_HFI_QUEUE_EMPTY: + name = "HFI_QUEUE_EMPTY"; + break; + case CAMERAICP_HFI_QUEUE_FULL: + name = "HFI_QUEUE_FULL"; + break; + default: + name = NULL; + break; + } + return name; +} + +static int cam_icp_mgr_handle_frame_process(uint32_t *msg_ptr, int flag) +{ + int i; + uint32_t idx; + uint64_t request_id; + struct cam_icp_hw_ctx_data *ctx_data = NULL; + struct hfi_msg_ipebps_async_ack *ioconfig_ack = NULL; + struct hfi_frame_process_info *hfi_frame_process; + struct cam_hw_done_event_data buf_data; + uint32_t clk_type; + + ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; + request_id = ioconfig_ack->user_data2; + ctx_data = (struct cam_icp_hw_ctx_data *) + U64_TO_PTR(ioconfig_ack->user_data1); + if (!ctx_data) { + CAM_ERR(CAM_ICP, "Invalid Context req %llu", request_id); + return -EINVAL; + } + + mutex_lock(&ctx_data->ctx_mutex); + cam_icp_ctx_timer_reset(ctx_data); + if (ctx_data->state != CAM_ICP_CTX_STATE_ACQUIRED) { + CAM_DBG(CAM_ICP, "ctx %u is in %d state", + ctx_data->ctx_id, ctx_data->state); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + + CAM_DBG(CAM_REQ, + "ctx_id : %u, request_id :%lld dev_type: %d", + ctx_data->ctx_id, request_id, + ctx_data->icp_dev_acquire_info->dev_type); + + clk_type = ICP_DEV_TYPE_TO_CLK_TYPE( + ctx_data->icp_dev_acquire_info->dev_type); + cam_icp_device_timer_reset(&icp_hw_mgr, clk_type); + + hfi_frame_process = &ctx_data->hfi_frame_process; + for (i = 0; i < CAM_FRAME_CMD_MAX; i++) + if (hfi_frame_process->request_id[i] == request_id) + break; + + if (i >= CAM_FRAME_CMD_MAX) { + CAM_ERR(CAM_ICP, "pkt not found in ctx data for req_id =%lld", + request_id); + mutex_unlock(&ctx_data->ctx_mutex); + return -EINVAL; + } + idx = i; + + if (flag == ICP_FRAME_PROCESS_FAILURE) { + if (ioconfig_ack->err_type == CAMERAICP_EABORTED) + CAM_WARN(CAM_ICP, + "ctx_id %d req %llu dev %d has been aborted[flushed]", + ctx_data->ctx_id, request_id, + ctx_data->icp_dev_acquire_info->dev_type); + else + CAM_ERR(CAM_ICP, + "Done with error: %u err_type= [%s] on ctx_id %d dev %d for req %llu", + ioconfig_ack->err_type, + cam_icp_error_handle_id_to_type( + ioconfig_ack->err_type), + ctx_data->ctx_id, + ctx_data->icp_dev_acquire_info->dev_type, + request_id); + } + + buf_data.request_id = hfi_frame_process->request_id[idx]; + ctx_data->ctxt_event_cb(ctx_data->context_priv, flag, &buf_data); + hfi_frame_process->request_id[idx] = 0; + if (ctx_data->hfi_frame_process.in_resource[idx] > 0) { + CAM_DBG(CAM_ICP, "Delete merged sync in object: %d", + ctx_data->hfi_frame_process.in_resource[idx]); + cam_sync_destroy(ctx_data->hfi_frame_process.in_resource[idx]); + ctx_data->hfi_frame_process.in_resource[idx] = 0; + } + clear_bit(idx, ctx_data->hfi_frame_process.bitmap); + hfi_frame_process->fw_process_flag[idx] = false; + mutex_unlock(&ctx_data->ctx_mutex); + + return 0; +} + +static int cam_icp_mgr_process_msg_frame_process(uint32_t *msg_ptr) +{ + struct hfi_msg_ipebps_async_ack *ioconfig_ack = NULL; + struct hfi_msg_frame_process_done *frame_done; + + if (!msg_ptr) { + CAM_ERR(CAM_ICP, "msg ptr is NULL"); + return -EINVAL; + } + + ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; + if (ioconfig_ack->err_type != CAMERAICP_SUCCESS) { + cam_icp_mgr_handle_frame_process(msg_ptr, + ICP_FRAME_PROCESS_FAILURE); + return -EIO; + } + + frame_done = + (struct hfi_msg_frame_process_done *)ioconfig_ack->msg_data; + if (!frame_done) { + cam_icp_mgr_handle_frame_process(msg_ptr, + ICP_FRAME_PROCESS_FAILURE); + return -EINVAL; + } + + if (frame_done->result) + return cam_icp_mgr_handle_frame_process(msg_ptr, + ICP_FRAME_PROCESS_FAILURE); + else + return cam_icp_mgr_handle_frame_process(msg_ptr, + ICP_FRAME_PROCESS_SUCCESS); +} + +static int cam_icp_mgr_process_msg_config_io(uint32_t *msg_ptr) +{ + struct cam_icp_hw_ctx_data *ctx_data = NULL; + struct hfi_msg_ipebps_async_ack *ioconfig_ack = NULL; + struct hfi_msg_ipe_config *ipe_config_ack = NULL; + struct hfi_msg_bps_common *bps_config_ack = NULL; + + if (!msg_ptr) { + CAM_ERR(CAM_ICP, "msg ptr is NULL"); + return -EINVAL; + } + + ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; + + if (ioconfig_ack->opcode == HFI_IPEBPS_CMD_OPCODE_IPE_CONFIG_IO) { + ipe_config_ack = + (struct hfi_msg_ipe_config *)(ioconfig_ack->msg_data); + if (ipe_config_ack->rc) { + CAM_ERR(CAM_ICP, "rc = %d failed with\n" + "err_no = [%u] err_type = [%s]", + ipe_config_ack->rc, + ioconfig_ack->err_type, + cam_icp_error_handle_id_to_type( + ioconfig_ack->err_type)); + + return -EIO; + } + ctx_data = (struct cam_icp_hw_ctx_data *) + U64_TO_PTR(ioconfig_ack->user_data1); + if (!ctx_data) { + CAM_ERR(CAM_ICP, "wrong ctx data from IPE response"); + return -EINVAL; + } + ctx_data->scratch_mem_size = ipe_config_ack->scratch_mem_size; + } else { + bps_config_ack = + (struct hfi_msg_bps_common *)(ioconfig_ack->msg_data); + if (bps_config_ack->rc) { + CAM_ERR(CAM_ICP, "rc : %u, opcode :%u", + bps_config_ack->rc, ioconfig_ack->opcode); + return -EIO; + } + ctx_data = (struct cam_icp_hw_ctx_data *) + U64_TO_PTR(ioconfig_ack->user_data1); + if (!ctx_data) { + CAM_ERR(CAM_ICP, "wrong ctx data from BPS response"); + return -EINVAL; + } + } + complete(&ctx_data->wait_complete); + + return 0; +} + +static int cam_icp_mgr_process_msg_create_handle(uint32_t *msg_ptr) +{ + struct hfi_msg_create_handle_ack *create_handle_ack = NULL; + struct cam_icp_hw_ctx_data *ctx_data = NULL; + int rc = 0; + + create_handle_ack = (struct hfi_msg_create_handle_ack *)msg_ptr; + if (!create_handle_ack) { + CAM_ERR(CAM_ICP, "Invalid create_handle_ack"); + return -EINVAL; + } + + ctx_data = + (struct cam_icp_hw_ctx_data *)(uintptr_t) + create_handle_ack->user_data1; + if (!ctx_data) { + CAM_ERR(CAM_ICP, "Invalid ctx_data"); + return -EINVAL; + } + + if (ctx_data->state == CAM_ICP_CTX_STATE_IN_USE) { + ctx_data->fw_handle = create_handle_ack->fw_handle; + CAM_DBG(CAM_ICP, "fw_handle = %x", ctx_data->fw_handle); + } else { + CAM_WARN(CAM_ICP, + "This ctx is no longer in use current state: %d", + ctx_data->state); + ctx_data->fw_handle = 0; + rc = -EPERM; + } + complete(&ctx_data->wait_complete); + return rc; +} + +static int cam_icp_mgr_process_msg_ping_ack(uint32_t *msg_ptr) +{ + struct hfi_msg_ping_ack *ping_ack = NULL; + struct cam_icp_hw_ctx_data *ctx_data = NULL; + + ping_ack = (struct hfi_msg_ping_ack *)msg_ptr; + if (!ping_ack) { + CAM_ERR(CAM_ICP, "Empty ping ack message"); + return -EINVAL; + } + + ctx_data = (struct cam_icp_hw_ctx_data *) + U64_TO_PTR(ping_ack->user_data); + if (!ctx_data) { + CAM_ERR(CAM_ICP, "Invalid ctx_data"); + return -EINVAL; + } + + if (ctx_data->state == CAM_ICP_CTX_STATE_IN_USE) + complete(&ctx_data->wait_complete); + + return 0; +} + +static int cam_icp_mgr_process_indirect_ack_msg(uint32_t *msg_ptr) +{ + int rc; + + if (!msg_ptr) { + CAM_ERR(CAM_ICP, "msg ptr is NULL"); + return -EINVAL; + } + + switch (msg_ptr[ICP_PACKET_OPCODE]) { + case HFI_IPEBPS_CMD_OPCODE_IPE_CONFIG_IO: + case HFI_IPEBPS_CMD_OPCODE_BPS_CONFIG_IO: + CAM_DBG(CAM_ICP, "received IPE/BPS_CONFIG_IO:"); + rc = cam_icp_mgr_process_msg_config_io(msg_ptr); + if (rc) + return rc; + break; + + case HFI_IPEBPS_CMD_OPCODE_IPE_FRAME_PROCESS: + case HFI_IPEBPS_CMD_OPCODE_BPS_FRAME_PROCESS: + rc = cam_icp_mgr_process_msg_frame_process(msg_ptr); + if (rc) + return rc; + break; + default: + CAM_ERR(CAM_ICP, "Invalid opcode : %u", + msg_ptr[ICP_PACKET_OPCODE]); + rc = -EINVAL; + break; + } + + return rc; +} + +static int cam_icp_mgr_process_direct_ack_msg(uint32_t *msg_ptr) +{ + struct cam_icp_hw_ctx_data *ctx_data = NULL; + struct hfi_msg_ipebps_async_ack *ioconfig_ack = NULL; + struct cam_hw_intf *a5_dev_intf = NULL; + struct cam_hw_info *a5_dev = NULL; + int rc = 0; + + a5_dev_intf = icp_hw_mgr.a5_dev_intf; + if (!a5_dev_intf) { + CAM_ERR(CAM_ICP, "a5_dev_intf is invalid"); + return -EINVAL; + } + a5_dev = (struct cam_hw_info *)a5_dev_intf->hw_priv; + switch (msg_ptr[ICP_PACKET_OPCODE]) { + case HFI_IPEBPS_CMD_OPCODE_IPE_ABORT: + case HFI_IPEBPS_CMD_OPCODE_BPS_ABORT: + ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; + ctx_data = (struct cam_icp_hw_ctx_data *) + U64_TO_PTR(ioconfig_ack->user_data1); + if (ctx_data->state != CAM_ICP_CTX_STATE_FREE) + complete(&ctx_data->wait_complete); + CAM_DBG(CAM_ICP, "received IPE/BPS/ ABORT: ctx_state =%d", + ctx_data->state); + break; + case HFI_IPEBPS_CMD_OPCODE_IPE_DESTROY: + case HFI_IPEBPS_CMD_OPCODE_BPS_DESTROY: + ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; + ctx_data = (struct cam_icp_hw_ctx_data *) + U64_TO_PTR(ioconfig_ack->user_data1); + if ((ctx_data->state == CAM_ICP_CTX_STATE_RELEASE) || + (ctx_data->state == CAM_ICP_CTX_STATE_IN_USE)) { + complete(&ctx_data->wait_complete); + } + CAM_DBG(CAM_ICP, "received IPE/BPS/ DESTROY: ctx_state =%d", + ctx_data->state); + break; + case HFI_IPEBPS_CMD_OPCODE_MEM_MAP: + ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; + ctx_data = + (struct cam_icp_hw_ctx_data *)ioconfig_ack->user_data1; + if (ctx_data->state != CAM_ICP_CTX_STATE_FREE) + complete(&ctx_data->wait_complete); + CAM_DBG(CAM_ICP, "received IPE/BPS\n" + "MAP ACK:ctx_state =%d\n" + "failed with err_no = [%u] err_type = [%s]", + ctx_data->state, + ioconfig_ack->err_type, + cam_icp_error_handle_id_to_type( + ioconfig_ack->err_type)); + break; + case HFI_IPEBPS_CMD_OPCODE_MEM_UNMAP: + ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; + ctx_data = + (struct cam_icp_hw_ctx_data *)ioconfig_ack->user_data1; + if (ctx_data->state != CAM_ICP_CTX_STATE_FREE) + complete(&ctx_data->wait_complete); + CAM_DBG(CAM_ICP, + "received IPE/BPS UNMAP ACK:ctx_state =%d\n" + "failed with err_no = [%u] err_type = [%s]", + ctx_data->state, + ioconfig_ack->err_type, + cam_icp_error_handle_id_to_type( + ioconfig_ack->err_type)); + break; + default: + CAM_ERR(CAM_ICP, "Invalid opcode : %u", + msg_ptr[ICP_PACKET_OPCODE]); + rc = -EINVAL; + break; + } + return rc; +} + +static int cam_icp_ipebps_reset(struct cam_icp_hw_mgr *hw_mgr) +{ + int rc = 0; + struct cam_hw_intf *ipe0_dev_intf; + struct cam_hw_intf *ipe1_dev_intf; + struct cam_hw_intf *bps_dev_intf; + + ipe0_dev_intf = hw_mgr->ipe0_dev_intf; + ipe1_dev_intf = hw_mgr->ipe1_dev_intf; + bps_dev_intf = hw_mgr->bps_dev_intf; + + if (hw_mgr->bps_ctxt_cnt) { + rc = bps_dev_intf->hw_ops.process_cmd( + bps_dev_intf->hw_priv, + CAM_ICP_BPS_CMD_RESET, + NULL, 0); + if (rc) + CAM_ERR(CAM_ICP, "bps reset failed"); + } + + if (hw_mgr->ipe_ctxt_cnt) { + rc = ipe0_dev_intf->hw_ops.process_cmd( + ipe0_dev_intf->hw_priv, + CAM_ICP_IPE_CMD_RESET, + NULL, 0); + if (rc) + CAM_ERR(CAM_ICP, "ipe0 reset failed"); + + if (ipe1_dev_intf) { + rc = ipe1_dev_intf->hw_ops.process_cmd( + ipe1_dev_intf->hw_priv, + CAM_ICP_IPE_CMD_RESET, + NULL, 0); + if (rc) + CAM_ERR(CAM_ICP, "ipe1 reset failed"); + } + } + + return 0; +} + +static int cam_icp_mgr_trigger_recovery(struct cam_icp_hw_mgr *hw_mgr) +{ + int rc = 0; + struct sfr_buf *sfr_buffer = NULL; + + CAM_DBG(CAM_ICP, "Enter"); + + if (atomic_read(&hw_mgr->recovery)) { + CAM_ERR(CAM_ICP, "Recovery is set"); + return rc; + } + + sfr_buffer = (struct sfr_buf *)icp_hw_mgr.hfi_mem.sfr_buf.kva; + CAM_WARN(CAM_ICP, "SFR:%s", sfr_buffer->msg); + + cam_icp_mgr_ipe_bps_get_gdsc_control(hw_mgr); + cam_icp_ipebps_reset(hw_mgr); + + atomic_set(&hw_mgr->recovery, 1); + CAM_DBG(CAM_ICP, "Done"); + return rc; +} +static int cam_icp_mgr_process_fatal_error( + struct cam_icp_hw_mgr *hw_mgr, uint32_t *msg_ptr) +{ + struct hfi_msg_event_notify *event_notify; + int rc = 0; + + CAM_DBG(CAM_ICP, "Enter"); + + event_notify = (struct hfi_msg_event_notify *)msg_ptr; + if (!event_notify) { + CAM_ERR(CAM_ICP, "Empty event message"); + return -EINVAL; + } + + CAM_DBG(CAM_ICP, "evt_id: %u evt_data1: %u evt_data2: %u", + event_notify->event_id, + event_notify->event_data1, + event_notify->event_data2); + + if (event_notify->event_id == HFI_EVENT_SYS_ERROR) { + CAM_INFO(CAM_ICP, "received HFI_EVENT_SYS_ERROR"); + if (event_notify->event_data1 == HFI_ERR_SYS_FATAL) { + CAM_ERR(CAM_ICP, "received HFI_ERR_SYS_FATAL"); + BUG(); + } + rc = cam_icp_mgr_trigger_recovery(hw_mgr); + cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); + } + + return rc; +} + +static void cam_icp_mgr_process_dbg_buf(unsigned int debug_lvl) +{ + uint32_t *msg_ptr = NULL, *pkt_ptr = NULL; + struct hfi_msg_debug *dbg_msg; + uint32_t read_len, size_processed = 0; + uint64_t timestamp = 0; + char *dbg_buf; + int rc = 0; + + rc = hfi_read_message(icp_hw_mgr.dbg_buf, Q_DBG, &read_len); + if (rc) + return; + + msg_ptr = (uint32_t *)icp_hw_mgr.dbg_buf; + while (true) { + pkt_ptr = msg_ptr; + if (pkt_ptr[ICP_PACKET_TYPE] == HFI_MSG_SYS_DEBUG) { + dbg_msg = (struct hfi_msg_debug *)pkt_ptr; + dbg_buf = (char *)&dbg_msg->msg_data; + timestamp = ((((uint64_t)(dbg_msg->timestamp_hi) << 32) + | dbg_msg->timestamp_lo) >> 16); + trace_cam_icp_fw_dbg(dbg_buf, timestamp/2); + if (!debug_lvl) + CAM_INFO(CAM_ICP, "FW_DBG:%s", dbg_buf); + } + size_processed += (pkt_ptr[ICP_PACKET_SIZE] >> + BYTE_WORD_SHIFT); + if (size_processed >= read_len) + return; + msg_ptr += (pkt_ptr[ICP_PACKET_SIZE] >> + BYTE_WORD_SHIFT); + pkt_ptr = NULL; + dbg_msg = NULL; + dbg_buf = NULL; + } +} + +static int cam_icp_process_msg_pkt_type( + struct cam_icp_hw_mgr *hw_mgr, + uint32_t *msg_ptr, + uint32_t *msg_processed_len) +{ + int rc = 0; + int size_processed = 0; + + switch (msg_ptr[ICP_PACKET_TYPE]) { + case HFI_MSG_SYS_INIT_DONE: + CAM_DBG(CAM_ICP, "received SYS_INIT_DONE"); + complete(&hw_mgr->a5_complete); + size_processed = ( + (struct hfi_msg_init_done *)msg_ptr)->size; + break; + + case HFI_MSG_SYS_PC_PREP_DONE: + CAM_DBG(CAM_ICP, "HFI_MSG_SYS_PC_PREP_DONE is received\n"); + complete(&hw_mgr->a5_complete); + size_processed = sizeof(struct hfi_msg_pc_prep_done); + break; + + case HFI_MSG_SYS_PING_ACK: + CAM_DBG(CAM_ICP, "received SYS_PING_ACK"); + rc = cam_icp_mgr_process_msg_ping_ack(msg_ptr); + size_processed = sizeof(struct hfi_msg_ping_ack); + break; + + case HFI_MSG_IPEBPS_CREATE_HANDLE_ACK: + CAM_DBG(CAM_ICP, "received IPEBPS_CREATE_HANDLE_ACK"); + rc = cam_icp_mgr_process_msg_create_handle(msg_ptr); + size_processed = sizeof(struct hfi_msg_create_handle_ack); + break; + + case HFI_MSG_IPEBPS_ASYNC_COMMAND_INDIRECT_ACK: + CAM_DBG(CAM_ICP, "received ASYNC_INDIRECT_ACK"); + rc = cam_icp_mgr_process_indirect_ack_msg(msg_ptr); + size_processed = ( + (struct hfi_msg_ipebps_async_ack *)msg_ptr)->size; + break; + + case HFI_MSG_IPEBPS_ASYNC_COMMAND_DIRECT_ACK: + CAM_DBG(CAM_ICP, "received ASYNC_DIRECT_ACK"); + rc = cam_icp_mgr_process_direct_ack_msg(msg_ptr); + size_processed = ( + (struct hfi_msg_ipebps_async_ack *)msg_ptr)->size; + break; + + case HFI_MSG_EVENT_NOTIFY: + CAM_DBG(CAM_ICP, "received EVENT_NOTIFY"); + size_processed = ( + (struct hfi_msg_event_notify *)msg_ptr)->size; + rc = cam_icp_mgr_process_fatal_error(hw_mgr, msg_ptr); + if (rc) + CAM_ERR(CAM_ICP, "failed in processing evt notify"); + + break; + + default: + CAM_ERR(CAM_ICP, "invalid msg : %u", + msg_ptr[ICP_PACKET_TYPE]); + rc = -EINVAL; + break; + } + + *msg_processed_len = size_processed; + return rc; +} + +static int32_t cam_icp_mgr_process_msg(void *priv, void *data) +{ + uint32_t read_len, msg_processed_len; + uint32_t *msg_ptr = NULL; + struct hfi_msg_work_data *task_data; + struct cam_icp_hw_mgr *hw_mgr; + int rc = 0; + + if (!data || !priv) { + CAM_ERR(CAM_ICP, "Invalid data"); + return -EINVAL; + } + + task_data = data; + hw_mgr = priv; + + rc = hfi_read_message(icp_hw_mgr.msg_buf, Q_MSG, &read_len); + if (rc) { + CAM_DBG(CAM_ICP, "Unable to read msg q rc %d", rc); + } else { + read_len = read_len << BYTE_WORD_SHIFT; + msg_ptr = (uint32_t *)icp_hw_mgr.msg_buf; + while (true) { + cam_icp_process_msg_pkt_type(hw_mgr, msg_ptr, + &msg_processed_len); + + if (!msg_processed_len) { + CAM_ERR(CAM_ICP, "Failed to read"); + rc = -EINVAL; + break; + } + + read_len -= msg_processed_len; + if (read_len > 0) { + msg_ptr += (msg_processed_len >> + BYTE_WORD_SHIFT); + msg_processed_len = 0; + } else { + break; + } + } + } + + cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); + + if ((task_data->irq_status & A5_WDT_0) || + (task_data->irq_status & A5_WDT_1)) { + CAM_ERR_RATE_LIMIT(CAM_ICP, "watch dog interrupt from A5"); + + rc = cam_icp_mgr_trigger_recovery(hw_mgr); + } + + return rc; +} + +int32_t cam_icp_hw_mgr_cb(uint32_t irq_status, void *data) +{ + int32_t rc = 0; + unsigned long flags; + struct cam_icp_hw_mgr *hw_mgr = data; + struct crm_workq_task *task; + struct hfi_msg_work_data *task_data; + + if (!data) { + CAM_ERR(CAM_ICP, "irq cb data is NULL"); + return rc; + } + + spin_lock_irqsave(&hw_mgr->hw_mgr_lock, flags); + task = cam_req_mgr_workq_get_task(icp_hw_mgr.msg_work); + if (!task) { + CAM_ERR(CAM_ICP, "no empty task"); + spin_unlock_irqrestore(&hw_mgr->hw_mgr_lock, flags); + return -ENOMEM; + } + + task_data = (struct hfi_msg_work_data *)task->payload; + task_data->data = hw_mgr; + task_data->irq_status = irq_status; + task_data->type = ICP_WORKQ_TASK_MSG_TYPE; + task->process_cb = cam_icp_mgr_process_msg; + rc = cam_req_mgr_workq_enqueue_task(task, &icp_hw_mgr, + CRM_TASK_PRIORITY_0); + spin_unlock_irqrestore(&hw_mgr->hw_mgr_lock, flags); + + return rc; +} + +static void cam_icp_free_hfi_mem(void) +{ + int rc; + + cam_smmu_dealloc_firmware(icp_hw_mgr.iommu_hdl); + rc = cam_mem_mgr_free_memory_region(&icp_hw_mgr.hfi_mem.sec_heap); + if (rc) + CAM_ERR(CAM_ICP, "failed to unreserve sec heap"); + + cam_smmu_dealloc_qdss(icp_hw_mgr.iommu_hdl); + cam_mem_mgr_release_mem(&icp_hw_mgr.hfi_mem.qtbl); + cam_mem_mgr_release_mem(&icp_hw_mgr.hfi_mem.cmd_q); + cam_mem_mgr_release_mem(&icp_hw_mgr.hfi_mem.msg_q); + cam_mem_mgr_release_mem(&icp_hw_mgr.hfi_mem.dbg_q); + cam_mem_mgr_release_mem(&icp_hw_mgr.hfi_mem.sfr_buf); +} + +static int cam_icp_alloc_secheap_mem(struct cam_mem_mgr_memory_desc *secheap) +{ + int rc; + struct cam_mem_mgr_request_desc alloc; + struct cam_mem_mgr_memory_desc out; + struct cam_smmu_region_info secheap_info; + + memset(&alloc, 0, sizeof(alloc)); + memset(&out, 0, sizeof(out)); + + rc = cam_smmu_get_region_info(icp_hw_mgr.iommu_hdl, + CAM_SMMU_REGION_SECHEAP, + &secheap_info); + if (rc) { + CAM_ERR(CAM_ICP, "Unable to get secheap memory info"); + return rc; + } + + alloc.size = secheap_info.iova_len; + alloc.align = 0; + alloc.flags = 0; + alloc.smmu_hdl = icp_hw_mgr.iommu_hdl; + rc = cam_mem_mgr_reserve_memory_region(&alloc, + CAM_SMMU_REGION_SECHEAP, + &out); + if (rc) { + CAM_ERR(CAM_ICP, "Unable to reserve secheap memory"); + return rc; + } + + *secheap = out; + CAM_DBG(CAM_ICP, "kva: %llX, iova: %x, hdl: %x, len: %lld", + out.kva, out.iova, out.mem_handle, out.len); + + return rc; +} + +static int cam_icp_alloc_sfr_mem(struct cam_mem_mgr_memory_desc *sfr) +{ + int rc; + struct cam_mem_mgr_request_desc alloc; + struct cam_mem_mgr_memory_desc out; + + memset(&alloc, 0, sizeof(alloc)); + memset(&out, 0, sizeof(out)); + alloc.size = SZ_8K; + alloc.align = 0; + alloc.flags = CAM_MEM_FLAG_HW_READ_WRITE | + CAM_MEM_FLAG_HW_SHARED_ACCESS; + + alloc.smmu_hdl = icp_hw_mgr.iommu_hdl; + rc = cam_mem_mgr_request_mem(&alloc, &out); + if (rc) + return rc; + + *sfr = out; + CAM_DBG(CAM_ICP, "kva: %llX, iova: %x, hdl: %x, len: %lld", + out.kva, out.iova, out.mem_handle, out.len); + + return rc; +} + +static int cam_icp_alloc_shared_mem(struct cam_mem_mgr_memory_desc *qtbl) +{ + int rc; + struct cam_mem_mgr_request_desc alloc; + struct cam_mem_mgr_memory_desc out; + + memset(&alloc, 0, sizeof(alloc)); + memset(&out, 0, sizeof(out)); + alloc.size = SZ_1M; + alloc.align = 0; + alloc.flags = CAM_MEM_FLAG_HW_READ_WRITE | + CAM_MEM_FLAG_HW_SHARED_ACCESS; + alloc.smmu_hdl = icp_hw_mgr.iommu_hdl; + rc = cam_mem_mgr_request_mem(&alloc, &out); + if (rc) + return rc; + + *qtbl = out; + CAM_DBG(CAM_ICP, "kva: %llX, iova: %x, hdl: %x, len: %lld", + out.kva, out.iova, out.mem_handle, out.len); + + return rc; +} + +static int cam_icp_allocate_fw_mem(void) +{ + int rc; + uintptr_t kvaddr; + size_t len; + dma_addr_t iova; + + rc = cam_smmu_alloc_firmware(icp_hw_mgr.iommu_hdl, + &iova, &kvaddr, &len); + if (rc) + return -ENOMEM; + + icp_hw_mgr.hfi_mem.fw_buf.len = len; + icp_hw_mgr.hfi_mem.fw_buf.kva = kvaddr; + icp_hw_mgr.hfi_mem.fw_buf.iova = iova; + icp_hw_mgr.hfi_mem.fw_buf.smmu_hdl = icp_hw_mgr.iommu_hdl; + + CAM_DBG(CAM_ICP, "kva: %zX, iova: %llx, len: %zu", + kvaddr, iova, len); + + return rc; +} + +static int cam_icp_allocate_qdss_mem(void) +{ + int rc; + size_t len; + dma_addr_t iova; + + rc = cam_smmu_alloc_qdss(icp_hw_mgr.iommu_hdl, + &iova, &len); + if (rc) + return rc; + + icp_hw_mgr.hfi_mem.qdss_buf.len = len; + icp_hw_mgr.hfi_mem.qdss_buf.iova = iova; + icp_hw_mgr.hfi_mem.qdss_buf.smmu_hdl = icp_hw_mgr.iommu_hdl; + + CAM_DBG(CAM_ICP, "iova: %llx, len: %zu", iova, len); + + return rc; +} + +static int cam_icp_get_io_mem_info(void) +{ + int rc; + size_t len, discard_iova_len; + dma_addr_t iova, discard_iova_start; + + rc = cam_smmu_get_io_region_info(icp_hw_mgr.iommu_hdl, + &iova, &len, &discard_iova_start, &discard_iova_len); + if (rc) + return rc; + + icp_hw_mgr.hfi_mem.io_mem.iova_len = len; + icp_hw_mgr.hfi_mem.io_mem.iova_start = iova; + icp_hw_mgr.hfi_mem.io_mem.discard_iova_start = discard_iova_start; + icp_hw_mgr.hfi_mem.io_mem.discard_iova_len = discard_iova_len; + + CAM_DBG(CAM_ICP, "iova: %llx, len: %zu discard iova %llx len %llx", + iova, len, discard_iova_start, discard_iova_len); + + return rc; +} + +static int cam_icp_allocate_hfi_mem(void) +{ + int rc; + + rc = cam_smmu_get_region_info(icp_hw_mgr.iommu_hdl, + CAM_SMMU_REGION_SHARED, + &icp_hw_mgr.hfi_mem.shmem); + if (rc) { + CAM_ERR(CAM_ICP, "Unable to get shared memory info"); + return rc; + } + + rc = cam_icp_allocate_fw_mem(); + if (rc) { + CAM_ERR(CAM_ICP, "Unable to allocate FW memory"); + return rc; + } + + rc = cam_icp_allocate_qdss_mem(); + if (rc) { + CAM_ERR(CAM_ICP, "Unable to allocate qdss memory"); + goto fw_alloc_failed; + } + + rc = cam_icp_alloc_shared_mem(&icp_hw_mgr.hfi_mem.qtbl); + if (rc) { + CAM_ERR(CAM_ICP, "Unable to allocate qtbl memory"); + goto qtbl_alloc_failed; + } + + rc = cam_icp_alloc_shared_mem(&icp_hw_mgr.hfi_mem.cmd_q); + if (rc) { + CAM_ERR(CAM_ICP, "Unable to allocate cmd q memory"); + goto cmd_q_alloc_failed; + } + + rc = cam_icp_alloc_shared_mem(&icp_hw_mgr.hfi_mem.msg_q); + if (rc) { + CAM_ERR(CAM_ICP, "Unable to allocate msg q memory"); + goto msg_q_alloc_failed; + } + + rc = cam_icp_alloc_shared_mem(&icp_hw_mgr.hfi_mem.dbg_q); + if (rc) { + CAM_ERR(CAM_ICP, "Unable to allocate dbg q memory"); + goto dbg_q_alloc_failed; + } + + rc = cam_icp_alloc_sfr_mem(&icp_hw_mgr.hfi_mem.sfr_buf); + if (rc) { + CAM_ERR(CAM_ICP, "Unable to allocate sfr buffer"); + goto sfr_buf_alloc_failed; + } + + rc = cam_icp_alloc_secheap_mem(&icp_hw_mgr.hfi_mem.sec_heap); + if (rc) { + CAM_ERR(CAM_ICP, "Unable to allocate sec heap memory"); + goto sec_heap_alloc_failed; + } + + rc = cam_icp_get_io_mem_info(); + if (rc) { + CAM_ERR(CAM_ICP, "Unable to get I/O region info"); + goto get_io_mem_failed; + } + + return rc; +get_io_mem_failed: + cam_mem_mgr_free_memory_region(&icp_hw_mgr.hfi_mem.sec_heap); +sec_heap_alloc_failed: + cam_mem_mgr_release_mem(&icp_hw_mgr.hfi_mem.sfr_buf); +sfr_buf_alloc_failed: + cam_mem_mgr_release_mem(&icp_hw_mgr.hfi_mem.dbg_q); +dbg_q_alloc_failed: + cam_mem_mgr_release_mem(&icp_hw_mgr.hfi_mem.msg_q); +msg_q_alloc_failed: + cam_mem_mgr_release_mem(&icp_hw_mgr.hfi_mem.cmd_q); +cmd_q_alloc_failed: + cam_mem_mgr_release_mem(&icp_hw_mgr.hfi_mem.qtbl); +qtbl_alloc_failed: + cam_smmu_dealloc_qdss(icp_hw_mgr.iommu_hdl); +fw_alloc_failed: + cam_smmu_dealloc_firmware(icp_hw_mgr.iommu_hdl); + return rc; +} + +static int cam_icp_mgr_get_free_ctx(struct cam_icp_hw_mgr *hw_mgr) +{ + int i = 0; + + for (i = 0; i < CAM_ICP_CTX_MAX; i++) { + mutex_lock(&hw_mgr->ctx_data[i].ctx_mutex); + if (hw_mgr->ctx_data[i].state == CAM_ICP_CTX_STATE_FREE) { + hw_mgr->ctx_data[i].state = CAM_ICP_CTX_STATE_IN_USE; + mutex_unlock(&hw_mgr->ctx_data[i].ctx_mutex); + break; + } + mutex_unlock(&hw_mgr->ctx_data[i].ctx_mutex); + } + + return i; +} + +static void cam_icp_mgr_put_ctx(struct cam_icp_hw_ctx_data *ctx_data) +{ + ctx_data->state = CAM_ICP_CTX_STATE_FREE; +} + +static int cam_icp_mgr_send_pc_prep(struct cam_icp_hw_mgr *hw_mgr) +{ + int rc; + struct cam_hw_intf *a5_dev_intf = NULL; + unsigned long rem_jiffies; + int timeout = 5000; + + a5_dev_intf = hw_mgr->a5_dev_intf; + if (!a5_dev_intf) { + CAM_ERR(CAM_ICP, "a5_dev_intf is invalid\n"); + return -EINVAL; + } + + reinit_completion(&hw_mgr->a5_complete); + CAM_DBG(CAM_ICP, "Sending HFI init command"); + rc = a5_dev_intf->hw_ops.process_cmd( + a5_dev_intf->hw_priv, CAM_ICP_A5_CMD_PC_PREP, NULL, 0); + if (rc) + return rc; + + CAM_DBG(CAM_ICP, "Wait for PC_PREP_DONE Message\n"); + rem_jiffies = wait_for_completion_timeout(&icp_hw_mgr.a5_complete, + msecs_to_jiffies((timeout))); + if (!rem_jiffies) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_ICP, "PC_PREP response timed out %d\n", rc); + } + CAM_DBG(CAM_ICP, "Done Waiting for PC_PREP Message\n"); + + return rc; +} + +static int cam_ipe_bps_deint(struct cam_icp_hw_mgr *hw_mgr) +{ + struct cam_hw_intf *ipe0_dev_intf = NULL; + struct cam_hw_intf *ipe1_dev_intf = NULL; + struct cam_hw_intf *bps_dev_intf = NULL; + + ipe0_dev_intf = hw_mgr->ipe0_dev_intf; + ipe1_dev_intf = hw_mgr->ipe1_dev_intf; + bps_dev_intf = hw_mgr->bps_dev_intf; + if ((!ipe0_dev_intf) || (!bps_dev_intf)) { + CAM_ERR(CAM_ICP, "dev intfs are wrong, failed to close"); + return 0; + } + + if (ipe1_dev_intf && hw_mgr->ipe_clk_state) { + ipe1_dev_intf->hw_ops.deinit(ipe1_dev_intf->hw_priv, + NULL, 0); + } + + if (hw_mgr->ipe_clk_state) + ipe0_dev_intf->hw_ops.deinit(ipe0_dev_intf->hw_priv, NULL, 0); + if (hw_mgr->bps_clk_state) + bps_dev_intf->hw_ops.deinit(bps_dev_intf->hw_priv, NULL, 0); + + + hw_mgr->bps_clk_state = false; + hw_mgr->ipe_clk_state = false; + + return 0; +} + +static int cam_icp_mgr_hw_close_u(void *hw_priv, void *hw_close_args) +{ + struct cam_icp_hw_mgr *hw_mgr = hw_priv; + int rc = 0; + + CAM_DBG(CAM_ICP, "UMD calls close"); + if (!hw_mgr) { + CAM_ERR(CAM_ICP, "Null hw mgr"); + return 0; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + rc = cam_icp_mgr_hw_close(hw_mgr, NULL); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + return rc; +} + +static int cam_icp_mgr_hw_close_k(void *hw_priv, void *hw_close_args) +{ + struct cam_icp_hw_mgr *hw_mgr = hw_priv; + + CAM_DBG(CAM_ICP, "KMD calls close"); + if (!hw_mgr) { + CAM_ERR(CAM_ICP, "Null hw mgr"); + return 0; + } + + return cam_icp_mgr_hw_close(hw_mgr, NULL); + +} + +static int cam_icp_mgr_icp_power_collapse(struct cam_icp_hw_mgr *hw_mgr) +{ + int rc; + struct cam_hw_intf *a5_dev_intf = NULL; + struct cam_hw_info *a5_dev = NULL; + + CAM_DBG(CAM_PERF, "ENTER"); + + a5_dev_intf = hw_mgr->a5_dev_intf; + if (!a5_dev_intf) { + CAM_ERR(CAM_ICP, "a5_dev_intf is invalid\n"); + return -EINVAL; + } + a5_dev = (struct cam_hw_info *)a5_dev_intf->hw_priv; + + if (!hw_mgr->icp_pc_flag || atomic_read(&hw_mgr->recovery)) { + cam_hfi_disable_cpu( + a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base); + rc = cam_icp_mgr_hw_close_k(hw_mgr, NULL); + } else { + CAM_DBG(CAM_PERF, "Sending PC prep ICP PC enabled"); + rc = cam_icp_mgr_send_pc_prep(hw_mgr); + cam_hfi_disable_cpu( + a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base); + } + a5_dev_intf->hw_ops.deinit(a5_dev_intf->hw_priv, NULL, 0); + CAM_DBG(CAM_PERF, "EXIT"); + + return rc; +} + +static int cam_icp_mgr_hfi_resume(struct cam_icp_hw_mgr *hw_mgr) +{ + struct cam_hw_intf *a5_dev_intf = NULL; + struct cam_hw_info *a5_dev = NULL; + struct hfi_mem_info hfi_mem; + + a5_dev_intf = hw_mgr->a5_dev_intf; + if (!a5_dev_intf) { + CAM_ERR(CAM_ICP, "a5_dev_intf is invalid\n"); + return -EINVAL; + } + a5_dev = (struct cam_hw_info *)a5_dev_intf->hw_priv; + + hfi_mem.qtbl.kva = icp_hw_mgr.hfi_mem.qtbl.kva; + hfi_mem.qtbl.iova = icp_hw_mgr.hfi_mem.qtbl.iova; + hfi_mem.qtbl.len = icp_hw_mgr.hfi_mem.qtbl.len; + CAM_DBG(CAM_ICP, "qtbl kva = %llX IOVA = %X length = %lld\n", + hfi_mem.qtbl.kva, hfi_mem.qtbl.iova, hfi_mem.qtbl.len); + + hfi_mem.cmd_q.kva = icp_hw_mgr.hfi_mem.cmd_q.kva; + hfi_mem.cmd_q.iova = icp_hw_mgr.hfi_mem.cmd_q.iova; + hfi_mem.cmd_q.len = icp_hw_mgr.hfi_mem.cmd_q.len; + CAM_DBG(CAM_ICP, "cmd_q kva = %llX IOVA = %X length = %lld\n", + hfi_mem.cmd_q.kva, hfi_mem.cmd_q.iova, hfi_mem.cmd_q.len); + + hfi_mem.msg_q.kva = icp_hw_mgr.hfi_mem.msg_q.kva; + hfi_mem.msg_q.iova = icp_hw_mgr.hfi_mem.msg_q.iova; + hfi_mem.msg_q.len = icp_hw_mgr.hfi_mem.msg_q.len; + CAM_DBG(CAM_ICP, "msg_q kva = %llX IOVA = %X length = %lld\n", + hfi_mem.msg_q.kva, hfi_mem.msg_q.iova, hfi_mem.msg_q.len); + + hfi_mem.dbg_q.kva = icp_hw_mgr.hfi_mem.dbg_q.kva; + hfi_mem.dbg_q.iova = icp_hw_mgr.hfi_mem.dbg_q.iova; + hfi_mem.dbg_q.len = icp_hw_mgr.hfi_mem.dbg_q.len; + CAM_DBG(CAM_ICP, "dbg_q kva = %llX IOVA = %X length = %lld\n", + hfi_mem.dbg_q.kva, hfi_mem.dbg_q.iova, hfi_mem.dbg_q.len); + + hfi_mem.sfr_buf.kva = icp_hw_mgr.hfi_mem.sfr_buf.kva; + hfi_mem.sfr_buf.iova = icp_hw_mgr.hfi_mem.sfr_buf.iova; + hfi_mem.sfr_buf.len = icp_hw_mgr.hfi_mem.sfr_buf.len; + CAM_DBG(CAM_ICP, "sfr kva = %llX IOVA = %X length = %lld\n", + hfi_mem.sfr_buf.kva, hfi_mem.sfr_buf.iova, + hfi_mem.sfr_buf.len); + + hfi_mem.sec_heap.kva = icp_hw_mgr.hfi_mem.sec_heap.kva; + hfi_mem.sec_heap.iova = icp_hw_mgr.hfi_mem.sec_heap.iova; + hfi_mem.sec_heap.len = icp_hw_mgr.hfi_mem.sec_heap.len; + + hfi_mem.shmem.iova = icp_hw_mgr.hfi_mem.shmem.iova_start; + hfi_mem.shmem.len = icp_hw_mgr.hfi_mem.shmem.iova_len; + + hfi_mem.qdss.iova = icp_hw_mgr.hfi_mem.qdss_buf.iova; + hfi_mem.qdss.len = icp_hw_mgr.hfi_mem.qdss_buf.len; + + if (icp_hw_mgr.hfi_mem.io_mem.discard_iova_start && + icp_hw_mgr.hfi_mem.io_mem.discard_iova_len) { + /* IO Region 1 */ + hfi_mem.io_mem.iova = icp_hw_mgr.hfi_mem.io_mem.iova_start; + hfi_mem.io_mem.len = + icp_hw_mgr.hfi_mem.io_mem.discard_iova_start - + icp_hw_mgr.hfi_mem.io_mem.iova_start; + + /* IO Region 2 */ + hfi_mem.io_mem2.iova = + icp_hw_mgr.hfi_mem.io_mem.discard_iova_start + + icp_hw_mgr.hfi_mem.io_mem.discard_iova_len; + hfi_mem.io_mem2.len = + icp_hw_mgr.hfi_mem.io_mem.iova_start + + icp_hw_mgr.hfi_mem.io_mem.iova_len - + hfi_mem.io_mem2.iova; + } else { + /* IO Region 1 */ + hfi_mem.io_mem.iova = icp_hw_mgr.hfi_mem.io_mem.iova_start; + hfi_mem.io_mem.len = icp_hw_mgr.hfi_mem.io_mem.iova_len; + + /* IO Region 2 */ + hfi_mem.io_mem2.iova = 0x0; + hfi_mem.io_mem2.len = 0x0; + } + + CAM_DBG(CAM_ICP, + "IO region1 IOVA = %X length = %lld, IO region2 IOVA = %X length = %lld", + hfi_mem.io_mem.iova, + hfi_mem.io_mem.len, + hfi_mem.io_mem2.iova, + hfi_mem.io_mem2.len); + + return cam_hfi_resume(&hfi_mem, + a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base, + hw_mgr->a5_jtag_debug); +} + +static int cam_icp_retry_wait_for_abort( + struct cam_icp_hw_ctx_data *ctx_data) +{ + int retry_cnt = 1; + unsigned long rem_jiffies; + int timeout = 1000; + + CAM_WARN(CAM_ICP, "FW timeout in abort ctx: %u retry_left: %d", + ctx_data->ctx_id, retry_cnt); + while (retry_cnt > 0) { + rem_jiffies = wait_for_completion_timeout( + &ctx_data->wait_complete, + msecs_to_jiffies((timeout))); + if (!rem_jiffies) { + retry_cnt--; + if (retry_cnt > 0) { + CAM_WARN(CAM_ICP, + "FW timeout in abort ctx: %u retry_left: %u", + ctx_data->ctx_id, retry_cnt); + continue; + } + } + + if (retry_cnt > 0) + return 0; + } + + return -ETIMEDOUT; +} + +static int cam_icp_mgr_abort_handle_wq( + void *priv, void *data) +{ + int rc; + size_t packet_size; + struct hfi_cmd_work_data *task_data = NULL; + struct cam_icp_hw_ctx_data *ctx_data; + struct hfi_cmd_ipebps_async *abort_cmd; + + if (!data || !priv) { + CAM_ERR(CAM_ICP, "Invalid params %pK %pK", data, priv); + return -EINVAL; + } + + task_data = (struct hfi_cmd_work_data *)data; + ctx_data = + (struct cam_icp_hw_ctx_data *)task_data->data; + packet_size = + sizeof(struct hfi_cmd_ipebps_async) + + sizeof(struct hfi_cmd_abort) - + sizeof(((struct hfi_cmd_ipebps_async *)0)->payload.direct); + abort_cmd = kzalloc(packet_size, GFP_KERNEL); + CAM_DBG(CAM_ICP, "abort pkt size = %d", (int) packet_size); + if (!abort_cmd) { + rc = -ENOMEM; + return rc; + } + + abort_cmd->size = packet_size; + abort_cmd->pkt_type = HFI_CMD_IPEBPS_ASYNC_COMMAND_DIRECT; + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) + abort_cmd->opcode = HFI_IPEBPS_CMD_OPCODE_BPS_ABORT; + else + abort_cmd->opcode = HFI_IPEBPS_CMD_OPCODE_IPE_ABORT; + + abort_cmd->num_fw_handles = 1; + abort_cmd->fw_handles[0] = ctx_data->fw_handle; + abort_cmd->user_data1 = PTR_TO_U64(ctx_data); + abort_cmd->user_data2 = (uint64_t)0x0; + + rc = hfi_write_cmd(abort_cmd); + if (rc) { + kfree(abort_cmd); + return rc; + } + CAM_DBG(CAM_ICP, "fw_handle = %x ctx_data = %pK ctx_id %d", + ctx_data->fw_handle, ctx_data, ctx_data->ctx_id); + + kfree(abort_cmd); + return rc; +} + +static int cam_icp_mgr_abort_handle( + struct cam_icp_hw_ctx_data *ctx_data) +{ + int rc = 0; + unsigned long rem_jiffies = 0; + size_t packet_size; + int timeout = 1000; + struct hfi_cmd_ipebps_async *abort_cmd; + + packet_size = + sizeof(struct hfi_cmd_ipebps_async) + + sizeof(struct hfi_cmd_abort) - + sizeof(((struct hfi_cmd_ipebps_async *)0)->payload.direct); + abort_cmd = kzalloc(packet_size, GFP_KERNEL); + CAM_DBG(CAM_ICP, "abort pkt size = %d", (int) packet_size); + if (!abort_cmd) { + rc = -ENOMEM; + return rc; + } + + abort_cmd->size = packet_size; + abort_cmd->pkt_type = HFI_CMD_IPEBPS_ASYNC_COMMAND_DIRECT; + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) + abort_cmd->opcode = HFI_IPEBPS_CMD_OPCODE_BPS_ABORT; + else + abort_cmd->opcode = HFI_IPEBPS_CMD_OPCODE_IPE_ABORT; + + reinit_completion(&ctx_data->wait_complete); + abort_cmd->num_fw_handles = 1; + abort_cmd->fw_handles[0] = ctx_data->fw_handle; + abort_cmd->user_data1 = PTR_TO_U64(ctx_data); + abort_cmd->user_data2 = (uint64_t)0x0; + + rc = hfi_write_cmd(abort_cmd); + if (rc) { + kfree(abort_cmd); + return rc; + } + CAM_DBG(CAM_ICP, "fw_handle = %x ctx_data = %pK", + ctx_data->fw_handle, ctx_data); + rem_jiffies = wait_for_completion_timeout(&ctx_data->wait_complete, + msecs_to_jiffies((timeout))); + if (!rem_jiffies) { + rc = cam_icp_retry_wait_for_abort(ctx_data); + if (rc) { + CAM_ERR(CAM_ICP, + "FW timeout/err in abort handle command ctx: %u", + ctx_data->ctx_id); + cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); + cam_hfi_queue_dump(); + } + } + + kfree(abort_cmd); + return rc; +} + +static int cam_icp_mgr_destroy_handle( + struct cam_icp_hw_ctx_data *ctx_data) +{ + int rc = 0; + int timeout = 1000; + unsigned long rem_jiffies; + size_t packet_size; + struct hfi_cmd_ipebps_async *destroy_cmd; + + packet_size = + sizeof(struct hfi_cmd_ipebps_async) + + sizeof(struct hfi_cmd_abort_destroy) - + sizeof(((struct hfi_cmd_ipebps_async *)0)->payload.direct); + destroy_cmd = kzalloc(packet_size, GFP_KERNEL); + if (!destroy_cmd) { + rc = -ENOMEM; + return rc; + } + + destroy_cmd->size = packet_size; + destroy_cmd->pkt_type = HFI_CMD_IPEBPS_ASYNC_COMMAND_DIRECT; + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) + destroy_cmd->opcode = HFI_IPEBPS_CMD_OPCODE_BPS_DESTROY; + else + destroy_cmd->opcode = HFI_IPEBPS_CMD_OPCODE_IPE_DESTROY; + + reinit_completion(&ctx_data->wait_complete); + destroy_cmd->num_fw_handles = 1; + destroy_cmd->fw_handles[0] = ctx_data->fw_handle; + destroy_cmd->user_data1 = PTR_TO_U64(ctx_data); + destroy_cmd->user_data2 = (uint64_t)0x0; + memcpy(destroy_cmd->payload.direct, &ctx_data->temp_payload, + sizeof(uint64_t)); + + rc = hfi_write_cmd(destroy_cmd); + if (rc) { + kfree(destroy_cmd); + return rc; + } + CAM_DBG(CAM_ICP, "fw_handle = %x ctx_data = %pK", + ctx_data->fw_handle, ctx_data); + rem_jiffies = wait_for_completion_timeout(&ctx_data->wait_complete, + msecs_to_jiffies((timeout))); + if (!rem_jiffies) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_ICP, "FW response timeout: %d for %u", + rc, ctx_data->ctx_id); + cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); + cam_hfi_queue_dump(); + } + kfree(destroy_cmd); + return rc; +} + +static int cam_icp_mgr_release_ctx(struct cam_icp_hw_mgr *hw_mgr, int ctx_id) +{ + int i = 0; + + if (ctx_id >= CAM_ICP_CTX_MAX) { + CAM_ERR(CAM_ICP, "ctx_id is wrong: %d", ctx_id); + return -EINVAL; + } + + mutex_lock(&hw_mgr->ctx_data[ctx_id].ctx_mutex); + if (hw_mgr->ctx_data[ctx_id].state != + CAM_ICP_CTX_STATE_ACQUIRED) { + mutex_unlock(&hw_mgr->ctx_data[ctx_id].ctx_mutex); + CAM_DBG(CAM_ICP, + "ctx with id: %d not in right state to release: %d", + ctx_id, hw_mgr->ctx_data[ctx_id].state); + return 0; + } + cam_icp_mgr_ipe_bps_power_collapse(hw_mgr, + &hw_mgr->ctx_data[ctx_id], 0); + hw_mgr->ctx_data[ctx_id].state = CAM_ICP_CTX_STATE_RELEASE; + CAM_DBG(CAM_ICP, "E: ctx_id = %d recovery = %d", + ctx_id, atomic_read(&hw_mgr->recovery)); + cam_icp_mgr_abort_handle(&hw_mgr->ctx_data[ctx_id]); + cam_icp_mgr_destroy_handle(&hw_mgr->ctx_data[ctx_id]); + cam_icp_mgr_cleanup_ctx(&hw_mgr->ctx_data[ctx_id]); + + hw_mgr->ctx_data[ctx_id].fw_handle = 0; + hw_mgr->ctx_data[ctx_id].scratch_mem_size = 0; + hw_mgr->ctx_data[ctx_id].last_flush_req = 0; + for (i = 0; i < CAM_FRAME_CMD_MAX; i++) + clear_bit(i, hw_mgr->ctx_data[ctx_id].hfi_frame_process.bitmap); + kfree(hw_mgr->ctx_data[ctx_id].hfi_frame_process.bitmap); + hw_mgr->ctx_data[ctx_id].hfi_frame_process.bitmap = NULL; + cam_icp_hw_mgr_clk_info_update(hw_mgr, &hw_mgr->ctx_data[ctx_id]); + hw_mgr->ctx_data[ctx_id].clk_info.curr_fc = 0; + hw_mgr->ctx_data[ctx_id].clk_info.base_clk = 0; + hw_mgr->ctxt_cnt--; + kfree(hw_mgr->ctx_data[ctx_id].icp_dev_acquire_info); + hw_mgr->ctx_data[ctx_id].icp_dev_acquire_info = NULL; + hw_mgr->ctx_data[ctx_id].state = CAM_ICP_CTX_STATE_FREE; + cam_icp_ctx_timer_stop(&hw_mgr->ctx_data[ctx_id]); + mutex_unlock(&hw_mgr->ctx_data[ctx_id].ctx_mutex); + + CAM_DBG(CAM_ICP, "X: ctx_id = %d", ctx_id); + return 0; +} + +static void cam_icp_mgr_device_deinit(struct cam_icp_hw_mgr *hw_mgr) +{ + struct cam_hw_intf *a5_dev_intf = NULL; + struct cam_hw_intf *ipe0_dev_intf = NULL; + struct cam_hw_intf *ipe1_dev_intf = NULL; + struct cam_hw_intf *bps_dev_intf = NULL; + + a5_dev_intf = hw_mgr->a5_dev_intf; + ipe0_dev_intf = hw_mgr->ipe0_dev_intf; + ipe1_dev_intf = hw_mgr->ipe1_dev_intf; + bps_dev_intf = hw_mgr->bps_dev_intf; + + if ((!a5_dev_intf) || (!ipe0_dev_intf) || (!bps_dev_intf)) { + CAM_ERR(CAM_ICP, "dev intfs are wrong, failed to close"); + return; + } + + if (ipe1_dev_intf) + ipe1_dev_intf->hw_ops.deinit(ipe1_dev_intf->hw_priv, NULL, 0); + ipe0_dev_intf->hw_ops.deinit(ipe0_dev_intf->hw_priv, NULL, 0); + bps_dev_intf->hw_ops.deinit(bps_dev_intf->hw_priv, NULL, 0); + a5_dev_intf->hw_ops.deinit(a5_dev_intf->hw_priv, NULL, 0); + hw_mgr->bps_clk_state = false; + hw_mgr->ipe_clk_state = false; +} + +static int cam_icp_mgr_hw_close(void *hw_priv, void *hw_close_args) +{ + struct cam_icp_hw_mgr *hw_mgr = hw_priv; + struct cam_hw_intf *a5_dev_intf = NULL; + struct cam_hw_info *a5_dev = NULL; + struct cam_icp_a5_set_irq_cb irq_cb; + struct cam_icp_a5_set_fw_buf_info fw_buf_info; + int rc = 0; + + CAM_DBG(CAM_ICP, "E"); + if (hw_mgr->fw_download == false) { + CAM_DBG(CAM_ICP, "hw mgr is already closed"); + return 0; + } + a5_dev_intf = hw_mgr->a5_dev_intf; + if (!a5_dev_intf) { + CAM_DBG(CAM_ICP, "a5_dev_intf is NULL"); + return -EINVAL; + } + a5_dev = (struct cam_hw_info *)a5_dev_intf->hw_priv; + fw_buf_info.kva = 0; + fw_buf_info.iova = 0; + fw_buf_info.len = 0; + rc = a5_dev_intf->hw_ops.process_cmd( + a5_dev_intf->hw_priv, + CAM_ICP_A5_CMD_SET_FW_BUF, + &fw_buf_info, + sizeof(fw_buf_info)); + if (rc) + CAM_ERR(CAM_ICP, "nullify the fw buf failed"); + cam_hfi_deinit( + a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base); + irq_cb.icp_hw_mgr_cb = NULL; + irq_cb.data = NULL; + rc = a5_dev_intf->hw_ops.process_cmd( + a5_dev_intf->hw_priv, + CAM_ICP_A5_SET_IRQ_CB, + &irq_cb, sizeof(irq_cb)); + if (rc) + CAM_ERR(CAM_ICP, "deregister irq call back failed"); + + cam_icp_free_hfi_mem(); + hw_mgr->fw_download = false; + + CAM_DBG(CAM_ICP, "Exit"); + return rc; +} + +static int cam_icp_mgr_device_init(struct cam_icp_hw_mgr *hw_mgr) +{ + int rc = 0; + struct cam_hw_intf *a5_dev_intf = NULL; + struct cam_hw_intf *ipe0_dev_intf = NULL; + struct cam_hw_intf *ipe1_dev_intf = NULL; + struct cam_hw_intf *bps_dev_intf = NULL; + + a5_dev_intf = hw_mgr->a5_dev_intf; + ipe0_dev_intf = hw_mgr->ipe0_dev_intf; + ipe1_dev_intf = hw_mgr->ipe1_dev_intf; + bps_dev_intf = hw_mgr->bps_dev_intf; + + if ((!a5_dev_intf) || (!ipe0_dev_intf) || (!bps_dev_intf)) { + CAM_ERR(CAM_ICP, "dev intfs are wrong"); + return -EINVAL; + } + + rc = a5_dev_intf->hw_ops.init(a5_dev_intf->hw_priv, NULL, 0); + if (rc) + goto a5_dev_init_failed; + + rc = bps_dev_intf->hw_ops.init(bps_dev_intf->hw_priv, NULL, 0); + if (rc) + goto bps_dev_init_failed; + + rc = ipe0_dev_intf->hw_ops.init(ipe0_dev_intf->hw_priv, NULL, 0); + if (rc) + goto ipe0_dev_init_failed; + + if (ipe1_dev_intf) { + rc = ipe1_dev_intf->hw_ops.init(ipe1_dev_intf->hw_priv, + NULL, 0); + if (rc) + goto ipe1_dev_init_failed; + } + + hw_mgr->bps_clk_state = true; + hw_mgr->ipe_clk_state = true; + + return rc; +ipe1_dev_init_failed: + ipe0_dev_intf->hw_ops.deinit(ipe0_dev_intf->hw_priv, NULL, 0); + hw_mgr->ipe_clk_state = false; +ipe0_dev_init_failed: + bps_dev_intf->hw_ops.deinit(bps_dev_intf->hw_priv, NULL, 0); + hw_mgr->bps_clk_state = false; +bps_dev_init_failed: + a5_dev_intf->hw_ops.deinit(a5_dev_intf->hw_priv, NULL, 0); +a5_dev_init_failed: + return rc; +} + +static int cam_icp_mgr_fw_download(struct cam_icp_hw_mgr *hw_mgr) +{ + int rc; + struct cam_hw_intf *a5_dev_intf = NULL; + struct cam_hw_info *a5_dev = NULL; + struct cam_icp_a5_set_irq_cb irq_cb; + struct cam_icp_a5_set_fw_buf_info fw_buf_info; + + a5_dev_intf = hw_mgr->a5_dev_intf; + if (!a5_dev_intf) { + CAM_ERR(CAM_ICP, "a5_dev_intf is invalid"); + return -EINVAL; + } + a5_dev = (struct cam_hw_info *)a5_dev_intf->hw_priv; + + irq_cb.icp_hw_mgr_cb = cam_icp_hw_mgr_cb; + irq_cb.data = hw_mgr; + rc = a5_dev_intf->hw_ops.process_cmd( + a5_dev_intf->hw_priv, + CAM_ICP_A5_SET_IRQ_CB, + &irq_cb, sizeof(irq_cb)); + if (rc) + goto set_irq_failed; + + fw_buf_info.kva = icp_hw_mgr.hfi_mem.fw_buf.kva; + fw_buf_info.iova = icp_hw_mgr.hfi_mem.fw_buf.iova; + fw_buf_info.len = icp_hw_mgr.hfi_mem.fw_buf.len; + + rc = a5_dev_intf->hw_ops.process_cmd( + a5_dev_intf->hw_priv, + CAM_ICP_A5_CMD_SET_FW_BUF, + &fw_buf_info, sizeof(fw_buf_info)); + if (rc) + goto set_irq_failed; + + cam_hfi_enable_cpu(a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base); + + rc = a5_dev_intf->hw_ops.process_cmd( + a5_dev_intf->hw_priv, + CAM_ICP_A5_CMD_FW_DOWNLOAD, + NULL, 0); + if (rc) + goto fw_download_failed; + + return rc; +fw_download_failed: + cam_hfi_disable_cpu(a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base); +set_irq_failed: + return rc; +} + +static int cam_icp_mgr_hfi_init(struct cam_icp_hw_mgr *hw_mgr) +{ + struct cam_hw_intf *a5_dev_intf = NULL; + struct cam_hw_info *a5_dev = NULL; + struct hfi_mem_info hfi_mem; + + a5_dev_intf = hw_mgr->a5_dev_intf; + if (!a5_dev_intf) { + CAM_ERR(CAM_ICP, "a5_dev_intf is invalid"); + return -EINVAL; + } + a5_dev = (struct cam_hw_info *)a5_dev_intf->hw_priv; + + hfi_mem.qtbl.kva = icp_hw_mgr.hfi_mem.qtbl.kva; + hfi_mem.qtbl.iova = icp_hw_mgr.hfi_mem.qtbl.iova; + hfi_mem.qtbl.len = icp_hw_mgr.hfi_mem.qtbl.len; + + hfi_mem.cmd_q.kva = icp_hw_mgr.hfi_mem.cmd_q.kva; + hfi_mem.cmd_q.iova = icp_hw_mgr.hfi_mem.cmd_q.iova; + hfi_mem.cmd_q.len = icp_hw_mgr.hfi_mem.cmd_q.len; + + hfi_mem.msg_q.kva = icp_hw_mgr.hfi_mem.msg_q.kva; + hfi_mem.msg_q.iova = icp_hw_mgr.hfi_mem.msg_q.iova; + hfi_mem.msg_q.len = icp_hw_mgr.hfi_mem.msg_q.len; + + hfi_mem.dbg_q.kva = icp_hw_mgr.hfi_mem.dbg_q.kva; + hfi_mem.dbg_q.iova = icp_hw_mgr.hfi_mem.dbg_q.iova; + hfi_mem.dbg_q.len = icp_hw_mgr.hfi_mem.dbg_q.len; + + hfi_mem.sfr_buf.kva = icp_hw_mgr.hfi_mem.sfr_buf.kva; + hfi_mem.sfr_buf.iova = icp_hw_mgr.hfi_mem.sfr_buf.iova; + hfi_mem.sfr_buf.len = icp_hw_mgr.hfi_mem.sfr_buf.len; + + hfi_mem.sec_heap.kva = icp_hw_mgr.hfi_mem.sec_heap.kva; + hfi_mem.sec_heap.iova = icp_hw_mgr.hfi_mem.sec_heap.iova; + hfi_mem.sec_heap.len = icp_hw_mgr.hfi_mem.sec_heap.len; + + hfi_mem.shmem.iova = icp_hw_mgr.hfi_mem.shmem.iova_start; + hfi_mem.shmem.len = icp_hw_mgr.hfi_mem.shmem.iova_len; + + hfi_mem.qdss.iova = icp_hw_mgr.hfi_mem.qdss_buf.iova; + hfi_mem.qdss.len = icp_hw_mgr.hfi_mem.qdss_buf.len; + + if (icp_hw_mgr.hfi_mem.io_mem.discard_iova_start && + icp_hw_mgr.hfi_mem.io_mem.discard_iova_len) { + /* IO Region 1 */ + hfi_mem.io_mem.iova = icp_hw_mgr.hfi_mem.io_mem.iova_start; + hfi_mem.io_mem.len = + icp_hw_mgr.hfi_mem.io_mem.discard_iova_start - + icp_hw_mgr.hfi_mem.io_mem.iova_start; + + /* IO Region 2 */ + hfi_mem.io_mem2.iova = + icp_hw_mgr.hfi_mem.io_mem.discard_iova_start + + icp_hw_mgr.hfi_mem.io_mem.discard_iova_len; + hfi_mem.io_mem2.len = + icp_hw_mgr.hfi_mem.io_mem.iova_start + + icp_hw_mgr.hfi_mem.io_mem.iova_len - + hfi_mem.io_mem2.iova; + } else { + /* IO Region 1 */ + hfi_mem.io_mem.iova = icp_hw_mgr.hfi_mem.io_mem.iova_start; + hfi_mem.io_mem.len = icp_hw_mgr.hfi_mem.io_mem.iova_len; + + /* IO Region 2 */ + hfi_mem.io_mem2.iova = 0x0; + hfi_mem.io_mem2.len = 0x0; + } + + return cam_hfi_init(0, &hfi_mem, + a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base, + hw_mgr->a5_jtag_debug); +} + +static int cam_icp_mgr_send_fw_init(struct cam_icp_hw_mgr *hw_mgr) +{ + int rc; + struct cam_hw_intf *a5_dev_intf = NULL; + unsigned long rem_jiffies; + int timeout = 5000; + + a5_dev_intf = hw_mgr->a5_dev_intf; + if (!a5_dev_intf) { + CAM_ERR(CAM_ICP, "a5_dev_intf is invalid"); + return -EINVAL; + } + + reinit_completion(&hw_mgr->a5_complete); + CAM_DBG(CAM_ICP, "Sending HFI init command"); + rc = a5_dev_intf->hw_ops.process_cmd( + a5_dev_intf->hw_priv, + CAM_ICP_A5_SEND_INIT, + NULL, 0); + if (rc) + return rc; + + rem_jiffies = wait_for_completion_timeout(&icp_hw_mgr.a5_complete, + msecs_to_jiffies((timeout))); + if (!rem_jiffies) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_ICP, "FW response timed out %d", rc); + cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); + cam_hfi_queue_dump(); + } + CAM_DBG(CAM_ICP, "Done Waiting for INIT DONE Message"); + + return rc; +} + +static int cam_icp_mgr_hw_open_u(void *hw_mgr_priv, void *download_fw_args) +{ + struct cam_icp_hw_mgr *hw_mgr = hw_mgr_priv; + int rc = 0; + + if (!hw_mgr) { + CAM_ERR(CAM_ICP, "Null hw mgr"); + return 0; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + rc = cam_icp_mgr_hw_open(hw_mgr, download_fw_args); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + return rc; +} + +static int cam_icp_mgr_hw_open_k(void *hw_mgr_priv, void *download_fw_args) +{ + struct cam_icp_hw_mgr *hw_mgr = hw_mgr_priv; + + if (!hw_mgr) { + CAM_ERR(CAM_ICP, "Null hw mgr"); + return 0; + } + + return cam_icp_mgr_hw_open(hw_mgr, download_fw_args); +} + +static int cam_icp_mgr_icp_resume(struct cam_icp_hw_mgr *hw_mgr) +{ + int rc = 0; + struct cam_hw_intf *a5_dev_intf = NULL; + bool downloadFromResume = true; + + CAM_DBG(CAM_ICP, "Enter"); + a5_dev_intf = hw_mgr->devices[CAM_ICP_DEV_A5][0]; + + if (!a5_dev_intf) { + CAM_ERR(CAM_ICP, "a5 dev intf is wrong"); + return -EINVAL; + } + + if (hw_mgr->fw_download == false) { + CAM_DBG(CAM_ICP, "Downloading FW"); + rc = cam_icp_mgr_hw_open_k(hw_mgr, &downloadFromResume); + CAM_DBG(CAM_ICP, "FW Download Done Exit"); + return rc; + } + + rc = a5_dev_intf->hw_ops.init(a5_dev_intf->hw_priv, NULL, 0); + if (rc) + return -EINVAL; + + rc = cam_icp_mgr_hfi_resume(hw_mgr); + if (rc) + goto hfi_resume_failed; + + CAM_DBG(CAM_ICP, "Exit"); + return rc; +hfi_resume_failed: + cam_icp_mgr_icp_power_collapse(hw_mgr); + return rc; +} + +static int cam_icp_mgr_hw_open(void *hw_mgr_priv, void *download_fw_args) +{ + struct cam_hw_intf *a5_dev_intf = NULL; + struct cam_hw_info *a5_dev = NULL; + struct cam_icp_hw_mgr *hw_mgr = hw_mgr_priv; + bool icp_pc = false; + int rc = 0; + + if (!hw_mgr) { + CAM_ERR(CAM_ICP, "hw_mgr is NULL"); + return -EINVAL; + } + + if (hw_mgr->fw_download) { + CAM_DBG(CAM_ICP, "FW already downloaded"); + return rc; + } + + a5_dev_intf = hw_mgr->a5_dev_intf; + if (!a5_dev_intf) { + CAM_ERR(CAM_ICP, "a5_dev_intf is invalid"); + return -EINVAL; + } + a5_dev = (struct cam_hw_info *)a5_dev_intf->hw_priv; + rc = cam_icp_allocate_hfi_mem(); + if (rc) + goto alloc_hfi_mem_failed; + + rc = cam_icp_mgr_device_init(hw_mgr); + if (rc) + goto dev_init_fail; + + rc = cam_icp_mgr_fw_download(hw_mgr); + if (rc) + goto fw_download_failed; + + rc = cam_icp_mgr_hfi_init(hw_mgr); + if (rc) + goto hfi_init_failed; + + rc = cam_icp_mgr_send_fw_init(hw_mgr); + if (rc) + goto fw_init_failed; + + hw_mgr->ctxt_cnt = 0; + hw_mgr->fw_download = true; + atomic_set(&hw_mgr->recovery, 0); + + CAM_INFO(CAM_ICP, "FW download done successfully"); + + rc = cam_ipe_bps_deint(hw_mgr); + if (download_fw_args) + icp_pc = *((bool *)download_fw_args); + + if (download_fw_args && icp_pc == true && hw_mgr->icp_pc_flag) { + rc = cam_ipe_bps_deint(hw_mgr); + CAM_DBG(CAM_ICP, "deinit all clocks"); + } + + if (download_fw_args && icp_pc == true) + return rc; + + rc = cam_ipe_bps_deint(hw_mgr); + rc = cam_icp_mgr_icp_power_collapse(hw_mgr); + CAM_DBG(CAM_ICP, "deinit all clocks at boot up"); + + return rc; + +fw_init_failed: + cam_hfi_deinit( + a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base); +hfi_init_failed: + cam_hfi_disable_cpu( + a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base); +fw_download_failed: + cam_icp_mgr_device_deinit(hw_mgr); +dev_init_fail: + cam_icp_free_hfi_mem(); +alloc_hfi_mem_failed: + return rc; +} + +static int cam_icp_mgr_handle_config_err( + struct cam_hw_config_args *config_args, + struct cam_icp_hw_ctx_data *ctx_data, + int idx) +{ + struct cam_hw_done_event_data buf_data; + + buf_data.request_id = *(uint64_t *)config_args->priv; + ctx_data->ctxt_event_cb(ctx_data->context_priv, false, &buf_data); + + ctx_data->hfi_frame_process.request_id[idx] = 0; + ctx_data->hfi_frame_process.fw_process_flag[idx] = false; + clear_bit(idx, ctx_data->hfi_frame_process.bitmap); + + return 0; +} + +static int cam_icp_mgr_enqueue_config(struct cam_icp_hw_mgr *hw_mgr, + struct cam_hw_config_args *config_args) +{ + int rc = 0; + uint64_t request_id = 0; + struct crm_workq_task *task; + struct hfi_cmd_work_data *task_data; + struct hfi_cmd_ipebps_async *hfi_cmd; + struct cam_hw_update_entry *hw_update_entries; + struct icp_frame_info *frame_info = NULL; + + frame_info = (struct icp_frame_info *)config_args->priv; + request_id = frame_info->request_id; + hw_update_entries = config_args->hw_update_entries; + CAM_DBG(CAM_ICP, "req_id = %lld %pK", request_id, config_args->priv); + + task = cam_req_mgr_workq_get_task(icp_hw_mgr.cmd_work); + if (!task) { + CAM_ERR(CAM_ICP, "no empty task"); + return -ENOMEM; + } + + task_data = (struct hfi_cmd_work_data *)task->payload; + task_data->data = (void *)hw_update_entries->addr; + hfi_cmd = (struct hfi_cmd_ipebps_async *)hw_update_entries->addr; + task_data->request_id = request_id; + task_data->type = ICP_WORKQ_TASK_CMD_TYPE; + task->process_cb = cam_icp_mgr_process_cmd; + rc = cam_req_mgr_workq_enqueue_task(task, &icp_hw_mgr, + CRM_TASK_PRIORITY_0); + + return rc; +} + +static int cam_icp_mgr_send_config_io(struct cam_icp_hw_ctx_data *ctx_data, + uint32_t io_buf_addr) +{ + int rc = 0; + struct hfi_cmd_work_data *task_data; + struct hfi_cmd_ipebps_async ioconfig_cmd; + unsigned long rem_jiffies; + int timeout = 5000; + struct crm_workq_task *task; + uint32_t size_in_words; + + task = cam_req_mgr_workq_get_task(icp_hw_mgr.cmd_work); + if (!task) + return -ENOMEM; + + ioconfig_cmd.size = sizeof(struct hfi_cmd_ipebps_async); + ioconfig_cmd.pkt_type = HFI_CMD_IPEBPS_ASYNC_COMMAND_INDIRECT; + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) + ioconfig_cmd.opcode = HFI_IPEBPS_CMD_OPCODE_BPS_CONFIG_IO; + else + ioconfig_cmd.opcode = HFI_IPEBPS_CMD_OPCODE_IPE_CONFIG_IO; + + reinit_completion(&ctx_data->wait_complete); + + ioconfig_cmd.num_fw_handles = 1; + ioconfig_cmd.fw_handles[0] = ctx_data->fw_handle; + ioconfig_cmd.payload.indirect = io_buf_addr; + ioconfig_cmd.user_data1 = PTR_TO_U64(ctx_data); + ioconfig_cmd.user_data2 = (uint64_t)0x0; + task_data = (struct hfi_cmd_work_data *)task->payload; + task_data->data = (void *)&ioconfig_cmd; + task_data->request_id = 0; + task_data->type = ICP_WORKQ_TASK_MSG_TYPE; + task->process_cb = cam_icp_mgr_process_cmd; + size_in_words = (*(uint32_t *)task_data->data) >> 2; + CAM_DBG(CAM_ICP, "size_in_words %u", size_in_words); + rc = cam_req_mgr_workq_enqueue_task(task, &icp_hw_mgr, + CRM_TASK_PRIORITY_0); + if (rc) + return rc; + + rem_jiffies = wait_for_completion_timeout(&ctx_data->wait_complete, + msecs_to_jiffies((timeout))); + if (!rem_jiffies) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_ICP, "FW response timed out %d", rc); + cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); + cam_hfi_queue_dump(); + } + + return rc; +} + +static int cam_icp_mgr_send_recfg_io(struct cam_icp_hw_ctx_data *ctx_data, + struct hfi_cmd_ipebps_async *ioconfig_cmd, uint64_t req_id) +{ + int rc = 0; + struct hfi_cmd_work_data *task_data; + struct crm_workq_task *task; + + task = cam_req_mgr_workq_get_task(icp_hw_mgr.cmd_work); + if (!task) + return -ENOMEM; + + task_data = (struct hfi_cmd_work_data *)task->payload; + task_data->data = (void *)ioconfig_cmd; + task_data->request_id = req_id; + task_data->type = ICP_WORKQ_TASK_CMD_TYPE; + task->process_cb = cam_icp_mgr_process_cmd; + rc = cam_req_mgr_workq_enqueue_task(task, &icp_hw_mgr, + CRM_TASK_PRIORITY_0); + if (rc) + return rc; + + return rc; +} + +static int cam_icp_mgr_config_hw(void *hw_mgr_priv, void *config_hw_args) +{ + int rc = 0; + int idx; + uint64_t req_id; + struct cam_icp_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_config_args *config_args = config_hw_args; + struct cam_icp_hw_ctx_data *ctx_data = NULL; + struct icp_frame_info *frame_info = NULL; + + if (!hw_mgr || !config_args) { + CAM_ERR(CAM_ICP, "Invalid arguments %pK %pK", + hw_mgr, config_args); + return -EINVAL; + } + + if (!config_args->num_hw_update_entries) { + CAM_ERR(CAM_ICP, "No hw update enteries are available"); + return -EINVAL; + } + + ctx_data = config_args->ctxt_to_hw_map; + mutex_lock(&hw_mgr->hw_mgr_mutex); + mutex_lock(&ctx_data->ctx_mutex); + if (ctx_data->state != CAM_ICP_CTX_STATE_ACQUIRED) { + mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + CAM_ERR(CAM_ICP, "ctx id :%u is not in use", + ctx_data->ctx_id); + return -EINVAL; + } + + frame_info = (struct icp_frame_info *)config_args->priv; + req_id = frame_info->request_id; + idx = cam_icp_clk_idx_from_req_id(ctx_data, req_id); + + cam_icp_mgr_ipe_bps_clk_update(hw_mgr, ctx_data, idx); + ctx_data->hfi_frame_process.fw_process_flag[idx] = true; + ctx_data->hfi_frame_process.submit_timestamp[idx] = ktime_get(); + + CAM_DBG(CAM_ICP, "req_id %llu, io config %llu", req_id, + frame_info->io_config); + + if (frame_info->io_config != 0) { + CAM_INFO(CAM_ICP, "Send recfg io"); + rc = cam_icp_mgr_send_recfg_io(ctx_data, + &frame_info->hfi_cfg_io_cmd, req_id); + if (rc) + CAM_ERR(CAM_ICP, "Fail to send reconfig io cmd"); + } + + if (req_id <= ctx_data->last_flush_req) + CAM_WARN(CAM_ICP, + "Anomaly submitting flushed req %llu [last_flush %llu] in ctx %u", + req_id, ctx_data->last_flush_req, ctx_data->ctx_id); + + rc = cam_icp_mgr_enqueue_config(hw_mgr, config_args); + if (rc) + goto config_err; + CAM_DBG(CAM_REQ, + "req_id = %lld on ctx_id %u for dev %d queued to FW", + req_id, ctx_data->ctx_id, + ctx_data->icp_dev_acquire_info->dev_type); + mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + return 0; +config_err: + cam_icp_mgr_handle_config_err(config_args, ctx_data, idx); + mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static int cam_icp_mgr_prepare_frame_process_cmd( + struct cam_icp_hw_ctx_data *ctx_data, + struct hfi_cmd_ipebps_async *hfi_cmd, + uint64_t request_id, + uint32_t fw_cmd_buf_iova_addr) +{ + hfi_cmd->size = sizeof(struct hfi_cmd_ipebps_async); + hfi_cmd->pkt_type = HFI_CMD_IPEBPS_ASYNC_COMMAND_INDIRECT; + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) + hfi_cmd->opcode = HFI_IPEBPS_CMD_OPCODE_BPS_FRAME_PROCESS; + else + hfi_cmd->opcode = HFI_IPEBPS_CMD_OPCODE_IPE_FRAME_PROCESS; + hfi_cmd->num_fw_handles = 1; + hfi_cmd->fw_handles[0] = ctx_data->fw_handle; + hfi_cmd->payload.indirect = fw_cmd_buf_iova_addr; + hfi_cmd->user_data1 = PTR_TO_U64(ctx_data); + hfi_cmd->user_data2 = request_id; + + CAM_DBG(CAM_ICP, "ctx_data : %pK, request_id :%lld cmd_buf %x", + (void *)ctx_data->context_priv, request_id, + fw_cmd_buf_iova_addr); + + return 0; +} + +static bool cam_icp_mgr_is_valid_inconfig(struct cam_packet *packet) +{ + int i, num_in_map_entries = 0; + bool in_config_valid = false; + struct cam_buf_io_cfg *io_cfg_ptr = NULL; + + io_cfg_ptr = (struct cam_buf_io_cfg *) ((uint32_t *) &packet->payload + + packet->io_configs_offset/4); + + for (i = 0 ; i < packet->num_io_configs; i++) + if (io_cfg_ptr[i].direction == CAM_BUF_INPUT) + num_in_map_entries++; + + if (num_in_map_entries <= CAM_MAX_IN_RES) { + in_config_valid = true; + } else { + CAM_ERR(CAM_ICP, "In config entries(%u) more than allowed(%u)", + num_in_map_entries, CAM_MAX_IN_RES); + } + + CAM_DBG(CAM_ICP, "number of in_config info: %u %u %u %u", + packet->num_io_configs, IPE_IO_IMAGES_MAX, + num_in_map_entries, CAM_MAX_IN_RES); + + return in_config_valid; +} + +static bool cam_icp_mgr_is_valid_outconfig(struct cam_packet *packet) +{ + int i, num_out_map_entries = 0; + bool out_config_valid = false; + struct cam_buf_io_cfg *io_cfg_ptr = NULL; + + io_cfg_ptr = (struct cam_buf_io_cfg *) ((uint32_t *) &packet->payload + + packet->io_configs_offset/4); + + for (i = 0 ; i < packet->num_io_configs; i++) + if (io_cfg_ptr[i].direction == CAM_BUF_OUTPUT) + num_out_map_entries++; + + if (num_out_map_entries <= CAM_MAX_OUT_RES) { + out_config_valid = true; + } else { + CAM_ERR(CAM_ICP, "Out config entries(%u) more than allowed(%u)", + num_out_map_entries, CAM_MAX_OUT_RES); + } + + CAM_DBG(CAM_ICP, "number of out_config info: %u %u %u %u", + packet->num_io_configs, IPE_IO_IMAGES_MAX, + num_out_map_entries, CAM_MAX_OUT_RES); + + return out_config_valid; +} + +static int cam_icp_mgr_pkt_validation(struct cam_packet *packet) +{ + if (((packet->header.op_code & 0xff) != + CAM_ICP_OPCODE_IPE_UPDATE) && + ((packet->header.op_code & 0xff) != + CAM_ICP_OPCODE_BPS_UPDATE)) { + CAM_ERR(CAM_ICP, "Invalid Opcode in pkt: %d", + packet->header.op_code & 0xff); + return -EINVAL; + } + + if (packet->num_io_configs > IPE_IO_IMAGES_MAX) { + CAM_ERR(CAM_ICP, "Invalid number of io configs: %d %d", + IPE_IO_IMAGES_MAX, packet->num_io_configs); + return -EINVAL; + } + + if (packet->num_cmd_buf > CAM_ICP_CTX_MAX_CMD_BUFFERS) { + CAM_ERR(CAM_ICP, "Invalid number of cmd buffers: %d %d", + CAM_ICP_CTX_MAX_CMD_BUFFERS, packet->num_cmd_buf); + return -EINVAL; + } + + if (!cam_icp_mgr_is_valid_inconfig(packet) || + !cam_icp_mgr_is_valid_outconfig(packet)) { + return -EINVAL; + } + + CAM_DBG(CAM_ICP, "number of cmd/patch info: %u %u %u %u", + packet->num_cmd_buf, + packet->num_io_configs, IPE_IO_IMAGES_MAX, + packet->num_patches); + return 0; +} + +static int cam_icp_mgr_process_cmd_desc(struct cam_icp_hw_mgr *hw_mgr, + struct cam_packet *packet, struct cam_icp_hw_ctx_data *ctx_data, + uint32_t *fw_cmd_buf_iova_addr) +{ + int rc = 0; + int i; + int num_cmd_buf = 0; + dma_addr_t addr; + size_t len; + struct cam_cmd_buf_desc *cmd_desc = NULL; + uintptr_t cpu_addr = 0; + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); + rc = cam_packet_util_validate_cmd_desc(cmd_desc); + if (rc) + return rc; + + *fw_cmd_buf_iova_addr = 0; + for (i = 0; i < packet->num_cmd_buf; i++, num_cmd_buf++) { + if (cmd_desc[i].type == CAM_CMD_BUF_FW) { + rc = cam_mem_get_io_buf(cmd_desc[i].mem_handle, + hw_mgr->iommu_hdl, &addr, &len); + if (rc) { + CAM_ERR(CAM_ICP, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + + if (num_cmd_buf > 0) + num_cmd_buf--; + return rc; + } + *fw_cmd_buf_iova_addr = addr; + + if ((cmd_desc[i].offset >= len) || + ((len - cmd_desc[i].offset) < + cmd_desc[i].size)){ + CAM_ERR(CAM_ICP, + "Invalid offset, i: %d offset: %u len: %zu size: %zu", + i, cmd_desc[i].offset, + len, cmd_desc[i].size); + return -EINVAL; + } + + *fw_cmd_buf_iova_addr = + (*fw_cmd_buf_iova_addr + cmd_desc[i].offset); + + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, + &cpu_addr, &len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_ICP, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + *fw_cmd_buf_iova_addr = 0; + + if (num_cmd_buf > 0) + num_cmd_buf--; + return rc; + } + if ((len <= cmd_desc[i].offset) || + (cmd_desc[i].size < cmd_desc[i].length) || + ((len - cmd_desc[i].offset) < + cmd_desc[i].length)) { + CAM_ERR(CAM_ICP, "Invalid offset or length"); + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + return -EINVAL; + } + cpu_addr = cpu_addr + cmd_desc[i].offset; + + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + } + } + + if (!cpu_addr) { + CAM_ERR(CAM_ICP, "invalid number of cmd buf"); + return -EINVAL; + } + + return rc; +} + +static int cam_icp_mgr_process_io_cfg(struct cam_icp_hw_mgr *hw_mgr, + struct cam_icp_hw_ctx_data *ctx_data, + struct cam_packet *packet, + struct cam_hw_prepare_update_args *prepare_args, + int32_t index) +{ + int i, j, k, rc = 0; + struct cam_buf_io_cfg *io_cfg_ptr = NULL; + int32_t sync_in_obj[CAM_MAX_IN_RES]; + int32_t merged_sync_in_obj; + + io_cfg_ptr = (struct cam_buf_io_cfg *) ((uint32_t *) &packet->payload + + packet->io_configs_offset/4); + prepare_args->num_out_map_entries = 0; + prepare_args->num_in_map_entries = 0; + + for (i = 0, j = 0, k = 0; i < packet->num_io_configs; i++) { + if (io_cfg_ptr[i].direction == CAM_BUF_INPUT) { + sync_in_obj[j++] = io_cfg_ptr[i].fence; + prepare_args->num_in_map_entries++; + } else { + prepare_args->out_map_entries[k++].sync_id = + io_cfg_ptr[i].fence; + prepare_args->num_out_map_entries++; + } + CAM_DBG(CAM_REQ, + "ctx_id: %u req_id: %llu dir[%d]: %u, fence: %u resource_type = %u memh %x", + ctx_data->ctx_id, packet->header.request_id, i, + io_cfg_ptr[i].direction, io_cfg_ptr[i].fence, + io_cfg_ptr[i].resource_type, + io_cfg_ptr[i].mem_handle[0]); + } + + if (prepare_args->num_in_map_entries > 1) + prepare_args->num_in_map_entries = + cam_common_util_remove_duplicate_arr( + sync_in_obj, prepare_args->num_in_map_entries); + + if (prepare_args->num_in_map_entries > 1) { + rc = cam_sync_merge(&sync_in_obj[0], + prepare_args->num_in_map_entries, &merged_sync_in_obj); + if (rc) { + prepare_args->num_out_map_entries = 0; + prepare_args->num_in_map_entries = 0; + return rc; + } + + ctx_data->hfi_frame_process.in_resource[index] = + merged_sync_in_obj; + prepare_args->in_map_entries[0].sync_id = merged_sync_in_obj; + prepare_args->num_in_map_entries = 1; + CAM_DBG(CAM_REQ, "ctx_id: %u req_id: %llu Merged Sync obj: %d", + ctx_data->ctx_id, packet->header.request_id, + merged_sync_in_obj); + } else if (prepare_args->num_in_map_entries == 1) { + prepare_args->in_map_entries[0].sync_id = sync_in_obj[0]; + prepare_args->num_in_map_entries = 1; + ctx_data->hfi_frame_process.in_resource[index] = 0; + } else { + CAM_ERR(CAM_ICP, "No input fences"); + prepare_args->num_in_map_entries = 0; + ctx_data->hfi_frame_process.in_resource[index] = 0; + rc = -EINVAL; + } + + return rc; +} + +static int cam_icp_process_stream_settings( + struct cam_icp_hw_ctx_data *ctx_data, + struct cam_cmd_mem_regions *cmd_mem_regions, + bool map_unmap) +{ + int rc = 0, i = 0; + size_t packet_size, map_cmd_size, len; + dma_addr_t iova; + unsigned long rem_jiffies; + int timeout = 5000; + struct hfi_cmd_ipe_bps_map *map_cmd; + struct hfi_cmd_ipebps_async *async_direct; + + map_cmd_size = + sizeof(struct hfi_cmd_ipe_bps_map) + + ((cmd_mem_regions->num_regions - 1) * + sizeof(struct mem_map_region_data)); + + map_cmd = kzalloc(map_cmd_size, GFP_KERNEL); + if (!map_cmd) + return -ENOMEM; + + for (i = 0; i < cmd_mem_regions->num_regions; i++) { + rc = cam_mem_get_io_buf( + cmd_mem_regions->map_info_array[i].mem_handle, + icp_hw_mgr.iommu_hdl, &iova, &len); + if (rc) { + CAM_ERR(CAM_ICP, + "Failed to get cmd region iova for handle %u", + cmd_mem_regions->map_info_array[i].mem_handle); + kfree(map_cmd); + return -EINVAL; + } + + map_cmd->mem_map_region_sets[i].start_addr = (uint32_t)iova + + (cmd_mem_regions->map_info_array[i].offset); + map_cmd->mem_map_region_sets[i].len = (uint32_t) len; + + CAM_DBG(CAM_ICP, "Region %u mem_handle %d iova %pK len %u", + (i+1), cmd_mem_regions->map_info_array[i].mem_handle, + (uint32_t)iova, (uint32_t)len); + } + + map_cmd->mem_map_request_num = cmd_mem_regions->num_regions; + map_cmd->user_data = 0; + + packet_size = + sizeof(struct hfi_cmd_ipebps_async) + + (sizeof(struct hfi_cmd_ipe_bps_map) + + ((cmd_mem_regions->num_regions - 1) * + sizeof(struct mem_map_region_data))) - + sizeof(((struct hfi_cmd_ipebps_async *)0)->payload.direct); + + async_direct = kzalloc(packet_size, GFP_KERNEL); + if (!async_direct) { + kfree(map_cmd); + return -ENOMEM; + } + + async_direct->size = packet_size; + async_direct->pkt_type = HFI_CMD_IPEBPS_ASYNC_COMMAND_DIRECT; + if (map_unmap) + async_direct->opcode = HFI_IPEBPS_CMD_OPCODE_MEM_MAP; + else + async_direct->opcode = HFI_IPEBPS_CMD_OPCODE_MEM_UNMAP; + async_direct->num_fw_handles = 1; + async_direct->fw_handles[0] = ctx_data->fw_handle; + async_direct->user_data1 = (uint64_t)ctx_data; + async_direct->user_data2 = (uint64_t)0x0; + memcpy(async_direct->payload.direct, map_cmd, + map_cmd_size); + + reinit_completion(&ctx_data->wait_complete); + rc = hfi_write_cmd(async_direct); + if (rc) { + CAM_ERR(CAM_ICP, "hfi write failed rc %d", rc); + goto end; + } + + CAM_DBG(CAM_ICP, "Sent FW %s cmd", + map_unmap ? "Map" : "Unmap"); + + rem_jiffies = wait_for_completion_timeout(&ctx_data->wait_complete, + msecs_to_jiffies((timeout))); + if (!rem_jiffies) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_ICP, "FW response timed out %d", rc); + cam_hfi_queue_dump(); + } + +end: + kfree(map_cmd); + kfree(async_direct); + return rc; +} + +static int cam_icp_packet_generic_blob_handler(void *user_data, + uint32_t blob_type, uint32_t blob_size, uint8_t *blob_data) +{ + struct cam_icp_clk_bw_request *soc_req; + struct cam_icp_clk_bw_request *clk_info; + struct cam_icp_clk_bw_request_v2 *soc_req_v2; + struct cam_icp_clk_bw_req_internal_v2 *clk_info_v2; + struct cam_cmd_mem_regions *cmd_mem_regions; + struct icp_cmd_generic_blob *blob; + struct cam_icp_hw_ctx_data *ctx_data; + uint32_t index; + size_t io_buf_size, clk_update_size; + int rc = 0; + uintptr_t pResource; + uint32_t i = 0; + + if (!blob_data || (blob_size == 0)) { + CAM_ERR(CAM_ICP, "Invalid blob info %pK %d", blob_data, + blob_size); + return -EINVAL; + } + + blob = (struct icp_cmd_generic_blob *)user_data; + ctx_data = blob->ctx; + index = blob->frame_info_idx; + + switch (blob_type) { + case CAM_ICP_CMD_GENERIC_BLOB_CLK: + CAM_WARN_RATE_LIMIT_CUSTOM(CAM_PERF, 300, 1, + "Using deprecated blob type GENERIC_BLOB_CLK"); + if (blob_size != sizeof(struct cam_icp_clk_bw_request)) { + CAM_ERR(CAM_ICP, "Mismatch blob size %d expected %lu", + blob_size, + sizeof(struct cam_icp_clk_bw_request)); + return -EINVAL; + } + + if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_UNKNOWN) { + ctx_data->bw_config_version = CAM_ICP_BW_CONFIG_V1; + } else if (ctx_data->bw_config_version != + CAM_ICP_BW_CONFIG_V1) { + CAM_ERR(CAM_ICP, + "Mismatch blob versions %d expected v1 %d, blob_type=%d", + ctx_data->bw_config_version, + CAM_ICP_BW_CONFIG_V1, blob_type); + return -EINVAL; + } + + clk_info = &ctx_data->hfi_frame_process.clk_info[index]; + + soc_req = (struct cam_icp_clk_bw_request *)blob_data; + *clk_info = *soc_req; + CAM_DBG(CAM_PERF, "budget:%llu fc: %llu %d BW %lld %lld", + clk_info->budget_ns, clk_info->frame_cycles, + clk_info->rt_flag, clk_info->uncompressed_bw, + clk_info->compressed_bw); + break; + + case CAM_ICP_CMD_GENERIC_BLOB_CLK_V2: + if (blob_size < sizeof(struct cam_icp_clk_bw_request_v2)) { + CAM_ERR(CAM_ICP, "Mismatch blob size %d expected %lu", + blob_size, + sizeof(struct cam_icp_clk_bw_request_v2)); + return -EINVAL; + } + + if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_UNKNOWN) { + ctx_data->bw_config_version = CAM_ICP_BW_CONFIG_V2; + } else if (ctx_data->bw_config_version != + CAM_ICP_BW_CONFIG_V2) { + CAM_ERR(CAM_ICP, + "Mismatch blob versions %d expected v2 %d, blob_type=%d", + ctx_data->bw_config_version, + CAM_ICP_BW_CONFIG_V2, blob_type); + return -EINVAL; + } + + soc_req_v2 = (struct cam_icp_clk_bw_request_v2 *)blob_data; + if (soc_req_v2->num_paths > CAM_ICP_MAX_PER_PATH_VOTES) { + CAM_ERR(CAM_PERF, "Invalid num paths: %d", + soc_req_v2->num_paths); + return -EINVAL; + } + + /* Check for integer overflow */ + if (soc_req_v2->num_paths != 1) { + if (sizeof(struct cam_axi_per_path_bw_vote) > + ((UINT_MAX - + sizeof(struct cam_icp_clk_bw_request_v2)) / + (soc_req_v2->num_paths - 1))) { + CAM_ERR(CAM_ICP, + "Size exceeds limit paths:%u size per path:%lu", + soc_req_v2->num_paths - 1, + sizeof( + struct cam_axi_per_path_bw_vote)); + return -EINVAL; + } + } + + clk_update_size = sizeof(struct cam_icp_clk_bw_request_v2) + + ((soc_req_v2->num_paths - 1) * + sizeof(struct cam_axi_per_path_bw_vote)); + if (blob_size < clk_update_size) { + CAM_ERR(CAM_ICP, "Invalid blob size: %u", + blob_size); + return -EINVAL; + } + + clk_info = &ctx_data->hfi_frame_process.clk_info[index]; + clk_info_v2 = &ctx_data->hfi_frame_process.clk_info_v2[index]; + + memcpy(clk_info_v2, soc_req_v2, clk_update_size); + + /* Use v1 structure for clk fields */ + clk_info->budget_ns = clk_info_v2->budget_ns; + clk_info->frame_cycles = clk_info_v2->frame_cycles; + clk_info->rt_flag = clk_info_v2->rt_flag; + + CAM_DBG(CAM_PERF, + "budget=%llu, frame_cycle=%llu, rt_flag=%d, num_paths=%d, clk_update_size=%d, index=%d, ctx_data=%pK", + clk_info_v2->budget_ns, clk_info_v2->frame_cycles, + clk_info_v2->rt_flag, + clk_info_v2->num_paths, + clk_update_size, + index, + ctx_data); + + for (i = 0; i < clk_info_v2->num_paths; i++) { + CAM_DBG(CAM_PERF, + "[%d] : path_type=%d, trans_type=%d, camnoc=%lld, mnoc_ab=%lld, mnoc_ib=%lld", + i, + clk_info_v2->axi_path[i].path_data_type, + clk_info_v2->axi_path[i].transac_type, + clk_info_v2->axi_path[i].camnoc_bw, + clk_info_v2->axi_path[i].mnoc_ab_bw, + clk_info_v2->axi_path[i].mnoc_ib_bw); + } + + break; + + case CAM_ICP_CMD_GENERIC_BLOB_CFG_IO: + CAM_DBG(CAM_ICP, "CAM_ICP_CMD_GENERIC_BLOB_CFG_IO"); + pResource = *((uint32_t *)blob_data); + if (copy_from_user(&ctx_data->icp_dev_io_info, + (void __user *)pResource, + sizeof(struct cam_icp_acquire_dev_info))) { + CAM_ERR(CAM_ICP, "Failed in copy from user"); + return -EFAULT; + } + CAM_DBG(CAM_ICP, "buf handle %d", + ctx_data->icp_dev_io_info.io_config_cmd_handle); + rc = cam_mem_get_io_buf( + ctx_data->icp_dev_io_info.io_config_cmd_handle, + icp_hw_mgr.iommu_hdl, + blob->io_buf_addr, &io_buf_size); + if (rc) + CAM_ERR(CAM_ICP, "Failed in blob update"); + else + CAM_DBG(CAM_ICP, "io buf addr %llu", + *blob->io_buf_addr); + break; + + case CAM_ICP_CMD_GENERIC_BLOB_FW_MEM_MAP: + cmd_mem_regions = + (struct cam_cmd_mem_regions *)blob_data; + if (cmd_mem_regions->num_regions <= 0) { + rc = -EINVAL; + CAM_ERR(CAM_ICP, + "Invalid number of regions for FW map %u", + cmd_mem_regions->num_regions); + } else { + CAM_DBG(CAM_ICP, + "Processing blob for mapping %u regions", + cmd_mem_regions->num_regions); + rc = cam_icp_process_stream_settings(ctx_data, + cmd_mem_regions, true); + } + break; + + case CAM_ICP_CMD_GENERIC_BLOB_FW_MEM_UNMAP: + cmd_mem_regions = + (struct cam_cmd_mem_regions *)blob_data; + if (cmd_mem_regions->num_regions <= 0) { + rc = -EINVAL; + CAM_ERR(CAM_ICP, + "Invalid number of regions for FW unmap %u", + cmd_mem_regions->num_regions); + } else { + CAM_DBG(CAM_ICP, + "Processing blob for unmapping %u regions", + cmd_mem_regions->num_regions); + rc = cam_icp_process_stream_settings(ctx_data, + cmd_mem_regions, false); + } + break; + + default: + CAM_WARN(CAM_ICP, "Invalid blob type %d", blob_type); + break; + } + return rc; +} + +static int cam_icp_process_generic_cmd_buffer( + struct cam_packet *packet, + struct cam_icp_hw_ctx_data *ctx_data, + int32_t index, + dma_addr_t *io_buf_addr) +{ + int i, rc = 0; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct icp_cmd_generic_blob cmd_generic_blob; + + cmd_generic_blob.ctx = ctx_data; + cmd_generic_blob.frame_info_idx = index; + cmd_generic_blob.io_buf_addr = io_buf_addr; + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); + for (i = 0; i < packet->num_cmd_buf; i++) { + if (!cmd_desc[i].length) + continue; + + if (cmd_desc[i].meta_data != CAM_ICP_CMD_META_GENERIC_BLOB) + continue; + + rc = cam_packet_util_process_generic_cmd_buffer(&cmd_desc[i], + cam_icp_packet_generic_blob_handler, &cmd_generic_blob); + if (rc) + CAM_ERR(CAM_ICP, "Failed in processing blobs %d", rc); + } + + return rc; +} + +static int cam_icp_mgr_process_cfg_io_cmd( + struct cam_icp_hw_ctx_data *ctx_data, + struct hfi_cmd_ipebps_async *ioconfig_cmd, + uint64_t request_id, + uint64_t io_config) +{ + ioconfig_cmd->size = sizeof(struct hfi_cmd_ipebps_async); + ioconfig_cmd->pkt_type = HFI_CMD_IPEBPS_ASYNC_COMMAND_INDIRECT; + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) + ioconfig_cmd->opcode = HFI_IPEBPS_CMD_OPCODE_BPS_CONFIG_IO; + else + ioconfig_cmd->opcode = HFI_IPEBPS_CMD_OPCODE_IPE_CONFIG_IO; + + ioconfig_cmd->num_fw_handles = 1; + ioconfig_cmd->fw_handles[0] = ctx_data->fw_handle; + ioconfig_cmd->payload.indirect = io_config; + ioconfig_cmd->user_data1 = PTR_TO_U64(ctx_data); + ioconfig_cmd->user_data2 = request_id; + + return 0; +} + +static int cam_icp_mgr_update_hfi_frame_process( + struct cam_icp_hw_ctx_data *ctx_data, + struct cam_packet *packet, + struct cam_hw_prepare_update_args *prepare_args, + int32_t *idx) +{ + int32_t index, rc; + struct hfi_cmd_ipebps_async *hfi_cmd = NULL; + + index = find_first_zero_bit(ctx_data->hfi_frame_process.bitmap, + ctx_data->hfi_frame_process.bits); + if (index < 0 || index >= CAM_FRAME_CMD_MAX) { + CAM_ERR(CAM_ICP, "request idx is wrong: %d", index); + return -EINVAL; + } + set_bit(index, ctx_data->hfi_frame_process.bitmap); + + ctx_data->hfi_frame_process.request_id[index] = + packet->header.request_id; + ctx_data->hfi_frame_process.frame_info[index].request_id = + packet->header.request_id; + ctx_data->hfi_frame_process.frame_info[index].io_config = 0; + rc = cam_icp_process_generic_cmd_buffer(packet, ctx_data, index, + &ctx_data->hfi_frame_process.frame_info[index].io_config); + if (rc) { + clear_bit(index, ctx_data->hfi_frame_process.bitmap); + ctx_data->hfi_frame_process.request_id[index] = -1; + return rc; + } + + if (ctx_data->hfi_frame_process.frame_info[index].io_config) { + hfi_cmd = (struct hfi_cmd_ipebps_async *) + &ctx_data->hfi_frame_process.frame_info[index].hfi_cfg_io_cmd; + rc = cam_icp_mgr_process_cfg_io_cmd(ctx_data, hfi_cmd, + packet->header.request_id, + ctx_data->hfi_frame_process.frame_info[index].io_config); + } + *idx = index; + + return rc; +} + +static void cam_icp_mgr_print_io_bufs(struct cam_packet *packet, + int32_t iommu_hdl, int32_t sec_mmu_hdl, uint32_t pf_buf_info, + bool *mem_found) +{ + dma_addr_t iova_addr; + size_t src_buf_size; + int i; + int j; + int rc = 0; + int32_t mmu_hdl; + + struct cam_buf_io_cfg *io_cfg = NULL; + + if (mem_found) + *mem_found = false; + + io_cfg = (struct cam_buf_io_cfg *)((uint32_t *)&packet->payload + + packet->io_configs_offset / 4); + + for (i = 0; i < packet->num_io_configs; i++) { + for (j = 0; j < CAM_PACKET_MAX_PLANES; j++) { + if (!io_cfg[i].mem_handle[j]) + break; + + if (GET_FD_FROM_HANDLE(io_cfg[i].mem_handle[j]) == + GET_FD_FROM_HANDLE(pf_buf_info)) { + CAM_INFO(CAM_ICP, + "Found PF at port: %d mem %x fd: %x", + io_cfg[i].resource_type, + io_cfg[i].mem_handle[j], + pf_buf_info); + if (mem_found) + *mem_found = true; + } + + CAM_INFO(CAM_ICP, "port: %d f: %u format: %d dir %d", + io_cfg[i].resource_type, + io_cfg[i].fence, + io_cfg[i].format, + io_cfg[i].direction); + + mmu_hdl = cam_mem_is_secure_buf( + io_cfg[i].mem_handle[j]) ? sec_mmu_hdl : + iommu_hdl; + rc = cam_mem_get_io_buf(io_cfg[i].mem_handle[j], + mmu_hdl, &iova_addr, &src_buf_size); + if (rc < 0) { + CAM_ERR(CAM_UTIL, + "get src buf address fail rc %d", rc); + continue; + } + if ((iova_addr & 0xFFFFFFFF) != iova_addr) { + CAM_ERR(CAM_ICP, "Invalid mapped address"); + rc = -EINVAL; + continue; + } + + CAM_INFO(CAM_ICP, + "pln %d dir %d w %d h %d s %u sh %u sz %d addr 0x%x off 0x%x memh %x", + j, io_cfg[i].direction, + io_cfg[i].planes[j].width, + io_cfg[i].planes[j].height, + io_cfg[i].planes[j].plane_stride, + io_cfg[i].planes[j].slice_height, + (int32_t)src_buf_size, + (unsigned int)iova_addr, + io_cfg[i].offsets[j], + io_cfg[i].mem_handle[j]); + + iova_addr += io_cfg[i].offsets[j]; + + } + } + cam_packet_dump_patch_info(packet, icp_hw_mgr.iommu_hdl, + icp_hw_mgr.iommu_sec_hdl); +} + +static int cam_icp_mgr_config_stream_settings( + void *hw_mgr_priv, void *hw_stream_settings) +{ + int rc = 0; + struct cam_icp_hw_ctx_data *ctx_data = NULL; + struct cam_packet *packet = NULL; + struct cam_icp_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct icp_cmd_generic_blob cmd_generic_blob; + struct cam_hw_stream_setttings *config_args = + hw_stream_settings; + + if ((!hw_stream_settings) || + (!hw_mgr) || (!config_args->packet)) { + CAM_ERR(CAM_ICP, "Invalid input arguments"); + return -EINVAL; + } + + ctx_data = config_args->ctxt_to_hw_map; + mutex_lock(&ctx_data->ctx_mutex); + packet = config_args->packet; + + cmd_generic_blob.ctx = ctx_data; + cmd_generic_blob.frame_info_idx = -1; + cmd_generic_blob.io_buf_addr = NULL; + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); + + if (!cmd_desc[0].length || + cmd_desc[0].meta_data != CAM_ICP_CMD_META_GENERIC_BLOB) { + CAM_ERR(CAM_ICP, "Invalid cmd buffer length/metadata"); + rc = -EINVAL; + goto end; + } + + rc = cam_packet_util_process_generic_cmd_buffer(&cmd_desc[0], + cam_icp_packet_generic_blob_handler, &cmd_generic_blob); + if (rc) + CAM_ERR(CAM_ICP, "Failed in processing cmd mem blob %d", rc); + +end: + mutex_unlock(&ctx_data->ctx_mutex); + return rc; +} + +static int cam_icp_mgr_prepare_hw_update(void *hw_mgr_priv, + void *prepare_hw_update_args) +{ + int rc = 0; + int32_t idx; + uint32_t fw_cmd_buf_iova_addr; + struct cam_icp_hw_ctx_data *ctx_data = NULL; + struct cam_packet *packet = NULL; + struct hfi_cmd_ipebps_async *hfi_cmd = NULL; + struct cam_icp_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_prepare_update_args *prepare_args = + prepare_hw_update_args; + + if ((!prepare_args) || (!hw_mgr) || (!prepare_args->packet)) { + CAM_ERR(CAM_ICP, "Invalid args"); + return -EINVAL; + } + + ctx_data = prepare_args->ctxt_to_hw_map; + mutex_lock(&ctx_data->ctx_mutex); + if (ctx_data->state != CAM_ICP_CTX_STATE_ACQUIRED) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_ICP, "ctx id: %u is not in use", + ctx_data->ctx_id); + return -EINVAL; + } + + packet = prepare_args->packet; + + if (cam_packet_util_validate_packet(packet, prepare_args->remain_len)) + return -EINVAL; + + rc = cam_icp_mgr_pkt_validation(packet); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + return rc; + } + + rc = cam_icp_mgr_process_cmd_desc(hw_mgr, packet, + ctx_data, &fw_cmd_buf_iova_addr); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + return rc; + } + + prepare_args->pf_data->packet = packet; + + CAM_DBG(CAM_REQ, "req id = %lld for ctx = %u", + packet->header.request_id, ctx_data->ctx_id); + /* Update Buffer Address from handles and patch information */ + rc = cam_packet_util_process_patches(packet, hw_mgr->iommu_hdl, + hw_mgr->iommu_sec_hdl); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + return rc; + } + + rc = cam_icp_mgr_update_hfi_frame_process(ctx_data, packet, + prepare_args, &idx); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + return rc; + } + + rc = cam_icp_mgr_process_io_cfg(hw_mgr, ctx_data, + packet, prepare_args, idx); + if (rc) { + if (ctx_data->hfi_frame_process.in_resource[idx] > 0) + cam_sync_destroy( + ctx_data->hfi_frame_process.in_resource[idx]); + clear_bit(idx, ctx_data->hfi_frame_process.bitmap); + ctx_data->hfi_frame_process.request_id[idx] = -1; + mutex_unlock(&ctx_data->ctx_mutex); + return rc; + } + + hfi_cmd = (struct hfi_cmd_ipebps_async *) + &ctx_data->hfi_frame_process.hfi_frame_cmd[idx]; + cam_icp_mgr_prepare_frame_process_cmd( + ctx_data, hfi_cmd, packet->header.request_id, + fw_cmd_buf_iova_addr); + + prepare_args->num_hw_update_entries = 1; + prepare_args->hw_update_entries[0].addr = (uintptr_t)hfi_cmd; + prepare_args->priv = &ctx_data->hfi_frame_process.frame_info[idx]; + + CAM_DBG(CAM_ICP, "X: req id = %lld ctx_id = %u", + packet->header.request_id, ctx_data->ctx_id); + mutex_unlock(&ctx_data->ctx_mutex); + return rc; +} + +static int cam_icp_mgr_send_abort_status(struct cam_icp_hw_ctx_data *ctx_data) +{ + struct hfi_frame_process_info *hfi_frame_process; + int idx; + + mutex_lock(&ctx_data->ctx_mutex); + hfi_frame_process = &ctx_data->hfi_frame_process; + for (idx = 0; idx < CAM_FRAME_CMD_MAX; idx++) { + if (!hfi_frame_process->request_id[idx]) + continue; + + ctx_data->ctxt_event_cb(ctx_data->context_priv, true, + &hfi_frame_process->request_id[idx]); + + /* now release memory for hfi frame process command */ + hfi_frame_process->request_id[idx] = 0; + if (ctx_data->hfi_frame_process.in_resource[idx] > 0) { + CAM_DBG(CAM_ICP, "Delete merged sync in object: %d", + ctx_data->hfi_frame_process.in_resource[idx]); + cam_sync_destroy( + ctx_data->hfi_frame_process.in_resource[idx]); + ctx_data->hfi_frame_process.in_resource[idx] = 0; + } + clear_bit(idx, ctx_data->hfi_frame_process.bitmap); + } + mutex_unlock(&ctx_data->ctx_mutex); + return 0; +} + +static int cam_icp_mgr_delete_sync(void *priv, void *data) +{ + struct hfi_cmd_work_data *task_data = NULL; + struct cam_icp_hw_ctx_data *ctx_data; + struct hfi_frame_process_info *hfi_frame_process; + int idx; + + if (!data || !priv) { + CAM_ERR(CAM_ICP, "Invalid params%pK %pK", data, priv); + return -EINVAL; + } + + task_data = (struct hfi_cmd_work_data *)data; + ctx_data = task_data->data; + + if (!ctx_data) { + CAM_ERR(CAM_ICP, "Null Context"); + return -EINVAL; + } + + mutex_lock(&ctx_data->ctx_mutex); + hfi_frame_process = &ctx_data->hfi_frame_process; + for (idx = 0; idx < CAM_FRAME_CMD_MAX; idx++) { + if (!hfi_frame_process->in_free_resource[idx]) + continue; + //cam_sync_destroy( + //ctx_data->hfi_frame_process.in_free_resource[idx]); + ctx_data->hfi_frame_process.in_resource[idx] = 0; + } + mutex_unlock(&ctx_data->ctx_mutex); + return 0; +} + +static int cam_icp_mgr_delete_sync_obj(struct cam_icp_hw_ctx_data *ctx_data) +{ + int rc = 0; + struct crm_workq_task *task; + struct hfi_cmd_work_data *task_data; + + task = cam_req_mgr_workq_get_task(icp_hw_mgr.cmd_work); + if (!task) { + CAM_ERR(CAM_ICP, "no empty task"); + return -ENOMEM; + } + + task_data = (struct hfi_cmd_work_data *)task->payload; + task_data->data = (void *)ctx_data; + task_data->request_id = 0; + task_data->type = ICP_WORKQ_TASK_CMD_TYPE; + task->process_cb = cam_icp_mgr_delete_sync; + rc = cam_req_mgr_workq_enqueue_task(task, &icp_hw_mgr, + CRM_TASK_PRIORITY_0); + + return rc; +} + +static int cam_icp_mgr_flush_all(struct cam_icp_hw_ctx_data *ctx_data, + struct cam_hw_flush_args *flush_args) +{ + struct hfi_frame_process_info *hfi_frame_process; + int idx; + bool clear_in_resource = false; + + hfi_frame_process = &ctx_data->hfi_frame_process; + for (idx = 0; idx < CAM_FRAME_CMD_MAX; idx++) { + if (!hfi_frame_process->request_id[idx]) + continue; + + /* now release memory for hfi frame process command */ + hfi_frame_process->request_id[idx] = 0; + if (ctx_data->hfi_frame_process.in_resource[idx] > 0) { + ctx_data->hfi_frame_process.in_free_resource[idx] = + ctx_data->hfi_frame_process.in_resource[idx]; + ctx_data->hfi_frame_process.in_resource[idx] = 0; + } + clear_bit(idx, ctx_data->hfi_frame_process.bitmap); + clear_in_resource = true; + } + + if (clear_in_resource) + cam_icp_mgr_delete_sync_obj(ctx_data); + + return 0; +} + +static int cam_icp_mgr_flush_req(struct cam_icp_hw_ctx_data *ctx_data, + struct cam_hw_flush_args *flush_args) +{ + int64_t request_id; + struct hfi_frame_process_info *hfi_frame_process; + int idx; + bool clear_in_resource = false; + + hfi_frame_process = &ctx_data->hfi_frame_process; + request_id = *(int64_t *)flush_args->flush_req_pending[0]; + for (idx = 0; idx < CAM_FRAME_CMD_MAX; idx++) { + if (!hfi_frame_process->request_id[idx]) + continue; + + if (hfi_frame_process->request_id[idx] != request_id) + continue; + + /* now release memory for hfi frame process command */ + hfi_frame_process->request_id[idx] = 0; + if (ctx_data->hfi_frame_process.in_resource[idx] > 0) { + ctx_data->hfi_frame_process.in_free_resource[idx] = + ctx_data->hfi_frame_process.in_resource[idx]; + ctx_data->hfi_frame_process.in_resource[idx] = 0; + } + clear_bit(idx, ctx_data->hfi_frame_process.bitmap); + clear_in_resource = true; + } + + if (clear_in_resource) + cam_icp_mgr_delete_sync_obj(ctx_data); + + return 0; +} + +static void cam_icp_mgr_flush_info_dump( + struct cam_hw_flush_args *flush_args, uint32_t ctx_id) +{ + int i; + + for (i = 0; i < flush_args->num_req_active; i++) { + CAM_DBG(CAM_ICP, "Flushing active request %lld in ctx %u", + *(int64_t *)flush_args->flush_req_active[i], + ctx_id); + } + + for (i = 0; i < flush_args->num_req_pending; i++) { + CAM_DBG(CAM_ICP, "Flushing pending request %lld in ctx %u", + *(int64_t *)flush_args->flush_req_pending[i], + ctx_id); + } +} + +static int cam_icp_mgr_enqueue_abort( + struct cam_icp_hw_ctx_data *ctx_data) +{ + int timeout = 1000, rc; + unsigned long rem_jiffies = 0; + struct hfi_cmd_work_data *task_data; + struct crm_workq_task *task; + + task = cam_req_mgr_workq_get_task(icp_hw_mgr.cmd_work); + if (!task) { + CAM_ERR(CAM_ICP, "no empty task"); + return -ENOMEM; + } + + reinit_completion(&ctx_data->wait_complete); + task_data = (struct hfi_cmd_work_data *)task->payload; + task_data->data = (void *)ctx_data; + task_data->type = ICP_WORKQ_TASK_CMD_TYPE; + task->process_cb = cam_icp_mgr_abort_handle_wq; + cam_req_mgr_workq_enqueue_task(task, &icp_hw_mgr, + CRM_TASK_PRIORITY_0); + + rem_jiffies = wait_for_completion_timeout(&ctx_data->wait_complete, + msecs_to_jiffies((timeout))); + if (!rem_jiffies) { + rc = cam_icp_retry_wait_for_abort(ctx_data); + if (rc) { + CAM_ERR(CAM_ICP, + "FW timeout/err in abort handle command ctx: %u", + ctx_data->ctx_id); + cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); + cam_hfi_queue_dump(); + return rc; + } + } + + CAM_DBG(CAM_ICP, "Abort after flush is success"); + return 0; +} + +static int cam_icp_mgr_hw_dump(void *hw_priv, void *hw_dump_args) +{ + int rc; + int i; + size_t remain_len; + uint8_t *dst; + uint32_t min_len; + uint64_t diff; + uint64_t *addr, *start; + struct timespec64 cur_ts; + struct timespec64 req_ts; + ktime_t cur_time; + struct cam_hw_intf *a5_dev_intf; + struct cam_icp_hw_mgr *hw_mgr; + struct cam_hw_dump_args *dump_args; + struct cam_icp_hw_ctx_data *ctx_data; + struct cam_icp_dump_header *hdr; + struct cam_icp_hw_dump_args icp_dump_args; + struct hfi_frame_process_info *frm_process; + + if ((!hw_priv) || (!hw_dump_args)) { + CAM_ERR(CAM_ICP, "Invalid params %pK %pK", + hw_priv, hw_dump_args); + return -EINVAL; + } + + dump_args = (struct cam_hw_dump_args *)hw_dump_args; + hw_mgr = hw_priv; + ctx_data = dump_args->ctxt_to_hw_map; + CAM_DBG(CAM_ICP, "Req %lld", dump_args->request_id); + frm_process = &ctx_data->hfi_frame_process; + for (i = 0; i < CAM_FRAME_CMD_MAX; i++) { + if ((frm_process->request_id[i] == + dump_args->request_id) && + frm_process->fw_process_flag[i]) + goto hw_dump; + } + return 0; +hw_dump: + cur_time = ktime_get(); + diff = ktime_us_delta(frm_process->submit_timestamp[i], cur_time); + cur_ts = ktime_to_timespec64(cur_time); + req_ts = ktime_to_timespec64(frm_process->submit_timestamp[i]); + + if (diff < CAM_ICP_CTX_RESPONSE_TIME_THRESHOLD) { + CAM_INFO(CAM_ICP, "No Error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + return 0; + } + + CAM_INFO(CAM_ICP, "Error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &icp_dump_args.cpu_addr, &icp_dump_args.buf_len); + if (rc) { + CAM_ERR(CAM_ICP, "Invalid addr %u rc %d", + dump_args->buf_handle, rc); + return rc; + } + if (icp_dump_args.buf_len <= dump_args->offset) { + CAM_WARN(CAM_ICP, "dump buffer overshoot len %zu offset %zu", + icp_dump_args.buf_len, dump_args->offset); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return -ENOSPC; + } + + remain_len = icp_dump_args.buf_len - dump_args->offset; + min_len = sizeof(struct cam_icp_dump_header) + + (CAM_ICP_DUMP_NUM_WORDS * sizeof(uint64_t)); + + if (remain_len < min_len) { + CAM_WARN(CAM_ICP, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return -ENOSPC; + } + + dst = (uint8_t *)icp_dump_args.cpu_addr + dump_args->offset; + hdr = (struct cam_icp_dump_header *)dst; + scnprintf(hdr->tag, CAM_ICP_DUMP_TAG_MAX_LEN, "ICP_REQ:"); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + sizeof(struct cam_icp_dump_header)); + start = addr; + *addr++ = frm_process->request_id[i]; + *addr++ = req_ts.tv_sec; + *addr++ = req_ts.tv_nsec/NSEC_PER_USEC; + *addr++ = cur_ts.tv_sec; + *addr++ = cur_ts.tv_nsec/NSEC_PER_USEC; + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += (hdr->size + sizeof(struct cam_icp_dump_header)); + /* Dumping the fw image*/ + icp_dump_args.offset = dump_args->offset; + a5_dev_intf = hw_mgr->a5_dev_intf; + rc = a5_dev_intf->hw_ops.process_cmd( + a5_dev_intf->hw_priv, + CAM_ICP_A5_CMD_HW_DUMP, &icp_dump_args, + sizeof(struct cam_icp_hw_dump_args)); + CAM_DBG(CAM_ICP, "Offset before %zu after %zu", + dump_args->offset, icp_dump_args.offset); + dump_args->offset = icp_dump_args.offset; + + cam_mem_put_cpu_buf(dump_args->buf_handle); + return rc; +} + +static int cam_icp_mgr_hw_flush(void *hw_priv, void *hw_flush_args) +{ + struct cam_hw_flush_args *flush_args = hw_flush_args; + struct cam_icp_hw_ctx_data *ctx_data; + struct cam_icp_hw_mgr *hw_mgr = hw_priv; + + if ((!hw_priv) || (!hw_flush_args)) { + CAM_ERR(CAM_ICP, "Input params are Null:"); + return -EINVAL; + } + + ctx_data = flush_args->ctxt_to_hw_map; + if (!ctx_data) { + CAM_ERR(CAM_ICP, "Ctx data is NULL"); + return -EINVAL; + } + + if ((flush_args->flush_type >= CAM_FLUSH_TYPE_MAX) || + (flush_args->flush_type < CAM_FLUSH_TYPE_REQ)) { + CAM_ERR(CAM_ICP, "Invalid lush type: %d", + flush_args->flush_type); + return -EINVAL; + } + + ctx_data->last_flush_req = flush_args->last_flush_req; + CAM_DBG(CAM_REQ, "ctx_id %d Flush type %d last_flush_req %u", + ctx_data->ctx_id, flush_args->flush_type, + ctx_data->last_flush_req); + switch (flush_args->flush_type) { + case CAM_FLUSH_TYPE_ALL: + mutex_lock(&hw_mgr->hw_mgr_mutex); + if (!atomic_read(&hw_mgr->recovery) + && flush_args->num_req_active) { + mutex_unlock(&hw_mgr->hw_mgr_mutex); + cam_icp_mgr_flush_info_dump(flush_args, + ctx_data->ctx_id); + cam_icp_mgr_enqueue_abort(ctx_data); + } else { + mutex_unlock(&hw_mgr->hw_mgr_mutex); + } + mutex_lock(&ctx_data->ctx_mutex); + cam_icp_mgr_flush_all(ctx_data, flush_args); + mutex_unlock(&ctx_data->ctx_mutex); + break; + case CAM_FLUSH_TYPE_REQ: + mutex_lock(&ctx_data->ctx_mutex); + if (flush_args->num_req_active) { + CAM_ERR(CAM_ICP, "Flush request is not supported"); + mutex_unlock(&ctx_data->ctx_mutex); + return -EINVAL; + } + if (flush_args->num_req_pending) + cam_icp_mgr_flush_req(ctx_data, flush_args); + mutex_unlock(&ctx_data->ctx_mutex); + break; + default: + CAM_ERR(CAM_ICP, "Invalid flush type: %d", + flush_args->flush_type); + return -EINVAL; + } + + return 0; +} + +static int cam_icp_mgr_release_hw(void *hw_mgr_priv, void *release_hw_args) +{ + int rc = 0; + int ctx_id = 0; + struct cam_hw_release_args *release_hw = release_hw_args; + struct cam_icp_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_icp_hw_ctx_data *ctx_data = NULL; + + if (!release_hw || !hw_mgr) { + CAM_ERR(CAM_ICP, "Invalid args: %pK %pK", release_hw, hw_mgr); + return -EINVAL; + } + + CAM_DBG(CAM_ICP, "Enter recovery set %d", + atomic_read(&hw_mgr->recovery)); + ctx_data = release_hw->ctxt_to_hw_map; + if (!ctx_data) { + CAM_ERR(CAM_ICP, "NULL ctx data"); + return -EINVAL; + } + + ctx_id = ctx_data->ctx_id; + if (ctx_id < 0 || ctx_id >= CAM_ICP_CTX_MAX) { + CAM_ERR(CAM_ICP, "Invalid ctx id: %d", ctx_id); + return -EINVAL; + } + + mutex_lock(&hw_mgr->ctx_data[ctx_id].ctx_mutex); + if (hw_mgr->ctx_data[ctx_id].state != CAM_ICP_CTX_STATE_ACQUIRED) { + CAM_DBG(CAM_ICP, "ctx is not in use: %d", ctx_id); + mutex_unlock(&hw_mgr->ctx_data[ctx_id].ctx_mutex); + return -EINVAL; + } + mutex_unlock(&hw_mgr->ctx_data[ctx_id].ctx_mutex); + + mutex_lock(&hw_mgr->hw_mgr_mutex); + if (!atomic_read(&hw_mgr->recovery) && release_hw->active_req) { + mutex_unlock(&hw_mgr->hw_mgr_mutex); + cam_icp_mgr_abort_handle(ctx_data); + cam_icp_mgr_send_abort_status(ctx_data); + } else { + mutex_unlock(&hw_mgr->hw_mgr_mutex); + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + rc = cam_icp_mgr_release_ctx(hw_mgr, ctx_id); + if (!hw_mgr->ctxt_cnt) { + CAM_DBG(CAM_ICP, "Last Release"); + cam_icp_mgr_icp_power_collapse(hw_mgr); + cam_icp_hw_mgr_reset_clk_info(hw_mgr); + rc = cam_ipe_bps_deint(hw_mgr); + } + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + if ((!hw_mgr->bps_ctxt_cnt || !hw_mgr->ipe_ctxt_cnt)) + cam_icp_device_timer_stop(hw_mgr); + + CAM_DBG(CAM_ICP, "Release done for ctx_id %d", ctx_id); + return rc; +} + +static int cam_icp_mgr_create_handle(uint32_t dev_type, + struct cam_icp_hw_ctx_data *ctx_data) +{ + struct hfi_cmd_create_handle create_handle; + struct hfi_cmd_work_data *task_data; + unsigned long rem_jiffies; + int timeout = 5000; + struct crm_workq_task *task; + int rc = 0; + + task = cam_req_mgr_workq_get_task(icp_hw_mgr.cmd_work); + if (!task) + return -ENOMEM; + + create_handle.size = sizeof(struct hfi_cmd_create_handle); + create_handle.pkt_type = HFI_CMD_IPEBPS_CREATE_HANDLE; + create_handle.handle_type = dev_type; + create_handle.user_data1 = PTR_TO_U64(ctx_data); + reinit_completion(&ctx_data->wait_complete); + task_data = (struct hfi_cmd_work_data *)task->payload; + task_data->data = (void *)&create_handle; + task_data->request_id = 0; + task_data->type = ICP_WORKQ_TASK_CMD_TYPE; + task->process_cb = cam_icp_mgr_process_cmd; + rc = cam_req_mgr_workq_enqueue_task(task, &icp_hw_mgr, + CRM_TASK_PRIORITY_0); + if (rc) + return rc; + + rem_jiffies = wait_for_completion_timeout(&ctx_data->wait_complete, + msecs_to_jiffies((timeout))); + if (!rem_jiffies) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_ICP, "FW response timed out %d", rc); + cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); + cam_hfi_queue_dump(); + } + + if (ctx_data->fw_handle == 0) { + CAM_ERR(CAM_ICP, "Invalid handle created"); + rc = -EINVAL; + } + + return rc; +} + +static int cam_icp_mgr_send_ping(struct cam_icp_hw_ctx_data *ctx_data) +{ + struct hfi_cmd_ping_pkt ping_pkt; + struct hfi_cmd_work_data *task_data; + unsigned long rem_jiffies; + int timeout = 5000; + struct crm_workq_task *task; + int rc = 0; + + task = cam_req_mgr_workq_get_task(icp_hw_mgr.cmd_work); + if (!task) { + CAM_ERR(CAM_ICP, "No free task to send ping command"); + return -ENOMEM; + } + + ping_pkt.size = sizeof(struct hfi_cmd_ping_pkt); + ping_pkt.pkt_type = HFI_CMD_SYS_PING; + ping_pkt.user_data = PTR_TO_U64(ctx_data); + init_completion(&ctx_data->wait_complete); + task_data = (struct hfi_cmd_work_data *)task->payload; + task_data->data = (void *)&ping_pkt; + task_data->request_id = 0; + task_data->type = ICP_WORKQ_TASK_CMD_TYPE; + task->process_cb = cam_icp_mgr_process_cmd; + + rc = cam_req_mgr_workq_enqueue_task(task, &icp_hw_mgr, + CRM_TASK_PRIORITY_0); + if (rc) + return rc; + + rem_jiffies = wait_for_completion_timeout(&ctx_data->wait_complete, + msecs_to_jiffies((timeout))); + if (!rem_jiffies) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_ICP, "FW response timed out %d", rc); + cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); + cam_hfi_queue_dump(); + } + + return rc; +} + +static int cam_icp_get_acquire_info(struct cam_icp_hw_mgr *hw_mgr, + struct cam_hw_acquire_args *args, + struct cam_icp_hw_ctx_data *ctx_data) +{ + int i; + int acquire_size; + struct cam_icp_acquire_dev_info icp_dev_acquire_info; + struct cam_icp_res_info *p_icp_out = NULL; + + if (copy_from_user(&icp_dev_acquire_info, + (void __user *)args->acquire_info, + sizeof(struct cam_icp_acquire_dev_info))) { + CAM_ERR(CAM_ICP, "Failed in acquire"); + return -EFAULT; + } + + if (icp_dev_acquire_info.secure_mode > CAM_SECURE_MODE_SECURE) { + CAM_ERR(CAM_ICP, "Invalid mode:%d", + icp_dev_acquire_info.secure_mode); + return -EINVAL; + } + + if ((icp_dev_acquire_info.num_out_res > ICP_MAX_OUTPUT_SUPPORTED) || + (icp_dev_acquire_info.num_out_res <= 0)) { + CAM_ERR(CAM_ICP, "Invalid num of out resources: %u", + icp_dev_acquire_info.num_out_res); + return -EINVAL; + } + + if (icp_dev_acquire_info.dev_type >= CAM_ICP_RES_TYPE_MAX) { + CAM_ERR(CAM_ICP, "Invalid device type: %d", + icp_dev_acquire_info.dev_type); + return -EFAULT; + } + + acquire_size = sizeof(struct cam_icp_acquire_dev_info) + + ((icp_dev_acquire_info.num_out_res - 1) * + sizeof(struct cam_icp_res_info)); + ctx_data->icp_dev_acquire_info = kzalloc(acquire_size, GFP_KERNEL); + if (!ctx_data->icp_dev_acquire_info) + return -ENOMEM; + + if (copy_from_user(ctx_data->icp_dev_acquire_info, + (void __user *)args->acquire_info, acquire_size)) { + CAM_ERR(CAM_ICP, "Failed in acquire: size = %d", acquire_size); + kfree(ctx_data->icp_dev_acquire_info); + ctx_data->icp_dev_acquire_info = NULL; + return -EFAULT; + } + + CAM_DBG(CAM_ICP, "%x %x %x %x %x %x %x", + ctx_data->icp_dev_acquire_info->dev_type, + ctx_data->icp_dev_acquire_info->in_res.format, + ctx_data->icp_dev_acquire_info->in_res.width, + ctx_data->icp_dev_acquire_info->in_res.height, + ctx_data->icp_dev_acquire_info->in_res.fps, + ctx_data->icp_dev_acquire_info->num_out_res, + ctx_data->icp_dev_acquire_info->scratch_mem_size); + + p_icp_out = ctx_data->icp_dev_acquire_info->out_res; + for (i = 0; i < icp_dev_acquire_info.num_out_res; i++) + CAM_DBG(CAM_ICP, "out[i] %x %x %x %x", + p_icp_out[i].format, + p_icp_out[i].width, + p_icp_out[i].height, + p_icp_out[i].fps); + + return 0; +} + +static uint32_t cam_icp_unify_dev_type( + uint32_t dev_type) +{ + switch (dev_type) { + case CAM_ICP_RES_TYPE_BPS: + return CAM_ICP_RES_TYPE_BPS; + case CAM_ICP_RES_TYPE_BPS_RT: + return CAM_ICP_RES_TYPE_BPS; + case CAM_ICP_RES_TYPE_BPS_SEMI_RT: + return CAM_ICP_RES_TYPE_BPS; + case CAM_ICP_RES_TYPE_IPE: + return CAM_ICP_RES_TYPE_IPE; + case CAM_ICP_RES_TYPE_IPE_RT: + return CAM_ICP_RES_TYPE_IPE; + case CAM_ICP_RES_TYPE_IPE_SEMI_RT: + return CAM_ICP_RES_TYPE_IPE; + default: + return CAM_ICP_RES_TYPE_MAX; + } +} + +static int cam_icp_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) +{ + int rc = 0, bitmap_size = 0; + uint32_t ctx_id = 0, dev_type; + dma_addr_t io_buf_addr; + size_t io_buf_size; + struct cam_icp_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_icp_hw_ctx_data *ctx_data = NULL; + struct cam_hw_acquire_args *args = acquire_hw_args; + struct cam_icp_acquire_dev_info *icp_dev_acquire_info; + struct cam_cmd_mem_regions cmd_mem_region; + + if ((!hw_mgr_priv) || (!acquire_hw_args)) { + CAM_ERR(CAM_ICP, "Invalid params: %pK %pK", hw_mgr_priv, + acquire_hw_args); + return -EINVAL; + } + + if (args->num_acq > 1) { + CAM_ERR(CAM_ICP, "number of resources are wrong: %u", + args->num_acq); + return -EINVAL; + } + + CAM_DBG(CAM_ICP, "ENTER"); + mutex_lock(&hw_mgr->hw_mgr_mutex); + ctx_id = cam_icp_mgr_get_free_ctx(hw_mgr); + if (ctx_id >= CAM_ICP_CTX_MAX) { + CAM_ERR(CAM_ICP, "No free ctx space in hw_mgr"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -ENOSPC; + } + ctx_data = &hw_mgr->ctx_data[ctx_id]; + ctx_data->ctx_id = ctx_id; + + mutex_lock(&ctx_data->ctx_mutex); + rc = cam_icp_get_acquire_info(hw_mgr, args, ctx_data); + if (rc) + goto acquire_info_failed; + + icp_dev_acquire_info = ctx_data->icp_dev_acquire_info; + dev_type = icp_dev_acquire_info->dev_type; + icp_dev_acquire_info->dev_type = + cam_icp_unify_dev_type(dev_type); + + CAM_DBG(CAM_ICP, "acquire io buf handle %d", + icp_dev_acquire_info->io_config_cmd_handle); + rc = cam_mem_get_io_buf( + icp_dev_acquire_info->io_config_cmd_handle, + hw_mgr->iommu_hdl, + &io_buf_addr, &io_buf_size); + if (rc) { + CAM_ERR(CAM_ICP, "unable to get src buf info from io desc"); + goto get_io_buf_failed; + } + + CAM_DBG(CAM_ICP, "hdl: %d, addr: %pK, size: %zu", + icp_dev_acquire_info->io_config_cmd_handle, + (void *)io_buf_addr, io_buf_size); + + if (!hw_mgr->ctxt_cnt) { + rc = cam_icp_clk_info_init(hw_mgr, ctx_data); + if (rc) + goto get_io_buf_failed; + + rc = cam_icp_mgr_icp_resume(hw_mgr); + if (rc) + goto get_io_buf_failed; + + if (icp_hw_mgr.a5_debug_type) + hfi_set_debug_level(icp_hw_mgr.a5_debug_type, + icp_hw_mgr.a5_dbg_lvl); + + hfi_set_fw_dump_level(icp_hw_mgr.a5_fw_dump_lvl); + + rc = cam_icp_send_ubwc_cfg(hw_mgr); + if (rc) + goto ubwc_cfg_failed; + } + + + rc = cam_icp_mgr_ipe_bps_resume(hw_mgr, ctx_data); + if (rc) + goto ipe_bps_resume_failed; + + rc = cam_icp_mgr_send_ping(ctx_data); + if (rc) { + CAM_ERR(CAM_ICP, "ping ack not received"); + goto send_ping_failed; + } + CAM_DBG(CAM_ICP, "ping ack received"); + + rc = cam_icp_mgr_create_handle(dev_type, + ctx_data); + if (rc) { + CAM_ERR(CAM_ICP, "create handle failed"); + goto create_handle_failed; + } + + CAM_DBG(CAM_ICP, + "created stream handle for dev_type %u", + dev_type); + + cmd_mem_region.num_regions = 1; + cmd_mem_region.map_info_array[0].mem_handle = + icp_dev_acquire_info->io_config_cmd_handle; + cmd_mem_region.map_info_array[0].offset = 0; + cmd_mem_region.map_info_array[0].size = + icp_dev_acquire_info->io_config_cmd_size; + cmd_mem_region.map_info_array[0].flags = 0; + + rc = cam_icp_process_stream_settings(ctx_data, + &cmd_mem_region, true); + if (rc) { + CAM_ERR(CAM_ICP, + "sending config io mapping failed rc %d", rc); + goto send_map_info_failed; + } + + rc = cam_icp_mgr_send_config_io(ctx_data, io_buf_addr); + if (rc) { + CAM_ERR(CAM_ICP, "IO Config command failed %d", rc); + cam_icp_dump_io_cfg(ctx_data, + icp_dev_acquire_info->io_config_cmd_handle); + goto ioconfig_failed; + } + + rc = cam_icp_process_stream_settings(ctx_data, + &cmd_mem_region, false); + if (rc) { + CAM_ERR(CAM_ICP, + "sending config io unmapping failed %d", rc); + goto send_map_info_failed; + } + + ctx_data->context_priv = args->context_data; + args->ctxt_to_hw_map = ctx_data; + + bitmap_size = BITS_TO_LONGS(CAM_FRAME_CMD_MAX) * sizeof(long); + ctx_data->hfi_frame_process.bitmap = + kzalloc(bitmap_size, GFP_KERNEL); + if (!ctx_data->hfi_frame_process.bitmap) + goto ioconfig_failed; + + ctx_data->hfi_frame_process.bits = bitmap_size * BITS_PER_BYTE; + hw_mgr->ctx_data[ctx_id].ctxt_event_cb = args->event_cb; + icp_dev_acquire_info->scratch_mem_size = ctx_data->scratch_mem_size; + + if (copy_to_user((void __user *)args->acquire_info, + icp_dev_acquire_info, sizeof(struct cam_icp_acquire_dev_info))) + goto copy_to_user_failed; + + cam_icp_ctx_clk_info_init(ctx_data); + ctx_data->state = CAM_ICP_CTX_STATE_ACQUIRED; + mutex_unlock(&ctx_data->ctx_mutex); + CAM_DBG(CAM_ICP, "scratch size = %x fw_handle = %x", + (unsigned int)icp_dev_acquire_info->scratch_mem_size, + (unsigned int)ctx_data->fw_handle); + /* Start device timer*/ + if (((hw_mgr->bps_ctxt_cnt == 1) || (hw_mgr->ipe_ctxt_cnt == 1))) + cam_icp_device_timer_start(hw_mgr); + /* Start context timer*/ + cam_icp_ctx_timer_start(ctx_data); + hw_mgr->ctxt_cnt++; + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + CAM_DBG(CAM_ICP, "Acquire Done for ctx_id %u dev type %d", + ctx_data->ctx_id, + ctx_data->icp_dev_acquire_info->dev_type); + + return 0; + +copy_to_user_failed: + kfree(ctx_data->hfi_frame_process.bitmap); + ctx_data->hfi_frame_process.bitmap = NULL; +ioconfig_failed: + cam_icp_process_stream_settings(ctx_data, + &cmd_mem_region, false); +send_map_info_failed: + cam_icp_mgr_destroy_handle(ctx_data); +create_handle_failed: +send_ping_failed: + cam_icp_mgr_ipe_bps_power_collapse(hw_mgr, ctx_data, 0); +ipe_bps_resume_failed: +ubwc_cfg_failed: + if (!hw_mgr->ctxt_cnt) + cam_icp_mgr_icp_power_collapse(hw_mgr); +get_io_buf_failed: + kfree(hw_mgr->ctx_data[ctx_id].icp_dev_acquire_info); + hw_mgr->ctx_data[ctx_id].icp_dev_acquire_info = NULL; +acquire_info_failed: + cam_icp_mgr_put_ctx(ctx_data); + cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); + mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static int cam_icp_mgr_get_hw_caps(void *hw_mgr_priv, void *hw_caps_args) +{ + int rc = 0; + struct cam_icp_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_query_cap_cmd *query_cap = hw_caps_args; + + if ((!hw_mgr_priv) || (!hw_caps_args)) { + CAM_ERR(CAM_ICP, "Invalid params: %pK %pK", + hw_mgr_priv, hw_caps_args); + return -EINVAL; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + if (copy_from_user(&icp_hw_mgr.icp_caps, + u64_to_user_ptr(query_cap->caps_handle), + sizeof(struct cam_icp_query_cap_cmd))) { + CAM_ERR(CAM_ICP, "copy_from_user failed"); + rc = -EFAULT; + goto end; + } + + rc = hfi_get_hw_caps(&icp_hw_mgr.icp_caps); + if (rc) + goto end; + + icp_hw_mgr.icp_caps.dev_iommu_handle.non_secure = hw_mgr->iommu_hdl; + icp_hw_mgr.icp_caps.dev_iommu_handle.secure = hw_mgr->iommu_sec_hdl; + + if (copy_to_user(u64_to_user_ptr(query_cap->caps_handle), + &icp_hw_mgr.icp_caps, sizeof(struct cam_icp_query_cap_cmd))) { + CAM_ERR(CAM_ICP, "copy_to_user failed"); + rc = -EFAULT; + } +end: + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static int cam_icp_mgr_alloc_devs(struct device_node *of_node) +{ + int rc; + uint32_t num_dev; + + rc = of_property_read_u32(of_node, "num-a5", &num_dev); + if (rc) { + CAM_ERR(CAM_ICP, "getting num of a5 failed"); + goto num_a5_failed; + } + + icp_hw_mgr.devices[CAM_ICP_DEV_A5] = kzalloc( + sizeof(struct cam_hw_intf *) * num_dev, GFP_KERNEL); + if (!icp_hw_mgr.devices[CAM_ICP_DEV_A5]) { + rc = -ENOMEM; + goto num_a5_failed; + } + + rc = of_property_read_u32(of_node, "num-ipe", &num_dev); + if (rc) { + CAM_ERR(CAM_ICP, "getting number of ipe dev nodes failed"); + goto num_ipe_failed; + } + + if (!icp_hw_mgr.ipe1_enable) + num_dev = 1; + + icp_hw_mgr.devices[CAM_ICP_DEV_IPE] = kcalloc(num_dev, + sizeof(struct cam_hw_intf *), GFP_KERNEL); + if (!icp_hw_mgr.devices[CAM_ICP_DEV_IPE]) { + rc = -ENOMEM; + goto num_ipe_failed; + } + + rc = of_property_read_u32(of_node, "num-bps", &num_dev); + if (rc) { + CAM_ERR(CAM_ICP, "read num bps devices failed"); + goto num_bps_failed; + } + icp_hw_mgr.devices[CAM_ICP_DEV_BPS] = kcalloc(num_dev, + sizeof(struct cam_hw_intf *), GFP_KERNEL); + if (!icp_hw_mgr.devices[CAM_ICP_DEV_BPS]) { + rc = -ENOMEM; + goto num_bps_failed; + } + + icp_hw_mgr.ipe_bps_pc_flag = of_property_read_bool(of_node, + "ipe_bps_pc_en"); + + icp_hw_mgr.icp_pc_flag = of_property_read_bool(of_node, + "icp_pc_en"); + + return 0; +num_bps_failed: + kfree(icp_hw_mgr.devices[CAM_ICP_DEV_IPE]); +num_ipe_failed: + kfree(icp_hw_mgr.devices[CAM_ICP_DEV_A5]); +num_a5_failed: + return rc; +} + +static int cam_icp_mgr_init_devs(struct device_node *of_node) +{ + int rc = 0; + int count, i; + const char *name = NULL; + struct device_node *child_node = NULL; + struct platform_device *child_pdev = NULL; + struct cam_hw_intf *child_dev_intf = NULL; + + rc = cam_icp_mgr_alloc_devs(of_node); + if (rc) + return rc; + + count = of_property_count_strings(of_node, "compat-hw-name"); + if (!count) { + CAM_ERR(CAM_ICP, "no compat hw found in dev tree, cnt = %d", + count); + rc = -EINVAL; + goto compat_hw_name_failed; + } + + for (i = 0; i < count; i++) { + rc = of_property_read_string_index(of_node, "compat-hw-name", + i, &name); + if (rc) { + CAM_ERR(CAM_ICP, "getting dev object name failed"); + goto compat_hw_name_failed; + } + + child_node = of_find_node_by_name(NULL, name); + if (!child_node) { + CAM_ERR(CAM_ICP, "Cannot find node in dtsi %s", name); + rc = -ENODEV; + goto compat_hw_name_failed; + } + + child_pdev = of_find_device_by_node(child_node); + if (!child_pdev) { + CAM_ERR(CAM_ICP, "failed to find device on bus %s", + child_node->name); + rc = -ENODEV; + of_node_put(child_node); + goto compat_hw_name_failed; + } + + child_dev_intf = (struct cam_hw_intf *)platform_get_drvdata( + child_pdev); + if (!child_dev_intf) { + CAM_ERR(CAM_ICP, "no child device"); + of_node_put(child_node); + if (!icp_hw_mgr.ipe1_enable) + continue; + goto compat_hw_name_failed; + } + icp_hw_mgr.devices[child_dev_intf->hw_type] + [child_dev_intf->hw_idx] = child_dev_intf; + + if (!child_dev_intf->hw_ops.process_cmd) + goto compat_hw_name_failed; + + of_node_put(child_node); + } + + icp_hw_mgr.a5_dev_intf = icp_hw_mgr.devices[CAM_ICP_DEV_A5][0]; + icp_hw_mgr.bps_dev_intf = icp_hw_mgr.devices[CAM_ICP_DEV_BPS][0]; + icp_hw_mgr.ipe0_dev_intf = icp_hw_mgr.devices[CAM_ICP_DEV_IPE][0]; + if (icp_hw_mgr.ipe1_enable) + icp_hw_mgr.ipe1_dev_intf = + icp_hw_mgr.devices[CAM_ICP_DEV_IPE][1]; + + return 0; +compat_hw_name_failed: + kfree(icp_hw_mgr.devices[CAM_ICP_DEV_BPS]); + kfree(icp_hw_mgr.devices[CAM_ICP_DEV_IPE]); + kfree(icp_hw_mgr.devices[CAM_ICP_DEV_A5]); + return rc; +} + +static int cam_icp_mgr_create_wq(void) +{ + int rc; + int i; + + rc = cam_req_mgr_workq_create("icp_command_queue", ICP_WORKQ_NUM_TASK, + &icp_hw_mgr.cmd_work, CRM_WORKQ_USAGE_NON_IRQ, + 0); + if (rc) { + CAM_ERR(CAM_ICP, "unable to create a command worker"); + goto cmd_work_failed; + } + + rc = cam_req_mgr_workq_create("icp_message_queue", ICP_WORKQ_NUM_TASK, + &icp_hw_mgr.msg_work, CRM_WORKQ_USAGE_IRQ, 0); + if (rc) { + CAM_ERR(CAM_ICP, "unable to create a message worker"); + goto msg_work_failed; + } + + rc = cam_req_mgr_workq_create("icp_timer_queue", ICP_WORKQ_NUM_TASK, + &icp_hw_mgr.timer_work, CRM_WORKQ_USAGE_IRQ, 0); + if (rc) { + CAM_ERR(CAM_ICP, "unable to create a timer worker"); + goto timer_work_failed; + } + + icp_hw_mgr.cmd_work_data = + kzalloc(sizeof(struct hfi_cmd_work_data) * ICP_WORKQ_NUM_TASK, + GFP_KERNEL); + if (!icp_hw_mgr.cmd_work_data) + goto cmd_work_data_failed; + + icp_hw_mgr.msg_work_data = + kzalloc(sizeof(struct hfi_msg_work_data) * ICP_WORKQ_NUM_TASK, + GFP_KERNEL); + if (!icp_hw_mgr.msg_work_data) + goto msg_work_data_failed; + + icp_hw_mgr.timer_work_data = + kzalloc(sizeof(struct hfi_msg_work_data) * ICP_WORKQ_NUM_TASK, + GFP_KERNEL); + if (!icp_hw_mgr.timer_work_data) + goto timer_work_data_failed; + + rc = cam_icp_hw_mgr_create_debugfs_entry(); + if (rc) + goto debugfs_create_failed; + + for (i = 0; i < ICP_WORKQ_NUM_TASK; i++) + icp_hw_mgr.msg_work->task.pool[i].payload = + &icp_hw_mgr.msg_work_data[i]; + + for (i = 0; i < ICP_WORKQ_NUM_TASK; i++) + icp_hw_mgr.cmd_work->task.pool[i].payload = + &icp_hw_mgr.cmd_work_data[i]; + + for (i = 0; i < ICP_WORKQ_NUM_TASK; i++) + icp_hw_mgr.timer_work->task.pool[i].payload = + &icp_hw_mgr.timer_work_data[i]; + return 0; + +debugfs_create_failed: + kfree(icp_hw_mgr.timer_work_data); +timer_work_data_failed: + kfree(icp_hw_mgr.msg_work_data); +msg_work_data_failed: + kfree(icp_hw_mgr.cmd_work_data); +cmd_work_data_failed: + cam_req_mgr_workq_destroy(&icp_hw_mgr.timer_work); +timer_work_failed: + cam_req_mgr_workq_destroy(&icp_hw_mgr.msg_work); +msg_work_failed: + cam_req_mgr_workq_destroy(&icp_hw_mgr.cmd_work); +cmd_work_failed: + return rc; +} + +static int cam_icp_mgr_cmd(void *hw_mgr_priv, void *cmd_args) +{ + int rc = 0; + struct cam_hw_cmd_args *hw_cmd_args = cmd_args; + struct cam_icp_hw_mgr *hw_mgr = hw_mgr_priv; + + if (!hw_mgr_priv || !cmd_args) { + CAM_ERR(CAM_ICP, "Invalid arguments"); + return -EINVAL; + } + + switch (hw_cmd_args->cmd_type) { + case CAM_HW_MGR_CMD_DUMP_PF_INFO: + cam_icp_mgr_print_io_bufs( + hw_cmd_args->u.pf_args.pf_data.packet, + hw_mgr->iommu_hdl, + hw_mgr->iommu_sec_hdl, + hw_cmd_args->u.pf_args.buf_info, + hw_cmd_args->u.pf_args.mem_found); + + break; + default: + CAM_ERR(CAM_ICP, "Invalid cmd"); + } + + return rc; +} + +int cam_icp_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, + int *iommu_hdl) +{ + int i, rc = 0; + struct cam_hw_mgr_intf *hw_mgr_intf; + struct cam_cpas_query_cap query; + uint32_t cam_caps, camera_hw_version; + + hw_mgr_intf = (struct cam_hw_mgr_intf *)hw_mgr_hdl; + if (!of_node || !hw_mgr_intf) { + CAM_ERR(CAM_ICP, "Invalid args of_node %pK hw_mgr %pK", + of_node, hw_mgr_intf); + return -EINVAL; + } + + hw_mgr_intf->hw_mgr_priv = &icp_hw_mgr; + hw_mgr_intf->hw_get_caps = cam_icp_mgr_get_hw_caps; + hw_mgr_intf->hw_acquire = cam_icp_mgr_acquire_hw; + hw_mgr_intf->hw_release = cam_icp_mgr_release_hw; + hw_mgr_intf->hw_prepare_update = cam_icp_mgr_prepare_hw_update; + hw_mgr_intf->hw_config_stream_settings = + cam_icp_mgr_config_stream_settings; + hw_mgr_intf->hw_config = cam_icp_mgr_config_hw; + hw_mgr_intf->hw_open = cam_icp_mgr_hw_open_u; + hw_mgr_intf->hw_close = cam_icp_mgr_hw_close_u; + hw_mgr_intf->hw_flush = cam_icp_mgr_hw_flush; + hw_mgr_intf->hw_cmd = cam_icp_mgr_cmd; + hw_mgr_intf->hw_dump = cam_icp_mgr_hw_dump; + + icp_hw_mgr.secure_mode = CAM_SECURE_MODE_NON_SECURE; + mutex_init(&icp_hw_mgr.hw_mgr_mutex); + spin_lock_init(&icp_hw_mgr.hw_mgr_lock); + + for (i = 0; i < CAM_ICP_CTX_MAX; i++) + mutex_init(&icp_hw_mgr.ctx_data[i].ctx_mutex); + + cam_cpas_get_hw_info(&query.camera_family, + &query.camera_version, &query.cpas_version, &cam_caps); + cam_cpas_get_cpas_hw_version(&camera_hw_version); + + if (camera_hw_version == CAM_CPAS_TITAN_480_V100) { + if (cam_caps & CPAS_TITAN_480_IPE0_BIT) + icp_hw_mgr.ipe0_enable = true; + if (cam_caps & CPAS_BPS_BIT) + icp_hw_mgr.bps_enable = true; + } else { + if (cam_caps & CPAS_IPE0_BIT) + icp_hw_mgr.ipe0_enable = true; + if (cam_caps & CPAS_IPE1_BIT) + icp_hw_mgr.ipe1_enable = true; + if (cam_caps & CPAS_BPS_BIT) + icp_hw_mgr.bps_enable = true; + } + + rc = cam_icp_mgr_init_devs(of_node); + if (rc) + goto dev_init_failed; + + rc = cam_smmu_get_handle("icp", &icp_hw_mgr.iommu_hdl); + if (rc) { + CAM_ERR(CAM_ICP, "get mmu handle failed: %d", rc); + goto icp_get_hdl_failed; + } + + rc = cam_smmu_get_handle("cam-secure", &icp_hw_mgr.iommu_sec_hdl); + if (rc) { + CAM_ERR(CAM_ICP, "get secure mmu handle failed: %d", rc); + goto secure_hdl_failed; + } + + rc = cam_icp_mgr_create_wq(); + if (rc) + goto icp_wq_create_failed; + + if (iommu_hdl) + *iommu_hdl = icp_hw_mgr.iommu_hdl; + + init_completion(&icp_hw_mgr.a5_complete); + return rc; + +icp_wq_create_failed: + cam_smmu_destroy_handle(icp_hw_mgr.iommu_sec_hdl); + icp_hw_mgr.iommu_sec_hdl = -1; +secure_hdl_failed: + cam_smmu_destroy_handle(icp_hw_mgr.iommu_hdl); + icp_hw_mgr.iommu_hdl = -1; +icp_get_hdl_failed: + kfree(icp_hw_mgr.devices[CAM_ICP_DEV_BPS]); + kfree(icp_hw_mgr.devices[CAM_ICP_DEV_IPE]); + kfree(icp_hw_mgr.devices[CAM_ICP_DEV_A5]); +dev_init_failed: + mutex_destroy(&icp_hw_mgr.hw_mgr_mutex); + for (i = 0; i < CAM_ICP_CTX_MAX; i++) + mutex_destroy(&icp_hw_mgr.ctx_data[i].ctx_mutex); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h new file mode 100644 index 0000000000000000000000000000000000000000..c438d438e8921dc5fa479eb69065fc49ca6294fa --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h @@ -0,0 +1,409 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_ICP_HW_MGR_H +#define CAM_ICP_HW_MGR_H + +#include +#include +#include +#include "cam_icp_hw_intf.h" +#include "cam_hw_mgr_intf.h" +#include "cam_hw_intf.h" +#include "cam_a5_hw_intf.h" +#include "hfi_session_defs.h" +#include "cam_req_mgr_workq.h" +#include "cam_mem_mgr.h" +#include "cam_smmu_api.h" +#include "cam_soc_util.h" +#include "cam_req_mgr_timer.h" + +#define CAM_ICP_ROLE_PARENT 1 +#define CAM_ICP_ROLE_CHILD 2 + +#define CAM_FRAME_CMD_MAX 20 + +#define CAM_MAX_OUT_RES 6 +#define CAM_MAX_IN_RES 8 + +#define ICP_WORKQ_NUM_TASK 100 +#define ICP_WORKQ_TASK_CMD_TYPE 1 +#define ICP_WORKQ_TASK_MSG_TYPE 2 + +#define ICP_PACKET_SIZE 0 +#define ICP_PACKET_TYPE 1 +#define ICP_PACKET_OPCODE 2 +#define ICP_MAX_OUTPUT_SUPPORTED 6 + +#define ICP_FRAME_PROCESS_SUCCESS 0 +#define ICP_FRAME_PROCESS_FAILURE 1 +#define ICP_MSG_BUF_SIZE 256 +#define ICP_DBG_BUF_SIZE 102400 + +#define ICP_CLK_HW_IPE 0x0 +#define ICP_CLK_HW_BPS 0x1 +#define ICP_CLK_HW_MAX 0x2 + +#define ICP_OVER_CLK_THRESHOLD 5 + +#define CPAS_IPE0_BIT 0x1000 +#define CPAS_IPE1_BIT 0x2000 +#define CPAS_BPS_BIT 0x400 +#define CPAS_TITAN_480_IPE0_BIT 0x800 + +#define ICP_PWR_CLP_BPS 0x00000001 +#define ICP_PWR_CLP_IPE0 0x00010000 +#define ICP_PWR_CLP_IPE1 0x00020000 + +#define CAM_ICP_CTX_STATE_FREE 0x0 +#define CAM_ICP_CTX_STATE_IN_USE 0x1 +#define CAM_ICP_CTX_STATE_ACQUIRED 0x2 +#define CAM_ICP_CTX_STATE_RELEASE 0x3 + +#define CAM_ICP_CTX_MAX_CMD_BUFFERS 0x2 + +/* Current appliacble vote paths, based on number of UAPI definitions */ +#define CAM_ICP_MAX_PER_PATH_VOTES 6 + +/* + * Response time threshold in ms beyond which a request is not expected + * to be with ICP hw + */ +#define CAM_ICP_CTX_RESPONSE_TIME_THRESHOLD 300000 + +/** + * struct icp_hfi_mem_info + * @qtbl: Memory info of queue table + * @cmd_q: Memory info of command queue + * @msg_q: Memory info of message queue + * @dbg_q: Memory info of debug queue + * @sec_heap: Memory info of secondary heap + * @fw_buf: Memory info of firmware + * @qdss_buf: Memory info of qdss + * @sfr_buf: Memory info for sfr buffer + * @shmem: Memory info for shared region + * @io_mem: Memory info for io region + */ +struct icp_hfi_mem_info { + struct cam_mem_mgr_memory_desc qtbl; + struct cam_mem_mgr_memory_desc cmd_q; + struct cam_mem_mgr_memory_desc msg_q; + struct cam_mem_mgr_memory_desc dbg_q; + struct cam_mem_mgr_memory_desc sec_heap; + struct cam_mem_mgr_memory_desc fw_buf; + struct cam_mem_mgr_memory_desc qdss_buf; + struct cam_mem_mgr_memory_desc sfr_buf; + struct cam_smmu_region_info shmem; + struct cam_smmu_region_info io_mem; +}; + +/** + * struct hfi_cmd_work_data + * @type: Task type + * @data: Pointer to command data + * @request_id: Request id + */ +struct hfi_cmd_work_data { + uint32_t type; + void *data; + int32_t request_id; +}; + +/** + * struct hfi_msg_work_data + * @type: Task type + * @data: Pointer to message data + * @irq_status: IRQ status + */ +struct hfi_msg_work_data { + uint32_t type; + void *data; + uint32_t irq_status; +}; + +/** + * struct clk_work_data + * @type: Task type + * @data: Pointer to clock info + */ +struct clk_work_data { + uint32_t type; + void *data; +}; + +/* + * struct icp_frame_info + * @request_id: request id + * @io_config: the address of io config + * @hfi_cfg_io_cmd: command struct to be sent to hfi + */ +struct icp_frame_info { + uint64_t request_id; + dma_addr_t io_config; + struct hfi_cmd_ipebps_async hfi_cfg_io_cmd; +}; + +/** + * struct cam_icp_clk_bw_request_v2 + * + * @budget_ns: Time required to process frame + * @frame_cycles: Frame cycles needed to process the frame + * @rt_flag: Flag to indicate real time stream + * @reserved: Reserved filed. + * @num_paths: Number of paths for per path bw vote + * @axi_path: Per path vote info for IPE/BPS + */ +struct cam_icp_clk_bw_req_internal_v2 { + uint64_t budget_ns; + uint32_t frame_cycles; + uint32_t rt_flag; + uint32_t reserved; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[CAM_ICP_MAX_PER_PATH_VOTES]; +}; + +/** + * struct hfi_frame_process_info + * @hfi_frame_cmd: Frame process command info + * @bitmap: Bitmap for hfi_frame_cmd + * @bits: Used in hfi_frame_cmd bitmap + * @lock: Lock for hfi_frame_cmd + * @request_id: Request id list + * @num_out_resources: Number of out syncs + * @out_resource: Out sync info + * @fw_process_flag: Frame process flag + * @clk_info: Clock information for a request + * @clk_info_v2: Clock info for AXI bw voting v2 + * @frame_info: information needed to process request + * @submit_timestamp: Submit timestamp to hw + */ +struct hfi_frame_process_info { + struct hfi_cmd_ipebps_async hfi_frame_cmd[CAM_FRAME_CMD_MAX]; + void *bitmap; + size_t bits; + struct mutex lock; + uint64_t request_id[CAM_FRAME_CMD_MAX]; + uint32_t num_out_resources[CAM_FRAME_CMD_MAX]; + uint32_t out_resource[CAM_FRAME_CMD_MAX][CAM_MAX_OUT_RES]; + uint32_t in_resource[CAM_FRAME_CMD_MAX]; + uint32_t in_free_resource[CAM_FRAME_CMD_MAX]; + uint32_t fw_process_flag[CAM_FRAME_CMD_MAX]; + struct cam_icp_clk_bw_request clk_info[CAM_FRAME_CMD_MAX]; + struct cam_icp_clk_bw_req_internal_v2 clk_info_v2[CAM_FRAME_CMD_MAX]; + struct icp_frame_info frame_info[CAM_FRAME_CMD_MAX]; + ktime_t submit_timestamp[CAM_FRAME_CMD_MAX]; +}; + +/** + * struct cam_ctx_clk_info + * @curr_fc: Context latest request frame cycles + * @rt_flag: Flag to indicate real time request + * @base_clk: Base clock to process the request + * @reserved: Reserved field + * #uncompressed_bw: Current bandwidth voting + * @compressed_bw: Current compressed bandwidth voting + * @clk_rate: Supported clock rates for the context + * @num_paths: Number of valid AXI paths + * @axi_path: ctx based per path bw vote + */ +struct cam_ctx_clk_info { + uint32_t curr_fc; + uint32_t rt_flag; + uint32_t base_clk; + uint32_t reserved; + uint64_t uncompressed_bw; + uint64_t compressed_bw; + int32_t clk_rate[CAM_MAX_VOTE]; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[CAM_ICP_MAX_PER_PATH_VOTES]; +}; +/** + * struct cam_icp_hw_ctx_data + * @context_priv: Context private data + * @ctx_mutex: Mutex for context + * @fw_handle: Firmware handle + * @scratch_mem_size: Scratch memory size + * @acquire_dev_cmd: Acquire command + * @icp_dev_acquire_info: Acquire device info + * @ctxt_event_cb: Context callback function + * @state: context state + * @role: Role of a context in case of chaining + * @chain_ctx: Peer context + * @hfi_frame_process: Frame process command + * @wait_complete: Completion info + * @temp_payload: Payload for destroy handle data + * @ctx_id: Context Id + * @bw_config_version: BW config version indicator + * @clk_info: Current clock info of a context + * @watch_dog: watchdog timer handle + * @watch_dog_reset_counter: Counter for watch dog reset + * @icp_dev_io_info: io config resource + * @last_flush_req: last flush req for this ctx + */ +struct cam_icp_hw_ctx_data { + void *context_priv; + struct mutex ctx_mutex; + uint32_t fw_handle; + uint32_t scratch_mem_size; + struct cam_acquire_dev_cmd acquire_dev_cmd; + struct cam_icp_acquire_dev_info *icp_dev_acquire_info; + cam_hw_event_cb_func ctxt_event_cb; + uint32_t state; + uint32_t role; + struct cam_icp_hw_ctx_data *chain_ctx; + struct hfi_frame_process_info hfi_frame_process; + struct completion wait_complete; + struct ipe_bps_destroy temp_payload; + uint32_t ctx_id; + uint32_t bw_config_version; + struct cam_ctx_clk_info clk_info; + struct cam_req_mgr_timer *watch_dog; + uint32_t watch_dog_reset_counter; + struct cam_icp_acquire_dev_info icp_dev_io_info; + uint64_t last_flush_req; +}; + +/** + * struct icp_cmd_generic_blob + * @ctx: Current context info + * @frame_info_idx: Index used for frame process info + * @io_buf_addr: pointer to io buffer address + */ +struct icp_cmd_generic_blob { + struct cam_icp_hw_ctx_data *ctx; + uint32_t frame_info_idx; + dma_addr_t *io_buf_addr; +}; + +/** + * struct cam_icp_clk_info + * @base_clk: Base clock to process request + * @curr_clk: Current clock of hadrware + * @threshold: Threshold for overclk count + * @over_clked: Over clock count + * @uncompressed_bw: Current bandwidth voting + * @compressed_bw: Current compressed bandwidth voting + * @num_paths: Number of AXI vote paths + * @axi_path: Current per path bw vote info + * @hw_type: IPE/BPS device type + * @watch_dog: watchdog timer handle + * @watch_dog_reset_counter: Counter for watch dog reset + */ +struct cam_icp_clk_info { + uint32_t base_clk; + uint32_t curr_clk; + uint32_t threshold; + uint32_t over_clked; + uint64_t uncompressed_bw; + uint64_t compressed_bw; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[CAM_ICP_MAX_PER_PATH_VOTES]; + uint32_t hw_type; + struct cam_req_mgr_timer *watch_dog; + uint32_t watch_dog_reset_counter; +}; + +/** + * struct cam_icp_hw_mgr + * @hw_mgr_mutex: Mutex for ICP hardware manager + * @hw_mgr_lock: Spinlock for ICP hardware manager + * @devices: Devices of ICP hardware manager + * @ctx_data: Context data + * @icp_caps: ICP capabilities + * @fw_download: Firmware download state + * @iommu_hdl: Non secure IOMMU handle + * @iommu_sec_hdl: Secure IOMMU handle + * @hfi_mem: Memory for hfi + * @cmd_work: Work queue for hfi commands + * @msg_work: Work queue for hfi messages + * @timer_work: Work queue for timer watchdog + * @msg_buf: Buffer for message data from firmware + * @dbg_buf: Buffer for debug data from firmware + * @a5_complete: Completion info + * @cmd_work_data: Pointer to command work queue task + * @msg_work_data: Pointer to message work queue task + * @timer_work_data: Pointer to timer work queue task + * @ctxt_cnt: Active context count + * @ipe_ctxt_cnt: IPE Active context count + * @bps_ctxt_cnt: BPS Active context count + * @dentry: Debugfs entry + * @a5_debug: A5 debug flag + * @icp_pc_flag: Flag to enable/disable power collapse + * @ipe_bps_pc_flag: Flag to enable/disable + * power collapse for ipe & bps + * @icp_debug_clk: Set clock based on debug value + * @icp_default_clk: Set this clok if user doesn't supply + * @clk_info: Clock info of hardware + * @secure_mode: Flag to enable/disable secure camera + * @a5_jtag_debug: entry to enable A5 JTAG debugging + * @a5_debug_type : entry to enable FW debug message/qdss + * @a5_dbg_lvl : debug level set to FW. + * @a5_fw_dump_lvl : level set for dumping the FW data + * @ipe0_enable: Flag for IPE0 + * @ipe1_enable: Flag for IPE1 + * @bps_enable: Flag for BPS + * @a5_dev_intf : Device interface for A5 + * @ipe0_dev_intf: Device interface for IPE0 + * @ipe1_dev_intf: Device interface for IPE1 + * @bps_dev_intf: Device interface for BPS + * @ipe_clk_state: IPE clock state flag + * @bps_clk_state: BPS clock state flag + * @recovery: Flag to validate if in previous session FW + * reported a fatal error or wdt. If set FW is + * re-downloaded for new camera session. + */ +struct cam_icp_hw_mgr { + struct mutex hw_mgr_mutex; + spinlock_t hw_mgr_lock; + + struct cam_hw_intf **devices[CAM_ICP_DEV_MAX]; + struct cam_icp_hw_ctx_data ctx_data[CAM_ICP_CTX_MAX]; + struct cam_icp_query_cap_cmd icp_caps; + + bool fw_download; + int32_t iommu_hdl; + int32_t iommu_sec_hdl; + struct icp_hfi_mem_info hfi_mem; + struct cam_req_mgr_core_workq *cmd_work; + struct cam_req_mgr_core_workq *msg_work; + struct cam_req_mgr_core_workq *timer_work; + uint32_t msg_buf[ICP_MSG_BUF_SIZE]; + uint32_t dbg_buf[ICP_DBG_BUF_SIZE]; + struct completion a5_complete; + struct hfi_cmd_work_data *cmd_work_data; + struct hfi_msg_work_data *msg_work_data; + struct hfi_msg_work_data *timer_work_data; + uint32_t ctxt_cnt; + uint32_t ipe_ctxt_cnt; + uint32_t bps_ctxt_cnt; + struct dentry *dentry; + bool a5_debug; + bool icp_pc_flag; + bool ipe_bps_pc_flag; + uint64_t icp_debug_clk; + uint64_t icp_default_clk; + struct cam_icp_clk_info clk_info[ICP_CLK_HW_MAX]; + bool secure_mode; + bool a5_jtag_debug; + u64 a5_debug_type; + u64 a5_dbg_lvl; + u64 a5_fw_dump_lvl; + bool ipe0_enable; + bool ipe1_enable; + bool bps_enable; + struct cam_hw_intf *a5_dev_intf; + struct cam_hw_intf *ipe0_dev_intf; + struct cam_hw_intf *ipe1_dev_intf; + struct cam_hw_intf *bps_dev_intf; + bool ipe_clk_state; + bool bps_clk_state; + atomic_t recovery; +}; + +static int cam_icp_mgr_hw_close(void *hw_priv, void *hw_close_args); +static int cam_icp_mgr_hw_open(void *hw_mgr_priv, void *download_fw_args); +static int cam_icp_mgr_icp_resume(struct cam_icp_hw_mgr *hw_mgr); +static int cam_icp_mgr_icp_power_collapse(struct cam_icp_hw_mgr *hw_mgr); +#endif /* CAM_ICP_HW_MGR_H */ diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_a5_hw_intf.h b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_a5_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..c3fefdc09ba9421dca40ebf0aa25fc813f663b4d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_a5_hw_intf.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_A5_HW_INTF_H +#define CAM_A5_HW_INTF_H + +#include +#include +#include +#include "cam_hw_mgr_intf.h" +#include "cam_icp_hw_intf.h" + +enum cam_icp_a5_cmd_type { + CAM_ICP_A5_CMD_FW_DOWNLOAD, + CAM_ICP_A5_CMD_POWER_COLLAPSE, + CAM_ICP_A5_CMD_POWER_RESUME, + CAM_ICP_A5_CMD_SET_FW_BUF, + CAM_ICP_A5_CMD_ACQUIRE, + CAM_ICP_A5_SET_IRQ_CB, + CAM_ICP_A5_TEST_IRQ, + CAM_ICP_A5_SEND_INIT, + CAM_ICP_A5_CMD_VOTE_CPAS, + CAM_ICP_A5_CMD_CPAS_START, + CAM_ICP_A5_CMD_CPAS_STOP, + CAM_ICP_A5_CMD_UBWC_CFG, + CAM_ICP_A5_CMD_PC_PREP, + CAM_ICP_A5_CMD_CLK_UPDATE, + CAM_ICP_A5_CMD_HW_DUMP, + CAM_ICP_A5_CMD_MAX, +}; + +struct cam_icp_a5_set_fw_buf_info { + uint32_t iova; + uint64_t kva; + uint64_t len; +}; + +/** + * struct cam_icp_a5_query_cap - ICP query device capability payload + * @fw_version: firmware version info + * @api_version: api version info + * @num_ipe: number of ipes + * @num_bps: number of bps + * @num_dev: number of device capabilities in dev_caps + * @reserved: reserved + * @dev_ver: returned device capability array + * @CAM_QUERY_CAP IOCTL + */ +struct cam_icp_a5_query_cap { + struct cam_icp_ver fw_version; + struct cam_icp_ver api_version; + uint32_t num_ipe; + uint32_t num_bps; + uint32_t num_dev; + uint32_t reserved; + struct cam_icp_dev_ver dev_ver[CAM_ICP_DEV_TYPE_MAX]; +}; + +struct cam_icp_a5_acquire_dev { + uint32_t ctx_id; + struct cam_icp_acquire_dev_info icp_acquire_info; + struct cam_icp_res_info icp_out_acquire_info[2]; + uint32_t fw_handle; +}; + +struct cam_icp_a5_set_irq_cb { + int32_t (*icp_hw_mgr_cb)(uint32_t irq_status, void *data); + void *data; +}; + +struct cam_icp_a5_test_irq { + uint32_t test_irq; +}; +#endif /* CAM_A5_HW_INTF_H */ diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_bps_hw_intf.h b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_bps_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..f2628e41640b757d75000b93f045f5fb62511759 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_bps_hw_intf.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_BPS_HW_INTF_H +#define CAM_BPS_HW_INTF_H + +#include +#include +#include "cam_hw_mgr_intf.h" +#include "cam_icp_hw_intf.h" + +/* BPS register */ +#define BPS_TOP_RST_CMD 0x1008 +#define BPS_CDM_RST_CMD 0x10 +#define BPS_CDM_IRQ_STATUS 0x44 +#define BPS_TOP_IRQ_STATUS 0x100C + +/* BPS CDM/TOP status register */ +#define BPS_RST_DONE_IRQ_STATUS_BIT 0x1 + +enum cam_icp_bps_cmd_type { + CAM_ICP_BPS_CMD_FW_DOWNLOAD, + CAM_ICP_BPS_CMD_POWER_COLLAPSE, + CAM_ICP_BPS_CMD_POWER_RESUME, + CAM_ICP_BPS_CMD_SET_FW_BUF, + CAM_ICP_BPS_CMD_VOTE_CPAS, + CAM_ICP_BPS_CMD_CPAS_START, + CAM_ICP_BPS_CMD_CPAS_STOP, + CAM_ICP_BPS_CMD_UPDATE_CLK, + CAM_ICP_BPS_CMD_DISABLE_CLK, + CAM_ICP_BPS_CMD_RESET, + CAM_ICP_BPS_CMD_MAX, +}; + +#endif /* CAM_BPS_HW_INTF_H */ diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_icp_hw_intf.h b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_icp_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..80a724b53d9479bbb351def8e7a975465de12481 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_icp_hw_intf.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_ICP_HW_INTF_H +#define CAM_ICP_HW_INTF_H + +#define CAM_ICP_CMD_BUF_MAX_SIZE 128 +#define CAM_ICP_MSG_BUF_MAX_SIZE CAM_ICP_CMD_BUF_MAX_SIZE + +#define CAM_ICP_BW_CONFIG_UNKNOWN 0 +#define CAM_ICP_BW_CONFIG_V1 1 +#define CAM_ICP_BW_CONFIG_V2 2 + +enum cam_a5_hw_type { + CAM_ICP_DEV_A5, + CAM_ICP_DEV_IPE, + CAM_ICP_DEV_BPS, + CAM_ICP_DEV_MAX, +}; + +/** + * struct cam_a5_clk_update_cmd - Payload for hw manager command + * + * @curr_clk_rate: clk rate to HW + * @ipe_bps_pc_enable power collpase enable flag + * @clk_level: clk level corresponding to the clk rate + * populated as output while the clk is being + * updated to the given rate + */ +struct cam_a5_clk_update_cmd { + uint32_t curr_clk_rate; + bool ipe_bps_pc_enable; + int32_t clk_level; +}; + +#endif diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_ipe_hw_intf.h b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_ipe_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..ea14ee623fb3b46fbd079f2bf47170fe53ad6d65 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_ipe_hw_intf.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_IPE_HW_INTF_H +#define CAM_IPE_HW_INTF_H + +#include +#include +#include "cam_hw_mgr_intf.h" +#include "cam_icp_hw_intf.h" + +/* IPE registers */ +#define IPE_TOP_RST_CMD 0x1008 +#define IPE_CDM_RST_CMD 0x10 +#define IPE_CDM_IRQ_STATUS 0x44 +#define IPE_TOP_IRQ_STATUS 0x100C + +/* IPE CDM/TOP status register */ +#define IPE_RST_DONE_IRQ_STATUS_BIT 0x1 + +enum cam_icp_ipe_cmd_type { + CAM_ICP_IPE_CMD_FW_DOWNLOAD, + CAM_ICP_IPE_CMD_POWER_COLLAPSE, + CAM_ICP_IPE_CMD_POWER_RESUME, + CAM_ICP_IPE_CMD_SET_FW_BUF, + CAM_ICP_IPE_CMD_VOTE_CPAS, + CAM_ICP_IPE_CMD_CPAS_START, + CAM_ICP_IPE_CMD_CPAS_STOP, + CAM_ICP_IPE_CMD_UPDATE_CLK, + CAM_ICP_IPE_CMD_DISABLE_CLK, + CAM_ICP_IPE_CMD_RESET, + CAM_ICP_IPE_CMD_MAX, +}; + +#endif /* CAM_IPE_HW_INTF_H */ diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/include/cam_icp_hw_mgr_intf.h b/techpack/camera-bengal/drivers/cam_icp/icp_hw/include/cam_icp_hw_mgr_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..84129cba7e19f2da681d82e5f683122d3b22e5c2 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/include/cam_icp_hw_mgr_intf.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_ICP_HW_MGR_INTF_H +#define CAM_ICP_HW_MGR_INTF_H + +#include +#include +#include +#include "cam_cpas_api.h" + +#define ICP_CLK_TURBO_HZ 600000000 +#define ICP_CLK_SVS_HZ 400000000 + +#define CAM_ICP_A5_BW_BYTES_VOTE 40000000 + +#define CAM_ICP_CTX_MAX 54 + +#define CPAS_IPE1_BIT 0x2000 + +#define CAM_IPE_DEFAULT_AXI_PATH CAM_AXI_PATH_DATA_IPE_WR_VID +#define CAM_IPE_DEFAULT_AXI_TRANSAC CAM_AXI_TRANSACTION_WRITE +#define CAM_BPS_DEFAULT_AXI_PATH CAM_AXI_PATH_DATA_ALL +#define CAM_BPS_DEFAULT_AXI_TRANSAC CAM_AXI_TRANSACTION_WRITE +#define CAM_ICP_DEFAULT_AXI_PATH CAM_AXI_PATH_DATA_ALL +#define CAM_ICP_DEFAULT_AXI_TRANSAC CAM_AXI_TRANSACTION_READ + +#define CAM_ICP_DUMP_TAG_MAX_LEN 32 +#define CAM_ICP_DUMP_NUM_WORDS 5 + +int cam_icp_hw_mgr_init(struct device_node *of_node, + uint64_t *hw_mgr_hdl, int *iommu_hdl); + +/** + * struct cam_icp_cpas_vote + * @ahb_vote: AHB vote info + * @axi_vote: AXI vote info + * @ahb_vote_valid: Flag for ahb vote data + * @axi_vote_valid: flag for axi vote data + */ +struct cam_icp_cpas_vote { + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote; + uint32_t ahb_vote_valid; + uint32_t axi_vote_valid; +}; + +/** + * struct cam_icp_hw_dump_args + * @cpu_addr: kernel vaddr + * @buf_len: buffer length + * @offset: offset + */ +struct cam_icp_hw_dump_args { + uintptr_t cpu_addr; + size_t buf_len; + size_t offset; +}; + +/** + * struct cam_icp_dump_header + * @tag: tag of the packet + * @size: size of data in packet + * @word_size: size of each word in packet + */ +struct cam_icp_dump_header { + uint8_t tag[CAM_ICP_DUMP_TAG_MAX_LEN]; + uint64_t size; + int32_t word_size; +}; + +#endif /* CAM_ICP_HW_MGR_INTF_H */ diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/Makefile b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..cc0916b5fe0c92fc396de37e9bb5702ed8e17857 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/fw_inc +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += ipe_dev.o ipe_core.o ipe_soc.o diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c new file mode 100644 index 0000000000000000000000000000000000000000..4263cf7ea669a4b312cc03901f15d7019b846032 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_io_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "ipe_core.h" +#include "ipe_soc.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_ipe_hw_intf.h" +#include "cam_icp_hw_mgr_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "hfi_reg.h" + +#define HFI_MAX_POLL_TRY 5 + +static int cam_ipe_cpas_vote(struct cam_ipe_device_core_info *core_info, + struct cam_icp_cpas_vote *cpas_vote) +{ + int rc = 0; + + if (cpas_vote->ahb_vote_valid) + rc = cam_cpas_update_ahb_vote(core_info->cpas_handle, + &cpas_vote->ahb_vote); + if (cpas_vote->axi_vote_valid) + rc = cam_cpas_update_axi_vote(core_info->cpas_handle, + &cpas_vote->axi_vote); + + if (rc) + CAM_ERR(CAM_PERF, "cpas vote is failed: %d", rc); + + return rc; +} + +int cam_ipe_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *ipe_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ipe_device_core_info *core_info = NULL; + struct cam_icp_cpas_vote cpas_vote; + int rc = 0; + + if (!device_priv) { + CAM_ERR(CAM_ICP, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &ipe_dev->soc_info; + core_info = (struct cam_ipe_device_core_info *)ipe_dev->core_info; + + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_ICP, "soc_info = %pK core_info = %pK", + soc_info, core_info); + return -EINVAL; + } + + cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE; + cpas_vote.ahb_vote.vote.level = CAM_LOWSVS_VOTE; + cpas_vote.axi_vote.num_paths = 1; + cpas_vote.axi_vote.axi_path[0].path_data_type = + CAM_IPE_DEFAULT_AXI_PATH; + cpas_vote.axi_vote.axi_path[0].transac_type = + CAM_IPE_DEFAULT_AXI_TRANSAC; + cpas_vote.axi_vote.axi_path[0].camnoc_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].mnoc_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].mnoc_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].ddr_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].ddr_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + + rc = cam_cpas_start(core_info->cpas_handle, + &cpas_vote.ahb_vote, &cpas_vote.axi_vote); + if (rc) { + CAM_ERR(CAM_ICP, "cpas start failed: %d", rc); + goto error; + } + core_info->cpas_start = true; + + rc = cam_ipe_enable_soc_resources(soc_info); + if (rc) { + CAM_ERR(CAM_ICP, "soc enable is failed : %d", rc); + if (cam_cpas_stop(core_info->cpas_handle)) + CAM_ERR(CAM_ICP, "cpas stop is failed"); + else + core_info->cpas_start = false; + } else { + core_info->clk_enable = true; + } + +error: + return rc; +} + +int cam_ipe_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *ipe_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ipe_device_core_info *core_info = NULL; + int rc = 0; + + if (!device_priv) { + CAM_ERR(CAM_ICP, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &ipe_dev->soc_info; + core_info = (struct cam_ipe_device_core_info *)ipe_dev->core_info; + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_ICP, "soc_info = %pK core_info = %pK", + soc_info, core_info); + return -EINVAL; + } + + rc = cam_ipe_disable_soc_resources(soc_info, core_info->clk_enable); + if (rc) + CAM_ERR(CAM_ICP, "soc disable is failed : %d", rc); + core_info->clk_enable = false; + + if (core_info->cpas_start) { + if (cam_cpas_stop(core_info->cpas_handle)) + CAM_ERR(CAM_ICP, "cpas stop is failed"); + else + core_info->cpas_start = false; + } + + return rc; +} + +static int cam_ipe_handle_pc(struct cam_hw_info *ipe_dev) +{ + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ipe_device_core_info *core_info = NULL; + struct cam_ipe_device_hw_info *hw_info = NULL; + int pwr_ctrl; + int pwr_status; + + soc_info = &ipe_dev->soc_info; + core_info = (struct cam_ipe_device_core_info *)ipe_dev->core_info; + hw_info = core_info->ipe_hw_info; + + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, + true, &pwr_ctrl); + if (!(pwr_ctrl & IPE_COLLAPSE_MASK)) { + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, + true, &pwr_status); + cam_cpas_reg_write(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, + hw_info->pwr_ctrl, true, 0x1); + + if (pwr_status >> IPE_PWR_ON_MASK) + CAM_WARN(CAM_PERF, "BPS: pwr_status(%x):pwr_ctrl(%x)", + pwr_status, pwr_ctrl); + + } + cam_ipe_get_gdsc_control(soc_info); + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, + true, &pwr_ctrl); + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, + true, &pwr_status); + CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x", + pwr_ctrl, pwr_status); + + return 0; +} + +static int cam_ipe_handle_resume(struct cam_hw_info *ipe_dev) +{ + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ipe_device_core_info *core_info = NULL; + struct cam_ipe_device_hw_info *hw_info = NULL; + int pwr_ctrl; + int pwr_status; + int rc = 0; + + soc_info = &ipe_dev->soc_info; + core_info = (struct cam_ipe_device_core_info *)ipe_dev->core_info; + hw_info = core_info->ipe_hw_info; + + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, + true, &pwr_ctrl); + if (pwr_ctrl & IPE_COLLAPSE_MASK) { + CAM_DBG(CAM_PERF, "IPE pwr_ctrl set(%x)", pwr_ctrl); + cam_cpas_reg_write(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, + hw_info->pwr_ctrl, true, 0); + } + + rc = cam_ipe_transfer_gdsc_control(soc_info); + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl); + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, + true, &pwr_status); + CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x", + pwr_ctrl, pwr_status); + + return rc; +} + +static int cam_ipe_cmd_reset(struct cam_hw_soc_info *soc_info, + struct cam_ipe_device_core_info *core_info) +{ + int pwr_ctrl, pwr_status, rc = 0; + uint32_t status = 0, retry_cnt = 0; + bool reset_ipe_cdm_fail = false; + bool reset_ipe_top_fail = false; + + CAM_DBG(CAM_ICP, "CAM_ICP_IPE_CMD_RESET"); + if (!core_info->clk_enable || !core_info->cpas_start) { + CAM_ERR(CAM_HFI, "IPE reset failed. clk_en %d cpas_start %d", + core_info->clk_enable, core_info->cpas_start); + return -EINVAL; + } + + /* IPE CDM core reset*/ + cam_io_w_mb((uint32_t)0xF, + soc_info->reg_map[0].mem_base + IPE_CDM_RST_CMD); + while (retry_cnt < HFI_MAX_POLL_TRY) { + readw_poll_timeout((soc_info->reg_map[0].mem_base + + IPE_CDM_IRQ_STATUS), + status, ((status & IPE_RST_DONE_IRQ_STATUS_BIT) == 0x1), + 100, 10000); + + CAM_DBG(CAM_HFI, "ipe_cdm_irq_status = %u", status); + + if ((status & IPE_RST_DONE_IRQ_STATUS_BIT) == 0x1) + break; + retry_cnt++; + } + status = cam_io_r_mb(soc_info->reg_map[0].mem_base + + IPE_CDM_IRQ_STATUS); + if ((status & IPE_RST_DONE_IRQ_STATUS_BIT) != 0x1) { + CAM_ERR(CAM_ICP, "IPE CDM rst failed status 0x%x", status); + reset_ipe_cdm_fail = true; + } + + /* IPE reset*/ + status = 0; + cam_io_w_mb((uint32_t)0x3, + soc_info->reg_map[0].mem_base + IPE_TOP_RST_CMD); + while (retry_cnt < HFI_MAX_POLL_TRY) { + readw_poll_timeout((soc_info->reg_map[0].mem_base + + IPE_TOP_IRQ_STATUS), + status, ((status & IPE_RST_DONE_IRQ_STATUS_BIT) == 0x1), + 100, 10000); + + CAM_DBG(CAM_HFI, "ipe_top_irq_status = %u", status); + + + if ((status & IPE_RST_DONE_IRQ_STATUS_BIT) == 0x1) + break; + retry_cnt++; + } + status = cam_io_r_mb(soc_info->reg_map[0].mem_base + + IPE_TOP_IRQ_STATUS); + if ((status & IPE_RST_DONE_IRQ_STATUS_BIT) != 0x1) { + CAM_ERR(CAM_ICP, "IPE top rst failed status 0x%x", status); + reset_ipe_top_fail = true; + } + + cam_ipe_get_gdsc_control(soc_info); + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, core_info->ipe_hw_info->pwr_ctrl, + true, &pwr_ctrl); + cam_cpas_reg_read(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, core_info->ipe_hw_info->pwr_status, + true, &pwr_status); + CAM_DBG(CAM_ICP, "(After)pwr_ctrl = %x pwr_status = %x", + pwr_ctrl, pwr_status); + + if (reset_ipe_cdm_fail || reset_ipe_top_fail) + rc = -EAGAIN; + + return rc; +} + +int cam_ipe_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + struct cam_hw_info *ipe_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ipe_device_core_info *core_info = NULL; + struct cam_ipe_device_hw_info *hw_info = NULL; + int rc = 0; + + if (!device_priv) { + CAM_ERR(CAM_ICP, "Invalid arguments"); + return -EINVAL; + } + + if (cmd_type >= CAM_ICP_IPE_CMD_MAX) { + CAM_ERR(CAM_ICP, "Invalid command : %x", cmd_type); + return -EINVAL; + } + + soc_info = &ipe_dev->soc_info; + core_info = (struct cam_ipe_device_core_info *)ipe_dev->core_info; + hw_info = core_info->ipe_hw_info; + + switch (cmd_type) { + case CAM_ICP_IPE_CMD_VOTE_CPAS: { + struct cam_icp_cpas_vote *cpas_vote = cmd_args; + + if (!cmd_args) + return -EINVAL; + + cam_ipe_cpas_vote(core_info, cpas_vote); + break; + } + + case CAM_ICP_IPE_CMD_CPAS_START: { + struct cam_icp_cpas_vote *cpas_vote = cmd_args; + + if (!cmd_args) + return -EINVAL; + + if (!core_info->cpas_start) { + rc = cam_cpas_start(core_info->cpas_handle, + &cpas_vote->ahb_vote, &cpas_vote->axi_vote); + core_info->cpas_start = true; + } + break; + } + + case CAM_ICP_IPE_CMD_CPAS_STOP: + if (core_info->cpas_start) { + cam_cpas_stop(core_info->cpas_handle); + core_info->cpas_start = false; + } + break; + case CAM_ICP_IPE_CMD_POWER_COLLAPSE: + rc = cam_ipe_handle_pc(ipe_dev); + break; + case CAM_ICP_IPE_CMD_POWER_RESUME: + rc = cam_ipe_handle_resume(ipe_dev); + break; + case CAM_ICP_IPE_CMD_UPDATE_CLK: { + struct cam_a5_clk_update_cmd *clk_upd_cmd = + (struct cam_a5_clk_update_cmd *)cmd_args; + struct cam_ahb_vote ahb_vote; + uint32_t clk_rate = clk_upd_cmd->curr_clk_rate; + int32_t clk_level = 0, err = 0; + + CAM_DBG(CAM_PERF, "ipe_src_clk rate = %d", (int)clk_rate); + if (!core_info->clk_enable) { + if (clk_upd_cmd->ipe_bps_pc_enable) { + cam_ipe_handle_pc(ipe_dev); + cam_cpas_reg_write(core_info->cpas_handle, + CAM_CPAS_REG_CPASTOP, + hw_info->pwr_ctrl, true, 0x0); + } + rc = cam_ipe_toggle_clk(soc_info, true); + if (rc) + CAM_ERR(CAM_ICP, "Enable failed"); + else + core_info->clk_enable = true; + if (clk_upd_cmd->ipe_bps_pc_enable) { + rc = cam_ipe_handle_resume(ipe_dev); + if (rc) + CAM_ERR(CAM_ICP, "bps resume failed"); + } + } + CAM_DBG(CAM_PERF, "clock rate %d", clk_rate); + + rc = cam_ipe_update_clk_rate(soc_info, clk_rate); + if (rc) + CAM_ERR(CAM_PERF, "Failed to update clk %d", clk_rate); + + err = cam_soc_util_get_clk_level(soc_info, + clk_rate, soc_info->src_clk_idx, + &clk_level); + + if (!err) { + clk_upd_cmd->clk_level = clk_level; + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = clk_level; + cam_cpas_update_ahb_vote( + core_info->cpas_handle, + &ahb_vote); + } + break; + } + case CAM_ICP_IPE_CMD_DISABLE_CLK: + if (core_info->clk_enable == true) + cam_ipe_toggle_clk(soc_info, false); + core_info->clk_enable = false; + break; + case CAM_ICP_IPE_CMD_RESET: + rc = cam_ipe_cmd_reset(soc_info, core_info); + break; + default: + CAM_ERR(CAM_ICP, "Invalid Cmd Type:%u", cmd_type); + rc = -EINVAL; + break; + } + return rc; +} + +irqreturn_t cam_ipe_irq(int irq_num, void *data) +{ + return IRQ_HANDLED; +} diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.h b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.h new file mode 100644 index 0000000000000000000000000000000000000000..1a15e9233896f13887df181ea87f4c350eb7956a --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_IPE_CORE_H +#define CAM_IPE_CORE_H + +#include +#include +#include +#include + +#define IPE_COLLAPSE_MASK 0x1 +#define IPE_PWR_ON_MASK 0x2 + +struct cam_ipe_device_hw_info { + uint32_t hw_idx; + uint32_t pwr_ctrl; + uint32_t pwr_status; + uint32_t reserved; +}; + +struct cam_ipe_device_core_info { + struct cam_ipe_device_hw_info *ipe_hw_info; + uint32_t cpas_handle; + bool cpas_start; + bool clk_enable; +}; + +int cam_ipe_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_ipe_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_ipe_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size); +irqreturn_t cam_ipe_irq(int irq_num, void *data); + +#endif /* CAM_IPE_CORE_H */ diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_dev.c b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..0390488d92b3d790eb32937cb942b28ec963a272 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_dev.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "ipe_core.h" +#include "ipe_soc.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "cam_io_util.h" +#include "cam_icp_hw_intf.h" +#include "cam_icp_hw_mgr_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" + +static struct cam_ipe_device_hw_info cam_ipe_hw_info[] = { + { + .hw_idx = 0, + .pwr_ctrl = 0x4c, + .pwr_status = 0x48, + .reserved = 0, + }, + { + .hw_idx = 1, + .pwr_ctrl = 0x54, + .pwr_status = 0x50, + .reserved = 0, + }, +}; +EXPORT_SYMBOL(cam_ipe_hw_info); + +static char ipe_dev_name[8]; + +int cam_ipe_register_cpas(struct cam_hw_soc_info *soc_info, + struct cam_ipe_device_core_info *core_info, + uint32_t hw_idx) +{ + struct cam_cpas_register_params cpas_register_params; + int rc; + + cpas_register_params.dev = &soc_info->pdev->dev; + memcpy(cpas_register_params.identifier, "ipe", sizeof("ipe")); + cpas_register_params.cam_cpas_client_cb = NULL; + cpas_register_params.cell_index = hw_idx; + cpas_register_params.userdata = NULL; + + rc = cam_cpas_register_client(&cpas_register_params); + if (rc < 0) { + CAM_ERR(CAM_ICP, "failed: %d", rc); + return rc; + } + core_info->cpas_handle = cpas_register_params.client_handle; + + return rc; +} + +int cam_ipe_probe(struct platform_device *pdev) +{ + struct cam_hw_info *ipe_dev = NULL; + struct cam_hw_intf *ipe_dev_intf = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_ipe_device_core_info *core_info = NULL; + struct cam_ipe_device_hw_info *hw_info = NULL; + int rc = 0; + struct cam_cpas_query_cap query; + uint32_t cam_caps; + uint32_t hw_idx; + + of_property_read_u32(pdev->dev.of_node, + "cell-index", &hw_idx); + + cam_cpas_get_hw_info(&query.camera_family, + &query.camera_version, &query.cpas_version, &cam_caps); + if ((!(cam_caps & CPAS_IPE1_BIT)) && (hw_idx)) { + CAM_ERR(CAM_ICP, "IPE1 hw idx = %d\n", hw_idx); + return -EINVAL; + } + + ipe_dev_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!ipe_dev_intf) + return -ENOMEM; + + ipe_dev_intf->hw_idx = hw_idx; + ipe_dev = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!ipe_dev) { + kfree(ipe_dev_intf); + return -ENOMEM; + } + + memset(ipe_dev_name, 0, sizeof(ipe_dev_name)); + snprintf(ipe_dev_name, sizeof(ipe_dev_name), + "ipe%1u", ipe_dev_intf->hw_idx); + + ipe_dev->soc_info.pdev = pdev; + ipe_dev->soc_info.dev = &pdev->dev; + ipe_dev->soc_info.dev_name = ipe_dev_name; + ipe_dev_intf->hw_priv = ipe_dev; + ipe_dev_intf->hw_ops.init = cam_ipe_init_hw; + ipe_dev_intf->hw_ops.deinit = cam_ipe_deinit_hw; + ipe_dev_intf->hw_ops.process_cmd = cam_ipe_process_cmd; + ipe_dev_intf->hw_type = CAM_ICP_DEV_IPE; + + CAM_DBG(CAM_ICP, "type %d index %d", + ipe_dev_intf->hw_type, + ipe_dev_intf->hw_idx); + + platform_set_drvdata(pdev, ipe_dev_intf); + + ipe_dev->core_info = kzalloc(sizeof(struct cam_ipe_device_core_info), + GFP_KERNEL); + if (!ipe_dev->core_info) { + kfree(ipe_dev); + kfree(ipe_dev_intf); + return -ENOMEM; + } + core_info = (struct cam_ipe_device_core_info *)ipe_dev->core_info; + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_DBG(CAM_ICP, "No ipe hardware info"); + kfree(ipe_dev->core_info); + kfree(ipe_dev); + kfree(ipe_dev_intf); + rc = -EINVAL; + return rc; + } + hw_info = &cam_ipe_hw_info[ipe_dev_intf->hw_idx]; + core_info->ipe_hw_info = hw_info; + + rc = cam_ipe_init_soc_resources(&ipe_dev->soc_info, cam_ipe_irq, + ipe_dev); + if (rc < 0) { + CAM_ERR(CAM_ICP, "failed to init_soc"); + kfree(ipe_dev->core_info); + kfree(ipe_dev); + kfree(ipe_dev_intf); + return rc; + } + + CAM_DBG(CAM_ICP, "cam_ipe_init_soc_resources : %pK", + (void *)&ipe_dev->soc_info); + rc = cam_ipe_register_cpas(&ipe_dev->soc_info, + core_info, ipe_dev_intf->hw_idx); + if (rc < 0) { + kfree(ipe_dev->core_info); + kfree(ipe_dev); + kfree(ipe_dev_intf); + return rc; + } + ipe_dev->hw_state = CAM_HW_STATE_POWER_DOWN; + mutex_init(&ipe_dev->hw_mutex); + spin_lock_init(&ipe_dev->hw_lock); + init_completion(&ipe_dev->hw_complete); + + CAM_DBG(CAM_ICP, "IPE%d probe successful", + ipe_dev_intf->hw_idx); + + return rc; +} + +static const struct of_device_id cam_ipe_dt_match[] = { + { + .compatible = "qcom,cam-ipe", + .data = &cam_ipe_hw_info, + }, + {} +}; +MODULE_DEVICE_TABLE(of, cam_ipe_dt_match); + +static struct platform_driver cam_ipe_driver = { + .probe = cam_ipe_probe, + .driver = { + .name = "cam-ipe", + .owner = THIS_MODULE, + .of_match_table = cam_ipe_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_ipe_init_module(void) +{ + return platform_driver_register(&cam_ipe_driver); +} + +static void __exit cam_ipe_exit_module(void) +{ + platform_driver_unregister(&cam_ipe_driver); +} + +module_init(cam_ipe_init_module); +module_exit(cam_ipe_exit_module); +MODULE_DESCRIPTION("CAM IPE driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.c b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..11cc7f7a33172cf23c4c51fdc1025f49f77b2b5d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "ipe_soc.h" +#include "cam_soc_util.h" +#include "cam_debug_util.h" + + +int cam_ipe_transfer_gdsc_control(struct cam_hw_soc_info *soc_info) +{ + int i; + int rc; + + for (i = 0; i < soc_info->num_rgltr; i++) { + rc = regulator_set_mode(soc_info->rgltr[i], + REGULATOR_MODE_FAST); + if (rc) { + CAM_ERR(CAM_ICP, "Regulator set mode %s failed", + soc_info->rgltr_name[i]); + goto rgltr_set_mode_failed; + } + } + return 0; + +rgltr_set_mode_failed: + for (i = i - 1; i >= 0; i--) + if (soc_info->rgltr[i]) + regulator_set_mode(soc_info->rgltr[i], + REGULATOR_MODE_NORMAL); + + return rc; +} + +int cam_ipe_get_gdsc_control(struct cam_hw_soc_info *soc_info) +{ + int i; + int rc; + + for (i = 0; i < soc_info->num_rgltr; i++) { + rc = regulator_set_mode(soc_info->rgltr[i], + REGULATOR_MODE_NORMAL); + if (rc) { + CAM_ERR(CAM_ICP, "Regulator set mode %s failed", + soc_info->rgltr_name[i]); + goto rgltr_set_mode_failed; + } + } + return 0; + +rgltr_set_mode_failed: + for (i = i - 1; i >= 0; i--) + if (soc_info->rgltr[i]) + regulator_set_mode(soc_info->rgltr[i], + REGULATOR_MODE_FAST); + + return rc; +} + +static int cam_ipe_get_dt_properties(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) + CAM_ERR(CAM_ICP, "get ipe dt prop is failed"); + + return rc; +} + +static int cam_ipe_request_platform_resource( + struct cam_hw_soc_info *soc_info, + irq_handler_t ipe_irq_handler, void *irq_data) +{ + int rc = 0; + + rc = cam_soc_util_request_platform_resource(soc_info, ipe_irq_handler, + irq_data); + + return rc; +} + +int cam_ipe_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t ipe_irq_handler, void *irq_data) +{ + int rc = 0; + + rc = cam_ipe_get_dt_properties(soc_info); + if (rc < 0) + return rc; + + rc = cam_ipe_request_platform_resource(soc_info, ipe_irq_handler, + irq_data); + if (rc < 0) + return rc; + + return rc; +} + +int cam_ipe_enable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_SVS_VOTE, false); + if (rc) { + CAM_ERR(CAM_ICP, "enable platform failed"); + return rc; + } + + return rc; +} + +int cam_ipe_disable_soc_resources(struct cam_hw_soc_info *soc_info, + bool disable_clk) +{ + int rc = 0; + + rc = cam_soc_util_disable_platform_resource(soc_info, disable_clk, + false); + if (rc) + CAM_ERR(CAM_ICP, "enable platform failed"); + + return rc; +} + +int cam_ipe_update_clk_rate(struct cam_hw_soc_info *soc_info, + uint32_t clk_rate) +{ + int32_t src_clk_idx; + + if (!soc_info) + return -EINVAL; + + src_clk_idx = soc_info->src_clk_idx; + + if ((soc_info->clk_level_valid[CAM_TURBO_VOTE] == true) && + (soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx] != 0) && + (clk_rate > soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx])) { + CAM_DBG(CAM_PERF, "clk_rate %d greater than max, reset to %d", + clk_rate, + soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]); + clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]; + } + + return cam_soc_util_set_src_clk_rate(soc_info, clk_rate); +} + +int cam_ipe_toggle_clk(struct cam_hw_soc_info *soc_info, bool clk_enable) +{ + int rc = 0; + + if (clk_enable) + rc = cam_soc_util_clk_enable_default(soc_info, CAM_SVS_VOTE); + else + cam_soc_util_clk_disable_default(soc_info); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.h b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..8981b18823adb0568a2ed98ef4b85ac3071aef38 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_IPE_SOC_H +#define CAM_IPE_SOC_H + +#include "cam_soc_util.h" + +int cam_ipe_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t ipe_irq_handler, void *irq_data); + +int cam_ipe_enable_soc_resources(struct cam_hw_soc_info *soc_info); + +int cam_ipe_disable_soc_resources(struct cam_hw_soc_info *soc_info, + bool disable_clk); + +int cam_ipe_get_gdsc_control(struct cam_hw_soc_info *soc_info); + +int cam_ipe_transfer_gdsc_control(struct cam_hw_soc_info *soc_info); + +int cam_ipe_update_clk_rate(struct cam_hw_soc_info *soc_info, + uint32_t clk_rate); +int cam_ipe_toggle_clk(struct cam_hw_soc_info *soc_info, bool clk_enable); +#endif /* CAM_IPE_SOC_H */ diff --git a/techpack/camera-bengal/drivers/cam_isp/Makefile b/techpack/camera-bengal/drivers/cam_isp/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..3cfdbe309a858251ddfdc6fad5128f240bb38326 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ + +obj-$(CONFIG_SPECTRA_CAMERA) += isp_hw_mgr/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_isp_dev.o cam_isp_context.o diff --git a/techpack/camera-bengal/drivers/cam_isp/cam_isp_context.c b/techpack/camera-bengal/drivers/cam_isp/cam_isp_context.c new file mode 100644 index 0000000000000000000000000000000000000000..d6a29cb380896d066672800e23dd6a2ed684c6f8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/cam_isp_context.c @@ -0,0 +1,5107 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "cam_mem_mgr.h" +#include "cam_sync_api.h" +#include "cam_req_mgr_dev.h" +#include "cam_trace.h" +#include "cam_debug_util.h" +#include "cam_packet_util.h" +#include "cam_context_utils.h" +#include "cam_cdm_util.h" +#include "cam_isp_context.h" +#include "cam_common_util.h" +#include "cam_req_mgr_debug.h" + +static const char isp_dev_name[] = "cam-isp"; + +static struct cam_isp_ctx_debug isp_ctx_debug; + +#define INC_HEAD(head, max_entries, ret) \ + div_u64_rem(atomic64_add_return(1, head),\ + max_entries, (ret)) + +static int cam_isp_context_dump_active_request(void *data, unsigned long iova, + uint32_t buf_info); + +static int __cam_isp_ctx_start_dev_in_ready(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd); + +static const char *__cam_isp_evt_val_to_type( + uint32_t evt_id) +{ + switch (evt_id) { + case CAM_ISP_CTX_EVENT_SUBMIT: + return "SUBMIT"; + case CAM_ISP_CTX_EVENT_APPLY: + return "APPLY"; + case CAM_ISP_CTX_EVENT_EPOCH: + return "EPOCH"; + case CAM_ISP_CTX_EVENT_RUP: + return "RUP"; + case CAM_ISP_CTX_EVENT_BUFDONE: + return "BUFDONE"; + default: + return "CAM_ISP_EVENT_INVALID"; + } +} + +static void __cam_isp_ctx_update_event_record( + struct cam_isp_context *ctx_isp, + enum cam_isp_ctx_event event, + struct cam_ctx_request *req) +{ + int iterator = 0; + ktime_t cur_time; + struct cam_isp_ctx_req *req_isp; + + if (!ctx_isp) { + CAM_ERR(CAM_ISP, "Invalid Args"); + return; + } + switch (event) { + case CAM_ISP_CTX_EVENT_EPOCH: + case CAM_ISP_CTX_EVENT_RUP: + case CAM_ISP_CTX_EVENT_BUFDONE: + break; + case CAM_ISP_CTX_EVENT_SUBMIT: + case CAM_ISP_CTX_EVENT_APPLY: + if (!req) { + CAM_ERR(CAM_ISP, "Invalid arg for event %d", event); + return; + } + break; + default: + break; + } + + INC_HEAD(&ctx_isp->event_record_head[event], + CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES, &iterator); + cur_time = ktime_get(); + if (req) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + ctx_isp->event_record[event][iterator].req_id = + req->request_id; + req_isp->event_timestamp[event] = cur_time; + } else { + ctx_isp->event_record[event][iterator].req_id = 0; + } + ctx_isp->event_record[event][iterator].timestamp = cur_time; +} + +static int __cam_isp_ctx_dump_event_record( + struct cam_isp_context *ctx_isp, + uintptr_t cpu_addr, + size_t buf_len, + size_t *offset) +{ + int i, j; + int index; + size_t remain_len; + uint8_t *dst; + uint32_t oldest_entry, num_entries; + uint32_t min_len; + uint64_t *addr, *start; + uint64_t state_head; + struct timespec64 ts; + struct cam_isp_context_dump_header *hdr; + struct cam_isp_context_event_record *record; + + if (!cpu_addr || !buf_len || !offset || !ctx_isp) { + CAM_ERR(CAM_ISP, "Invalid args %pK %zu %pK %pK", + cpu_addr, buf_len, offset, ctx_isp); + return -EINVAL; + } + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) { + state_head = atomic64_read(&ctx_isp->event_record_head[i]); + + if (state_head == -1) { + return 0; + } else if (state_head < CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES) { + num_entries = state_head + 1; + oldest_entry = 0; + } else { + num_entries = CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES; + div_u64_rem(state_head + 1, + CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES, + &oldest_entry); + } + index = oldest_entry; + + if (buf_len <= *offset) { + CAM_WARN(CAM_ISP, + "Dump buffer overshoot len %zu offset %zu", + buf_len, *offset); + return -ENOSPC; + } + + min_len = sizeof(struct cam_isp_context_dump_header) + + ((num_entries * CAM_ISP_CTX_DUMP_EVENT_NUM_WORDS) * + sizeof(uint64_t)); + remain_len = buf_len - *offset; + + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, + "Dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return -ENOSPC; + } + dst = (uint8_t *)cpu_addr + *offset; + hdr = (struct cam_isp_context_dump_header *)dst; + scnprintf(hdr->tag, + CAM_ISP_CONTEXT_DUMP_TAG_MAX_LEN, "ISP_EVT_%s:", + __cam_isp_evt_val_to_type(i)); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + + sizeof(struct cam_isp_context_dump_header)); + start = addr; + for (j = 0; j < num_entries; j++) { + record = &ctx_isp->event_record[i][index]; + ts = ktime_to_timespec64(record->timestamp); + *addr++ = record->req_id; + *addr++ = ts.tv_sec; + *addr++ = ts.tv_nsec/NSEC_PER_USEC; + index = (index + 1) % + CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES; + } + hdr->size = hdr->word_size * (addr - start); + *offset += hdr->size + + sizeof(struct cam_isp_context_dump_header); + } + return 0; +} + +static void __cam_isp_ctx_update_state_monitor_array( + struct cam_isp_context *ctx_isp, + enum cam_isp_state_change_trigger trigger_type, + uint64_t req_id) +{ + int iterator; + + INC_HEAD(&ctx_isp->state_monitor_head, + CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES, &iterator); + + ctx_isp->cam_isp_ctx_state_monitor[iterator].curr_state = + ctx_isp->substate_activated; + ctx_isp->cam_isp_ctx_state_monitor[iterator].frame_id = + ctx_isp->frame_id; + ctx_isp->cam_isp_ctx_state_monitor[iterator].trigger = + trigger_type; + ctx_isp->cam_isp_ctx_state_monitor[iterator].req_id = + req_id; + ctx_isp->cam_isp_ctx_state_monitor[iterator].evt_time_stamp = + jiffies_to_msecs(jiffies) - ctx_isp->init_timestamp; +} + +static const char *__cam_isp_ctx_substate_val_to_type( + enum cam_isp_ctx_activated_substate type) +{ + switch (type) { + case CAM_ISP_CTX_ACTIVATED_SOF: + return "SOF"; + case CAM_ISP_CTX_ACTIVATED_APPLIED: + return "APPLIED"; + case CAM_ISP_CTX_ACTIVATED_EPOCH: + return "EPOCH"; + case CAM_ISP_CTX_ACTIVATED_BUBBLE: + return "BUBBLE"; + case CAM_ISP_CTX_ACTIVATED_BUBBLE_APPLIED: + return "BUBBLE_APPLIED"; + case CAM_ISP_CTX_ACTIVATED_HW_ERROR: + return "HW_ERROR"; + case CAM_ISP_CTX_ACTIVATED_HALT: + return "HALT"; + default: + return "INVALID"; + } +} + +static const char *__cam_isp_hw_evt_val_to_type( + uint32_t evt_id) +{ + switch (evt_id) { + case CAM_ISP_STATE_CHANGE_TRIGGER_ERROR: + return "ERROR"; + case CAM_ISP_STATE_CHANGE_TRIGGER_APPLIED: + return "APPLIED"; + case CAM_ISP_STATE_CHANGE_TRIGGER_SOF: + return "SOF"; + case CAM_ISP_STATE_CHANGE_TRIGGER_REG_UPDATE: + return "REG_UPDATE"; + case CAM_ISP_STATE_CHANGE_TRIGGER_EPOCH: + return "EPOCH"; + case CAM_ISP_STATE_CHANGE_TRIGGER_EOF: + return "EOF"; + case CAM_ISP_STATE_CHANGE_TRIGGER_DONE: + return "DONE"; + case CAM_ISP_STATE_CHANGE_TRIGGER_FLUSH: + return "FLUSH"; + default: + return "CAM_ISP_EVENT_INVALID"; + } +} + +static void __cam_isp_ctx_dump_state_monitor_array( + struct cam_isp_context *ctx_isp) +{ + int i = 0; + int64_t state_head = 0; + uint32_t index, num_entries, oldest_entry; + + state_head = atomic64_read(&ctx_isp->state_monitor_head); + + if (state_head == -1) { + return; + } else if (state_head < CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES) { + num_entries = state_head; + oldest_entry = 0; + } else { + num_entries = CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES; + div_u64_rem(state_head + 1, + CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES, &oldest_entry); + } + + CAM_ERR(CAM_ISP, + "Dumping state information for preceding requests"); + + index = oldest_entry; + + for (i = 0; i < num_entries; i++) { + CAM_ERR(CAM_ISP, + "Index[%d] time[%d] : Substate[%s] Frame[%lld] ReqId[%llu] evt_type[%s]", + index, + ctx_isp->cam_isp_ctx_state_monitor[index].evt_time_stamp, + __cam_isp_ctx_substate_val_to_type( + ctx_isp->cam_isp_ctx_state_monitor[index].curr_state), + ctx_isp->cam_isp_ctx_state_monitor[index].frame_id, + ctx_isp->cam_isp_ctx_state_monitor[index].req_id, + __cam_isp_hw_evt_val_to_type( + ctx_isp->cam_isp_ctx_state_monitor[index].trigger)); + + index = (index + 1) % CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES; + } +} + +static int cam_isp_context_info_dump(void *context, + enum cam_context_dump_id id) +{ + struct cam_context *ctx = (struct cam_context *)context; + + switch (id) { + case CAM_CTX_DUMP_ACQ_INFO: { + cam_context_dump_hw_acq_info(ctx); + break; + } + default: + CAM_DBG(CAM_ISP, "DUMP id not valid %u", id); + break; + } + + return 0; +} + +static int cam_isp_ctx_dump_req( + struct cam_isp_ctx_req *req_isp, + uintptr_t cpu_addr, + size_t buf_len, + size_t *offset, + bool dump_to_buff) +{ + int i = 0, rc = 0; + size_t len = 0; + uint32_t *buf_addr; + uint32_t *buf_start, *buf_end; + size_t remain_len = 0; + struct cam_cdm_cmd_buf_dump_info dump_info; + + for (i = 0; i < req_isp->num_cfg; i++) { + rc = cam_packet_util_get_cmd_mem_addr( + req_isp->cfg[i].handle, &buf_addr, &len); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Failed to get_cmd_mem_addr, rc=%d", + rc); + } else { + if (req_isp->cfg[i].offset >= ((uint32_t)len)) { + CAM_ERR(CAM_ISP, + "Invalid offset exp %u actual %u", + req_isp->cfg[i].offset, (uint32_t)len); + cam_mem_put_cpu_buf(req_isp->cfg[i].handle); + return -EINVAL; + } + remain_len = len - req_isp->cfg[i].offset; + + if (req_isp->cfg[i].len > + ((uint32_t)remain_len)) { + CAM_ERR(CAM_ISP, + "Invalid len exp %u remain_len %u", + req_isp->cfg[i].len, + (uint32_t)remain_len); + cam_mem_put_cpu_buf(req_isp->cfg[i].handle); + return -EINVAL; + } + + buf_start = (uint32_t *)((uint8_t *) buf_addr + + req_isp->cfg[i].offset); + buf_end = (uint32_t *)((uint8_t *) buf_start + + req_isp->cfg[i].len - 1); + if (dump_to_buff) { + if (!cpu_addr || !offset || !buf_len) { + CAM_ERR(CAM_ISP, "Invalid args"); + break; + } + dump_info.src_start = buf_start; + dump_info.src_end = buf_end; + dump_info.dst_start = cpu_addr; + dump_info.dst_offset = *offset; + dump_info.dst_max_size = buf_len; + rc = cam_cdm_util_dump_cmd_bufs_v2(&dump_info); + *offset = dump_info.dst_offset; + if (rc) + return rc; + } else { + cam_cdm_util_dump_cmd_buf(buf_start, buf_end); + } + cam_mem_put_cpu_buf(req_isp->cfg[i].handle); + } + } + return rc; +} + +static int __cam_isp_ctx_enqueue_request_in_order( + struct cam_context *ctx, struct cam_ctx_request *req) +{ + struct cam_ctx_request *req_current; + struct cam_ctx_request *req_prev; + struct list_head temp_list; + struct cam_isp_context *ctx_isp; + + INIT_LIST_HEAD(&temp_list); + spin_lock_bh(&ctx->lock); + if (list_empty(&ctx->pending_req_list)) { + list_add_tail(&req->list, &ctx->pending_req_list); + } else { + list_for_each_entry_safe_reverse( + req_current, req_prev, &ctx->pending_req_list, list) { + if (req->request_id < req_current->request_id) { + list_del_init(&req_current->list); + list_add(&req_current->list, &temp_list); + continue; + } else if (req->request_id == req_current->request_id) { + CAM_WARN(CAM_ISP, + "Received duplicated request %lld", + req->request_id); + } + break; + } + list_add_tail(&req->list, &ctx->pending_req_list); + + if (!list_empty(&temp_list)) { + list_for_each_entry_safe( + req_current, req_prev, &temp_list, list) { + list_del_init(&req_current->list); + list_add_tail(&req_current->list, + &ctx->pending_req_list); + } + } + } + ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_SUBMIT, req); + spin_unlock_bh(&ctx->lock); + return 0; +} + +static int __cam_isp_ctx_enqueue_init_request( + struct cam_context *ctx, struct cam_ctx_request *req) +{ + int rc = 0; + struct cam_ctx_request *req_old; + struct cam_isp_ctx_req *req_isp_old; + struct cam_isp_ctx_req *req_isp_new; + + spin_lock_bh(&ctx->lock); + if (list_empty(&ctx->pending_req_list)) { + list_add_tail(&req->list, &ctx->pending_req_list); + CAM_DBG(CAM_ISP, "INIT packet added req id= %d", + req->request_id); + goto end; + } + + req_old = list_first_entry(&ctx->pending_req_list, + struct cam_ctx_request, list); + req_isp_old = (struct cam_isp_ctx_req *) req_old->req_priv; + req_isp_new = (struct cam_isp_ctx_req *) req->req_priv; + if (req_isp_old->hw_update_data.packet_opcode_type == + CAM_ISP_PACKET_INIT_DEV) { + if ((req_isp_old->num_cfg + req_isp_new->num_cfg) >= + CAM_ISP_CTX_CFG_MAX) { + CAM_WARN(CAM_ISP, "Can not merge INIT pkt"); + rc = -ENOMEM; + } + + if (req_isp_old->num_fence_map_out != 0 || + req_isp_old->num_fence_map_in != 0) { + CAM_WARN(CAM_ISP, "Invalid INIT pkt sequence"); + rc = -EINVAL; + } + + if (!rc) { + memcpy(req_isp_old->fence_map_out, + req_isp_new->fence_map_out, + sizeof(req_isp_new->fence_map_out[0])* + req_isp_new->num_fence_map_out); + req_isp_old->num_fence_map_out = + req_isp_new->num_fence_map_out; + + memcpy(req_isp_old->fence_map_in, + req_isp_new->fence_map_in, + sizeof(req_isp_new->fence_map_in[0])* + req_isp_new->num_fence_map_in); + req_isp_old->num_fence_map_in = + req_isp_new->num_fence_map_in; + + memcpy(&req_isp_old->cfg[req_isp_old->num_cfg], + req_isp_new->cfg, + sizeof(req_isp_new->cfg[0])* + req_isp_new->num_cfg); + req_isp_old->num_cfg += req_isp_new->num_cfg; + + memcpy(&req_old->pf_data, &req->pf_data, + sizeof(struct cam_hw_mgr_dump_pf_data)); + + req_old->request_id = req->request_id; + + list_add_tail(&req->list, &ctx->free_req_list); + } + } else { + CAM_WARN(CAM_ISP, + "Received Update pkt before INIT pkt. req_id= %lld", + req->request_id); + rc = -EINVAL; + } +end: + spin_unlock_bh(&ctx->lock); + return rc; +} + +static const char *__cam_isp_resource_handle_id_to_type( + uint32_t resource_handle) +{ + switch (resource_handle) { + case CAM_ISP_IFE_OUT_RES_FULL: + return "FULL"; + case CAM_ISP_IFE_OUT_RES_DS4: + return "DS4"; + case CAM_ISP_IFE_OUT_RES_DS16: + return "DS16"; + case CAM_ISP_IFE_OUT_RES_RAW_DUMP: + return "RAW_DUMP"; + case CAM_ISP_IFE_OUT_RES_FD: + return "FD"; + case CAM_ISP_IFE_OUT_RES_PDAF: + return "PDAF"; + case CAM_ISP_IFE_OUT_RES_RDI_0: + return "RDI_0"; + case CAM_ISP_IFE_OUT_RES_RDI_1: + return "RDI_1"; + case CAM_ISP_IFE_OUT_RES_RDI_2: + return "RDI_2"; + case CAM_ISP_IFE_OUT_RES_RDI_3: + return "RDI_3"; + case CAM_ISP_IFE_OUT_RES_STATS_HDR_BE: + return "STATS_HDR_BE"; + case CAM_ISP_IFE_OUT_RES_STATS_HDR_BHIST: + return "STATS_HDR_BHIST"; + case CAM_ISP_IFE_OUT_RES_STATS_TL_BG: + return "STATS_TL_BG"; + case CAM_ISP_IFE_OUT_RES_STATS_BF: + return "STATS_BF"; + case CAM_ISP_IFE_OUT_RES_STATS_AWB_BG: + return "STATS_AWB_BG"; + case CAM_ISP_IFE_OUT_RES_STATS_BHIST: + return "STATS_BHIST"; + case CAM_ISP_IFE_OUT_RES_STATS_RS: + return "STATS_RS"; + case CAM_ISP_IFE_OUT_RES_STATS_CS: + return "STATS_CS"; + case CAM_ISP_IFE_OUT_RES_STATS_IHIST: + return "STATS_IHIST"; + case CAM_ISP_IFE_OUT_RES_FULL_DISP: + return "FULL_DISP"; + case CAM_ISP_IFE_OUT_RES_DS4_DISP: + return "DS4_DISP"; + case CAM_ISP_IFE_OUT_RES_DS16_DISP: + return "DS16_DISP"; + case CAM_ISP_IFE_OUT_RES_2PD: + return "2PD"; + case CAM_ISP_IFE_OUT_RES_RDI_RD: + return "RDI_RD"; + case CAM_ISP_IFE_OUT_RES_LCR: + return "LCR"; + default: + return "CAM_ISP_Invalid_Resource_Type"; + } +} + +static const char *__cam_isp_tfe_resource_handle_id_to_type( + uint32_t resource_handle) +{ + + switch (resource_handle) { + case CAM_ISP_TFE_OUT_RES_FULL: + return "FULL"; + case CAM_ISP_TFE_OUT_RES_RAW_DUMP: + return "RAW_DUMP"; + case CAM_ISP_TFE_OUT_RES_PDAF: + return "PDAF"; + case CAM_ISP_TFE_OUT_RES_RDI_0: + return "RDI_0"; + case CAM_ISP_TFE_OUT_RES_RDI_1: + return "RDI_1"; + case CAM_ISP_TFE_OUT_RES_RDI_2: + return "RDI_2"; + case CAM_ISP_TFE_OUT_RES_STATS_HDR_BE: + return "STATS_HDR_BE"; + case CAM_ISP_TFE_OUT_RES_STATS_HDR_BHIST: + return "STATS_HDR_BHIST"; + case CAM_ISP_TFE_OUT_RES_STATS_TL_BG: + return "STATS_TL_BG"; + case CAM_ISP_TFE_OUT_RES_STATS_BF: + return "STATS_BF"; + case CAM_ISP_TFE_OUT_RES_STATS_AWB_BG: + return "STATS_AWB_BG"; + default: + return "CAM_ISP_Invalid_Resource_Type"; + } +} + +static uint64_t __cam_isp_ctx_get_event_ts(uint32_t evt_id, void *evt_data) +{ + uint64_t ts = 0; + + if (!evt_data) + return 0; + + switch (evt_id) { + case CAM_ISP_HW_EVENT_ERROR: + ts = ((struct cam_isp_hw_error_event_data *)evt_data)-> + timestamp; + break; + case CAM_ISP_HW_EVENT_SOF: + ts = ((struct cam_isp_hw_sof_event_data *)evt_data)-> + timestamp; + break; + case CAM_ISP_HW_EVENT_REG_UPDATE: + ts = ((struct cam_isp_hw_reg_update_event_data *)evt_data)-> + timestamp; + break; + case CAM_ISP_HW_EVENT_EPOCH: + ts = ((struct cam_isp_hw_epoch_event_data *)evt_data)-> + timestamp; + break; + case CAM_ISP_HW_EVENT_EOF: + ts = ((struct cam_isp_hw_eof_event_data *)evt_data)-> + timestamp; + break; + case CAM_ISP_HW_EVENT_DONE: + break; + default: + CAM_DBG(CAM_ISP, "Invalid Event Type %d", evt_id); + } + + return ts; +} + +static void __cam_isp_ctx_send_sof_boot_timestamp( + struct cam_isp_context *ctx_isp, uint64_t request_id, + uint32_t sof_event_status) +{ + struct cam_req_mgr_message req_msg; + + req_msg.session_hdl = ctx_isp->base->session_hdl; + req_msg.u.frame_msg.frame_id = ctx_isp->frame_id; + req_msg.u.frame_msg.request_id = request_id; + req_msg.u.frame_msg.timestamp = ctx_isp->boot_timestamp; + req_msg.u.frame_msg.link_hdl = ctx_isp->base->link_hdl; + req_msg.u.frame_msg.sof_status = sof_event_status; + req_msg.u.frame_msg.frame_id_meta = ctx_isp->frame_id_meta; + + CAM_DBG(CAM_ISP, + "request id:%lld frame number:%lld boot time stamp:0x%llx", + request_id, ctx_isp->frame_id, + ctx_isp->boot_timestamp); + + if (cam_req_mgr_notify_message(&req_msg, + V4L_EVENT_CAM_REQ_MGR_SOF_BOOT_TS, + V4L_EVENT_CAM_REQ_MGR_EVENT)) + CAM_ERR(CAM_ISP, + "Error in notifying the boot time for req id:%lld", + request_id); +} + + +static void __cam_isp_ctx_send_sof_timestamp( + struct cam_isp_context *ctx_isp, uint64_t request_id, + uint32_t sof_event_status) +{ + struct cam_req_mgr_message req_msg; + + req_msg.session_hdl = ctx_isp->base->session_hdl; + req_msg.u.frame_msg.frame_id = ctx_isp->frame_id; + req_msg.u.frame_msg.request_id = request_id; + req_msg.u.frame_msg.timestamp = ctx_isp->sof_timestamp_val; + req_msg.u.frame_msg.link_hdl = ctx_isp->base->link_hdl; + req_msg.u.frame_msg.sof_status = sof_event_status; + req_msg.u.frame_msg.frame_id_meta = ctx_isp->frame_id_meta; + + CAM_DBG(CAM_ISP, + "request id:%lld frame number:%lld SOF time stamp:0x%llx", + request_id, ctx_isp->frame_id, + ctx_isp->sof_timestamp_val); + CAM_DBG(CAM_ISP, "sof status:%d", sof_event_status); + + if (cam_req_mgr_notify_message(&req_msg, + V4L_EVENT_CAM_REQ_MGR_SOF, V4L_EVENT_CAM_REQ_MGR_EVENT)) + CAM_ERR(CAM_ISP, + "Error in notifying the sof time for req id:%lld", + request_id); + + __cam_isp_ctx_send_sof_boot_timestamp(ctx_isp, + request_id, sof_event_status); + +} + +static void __cam_isp_ctx_handle_buf_done_fail_log( + uint64_t request_id, struct cam_isp_ctx_req *req_isp, + uint32_t isp_device_type) +{ + int i; + const char *handle_type; + + if (req_isp->num_fence_map_out >= CAM_ISP_CTX_RES_MAX) { + CAM_ERR(CAM_ISP, + "Num Resources exceed mMAX %d >= %d ", + req_isp->num_fence_map_out, CAM_ISP_CTX_RES_MAX); + return; + } + + CAM_WARN(CAM_ISP, + "Prev Req[%lld] : num_out=%d, num_acked=%d, bubble : report=%d, detected=%d", + request_id, req_isp->num_fence_map_out, req_isp->num_acked, + req_isp->bubble_report, req_isp->bubble_detected); + CAM_WARN(CAM_ISP, + "Resource Handles that fail to generate buf_done in prev frame"); + for (i = 0; i < req_isp->num_fence_map_out; i++) { + if (req_isp->fence_map_out[i].sync_id != -1) { + if (isp_device_type == CAM_IFE_DEVICE_TYPE) { + handle_type = + __cam_isp_resource_handle_id_to_type( + req_isp->fence_map_out[i].resource_handle); + + trace_cam_log_event("Buf_done Congestion", + __cam_isp_resource_handle_id_to_type( + req_isp->fence_map_out[i].resource_handle), + request_id, req_isp->fence_map_out[i].sync_id); + } else { + handle_type = + __cam_isp_tfe_resource_handle_id_to_type( + req_isp->fence_map_out[i].resource_handle); + + trace_cam_log_event("Buf_done Congestion", + __cam_isp_tfe_resource_handle_id_to_type( + req_isp->fence_map_out[i].resource_handle), + request_id, req_isp->fence_map_out[i].sync_id); + } + + CAM_WARN(CAM_ISP, + "Resource_Handle: [%s][0x%x] Sync_ID: [0x%x]", + handle_type, + req_isp->fence_map_out[i].resource_handle, + req_isp->fence_map_out[i].sync_id); + } + } +} + +static int __cam_isp_ctx_handle_buf_done_for_request( + struct cam_isp_context *ctx_isp, + struct cam_ctx_request *req, + struct cam_isp_hw_done_event_data *done, + uint32_t bubble_state, + struct cam_isp_hw_done_event_data *done_next_req) +{ + int rc = 0; + int i, j; + struct cam_isp_ctx_req *req_isp; + struct cam_context *ctx = ctx_isp->base; + uint64_t buf_done_req_id; + const char *handle_type; + + trace_cam_buf_done("ISP", ctx, req); + + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + + CAM_DBG(CAM_ISP, "Enter with bubble_state %d, req_bubble_detected %d", + bubble_state, req_isp->bubble_detected); + + if (done_next_req) { + done_next_req->num_handles = 0; + done_next_req->timestamp = done->timestamp; + } + + for (i = 0; i < done->num_handles; i++) { + for (j = 0; j < req_isp->num_fence_map_out; j++) { + if (done->resource_handle[i] == + req_isp->fence_map_out[j].resource_handle) + break; + } + + if (j == req_isp->num_fence_map_out) { + if (done_next_req) { + /* + * If not found in current request, it could be + * belonging to next request, This can happen if + * IRQ delay happens. + */ + CAM_WARN(CAM_ISP, + "BUF_DONE for res 0x%x not found in Req %lld ", + __cam_isp_resource_handle_id_to_type( + done->resource_handle[i]), + req->request_id); + + done_next_req->resource_handle + [done_next_req->num_handles++] = + done->resource_handle[i]; + } else { + CAM_ERR(CAM_ISP, + "Can not find matching lane handle 0x%x! in Req %lld", + done->resource_handle[i], + req->request_id); + rc = -EINVAL; + } + continue; + } + + if (req_isp->fence_map_out[j].sync_id == -1) { + if (ctx_isp->isp_device_type == CAM_IFE_DEVICE_TYPE) + handle_type = + __cam_isp_resource_handle_id_to_type( + req_isp->fence_map_out[i].resource_handle); + else + handle_type = + __cam_isp_tfe_resource_handle_id_to_type( + req_isp->fence_map_out[i].resource_handle); + + CAM_WARN(CAM_ISP, + "Duplicate BUF_DONE for req %lld : i=%d, j=%d, res=%s", + req->request_id, i, j, handle_type); + + trace_cam_log_event("Duplicate BufDone", + handle_type, req->request_id, ctx->ctx_id); + + if (done_next_req) { + done_next_req->resource_handle + [done_next_req->num_handles++] = + done->resource_handle[i]; + } + + continue; + } + + if (!req_isp->bubble_detected) { + CAM_DBG(CAM_ISP, + "Sync with success: req %lld res 0x%x fd 0x%x, ctx %u", + req->request_id, + req_isp->fence_map_out[j].resource_handle, + req_isp->fence_map_out[j].sync_id, + ctx->ctx_id); + + rc = cam_sync_signal(req_isp->fence_map_out[j].sync_id, + CAM_SYNC_STATE_SIGNALED_SUCCESS); + if (rc) + CAM_DBG(CAM_ISP, "Sync failed with rc = %d", + rc); + } else if (!req_isp->bubble_report) { + CAM_ERR(CAM_ISP, + "Sync with failure: req %lld res 0x%x fd 0x%x, ctx %u", + req->request_id, + req_isp->fence_map_out[j].resource_handle, + req_isp->fence_map_out[j].sync_id, + ctx->ctx_id); + + rc = cam_sync_signal(req_isp->fence_map_out[j].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + if (rc) + CAM_ERR(CAM_ISP, "Sync failed with rc = %d", + rc); + } else { + /* + * Ignore the buffer done if bubble detect is on + * Increment the ack number here, and queue the + * request back to pending list whenever all the + * buffers are done. + */ + req_isp->num_acked++; + CAM_DBG(CAM_ISP, + "buf done with bubble state %d recovery %d", + bubble_state, req_isp->bubble_report); + continue; + } + + CAM_DBG(CAM_ISP, "req %lld, reset sync id 0x%x ctx %u", + req->request_id, + req_isp->fence_map_out[j].sync_id, ctx->ctx_id); + if (!rc) { + req_isp->num_acked++; + req_isp->fence_map_out[j].sync_id = -1; + } + } + + if (req_isp->num_acked > req_isp->num_fence_map_out) { + /* Should not happen */ + CAM_ERR(CAM_ISP, + "WARNING: req_id %lld num_acked %d > map_out %d, ctx %u", + req->request_id, req_isp->num_acked, + req_isp->num_fence_map_out, ctx->ctx_id); + WARN_ON(req_isp->num_acked > req_isp->num_fence_map_out); + } + + if (req_isp->num_acked != req_isp->num_fence_map_out) + return rc; + + ctx_isp->active_req_cnt--; + buf_done_req_id = req->request_id; + + if (req_isp->bubble_detected && req_isp->bubble_report) { + req_isp->num_acked = 0; + req_isp->bubble_detected = false; + list_del_init(&req->list); + atomic_set(&ctx_isp->process_bubble, 0); + + if (buf_done_req_id <= ctx->last_flush_req) { + for (i = 0; i < req_isp->num_fence_map_out; i++) + cam_sync_signal( + req_isp->fence_map_out[i].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + + list_add_tail(&req->list, &ctx->free_req_list); + CAM_DBG(CAM_REQ, + "Move active request %lld to free list(cnt = %d) [flushed], ctx %u", + buf_done_req_id, ctx_isp->active_req_cnt, + ctx->ctx_id); + } else { + list_add(&req->list, &ctx->pending_req_list); + ctx_isp->bubble_frame_cnt = 0; + CAM_DBG(CAM_REQ, + "Move active request %lld to pending list(cnt = %d) [bubble recovery], ctx %u", + req->request_id, ctx_isp->active_req_cnt, + ctx->ctx_id); + } + } else { + if (ctx_isp->reported_req_id < buf_done_req_id) { + ctx_isp->reported_req_id = buf_done_req_id; + __cam_isp_ctx_send_sof_timestamp(ctx_isp, + buf_done_req_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); + } + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->free_req_list); + req_isp->reapply = false; + + CAM_DBG(CAM_REQ, + "Move active request %lld to free list(cnt = %d) [all fences done], ctx %u", + buf_done_req_id, ctx_isp->active_req_cnt, ctx->ctx_id); + ctx_isp->req_info.last_bufdone_req_id = req->request_id; + } + + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_DONE, buf_done_req_id); + + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_BUFDONE, req); + return rc; +} + +static int __cam_isp_ctx_handle_buf_done_in_activated_state( + struct cam_isp_context *ctx_isp, + struct cam_isp_hw_done_event_data *done, + uint32_t bubble_state) +{ + int rc = 0; + struct cam_ctx_request *req; + struct cam_context *ctx = ctx_isp->base; + struct cam_isp_hw_done_event_data done_next_req; + + if (list_empty(&ctx->active_req_list)) { + CAM_DBG(CAM_ISP, "Buf done with no active request"); + return 0; + } + + req = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + + rc = __cam_isp_ctx_handle_buf_done_for_request(ctx_isp, req, done, + bubble_state, &done_next_req); + + if (done_next_req.num_handles) { + struct cam_isp_hw_done_event_data unhandled_res; + struct cam_ctx_request *next_req = list_last_entry( + &ctx->active_req_list, struct cam_ctx_request, list); + + if (next_req->request_id != req->request_id) { + /* + * Few resource handles are already signalled in the + * current request, lets check if there is another + * request waiting for these resources. This can + * happen if handling some of next request's buf done + * events are happening first before handling current + * request's remaining buf dones due to IRQ scheduling. + * Lets check only one more request as we will have + * maximum of 2 requests in active_list at any time. + */ + + CAM_WARN(CAM_ISP, + "Unhandled buf done resources for req %lld, trying next request %lld in active_list", + req->request_id, next_req->request_id); + + __cam_isp_ctx_handle_buf_done_for_request(ctx_isp, + next_req, &done_next_req, + bubble_state, &unhandled_res); + + if (unhandled_res.num_handles == 0) + CAM_INFO(CAM_ISP, + "BUF Done event handed for next request %lld", + next_req->request_id); + else + CAM_ERR(CAM_ISP, + "BUF Done not handled for next request %lld", + next_req->request_id); + } else { + CAM_WARN(CAM_ISP, + "Req %lld only active request, spurious buf_done rxd", + req->request_id); + } + } + + return rc; +} + +static int __cam_isp_ctx_reg_upd_in_epoch_bubble_state( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + if (ctx_isp->frame_id == 1) + CAM_DBG(CAM_ISP, "Reg update in Substate[%s] for early PCR", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + else + CAM_WARN(CAM_ISP, + "Unexpected reg update in activated Substate[%s] for frame_id:%lld", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated), + ctx_isp->frame_id); + return 0; +} + +static int __cam_isp_ctx_reg_upd_in_applied_state( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + int rc = 0; + struct cam_ctx_request *req; + struct cam_context *ctx = ctx_isp->base; + struct cam_isp_ctx_req *req_isp; + uint64_t request_id = 0; + + if (list_empty(&ctx->wait_req_list)) { + CAM_ERR(CAM_ISP, "Reg upd ack with no waiting request"); + goto end; + } + req = list_first_entry(&ctx->wait_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + if (req_isp->num_fence_map_out != 0) { + list_add_tail(&req->list, &ctx->active_req_list); + ctx_isp->active_req_cnt++; + request_id = req->request_id; + CAM_DBG(CAM_REQ, + "move request %lld to active list(cnt = %d), ctx %u", + req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_RUP, req); + } else { + /* no io config, so the request is completed. */ + list_add_tail(&req->list, &ctx->free_req_list); + CAM_DBG(CAM_ISP, + "move active request %lld to free list(cnt = %d), ctx %u", + req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id); + } + + /* + * This function only called directly from applied and bubble applied + * state so change substate here. + */ + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_EPOCH; + CAM_DBG(CAM_ISP, "next Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_REG_UPDATE, request_id); + +end: + return rc; +} + +static int __cam_isp_ctx_notify_sof_in_activated_state( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + int rc = 0; + uint64_t request_id = 0; + struct cam_req_mgr_trigger_notify notify; + struct cam_context *ctx = ctx_isp->base; + struct cam_ctx_request *req; + struct cam_isp_ctx_req *req_isp; + struct cam_isp_hw_epoch_event_data *epoch_done_event_data = + (struct cam_isp_hw_epoch_event_data *)evt_data; + + if (!evt_data) { + CAM_ERR(CAM_ISP, "invalid event data"); + return -EINVAL; + } + + ctx_isp->frame_id_meta = epoch_done_event_data->frame_id_meta; + + /* + * notify reqmgr with sof signal. Note, due to scheduling delay + * we can run into situation that two active requests has already + * be in the active queue while we try to do the notification. + * In this case, we need to skip the current notification. This + * helps the state machine to catch up the delay. + */ + + if (atomic_read(&ctx_isp->process_bubble)) { + + if (list_empty(&ctx->active_req_list)) { + CAM_ERR(CAM_ISP, + "No available active req in bubble"); + atomic_set(&ctx_isp->process_bubble, 0); + rc = -EINVAL; + return rc; + } + + req = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + + if (ctx_isp->bubble_frame_cnt >= 1 && + req_isp->bubble_detected) { + req_isp->num_acked = 0; + ctx_isp->bubble_frame_cnt = 0; + req_isp->bubble_detected = false; + list_del_init(&req->list); + list_add(&req->list, &ctx->pending_req_list); + atomic_set(&ctx_isp->process_bubble, 0); + ctx_isp->active_req_cnt--; + CAM_DBG(CAM_REQ, + "Move active req: %lld to pending list(cnt = %d) [bubble re-apply], ctx %u", + req->request_id, + ctx_isp->active_req_cnt, ctx->ctx_id); + } else if (req_isp->bubble_detected) { + ctx_isp->bubble_frame_cnt++; + CAM_DBG(CAM_ISP, + "Waiting on bufdone for bubble req: %lld, since frame_cnt = %lld", + req->request_id, ctx_isp->bubble_frame_cnt); + } else + CAM_DBG(CAM_ISP, "Delayed bufdone for req: %lld", + req->request_id); + } + + if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_trigger && + ctx_isp->active_req_cnt <= 2) { + if (ctx_isp->subscribe_event & CAM_TRIGGER_POINT_SOF) { + notify.link_hdl = ctx->link_hdl; + notify.dev_hdl = ctx->dev_hdl; + notify.frame_id = ctx_isp->frame_id; + notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.req_id = ctx_isp->req_info.last_bufdone_req_id; + notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; + + ctx->ctx_crm_intf->notify_trigger(¬ify); + CAM_DBG(CAM_ISP, "Notify CRM SOF frame %lld ctx %u", + ctx_isp->frame_id, ctx->ctx_id); + } + + list_for_each_entry(req, &ctx->active_req_list, list) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + if ((!req_isp->bubble_detected) && + (req->request_id > ctx_isp->reported_req_id)) { + request_id = req->request_id; + ctx_isp->reported_req_id = request_id; + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, req); + break; + } + } + + if (ctx_isp->substate_activated == CAM_ISP_CTX_ACTIVATED_BUBBLE) + request_id = 0; + + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_EPOCH, + request_id); + } else { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Can not notify SOF to CRM for ctx %u", + ctx->ctx_id); + rc = -EFAULT; + } + + return 0; +} + +static int __cam_isp_ctx_notify_eof_in_activated_state( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + int rc = 0; + struct cam_req_mgr_trigger_notify notify; + struct cam_context *ctx = ctx_isp->base; + + if (!(ctx_isp->subscribe_event & CAM_TRIGGER_POINT_EOF)) + return rc; + + /* notify reqmgr with eof signal */ + if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_trigger) { + notify.link_hdl = ctx->link_hdl; + notify.dev_hdl = ctx->dev_hdl; + notify.frame_id = ctx_isp->frame_id; + notify.trigger = CAM_TRIGGER_POINT_EOF; + + ctx->ctx_crm_intf->notify_trigger(¬ify); + CAM_DBG(CAM_ISP, "Notify CRM EOF frame %lld ctx %u", + ctx_isp->frame_id, ctx->ctx_id); + + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_EOF, 0); + } else { + CAM_ERR(CAM_ISP, "Can not notify EOF to CRM for ctx %u", + ctx->ctx_id); + rc = -EFAULT; + } + + return rc; +} + +static int __cam_isp_ctx_reg_upd_in_hw_error( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF; + return 0; +} + +static int __cam_isp_ctx_sof_in_activated_state( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + int rc = 0; + struct cam_isp_hw_sof_event_data *sof_event_data = evt_data; + struct cam_ctx_request *req = NULL; + struct cam_context *ctx = ctx_isp->base; + uint64_t request_id = 0; + + /* First check if there is a valid request in active list */ + list_for_each_entry(req, &ctx->active_req_list, list) { + if (req->request_id > ctx_isp->reported_req_id) { + request_id = req->request_id; + break; + } + } + + /* + * If nothing in active list, current request might have not moved + * from wait to active list. This could happen if REG_UPDATE to sw + * is coming immediately after SOF + */ + if (request_id == 0) { + req = list_first_entry(&ctx->wait_req_list, + struct cam_ctx_request, list); + if (req) + request_id = req->request_id; + } + + if (!evt_data) { + CAM_ERR(CAM_ISP, "in valid sof event data"); + return -EINVAL; + } + + ctx_isp->frame_id++; + ctx_isp->sof_timestamp_val = sof_event_data->timestamp; + ctx_isp->boot_timestamp = sof_event_data->boot_time; + + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_SOF, request_id); + + CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx, ctx %u", + ctx_isp->frame_id, ctx_isp->sof_timestamp_val, ctx->ctx_id); + + return rc; +} + +static int __cam_isp_ctx_reg_upd_in_sof(struct cam_isp_context *ctx_isp, + void *evt_data) +{ + int rc = 0; + struct cam_ctx_request *req = NULL; + struct cam_isp_ctx_req *req_isp; + struct cam_context *ctx = ctx_isp->base; + + if (ctx->state != CAM_CTX_ACTIVATED && ctx_isp->frame_id > 1) { + CAM_DBG(CAM_ISP, "invalid RUP"); + goto end; + } + + /* + * This is for the first update. The initial setting will + * cause the reg_upd in the first frame. + */ + if (!list_empty(&ctx->wait_req_list)) { + req = list_first_entry(&ctx->wait_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + if (req_isp->num_fence_map_out == req_isp->num_acked) + list_add_tail(&req->list, &ctx->free_req_list); + else + CAM_ERR(CAM_ISP, + "receive rup in unexpected state"); + } + if (req != NULL) { + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_REG_UPDATE, + req->request_id); + } +end: + return rc; +} + +static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, + void *evt_data) +{ + uint64_t request_id = 0; + struct cam_ctx_request *req; + struct cam_isp_ctx_req *req_isp; + struct cam_context *ctx = ctx_isp->base; + struct cam_isp_hw_epoch_event_data *epoch_done_event_data = + (struct cam_isp_hw_epoch_event_data *)evt_data; + + if (!evt_data) { + CAM_ERR(CAM_ISP, "invalid event data"); + return -EINVAL; + } + + ctx_isp->frame_id_meta = epoch_done_event_data->frame_id_meta; + if (list_empty(&ctx->wait_req_list)) { + /* + * If no wait req in epoch, this is an error case. + * The recovery is to go back to sof state + */ + CAM_ERR(CAM_ISP, "Ctx:%d No wait request", ctx->ctx_id); + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF; + + /* Send SOF event as empty frame*/ + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, NULL); + goto end; + } + + req = list_first_entry(&ctx->wait_req_list, struct cam_ctx_request, + list); + req_isp = (struct cam_isp_ctx_req *)req->req_priv; + req_isp->bubble_detected = true; + req_isp->reapply = true; + + CAM_INFO(CAM_ISP, "ctx:%d Report Bubble flag %d req id:%lld", + ctx->ctx_id, req_isp->bubble_report, req->request_id); + if (req_isp->bubble_report && ctx->ctx_crm_intf && + ctx->ctx_crm_intf->notify_err) { + struct cam_req_mgr_error_notify notify; + + notify.link_hdl = ctx->link_hdl; + notify.dev_hdl = ctx->dev_hdl; + notify.req_id = req->request_id; + notify.error = CRM_KMD_ERR_BUBBLE; + notify.trigger = 0; + if (ctx_isp->subscribe_event & CAM_TRIGGER_POINT_SOF) + notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.frame_id = ctx_isp->frame_id; + notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; + CAM_WARN(CAM_ISP, + "Notify CRM about Bubble req %lld frame %lld, ctx %u", + req->request_id, ctx_isp->frame_id, ctx->ctx_id); + trace_cam_log_event("Bubble", "Rcvd epoch in applied state", + req->request_id, ctx->ctx_id); + ctx->ctx_crm_intf->notify_err(¬ify); + atomic_set(&ctx_isp->process_bubble, 1); + } else { + req_isp->bubble_report = 0; + } + + /* + * Always move the request to active list. Let buf done + * function handles the rest. + */ + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->active_req_list); + ctx_isp->active_req_cnt++; + CAM_DBG(CAM_REQ, "move request %lld to active list(cnt = %d), ctx %u", + req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id); + + if ((req->request_id > ctx_isp->reported_req_id) + && !req_isp->bubble_report) { + request_id = req->request_id; + ctx_isp->reported_req_id = request_id; + } + + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_ERROR); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, req); + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE; + CAM_DBG(CAM_ISP, "next Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + + cam_req_mgr_debug_delay_detect(); + trace_cam_delay_detect("ISP", + "bubble epoch_in_applied", req->request_id, + ctx->ctx_id, ctx->link_hdl, ctx->session_hdl, + CAM_DEFAULT_VALUE); +end: + if (request_id == 0) { + req = list_last_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_EPOCH, req->request_id); + } else { + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_EPOCH, request_id); + } + return 0; +} + + +static int __cam_isp_ctx_buf_done_in_applied(struct cam_isp_context *ctx_isp, + void *evt_data) +{ + int rc = 0; + struct cam_isp_hw_done_event_data *done = + (struct cam_isp_hw_done_event_data *) evt_data; + + rc = __cam_isp_ctx_handle_buf_done_in_activated_state(ctx_isp, done, 0); + return rc; +} + + +static int __cam_isp_ctx_sof_in_epoch(struct cam_isp_context *ctx_isp, + void *evt_data) +{ + int rc = 0; + struct cam_context *ctx = ctx_isp->base; + struct cam_isp_hw_sof_event_data *sof_event_data = evt_data; + struct cam_ctx_request *req; + + if (!evt_data) { + CAM_ERR(CAM_ISP, "in valid sof event data"); + return -EINVAL; + } + + ctx_isp->frame_id++; + ctx_isp->sof_timestamp_val = sof_event_data->timestamp; + ctx_isp->boot_timestamp = sof_event_data->boot_time; + + if (list_empty(&ctx->active_req_list)) + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF; + else + CAM_DBG(CAM_ISP, "Still need to wait for the buf done"); + + req = list_last_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + if (req) + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_SOF, + req->request_id); + + if (ctx_isp->frame_id == 1) + CAM_INFO(CAM_ISP, + "First SOF in EPCR ctx:%d frame_id:%lld next substate %s", + ctx->ctx_id, ctx_isp->frame_id, + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + + CAM_DBG(CAM_ISP, "SOF in epoch ctx:%d frame_id:%lld next substate:%s", + ctx->ctx_id, ctx_isp->frame_id, + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + + return rc; +} + +static int __cam_isp_ctx_buf_done_in_epoch(struct cam_isp_context *ctx_isp, + void *evt_data) +{ + int rc = 0; + struct cam_isp_hw_done_event_data *done = + (struct cam_isp_hw_done_event_data *) evt_data; + + rc = __cam_isp_ctx_handle_buf_done_in_activated_state(ctx_isp, done, 0); + return rc; +} + +static int __cam_isp_ctx_buf_done_in_bubble( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + int rc = 0; + struct cam_isp_hw_done_event_data *done = + (struct cam_isp_hw_done_event_data *) evt_data; + + rc = __cam_isp_ctx_handle_buf_done_in_activated_state(ctx_isp, done, 1); + return rc; +} + +static int __cam_isp_ctx_epoch_in_bubble_applied( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + uint64_t request_id = 0; + struct cam_ctx_request *req; + struct cam_isp_ctx_req *req_isp; + struct cam_context *ctx = ctx_isp->base; + struct cam_isp_hw_epoch_event_data *epoch_done_event_data = + (struct cam_isp_hw_epoch_event_data *)evt_data; + + if (!evt_data) { + CAM_ERR(CAM_ISP, "invalid event data"); + return -EINVAL; + } + + ctx_isp->frame_id_meta = epoch_done_event_data->frame_id_meta; + + /* + * This means we missed the reg upd ack. So we need to + * transition to BUBBLE state again. + */ + + if (list_empty(&ctx->wait_req_list)) { + /* + * If no pending req in epoch, this is an error case. + * Just go back to the bubble state. + */ + CAM_ERR(CAM_ISP, "ctx:%d No pending request.", ctx->ctx_id); + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, NULL); + + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE; + goto end; + } + + req = list_first_entry(&ctx->wait_req_list, struct cam_ctx_request, + list); + req_isp = (struct cam_isp_ctx_req *)req->req_priv; + req_isp->bubble_detected = true; + CAM_INFO(CAM_ISP, "Ctx:%d Report Bubble flag %d req id:%lld", + ctx->ctx_id, req_isp->bubble_report, req->request_id); + req_isp->reapply = true; + + if (req_isp->bubble_report && ctx->ctx_crm_intf && + ctx->ctx_crm_intf->notify_err) { + struct cam_req_mgr_error_notify notify; + + notify.link_hdl = ctx->link_hdl; + notify.dev_hdl = ctx->dev_hdl; + notify.req_id = req->request_id; + notify.error = CRM_KMD_ERR_BUBBLE; + notify.trigger = 0; + if (ctx_isp->subscribe_event & CAM_TRIGGER_POINT_SOF) + notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.frame_id = ctx_isp->frame_id; + notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; + CAM_WARN(CAM_REQ, + "Notify CRM about Bubble req_id %llu frame %lld, ctx %u", + req->request_id, ctx_isp->frame_id, ctx->ctx_id); + ctx->ctx_crm_intf->notify_err(¬ify); + atomic_set(&ctx_isp->process_bubble, 1); + } else { + req_isp->bubble_report = 0; + } + + /* + * Always move the request to active list. Let buf done + * function handles the rest. + */ + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->active_req_list); + ctx_isp->active_req_cnt++; + CAM_DBG(CAM_ISP, "move request %lld to active list(cnt = %d) ctx %u", + req->request_id, ctx_isp->active_req_cnt); + + if (!req_isp->bubble_report) { + if (req->request_id > ctx_isp->reported_req_id) { + request_id = req->request_id; + ctx_isp->reported_req_id = request_id; + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_ERROR); + + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, req); + } else { + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, NULL); + } + } else { + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, NULL); + } + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE; + CAM_DBG(CAM_ISP, "next Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + + cam_req_mgr_debug_delay_detect(); + trace_cam_delay_detect("ISP", + "bubble epoch_in_bubble_applied", + req->request_id, ctx->ctx_id, + ctx->link_hdl, ctx->session_hdl, + CAM_DEFAULT_VALUE); +end: + req = list_last_entry(&ctx->active_req_list, struct cam_ctx_request, + list); + if (req) + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_EPOCH, req->request_id); + return 0; +} + +static int __cam_isp_ctx_buf_done_in_bubble_applied( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + int rc = 0; + struct cam_isp_hw_done_event_data *done = + (struct cam_isp_hw_done_event_data *) evt_data; + + rc = __cam_isp_ctx_handle_buf_done_in_activated_state(ctx_isp, done, 1); + + return rc; +} + +static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, + void *evt_data) +{ + int rc = 0; + uint32_t i = 0; + bool found = 0; + struct cam_ctx_request *req = NULL; + struct cam_ctx_request *req_to_report = NULL; + struct cam_ctx_request *req_to_dump = NULL; + struct cam_ctx_request *req_temp; + struct cam_isp_ctx_req *req_isp = NULL; + struct cam_isp_ctx_req *req_isp_to_report = NULL; + struct cam_req_mgr_error_notify notify = {}; + uint64_t error_request_id; + struct cam_hw_fence_map_entry *fence_map_out = NULL; + struct cam_req_mgr_message req_msg; + + struct cam_context *ctx = ctx_isp->base; + struct cam_isp_hw_error_event_data *error_event_data = + (struct cam_isp_hw_error_event_data *)evt_data; + + uint32_t error_type = error_event_data->error_type; + + CAM_DBG(CAM_ISP, "Enter error_type = %d", error_type); + + if ((error_type == CAM_ISP_HW_ERROR_OVERFLOW) || + (error_type == CAM_ISP_HW_ERROR_BUSIF_OVERFLOW) || + (error_type == CAM_ISP_HW_ERROR_VIOLATION)) { + struct cam_hw_cmd_args hw_cmd_args; + + memset(&hw_cmd_args, 0, sizeof(hw_cmd_args)); + hw_cmd_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_REG_DUMP_ON_ERROR; + rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &hw_cmd_args); + if (rc) { + CAM_ERR(CAM_ISP, "Reg dump on error failed rc: %d", rc); + rc = 0; + } + } + /* + * The error is likely caused by first request on the active list. + * If active list is empty check wait list (maybe error hit as soon + * as RUP and we handle error before RUP. + */ + if (list_empty(&ctx->active_req_list)) { + CAM_DBG(CAM_ISP, + "handling error with no active request"); + if (list_empty(&ctx->wait_req_list)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Error with no active/wait request"); + goto end; + } else { + req_to_dump = list_first_entry(&ctx->wait_req_list, + struct cam_ctx_request, list); + } + } else { + req_to_dump = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + } + + req_isp = (struct cam_isp_ctx_req *) req_to_dump->req_priv; + + if (error_event_data->enable_req_dump) + rc = cam_isp_ctx_dump_req(req_isp, 0, 0, NULL, false); + + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_ERROR, req_to_dump->request_id); + + list_for_each_entry_safe(req, req_temp, + &ctx->active_req_list, list) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + if (!req_isp->bubble_report) { + for (i = 0; i < req_isp->num_fence_map_out; i++) { + fence_map_out = + &req_isp->fence_map_out[i]; + CAM_ERR(CAM_ISP, + "req %llu, Sync fd 0x%x ctx %u", + req->request_id, + req_isp->fence_map_out[i].sync_id, + ctx->ctx_id); + if (req_isp->fence_map_out[i].sync_id != -1) { + rc = cam_sync_signal( + fence_map_out->sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + fence_map_out->sync_id = -1; + } + } + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->free_req_list); + ctx_isp->active_req_cnt--; + } else { + found = 1; + break; + } + } + + if (found) + goto move_to_pending; + + list_for_each_entry_safe(req, req_temp, + &ctx->wait_req_list, list) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + if (!req_isp->bubble_report) { + for (i = 0; i < req_isp->num_fence_map_out; i++) { + fence_map_out = + &req_isp->fence_map_out[i]; + CAM_ERR(CAM_ISP, + "req %llu, Sync fd 0x%x ctx %u", + req->request_id, + req_isp->fence_map_out[i].sync_id, + ctx->ctx_id); + if (req_isp->fence_map_out[i].sync_id != -1) { + rc = cam_sync_signal( + fence_map_out->sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + fence_map_out->sync_id = -1; + } + } + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->free_req_list); + ctx_isp->active_req_cnt--; + } else { + found = 1; + break; + } + } + +move_to_pending: + /* + * If bubble recovery is enabled on any request we need to move that + * request and all the subsequent requests to the pending list. + * Note: + * We need to traverse the active list in reverse order and add + * to head of pending list. + * e.g. pending current state: 10, 11 | active current state: 8, 9 + * intermittent for loop iteration- pending: 9, 10, 11 | active: 8 + * final state - pending: 8, 9, 10, 11 | active: NULL + */ + if (found) { + list_for_each_entry_safe_reverse(req, req_temp, + &ctx->active_req_list, list) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + list_del_init(&req->list); + list_add(&req->list, &ctx->pending_req_list); + ctx_isp->active_req_cnt--; + } + list_for_each_entry_safe_reverse(req, req_temp, + &ctx->wait_req_list, list) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + list_del_init(&req->list); + list_add(&req->list, &ctx->pending_req_list); + ctx_isp->active_req_cnt--; + } + } + +end: + do { + if (list_empty(&ctx->pending_req_list)) { + error_request_id = ctx_isp->last_applied_req_id; + req_isp = NULL; + break; + } + req = list_first_entry(&ctx->pending_req_list, + struct cam_ctx_request, list); + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + error_request_id = ctx_isp->last_applied_req_id; + + if (req_isp->bubble_report) { + req_to_report = req; + req_isp_to_report = req_to_report->req_priv; + break; + } + + for (i = 0; i < req_isp->num_fence_map_out; i++) { + if (req_isp->fence_map_out[i].sync_id != -1) + rc = cam_sync_signal( + req_isp->fence_map_out[i].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + req_isp->fence_map_out[i].sync_id = -1; + } + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->free_req_list); + + } while (req->request_id < ctx_isp->last_applied_req_id); + + if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_err) { + notify.link_hdl = ctx->link_hdl; + notify.dev_hdl = ctx->dev_hdl; + notify.req_id = error_request_id; + notify.error = CRM_KMD_ERR_FATAL; + + if (req_isp_to_report && req_isp_to_report->bubble_report) + if (error_event_data->recovery_enabled) + notify.error = CRM_KMD_ERR_BUBBLE; + + CAM_WARN(CAM_ISP, + "Notify CRM: req %lld, frame %lld ctx %u, error %d", + error_request_id, ctx_isp->frame_id, ctx->ctx_id, + notify.error); + + ctx->ctx_crm_intf->notify_err(¬ify); + + /* + * Need to send error occurred in KMD + * This will help UMD to take necessary action + * and to dump relevant info + */ + + if (notify.error == CRM_KMD_ERR_FATAL) { + req_msg.session_hdl = ctx_isp->base->session_hdl; + req_msg.u.err_msg.device_hdl = ctx_isp->base->dev_hdl; + + if (error_type == CAM_ISP_HW_ERROR_CSID_FATAL) + req_msg.u.err_msg.error_type = + CAM_REQ_MGR_ERROR_TYPE_FULL_RECOVERY; + else + req_msg.u.err_msg.error_type = + CAM_REQ_MGR_ERROR_TYPE_RECOVERY; + + req_msg.u.err_msg.link_hdl = ctx_isp->base->link_hdl; + req_msg.u.err_msg.request_id = error_request_id; + req_msg.u.err_msg.resource_size = 0x0; + + if (cam_req_mgr_notify_message(&req_msg, + V4L_EVENT_CAM_REQ_MGR_ERROR, + V4L_EVENT_CAM_REQ_MGR_EVENT)) + CAM_ERR(CAM_ISP, + "Error in notifying the error time for req id:%lld ctx %u", + ctx_isp->last_applied_req_id, + ctx->ctx_id); + } + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_HW_ERROR; + } else { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Can not notify ERRROR to CRM for ctx %u", + ctx->ctx_id); + rc = -EFAULT; + } + + CAM_DBG(CAM_ISP, "Exit"); + + return rc; +} + +static int __cam_isp_ctx_fs2_sof_in_sof_state( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + int rc = 0; + struct cam_isp_hw_sof_event_data *sof_event_data = evt_data; + struct cam_ctx_request *req; + struct cam_context *ctx = ctx_isp->base; + struct cam_req_mgr_trigger_notify notify; + uint64_t request_id = 0; + + if (!evt_data) { + CAM_ERR(CAM_ISP, "in valid sof event data"); + return -EINVAL; + } + + ctx_isp->frame_id++; + ctx_isp->sof_timestamp_val = sof_event_data->timestamp; + ctx_isp->boot_timestamp = sof_event_data->boot_time; + + CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx", + ctx_isp->frame_id, ctx_isp->sof_timestamp_val); + + if (!(list_empty(&ctx->wait_req_list))) + goto end; + + if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_trigger && + ctx_isp->active_req_cnt <= 2) { + if (ctx_isp->subscribe_event & CAM_TRIGGER_POINT_SOF) { + notify.link_hdl = ctx->link_hdl; + notify.dev_hdl = ctx->dev_hdl; + notify.frame_id = ctx_isp->frame_id; + notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.req_id = ctx_isp->req_info.last_bufdone_req_id; + notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; + + ctx->ctx_crm_intf->notify_trigger(¬ify); + CAM_DBG(CAM_ISP, "Notify CRM SOF frame %lld", + ctx_isp->frame_id); + } + + list_for_each_entry(req, &ctx->active_req_list, list) { + if (req->request_id > ctx_isp->reported_req_id) { + request_id = req->request_id; + ctx_isp->reported_req_id = request_id; + break; + } + } + + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_SOF, request_id); + } else { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Can not notify SOF to CRM"); + rc = -EFAULT; + } + +end: + return rc; +} + +static int __cam_isp_ctx_fs2_buf_done(struct cam_isp_context *ctx_isp, + void *evt_data) +{ + int rc = 0; + struct cam_isp_hw_done_event_data *done = + (struct cam_isp_hw_done_event_data *) evt_data; + struct cam_context *ctx = ctx_isp->base; + int prev_active_req_cnt = 0; + int curr_req_id = 0; + struct cam_ctx_request *req; + + prev_active_req_cnt = ctx_isp->active_req_cnt; + req = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + if (req) + curr_req_id = req->request_id; + + rc = __cam_isp_ctx_handle_buf_done_in_activated_state(ctx_isp, done, 0); + + if (prev_active_req_cnt == ctx_isp->active_req_cnt + 1) { + if (list_empty(&ctx->wait_req_list) && + list_empty(&ctx->active_req_list)) { + CAM_DBG(CAM_ISP, "No request, move to SOF"); + ctx_isp->substate_activated = + CAM_ISP_CTX_ACTIVATED_SOF; + if (ctx_isp->reported_req_id < curr_req_id) { + ctx_isp->reported_req_id = curr_req_id; + __cam_isp_ctx_send_sof_timestamp(ctx_isp, + curr_req_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + } + } + } + + return rc; +} + +static int __cam_isp_ctx_fs2_buf_done_in_epoch(struct cam_isp_context *ctx_isp, + void *evt_data) +{ + int rc = 0; + + rc = __cam_isp_ctx_fs2_buf_done(ctx_isp, evt_data); + return rc; +} + +static int __cam_isp_ctx_fs2_buf_done_in_applied( + struct cam_isp_context *ctx_isp, + void *evt_data) +{ + int rc = 0; + + rc = __cam_isp_ctx_fs2_buf_done(ctx_isp, evt_data); + return rc; +} + +static int __cam_isp_ctx_fs2_reg_upd_in_sof(struct cam_isp_context *ctx_isp, + void *evt_data) +{ + int rc = 0; + struct cam_ctx_request *req = NULL; + struct cam_isp_ctx_req *req_isp; + struct cam_context *ctx = ctx_isp->base; + + if (ctx->state != CAM_CTX_ACTIVATED && ctx_isp->frame_id > 1) { + CAM_DBG(CAM_ISP, "invalid RUP"); + goto end; + } + + /* + * This is for the first update. The initial setting will + * cause the reg_upd in the first frame. + */ + if (!list_empty(&ctx->wait_req_list)) { + req = list_first_entry(&ctx->wait_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + if (req_isp->num_fence_map_out == req_isp->num_acked) + list_add_tail(&req->list, &ctx->free_req_list); + else + CAM_ERR(CAM_ISP, + "receive rup in unexpected state"); + } + if (req != NULL) { + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_REG_UPDATE, + req->request_id); + } +end: + return rc; +} + +static int __cam_isp_ctx_fs2_reg_upd_in_applied_state( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + int rc = 0; + struct cam_ctx_request *req = NULL; + struct cam_context *ctx = ctx_isp->base; + struct cam_isp_ctx_req *req_isp; + struct cam_req_mgr_trigger_notify notify; + uint64_t request_id = 0; + + if (list_empty(&ctx->wait_req_list)) { + CAM_ERR(CAM_ISP, "Reg upd ack with no waiting request"); + goto end; + } + req = list_first_entry(&ctx->wait_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + if (req_isp->num_fence_map_out != 0) { + list_add_tail(&req->list, &ctx->active_req_list); + ctx_isp->active_req_cnt++; + CAM_DBG(CAM_REQ, "move request %lld to active list(cnt = %d)", + req->request_id, ctx_isp->active_req_cnt); + } else { + /* no io config, so the request is completed. */ + list_add_tail(&req->list, &ctx->free_req_list); + } + + /* + * This function only called directly from applied and bubble applied + * state so change substate here. + */ + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_EPOCH; + if (req_isp->num_fence_map_out != 1) + goto end; + + if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_trigger && + ctx_isp->active_req_cnt <= 2) { + list_for_each_entry(req, &ctx->active_req_list, list) { + if (req->request_id > ctx_isp->reported_req_id) { + request_id = req->request_id; + ctx_isp->reported_req_id = request_id; + break; + } + } + + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + + if (ctx_isp->subscribe_event & CAM_TRIGGER_POINT_SOF) { + notify.link_hdl = ctx->link_hdl; + notify.dev_hdl = ctx->dev_hdl; + notify.frame_id = ctx_isp->frame_id; + notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.req_id = ctx_isp->req_info.last_bufdone_req_id; + notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; + + ctx->ctx_crm_intf->notify_trigger(¬ify); + CAM_DBG(CAM_ISP, "Notify CRM SOF frame %lld", + ctx_isp->frame_id); + } + } else { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Can not notify SOF to CRM"); + rc = -EFAULT; + } + + CAM_DBG(CAM_ISP, "next Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); +end: + if (req != NULL && !rc) { + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_REG_UPDATE, + req->request_id); + } + return rc; +} + +static struct cam_isp_ctx_irq_ops + cam_isp_ctx_activated_state_machine_irq[CAM_ISP_CTX_ACTIVATED_MAX] = { + /* SOF */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_sof_in_activated_state, + __cam_isp_ctx_reg_upd_in_sof, + __cam_isp_ctx_notify_sof_in_activated_state, + __cam_isp_ctx_notify_eof_in_activated_state, + NULL, + }, + }, + /* APPLIED */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_sof_in_activated_state, + __cam_isp_ctx_reg_upd_in_applied_state, + __cam_isp_ctx_epoch_in_applied, + __cam_isp_ctx_notify_eof_in_activated_state, + __cam_isp_ctx_buf_done_in_applied, + }, + }, + /* EPOCH */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_sof_in_epoch, + __cam_isp_ctx_reg_upd_in_epoch_bubble_state, + __cam_isp_ctx_notify_sof_in_activated_state, + __cam_isp_ctx_notify_eof_in_activated_state, + __cam_isp_ctx_buf_done_in_epoch, + }, + }, + /* BUBBLE */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_sof_in_activated_state, + __cam_isp_ctx_reg_upd_in_epoch_bubble_state, + __cam_isp_ctx_notify_sof_in_activated_state, + __cam_isp_ctx_notify_eof_in_activated_state, + __cam_isp_ctx_buf_done_in_bubble, + }, + }, + /* Bubble Applied */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_sof_in_activated_state, + __cam_isp_ctx_reg_upd_in_applied_state, + __cam_isp_ctx_epoch_in_bubble_applied, + NULL, + __cam_isp_ctx_buf_done_in_bubble_applied, + }, + }, + /* HW ERROR */ + { + .irq_ops = { + NULL, + __cam_isp_ctx_sof_in_activated_state, + __cam_isp_ctx_reg_upd_in_hw_error, + NULL, + NULL, + NULL, + }, + }, + /* HALT */ + { + }, +}; + +static struct cam_isp_ctx_irq_ops + cam_isp_ctx_fs2_state_machine_irq[CAM_ISP_CTX_ACTIVATED_MAX] = { + /* SOF */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_fs2_sof_in_sof_state, + __cam_isp_ctx_fs2_reg_upd_in_sof, + __cam_isp_ctx_fs2_sof_in_sof_state, + __cam_isp_ctx_notify_eof_in_activated_state, + NULL, + }, + }, + /* APPLIED */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_sof_in_activated_state, + __cam_isp_ctx_fs2_reg_upd_in_applied_state, + __cam_isp_ctx_epoch_in_applied, + __cam_isp_ctx_notify_eof_in_activated_state, + __cam_isp_ctx_fs2_buf_done_in_applied, + }, + }, + /* EPOCH */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_sof_in_epoch, + __cam_isp_ctx_reg_upd_in_epoch_bubble_state, + __cam_isp_ctx_notify_sof_in_activated_state, + __cam_isp_ctx_notify_eof_in_activated_state, + __cam_isp_ctx_fs2_buf_done_in_epoch, + }, + }, + /* BUBBLE */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_sof_in_activated_state, + __cam_isp_ctx_reg_upd_in_epoch_bubble_state, + __cam_isp_ctx_notify_sof_in_activated_state, + __cam_isp_ctx_notify_eof_in_activated_state, + __cam_isp_ctx_buf_done_in_bubble, + }, + }, + /* Bubble Applied */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_sof_in_activated_state, + __cam_isp_ctx_reg_upd_in_applied_state, + __cam_isp_ctx_epoch_in_bubble_applied, + NULL, + __cam_isp_ctx_buf_done_in_bubble_applied, + }, + }, + /* HW ERROR */ + { + .irq_ops = { + NULL, + __cam_isp_ctx_sof_in_activated_state, + __cam_isp_ctx_reg_upd_in_hw_error, + NULL, + NULL, + NULL, + }, + }, + /* HALT */ + { + }, +}; + +static int __cam_isp_ctx_apply_req_in_activated_state( + struct cam_context *ctx, struct cam_req_mgr_apply_request *apply, + enum cam_isp_ctx_activated_substate next_state) +{ + int rc = 0; + struct cam_ctx_request *req; + struct cam_ctx_request *active_req = NULL; + struct cam_isp_ctx_req *req_isp; + struct cam_isp_ctx_req *active_req_isp; + struct cam_isp_context *ctx_isp = NULL; + struct cam_hw_config_args cfg; + + if (list_empty(&ctx->pending_req_list)) { + CAM_ERR(CAM_ISP, "No available request for Apply id %lld", + apply->request_id); + rc = -EFAULT; + goto end; + } + + /* + * When the pipeline has issue, the requests can be queued up in the + * pipeline. In this case, we should reject the additional request. + * The maximum number of request allowed to be outstanding is 2. + * + */ + ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; + + if (atomic_read(&ctx_isp->process_bubble)) { + CAM_INFO(CAM_ISP, + "Processing bubble cannot apply Request Id %llu", + apply->request_id); + rc = -EAGAIN; + goto end; + } + + spin_lock_bh(&ctx->lock); + req = list_first_entry(&ctx->pending_req_list, struct cam_ctx_request, + list); + spin_unlock_bh(&ctx->lock); + + /* + * Check whether the request id is matching the tip, if not, this means + * we are in the middle of the error handling. Need to reject this apply + */ + if (req->request_id != apply->request_id) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Invalid Request Id asking %llu existing %llu", + apply->request_id, req->request_id); + rc = -EFAULT; + goto end; + } + + CAM_DBG(CAM_REQ, "Apply request %lld in Substate[%s] ctx %u", + req->request_id, + __cam_isp_ctx_substate_val_to_type(ctx_isp->substate_activated), + ctx->ctx_id); + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + + if (ctx_isp->active_req_cnt >= 2) { + CAM_WARN(CAM_ISP, + "Reject apply request (id %lld) due to congestion(cnt = %d) ctx %u", + req->request_id, + ctx_isp->active_req_cnt, + ctx->ctx_id); + + spin_lock_bh(&ctx->lock); + if (!list_empty(&ctx->active_req_list)) + active_req = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + else + CAM_ERR_RATE_LIMIT(CAM_ISP, + "WARNING: should not happen (cnt = %d) but active_list empty", + ctx_isp->active_req_cnt); + spin_unlock_bh(&ctx->lock); + + if (active_req) { + active_req_isp = + (struct cam_isp_ctx_req *) active_req->req_priv; + __cam_isp_ctx_handle_buf_done_fail_log( + active_req->request_id, active_req_isp, + ctx_isp->isp_device_type); + } + + rc = -EFAULT; + goto end; + } + req_isp->bubble_report = apply->report_if_bubble; + + cfg.ctxt_to_hw_map = ctx_isp->hw_ctx; + cfg.request_id = req->request_id; + cfg.hw_update_entries = req_isp->cfg; + cfg.num_hw_update_entries = req_isp->num_cfg; + cfg.priv = &req_isp->hw_update_data; + cfg.init_packet = 0; + cfg.reapply = req_isp->reapply; + + rc = ctx->hw_mgr_intf->hw_config(ctx->hw_mgr_intf->hw_mgr_priv, &cfg); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Can not apply the configuration"); + } else { + spin_lock_bh(&ctx->lock); + ctx_isp->substate_activated = next_state; + ctx_isp->last_applied_req_id = apply->request_id; + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->wait_req_list); + CAM_DBG(CAM_ISP, "new substate Substate[%s], applied req %lld", + __cam_isp_ctx_substate_val_to_type(next_state), + ctx_isp->last_applied_req_id); + spin_unlock_bh(&ctx->lock); + + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_APPLIED, + req->request_id); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_APPLY, req); + } +end: + return rc; +} + +static int __cam_isp_ctx_apply_req_in_sof( + struct cam_context *ctx, struct cam_req_mgr_apply_request *apply) +{ + int rc = 0; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + + CAM_DBG(CAM_ISP, "current Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + rc = __cam_isp_ctx_apply_req_in_activated_state(ctx, apply, + CAM_ISP_CTX_ACTIVATED_APPLIED); + CAM_DBG(CAM_ISP, "new Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + + if (rc) + CAM_DBG(CAM_ISP, "Apply failed in Substate[%s], rc %d", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated), rc); + + return rc; +} + +static int __cam_isp_ctx_apply_req_in_epoch( + struct cam_context *ctx, struct cam_req_mgr_apply_request *apply) +{ + int rc = 0; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + + CAM_DBG(CAM_ISP, "current Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + rc = __cam_isp_ctx_apply_req_in_activated_state(ctx, apply, + CAM_ISP_CTX_ACTIVATED_APPLIED); + CAM_DBG(CAM_ISP, "new Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + + if (rc) + CAM_DBG(CAM_ISP, "Apply failed in Substate[%s], rc %d", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated), rc); + + return rc; +} + +static int __cam_isp_ctx_apply_req_in_bubble( + struct cam_context *ctx, struct cam_req_mgr_apply_request *apply) +{ + int rc = 0; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + + CAM_DBG(CAM_ISP, "current Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + rc = __cam_isp_ctx_apply_req_in_activated_state(ctx, apply, + CAM_ISP_CTX_ACTIVATED_BUBBLE_APPLIED); + CAM_DBG(CAM_ISP, "new Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + + if (rc) + CAM_DBG(CAM_ISP, "Apply failed in Substate[%s], rc %d", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated), rc); + + return rc; +} + +static int __cam_isp_ctx_dump_req_info( + struct cam_context *ctx, + struct cam_ctx_request *req, + uintptr_t cpu_addr, + size_t buf_len, + size_t *offset) +{ + int i, rc; + uint8_t *dst; + int32_t *addr, *start; + uint32_t min_len; + size_t remain_len; + struct cam_isp_ctx_req *req_isp; + struct cam_isp_context *ctx_isp; + struct cam_isp_context_dump_header *hdr; + + if (!req || !ctx || !offset || !cpu_addr || !buf_len) { + CAM_ERR(CAM_ISP, "Invalid parameters %pK %pK %pK %zu", + req, ctx, offset, buf_len); + return -EINVAL; + } + req_isp = (struct cam_isp_ctx_req *)req->req_priv; + ctx_isp = (struct cam_isp_context *)ctx->ctx_priv; + + if (buf_len <= *offset) { + CAM_WARN(CAM_ISP, "Dump buffer overshoot len %zu offset %zu", + buf_len, *offset); + return -ENOSPC; + } + + remain_len = buf_len - *offset; + min_len = sizeof(struct cam_isp_context_dump_header) + + (CAM_ISP_CTX_DUMP_REQUEST_NUM_WORDS * + req_isp->num_fence_map_out * + sizeof(int32_t)); + + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return -ENOSPC; + } + + dst = (uint8_t *)cpu_addr + *offset; + hdr = (struct cam_isp_context_dump_header *)dst; + hdr->word_size = sizeof(int32_t); + scnprintf(hdr->tag, CAM_ISP_CONTEXT_DUMP_TAG_MAX_LEN, + "ISP_OUT_FENCE:"); + addr = (int32_t *)(dst + sizeof(struct cam_isp_context_dump_header)); + start = addr; + for (i = 0; i < req_isp->num_fence_map_out; i++) { + *addr++ = req_isp->fence_map_out[i].resource_handle; + *addr++ = req_isp->fence_map_out[i].sync_id; + } + hdr->size = hdr->word_size * (addr - start); + *offset += hdr->size + sizeof(struct cam_isp_context_dump_header); + rc = cam_isp_ctx_dump_req(req_isp, cpu_addr, buf_len, + offset, true); + return rc; +} + +static int __cam_isp_ctx_dump_in_top_state( + struct cam_context *ctx, + struct cam_req_mgr_dump_info *dump_info) +{ + int rc = 0; + bool dump_only_event_record = false; + size_t buf_len; + size_t remain_len; + uint8_t *dst; + ktime_t cur_time; + uint32_t min_len; + uint64_t diff; + uint64_t *addr, *start; + uintptr_t cpu_addr; + struct timespec64 ts; + struct cam_isp_context *ctx_isp; + struct cam_ctx_request *req = NULL; + struct cam_isp_ctx_req *req_isp; + struct cam_ctx_request *req_temp; + struct cam_hw_dump_args dump_args; + struct cam_isp_context_dump_header *hdr; + + spin_lock_bh(&ctx->lock); + list_for_each_entry_safe(req, req_temp, + &ctx->active_req_list, list) { + if (req->request_id == dump_info->req_id) { + CAM_INFO(CAM_ISP, "isp dump active list req: %lld", + dump_info->req_id); + goto hw_dump; + } + } + list_for_each_entry_safe(req, req_temp, + &ctx->wait_req_list, list) { + if (req->request_id == dump_info->req_id) { + CAM_INFO(CAM_ISP, "isp dump wait list req: %lld", + dump_info->req_id); + goto hw_dump; + } + } + spin_unlock_bh(&ctx->lock); + return rc; +hw_dump: + rc = cam_mem_get_cpu_buf(dump_info->buf_handle, + &cpu_addr, &buf_len); + if (rc) { + CAM_ERR(CAM_ISP, "Invalid handle %u rc %d", + dump_info->buf_handle, rc); + spin_unlock_bh(&ctx->lock); + return rc; + } + if (buf_len <= dump_info->offset) { + spin_unlock_bh(&ctx->lock); + CAM_WARN(CAM_ISP, "Dump buffer overshoot len %zu offset %zu", + buf_len, dump_info->offset); + cam_mem_put_cpu_buf(dump_info->buf_handle); + return -ENOSPC; + } + + remain_len = buf_len - dump_info->offset; + min_len = sizeof(struct cam_isp_context_dump_header) + + (CAM_ISP_CTX_DUMP_NUM_WORDS * sizeof(uint64_t)); + + if (remain_len < min_len) { + spin_unlock_bh(&ctx->lock); + CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu min %u", + remain_len, min_len); + cam_mem_put_cpu_buf(dump_info->buf_handle); + return -ENOSPC; + } + + ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + cur_time = ktime_get(); + diff = ktime_us_delta( + req_isp->event_timestamp[CAM_ISP_CTX_EVENT_APPLY], + cur_time); + if (diff < CAM_ISP_CTX_RESPONSE_TIME_THRESHOLD) { + CAM_INFO(CAM_ISP, "req %lld found no error", + req->request_id); + dump_only_event_record = true; + } + dst = (uint8_t *)cpu_addr + dump_info->offset; + hdr = (struct cam_isp_context_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_CONTEXT_DUMP_TAG_MAX_LEN, + "ISP_CTX_DUMP:"); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + + sizeof(struct cam_isp_context_dump_header)); + start = addr; + *addr++ = req->request_id; + ts = ktime_to_timespec64( + req_isp->event_timestamp[CAM_ISP_CTX_EVENT_APPLY]); + *addr++ = ts.tv_sec; + *addr++ = ts.tv_nsec/NSEC_PER_USEC; + ts = ktime_to_timespec64(cur_time); + *addr++ = ts.tv_sec; + *addr++ = ts.tv_nsec/NSEC_PER_USEC; + hdr->size = hdr->word_size * (addr - start); + dump_info->offset += hdr->size + + sizeof(struct cam_isp_context_dump_header); + + rc = __cam_isp_ctx_dump_event_record(ctx_isp, cpu_addr, + buf_len, &dump_info->offset); + if (rc) { + CAM_ERR(CAM_ISP, "Dump event fail %lld", + req->request_id); + goto end; + } + if (dump_only_event_record) + goto end; + + rc = __cam_isp_ctx_dump_req_info(ctx, req, cpu_addr, + buf_len, &dump_info->offset); + if (rc) { + CAM_ERR(CAM_ISP, "Dump Req info fail %lld", + req->request_id); + goto end; + } + spin_unlock_bh(&ctx->lock); + + if (ctx->hw_mgr_intf->hw_dump) { + dump_args.offset = dump_info->offset; + dump_args.request_id = dump_info->req_id; + dump_args.buf_handle = dump_info->buf_handle; + dump_args.ctxt_to_hw_map = ctx_isp->hw_ctx; + rc = ctx->hw_mgr_intf->hw_dump( + ctx->hw_mgr_intf->hw_mgr_priv, + &dump_args); + dump_info->offset = dump_args.offset; + } + cam_mem_put_cpu_buf(dump_info->buf_handle); + return rc; + +end: + spin_unlock_bh(&ctx->lock); + cam_mem_put_cpu_buf(dump_info->buf_handle); + return rc; +} + +static int __cam_isp_ctx_flush_req(struct cam_context *ctx, + struct list_head *req_list, struct cam_req_mgr_flush_request *flush_req) +{ + int i, rc, tmp = 0; + uint32_t cancel_req_id_found = 0; + struct cam_ctx_request *req; + struct cam_ctx_request *req_temp; + struct cam_isp_ctx_req *req_isp; + struct list_head flush_list; + struct cam_isp_context *ctx_isp = NULL; + + ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; + + INIT_LIST_HEAD(&flush_list); + if (list_empty(req_list)) { + CAM_DBG(CAM_ISP, "request list is empty"); + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ) { + CAM_ERR(CAM_ISP, "no request to cancel"); + return -EINVAL; + } else + return 0; + } + + CAM_DBG(CAM_REQ, "Flush [%u] in progress for req_id %llu", + flush_req->type, flush_req->req_id); + list_for_each_entry_safe(req, req_temp, req_list, list) { + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ) { + if (req->request_id != flush_req->req_id) { + continue; + } else { + list_del_init(&req->list); + list_add_tail(&req->list, &flush_list); + cancel_req_id_found = 1; + __cam_isp_ctx_update_state_monitor_array( + ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_FLUSH, + req->request_id); + break; + } + } + list_del_init(&req->list); + list_add_tail(&req->list, &flush_list); + __cam_isp_ctx_update_state_monitor_array(ctx_isp, + CAM_ISP_STATE_CHANGE_TRIGGER_FLUSH, req->request_id); + } + + list_for_each_entry_safe(req, req_temp, &flush_list, list) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + for (i = 0; i < req_isp->num_fence_map_out; i++) { + if (req_isp->fence_map_out[i].sync_id != -1) { + CAM_DBG(CAM_ISP, "Flush req 0x%llx, fence %d", + req->request_id, + req_isp->fence_map_out[i].sync_id); + rc = cam_sync_signal( + req_isp->fence_map_out[i].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + if (rc) { + tmp = req_isp->fence_map_out[i].sync_id; + CAM_ERR_RATE_LIMIT(CAM_ISP, + "signal fence %d failed", tmp); + } + req_isp->fence_map_out[i].sync_id = -1; + } + } + req_isp->reapply = false; + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->free_req_list); + } + + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ && + !cancel_req_id_found) + CAM_DBG(CAM_ISP, + "Flush request id:%lld is not found in the list", + flush_req->req_id); + + return 0; +} + +static int __cam_isp_ctx_flush_req_in_top_state( + struct cam_context *ctx, + struct cam_req_mgr_flush_request *flush_req) +{ + int rc = 0; + struct cam_isp_context *ctx_isp; + struct cam_isp_stop_args stop_isp; + struct cam_hw_stop_args stop_args; + struct cam_hw_reset_args reset_args; + struct cam_hw_cmd_args hw_cmd_args; + struct cam_req_mgr_timer_notify timer; + + ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; + + CAM_DBG(CAM_ISP, "Flush pending list"); + spin_lock_bh(&ctx->lock); + rc = __cam_isp_ctx_flush_req(ctx, &ctx->pending_req_list, flush_req); + spin_unlock_bh(&ctx->lock); + + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) { + if (ctx->state <= CAM_CTX_READY) { + ctx->state = CAM_CTX_ACQUIRED; + goto end; + } + + spin_lock_bh(&ctx->lock); + ctx->state = CAM_CTX_FLUSHED; + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_HALT; + spin_unlock_bh(&ctx->lock); + + CAM_INFO(CAM_ISP, "Last request id to flush is %lld", + flush_req->req_id); + ctx->last_flush_req = flush_req->req_id; + + memset(&hw_cmd_args, 0, sizeof(hw_cmd_args)); + hw_cmd_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_REG_DUMP_ON_FLUSH; + rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &hw_cmd_args); + if (rc) { + CAM_ERR(CAM_ISP, "Reg dump on flush failed rc: %d", rc); + rc = 0; + } + + stop_args.ctxt_to_hw_map = ctx_isp->hw_ctx; + stop_isp.hw_stop_cmd = CAM_ISP_HW_STOP_IMMEDIATELY; + stop_isp.stop_only = true; + stop_args.args = (void *)&stop_isp; + rc = ctx->hw_mgr_intf->hw_stop(ctx->hw_mgr_intf->hw_mgr_priv, + &stop_args); + if (rc) + CAM_ERR(CAM_ISP, "Failed to stop HW in Flush rc: %d", + rc); + + CAM_INFO(CAM_ISP, "Stop HW complete. Reset HW next."); + CAM_DBG(CAM_ISP, "Flush wait and active lists"); + + if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_timer) { + timer.link_hdl = ctx->link_hdl; + timer.dev_hdl = ctx->dev_hdl; + timer.state = false; + ctx->ctx_crm_intf->notify_timer(&timer); + } + + spin_lock_bh(&ctx->lock); + if (!list_empty(&ctx->wait_req_list)) + rc = __cam_isp_ctx_flush_req(ctx, &ctx->wait_req_list, + flush_req); + + if (!list_empty(&ctx->active_req_list)) + rc = __cam_isp_ctx_flush_req(ctx, &ctx->active_req_list, + flush_req); + + ctx_isp->active_req_cnt = 0; + spin_unlock_bh(&ctx->lock); + + reset_args.ctxt_to_hw_map = ctx_isp->hw_ctx; + rc = ctx->hw_mgr_intf->hw_reset(ctx->hw_mgr_intf->hw_mgr_priv, + &reset_args); + if (rc) + CAM_ERR(CAM_ISP, "Failed to reset HW rc: %d", rc); + + ctx_isp->init_received = false; + } + +end: + ctx_isp->bubble_frame_cnt = 0; + atomic_set(&ctx_isp->process_bubble, 0); + return rc; +} + +static int __cam_isp_ctx_flush_req_in_ready( + struct cam_context *ctx, + struct cam_req_mgr_flush_request *flush_req) +{ + int rc = 0; + + CAM_DBG(CAM_ISP, "try to flush pending list"); + spin_lock_bh(&ctx->lock); + rc = __cam_isp_ctx_flush_req(ctx, &ctx->pending_req_list, flush_req); + + /* if nothing is in pending req list, change state to acquire */ + if (list_empty(&ctx->pending_req_list)) + ctx->state = CAM_CTX_ACQUIRED; + spin_unlock_bh(&ctx->lock); + + trace_cam_context_state("ISP", ctx); + + CAM_DBG(CAM_ISP, "Flush request in ready state. next state %d", + ctx->state); + return rc; +} + +static struct cam_ctx_ops + cam_isp_ctx_activated_state_machine[CAM_ISP_CTX_ACTIVATED_MAX] = { + /* SOF */ + { + .ioctl_ops = {}, + .crm_ops = { + .apply_req = __cam_isp_ctx_apply_req_in_sof, + }, + .irq_ops = NULL, + }, + /* APPLIED */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* EPOCH */ + { + .ioctl_ops = {}, + .crm_ops = { + .apply_req = __cam_isp_ctx_apply_req_in_epoch, + }, + .irq_ops = NULL, + }, + /* BUBBLE */ + { + .ioctl_ops = {}, + .crm_ops = { + .apply_req = __cam_isp_ctx_apply_req_in_bubble, + }, + .irq_ops = NULL, + }, + /* Bubble Applied */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* HW ERROR */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* HALT */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, +}; + +static struct cam_ctx_ops + cam_isp_ctx_fs2_state_machine[CAM_ISP_CTX_ACTIVATED_MAX] = { + /* SOF */ + { + .ioctl_ops = {}, + .crm_ops = { + .apply_req = __cam_isp_ctx_apply_req_in_sof, + }, + .irq_ops = NULL, + }, + /* APPLIED */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* EPOCH */ + { + .ioctl_ops = {}, + .crm_ops = { + .apply_req = __cam_isp_ctx_apply_req_in_epoch, + }, + .irq_ops = NULL, + }, + /* BUBBLE */ + { + .ioctl_ops = {}, + .crm_ops = { + .apply_req = __cam_isp_ctx_apply_req_in_bubble, + }, + .irq_ops = NULL, + }, + /* Bubble Applied */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* HW ERROR */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* HALT */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, +}; + +static int __cam_isp_ctx_rdi_only_sof_in_top_state( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + int rc = 0; + struct cam_context *ctx = ctx_isp->base; + struct cam_req_mgr_trigger_notify notify; + struct cam_isp_hw_sof_event_data *sof_event_data = evt_data; + uint64_t request_id = 0; + + if (!evt_data) { + CAM_ERR(CAM_ISP, "in valid sof event data"); + return -EINVAL; + } + + ctx_isp->frame_id++; + ctx_isp->sof_timestamp_val = sof_event_data->timestamp; + ctx_isp->boot_timestamp = sof_event_data->boot_time; + + CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx", + ctx_isp->frame_id, ctx_isp->sof_timestamp_val); + + /* + * notify reqmgr with sof signal. Note, due to scheduling delay + * we can run into situation that two active requests has already + * be in the active queue while we try to do the notification. + * In this case, we need to skip the current notification. This + * helps the state machine to catch up the delay. + */ + if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_trigger && + ctx_isp->active_req_cnt <= 2) { + notify.link_hdl = ctx->link_hdl; + notify.dev_hdl = ctx->dev_hdl; + notify.frame_id = ctx_isp->frame_id; + notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.req_id = ctx_isp->req_info.last_bufdone_req_id; + notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; + + ctx->ctx_crm_intf->notify_trigger(¬ify); + CAM_DBG(CAM_ISP, "Notify CRM SOF frame %lld", + ctx_isp->frame_id); + + /* + * It is idle frame with out any applied request id, send + * request id as zero + */ + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + } else { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Can not notify SOF to CRM"); + } + + if (list_empty(&ctx->active_req_list)) + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF; + else + CAM_DBG(CAM_ISP, "Still need to wait for the buf done"); + + CAM_DBG(CAM_ISP, "next Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + return rc; +} + +static int __cam_isp_ctx_rdi_only_sof_in_applied_state( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + struct cam_isp_hw_sof_event_data *sof_event_data = evt_data; + + if (!evt_data) { + CAM_ERR(CAM_ISP, "in valid sof event data"); + return -EINVAL; + } + + ctx_isp->frame_id++; + ctx_isp->sof_timestamp_val = sof_event_data->timestamp; + ctx_isp->boot_timestamp = sof_event_data->boot_time; + CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx", + ctx_isp->frame_id, ctx_isp->sof_timestamp_val); + + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE_APPLIED; + CAM_DBG(CAM_ISP, "next Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + + return 0; +} + +static int __cam_isp_ctx_rdi_only_sof_in_bubble_applied( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + struct cam_ctx_request *req; + struct cam_isp_ctx_req *req_isp; + struct cam_context *ctx = ctx_isp->base; + struct cam_isp_hw_sof_event_data *sof_event_data = evt_data; + uint64_t request_id = 0; + + /* + * Sof in bubble applied state means, reg update not received. + * before increment frame id and override time stamp value, send + * the previous sof time stamp that got captured in the + * sof in applied state. + */ + CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx", + ctx_isp->frame_id, ctx_isp->sof_timestamp_val); + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + + ctx_isp->frame_id++; + ctx_isp->sof_timestamp_val = sof_event_data->timestamp; + ctx_isp->boot_timestamp = sof_event_data->boot_time; + CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx", + ctx_isp->frame_id, ctx_isp->sof_timestamp_val); + + if (list_empty(&ctx->wait_req_list)) { + /* + * If no pending req in epoch, this is an error case. + * The recovery is to go back to sof state + */ + CAM_ERR(CAM_ISP, "No wait request"); + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF; + + /* Send SOF event as empty frame*/ + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + + goto end; + } + + req = list_first_entry(&ctx->wait_req_list, struct cam_ctx_request, + list); + req_isp = (struct cam_isp_ctx_req *)req->req_priv; + req_isp->bubble_detected = true; + CAM_INFO(CAM_ISP, "Ctx:%d Report Bubble flag %d req id:%lld", + ctx->ctx_id, req_isp->bubble_report, req->request_id); + req_isp->reapply = true; + + if (req_isp->bubble_report && ctx->ctx_crm_intf && + ctx->ctx_crm_intf->notify_err) { + struct cam_req_mgr_error_notify notify; + + notify.link_hdl = ctx->link_hdl; + notify.dev_hdl = ctx->dev_hdl; + notify.req_id = req->request_id; + notify.error = CRM_KMD_ERR_BUBBLE; + notify.trigger = 0; + if (ctx_isp->subscribe_event & CAM_TRIGGER_POINT_SOF) + notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.frame_id = ctx_isp->frame_id; + notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; + CAM_WARN(CAM_ISP, + "Notify CRM about Bubble req %lld frame %lld ctx %u", + req->request_id, + ctx_isp->frame_id, + ctx->ctx_id); + ctx->ctx_crm_intf->notify_err(¬ify); + atomic_set(&ctx_isp->process_bubble, 1); + } else { + req_isp->bubble_report = 0; + } + + /* + * Always move the request to active list. Let buf done + * function handles the rest. + */ + list_del_init(&req->list); + list_add_tail(&req->list, &ctx->active_req_list); + ctx_isp->active_req_cnt++; + CAM_DBG(CAM_ISP, "move request %lld to active list(cnt = %d)", + req->request_id, ctx_isp->active_req_cnt); + + if (!req_isp->bubble_report) { + if (req->request_id > ctx_isp->reported_req_id) { + request_id = req->request_id; + ctx_isp->reported_req_id = request_id; + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_ERROR); + } else + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + } else + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + + /* change the state to bubble, as reg update has not come */ + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE; + CAM_DBG(CAM_ISP, "next Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); +end: + return 0; +} + +static int __cam_isp_ctx_rdi_only_sof_in_bubble_state( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + uint32_t i; + struct cam_ctx_request *req; + struct cam_context *ctx = ctx_isp->base; + struct cam_req_mgr_trigger_notify notify; + struct cam_isp_hw_sof_event_data *sof_event_data = evt_data; + struct cam_isp_ctx_req *req_isp; + uint64_t request_id = 0; + + if (!evt_data) { + CAM_ERR(CAM_ISP, "in valid sof event data"); + return -EINVAL; + } + + ctx_isp->frame_id++; + ctx_isp->sof_timestamp_val = sof_event_data->timestamp; + ctx_isp->boot_timestamp = sof_event_data->boot_time; + CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx", + ctx_isp->frame_id, ctx_isp->sof_timestamp_val); + + + if (atomic_read(&ctx_isp->process_bubble)) { + if (list_empty(&ctx->active_req_list)) { + CAM_ERR(CAM_ISP, "No available active req in bubble"); + atomic_set(&ctx_isp->process_bubble, 0); + return -EINVAL; + } + + if (ctx_isp->last_sof_timestamp == + ctx_isp->sof_timestamp_val) { + CAM_DBG(CAM_ISP, + "Tasklet delay detected! Bubble frame: %lld check skipped, sof_timestamp: %lld, ctx_id: %d", + ctx_isp->frame_id, + ctx_isp->sof_timestamp_val, + ctx->ctx_id); + goto end; + } + + req = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + + if (req_isp->bubble_detected) { + req_isp->num_acked = 0; + req_isp->bubble_detected = false; + list_del_init(&req->list); + list_add(&req->list, &ctx->pending_req_list); + atomic_set(&ctx_isp->process_bubble, 0); + ctx_isp->active_req_cnt--; + CAM_DBG(CAM_REQ, + "Move active req: %lld to pending list(cnt = %d) [bubble re-apply],ctx %u", + req->request_id, + ctx_isp->active_req_cnt, ctx->ctx_id); + goto end; + } + } + + /* + * Signal all active requests with error and move the all the active + * requests to free list + */ + while (!list_empty(&ctx->active_req_list)) { + req = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + CAM_DBG(CAM_ISP, "signal fence in active list. fence num %d", + req_isp->num_fence_map_out); + for (i = 0; i < req_isp->num_fence_map_out; i++) + if (req_isp->fence_map_out[i].sync_id != -1) { + cam_sync_signal( + req_isp->fence_map_out[i].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + } + list_add_tail(&req->list, &ctx->free_req_list); + ctx_isp->active_req_cnt--; + } + +end: + /* notify reqmgr with sof signal */ + if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_trigger) { + notify.link_hdl = ctx->link_hdl; + notify.dev_hdl = ctx->dev_hdl; + notify.frame_id = ctx_isp->frame_id; + notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.req_id = ctx_isp->req_info.last_bufdone_req_id; + notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; + + ctx->ctx_crm_intf->notify_trigger(¬ify); + CAM_DBG(CAM_ISP, "Notify CRM SOF frame %lld", + ctx_isp->frame_id); + + } else { + CAM_ERR(CAM_ISP, "Can not notify SOF to CRM"); + } + + /* + * It is idle frame with out any applied request id, send + * request id as zero + */ + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF; + + CAM_DBG(CAM_ISP, "next Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + + ctx_isp->last_sof_timestamp = ctx_isp->sof_timestamp_val; + return 0; +} + +static int __cam_isp_ctx_rdi_only_reg_upd_in_bubble_applied_state( + struct cam_isp_context *ctx_isp, void *evt_data) +{ + struct cam_ctx_request *req; + struct cam_context *ctx = ctx_isp->base; + struct cam_isp_ctx_req *req_isp; + struct cam_req_mgr_trigger_notify notify; + uint64_t request_id = 0; + + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_EPOCH; + /* notify reqmgr with sof signal*/ + if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_trigger) { + if (list_empty(&ctx->wait_req_list)) { + CAM_ERR(CAM_ISP, "Reg upd ack with no waiting request"); + goto error; + } + req = list_first_entry(&ctx->wait_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + request_id = + (req_isp->hw_update_data.packet_opcode_type == + CAM_ISP_PACKET_INIT_DEV) ? + 0 : req->request_id; + + if (req_isp->num_fence_map_out != 0) { + list_add_tail(&req->list, &ctx->active_req_list); + ctx_isp->active_req_cnt++; + CAM_DBG(CAM_ISP, + "move request %lld to active list(cnt = %d)", + req->request_id, ctx_isp->active_req_cnt); + /* if packet has buffers, set correct request id */ + request_id = req->request_id; + } else { + /* no io config, so the request is completed. */ + list_add_tail(&req->list, &ctx->free_req_list); + CAM_DBG(CAM_ISP, + "move active req %lld to free list(cnt=%d)", + req->request_id, ctx_isp->active_req_cnt); + } + + notify.link_hdl = ctx->link_hdl; + notify.dev_hdl = ctx->dev_hdl; + notify.frame_id = ctx_isp->frame_id; + notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.req_id = ctx_isp->req_info.last_bufdone_req_id; + notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; + + ctx->ctx_crm_intf->notify_trigger(¬ify); + CAM_DBG(CAM_ISP, "Notify CRM SOF frame %lld", + ctx_isp->frame_id); + } else { + CAM_ERR(CAM_ISP, "Can not notify SOF to CRM"); + } + if (request_id) + ctx_isp->reported_req_id = request_id; + + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + CAM_DBG(CAM_ISP, "next Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_RUP, req); + return 0; +error: + /* Send SOF event as idle frame*/ + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, + CAM_REQ_MGR_SOF_EVENT_SUCCESS); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_RUP, NULL); + + /* + * There is no request in the pending list, move the sub state machine + * to SOF sub state + */ + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF; + + return 0; +} + +static struct cam_isp_ctx_irq_ops + cam_isp_ctx_rdi_only_activated_state_machine_irq + [CAM_ISP_CTX_ACTIVATED_MAX] = { + /* SOF */ + { + .irq_ops = { + NULL, + __cam_isp_ctx_rdi_only_sof_in_top_state, + __cam_isp_ctx_reg_upd_in_sof, + NULL, + NULL, + NULL, + }, + }, + /* APPLIED */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_rdi_only_sof_in_applied_state, + NULL, + NULL, + NULL, + __cam_isp_ctx_buf_done_in_applied, + }, + }, + /* EPOCH */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_rdi_only_sof_in_top_state, + NULL, + NULL, + NULL, + __cam_isp_ctx_buf_done_in_epoch, + }, + }, + /* BUBBLE*/ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_rdi_only_sof_in_bubble_state, + NULL, + NULL, + NULL, + __cam_isp_ctx_buf_done_in_bubble, + }, + }, + /* BUBBLE APPLIED ie PRE_BUBBLE */ + { + .irq_ops = { + __cam_isp_ctx_handle_error, + __cam_isp_ctx_rdi_only_sof_in_bubble_applied, + __cam_isp_ctx_rdi_only_reg_upd_in_bubble_applied_state, + NULL, + NULL, + __cam_isp_ctx_buf_done_in_bubble_applied, + }, + }, + /* HW ERROR */ + { + }, + /* HALT */ + { + }, +}; + +static int __cam_isp_ctx_rdi_only_apply_req_top_state( + struct cam_context *ctx, struct cam_req_mgr_apply_request *apply) +{ + int rc = 0; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + + CAM_DBG(CAM_ISP, "current Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + rc = __cam_isp_ctx_apply_req_in_activated_state(ctx, apply, + CAM_ISP_CTX_ACTIVATED_APPLIED); + CAM_DBG(CAM_ISP, "new Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + + if (rc) + CAM_ERR(CAM_ISP, "Apply failed in Substate[%s], rc %d", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated), rc); + + return rc; +} + +static struct cam_ctx_ops + cam_isp_ctx_rdi_only_activated_state_machine + [CAM_ISP_CTX_ACTIVATED_MAX] = { + /* SOF */ + { + .ioctl_ops = {}, + .crm_ops = { + .apply_req = __cam_isp_ctx_rdi_only_apply_req_top_state, + }, + .irq_ops = NULL, + }, + /* APPLIED */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* EPOCH */ + { + .ioctl_ops = {}, + .crm_ops = { + .apply_req = __cam_isp_ctx_rdi_only_apply_req_top_state, + }, + .irq_ops = NULL, + }, + /* PRE BUBBLE */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* BUBBLE */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* HW ERROR */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* HALT */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, +}; + +static int __cam_isp_ctx_release_hw_in_top_state(struct cam_context *ctx, + void *cmd) +{ + int rc = 0; + struct cam_hw_release_args rel_arg; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + struct cam_req_mgr_flush_request flush_req; + int i; + + if (ctx_isp->hw_ctx) { + rel_arg.ctxt_to_hw_map = ctx_isp->hw_ctx; + ctx->hw_mgr_intf->hw_release(ctx->hw_mgr_intf->hw_mgr_priv, + &rel_arg); + ctx_isp->hw_ctx = NULL; + } else { + CAM_ERR(CAM_ISP, "No hw resources acquired for this ctx"); + } + + ctx->last_flush_req = 0; + ctx_isp->frame_id = 0; + ctx_isp->active_req_cnt = 0; + ctx_isp->reported_req_id = 0; + ctx_isp->hw_acquired = false; + ctx_isp->init_received = false; + ctx_isp->req_info.last_bufdone_req_id = 0; + ctx_isp->last_sof_timestamp = 0; + + atomic64_set(&ctx_isp->state_monitor_head, -1); + + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx_isp->event_record_head[i], -1); + /* + * Ideally, we should never have any active request here. + * But we still add some sanity check code here to help the debug + */ + if (!list_empty(&ctx->active_req_list)) + CAM_WARN(CAM_ISP, "Active list is not empty"); + + /* Flush all the pending request list */ + flush_req.type = CAM_REQ_MGR_FLUSH_TYPE_ALL; + flush_req.link_hdl = ctx->link_hdl; + flush_req.dev_hdl = ctx->dev_hdl; + + CAM_DBG(CAM_ISP, "try to flush pending list"); + spin_lock_bh(&ctx->lock); + rc = __cam_isp_ctx_flush_req(ctx, &ctx->pending_req_list, &flush_req); + spin_unlock_bh(&ctx->lock); + ctx->state = CAM_CTX_ACQUIRED; + + trace_cam_context_state("ISP", ctx); + CAM_DBG(CAM_ISP, "Release device success[%u] next state %d", + ctx->ctx_id, ctx->state); + return rc; +} + +/* top level state machine */ +static int __cam_isp_ctx_release_dev_in_top_state(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc = 0; + int i; + struct cam_hw_release_args rel_arg; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + struct cam_req_mgr_flush_request flush_req; + + if (cmd && ctx_isp->hw_ctx) { + CAM_ERR(CAM_ISP, "releasing hw"); + __cam_isp_ctx_release_hw_in_top_state(ctx, NULL); + } + + if (ctx_isp->hw_ctx) { + rel_arg.ctxt_to_hw_map = ctx_isp->hw_ctx; + ctx->hw_mgr_intf->hw_release(ctx->hw_mgr_intf->hw_mgr_priv, + &rel_arg); + ctx_isp->hw_ctx = NULL; + } + + ctx->session_hdl = -1; + ctx->dev_hdl = -1; + ctx->link_hdl = -1; + ctx->ctx_crm_intf = NULL; + ctx->last_flush_req = 0; + ctx_isp->frame_id = 0; + ctx_isp->active_req_cnt = 0; + ctx_isp->reported_req_id = 0; + ctx_isp->hw_acquired = false; + ctx_isp->init_received = false; + ctx_isp->rdi_only_context = false; + ctx_isp->req_info.last_bufdone_req_id = 0; + ctx_isp->last_sof_timestamp = 0; + + atomic64_set(&ctx_isp->state_monitor_head, -1); + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx_isp->event_record_head[i], -1); + /* + * Ideally, we should never have any active request here. + * But we still add some sanity check code here to help the debug + */ + if (!list_empty(&ctx->active_req_list)) + CAM_ERR(CAM_ISP, "Active list is not empty"); + + /* Flush all the pending request list */ + flush_req.type = CAM_REQ_MGR_FLUSH_TYPE_ALL; + flush_req.link_hdl = ctx->link_hdl; + flush_req.dev_hdl = ctx->dev_hdl; + + CAM_DBG(CAM_ISP, "try to flush pending list"); + spin_lock_bh(&ctx->lock); + rc = __cam_isp_ctx_flush_req(ctx, &ctx->pending_req_list, &flush_req); + spin_unlock_bh(&ctx->lock); + ctx->state = CAM_CTX_AVAILABLE; + + trace_cam_context_state("ISP", ctx); + CAM_DBG(CAM_ISP, "Release device success[%u] next state %d", + ctx->ctx_id, ctx->state); + return rc; +} + +static int __cam_isp_ctx_config_dev_in_top_state( + struct cam_context *ctx, struct cam_config_dev_cmd *cmd) +{ + int rc = 0, i; + struct cam_ctx_request *req = NULL; + struct cam_isp_ctx_req *req_isp; + uintptr_t packet_addr; + struct cam_packet *packet; + size_t len = 0; + size_t remain_len = 0; + struct cam_hw_prepare_update_args cfg; + struct cam_req_mgr_add_request add_req; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + struct cam_hw_cmd_args hw_cmd_args; + struct cam_isp_hw_cmd_args isp_hw_cmd_args; + uint32_t packet_opcode = 0; + + CAM_DBG(CAM_ISP, "get free request object......"); + + /* get free request */ + spin_lock_bh(&ctx->lock); + if (!list_empty(&ctx->free_req_list)) { + req = list_first_entry(&ctx->free_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + } + spin_unlock_bh(&ctx->lock); + + if (!req) { + CAM_ERR(CAM_ISP, "No more request obj free"); + return -ENOMEM; + } + + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + + /* for config dev, only memory handle is supported */ + /* map packet from the memhandle */ + rc = cam_mem_get_cpu_buf((int32_t) cmd->packet_handle, + &packet_addr, &len); + if (rc != 0) { + CAM_ERR(CAM_ISP, "Can not get packet address"); + rc = -EINVAL; + goto free_req; + } + + remain_len = len; + if ((len < sizeof(struct cam_packet)) || + ((size_t)cmd->offset >= len - sizeof(struct cam_packet))) { + CAM_ERR(CAM_ISP, "invalid buff length: %zu or offset", len); + rc = -EINVAL; + goto free_req; + } + + remain_len -= (size_t)cmd->offset; + packet = (struct cam_packet *)(packet_addr + (uint32_t)cmd->offset); + CAM_DBG(CAM_ISP, "pack_handle %llx", cmd->packet_handle); + CAM_DBG(CAM_ISP, "packet address is 0x%zx", packet_addr); + CAM_DBG(CAM_ISP, "packet with length %zu, offset 0x%llx", + len, cmd->offset); + CAM_DBG(CAM_ISP, "Packet request id %lld", + packet->header.request_id); + CAM_DBG(CAM_ISP, "Packet size 0x%x", packet->header.size); + CAM_DBG(CAM_ISP, "packet op %d", packet->header.op_code); + + /* Query the packet opcode */ + hw_cmd_args.ctxt_to_hw_map = ctx_isp->hw_ctx; + hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; + isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_GET_PACKET_OPCODE; + isp_hw_cmd_args.cmd_data = (void *)packet; + hw_cmd_args.u.internal_args = (void *)&isp_hw_cmd_args; + rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &hw_cmd_args); + if (rc) { + CAM_ERR(CAM_ISP, "HW command failed"); + goto free_req; + } + + packet_opcode = isp_hw_cmd_args.u.packet_op_code; + CAM_DBG(CAM_ISP, "packet op %d", packet_opcode); + + if ((packet_opcode == CAM_ISP_PACKET_UPDATE_DEV) + && (packet->header.request_id <= ctx->last_flush_req)) { + CAM_INFO(CAM_ISP, + "request %lld has been flushed, reject packet", + packet->header.request_id); + rc = -EBADR; + goto free_req; + } + + /* preprocess the configuration */ + memset(&cfg, 0, sizeof(cfg)); + cfg.packet = packet; + cfg.remain_len = remain_len; + cfg.ctxt_to_hw_map = ctx_isp->hw_ctx; + cfg.max_hw_update_entries = CAM_ISP_CTX_CFG_MAX; + cfg.hw_update_entries = req_isp->cfg; + cfg.max_out_map_entries = CAM_ISP_CTX_RES_MAX; + cfg.max_in_map_entries = CAM_ISP_CTX_RES_MAX; + cfg.out_map_entries = req_isp->fence_map_out; + cfg.in_map_entries = req_isp->fence_map_in; + cfg.priv = &req_isp->hw_update_data; + cfg.pf_data = &(req->pf_data); + + CAM_DBG(CAM_ISP, "try to prepare config packet......"); + + rc = ctx->hw_mgr_intf->hw_prepare_update( + ctx->hw_mgr_intf->hw_mgr_priv, &cfg); + if (rc != 0) { + CAM_ERR(CAM_ISP, "Prepare config packet failed in HW layer"); + rc = -EFAULT; + goto free_req; + } + req_isp->num_cfg = cfg.num_hw_update_entries; + req_isp->num_fence_map_out = cfg.num_out_map_entries; + req_isp->num_fence_map_in = cfg.num_in_map_entries; + req_isp->num_acked = 0; + req_isp->bubble_detected = false; + req_isp->hw_update_data.packet = packet; + + for (i = 0; i < req_isp->num_fence_map_out; i++) { + rc = cam_sync_get_obj_ref(req_isp->fence_map_out[i].sync_id); + if (rc) { + CAM_ERR(CAM_ISP, "Can't get ref for fence %d", + req_isp->fence_map_out[i].sync_id); + goto put_ref; + } + } + + CAM_DBG(CAM_ISP, "num_entry: %d, num fence out: %d, num fence in: %d", + req_isp->num_cfg, req_isp->num_fence_map_out, + req_isp->num_fence_map_in); + + req->request_id = packet->header.request_id; + req->status = 1; + + CAM_DBG(CAM_ISP, "Packet request id %lld packet opcode:%d", + packet->header.request_id, + req_isp->hw_update_data.packet_opcode_type); + + if (req_isp->hw_update_data.packet_opcode_type == + CAM_ISP_PACKET_INIT_DEV) { + if (ctx->state < CAM_CTX_ACTIVATED) { + rc = __cam_isp_ctx_enqueue_init_request(ctx, req); + if (rc) + CAM_ERR(CAM_ISP, "Enqueue INIT pkt failed"); + ctx_isp->init_received = true; + } else { + rc = -EINVAL; + CAM_ERR(CAM_ISP, "Recevied INIT pkt in wrong state:%d", + ctx->state); + } + } else { + if (ctx->state != CAM_CTX_FLUSHED && ctx->state >= CAM_CTX_READY + && ctx->ctx_crm_intf->add_req) { + add_req.link_hdl = ctx->link_hdl; + add_req.dev_hdl = ctx->dev_hdl; + add_req.req_id = req->request_id; + add_req.skip_before_applying = 0; + rc = ctx->ctx_crm_intf->add_req(&add_req); + if (rc) { + CAM_ERR(CAM_ISP, "Add req failed: req id=%llu", + req->request_id); + } else { + __cam_isp_ctx_enqueue_request_in_order( + ctx, req); + } + } else { + rc = -EINVAL; + CAM_ERR(CAM_ISP, + "Recevied update req %lld in wrong state:%d", + req->request_id, ctx->state); + } + } + if (rc) + goto put_ref; + + CAM_DBG(CAM_REQ, + "Preprocessing Config req_id %lld successful on ctx %u", + req->request_id, ctx->ctx_id); + + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); + return rc; + +put_ref: + for (--i; i >= 0; i--) { + if (cam_sync_put_obj_ref(req_isp->fence_map_out[i].sync_id)) + CAM_ERR(CAM_CTXT, "Failed to put ref of fence %d", + req_isp->fence_map_out[i].sync_id); + } +free_req: + spin_lock_bh(&ctx->lock); + list_add_tail(&req->list, &ctx->free_req_list); + spin_unlock_bh(&ctx->lock); + + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); + return rc; +} + +static int __cam_isp_ctx_acquire_dev_in_available(struct cam_context *ctx, + struct cam_acquire_dev_cmd *cmd) +{ + int rc = 0; + int i; + struct cam_hw_acquire_args param; + struct cam_isp_resource *isp_res = NULL; + struct cam_create_dev_hdl req_hdl_param; + struct cam_hw_release_args release; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + struct cam_hw_cmd_args hw_cmd_args; + struct cam_isp_hw_cmd_args isp_hw_cmd_args; + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_ISP, "HW interface is not ready"); + rc = -EFAULT; + goto end; + } + + CAM_DBG(CAM_ISP, + "session_hdl 0x%x, num_resources %d, hdl type %d, res %lld", + cmd->session_handle, cmd->num_resources, + cmd->handle_type, cmd->resource_hdl); + + if (cmd->num_resources == CAM_API_COMPAT_CONSTANT) { + ctx_isp->split_acquire = true; + CAM_DBG(CAM_ISP, "Acquire dev handle"); + goto get_dev_handle; + } + + if (cmd->num_resources > CAM_ISP_CTX_RES_MAX) { + CAM_ERR(CAM_ISP, "Too much resources in the acquire"); + rc = -ENOMEM; + goto end; + } + + /* for now we only support user pointer */ + if (cmd->handle_type != 1) { + CAM_ERR(CAM_ISP, "Only user pointer is supported"); + rc = -EINVAL; + goto end; + } + + isp_res = kzalloc( + sizeof(*isp_res)*cmd->num_resources, GFP_KERNEL); + if (!isp_res) { + rc = -ENOMEM; + goto end; + } + + CAM_DBG(CAM_ISP, "start copy %d resources from user", + cmd->num_resources); + + if (copy_from_user(isp_res, u64_to_user_ptr(cmd->resource_hdl), + sizeof(*isp_res)*cmd->num_resources)) { + rc = -EFAULT; + goto free_res; + } + + param.context_data = ctx; + param.event_cb = ctx->irq_cb_intf; + param.num_acq = cmd->num_resources; + param.acquire_info = (uintptr_t) isp_res; + + /* call HW manager to reserve the resource */ + rc = ctx->hw_mgr_intf->hw_acquire(ctx->hw_mgr_intf->hw_mgr_priv, + ¶m); + if (rc != 0) { + CAM_ERR(CAM_ISP, "Acquire device failed"); + goto free_res; + } + + /* Query the context has rdi only resource */ + hw_cmd_args.ctxt_to_hw_map = param.ctxt_to_hw_map; + hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; + isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_CMD_CTX_TYPE; + hw_cmd_args.u.internal_args = (void *)&isp_hw_cmd_args; + rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &hw_cmd_args); + if (rc) { + CAM_ERR(CAM_ISP, "HW command failed"); + goto free_hw; + } + + if (isp_hw_cmd_args.u.ctx_type == CAM_ISP_CTX_RDI) { + /* + * this context has rdi only resource assign rdi only + * state machine + */ + CAM_DBG(CAM_ISP, "RDI only session Context"); + + ctx_isp->substate_machine_irq = + cam_isp_ctx_rdi_only_activated_state_machine_irq; + ctx_isp->substate_machine = + cam_isp_ctx_rdi_only_activated_state_machine; + ctx_isp->rdi_only_context = true; + } else if (isp_hw_cmd_args.u.ctx_type == CAM_ISP_CTX_FS2) { + CAM_DBG(CAM_ISP, "FS2 Session has PIX ,RD and RDI"); + ctx_isp->substate_machine_irq = + cam_isp_ctx_fs2_state_machine_irq; + ctx_isp->substate_machine = + cam_isp_ctx_fs2_state_machine; + } else { + CAM_DBG(CAM_ISP, "Session has PIX or PIX and RDI resources"); + ctx_isp->substate_machine_irq = + cam_isp_ctx_activated_state_machine_irq; + ctx_isp->substate_machine = + cam_isp_ctx_activated_state_machine; + } + + ctx_isp->hw_ctx = param.ctxt_to_hw_map; + ctx_isp->hw_acquired = true; + ctx_isp->split_acquire = false; + ctx->ctxt_to_hw_map = param.ctxt_to_hw_map; + ctx_isp->last_sof_timestamp = 0; + + atomic64_set(&ctx_isp->state_monitor_head, -1); + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx_isp->event_record_head[i], -1); + + kfree(isp_res); + isp_res = NULL; + +get_dev_handle: + + req_hdl_param.session_hdl = cmd->session_handle; + /* bridge is not ready for these flags. so false for now */ + req_hdl_param.v4l2_sub_dev_flag = 0; + req_hdl_param.media_entity_flag = 0; + req_hdl_param.ops = ctx->crm_ctx_intf; + req_hdl_param.priv = ctx; + req_hdl_param.dev_id = CAM_ISP; + CAM_DBG(CAM_ISP, "get device handle form bridge"); + ctx->dev_hdl = cam_create_device_hdl(&req_hdl_param); + if (ctx->dev_hdl <= 0) { + rc = -EFAULT; + CAM_ERR(CAM_ISP, "Can not create device handle"); + goto free_hw; + } + cmd->dev_handle = ctx->dev_hdl; + + /* store session information */ + ctx->session_hdl = cmd->session_handle; + ctx->state = CAM_CTX_ACQUIRED; + + trace_cam_context_state("ISP", ctx); + CAM_DBG(CAM_ISP, + "Acquire success on session_hdl 0x%x num_rsrces %d ctx %u", + cmd->session_handle, cmd->num_resources, ctx->ctx_id); + + return rc; + +free_hw: + release.ctxt_to_hw_map = ctx_isp->hw_ctx; + if (ctx_isp->hw_acquired) + ctx->hw_mgr_intf->hw_release(ctx->hw_mgr_intf->hw_mgr_priv, + &release); + ctx_isp->hw_ctx = NULL; + ctx_isp->hw_acquired = false; +free_res: + kfree(isp_res); +end: + return rc; +} + +static int __cam_isp_ctx_acquire_hw_v1(struct cam_context *ctx, + void *args) +{ + int rc = 0; + int i; + struct cam_acquire_hw_cmd_v1 *cmd = + (struct cam_acquire_hw_cmd_v1 *)args; + struct cam_hw_acquire_args param; + struct cam_hw_release_args release; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + struct cam_hw_cmd_args hw_cmd_args; + struct cam_isp_hw_cmd_args isp_hw_cmd_args; + struct cam_isp_acquire_hw_info *acquire_hw_info = NULL; + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_ISP, "HW interface is not ready"); + rc = -EFAULT; + goto end; + } + + CAM_DBG(CAM_ISP, + "session_hdl 0x%x, hdl type %d, res %lld", + cmd->session_handle, cmd->handle_type, cmd->resource_hdl); + + /* for now we only support user pointer */ + if (cmd->handle_type != 1) { + CAM_ERR(CAM_ISP, "Only user pointer is supported"); + rc = -EINVAL; + goto end; + } + + if (cmd->data_size < sizeof(*acquire_hw_info)) { + CAM_ERR(CAM_ISP, "data_size is not a valid value"); + goto end; + } + + acquire_hw_info = kzalloc(cmd->data_size, GFP_KERNEL); + if (!acquire_hw_info) { + rc = -ENOMEM; + goto end; + } + + CAM_DBG(CAM_ISP, "start copy resources from user"); + + if (copy_from_user(acquire_hw_info, (void __user *)cmd->resource_hdl, + cmd->data_size)) { + rc = -EFAULT; + goto free_res; + } + + memset(¶m, 0, sizeof(param)); + param.context_data = ctx; + param.event_cb = ctx->irq_cb_intf; + param.num_acq = CAM_API_COMPAT_CONSTANT; + param.acquire_info_size = cmd->data_size; + param.acquire_info = (uint64_t) acquire_hw_info; + + /* call HW manager to reserve the resource */ + rc = ctx->hw_mgr_intf->hw_acquire(ctx->hw_mgr_intf->hw_mgr_priv, + ¶m); + if (rc != 0) { + CAM_ERR(CAM_ISP, "Acquire device failed"); + goto free_res; + } + + /* Query the context has rdi only resource */ + hw_cmd_args.ctxt_to_hw_map = param.ctxt_to_hw_map; + hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; + isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_CMD_CTX_TYPE; + hw_cmd_args.u.internal_args = (void *)&isp_hw_cmd_args; + rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &hw_cmd_args); + if (rc) { + CAM_ERR(CAM_ISP, "HW command failed"); + goto free_hw; + } + + if (isp_hw_cmd_args.u.ctx_type == CAM_ISP_CTX_RDI) { + /* + * this context has rdi only resource assign rdi only + * state machine + */ + CAM_DBG(CAM_ISP, "RDI only session Context"); + + ctx_isp->substate_machine_irq = + cam_isp_ctx_rdi_only_activated_state_machine_irq; + ctx_isp->substate_machine = + cam_isp_ctx_rdi_only_activated_state_machine; + ctx_isp->rdi_only_context = true; + } else if (isp_hw_cmd_args.u.ctx_type == CAM_ISP_CTX_FS2) { + CAM_DBG(CAM_ISP, "FS2 Session has PIX ,RD and RDI"); + ctx_isp->substate_machine_irq = + cam_isp_ctx_fs2_state_machine_irq; + ctx_isp->substate_machine = + cam_isp_ctx_fs2_state_machine; + } else { + CAM_DBG(CAM_ISP, "Session has PIX or PIX and RDI resources"); + ctx_isp->substate_machine_irq = + cam_isp_ctx_activated_state_machine_irq; + ctx_isp->substate_machine = + cam_isp_ctx_activated_state_machine; + } + + ctx_isp->hw_ctx = param.ctxt_to_hw_map; + ctx_isp->hw_acquired = true; + ctx->ctxt_to_hw_map = param.ctxt_to_hw_map; + ctx_isp->last_sof_timestamp = 0; + + atomic64_set(&ctx_isp->state_monitor_head, -1); + + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx_isp->event_record_head[i], -1); + + trace_cam_context_state("ISP", ctx); + CAM_DBG(CAM_ISP, + "Acquire success on session_hdl 0x%xs ctx_type %d ctx_id %u", + ctx->session_hdl, isp_hw_cmd_args.u.ctx_type, ctx->ctx_id); + kfree(acquire_hw_info); + return rc; + +free_hw: + release.ctxt_to_hw_map = ctx_isp->hw_ctx; + ctx->hw_mgr_intf->hw_release(ctx->hw_mgr_intf->hw_mgr_priv, &release); + ctx_isp->hw_ctx = NULL; + ctx_isp->hw_acquired = false; +free_res: + kfree(acquire_hw_info); +end: + return rc; +} + +static int __cam_isp_ctx_acquire_hw_v2(struct cam_context *ctx, + void *args) +{ + int rc = 0, i, j; + struct cam_acquire_hw_cmd_v2 *cmd = + (struct cam_acquire_hw_cmd_v2 *)args; + struct cam_hw_acquire_args param; + struct cam_hw_release_args release; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + struct cam_hw_cmd_args hw_cmd_args; + struct cam_isp_hw_cmd_args isp_hw_cmd_args; + struct cam_isp_acquire_hw_info *acquire_hw_info = NULL; + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_ISP, "HW interface is not ready"); + rc = -EFAULT; + goto end; + } + + CAM_DBG(CAM_ISP, + "session_hdl 0x%x, hdl type %d, res %lld", + cmd->session_handle, cmd->handle_type, cmd->resource_hdl); + + /* for now we only support user pointer */ + if (cmd->handle_type != 1) { + CAM_ERR(CAM_ISP, "Only user pointer is supported"); + rc = -EINVAL; + goto end; + } + + if (cmd->data_size < sizeof(*acquire_hw_info)) { + CAM_ERR(CAM_ISP, "data_size is not a valid value"); + goto end; + } + + acquire_hw_info = kzalloc(cmd->data_size, GFP_KERNEL); + if (!acquire_hw_info) { + rc = -ENOMEM; + goto end; + } + + CAM_DBG(CAM_ISP, "start copy resources from user"); + + if (copy_from_user(acquire_hw_info, (void __user *)cmd->resource_hdl, + cmd->data_size)) { + rc = -EFAULT; + goto free_res; + } + + memset(¶m, 0, sizeof(param)); + param.context_data = ctx; + param.event_cb = ctx->irq_cb_intf; + param.num_acq = CAM_API_COMPAT_CONSTANT; + param.acquire_info_size = cmd->data_size; + param.acquire_info = (uint64_t) acquire_hw_info; + + /* call HW manager to reserve the resource */ + rc = ctx->hw_mgr_intf->hw_acquire(ctx->hw_mgr_intf->hw_mgr_priv, + ¶m); + if (rc != 0) { + CAM_ERR(CAM_ISP, "Acquire device failed"); + goto free_res; + } + + /* Query the context has rdi only resource */ + hw_cmd_args.ctxt_to_hw_map = param.ctxt_to_hw_map; + hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; + isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_CMD_CTX_TYPE; + hw_cmd_args.u.internal_args = (void *)&isp_hw_cmd_args; + rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &hw_cmd_args); + if (rc) { + CAM_ERR(CAM_ISP, "HW command failed"); + goto free_hw; + } + + if (param.valid_acquired_hw) { + for (i = 0; i < CAM_MAX_ACQ_RES; i++) + cmd->hw_info.acquired_hw_id[i] = + param.acquired_hw_id[i]; + + for (i = 0; i < CAM_MAX_ACQ_RES; i++) + for (j = 0; j < CAM_MAX_HW_SPLIT; j++) + cmd->hw_info.acquired_hw_path[i][j] = + param.acquired_hw_path[i][j]; + } + cmd->hw_info.valid_acquired_hw = + param.valid_acquired_hw; + + cmd->hw_info.valid_acquired_hw = param.valid_acquired_hw; + + if (isp_hw_cmd_args.u.ctx_type == CAM_ISP_CTX_RDI) { + /* + * this context has rdi only resource assign rdi only + * state machine + */ + CAM_DBG(CAM_ISP, "RDI only session Context"); + + ctx_isp->substate_machine_irq = + cam_isp_ctx_rdi_only_activated_state_machine_irq; + ctx_isp->substate_machine = + cam_isp_ctx_rdi_only_activated_state_machine; + ctx_isp->rdi_only_context = true; + } else if (isp_hw_cmd_args.u.ctx_type == CAM_ISP_CTX_FS2) { + CAM_DBG(CAM_ISP, "FS2 Session has PIX ,RD and RDI"); + ctx_isp->substate_machine_irq = + cam_isp_ctx_fs2_state_machine_irq; + ctx_isp->substate_machine = + cam_isp_ctx_fs2_state_machine; + } else { + CAM_DBG(CAM_ISP, "Session has PIX or PIX and RDI resources"); + ctx_isp->substate_machine_irq = + cam_isp_ctx_activated_state_machine_irq; + ctx_isp->substate_machine = + cam_isp_ctx_activated_state_machine; + } + + ctx_isp->hw_ctx = param.ctxt_to_hw_map; + ctx_isp->hw_acquired = true; + ctx->ctxt_to_hw_map = param.ctxt_to_hw_map; + ctx_isp->last_sof_timestamp = 0; + + trace_cam_context_state("ISP", ctx); + CAM_DBG(CAM_ISP, + "Acquire success on session_hdl 0x%xs ctx_type %d ctx_id %u", + ctx->session_hdl, isp_hw_cmd_args.u.ctx_type, ctx->ctx_id); + kfree(acquire_hw_info); + return rc; + +free_hw: + release.ctxt_to_hw_map = ctx_isp->hw_ctx; + ctx->hw_mgr_intf->hw_release(ctx->hw_mgr_intf->hw_mgr_priv, &release); + ctx_isp->hw_ctx = NULL; + ctx_isp->hw_acquired = false; +free_res: + kfree(acquire_hw_info); +end: + return rc; +} + +static int __cam_isp_ctx_acquire_hw_in_acquired(struct cam_context *ctx, + void *args) +{ + int rc = -EINVAL; + uint32_t api_version; + + if (!ctx || !args) { + CAM_ERR(CAM_ISP, "Invalid input pointer"); + return rc; + } + + api_version = *((uint32_t *)args); + if (api_version == 1) + rc = __cam_isp_ctx_acquire_hw_v1(ctx, args); + else if (api_version == 2) + rc = __cam_isp_ctx_acquire_hw_v2(ctx, args); + else + CAM_ERR(CAM_ISP, "Unsupported api version %d", api_version); + + return rc; +} + +static int __cam_isp_ctx_config_dev_in_acquired(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + int rc = 0; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + + if (!ctx_isp->hw_acquired) { + CAM_ERR(CAM_ISP, "HW is not acquired, reject packet"); + return -EINVAL; + } + + rc = __cam_isp_ctx_config_dev_in_top_state(ctx, cmd); + + if (!rc && (ctx->link_hdl >= 0)) { + ctx->state = CAM_CTX_READY; + trace_cam_context_state("ISP", ctx); + } + + CAM_DBG(CAM_ISP, "next state %d", ctx->state); + return rc; +} + +static int __cam_isp_ctx_config_dev_in_flushed(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + int rc = 0; + struct cam_start_stop_dev_cmd start_cmd; + struct cam_hw_cmd_args hw_cmd_args; + struct cam_isp_hw_cmd_args isp_hw_cmd_args; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + + if (!ctx_isp->hw_acquired) { + CAM_ERR(CAM_ISP, "HW is not acquired, reject packet"); + rc = -EINVAL; + goto end; + } + + rc = __cam_isp_ctx_config_dev_in_top_state(ctx, cmd); + if (rc) + goto end; + + if (!ctx_isp->init_received) { + CAM_WARN(CAM_ISP, + "Received update packet in flushed state, skip start"); + goto end; + } + + hw_cmd_args.ctxt_to_hw_map = ctx_isp->hw_ctx; + hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; + isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_CMD_RESUME_HW; + hw_cmd_args.u.internal_args = (void *)&isp_hw_cmd_args; + rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &hw_cmd_args); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to resume HW rc: %d", rc); + goto end; + } + + start_cmd.dev_handle = cmd->dev_handle; + start_cmd.session_handle = cmd->session_handle; + rc = __cam_isp_ctx_start_dev_in_ready(ctx, &start_cmd); + if (rc) + CAM_ERR(CAM_ISP, + "Failed to re-start HW after flush rc: %d", rc); + else + CAM_INFO(CAM_ISP, + "Received init after flush. Re-start HW complete."); + +end: + CAM_DBG(CAM_ISP, "next state %d sub_state:%d", ctx->state, + ctx_isp->substate_activated); + return rc; +} + +static int __cam_isp_ctx_link_in_acquired(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *link) +{ + int rc = 0; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + + CAM_DBG(CAM_ISP, "Enter........."); + + ctx->link_hdl = link->link_hdl; + ctx->ctx_crm_intf = link->crm_cb; + ctx_isp->subscribe_event = link->subscribe_event; + + /* change state only if we had the init config */ + if (ctx_isp->init_received) { + ctx->state = CAM_CTX_READY; + trace_cam_context_state("ISP", ctx); + } + + CAM_DBG(CAM_ISP, "next state %d", ctx->state); + + return rc; +} + +static int __cam_isp_ctx_unlink_in_acquired(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *unlink) +{ + int rc = 0; + + ctx->link_hdl = -1; + ctx->ctx_crm_intf = NULL; + + return rc; +} + +static int __cam_isp_ctx_get_dev_info_in_acquired(struct cam_context *ctx, + struct cam_req_mgr_device_info *dev_info) +{ + int rc = 0; + + dev_info->dev_hdl = ctx->dev_hdl; + strlcpy(dev_info->name, CAM_ISP_DEV_NAME, sizeof(dev_info->name)); + dev_info->dev_id = CAM_REQ_MGR_DEVICE_IFE; + dev_info->p_delay = 1; + dev_info->trigger = CAM_TRIGGER_POINT_SOF; + + return rc; +} + +static int __cam_isp_ctx_start_dev_in_ready(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc = 0; + int i; + struct cam_isp_start_args start_isp; + struct cam_ctx_request *req; + struct cam_isp_ctx_req *req_isp; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + + if (cmd->session_handle != ctx->session_hdl || + cmd->dev_handle != ctx->dev_hdl) { + rc = -EPERM; + goto end; + } + + if (list_empty(&ctx->pending_req_list)) { + /* should never happen */ + CAM_ERR(CAM_ISP, "Start device with empty configuration"); + rc = -EFAULT; + goto end; + } else { + req = list_first_entry(&ctx->pending_req_list, + struct cam_ctx_request, list); + } + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + + if (!ctx_isp->hw_ctx) { + CAM_ERR(CAM_ISP, "Wrong hw context pointer."); + rc = -EFAULT; + goto end; + } + + start_isp.hw_config.ctxt_to_hw_map = ctx_isp->hw_ctx; + start_isp.hw_config.request_id = req->request_id; + start_isp.hw_config.hw_update_entries = req_isp->cfg; + start_isp.hw_config.num_hw_update_entries = req_isp->num_cfg; + start_isp.hw_config.priv = &req_isp->hw_update_data; + start_isp.hw_config.init_packet = 1; + start_isp.hw_config.reapply = 0; + + ctx_isp->last_applied_req_id = req->request_id; + + if (ctx->state == CAM_CTX_FLUSHED) + start_isp.start_only = true; + else + start_isp.start_only = false; + + atomic_set(&ctx_isp->process_bubble, 0); + ctx_isp->frame_id = 0; + ctx_isp->active_req_cnt = 0; + ctx_isp->reported_req_id = 0; + ctx_isp->bubble_frame_cnt = 0; + ctx_isp->substate_activated = ctx_isp->rdi_only_context ? + CAM_ISP_CTX_ACTIVATED_APPLIED : + (req_isp->num_fence_map_out) ? CAM_ISP_CTX_ACTIVATED_EPOCH : + CAM_ISP_CTX_ACTIVATED_SOF; + + atomic64_set(&ctx_isp->state_monitor_head, -1); + + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx_isp->event_record_head[i], -1); + + /* + * In case of CSID TPG we might receive SOF and RUP IRQs + * before hw_mgr_intf->hw_start has returned. So move + * req out of pending list before hw_start and add it + * back to pending list if hw_start fails. + */ + list_del_init(&req->list); + + if (ctx_isp->rdi_only_context || !req_isp->num_fence_map_out) { + list_add_tail(&req->list, &ctx->wait_req_list); + } else { + list_add_tail(&req->list, &ctx->active_req_list); + ctx_isp->active_req_cnt++; + } + + /* + * Only place to change state before calling the hw due to + * hardware tasklet has higher priority that can cause the + * irq handling comes early + */ + ctx->state = CAM_CTX_ACTIVATED; + trace_cam_context_state("ISP", ctx); + rc = ctx->hw_mgr_intf->hw_start(ctx->hw_mgr_intf->hw_mgr_priv, + &start_isp); + if (rc) { + /* HW failure. user need to clean up the resource */ + CAM_ERR(CAM_ISP, "Start HW failed"); + ctx->state = CAM_CTX_READY; + if ((rc == -ETIMEDOUT) && + (isp_ctx_debug.enable_cdm_cmd_buff_dump)) + rc = cam_isp_ctx_dump_req(req_isp, 0, 0, NULL, false); + + trace_cam_context_state("ISP", ctx); + list_del_init(&req->list); + list_add(&req->list, &ctx->pending_req_list); + goto end; + } + CAM_DBG(CAM_ISP, "start device success ctx %u", ctx->ctx_id); + +end: + return rc; +} + +static int __cam_isp_ctx_unlink_in_ready(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *unlink) +{ + int rc = 0; + + ctx->link_hdl = -1; + ctx->ctx_crm_intf = NULL; + ctx->state = CAM_CTX_ACQUIRED; + trace_cam_context_state("ISP", ctx); + + return rc; +} + +static int __cam_isp_ctx_stop_dev_in_activated_unlock( + struct cam_context *ctx, struct cam_start_stop_dev_cmd *stop_cmd) +{ + int rc = 0; + uint32_t i; + struct cam_hw_stop_args stop; + struct cam_ctx_request *req; + struct cam_isp_ctx_req *req_isp; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + struct cam_isp_stop_args stop_isp; + + /* stop hw first */ + if (ctx_isp->hw_ctx) { + stop.ctxt_to_hw_map = ctx_isp->hw_ctx; + + if (stop_cmd) + stop_isp.hw_stop_cmd = + CAM_ISP_HW_STOP_AT_FRAME_BOUNDARY; + else + stop_isp.hw_stop_cmd = CAM_ISP_HW_STOP_IMMEDIATELY; + + stop_isp.stop_only = false; + stop.args = (void *) &stop_isp; + ctx->hw_mgr_intf->hw_stop(ctx->hw_mgr_intf->hw_mgr_priv, + &stop); + } + + /* Mask off all the incoming hardware events */ + spin_lock_bh(&ctx->lock); + ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_HALT; + spin_unlock_bh(&ctx->lock); + CAM_DBG(CAM_ISP, "next Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + + if (ctx->ctx_crm_intf && + ctx->ctx_crm_intf->notify_stop) { + struct cam_req_mgr_notify_stop notify; + + notify.link_hdl = ctx->link_hdl; + CAM_DBG(CAM_ISP, + "Notify CRM about device stop ctx %u link 0x%x", + ctx->ctx_id, ctx->link_hdl); + ctx->ctx_crm_intf->notify_stop(¬ify); + } else + CAM_ERR(CAM_ISP, "cb not present"); + + while (!list_empty(&ctx->pending_req_list)) { + req = list_first_entry(&ctx->pending_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + CAM_DBG(CAM_ISP, "signal fence in pending list. fence num %d", + req_isp->num_fence_map_out); + for (i = 0; i < req_isp->num_fence_map_out; i++) + if (req_isp->fence_map_out[i].sync_id != -1) { + cam_sync_signal( + req_isp->fence_map_out[i].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + } + list_add_tail(&req->list, &ctx->free_req_list); + } + + while (!list_empty(&ctx->wait_req_list)) { + req = list_first_entry(&ctx->wait_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + CAM_DBG(CAM_ISP, "signal fence in wait list. fence num %d", + req_isp->num_fence_map_out); + for (i = 0; i < req_isp->num_fence_map_out; i++) + if (req_isp->fence_map_out[i].sync_id != -1) { + cam_sync_signal( + req_isp->fence_map_out[i].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + } + list_add_tail(&req->list, &ctx->free_req_list); + } + + while (!list_empty(&ctx->active_req_list)) { + req = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + list_del_init(&req->list); + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + CAM_DBG(CAM_ISP, "signal fence in active list. fence num %d", + req_isp->num_fence_map_out); + for (i = 0; i < req_isp->num_fence_map_out; i++) + if (req_isp->fence_map_out[i].sync_id != -1) { + cam_sync_signal( + req_isp->fence_map_out[i].sync_id, + CAM_SYNC_STATE_SIGNALED_ERROR); + } + list_add_tail(&req->list, &ctx->free_req_list); + } + + ctx_isp->frame_id = 0; + ctx_isp->active_req_cnt = 0; + ctx_isp->reported_req_id = 0; + ctx_isp->bubble_frame_cnt = 0; + ctx_isp->last_applied_req_id = 0; + ctx_isp->req_info.last_bufdone_req_id = 0; + atomic_set(&ctx_isp->process_bubble, 0); + atomic64_set(&ctx_isp->state_monitor_head, -1); + + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx_isp->event_record_head[i], -1); + + CAM_DBG(CAM_ISP, "Stop device success next state %d on ctx %u", + ctx->state, ctx->ctx_id); + + if (!stop_cmd) { + rc = __cam_isp_ctx_unlink_in_ready(ctx, NULL); + if (rc) + CAM_ERR(CAM_ISP, "Unlink failed rc=%d", rc); + } + return rc; +} + +static int __cam_isp_ctx_stop_dev_in_activated(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc = 0; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *)ctx->ctx_priv; + + __cam_isp_ctx_stop_dev_in_activated_unlock(ctx, cmd); + ctx_isp->init_received = false; + ctx->state = CAM_CTX_ACQUIRED; + trace_cam_context_state("ISP", ctx); + return rc; +} + +static int __cam_isp_ctx_release_dev_in_activated(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc = 0; + + rc = __cam_isp_ctx_stop_dev_in_activated_unlock(ctx, NULL); + if (rc) + CAM_ERR(CAM_ISP, "Stop device failed rc=%d", rc); + + rc = __cam_isp_ctx_release_dev_in_top_state(ctx, cmd); + if (rc) + CAM_ERR(CAM_ISP, "Release device failed rc=%d", rc); + + return rc; +} + +static int __cam_isp_ctx_release_hw_in_activated(struct cam_context *ctx, + void *cmd) +{ + int rc = 0; + + rc = __cam_isp_ctx_stop_dev_in_activated_unlock(ctx, NULL); + if (rc) + CAM_ERR(CAM_ISP, "Stop device failed rc=%d", rc); + + rc = __cam_isp_ctx_release_hw_in_top_state(ctx, cmd); + if (rc) + CAM_ERR(CAM_ISP, "Release hw failed rc=%d", rc); + + return rc; +} + +static int __cam_isp_ctx_link_pause(struct cam_context *ctx) +{ + int rc = 0; + struct cam_hw_cmd_args hw_cmd_args; + struct cam_isp_hw_cmd_args isp_hw_cmd_args; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + + hw_cmd_args.ctxt_to_hw_map = ctx_isp->hw_ctx; + hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; + isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_CMD_PAUSE_HW; + hw_cmd_args.u.internal_args = (void *)&isp_hw_cmd_args; + rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &hw_cmd_args); + + return rc; +} + +static int __cam_isp_ctx_link_resume(struct cam_context *ctx) +{ + int rc = 0; + struct cam_hw_cmd_args hw_cmd_args; + struct cam_isp_hw_cmd_args isp_hw_cmd_args; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + + hw_cmd_args.ctxt_to_hw_map = ctx_isp->hw_ctx; + hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; + isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_CMD_RESUME_HW; + hw_cmd_args.u.internal_args = (void *)&isp_hw_cmd_args; + rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &hw_cmd_args); + + return rc; +} + +static int __cam_isp_ctx_handle_sof_freeze_evt( + struct cam_context *ctx) +{ + int rc = 0; + struct cam_hw_cmd_args hw_cmd_args; + struct cam_isp_hw_cmd_args isp_hw_cmd_args; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + + hw_cmd_args.ctxt_to_hw_map = ctx_isp->hw_ctx; + hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; + isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_CMD_SOF_DEBUG; + isp_hw_cmd_args.u.sof_irq_enable = 1; + hw_cmd_args.u.internal_args = (void *)&isp_hw_cmd_args; + + rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &hw_cmd_args); + + return rc; +} + +static int __cam_isp_ctx_process_evt(struct cam_context *ctx, + struct cam_req_mgr_link_evt_data *link_evt_data) +{ + int rc = 0; + + switch (link_evt_data->evt_type) { + case CAM_REQ_MGR_LINK_EVT_ERR: + /* No need to handle this message now */ + break; + case CAM_REQ_MGR_LINK_EVT_PAUSE: + __cam_isp_ctx_link_pause(ctx); + break; + case CAM_REQ_MGR_LINK_EVT_RESUME: + __cam_isp_ctx_link_resume(ctx); + break; + case CAM_REQ_MGR_LINK_EVT_SOF_FREEZE: + __cam_isp_ctx_handle_sof_freeze_evt(ctx); + break; + default: + CAM_WARN(CAM_ISP, "Unknown event from CRM"); + break; + } + return rc; +} + +static int __cam_isp_ctx_unlink_in_activated(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *unlink) +{ + int rc = 0; + + CAM_WARN(CAM_ISP, + "Received unlink in activated state. It's unexpected"); + + rc = __cam_isp_ctx_stop_dev_in_activated_unlock(ctx, NULL); + if (rc) + CAM_WARN(CAM_ISP, "Stop device failed rc=%d", rc); + + rc = __cam_isp_ctx_unlink_in_ready(ctx, unlink); + if (rc) + CAM_ERR(CAM_ISP, "Unlink failed rc=%d", rc); + + return rc; +} + +static int __cam_isp_ctx_apply_req(struct cam_context *ctx, + struct cam_req_mgr_apply_request *apply) +{ + int rc = 0; + struct cam_ctx_ops *ctx_ops = NULL; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *) ctx->ctx_priv; + + trace_cam_apply_req("ISP", apply->request_id); + CAM_DBG(CAM_ISP, "Enter: apply req in Substate[%s] request_id:%lld", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated), apply->request_id); + ctx_ops = &ctx_isp->substate_machine[ctx_isp->substate_activated]; + if (ctx_ops->crm_ops.apply_req) { + rc = ctx_ops->crm_ops.apply_req(ctx, apply); + } else { + CAM_WARN_RATE_LIMIT(CAM_ISP, + "No handle function in activated Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + rc = -EFAULT; + } + + if (rc) + CAM_WARN_RATE_LIMIT(CAM_ISP, + "Apply failed in active Substate[%s] rc %d", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated), rc); + return rc; +} + + + +static int __cam_isp_ctx_handle_irq_in_activated(void *context, + uint32_t evt_id, void *evt_data) +{ + int rc = 0; + struct cam_isp_ctx_irq_ops *irq_ops = NULL; + struct cam_context *ctx = (struct cam_context *)context; + struct cam_isp_context *ctx_isp = + (struct cam_isp_context *)ctx->ctx_priv; + + spin_lock(&ctx->lock); + + trace_cam_isp_activated_irq(ctx, ctx_isp->substate_activated, evt_id, + __cam_isp_ctx_get_event_ts(evt_id, evt_data)); + + CAM_DBG(CAM_ISP, "Enter: State %d, Substate[%s], evt id %d", + ctx->state, __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated), evt_id); + irq_ops = &ctx_isp->substate_machine_irq[ctx_isp->substate_activated]; + if (irq_ops->irq_ops[evt_id]) { + rc = irq_ops->irq_ops[evt_id](ctx_isp, evt_data); + } else { + CAM_DBG(CAM_ISP, "No handle function for Substate[%s]", + __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + if (isp_ctx_debug.enable_state_monitor_dump) + __cam_isp_ctx_dump_state_monitor_array(ctx_isp); + } + + CAM_DBG(CAM_ISP, "Exit: State %d Substate[%s]", + ctx->state, __cam_isp_ctx_substate_val_to_type( + ctx_isp->substate_activated)); + spin_unlock(&ctx->lock); + return rc; +} + +/* top state machine */ +static struct cam_ctx_ops + cam_isp_ctx_top_state_machine[CAM_CTX_STATE_MAX] = { + /* Uninit */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Available */ + { + .ioctl_ops = { + .acquire_dev = __cam_isp_ctx_acquire_dev_in_available, + }, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Acquired */ + { + .ioctl_ops = { + .acquire_hw = __cam_isp_ctx_acquire_hw_in_acquired, + .release_dev = __cam_isp_ctx_release_dev_in_top_state, + .config_dev = __cam_isp_ctx_config_dev_in_acquired, + .release_hw = __cam_isp_ctx_release_hw_in_top_state, + }, + .crm_ops = { + .link = __cam_isp_ctx_link_in_acquired, + .unlink = __cam_isp_ctx_unlink_in_acquired, + .get_dev_info = __cam_isp_ctx_get_dev_info_in_acquired, + .flush_req = __cam_isp_ctx_flush_req_in_top_state, + .dump_req = __cam_isp_ctx_dump_in_top_state, + }, + .irq_ops = NULL, + .pagefault_ops = cam_isp_context_dump_active_request, + .dumpinfo_ops = cam_isp_context_info_dump, + }, + /* Ready */ + { + .ioctl_ops = { + .start_dev = __cam_isp_ctx_start_dev_in_ready, + .release_dev = __cam_isp_ctx_release_dev_in_top_state, + .config_dev = __cam_isp_ctx_config_dev_in_top_state, + .release_hw = __cam_isp_ctx_release_hw_in_top_state, + }, + .crm_ops = { + .unlink = __cam_isp_ctx_unlink_in_ready, + .flush_req = __cam_isp_ctx_flush_req_in_ready, + .dump_req = __cam_isp_ctx_dump_in_top_state, + }, + .irq_ops = NULL, + .pagefault_ops = cam_isp_context_dump_active_request, + .dumpinfo_ops = cam_isp_context_info_dump, + }, + /* Flushed */ + { + .ioctl_ops = { + .stop_dev = __cam_isp_ctx_stop_dev_in_activated, + .release_dev = __cam_isp_ctx_release_dev_in_activated, + .config_dev = __cam_isp_ctx_config_dev_in_flushed, + .release_hw = __cam_isp_ctx_release_hw_in_activated, + }, + .crm_ops = { + .unlink = __cam_isp_ctx_unlink_in_ready, + .process_evt = __cam_isp_ctx_process_evt, + }, + .irq_ops = NULL, + .pagefault_ops = cam_isp_context_dump_active_request, + .dumpinfo_ops = cam_isp_context_info_dump, + }, + /* Activated */ + { + .ioctl_ops = { + .stop_dev = __cam_isp_ctx_stop_dev_in_activated, + .release_dev = __cam_isp_ctx_release_dev_in_activated, + .config_dev = __cam_isp_ctx_config_dev_in_top_state, + .release_hw = __cam_isp_ctx_release_hw_in_activated, + }, + .crm_ops = { + .unlink = __cam_isp_ctx_unlink_in_activated, + .apply_req = __cam_isp_ctx_apply_req, + .flush_req = __cam_isp_ctx_flush_req_in_top_state, + .process_evt = __cam_isp_ctx_process_evt, + .dump_req = __cam_isp_ctx_dump_in_top_state, + }, + .irq_ops = __cam_isp_ctx_handle_irq_in_activated, + .pagefault_ops = cam_isp_context_dump_active_request, + .dumpinfo_ops = cam_isp_context_info_dump, + }, +}; + + +static int cam_isp_context_dump_active_request(void *data, unsigned long iova, + uint32_t buf_info) +{ + + struct cam_context *ctx = (struct cam_context *)data; + struct cam_ctx_request *req = NULL; + struct cam_ctx_request *req_temp = NULL; + struct cam_isp_ctx_req *req_isp = NULL; + struct cam_isp_prepare_hw_update_data *hw_update_data = NULL; + struct cam_hw_mgr_dump_pf_data *pf_dbg_entry = NULL; + bool mem_found = false; + int rc = 0; + + struct cam_isp_context *isp_ctx = + (struct cam_isp_context *)ctx->ctx_priv; + + if (!isp_ctx) { + CAM_ERR(CAM_ISP, "Invalid isp ctx"); + return -EINVAL; + } + + CAM_INFO(CAM_ISP, "iommu fault handler for isp ctx %d state %d", + ctx->ctx_id, ctx->state); + + list_for_each_entry_safe(req, req_temp, + &ctx->active_req_list, list) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + hw_update_data = &req_isp->hw_update_data; + pf_dbg_entry = &(req->pf_data); + CAM_INFO(CAM_ISP, "req_id : %lld ", req->request_id); + + rc = cam_context_dump_pf_info_to_hw(ctx, pf_dbg_entry->packet, + iova, buf_info, &mem_found); + if (rc) + CAM_ERR(CAM_ISP, "Failed to dump pf info"); + + if (mem_found) + CAM_ERR(CAM_ISP, "Found page fault in req %lld %d", + req->request_id, rc); + } + + CAM_INFO(CAM_ISP, "Iterating over wait_list of isp ctx %d state %d", + ctx->ctx_id, ctx->state); + + list_for_each_entry_safe(req, req_temp, + &ctx->wait_req_list, list) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + hw_update_data = &req_isp->hw_update_data; + pf_dbg_entry = &(req->pf_data); + CAM_INFO(CAM_ISP, "req_id : %lld ", req->request_id); + + rc = cam_context_dump_pf_info_to_hw(ctx, pf_dbg_entry->packet, + iova, buf_info, &mem_found); + if (rc) + CAM_ERR(CAM_ISP, "Failed to dump pf info"); + + if (mem_found) + CAM_ERR(CAM_ISP, "Found page fault in req %lld %d", + req->request_id, rc); + } + + /* + * In certain scenarios we observe both overflow and SMMU pagefault + * for a particular request. If overflow is handled before page fault + * we need to traverse through pending request list because if + * bubble recovery is enabled on any request we move that request + * and all the subsequent requests to the pending list while handling + * overflow error. + */ + + CAM_INFO(CAM_ISP, + "Iterating over pending req list of isp ctx %d state %d", + ctx->ctx_id, ctx->state); + + list_for_each_entry_safe(req, req_temp, + &ctx->pending_req_list, list) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + hw_update_data = &req_isp->hw_update_data; + pf_dbg_entry = &(req->pf_data); + CAM_INFO(CAM_ISP, "req_id : %lld ", req->request_id); + + rc = cam_context_dump_pf_info_to_hw(ctx, pf_dbg_entry->packet, + iova, buf_info, &mem_found); + if (rc) + CAM_ERR(CAM_ISP, "Failed to dump pf info"); + + if (mem_found) + CAM_ERR(CAM_ISP, "Found page fault in req %lld %d", + req->request_id, rc); + } + + return rc; +} + +static int cam_isp_context_debug_register(void) +{ + isp_ctx_debug.dentry = debugfs_create_dir("camera_isp_ctx", + NULL); + + if (!isp_ctx_debug.dentry) { + CAM_ERR(CAM_ISP, "failed to create dentry"); + return -ENOMEM; + } + + if (!debugfs_create_u32("enable_state_monitor_dump", + 0644, + isp_ctx_debug.dentry, + &isp_ctx_debug.enable_state_monitor_dump)) { + CAM_ERR(CAM_ISP, "failed to create enable_state_monitor_dump"); + goto err; + } + + if (!debugfs_create_u32("enable_cdm_cmd_buffer_dump", + 0644, + isp_ctx_debug.dentry, + &isp_ctx_debug.enable_cdm_cmd_buff_dump)) { + CAM_ERR(CAM_ISP, "failed to create enable_cdm_cmd_buffer_dump"); + goto err; + } + + return 0; +err: + debugfs_remove_recursive(isp_ctx_debug.dentry); + return -ENOMEM; +} + +int cam_isp_context_init(struct cam_isp_context *ctx, + struct cam_context *ctx_base, + struct cam_req_mgr_kmd_ops *crm_node_intf, + struct cam_hw_mgr_intf *hw_intf, + uint32_t ctx_id, + uint32_t isp_device_type) + +{ + int rc = -1; + int i; + + if (!ctx || !ctx_base) { + CAM_ERR(CAM_ISP, "Invalid Context"); + goto err; + } + + /* ISP context setup */ + memset(ctx, 0, sizeof(*ctx)); + + ctx->base = ctx_base; + ctx->frame_id = 0; + ctx->active_req_cnt = 0; + ctx->reported_req_id = 0; + ctx->req_info.last_bufdone_req_id = 0; + ctx->bubble_frame_cnt = 0; + ctx->hw_ctx = NULL; + ctx->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF; + ctx->substate_machine = cam_isp_ctx_activated_state_machine; + ctx->substate_machine_irq = cam_isp_ctx_activated_state_machine_irq; + ctx->init_timestamp = jiffies_to_msecs(jiffies); + ctx->isp_device_type = isp_device_type; + + for (i = 0; i < CAM_ISP_CTX_REQ_MAX; i++) { + ctx->req_base[i].req_priv = &ctx->req_isp[i]; + ctx->req_isp[i].base = &ctx->req_base[i]; + } + + /* camera context setup */ + rc = cam_context_init(ctx_base, isp_dev_name, CAM_ISP, ctx_id, + crm_node_intf, hw_intf, ctx->req_base, CAM_ISP_CTX_REQ_MAX); + if (rc) { + CAM_ERR(CAM_ISP, "Camera Context Base init failed"); + goto err; + } + + /* link camera context with isp context */ + ctx_base->state_machine = cam_isp_ctx_top_state_machine; + ctx_base->ctx_priv = ctx; + + /* initializing current state for error logging */ + for (i = 0; i < CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES; i++) { + ctx->cam_isp_ctx_state_monitor[i].curr_state = + CAM_ISP_CTX_ACTIVATED_MAX; + } + atomic64_set(&ctx->state_monitor_head, -1); + + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx->event_record_head[i], -1); + + cam_isp_context_debug_register(); +err: + return rc; +} + +int cam_isp_context_deinit(struct cam_isp_context *ctx) +{ + int rc = 0; + + if (ctx->base) + cam_context_deinit(ctx->base); + + if (ctx->substate_activated != CAM_ISP_CTX_ACTIVATED_SOF) + CAM_ERR(CAM_ISP, "ISP context Substate[%s] is invalid", + __cam_isp_ctx_substate_val_to_type( + ctx->substate_activated)); + + memset(ctx, 0, sizeof(*ctx)); + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/cam_isp_context.h b/techpack/camera-bengal/drivers/cam_isp/cam_isp_context.h new file mode 100644 index 0000000000000000000000000000000000000000..72d35cb7e9f90023f68b5278bb1372ceccabd7ca --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/cam_isp_context.h @@ -0,0 +1,339 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_ISP_CONTEXT_H_ +#define _CAM_ISP_CONTEXT_H_ + + +#include +#include +#include +#include + +#include "cam_context.h" +#include "cam_isp_hw_mgr_intf.h" + +/* + * Maximum hw resource - This number is based on the maximum + * output port resource. The current maximum resource number + * is 24. + */ +#define CAM_ISP_CTX_RES_MAX 24 + +/* max requests per ctx for isp */ +#define CAM_ISP_CTX_REQ_MAX 8 +/* + * Maximum configuration entry size - This is based on the + * worst case DUAL IFE use case plus some margin. + */ +#define CAM_ISP_CTX_CFG_MAX 25 + +/* + * Maximum entries in state monitoring array for error logging + */ +#define CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES 40 + +/* + * Threshold response time in us beyond which a request is not expected + * to be with IFE hw + */ +#define CAM_ISP_CTX_RESPONSE_TIME_THRESHOLD 100000 + +/* Number of words for dumping isp context */ +#define CAM_ISP_CTX_DUMP_NUM_WORDS 5 + +/* Number of words for dumping isp context events*/ +#define CAM_ISP_CTX_DUMP_EVENT_NUM_WORDS 3 + +/* Number of words for dumping request info*/ +#define CAM_ISP_CTX_DUMP_REQUEST_NUM_WORDS 2 + +/* Maximum entries in event record */ +#define CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES 20 + +/* Maximum length of tag while dumping */ +#define CAM_ISP_CONTEXT_DUMP_TAG_MAX_LEN 32 + +/* forward declaration */ +struct cam_isp_context; + +/* cam isp context irq handling function type */ +typedef int (*cam_isp_hw_event_cb_func)(struct cam_isp_context *ctx_isp, + void *evt_data); + +/** + * enum cam_isp_ctx_activated_substate - sub states for activated + * + */ +enum cam_isp_ctx_activated_substate { + CAM_ISP_CTX_ACTIVATED_SOF, + CAM_ISP_CTX_ACTIVATED_APPLIED, + CAM_ISP_CTX_ACTIVATED_EPOCH, + CAM_ISP_CTX_ACTIVATED_BUBBLE, + CAM_ISP_CTX_ACTIVATED_BUBBLE_APPLIED, + CAM_ISP_CTX_ACTIVATED_HW_ERROR, + CAM_ISP_CTX_ACTIVATED_HALT, + CAM_ISP_CTX_ACTIVATED_MAX, +}; + +/** + * enum cam_isp_ctx_event_type - events for a request + * + */ +enum cam_isp_ctx_event { + CAM_ISP_CTX_EVENT_SUBMIT, + CAM_ISP_CTX_EVENT_APPLY, + CAM_ISP_CTX_EVENT_EPOCH, + CAM_ISP_CTX_EVENT_RUP, + CAM_ISP_CTX_EVENT_BUFDONE, + CAM_ISP_CTX_EVENT_MAX +}; + +/** + * enum cam_isp_state_change_trigger - Different types of ISP events + * + */ +enum cam_isp_state_change_trigger { + CAM_ISP_STATE_CHANGE_TRIGGER_ERROR, + CAM_ISP_STATE_CHANGE_TRIGGER_APPLIED, + CAM_ISP_STATE_CHANGE_TRIGGER_REG_UPDATE, + CAM_ISP_STATE_CHANGE_TRIGGER_SOF, + CAM_ISP_STATE_CHANGE_TRIGGER_EPOCH, + CAM_ISP_STATE_CHANGE_TRIGGER_DONE, + CAM_ISP_STATE_CHANGE_TRIGGER_EOF, + CAM_ISP_STATE_CHANGE_TRIGGER_FLUSH, + CAM_ISP_STATE_CHANGE_TRIGGER_MAX +}; + +/** + * struct cam_isp_ctx_debug - Contains debug parameters + * + * @dentry: Debugfs entry + * @enable_state_monitor_dump: Enable isp state monitor dump + * @enable_cdm_cmd_buff_dump: Enable CDM Command buffer dump + * + */ +struct cam_isp_ctx_debug { + struct dentry *dentry; + uint32_t enable_state_monitor_dump; + uint32_t enable_cdm_cmd_buff_dump; +}; + +/** + * struct cam_isp_ctx_irq_ops - Function table for handling IRQ callbacks + * + * @irq_ops: Array of handle function pointers. + * + */ +struct cam_isp_ctx_irq_ops { + cam_isp_hw_event_cb_func irq_ops[CAM_ISP_HW_EVENT_MAX]; +}; + +/** + * struct cam_isp_ctx_req - ISP context request object + * + * @base: Common request object ponter + * @cfg: ISP hardware configuration array + * @num_cfg: Number of ISP hardware configuration entries + * @fence_map_out: Output fence mapping array + * @num_fence_map_out: Number of the output fence map + * @fence_map_in: Input fence mapping array + * @num_fence_map_in: Number of input fence map + * @num_acked: Count to track acked entried for output. + * If count equals the number of fence out, it means + * the request has been completed. + * @bubble_report: Flag to track if bubble report is active on + * current request + * @hw_update_data: HW update data for this request + * @event_timestamp: Timestamp for different stage of request + * @reapply: True if reapplying after bubble + * + */ +struct cam_isp_ctx_req { + struct cam_ctx_request *base; + + struct cam_hw_update_entry cfg[CAM_ISP_CTX_CFG_MAX]; + uint32_t num_cfg; + struct cam_hw_fence_map_entry fence_map_out + [CAM_ISP_CTX_RES_MAX]; + uint32_t num_fence_map_out; + struct cam_hw_fence_map_entry fence_map_in[CAM_ISP_CTX_RES_MAX]; + uint32_t num_fence_map_in; + uint32_t num_acked; + int32_t bubble_report; + struct cam_isp_prepare_hw_update_data hw_update_data; + ktime_t event_timestamp + [CAM_ISP_CTX_EVENT_MAX]; + bool bubble_detected; + bool reapply; +}; + +/** + * struct cam_isp_context_state_monitor - ISP context state + * monitoring for + * debug purposes + * + * @curr_state: Current sub state that received req + * @trigger: Event type of incoming req + * @req_id: Request id + * @frame_id: Frame id based on SOFs + * @evt_time_stamp Current time stamp + * + */ +struct cam_isp_context_state_monitor { + enum cam_isp_ctx_activated_substate curr_state; + enum cam_isp_state_change_trigger trigger; + uint64_t req_id; + int64_t frame_id; + unsigned int evt_time_stamp; +}; + +/** + * struct cam_isp_context_req_id_info - ISP context request id + * information for bufdone. + * + *@last_bufdone_req_id: Last bufdone request id + * + */ + +struct cam_isp_context_req_id_info { + int64_t last_bufdone_req_id; +}; + +/** + * + * + * struct cam_isp_context_event_record - Information for last 20 Events + * for a request; Submit, Apply, EPOCH, RUP, Buf done. + * + * @req_id: Last applied request id + * @timestamp: Timestamp for the event + * + */ +struct cam_isp_context_event_record { + uint64_t req_id; + ktime_t timestamp; +}; + +/** + * struct cam_isp_context - ISP context object + * + * @base: Common context object pointer + * @frame_id: Frame id tracking for the isp context + * @frame_id_meta: Frame id read every epoch for the ctx + * meta from the sensor + * @substate_actiavted: Current substate for the activated state. + * @process_bubble: Atomic variable to check if ctx is still + * processing bubble. + * @bubble_frame_cnt: Count number of frames since the req is in bubble + * @substate_machine: ISP substate machine for external interface + * @substate_machine_irq: ISP substate machine for irq handling + * @req_base: Common request object storage + * @req_isp: ISP private request object storage + * @hw_ctx: HW object returned by the acquire device command + * @sof_timestamp_val: Captured time stamp value at sof hw event + * @last_sof_timestamp: Time stamp value for last SOF event + * @boot_timestamp: Boot time stamp for a given req_id + * @active_req_cnt: Counter for the active request + * @reported_req_id: Last reported request id + * @subscribe_event: The irq event mask that CRM subscribes to, IFE + * will invoke CRM cb at those event. + * @last_applied_req_id: Last applied request id + * @state_monitor_head: Write index to the state monitoring array + * @req_info Request id information about last buf done + * @cam_isp_ctx_state_monitor: State monitoring array + * @event_record_head: Write index to the state monitoring array + * @event_record: Event record array + * @rdi_only_context: Get context type information. + * true, if context is rdi only context + * @hw_acquired: Indicate whether HW resources are acquired + * @init_received: Indicate whether init config packet is received + * @split_acquire: Indicate whether a separate acquire is expected + * @init_timestamp: Timestamp at which this context is initialized + * @isp_device_type ISP device type + * + */ +struct cam_isp_context { + struct cam_context *base; + + int64_t frame_id; + uint32_t frame_id_meta; + uint32_t substate_activated; + atomic_t process_bubble; + uint32_t bubble_frame_cnt; + struct cam_ctx_ops *substate_machine; + struct cam_isp_ctx_irq_ops *substate_machine_irq; + + struct cam_ctx_request req_base[CAM_ISP_CTX_REQ_MAX]; + struct cam_isp_ctx_req req_isp[CAM_ISP_CTX_REQ_MAX]; + + void *hw_ctx; + uint64_t sof_timestamp_val; + uint64_t last_sof_timestamp; + uint64_t boot_timestamp; + int32_t active_req_cnt; + int64_t reported_req_id; + uint32_t subscribe_event; + int64_t last_applied_req_id; + atomic64_t state_monitor_head; + struct cam_isp_context_state_monitor cam_isp_ctx_state_monitor[ + CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES]; + struct cam_isp_context_req_id_info req_info; + atomic64_t event_record_head[ + CAM_ISP_CTX_EVENT_MAX]; + struct cam_isp_context_event_record event_record[ + CAM_ISP_CTX_EVENT_MAX][CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES]; + bool rdi_only_context; + bool hw_acquired; + bool init_received; + bool split_acquire; + unsigned int init_timestamp; + uint32_t isp_device_type; +}; + +/** + * struct cam_isp_context_dump_header - ISP context dump header + * @tag: Tag name for the header + * @word_size: Size of word + * @size: Size of data + * + */ +struct cam_isp_context_dump_header { + uint8_t tag[CAM_ISP_CONTEXT_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + +/** + * cam_isp_context_init() + * + * @brief: Initialization function for the ISP context + * + * @ctx: ISP context obj to be initialized + * @bridge_ops: Bridge call back funciton + * @hw_intf: ISP hw manager interface + * @ctx_id: ID for this context + * @isp_device_type Isp device type + * + */ +int cam_isp_context_init(struct cam_isp_context *ctx, + struct cam_context *ctx_base, + struct cam_req_mgr_kmd_ops *bridge_ops, + struct cam_hw_mgr_intf *hw_intf, + uint32_t ctx_id, + uint32_t isp_device_type); + +/** + * cam_isp_context_deinit() + * + * @brief: Deinitialize function for the ISP context + * + * @ctx: ISP context obj to be deinitialized + * + */ +int cam_isp_context_deinit(struct cam_isp_context *ctx); + + +#endif /* __CAM_ISP_CONTEXT_H__ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/cam_isp_dev.c b/techpack/camera-bengal/drivers/cam_isp/cam_isp_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..b08956ef957e4ba24a849db52cf894bf3dbc2c27 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/cam_isp_dev.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include "cam_isp_dev.h" +#include "cam_hw_mgr_intf.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_node.h" +#include "cam_debug_util.h" +#include "cam_smmu_api.h" + +static struct cam_isp_dev g_isp_dev; + +static void cam_isp_dev_iommu_fault_handler( + struct iommu_domain *domain, struct device *dev, unsigned long iova, + int flags, void *token, uint32_t buf_info) +{ + int i = 0; + struct cam_node *node = NULL; + + if (!token) { + CAM_ERR(CAM_ISP, "invalid token in page handler cb"); + return; + } + + node = (struct cam_node *)token; + + for (i = 0; i < node->ctx_size; i++) + cam_context_dump_pf_info(&(node->ctx_list[i]), iova, + buf_info); +} + +static const struct of_device_id cam_isp_dt_match[] = { + { + .compatible = "qcom,cam-isp" + }, + {} +}; + +static int cam_isp_subdev_open(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); + + mutex_lock(&g_isp_dev.isp_mutex); + g_isp_dev.open_cnt++; + mutex_unlock(&g_isp_dev.isp_mutex); + + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); + + return 0; +} + +static int cam_isp_subdev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + int rc = 0; + struct cam_node *node = v4l2_get_subdevdata(sd); + + mutex_lock(&g_isp_dev.isp_mutex); + if (g_isp_dev.open_cnt <= 0) { + CAM_DBG(CAM_ISP, "ISP subdev is already closed"); + rc = -EINVAL; + goto end; + } + + g_isp_dev.open_cnt--; + if (!node) { + CAM_ERR(CAM_ISP, "Node ptr is NULL"); + rc = -EINVAL; + goto end; + } + + if (g_isp_dev.open_cnt == 0) + cam_node_shutdown(node); + +end: + mutex_unlock(&g_isp_dev.isp_mutex); + return rc; +} + +static const struct v4l2_subdev_internal_ops cam_isp_subdev_internal_ops = { + .close = cam_isp_subdev_close, + .open = cam_isp_subdev_open, +}; + +static int cam_isp_dev_remove(struct platform_device *pdev) +{ + int rc = 0; + int i; + + /* clean up ife/tfe resources */ + for (i = 0; i < g_isp_dev.max_context; i++) { + rc = cam_isp_context_deinit(&g_isp_dev.ctx_isp[i]); + if (rc) + CAM_ERR(CAM_ISP, "ISP context %d deinit failed", + i); + } + kfree(g_isp_dev.ctx); + g_isp_dev.ctx = NULL; + kfree(g_isp_dev.ctx_isp); + g_isp_dev.ctx_isp = NULL; + + rc = cam_subdev_remove(&g_isp_dev.sd); + if (rc) + CAM_ERR(CAM_ISP, "Unregister failed"); + + memset(&g_isp_dev, 0, sizeof(g_isp_dev)); + return 0; +} + +static int cam_isp_dev_probe(struct platform_device *pdev) +{ + int rc = -1; + int i; + struct cam_hw_mgr_intf hw_mgr_intf; + struct cam_node *node; + const char *compat_str = NULL; + + int iommu_hdl = -1; + + rc = of_property_read_string_index(pdev->dev.of_node, "arch-compat", 0, + (const char **)&compat_str); + + g_isp_dev.sd.internal_ops = &cam_isp_subdev_internal_ops; + /* Initialize the v4l2 subdevice first. (create cam_node) */ + if (strnstr(compat_str, "ife", strlen(compat_str))) { + rc = cam_subdev_probe(&g_isp_dev.sd, pdev, CAM_ISP_DEV_NAME, + CAM_IFE_DEVICE_TYPE); + g_isp_dev.isp_device_type = CAM_IFE_DEVICE_TYPE; + g_isp_dev.max_context = CAM_IFE_CTX_MAX; + } else if (strnstr(compat_str, "tfe", strlen(compat_str))) { + rc = cam_subdev_probe(&g_isp_dev.sd, pdev, CAM_ISP_DEV_NAME, + CAM_TFE_DEVICE_TYPE); + g_isp_dev.isp_device_type = CAM_TFE_DEVICE_TYPE; + g_isp_dev.max_context = CAM_TFE_CTX_MAX; + } else { + CAM_ERR(CAM_ISP, "Invalid ISP hw type %s", compat_str); + rc = -EINVAL; + goto err; + } + + if (rc) { + CAM_ERR(CAM_ISP, "ISP cam_subdev_probe failed!"); + goto err; + } + node = (struct cam_node *) g_isp_dev.sd.token; + + memset(&hw_mgr_intf, 0, sizeof(hw_mgr_intf)); + g_isp_dev.ctx = kcalloc(g_isp_dev.max_context, + sizeof(struct cam_context), + GFP_KERNEL); + if (!g_isp_dev.ctx) { + CAM_ERR(CAM_ISP, + "Mem Allocation failed for ISP base context"); + goto unregister; + } + + g_isp_dev.ctx_isp = kcalloc(g_isp_dev.max_context, + sizeof(struct cam_isp_context), + GFP_KERNEL); + if (!g_isp_dev.ctx_isp) { + CAM_ERR(CAM_ISP, + "Mem Allocation failed for Isp private context"); + kfree(g_isp_dev.ctx); + g_isp_dev.ctx = NULL; + goto unregister; + } + + rc = cam_isp_hw_mgr_init(compat_str, &hw_mgr_intf, &iommu_hdl); + if (rc != 0) { + CAM_ERR(CAM_ISP, "Can not initialized ISP HW manager!"); + goto kfree; + } + + for (i = 0; i < g_isp_dev.max_context; i++) { + rc = cam_isp_context_init(&g_isp_dev.ctx_isp[i], + &g_isp_dev.ctx[i], + &node->crm_node_intf, + &node->hw_mgr_intf, + i, + g_isp_dev.isp_device_type); + if (rc) { + CAM_ERR(CAM_ISP, "ISP context init failed!"); + goto kfree; + } + } + rc = cam_node_init(node, &hw_mgr_intf, g_isp_dev.ctx, + g_isp_dev.max_context, CAM_ISP_DEV_NAME); + + if (rc) { + CAM_ERR(CAM_ISP, "ISP node init failed!"); + goto kfree; + } + + cam_smmu_set_client_page_fault_handler(iommu_hdl, + cam_isp_dev_iommu_fault_handler, node); + + mutex_init(&g_isp_dev.isp_mutex); + + CAM_INFO(CAM_ISP, "Camera ISP probe complete"); + + return 0; + +kfree: + kfree(g_isp_dev.ctx); + g_isp_dev.ctx = NULL; + kfree(g_isp_dev.ctx_isp); + g_isp_dev.ctx_isp = NULL; + +unregister: + rc = cam_subdev_remove(&g_isp_dev.sd); +err: + return rc; +} + + +static struct platform_driver isp_driver = { + .probe = cam_isp_dev_probe, + .remove = cam_isp_dev_remove, + .driver = { + .name = "cam_isp", + .owner = THIS_MODULE, + .of_match_table = cam_isp_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_isp_dev_init_module(void) +{ + return platform_driver_register(&isp_driver); +} + +static void __exit cam_isp_dev_exit_module(void) +{ + platform_driver_unregister(&isp_driver); +} + +module_init(cam_isp_dev_init_module); +module_exit(cam_isp_dev_exit_module); +MODULE_DESCRIPTION("MSM ISP driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_isp/cam_isp_dev.h b/techpack/camera-bengal/drivers/cam_isp/cam_isp_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..5ba338f77e6fe4835c86f6ec98c67efea377c520 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/cam_isp_dev.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_ISP_DEV_H_ +#define _CAM_ISP_DEV_H_ + +#include "cam_subdev.h" +#include "cam_hw_mgr_intf.h" +#include "cam_context.h" +#include "cam_isp_context.h" + +/** + * struct cam_isp_dev - Camera ISP V4l2 device node + * + * @sd: Commone camera subdevice node + * @ctx: Isp base context storage + * @ctx_isp: Isp private context storage + * @isp_mutex: ISP dev mutex + * @open_cnt: Open device count + * @isp_device_type ISP device type + * @max_context maximum contexts for TFE is 4 and for IFE is 8 + */ +struct cam_isp_dev { + struct cam_subdev sd; + struct cam_context *ctx; + struct cam_isp_context *ctx_isp; + struct mutex isp_mutex; + int32_t open_cnt; + uint32_t isp_device_type; + int32_t max_context; +}; + +#endif /* __CAM_ISP_DEV_H__ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..234f0431b26770d3ae78310e7418e8e16541a37d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/Makefile @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(src) + +obj-$(CONFIG_SPECTRA_CAMERA) += hw_utils/ isp_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_isp_hw_mgr.o + +ifdef CONFIG_SPECTRA_CAMERA_TFE +obj-$(CONFIG_SPECTRA_CAMERA) += cam_tfe_hw_mgr.o +endif + +ifdef CONFIG_SPECTRA_CAMERA_IFE +obj-$(CONFIG_SPECTRA_CAMERA) += cam_ife_hw_mgr.o +endif diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c new file mode 100644 index 0000000000000000000000000000000000000000..e61591714bbee65458161045d0a025e70ea452e8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -0,0 +1,7167 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "cam_smmu_api.h" +#include "cam_req_mgr_workq.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_isp_hw.h" +#include "cam_ife_csid_hw_intf.h" +#include "cam_vfe_hw_intf.h" +#include "cam_isp_packet_parser.h" +#include "cam_ife_hw_mgr.h" +#include "cam_cdm_intf_api.h" +#include "cam_packet_util.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" +#include "cam_mem_mgr_api.h" +#include "cam_common_util.h" + +#define CAM_IFE_HW_ENTRIES_MAX 20 + +#define TZ_SVC_SMMU_PROGRAM 0x15 +#define TZ_SAFE_SYSCALL_ID 0x3 +#define CAM_IFE_SAFE_DISABLE 0 +#define CAM_IFE_SAFE_ENABLE 1 +#define SMMU_SE_IFE 0 + +#define CAM_ISP_PACKET_META_MAX \ + (CAM_ISP_PACKET_META_GENERIC_BLOB_COMMON + 1) + +#define CAM_ISP_GENERIC_BLOB_TYPE_MAX \ + (CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG_V2 + 1) + +static uint32_t blob_type_hw_cmd_map[CAM_ISP_GENERIC_BLOB_TYPE_MAX] = { + CAM_ISP_HW_CMD_GET_HFR_UPDATE, + CAM_ISP_HW_CMD_CLOCK_UPDATE, + CAM_ISP_HW_CMD_BW_UPDATE, + CAM_ISP_HW_CMD_UBWC_UPDATE, + CAM_ISP_HW_CMD_CSID_CLOCK_UPDATE, + CAM_ISP_GENERIC_BLOB_TYPE_FE_CONFIG, + CAM_ISP_HW_CMD_UBWC_UPDATE_V2, + CAM_ISP_HW_CMD_CORE_CONFIG, + CAM_ISP_HW_CMD_WM_CONFIG_UPDATE, + CAM_ISP_HW_CMD_BW_UPDATE_V2, +}; + +static struct cam_ife_hw_mgr g_ife_hw_mgr; + +static int cam_ife_hw_mgr_event_handler( + void *priv, + uint32_t evt_id, + void *evt_info); + +static int cam_ife_mgr_regspace_data_cb(uint32_t reg_base_type, + void *hw_mgr_ctx, struct cam_hw_soc_info **soc_info_ptr, + uint32_t *reg_base_idx) +{ + int rc = 0; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res_temp; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ife_hw_mgr_ctx *ctx = + (struct cam_ife_hw_mgr_ctx *) hw_mgr_ctx; + + *soc_info_ptr = NULL; + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &ctx->res_list_ife_src, list) { + if (hw_mgr_res->res_id != CAM_ISP_HW_VFE_IN_CAMIF) + continue; + + switch (reg_base_type) { + case CAM_REG_DUMP_BASE_TYPE_CAMNOC: + case CAM_REG_DUMP_BASE_TYPE_ISP_LEFT: + if (!hw_mgr_res->hw_res[CAM_ISP_HW_SPLIT_LEFT]) + continue; + + rc = hw_mgr_res->hw_res[ + CAM_ISP_HW_SPLIT_LEFT]->process_cmd( + hw_mgr_res->hw_res[CAM_ISP_HW_SPLIT_LEFT], + CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA, &soc_info, + sizeof(void *)); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in regspace data query split idx: %d rc : %d", + CAM_ISP_HW_SPLIT_LEFT, rc); + return rc; + } + + if (reg_base_type == CAM_REG_DUMP_BASE_TYPE_ISP_LEFT) + *reg_base_idx = 0; + else + *reg_base_idx = 1; + + *soc_info_ptr = soc_info; + break; + case CAM_REG_DUMP_BASE_TYPE_ISP_RIGHT: + if (!hw_mgr_res->hw_res[CAM_ISP_HW_SPLIT_RIGHT]) + continue; + + rc = hw_mgr_res->hw_res[ + CAM_ISP_HW_SPLIT_RIGHT]->process_cmd( + hw_mgr_res->hw_res[CAM_ISP_HW_SPLIT_RIGHT], + CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA, &soc_info, + sizeof(void *)); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in regspace data query split idx: %d rc : %d", + CAM_ISP_HW_SPLIT_RIGHT, rc); + return rc; + } + + *reg_base_idx = 0; + *soc_info_ptr = soc_info; + break; + default: + CAM_ERR(CAM_ISP, + "Unrecognized reg base type: %u", + reg_base_type); + return -EINVAL; + } + + break; + } + + return rc; +} + +static int cam_ife_mgr_handle_reg_dump(struct cam_ife_hw_mgr_ctx *ctx, + struct cam_cmd_buf_desc *reg_dump_buf_desc, uint32_t num_reg_dump_buf, + uint32_t meta_type, + void *soc_dump_args, + bool user_triggered_dump) +{ + int rc = 0, i; + + if (!num_reg_dump_buf || !reg_dump_buf_desc) { + CAM_DBG(CAM_ISP, + "Invalid args for reg dump req_id: [%llu] ctx idx: [%u] meta_type: [%u] num_reg_dump_buf: [%u] reg_dump_buf_desc: [%pK]", + ctx->applied_req_id, ctx->ctx_index, meta_type, + num_reg_dump_buf, reg_dump_buf_desc); + return rc; + } + + if (!atomic_read(&ctx->cdm_done)) + CAM_WARN_RATE_LIMIT(CAM_ISP, + "Reg dump values might be from more than one request"); + + for (i = 0; i < num_reg_dump_buf; i++) { + CAM_DBG(CAM_ISP, "Reg dump cmd meta data: %u req_type: %u", + reg_dump_buf_desc[i].meta_data, meta_type); + if (reg_dump_buf_desc[i].meta_data == meta_type) { + rc = cam_soc_util_reg_dump_to_cmd_buf(ctx, + ®_dump_buf_desc[i], + ctx->applied_req_id, + cam_ife_mgr_regspace_data_cb, + soc_dump_args, + user_triggered_dump); + if (rc) { + CAM_ERR(CAM_ISP, + "Reg dump failed at idx: %d, rc: %d req_id: %llu meta type: %u", + i, rc, ctx->applied_req_id, meta_type); + return rc; + } + } + } + + return rc; +} + +static int cam_ife_notify_safe_lut_scm(bool safe_trigger) +{ + uint32_t camera_hw_version, rc = 0; + struct scm_desc desc = {0}; + + rc = cam_cpas_get_cpas_hw_version(&camera_hw_version); + if (!rc) { + switch (camera_hw_version) { + case CAM_CPAS_TITAN_170_V100: + case CAM_CPAS_TITAN_170_V110: + case CAM_CPAS_TITAN_175_V100: + + desc.arginfo = SCM_ARGS(2, SCM_VAL, SCM_VAL); + desc.args[0] = SMMU_SE_IFE; + desc.args[1] = safe_trigger; + + CAM_DBG(CAM_ISP, "Safe scm call %d", safe_trigger); + if (scm_call2(SCM_SIP_FNID(TZ_SVC_SMMU_PROGRAM, + TZ_SAFE_SYSCALL_ID), &desc)) { + CAM_ERR(CAM_ISP, + "scm call to Enable Safe failed"); + rc = -EINVAL; + } + break; + default: + break; + } + } + + return rc; +} + +static int cam_ife_mgr_get_hw_caps(void *hw_mgr_priv, + void *hw_caps_args) +{ + int rc = 0; + int i; + struct cam_ife_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_query_cap_cmd *query = hw_caps_args; + struct cam_isp_query_cap_cmd query_isp; + + CAM_DBG(CAM_ISP, "enter"); + + if (copy_from_user(&query_isp, + u64_to_user_ptr(query->caps_handle), + sizeof(struct cam_isp_query_cap_cmd))) { + rc = -EFAULT; + return rc; + } + + query_isp.device_iommu.non_secure = hw_mgr->mgr_common.img_iommu_hdl; + query_isp.device_iommu.secure = hw_mgr->mgr_common.img_iommu_hdl_secure; + query_isp.cdm_iommu.non_secure = hw_mgr->mgr_common.cmd_iommu_hdl; + query_isp.cdm_iommu.secure = hw_mgr->mgr_common.cmd_iommu_hdl_secure; + query_isp.num_dev = 2; + for (i = 0; i < query_isp.num_dev; i++) { + query_isp.dev_caps[i].hw_type = CAM_ISP_HW_IFE; + query_isp.dev_caps[i].hw_version.major = 1; + query_isp.dev_caps[i].hw_version.minor = 7; + query_isp.dev_caps[i].hw_version.incr = 0; + query_isp.dev_caps[i].hw_version.reserved = 0; + } + + if (copy_to_user(u64_to_user_ptr(query->caps_handle), + &query_isp, sizeof(struct cam_isp_query_cap_cmd))) + rc = -EFAULT; + + CAM_DBG(CAM_ISP, "exit rc :%d", rc); + + return rc; +} + +static int cam_ife_hw_mgr_is_rdi_res(uint32_t res_id) +{ + int rc = 0; + + switch (res_id) { + case CAM_ISP_IFE_OUT_RES_RDI_0: + case CAM_ISP_IFE_OUT_RES_RDI_1: + case CAM_ISP_IFE_OUT_RES_RDI_2: + case CAM_ISP_IFE_OUT_RES_RDI_3: + rc = 1; + break; + default: + break; + } + + return rc; +} + +static int cam_ife_hw_mgr_reset_csid_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int i; + int rc = 0; + struct cam_hw_intf *hw_intf; + struct cam_csid_reset_cfg_args csid_reset_args; + + csid_reset_args.reset_type = CAM_IFE_CSID_RESET_PATH; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + csid_reset_args.node_res = isp_hw_res->hw_res[i]; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + CAM_DBG(CAM_ISP, "Resetting csid hardware %d", + hw_intf->hw_idx); + if (hw_intf->hw_ops.reset) { + rc = hw_intf->hw_ops.reset(hw_intf->hw_priv, + &csid_reset_args, + sizeof(struct cam_csid_reset_cfg_args)); + if (rc) + goto err; + } + } + + return 0; +err: + CAM_ERR(CAM_ISP, "RESET HW res failed: (type:%d, id:%d)", + isp_hw_res->res_type, isp_hw_res->res_id); + return rc; +} + +static int cam_ife_hw_mgr_init_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int i; + int rc = -1; + struct cam_hw_intf *hw_intf; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + CAM_DBG(CAM_ISP, "enabled vfe hardware %d", + hw_intf->hw_idx); + if (hw_intf->hw_ops.init) { + rc = hw_intf->hw_ops.init(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + if (rc) + goto err; + } + } + + return 0; +err: + CAM_ERR(CAM_ISP, "INIT HW res failed: (type:%d, id:%d)", + isp_hw_res->res_type, isp_hw_res->res_id); + return rc; +} + +static int cam_ife_hw_mgr_start_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res, + struct cam_ife_hw_mgr_ctx *ctx) +{ + int i; + int rc = -1; + struct cam_hw_intf *hw_intf; + + /* Start slave (which is right split) first */ + for (i = CAM_ISP_HW_SPLIT_MAX - 1; i >= 0; i--) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.start) { + rc = hw_intf->hw_ops.start(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start HW resources"); + goto err; + } + CAM_DBG(CAM_ISP, "Start HW %d Res %d", hw_intf->hw_idx, + isp_hw_res->hw_res[i]->res_id); + } else { + CAM_ERR(CAM_ISP, "function null"); + goto err; + } + } + + return 0; +err: + CAM_ERR(CAM_ISP, "Start hw res failed (type:%d, id:%d)", + isp_hw_res->res_type, isp_hw_res->res_id); + return rc; +} + +static void cam_ife_hw_mgr_stop_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int i; + struct cam_hw_intf *hw_intf; + uint32_t dummy_args; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + + if (isp_hw_res->hw_res[i]->res_state != + CAM_ISP_RESOURCE_STATE_STREAMING) + continue; + + if (hw_intf->hw_ops.stop) + hw_intf->hw_ops.stop(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + else + CAM_ERR(CAM_ISP, "stop null"); + if (hw_intf->hw_ops.process_cmd && + isp_hw_res->res_type == CAM_ISP_RESOURCE_VFE_OUT) { + hw_intf->hw_ops.process_cmd(hw_intf->hw_priv, + CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ, + &dummy_args, sizeof(dummy_args)); + } + } +} + +static void cam_ife_hw_mgr_deinit_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int i; + struct cam_hw_intf *hw_intf; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.deinit) + hw_intf->hw_ops.deinit(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + } +} + +static void cam_ife_hw_mgr_deinit_hw( + struct cam_ife_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + int i = 0; + + if (!ctx->init_done) { + CAM_WARN(CAM_ISP, "ctx is not in init state"); + return; + } + + /* Deinit IFE CID */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_cid, list) { + CAM_DBG(CAM_ISP, "%s: Going to DeInit IFE CID\n", __func__); + cam_ife_hw_mgr_deinit_hw_res(hw_mgr_res); + } + + /* Deinit IFE CSID */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, list) { + CAM_DBG(CAM_ISP, "%s: Going to DeInit IFE CSID\n", __func__); + cam_ife_hw_mgr_deinit_hw_res(hw_mgr_res); + } + + /* Deint IFE MUX(SRC) */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + cam_ife_hw_mgr_deinit_hw_res(hw_mgr_res); + } + + /* Deint IFE RD */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_in_rd, list) { + cam_ife_hw_mgr_deinit_hw_res(hw_mgr_res); + } + + /* Deinit IFE OUT */ + for (i = 0; i < CAM_IFE_HW_OUT_RES_MAX; i++) + cam_ife_hw_mgr_deinit_hw_res(&ctx->res_list_ife_out[i]); + + ctx->init_done = false; +} + +static int cam_ife_hw_mgr_init_hw( + struct cam_ife_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + int rc = 0, i; + + CAM_DBG(CAM_ISP, "INIT IFE CID ... in ctx id:%d", + ctx->ctx_index); + /* INIT IFE CID */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_cid, list) { + rc = cam_ife_hw_mgr_init_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Can not INIT IFE CID(id :%d)", + hw_mgr_res->res_id); + goto deinit; + } + } + + CAM_DBG(CAM_ISP, "INIT IFE csid ... in ctx id:%d", + ctx->ctx_index); + + /* INIT IFE csid */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, list) { + rc = cam_ife_hw_mgr_init_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Can not INIT IFE CSID(id :%d)", + hw_mgr_res->res_id); + goto deinit; + } + } + + /* INIT IFE SRC */ + CAM_DBG(CAM_ISP, "INIT IFE SRC in ctx id:%d", + ctx->ctx_index); + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + rc = cam_ife_hw_mgr_init_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Can not INIT IFE SRC (%d)", + hw_mgr_res->res_id); + goto deinit; + } + } + + /* INIT IFE BUS RD */ + CAM_DBG(CAM_ISP, "INIT IFE BUS RD in ctx id:%d", + ctx->ctx_index); + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_in_rd, list) { + rc = cam_ife_hw_mgr_init_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Can not IFE BUS RD (%d)", + hw_mgr_res->res_id); + return rc; + } + } + + /* INIT IFE OUT */ + CAM_DBG(CAM_ISP, "INIT IFE OUT RESOURCES in ctx id:%d", + ctx->ctx_index); + + for (i = 0; i < CAM_IFE_HW_OUT_RES_MAX; i++) { + rc = cam_ife_hw_mgr_init_hw_res(&ctx->res_list_ife_out[i]); + if (rc) { + CAM_ERR(CAM_ISP, "Can not INIT IFE OUT (%d)", + ctx->res_list_ife_out[i].res_id); + goto deinit; + } + } + + return rc; +deinit: + ctx->init_done = true; + cam_ife_hw_mgr_deinit_hw(ctx); + return rc; +} + +static int cam_ife_hw_mgr_put_res( + struct list_head *src_list, + struct cam_isp_hw_mgr_res **res) +{ + int rc = 0; + struct cam_isp_hw_mgr_res *res_ptr = NULL; + + res_ptr = *res; + if (res_ptr) + list_add_tail(&res_ptr->list, src_list); + + return rc; +} + +static int cam_ife_hw_mgr_get_res( + struct list_head *src_list, + struct cam_isp_hw_mgr_res **res) +{ + int rc = 0; + struct cam_isp_hw_mgr_res *res_ptr = NULL; + + if (!list_empty(src_list)) { + res_ptr = list_first_entry(src_list, + struct cam_isp_hw_mgr_res, list); + list_del_init(&res_ptr->list); + } else { + CAM_ERR(CAM_ISP, "No more free ife hw mgr ctx"); + rc = -1; + } + *res = res_ptr; + + return rc; +} + +static int cam_ife_hw_mgr_free_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int rc = 0; + int i; + struct cam_hw_intf *hw_intf; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.release) { + rc = hw_intf->hw_ops.release(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + if (rc) + CAM_ERR(CAM_ISP, + "Release hw resource id %d failed", + isp_hw_res->res_id); + isp_hw_res->hw_res[i] = NULL; + } else + CAM_ERR(CAM_ISP, "Release null"); + } + /* caller should make sure the resource is in a list */ + list_del_init(&isp_hw_res->list); + memset(isp_hw_res, 0, sizeof(*isp_hw_res)); + INIT_LIST_HEAD(&isp_hw_res->list); + + return 0; +} + +static const char *cam_ife_hw_mgr_get_res_state( + uint32_t res_state) +{ + switch (res_state) { + case CAM_ISP_RESOURCE_STATE_UNAVAILABLE: + return "UNAVAILABLE"; + case CAM_ISP_RESOURCE_STATE_AVAILABLE: + return "AVAILABLE"; + case CAM_ISP_RESOURCE_STATE_RESERVED: + return "RESERVED"; + case CAM_ISP_RESOURCE_STATE_INIT_HW: + return "HW INIT DONE"; + case CAM_ISP_RESOURCE_STATE_STREAMING: + return "STREAMING"; + default: + return "INVALID STATE"; + } +} + +static const char *cam_ife_hw_mgr_get_csid_res_id( + uint32_t res_id) +{ + switch (res_id) { + case CAM_IFE_PIX_PATH_RES_RDI_0: + return "RDI_0"; + case CAM_IFE_PIX_PATH_RES_RDI_1: + return "RDI_1"; + case CAM_IFE_PIX_PATH_RES_RDI_2: + return "RDI_2"; + case CAM_IFE_PIX_PATH_RES_RDI_3: + return "RDI_3"; + case CAM_IFE_PIX_PATH_RES_IPP: + return "IPP"; + case CAM_IFE_PIX_PATH_RES_PPP: + return "PPP"; + default: + return "INVALID"; + } +} + +static const char *cam_ife_hw_mgr_get_src_res_id( + uint32_t res_id) +{ + switch (res_id) { + case CAM_ISP_HW_VFE_IN_CAMIF: + return "CAMIF"; + case CAM_ISP_HW_VFE_IN_TESTGEN: + return "TESTGEN"; + case CAM_ISP_HW_VFE_IN_RD: + return "BUS_RD"; + case CAM_ISP_HW_VFE_IN_RDI0: + return "RDI_0"; + case CAM_ISP_HW_VFE_IN_RDI1: + return "RDI_1"; + case CAM_ISP_HW_VFE_IN_RDI2: + return "RDI_2"; + case CAM_ISP_HW_VFE_IN_RDI3: + return "RDI_3"; + case CAM_ISP_HW_VFE_IN_PDLIB: + return "PDLIB"; + case CAM_ISP_HW_VFE_IN_LCR: + return "LCR"; + default: + return "INVALID"; + } +} + +static void cam_ife_hw_mgr_dump_src_acq_info( + struct cam_ife_hw_mgr_ctx *hwr_mgr_ctx, + uint32_t num_pix_port, uint32_t num_rdi_port) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res_temp = NULL; + struct cam_isp_resource_node *hw_res = NULL; + int i = 0; + + CAM_INFO(CAM_ISP, + "Acquired HW for ctx: %u with pix_port: %u rdi_port: %u", + hwr_mgr_ctx->ctx_index, num_pix_port, num_rdi_port); + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &hwr_mgr_ctx->res_list_ife_src, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + hw_res = hw_mgr_res->hw_res[i]; + if (hw_res && hw_res->hw_intf) + CAM_INFO(CAM_ISP, + "IFE src split_id: %d res_id: %s hw_idx: %u state: %s", + i, + cam_ife_hw_mgr_get_src_res_id( + hw_res->res_id), + hw_res->hw_intf->hw_idx, + cam_ife_hw_mgr_get_res_state + (hw_res->res_state)); + } + } +} + +static void cam_ife_hw_mgr_dump_acq_data( + struct cam_ife_hw_mgr_ctx *hwr_mgr_ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res_temp = NULL; + struct cam_isp_resource_node *hw_res = NULL; + struct timespec64 *ts = NULL; + uint64_t ms, tmp, hrs, min, sec; + int i = 0, j = 0; + + ts = &hwr_mgr_ctx->ts; + tmp = ts->tv_sec; + ms = (ts->tv_nsec) / 1000000; + sec = do_div(tmp, 60); + min = do_div(tmp, 60); + hrs = do_div(tmp, 24); + + CAM_INFO(CAM_ISP, + "**** %llu:%llu:%llu.%llu ctx_idx: %u rdi_only: %s is_dual: %s acquired ****", + hrs, min, sec, ms, + hwr_mgr_ctx->ctx_index, + (hwr_mgr_ctx->is_rdi_only_context ? "true" : "false"), + (hwr_mgr_ctx->is_dual ? "true" : "false")); + + /* Iterate over CID resources */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &hwr_mgr_ctx->res_list_ife_cid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + hw_res = hw_mgr_res->hw_res[i]; + if (hw_res && hw_res->hw_intf) { + CAM_INFO(CAM_ISP, + "CID split_id: %d res_id: %u hw_idx: %u state: %s", + i, hw_res->res_id, + hw_res->hw_intf->hw_idx, + cam_ife_hw_mgr_get_res_state + (hw_res->res_state)); + } + } + } + + /* Iterate over CSID resources */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &hwr_mgr_ctx->res_list_ife_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + hw_res = hw_mgr_res->hw_res[i]; + if (hw_res && hw_res->hw_intf) + CAM_INFO(CAM_ISP, + "CSID split_id: %d res_id: %s hw_idx: %u state: %s", + i, + cam_ife_hw_mgr_get_csid_res_id( + hw_res->res_id), + hw_res->hw_intf->hw_idx, + cam_ife_hw_mgr_get_res_state + (hw_res->res_state)); + } + } + + /* Iterate over IFE IN resources */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &hwr_mgr_ctx->res_list_ife_src, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + hw_res = hw_mgr_res->hw_res[i]; + if (hw_res && hw_res->hw_intf) + CAM_INFO(CAM_ISP, + "IFE src split_id: %d res_id: %s hw_idx: %u state: %s", + i, + cam_ife_hw_mgr_get_src_res_id( + hw_res->res_id), + hw_res->hw_intf->hw_idx, + cam_ife_hw_mgr_get_res_state + (hw_res->res_state)); + } + } + + /* Iterate over IFE RD resources */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &hwr_mgr_ctx->res_list_ife_in_rd, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + hw_res = hw_mgr_res->hw_res[i]; + if (hw_res && hw_res->hw_intf) + CAM_INFO(CAM_ISP, + "IFE src_rd split_id: %d res_id: %s hw_idx: %u state: %s", + i, + cam_ife_hw_mgr_get_src_res_id( + hw_res->res_id), + hw_res->hw_intf->hw_idx, + cam_ife_hw_mgr_get_res_state + (hw_res->res_state)); + } + } + + /* Iterate over IFE OUT resources */ + for (i = 0; i < CAM_IFE_HW_OUT_RES_MAX; i++) { + for (j = 0; j < CAM_ISP_HW_SPLIT_MAX; j++) { + hw_mgr_res = &hwr_mgr_ctx->res_list_ife_out[i]; + hw_res = hw_mgr_res->hw_res[j]; + if (hw_res && hw_res->hw_intf) + CAM_INFO(CAM_ISP, + "IFE out split_id: %d res_id: 0x%x hw_idx: %u state: %s", + j, hw_res->res_id, + hw_res->hw_intf->hw_idx, + cam_ife_hw_mgr_get_res_state + (hw_res->res_state)); + } + } +} + +static int cam_ife_mgr_csid_stop_hw( + struct cam_ife_hw_mgr_ctx *ctx, struct list_head *stop_list, + uint32_t base_idx, uint32_t stop_cmd) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *isp_res; + struct cam_isp_resource_node *stop_res[CAM_IFE_PIX_PATH_RES_MAX - 1]; + struct cam_csid_hw_stop_args stop; + struct cam_hw_intf *hw_intf; + uint32_t i, cnt; + + cnt = 0; + list_for_each_entry(hw_mgr_res, stop_list, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i] || + (hw_mgr_res->hw_res[i]->res_state != + CAM_ISP_RESOURCE_STATE_STREAMING)) + continue; + + isp_res = hw_mgr_res->hw_res[i]; + if (isp_res->hw_intf->hw_idx != base_idx) + continue; + CAM_DBG(CAM_ISP, "base_idx %d res_id %d cnt %u", + base_idx, isp_res->res_id, cnt); + stop_res[cnt] = isp_res; + cnt++; + } + } + + if (cnt) { + hw_intf = stop_res[0]->hw_intf; + stop.num_res = cnt; + stop.node_res = stop_res; + stop.stop_cmd = stop_cmd; + hw_intf->hw_ops.stop(hw_intf->hw_priv, &stop, sizeof(stop)); + } + + return 0; +} + +static int cam_ife_hw_mgr_release_hw_for_ctx( + struct cam_ife_hw_mgr_ctx *ife_ctx) +{ + uint32_t i; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res_temp; + + /* ife leaf resource */ + for (i = 0; i < CAM_IFE_HW_OUT_RES_MAX; i++) + cam_ife_hw_mgr_free_hw_res(&ife_ctx->res_list_ife_out[i]); + + /* ife bus rd resource */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &ife_ctx->res_list_ife_in_rd, list) { + cam_ife_hw_mgr_free_hw_res(hw_mgr_res); + cam_ife_hw_mgr_put_res(&ife_ctx->free_res_list, &hw_mgr_res); + } + + /* ife source resource */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &ife_ctx->res_list_ife_src, list) { + cam_ife_hw_mgr_free_hw_res(hw_mgr_res); + cam_ife_hw_mgr_put_res(&ife_ctx->free_res_list, &hw_mgr_res); + } + + /* ife csid resource */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &ife_ctx->res_list_ife_csid, list) { + cam_ife_hw_mgr_free_hw_res(hw_mgr_res); + cam_ife_hw_mgr_put_res(&ife_ctx->free_res_list, &hw_mgr_res); + } + + /* ife cid resource */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &ife_ctx->res_list_ife_cid, list) { + cam_ife_hw_mgr_free_hw_res(hw_mgr_res); + cam_ife_hw_mgr_put_res(&ife_ctx->free_res_list, &hw_mgr_res); + } + + /* ife root node */ + if (ife_ctx->res_list_ife_in.res_type != CAM_ISP_RESOURCE_UNINT) + cam_ife_hw_mgr_free_hw_res(&ife_ctx->res_list_ife_in); + + /* clean up the callback function */ + ife_ctx->common.cb_priv = NULL; + memset(ife_ctx->common.event_cb, 0, sizeof(ife_ctx->common.event_cb)); + + CAM_DBG(CAM_ISP, "release context completed ctx id:%d", + ife_ctx->ctx_index); + + return 0; +} + + +static int cam_ife_hw_mgr_put_ctx( + struct list_head *src_list, + struct cam_ife_hw_mgr_ctx **ife_ctx) +{ + int rc = 0; + struct cam_ife_hw_mgr_ctx *ctx_ptr = NULL; + + mutex_lock(&g_ife_hw_mgr.ctx_mutex); + ctx_ptr = *ife_ctx; + if (ctx_ptr) + list_add_tail(&ctx_ptr->list, src_list); + *ife_ctx = NULL; + mutex_unlock(&g_ife_hw_mgr.ctx_mutex); + return rc; +} + +static int cam_ife_hw_mgr_get_ctx( + struct list_head *src_list, + struct cam_ife_hw_mgr_ctx **ife_ctx) +{ + int rc = 0; + struct cam_ife_hw_mgr_ctx *ctx_ptr = NULL; + + mutex_lock(&g_ife_hw_mgr.ctx_mutex); + if (!list_empty(src_list)) { + ctx_ptr = list_first_entry(src_list, + struct cam_ife_hw_mgr_ctx, list); + list_del_init(&ctx_ptr->list); + } else { + CAM_ERR(CAM_ISP, "No more free ife hw mgr ctx"); + rc = -1; + } + *ife_ctx = ctx_ptr; + mutex_unlock(&g_ife_hw_mgr.ctx_mutex); + + return rc; +} + +static void cam_ife_mgr_add_base_info( + struct cam_ife_hw_mgr_ctx *ctx, + enum cam_isp_hw_split_id split_id, + uint32_t base_idx) +{ + uint32_t i; + + if (!ctx->num_base) { + ctx->base[0].split_id = split_id; + ctx->base[0].idx = base_idx; + ctx->num_base++; + CAM_DBG(CAM_ISP, + "Add split id = %d for base idx = %d num_base=%d", + split_id, base_idx, ctx->num_base); + } else { + /*Check if base index already exists in the list */ + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].idx == base_idx) { + if (split_id != CAM_ISP_HW_SPLIT_MAX && + ctx->base[i].split_id == + CAM_ISP_HW_SPLIT_MAX) + ctx->base[i].split_id = split_id; + + break; + } + } + + if (i == ctx->num_base) { + ctx->base[ctx->num_base].split_id = split_id; + ctx->base[ctx->num_base].idx = base_idx; + ctx->num_base++; + CAM_DBG(CAM_ISP, + "Add split_id=%d for base idx=%d num_base=%d", + split_id, base_idx, ctx->num_base); + } + } +} + +static int cam_ife_mgr_process_base_info( + struct cam_ife_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *res = NULL; + uint32_t i; + + if (list_empty(&ctx->res_list_ife_src)) { + CAM_ERR(CAM_ISP, "Mux List empty"); + return -ENODEV; + } + + /* IFE mux in resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) + continue; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + res = hw_mgr_res->hw_res[i]; + cam_ife_mgr_add_base_info(ctx, i, + res->hw_intf->hw_idx); + CAM_DBG(CAM_ISP, "add base info for hw %d", + res->hw_intf->hw_idx); + } + } + CAM_DBG(CAM_ISP, "ctx base num = %d", ctx->num_base); + + return 0; +} + +static int cam_ife_hw_mgr_acquire_res_bus_rd( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_in_port_generic_info *in_port) +{ + int rc = -EINVAL; + struct cam_vfe_acquire_args vfe_acquire; + struct cam_isp_hw_mgr_res *ife_in_rd_res; + struct cam_hw_intf *hw_intf; + struct cam_isp_hw_mgr_res *ife_src_res; + int i; + + CAM_DBG(CAM_ISP, "Enter"); + + list_for_each_entry(ife_src_res, &ife_ctx->res_list_ife_src, list) { + if (ife_src_res->res_id != CAM_ISP_HW_VFE_IN_RD) + continue; + + rc = cam_ife_hw_mgr_get_res(&ife_ctx->free_res_list, + &ife_in_rd_res); + if (rc) { + CAM_ERR(CAM_ISP, "No more free hw mgr resource"); + goto err; + } + cam_ife_hw_mgr_put_res(&ife_ctx->res_list_ife_in_rd, + &ife_in_rd_res); + + vfe_acquire.rsrc_type = CAM_ISP_RESOURCE_VFE_BUS_RD; + vfe_acquire.tasklet = ife_ctx->common.tasklet_info; + vfe_acquire.vfe_out.cdm_ops = ife_ctx->cdm_ops; + vfe_acquire.priv = ife_ctx; + vfe_acquire.vfe_out.unique_id = ife_ctx->ctx_index; + vfe_acquire.vfe_out.is_dual = ife_src_res->is_dual_isp; + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!ife_src_res->hw_res[i]) + continue; + + hw_intf = ife_src_res->hw_res[i]->hw_intf; + if (i == CAM_ISP_HW_SPLIT_LEFT) { + vfe_acquire.vfe_out.split_id = + CAM_ISP_HW_SPLIT_LEFT; + if (ife_src_res->is_dual_isp) { + /*TBD */ + vfe_acquire.vfe_out.is_master = 1; + vfe_acquire.vfe_out.dual_slave_core = + ife_ctx->slave_hw_idx; + } else { + vfe_acquire.vfe_out.is_master = 0; + vfe_acquire.vfe_out.dual_slave_core = + 0; + } + } else { + vfe_acquire.vfe_out.split_id = + CAM_ISP_HW_SPLIT_RIGHT; + vfe_acquire.vfe_out.is_master = 0; + vfe_acquire.vfe_out.dual_slave_core = + ife_ctx->master_hw_idx; + } + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &vfe_acquire, + sizeof(struct cam_vfe_acquire_args)); + if (rc) { + CAM_ERR(CAM_ISP, + "Can not acquire out resource 0x%x", + vfe_acquire.rsrc_type); + goto err; + } + + ife_in_rd_res->hw_res[i] = + vfe_acquire.vfe_out.rsrc_node; + CAM_DBG(CAM_ISP, "resource type :0x%x res id:0x%x", + ife_in_rd_res->hw_res[i]->res_type, + ife_in_rd_res->hw_res[i]->res_id); + + } + ife_in_rd_res->is_dual_isp = in_port->usage_type; + ife_in_rd_res->res_type = CAM_ISP_RESOURCE_VFE_BUS_RD; + } + + return 0; +err: + CAM_DBG(CAM_ISP, "Exit rc(0x%x)", rc); + return rc; +} + +static int cam_ife_hw_mgr_acquire_res_ife_out_rdi( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_hw_mgr_res *ife_src_res, + struct cam_isp_in_port_generic_info *in_port) +{ + int rc = -EINVAL; + struct cam_vfe_acquire_args vfe_acquire; + struct cam_isp_out_port_generic_info *out_port = NULL; + struct cam_isp_hw_mgr_res *ife_out_res; + struct cam_hw_intf *hw_intf; + uint32_t i, vfe_out_res_id, vfe_in_res_id; + + /* take left resource */ + vfe_in_res_id = ife_src_res->hw_res[0]->res_id; + + switch (vfe_in_res_id) { + case CAM_ISP_HW_VFE_IN_RDI0: + vfe_out_res_id = CAM_ISP_IFE_OUT_RES_RDI_0; + break; + case CAM_ISP_HW_VFE_IN_RDI1: + vfe_out_res_id = CAM_ISP_IFE_OUT_RES_RDI_1; + break; + case CAM_ISP_HW_VFE_IN_RDI2: + vfe_out_res_id = CAM_ISP_IFE_OUT_RES_RDI_2; + break; + case CAM_ISP_HW_VFE_IN_RDI3: + vfe_out_res_id = CAM_ISP_IFE_OUT_RES_RDI_3; + break; + default: + CAM_ERR(CAM_ISP, "invalid resource type"); + goto err; + } + CAM_DBG(CAM_ISP, "vfe_in_res_id = %d, vfe_out_red_id = %d", + vfe_in_res_id, vfe_out_res_id); + + vfe_acquire.rsrc_type = CAM_ISP_RESOURCE_VFE_OUT; + vfe_acquire.tasklet = ife_ctx->common.tasklet_info; + + ife_out_res = &ife_ctx->res_list_ife_out[vfe_out_res_id & 0xFF]; + for (i = 0; i < in_port->num_out_res; i++) { + out_port = &in_port->data[i]; + + CAM_DBG(CAM_ISP, "i = %d, vfe_out_res_id = %d, out_port: %d", + i, vfe_out_res_id, out_port->res_type); + + if (vfe_out_res_id != out_port->res_type) + continue; + + vfe_acquire.vfe_out.cdm_ops = ife_ctx->cdm_ops; + vfe_acquire.priv = ife_ctx; + vfe_acquire.vfe_out.out_port_info = out_port; + vfe_acquire.vfe_out.split_id = CAM_ISP_HW_SPLIT_LEFT; + vfe_acquire.vfe_out.unique_id = ife_ctx->ctx_index; + vfe_acquire.vfe_out.is_dual = 0; + vfe_acquire.event_cb = cam_ife_hw_mgr_event_handler; + hw_intf = ife_src_res->hw_res[0]->hw_intf; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &vfe_acquire, + sizeof(struct cam_vfe_acquire_args)); + if (rc) { + CAM_ERR(CAM_ISP, "Can not acquire out resource 0x%x", + out_port->res_type); + goto err; + } + break; + } + + if (i == in_port->num_out_res) { + CAM_ERR(CAM_ISP, + "Cannot acquire out resource, i=%d, num_out_res=%d", + i, in_port->num_out_res); + goto err; + } + + ife_out_res->hw_res[0] = vfe_acquire.vfe_out.rsrc_node; + ife_out_res->is_dual_isp = 0; + ife_out_res->res_id = vfe_out_res_id; + ife_out_res->res_type = CAM_ISP_RESOURCE_VFE_OUT; + ife_src_res->num_children++; + + return 0; +err: + return rc; +} + +static int cam_ife_hw_mgr_acquire_res_ife_out_pixel( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_hw_mgr_res *ife_src_res, + struct cam_isp_in_port_generic_info *in_port, + bool acquire_lcr) +{ + int rc = -1; + uint32_t i, j, k; + struct cam_vfe_acquire_args vfe_acquire; + struct cam_isp_out_port_generic_info *out_port; + struct cam_isp_hw_mgr_res *ife_out_res; + struct cam_hw_intf *hw_intf; + + for (i = 0; i < in_port->num_out_res; i++) { + out_port = &in_port->data[i]; + k = out_port->res_type & 0xFF; + if (k >= CAM_IFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "invalid output resource type 0x%x", + out_port->res_type); + continue; + } + + if (cam_ife_hw_mgr_is_rdi_res(out_port->res_type)) + continue; + + if ((acquire_lcr && + out_port->res_type != CAM_ISP_IFE_OUT_RES_LCR) || + (!acquire_lcr && + out_port->res_type == CAM_ISP_IFE_OUT_RES_LCR)) + continue; + + if ((out_port->res_type == CAM_ISP_IFE_OUT_RES_2PD && + ife_src_res->res_id != CAM_ISP_HW_VFE_IN_PDLIB) || + (ife_src_res->res_id == CAM_ISP_HW_VFE_IN_PDLIB && + out_port->res_type != CAM_ISP_IFE_OUT_RES_2PD)) + continue; + + CAM_DBG(CAM_ISP, "res_type 0x%x", out_port->res_type); + + ife_out_res = &ife_ctx->res_list_ife_out[k]; + ife_out_res->is_dual_isp = in_port->usage_type; + + vfe_acquire.rsrc_type = CAM_ISP_RESOURCE_VFE_OUT; + vfe_acquire.tasklet = ife_ctx->common.tasklet_info; + vfe_acquire.vfe_out.cdm_ops = ife_ctx->cdm_ops; + vfe_acquire.priv = ife_ctx; + vfe_acquire.vfe_out.out_port_info = out_port; + vfe_acquire.vfe_out.is_dual = ife_src_res->is_dual_isp; + vfe_acquire.vfe_out.unique_id = ife_ctx->ctx_index; + vfe_acquire.event_cb = cam_ife_hw_mgr_event_handler; + + for (j = 0; j < CAM_ISP_HW_SPLIT_MAX; j++) { + if (!ife_src_res->hw_res[j]) + continue; + + hw_intf = ife_src_res->hw_res[j]->hw_intf; + + if (j == CAM_ISP_HW_SPLIT_LEFT) { + vfe_acquire.vfe_out.split_id = + CAM_ISP_HW_SPLIT_LEFT; + if (ife_src_res->is_dual_isp) { + /*TBD */ + vfe_acquire.vfe_out.is_master = 1; + vfe_acquire.vfe_out.dual_slave_core = + ife_ctx->slave_hw_idx; + } else { + vfe_acquire.vfe_out.is_master = 0; + vfe_acquire.vfe_out.dual_slave_core = + 0; + } + } else { + vfe_acquire.vfe_out.split_id = + CAM_ISP_HW_SPLIT_RIGHT; + vfe_acquire.vfe_out.is_master = 0; + vfe_acquire.vfe_out.dual_slave_core = + ife_ctx->master_hw_idx; + } + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &vfe_acquire, + sizeof(struct cam_vfe_acquire_args)); + if (rc) { + CAM_ERR(CAM_ISP, + "Can not acquire out resource 0x%x", + out_port->res_type); + goto err; + } + + ife_out_res->hw_res[j] = + vfe_acquire.vfe_out.rsrc_node; + CAM_DBG(CAM_ISP, "resource type :0x%x res id:0x%x", + ife_out_res->hw_res[j]->res_type, + ife_out_res->hw_res[j]->res_id); + + } + ife_out_res->res_type = CAM_ISP_RESOURCE_VFE_OUT; + ife_out_res->res_id = out_port->res_type; + ife_src_res->num_children++; + } + + return 0; +err: + /* release resource at the entry function */ + return rc; +} + +static int cam_ife_hw_mgr_acquire_res_ife_out( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_in_port_generic_info *in_port) +{ + int rc = -EINVAL; + struct cam_isp_hw_mgr_res *ife_src_res; + + list_for_each_entry(ife_src_res, &ife_ctx->res_list_ife_src, list) { + if (ife_src_res->num_children) + continue; + + switch (ife_src_res->res_id) { + case CAM_ISP_HW_VFE_IN_CAMIF: + case CAM_ISP_HW_VFE_IN_PDLIB: + case CAM_ISP_HW_VFE_IN_RD: + rc = cam_ife_hw_mgr_acquire_res_ife_out_pixel(ife_ctx, + ife_src_res, in_port, false); + break; + case CAM_ISP_HW_VFE_IN_LCR: + rc = cam_ife_hw_mgr_acquire_res_ife_out_pixel(ife_ctx, + ife_src_res, in_port, true); + break; + case CAM_ISP_HW_VFE_IN_RDI0: + case CAM_ISP_HW_VFE_IN_RDI1: + case CAM_ISP_HW_VFE_IN_RDI2: + case CAM_ISP_HW_VFE_IN_RDI3: + rc = cam_ife_hw_mgr_acquire_res_ife_out_rdi(ife_ctx, + ife_src_res, in_port); + break; + default: + CAM_ERR(CAM_ISP, "Unknown IFE SRC resource: %d", + ife_src_res->res_id); + break; + } + if (rc) + goto err; + } + + return 0; +err: + /* release resource on entry function */ + return rc; +} + +static int cam_ife_hw_mgr_acquire_res_ife_rd_src( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_in_port_generic_info *in_port) +{ + int rc = -1; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_isp_hw_mgr_res *ife_src_res; + struct cam_vfe_acquire_args vfe_acquire; + struct cam_hw_intf *hw_intf; + struct cam_ife_hw_mgr *ife_hw_mgr; + int vfe_idx = -1, i = 0; + + ife_hw_mgr = ife_ctx->hw_mgr; + + CAM_DBG(CAM_ISP, "Enter"); + list_for_each_entry(csid_res, &ife_ctx->res_list_ife_csid, list) { + if (csid_res->res_id != CAM_IFE_PIX_PATH_RES_RDI_0) { + CAM_DBG(CAM_ISP, "not RDI0: %d", csid_res->res_id); + continue; + } + + rc = cam_ife_hw_mgr_get_res(&ife_ctx->free_res_list, + &ife_src_res); + if (rc) { + CAM_ERR(CAM_ISP, "No more free hw mgr resource"); + goto err; + } + cam_ife_hw_mgr_put_res(&ife_ctx->res_list_ife_src, + &ife_src_res); + + CAM_DBG(CAM_ISP, "csid_res_id %d", csid_res->res_id); + vfe_acquire.rsrc_type = CAM_ISP_RESOURCE_VFE_IN; + vfe_acquire.tasklet = ife_ctx->common.tasklet_info; + vfe_acquire.vfe_in.cdm_ops = ife_ctx->cdm_ops; + vfe_acquire.vfe_in.in_port = in_port; + vfe_acquire.vfe_in.res_id = CAM_ISP_HW_VFE_IN_RD; + vfe_acquire.vfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; + + ife_src_res->res_type = vfe_acquire.rsrc_type; + ife_src_res->res_id = vfe_acquire.vfe_in.res_id; + ife_src_res->is_dual_isp = csid_res->is_dual_isp; + + hw_intf = + ife_hw_mgr->ife_devices[csid_res->hw_res[ + CAM_ISP_HW_SPLIT_LEFT]->hw_intf->hw_idx]; + + vfe_idx = csid_res->hw_res[ + CAM_ISP_HW_SPLIT_LEFT]->hw_intf->hw_idx; + + /* + * fill in more acquire information as needed + */ + if (ife_src_res->is_dual_isp) + vfe_acquire.vfe_in.sync_mode = CAM_ISP_HW_SYNC_MASTER; + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &vfe_acquire, + sizeof(struct cam_vfe_acquire_args)); + if (rc) { + CAM_ERR(CAM_ISP, + "Can not acquire IFE HW res %d", + csid_res->res_id); + goto err; + } + ife_src_res->hw_res[CAM_ISP_HW_SPLIT_LEFT] = + vfe_acquire.vfe_in.rsrc_node; + CAM_DBG(CAM_ISP, + "acquire success IFE:%d res type :0x%x res id:0x%x", + hw_intf->hw_idx, + ife_src_res->hw_res[CAM_ISP_HW_SPLIT_LEFT]->res_type, + ife_src_res->hw_res[CAM_ISP_HW_SPLIT_LEFT]->res_id); + + if (!ife_src_res->is_dual_isp) + goto acq; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (i == CAM_ISP_HW_SPLIT_LEFT) { + CAM_DBG(CAM_ISP, "vfe_idx %d is acquired", + vfe_idx); + continue; + } + + hw_intf = ife_hw_mgr->ife_devices[i]; + + /* fill in more acquire information as needed */ + if (i == CAM_ISP_HW_SPLIT_RIGHT) + vfe_acquire.vfe_in.sync_mode = + CAM_ISP_HW_SYNC_SLAVE; + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &vfe_acquire, + sizeof(struct cam_vfe_acquire_args)); + if (rc) { + CAM_ERR(CAM_ISP, + "Can not acquire IFE HW res %d", + csid_res->res_id); + goto err; + } + ife_src_res->hw_res[i] = vfe_acquire.vfe_in.rsrc_node; + CAM_DBG(CAM_ISP, + "acquire success IFE:%d res type :0x%x res id:0x%x", + hw_intf->hw_idx, + ife_src_res->hw_res[i]->res_type, + ife_src_res->hw_res[i]->res_id); + } +acq: + /* + * It should be one to one mapping between + * csid resource and ife source resource + */ + csid_res->num_children++; + } + +err: + /* release resource at the entry function */ + CAM_DBG(CAM_ISP, "Exit rc %d", rc); + return rc; +} + +static int cam_convert_hw_idx_to_ife_hw_num(int hw_idx) +{ + uint32_t hw_version, rc = 0; + + rc = cam_cpas_get_cpas_hw_version(&hw_version); + if (!rc) { + switch (hw_version) { + case CAM_CPAS_TITAN_170_V100: + case CAM_CPAS_TITAN_170_V110: + case CAM_CPAS_TITAN_170_V120: + case CAM_CPAS_TITAN_175_V100: + case CAM_CPAS_TITAN_175_V101: + case CAM_CPAS_TITAN_175_V120: + case CAM_CPAS_TITAN_175_V130: + case CAM_CPAS_TITAN_480_V100: + if (hw_idx == 0) + return CAM_ISP_IFE0_HW; + else if (hw_idx == 1) + return CAM_ISP_IFE1_HW; + else if (hw_idx == 2) + return CAM_ISP_IFE0_LITE_HW; + else if (hw_idx == 3) + return CAM_ISP_IFE1_LITE_HW; + else if (hw_idx == 4) + return CAM_ISP_IFE2_LITE_HW; + break; + default: + CAM_ERR(CAM_ISP, "Invalid hw_version: 0x%X", + hw_version); + rc = -EINVAL; + break; + } + } + + return rc; +} + +static int cam_convert_rdi_out_res_id_to_src(int res_id) +{ + if (res_id == CAM_ISP_IFE_OUT_RES_RDI_0) + return CAM_ISP_HW_VFE_IN_RDI0; + else if (res_id == CAM_ISP_IFE_OUT_RES_RDI_1) + return CAM_ISP_HW_VFE_IN_RDI1; + else if (res_id == CAM_ISP_IFE_OUT_RES_RDI_2) + return CAM_ISP_HW_VFE_IN_RDI2; + else if (res_id == CAM_ISP_IFE_OUT_RES_RDI_3) + return CAM_ISP_HW_VFE_IN_RDI3; + return CAM_ISP_HW_VFE_IN_MAX; +} + +static int cam_convert_res_id_to_hw_path(int res_id) +{ + if (res_id == CAM_ISP_HW_VFE_IN_LCR) + return CAM_ISP_LCR_PATH; + else if (res_id == CAM_ISP_HW_VFE_IN_PDLIB) + return CAM_ISP_PPP_PATH; + else if (res_id == CAM_ISP_HW_VFE_IN_CAMIF) + return CAM_ISP_PXL_PATH; + else if (res_id == CAM_ISP_HW_VFE_IN_RDI0) + return CAM_ISP_RDI0_PATH; + else if (res_id == CAM_ISP_HW_VFE_IN_RDI1) + return CAM_ISP_RDI1_PATH; + else if (res_id == CAM_ISP_HW_VFE_IN_RDI2) + return CAM_ISP_RDI2_PATH; + else if (res_id == CAM_ISP_HW_VFE_IN_RDI3) + return CAM_ISP_RDI3_PATH; + return 0; +} + +static int cam_ife_hw_mgr_acquire_res_ife_src( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_in_port_generic_info *in_port, + bool acquire_lcr, uint32_t *acquired_hw_id, + uint32_t *acquired_hw_path) +{ + int rc = -1; + int i; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_isp_hw_mgr_res *ife_src_res; + struct cam_vfe_acquire_args vfe_acquire; + struct cam_hw_intf *hw_intf; + struct cam_ife_hw_mgr *ife_hw_mgr; + + ife_hw_mgr = ife_ctx->hw_mgr; + + list_for_each_entry(csid_res, &ife_ctx->res_list_ife_csid, list) { + if (csid_res->num_children && !acquire_lcr) + continue; + + if (acquire_lcr && csid_res->res_id != CAM_IFE_PIX_PATH_RES_IPP) + continue; + + rc = cam_ife_hw_mgr_get_res(&ife_ctx->free_res_list, + &ife_src_res); + if (rc) { + CAM_ERR(CAM_ISP, "No more free hw mgr resource"); + goto err; + } + cam_ife_hw_mgr_put_res(&ife_ctx->res_list_ife_src, + &ife_src_res); + + vfe_acquire.rsrc_type = CAM_ISP_RESOURCE_VFE_IN; + vfe_acquire.tasklet = ife_ctx->common.tasklet_info; + vfe_acquire.vfe_in.cdm_ops = ife_ctx->cdm_ops; + vfe_acquire.vfe_in.in_port = in_port; + vfe_acquire.priv = ife_ctx; + vfe_acquire.event_cb = cam_ife_hw_mgr_event_handler; + + switch (csid_res->res_id) { + case CAM_IFE_PIX_PATH_RES_IPP: + if (!acquire_lcr) + vfe_acquire.vfe_in.res_id = + CAM_ISP_HW_VFE_IN_CAMIF; + else + vfe_acquire.vfe_in.res_id = + CAM_ISP_HW_VFE_IN_LCR; + if (csid_res->is_dual_isp) + vfe_acquire.vfe_in.sync_mode = + CAM_ISP_HW_SYNC_MASTER; + else + vfe_acquire.vfe_in.sync_mode = + CAM_ISP_HW_SYNC_NONE; + + break; + case CAM_IFE_PIX_PATH_RES_PPP: + vfe_acquire.vfe_in.res_id = + CAM_ISP_HW_VFE_IN_PDLIB; + vfe_acquire.vfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; + + break; + case CAM_IFE_PIX_PATH_RES_RDI_0: + vfe_acquire.vfe_in.res_id = CAM_ISP_HW_VFE_IN_RDI0; + vfe_acquire.vfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; + break; + case CAM_IFE_PIX_PATH_RES_RDI_1: + vfe_acquire.vfe_in.res_id = CAM_ISP_HW_VFE_IN_RDI1; + vfe_acquire.vfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; + break; + case CAM_IFE_PIX_PATH_RES_RDI_2: + vfe_acquire.vfe_in.res_id = CAM_ISP_HW_VFE_IN_RDI2; + vfe_acquire.vfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; + break; + case CAM_IFE_PIX_PATH_RES_RDI_3: + vfe_acquire.vfe_in.res_id = CAM_ISP_HW_VFE_IN_RDI3; + vfe_acquire.vfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; + break; + default: + CAM_ERR(CAM_ISP, "Wrong IFE CSID Resource Node"); + goto err; + } + ife_src_res->res_type = vfe_acquire.rsrc_type; + ife_src_res->res_id = vfe_acquire.vfe_in.res_id; + ife_src_res->is_dual_isp = csid_res->is_dual_isp; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!csid_res->hw_res[i]) + continue; + + hw_intf = ife_hw_mgr->ife_devices[ + csid_res->hw_res[i]->hw_intf->hw_idx]; + + /* fill in more acquire information as needed */ + /* slave Camif resource, */ + if (i == CAM_ISP_HW_SPLIT_RIGHT && + ife_src_res->is_dual_isp) + vfe_acquire.vfe_in.sync_mode = + CAM_ISP_HW_SYNC_SLAVE; + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &vfe_acquire, + sizeof(struct cam_vfe_acquire_args)); + if (rc) { + CAM_ERR(CAM_ISP, + "Can not acquire IFE HW res %d", + csid_res->res_id); + goto err; + } + ife_src_res->hw_res[i] = vfe_acquire.vfe_in.rsrc_node; + + *acquired_hw_id |= + cam_convert_hw_idx_to_ife_hw_num( + hw_intf->hw_idx); + + if (i >= CAM_MAX_HW_SPLIT) { + CAM_ERR(CAM_ISP, "HW split is invalid: %d", i); + return -EINVAL; + } + + acquired_hw_path[i] |= cam_convert_res_id_to_hw_path( + ife_src_res->hw_res[i]->res_id); + + CAM_DBG(CAM_ISP, + "acquire success IFE:%d res type :0x%x res id:0x%x", + hw_intf->hw_idx, + ife_src_res->hw_res[i]->res_type, + ife_src_res->hw_res[i]->res_id); + + } + csid_res->num_children++; + } + + return 0; +err: + /* release resource at the entry function */ + return rc; +} + +static int cam_ife_hw_mgr_acquire_csid_hw( + struct cam_ife_hw_mgr *ife_hw_mgr, + struct cam_csid_hw_reserve_resource_args *csid_acquire, + bool is_start_lower_idx) +{ + int i; + int rc = -1; + struct cam_hw_intf *hw_intf; + + if (!ife_hw_mgr || !csid_acquire) { + CAM_ERR(CAM_ISP, + "Invalid args ife hw mgr %pK csid_acquire %pK", + ife_hw_mgr, csid_acquire); + return -EINVAL; + } + + if (is_start_lower_idx) { + for (i = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) { + if (!ife_hw_mgr->csid_devices[i]) + continue; + + hw_intf = ife_hw_mgr->csid_devices[i]; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + csid_acquire, + sizeof(struct + cam_csid_hw_reserve_resource_args)); + if (!rc) + return rc; + } + return rc; + } + + for (i = CAM_IFE_CSID_HW_NUM_MAX - 1; i >= 0; i--) { + if (!ife_hw_mgr->csid_devices[i]) + continue; + + hw_intf = ife_hw_mgr->csid_devices[i]; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + csid_acquire, + sizeof(struct + cam_csid_hw_reserve_resource_args)); + if (!rc) + return rc; + } + + return rc; +} + +static int cam_ife_mgr_acquire_cid_res( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_in_port_generic_info *in_port, + struct cam_isp_hw_mgr_res **cid_res, + enum cam_ife_pix_path_res_id path_res_id) +{ + int rc = -1; + int i, j; + struct cam_ife_hw_mgr *ife_hw_mgr; + struct cam_hw_intf *hw_intf; + struct cam_isp_hw_mgr_res *cid_res_temp, *cid_res_iterator; + struct cam_csid_hw_reserve_resource_args csid_acquire; + uint32_t acquired_cnt = 0; + struct cam_isp_out_port_generic_info *out_port = NULL; + + ife_hw_mgr = ife_ctx->hw_mgr; + *cid_res = NULL; + + rc = cam_ife_hw_mgr_get_res(&ife_ctx->free_res_list, cid_res); + if (rc) { + CAM_ERR(CAM_ISP, "No more free hw mgr resource"); + goto end; + } + + cid_res_temp = *cid_res; + + csid_acquire.res_type = CAM_ISP_RESOURCE_CID; + csid_acquire.in_port = in_port; + csid_acquire.res_id = path_res_id; + CAM_DBG(CAM_ISP, "path_res_id %d", path_res_id); + + if (in_port->num_out_res) + out_port = &(in_port->data[0]); + + /* Try acquiring CID resource from previously acquired HW */ + list_for_each_entry(cid_res_iterator, &ife_ctx->res_list_ife_cid, + list) { + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!cid_res_iterator->hw_res[i]) + continue; + + if (in_port->num_out_res && + ((cid_res_iterator->is_secure == 1 && + out_port->secure_mode == 0) || + (cid_res_iterator->is_secure == 0 && + out_port->secure_mode == 1))) + continue; + + if (!in_port->num_out_res && + cid_res_iterator->is_secure == 1) + continue; + + hw_intf = cid_res_iterator->hw_res[i]->hw_intf; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) { + CAM_DBG(CAM_ISP, + "No ife cid resource from hw %d", + hw_intf->hw_idx); + continue; + } + + cid_res_temp->hw_res[acquired_cnt++] = + csid_acquire.node_res; + + CAM_DBG(CAM_ISP, + "acquired from old csid(%s)=%d CID rsrc successfully", + (i == 0) ? "left" : "right", + hw_intf->hw_idx); + + if (in_port->usage_type && acquired_cnt == 1 && + path_res_id == CAM_IFE_PIX_PATH_RES_IPP) + /* + * Continue to acquire Right for IPP. + * Dual IFE for RDI and PPP is not currently + * supported. + */ + + continue; + + if (acquired_cnt) + /* + * If successfully acquired CID from + * previously acquired HW, skip the next + * part + */ + goto acquire_successful; + } + } + + /* Acquire Left if not already acquired */ + /* For dual IFE cases, start acquiring the lower idx first */ + if (ife_ctx->is_fe_enable || in_port->usage_type) + rc = cam_ife_hw_mgr_acquire_csid_hw(ife_hw_mgr, + &csid_acquire, true); + else + rc = cam_ife_hw_mgr_acquire_csid_hw(ife_hw_mgr, + &csid_acquire, false); + + if (rc || !csid_acquire.node_res) { + CAM_ERR(CAM_ISP, + "Can not acquire ife cid resource for path %d", + path_res_id); + goto put_res; + } + cid_res_temp->hw_res[acquired_cnt++] = csid_acquire.node_res; + +acquire_successful: + CAM_DBG(CAM_ISP, "CID left acquired success is_dual %d", + in_port->usage_type); + + cid_res_temp->res_type = CAM_ISP_RESOURCE_CID; + /* CID(DT_ID) value of acquire device, require for path */ + cid_res_temp->res_id = csid_acquire.node_res->res_id; + cid_res_temp->is_dual_isp = in_port->usage_type; + ife_ctx->is_dual = (bool)in_port->usage_type; + if (ife_ctx->is_dual) + ife_ctx->master_hw_idx = + cid_res_temp->hw_res[0]->hw_intf->hw_idx; + if (in_port->num_out_res) + cid_res_temp->is_secure = out_port->secure_mode; + + cam_ife_hw_mgr_put_res(&ife_ctx->res_list_ife_cid, cid_res); + + /* + * Acquire Right if not already acquired. + * Dual IFE for RDI and PPP is not currently supported. + */ + if (cid_res_temp->is_dual_isp && path_res_id + == CAM_IFE_PIX_PATH_RES_IPP && acquired_cnt == 1) { + csid_acquire.node_res = NULL; + csid_acquire.res_type = CAM_ISP_RESOURCE_CID; + csid_acquire.in_port = in_port; + for (j = 0; j < CAM_IFE_CSID_HW_NUM_MAX; j++) { + if (!ife_hw_mgr->csid_devices[j]) + continue; + + if (j == cid_res_temp->hw_res[0]->hw_intf->hw_idx) + continue; + + hw_intf = ife_hw_mgr->csid_devices[j]; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) + continue; + else + break; + } + + if (j == CAM_IFE_CSID_HW_NUM_MAX) { + CAM_ERR(CAM_ISP, + "Can not acquire ife csid rdi resource"); + goto end; + } + cid_res_temp->hw_res[1] = csid_acquire.node_res; + ife_ctx->slave_hw_idx = + cid_res_temp->hw_res[1]->hw_intf->hw_idx; + CAM_DBG(CAM_ISP, "CID right acquired success is_dual %d", + in_port->usage_type); + } + + return 0; +put_res: + cam_ife_hw_mgr_put_res(&ife_ctx->free_res_list, cid_res); +end: + return rc; + +} + +static int cam_ife_hw_mgr_acquire_res_ife_csid_pxl( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_in_port_generic_info *in_port, + bool is_ipp, + bool crop_enable) +{ + int rc = -1; + int i; + int master_idx = -1; + + struct cam_ife_hw_mgr *ife_hw_mgr; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_isp_hw_mgr_res *cid_res; + struct cam_hw_intf *hw_intf; + struct cam_csid_hw_reserve_resource_args csid_acquire; + enum cam_ife_pix_path_res_id path_res_id; + + ife_hw_mgr = ife_ctx->hw_mgr; + /* get cid resource */ + if (is_ipp) + path_res_id = CAM_IFE_PIX_PATH_RES_IPP; + else + path_res_id = CAM_IFE_PIX_PATH_RES_PPP; + + rc = cam_ife_mgr_acquire_cid_res(ife_ctx, in_port, &cid_res, + path_res_id); + + if (rc) { + CAM_ERR(CAM_ISP, "Acquire IFE CID resource Failed"); + goto end; + } + + rc = cam_ife_hw_mgr_get_res(&ife_ctx->free_res_list, &csid_res); + if (rc) { + CAM_ERR(CAM_ISP, "No more free hw mgr resource"); + goto end; + } + + csid_res->res_type = CAM_ISP_RESOURCE_PIX_PATH; + + csid_res->res_id = path_res_id; + + if (in_port->usage_type && is_ipp) + csid_res->is_dual_isp = 1; + else { + csid_res->is_dual_isp = 0; + csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE; + } + + CAM_DBG(CAM_ISP, "CSID Acq: E"); + /* IPP resource needs to be from same HW as CID resource */ + for (i = 0; i <= csid_res->is_dual_isp; i++) { + CAM_DBG(CAM_ISP, "i %d is_dual %d", i, csid_res->is_dual_isp); + + csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH; + csid_acquire.res_id = path_res_id; + csid_acquire.cid = cid_res->hw_res[i]->res_id; + csid_acquire.in_port = in_port; + csid_acquire.out_port = in_port->data; + csid_acquire.node_res = NULL; + csid_acquire.event_cb = cam_ife_hw_mgr_event_handler; + csid_acquire.priv = ife_ctx; + csid_acquire.crop_enable = crop_enable; + csid_acquire.drop_enable = false; + + hw_intf = cid_res->hw_res[i]->hw_intf; + + if (csid_res->is_dual_isp) { + if (i == CAM_ISP_HW_SPLIT_LEFT) { + master_idx = hw_intf->hw_idx; + csid_acquire.sync_mode = + CAM_ISP_HW_SYNC_MASTER; + } else { + if (master_idx == -1) { + CAM_ERR(CAM_ISP, + "No Master found"); + goto put_res; + } + csid_acquire.sync_mode = + CAM_ISP_HW_SYNC_SLAVE; + csid_acquire.master_idx = master_idx; + } + } + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) { + CAM_ERR(CAM_ISP, + "Cannot acquire ife csid pxl path rsrc %s", + (is_ipp) ? "IPP" : "PPP"); + goto put_res; + } + + csid_res->hw_res[i] = csid_acquire.node_res; + CAM_DBG(CAM_ISP, + "acquired csid(%s)=%d pxl path rsrc %s successfully", + (i == 0) ? "left" : "right", hw_intf->hw_idx, + (is_ipp) ? "IPP" : "PPP"); + } + cam_ife_hw_mgr_put_res(&ife_ctx->res_list_ife_csid, &csid_res); + cid_res->num_children++; + + CAM_DBG(CAM_ISP, "acquire res %d CID children = %d", + csid_acquire.res_id, cid_res->num_children); + + return 0; +put_res: + cam_ife_hw_mgr_put_res(&ife_ctx->free_res_list, &csid_res); +end: + return rc; +} + +static enum cam_ife_pix_path_res_id + cam_ife_hw_mgr_get_ife_csid_rdi_res_type( + uint32_t out_port_type) +{ + enum cam_ife_pix_path_res_id path_id; + CAM_DBG(CAM_ISP, "out_port_type %x", out_port_type); + + switch (out_port_type) { + case CAM_ISP_IFE_OUT_RES_RDI_0: + path_id = CAM_IFE_PIX_PATH_RES_RDI_0; + break; + case CAM_ISP_IFE_OUT_RES_RDI_1: + path_id = CAM_IFE_PIX_PATH_RES_RDI_1; + break; + case CAM_ISP_IFE_OUT_RES_RDI_2: + path_id = CAM_IFE_PIX_PATH_RES_RDI_2; + break; + case CAM_ISP_IFE_OUT_RES_RDI_3: + path_id = CAM_IFE_PIX_PATH_RES_RDI_3; + break; + default: + path_id = CAM_IFE_PIX_PATH_RES_MAX; + CAM_DBG(CAM_ISP, "maximum rdi output type exceeded"); + break; + } + + CAM_DBG(CAM_ISP, "out_port %x path_id %d", out_port_type, path_id); + + return path_id; +} + +static int cam_ife_hw_mgr_acquire_res_ife_csid_rdi( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_in_port_generic_info *in_port) +{ + int rc = -EINVAL; + int i; + + struct cam_ife_hw_mgr *ife_hw_mgr; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_isp_hw_mgr_res *cid_res; + struct cam_hw_intf *hw_intf; + struct cam_isp_out_port_generic_info *out_port; + struct cam_csid_hw_reserve_resource_args csid_acquire; + enum cam_ife_pix_path_res_id path_res_id; + + ife_hw_mgr = ife_ctx->hw_mgr; + + for (i = 0; i < in_port->num_out_res; i++) { + out_port = &in_port->data[i]; + path_res_id = cam_ife_hw_mgr_get_ife_csid_rdi_res_type( + out_port->res_type); + if (path_res_id == CAM_IFE_PIX_PATH_RES_MAX) + continue; + + /* get cid resource */ + rc = cam_ife_mgr_acquire_cid_res(ife_ctx, in_port, &cid_res, + path_res_id); + if (rc) { + CAM_ERR(CAM_ISP, "Acquire IFE CID resource Failed"); + goto end; + } + + /* For each RDI we need CID + PATH resource */ + rc = cam_ife_hw_mgr_get_res(&ife_ctx->free_res_list, + &csid_res); + if (rc) { + CAM_ERR(CAM_ISP, "No more free hw mgr resource"); + goto end; + } + + memset(&csid_acquire, 0, sizeof(csid_acquire)); + csid_acquire.res_id = path_res_id; + csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH; + csid_acquire.cid = cid_res->hw_res[0]->res_id; + csid_acquire.in_port = in_port; + csid_acquire.out_port = out_port; + csid_acquire.node_res = NULL; + csid_acquire.event_cb = cam_ife_hw_mgr_event_handler; + csid_acquire.priv = ife_ctx; + + /* + * Enable RDI pixel drop by default. CSID will enable only for + * ver 480 HW to allow userspace to control pixel drop pattern. + */ + csid_acquire.drop_enable = true; + csid_acquire.crop_enable = true; + + if (in_port->usage_type) + csid_acquire.sync_mode = CAM_ISP_HW_SYNC_MASTER; + else + csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE; + + hw_intf = cid_res->hw_res[0]->hw_intf; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) { + CAM_ERR(CAM_ISP, + "CSID Path reserve failed hw=%d rc=%d cid=%d", + hw_intf->hw_idx, rc, + cid_res->hw_res[0]->res_id); + + goto put_res; + } + + if (csid_acquire.node_res == NULL) { + CAM_ERR(CAM_ISP, "Acquire CSID RDI rsrc failed"); + + goto put_res; + } + + csid_res->res_type = CAM_ISP_RESOURCE_PIX_PATH; + csid_res->res_id = csid_acquire.res_id; + csid_res->is_dual_isp = 0; + csid_res->hw_res[0] = csid_acquire.node_res; + csid_res->hw_res[1] = NULL; + cam_ife_hw_mgr_put_res(&ife_ctx->res_list_ife_csid, &csid_res); + cid_res->num_children++; + } + + return 0; +put_res: + cam_ife_hw_mgr_put_res(&ife_ctx->free_res_list, &csid_res); +end: + return rc; +} + +static int cam_ife_hw_mgr_acquire_res_root( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_in_port_generic_info *in_port) +{ + int rc = -1; + + if (ife_ctx->res_list_ife_in.res_type == CAM_ISP_RESOURCE_UNINT) { + /* first acquire */ + ife_ctx->res_list_ife_in.res_type = CAM_ISP_RESOURCE_SRC; + ife_ctx->res_list_ife_in.res_id = in_port->res_type; + ife_ctx->res_list_ife_in.is_dual_isp = in_port->usage_type; + } else if ((ife_ctx->res_list_ife_in.res_id != + in_port->res_type) && (!ife_ctx->is_fe_enable)) { + CAM_ERR(CAM_ISP, "No Free resource for this context"); + goto err; + } else { + /* else do nothing */ + } + return 0; +err: + /* release resource in entry function */ + return rc; +} + +static int cam_ife_mgr_check_and_update_fe_v0( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_acquire_hw_info *acquire_hw_info, + uint32_t acquire_info_size) +{ + int i; + struct cam_isp_in_port_info *in_port = NULL; + uint32_t in_port_length = 0; + uint32_t total_in_port_length = 0; + + if (acquire_hw_info->input_info_offset >= + acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, + "Invalid size offset 0x%x is greater then size 0x%x", + acquire_hw_info->input_info_offset, + acquire_hw_info->input_info_size); + return -EINVAL; + } + + in_port = (struct cam_isp_in_port_info *) + ((uint8_t *)&acquire_hw_info->data + + acquire_hw_info->input_info_offset); + for (i = 0; i < acquire_hw_info->num_inputs; i++) { + + if (((uint8_t *)in_port + + sizeof(struct cam_isp_in_port_info)) > + ((uint8_t *)acquire_hw_info + + acquire_info_size)) { + CAM_ERR(CAM_ISP, "Invalid size"); + return -EINVAL; + } + + if ((in_port->num_out_res > CAM_IFE_HW_OUT_RES_MAX) || + (in_port->num_out_res <= 0)) { + CAM_ERR(CAM_ISP, "Invalid num output res %u", + in_port->num_out_res); + return -EINVAL; + } + + in_port_length = sizeof(struct cam_isp_in_port_info) + + (in_port->num_out_res - 1) * + sizeof(struct cam_isp_out_port_info); + total_in_port_length += in_port_length; + + if (total_in_port_length > acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, "buffer size is not enough"); + return -EINVAL; + } + CAM_DBG(CAM_ISP, "in_port%d res_type %d", i, + in_port->res_type); + if (in_port->res_type == CAM_ISP_IFE_IN_RES_RD) { + ife_ctx->is_fe_enable = true; + break; + } + + in_port = (struct cam_isp_in_port_info *)((uint8_t *)in_port + + in_port_length); + } + CAM_DBG(CAM_ISP, "is_fe_enable %d", ife_ctx->is_fe_enable); + + return 0; +} + +static int cam_ife_mgr_check_and_update_fe_v2( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_acquire_hw_info *acquire_hw_info, + uint32_t acquire_info_size) +{ + int i; + struct cam_isp_in_port_info_v2 *in_port = NULL; + uint32_t in_port_length = 0; + uint32_t total_in_port_length = 0; + + if (acquire_hw_info->input_info_offset >= + acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, + "Invalid size offset 0x%x is greater then size 0x%x", + acquire_hw_info->input_info_offset, + acquire_hw_info->input_info_size); + return -EINVAL; + } + + in_port = (struct cam_isp_in_port_info_v2 *) + ((uint8_t *)&acquire_hw_info->data + + acquire_hw_info->input_info_offset); + for (i = 0; i < acquire_hw_info->num_inputs; i++) { + + if (((uint8_t *)in_port + + sizeof(struct cam_isp_in_port_info)) > + ((uint8_t *)acquire_hw_info + + acquire_info_size)) { + CAM_ERR(CAM_ISP, "Invalid size"); + return -EINVAL; + } + + if ((in_port->num_out_res > CAM_IFE_HW_OUT_RES_MAX) || + (in_port->num_out_res <= 0)) { + CAM_ERR(CAM_ISP, "Invalid num output res %u", + in_port->num_out_res); + return -EINVAL; + } + + in_port_length = sizeof(struct cam_isp_in_port_info_v2) + + (in_port->num_out_res - 1) * + sizeof(struct cam_isp_out_port_info_v2); + total_in_port_length += in_port_length; + + if (total_in_port_length > acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, "buffer size is not enough"); + return -EINVAL; + } + CAM_DBG(CAM_ISP, "in_port%d res_type %d", i, + in_port->res_type); + if (in_port->res_type == CAM_ISP_IFE_IN_RES_RD) { + ife_ctx->is_fe_enable = true; + break; + } + + in_port = (struct cam_isp_in_port_info_v2 *) + ((uint8_t *)in_port + in_port_length); + } + CAM_DBG(CAM_ISP, "is_fe_enable %d", ife_ctx->is_fe_enable); + + return 0; +} + +static int cam_ife_mgr_check_and_update_fe( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_acquire_hw_info *acquire_hw_info, + uint32_t acquire_info_size) +{ + uint32_t major_ver = 0, minor_ver = 0; + + if (acquire_hw_info == NULL || ife_ctx == NULL) + return -EINVAL; + + major_ver = (acquire_hw_info->common_info_version >> 12) & 0xF; + minor_ver = (acquire_hw_info->common_info_version) & 0xFFF; + + switch (major_ver) { + case 1: + return cam_ife_mgr_check_and_update_fe_v0( + ife_ctx, acquire_hw_info, acquire_info_size); + case 2: + return cam_ife_mgr_check_and_update_fe_v2( + ife_ctx, acquire_hw_info, acquire_info_size); + break; + default: + CAM_ERR(CAM_ISP, "Invalid ver of common info from user"); + return -EINVAL; + } + + return 0; +} + +static int cam_ife_hw_mgr_preprocess_port( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_in_port_generic_info *in_port, + int *ipp_count, + int *rdi_count, + int *ppp_count, + int *ife_rd_count, + int *lcr_count) +{ + int ipp_num = 0; + int rdi_num = 0; + int ppp_num = 0; + int ife_rd_num = 0; + int lcr_num = 0; + uint32_t i; + struct cam_isp_out_port_generic_info *out_port; + struct cam_ife_hw_mgr *ife_hw_mgr; + + ife_hw_mgr = ife_ctx->hw_mgr; + + if (in_port->res_type == CAM_ISP_IFE_IN_RES_RD) { + ife_rd_num++; + } else { + for (i = 0; i < in_port->num_out_res; i++) { + out_port = &in_port->data[i]; + if (cam_ife_hw_mgr_is_rdi_res(out_port->res_type)) + rdi_num++; + else if (out_port->res_type == CAM_ISP_IFE_OUT_RES_2PD) + ppp_num++; + else if (out_port->res_type == CAM_ISP_IFE_OUT_RES_LCR) + lcr_num++; + else { + CAM_DBG(CAM_ISP, "out_res_type %d", + out_port->res_type); + ipp_num++; + } + } + } + + *ipp_count = ipp_num; + *rdi_count = rdi_num; + *ppp_count = ppp_num; + *ife_rd_count = ife_rd_num; + *lcr_count = lcr_num; + + CAM_DBG(CAM_ISP, "rdi: %d ipp: %d ppp: %d ife_rd: %d lcr: %d", + rdi_num, ipp_num, ppp_num, ife_rd_num, lcr_num); + + return 0; +} + +static int cam_ife_mgr_acquire_hw_for_ctx( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_in_port_generic_info *in_port, + uint32_t *num_pix_port, uint32_t *num_rdi_port, + uint32_t *acquired_hw_id, uint32_t *acquired_hw_path) +{ + int rc = -1; + int is_dual_isp = 0; + int ipp_count = 0; + int rdi_count = 0; + int ppp_count = 0; + int ife_rd_count = 0; + int lcr_count = 0; + bool crop_enable = true; + + is_dual_isp = in_port->usage_type; + /* get root node resource */ + rc = cam_ife_hw_mgr_acquire_res_root(ife_ctx, in_port); + if (rc) { + CAM_ERR(CAM_ISP, "Can not acquire root resource"); + goto err; + } + + cam_ife_hw_mgr_preprocess_port(ife_ctx, in_port, &ipp_count, + &rdi_count, &ppp_count, &ife_rd_count, &lcr_count); + + if (!ipp_count && !rdi_count && !ppp_count && !ife_rd_count + && !lcr_count) { + CAM_ERR(CAM_ISP, + "No PIX or RDI or PPP or IFE RD or LCR resource"); + return -EINVAL; + } + + if (ipp_count || lcr_count) { + /* get ife csid IPP resource */ + rc = cam_ife_hw_mgr_acquire_res_ife_csid_pxl(ife_ctx, + in_port, true, crop_enable); + if (rc) { + CAM_ERR(CAM_ISP, + "Acquire IFE CSID IPP/LCR resource Failed"); + goto err; + } + } + + if (rdi_count) { + /* get ife csid RDI resource */ + rc = cam_ife_hw_mgr_acquire_res_ife_csid_rdi(ife_ctx, in_port); + if (rc) { + CAM_ERR(CAM_ISP, + "Acquire IFE CSID RDI resource Failed"); + goto err; + } + } + + if (ppp_count) { + /* get ife csid PPP resource */ + + /* If both IPP and PPP paths are requested with the same vc dt + * it is implied that the sensor is a type 3 PD sensor. Crop + * must be enabled for this sensor on PPP path as well. + */ + if (!ipp_count) + crop_enable = false; + + rc = cam_ife_hw_mgr_acquire_res_ife_csid_pxl(ife_ctx, + in_port, false, crop_enable); + if (rc) { + CAM_ERR(CAM_ISP, + "Acquire IFE CSID PPP resource Failed"); + goto err; + } + } + + /* get ife src resource */ + if (ife_rd_count) { + rc = cam_ife_hw_mgr_acquire_res_ife_rd_src(ife_ctx, in_port); + rc = cam_ife_hw_mgr_acquire_res_bus_rd(ife_ctx, in_port); + + if (rc) { + CAM_ERR(CAM_ISP, "Acquire IFE RD SRC resource Failed"); + goto err; + } + } else if (ipp_count || ppp_count || rdi_count) { + rc = cam_ife_hw_mgr_acquire_res_ife_src(ife_ctx, + in_port, false, + acquired_hw_id, acquired_hw_path); + + if (rc) { + CAM_ERR(CAM_ISP, + "Acquire IFE IPP/PPP SRC resource Failed"); + goto err; + } + } + + if (lcr_count) { + rc = cam_ife_hw_mgr_acquire_res_ife_src(ife_ctx, in_port, true, + acquired_hw_id, acquired_hw_path); + + if (rc) { + CAM_ERR(CAM_ISP, "Acquire IFE LCR SRC resource Failed"); + goto err; + } + } + + CAM_DBG(CAM_ISP, "Acquiring IFE OUT resource..."); + rc = cam_ife_hw_mgr_acquire_res_ife_out(ife_ctx, in_port); + if (rc) { + CAM_ERR(CAM_ISP, "Acquire IFE OUT resource Failed"); + goto err; + } + + *num_pix_port = ipp_count + ppp_count + ife_rd_count + lcr_count; + *num_rdi_port = rdi_count; + + return 0; +err: + /* release resource at the acquire entry funciton */ + return rc; +} + +void cam_ife_cam_cdm_callback(uint32_t handle, void *userdata, + enum cam_cdm_cb_status status, uint64_t cookie) +{ + struct cam_isp_prepare_hw_update_data *hw_update_data = NULL; + struct cam_ife_hw_mgr_ctx *ctx = NULL; + + if (!userdata) { + CAM_ERR(CAM_ISP, "Invalid args"); + return; + } + + hw_update_data = (struct cam_isp_prepare_hw_update_data *)userdata; + ctx = (struct cam_ife_hw_mgr_ctx *)hw_update_data->isp_mgr_ctx; + + if (status == CAM_CDM_CB_STATUS_BL_SUCCESS) { + complete_all(&ctx->config_done_complete); + atomic_set(&ctx->cdm_done, 1); + if (g_ife_hw_mgr.debug_cfg.per_req_reg_dump) + cam_ife_mgr_handle_reg_dump(ctx, + hw_update_data->reg_dump_buf_desc, + hw_update_data->num_reg_dump_buf, + CAM_ISP_PACKET_META_REG_DUMP_PER_REQUEST, + NULL, false); + + CAM_DBG(CAM_ISP, + "Called by CDM hdl=%x, udata=%pK, status=%d, cookie=%llu ctx_index=%d", + handle, userdata, status, cookie, ctx->ctx_index); + } else { + CAM_WARN(CAM_ISP, + "Called by CDM hdl=%x, udata=%pK, status=%d, cookie=%llu", + handle, userdata, status, cookie); + } +} + +static int cam_ife_mgr_acquire_get_unified_structure_v0( + struct cam_isp_acquire_hw_info *acquire_hw_info, + uint32_t offset, uint32_t *input_size, + struct cam_isp_in_port_generic_info **in_port) +{ + struct cam_isp_in_port_info *in = NULL; + uint32_t in_port_length = 0; + struct cam_isp_in_port_generic_info *port_info = NULL; + int32_t rc = 0, i; + + in = (struct cam_isp_in_port_info *) + ((uint8_t *)&acquire_hw_info->data + + acquire_hw_info->input_info_offset + *input_size); + + in_port_length = sizeof(struct cam_isp_in_port_info) + + (in->num_out_res - 1) * + sizeof(struct cam_isp_out_port_info); + + *input_size += in_port_length; + + if ((*input_size) > acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, "Input is not proper"); + rc = -EINVAL; + } + + port_info = kzalloc( + sizeof(struct cam_isp_in_port_generic_info), GFP_KERNEL); + + if (!port_info) + return -ENOMEM; + + port_info->major_ver = + (acquire_hw_info->input_info_version >> 16) & 0xFFFF; + port_info->minor_ver = + acquire_hw_info->input_info_version & 0xFFFF; + port_info->res_type = in->res_type; + port_info->lane_type = in->lane_type; + port_info->lane_num = in->lane_num; + port_info->lane_cfg = in->lane_cfg; + port_info->vc[0] = in->vc; + port_info->dt[0] = in->dt; + port_info->num_valid_vc_dt = 1; + port_info->format = in->format; + port_info->test_pattern = in->test_pattern; + port_info->usage_type = in->usage_type; + port_info->left_start = in->left_start; + port_info->left_stop = in->left_stop; + port_info->left_width = in->left_width; + port_info->right_start = in->right_start; + port_info->right_stop = in->right_stop; + port_info->right_width = in->right_width; + port_info->line_start = in->line_start; + port_info->line_stop = in->line_stop; + port_info->height = in->height; + port_info->pixel_clk = in->pixel_clk; + port_info->batch_size = in->batch_size; + port_info->dsp_mode = in->dsp_mode; + port_info->hbi_cnt = in->hbi_cnt; + port_info->cust_node = 0; + port_info->horizontal_bin = 0; + port_info->qcfa_bin = 0; + port_info->num_out_res = in->num_out_res; + + port_info->data = kcalloc(in->num_out_res, + sizeof(struct cam_isp_out_port_generic_info), + GFP_KERNEL); + if (port_info->data == NULL) { + rc = -ENOMEM; + goto release_port_mem; + } + + for (i = 0; i < in->num_out_res; i++) { + port_info->data[i].res_type = in->data[i].res_type; + port_info->data[i].format = in->data[i].format; + port_info->data[i].width = in->data[i].width; + port_info->data[i].height = in->data[i].height; + port_info->data[i].comp_grp_id = in->data[i].comp_grp_id; + port_info->data[i].split_point = in->data[i].split_point; + port_info->data[i].secure_mode = in->data[i].secure_mode; + port_info->data[i].reserved = in->data[i].reserved; + } + *in_port = port_info; + + return 0; +release_port_mem: + kfree(port_info); + return rc; +} + +static int cam_ife_mgr_acquire_get_unified_structure_v2( + struct cam_isp_acquire_hw_info *acquire_hw_info, + uint32_t offset, uint32_t *input_size, + struct cam_isp_in_port_generic_info **in_port) +{ + struct cam_isp_in_port_info_v2 *in = NULL; + uint32_t in_port_length = 0; + struct cam_isp_in_port_generic_info *port_info = NULL; + int32_t rc = 0, i; + + in = (struct cam_isp_in_port_info_v2 *) + ((uint8_t *)&acquire_hw_info->data + + acquire_hw_info->input_info_offset + *input_size); + + in_port_length = sizeof(struct cam_isp_in_port_info_v2) + + (in->num_out_res - 1) * + sizeof(struct cam_isp_out_port_info_v2); + + *input_size += in_port_length; + + if ((*input_size) > acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, "Input is not proper"); + rc = -EINVAL; + } + + port_info = kzalloc( + sizeof(struct cam_isp_in_port_generic_info), GFP_KERNEL); + + if (!port_info) + return -ENOMEM; + + port_info->major_ver = + (acquire_hw_info->input_info_version >> 16) & 0xFFFF; + port_info->minor_ver = + acquire_hw_info->input_info_version & 0xFFFF; + port_info->res_type = in->res_type; + port_info->lane_type = in->lane_type; + port_info->lane_num = in->lane_num; + port_info->lane_cfg = in->lane_cfg; + port_info->num_valid_vc_dt = in->num_valid_vc_dt; + + if (port_info->num_valid_vc_dt == 0 || + port_info->num_valid_vc_dt >= CAM_ISP_VC_DT_CFG) { + CAM_ERR(CAM_ISP, "Invalid i/p arg invalid vc-dt: %d", + in->num_valid_vc_dt); + rc = -EINVAL; + goto release_mem; + } + + for (i = 0; i < port_info->num_valid_vc_dt; i++) { + port_info->vc[i] = in->vc[i]; + port_info->dt[i] = in->dt[i]; + } + + port_info->format = in->format; + port_info->test_pattern = in->test_pattern; + port_info->usage_type = in->usage_type; + port_info->left_start = in->left_start; + port_info->left_stop = in->left_stop; + port_info->left_width = in->left_width; + port_info->right_start = in->right_start; + port_info->right_stop = in->right_stop; + port_info->right_width = in->right_width; + port_info->line_start = in->line_start; + port_info->line_stop = in->line_stop; + port_info->height = in->height; + port_info->pixel_clk = in->pixel_clk; + port_info->batch_size = in->batch_size; + port_info->dsp_mode = in->dsp_mode; + port_info->hbi_cnt = in->hbi_cnt; + port_info->cust_node = in->cust_node; + port_info->horizontal_bin = in->horizontal_bin; + port_info->qcfa_bin = in->qcfa_bin; + port_info->num_out_res = in->num_out_res; + + port_info->data = kcalloc(in->num_out_res, + sizeof(struct cam_isp_out_port_generic_info), + GFP_KERNEL); + if (port_info->data == NULL) { + rc = -ENOMEM; + goto release_mem; + } + + for (i = 0; i < port_info->num_out_res; i++) { + port_info->data[i].res_type = in->data[i].res_type; + port_info->data[i].format = in->data[i].format; + port_info->data[i].width = in->data[i].width; + port_info->data[i].height = in->data[i].height; + port_info->data[i].comp_grp_id = in->data[i].comp_grp_id; + port_info->data[i].split_point = in->data[i].split_point; + port_info->data[i].secure_mode = in->data[i].secure_mode; + } + + *in_port = port_info; + + return 0; + +release_mem: + kfree(port_info); + return rc; +} + +static int cam_ife_mgr_acquire_get_unified_structure( + struct cam_isp_acquire_hw_info *acquire_hw_info, + uint32_t offset, uint32_t *input_size, + struct cam_isp_in_port_generic_info **in_port) +{ + uint32_t major_ver = 0, minor_ver = 0; + + if (acquire_hw_info == NULL || input_size == NULL) + return -EINVAL; + + major_ver = (acquire_hw_info->common_info_version >> 12) & 0xF; + minor_ver = (acquire_hw_info->common_info_version) & 0xFFF; + + switch (major_ver) { + case 1: + return cam_ife_mgr_acquire_get_unified_structure_v0( + acquire_hw_info, offset, input_size, in_port); + case 2: + return cam_ife_mgr_acquire_get_unified_structure_v2( + acquire_hw_info, offset, input_size, in_port); + break; + default: + CAM_ERR(CAM_ISP, "Invalid ver of i/p port info from user"); + return -EINVAL; + } + + return 0; +} + +/* entry function: acquire_hw */ +static int cam_ife_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) +{ + struct cam_ife_hw_mgr *ife_hw_mgr = hw_mgr_priv; + struct cam_hw_acquire_args *acquire_args = acquire_hw_args; + int rc = -1; + int i, j; + struct cam_ife_hw_mgr_ctx *ife_ctx; + struct cam_isp_in_port_generic_info *in_port = NULL; + struct cam_cdm_acquire_data cdm_acquire; + uint32_t num_pix_port_per_in = 0; + uint32_t num_rdi_port_per_in = 0; + uint32_t total_pix_port = 0; + uint32_t total_rdi_port = 0; + struct cam_isp_acquire_hw_info *acquire_hw_info = NULL; + uint32_t input_size = 0; + + CAM_DBG(CAM_ISP, "Enter..."); + + if (!acquire_args || acquire_args->num_acq <= 0) { + CAM_ERR(CAM_ISP, "Nothing to acquire. Seems like error"); + return -EINVAL; + } + + /* get the ife ctx */ + rc = cam_ife_hw_mgr_get_ctx(&ife_hw_mgr->free_ctx_list, &ife_ctx); + if (rc || !ife_ctx) { + CAM_ERR(CAM_ISP, "Get ife hw context failed"); + goto err; + } + + ife_ctx->common.cb_priv = acquire_args->context_data; + for (i = 0; i < CAM_ISP_HW_EVENT_MAX; i++) + ife_ctx->common.event_cb[i] = acquire_args->event_cb; + + ife_ctx->hw_mgr = ife_hw_mgr; + + + memcpy(cdm_acquire.identifier, "ife", sizeof("ife")); + cdm_acquire.cell_index = 0; + cdm_acquire.handle = 0; + cdm_acquire.userdata = ife_ctx; + cdm_acquire.base_array_cnt = CAM_IFE_HW_NUM_MAX; + for (i = 0, j = 0; i < CAM_IFE_HW_NUM_MAX; i++) { + if (ife_hw_mgr->cdm_reg_map[i]) + cdm_acquire.base_array[j++] = + ife_hw_mgr->cdm_reg_map[i]; + } + + cdm_acquire.base_array_cnt = j; + cdm_acquire.priority = CAM_CDM_BL_FIFO_0; + cdm_acquire.id = CAM_CDM_VIRTUAL; + cdm_acquire.cam_cdm_callback = cam_ife_cam_cdm_callback; + rc = cam_cdm_acquire(&cdm_acquire); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to acquire the CDM HW"); + goto free_ctx; + } + + CAM_DBG(CAM_ISP, "Successfully acquired the CDM HW hdl=%x", + cdm_acquire.handle); + ife_ctx->cdm_handle = cdm_acquire.handle; + ife_ctx->cdm_ops = cdm_acquire.ops; + atomic_set(&ife_ctx->cdm_done, 1); + + acquire_hw_info = + (struct cam_isp_acquire_hw_info *)acquire_args->acquire_info; + + rc = cam_ife_mgr_check_and_update_fe(ife_ctx, acquire_hw_info, + acquire_args->acquire_info_size); + if (rc) { + CAM_ERR(CAM_ISP, "buffer size is not enough"); + goto free_cdm; + } + + /* acquire HW resources */ + for (i = 0; i < acquire_hw_info->num_inputs; i++) { + rc = cam_ife_mgr_acquire_get_unified_structure(acquire_hw_info, + i, &input_size, &in_port); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Failed in parsing: %d", rc); + goto free_res; + } + CAM_DBG(CAM_ISP, "in_res_type %x", in_port->res_type); + + rc = cam_ife_mgr_acquire_hw_for_ctx(ife_ctx, in_port, + &num_pix_port_per_in, &num_rdi_port_per_in, + &acquire_args->acquired_hw_id[i], + acquire_args->acquired_hw_path[i]); + + total_pix_port += num_pix_port_per_in; + total_rdi_port += num_rdi_port_per_in; + + if (rc) { + CAM_ERR(CAM_ISP, "can not acquire resource"); + cam_ife_hw_mgr_dump_src_acq_info(ife_ctx, + total_pix_port, total_rdi_port); + goto free_mem; + } + + kfree(in_port->data); + kfree(in_port); + in_port = NULL; + } + + /* Check whether context has only RDI resource */ + if (!total_pix_port) { + ife_ctx->is_rdi_only_context = 1; + CAM_DBG(CAM_ISP, "RDI only context"); + } + + /* Process base info */ + rc = cam_ife_mgr_process_base_info(ife_ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Process base info failed"); + goto free_res; + } + + acquire_args->ctxt_to_hw_map = ife_ctx; + ife_ctx->ctx_in_use = 1; + + acquire_args->valid_acquired_hw = + acquire_hw_info->num_inputs; + + getnstimeofday64(&ife_ctx->ts); + CAM_INFO(CAM_ISP, + "Acquire HW success with total_pix: %u total_rdi: %u is_dual: %u in ctx: %u", + total_pix_port, total_rdi_port, + ife_ctx->is_dual, ife_ctx->ctx_index); + + cam_ife_hw_mgr_put_ctx(&ife_hw_mgr->used_ctx_list, &ife_ctx); + + return 0; +free_mem: + kfree(in_port->data); + kfree(in_port); +free_res: + cam_ife_hw_mgr_release_hw_for_ctx(ife_ctx); +free_cdm: + cam_cdm_release(ife_ctx->cdm_handle); +free_ctx: + cam_ife_hw_mgr_put_ctx(&ife_hw_mgr->free_ctx_list, &ife_ctx); +err: + CAM_DBG(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; +} + +void cam_ife_mgr_acquire_get_unified_dev_str(struct cam_isp_in_port_info *in, + struct cam_isp_in_port_generic_info *gen_port_info) +{ + int i; + + gen_port_info->res_type = in->res_type; + gen_port_info->lane_type = in->lane_type; + gen_port_info->lane_num = in->lane_num; + gen_port_info->lane_cfg = in->lane_cfg; + gen_port_info->vc[0] = in->vc; + gen_port_info->dt[0] = in->dt; + gen_port_info->num_valid_vc_dt = 1; + gen_port_info->format = in->format; + gen_port_info->test_pattern = in->test_pattern; + gen_port_info->usage_type = in->usage_type; + gen_port_info->left_start = in->left_start; + gen_port_info->left_stop = in->left_stop; + gen_port_info->left_width = in->left_width; + gen_port_info->right_start = in->right_start; + gen_port_info->right_stop = in->right_stop; + gen_port_info->right_width = in->right_width; + gen_port_info->line_start = in->line_start; + gen_port_info->line_stop = in->line_stop; + gen_port_info->height = in->height; + gen_port_info->pixel_clk = in->pixel_clk; + gen_port_info->batch_size = in->batch_size; + gen_port_info->dsp_mode = in->dsp_mode; + gen_port_info->hbi_cnt = in->hbi_cnt; + gen_port_info->cust_node = 0; + gen_port_info->num_out_res = in->num_out_res; + + for (i = 0; i < in->num_out_res; i++) { + gen_port_info->data[i].res_type = in->data[i].res_type; + gen_port_info->data[i].format = in->data[i].format; + gen_port_info->data[i].width = in->data[i].width; + gen_port_info->data[i].height = in->data[i].height; + gen_port_info->data[i].comp_grp_id = in->data[i].comp_grp_id; + gen_port_info->data[i].split_point = in->data[i].split_point; + gen_port_info->data[i].secure_mode = in->data[i].secure_mode; + } +} + +/* entry function: acquire_hw */ +static int cam_ife_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) +{ + struct cam_ife_hw_mgr *ife_hw_mgr = hw_mgr_priv; + struct cam_hw_acquire_args *acquire_args = acquire_hw_args; + int rc = -1; + int i, j; + struct cam_ife_hw_mgr_ctx *ife_ctx; + struct cam_isp_in_port_info *in_port = NULL; + struct cam_isp_resource *isp_resource = NULL; + struct cam_cdm_acquire_data cdm_acquire; + struct cam_isp_in_port_generic_info *gen_port_info = NULL; + uint32_t num_pix_port_per_in = 0; + uint32_t num_rdi_port_per_in = 0; + uint32_t total_pix_port = 0; + uint32_t total_rdi_port = 0; + uint32_t in_port_length = 0; + + CAM_DBG(CAM_ISP, "Enter..."); + + if (!acquire_args || acquire_args->num_acq <= 0) { + CAM_ERR(CAM_ISP, "Nothing to acquire. Seems like error"); + return -EINVAL; + } + + /* get the ife ctx */ + rc = cam_ife_hw_mgr_get_ctx(&ife_hw_mgr->free_ctx_list, &ife_ctx); + if (rc || !ife_ctx) { + CAM_ERR(CAM_ISP, "Get ife hw context failed"); + goto err; + } + + ife_ctx->common.cb_priv = acquire_args->context_data; + for (i = 0; i < CAM_ISP_HW_EVENT_MAX; i++) + ife_ctx->common.event_cb[i] = acquire_args->event_cb; + + ife_ctx->hw_mgr = ife_hw_mgr; + + + memcpy(cdm_acquire.identifier, "ife", sizeof("ife")); + cdm_acquire.cell_index = 0; + cdm_acquire.handle = 0; + cdm_acquire.userdata = ife_ctx; + cdm_acquire.base_array_cnt = CAM_IFE_HW_NUM_MAX; + for (i = 0, j = 0; i < CAM_IFE_HW_NUM_MAX; i++) { + if (ife_hw_mgr->cdm_reg_map[i]) + cdm_acquire.base_array[j++] = + ife_hw_mgr->cdm_reg_map[i]; + } + + cdm_acquire.base_array_cnt = j; + cdm_acquire.priority = CAM_CDM_BL_FIFO_0; + cdm_acquire.id = CAM_CDM_VIRTUAL; + cdm_acquire.cam_cdm_callback = cam_ife_cam_cdm_callback; + rc = cam_cdm_acquire(&cdm_acquire); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to acquire the CDM HW"); + goto free_ctx; + } + + CAM_DBG(CAM_ISP, "Successfully acquired the CDM HW hdl=%x", + cdm_acquire.handle); + ife_ctx->cdm_handle = cdm_acquire.handle; + ife_ctx->cdm_ops = cdm_acquire.ops; + atomic_set(&ife_ctx->cdm_done, 1); + + isp_resource = (struct cam_isp_resource *)acquire_args->acquire_info; + + /* acquire HW resources */ + for (i = 0; i < acquire_args->num_acq; i++) { + if (isp_resource[i].resource_id != CAM_ISP_RES_ID_PORT) + continue; + + CAM_DBG(CAM_ISP, "acquire no = %d total = %d", i, + acquire_args->num_acq); + CAM_DBG(CAM_ISP, + "start copy from user handle %lld with len = %d", + isp_resource[i].res_hdl, + isp_resource[i].length); + + in_port_length = sizeof(struct cam_isp_in_port_info); + + if (in_port_length > isp_resource[i].length) { + CAM_ERR(CAM_ISP, "buffer size is not enough"); + rc = -EINVAL; + goto free_res; + } + + in_port = memdup_user( + u64_to_user_ptr(isp_resource[i].res_hdl), + isp_resource[i].length); + if (!IS_ERR(in_port)) { + if (in_port->num_out_res > CAM_IFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "too many output res %d", + in_port->num_out_res); + rc = -EINVAL; + kfree(in_port); + goto free_res; + } + + in_port_length = sizeof(struct cam_isp_in_port_info) + + (in_port->num_out_res - 1) * + sizeof(struct cam_isp_out_port_info); + if (in_port_length > isp_resource[i].length) { + CAM_ERR(CAM_ISP, "buffer size is not enough"); + rc = -EINVAL; + kfree(in_port); + goto free_res; + } + + gen_port_info = kzalloc( + sizeof(struct cam_isp_in_port_generic_info), + GFP_KERNEL); + if (gen_port_info == NULL) { + rc = -ENOMEM; + goto free_res; + } + + gen_port_info->data = kcalloc( + sizeof(struct cam_isp_out_port_generic_info), + in_port->num_out_res, GFP_KERNEL); + if (gen_port_info->data == NULL) { + kfree(gen_port_info); + gen_port_info = NULL; + rc = -ENOMEM; + goto free_res; + } + + cam_ife_mgr_acquire_get_unified_dev_str(in_port, + gen_port_info); + + rc = cam_ife_mgr_acquire_hw_for_ctx(ife_ctx, + gen_port_info, &num_pix_port_per_in, + &num_rdi_port_per_in, + &acquire_args->acquired_hw_id[i], + acquire_args->acquired_hw_path[i]); + + total_pix_port += num_pix_port_per_in; + total_rdi_port += num_rdi_port_per_in; + + kfree(in_port); + if (gen_port_info != NULL) { + kfree(gen_port_info->data); + kfree(gen_port_info); + gen_port_info = NULL; + } + if (rc) { + CAM_ERR(CAM_ISP, "can not acquire resource"); + goto free_res; + } + } else { + CAM_ERR(CAM_ISP, + "Copy from user failed with in_port = %pK", + in_port); + rc = -EFAULT; + goto free_res; + } + } + + /* Check whether context has only RDI resource */ + if (!total_pix_port) { + ife_ctx->is_rdi_only_context = 1; + CAM_DBG(CAM_ISP, "RDI only context"); + } + + /* Process base info */ + rc = cam_ife_mgr_process_base_info(ife_ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Process base info failed"); + goto free_res; + } + + acquire_args->ctxt_to_hw_map = ife_ctx; + ife_ctx->ctx_in_use = 1; + + CAM_INFO(CAM_ISP, + "Acquire HW success with total_pix: %u total_rdi: %u is_dual: %u in ctx: %u", + total_pix_port, total_rdi_port, + ife_ctx->is_dual, ife_ctx->ctx_index); + + cam_ife_hw_mgr_put_ctx(&ife_hw_mgr->used_ctx_list, &ife_ctx); + + return 0; +free_res: + cam_ife_hw_mgr_release_hw_for_ctx(ife_ctx); + cam_cdm_release(ife_ctx->cdm_handle); +free_ctx: + cam_ife_hw_mgr_put_ctx(&ife_hw_mgr->free_ctx_list, &ife_ctx); +err: + CAM_DBG(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; +} + +/* entry function: acquire_hw */ +static int cam_ife_mgr_acquire(void *hw_mgr_priv, + void *acquire_hw_args) +{ + struct cam_hw_acquire_args *acquire_args = acquire_hw_args; + int rc = -1; + + CAM_DBG(CAM_ISP, "Enter..."); + + if (!acquire_args || acquire_args->num_acq <= 0) { + CAM_ERR(CAM_ISP, "Nothing to acquire. Seems like error"); + return -EINVAL; + } + + if (acquire_args->num_acq == CAM_API_COMPAT_CONSTANT) + rc = cam_ife_mgr_acquire_hw(hw_mgr_priv, acquire_hw_args); + else + rc = cam_ife_mgr_acquire_dev(hw_mgr_priv, acquire_hw_args); + + CAM_DBG(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; +} + +static const char *cam_isp_util_usage_data_to_string( + uint32_t usage_data) +{ + switch (usage_data) { + case CAM_ISP_USAGE_LEFT_PX: + return "LEFT_PX"; + case CAM_ISP_USAGE_RIGHT_PX: + return "RIGHT_PX"; + case CAM_ISP_USAGE_RDI: + return "RDI"; + default: + return "USAGE_INVALID"; + } +} + +static int cam_isp_classify_vote_info( + struct cam_isp_hw_mgr_res *hw_mgr_res, + struct cam_isp_bw_config_v2 *bw_config, + struct cam_axi_vote *isp_vote, + uint32_t split_idx, + bool *camif_l_bw_updated, + bool *camif_r_bw_updated) +{ + int rc = 0, i, j = 0; + + if ((hw_mgr_res->res_id == CAM_ISP_HW_VFE_IN_CAMIF) + || (hw_mgr_res->res_id == CAM_ISP_HW_VFE_IN_RD) || + (hw_mgr_res->res_id == CAM_ISP_HW_VFE_IN_PDLIB) || + (hw_mgr_res->res_id == CAM_ISP_HW_VFE_IN_LCR)) { + if (split_idx == CAM_ISP_HW_SPLIT_LEFT) { + if (*camif_l_bw_updated) + return rc; + + for (i = 0; i < bw_config->num_paths; i++) { + if (bw_config->axi_path[i].usage_data == + CAM_ISP_USAGE_LEFT_PX) { + memcpy(&isp_vote->axi_path[j], + &bw_config->axi_path[i], + sizeof(struct + cam_axi_per_path_bw_vote)); + j++; + } + } + isp_vote->num_paths = j; + + *camif_l_bw_updated = true; + } else { + if (*camif_r_bw_updated) + return rc; + + for (i = 0; i < bw_config->num_paths; i++) { + if (bw_config->axi_path[i].usage_data == + CAM_ISP_USAGE_RIGHT_PX) { + memcpy(&isp_vote->axi_path[j], + &bw_config->axi_path[i], + sizeof(struct + cam_axi_per_path_bw_vote)); + j++; + } + } + isp_vote->num_paths = j; + + *camif_r_bw_updated = true; + } + } else if ((hw_mgr_res->res_id >= CAM_ISP_HW_VFE_IN_RDI0) + && (hw_mgr_res->res_id <= + CAM_ISP_HW_VFE_IN_RDI3)) { + for (i = 0; i < bw_config->num_paths; i++) { + if ((bw_config->axi_path[i].usage_data == + CAM_ISP_USAGE_RDI) && + ((bw_config->axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_IFE_RDI0) == + (hw_mgr_res->res_id - + CAM_ISP_HW_VFE_IN_RDI0))) { + memcpy(&isp_vote->axi_path[j], + &bw_config->axi_path[i], + sizeof(struct + cam_axi_per_path_bw_vote)); + j++; + } + } + isp_vote->num_paths = j; + + } else { + if (hw_mgr_res->hw_res[split_idx]) { + CAM_ERR(CAM_ISP, "Invalid res_id %u, split_idx: %u", + hw_mgr_res->res_id, split_idx); + rc = -EINVAL; + return rc; + } + } + + for (i = 0; i < isp_vote->num_paths; i++) { + CAM_DBG(CAM_PERF, + "CLASSIFY_VOTE [%s] [%s] [%s] [%llu] [%llu] [%llu]", + cam_isp_util_usage_data_to_string( + isp_vote->axi_path[i].usage_data), + cam_cpas_axi_util_path_type_to_string( + isp_vote->axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + isp_vote->axi_path[i].transac_type), + isp_vote->axi_path[i].camnoc_bw, + isp_vote->axi_path[i].mnoc_ab_bw, + isp_vote->axi_path[i].mnoc_ib_bw); + } + + return rc; +} + +static int cam_isp_blob_bw_update_v2( + struct cam_isp_bw_config_v2 *bw_config, + struct cam_ife_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_vfe_bw_update_args_v2 bw_upd_args; + int rc = -EINVAL; + uint32_t i, split_idx; + bool camif_l_bw_updated = false; + bool camif_r_bw_updated = false; + + for (i = 0; i < bw_config->num_paths; i++) { + CAM_DBG(CAM_PERF, + "ISP_BLOB usage_type=%u [%s] [%s] [%s] [%llu] [%llu] [%llu]", + bw_config->usage_type, + cam_isp_util_usage_data_to_string( + bw_config->axi_path[i].usage_data), + cam_cpas_axi_util_path_type_to_string( + bw_config->axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + bw_config->axi_path[i].transac_type), + bw_config->axi_path[i].camnoc_bw, + bw_config->axi_path[i].mnoc_ab_bw, + bw_config->axi_path[i].mnoc_ib_bw); + } + + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + for (split_idx = 0; split_idx < CAM_ISP_HW_SPLIT_MAX; + split_idx++) { + if (!hw_mgr_res->hw_res[split_idx]) + continue; + + memset(&bw_upd_args.isp_vote, 0, + sizeof(struct cam_axi_vote)); + rc = cam_isp_classify_vote_info(hw_mgr_res, bw_config, + &bw_upd_args.isp_vote, split_idx, + &camif_l_bw_updated, &camif_r_bw_updated); + if (rc) + return rc; + + if (!bw_upd_args.isp_vote.num_paths) + continue; + + hw_intf = hw_mgr_res->hw_res[split_idx]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + bw_upd_args.node_res = + hw_mgr_res->hw_res[split_idx]; + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_BW_UPDATE_V2, + &bw_upd_args, + sizeof( + struct cam_vfe_bw_update_args_v2)); + if (rc) + CAM_ERR(CAM_PERF, + "BW Update failed rc: %d", rc); + } else { + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } + } + } + + return rc; +} + +static int cam_isp_blob_bw_update( + struct cam_isp_bw_config *bw_config, + struct cam_ife_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_vfe_bw_update_args bw_upd_args; + uint64_t cam_bw_bps = 0; + uint64_t ext_bw_bps = 0; + int rc = -EINVAL; + uint32_t i; + bool camif_l_bw_updated = false; + bool camif_r_bw_updated = false; + + CAM_DBG(CAM_PERF, + "ISP_BLOB usage=%u left cam_bw_bps=%llu ext_bw_bps=%llu, right cam_bw_bps=%llu ext_bw_bps=%llu", + bw_config->usage_type, + bw_config->left_pix_vote.cam_bw_bps, + bw_config->left_pix_vote.ext_bw_bps, + bw_config->right_pix_vote.cam_bw_bps, + bw_config->right_pix_vote.ext_bw_bps); + + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + if ((hw_mgr_res->res_id == CAM_ISP_HW_VFE_IN_CAMIF) || + (hw_mgr_res->res_id == CAM_ISP_HW_VFE_IN_RD) || + (hw_mgr_res->res_id == CAM_ISP_HW_VFE_IN_PDLIB) + || (hw_mgr_res->res_id == + CAM_ISP_HW_VFE_IN_LCR)) + if (i == CAM_ISP_HW_SPLIT_LEFT) { + if (camif_l_bw_updated) + continue; + + cam_bw_bps = + bw_config->left_pix_vote.cam_bw_bps; + ext_bw_bps = + bw_config->left_pix_vote.ext_bw_bps; + + camif_l_bw_updated = true; + } else { + if (camif_r_bw_updated) + continue; + + cam_bw_bps = + bw_config->right_pix_vote.cam_bw_bps; + ext_bw_bps = + bw_config->right_pix_vote.ext_bw_bps; + + camif_r_bw_updated = true; + } + else if ((hw_mgr_res->res_id >= CAM_ISP_HW_VFE_IN_RDI0) + && (hw_mgr_res->res_id <= + CAM_ISP_HW_VFE_IN_RDI3)) { + uint32_t idx = hw_mgr_res->res_id - + CAM_ISP_HW_VFE_IN_RDI0; + if (idx >= bw_config->num_rdi) + continue; + + cam_bw_bps = + bw_config->rdi_vote[idx].cam_bw_bps; + ext_bw_bps = + bw_config->rdi_vote[idx].ext_bw_bps; + } else { + if (hw_mgr_res->hw_res[i]) { + CAM_ERR(CAM_ISP, "Invalid res_id %u", + hw_mgr_res->res_id); + rc = -EINVAL; + return rc; + } + } + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + bw_upd_args.node_res = + hw_mgr_res->hw_res[i]; + + bw_upd_args.camnoc_bw_bytes = cam_bw_bps; + bw_upd_args.external_bw_bytes = ext_bw_bps; + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_BW_UPDATE, + &bw_upd_args, + sizeof(struct cam_vfe_bw_update_args)); + if (rc) + CAM_ERR(CAM_PERF, "BW Update failed"); + } else + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } + } + + return rc; +} + +/* entry function: config_hw */ +static int cam_ife_mgr_config_hw(void *hw_mgr_priv, + void *config_hw_args) +{ + int rc = -1, i, skip = 0; + struct cam_hw_config_args *cfg; + struct cam_hw_update_entry *cmd; + struct cam_cdm_bl_request *cdm_cmd; + struct cam_ife_hw_mgr_ctx *ctx; + struct cam_isp_prepare_hw_update_data *hw_update_data; + + if (!hw_mgr_priv || !config_hw_args) { + CAM_ERR(CAM_ISP, + "Invalid arguments, hw_mgr_priv=%pK, config_hw_args=%pK", + hw_mgr_priv, config_hw_args); + return -EINVAL; + } + + cfg = config_hw_args; + ctx = (struct cam_ife_hw_mgr_ctx *)cfg->ctxt_to_hw_map; + if (!ctx) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EINVAL; + } + + if (!ctx->ctx_in_use || !ctx->cdm_cmd) { + CAM_ERR(CAM_ISP, + "Invalid context parameters : ctx_in_use=%d, cdm_cmd=%pK", + ctx->ctx_in_use, ctx->cdm_cmd); + return -EPERM; + } + + if (atomic_read(&ctx->overflow_pending)) { + CAM_DBG(CAM_ISP, + "Ctx[%pK][%d] Overflow pending, cannot apply req %llu", + ctx, ctx->ctx_index, cfg->request_id); + return -EPERM; + } + + hw_update_data = (struct cam_isp_prepare_hw_update_data *) cfg->priv; + hw_update_data->isp_mgr_ctx = ctx; + + CAM_DBG(CAM_ISP, "Ctx[%pK][%d] : Applying Req %lld, init_packet=%d", + ctx, ctx->ctx_index, cfg->request_id, cfg->init_packet); + + for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) { + if (hw_update_data->bw_config_valid[i] == true) { + + CAM_DBG(CAM_PERF, "idx=%d, bw_config_version=%d", + ctx, ctx->ctx_index, i, + hw_update_data->bw_config_version); + + if (hw_update_data->bw_config_version == + CAM_ISP_BW_CONFIG_V1) { + rc = cam_isp_blob_bw_update( + (struct cam_isp_bw_config *) + &hw_update_data->bw_config[i], ctx); + if (rc) + CAM_ERR(CAM_PERF, + "Bandwidth Update Failed rc: %d", rc); + } else if (hw_update_data->bw_config_version == + CAM_ISP_BW_CONFIG_V2) { + rc = cam_isp_blob_bw_update_v2( + (struct cam_isp_bw_config_v2 *) + &hw_update_data->bw_config_v2[i], ctx); + if (rc) + CAM_ERR(CAM_PERF, + "Bandwidth Update Failed rc: %d", rc); + + } else { + CAM_ERR(CAM_PERF, + "Invalid bw config version: %d", + hw_update_data->bw_config_version); + } + } + } + + CAM_DBG(CAM_ISP, + "Enter ctx id:%d num_hw_upd_entries %d request id: %llu", + ctx->ctx_index, cfg->num_hw_update_entries, cfg->request_id); + + if (cfg->num_hw_update_entries > 0) { + cdm_cmd = ctx->cdm_cmd; + cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE; + cdm_cmd->flag = true; + cdm_cmd->userdata = hw_update_data; + cdm_cmd->cookie = cfg->request_id; + cdm_cmd->gen_irq_arb = false; + + for (i = 0 ; i < cfg->num_hw_update_entries; i++) { + cmd = (cfg->hw_update_entries + i); + + if (cfg->reapply && + cmd->flags == CAM_ISP_IQ_BL) { + skip++; + continue; + } + + if (cmd->flags == CAM_ISP_UNUSED_BL || + cmd->flags >= CAM_ISP_BL_MAX) + CAM_ERR(CAM_ISP, "Unexpected BL type %d", + cmd->flags); + + cdm_cmd->cmd[i - skip].bl_addr.mem_handle = cmd->handle; + cdm_cmd->cmd[i - skip].offset = cmd->offset; + cdm_cmd->cmd[i - skip].len = cmd->len; + cdm_cmd->cmd[i - skip].arbitrate = false; + } + cdm_cmd->cmd_arrary_count = cfg->num_hw_update_entries - skip; + + reinit_completion(&ctx->config_done_complete); + ctx->applied_req_id = cfg->request_id; + + CAM_DBG(CAM_ISP, "Submit to CDM"); + atomic_set(&ctx->cdm_done, 0); + rc = cam_cdm_submit_bls(ctx->cdm_handle, cdm_cmd); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed to apply the configs for req %llu, rc %d", + cfg->request_id, rc); + return rc; + } + + if (cfg->init_packet) { + rc = wait_for_completion_timeout( + &ctx->config_done_complete, + msecs_to_jiffies(30)); + if (rc <= 0) { + CAM_ERR(CAM_ISP, + "config done completion timeout for req_id=%llu rc=%d ctx_index %d", + cfg->request_id, rc, ctx->ctx_index); + if (rc == 0) + rc = -ETIMEDOUT; + } else { + rc = 0; + CAM_DBG(CAM_ISP, + "config done Success for req_id=%llu ctx_index %d", + cfg->request_id, ctx->ctx_index); + } + } + } else { + CAM_ERR(CAM_ISP, "No commands to config"); + } + CAM_DBG(CAM_ISP, "Exit: Config Done: %llu", cfg->request_id); + + return rc; +} + +static int cam_ife_mgr_stop_hw_in_overflow(void *stop_hw_args) +{ + int rc = 0; + struct cam_hw_stop_args *stop_args = stop_hw_args; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_ife_hw_mgr_ctx *ctx; + uint32_t i, master_base_idx = 0; + + if (!stop_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + ctx = (struct cam_ife_hw_mgr_ctx *)stop_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, "Enter...ctx id:%d", + ctx->ctx_index); + + if (!ctx->num_base) { + CAM_ERR(CAM_ISP, "Number of bases are zero"); + return -EINVAL; + } + + /* get master base index first */ + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].split_id == CAM_ISP_HW_SPLIT_LEFT) { + master_base_idx = ctx->base[i].idx; + break; + } + } + + if (i == ctx->num_base) + master_base_idx = ctx->base[0].idx; + + + /* stop the master CIDs first */ + cam_ife_mgr_csid_stop_hw(ctx, &ctx->res_list_ife_cid, + master_base_idx, CAM_CSID_HALT_IMMEDIATELY); + + /* stop rest of the CIDs */ + for (i = 0; i < ctx->num_base; i++) { + if (i == master_base_idx) + continue; + cam_ife_mgr_csid_stop_hw(ctx, &ctx->res_list_ife_cid, + ctx->base[i].idx, CAM_CSID_HALT_IMMEDIATELY); + } + + /* stop the master CSID path first */ + cam_ife_mgr_csid_stop_hw(ctx, &ctx->res_list_ife_csid, + master_base_idx, CAM_CSID_HALT_IMMEDIATELY); + + /* Stop rest of the CSID paths */ + for (i = 0; i < ctx->num_base; i++) { + if (i == master_base_idx) + continue; + + cam_ife_mgr_csid_stop_hw(ctx, &ctx->res_list_ife_csid, + ctx->base[i].idx, CAM_CSID_HALT_IMMEDIATELY); + } + + /* IFE mux in resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + cam_ife_hw_mgr_stop_hw_res(hw_mgr_res); + } + + /* IFE bus rd resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_in_rd, list) { + cam_ife_hw_mgr_stop_hw_res(hw_mgr_res); + } + + /* IFE out resources */ + for (i = 0; i < CAM_IFE_HW_OUT_RES_MAX; i++) + cam_ife_hw_mgr_stop_hw_res(&ctx->res_list_ife_out[i]); + + + /* Stop tasklet for context */ + cam_tasklet_stop(ctx->common.tasklet_info); + CAM_DBG(CAM_ISP, "Exit...ctx id:%d rc :%d", + ctx->ctx_index, rc); + + return rc; +} + +static int cam_ife_mgr_bw_control(struct cam_ife_hw_mgr_ctx *ctx, + enum cam_vfe_bw_control_action action) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_vfe_bw_control_args bw_ctrl_args; + int rc = -EINVAL; + uint32_t i; + + CAM_DBG(CAM_ISP, "Enter...ctx id:%d", ctx->ctx_index); + + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + bw_ctrl_args.node_res = + hw_mgr_res->hw_res[i]; + bw_ctrl_args.action = action; + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_BW_CONTROL, + &bw_ctrl_args, + sizeof(struct cam_vfe_bw_control_args)); + if (rc) + CAM_ERR(CAM_ISP, "BW Update failed"); + } else + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } + } + + return rc; +} + +static int cam_ife_mgr_pause_hw(struct cam_ife_hw_mgr_ctx *ctx) +{ + return cam_ife_mgr_bw_control(ctx, CAM_VFE_BW_CONTROL_EXCLUDE); +} + +/* entry function: stop_hw */ +static int cam_ife_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) +{ + int rc = 0; + struct cam_hw_stop_args *stop_args = stop_hw_args; + struct cam_isp_stop_args *stop_isp; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_ife_hw_mgr_ctx *ctx; + enum cam_ife_csid_halt_cmd csid_halt_type; + uint32_t i, master_base_idx = 0; + + if (!hw_mgr_priv || !stop_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_ife_hw_mgr_ctx *)stop_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, " Enter...ctx id:%d", ctx->ctx_index); + stop_isp = (struct cam_isp_stop_args *)stop_args->args; + + /* Set the csid halt command */ + if (stop_isp->hw_stop_cmd == CAM_ISP_HW_STOP_AT_FRAME_BOUNDARY) + csid_halt_type = CAM_CSID_HALT_AT_FRAME_BOUNDARY; + else + csid_halt_type = CAM_CSID_HALT_IMMEDIATELY; + + /* Note:stop resource will remove the irq mask from the hardware */ + + if (!ctx->num_base) { + CAM_ERR(CAM_ISP, "number of bases are zero"); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Halting CSIDs"); + + /* get master base index first */ + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].split_id == CAM_ISP_HW_SPLIT_LEFT) { + master_base_idx = ctx->base[i].idx; + break; + } + } + + /* + * If Context does not have PIX resources and has only RDI resource + * then take the first base index. + */ + if (i == ctx->num_base) + master_base_idx = ctx->base[0].idx; + CAM_DBG(CAM_ISP, "Stopping master CSID idx %d", master_base_idx); + + /* Stop the master CSID path first */ + cam_ife_mgr_csid_stop_hw(ctx, &ctx->res_list_ife_csid, + master_base_idx, csid_halt_type); + + /* stop rest of the CSID paths */ + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].idx == master_base_idx) + continue; + CAM_DBG(CAM_ISP, "Stopping CSID idx %d i %d master %d", + ctx->base[i].idx, i, master_base_idx); + + cam_ife_mgr_csid_stop_hw(ctx, &ctx->res_list_ife_csid, + ctx->base[i].idx, csid_halt_type); + } + + CAM_DBG(CAM_ISP, "Stopping master CID idx %d", master_base_idx); + + /* Stop the master CIDs first */ + cam_ife_mgr_csid_stop_hw(ctx, &ctx->res_list_ife_cid, + master_base_idx, csid_halt_type); + + /* stop rest of the CIDs */ + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].idx == master_base_idx) + continue; + CAM_DBG(CAM_ISP, "Stopping CID idx %d i %d master %d", + ctx->base[i].idx, i, master_base_idx); + cam_ife_mgr_csid_stop_hw(ctx, &ctx->res_list_ife_cid, + ctx->base[i].idx, csid_halt_type); + } + + CAM_DBG(CAM_ISP, "Going to stop IFE Out"); + + /* IFE out resources */ + for (i = 0; i < CAM_IFE_HW_OUT_RES_MAX; i++) + cam_ife_hw_mgr_stop_hw_res(&ctx->res_list_ife_out[i]); + + /* IFE bus rd resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_in_rd, list) { + cam_ife_hw_mgr_stop_hw_res(hw_mgr_res); + } + + CAM_DBG(CAM_ISP, "Going to stop IFE Mux"); + + /* IFE mux in resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + cam_ife_hw_mgr_stop_hw_res(hw_mgr_res); + } + + cam_tasklet_stop(ctx->common.tasklet_info); + + cam_ife_mgr_pause_hw(ctx); + + wait_for_completion(&ctx->config_done_complete); + + if (stop_isp->stop_only) + goto end; + + if (cam_cdm_stream_off(ctx->cdm_handle)) + CAM_ERR(CAM_ISP, "CDM stream off failed %d", ctx->cdm_handle); + + cam_ife_hw_mgr_deinit_hw(ctx); + CAM_DBG(CAM_ISP, + "Stop success for ctx id:%d rc :%d", ctx->ctx_index, rc); + + mutex_lock(&g_ife_hw_mgr.ctx_mutex); + if (!atomic_dec_return(&g_ife_hw_mgr.active_ctx_cnt)) { + rc = cam_ife_notify_safe_lut_scm(CAM_IFE_SAFE_DISABLE); + if (rc) { + CAM_ERR(CAM_ISP, + "SAFE SCM call failed:Check TZ/HYP dependency"); + rc = 0; + } + } + mutex_unlock(&g_ife_hw_mgr.ctx_mutex); + +end: + return rc; +} + +static int cam_ife_mgr_reset_vfe_hw(struct cam_ife_hw_mgr *hw_mgr, + uint32_t hw_idx) +{ + uint32_t i = 0; + struct cam_hw_intf *vfe_hw_intf; + uint32_t vfe_reset_type; + + if (!hw_mgr) { + CAM_DBG(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + /* Reset VFE HW*/ + vfe_reset_type = CAM_VFE_HW_RESET_HW; + + for (i = 0; i < CAM_VFE_HW_NUM_MAX; i++) { + if (!hw_mgr->ife_devices[i]) + continue; + + if (hw_idx != hw_mgr->ife_devices[i]->hw_idx) + continue; + CAM_DBG(CAM_ISP, "VFE (id = %d) reset", hw_idx); + vfe_hw_intf = hw_mgr->ife_devices[i]; + vfe_hw_intf->hw_ops.reset(vfe_hw_intf->hw_priv, + &vfe_reset_type, sizeof(vfe_reset_type)); + break; + } + + CAM_DBG(CAM_ISP, "Exit Successfully"); + return 0; +} + +static int cam_ife_mgr_restart_hw(void *start_hw_args) +{ + int rc = -1; + struct cam_hw_start_args *start_args = start_hw_args; + struct cam_ife_hw_mgr_ctx *ctx; + struct cam_isp_hw_mgr_res *hw_mgr_res; + uint32_t i; + + if (!start_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_ife_hw_mgr_ctx *)start_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, "START IFE OUT ... in ctx id:%d", ctx->ctx_index); + + cam_tasklet_start(ctx->common.tasklet_info); + + /* start the IFE out devices */ + for (i = 0; i < CAM_IFE_HW_OUT_RES_MAX; i++) { + rc = cam_ife_hw_mgr_start_hw_res( + &ctx->res_list_ife_out[i], ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start IFE OUT (%d)", i); + goto err; + } + } + + CAM_DBG(CAM_ISP, "START IFE SRC ... in ctx id:%d", ctx->ctx_index); + + /* Start IFE BUS RD device */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_in_rd, list) { + rc = cam_ife_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start IFE BUS RD (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + /* Start the IFE mux in devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + rc = cam_ife_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start IFE MUX (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + CAM_DBG(CAM_ISP, "START CSID HW ... in ctx id:%d", ctx->ctx_index); + /* Start the IFE CSID HW devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, list) { + rc = cam_ife_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start IFE CSID (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + CAM_DBG(CAM_ISP, "START CID SRC ... in ctx id:%d", ctx->ctx_index); + /* Start IFE root node: do nothing */ + CAM_DBG(CAM_ISP, "Exit...(success)"); + return 0; + +err: + cam_ife_mgr_stop_hw_in_overflow(start_hw_args); + CAM_DBG(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; +} + +static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) +{ + int rc = -1; + struct cam_isp_start_args *start_isp = start_hw_args; + struct cam_hw_stop_args stop_args; + struct cam_isp_stop_args stop_isp; + struct cam_ife_hw_mgr_ctx *ctx; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *rsrc_node = NULL; + uint32_t i, camif_debug; + bool res_rdi_context_set = false; + uint32_t primary_rdi_src_res; + uint32_t primary_rdi_out_res; + + primary_rdi_src_res = CAM_ISP_HW_VFE_IN_MAX; + primary_rdi_out_res = CAM_ISP_IFE_OUT_RES_MAX; + + if (!hw_mgr_priv || !start_isp) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_ife_hw_mgr_ctx *) + start_isp->hw_config.ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + if ((!ctx->init_done) && start_isp->start_only) { + CAM_ERR(CAM_ISP, "Invalid args init_done %d start_only %d", + ctx->init_done, start_isp->start_only); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Enter... ctx id:%d", + ctx->ctx_index); + + /* update Bandwidth should be done at the hw layer */ + + cam_tasklet_start(ctx->common.tasklet_info); + + if (ctx->init_done && start_isp->start_only) + goto start_only; + + /* set current csid debug information to CSID HW */ + for (i = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) { + if (g_ife_hw_mgr.csid_devices[i]) + rc = g_ife_hw_mgr.csid_devices[i]->hw_ops.process_cmd( + g_ife_hw_mgr.csid_devices[i]->hw_priv, + CAM_IFE_CSID_SET_CSID_DEBUG, + &g_ife_hw_mgr.debug_cfg.csid_debug, + sizeof(g_ife_hw_mgr.debug_cfg.csid_debug)); + } + + camif_debug = g_ife_hw_mgr.debug_cfg.camif_debug; + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + rsrc_node = hw_mgr_res->hw_res[i]; + if (rsrc_node->process_cmd && (rsrc_node->res_id == + CAM_ISP_HW_VFE_IN_CAMIF)) { + rc = hw_mgr_res->hw_res[i]->process_cmd( + hw_mgr_res->hw_res[i], + CAM_ISP_HW_CMD_SET_CAMIF_DEBUG, + &camif_debug, + sizeof(camif_debug)); + } + } + } + + rc = cam_ife_hw_mgr_init_hw(ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Init failed"); + goto tasklet_stop; + } + + ctx->init_done = true; + + mutex_lock(&g_ife_hw_mgr.ctx_mutex); + if (!atomic_fetch_inc(&g_ife_hw_mgr.active_ctx_cnt)) { + rc = cam_ife_notify_safe_lut_scm(CAM_IFE_SAFE_ENABLE); + if (rc) { + CAM_ERR(CAM_ISP, + "SAFE SCM call failed:Check TZ/HYP dependency"); + rc = -EFAULT; + goto deinit_hw; + } + } + mutex_unlock(&g_ife_hw_mgr.ctx_mutex); + + CAM_DBG(CAM_ISP, "start cdm interface"); + rc = cam_cdm_stream_on(ctx->cdm_handle); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start cdm (%d)", + ctx->cdm_handle); + goto safe_disable; + } + +start_only: + + atomic_set(&ctx->overflow_pending, 0); + + /* Apply initial configuration */ + CAM_DBG(CAM_ISP, "Config HW"); + rc = cam_ife_mgr_config_hw(hw_mgr_priv, &start_isp->hw_config); + if (rc) { + CAM_ERR(CAM_ISP, + "Config HW failed, start_only=%d, rc=%d", + start_isp->start_only, rc); + goto cdm_streamoff; + } + + CAM_DBG(CAM_ISP, "START IFE OUT ... in ctx id:%d", + ctx->ctx_index); + /* start the IFE out devices */ + for (i = 0; i < CAM_IFE_HW_OUT_RES_MAX; i++) { + hw_mgr_res = &ctx->res_list_ife_out[i]; + switch (hw_mgr_res->res_id) { + case CAM_ISP_IFE_OUT_RES_RDI_0: + case CAM_ISP_IFE_OUT_RES_RDI_1: + case CAM_ISP_IFE_OUT_RES_RDI_2: + case CAM_ISP_IFE_OUT_RES_RDI_3: + if (!res_rdi_context_set && ctx->is_rdi_only_context) { + hw_mgr_res->hw_res[0]->rdi_only_ctx = + ctx->is_rdi_only_context; + res_rdi_context_set = true; + primary_rdi_out_res = hw_mgr_res->res_id; + } + break; + default: + break; + } + rc = cam_ife_hw_mgr_start_hw_res( + &ctx->res_list_ife_out[i], ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start IFE OUT (%d)", + i); + goto err; + } + } + + CAM_DBG(CAM_ISP, "START IFE BUS RD ... in ctx id:%d", + ctx->ctx_index); + /* Start the IFE mux in devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_in_rd, list) { + rc = cam_ife_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start IFE BUS RD (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + if (primary_rdi_out_res < CAM_ISP_IFE_OUT_RES_MAX) + primary_rdi_src_res = + cam_convert_rdi_out_res_id_to_src(primary_rdi_out_res); + + CAM_DBG(CAM_ISP, "START IFE SRC ... in ctx id:%d", + ctx->ctx_index); + /* Start the IFE mux in devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + if (primary_rdi_src_res == hw_mgr_res->res_id) { + hw_mgr_res->hw_res[0]->rdi_only_ctx = + ctx->is_rdi_only_context; + } + + rc = cam_ife_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start IFE MUX (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + CAM_DBG(CAM_ISP, "START CSID HW ... in ctx id:%d", + ctx->ctx_index); + /* Start the IFE CSID HW devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, list) { + rc = cam_ife_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start IFE CSID (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + CAM_DBG(CAM_ISP, "START CID SRC ... in ctx id:%d", + ctx->ctx_index); + /* Start the IFE CID HW devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_cid, list) { + rc = cam_ife_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start IFE CSID (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + /* Start IFE root node: do nothing */ + CAM_DBG(CAM_ISP, "Start success for ctx id:%d", ctx->ctx_index); + + return 0; + +err: + stop_isp.stop_only = false; + stop_isp.hw_stop_cmd = CAM_ISP_HW_STOP_IMMEDIATELY; + stop_args.ctxt_to_hw_map = start_isp->hw_config.ctxt_to_hw_map; + stop_args.args = (void *)(&stop_isp); + + cam_ife_mgr_stop_hw(hw_mgr_priv, &stop_args); + CAM_DBG(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; + +cdm_streamoff: + cam_cdm_stream_off(ctx->cdm_handle); + +safe_disable: + cam_ife_notify_safe_lut_scm(CAM_IFE_SAFE_DISABLE); + +deinit_hw: + cam_ife_hw_mgr_deinit_hw(ctx); + +tasklet_stop: + cam_tasklet_stop(ctx->common.tasklet_info); + + return rc; +} + +static int cam_ife_mgr_read(void *hw_mgr_priv, void *read_args) +{ + return -EPERM; +} + +static int cam_ife_mgr_write(void *hw_mgr_priv, void *write_args) +{ + return -EPERM; +} + +static int cam_ife_mgr_reset(void *hw_mgr_priv, void *hw_reset_args) +{ + struct cam_ife_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_reset_args *reset_args = hw_reset_args; + struct cam_ife_hw_mgr_ctx *ctx; + struct cam_isp_hw_mgr_res *hw_mgr_res; + int rc = 0, i = 0; + + if (!hw_mgr_priv || !hw_reset_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_ife_hw_mgr_ctx *)reset_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, "Reset CSID and VFE"); + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, list) { + rc = cam_ife_hw_mgr_reset_csid_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to reset CSID:%d rc: %d", + hw_mgr_res->res_id, rc); + goto end; + } + } + + for (i = 0; i < ctx->num_base; i++) { + rc = cam_ife_mgr_reset_vfe_hw(hw_mgr, ctx->base[i].idx); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to reset VFE:%d rc: %d", + ctx->base[i].idx, rc); + goto end; + } + } + +end: + return rc; +} + +static int cam_ife_mgr_release_hw(void *hw_mgr_priv, + void *release_hw_args) +{ + int rc = 0; + struct cam_hw_release_args *release_args = release_hw_args; + struct cam_ife_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_ife_hw_mgr_ctx *ctx; + uint32_t i; + + if (!hw_mgr_priv || !release_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_ife_hw_mgr_ctx *)release_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, "Enter...ctx id:%d", + ctx->ctx_index); + + if (ctx->init_done) + cam_ife_hw_mgr_deinit_hw(ctx); + + /* we should called the stop hw before this already */ + cam_ife_hw_mgr_release_hw_for_ctx(ctx); + + /* reset base info */ + ctx->num_base = 0; + memset(ctx->base, 0, sizeof(ctx->base)); + + /* release cdm handle */ + cam_cdm_release(ctx->cdm_handle); + + /* clean context */ + list_del_init(&ctx->list); + ctx->ctx_in_use = 0; + ctx->is_rdi_only_context = 0; + ctx->cdm_handle = 0; + ctx->cdm_ops = NULL; + atomic_set(&ctx->overflow_pending, 0); + for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) { + ctx->sof_cnt[i] = 0; + ctx->eof_cnt[i] = 0; + ctx->epoch_cnt[i] = 0; + } + + CAM_INFO(CAM_ISP, "Release HW success ctx id: %u", + ctx->ctx_index); + + memset(&ctx->ts, 0, sizeof(struct timespec64)); + cam_ife_hw_mgr_put_ctx(&hw_mgr->free_ctx_list, &ctx); + return rc; +} + +static int cam_isp_blob_fe_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_fe_config *fe_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_ife_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + int rc = -EINVAL; + uint32_t i; + struct cam_vfe_fe_update_args fe_upd_args; + + ctx = prepare->ctxt_to_hw_map; + + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_in_rd, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + fe_upd_args.node_res = + hw_mgr_res->hw_res[i]; + + memcpy(&fe_upd_args.fe_config, fe_config, + sizeof(struct cam_fe_config)); + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_FE_UPDATE_BUS_RD, + &fe_upd_args, + sizeof( + struct cam_fe_config)); + if (rc) + CAM_ERR(CAM_ISP, "fs Update failed"); + } else + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } + } + + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + if (hw_mgr_res->res_id != CAM_ISP_HW_VFE_IN_RD) + continue; + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + fe_upd_args.node_res = + hw_mgr_res->hw_res[i]; + + memcpy(&fe_upd_args.fe_config, fe_config, + sizeof(struct cam_fe_config)); + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_FE_UPDATE_IN_RD, + &fe_upd_args, + sizeof( + struct cam_vfe_fe_update_args)); + if (rc) + CAM_ERR(CAM_ISP, "fe Update failed"); + } else + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } + } + return rc; +} + +static int cam_isp_blob_ubwc_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_ubwc_config *ubwc_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_ubwc_plane_cfg_v1 *ubwc_plane_cfg; + struct cam_kmd_buf_info *kmd_buf_info; + struct cam_ife_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + uint32_t res_id_out, i; + uint32_t total_used_bytes = 0; + uint32_t kmd_buf_remain_size; + uint32_t *cmd_buf_addr; + uint32_t bytes_used = 0; + int num_ent, rc = 0; + + ctx = prepare->ctxt_to_hw_map; + if (!ctx) { + CAM_ERR(CAM_ISP, "Invalid ctx"); + rc = -EINVAL; + goto end; + } + + if ((prepare->num_hw_update_entries + 1) >= + prepare->max_hw_update_entries) { + CAM_ERR(CAM_ISP, "Insufficient HW entries :%d max:%d", + prepare->num_hw_update_entries, + prepare->max_hw_update_entries); + rc = -EINVAL; + goto end; + } + + switch (ubwc_config->api_version) { + case CAM_UBWC_CFG_VERSION_1: + CAM_DBG(CAM_ISP, "num_ports= %d", ubwc_config->num_ports); + + kmd_buf_info = blob_info->kmd_buf_info; + for (i = 0; i < ubwc_config->num_ports; i++) { + ubwc_plane_cfg = &ubwc_config->ubwc_plane_cfg[i][0]; + res_id_out = ubwc_plane_cfg->port_type & 0xFF; + + CAM_DBG(CAM_ISP, "UBWC config idx %d, port_type=%d", i, + ubwc_plane_cfg->port_type); + + if (res_id_out >= CAM_IFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "Invalid port type:%x", + ubwc_plane_cfg->port_type); + rc = -EINVAL; + goto end; + } + + if ((kmd_buf_info->used_bytes + + total_used_bytes) < kmd_buf_info->size) { + kmd_buf_remain_size = kmd_buf_info->size - + (kmd_buf_info->used_bytes + + total_used_bytes); + } else { + CAM_ERR(CAM_ISP, + "no free kmd memory for base=%d bytes_used=%u buf_size=%u", + blob_info->base_info->idx, bytes_used, + kmd_buf_info->size); + rc = -ENOMEM; + goto end; + } + + cmd_buf_addr = kmd_buf_info->cpu_addr + + kmd_buf_info->used_bytes/4 + + total_used_bytes/4; + hw_mgr_res = &ctx->res_list_ife_out[res_id_out]; + + if (!hw_mgr_res) { + CAM_ERR(CAM_ISP, "Invalid hw_mgr_res"); + rc = -EINVAL; + goto end; + } + + rc = cam_isp_add_cmd_buf_update( + hw_mgr_res, blob_type, + blob_type_hw_cmd_map[blob_type], + blob_info->base_info->idx, + (void *)cmd_buf_addr, + kmd_buf_remain_size, + (void *)ubwc_plane_cfg, + &bytes_used); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Failed cmd_update, base_idx=%d, bytes_used=%u, res_id_out=0x%x", + blob_info->base_info->idx, + bytes_used, + res_id_out); + goto end; + } + + total_used_bytes += bytes_used; + } + + if (total_used_bytes) { + /* Update the HW entries */ + num_ent = prepare->num_hw_update_entries; + prepare->hw_update_entries[num_ent].handle = + kmd_buf_info->handle; + prepare->hw_update_entries[num_ent].len = + total_used_bytes; + prepare->hw_update_entries[num_ent].offset = + kmd_buf_info->offset; + num_ent++; + + kmd_buf_info->used_bytes += total_used_bytes; + kmd_buf_info->offset += total_used_bytes; + prepare->num_hw_update_entries = num_ent; + } + break; + default: + CAM_ERR(CAM_ISP, "Invalid UBWC API Version %d", + ubwc_config->api_version); + rc = -EINVAL; + break; + } +end: + return rc; +} + +static int cam_isp_get_generic_ubwc_data_v2( + struct cam_ubwc_plane_cfg_v2 *ubwc_cfg, + uint32_t version, + struct cam_vfe_generic_ubwc_config *generic_ubwc_cfg) +{ + int i = 0; + + generic_ubwc_cfg->api_version = version; + for (i = 0; i < CAM_PACKET_MAX_PLANES - 1; i++) { + generic_ubwc_cfg->ubwc_plane_cfg[i].port_type = + ubwc_cfg[i].port_type; + generic_ubwc_cfg->ubwc_plane_cfg[i].meta_stride = + ubwc_cfg[i].meta_stride; + generic_ubwc_cfg->ubwc_plane_cfg[i].meta_size = + ubwc_cfg[i].meta_size; + generic_ubwc_cfg->ubwc_plane_cfg[i].meta_offset = + ubwc_cfg[i].meta_offset; + generic_ubwc_cfg->ubwc_plane_cfg[i].packer_config = + ubwc_cfg[i].packer_config; + generic_ubwc_cfg->ubwc_plane_cfg[i].mode_config_0 = + ubwc_cfg[i].mode_config_0; + generic_ubwc_cfg->ubwc_plane_cfg[i].mode_config_1 = + ubwc_cfg[i].mode_config_1; + generic_ubwc_cfg->ubwc_plane_cfg[i].tile_config = + ubwc_cfg[i].tile_config; + generic_ubwc_cfg->ubwc_plane_cfg[i].h_init = + ubwc_cfg[i].h_init; + generic_ubwc_cfg->ubwc_plane_cfg[i].v_init = + ubwc_cfg[i].v_init; + generic_ubwc_cfg->ubwc_plane_cfg[i].static_ctrl = + ubwc_cfg[i].static_ctrl; + generic_ubwc_cfg->ubwc_plane_cfg[i].ctrl_2 = + ubwc_cfg[i].ctrl_2; + generic_ubwc_cfg->ubwc_plane_cfg[i].stats_ctrl_2 = + ubwc_cfg[i].stats_ctrl_2; + generic_ubwc_cfg->ubwc_plane_cfg[i].lossy_threshold_0 = + ubwc_cfg[i].lossy_threshold_0; + generic_ubwc_cfg->ubwc_plane_cfg[i].lossy_threshold_1 = + ubwc_cfg[i].lossy_threshold_1; + generic_ubwc_cfg->ubwc_plane_cfg[i].lossy_var_offset = + ubwc_cfg[i].lossy_var_offset; + generic_ubwc_cfg->ubwc_plane_cfg[i].bandwidth_limit = + ubwc_cfg[i].bandwidth_limit; + } + + return 0; +} + +static int cam_isp_blob_ubwc_update_v2( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_ubwc_config_v2 *ubwc_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_ubwc_plane_cfg_v2 *ubwc_plane_cfg; + struct cam_kmd_buf_info *kmd_buf_info; + struct cam_ife_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + uint32_t res_id_out, i; + uint32_t total_used_bytes = 0; + uint32_t kmd_buf_remain_size; + uint32_t *cmd_buf_addr; + uint32_t bytes_used = 0; + int num_ent, rc = 0; + struct cam_vfe_generic_ubwc_config generic_ubwc_cfg; + + ctx = prepare->ctxt_to_hw_map; + if (!ctx) { + CAM_ERR(CAM_ISP, "Invalid ctx"); + rc = -EINVAL; + goto end; + } + + if (prepare->num_hw_update_entries + 1 >= + prepare->max_hw_update_entries) { + CAM_ERR(CAM_ISP, "Insufficient HW entries :%d max:%d", + prepare->num_hw_update_entries, + prepare->max_hw_update_entries); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ISP, "num_ports= %d", ubwc_config->num_ports); + + kmd_buf_info = blob_info->kmd_buf_info; + for (i = 0; i < ubwc_config->num_ports; i++) { + ubwc_plane_cfg = &ubwc_config->ubwc_plane_cfg[i][0]; + res_id_out = ubwc_plane_cfg->port_type & 0xFF; + + CAM_DBG(CAM_ISP, "UBWC config idx %d, port_type=%d", i, + ubwc_plane_cfg->port_type); + + if (res_id_out >= CAM_IFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "Invalid port type:%x", + ubwc_plane_cfg->port_type); + rc = -EINVAL; + goto end; + } + + if ((kmd_buf_info->used_bytes + + total_used_bytes) < kmd_buf_info->size) { + kmd_buf_remain_size = kmd_buf_info->size - + (kmd_buf_info->used_bytes + + total_used_bytes); + } else { + CAM_ERR(CAM_ISP, + "no free kmd memory for base=%d bytes_used=%u buf_size=%u", + blob_info->base_info->idx, bytes_used, + kmd_buf_info->size); + rc = -ENOMEM; + goto end; + } + + cmd_buf_addr = kmd_buf_info->cpu_addr + + kmd_buf_info->used_bytes/4 + + total_used_bytes/4; + hw_mgr_res = &ctx->res_list_ife_out[res_id_out]; + + if (!hw_mgr_res) { + CAM_ERR(CAM_ISP, "Invalid hw_mgr_res"); + rc = -EINVAL; + goto end; + } + + rc = cam_isp_get_generic_ubwc_data_v2(ubwc_plane_cfg, + ubwc_config->api_version, &generic_ubwc_cfg); + + rc = cam_isp_add_cmd_buf_update( + hw_mgr_res, blob_type, + blob_type_hw_cmd_map[blob_type], + blob_info->base_info->idx, + (void *)cmd_buf_addr, + kmd_buf_remain_size, + (void *)&generic_ubwc_cfg, + &bytes_used); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Failed cmd_update, base_idx=%d, bytes_used=%u, res_id_out=0x%x", + blob_info->base_info->idx, + bytes_used, + res_id_out); + goto end; + } + + total_used_bytes += bytes_used; + } + + if (total_used_bytes) { + /* Update the HW entries */ + num_ent = prepare->num_hw_update_entries; + prepare->hw_update_entries[num_ent].handle = + kmd_buf_info->handle; + prepare->hw_update_entries[num_ent].len = + total_used_bytes; + prepare->hw_update_entries[num_ent].offset = + kmd_buf_info->offset; + num_ent++; + + kmd_buf_info->used_bytes += total_used_bytes; + kmd_buf_info->offset += total_used_bytes; + prepare->num_hw_update_entries = num_ent; + } +end: + return rc; +} + +static int cam_isp_blob_hfr_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_resource_hfr_config *hfr_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_isp_port_hfr_config *port_hfr_config; + struct cam_kmd_buf_info *kmd_buf_info; + struct cam_ife_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + uint32_t res_id_out, i; + uint32_t total_used_bytes = 0; + uint32_t kmd_buf_remain_size; + uint32_t *cmd_buf_addr; + uint32_t bytes_used = 0; + int num_ent, rc = 0; + + ctx = prepare->ctxt_to_hw_map; + CAM_DBG(CAM_ISP, "num_ports= %d", + hfr_config->num_ports); + + /* Max one hw entries required for hfr config update */ + if (prepare->num_hw_update_entries + 1 >= + prepare->max_hw_update_entries) { + CAM_ERR(CAM_ISP, "Insufficient HW entries :%d %d", + prepare->num_hw_update_entries, + prepare->max_hw_update_entries); + return -EINVAL; + } + + kmd_buf_info = blob_info->kmd_buf_info; + for (i = 0; i < hfr_config->num_ports; i++) { + port_hfr_config = &hfr_config->port_hfr_config[i]; + res_id_out = port_hfr_config->resource_type & 0xFF; + + CAM_DBG(CAM_ISP, "hfr config idx %d, type=%d", i, + res_id_out); + + if (res_id_out >= CAM_IFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "invalid out restype:%x", + port_hfr_config->resource_type); + return -EINVAL; + } + + if ((kmd_buf_info->used_bytes + + total_used_bytes) < kmd_buf_info->size) { + kmd_buf_remain_size = kmd_buf_info->size - + (kmd_buf_info->used_bytes + + total_used_bytes); + } else { + CAM_ERR(CAM_ISP, + "no free kmd memory for base %d", + blob_info->base_info->idx); + rc = -ENOMEM; + return rc; + } + + cmd_buf_addr = kmd_buf_info->cpu_addr + + kmd_buf_info->used_bytes/4 + + total_used_bytes/4; + hw_mgr_res = &ctx->res_list_ife_out[res_id_out]; + + rc = cam_isp_add_cmd_buf_update( + hw_mgr_res, blob_type, + blob_type_hw_cmd_map[blob_type], + blob_info->base_info->idx, + (void *)cmd_buf_addr, + kmd_buf_remain_size, + (void *)port_hfr_config, + &bytes_used); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Failed cmd_update, base_idx=%d, rc=%d", + blob_info->base_info->idx, bytes_used); + return rc; + } + + total_used_bytes += bytes_used; + } + + if (total_used_bytes) { + /* Update the HW entries */ + num_ent = prepare->num_hw_update_entries; + prepare->hw_update_entries[num_ent].handle = + kmd_buf_info->handle; + prepare->hw_update_entries[num_ent].len = total_used_bytes; + prepare->hw_update_entries[num_ent].offset = + kmd_buf_info->offset; + num_ent++; + + kmd_buf_info->used_bytes += total_used_bytes; + kmd_buf_info->offset += total_used_bytes; + prepare->num_hw_update_entries = num_ent; + } + + return rc; +} + +static int cam_isp_blob_csid_clock_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_csid_clock_config *clock_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_ife_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_ife_csid_clock_update_args csid_clock_upd_args; + uint64_t clk_rate = 0; + int rc = -EINVAL; + uint32_t i; + + ctx = prepare->ctxt_to_hw_map; + + CAM_DBG(CAM_ISP, + "csid clk=%llu", clock_config->csid_clock); + + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + clk_rate = 0; + if (!hw_mgr_res->hw_res[i]) + continue; + clk_rate = clock_config->csid_clock; + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + csid_clock_upd_args.clk_rate = clk_rate; + CAM_DBG(CAM_ISP, "i= %d clk=%llu\n", + i, csid_clock_upd_args.clk_rate); + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + blob_type_hw_cmd_map[blob_type], + &csid_clock_upd_args, + sizeof( + struct cam_ife_csid_clock_update_args)); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update failed"); + } else + CAM_ERR(CAM_ISP, "NULL hw_intf!"); + } + } + + return rc; +} + +static int cam_isp_blob_csid_qcfa_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_csid_qcfa_config *qcfa_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_ife_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_ife_csid_qcfa_update_args csid_qcfa_upd_args; + int rc = -EINVAL; + uint32_t i; + + ctx = prepare->ctxt_to_hw_map; + + CAM_DBG(CAM_ISP, + "csid binning=%d", qcfa_config->csid_binning); + + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + + if (!hw_mgr_res->hw_res[i] || + hw_mgr_res->res_id != CAM_IFE_PIX_PATH_RES_IPP) + continue; + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + csid_qcfa_upd_args.qcfa_binning = + qcfa_config->csid_binning; + CAM_DBG(CAM_ISP, "i= %d QCFA binning=%d\n", + i, csid_qcfa_upd_args.qcfa_binning); + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_CSID_QCFA_SUPPORTED, + &csid_qcfa_upd_args, + sizeof( + struct cam_ife_csid_qcfa_update_args)); + if (rc) + CAM_ERR(CAM_ISP, "QCFA Update failed"); + } else + CAM_ERR(CAM_ISP, "NULL hw_intf!"); + } + } + + return rc; +} + +static int cam_isp_blob_core_cfg_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_core_config *core_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_ife_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + uint64_t clk_rate = 0; + int rc = 0, i; + struct cam_vfe_core_config_args vfe_core_config; + + ctx = prepare->ctxt_to_hw_map; + + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + clk_rate = 0; + if (!hw_mgr_res->hw_res[i]) + continue; + + if ((hw_mgr_res->res_id == + CAM_ISP_HW_VFE_IN_CAMIF) || + (hw_mgr_res->res_id == + CAM_ISP_HW_VFE_IN_PDLIB)) { + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + vfe_core_config.node_res = + hw_mgr_res->hw_res[i]; + + memcpy(&vfe_core_config.core_config, + core_config, + sizeof( + struct cam_isp_core_config)); + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_CORE_CONFIG, + &vfe_core_config, + sizeof( + struct cam_vfe_core_config_args) + ); + if (rc) + CAM_ERR(CAM_ISP, + "Core cfg parse fail"); + } else { + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } + } + } + } + + return rc; +} + +static int cam_isp_blob_clock_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_clock_config *clock_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_ife_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_vfe_clock_update_args clock_upd_args; + uint64_t clk_rate = 0; + int rc = -EINVAL; + uint32_t i; + uint32_t j; + bool camif_l_clk_updated = false; + bool camif_r_clk_updated = false; + + ctx = prepare->ctxt_to_hw_map; + + CAM_DBG(CAM_PERF, + "usage=%u left_clk= %lu right_clk=%lu", + clock_config->usage_type, + clock_config->left_pix_hz, + clock_config->right_pix_hz); + + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + clk_rate = 0; + if (!hw_mgr_res->hw_res[i]) + continue; + + if (hw_mgr_res->res_id == CAM_ISP_HW_VFE_IN_CAMIF) { + if (i == CAM_ISP_HW_SPLIT_LEFT) { + if (camif_l_clk_updated) + continue; + + clk_rate = + clock_config->left_pix_hz; + + camif_l_clk_updated = true; + } else { + if (camif_r_clk_updated) + continue; + + clk_rate = + clock_config->right_pix_hz; + + camif_r_clk_updated = true; + } + } else if (hw_mgr_res->res_id == + CAM_ISP_HW_VFE_IN_PDLIB) { + if (i == CAM_ISP_HW_SPLIT_LEFT) { + if (camif_l_clk_updated) + continue; + + clk_rate = + clock_config->left_pix_hz; + + camif_l_clk_updated = true; + } else { + if (camif_r_clk_updated) + continue; + + clk_rate = + clock_config->right_pix_hz; + + camif_r_clk_updated = true; + } + } else if ((hw_mgr_res->res_id >= + CAM_ISP_HW_VFE_IN_RD) && (hw_mgr_res->res_id + <= CAM_ISP_HW_VFE_IN_RDI3)) + for (j = 0; j < clock_config->num_rdi; j++) + clk_rate = max(clock_config->rdi_hz[j], + clk_rate); + else + if (hw_mgr_res->res_id != CAM_ISP_HW_VFE_IN_LCR + && hw_mgr_res->hw_res[i]) { + CAM_ERR(CAM_ISP, "Invalid res_id %u", + hw_mgr_res->res_id); + rc = -EINVAL; + return rc; + } + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + clock_upd_args.node_res = + hw_mgr_res->hw_res[i]; + CAM_DBG(CAM_PERF, + "res_id=%u i= %d clk=%llu\n", + hw_mgr_res->res_id, i, clk_rate); + + clock_upd_args.clk_rate = clk_rate; + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_CLOCK_UPDATE, + &clock_upd_args, + sizeof( + struct cam_vfe_clock_update_args)); + if (rc) + CAM_ERR(CAM_PERF, + "Clock Update failed"); + } else + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } + } + + return rc; +} + +static int cam_isp_blob_vfe_out_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_vfe_out_config *vfe_out_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_isp_vfe_wm_config *wm_config; + struct cam_kmd_buf_info *kmd_buf_info; + struct cam_ife_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *ife_out_res; + uint32_t res_id_out, i; + uint32_t total_used_bytes = 0; + uint32_t kmd_buf_remain_size; + uint32_t *cmd_buf_addr; + uint32_t bytes_used = 0; + int num_ent, rc = 0; + + ctx = prepare->ctxt_to_hw_map; + + if (prepare->num_hw_update_entries + 1 >= + prepare->max_hw_update_entries) { + CAM_ERR(CAM_ISP, "Insufficient HW entries :%d %d", + prepare->num_hw_update_entries, + prepare->max_hw_update_entries); + return -EINVAL; + } + + kmd_buf_info = blob_info->kmd_buf_info; + for (i = 0; i < vfe_out_config->num_ports; i++) { + wm_config = &vfe_out_config->wm_config[i]; + res_id_out = wm_config->port_type & 0xFF; + + CAM_DBG(CAM_ISP, "VFE out config idx: %d port: 0x%x", + i, wm_config->port_type); + + if (res_id_out >= CAM_IFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "Invalid out port:0x%x", + wm_config->port_type); + return -EINVAL; + } + + if ((kmd_buf_info->used_bytes + + total_used_bytes) < kmd_buf_info->size) { + kmd_buf_remain_size = kmd_buf_info->size - + (kmd_buf_info->used_bytes + + total_used_bytes); + } else { + CAM_ERR(CAM_ISP, + "No free kmd memory for base idx: %d", + blob_info->base_info->idx); + rc = -ENOMEM; + return rc; + } + + cmd_buf_addr = kmd_buf_info->cpu_addr + + (kmd_buf_info->used_bytes / 4) + + (total_used_bytes / 4); + ife_out_res = &ctx->res_list_ife_out[res_id_out]; + + rc = cam_isp_add_cmd_buf_update( + ife_out_res, blob_type, + blob_type_hw_cmd_map[blob_type], + blob_info->base_info->idx, + (void *)cmd_buf_addr, + kmd_buf_remain_size, + (void *)wm_config, + &bytes_used); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Failed to update VFE Out out_type:0x%X base_idx:%d bytes_used:%u rc:%d", + wm_config->port_type, blob_info->base_info->idx, + bytes_used, rc); + return rc; + } + + total_used_bytes += bytes_used; + } + + if (total_used_bytes) { + num_ent = prepare->num_hw_update_entries; + prepare->hw_update_entries[num_ent].handle = + kmd_buf_info->handle; + prepare->hw_update_entries[num_ent].len = total_used_bytes; + prepare->hw_update_entries[num_ent].offset = + kmd_buf_info->offset; + num_ent++; + + kmd_buf_info->used_bytes += total_used_bytes; + kmd_buf_info->offset += total_used_bytes; + prepare->num_hw_update_entries = num_ent; + } + + return rc; +} + +static int cam_isp_packet_generic_blob_handler(void *user_data, + uint32_t blob_type, uint32_t blob_size, uint8_t *blob_data) +{ + int rc = 0; + struct cam_isp_generic_blob_info *blob_info = user_data; + struct cam_hw_prepare_update_args *prepare = NULL; + struct cam_ife_hw_mgr_ctx *ife_mgr_ctx = NULL; + + if (!blob_data || (blob_size == 0) || !blob_info) { + CAM_ERR(CAM_ISP, "Invalid args data %pK size %d info %pK", + blob_data, blob_size, blob_info); + return -EINVAL; + } + + if (blob_type >= CAM_ISP_GENERIC_BLOB_TYPE_MAX) { + CAM_ERR(CAM_ISP, "Invalid Blob Type %d Max %d", blob_type, + CAM_ISP_GENERIC_BLOB_TYPE_MAX); + return -EINVAL; + } + + prepare = blob_info->prepare; + if (!prepare || !prepare->ctxt_to_hw_map) { + CAM_ERR(CAM_ISP, "Failed. prepare is NULL, blob_type %d", + blob_type); + return -EINVAL; + } + + ife_mgr_ctx = prepare->ctxt_to_hw_map; + CAM_DBG(CAM_ISP, "Context[%pK][%d] blob_type=%d, blob_size=%d", + ife_mgr_ctx, ife_mgr_ctx->ctx_index, blob_type, blob_size); + + switch (blob_type) { + case CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG: { + struct cam_isp_resource_hfr_config *hfr_config; + + if (blob_size < sizeof(struct cam_isp_resource_hfr_config)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u", blob_size); + return -EINVAL; + } + + hfr_config = (struct cam_isp_resource_hfr_config *)blob_data; + + if (hfr_config->num_ports > CAM_ISP_IFE_OUT_RES_MAX || + hfr_config->num_ports == 0) { + CAM_ERR(CAM_ISP, "Invalid num_ports %u in HFR config", + hfr_config->num_ports); + return -EINVAL; + } + + /* Check for integer overflow */ + if (hfr_config->num_ports != 1) { + if (sizeof(struct cam_isp_port_hfr_config) > + ((UINT_MAX - + sizeof(struct cam_isp_resource_hfr_config)) / + (hfr_config->num_ports - 1))) { + CAM_ERR(CAM_ISP, + "Max size exceeded in hfr config num_ports:%u size per port:%lu", + hfr_config->num_ports, + sizeof(struct cam_isp_port_hfr_config)); + return -EINVAL; + } + } + + if (blob_size < (sizeof(struct cam_isp_resource_hfr_config) + + (hfr_config->num_ports - 1) * + sizeof(struct cam_isp_port_hfr_config))) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, + sizeof(struct cam_isp_resource_hfr_config) + + (hfr_config->num_ports - 1) * + sizeof(struct cam_isp_port_hfr_config)); + return -EINVAL; + } + + rc = cam_isp_blob_hfr_update(blob_type, blob_info, + hfr_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "HFR Update Failed"); + } + break; + case CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG: { + struct cam_isp_clock_config *clock_config; + + if (blob_size < sizeof(struct cam_isp_clock_config)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u", blob_size); + return -EINVAL; + } + + clock_config = (struct cam_isp_clock_config *)blob_data; + + if (clock_config->num_rdi > CAM_IFE_RDI_NUM_MAX) { + CAM_ERR(CAM_ISP, "Invalid num_rdi %u in clock config", + clock_config->num_rdi); + return -EINVAL; + } + + /* Check for integer overflow */ + if (clock_config->num_rdi > 1) { + if (sizeof(uint64_t) > ((UINT_MAX - + sizeof(struct cam_isp_clock_config)) / + (clock_config->num_rdi - 1))) { + CAM_ERR(CAM_ISP, + "Max size exceeded in clock config num_rdi:%u size per port:%lu", + clock_config->num_rdi, + sizeof(uint64_t)); + return -EINVAL; + } + } + + if ((clock_config->num_rdi != 0) && (blob_size < + (sizeof(struct cam_isp_clock_config) + + sizeof(uint64_t) * (clock_config->num_rdi - 1)))) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, + sizeof(uint32_t) * 2 + sizeof(uint64_t) * + (clock_config->num_rdi + 2)); + return -EINVAL; + } + + rc = cam_isp_blob_clock_update(blob_type, blob_info, + clock_config, prepare); + if (rc) + CAM_ERR(CAM_PERF, "Clock Update Failed, rc=%d", rc); + } + break; + case CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG: { + struct cam_isp_bw_config *bw_config; + struct cam_isp_prepare_hw_update_data *prepare_hw_data; + + CAM_WARN_RATE_LIMIT_CUSTOM(CAM_PERF, 300, 1, + "Deprecated Blob TYPE_BW_CONFIG"); + if (blob_size < sizeof(struct cam_isp_bw_config)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u", blob_size); + return -EINVAL; + } + + bw_config = (struct cam_isp_bw_config *)blob_data; + + if (bw_config->num_rdi > CAM_IFE_RDI_NUM_MAX) { + CAM_ERR(CAM_ISP, "Invalid num_rdi %u in bw config", + bw_config->num_rdi); + return -EINVAL; + } + + /* Check for integer overflow */ + if (bw_config->num_rdi > 1) { + if (sizeof(struct cam_isp_bw_vote) > ((UINT_MAX - + sizeof(struct cam_isp_bw_config)) / + (bw_config->num_rdi - 1))) { + CAM_ERR(CAM_ISP, + "Max size exceeded in bw config num_rdi:%u size per port:%lu", + bw_config->num_rdi, + sizeof(struct cam_isp_bw_vote)); + return -EINVAL; + } + } + + if ((bw_config->num_rdi != 0) && (blob_size < + (sizeof(struct cam_isp_bw_config) + + (bw_config->num_rdi - 1) * + sizeof(struct cam_isp_bw_vote)))) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, sizeof(struct cam_isp_bw_config) + + (bw_config->num_rdi - 1) * + sizeof(struct cam_isp_bw_vote)); + return -EINVAL; + } + + if (!prepare || !prepare->priv || + (bw_config->usage_type >= CAM_IFE_HW_NUM_MAX)) { + CAM_ERR(CAM_ISP, "Invalid inputs"); + return -EINVAL; + } + + prepare_hw_data = (struct cam_isp_prepare_hw_update_data *) + prepare->priv; + + memcpy(&prepare_hw_data->bw_config[bw_config->usage_type], + bw_config, sizeof(prepare_hw_data->bw_config[0])); + prepare_hw_data->bw_config_version = CAM_ISP_BW_CONFIG_V1; + prepare_hw_data->bw_config_valid[bw_config->usage_type] = true; + } + break; + case CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG_V2: { + size_t bw_config_size = 0; + struct cam_isp_bw_config_v2 *bw_config; + struct cam_isp_prepare_hw_update_data *prepare_hw_data; + + if (blob_size < sizeof(struct cam_isp_bw_config_v2)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u", blob_size); + return -EINVAL; + } + + bw_config = (struct cam_isp_bw_config_v2 *)blob_data; + + if (bw_config->num_paths > CAM_ISP_MAX_PER_PATH_VOTES) { + CAM_ERR(CAM_ISP, "Invalid num paths %d", + bw_config->num_paths); + return -EINVAL; + } + + /* Check for integer overflow */ + if (bw_config->num_paths > 1) { + if (sizeof(struct cam_axi_per_path_bw_vote) > + ((UINT_MAX - + sizeof(struct cam_isp_bw_config_v2)) / + (bw_config->num_paths - 1))) { + CAM_ERR(CAM_ISP, + "Size exceeds limit paths:%u size per path:%lu", + bw_config->num_paths - 1, + sizeof( + struct cam_axi_per_path_bw_vote)); + return -EINVAL; + } + } + + if ((bw_config->num_paths != 0) && (blob_size < + (sizeof(struct cam_isp_bw_config_v2) + + (bw_config->num_paths - 1) * + sizeof(struct cam_axi_per_path_bw_vote)))) { + CAM_ERR(CAM_ISP, + "Invalid blob size: %u, num_paths: %u, bw_config size: %lu, per_path_vote size: %lu", + blob_size, bw_config->num_paths, + sizeof(struct cam_isp_bw_config_v2), + sizeof(struct cam_axi_per_path_bw_vote)); + return -EINVAL; + } + + if (!prepare || !prepare->priv || + (bw_config->usage_type >= CAM_IFE_HW_NUM_MAX)) { + CAM_ERR(CAM_ISP, "Invalid inputs"); + return -EINVAL; + } + + prepare_hw_data = (struct cam_isp_prepare_hw_update_data *) + prepare->priv; + + memset(&prepare_hw_data->bw_config_v2[bw_config->usage_type], + 0, sizeof( + prepare_hw_data->bw_config_v2[bw_config->usage_type])); + bw_config_size = sizeof(struct cam_isp_bw_config_v2) + + ((bw_config->num_paths - 1) * + sizeof(struct cam_axi_per_path_bw_vote)); + memcpy(&prepare_hw_data->bw_config_v2[bw_config->usage_type], + bw_config, bw_config_size); + + prepare_hw_data->bw_config_version = CAM_ISP_BW_CONFIG_V2; + prepare_hw_data->bw_config_valid[bw_config->usage_type] = true; + } + break; + case CAM_ISP_GENERIC_BLOB_TYPE_UBWC_CONFIG: { + struct cam_ubwc_config *ubwc_config; + + if (blob_size < sizeof(struct cam_ubwc_config)) { + CAM_ERR(CAM_ISP, "Invalid blob_size %u", blob_size); + return -EINVAL; + } + + ubwc_config = (struct cam_ubwc_config *)blob_data; + + if (ubwc_config->num_ports > CAM_VFE_MAX_UBWC_PORTS || + ubwc_config->num_ports == 0) { + CAM_ERR(CAM_ISP, "Invalid num_ports %u in ubwc config", + ubwc_config->num_ports); + return -EINVAL; + } + + /* Check for integer overflow */ + if (ubwc_config->num_ports != 1) { + if (sizeof(struct cam_ubwc_plane_cfg_v1) > + ((UINT_MAX - sizeof(struct cam_ubwc_config)) / + ((ubwc_config->num_ports - 1) * 2))) { + CAM_ERR(CAM_ISP, + "Max size exceeded in ubwc config num_ports:%u size per port:%lu", + ubwc_config->num_ports, + sizeof(struct cam_ubwc_plane_cfg_v1) * + 2); + return -EINVAL; + } + } + + if (blob_size < (sizeof(struct cam_ubwc_config) + + (ubwc_config->num_ports - 1) * + sizeof(struct cam_ubwc_plane_cfg_v1) * 2)) { + CAM_ERR(CAM_ISP, "Invalid blob_size %u expected %lu", + blob_size, + sizeof(struct cam_ubwc_config) + + (ubwc_config->num_ports - 1) * + sizeof(struct cam_ubwc_plane_cfg_v1) * 2); + return -EINVAL; + } + + rc = cam_isp_blob_ubwc_update(blob_type, blob_info, + ubwc_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "UBWC Update Failed rc: %d", rc); + } + break; + + case CAM_ISP_GENERIC_BLOB_TYPE_UBWC_CONFIG_V2: { + struct cam_ubwc_config_v2 *ubwc_config; + + if (blob_size < sizeof(struct cam_ubwc_config_v2)) { + CAM_ERR(CAM_ISP, "Invalid blob_size %u", blob_size); + return -EINVAL; + } + + ubwc_config = (struct cam_ubwc_config_v2 *)blob_data; + + if (ubwc_config->num_ports > CAM_VFE_MAX_UBWC_PORTS || + ubwc_config->num_ports == 0) { + CAM_ERR(CAM_ISP, "Invalid num_ports %u in ubwc config", + ubwc_config->num_ports); + return -EINVAL; + } + + /* Check for integer overflow */ + if (ubwc_config->num_ports != 1) { + if (sizeof(struct cam_ubwc_plane_cfg_v2) > + ((UINT_MAX - sizeof(struct cam_ubwc_config_v2)) + / ((ubwc_config->num_ports - 1) * 2))) { + CAM_ERR(CAM_ISP, + "Max size exceeded in ubwc config num_ports:%u size per port:%lu", + ubwc_config->num_ports, + sizeof(struct cam_ubwc_plane_cfg_v2) * + 2); + return -EINVAL; + } + } + + if (blob_size < (sizeof(struct cam_ubwc_config_v2) + + (ubwc_config->num_ports - 1) * + sizeof(struct cam_ubwc_plane_cfg_v2) * 2)) { + CAM_ERR(CAM_ISP, "Invalid blob_size %u expected %lu", + blob_size, + sizeof(struct cam_ubwc_config_v2) + + (ubwc_config->num_ports - 1) * + sizeof(struct cam_ubwc_plane_cfg_v2) * 2); + return -EINVAL; + } + + rc = cam_isp_blob_ubwc_update_v2(blob_type, blob_info, + ubwc_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "UBWC Update Failed rc: %d", rc); + } + break; + case CAM_ISP_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG: { + struct cam_isp_csid_clock_config *clock_config; + + if (blob_size < sizeof(struct cam_isp_csid_clock_config)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, + sizeof(struct cam_isp_csid_clock_config)); + return -EINVAL; + } + + clock_config = (struct cam_isp_csid_clock_config *)blob_data; + + rc = cam_isp_blob_csid_clock_update(blob_type, blob_info, + clock_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update Failed"); + } + break; + case CAM_ISP_GENERIC_BLOB_TYPE_CSID_QCFA_CONFIG: { + struct cam_isp_csid_qcfa_config *qcfa_config; + + if (blob_size < sizeof(struct cam_isp_csid_qcfa_config)) { + CAM_ERR(CAM_ISP, + "Invalid qcfa blob size %u expected %u", + blob_size, + sizeof(struct cam_isp_csid_qcfa_config)); + return -EINVAL; + } + + qcfa_config = (struct cam_isp_csid_qcfa_config *)blob_data; + + rc = cam_isp_blob_csid_qcfa_update(blob_type, blob_info, + qcfa_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "QCFA Update Failed rc: %d", rc); + + } + break; + case CAM_ISP_GENERIC_BLOB_TYPE_FE_CONFIG: { + struct cam_fe_config *fe_config; + + if (blob_size < sizeof(struct cam_fe_config)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, sizeof(struct cam_fe_config)); + return -EINVAL; + } + + fe_config = (struct cam_fe_config *)blob_data; + + rc = cam_isp_blob_fe_update(blob_type, blob_info, + fe_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "FS Update Failed rc: %d", rc); + } + break; + case CAM_ISP_GENERIC_BLOB_TYPE_IFE_CORE_CONFIG: { + struct cam_isp_core_config *core_config; + + if (blob_size < sizeof(struct cam_isp_core_config)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, sizeof(struct cam_isp_core_config)); + return -EINVAL; + } + + core_config = (struct cam_isp_core_config *)blob_data; + + rc = cam_isp_blob_core_cfg_update(blob_type, blob_info, + core_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "Core cfg update fail: %d", rc); + } + break; + case CAM_ISP_GENERIC_BLOB_TYPE_VFE_OUT_CONFIG: { + struct cam_isp_vfe_out_config *vfe_out_config; + + if (blob_size < sizeof(struct cam_isp_vfe_out_config)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u", + blob_size, + sizeof(struct cam_isp_vfe_out_config)); + return -EINVAL; + } + + vfe_out_config = (struct cam_isp_vfe_out_config *)blob_data; + + if (vfe_out_config->num_ports > CAM_IFE_HW_OUT_RES_MAX || + vfe_out_config->num_ports == 0) { + CAM_ERR(CAM_ISP, + "Invalid num_ports:%u in vfe out config", + vfe_out_config->num_ports, + CAM_IFE_HW_OUT_RES_MAX); + return -EINVAL; + } + + /* Check for integer overflow */ + if (vfe_out_config->num_ports != 1) { + if (sizeof(struct cam_isp_vfe_wm_config) > ((UINT_MAX - + sizeof(struct cam_isp_vfe_out_config)) / + (vfe_out_config->num_ports - 1))) { + CAM_ERR(CAM_ISP, + "Max size exceeded in vfe out config num_ports:%u size per port:%lu", + vfe_out_config->num_ports, + sizeof(struct cam_isp_vfe_wm_config)); + return -EINVAL; + } + } + + if (blob_size < (sizeof(struct cam_isp_vfe_out_config) + + (vfe_out_config->num_ports - 1) * + sizeof(struct cam_isp_vfe_wm_config))) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, sizeof(struct cam_isp_vfe_out_config) + + (vfe_out_config->num_ports - 1) * + sizeof(struct cam_isp_vfe_wm_config)); + return -EINVAL; + } + + rc = cam_isp_blob_vfe_out_update(blob_type, blob_info, + vfe_out_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "VFE out update failed rc: %d", rc); + } + break; + + default: + CAM_WARN(CAM_ISP, "Invalid blob type %d", blob_type); + break; + } + + return rc; +} + +static int cam_ife_mgr_prepare_hw_update(void *hw_mgr_priv, + void *prepare_hw_update_args) +{ + int rc = 0; + struct cam_hw_prepare_update_args *prepare = + (struct cam_hw_prepare_update_args *) prepare_hw_update_args; + struct cam_ife_hw_mgr_ctx *ctx; + struct cam_ife_hw_mgr *hw_mgr; + struct cam_kmd_buf_info kmd_buf; + uint32_t i; + bool fill_fence = true; + struct cam_isp_prepare_hw_update_data *prepare_hw_data; + + if (!hw_mgr_priv || !prepare_hw_update_args) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + prepare_hw_data = (struct cam_isp_prepare_hw_update_data *) + prepare->priv; + + ctx = (struct cam_ife_hw_mgr_ctx *) prepare->ctxt_to_hw_map; + hw_mgr = (struct cam_ife_hw_mgr *)hw_mgr_priv; + + + CAM_DBG(CAM_REQ, "ctx[%pK][%d] Enter for req_id %lld", + ctx, ctx->ctx_index, prepare->packet->header.request_id); + + rc = cam_packet_util_validate_packet(prepare->packet, + prepare->remain_len); + if (rc) + return rc; + + /* Pre parse the packet*/ + rc = cam_packet_util_get_kmd_buffer(prepare->packet, &kmd_buf); + if (rc) + return rc; + + rc = cam_packet_util_process_patches(prepare->packet, + hw_mgr->mgr_common.cmd_iommu_hdl, + hw_mgr->mgr_common.cmd_iommu_hdl_secure); + if (rc) { + CAM_ERR(CAM_ISP, "Patch ISP packet failed."); + return rc; + } + + prepare->num_hw_update_entries = 0; + prepare->num_in_map_entries = 0; + prepare->num_out_map_entries = 0; + prepare->num_reg_dump_buf = 0; + + memset(&prepare_hw_data->bw_config[0], 0x0, + sizeof(prepare_hw_data->bw_config[0]) * + CAM_IFE_HW_NUM_MAX); + memset(&prepare_hw_data->bw_config_valid[0], 0x0, + sizeof(prepare_hw_data->bw_config_valid[0]) * + CAM_IFE_HW_NUM_MAX); + + for (i = 0; i < ctx->num_base; i++) { + CAM_DBG(CAM_ISP, "process cmd buffer for device %d", i); + + /* Add change base */ + rc = cam_isp_add_change_base(prepare, &ctx->res_list_ife_src, + ctx->base[i].idx, &kmd_buf); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in change base i=%d, idx=%d, rc=%d", + i, ctx->base[i].idx, rc); + goto end; + } + + + /* get command buffers */ + if (ctx->base[i].split_id != CAM_ISP_HW_SPLIT_MAX) { + rc = cam_isp_add_command_buffers(prepare, &kmd_buf, + &ctx->base[i], + cam_isp_packet_generic_blob_handler, + ctx->res_list_ife_out, CAM_IFE_HW_OUT_RES_MAX); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in add cmdbuf, i=%d, split_id=%d, rc=%d", + i, ctx->base[i].split_id, rc); + goto end; + } + } + + /* get IO buffers */ + rc = cam_isp_add_io_buffers(hw_mgr->mgr_common.img_iommu_hdl, + hw_mgr->mgr_common.img_iommu_hdl_secure, + prepare, ctx->base[i].idx, + &kmd_buf, ctx->res_list_ife_out, + &ctx->res_list_ife_in_rd, + CAM_IFE_HW_OUT_RES_MAX, fill_fence); + + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in io buffers, i=%d, rc=%d", + i, rc); + goto end; + } + + /* fence map table entries need to fill only once in the loop */ + if (fill_fence) + fill_fence = false; + } + + /* + * reg update will be done later for the initial configure. + * need to plus one to the op_code and only take the lower + * bits to get the type of operation since UMD definition + * of op_code has some difference from KMD. + */ + if (((prepare->packet->header.op_code + 1) & 0xF) == + CAM_ISP_PACKET_INIT_DEV) { + prepare_hw_data->packet_opcode_type = CAM_ISP_PACKET_INIT_DEV; + if ((prepare->num_reg_dump_buf) && (prepare->num_reg_dump_buf < + CAM_REG_DUMP_MAX_BUF_ENTRIES)) { + ctx->num_reg_dump_buf = prepare->num_reg_dump_buf; + memcpy(ctx->reg_dump_buf_desc, + prepare->reg_dump_buf_desc, + sizeof(struct cam_cmd_buf_desc) * + prepare->num_reg_dump_buf); + } + + goto end; + } else { + prepare_hw_data->packet_opcode_type = CAM_ISP_PACKET_UPDATE_DEV; + prepare_hw_data->num_reg_dump_buf = prepare->num_reg_dump_buf; + if ((prepare_hw_data->num_reg_dump_buf) && + (prepare_hw_data->num_reg_dump_buf < + CAM_REG_DUMP_MAX_BUF_ENTRIES)) { + memcpy(prepare_hw_data->reg_dump_buf_desc, + prepare->reg_dump_buf_desc, + sizeof(struct cam_cmd_buf_desc) * + prepare_hw_data->num_reg_dump_buf); + } + } + + /* add reg update commands */ + for (i = 0; i < ctx->num_base; i++) { + /* Add change base */ + rc = cam_isp_add_change_base(prepare, &ctx->res_list_ife_src, + ctx->base[i].idx, &kmd_buf); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in change base adding reg_update cmd i=%d, idx=%d, rc=%d", + i, ctx->base[i].idx, rc); + goto end; + } + + /*Add reg update */ + rc = cam_isp_add_reg_update(prepare, &ctx->res_list_ife_src, + ctx->base[i].idx, &kmd_buf); + if (rc) { + CAM_ERR(CAM_ISP, + "Add Reg_update cmd Failed i=%d, idx=%d, rc=%d", + i, ctx->base[i].idx, rc); + goto end; + } + } + +end: + return rc; +} + +static int cam_ife_mgr_resume_hw(struct cam_ife_hw_mgr_ctx *ctx) +{ + return cam_ife_mgr_bw_control(ctx, CAM_VFE_BW_CONTROL_INCLUDE); +} + +static int cam_ife_mgr_sof_irq_debug( + struct cam_ife_hw_mgr_ctx *ctx, + uint32_t sof_irq_enable) +{ + int rc = 0; + uint32_t i = 0; + struct cam_isp_hw_mgr_res *hw_mgr_res = NULL; + struct cam_hw_intf *hw_intf = NULL; + struct cam_isp_resource_node *rsrc_node = NULL; + + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.process_cmd) { + rc |= hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_IFE_CSID_SOF_IRQ_DEBUG, + &sof_irq_enable, + sizeof(sof_irq_enable)); + } + } + } + + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + rsrc_node = hw_mgr_res->hw_res[i]; + if (rsrc_node->process_cmd && (rsrc_node->res_id == + CAM_ISP_HW_VFE_IN_CAMIF)) { + rc |= hw_mgr_res->hw_res[i]->process_cmd( + hw_mgr_res->hw_res[i], + CAM_ISP_HW_CMD_SOF_IRQ_DEBUG, + &sof_irq_enable, + sizeof(sof_irq_enable)); + } + } + } + + return rc; +} + +static void cam_ife_mgr_print_io_bufs(struct cam_packet *packet, + int32_t iommu_hdl, int32_t sec_mmu_hdl, uint32_t pf_buf_info, + bool *mem_found) +{ + dma_addr_t iova_addr; + size_t src_buf_size; + int i; + int j; + int rc = 0; + int32_t mmu_hdl; + + struct cam_buf_io_cfg *io_cfg = NULL; + + if (mem_found) + *mem_found = false; + + io_cfg = (struct cam_buf_io_cfg *)((uint32_t *)&packet->payload + + packet->io_configs_offset / 4); + + for (i = 0; i < packet->num_io_configs; i++) { + for (j = 0; j < CAM_PACKET_MAX_PLANES; j++) { + if (!io_cfg[i].mem_handle[j]) + break; + + if (pf_buf_info && + GET_FD_FROM_HANDLE(io_cfg[i].mem_handle[j]) == + GET_FD_FROM_HANDLE(pf_buf_info)) { + CAM_INFO(CAM_ISP, + "Found PF at port: 0x%x mem 0x%x fd: 0x%x", + io_cfg[i].resource_type, + io_cfg[i].mem_handle[j], + pf_buf_info); + if (mem_found) + *mem_found = true; + } + + CAM_INFO(CAM_ISP, "port: 0x%x f: %u format: %d dir %d", + io_cfg[i].resource_type, + io_cfg[i].fence, + io_cfg[i].format, + io_cfg[i].direction); + + mmu_hdl = cam_mem_is_secure_buf( + io_cfg[i].mem_handle[j]) ? sec_mmu_hdl : + iommu_hdl; + rc = cam_mem_get_io_buf(io_cfg[i].mem_handle[j], + mmu_hdl, &iova_addr, &src_buf_size); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "get src buf address fail mem_handle 0x%x", + io_cfg[i].mem_handle[j]); + continue; + } + if ((iova_addr & 0xFFFFFFFF) != iova_addr) { + CAM_ERR(CAM_ISP, "Invalid mapped address"); + rc = -EINVAL; + continue; + } + + CAM_INFO(CAM_ISP, + "pln %d w %d h %d s %u size 0x%x addr 0x%x end_addr 0x%x offset %x memh %x", + j, io_cfg[i].planes[j].width, + io_cfg[i].planes[j].height, + io_cfg[i].planes[j].plane_stride, + (unsigned int)src_buf_size, + (unsigned int)iova_addr, + (unsigned int)iova_addr + + (unsigned int)src_buf_size, + io_cfg[i].offsets[j], + io_cfg[i].mem_handle[j]); + } + } +} + +static int cam_ife_mgr_cmd(void *hw_mgr_priv, void *cmd_args) +{ + int rc = 0; + struct cam_hw_cmd_args *hw_cmd_args = cmd_args; + struct cam_ife_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_ife_hw_mgr_ctx *ctx = (struct cam_ife_hw_mgr_ctx *) + hw_cmd_args->ctxt_to_hw_map; + struct cam_isp_hw_cmd_args *isp_hw_cmd_args = NULL; + struct cam_packet *packet; + + if (!hw_mgr_priv || !cmd_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Fatal: Invalid context is used"); + return -EPERM; + } + + switch (hw_cmd_args->cmd_type) { + case CAM_HW_MGR_CMD_INTERNAL: + if (!hw_cmd_args->u.internal_args) { + CAM_ERR(CAM_ISP, "Invalid cmd arguments"); + return -EINVAL; + } + + isp_hw_cmd_args = (struct cam_isp_hw_cmd_args *) + hw_cmd_args->u.internal_args; + + switch (isp_hw_cmd_args->cmd_type) { + case CAM_ISP_HW_MGR_CMD_PAUSE_HW: + cam_ife_mgr_pause_hw(ctx); + break; + case CAM_ISP_HW_MGR_CMD_RESUME_HW: + cam_ife_mgr_resume_hw(ctx); + break; + case CAM_ISP_HW_MGR_CMD_SOF_DEBUG: + cam_ife_mgr_sof_irq_debug(ctx, + isp_hw_cmd_args->u.sof_irq_enable); + break; + case CAM_ISP_HW_MGR_CMD_CTX_TYPE: + if (ctx->is_fe_enable) + isp_hw_cmd_args->u.ctx_type = CAM_ISP_CTX_FS2; + else if (ctx->is_rdi_only_context) + isp_hw_cmd_args->u.ctx_type = CAM_ISP_CTX_RDI; + else + isp_hw_cmd_args->u.ctx_type = CAM_ISP_CTX_PIX; + break; + case CAM_ISP_HW_MGR_GET_PACKET_OPCODE: + packet = (struct cam_packet *) + isp_hw_cmd_args->cmd_data; + if (((packet->header.op_code + 1) & 0xF) == + CAM_ISP_PACKET_INIT_DEV) + isp_hw_cmd_args->u.packet_op_code = + CAM_ISP_PACKET_INIT_DEV; + else + isp_hw_cmd_args->u.packet_op_code = + CAM_ISP_PACKET_UPDATE_DEV; + break; + default: + CAM_ERR(CAM_ISP, "Invalid HW mgr command:0x%x", + hw_cmd_args->cmd_type); + rc = -EINVAL; + break; + } + break; + case CAM_HW_MGR_CMD_DUMP_PF_INFO: + cam_ife_mgr_print_io_bufs( + hw_cmd_args->u.pf_args.pf_data.packet, + hw_mgr->mgr_common.img_iommu_hdl, + hw_mgr->mgr_common.img_iommu_hdl_secure, + hw_cmd_args->u.pf_args.buf_info, + hw_cmd_args->u.pf_args.mem_found); + break; + case CAM_HW_MGR_CMD_REG_DUMP_ON_FLUSH: + if (ctx->last_dump_flush_req_id == ctx->applied_req_id) + return 0; + + rc = wait_for_completion_timeout( + &ctx->config_done_complete, + msecs_to_jiffies(30)); + if (rc <= 0) { + CAM_ERR(CAM_ISP, + "config done completion timeout, Reg dump will be unreliable rc=%d ctx_index %d", + rc, ctx->ctx_index); + rc = 0; + } + + ctx->last_dump_flush_req_id = ctx->applied_req_id; + rc = cam_ife_mgr_handle_reg_dump(ctx, ctx->reg_dump_buf_desc, + ctx->num_reg_dump_buf, + CAM_ISP_PACKET_META_REG_DUMP_ON_FLUSH, NULL, false); + if (rc) { + CAM_ERR(CAM_ISP, + "Reg dump on flush failed req id: %llu rc: %d", + ctx->applied_req_id, rc); + return rc; + } + + break; + case CAM_HW_MGR_CMD_REG_DUMP_ON_ERROR: + if (ctx->last_dump_err_req_id == ctx->applied_req_id) + return 0; + + ctx->last_dump_err_req_id = ctx->applied_req_id; + rc = cam_ife_mgr_handle_reg_dump(ctx, ctx->reg_dump_buf_desc, + ctx->num_reg_dump_buf, + CAM_ISP_PACKET_META_REG_DUMP_ON_ERROR, NULL, false); + if (rc) { + CAM_ERR(CAM_ISP, + "Reg dump on error failed req id: %llu rc: %d", + ctx->applied_req_id, rc); + return rc; + } + + break; + case CAM_HW_MGR_CMD_DUMP_ACQ_INFO: + cam_ife_hw_mgr_dump_acq_data(ctx); + break; + default: + CAM_ERR(CAM_ISP, "Invalid cmd"); + } + + return rc; +} + +static int cam_ife_mgr_user_dump_hw( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_hw_dump_args *dump_args) +{ + int rc = 0; + struct cam_hw_soc_dump_args soc_dump_args; + + if (!ife_ctx || !dump_args) { + CAM_ERR(CAM_ISP, "Invalid parameters %pK %pK", + ife_ctx, dump_args); + rc = -EINVAL; + goto end; + } + soc_dump_args.buf_handle = dump_args->buf_handle; + soc_dump_args.request_id = dump_args->request_id; + soc_dump_args.offset = dump_args->offset; + + rc = cam_ife_mgr_handle_reg_dump(ife_ctx, + ife_ctx->reg_dump_buf_desc, + ife_ctx->num_reg_dump_buf, + CAM_ISP_PACKET_META_REG_DUMP_ON_ERROR, + &soc_dump_args, + true); + if (rc) { + CAM_ERR(CAM_ISP, + "Dump failed req: %lld handle %u offset %u", + dump_args->request_id, + dump_args->buf_handle, + dump_args->offset); + goto end; + } + dump_args->offset = soc_dump_args.offset; +end: + return rc; +} + +static int cam_ife_mgr_dump(void *hw_mgr_priv, void *args) +{ + struct cam_isp_hw_dump_args isp_hw_dump_args; + struct cam_hw_dump_args *dump_args = (struct cam_hw_dump_args *)args; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_ife_hw_mgr_ctx *ife_ctx = (struct cam_ife_hw_mgr_ctx *) + dump_args->ctxt_to_hw_map; + int i; + int rc = 0; + + /* for some targets, information about the IFE registers to be dumped + * is already submitted with the hw manager. In this case, we + * can dump just the related registers and skip going to core files. + */ + if (ife_ctx->num_reg_dump_buf) { + cam_ife_mgr_user_dump_hw(ife_ctx, dump_args); + goto end; + } + + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &isp_hw_dump_args.cpu_addr, + &isp_hw_dump_args.buf_len); + if (rc) { + CAM_ERR(CAM_ISP, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + return rc; + } + + isp_hw_dump_args.offset = dump_args->offset; + isp_hw_dump_args.req_id = dump_args->request_id; + + list_for_each_entry(hw_mgr_res, &ife_ctx->res_list_ife_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + switch (hw_mgr_res->hw_res[i]->res_id) { + case CAM_IFE_PIX_PATH_RES_RDI_0: + case CAM_IFE_PIX_PATH_RES_RDI_1: + case CAM_IFE_PIX_PATH_RES_RDI_2: + case CAM_IFE_PIX_PATH_RES_RDI_3: + if (ife_ctx->is_rdi_only_context && + hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + case CAM_IFE_PIX_PATH_RES_IPP: + if (hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + default: + CAM_DBG(CAM_ISP, "not a valid res %d", + hw_mgr_res->res_id); + break; + } + } + } + + list_for_each_entry(hw_mgr_res, &ife_ctx->res_list_ife_src, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + switch (hw_mgr_res->res_id) { + case CAM_ISP_HW_VFE_IN_RDI0: + case CAM_ISP_HW_VFE_IN_RDI1: + case CAM_ISP_HW_VFE_IN_RDI2: + case CAM_ISP_HW_VFE_IN_RDI3: + if (ife_ctx->is_rdi_only_context && + hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + case CAM_ISP_HW_VFE_IN_CAMIF: + if (hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + default: + CAM_DBG(CAM_ISP, "not a valid res %d", + hw_mgr_res->res_id); + break; + } + } + } + dump_args->offset = isp_hw_dump_args.offset; + cam_mem_put_cpu_buf(dump_args->buf_handle); +end: + CAM_DBG(CAM_ISP, "offset %u", dump_args->offset); + return rc; +} + +static int cam_ife_mgr_cmd_get_sof_timestamp( + struct cam_ife_hw_mgr_ctx *ife_ctx, + uint64_t *time_stamp, + uint64_t *boot_time_stamp) +{ + int rc = -EINVAL; + uint32_t i; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_csid_get_time_stamp_args csid_get_time; + + hw_mgr_res = list_first_entry(&ife_ctx->res_list_ife_csid, + struct cam_isp_hw_mgr_res, list); + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + /* + * Get the SOF time stamp from left resource only. + * Left resource is master for dual vfe case and + * Rdi only context case left resource only hold + * the RDI resource + */ + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.process_cmd) { + /* + * Single VFE case, Get the time stamp from + * available one csid hw in the context + * Dual VFE case, get the time stamp from + * master(left) would be sufficient + */ + + csid_get_time.node_res = + hw_mgr_res->hw_res[i]; + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_IFE_CSID_CMD_GET_TIME_STAMP, + &csid_get_time, + sizeof( + struct cam_csid_get_time_stamp_args)); + if (!rc && (i == CAM_ISP_HW_SPLIT_LEFT)) { + *time_stamp = + csid_get_time.time_stamp_val; + *boot_time_stamp = + csid_get_time.boot_timestamp; + } + } + } + + if (rc) + CAM_ERR_RATE_LIMIT(CAM_ISP, "Getting sof time stamp failed"); + + return rc; +} + +static int cam_ife_mgr_process_recovery_cb(void *priv, void *data) +{ + int32_t rc = 0; + struct cam_ife_hw_event_recovery_data *recovery_data = data; + struct cam_hw_start_args start_args; + struct cam_hw_stop_args stop_args; + struct cam_ife_hw_mgr *ife_hw_mgr = priv; + struct cam_isp_hw_mgr_res *hw_mgr_res; + uint32_t i = 0; + + uint32_t error_type = recovery_data->error_type; + struct cam_ife_hw_mgr_ctx *ctx = NULL; + + /* Here recovery is performed */ + CAM_DBG(CAM_ISP, "ErrorType = %d", error_type); + + switch (error_type) { + case CAM_ISP_HW_ERROR_OVERFLOW: + case CAM_ISP_HW_ERROR_BUSIF_OVERFLOW: + if (!recovery_data->affected_ctx[0]) { + CAM_ERR(CAM_ISP, + "No context is affected but recovery called"); + kfree(recovery_data); + return 0; + } + /* stop resources here */ + CAM_DBG(CAM_ISP, "STOP: Number of affected context: %d", + recovery_data->no_of_context); + for (i = 0; i < recovery_data->no_of_context; i++) { + stop_args.ctxt_to_hw_map = + recovery_data->affected_ctx[i]; + rc = cam_ife_mgr_stop_hw_in_overflow(&stop_args); + if (rc) { + CAM_ERR(CAM_ISP, "CTX stop failed(%d)", rc); + return rc; + } + } + + if (!g_ife_hw_mgr.debug_cfg.enable_recovery) + break; + + CAM_DBG(CAM_ISP, "RESET: CSID PATH"); + for (i = 0; i < recovery_data->no_of_context; i++) { + ctx = recovery_data->affected_ctx[i]; + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, + list) { + rc = cam_ife_hw_mgr_reset_csid_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Failed RESET (%d)", + hw_mgr_res->res_id); + return rc; + } + } + } + + CAM_DBG(CAM_ISP, "RESET: Calling VFE reset"); + + for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) { + if (recovery_data->affected_core[i]) + cam_ife_mgr_reset_vfe_hw(ife_hw_mgr, i); + } + + CAM_DBG(CAM_ISP, "START: Number of affected context: %d", + recovery_data->no_of_context); + + for (i = 0; i < recovery_data->no_of_context; i++) { + ctx = recovery_data->affected_ctx[i]; + start_args.ctxt_to_hw_map = ctx; + + atomic_set(&ctx->overflow_pending, 0); + + rc = cam_ife_mgr_restart_hw(&start_args); + if (rc) { + CAM_ERR(CAM_ISP, "CTX start failed(%d)", rc); + return rc; + } + CAM_DBG(CAM_ISP, "Started resources rc (%d)", rc); + } + CAM_DBG(CAM_ISP, "Recovery Done rc (%d)", rc); + + break; + + case CAM_ISP_HW_ERROR_P2I_ERROR: + break; + + case CAM_ISP_HW_ERROR_VIOLATION: + break; + + default: + CAM_ERR(CAM_ISP, "Invalid Error"); + } + CAM_DBG(CAM_ISP, "Exit: ErrorType = %d", error_type); + + kfree(recovery_data); + return rc; +} + +static int cam_ife_hw_mgr_do_error_recovery( + struct cam_ife_hw_event_recovery_data *ife_mgr_recovery_data) +{ + int32_t rc = 0; + struct crm_workq_task *task = NULL; + struct cam_ife_hw_event_recovery_data *recovery_data = NULL; + + recovery_data = kzalloc(sizeof(struct cam_ife_hw_event_recovery_data), + GFP_ATOMIC); + if (!recovery_data) + return -ENOMEM; + + memcpy(recovery_data, ife_mgr_recovery_data, + sizeof(struct cam_ife_hw_event_recovery_data)); + + CAM_DBG(CAM_ISP, "Enter: error_type (%d)", recovery_data->error_type); + + task = cam_req_mgr_workq_get_task(g_ife_hw_mgr.workq); + if (!task) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No empty task frame"); + kfree(recovery_data); + return -ENOMEM; + } + + task->process_cb = &cam_ife_mgr_process_recovery_cb; + task->payload = recovery_data; + rc = cam_req_mgr_workq_enqueue_task(task, + recovery_data->affected_ctx[0]->hw_mgr, + CRM_TASK_PRIORITY_0); + + return rc; +} + +/* + * This function checks if any of the valid entry in affected_core[] + * is associated with this context. if YES + * a. It fills the other cores associated with this context.in + * affected_core[] + * b. Return true + */ +static bool cam_ife_hw_mgr_is_ctx_affected( + struct cam_ife_hw_mgr_ctx *ife_hwr_mgr_ctx, + uint32_t *affected_core, + uint32_t size) +{ + + bool rc = false; + uint32_t i = 0, j = 0; + uint32_t max_idx = ife_hwr_mgr_ctx->num_base; + uint32_t ctx_affected_core_idx[CAM_IFE_HW_NUM_MAX] = {0}; + + CAM_DBG(CAM_ISP, "Enter:max_idx = %d", max_idx); + + if ((max_idx >= CAM_IFE_HW_NUM_MAX) || (size > CAM_IFE_HW_NUM_MAX)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "invalid parameter = %d", max_idx); + return rc; + } + + for (i = 0; i < max_idx; i++) { + if (affected_core[ife_hwr_mgr_ctx->base[i].idx]) + rc = true; + else { + ctx_affected_core_idx[j] = ife_hwr_mgr_ctx->base[i].idx; + j = j + 1; + } + } + + if (rc) { + while (j) { + if (affected_core[ctx_affected_core_idx[j-1]] != 1) + affected_core[ctx_affected_core_idx[j-1]] = 1; + j = j - 1; + } + } + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +/* + * For any dual VFE context, if non-affected VFE is also serving + * another context, then that context should also be notified with fatal error + * So Loop through each context and - + * a. match core_idx + * b. Notify CTX with fatal error + */ +static int cam_ife_hw_mgr_find_affected_ctx( + struct cam_isp_hw_error_event_data *error_event_data, + uint32_t curr_core_idx, + struct cam_ife_hw_event_recovery_data *recovery_data) +{ + uint32_t affected_core[CAM_IFE_HW_NUM_MAX] = {0}; + struct cam_ife_hw_mgr_ctx *ife_hwr_mgr_ctx = NULL; + cam_hw_event_cb_func notify_err_cb; + struct cam_ife_hw_mgr *ife_hwr_mgr = NULL; + enum cam_isp_hw_event_type event_type = CAM_ISP_HW_EVENT_ERROR; + uint32_t i = 0; + + if (!recovery_data) { + CAM_ERR(CAM_ISP, "recovery_data parameter is NULL"); + return -EINVAL; + } + + recovery_data->no_of_context = 0; + affected_core[curr_core_idx] = 1; + ife_hwr_mgr = &g_ife_hw_mgr; + + list_for_each_entry(ife_hwr_mgr_ctx, + &ife_hwr_mgr->used_ctx_list, list) { + /* + * Check if current core_idx matches the HW associated + * with this context + */ + if (!cam_ife_hw_mgr_is_ctx_affected(ife_hwr_mgr_ctx, + affected_core, CAM_IFE_HW_NUM_MAX)) + continue; + + if (atomic_read(&ife_hwr_mgr_ctx->overflow_pending)) { + CAM_INFO(CAM_ISP, "CTX:%d already error reported", + ife_hwr_mgr_ctx->ctx_index); + continue; + } + + atomic_set(&ife_hwr_mgr_ctx->overflow_pending, 1); + notify_err_cb = ife_hwr_mgr_ctx->common.event_cb[event_type]; + + /* Add affected_context in list of recovery data */ + CAM_DBG(CAM_ISP, "Add affected ctx %d to list", + ife_hwr_mgr_ctx->ctx_index); + if (recovery_data->no_of_context < CAM_IFE_CTX_MAX) + recovery_data->affected_ctx[ + recovery_data->no_of_context++] = + ife_hwr_mgr_ctx; + + /* + * In the call back function corresponding ISP context + * will update CRM about fatal Error + */ + if (notify_err_cb) { + notify_err_cb(ife_hwr_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_ERROR, error_event_data); + } else { + CAM_WARN(CAM_ISP, "Error call back is not set"); + goto end; + } + } + + /* fill the affected_core in recovery data */ + for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) { + recovery_data->affected_core[i] = affected_core[i]; + CAM_DBG(CAM_ISP, "Vfe core %d is affected (%d)", + i, recovery_data->affected_core[i]); + } +end: + return 0; +} + +static int cam_ife_hw_mgr_handle_csid_event( + struct cam_isp_hw_event_info *event_info) +{ + struct cam_isp_hw_error_event_data error_event_data = {0}; + struct cam_ife_hw_event_recovery_data recovery_data = {0}; + + /* this can be extended based on the types of error + * received from CSID + */ + switch (event_info->err_type) { + case CAM_ISP_HW_ERROR_CSID_FATAL: { + + if (!g_ife_hw_mgr.debug_cfg.enable_csid_recovery) + break; + + error_event_data.error_type = event_info->err_type; + cam_ife_hw_mgr_find_affected_ctx(&error_event_data, + event_info->hw_idx, + &recovery_data); + break; + } + default: + break; + } + return 0; +} + +static int cam_ife_hw_mgr_handle_hw_err( + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + uint32_t core_idx; + struct cam_isp_hw_error_event_data error_event_data = {0}; + struct cam_ife_hw_event_recovery_data recovery_data = {0}; + int rc = -EINVAL; + + if (event_info->err_type == CAM_VFE_IRQ_STATUS_VIOLATION) + error_event_data.error_type = CAM_ISP_HW_ERROR_VIOLATION; + else if (event_info->res_type == CAM_ISP_RESOURCE_VFE_IN) + error_event_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; + else if (event_info->res_type == CAM_ISP_RESOURCE_VFE_OUT) + error_event_data.error_type = CAM_ISP_HW_ERROR_BUSIF_OVERFLOW; + + spin_lock(&g_ife_hw_mgr.ctx_lock); + if (event_info->err_type == CAM_ISP_HW_ERROR_CSID_FATAL) { + rc = cam_ife_hw_mgr_handle_csid_event(event_info); + spin_unlock(&g_ife_hw_mgr.ctx_lock); + return rc; + } + + core_idx = event_info->hw_idx; + + if (g_ife_hw_mgr.debug_cfg.enable_recovery) + error_event_data.recovery_enabled = true; + + if (g_ife_hw_mgr.debug_cfg.enable_req_dump) + error_event_data.enable_req_dump = true; + + rc = cam_ife_hw_mgr_find_affected_ctx(&error_event_data, + core_idx, &recovery_data); + if (rc || !(recovery_data.no_of_context)) + goto end; + + if (event_info->err_type == CAM_VFE_IRQ_STATUS_VIOLATION) + recovery_data.error_type = CAM_ISP_HW_ERROR_VIOLATION; + else + recovery_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; + + cam_ife_hw_mgr_do_error_recovery(&recovery_data); +end: + spin_unlock(&g_ife_hw_mgr.ctx_lock); + return rc; +} + +static int cam_ife_hw_mgr_handle_hw_rup( + void *ctx, + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_ife_hw_mgr_ctx *ife_hw_mgr_ctx = ctx; + cam_hw_event_cb_func ife_hwr_irq_rup_cb; + struct cam_isp_hw_reg_update_event_data rup_event_data; + + ife_hwr_irq_rup_cb = + ife_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_REG_UPDATE]; + + switch (event_info->res_id) { + case CAM_ISP_HW_VFE_IN_CAMIF: + if ((ife_hw_mgr_ctx->is_dual) && + (event_info->hw_idx != + ife_hw_mgr_ctx->master_hw_idx)) + break; + + if (atomic_read(&ife_hw_mgr_ctx->overflow_pending)) + break; + ife_hwr_irq_rup_cb(ife_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_REG_UPDATE, &rup_event_data); + break; + + case CAM_ISP_HW_VFE_IN_RDI0: + case CAM_ISP_HW_VFE_IN_RDI1: + case CAM_ISP_HW_VFE_IN_RDI2: + case CAM_ISP_HW_VFE_IN_RDI3: + if (!ife_hw_mgr_ctx->is_rdi_only_context) + break; + if (atomic_read(&ife_hw_mgr_ctx->overflow_pending)) + break; + ife_hwr_irq_rup_cb(ife_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_REG_UPDATE, &rup_event_data); + break; + + case CAM_ISP_HW_VFE_IN_PDLIB: + case CAM_ISP_HW_VFE_IN_LCR: + break; + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", + event_info->res_id); + break; + } + + CAM_DBG(CAM_ISP, "RUP done for VFE:%d source %d", event_info->hw_idx, + event_info->res_id); + + return 0; +} + +static int cam_ife_hw_mgr_check_irq_for_dual_vfe( + struct cam_ife_hw_mgr_ctx *ife_hw_mgr_ctx, + uint32_t hw_event_type) +{ + int32_t rc = -1; + uint32_t *event_cnt = NULL; + uint32_t master_hw_idx; + uint32_t slave_hw_idx; + + if (!ife_hw_mgr_ctx->is_dual) + return 0; + + switch (hw_event_type) { + case CAM_ISP_HW_EVENT_SOF: + event_cnt = ife_hw_mgr_ctx->sof_cnt; + break; + case CAM_ISP_HW_EVENT_EPOCH: + event_cnt = ife_hw_mgr_ctx->epoch_cnt; + break; + case CAM_ISP_HW_EVENT_EOF: + event_cnt = ife_hw_mgr_ctx->eof_cnt; + break; + default: + return 0; + } + + master_hw_idx = ife_hw_mgr_ctx->master_hw_idx; + slave_hw_idx = ife_hw_mgr_ctx->slave_hw_idx; + + if (event_cnt[master_hw_idx] == event_cnt[slave_hw_idx]) { + + event_cnt[master_hw_idx] = 0; + event_cnt[slave_hw_idx] = 0; + + rc = 0; + return rc; + } + + if ((event_cnt[master_hw_idx] && + (event_cnt[master_hw_idx] - event_cnt[slave_hw_idx] > 1)) || + (event_cnt[slave_hw_idx] && + (event_cnt[slave_hw_idx] - event_cnt[master_hw_idx] > 1))) { + + CAM_ERR_RATE_LIMIT(CAM_ISP, + "One of the VFE could not generate hw event %d master[%d] core_cnt %d slave[%d] core_cnt %d", + hw_event_type, master_hw_idx, event_cnt[master_hw_idx], + slave_hw_idx, event_cnt[slave_hw_idx]); + rc = -1; + return rc; + } + + CAM_DBG(CAM_ISP, "Only one core_index has given hw event %d", + hw_event_type); + + return rc; +} + +static int cam_ife_hw_mgr_handle_hw_epoch( + void *ctx, + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_ife_hw_mgr_ctx *ife_hw_mgr_ctx = ctx; + cam_hw_event_cb_func ife_hw_irq_epoch_cb; + struct cam_isp_hw_epoch_event_data epoch_done_event_data; + int rc = 0; + + ife_hw_irq_epoch_cb = + ife_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_EPOCH]; + + switch (event_info->res_id) { + case CAM_ISP_HW_VFE_IN_CAMIF: + ife_hw_mgr_ctx->epoch_cnt[event_info->hw_idx]++; + rc = cam_ife_hw_mgr_check_irq_for_dual_vfe(ife_hw_mgr_ctx, + CAM_ISP_HW_EVENT_EPOCH); + if (!rc) { + if (atomic_read(&ife_hw_mgr_ctx->overflow_pending)) + break; + + epoch_done_event_data.frame_id_meta = + event_info->th_reg_val; + ife_hw_irq_epoch_cb(ife_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_EPOCH, &epoch_done_event_data); + } + break; + + case CAM_ISP_HW_VFE_IN_RDI0: + case CAM_ISP_HW_VFE_IN_RDI1: + case CAM_ISP_HW_VFE_IN_RDI2: + case CAM_ISP_HW_VFE_IN_RDI3: + case CAM_ISP_HW_VFE_IN_PDLIB: + case CAM_ISP_HW_VFE_IN_LCR: + break; + + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", + event_info->res_id); + break; + } + + CAM_DBG(CAM_ISP, "Epoch for VFE:%d source %d", event_info->hw_idx, + event_info->res_id); + + return 0; +} + +static int cam_ife_hw_mgr_handle_hw_sof( + void *ctx, + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_ife_hw_mgr_ctx *ife_hw_mgr_ctx = ctx; + cam_hw_event_cb_func ife_hw_irq_sof_cb; + struct cam_isp_hw_sof_event_data sof_done_event_data; + int rc = 0; + + ife_hw_irq_sof_cb = + ife_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_SOF]; + + switch (event_info->res_id) { + case CAM_ISP_HW_VFE_IN_CAMIF: + case CAM_ISP_HW_VFE_IN_RD: + ife_hw_mgr_ctx->sof_cnt[event_info->hw_idx]++; + rc = cam_ife_hw_mgr_check_irq_for_dual_vfe(ife_hw_mgr_ctx, + CAM_ISP_HW_EVENT_SOF); + if (!rc) { + cam_ife_mgr_cmd_get_sof_timestamp(ife_hw_mgr_ctx, + &sof_done_event_data.timestamp, + &sof_done_event_data.boot_time); + + if (atomic_read(&ife_hw_mgr_ctx->overflow_pending)) + break; + + ife_hw_irq_sof_cb(ife_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_SOF, &sof_done_event_data); + } + break; + + case CAM_ISP_HW_VFE_IN_RDI0: + case CAM_ISP_HW_VFE_IN_RDI1: + case CAM_ISP_HW_VFE_IN_RDI2: + case CAM_ISP_HW_VFE_IN_RDI3: + if (!ife_hw_mgr_ctx->is_rdi_only_context) + break; + cam_ife_mgr_cmd_get_sof_timestamp(ife_hw_mgr_ctx, + &sof_done_event_data.timestamp, + &sof_done_event_data.boot_time); + if (atomic_read(&ife_hw_mgr_ctx->overflow_pending)) + break; + ife_hw_irq_sof_cb(ife_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_SOF, &sof_done_event_data); + break; + + case CAM_ISP_HW_VFE_IN_PDLIB: + case CAM_ISP_HW_VFE_IN_LCR: + break; + + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", + event_info->res_id); + break; + } + + CAM_DBG(CAM_ISP, "SOF for VFE:%d source %d", event_info->hw_idx, + event_info->res_id); + + return 0; +} + +static int cam_ife_hw_mgr_handle_hw_eof( + void *ctx, + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_ife_hw_mgr_ctx *ife_hw_mgr_ctx = ctx; + cam_hw_event_cb_func ife_hw_irq_eof_cb; + struct cam_isp_hw_eof_event_data eof_done_event_data; + int rc = 0; + + ife_hw_irq_eof_cb = + ife_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_EOF]; + + switch (event_info->res_id) { + case CAM_ISP_HW_VFE_IN_CAMIF: + ife_hw_mgr_ctx->eof_cnt[event_info->hw_idx]++; + rc = cam_ife_hw_mgr_check_irq_for_dual_vfe(ife_hw_mgr_ctx, + CAM_ISP_HW_EVENT_EOF); + if (!rc) { + if (atomic_read(&ife_hw_mgr_ctx->overflow_pending)) + break; + ife_hw_irq_eof_cb(ife_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_EOF, &eof_done_event_data); + } + break; + + case CAM_ISP_HW_VFE_IN_RDI0: + case CAM_ISP_HW_VFE_IN_RDI1: + case CAM_ISP_HW_VFE_IN_RDI2: + case CAM_ISP_HW_VFE_IN_RDI3: + case CAM_ISP_HW_VFE_IN_PDLIB: + case CAM_ISP_HW_VFE_IN_LCR: + break; + + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", + event_info->res_id); + break; + } + + CAM_DBG(CAM_ISP, "EOF for VFE:%d source %d", event_info->hw_idx, + event_info->res_id); + + return 0; +} + +static int cam_ife_hw_mgr_handle_hw_buf_done( + void *ctx, + void *evt_info) +{ + cam_hw_event_cb_func ife_hwr_irq_wm_done_cb; + struct cam_ife_hw_mgr_ctx *ife_hw_mgr_ctx = ctx; + struct cam_isp_hw_done_event_data buf_done_event_data = {0}; + struct cam_isp_hw_event_info *event_info = evt_info; + + ife_hwr_irq_wm_done_cb = + ife_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_DONE]; + + buf_done_event_data.num_handles = 1; + buf_done_event_data.resource_handle[0] = event_info->res_id; + + if (atomic_read(&ife_hw_mgr_ctx->overflow_pending)) + return 0; + + if (buf_done_event_data.num_handles > 0 && ife_hwr_irq_wm_done_cb) { + CAM_DBG(CAM_ISP, "Notify ISP context"); + ife_hwr_irq_wm_done_cb(ife_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_DONE, &buf_done_event_data); + } + + CAM_DBG(CAM_ISP, "Buf done for VFE:%d out_res->res_id: 0x%x", + event_info->hw_idx, event_info->res_id); + + return 0; +} + +static int cam_ife_hw_mgr_event_handler( + void *priv, + uint32_t evt_id, + void *evt_info) +{ + int rc = 0; + + if (!evt_info) + return -EINVAL; + + if (!priv) + if (evt_id != CAM_ISP_HW_EVENT_ERROR) + return -EINVAL; + + CAM_DBG(CAM_ISP, "Event ID 0x%x", evt_id); + + switch (evt_id) { + case CAM_ISP_HW_EVENT_SOF: + rc = cam_ife_hw_mgr_handle_hw_sof(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_REG_UPDATE: + rc = cam_ife_hw_mgr_handle_hw_rup(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_EPOCH: + rc = cam_ife_hw_mgr_handle_hw_epoch(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_EOF: + rc = cam_ife_hw_mgr_handle_hw_eof(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_DONE: + rc = cam_ife_hw_mgr_handle_hw_buf_done(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_ERROR: + rc = cam_ife_hw_mgr_handle_hw_err(evt_info); + break; + + default: + CAM_ERR(CAM_ISP, "Invalid event ID %d", evt_id); + break; + } + + return rc; +} + +static int cam_ife_hw_mgr_sort_dev_with_caps( + struct cam_ife_hw_mgr *ife_hw_mgr) +{ + int i; + + /* get caps for csid devices */ + for (i = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) { + if (!ife_hw_mgr->csid_devices[i]) + continue; + if (ife_hw_mgr->csid_devices[i]->hw_ops.get_hw_caps) { + ife_hw_mgr->csid_devices[i]->hw_ops.get_hw_caps( + ife_hw_mgr->csid_devices[i]->hw_priv, + &ife_hw_mgr->ife_csid_dev_caps[i], + sizeof(ife_hw_mgr->ife_csid_dev_caps[i])); + } + } + + /* get caps for ife devices */ + for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) { + if (!ife_hw_mgr->ife_devices[i]) + continue; + if (ife_hw_mgr->ife_devices[i]->hw_ops.get_hw_caps) { + ife_hw_mgr->ife_devices[i]->hw_ops.get_hw_caps( + ife_hw_mgr->ife_devices[i]->hw_priv, + &ife_hw_mgr->ife_dev_caps[i], + sizeof(ife_hw_mgr->ife_dev_caps[i])); + } + } + + return 0; +} + +static int cam_ife_set_csid_debug(void *data, u64 val) +{ + g_ife_hw_mgr.debug_cfg.csid_debug = val; + CAM_DBG(CAM_ISP, "Set CSID Debug value :%lld", val); + return 0; +} + +static int cam_ife_get_csid_debug(void *data, u64 *val) +{ + *val = g_ife_hw_mgr.debug_cfg.csid_debug; + CAM_DBG(CAM_ISP, "Get CSID Debug value :%lld", + g_ife_hw_mgr.debug_cfg.csid_debug); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(cam_ife_csid_debug, + cam_ife_get_csid_debug, + cam_ife_set_csid_debug, "%16llu"); + +static int cam_ife_set_camif_debug(void *data, u64 val) +{ + g_ife_hw_mgr.debug_cfg.camif_debug = val; + CAM_DBG(CAM_ISP, + "Set camif enable_diag_sensor_status value :%lld", val); + return 0; +} + +static int cam_ife_get_camif_debug(void *data, u64 *val) +{ + *val = g_ife_hw_mgr.debug_cfg.camif_debug; + CAM_DBG(CAM_ISP, + "Set camif enable_diag_sensor_status value :%lld", + g_ife_hw_mgr.debug_cfg.csid_debug); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(cam_ife_camif_debug, + cam_ife_get_camif_debug, + cam_ife_set_camif_debug, "%16llu"); + +static int cam_ife_hw_mgr_debug_register(void) +{ + g_ife_hw_mgr.debug_cfg.dentry = debugfs_create_dir("camera_ife", + NULL); + + if (!g_ife_hw_mgr.debug_cfg.dentry) { + CAM_ERR(CAM_ISP, "failed to create dentry"); + return -ENOMEM; + } + + if (!debugfs_create_file("ife_csid_debug", + 0644, + g_ife_hw_mgr.debug_cfg.dentry, NULL, + &cam_ife_csid_debug)) { + CAM_ERR(CAM_ISP, "failed to create cam_ife_csid_debug"); + goto err; + } + + if (!debugfs_create_u32("enable_recovery", + 0644, + g_ife_hw_mgr.debug_cfg.dentry, + &g_ife_hw_mgr.debug_cfg.enable_recovery)) { + CAM_ERR(CAM_ISP, "failed to create enable_recovery"); + goto err; + } + + if (!debugfs_create_u32("enable_csid_recovery", + 0644, + g_ife_hw_mgr.debug_cfg.dentry, + &g_ife_hw_mgr.debug_cfg.enable_csid_recovery)) { + CAM_ERR(CAM_ISP, "failed to create enable_csid_recovery"); + goto err; + } + + if (!debugfs_create_bool("enable_req_dump", + 0644, + g_ife_hw_mgr.debug_cfg.dentry, + &g_ife_hw_mgr.debug_cfg.enable_req_dump)) { + CAM_ERR(CAM_ISP, "failed to create enable_req_dump"); + goto err; + } + + if (!debugfs_create_file("ife_camif_debug", + 0644, + g_ife_hw_mgr.debug_cfg.dentry, NULL, + &cam_ife_camif_debug)) { + CAM_ERR(CAM_ISP, "failed to create cam_ife_camif_debug"); + goto err; + } + + if (!debugfs_create_bool("per_req_reg_dump", + 0644, + g_ife_hw_mgr.debug_cfg.dentry, + &g_ife_hw_mgr.debug_cfg.per_req_reg_dump)) { + CAM_ERR(CAM_ISP, "failed to create per_req_reg_dump entry"); + goto err; + } + + g_ife_hw_mgr.debug_cfg.enable_recovery = 0; + + return 0; + +err: + debugfs_remove_recursive(g_ife_hw_mgr.debug_cfg.dentry); + return -ENOMEM; +} + +int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) +{ + int rc = -EFAULT; + int i, j; + struct cam_iommu_handle cdm_handles; + struct cam_ife_hw_mgr_ctx *ctx_pool; + struct cam_isp_hw_mgr_res *res_list_ife_out; + + CAM_DBG(CAM_ISP, "Enter"); + + memset(&g_ife_hw_mgr, 0, sizeof(g_ife_hw_mgr)); + + mutex_init(&g_ife_hw_mgr.ctx_mutex); + spin_lock_init(&g_ife_hw_mgr.ctx_lock); + + if (CAM_IFE_HW_NUM_MAX != CAM_IFE_CSID_HW_NUM_MAX) { + CAM_ERR(CAM_ISP, "CSID num is different then IFE num"); + return -EINVAL; + } + + /* fill ife hw intf information */ + for (i = 0, j = 0; i < CAM_IFE_HW_NUM_MAX; i++) { + rc = cam_vfe_hw_init(&g_ife_hw_mgr.ife_devices[i], i); + if (!rc) { + struct cam_hw_info *vfe_hw = + (struct cam_hw_info *) + g_ife_hw_mgr.ife_devices[i]->hw_priv; + struct cam_hw_soc_info *soc_info = &vfe_hw->soc_info; + + j++; + + g_ife_hw_mgr.cdm_reg_map[i] = &soc_info->reg_map[0]; + CAM_DBG(CAM_ISP, + "reg_map: mem base = %pK cam_base = 0x%llx", + (void __iomem *)soc_info->reg_map[0].mem_base, + (uint64_t) soc_info->reg_map[0].mem_cam_base); + } else { + g_ife_hw_mgr.cdm_reg_map[i] = NULL; + } + } + if (j == 0) { + CAM_ERR(CAM_ISP, "no valid IFE HW"); + return -EINVAL; + } + + /* fill csid hw intf information */ + for (i = 0, j = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) { + rc = cam_ife_csid_hw_init(&g_ife_hw_mgr.csid_devices[i], i); + if (!rc) + j++; + } + if (!j) { + CAM_ERR(CAM_ISP, "no valid IFE CSID HW"); + return -EINVAL; + } + + cam_ife_hw_mgr_sort_dev_with_caps(&g_ife_hw_mgr); + + /* setup ife context list */ + INIT_LIST_HEAD(&g_ife_hw_mgr.free_ctx_list); + INIT_LIST_HEAD(&g_ife_hw_mgr.used_ctx_list); + + /* + * for now, we only support one iommu handle. later + * we will need to setup more iommu handle for other + * use cases. + * Also, we have to release them once we have the + * deinit support + */ + if (cam_smmu_get_handle("ife", + &g_ife_hw_mgr.mgr_common.img_iommu_hdl)) { + CAM_ERR(CAM_ISP, "Can not get iommu handle"); + return -EINVAL; + } + + if (cam_smmu_get_handle("cam-secure", + &g_ife_hw_mgr.mgr_common.img_iommu_hdl_secure)) { + CAM_ERR(CAM_ISP, "Failed to get secure iommu handle"); + goto secure_fail; + } + + CAM_DBG(CAM_ISP, "iommu_handles: non-secure[0x%x], secure[0x%x]", + g_ife_hw_mgr.mgr_common.img_iommu_hdl, + g_ife_hw_mgr.mgr_common.img_iommu_hdl_secure); + + if (!cam_cdm_get_iommu_handle("ife", &cdm_handles)) { + CAM_DBG(CAM_ISP, "Successfully acquired the CDM iommu handles"); + g_ife_hw_mgr.mgr_common.cmd_iommu_hdl = cdm_handles.non_secure; + g_ife_hw_mgr.mgr_common.cmd_iommu_hdl_secure = + cdm_handles.secure; + } else { + CAM_DBG(CAM_ISP, "Failed to acquire the CDM iommu handles"); + g_ife_hw_mgr.mgr_common.cmd_iommu_hdl = -1; + g_ife_hw_mgr.mgr_common.cmd_iommu_hdl_secure = -1; + } + + atomic_set(&g_ife_hw_mgr.active_ctx_cnt, 0); + for (i = 0; i < CAM_IFE_CTX_MAX; i++) { + memset(&g_ife_hw_mgr.ctx_pool[i], 0, + sizeof(g_ife_hw_mgr.ctx_pool[i])); + INIT_LIST_HEAD(&g_ife_hw_mgr.ctx_pool[i].list); + + INIT_LIST_HEAD(&g_ife_hw_mgr.ctx_pool[i].res_list_ife_in.list); + INIT_LIST_HEAD(&g_ife_hw_mgr.ctx_pool[i].res_list_ife_cid); + INIT_LIST_HEAD(&g_ife_hw_mgr.ctx_pool[i].res_list_ife_csid); + INIT_LIST_HEAD(&g_ife_hw_mgr.ctx_pool[i].res_list_ife_src); + INIT_LIST_HEAD(&g_ife_hw_mgr.ctx_pool[i].res_list_ife_in_rd); + ctx_pool = &g_ife_hw_mgr.ctx_pool[i]; + for (j = 0; j < CAM_IFE_HW_OUT_RES_MAX; j++) { + res_list_ife_out = &ctx_pool->res_list_ife_out[j]; + INIT_LIST_HEAD(&res_list_ife_out->list); + } + + /* init context pool */ + INIT_LIST_HEAD(&g_ife_hw_mgr.ctx_pool[i].free_res_list); + for (j = 0; j < CAM_IFE_HW_RES_POOL_MAX; j++) { + INIT_LIST_HEAD( + &g_ife_hw_mgr.ctx_pool[i].res_pool[j].list); + list_add_tail( + &g_ife_hw_mgr.ctx_pool[i].res_pool[j].list, + &g_ife_hw_mgr.ctx_pool[i].free_res_list); + } + + g_ife_hw_mgr.ctx_pool[i].cdm_cmd = + kzalloc(((sizeof(struct cam_cdm_bl_request)) + + ((CAM_IFE_HW_ENTRIES_MAX - 1) * + sizeof(struct cam_cdm_bl_cmd))), GFP_KERNEL); + if (!g_ife_hw_mgr.ctx_pool[i].cdm_cmd) { + rc = -ENOMEM; + CAM_ERR(CAM_ISP, "Allocation Failed for cdm command"); + goto end; + } + + g_ife_hw_mgr.ctx_pool[i].ctx_index = i; + g_ife_hw_mgr.ctx_pool[i].hw_mgr = &g_ife_hw_mgr; + + cam_tasklet_init(&g_ife_hw_mgr.mgr_common.tasklet_pool[i], + &g_ife_hw_mgr.ctx_pool[i], i); + g_ife_hw_mgr.ctx_pool[i].common.tasklet_info = + g_ife_hw_mgr.mgr_common.tasklet_pool[i]; + + + init_completion(&g_ife_hw_mgr.ctx_pool[i].config_done_complete); + list_add_tail(&g_ife_hw_mgr.ctx_pool[i].list, + &g_ife_hw_mgr.free_ctx_list); + } + + /* Create Worker for ife_hw_mgr with 10 tasks */ + rc = cam_req_mgr_workq_create("cam_ife_worker", 10, + &g_ife_hw_mgr.workq, CRM_WORKQ_USAGE_NON_IRQ, 0); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Unable to create worker"); + goto end; + } + + /* fill return structure */ + hw_mgr_intf->hw_mgr_priv = &g_ife_hw_mgr; + hw_mgr_intf->hw_get_caps = cam_ife_mgr_get_hw_caps; + hw_mgr_intf->hw_acquire = cam_ife_mgr_acquire; + hw_mgr_intf->hw_start = cam_ife_mgr_start_hw; + hw_mgr_intf->hw_stop = cam_ife_mgr_stop_hw; + hw_mgr_intf->hw_read = cam_ife_mgr_read; + hw_mgr_intf->hw_write = cam_ife_mgr_write; + hw_mgr_intf->hw_release = cam_ife_mgr_release_hw; + hw_mgr_intf->hw_prepare_update = cam_ife_mgr_prepare_hw_update; + hw_mgr_intf->hw_config = cam_ife_mgr_config_hw; + hw_mgr_intf->hw_cmd = cam_ife_mgr_cmd; + hw_mgr_intf->hw_reset = cam_ife_mgr_reset; + hw_mgr_intf->hw_dump = cam_ife_mgr_dump; + + if (iommu_hdl) + *iommu_hdl = g_ife_hw_mgr.mgr_common.img_iommu_hdl; + + cam_ife_hw_mgr_debug_register(); + CAM_DBG(CAM_ISP, "Exit"); + + return 0; +end: + if (rc) { + for (i = 0; i < CAM_IFE_CTX_MAX; i++) { + cam_tasklet_deinit( + &g_ife_hw_mgr.mgr_common.tasklet_pool[i]); + kfree(g_ife_hw_mgr.ctx_pool[i].cdm_cmd); + g_ife_hw_mgr.ctx_pool[i].cdm_cmd = NULL; + g_ife_hw_mgr.ctx_pool[i].common.tasklet_info = NULL; + } + } + cam_smmu_destroy_handle( + g_ife_hw_mgr.mgr_common.img_iommu_hdl_secure); + g_ife_hw_mgr.mgr_common.img_iommu_hdl_secure = -1; +secure_fail: + cam_smmu_destroy_handle(g_ife_hw_mgr.mgr_common.img_iommu_hdl); + g_ife_hw_mgr.mgr_common.img_iommu_hdl = -1; + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h new file mode 100644 index 0000000000000000000000000000000000000000..63ac13323a411df76674cf232b180c1f67415605 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_IFE_HW_MGR_H_ +#define _CAM_IFE_HW_MGR_H_ + +#include +#include +#include "cam_isp_hw_mgr.h" +#include "cam_vfe_hw_intf.h" +#include "cam_ife_csid_hw_intf.h" +#include "cam_tasklet_util.h" + +/* IFE resource constants */ +#define CAM_IFE_HW_IN_RES_MAX (CAM_ISP_IFE_IN_RES_MAX & 0xFF) +#define CAM_IFE_HW_OUT_RES_MAX (CAM_ISP_IFE_OUT_RES_MAX & 0xFF) +#define CAM_IFE_HW_RES_POOL_MAX 64 + +/** + * struct cam_ife_hw_mgr_debug - contain the debug information + * + * @dentry: Debugfs entry + * @csid_debug: csid debug information + * @enable_recovery: enable recovery + * @enable_csid_recovery: enable csid recovery + * @enable_diag_sensor_status: enable sensor diagnosis status + * @enable_req_dump: Enable request dump on HW errors + * @per_req_reg_dump: Enable per request reg dump + * + */ +struct cam_ife_hw_mgr_debug { + struct dentry *dentry; + uint64_t csid_debug; + uint32_t enable_recovery; + uint32_t enable_csid_recovery; + uint32_t camif_debug; + bool enable_req_dump; + bool per_req_reg_dump; +}; + +/** + * struct cam_vfe_hw_mgr_ctx - IFE HW manager Context object + * + * @list: used by the ctx list. + * @common: common acquired context data + * @ctx_index: acquired context id. + * @master_hw_idx: hw index for master core + * @slave_hw_idx: hw index for slave core + * @hw_mgr: IFE hw mgr which owns this context + * @ctx_in_use: flag to tell whether context is active + * @res_list_ife_in: Starting resource(TPG,PHY0, PHY1...) Can only be + * one. + * @res_list_csid: CSID resource list + * @res_list_ife_src: IFE input resource list + * @res_list_ife_in_rd IFE input resource list for read path + * @res_list_ife_out: IFE output resoruces array + * @free_res_list: Free resources list for the branch node + * @res_pool: memory storage for the free resource list + * @irq_status0_mask: irq_status0_mask for the context + * @irq_status1_mask: irq_status1_mask for the context + * @base device base index array contain the all IFE HW + * instance associated with this context. + * @num_base number of valid base data in the base array + * @cdm_handle cdm hw acquire handle + * @cdm_ops cdm util operation pointer for building + * cdm commands + * @cdm_cmd cdm base and length request pointer + * @sof_cnt sof count value per core, used for dual VFE + * @epoch_cnt epoch count value per core, used for dual VFE + * @eof_cnt eof count value per core, used for dual VFE + * @overflow_pending flat to specify the overflow is pending for the + * context + * @cdm_done flag to indicate cdm has finished writing shadow + * registers + * @is_rdi_only_context flag to specify the context has only rdi resource + * @config_done_complete indicator for configuration complete + * @reg_dump_buf_desc: cmd buffer descriptors for reg dump + * @num_reg_dump_buf: Count of descriptors in reg_dump_buf_desc + * @applied_req_id: Last request id to be applied + * @last_dump_flush_req_id Last req id for which reg dump on flush was called + * @last_dump_err_req_id Last req id for which reg dump on error was called + * @init_done indicate whether init hw is done + * @is_fe_enable indicate whether fetch engine\read path is enabled + * @is_dual indicate whether context is in dual VFE mode + * @ts captured timestamp when the ctx is acquired + */ +struct cam_ife_hw_mgr_ctx { + struct list_head list; + struct cam_isp_hw_mgr_ctx common; + + uint32_t ctx_index; + uint32_t master_hw_idx; + uint32_t slave_hw_idx; + struct cam_ife_hw_mgr *hw_mgr; + uint32_t ctx_in_use; + + struct cam_isp_hw_mgr_res res_list_ife_in; + struct list_head res_list_ife_cid; + struct list_head res_list_ife_csid; + struct list_head res_list_ife_src; + struct list_head res_list_ife_in_rd; + struct cam_isp_hw_mgr_res res_list_ife_out[ + CAM_IFE_HW_OUT_RES_MAX]; + + struct list_head free_res_list; + struct cam_isp_hw_mgr_res res_pool[CAM_IFE_HW_RES_POOL_MAX]; + + uint32_t irq_status0_mask[CAM_IFE_HW_NUM_MAX]; + uint32_t irq_status1_mask[CAM_IFE_HW_NUM_MAX]; + struct cam_isp_ctx_base_info base[CAM_IFE_HW_NUM_MAX]; + uint32_t num_base; + uint32_t cdm_handle; + struct cam_cdm_utils_ops *cdm_ops; + struct cam_cdm_bl_request *cdm_cmd; + + uint32_t sof_cnt[CAM_IFE_HW_NUM_MAX]; + uint32_t epoch_cnt[CAM_IFE_HW_NUM_MAX]; + uint32_t eof_cnt[CAM_IFE_HW_NUM_MAX]; + atomic_t overflow_pending; + atomic_t cdm_done; + uint32_t is_rdi_only_context; + struct completion config_done_complete; + struct cam_cmd_buf_desc reg_dump_buf_desc[ + CAM_REG_DUMP_MAX_BUF_ENTRIES]; + uint32_t num_reg_dump_buf; + uint64_t applied_req_id; + uint64_t last_dump_flush_req_id; + uint64_t last_dump_err_req_id; + bool init_done; + bool is_fe_enable; + bool is_dual; + struct timespec64 ts; +}; + +/** + * struct cam_ife_hw_mgr - IFE HW Manager + * + * @mgr_common: common data for all HW managers + * @csid_devices; csid device instances array. This will be filled by + * HW manager during the initialization. + * @ife_devices: IFE device instances array. This will be filled by + * HW layer during initialization + * @ctx_mutex: mutex for the hw context pool + * @free_ctx_list: free hw context list + * @used_ctx_list: used hw context list + * @ctx_pool: context storage + * @ife_csid_dev_caps csid device capability stored per core + * @ife_dev_caps ife device capability per core + * @work q work queue for IFE hw manager + * @debug_cfg debug configuration + * @ctx_lock Spinlock for HW manager + */ +struct cam_ife_hw_mgr { + struct cam_isp_hw_mgr mgr_common; + struct cam_hw_intf *csid_devices[CAM_IFE_CSID_HW_NUM_MAX]; + struct cam_hw_intf *ife_devices[CAM_IFE_HW_NUM_MAX]; + struct cam_soc_reg_map *cdm_reg_map[CAM_IFE_HW_NUM_MAX]; + + struct mutex ctx_mutex; + atomic_t active_ctx_cnt; + struct list_head free_ctx_list; + struct list_head used_ctx_list; + struct cam_ife_hw_mgr_ctx ctx_pool[CAM_IFE_CTX_MAX]; + + struct cam_ife_csid_hw_caps ife_csid_dev_caps[ + CAM_IFE_CSID_HW_NUM_MAX]; + struct cam_vfe_hw_get_hw_cap ife_dev_caps[CAM_IFE_HW_NUM_MAX]; + struct cam_req_mgr_core_workq *workq; + struct cam_ife_hw_mgr_debug debug_cfg; + spinlock_t ctx_lock; +}; + +/** + * struct cam_ife_hw_event_recovery_data - Payload for the recovery procedure + * + * @error_type: Error type that causes the recovery + * @affected_core: Array of the hardware cores that are affected + * @affected_ctx: Array of the hardware contexts that are affected + * @no_of_context: Actual number of the affected context + * + */ +struct cam_ife_hw_event_recovery_data { + uint32_t error_type; + uint32_t affected_core[CAM_ISP_HW_NUM_MAX]; + struct cam_ife_hw_mgr_ctx *affected_ctx[CAM_IFE_CTX_MAX]; + uint32_t no_of_context; +}; + +/** + * cam_ife_hw_mgr_init() + * + * @brief: Initialize the IFE hardware manger. This is the + * etnry functinon for the IFE HW manager. + * + * @hw_mgr_intf: IFE hardware manager object returned + * @iommu_hdl: Iommu handle to be returned + * + */ +int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl); + +#ifndef CONFIG_SPECTRA_CAMERA_IFE +int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) +{ + return 0; +} +#endif +#endif /* _CAM_IFE_HW_MGR_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.c new file mode 100644 index 0000000000000000000000000000000000000000..ff1ca48330030a0a96f0d2adc7616b2e0074cf12 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_isp_hw_mgr_intf.h" +#include "cam_ife_hw_mgr.h" +#include "cam_debug_util.h" +#include "cam_tfe_hw_mgr.h" + + +int cam_isp_hw_mgr_init(const char *device_name_str, + struct cam_hw_mgr_intf *hw_mgr, int *iommu_hdl) +{ + int rc = 0; + + if (strnstr(device_name_str, "ife", strlen(device_name_str))) + rc = cam_ife_hw_mgr_init(hw_mgr, iommu_hdl); + else if (strnstr(device_name_str, "tfe", strlen(device_name_str))) + rc = cam_tfe_hw_mgr_init(hw_mgr, iommu_hdl); + else { + CAM_ERR(CAM_ISP, "Invalid ISP hw type :%s", device_name_str); + rc = -EINVAL; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.h new file mode 100644 index 0000000000000000000000000000000000000000..99f665de82e23ed2dc3a97c0a45251be22d40e53 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_ISP_HW_MGR_H_ +#define _CAM_ISP_HW_MGR_H_ + +#include +#include "cam_isp_hw_mgr_intf.h" +#include "cam_tasklet_util.h" +#include "cam_isp_hw.h" + + +#define CAM_ISP_HW_NUM_MAX 7 + +/** + * struct cam_isp_hw_mgr_ctx - common acquired context for managers + * + * @takslet_info: assciated tasklet + * @event_cb: call back interface to ISP context. Set during + * acquire device + * @cb_priv: first argument for the call back function + * set during acquire device + * + */ +struct cam_isp_hw_mgr_ctx { + void *tasklet_info; + cam_hw_event_cb_func event_cb[CAM_ISP_HW_EVENT_MAX]; + void *cb_priv; +}; + +/** + * struct cam_isp_hw_mgr - ISP HW Manager common object + * + * @tasklet_pool: Tasklet pool + * @img_iommu_hdl: iommu memory handle for regular image buffer + * @img_iommu_hdl_secure: iommu memory handle for secure image buffer + * @cmd_iommu_hdl: iommu memory handle for regular command buffer + * @cmd_iommu_hdl: iommu memory handle for secure command buffer + * @scratch_buf_range: scratch buffer range (not for IFE) + * @scratch_buf_addr: scratch buffer address (not for IFE) + * + */ +struct cam_isp_hw_mgr { + void *tasklet_pool[CAM_CTX_MAX]; + int img_iommu_hdl; + int img_iommu_hdl_secure; + int cmd_iommu_hdl; + int cmd_iommu_hdl_secure; + uint32_t scratch_buf_range; + dma_addr_t scratch_buf_addr; +}; + +/** + * struct cam_isp_hw_mgr_res- HW resources for the ISP hw manager + * + * @list: used by the resource list + * @res_type: ISP manager resource type + * @res_id: resource id based on the resource type for root or + * leaf resource, it matches the KMD interface port id. + * For branch resrouce, it is defined by the ISP HW + * layer + * @is_dual_isp is dual isp hw resource + * @hw_res: hw layer resource array. For single ISP, only one ISP + * hw resrouce will be acquired. For dual ISP, two hw + * resources from different ISP HW device will be + * acquired + * @is_secure informs whether the resource is in secure mode or not + * @num_children: number of the child resource node. + * + */ +struct cam_isp_hw_mgr_res { + struct list_head list; + enum cam_isp_resource_type res_type; + uint32_t res_id; + uint32_t is_dual_isp; + struct cam_isp_resource_node *hw_res[CAM_ISP_HW_SPLIT_MAX]; + uint32_t is_secure; + uint32_t num_children; +}; + + +/** + * struct cam_isp_ctx_base_info - Base hardware information for the context + * + * @idx: Base resource index + * @split_id: Split info for the base resource + * + */ +struct cam_isp_ctx_base_info { + uint32_t idx; + enum cam_isp_hw_split_id split_id; +}; +#endif /* _CAM_ISP_HW_MGR_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c new file mode 100644 index 0000000000000000000000000000000000000000..ac08e20e7c6ca0e2cf70d1e4be4b152fd825553f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -0,0 +1,5746 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "cam_smmu_api.h" +#include "cam_req_mgr_workq.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_isp_hw.h" +#include "cam_tfe_csid_hw_intf.h" +#include "cam_tfe_hw_intf.h" +#include "cam_isp_packet_parser.h" +#include "cam_tfe_hw_mgr.h" +#include "cam_cdm_intf_api.h" +#include "cam_packet_util.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" +#include "cam_mem_mgr_api.h" +#include "cam_common_util.h" +#include "cam_req_mgr_debug.h" +#include "cam_trace.h" + +#define CAM_TFE_HW_ENTRIES_MAX 20 +#define CAM_TFE_HW_CONFIG_TIMEOUT 60 +#define CAM_TFE_HW_CONFIG_WAIT_MAX_TRY 3 + +#define TZ_SVC_SMMU_PROGRAM 0x15 +#define TZ_SAFE_SYSCALL_ID 0x3 +#define CAM_TFE_SAFE_DISABLE 0 +#define CAM_TFE_SAFE_ENABLE 1 +#define SMMU_SE_TFE 0 + + +static struct cam_tfe_hw_mgr g_tfe_hw_mgr; + +static int cam_tfe_hw_mgr_event_handler( + void *priv, + uint32_t evt_id, + void *evt_info); + +static int cam_tfe_mgr_regspace_data_cb(uint32_t reg_base_type, + void *hw_mgr_ctx, struct cam_hw_soc_info **soc_info_ptr, + uint32_t *reg_base_idx) +{ + int rc = 0; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_isp_resource_node *res; + struct cam_tfe_hw_mgr_ctx *ctx = + (struct cam_tfe_hw_mgr_ctx *) hw_mgr_ctx; + + *soc_info_ptr = NULL; + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + if ((hw_mgr_res->res_id != CAM_ISP_HW_TFE_IN_CAMIF) && + !ctx->is_rdi_only_context) + continue; + + switch (reg_base_type) { + case CAM_REG_DUMP_BASE_TYPE_CAMNOC: + case CAM_REG_DUMP_BASE_TYPE_ISP_LEFT: + if (!hw_mgr_res->hw_res[CAM_ISP_HW_SPLIT_LEFT]) + continue; + + res = hw_mgr_res->hw_res[CAM_ISP_HW_SPLIT_LEFT]; + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA, + &soc_info, sizeof(void *)); + + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in regspace data query split idx: %d rc : %d", + CAM_ISP_HW_SPLIT_LEFT, rc); + return rc; + } + + if (reg_base_type == CAM_REG_DUMP_BASE_TYPE_ISP_LEFT) + *reg_base_idx = 0; + else + *reg_base_idx = 1; + + *soc_info_ptr = soc_info; + break; + case CAM_REG_DUMP_BASE_TYPE_ISP_RIGHT: + if (!hw_mgr_res->hw_res[CAM_ISP_HW_SPLIT_RIGHT]) + continue; + + + res = hw_mgr_res->hw_res[CAM_ISP_HW_SPLIT_RIGHT]; + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA, + &soc_info, sizeof(void *)); + + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in regspace data query split idx: %d rc : %d", + CAM_ISP_HW_SPLIT_RIGHT, rc); + return rc; + } + + *reg_base_idx = 0; + *soc_info_ptr = soc_info; + break; + default: + CAM_ERR(CAM_ISP, + "Unrecognized reg base type: %d", + reg_base_type); + return -EINVAL; + } + } + + return rc; +} + +static int cam_tfe_mgr_handle_reg_dump(struct cam_tfe_hw_mgr_ctx *ctx, + struct cam_cmd_buf_desc *reg_dump_buf_desc, uint32_t num_reg_dump_buf, + uint32_t meta_type, + void *soc_dump_args, + bool user_triggered_dump) +{ + int rc = -EINVAL, i; + + if (!num_reg_dump_buf || !reg_dump_buf_desc) { + CAM_DBG(CAM_ISP, + "Invalid args for reg dump req_id: [%llu] ctx idx: [%u] meta_type: [%u] num_reg_dump_buf: [%u] reg_dump_buf_desc: [%pK]", + ctx->applied_req_id, ctx->ctx_index, meta_type, + num_reg_dump_buf, reg_dump_buf_desc); + return rc; + } + + if (!atomic_read(&ctx->cdm_done)) + CAM_WARN_RATE_LIMIT(CAM_ISP, + "Reg dump values might be from more than one request"); + + for (i = 0; i < num_reg_dump_buf; i++) { + CAM_DBG(CAM_ISP, "Reg dump cmd meta data: %u req_type: %u", + reg_dump_buf_desc[i].meta_data, meta_type); + if (reg_dump_buf_desc[i].meta_data == meta_type) { + rc = cam_soc_util_reg_dump_to_cmd_buf(ctx, + ®_dump_buf_desc[i], + ctx->applied_req_id, + cam_tfe_mgr_regspace_data_cb, + soc_dump_args, + user_triggered_dump); + if (rc) { + CAM_ERR(CAM_ISP, + "Reg dump failed at idx: %d, rc: %d req_id: %llu meta type: %u", + i, rc, ctx->applied_req_id, meta_type); + return rc; + } + } + } + + return rc; +} + +static int cam_tfe_mgr_get_hw_caps(void *hw_mgr_priv, + void *hw_caps_args) +{ + int rc = 0; + int i; + uint32_t num_dev = 0; + struct cam_tfe_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_query_cap_cmd *query = hw_caps_args; + struct cam_isp_tfe_query_cap_cmd query_isp; + + CAM_DBG(CAM_ISP, "enter"); + + if (copy_from_user(&query_isp, + u64_to_user_ptr(query->caps_handle), + sizeof(struct cam_isp_tfe_query_cap_cmd))) { + rc = -EFAULT; + return rc; + } + + query_isp.device_iommu.non_secure = hw_mgr->mgr_common.img_iommu_hdl; + query_isp.device_iommu.secure = hw_mgr->mgr_common.img_iommu_hdl_secure; + query_isp.cdm_iommu.non_secure = hw_mgr->mgr_common.cmd_iommu_hdl; + query_isp.cdm_iommu.secure = hw_mgr->mgr_common.cmd_iommu_hdl_secure; + + for (i = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { + if (!hw_mgr->csid_devices[i]) + continue; + + query_isp.dev_caps[i].hw_type = CAM_ISP_TFE_HW_TFE; + query_isp.dev_caps[i].hw_version.major = 5; + query_isp.dev_caps[i].hw_version.minor = 3; + query_isp.dev_caps[i].hw_version.incr = 0; + + /* + * device number is based on number of full tfe + * if pix is not supported, set reserve to 1 + */ + if (hw_mgr->tfe_csid_dev_caps[i].num_pix) { + query_isp.dev_caps[i].hw_version.reserved = 0; + num_dev++; + } else + query_isp.dev_caps[i].hw_version.reserved = 1; + } + + query_isp.num_dev = num_dev; + + if (copy_to_user(u64_to_user_ptr(query->caps_handle), + &query_isp, sizeof(struct cam_isp_tfe_query_cap_cmd))) + rc = -EFAULT; + + CAM_DBG(CAM_ISP, "exit rc :%d", rc); + + return rc; +} + +static int cam_tfe_hw_mgr_is_rdi_res(uint32_t res_id) +{ + int rc = 0; + + switch (res_id) { + case CAM_ISP_TFE_OUT_RES_RDI_0: + case CAM_ISP_TFE_OUT_RES_RDI_1: + case CAM_ISP_TFE_OUT_RES_RDI_2: + rc = 1; + break; + default: + break; + } + + return rc; +} + +static int cam_tfe_hw_mgr_convert_rdi_out_res_id_to_in_res(int res_id) +{ + if (res_id == CAM_ISP_TFE_OUT_RES_RDI_0) + return CAM_ISP_HW_TFE_IN_RDI0; + else if (res_id == CAM_ISP_TFE_OUT_RES_RDI_1) + return CAM_ISP_HW_TFE_IN_RDI1; + else if (res_id == CAM_ISP_TFE_OUT_RES_RDI_2) + return CAM_ISP_HW_TFE_IN_RDI1; + + return CAM_ISP_HW_TFE_IN_MAX; +} + +static int cam_tfe_hw_mgr_reset_csid_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int i; + int rc = 0; + struct cam_hw_intf *hw_intf; + struct cam_tfe_csid_reset_cfg_args csid_reset_args; + + csid_reset_args.reset_type = CAM_TFE_CSID_RESET_PATH; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + csid_reset_args.node_res = isp_hw_res->hw_res[i]; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + CAM_DBG(CAM_ISP, "Resetting csid hardware %d", + hw_intf->hw_idx); + if (hw_intf->hw_ops.reset) { + rc = hw_intf->hw_ops.reset(hw_intf->hw_priv, + &csid_reset_args, + sizeof(struct cam_tfe_csid_reset_cfg_args)); + if (rc <= 0) + goto err; + } + } + + return 0; +err: + CAM_ERR(CAM_ISP, "RESET HW res failed: (type:%d, id:%d)", + isp_hw_res->res_type, isp_hw_res->res_id); + return rc; +} + +static int cam_tfe_hw_mgr_init_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int i; + int rc = -EINVAL; + struct cam_hw_intf *hw_intf; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + CAM_DBG(CAM_ISP, "hw type %d hw index:%d", + hw_intf->hw_type, hw_intf->hw_idx); + if (hw_intf->hw_ops.init) { + rc = hw_intf->hw_ops.init(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + if (rc) + goto err; + } + } + + return 0; +err: + CAM_ERR(CAM_ISP, "INIT HW res failed: (type:%d, id:%d)", + isp_hw_res->res_type, isp_hw_res->res_id); + return rc; +} + +static int cam_tfe_hw_mgr_start_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res, + struct cam_tfe_hw_mgr_ctx *ctx) +{ + int i; + int rc = -EINVAL; + struct cam_hw_intf *hw_intf; + + /* Start slave (which is right split) first */ + for (i = CAM_ISP_HW_SPLIT_MAX - 1; i >= 0; i--) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.start) { + rc = hw_intf->hw_ops.start(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start HW resources"); + goto err; + } + CAM_DBG(CAM_ISP, "Start hw type:%d HW idx %d Res %d", + hw_intf->hw_type, + hw_intf->hw_idx, + isp_hw_res->hw_res[i]->res_id); + } else { + CAM_ERR(CAM_ISP, "function null"); + goto err; + } + } + + return 0; +err: + CAM_ERR(CAM_ISP, "Start hw res failed (type:%d, id:%d)", + isp_hw_res->res_type, isp_hw_res->res_id); + return rc; +} + +static void cam_tfe_hw_mgr_stop_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int i; + struct cam_hw_intf *hw_intf; + uint32_t dummy_args; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + + if (isp_hw_res->hw_res[i]->res_state != + CAM_ISP_RESOURCE_STATE_STREAMING) + continue; + + if (hw_intf->hw_ops.stop) + hw_intf->hw_ops.stop(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + else + CAM_ERR(CAM_ISP, "stop null"); + if (hw_intf->hw_ops.process_cmd && + isp_hw_res->res_type == CAM_ISP_RESOURCE_TFE_OUT) { + hw_intf->hw_ops.process_cmd(hw_intf->hw_priv, + CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ, + &dummy_args, sizeof(dummy_args)); + } + } +} + +static void cam_tfe_hw_mgr_deinit_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int i; + struct cam_hw_intf *hw_intf; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.deinit) + hw_intf->hw_ops.deinit(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + } +} + +static void cam_tfe_hw_mgr_deinit_hw( + struct cam_tfe_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + + if (!ctx->init_done) { + CAM_WARN(CAM_ISP, "ctx is not in init state"); + return; + } + + /* Deinit TFE CSID hw */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + CAM_DBG(CAM_ISP, "Going to DeInit TFE CSID"); + cam_tfe_hw_mgr_deinit_hw_res(hw_mgr_res); + } + + /* Deint TFE HW */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + cam_tfe_hw_mgr_deinit_hw_res(hw_mgr_res); + } + + if (ctx->is_tpg) + cam_tfe_hw_mgr_deinit_hw_res(&ctx->res_list_tpg); + + ctx->init_done = false; +} + +static int cam_tfe_hw_mgr_init_hw( + struct cam_tfe_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + int rc = 0; + + if (ctx->is_tpg) { + CAM_DBG(CAM_ISP, "INIT TPG ... in ctx id:%d", + ctx->ctx_index); + rc = cam_tfe_hw_mgr_init_hw_res(&ctx->res_list_tpg); + if (rc) { + CAM_ERR(CAM_ISP, "Can not INIT TFE TPG(id :%d)", + ctx->res_list_tpg.hw_res[0]->hw_intf->hw_idx); + goto deinit; + } + } + + CAM_DBG(CAM_ISP, "INIT TFE csid ... in ctx id:%d", + ctx->ctx_index); + /* INIT TFE csid */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + rc = cam_tfe_hw_mgr_init_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Can not INIT TFE CSID(id :%d)", + hw_mgr_res->res_id); + goto deinit; + } + } + + /* INIT TFE IN */ + CAM_DBG(CAM_ISP, "INIT TFE in resource ctx id:%d", + ctx->ctx_index); + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + rc = cam_tfe_hw_mgr_init_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Can not INIT TFE SRC (%d)", + hw_mgr_res->res_id); + goto deinit; + } + } + + return rc; +deinit: + ctx->init_done = true; + cam_tfe_hw_mgr_deinit_hw(ctx); + return rc; +} + +static int cam_tfe_hw_mgr_put_res( + struct list_head *src_list, + struct cam_isp_hw_mgr_res **res) +{ + struct cam_isp_hw_mgr_res *res_ptr = NULL; + + res_ptr = *res; + if (res_ptr) + list_add_tail(&res_ptr->list, src_list); + + return 0; +} + +static int cam_tfe_hw_mgr_get_res( + struct list_head *src_list, + struct cam_isp_hw_mgr_res **res) +{ + int rc = 0; + struct cam_isp_hw_mgr_res *res_ptr = NULL; + + if (!list_empty(src_list)) { + res_ptr = list_first_entry(src_list, + struct cam_isp_hw_mgr_res, list); + list_del_init(&res_ptr->list); + } else { + CAM_ERR(CAM_ISP, "No more free tfe hw mgr ctx"); + rc = -EINVAL; + } + *res = res_ptr; + + return rc; +} + +static int cam_tfe_hw_mgr_free_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int rc = 0; + int i; + struct cam_hw_intf *hw_intf; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.release) { + rc = hw_intf->hw_ops.release(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + if (rc) + CAM_ERR(CAM_ISP, + "Release hw resource id %d failed", + isp_hw_res->res_id); + isp_hw_res->hw_res[i] = NULL; + } else + CAM_ERR(CAM_ISP, "Release null"); + } + /* caller should make sure the resource is in a list */ + list_del_init(&isp_hw_res->list); + memset(isp_hw_res, 0, sizeof(*isp_hw_res)); + INIT_LIST_HEAD(&isp_hw_res->list); + + return 0; +} + +static int cam_tfe_mgr_csid_stop_hw( + struct cam_tfe_hw_mgr_ctx *ctx, struct list_head *stop_list, + uint32_t base_idx, uint32_t stop_cmd) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *isp_res; + struct cam_isp_resource_node *stop_res[CAM_TFE_CSID_PATH_RES_MAX]; + struct cam_tfe_csid_hw_stop_args stop; + struct cam_hw_intf *hw_intf; + uint32_t i, cnt; + + cnt = 0; + list_for_each_entry(hw_mgr_res, stop_list, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i] || + (hw_mgr_res->hw_res[i]->res_state != + CAM_ISP_RESOURCE_STATE_STREAMING)) + continue; + + isp_res = hw_mgr_res->hw_res[i]; + if (isp_res->hw_intf->hw_idx != base_idx) + continue; + CAM_DBG(CAM_ISP, "base_idx %d res_id %d cnt %u", + base_idx, isp_res->res_id, cnt); + stop_res[cnt] = isp_res; + cnt++; + } + } + + if (cnt) { + hw_intf = stop_res[0]->hw_intf; + stop.num_res = cnt; + stop.node_res = stop_res; + stop.stop_cmd = stop_cmd; + hw_intf->hw_ops.stop(hw_intf->hw_priv, &stop, sizeof(stop)); + } + + return 0; +} + +static int cam_tfe_hw_mgr_release_hw_for_ctx( + struct cam_tfe_hw_mgr_ctx *tfe_ctx) +{ + uint32_t i; + int rc = 0; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res_temp; + struct cam_hw_intf *hw_intf; + + /* tfe out resource */ + for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) + cam_tfe_hw_mgr_free_hw_res(&tfe_ctx->res_list_tfe_out[i]); + + /* tfe in resource */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &tfe_ctx->res_list_tfe_in, list) { + cam_tfe_hw_mgr_free_hw_res(hw_mgr_res); + cam_tfe_hw_mgr_put_res(&tfe_ctx->free_res_list, &hw_mgr_res); + } + + /* tfe csid resource */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &tfe_ctx->res_list_tfe_csid, list) { + cam_tfe_hw_mgr_free_hw_res(hw_mgr_res); + cam_tfe_hw_mgr_put_res(&tfe_ctx->free_res_list, &hw_mgr_res); + } + + /* release tpg resource */ + if (tfe_ctx->is_tpg) { + hw_intf = tfe_ctx->res_list_tpg.hw_res[0]->hw_intf; + if (hw_intf->hw_ops.release) { + rc = hw_intf->hw_ops.release(hw_intf->hw_priv, + tfe_ctx->res_list_tpg.hw_res[0], + sizeof(struct cam_isp_resource_node)); + if (rc) + CAM_ERR(CAM_ISP, + "TPG Release hw failed"); + tfe_ctx->res_list_tpg.hw_res[0] = NULL; + } else + CAM_ERR(CAM_ISP, "TPG resource Release null"); + } + + /* clean up the callback function */ + tfe_ctx->common.cb_priv = NULL; + memset(tfe_ctx->common.event_cb, 0, sizeof(tfe_ctx->common.event_cb)); + + CAM_DBG(CAM_ISP, "release context completed ctx id:%d", + tfe_ctx->ctx_index); + + return 0; +} + + +static int cam_tfe_hw_mgr_put_ctx( + struct list_head *src_list, + struct cam_tfe_hw_mgr_ctx **tfe_ctx) +{ + struct cam_tfe_hw_mgr_ctx *ctx_ptr = NULL; + + mutex_lock(&g_tfe_hw_mgr.ctx_mutex); + ctx_ptr = *tfe_ctx; + if (ctx_ptr) + list_add_tail(&ctx_ptr->list, src_list); + *tfe_ctx = NULL; + mutex_unlock(&g_tfe_hw_mgr.ctx_mutex); + return 0; +} + +static int cam_tfe_hw_mgr_get_ctx( + struct list_head *src_list, + struct cam_tfe_hw_mgr_ctx **tfe_ctx) +{ + int rc = 0; + struct cam_tfe_hw_mgr_ctx *ctx_ptr = NULL; + + mutex_lock(&g_tfe_hw_mgr.ctx_mutex); + if (!list_empty(src_list)) { + ctx_ptr = list_first_entry(src_list, + struct cam_tfe_hw_mgr_ctx, list); + list_del_init(&ctx_ptr->list); + } else { + CAM_ERR(CAM_ISP, "No more free tfe hw mgr ctx"); + rc = -EINVAL; + } + *tfe_ctx = ctx_ptr; + mutex_unlock(&g_tfe_hw_mgr.ctx_mutex); + + return rc; +} + +static void cam_tfe_hw_mgr_dump_all_ctx(void) +{ + uint32_t i; + struct cam_tfe_hw_mgr_ctx *ctx; + struct cam_isp_hw_mgr_res *hw_mgr_res; + + mutex_lock(&g_tfe_hw_mgr.ctx_mutex); + list_for_each_entry(ctx, &g_tfe_hw_mgr.used_ctx_list, list) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "ctx id:%d is_dual:%d is_tpg:%d num_base:%d rdi only:%d", + ctx->ctx_index, ctx->is_dual, ctx->is_tpg, + ctx->num_base, ctx->is_rdi_only_context); + + if (ctx->res_list_tpg.res_type == CAM_ISP_RESOURCE_TPG) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "Acquired TPG HW:%d", + ctx->res_list_tpg.hw_res[0]->hw_intf->hw_idx); + } + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, + list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + CAM_INFO_RATE_LIMIT(CAM_ISP, + "csid:%d res_type:%d res_id:%d res_state:%d", + hw_mgr_res->hw_res[i]->hw_intf->hw_idx, + hw_mgr_res->hw_res[i]->res_type, + hw_mgr_res->hw_res[i]->res_id, + hw_mgr_res->hw_res[i]->res_state); + } + } + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, + list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + CAM_INFO_RATE_LIMIT(CAM_ISP, + "TFE IN:%d res_type:%d res_id:%d res_state:%d", + hw_mgr_res->hw_res[i]->hw_intf->hw_idx, + hw_mgr_res->hw_res[i]->res_type, + hw_mgr_res->hw_res[i]->res_id, + hw_mgr_res->hw_res[i]->res_state); + } + } + } + mutex_unlock(&g_tfe_hw_mgr.ctx_mutex); + +} + +static void cam_tfe_mgr_add_base_info( + struct cam_tfe_hw_mgr_ctx *ctx, + enum cam_isp_hw_split_id split_id, + uint32_t base_idx) +{ + uint32_t i; + + if (!ctx->num_base) { + ctx->base[0].split_id = split_id; + ctx->base[0].idx = base_idx; + ctx->num_base++; + CAM_DBG(CAM_ISP, + "Add split id = %d for base idx = %d num_base=%d", + split_id, base_idx, ctx->num_base); + } else { + /*Check if base index already exists in the list */ + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].idx == base_idx) { + if (split_id != CAM_ISP_HW_SPLIT_MAX && + ctx->base[i].split_id == + CAM_ISP_HW_SPLIT_MAX) + ctx->base[i].split_id = split_id; + + break; + } + } + + if (i == ctx->num_base) { + ctx->base[ctx->num_base].split_id = split_id; + ctx->base[ctx->num_base].idx = base_idx; + ctx->num_base++; + CAM_DBG(CAM_ISP, + "Add split_id=%d for base idx=%d num_base=%d", + split_id, base_idx, ctx->num_base); + } + } +} + +static int cam_tfe_mgr_process_base_info( + struct cam_tfe_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *res = NULL; + uint32_t i; + + if (list_empty(&ctx->res_list_tfe_in)) { + CAM_ERR(CAM_ISP, "tfe in list empty"); + return -ENODEV; + } + + /* TFE in resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) + continue; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + res = hw_mgr_res->hw_res[i]; + cam_tfe_mgr_add_base_info(ctx, i, + res->hw_intf->hw_idx); + CAM_DBG(CAM_ISP, "add base info for hw %d", + res->hw_intf->hw_idx); + } + } + CAM_DBG(CAM_ISP, "ctx base num = %d", ctx->num_base); + + return 0; +} + +static int cam_tfe_hw_mgr_acquire_res_tfe_out_rdi( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_hw_mgr_res *tfe_in_res, + struct cam_isp_tfe_in_port_info *in_port) +{ + int rc = -EINVAL; + struct cam_tfe_acquire_args tfe_acquire; + struct cam_isp_tfe_out_port_info *out_port = NULL; + struct cam_isp_hw_mgr_res *tfe_out_res; + struct cam_hw_intf *hw_intf; + uint32_t i, tfe_out_res_id, tfe_in_res_id; + + /* take left resource */ + tfe_in_res_id = tfe_in_res->hw_res[0]->res_id; + + switch (tfe_in_res_id) { + case CAM_ISP_HW_TFE_IN_RDI0: + tfe_out_res_id = CAM_ISP_TFE_OUT_RES_RDI_0; + break; + case CAM_ISP_HW_TFE_IN_RDI1: + tfe_out_res_id = CAM_ISP_TFE_OUT_RES_RDI_1; + break; + case CAM_ISP_HW_TFE_IN_RDI2: + tfe_out_res_id = CAM_ISP_TFE_OUT_RES_RDI_2; + break; + default: + CAM_ERR(CAM_ISP, "invalid resource type"); + goto err; + } + CAM_DBG(CAM_ISP, "tfe_in_res_id = %d, tfe_out_red_id = %d", + tfe_in_res_id, tfe_out_res_id); + + tfe_acquire.rsrc_type = CAM_ISP_RESOURCE_TFE_OUT; + tfe_acquire.tasklet = tfe_ctx->common.tasklet_info; + + tfe_out_res = &tfe_ctx->res_list_tfe_out[tfe_out_res_id & 0xFF]; + for (i = 0; i < in_port->num_out_res; i++) { + out_port = &in_port->data[i]; + + CAM_DBG(CAM_ISP, "i = %d, tfe_out_res_id = %d, out_port: %d", + i, tfe_out_res_id, out_port->res_id); + + if (tfe_out_res_id != out_port->res_id) + continue; + + tfe_acquire.tfe_out.cdm_ops = tfe_ctx->cdm_ops; + tfe_acquire.priv = tfe_ctx; + tfe_acquire.tfe_out.out_port_info = out_port; + tfe_acquire.tfe_out.split_id = CAM_ISP_HW_SPLIT_LEFT; + tfe_acquire.tfe_out.unique_id = tfe_ctx->ctx_index; + tfe_acquire.tfe_out.is_dual = 0; + tfe_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + hw_intf = tfe_in_res->hw_res[0]->hw_intf; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &tfe_acquire, + sizeof(struct cam_tfe_acquire_args)); + if (rc) { + CAM_ERR(CAM_ISP, "Can not acquire out resource 0x%x", + out_port->res_id); + goto err; + } + break; + } + + if (i == in_port->num_out_res) { + CAM_ERR(CAM_ISP, + "Cannot acquire out resource, i=%d, num_out_res=%d", + i, in_port->num_out_res); + goto err; + } + + tfe_out_res->hw_res[0] = tfe_acquire.tfe_out.rsrc_node; + tfe_out_res->is_dual_isp = 0; + tfe_out_res->res_id = tfe_out_res_id; + tfe_out_res->res_type = CAM_ISP_RESOURCE_TFE_OUT; + tfe_in_res->num_children++; + + return 0; +err: + return rc; +} + +static int cam_tfe_hw_mgr_acquire_res_tfe_out_pixel( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_hw_mgr_res *tfe_in_res, + struct cam_isp_tfe_in_port_info *in_port) +{ + int rc = -EINVAL; + uint32_t i, j, k; + struct cam_tfe_acquire_args tfe_acquire; + struct cam_isp_tfe_out_port_info *out_port; + struct cam_isp_hw_mgr_res *tfe_out_res; + struct cam_hw_intf *hw_intf; + + for (i = 0; i < in_port->num_out_res; i++) { + out_port = &in_port->data[i]; + k = out_port->res_id & 0xFF; + if (k >= CAM_TFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "invalid output resource type 0x%x", + out_port->res_id); + continue; + } + + if (cam_tfe_hw_mgr_is_rdi_res(out_port->res_id)) + continue; + + CAM_DBG(CAM_ISP, "res_type 0x%x", out_port->res_id); + + tfe_out_res = &tfe_ctx->res_list_tfe_out[k]; + tfe_out_res->is_dual_isp = in_port->usage_type; + + tfe_acquire.rsrc_type = CAM_ISP_RESOURCE_TFE_OUT; + tfe_acquire.tasklet = tfe_ctx->common.tasklet_info; + tfe_acquire.tfe_out.cdm_ops = tfe_ctx->cdm_ops; + tfe_acquire.priv = tfe_ctx; + tfe_acquire.tfe_out.out_port_info = out_port; + tfe_acquire.tfe_out.is_dual = tfe_in_res->is_dual_isp; + tfe_acquire.tfe_out.unique_id = tfe_ctx->ctx_index; + tfe_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + + for (j = 0; j < CAM_ISP_HW_SPLIT_MAX; j++) { + if (!tfe_in_res->hw_res[j]) + continue; + + hw_intf = tfe_in_res->hw_res[j]->hw_intf; + + if (j == CAM_ISP_HW_SPLIT_LEFT) { + tfe_acquire.tfe_out.split_id = + CAM_ISP_HW_SPLIT_LEFT; + if (tfe_in_res->is_dual_isp) + tfe_acquire.tfe_out.is_master = 1; + else + tfe_acquire.tfe_out.is_master = 0; + } else { + tfe_acquire.tfe_out.split_id = + CAM_ISP_HW_SPLIT_RIGHT; + tfe_acquire.tfe_out.is_master = 0; + } + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &tfe_acquire, + sizeof(struct cam_tfe_acquire_args)); + if (rc) { + CAM_ERR(CAM_ISP, + "Can not acquire out resource 0x%x", + out_port->res_id); + goto err; + } + + tfe_out_res->hw_res[j] = + tfe_acquire.tfe_out.rsrc_node; + CAM_DBG(CAM_ISP, "resource type :0x%x res id:0x%x", + tfe_out_res->hw_res[j]->res_type, + tfe_out_res->hw_res[j]->res_id); + + } + tfe_out_res->res_type = CAM_ISP_RESOURCE_TFE_OUT; + tfe_out_res->res_id = out_port->res_id; + tfe_in_res->num_children++; + } + + return 0; +err: + /* release resource at the entry function */ + return rc; +} + +static int cam_tfe_hw_mgr_acquire_res_tfe_out( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info *in_port) +{ + int rc = -EINVAL; + struct cam_isp_hw_mgr_res *tfe_in_res; + + list_for_each_entry(tfe_in_res, &tfe_ctx->res_list_tfe_in, list) { + if (tfe_in_res->num_children) + continue; + + switch (tfe_in_res->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + rc = cam_tfe_hw_mgr_acquire_res_tfe_out_pixel(tfe_ctx, + tfe_in_res, in_port); + break; + case CAM_ISP_HW_TFE_IN_RDI0: + case CAM_ISP_HW_TFE_IN_RDI1: + case CAM_ISP_HW_TFE_IN_RDI2: + rc = cam_tfe_hw_mgr_acquire_res_tfe_out_rdi(tfe_ctx, + tfe_in_res, in_port); + break; + default: + CAM_ERR(CAM_ISP, "Unknown TFE SRC resource: %d", + tfe_in_res->res_id); + break; + } + if (rc) + goto err; + } + + return 0; +err: + /* release resource on entry function */ + return rc; +} + +static int cam_tfe_hw_mgr_acquire_res_tfe_in( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info *in_port, + uint32_t *pdaf_enable) +{ + int rc = -EINVAL; + int i; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_isp_hw_mgr_res *tfe_src_res; + struct cam_tfe_acquire_args tfe_acquire; + struct cam_hw_intf *hw_intf; + struct cam_tfe_hw_mgr *tfe_hw_mgr; + + tfe_hw_mgr = tfe_ctx->hw_mgr; + + list_for_each_entry(csid_res, &tfe_ctx->res_list_tfe_csid, list) { + if (csid_res->num_children) + continue; + + rc = cam_tfe_hw_mgr_get_res(&tfe_ctx->free_res_list, + &tfe_src_res); + if (rc) { + CAM_ERR(CAM_ISP, "No more free hw mgr resource"); + goto err; + } + cam_tfe_hw_mgr_put_res(&tfe_ctx->res_list_tfe_in, + &tfe_src_res); + tfe_src_res->hw_res[0] = NULL; + tfe_src_res->hw_res[1] = NULL; + + tfe_acquire.rsrc_type = CAM_ISP_RESOURCE_TFE_IN; + tfe_acquire.tasklet = tfe_ctx->common.tasklet_info; + tfe_acquire.tfe_in.cdm_ops = tfe_ctx->cdm_ops; + tfe_acquire.tfe_in.in_port = in_port; + tfe_acquire.tfe_in.camif_pd_enable = *pdaf_enable; + tfe_acquire.priv = tfe_ctx; + tfe_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + + switch (csid_res->res_id) { + case CAM_TFE_CSID_PATH_RES_IPP: + tfe_acquire.tfe_in.res_id = + CAM_ISP_HW_TFE_IN_CAMIF; + + if (csid_res->is_dual_isp) + tfe_acquire.tfe_in.sync_mode = + CAM_ISP_HW_SYNC_MASTER; + else + tfe_acquire.tfe_in.sync_mode = + CAM_ISP_HW_SYNC_NONE; + + break; + case CAM_TFE_CSID_PATH_RES_RDI_0: + tfe_acquire.tfe_in.res_id = CAM_ISP_HW_TFE_IN_RDI0; + tfe_acquire.tfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; + break; + case CAM_TFE_CSID_PATH_RES_RDI_1: + tfe_acquire.tfe_in.res_id = CAM_ISP_HW_TFE_IN_RDI1; + tfe_acquire.tfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; + break; + case CAM_TFE_CSID_PATH_RES_RDI_2: + tfe_acquire.tfe_in.res_id = CAM_ISP_HW_TFE_IN_RDI2; + tfe_acquire.tfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; + break; + default: + CAM_ERR(CAM_ISP, "Wrong TFE CSID Resource Node"); + goto err; + } + tfe_src_res->res_type = tfe_acquire.rsrc_type; + tfe_src_res->res_id = tfe_acquire.tfe_in.res_id; + tfe_src_res->is_dual_isp = csid_res->is_dual_isp; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!csid_res->hw_res[i]) + continue; + + hw_intf = tfe_hw_mgr->tfe_devices[ + csid_res->hw_res[i]->hw_intf->hw_idx]; + + /* fill in more acquire information as needed */ + /* slave Camif resource, */ + if (i == CAM_ISP_HW_SPLIT_RIGHT && + tfe_src_res->is_dual_isp) { + tfe_acquire.tfe_in.sync_mode = + CAM_ISP_HW_SYNC_SLAVE; + tfe_acquire.tfe_in.dual_tfe_sync_sel_idx = + csid_res->hw_res[0]->hw_intf->hw_idx; + } else if (i == CAM_ISP_HW_SPLIT_LEFT && + tfe_src_res->is_dual_isp) + tfe_acquire.tfe_in.dual_tfe_sync_sel_idx = + csid_res->hw_res[1]->hw_intf->hw_idx; + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &tfe_acquire, + sizeof(struct cam_tfe_acquire_args)); + if (rc) { + CAM_ERR(CAM_ISP, + "Can not acquire TFE HW res %d", + csid_res->res_id); + goto err; + } + tfe_src_res->hw_res[i] = tfe_acquire.tfe_in.rsrc_node; + CAM_DBG(CAM_ISP, + "acquire success TFE:%d res type :0x%x res id:0x%x", + hw_intf->hw_idx, + tfe_src_res->hw_res[i]->res_type, + tfe_src_res->hw_res[i]->res_id); + + } + csid_res->num_children++; + } + + return 0; +err: + /* release resource at the entry function */ + return rc; +} + +static int cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info *in_port) +{ + int rc = -EINVAL; + int i, j; + uint32_t acquired_cnt = 0; + struct cam_tfe_hw_mgr *tfe_hw_mgr; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_csid_hw_reserve_resource_args csid_acquire; + enum cam_tfe_csid_path_res_id path_res_id; + struct cam_isp_hw_mgr_res *csid_res_temp, *csid_res_iterator; + struct cam_isp_tfe_out_port_info *out_port = NULL; + + tfe_hw_mgr = tfe_ctx->hw_mgr; + /* get csid resource */ + path_res_id = CAM_TFE_CSID_PATH_RES_IPP; + + rc = cam_tfe_hw_mgr_get_res(&tfe_ctx->free_res_list, &csid_res); + if (rc) { + CAM_ERR(CAM_ISP, "No more free hw mgr resource"); + goto end; + } + + csid_res_temp = csid_res; + + csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH; + csid_acquire.res_id = path_res_id; + csid_acquire.in_port = in_port; + csid_acquire.out_port = in_port->data; + csid_acquire.node_res = NULL; + csid_acquire.event_cb_prv = tfe_ctx; + csid_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + if (in_port->num_out_res) + out_port = &(in_port->data[0]); + + if (tfe_ctx->is_tpg) { + if (tfe_ctx->res_list_tpg.hw_res[0]->hw_intf->hw_idx == 0) + csid_acquire.phy_sel = CAM_ISP_TFE_IN_RES_PHY_0; + else + csid_acquire.phy_sel = CAM_ISP_TFE_IN_RES_PHY_1; + } + + if (in_port->usage_type) + csid_acquire.sync_mode = CAM_ISP_HW_SYNC_MASTER; + else + csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE; + + /* Try acquiring CSID resource from previously acquired HW */ + list_for_each_entry(csid_res_iterator, &tfe_ctx->res_list_tfe_csid, + list) { + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!csid_res_iterator->hw_res[i]) + continue; + + if (csid_res_iterator->is_secure == 1 || + (csid_res_iterator->is_secure == 0 && + in_port->num_out_res && + out_port->secure_mode == 1)) + continue; + + hw_intf = csid_res_iterator->hw_res[i]->hw_intf; + csid_acquire.master_idx = hw_intf->hw_idx; + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) { + CAM_DBG(CAM_ISP, + "No tfe csid resource from hw %d", + hw_intf->hw_idx); + continue; + } + + csid_res_temp->hw_res[acquired_cnt++] = + csid_acquire.node_res; + + CAM_DBG(CAM_ISP, + "acquired from old csid(%s)=%d CSID rsrc successfully", + (i == 0) ? "left" : "right", + hw_intf->hw_idx); + + if (in_port->usage_type && acquired_cnt == 1 && + path_res_id == CAM_TFE_CSID_PATH_RES_IPP) + /* + * Continue to acquire Right for IPP. + * Dual TFE for RDI is not currently + * supported. + */ + continue; + + if (acquired_cnt) + /* + * If successfully acquired CSID from + * previously acquired HW, skip the next + * part + */ + goto acquire_successful; + } + } + + /* + * If successfully acquired CSID from + * previously acquired HW, skip the next + * part + */ + if (acquired_cnt) + goto acquire_successful; + + /* Acquire Left if not already acquired */ + if (in_port->usage_type) { + for (i = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { + if (!tfe_hw_mgr->csid_devices[i]) + continue; + + hw_intf = tfe_hw_mgr->csid_devices[i]; + csid_acquire.master_idx = hw_intf->hw_idx; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) + continue; + else { + csid_res_temp->hw_res[acquired_cnt++] = + csid_acquire.node_res; + break; + } + } + + if (i == CAM_TFE_CSID_HW_NUM_MAX || !csid_acquire.node_res) { + CAM_ERR(CAM_ISP, + "Can not acquire left tfe csid path resource %d", + path_res_id); + goto put_res; + } + } else { + for (i = (CAM_TFE_CSID_HW_NUM_MAX - 1); i >= 0; i--) { + if (!tfe_hw_mgr->csid_devices[i]) + continue; + + hw_intf = tfe_hw_mgr->csid_devices[i]; + csid_acquire.master_idx = hw_intf->hw_idx; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) + continue; + else { + csid_res_temp->hw_res[acquired_cnt++] = + csid_acquire.node_res; + break; + } + } + + if (i == -1 || !csid_acquire.node_res) { + CAM_ERR(CAM_ISP, + "Can not acquire tfe csid path resource %d", + path_res_id); + goto put_res; + } + } +acquire_successful: + CAM_DBG(CAM_ISP, "CSID path left acquired success. is_dual %d", + in_port->usage_type); + + csid_res_temp->res_type = CAM_ISP_RESOURCE_PIX_PATH; + csid_res_temp->res_id = path_res_id; + + if (in_port->usage_type) { + csid_res_temp->is_dual_isp = 1; + tfe_ctx->is_dual = true; + tfe_ctx->master_hw_idx = + csid_res_temp->hw_res[0]->hw_intf->hw_idx; + } else + csid_res_temp->is_dual_isp = 0; + + if (in_port->num_out_res) + csid_res_temp->is_secure = out_port->secure_mode; + + cam_tfe_hw_mgr_put_res(&tfe_ctx->res_list_tfe_csid, &csid_res); + + /* + * Acquire Right if not already acquired. + * Dual TFE for RDI is not currently supported. + */ + if (in_port->usage_type && (path_res_id == CAM_TFE_CSID_PATH_RES_IPP) + && (acquired_cnt == 1)) { + memset(&csid_acquire, 0, sizeof(csid_acquire)); + csid_acquire.node_res = NULL; + csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH; + csid_acquire.res_id = path_res_id; + csid_acquire.in_port = in_port; + csid_acquire.master_idx = + csid_res_temp->hw_res[0]->hw_intf->hw_idx; + csid_acquire.sync_mode = CAM_ISP_HW_SYNC_SLAVE; + csid_acquire.node_res = NULL; + csid_acquire.out_port = in_port->data; + csid_acquire.event_cb_prv = tfe_ctx; + csid_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + + if (tfe_ctx->is_tpg) { + if (tfe_ctx->res_list_tpg.hw_res[0]->hw_intf->hw_idx + == 0) + csid_acquire.phy_sel = CAM_ISP_TFE_IN_RES_PHY_0; + else + csid_acquire.phy_sel = CAM_ISP_TFE_IN_RES_PHY_1; + } + + for (j = 0; j < CAM_TFE_CSID_HW_NUM_MAX; j++) { + if (!tfe_hw_mgr->csid_devices[j]) + continue; + + if (j == csid_res_temp->hw_res[0]->hw_intf->hw_idx) + continue; + + hw_intf = tfe_hw_mgr->csid_devices[j]; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) + continue; + else + break; + } + + if (j == CAM_TFE_CSID_HW_NUM_MAX) { + CAM_ERR(CAM_ISP, + "Can not acquire tfe csid pixel resource"); + goto end; + } + csid_res_temp->hw_res[1] = csid_acquire.node_res; + tfe_ctx->slave_hw_idx = + csid_res_temp->hw_res[1]->hw_intf->hw_idx; + CAM_DBG(CAM_ISP, "CSID right acquired success is_dual %d", + in_port->usage_type); + } + + return 0; +put_res: + cam_tfe_hw_mgr_put_res(&tfe_ctx->free_res_list, &csid_res); +end: + return rc; +} + +static int cam_tfe_hw_mgr_acquire_tpg( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info **in_port, + uint32_t num_inport) +{ + int rc = -EINVAL; + uint32_t i, j = 0; + struct cam_tfe_hw_mgr *tfe_hw_mgr; + struct cam_hw_intf *hw_intf; + struct cam_top_tpg_hw_reserve_resource_args tpg_reserve; + + tfe_hw_mgr = tfe_ctx->hw_mgr; + + for (i = 0; i < CAM_TOP_TPG_HW_NUM_MAX; i++) { + if (!tfe_hw_mgr->tpg_devices[i]) + continue; + + hw_intf = tfe_hw_mgr->tpg_devices[i]; + tpg_reserve.num_inport = num_inport; + tpg_reserve.node_res = NULL; + for (j = 0; j < num_inport; j++) + tpg_reserve.in_port[j] = in_port[j]; + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &tpg_reserve, sizeof(tpg_reserve)); + if (!rc) + break; + } + + if (i == CAM_TOP_TPG_HW_NUM_MAX || !tpg_reserve.node_res) { + CAM_ERR(CAM_ISP, "Can not acquire tfe TPG"); + rc = -EINVAL; + goto end; + } + + tfe_ctx->res_list_tpg.res_type = CAM_ISP_RESOURCE_TPG; + tfe_ctx->res_list_tpg.hw_res[0] = tpg_reserve.node_res; + +end: + return rc; +} + +static enum cam_tfe_csid_path_res_id + cam_tfe_hw_mgr_get_tfe_csid_rdi_res_type( + uint32_t out_port_type) +{ + enum cam_tfe_csid_path_res_id path_id; + + CAM_DBG(CAM_ISP, "out_port_type %x", out_port_type); + switch (out_port_type) { + case CAM_ISP_TFE_OUT_RES_RDI_0: + path_id = CAM_TFE_CSID_PATH_RES_RDI_0; + break; + case CAM_ISP_TFE_OUT_RES_RDI_1: + path_id = CAM_TFE_CSID_PATH_RES_RDI_1; + break; + case CAM_ISP_TFE_OUT_RES_RDI_2: + path_id = CAM_TFE_CSID_PATH_RES_RDI_2; + break; + default: + path_id = CAM_TFE_CSID_PATH_RES_MAX; + CAM_DBG(CAM_ISP, "maximum rdi type exceeded out_port_type:%d ", + out_port_type); + break; + } + + CAM_DBG(CAM_ISP, "out_port %x path_id %d", out_port_type, path_id); + + return path_id; +} + +static int cam_tfe_hw_mgr_acquire_res_tfe_csid_rdi( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info *in_port) +{ + int rc = -EINVAL; + int i, j; + + struct cam_tfe_hw_mgr *tfe_hw_mgr; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_hw_intf *hw_intf; + struct cam_isp_tfe_out_port_info *out_port; + struct cam_tfe_csid_hw_reserve_resource_args csid_acquire; + struct cam_isp_hw_mgr_res *csid_res_iterator; + enum cam_tfe_csid_path_res_id path_res_id; + + tfe_hw_mgr = tfe_ctx->hw_mgr; + + for (j = 0; j < in_port->num_out_res; j++) { + out_port = &in_port->data[j]; + path_res_id = cam_tfe_hw_mgr_get_tfe_csid_rdi_res_type( + out_port->res_id); + + if (path_res_id == CAM_TFE_CSID_PATH_RES_MAX) + continue; + + rc = cam_tfe_hw_mgr_get_res(&tfe_ctx->free_res_list, &csid_res); + if (rc) { + CAM_ERR(CAM_ISP, "No more free hw mgr resource"); + goto end; + } + + memset(&csid_acquire, 0, sizeof(csid_acquire)); + csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH; + csid_acquire.res_id = path_res_id; + csid_acquire.in_port = in_port; + csid_acquire.out_port = out_port; + csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE; + csid_acquire.node_res = NULL; + csid_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + csid_acquire.event_cb_prv = tfe_ctx; + + if (tfe_ctx->is_tpg) { + if (tfe_ctx->res_list_tpg.hw_res[0]->hw_intf->hw_idx == + 0) + csid_acquire.phy_sel = CAM_ISP_TFE_IN_RES_PHY_0; + else + csid_acquire.phy_sel = CAM_ISP_TFE_IN_RES_PHY_1; + } + + /* Try acquiring CSID resource from previously acquired HW */ + list_for_each_entry(csid_res_iterator, + &tfe_ctx->res_list_tfe_csid, list) { + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!csid_res_iterator->hw_res[i]) + continue; + + if (csid_res_iterator->is_secure == 1 || + (csid_res_iterator->is_secure == 0 && + in_port->num_out_res && + out_port->secure_mode == 1)) + continue; + + hw_intf = csid_res_iterator->hw_res[i]->hw_intf; + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) { + CAM_DBG(CAM_ISP, + "No tfe csid resource from hw %d", + hw_intf->hw_idx); + continue; + } + + if (csid_acquire.node_res == NULL) { + CAM_ERR(CAM_ISP, + "Acquire RDI:%d rsrc failed", + path_res_id); + goto put_res; + } + + csid_res->hw_res[0] = csid_acquire.node_res; + + CAM_DBG(CAM_ISP, + "acquired from old csid(%s)=%d CSID rsrc successfully", + (i == 0) ? "left" : "right", + hw_intf->hw_idx); + /* + * If successfully acquired CSID from + * previously acquired HW, skip the next + * part + */ + goto acquire_successful; + } + } + + /* Acquire if not already acquired */ + if (tfe_ctx->is_dual) { + for (i = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { + if (!tfe_hw_mgr->csid_devices[i]) + continue; + + hw_intf = tfe_hw_mgr->csid_devices[i]; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) + continue; + else { + csid_res->hw_res[0] = + csid_acquire.node_res; + break; + } + } + + if (i == CAM_TFE_CSID_HW_NUM_MAX || + !csid_acquire.node_res) { + CAM_ERR(CAM_ISP, + "Can not acquire tfe csid rdi path%d", + path_res_id); + + rc = -EINVAL; + goto put_res; + } + } else { + for (i = CAM_TFE_CSID_HW_NUM_MAX - 1; i >= 0; i--) { + if (!tfe_hw_mgr->csid_devices[i]) + continue; + + hw_intf = tfe_hw_mgr->csid_devices[i]; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) + continue; + else { + csid_res->hw_res[0] = + csid_acquire.node_res; + break; + } + } + + if (i == -1 || !csid_acquire.node_res) { + CAM_ERR(CAM_ISP, + "Can not acquire tfe csid rdi path %d", + path_res_id); + + rc = -EINVAL; + goto put_res; + } + } + +acquire_successful: + CAM_DBG(CAM_ISP, "CSID path :%d acquired success", path_res_id); + csid_res->res_type = CAM_ISP_RESOURCE_PIX_PATH; + csid_res->res_id = path_res_id; + csid_res->hw_res[1] = NULL; + csid_res->is_dual_isp = 0; + + if (in_port->num_out_res) + csid_res->is_secure = out_port->secure_mode; + + cam_tfe_hw_mgr_put_res(&tfe_ctx->res_list_tfe_csid, &csid_res); + } + + return 0; +put_res: + cam_tfe_hw_mgr_put_res(&tfe_ctx->free_res_list, &csid_res); +end: + return rc; +} + +static int cam_tfe_hw_mgr_preprocess_port( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info *in_port, + int *ipp_count, + int *rdi_count, + int *pdaf_enable) +{ + int ipp_num = 0; + int rdi_num = 0; + bool rdi2_enable = false; + uint32_t i; + struct cam_isp_tfe_out_port_info *out_port; + struct cam_tfe_hw_mgr *tfe_hw_mgr; + + tfe_hw_mgr = tfe_ctx->hw_mgr; + + + for (i = 0; i < in_port->num_out_res; i++) { + out_port = &in_port->data[i]; + CAM_DBG(CAM_ISP, "out_res id %d", out_port->res_id); + + if (cam_tfe_hw_mgr_is_rdi_res(out_port->res_id)) { + rdi_num++; + if (out_port->res_id == CAM_ISP_TFE_OUT_RES_RDI_2) + rdi2_enable = true; + } else { + ipp_num++; + if (out_port->res_id == CAM_ISP_TFE_OUT_RES_PDAF) + *pdaf_enable = 1; + } + } + + if (*pdaf_enable && rdi2_enable) { + CAM_ERR(CAM_ISP, "invalid outports both RDI2 and PDAF enabled"); + return -EINVAL; + } + + *ipp_count = ipp_num; + *rdi_count = rdi_num; + + CAM_DBG(CAM_ISP, "rdi: %d ipp: %d pdaf:%d", rdi_num, ipp_num, + *pdaf_enable); + + return 0; +} + +static int cam_tfe_mgr_acquire_hw_for_ctx( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info *in_port, + uint32_t *num_pix_port, uint32_t *num_rdi_port, + uint32_t *pdaf_enable) +{ + int rc = -EINVAL; + int is_dual_isp = 0; + int ipp_count = 0; + int rdi_count = 0; + + is_dual_isp = in_port->usage_type; + + cam_tfe_hw_mgr_preprocess_port(tfe_ctx, in_port, &ipp_count, + &rdi_count, pdaf_enable); + + if (!ipp_count && !rdi_count) { + CAM_ERR(CAM_ISP, + "No PIX or RDI"); + return -EINVAL; + } + + if (ipp_count) { + /* get tfe csid IPP resource */ + rc = cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl(tfe_ctx, + in_port); + if (rc) { + CAM_ERR(CAM_ISP, + "Acquire TFE CSID IPP resource Failed dual:%d", + in_port->usage_type); + goto err; + } + } + + if (rdi_count) { + /* get tfe csid rdi resource */ + rc = cam_tfe_hw_mgr_acquire_res_tfe_csid_rdi(tfe_ctx, in_port); + if (rc) { + CAM_ERR(CAM_ISP, + "Acquire TFE CSID RDI resource Failed dual:%d", + in_port->usage_type); + goto err; + } + } + + rc = cam_tfe_hw_mgr_acquire_res_tfe_in(tfe_ctx, in_port, pdaf_enable); + if (rc) { + CAM_ERR(CAM_ISP, + "Acquire TFE IN resource Failed dual:%d", in_port->usage_type); + goto err; + } + + CAM_DBG(CAM_ISP, "Acquiring TFE OUT resource..."); + rc = cam_tfe_hw_mgr_acquire_res_tfe_out(tfe_ctx, in_port); + if (rc) { + CAM_ERR(CAM_ISP, "Acquire TFE OUT resource Failed dual:%d", + in_port->usage_type); + goto err; + } + + *num_pix_port += ipp_count; + *num_rdi_port += rdi_count; + + return 0; +err: + /* release resource at the acquire entry funciton */ + return rc; +} + +void cam_tfe_cam_cdm_callback(uint32_t handle, void *userdata, + enum cam_cdm_cb_status status, uint64_t cookie) +{ + struct cam_isp_prepare_hw_update_data *hw_update_data = NULL; + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + uint32_t *buf_start, *buf_end; + int i, rc = 0; + size_t len = 0; + uint32_t *buf_addr; + + if (!userdata) { + CAM_ERR(CAM_ISP, "Invalid args"); + return; + } + + if (status == CAM_CDM_CB_STATUS_BL_SUCCESS) { + hw_update_data = + (struct cam_isp_prepare_hw_update_data *)userdata; + ctx = + (struct cam_tfe_hw_mgr_ctx *)hw_update_data->isp_mgr_ctx; + complete_all(&ctx->config_done_complete); + atomic_set(&ctx->cdm_done, 1); + if (g_tfe_hw_mgr.debug_cfg.per_req_reg_dump) + cam_tfe_mgr_handle_reg_dump(ctx, + hw_update_data->reg_dump_buf_desc, + hw_update_data->num_reg_dump_buf, + CAM_ISP_TFE_PACKET_META_REG_DUMP_PER_REQUEST, + NULL, false); + CAM_DBG(CAM_ISP, + "Called by CDM hdl=%x, udata=%pK, status=%d, cookie=%llu ctx_index=%d", + handle, userdata, status, cookie, ctx->ctx_index); + } else if (status == CAM_CDM_CB_STATUS_PAGEFAULT || + status == CAM_CDM_CB_STATUS_INVALID_BL_CMD || + status == CAM_CDM_CB_STATUS_HW_ERROR) { + ctx = userdata; + CAM_INFO(CAM_ISP, + "req_id =%d ctx_id =%d Bl_cmd_count =%d status=%d", + ctx->applied_req_id, ctx->ctx_index, + ctx->last_submit_bl_cmd.bl_count, status); + + for (i = 0; i < ctx->last_submit_bl_cmd.bl_count; i++) { + CAM_INFO(CAM_ISP, + "BL(%d) hdl=0x%x addr=0x%x len=%d input_len =%d offset=0x%x type=%d", + i, ctx->last_submit_bl_cmd.cmd[i].mem_handle, + ctx->last_submit_bl_cmd.cmd[i].hw_addr, + ctx->last_submit_bl_cmd.cmd[i].len, + ctx->last_submit_bl_cmd.cmd[i].input_len, + ctx->last_submit_bl_cmd.cmd[i].offset, + ctx->last_submit_bl_cmd.cmd[i].type); + + rc = cam_packet_util_get_cmd_mem_addr( + ctx->last_submit_bl_cmd.cmd[i].mem_handle, + &buf_addr, &len); + + buf_start = (uint32_t *)((uint8_t *) buf_addr + + ctx->last_submit_bl_cmd.cmd[i].offset); + buf_end = (uint32_t *)((uint8_t *) buf_start + + ctx->last_submit_bl_cmd.cmd[i].input_len - 1); + + cam_cdm_util_dump_cmd_buf(buf_start, buf_end); + cam_mem_put_cpu_buf( + ctx->last_submit_bl_cmd.cmd[i].mem_handle); + } + if (ctx->packet != NULL) + cam_packet_dump_patch_info(ctx->packet, + g_tfe_hw_mgr.mgr_common.img_iommu_hdl, + g_tfe_hw_mgr.mgr_common.img_iommu_hdl_secure); + } else { + CAM_WARN(CAM_ISP, + "Called by CDM hdl=%x, udata=%pK, status=%d, cookie=%llu", + handle, userdata, status, cookie); + } +} + +/* entry function: acquire_hw */ +static int cam_tfe_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) +{ + struct cam_tfe_hw_mgr *tfe_hw_mgr = hw_mgr_priv; + struct cam_hw_acquire_args *acquire_args = acquire_hw_args; + int rc = -EINVAL; + int i, j; + struct cam_tfe_hw_mgr_ctx *tfe_ctx; + struct cam_isp_tfe_in_port_info *in_port = NULL; + struct cam_cdm_acquire_data cdm_acquire; + uint32_t num_pix_port_per_in = 0; + uint32_t num_rdi_port_per_in = 0; + uint32_t pdaf_enable = 0; + uint32_t total_pix_port = 0; + uint32_t total_rdi_port = 0; + uint32_t in_port_length = 0; + uint32_t total_in_port_length = 0; + struct cam_isp_tfe_acquire_hw_info *acquire_hw_info = NULL; + struct cam_isp_tfe_in_port_info + *tpg_inport[CAM_TOP_TPG_MAX_SUPPORTED_DT] = {0, 0, 0, 0}; + + CAM_DBG(CAM_ISP, "Enter..."); + + if (!acquire_args || acquire_args->num_acq <= 0) { + CAM_ERR(CAM_ISP, "Nothing to acquire. Seems like error"); + return -EINVAL; + } + + /* get the tfe ctx */ + rc = cam_tfe_hw_mgr_get_ctx(&tfe_hw_mgr->free_ctx_list, &tfe_ctx); + if (rc || !tfe_ctx) { + CAM_ERR(CAM_ISP, "Get tfe hw context failed"); + goto err; + } + + tfe_ctx->common.cb_priv = acquire_args->context_data; + for (i = 0; i < CAM_ISP_HW_EVENT_MAX; i++) + tfe_ctx->common.event_cb[i] = acquire_args->event_cb; + + tfe_ctx->hw_mgr = tfe_hw_mgr; + + memcpy(cdm_acquire.identifier, "tfe", sizeof("tfe")); + cdm_acquire.cell_index = 0; + cdm_acquire.handle = 0; + cdm_acquire.userdata = tfe_ctx; + cdm_acquire.priority = CAM_CDM_BL_FIFO_0; + cdm_acquire.base_array_cnt = CAM_TFE_HW_NUM_MAX; + for (i = 0, j = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (tfe_hw_mgr->cdm_reg_map[i]) + cdm_acquire.base_array[j++] = + tfe_hw_mgr->cdm_reg_map[i]; + } + cdm_acquire.base_array_cnt = j; + + + cdm_acquire.id = CAM_CDM_VIRTUAL; + cdm_acquire.cam_cdm_callback = cam_tfe_cam_cdm_callback; + rc = cam_cdm_acquire(&cdm_acquire); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to acquire the CDM HW"); + goto free_ctx; + } + + CAM_DBG(CAM_ISP, "Successfully acquired the CDM HW hdl=%x", + cdm_acquire.handle); + tfe_ctx->cdm_handle = cdm_acquire.handle; + tfe_ctx->cdm_ops = cdm_acquire.ops; + atomic_set(&tfe_ctx->cdm_done, 1); + + acquire_hw_info = (struct cam_isp_tfe_acquire_hw_info *) + acquire_args->acquire_info; + in_port = (struct cam_isp_tfe_in_port_info *) + ((uint8_t *)&acquire_hw_info->data + + acquire_hw_info->input_info_offset); + + /* Check any inport has dual tfe usage */ + tfe_ctx->is_dual = false; + for (i = 0; i < acquire_hw_info->num_inputs; i++) { + if (in_port->usage_type) + tfe_ctx->is_dual = true; + + in_port_length = + sizeof(struct cam_isp_tfe_in_port_info) + + (in_port->num_out_res - 1) * + sizeof(struct cam_isp_tfe_out_port_info); + total_in_port_length += in_port_length; + if (total_in_port_length > + acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, + "buffer size is not enough %d %d", + total_in_port_length, + acquire_hw_info->input_info_size); + rc = -EINVAL; + goto free_cdm; + } + + in_port = (struct cam_isp_tfe_in_port_info *) + ((uint8_t *)in_port + in_port_length); + } + + in_port_length = 0; + total_in_port_length = 0; + in_port = (struct cam_isp_tfe_in_port_info *) + ((uint8_t *)&acquire_hw_info->data + + acquire_hw_info->input_info_offset); + + if (in_port->res_id == CAM_ISP_TFE_IN_RES_TPG) { + if (acquire_hw_info->num_inputs > + CAM_TOP_TPG_MAX_SUPPORTED_DT) { + CAM_ERR(CAM_ISP, "too many number inport:%d for TPG ", + acquire_hw_info->num_inputs); + rc = -EINVAL; + goto free_cdm; + } + + for (i = 0; i < acquire_hw_info->num_inputs; i++) { + if (in_port->res_id != CAM_ISP_TFE_IN_RES_TPG) { + CAM_ERR(CAM_ISP, "Inval :%d inport res id:0x%x", + i, in_port->res_id); + rc = -EINVAL; + goto free_cdm; + } + + tpg_inport[i] = in_port; + in_port_length = + sizeof(struct cam_isp_tfe_in_port_info) + + (in_port->num_out_res - 1) * + sizeof(struct cam_isp_tfe_out_port_info); + total_in_port_length += in_port_length; + if (total_in_port_length > + acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, + "buffer size is not enough %d %d", + total_in_port_length, + acquire_hw_info->input_info_size); + rc = -EINVAL; + goto free_cdm; + } + + in_port = (struct cam_isp_tfe_in_port_info *) + ((uint8_t *)in_port + in_port_length); + } + + rc = cam_tfe_hw_mgr_acquire_tpg(tfe_ctx, tpg_inport, + acquire_hw_info->num_inputs); + if (rc) + goto free_cdm; + + tfe_ctx->is_tpg = true; + } + + in_port = (struct cam_isp_tfe_in_port_info *) + ((uint8_t *)&acquire_hw_info->data + + acquire_hw_info->input_info_offset); + in_port_length = 0; + total_in_port_length = 0; + + /* acquire HW resources */ + for (i = 0; i < acquire_hw_info->num_inputs; i++) { + + if (in_port->num_out_res > CAM_TFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "too many output res %d", + in_port->num_out_res); + rc = -EINVAL; + goto free_res; + } + + in_port_length = sizeof(struct cam_isp_tfe_in_port_info) + + (in_port->num_out_res - 1) * + sizeof(struct cam_isp_tfe_out_port_info); + total_in_port_length += in_port_length; + + if (total_in_port_length > acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, "buffer size is not enough"); + rc = -EINVAL; + goto free_res; + } + CAM_DBG(CAM_ISP, "in_res_id %x", in_port->res_id); + rc = cam_tfe_mgr_acquire_hw_for_ctx(tfe_ctx, in_port, + &num_pix_port_per_in, &num_rdi_port_per_in, + &pdaf_enable); + total_pix_port += num_pix_port_per_in; + total_rdi_port += num_rdi_port_per_in; + + if (rc) { + CAM_ERR(CAM_ISP, "can not acquire resource"); + goto free_res; + } + in_port = (struct cam_isp_tfe_in_port_info *) + ((uint8_t *)in_port + in_port_length); + } + + /* Check whether context has only RDI resource */ + if (!total_pix_port) { + tfe_ctx->is_rdi_only_context = 1; + CAM_DBG(CAM_ISP, "RDI only context"); + } else + tfe_ctx->is_rdi_only_context = 0; + + /* Process base info */ + rc = cam_tfe_mgr_process_base_info(tfe_ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Process base info failed"); + goto free_res; + } + + acquire_args->ctxt_to_hw_map = tfe_ctx; + tfe_ctx->ctx_in_use = 1; + tfe_ctx->num_reg_dump_buf = 0; + + cam_tfe_hw_mgr_put_ctx(&tfe_hw_mgr->used_ctx_list, &tfe_ctx); + + CAM_DBG(CAM_ISP, "Exit...(success)"); + + return 0; +free_res: + cam_tfe_hw_mgr_release_hw_for_ctx(tfe_ctx); + tfe_ctx->ctx_in_use = 0; + tfe_ctx->is_rdi_only_context = 0; + tfe_ctx->cdm_handle = 0; + tfe_ctx->cdm_ops = NULL; + tfe_ctx->init_done = false; + tfe_ctx->is_dual = false; + tfe_ctx->is_tpg = false; + tfe_ctx->res_list_tpg.res_type = CAM_ISP_RESOURCE_MAX; +free_cdm: + cam_cdm_release(tfe_ctx->cdm_handle); +free_ctx: + cam_tfe_hw_mgr_put_ctx(&tfe_hw_mgr->free_ctx_list, &tfe_ctx); +err: + /* Dump all the current acquired HW */ + cam_tfe_hw_mgr_dump_all_ctx(); + + CAM_ERR_RATE_LIMIT(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; +} + +/* entry function: acquire_hw */ +static int cam_tfe_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) +{ + struct cam_tfe_hw_mgr *tfe_hw_mgr = hw_mgr_priv; + struct cam_hw_acquire_args *acquire_args = acquire_hw_args; + int rc = -EINVAL; + int i, j; + struct cam_tfe_hw_mgr_ctx *tfe_ctx; + struct cam_isp_tfe_in_port_info *in_port = NULL; + struct cam_isp_resource *isp_resource = NULL; + struct cam_cdm_acquire_data cdm_acquire; + uint32_t num_pix_port_per_in = 0; + uint32_t num_rdi_port_per_in = 0; + uint32_t pdad_enable = 0; + uint32_t total_pix_port = 0; + uint32_t total_rdi_port = 0; + uint32_t in_port_length = 0; + + CAM_DBG(CAM_ISP, "Enter..."); + + if (!acquire_args || acquire_args->num_acq <= 0) { + CAM_ERR(CAM_ISP, "Nothing to acquire. Seems like error"); + return -EINVAL; + } + + /* get the tfe ctx */ + rc = cam_tfe_hw_mgr_get_ctx(&tfe_hw_mgr->free_ctx_list, &tfe_ctx); + if (rc || !tfe_ctx) { + CAM_ERR(CAM_ISP, "Get tfe hw context failed"); + goto err; + } + + tfe_ctx->common.cb_priv = acquire_args->context_data; + for (i = 0; i < CAM_ISP_HW_EVENT_MAX; i++) + tfe_ctx->common.event_cb[i] = acquire_args->event_cb; + + tfe_ctx->hw_mgr = tfe_hw_mgr; + + memcpy(cdm_acquire.identifier, "tfe", sizeof("tfe")); + cdm_acquire.cell_index = 0; + cdm_acquire.handle = 0; + cdm_acquire.userdata = tfe_ctx; + cdm_acquire.base_array_cnt = CAM_TFE_HW_NUM_MAX; + for (i = 0, j = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (tfe_hw_mgr->cdm_reg_map[i]) + cdm_acquire.base_array[j++] = + tfe_hw_mgr->cdm_reg_map[i]; + } + cdm_acquire.base_array_cnt = j; + + + cdm_acquire.id = CAM_CDM_VIRTUAL; + cdm_acquire.cam_cdm_callback = cam_tfe_cam_cdm_callback; + rc = cam_cdm_acquire(&cdm_acquire); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to acquire the CDM HW"); + goto free_ctx; + } + + CAM_DBG(CAM_ISP, "Successfully acquired the CDM HW hdl=%x", + cdm_acquire.handle); + tfe_ctx->cdm_handle = cdm_acquire.handle; + tfe_ctx->cdm_ops = cdm_acquire.ops; + atomic_set(&tfe_ctx->cdm_done, 1); + + isp_resource = (struct cam_isp_resource *)acquire_args->acquire_info; + + /* acquire HW resources */ + for (i = 0; i < acquire_args->num_acq; i++) { + if (isp_resource[i].resource_id != CAM_ISP_RES_ID_PORT) + continue; + + CAM_DBG(CAM_ISP, "acquire no = %d total = %d", i, + acquire_args->num_acq); + CAM_DBG(CAM_ISP, + "start copy from user handle %lld with len = %d", + isp_resource[i].res_hdl, + isp_resource[i].length); + + in_port_length = sizeof(struct cam_isp_tfe_in_port_info); + + if (in_port_length > isp_resource[i].length) { + CAM_ERR(CAM_ISP, "buffer size is not enough"); + rc = -EINVAL; + goto free_res; + } + + in_port = memdup_user( + u64_to_user_ptr(isp_resource[i].res_hdl), + isp_resource[i].length); + if (!IS_ERR(in_port)) { + if (in_port->num_out_res > CAM_TFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "too many output res %d", + in_port->num_out_res); + rc = -EINVAL; + kfree(in_port); + goto free_res; + } + + in_port_length = + sizeof(struct cam_isp_tfe_in_port_info) + + (in_port->num_out_res - 1) * + sizeof(struct cam_isp_tfe_out_port_info); + if (in_port_length > isp_resource[i].length) { + CAM_ERR(CAM_ISP, "buffer size is not enough"); + rc = -EINVAL; + kfree(in_port); + goto free_res; + } + + rc = cam_tfe_mgr_acquire_hw_for_ctx(tfe_ctx, in_port, + &num_pix_port_per_in, &num_rdi_port_per_in, + &pdad_enable); + total_pix_port += num_pix_port_per_in; + total_rdi_port += num_rdi_port_per_in; + + kfree(in_port); + if (rc) { + CAM_ERR(CAM_ISP, "can not acquire resource"); + goto free_res; + } + } else { + CAM_ERR(CAM_ISP, + "Copy from user failed with in_port = %pK", + in_port); + rc = -EFAULT; + goto free_res; + } + } + + /* Check whether context has only RDI resource */ + if (!total_pix_port) { + tfe_ctx->is_rdi_only_context = 1; + CAM_DBG(CAM_ISP, "RDI only context"); + } else + tfe_ctx->is_rdi_only_context = 0; + + /* Process base info */ + rc = cam_tfe_mgr_process_base_info(tfe_ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Process base info failed"); + goto free_res; + } + + acquire_args->ctxt_to_hw_map = tfe_ctx; + tfe_ctx->ctx_in_use = 1; + + cam_tfe_hw_mgr_put_ctx(&tfe_hw_mgr->used_ctx_list, &tfe_ctx); + + CAM_DBG(CAM_ISP, "Exit...(success)"); + + return 0; +free_res: + cam_tfe_hw_mgr_release_hw_for_ctx(tfe_ctx); + cam_cdm_release(tfe_ctx->cdm_handle); +free_ctx: + cam_tfe_hw_mgr_put_ctx(&tfe_hw_mgr->free_ctx_list, &tfe_ctx); +err: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; +} + +/* entry function: acquire_hw */ +static int cam_tfe_mgr_acquire(void *hw_mgr_priv, + void *acquire_hw_args) +{ + struct cam_hw_acquire_args *acquire_args = acquire_hw_args; + int rc = -EINVAL; + + CAM_DBG(CAM_ISP, "Enter..."); + + if (!acquire_args || acquire_args->num_acq <= 0) { + CAM_ERR(CAM_ISP, "Nothing to acquire. Seems like error"); + return -EINVAL; + } + + if (acquire_args->num_acq == CAM_API_COMPAT_CONSTANT) + rc = cam_tfe_mgr_acquire_hw(hw_mgr_priv, acquire_hw_args); + else + rc = cam_tfe_mgr_acquire_dev(hw_mgr_priv, acquire_hw_args); + + CAM_DBG(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; +} + +static const char *cam_tfe_util_usage_data_to_string( + uint32_t usage_data) +{ + switch (usage_data) { + case CAM_ISP_TFE_USAGE_LEFT_PX: + return "LEFT_PX"; + case CAM_ISP_TFE_USAGE_RIGHT_PX: + return "RIGHT_PX"; + case CAM_ISP_TFE_USAGE_RDI: + return "RDI"; + default: + return "USAGE_INVALID"; + } +} + +static int cam_tfe_classify_vote_info( + struct cam_isp_hw_mgr_res *hw_mgr_res, + struct cam_isp_bw_config_internal_v2 *bw_config, + struct cam_axi_vote *isp_vote, + uint32_t split_idx, + bool *camif_l_bw_updated, + bool *camif_r_bw_updated) +{ + int rc = 0, i, j = 0; + + if (hw_mgr_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + if (split_idx == CAM_ISP_HW_SPLIT_LEFT) { + if (*camif_l_bw_updated) + return rc; + + for (i = 0; i < bw_config->num_paths; i++) { + if (bw_config->axi_path[i].usage_data == + CAM_ISP_TFE_USAGE_LEFT_PX) { + memcpy(&isp_vote->axi_path[j], + &bw_config->axi_path[i], + sizeof(struct + cam_axi_per_path_bw_vote)); + j++; + } + } + isp_vote->num_paths = j; + + *camif_l_bw_updated = true; + } else { + if (*camif_r_bw_updated) + return rc; + + for (i = 0; i < bw_config->num_paths; i++) { + if (bw_config->axi_path[i].usage_data == + CAM_ISP_TFE_USAGE_RIGHT_PX) { + memcpy(&isp_vote->axi_path[j], + &bw_config->axi_path[i], + sizeof(struct + cam_axi_per_path_bw_vote)); + j++; + } + } + isp_vote->num_paths = j; + + *camif_r_bw_updated = true; + } + } else if ((hw_mgr_res->res_id >= CAM_ISP_HW_TFE_IN_RDI0) + && (hw_mgr_res->res_id <= + CAM_ISP_HW_TFE_IN_RDI2)) { + for (i = 0; i < bw_config->num_paths; i++) { + if ((bw_config->axi_path[i].usage_data == + CAM_ISP_TFE_USAGE_RDI) && + ((bw_config->axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_IFE_RDI0) == + (hw_mgr_res->res_id - + CAM_ISP_HW_TFE_IN_RDI0))) { + memcpy(&isp_vote->axi_path[j], + &bw_config->axi_path[i], + sizeof(struct + cam_axi_per_path_bw_vote)); + j++; + } + } + isp_vote->num_paths = j; + + } else { + if (hw_mgr_res->hw_res[split_idx]) { + CAM_ERR(CAM_ISP, "Invalid res_id %u, split_idx: %u", + hw_mgr_res->res_id, split_idx); + rc = -EINVAL; + return rc; + } + } + + for (i = 0; i < isp_vote->num_paths; i++) { + CAM_DBG(CAM_PERF, + "CLASSIFY_VOTE [%s] [%s] [%s] [%llu] [%llu] [%llu]", + cam_tfe_util_usage_data_to_string( + isp_vote->axi_path[i].usage_data), + cam_cpas_axi_util_path_type_to_string( + isp_vote->axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + isp_vote->axi_path[i].transac_type), + isp_vote->axi_path[i].camnoc_bw, + isp_vote->axi_path[i].mnoc_ab_bw, + isp_vote->axi_path[i].mnoc_ib_bw); + } + + return rc; +} + +static int cam_isp_tfe_blob_bw_update( + struct cam_isp_bw_config_internal_v2 *bw_config, + struct cam_tfe_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_bw_update_args *bw_upd_args = NULL; + int rc = -EINVAL; + uint32_t i, split_idx; + bool camif_l_bw_updated = false; + bool camif_r_bw_updated = false; + + for (i = 0; i < bw_config->num_paths; i++) { + CAM_DBG(CAM_PERF, + "ISP_BLOB usage_type=%u [%s] [%s] [%s] [%llu] [%llu] [%llu]", + bw_config->usage_type, + cam_tfe_util_usage_data_to_string( + bw_config->axi_path[i].usage_data), + cam_cpas_axi_util_path_type_to_string( + bw_config->axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + bw_config->axi_path[i].transac_type), + bw_config->axi_path[i].camnoc_bw, + bw_config->axi_path[i].mnoc_ab_bw, + bw_config->axi_path[i].mnoc_ib_bw); + } + + bw_upd_args = kzalloc(sizeof(struct cam_tfe_bw_update_args), + GFP_KERNEL); + if (!bw_upd_args) { + CAM_ERR(CAM_ISP, "Out of memory"); + return -ENOMEM; + } + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + for (split_idx = 0; split_idx < CAM_ISP_HW_SPLIT_MAX; + split_idx++) { + if (!hw_mgr_res->hw_res[split_idx]) + continue; + + memset(&bw_upd_args->isp_vote, 0, + sizeof(struct cam_axi_vote)); + rc = cam_tfe_classify_vote_info(hw_mgr_res, bw_config, + &bw_upd_args->isp_vote, split_idx, + &camif_l_bw_updated, &camif_r_bw_updated); + if (rc) + goto end; + + if (!bw_upd_args->isp_vote.num_paths) + continue; + + hw_intf = hw_mgr_res->hw_res[split_idx]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + bw_upd_args->node_res = + hw_mgr_res->hw_res[split_idx]; + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_BW_UPDATE_V2, + bw_upd_args, + sizeof( + struct cam_tfe_bw_update_args)); + if (rc) + CAM_ERR(CAM_ISP, + "BW Update failed rc: %d", rc); + } else { + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } + } + } + +end: + kzfree(bw_upd_args); + bw_upd_args = NULL; + return rc; +} + +/* entry function: config_hw */ +static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, + void *config_hw_args) +{ + int rc = -EINVAL, i, skip = 0; + struct cam_hw_config_args *cfg; + struct cam_hw_update_entry *cmd; + struct cam_cdm_bl_request *cdm_cmd; + struct cam_tfe_hw_mgr_ctx *ctx; + struct cam_isp_prepare_hw_update_data *hw_update_data; + + CAM_DBG(CAM_ISP, "Enter"); + if (!hw_mgr_priv || !config_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + cfg = config_hw_args; + ctx = (struct cam_tfe_hw_mgr_ctx *)cfg->ctxt_to_hw_map; + if (!ctx) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + if (!ctx->ctx_in_use || !ctx->cdm_cmd) { + CAM_ERR(CAM_ISP, "Invalid context parameters"); + return -EPERM; + } + if (atomic_read(&ctx->overflow_pending)) + return -EINVAL; + + hw_update_data = (struct cam_isp_prepare_hw_update_data *) cfg->priv; + hw_update_data->isp_mgr_ctx = ctx; + + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (hw_update_data->bw_config_valid[i] == true) { + + CAM_DBG(CAM_ISP, "idx=%d, bw_config_version=%d", + ctx->ctx_index, i, + hw_update_data->bw_config_version); + if (hw_update_data->bw_config_version == + CAM_ISP_BW_CONFIG_V2) { + rc = cam_isp_tfe_blob_bw_update( + &hw_update_data->bw_config_v2[i], ctx); + if (rc) + CAM_ERR(CAM_ISP, + "Bandwidth Update Failed rc: %d", rc); + } else { + CAM_ERR(CAM_ISP, + "Invalid bw config version: %d", + hw_update_data->bw_config_version); + } + } + } + + CAM_DBG(CAM_ISP, + "Enter ctx id:%d num_hw_upd_entries %d request id: %llu", + ctx->ctx_index, cfg->num_hw_update_entries, cfg->request_id); + + if (cfg->num_hw_update_entries <= 0) { + CAM_ERR(CAM_ISP, + "Enter ctx id:%d no valid hw entries:%d request id: %llu", + ctx->ctx_index, cfg->num_hw_update_entries, + cfg->request_id); + goto end; + } + + cdm_cmd = ctx->cdm_cmd; + cdm_cmd->cmd_arrary_count = cfg->num_hw_update_entries; + cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE; + cdm_cmd->flag = true; + cdm_cmd->userdata = hw_update_data; + cdm_cmd->cookie = cfg->request_id; + cdm_cmd->gen_irq_arb = false; + + for (i = 0 ; i < cfg->num_hw_update_entries; i++) { + cmd = (cfg->hw_update_entries + i); + if (cfg->reapply && cmd->flags == CAM_ISP_IQ_BL) { + skip++; + continue; + } + + if (cmd->flags == CAM_ISP_UNUSED_BL || + cmd->flags >= CAM_ISP_BL_MAX) + CAM_ERR(CAM_ISP, "Unexpected BL type %d", + cmd->flags); + + cdm_cmd->cmd[i - skip].bl_addr.mem_handle = cmd->handle; + cdm_cmd->cmd[i - skip].offset = cmd->offset; + cdm_cmd->cmd[i - skip].len = cmd->len; + cdm_cmd->cmd[i - skip].arbitrate = false; + } + cdm_cmd->cmd_arrary_count = cfg->num_hw_update_entries - skip; + + reinit_completion(&ctx->config_done_complete); + ctx->applied_req_id = cfg->request_id; + + CAM_DBG(CAM_ISP, "Submit to CDM"); + atomic_set(&ctx->cdm_done, 0); + rc = cam_cdm_submit_bls(ctx->cdm_handle, cdm_cmd); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to apply the configs"); + return rc; + } + + ctx->packet = (struct cam_packet *)hw_update_data->packet; + ctx->last_submit_bl_cmd.bl_count = cdm_cmd->cmd_arrary_count; + + for (i = 0; i < cdm_cmd->cmd_arrary_count; i++) { + if (cdm_cmd->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) { + ctx->last_submit_bl_cmd.cmd[i].mem_handle = + cdm_cmd->cmd[i].bl_addr.mem_handle; + + rc = cam_mem_get_io_buf( + cdm_cmd->cmd[i].bl_addr.mem_handle, + g_tfe_hw_mgr.mgr_common.cmd_iommu_hdl, + &ctx->last_submit_bl_cmd.cmd[i].hw_addr, + &ctx->last_submit_bl_cmd.cmd[i].len); + } else if (cdm_cmd->type == + CAM_CDM_BL_CMD_TYPE_HW_IOVA) { + if (!cdm_cmd->cmd[i].bl_addr.hw_iova) { + CAM_ERR(CAM_CDM, + "Submitted Hw bl hw_iova is invalid %d:%d", + i, cdm_cmd->cmd_arrary_count); + rc = -EINVAL; + break; + } + rc = 0; + ctx->last_submit_bl_cmd.cmd[i].hw_addr = + (uint64_t)cdm_cmd->cmd[i].bl_addr.hw_iova; + ctx->last_submit_bl_cmd.cmd[i].len = + cdm_cmd->cmd[i].len + cdm_cmd->cmd[i].offset; + ctx->last_submit_bl_cmd.cmd[i].mem_handle = 0; + } else + CAM_INFO(CAM_ISP, + "submitted invalid bl cmd addr type :%d for Bl(%d)", + cdm_cmd->type, i); + + ctx->last_submit_bl_cmd.cmd[i].offset = + cdm_cmd->cmd[i].offset; + ctx->last_submit_bl_cmd.cmd[i].type = + cdm_cmd->type; + ctx->last_submit_bl_cmd.cmd[i].input_len = + cdm_cmd->cmd[i].len; + } + + if (!cfg->init_packet) + goto end; + + for (i = 0; i < CAM_TFE_HW_CONFIG_WAIT_MAX_TRY; i++) { + rc = wait_for_completion_timeout( + &ctx->config_done_complete, + msecs_to_jiffies( + CAM_TFE_HW_CONFIG_TIMEOUT)); + if (rc <= 0) { + if (!cam_cdm_detect_hang_error(ctx->cdm_handle)) { + CAM_ERR(CAM_ISP, + "CDM workqueue delay detected, wait for some more time req_id=%llu rc=%d ctx_index %d", + cfg->request_id, rc, + ctx->ctx_index); + cam_req_mgr_debug_delay_detect(); + trace_cam_delay_detect("CDM", + "CDM workqueue delay detected", + cfg->request_id, ctx->ctx_index, + CAM_DEFAULT_VALUE, + CAM_DEFAULT_VALUE, rc); + continue; + } + + CAM_ERR(CAM_ISP, + "config done completion timeout for req_id=%llu rc=%d ctx_index %d", + cfg->request_id, rc, + ctx->ctx_index); + + cam_req_mgr_debug_delay_detect(); + trace_cam_delay_detect("ISP", + "config done completion timeout", + cfg->request_id, ctx->ctx_index, + CAM_DEFAULT_VALUE, CAM_DEFAULT_VALUE, + rc); + + if (rc == 0) + rc = -ETIMEDOUT; + + goto end; + } else { + rc = 0; + CAM_DBG(CAM_ISP, + "config done Success for req_id=%llu ctx_index %d", + cfg->request_id, ctx->ctx_index); + break; + } + } + + if ((i == CAM_TFE_HW_CONFIG_WAIT_MAX_TRY) && (rc == 0)) + rc = -ETIMEDOUT; + +end: + CAM_DBG(CAM_ISP, "Exit: Config Done: %llu", cfg->request_id); + + return rc; +} + +static int cam_tfe_mgr_stop_hw_in_overflow(void *stop_hw_args) +{ + int rc = 0; + struct cam_hw_stop_args *stop_args = stop_hw_args; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_tfe_hw_mgr_ctx *ctx; + uint32_t i, master_base_idx = 0; + + if (!stop_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + ctx = (struct cam_tfe_hw_mgr_ctx *)stop_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, "Enter...ctx id:%d", + ctx->ctx_index); + + if (!ctx->num_base) { + CAM_ERR(CAM_ISP, "Number of bases are zero"); + return -EINVAL; + } + + /* get master base index first */ + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].split_id == CAM_ISP_HW_SPLIT_LEFT) { + master_base_idx = ctx->base[i].idx; + break; + } + } + + if (i == ctx->num_base) + master_base_idx = ctx->base[0].idx; + + + /* stop the master CSID path first */ + cam_tfe_mgr_csid_stop_hw(ctx, &ctx->res_list_tfe_csid, + master_base_idx, CAM_TFE_CSID_HALT_IMMEDIATELY); + + /* Stop rest of the CSID paths */ + for (i = 0; i < ctx->num_base; i++) { + if (i == master_base_idx) + continue; + + cam_tfe_mgr_csid_stop_hw(ctx, &ctx->res_list_tfe_csid, + ctx->base[i].idx, CAM_TFE_CSID_HALT_IMMEDIATELY); + } + + /* TFE in resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + cam_tfe_hw_mgr_stop_hw_res(hw_mgr_res); + } + + /* TFE out resources */ + for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) + cam_tfe_hw_mgr_stop_hw_res(&ctx->res_list_tfe_out[i]); + + if (ctx->is_tpg) + cam_tfe_hw_mgr_stop_hw_res(&ctx->res_list_tpg); + + /* Stop tasklet for context */ + cam_tasklet_stop(ctx->common.tasklet_info); + CAM_DBG(CAM_ISP, "Exit...ctx id:%d rc :%d", + ctx->ctx_index, rc); + + return rc; +} + +static int cam_tfe_mgr_bw_control(struct cam_tfe_hw_mgr_ctx *ctx, + enum cam_tfe_bw_control_action action) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_bw_control_args bw_ctrl_args; + int rc = -EINVAL; + uint32_t i; + + CAM_DBG(CAM_ISP, "Enter...ctx id:%d", ctx->ctx_index); + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + bw_ctrl_args.node_res = + hw_mgr_res->hw_res[i]; + bw_ctrl_args.action = action; + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_BW_CONTROL, + &bw_ctrl_args, + sizeof(struct cam_tfe_bw_control_args)); + if (rc) + CAM_ERR(CAM_ISP, "BW Update failed"); + } else + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } + } + + return rc; +} + +static int cam_tfe_mgr_pause_hw(struct cam_tfe_hw_mgr_ctx *ctx) +{ + return cam_tfe_mgr_bw_control(ctx, CAM_TFE_BW_CONTROL_EXCLUDE); +} + +/* entry function: stop_hw */ +static int cam_tfe_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) +{ + int rc = 0; + struct cam_hw_stop_args *stop_args = stop_hw_args; + struct cam_isp_stop_args *stop_isp; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_tfe_hw_mgr_ctx *ctx; + enum cam_tfe_csid_halt_cmd csid_halt_type; + uint32_t i, master_base_idx = 0; + + if (!hw_mgr_priv || !stop_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_tfe_hw_mgr_ctx *)stop_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, " Enter...ctx id:%d", ctx->ctx_index); + stop_isp = (struct cam_isp_stop_args *)stop_args->args; + + /* Set the csid halt command */ + if (stop_isp->hw_stop_cmd == CAM_ISP_HW_STOP_AT_FRAME_BOUNDARY) + csid_halt_type = CAM_TFE_CSID_HALT_AT_FRAME_BOUNDARY; + else + csid_halt_type = CAM_TFE_CSID_HALT_IMMEDIATELY; + + /* Note:stop resource will remove the irq mask from the hardware */ + + if (!ctx->num_base) { + CAM_ERR(CAM_ISP, "number of bases are zero"); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Halting CSIDs"); + + /* get master base index first */ + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].split_id == CAM_ISP_HW_SPLIT_LEFT) { + master_base_idx = ctx->base[i].idx; + break; + } + } + + /* + * If Context does not have PIX resources and has only RDI resource + * then take the first base index. + */ + if (i == ctx->num_base) + master_base_idx = ctx->base[0].idx; + CAM_DBG(CAM_ISP, "Stopping master CSID idx %d", master_base_idx); + + /* Stop the master CSID path first */ + cam_tfe_mgr_csid_stop_hw(ctx, &ctx->res_list_tfe_csid, + master_base_idx, csid_halt_type); + + /* stop rest of the CSID paths */ + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].idx == master_base_idx) + continue; + CAM_DBG(CAM_ISP, "Stopping CSID idx %d i %d master %d", + ctx->base[i].idx, i, master_base_idx); + + cam_tfe_mgr_csid_stop_hw(ctx, &ctx->res_list_tfe_csid, + ctx->base[i].idx, csid_halt_type); + } + + CAM_DBG(CAM_ISP, "Going to stop TFE Out"); + + /* TFE out resources */ + for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) + cam_tfe_hw_mgr_stop_hw_res(&ctx->res_list_tfe_out[i]); + + CAM_DBG(CAM_ISP, "Going to stop TFE IN"); + + /* TFE in resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + cam_tfe_hw_mgr_stop_hw_res(hw_mgr_res); + } + + cam_tasklet_stop(ctx->common.tasklet_info); + + cam_tfe_mgr_pause_hw(ctx); + + wait_for_completion(&ctx->config_done_complete); + + if (ctx->is_tpg) + cam_tfe_hw_mgr_stop_hw_res(&ctx->res_list_tpg); + + if (stop_isp->stop_only) + goto end; + + if (cam_cdm_stream_off(ctx->cdm_handle)) + CAM_ERR(CAM_ISP, "CDM stream off failed %d", ctx->cdm_handle); + + cam_tfe_hw_mgr_deinit_hw(ctx); + + CAM_DBG(CAM_ISP, + "Stop success for ctx id:%d rc :%d", ctx->ctx_index, rc); + + mutex_lock(&g_tfe_hw_mgr.ctx_mutex); + atomic_dec_return(&g_tfe_hw_mgr.active_ctx_cnt); + mutex_unlock(&g_tfe_hw_mgr.ctx_mutex); + + for (i = 0; i < ctx->last_submit_bl_cmd.bl_count; i++) { + ctx->last_submit_bl_cmd.cmd[i].mem_handle = 0; + ctx->last_submit_bl_cmd.cmd[i].hw_addr = 0; + ctx->last_submit_bl_cmd.cmd[i].len = 0; + ctx->last_submit_bl_cmd.cmd[i].offset = 0; + ctx->last_submit_bl_cmd.cmd[i].type = 0; + ctx->last_submit_bl_cmd.cmd[i].input_len = 0; + } + ctx->last_submit_bl_cmd.bl_count = 0; + ctx->packet = NULL; + +end: + return rc; +} + +static int cam_tfe_mgr_reset_tfe_hw(struct cam_tfe_hw_mgr *hw_mgr, + uint32_t hw_idx) +{ + uint32_t i = 0; + struct cam_hw_intf *tfe_hw_intf; + uint32_t tfe_reset_type; + + if (!hw_mgr) { + CAM_DBG(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + /* Reset TFE HW*/ + tfe_reset_type = CAM_TFE_HW_RESET_HW; + + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (!hw_mgr->tfe_devices[i]) + continue; + + if (hw_idx != hw_mgr->tfe_devices[i]->hw_idx) + continue; + CAM_DBG(CAM_ISP, "TFE (id = %d) reset", hw_idx); + tfe_hw_intf = hw_mgr->tfe_devices[i]; + tfe_hw_intf->hw_ops.reset(tfe_hw_intf->hw_priv, + &tfe_reset_type, sizeof(tfe_reset_type)); + break; + } + + CAM_DBG(CAM_ISP, "Exit Successfully"); + return 0; +} + +static int cam_tfe_mgr_restart_hw(void *start_hw_args) +{ + int rc = -EINVAL; + struct cam_hw_start_args *start_args = start_hw_args; + struct cam_tfe_hw_mgr_ctx *ctx; + struct cam_isp_hw_mgr_res *hw_mgr_res; + uint32_t i; + + if (!start_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_tfe_hw_mgr_ctx *)start_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, "START TFE OUT ... in ctx id:%d", ctx->ctx_index); + + cam_tasklet_start(ctx->common.tasklet_info); + + /* start the TFE out devices */ + for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) { + rc = cam_tfe_hw_mgr_start_hw_res( + &ctx->res_list_tfe_out[i], ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE OUT (%d)", i); + goto err; + } + } + + CAM_DBG(CAM_ISP, "START TFE SRC ... in ctx id:%d", ctx->ctx_index); + + /* Start the TFE in devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + rc = cam_tfe_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE IN (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + CAM_DBG(CAM_ISP, "START CSID HW ... in ctx id:%d", ctx->ctx_index); + /* Start the TFE CSID HW devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + rc = cam_tfe_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE CSID (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + CAM_DBG(CAM_ISP, "Exit...(success)"); + return 0; + +err: + cam_tfe_mgr_stop_hw_in_overflow(start_hw_args); + CAM_DBG(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; +} + +static int cam_tfe_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) +{ + int rc = -EINVAL; + struct cam_isp_start_args *start_isp = start_hw_args; + struct cam_hw_stop_args stop_args; + struct cam_isp_stop_args stop_isp; + struct cam_tfe_hw_mgr_ctx *ctx; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *rsrc_node = NULL; + uint32_t i, camif_debug; + bool res_rdi_context_set = false; + uint32_t primary_rdi_in_res; + uint32_t primary_rdi_out_res; + + primary_rdi_in_res = CAM_ISP_HW_TFE_IN_MAX; + primary_rdi_out_res = CAM_ISP_TFE_OUT_RES_MAX; + + if (!hw_mgr_priv || !start_isp) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_tfe_hw_mgr_ctx *) + start_isp->hw_config.ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + if ((!ctx->init_done) && start_isp->start_only) { + CAM_ERR(CAM_ISP, "Invalid args init_done %d start_only %d", + ctx->init_done, start_isp->start_only); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Enter... ctx id:%d", + ctx->ctx_index); + + /* update Bandwidth should be done at the hw layer */ + + cam_tasklet_start(ctx->common.tasklet_info); + + if (ctx->init_done && start_isp->start_only) + goto start_only; + + /* set current csid debug information to CSID HW */ + for (i = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { + if (g_tfe_hw_mgr.csid_devices[i]) + rc = g_tfe_hw_mgr.csid_devices[i]->hw_ops.process_cmd( + g_tfe_hw_mgr.csid_devices[i]->hw_priv, + CAM_TFE_CSID_SET_CSID_DEBUG, + &g_tfe_hw_mgr.debug_cfg.csid_debug, + sizeof(g_tfe_hw_mgr.debug_cfg.csid_debug)); + } + + /* set tpg debug information for top tpg */ + for (i = 0; i < CAM_TOP_TPG_HW_NUM_MAX; i++) { + if (g_tfe_hw_mgr.tpg_devices[i]) { + rc = g_tfe_hw_mgr.tpg_devices[i]->hw_ops.process_cmd( + g_tfe_hw_mgr.tpg_devices[i]->hw_priv, + CAM_ISP_HW_CMD_TPG_SET_PATTERN, + &g_tfe_hw_mgr.debug_cfg.set_tpg_pattern, + sizeof(g_tfe_hw_mgr.debug_cfg.set_tpg_pattern)); + } + } + + camif_debug = g_tfe_hw_mgr.debug_cfg.camif_debug; + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + rsrc_node = hw_mgr_res->hw_res[i]; + if (rsrc_node->process_cmd && (rsrc_node->res_id == + CAM_ISP_HW_TFE_IN_CAMIF)) { + rc = hw_mgr_res->hw_res[i]->process_cmd( + hw_mgr_res->hw_res[i], + CAM_ISP_HW_CMD_SET_CAMIF_DEBUG, + &camif_debug, + sizeof(camif_debug)); + } + } + } + + rc = cam_tfe_hw_mgr_init_hw(ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Init failed"); + goto tasklet_stop; + } + + ctx->init_done = true; + + mutex_lock(&g_tfe_hw_mgr.ctx_mutex); + atomic_fetch_inc(&g_tfe_hw_mgr.active_ctx_cnt); + mutex_unlock(&g_tfe_hw_mgr.ctx_mutex); + + CAM_DBG(CAM_ISP, "start cdm interface"); + rc = cam_cdm_stream_on(ctx->cdm_handle); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start cdm (%d)", + ctx->cdm_handle); + goto deinit_hw; + } + +start_only: + /* Apply initial configuration */ + CAM_DBG(CAM_ISP, "Config HW"); + rc = cam_tfe_mgr_config_hw(hw_mgr_priv, &start_isp->hw_config); + if (rc) { + CAM_ERR(CAM_ISP, "Config HW failed"); + goto cdm_streamoff; + } + + CAM_DBG(CAM_ISP, "START TFE OUT ... in ctx id:%d", + ctx->ctx_index); + /* start the TFE out devices */ + for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) { + hw_mgr_res = &ctx->res_list_tfe_out[i]; + switch (hw_mgr_res->res_id) { + case CAM_ISP_TFE_OUT_RES_RDI_0: + case CAM_ISP_TFE_OUT_RES_RDI_1: + case CAM_ISP_TFE_OUT_RES_RDI_2: + if (!res_rdi_context_set && ctx->is_rdi_only_context) { + hw_mgr_res->hw_res[0]->rdi_only_ctx = + ctx->is_rdi_only_context; + res_rdi_context_set = true; + primary_rdi_out_res = hw_mgr_res->res_id; + } + } + + rc = cam_tfe_hw_mgr_start_hw_res( + &ctx->res_list_tfe_out[i], ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE OUT (%d)", + i); + goto err; + } + } + + if (primary_rdi_out_res < CAM_ISP_TFE_OUT_RES_MAX) + primary_rdi_in_res = + cam_tfe_hw_mgr_convert_rdi_out_res_id_to_in_res( + primary_rdi_out_res); + + CAM_DBG(CAM_ISP, "START TFE IN ... in ctx id:%d", + ctx->ctx_index); + /* Start the TFE in resources devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + /* + * if rdi only context has two rdi resources then only one irq + * subscription should be sufficient + */ + if (primary_rdi_in_res == hw_mgr_res->res_id) + hw_mgr_res->hw_res[0]->rdi_only_ctx = + ctx->is_rdi_only_context; + + rc = cam_tfe_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE in resource (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + CAM_DBG(CAM_ISP, "START CSID HW ... in ctx id:%d", + ctx->ctx_index); + /* Start the TFE CSID HW devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + rc = cam_tfe_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE CSID (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + if (ctx->is_tpg) { + CAM_DBG(CAM_ISP, "START TPG HW ... in ctx id:%d", + ctx->ctx_index); + rc = cam_tfe_hw_mgr_start_hw_res(&ctx->res_list_tpg, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE TPG (%d)", + ctx->res_list_tpg.res_id); + goto err; + } + } + + return 0; + +err: + stop_isp.stop_only = false; + stop_isp.hw_stop_cmd = CAM_ISP_HW_STOP_IMMEDIATELY; + stop_args.ctxt_to_hw_map = start_isp->hw_config.ctxt_to_hw_map; + stop_args.args = (void *)(&stop_isp); + + cam_tfe_mgr_stop_hw(hw_mgr_priv, &stop_args); + CAM_DBG(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; + +cdm_streamoff: + cam_cdm_stream_off(ctx->cdm_handle); + +deinit_hw: + cam_tfe_hw_mgr_deinit_hw(ctx); + +tasklet_stop: + cam_tasklet_stop(ctx->common.tasklet_info); + + return rc; +} + +static int cam_tfe_mgr_read(void *hw_mgr_priv, void *read_args) +{ + return -EPERM; +} + +static int cam_tfe_mgr_write(void *hw_mgr_priv, void *write_args) +{ + return -EPERM; +} + +static int cam_tfe_mgr_user_dump_hw( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_hw_dump_args *dump_args) +{ + int rc = 0; + struct cam_hw_soc_dump_args soc_dump_args; + + if (!tfe_ctx || !dump_args) { + CAM_ERR(CAM_ISP, "Invalid parameters %pK %pK", + tfe_ctx, dump_args); + return -EINVAL; + } + soc_dump_args.buf_handle = dump_args->buf_handle; + soc_dump_args.request_id = dump_args->request_id; + soc_dump_args.offset = dump_args->offset; + + rc = cam_tfe_mgr_handle_reg_dump(tfe_ctx, + tfe_ctx->reg_dump_buf_desc, + tfe_ctx->num_reg_dump_buf, + CAM_ISP_PACKET_META_REG_DUMP_ON_ERROR, + &soc_dump_args, + true); + if (rc) { + CAM_DBG(CAM_ISP, + "Dump failed req: %lld handle %u offset %u rc %d", + dump_args->request_id, + dump_args->buf_handle, + dump_args->offset, + rc); + return rc; + } + dump_args->offset = soc_dump_args.offset; + return rc; +} + +static int cam_tfe_mgr_dump(void *hw_mgr_priv, void *args) +{ + + struct cam_isp_hw_dump_args isp_hw_dump_args; + struct cam_hw_dump_args *dump_args = (struct cam_hw_dump_args *)args; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_hw_mgr_ctx *tfe_ctx = (struct cam_tfe_hw_mgr_ctx *) + dump_args->ctxt_to_hw_map; + int i; + int rc = 0; + + /* for some targets, information about the TFE registers to be dumped + * is already submitted with the hw manager. In this case, we + * can dump just the related registers and skip going to core files. + * If dump to this buffer falis due to any reason, fallback to dump + * to the LDAR buffer + */ + isp_hw_dump_args.is_dump_all = true; + if (tfe_ctx->num_reg_dump_buf) { + rc = cam_tfe_mgr_user_dump_hw(tfe_ctx, dump_args); + if (!rc) + isp_hw_dump_args.is_dump_all = false; + } + + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &isp_hw_dump_args.cpu_addr, + &isp_hw_dump_args.buf_len); + + if (rc) { + CAM_ERR(CAM_ISP, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + return rc; + } + + isp_hw_dump_args.offset = dump_args->offset; + isp_hw_dump_args.req_id = dump_args->request_id; + + list_for_each_entry(hw_mgr_res, &tfe_ctx->res_list_tfe_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + switch (hw_mgr_res->hw_res[i]->res_id) { + case CAM_TFE_CSID_PATH_RES_RDI_0: + case CAM_TFE_CSID_PATH_RES_RDI_1: + case CAM_TFE_CSID_PATH_RES_RDI_2: + if (tfe_ctx->is_rdi_only_context && + hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + + case CAM_TFE_CSID_PATH_RES_IPP: + if (hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + default: + CAM_DBG(CAM_ISP, "not a valid res %d", + hw_mgr_res->res_id); + break; + } + } + } + + list_for_each_entry(hw_mgr_res, &tfe_ctx->res_list_tfe_in, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + switch (hw_mgr_res->hw_res[i]->res_id) { + case CAM_ISP_HW_TFE_IN_RDI0: + case CAM_ISP_HW_TFE_IN_RDI1: + case CAM_ISP_HW_TFE_IN_RDI2: + if (tfe_ctx->is_rdi_only_context && + hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + + case CAM_ISP_HW_TFE_IN_CAMIF: + if (hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + default: + CAM_DBG(CAM_ISP, "not a valid res %d", + hw_mgr_res->res_id); + break; + } + } + } + dump_args->offset = isp_hw_dump_args.offset; + CAM_DBG(CAM_ISP, "offset %u", dump_args->offset); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return rc; +} + +static int cam_tfe_mgr_reset(void *hw_mgr_priv, void *hw_reset_args) +{ + struct cam_tfe_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_reset_args *reset_args = hw_reset_args; + struct cam_tfe_hw_mgr_ctx *ctx; + struct cam_isp_hw_mgr_res *hw_mgr_res; + int rc = 0, i = 0; + + if (!hw_mgr_priv || !hw_reset_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_tfe_hw_mgr_ctx *)reset_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, "Reset CSID and TFE"); + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + rc = cam_tfe_hw_mgr_reset_csid_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to reset CSID:%d rc: %d", + hw_mgr_res->res_id, rc); + goto end; + } + } + + for (i = 0; i < ctx->num_base; i++) { + rc = cam_tfe_mgr_reset_tfe_hw(hw_mgr, ctx->base[i].idx); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to reset TFE:%d rc: %d", + ctx->base[i].idx, rc); + goto end; + } + } + + atomic_set(&ctx->overflow_pending, 0); +end: + return rc; +} + +static int cam_tfe_mgr_release_hw(void *hw_mgr_priv, + void *release_hw_args) +{ + int rc = 0; + struct cam_hw_release_args *release_args = release_hw_args; + struct cam_tfe_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_tfe_hw_mgr_ctx *ctx; + uint32_t i; + + if (!hw_mgr_priv || !release_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_tfe_hw_mgr_ctx *)release_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, "Enter...ctx id:%d", + ctx->ctx_index); + + if (ctx->init_done) + cam_tfe_hw_mgr_deinit_hw(ctx); + + /* we should called the stop hw before this already */ + cam_tfe_hw_mgr_release_hw_for_ctx(ctx); + + /* reset base info */ + ctx->num_base = 0; + memset(ctx->base, 0, sizeof(ctx->base)); + + /* release cdm handle */ + cam_cdm_release(ctx->cdm_handle); + + /* clean context */ + list_del_init(&ctx->list); + ctx->ctx_in_use = 0; + ctx->is_rdi_only_context = 0; + ctx->cdm_handle = 0; + ctx->cdm_ops = NULL; + ctx->init_done = false; + ctx->is_dual = false; + ctx->is_tpg = false; + ctx->num_reg_dump_buf = 0; + ctx->res_list_tpg.res_type = CAM_ISP_RESOURCE_MAX; + atomic_set(&ctx->overflow_pending, 0); + + for (i = 0; i < ctx->last_submit_bl_cmd.bl_count; i++) { + ctx->last_submit_bl_cmd.cmd[i].mem_handle = 0; + ctx->last_submit_bl_cmd.cmd[i].hw_addr = 0; + ctx->last_submit_bl_cmd.cmd[i].len = 0; + ctx->last_submit_bl_cmd.cmd[i].offset = 0; + ctx->last_submit_bl_cmd.cmd[i].type = 0; + ctx->last_submit_bl_cmd.cmd[i].input_len = 0; + } + ctx->last_submit_bl_cmd.bl_count = 0; + ctx->packet = NULL; + + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + ctx->sof_cnt[i] = 0; + ctx->eof_cnt[i] = 0; + ctx->epoch_cnt[i] = 0; + } + CAM_DBG(CAM_ISP, "Exit...ctx id:%d", + ctx->ctx_index); + cam_tfe_hw_mgr_put_ctx(&hw_mgr->free_ctx_list, &ctx); + return rc; +} + + +static int cam_isp_tfe_blob_hfr_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_tfe_resource_hfr_config *hfr_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_isp_tfe_port_hfr_config *port_hfr_config; + struct cam_kmd_buf_info *kmd_buf_info; + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + uint32_t res_id_out, i; + uint32_t total_used_bytes = 0; + uint32_t kmd_buf_remain_size; + uint32_t *cmd_buf_addr; + uint32_t bytes_used = 0; + int num_ent, rc = 0; + + ctx = prepare->ctxt_to_hw_map; + CAM_DBG(CAM_ISP, "num_ports= %d", hfr_config->num_ports); + + /* Max one hw entries required for hfr config update */ + if (prepare->num_hw_update_entries + 1 >= + prepare->max_hw_update_entries) { + CAM_ERR(CAM_ISP, "Insufficient HW entries :%d %d", + prepare->num_hw_update_entries, + prepare->max_hw_update_entries); + return -EINVAL; + } + + kmd_buf_info = blob_info->kmd_buf_info; + for (i = 0; i < hfr_config->num_ports; i++) { + port_hfr_config = &hfr_config->port_hfr_config[i]; + res_id_out = port_hfr_config->resource_type & 0xFF; + + CAM_DBG(CAM_ISP, "hfr config idx %d, type=%d", i, + res_id_out); + + if (res_id_out >= CAM_TFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "invalid out restype:%x", + port_hfr_config->resource_type); + return -EINVAL; + } + + if ((kmd_buf_info->used_bytes + + total_used_bytes) < kmd_buf_info->size) { + kmd_buf_remain_size = kmd_buf_info->size - + (kmd_buf_info->used_bytes + + total_used_bytes); + } else { + CAM_ERR(CAM_ISP, + "no free kmd memory for base %d", + blob_info->base_info->idx); + rc = -ENOMEM; + return rc; + } + + cmd_buf_addr = kmd_buf_info->cpu_addr + + kmd_buf_info->used_bytes/4 + + total_used_bytes/4; + hw_mgr_res = &ctx->res_list_tfe_out[res_id_out]; + + rc = cam_isp_add_cmd_buf_update( + hw_mgr_res, blob_type, CAM_ISP_HW_CMD_GET_HFR_UPDATE, + blob_info->base_info->idx, + (void *)cmd_buf_addr, + kmd_buf_remain_size, + (void *)port_hfr_config, + &bytes_used); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Failed cmd_update, base_idx=%d, rc=%d", + blob_info->base_info->idx, bytes_used); + return rc; + } + + total_used_bytes += bytes_used; + } + + if (total_used_bytes) { + /* Update the HW entries */ + num_ent = prepare->num_hw_update_entries; + prepare->hw_update_entries[num_ent].handle = + kmd_buf_info->handle; + prepare->hw_update_entries[num_ent].len = total_used_bytes; + prepare->hw_update_entries[num_ent].offset = + kmd_buf_info->offset; + num_ent++; + + kmd_buf_info->used_bytes += total_used_bytes; + kmd_buf_info->offset += total_used_bytes; + prepare->num_hw_update_entries = num_ent; + } + + return rc; +} + +static int cam_isp_tfe_blob_csid_clock_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_tfe_csid_clock_config *clock_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_csid_clock_update_args csid_clock_upd_args; + struct cam_top_tpg_clock_update_args tpg_clock_upd_args; + uint64_t clk_rate = 0; + int rc = -EINVAL; + uint32_t i; + + ctx = prepare->ctxt_to_hw_map; + + CAM_DBG(CAM_ISP, "csid clk=%llu", clock_config->csid_clock); + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + clk_rate = 0; + if (!hw_mgr_res->hw_res[i]) + continue; + clk_rate = clock_config->csid_clock; + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + csid_clock_upd_args.clk_rate = clk_rate; + CAM_DBG(CAM_ISP, "i= %d csid clk=%llu", + i, csid_clock_upd_args.clk_rate); + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_CSID_CLOCK_UPDATE, + &csid_clock_upd_args, + sizeof( + struct cam_tfe_csid_clock_update_args)); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update failed"); + } else + CAM_ERR(CAM_ISP, "NULL hw_intf!"); + } + } + + if (ctx->res_list_tpg.res_type == CAM_ISP_RESOURCE_TPG) { + tpg_clock_upd_args.clk_rate = clock_config->phy_clock; + hw_intf = ctx->res_list_tpg.hw_res[0]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + CAM_DBG(CAM_ISP, "i= %d phy clk=%llu", + tpg_clock_upd_args.clk_rate); + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_TPG_PHY_CLOCK_UPDATE, + &tpg_clock_upd_args, + sizeof(struct cam_top_tpg_clock_update_args)); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update failed"); + } else + CAM_ERR(CAM_ISP, "NULL hw_intf!"); + } + + return rc; +} + +static int cam_isp_tfe_blob_clock_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_tfe_clock_config *clock_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_clock_update_args clock_upd_args; + uint64_t clk_rate = 0; + int rc = -EINVAL; + uint32_t i; + uint32_t j; + bool camif_l_clk_updated = false; + bool camif_r_clk_updated = false; + + ctx = prepare->ctxt_to_hw_map; + + CAM_DBG(CAM_PERF, + "usage=%u left_clk= %lu right_clk=%lu", + clock_config->usage_type, + clock_config->left_pix_hz, + clock_config->right_pix_hz); + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + clk_rate = 0; + if (!hw_mgr_res->hw_res[i]) + continue; + + if (hw_mgr_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + if (i == CAM_ISP_HW_SPLIT_LEFT) { + if (camif_l_clk_updated) + continue; + + clk_rate = + clock_config->left_pix_hz; + + camif_l_clk_updated = true; + } else { + if (camif_r_clk_updated) + continue; + + clk_rate = + clock_config->right_pix_hz; + + camif_r_clk_updated = true; + } + } else if ((hw_mgr_res->res_id >= + CAM_ISP_HW_TFE_IN_RDI0) && (hw_mgr_res->res_id + <= CAM_ISP_HW_TFE_IN_RDI2)) { + for (j = 0; j < clock_config->num_rdi; j++) + clk_rate = max(clock_config->rdi_hz[j], + clk_rate); + } else { + CAM_ERR(CAM_ISP, "Invalid res_id %u", + hw_mgr_res->res_id); + rc = -EINVAL; + return rc; + } + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + clock_upd_args.node_res = + hw_mgr_res->hw_res[i]; + CAM_DBG(CAM_ISP, + "res_id=%u i= %d clk=%llu", + hw_mgr_res->res_id, i, clk_rate); + + clock_upd_args.clk_rate = clk_rate; + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_CLOCK_UPDATE, + &clock_upd_args, + sizeof( + struct cam_tfe_clock_update_args)); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update failed"); + } else + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } + } + + return rc; +} + +static int cam_isp_tfe_packet_generic_blob_handler(void *user_data, + uint32_t blob_type, uint32_t blob_size, uint8_t *blob_data) +{ + int rc = 0; + struct cam_isp_generic_blob_info *blob_info = user_data; + struct cam_hw_prepare_update_args *prepare = NULL; + + if (!blob_data || (blob_size == 0) || !blob_info) { + CAM_ERR(CAM_ISP, "Invalid args data %pK size %d info %pK", + blob_data, blob_size, blob_info); + return -EINVAL; + } + + prepare = blob_info->prepare; + if (!prepare) { + CAM_ERR(CAM_ISP, "Failed. prepare is NULL, blob_type %d", + blob_type); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "BLOB Type: %d", blob_type); + switch (blob_type) { + case CAM_ISP_TFE_GENERIC_BLOB_TYPE_HFR_CONFIG: { + struct cam_isp_tfe_resource_hfr_config *hfr_config = + (struct cam_isp_tfe_resource_hfr_config *)blob_data; + + if (blob_size < + sizeof(struct cam_isp_tfe_resource_hfr_config)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u", blob_size); + return -EINVAL; + } + + if (hfr_config->num_ports > CAM_ISP_TFE_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "Invalid num_ports %u in hfr config", + hfr_config->num_ports); + return -EINVAL; + } + + /* Check for integer overflow */ + if (hfr_config->num_ports > 1) { + if (sizeof(struct cam_isp_tfe_resource_hfr_config) > + ((UINT_MAX - + sizeof(struct cam_isp_tfe_resource_hfr_config)) + / (hfr_config->num_ports - 1))) { + CAM_ERR(CAM_ISP, + "Max size exceeded in hfr config num_ports:%u size per port:%lu", + hfr_config->num_ports, + sizeof(struct + cam_isp_tfe_resource_hfr_config)); + return -EINVAL; + } + } + + if ((hfr_config->num_ports != 0) && (blob_size < + (sizeof(struct cam_isp_tfe_resource_hfr_config) + + (hfr_config->num_ports - 1) * + sizeof(struct cam_isp_tfe_port_hfr_config)))) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, + sizeof(struct cam_isp_tfe_resource_hfr_config) + + (hfr_config->num_ports - 1) * + sizeof(struct cam_isp_tfe_resource_hfr_config)); + return -EINVAL; + } + + rc = cam_isp_tfe_blob_hfr_update(blob_type, blob_info, + hfr_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "HFR Update Failed"); + } + break; + case CAM_ISP_TFE_GENERIC_BLOB_TYPE_CLOCK_CONFIG: { + struct cam_isp_tfe_clock_config *clock_config = + (struct cam_isp_tfe_clock_config *)blob_data; + + if (blob_size < sizeof(struct cam_isp_tfe_clock_config)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u", blob_size); + return -EINVAL; + } + + if (clock_config->num_rdi > CAM_TFE_RDI_NUM_MAX) { + CAM_ERR(CAM_ISP, "Invalid num_rdi %u in clock config", + clock_config->num_rdi); + return -EINVAL; + } + /* Check integer overflow */ + if (clock_config->num_rdi > 1) { + if (sizeof(uint64_t) > ((UINT_MAX- + sizeof(struct cam_isp_tfe_clock_config))/ + (clock_config->num_rdi - 1))) { + CAM_ERR(CAM_ISP, + "Max size exceeded in clock config num_rdi:%u size per port:%lu", + clock_config->num_rdi, + sizeof(uint64_t)); + return -EINVAL; + } + } + + if ((clock_config->num_rdi != 0) && (blob_size < + (sizeof(struct cam_isp_tfe_clock_config) + + sizeof(uint64_t) * (clock_config->num_rdi - 1)))) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, + sizeof(uint32_t) * 2 + sizeof(uint64_t) * + (clock_config->num_rdi + 2)); + return -EINVAL; + } + + rc = cam_isp_tfe_blob_clock_update(blob_type, blob_info, + clock_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update Failed"); + } + break; + case CAM_ISP_TFE_GENERIC_BLOB_TYPE_BW_CONFIG_V2: { + size_t bw_config_size = 0; + struct cam_isp_tfe_bw_config_v2 *bw_config = + (struct cam_isp_tfe_bw_config_v2 *)blob_data; + struct cam_isp_prepare_hw_update_data *prepare_hw_data; + + if (blob_size < sizeof(struct cam_isp_tfe_bw_config_v2)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u", blob_size); + return -EINVAL; + } + + if ((bw_config->num_paths > CAM_ISP_MAX_PER_PATH_VOTES) || + !bw_config->num_paths) { + CAM_ERR(CAM_ISP, "Invalid num paths %d", + bw_config->num_paths); + return -EINVAL; + } + + /* Check for integer overflow */ + if (bw_config->num_paths > 1) { + if (sizeof(struct cam_axi_per_path_bw_vote) > + ((UINT_MAX - + sizeof(struct cam_isp_tfe_bw_config_v2)) / + (bw_config->num_paths - 1))) { + CAM_ERR(CAM_ISP, + "Size exceeds limit paths:%u size per path:%lu", + bw_config->num_paths - 1, + sizeof( + struct cam_axi_per_path_bw_vote)); + return -EINVAL; + } + } + + if ((bw_config->num_paths != 0) && (blob_size < + (sizeof(struct cam_isp_tfe_bw_config_v2) + + ((bw_config->num_paths - 1) * + sizeof(struct cam_axi_per_path_bw_vote))))) { + CAM_ERR(CAM_ISP, + "Invalid blob size: %u, num_paths: %u, bw_config size: %lu, per_path_vote size: %lu", + blob_size, bw_config->num_paths, + sizeof(struct cam_isp_tfe_bw_config_v2), + sizeof(struct cam_axi_per_path_bw_vote)); + return -EINVAL; + } + + if (!prepare || !prepare->priv || + (bw_config->usage_type >= CAM_TFE_HW_NUM_MAX)) { + CAM_ERR(CAM_ISP, "Invalid inputs"); + return -EINVAL; + } + + prepare_hw_data = (struct cam_isp_prepare_hw_update_data *) + prepare->priv; + + memset(&prepare_hw_data->bw_config_v2[bw_config->usage_type], + 0, sizeof( + prepare_hw_data->bw_config_v2[bw_config->usage_type])); + bw_config_size = sizeof(struct cam_isp_tfe_bw_config_v2) + + ((bw_config->num_paths - 1) * + sizeof(struct cam_axi_per_path_bw_vote)); + memcpy(&prepare_hw_data->bw_config_v2[bw_config->usage_type], + bw_config, bw_config_size); + + prepare_hw_data->bw_config_version = CAM_ISP_BW_CONFIG_V2; + prepare_hw_data->bw_config_valid[bw_config->usage_type] = true; + } + + break; + case CAM_ISP_TFE_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG: { + struct cam_isp_tfe_csid_clock_config *clock_config = + (struct cam_isp_tfe_csid_clock_config *)blob_data; + + if (blob_size < sizeof(struct cam_isp_tfe_csid_clock_config)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %u", + blob_size, + sizeof(struct cam_isp_tfe_csid_clock_config)); + return -EINVAL; + } + rc = cam_isp_tfe_blob_csid_clock_update(blob_type, blob_info, + clock_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update Failed"); + } + break; + default: + CAM_WARN(CAM_ISP, "Invalid blob type %d", blob_type); + break; + } + + return rc; +} + +static int cam_tfe_update_dual_config( + struct cam_hw_prepare_update_args *prepare, + struct cam_cmd_buf_desc *cmd_desc, + uint32_t split_id, + uint32_t base_idx, + struct cam_isp_hw_mgr_res *res_list_isp_out, + uint32_t size_isp_out) +{ + int rc = -EINVAL; + struct cam_isp_tfe_dual_config *dual_config; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *res; + struct cam_tfe_dual_update_args dual_isp_update_args; + uint32_t outport_id; + size_t len = 0, remain_len = 0; + uint32_t *cpu_addr; + uint32_t i, j, stp_index; + + CAM_DBG(CAM_ISP, "cmd des size %d, length: %d", + cmd_desc->size, cmd_desc->length); + + rc = cam_packet_util_get_cmd_mem_addr( + cmd_desc->mem_handle, &cpu_addr, &len); + if (rc) { + CAM_DBG(CAM_ISP, "unable to get cmd mem addr handle:0x%x", + cmd_desc->mem_handle); + return rc; + } + + if ((len < sizeof(struct cam_isp_tfe_dual_config)) || + (cmd_desc->offset >= + (len - sizeof(struct cam_isp_tfe_dual_config)))) { + CAM_ERR(CAM_ISP, "not enough buffer provided"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + return -EINVAL; + } + + remain_len = len - cmd_desc->offset; + cpu_addr += (cmd_desc->offset / 4); + dual_config = (struct cam_isp_tfe_dual_config *)cpu_addr; + + if ((dual_config->num_ports * + sizeof(struct cam_isp_tfe_dual_stripe_config)) > + (remain_len - + offsetof(struct cam_isp_tfe_dual_config, stripes))) { + CAM_ERR(CAM_ISP, "not enough buffer for all the dual configs"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "num_ports:%d", dual_config->num_ports); + if (dual_config->num_ports >= size_isp_out) { + CAM_ERR(CAM_UTIL, + "inval num ports %d max num tfe ports:%d", + dual_config->num_ports, size_isp_out); + rc = -EINVAL; + goto end; + } + + for (i = 0; i < dual_config->num_ports; i++) { + for (j = 0; j < CAM_ISP_HW_SPLIT_MAX; j++) { + stp_index = (i * CAM_PACKET_MAX_PLANES) + + (j * (CAM_PACKET_MAX_PLANES * + dual_config->num_ports)); + + if (!dual_config->stripes[stp_index].port_id) + continue; + + outport_id = dual_config->stripes[stp_index].port_id; + if (outport_id >= size_isp_out) { + CAM_ERR(CAM_UTIL, + "inval outport id:%d i:%d j:%d num ports:%d ", + outport_id, i, j, + dual_config->num_ports); + rc = -EINVAL; + goto end; + } + + hw_mgr_res = &res_list_isp_out[outport_id]; + if (!hw_mgr_res->hw_res[j]) + continue; + + if (hw_mgr_res->hw_res[j]->hw_intf->hw_idx != base_idx) + continue; + + res = hw_mgr_res->hw_res[j]; + + if (res->res_id < CAM_ISP_TFE_OUT_RES_BASE || + res->res_id >= CAM_ISP_TFE_OUT_RES_MAX) { + CAM_DBG(CAM_ISP, "res id :%d", res->res_id); + continue; + } + + dual_isp_update_args.split_id = j; + dual_isp_update_args.res = res; + dual_isp_update_args.stripe_config = + &dual_config->stripes[stp_index]; + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_STRIPE_UPDATE, + &dual_isp_update_args, + sizeof(struct cam_tfe_dual_update_args)); + if (rc) + goto end; + } + } + +end: + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + return rc; +} + +int cam_tfe_add_command_buffers( + struct cam_hw_prepare_update_args *prepare, + struct cam_kmd_buf_info *kmd_buf_info, + struct cam_isp_ctx_base_info *base_info, + cam_packet_generic_blob_handler blob_handler_cb, + struct cam_isp_hw_mgr_res *res_list_isp_out, + uint32_t size_isp_out) +{ + int rc = 0; + uint32_t cmd_meta_data, num_ent, i; + uint32_t base_idx; + enum cam_isp_hw_split_id split_id; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct cam_hw_update_entry *hw_entry; + + hw_entry = prepare->hw_update_entries; + split_id = base_info->split_id; + base_idx = base_info->idx; + + /* + * set the cmd_desc to point the first command descriptor in the + * packet + */ + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint8_t *)&prepare->packet->payload + + prepare->packet->cmd_buf_offset); + + CAM_DBG(CAM_ISP, "split id = %d, number of command buffers:%d", + split_id, prepare->packet->num_cmd_buf); + + for (i = 0; i < prepare->packet->num_cmd_buf; i++) { + num_ent = prepare->num_hw_update_entries; + if (!cmd_desc[i].length) + continue; + + /* One hw entry space required for left or right or common */ + if (num_ent + 1 >= prepare->max_hw_update_entries) { + CAM_ERR(CAM_ISP, "Insufficient HW entries :%d %d", + num_ent, prepare->max_hw_update_entries); + return -EINVAL; + } + + rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]); + if (rc) + return rc; + + cmd_meta_data = cmd_desc[i].meta_data; + + CAM_DBG(CAM_ISP, "meta type: %d, split_id: %d", + cmd_meta_data, split_id); + + switch (cmd_meta_data) { + case CAM_ISP_TFE_PACKET_META_BASE: + case CAM_ISP_TFE_PACKET_META_LEFT: + if (split_id == CAM_ISP_HW_SPLIT_LEFT) { + hw_entry[num_ent].len = cmd_desc[i].length; + hw_entry[num_ent].handle = + cmd_desc[i].mem_handle; + hw_entry[num_ent].offset = cmd_desc[i].offset; + hw_entry[num_ent].flags = CAM_ISP_IQ_BL; + CAM_DBG(CAM_ISP, + "Meta_Left num_ent=%d handle=0x%x, len=%u, offset=%u", + num_ent, + hw_entry[num_ent].handle, + hw_entry[num_ent].len, + hw_entry[num_ent].offset); + + num_ent++; + } + break; + case CAM_ISP_TFE_PACKET_META_RIGHT: + if (split_id == CAM_ISP_HW_SPLIT_RIGHT) { + hw_entry[num_ent].len = cmd_desc[i].length; + hw_entry[num_ent].handle = + cmd_desc[i].mem_handle; + hw_entry[num_ent].offset = cmd_desc[i].offset; + hw_entry[num_ent].flags = CAM_ISP_IQ_BL; + CAM_DBG(CAM_ISP, + "Meta_Right num_ent=%d handle=0x%x, len=%u, offset=%u", + num_ent, + hw_entry[num_ent].handle, + hw_entry[num_ent].len, + hw_entry[num_ent].offset); + + num_ent++; + } + break; + case CAM_ISP_TFE_PACKET_META_COMMON: + hw_entry[num_ent].len = cmd_desc[i].length; + hw_entry[num_ent].handle = + cmd_desc[i].mem_handle; + hw_entry[num_ent].offset = cmd_desc[i].offset; + hw_entry[num_ent].flags = CAM_ISP_IQ_BL; + CAM_DBG(CAM_ISP, + "Meta_Common num_ent=%d handle=0x%x, len=%u, offset=%u", + num_ent, + hw_entry[num_ent].handle, + hw_entry[num_ent].len, + hw_entry[num_ent].offset); + if (cmd_meta_data == CAM_ISP_PACKET_META_DMI_COMMON) + hw_entry[num_ent].flags = 0x1; + + num_ent++; + break; + case CAM_ISP_TFE_PACKET_META_DUAL_CONFIG: + + rc = cam_tfe_update_dual_config(prepare, + &cmd_desc[i], split_id, base_idx, + res_list_isp_out, size_isp_out); + + if (rc) + return rc; + break; + case CAM_ISP_TFE_PACKET_META_GENERIC_BLOB_COMMON: { + struct cam_isp_generic_blob_info blob_info; + + prepare->num_hw_update_entries = num_ent; + blob_info.prepare = prepare; + blob_info.base_info = base_info; + blob_info.kmd_buf_info = kmd_buf_info; + + rc = cam_packet_util_process_generic_cmd_buffer( + &cmd_desc[i], + blob_handler_cb, + &blob_info); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in processing blobs %d", rc); + return rc; + } + hw_entry[num_ent].flags = CAM_ISP_IQ_BL; + num_ent = prepare->num_hw_update_entries; + } + break; + case CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_FLUSH: + case CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_ERROR: + case CAM_ISP_TFE_PACKET_META_REG_DUMP_PER_REQUEST: + if (split_id == CAM_ISP_HW_SPLIT_LEFT) { + if (prepare->num_reg_dump_buf >= + CAM_REG_DUMP_MAX_BUF_ENTRIES) { + CAM_ERR(CAM_ISP, + "Descriptor count out of bounds: %d", + prepare->num_reg_dump_buf); + return -EINVAL; + } + prepare->reg_dump_buf_desc[ + prepare->num_reg_dump_buf] = + cmd_desc[i]; + prepare->num_reg_dump_buf++; + CAM_DBG(CAM_ISP, + "Added command buffer: %d desc_count: %d", + cmd_desc[i].meta_data, + prepare->num_reg_dump_buf); + } + break; + default: + CAM_ERR(CAM_ISP, "invalid cdm command meta data %d", + cmd_meta_data); + return -EINVAL; + } + prepare->num_hw_update_entries = num_ent; + } + + return rc; +} + +static int cam_tfe_mgr_prepare_hw_update(void *hw_mgr_priv, + void *prepare_hw_update_args) +{ + int rc = 0; + struct cam_hw_prepare_update_args *prepare = + (struct cam_hw_prepare_update_args *) prepare_hw_update_args; + struct cam_tfe_hw_mgr_ctx *ctx; + struct cam_tfe_hw_mgr *hw_mgr; + struct cam_kmd_buf_info kmd_buf; + uint32_t i; + bool fill_fence = true; + struct cam_isp_prepare_hw_update_data *prepare_hw_data; + + if (!hw_mgr_priv || !prepare_hw_update_args) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + CAM_DBG(CAM_REQ, "Enter for req_id %lld", + prepare->packet->header.request_id); + + prepare_hw_data = (struct cam_isp_prepare_hw_update_data *) + prepare->priv; + + ctx = (struct cam_tfe_hw_mgr_ctx *) prepare->ctxt_to_hw_map; + hw_mgr = (struct cam_tfe_hw_mgr *)hw_mgr_priv; + + rc = cam_packet_util_validate_packet(prepare->packet, + prepare->remain_len); + if (rc) + return rc; + + /* Pre parse the packet*/ + rc = cam_packet_util_get_kmd_buffer(prepare->packet, &kmd_buf); + if (rc) + return rc; + + rc = cam_packet_util_process_patches(prepare->packet, + hw_mgr->mgr_common.cmd_iommu_hdl, + hw_mgr->mgr_common.cmd_iommu_hdl_secure); + if (rc) { + CAM_ERR(CAM_ISP, "Patch ISP packet failed."); + return rc; + } + + prepare->num_hw_update_entries = 0; + prepare->num_in_map_entries = 0; + prepare->num_out_map_entries = 0; + prepare->num_reg_dump_buf = 0; + + memset(&prepare_hw_data->bw_config[0], 0x0, + sizeof(prepare_hw_data->bw_config[0]) * + CAM_TFE_HW_NUM_MAX); + memset(&prepare_hw_data->bw_config_valid[0], 0x0, + sizeof(prepare_hw_data->bw_config_valid[0]) * + CAM_TFE_HW_NUM_MAX); + + for (i = 0; i < ctx->num_base; i++) { + CAM_DBG(CAM_ISP, "process cmd buffer for device %d", i); + + CAM_DBG(CAM_ISP, + "change base i=%d, idx=%d", + i, ctx->base[i].idx); + + /* Add change base */ + rc = cam_isp_add_change_base(prepare, &ctx->res_list_tfe_in, + ctx->base[i].idx, &kmd_buf); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in change base i=%d, idx=%d, rc=%d", + i, ctx->base[i].idx, rc); + goto end; + } + + + /* get command buffers */ + if (ctx->base[i].split_id != CAM_ISP_HW_SPLIT_MAX) { + rc = cam_tfe_add_command_buffers(prepare, &kmd_buf, + &ctx->base[i], + cam_isp_tfe_packet_generic_blob_handler, + ctx->res_list_tfe_out, CAM_TFE_HW_OUT_RES_MAX); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in add cmdbuf, i=%d, split_id=%d, rc=%d", + i, ctx->base[i].split_id, rc); + goto end; + } + } + + /* get IO buffers */ + rc = cam_isp_add_io_buffers(hw_mgr->mgr_common.img_iommu_hdl, + hw_mgr->mgr_common.img_iommu_hdl_secure, + prepare, ctx->base[i].idx, + &kmd_buf, ctx->res_list_tfe_out, + NULL, + CAM_TFE_HW_OUT_RES_MAX, fill_fence); + + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in io buffers, i=%d, rc=%d", + i, rc); + goto end; + } + + /* fence map table entries need to fill only once in the loop */ + if (fill_fence) + fill_fence = false; + } + + CAM_DBG(CAM_ISP, + "num_reg_dump_buf=%d ope code:%d", + prepare->num_reg_dump_buf, prepare->packet->header.op_code); + + /* reg update will be done later for the initial configure */ + if (((prepare->packet->header.op_code) & 0xF) == + CAM_ISP_PACKET_INIT_DEV) { + prepare_hw_data->packet_opcode_type = + CAM_ISP_TFE_PACKET_INIT_DEV; + + if ((!prepare->num_reg_dump_buf) || (prepare->num_reg_dump_buf > + CAM_REG_DUMP_MAX_BUF_ENTRIES)) + goto end; + + if (!ctx->num_reg_dump_buf) { + ctx->num_reg_dump_buf = + prepare->num_reg_dump_buf; + memcpy(ctx->reg_dump_buf_desc, + prepare->reg_dump_buf_desc, + sizeof(struct cam_cmd_buf_desc) * + prepare->num_reg_dump_buf); + } else { + prepare_hw_data->num_reg_dump_buf = + prepare->num_reg_dump_buf; + memcpy(prepare_hw_data->reg_dump_buf_desc, + prepare->reg_dump_buf_desc, + sizeof(struct cam_cmd_buf_desc) * + prepare_hw_data->num_reg_dump_buf); + } + + goto end; + } else { + prepare_hw_data->packet_opcode_type = + CAM_ISP_TFE_PACKET_CONFIG_DEV; + prepare_hw_data->num_reg_dump_buf = prepare->num_reg_dump_buf; + if ((prepare_hw_data->num_reg_dump_buf) && + (prepare_hw_data->num_reg_dump_buf < + CAM_REG_DUMP_MAX_BUF_ENTRIES)) { + memcpy(prepare_hw_data->reg_dump_buf_desc, + prepare->reg_dump_buf_desc, + sizeof(struct cam_cmd_buf_desc) * + prepare_hw_data->num_reg_dump_buf); + } + } + + /* add reg update commands */ + for (i = 0; i < ctx->num_base; i++) { + /* Add change base */ + rc = cam_isp_add_change_base(prepare, &ctx->res_list_tfe_in, + ctx->base[i].idx, &kmd_buf); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in change base adding reg_update cmd i=%d, idx=%d, rc=%d", + i, ctx->base[i].idx, rc); + goto end; + } + + /*Add reg update */ + rc = cam_isp_add_reg_update(prepare, &ctx->res_list_tfe_in, + ctx->base[i].idx, &kmd_buf); + if (rc) { + CAM_ERR(CAM_ISP, + "Add Reg_update cmd Failed i=%d, idx=%d, rc=%d", + i, ctx->base[i].idx, rc); + goto end; + } + } + +end: + return rc; +} + +static int cam_tfe_mgr_resume_hw(struct cam_tfe_hw_mgr_ctx *ctx) +{ + return cam_tfe_mgr_bw_control(ctx, CAM_TFE_BW_CONTROL_INCLUDE); +} + +static int cam_tfe_mgr_sof_irq_debug( + struct cam_tfe_hw_mgr_ctx *ctx, + uint32_t sof_irq_enable) +{ + int rc = 0; + uint32_t i = 0; + struct cam_isp_hw_mgr_res *hw_mgr_res = NULL; + struct cam_hw_intf *hw_intf = NULL; + struct cam_isp_resource_node *rsrc_node = NULL; + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.process_cmd) { + rc |= hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_TFE_CSID_SOF_IRQ_DEBUG, + &sof_irq_enable, + sizeof(sof_irq_enable)); + } + } + } + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + rsrc_node = hw_mgr_res->hw_res[i]; + if (rsrc_node->process_cmd && (rsrc_node->res_id == + CAM_ISP_HW_TFE_IN_CAMIF)) { + rc |= hw_mgr_res->hw_res[i]->process_cmd( + hw_mgr_res->hw_res[i], + CAM_ISP_HW_CMD_SOF_IRQ_DEBUG, + &sof_irq_enable, + sizeof(sof_irq_enable)); + } + } + } + + return rc; +} + +static void cam_tfe_mgr_print_io_bufs(struct cam_packet *packet, + int32_t iommu_hdl, int32_t sec_mmu_hdl, uint32_t pf_buf_info, + bool *mem_found) +{ + dma_addr_t iova_addr; + size_t src_buf_size; + int i, j; + int rc = 0; + int32_t mmu_hdl; + + struct cam_buf_io_cfg *io_cfg = NULL; + + if (mem_found) + *mem_found = false; + + io_cfg = (struct cam_buf_io_cfg *)((uint32_t *)&packet->payload + + packet->io_configs_offset / 4); + + for (i = 0; i < packet->num_io_configs; i++) { + for (j = 0; j < CAM_PACKET_MAX_PLANES; j++) { + if (!io_cfg[i].mem_handle[j]) + break; + + if (pf_buf_info && + GET_FD_FROM_HANDLE(io_cfg[i].mem_handle[j]) == + GET_FD_FROM_HANDLE(pf_buf_info)) { + CAM_INFO(CAM_ISP, + "Found PF at port: 0x%x mem 0x%x fd: 0x%x", + io_cfg[i].resource_type, + io_cfg[i].mem_handle[j], + pf_buf_info); + if (mem_found) + *mem_found = true; + } + + CAM_INFO(CAM_ISP, "port: 0x%x f: %u format: %d dir %d", + io_cfg[i].resource_type, + io_cfg[i].fence, + io_cfg[i].format, + io_cfg[i].direction); + + mmu_hdl = cam_mem_is_secure_buf( + io_cfg[i].mem_handle[j]) ? sec_mmu_hdl : + iommu_hdl; + rc = cam_mem_get_io_buf(io_cfg[i].mem_handle[j], + mmu_hdl, &iova_addr, &src_buf_size); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "get src buf address fail mem_handle 0x%x", + io_cfg[i].mem_handle[j]); + continue; + } + if ((iova_addr & 0xFFFFFFFF) != iova_addr) { + CAM_ERR(CAM_ISP, "Invalid mapped address"); + rc = -EINVAL; + continue; + } + + CAM_INFO(CAM_ISP, + "pln %d w %d h %d s %u size 0x%x addr 0x%x end_addr 0x%x offset %x memh %x", + j, io_cfg[i].planes[j].width, + io_cfg[i].planes[j].height, + io_cfg[i].planes[j].plane_stride, + (unsigned int)src_buf_size, + (unsigned int)iova_addr, + (unsigned int)iova_addr + + (unsigned int)src_buf_size, + io_cfg[i].offsets[j], + io_cfg[i].mem_handle[j]); + } + } +} + +static void cam_tfe_mgr_ctx_irq_dump(struct cam_tfe_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_isp_hw_get_cmd_update cmd_update; + int i = 0; + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) + continue; + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + switch (hw_mgr_res->hw_res[i]->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + cmd_update.res = hw_mgr_res->hw_res[i]; + cmd_update.cmd_type = + CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP; + hw_intf->hw_ops.process_cmd(hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP, + &cmd_update, sizeof(cmd_update)); + break; + default: + break; + } + } + } +} + +static int cam_tfe_mgr_cmd(void *hw_mgr_priv, void *cmd_args) +{ + int rc = 0; + struct cam_hw_cmd_args *hw_cmd_args = cmd_args; + struct cam_tfe_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_tfe_hw_mgr_ctx *ctx = (struct cam_tfe_hw_mgr_ctx *) + hw_cmd_args->ctxt_to_hw_map; + struct cam_isp_hw_cmd_args *isp_hw_cmd_args = NULL; + struct cam_packet *packet; + + if (!hw_mgr_priv || !cmd_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Fatal: Invalid context is used"); + return -EPERM; + } + + switch (hw_cmd_args->cmd_type) { + case CAM_HW_MGR_CMD_INTERNAL: + if (!hw_cmd_args->u.internal_args) { + CAM_ERR(CAM_ISP, "Invalid cmd arguments"); + return -EINVAL; + } + + isp_hw_cmd_args = (struct cam_isp_hw_cmd_args *) + hw_cmd_args->u.internal_args; + + switch (isp_hw_cmd_args->cmd_type) { + case CAM_ISP_HW_MGR_CMD_PAUSE_HW: + cam_tfe_mgr_pause_hw(ctx); + break; + case CAM_ISP_HW_MGR_CMD_RESUME_HW: + cam_tfe_mgr_resume_hw(ctx); + break; + case CAM_ISP_HW_MGR_CMD_SOF_DEBUG: + cam_tfe_mgr_sof_irq_debug(ctx, + isp_hw_cmd_args->u.sof_irq_enable); + break; + case CAM_ISP_HW_MGR_CMD_CTX_TYPE: + if (ctx->is_rdi_only_context) + isp_hw_cmd_args->u.ctx_type = CAM_ISP_CTX_RDI; + else + isp_hw_cmd_args->u.ctx_type = CAM_ISP_CTX_PIX; + break; + case CAM_ISP_HW_MGR_GET_PACKET_OPCODE: + packet = (struct cam_packet *) + isp_hw_cmd_args->cmd_data; + if ((packet->header.op_code & 0xF) == + CAM_ISP_TFE_PACKET_INIT_DEV) + isp_hw_cmd_args->u.packet_op_code = + CAM_ISP_TFE_PACKET_INIT_DEV; + else + isp_hw_cmd_args->u.packet_op_code = + CAM_ISP_TFE_PACKET_CONFIG_DEV; + break; + default: + CAM_ERR(CAM_ISP, "Invalid HW mgr command:0x%x", + hw_cmd_args->cmd_type); + rc = -EINVAL; + break; + } + break; + case CAM_HW_MGR_CMD_DUMP_PF_INFO: + cam_tfe_mgr_print_io_bufs( + hw_cmd_args->u.pf_args.pf_data.packet, + hw_mgr->mgr_common.img_iommu_hdl, + hw_mgr->mgr_common.img_iommu_hdl_secure, + hw_cmd_args->u.pf_args.buf_info, + hw_cmd_args->u.pf_args.mem_found); + break; + case CAM_HW_MGR_CMD_REG_DUMP_ON_FLUSH: + if (ctx->last_dump_flush_req_id == ctx->applied_req_id) + return 0; + + ctx->last_dump_flush_req_id = ctx->applied_req_id; + + rc = cam_tfe_mgr_handle_reg_dump(ctx, ctx->reg_dump_buf_desc, + ctx->num_reg_dump_buf, + CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_FLUSH, + NULL, false); + if (rc) { + CAM_ERR(CAM_ISP, + "Reg dump on flush failed req id: %llu num_reg_dump:0x%x rc: %d", + ctx->applied_req_id, ctx->num_reg_dump_buf, rc); + return rc; + } + + break; + case CAM_HW_MGR_CMD_REG_DUMP_ON_ERROR: + if (ctx->last_dump_err_req_id == ctx->applied_req_id) + return 0; + + ctx->last_dump_err_req_id = ctx->applied_req_id; + rc = cam_tfe_mgr_handle_reg_dump(ctx, ctx->reg_dump_buf_desc, + ctx->num_reg_dump_buf, + CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_ERROR, + NULL, false); + if (rc) { + CAM_ERR(CAM_ISP, + "Reg dump on error failed req id:%llu num_reg_dump:0x%x rc: %d", + ctx->applied_req_id, ctx->num_reg_dump_buf, rc); + return rc; + } + break; + default: + CAM_ERR(CAM_ISP, "Invalid cmd"); + } + + return rc; +} + +static int cam_tfe_mgr_cmd_get_sof_timestamp( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + uint64_t *time_stamp, + uint64_t *boot_time_stamp) +{ + int rc = -EINVAL; + uint32_t i; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_csid_get_time_stamp_args csid_get_time; + + hw_mgr_res = list_first_entry(&tfe_ctx->res_list_tfe_csid, + struct cam_isp_hw_mgr_res, list); + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + /* + * Get the SOF time stamp from left resource only. + * Left resource is master for dual tfe case and + * Rdi only context case left resource only hold + * the RDI resource + */ + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.process_cmd) { + /* + * Single TFE case, Get the time stamp from + * available one csid hw in the context + * Dual TFE case, get the time stamp from + * master(left) would be sufficient + */ + + csid_get_time.node_res = + hw_mgr_res->hw_res[i]; + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_TFE_CSID_CMD_GET_TIME_STAMP, + &csid_get_time, + sizeof(struct + cam_tfe_csid_get_time_stamp_args)); + if (!rc && (i == CAM_ISP_HW_SPLIT_LEFT)) { + *time_stamp = + csid_get_time.time_stamp_val; + *boot_time_stamp = + csid_get_time.boot_timestamp; + break; + } + } + } + + if (rc) + CAM_ERR_RATE_LIMIT(CAM_ISP, "Getting sof time stamp failed"); + + return rc; +} + +static void cam_tfe_mgr_ctx_reg_dump(struct cam_tfe_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_isp_hw_get_cmd_update cmd_update; + int i = 0; + + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, + list) { + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) + continue; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + switch (hw_mgr_res->hw_res[i]->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + cmd_update.res = hw_mgr_res->hw_res[i]; + cmd_update.cmd_type = + CAM_ISP_HW_CMD_GET_REG_DUMP; + hw_intf->hw_ops.process_cmd(hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_REG_DUMP, + &cmd_update, sizeof(cmd_update)); + break; + default: + break; + } + } + } + + /* Dump the TFE CSID registers */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, + list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.process_cmd) { + hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_TFE_CSID_CMD_GET_REG_DUMP, + hw_mgr_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + } + } + } +} + +static int cam_tfe_mgr_process_recovery_cb(void *priv, void *data) +{ + int32_t rc = 0; + struct cam_tfe_hw_event_recovery_data *recovery_data = data; + struct cam_hw_start_args start_args; + struct cam_hw_stop_args stop_args; + struct cam_tfe_hw_mgr *tfe_hw_mgr = priv; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx; + uint32_t i = 0; + + uint32_t error_type = recovery_data->error_type; + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + + /* Here recovery is performed */ + CAM_DBG(CAM_ISP, "ErrorType = %d", error_type); + + switch (error_type) { + case CAM_ISP_HW_ERROR_OVERFLOW: + case CAM_ISP_HW_ERROR_BUSIF_OVERFLOW: + if (!recovery_data->affected_ctx[0]) { + CAM_ERR(CAM_ISP, + "No context is affected but recovery called"); + kfree(recovery_data); + return 0; + } + + /* stop resources here */ + CAM_DBG(CAM_ISP, "STOP: Number of affected context: %d", + recovery_data->no_of_context); + for (i = 0; i < recovery_data->no_of_context; i++) { + stop_args.ctxt_to_hw_map = + recovery_data->affected_ctx[i]; + tfe_hw_mgr_ctx = recovery_data->affected_ctx[i]; + + if (g_tfe_hw_mgr.debug_cfg.enable_reg_dump) + cam_tfe_mgr_ctx_reg_dump(tfe_hw_mgr_ctx); + + if (g_tfe_hw_mgr.debug_cfg.enable_recovery) { + rc = cam_tfe_mgr_stop_hw_in_overflow( + &stop_args); + if (rc) { + CAM_ERR(CAM_ISP, + "CTX stop failed(%d)", rc); + return rc; + } + } + } + + if (!g_tfe_hw_mgr.debug_cfg.enable_recovery) { + CAM_INFO(CAM_ISP, "reg dumping is done "); + return 0; + } + + CAM_DBG(CAM_ISP, "RESET: CSID PATH"); + for (i = 0; i < recovery_data->no_of_context; i++) { + ctx = recovery_data->affected_ctx[i]; + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, + list) { + rc = cam_tfe_hw_mgr_reset_csid_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Failed RESET (%d)", + hw_mgr_res->res_id); + return rc; + } + } + } + + CAM_DBG(CAM_ISP, "RESET: Calling TFE reset"); + + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (recovery_data->affected_core[i]) + cam_tfe_mgr_reset_tfe_hw(tfe_hw_mgr, i); + } + + CAM_DBG(CAM_ISP, "START: Number of affected context: %d", + recovery_data->no_of_context); + + for (i = 0; i < recovery_data->no_of_context; i++) { + ctx = recovery_data->affected_ctx[i]; + start_args.ctxt_to_hw_map = ctx; + + atomic_set(&ctx->overflow_pending, 0); + + rc = cam_tfe_mgr_restart_hw(&start_args); + if (rc) { + CAM_ERR(CAM_ISP, "CTX start failed(%d)", rc); + return rc; + } + CAM_DBG(CAM_ISP, "Started resources rc (%d)", rc); + } + CAM_DBG(CAM_ISP, "Recovery Done rc (%d)", rc); + + break; + + case CAM_ISP_HW_ERROR_P2I_ERROR: + break; + + case CAM_ISP_HW_ERROR_VIOLATION: + break; + + default: + CAM_ERR(CAM_ISP, "Invalid Error"); + } + CAM_DBG(CAM_ISP, "Exit: ErrorType = %d", error_type); + + kfree(recovery_data); + return rc; +} + +static int cam_tfe_hw_mgr_do_error_recovery( + struct cam_tfe_hw_event_recovery_data *tfe_mgr_recovery_data) +{ + int32_t rc = 0; + struct crm_workq_task *task = NULL; + struct cam_tfe_hw_event_recovery_data *recovery_data = NULL; + + recovery_data = kmemdup(tfe_mgr_recovery_data, + sizeof(struct cam_tfe_hw_event_recovery_data), GFP_ATOMIC); + + if (!recovery_data) + return -ENOMEM; + + CAM_DBG(CAM_ISP, "Enter: error_type (%d)", recovery_data->error_type); + + task = cam_req_mgr_workq_get_task(g_tfe_hw_mgr.workq); + if (!task) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No empty task frame"); + kfree(recovery_data); + return -ENOMEM; + } + + task->process_cb = &cam_tfe_mgr_process_recovery_cb; + task->payload = recovery_data; + rc = cam_req_mgr_workq_enqueue_task(task, + recovery_data->affected_ctx[0]->hw_mgr, + CRM_TASK_PRIORITY_0); + + return rc; +} + +/* + * This function checks if any of the valid entry in affected_core[] + * is associated with this context. if YES + * a. It fills the other cores associated with this context.in + * affected_core[] + * b. Return true + */ +static bool cam_tfe_hw_mgr_is_ctx_affected( + struct cam_tfe_hw_mgr_ctx *tfe_hwr_mgr_ctx, + uint32_t *affected_core, + uint32_t size) +{ + + bool rc = false; + uint32_t i = 0, j = 0; + uint32_t max_idx = tfe_hwr_mgr_ctx->num_base; + uint32_t ctx_affected_core_idx[CAM_TFE_HW_NUM_MAX] = {0}; + + CAM_DBG(CAM_ISP, "Enter:max_idx = %d", max_idx); + + if ((max_idx >= CAM_TFE_HW_NUM_MAX) || (size > CAM_TFE_HW_NUM_MAX)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "invalid parameter = %d", max_idx); + return rc; + } + + for (i = 0; i < max_idx; i++) { + if (affected_core[tfe_hwr_mgr_ctx->base[i].idx]) + rc = true; + else { + ctx_affected_core_idx[j] = tfe_hwr_mgr_ctx->base[i].idx; + j = j + 1; + } + } + + if (rc) { + while (j) { + if (affected_core[ctx_affected_core_idx[j-1]] != 1) + affected_core[ctx_affected_core_idx[j-1]] = 1; + j = j - 1; + } + } + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +/* + * For any dual TFE context, if non-affected TFE is also serving + * another context, then that context should also be notified with fatal error + * So Loop through each context and - + * a. match core_idx + * b. Notify CTX with fatal error + */ +static int cam_tfe_hw_mgr_find_affected_ctx( + struct cam_isp_hw_error_event_data *error_event_data, + uint32_t curr_core_idx, + struct cam_tfe_hw_event_recovery_data *recovery_data) +{ + uint32_t affected_core[CAM_TFE_HW_NUM_MAX] = {0}; + struct cam_tfe_hw_mgr_ctx *tfe_hwr_mgr_ctx = NULL; + cam_hw_event_cb_func notify_err_cb; + struct cam_tfe_hw_mgr *tfe_hwr_mgr = NULL; + enum cam_isp_hw_event_type event_type = CAM_ISP_HW_EVENT_ERROR; + uint32_t i = 0; + + if (!recovery_data) { + CAM_ERR(CAM_ISP, "recovery_data parameter is NULL"); + return -EINVAL; + } + + recovery_data->no_of_context = 0; + affected_core[curr_core_idx] = 1; + tfe_hwr_mgr = &g_tfe_hw_mgr; + + list_for_each_entry(tfe_hwr_mgr_ctx, + &tfe_hwr_mgr->used_ctx_list, list) { + /* + * Check if current core_idx matches the HW associated + * with this context + */ + if (!cam_tfe_hw_mgr_is_ctx_affected(tfe_hwr_mgr_ctx, + affected_core, CAM_TFE_HW_NUM_MAX)) + continue; + + if (atomic_read(&tfe_hwr_mgr_ctx->overflow_pending)) { + CAM_INFO(CAM_ISP, "CTX:%d already error reported", + tfe_hwr_mgr_ctx->ctx_index); + continue; + } + + atomic_set(&tfe_hwr_mgr_ctx->overflow_pending, 1); + notify_err_cb = tfe_hwr_mgr_ctx->common.event_cb[event_type]; + + /* Add affected_context in list of recovery data */ + CAM_DBG(CAM_ISP, "Add affected ctx %d to list", + tfe_hwr_mgr_ctx->ctx_index); + if (recovery_data->no_of_context < CAM_TFE_CTX_MAX) + recovery_data->affected_ctx[ + recovery_data->no_of_context++] = + tfe_hwr_mgr_ctx; + + /* + * In the call back function corresponding ISP context + * will update CRM about fatal Error + */ + if (notify_err_cb) { + notify_err_cb(tfe_hwr_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_ERROR, error_event_data); + } else { + CAM_WARN(CAM_ISP, "Error call back is not set"); + goto end; + } + } + + /* fill the affected_core in recovery data */ + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + recovery_data->affected_core[i] = affected_core[i]; + CAM_DBG(CAM_ISP, "tfe core %d is affected (%d)", + i, recovery_data->affected_core[i]); + } +end: + return 0; +} + +static int cam_tfe_hw_mgr_handle_csid_event( + struct cam_isp_hw_event_info *event_info) +{ + struct cam_isp_hw_error_event_data error_event_data = {0}; + struct cam_tfe_hw_event_recovery_data recovery_data = {0}; + + /* this can be extended based on the types of error + * received from CSID + */ + switch (event_info->err_type) { + case CAM_ISP_HW_ERROR_CSID_FATAL: { + + if (!g_tfe_hw_mgr.debug_cfg.enable_csid_recovery) + break; + + error_event_data.error_type = event_info->err_type; + cam_tfe_hw_mgr_find_affected_ctx(&error_event_data, + event_info->hw_idx, + &recovery_data); + break; + } + default: + break; + } + return 0; +} + +static int cam_tfe_hw_mgr_handle_hw_err( + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_isp_hw_error_event_data error_event_data = {0}; + struct cam_tfe_hw_event_recovery_data recovery_data = {0}; + int rc = -EINVAL; + uint32_t core_idx; + + if (event_info->err_type == CAM_TFE_IRQ_STATUS_VIOLATION) + error_event_data.error_type = CAM_ISP_HW_ERROR_VIOLATION; + else if (event_info->res_type == CAM_ISP_RESOURCE_TFE_IN || + event_info->res_type == CAM_ISP_RESOURCE_PIX_PATH) + error_event_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; + else if (event_info->res_type == CAM_ISP_RESOURCE_TFE_OUT) + error_event_data.error_type = CAM_ISP_HW_ERROR_BUSIF_OVERFLOW; + + spin_lock(&g_tfe_hw_mgr.ctx_lock); + if (event_info->err_type == CAM_ISP_HW_ERROR_CSID_FATAL) { + rc = cam_tfe_hw_mgr_handle_csid_event(event_info); + spin_unlock(&g_tfe_hw_mgr.ctx_lock); + return rc; + } + + core_idx = event_info->hw_idx; + + if (g_tfe_hw_mgr.debug_cfg.enable_recovery) + error_event_data.recovery_enabled = true; + else + error_event_data.recovery_enabled = false; + + rc = cam_tfe_hw_mgr_find_affected_ctx(&error_event_data, + core_idx, &recovery_data); + if (rc || !(recovery_data.no_of_context)) + goto end; + + if (event_info->res_type == CAM_ISP_RESOURCE_TFE_OUT) { + spin_unlock(&g_tfe_hw_mgr.ctx_lock); + return rc; + } + + if (g_tfe_hw_mgr.debug_cfg.enable_recovery) { + /* Trigger for recovery */ + if (event_info->err_type == CAM_TFE_IRQ_STATUS_VIOLATION) + recovery_data.error_type = CAM_ISP_HW_ERROR_VIOLATION; + else + recovery_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; + cam_tfe_hw_mgr_do_error_recovery(&recovery_data); + } else { + CAM_DBG(CAM_ISP, "recovery is not enabled"); + rc = 0; + } +end: + spin_unlock(&g_tfe_hw_mgr.ctx_lock); + return rc; +} + +static int cam_tfe_hw_mgr_handle_hw_rup( + void *ctx, + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx; + cam_hw_event_cb_func tfe_hwr_irq_rup_cb; + struct cam_isp_hw_reg_update_event_data rup_event_data; + + tfe_hwr_irq_rup_cb = + tfe_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_REG_UPDATE]; + + switch (event_info->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + if (tfe_hw_mgr_ctx->is_dual) + if (event_info->hw_idx != tfe_hw_mgr_ctx->master_hw_idx) + break; + + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + break; + + tfe_hwr_irq_rup_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_REG_UPDATE, &rup_event_data); + break; + + case CAM_ISP_HW_TFE_IN_RDI0: + case CAM_ISP_HW_TFE_IN_RDI1: + case CAM_ISP_HW_TFE_IN_RDI2: + if (!tfe_hw_mgr_ctx->is_rdi_only_context) + break; + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + break; + tfe_hwr_irq_rup_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_REG_UPDATE, &rup_event_data); + break; + + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", + event_info->res_id); + break; + } + + CAM_DBG(CAM_ISP, "RUP done for TFE source %d", + event_info->res_id); + + return 0; +} + +static int cam_tfe_hw_mgr_check_irq_for_dual_tfe( + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx, + uint32_t hw_event_type) +{ + int32_t rc = -EINVAL; + uint32_t *event_cnt = NULL; + uint32_t master_hw_idx; + uint32_t slave_hw_idx; + + if (!tfe_hw_mgr_ctx->is_dual) + return 0; + + master_hw_idx = tfe_hw_mgr_ctx->master_hw_idx; + slave_hw_idx = tfe_hw_mgr_ctx->slave_hw_idx; + + switch (hw_event_type) { + case CAM_ISP_HW_EVENT_SOF: + event_cnt = tfe_hw_mgr_ctx->sof_cnt; + break; + case CAM_ISP_HW_EVENT_EPOCH: + event_cnt = tfe_hw_mgr_ctx->epoch_cnt; + break; + case CAM_ISP_HW_EVENT_EOF: + event_cnt = tfe_hw_mgr_ctx->eof_cnt; + break; + default: + return 0; + } + + if (event_cnt[master_hw_idx] == event_cnt[slave_hw_idx]) { + + event_cnt[master_hw_idx] = 0; + event_cnt[slave_hw_idx] = 0; + + return 0; + } + + if ((event_cnt[master_hw_idx] && + (event_cnt[master_hw_idx] - event_cnt[slave_hw_idx] > 1)) || + (event_cnt[slave_hw_idx] && + (event_cnt[slave_hw_idx] - event_cnt[master_hw_idx] > 1))) { + + if (tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt > 10) { + rc = -1; + return rc; + } + + CAM_ERR_RATE_LIMIT(CAM_ISP, + "One TFE could not generate hw event %d master id :%d slave id:%d", + hw_event_type, event_cnt[master_hw_idx], + event_cnt[slave_hw_idx]); + if (event_cnt[master_hw_idx] >= 2) { + event_cnt[master_hw_idx]--; + tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt++; + } + if (event_cnt[slave_hw_idx] >= 2) { + event_cnt[slave_hw_idx]--; + tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt++; + } + + if (tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt == 1) { + cam_tfe_mgr_ctx_irq_dump(tfe_hw_mgr_ctx); + trace_cam_delay_detect("ISP", "dual tfe irq mismatch", + CAM_DEFAULT_VALUE, tfe_hw_mgr_ctx->ctx_index, + CAM_DEFAULT_VALUE, CAM_DEFAULT_VALUE, + rc); + } + rc = 0; + } + + CAM_DBG(CAM_ISP, "Only one core_index has given hw event %d", + hw_event_type); + + return rc; +} + +static int cam_tfe_hw_mgr_handle_hw_epoch( + void *ctx, + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx; + cam_hw_event_cb_func tfe_hw_irq_epoch_cb; + struct cam_isp_hw_epoch_event_data epoch_done_event_data; + int rc = 0; + + tfe_hw_irq_epoch_cb = + tfe_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_EPOCH]; + + switch (event_info->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + tfe_hw_mgr_ctx->epoch_cnt[event_info->hw_idx]++; + rc = cam_tfe_hw_mgr_check_irq_for_dual_tfe(tfe_hw_mgr_ctx, + CAM_ISP_HW_EVENT_EPOCH); + if (!rc) { + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + break; + tfe_hw_irq_epoch_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_EPOCH, &epoch_done_event_data); + } + break; + + case CAM_ISP_HW_TFE_IN_RDI0: + case CAM_ISP_HW_TFE_IN_RDI1: + case CAM_ISP_HW_TFE_IN_RDI2: + break; + + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", + event_info->res_id); + break; + } + + CAM_DBG(CAM_ISP, "Epoch for TFE source %d", event_info->res_id); + + return 0; +} + +static int cam_tfe_hw_mgr_handle_hw_sof( + void *ctx, + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx; + cam_hw_event_cb_func tfe_hw_irq_sof_cb; + struct cam_isp_hw_sof_event_data sof_done_event_data; + int rc = 0; + + tfe_hw_irq_sof_cb = + tfe_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_SOF]; + + switch (event_info->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + tfe_hw_mgr_ctx->sof_cnt[event_info->hw_idx]++; + rc = cam_tfe_hw_mgr_check_irq_for_dual_tfe(tfe_hw_mgr_ctx, + CAM_ISP_HW_EVENT_SOF); + if (!rc) { + cam_tfe_mgr_cmd_get_sof_timestamp(tfe_hw_mgr_ctx, + &sof_done_event_data.timestamp, + &sof_done_event_data.boot_time); + + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + break; + + tfe_hw_irq_sof_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_SOF, &sof_done_event_data); + } + break; + + case CAM_ISP_HW_TFE_IN_RDI0: + case CAM_ISP_HW_TFE_IN_RDI1: + case CAM_ISP_HW_TFE_IN_RDI2: + if (!tfe_hw_mgr_ctx->is_rdi_only_context) + break; + cam_tfe_mgr_cmd_get_sof_timestamp(tfe_hw_mgr_ctx, + &sof_done_event_data.timestamp, + &sof_done_event_data.boot_time); + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + break; + tfe_hw_irq_sof_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_SOF, &sof_done_event_data); + break; + + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", + event_info->res_id); + break; + } + + CAM_DBG(CAM_ISP, "SOF for TFE source %d", event_info->res_id); + + return 0; +} + +static int cam_tfe_hw_mgr_handle_hw_eof( + void *ctx, + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx; + cam_hw_event_cb_func tfe_hw_irq_eof_cb; + struct cam_isp_hw_eof_event_data eof_done_event_data; + int rc = 0; + + tfe_hw_irq_eof_cb = + tfe_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_EOF]; + + switch (event_info->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + tfe_hw_mgr_ctx->eof_cnt[event_info->hw_idx]++; + rc = cam_tfe_hw_mgr_check_irq_for_dual_tfe(tfe_hw_mgr_ctx, + CAM_ISP_HW_EVENT_EOF); + if (!rc) { + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + break; + tfe_hw_irq_eof_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_EOF, &eof_done_event_data); + } + break; + + case CAM_ISP_HW_TFE_IN_RDI0: + case CAM_ISP_HW_TFE_IN_RDI1: + case CAM_ISP_HW_TFE_IN_RDI2: + break; + + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", + event_info->res_id); + break; + } + + CAM_DBG(CAM_ISP, "EOF for out_res->res_id: 0x%x", + event_info->res_id); + + return 0; +} + +static int cam_tfe_hw_mgr_handle_hw_buf_done( + void *ctx, + void *evt_info) +{ + cam_hw_event_cb_func tfe_hwr_irq_wm_done_cb; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx; + struct cam_isp_hw_done_event_data buf_done_event_data = {0}; + struct cam_isp_hw_event_info *event_info = evt_info; + + tfe_hwr_irq_wm_done_cb = + tfe_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_DONE]; + + buf_done_event_data.num_handles = 1; + buf_done_event_data.resource_handle[0] = event_info->res_id; + + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + return 0; + + if (buf_done_event_data.num_handles > 0 && tfe_hwr_irq_wm_done_cb) { + CAM_DBG(CAM_ISP, "Notify ISP context"); + tfe_hwr_irq_wm_done_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_DONE, &buf_done_event_data); + } + + CAM_DBG(CAM_ISP, "Buf done for out_res->res_id: 0x%x", + event_info->res_id); + + return 0; +} + +static int cam_tfe_hw_mgr_event_handler( + void *priv, + uint32_t evt_id, + void *evt_info) +{ + int rc = 0; + + if (!evt_info) + return -EINVAL; + + if (!priv) + if (evt_id != CAM_ISP_HW_EVENT_ERROR) + return -EINVAL; + + CAM_DBG(CAM_ISP, "Event ID 0x%x", evt_id); + + switch (evt_id) { + case CAM_ISP_HW_EVENT_SOF: + rc = cam_tfe_hw_mgr_handle_hw_sof(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_REG_UPDATE: + rc = cam_tfe_hw_mgr_handle_hw_rup(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_EPOCH: + rc = cam_tfe_hw_mgr_handle_hw_epoch(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_EOF: + rc = cam_tfe_hw_mgr_handle_hw_eof(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_DONE: + rc = cam_tfe_hw_mgr_handle_hw_buf_done(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_ERROR: + rc = cam_tfe_hw_mgr_handle_hw_err(evt_info); + break; + + default: + CAM_ERR(CAM_ISP, "Invalid event ID %d", evt_id); + break; + } + + return rc; +} + +static int cam_tfe_hw_mgr_sort_dev_with_caps( + struct cam_tfe_hw_mgr *tfe_hw_mgr) +{ + int i; + + /* get caps for csid devices */ + for (i = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { + if (!tfe_hw_mgr->csid_devices[i]) + continue; + if (tfe_hw_mgr->csid_devices[i]->hw_ops.get_hw_caps) { + tfe_hw_mgr->csid_devices[i]->hw_ops.get_hw_caps( + tfe_hw_mgr->csid_devices[i]->hw_priv, + &tfe_hw_mgr->tfe_csid_dev_caps[i], + sizeof(tfe_hw_mgr->tfe_csid_dev_caps[i])); + } + } + + /* get caps for tfe devices */ + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (!tfe_hw_mgr->tfe_devices[i]) + continue; + if (tfe_hw_mgr->tfe_devices[i]->hw_ops.get_hw_caps) { + tfe_hw_mgr->tfe_devices[i]->hw_ops.get_hw_caps( + tfe_hw_mgr->tfe_devices[i]->hw_priv, + &tfe_hw_mgr->tfe_dev_caps[i], + sizeof(tfe_hw_mgr->tfe_dev_caps[i])); + } + } + + return 0; +} + +static int cam_tfe_set_csid_debug(void *data, u64 val) +{ + g_tfe_hw_mgr.debug_cfg.csid_debug = val; + CAM_DBG(CAM_ISP, "Set CSID Debug value :%lld", val); + return 0; +} + +static int cam_tfe_get_csid_debug(void *data, u64 *val) +{ + *val = g_tfe_hw_mgr.debug_cfg.csid_debug; + CAM_DBG(CAM_ISP, "Get CSID Debug value :%lld", + g_tfe_hw_mgr.debug_cfg.csid_debug); + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(cam_tfe_csid_debug, + cam_tfe_get_csid_debug, + cam_tfe_set_csid_debug, "%16llu"); + +static int cam_tfe_set_camif_debug(void *data, u64 val) +{ + g_tfe_hw_mgr.debug_cfg.camif_debug = val; + CAM_DBG(CAM_ISP, + "Set camif enable_diag_sensor_status value :%lld", val); + return 0; +} + +static int cam_tfe_get_camif_debug(void *data, u64 *val) +{ + *val = g_tfe_hw_mgr.debug_cfg.camif_debug; + CAM_DBG(CAM_ISP, + "Set camif enable_diag_sensor_status value :%lld", + g_tfe_hw_mgr.debug_cfg.csid_debug); + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(cam_tfe_camif_debug, + cam_tfe_get_camif_debug, + cam_tfe_set_camif_debug, "%16llu"); + +static int cam_tfe_hw_mgr_debug_register(void) +{ + g_tfe_hw_mgr.debug_cfg.set_tpg_pattern = CAM_TOP_TPG_DEFAULT_PATTERN; + g_tfe_hw_mgr.debug_cfg.dentry = debugfs_create_dir("camera_tfe", + NULL); + + if (!g_tfe_hw_mgr.debug_cfg.dentry) { + CAM_ERR(CAM_ISP, "failed to create dentry"); + return -ENOMEM; + } + + if (!debugfs_create_file("tfe_csid_debug", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, NULL, + &cam_tfe_csid_debug)) { + CAM_ERR(CAM_ISP, "failed to create cam_tfe_csid_debug"); + goto err; + } + + if (!debugfs_create_u32("enable_recovery", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, + &g_tfe_hw_mgr.debug_cfg.enable_recovery)) { + CAM_ERR(CAM_ISP, "failed to create enable_recovery"); + goto err; + } + + if (!debugfs_create_u32("enable_csid_recovery", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, + &g_tfe_hw_mgr.debug_cfg.enable_csid_recovery)) { + CAM_ERR(CAM_ISP, "failed to create enable_csid_recovery"); + goto err; + } + + if (!debugfs_create_u32("set_tpg_pattern", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, + &g_tfe_hw_mgr.debug_cfg.set_tpg_pattern)) { + CAM_ERR(CAM_ISP, "failed to create set_tpg_pattern"); + goto err; + } + + if (!debugfs_create_u32("enable_reg_dump", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, + &g_tfe_hw_mgr.debug_cfg.enable_reg_dump)) { + CAM_ERR(CAM_ISP, "failed to create enable_reg_dump"); + goto err; + } + + if (!debugfs_create_file("tfe_camif_debug", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, NULL, + &cam_tfe_camif_debug)) { + CAM_ERR(CAM_ISP, "failed to create cam_tfe_camif_debug"); + goto err; + } + + if (!debugfs_create_u32("per_req_reg_dump", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, + &g_tfe_hw_mgr.debug_cfg.per_req_reg_dump)) { + CAM_ERR(CAM_ISP, "failed to create per_req_reg_dump entry"); + goto err; + } + + + g_tfe_hw_mgr.debug_cfg.enable_recovery = 0; + + return 0; + +err: + debugfs_remove_recursive(g_tfe_hw_mgr.debug_cfg.dentry); + return -ENOMEM; +} + +int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) +{ + int rc = -EFAULT; + int i, j; + struct cam_iommu_handle cdm_handles; + struct cam_tfe_hw_mgr_ctx *ctx_pool; + struct cam_isp_hw_mgr_res *res_list_tfe_out; + + CAM_DBG(CAM_ISP, "Enter"); + + memset(&g_tfe_hw_mgr, 0, sizeof(g_tfe_hw_mgr)); + + mutex_init(&g_tfe_hw_mgr.ctx_mutex); + spin_lock_init(&g_tfe_hw_mgr.ctx_lock); + + if (CAM_TFE_HW_NUM_MAX != CAM_TFE_CSID_HW_NUM_MAX) { + CAM_ERR(CAM_ISP, "CSID num is different then TFE num"); + return -EINVAL; + } + + /* fill tfe hw intf information */ + for (i = 0, j = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + rc = cam_tfe_hw_init(&g_tfe_hw_mgr.tfe_devices[i], i); + if (!rc) { + struct cam_hw_info *tfe_hw = (struct cam_hw_info *) + g_tfe_hw_mgr.tfe_devices[i]->hw_priv; + struct cam_hw_soc_info *soc_info = &tfe_hw->soc_info; + + j++; + + g_tfe_hw_mgr.cdm_reg_map[i] = &soc_info->reg_map[0]; + CAM_DBG(CAM_ISP, + "reg_map: mem base = %pK cam_base = 0x%llx", + (void __iomem *)soc_info->reg_map[0].mem_base, + (uint64_t) soc_info->reg_map[0].mem_cam_base); + } else { + g_tfe_hw_mgr.cdm_reg_map[i] = NULL; + } + } + if (j == 0) { + CAM_ERR(CAM_ISP, "no valid TFE HW"); + return -EINVAL; + } + + /* fill csid hw intf information */ + for (i = 0, j = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { + rc = cam_tfe_csid_hw_init(&g_tfe_hw_mgr.csid_devices[i], i); + if (!rc) + j++; + } + if (!j) { + CAM_ERR(CAM_ISP, "no valid TFE CSID HW"); + return -EINVAL; + } + + /* fill tpg hw intf information */ + for (i = 0, j = 0; i < CAM_TOP_TPG_HW_NUM_MAX; i++) { + rc = cam_top_tpg_hw_init(&g_tfe_hw_mgr.tpg_devices[i], i); + if (!rc) + j++; + } + if (!j) { + CAM_ERR(CAM_ISP, "no valid TFE TPG HW"); + return -EINVAL; + } + + cam_tfe_hw_mgr_sort_dev_with_caps(&g_tfe_hw_mgr); + + /* setup tfe context list */ + INIT_LIST_HEAD(&g_tfe_hw_mgr.free_ctx_list); + INIT_LIST_HEAD(&g_tfe_hw_mgr.used_ctx_list); + + /* + * for now, we only support one iommu handle. later + * we will need to setup more iommu handle for other + * use cases. + * Also, we have to release them once we have the + * deinit support + */ + if (cam_smmu_get_handle("tfe", + &g_tfe_hw_mgr.mgr_common.img_iommu_hdl)) { + CAM_ERR(CAM_ISP, "Can not get iommu handle"); + return -EINVAL; + } + + if (cam_smmu_get_handle("cam-secure", + &g_tfe_hw_mgr.mgr_common.img_iommu_hdl_secure)) { + CAM_ERR(CAM_ISP, "Failed to get secure iommu handle"); + goto secure_fail; + } + + CAM_DBG(CAM_ISP, "iommu_handles: non-secure[0x%x], secure[0x%x]", + g_tfe_hw_mgr.mgr_common.img_iommu_hdl, + g_tfe_hw_mgr.mgr_common.img_iommu_hdl_secure); + + if (!cam_cdm_get_iommu_handle("tfe0", &cdm_handles)) { + CAM_DBG(CAM_ISP, "Successfully acquired the CDM iommu handles"); + g_tfe_hw_mgr.mgr_common.cmd_iommu_hdl = cdm_handles.non_secure; + g_tfe_hw_mgr.mgr_common.cmd_iommu_hdl_secure = + cdm_handles.secure; + } else { + CAM_DBG(CAM_ISP, "Failed to acquire the CDM iommu handles"); + g_tfe_hw_mgr.mgr_common.cmd_iommu_hdl = -1; + g_tfe_hw_mgr.mgr_common.cmd_iommu_hdl_secure = -1; + } + + atomic_set(&g_tfe_hw_mgr.active_ctx_cnt, 0); + for (i = 0; i < CAM_TFE_CTX_MAX; i++) { + memset(&g_tfe_hw_mgr.ctx_pool[i], 0, + sizeof(g_tfe_hw_mgr.ctx_pool[i])); + INIT_LIST_HEAD(&g_tfe_hw_mgr.ctx_pool[i].list); + INIT_LIST_HEAD(&g_tfe_hw_mgr.ctx_pool[i].res_list_tfe_csid); + INIT_LIST_HEAD(&g_tfe_hw_mgr.ctx_pool[i].res_list_tfe_in); + ctx_pool = &g_tfe_hw_mgr.ctx_pool[i]; + for (j = 0; j < CAM_TFE_HW_OUT_RES_MAX; j++) { + res_list_tfe_out = &ctx_pool->res_list_tfe_out[j]; + INIT_LIST_HEAD(&res_list_tfe_out->list); + } + + /* init context pool */ + INIT_LIST_HEAD(&g_tfe_hw_mgr.ctx_pool[i].free_res_list); + for (j = 0; j < CAM_TFE_HW_RES_POOL_MAX; j++) { + INIT_LIST_HEAD( + &g_tfe_hw_mgr.ctx_pool[i].res_pool[j].list); + list_add_tail( + &g_tfe_hw_mgr.ctx_pool[i].res_pool[j].list, + &g_tfe_hw_mgr.ctx_pool[i].free_res_list); + } + + g_tfe_hw_mgr.ctx_pool[i].cdm_cmd = + kzalloc(((sizeof(struct cam_cdm_bl_request)) + + ((CAM_TFE_HW_ENTRIES_MAX - 1) * + sizeof(struct cam_cdm_bl_cmd))), GFP_KERNEL); + if (!g_tfe_hw_mgr.ctx_pool[i].cdm_cmd) { + rc = -ENOMEM; + CAM_ERR(CAM_ISP, "Allocation Failed for cdm command"); + goto end; + } + + g_tfe_hw_mgr.ctx_pool[i].ctx_index = i; + g_tfe_hw_mgr.ctx_pool[i].hw_mgr = &g_tfe_hw_mgr; + + cam_tasklet_init(&g_tfe_hw_mgr.mgr_common.tasklet_pool[i], + &g_tfe_hw_mgr.ctx_pool[i], i); + g_tfe_hw_mgr.ctx_pool[i].common.tasklet_info = + g_tfe_hw_mgr.mgr_common.tasklet_pool[i]; + + + init_completion(&g_tfe_hw_mgr.ctx_pool[i].config_done_complete); + list_add_tail(&g_tfe_hw_mgr.ctx_pool[i].list, + &g_tfe_hw_mgr.free_ctx_list); + } + + /* Create Worker for tfe_hw_mgr with 10 tasks */ + rc = cam_req_mgr_workq_create("cam_tfe_worker", 10, + &g_tfe_hw_mgr.workq, CRM_WORKQ_USAGE_NON_IRQ, 0); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Unable to create worker"); + goto end; + } + + /* fill return structure */ + hw_mgr_intf->hw_mgr_priv = &g_tfe_hw_mgr; + hw_mgr_intf->hw_get_caps = cam_tfe_mgr_get_hw_caps; + hw_mgr_intf->hw_acquire = cam_tfe_mgr_acquire; + hw_mgr_intf->hw_start = cam_tfe_mgr_start_hw; + hw_mgr_intf->hw_stop = cam_tfe_mgr_stop_hw; + hw_mgr_intf->hw_read = cam_tfe_mgr_read; + hw_mgr_intf->hw_write = cam_tfe_mgr_write; + hw_mgr_intf->hw_release = cam_tfe_mgr_release_hw; + hw_mgr_intf->hw_prepare_update = cam_tfe_mgr_prepare_hw_update; + hw_mgr_intf->hw_config = cam_tfe_mgr_config_hw; + hw_mgr_intf->hw_cmd = cam_tfe_mgr_cmd; + hw_mgr_intf->hw_reset = cam_tfe_mgr_reset; + hw_mgr_intf->hw_dump = cam_tfe_mgr_dump; + + if (iommu_hdl) + *iommu_hdl = g_tfe_hw_mgr.mgr_common.img_iommu_hdl; + + cam_tfe_hw_mgr_debug_register(); + CAM_DBG(CAM_ISP, "Exit"); + + return 0; +end: + if (rc) { + for (i = 0; i < CAM_TFE_CTX_MAX; i++) { + cam_tasklet_deinit( + &g_tfe_hw_mgr.mgr_common.tasklet_pool[i]); + kfree(g_tfe_hw_mgr.ctx_pool[i].cdm_cmd); + g_tfe_hw_mgr.ctx_pool[i].cdm_cmd = NULL; + g_tfe_hw_mgr.ctx_pool[i].common.tasklet_info = NULL; + } + } + cam_smmu_destroy_handle( + g_tfe_hw_mgr.mgr_common.img_iommu_hdl_secure); + g_tfe_hw_mgr.mgr_common.img_iommu_hdl_secure = -1; +secure_fail: + cam_smmu_destroy_handle(g_tfe_hw_mgr.mgr_common.img_iommu_hdl); + g_tfe_hw_mgr.mgr_common.img_iommu_hdl = -1; + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h new file mode 100644 index 0000000000000000000000000000000000000000..f66ea4052bd5ae02f9c4969e19668cd5b5ce56d7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_HW_MGR_H_ +#define _CAM_TFE_HW_MGR_H_ + +#include +#include +#include "cam_isp_hw_mgr.h" +#include "cam_tfe_hw_intf.h" +#include "cam_tfe_csid_hw_intf.h" +#include "cam_top_tpg_hw_intf.h" +#include "cam_tasklet_util.h" +#include "cam_cdm_intf_api.h" + + + +/* TFE resource constants */ +#define CAM_TFE_HW_IN_RES_MAX (CAM_ISP_TFE_IN_RES_MAX & 0xFF) +#define CAM_TFE_HW_OUT_RES_MAX (CAM_ISP_TFE_OUT_RES_MAX & 0xFF) +#define CAM_TFE_HW_RES_POOL_MAX 64 + +/** + * struct cam_tfe_hw_mgr_debug - contain the debug information + * + * @dentry: Debugfs entry + * @csid_debug: csid debug information + * @enable_recovery: enable recovery + * @enable_csid_recovery: enable csid recovery + * @camif_debug: enable sensor diagnosis status + * @set_tpg_pattern: tpg pattern information + * @enable_reg_dump: enable reg dump on error; + * @per_req_reg_dump: Enable per request reg dump + * + */ +struct cam_tfe_hw_mgr_debug { + struct dentry *dentry; + uint64_t csid_debug; + uint32_t enable_recovery; + uint32_t enable_csid_recovery; + uint32_t camif_debug; + uint32_t set_tpg_pattern; + uint32_t enable_reg_dump; + uint32_t per_req_reg_dump; +}; + +/** + * struct cam_tfe_hw_mgr_ctx - TFE HW manager Context object + * + * @list: used by the ctx list. + * @common: common acquired context data + * @ctx_index: acquired context id. + * @hw_mgr: tfe hw mgr which owns this context + * @ctx_in_use: flag to tell whether context is active + * @res_list_csid: csid resource list + * @res_list_tfe_in: tfe input resource list + * @res_list_tfe_out: tfe output resoruces array + * @free_res_list: free resources list for the branch node + * @res_pool: memory storage for the free resource list + * @base device base index array contain the all TFE HW + * instance associated with this context. + * @num_base number of valid base data in the base array + * @cdm_handle cdm hw acquire handle + * @cdm_ops cdm util operation pointer for building + * cdm commands + * @cdm_cmd cdm base and length request pointer + * @last_submit_bl_cmd last submiited CDM BL command data + * @config_done_complete indicator for configuration complete + * @sof_cnt sof count value per core, used for dual TFE + * @epoch_cnt epoch count value per core, used for dual TFE + * @eof_cnt eof count value per core, used for dual TFE + * @overflow_pending flat to specify the overflow is pending for the + * context + * @cdm_done flag to indicate cdm has finished writing shadow + * registers + * @is_rdi_only_context flag to specify the context has only rdi resource + * @reg_dump_buf_desc: cmd buffer descriptors for reg dump + * @num_reg_dump_buf: count of descriptors in reg_dump_buf_desc + * @applied_req_id: last request id to be applied + * @last_dump_flush_req_id last req id for which reg dump on flush was called + * @last_dump_err_req_id last req id for which reg dump on error was called + * @init_done indicate whether init hw is done + * @is_dual indicate whether context is in dual TFE mode + * @is_tpg indicate whether context use tpg + * @master_hw_idx master hardware index in dual tfe case + * @slave_hw_idx slave hardware index in dual tfe case + * @dual_tfe_irq_mismatch_cnt irq mismatch count value per core, used for + * dual TFE + * packet CSL packet from user mode driver + */ +struct cam_tfe_hw_mgr_ctx { + struct list_head list; + struct cam_isp_hw_mgr_ctx common; + + uint32_t ctx_index; + struct cam_tfe_hw_mgr *hw_mgr; + uint32_t ctx_in_use; + + struct cam_isp_hw_mgr_res res_list_tpg; + struct list_head res_list_tfe_csid; + struct list_head res_list_tfe_in; + struct cam_isp_hw_mgr_res + res_list_tfe_out[CAM_TFE_HW_OUT_RES_MAX]; + + struct list_head free_res_list; + struct cam_isp_hw_mgr_res res_pool[CAM_TFE_HW_RES_POOL_MAX]; + + struct cam_isp_ctx_base_info base[CAM_TFE_HW_NUM_MAX]; + uint32_t num_base; + uint32_t cdm_handle; + struct cam_cdm_utils_ops *cdm_ops; + struct cam_cdm_bl_request *cdm_cmd; + struct cam_cdm_bl_info last_submit_bl_cmd; + struct completion config_done_complete; + + uint32_t sof_cnt[CAM_TFE_HW_NUM_MAX]; + uint32_t epoch_cnt[CAM_TFE_HW_NUM_MAX]; + uint32_t eof_cnt[CAM_TFE_HW_NUM_MAX]; + atomic_t overflow_pending; + atomic_t cdm_done; + uint32_t is_rdi_only_context; + struct cam_cmd_buf_desc reg_dump_buf_desc[ + CAM_REG_DUMP_MAX_BUF_ENTRIES]; + uint32_t num_reg_dump_buf; + uint64_t applied_req_id; + uint64_t last_dump_flush_req_id; + uint64_t last_dump_err_req_id; + bool init_done; + bool is_dual; + bool is_tpg; + uint32_t master_hw_idx; + uint32_t slave_hw_idx; + uint32_t dual_tfe_irq_mismatch_cnt; + struct cam_packet *packet; +}; + +/** + * struct cam_tfe_hw_mgr - TFE HW Manager + * + * @mgr_common: common data for all HW managers + * @tpg_devices: tpg devices instacnce array. This will be filled by + * HW manager during the initialization. + * @csid_devices: csid device instances array. This will be filled by + * HW manager during the initialization. + * @tfe_devices: TFE device instances array. This will be filled by + * HW layer during initialization + * @cdm_reg_map commands for register dump + * @ctx_mutex: mutex for the hw context pool + * @active_ctx_cnt active context count number + * @free_ctx_list: free hw context list + * @used_ctx_list: used hw context list + * @ctx_pool: context storage + * @tfe_csid_dev_caps csid device capability stored per core + * @tfe_dev_caps tfe device capability per core + * @work q work queue for TFE hw manager + * @debug_cfg debug configuration + * @ctx_lock Spinlock for HW manager + */ +struct cam_tfe_hw_mgr { + struct cam_isp_hw_mgr mgr_common; + struct cam_hw_intf *tpg_devices[CAM_TOP_TPG_HW_NUM_MAX]; + struct cam_hw_intf *csid_devices[CAM_TFE_CSID_HW_NUM_MAX]; + struct cam_hw_intf *tfe_devices[CAM_TFE_HW_NUM_MAX]; + struct cam_soc_reg_map *cdm_reg_map[CAM_TFE_HW_NUM_MAX]; + struct mutex ctx_mutex; + atomic_t active_ctx_cnt; + struct list_head free_ctx_list; + struct list_head used_ctx_list; + struct cam_tfe_hw_mgr_ctx ctx_pool[CAM_TFE_CTX_MAX]; + + struct cam_tfe_csid_hw_caps tfe_csid_dev_caps[ + CAM_TFE_CSID_HW_NUM_MAX]; + struct cam_tfe_hw_get_hw_cap tfe_dev_caps[CAM_TFE_HW_NUM_MAX]; + struct cam_req_mgr_core_workq *workq; + struct cam_tfe_hw_mgr_debug debug_cfg; + spinlock_t ctx_lock; +}; + +/** + * struct cam_tfe_hw_event_recovery_data - Payload for the recovery procedure + * + * @error_type: Error type that causes the recovery + * @affected_core: Array of the hardware cores that are affected + * @affected_ctx: Array of the hardware contexts that are affected + * @no_of_context: Actual number of the affected context + * + */ +struct cam_tfe_hw_event_recovery_data { + uint32_t error_type; + uint32_t affected_core[CAM_TFE_HW_NUM_MAX]; + struct cam_tfe_hw_mgr_ctx *affected_ctx[CAM_TFE_CTX_MAX]; + uint32_t no_of_context; +}; + +/** + * cam_tfe_hw_mgr_init() + * + * @brief: Initialize the TFE hardware manger. This is the + * etnry functinon for the TFE HW manager. + * + * @hw_mgr_intf: TFE hardware manager object returned + * @iommu_hdl: Iommu handle to be returned + * + */ +int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl); + +#ifndef CONFIG_SPECTRA_CAMERA_TFE +int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) +{ + return 0; +} +#endif +#endif /* _CAM_TFE_HW_MGR_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..9929e4d4cf4efcf5aa50e3b504b22e1621013907 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_tasklet_util.o cam_isp_packet_parser.o +obj-$(CONFIG_SPECTRA_CAMERA) += irq_controller/ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c new file mode 100644 index 0000000000000000000000000000000000000000..7c43f331a0095aed564ca201442ff24b015c47c5 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c @@ -0,0 +1,978 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "cam_mem_mgr.h" +#include "cam_isp_hw.h" +#include "cam_vfe_hw_intf.h" +#include "cam_isp_packet_parser.h" +#include "cam_debug_util.h" + +int cam_isp_add_change_base( + struct cam_hw_prepare_update_args *prepare, + struct list_head *res_list_isp_src, + uint32_t base_idx, + struct cam_kmd_buf_info *kmd_buf_info) +{ + int rc = -EINVAL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *res; + struct cam_isp_hw_get_cmd_update get_base; + struct cam_hw_update_entry *hw_entry; + uint32_t num_ent, i; + + hw_entry = prepare->hw_update_entries; + num_ent = prepare->num_hw_update_entries; + + /* Max one hw entries required for each base */ + if (num_ent + 1 >= prepare->max_hw_update_entries) { + CAM_ERR(CAM_ISP, "Insufficient HW entries :%d %d", + num_ent, prepare->max_hw_update_entries); + return -EINVAL; + } + + list_for_each_entry(hw_mgr_res, res_list_isp_src, list) { + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) + continue; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + res = hw_mgr_res->hw_res[i]; + if (res->hw_intf->hw_idx != base_idx) + continue; + + get_base.res = res; + get_base.cmd_type = CAM_ISP_HW_CMD_GET_CHANGE_BASE; + get_base.cmd.cmd_buf_addr = kmd_buf_info->cpu_addr + + kmd_buf_info->used_bytes/4; + get_base.cmd.size = kmd_buf_info->size - + kmd_buf_info->used_bytes; + + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_CHANGE_BASE, &get_base, + sizeof(struct cam_isp_hw_get_cmd_update)); + if (rc) + return rc; + + hw_entry[num_ent].handle = kmd_buf_info->handle; + hw_entry[num_ent].len = get_base.cmd.used_bytes; + hw_entry[num_ent].offset = kmd_buf_info->offset; + + /* Marking change base as IOCFG to reapply on bubble */ + hw_entry[num_ent].flags = CAM_ISP_IOCFG_BL; + CAM_DBG(CAM_ISP, + "num_ent=%d handle=0x%x, len=%u, offset=%u", + num_ent, + hw_entry[num_ent].handle, + hw_entry[num_ent].len, + hw_entry[num_ent].offset); + + kmd_buf_info->used_bytes += get_base.cmd.used_bytes; + kmd_buf_info->offset += get_base.cmd.used_bytes; + num_ent++; + prepare->num_hw_update_entries = num_ent; + + /* return success */ + return 0; + } + } + + return rc; +} + +static int cam_isp_update_dual_config( + struct cam_hw_prepare_update_args *prepare, + struct cam_cmd_buf_desc *cmd_desc, + uint32_t split_id, + uint32_t base_idx, + struct cam_isp_hw_mgr_res *res_list_isp_out, + uint32_t size_isp_out) +{ + int rc = -EINVAL; + struct cam_isp_dual_config *dual_config; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *res; + struct cam_isp_hw_dual_isp_update_args dual_isp_update_args; + uint32_t outport_id; + uint32_t ports_plane_idx; + size_t len = 0, remain_len = 0; + uint32_t *cpu_addr; + uint32_t i, j; + + CAM_DBG(CAM_ISP, "cmd des size %d, length: %d", + cmd_desc->size, cmd_desc->length); + + rc = cam_packet_util_get_cmd_mem_addr( + cmd_desc->mem_handle, &cpu_addr, &len); + if (rc) + return rc; + + if ((len < sizeof(struct cam_isp_dual_config)) || + (cmd_desc->offset >= + (len - sizeof(struct cam_isp_dual_config)))) { + CAM_ERR(CAM_ISP, "not enough buffer provided"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + return -EINVAL; + } + remain_len = len - cmd_desc->offset; + cpu_addr += (cmd_desc->offset / 4); + dual_config = (struct cam_isp_dual_config *)cpu_addr; + + if ((dual_config->num_ports * + sizeof(struct cam_isp_dual_stripe_config)) > + (remain_len - offsetof(struct cam_isp_dual_config, stripes))) { + CAM_ERR(CAM_ISP, "not enough buffer for all the dual configs"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + return -EINVAL; + } + for (i = 0; i < dual_config->num_ports; i++) { + + if (i >= CAM_ISP_IFE_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, + "failed update for i:%d > size_isp_out:%d", + i, size_isp_out); + rc = -EINVAL; + goto end; + } + + hw_mgr_res = &res_list_isp_out[i]; + if (!hw_mgr_res) { + CAM_ERR(CAM_ISP, + "Invalid isp out resource i %d num_out_res %d", + i, dual_config->num_ports); + rc = -EINVAL; + goto end; + } + + for (j = 0; j < CAM_ISP_HW_SPLIT_MAX; j++) { + if (!hw_mgr_res->hw_res[j]) + continue; + + if (hw_mgr_res->hw_res[j]->hw_intf->hw_idx != base_idx) + continue; + + res = hw_mgr_res->hw_res[j]; + + if (res->res_id < CAM_ISP_IFE_OUT_RES_BASE || + res->res_id >= CAM_ISP_IFE_OUT_RES_MAX) + continue; + + outport_id = res->res_id & 0xFF; + + ports_plane_idx = (j * (dual_config->num_ports * + CAM_PACKET_MAX_PLANES)) + + (outport_id * CAM_PACKET_MAX_PLANES); + + if (dual_config->stripes[ports_plane_idx].port_id == 0) + continue; + + dual_isp_update_args.split_id = j; + dual_isp_update_args.res = res; + dual_isp_update_args.dual_cfg = dual_config; + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_STRIPE_UPDATE, + &dual_isp_update_args, + sizeof(struct cam_isp_hw_dual_isp_update_args)); + if (rc) + goto end; + } + } + +end: + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + return rc; +} + +int cam_isp_add_cmd_buf_update( + struct cam_isp_hw_mgr_res *hw_mgr_res, + uint32_t cmd_type, + uint32_t hw_cmd_type, + uint32_t base_idx, + uint32_t *cmd_buf_addr, + uint32_t kmd_buf_remain_size, + void *cmd_update_data, + uint32_t *bytes_used) +{ + int rc = 0; + struct cam_isp_resource_node *res; + struct cam_isp_hw_get_cmd_update cmd_update; + uint32_t i; + uint32_t total_used_bytes = 0; + + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) { + CAM_ERR(CAM_ISP, "io res id:%d not valid", + hw_mgr_res->res_type); + return -EINVAL; + } + + cmd_update.cmd_type = hw_cmd_type; + cmd_update.cmd.cmd_buf_addr = cmd_buf_addr; + cmd_update.cmd.size = kmd_buf_remain_size; + cmd_update.cmd.used_bytes = 0; + cmd_update.data = cmd_update_data; + CAM_DBG(CAM_ISP, "cmd_type %u cmd buffer 0x%pK, size %d", + cmd_update.cmd_type, + cmd_update.cmd.cmd_buf_addr, + cmd_update.cmd.size); + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + if (hw_mgr_res->hw_res[i]->hw_intf->hw_idx != base_idx) + continue; + + res = hw_mgr_res->hw_res[i]; + cmd_update.res = res; + + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + cmd_update.cmd_type, &cmd_update, + sizeof(struct cam_isp_hw_get_cmd_update)); + + if (rc) { + CAM_ERR(CAM_ISP, "get buf cmd error:%d", + res->res_id); + rc = -ENOMEM; + return rc; + } + + total_used_bytes += cmd_update.cmd.used_bytes; + } + *bytes_used = total_used_bytes; + CAM_DBG(CAM_ISP, "total_used_bytes %u", total_used_bytes); + return rc; +} + +int cam_isp_add_command_buffers( + struct cam_hw_prepare_update_args *prepare, + struct cam_kmd_buf_info *kmd_buf_info, + struct cam_isp_ctx_base_info *base_info, + cam_packet_generic_blob_handler blob_handler_cb, + struct cam_isp_hw_mgr_res *res_list_isp_out, + uint32_t size_isp_out) +{ + int rc = 0; + uint32_t cmd_meta_data, num_ent, i; + uint32_t base_idx; + enum cam_isp_hw_split_id split_id; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct cam_hw_update_entry *hw_entry; + + hw_entry = prepare->hw_update_entries; + split_id = base_info->split_id; + base_idx = base_info->idx; + + /* + * set the cmd_desc to point the first command descriptor in the + * packet + */ + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint8_t *)&prepare->packet->payload + + prepare->packet->cmd_buf_offset); + + CAM_DBG(CAM_ISP, "split id = %d, number of command buffers:%d", + split_id, prepare->packet->num_cmd_buf); + + for (i = 0; i < prepare->packet->num_cmd_buf; i++) { + num_ent = prepare->num_hw_update_entries; + if (!cmd_desc[i].length) + continue; + + /* One hw entry space required for left or right or common */ + if (num_ent + 1 >= prepare->max_hw_update_entries) { + CAM_ERR(CAM_ISP, "Insufficient HW entries :%d %d", + num_ent, prepare->max_hw_update_entries); + return -EINVAL; + } + + rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]); + if (rc) + return rc; + + cmd_meta_data = cmd_desc[i].meta_data; + + CAM_DBG(CAM_ISP, "meta type: %d, split_id: %d", + cmd_meta_data, split_id); + + switch (cmd_meta_data) { + case CAM_ISP_PACKET_META_BASE: + case CAM_ISP_PACKET_META_LEFT: + case CAM_ISP_PACKET_META_DMI_LEFT: + if (split_id == CAM_ISP_HW_SPLIT_LEFT) { + hw_entry[num_ent].len = cmd_desc[i].length; + hw_entry[num_ent].handle = + cmd_desc[i].mem_handle; + hw_entry[num_ent].offset = cmd_desc[i].offset; + CAM_DBG(CAM_ISP, + "Meta_Left num_ent=%d handle=0x%x, len=%u, offset=%u", + num_ent, + hw_entry[num_ent].handle, + hw_entry[num_ent].len, + hw_entry[num_ent].offset); + hw_entry[num_ent].flags = + CAM_ISP_IQ_BL; + + num_ent++; + } + break; + case CAM_ISP_PACKET_META_RIGHT: + case CAM_ISP_PACKET_META_DMI_RIGHT: + if (split_id == CAM_ISP_HW_SPLIT_RIGHT) { + hw_entry[num_ent].len = cmd_desc[i].length; + hw_entry[num_ent].handle = + cmd_desc[i].mem_handle; + hw_entry[num_ent].offset = cmd_desc[i].offset; + CAM_DBG(CAM_ISP, + "Meta_Right num_ent=%d handle=0x%x, len=%u, offset=%u", + num_ent, + hw_entry[num_ent].handle, + hw_entry[num_ent].len, + hw_entry[num_ent].offset); + hw_entry[num_ent].flags = + CAM_ISP_IQ_BL; + num_ent++; + } + break; + case CAM_ISP_PACKET_META_COMMON: + case CAM_ISP_PACKET_META_DMI_COMMON: + hw_entry[num_ent].len = cmd_desc[i].length; + hw_entry[num_ent].handle = + cmd_desc[i].mem_handle; + hw_entry[num_ent].offset = cmd_desc[i].offset; + CAM_DBG(CAM_ISP, + "Meta_Common num_ent=%d handle=0x%x, len=%u, offset=%u", + num_ent, + hw_entry[num_ent].handle, + hw_entry[num_ent].len, + hw_entry[num_ent].offset); + hw_entry[num_ent].flags = CAM_ISP_IQ_BL; + + num_ent++; + break; + case CAM_ISP_PACKET_META_DUAL_CONFIG: + rc = cam_isp_update_dual_config(prepare, + &cmd_desc[i], split_id, base_idx, + res_list_isp_out, size_isp_out); + + if (rc) + return rc; + break; + case CAM_ISP_PACKET_META_GENERIC_BLOB_LEFT: + if (split_id == CAM_ISP_HW_SPLIT_LEFT) { + struct cam_isp_generic_blob_info blob_info; + + prepare->num_hw_update_entries = num_ent; + blob_info.prepare = prepare; + blob_info.base_info = base_info; + blob_info.kmd_buf_info = kmd_buf_info; + + rc = cam_packet_util_process_generic_cmd_buffer( + &cmd_desc[i], + blob_handler_cb, + &blob_info); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in processing blobs %d", + rc); + return rc; + } + hw_entry[num_ent].flags = CAM_ISP_IQ_BL; + num_ent = prepare->num_hw_update_entries; + } + break; + case CAM_ISP_PACKET_META_GENERIC_BLOB_RIGHT: + if (split_id == CAM_ISP_HW_SPLIT_RIGHT) { + struct cam_isp_generic_blob_info blob_info; + + prepare->num_hw_update_entries = num_ent; + blob_info.prepare = prepare; + blob_info.base_info = base_info; + blob_info.kmd_buf_info = kmd_buf_info; + + rc = cam_packet_util_process_generic_cmd_buffer( + &cmd_desc[i], + blob_handler_cb, + &blob_info); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in processing blobs %d", + rc); + return rc; + } + hw_entry[num_ent].flags = CAM_ISP_IQ_BL; + num_ent = prepare->num_hw_update_entries; + } + break; + case CAM_ISP_PACKET_META_GENERIC_BLOB_COMMON: { + struct cam_isp_generic_blob_info blob_info; + + prepare->num_hw_update_entries = num_ent; + blob_info.prepare = prepare; + blob_info.base_info = base_info; + blob_info.kmd_buf_info = kmd_buf_info; + + rc = cam_packet_util_process_generic_cmd_buffer( + &cmd_desc[i], + blob_handler_cb, + &blob_info); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in processing blobs %d", rc); + return rc; + } + hw_entry[num_ent].flags = CAM_ISP_IQ_BL; + num_ent = prepare->num_hw_update_entries; + } + break; + case CAM_ISP_PACKET_META_REG_DUMP_ON_FLUSH: + case CAM_ISP_PACKET_META_REG_DUMP_ON_ERROR: + case CAM_ISP_PACKET_META_REG_DUMP_PER_REQUEST: + if (split_id == CAM_ISP_HW_SPLIT_LEFT) { + if (prepare->num_reg_dump_buf >= + CAM_REG_DUMP_MAX_BUF_ENTRIES) { + CAM_ERR(CAM_ISP, + "Descriptor count out of bounds: %d", + prepare->num_reg_dump_buf); + return -EINVAL; + } + + prepare->reg_dump_buf_desc[ + prepare->num_reg_dump_buf] = + cmd_desc[i]; + prepare->num_reg_dump_buf++; + CAM_DBG(CAM_ISP, + "Added command buffer: %d desc_count: %d", + cmd_desc[i].meta_data, + prepare->num_reg_dump_buf); + } + break; + default: + CAM_ERR(CAM_ISP, "invalid cdm command meta data %d", + cmd_meta_data); + return -EINVAL; + } + prepare->num_hw_update_entries = num_ent; + } + + return rc; +} + +int cam_isp_add_io_buffers( + int iommu_hdl, + int sec_iommu_hdl, + struct cam_hw_prepare_update_args *prepare, + uint32_t base_idx, + struct cam_kmd_buf_info *kmd_buf_info, + struct cam_isp_hw_mgr_res *res_list_isp_out, + struct list_head *res_list_ife_in_rd, + uint32_t size_isp_out, + bool fill_fence) +{ + int rc = 0; + dma_addr_t io_addr[CAM_PACKET_MAX_PLANES]; + struct cam_buf_io_cfg *io_cfg; + struct cam_isp_resource_node *res; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_get_cmd_update update_buf; + struct cam_isp_hw_get_wm_update wm_update; + struct cam_isp_hw_get_wm_update bus_rd_update; + struct cam_hw_fence_map_entry *out_map_entries; + struct cam_hw_fence_map_entry *in_map_entries; + struct cam_isp_hw_get_cmd_update secure_mode; + uint32_t kmd_buf_remain_size; + uint32_t i, j, num_out_buf, num_in_buf; + uint32_t res_id_out, res_id_in, plane_id; + uint32_t io_cfg_used_bytes, num_ent; + size_t size; + int32_t hdl; + int mmu_hdl; + bool is_buf_secure; + uint32_t mode; + + io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) + &prepare->packet->payload + + prepare->packet->io_configs_offset); + num_out_buf = 0; + num_in_buf = 0; + io_cfg_used_bytes = 0; + prepare->pf_data->packet = prepare->packet; + + /* Max one hw entries required for each base */ + if (prepare->num_hw_update_entries + 1 >= + prepare->max_hw_update_entries) { + CAM_ERR(CAM_ISP, "Insufficient HW entries :%d %d", + prepare->num_hw_update_entries, + prepare->max_hw_update_entries); + return -EINVAL; + } + + for (i = 0; i < prepare->packet->num_io_configs; i++) { + CAM_DBG(CAM_ISP, "======= io config idx %d ============", i); + CAM_DBG(CAM_REQ, + "i %d req_id %llu resource_type:%d fence:%d direction %d", + i, prepare->packet->header.request_id, + io_cfg[i].resource_type, io_cfg[i].fence, + io_cfg[i].direction); + CAM_DBG(CAM_ISP, "format: %d", io_cfg[i].format); + + if (io_cfg[i].direction == CAM_BUF_OUTPUT) { + res_id_out = io_cfg[i].resource_type & 0xFF; + if (res_id_out >= size_isp_out) { + CAM_ERR(CAM_ISP, "invalid out restype:%x", + io_cfg[i].resource_type); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, + "configure output io with fill fence %d", + fill_fence); + out_map_entries = + &prepare->out_map_entries[num_out_buf]; + if (fill_fence) { + if (num_out_buf < + prepare->max_out_map_entries) { + out_map_entries->resource_handle = + io_cfg[i].resource_type; + out_map_entries->sync_id = + io_cfg[i].fence; + num_out_buf++; + } else { + CAM_ERR(CAM_ISP, "ln_out:%d max_ln:%d", + num_out_buf, + prepare->max_out_map_entries); + return -EINVAL; + } + } + + hw_mgr_res = &res_list_isp_out[res_id_out]; + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) { + CAM_ERR(CAM_ISP, "io res id:%d not valid", + io_cfg[i].resource_type); + return -EINVAL; + } + } else if (io_cfg[i].direction == CAM_BUF_INPUT) { + res_id_in = io_cfg[i].resource_type & 0xFF; + CAM_DBG(CAM_ISP, + "configure input io with fill fence %d", + fill_fence); + if (!res_list_ife_in_rd) { + CAM_ERR(CAM_ISP, + "No ISP in Read supported"); + return -EINVAL; + } + if (!list_empty(res_list_ife_in_rd)) { + hw_mgr_res = + list_first_entry(res_list_ife_in_rd, + struct cam_isp_hw_mgr_res, list); + } else { + CAM_ERR(CAM_ISP, + "No IFE in Read resource"); + return -EINVAL; + } + in_map_entries = + &prepare->in_map_entries[num_in_buf]; + if (fill_fence) { + if (num_in_buf < prepare->max_in_map_entries) { + in_map_entries->resource_handle = + io_cfg[i].resource_type; + in_map_entries->sync_id = + io_cfg[i].fence; + num_in_buf++; + } else { + CAM_ERR(CAM_ISP, "ln_in:%d imax_ln:%d", + num_in_buf, + prepare->max_in_map_entries); + return -EINVAL; + } + } + } else { + CAM_ERR(CAM_ISP, "Invalid io config direction :%d", + io_cfg[i].direction); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "setup mem io"); + for (j = 0; j < CAM_ISP_HW_SPLIT_MAX && + io_cfg[i].direction == CAM_BUF_OUTPUT; j++) { + if (!hw_mgr_res->hw_res[j]) + continue; + + if (hw_mgr_res->hw_res[j]->hw_intf->hw_idx != base_idx) + continue; + + res = hw_mgr_res->hw_res[j]; + if (res->res_id != io_cfg[i].resource_type) { + CAM_ERR(CAM_ISP, + "wm err res id:%d io res id:%d", + res->res_id, io_cfg[i].resource_type); + return -EINVAL; + } + + memset(io_addr, 0, sizeof(io_addr)); + + for (plane_id = 0; plane_id < CAM_PACKET_MAX_PLANES; + plane_id++) { + if (!io_cfg[i].mem_handle[plane_id]) + break; + + hdl = io_cfg[i].mem_handle[plane_id]; + secure_mode.cmd_type = + CAM_ISP_HW_CMD_GET_SECURE_MODE; + secure_mode.res = res; + secure_mode.data = (void *)&mode; + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_SECURE_MODE, + &secure_mode, + sizeof( + struct cam_isp_hw_get_cmd_update)); + if (rc) + return -EINVAL; + + is_buf_secure = cam_mem_is_secure_buf(hdl); + if ((mode == CAM_SECURE_MODE_SECURE) && + is_buf_secure) { + mmu_hdl = sec_iommu_hdl; + } else if ( + (mode == CAM_SECURE_MODE_NON_SECURE) && + (!is_buf_secure)) { + mmu_hdl = iommu_hdl; + } else { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Invalid hdl: port mode[%u], buf mode[%u]", + mode, is_buf_secure); + return -EINVAL; + } + + rc = cam_mem_get_io_buf( + io_cfg[i].mem_handle[plane_id], + mmu_hdl, &io_addr[plane_id], &size); + if (rc) { + CAM_ERR(CAM_ISP, + "no io addr for plane%d", + plane_id); + rc = -ENOMEM; + return rc; + } + + /* need to update with offset */ + io_addr[plane_id] += + io_cfg[i].offsets[plane_id]; + CAM_DBG(CAM_ISP, + "get io_addr for plane %d: 0x%llx, mem_hdl=0x%x", + plane_id, io_addr[plane_id], + io_cfg[i].mem_handle[plane_id]); + + CAM_DBG(CAM_ISP, + "mmu_hdl=0x%x, size=%d, end=0x%x", + mmu_hdl, (int)size, + io_addr[plane_id]+size); + + } + if (!plane_id) { + CAM_ERR(CAM_ISP, "No valid planes for res%d", + res->res_id); + rc = -ENOMEM; + return rc; + } + + if ((kmd_buf_info->used_bytes + io_cfg_used_bytes) < + kmd_buf_info->size) { + kmd_buf_remain_size = kmd_buf_info->size - + (kmd_buf_info->used_bytes + + io_cfg_used_bytes); + } else { + CAM_ERR(CAM_ISP, + "no free kmd memory for base %d", + base_idx); + rc = -ENOMEM; + return rc; + } + update_buf.res = res; + update_buf.cmd_type = CAM_ISP_HW_CMD_GET_BUF_UPDATE; + update_buf.cmd.cmd_buf_addr = kmd_buf_info->cpu_addr + + kmd_buf_info->used_bytes/4 + + io_cfg_used_bytes/4; + wm_update.image_buf = io_addr; + wm_update.num_buf = plane_id; + wm_update.io_cfg = &io_cfg[i]; + update_buf.cmd.size = kmd_buf_remain_size; + update_buf.wm_update = &wm_update; + + CAM_DBG(CAM_ISP, "cmd buffer 0x%pK, size %d", + update_buf.cmd.cmd_buf_addr, + update_buf.cmd.size); + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_BUF_UPDATE, &update_buf, + sizeof(struct cam_isp_hw_get_cmd_update)); + + if (rc) { + CAM_ERR(CAM_ISP, "get buf cmd error:%d", + res->res_id); + rc = -ENOMEM; + return rc; + } + io_cfg_used_bytes += update_buf.cmd.used_bytes; + } + for (j = 0; j < CAM_ISP_HW_SPLIT_MAX && + io_cfg[i].direction == CAM_BUF_INPUT; j++) { + if (!hw_mgr_res->hw_res[j]) + continue; + + if (hw_mgr_res->hw_res[j]->hw_intf->hw_idx != base_idx) + continue; + + res = hw_mgr_res->hw_res[j]; + + memset(io_addr, 0, sizeof(io_addr)); + + for (plane_id = 0; plane_id < CAM_PACKET_MAX_PLANES; + plane_id++) { + if (!io_cfg[i].mem_handle[plane_id]) + break; + + hdl = io_cfg[i].mem_handle[plane_id]; + secure_mode.cmd_type = + CAM_ISP_HW_CMD_GET_SECURE_MODE; + secure_mode.res = res; + secure_mode.data = (void *)&mode; + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_SECURE_MODE, + &secure_mode, + sizeof( + struct cam_isp_hw_get_cmd_update)); + if (rc) + return -EINVAL; + + is_buf_secure = cam_mem_is_secure_buf(hdl); + if ((mode == CAM_SECURE_MODE_SECURE) && + is_buf_secure) { + mmu_hdl = sec_iommu_hdl; + } else if ( + (mode == CAM_SECURE_MODE_NON_SECURE) && + (!is_buf_secure)) { + mmu_hdl = iommu_hdl; + } else { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Invalid hdl: port mode[%u], buf mode[%u]", + mode, is_buf_secure); + return -EINVAL; + } + + rc = cam_mem_get_io_buf( + io_cfg[i].mem_handle[plane_id], + mmu_hdl, &io_addr[plane_id], &size); + if (rc) { + CAM_ERR(CAM_ISP, + "no io addr for plane%d", + plane_id); + rc = -ENOMEM; + return rc; + } + + /* need to update with offset */ + io_addr[plane_id] += + io_cfg[i].offsets[plane_id]; + CAM_DBG(CAM_ISP, + "get io_addr for plane %d: 0x%llx, mem_hdl=0x%x", + plane_id, io_addr[plane_id], + io_cfg[i].mem_handle[plane_id]); + + CAM_DBG(CAM_ISP, + "mmu_hdl=0x%x, size=%d, end=0x%x", + mmu_hdl, (int)size, + io_addr[plane_id]+size); + + } + if (!plane_id) { + CAM_ERR(CAM_ISP, "No valid planes for res%d", + res->res_id); + rc = -ENOMEM; + return rc; + } + + if ((kmd_buf_info->used_bytes + io_cfg_used_bytes) < + kmd_buf_info->size) { + kmd_buf_remain_size = kmd_buf_info->size - + (kmd_buf_info->used_bytes + + io_cfg_used_bytes); + } else { + CAM_ERR(CAM_ISP, + "no free kmd memory for base %d", + base_idx); + rc = -ENOMEM; + return rc; + } + update_buf.res = res; + update_buf.cmd_type = CAM_ISP_HW_CMD_GET_BUF_UPDATE_RM; + update_buf.cmd.cmd_buf_addr = kmd_buf_info->cpu_addr + + kmd_buf_info->used_bytes/4 + + io_cfg_used_bytes/4; + bus_rd_update.image_buf = io_addr; + bus_rd_update.num_buf = plane_id; + bus_rd_update.io_cfg = &io_cfg[i]; + update_buf.cmd.size = kmd_buf_remain_size; + update_buf.rm_update = &bus_rd_update; + + CAM_DBG(CAM_ISP, "cmd buffer 0x%pK, size %d", + update_buf.cmd.cmd_buf_addr, + update_buf.cmd.size); + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_BUF_UPDATE_RM, &update_buf, + sizeof(struct cam_isp_hw_get_cmd_update)); + + if (rc) { + CAM_ERR(CAM_ISP, "get buf cmd error:%d", + res->res_id); + rc = -ENOMEM; + return rc; + } + io_cfg_used_bytes += update_buf.cmd.used_bytes; + } + } + + CAM_DBG(CAM_ISP, "io_cfg_used_bytes %d, fill_fence %d", + io_cfg_used_bytes, fill_fence); + if (io_cfg_used_bytes) { + /* Update the HW entries */ + num_ent = prepare->num_hw_update_entries; + prepare->hw_update_entries[num_ent].handle = + kmd_buf_info->handle; + prepare->hw_update_entries[num_ent].len = io_cfg_used_bytes; + prepare->hw_update_entries[num_ent].offset = + kmd_buf_info->offset; + prepare->hw_update_entries[num_ent].flags = + CAM_ISP_IOCFG_BL; + CAM_DBG(CAM_ISP, + "num_ent=%d handle=0x%x, len=%u, offset=%u", + num_ent, + prepare->hw_update_entries[num_ent].handle, + prepare->hw_update_entries[num_ent].len, + prepare->hw_update_entries[num_ent].offset); + num_ent++; + + kmd_buf_info->used_bytes += io_cfg_used_bytes; + kmd_buf_info->offset += io_cfg_used_bytes; + prepare->num_hw_update_entries = num_ent; + } + + if (fill_fence) { + prepare->num_out_map_entries = num_out_buf; + prepare->num_in_map_entries = num_in_buf; + } + + return rc; +} + + +int cam_isp_add_reg_update( + struct cam_hw_prepare_update_args *prepare, + struct list_head *res_list_isp_src, + uint32_t base_idx, + struct cam_kmd_buf_info *kmd_buf_info) +{ + int rc = -EINVAL; + struct cam_isp_resource_node *res; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_update_entry *hw_entry; + struct cam_isp_hw_get_cmd_update get_regup; + uint32_t kmd_buf_remain_size, num_ent, i, reg_update_size; + + hw_entry = prepare->hw_update_entries; + /* Max one hw entries required for each base */ + if (prepare->num_hw_update_entries + 1 >= + prepare->max_hw_update_entries) { + CAM_ERR(CAM_ISP, "Insufficient HW entries :%d %d", + prepare->num_hw_update_entries, + prepare->max_hw_update_entries); + return -EINVAL; + } + + reg_update_size = 0; + list_for_each_entry(hw_mgr_res, res_list_isp_src, list) { + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) + continue; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + res = hw_mgr_res->hw_res[i]; + if (res->hw_intf->hw_idx != base_idx) + continue; + + if (kmd_buf_info->size > (kmd_buf_info->used_bytes + + reg_update_size)) { + kmd_buf_remain_size = kmd_buf_info->size - + (kmd_buf_info->used_bytes + + reg_update_size); + } else { + CAM_ERR(CAM_ISP, "no free mem %d %d %d", + base_idx, kmd_buf_info->size, + kmd_buf_info->used_bytes + + reg_update_size); + rc = -EINVAL; + return rc; + } + + get_regup.cmd.cmd_buf_addr = kmd_buf_info->cpu_addr + + kmd_buf_info->used_bytes/4 + + reg_update_size/4; + get_regup.cmd.size = kmd_buf_remain_size; + get_regup.cmd_type = CAM_ISP_HW_CMD_GET_REG_UPDATE; + get_regup.res = res; + + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_REG_UPDATE, &get_regup, + sizeof(struct cam_isp_hw_get_cmd_update)); + if (rc) + return rc; + + CAM_DBG(CAM_ISP, "Reg update added for res %d hw_id %d", + res->res_id, res->hw_intf->hw_idx); + reg_update_size += get_regup.cmd.used_bytes; + } + } + + if (reg_update_size) { + /* Update the HW entries */ + num_ent = prepare->num_hw_update_entries; + prepare->hw_update_entries[num_ent].handle = + kmd_buf_info->handle; + prepare->hw_update_entries[num_ent].len = reg_update_size; + prepare->hw_update_entries[num_ent].offset = + kmd_buf_info->offset; + + /* Marking reg update as IOCFG to reapply on bubble */ + prepare->hw_update_entries[num_ent].flags = + CAM_ISP_IOCFG_BL; + CAM_DBG(CAM_ISP, + "num_ent=%d handle=0x%x, len=%u, offset=%u", + num_ent, + prepare->hw_update_entries[num_ent].handle, + prepare->hw_update_entries[num_ent].len, + prepare->hw_update_entries[num_ent].offset); + num_ent++; + + kmd_buf_info->used_bytes += reg_update_size; + kmd_buf_info->offset += reg_update_size; + prepare->num_hw_update_entries = num_ent; + /* reg update is success return status 0 */ + rc = 0; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_tasklet_util.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_tasklet_util.c new file mode 100644 index 0000000000000000000000000000000000000000..356c9a0a891967e704a887946683855506e7f0f9 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_tasklet_util.c @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "cam_tasklet_util.h" +#include "cam_irq_controller.h" +#include "cam_debug_util.h" + +#define CAM_TASKLETQ_SIZE 256 + +static void cam_tasklet_action(unsigned long data); + +/** + * struct cam_tasklet_queue_cmd: + * @Brief: Structure associated with each slot in the + * tasklet queue + * + * @list: list_head member for each entry in queue + * @payload: Payload structure for the event. This will be + * passed to the handler function + * @handler_priv: Private data passed at event subscribe + * @bottom_half_handler: Function pointer for event handler in bottom + * half context + * + */ +struct cam_tasklet_queue_cmd { + struct list_head list; + void *payload; + void *handler_priv; + CAM_IRQ_HANDLER_BOTTOM_HALF bottom_half_handler; +}; + +/** + * struct cam_tasklet_info: + * @Brief: Tasklet private structure + * + * @list: list_head member for each tasklet + * @index: Instance id for the tasklet + * @tasklet_lock: Spin lock + * @tasklet_active: Atomic variable to control tasklet state + * @tasklet: Tasklet structure used to schedule bottom half + * @free_cmd_list: List of free tasklet queue cmd for use + * @used_cmd_list: List of used tasklet queue cmd + * @cmd_queue: Array of tasklet cmd for storage + * @ctx_priv: Private data passed to the handling function + * + */ +struct cam_tasklet_info { + struct list_head list; + uint32_t index; + spinlock_t tasklet_lock; + atomic_t tasklet_active; + struct tasklet_struct tasklet; + + struct list_head free_cmd_list; + struct list_head used_cmd_list; + struct cam_tasklet_queue_cmd cmd_queue[CAM_TASKLETQ_SIZE]; + + void *ctx_priv; +}; + +struct cam_irq_bh_api tasklet_bh_api = { + .bottom_half_enqueue_func = cam_tasklet_enqueue_cmd, + .get_bh_payload_func = cam_tasklet_get_cmd, + .put_bh_payload_func = cam_tasklet_put_cmd, +}; + +int cam_tasklet_get_cmd( + void *bottom_half, + void **bh_cmd) +{ + int rc = 0; + unsigned long flags; + struct cam_tasklet_info *tasklet = bottom_half; + struct cam_tasklet_queue_cmd *tasklet_cmd = NULL; + + *bh_cmd = NULL; + + if (tasklet == NULL) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "tasklet is NULL"); + return -EINVAL; + } + + if (!atomic_read(&tasklet->tasklet_active)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Tasklet idx:%d is not active", + tasklet->index); + rc = -EPIPE; + return rc; + } + + spin_lock_irqsave(&tasklet->tasklet_lock, flags); + if (list_empty(&tasklet->free_cmd_list)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No more free tasklet cmd idx:%d", + tasklet->index); + rc = -ENODEV; + goto spin_unlock; + } else { + tasklet_cmd = list_first_entry(&tasklet->free_cmd_list, + struct cam_tasklet_queue_cmd, list); + list_del_init(&(tasklet_cmd)->list); + *bh_cmd = tasklet_cmd; + } + +spin_unlock: + spin_unlock_irqrestore(&tasklet->tasklet_lock, flags); + return rc; +} + +void cam_tasklet_put_cmd( + void *bottom_half, + void **bh_cmd) +{ + unsigned long flags; + struct cam_tasklet_info *tasklet = bottom_half; + struct cam_tasklet_queue_cmd *tasklet_cmd = *bh_cmd; + + if (tasklet == NULL) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "tasklet is NULL"); + return; + } + + if (tasklet_cmd == NULL) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid tasklet_cmd"); + return; + } + + spin_lock_irqsave(&tasklet->tasklet_lock, flags); + list_del_init(&tasklet_cmd->list); + list_add_tail(&tasklet_cmd->list, &tasklet->free_cmd_list); + *bh_cmd = NULL; + spin_unlock_irqrestore(&tasklet->tasklet_lock, flags); +} + +/** + * cam_tasklet_dequeue_cmd() + * + * @brief: Initialize the tasklet info structure + * + * @hw_mgr_ctx: Private Ctx data that will be passed to the handler + * function + * @idx: Index of tasklet used as identity + * @tasklet_action: Tasklet callback function that will be called + * when tasklet runs on CPU + * + * @return: 0: Success + * Negative: Failure + */ +static int cam_tasklet_dequeue_cmd( + struct cam_tasklet_info *tasklet, + struct cam_tasklet_queue_cmd **tasklet_cmd) +{ + int rc = 0; + unsigned long flags; + + *tasklet_cmd = NULL; + + CAM_DBG(CAM_ISP, "Dequeue before lock tasklet idx:%d", tasklet->index); + spin_lock_irqsave(&tasklet->tasklet_lock, flags); + if (list_empty(&tasklet->used_cmd_list)) { + CAM_DBG(CAM_ISP, "End of list reached. Exit"); + rc = -ENODEV; + goto spin_unlock; + } else { + *tasklet_cmd = list_first_entry(&tasklet->used_cmd_list, + struct cam_tasklet_queue_cmd, list); + list_del_init(&(*tasklet_cmd)->list); + CAM_DBG(CAM_ISP, "Dequeue Successful"); + } + +spin_unlock: + spin_unlock_irqrestore(&tasklet->tasklet_lock, flags); + return rc; +} + +void cam_tasklet_enqueue_cmd( + void *bottom_half, + void *bh_cmd, + void *handler_priv, + void *evt_payload_priv, + CAM_IRQ_HANDLER_BOTTOM_HALF bottom_half_handler) +{ + unsigned long flags; + struct cam_tasklet_queue_cmd *tasklet_cmd = bh_cmd; + struct cam_tasklet_info *tasklet = bottom_half; + + if (!bottom_half) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "NULL bottom half"); + return; + } + + if (!bh_cmd) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "NULL bh cmd"); + return; + } + + if (!atomic_read(&tasklet->tasklet_active)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Tasklet is not active idx:%d", + tasklet->index); + return; + } + + CAM_DBG(CAM_ISP, "Enqueue tasklet cmd idx:%d", tasklet->index); + tasklet_cmd->bottom_half_handler = bottom_half_handler; + tasklet_cmd->payload = evt_payload_priv; + tasklet_cmd->handler_priv = handler_priv; + spin_lock_irqsave(&tasklet->tasklet_lock, flags); + list_add_tail(&tasklet_cmd->list, + &tasklet->used_cmd_list); + spin_unlock_irqrestore(&tasklet->tasklet_lock, flags); + tasklet_hi_schedule(&tasklet->tasklet); +} + +int cam_tasklet_init( + void **tasklet_info, + void *hw_mgr_ctx, + uint32_t idx) +{ + int i; + struct cam_tasklet_info *tasklet = NULL; + + tasklet = kzalloc(sizeof(struct cam_tasklet_info), GFP_KERNEL); + if (!tasklet) { + CAM_DBG(CAM_ISP, + "Error! Unable to allocate memory for tasklet"); + *tasklet_info = NULL; + return -ENOMEM; + } + + tasklet->ctx_priv = hw_mgr_ctx; + tasklet->index = idx; + spin_lock_init(&tasklet->tasklet_lock); + memset(tasklet->cmd_queue, 0, sizeof(tasklet->cmd_queue)); + INIT_LIST_HEAD(&tasklet->free_cmd_list); + INIT_LIST_HEAD(&tasklet->used_cmd_list); + for (i = 0; i < CAM_TASKLETQ_SIZE; i++) { + INIT_LIST_HEAD(&tasklet->cmd_queue[i].list); + list_add_tail(&tasklet->cmd_queue[i].list, + &tasklet->free_cmd_list); + } + tasklet_init(&tasklet->tasklet, cam_tasklet_action, + (unsigned long)tasklet); + tasklet_disable(&tasklet->tasklet); + + *tasklet_info = tasklet; + + return 0; +} + +void cam_tasklet_deinit(void **tasklet_info) +{ + struct cam_tasklet_info *tasklet = *tasklet_info; + + if (atomic_read(&tasklet->tasklet_active)) { + atomic_set(&tasklet->tasklet_active, 0); + tasklet_kill(&tasklet->tasklet); + tasklet_disable(&tasklet->tasklet); + } + kfree(tasklet); + *tasklet_info = NULL; +} + +static inline void cam_tasklet_flush(struct cam_tasklet_info *tasklet_info) +{ + cam_tasklet_action((unsigned long) tasklet_info); +} + +int cam_tasklet_start(void *tasklet_info) +{ + struct cam_tasklet_info *tasklet = tasklet_info; + int i = 0; + + if (atomic_read(&tasklet->tasklet_active)) { + CAM_ERR(CAM_ISP, "Tasklet already active idx:%d", + tasklet->index); + return -EBUSY; + } + + /* clean up the command queue first */ + for (i = 0; i < CAM_TASKLETQ_SIZE; i++) { + list_del_init(&tasklet->cmd_queue[i].list); + list_add_tail(&tasklet->cmd_queue[i].list, + &tasklet->free_cmd_list); + } + + atomic_set(&tasklet->tasklet_active, 1); + + tasklet_enable(&tasklet->tasklet); + + return 0; +} + +void cam_tasklet_stop(void *tasklet_info) +{ + struct cam_tasklet_info *tasklet = tasklet_info; + + if (!atomic_read(&tasklet->tasklet_active)) + return; + + atomic_set(&tasklet->tasklet_active, 0); + tasklet_kill(&tasklet->tasklet); + tasklet_disable(&tasklet->tasklet); + cam_tasklet_flush(tasklet); +} + +/* + * cam_tasklet_action() + * + * @brief: Process function that will be called when tasklet runs + * on CPU + * + * @data: Tasklet Info structure that is passed in tasklet_init + * + * @return: Void + */ +static void cam_tasklet_action(unsigned long data) +{ + struct cam_tasklet_info *tasklet_info = NULL; + struct cam_tasklet_queue_cmd *tasklet_cmd = NULL; + + tasklet_info = (struct cam_tasklet_info *)data; + + while (!cam_tasklet_dequeue_cmd(tasklet_info, &tasklet_cmd)) { + tasklet_cmd->bottom_half_handler(tasklet_cmd->handler_priv, + tasklet_cmd->payload); + cam_tasklet_put_cmd(tasklet_info, (void **)(&tasklet_cmd)); + } +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h new file mode 100644 index 0000000000000000000000000000000000000000..4f3d9324d24527763b3649ad5cdb44daee97452f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_ISP_HW_PARSER_H_ +#define _CAM_ISP_HW_PARSER_H_ + +#include +#include +#include "cam_isp_hw_mgr_intf.h" +#include "cam_isp_hw_mgr.h" +#include "cam_hw_intf.h" +#include "cam_packet_util.h" + +/* enum cam_isp_cdm_bl_type - isp cdm packet type*/ +enum cam_isp_cdm_bl_type { + CAM_ISP_UNUSED_BL, + CAM_ISP_IQ_BL, + CAM_ISP_IOCFG_BL, + CAM_ISP_BL_MAX, +}; + +/* + * struct cam_isp_generic_blob_info + * + * @prepare: Payload for prepare command + * @base_info: Base hardware information for the context + * @kmd_buf_info: Kmd buffer to store the custom cmd data + */ +struct cam_isp_generic_blob_info { + struct cam_hw_prepare_update_args *prepare; + struct cam_isp_ctx_base_info *base_info; + struct cam_kmd_buf_info *kmd_buf_info; +}; + +/* + * cam_isp_add_change_base() + * + * @brief Add change base in the hw entries list + * processe the isp source list get the change base from + * ISP HW instance + * + * @prepare: Contain the packet and HW update variables + * @res_list_isp_src: Resource list for IFE/VFE source + * @base_idx: Base or dev index of the IFE/VFE HW instance for + * which change change base need to be added + * @kmd_buf_info: Kmd buffer to store the change base command + * + * @return: 0 for success + * -EINVAL for Fail + */ +int cam_isp_add_change_base( + struct cam_hw_prepare_update_args *prepare, + struct list_head *res_list_isp_src, + uint32_t base_idx, + struct cam_kmd_buf_info *kmd_buf_info); + +/* + * cam_isp_add_cmd_buf_update() + * + * @brief Add command buffer in the HW entries list for given + * Blob Data. + * + * @hw_mgr_res: HW resource to get the update from + * @cmd_type: Cmd type to get update for + * @hw_cmd_type: HW Cmd type corresponding to cmd_type + * @base_idx: Base hardware index + * @cmd_buf_addr: Cpu buf addr of kmd scratch buffer + * @kmd_buf_remain_size: Remaining size left for cmd buffer update + * @cmd_update_data: Data needed by HW to process the cmd and provide + * cmd buffer + * @bytes_used: Address of the field to be populated with + * total bytes used as output to caller + * + * @return: Negative for Failure + * otherwise returns bytes used + */ +int cam_isp_add_cmd_buf_update( + struct cam_isp_hw_mgr_res *hw_mgr_res, + uint32_t cmd_type, + uint32_t hw_cmd_type, + uint32_t base_idx, + uint32_t *cmd_buf_addr, + uint32_t kmd_buf_remain_size, + void *cmd_update_data, + uint32_t *bytes_used); + +/* + * cam_isp_add_command_buffers() + * + * @brief Add command buffer in the HW entries list for given + * left or right VFE/IFE instance. + * + * @prepare: Contain the packet and HW update variables + * @kmd_buf_info: KMD buffer to store the custom cmd data + * @base_info: base hardware information + * @blob_handler_cb: Call_back_function for Meta handling + * @res_list_isp_out: IFE /VFE out resource list + * @size_isp_out: Size of the res_list_isp_out array + * + * @return: 0 for success + * Negative for Failure + */ +int cam_isp_add_command_buffers( + struct cam_hw_prepare_update_args *prepare, + struct cam_kmd_buf_info *kmd_buf_info, + struct cam_isp_ctx_base_info *base_info, + cam_packet_generic_blob_handler blob_handler_cb, + struct cam_isp_hw_mgr_res *res_list_isp_out, + uint32_t size_isp_out); + +/* + * cam_isp_add_io_buffers() + * + * @brief Add io buffer configurations in the HW entries list + * processe the io configurations based on the base + * index and update the HW entries list + * + * @iommu_hdl: Iommu handle to get the IO buf from memory manager + * @sec_iommu_hdl: Secure iommu handle to get the IO buf from + * memory manager + * @prepare: Contain the packet and HW update variables + * @base_idx: Base or dev index of the IFE/VFE HW instance + * @kmd_buf_info: Kmd buffer to store the change base command + * @res_list_isp_out: IFE /VFE out resource list + * @res_list_ife_in_rd: IFE /VFE in rd resource list + * @size_isp_out: Size of the res_list_isp_out array + * @fill_fence: If true, Fence map table will be filled + * + * @return: 0 for success + * -EINVAL for Fail + */ +int cam_isp_add_io_buffers( + int iommu_hdl, + int sec_iommu_hdl, + struct cam_hw_prepare_update_args *prepare, + uint32_t base_idx, + struct cam_kmd_buf_info *kmd_buf_info, + struct cam_isp_hw_mgr_res *res_list_isp_out, + struct list_head *res_list_ife_in_rd, + uint32_t size_isp_out, + bool fill_fence); + +/* + * cam_isp_add_reg_update() + * + * @brief Add reg update in the hw entries list + * processe the isp source list get the reg update from + * ISP HW instance + * + * @prepare: Contain the packet and HW update variables + * @res_list_isp_src: Resource list for IFE/VFE source + * @base_idx: Base or dev index of the IFE/VFE HW instance + * @kmd_buf_info: Kmd buffer to store the change base command + * @return: 0 for success + * -EINVAL for Fail + */ +int cam_isp_add_reg_update( + struct cam_hw_prepare_update_args *prepare, + struct list_head *res_list_isp_src, + uint32_t base_idx, + struct cam_kmd_buf_info *kmd_buf_info); + +#endif /*_CAM_ISP_HW_PARSER_H */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_tasklet_util.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_tasklet_util.h new file mode 100644 index 0000000000000000000000000000000000000000..22beb49ef6fca022ac0549fe85f648c6acd43acb --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_tasklet_util.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TASKLET_UTIL_H_ +#define _CAM_TASKLET_UTIL_H_ + +#include "cam_irq_controller.h" + +/* + * cam_tasklet_init() + * + * @brief: Initialize the tasklet info structure + * + * @tasklet: Tasklet to initialize + * @hw_mgr_ctx: Private Ctx data that will be passed to the handler + * function + * @idx: Index of tasklet used as identity + * + * @return: 0: Success + * Negative: Failure + */ +int cam_tasklet_init( + void **tasklet, + void *hw_mgr_ctx, + uint32_t idx); + +/* + * cam_tasklet_deinit() + * + * @brief: Deinitialize the tasklet info structure + * + * @tasklet: Tasklet to deinitialize + * + * @return: Void + */ +void cam_tasklet_deinit(void **tasklet); + +/* + * cam_tasklet_start() + * + * @brief: Enable the tasklet to be scheduled and run. + * Caller should make sure this function is called + * before trying to enqueue. + * + * @tasklet: Tasklet to start + * + * @return: 0: Success + * Negative: Failure + */ +int cam_tasklet_start(void *tasklet); + +/* + * cam_tasklet_stop() + * + * @brief: Disable the tasklet so it can no longer be scheduled. + * Need to enable again to run. + * + * @tasklet: Tasklet to stop + * + * @return: Void + */ +void cam_tasklet_stop(void *tasklet); + +/* + * cam_tasklet_enqueue_cmd() + * + * @brief: Enqueue the tasklet_cmd to used list + * + * @bottom_half: Tasklet info to enqueue onto + * @bh_cmd: Tasklet cmd used to enqueue task + * @handler_priv: Private Handler data that will be passed to the + * handler function + * @evt_payload_priv: Event payload that will be passed to the handler + * function + * @bottom_half_handler: Callback function that will be called by tasklet + * for handling event + * + * @return: Void + */ +void cam_tasklet_enqueue_cmd( + void *bottom_half, + void *bh_cmd, + void *handler_priv, + void *evt_payload_priv, + CAM_IRQ_HANDLER_BOTTOM_HALF bottom_half_handler); + +/** + * cam_tasklet_get_cmd() + * + * @brief: Get free cmd from tasklet + * + * @bottom_half: Tasklet Info structure to get cmd from + * @bh_cmd: Return tasklet_cmd pointer if successful + * + * @return: 0: Success + * Negative: Failure + */ +int cam_tasklet_get_cmd(void *bottom_half, void **bh_cmd); + +/** + * cam_tasklet_put_cmd() + * + * @brief: Put back cmd to free list + * + * @bottom_half: Tasklet Info structure to put cmd into + * @bh_cmd: tasklet_cmd pointer that needs to be put back + * + * @return: Void + */ +void cam_tasklet_put_cmd(void *bottom_half, void **bh_cmd); + +extern struct cam_irq_bh_api tasklet_bh_api; + +#endif /* _CAM_TASKLET_UTIL_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..533734128eb5e2101927dc9a6791bac895a77a55 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_irq_controller.o \ No newline at end of file diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c new file mode 100644 index 0000000000000000000000000000000000000000..5763939fd31007eae6b25b18a5a2e614c540331d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c @@ -0,0 +1,750 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "cam_io_util.h" +#include "cam_irq_controller.h" +#include "cam_debug_util.h" + +/** + * struct cam_irq_evt_handler: + * @Brief: Event handler information + * + * @priority: Priority level of this event + * @evt_bit_mask_arr: evt_bit_mask that has the bits set for IRQs to + * subscribe for + * @handler_priv: Private data that will be passed to the Top/Bottom + * Half handler function + * @top_half_handler: Top half Handler callback function + * @bottom_half_handler: Bottom half Handler callback function + * @bottom_half: Pointer to bottom_half implementation on which to + * enqueue the event for further handling + * @bottom_half_enqueue_func: + * Function used to enqueue the bottom_half event + * @list_node: list_head struct used for overall handler List + * @th_list_node: list_head struct used for top half handler List + */ +struct cam_irq_evt_handler { + enum cam_irq_priority_level priority; + uint32_t *evt_bit_mask_arr; + void *handler_priv; + CAM_IRQ_HANDLER_TOP_HALF top_half_handler; + CAM_IRQ_HANDLER_BOTTOM_HALF bottom_half_handler; + void *bottom_half; + struct cam_irq_bh_api irq_bh_api; + struct list_head list_node; + struct list_head th_list_node; + int index; +}; + +/** + * struct cam_irq_register_obj: + * @Brief: Structure containing information related to + * a particular register Set + * + * @index: Index of set in Array + * @mask_reg_offset: Offset of IRQ MASK register + * @clear_reg_offset: Offset of IRQ CLEAR register + * @status_reg_offset: Offset of IRQ STATUS register + * @top_half_enable_mask: Array of enabled bit_mask sorted by priority + * @pclear_mask: Partial mask to be cleared in case entire status + * register is not to be cleared + */ +struct cam_irq_register_obj { + uint32_t index; + uint32_t mask_reg_offset; + uint32_t clear_reg_offset; + uint32_t status_reg_offset; + uint32_t top_half_enable_mask[CAM_IRQ_PRIORITY_MAX]; + uint32_t pclear_mask; +}; + +/** + * struct cam_irq_controller: + * + * @brief: IRQ Controller structure. + * + * @name: Name of IRQ Controller block + * @mem_base: Mapped base address of register space to which + * register offsets are added to access registers + * @num_registers: Number of sets(mask/clear/status) of IRQ registers + * @irq_register_arr: Array of Register object associated with this + * Controller + * @irq_status_arr: Array of IRQ Status values + * @global_clear_offset: Offset of Global IRQ Clear register. This register + * contains the BIT that needs to be set for the CLEAR + * to take effect + * @global_clear_bitmask: Bitmask needed to be used in Global Clear register + * for Clear IRQ cmd to take effect + * @evt_handler_list_head: List of all event handlers + * @th_list_head: List of handlers sorted by priority + * @hdl_idx: Unique identity of handler assigned on Subscribe. + * Used to Unsubscribe. + * @lock: Lock for use by controller + * @clear_all: Flag to indicate whether to clear entire status + * register + */ +struct cam_irq_controller { + const char *name; + void __iomem *mem_base; + uint32_t num_registers; + struct cam_irq_register_obj *irq_register_arr; + uint32_t *irq_status_arr; + uint32_t global_clear_offset; + uint32_t global_clear_bitmask; + struct list_head evt_handler_list_head; + struct list_head th_list_head[CAM_IRQ_PRIORITY_MAX]; + uint32_t hdl_idx; + spinlock_t lock; + struct cam_irq_th_payload th_payload; + bool clear_all; +}; + +int cam_irq_controller_deinit(void **irq_controller) +{ + struct cam_irq_controller *controller = *irq_controller; + struct cam_irq_evt_handler *evt_handler = NULL; + + while (!list_empty(&controller->evt_handler_list_head)) { + evt_handler = list_first_entry( + &controller->evt_handler_list_head, + struct cam_irq_evt_handler, list_node); + list_del_init(&evt_handler->list_node); + kfree(evt_handler->evt_bit_mask_arr); + kfree(evt_handler); + } + + kfree(controller->th_payload.evt_status_arr); + kfree(controller->irq_status_arr); + kfree(controller->irq_register_arr); + kfree(controller); + *irq_controller = NULL; + return 0; +} + +int cam_irq_controller_init(const char *name, + void __iomem *mem_base, + struct cam_irq_controller_reg_info *register_info, + void **irq_controller, + bool clear_all) +{ + struct cam_irq_controller *controller = NULL; + int i, rc = 0; + + *irq_controller = NULL; + + if (!register_info->num_registers || !register_info->irq_reg_set || + !name || !mem_base) { + CAM_ERR(CAM_IRQ_CTRL, "Invalid parameters"); + rc = -EINVAL; + return rc; + } + + controller = kzalloc(sizeof(struct cam_irq_controller), GFP_KERNEL); + if (!controller) { + CAM_DBG(CAM_IRQ_CTRL, "Failed to allocate IRQ Controller"); + return -ENOMEM; + } + + controller->irq_register_arr = kzalloc(register_info->num_registers * + sizeof(struct cam_irq_register_obj), GFP_KERNEL); + if (!controller->irq_register_arr) { + CAM_DBG(CAM_IRQ_CTRL, "Failed to allocate IRQ register Arr"); + rc = -ENOMEM; + goto reg_alloc_error; + } + + controller->irq_status_arr = kzalloc(register_info->num_registers * + sizeof(uint32_t), GFP_KERNEL); + if (!controller->irq_status_arr) { + CAM_DBG(CAM_IRQ_CTRL, "Failed to allocate IRQ status Arr"); + rc = -ENOMEM; + goto status_alloc_error; + } + + controller->th_payload.evt_status_arr = + kzalloc(register_info->num_registers * sizeof(uint32_t), + GFP_KERNEL); + if (!controller->th_payload.evt_status_arr) { + CAM_DBG(CAM_IRQ_CTRL, + "Failed to allocate BH payload bit mask Arr"); + rc = -ENOMEM; + goto evt_mask_alloc_error; + } + + controller->name = name; + + CAM_DBG(CAM_IRQ_CTRL, "num_registers: %d", + register_info->num_registers); + for (i = 0; i < register_info->num_registers; i++) { + controller->irq_register_arr[i].index = i; + controller->irq_register_arr[i].mask_reg_offset = + register_info->irq_reg_set[i].mask_reg_offset; + controller->irq_register_arr[i].clear_reg_offset = + register_info->irq_reg_set[i].clear_reg_offset; + controller->irq_register_arr[i].status_reg_offset = + register_info->irq_reg_set[i].status_reg_offset; + CAM_DBG(CAM_IRQ_CTRL, "i %d mask_reg_offset: 0x%x", i, + controller->irq_register_arr[i].mask_reg_offset); + CAM_DBG(CAM_IRQ_CTRL, "i %d clear_reg_offset: 0x%x", i, + controller->irq_register_arr[i].clear_reg_offset); + CAM_DBG(CAM_IRQ_CTRL, "i %d status_reg_offset: 0x%x", i, + controller->irq_register_arr[i].status_reg_offset); + } + controller->num_registers = register_info->num_registers; + controller->global_clear_bitmask = register_info->global_clear_bitmask; + controller->global_clear_offset = register_info->global_clear_offset; + controller->mem_base = mem_base; + controller->clear_all = clear_all; + + CAM_DBG(CAM_IRQ_CTRL, "global_clear_bitmask: 0x%x", + controller->global_clear_bitmask); + CAM_DBG(CAM_IRQ_CTRL, "global_clear_offset: 0x%x", + controller->global_clear_offset); + CAM_DBG(CAM_IRQ_CTRL, "mem_base: %pK", + (void __iomem *)controller->mem_base); + + INIT_LIST_HEAD(&controller->evt_handler_list_head); + for (i = 0; i < CAM_IRQ_PRIORITY_MAX; i++) + INIT_LIST_HEAD(&controller->th_list_head[i]); + + spin_lock_init(&controller->lock); + + controller->hdl_idx = 1; + *irq_controller = controller; + + return rc; + +evt_mask_alloc_error: + kfree(controller->irq_status_arr); +status_alloc_error: + kfree(controller->irq_register_arr); +reg_alloc_error: + kfree(controller); + + return rc; +} + +int cam_irq_controller_subscribe_irq(void *irq_controller, + enum cam_irq_priority_level priority, + uint32_t *evt_bit_mask_arr, + void *handler_priv, + CAM_IRQ_HANDLER_TOP_HALF top_half_handler, + CAM_IRQ_HANDLER_BOTTOM_HALF bottom_half_handler, + void *bottom_half, + struct cam_irq_bh_api *irq_bh_api) +{ + struct cam_irq_controller *controller = irq_controller; + struct cam_irq_evt_handler *evt_handler = NULL; + int i; + int rc = 0; + uint32_t irq_mask; + unsigned long flags = 0; + bool need_lock; + + if (!controller || !handler_priv || !evt_bit_mask_arr) { + CAM_ERR(CAM_IRQ_CTRL, + "Inval params: ctlr=%pK hdl_priv=%pK bit_mask_arr=%pK", + controller, handler_priv, evt_bit_mask_arr); + return -EINVAL; + } + + if (!top_half_handler) { + CAM_ERR(CAM_IRQ_CTRL, "Missing top half handler"); + return -EINVAL; + } + + if (bottom_half_handler && + (!bottom_half || !irq_bh_api)) { + CAM_ERR(CAM_IRQ_CTRL, + "Invalid params: bh_handler=%pK bh=%pK bh_enq_f=%pK", + bottom_half_handler, + bottom_half, + irq_bh_api); + return -EINVAL; + } + + if (irq_bh_api && + (!irq_bh_api->bottom_half_enqueue_func || + !irq_bh_api->get_bh_payload_func || + !irq_bh_api->put_bh_payload_func)) { + CAM_ERR(CAM_IRQ_CTRL, + "Invalid: enqueue_func=%pK get_bh=%pK put_bh=%pK", + irq_bh_api->bottom_half_enqueue_func, + irq_bh_api->get_bh_payload_func, + irq_bh_api->put_bh_payload_func); + return -EINVAL; + } + + if (priority >= CAM_IRQ_PRIORITY_MAX) { + CAM_ERR(CAM_IRQ_CTRL, "Invalid priority=%u, max=%u", priority, + CAM_IRQ_PRIORITY_MAX); + return -EINVAL; + } + + evt_handler = kzalloc(sizeof(struct cam_irq_evt_handler), GFP_KERNEL); + if (!evt_handler) { + CAM_DBG(CAM_IRQ_CTRL, "Error allocating hlist_node"); + return -ENOMEM; + } + + evt_handler->evt_bit_mask_arr = kzalloc(sizeof(uint32_t) * + controller->num_registers, GFP_KERNEL); + if (!evt_handler->evt_bit_mask_arr) { + CAM_DBG(CAM_IRQ_CTRL, "Error allocating hlist_node"); + rc = -ENOMEM; + goto free_evt_handler; + } + + INIT_LIST_HEAD(&evt_handler->list_node); + INIT_LIST_HEAD(&evt_handler->th_list_node); + + for (i = 0; i < controller->num_registers; i++) + evt_handler->evt_bit_mask_arr[i] = evt_bit_mask_arr[i]; + + evt_handler->priority = priority; + evt_handler->handler_priv = handler_priv; + evt_handler->top_half_handler = top_half_handler; + evt_handler->bottom_half_handler = bottom_half_handler; + evt_handler->bottom_half = bottom_half; + evt_handler->index = controller->hdl_idx++; + + if (irq_bh_api) + evt_handler->irq_bh_api = *irq_bh_api; + + /* Avoid rollover to negative values */ + if (controller->hdl_idx > 0x3FFFFFFF) + controller->hdl_idx = 1; + + need_lock = !in_irq(); + if (need_lock) + spin_lock_irqsave(&controller->lock, flags); + for (i = 0; i < controller->num_registers; i++) { + controller->irq_register_arr[i].top_half_enable_mask[priority] + |= evt_bit_mask_arr[i]; + + controller->irq_register_arr[i].pclear_mask + |= evt_bit_mask_arr[i]; + + irq_mask = cam_io_r_mb(controller->mem_base + + controller->irq_register_arr[i].mask_reg_offset); + irq_mask |= evt_bit_mask_arr[i]; + + cam_io_w_mb(irq_mask, controller->mem_base + + controller->irq_register_arr[i].mask_reg_offset); + } + + list_add_tail(&evt_handler->list_node, + &controller->evt_handler_list_head); + list_add_tail(&evt_handler->th_list_node, + &controller->th_list_head[priority]); + + if (need_lock) + spin_unlock_irqrestore(&controller->lock, flags); + + return evt_handler->index; + +free_evt_handler: + kfree(evt_handler); + evt_handler = NULL; + + return rc; +} + +int cam_irq_controller_enable_irq(void *irq_controller, uint32_t handle) +{ + struct cam_irq_controller *controller = irq_controller; + struct cam_irq_evt_handler *evt_handler = NULL; + struct cam_irq_evt_handler *evt_handler_temp; + struct cam_irq_register_obj *irq_register = NULL; + enum cam_irq_priority_level priority; + unsigned long flags = 0; + unsigned int i; + uint32_t irq_mask; + uint32_t found = 0; + int rc = -EINVAL; + bool need_lock; + + if (!controller) + return rc; + + need_lock = !in_irq(); + if (need_lock) + spin_lock_irqsave(&controller->lock, flags); + + list_for_each_entry_safe(evt_handler, evt_handler_temp, + &controller->evt_handler_list_head, list_node) { + if (evt_handler->index == handle) { + CAM_DBG(CAM_IRQ_CTRL, "enable item %d", handle); + found = 1; + rc = 0; + break; + } + } + + if (!found) { + if (need_lock) + spin_unlock_irqrestore(&controller->lock, flags); + return rc; + } + + priority = evt_handler->priority; + for (i = 0; i < controller->num_registers; i++) { + irq_register = &controller->irq_register_arr[i]; + irq_register->top_half_enable_mask[priority] |= + evt_handler->evt_bit_mask_arr[i]; + + irq_mask = cam_io_r_mb(controller->mem_base + + irq_register->mask_reg_offset); + irq_mask |= evt_handler->evt_bit_mask_arr[i]; + + cam_io_w_mb(irq_mask, controller->mem_base + + controller->irq_register_arr[i].mask_reg_offset); + } + if (need_lock) + spin_unlock_irqrestore(&controller->lock, flags); + + return rc; +} + +int cam_irq_controller_disable_irq(void *irq_controller, uint32_t handle) +{ + struct cam_irq_controller *controller = irq_controller; + struct cam_irq_evt_handler *evt_handler = NULL; + struct cam_irq_evt_handler *evt_handler_temp; + struct cam_irq_register_obj *irq_register; + enum cam_irq_priority_level priority; + unsigned long flags = 0; + unsigned int i; + uint32_t irq_mask; + uint32_t found = 0; + int rc = -EINVAL; + bool need_lock; + + if (!controller) + return rc; + + need_lock = !in_irq(); + if (need_lock) + spin_lock_irqsave(&controller->lock, flags); + + list_for_each_entry_safe(evt_handler, evt_handler_temp, + &controller->evt_handler_list_head, list_node) { + if (evt_handler->index == handle) { + CAM_DBG(CAM_IRQ_CTRL, "disable item %d", handle); + found = 1; + rc = 0; + break; + } + } + + if (!found) { + if (need_lock) + spin_unlock_irqrestore(&controller->lock, flags); + return rc; + } + + priority = evt_handler->priority; + for (i = 0; i < controller->num_registers; i++) { + irq_register = &controller->irq_register_arr[i]; + irq_register->top_half_enable_mask[priority] &= + ~(evt_handler->evt_bit_mask_arr[i]); + + irq_mask = cam_io_r_mb(controller->mem_base + + irq_register->mask_reg_offset); + CAM_DBG(CAM_IRQ_CTRL, "irq_mask 0x%x before disable 0x%x", + irq_register->mask_reg_offset, irq_mask); + irq_mask &= ~(evt_handler->evt_bit_mask_arr[i]); + + cam_io_w_mb(irq_mask, controller->mem_base + + irq_register->mask_reg_offset); + CAM_DBG(CAM_IRQ_CTRL, "irq_mask 0x%x after disable 0x%x", + irq_register->mask_reg_offset, irq_mask); + + /* Clear the IRQ bits of this handler */ + cam_io_w_mb(evt_handler->evt_bit_mask_arr[i], + controller->mem_base + + irq_register->clear_reg_offset); + + if (controller->global_clear_offset) + cam_io_w_mb( + controller->global_clear_bitmask, + controller->mem_base + + controller->global_clear_offset); + } + if (need_lock) + spin_unlock_irqrestore(&controller->lock, flags); + + return rc; +} + +int cam_irq_controller_unsubscribe_irq(void *irq_controller, + uint32_t handle) +{ + struct cam_irq_controller *controller = irq_controller; + struct cam_irq_evt_handler *evt_handler = NULL; + struct cam_irq_evt_handler *evt_handler_temp; + struct cam_irq_register_obj *irq_register; + enum cam_irq_priority_level priority; + uint32_t i; + uint32_t found = 0; + uint32_t irq_mask; + unsigned long flags = 0; + int rc = -EINVAL; + bool need_lock; + + need_lock = !in_irq(); + if (need_lock) + spin_lock_irqsave(&controller->lock, flags); + + list_for_each_entry_safe(evt_handler, evt_handler_temp, + &controller->evt_handler_list_head, list_node) { + if (evt_handler->index == handle) { + CAM_DBG(CAM_IRQ_CTRL, "unsubscribe item %d", handle); + list_del_init(&evt_handler->list_node); + list_del_init(&evt_handler->th_list_node); + found = 1; + rc = 0; + break; + } + } + + if (found) { + priority = evt_handler->priority; + for (i = 0; i < controller->num_registers; i++) { + irq_register = &controller->irq_register_arr[i]; + irq_register->top_half_enable_mask[priority] &= + ~(evt_handler->evt_bit_mask_arr[i]); + + irq_mask = cam_io_r_mb(controller->mem_base + + irq_register->mask_reg_offset); + irq_mask &= ~(evt_handler->evt_bit_mask_arr[i]); + + cam_io_w_mb(irq_mask, controller->mem_base + + irq_register->mask_reg_offset); + + /* Clear the IRQ bits of this handler */ + cam_io_w_mb(evt_handler->evt_bit_mask_arr[i], + controller->mem_base + + irq_register->clear_reg_offset); + if (controller->global_clear_offset) + cam_io_w_mb( + controller->global_clear_bitmask, + controller->mem_base + + controller->global_clear_offset); + } + + kfree(evt_handler->evt_bit_mask_arr); + kfree(evt_handler); + } + + if (need_lock) + spin_unlock_irqrestore(&controller->lock, flags); + + return rc; +} + +/** + * cam_irq_controller_match_bit_mask() + * + * @Brief: This function checks if any of the enabled IRQ bits + * for a certain handler is Set in the Status values + * of the controller. + * + * @controller: IRQ Controller structure + * @evt_handler: Event handler structure + * + * @Return: True: If any interested IRQ Bit is Set + * False: Otherwise + */ +static bool cam_irq_controller_match_bit_mask( + struct cam_irq_controller *controller, + struct cam_irq_evt_handler *evt_handler) +{ + int i; + + for (i = 0; i < controller->num_registers; i++) { + if (evt_handler->evt_bit_mask_arr[i] & + controller->irq_status_arr[i]) + return true; + } + + return false; +} + +static void cam_irq_controller_th_processing( + struct cam_irq_controller *controller, + struct list_head *th_list_head) +{ + struct cam_irq_evt_handler *evt_handler = NULL; + struct cam_irq_th_payload *th_payload = &controller->th_payload; + bool is_irq_match; + int rc = -EINVAL; + int i; + void *bh_cmd = NULL; + struct cam_irq_bh_api *irq_bh_api = NULL; + + CAM_DBG(CAM_IRQ_CTRL, "Enter"); + + if (list_empty(th_list_head)) + return; + + list_for_each_entry(evt_handler, th_list_head, th_list_node) { + is_irq_match = cam_irq_controller_match_bit_mask(controller, + evt_handler); + + if (!is_irq_match) + continue; + + CAM_DBG(CAM_IRQ_CTRL, "match found"); + + cam_irq_th_payload_init(th_payload); + th_payload->handler_priv = evt_handler->handler_priv; + th_payload->num_registers = controller->num_registers; + for (i = 0; i < controller->num_registers; i++) { + th_payload->evt_status_arr[i] = + controller->irq_status_arr[i] & + evt_handler->evt_bit_mask_arr[i]; + } + + irq_bh_api = &evt_handler->irq_bh_api; + bh_cmd = NULL; + + if (evt_handler->bottom_half_handler) { + rc = irq_bh_api->get_bh_payload_func( + evt_handler->bottom_half, &bh_cmd); + if (rc || !bh_cmd) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "No payload, IRQ handling frozen for %s", + controller->name); + continue; + } + } + + /* + * irq_status_arr[0] is dummy argument passed. the entire + * status array is passed in th_payload. + */ + if (evt_handler->top_half_handler) + rc = evt_handler->top_half_handler( + controller->irq_status_arr[0], + (void *)th_payload); + + if (rc && bh_cmd) { + irq_bh_api->put_bh_payload_func( + evt_handler->bottom_half, &bh_cmd); + continue; + } + + if (evt_handler->bottom_half_handler) { + CAM_DBG(CAM_IRQ_CTRL, "Enqueuing bottom half for %s", + controller->name); + irq_bh_api->bottom_half_enqueue_func( + evt_handler->bottom_half, + bh_cmd, + evt_handler->handler_priv, + th_payload->evt_payload_priv, + evt_handler->bottom_half_handler); + } + } + + CAM_DBG(CAM_IRQ_CTRL, "Exit"); +} + +irqreturn_t cam_irq_controller_clear_and_mask(int irq_num, void *priv) +{ + struct cam_irq_controller *controller = priv; + uint32_t i = 0; + + if (!controller) + return IRQ_NONE; + + for (i = 0; i < controller->num_registers; i++) { + + cam_io_w_mb(0x0, controller->mem_base + + controller->irq_register_arr[i].clear_reg_offset); + } + + if (controller->global_clear_offset) + cam_io_w_mb(controller->global_clear_bitmask, + controller->mem_base + + controller->global_clear_offset); + + for (i = 0; i < controller->num_registers; i++) { + cam_io_w_mb(0x0, controller->mem_base + + controller->irq_register_arr[i].mask_reg_offset); + } + + return IRQ_HANDLED; +} + +irqreturn_t cam_irq_controller_handle_irq(int irq_num, void *priv) +{ + struct cam_irq_controller *controller = priv; + struct cam_irq_register_obj *irq_register; + bool need_th_processing[CAM_IRQ_PRIORITY_MAX] = {false}; + int i; + int j; + + if (!controller) + return IRQ_NONE; + + CAM_DBG(CAM_IRQ_CTRL, "locking controller %pK name %s lock %pK", + controller, controller->name, &controller->lock); + spin_lock(&controller->lock); + for (i = 0; i < controller->num_registers; i++) { + irq_register = &controller->irq_register_arr[i]; + controller->irq_status_arr[i] = cam_io_r_mb( + controller->mem_base + irq_register->status_reg_offset); + + if (controller->clear_all) + cam_io_w_mb(controller->irq_status_arr[i], + controller->mem_base + + irq_register->clear_reg_offset); + else + cam_io_w_mb( + controller->irq_register_arr[i].pclear_mask & + controller->irq_status_arr[i], + controller->mem_base + + irq_register->clear_reg_offset); + + CAM_DBG(CAM_IRQ_CTRL, "Read irq status%d (0x%x) = 0x%x", i, + controller->irq_register_arr[i].status_reg_offset, + controller->irq_status_arr[i]); + for (j = 0; j < CAM_IRQ_PRIORITY_MAX; j++) { + if (irq_register->top_half_enable_mask[j] & + controller->irq_status_arr[i]) + need_th_processing[j] = true; + CAM_DBG(CAM_IRQ_CTRL, + "i %d j %d need_th_processing = %d", + i, j, need_th_processing[j]); + } + } + + CAM_DBG(CAM_IRQ_CTRL, "Status Registers read Successful"); + + if (controller->global_clear_offset) + cam_io_w_mb(controller->global_clear_bitmask, + controller->mem_base + controller->global_clear_offset); + + CAM_DBG(CAM_IRQ_CTRL, "Status Clear done"); + + for (i = 0; i < CAM_IRQ_PRIORITY_MAX; i++) { + if (need_th_processing[i]) { + CAM_DBG(CAM_IRQ_CTRL, "Invoke TH processing"); + cam_irq_controller_th_processing(controller, + &controller->th_list_head[i]); + } + } + spin_unlock(&controller->lock); + CAM_DBG(CAM_IRQ_CTRL, "unlocked controller %pK name %s lock %pK", + controller, controller->name, &controller->lock); + + return IRQ_HANDLED; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.h new file mode 100644 index 0000000000000000000000000000000000000000..8fa0e951b71401cbd3f94c25d0893cf30bf22fa6 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.h @@ -0,0 +1,274 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_IRQ_CONTROLLER_H_ +#define _CAM_IRQ_CONTROLLER_H_ + +#include + +#define CAM_IRQ_BITS_PER_REGISTER 32 + +/* + * enum cam_irq_priority_level: + * @Brief: Priority levels for IRQ events. + * Priority_0 events will be serviced before + * Priority_1 if they these bits are set in the same + * Status Read. And so on upto Priority_4. + * + * Default Priority is Priority_4. + */ +enum cam_irq_priority_level { + CAM_IRQ_PRIORITY_0, + CAM_IRQ_PRIORITY_1, + CAM_IRQ_PRIORITY_2, + CAM_IRQ_PRIORITY_3, + CAM_IRQ_PRIORITY_4, + CAM_IRQ_PRIORITY_MAX, +}; + +/* + * struct cam_irq_register_set: + * @Brief: Structure containing offsets of IRQ related + * registers belonging to a Set + * + * @mask_reg_offset: Offset of IRQ MASK register + * @clear_reg_offset: Offset of IRQ CLEAR register + * @status_reg_offset: Offset of IRQ STATUS register + */ +struct cam_irq_register_set { + uint32_t mask_reg_offset; + uint32_t clear_reg_offset; + uint32_t status_reg_offset; +}; + +/* + * struct cam_irq_controller_reg_info: + * @Brief: Structure describing the IRQ registers + * + * @num_registers: Number of sets(mask/clear/status) of IRQ registers + * @irq_reg_set: Array of Register Set Offsets. + * Length of array = num_registers + * @global_clear_offset: Offset of Global IRQ Clear register. This register + * contains the BIT that needs to be set for the CLEAR + * to take effect + * @global_clear_bitmask: Bitmask needed to be used in Global Clear register + * for Clear IRQ cmd to take effect + */ +struct cam_irq_controller_reg_info { + uint32_t num_registers; + struct cam_irq_register_set *irq_reg_set; + uint32_t global_clear_offset; + uint32_t global_clear_bitmask; +}; + +/* + * struct cam_irq_th_payload: + * @Brief: Event payload structure. This structure will be + * passed to the Top Half handler functions. + * + * @handler_priv: Private Data of handling object set when + * subscribing to IRQ event. + * @num_registers: Length of evt_bit_mask Array below + * @evt_status_arr: Array of Status bitmask read from registers. + * Length of array = num_registers + * @evt_payload_priv: Private payload pointer which can be set by Top + * Half handler for use in Bottom Half. + */ +struct cam_irq_th_payload { + void *handler_priv; + uint32_t num_registers; + uint32_t *evt_status_arr; + void *evt_payload_priv; +}; + +/* + * cam_irq_th_payload_init() + * + * @brief: Initialize the top half payload structure + * + * @th_payload: Top Half payload structure to Initialize + * + * @return: Void + */ +static inline void cam_irq_th_payload_init( + struct cam_irq_th_payload *th_payload) { + th_payload->handler_priv = NULL; + th_payload->evt_payload_priv = NULL; +} + +typedef int (*CAM_IRQ_HANDLER_TOP_HALF)(uint32_t evt_id, + struct cam_irq_th_payload *th_payload); + +typedef int (*CAM_IRQ_HANDLER_BOTTOM_HALF)(void *handler_priv, + void *evt_payload_priv); + +typedef void (*CAM_IRQ_BOTTOM_HALF_ENQUEUE_FUNC)(void *bottom_half, + void *bh_cmd, void *handler_priv, void *evt_payload_priv, + CAM_IRQ_HANDLER_BOTTOM_HALF); + +typedef int (*CAM_IRQ_GET_TASKLET_PAYLOAD_FUNC)(void *bottom_half, + void **bh_cmd); + +typedef void (*CAM_IRQ_PUT_TASKLET_PAYLOAD_FUNC)(void *bottom_half, + void **bh_cmd); + +struct cam_irq_bh_api { + CAM_IRQ_BOTTOM_HALF_ENQUEUE_FUNC bottom_half_enqueue_func; + CAM_IRQ_GET_TASKLET_PAYLOAD_FUNC get_bh_payload_func; + CAM_IRQ_PUT_TASKLET_PAYLOAD_FUNC put_bh_payload_func; +}; + +/* + * cam_irq_controller_init() + * + * @brief: Create and Initialize IRQ Controller. + * + * @name: Name of IRQ Controller block + * @mem_base: Mapped base address of register space to which + * register offsets are added to access registers + * @register_info: Register Info structure associated with this Controller + * @irq_controller: Pointer to IRQ Controller that will be filled if + * initialization is successful + * @clear_all: Flag to indicate whether to clear entire status register + * + * @return: 0: Success + * Negative: Failure + */ +int cam_irq_controller_init(const char *name, + void __iomem *mem_base, + struct cam_irq_controller_reg_info *register_info, + void **irq_controller, + bool clear_all); + +/* + * cam_irq_controller_subscribe_irq() + * + * @brief: Subscribe to certain IRQ events. + * + * @irq_controller: Pointer to IRQ Controller that controls this event IRQ + * @priority: Priority level of these events used if multiple events + * are SET in the Status Register + * @evt_bit_mask_arr: evt_bit_mask that has the bits set for IRQs to + * subscribe for + * @handler_priv: Private data that will be passed to the Top/Bottom Half + * handler function + * @top_half_handler: Top half Handler callback function + * @bottom_half_handler: Bottom half Handler callback function + * @bottom_half: Pointer to bottom_half implementation on which to + * enqueue the event for further handling + * @bottom_half_enqueue_func: + * Function used to enqueue the bottom_half event + * + * @return: Positive: Success. Value represents handle which is + * to be used to unsubscribe + * Negative: Failure + */ +int cam_irq_controller_subscribe_irq(void *irq_controller, + enum cam_irq_priority_level priority, + uint32_t *evt_bit_mask_arr, + void *handler_priv, + CAM_IRQ_HANDLER_TOP_HALF top_half_handler, + CAM_IRQ_HANDLER_BOTTOM_HALF bottom_half_handler, + void *bottom_half, + struct cam_irq_bh_api *irq_bh_api); + +/* + * cam_irq_controller_unsubscribe_irq() + * + * @brief: Unsubscribe to IRQ events previously subscribed to. + * + * @irq_controller: Pointer to IRQ Controller that controls this event IRQ + * @handle: Handle returned on successful subscribe used to + * identify the handler object + * + * @return: 0: Success + * Negative: Failure + */ +int cam_irq_controller_unsubscribe_irq(void *irq_controller, + uint32_t handle); + +/* + * cam_irq_controller_deinit() + * + * @brief: Deinitialize IRQ Controller. + * + * @irq_controller: Pointer to IRQ Controller that needs to be + * deinitialized + * + * @return: 0: Success + * Negative: Failure + */ +int cam_irq_controller_deinit(void **irq_controller); + +/* + * cam_irq_controller_handle_irq() + * + * @brief: Function that should be registered with the IRQ line. + * This is the first function to be called when the IRQ + * is fired. It will read the Status register and Clear + * the IRQ bits. It will then call the top_half handlers + * and enqueue the result to bottom_half. + * + * @irq_num: Number of IRQ line that was set that lead to this + * function being called + * @priv: Private data registered with request_irq is passed back + * here. This private data should be the irq_controller + * structure. + * + * @return: IRQ_HANDLED/IRQ_NONE + */ +irqreturn_t cam_irq_controller_handle_irq(int irq_num, void *priv); + +/* + * cam_irq_controller_disable_irq() + * + * @brief: Disable the interrupts on given controller. + * Unsubscribe will disable the IRQ by default, so this is + * only needed if between subscribe/unsubscribe there is + * need to disable IRQ again + * + * @irq_controller: Pointer to IRQ Controller that controls the registered + * events to it. + * @handle: Handle returned on successful subscribe, used to + * identify the handler object + * + * @return: 0: events found and disabled + * Negative: events not registered on this controller + */ +int cam_irq_controller_disable_irq(void *irq_controller, uint32_t handle); + +/* + * cam_irq_controller_enable_irq() + * + * @brief: Enable the interrupts on given controller. + * Subscribe will enable the IRQ by default, so this is + * only needed if between subscribe/unsubscribe there is + * need to enable IRQ again + * + * @irq_controller: Pointer to IRQ Controller that controls the registered + * events to it. + * @handle: Handle returned on successful subscribe, used to + * identify the handler object + * + * @return: 0: events found and enabled + * Negative: events not registered on this controller + */ +int cam_irq_controller_enable_irq(void *irq_controller, uint32_t handle); + +/* + * cam_irq_controller_clear_and_mask() + * + * @brief: This function clears and masks all the irq bits + * + * @irq_num: Number of IRQ line that was set that lead to this + * function being called + * @priv: Private data registered with request_irq is passed back + * here. This private data should be the irq_controller + * structure. + * + * @return: IRQ_HANDLED/IRQ_NONE + */ +irqreturn_t cam_irq_controller_clear_and_mask(int irq_num, void *priv); +#endif /* _CAM_IRQ_CONTROLLER_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..7b2bea80ffc800b6bd83c0e4fce262c7c169e0d3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h @@ -0,0 +1,280 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_ISP_HW_MGR_INTF_H_ +#define _CAM_ISP_HW_MGR_INTF_H_ + +#include +#include +#include +#include +#include "cam_hw_mgr_intf.h" + +/* MAX IFE instance */ +#define CAM_IFE_HW_NUM_MAX 7 +#define CAM_IFE_RDI_NUM_MAX 4 +#define CAM_ISP_BW_CONFIG_V1 1 +#define CAM_ISP_BW_CONFIG_V2 2 +#define CAM_TFE_HW_NUM_MAX 3 +#define CAM_TFE_RDI_NUM_MAX 3 + +/* maximum context numbers for TFE */ +#define CAM_TFE_CTX_MAX 4 + +/* maximum context numbers for IFE */ +#define CAM_IFE_CTX_MAX 8 + +/* Appliacble vote paths for dual ife, based on no. of UAPI definitions */ +#define CAM_ISP_MAX_PER_PATH_VOTES 30 +/** + * enum cam_isp_hw_event_type - Collection of the ISP hardware events + */ +enum cam_isp_hw_event_type { + CAM_ISP_HW_EVENT_ERROR, + CAM_ISP_HW_EVENT_SOF, + CAM_ISP_HW_EVENT_REG_UPDATE, + CAM_ISP_HW_EVENT_EPOCH, + CAM_ISP_HW_EVENT_EOF, + CAM_ISP_HW_EVENT_DONE, + CAM_ISP_HW_EVENT_MAX +}; + + +/** + * enum cam_isp_hw_err_type - Collection of the ISP error types for + * ISP hardware event CAM_ISP_HW_EVENT_ERROR + */ +enum cam_isp_hw_err_type { + CAM_ISP_HW_ERROR_NONE, + CAM_ISP_HW_ERROR_OVERFLOW, + CAM_ISP_HW_ERROR_P2I_ERROR, + CAM_ISP_HW_ERROR_VIOLATION, + CAM_ISP_HW_ERROR_BUSIF_OVERFLOW, + CAM_ISP_HW_ERROR_CSID_FATAL, + CAM_ISP_HW_ERROR_MAX, +}; + +/** + * enum cam_isp_hw_stop_cmd - Specify the stop command type + */ +enum cam_isp_hw_stop_cmd { + CAM_ISP_HW_STOP_AT_FRAME_BOUNDARY, + CAM_ISP_HW_STOP_IMMEDIATELY, + CAM_ISP_HW_STOP_MAX, +}; + +/** + * struct cam_isp_stop_args - hardware stop arguments + * + * @hw_stop_cmd: Hardware stop command type information + * @stop_only Send stop only to hw drivers. No Deinit to be + * done. + * + */ +struct cam_isp_stop_args { + enum cam_isp_hw_stop_cmd hw_stop_cmd; + bool stop_only; +}; + +/** + * struct cam_isp_start_args - isp hardware start arguments + * + * @config_args: Hardware configuration commands. + * @start_only Send start only to hw drivers. No init to + * be done. + * + */ +struct cam_isp_start_args { + struct cam_hw_config_args hw_config; + bool start_only; +}; + +/** + * struct cam_isp_bw_config_internal_v2 - Bandwidth configuration + * + * @usage_type: ife hw index + * @num_paths: Number of data paths + * @axi_path per path vote info + */ +struct cam_isp_bw_config_internal_v2 { + uint32_t usage_type; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[CAM_ISP_MAX_PER_PATH_VOTES]; +}; + +/** + * struct cam_isp_bw_config_internal - Internal Bandwidth configuration + * + * @usage_type: Usage type (Single/Dual) + * @num_rdi: Number of RDI votes + * @left_pix_vote: Bandwidth vote for left ISP + * @right_pix_vote: Bandwidth vote for right ISP + * @rdi_vote: RDI bandwidth requirements + */ +struct cam_isp_bw_config_internal { + uint32_t usage_type; + uint32_t num_rdi; + struct cam_isp_bw_vote left_pix_vote; + struct cam_isp_bw_vote right_pix_vote; + struct cam_isp_bw_vote rdi_vote[CAM_IFE_RDI_NUM_MAX]; +}; + +/** + * struct cam_isp_prepare_hw_update_data - hw prepare data + * + * @isp_mgr_ctx: ISP HW manager Context for current request + * @packet_opcode_type: Packet header opcode in the packet header + * this opcode defines, packet is init packet or + * update packet + * @bw_config_version: BW config version indicator + * @bw_config: BW config information + * @bw_config_v2: BW config info for AXI bw voting v2 + * @bw_config_valid: Flag indicating whether the bw_config at the index + * is valid or not + * @reg_dump_buf_desc: cmd buffer descriptors for reg dump + * @num_reg_dump_buf: Count of descriptors in reg_dump_buf_desc + * @packet CSL packet from user mode driver + * + */ +struct cam_isp_prepare_hw_update_data { + void *isp_mgr_ctx; + uint32_t packet_opcode_type; + uint32_t bw_config_version; + struct cam_isp_bw_config_internal bw_config[CAM_IFE_HW_NUM_MAX]; + struct cam_isp_bw_config_internal_v2 bw_config_v2[CAM_IFE_HW_NUM_MAX]; + bool bw_config_valid[CAM_IFE_HW_NUM_MAX]; + struct cam_cmd_buf_desc reg_dump_buf_desc[ + CAM_REG_DUMP_MAX_BUF_ENTRIES]; + uint32_t num_reg_dump_buf; + struct cam_packet *packet; +}; + + +/** + * struct cam_isp_hw_sof_event_data - Event payload for CAM_HW_EVENT_SOF + * + * @timestamp: Time stamp for the sof event + * @boot_time: Boot time stamp for the sof event + * + */ +struct cam_isp_hw_sof_event_data { + uint64_t timestamp; + uint64_t boot_time; +}; + +/** + * struct cam_isp_hw_reg_update_event_data - Event payload for + * CAM_HW_EVENT_REG_UPDATE + * + * @timestamp: Time stamp for the reg update event + * + */ +struct cam_isp_hw_reg_update_event_data { + uint64_t timestamp; +}; + +/** + * struct cam_isp_hw_epoch_event_data - Event payload for CAM_HW_EVENT_EPOCH + * + * @timestamp: Time stamp for the epoch event + * @frame_id_meta: Frame id value corresponding to this frame + */ +struct cam_isp_hw_epoch_event_data { + uint64_t timestamp; + uint32_t frame_id_meta; +}; + +/** + * struct cam_isp_hw_done_event_data - Event payload for CAM_HW_EVENT_DONE + * + * @num_handles: Number of resource handeles + * @resource_handle: Resource handle array + * @timestamp: Timestamp for the buf done event + * + */ +struct cam_isp_hw_done_event_data { + uint32_t num_handles; + uint32_t resource_handle[ + CAM_NUM_OUT_PER_COMP_IRQ_MAX]; + uint64_t timestamp; +}; + +/** + * struct cam_isp_hw_eof_event_data - Event payload for CAM_HW_EVENT_EOF + * + * @timestamp: Timestamp for the eof event + * + */ +struct cam_isp_hw_eof_event_data { + uint64_t timestamp; +}; + +/** + * struct cam_isp_hw_error_event_data - Event payload for CAM_HW_EVENT_ERROR + * + * @error_type: Error type for the error event + * @timestamp: Timestamp for the error event + * @recovery_enabled: Identifies if the context needs to recover & reapply + * this request + * @enable_req_dump: Enable request dump on HW errors + */ +struct cam_isp_hw_error_event_data { + uint32_t error_type; + uint64_t timestamp; + bool recovery_enabled; + bool enable_req_dump; +}; + +/* enum cam_isp_hw_mgr_command - Hardware manager command type */ +enum cam_isp_hw_mgr_command { + CAM_ISP_HW_MGR_CMD_IS_RDI_ONLY_CONTEXT, + CAM_ISP_HW_MGR_CMD_PAUSE_HW, + CAM_ISP_HW_MGR_CMD_RESUME_HW, + CAM_ISP_HW_MGR_CMD_SOF_DEBUG, + CAM_ISP_HW_MGR_CMD_CTX_TYPE, + CAM_ISP_HW_MGR_GET_PACKET_OPCODE, + CAM_ISP_HW_MGR_CMD_MAX, +}; + +enum cam_isp_ctx_type { + CAM_ISP_CTX_FS2 = 1, + CAM_ISP_CTX_RDI, + CAM_ISP_CTX_PIX, + CAM_ISP_CTX_MAX, +}; +/** + * struct cam_isp_hw_cmd_args - Payload for hw manager command + * + * @cmd_type HW command type + * @cmd_data command data + * @sof_irq_enable To debug if SOF irq is enabled + * @ctx_type RDI_ONLY, PIX and RDI, or FS2 + * @packet_op_code packet opcode + */ +struct cam_isp_hw_cmd_args { + uint32_t cmd_type; + void *cmd_data; + union { + uint32_t sof_irq_enable; + uint32_t ctx_type; + uint32_t packet_op_code; + } u; +}; + + +/** + * cam_isp_hw_mgr_init() + * + * @brief: Initialization function for the ISP hardware manager + * + * @device_name_str: Device name string + * @hw_mgr: Input/output structure for the ISP hardware manager + * initialization + * @iommu_hdl: Iommu handle to be returned + */ +int cam_isp_hw_mgr_init(const char *device_name_str, + struct cam_hw_mgr_intf *hw_mgr, int *iommu_hdl); + +#endif /* __CAM_ISP_HW_MGR_INTF_H__ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..e5158b69f19bab966dcc89a8d011cdaff07acfe3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_SPECTRA_CAMERA) += top_tpg/ + +ifdef CONFIG_SPECTRA_CAMERA_TFE +obj-$(CONFIG_SPECTRA_CAMERA) += ppi_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += tfe_csid_hw/ tfe_hw/ +endif + +ifdef CONFIG_SPECTRA_CAMERA_IFE +obj-$(CONFIG_SPECTRA_CAMERA) += ife_csid_hw/ vfe_hw/ +endif diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..bc859fdce65689746a2e0ea170fcf5da2de703aa --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_ife_csid_dev.o cam_ife_csid_soc.o cam_ife_csid_core.o +obj-$(CONFIG_SPECTRA_CAMERA) += cam_ife_csid17x.o cam_ife_csid_lite17x.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170.h new file mode 100644 index 0000000000000000000000000000000000000000..714fa8ef2b3167e20eef1c5412ac4420e03b0c59 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170.h @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_IFE_CSID_170_H_ +#define _CAM_IFE_CSID_170_H_ + +#include "cam_ife_csid_core.h" + +static struct cam_ife_csid_pxl_reg_offset cam_ife_csid_170_ipp_reg_offset = { + .csid_pxl_irq_status_addr = 0x30, + .csid_pxl_irq_mask_addr = 0x34, + .csid_pxl_irq_clear_addr = 0x38, + .csid_pxl_irq_set_addr = 0x3c, + + .csid_pxl_cfg0_addr = 0x200, + .csid_pxl_cfg1_addr = 0x204, + .csid_pxl_ctrl_addr = 0x208, + .csid_pxl_frm_drop_pattern_addr = 0x20c, + .csid_pxl_frm_drop_period_addr = 0x210, + .csid_pxl_irq_subsample_pattern_addr = 0x214, + .csid_pxl_irq_subsample_period_addr = 0x218, + .csid_pxl_hcrop_addr = 0x21c, + .csid_pxl_vcrop_addr = 0x220, + .csid_pxl_pix_drop_pattern_addr = 0x224, + .csid_pxl_pix_drop_period_addr = 0x228, + .csid_pxl_line_drop_pattern_addr = 0x22c, + .csid_pxl_line_drop_period_addr = 0x230, + .csid_pxl_rst_strobes_addr = 0x240, + .csid_pxl_status_addr = 0x254, + .csid_pxl_misr_val_addr = 0x258, + .csid_pxl_format_measure_cfg0_addr = 0x270, + .csid_pxl_format_measure_cfg1_addr = 0x274, + .csid_pxl_format_measure0_addr = 0x278, + .csid_pxl_format_measure1_addr = 0x27c, + .csid_pxl_format_measure2_addr = 0x280, + .csid_pxl_timestamp_curr0_sof_addr = 0x290, + .csid_pxl_timestamp_curr1_sof_addr = 0x294, + .csid_pxl_timestamp_perv0_sof_addr = 0x298, + .csid_pxl_timestamp_perv1_sof_addr = 0x29c, + .csid_pxl_timestamp_curr0_eof_addr = 0x2a0, + .csid_pxl_timestamp_curr1_eof_addr = 0x2a4, + .csid_pxl_timestamp_perv0_eof_addr = 0x2a8, + .csid_pxl_timestamp_perv1_eof_addr = 0x2ac, + /* configurations */ + .pix_store_en_shift_val = 7, + .early_eof_en_shift_val = 29, +}; + +static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_170_rdi_0_reg_offset = { + .csid_rdi_irq_status_addr = 0x40, + .csid_rdi_irq_mask_addr = 0x44, + .csid_rdi_irq_clear_addr = 0x48, + .csid_rdi_irq_set_addr = 0x4c, + .csid_rdi_cfg0_addr = 0x300, + .csid_rdi_cfg1_addr = 0x304, + .csid_rdi_ctrl_addr = 0x308, + .csid_rdi_frm_drop_pattern_addr = 0x30c, + .csid_rdi_frm_drop_period_addr = 0x310, + .csid_rdi_irq_subsample_pattern_addr = 0x314, + .csid_rdi_irq_subsample_period_addr = 0x318, + .csid_rdi_rpp_hcrop_addr = 0x31c, + .csid_rdi_rpp_vcrop_addr = 0x320, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x324, + .csid_rdi_rpp_pix_drop_period_addr = 0x328, + .csid_rdi_rpp_line_drop_pattern_addr = 0x32c, + .csid_rdi_rpp_line_drop_period_addr = 0x330, + .csid_rdi_rst_strobes_addr = 0x340, + .csid_rdi_status_addr = 0x350, + .csid_rdi_misr_val0_addr = 0x354, + .csid_rdi_misr_val1_addr = 0x358, + .csid_rdi_misr_val2_addr = 0x35c, + .csid_rdi_misr_val3_addr = 0x360, + .csid_rdi_format_measure_cfg0_addr = 0x370, + .csid_rdi_format_measure_cfg1_addr = 0x374, + .csid_rdi_format_measure0_addr = 0x378, + .csid_rdi_format_measure1_addr = 0x37c, + .csid_rdi_format_measure2_addr = 0x380, + .csid_rdi_timestamp_curr0_sof_addr = 0x390, + .csid_rdi_timestamp_curr1_sof_addr = 0x394, + .csid_rdi_timestamp_prev0_sof_addr = 0x398, + .csid_rdi_timestamp_prev1_sof_addr = 0x39c, + .csid_rdi_timestamp_curr0_eof_addr = 0x3a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x3a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x3a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x3ac, + .csid_rdi_byte_cntr_ping_addr = 0x3e0, + .csid_rdi_byte_cntr_pong_addr = 0x3e4, +}; + +static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_170_rdi_1_reg_offset = { + .csid_rdi_irq_status_addr = 0x50, + .csid_rdi_irq_mask_addr = 0x54, + .csid_rdi_irq_clear_addr = 0x58, + .csid_rdi_irq_set_addr = 0x5c, + .csid_rdi_cfg0_addr = 0x400, + .csid_rdi_cfg1_addr = 0x404, + .csid_rdi_ctrl_addr = 0x408, + .csid_rdi_frm_drop_pattern_addr = 0x40c, + .csid_rdi_frm_drop_period_addr = 0x410, + .csid_rdi_irq_subsample_pattern_addr = 0x414, + .csid_rdi_irq_subsample_period_addr = 0x418, + .csid_rdi_rpp_hcrop_addr = 0x41c, + .csid_rdi_rpp_vcrop_addr = 0x420, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x424, + .csid_rdi_rpp_pix_drop_period_addr = 0x428, + .csid_rdi_rpp_line_drop_pattern_addr = 0x42c, + .csid_rdi_rpp_line_drop_period_addr = 0x430, + .csid_rdi_rst_strobes_addr = 0x440, + .csid_rdi_status_addr = 0x450, + .csid_rdi_misr_val0_addr = 0x454, + .csid_rdi_misr_val1_addr = 0x458, + .csid_rdi_misr_val2_addr = 0x45c, + .csid_rdi_misr_val3_addr = 0x460, + .csid_rdi_format_measure_cfg0_addr = 0x470, + .csid_rdi_format_measure_cfg1_addr = 0x474, + .csid_rdi_format_measure0_addr = 0x478, + .csid_rdi_format_measure1_addr = 0x47c, + .csid_rdi_format_measure2_addr = 0x480, + .csid_rdi_timestamp_curr0_sof_addr = 0x490, + .csid_rdi_timestamp_curr1_sof_addr = 0x494, + .csid_rdi_timestamp_prev0_sof_addr = 0x498, + .csid_rdi_timestamp_prev1_sof_addr = 0x49c, + .csid_rdi_timestamp_curr0_eof_addr = 0x4a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x4a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x4a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x4ac, + .csid_rdi_byte_cntr_ping_addr = 0x4e0, + .csid_rdi_byte_cntr_pong_addr = 0x4e4, +}; + +static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_170_rdi_2_reg_offset = { + .csid_rdi_irq_status_addr = 0x60, + .csid_rdi_irq_mask_addr = 0x64, + .csid_rdi_irq_clear_addr = 0x68, + .csid_rdi_irq_set_addr = 0x6c, + .csid_rdi_cfg0_addr = 0x500, + .csid_rdi_cfg1_addr = 0x504, + .csid_rdi_ctrl_addr = 0x508, + .csid_rdi_frm_drop_pattern_addr = 0x50c, + .csid_rdi_frm_drop_period_addr = 0x510, + .csid_rdi_irq_subsample_pattern_addr = 0x514, + .csid_rdi_irq_subsample_period_addr = 0x518, + .csid_rdi_rpp_hcrop_addr = 0x51c, + .csid_rdi_rpp_vcrop_addr = 0x520, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x524, + .csid_rdi_rpp_pix_drop_period_addr = 0x528, + .csid_rdi_rpp_line_drop_pattern_addr = 0x52c, + .csid_rdi_rpp_line_drop_period_addr = 0x530, + .csid_rdi_yuv_chroma_conversion_addr = 0x534, + .csid_rdi_rst_strobes_addr = 0x540, + .csid_rdi_status_addr = 0x550, + .csid_rdi_misr_val0_addr = 0x554, + .csid_rdi_misr_val1_addr = 0x558, + .csid_rdi_misr_val2_addr = 0x55c, + .csid_rdi_misr_val3_addr = 0x560, + .csid_rdi_format_measure_cfg0_addr = 0x570, + .csid_rdi_format_measure_cfg1_addr = 0x574, + .csid_rdi_format_measure0_addr = 0x578, + .csid_rdi_format_measure1_addr = 0x57c, + .csid_rdi_format_measure2_addr = 0x580, + .csid_rdi_timestamp_curr0_sof_addr = 0x590, + .csid_rdi_timestamp_curr1_sof_addr = 0x594, + .csid_rdi_timestamp_prev0_sof_addr = 0x598, + .csid_rdi_timestamp_prev1_sof_addr = 0x59c, + .csid_rdi_timestamp_curr0_eof_addr = 0x5a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x5a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x5a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x5ac, + .csid_rdi_byte_cntr_ping_addr = 0x5e0, + .csid_rdi_byte_cntr_pong_addr = 0x5e4, +}; + +static struct cam_ife_csid_csi2_rx_reg_offset + cam_ife_csid_170_csi2_reg_offset = { + .csid_csi2_rx_irq_status_addr = 0x20, + .csid_csi2_rx_irq_mask_addr = 0x24, + .csid_csi2_rx_irq_clear_addr = 0x28, + .csid_csi2_rx_irq_set_addr = 0x2c, + + /*CSI2 rx control */ + .csid_csi2_rx_cfg0_addr = 0x100, + .csid_csi2_rx_cfg1_addr = 0x104, + .csid_csi2_rx_capture_ctrl_addr = 0x108, + .csid_csi2_rx_rst_strobes_addr = 0x110, + .csid_csi2_rx_de_scramble_cfg0_addr = 0x114, + .csid_csi2_rx_de_scramble_cfg1_addr = 0x118, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, + .csid_csi2_rx_captured_short_pkt_0_addr = 0x128, + .csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, + .csid_csi2_rx_captured_long_pkt_0_addr = 0x130, + .csid_csi2_rx_captured_long_pkt_1_addr = 0x134, + .csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, + .csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, + .csid_csi2_rx_lane0_misr_addr = 0x150, + .csid_csi2_rx_lane1_misr_addr = 0x154, + .csid_csi2_rx_lane2_misr_addr = 0x158, + .csid_csi2_rx_lane3_misr_addr = 0x15c, + .csid_csi2_rx_total_pkts_rcvd_addr = 0x160, + .csid_csi2_rx_stats_ecc_addr = 0x164, + .csid_csi2_rx_total_crc_err_addr = 0x168, + + .csi2_rst_srb_all = 0x3FFF, + .csi2_rst_done_shift_val = 27, + .csi2_irq_mask_all = 0xFFFFFFF, + .csi2_misr_enable_shift_val = 6, + .csi2_vc_mode_shift_val = 2, + .csi2_capture_long_pkt_en_shift = 0, + .csi2_capture_short_pkt_en_shift = 1, + .csi2_capture_cphy_pkt_en_shift = 2, + .csi2_capture_long_pkt_dt_shift = 4, + .csi2_capture_long_pkt_vc_shift = 10, + .csi2_capture_short_pkt_vc_shift = 15, + .csi2_capture_cphy_pkt_dt_shift = 20, + .csi2_capture_cphy_pkt_vc_shift = 26, + .csi2_rx_phy_num_mask = 0x3, +}; + +static struct cam_ife_csid_csi2_tpg_reg_offset + cam_ife_csid_170_tpg_reg_offset = { + /*CSID TPG control */ + .csid_tpg_ctrl_addr = 0x600, + .csid_tpg_vc_cfg0_addr = 0x604, + .csid_tpg_vc_cfg1_addr = 0x608, + .csid_tpg_lfsr_seed_addr = 0x60c, + .csid_tpg_dt_n_cfg_0_addr = 0x610, + .csid_tpg_dt_n_cfg_1_addr = 0x614, + .csid_tpg_dt_n_cfg_2_addr = 0x618, + .csid_tpg_color_bars_cfg_addr = 0x640, + .csid_tpg_color_box_cfg_addr = 0x644, + .csid_tpg_common_gen_cfg_addr = 0x648, + .csid_tpg_cgen_n_cfg_addr = 0x650, + .csid_tpg_cgen_n_x0_addr = 0x654, + .csid_tpg_cgen_n_x1_addr = 0x658, + .csid_tpg_cgen_n_x2_addr = 0x65c, + .csid_tpg_cgen_n_xy_addr = 0x660, + .csid_tpg_cgen_n_y1_addr = 0x664, + .csid_tpg_cgen_n_y2_addr = 0x668, + + /* configurations */ + .tpg_dtn_cfg_offset = 0xc, + .tpg_cgen_cfg_offset = 0x20, + .tpg_cpas_ife_reg_offset = 0x28, +}; + +static struct cam_ife_csid_common_reg_offset + cam_ife_csid_170_cmn_reg_offset = { + .csid_hw_version_addr = 0x0, + .csid_cfg0_addr = 0x4, + .csid_ctrl_addr = 0x8, + .csid_reset_addr = 0xc, + .csid_rst_strobes_addr = 0x10, + + .csid_test_bus_ctrl_addr = 0x14, + .csid_top_irq_status_addr = 0x70, + .csid_top_irq_mask_addr = 0x74, + .csid_top_irq_clear_addr = 0x78, + .csid_top_irq_set_addr = 0x7c, + .csid_irq_cmd_addr = 0x80, + + /*configurations */ + .major_version = 1, + .minor_version = 7, + .version_incr = 0, + .num_rdis = 3, + .num_pix = 1, + .num_ppp = 0, + .csid_reg_rst_stb = 1, + .csid_rst_stb = 0x1e, + .csid_rst_stb_sw_all = 0x1f, + .path_rst_stb_all = 0x7f, + .path_rst_done_shift_val = 1, + .path_en_shift_val = 31, + .dt_id_shift_val = 27, + .vc_shift_val = 22, + .dt_shift_val = 16, + .fmt_shift_val = 12, + .plain_fmt_shit_val = 10, + .crop_v_en_shift_val = 6, + .crop_h_en_shift_val = 5, + .crop_shift = 16, + .ipp_irq_mask_all = 0x7FFF, + .rdi_irq_mask_all = 0x7FFF, + .ppp_irq_mask_all = 0x0, + .measure_en_hbi_vbi_cnt_mask = 0xC, + .format_measure_en_val = 1, +}; + +static struct cam_ife_csid_reg_offset cam_ife_csid_170_reg_offset = { + .cmn_reg = &cam_ife_csid_170_cmn_reg_offset, + .csi2_reg = &cam_ife_csid_170_csi2_reg_offset, + .ipp_reg = &cam_ife_csid_170_ipp_reg_offset, + .ppp_reg = NULL, + .rdi_reg = { + &cam_ife_csid_170_rdi_0_reg_offset, + &cam_ife_csid_170_rdi_1_reg_offset, + &cam_ife_csid_170_rdi_2_reg_offset, + NULL, + }, + .tpg_reg = &cam_ife_csid_170_tpg_reg_offset, +}; + +#endif /*_CAM_IFE_CSID_170_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175.h new file mode 100644 index 0000000000000000000000000000000000000000..70f96ea416d842f19495d23c512057e76d780c12 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175.h @@ -0,0 +1,346 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_IFE_CSID_175_H_ +#define _CAM_IFE_CSID_175_H_ + +#include "cam_ife_csid_core.h" + +static struct cam_ife_csid_pxl_reg_offset cam_ife_csid_175_ipp_reg_offset = { + .csid_pxl_irq_status_addr = 0x30, + .csid_pxl_irq_mask_addr = 0x34, + .csid_pxl_irq_clear_addr = 0x38, + .csid_pxl_irq_set_addr = 0x3c, + + .csid_pxl_cfg0_addr = 0x200, + .csid_pxl_cfg1_addr = 0x204, + .csid_pxl_ctrl_addr = 0x208, + .csid_pxl_frm_drop_pattern_addr = 0x20c, + .csid_pxl_frm_drop_period_addr = 0x210, + .csid_pxl_irq_subsample_pattern_addr = 0x214, + .csid_pxl_irq_subsample_period_addr = 0x218, + .csid_pxl_hcrop_addr = 0x21c, + .csid_pxl_vcrop_addr = 0x220, + .csid_pxl_pix_drop_pattern_addr = 0x224, + .csid_pxl_pix_drop_period_addr = 0x228, + .csid_pxl_line_drop_pattern_addr = 0x22c, + .csid_pxl_line_drop_period_addr = 0x230, + .csid_pxl_rst_strobes_addr = 0x240, + .csid_pxl_status_addr = 0x254, + .csid_pxl_misr_val_addr = 0x258, + .csid_pxl_format_measure_cfg0_addr = 0x270, + .csid_pxl_format_measure_cfg1_addr = 0x274, + .csid_pxl_format_measure0_addr = 0x278, + .csid_pxl_format_measure1_addr = 0x27c, + .csid_pxl_format_measure2_addr = 0x280, + .csid_pxl_timestamp_curr0_sof_addr = 0x290, + .csid_pxl_timestamp_curr1_sof_addr = 0x294, + .csid_pxl_timestamp_perv0_sof_addr = 0x298, + .csid_pxl_timestamp_perv1_sof_addr = 0x29c, + .csid_pxl_timestamp_curr0_eof_addr = 0x2a0, + .csid_pxl_timestamp_curr1_eof_addr = 0x2a4, + .csid_pxl_timestamp_perv0_eof_addr = 0x2a8, + .csid_pxl_timestamp_perv1_eof_addr = 0x2ac, + /* configurations */ + .pix_store_en_shift_val = 7, + .early_eof_en_shift_val = 29, +}; + +static struct cam_ife_csid_pxl_reg_offset cam_ife_csid_175_ppp_reg_offset = { + .csid_pxl_irq_status_addr = 0xa0, + .csid_pxl_irq_mask_addr = 0xa4, + .csid_pxl_irq_clear_addr = 0xa8, + .csid_pxl_irq_set_addr = 0xac, + + .csid_pxl_cfg0_addr = 0x700, + .csid_pxl_cfg1_addr = 0x704, + .csid_pxl_ctrl_addr = 0x708, + .csid_pxl_frm_drop_pattern_addr = 0x70c, + .csid_pxl_frm_drop_period_addr = 0x710, + .csid_pxl_irq_subsample_pattern_addr = 0x714, + .csid_pxl_irq_subsample_period_addr = 0x718, + .csid_pxl_hcrop_addr = 0x71c, + .csid_pxl_vcrop_addr = 0x720, + .csid_pxl_pix_drop_pattern_addr = 0x724, + .csid_pxl_pix_drop_period_addr = 0x728, + .csid_pxl_line_drop_pattern_addr = 0x72c, + .csid_pxl_line_drop_period_addr = 0x730, + .csid_pxl_rst_strobes_addr = 0x740, + .csid_pxl_status_addr = 0x754, + .csid_pxl_misr_val_addr = 0x758, + .csid_pxl_format_measure_cfg0_addr = 0x770, + .csid_pxl_format_measure_cfg1_addr = 0x774, + .csid_pxl_format_measure0_addr = 0x778, + .csid_pxl_format_measure1_addr = 0x77c, + .csid_pxl_format_measure2_addr = 0x780, + .csid_pxl_timestamp_curr0_sof_addr = 0x790, + .csid_pxl_timestamp_curr1_sof_addr = 0x794, + .csid_pxl_timestamp_perv0_sof_addr = 0x798, + .csid_pxl_timestamp_perv1_sof_addr = 0x79c, + .csid_pxl_timestamp_curr0_eof_addr = 0x7a0, + .csid_pxl_timestamp_curr1_eof_addr = 0x7a4, + .csid_pxl_timestamp_perv0_eof_addr = 0x7a8, + .csid_pxl_timestamp_perv1_eof_addr = 0x7ac, + /* configurations */ + .pix_store_en_shift_val = 7, + .early_eof_en_shift_val = 29, +}; + + +static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_175_rdi_0_reg_offset = { + .csid_rdi_irq_status_addr = 0x40, + .csid_rdi_irq_mask_addr = 0x44, + .csid_rdi_irq_clear_addr = 0x48, + .csid_rdi_irq_set_addr = 0x4c, + .csid_rdi_cfg0_addr = 0x300, + .csid_rdi_cfg1_addr = 0x304, + .csid_rdi_ctrl_addr = 0x308, + .csid_rdi_frm_drop_pattern_addr = 0x30c, + .csid_rdi_frm_drop_period_addr = 0x310, + .csid_rdi_irq_subsample_pattern_addr = 0x314, + .csid_rdi_irq_subsample_period_addr = 0x318, + .csid_rdi_rpp_hcrop_addr = 0x31c, + .csid_rdi_rpp_vcrop_addr = 0x320, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x324, + .csid_rdi_rpp_pix_drop_period_addr = 0x328, + .csid_rdi_rpp_line_drop_pattern_addr = 0x32c, + .csid_rdi_rpp_line_drop_period_addr = 0x330, + .csid_rdi_rst_strobes_addr = 0x340, + .csid_rdi_status_addr = 0x350, + .csid_rdi_misr_val0_addr = 0x354, + .csid_rdi_misr_val1_addr = 0x358, + .csid_rdi_misr_val2_addr = 0x35c, + .csid_rdi_misr_val3_addr = 0x360, + .csid_rdi_format_measure_cfg0_addr = 0x370, + .csid_rdi_format_measure_cfg1_addr = 0x374, + .csid_rdi_format_measure0_addr = 0x378, + .csid_rdi_format_measure1_addr = 0x37c, + .csid_rdi_format_measure2_addr = 0x380, + .csid_rdi_timestamp_curr0_sof_addr = 0x390, + .csid_rdi_timestamp_curr1_sof_addr = 0x394, + .csid_rdi_timestamp_prev0_sof_addr = 0x398, + .csid_rdi_timestamp_prev1_sof_addr = 0x39c, + .csid_rdi_timestamp_curr0_eof_addr = 0x3a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x3a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x3a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x3ac, + .csid_rdi_byte_cntr_ping_addr = 0x3e0, + .csid_rdi_byte_cntr_pong_addr = 0x3e4, +}; + +static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_175_rdi_1_reg_offset = { + .csid_rdi_irq_status_addr = 0x50, + .csid_rdi_irq_mask_addr = 0x54, + .csid_rdi_irq_clear_addr = 0x58, + .csid_rdi_irq_set_addr = 0x5c, + .csid_rdi_cfg0_addr = 0x400, + .csid_rdi_cfg1_addr = 0x404, + .csid_rdi_ctrl_addr = 0x408, + .csid_rdi_frm_drop_pattern_addr = 0x40c, + .csid_rdi_frm_drop_period_addr = 0x410, + .csid_rdi_irq_subsample_pattern_addr = 0x414, + .csid_rdi_irq_subsample_period_addr = 0x418, + .csid_rdi_rpp_hcrop_addr = 0x41c, + .csid_rdi_rpp_vcrop_addr = 0x420, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x424, + .csid_rdi_rpp_pix_drop_period_addr = 0x428, + .csid_rdi_rpp_line_drop_pattern_addr = 0x42c, + .csid_rdi_rpp_line_drop_period_addr = 0x430, + .csid_rdi_rst_strobes_addr = 0x440, + .csid_rdi_status_addr = 0x450, + .csid_rdi_misr_val0_addr = 0x454, + .csid_rdi_misr_val1_addr = 0x458, + .csid_rdi_misr_val2_addr = 0x45c, + .csid_rdi_misr_val3_addr = 0x460, + .csid_rdi_format_measure_cfg0_addr = 0x470, + .csid_rdi_format_measure_cfg1_addr = 0x474, + .csid_rdi_format_measure0_addr = 0x478, + .csid_rdi_format_measure1_addr = 0x47c, + .csid_rdi_format_measure2_addr = 0x480, + .csid_rdi_timestamp_curr0_sof_addr = 0x490, + .csid_rdi_timestamp_curr1_sof_addr = 0x494, + .csid_rdi_timestamp_prev0_sof_addr = 0x498, + .csid_rdi_timestamp_prev1_sof_addr = 0x49c, + .csid_rdi_timestamp_curr0_eof_addr = 0x4a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x4a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x4a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x4ac, + .csid_rdi_byte_cntr_ping_addr = 0x4e0, + .csid_rdi_byte_cntr_pong_addr = 0x4e4, +}; + +static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_175_rdi_2_reg_offset = { + .csid_rdi_irq_status_addr = 0x60, + .csid_rdi_irq_mask_addr = 0x64, + .csid_rdi_irq_clear_addr = 0x68, + .csid_rdi_irq_set_addr = 0x6c, + .csid_rdi_cfg0_addr = 0x500, + .csid_rdi_cfg1_addr = 0x504, + .csid_rdi_ctrl_addr = 0x508, + .csid_rdi_frm_drop_pattern_addr = 0x50c, + .csid_rdi_frm_drop_period_addr = 0x510, + .csid_rdi_irq_subsample_pattern_addr = 0x514, + .csid_rdi_irq_subsample_period_addr = 0x518, + .csid_rdi_rpp_hcrop_addr = 0x51c, + .csid_rdi_rpp_vcrop_addr = 0x520, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x524, + .csid_rdi_rpp_pix_drop_period_addr = 0x528, + .csid_rdi_rpp_line_drop_pattern_addr = 0x52c, + .csid_rdi_rpp_line_drop_period_addr = 0x530, + .csid_rdi_yuv_chroma_conversion_addr = 0x534, + .csid_rdi_rst_strobes_addr = 0x540, + .csid_rdi_status_addr = 0x550, + .csid_rdi_misr_val0_addr = 0x554, + .csid_rdi_misr_val1_addr = 0x558, + .csid_rdi_misr_val2_addr = 0x55c, + .csid_rdi_misr_val3_addr = 0x560, + .csid_rdi_format_measure_cfg0_addr = 0x570, + .csid_rdi_format_measure_cfg1_addr = 0x574, + .csid_rdi_format_measure0_addr = 0x578, + .csid_rdi_format_measure1_addr = 0x57c, + .csid_rdi_format_measure2_addr = 0x580, + .csid_rdi_timestamp_curr0_sof_addr = 0x590, + .csid_rdi_timestamp_curr1_sof_addr = 0x594, + .csid_rdi_timestamp_prev0_sof_addr = 0x598, + .csid_rdi_timestamp_prev1_sof_addr = 0x59c, + .csid_rdi_timestamp_curr0_eof_addr = 0x5a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x5a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x5a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x5ac, + .csid_rdi_byte_cntr_ping_addr = 0x5e0, + .csid_rdi_byte_cntr_pong_addr = 0x5e4, +}; + +static struct cam_ife_csid_csi2_rx_reg_offset + cam_ife_csid_175_csi2_reg_offset = { + .csid_csi2_rx_irq_status_addr = 0x20, + .csid_csi2_rx_irq_mask_addr = 0x24, + .csid_csi2_rx_irq_clear_addr = 0x28, + .csid_csi2_rx_irq_set_addr = 0x2c, + + /*CSI2 rx control */ + .csid_csi2_rx_cfg0_addr = 0x100, + .csid_csi2_rx_cfg1_addr = 0x104, + .csid_csi2_rx_capture_ctrl_addr = 0x108, + .csid_csi2_rx_rst_strobes_addr = 0x110, + .csid_csi2_rx_de_scramble_cfg0_addr = 0x114, + .csid_csi2_rx_de_scramble_cfg1_addr = 0x118, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, + .csid_csi2_rx_captured_short_pkt_0_addr = 0x128, + .csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, + .csid_csi2_rx_captured_long_pkt_0_addr = 0x130, + .csid_csi2_rx_captured_long_pkt_1_addr = 0x134, + .csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, + .csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, + .csid_csi2_rx_lane0_misr_addr = 0x150, + .csid_csi2_rx_lane1_misr_addr = 0x154, + .csid_csi2_rx_lane2_misr_addr = 0x158, + .csid_csi2_rx_lane3_misr_addr = 0x15c, + .csid_csi2_rx_total_pkts_rcvd_addr = 0x160, + .csid_csi2_rx_stats_ecc_addr = 0x164, + .csid_csi2_rx_total_crc_err_addr = 0x168, + + .csi2_rst_srb_all = 0x3FFF, + .csi2_rst_done_shift_val = 27, + .csi2_irq_mask_all = 0xFFFFFFF, + .csi2_misr_enable_shift_val = 6, + .csi2_vc_mode_shift_val = 2, + .csi2_capture_long_pkt_en_shift = 0, + .csi2_capture_short_pkt_en_shift = 1, + .csi2_capture_cphy_pkt_en_shift = 2, + .csi2_capture_long_pkt_dt_shift = 4, + .csi2_capture_long_pkt_vc_shift = 10, + .csi2_capture_short_pkt_vc_shift = 15, + .csi2_capture_cphy_pkt_dt_shift = 20, + .csi2_capture_cphy_pkt_vc_shift = 26, + .csi2_rx_phy_num_mask = 0x3, +}; + +static struct cam_ife_csid_csi2_tpg_reg_offset + cam_ife_csid_175_tpg_reg_offset = { + /*CSID TPG control */ + .csid_tpg_ctrl_addr = 0x600, + .csid_tpg_vc_cfg0_addr = 0x604, + .csid_tpg_vc_cfg1_addr = 0x608, + .csid_tpg_lfsr_seed_addr = 0x60c, + .csid_tpg_dt_n_cfg_0_addr = 0x610, + .csid_tpg_dt_n_cfg_1_addr = 0x614, + .csid_tpg_dt_n_cfg_2_addr = 0x618, + .csid_tpg_color_bars_cfg_addr = 0x640, + .csid_tpg_color_box_cfg_addr = 0x644, + .csid_tpg_common_gen_cfg_addr = 0x648, + .csid_tpg_cgen_n_cfg_addr = 0x650, + .csid_tpg_cgen_n_x0_addr = 0x654, + .csid_tpg_cgen_n_x1_addr = 0x658, + .csid_tpg_cgen_n_x2_addr = 0x65c, + .csid_tpg_cgen_n_xy_addr = 0x660, + .csid_tpg_cgen_n_y1_addr = 0x664, + .csid_tpg_cgen_n_y2_addr = 0x668, + + /* configurations */ + .tpg_dtn_cfg_offset = 0xc, + .tpg_cgen_cfg_offset = 0x20, + .tpg_cpas_ife_reg_offset = 0x28, +}; + +static struct cam_ife_csid_common_reg_offset + cam_ife_csid_175_cmn_reg_offset = { + .csid_hw_version_addr = 0x0, + .csid_cfg0_addr = 0x4, + .csid_ctrl_addr = 0x8, + .csid_reset_addr = 0xc, + .csid_rst_strobes_addr = 0x10, + + .csid_test_bus_ctrl_addr = 0x14, + .csid_top_irq_status_addr = 0x70, + .csid_top_irq_mask_addr = 0x74, + .csid_top_irq_clear_addr = 0x78, + .csid_top_irq_set_addr = 0x7c, + .csid_irq_cmd_addr = 0x80, + + /*configurations */ + .major_version = 1, + .minor_version = 7, + .version_incr = 0, + .num_rdis = 3, + .num_pix = 1, + .num_ppp = 1, + .csid_reg_rst_stb = 1, + .csid_rst_stb = 0x1e, + .csid_rst_stb_sw_all = 0x1f, + .path_rst_stb_all = 0x7f, + .path_rst_done_shift_val = 1, + .path_en_shift_val = 31, + .dt_id_shift_val = 27, + .vc_shift_val = 22, + .dt_shift_val = 16, + .fmt_shift_val = 12, + .plain_fmt_shit_val = 10, + .crop_v_en_shift_val = 6, + .crop_h_en_shift_val = 5, + .crop_shift = 16, + .ipp_irq_mask_all = 0x7FFF, + .rdi_irq_mask_all = 0x7FFF, + .ppp_irq_mask_all = 0xFFFF, + .measure_en_hbi_vbi_cnt_mask = 0xC, + .format_measure_en_val = 1, +}; + +static struct cam_ife_csid_reg_offset cam_ife_csid_175_reg_offset = { + .cmn_reg = &cam_ife_csid_175_cmn_reg_offset, + .csi2_reg = &cam_ife_csid_175_csi2_reg_offset, + .ipp_reg = &cam_ife_csid_175_ipp_reg_offset, + .ppp_reg = &cam_ife_csid_175_ppp_reg_offset, + .rdi_reg = { + &cam_ife_csid_175_rdi_0_reg_offset, + &cam_ife_csid_175_rdi_1_reg_offset, + &cam_ife_csid_175_rdi_2_reg_offset, + NULL, + }, + .tpg_reg = &cam_ife_csid_175_tpg_reg_offset, +}; + +#endif /*_CAM_IFE_CSID_175_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175_200.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175_200.h new file mode 100644 index 0000000000000000000000000000000000000000..612379ec4bdd54686d57a8cda0e600885c9ceda8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175_200.h @@ -0,0 +1,364 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_IFE_CSID_175_200_H_ +#define _CAM_IFE_CSID_175_200_H_ + +#include "cam_ife_csid_core.h" + +static struct cam_ife_csid_pxl_reg_offset + cam_ife_csid_175_200_ipp_reg_offset = { + .csid_pxl_irq_status_addr = 0x30, + .csid_pxl_irq_mask_addr = 0x34, + .csid_pxl_irq_clear_addr = 0x38, + .csid_pxl_irq_set_addr = 0x3c, + + .csid_pxl_cfg0_addr = 0x200, + .csid_pxl_cfg1_addr = 0x204, + .csid_pxl_ctrl_addr = 0x208, + .csid_pxl_frm_drop_pattern_addr = 0x20c, + .csid_pxl_frm_drop_period_addr = 0x210, + .csid_pxl_irq_subsample_pattern_addr = 0x214, + .csid_pxl_irq_subsample_period_addr = 0x218, + .csid_pxl_hcrop_addr = 0x21c, + .csid_pxl_vcrop_addr = 0x220, + .csid_pxl_pix_drop_pattern_addr = 0x224, + .csid_pxl_pix_drop_period_addr = 0x228, + .csid_pxl_line_drop_pattern_addr = 0x22c, + .csid_pxl_line_drop_period_addr = 0x230, + .csid_pxl_rst_strobes_addr = 0x240, + .csid_pxl_status_addr = 0x254, + .csid_pxl_misr_val_addr = 0x258, + .csid_pxl_format_measure_cfg0_addr = 0x270, + .csid_pxl_format_measure_cfg1_addr = 0x274, + .csid_pxl_format_measure0_addr = 0x278, + .csid_pxl_format_measure1_addr = 0x27c, + .csid_pxl_format_measure2_addr = 0x280, + .csid_pxl_timestamp_curr0_sof_addr = 0x290, + .csid_pxl_timestamp_curr1_sof_addr = 0x294, + .csid_pxl_timestamp_perv0_sof_addr = 0x298, + .csid_pxl_timestamp_perv1_sof_addr = 0x29c, + .csid_pxl_timestamp_curr0_eof_addr = 0x2a0, + .csid_pxl_timestamp_curr1_eof_addr = 0x2a4, + .csid_pxl_timestamp_perv0_eof_addr = 0x2a8, + .csid_pxl_timestamp_perv1_eof_addr = 0x2ac, + /* configurations */ + .pix_store_en_shift_val = 7, + .early_eof_en_shift_val = 29, + .quad_cfa_bin_en_shift_val = 30, + .ccif_violation_en = 1, +}; + +static struct cam_ife_csid_pxl_reg_offset + cam_ife_csid_175_200_ppp_reg_offset = { + .csid_pxl_irq_status_addr = 0xa0, + .csid_pxl_irq_mask_addr = 0xa4, + .csid_pxl_irq_clear_addr = 0xa8, + .csid_pxl_irq_set_addr = 0xac, + + .csid_pxl_cfg0_addr = 0x700, + .csid_pxl_cfg1_addr = 0x704, + .csid_pxl_ctrl_addr = 0x708, + .csid_pxl_frm_drop_pattern_addr = 0x70c, + .csid_pxl_frm_drop_period_addr = 0x710, + .csid_pxl_irq_subsample_pattern_addr = 0x714, + .csid_pxl_irq_subsample_period_addr = 0x718, + .csid_pxl_hcrop_addr = 0x71c, + .csid_pxl_vcrop_addr = 0x720, + .csid_pxl_pix_drop_pattern_addr = 0x724, + .csid_pxl_pix_drop_period_addr = 0x728, + .csid_pxl_line_drop_pattern_addr = 0x72c, + .csid_pxl_line_drop_period_addr = 0x730, + .csid_pxl_rst_strobes_addr = 0x740, + .csid_pxl_status_addr = 0x754, + .csid_pxl_misr_val_addr = 0x758, + .csid_pxl_format_measure_cfg0_addr = 0x770, + .csid_pxl_format_measure_cfg1_addr = 0x774, + .csid_pxl_format_measure0_addr = 0x778, + .csid_pxl_format_measure1_addr = 0x77c, + .csid_pxl_format_measure2_addr = 0x780, + .csid_pxl_timestamp_curr0_sof_addr = 0x790, + .csid_pxl_timestamp_curr1_sof_addr = 0x794, + .csid_pxl_timestamp_perv0_sof_addr = 0x798, + .csid_pxl_timestamp_perv1_sof_addr = 0x79c, + .csid_pxl_timestamp_curr0_eof_addr = 0x7a0, + .csid_pxl_timestamp_curr1_eof_addr = 0x7a4, + .csid_pxl_timestamp_perv0_eof_addr = 0x7a8, + .csid_pxl_timestamp_perv1_eof_addr = 0x7ac, + /* configurations */ + .pix_store_en_shift_val = 7, + .early_eof_en_shift_val = 29, + .ccif_violation_en = 1, +}; + + +static struct cam_ife_csid_rdi_reg_offset + cam_ife_csid_175_200_rdi_0_reg_offset = { + .csid_rdi_irq_status_addr = 0x40, + .csid_rdi_irq_mask_addr = 0x44, + .csid_rdi_irq_clear_addr = 0x48, + .csid_rdi_irq_set_addr = 0x4c, + .csid_rdi_cfg0_addr = 0x300, + .csid_rdi_cfg1_addr = 0x304, + .csid_rdi_ctrl_addr = 0x308, + .csid_rdi_frm_drop_pattern_addr = 0x30c, + .csid_rdi_frm_drop_period_addr = 0x310, + .csid_rdi_irq_subsample_pattern_addr = 0x314, + .csid_rdi_irq_subsample_period_addr = 0x318, + .csid_rdi_rpp_hcrop_addr = 0x31c, + .csid_rdi_rpp_vcrop_addr = 0x320, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x324, + .csid_rdi_rpp_pix_drop_period_addr = 0x328, + .csid_rdi_rpp_line_drop_pattern_addr = 0x32c, + .csid_rdi_rpp_line_drop_period_addr = 0x330, + .csid_rdi_rst_strobes_addr = 0x340, + .csid_rdi_status_addr = 0x350, + .csid_rdi_misr_val0_addr = 0x354, + .csid_rdi_misr_val1_addr = 0x358, + .csid_rdi_misr_val2_addr = 0x35c, + .csid_rdi_misr_val3_addr = 0x360, + .csid_rdi_format_measure_cfg0_addr = 0x370, + .csid_rdi_format_measure_cfg1_addr = 0x374, + .csid_rdi_format_measure0_addr = 0x378, + .csid_rdi_format_measure1_addr = 0x37c, + .csid_rdi_format_measure2_addr = 0x380, + .csid_rdi_timestamp_curr0_sof_addr = 0x390, + .csid_rdi_timestamp_curr1_sof_addr = 0x394, + .csid_rdi_timestamp_prev0_sof_addr = 0x398, + .csid_rdi_timestamp_prev1_sof_addr = 0x39c, + .csid_rdi_timestamp_curr0_eof_addr = 0x3a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x3a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x3a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x3ac, + .csid_rdi_byte_cntr_ping_addr = 0x3e0, + .csid_rdi_byte_cntr_pong_addr = 0x3e4, + .ccif_violation_en = 1, +}; + +static struct cam_ife_csid_rdi_reg_offset + cam_ife_csid_175_200_rdi_1_reg_offset = { + .csid_rdi_irq_status_addr = 0x50, + .csid_rdi_irq_mask_addr = 0x54, + .csid_rdi_irq_clear_addr = 0x58, + .csid_rdi_irq_set_addr = 0x5c, + .csid_rdi_cfg0_addr = 0x400, + .csid_rdi_cfg1_addr = 0x404, + .csid_rdi_ctrl_addr = 0x408, + .csid_rdi_frm_drop_pattern_addr = 0x40c, + .csid_rdi_frm_drop_period_addr = 0x410, + .csid_rdi_irq_subsample_pattern_addr = 0x414, + .csid_rdi_irq_subsample_period_addr = 0x418, + .csid_rdi_rpp_hcrop_addr = 0x41c, + .csid_rdi_rpp_vcrop_addr = 0x420, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x424, + .csid_rdi_rpp_pix_drop_period_addr = 0x428, + .csid_rdi_rpp_line_drop_pattern_addr = 0x42c, + .csid_rdi_rpp_line_drop_period_addr = 0x430, + .csid_rdi_rst_strobes_addr = 0x440, + .csid_rdi_status_addr = 0x450, + .csid_rdi_misr_val0_addr = 0x454, + .csid_rdi_misr_val1_addr = 0x458, + .csid_rdi_misr_val2_addr = 0x45c, + .csid_rdi_misr_val3_addr = 0x460, + .csid_rdi_format_measure_cfg0_addr = 0x470, + .csid_rdi_format_measure_cfg1_addr = 0x474, + .csid_rdi_format_measure0_addr = 0x478, + .csid_rdi_format_measure1_addr = 0x47c, + .csid_rdi_format_measure2_addr = 0x480, + .csid_rdi_timestamp_curr0_sof_addr = 0x490, + .csid_rdi_timestamp_curr1_sof_addr = 0x494, + .csid_rdi_timestamp_prev0_sof_addr = 0x498, + .csid_rdi_timestamp_prev1_sof_addr = 0x49c, + .csid_rdi_timestamp_curr0_eof_addr = 0x4a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x4a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x4a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x4ac, + .csid_rdi_byte_cntr_ping_addr = 0x4e0, + .csid_rdi_byte_cntr_pong_addr = 0x4e4, + .ccif_violation_en = 1, +}; + +static struct cam_ife_csid_rdi_reg_offset + cam_ife_csid_175_200_rdi_2_reg_offset = { + .csid_rdi_irq_status_addr = 0x60, + .csid_rdi_irq_mask_addr = 0x64, + .csid_rdi_irq_clear_addr = 0x68, + .csid_rdi_irq_set_addr = 0x6c, + .csid_rdi_cfg0_addr = 0x500, + .csid_rdi_cfg1_addr = 0x504, + .csid_rdi_ctrl_addr = 0x508, + .csid_rdi_frm_drop_pattern_addr = 0x50c, + .csid_rdi_frm_drop_period_addr = 0x510, + .csid_rdi_irq_subsample_pattern_addr = 0x514, + .csid_rdi_irq_subsample_period_addr = 0x518, + .csid_rdi_rpp_hcrop_addr = 0x51c, + .csid_rdi_rpp_vcrop_addr = 0x520, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x524, + .csid_rdi_rpp_pix_drop_period_addr = 0x528, + .csid_rdi_rpp_line_drop_pattern_addr = 0x52c, + .csid_rdi_rpp_line_drop_period_addr = 0x530, + .csid_rdi_yuv_chroma_conversion_addr = 0x534, + .csid_rdi_rst_strobes_addr = 0x540, + .csid_rdi_status_addr = 0x550, + .csid_rdi_misr_val0_addr = 0x554, + .csid_rdi_misr_val1_addr = 0x558, + .csid_rdi_misr_val2_addr = 0x55c, + .csid_rdi_misr_val3_addr = 0x560, + .csid_rdi_format_measure_cfg0_addr = 0x570, + .csid_rdi_format_measure_cfg1_addr = 0x574, + .csid_rdi_format_measure0_addr = 0x578, + .csid_rdi_format_measure1_addr = 0x57c, + .csid_rdi_format_measure2_addr = 0x580, + .csid_rdi_timestamp_curr0_sof_addr = 0x590, + .csid_rdi_timestamp_curr1_sof_addr = 0x594, + .csid_rdi_timestamp_prev0_sof_addr = 0x598, + .csid_rdi_timestamp_prev1_sof_addr = 0x59c, + .csid_rdi_timestamp_curr0_eof_addr = 0x5a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x5a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x5a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x5ac, + .csid_rdi_byte_cntr_ping_addr = 0x5e0, + .csid_rdi_byte_cntr_pong_addr = 0x5e4, + .ccif_violation_en = 1, +}; + +static struct cam_ife_csid_csi2_rx_reg_offset + cam_ife_csid_175_200_csi2_reg_offset = { + .csid_csi2_rx_irq_status_addr = 0x20, + .csid_csi2_rx_irq_mask_addr = 0x24, + .csid_csi2_rx_irq_clear_addr = 0x28, + .csid_csi2_rx_irq_set_addr = 0x2c, + + /*CSI2 rx control */ + .csid_csi2_rx_cfg0_addr = 0x100, + .csid_csi2_rx_cfg1_addr = 0x104, + .csid_csi2_rx_capture_ctrl_addr = 0x108, + .csid_csi2_rx_rst_strobes_addr = 0x110, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, + .csid_csi2_rx_captured_short_pkt_0_addr = 0x128, + .csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, + .csid_csi2_rx_captured_long_pkt_0_addr = 0x130, + .csid_csi2_rx_captured_long_pkt_1_addr = 0x134, + .csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, + .csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, + .csid_csi2_rx_lane0_misr_addr = 0x150, + .csid_csi2_rx_lane1_misr_addr = 0x154, + .csid_csi2_rx_lane2_misr_addr = 0x158, + .csid_csi2_rx_lane3_misr_addr = 0x15c, + .csid_csi2_rx_total_pkts_rcvd_addr = 0x160, + .csid_csi2_rx_stats_ecc_addr = 0x164, + .csid_csi2_rx_total_crc_err_addr = 0x168, + .csid_csi2_rx_de_scramble_type3_cfg0_addr = 0x170, + .csid_csi2_rx_de_scramble_type3_cfg1_addr = 0x174, + .csid_csi2_rx_de_scramble_type2_cfg0_addr = 0x178, + .csid_csi2_rx_de_scramble_type2_cfg1_addr = 0x17c, + .csid_csi2_rx_de_scramble_type1_cfg0_addr = 0x180, + .csid_csi2_rx_de_scramble_type1_cfg1_addr = 0x184, + .csid_csi2_rx_de_scramble_type0_cfg0_addr = 0x188, + .csid_csi2_rx_de_scramble_type0_cfg1_addr = 0x18c, + + .csi2_rst_srb_all = 0x3FFF, + .csi2_rst_done_shift_val = 27, + .csi2_irq_mask_all = 0xFFFFFFF, + .csi2_misr_enable_shift_val = 6, + .csi2_vc_mode_shift_val = 2, + .csi2_capture_long_pkt_en_shift = 0, + .csi2_capture_short_pkt_en_shift = 1, + .csi2_capture_cphy_pkt_en_shift = 2, + .csi2_capture_long_pkt_dt_shift = 4, + .csi2_capture_long_pkt_vc_shift = 10, + .csi2_capture_short_pkt_vc_shift = 15, + .csi2_capture_cphy_pkt_dt_shift = 20, + .csi2_capture_cphy_pkt_vc_shift = 26, + .csi2_rx_phy_num_mask = 0x7, +}; + +static struct cam_ife_csid_csi2_tpg_reg_offset + cam_ife_csid_175_200_tpg_reg_offset = { + /*CSID TPG control */ + .csid_tpg_ctrl_addr = 0x600, + .csid_tpg_vc_cfg0_addr = 0x604, + .csid_tpg_vc_cfg1_addr = 0x608, + .csid_tpg_lfsr_seed_addr = 0x60c, + .csid_tpg_dt_n_cfg_0_addr = 0x610, + .csid_tpg_dt_n_cfg_1_addr = 0x614, + .csid_tpg_dt_n_cfg_2_addr = 0x618, + .csid_tpg_color_bars_cfg_addr = 0x640, + .csid_tpg_color_box_cfg_addr = 0x644, + .csid_tpg_common_gen_cfg_addr = 0x648, + .csid_tpg_cgen_n_cfg_addr = 0x650, + .csid_tpg_cgen_n_x0_addr = 0x654, + .csid_tpg_cgen_n_x1_addr = 0x658, + .csid_tpg_cgen_n_x2_addr = 0x65c, + .csid_tpg_cgen_n_xy_addr = 0x660, + .csid_tpg_cgen_n_y1_addr = 0x664, + .csid_tpg_cgen_n_y2_addr = 0x668, + + /* configurations */ + .tpg_dtn_cfg_offset = 0xc, + .tpg_cgen_cfg_offset = 0x20, + .tpg_cpas_ife_reg_offset = 0x28, +}; + +static struct cam_ife_csid_common_reg_offset + cam_ife_csid_175_200_cmn_reg_offset = { + .csid_hw_version_addr = 0x0, + .csid_cfg0_addr = 0x4, + .csid_ctrl_addr = 0x8, + .csid_reset_addr = 0xc, + .csid_rst_strobes_addr = 0x10, + + .csid_test_bus_ctrl_addr = 0x14, + .csid_top_irq_status_addr = 0x70, + .csid_top_irq_mask_addr = 0x74, + .csid_top_irq_clear_addr = 0x78, + .csid_top_irq_set_addr = 0x7c, + .csid_irq_cmd_addr = 0x80, + + /*configurations */ + .major_version = 1, + .minor_version = 7, + .version_incr = 5, + .num_rdis = 3, + .num_pix = 1, + .num_ppp = 1, + .csid_reg_rst_stb = 1, + .csid_rst_stb = 0x1e, + .csid_rst_stb_sw_all = 0x1f, + .path_rst_stb_all = 0x7f, + .path_rst_done_shift_val = 1, + .path_en_shift_val = 31, + .packing_fmt_shift_val = 30, + .dt_id_shift_val = 27, + .vc_shift_val = 22, + .dt_shift_val = 16, + .fmt_shift_val = 12, + .plain_fmt_shit_val = 10, + .crop_v_en_shift_val = 6, + .crop_h_en_shift_val = 5, + .crop_shift = 16, + .ipp_irq_mask_all = 0xFFFF, + .rdi_irq_mask_all = 0xFFFF, + .ppp_irq_mask_all = 0xFFFF, + .measure_en_hbi_vbi_cnt_mask = 0xC, + .format_measure_en_val = 1, +}; + +static struct cam_ife_csid_reg_offset cam_ife_csid_175_200_reg_offset = { + .cmn_reg = &cam_ife_csid_175_200_cmn_reg_offset, + .csi2_reg = &cam_ife_csid_175_200_csi2_reg_offset, + .ipp_reg = &cam_ife_csid_175_200_ipp_reg_offset, + .ppp_reg = &cam_ife_csid_175_200_ppp_reg_offset, + .rdi_reg = { + &cam_ife_csid_175_200_rdi_0_reg_offset, + &cam_ife_csid_175_200_rdi_1_reg_offset, + &cam_ife_csid_175_200_rdi_2_reg_offset, + NULL, + }, + .tpg_reg = &cam_ife_csid_175_200_tpg_reg_offset, +}; + +#endif /*_CAM_IFE_CSID_175_200_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid17x.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid17x.c new file mode 100644 index 0000000000000000000000000000000000000000..d88347caa38864ae20964e55c756c344b5e75621 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid17x.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + + +#include +#include "cam_ife_csid_core.h" +#include "cam_ife_csid170.h" +#include "cam_ife_csid175.h" +#include "cam_ife_csid175_200.h" +#include "cam_ife_csid480.h" +#include "cam_ife_csid_dev.h" + +#define CAM_CSID_DRV_NAME "csid_17x" +#define CAM_CSID_VERSION_V170 0x10070000 +#define CAM_CSID_VERSION_V175 0x10070050 +#define CAM_CSID_VERSION_V480 0x40080000 + +static struct cam_ife_csid_hw_info cam_ife_csid170_hw_info = { + .csid_reg = &cam_ife_csid_170_reg_offset, + .hw_dts_version = CAM_CSID_VERSION_V170, +}; + +static struct cam_ife_csid_hw_info cam_ife_csid175_hw_info = { + .csid_reg = &cam_ife_csid_175_reg_offset, + .hw_dts_version = CAM_CSID_VERSION_V175, +}; + +static struct cam_ife_csid_hw_info cam_ife_csid175_200_hw_info = { + .csid_reg = &cam_ife_csid_175_200_reg_offset, + .hw_dts_version = CAM_CSID_VERSION_V175, +}; + +static struct cam_ife_csid_hw_info cam_ife_csid480_hw_info = { + .csid_reg = &cam_ife_csid_480_reg_offset, + .hw_dts_version = CAM_CSID_VERSION_V480, +}; + +static const struct of_device_id cam_ife_csid17x_dt_match[] = { + { + .compatible = "qcom,csid170", + .data = &cam_ife_csid170_hw_info, + }, + { + .compatible = "qcom,csid175", + .data = &cam_ife_csid175_hw_info, + }, + { + .compatible = "qcom,csid175_200", + .data = &cam_ife_csid175_200_hw_info, + }, + { + .compatible = "qcom,csid480", + .data = &cam_ife_csid480_hw_info, + }, + {} +}; + +MODULE_DEVICE_TABLE(of, cam_ife_csid17x_dt_match); + +static struct platform_driver cam_ife_csid17x_driver = { + .probe = cam_ife_csid_probe, + .remove = cam_ife_csid_remove, + .driver = { + .name = CAM_CSID_DRV_NAME, + .owner = THIS_MODULE, + .of_match_table = cam_ife_csid17x_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_ife_csid17x_init_module(void) +{ + return platform_driver_register(&cam_ife_csid17x_driver); +} + +static void __exit cam_ife_csid17x_exit_module(void) +{ + platform_driver_unregister(&cam_ife_csid17x_driver); +} + +module_init(cam_ife_csid17x_init_module); +module_exit(cam_ife_csid17x_exit_module); +MODULE_DESCRIPTION("CAM IFE_CSID17X driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid480.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid480.h new file mode 100644 index 0000000000000000000000000000000000000000..66c1b32d51b0f51cf47e526198e30c9a7eeea9eb --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid480.h @@ -0,0 +1,384 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_IFE_CSID_480_H_ +#define _CAM_IFE_CSID_480_H_ + +#include "cam_ife_csid_core.h" + +static struct cam_ife_csid_pxl_reg_offset cam_ife_csid_480_ipp_reg_offset = { + .csid_pxl_irq_status_addr = 0x30, + .csid_pxl_irq_mask_addr = 0x34, + .csid_pxl_irq_clear_addr = 0x38, + .csid_pxl_irq_set_addr = 0x3c, + + .csid_pxl_cfg0_addr = 0x200, + .csid_pxl_cfg1_addr = 0x204, + .csid_pxl_ctrl_addr = 0x208, + .csid_pxl_frm_drop_pattern_addr = 0x20c, + .csid_pxl_frm_drop_period_addr = 0x210, + .csid_pxl_irq_subsample_pattern_addr = 0x214, + .csid_pxl_irq_subsample_period_addr = 0x218, + .csid_pxl_hcrop_addr = 0x21c, + .csid_pxl_vcrop_addr = 0x220, + .csid_pxl_pix_drop_pattern_addr = 0x224, + .csid_pxl_pix_drop_period_addr = 0x228, + .csid_pxl_line_drop_pattern_addr = 0x22c, + .csid_pxl_line_drop_period_addr = 0x230, + .csid_pxl_rst_strobes_addr = 0x240, + .csid_pxl_status_addr = 0x254, + .csid_pxl_misr_val_addr = 0x258, + .csid_pxl_format_measure_cfg0_addr = 0x270, + .csid_pxl_format_measure_cfg1_addr = 0x274, + .csid_pxl_format_measure0_addr = 0x278, + .csid_pxl_format_measure1_addr = 0x27c, + .csid_pxl_format_measure2_addr = 0x280, + .csid_pxl_timestamp_curr0_sof_addr = 0x290, + .csid_pxl_timestamp_curr1_sof_addr = 0x294, + .csid_pxl_timestamp_perv0_sof_addr = 0x298, + .csid_pxl_timestamp_perv1_sof_addr = 0x29c, + .csid_pxl_timestamp_curr0_eof_addr = 0x2a0, + .csid_pxl_timestamp_curr1_eof_addr = 0x2a4, + .csid_pxl_timestamp_perv0_eof_addr = 0x2a8, + .csid_pxl_timestamp_perv1_eof_addr = 0x2ac, + .csid_pxl_err_recovery_cfg0_addr = 0x2d0, + .csid_pxl_err_recovery_cfg1_addr = 0x2d4, + .csid_pxl_err_recovery_cfg2_addr = 0x2d8, + .csid_pxl_multi_vcdt_cfg0_addr = 0x2dc, + /* configurations */ + .pix_store_en_shift_val = 7, + .early_eof_en_shift_val = 29, + .horizontal_bin_en_shift_val = 2, + .quad_cfa_bin_en_shift_val = 30, + .ccif_violation_en = 1, + .overflow_ctrl_en = 1, +}; + +static struct cam_ife_csid_pxl_reg_offset cam_ife_csid_480_ppp_reg_offset = { + .csid_pxl_irq_status_addr = 0xa0, + .csid_pxl_irq_mask_addr = 0xa4, + .csid_pxl_irq_clear_addr = 0xa8, + .csid_pxl_irq_set_addr = 0xac, + + .csid_pxl_cfg0_addr = 0x700, + .csid_pxl_cfg1_addr = 0x704, + .csid_pxl_ctrl_addr = 0x708, + .csid_pxl_frm_drop_pattern_addr = 0x70c, + .csid_pxl_frm_drop_period_addr = 0x710, + .csid_pxl_irq_subsample_pattern_addr = 0x714, + .csid_pxl_irq_subsample_period_addr = 0x718, + .csid_pxl_hcrop_addr = 0x71c, + .csid_pxl_vcrop_addr = 0x720, + .csid_pxl_pix_drop_pattern_addr = 0x724, + .csid_pxl_pix_drop_period_addr = 0x728, + .csid_pxl_line_drop_pattern_addr = 0x72c, + .csid_pxl_line_drop_period_addr = 0x730, + .csid_pxl_rst_strobes_addr = 0x740, + .csid_pxl_status_addr = 0x754, + .csid_pxl_misr_val_addr = 0x758, + .csid_pxl_format_measure_cfg0_addr = 0x770, + .csid_pxl_format_measure_cfg1_addr = 0x774, + .csid_pxl_format_measure0_addr = 0x778, + .csid_pxl_format_measure1_addr = 0x77c, + .csid_pxl_format_measure2_addr = 0x780, + .csid_pxl_timestamp_curr0_sof_addr = 0x790, + .csid_pxl_timestamp_curr1_sof_addr = 0x794, + .csid_pxl_timestamp_perv0_sof_addr = 0x798, + .csid_pxl_timestamp_perv1_sof_addr = 0x79c, + .csid_pxl_timestamp_curr0_eof_addr = 0x7a0, + .csid_pxl_timestamp_curr1_eof_addr = 0x7a4, + .csid_pxl_timestamp_perv0_eof_addr = 0x7a8, + .csid_pxl_timestamp_perv1_eof_addr = 0x7ac, + .csid_pxl_err_recovery_cfg0_addr = 0x7d0, + .csid_pxl_err_recovery_cfg1_addr = 0x7d4, + .csid_pxl_err_recovery_cfg2_addr = 0x7d8, + .csid_pxl_multi_vcdt_cfg0_addr = 0x7dc, + /* configurations */ + .pix_store_en_shift_val = 7, + .early_eof_en_shift_val = 29, + .ccif_violation_en = 1, + .overflow_ctrl_en = 1, +}; + + +static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_480_rdi_0_reg_offset = { + .csid_rdi_irq_status_addr = 0x40, + .csid_rdi_irq_mask_addr = 0x44, + .csid_rdi_irq_clear_addr = 0x48, + .csid_rdi_irq_set_addr = 0x4c, + .csid_rdi_cfg0_addr = 0x300, + .csid_rdi_cfg1_addr = 0x304, + .csid_rdi_ctrl_addr = 0x308, + .csid_rdi_frm_drop_pattern_addr = 0x30c, + .csid_rdi_frm_drop_period_addr = 0x310, + .csid_rdi_irq_subsample_pattern_addr = 0x314, + .csid_rdi_irq_subsample_period_addr = 0x318, + .csid_rdi_rpp_hcrop_addr = 0x31c, + .csid_rdi_rpp_vcrop_addr = 0x320, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x324, + .csid_rdi_rpp_pix_drop_period_addr = 0x328, + .csid_rdi_rpp_line_drop_pattern_addr = 0x32c, + .csid_rdi_rpp_line_drop_period_addr = 0x330, + .csid_rdi_rst_strobes_addr = 0x340, + .csid_rdi_status_addr = 0x350, + .csid_rdi_misr_val0_addr = 0x354, + .csid_rdi_misr_val1_addr = 0x358, + .csid_rdi_misr_val2_addr = 0x35c, + .csid_rdi_misr_val3_addr = 0x360, + .csid_rdi_format_measure_cfg0_addr = 0x370, + .csid_rdi_format_measure_cfg1_addr = 0x374, + .csid_rdi_format_measure0_addr = 0x378, + .csid_rdi_format_measure1_addr = 0x37c, + .csid_rdi_format_measure2_addr = 0x380, + .csid_rdi_timestamp_curr0_sof_addr = 0x390, + .csid_rdi_timestamp_curr1_sof_addr = 0x394, + .csid_rdi_timestamp_prev0_sof_addr = 0x398, + .csid_rdi_timestamp_prev1_sof_addr = 0x39c, + .csid_rdi_timestamp_curr0_eof_addr = 0x3a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x3a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x3a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x3ac, + .csid_rdi_err_recovery_cfg0_addr = 0x3b0, + .csid_rdi_err_recovery_cfg1_addr = 0x3b4, + .csid_rdi_err_recovery_cfg2_addr = 0x3b8, + .csid_rdi_multi_vcdt_cfg0_addr = 0x3bc, + .csid_rdi_byte_cntr_ping_addr = 0x3e0, + .csid_rdi_byte_cntr_pong_addr = 0x3e4, + /* configurations */ + .ccif_violation_en = 1, + .overflow_ctrl_en = 1, +}; + +static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_480_rdi_1_reg_offset = { + .csid_rdi_irq_status_addr = 0x50, + .csid_rdi_irq_mask_addr = 0x54, + .csid_rdi_irq_clear_addr = 0x58, + .csid_rdi_irq_set_addr = 0x5c, + .csid_rdi_cfg0_addr = 0x400, + .csid_rdi_cfg1_addr = 0x404, + .csid_rdi_ctrl_addr = 0x408, + .csid_rdi_frm_drop_pattern_addr = 0x40c, + .csid_rdi_frm_drop_period_addr = 0x410, + .csid_rdi_irq_subsample_pattern_addr = 0x414, + .csid_rdi_irq_subsample_period_addr = 0x418, + .csid_rdi_rpp_hcrop_addr = 0x41c, + .csid_rdi_rpp_vcrop_addr = 0x420, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x424, + .csid_rdi_rpp_pix_drop_period_addr = 0x428, + .csid_rdi_rpp_line_drop_pattern_addr = 0x42c, + .csid_rdi_rpp_line_drop_period_addr = 0x430, + .csid_rdi_rst_strobes_addr = 0x440, + .csid_rdi_status_addr = 0x450, + .csid_rdi_misr_val0_addr = 0x454, + .csid_rdi_misr_val1_addr = 0x458, + .csid_rdi_misr_val2_addr = 0x45c, + .csid_rdi_misr_val3_addr = 0x460, + .csid_rdi_format_measure_cfg0_addr = 0x470, + .csid_rdi_format_measure_cfg1_addr = 0x474, + .csid_rdi_format_measure0_addr = 0x478, + .csid_rdi_format_measure1_addr = 0x47c, + .csid_rdi_format_measure2_addr = 0x480, + .csid_rdi_timestamp_curr0_sof_addr = 0x490, + .csid_rdi_timestamp_curr1_sof_addr = 0x494, + .csid_rdi_timestamp_prev0_sof_addr = 0x498, + .csid_rdi_timestamp_prev1_sof_addr = 0x49c, + .csid_rdi_timestamp_curr0_eof_addr = 0x4a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x4a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x4a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x4ac, + .csid_rdi_err_recovery_cfg0_addr = 0x4b0, + .csid_rdi_err_recovery_cfg1_addr = 0x4b4, + .csid_rdi_err_recovery_cfg2_addr = 0x4b8, + .csid_rdi_multi_vcdt_cfg0_addr = 0x4bc, + .csid_rdi_byte_cntr_ping_addr = 0x4e0, + .csid_rdi_byte_cntr_pong_addr = 0x4e4, + /* configurations */ + .ccif_violation_en = 1, + .overflow_ctrl_en = 1, +}; + +static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_480_rdi_2_reg_offset = { + .csid_rdi_irq_status_addr = 0x60, + .csid_rdi_irq_mask_addr = 0x64, + .csid_rdi_irq_clear_addr = 0x68, + .csid_rdi_irq_set_addr = 0x6c, + .csid_rdi_cfg0_addr = 0x500, + .csid_rdi_cfg1_addr = 0x504, + .csid_rdi_ctrl_addr = 0x508, + .csid_rdi_frm_drop_pattern_addr = 0x50c, + .csid_rdi_frm_drop_period_addr = 0x510, + .csid_rdi_irq_subsample_pattern_addr = 0x514, + .csid_rdi_irq_subsample_period_addr = 0x518, + .csid_rdi_rpp_hcrop_addr = 0x51c, + .csid_rdi_rpp_vcrop_addr = 0x520, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x524, + .csid_rdi_rpp_pix_drop_period_addr = 0x528, + .csid_rdi_rpp_line_drop_pattern_addr = 0x52c, + .csid_rdi_rpp_line_drop_period_addr = 0x530, + .csid_rdi_yuv_chroma_conversion_addr = 0x534, + .csid_rdi_rst_strobes_addr = 0x540, + .csid_rdi_status_addr = 0x550, + .csid_rdi_misr_val0_addr = 0x554, + .csid_rdi_misr_val1_addr = 0x558, + .csid_rdi_misr_val2_addr = 0x55c, + .csid_rdi_misr_val3_addr = 0x560, + .csid_rdi_format_measure_cfg0_addr = 0x570, + .csid_rdi_format_measure_cfg1_addr = 0x574, + .csid_rdi_format_measure0_addr = 0x578, + .csid_rdi_format_measure1_addr = 0x57c, + .csid_rdi_format_measure2_addr = 0x580, + .csid_rdi_timestamp_curr0_sof_addr = 0x590, + .csid_rdi_timestamp_curr1_sof_addr = 0x594, + .csid_rdi_timestamp_prev0_sof_addr = 0x598, + .csid_rdi_timestamp_prev1_sof_addr = 0x59c, + .csid_rdi_timestamp_curr0_eof_addr = 0x5a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x5a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x5a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x5ac, + .csid_rdi_err_recovery_cfg0_addr = 0x5b0, + .csid_rdi_err_recovery_cfg1_addr = 0x5b4, + .csid_rdi_err_recovery_cfg2_addr = 0x5b8, + .csid_rdi_multi_vcdt_cfg0_addr = 0x5bc, + .csid_rdi_byte_cntr_ping_addr = 0x5e0, + .csid_rdi_byte_cntr_pong_addr = 0x5e4, + /* configurations */ + .ccif_violation_en = 1, + .overflow_ctrl_en = 1, +}; + +static struct cam_ife_csid_csi2_rx_reg_offset + cam_ife_csid_480_csi2_reg_offset = { + .csid_csi2_rx_irq_status_addr = 0x20, + .csid_csi2_rx_irq_mask_addr = 0x24, + .csid_csi2_rx_irq_clear_addr = 0x28, + .csid_csi2_rx_irq_set_addr = 0x2c, + + /*CSI2 rx control */ + .csid_csi2_rx_cfg0_addr = 0x100, + .csid_csi2_rx_cfg1_addr = 0x104, + .csid_csi2_rx_capture_ctrl_addr = 0x108, + .csid_csi2_rx_rst_strobes_addr = 0x110, + .csid_csi2_rx_de_scramble_cfg0_addr = 0x114, + .csid_csi2_rx_de_scramble_cfg1_addr = 0x118, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, + .csid_csi2_rx_captured_short_pkt_0_addr = 0x128, + .csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, + .csid_csi2_rx_captured_long_pkt_0_addr = 0x130, + .csid_csi2_rx_captured_long_pkt_1_addr = 0x134, + .csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, + .csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, + .csid_csi2_rx_lane0_misr_addr = 0x150, + .csid_csi2_rx_lane1_misr_addr = 0x154, + .csid_csi2_rx_lane2_misr_addr = 0x158, + .csid_csi2_rx_lane3_misr_addr = 0x15c, + .csid_csi2_rx_total_pkts_rcvd_addr = 0x160, + .csid_csi2_rx_stats_ecc_addr = 0x164, + .csid_csi2_rx_total_crc_err_addr = 0x168, + + .csi2_rst_srb_all = 0x3FFF, + .csi2_rst_done_shift_val = 27, + .csi2_irq_mask_all = 0xFFFFFFF, + .csi2_misr_enable_shift_val = 6, + .csi2_vc_mode_shift_val = 2, + .csi2_capture_long_pkt_en_shift = 0, + .csi2_capture_short_pkt_en_shift = 1, + .csi2_capture_cphy_pkt_en_shift = 2, + .csi2_capture_long_pkt_dt_shift = 4, + .csi2_capture_long_pkt_vc_shift = 10, + .csi2_capture_short_pkt_vc_shift = 15, + .csi2_capture_cphy_pkt_dt_shift = 20, + .csi2_capture_cphy_pkt_vc_shift = 26, + .csi2_rx_phy_num_mask = 0x7, +}; + +static struct cam_ife_csid_csi2_tpg_reg_offset + cam_ife_csid_480_tpg_reg_offset = { + /*CSID TPG control */ + .csid_tpg_ctrl_addr = 0x600, + .csid_tpg_vc_cfg0_addr = 0x604, + .csid_tpg_vc_cfg1_addr = 0x608, + .csid_tpg_lfsr_seed_addr = 0x60c, + .csid_tpg_dt_n_cfg_0_addr = 0x610, + .csid_tpg_dt_n_cfg_1_addr = 0x614, + .csid_tpg_dt_n_cfg_2_addr = 0x618, + .csid_tpg_color_bars_cfg_addr = 0x640, + .csid_tpg_color_box_cfg_addr = 0x644, + .csid_tpg_common_gen_cfg_addr = 0x648, + .csid_tpg_cgen_n_cfg_addr = 0x650, + .csid_tpg_cgen_n_x0_addr = 0x654, + .csid_tpg_cgen_n_x1_addr = 0x658, + .csid_tpg_cgen_n_x2_addr = 0x65c, + .csid_tpg_cgen_n_xy_addr = 0x660, + .csid_tpg_cgen_n_y1_addr = 0x664, + .csid_tpg_cgen_n_y2_addr = 0x668, + + /* configurations */ + .tpg_dtn_cfg_offset = 0xc, + .tpg_cgen_cfg_offset = 0x20, + .tpg_cpas_ife_reg_offset = 0x28, +}; + +static struct cam_ife_csid_common_reg_offset + cam_ife_csid_480_cmn_reg_offset = { + .csid_hw_version_addr = 0x0, + .csid_cfg0_addr = 0x4, + .csid_ctrl_addr = 0x8, + .csid_reset_addr = 0xc, + .csid_rst_strobes_addr = 0x10, + + .csid_test_bus_ctrl_addr = 0x14, + .csid_top_irq_status_addr = 0x70, + .csid_top_irq_mask_addr = 0x74, + .csid_top_irq_clear_addr = 0x78, + .csid_top_irq_set_addr = 0x7c, + .csid_irq_cmd_addr = 0x80, + + /*configurations */ + .major_version = 1, + .minor_version = 7, + .version_incr = 0, + .num_rdis = 3, + .num_pix = 1, + .num_ppp = 1, + .csid_reg_rst_stb = 1, + .csid_rst_stb = 0x1e, + .csid_rst_stb_sw_all = 0x1f, + .path_rst_stb_all = 0x7f, + .path_rst_done_shift_val = 1, + .path_en_shift_val = 31, + .packing_fmt_shift_val = 30, + .dt_id_shift_val = 27, + .vc_shift_val = 22, + .dt_shift_val = 16, + .fmt_shift_val = 12, + .plain_fmt_shit_val = 10, + .crop_v_en_shift_val = 6, + .crop_h_en_shift_val = 5, + .drop_v_en_shift_val = 4, + .drop_h_en_shift_val = 3, + .crop_shift = 16, + .ipp_irq_mask_all = 0x7FFF, + .rdi_irq_mask_all = 0x7FFF, + .ppp_irq_mask_all = 0xFFFF, + .measure_en_hbi_vbi_cnt_mask = 0xC, + .format_measure_en_val = 1, +}; + +static struct cam_ife_csid_reg_offset cam_ife_csid_480_reg_offset = { + .cmn_reg = &cam_ife_csid_480_cmn_reg_offset, + .csi2_reg = &cam_ife_csid_480_csi2_reg_offset, + .ipp_reg = &cam_ife_csid_480_ipp_reg_offset, + .ppp_reg = &cam_ife_csid_480_ppp_reg_offset, + .rdi_reg = { + &cam_ife_csid_480_rdi_0_reg_offset, + &cam_ife_csid_480_rdi_1_reg_offset, + &cam_ife_csid_480_rdi_2_reg_offset, + NULL, + }, + .tpg_reg = &cam_ife_csid_480_tpg_reg_offset, +}; + +#endif /*_CAM_IFE_CSID_480_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c new file mode 100644 index 0000000000000000000000000000000000000000..0da6d5117e27b75c500bf0daa3719e3505083f57 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -0,0 +1,4837 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "cam_isp_hw_mgr_intf.h" +#include "cam_ife_csid_core.h" +#include "cam_isp_hw.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" +#include "cam_subdev.h" +#include "cam_tasklet_util.h" + +/* Timeout value in msec */ +#define IFE_CSID_TIMEOUT 1000 + +/* TPG VC/DT values */ +#define CAM_IFE_CSID_TPG_VC_VAL 0xA +#define CAM_IFE_CSID_TPG_DT_VAL 0x2B + +/* Timeout values in usec */ +#define CAM_IFE_CSID_TIMEOUT_SLEEP_US 1000 +#define CAM_IFE_CSID_TIMEOUT_ALL_US 100000 + +/* + * Constant Factors needed to change QTimer ticks to nanoseconds + * QTimer Freq = 19.2 MHz + * Time(us) = ticks/19.2 + * Time(ns) = ticks/19.2 * 1000 + */ +#define CAM_IFE_CSID_QTIMER_MUL_FACTOR 10000 +#define CAM_IFE_CSID_QTIMER_DIV_FACTOR 192 + +/* Max number of sof irq's triggered in case of SOF freeze */ +#define CAM_CSID_IRQ_SOF_DEBUG_CNT_MAX 12 + +/* Max CSI Rx irq error count threshold value */ +#define CAM_IFE_CSID_MAX_IRQ_ERROR_COUNT 100 + +static int cam_ife_csid_reset_regs( + struct cam_ife_csid_hw *csid_hw, bool reset_hw); +static int cam_ife_csid_is_ipp_ppp_format_supported( + uint32_t in_format) +{ + int rc = -EINVAL; + + switch (in_format) { + case CAM_FORMAT_MIPI_RAW_6: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_MIPI_RAW_20: + case CAM_FORMAT_DPCM_10_6_10: + case CAM_FORMAT_DPCM_10_8_10: + case CAM_FORMAT_DPCM_12_6_12: + case CAM_FORMAT_DPCM_12_8_12: + case CAM_FORMAT_DPCM_14_8_14: + case CAM_FORMAT_DPCM_14_10_14: + case CAM_FORMAT_DPCM_12_10_12: + rc = 0; + break; + default: + break; + } + return rc; +} + +static int cam_ife_csid_get_format_rdi( + uint32_t in_format, uint32_t out_format, uint32_t *decode_fmt, + uint32_t *plain_fmt, uint32_t *packing_fmt, bool rpp) +{ + int rc = 0; + + switch (in_format) { + case CAM_FORMAT_MIPI_RAW_6: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_6: + *decode_fmt = 0xf; + if (rpp) { + *decode_fmt = 0x0; + *packing_fmt = 0x1; + } + break; + case CAM_FORMAT_PLAIN8: + *decode_fmt = 0x0; + *plain_fmt = 0x0; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_8: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_PLAIN128: + *decode_fmt = 0xf; + if (rpp) { + *decode_fmt = 0x1; + *packing_fmt = 0x1; + } + break; + case CAM_FORMAT_PLAIN8: + *decode_fmt = 0x1; + *plain_fmt = 0x0; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_10: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_PLAIN128: + *decode_fmt = 0xf; + if (rpp) { + *decode_fmt = 0x2; + *packing_fmt = 0x1; + } + break; + case CAM_FORMAT_PLAIN16_10: + *decode_fmt = 0x2; + *plain_fmt = 0x1; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_12: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_12: + *decode_fmt = 0xf; + if (rpp) { + *decode_fmt = 0x3; + *packing_fmt = 0x1; + } + break; + case CAM_FORMAT_PLAIN16_12: + *decode_fmt = 0x3; + *plain_fmt = 0x1; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_14: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_14: + *decode_fmt = 0xf; + if (rpp) { + *decode_fmt = 0x4; + *packing_fmt = 0x1; + } + break; + case CAM_FORMAT_PLAIN16_14: + *decode_fmt = 0x4; + *plain_fmt = 0x1; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_16: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_16: + *decode_fmt = 0xf; + if (rpp) { + *decode_fmt = 0x5; + *packing_fmt = 0x1; + } + break; + case CAM_FORMAT_PLAIN16_16: + *decode_fmt = 0x5; + *plain_fmt = 0x1; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_20: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_20: + *decode_fmt = 0xf; + if (rpp) { + *decode_fmt = 0x6; + *packing_fmt = 0x1; + } + break; + case CAM_FORMAT_PLAIN32_20: + *decode_fmt = 0x6; + *plain_fmt = 0x2; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_DPCM_10_6_10: + *decode_fmt = 0x7; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_DPCM_10_8_10: + *decode_fmt = 0x8; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_DPCM_12_6_12: + *decode_fmt = 0x9; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_DPCM_12_8_12: + *decode_fmt = 0xA; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_DPCM_14_8_14: + *decode_fmt = 0xB; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_DPCM_14_10_14: + *decode_fmt = 0xC; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_DPCM_12_10_12: + *decode_fmt = 0xD; + *plain_fmt = 0x1; + break; + default: + rc = -EINVAL; + break; + } + + if (rc) + CAM_ERR(CAM_ISP, "Unsupported format pair in %d out %d", + in_format, out_format); + + return rc; +} + +static int cam_ife_csid_get_format_ipp_ppp( + uint32_t in_format, + uint32_t *decode_fmt, uint32_t *plain_fmt) +{ + int rc = 0; + + CAM_DBG(CAM_ISP, "input format:%d", + in_format); + + switch (in_format) { + case CAM_FORMAT_MIPI_RAW_6: + *decode_fmt = 0; + *plain_fmt = 0; + break; + case CAM_FORMAT_MIPI_RAW_8: + *decode_fmt = 0x1; + *plain_fmt = 0; + break; + case CAM_FORMAT_MIPI_RAW_10: + *decode_fmt = 0x2; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_MIPI_RAW_12: + *decode_fmt = 0x3; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_MIPI_RAW_14: + *decode_fmt = 0x4; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_MIPI_RAW_16: + *decode_fmt = 0x5; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_MIPI_RAW_20: + *decode_fmt = 0x6; + *plain_fmt = 0x2; + break; + case CAM_FORMAT_DPCM_10_6_10: + *decode_fmt = 0x7; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_DPCM_10_8_10: + *decode_fmt = 0x8; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_DPCM_12_6_12: + *decode_fmt = 0x9; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_DPCM_12_8_12: + *decode_fmt = 0xA; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_DPCM_14_8_14: + *decode_fmt = 0xB; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_DPCM_14_10_14: + *decode_fmt = 0xC; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_DPCM_12_10_12: + *decode_fmt = 0xD; + *plain_fmt = 0x1; + break; + default: + CAM_ERR(CAM_ISP, "Unsupported format %d", + in_format); + rc = -EINVAL; + } + + CAM_DBG(CAM_ISP, "decode_fmt:%d plain_fmt:%d", + *decode_fmt, *plain_fmt); + + return rc; +} + +static int cam_ife_match_vc_dt_pair(int32_t *vc, uint32_t *dt, + uint32_t num_valid_vc_dt, struct cam_ife_csid_cid_data *cid_data) +{ + uint32_t camera_hw_version; + int rc = 0; + + rc = cam_cpas_get_cpas_hw_version(&camera_hw_version); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to get HW version rc:%d", rc); + return -EINVAL; + } + + if (camera_hw_version != CAM_CPAS_TITAN_480_V100) + num_valid_vc_dt = 1; + + switch (num_valid_vc_dt) { + case 2: + if (vc[1] != cid_data->vc1 || + dt[1] != cid_data->dt1) + return -EINVAL; + case 1: + if (vc[0] != cid_data->vc || + dt[0] != cid_data->dt) + return -EINVAL; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int cam_ife_csid_cid_get(struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node **res, int32_t *vc, uint32_t *dt, + uint32_t num_valid_vc_dt) +{ + struct cam_ife_csid_cid_data *cid_data; + uint32_t i = 0; + + *res = NULL; + + /* Return already reserved CID if the VC/DT matches */ + for (i = 0; i < CAM_IFE_CSID_CID_MAX; i++) { + if (csid_hw->cid_res[i].res_state >= + CAM_ISP_RESOURCE_STATE_RESERVED) { + cid_data = (struct cam_ife_csid_cid_data *) + csid_hw->cid_res[i].res_priv; + if (!cam_ife_match_vc_dt_pair(vc, dt, + num_valid_vc_dt, cid_data)) { + cid_data->cnt++; + *res = &csid_hw->cid_res[i]; + CAM_DBG(CAM_ISP, "CSID:%d CID %d", + csid_hw->hw_intf->hw_idx, + csid_hw->cid_res[i].res_id); + return 0; + } + } + } + + for (i = 0; i < CAM_IFE_CSID_CID_MAX; i++) { + if (csid_hw->cid_res[i].res_state == + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + cid_data = (struct cam_ife_csid_cid_data *) + csid_hw->cid_res[i].res_priv; + cid_data->vc = vc[0]; + cid_data->dt = dt[0]; + if (num_valid_vc_dt > 1) { + cid_data->vc1 = vc[1]; + cid_data->dt1 = dt[1]; + cid_data->is_valid_vc1_dt1 = 1; + } + cid_data->cnt = 1; + csid_hw->cid_res[i].res_state = + CAM_ISP_RESOURCE_STATE_RESERVED; + *res = &csid_hw->cid_res[i]; + CAM_DBG(CAM_ISP, "CSID:%d CID %d allocated", + csid_hw->hw_intf->hw_idx, + csid_hw->cid_res[i].res_id); + return 0; + } + } + + CAM_ERR(CAM_ISP, "CSID:%d Free cid is not available", + csid_hw->hw_intf->hw_idx); + + return -EINVAL; +} + + +static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw) +{ + struct cam_hw_soc_info *soc_info; + const struct cam_ife_csid_reg_offset *csid_reg; + int rc = 0; + uint32_t val = 0, i; + unsigned long flags; + + soc_info = &csid_hw->hw_info->soc_info; + csid_reg = csid_hw->csid_info->csid_reg; + + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid HW State:%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "CSID:%d Csid reset", + csid_hw->hw_intf->hw_idx); + + spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); + + /* Mask all interrupts */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + + if (csid_reg->cmn_reg->num_pix) + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + + if (csid_reg->cmn_reg->num_ppp) + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_mask_addr); + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); + + /* clear all interrupts */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + + cam_io_w_mb(csid_reg->csi2_reg->csi2_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); + + if (csid_reg->cmn_reg->num_pix) + cam_io_w_mb(csid_reg->cmn_reg->ipp_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_clear_addr); + + if (csid_reg->cmn_reg->num_ppp) + cam_io_w_mb(csid_reg->cmn_reg->ppp_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_clear_addr); + + for (i = 0 ; i < csid_reg->cmn_reg->num_rdis; i++) + cam_io_w_mb(csid_reg->cmn_reg->rdi_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr); + + for (i = 0 ; i < csid_reg->cmn_reg->num_udis; i++) + cam_io_w_mb(csid_reg->cmn_reg->udi_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[i]->csid_udi_irq_clear_addr); + + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); + + cam_io_w_mb(0x80, soc_info->reg_map[0].mem_base + + csid_hw->csid_info->csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + + /* enable the IPP and RDI format measure */ + if (csid_reg->cmn_reg->num_pix) + cam_io_w_mb(0x1, soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_cfg0_addr); + + if (csid_reg->cmn_reg->num_ppp) + cam_io_w_mb(0x1, soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_cfg0_addr); + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) + cam_io_w_mb(0x2, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_cfg0_addr); + + /* reset HW regs first, then SW */ + rc = cam_ife_csid_reset_regs(csid_hw, true); + if (rc < 0) + goto end; + rc = cam_ife_csid_reset_regs(csid_hw, false); + if (rc < 0) + goto end; + + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + if (val != 0) + CAM_ERR(CAM_ISP, "CSID:%d IRQ value after reset rc = %d", + csid_hw->hw_intf->hw_idx, val); + csid_hw->error_irq_count = 0; + csid_hw->prev_boot_timestamp = 0; + +end: + return rc; +} + +static int cam_ife_csid_path_reset(struct cam_ife_csid_hw *csid_hw, + struct cam_csid_reset_cfg_args *reset) +{ + int rc = 0; + unsigned long rem_jiffies; + struct cam_hw_soc_info *soc_info; + struct cam_isp_resource_node *res; + const struct cam_ife_csid_reg_offset *csid_reg; + uint32_t reset_strb_addr, reset_strb_val, val, id; + struct completion *complete; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + res = reset->node_res; + + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid hw state :%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + return -EINVAL; + } + + if (res->res_id >= CAM_IFE_PIX_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res id%d", + csid_hw->hw_intf->hw_idx, res->res_id); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ISP, "CSID:%d resource:%d", + csid_hw->hw_intf->hw_idx, res->res_id); + + if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) { + if (!csid_reg->ipp_reg) { + CAM_ERR(CAM_ISP, "CSID:%d IPP not supported :%d", + csid_hw->hw_intf->hw_idx, + res->res_id); + return -EINVAL; + } + + reset_strb_addr = csid_reg->ipp_reg->csid_pxl_rst_strobes_addr; + complete = &csid_hw->csid_ipp_complete; + + /* Enable path reset done interrupt */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + val |= CSID_PATH_INFO_RST_DONE; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_PPP) { + if (!csid_reg->ppp_reg) { + CAM_ERR(CAM_ISP, "CSID:%d PPP not supported :%d", + csid_hw->hw_intf->hw_idx, + res->res_id); + return -EINVAL; + } + + reset_strb_addr = csid_reg->ppp_reg->csid_pxl_rst_strobes_addr; + complete = &csid_hw->csid_ppp_complete; + + /* Enable path reset done interrupt */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_mask_addr); + val |= CSID_PATH_INFO_RST_DONE; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_mask_addr); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_RDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_2 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_3) { + id = res->res_id; + if (!csid_reg->rdi_reg[id]) { + CAM_ERR(CAM_ISP, "CSID:%d RDI res not supported :%d", + csid_hw->hw_intf->hw_idx, + res->res_id); + return -EINVAL; + } + + reset_strb_addr = + csid_reg->rdi_reg[id]->csid_rdi_rst_strobes_addr; + complete = + &csid_hw->csid_rdin_complete[id]; + + /* Enable path reset done interrupt */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); + val |= CSID_PATH_INFO_RST_DONE; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_UDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_2) { + id = res->res_id - CAM_IFE_PIX_PATH_RES_UDI_0; + if (!csid_reg->udi_reg[id]) { + CAM_ERR(CAM_ISP, "CSID:%d UDI res not supported :%d", + csid_hw->hw_intf->hw_idx, + res->res_id); + return -EINVAL; + } + + reset_strb_addr = + csid_reg->udi_reg[id]->csid_udi_rst_strobes_addr; + complete = + &csid_hw->csid_udin_complete[id]; + + /* Enable path reset done interrupt */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_irq_mask_addr); + val |= CSID_PATH_INFO_RST_DONE; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_irq_mask_addr); + } else { + CAM_ERR(CAM_ISP, "Invalid res_id %u", res->res_id); + return -EINVAL; + } + + reinit_completion(complete); + reset_strb_val = csid_reg->cmn_reg->path_rst_stb_all; + + /* Reset the corresponding ife csid path */ + cam_io_w_mb(reset_strb_val, soc_info->reg_map[0].mem_base + + reset_strb_addr); + + rem_jiffies = wait_for_completion_timeout(complete, + msecs_to_jiffies(IFE_CSID_TIMEOUT)); + if (!rem_jiffies) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_ISP, "CSID:%d Res id %d fail rc = %d", + csid_hw->hw_intf->hw_idx, + res->res_id, rc); + } + +end: + return rc; + +} + +int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw, + struct cam_csid_hw_reserve_resource_args *cid_reserv) +{ + int rc = 0, i, id; + struct cam_ife_csid_cid_data *cid_data; + uint32_t camera_hw_version; + uint32_t valid_vc_dt; + + CAM_DBG(CAM_ISP, + "CSID:%d res_sel:0x%x Lane type:%d lane_num:%d dt:%d vc:%d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->res_type, + cid_reserv->in_port->lane_type, + cid_reserv->in_port->lane_num, + cid_reserv->in_port->dt[0], + cid_reserv->in_port->vc[0]); + + if (cid_reserv->in_port->res_type >= CAM_ISP_IFE_IN_RES_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid phy sel %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->res_type); + rc = -EINVAL; + goto end; + } + + if (cid_reserv->in_port->lane_type >= CAM_ISP_LANE_TYPE_MAX && + cid_reserv->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid lane type %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->lane_type); + rc = -EINVAL; + goto end; + } + + if ((cid_reserv->in_port->lane_type == CAM_ISP_LANE_TYPE_DPHY && + cid_reserv->in_port->lane_num > 4) && + cid_reserv->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid lane num %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->lane_num); + rc = -EINVAL; + goto end; + } + if ((cid_reserv->in_port->lane_type == CAM_ISP_LANE_TYPE_CPHY && + cid_reserv->in_port->lane_num > 3) && + cid_reserv->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) { + CAM_ERR(CAM_ISP, " CSID:%d Invalid lane type %d & num %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->lane_type, + cid_reserv->in_port->lane_num); + rc = -EINVAL; + goto end; + } + + valid_vc_dt = cid_reserv->in_port->num_valid_vc_dt; + + /* CSID CSI2 v2.0 supports 31 vc */ + for (i = 0; i < valid_vc_dt; i++) { + if (cid_reserv->in_port->vc[i] > 0x1f || + cid_reserv->in_port->dt[i] > 0x3f) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid vc:%d or dt: %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->vc[i], + cid_reserv->in_port->dt[i]); + rc = -EINVAL; + goto end; + } + } + + if (cid_reserv->in_port->res_type == CAM_ISP_IFE_IN_RES_TPG && ( + (cid_reserv->in_port->format < CAM_FORMAT_MIPI_RAW_8 && + cid_reserv->in_port->format > CAM_FORMAT_MIPI_RAW_16))) { + CAM_ERR(CAM_ISP, " CSID:%d Invalid tpg decode fmt %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->format); + rc = -EINVAL; + goto end; + } + + if (csid_hw->csi2_reserve_cnt == UINT_MAX) { + CAM_ERR(CAM_ISP, + "CSID%d reserve cnt reached max", + csid_hw->hw_intf->hw_idx); + rc = -EINVAL; + goto end; + } + + rc = cam_cpas_get_cpas_hw_version(&camera_hw_version); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to get HW version rc:%d", rc); + goto end; + } + CAM_DBG(CAM_ISP, "HW version: %x", camera_hw_version); + + switch (camera_hw_version) { + case CAM_CPAS_TITAN_NONE: + case CAM_CPAS_TITAN_MAX: + CAM_ERR(CAM_ISP, "Invalid HW version: %x", camera_hw_version); + break; + case CAM_CPAS_TITAN_170_V100: + case CAM_CPAS_TITAN_170_V110: + case CAM_CPAS_TITAN_170_V120: + if (cid_reserv->in_port->res_type == CAM_ISP_IFE_IN_RES_PHY_3 && + csid_hw->hw_intf->hw_idx != 2) { + rc = -EINVAL; + goto end; + } + break; + case CAM_CPAS_TITAN_480_V100: + if (cid_reserv->in_port->cust_node == 1) { + if (cid_reserv->in_port->usage_type == 1) { + CAM_ERR(CAM_ISP, "Dual IFE is not supported"); + rc = -EINVAL; + goto end; + } + if (csid_hw->hw_intf->hw_idx != 0) { + CAM_DBG(CAM_ISP, "CSID%d not eligible", + csid_hw->hw_intf->hw_idx); + rc = -EINVAL; + goto end; + } + } + break; + default: + break; + } + CAM_DBG(CAM_ISP, "Reserve_cnt %u", csid_hw->csi2_reserve_cnt); + + if (csid_hw->csi2_reserve_cnt) { + /* current configure res type should match requested res type */ + if (csid_hw->res_type != cid_reserv->in_port->res_type) { + rc = -EINVAL; + goto end; + } + + if (cid_reserv->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) { + if (csid_hw->csi2_rx_cfg.lane_cfg != + cid_reserv->in_port->lane_cfg || + csid_hw->csi2_rx_cfg.lane_type != + cid_reserv->in_port->lane_type || + csid_hw->csi2_rx_cfg.lane_num != + cid_reserv->in_port->lane_num) { + rc = -EINVAL; + goto end; + } + } else { + if (csid_hw->tpg_cfg.in_format != + cid_reserv->in_port->format || + csid_hw->tpg_cfg.width != + cid_reserv->in_port->left_width || + csid_hw->tpg_cfg.height != + cid_reserv->in_port->height || + csid_hw->tpg_cfg.test_pattern != + cid_reserv->in_port->test_pattern) { + rc = -EINVAL; + goto end; + } + } + } + + switch (cid_reserv->res_id) { + case CAM_IFE_PIX_PATH_RES_IPP: + if (csid_hw->ipp_res.res_state != + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_DBG(CAM_ISP, + "CSID:%d IPP resource not available", + csid_hw->hw_intf->hw_idx); + rc = -EINVAL; + goto end; + } + break; + case CAM_IFE_PIX_PATH_RES_PPP: + if (csid_hw->ppp_res.res_state != + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, + "CSID:%d PPP resource not available state %d", + csid_hw->hw_intf->hw_idx, + csid_hw->ppp_res.res_state); + rc = -EINVAL; + goto end; + } + break; + case CAM_IFE_PIX_PATH_RES_RDI_0: + case CAM_IFE_PIX_PATH_RES_RDI_1: + case CAM_IFE_PIX_PATH_RES_RDI_2: + case CAM_IFE_PIX_PATH_RES_RDI_3: + if (csid_hw->rdi_res[cid_reserv->res_id].res_state != + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, + "CSID:%d RDI:%d resource not available", + csid_hw->hw_intf->hw_idx, + cid_reserv->res_id); + rc = -EINVAL; + goto end; + } + break; + case CAM_IFE_PIX_PATH_RES_UDI_0: + case CAM_IFE_PIX_PATH_RES_UDI_1: + case CAM_IFE_PIX_PATH_RES_UDI_2: + id = cid_reserv->res_id - CAM_IFE_PIX_PATH_RES_UDI_0; + if (csid_hw->udi_res[id].res_state != + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, + "CSID:%d UDI:%d resource not available", + csid_hw->hw_intf->hw_idx, + cid_reserv->res_id); + rc = -EINVAL; + goto end; + } + break; + default: + CAM_ERR(CAM_ISP, "CSID%d: Invalid csid path", + csid_hw->hw_intf->hw_idx); + rc = -EINVAL; + goto end; + } + + rc = cam_ife_csid_cid_get(csid_hw, + &cid_reserv->node_res, + cid_reserv->in_port->vc, + cid_reserv->in_port->dt, + cid_reserv->in_port->num_valid_vc_dt); + if (rc) { + CAM_ERR(CAM_ISP, "CSID:%d CID Reserve failed res_type %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->res_type); + goto end; + } + cid_data = (struct cam_ife_csid_cid_data *) + cid_reserv->node_res->res_priv; + + if (!csid_hw->csi2_reserve_cnt) { + csid_hw->res_type = cid_reserv->in_port->res_type; + + csid_hw->csi2_rx_cfg.lane_cfg = + cid_reserv->in_port->lane_cfg; + csid_hw->csi2_rx_cfg.lane_type = + cid_reserv->in_port->lane_type; + csid_hw->csi2_rx_cfg.lane_num = + cid_reserv->in_port->lane_num; + + if (cid_reserv->in_port->res_type == CAM_ISP_IFE_IN_RES_TPG) { + csid_hw->csi2_rx_cfg.phy_sel = 0; + if (cid_reserv->in_port->format > + CAM_FORMAT_MIPI_RAW_16) { + CAM_ERR(CAM_ISP, " Wrong TPG format"); + rc = -EINVAL; + goto end; + } + csid_hw->tpg_cfg.in_format = + cid_reserv->in_port->format; + csid_hw->tpg_cfg.usage_type = + cid_reserv->in_port->usage_type; + if (cid_reserv->in_port->usage_type) + csid_hw->tpg_cfg.width = + (cid_reserv->in_port->right_stop + 1); + else + csid_hw->tpg_cfg.width = + cid_reserv->in_port->left_width; + + csid_hw->tpg_cfg.height = cid_reserv->in_port->height; + csid_hw->tpg_cfg.test_pattern = + cid_reserv->in_port->test_pattern; + + CAM_DBG(CAM_ISP, "CSID:%d TPG width:%d height:%d", + csid_hw->hw_intf->hw_idx, + csid_hw->tpg_cfg.width, + csid_hw->tpg_cfg.height); + + cid_data->tpg_set = 1; + } else { + csid_hw->csi2_rx_cfg.phy_sel = + (cid_reserv->in_port->res_type & 0xFF) - 1; + } + } + + csid_hw->csi2_reserve_cnt++; + CAM_DBG(CAM_ISP, "CSID:%d CID:%d acquired", + csid_hw->hw_intf->hw_idx, + cid_reserv->node_res->res_id); + +end: + return rc; +} + +int cam_ife_csid_path_reserve(struct cam_ife_csid_hw *csid_hw, + struct cam_csid_hw_reserve_resource_args *reserve) +{ + int rc = 0, i, id; + struct cam_ife_csid_path_cfg *path_data; + struct cam_isp_resource_node *res; + bool is_rdi = false; + + /* CSID CSI2 v2.0 supports 31 vc */ + if (reserve->sync_mode >= CAM_ISP_HW_SYNC_MAX) { + CAM_ERR(CAM_ISP, "CSID: %d Sync Mode: %d", + reserve->sync_mode); + return -EINVAL; + } + + for (i = 0; i < reserve->in_port->num_valid_vc_dt; i++) { + if (reserve->in_port->dt[i] > 0x3f || + reserve->in_port->vc[i] > 0x1f) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid vc:%d dt %d", + csid_hw->hw_intf->hw_idx, + reserve->in_port->vc, reserve->in_port->dt); + rc = -EINVAL; + goto end; + } + } + + switch (reserve->res_id) { + case CAM_IFE_PIX_PATH_RES_IPP: + if (csid_hw->ipp_res.res_state != + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, + "CSID:%d IPP resource not available %d", + csid_hw->hw_intf->hw_idx, + csid_hw->ipp_res.res_state); + rc = -EINVAL; + goto end; + } + + if (cam_ife_csid_is_ipp_ppp_format_supported( + reserve->in_port->format)) { + CAM_ERR(CAM_ISP, + "CSID:%d res id:%d un support format %d", + csid_hw->hw_intf->hw_idx, reserve->res_id, + reserve->in_port->format); + rc = -EINVAL; + goto end; + } + + /* assign the IPP resource */ + res = &csid_hw->ipp_res; + CAM_DBG(CAM_ISP, + "CSID:%d IPP resource:%d acquired successfully", + csid_hw->hw_intf->hw_idx, res->res_id); + + break; + case CAM_IFE_PIX_PATH_RES_PPP: + if (csid_hw->ppp_res.res_state != + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, + "CSID:%d PPP resource not available %d", + csid_hw->hw_intf->hw_idx, + csid_hw->ppp_res.res_state); + rc = -EINVAL; + goto end; + } + + if (cam_ife_csid_is_ipp_ppp_format_supported( + reserve->in_port->format)) { + CAM_ERR(CAM_ISP, + "CSID:%d res id:%d unsupported format %d", + csid_hw->hw_intf->hw_idx, reserve->res_id, + reserve->in_port->format); + rc = -EINVAL; + goto end; + } + + /* assign the PPP resource */ + res = &csid_hw->ppp_res; + CAM_DBG(CAM_ISP, + "CSID:%d PPP resource:%d acquired successfully", + csid_hw->hw_intf->hw_idx, res->res_id); + + break; + case CAM_IFE_PIX_PATH_RES_RDI_0: + case CAM_IFE_PIX_PATH_RES_RDI_1: + case CAM_IFE_PIX_PATH_RES_RDI_2: + case CAM_IFE_PIX_PATH_RES_RDI_3: + if (csid_hw->rdi_res[reserve->res_id].res_state != + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, + "CSID:%d RDI:%d resource not available %d", + csid_hw->hw_intf->hw_idx, + reserve->res_id, + csid_hw->rdi_res[reserve->res_id].res_state); + rc = -EINVAL; + goto end; + } else { + res = &csid_hw->rdi_res[reserve->res_id]; + CAM_DBG(CAM_ISP, + "CSID:%d RDI resource:%d acquire success", + csid_hw->hw_intf->hw_idx, + res->res_id); + is_rdi = true; + } + + break; + case CAM_IFE_PIX_PATH_RES_UDI_0: + case CAM_IFE_PIX_PATH_RES_UDI_1: + case CAM_IFE_PIX_PATH_RES_UDI_2: + id = reserve->res_id - CAM_IFE_PIX_PATH_RES_UDI_0; + if (csid_hw->udi_res[id].res_state != + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, + "CSID:%d UDI:%d resource not available %d", + csid_hw->hw_intf->hw_idx, + reserve->res_id, + csid_hw->udi_res[id].res_state); + rc = -EINVAL; + goto end; + } else { + res = &csid_hw->udi_res[id]; + CAM_DBG(CAM_ISP, + "CSID:%d UDI resource:%d acquire success", + csid_hw->hw_intf->hw_idx, + res->res_id); + } + + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid res id:%d", + csid_hw->hw_intf->hw_idx, reserve->res_id); + rc = -EINVAL; + goto end; + } + + res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + path_data = (struct cam_ife_csid_path_cfg *)res->res_priv; + + path_data->cid = reserve->cid; + path_data->in_format = reserve->in_port->format; + path_data->out_format = reserve->out_port->format; + path_data->sync_mode = reserve->sync_mode; + path_data->height = reserve->in_port->height; + path_data->start_line = reserve->in_port->line_start; + path_data->end_line = reserve->in_port->line_stop; + path_data->crop_enable = reserve->crop_enable; + path_data->drop_enable = reserve->drop_enable; + path_data->horizontal_bin = reserve->in_port->horizontal_bin; + path_data->qcfa_bin = reserve->in_port->qcfa_bin; + path_data->num_bytes_out = reserve->in_port->num_bytes_out; + + CAM_DBG(CAM_ISP, + "Res id: %d height:%d line_start %d line_stop %d crop_en %d", + reserve->res_id, reserve->in_port->height, + reserve->in_port->line_start, reserve->in_port->line_stop, + path_data->crop_enable); + + if (reserve->in_port->res_type == CAM_ISP_IFE_IN_RES_TPG) { + path_data->dt = CAM_IFE_CSID_TPG_DT_VAL; + path_data->vc = CAM_IFE_CSID_TPG_VC_VAL; + } else { + path_data->dt = reserve->in_port->dt[0]; + path_data->vc = reserve->in_port->vc[0]; + if (reserve->in_port->num_valid_vc_dt) { + path_data->dt1 = reserve->in_port->dt[1]; + path_data->vc1 = reserve->in_port->vc[1]; + path_data->is_valid_vc1_dt1 = 1; + } + } + + if (reserve->sync_mode == CAM_ISP_HW_SYNC_MASTER) { + path_data->start_pixel = reserve->in_port->left_start; + path_data->end_pixel = reserve->in_port->left_stop; + path_data->width = reserve->in_port->left_width; + + if (is_rdi) { + path_data->end_pixel = reserve->in_port->right_stop; + path_data->width = path_data->end_pixel - + path_data->start_pixel + 1; + } + + CAM_DBG(CAM_ISP, + "CSID:%d res:%d master:startpixel 0x%x endpixel:0x%x", + csid_hw->hw_intf->hw_idx, reserve->res_id, + path_data->start_pixel, path_data->end_pixel); + CAM_DBG(CAM_ISP, + "CSID:%d res:%d master:line start:0x%x line end:0x%x", + csid_hw->hw_intf->hw_idx, reserve->res_id, + path_data->start_line, path_data->end_line); + } else if (reserve->sync_mode == CAM_ISP_HW_SYNC_SLAVE) { + path_data->master_idx = reserve->master_idx; + CAM_DBG(CAM_ISP, "CSID:%d master_idx=%d", + csid_hw->hw_intf->hw_idx, path_data->master_idx); + path_data->start_pixel = reserve->in_port->right_start; + path_data->end_pixel = reserve->in_port->right_stop; + path_data->width = reserve->in_port->right_width; + CAM_DBG(CAM_ISP, + "CSID:%d res:%d slave:start:0x%x end:0x%x width 0x%x", + csid_hw->hw_intf->hw_idx, reserve->res_id, + path_data->start_pixel, path_data->end_pixel, + path_data->width); + CAM_DBG(CAM_ISP, + "CSID:%d res:%d slave:line start:0x%x line end:0x%x", + csid_hw->hw_intf->hw_idx, reserve->res_id, + path_data->start_line, path_data->end_line); + } else { + path_data->width = reserve->in_port->left_width; + path_data->start_pixel = reserve->in_port->left_start; + path_data->end_pixel = reserve->in_port->left_stop; + CAM_DBG(CAM_ISP, + "CSID:%d res:%d left width %d start: %d stop:%d", + csid_hw->hw_intf->hw_idx, reserve->res_id, + reserve->in_port->left_width, + reserve->in_port->left_start, + reserve->in_port->left_stop); + } + + CAM_DBG(CAM_ISP, "CSID:%d res:%d width %d height %d", + csid_hw->hw_intf->hw_idx, reserve->res_id, + path_data->width, path_data->height); + reserve->node_res = res; + csid_hw->event_cb = reserve->event_cb; + csid_hw->priv = reserve->priv; + +end: + return rc; +} + +static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw) +{ + int rc = 0; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t i, val; + int clk_lvl; + unsigned long flags; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + /* overflow check before increment */ + if (csid_hw->hw_info->open_count == UINT_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Open count reached max", + csid_hw->hw_intf->hw_idx); + return -EINVAL; + } + + /* Increment ref Count */ + csid_hw->hw_info->open_count++; + if (csid_hw->hw_info->open_count > 1) { + CAM_DBG(CAM_ISP, "CSID hw has already been enabled"); + return rc; + } + + CAM_DBG(CAM_ISP, "CSID:%d init CSID HW", + csid_hw->hw_intf->hw_idx); + + rc = cam_soc_util_get_clk_level(soc_info, csid_hw->clk_rate, + soc_info->src_clk_idx, &clk_lvl); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to get clk level for rate %d", + csid_hw->clk_rate); + goto err; + } + + CAM_DBG(CAM_ISP, "CSID clock lvl %d", clk_lvl); + + rc = cam_ife_csid_enable_soc_resources(soc_info, clk_lvl); + if (rc) { + CAM_ERR(CAM_ISP, "CSID:%d Enable SOC failed", + csid_hw->hw_intf->hw_idx); + goto err; + } + + csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_UP; + /* Reset CSID top */ + rc = cam_ife_csid_global_reset(csid_hw); + if (rc) + goto disable_soc; + + spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); + + /* clear all interrupts */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + + cam_io_w_mb(csid_reg->csi2_reg->csi2_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); + + if (csid_reg->cmn_reg->num_pix) + cam_io_w_mb(csid_reg->cmn_reg->ipp_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_clear_addr); + + if (csid_reg->cmn_reg->num_ppp) + cam_io_w_mb(csid_reg->cmn_reg->ppp_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_clear_addr); + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) + cam_io_w_mb(csid_reg->cmn_reg->rdi_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr); + + for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) + cam_io_w_mb(csid_reg->cmn_reg->udi_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[i]->csid_udi_irq_clear_addr); + + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); + + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_hw_version_addr); + CAM_DBG(CAM_ISP, "CSID:%d CSID HW version: 0x%x", + csid_hw->hw_intf->hw_idx, val); + + spin_lock_irqsave(&csid_hw->lock_state, flags); + csid_hw->fatal_err_detected = false; + csid_hw->device_enabled = 1; + spin_unlock_irqrestore(&csid_hw->lock_state, flags); + cam_tasklet_start(csid_hw->tasklet); + + return 0; + +disable_soc: + cam_ife_csid_disable_soc_resources(soc_info); + csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; +err: + csid_hw->hw_info->open_count--; + return rc; +} + +static int cam_ife_csid_disable_hw(struct cam_ife_csid_hw *csid_hw) +{ + int rc = -EINVAL; + struct cam_hw_soc_info *soc_info; + const struct cam_ife_csid_reg_offset *csid_reg; + unsigned long flags; + + /* Check for refcount */ + if (!csid_hw->hw_info->open_count) { + CAM_WARN(CAM_ISP, "Unbalanced disable_hw"); + return rc; + } + + /* Decrement ref Count */ + csid_hw->hw_info->open_count--; + + if (csid_hw->hw_info->open_count) { + rc = 0; + return rc; + } + + soc_info = &csid_hw->hw_info->soc_info; + csid_reg = csid_hw->csid_info->csid_reg; + + CAM_DBG(CAM_ISP, "%s:Calling Global Reset\n", __func__); + cam_ife_csid_global_reset(csid_hw); + CAM_DBG(CAM_ISP, "%s:Global Reset Done\n", __func__); + + CAM_DBG(CAM_ISP, "CSID:%d De-init CSID HW", + csid_hw->hw_intf->hw_idx); + + /*disable the top IRQ interrupt */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_mask_addr); + + rc = cam_ife_csid_disable_soc_resources(soc_info); + if (rc) + CAM_ERR(CAM_ISP, "CSID:%d Disable CSID SOC failed", + csid_hw->hw_intf->hw_idx); + + cam_tasklet_stop(csid_hw->tasklet); + spin_lock_irqsave(&csid_hw->lock_state, flags); + csid_hw->device_enabled = 0; + spin_unlock_irqrestore(&csid_hw->lock_state, flags); + csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; + csid_hw->error_irq_count = 0; + csid_hw->prev_boot_timestamp = 0; + + return rc; +} + + +static int cam_ife_csid_tpg_start(struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + uint32_t val = 0; + struct cam_hw_soc_info *soc_info; + const struct cam_ife_csid_reg_offset *csid_reg = NULL; + + csid_hw->tpg_start_cnt++; + if (csid_hw->tpg_start_cnt == 1) { + /*Enable the TPG */ + CAM_DBG(CAM_ISP, "CSID:%d start CSID TPG", + csid_hw->hw_intf->hw_idx); + + soc_info = &csid_hw->hw_info->soc_info; + { + uint32_t val; + uint32_t i; + uint32_t base = 0x600; + + CAM_DBG(CAM_ISP, "================ TPG ============"); + for (i = 0; i < 16; i++) { + val = cam_io_r_mb( + soc_info->reg_map[0].mem_base + + base + i * 4); + CAM_DBG(CAM_ISP, "reg 0x%x = 0x%x", + (base + i*4), val); + } + + CAM_DBG(CAM_ISP, "================ IPP ============="); + base = 0x200; + for (i = 0; i < 10; i++) { + val = cam_io_r_mb( + soc_info->reg_map[0].mem_base + + base + i * 4); + CAM_DBG(CAM_ISP, "reg 0x%x = 0x%x", + (base + i*4), val); + } + + CAM_DBG(CAM_ISP, "================ RX ============="); + base = 0x100; + for (i = 0; i < 5; i++) { + val = cam_io_r_mb( + soc_info->reg_map[0].mem_base + + base + i * 4); + CAM_DBG(CAM_ISP, "reg 0x%x = 0x%x", + (base + i*4), val); + } + } + + /* Enable the IFE force clock on for dual isp case */ + csid_reg = csid_hw->csid_info->csid_reg; + if (csid_hw->tpg_cfg.usage_type) { + rc = cam_ife_csid_enable_ife_force_clock_on(soc_info, + csid_reg->tpg_reg->tpg_cpas_ife_reg_offset); + if (rc) + return rc; + } + + CAM_DBG(CAM_ISP, "============ TPG control ============"); + val = (4 << 20); + val |= (0x80 << 8); + val |= (((csid_hw->csi2_rx_cfg.lane_num - 1) & 0x3) << 4); + val |= 7; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->tpg_reg->csid_tpg_ctrl_addr); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + 0x600); + CAM_DBG(CAM_ISP, "reg 0x%x = 0x%x", 0x600, val); + } + + return 0; +} + +static int cam_ife_csid_tpg_stop(struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + struct cam_hw_soc_info *soc_info; + const struct cam_ife_csid_reg_offset *csid_reg = NULL; + + if (csid_hw->tpg_start_cnt) + csid_hw->tpg_start_cnt--; + + if (csid_hw->tpg_start_cnt) + return 0; + + soc_info = &csid_hw->hw_info->soc_info; + csid_reg = csid_hw->csid_info->csid_reg; + + /* disable the TPG */ + if (!csid_hw->tpg_start_cnt) { + CAM_DBG(CAM_ISP, "CSID:%d stop CSID TPG", + csid_hw->hw_intf->hw_idx); + + /* Disable the IFE force clock on for dual isp case */ + if (csid_hw->tpg_cfg.usage_type) + rc = cam_ife_csid_disable_ife_force_clock_on(soc_info, + csid_reg->tpg_reg->tpg_cpas_ife_reg_offset); + + /*stop the TPG */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_hw->csid_info->csid_reg->tpg_reg->csid_tpg_ctrl_addr); + } + + return 0; +} + + +static int cam_ife_csid_config_tpg(struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t val = 0; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + CAM_DBG(CAM_ISP, "CSID:%d TPG config", + csid_hw->hw_intf->hw_idx); + + /* configure one DT, infinite frames */ + val = (0 << 16) | (1 << 10) | CAM_IFE_CSID_TPG_VC_VAL; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->tpg_reg->csid_tpg_vc_cfg0_addr); + + /* vertical blanking count = 0x3FF, horzontal blanking count = 0x740*/ + val = (0x3FF << 12) | 0x740; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->tpg_reg->csid_tpg_vc_cfg1_addr); + + cam_io_w_mb(0x12345678, soc_info->reg_map[0].mem_base + + csid_hw->csid_info->csid_reg->tpg_reg->csid_tpg_lfsr_seed_addr); + + val = csid_hw->tpg_cfg.width << 16 | + csid_hw->tpg_cfg.height; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->tpg_reg->csid_tpg_dt_n_cfg_0_addr); + + cam_io_w_mb(CAM_IFE_CSID_TPG_DT_VAL, soc_info->reg_map[0].mem_base + + csid_reg->tpg_reg->csid_tpg_dt_n_cfg_1_addr); + + /* + * in_format is the same as the input resource format. + * it is one larger than the register spec format. + */ + val = ((csid_hw->tpg_cfg.in_format - 1) << 16) | 0x8; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->tpg_reg->csid_tpg_dt_n_cfg_2_addr); + + /* static frame with split color bar */ + val = 1 << 5; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->tpg_reg->csid_tpg_color_bars_cfg_addr); + /* config pix pattern */ + cam_io_w_mb(csid_hw->tpg_cfg.test_pattern, + soc_info->reg_map[0].mem_base + + csid_reg->tpg_reg->csid_tpg_common_gen_cfg_addr); + + return 0; +} + +static int cam_ife_csid_enable_csi2( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + struct cam_ife_csid_cid_data *cid_data; + uint32_t val = 0; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + CAM_DBG(CAM_ISP, "CSID:%d count:%d config csi2 rx", + csid_hw->hw_intf->hw_idx, csid_hw->csi2_cfg_cnt); + + /* overflow check before increment */ + if (csid_hw->csi2_cfg_cnt == UINT_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Open count reached max", + csid_hw->hw_intf->hw_idx); + return -EINVAL; + } + + cid_data = (struct cam_ife_csid_cid_data *)res->res_priv; + + res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + csid_hw->csi2_cfg_cnt++; + if (csid_hw->csi2_cfg_cnt > 1) + return rc; + + /* rx cfg0 */ + val = 0; + val = (csid_hw->csi2_rx_cfg.lane_num - 1) | + (csid_hw->csi2_rx_cfg.lane_cfg << 4) | + (csid_hw->csi2_rx_cfg.lane_type << 24); + val |= (csid_hw->csi2_rx_cfg.phy_sel & + csid_reg->csi2_reg->csi2_rx_phy_num_mask) << 20; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg0_addr); + + /* rx cfg1*/ + val = (1 << csid_reg->csi2_reg->csi2_misr_enable_shift_val); + /* if VC value is more than 3 than set full width of VC */ + if (cid_data->vc > 3 || (cid_data->is_valid_vc1_dt1 && + cid_data->vc1 > 3)) + val |= (1 << csid_reg->csi2_reg->csi2_vc_mode_shift_val); + + /* enable packet ecc correction */ + val |= 1; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + + if (csid_hw->res_type == CAM_ISP_IFE_IN_RES_TPG) { + /* Config the TPG */ + rc = cam_ife_csid_config_tpg(csid_hw, res); + if (rc) { + res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + return rc; + } + } + + /*Enable the CSI2 rx interrupts */ + val = CSID_CSI2_RX_INFO_RST_DONE | + CSID_CSI2_RX_ERROR_TG_FIFO_OVERFLOW | + CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW | + CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW | + CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW | + CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW | + CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION | + CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION | + CSID_CSI2_RX_ERROR_CRC | + CSID_CSI2_RX_ERROR_ECC | + CSID_CSI2_RX_ERROR_MMAPPED_VC_DT | + CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW | + CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME | + CSID_CSI2_RX_ERROR_CPHY_PH_CRC; + + /* Enable the interrupt based on csid debug info set */ + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOT_IRQ) + val |= CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED | + CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED | + CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED | + CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED; + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOT_IRQ) + val |= CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED | + CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED | + CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED | + CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED; + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) + val |= CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED; + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) + val |= CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED; + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) + val |= CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + + return 0; +} + +static int cam_ife_csid_disable_csi2( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + if (res->res_id >= CAM_IFE_CSID_CID_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res id :%d", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + CAM_DBG(CAM_ISP, "CSID:%d cnt : %d Disable csi2 rx", + csid_hw->hw_intf->hw_idx, csid_hw->csi2_cfg_cnt); + + if (csid_hw->csi2_cfg_cnt) + csid_hw->csi2_cfg_cnt--; + + if (csid_hw->csi2_cfg_cnt) + return 0; + + /* Disable the CSI2 rx inerrupts */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + + /* Reset the Rx CFG registers */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg0_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + + res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + return 0; +} + +static void cam_ife_csid_halt_csi2( + struct cam_ife_csid_hw *csid_hw) +{ + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + CAM_INFO(CAM_ISP, "CSID: %d cnt: %d Halt csi2 rx", + csid_hw->hw_intf->hw_idx, csid_hw->csi2_cfg_cnt); + + /* Disable the CSI2 rx inerrupts */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + + /* Reset the Rx CFG registers */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg0_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE, + CAM_SUBDEV_MESSAGE_IRQ_ERR, + csid_hw->csi2_rx_cfg.phy_sel); +} + +static int cam_ife_csid_init_config_pxl_path( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + struct cam_ife_csid_path_cfg *path_data; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + const struct cam_ife_csid_pxl_reg_offset *pxl_reg = NULL; + bool is_ipp; + uint32_t decode_format = 0, plain_format = 0, val = 0; + uint32_t camera_hw_version; + + path_data = (struct cam_ife_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) { + is_ipp = true; + pxl_reg = csid_reg->ipp_reg; + } else { + is_ipp = false; + pxl_reg = csid_reg->ppp_reg; + } + + if (!pxl_reg) { + CAM_ERR(CAM_ISP, "CSID:%d %s:%d is not supported on HW", + csid_hw->hw_intf->hw_idx, + (is_ipp) ? "IPP" : "PPP", res->res_id); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Config %s Path", (is_ipp) ? "IPP" : "PPP"); + rc = cam_ife_csid_get_format_ipp_ppp(path_data->in_format, + &decode_format, &plain_format); + if (rc) + return rc; + + /* + * configure Pxl path and enable the time stamp capture. + * enable the HW measrurement blocks + */ + val = (path_data->vc << csid_reg->cmn_reg->vc_shift_val) | + (path_data->dt << csid_reg->cmn_reg->dt_shift_val) | + (path_data->cid << csid_reg->cmn_reg->dt_id_shift_val) | + (decode_format << csid_reg->cmn_reg->fmt_shift_val) | + (path_data->crop_enable << + csid_reg->cmn_reg->crop_h_en_shift_val) | + (path_data->crop_enable << + csid_reg->cmn_reg->crop_v_en_shift_val) | + (1 << 1) | 1; + + rc = cam_cpas_get_cpas_hw_version(&camera_hw_version); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to get HW version rc:%d", rc); + camera_hw_version = 0; + } + CAM_DBG(CAM_ISP, "HW version: %x", camera_hw_version); + + if (camera_hw_version == CAM_CPAS_TITAN_480_V100) + val |= (path_data->drop_enable << + csid_reg->cmn_reg->drop_h_en_shift_val) | + (path_data->drop_enable << + csid_reg->cmn_reg->drop_v_en_shift_val); + + if (path_data->horizontal_bin || path_data->qcfa_bin) { + val |= (1 << pxl_reg->horizontal_bin_en_shift_val); + if (path_data->qcfa_bin) + val |= (1 << pxl_reg->quad_cfa_bin_en_shift_val); + } + + if (is_ipp && csid_hw->binning_supported && + csid_hw->binning_enable) + val |= (1 << pxl_reg->quad_cfa_bin_en_shift_val); + + val |= (1 << pxl_reg->pix_store_en_shift_val); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + + if (path_data->is_valid_vc1_dt1 && + camera_hw_version == CAM_CPAS_TITAN_480_V100) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_multi_vcdt_cfg0_addr); + val |= ((path_data->vc1 << 2) | + (path_data->dt1 << 7) | 1); + } + + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg1_addr); + + /* select the post irq sub sample strobe for time stamp capture */ + val |= CSID_TIMESTAMP_STB_POST_IRQ; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg1_addr); + + if (path_data->crop_enable) { + val = (((path_data->end_pixel & 0xFFFF) << + csid_reg->cmn_reg->crop_shift) | + (path_data->start_pixel & 0xFFFF)); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_hcrop_addr); + CAM_DBG(CAM_ISP, "CSID:%d Horizontal crop config val: 0x%x", + csid_hw->hw_intf->hw_idx, val); + + val = (((path_data->end_line & 0xFFFF) << + csid_reg->cmn_reg->crop_shift) | + (path_data->start_line & 0xFFFF)); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_vcrop_addr); + CAM_DBG(CAM_ISP, "CSID:%d Vertical Crop config val: 0x%x", + csid_hw->hw_intf->hw_idx, val); + + /* Enable generating early eof strobe based on crop config. + * Skip for version 480 HW due to HW limitation. + */ + if (!(csid_hw->csid_debug & CSID_DEBUG_DISABLE_EARLY_EOF) && + (camera_hw_version != CAM_CPAS_TITAN_480_V100)) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + val |= (1 << pxl_reg->early_eof_en_shift_val); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + } + } + + /* set frame drop pattern to 0 and period to 1 */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_frm_drop_period_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_frm_drop_pattern_addr); + /* set irq sub sample pattern to 0 and period to 1 */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_irq_subsample_period_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_irq_subsample_pattern_addr); + /* set pxl drop pattern to 0 and period to 1 */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_pix_drop_pattern_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_pix_drop_period_addr); + /* set line drop pattern to 0 and period to 1 */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_line_drop_pattern_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_line_drop_period_addr); + + + /* Enable the Pxl path */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + val |= (1 << csid_reg->cmn_reg->path_en_shift_val); + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_HBI_VBI_INFO) + val |= csid_reg->cmn_reg->format_measure_en_val; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + + /* Enable Error Detection */ + if (pxl_reg->overflow_ctrl_en) { + val = pxl_reg->overflow_ctrl_en; + /* Overflow ctrl mode: 2 -> Detect overflow */ + val |= 0x8; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_err_recovery_cfg0_addr); + } + + /* Enable the HBI/VBI counter */ + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_HBI_VBI_INFO) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_format_measure_cfg0_addr); + val |= csid_reg->cmn_reg->measure_en_hbi_vbi_cnt_mask; + cam_io_w_mb(val, + soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_format_measure_cfg0_addr); + } + + /* configure the rx packet capture based on csid debug set */ + val = 0; + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) + val = ((1 << + csid_reg->csi2_reg->csi2_capture_short_pkt_en_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_short_pkt_vc_shift)); + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_long_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_long_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_long_pkt_vc_shift)); + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_vc_shift)); + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_capture_ctrl_addr); + CAM_DBG(CAM_ISP, "rx capture control value 0x%x", val); + + res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; + + return rc; +} + +static int cam_ife_csid_deinit_pxl_path( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + uint32_t val; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + const struct cam_ife_csid_pxl_reg_offset *pxl_reg = NULL; + bool is_ipp; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) { + is_ipp = true; + pxl_reg = csid_reg->ipp_reg; + } else { + is_ipp = false; + pxl_reg = csid_reg->ppp_reg; + } + + if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) { + CAM_ERR(CAM_ISP, + "CSID:%d %s Res type %d res_id:%d in wrong state %d", + csid_hw->hw_intf->hw_idx, + (is_ipp) ? "IPP" : "PPP", + res->res_type, res->res_id, res->res_state); + rc = -EINVAL; + } + + if (!pxl_reg) { + CAM_ERR(CAM_ISP, "CSID:%d %s %d is not supported on HW", + csid_hw->hw_intf->hw_idx, (is_ipp) ? "IPP" : "PPP", + res->res_id); + rc = -EINVAL; + goto end; + } + + /* Disable Error Recovery */ + if (pxl_reg->overflow_ctrl_en) + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_err_recovery_cfg0_addr); + + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + if (val & csid_reg->cmn_reg->format_measure_en_val) { + val &= ~csid_reg->cmn_reg->format_measure_en_val; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + + /* Disable the HBI/VBI counter */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_format_measure_cfg0_addr); + val &= ~csid_reg->cmn_reg->measure_en_hbi_vbi_cnt_mask; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_format_measure_cfg0_addr); + } + +end: + res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + return rc; +} + +static int cam_ife_csid_enable_pxl_path( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + struct cam_ife_csid_path_cfg *path_data; + const struct cam_ife_csid_pxl_reg_offset *pxl_reg = NULL; + bool is_ipp; + uint32_t val = 0; + + path_data = (struct cam_ife_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) { + is_ipp = true; + pxl_reg = csid_reg->ipp_reg; + } else { + is_ipp = false; + pxl_reg = csid_reg->ppp_reg; + } + + if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) { + CAM_ERR(CAM_ISP, + "CSID:%d %s path res type:%d res_id:%d Invalid state%d", + csid_hw->hw_intf->hw_idx, + (is_ipp) ? "IPP" : "PPP", + res->res_type, res->res_id, res->res_state); + return -EINVAL; + } + + if (!pxl_reg) { + CAM_ERR(CAM_ISP, "CSID:%d %s %d not supported on HW", + csid_hw->hw_intf->hw_idx, (is_ipp) ? "IPP" : "PPP", + res->res_id); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Enable %s path", (is_ipp) ? "IPP" : "PPP"); + + /* Set master or slave path */ + if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER) + /*Set halt mode as master */ + val = CSID_HALT_MODE_MASTER << 2; + else if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) + /*Set halt mode as slave and set master idx */ + val = path_data->master_idx << 4 | CSID_HALT_MODE_SLAVE << 2; + else + /* Default is internal halt mode */ + val = 0; + + /* + * Resume at frame boundary if Master or No Sync. + * Slave will get resume command from Master. + */ + if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER || + path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) + val |= CAM_CSID_RESUME_AT_FRAME_BOUNDARY; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + + CAM_DBG(CAM_ISP, "CSID:%d %s Ctrl val: 0x%x", + csid_hw->hw_intf->hw_idx, + (is_ipp) ? "IPP" : "PPP", val); + + /* Enable the required pxl path interrupts */ + val = CSID_PATH_INFO_RST_DONE | CSID_PATH_ERROR_FIFO_OVERFLOW; + + if (pxl_reg->ccif_violation_en) + val |= CSID_PATH_ERROR_CCIF_VIOLATION; + + if (pxl_reg->overflow_ctrl_en) + val |= CSID_PATH_OVERFLOW_RECOVERY; + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ) + val |= CSID_PATH_INFO_INPUT_SOF; + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ) + val |= CSID_PATH_INFO_INPUT_EOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_irq_mask_addr); + + CAM_DBG(CAM_ISP, "Enable %s IRQ mask 0x%x", + (is_ipp) ? "IPP" : "PPP", val); + + res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return 0; +} + +static int cam_ife_csid_disable_pxl_path( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res, + enum cam_ife_csid_halt_cmd stop_cmd) +{ + int rc = 0; + uint32_t val = 0; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + struct cam_ife_csid_path_cfg *path_data; + const struct cam_ife_csid_pxl_reg_offset *pxl_reg; + bool is_ipp; + + path_data = (struct cam_ife_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (res->res_id >= CAM_IFE_PIX_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res id%d", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + if (res->res_state == CAM_ISP_RESOURCE_STATE_INIT_HW || + res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_DBG(CAM_ISP, "CSID:%d Res:%d already in stopped state:%d", + csid_hw->hw_intf->hw_idx, res->res_id, res->res_state); + return rc; + } + + if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) { + is_ipp = true; + pxl_reg = csid_reg->ipp_reg; + } else { + is_ipp = false; + pxl_reg = csid_reg->ppp_reg; + } + + if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_DBG(CAM_ISP, "CSID:%d %s path Res:%d Invalid state%d", + csid_hw->hw_intf->hw_idx, (is_ipp) ? "IPP" : "PPP", + res->res_id, res->res_state); + return -EINVAL; + } + + if (!pxl_reg) { + CAM_ERR(CAM_ISP, "CSID:%d %s %d is not supported on HW", + csid_hw->hw_intf->hw_idx, (is_ipp) ? "IPP" : "PPP", + res->res_id); + return -EINVAL; + } + + if (stop_cmd != CAM_CSID_HALT_AT_FRAME_BOUNDARY && + stop_cmd != CAM_CSID_HALT_IMMEDIATELY) { + CAM_ERR(CAM_ISP, "CSID:%d %s path un supported stop command:%d", + csid_hw->hw_intf->hw_idx, (is_ipp) ? "IPP" : "PPP", + stop_cmd); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "CSID:%d res_id:%d %s path", + csid_hw->hw_intf->hw_idx, res->res_id, + (is_ipp) ? "IPP" : "PPP"); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_irq_mask_addr); + + if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER || + path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) { + /* configure Halt for master */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + val &= ~0x3; + val |= stop_cmd; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + } + + if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE && + stop_cmd == CAM_CSID_HALT_IMMEDIATELY) { + /* configure Halt for slave */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + val &= ~0xF; + val |= stop_cmd; + val |= (CSID_HALT_MODE_MASTER << 2); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + } + + return rc; +} + +static int cam_ife_csid_init_config_rdi_path( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + struct cam_ife_csid_path_cfg *path_data; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t path_format = 0, plain_fmt = 0, val = 0, id; + uint32_t format_measure_addr, camera_hw_version, packing_fmt = 0; + + path_data = (struct cam_ife_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + id = res->res_id; + if (!csid_reg->rdi_reg[id]) { + CAM_ERR(CAM_ISP, "CSID:%d RDI:%d is not supported on HW", + csid_hw->hw_intf->hw_idx, id); + return -EINVAL; + } + + rc = cam_ife_csid_get_format_rdi(path_data->in_format, + path_data->out_format, &path_format, &plain_fmt, &packing_fmt, + path_data->crop_enable || path_data->drop_enable); + if (rc) + return rc; + + /* + * RDI path config and enable the time stamp capture + * Enable the measurement blocks + */ + val = (path_data->vc << csid_reg->cmn_reg->vc_shift_val) | + (path_data->dt << csid_reg->cmn_reg->dt_shift_val) | + (path_data->cid << csid_reg->cmn_reg->dt_id_shift_val) | + (path_format << csid_reg->cmn_reg->fmt_shift_val) | + (plain_fmt << csid_reg->cmn_reg->plain_fmt_shit_val) | + (path_data->crop_enable << + csid_reg->cmn_reg->crop_h_en_shift_val) | + (path_data->crop_enable << + csid_reg->cmn_reg->crop_v_en_shift_val) | + (1 << 2) | 3; + + rc = cam_cpas_get_cpas_hw_version(&camera_hw_version); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to get HW version rc:%d", rc); + camera_hw_version = 0; + } + CAM_DBG(CAM_ISP, "HW version: %x", camera_hw_version); + + if (camera_hw_version == CAM_CPAS_TITAN_480_V100 || + camera_hw_version == CAM_CPAS_TITAN_175_V130) { + val |= (path_data->drop_enable << + csid_reg->cmn_reg->drop_h_en_shift_val) | + (path_data->drop_enable << + csid_reg->cmn_reg->drop_v_en_shift_val) | + (packing_fmt << + csid_reg->cmn_reg->packing_fmt_shift_val); + } + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); + + if (path_data->is_valid_vc1_dt1 && + camera_hw_version == CAM_CPAS_TITAN_480_V100) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_multi_vcdt_cfg0_addr); + val |= ((path_data->vc1 << 2) | + (path_data->dt1 << 7) | 1); + } + + /* select the post irq sub sample strobe for time stamp capture */ + cam_io_w_mb(CSID_TIMESTAMP_STB_POST_IRQ, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg1_addr); + + if (path_data->crop_enable) { + val = (((path_data->end_pixel & 0xFFFF) << + csid_reg->cmn_reg->crop_shift) | + (path_data->start_pixel & 0xFFFF)); + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_rpp_hcrop_addr); + CAM_DBG(CAM_ISP, "CSID:%d Horizontal crop config val: 0x%x", + csid_hw->hw_intf->hw_idx, val); + + val = (((path_data->end_line & 0xFFFF) << + csid_reg->cmn_reg->crop_shift) | + (path_data->start_line & 0xFFFF)); + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_rpp_vcrop_addr); + CAM_DBG(CAM_ISP, "CSID:%d Vertical Crop config val: 0x%x", + csid_hw->hw_intf->hw_idx, val); + } + + /* Enable Error Detection */ + if (csid_reg->rdi_reg[id]->overflow_ctrl_en) { + val = csid_reg->rdi_reg[id]->overflow_ctrl_en; + /* Overflow ctrl mode: 2 -> Detect overflow */ + val |= 0x8; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_err_recovery_cfg0_addr); + } + + /* set frame drop pattern to 0 and period to 1 */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_frm_drop_period_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_frm_drop_pattern_addr); + /* set IRQ sum sabmple */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_subsample_period_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_subsample_pattern_addr); + + /* set pixel drop pattern to 0 and period to 1 */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_rpp_pix_drop_pattern_addr); + + /* Write max value to pixel drop period due to a bug in ver 480 HW */ + if (camera_hw_version == CAM_CPAS_TITAN_480_V100 && + path_data->drop_enable) + cam_io_w_mb(0x1F, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_rpp_pix_drop_period_addr); + else + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_rpp_pix_drop_period_addr); + + /* set line drop pattern to 0 and period to 1 */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_rpp_line_drop_pattern_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_rpp_line_drop_period_addr); + + /* Configure the halt mode */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + + /* Enable the RPP path */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); + val |= (1 << csid_reg->cmn_reg->path_en_shift_val); + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_HBI_VBI_INFO) + val |= csid_reg->cmn_reg->format_measure_en_val; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); + + format_measure_addr = + csid_reg->rdi_reg[id]->csid_rdi_format_measure_cfg0_addr; + + /* Enable the HBI/VBI counter */ + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_HBI_VBI_INFO) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + format_measure_addr); + val |= csid_reg->cmn_reg->measure_en_hbi_vbi_cnt_mask; + cam_io_w_mb(val, + soc_info->reg_map[0].mem_base + format_measure_addr); + } + + /* configure the rx packet capture based on csid debug set */ + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) + val = ((1 << + csid_reg->csi2_reg->csi2_capture_short_pkt_en_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_short_pkt_vc_shift)); + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_long_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_long_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_long_pkt_vc_shift)); + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_vc_shift)); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_capture_ctrl_addr); + + res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; + + return rc; +} + +static int cam_ife_csid_init_config_udi_path( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + struct cam_ife_csid_path_cfg *path_data; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t path_format = 0, plain_fmt = 0, val = 0, val1, id; + uint32_t format_measure_addr, packing_fmt = 0; + + path_data = (struct cam_ife_csid_path_cfg *)res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + id = res->res_id - CAM_IFE_PIX_PATH_RES_UDI_0; + if ((id >= CAM_IFE_CSID_UDI_MAX) || (!csid_reg->udi_reg[id])) { + CAM_ERR(CAM_ISP, "CSID:%d UDI:%d is not supported on HW", + csid_hw->hw_intf->hw_idx, id); + return -EINVAL; + } + + rc = cam_ife_csid_get_format_rdi(path_data->in_format, + path_data->out_format, &path_format, &plain_fmt, &packing_fmt, + path_data->crop_enable || path_data->drop_enable); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed to get format in_format: %u out_format: %u rc: %d", + path_data->in_format, path_data->out_format, rc); + return rc; + } + + /* + * UDI path config and enable the time stamp capture + * Enable the measurement blocks + */ + val = (path_data->vc << csid_reg->cmn_reg->vc_shift_val) | + (path_data->dt << csid_reg->cmn_reg->dt_shift_val) | + (path_data->cid << csid_reg->cmn_reg->dt_id_shift_val) | + (path_format << csid_reg->cmn_reg->fmt_shift_val) | + (plain_fmt << csid_reg->cmn_reg->plain_fmt_shit_val) | + (path_data->crop_enable << + csid_reg->cmn_reg->crop_h_en_shift_val) | + (path_data->crop_enable << + csid_reg->cmn_reg->crop_v_en_shift_val) | + (1 << 2) | 3; + + val |= (packing_fmt << csid_reg->cmn_reg->packing_fmt_shift_val); + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_cfg0_addr); + + /* select the post irq sub sample strobe for time stamp capture */ + val1 = CSID_TIMESTAMP_STB_POST_IRQ; + + /* select the num bytes out per cycle */ + val1 |= (path_data->num_bytes_out << + csid_reg->cmn_reg->num_bytes_out_shift_val); + + cam_io_w_mb(val1, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_cfg1_addr); + + /* Enable Error Detection */ + if (csid_reg->udi_reg[id]->overflow_ctrl_en) { + val = csid_reg->udi_reg[id]->overflow_ctrl_en; + /* Overflow ctrl mode: 2 -> Detect overflow */ + val |= 0x8; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_err_recovery_cfg0_addr); + } + + /* set frame drop pattern to 0 and period to 1 */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_frm_drop_period_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_frm_drop_pattern_addr); + /* set IRQ sum sabmple */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_irq_subsample_period_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_irq_subsample_pattern_addr); + + /* set pixel drop pattern to 0 and period to 1 */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_rpp_pix_drop_pattern_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_rpp_pix_drop_period_addr); + /* set line drop pattern to 0 and period to 1 */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_rpp_line_drop_pattern_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_rpp_line_drop_period_addr); + + /* Configure the halt mode */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_ctrl_addr); + + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_cfg0_addr); + val |= (1 << csid_reg->cmn_reg->path_en_shift_val); + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_HBI_VBI_INFO) + val |= csid_reg->cmn_reg->format_measure_en_val; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_cfg0_addr); + + format_measure_addr = + csid_reg->udi_reg[id]->csid_udi_format_measure_cfg0_addr; + + /* Enable the HBI/VBI counter */ + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_HBI_VBI_INFO) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + format_measure_addr); + val |= csid_reg->cmn_reg->measure_en_hbi_vbi_cnt_mask; + cam_io_w_mb(val, + soc_info->reg_map[0].mem_base + format_measure_addr); + } + + /* configure the rx packet capture based on csid debug set */ + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) + val = ((1 << + csid_reg->csi2_reg->csi2_capture_short_pkt_en_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_short_pkt_vc_shift)); + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_long_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_long_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_long_pkt_vc_shift)); + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_vc_shift)); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_capture_ctrl_addr); + + res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; + + return rc; +} + +static int cam_ife_csid_deinit_udi_path( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + uint32_t id, val, format_measure_addr; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + id = res->res_id - CAM_IFE_PIX_PATH_RES_UDI_0; + + if ((res->res_id < CAM_IFE_PIX_PATH_RES_UDI_0) || + (res->res_id > CAM_IFE_PIX_PATH_RES_UDI_2) || + (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) || + (!csid_reg->udi_reg[id])) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res id%d state:%d", + csid_hw->hw_intf->hw_idx, res->res_id, + res->res_state); + return -EINVAL; + } + + /* Disable Error Recovery */ + if (csid_reg->udi_reg[id]->overflow_ctrl_en) { + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_err_recovery_cfg0_addr); + } + + format_measure_addr = + csid_reg->udi_reg[id]->csid_udi_format_measure_cfg0_addr; + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_HBI_VBI_INFO) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_cfg0_addr); + val &= ~csid_reg->cmn_reg->format_measure_en_val; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_cfg0_addr); + + /* Disable the HBI/VBI counter */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + format_measure_addr); + val &= ~csid_reg->cmn_reg->measure_en_hbi_vbi_cnt_mask; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + format_measure_addr); + } + + res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + return rc; +} + +static int cam_ife_csid_deinit_rdi_path( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + uint32_t id, val, format_measure_addr; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + id = res->res_id; + + if (res->res_id > CAM_IFE_PIX_PATH_RES_RDI_3 || + res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW || + !csid_reg->rdi_reg[id]) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res id%d state:%d", + csid_hw->hw_intf->hw_idx, res->res_id, + res->res_state); + return -EINVAL; + } + + /* Disable Error Recovery */ + if (csid_reg->rdi_reg[id]->overflow_ctrl_en) { + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_err_recovery_cfg0_addr); + } + + format_measure_addr = + csid_reg->rdi_reg[id]->csid_rdi_format_measure_cfg0_addr; + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_HBI_VBI_INFO) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); + val &= ~csid_reg->cmn_reg->format_measure_en_val; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); + + /* Disable the HBI/VBI counter */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + format_measure_addr); + val &= ~csid_reg->cmn_reg->measure_en_hbi_vbi_cnt_mask; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + format_measure_addr); + } + + res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + return rc; +} + +static int cam_ife_csid_enable_rdi_path( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t id, val; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + id = res->res_id; + + if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW || + res->res_id > CAM_IFE_PIX_PATH_RES_RDI_3 || + !csid_reg->rdi_reg[id]) { + CAM_ERR(CAM_ISP, + "CSID:%d invalid res type:%d res_id:%d state%d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, res->res_state); + return -EINVAL; + } + + /*resume at frame boundary */ + cam_io_w_mb(CAM_CSID_RESUME_AT_FRAME_BOUNDARY, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + + /* Enable the required RDI interrupts */ + val = CSID_PATH_INFO_RST_DONE | CSID_PATH_ERROR_FIFO_OVERFLOW; + + if (csid_reg->rdi_reg[id]->ccif_violation_en) + val |= CSID_PATH_ERROR_CCIF_VIOLATION; + + if (csid_reg->rdi_reg[id]->overflow_ctrl_en) + val |= CSID_PATH_OVERFLOW_RECOVERY; + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ) + val |= CSID_PATH_INFO_INPUT_SOF; + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ) + val |= CSID_PATH_INFO_INPUT_EOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); + + res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return 0; +} + +static int cam_ife_csid_enable_udi_path( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t id, val; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + id = res->res_id - CAM_IFE_PIX_PATH_RES_UDI_0; + + if ((res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) || + (res->res_id > CAM_IFE_PIX_PATH_RES_UDI_2) || + (res->res_id < CAM_IFE_PIX_PATH_RES_UDI_0) || + (!csid_reg->udi_reg[id])) { + CAM_ERR(CAM_ISP, + "CSID:%d invalid res type:%d res_id:%d state%d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, res->res_state); + return -EINVAL; + } + + /*resume at frame boundary */ + cam_io_w_mb(CAM_CSID_RESUME_AT_FRAME_BOUNDARY, + soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_ctrl_addr); + + /* Enable the required UDI interrupts */ + val = CSID_PATH_INFO_RST_DONE | CSID_PATH_ERROR_FIFO_OVERFLOW; + + if (csid_reg->udi_reg[id]->ccif_violation_en) + val |= CSID_PATH_ERROR_CCIF_VIOLATION; + + if (csid_reg->udi_reg[id]->overflow_ctrl_en) + val |= CSID_PATH_OVERFLOW_RECOVERY; + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ) + val |= CSID_PATH_INFO_INPUT_SOF; + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ) + val |= CSID_PATH_INFO_INPUT_EOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_irq_mask_addr); + + res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return 0; +} + +static int cam_ife_csid_disable_rdi_path( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res, + enum cam_ife_csid_halt_cmd stop_cmd) +{ + int rc = 0; + uint32_t id, val = 0; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + id = res->res_id; + + if ((res->res_id > CAM_IFE_PIX_PATH_RES_RDI_3) || + (!csid_reg->rdi_reg[res->res_id])) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d Invalid res id%d", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + if (res->res_state == CAM_ISP_RESOURCE_STATE_INIT_HW || + res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d Res:%d already in stopped state:%d", + csid_hw->hw_intf->hw_idx, + res->res_id, res->res_state); + return rc; + } + + if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d Res:%d Invalid res_state%d", + csid_hw->hw_intf->hw_idx, res->res_id, + res->res_state); + return -EINVAL; + } + + if (stop_cmd != CAM_CSID_HALT_AT_FRAME_BOUNDARY && + stop_cmd != CAM_CSID_HALT_IMMEDIATELY) { + CAM_ERR(CAM_ISP, "CSID:%d un supported stop command:%d", + csid_hw->hw_intf->hw_idx, stop_cmd); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "CSID:%d res_id:%d", + csid_hw->hw_intf->hw_idx, res->res_id); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); + + /* Halt the RDI path */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + val &= ~0x3; + val |= stop_cmd; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + + return rc; +} + +static int cam_ife_csid_disable_udi_path( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res, + enum cam_ife_csid_halt_cmd stop_cmd) +{ + int rc = 0; + uint32_t id, val = 0; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + id = res->res_id - CAM_IFE_PIX_PATH_RES_UDI_0; + + if ((res->res_id > CAM_IFE_PIX_PATH_RES_UDI_2) || + (res->res_id < CAM_IFE_PIX_PATH_RES_UDI_0) || + (!csid_reg->udi_reg[id])) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d Invalid res id%d", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + if (res->res_state == CAM_ISP_RESOURCE_STATE_INIT_HW || + res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d Res:%d already in stopped state:%d", + csid_hw->hw_intf->hw_idx, + res->res_id, res->res_state); + return rc; + } + + if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d Res:%d Invalid res_state%d", + csid_hw->hw_intf->hw_idx, res->res_id, + res->res_state); + return -EINVAL; + } + + if (stop_cmd != CAM_CSID_HALT_AT_FRAME_BOUNDARY && + stop_cmd != CAM_CSID_HALT_IMMEDIATELY) { + CAM_ERR(CAM_ISP, "CSID:%d un supported stop command:%d", + csid_hw->hw_intf->hw_idx, stop_cmd); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "CSID:%d res_id:%d", + csid_hw->hw_intf->hw_idx, res->res_id); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_irq_mask_addr); + + /* Halt the UDI path */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_ctrl_addr); + val &= ~0x3; + val |= stop_cmd; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[id]->csid_udi_ctrl_addr); + + return rc; +} + +static int cam_ife_csid_poll_stop_status( + struct cam_ife_csid_hw *csid_hw, + uint32_t res_mask) +{ + int rc = 0, id; + uint32_t csid_status_addr = 0, val = 0, res_id = 0; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + for (; res_id < CAM_IFE_PIX_PATH_RES_MAX; res_id++, res_mask >>= 1) { + if ((res_mask & 0x1) == 0) + continue; + val = 0; + + if (res_id == CAM_IFE_PIX_PATH_RES_IPP) { + csid_status_addr = + csid_reg->ipp_reg->csid_pxl_status_addr; + } else if (res_id == CAM_IFE_PIX_PATH_RES_PPP) { + csid_status_addr = + csid_reg->ppp_reg->csid_pxl_status_addr; + } else if (res_id == CAM_IFE_PIX_PATH_RES_RDI_0 || + res_id == CAM_IFE_PIX_PATH_RES_RDI_1 || + res_id == CAM_IFE_PIX_PATH_RES_RDI_2 || + res_id == CAM_IFE_PIX_PATH_RES_RDI_3) { + csid_status_addr = + csid_reg->rdi_reg[res_id]->csid_rdi_status_addr; + } else if (res_id == CAM_IFE_PIX_PATH_RES_UDI_0 || + res_id == CAM_IFE_PIX_PATH_RES_UDI_1 || + res_id == CAM_IFE_PIX_PATH_RES_UDI_2) { + id = res_id - CAM_IFE_PIX_PATH_RES_UDI_0; + csid_status_addr = + csid_reg->udi_reg[id]->csid_udi_status_addr; + } else { + CAM_ERR(CAM_ISP, "Invalid res_id: %u", res_id); + rc = -EINVAL; + break; + } + + CAM_DBG(CAM_ISP, "start polling CSID:%d res_id:%d", + csid_hw->hw_intf->hw_idx, res_id); + + rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + + csid_status_addr, val, (val & 0x1) == 0x1, + CAM_IFE_CSID_TIMEOUT_SLEEP_US, + CAM_IFE_CSID_TIMEOUT_ALL_US); + if (rc < 0) { + CAM_ERR(CAM_ISP, "CSID:%d res:%d halt failed rc %d", + csid_hw->hw_intf->hw_idx, res_id, rc); + rc = -ETIMEDOUT; + break; + } + CAM_DBG(CAM_ISP, "End polling CSID:%d res_id:%d", + csid_hw->hw_intf->hw_idx, res_id); + } + + return rc; +} + +static int cam_ife_csid_get_hbi_vbi( + struct cam_ife_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + uint32_t hbi, vbi; + int32_t id; + const struct cam_ife_csid_reg_offset *csid_reg; + const struct cam_ife_csid_rdi_reg_offset *rdi_reg; + const struct cam_ife_csid_udi_reg_offset *udi_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH || + res->res_id >= CAM_IFE_PIX_PATH_RES_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res_type:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid dev state :%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + return -EINVAL; + } + + if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) { + hbi = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_format_measure1_addr); + vbi = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_format_measure2_addr); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_PPP) { + hbi = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_format_measure1_addr); + vbi = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_format_measure2_addr); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_RDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_2 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_3) { + rdi_reg = csid_reg->rdi_reg[res->res_id]; + hbi = cam_io_r_mb(soc_info->reg_map[0].mem_base + + rdi_reg->csid_rdi_format_measure1_addr); + vbi = cam_io_r_mb(soc_info->reg_map[0].mem_base + + rdi_reg->csid_rdi_format_measure2_addr); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_UDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_2) { + id = res->res_id - CAM_IFE_PIX_PATH_RES_UDI_0; + udi_reg = csid_reg->udi_reg[id]; + hbi = cam_io_r_mb(soc_info->reg_map[0].mem_base + + udi_reg->csid_udi_format_measure1_addr); + vbi = cam_io_r_mb(soc_info->reg_map[0].mem_base + + udi_reg->csid_udi_format_measure2_addr); + } else { + CAM_ERR(CAM_ISP, "Invalid res_id: %u", res->res_id); + return -EINVAL; + } + + CAM_INFO_RATE_LIMIT(CAM_ISP, + "Device %s index %u Resource %u HBI: 0x%x VBI: 0x%x", + soc_info->dev_name, soc_info->index, + res->res_id, hbi, vbi); + + return 0; +} + +static int cam_ife_csid_get_time_stamp( + struct cam_ife_csid_hw *csid_hw, void *cmd_args) +{ + struct cam_csid_get_time_stamp_args *time_stamp; + struct cam_isp_resource_node *res; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + const struct cam_ife_csid_rdi_reg_offset *rdi_reg; + const struct cam_ife_csid_udi_reg_offset *udi_reg; + struct timespec64 ts; + uint32_t time_32, id; + uint64_t time_delta; + + time_stamp = (struct cam_csid_get_time_stamp_args *)cmd_args; + res = time_stamp->node_res; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH || + res->res_id >= CAM_IFE_PIX_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res_type:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid dev state :%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + return -EINVAL; + } + + if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) { + time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_timestamp_curr1_sof_addr); + time_stamp->time_stamp_val = (uint64_t) time_32; + time_stamp->time_stamp_val = time_stamp->time_stamp_val << 32; + time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_timestamp_curr0_sof_addr); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_PPP) { + time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_timestamp_curr1_sof_addr); + time_stamp->time_stamp_val = (uint64_t) time_32; + time_stamp->time_stamp_val = time_stamp->time_stamp_val << 32; + time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_timestamp_curr0_sof_addr); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_RDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_2 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_3) { + id = res->res_id; + rdi_reg = csid_reg->rdi_reg[id]; + time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + + rdi_reg->csid_rdi_timestamp_curr1_sof_addr); + time_stamp->time_stamp_val = (uint64_t) time_32; + time_stamp->time_stamp_val = time_stamp->time_stamp_val << 32; + + time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + + rdi_reg->csid_rdi_timestamp_curr0_sof_addr); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_UDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_2) { + id = res->res_id - CAM_IFE_PIX_PATH_RES_UDI_0; + udi_reg = csid_reg->udi_reg[id]; + time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + + udi_reg->csid_udi_timestamp_curr1_sof_addr); + time_stamp->time_stamp_val = (uint64_t) time_32; + time_stamp->time_stamp_val = time_stamp->time_stamp_val << 32; + + time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + + udi_reg->csid_udi_timestamp_curr0_sof_addr); + } else { + CAM_ERR(CAM_ISP, "Invalid res_id: %u", res->res_id); + return -EINVAL; + } + + time_stamp->time_stamp_val |= (uint64_t) time_32; + time_stamp->time_stamp_val = mul_u64_u32_div( + time_stamp->time_stamp_val, + CAM_IFE_CSID_QTIMER_MUL_FACTOR, + CAM_IFE_CSID_QTIMER_DIV_FACTOR); + + if (!csid_hw->prev_boot_timestamp) { + get_monotonic_boottime64(&ts); + time_stamp->boot_timestamp = + (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); + csid_hw->prev_qtimer_ts = 0; + CAM_DBG(CAM_ISP, "timestamp:%lld", + time_stamp->boot_timestamp); + } else { + time_delta = time_stamp->time_stamp_val - + csid_hw->prev_qtimer_ts; + time_stamp->boot_timestamp = + csid_hw->prev_boot_timestamp + time_delta; + } + csid_hw->prev_qtimer_ts = time_stamp->time_stamp_val; + csid_hw->prev_boot_timestamp = time_stamp->boot_timestamp; + + return 0; +} + +static int cam_ife_csid_set_csid_debug(struct cam_ife_csid_hw *csid_hw, + void *cmd_args) +{ + uint32_t *csid_debug; + + csid_debug = (uint32_t *) cmd_args; + csid_hw->csid_debug = *csid_debug; + CAM_DBG(CAM_ISP, "CSID:%d set csid debug value:%d", + csid_hw->hw_intf->hw_idx, csid_hw->csid_debug); + + return 0; +} + +int cam_ife_csid_get_hw_caps(void *hw_priv, + void *get_hw_cap_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_ife_csid_hw_caps *hw_caps; + struct cam_ife_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + const struct cam_ife_csid_reg_offset *csid_reg; + + if (!hw_priv || !get_hw_cap_args) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; + csid_reg = csid_hw->csid_info->csid_reg; + hw_caps = (struct cam_ife_csid_hw_caps *) get_hw_cap_args; + + hw_caps->num_rdis = csid_reg->cmn_reg->num_rdis; + hw_caps->num_pix = csid_reg->cmn_reg->num_pix; + hw_caps->num_ppp = csid_reg->cmn_reg->num_ppp; + hw_caps->major_version = csid_reg->cmn_reg->major_version; + hw_caps->minor_version = csid_reg->cmn_reg->minor_version; + hw_caps->version_incr = csid_reg->cmn_reg->version_incr; + + CAM_DBG(CAM_ISP, + "CSID:%d No rdis:%d, no pix:%d, major:%d minor:%d ver :%d", + csid_hw->hw_intf->hw_idx, hw_caps->num_rdis, + hw_caps->num_pix, hw_caps->major_version, + hw_caps->minor_version, hw_caps->version_incr); + + return rc; +} + +int cam_ife_csid_reset(void *hw_priv, + void *reset_args, uint32_t arg_size) +{ + struct cam_ife_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_csid_reset_cfg_args *reset; + int rc = 0; + + if (!hw_priv || !reset_args || (arg_size != + sizeof(struct cam_csid_reset_cfg_args))) { + CAM_ERR(CAM_ISP, "CSID:Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; + reset = (struct cam_csid_reset_cfg_args *)reset_args; + + mutex_lock(&csid_hw->hw_info->hw_mutex); + switch (reset->reset_type) { + case CAM_IFE_CSID_RESET_GLOBAL: + rc = cam_ife_csid_global_reset(csid_hw); + break; + case CAM_IFE_CSID_RESET_PATH: + rc = cam_ife_csid_path_reset(csid_hw, reset); + break; + default: + CAM_ERR(CAM_ISP, "CSID:Invalid reset type :%d", + reset->reset_type); + rc = -EINVAL; + break; + } + mutex_unlock(&csid_hw->hw_info->hw_mutex); + + return rc; +} + +int cam_ife_csid_reserve(void *hw_priv, + void *reserve_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_ife_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_csid_hw_reserve_resource_args *reserv; + + if (!hw_priv || !reserve_args || (arg_size != + sizeof(struct cam_csid_hw_reserve_resource_args))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; + reserv = (struct cam_csid_hw_reserve_resource_args *)reserve_args; + + CAM_DBG(CAM_ISP, "res_type %d, CSID: %u", + reserv->res_type, csid_hw->hw_intf->hw_idx); + + mutex_lock(&csid_hw->hw_info->hw_mutex); + switch (reserv->res_type) { + case CAM_ISP_RESOURCE_CID: + rc = cam_ife_csid_cid_reserve(csid_hw, reserv); + break; + case CAM_ISP_RESOURCE_PIX_PATH: + rc = cam_ife_csid_path_reserve(csid_hw, reserv); + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type :%d", + csid_hw->hw_intf->hw_idx, reserv->res_type); + rc = -EINVAL; + break; + } + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return rc; +} + +int cam_ife_csid_release(void *hw_priv, + void *release_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_ife_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + struct cam_ife_csid_cid_data *cid_data; + + if (!hw_priv || !release_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; + res = (struct cam_isp_resource_node *)release_args; + + mutex_lock(&csid_hw->hw_info->hw_mutex); + csid_hw->event_cb = NULL; + csid_hw->priv = NULL; + if ((res->res_type == CAM_ISP_RESOURCE_CID && + res->res_id >= CAM_IFE_CSID_CID_MAX) || + (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && + res->res_id >= CAM_IFE_PIX_PATH_RES_MAX)) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + rc = -EINVAL; + goto end; + } + + if ((res->res_state <= CAM_ISP_RESOURCE_STATE_AVAILABLE) || + (res->res_state >= CAM_ISP_RESOURCE_STATE_STREAMING)) { + CAM_WARN(CAM_ISP, + "CSID:%d res type:%d Res %d in state %d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, + res->res_state); + goto end; + } + + CAM_DBG(CAM_ISP, "CSID:%d res type :%d Resource id:%d", + csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); + + switch (res->res_type) { + case CAM_ISP_RESOURCE_CID: + cid_data = (struct cam_ife_csid_cid_data *) res->res_priv; + if (cid_data->cnt) + cid_data->cnt--; + + if (!cid_data->cnt) + res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + if (csid_hw->csi2_reserve_cnt) + csid_hw->csi2_reserve_cnt--; + + if (!csid_hw->csi2_reserve_cnt) + memset(&csid_hw->csi2_rx_cfg, 0, + sizeof(struct cam_ife_csid_csi2_rx_cfg)); + + CAM_DBG(CAM_ISP, "CSID:%d res id :%d cnt:%d reserv cnt:%d", + csid_hw->hw_intf->hw_idx, + res->res_id, cid_data->cnt, csid_hw->csi2_reserve_cnt); + + break; + case CAM_ISP_RESOURCE_PIX_PATH: + res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + rc = -EINVAL; + break; + } + +end: + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_ife_csid_reset_regs( + struct cam_ife_csid_hw *csid_hw, bool reset_hw) +{ + int rc = 0; + const struct cam_ife_csid_reg_offset *csid_reg = + csid_hw->csid_info->csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t val = 0; + unsigned long flags; + + soc_info = &csid_hw->hw_info->soc_info; + + reinit_completion(&csid_hw->csid_top_complete); + + spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); + + /* clear the top interrupt first */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + if (reset_hw) { + /* enable top reset complete IRQ */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_mask_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + } + + /* perform the top CSID registers reset */ + val = reset_hw ? csid_reg->cmn_reg->csid_rst_stb : + csid_reg->cmn_reg->csid_reg_rst_stb; + cam_io_w_mb(val, + soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_rst_strobes_addr); + + /* + * for SW reset, we enable the IRQ after since the mask + * register has been reset + */ + if (!reset_hw) { + /* enable top reset complete IRQ */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_mask_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + } + + spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); + CAM_DBG(CAM_ISP, "CSID reset start"); + rc = wait_for_completion_timeout(&csid_hw->csid_top_complete, + msecs_to_jiffies(IFE_CSID_TIMEOUT)); + if (rc <= 0) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_status_addr); + if (val & 0x1) { + /* clear top reset IRQ */ + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + CAM_DBG(CAM_ISP, "CSID:%d %s reset completed %d", + csid_hw->hw_intf->hw_idx, + reset_hw ? "hw" : "sw", + rc); + rc = 0; + goto end; + } + CAM_ERR(CAM_ISP, "CSID:%d csid_reset %s fail rc = %d", + csid_hw->hw_intf->hw_idx, reset_hw ? "hw" : "sw", rc); + rc = -ETIMEDOUT; + goto end; + } else { + CAM_DBG(CAM_ISP, "CSID:%d %s reset completed %d", + csid_hw->hw_intf->hw_idx, reset_hw ? "hw" : "sw", rc); + rc = 0; + } + +end: + return rc; +} + +int cam_ife_csid_init_hw(void *hw_priv, + void *init_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_ife_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + const struct cam_ife_csid_reg_offset *csid_reg; + + if (!hw_priv || !init_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; + res = (struct cam_isp_resource_node *)init_args; + csid_reg = csid_hw->csid_info->csid_reg; + + mutex_lock(&csid_hw->hw_info->hw_mutex); + if ((res->res_type == CAM_ISP_RESOURCE_CID && + res->res_id >= CAM_IFE_CSID_CID_MAX) || + (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && + res->res_id >= CAM_IFE_PIX_PATH_RES_MAX)) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res tpe:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + rc = -EINVAL; + goto end; + } + + if ((res->res_type == CAM_ISP_RESOURCE_PIX_PATH) && + (res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED)) { + CAM_ERR(CAM_ISP, + "CSID:%d res type:%d res_id:%dInvalid state %d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, res->res_state); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ISP, "CSID:%d res type :%d res_id:%d", + csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); + + /* Initialize the csid hardware */ + rc = cam_ife_csid_enable_hw(csid_hw); + if (rc) + goto end; + + switch (res->res_type) { + case CAM_ISP_RESOURCE_CID: + rc = cam_ife_csid_enable_csi2(csid_hw, res); + break; + case CAM_ISP_RESOURCE_PIX_PATH: + if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP || + res->res_id == CAM_IFE_PIX_PATH_RES_PPP) { + rc = cam_ife_csid_init_config_pxl_path(csid_hw, res); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_RDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_2 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_3) { + rc = cam_ife_csid_init_config_rdi_path(csid_hw, res); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_UDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_2) { + rc = cam_ife_csid_init_config_udi_path(csid_hw, res); + } else { + CAM_ERR(CAM_ISP, "Invalid res_id: %u", res->res_id); + rc = -EINVAL; + goto end; + } + + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type state %d", + csid_hw->hw_intf->hw_idx, + res->res_type); + break; + } + + rc = cam_ife_csid_reset_regs(csid_hw, true); + if (rc < 0) + CAM_ERR(CAM_ISP, "CSID: Failed in HW reset"); + + if (rc) + cam_ife_csid_disable_hw(csid_hw); + +end: + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return rc; +} + +int cam_ife_csid_deinit_hw(void *hw_priv, + void *deinit_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_ife_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + + if (!hw_priv || !deinit_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "CSID:Invalid arguments"); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Enter"); + res = (struct cam_isp_resource_node *)deinit_args; + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; + + mutex_lock(&csid_hw->hw_info->hw_mutex); + if (res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_DBG(CAM_ISP, "CSID:%d Res:%d already in De-init state", + csid_hw->hw_intf->hw_idx, + res->res_id); + goto end; + } + + switch (res->res_type) { + case CAM_ISP_RESOURCE_CID: + CAM_DBG(CAM_ISP, "De-Init ife_csid"); + rc = cam_ife_csid_disable_csi2(csid_hw, res); + break; + case CAM_ISP_RESOURCE_PIX_PATH: + CAM_DBG(CAM_ISP, "De-Init Pix Path: %d\n", res->res_id); + if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP || + res->res_id == CAM_IFE_PIX_PATH_RES_PPP) { + rc = cam_ife_csid_deinit_pxl_path(csid_hw, res); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_RDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_2 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_3) { + rc = cam_ife_csid_deinit_rdi_path(csid_hw, res); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_UDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_2) { + rc = cam_ife_csid_deinit_udi_path(csid_hw, res); + } else { + CAM_ERR(CAM_ISP, "Invalid res_id: %u", res->res_id); + rc = -EINVAL; + goto end; + } + + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid Res type %d", + csid_hw->hw_intf->hw_idx, + res->res_type); + goto end; + } + + /* Disable CSID HW */ + CAM_DBG(CAM_ISP, "Disabling CSID Hw\n"); + cam_ife_csid_disable_hw(csid_hw); + CAM_DBG(CAM_ISP, "%s: Exit\n", __func__); + +end: + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return rc; +} + +int cam_ife_csid_start(void *hw_priv, void *start_args, + uint32_t arg_size) +{ + int rc = 0; + struct cam_ife_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + const struct cam_ife_csid_reg_offset *csid_reg; + + if (!hw_priv || !start_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; + res = (struct cam_isp_resource_node *)start_args; + csid_reg = csid_hw->csid_info->csid_reg; + + if ((res->res_type == CAM_ISP_RESOURCE_CID && + res->res_id >= CAM_IFE_CSID_CID_MAX) || + (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && + res->res_id >= CAM_IFE_PIX_PATH_RES_MAX)) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res tpe:%d res id:%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + rc = -EINVAL; + goto end; + } + + /* Reset sof irq debug fields */ + csid_hw->sof_irq_triggered = false; + csid_hw->irq_debug_cnt = 0; + + CAM_DBG(CAM_ISP, "CSID:%d res_type :%d res_id:%d", + csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); + + switch (res->res_type) { + case CAM_ISP_RESOURCE_CID: + if (csid_hw->res_type == CAM_ISP_IFE_IN_RES_TPG) + rc = cam_ife_csid_tpg_start(csid_hw, res); + break; + case CAM_ISP_RESOURCE_PIX_PATH: + if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP || + res->res_id == CAM_IFE_PIX_PATH_RES_PPP) { + rc = cam_ife_csid_enable_pxl_path(csid_hw, res); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_RDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_2 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_3) { + rc = cam_ife_csid_enable_rdi_path(csid_hw, res); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_UDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_2) { + rc = cam_ife_csid_enable_udi_path(csid_hw, res); + } else { + CAM_ERR(CAM_ISP, "Invalid res_id: %u", res->res_id); + rc = -EINVAL; + goto end; + } + + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type%d", + csid_hw->hw_intf->hw_idx, + res->res_type); + break; + } +end: + return rc; +} + +int cam_ife_csid_stop(void *hw_priv, + void *stop_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_ife_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + struct cam_csid_hw_stop_args *csid_stop; + uint32_t i; + uint32_t res_mask = 0; + + if (!hw_priv || !stop_args || + (arg_size != sizeof(struct cam_csid_hw_stop_args))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + csid_stop = (struct cam_csid_hw_stop_args *) stop_args; + + if (!csid_stop->num_res) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; + CAM_DBG(CAM_ISP, "CSID:%d num_res %d", + csid_hw->hw_intf->hw_idx, + csid_stop->num_res); + + /* Stop the resource first */ + for (i = 0; i < csid_stop->num_res; i++) { + res = csid_stop->node_res[i]; + CAM_DBG(CAM_ISP, "CSID:%d res_type %d res_id %d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id); + switch (res->res_type) { + case CAM_ISP_RESOURCE_CID: + if (csid_hw->res_type == CAM_ISP_IFE_IN_RES_TPG) + rc = cam_ife_csid_tpg_stop(csid_hw, res); + break; + case CAM_ISP_RESOURCE_PIX_PATH: + res_mask |= (1 << res->res_id); + if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP || + res->res_id == CAM_IFE_PIX_PATH_RES_PPP) { + rc = cam_ife_csid_disable_pxl_path(csid_hw, + res, csid_stop->stop_cmd); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_RDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_2 || + res->res_id == CAM_IFE_PIX_PATH_RES_RDI_3) { + rc = cam_ife_csid_disable_rdi_path(csid_hw, + res, csid_stop->stop_cmd); + } else if (res->res_id == CAM_IFE_PIX_PATH_RES_UDI_0 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_1 || + res->res_id == CAM_IFE_PIX_PATH_RES_UDI_2) { + rc = cam_ife_csid_disable_udi_path(csid_hw, + res, csid_stop->stop_cmd); + } else { + CAM_ERR(CAM_ISP, "Invalid res_id: %u", + res->res_id); + return -EINVAL; + } + + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type%d", + csid_hw->hw_intf->hw_idx, + res->res_type); + break; + } + } + + if (res_mask) + rc = cam_ife_csid_poll_stop_status(csid_hw, res_mask); + + for (i = 0; i < csid_stop->num_res; i++) { + res = csid_stop->node_res[i]; + res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; + } + + CAM_DBG(CAM_ISP, "%s: Exit\n", __func__); + + return rc; + +} + +int cam_ife_csid_read(void *hw_priv, + void *read_args, uint32_t arg_size) +{ + CAM_ERR(CAM_ISP, "CSID: un supported"); + + return -EINVAL; +} + +int cam_ife_csid_write(void *hw_priv, + void *write_args, uint32_t arg_size) +{ + CAM_ERR(CAM_ISP, "CSID: un supported"); + return -EINVAL; +} + +static int cam_ife_csid_sof_irq_debug( + struct cam_ife_csid_hw *csid_hw, void *cmd_args) +{ + int i = 0; + uint32_t val = 0; + bool sof_irq_enable = false; + const struct cam_ife_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (*((uint32_t *)cmd_args) == 1) + sof_irq_enable = true; + + if (csid_hw->hw_info->hw_state == + CAM_HW_STATE_POWER_DOWN) { + CAM_WARN(CAM_ISP, + "CSID powered down unable to %s sof irq", + (sof_irq_enable == true) ? "enable" : "disable"); + return 0; + } + + if (csid_reg->ipp_reg) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + + if (val) { + if (sof_irq_enable) + val |= CSID_PATH_INFO_INPUT_SOF; + else + val &= ~CSID_PATH_INFO_INPUT_SOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + val = 0; + } + } + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); + if (val) { + if (sof_irq_enable) + val |= CSID_PATH_INFO_INPUT_SOF; + else + val &= ~CSID_PATH_INFO_INPUT_SOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); + val = 0; + } + } + + for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[i]->csid_udi_irq_mask_addr); + if (val) { + if (sof_irq_enable) + val |= CSID_PATH_INFO_INPUT_SOF; + else + val &= ~CSID_PATH_INFO_INPUT_SOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[i]->csid_udi_irq_mask_addr); + val = 0; + } + } + + if (sof_irq_enable) { + csid_hw->csid_debug |= CSID_DEBUG_ENABLE_SOF_IRQ; + csid_hw->sof_irq_triggered = true; + } else { + csid_hw->csid_debug &= ~CSID_DEBUG_ENABLE_SOF_IRQ; + csid_hw->sof_irq_triggered = false; + } + + CAM_INFO(CAM_ISP, "SOF freeze: CSID SOF irq %s", + (sof_irq_enable == true) ? "enabled" : "disabled"); + + return 0; +} + +static int cam_ife_csid_set_csid_clock( + struct cam_ife_csid_hw *csid_hw, void *cmd_args) +{ + struct cam_ife_csid_clock_update_args *clk_update = NULL; + + if (!csid_hw) + return -EINVAL; + + clk_update = + (struct cam_ife_csid_clock_update_args *)cmd_args; + + csid_hw->clk_rate = clk_update->clk_rate; + CAM_INFO(CAM_ISP, "CSID clock rate %llu", csid_hw->clk_rate); + + return 0; +} + +static int cam_ife_csid_set_csid_qcfa( + struct cam_ife_csid_hw *csid_hw, void *cmd_args) +{ + struct cam_ife_csid_qcfa_update_args *qcfa_update = NULL; + + if (!csid_hw) + return -EINVAL; + + qcfa_update = + (struct cam_ife_csid_qcfa_update_args *)cmd_args; + + csid_hw->binning_supported = qcfa_update->qcfa_binning; + CAM_DBG(CAM_ISP, "CSID QCFA binning %d", csid_hw->binning_supported); + + return 0; +} + +static int cam_ife_csid_dump_hw( + struct cam_ife_csid_hw *csid_hw, void *cmd_args) +{ + int i; + uint8_t *dst; + uint32_t *addr, *start; + uint32_t min_len; + uint32_t num_reg; + size_t remain_len; + struct cam_isp_hw_dump_header *hdr; + struct cam_isp_hw_dump_args *dump_args = + (struct cam_isp_hw_dump_args *)cmd_args; + struct cam_hw_soc_info *soc_info; + + if (!dump_args) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + if (!dump_args->cpu_addr || !dump_args->buf_len) { + CAM_ERR(CAM_ISP, + "Invalid params %pK %zu", + (void *)dump_args->cpu_addr, + dump_args->buf_len); + return -EINVAL; + } + soc_info = &csid_hw->hw_info->soc_info; + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_ISP, + "Dump offset overshoot offset %zu buf_len %zu", + dump_args->offset, dump_args->buf_len); + return -ENOSPC; + } + min_len = soc_info->reg_map[0].size + + sizeof(struct cam_isp_hw_dump_header) + + sizeof(uint32_t); + remain_len = dump_args->buf_len - dump_args->offset; + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu, min %u", + remain_len, min_len); + return -ENOSPC; + } + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "CSID_REG:"); + addr = (uint32_t *)(dst + sizeof(struct cam_isp_hw_dump_header)); + + start = addr; + num_reg = soc_info->reg_map[0].size/4; + hdr->word_size = sizeof(uint32_t); + *addr = soc_info->index; + addr++; + for (i = 0; i < num_reg; i++) { + addr[0] = soc_info->mem_block[0]->start + (i*4); + addr[1] = cam_io_r(soc_info->reg_map[0].mem_base + + (i*4)); + addr += 2; + } + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + CAM_DBG(CAM_ISP, "offset %zu", dump_args->offset); + return 0; +} + +static int cam_ife_csid_process_cmd(void *hw_priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_ife_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res = NULL; + + if (!hw_priv || !cmd_args) { + CAM_ERR(CAM_ISP, "CSID: Invalid arguments"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; + + switch (cmd_type) { + case CAM_IFE_CSID_CMD_GET_TIME_STAMP: + rc = cam_ife_csid_get_time_stamp(csid_hw, cmd_args); + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_HBI_VBI_INFO) { + res = ((struct cam_csid_get_time_stamp_args *) + cmd_args)->node_res; + cam_ife_csid_get_hbi_vbi(csid_hw, res); + } + break; + case CAM_IFE_CSID_SET_CSID_DEBUG: + rc = cam_ife_csid_set_csid_debug(csid_hw, cmd_args); + break; + case CAM_IFE_CSID_SOF_IRQ_DEBUG: + rc = cam_ife_csid_sof_irq_debug(csid_hw, cmd_args); + break; + case CAM_ISP_HW_CMD_CSID_CLOCK_UPDATE: + rc = cam_ife_csid_set_csid_clock(csid_hw, cmd_args); + break; + case CAM_ISP_HW_CMD_CSID_QCFA_SUPPORTED: + rc = cam_ife_csid_set_csid_qcfa(csid_hw, cmd_args); + break; + case CAM_ISP_HW_CMD_DUMP_HW: + rc = cam_ife_csid_dump_hw(csid_hw, cmd_args); + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d unsupported cmd:%d", + csid_hw->hw_intf->hw_idx, cmd_type); + rc = -EINVAL; + break; + } + + return rc; + +} + +static int cam_csid_get_evt_payload( + struct cam_ife_csid_hw *csid_hw, + struct cam_csid_evt_payload **evt_payload) +{ + + spin_lock(&csid_hw->lock_state); + + if (list_empty(&csid_hw->free_payload_list)) { + *evt_payload = NULL; + spin_unlock(&csid_hw->lock_state); + CAM_ERR_RATE_LIMIT(CAM_ISP, "No free payload core %d", + csid_hw->hw_intf->hw_idx); + return -ENOMEM; + } + + *evt_payload = list_first_entry(&csid_hw->free_payload_list, + struct cam_csid_evt_payload, list); + list_del_init(&(*evt_payload)->list); + spin_unlock(&csid_hw->lock_state); + + return 0; +} + +static int cam_csid_put_evt_payload( + struct cam_ife_csid_hw *csid_hw, + struct cam_csid_evt_payload **evt_payload) +{ + unsigned long flags; + + if (*evt_payload == NULL) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid payload core %d", + csid_hw->hw_intf->hw_idx); + return -EINVAL; + } + spin_lock_irqsave(&csid_hw->lock_state, flags); + list_add_tail(&(*evt_payload)->list, + &csid_hw->free_payload_list); + *evt_payload = NULL; + spin_unlock_irqrestore(&csid_hw->lock_state, flags); + + return 0; +} +static char *cam_csid_status_to_str(uint32_t status) +{ + switch (status) { + case CAM_IFE_CSID_IRQ_REG_TOP: + return "TOP"; + case CAM_IFE_CSID_IRQ_REG_RX: + return "RX"; + case CAM_IFE_CSID_IRQ_REG_IPP: + return "IPP"; + case CAM_IFE_CSID_IRQ_REG_PPP: + return "PPP"; + case CAM_IFE_CSID_IRQ_REG_RDI_0: + return "RDI0"; + case CAM_IFE_CSID_IRQ_REG_RDI_1: + return "RDI1"; + case CAM_IFE_CSID_IRQ_REG_RDI_2: + return "RDI2"; + case CAM_IFE_CSID_IRQ_REG_RDI_3: + return "RDI3"; + case CAM_IFE_CSID_IRQ_REG_UDI_0: + return "UDI0"; + case CAM_IFE_CSID_IRQ_REG_UDI_1: + return "UDI1"; + case CAM_IFE_CSID_IRQ_REG_UDI_2: + return "UDI2"; + default: + return "Invalid IRQ"; + } +} + +static int cam_csid_evt_bottom_half_handler( + void *handler_priv, + void *evt_payload_priv) +{ + struct cam_ife_csid_hw *csid_hw; + struct cam_csid_evt_payload *evt_payload; + int i; + int rc = 0; + struct cam_isp_hw_event_info event_info; + + if (!handler_priv || !evt_payload_priv) { + CAM_ERR(CAM_ISP, + "Invalid Param handler_priv %pK evt_payload_priv %pK", + handler_priv, evt_payload_priv); + return 0; + } + + csid_hw = (struct cam_ife_csid_hw *)handler_priv; + evt_payload = (struct cam_csid_evt_payload *)evt_payload_priv; + + if (!csid_hw->event_cb || !csid_hw->priv) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "hw_idx %d Invalid args %pK %pK", + csid_hw->hw_intf->hw_idx, + csid_hw->event_cb, + csid_hw->priv); + goto end; + } + + if (csid_hw->priv != evt_payload->priv) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "hw_idx %d priv mismatch %pK, %pK", + csid_hw->hw_intf->hw_idx, + csid_hw->priv, + evt_payload->priv); + goto end; + } + + CAM_ERR_RATE_LIMIT(CAM_ISP, "idx %d err %d phy %d cnt %d", + csid_hw->hw_intf->hw_idx, + evt_payload->evt_type, + csid_hw->csi2_rx_cfg.phy_sel, + csid_hw->csi2_cfg_cnt); + + for (i = 0; i < CAM_IFE_CSID_IRQ_REG_MAX; i++) + CAM_ERR_RATE_LIMIT(CAM_ISP, "status %s: %x", + cam_csid_status_to_str(i), + evt_payload->irq_status[i]); + + /* this hunk can be extended to handle more cases + * which we want to offload to bottom half from + * irq handlers + */ + event_info.err_type = evt_payload->evt_type; + event_info.hw_idx = evt_payload->hw_idx; + + switch (evt_payload->evt_type) { + case CAM_ISP_HW_ERROR_CSID_FATAL: + if (csid_hw->fatal_err_detected) + break; + csid_hw->fatal_err_detected = true; + rc = csid_hw->event_cb(NULL, + CAM_ISP_HW_EVENT_ERROR, (void *)&event_info); + break; + + default: + CAM_DBG(CAM_ISP, "CSID[%d] invalid error type %d", + csid_hw->hw_intf->hw_idx, + evt_payload->evt_type); + break; + } +end: + cam_csid_put_evt_payload(csid_hw, &evt_payload); + return 0; +} + +static int cam_csid_handle_hw_err_irq( + struct cam_ife_csid_hw *csid_hw, + int evt_type, + uint32_t *irq_status) +{ + int rc = 0; + int i; + void *bh_cmd = NULL; + struct cam_csid_evt_payload *evt_payload; + + CAM_DBG(CAM_ISP, "CSID[%d] error %d", + csid_hw->hw_intf->hw_idx, evt_type); + + rc = cam_csid_get_evt_payload(csid_hw, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "No free payload core %d", + csid_hw->hw_intf->hw_idx); + return rc; + } + + rc = tasklet_bh_api.get_bh_payload_func(csid_hw->tasklet, &bh_cmd); + if (rc || !bh_cmd) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID[%d] Can not get cmd for tasklet, evt_type %d", + csid_hw->hw_intf->hw_idx, + evt_type); + cam_csid_put_evt_payload(csid_hw, &evt_payload); + return rc; + } + + evt_payload->evt_type = evt_type; + evt_payload->priv = csid_hw->priv; + evt_payload->hw_idx = csid_hw->hw_intf->hw_idx; + + for (i = 0; i < CAM_IFE_CSID_IRQ_REG_MAX; i++) + evt_payload->irq_status[i] = irq_status[i]; + + tasklet_bh_api.bottom_half_enqueue_func(csid_hw->tasklet, + bh_cmd, + csid_hw, + evt_payload, + cam_csid_evt_bottom_half_handler); + + return rc; +} + +irqreturn_t cam_ife_csid_irq(int irq_num, void *data) +{ + struct cam_ife_csid_hw *csid_hw; + struct cam_hw_soc_info *soc_info; + const struct cam_ife_csid_reg_offset *csid_reg; + const struct cam_ife_csid_csi2_rx_reg_offset *csi2_reg; + uint32_t i, val; + uint32_t irq_status[CAM_IFE_CSID_IRQ_REG_MAX] = {0}; + bool fatal_err_detected = false; + uint32_t sof_irq_debug_en = 0; + unsigned long flags; + + csid_hw = (struct cam_ife_csid_hw *)data; + + CAM_DBG(CAM_ISP, "CSID %d IRQ Handling", csid_hw->hw_intf->hw_idx); + + if (!data) { + CAM_ERR(CAM_ISP, "CSID: Invalid arguments"); + return IRQ_HANDLED; + } + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + csi2_reg = csid_reg->csi2_reg; + + /* read */ + irq_status[CAM_IFE_CSID_IRQ_REG_TOP] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_status_addr); + + irq_status[CAM_IFE_CSID_IRQ_REG_RX] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_status_addr); + + if (csid_reg->cmn_reg->num_pix) + irq_status[CAM_IFE_CSID_IRQ_REG_IPP] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_status_addr); + + if (csid_reg->cmn_reg->num_ppp) + irq_status[CAM_IFE_CSID_IRQ_REG_PPP] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_status_addr); + + if (csid_reg->cmn_reg->num_rdis <= CAM_IFE_CSID_RDI_MAX) { + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { + irq_status[i] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_status_addr); + } + } + + if (csid_reg->cmn_reg->num_udis <= CAM_IFE_CSID_UDI_MAX) { + for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) { + irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[i]->csid_udi_irq_status_addr); + } + } + + spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); + /* clear */ + cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_TOP], + soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + + cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_RX], + soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); + if (csid_reg->cmn_reg->num_pix) + cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_IPP], + soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_clear_addr); + + if (csid_reg->cmn_reg->num_ppp) + cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_PPP], + soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_irq_clear_addr); + + if (csid_reg->cmn_reg->num_rdis <= CAM_IFE_CSID_RDI_MAX) { + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { + cam_io_w_mb(irq_status[i], + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr); + } + } + + if (csid_reg->cmn_reg->num_udis <= CAM_IFE_CSID_UDI_MAX) { + for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) { + cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i], + soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[i]->csid_udi_irq_clear_addr); + } + } + + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); + + CAM_DBG(CAM_ISP, "irq_status_top = 0x%x", + irq_status[CAM_IFE_CSID_IRQ_REG_TOP]); + CAM_DBG(CAM_ISP, "irq_status_rx = 0x%x", + irq_status[CAM_IFE_CSID_IRQ_REG_RX]); + CAM_DBG(CAM_ISP, "irq_status_ipp = 0x%x", + irq_status[CAM_IFE_CSID_IRQ_REG_IPP]); + CAM_DBG(CAM_ISP, "irq_status_ppp = 0x%x", + irq_status[CAM_IFE_CSID_IRQ_REG_PPP]); + CAM_DBG(CAM_ISP, + "irq_status_rdi0= 0x%x irq_status_rdi1= 0x%x irq_status_rdi2= 0x%x", + irq_status[0], irq_status[1], irq_status[2]); + CAM_DBG(CAM_ISP, + "irq_status_udi0= 0x%x irq_status_udi1= 0x%x irq_status_udi2= 0x%x", + irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0], + irq_status[CAM_IFE_CSID_IRQ_REG_UDI_1], + irq_status[CAM_IFE_CSID_IRQ_REG_UDI_2]); + + if (irq_status[CAM_IFE_CSID_IRQ_REG_TOP] & CSID_TOP_IRQ_DONE) { + CAM_DBG(CAM_ISP, "csid top reset complete"); + complete(&csid_hw->csid_top_complete); + } + + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + BIT(csid_reg->csi2_reg->csi2_rst_done_shift_val)) { + CAM_DBG(CAM_ISP, "csi rx reset complete"); + complete(&csid_hw->csid_csi2_complete); + } + + spin_lock_irqsave(&csid_hw->lock_state, flags); + if (csid_hw->device_enabled == 1) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 0 over flow", + csid_hw->hw_intf->hw_idx); + fatal_err_detected = true; + goto handle_fatal_error; + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 1 over flow", + csid_hw->hw_intf->hw_idx); + fatal_err_detected = true; + goto handle_fatal_error; + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 2 over flow", + csid_hw->hw_intf->hw_idx); + fatal_err_detected = true; + goto handle_fatal_error; + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 3 over flow", + csid_hw->hw_intf->hw_idx); + fatal_err_detected = true; + goto handle_fatal_error; + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_TG_FIFO_OVERFLOW) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d TG OVER FLOW", + csid_hw->hw_intf->hw_idx); + fatal_err_detected = true; + goto handle_fatal_error; + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d CPHY_EOT_RECEPTION", + csid_hw->hw_intf->hw_idx); + csid_hw->error_irq_count++; + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d CPHY_SOT_RECEPTION", + csid_hw->hw_intf->hw_idx); + csid_hw->error_irq_count++; + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_CPHY_PH_CRC) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_PH_CRC", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_CRC) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_CRC", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_ECC) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_ECC", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_MMAPPED_VC_DT) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d MMAPPED_VC_DT", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d ERROR_STREAM_UNDERFLOW", + csid_hw->hw_intf->hw_idx); + csid_hw->error_irq_count++; + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d UNBOUNDED_FRAME", + csid_hw->hw_intf->hw_idx); + csid_hw->error_irq_count++; + } + } +handle_fatal_error: + spin_unlock_irqrestore(&csid_hw->lock_state, flags); + + if (csid_hw->error_irq_count > + CAM_IFE_CSID_MAX_IRQ_ERROR_COUNT) { + fatal_err_detected = true; + csid_hw->error_irq_count = 0; + } + + if (fatal_err_detected) { + cam_ife_csid_halt_csi2(csid_hw); + cam_csid_handle_hw_err_irq(csid_hw, + CAM_ISP_HW_ERROR_CSID_FATAL, irq_status); + } + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOT_IRQ) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL0_EOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL1_EOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL2_EOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL3_EOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + } + + if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOT_IRQ) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL0_SOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL1_SOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL2_SOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL3_SOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + } + + if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) && + (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED)) { + + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d LONG_PKT_CAPTURED", + csid_hw->hw_intf->hw_idx); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_long_pkt_0_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d long packet VC :%d DT:%d WC:%d", + csid_hw->hw_intf->hw_idx, + (val >> 22), ((val >> 16) & 0x3F), (val & 0xFFFF)); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_long_pkt_1_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d long packet ECC :%d", + csid_hw->hw_intf->hw_idx, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_long_pkt_ftr_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d long pkt cal CRC:%d expected CRC:%d", + csid_hw->hw_intf->hw_idx, (val >> 16), (val & 0xFFFF)); + } + if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) && + (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED)) { + + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d SHORT_PKT_CAPTURED", + csid_hw->hw_intf->hw_idx); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_short_pkt_0_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d short pkt VC :%d DT:%d LC:%d", + csid_hw->hw_intf->hw_idx, + (val >> 22), ((val >> 16) & 0x3F), (val & 0xFFFF)); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_short_pkt_1_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d short packet ECC :%d", + csid_hw->hw_intf->hw_idx, val); + } + + if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) && + (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_PKT_HDR_CAPTURED", + csid_hw->hw_intf->hw_idx); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_cphy_pkt_hdr_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d cphy packet VC :%d DT:%d WC:%d", + csid_hw->hw_intf->hw_idx, + (val >> 22), ((val >> 16) & 0x3F), (val & 0xFFFF)); + } + + /*read the IPP errors */ + if (csid_reg->cmn_reg->num_pix) { + /* IPP reset done bit */ + if (irq_status[CAM_IFE_CSID_IRQ_REG_IPP] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { + CAM_DBG(CAM_ISP, "CSID IPP reset complete"); + complete(&csid_hw->csid_ipp_complete); + } + + if ((irq_status[CAM_IFE_CSID_IRQ_REG_IPP] & + CSID_PATH_INFO_INPUT_SOF) && + (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP SOF received", + csid_hw->hw_intf->hw_idx); + if (csid_hw->sof_irq_triggered) + csid_hw->irq_debug_cnt++; + } + + if ((irq_status[CAM_IFE_CSID_IRQ_REG_IPP] & + CSID_PATH_INFO_INPUT_EOF) && + (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)) + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP EOF received", + csid_hw->hw_intf->hw_idx); + + if ((irq_status[CAM_IFE_CSID_IRQ_REG_IPP] & + CSID_PATH_ERROR_CCIF_VIOLATION)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d IPP CCIF violation", + csid_hw->hw_intf->hw_idx); + + if ((irq_status[CAM_IFE_CSID_IRQ_REG_IPP] & + CSID_PATH_OVERFLOW_RECOVERY)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d IPP Overflow due to back pressure", + csid_hw->hw_intf->hw_idx); + + if (irq_status[CAM_IFE_CSID_IRQ_REG_IPP] & + CSID_PATH_ERROR_FIFO_OVERFLOW) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d IPP fifo over flow", + csid_hw->hw_intf->hw_idx); + /* Stop IPP path immediately */ + cam_io_w_mb(CAM_CSID_HALT_IMMEDIATELY, + soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_ctrl_addr); + } + } + + /*read PPP errors */ + if (csid_reg->cmn_reg->num_ppp) { + /* PPP reset done bit */ + if (irq_status[CAM_IFE_CSID_IRQ_REG_PPP] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { + CAM_DBG(CAM_ISP, "CSID PPP reset complete"); + complete(&csid_hw->csid_ppp_complete); + } + + if ((irq_status[CAM_IFE_CSID_IRQ_REG_PPP] & + CSID_PATH_INFO_INPUT_SOF) && + (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PPP SOF received", + csid_hw->hw_intf->hw_idx); + if (csid_hw->sof_irq_triggered) + csid_hw->irq_debug_cnt++; + } + + if ((irq_status[CAM_IFE_CSID_IRQ_REG_PPP] & + CSID_PATH_INFO_INPUT_EOF) && + (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)) + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PPP EOF received", + csid_hw->hw_intf->hw_idx); + + if ((irq_status[CAM_IFE_CSID_IRQ_REG_PPP] & + CSID_PATH_ERROR_CCIF_VIOLATION)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PPP CCIF violation", + csid_hw->hw_intf->hw_idx); + + if ((irq_status[CAM_IFE_CSID_IRQ_REG_PPP] & + CSID_PATH_OVERFLOW_RECOVERY)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d IPP Overflow due to back pressure", + csid_hw->hw_intf->hw_idx); + + if (irq_status[CAM_IFE_CSID_IRQ_REG_PPP] & + CSID_PATH_ERROR_FIFO_OVERFLOW) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d PPP fifo over flow", + csid_hw->hw_intf->hw_idx); + /* Stop PPP path immediately */ + cam_io_w_mb(CAM_CSID_HALT_IMMEDIATELY, + soc_info->reg_map[0].mem_base + + csid_reg->ppp_reg->csid_pxl_ctrl_addr); + } + } + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { + if (irq_status[i] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { + CAM_DBG(CAM_ISP, "CSID RDI%d reset complete", i); + complete(&csid_hw->csid_rdin_complete[i]); + } + + if ((irq_status[i] & CSID_PATH_INFO_INPUT_SOF) && + (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID RDI:%d SOF received", i); + if (csid_hw->sof_irq_triggered) + csid_hw->irq_debug_cnt++; + } + + if ((irq_status[i] & CSID_PATH_INFO_INPUT_EOF) && + (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID RDI:%d EOF received", i); + + if ((irq_status[i] & CSID_PATH_ERROR_CCIF_VIOLATION)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID RDI :%d CCIF violation", i); + + if ((irq_status[i] & CSID_PATH_OVERFLOW_RECOVERY)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID RDI :%d Overflow due to back pressure", + i); + + if (irq_status[i] & CSID_PATH_ERROR_FIFO_OVERFLOW) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d RDI fifo over flow", + csid_hw->hw_intf->hw_idx); + /* Stop RDI path immediately */ + cam_io_w_mb(CAM_CSID_HALT_IMMEDIATELY, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_ctrl_addr); + } + } + + for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { + CAM_DBG(CAM_ISP, "CSID UDI%d reset complete", i); + complete(&csid_hw->csid_udin_complete[i]); + } + + if ((irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] & + CSID_PATH_INFO_INPUT_SOF) && + (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID UDI:%d SOF received", i); + if (csid_hw->sof_irq_triggered) + csid_hw->irq_debug_cnt++; + } + + if ((irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] & + CSID_PATH_INFO_INPUT_EOF) && + (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID UDI:%d EOF received", i); + + if ((irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] & + CSID_PATH_ERROR_CCIF_VIOLATION)) + CAM_WARN_RATE_LIMIT(CAM_ISP, + "CSID UDI :%d CCIF violation", i); + + if ((irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] & + CSID_PATH_OVERFLOW_RECOVERY)) + CAM_WARN_RATE_LIMIT(CAM_ISP, + "CSID UDI :%d Overflow due to back pressure", + i); + + if (irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] & + CSID_PATH_ERROR_FIFO_OVERFLOW) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d UDI fifo over flow", + csid_hw->hw_intf->hw_idx); + /* Stop UDI path immediately */ + cam_io_w_mb(CAM_CSID_HALT_IMMEDIATELY, + soc_info->reg_map[0].mem_base + + csid_reg->udi_reg[i]->csid_udi_ctrl_addr); + } + } + + if (csid_hw->irq_debug_cnt >= CAM_CSID_IRQ_SOF_DEBUG_CNT_MAX) { + cam_ife_csid_sof_irq_debug(csid_hw, &sof_irq_debug_en); + csid_hw->irq_debug_cnt = 0; + } + + CAM_DBG(CAM_ISP, "IRQ Handling exit"); + return IRQ_HANDLED; +} + +int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, + uint32_t csid_idx, bool is_custom) +{ + int rc = -EINVAL; + uint32_t i; + uint32_t num_paths; + struct cam_ife_csid_path_cfg *path_data; + struct cam_ife_csid_cid_data *cid_data; + struct cam_hw_info *csid_hw_info; + struct cam_ife_csid_hw *ife_csid_hw = NULL; + + if (csid_idx >= CAM_IFE_CSID_HW_NUM_MAX) { + CAM_ERR(CAM_ISP, "Invalid csid index:%d", csid_idx); + return rc; + } + + csid_hw_info = (struct cam_hw_info *) csid_hw_intf->hw_priv; + ife_csid_hw = (struct cam_ife_csid_hw *) csid_hw_info->core_info; + + ife_csid_hw->hw_intf = csid_hw_intf; + ife_csid_hw->hw_info = csid_hw_info; + + CAM_DBG(CAM_ISP, "type %d index %d", + ife_csid_hw->hw_intf->hw_type, csid_idx); + + + ife_csid_hw->device_enabled = 0; + ife_csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; + mutex_init(&ife_csid_hw->hw_info->hw_mutex); + spin_lock_init(&ife_csid_hw->hw_info->hw_lock); + spin_lock_init(&ife_csid_hw->lock_state); + init_completion(&ife_csid_hw->hw_info->hw_complete); + + init_completion(&ife_csid_hw->csid_top_complete); + init_completion(&ife_csid_hw->csid_csi2_complete); + init_completion(&ife_csid_hw->csid_ipp_complete); + init_completion(&ife_csid_hw->csid_ppp_complete); + for (i = 0; i < CAM_IFE_CSID_RDI_MAX; i++) + init_completion(&ife_csid_hw->csid_rdin_complete[i]); + + for (i = 0; i < CAM_IFE_CSID_UDI_MAX; i++) + init_completion(&ife_csid_hw->csid_udin_complete[i]); + + rc = cam_ife_csid_init_soc_resources(&ife_csid_hw->hw_info->soc_info, + cam_ife_csid_irq, ife_csid_hw, is_custom); + if (rc < 0) { + CAM_ERR(CAM_ISP, "CSID:%d Failed to init_soc", csid_idx); + goto err; + } + + if (cam_cpas_is_feature_supported(CAM_CPAS_QCFA_BINNING_ENABLE, + csid_idx) == true) + ife_csid_hw->binning_enable = 1; + + ife_csid_hw->hw_intf->hw_ops.get_hw_caps = cam_ife_csid_get_hw_caps; + ife_csid_hw->hw_intf->hw_ops.init = cam_ife_csid_init_hw; + ife_csid_hw->hw_intf->hw_ops.deinit = cam_ife_csid_deinit_hw; + ife_csid_hw->hw_intf->hw_ops.reset = cam_ife_csid_reset; + ife_csid_hw->hw_intf->hw_ops.reserve = cam_ife_csid_reserve; + ife_csid_hw->hw_intf->hw_ops.release = cam_ife_csid_release; + ife_csid_hw->hw_intf->hw_ops.start = cam_ife_csid_start; + ife_csid_hw->hw_intf->hw_ops.stop = cam_ife_csid_stop; + ife_csid_hw->hw_intf->hw_ops.read = cam_ife_csid_read; + ife_csid_hw->hw_intf->hw_ops.write = cam_ife_csid_write; + ife_csid_hw->hw_intf->hw_ops.process_cmd = cam_ife_csid_process_cmd; + + num_paths = ife_csid_hw->csid_info->csid_reg->cmn_reg->num_pix + + ife_csid_hw->csid_info->csid_reg->cmn_reg->num_rdis + + ife_csid_hw->csid_info->csid_reg->cmn_reg->num_udis; + /* Initialize the CID resource */ + for (i = 0; i < num_paths; i++) { + ife_csid_hw->cid_res[i].res_type = CAM_ISP_RESOURCE_CID; + ife_csid_hw->cid_res[i].res_id = i; + ife_csid_hw->cid_res[i].res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + ife_csid_hw->cid_res[i].hw_intf = ife_csid_hw->hw_intf; + + cid_data = kzalloc(sizeof(struct cam_ife_csid_cid_data), + GFP_KERNEL); + if (!cid_data) { + rc = -ENOMEM; + goto err; + } + ife_csid_hw->cid_res[i].res_priv = cid_data; + } + + /* Initialize the IPP resources */ + if (ife_csid_hw->csid_info->csid_reg->cmn_reg->num_pix) { + ife_csid_hw->ipp_res.res_type = CAM_ISP_RESOURCE_PIX_PATH; + ife_csid_hw->ipp_res.res_id = CAM_IFE_PIX_PATH_RES_IPP; + ife_csid_hw->ipp_res.res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + ife_csid_hw->ipp_res.hw_intf = ife_csid_hw->hw_intf; + path_data = kzalloc(sizeof(*path_data), + GFP_KERNEL); + if (!path_data) { + rc = -ENOMEM; + goto err; + } + ife_csid_hw->ipp_res.res_priv = path_data; + } + + /* Initialize PPP resource */ + if (ife_csid_hw->csid_info->csid_reg->cmn_reg->num_ppp) { + ife_csid_hw->ppp_res.res_type = CAM_ISP_RESOURCE_PIX_PATH; + ife_csid_hw->ppp_res.res_id = CAM_IFE_PIX_PATH_RES_PPP; + ife_csid_hw->ppp_res.res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + ife_csid_hw->ppp_res.hw_intf = ife_csid_hw->hw_intf; + path_data = kzalloc(sizeof(*path_data), + GFP_KERNEL); + if (!path_data) { + rc = -ENOMEM; + goto err; + } + ife_csid_hw->ppp_res.res_priv = path_data; + } + + /* Initialize the RDI resource */ + for (i = 0; i < ife_csid_hw->csid_info->csid_reg->cmn_reg->num_rdis; + i++) { + /* res type is from RDI 0 to RDI3 */ + ife_csid_hw->rdi_res[i].res_type = + CAM_ISP_RESOURCE_PIX_PATH; + ife_csid_hw->rdi_res[i].res_id = i; + ife_csid_hw->rdi_res[i].res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + ife_csid_hw->rdi_res[i].hw_intf = ife_csid_hw->hw_intf; + + path_data = kzalloc(sizeof(*path_data), + GFP_KERNEL); + if (!path_data) { + rc = -ENOMEM; + goto err; + } + ife_csid_hw->rdi_res[i].res_priv = path_data; + } + + /* Initialize the UDI resource */ + for (i = 0; i < ife_csid_hw->csid_info->csid_reg->cmn_reg->num_udis; + i++) { + /* res type is from UDI0 to UDI3 */ + ife_csid_hw->udi_res[i].res_type = + CAM_ISP_RESOURCE_PIX_PATH; + ife_csid_hw->udi_res[i].res_id = i + + CAM_IFE_PIX_PATH_RES_UDI_0; + ife_csid_hw->udi_res[i].res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + ife_csid_hw->udi_res[i].hw_intf = ife_csid_hw->hw_intf; + + path_data = kzalloc(sizeof(*path_data), + GFP_KERNEL); + if (!path_data) { + rc = -ENOMEM; + goto err; + } + ife_csid_hw->udi_res[i].res_priv = path_data; + } + + rc = cam_tasklet_init(&ife_csid_hw->tasklet, ife_csid_hw, csid_idx); + if (rc) { + CAM_ERR(CAM_ISP, "Unable to create CSID tasklet rc %d", rc); + goto err; + } + + INIT_LIST_HEAD(&ife_csid_hw->free_payload_list); + for (i = 0; i < CAM_CSID_EVT_PAYLOAD_MAX; i++) { + INIT_LIST_HEAD(&ife_csid_hw->evt_payload[i].list); + list_add_tail(&ife_csid_hw->evt_payload[i].list, + &ife_csid_hw->free_payload_list); + } + + ife_csid_hw->csid_debug = 0; + ife_csid_hw->error_irq_count = 0; + + return 0; +err: + if (rc) { + kfree(ife_csid_hw->ipp_res.res_priv); + kfree(ife_csid_hw->ppp_res.res_priv); + for (i = 0; i < + ife_csid_hw->csid_info->csid_reg->cmn_reg->num_rdis; + i++) + kfree(ife_csid_hw->rdi_res[i].res_priv); + + for (i = 0; i < + ife_csid_hw->csid_info->csid_reg->cmn_reg->num_udis; + i++) + kfree(ife_csid_hw->udi_res[i].res_priv); + + for (i = 0; i < CAM_IFE_CSID_CID_MAX; i++) + kfree(ife_csid_hw->cid_res[i].res_priv); + + } + + return rc; +} +EXPORT_SYMBOL(cam_ife_csid_hw_probe_init); + +int cam_ife_csid_hw_deinit(struct cam_ife_csid_hw *ife_csid_hw) +{ + int rc = -EINVAL; + uint32_t i; + + if (!ife_csid_hw) { + CAM_ERR(CAM_ISP, "Invalid param"); + return rc; + } + + /* release the privdate data memory from resources */ + kfree(ife_csid_hw->ipp_res.res_priv); + kfree(ife_csid_hw->ppp_res.res_priv); + for (i = 0; i < + ife_csid_hw->csid_info->csid_reg->cmn_reg->num_rdis; + i++) { + kfree(ife_csid_hw->rdi_res[i].res_priv); + } + for (i = 0; i < + ife_csid_hw->csid_info->csid_reg->cmn_reg->num_udis; + i++) { + kfree(ife_csid_hw->udi_res[i].res_priv); + } + for (i = 0; i < CAM_IFE_CSID_CID_MAX; i++) + kfree(ife_csid_hw->cid_res[i].res_priv); + + cam_ife_csid_deinit_soc_resources(&ife_csid_hw->hw_info->soc_info); + + return 0; +} +EXPORT_SYMBOL(cam_ife_csid_hw_deinit); diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h new file mode 100644 index 0000000000000000000000000000000000000000..a65783c29d184e53a3b7900279ad3ec3b2d0d2e6 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h @@ -0,0 +1,650 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_IFE_CSID_HW_H_ +#define _CAM_IFE_CSID_HW_H_ + +#include "cam_hw.h" +#include "cam_ife_csid_hw_intf.h" +#include "cam_ife_csid_soc.h" +#include "cam_ife_csid_core.h" + +#define CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED BIT(0) +#define CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED BIT(1) +#define CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED BIT(2) +#define CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED BIT(3) +#define CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED BIT(4) +#define CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED BIT(5) +#define CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED BIT(6) +#define CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED BIT(7) +#define CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED BIT(8) +#define CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED BIT(9) +#define CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED BIT(10) +#define CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION BIT(11) +#define CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION BIT(12) +#define CSID_CSI2_RX_ERROR_CPHY_PH_CRC BIT(13) +#define CSID_CSI2_RX_WARNING_ECC BIT(14) +#define CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW BIT(15) +#define CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW BIT(16) +#define CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW BIT(17) +#define CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW BIT(18) +#define CSID_CSI2_RX_ERROR_CRC BIT(19) +#define CSID_CSI2_RX_ERROR_ECC BIT(20) +#define CSID_CSI2_RX_ERROR_MMAPPED_VC_DT BIT(21) +#define CSID_CSI2_RX_ERROR_UNMAPPED_VC_DT BIT(22) +#define CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW BIT(23) +#define CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME BIT(24) +#define CSID_CSI2_RX_INFO_TG_DONE BIT(25) +#define CSID_CSI2_RX_ERROR_TG_FIFO_OVERFLOW BIT(26) +#define CSID_CSI2_RX_INFO_RST_DONE BIT(27) + +#define CSID_TOP_IRQ_DONE BIT(0) +#define CSID_PATH_INFO_RST_DONE BIT(1) +#define CSID_PATH_ERROR_FIFO_OVERFLOW BIT(2) +#define CSID_PATH_INFO_SUBSAMPLED_EOF BIT(3) +#define CSID_PATH_INFO_SUBSAMPLED_SOF BIT(4) +#define CSID_PATH_INFO_FRAME_DROP_EOF BIT(5) +#define CSID_PATH_INFO_FRAME_DROP_EOL BIT(6) +#define CSID_PATH_INFO_FRAME_DROP_SOL BIT(7) +#define CSID_PATH_INFO_FRAME_DROP_SOF BIT(8) +#define CSID_PATH_INFO_INPUT_EOF BIT(9) +#define CSID_PATH_INFO_INPUT_EOL BIT(10) +#define CSID_PATH_INFO_INPUT_SOL BIT(11) +#define CSID_PATH_INFO_INPUT_SOF BIT(12) +#define CSID_PATH_ERROR_PIX_COUNT BIT(13) +#define CSID_PATH_ERROR_LINE_COUNT BIT(14) +#define CSID_PATH_ERROR_CCIF_VIOLATION BIT(15) +#define CSID_PATH_OVERFLOW_RECOVERY BIT(17) + +/* + * Debug values enable the corresponding interrupts and debug logs provide + * necessary information + */ +#define CSID_DEBUG_ENABLE_SOF_IRQ BIT(0) +#define CSID_DEBUG_ENABLE_EOF_IRQ BIT(1) +#define CSID_DEBUG_ENABLE_SOT_IRQ BIT(2) +#define CSID_DEBUG_ENABLE_EOT_IRQ BIT(3) +#define CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE BIT(4) +#define CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE BIT(5) +#define CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE BIT(6) +#define CSID_DEBUG_ENABLE_HBI_VBI_INFO BIT(7) +#define CSID_DEBUG_DISABLE_EARLY_EOF BIT(8) + +#define CAM_CSID_EVT_PAYLOAD_MAX 10 + +/* enum cam_csid_path_halt_mode select the path halt mode control */ +enum cam_csid_path_halt_mode { + CSID_HALT_MODE_INTERNAL, + CSID_HALT_MODE_GLOBAL, + CSID_HALT_MODE_MASTER, + CSID_HALT_MODE_SLAVE, +}; + +/** + *enum cam_csid_path_timestamp_stb_sel - select the sof/eof strobes used to + * capture the timestamp + */ +enum cam_csid_path_timestamp_stb_sel { + CSID_TIMESTAMP_STB_PRE_HALT, + CSID_TIMESTAMP_STB_POST_HALT, + CSID_TIMESTAMP_STB_POST_IRQ, + CSID_TIMESTAMP_STB_MAX, +}; + +/** + * enum cam_ife_pix_path_res_id - Specify the csid patch + */ +enum cam_ife_csid_irq_reg { + CAM_IFE_CSID_IRQ_REG_RDI_0, + CAM_IFE_CSID_IRQ_REG_RDI_1, + CAM_IFE_CSID_IRQ_REG_RDI_2, + CAM_IFE_CSID_IRQ_REG_RDI_3, + CAM_IFE_CSID_IRQ_REG_TOP, + CAM_IFE_CSID_IRQ_REG_RX, + CAM_IFE_CSID_IRQ_REG_IPP, + CAM_IFE_CSID_IRQ_REG_PPP, + CAM_IFE_CSID_IRQ_REG_UDI_0, + CAM_IFE_CSID_IRQ_REG_UDI_1, + CAM_IFE_CSID_IRQ_REG_UDI_2, + CAM_IFE_CSID_IRQ_REG_MAX, +}; + +struct cam_ife_csid_pxl_reg_offset { + /* Pxl path register offsets*/ + uint32_t csid_pxl_irq_status_addr; + uint32_t csid_pxl_irq_mask_addr; + uint32_t csid_pxl_irq_clear_addr; + uint32_t csid_pxl_irq_set_addr; + + uint32_t csid_pxl_cfg0_addr; + uint32_t csid_pxl_cfg1_addr; + uint32_t csid_pxl_ctrl_addr; + uint32_t csid_pxl_frm_drop_pattern_addr; + uint32_t csid_pxl_frm_drop_period_addr; + uint32_t csid_pxl_irq_subsample_pattern_addr; + uint32_t csid_pxl_irq_subsample_period_addr; + uint32_t csid_pxl_hcrop_addr; + uint32_t csid_pxl_vcrop_addr; + uint32_t csid_pxl_pix_drop_pattern_addr; + uint32_t csid_pxl_pix_drop_period_addr; + uint32_t csid_pxl_line_drop_pattern_addr; + uint32_t csid_pxl_line_drop_period_addr; + uint32_t csid_pxl_rst_strobes_addr; + uint32_t csid_pxl_status_addr; + uint32_t csid_pxl_misr_val_addr; + uint32_t csid_pxl_format_measure_cfg0_addr; + uint32_t csid_pxl_format_measure_cfg1_addr; + uint32_t csid_pxl_format_measure0_addr; + uint32_t csid_pxl_format_measure1_addr; + uint32_t csid_pxl_format_measure2_addr; + uint32_t csid_pxl_timestamp_curr0_sof_addr; + uint32_t csid_pxl_timestamp_curr1_sof_addr; + uint32_t csid_pxl_timestamp_perv0_sof_addr; + uint32_t csid_pxl_timestamp_perv1_sof_addr; + uint32_t csid_pxl_timestamp_curr0_eof_addr; + uint32_t csid_pxl_timestamp_curr1_eof_addr; + uint32_t csid_pxl_timestamp_perv0_eof_addr; + uint32_t csid_pxl_timestamp_perv1_eof_addr; + uint32_t csid_pxl_err_recovery_cfg0_addr; + uint32_t csid_pxl_err_recovery_cfg1_addr; + uint32_t csid_pxl_err_recovery_cfg2_addr; + uint32_t csid_pxl_multi_vcdt_cfg0_addr; + + /* configuration */ + uint32_t pix_store_en_shift_val; + uint32_t early_eof_en_shift_val; + uint32_t horizontal_bin_en_shift_val; + uint32_t quad_cfa_bin_en_shift_val; + uint32_t ccif_violation_en; + uint32_t overflow_ctrl_en; +}; + +struct cam_ife_csid_rdi_reg_offset { + uint32_t csid_rdi_irq_status_addr; + uint32_t csid_rdi_irq_mask_addr; + uint32_t csid_rdi_irq_clear_addr; + uint32_t csid_rdi_irq_set_addr; + + /*RDI N register address */ + uint32_t csid_rdi_cfg0_addr; + uint32_t csid_rdi_cfg1_addr; + uint32_t csid_rdi_ctrl_addr; + uint32_t csid_rdi_frm_drop_pattern_addr; + uint32_t csid_rdi_frm_drop_period_addr; + uint32_t csid_rdi_irq_subsample_pattern_addr; + uint32_t csid_rdi_irq_subsample_period_addr; + uint32_t csid_rdi_rpp_hcrop_addr; + uint32_t csid_rdi_rpp_vcrop_addr; + uint32_t csid_rdi_rpp_pix_drop_pattern_addr; + uint32_t csid_rdi_rpp_pix_drop_period_addr; + uint32_t csid_rdi_rpp_line_drop_pattern_addr; + uint32_t csid_rdi_rpp_line_drop_period_addr; + uint32_t csid_rdi_yuv_chroma_conversion_addr; + uint32_t csid_rdi_rst_strobes_addr; + uint32_t csid_rdi_status_addr; + uint32_t csid_rdi_misr_val0_addr; + uint32_t csid_rdi_misr_val1_addr; + uint32_t csid_rdi_misr_val2_addr; + uint32_t csid_rdi_misr_val3_addr; + uint32_t csid_rdi_format_measure_cfg0_addr; + uint32_t csid_rdi_format_measure_cfg1_addr; + uint32_t csid_rdi_format_measure0_addr; + uint32_t csid_rdi_format_measure1_addr; + uint32_t csid_rdi_format_measure2_addr; + uint32_t csid_rdi_timestamp_curr0_sof_addr; + uint32_t csid_rdi_timestamp_curr1_sof_addr; + uint32_t csid_rdi_timestamp_prev0_sof_addr; + uint32_t csid_rdi_timestamp_prev1_sof_addr; + uint32_t csid_rdi_timestamp_curr0_eof_addr; + uint32_t csid_rdi_timestamp_curr1_eof_addr; + uint32_t csid_rdi_timestamp_prev0_eof_addr; + uint32_t csid_rdi_timestamp_prev1_eof_addr; + uint32_t csid_rdi_err_recovery_cfg0_addr; + uint32_t csid_rdi_err_recovery_cfg1_addr; + uint32_t csid_rdi_err_recovery_cfg2_addr; + uint32_t csid_rdi_multi_vcdt_cfg0_addr; + uint32_t csid_rdi_byte_cntr_ping_addr; + uint32_t csid_rdi_byte_cntr_pong_addr; + + /* configuration */ + uint32_t packing_format; + uint32_t ccif_violation_en; + uint32_t overflow_ctrl_en; +}; + +struct cam_ife_csid_udi_reg_offset { + uint32_t csid_udi_irq_status_addr; + uint32_t csid_udi_irq_mask_addr; + uint32_t csid_udi_irq_clear_addr; + uint32_t csid_udi_irq_set_addr; + + /* UDI N register address */ + uint32_t csid_udi_cfg0_addr; + uint32_t csid_udi_cfg1_addr; + uint32_t csid_udi_ctrl_addr; + uint32_t csid_udi_frm_drop_pattern_addr; + uint32_t csid_udi_frm_drop_period_addr; + uint32_t csid_udi_irq_subsample_pattern_addr; + uint32_t csid_udi_irq_subsample_period_addr; + uint32_t csid_udi_rpp_hcrop_addr; + uint32_t csid_udi_rpp_vcrop_addr; + uint32_t csid_udi_rpp_pix_drop_pattern_addr; + uint32_t csid_udi_rpp_pix_drop_period_addr; + uint32_t csid_udi_rpp_line_drop_pattern_addr; + uint32_t csid_udi_rpp_line_drop_period_addr; + uint32_t csid_udi_yuv_chroma_conversion_addr; + uint32_t csid_udi_rst_strobes_addr; + uint32_t csid_udi_status_addr; + uint32_t csid_udi_misr_val0_addr; + uint32_t csid_udi_misr_val1_addr; + uint32_t csid_udi_misr_val2_addr; + uint32_t csid_udi_misr_val3_addr; + uint32_t csid_udi_format_measure_cfg0_addr; + uint32_t csid_udi_format_measure_cfg1_addr; + uint32_t csid_udi_format_measure0_addr; + uint32_t csid_udi_format_measure1_addr; + uint32_t csid_udi_format_measure2_addr; + uint32_t csid_udi_timestamp_curr0_sof_addr; + uint32_t csid_udi_timestamp_curr1_sof_addr; + uint32_t csid_udi_timestamp_prev0_sof_addr; + uint32_t csid_udi_timestamp_prev1_sof_addr; + uint32_t csid_udi_timestamp_curr0_eof_addr; + uint32_t csid_udi_timestamp_curr1_eof_addr; + uint32_t csid_udi_timestamp_prev0_eof_addr; + uint32_t csid_udi_timestamp_prev1_eof_addr; + uint32_t csid_udi_err_recovery_cfg0_addr; + uint32_t csid_udi_err_recovery_cfg1_addr; + uint32_t csid_udi_err_recovery_cfg2_addr; + uint32_t csid_udi_multi_vcdt_cfg0_addr; + uint32_t csid_udi_byte_cntr_ping_addr; + uint32_t csid_udi_byte_cntr_pong_addr; + + /* configuration */ + uint32_t packing_format; + uint32_t ccif_violation_en; + uint32_t overflow_ctrl_en; +}; + +struct cam_ife_csid_csi2_rx_reg_offset { + uint32_t csid_csi2_rx_irq_status_addr; + uint32_t csid_csi2_rx_irq_mask_addr; + uint32_t csid_csi2_rx_irq_clear_addr; + uint32_t csid_csi2_rx_irq_set_addr; + uint32_t csid_csi2_rx_cfg0_addr; + uint32_t csid_csi2_rx_cfg1_addr; + uint32_t csid_csi2_rx_capture_ctrl_addr; + uint32_t csid_csi2_rx_rst_strobes_addr; + uint32_t csid_csi2_rx_de_scramble_cfg0_addr; + uint32_t csid_csi2_rx_de_scramble_cfg1_addr; + uint32_t csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr; + uint32_t csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr; + uint32_t csid_csi2_rx_captured_short_pkt_0_addr; + uint32_t csid_csi2_rx_captured_short_pkt_1_addr; + uint32_t csid_csi2_rx_captured_long_pkt_0_addr; + uint32_t csid_csi2_rx_captured_long_pkt_1_addr; + uint32_t csid_csi2_rx_captured_long_pkt_ftr_addr; + uint32_t csid_csi2_rx_captured_cphy_pkt_hdr_addr; + uint32_t csid_csi2_rx_lane0_misr_addr; + uint32_t csid_csi2_rx_lane1_misr_addr; + uint32_t csid_csi2_rx_lane2_misr_addr; + uint32_t csid_csi2_rx_lane3_misr_addr; + uint32_t csid_csi2_rx_total_pkts_rcvd_addr; + uint32_t csid_csi2_rx_stats_ecc_addr; + uint32_t csid_csi2_rx_total_crc_err_addr; + uint32_t csid_csi2_rx_de_scramble_type3_cfg0_addr; + uint32_t csid_csi2_rx_de_scramble_type3_cfg1_addr; + uint32_t csid_csi2_rx_de_scramble_type2_cfg0_addr; + uint32_t csid_csi2_rx_de_scramble_type2_cfg1_addr; + uint32_t csid_csi2_rx_de_scramble_type1_cfg0_addr; + uint32_t csid_csi2_rx_de_scramble_type1_cfg1_addr; + uint32_t csid_csi2_rx_de_scramble_type0_cfg0_addr; + uint32_t csid_csi2_rx_de_scramble_type0_cfg1_addr; + + /*configurations */ + uint32_t csi2_rst_srb_all; + uint32_t csi2_rst_done_shift_val; + uint32_t csi2_irq_mask_all; + uint32_t csi2_misr_enable_shift_val; + uint32_t csi2_vc_mode_shift_val; + uint32_t csi2_capture_long_pkt_en_shift; + uint32_t csi2_capture_short_pkt_en_shift; + uint32_t csi2_capture_cphy_pkt_en_shift; + uint32_t csi2_capture_long_pkt_dt_shift; + uint32_t csi2_capture_long_pkt_vc_shift; + uint32_t csi2_capture_short_pkt_vc_shift; + uint32_t csi2_capture_cphy_pkt_dt_shift; + uint32_t csi2_capture_cphy_pkt_vc_shift; + uint32_t csi2_rx_phy_num_mask; +}; + +struct cam_ife_csid_csi2_tpg_reg_offset { + uint32_t csid_tpg_ctrl_addr; + uint32_t csid_tpg_vc_cfg0_addr; + uint32_t csid_tpg_vc_cfg1_addr; + uint32_t csid_tpg_lfsr_seed_addr; + uint32_t csid_tpg_dt_n_cfg_0_addr; + uint32_t csid_tpg_dt_n_cfg_1_addr; + uint32_t csid_tpg_dt_n_cfg_2_addr; + uint32_t csid_tpg_color_bars_cfg_addr; + uint32_t csid_tpg_color_box_cfg_addr; + uint32_t csid_tpg_common_gen_cfg_addr; + uint32_t csid_tpg_cgen_n_cfg_addr; + uint32_t csid_tpg_cgen_n_x0_addr; + uint32_t csid_tpg_cgen_n_x1_addr; + uint32_t csid_tpg_cgen_n_x2_addr; + uint32_t csid_tpg_cgen_n_xy_addr; + uint32_t csid_tpg_cgen_n_y1_addr; + uint32_t csid_tpg_cgen_n_y2_addr; + + /*configurations */ + uint32_t tpg_dtn_cfg_offset; + uint32_t tpg_cgen_cfg_offset; + uint32_t tpg_cpas_ife_reg_offset; + +}; +struct cam_ife_csid_common_reg_offset { + /* MIPI CSID registers */ + uint32_t csid_hw_version_addr; + uint32_t csid_cfg0_addr; + uint32_t csid_ctrl_addr; + uint32_t csid_reset_addr; + uint32_t csid_rst_strobes_addr; + + uint32_t csid_test_bus_ctrl_addr; + uint32_t csid_top_irq_status_addr; + uint32_t csid_top_irq_mask_addr; + uint32_t csid_top_irq_clear_addr; + uint32_t csid_top_irq_set_addr; + uint32_t csid_irq_cmd_addr; + + /*configurations */ + uint32_t major_version; + uint32_t minor_version; + uint32_t version_incr; + uint32_t num_udis; + uint32_t num_rdis; + uint32_t num_pix; + uint32_t num_ppp; + uint32_t csid_reg_rst_stb; + uint32_t csid_rst_stb; + uint32_t csid_rst_stb_sw_all; + uint32_t path_rst_stb_all; + uint32_t path_rst_done_shift_val; + uint32_t path_en_shift_val; + uint32_t packing_fmt_shift_val; + uint32_t dt_id_shift_val; + uint32_t vc_shift_val; + uint32_t dt_shift_val; + uint32_t fmt_shift_val; + uint32_t plain_fmt_shit_val; + uint32_t crop_v_en_shift_val; + uint32_t crop_h_en_shift_val; + uint32_t drop_v_en_shift_val; + uint32_t drop_h_en_shift_val; + uint32_t crop_shift; + uint32_t ipp_irq_mask_all; + uint32_t rdi_irq_mask_all; + uint32_t ppp_irq_mask_all; + uint32_t udi_irq_mask_all; + uint32_t measure_en_hbi_vbi_cnt_mask; + uint32_t format_measure_en_val; + uint32_t num_bytes_out_shift_val; +}; + +/** + * struct cam_ife_csid_reg_offset- CSID instance register info + * + * @cmn_reg: csid common registers info + * @ipp_reg: ipp register offset information + * @ppp_reg: ppp register offset information + * @rdi_reg: rdi register offset information + * @udi_reg: udi register offset information + * @tpg_reg: tpg register offset information + * + */ +struct cam_ife_csid_reg_offset { + const struct cam_ife_csid_common_reg_offset *cmn_reg; + const struct cam_ife_csid_csi2_rx_reg_offset *csi2_reg; + const struct cam_ife_csid_pxl_reg_offset *ipp_reg; + const struct cam_ife_csid_pxl_reg_offset *ppp_reg; + const struct cam_ife_csid_rdi_reg_offset *rdi_reg[CAM_IFE_CSID_RDI_MAX]; + const struct cam_ife_csid_udi_reg_offset *udi_reg[CAM_IFE_CSID_UDI_MAX]; + const struct cam_ife_csid_csi2_tpg_reg_offset *tpg_reg; +}; + + +/** + * struct cam_ife_csid_hw_info- CSID HW info + * + * @csid_reg: csid register offsets + * @hw_dts_version: HW DTS version + * @csid_max_clk: maximim csid clock + * + */ +struct cam_ife_csid_hw_info { + const struct cam_ife_csid_reg_offset *csid_reg; + uint32_t hw_dts_version; + uint32_t csid_max_clk; + +}; + + + +/** + * struct cam_ife_csid_csi2_rx_cfg- csid csi2 rx configuration data + * @phy_sel: input resource type for sensor only + * @lane_type: lane type: c-phy or d-phy + * @lane_num : active lane number + * @lane_cfg: lane configurations: 4 bits per lane + * + */ +struct cam_ife_csid_csi2_rx_cfg { + uint32_t phy_sel; + uint32_t lane_type; + uint32_t lane_num; + uint32_t lane_cfg; +}; + +/** + * struct cam_ife_csid_tpg_cfg- csid tpg configuration data + * @width: width + * @height: height + * @test_pattern : pattern + * @in_format: decode format + * @usage_type: whether dual isp is required + * + */ +struct cam_ife_csid_tpg_cfg { + uint32_t width; + uint32_t height; + uint32_t test_pattern; + uint32_t in_format; + uint32_t usage_type; +}; + +/** + * struct cam_ife_csid_cid_data- cid configuration private data + * + * @vc: Virtual channel + * @dt: Data type + * @cnt: Cid resource reference count. + * @tpg_set: Tpg used for this cid resource + * @is_valid_vc1_dt1: Valid vc1 and dt1 + * + */ +struct cam_ife_csid_cid_data { + uint32_t vc; + uint32_t dt; + uint32_t vc1; + uint32_t dt1; + uint32_t cnt; + uint32_t tpg_set; + uint32_t is_valid_vc1_dt1; +}; + + +/** + * struct cam_ife_csid_path_cfg- csid path configuration details. It is stored + * as private data for IPP/ RDI paths + * @vc : Virtual channel number + * @dt : Data type number + * @cid cid number, it is same as DT_ID number in HW + * @in_format: input decode format + * @out_format: output format + * @crop_enable: crop is enable or disabled, if enabled + * then remaining parameters are valid. + * @drop_enable: flag to indicate pixel drop enable or disable + * @start_pixel: start pixel + * @end_pixel: end_pixel + * @width: width + * @start_line: start line + * @end_line: end_line + * @height: heigth + * @sync_mode: Applicable for IPP/RDI path reservation + * Reserving the path for master IPP or slave IPP + * master (set value 1), Slave ( set value 2) + * for RDI, set mode to none + * @master_idx: For Slave reservation, Give master IFE instance Index. + * Slave will synchronize with master Start and stop operations + * @clk_rate Clock rate + * @num_bytes_out: Number of output bytes per cycle + * + */ +struct cam_ife_csid_path_cfg { + uint32_t vc; + uint32_t dt; + uint32_t vc1; + uint32_t dt1; + uint32_t is_valid_vc1_dt1; + uint32_t cid; + uint32_t in_format; + uint32_t out_format; + bool crop_enable; + bool drop_enable; + uint32_t start_pixel; + uint32_t end_pixel; + uint32_t width; + uint32_t start_line; + uint32_t end_line; + uint32_t height; + enum cam_isp_hw_sync_mode sync_mode; + uint32_t master_idx; + uint64_t clk_rate; + uint32_t horizontal_bin; + uint32_t qcfa_bin; + uint32_t num_bytes_out; +}; + +/** + * struct cam_csid_evt_payload- payload for csid hw event + * @list : list head + * @evt_type : Event type from CSID + * @irq_status : IRQ Status register + * @hw_idx : Hw index + * @priv : Private data of payload + */ +struct cam_csid_evt_payload { + struct list_head list; + uint32_t evt_type; + uint32_t irq_status[CAM_IFE_CSID_IRQ_REG_MAX]; + uint32_t hw_idx; + void *priv; +}; + +/** + * struct cam_ife_csid_hw- csid hw device resources data + * + * @hw_intf: contain the csid hw interface information + * @hw_info: csid hw device information + * @csid_info: csid hw specific information + * @tasklet: tasklet to handle csid errors + * @priv: private data to be sent with callback + * @free_payload_list: list head for payload + * @evt_payload: Event payload to be passed to tasklet + * @res_type: CSID in resource type + * @csi2_rx_cfg: Csi2 rx decoder configuration for csid + * @tpg_cfg: TPG configuration + * @csi2_rx_reserve_cnt: CSI2 reservations count value + * @csi2_cfg_cnt: csi2 configuration count + * @tpg_start_cnt: tpg start count + * @ipp_res: image pixel path resource + * @ppp_res: phase pxl path resource + * @rdi_res: raw dump image path resources + * @udi_res: udi path resources + * @cid_res: cid resources state + * @csid_top_reset_complete: csid top reset completion + * @csid_csi2_reset_complete: csi2 reset completion + * @csid_ipp_reset_complete: ipp reset completion + * @csid_ppp_complete: ppp reset completion + * @csid_rdin_reset_complete: rdi n completion + * @csid_udin_reset_complete: udi n completion + * @csid_debug: csid debug information to enable the SOT, EOT, + * SOF, EOF, measure etc in the csid hw + * @clk_rate Clock rate + * @sof_irq_triggered: Flag is set on receiving event to enable sof irq + * incase of SOF freeze. + * @irq_debug_cnt: Counter to track sof irq's when above flag is set. + * @error_irq_count Error IRQ count, if continuous error irq comes + * need to stop the CSID and mask interrupts. + * @binning_enable Flag is set if hardware supports QCFA binning + * @binning_supported Flag is set if sensor supports QCFA binning + * + * @prev_boot_timestamp first bootime stamp at the start + * @prev_qtimer_ts stores csid timestamp + * @fatal_err_detected flag to indicate fatal errror is reported + * @event_cb Callback to hw manager if CSID event reported + */ +struct cam_ife_csid_hw { + struct cam_hw_intf *hw_intf; + struct cam_hw_info *hw_info; + struct cam_ife_csid_hw_info *csid_info; + void *tasklet; + void *priv; + struct list_head free_payload_list; + struct cam_csid_evt_payload evt_payload[CAM_CSID_EVT_PAYLOAD_MAX]; + uint32_t res_type; + struct cam_ife_csid_csi2_rx_cfg csi2_rx_cfg; + struct cam_ife_csid_tpg_cfg tpg_cfg; + uint32_t csi2_reserve_cnt; + uint32_t csi2_cfg_cnt; + uint32_t tpg_start_cnt; + struct cam_isp_resource_node ipp_res; + struct cam_isp_resource_node ppp_res; + struct cam_isp_resource_node rdi_res[CAM_IFE_CSID_RDI_MAX]; + struct cam_isp_resource_node udi_res[CAM_IFE_CSID_UDI_MAX]; + struct cam_isp_resource_node cid_res[CAM_IFE_CSID_CID_MAX]; + struct completion csid_top_complete; + struct completion csid_csi2_complete; + struct completion csid_ipp_complete; + struct completion csid_ppp_complete; + struct completion csid_rdin_complete[CAM_IFE_CSID_RDI_MAX]; + struct completion csid_udin_complete[CAM_IFE_CSID_UDI_MAX]; + uint64_t csid_debug; + uint64_t clk_rate; + bool sof_irq_triggered; + uint32_t irq_debug_cnt; + uint32_t error_irq_count; + uint32_t device_enabled; + spinlock_t lock_state; + uint32_t binning_enable; + uint32_t binning_supported; + uint64_t prev_boot_timestamp; + uint64_t prev_qtimer_ts; + bool fatal_err_detected; + cam_hw_mgr_event_cb_func event_cb; +}; + +int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, + uint32_t csid_idx, bool is_custom); + +int cam_ife_csid_hw_deinit(struct cam_ife_csid_hw *ife_csid_hw); + +int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw, + struct cam_csid_hw_reserve_resource_args *cid_reserv); + +int cam_ife_csid_path_reserve(struct cam_ife_csid_hw *csid_hw, + struct cam_csid_hw_reserve_resource_args *reserve); + +#endif /* _CAM_IFE_CSID_HW_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..eca0e43a9b5e19dd5b9ad4c8639dff467c5fa5bb --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include "cam_ife_csid_core.h" +#include "cam_ife_csid_dev.h" +#include "cam_ife_csid_hw_intf.h" +#include "cam_debug_util.h" + +static struct cam_hw_intf *cam_ife_csid_hw_list[CAM_IFE_CSID_HW_NUM_MAX] = { + 0, 0, 0, 0}; + +static char csid_dev_name[8]; + +int cam_ife_csid_probe(struct platform_device *pdev) +{ + + struct cam_hw_intf *csid_hw_intf; + struct cam_hw_info *csid_hw_info; + struct cam_ife_csid_hw *csid_dev = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_ife_csid_hw_info *csid_hw_data = NULL; + uint32_t csid_dev_idx; + int rc = 0; + + CAM_DBG(CAM_ISP, "probe called"); + + csid_hw_intf = kzalloc(sizeof(*csid_hw_intf), GFP_KERNEL); + if (!csid_hw_intf) { + rc = -ENOMEM; + goto err; + } + + csid_hw_info = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!csid_hw_info) { + rc = -ENOMEM; + goto free_hw_intf; + } + + csid_dev = kzalloc(sizeof(struct cam_ife_csid_hw), GFP_KERNEL); + if (!csid_dev) { + rc = -ENOMEM; + goto free_hw_info; + } + + /* get ife csid hw index */ + of_property_read_u32(pdev->dev.of_node, "cell-index", &csid_dev_idx); + /* get ife csid hw information */ + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_ISP, "No matching table for the IFE CSID HW!"); + rc = -EINVAL; + goto free_dev; + } + + memset(csid_dev_name, 0, sizeof(csid_dev_name)); + snprintf(csid_dev_name, sizeof(csid_dev_name), + "csid%1u", csid_dev_idx); + + csid_hw_intf->hw_idx = csid_dev_idx; + csid_hw_intf->hw_type = CAM_ISP_HW_TYPE_IFE_CSID; + csid_hw_intf->hw_priv = csid_hw_info; + + csid_hw_info->core_info = csid_dev; + csid_hw_info->soc_info.pdev = pdev; + csid_hw_info->soc_info.dev = &pdev->dev; + csid_hw_info->soc_info.dev_name = csid_dev_name; + csid_hw_info->soc_info.index = csid_dev_idx; + + csid_hw_data = (struct cam_ife_csid_hw_info *)match_dev->data; + /* need to setup the pdev before call the ife hw probe init */ + csid_dev->csid_info = csid_hw_data; + + rc = cam_ife_csid_hw_probe_init(csid_hw_intf, csid_dev_idx, false); + if (rc) + goto free_dev; + + platform_set_drvdata(pdev, csid_dev); + CAM_DBG(CAM_ISP, "CSID:%d probe successful", + csid_hw_intf->hw_idx); + + + if (csid_hw_intf->hw_idx < CAM_IFE_CSID_HW_NUM_MAX) + cam_ife_csid_hw_list[csid_hw_intf->hw_idx] = csid_hw_intf; + else + goto free_dev; + + return 0; + +free_dev: + kfree(csid_dev); +free_hw_info: + kfree(csid_hw_info); +free_hw_intf: + kfree(csid_hw_intf); +err: + return rc; +} + +int cam_ife_csid_remove(struct platform_device *pdev) +{ + struct cam_ife_csid_hw *csid_dev = NULL; + struct cam_hw_intf *csid_hw_intf; + struct cam_hw_info *csid_hw_info; + + csid_dev = (struct cam_ife_csid_hw *)platform_get_drvdata(pdev); + csid_hw_intf = csid_dev->hw_intf; + csid_hw_info = csid_dev->hw_info; + + CAM_DBG(CAM_ISP, "CSID:%d remove", + csid_dev->hw_intf->hw_idx); + + cam_ife_csid_hw_deinit(csid_dev); + + /*release the csid device memory */ + kfree(csid_dev); + kfree(csid_hw_info); + kfree(csid_hw_intf); + return 0; +} + +int cam_ife_csid_hw_init(struct cam_hw_intf **ife_csid_hw, + uint32_t hw_idx) +{ + int rc = 0; + + if (cam_ife_csid_hw_list[hw_idx]) { + *ife_csid_hw = cam_ife_csid_hw_list[hw_idx]; + } else { + *ife_csid_hw = NULL; + rc = -1; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..1f8e4d05b74b427412b2660be6f498a7d2b5a87d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_IFE_CSID_DEV_H_ +#define _CAM_IFE_CSID_DEV_H_ + +#include "cam_isp_hw.h" + +irqreturn_t cam_ife_csid_irq(int irq_num, void *data); + +int cam_ife_csid_probe(struct platform_device *pdev); +int cam_ife_csid_remove(struct platform_device *pdev); + +#endif /*_CAM_IFE_CSID_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite17x.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite17x.c new file mode 100644 index 0000000000000000000000000000000000000000..07d555b170093c041e545bab06dfa13274c02d39 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite17x.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_ife_csid_lite17x.h" +#include "cam_ife_csid_lite480.h" +#include "cam_ife_csid_core.h" +#include "cam_ife_csid_dev.h" + +#define CAM_CSID_LITE_DRV_NAME "csid_lite" + +static struct cam_ife_csid_hw_info cam_ife_csid_lite_17x_hw_info = { + .csid_reg = &cam_ife_csid_lite_17x_reg_offset, +}; + +static struct cam_ife_csid_hw_info cam_ife_csid_lite_480_hw_info = { + .csid_reg = &cam_ife_csid_lite_480_reg_offset, +}; + +static const struct of_device_id cam_ife_csid_lite_dt_match[] = { + { + .compatible = "qcom,csid-lite170", + .data = &cam_ife_csid_lite_17x_hw_info, + }, + { + .compatible = "qcom,csid-lite175", + .data = &cam_ife_csid_lite_17x_hw_info, + }, + { + .compatible = "qcom,csid-lite480", + .data = &cam_ife_csid_lite_480_hw_info, + }, + {} +}; +MODULE_DEVICE_TABLE(of, cam_ife_csid_lite_dt_match); + +static struct platform_driver cam_ife_csid_lite_driver = { + .probe = cam_ife_csid_probe, + .remove = cam_ife_csid_remove, + .driver = { + .name = CAM_CSID_LITE_DRV_NAME, + .owner = THIS_MODULE, + .of_match_table = cam_ife_csid_lite_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_ife_csid_lite_init_module(void) +{ + return platform_driver_register(&cam_ife_csid_lite_driver); +} + +static void __exit cam_ife_csid_lite_exit_module(void) +{ + platform_driver_unregister(&cam_ife_csid_lite_driver); +} + +module_init(cam_ife_csid_lite_init_module); +module_exit(cam_ife_csid_lite_exit_module); +MODULE_DESCRIPTION("CAM IFE_CSID_LITE driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite17x.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite17x.h new file mode 100644 index 0000000000000000000000000000000000000000..4d8783ce0c0f4d7f2e96a418ebc7fb46942021e0 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite17x.h @@ -0,0 +1,316 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_IFE_CSID_LITE17X_H_ +#define _CAM_IFE_CSID_LITE17X_H_ +#include "cam_ife_csid_core.h" + +static const struct cam_ife_csid_rdi_reg_offset + cam_ife_csid_lite_17x_rdi_0_reg_offset = { + + .csid_rdi_irq_status_addr = 0x30, + .csid_rdi_irq_mask_addr = 0x34, + .csid_rdi_irq_clear_addr = 0x38, + .csid_rdi_irq_set_addr = 0x3c, + .csid_rdi_cfg0_addr = 0x200, + .csid_rdi_cfg1_addr = 0x204, + .csid_rdi_ctrl_addr = 0x208, + .csid_rdi_frm_drop_pattern_addr = 0x20c, + .csid_rdi_frm_drop_period_addr = 0x210, + .csid_rdi_irq_subsample_pattern_addr = 0x214, + .csid_rdi_irq_subsample_period_addr = 0x218, + .csid_rdi_rpp_hcrop_addr = 0x21c, + .csid_rdi_rpp_vcrop_addr = 0x220, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x224, + .csid_rdi_rpp_pix_drop_period_addr = 0x228, + .csid_rdi_rpp_line_drop_pattern_addr = 0x22c, + .csid_rdi_rpp_line_drop_period_addr = 0x230, + .csid_rdi_rst_strobes_addr = 0x240, + .csid_rdi_status_addr = 0x250, + .csid_rdi_misr_val0_addr = 0x254, + .csid_rdi_misr_val1_addr = 0x258, + .csid_rdi_misr_val2_addr = 0x25c, + .csid_rdi_misr_val3_addr = 0x260, + .csid_rdi_format_measure_cfg0_addr = 0x270, + .csid_rdi_format_measure_cfg1_addr = 0x274, + .csid_rdi_format_measure0_addr = 0x278, + .csid_rdi_format_measure1_addr = 0x27c, + .csid_rdi_format_measure2_addr = 0x280, + .csid_rdi_timestamp_curr0_sof_addr = 0x290, + .csid_rdi_timestamp_curr1_sof_addr = 0x294, + .csid_rdi_timestamp_prev0_sof_addr = 0x298, + .csid_rdi_timestamp_prev1_sof_addr = 0x29c, + .csid_rdi_timestamp_curr0_eof_addr = 0x2a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x2a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x2a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x2ac, + .csid_rdi_byte_cntr_ping_addr = 0x2e0, + .csid_rdi_byte_cntr_pong_addr = 0x2e4, +}; + +static const struct cam_ife_csid_rdi_reg_offset + cam_ife_csid_lite_17x_rdi_1_reg_offset = { + + .csid_rdi_irq_status_addr = 0x40, + .csid_rdi_irq_mask_addr = 0x44, + .csid_rdi_irq_clear_addr = 0x48, + .csid_rdi_irq_set_addr = 0x4c, + .csid_rdi_cfg0_addr = 0x300, + .csid_rdi_cfg1_addr = 0x304, + .csid_rdi_ctrl_addr = 0x308, + .csid_rdi_frm_drop_pattern_addr = 0x30c, + .csid_rdi_frm_drop_period_addr = 0x310, + .csid_rdi_irq_subsample_pattern_addr = 0x314, + .csid_rdi_irq_subsample_period_addr = 0x318, + .csid_rdi_rpp_hcrop_addr = 0x31c, + .csid_rdi_rpp_vcrop_addr = 0x320, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x324, + .csid_rdi_rpp_pix_drop_period_addr = 0x328, + .csid_rdi_rpp_line_drop_pattern_addr = 0x32c, + .csid_rdi_rpp_line_drop_period_addr = 0x330, + .csid_rdi_rst_strobes_addr = 0x340, + .csid_rdi_status_addr = 0x350, + .csid_rdi_misr_val0_addr = 0x354, + .csid_rdi_misr_val1_addr = 0x358, + .csid_rdi_misr_val2_addr = 0x35c, + .csid_rdi_misr_val3_addr = 0x360, + .csid_rdi_format_measure_cfg0_addr = 0x370, + .csid_rdi_format_measure_cfg1_addr = 0x374, + .csid_rdi_format_measure0_addr = 0x378, + .csid_rdi_format_measure1_addr = 0x37c, + .csid_rdi_format_measure2_addr = 0x380, + .csid_rdi_timestamp_curr0_sof_addr = 0x390, + .csid_rdi_timestamp_curr1_sof_addr = 0x394, + .csid_rdi_timestamp_prev0_sof_addr = 0x398, + .csid_rdi_timestamp_prev1_sof_addr = 0x39c, + .csid_rdi_timestamp_curr0_eof_addr = 0x3a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x3a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x3a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x3ac, + .csid_rdi_byte_cntr_ping_addr = 0x3e0, + .csid_rdi_byte_cntr_pong_addr = 0x3e4, +}; + +static const struct cam_ife_csid_rdi_reg_offset + cam_ife_csid_lite_17x_rdi_2_reg_offset = { + + .csid_rdi_irq_status_addr = 0x50, + .csid_rdi_irq_mask_addr = 0x54, + .csid_rdi_irq_clear_addr = 0x58, + .csid_rdi_irq_set_addr = 0x5c, + .csid_rdi_cfg0_addr = 0x400, + .csid_rdi_cfg1_addr = 0x404, + .csid_rdi_ctrl_addr = 0x408, + .csid_rdi_frm_drop_pattern_addr = 0x40c, + .csid_rdi_frm_drop_period_addr = 0x410, + .csid_rdi_irq_subsample_pattern_addr = 0x414, + .csid_rdi_irq_subsample_period_addr = 0x418, + .csid_rdi_rpp_hcrop_addr = 0x41c, + .csid_rdi_rpp_vcrop_addr = 0x420, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x424, + .csid_rdi_rpp_pix_drop_period_addr = 0x428, + .csid_rdi_rpp_line_drop_pattern_addr = 0x42c, + .csid_rdi_rpp_line_drop_period_addr = 0x430, + .csid_rdi_yuv_chroma_conversion_addr = 0x434, + .csid_rdi_rst_strobes_addr = 0x440, + .csid_rdi_status_addr = 0x450, + .csid_rdi_misr_val0_addr = 0x454, + .csid_rdi_misr_val1_addr = 0x458, + .csid_rdi_misr_val2_addr = 0x45c, + .csid_rdi_misr_val3_addr = 0x460, + .csid_rdi_format_measure_cfg0_addr = 0x470, + .csid_rdi_format_measure_cfg1_addr = 0x474, + .csid_rdi_format_measure0_addr = 0x478, + .csid_rdi_format_measure1_addr = 0x47c, + .csid_rdi_format_measure2_addr = 0x480, + .csid_rdi_timestamp_curr0_sof_addr = 0x490, + .csid_rdi_timestamp_curr1_sof_addr = 0x494, + .csid_rdi_timestamp_prev0_sof_addr = 0x498, + .csid_rdi_timestamp_prev1_sof_addr = 0x49c, + .csid_rdi_timestamp_curr0_eof_addr = 0x4a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x4a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x4a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x4ac, + .csid_rdi_byte_cntr_ping_addr = 0x4e0, + .csid_rdi_byte_cntr_pong_addr = 0x4e4, +}; + +static const struct cam_ife_csid_rdi_reg_offset + cam_ife_csid_lite_17x_rdi_3_reg_offset = { + + .csid_rdi_irq_status_addr = 0x60, + .csid_rdi_irq_mask_addr = 0x64, + .csid_rdi_irq_clear_addr = 0x68, + .csid_rdi_irq_set_addr = 0x6c, + .csid_rdi_cfg0_addr = 0x500, + .csid_rdi_cfg1_addr = 0x504, + .csid_rdi_ctrl_addr = 0x508, + .csid_rdi_frm_drop_pattern_addr = 0x50c, + .csid_rdi_frm_drop_period_addr = 0x510, + .csid_rdi_irq_subsample_pattern_addr = 0x514, + .csid_rdi_irq_subsample_period_addr = 0x518, + .csid_rdi_rpp_hcrop_addr = 0x51c, + .csid_rdi_rpp_vcrop_addr = 0x520, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x524, + .csid_rdi_rpp_pix_drop_period_addr = 0x528, + .csid_rdi_rpp_line_drop_pattern_addr = 0x52c, + .csid_rdi_rpp_line_drop_period_addr = 0x530, + .csid_rdi_yuv_chroma_conversion_addr = 0x534, + .csid_rdi_rst_strobes_addr = 0x540, + .csid_rdi_status_addr = 0x550, + .csid_rdi_misr_val0_addr = 0x554, + .csid_rdi_misr_val1_addr = 0x558, + .csid_rdi_misr_val2_addr = 0x55c, + .csid_rdi_misr_val3_addr = 0x560, + .csid_rdi_format_measure_cfg0_addr = 0x570, + .csid_rdi_format_measure_cfg1_addr = 0x574, + .csid_rdi_format_measure0_addr = 0x578, + .csid_rdi_format_measure1_addr = 0x57c, + .csid_rdi_format_measure2_addr = 0x580, + .csid_rdi_timestamp_curr0_sof_addr = 0x590, + .csid_rdi_timestamp_curr1_sof_addr = 0x594, + .csid_rdi_timestamp_prev0_sof_addr = 0x598, + .csid_rdi_timestamp_prev1_sof_addr = 0x59c, + .csid_rdi_timestamp_curr0_eof_addr = 0x5a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x5a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x5a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x5ac, + .csid_rdi_byte_cntr_ping_addr = 0x5e0, + .csid_rdi_byte_cntr_pong_addr = 0x5e4, +}; + +static const struct cam_ife_csid_csi2_rx_reg_offset + cam_ife_csid_lite_17x_csi2_reg_offset = { + + .csid_csi2_rx_irq_status_addr = 0x20, + .csid_csi2_rx_irq_mask_addr = 0x24, + .csid_csi2_rx_irq_clear_addr = 0x28, + .csid_csi2_rx_irq_set_addr = 0x2c, + + /*CSI2 rx control */ + .csid_csi2_rx_cfg0_addr = 0x100, + .csid_csi2_rx_cfg1_addr = 0x104, + .csid_csi2_rx_capture_ctrl_addr = 0x108, + .csid_csi2_rx_rst_strobes_addr = 0x110, + .csid_csi2_rx_de_scramble_cfg0_addr = 0x114, + .csid_csi2_rx_de_scramble_cfg1_addr = 0x118, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, + .csid_csi2_rx_captured_short_pkt_0_addr = 0x128, + .csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, + .csid_csi2_rx_captured_long_pkt_0_addr = 0x130, + .csid_csi2_rx_captured_long_pkt_1_addr = 0x134, + .csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, + .csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, + .csid_csi2_rx_lane0_misr_addr = 0x150, + .csid_csi2_rx_lane1_misr_addr = 0x154, + .csid_csi2_rx_lane2_misr_addr = 0x158, + .csid_csi2_rx_lane3_misr_addr = 0x15c, + .csid_csi2_rx_total_pkts_rcvd_addr = 0x160, + .csid_csi2_rx_stats_ecc_addr = 0x164, + .csid_csi2_rx_total_crc_err_addr = 0x168, + + .csi2_rst_srb_all = 0x3FFF, + .csi2_rst_done_shift_val = 27, + .csi2_irq_mask_all = 0xFFFFFFF, + .csi2_misr_enable_shift_val = 6, + .csi2_vc_mode_shift_val = 2, + .csi2_capture_long_pkt_en_shift = 0, + .csi2_capture_short_pkt_en_shift = 1, + .csi2_capture_cphy_pkt_en_shift = 2, + .csi2_capture_long_pkt_dt_shift = 4, + .csi2_capture_long_pkt_vc_shift = 10, + .csi2_capture_short_pkt_vc_shift = 15, + .csi2_capture_cphy_pkt_dt_shift = 20, + .csi2_capture_cphy_pkt_vc_shift = 26, + .csi2_rx_phy_num_mask = 0x3, +}; + + +static const struct cam_ife_csid_csi2_tpg_reg_offset + cam_ife_csid_lite_17x_tpg_reg_offset = { + + /*CSID TPG control */ + .csid_tpg_ctrl_addr = 0x600, + .csid_tpg_vc_cfg0_addr = 0x604, + .csid_tpg_vc_cfg1_addr = 0x608, + .csid_tpg_lfsr_seed_addr = 0x60c, + .csid_tpg_dt_n_cfg_0_addr = 0x610, + .csid_tpg_dt_n_cfg_1_addr = 0x614, + .csid_tpg_dt_n_cfg_2_addr = 0x618, + .csid_tpg_color_bars_cfg_addr = 0x640, + .csid_tpg_color_box_cfg_addr = 0x644, + .csid_tpg_common_gen_cfg_addr = 0x648, + .csid_tpg_cgen_n_cfg_addr = 0x650, + .csid_tpg_cgen_n_x0_addr = 0x654, + .csid_tpg_cgen_n_x1_addr = 0x658, + .csid_tpg_cgen_n_x2_addr = 0x65c, + .csid_tpg_cgen_n_xy_addr = 0x660, + .csid_tpg_cgen_n_y1_addr = 0x664, + .csid_tpg_cgen_n_y2_addr = 0x668, + + /*configurations */ + .tpg_dtn_cfg_offset = 0xc, + .tpg_cgen_cfg_offset = 0x20, + .tpg_cpas_ife_reg_offset = 0x28, +}; + + +static const struct cam_ife_csid_common_reg_offset + cam_csid_lite_17x_cmn_reg_offset = { + + .csid_hw_version_addr = 0x0, + .csid_cfg0_addr = 0x4, + .csid_ctrl_addr = 0x8, + .csid_reset_addr = 0xc, + .csid_rst_strobes_addr = 0x10, + + .csid_test_bus_ctrl_addr = 0x14, + .csid_top_irq_status_addr = 0x70, + .csid_top_irq_mask_addr = 0x74, + .csid_top_irq_clear_addr = 0x78, + .csid_top_irq_set_addr = 0x7c, + .csid_irq_cmd_addr = 0x80, + + /*configurations */ + .major_version = 1, + .minor_version = 7, + .version_incr = 0, + .num_rdis = 4, + .num_pix = 0, + .csid_reg_rst_stb = 1, + .csid_rst_stb = 0x1e, + .csid_rst_stb_sw_all = 0x1f, + .path_rst_stb_all = 0x7f, + .path_rst_done_shift_val = 1, + .path_en_shift_val = 31, + .packing_fmt_shift_val = 30, + .dt_id_shift_val = 27, + .vc_shift_val = 22, + .dt_shift_val = 16, + .fmt_shift_val = 12, + .plain_fmt_shit_val = 10, + .crop_v_en_shift_val = 6, + .crop_h_en_shift_val = 5, + .crop_shift = 16, + .ipp_irq_mask_all = 0x7FFF, + .rdi_irq_mask_all = 0x7FFF, + .ppp_irq_mask_all = 0xFFFF, +}; + +static const struct cam_ife_csid_reg_offset cam_ife_csid_lite_17x_reg_offset = { + .cmn_reg = &cam_csid_lite_17x_cmn_reg_offset, + .csi2_reg = &cam_ife_csid_lite_17x_csi2_reg_offset, + .ipp_reg = NULL, + .rdi_reg = { + &cam_ife_csid_lite_17x_rdi_0_reg_offset, + &cam_ife_csid_lite_17x_rdi_1_reg_offset, + &cam_ife_csid_lite_17x_rdi_2_reg_offset, + &cam_ife_csid_lite_17x_rdi_3_reg_offset, + }, + .tpg_reg = &cam_ife_csid_lite_17x_tpg_reg_offset, +}; + +#endif /*_CAM_IFE_CSID_LITE17X_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite480.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite480.h new file mode 100644 index 0000000000000000000000000000000000000000..b77f2dfa350e6de73c5f45addc501747497ae6fc --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite480.h @@ -0,0 +1,340 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_IFE_CSID_LITE_480_H_ +#define _CAM_IFE_CSID_LITE_480_H_ + +#include "cam_ife_csid_core.h" + +static struct cam_ife_csid_rdi_reg_offset + cam_ife_csid_lite_480_rdi_0_reg_offset = { + .csid_rdi_irq_status_addr = 0x30, + .csid_rdi_irq_mask_addr = 0x34, + .csid_rdi_irq_clear_addr = 0x38, + .csid_rdi_irq_set_addr = 0x3c, + .csid_rdi_cfg0_addr = 0x200, + .csid_rdi_cfg1_addr = 0x204, + .csid_rdi_ctrl_addr = 0x208, + .csid_rdi_frm_drop_pattern_addr = 0x20c, + .csid_rdi_frm_drop_period_addr = 0x210, + .csid_rdi_irq_subsample_pattern_addr = 0x214, + .csid_rdi_irq_subsample_period_addr = 0x218, + .csid_rdi_rpp_hcrop_addr = 0x21c, + .csid_rdi_rpp_vcrop_addr = 0x220, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x224, + .csid_rdi_rpp_pix_drop_period_addr = 0x228, + .csid_rdi_rpp_line_drop_pattern_addr = 0x22c, + .csid_rdi_rpp_line_drop_period_addr = 0x230, + .csid_rdi_rst_strobes_addr = 0x240, + .csid_rdi_status_addr = 0x250, + .csid_rdi_misr_val0_addr = 0x254, + .csid_rdi_misr_val1_addr = 0x258, + .csid_rdi_misr_val2_addr = 0x25c, + .csid_rdi_misr_val3_addr = 0x260, + .csid_rdi_format_measure_cfg0_addr = 0x270, + .csid_rdi_format_measure_cfg1_addr = 0x274, + .csid_rdi_format_measure0_addr = 0x278, + .csid_rdi_format_measure1_addr = 0x27c, + .csid_rdi_format_measure2_addr = 0x280, + .csid_rdi_timestamp_curr0_sof_addr = 0x290, + .csid_rdi_timestamp_curr1_sof_addr = 0x294, + .csid_rdi_timestamp_prev0_sof_addr = 0x298, + .csid_rdi_timestamp_prev1_sof_addr = 0x29c, + .csid_rdi_timestamp_curr0_eof_addr = 0x2a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x2a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x2a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x2ac, + .csid_rdi_err_recovery_cfg0_addr = 0x2b0, + .csid_rdi_err_recovery_cfg1_addr = 0x2b4, + .csid_rdi_err_recovery_cfg2_addr = 0x2b8, + .csid_rdi_multi_vcdt_cfg0_addr = 0x2bc, + .csid_rdi_byte_cntr_ping_addr = 0x2e0, + .csid_rdi_byte_cntr_pong_addr = 0x2e4, + /* configurations */ + .ccif_violation_en = 1, + .overflow_ctrl_en = 1, +}; + +static struct cam_ife_csid_rdi_reg_offset + cam_ife_csid_lite_480_rdi_1_reg_offset = { + .csid_rdi_irq_status_addr = 0x40, + .csid_rdi_irq_mask_addr = 0x44, + .csid_rdi_irq_clear_addr = 0x48, + .csid_rdi_irq_set_addr = 0x4c, + .csid_rdi_cfg0_addr = 0x300, + .csid_rdi_cfg1_addr = 0x304, + .csid_rdi_ctrl_addr = 0x308, + .csid_rdi_frm_drop_pattern_addr = 0x30c, + .csid_rdi_frm_drop_period_addr = 0x310, + .csid_rdi_irq_subsample_pattern_addr = 0x314, + .csid_rdi_irq_subsample_period_addr = 0x318, + .csid_rdi_rpp_hcrop_addr = 0x31c, + .csid_rdi_rpp_vcrop_addr = 0x320, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x324, + .csid_rdi_rpp_pix_drop_period_addr = 0x328, + .csid_rdi_rpp_line_drop_pattern_addr = 0x32c, + .csid_rdi_rpp_line_drop_period_addr = 0x330, + .csid_rdi_rst_strobes_addr = 0x340, + .csid_rdi_status_addr = 0x350, + .csid_rdi_misr_val0_addr = 0x354, + .csid_rdi_misr_val1_addr = 0x358, + .csid_rdi_misr_val2_addr = 0x35c, + .csid_rdi_misr_val3_addr = 0x360, + .csid_rdi_format_measure_cfg0_addr = 0x370, + .csid_rdi_format_measure_cfg1_addr = 0x374, + .csid_rdi_format_measure0_addr = 0x378, + .csid_rdi_format_measure1_addr = 0x37c, + .csid_rdi_format_measure2_addr = 0x380, + .csid_rdi_timestamp_curr0_sof_addr = 0x390, + .csid_rdi_timestamp_curr1_sof_addr = 0x394, + .csid_rdi_timestamp_prev0_sof_addr = 0x398, + .csid_rdi_timestamp_prev1_sof_addr = 0x39c, + .csid_rdi_timestamp_curr0_eof_addr = 0x3a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x3a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x3a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x3ac, + .csid_rdi_err_recovery_cfg0_addr = 0x3b0, + .csid_rdi_err_recovery_cfg1_addr = 0x3b4, + .csid_rdi_err_recovery_cfg2_addr = 0x3b8, + .csid_rdi_multi_vcdt_cfg0_addr = 0x3bc, + .csid_rdi_byte_cntr_ping_addr = 0x3e0, + .csid_rdi_byte_cntr_pong_addr = 0x3e4, + /* configurations */ + .ccif_violation_en = 1, + .overflow_ctrl_en = 1, +}; + +static struct cam_ife_csid_rdi_reg_offset + cam_ife_csid_lite_480_rdi_2_reg_offset = { + .csid_rdi_irq_status_addr = 0x50, + .csid_rdi_irq_mask_addr = 0x54, + .csid_rdi_irq_clear_addr = 0x58, + .csid_rdi_irq_set_addr = 0x5c, + .csid_rdi_cfg0_addr = 0x400, + .csid_rdi_cfg1_addr = 0x404, + .csid_rdi_ctrl_addr = 0x408, + .csid_rdi_frm_drop_pattern_addr = 0x40c, + .csid_rdi_frm_drop_period_addr = 0x410, + .csid_rdi_irq_subsample_pattern_addr = 0x414, + .csid_rdi_irq_subsample_period_addr = 0x418, + .csid_rdi_rpp_hcrop_addr = 0x41c, + .csid_rdi_rpp_vcrop_addr = 0x420, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x424, + .csid_rdi_rpp_pix_drop_period_addr = 0x428, + .csid_rdi_rpp_line_drop_pattern_addr = 0x42c, + .csid_rdi_rpp_line_drop_period_addr = 0x430, + .csid_rdi_rst_strobes_addr = 0x440, + .csid_rdi_status_addr = 0x450, + .csid_rdi_misr_val0_addr = 0x454, + .csid_rdi_misr_val1_addr = 0x458, + .csid_rdi_misr_val2_addr = 0x45c, + .csid_rdi_misr_val3_addr = 0x460, + .csid_rdi_format_measure_cfg0_addr = 0x470, + .csid_rdi_format_measure_cfg1_addr = 0x474, + .csid_rdi_format_measure0_addr = 0x478, + .csid_rdi_format_measure1_addr = 0x47c, + .csid_rdi_format_measure2_addr = 0x480, + .csid_rdi_timestamp_curr0_sof_addr = 0x490, + .csid_rdi_timestamp_curr1_sof_addr = 0x494, + .csid_rdi_timestamp_prev0_sof_addr = 0x498, + .csid_rdi_timestamp_prev1_sof_addr = 0x49c, + .csid_rdi_timestamp_curr0_eof_addr = 0x4a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x4a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x4a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x4ac, + .csid_rdi_err_recovery_cfg0_addr = 0x4b0, + .csid_rdi_err_recovery_cfg1_addr = 0x4b4, + .csid_rdi_err_recovery_cfg2_addr = 0x4b8, + .csid_rdi_multi_vcdt_cfg0_addr = 0x4bc, + .csid_rdi_byte_cntr_ping_addr = 0x4e0, + .csid_rdi_byte_cntr_pong_addr = 0x4e4, + /* configurations */ + .ccif_violation_en = 1, + .overflow_ctrl_en = 1, +}; + +static struct cam_ife_csid_rdi_reg_offset + cam_ife_csid_lite_480_rdi_3_reg_offset = { + .csid_rdi_irq_status_addr = 0x60, + .csid_rdi_irq_mask_addr = 0x64, + .csid_rdi_irq_clear_addr = 0x68, + .csid_rdi_irq_set_addr = 0x6c, + .csid_rdi_cfg0_addr = 0x500, + .csid_rdi_cfg1_addr = 0x504, + .csid_rdi_ctrl_addr = 0x508, + .csid_rdi_frm_drop_pattern_addr = 0x50c, + .csid_rdi_frm_drop_period_addr = 0x510, + .csid_rdi_irq_subsample_pattern_addr = 0x514, + .csid_rdi_irq_subsample_period_addr = 0x518, + .csid_rdi_rpp_hcrop_addr = 0x51c, + .csid_rdi_rpp_vcrop_addr = 0x520, + .csid_rdi_rpp_pix_drop_pattern_addr = 0x524, + .csid_rdi_rpp_pix_drop_period_addr = 0x528, + .csid_rdi_rpp_line_drop_pattern_addr = 0x52c, + .csid_rdi_rpp_line_drop_period_addr = 0x530, + .csid_rdi_rst_strobes_addr = 0x540, + .csid_rdi_status_addr = 0x550, + .csid_rdi_misr_val0_addr = 0x554, + .csid_rdi_misr_val1_addr = 0x558, + .csid_rdi_misr_val2_addr = 0x55c, + .csid_rdi_misr_val3_addr = 0x560, + .csid_rdi_format_measure_cfg0_addr = 0x570, + .csid_rdi_format_measure_cfg1_addr = 0x574, + .csid_rdi_format_measure0_addr = 0x578, + .csid_rdi_format_measure1_addr = 0x57c, + .csid_rdi_format_measure2_addr = 0x580, + .csid_rdi_timestamp_curr0_sof_addr = 0x590, + .csid_rdi_timestamp_curr1_sof_addr = 0x594, + .csid_rdi_timestamp_prev0_sof_addr = 0x598, + .csid_rdi_timestamp_prev1_sof_addr = 0x59c, + .csid_rdi_timestamp_curr0_eof_addr = 0x5a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x5a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x5a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x5ac, + .csid_rdi_err_recovery_cfg0_addr = 0x5b0, + .csid_rdi_err_recovery_cfg1_addr = 0x5b4, + .csid_rdi_err_recovery_cfg2_addr = 0x5b8, + .csid_rdi_multi_vcdt_cfg0_addr = 0x5bc, + .csid_rdi_byte_cntr_ping_addr = 0x5e0, + .csid_rdi_byte_cntr_pong_addr = 0x5e4, + /* configurations */ + .ccif_violation_en = 1, + .overflow_ctrl_en = 1, +}; + +static struct cam_ife_csid_csi2_rx_reg_offset + cam_ife_csid_lite_480_csi2_reg_offset = { + .csid_csi2_rx_irq_status_addr = 0x20, + .csid_csi2_rx_irq_mask_addr = 0x24, + .csid_csi2_rx_irq_clear_addr = 0x28, + .csid_csi2_rx_irq_set_addr = 0x2c, + + /*CSI2 rx control */ + .csid_csi2_rx_cfg0_addr = 0x100, + .csid_csi2_rx_cfg1_addr = 0x104, + .csid_csi2_rx_capture_ctrl_addr = 0x108, + .csid_csi2_rx_rst_strobes_addr = 0x110, + .csid_csi2_rx_de_scramble_cfg0_addr = 0x114, + .csid_csi2_rx_de_scramble_cfg1_addr = 0x118, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, + .csid_csi2_rx_captured_short_pkt_0_addr = 0x128, + .csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, + .csid_csi2_rx_captured_long_pkt_0_addr = 0x130, + .csid_csi2_rx_captured_long_pkt_1_addr = 0x134, + .csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, + .csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, + .csid_csi2_rx_lane0_misr_addr = 0x150, + .csid_csi2_rx_lane1_misr_addr = 0x154, + .csid_csi2_rx_lane2_misr_addr = 0x158, + .csid_csi2_rx_lane3_misr_addr = 0x15c, + .csid_csi2_rx_total_pkts_rcvd_addr = 0x160, + .csid_csi2_rx_stats_ecc_addr = 0x164, + .csid_csi2_rx_total_crc_err_addr = 0x168, + + .csi2_rst_srb_all = 0x3FFF, + .csi2_rst_done_shift_val = 27, + .csi2_irq_mask_all = 0xFFFFFFF, + .csi2_misr_enable_shift_val = 6, + .csi2_vc_mode_shift_val = 2, + .csi2_capture_long_pkt_en_shift = 0, + .csi2_capture_short_pkt_en_shift = 1, + .csi2_capture_cphy_pkt_en_shift = 2, + .csi2_capture_long_pkt_dt_shift = 4, + .csi2_capture_long_pkt_vc_shift = 10, + .csi2_capture_short_pkt_vc_shift = 15, + .csi2_capture_cphy_pkt_dt_shift = 20, + .csi2_capture_cphy_pkt_vc_shift = 26, + .csi2_rx_phy_num_mask = 0x7, +}; + +static struct cam_ife_csid_csi2_tpg_reg_offset + cam_ife_csid_lite_480_tpg_reg_offset = { + /*CSID TPG control */ + .csid_tpg_ctrl_addr = 0x600, + .csid_tpg_vc_cfg0_addr = 0x604, + .csid_tpg_vc_cfg1_addr = 0x608, + .csid_tpg_lfsr_seed_addr = 0x60c, + .csid_tpg_dt_n_cfg_0_addr = 0x610, + .csid_tpg_dt_n_cfg_1_addr = 0x614, + .csid_tpg_dt_n_cfg_2_addr = 0x618, + .csid_tpg_color_bars_cfg_addr = 0x640, + .csid_tpg_color_box_cfg_addr = 0x644, + .csid_tpg_common_gen_cfg_addr = 0x648, + .csid_tpg_cgen_n_cfg_addr = 0x650, + .csid_tpg_cgen_n_x0_addr = 0x654, + .csid_tpg_cgen_n_x1_addr = 0x658, + .csid_tpg_cgen_n_x2_addr = 0x65c, + .csid_tpg_cgen_n_xy_addr = 0x660, + .csid_tpg_cgen_n_y1_addr = 0x664, + .csid_tpg_cgen_n_y2_addr = 0x668, + + /* configurations */ + .tpg_dtn_cfg_offset = 0xc, + .tpg_cgen_cfg_offset = 0x20, + .tpg_cpas_ife_reg_offset = 0x28, +}; + +static struct cam_ife_csid_common_reg_offset + cam_ife_csid_lite_480_cmn_reg_offset = { + .csid_hw_version_addr = 0x0, + .csid_cfg0_addr = 0x4, + .csid_ctrl_addr = 0x8, + .csid_reset_addr = 0xc, + .csid_rst_strobes_addr = 0x10, + + .csid_test_bus_ctrl_addr = 0x14, + .csid_top_irq_status_addr = 0x70, + .csid_top_irq_mask_addr = 0x74, + .csid_top_irq_clear_addr = 0x78, + .csid_top_irq_set_addr = 0x7c, + .csid_irq_cmd_addr = 0x80, + + /*configurations */ + .major_version = 4, + .minor_version = 8, + .version_incr = 0, + .num_rdis = 4, + .num_pix = 0, + .num_ppp = 0, + .csid_reg_rst_stb = 1, + .csid_rst_stb = 0x1e, + .csid_rst_stb_sw_all = 0x1f, + .path_rst_stb_all = 0x7f, + .path_rst_done_shift_val = 1, + .path_en_shift_val = 31, + .packing_fmt_shift_val = 30, + .dt_id_shift_val = 27, + .vc_shift_val = 22, + .dt_shift_val = 16, + .fmt_shift_val = 12, + .plain_fmt_shit_val = 10, + .crop_v_en_shift_val = 6, + .crop_h_en_shift_val = 5, + .drop_v_en_shift_val = 4, + .drop_h_en_shift_val = 3, + .crop_shift = 16, + .ipp_irq_mask_all = 0x7FFF, + .rdi_irq_mask_all = 0x7FFF, + .ppp_irq_mask_all = 0xFFFF, + .measure_en_hbi_vbi_cnt_mask = 0xC, + .format_measure_en_val = 1, +}; + +static struct cam_ife_csid_reg_offset cam_ife_csid_lite_480_reg_offset = { + .cmn_reg = &cam_ife_csid_lite_480_cmn_reg_offset, + .csi2_reg = &cam_ife_csid_lite_480_csi2_reg_offset, + .ipp_reg = NULL, + .ppp_reg = NULL, + .rdi_reg = { + &cam_ife_csid_lite_480_rdi_0_reg_offset, + &cam_ife_csid_lite_480_rdi_1_reg_offset, + &cam_ife_csid_lite_480_rdi_2_reg_offset, + &cam_ife_csid_lite_480_rdi_3_reg_offset, + }, + .tpg_reg = &cam_ife_csid_lite_480_tpg_reg_offset, +}; + +#endif /*_CAM_IFE_CSID_LITE480_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..7abcc64068eed5df8fe5fcde887aeef0c7f7cc0f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ +#include +#include "cam_ife_csid_soc.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" + +static int cam_ife_csid_get_dt_properties(struct cam_hw_soc_info *soc_info) +{ + struct device_node *of_node = NULL; + struct csid_device_soc_info *csid_soc_info = NULL; + int rc = 0; + + of_node = soc_info->pdev->dev.of_node; + csid_soc_info = (struct csid_device_soc_info *)soc_info->soc_private; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc) + return rc; + + return rc; +} + +static int cam_ife_csid_request_platform_resource( + struct cam_hw_soc_info *soc_info, + irq_handler_t csid_irq_handler, + void *irq_data) +{ + int rc = 0; + + rc = cam_soc_util_request_platform_resource(soc_info, csid_irq_handler, + irq_data); + if (rc) + return rc; + + return rc; +} + +int cam_ife_csid_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t csid_irq_handler, void *irq_data, bool is_custom) +{ + int rc = 0; + struct cam_cpas_register_params cpas_register_param; + struct cam_csid_soc_private *soc_private; + + soc_private = kzalloc(sizeof(struct cam_csid_soc_private), GFP_KERNEL); + if (!soc_private) + return -ENOMEM; + + soc_info->soc_private = soc_private; + + rc = cam_ife_csid_get_dt_properties(soc_info); + if (rc < 0) + return rc; + + /* Need to see if we want post process the clock list */ + + rc = cam_ife_csid_request_platform_resource(soc_info, csid_irq_handler, + irq_data); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Error Request platform resources failed rc=%d", rc); + goto free_soc_private; + } + + memset(&cpas_register_param, 0, sizeof(cpas_register_param)); + if (is_custom) + strlcpy(cpas_register_param.identifier, "csid-custom", + CAM_HW_IDENTIFIER_LENGTH); + else + strlcpy(cpas_register_param.identifier, "csid", + CAM_HW_IDENTIFIER_LENGTH); + + cpas_register_param.cell_index = soc_info->index; + cpas_register_param.dev = soc_info->dev; + rc = cam_cpas_register_client(&cpas_register_param); + if (rc) { + CAM_ERR(CAM_ISP, "CPAS registration failed rc=%d", rc); + goto release_soc; + } else { + soc_private->cpas_handle = cpas_register_param.client_handle; + } + + return rc; + +release_soc: + cam_soc_util_release_platform_resource(soc_info); +free_soc_private: + kfree(soc_private); + + return rc; +} + +int cam_ife_csid_deinit_soc_resources( + struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_csid_soc_private *soc_private; + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error soc_private NULL"); + return -ENODEV; + } + + rc = cam_cpas_unregister_client(soc_private->cpas_handle); + if (rc) + CAM_ERR(CAM_ISP, "CPAS unregistration failed rc=%d", rc); + + rc = cam_soc_util_release_platform_resource(soc_info); + + return rc; +} + +int cam_ife_csid_enable_soc_resources( + struct cam_hw_soc_info *soc_info, enum cam_vote_level clk_level) +{ + int rc = 0; + struct cam_csid_soc_private *soc_private; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + + soc_private = soc_info->soc_private; + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_LOWSVS_VOTE; + axi_vote.num_paths = 1; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_WRITE; + + axi_vote.axi_path[0].camnoc_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ab_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW; + + CAM_DBG(CAM_ISP, "csid camnoc_bw:%lld mnoc_ab_bw:%lld mnoc_ib_bw:%lld ", + axi_vote.axi_path[0].camnoc_bw, + axi_vote.axi_path[0].mnoc_ab_bw, + axi_vote.axi_path[0].mnoc_ib_bw); + + rc = cam_cpas_start(soc_private->cpas_handle, &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_ISP, "Error CPAS start failed"); + rc = -EFAULT; + goto end; + } + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + clk_level, true); + if (rc) { + CAM_ERR(CAM_ISP, "enable platform failed"); + goto stop_cpas; + } + + return rc; + +stop_cpas: + cam_cpas_stop(soc_private->cpas_handle); +end: + return rc; +} + +int cam_ife_csid_disable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_csid_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + return -EINVAL; + } + soc_private = soc_info->soc_private; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) + CAM_ERR(CAM_ISP, "Disable platform failed"); + + rc = cam_cpas_stop(soc_private->cpas_handle); + if (rc) { + CAM_ERR(CAM_ISP, "Error CPAS stop failed rc=%d", rc); + return rc; + } + + return rc; +} + +int cam_ife_csid_enable_ife_force_clock_on(struct cam_hw_soc_info *soc_info, + uint32_t cpas_ife_base_offset) +{ + int rc = 0; + struct cam_csid_soc_private *soc_private; + uint32_t cpass_ife_force_clk_offset; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + return -EINVAL; + } + + soc_private = soc_info->soc_private; + cpass_ife_force_clk_offset = + cpas_ife_base_offset + (0x4 * soc_info->index); + rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REG_CPASTOP, + cpass_ife_force_clk_offset, 1, 1); + + if (rc) + CAM_ERR(CAM_ISP, "CPASS set IFE:%d Force clock On failed", + soc_info->index); + else + CAM_DBG(CAM_ISP, "CPASS set IFE:%d Force clock On", + soc_info->index); + + return rc; +} + +int cam_ife_csid_disable_ife_force_clock_on(struct cam_hw_soc_info *soc_info, + uint32_t cpas_ife_base_offset) +{ + int rc = 0; + struct cam_csid_soc_private *soc_private; + uint32_t cpass_ife_force_clk_offset; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + return -EINVAL; + } + + soc_private = soc_info->soc_private; + cpass_ife_force_clk_offset = + cpas_ife_base_offset + (0x4 * soc_info->index); + rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REG_CPASTOP, + cpass_ife_force_clk_offset, 1, 0); + + if (rc) + CAM_ERR(CAM_ISP, "CPASS set IFE:%d Force clock Off failed", + soc_info->index); + else + CAM_DBG(CAM_ISP, "CPASS set IFE:%d Force clock off", + soc_info->index); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..4f76d084fba3050b770dce731cb4b75752c8c084 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_IFE_CSID_SOC_H_ +#define _CAM_IFE_CSID_SOC_H_ + +#include "cam_isp_hw.h" + +/* + * struct cam_csid_soc_private: + * + * @Brief: Private SOC data specific to CSID HW Driver + * + * @cpas_handle: Handle returned on registering with CPAS driver. + * This handle is used for all further interface + * with CPAS. + */ +struct cam_csid_soc_private { + uint32_t cpas_handle; +}; + +/** + * struct csid_device_soc_info - CSID SOC info object + * + * @csi_vdd_voltage: csi vdd voltage value + * + */ +struct csid_device_soc_info { + int csi_vdd_voltage; +}; + +/** + * cam_ife_csid_init_soc_resources() + * + * @brief: csid initialization function for the soc info + * + * @soc_info: soc info structure pointer + * @csid_irq_handler: irq handler function to be registered + * @irq_data: irq data for the callback function + * @is_custom: for custom csid hw + * + */ +int cam_ife_csid_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t csid_irq_handler, void *irq_data, bool is_custom); + + +/** + * cam_ife_csid_deinit_soc_resources() + * + * @brief: csid de initialization function for the soc info + * + * @soc_info: soc info structure pointer + * + */ +int cam_ife_csid_deinit_soc_resources(struct cam_hw_soc_info *soc_info); + +/** + * cam_ife_csid_enable_soc_resources() + * + * @brief: csid soc resource enable function + * + * @soc_info: soc info structure pointer + * @clk_lvl: vote level to start with + * + */ +int cam_ife_csid_enable_soc_resources(struct cam_hw_soc_info *soc_info, + uint32_t clk_lvl); + +/** + * cam_ife_csid_disable_soc_resources() + * + * @brief: csid soc resource disable function + * + * @soc_info: soc info structure pointer + * + */ +int cam_ife_csid_disable_soc_resources(struct cam_hw_soc_info *soc_info); + +/** + * cam_ife_csid_enable_ife_force_clock() + * + * @brief: if csid testgen used for dual isp case, before + * starting csid test gen, enable ife force clock on + * through cpas + * + * @soc_info: soc info structure pointer + * @cpas_ife_base_offset: cpas ife force clock base reg offset value + * + */ +int cam_ife_csid_enable_ife_force_clock_on(struct cam_hw_soc_info *soc_info, + uint32_t cpas_ife_base_offset); + +/** + * cam_ife_csid_disable_ife_force_clock_on() + * + * @brief: disable the IFE force clock on after dual ISP + * CSID test gen stop + * + * @soc_info: soc info structure pointer + * @cpas_ife_base_offset: cpas ife force clock base reg offset value + * + */ +int cam_ife_csid_disable_ife_force_clock_on(struct cam_hw_soc_info *soc_info, + uint32_t cpas_ife_base_offset); + +/** + * cam_ife_csid_get_vote_level() + * + * @brief: get the vote level from clock rate + * + * @soc_info: soc info structure pointer + * @clock_rate clock rate + * + */ +uint32_t cam_ife_csid_get_vote_level(struct cam_hw_soc_info *soc_info, + uint64_t clock_rate); + +#endif diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..62c49ed8be9e5b06aeb59227d510200671e7f1c5 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSID_HW_INTF_H_ +#define _CAM_CSID_HW_INTF_H_ + +#include "cam_isp_hw.h" +#include "cam_hw_intf.h" + +/* MAX IFE CSID instance */ +#define CAM_IFE_CSID_HW_NUM_MAX 7 +#define CAM_IFE_CSID_RDI_MAX 4 +#define CAM_IFE_CSID_UDI_MAX 3 + +/** + * enum cam_ife_pix_path_res_id - Specify the csid patch + */ +enum cam_ife_pix_path_res_id { + CAM_IFE_PIX_PATH_RES_RDI_0, + CAM_IFE_PIX_PATH_RES_RDI_1, + CAM_IFE_PIX_PATH_RES_RDI_2, + CAM_IFE_PIX_PATH_RES_RDI_3, + CAM_IFE_PIX_PATH_RES_IPP, + CAM_IFE_PIX_PATH_RES_PPP, + CAM_IFE_PIX_PATH_RES_UDI_0, + CAM_IFE_PIX_PATH_RES_UDI_1, + CAM_IFE_PIX_PATH_RES_UDI_2, + CAM_IFE_PIX_PATH_RES_MAX, +}; + +/** + * enum cam_ife_cid_res_id - Specify the csid cid + */ +enum cam_ife_cid_res_id { + CAM_IFE_CSID_CID_0, + CAM_IFE_CSID_CID_1, + CAM_IFE_CSID_CID_2, + CAM_IFE_CSID_CID_3, + CAM_IFE_CSID_CID_MAX, +}; + +/** + * struct cam_ife_csid_hw_caps- get the CSID hw capability + * @num_rdis: number of rdis supported by CSID HW device + * @num_pix: number of pxl paths supported by CSID HW device + * @num_ppp: number of ppp paths supported by CSID HW device + * @major_version : major version + * @minor_version: minor version + * @version_incr: version increment + * + */ +struct cam_ife_csid_hw_caps { + uint32_t num_rdis; + uint32_t num_pix; + uint32_t num_ppp; + uint32_t major_version; + uint32_t minor_version; + uint32_t version_incr; +}; + +struct cam_isp_out_port_generic_info { + uint32_t res_type; + uint32_t format; + uint32_t width; + uint32_t height; + uint32_t comp_grp_id; + uint32_t split_point; + uint32_t secure_mode; + uint32_t reserved; +}; + +struct cam_isp_in_port_generic_info { + uint32_t major_ver; + uint32_t minor_ver; + uint32_t res_type; + uint32_t lane_type; + uint32_t lane_num; + uint32_t lane_cfg; + uint32_t vc[CAM_ISP_VC_DT_CFG]; + uint32_t dt[CAM_ISP_VC_DT_CFG]; + uint32_t num_valid_vc_dt; + uint32_t format; + uint32_t test_pattern; + uint32_t usage_type; + uint32_t left_start; + uint32_t left_stop; + uint32_t left_width; + uint32_t right_start; + uint32_t right_stop; + uint32_t right_width; + uint32_t line_start; + uint32_t line_stop; + uint32_t height; + uint32_t pixel_clk; + uint32_t batch_size; + uint32_t dsp_mode; + uint32_t hbi_cnt; + uint32_t cust_node; + uint32_t num_out_res; + uint32_t horizontal_bin; + uint32_t qcfa_bin; + uint32_t num_bytes_out; + struct cam_isp_out_port_generic_info *data; +}; + +/** + * struct cam_csid_hw_reserve_resource- hw reserve + * @res_type : Reource type CID or PATH + * if type is CID, then res_id is not required, + * if type is path then res id need to be filled + * @res_id : Resource id to be reserved + * @in_port : Input port resource info + * @out_port: Output port resource info, used for RDI path only + * @sync_mode: Sync mode + * Sync mode could be master, slave or none + * @master_idx: Master device index to be configured in the slave path + * for master path, this value is not required. + * only slave need to configure the master index value + * @cid: cid (DT_ID) value for path, this is applicable for CSID path + * reserve + * @node_res : Reserved resource structure pointer + * @crop_enable : Flag to indicate CSID crop enable + * @drop_enable : Flag to indicate CSID drop enable + * @priv: private data to be sent in callback + * @event_cb: CSID event callback to hw manager + * + */ +struct cam_csid_hw_reserve_resource_args { + enum cam_isp_resource_type res_type; + uint32_t res_id; + struct cam_isp_in_port_generic_info *in_port; + struct cam_isp_out_port_generic_info *out_port; + enum cam_isp_hw_sync_mode sync_mode; + uint32_t master_idx; + uint32_t cid; + struct cam_isp_resource_node *node_res; + bool crop_enable; + bool drop_enable; + void *priv; + cam_hw_mgr_event_cb_func event_cb; +}; + +/** + * enum cam_ife_csid_halt_cmd - Specify the halt command type + */ +enum cam_ife_csid_halt_cmd { + CAM_CSID_HALT_AT_FRAME_BOUNDARY, + CAM_CSID_RESUME_AT_FRAME_BOUNDARY, + CAM_CSID_HALT_IMMEDIATELY, + CAM_CSID_HALT_MAX, +}; + +/** + * struct cam_csid_hw_stop- stop all resources + * @stop_cmd : Applicable only for PATH resources + * if stop command set to Halt immediately,driver will stop + * path immediately, manager need to reset the path after HI + * if stop command set to halt at frame boundary, driver will set + * halt at frame boundary and wait for frame boundary + * @node_res : reource pointer array( ie cid or CSID) + * @num_res : number of resources to be stopped + * + */ +struct cam_csid_hw_stop_args { + enum cam_ife_csid_halt_cmd stop_cmd; + struct cam_isp_resource_node **node_res; + uint32_t num_res; +}; + +/** + * enum cam_ife_csid_reset_type - Specify the reset type + */ +enum cam_ife_csid_reset_type { + CAM_IFE_CSID_RESET_GLOBAL, + CAM_IFE_CSID_RESET_PATH, + CAM_IFE_CSID_RESET_MAX, +}; + +/** + * struct cam_ife_csid_reset_cfg- csid reset configuration + * @ reset_type : Global reset or path reset + * @res_node : resource need to be reset + * + */ +struct cam_csid_reset_cfg_args { + enum cam_ife_csid_reset_type reset_type; + struct cam_isp_resource_node *node_res; +}; + +/** + * struct cam_csid_get_time_stamp_args- time stamp capture arguments + * @res_node : resource to get the time stamp + * @time_stamp_val : captured time stamp + * @boot_timestamp : boot time stamp + */ +struct cam_csid_get_time_stamp_args { + struct cam_isp_resource_node *node_res; + uint64_t time_stamp_val; + uint64_t boot_timestamp; +}; + +/** + * enum cam_ife_csid_cmd_type - Specify the csid command + */ +enum cam_ife_csid_cmd_type { + CAM_IFE_CSID_CMD_GET_TIME_STAMP, + CAM_IFE_CSID_SET_CSID_DEBUG, + CAM_IFE_CSID_SOF_IRQ_DEBUG, + CAM_IFE_CSID_CMD_MAX, +}; + +/** + * cam_ife_csid_hw_init() + * + * @brief: Initialize function for the CSID hardware + * + * @ife_csid_hw: CSID hardware instance returned + * @hw_idex: CSID hardware instance id + */ +int cam_ife_csid_hw_init(struct cam_hw_intf **ife_csid_hw, + uint32_t hw_idx); + +/* + * struct cam_ife_csid_clock_update_args: + * + * @clk_rate: Clock rate requested + */ +struct cam_ife_csid_clock_update_args { + uint64_t clk_rate; +}; + +/* + * struct cam_ife_csid_qcfa_update_args: + * + * @qcfa_binning: QCFA binning supported + */ +struct cam_ife_csid_qcfa_update_args { + uint32_t qcfa_binning; +}; + + +#endif /* _CAM_CSID_HW_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h new file mode 100644 index 0000000000000000000000000000000000000000..4603b20b6a68e88d41d860cd4fac5d200037401d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h @@ -0,0 +1,298 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_ISP_HW_H_ +#define _CAM_ISP_HW_H_ + +#include +#include +#include "cam_hw.h" +#include "cam_soc_util.h" +#include "cam_irq_controller.h" +#include "cam_hw_intf.h" + +/* Maximum length of tag while dumping */ +#define CAM_ISP_HW_DUMP_TAG_MAX_LEN 32 +/* + * struct cam_isp_timestamp: + * + * @mono_time: Monotonic boot time + * @vt_time: AV Timer time + * @ticks: Qtimer ticks + */ +struct cam_isp_timestamp { + struct timeval mono_time; + struct timeval vt_time; + uint64_t ticks; +}; + +/* + * cam_isp_hw_get_timestamp() + * + * @Brief: Get timestamp values + * + * @time_stamp: Structure that holds different time values + * + * @Return: Void + */ +void cam_isp_hw_get_timestamp(struct cam_isp_timestamp *time_stamp); + +enum cam_isp_hw_type { + CAM_ISP_HW_TYPE_CSID, + CAM_ISP_HW_TYPE_ISPIF, + CAM_ISP_HW_TYPE_VFE, + CAM_ISP_HW_TYPE_IFE_CSID, + CAM_ISP_HW_TYPE_TFE, + CAM_ISP_HW_TYPE_TFE_CSID, + CAM_ISP_HW_TYPE_TPG, + CAM_ISP_HW_TYPE_MAX, +}; + +enum cam_isp_hw_split_id { + CAM_ISP_HW_SPLIT_LEFT = 0, + CAM_ISP_HW_SPLIT_RIGHT, + CAM_ISP_HW_SPLIT_MAX, +}; + +enum cam_isp_hw_sync_mode { + CAM_ISP_HW_SYNC_NONE, + CAM_ISP_HW_SYNC_MASTER, + CAM_ISP_HW_SYNC_SLAVE, + CAM_ISP_HW_SYNC_MAX, +}; + +enum cam_isp_resource_state { + CAM_ISP_RESOURCE_STATE_UNAVAILABLE = 0, + CAM_ISP_RESOURCE_STATE_AVAILABLE = 1, + CAM_ISP_RESOURCE_STATE_RESERVED = 2, + CAM_ISP_RESOURCE_STATE_INIT_HW = 3, + CAM_ISP_RESOURCE_STATE_STREAMING = 4, +}; + +enum cam_isp_resource_type { + CAM_ISP_RESOURCE_UNINT, + CAM_ISP_RESOURCE_SRC, + CAM_ISP_RESOURCE_CID, + CAM_ISP_RESOURCE_PIX_PATH, + CAM_ISP_RESOURCE_VFE_IN, + CAM_ISP_RESOURCE_VFE_OUT, + CAM_ISP_RESOURCE_VFE_BUS_RD, + CAM_ISP_RESOURCE_TPG, + CAM_ISP_RESOURCE_TFE_IN, + CAM_ISP_RESOURCE_TFE_OUT, + CAM_ISP_RESOURCE_MAX, +}; + +enum cam_isp_hw_cmd_type { + CAM_ISP_HW_CMD_GET_CHANGE_BASE, + CAM_ISP_HW_CMD_GET_BUF_UPDATE, + CAM_ISP_HW_CMD_GET_BUF_UPDATE_RM, + CAM_ISP_HW_CMD_GET_REG_UPDATE, + CAM_ISP_HW_CMD_GET_HFR_UPDATE, + CAM_ISP_HW_CMD_GET_HFR_UPDATE_RM, + CAM_ISP_HW_CMD_GET_SECURE_MODE, + CAM_ISP_HW_CMD_STRIPE_UPDATE, + CAM_ISP_HW_CMD_CLOCK_UPDATE, + CAM_ISP_HW_CMD_BW_UPDATE, + CAM_ISP_HW_CMD_BW_UPDATE_V2, + CAM_ISP_HW_CMD_BW_CONTROL, + CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ, + CAM_ISP_HW_CMD_GET_REG_DUMP, + CAM_ISP_HW_CMD_UBWC_UPDATE, + CAM_ISP_HW_CMD_SOF_IRQ_DEBUG, + CAM_ISP_HW_CMD_SET_CAMIF_DEBUG, + CAM_ISP_HW_CMD_CSID_CLOCK_UPDATE, + CAM_ISP_HW_CMD_FE_UPDATE_IN_RD, + CAM_ISP_HW_CMD_FE_UPDATE_BUS_RD, + CAM_ISP_HW_CMD_UBWC_UPDATE_V2, + CAM_ISP_HW_CMD_CORE_CONFIG, + CAM_ISP_HW_CMD_WM_CONFIG_UPDATE, + CAM_ISP_HW_CMD_CSID_QCFA_SUPPORTED, + CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA, + CAM_ISP_HW_CMD_TPG_PHY_CLOCK_UPDATE, + CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP, + CAM_ISP_HW_CMD_DUMP_HW, + CAM_ISP_HW_CMD_TPG_SET_PATTERN, + CAM_ISP_HW_CMD_MAX, +}; + +/* + * struct cam_isp_resource_node: + * + * @Brief: Structure representing HW resource object + * + * @res_type: Resource Type + * @res_id: Unique resource ID within res_type objects + * for a particular HW + * @res_state: State of the resource + * @hw_intf: HW Interface of HW to which this resource + * belongs + * @res_priv: Private data of the resource + * @list: list_head node for this resource + * @cdm_ops: CDM operation functions + * @tasklet_info: Tasklet structure that will be used to + * schedule IRQ events related to this resource + * @irq_handle: handle returned on subscribing for IRQ event + * @rdi_only_ctx: resource belong to rdi only context or not + * @init: function pointer to init the HW resource + * @deinit: function pointer to deinit the HW resource + * @start: function pointer to start the HW resource + * @stop: function pointer to stop the HW resource + * @process_cmd: function pointer for processing commands + * specific to the resource + * @top_half_handler: Top Half handler function + * @bottom_half_handler: Bottom Half handler function + */ +struct cam_isp_resource_node { + enum cam_isp_resource_type res_type; + uint32_t res_id; + enum cam_isp_resource_state res_state; + struct cam_hw_intf *hw_intf; + void *res_priv; + struct list_head list; + void *cdm_ops; + void *tasklet_info; + int irq_handle; + int rdi_only_ctx; + + int (*init)(struct cam_isp_resource_node *rsrc_node, + void *init_args, uint32_t arg_size); + int (*deinit)(struct cam_isp_resource_node *rsrc_node, + void *deinit_args, uint32_t arg_size); + int (*start)(struct cam_isp_resource_node *rsrc_node); + int (*stop)(struct cam_isp_resource_node *rsrc_node); + int (*process_cmd)(struct cam_isp_resource_node *rsrc_node, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size); + CAM_IRQ_HANDLER_TOP_HALF top_half_handler; + CAM_IRQ_HANDLER_BOTTOM_HALF bottom_half_handler; +}; + +/* + * struct cam_isp_hw_event_info: + * + * @Brief: Structure to pass event details to hw mgr + * + * @res_type: Type of IFE resource + * @res_id: Unique resource ID + * @hw_idx: IFE hw index + * @err_type: Error type if any + * @th_reg_val: Any critical register value captured during th + * + */ +struct cam_isp_hw_event_info { + enum cam_isp_resource_type res_type; + uint32_t res_id; + uint32_t hw_idx; + uint32_t err_type; + uint32_t th_reg_val; +}; + +/* + * struct cam_isp_hw_cmd_buf_update: + * + * @Brief: Contain the new created command buffer information + * + * @cmd_buf_addr: Command buffer to store the change base command + * @size: Size of the buffer in bytes + * @used_bytes: Consumed bytes in the command buffer + * + */ +struct cam_isp_hw_cmd_buf_update { + uint32_t *cmd_buf_addr; + uint32_t size; + uint32_t used_bytes; +}; + +/* + * struct cam_isp_hw_get_wm_update: + * + * @Brief: Get cmd buffer for WM updates. + * + * @ image_buf: image buffer address array + * @ num_buf: Number of buffers in the image_buf array + * @ io_cfg: IO buffer config information sent from UMD + * + */ +struct cam_isp_hw_get_wm_update { + dma_addr_t *image_buf; + uint32_t num_buf; + struct cam_buf_io_cfg *io_cfg; +}; + +/* + * struct cam_isp_hw_get_cmd_update: + * + * @Brief: Get cmd buffer update for different CMD types + * + * @res: Resource node + * @cmd_type: Command type for which to get update + * @cmd: Command buffer information + * + */ +struct cam_isp_hw_get_cmd_update { + struct cam_isp_resource_node *res; + enum cam_isp_hw_cmd_type cmd_type; + struct cam_isp_hw_cmd_buf_update cmd; + union { + void *data; + struct cam_isp_hw_get_wm_update *wm_update; + struct cam_isp_hw_get_wm_update *rm_update; + }; +}; + +/* + * struct cam_isp_hw_dual_isp_update_args: + * + * @Brief: update the dual isp striping configuration. + * + * @ split_id: spilt id to inform left or rifht + * @ res: resource node + * @ dual_cfg: dual isp configuration + * + */ +struct cam_isp_hw_dual_isp_update_args { + enum cam_isp_hw_split_id split_id; + struct cam_isp_resource_node *res; + struct cam_isp_dual_config *dual_cfg; +}; + +/* + * struct cam_isp_hw_dump_args: + * + * @Brief: isp hw dump args + * + * @ req_id: request id + * @ cpu_addr: cpu address + * @ buf_len: buf len + * @ offset: offset of buffer + * @ ctxt_to_hw_map: ctx to hw map + * @ is_dump_all: flag to indicate if all information or just bw/clk rate + */ +struct cam_isp_hw_dump_args { + uint64_t req_id; + uintptr_t cpu_addr; + size_t buf_len; + size_t offset; + void *ctxt_to_hw_map; + bool is_dump_all; +}; + +/** + * struct cam_isp_hw_dump_header - ISP context dump header + * + * @Brief: isp hw dump header + * + * @tag: Tag name for the header + * @word_size: Size of word + * @size: Size of data + * + */ +struct cam_isp_hw_dump_header { + uint8_t tag[CAM_ISP_HW_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + +#endif /* _CAM_ISP_HW_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_csid_hw_intf.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_csid_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..75de9d3ea945055cddf08de71d0f4605a48eee13 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_csid_hw_intf.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_CSID_HW_INTF_H_ +#define _CAM_TFE_CSID_HW_INTF_H_ + +#include "cam_isp_hw.h" +#include "cam_hw_intf.h" + +/* MAX TFE CSID instance */ +#define CAM_TFE_CSID_HW_NUM_MAX 3 +#define CAM_TFE_CSID_RDI_MAX 3 + +/** + * enum cam_tfe_pix_path_res_id - Specify the csid patch + */ +enum cam_tfe_csid_path_res_id { + CAM_TFE_CSID_PATH_RES_RDI_0, + CAM_TFE_CSID_PATH_RES_RDI_1, + CAM_TFE_CSID_PATH_RES_RDI_2, + CAM_TFE_CSID_PATH_RES_IPP, + CAM_TFE_CSID_PATH_RES_MAX, +}; + +/** + * enum cam_tfe_csid_irq_reg + */ +enum cam_tfe_csid_irq_reg { + TFE_CSID_IRQ_REG_RDI0, + TFE_CSID_IRQ_REG_RDI1, + TFE_CSID_IRQ_REG_RDI2, + TFE_CSID_IRQ_REG_TOP, + TFE_CSID_IRQ_REG_RX, + TFE_CSID_IRQ_REG_IPP, + TFE_CSID_IRQ_REG_MAX, +}; + + +/** + * struct cam_tfe_csid_hw_caps- get the CSID hw capability + * @num_rdis: number of rdis supported by CSID HW device + * @num_pix: number of pxl paths supported by CSID HW device + * @major_version : major version + * @minor_version: minor version + * @version_incr: version increment + * + */ +struct cam_tfe_csid_hw_caps { + uint32_t num_rdis; + uint32_t num_pix; + uint32_t major_version; + uint32_t minor_version; + uint32_t version_incr; +}; + +/** + * struct cam_tfe_csid_hw_reserve_resource_args- hw reserve + * @res_type : Reource type ie PATH + * @res_id : Resource id to be reserved + * @in_port : Input port resource info + * @out_port: Output port resource info, used for RDI path only + * @sync_mode: Sync mode + * Sync mode could be master, slave or none + * @master_idx: Master device index to be configured in the slave path + * for master path, this value is not required. + * only slave need to configure the master index value + * @phy_sel: Phy selection number if tpg is enabled from userspace + * @event_cb_prv: Context data + * @event_cb: Callback function to hw mgr in case of hw events + * @node_res : Reserved resource structure pointer + * + */ +struct cam_tfe_csid_hw_reserve_resource_args { + enum cam_isp_resource_type res_type; + uint32_t res_id; + struct cam_isp_tfe_in_port_info *in_port; + struct cam_isp_tfe_out_port_info *out_port; + enum cam_isp_hw_sync_mode sync_mode; + uint32_t master_idx; + uint32_t phy_sel; + void *event_cb_prv; + cam_hw_mgr_event_cb_func event_cb; + struct cam_isp_resource_node *node_res; +}; + +/** + * enum cam_tfe_csid_halt_cmd - Specify the halt command type + */ +enum cam_tfe_csid_halt_cmd { + CAM_TFE_CSID_HALT_AT_FRAME_BOUNDARY, + CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY, + CAM_TFE_CSID_HALT_IMMEDIATELY, + CAM_TFE_CSID_HALT_MAX, +}; + +/** + * struct cam_csid_hw_stop- stop all resources + * @stop_cmd : Applicable only for PATH resources + * if stop command set to Halt immediately,driver will stop + * path immediately, manager need to reset the path after HI + * if stop command set to halt at frame boundary, driver will set + * halt at frame boundary and wait for frame boundary + * @num_res : Number of resources to be stopped + * @node_res : Reource pointer array( ie cid or CSID) + * + */ +struct cam_tfe_csid_hw_stop_args { + enum cam_tfe_csid_halt_cmd stop_cmd; + uint32_t num_res; + struct cam_isp_resource_node **node_res; +}; + +/** + * enum cam_tfe_csid_reset_type - Specify the reset type + */ +enum cam_tfe_csid_reset_type { + CAM_TFE_CSID_RESET_GLOBAL, + CAM_TFE_CSID_RESET_PATH, + CAM_TFE_CSID_RESET_MAX, +}; + +/** + * struct cam_tfe_csid_reset_cfg- Csid reset configuration + * @ reset_type : Global reset or path reset + * @res_node : Resource need to be reset + * + */ +struct cam_tfe_csid_reset_cfg_args { + enum cam_tfe_csid_reset_type reset_type; + struct cam_isp_resource_node *node_res; +}; + +/** + * struct cam_csid_get_time_stamp_args- time stamp capture arguments + * @res_node : Resource to get the time stamp + * @time_stamp_val : Captured time stamp + * @boot_timestamp : Boot time stamp + */ +struct cam_tfe_csid_get_time_stamp_args { + struct cam_isp_resource_node *node_res; + uint64_t time_stamp_val; + uint64_t boot_timestamp; +}; + +/** + * enum cam_tfe_csid_cmd_type - Specify the csid command + */ +enum cam_tfe_csid_cmd_type { + CAM_TFE_CSID_CMD_GET_TIME_STAMP, + CAM_TFE_CSID_SET_CSID_DEBUG, + CAM_TFE_CSID_SOF_IRQ_DEBUG, + CAM_TFE_CSID_CMD_GET_REG_DUMP, + CAM_TFE_CSID_CMD_MAX, +}; + +/** + * cam_tfe_csid_hw_init() + * + * @brief: Initialize function for the CSID hardware + * + * @tfe_csid_hw: CSID hardware instance returned + * @hw_idex: CSID hardware instance id + */ +int cam_tfe_csid_hw_init(struct cam_hw_intf **tfe_csid_hw, + uint32_t hw_idx); + +/* + * struct cam_tfe_csid_clock_update_args: + * + * @clk_rate: Clock rate requested + */ +struct cam_tfe_csid_clock_update_args { + uint64_t clk_rate; +}; + + +#endif /* _CAM_TFE_CSID_HW_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_hw_intf.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..0678a89d026422ff16cdaa31bd47cbb34a12e8b8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_hw_intf.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_HW_INTF_H_ +#define _CAM_TFE_HW_INTF_H_ + +#include "cam_isp_hw.h" +#include "cam_cpas_api.h" + +#define CAM_TFE_HW_NUM_MAX 3 +#define TFE_CORE_BASE_IDX 0 + + +enum cam_isp_hw_tfe_in { + CAM_ISP_HW_TFE_IN_CAMIF = 0, + CAM_ISP_HW_TFE_IN_RDI0 = 1, + CAM_ISP_HW_TFE_IN_RDI1 = 2, + CAM_ISP_HW_TFE_IN_RDI2 = 3, + CAM_ISP_HW_TFE_IN_MAX, +}; + +enum cam_isp_hw_tfe_core { + CAM_ISP_HW_TFE_CORE_0, + CAM_ISP_HW_TFE_CORE_1, + CAM_ISP_HW_TFE_CORE_2, + CAM_ISP_HW_TFE_CORE_MAX, +}; + +enum cam_tfe_hw_irq_status { + CAM_TFE_IRQ_STATUS_SUCCESS, + CAM_TFE_IRQ_STATUS_ERR, + CAM_TFE_IRQ_STATUS_OVERFLOW, + CAM_TFE_IRQ_STATUS_P2I_ERROR, + CAM_TFE_IRQ_STATUS_VIOLATION, + CAM_TFE_IRQ_STATUS_MAX, +}; + +enum cam_tfe_hw_irq_regs { + CAM_TFE_IRQ_CAMIF_REG_STATUS0 = 0, + CAM_TFE_IRQ_CAMIF_REG_STATUS1 = 1, + CAM_TFE_IRQ_CAMIF_REG_STATUS2 = 2, + CAM_TFE_IRQ_REGISTERS_MAX, +}; + +enum cam_tfe_bus_irq_regs { + CAM_TFE_IRQ_BUS_REG_STATUS0 = 0, + CAM_TFE_IRQ_BUS_REG_STATUS1 = 1, + CAM_TFE_BUS_IRQ_REGISTERS_MAX, +}; + +enum cam_tfe_reset_type { + CAM_TFE_HW_RESET_HW_AND_REG, + CAM_TFE_HW_RESET_HW, + CAM_TFE_HW_RESET_MAX, +}; + +enum cam_tfe_bw_control_action { + CAM_TFE_BW_CONTROL_EXCLUDE = 0, + CAM_TFE_BW_CONTROL_INCLUDE = 1 +}; + +/* + * struct cam_tfe_hw_get_hw_cap: + * + * @max_width: Max width supported by HW + * @max_height: Max height supported by HW + * @max_pixel_num: Max Pixel channels available + * @max_rdi_num: Max Raw channels available + */ +struct cam_tfe_hw_get_hw_cap { + uint32_t max_width; + uint32_t max_height; + uint32_t max_pixel_num; + uint32_t max_rdi_num; +}; + +/* + * struct cam_tfe_hw_tfe_out_acquire_args: + * + * @rsrc_node: Pointer to Resource Node object, filled if acquire + * is successful + * @out_port_info: Output Port details to acquire + * @unique_id: Unique Identity of Context to associate with this + * resource. Used for composite grouping of multiple + * resources in the same context + * @is_dual: Dual TFE or not + * @split_id: In case of Dual TFE, this is Left or Right. + * (Default is Left if Single TFE) + * @is_master: In case of Dual TFE, this is Master or Slave. + * (Default is Master in case of Single TFE) + * @cdm_ops: CDM operations + * @ctx: Context data + */ +struct cam_tfe_hw_tfe_out_acquire_args { + struct cam_isp_resource_node *rsrc_node; + struct cam_isp_tfe_out_port_info *out_port_info; + uint32_t unique_id; + uint32_t is_dual; + enum cam_isp_hw_split_id split_id; + uint32_t is_master; + struct cam_cdm_utils_ops *cdm_ops; + void *ctx; +}; + +/* + * struct cam_tfe_hw_tfe_in_acquire_args: + * + * @rsrc_node: Pointer to Resource Node object, filled if acquire + * is successful + * @res_id: Resource ID of resource to acquire if specific, + * else CAM_ISP_HW_TFE_IN_MAX + * @cdm_ops: CDM operations + * @sync_mode: In case of Dual TFE, this is Master or Slave. + * (Default is Master in case of Single TFE) + * @in_port: Input port details to acquire + * @camif_pd_enable Camif pd enable or disable + * @dual_tfe_sync_sel_idx Dual tfe master hardware index + */ +struct cam_tfe_hw_tfe_in_acquire_args { + struct cam_isp_resource_node *rsrc_node; + struct cam_isp_tfe_in_port_info *in_port; + uint32_t res_id; + void *cdm_ops; + enum cam_isp_hw_sync_mode sync_mode; + bool camif_pd_enable; + uint32_t dual_tfe_sync_sel_idx; +}; + +/* + * struct cam_tfe_acquire_args: + * + * @rsrc_type: Type of Resource (OUT/IN) to acquire + * @tasklet: Tasklet to associate with this resource. This is + * used to schedule bottom of IRQ events associated + * with this resource. + * @priv: Context data + * @event_cb: Callback function to hw mgr in case of hw events + * @tfe_out: Acquire args for TFE_OUT + * @tfe_in: Acquire args for TFE_IN + */ +struct cam_tfe_acquire_args { + enum cam_isp_resource_type rsrc_type; + void *tasklet; + void *priv; + cam_hw_mgr_event_cb_func event_cb; + union { + struct cam_tfe_hw_tfe_out_acquire_args tfe_out; + struct cam_tfe_hw_tfe_in_acquire_args tfe_in; + }; +}; + +/* + * struct cam_tfe_clock_update_args: + * + * @node_res: Resource to get the time stamp + * @clk_rate: Clock rate requested + */ +struct cam_tfe_clock_update_args { + struct cam_isp_resource_node *node_res; + uint64_t clk_rate; +}; + +/* + * struct cam_tfe_bw_update_args: + * + * @node_res: Resource to get the BW + * @isp_vote: Vote info according to usage data (left/right/rdi) + */ +struct cam_tfe_bw_update_args { + struct cam_isp_resource_node *node_res; + struct cam_axi_vote isp_vote; +}; + +/* + * struct cam_tfe_dual_update_args: + * + * @Brief: update the dual isp striping configuration. + * + * @ split_id: spilt id to inform left or rifht + * @ res: resource node + * @ stripe_config: stripe configuration for port + * + */ +struct cam_tfe_dual_update_args { + enum cam_isp_hw_split_id split_id; + struct cam_isp_resource_node *res; + struct cam_isp_tfe_dual_stripe_config *stripe_config; +}; + +/* + * struct cam_tfe_bw_control_args: + * + * @node_res: Resource to get the time stamp + * @action: Bandwidth control action + */ +struct cam_tfe_bw_control_args { + struct cam_isp_resource_node *node_res; + enum cam_tfe_bw_control_action action; +}; + +/* + * struct cam_tfe_irq_evt_payload: + * + * @Brief: This structure is used to save payload for IRQ + * related to TFE_TOP resources + * + * @list: list_head node for the payload + * @core_index: Index of TFE HW that generated this IRQ event + * @core_info: Private data of handler in bottom half context + * @evt_id: IRQ event + * @irq_reg_val: IRQ and Error register values, read when IRQ was + * handled + * @bus_irq_val Bus irq register status + * @debug_status_0: Value of debug status_0 register at time of IRQ + * @ccif_violation_status ccif violation status + * @overflow_status bus overflow status + * @image_size_violation_status image size violations status + + * @error_type: Identify different errors + * @enable_reg_dump: enable register dump on error + * @ts: Timestamp + */ +struct cam_tfe_irq_evt_payload { + struct list_head list; + uint32_t core_index; + void *core_info; + uint32_t evt_id; + uint32_t irq_reg_val[CAM_TFE_IRQ_REGISTERS_MAX]; + uint32_t bus_irq_val[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; + uint32_t ccif_violation_status; + uint32_t overflow_status; + uint32_t image_size_violation_status; + uint32_t debug_status_0; + + uint32_t error_type; + bool enable_reg_dump; + struct cam_isp_timestamp ts; +}; + +/* + * cam_tfe_hw_init() + * + * @Brief: Initialize TFE HW device + * + * @tfe_hw: tfe_hw interface to fill in and return on + * successful initialization + * @hw_idx: Index of TFE HW + */ +int cam_tfe_hw_init(struct cam_hw_intf **tfe_hw, uint32_t hw_idx); + +#endif /* _CAM_TFE_HW_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_top_tpg_hw_intf.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_top_tpg_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..224d4bbfb7b7da103faaba38cc9f3ceddddd7007 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_top_tpg_hw_intf.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TOP_TPG_HW_INTF_H_ +#define _CAM_TOP_TPG_HW_INTF_H_ + +#include "cam_isp_hw.h" +#include "cam_hw_intf.h" + +/* Max top tpg instance */ +#define CAM_TOP_TPG_HW_NUM_MAX 2 +/* Max supported number of DT for TPG */ +#define CAM_TOP_TPG_MAX_SUPPORTED_DT 4 +/* TPG default pattern should be color bar */ +#define CAM_TOP_TPG_DEFAULT_PATTERN 0x8 +/** + * enum cam_top_tpg_id - top tpg hw instance id + */ +enum cam_top_tpg_id { + CAM_TOP_TPG_ID_0, + CAM_TOP_TPG_ID_1, + CAM_TFE_TPG_ID_MAX, +}; + +/** + * struct cam_top_tpg_hw_caps- Get the top tpg hw capability + * @major_version : Major version + * @minor_version: Minor version + * @version_incr: Version increment + * + */ +struct cam_top_tpg_hw_caps { + uint32_t major_version; + uint32_t minor_version; + uint32_t version_incr; +}; + +/** + * struct cam_tfe_csid_hw_reserve_resource_args- hw reserve + * @num_inport: number of inport + * TPG support 4 dt types, each different dt comes in different + * in port. + * @in_port : Input port resource info structure pointer + * @node_res : Reserved resource structure pointer + * + */ +struct cam_top_tpg_hw_reserve_resource_args { + uint32_t num_inport; + struct cam_isp_tfe_in_port_info *in_port[CAM_TOP_TPG_MAX_SUPPORTED_DT]; + struct cam_isp_resource_node *node_res; +}; + +/** + * cam_top_tpg_hw_init() + * + * @brief: Initialize function for the tpg hardware + * + * @top_tpg_hw: TPG hardware instance returned + * @hw_idex: TPG hardware instance id + */ +int cam_top_tpg_hw_init(struct cam_hw_intf **top_tpg_hw, + uint32_t hw_idx); + +/* + * struct cam_top_tpg_clock_update_args: + * + * @clk_rate: phy rate requested + */ +struct cam_top_tpg_clock_update_args { + uint64_t clk_rate; +}; + +#endif /* _CAM_TOP_TPG_HW_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..e4f86edaf5e6bac7c98f716953f06724bd02a450 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h @@ -0,0 +1,375 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_HW_INTF_H_ +#define _CAM_VFE_HW_INTF_H_ + +#include "cam_isp_hw.h" +#include "cam_ife_csid_hw_intf.h" +#include "cam_ife_csid_hw_intf.h" +#include "cam_cpas_api.h" + +#define CAM_VFE_HW_NUM_MAX 7 + +#define VFE_CORE_BASE_IDX 0 +/* + * VBIF and BUS do not exist on same HW. + * Hence both can be 1 below. + */ +#define VFE_VBIF_BASE_IDX 1 +#define VFE_BUS_BASE_IDX 1 + +#define CAM_VFE_MAX_UBWC_PORTS 4 + +enum cam_isp_hw_vfe_in_mux { + CAM_ISP_HW_VFE_IN_CAMIF = 0, + CAM_ISP_HW_VFE_IN_TESTGEN = 1, + CAM_ISP_HW_VFE_IN_RD = 2, + CAM_ISP_HW_VFE_IN_RDI0 = 3, + CAM_ISP_HW_VFE_IN_RDI1 = 4, + CAM_ISP_HW_VFE_IN_RDI2 = 5, + CAM_ISP_HW_VFE_IN_RDI3 = 6, + CAM_ISP_HW_VFE_IN_PDLIB = 7, + CAM_ISP_HW_VFE_IN_LCR = 8, + CAM_ISP_HW_VFE_IN_MAX, +}; + +enum cam_isp_hw_vfe_core { + CAM_ISP_HW_VFE_CORE_0, + CAM_ISP_HW_VFE_CORE_1, + CAM_ISP_HW_VFE_CORE_2, + CAM_ISP_HW_VFE_CORE_3, + CAM_ISP_HW_VFE_CORE_MAX, +}; + +enum cam_vfe_hw_irq_status { + CAM_VFE_IRQ_STATUS_ERR_COMP = -3, + CAM_VFE_IRQ_STATUS_COMP_OWRT = -2, + CAM_VFE_IRQ_STATUS_ERR = -1, + CAM_VFE_IRQ_STATUS_SUCCESS = 0, + CAM_VFE_IRQ_STATUS_OVERFLOW = 1, + CAM_VFE_IRQ_STATUS_P2I_ERROR = 2, + CAM_VFE_IRQ_STATUS_VIOLATION = 3, + CAM_VFE_IRQ_STATUS_MAX, +}; + +enum cam_vfe_hw_irq_regs { + CAM_IFE_IRQ_CAMIF_REG_STATUS0 = 0, + CAM_IFE_IRQ_CAMIF_REG_STATUS1 = 1, + CAM_IFE_IRQ_CAMIF_REG_STATUS2 = 2, + CAM_IFE_IRQ_VIOLATION_STATUS = 3, + CAM_IFE_IRQ_BUS_OVERFLOW_STATUS = 4, + CAM_IFE_IRQ_REGISTERS_MAX, +}; + +enum cam_vfe_bus_irq_regs { + CAM_IFE_IRQ_BUS_REG_STATUS0 = 0, + CAM_IFE_IRQ_BUS_REG_STATUS1 = 1, + CAM_IFE_IRQ_BUS_REG_STATUS2 = 2, + CAM_IFE_IRQ_BUS_REG_COMP_ERR = 3, + CAM_IFE_IRQ_BUS_REG_COMP_OWRT = 4, + CAM_IFE_IRQ_BUS_DUAL_COMP_ERR = 5, + CAM_IFE_IRQ_BUS_DUAL_COMP_OWRT = 6, + CAM_IFE_BUS_IRQ_REGISTERS_MAX, +}; + +enum cam_vfe_bus_ver3_irq_regs { + CAM_IFE_IRQ_BUS_VER3_REG_STATUS0 = 0, + CAM_IFE_IRQ_BUS_VER3_REG_STATUS1 = 1, + CAM_IFE_IRQ_BUS_VER3_REG_MAX, +}; + +enum cam_vfe_reset_type { + CAM_VFE_HW_RESET_HW_AND_REG, + CAM_VFE_HW_RESET_HW, + CAM_VFE_HW_RESET_MAX, +}; + +/* + * struct cam_vfe_hw_get_hw_cap: + * + * @max_width: Max width supported by HW + * @max_height: Max height supported by HW + * @max_pixel_num: Max Pixel channels available + * @max_rdi_num: Max Raw channels available + */ +struct cam_vfe_hw_get_hw_cap { + uint32_t max_width; + uint32_t max_height; + uint32_t max_pixel_num; + uint32_t max_rdi_num; +}; + +/* + * struct cam_vfe_hw_vfe_out_acquire_args: + * + * @rsrc_node: Pointer to Resource Node object, filled if acquire + * is successful + * @out_port_info: Output Port details to acquire + * @unique_id: Unique Identity of Context to associate with this + * resource. Used for composite grouping of multiple + * resources in the same context + * @is_dual: Dual VFE or not + * @split_id: In case of Dual VFE, this is Left or Right. + * (Default is Left if Single VFE) + * @is_master: In case of Dual VFE, this is Master or Slave. + * (Default is Master in case of Single VFE) + * @dual_slave_core: If Master and Slave exists, HW Index of Slave + * @cdm_ops: CDM operations + */ +struct cam_vfe_hw_vfe_out_acquire_args { + struct cam_isp_resource_node *rsrc_node; + struct cam_isp_out_port_generic_info *out_port_info; + uint32_t unique_id; + uint32_t is_dual; + enum cam_isp_hw_split_id split_id; + uint32_t is_master; + uint32_t dual_slave_core; + struct cam_cdm_utils_ops *cdm_ops; +}; + +/* + * struct cam_vfe_hw_vfe_in_acquire_args: + * + * @rsrc_node: Pointer to Resource Node object, filled if acquire + * is successful + * @res_id: Resource ID of resource to acquire if specific, + * else CAM_ISP_HW_VFE_IN_MAX + * @cdm_ops: CDM operations + * @sync_mode: In case of Dual VFE, this is Master or Slave. + * (Default is Master in case of Single VFE) + * @in_port: Input port details to acquire + */ +struct cam_vfe_hw_vfe_in_acquire_args { + struct cam_isp_resource_node *rsrc_node; + uint32_t res_id; + void *cdm_ops; + enum cam_isp_hw_sync_mode sync_mode; + struct cam_isp_in_port_generic_info *in_port; +}; + +/* + * struct cam_vfe_acquire_args: + * + * @rsrc_type: Type of Resource (OUT/IN) to acquire + * @tasklet: Tasklet to associate with this resource. This is + * used to schedule bottom of IRQ events associated + * with this resource. + * @priv: Context data + * @event_cb: Callback function to hw mgr in case of hw events + * @vfe_out: Acquire args for VFE_OUT + * @vfe_bus_rd Acquire args for VFE_BUS_READ + * @vfe_in: Acquire args for VFE_IN + */ +struct cam_vfe_acquire_args { + enum cam_isp_resource_type rsrc_type; + void *tasklet; + void *priv; + cam_hw_mgr_event_cb_func event_cb; + union { + struct cam_vfe_hw_vfe_out_acquire_args vfe_out; + struct cam_vfe_hw_vfe_out_acquire_args vfe_bus_rd; + struct cam_vfe_hw_vfe_in_acquire_args vfe_in; + }; +}; + +/* + * struct cam_vfe_clock_update_args: + * + * @node_res: Resource to get the time stamp + * @clk_rate: Clock rate requested + */ +struct cam_vfe_clock_update_args { + struct cam_isp_resource_node *node_res; + uint64_t clk_rate; +}; + +/* + * struct cam_vfe_core_config_args: + * + * @node_res: Resource to get the time stamp + * @core_config: Core config for IFE + */ +struct cam_vfe_core_config_args { + struct cam_isp_resource_node *node_res; + struct cam_isp_core_config core_config; +}; + +/* + * struct cam_vfe_bw_update_args_v2: + * + * @node_res: Resource to get the BW + * @isp_vote: Vote info according to usage data (left/right/rdi) + */ +struct cam_vfe_bw_update_args_v2 { + struct cam_isp_resource_node *node_res; + struct cam_axi_vote isp_vote; +}; + +/* + * struct cam_vfe_bw_update_args: + * + * @node_res: Resource to get the BW + * @camnoc_bw_bytes: Bandwidth vote request for CAMNOC + * @external_bw_bytes: Bandwidth vote request from CAMNOC + * out to the rest of the path-to-DDR + */ +struct cam_vfe_bw_update_args { + struct cam_isp_resource_node *node_res; + uint64_t camnoc_bw_bytes; + uint64_t external_bw_bytes; +}; + +/* + * struct cam_vfe_fe_update_args: + * + * @node_res: Resource to get fetch configuration + * @fe_config: fetch engine configuration + * + */ +struct cam_vfe_fe_update_args { + struct cam_isp_resource_node *node_res; + struct cam_fe_config fe_config; +}; + +enum cam_vfe_bw_control_action { + CAM_VFE_BW_CONTROL_EXCLUDE = 0, + CAM_VFE_BW_CONTROL_INCLUDE = 1 +}; + +/* + * struct cam_vfe_bw_control_args: + * + * @node_res: Resource to get the time stamp + * @action: Bandwidth control action + */ +struct cam_vfe_bw_control_args { + struct cam_isp_resource_node *node_res; + enum cam_vfe_bw_control_action action; +}; + +/* + * struct cam_vfe_top_irq_evt_payload: + * + * @Brief: This structure is used to save payload for IRQ + * related to VFE_TOP resources + * + * @list: list_head node for the payload + * @irq_reg_val: IRQ and Error register values, read when IRQ was + * handled + * @th_reg_val: Value of any critical register that needs to be + * read at th to avoid any latencies in bh processing + * + * @ts: Timestamp + */ +struct cam_vfe_top_irq_evt_payload { + struct list_head list; + uint32_t irq_reg_val[CAM_IFE_IRQ_REGISTERS_MAX]; + uint32_t th_reg_val; + struct cam_isp_timestamp ts; +}; + +/* + * struct cam_vfe_bus_irq_evt_payload: + * + * @Brief: This structure is used to save payload for IRQ + * related to VFE_BUS resources + * + * @list: list_head node for the payload + * @core_index: Index of VFE HW that generated this IRQ event + * @debug_status_0: Value of debug status_0 register at time of IRQ + * @evt_id: IRQ event + * @irq_reg_val: IRQ and Error register values, read when IRQ was + * handled + * @error_type: Identify different errors + * @ts: Timestamp + */ +struct cam_vfe_bus_irq_evt_payload { + struct list_head list; + uint32_t core_index; + uint32_t debug_status_0; + uint32_t ccif_violation_status; + uint32_t overflow_status; + uint32_t image_size_violation_status; + uint32_t evt_id; + uint32_t irq_reg_val[CAM_IFE_BUS_IRQ_REGISTERS_MAX]; + struct cam_isp_timestamp ts; +}; + +/** + * struct cam_ubwc_generic_plane_config - UBWC Plane configuration info + * + * @port_type: Port Type + * @meta_stride: UBWC metadata stride + * @meta_size: UBWC metadata plane size + * @meta_offset: UBWC metadata offset + * @packer_config: UBWC packer config + * @mode_config: UBWC mode config + * @static ctrl: UBWC static ctrl + * @ctrl_2: UBWC ctrl 2 + * @tile_config: UBWC tile config + * @h_init: UBWC horizontal initial coordinate in pixels + * @v_init: UBWC vertical initial coordinate in lines + * @stats_ctrl_2: UBWC stats control + * @lossy_threshold0 UBWC lossy threshold 0 + * @lossy_threshold1 UBWC lossy threshold 1 + * @lossy_var_offset UBWC offset variance threshold + * @bandwidth limit UBWC bandwidth limit + */ +struct cam_vfe_generic_ubwc_plane_config { + uint32_t port_type; + uint32_t meta_stride; + uint32_t meta_size; + uint32_t meta_offset; + uint32_t packer_config; + uint32_t mode_config_0; + uint32_t mode_config_1; + uint32_t tile_config; + uint32_t h_init; + uint32_t v_init; + uint32_t static_ctrl; + uint32_t ctrl_2; + uint32_t stats_ctrl_2; + uint32_t lossy_threshold_0; + uint32_t lossy_threshold_1; + uint32_t lossy_var_offset; + uint32_t bandwidth_limit; +}; + +/** + * struct cam_ubwc_generic_config - UBWC Configuration Payload + * + * @api_version: UBWC config api version + * @ubwc_plane_config: Array of UBWC configurations per plane + */ +struct cam_vfe_generic_ubwc_config { + uint32_t api_version; + struct cam_vfe_generic_ubwc_plane_config + ubwc_plane_cfg[CAM_PACKET_MAX_PLANES - 1]; +}; + +/* + * cam_vfe_hw_init() + * + * @Brief: Initialize VFE HW device + * + * @vfe_hw: vfe_hw interface to fill in and return on + * successful initialization + * @hw_idx: Index of VFE HW + */ +int cam_vfe_hw_init(struct cam_hw_intf **vfe_hw, uint32_t hw_idx); + +/* + * cam_vfe_put_evt_payload() + * + * @Brief: Put the evt payload back to free list + * + * @core_info: VFE HW core_info + * @evt_payload: Event payload data + */ +int cam_vfe_put_evt_payload(void *core_info, + struct cam_vfe_top_irq_evt_payload **evt_payload); + +#endif /* _CAM_VFE_HW_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..3f26c013b5c4b283346dbc3bcc927a9f5f80e7a7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_csid_ppi_dev.o cam_csid_ppi_core.o cam_csid_ppi100.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.c new file mode 100644 index 0000000000000000000000000000000000000000..7b2f449f277f7d255e89fc2c553ec93408a79369 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_csid_ppi_core.h" +#include "cam_csid_ppi100.h" +#include "cam_csid_ppi_dev.h" + +#define CAM_PPI_DRV_NAME "ppi_100" +#define CAM_PPI_VERSION_V100 0x10000000 + +static struct cam_csid_ppi_hw_info cam_csid_ppi100_hw_info = { + .ppi_reg = &cam_csid_ppi_100_reg_offset, +}; + +static const struct of_device_id cam_csid_ppi100_dt_match[] = { + { + .compatible = "qcom,ppi100", + .data = &cam_csid_ppi100_hw_info, + }, + {} +}; + +MODULE_DEVICE_TABLE(of, cam_csid_ppi100_dt_match); + +static struct platform_driver cam_csid_ppi100_driver = { + .probe = cam_csid_ppi_probe, + .remove = cam_csid_ppi_remove, + .driver = { + .name = CAM_PPI_DRV_NAME, + .of_match_table = cam_csid_ppi100_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_csid_ppi100_init_module(void) +{ + return platform_driver_register(&cam_csid_ppi100_driver); +} + +static void __exit cam_csid_ppi100_exit_module(void) +{ + platform_driver_unregister(&cam_csid_ppi100_driver); +} + +module_init(cam_csid_ppi100_init_module); +MODULE_DESCRIPTION("CAM CSID_PPI100 driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.h new file mode 100644 index 0000000000000000000000000000000000000000..8aee24c13aef1e9c3dd71e4a8c59a7200369cd12 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSID_PPI_100_H_ +#define _CAM_CSID_PPI_100_H_ + +#include "cam_csid_ppi_core.h" + +static struct cam_csid_ppi_reg_offset cam_csid_ppi_100_reg_offset = { + .ppi_hw_version_addr = 0, + .ppi_module_cfg_addr = 0x60, + .ppi_irq_status_addr = 0x68, + .ppi_irq_mask_addr = 0x6c, + .ppi_irq_set_addr = 0x70, + .ppi_irq_clear_addr = 0x74, + .ppi_irq_cmd_addr = 0x78, + .ppi_rst_cmd_addr = 0x7c, + .ppi_test_bus_ctrl_addr = 0x1f4, + .ppi_debug_addr = 0x1f8, + .ppi_spare_addr = 0x1fc, +}; + +#endif /*_CAM_CSID_PPI_100_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c new file mode 100644 index 0000000000000000000000000000000000000000..63bd4e9a9b6fc987bc2a9de8459587f582a76baf --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include + +#include "cam_csid_ppi_core.h" +#include "cam_csid_ppi_dev.h" +#include "cam_soc_util.h" +#include "cam_debug_util.h" +#include "cam_io_util.h" + +static int cam_csid_ppi_reset(struct cam_csid_ppi_hw *ppi_hw) +{ + struct cam_hw_soc_info *soc_info; + const struct cam_csid_ppi_reg_offset *ppi_reg; + int rc = 0; + uint32_t status; + + soc_info = &ppi_hw->hw_info->soc_info; + ppi_reg = ppi_hw->ppi_info->ppi_reg; + + CAM_DBG(CAM_ISP, "PPI:%d reset", ppi_hw->hw_intf->hw_idx); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_mask_addr); + cam_io_w_mb(PPI_RST_CONTROL, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_set_addr); + cam_io_w_mb(PPI_RST_CONTROL, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_rst_cmd_addr); + cam_io_w_mb(PPI_IRQ_CMD_SET, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_cmd_addr); + + rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_status_addr, status, + (status & 0x1) == 0x1, 1000, 500000); + CAM_DBG(CAM_ISP, "PPI:%d reset status %d", ppi_hw->hw_intf->hw_idx, + status); + if (rc < 0) { + CAM_ERR(CAM_ISP, "PPI:%d ppi_reset fail rc = %d status = %d", + ppi_hw->hw_intf->hw_idx, rc, status); + return rc; + } + cam_io_w_mb(PPI_RST_CONTROL, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_clear_addr); + cam_io_w_mb(PPI_IRQ_CMD_CLEAR, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_cmd_addr); + + return 0; +} + +static int cam_csid_ppi_enable_hw(struct cam_csid_ppi_hw *ppi_hw) +{ + int rc = 0; + int32_t i; + uint64_t val; + const struct cam_csid_ppi_reg_offset *ppi_reg; + struct cam_hw_soc_info *soc_info; + uint32_t err_irq_mask; + + ppi_reg = ppi_hw->ppi_info->ppi_reg; + soc_info = &ppi_hw->hw_info->soc_info; + + CAM_DBG(CAM_ISP, "PPI:%d init PPI HW", ppi_hw->hw_intf->hw_idx); + + ppi_hw->hw_info->open_count++; + if (ppi_hw->hw_info->open_count > 1) { + CAM_DBG(CAM_ISP, "PPI:%d dual vfe already enabled", + ppi_hw->hw_intf->hw_idx); + return 0; + } + + for (i = 0; i < soc_info->num_clk; i++) { + rc = cam_soc_util_clk_enable(soc_info->clk[i], + soc_info->clk_name[i], 0); + if (rc) + goto clk_disable; + } + + rc = cam_csid_ppi_reset(ppi_hw); + if (rc) + goto clk_disable; + + err_irq_mask = PPI_IRQ_FIFO0_OVERFLOW | PPI_IRQ_FIFO1_OVERFLOW | + PPI_IRQ_FIFO2_OVERFLOW; + cam_io_w_mb(err_irq_mask, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_mask_addr); + rc = cam_soc_util_irq_enable(soc_info); + if (rc) + goto clk_disable; + + cam_io_w_mb(PPI_RST_CONTROL, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_clear_addr); + cam_io_w_mb(PPI_IRQ_CMD_CLEAR, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_cmd_addr); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + ppi_reg->ppi_hw_version_addr); + CAM_DBG(CAM_ISP, "PPI:%d PPI HW version: 0x%x", + ppi_hw->hw_intf->hw_idx, val); + ppi_hw->device_enabled = 1; + + return 0; +clk_disable: + for (--i; i >= 0; i--) + cam_soc_util_clk_disable(soc_info->clk[i], + soc_info->clk_name[i]); + ppi_hw->hw_info->open_count--; + return rc; +} + +static int cam_csid_ppi_disable_hw(struct cam_csid_ppi_hw *ppi_hw) +{ + int rc = 0; + int i; + struct cam_hw_soc_info *soc_info; + const struct cam_csid_ppi_reg_offset *ppi_reg; + uint64_t ppi_cfg_val = 0; + + CAM_DBG(CAM_ISP, "PPI:%d De-init PPI HW", + ppi_hw->hw_intf->hw_idx); + + if (!ppi_hw->hw_info->open_count) { + CAM_WARN(CAM_ISP, "ppi[%d] unbalanced disable hw", + ppi_hw->hw_intf->hw_idx); + return -EINVAL; + } + ppi_hw->hw_info->open_count--; + + if (ppi_hw->hw_info->open_count) + return rc; + + soc_info = &ppi_hw->hw_info->soc_info; + ppi_reg = ppi_hw->ppi_info->ppi_reg; + + CAM_DBG(CAM_ISP, "Calling PPI Reset"); + cam_csid_ppi_reset(ppi_hw); + CAM_DBG(CAM_ISP, "PPI Reset Done"); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_mask_addr); + cam_soc_util_irq_disable(soc_info); + + for (i = 0; i < CAM_CSID_PPI_LANES_MAX; i++) + ppi_cfg_val &= ~PPI_CFG_CPHY_DLX_EN(i); + + cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_module_cfg_addr); + + ppi_hw->device_enabled = 0; + + for (i = 0; i < soc_info->num_clk; i++) + cam_soc_util_clk_disable(soc_info->clk[i], + soc_info->clk_name[i]); + + return rc; +} + +static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args, + uint32_t arg_size) +{ + int i, rc = 0; + uint32_t num_lanes; + uint32_t cphy; + uint32_t ppi_cfg_val = 0; + struct cam_csid_ppi_hw *ppi_hw; + struct cam_hw_info *ppi_hw_info; + const struct cam_csid_ppi_reg_offset *ppi_reg; + struct cam_hw_soc_info *soc_info; + struct cam_csid_ppi_cfg ppi_cfg; + + if (!hw_priv || !init_args || + (arg_size != sizeof(struct cam_csid_ppi_cfg))) { + CAM_ERR(CAM_ISP, "PPI: Invalid args"); + rc = -EINVAL; + goto end; + } + + ppi_hw_info = (struct cam_hw_info *)hw_priv; + ppi_hw = (struct cam_csid_ppi_hw *)ppi_hw_info->core_info; + ppi_reg = ppi_hw->ppi_info->ppi_reg; + ppi_cfg = *((struct cam_csid_ppi_cfg *)init_args); + + rc = cam_csid_ppi_enable_hw(ppi_hw); + if (rc) + goto end; + + num_lanes = ppi_cfg.lane_num; + cphy = ppi_cfg.lane_type; + CAM_DBG(CAM_ISP, "lane_cfg 0x%x | num_lanes 0x%x | lane_type 0x%x", + ppi_cfg.lane_cfg, num_lanes, cphy); + + if (cphy) { + ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(0); + ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(1); + } else { + ppi_cfg_val = 0; + } + + for (i = 0; i < CAM_CSID_PPI_LANES_MAX; i++) + ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(i); + + CAM_DBG(CAM_ISP, "ppi_cfg_val 0x%x", ppi_cfg_val); + soc_info = &ppi_hw->hw_info->soc_info; + cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_module_cfg_addr); + + CAM_DBG(CAM_ISP, "ppi cfg 0x%x", + cam_io_r_mb(soc_info->reg_map[0].mem_base + + ppi_reg->ppi_module_cfg_addr)); +end: + return rc; +} + +static int cam_csid_ppi_deinit_hw(void *hw_priv, void *deinit_args, + uint32_t arg_size) +{ + int rc = 0; + struct cam_csid_ppi_hw *ppi_hw; + struct cam_hw_info *ppi_hw_info; + + CAM_DBG(CAM_ISP, "Enter"); + + if (!hw_priv) { + CAM_ERR(CAM_ISP, "PPI:Invalid arguments"); + rc = -EINVAL; + goto end; + } + + ppi_hw_info = (struct cam_hw_info *)hw_priv; + ppi_hw = (struct cam_csid_ppi_hw *)ppi_hw_info->core_info; + + CAM_DBG(CAM_ISP, "Disabling PPI Hw"); + rc = cam_csid_ppi_disable_hw(ppi_hw); + if (rc < 0) + CAM_DBG(CAM_ISP, "Exit with %d", rc); +end: + return rc; +} + +int cam_csid_ppi_hw_probe_init(struct cam_hw_intf *ppi_hw_intf, + uint32_t ppi_idx) +{ + int rc = -EINVAL; + struct cam_hw_info *ppi_hw_info; + struct cam_csid_ppi_hw *csid_ppi_hw = NULL; + + if (ppi_idx >= CAM_CSID_PPI_HW_MAX) { + CAM_ERR(CAM_ISP, "Invalid ppi index:%d", ppi_idx); + goto err; + } + + ppi_hw_info = (struct cam_hw_info *) ppi_hw_intf->hw_priv; + csid_ppi_hw = (struct cam_csid_ppi_hw *) ppi_hw_info->core_info; + + csid_ppi_hw->hw_intf = ppi_hw_intf; + csid_ppi_hw->hw_info = ppi_hw_info; + + CAM_DBG(CAM_ISP, "type %d index %d", + csid_ppi_hw->hw_intf->hw_type, ppi_idx); + + rc = cam_csid_ppi_init_soc_resources(&csid_ppi_hw->hw_info->soc_info, + cam_csid_ppi_irq, csid_ppi_hw); + if (rc < 0) { + CAM_ERR(CAM_ISP, "PPI:%d Failed to init_soc", ppi_idx); + goto err; + } + + csid_ppi_hw->hw_intf->hw_ops.init = cam_csid_ppi_init_hw; + csid_ppi_hw->hw_intf->hw_ops.deinit = cam_csid_ppi_deinit_hw; + return 0; +err: + return rc; +} + +int cam_csid_ppi_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t ppi_irq_handler, void *irq_data) +{ + int rc = 0; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc) { + CAM_ERR(CAM_ISP, "PPI: Failed to get dt properties"); + goto end; + } + + rc = cam_soc_util_request_platform_resource(soc_info, ppi_irq_handler, + irq_data); + if (rc) { + CAM_ERR(CAM_ISP, + "PPI: Error Request platform resources failed rc=%d", + rc); + goto err; + } +end: + return rc; +err: + cam_soc_util_release_platform_resource(soc_info); + return rc; +} + +irqreturn_t cam_csid_ppi_irq(int irq_num, void *data) +{ + uint32_t irq_status = 0; + uint32_t i, ppi_cfg_val = 0; + bool fatal_err_detected = false; + + struct cam_csid_ppi_hw *ppi_hw; + struct cam_hw_soc_info *soc_info; + const struct cam_csid_ppi_reg_offset *ppi_reg; + + if (!data) { + CAM_ERR(CAM_ISP, "PPI: Invalid arguments"); + return IRQ_HANDLED; + } + + ppi_hw = (struct cam_csid_ppi_hw *)data; + ppi_reg = ppi_hw->ppi_info->ppi_reg; + soc_info = &ppi_hw->hw_info->soc_info; + + if (ppi_hw->device_enabled != 1) + goto ret; + + irq_status = cam_io_r_mb(soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_status_addr); + + cam_io_w_mb(irq_status, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_clear_addr); + + cam_io_w_mb(PPI_IRQ_CMD_CLEAR, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_cmd_addr); + + CAM_DBG(CAM_ISP, "PPI %d irq status 0x%x", ppi_hw->hw_intf->hw_idx, + irq_status); + + if (irq_status & PPI_IRQ_RST_DONE) { + CAM_DBG(CAM_ISP, "PPI Reset Done"); + goto ret; + } + if ((irq_status & PPI_IRQ_FIFO0_OVERFLOW) || + (irq_status & PPI_IRQ_FIFO1_OVERFLOW) || + (irq_status & PPI_IRQ_FIFO2_OVERFLOW)) { + fatal_err_detected = true; + goto handle_fatal_error; + } + +handle_fatal_error: + if (fatal_err_detected) { + CAM_ERR(CAM_ISP, "PPI: %d irq_status:0x%x", + ppi_hw->hw_intf->hw_idx, irq_status); + for (i = 0; i < CAM_CSID_PPI_LANES_MAX; i++) + ppi_cfg_val &= ~PPI_CFG_CPHY_DLX_EN(i); + + cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_module_cfg_addr); + } +ret: + CAM_DBG(CAM_ISP, "IRQ Handling exit"); + return IRQ_HANDLED; +} + +int cam_csid_ppi_hw_deinit(struct cam_csid_ppi_hw *csid_ppi_hw) +{ + if (!csid_ppi_hw) { + CAM_ERR(CAM_ISP, "Invalid param"); + return -EINVAL; + } + return cam_soc_util_release_platform_resource( + &csid_ppi_hw->hw_info->soc_info); +} + + diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h new file mode 100644 index 0000000000000000000000000000000000000000..777c4e3fb5731a83f0d90414ce4a5a0372c5bff0 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSID_PPI_HW_H_ +#define _CAM_CSID_PPI_HW_H_ + +#include "cam_hw.h" +#include "cam_hw_intf.h" + +#define CAM_CSID_PPI_HW_MAX 4 +#define CAM_CSID_PPI_LANES_MAX 3 + +#define PPI_IRQ_RST_DONE BIT(0) +#define PPI_IRQ_FIFO0_OVERFLOW BIT(1) +#define PPI_IRQ_FIFO1_OVERFLOW BIT(2) +#define PPI_IRQ_FIFO2_OVERFLOW BIT(3) + +#define PPI_IRQ_CMD_SET BIT(1) + +#define PPI_IRQ_CMD_CLEAR BIT(0) + +#define PPI_RST_CONTROL BIT(0) +/* + * Select the PHY (CPHY set '1' or DPHY set '0') + */ +#define PPI_CFG_CPHY_DLX_SEL(X) BIT(X) + +#define PPI_CFG_CPHY_DLX_EN(X) BIT(4+X) + +struct cam_csid_ppi_reg_offset { + uint32_t ppi_hw_version_addr; + uint32_t ppi_module_cfg_addr; + + uint32_t ppi_irq_status_addr; + uint32_t ppi_irq_mask_addr; + uint32_t ppi_irq_set_addr; + uint32_t ppi_irq_clear_addr; + uint32_t ppi_irq_cmd_addr; + uint32_t ppi_rst_cmd_addr; + uint32_t ppi_test_bus_ctrl_addr; + uint32_t ppi_debug_addr; + uint32_t ppi_spare_addr; +}; + +/** + * struct cam_csid_ppi_hw_info- ppi HW info + * + * @ppi_reg: ppi register offsets + * + */ +struct cam_csid_ppi_hw_info { + const struct cam_csid_ppi_reg_offset *ppi_reg; +}; + +/** + * struct cam_csid_ppi_hw- ppi hw device resources data + * + * @hw_intf: contain the ppi hw interface information + * @hw_info: ppi hw device information + * @ppi_info: ppi hw specific information + * @device_enabled Device enabled will set once ppi powered on and + * initial configuration are done. + * + */ +struct cam_csid_ppi_hw { + struct cam_hw_intf *hw_intf; + struct cam_hw_info *hw_info; + struct cam_csid_ppi_hw_info *ppi_info; + uint32_t device_enabled; +}; + +/** + * struct cam_csid_ppi_cfg - ppi lane configuration data + * @lane_type: lane type: c-phy or d-phy + * @lane_num : active lane number + * @lane_cfg: lane configurations: 4 bits per lane + * + */ +struct cam_csid_ppi_cfg { + uint32_t lane_type; + uint32_t lane_num; + uint32_t lane_cfg; +}; + +int cam_csid_ppi_hw_probe_init(struct cam_hw_intf *ppi_hw_intf, + uint32_t ppi_idx); +int cam_csid_ppi_hw_deinit(struct cam_csid_ppi_hw *csid_ppi_hw); +int cam_csid_ppi_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t ppi_irq_handler, void *irq_data); +int cam_csid_ppi_deinit_soc_resources(struct cam_hw_soc_info *soc_info); +int cam_csid_ppi_hw_init(struct cam_hw_intf **csid_ppi_hw, + uint32_t hw_idx); +#endif /* _CAM_CSID_PPI_HW_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..1467815d5e654ad1ed79f9ea7db0c1c9b95d91d7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "cam_isp_hw.h" +#include "cam_hw_intf.h" +#include "cam_csid_ppi_core.h" +#include "cam_csid_ppi_dev.h" +#include "cam_debug_util.h" + +static struct cam_hw_intf *cam_csid_ppi_hw_list[CAM_CSID_PPI_HW_MAX] = { + NULL, NULL, NULL, NULL}; +static char ppi_dev_name[8]; + +int cam_csid_ppi_probe(struct platform_device *pdev) +{ + struct cam_hw_intf *ppi_hw_intf; + struct cam_hw_info *ppi_hw_info; + struct cam_csid_ppi_hw *ppi_dev = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_csid_ppi_hw_info *ppi_hw_data = NULL; + uint32_t ppi_dev_idx; + int rc = 0; + + CAM_DBG(CAM_ISP, "PPI probe called"); + + ppi_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!ppi_hw_intf) { + rc = -ENOMEM; + goto err; + } + + ppi_hw_info = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!ppi_hw_info) { + rc = -ENOMEM; + goto free_hw_intf; + } + + ppi_dev = kzalloc(sizeof(struct cam_csid_ppi_hw), GFP_KERNEL); + if (!ppi_dev) { + rc = -ENOMEM; + goto free_hw_info; + } + + of_property_read_u32(pdev->dev.of_node, "cell-index", &ppi_dev_idx); + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_ISP, "No matching table for the CSID PPI HW!"); + rc = -EINVAL; + goto free_dev; + } + + memset(ppi_dev_name, 0, sizeof(ppi_dev_name)); + snprintf(ppi_dev_name, sizeof(ppi_dev_name), "ppi%1u", ppi_dev_idx); + + ppi_hw_intf->hw_idx = ppi_dev_idx; + ppi_hw_intf->hw_priv = ppi_hw_info; + + if (ppi_hw_intf->hw_idx < CAM_CSID_PPI_HW_MAX) + cam_csid_ppi_hw_list[ppi_hw_intf->hw_idx] = ppi_hw_intf; + else { + rc = -EINVAL; + goto free_dev; + } + + ppi_hw_info->core_info = ppi_dev; + ppi_hw_info->soc_info.pdev = pdev; + ppi_hw_info->soc_info.dev = &pdev->dev; + ppi_hw_info->soc_info.dev_name = ppi_dev_name; + ppi_hw_info->soc_info.index = ppi_dev_idx; + + ppi_hw_data = (struct cam_csid_ppi_hw_info *)match_dev->data; + ppi_dev->ppi_info = ppi_hw_data; + + rc = cam_csid_ppi_hw_probe_init(ppi_hw_intf, ppi_dev_idx); + if (rc) { + CAM_ERR(CAM_ISP, "PPI: Probe init failed!"); + goto free_dev; + } + + platform_set_drvdata(pdev, ppi_dev); + CAM_DBG(CAM_ISP, "PPI:%d probe successful", + ppi_hw_intf->hw_idx); + + return 0; +free_dev: + kfree(ppi_dev); +free_hw_info: + kfree(ppi_hw_info); +free_hw_intf: + kfree(ppi_hw_intf); +err: + return rc; +} + +int cam_csid_ppi_remove(struct platform_device *pdev) +{ + struct cam_csid_ppi_hw *ppi_dev = NULL; + struct cam_hw_intf *ppi_hw_intf; + struct cam_hw_info *ppi_hw_info; + + ppi_dev = (struct cam_csid_ppi_hw *)platform_get_drvdata(pdev); + ppi_hw_intf = ppi_dev->hw_intf; + ppi_hw_info = ppi_dev->hw_info; + + CAM_DBG(CAM_ISP, "PPI:%d remove", ppi_dev->hw_intf->hw_idx); + + cam_csid_ppi_hw_deinit(ppi_dev); + + kfree(ppi_dev); + kfree(ppi_hw_info); + kfree(ppi_hw_intf); + + return 0; +} + +int cam_csid_ppi_hw_init(struct cam_hw_intf **csid_ppi_hw, + uint32_t hw_idx) +{ + int rc = 0; + + if (cam_csid_ppi_hw_list[hw_idx]) { + *csid_ppi_hw = cam_csid_ppi_hw_list[hw_idx]; + } else { + *csid_ppi_hw = NULL; + rc = -1; + } + + return rc; +} +EXPORT_SYMBOL(cam_csid_ppi_hw_init); diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..2992c224373239b8bc477367da816b74e8391146 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSID_PPI_DEV_H_ +#define _CAM_CSID_PPI_DEV_H_ + +#include "cam_isp_hw.h" + +irqreturn_t cam_csid_ppi_irq(int irq_num, void *data); +int cam_csid_ppi_probe(struct platform_device *pdev); +int cam_csid_ppi_remove(struct platform_device *pdev); + +#endif /*_CAM_CSID_PPI_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..e238cfc0cb73a735f467224499a423d593b373f5 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_tfe_csid_dev.o cam_tfe_csid_soc.o cam_tfe_csid_core.o +obj-$(CONFIG_SPECTRA_CAMERA) += cam_tfe_csid530.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.c new file mode 100644 index 0000000000000000000000000000000000000000..488431771b2af6c542d36e3b799ee5a2b21125ce --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + + +#include +#include "cam_tfe_csid_core.h" +#include "cam_tfe_csid530.h" +#include "cam_tfe_csid_dev.h" + +#define CAM_TFE_CSID_DRV_NAME "csid_530" +#define CAM_TFE_CSID_VERSION_V530 0x50030000 + +static struct cam_tfe_csid_hw_info cam_tfe_csid530_hw_info = { + .csid_reg = &cam_tfe_csid_530_reg_offset, + .hw_dts_version = CAM_TFE_CSID_VERSION_V530, +}; + +static const struct of_device_id cam_tfe_csid530_dt_match[] = { + { + .compatible = "qcom,csid530", + .data = &cam_tfe_csid530_hw_info, + }, + {} +}; + +MODULE_DEVICE_TABLE(of, cam_tfe_csid530_dt_match); + +static struct platform_driver cam_tfe_csid530_driver = { + .probe = cam_tfe_csid_probe, + .remove = cam_tfe_csid_remove, + .driver = { + .name = CAM_TFE_CSID_DRV_NAME, + .of_match_table = cam_tfe_csid530_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_tfe_csid530_init_module(void) +{ + return platform_driver_register(&cam_tfe_csid530_driver); +} + +static void __exit cam_tfe_csid530_exit_module(void) +{ + platform_driver_unregister(&cam_tfe_csid530_driver); +} + +module_init(cam_tfe_csid530_init_module); +module_exit(cam_tfe_csid530_exit_module); +MODULE_DESCRIPTION("CAM TFE_CSID530 driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h new file mode 100644 index 0000000000000000000000000000000000000000..634c359173969d7071140e3ad32d1f0dc7d6c221 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_CSID_530_H_ +#define _CAM_TFE_CSID_530_H_ + +#include "cam_tfe_csid_core.h" + +static struct cam_tfe_csid_pxl_reg_offset cam_tfe_csid_530_ipp_reg_offset = { + .csid_pxl_irq_status_addr = 0x30, + .csid_pxl_irq_mask_addr = 0x34, + .csid_pxl_irq_clear_addr = 0x38, + .csid_pxl_irq_set_addr = 0x3c, + + .csid_pxl_cfg0_addr = 0x200, + .csid_pxl_cfg1_addr = 0x204, + .csid_pxl_ctrl_addr = 0x208, + .csid_pxl_hcrop_addr = 0x21c, + .csid_pxl_vcrop_addr = 0x220, + .csid_pxl_rst_strobes_addr = 0x240, + .csid_pxl_status_addr = 0x254, + .csid_pxl_misr_val_addr = 0x258, + .csid_pxl_timestamp_curr0_sof_addr = 0x290, + .csid_pxl_timestamp_curr1_sof_addr = 0x294, + .csid_pxl_timestamp_perv0_sof_addr = 0x298, + .csid_pxl_timestamp_perv1_sof_addr = 0x29c, + .csid_pxl_timestamp_curr0_eof_addr = 0x2a0, + .csid_pxl_timestamp_curr1_eof_addr = 0x2a4, + .csid_pxl_timestamp_perv0_eof_addr = 0x2a8, + .csid_pxl_timestamp_perv1_eof_addr = 0x2ac, + .csid_pxl_err_recovery_cfg0_addr = 0x2d0, + .csid_pxl_err_recovery_cfg1_addr = 0x2d4, + .csid_pxl_err_recovery_cfg2_addr = 0x2d8, + /* configurations */ + .pix_store_en_shift_val = 7, + .early_eof_en_shift_val = 29, + .halt_master_sel_shift = 4, + .halt_mode_shift = 2, + .halt_master_sel_master_val = 3, + .halt_master_sel_slave_val = 0, +}; + +static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_530_rdi_0_reg_offset = { + .csid_rdi_irq_status_addr = 0x40, + .csid_rdi_irq_mask_addr = 0x44, + .csid_rdi_irq_clear_addr = 0x48, + .csid_rdi_irq_set_addr = 0x4c, + + .csid_rdi_cfg0_addr = 0x300, + .csid_rdi_cfg1_addr = 0x304, + .csid_rdi_ctrl_addr = 0x308, + .csid_rdi_rst_strobes_addr = 0x340, + .csid_rdi_status_addr = 0x350, + .csid_rdi_misr_val0_addr = 0x354, + .csid_rdi_misr_val1_addr = 0x358, + .csid_rdi_timestamp_curr0_sof_addr = 0x390, + .csid_rdi_timestamp_curr1_sof_addr = 0x394, + .csid_rdi_timestamp_prev0_sof_addr = 0x398, + .csid_rdi_timestamp_prev1_sof_addr = 0x39c, + .csid_rdi_timestamp_curr0_eof_addr = 0x3a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x3a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x3a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x3ac, + .csid_rdi_err_recovery_cfg0_addr = 0x3b0, + .csid_rdi_err_recovery_cfg1_addr = 0x3b4, + .csid_rdi_err_recovery_cfg2_addr = 0x3b8, + .csid_rdi_byte_cntr_ping_addr = 0x3e0, + .csid_rdi_byte_cntr_pong_addr = 0x3e4, +}; + +static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_530_rdi_1_reg_offset = { + .csid_rdi_irq_status_addr = 0x50, + .csid_rdi_irq_mask_addr = 0x54, + .csid_rdi_irq_clear_addr = 0x58, + .csid_rdi_irq_set_addr = 0x5c, + + .csid_rdi_cfg0_addr = 0x400, + .csid_rdi_cfg1_addr = 0x404, + .csid_rdi_ctrl_addr = 0x408, + .csid_rdi_rst_strobes_addr = 0x440, + .csid_rdi_status_addr = 0x450, + .csid_rdi_misr_val0_addr = 0x454, + .csid_rdi_misr_val1_addr = 0x458, + .csid_rdi_timestamp_curr0_sof_addr = 0x490, + .csid_rdi_timestamp_curr1_sof_addr = 0x494, + .csid_rdi_timestamp_prev0_sof_addr = 0x498, + .csid_rdi_timestamp_prev1_sof_addr = 0x49c, + .csid_rdi_timestamp_curr0_eof_addr = 0x4a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x4a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x4a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x4ac, + .csid_rdi_err_recovery_cfg0_addr = 0x4b0, + .csid_rdi_err_recovery_cfg1_addr = 0x4b4, + .csid_rdi_err_recovery_cfg2_addr = 0x4b8, + .csid_rdi_byte_cntr_ping_addr = 0x4e0, + .csid_rdi_byte_cntr_pong_addr = 0x4e4, +}; + +static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_530_rdi_2_reg_offset = { + .csid_rdi_irq_status_addr = 0x60, + .csid_rdi_irq_mask_addr = 0x64, + .csid_rdi_irq_clear_addr = 0x68, + .csid_rdi_irq_set_addr = 0x6c, + + .csid_rdi_cfg0_addr = 0x500, + .csid_rdi_cfg1_addr = 0x504, + .csid_rdi_ctrl_addr = 0x508, + .csid_rdi_rst_strobes_addr = 0x540, + .csid_rdi_status_addr = 0x550, + .csid_rdi_misr_val0_addr = 0x554, + .csid_rdi_misr_val1_addr = 0x558, + .csid_rdi_timestamp_curr0_sof_addr = 0x590, + .csid_rdi_timestamp_curr1_sof_addr = 0x594, + .csid_rdi_timestamp_prev0_sof_addr = 0x598, + .csid_rdi_timestamp_prev1_sof_addr = 0x59c, + .csid_rdi_timestamp_curr0_eof_addr = 0x5a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x5a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x5a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x5ac, + .csid_rdi_err_recovery_cfg0_addr = 0x5b0, + .csid_rdi_err_recovery_cfg1_addr = 0x5b4, + .csid_rdi_err_recovery_cfg2_addr = 0x5b8, + .csid_rdi_byte_cntr_ping_addr = 0x5e0, + .csid_rdi_byte_cntr_pong_addr = 0x5e4, +}; + +static struct cam_tfe_csid_csi2_rx_reg_offset + cam_tfe_csid_530_csi2_reg_offset = { + .csid_csi2_rx_irq_status_addr = 0x20, + .csid_csi2_rx_irq_mask_addr = 0x24, + .csid_csi2_rx_irq_clear_addr = 0x28, + .csid_csi2_rx_irq_set_addr = 0x2c, + + /*CSI2 rx control */ + .phy_sel_base = 1, + .csid_csi2_rx_cfg0_addr = 0x100, + .csid_csi2_rx_cfg1_addr = 0x104, + .csid_csi2_rx_capture_ctrl_addr = 0x108, + .csid_csi2_rx_rst_strobes_addr = 0x110, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, + .csid_csi2_rx_captured_short_pkt_0_addr = 0x128, + .csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, + .csid_csi2_rx_captured_long_pkt_0_addr = 0x130, + .csid_csi2_rx_captured_long_pkt_1_addr = 0x134, + .csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, + .csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, + .csid_csi2_rx_total_pkts_rcvd_addr = 0x160, + .csid_csi2_rx_stats_ecc_addr = 0x164, + .csid_csi2_rx_total_crc_err_addr = 0x168, + + .csi2_rst_srb_all = 0x3FFF, + .csi2_rst_done_shift_val = 27, + .csi2_irq_mask_all = 0xFFFFFFF, + .csi2_misr_enable_shift_val = 6, + .csi2_capture_long_pkt_en_shift = 0, + .csi2_capture_short_pkt_en_shift = 1, + .csi2_capture_cphy_pkt_en_shift = 2, + .csi2_capture_long_pkt_dt_shift = 4, + .csi2_capture_long_pkt_vc_shift = 10, + .csi2_capture_short_pkt_vc_shift = 12, + .csi2_capture_cphy_pkt_dt_shift = 14, + .csi2_capture_cphy_pkt_vc_shift = 20, + .csi2_rx_phy_num_mask = 0x3, + .csi2_rx_long_pkt_hdr_rst_stb_shift = 0x1, + .csi2_rx_short_pkt_hdr_rst_stb_shift = 0x2, +}; + +static struct cam_tfe_csid_common_reg_offset + cam_tfe_csid_530_cmn_reg_offset = { + .csid_hw_version_addr = 0x0, + .csid_cfg0_addr = 0x4, + .csid_ctrl_addr = 0x8, + .csid_rst_strobes_addr = 0x10, + + .csid_test_bus_ctrl_addr = 0x14, + .csid_top_irq_status_addr = 0x70, + .csid_top_irq_mask_addr = 0x74, + .csid_top_irq_clear_addr = 0x78, + .csid_top_irq_set_addr = 0x7c, + .csid_irq_cmd_addr = 0x80, + + /*configurations */ + .major_version = 5, + .minor_version = 3, + .version_incr = 0, + .num_rdis = 3, + .num_pix = 1, + .csid_reg_rst_stb = 1, + .csid_rst_stb = 0x1e, + .csid_rst_stb_sw_all = 0x1f, + .ipp_path_rst_stb_all = 0x17, + .rdi_path_rst_stb_all = 0x97, + .path_rst_done_shift_val = 1, + .path_en_shift_val = 31, + .dt_id_shift_val = 27, + .vc_shift_val = 22, + .dt_shift_val = 16, + .fmt_shift_val = 12, + .plain_fmt_shit_val = 10, + .crop_v_en_shift_val = 6, + .crop_h_en_shift_val = 5, + .crop_shift = 16, + .ipp_irq_mask_all = 0x3FFFF, + .rdi_irq_mask_all = 0x3FFFF, + .top_tfe2_pix_pipe_fuse_reg = 0xFE4, + .top_tfe2_fuse_reg = 0xFE8, +}; + +static struct cam_tfe_csid_reg_offset cam_tfe_csid_530_reg_offset = { + .cmn_reg = &cam_tfe_csid_530_cmn_reg_offset, + .csi2_reg = &cam_tfe_csid_530_csi2_reg_offset, + .ipp_reg = &cam_tfe_csid_530_ipp_reg_offset, + .rdi_reg = { + &cam_tfe_csid_530_rdi_0_reg_offset, + &cam_tfe_csid_530_rdi_1_reg_offset, + &cam_tfe_csid_530_rdi_2_reg_offset, + }, +}; + +#endif /*_CAM_TFE_CSID_530_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c new file mode 100644 index 0000000000000000000000000000000000000000..510ba0f382fb4061e88ee9db172d06a96da0adcf --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -0,0 +1,3308 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "cam_tfe_csid_core.h" +#include "cam_csid_ppi_core.h" +#include "cam_isp_hw.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" +#include "cam_isp_hw_mgr_intf.h" +#include +#include "cam_subdev.h" +#include "cam_tasklet_util.h" + +/* Timeout value in msec */ +#define TFE_CSID_TIMEOUT 1000 + +/* Timeout values in usec */ +#define CAM_TFE_CSID_TIMEOUT_SLEEP_US 1000 +#define CAM_TFE_CSID_TIMEOUT_ALL_US 100000 + +/* + * Constant Factors needed to change QTimer ticks to nanoseconds + * QTimer Freq = 19.2 MHz + * Time(us) = ticks/19.2 + * Time(ns) = ticks/19.2 * 1000 + */ +#define CAM_TFE_CSID_QTIMER_MUL_FACTOR 10000 +#define CAM_TFE_CSID_QTIMER_DIV_FACTOR 192 + +/* Max number of sof irq's triggered in case of SOF freeze */ +#define CAM_TFE_CSID_IRQ_SOF_DEBUG_CNT_MAX 12 + +/* Max CSI Rx irq error count threshold value */ +#define CAM_TFE_CSID_MAX_IRQ_ERROR_COUNT 5 + +static int cam_tfe_csid_is_ipp_format_supported( + uint32_t in_format) +{ + int rc = -EINVAL; + + switch (in_format) { + case CAM_FORMAT_MIPI_RAW_6: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + rc = 0; + break; + default: + break; + } + return rc; +} + +static int cam_tfe_csid_get_format_rdi( + uint32_t in_format, uint32_t out_format, + uint32_t *decode_fmt, uint32_t *plain_fmt) +{ + int rc = 0; + + switch (in_format) { + case CAM_FORMAT_MIPI_RAW_6: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_6: + *decode_fmt = 0xf; + break; + case CAM_FORMAT_PLAIN8: + *decode_fmt = 0x0; + *plain_fmt = 0x0; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_8: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_PLAIN128: + *decode_fmt = 0xf; + break; + case CAM_FORMAT_PLAIN8: + *decode_fmt = 0x1; + *plain_fmt = 0x0; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_10: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_PLAIN128: + *decode_fmt = 0xf; + break; + case CAM_FORMAT_PLAIN16_10: + *decode_fmt = 0x2; + *plain_fmt = 0x1; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_12: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_12: + *decode_fmt = 0xf; + break; + case CAM_FORMAT_PLAIN16_12: + *decode_fmt = 0x3; + *plain_fmt = 0x1; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_14: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_14: + *decode_fmt = 0xf; + break; + case CAM_FORMAT_PLAIN16_14: + *decode_fmt = 0x4; + *plain_fmt = 0x1; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_16: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_16: + *decode_fmt = 0xf; + break; + case CAM_FORMAT_PLAIN16_16: + *decode_fmt = 0x5; + *plain_fmt = 0x1; + break; + default: + rc = -EINVAL; + break; + } + break; + default: + rc = -EINVAL; + break; + } + + if (rc) + CAM_ERR(CAM_ISP, "Unsupported format pair in %d out %d", + in_format, out_format); + + return rc; +} + +static int cam_tfe_csid_get_format_ipp( + uint32_t in_format, + uint32_t *decode_fmt, uint32_t *plain_fmt) +{ + int rc = 0; + + CAM_DBG(CAM_ISP, "input format:%d", + in_format); + + switch (in_format) { + case CAM_FORMAT_MIPI_RAW_6: + *decode_fmt = 0; + *plain_fmt = 0; + break; + case CAM_FORMAT_MIPI_RAW_8: + *decode_fmt = 0x1; + *plain_fmt = 0; + break; + case CAM_FORMAT_MIPI_RAW_10: + *decode_fmt = 0x2; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_MIPI_RAW_12: + *decode_fmt = 0x3; + *plain_fmt = 0x1; + break; + default: + CAM_ERR(CAM_ISP, "Unsupported format %d", + in_format); + rc = -EINVAL; + } + + CAM_DBG(CAM_ISP, "decode_fmt:%d plain_fmt:%d", + *decode_fmt, *plain_fmt); + + return rc; +} + +static int cam_tfe_csid_cid_get(struct cam_tfe_csid_hw *csid_hw, + int32_t vc, uint32_t dt, uint32_t *cid) +{ + uint32_t i = 0; + + /* Return already reserved CID if the VC/DT matches */ + for (i = 0; i < CAM_TFE_CSID_CID_MAX; i++) { + if (csid_hw->cid_res[i].cnt >= 1) { + if (csid_hw->cid_res[i].vc == vc && + csid_hw->cid_res[i].dt == dt) { + csid_hw->cid_res[i].cnt++; + *cid = i; + CAM_DBG(CAM_ISP, "CSID:%d CID %d allocated", + csid_hw->hw_intf->hw_idx, i); + return 0; + } + } + } + + for (i = 0; i < CAM_TFE_CSID_CID_MAX; i++) { + if (!csid_hw->cid_res[i].cnt) { + csid_hw->cid_res[i].vc = vc; + csid_hw->cid_res[i].dt = dt; + csid_hw->cid_res[i].cnt = 1; + *cid = i; + CAM_DBG(CAM_ISP, "CSID:%d CID %d allocated", + csid_hw->hw_intf->hw_idx, i); + return 0; + } + } + + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d Free cid is not available", + csid_hw->hw_intf->hw_idx); + /* Dump CID values */ + for (i = 0; i < CAM_TFE_CSID_CID_MAX; i++) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CID:%d vc:%d dt:%d cnt:%d", + csid_hw->hw_intf->hw_idx, i, csid_hw->cid_res[i].vc, + csid_hw->cid_res[i].dt, csid_hw->cid_res[i].cnt); + } + return -EINVAL; +} + +static int cam_tfe_csid_global_reset(struct cam_tfe_csid_hw *csid_hw) +{ + struct cam_hw_soc_info *soc_info; + const struct cam_tfe_csid_reg_offset *csid_reg; + int rc = 0; + uint32_t val = 0, i; + uint32_t status; + + soc_info = &csid_hw->hw_info->soc_info; + csid_reg = csid_hw->csid_info->csid_reg; + + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid HW State:%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "CSID:%d Csid reset", csid_hw->hw_intf->hw_idx); + + /* Mask all interrupts */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_mask_addr); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + + if (csid_hw->pxl_pipe_enable) + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); + + /* clear all interrupts */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + + cam_io_w_mb(csid_reg->csi2_reg->csi2_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); + + if (csid_hw->pxl_pipe_enable) + cam_io_w_mb(csid_reg->cmn_reg->ipp_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_clear_addr); + + for (i = 0 ; i < csid_reg->cmn_reg->num_rdis; i++) + cam_io_w_mb(csid_reg->cmn_reg->rdi_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr); + + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + cam_io_w_mb(0x80, soc_info->reg_map[0].mem_base + + csid_hw->csid_info->csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + + /* perform the top CSID HW registers reset */ + cam_io_w_mb(csid_reg->cmn_reg->csid_rst_stb, + soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_rst_strobes_addr); + + rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_status_addr, + status, (status & 0x1) == 0x1, + CAM_TFE_CSID_TIMEOUT_SLEEP_US, CAM_TFE_CSID_TIMEOUT_ALL_US); + if (rc < 0) { + CAM_ERR(CAM_ISP, "CSID:%d csid_reset fail rc = %d", + csid_hw->hw_intf->hw_idx, rc); + rc = -ETIMEDOUT; + } + + status = cam_io_r(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_status_addr); + CAM_DBG(CAM_ISP, "Status reg %d", status); + + /* perform the SW registers reset */ + reinit_completion(&csid_hw->csid_top_complete); + cam_io_w_mb(csid_reg->cmn_reg->csid_reg_rst_stb, + soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_rst_strobes_addr); + + rc = wait_for_completion_timeout(&csid_hw->csid_top_complete, + msecs_to_jiffies(TFE_CSID_TIMEOUT)); + if (rc <= 0) { + CAM_ERR(CAM_ISP, "CSID:%d soft reg reset fail rc = %d", + csid_hw->hw_intf->hw_idx, rc); + if (rc == 0) + rc = -ETIMEDOUT; + } else + rc = 0; + + usleep_range(3000, 3010); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + if (val != 0) + CAM_ERR(CAM_ISP, "CSID:%d IRQ value after reset rc = %d", + csid_hw->hw_intf->hw_idx, val); + csid_hw->error_irq_count = 0; + csid_hw->prev_boot_timestamp = 0; + + return rc; +} + +static int cam_tfe_csid_path_reset(struct cam_tfe_csid_hw *csid_hw, + struct cam_tfe_csid_reset_cfg_args *reset) +{ + int rc = 0; + struct cam_hw_soc_info *soc_info; + struct cam_isp_resource_node *res; + const struct cam_tfe_csid_reg_offset *csid_reg; + uint32_t reset_strb_addr, reset_strb_val, val, id; + struct completion *complete; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + res = reset->node_res; + + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid hw state :%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + return -EINVAL; + } + + if (res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res id%d", + csid_hw->hw_intf->hw_idx, res->res_id); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ISP, "CSID:%d resource:%d", + csid_hw->hw_intf->hw_idx, res->res_id); + + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) { + if (!csid_reg->ipp_reg) { + CAM_ERR(CAM_ISP, "CSID:%d IPP not supported :%d", + csid_hw->hw_intf->hw_idx, + res->res_id); + return -EINVAL; + } + + reset_strb_addr = csid_reg->ipp_reg->csid_pxl_rst_strobes_addr; + complete = &csid_hw->csid_ipp_complete; + reset_strb_val = csid_reg->cmn_reg->ipp_path_rst_stb_all; + + /* Enable path reset done interrupt */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + val |= TFE_CSID_PATH_INFO_RST_DONE; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + } else { + id = res->res_id; + if (!csid_reg->rdi_reg[id]) { + CAM_ERR(CAM_ISP, "CSID:%d RDI res not supported :%d", + csid_hw->hw_intf->hw_idx, + res->res_id); + return -EINVAL; + } + + reset_strb_addr = + csid_reg->rdi_reg[id]->csid_rdi_rst_strobes_addr; + complete = + &csid_hw->csid_rdin_complete[id]; + reset_strb_val = csid_reg->cmn_reg->rdi_path_rst_stb_all; + + /* Enable path reset done interrupt */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); + val |= TFE_CSID_PATH_INFO_RST_DONE; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); + } + + reinit_completion(complete); + + /* Reset the corresponding tfe csid path */ + cam_io_w_mb(reset_strb_val, soc_info->reg_map[0].mem_base + + reset_strb_addr); + + rc = wait_for_completion_timeout(complete, + msecs_to_jiffies(TFE_CSID_TIMEOUT)); + if (rc <= 0) { + CAM_ERR(CAM_ISP, "CSID:%d Res id %d fail rc = %d", + csid_hw->hw_intf->hw_idx, + res->res_id, rc); + if (rc == 0) + rc = -ETIMEDOUT; + } + +end: + return rc; +} + +static int cam_tfe_csid_cid_reserve(struct cam_tfe_csid_hw *csid_hw, + struct cam_tfe_csid_hw_reserve_resource_args *cid_reserv, + uint32_t *cid_value) +{ + int rc = 0; + + CAM_DBG(CAM_ISP, + "CSID:%d res_id:0x%x Lane type:%d lane_num:%d dt:%d vc:%d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->res_id, + cid_reserv->in_port->lane_type, + cid_reserv->in_port->lane_num, + cid_reserv->in_port->dt, + cid_reserv->in_port->vc); + + if (cid_reserv->in_port->res_id >= CAM_ISP_TFE_IN_RES_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid phy sel %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->res_id); + rc = -EINVAL; + goto end; + } + + if (cid_reserv->in_port->lane_type >= CAM_ISP_LANE_TYPE_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid lane type %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->lane_type); + rc = -EINVAL; + goto end; + } + + if ((cid_reserv->in_port->lane_type == CAM_ISP_LANE_TYPE_DPHY && + cid_reserv->in_port->lane_num > 4)) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid lane num %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->lane_num); + rc = -EINVAL; + goto end; + } + + if (cid_reserv->in_port->lane_type == CAM_ISP_LANE_TYPE_CPHY && + cid_reserv->in_port->lane_num > 3) { + CAM_ERR(CAM_ISP, " CSID:%d Invalid lane type %d & num %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->lane_type, + cid_reserv->in_port->lane_num); + rc = -EINVAL; + goto end; + } + + /* CSID CSI2 v1.1 supports 4 vc */ + if (cid_reserv->in_port->dt > 0x3f || + cid_reserv->in_port->vc > 0x3) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid vc:%d dt %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->vc, cid_reserv->in_port->dt); + rc = -EINVAL; + goto end; + } + + if (csid_hw->csi2_reserve_cnt == UINT_MAX) { + CAM_ERR(CAM_ISP, + "CSID%d reserve cnt reached max", + csid_hw->hw_intf->hw_idx); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ISP, "Reserve_cnt %u", csid_hw->csi2_reserve_cnt); + + if (csid_hw->csi2_reserve_cnt) { + /* current configure res type should match requested res type */ + if (csid_hw->in_res_id != cid_reserv->in_port->res_id) { + rc = -EINVAL; + goto end; + } + + if (csid_hw->csi2_rx_cfg.lane_cfg != + cid_reserv->in_port->lane_cfg || + csid_hw->csi2_rx_cfg.lane_type != + cid_reserv->in_port->lane_type || + csid_hw->csi2_rx_cfg.lane_num != + cid_reserv->in_port->lane_num) { + rc = -EINVAL; + goto end; + } + } + + rc = cam_tfe_csid_cid_get(csid_hw, + cid_reserv->in_port->vc, + cid_reserv->in_port->dt, + cid_value); + if (rc) { + CAM_ERR(CAM_ISP, "CSID:%d CID Reserve failed res_id %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->res_id); + goto end; + } + + if (!csid_hw->csi2_reserve_cnt) { + csid_hw->in_res_id = cid_reserv->in_port->res_id; + + csid_hw->csi2_rx_cfg.lane_cfg = + cid_reserv->in_port->lane_cfg; + csid_hw->csi2_rx_cfg.lane_type = + cid_reserv->in_port->lane_type; + csid_hw->csi2_rx_cfg.lane_num = + cid_reserv->in_port->lane_num; + + if (cid_reserv->in_port->res_id != CAM_ISP_TFE_IN_RES_TPG) + csid_hw->csi2_rx_cfg.phy_sel = + (cid_reserv->in_port->res_id & 0xFF) - 1; + else + csid_hw->csi2_rx_cfg.phy_sel = + (cid_reserv->phy_sel & 0xFF) - 1; + } + + csid_hw->csi2_reserve_cnt++; + CAM_DBG(CAM_ISP, "CSID:%d CID:%d acquired reserv cnt:%d", + csid_hw->hw_intf->hw_idx, *cid_value, + csid_hw->csi2_reserve_cnt); + +end: + return rc; +} + +static int cam_tfe_csid_path_reserve(struct cam_tfe_csid_hw *csid_hw, + struct cam_tfe_csid_hw_reserve_resource_args *reserve) +{ + int rc = 0; + struct cam_tfe_csid_path_cfg *path_data; + struct cam_isp_resource_node *res; + uint32_t cid_value; + + /* CSID CSI2 v2.0 supports 4 vc */ + if (reserve->in_port->dt > 0x3f || reserve->in_port->vc > 0x3 || + (reserve->sync_mode >= CAM_ISP_HW_SYNC_MAX)) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid vc:%d dt %d mode:%d", + csid_hw->hw_intf->hw_idx, + reserve->in_port->vc, reserve->in_port->dt, + reserve->sync_mode); + rc = -EINVAL; + goto end; + } + + switch (reserve->res_id) { + case CAM_TFE_CSID_PATH_RES_IPP: + if (csid_hw->ipp_res.res_state != + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_DBG(CAM_ISP, + "CSID:%d IPP resource not available %d", + csid_hw->hw_intf->hw_idx, + csid_hw->ipp_res.res_state); + rc = -EINVAL; + goto end; + } + + if (cam_tfe_csid_is_ipp_format_supported( + reserve->in_port->format)) { + CAM_ERR(CAM_ISP, + "CSID:%d res id:%d un support format %d", + csid_hw->hw_intf->hw_idx, reserve->res_id, + reserve->in_port->format); + rc = -EINVAL; + goto end; + } + rc = cam_tfe_csid_cid_reserve(csid_hw, reserve, &cid_value); + if (rc) + goto end; + + /* assign the IPP resource */ + res = &csid_hw->ipp_res; + CAM_DBG(CAM_ISP, + "CSID:%d IPP resource:%d acquired successfully", + csid_hw->hw_intf->hw_idx, res->res_id); + + break; + + case CAM_TFE_CSID_PATH_RES_RDI_0: + case CAM_TFE_CSID_PATH_RES_RDI_1: + case CAM_TFE_CSID_PATH_RES_RDI_2: + if (csid_hw->rdi_res[reserve->res_id].res_state != + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, + "CSID:%d RDI:%d resource not available %d", + csid_hw->hw_intf->hw_idx, + reserve->res_id, + csid_hw->rdi_res[reserve->res_id].res_state); + rc = -EINVAL; + goto end; + } + + rc = cam_tfe_csid_cid_reserve(csid_hw, reserve, &cid_value); + if (rc) + goto end; + + res = &csid_hw->rdi_res[reserve->res_id]; + CAM_DBG(CAM_ISP, + "CSID:%d RDI resource:%d acquire success", + csid_hw->hw_intf->hw_idx, + res->res_id); + + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid res id:%d", + csid_hw->hw_intf->hw_idx, reserve->res_id); + rc = -EINVAL; + goto end; + } + + res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + path_data = (struct cam_tfe_csid_path_cfg *)res->res_priv; + + CAM_DBG(CAM_ISP, "sensor width:%d height:%d fps:%d vbi:%d hbi:%d", + reserve->in_port->sensor_width, + reserve->in_port->sensor_height, + reserve->in_port->sensor_fps, + reserve->in_port->sensor_vbi, + reserve->in_port->sensor_hbi); + path_data->sensor_width = reserve->in_port->sensor_width; + path_data->sensor_height = reserve->in_port->sensor_height; + path_data->sensor_fps = reserve->in_port->sensor_fps; + path_data->sensor_hbi = reserve->in_port->sensor_vbi; + path_data->sensor_vbi = reserve->in_port->sensor_hbi; + + path_data->cid = cid_value; + path_data->in_format = reserve->in_port->format; + path_data->out_format = reserve->out_port->format; + path_data->sync_mode = reserve->sync_mode; + path_data->height = reserve->in_port->height; + path_data->start_line = reserve->in_port->line_start; + path_data->end_line = reserve->in_port->line_end; + + csid_hw->event_cb = reserve->event_cb; + csid_hw->event_cb_priv = reserve->event_cb_prv; + + /* Enable crop only for ipp */ + if (reserve->res_id == CAM_TFE_CSID_PATH_RES_IPP) + path_data->crop_enable = true; + + CAM_DBG(CAM_ISP, + "Res id: %d height:%d line_start %d line_end %d crop_en %d", + reserve->res_id, reserve->in_port->height, + reserve->in_port->line_start, reserve->in_port->line_end, + path_data->crop_enable); + + path_data->dt = reserve->in_port->dt; + path_data->vc = reserve->in_port->vc; + + if (reserve->sync_mode == CAM_ISP_HW_SYNC_MASTER) { + path_data->start_pixel = reserve->in_port->left_start; + path_data->end_pixel = reserve->in_port->left_end; + path_data->width = reserve->in_port->left_width; + CAM_DBG(CAM_ISP, "CSID:%d master:startpixel 0x%x endpixel:0x%x", + csid_hw->hw_intf->hw_idx, path_data->start_pixel, + path_data->end_pixel); + CAM_DBG(CAM_ISP, "CSID:%d master:line start:0x%x line end:0x%x", + csid_hw->hw_intf->hw_idx, path_data->start_line, + path_data->end_line); + } else if (reserve->sync_mode == CAM_ISP_HW_SYNC_SLAVE) { + path_data->master_idx = reserve->master_idx; + CAM_DBG(CAM_ISP, "CSID:%d master_idx=%d", + csid_hw->hw_intf->hw_idx, path_data->master_idx); + path_data->start_pixel = reserve->in_port->right_start; + path_data->end_pixel = reserve->in_port->right_end; + path_data->width = reserve->in_port->right_width; + CAM_DBG(CAM_ISP, "CSID:%d slave:start:0x%x end:0x%x width 0x%x", + csid_hw->hw_intf->hw_idx, path_data->start_pixel, + path_data->end_pixel, path_data->width); + CAM_DBG(CAM_ISP, "CSID:%d slave:line start:0x%x line end:0x%x", + csid_hw->hw_intf->hw_idx, path_data->start_line, + path_data->end_line); + } else { + path_data->width = reserve->in_port->left_width; + path_data->start_pixel = reserve->in_port->left_start; + path_data->end_pixel = reserve->in_port->left_end; + CAM_DBG(CAM_ISP, "Res id: %d left width %d start: %d stop:%d", + reserve->res_id, reserve->in_port->left_width, + reserve->in_port->left_start, + reserve->in_port->left_end); + } + + CAM_DBG(CAM_ISP, "Res %d width %d height %d", reserve->res_id, + path_data->width, path_data->height); + reserve->node_res = res; + +end: + return rc; +} + +static int cam_tfe_csid_enable_csi2( + struct cam_tfe_csid_hw *csid_hw) +{ + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + struct cam_csid_ppi_cfg ppi_lane_cfg; + uint32_t ppi_index = 0, rc; + uint32_t val = 0; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + CAM_DBG(CAM_ISP, "CSID:%d config csi2 rx", + csid_hw->hw_intf->hw_idx); + + /* rx cfg0 */ + val = 0; + val = (csid_hw->csi2_rx_cfg.lane_num - 1) | + (csid_hw->csi2_rx_cfg.lane_cfg << 4) | + (csid_hw->csi2_rx_cfg.lane_type << 24); + val |= (csid_hw->csi2_rx_cfg.phy_sel & + csid_reg->csi2_reg->csi2_rx_phy_num_mask) << 20; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg0_addr); + + /* rx cfg1 */ + val = (1 << csid_reg->csi2_reg->csi2_misr_enable_shift_val); + + /* enable packet ecc correction */ + val |= 1; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + + /* Enable the CSI2 rx inerrupts */ + val = TFE_CSID_CSI2_RX_INFO_RST_DONE | + TFE_CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW | + TFE_CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW | + TFE_CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW | + TFE_CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW | + TFE_CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION | + TFE_CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION | + TFE_CSID_CSI2_RX_ERROR_CRC | + TFE_CSID_CSI2_RX_ERROR_ECC | + TFE_CSID_CSI2_RX_ERROR_MMAPPED_VC_DT | + TFE_CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW | + TFE_CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME | + TFE_CSID_CSI2_RX_ERROR_CPHY_PH_CRC; + + /* Enable the interrupt based on csid debug info set */ + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOT_IRQ) + val |= TFE_CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED | + TFE_CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED | + TFE_CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED | + TFE_CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED; + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOT_IRQ) + val |= TFE_CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED | + TFE_CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED | + TFE_CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED | + TFE_CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED; + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) + val |= TFE_CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED; + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) + val |= TFE_CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED; + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) + val |= TFE_CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + /* + * There is one to one mapping for ppi index with phy index + * we do not always update phy sel equal to phy number,for some + * targets "phy_sel = phy_num + 1", and for some targets it is + * "phy_sel = phy_num", ppi_index should be updated accordingly + */ + ppi_index = csid_hw->csi2_rx_cfg.phy_sel - + csid_reg->csi2_reg->phy_sel_base; + + if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) { + ppi_lane_cfg.lane_type = csid_hw->csi2_rx_cfg.lane_type; + ppi_lane_cfg.lane_num = csid_hw->csi2_rx_cfg.lane_num; + ppi_lane_cfg.lane_cfg = csid_hw->csi2_rx_cfg.lane_cfg; + + CAM_DBG(CAM_ISP, "ppi_index to init %d", ppi_index); + rc = csid_hw->ppi_hw_intf[ppi_index]->hw_ops.init( + csid_hw->ppi_hw_intf[ppi_index]->hw_priv, + &ppi_lane_cfg, + sizeof(struct cam_csid_ppi_cfg)); + if (rc < 0) { + CAM_ERR(CAM_ISP, "PPI:%d Init Failed", ppi_index); + return rc; + } + } + + return 0; +} + +static int cam_tfe_csid_disable_csi2( + struct cam_tfe_csid_hw *csid_hw) +{ + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t ppi_index = 0, rc; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + CAM_DBG(CAM_ISP, "CSID:%d Disable csi2 rx", + csid_hw->hw_intf->hw_idx); + + /* Disable the CSI2 rx inerrupts */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + + /* Reset the Rx CFG registers */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg0_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + + ppi_index = csid_hw->csi2_rx_cfg.phy_sel - + csid_reg->csi2_reg->phy_sel_base; + if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) { + /* De-Initialize the PPI bridge */ + CAM_DBG(CAM_ISP, "ppi_index to de-init %d\n", ppi_index); + rc = csid_hw->ppi_hw_intf[ppi_index]->hw_ops.deinit( + csid_hw->ppi_hw_intf[ppi_index]->hw_priv, + NULL, 0); + if (rc < 0) { + CAM_ERR(CAM_ISP, "PPI:%d De-Init Failed", ppi_index); + return rc; + } + } + + return 0; +} + +static int cam_tfe_csid_enable_hw(struct cam_tfe_csid_hw *csid_hw) +{ + int rc = 0; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t i, val, clk_lvl; + unsigned long flags; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + /* overflow check before increment */ + if (csid_hw->hw_info->open_count == UINT_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Open count reached max", + csid_hw->hw_intf->hw_idx); + return -EINVAL; + } + + /* Increment ref Count */ + csid_hw->hw_info->open_count++; + if (csid_hw->hw_info->open_count > 1) { + CAM_DBG(CAM_ISP, "CSID hw has already been enabled"); + return rc; + } + + CAM_DBG(CAM_ISP, "CSID:%d init CSID HW", + csid_hw->hw_intf->hw_idx); + + rc = cam_soc_util_get_clk_level(soc_info, csid_hw->clk_rate, + soc_info->src_clk_idx, &clk_lvl); + CAM_DBG(CAM_ISP, "CSID clock lvl %u", clk_lvl); + + rc = cam_tfe_csid_enable_soc_resources(soc_info, clk_lvl); + if (rc) { + CAM_ERR(CAM_ISP, "CSID:%d Enable SOC failed", + csid_hw->hw_intf->hw_idx); + goto err; + } + + csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_UP; + /* Disable the top IRQ interrupt */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_mask_addr); + /* Reset CSID top */ + rc = cam_tfe_csid_global_reset(csid_hw); + if (rc) + goto disable_soc; + + /* clear all interrupts */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + + cam_io_w_mb(csid_reg->csi2_reg->csi2_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); + + if (csid_hw->pxl_pipe_enable) + cam_io_w_mb(csid_reg->cmn_reg->ipp_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_clear_addr); + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) + cam_io_w_mb(csid_reg->cmn_reg->rdi_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr); + + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_hw_version_addr); + CAM_DBG(CAM_ISP, "CSID:%d CSID HW version: 0x%x", + csid_hw->hw_intf->hw_idx, val); + + /* enable the csi2 rx */ + rc = cam_tfe_csid_enable_csi2(csid_hw); + if (rc) + goto disable_soc; + + spin_lock_irqsave(&csid_hw->spin_lock, flags); + csid_hw->fatal_err_detected = false; + csid_hw->device_enabled = 1; + spin_unlock_irqrestore(&csid_hw->spin_lock, flags); + cam_tasklet_start(csid_hw->tasklet); + + return rc; + +disable_soc: + cam_tfe_csid_disable_soc_resources(soc_info); + csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; +err: + csid_hw->hw_info->open_count--; + return rc; +} + +static int cam_tfe_csid_disable_hw(struct cam_tfe_csid_hw *csid_hw) +{ + int rc = -EINVAL; + struct cam_hw_soc_info *soc_info; + const struct cam_tfe_csid_reg_offset *csid_reg; + unsigned long flags; + + /* Check for refcount */ + if (!csid_hw->hw_info->open_count) { + CAM_WARN(CAM_ISP, "Unbalanced disable_hw"); + return rc; + } + + /* Decrement ref Count */ + csid_hw->hw_info->open_count--; + + if (csid_hw->hw_info->open_count) { + rc = 0; + return rc; + } + + soc_info = &csid_hw->hw_info->soc_info; + csid_reg = csid_hw->csid_info->csid_reg; + + /* Disable the csi2 */ + cam_tfe_csid_disable_csi2(csid_hw); + + CAM_DBG(CAM_ISP, "%s:Calling Global Reset", __func__); + cam_tfe_csid_global_reset(csid_hw); + CAM_DBG(CAM_ISP, "%s:Global Reset Done", __func__); + + CAM_DBG(CAM_ISP, "CSID:%d De-init CSID HW", + csid_hw->hw_intf->hw_idx); + + /* Disable the top IRQ interrupt */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_mask_addr); + + rc = cam_tfe_csid_disable_soc_resources(soc_info); + if (rc) + CAM_ERR(CAM_ISP, "CSID:%d Disable CSID SOC failed", + csid_hw->hw_intf->hw_idx); + + cam_tasklet_stop(csid_hw->tasklet); + spin_lock_irqsave(&csid_hw->spin_lock, flags); + csid_hw->device_enabled = 0; + spin_unlock_irqrestore(&csid_hw->spin_lock, flags); + csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; + csid_hw->error_irq_count = 0; + csid_hw->prev_boot_timestamp = 0; + + return rc; +} + +static int cam_tfe_csid_init_config_pxl_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + struct cam_tfe_csid_path_cfg *path_data; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + const struct cam_tfe_csid_pxl_reg_offset *pxl_reg = NULL; + uint32_t decode_format = 0, plain_format = 0, val = 0; + + path_data = (struct cam_tfe_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + pxl_reg = csid_reg->ipp_reg; + if (!pxl_reg) { + CAM_ERR(CAM_ISP, "CSID:%d IPP :%d is not supported on HW", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Config IPP Path"); + rc = cam_tfe_csid_get_format_ipp(path_data->in_format, + &decode_format, &plain_format); + if (rc) + return rc; + + /* + * configure Pxl path and enable the time stamp capture. + * enable the HW measrurement blocks + */ + val = (path_data->vc << csid_reg->cmn_reg->vc_shift_val) | + (path_data->dt << csid_reg->cmn_reg->dt_shift_val) | + (path_data->cid << csid_reg->cmn_reg->dt_id_shift_val) | + (decode_format << csid_reg->cmn_reg->fmt_shift_val) | + (path_data->crop_enable << + csid_reg->cmn_reg->crop_h_en_shift_val) | + (path_data->crop_enable << + csid_reg->cmn_reg->crop_v_en_shift_val) | + (1 << 1); + + val |= (1 << pxl_reg->pix_store_en_shift_val); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg1_addr); + + /* select the post irq sub sample strobe for time stamp capture */ + val |= TFE_CSID_TIMESTAMP_STB_POST_IRQ; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg1_addr); + + if (path_data->crop_enable) { + val = (((path_data->end_pixel & 0xFFFF) << + csid_reg->cmn_reg->crop_shift) | + (path_data->start_pixel & 0xFFFF)); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_hcrop_addr); + CAM_DBG(CAM_ISP, "CSID:%d Horizontal crop config val: 0x%x", + csid_hw->hw_intf->hw_idx, val); + + val = (((path_data->end_line & 0xFFFF) << + csid_reg->cmn_reg->crop_shift) | + (path_data->start_line & 0xFFFF)); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_vcrop_addr); + CAM_DBG(CAM_ISP, "CSID:%d Vertical Crop config val: 0x%x", + csid_hw->hw_intf->hw_idx, val); + + /* Enable generating early eof strobe based on crop config */ + if (!(csid_hw->csid_debug & TFE_CSID_DEBUG_DISABLE_EARLY_EOF)) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + val |= (1 << pxl_reg->early_eof_en_shift_val); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + } + } + + /* Enable the Pxl path */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + val |= (1 << csid_reg->cmn_reg->path_en_shift_val); + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + + /* Enable Error Detection Overflow ctrl mode: 2 -> Detect overflow */ + val = 0x9; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_err_recovery_cfg0_addr); + + /* configure the rx packet capture based on csid debug set */ + val = 0; + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) + val = ((1 << + csid_reg->csi2_reg->csi2_capture_short_pkt_en_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_short_pkt_vc_shift)); + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_long_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_long_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_long_pkt_vc_shift)); + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_vc_shift)); + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_capture_ctrl_addr); + CAM_DBG(CAM_ISP, "rx capture control value 0x%x", val); + + res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; + + return rc; +} + +static int cam_tfe_csid_deinit_pxl_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + const struct cam_tfe_csid_pxl_reg_offset *pxl_reg = NULL; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + pxl_reg = csid_reg->ipp_reg; + if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) { + CAM_ERR(CAM_ISP, + "CSID:%d IPP Res type %d res_id:%d in wrong state %d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, res->res_state); + rc = -EINVAL; + } + + if (!pxl_reg) { + CAM_ERR(CAM_ISP, "CSID:%d IPP %d is not supported on HW", + csid_hw->hw_intf->hw_idx, res->res_id); + rc = -EINVAL; + goto end; + } + + /* Disable Error Recovery */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_err_recovery_cfg0_addr); + +end: + res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + return rc; +} + +static int cam_tfe_csid_enable_pxl_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + struct cam_tfe_csid_path_cfg *path_data; + const struct cam_tfe_csid_pxl_reg_offset *pxl_reg = NULL; + uint32_t val = 0; + + path_data = (struct cam_tfe_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + pxl_reg = csid_reg->ipp_reg; + + if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) { + CAM_ERR(CAM_ISP, + "CSID:%d IPP path res type:%d res_id:%d Invalid state%d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, res->res_state); + return -EINVAL; + } + + if (!pxl_reg) { + CAM_ERR(CAM_ISP, "CSID:%d IPP resid: %d not supported on HW", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Enable IPP path"); + + /* Set master or slave path */ + if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER) + /* Set halt mode as master */ + val = (TFE_CSID_HALT_MODE_MASTER << + pxl_reg->halt_mode_shift) | + (pxl_reg->halt_master_sel_master_val << + pxl_reg->halt_master_sel_shift); + else if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) + /* Set halt mode as slave and set master idx */ + val = (TFE_CSID_HALT_MODE_SLAVE << pxl_reg->halt_mode_shift); + else + /* Default is internal halt mode */ + val = 0; + + /* + * Resume at frame boundary if Master or No Sync. + * Slave will get resume command from Master. + */ + if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER || + path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) + val |= CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + + CAM_DBG(CAM_ISP, "CSID:%d IPP Ctrl val: 0x%x", + csid_hw->hw_intf->hw_idx, val); + + /* Enable the required pxl path interrupts */ + val = TFE_CSID_PATH_INFO_RST_DONE | + TFE_CSID_PATH_ERROR_FIFO_OVERFLOW | + TFE_CSID_PATH_IPP_ERROR_CCIF_VIOLATION | + TFE_CSID_PATH_IPP_OVERFLOW_IRQ; + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ) + val |= TFE_CSID_PATH_INFO_INPUT_SOF; + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOF_IRQ) + val |= TFE_CSID_PATH_INFO_INPUT_EOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_irq_mask_addr); + + CAM_DBG(CAM_ISP, "Enable IPP IRQ mask 0x%x", val); + + res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return 0; +} + +static int cam_tfe_csid_disable_pxl_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res, + enum cam_tfe_csid_halt_cmd stop_cmd) +{ + int rc = 0; + uint32_t val = 0; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + struct cam_tfe_csid_path_cfg *path_data; + const struct cam_tfe_csid_pxl_reg_offset *pxl_reg; + + path_data = (struct cam_tfe_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res id%d", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + if (res->res_state == CAM_ISP_RESOURCE_STATE_INIT_HW || + res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_DBG(CAM_ISP, "CSID:%d Res:%d already in stopped state:%d", + csid_hw->hw_intf->hw_idx, res->res_id, res->res_state); + return rc; + } + + pxl_reg = csid_reg->ipp_reg; + if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_DBG(CAM_ISP, "CSID:%d IPP path Res:%d Invalid state%d", + csid_hw->hw_intf->hw_idx, res->res_id, res->res_state); + return -EINVAL; + } + + if (!pxl_reg) { + CAM_ERR(CAM_ISP, "CSID:%d IPP %d is not supported on HW", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + if (stop_cmd != CAM_TFE_CSID_HALT_AT_FRAME_BOUNDARY && + stop_cmd != CAM_TFE_CSID_HALT_IMMEDIATELY) { + CAM_ERR(CAM_ISP, + "CSID:%d IPP path un supported stop command:%d", + csid_hw->hw_intf->hw_idx, stop_cmd); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "CSID:%d res_id:%d IPP path", + csid_hw->hw_intf->hw_idx, res->res_id); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_irq_mask_addr); + + if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER || + path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) { + /* configure Halt */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + val &= ~0x3; + val |= stop_cmd; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + } + + if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE && + stop_cmd == CAM_TFE_CSID_HALT_IMMEDIATELY) { + /* configure Halt for slave */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + val &= ~0xF; + val |= stop_cmd; + val |= (TFE_CSID_HALT_MODE_MASTER << 2); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + } + + return rc; +} + +static int cam_tfe_csid_init_config_rdi_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + struct cam_tfe_csid_path_cfg *path_data; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t path_format = 0, plain_fmt = 0, val = 0, id; + + path_data = (struct cam_tfe_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + id = res->res_id; + if (!csid_reg->rdi_reg[id]) { + CAM_ERR(CAM_ISP, "CSID:%d RDI:%d is not supported on HW", + csid_hw->hw_intf->hw_idx, id); + return -EINVAL; + } + + rc = cam_tfe_csid_get_format_rdi(path_data->in_format, + path_data->out_format, &path_format, &plain_fmt); + if (rc) + return rc; + + /* + * RDI path config and enable the time stamp capture + * Enable the measurement blocks + */ + val = (path_data->vc << csid_reg->cmn_reg->vc_shift_val) | + (path_data->dt << csid_reg->cmn_reg->dt_shift_val) | + (path_data->cid << csid_reg->cmn_reg->dt_id_shift_val) | + (path_format << csid_reg->cmn_reg->fmt_shift_val) | + (plain_fmt << csid_reg->cmn_reg->plain_fmt_shit_val) | + (1 << 2) | 1; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); + + /* select the post irq sub sample strobe for time stamp capture */ + cam_io_w_mb(TFE_CSID_TIMESTAMP_STB_POST_IRQ, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg1_addr); + + /* Enable Error Detection, Overflow ctrl mode: 2 -> Detect overflow */ + val = 0x9; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_err_recovery_cfg0_addr); + + /* Configure the halt mode */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + + /* Enable the RPP path */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); + val |= (1 << csid_reg->cmn_reg->path_en_shift_val); + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); + + /* configure the rx packet capture based on csid debug set */ + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) + val = ((1 << + csid_reg->csi2_reg->csi2_capture_short_pkt_en_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_short_pkt_vc_shift)); + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_long_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_long_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_long_pkt_vc_shift)); + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_vc_shift)); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_capture_ctrl_addr); + + res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; + + return rc; +} + +static int cam_tfe_csid_deinit_rdi_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + uint32_t id; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + id = res->res_id; + + if (res->res_id > CAM_TFE_CSID_PATH_RES_RDI_2 || + res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW || + !csid_reg->rdi_reg[id]) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res id%d state:%d", + csid_hw->hw_intf->hw_idx, res->res_id, + res->res_state); + return -EINVAL; + } + + /* Disable Error Recovery */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_err_recovery_cfg0_addr); + + res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + return rc; +} + +static int cam_tfe_csid_enable_rdi_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t id, val; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + id = res->res_id; + + if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW || + res->res_id > CAM_TFE_CSID_PATH_RES_RDI_2 || + !csid_reg->rdi_reg[id]) { + CAM_ERR(CAM_ISP, + "CSID:%d invalid res type:%d res_id:%d state%d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, res->res_state); + return -EINVAL; + } + + /* resume at frame boundary */ + cam_io_w_mb(CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + + /* Enable the required RDI interrupts */ + val = TFE_CSID_PATH_INFO_RST_DONE | TFE_CSID_PATH_ERROR_FIFO_OVERFLOW | + TFE_CSID_PATH_RDI_ERROR_CCIF_VIOLATION | + TFE_CSID_PATH_RDI_OVERFLOW_IRQ; + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ) + val |= TFE_CSID_PATH_INFO_INPUT_SOF; + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOF_IRQ) + val |= TFE_CSID_PATH_INFO_INPUT_EOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); + + res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return 0; +} + +static int cam_tfe_csid_disable_rdi_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res, + enum cam_tfe_csid_halt_cmd stop_cmd) +{ + int rc = 0; + uint32_t id, val = 0; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + id = res->res_id; + + if ((res->res_id > CAM_TFE_CSID_PATH_RES_RDI_2) || + (!csid_reg->rdi_reg[res->res_id])) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d Invalid res id%d", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + if (res->res_state == CAM_ISP_RESOURCE_STATE_INIT_HW || + res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d Res:%d already in stopped state:%d", + csid_hw->hw_intf->hw_idx, + res->res_id, res->res_state); + return rc; + } + + if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d Res:%d Invalid res_state%d", + csid_hw->hw_intf->hw_idx, res->res_id, + res->res_state); + return -EINVAL; + } + + if (stop_cmd != CAM_TFE_CSID_HALT_AT_FRAME_BOUNDARY && + stop_cmd != CAM_TFE_CSID_HALT_IMMEDIATELY) { + CAM_ERR(CAM_ISP, "CSID:%d un supported stop command:%d", + csid_hw->hw_intf->hw_idx, stop_cmd); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "CSID:%d res_id:%d", + csid_hw->hw_intf->hw_idx, res->res_id); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); + + /* Halt the RDI path */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + val &= ~0x3; + val |= stop_cmd; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + + return rc; +} + +static int cam_tfe_csid_poll_stop_status( + struct cam_tfe_csid_hw *csid_hw, + uint32_t res_mask) +{ + int rc = 0; + uint32_t csid_status_addr = 0, val = 0, res_id = 0; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + for (; res_id < CAM_TFE_CSID_PATH_RES_MAX; res_id++, res_mask >>= 1) { + if ((res_mask & 0x1) == 0) + continue; + val = 0; + + if (res_id == CAM_TFE_CSID_PATH_RES_IPP) { + csid_status_addr = + csid_reg->ipp_reg->csid_pxl_status_addr; + + if (csid_hw->ipp_res.res_state != + CAM_ISP_RESOURCE_STATE_STREAMING) + continue; + + } else { + csid_status_addr = + csid_reg->rdi_reg[res_id]->csid_rdi_status_addr; + + if (csid_hw->rdi_res[res_id].res_state != + CAM_ISP_RESOURCE_STATE_STREAMING) + continue; + + } + + CAM_DBG(CAM_ISP, "start polling CSID:%d res_id:%d", + csid_hw->hw_intf->hw_idx, res_id); + + rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + + csid_status_addr, val, (val & 0x1) == 0x1, + CAM_TFE_CSID_TIMEOUT_SLEEP_US, + CAM_TFE_CSID_TIMEOUT_ALL_US); + if (rc < 0) { + CAM_ERR(CAM_ISP, "CSID:%d res:%d halt failed rc %d", + csid_hw->hw_intf->hw_idx, res_id, rc); + rc = -ETIMEDOUT; + break; + } + CAM_DBG(CAM_ISP, "End polling CSID:%d res_id:%d", + csid_hw->hw_intf->hw_idx, res_id); + } + + return rc; +} + +static int __cam_tfe_csid_read_timestamp(void __iomem *base, + uint32_t msb_offset, uint32_t lsb_offset, uint64_t *timestamp) +{ + uint32_t lsb, msb, tmp, torn = 0; + + msb = cam_io_r_mb(base + msb_offset); + do { + tmp = msb; + torn++; + lsb = cam_io_r_mb(base + lsb_offset); + msb = cam_io_r_mb(base + msb_offset); + } while (tmp != msb); + + *timestamp = msb; + *timestamp = (*timestamp << 32) | lsb; + + return (torn > 1); +} + +static int cam_tfe_csid_get_time_stamp( + struct cam_tfe_csid_hw *csid_hw, void *cmd_args) +{ + struct cam_tfe_csid_get_time_stamp_args *time_stamp; + struct cam_isp_resource_node *res; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + const struct cam_tfe_csid_rdi_reg_offset *rdi_reg; + struct timespec64 ts; + uint32_t id, torn; + uint64_t time_delta; + + time_stamp = (struct cam_tfe_csid_get_time_stamp_args *)cmd_args; + res = time_stamp->node_res; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH || + res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res_type:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid dev state :%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + return -EINVAL; + } + + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) { + torn = __cam_tfe_csid_read_timestamp( + soc_info->reg_map[0].mem_base, + csid_reg->ipp_reg->csid_pxl_timestamp_curr1_sof_addr, + csid_reg->ipp_reg->csid_pxl_timestamp_curr0_sof_addr, + &time_stamp->time_stamp_val); + } else { + id = res->res_id; + rdi_reg = csid_reg->rdi_reg[id]; + torn = __cam_tfe_csid_read_timestamp( + soc_info->reg_map[0].mem_base, + rdi_reg->csid_rdi_timestamp_curr1_sof_addr, + rdi_reg->csid_rdi_timestamp_curr0_sof_addr, + &time_stamp->time_stamp_val); + } + + time_stamp->time_stamp_val = mul_u64_u32_div( + time_stamp->time_stamp_val, + CAM_TFE_CSID_QTIMER_MUL_FACTOR, + CAM_TFE_CSID_QTIMER_DIV_FACTOR); + + if (!csid_hw->prev_boot_timestamp) { + get_monotonic_boottime64(&ts); + time_stamp->boot_timestamp = + (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); + csid_hw->prev_qtimer_ts = 0; + CAM_DBG(CAM_ISP, "timestamp:%lld", + time_stamp->boot_timestamp); + } else { + time_delta = time_stamp->time_stamp_val - + csid_hw->prev_qtimer_ts; + + if (csid_hw->prev_boot_timestamp > + U64_MAX - time_delta) { + CAM_WARN(CAM_ISP, "boottimestamp overflowed"); + CAM_INFO(CAM_ISP, + "currQTimer %lx prevQTimer %lx prevBootTimer %lx torn %d", + time_stamp->time_stamp_val, + csid_hw->prev_qtimer_ts, + csid_hw->prev_boot_timestamp, torn); + return -EINVAL; + } + + time_stamp->boot_timestamp = + csid_hw->prev_boot_timestamp + time_delta; + } + + CAM_DBG(CAM_ISP, + "currQTimer %lx prevQTimer %lx currBootTimer %lx prevBootTimer %lx torn %d", + time_stamp->time_stamp_val, + csid_hw->prev_qtimer_ts, time_stamp->boot_timestamp, + csid_hw->prev_boot_timestamp, torn); + + csid_hw->prev_qtimer_ts = time_stamp->time_stamp_val; + csid_hw->prev_boot_timestamp = time_stamp->boot_timestamp; + + return 0; +} + +static int cam_tfe_csid_set_csid_debug(struct cam_tfe_csid_hw *csid_hw, + void *cmd_args) +{ + uint32_t *csid_debug; + + csid_debug = (uint32_t *) cmd_args; + csid_hw->csid_debug = *csid_debug; + CAM_DBG(CAM_ISP, "CSID:%d set csid debug value:%d", + csid_hw->hw_intf->hw_idx, csid_hw->csid_debug); + + return 0; +} + +static int cam_tfe_csid_get_hw_caps(void *hw_priv, + void *get_hw_cap_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw_caps *hw_caps; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + const struct cam_tfe_csid_reg_offset *csid_reg; + + if (!hw_priv || !get_hw_cap_args) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + csid_reg = csid_hw->csid_info->csid_reg; + hw_caps = (struct cam_tfe_csid_hw_caps *) get_hw_cap_args; + + hw_caps->num_rdis = csid_reg->cmn_reg->num_rdis; + hw_caps->num_pix = csid_hw->pxl_pipe_enable; + hw_caps->major_version = csid_reg->cmn_reg->major_version; + hw_caps->minor_version = csid_reg->cmn_reg->minor_version; + hw_caps->version_incr = csid_reg->cmn_reg->version_incr; + + CAM_DBG(CAM_ISP, + "CSID:%d No rdis:%d, no pix:%d, major:%d minor:%d ver :%d", + csid_hw->hw_intf->hw_idx, hw_caps->num_rdis, + hw_caps->num_pix, hw_caps->major_version, + hw_caps->minor_version, hw_caps->version_incr); + + return rc; +} + +static int cam_tfe_csid_reset(void *hw_priv, + void *reset_args, uint32_t arg_size) +{ + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_tfe_csid_reset_cfg_args *reset; + int rc = 0; + + if (!hw_priv || !reset_args || (arg_size != + sizeof(struct cam_tfe_csid_reset_cfg_args))) { + CAM_ERR(CAM_ISP, "CSID:Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + reset = (struct cam_tfe_csid_reset_cfg_args *)reset_args; + + switch (reset->reset_type) { + case CAM_TFE_CSID_RESET_GLOBAL: + rc = cam_tfe_csid_global_reset(csid_hw); + break; + case CAM_TFE_CSID_RESET_PATH: + rc = cam_tfe_csid_path_reset(csid_hw, reset); + break; + default: + CAM_ERR(CAM_ISP, "CSID:Invalid reset type :%d", + reset->reset_type); + rc = -EINVAL; + break; + } + + return rc; +} + +static int cam_tfe_csid_reserve(void *hw_priv, + void *reserve_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_tfe_csid_hw_reserve_resource_args *reserv; + + if (!hw_priv || !reserve_args || (arg_size != + sizeof(struct cam_tfe_csid_hw_reserve_resource_args))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + reserv = (struct cam_tfe_csid_hw_reserve_resource_args *)reserve_args; + + if (reserv->res_type != CAM_ISP_RESOURCE_PIX_PATH) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type :%d", + csid_hw->hw_intf->hw_idx, reserv->res_type); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "res_type %d, CSID: %u", + reserv->res_type, csid_hw->hw_intf->hw_idx); + + mutex_lock(&csid_hw->hw_info->hw_mutex); + rc = cam_tfe_csid_path_reserve(csid_hw, reserv); + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_tfe_csid_release(void *hw_priv, + void *release_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + struct cam_tfe_csid_path_cfg *path_data; + + if (!hw_priv || !release_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + res = (struct cam_isp_resource_node *)release_args; + + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + mutex_lock(&csid_hw->hw_info->hw_mutex); + if ((res->res_type == CAM_ISP_RESOURCE_PIX_PATH && + res->res_id >= CAM_TFE_CSID_PATH_RES_MAX)) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + rc = -EINVAL; + goto end; + } + + csid_hw->event_cb = NULL; + csid_hw->event_cb_priv = NULL; + + if ((res->res_state <= CAM_ISP_RESOURCE_STATE_AVAILABLE) || + (res->res_state >= CAM_ISP_RESOURCE_STATE_STREAMING)) { + CAM_WARN(CAM_ISP, + "CSID:%d res type:%d Res %d in state %d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, + res->res_state); + goto end; + } + + CAM_DBG(CAM_ISP, "CSID:%d res type :%d Resource id:%d", + csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); + + path_data = (struct cam_tfe_csid_path_cfg *)res->res_priv; + if (csid_hw->cid_res[path_data->cid].cnt) + csid_hw->cid_res[path_data->cid].cnt--; + + if (csid_hw->csi2_reserve_cnt) + csid_hw->csi2_reserve_cnt--; + + if (!csid_hw->csi2_reserve_cnt) + memset(&csid_hw->csi2_rx_cfg, 0, + sizeof(struct cam_tfe_csid_csi2_rx_cfg)); + + CAM_DBG(CAM_ISP, "CSID:%d res id :%d cnt:%d reserv cnt:%d", + csid_hw->hw_intf->hw_idx, + res->res_id, csid_hw->cid_res[path_data->cid].cnt, + csid_hw->csi2_reserve_cnt); + + res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + +end: + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_tfe_csid_reset_retain_sw_reg( + struct cam_tfe_csid_hw *csid_hw) +{ + int rc = 0; + uint32_t status; + const struct cam_tfe_csid_reg_offset *csid_reg = + csid_hw->csid_info->csid_reg; + struct cam_hw_soc_info *soc_info; + + soc_info = &csid_hw->hw_info->soc_info; + + /* Mask top interrupts */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_mask_addr); + /* clear the top interrupt first */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + cam_io_w_mb(csid_reg->cmn_reg->csid_rst_stb, + soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_rst_strobes_addr); + rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_status_addr, + status, (status & 0x1) == 0x1, + CAM_TFE_CSID_TIMEOUT_SLEEP_US, CAM_TFE_CSID_TIMEOUT_ALL_US); + if (rc < 0) { + CAM_ERR(CAM_ISP, "CSID:%d csid_reset fail rc = %d", + csid_hw->hw_intf->hw_idx, rc); + status = cam_io_r(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_status_addr); + CAM_DBG(CAM_ISP, "Status reg %d", status); + } else { + CAM_DBG(CAM_ISP, "CSID:%d hw reset completed %d", + csid_hw->hw_intf->hw_idx, rc); + rc = 0; + } + + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + return rc; +} + +static int cam_tfe_csid_init_hw(void *hw_priv, + void *init_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + const struct cam_tfe_csid_reg_offset *csid_reg; + + if (!hw_priv || !init_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + res = (struct cam_isp_resource_node *)init_args; + csid_reg = csid_hw->csid_info->csid_reg; + + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type state %d", + csid_hw->hw_intf->hw_idx, + res->res_type); + return -EINVAL; + } + + mutex_lock(&csid_hw->hw_info->hw_mutex); + if (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && + res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res tpe:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + rc = -EINVAL; + goto end; + } + + if ((res->res_type == CAM_ISP_RESOURCE_PIX_PATH) && + (res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED)) { + CAM_ERR(CAM_ISP, + "CSID:%d res type:%d res_id:%dInvalid state %d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, res->res_state); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ISP, "CSID:%d res type :%d res_id:%d", + csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); + + /* Initialize the csid hardware */ + rc = cam_tfe_csid_enable_hw(csid_hw); + if (rc) + goto end; + + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) + rc = cam_tfe_csid_init_config_pxl_path(csid_hw, res); + else + rc = cam_tfe_csid_init_config_rdi_path(csid_hw, res); + + rc = cam_tfe_csid_reset_retain_sw_reg(csid_hw); + if (rc < 0) + CAM_ERR(CAM_ISP, "CSID: Failed in SW reset"); + + if (rc) + cam_tfe_csid_disable_hw(csid_hw); + +end: + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_tfe_csid_deinit_hw(void *hw_priv, + void *deinit_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + + if (!hw_priv || !deinit_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "CSID:Invalid arguments"); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Enter"); + res = (struct cam_isp_resource_node *)deinit_args; + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid Res type %d", + csid_hw->hw_intf->hw_idx, + res->res_type); + return -EINVAL; + } + + mutex_lock(&csid_hw->hw_info->hw_mutex); + if (res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_DBG(CAM_ISP, "CSID:%d Res:%d already in De-init state", + csid_hw->hw_intf->hw_idx, + res->res_id); + goto end; + } + + CAM_DBG(CAM_ISP, "De-Init IPP Path: %d", res->res_id); + + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) + rc = cam_tfe_csid_deinit_pxl_path(csid_hw, res); + else + rc = cam_tfe_csid_deinit_rdi_path(csid_hw, res); + + /* Disable CSID HW */ + CAM_DBG(CAM_ISP, "Disabling CSID Hw"); + cam_tfe_csid_disable_hw(csid_hw); + CAM_DBG(CAM_ISP, "%s: Exit", __func__); + +end: + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_tfe_csid_start(void *hw_priv, void *start_args, + uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + const struct cam_tfe_csid_reg_offset *csid_reg; + + if (!hw_priv || !start_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + res = (struct cam_isp_resource_node *)start_args; + csid_reg = csid_hw->csid_info->csid_reg; + + if (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && + res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res tpe:%d res id:%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + rc = -EINVAL; + goto end; + } + + /* Reset sof irq debug fields */ + csid_hw->sof_irq_triggered = false; + csid_hw->irq_debug_cnt = 0; + + CAM_DBG(CAM_ISP, "CSID:%d res_type :%d res_id:%d", + csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); + + switch (res->res_type) { + case CAM_ISP_RESOURCE_PIX_PATH: + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) + rc = cam_tfe_csid_enable_pxl_path(csid_hw, res); + else + rc = cam_tfe_csid_enable_rdi_path(csid_hw, res); + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type%d", + csid_hw->hw_intf->hw_idx, res->res_type); + break; + } +end: + return rc; +} + +static int cam_tfe_csid_stop(void *hw_priv, + void *stop_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + struct cam_tfe_csid_hw_stop_args *csid_stop; + uint32_t i; + uint32_t res_mask = 0; + + if (!hw_priv || !stop_args || + (arg_size != sizeof(struct cam_tfe_csid_hw_stop_args))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + csid_stop = (struct cam_tfe_csid_hw_stop_args *) stop_args; + + if (!csid_stop->num_res) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + CAM_DBG(CAM_ISP, "CSID:%d num_res %d", + csid_hw->hw_intf->hw_idx, + csid_stop->num_res); + + /* Stop the resource first */ + for (i = 0; i < csid_stop->num_res; i++) { + res = csid_stop->node_res[i]; + CAM_DBG(CAM_ISP, "CSID:%d res_type %d res_id %d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id); + switch (res->res_type) { + case CAM_ISP_RESOURCE_PIX_PATH: + res_mask |= (1 << res->res_id); + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) + rc = cam_tfe_csid_disable_pxl_path(csid_hw, + res, csid_stop->stop_cmd); + else + rc = cam_tfe_csid_disable_rdi_path(csid_hw, + res, csid_stop->stop_cmd); + + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type%d", + csid_hw->hw_intf->hw_idx, + res->res_type); + break; + } + } + + if (res_mask) + rc = cam_tfe_csid_poll_stop_status(csid_hw, res_mask); + + for (i = 0; i < csid_stop->num_res; i++) { + res = csid_stop->node_res[i]; + res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; + } + + CAM_DBG(CAM_ISP, "%s: Exit", __func__); + return rc; +} + +static int cam_tfe_csid_read(void *hw_priv, + void *read_args, uint32_t arg_size) +{ + CAM_ERR(CAM_ISP, "CSID: un supported"); + return -EINVAL; +} + +static int cam_tfe_csid_write(void *hw_priv, + void *write_args, uint32_t arg_size) +{ + CAM_ERR(CAM_ISP, "CSID: un supported"); + return -EINVAL; +} + +static int cam_tfe_csid_sof_irq_debug( + struct cam_tfe_csid_hw *csid_hw, void *cmd_args) +{ + int i = 0; + uint32_t val = 0; + bool sof_irq_enable = false; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (*((uint32_t *)cmd_args) == 1) + sof_irq_enable = true; + + if (csid_hw->hw_info->hw_state == + CAM_HW_STATE_POWER_DOWN) { + CAM_WARN(CAM_ISP, + "CSID powered down unable to %s sof irq", + sof_irq_enable ? "enable" : "disable"); + return 0; + } + + if (csid_reg->ipp_reg) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + + if (val) { + if (sof_irq_enable) + val |= TFE_CSID_PATH_INFO_INPUT_SOF; + else + val &= ~TFE_CSID_PATH_INFO_INPUT_SOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + val = 0; + } + } + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); + if (val) { + if (sof_irq_enable) + val |= TFE_CSID_PATH_INFO_INPUT_SOF; + else + val &= ~TFE_CSID_PATH_INFO_INPUT_SOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); + val = 0; + } + } + + if (sof_irq_enable) { + csid_hw->csid_debug |= TFE_CSID_DEBUG_ENABLE_SOF_IRQ; + csid_hw->sof_irq_triggered = true; + } else { + csid_hw->csid_debug &= ~TFE_CSID_DEBUG_ENABLE_SOF_IRQ; + csid_hw->sof_irq_triggered = false; + } + + CAM_INFO(CAM_ISP, "SOF freeze: CSID SOF irq %s", + sof_irq_enable ? "enabled" : "disabled"); + + return 0; +} + +static int cam_tfe_csid_set_csid_clock( + struct cam_tfe_csid_hw *csid_hw, void *cmd_args) +{ + struct cam_tfe_csid_clock_update_args *clk_update = NULL; + + if (!csid_hw) + return -EINVAL; + + clk_update = + (struct cam_tfe_csid_clock_update_args *)cmd_args; + + csid_hw->clk_rate = clk_update->clk_rate; + CAM_DBG(CAM_ISP, "CSID clock rate %llu", csid_hw->clk_rate); + + return 0; +} + +static int cam_tfe_csid_get_regdump(struct cam_tfe_csid_hw *csid_hw, + void *cmd_args) +{ + struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + struct cam_isp_resource_node *res; + struct cam_tfe_csid_path_cfg *path_data; + uint32_t id; + int val; + + csid_reg = (struct cam_tfe_csid_reg_offset *) + csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + res = (struct cam_isp_resource_node *)cmd_args; + path_data = (struct cam_tfe_csid_path_cfg *)res->res_priv; + + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH || + res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res_type:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid dev state :%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + return -EINVAL; + } + + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) { + CAM_INFO(CAM_ISP, "Dumping CSID:%d IPP registers ", + csid_hw->hw_intf->hw_idx); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_cfg0_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ipp_reg->csid_pxl_cfg0_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_cfg1_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ipp_reg->csid_pxl_cfg1_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_ctrl_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ipp_reg->csid_pxl_ctrl_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_hcrop_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ipp_reg->csid_pxl_hcrop_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_vcrop_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ipp_reg->csid_pxl_vcrop_addr, val); + } else { + id = res->res_id; + CAM_INFO(CAM_ISP, "Dumping CSID:%d RDI:%d registers ", + csid_hw->hw_intf->hw_idx, id); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg1_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->rdi_reg[id]->csid_rdi_cfg1_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr, val); + } + CAM_INFO(CAM_ISP, + "start pix:%d end pix:%d start line:%d end line:%d w:%d h:%d", + path_data->start_pixel, path_data->end_pixel, + path_data->start_line, path_data->end_line, + path_data->width, path_data->height); + CAM_INFO(CAM_ISP, + "clock:%d crop_enable:%d vc:%d dt:%d informat:%d outformat:%d", + path_data->clk_rate, path_data->crop_enable, + path_data->vc, path_data->dt, + path_data->in_format, path_data->out_format); + + return 0; +} + +static int cam_tfe_csid_dump_hw( + struct cam_tfe_csid_hw *csid_hw, void *cmd_args) +{ + int i; + uint8_t *dst; + uint32_t *addr, *start; + uint64_t *clk_addr, *clk_start; + uint32_t min_len; + uint32_t num_reg; + uint32_t reg_size = 0; + size_t remain_len; + struct cam_isp_hw_dump_header *hdr; + struct cam_isp_hw_dump_args *dump_args = + (struct cam_isp_hw_dump_args *)cmd_args; + struct cam_hw_soc_info *soc_info; + + if (!dump_args) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + if (!dump_args->cpu_addr || !dump_args->buf_len) { + CAM_ERR(CAM_ISP, + "Invalid params %pK %zu", + (void *)dump_args->cpu_addr, + dump_args->buf_len); + return -EINVAL; + } + + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_ISP, + "Dump offset overshoot offset %zu buf_len %zu", + dump_args->offset, dump_args->buf_len); + return -ENOSPC; + } + + soc_info = &csid_hw->hw_info->soc_info; + if (dump_args->is_dump_all) + reg_size = soc_info->reg_map[0].size; + + min_len = reg_size + + sizeof(struct cam_isp_hw_dump_header) + + (sizeof(uint32_t) * CAM_TFE_CSID_DUMP_MISC_NUM_WORDS); + remain_len = dump_args->buf_len - dump_args->offset; + + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu, min %u", + remain_len, min_len); + return -ENOSPC; + } + + mutex_lock(&csid_hw->hw_info->hw_mutex); + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid HW State:%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return -EINVAL; + } + + if (!dump_args->is_dump_all) + goto dump_bw; + + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "CSID_REG:"); + addr = (uint32_t *)(dst + sizeof(struct cam_isp_hw_dump_header)); + start = addr; + num_reg = soc_info->reg_map[0].size/4; + hdr->word_size = sizeof(uint32_t); + *addr = soc_info->index; + addr++; + + for (i = 0; i < num_reg; i++) { + addr[0] = soc_info->mem_block[0]->start + (i*4); + addr[1] = cam_io_r(soc_info->reg_map[0].mem_base + + (i*4)); + addr += 2; + } + + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); +dump_bw: + dst = (char *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "CSID_CLK_RATE:"); + clk_addr = (uint64_t *)(dst + + sizeof(struct cam_isp_hw_dump_header)); + clk_start = clk_addr; + hdr->word_size = sizeof(uint64_t); + *clk_addr++ = csid_hw->clk_rate; + hdr->size = hdr->word_size * (clk_addr - clk_start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + CAM_DBG(CAM_ISP, "offset %zu", dump_args->offset); + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return 0; +} + +static int cam_tfe_csid_process_cmd(void *hw_priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + + if (!hw_priv || !cmd_args) { + CAM_ERR(CAM_ISP, "CSID: Invalid arguments"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + + switch (cmd_type) { + case CAM_TFE_CSID_CMD_GET_TIME_STAMP: + rc = cam_tfe_csid_get_time_stamp(csid_hw, cmd_args); + break; + case CAM_TFE_CSID_SET_CSID_DEBUG: + rc = cam_tfe_csid_set_csid_debug(csid_hw, cmd_args); + break; + case CAM_TFE_CSID_SOF_IRQ_DEBUG: + rc = cam_tfe_csid_sof_irq_debug(csid_hw, cmd_args); + break; + case CAM_ISP_HW_CMD_CSID_CLOCK_UPDATE: + rc = cam_tfe_csid_set_csid_clock(csid_hw, cmd_args); + break; + case CAM_TFE_CSID_CMD_GET_REG_DUMP: + rc = cam_tfe_csid_get_regdump(csid_hw, cmd_args); + break; + case CAM_ISP_HW_CMD_DUMP_HW: + rc = cam_tfe_csid_dump_hw(csid_hw, cmd_args); + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d unsupported cmd:%d", + csid_hw->hw_intf->hw_idx, cmd_type); + rc = -EINVAL; + break; + } + + return rc; +} + +static int cam_csid_get_evt_payload( + struct cam_tfe_csid_hw *csid_hw, + struct cam_csid_evt_payload **evt_payload) +{ + + spin_lock(&csid_hw->spin_lock); + + if (list_empty(&csid_hw->free_payload_list)) { + *evt_payload = NULL; + spin_unlock(&csid_hw->spin_lock); + CAM_ERR_RATE_LIMIT(CAM_ISP, "No free payload core %d", + csid_hw->hw_intf->hw_idx); + return -ENOMEM; + } + + *evt_payload = list_first_entry(&csid_hw->free_payload_list, + struct cam_csid_evt_payload, list); + list_del_init(&(*evt_payload)->list); + spin_unlock(&csid_hw->spin_lock); + + return 0; +} + +static int cam_csid_put_evt_payload( + struct cam_tfe_csid_hw *csid_hw, + struct cam_csid_evt_payload **evt_payload) +{ + unsigned long flags; + + if (*evt_payload == NULL) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid payload core %d", + csid_hw->hw_intf->hw_idx); + return -EINVAL; + } + spin_lock_irqsave(&csid_hw->spin_lock, flags); + list_add_tail(&(*evt_payload)->list, + &csid_hw->free_payload_list); + *evt_payload = NULL; + spin_unlock_irqrestore(&csid_hw->spin_lock, flags); + + return 0; +} +static char *cam_csid_status_to_str(uint32_t status) +{ + switch (status) { + case TFE_CSID_IRQ_REG_TOP: + return "TOP"; + case TFE_CSID_IRQ_REG_RX: + return "RX"; + case TFE_CSID_IRQ_REG_IPP: + return "IPP"; + case TFE_CSID_IRQ_REG_RDI0: + return "RDI0"; + case TFE_CSID_IRQ_REG_RDI1: + return "RDI1"; + case TFE_CSID_IRQ_REG_RDI2: + return "RDI2"; + default: + return "Invalid IRQ"; + } +} + +static int cam_csid_evt_bottom_half_handler( + void *handler_priv, + void *evt_payload_priv) +{ + struct cam_tfe_csid_hw *csid_hw; + struct cam_csid_evt_payload *evt_payload; + int i; + int rc = 0; + struct cam_isp_hw_event_info event_info; + + if (!handler_priv || !evt_payload_priv) { + CAM_ERR(CAM_ISP, + "Invalid Param handler_priv %pK evt_payload_priv %pK", + handler_priv, evt_payload_priv); + return 0; + } + + csid_hw = (struct cam_tfe_csid_hw *)handler_priv; + evt_payload = (struct cam_csid_evt_payload *)evt_payload_priv; + + if (!csid_hw->event_cb || !csid_hw->event_cb_priv) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "hw_idx %d Invalid args %pK %pK", + csid_hw->hw_intf->hw_idx, + csid_hw->event_cb, + csid_hw->event_cb_priv); + goto end; + } + + if (csid_hw->event_cb_priv != evt_payload->priv) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "hw_idx %d priv mismatch %pK, %pK", + csid_hw->hw_intf->hw_idx, + csid_hw->event_cb_priv, + evt_payload->priv); + goto end; + } + + CAM_ERR_RATE_LIMIT(CAM_ISP, "idx %d err %d phy %d", + csid_hw->hw_intf->hw_idx, + evt_payload->evt_type, + csid_hw->csi2_rx_cfg.phy_sel); + + for (i = 0; i < TFE_CSID_IRQ_REG_MAX; i++) + CAM_ERR_RATE_LIMIT(CAM_ISP, "status %s: %x", + cam_csid_status_to_str(i), + evt_payload->irq_status[i]); + + /* this hunk can be extended to handle more cases + * which we want to offload to bottom half from + * irq handlers + */ + event_info.err_type = evt_payload->evt_type; + event_info.hw_idx = evt_payload->hw_idx; + + switch (evt_payload->evt_type) { + case CAM_ISP_HW_ERROR_CSID_FATAL: + if (csid_hw->fatal_err_detected) + break; + csid_hw->fatal_err_detected = true; + rc = csid_hw->event_cb(NULL, + CAM_ISP_HW_EVENT_ERROR, (void *)&event_info); + break; + + default: + CAM_DBG(CAM_ISP, "CSID[%d] invalid error type %d", + csid_hw->hw_intf->hw_idx, + evt_payload->evt_type); + break; + } +end: + cam_csid_put_evt_payload(csid_hw, &evt_payload); + return 0; +} + +static int cam_csid_handle_hw_err_irq( + struct cam_tfe_csid_hw *csid_hw, + int evt_type, + uint32_t *irq_status) +{ + int rc = 0; + int i; + void *bh_cmd = NULL; + struct cam_csid_evt_payload *evt_payload; + + CAM_DBG(CAM_ISP, "CSID[%d] error %d", + csid_hw->hw_intf->hw_idx, evt_type); + + rc = cam_csid_get_evt_payload(csid_hw, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "No free payload core %d", + csid_hw->hw_intf->hw_idx); + return rc; + } + + rc = tasklet_bh_api.get_bh_payload_func(csid_hw->tasklet, &bh_cmd); + if (rc || !bh_cmd) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID[%d] Can not get cmd for tasklet, evt_type %d", + csid_hw->hw_intf->hw_idx, + evt_type); + return rc; + } + + evt_payload->evt_type = evt_type; + evt_payload->priv = csid_hw->event_cb_priv; + evt_payload->hw_idx = csid_hw->hw_intf->hw_idx; + + for (i = 0; i < TFE_CSID_IRQ_REG_MAX; i++) + evt_payload->irq_status[i] = irq_status[i]; + + tasklet_bh_api.bottom_half_enqueue_func(csid_hw->tasklet, + bh_cmd, + csid_hw, + evt_payload, + cam_csid_evt_bottom_half_handler); + + return rc; +} + +irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) +{ + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_soc_info *soc_info; + const struct cam_tfe_csid_reg_offset *csid_reg; + const struct cam_tfe_csid_csi2_rx_reg_offset *csi2_reg; + uint32_t irq_status[TFE_CSID_IRQ_REG_MAX]; + bool fatal_err_detected = false, is_error_irq = false; + uint32_t sof_irq_debug_en = 0; + unsigned long flags; + uint32_t i, val; + + + if (!data) { + CAM_ERR(CAM_ISP, "CSID: Invalid arguments"); + return IRQ_HANDLED; + } + + csid_hw = (struct cam_tfe_csid_hw *)data; + CAM_DBG(CAM_ISP, "CSID %d IRQ Handling", csid_hw->hw_intf->hw_idx); + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + csi2_reg = csid_reg->csi2_reg; + + /* read */ + irq_status[TFE_CSID_IRQ_REG_TOP] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_status_addr); + + irq_status[TFE_CSID_IRQ_REG_RX] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_status_addr); + + if (csid_hw->pxl_pipe_enable) + irq_status[TFE_CSID_IRQ_REG_IPP] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_status_addr); + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) + irq_status[i] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_status_addr); + + /* clear */ + cam_io_w_mb(irq_status[TFE_CSID_IRQ_REG_TOP], + soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + + cam_io_w_mb(irq_status[TFE_CSID_IRQ_REG_RX], + soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); + + if (csid_hw->pxl_pipe_enable) + cam_io_w_mb(irq_status[TFE_CSID_IRQ_REG_IPP], + soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_clear_addr); + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { + cam_io_w_mb(irq_status[i], + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr); + } + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + + /* Software register reset complete*/ + if (irq_status[TFE_CSID_IRQ_REG_TOP]) + complete(&csid_hw->csid_top_complete); + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + BIT(csid_reg->csi2_reg->csi2_rst_done_shift_val)) + complete(&csid_hw->csid_csi2_complete); + + spin_lock_irqsave(&csid_hw->spin_lock, flags); + if (csid_hw->device_enabled == 1) { + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW) { + fatal_err_detected = true; + goto handle_fatal_error; + } + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW) { + fatal_err_detected = true; + goto handle_fatal_error; + } + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW) { + fatal_err_detected = true; + goto handle_fatal_error; + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW) { + fatal_err_detected = true; + goto handle_fatal_error; + } + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION) + csid_hw->error_irq_count++; + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION) + csid_hw->error_irq_count++; + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW) + csid_hw->error_irq_count++; + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME) + csid_hw->error_irq_count++; + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_CRC) + is_error_irq = true; + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_ECC) + is_error_irq = true; + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_MMAPPED_VC_DT) + is_error_irq = true; + } +handle_fatal_error: + spin_unlock_irqrestore(&csid_hw->spin_lock, flags); + + if (csid_hw->error_irq_count || fatal_err_detected) + is_error_irq = true; + + if (csid_hw->error_irq_count > + CAM_TFE_CSID_MAX_IRQ_ERROR_COUNT) { + fatal_err_detected = true; + csid_hw->error_irq_count = 0; + } + + if (fatal_err_detected) { + /* Reset the Rx CFG registers */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg0_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + /* phy_sel starts from 1 and should never be zero*/ + if (csid_hw->csi2_rx_cfg.phy_sel > 0) { + cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE, + CAM_SUBDEV_MESSAGE_IRQ_ERR, + (csid_hw->csi2_rx_cfg.phy_sel - 1)); + } + cam_csid_handle_hw_err_irq(csid_hw, + CAM_ISP_HW_ERROR_CSID_FATAL, irq_status); + } + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOT_IRQ) { + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL0_EOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL1_EOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL2_EOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL3_EOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + } + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOT_IRQ) { + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL0_SOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL1_SOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL2_SOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL3_SOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + } + + if ((csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) && + (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d LONG_PKT_CAPTURED", + csid_hw->hw_intf->hw_idx); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_long_pkt_0_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d long packet VC :%d DT:%d WC:%d", + csid_hw->hw_intf->hw_idx, + (val >> 22), ((val >> 16) & 0x3F), (val & 0xFFFF)); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_long_pkt_1_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d long packet ECC :%d", + csid_hw->hw_intf->hw_idx, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_long_pkt_ftr_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d long pkt cal CRC:%d expected CRC:%d", + csid_hw->hw_intf->hw_idx, (val >> 16), (val & 0xFFFF)); + } + if ((csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) && + (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d SHORT_PKT_CAPTURED", + csid_hw->hw_intf->hw_idx); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_short_pkt_0_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d short pkt VC :%d DT:%d LC:%d", + csid_hw->hw_intf->hw_idx, + (val >> 22), ((val >> 16) & 0x3F), (val & 0xFFFF)); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_short_pkt_1_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d short packet ECC :%d", + csid_hw->hw_intf->hw_idx, val); + } + + if ((csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) && + (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_PKT_HDR_CAPTURED", + csid_hw->hw_intf->hw_idx); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_cphy_pkt_hdr_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d cphy packet VC :%d DT:%d WC:%d", + csid_hw->hw_intf->hw_idx, + (val >> 22), ((val >> 16) & 0x3F), (val & 0xFFFF)); + } + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_RST_IRQ_LOG) { + + if (irq_status[TFE_CSID_IRQ_REG_IPP] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID IPP reset complete"); + + if (irq_status[TFE_CSID_IRQ_REG_TOP]) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID TOP reset complete"); + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + BIT(csid_reg->csi2_reg->csi2_rst_done_shift_val)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID RX reset complete"); + } + + /* read the IPP errors */ + if (csid_hw->pxl_pipe_enable) { + /* IPP reset done bit */ + if (irq_status[TFE_CSID_IRQ_REG_IPP] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { + CAM_DBG(CAM_ISP, "CSID IPP reset complete"); + complete(&csid_hw->csid_ipp_complete); + } + + if ((irq_status[TFE_CSID_IRQ_REG_IPP] & + TFE_CSID_PATH_INFO_INPUT_SOF) && + (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP SOF received", + csid_hw->hw_intf->hw_idx); + if (csid_hw->sof_irq_triggered) + csid_hw->irq_debug_cnt++; + } + + if ((irq_status[TFE_CSID_IRQ_REG_IPP] & + TFE_CSID_PATH_INFO_INPUT_EOF) && + (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOF_IRQ)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP EOF received", + csid_hw->hw_intf->hw_idx); + } + + if (irq_status[TFE_CSID_IRQ_REG_IPP] & + TFE_CSID_PATH_ERROR_FIFO_OVERFLOW) { + /* Stop IPP path immediately */ + cam_io_w_mb(CAM_TFE_CSID_HALT_IMMEDIATELY, + soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_ctrl_addr); + is_error_irq = true; + } + + if (irq_status[TFE_CSID_IRQ_REG_IPP] & + TFE_CSID_PATH_IPP_ERROR_CCIF_VIOLATION) + is_error_irq = true; + + } + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { + + if ((irq_status[i] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) && + (csid_hw->csid_debug & + TFE_CSID_DEBUG_ENABLE_RST_IRQ_LOG)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID RDI%d reset complete", i); + + if (irq_status[i] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { + CAM_DBG(CAM_ISP, "CSID RDI%d reset complete", i); + complete(&csid_hw->csid_rdin_complete[i]); + } + + if ((irq_status[i] & TFE_CSID_PATH_INFO_INPUT_SOF) && + (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID RDI:%d SOF received", i); + if (csid_hw->sof_irq_triggered) + csid_hw->irq_debug_cnt++; + } + + if ((irq_status[i] & TFE_CSID_PATH_INFO_INPUT_EOF) && + (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOF_IRQ)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID RDI:%d EOF received", i); + } + + if (irq_status[i] & TFE_CSID_PATH_ERROR_FIFO_OVERFLOW) { + /* Stop RDI path immediately */ + is_error_irq = true; + cam_io_w_mb(CAM_TFE_CSID_HALT_IMMEDIATELY, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_ctrl_addr); + } + + if ((irq_status[i] & TFE_CSID_PATH_RDI_OVERFLOW_IRQ) || + (irq_status[i] & + TFE_CSID_PATH_RDI_ERROR_CCIF_VIOLATION)) + is_error_irq = true; + } + + if (is_error_irq) + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID %d irq status TOP: 0x%x RX: 0x%x IPP: 0x%x RDI0: 0x%x RDI1: 0x%x RDI2: 0x%x CSID clk:%d", + csid_hw->hw_intf->hw_idx, + irq_status[TFE_CSID_IRQ_REG_TOP], + irq_status[TFE_CSID_IRQ_REG_RX], + irq_status[TFE_CSID_IRQ_REG_IPP], + irq_status[TFE_CSID_IRQ_REG_RDI0], + irq_status[TFE_CSID_IRQ_REG_RDI1], + irq_status[TFE_CSID_IRQ_REG_RDI2], + csid_hw->clk_rate); + + if (csid_hw->irq_debug_cnt >= CAM_TFE_CSID_IRQ_SOF_DEBUG_CNT_MAX) { + cam_tfe_csid_sof_irq_debug(csid_hw, &sof_irq_debug_en); + csid_hw->irq_debug_cnt = 0; + } + + CAM_DBG(CAM_ISP, "IRQ Handling exit"); + return IRQ_HANDLED; +} + +int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, + uint32_t csid_idx) +{ + int rc = -EINVAL; + uint32_t i; + struct cam_tfe_csid_path_cfg *path_data; + struct cam_hw_info *csid_hw_info; + struct cam_tfe_csid_hw *tfe_csid_hw = NULL; + const struct cam_tfe_csid_reg_offset *csid_reg; + int pixel_pipe_supported = true; + + if (csid_idx >= CAM_TFE_CSID_HW_NUM_MAX) { + CAM_ERR(CAM_ISP, "Invalid csid index:%d", csid_idx); + return rc; + } + + csid_hw_info = (struct cam_hw_info *) csid_hw_intf->hw_priv; + tfe_csid_hw = (struct cam_tfe_csid_hw *) csid_hw_info->core_info; + + tfe_csid_hw->hw_intf = csid_hw_intf; + tfe_csid_hw->hw_info = csid_hw_info; + csid_reg = tfe_csid_hw->csid_info->csid_reg; + + tfe_csid_hw->device_enabled = 0; + tfe_csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; + + if (!cam_cpas_is_feature_supported(CAM_CPAS_ISP_FUSE_ID, + csid_idx)) { + CAM_INFO(CAM_ISP, "TFE:%d is not supported", + csid_idx); + rc = -EINVAL; + goto err; + } + + CAM_DBG(CAM_ISP, "type %d index %d supported", + tfe_csid_hw->hw_intf->hw_type, csid_idx); + + if (!cam_cpas_is_feature_supported(CAM_CPAS_ISP_PIX_FUSE_ID, + csid_idx)) { + pixel_pipe_supported = false; + CAM_INFO(CAM_ISP, "TFE:%d PIX path is not supported", + csid_idx); + } + + rc = cam_tfe_csid_init_soc_resources(&tfe_csid_hw->hw_info->soc_info, + cam_tfe_csid_irq, tfe_csid_hw); + if (rc < 0) { + CAM_ERR(CAM_ISP, "CSID:%d Failed to init_soc", csid_idx); + goto err; + } + + mutex_init(&tfe_csid_hw->hw_info->hw_mutex); + spin_lock_init(&tfe_csid_hw->hw_info->hw_lock); + spin_lock_init(&tfe_csid_hw->spin_lock); + init_completion(&tfe_csid_hw->hw_info->hw_complete); + + init_completion(&tfe_csid_hw->csid_top_complete); + init_completion(&tfe_csid_hw->csid_csi2_complete); + init_completion(&tfe_csid_hw->csid_ipp_complete); + for (i = 0; i < CAM_TFE_CSID_RDI_MAX; i++) + init_completion(&tfe_csid_hw->csid_rdin_complete[i]); + + tfe_csid_hw->hw_intf->hw_ops.get_hw_caps = cam_tfe_csid_get_hw_caps; + tfe_csid_hw->hw_intf->hw_ops.init = cam_tfe_csid_init_hw; + tfe_csid_hw->hw_intf->hw_ops.deinit = cam_tfe_csid_deinit_hw; + tfe_csid_hw->hw_intf->hw_ops.reset = cam_tfe_csid_reset; + tfe_csid_hw->hw_intf->hw_ops.reserve = cam_tfe_csid_reserve; + tfe_csid_hw->hw_intf->hw_ops.release = cam_tfe_csid_release; + tfe_csid_hw->hw_intf->hw_ops.start = cam_tfe_csid_start; + tfe_csid_hw->hw_intf->hw_ops.stop = cam_tfe_csid_stop; + tfe_csid_hw->hw_intf->hw_ops.read = cam_tfe_csid_read; + tfe_csid_hw->hw_intf->hw_ops.write = cam_tfe_csid_write; + tfe_csid_hw->hw_intf->hw_ops.process_cmd = cam_tfe_csid_process_cmd; + + /* reset the cid values */ + for (i = 0; i < CAM_TFE_CSID_CID_MAX; i++) { + tfe_csid_hw->cid_res[i].vc = 0; + tfe_csid_hw->cid_res[i].dt = 0; + tfe_csid_hw->cid_res[i].cnt = 0; + } + + /* Initialize the IPP resources */ + if (pixel_pipe_supported) { + CAM_DBG(CAM_ISP, "initializing the pix path"); + + tfe_csid_hw->ipp_res.res_type = CAM_ISP_RESOURCE_PIX_PATH; + tfe_csid_hw->ipp_res.res_id = CAM_TFE_CSID_PATH_RES_IPP; + tfe_csid_hw->ipp_res.res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + tfe_csid_hw->ipp_res.hw_intf = tfe_csid_hw->hw_intf; + path_data = kzalloc(sizeof(*path_data), + GFP_KERNEL); + if (!path_data) { + rc = -ENOMEM; + goto err; + } + tfe_csid_hw->ipp_res.res_priv = path_data; + tfe_csid_hw->pxl_pipe_enable = 1; + } + + /* Initialize the RDI resource */ + for (i = 0; i < tfe_csid_hw->csid_info->csid_reg->cmn_reg->num_rdis; + i++) { + /* res type is from RDI 0 to RDI2 */ + tfe_csid_hw->rdi_res[i].res_type = + CAM_ISP_RESOURCE_PIX_PATH; + tfe_csid_hw->rdi_res[i].res_id = i; + tfe_csid_hw->rdi_res[i].res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + tfe_csid_hw->rdi_res[i].hw_intf = tfe_csid_hw->hw_intf; + + path_data = kzalloc(sizeof(*path_data), + GFP_KERNEL); + if (!path_data) { + rc = -ENOMEM; + goto err; + } + tfe_csid_hw->rdi_res[i].res_priv = path_data; + } + + rc = cam_tasklet_init(&tfe_csid_hw->tasklet, tfe_csid_hw, csid_idx); + if (rc) { + CAM_ERR(CAM_ISP, "Unable to create CSID tasklet rc %d", rc); + goto err; + } + + INIT_LIST_HEAD(&tfe_csid_hw->free_payload_list); + for (i = 0; i < CAM_CSID_EVT_PAYLOAD_MAX; i++) { + INIT_LIST_HEAD(&tfe_csid_hw->evt_payload[i].list); + list_add_tail(&tfe_csid_hw->evt_payload[i].list, + &tfe_csid_hw->free_payload_list); + } + + tfe_csid_hw->csid_debug = 0; + tfe_csid_hw->error_irq_count = 0; + tfe_csid_hw->prev_boot_timestamp = 0; + + /* Check if ppi bridge is present or not? */ + tfe_csid_hw->ppi_enable = of_property_read_bool( + csid_hw_info->soc_info.pdev->dev.of_node, + "ppi-enable"); + + if (!tfe_csid_hw->ppi_enable) + return 0; + + /* Initialize the PPI bridge */ + for (i = 0; i < CAM_CSID_PPI_HW_MAX; i++) { + rc = cam_csid_ppi_hw_init(&tfe_csid_hw->ppi_hw_intf[i], i); + if (rc < 0) { + CAM_INFO(CAM_ISP, "PPI init failed for PPI %d", i); + rc = 0; + break; + } + } + + return 0; +err: + if (rc) { + kfree(tfe_csid_hw->ipp_res.res_priv); + for (i = 0; i < + tfe_csid_hw->csid_info->csid_reg->cmn_reg->num_rdis; + i++) + kfree(tfe_csid_hw->rdi_res[i].res_priv); + } + + return rc; +} + + +int cam_tfe_csid_hw_deinit(struct cam_tfe_csid_hw *tfe_csid_hw) +{ + int rc = -EINVAL; + uint32_t i; + + if (!tfe_csid_hw) { + CAM_ERR(CAM_ISP, "Invalid param"); + return rc; + } + + /* release the privdate data memory from resources */ + kfree(tfe_csid_hw->ipp_res.res_priv); + + for (i = 0; i < + tfe_csid_hw->csid_info->csid_reg->cmn_reg->num_rdis; + i++) { + kfree(tfe_csid_hw->rdi_res[i].res_priv); + } + + cam_tfe_csid_deinit_soc_resources(&tfe_csid_hw->hw_info->soc_info); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h new file mode 100644 index 0000000000000000000000000000000000000000..d0935689fd01ee4b0cac5dbc232ba5dfcc7b5b92 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h @@ -0,0 +1,456 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_CSID_HW_H_ +#define _CAM_TFE_CSID_HW_H_ + +#include "cam_hw.h" +#include "cam_tfe_csid_hw_intf.h" +#include "cam_tfe_csid_soc.h" +#include "cam_csid_ppi_core.h" + +#define CAM_TFE_CSID_CID_MAX 4 + +/* Each word is taken as uint32_t, for dumping uint64_t count as 2 words + * 1. soc_index + * 2. clk_rate --> uint64_t -> 2 words + */ +#define CAM_TFE_CSID_DUMP_MISC_NUM_WORDS 3 + +#define TFE_CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED BIT(0) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED BIT(1) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED BIT(2) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED BIT(3) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED BIT(4) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED BIT(5) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED BIT(6) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED BIT(7) +#define TFE_CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED BIT(8) +#define TFE_CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED BIT(9) +#define TFE_CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED BIT(10) +#define TFE_CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION BIT(11) +#define TFE_CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION BIT(12) +#define TFE_CSID_CSI2_RX_ERROR_CPHY_PH_CRC BIT(13) +#define TFE_CSID_CSI2_RX_WARNING_ECC BIT(14) +#define TFE_CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW BIT(15) +#define TFE_CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW BIT(16) +#define TFE_CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW BIT(17) +#define TFE_CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW BIT(18) +#define TFE_CSID_CSI2_RX_ERROR_CRC BIT(19) +#define TFE_CSID_CSI2_RX_ERROR_ECC BIT(20) +#define TFE_CSID_CSI2_RX_ERROR_MMAPPED_VC_DT BIT(21) +#define TFE_CSID_CSI2_RX_ERROR_UNMAPPED_VC_DT BIT(22) +#define TFE_CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW BIT(23) +#define TFE_CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME BIT(24) +#define TFE_CSID_CSI2_RX_INFO_RST_DONE BIT(27) + +#define TFE_CSID_PATH_INFO_RST_DONE BIT(1) +#define TFE_CSID_PATH_ERROR_FIFO_OVERFLOW BIT(2) +#define TFE_CSID_PATH_INFO_INPUT_EOF BIT(9) +#define TFE_CSID_PATH_INFO_INPUT_EOL BIT(10) +#define TFE_CSID_PATH_INFO_INPUT_SOL BIT(11) +#define TFE_CSID_PATH_INFO_INPUT_SOF BIT(12) +#define TFE_CSID_PATH_IPP_ERROR_CCIF_VIOLATION BIT(15) +#define TFE_CSID_PATH_IPP_OVERFLOW_IRQ BIT(16) +#define TFE_CSID_PATH_IPP_FRAME_DROP BIT(17) +#define TFE_CSID_PATH_RDI_FRAME_DROP BIT(16) +#define TFE_CSID_PATH_RDI_OVERFLOW_IRQ BIT(17) +#define TFE_CSID_PATH_RDI_ERROR_CCIF_VIOLATION BIT(18) + +/* + * Debug values enable the corresponding interrupts and debug logs provide + * necessary information + */ +#define TFE_CSID_DEBUG_ENABLE_SOF_IRQ BIT(0) +#define TFE_CSID_DEBUG_ENABLE_EOF_IRQ BIT(1) +#define TFE_CSID_DEBUG_ENABLE_SOT_IRQ BIT(2) +#define TFE_CSID_DEBUG_ENABLE_EOT_IRQ BIT(3) +#define TFE_CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE BIT(4) +#define TFE_CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE BIT(5) +#define TFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE BIT(6) +#define TFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO BIT(7) +#define TFE_CSID_DEBUG_DISABLE_EARLY_EOF BIT(8) +#define TFE_CSID_DEBUG_ENABLE_RST_IRQ_LOG BIT(9) + +#define CAM_CSID_EVT_PAYLOAD_MAX 10 + +/* enum cam_csid_path_halt_mode select the path halt mode control */ +enum cam_tfe_csid_path_halt_mode { + TFE_CSID_HALT_MODE_INTERNAL, + TFE_CSID_HALT_MODE_GLOBAL, + TFE_CSID_HALT_MODE_MASTER, + TFE_CSID_HALT_MODE_SLAVE, +}; + +/** + *enum cam_csid_path_timestamp_stb_sel - select the sof/eof strobes used to + * capture the timestamp + */ +enum cam_tfe_csid_path_timestamp_stb_sel { + TFE_CSID_TIMESTAMP_STB_PRE_HALT, + TFE_CSID_TIMESTAMP_STB_POST_HALT, + TFE_CSID_TIMESTAMP_STB_POST_IRQ, + TFE_CSID_TIMESTAMP_STB_MAX, +}; + +struct cam_tfe_csid_pxl_reg_offset { + /* Pxl path register offsets*/ + uint32_t csid_pxl_irq_status_addr; + uint32_t csid_pxl_irq_mask_addr; + uint32_t csid_pxl_irq_clear_addr; + uint32_t csid_pxl_irq_set_addr; + + uint32_t csid_pxl_cfg0_addr; + uint32_t csid_pxl_cfg1_addr; + uint32_t csid_pxl_ctrl_addr; + uint32_t csid_pxl_hcrop_addr; + uint32_t csid_pxl_vcrop_addr; + uint32_t csid_pxl_rst_strobes_addr; + uint32_t csid_pxl_status_addr; + uint32_t csid_pxl_misr_val_addr; + uint32_t csid_pxl_timestamp_curr0_sof_addr; + uint32_t csid_pxl_timestamp_curr1_sof_addr; + uint32_t csid_pxl_timestamp_perv0_sof_addr; + uint32_t csid_pxl_timestamp_perv1_sof_addr; + uint32_t csid_pxl_timestamp_curr0_eof_addr; + uint32_t csid_pxl_timestamp_curr1_eof_addr; + uint32_t csid_pxl_timestamp_perv0_eof_addr; + uint32_t csid_pxl_timestamp_perv1_eof_addr; + uint32_t csid_pxl_err_recovery_cfg0_addr; + uint32_t csid_pxl_err_recovery_cfg1_addr; + uint32_t csid_pxl_err_recovery_cfg2_addr; + + /* configuration */ + uint32_t pix_store_en_shift_val; + uint32_t early_eof_en_shift_val; + uint32_t halt_master_sel_shift; + uint32_t halt_mode_shift; + uint32_t halt_master_sel_master_val; + uint32_t halt_master_sel_slave_val; +}; + +struct cam_tfe_csid_rdi_reg_offset { + uint32_t csid_rdi_irq_status_addr; + uint32_t csid_rdi_irq_mask_addr; + uint32_t csid_rdi_irq_clear_addr; + uint32_t csid_rdi_irq_set_addr; + + /*RDI N register address */ + uint32_t csid_rdi_cfg0_addr; + uint32_t csid_rdi_cfg1_addr; + uint32_t csid_rdi_ctrl_addr; + uint32_t csid_rdi_rst_strobes_addr; + uint32_t csid_rdi_status_addr; + uint32_t csid_rdi_misr_val0_addr; + uint32_t csid_rdi_misr_val1_addr; + uint32_t csid_rdi_timestamp_curr0_sof_addr; + uint32_t csid_rdi_timestamp_curr1_sof_addr; + uint32_t csid_rdi_timestamp_prev0_sof_addr; + uint32_t csid_rdi_timestamp_prev1_sof_addr; + uint32_t csid_rdi_timestamp_curr0_eof_addr; + uint32_t csid_rdi_timestamp_curr1_eof_addr; + uint32_t csid_rdi_timestamp_prev0_eof_addr; + uint32_t csid_rdi_timestamp_prev1_eof_addr; + uint32_t csid_rdi_err_recovery_cfg0_addr; + uint32_t csid_rdi_err_recovery_cfg1_addr; + uint32_t csid_rdi_err_recovery_cfg2_addr; + uint32_t csid_rdi_byte_cntr_ping_addr; + uint32_t csid_rdi_byte_cntr_pong_addr; + + /* configuration */ + uint32_t packing_format; +}; + +struct cam_tfe_csid_csi2_rx_reg_offset { + uint32_t csid_csi2_rx_irq_status_addr; + uint32_t csid_csi2_rx_irq_mask_addr; + uint32_t csid_csi2_rx_irq_clear_addr; + uint32_t csid_csi2_rx_irq_set_addr; + uint32_t csid_csi2_rx_cfg0_addr; + uint32_t csid_csi2_rx_cfg1_addr; + uint32_t csid_csi2_rx_capture_ctrl_addr; + uint32_t csid_csi2_rx_rst_strobes_addr; + uint32_t csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr; + uint32_t csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr; + uint32_t csid_csi2_rx_captured_short_pkt_0_addr; + uint32_t csid_csi2_rx_captured_short_pkt_1_addr; + uint32_t csid_csi2_rx_captured_long_pkt_0_addr; + uint32_t csid_csi2_rx_captured_long_pkt_1_addr; + uint32_t csid_csi2_rx_captured_long_pkt_ftr_addr; + uint32_t csid_csi2_rx_captured_cphy_pkt_hdr_addr; + uint32_t csid_csi2_rx_total_pkts_rcvd_addr; + uint32_t csid_csi2_rx_stats_ecc_addr; //no + uint32_t csid_csi2_rx_total_crc_err_addr; + + /*configurations */ + uint32_t phy_sel_base; + uint32_t csi2_rst_srb_all; + uint32_t csi2_rst_done_shift_val; + uint32_t csi2_irq_mask_all; + uint32_t csi2_misr_enable_shift_val; + uint32_t csi2_vc_mode_shift_val; + uint32_t csi2_capture_long_pkt_en_shift; + uint32_t csi2_capture_short_pkt_en_shift; + uint32_t csi2_capture_cphy_pkt_en_shift; + uint32_t csi2_capture_long_pkt_dt_shift; + uint32_t csi2_capture_long_pkt_vc_shift; + uint32_t csi2_capture_short_pkt_vc_shift; + uint32_t csi2_capture_cphy_pkt_dt_shift; + uint32_t csi2_capture_cphy_pkt_vc_shift; + uint32_t csi2_rx_phy_num_mask; + uint32_t csi2_rx_long_pkt_hdr_rst_stb_shift; + uint32_t csi2_rx_short_pkt_hdr_rst_stb_shift; +}; + +struct cam_tfe_csid_common_reg_offset { + /* MIPI CSID registers */ + uint32_t csid_hw_version_addr; + uint32_t csid_cfg0_addr; + uint32_t csid_ctrl_addr; + uint32_t csid_rst_strobes_addr; + + uint32_t csid_test_bus_ctrl_addr; + uint32_t csid_top_irq_status_addr; + uint32_t csid_top_irq_mask_addr; + uint32_t csid_top_irq_clear_addr; + uint32_t csid_top_irq_set_addr; + uint32_t csid_irq_cmd_addr; + + /*configurations */ + uint32_t major_version; + uint32_t minor_version; + uint32_t version_incr; + uint32_t num_rdis; + uint32_t num_pix; + uint32_t csid_reg_rst_stb; + uint32_t csid_rst_stb; + uint32_t csid_rst_stb_sw_all; + uint32_t ipp_path_rst_stb_all; + uint32_t rdi_path_rst_stb_all; + uint32_t path_rst_done_shift_val; + uint32_t path_en_shift_val; + uint32_t dt_id_shift_val; + uint32_t vc_shift_val; + uint32_t dt_shift_val; + uint32_t fmt_shift_val; + uint32_t plain_fmt_shit_val; + uint32_t crop_v_en_shift_val; + uint32_t crop_h_en_shift_val; + uint32_t crop_shift; + uint32_t ipp_irq_mask_all; + uint32_t rdi_irq_mask_all; + uint32_t top_tfe2_pix_pipe_fuse_reg; + uint32_t top_tfe2_fuse_reg; +}; + +/** + * struct cam_tfe_csid_reg_offset- CSID instance register info + * + * @cmn_reg: csid common registers info + * @ipp_reg: ipp register offset information + * @ppp_reg: ppp register offset information + * @rdi_reg: rdi register offser information + * + */ +struct cam_tfe_csid_reg_offset { + const struct cam_tfe_csid_common_reg_offset *cmn_reg; + const struct cam_tfe_csid_csi2_rx_reg_offset *csi2_reg; + const struct cam_tfe_csid_pxl_reg_offset *ipp_reg; + const struct cam_tfe_csid_rdi_reg_offset *rdi_reg[CAM_TFE_CSID_RDI_MAX]; +}; + +/** + * struct cam_tfe_csid_hw_info- CSID HW info + * + * @csid_reg: csid register offsets + * @hw_dts_version: HW DTS version + * @csid_max_clk: maximim csid clock + * + */ +struct cam_tfe_csid_hw_info { + const struct cam_tfe_csid_reg_offset *csid_reg; + uint32_t hw_dts_version; + uint32_t csid_max_clk; +}; + +/** + * struct cam_tfe_csid_csi2_rx_cfg- csid csi2 rx configuration data + * @phy_sel: input resource type for sensor only + * @lane_type: lane type: c-phy or d-phy + * @lane_num : active lane number + * @lane_cfg: lane configurations: 4 bits per lane + * + */ +struct cam_tfe_csid_csi2_rx_cfg { + uint32_t phy_sel; + uint32_t lane_type; + uint32_t lane_num; + uint32_t lane_cfg; +}; + +/** + * struct cam_tfe_csid_cid_data- cid configuration private data + * + * @vc: Virtual channel + * @dt: Data type + * @cnt: Cid resource reference count. + * + */ +struct cam_tfe_csid_cid_data { + uint32_t vc; + uint32_t dt; + uint32_t cnt; +}; + +/** + * struct cam_tfe_csid_path_cfg- csid path configuration details. It is stored + * as private data for IPP/ RDI paths + * @vc : Virtual channel number + * @dt : Data type number + * @cid cid number, it is same as DT_ID number in HW + * @in_format: input decode format + * @out_format: output format + * @crop_enable: crop is enable or disabled, if enabled + * then remaining parameters are valid. + * @start_pixel: start pixel + * @end_pixel: end_pixel + * @width: width + * @start_line: start line + * @end_line: end_line + * @height: heigth + * @sync_mode: Applicable for IPP/RDI path reservation + * Reserving the path for master IPP or slave IPP + * master (set value 1), Slave ( set value 2) + * for RDI, set mode to none + * @master_idx: For Slave reservation, Give master TFE instance Index. + * Slave will synchronize with master Start and stop operations + * @clk_rate Clock rate + * @sensor_width Sensor width in pixel + * @sensor_height Sensor height in pixel + * @sensor_fps Sensor fps + * @sensor_hbi Sensor horizontal blanking interval + * @sensor_vbi Sensor vertical blanking interval + * + */ +struct cam_tfe_csid_path_cfg { + uint32_t vc; + uint32_t dt; + uint32_t cid; + uint32_t in_format; + uint32_t out_format; + bool crop_enable; + uint32_t start_pixel; + uint32_t end_pixel; + uint32_t width; + uint32_t start_line; + uint32_t end_line; + uint32_t height; + enum cam_isp_hw_sync_mode sync_mode; + uint32_t master_idx; + uint64_t clk_rate; + uint32_t sensor_width; + uint32_t sensor_height; + uint32_t sensor_fps; + uint32_t sensor_hbi; + uint32_t sensor_vbi; +}; + +/** + * struct cam_csid_evt_payload- payload for csid hw event + * @list : list head + * @evt_type : Event type from CSID + * @irq_status : IRQ Status register + * @hw_idx : Hw index + * @priv : Private data of payload + */ +struct cam_csid_evt_payload { + struct list_head list; + uint32_t evt_type; + uint32_t irq_status[TFE_CSID_IRQ_REG_MAX]; + uint32_t hw_idx; + void *priv; +}; + +/** + * struct cam_tfe_csid_hw- csid hw device resources data + * + * @hw_intf: contain the csid hw interface information + * @hw_info: csid hw device information + * @csid_info: csid hw specific information + * @tasklet: tasklet to handle csid errors + * @free_payload_list: list head for payload + * @evt_payload: Event payload to be passed to tasklet + * @in_res_id: csid in resource type + * @csi2_rx_cfg: csi2 rx decoder configuration for csid + * @csi2_rx_reserve_cnt: csi2 reservations count value + * @ipp_res: image pixel path resource + * @rdi_res: raw dump image path resources + * @cid_res: cid resources values + * @csid_top_reset_complete: csid top reset completion + * @csid_csi2_reset_complete: csi2 reset completion + * @csid_ipp_reset_complete: ipp reset completion + * @csid_ppp_complete: ppp reset completion + * @csid_rdin_reset_complete: rdi n completion + * @csid_debug: csid debug information to enable the SOT, EOT, + * SOF, EOF, measure etc in the csid hw + * @clk_rate Clock rate + * @sof_irq_triggered: Flag is set on receiving event to enable sof irq + * incase of SOF freeze. + * @irq_debug_cnt: Counter to track sof irq's when above flag is set. + * @error_irq_count Error IRQ count, if continuous error irq comes + * need to stop the CSID and mask interrupts. + * @device_enabled Device enabled will set once CSID powered on and + * initial configuration are done. + * @lock_state csid spin lock + * @fatal_err_detected flag to indicate fatal errror is reported + * @event_cb: Callback function to hw mgr in case of hw events + * @event_cb_priv: Context data + * @prev_boot_timestamp previous frame bootime stamp + * @prev_qtimer_ts previous frame qtimer csid timestamp + * @ppi_hw_intf interface to ppi hardware + * @ppi_enabled flag to specify if the hardware has ppi bridge + * or not + * + */ +struct cam_tfe_csid_hw { + struct cam_hw_intf *hw_intf; + struct cam_hw_info *hw_info; + struct cam_tfe_csid_hw_info *csid_info; + void *tasklet; + struct list_head free_payload_list; + struct cam_csid_evt_payload evt_payload[CAM_CSID_EVT_PAYLOAD_MAX]; + uint32_t in_res_id; + struct cam_tfe_csid_csi2_rx_cfg csi2_rx_cfg; + uint32_t csi2_reserve_cnt; + uint32_t pxl_pipe_enable; + struct cam_isp_resource_node ipp_res; + struct cam_isp_resource_node rdi_res[CAM_TFE_CSID_RDI_MAX]; + struct cam_tfe_csid_cid_data cid_res[CAM_TFE_CSID_CID_MAX]; + struct completion csid_top_complete; + struct completion csid_csi2_complete; + struct completion csid_ipp_complete; + struct completion csid_rdin_complete[CAM_TFE_CSID_RDI_MAX]; + uint64_t csid_debug; + uint64_t clk_rate; + bool sof_irq_triggered; + uint32_t irq_debug_cnt; + uint32_t error_irq_count; + uint32_t device_enabled; + spinlock_t spin_lock; + bool fatal_err_detected; + cam_hw_mgr_event_cb_func event_cb; + void *event_cb_priv; + uint64_t prev_boot_timestamp; + uint64_t prev_qtimer_ts; + struct cam_hw_intf *ppi_hw_intf[CAM_CSID_PPI_HW_MAX]; + bool ppi_enable; +}; + +int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, + uint32_t csid_idx); + +int cam_tfe_csid_hw_deinit(struct cam_tfe_csid_hw *tfe_csid_hw); + +#endif /* _CAM_TFE_CSID_HW_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..edd391ae97812744453745df0c3993108cce17d4 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include "cam_tfe_csid_core.h" +#include "cam_tfe_csid_dev.h" +#include "cam_tfe_csid_hw_intf.h" +#include "cam_debug_util.h" + +static struct cam_hw_intf *cam_tfe_csid_hw_list[CAM_TFE_CSID_HW_NUM_MAX] = { + 0, 0, 0}; + +static char csid_dev_name[8]; + +int cam_tfe_csid_probe(struct platform_device *pdev) +{ + + struct cam_hw_intf *csid_hw_intf; + struct cam_hw_info *csid_hw_info; + struct cam_tfe_csid_hw *csid_dev = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_tfe_csid_hw_info *csid_hw_data = NULL; + uint32_t csid_dev_idx; + int rc = 0; + + CAM_DBG(CAM_ISP, "probe called"); + + csid_hw_intf = kzalloc(sizeof(*csid_hw_intf), GFP_KERNEL); + if (!csid_hw_intf) { + rc = -ENOMEM; + goto err; + } + + csid_hw_info = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!csid_hw_info) { + rc = -ENOMEM; + goto free_hw_intf; + } + + csid_dev = kzalloc(sizeof(struct cam_tfe_csid_hw), GFP_KERNEL); + if (!csid_dev) { + rc = -ENOMEM; + goto free_hw_info; + } + + /* get tfe csid hw index */ + of_property_read_u32(pdev->dev.of_node, "cell-index", &csid_dev_idx); + /* get tfe csid hw information */ + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_ISP, "No matching table for the tfe csid hw"); + rc = -EINVAL; + goto free_dev; + } + + memset(csid_dev_name, 0, sizeof(csid_dev_name)); + snprintf(csid_dev_name, sizeof(csid_dev_name), + "csid%1u", csid_dev_idx); + + csid_hw_intf->hw_idx = csid_dev_idx; + csid_hw_intf->hw_type = CAM_ISP_HW_TYPE_TFE_CSID; + csid_hw_intf->hw_priv = csid_hw_info; + + csid_hw_info->core_info = csid_dev; + csid_hw_info->soc_info.pdev = pdev; + csid_hw_info->soc_info.dev = &pdev->dev; + csid_hw_info->soc_info.dev_name = csid_dev_name; + csid_hw_info->soc_info.index = csid_dev_idx; + + csid_hw_data = (struct cam_tfe_csid_hw_info *)match_dev->data; + /* need to setup the pdev before call the tfe hw probe init */ + csid_dev->csid_info = csid_hw_data; + + rc = cam_tfe_csid_hw_probe_init(csid_hw_intf, csid_dev_idx); + if (rc) + goto free_dev; + + platform_set_drvdata(pdev, csid_dev); + CAM_DBG(CAM_ISP, "CSID:%d probe successful", + csid_hw_intf->hw_idx); + + if (csid_hw_intf->hw_idx < CAM_TFE_CSID_HW_NUM_MAX) + cam_tfe_csid_hw_list[csid_hw_intf->hw_idx] = csid_hw_intf; + else + goto free_dev; + + return 0; + +free_dev: + kfree(csid_dev); +free_hw_info: + kfree(csid_hw_info); +free_hw_intf: + kfree(csid_hw_intf); +err: + return rc; +} + +int cam_tfe_csid_remove(struct platform_device *pdev) +{ + struct cam_tfe_csid_hw *csid_dev = NULL; + struct cam_hw_intf *csid_hw_intf; + struct cam_hw_info *csid_hw_info; + + csid_dev = (struct cam_tfe_csid_hw *)platform_get_drvdata(pdev); + csid_hw_intf = csid_dev->hw_intf; + csid_hw_info = csid_dev->hw_info; + + CAM_DBG(CAM_ISP, "CSID:%d remove", + csid_dev->hw_intf->hw_idx); + + cam_tfe_csid_hw_deinit(csid_dev); + + /*release the csid device memory */ + kfree(csid_dev); + kfree(csid_hw_info); + kfree(csid_hw_intf); + return 0; +} + +int cam_tfe_csid_hw_init(struct cam_hw_intf **tfe_csid_hw, + uint32_t hw_idx) +{ + int rc = 0; + + if (cam_tfe_csid_hw_list[hw_idx]) { + *tfe_csid_hw = cam_tfe_csid_hw_list[hw_idx]; + } else { + *tfe_csid_hw = NULL; + rc = -1; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..cca3108fb4505d7a865d7d51f2b7ff62fafb8141 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_CSID_DEV_H_ +#define _CAM_TFE_CSID_DEV_H_ + +#include "cam_isp_hw.h" + +irqreturn_t cam_tfe_csid_irq(int irq_num, void *data); + +int cam_tfe_csid_probe(struct platform_device *pdev); +int cam_tfe_csid_remove(struct platform_device *pdev); + +#endif /*_CAM_TFE_CSID_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..f7d776a7cb5ebfa53b226c8514d18cf55d156ad8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#include +#include "cam_tfe_csid_soc.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" + + +int cam_tfe_csid_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t csid_irq_handler, void *irq_data) +{ + int rc = 0; + struct cam_cpas_register_params cpas_register_param; + struct cam_tfe_csid_soc_private *soc_private; + + soc_private = kzalloc(sizeof(struct cam_tfe_csid_soc_private), + GFP_KERNEL); + if (!soc_private) + return -ENOMEM; + + soc_info->soc_private = soc_private; + + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) + return rc; + + /* Need to see if we want post process the clock list */ + rc = cam_soc_util_request_platform_resource(soc_info, csid_irq_handler, + irq_data); + + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Error Request platform resources failed rc=%d", rc); + goto free_soc_private; + } + + memset(&cpas_register_param, 0, sizeof(cpas_register_param)); + strlcpy(cpas_register_param.identifier, "csid", + CAM_HW_IDENTIFIER_LENGTH); + cpas_register_param.cell_index = soc_info->index; + cpas_register_param.dev = soc_info->dev; + rc = cam_cpas_register_client(&cpas_register_param); + if (rc) { + CAM_ERR(CAM_ISP, "CPAS registration failed rc=%d", rc); + goto release_soc; + } else { + soc_private->cpas_handle = cpas_register_param.client_handle; + } + + return rc; + +release_soc: + cam_soc_util_release_platform_resource(soc_info); +free_soc_private: + kfree(soc_private); + + return rc; +} + +int cam_tfe_csid_deinit_soc_resources( + struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_tfe_csid_soc_private *soc_private; + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error soc_private NULL"); + return -ENODEV; + } + + rc = cam_cpas_unregister_client(soc_private->cpas_handle); + if (rc) + CAM_ERR(CAM_ISP, "CPAS unregistration failed rc=%d", rc); + + rc = cam_soc_util_release_platform_resource(soc_info); + + return rc; +} + +int cam_tfe_csid_enable_soc_resources( + struct cam_hw_soc_info *soc_info, enum cam_vote_level clk_level) +{ + int rc = 0; + struct cam_tfe_csid_soc_private *soc_private; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + + soc_private = soc_info->soc_private; + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_SVS_VOTE; + axi_vote.num_paths = 1; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_WRITE; + + axi_vote.axi_path[0].camnoc_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ab_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW; + + CAM_DBG(CAM_ISP, "csid camnoc_bw:%lld mnoc_ab_bw:%lld mnoc_ib_bw:%lld ", + axi_vote.axi_path[0].camnoc_bw, + axi_vote.axi_path[0].mnoc_ab_bw, + axi_vote.axi_path[0].mnoc_ib_bw); + + rc = cam_cpas_start(soc_private->cpas_handle, &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_ISP, "Error CPAS start failed"); + rc = -EFAULT; + goto end; + } + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + clk_level, true); + if (rc) { + CAM_ERR(CAM_ISP, "enable platform failed"); + goto stop_cpas; + } + + return rc; + +stop_cpas: + cam_cpas_stop(soc_private->cpas_handle); +end: + return rc; +} + +int cam_tfe_csid_disable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_tfe_csid_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + return -EINVAL; + } + soc_private = soc_info->soc_private; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) + CAM_ERR(CAM_ISP, "Disable platform failed"); + + rc = cam_cpas_stop(soc_private->cpas_handle); + if (rc) { + CAM_ERR(CAM_ISP, "Error CPAS stop failed rc=%d", rc); + return rc; + } + + return rc; +} + +int cam_tfe_csid_enable_tfe_force_clock_on(struct cam_hw_soc_info *soc_info, + uint32_t cpas_tfe_base_offset) +{ + int rc = 0; + struct cam_tfe_csid_soc_private *soc_private; + uint32_t cpass_tfe_force_clk_offset; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + return -EINVAL; + } + + soc_private = soc_info->soc_private; + cpass_tfe_force_clk_offset = + cpas_tfe_base_offset + (0x4 * soc_info->index); + rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REG_CPASTOP, + cpass_tfe_force_clk_offset, 1, 1); + + if (rc) + CAM_ERR(CAM_ISP, "CPASS set TFE:%d Force clock On failed", + soc_info->index); + else + CAM_DBG(CAM_ISP, "CPASS set TFE:%d Force clock On", + soc_info->index); + + return rc; +} + +int cam_tfe_csid_disable_tfe_force_clock_on(struct cam_hw_soc_info *soc_info, + uint32_t cpas_tfe_base_offset) +{ + int rc = 0; + struct cam_tfe_csid_soc_private *soc_private; + uint32_t cpass_tfe_force_clk_offset; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + return -EINVAL; + } + + soc_private = soc_info->soc_private; + cpass_tfe_force_clk_offset = + cpas_tfe_base_offset + (0x4 * soc_info->index); + rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REG_CPASTOP, + cpass_tfe_force_clk_offset, 1, 0); + + if (rc) + CAM_ERR(CAM_ISP, "CPASS set TFE:%d Force clock Off failed", + soc_info->index); + else + CAM_DBG(CAM_ISP, "CPASS set TFE:%d Force clock off", + soc_info->index); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..5da1ff71334385da638fcd2d00ad50a492bc5dc3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_CSID_SOC_H_ +#define _CAM_TFE_CSID_SOC_H_ + +#include "cam_isp_hw.h" + +/* + * struct cam_csid_soc_private: + * + * @Brief: Private SOC data specific to CSID HW Driver + * + * @cpas_handle: Handle returned on registering with CPAS driver. + * This handle is used for all further interface + * with CPAS. + */ +struct cam_tfe_csid_soc_private { + uint32_t cpas_handle; +}; + +/** + * struct csid_device_soc_info - CSID SOC info object + * + * @csi_vdd_voltage: Csi vdd voltage value + * + */ +struct cam_tfe_csid_device_soc_info { + int csi_vdd_voltage; +}; + +/** + * cam_tfe_csid_init_soc_resources() + * + * @brief: Csid initialization function for the soc info + * + * @soc_info: Soc info structure pointer + * @csid_irq_handler: Irq handler function to be registered + * @irq_data: Irq data for the callback function + * + */ +int cam_tfe_csid_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t csid_irq_handler, void *irq_data); + + +/** + * cam_tfe_csid_deinit_soc_resources() + * + * @brief: Csid de initialization function for the soc info + * + * @soc_info: Soc info structure pointer + * + */ +int cam_tfe_csid_deinit_soc_resources(struct cam_hw_soc_info *soc_info); + +/** + * cam_tfe_csid_enable_soc_resources() + * + * @brief: Csid soc resource enable function + * + * @soc_info: Soc info structure pointer + * @clk_lvl: Vote level to start with + * + */ +int cam_tfe_csid_enable_soc_resources(struct cam_hw_soc_info *soc_info, + uint32_t clk_lvl); + +/** + * cam_tfe_csid_disable_soc_resources() + * + * @brief: Csid soc resource disable function + * + * @soc_info: Soc info structure pointer + * + */ +int cam_tfe_csid_disable_soc_resources(struct cam_hw_soc_info *soc_info); + +/** + * cam_tfe_csid_enable_tfe_force_clock() + * + * @brief: If csid testgen used for dual isp case, before + * starting csid test gen, enable tfe force clock on + * through cpas + * + * @soc_info: Soc info structure pointer + * @cpas_tfe_base_offset: Cpas tfe force clock base reg offset value + * + */ +int cam_tfe_csid_enable_tfe_force_clock_on(struct cam_hw_soc_info *soc_info, + uint32_t cpas_tfe_base_offset); + +/** + * cam_tfe_csid_disable_tfe_force_clock_on() + * + * @brief: Disable the TFE force clock on after dual ISP + * CSID test gen stop + * + * @soc_info: Soc info structure pointer + * @cpas_tfe_base_offset: Cpas tfe force clock base reg offset value + * + */ +int cam_tfe_csid_disable_tfe_force_clock_on(struct cam_hw_soc_info *soc_info, + uint32_t cpas_tfe_base_offset); + +/** + * cam_tfe_csid_get_vote_level() + * + * @brief: Get the vote level from clock rate + * + * @soc_info: Soc info structure pointer + * @clock_rate Clock rate + * + */ +uint32_t cam_tfe_csid_get_vote_level(struct cam_hw_soc_info *soc_info, + uint64_t clock_rate); + +#endif /* _CAM_TFE_CSID_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..a6c3a059787a1b7e3bdf7ee2c8f450b9a483f886 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_tfe_soc.o cam_tfe_dev.o cam_tfe_core.o cam_tfe_bus.o cam_tfe.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c new file mode 100644 index 0000000000000000000000000000000000000000..4bafa35e905cd059a522fd21370d50608827f692 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_tfe530.h" +#include "cam_tfe_hw_intf.h" +#include "cam_tfe_core.h" +#include "cam_tfe_dev.h" + +static const struct of_device_id cam_tfe_dt_match[] = { + { + .compatible = "qcom,tfe530", + .data = &cam_tfe530, + }, + {} +}; +MODULE_DEVICE_TABLE(of, cam_tfe_dt_match); + +static struct platform_driver cam_tfe_driver = { + .probe = cam_tfe_probe, + .remove = cam_tfe_remove, + .driver = { + .name = "cam_tfe", + .of_match_table = cam_tfe_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_tfe_init_module(void) +{ + return platform_driver_register(&cam_tfe_driver); +} + +static void __exit cam_tfe_exit_module(void) +{ + platform_driver_unregister(&cam_tfe_driver); +} + +module_init(cam_tfe_init_module); +module_exit(cam_tfe_exit_module); +MODULE_DESCRIPTION("CAM TFE driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h new file mode 100644 index 0000000000000000000000000000000000000000..ff9528b56e704aa39c01f0b0d323fe64a0103735 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h @@ -0,0 +1,891 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + + +#ifndef _CAM_TFE530_H_ +#define _CAM_TFE530_H_ +#include "cam_tfe_core.h" +#include "cam_tfe_bus.h" + + +static struct cam_tfe_top_reg_offset_common tfe530_top_commong_reg = { + .hw_version = 0x00001000, + .hw_capability = 0x00001004, + .lens_feature = 0x00001008, + .stats_feature = 0x0000100C, + .zoom_feature = 0x00001010, + .global_reset_cmd = 0x00001014, + .core_cgc_ctrl = 0x00001018, + .ahb_cgc_ctrl = 0x0000101C, + .core_cfg_0 = 0x00001024, + .core_cfg_1 = 0x00001028, + .reg_update_cmd = 0x0000102C, + .diag_config = 0x00001060, + .diag_sensor_status_0 = 0x00001064, + .diag_sensor_status_1 = 0x00001068, + .diag_sensor_frame_cnt_status = 0x0000106C, + .violation_status = 0x00001070, + .stats_throttle_cnt_cfg_0 = 0x00001074, + .stats_throttle_cnt_cfg_1 = 0x00001078, + .debug_0 = 0x000010A0, + .debug_1 = 0x000010A4, + .debug_2 = 0x000010A8, + .debug_3 = 0x000010AC, + .debug_cfg = 0x000010DC, + .perf_cnt_cfg = 0x000010E0, + .perf_pixel_count = 0x000010E4, + .perf_line_count = 0x000010E8, + .perf_stall_count = 0x000010EC, + .perf_always_count = 0x000010F0, + .perf_count_status = 0x000010F4, +}; + +static struct cam_tfe_camif_reg tfe530_camif_reg = { + .hw_version = 0x00001200, + .hw_status = 0x00001204, + .module_cfg = 0x00001260, + .pdaf_raw_crop_width_cfg = 0x00001268, + .pdaf_raw_crop_height_cfg = 0x0000126C, + .line_skip_pattern = 0x00001270, + .pixel_skip_pattern = 0x00001274, + .period_cfg = 0x00001278, + .irq_subsample_pattern = 0x0000127C, + .epoch_irq_cfg = 0x00001280, + .debug_1 = 0x000013F0, + .debug_0 = 0x000013F4, + .test_bus_ctrl = 0x000013F8, + .spare = 0x000013F8, + .reg_update_cmd = 0x0000102C, +}; + +static struct cam_tfe_camif_reg_data tfe530_camif_reg_data = { + .extern_reg_update_mask = 0x00000001, + .dual_tfe_pix_en_shift = 0x00000001, + .extern_reg_update_shift = 0x0, + .camif_pd_rdi2_src_sel_shift = 0x2, + .dual_tfe_sync_sel_shift = 18, + .delay_line_en_shift = 8, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x7000000, + .module_enable_shift = 0, + .pix_out_enable_shift = 8, + .pdaf_output_enable_shift = 9, + .dsp_mode_shift = 0, + .dsp_mode_mask = 0, + .dsp_en_shift = 0, + .dsp_en_mask = 0, + .reg_update_cmd_data = 0x1, + .epoch_line_cfg = 0x00140014, + .sof_irq_mask = 0x00000001, + .epoch0_irq_mask = 0x00000004, + .epoch1_irq_mask = 0x00000008, + .eof_irq_mask = 0x00000002, + .reg_update_irq_mask = 0x00000001, + .error_irq_mask0 = 0x00010100, + .error_irq_mask2 = 0x00000023, + .subscribe_irq_mask = { + 0x00000000, + 0x00000007, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .perf_cnt_start_cmd_shift = 0, + .perf_cnt_continuous_shift = 2, + .perf_client_sel_shift = 8, + .perf_window_start_shift = 16, + .perf_window_end_shift = 20, +}; + +static struct cam_tfe_rdi_reg tfe530_rdi0_reg = { + .rdi_hw_version = 0x00001400, + .rdi_hw_status = 0x00001404, + .rdi_module_config = 0x00001460, + .rdi_skip_period = 0x00001468, + .rdi_irq_subsample_pattern = 0x0000146C, + .rdi_epoch_irq = 0x00001470, + .rdi_debug_1 = 0x000015F0, + .rdi_debug_0 = 0x000015F4, + .rdi_test_bus_ctrl = 0x000015F8, + .rdi_spare = 0x000015FC, + .reg_update_cmd = 0x0000102C, +}; + +static struct cam_tfe_rdi_reg_data tfe530_rdi0_reg_data = { + .reg_update_cmd_data = 0x2, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00000010, + .epoch0_irq_mask = 0x00000040, + .epoch1_irq_mask = 0x00000080, + .eof_irq_mask = 0x00000020, + .error_irq_mask0 = 0x00020200, + .error_irq_mask2 = 0x00000004, + .subscribe_irq_mask = { + 0x00000000, + 0x00000030, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, +}; + +static struct cam_tfe_rdi_reg tfe530_rdi1_reg = { + .rdi_hw_version = 0x00001600, + .rdi_hw_status = 0x00001604, + .rdi_module_config = 0x00001660, + .rdi_skip_period = 0x00001668, + .rdi_irq_subsample_pattern = 0x0000166C, + .rdi_epoch_irq = 0x00001670, + .rdi_debug_1 = 0x000017F0, + .rdi_debug_0 = 0x000017F4, + .rdi_test_bus_ctrl = 0x000017F8, + .rdi_spare = 0x000017FC, + .reg_update_cmd = 0x0000102C, +}; + +static struct cam_tfe_rdi_reg_data tfe530_rdi1_reg_data = { + .reg_update_cmd_data = 0x4, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00000100, + .epoch0_irq_mask = 0x00000400, + .epoch1_irq_mask = 0x00000800, + .eof_irq_mask = 0x00000200, + .error_irq_mask0 = 0x00040400, + .error_irq_mask2 = 0x00000008, + .subscribe_irq_mask = { + 0x00000000, + 0x00000300, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, +}; + +static struct cam_tfe_rdi_reg tfe530_rdi2_reg = { + .rdi_hw_version = 0x00001800, + .rdi_hw_status = 0x00001804, + .rdi_module_config = 0x00001860, + .rdi_skip_period = 0x00001868, + .rdi_irq_subsample_pattern = 0x0000186C, + .rdi_epoch_irq = 0x00001870, + .rdi_debug_1 = 0x000019F0, + .rdi_debug_0 = 0x000019F4, + .rdi_test_bus_ctrl = 0x000019F8, + .rdi_spare = 0x000019FC, + .reg_update_cmd = 0x0000102C, +}; + +static struct cam_tfe_rdi_reg_data tfe530_rdi2_reg_data = { + .reg_update_cmd_data = 0x8, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00001000, + .epoch0_irq_mask = 0x00004000, + .epoch1_irq_mask = 0x00008000, + .eof_irq_mask = 0x00002000, + .error_irq_mask0 = 0x00080800, + .error_irq_mask2 = 0x00000004, + .subscribe_irq_mask = { + 0x00000000, + 0x00003000, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, +}; + +static struct cam_tfe_clc_hw_status tfe530_clc_hw_info[CAM_TFE_MAX_CLC] = { + { + .name = "CLC_CAMIF", + .hw_status_reg = 0x1204, + }, + { + .name = "CLC_RDI0_CAMIF", + .hw_status_reg = 0x1404, + }, + { + .name = "CLC_RDI1_CAMIF", + .hw_status_reg = 0x1604, + }, + { + .name = "CLC_RDI2_CAMIF", + .hw_status_reg = 0x1804, + }, + { + .name = "CLC_CHANNEL_GAIN", + .hw_status_reg = 0x2604, + }, + { + .name = "CLC_LENS_ROLL_OFF", + .hw_status_reg = 0x2804, + }, + { + .name = "CLC_WB_BDS", + .hw_status_reg = 0x2A04, + }, + { + .name = "CLC_STATS_BHIST", + .hw_status_reg = 0x2C04, + }, + { + .name = "CLC_STATS_TINTLESS_BG", + .hw_status_reg = 0x2E04, + }, + { + .name = "CLC_STATS_BAF", + .hw_status_reg = 0x3004, + }, + { + .name = "CLC_STATS_AWB_BG", + .hw_status_reg = 0x3204, + }, + { + .name = "CLC_STATS_AEC_BG", + .hw_status_reg = 0x3404, + }, + { + .name = "CLC_STATS_RAW_OUT", + .hw_status_reg = 0x3604, + }, + { + .name = "CLC_STATS_CROP_POST_BDS", + .hw_status_reg = 0x3804, + }, +}; + +static struct cam_tfe_top_hw_info tfe530_top_hw_info = { + .common_reg = &tfe530_top_commong_reg, + .camif_hw_info = { + .camif_reg = &tfe530_camif_reg, + .reg_data = &tfe530_camif_reg_data, + }, + .rdi_hw_info = { + { + .rdi_reg = &tfe530_rdi0_reg, + .reg_data = &tfe530_rdi0_reg_data, + }, + { + .rdi_reg = &tfe530_rdi1_reg, + .reg_data = &tfe530_rdi1_reg_data, + }, + { + .rdi_reg = &tfe530_rdi2_reg, + .reg_data = &tfe530_rdi2_reg_data, + }, + }, + .in_port = { + CAM_TFE_CAMIF_VER_1_0, + CAM_TFE_RDI_VER_1_0, + CAM_TFE_RDI_VER_1_0, + CAM_TFE_RDI_VER_1_0 + }, + .reg_dump_data = { + .num_reg_dump_entries = 19, + .num_lut_dump_entries = 0, + .bus_start_addr = 0x2000, + .bus_write_top_end_addr = 0x2120, + .bus_client_start_addr = 0x2200, + .bus_client_offset = 0x100, + .num_bus_clients = 10, + .reg_entry = { + { + .start_offset = 0x1000, + .end_offset = 0x10F4, + }, + { + .start_offset = 0x1260, + .end_offset = 0x1280, + }, + { + .start_offset = 0x13F0, + .end_offset = 0x13FC, + }, + { + .start_offset = 0x1460, + .end_offset = 0x1470, + }, + { + .start_offset = 0x15F0, + .end_offset = 0x15FC, + }, + { + .start_offset = 0x1660, + .end_offset = 0x1670, + }, + { + .start_offset = 0x17F0, + .end_offset = 0x17FC, + }, + { + .start_offset = 0x1860, + .end_offset = 0x1870, + }, + { + .start_offset = 0x19F0, + .end_offset = 0x19FC, + }, + { + .start_offset = 0x2660, + .end_offset = 0x2694, + }, + { + .start_offset = 0x2860, + .end_offset = 0x2884, + }, + { + .start_offset = 0x2A60, + .end_offset = 0X2B34, + }, + { + .start_offset = 0x2C60, + .end_offset = 0X2C80, + }, + { + .start_offset = 0x2E60, + .end_offset = 0X2E7C, + }, + { + .start_offset = 0x3060, + .end_offset = 0X3110, + }, + { + .start_offset = 0x3260, + .end_offset = 0X3278, + }, + { + .start_offset = 0x3460, + .end_offset = 0X3478, + }, + { + .start_offset = 0x3660, + .end_offset = 0X3684, + }, + { + .start_offset = 0x3860, + .end_offset = 0X3884, + }, + }, + .lut_entry = { + { + .lut_word_size = 1, + .lut_bank_sel = 0x40, + .lut_addr_size = 180, + .dmi_reg_offset = 0x2800, + }, + { + .lut_word_size = 1, + .lut_bank_sel = 0x41, + .lut_addr_size = 180, + .dmi_reg_offset = 0x3000, + }, + }, + }, +}; + +static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { + .common_reg = { + .hw_version = 0x00001A00, + .cgc_ovd = 0x00001A08, + .comp_cfg_0 = 0x00001A0C, + .comp_cfg_1 = 0x00001A10, + .frameheader_cfg = { + 0x00001A34, + 0x00001A38, + 0x00001A3C, + 0x00001A40, + }, + .pwr_iso_cfg = 0x00001A5C, + .overflow_status_clear = 0x00001A60, + .ccif_violation_status = 0x00001A64, + .overflow_status = 0x00001A68, + .image_size_violation_status = 0x00001A70, + .perf_count_cfg = { + 0x00001A74, + 0x00001A78, + 0x00001A7C, + 0x00001A80, + 0x00001A84, + 0x00001A88, + 0x00001A8C, + 0x00001A90, + }, + .perf_count_val = { + 0x00001A94, + 0x00001A98, + 0x00001A9C, + 0x00001AA0, + 0x00001AA4, + 0x00001AA8, + 0x00001AAC, + 0x00001AB0, + }, + .perf_count_status = 0x00001AB4, + .debug_status_top_cfg = 0x00001AD4, + .debug_status_top = 0x00001AD8, + .test_bus_ctrl = 0x00001ADC, + .irq_mask = { + 0x00001A18, + 0x00001A1C, + }, + .irq_clear = { + 0x00001A20, + 0x00001A24, + }, + .irq_status = { + 0x00001A28, + 0x00001A2C, + }, + .irq_cmd = 0x00001A30, + .cons_violation_shift = 28, + .violation_shift = 30, + .image_size_violation = 31, + }, + .num_client = CAM_TFE_BUS_MAX_CLIENTS, + .bus_client_reg = { + /* BUS Client 0 BAYER */ + { + .cfg = 0x00001C00, + .image_addr = 0x00001C04, + .frame_incr = 0x00001C08, + .image_cfg_0 = 0x00001C0C, + .image_cfg_1 = 0x00001C10, + .image_cfg_2 = 0x00001C14, + .packer_cfg = 0x00001C18, + .bw_limit = 0x00001C1C, + .frame_header_addr = 0x00001C20, + .frame_header_incr = 0x00001C24, + .frame_header_cfg = 0x00001C28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00001C30, + .irq_subsample_pattern = 0x00001C34, + .framedrop_period = 0x00001C38, + .framedrop_pattern = 0x00001C3C, + .addr_status_0 = 0x00001C68, + .addr_status_1 = 0x00001C6C, + .addr_status_2 = 0x00001C70, + .addr_status_3 = 0x00001C74, + .debug_status_cfg = 0x00001C78, + .debug_status_0 = 0x00001C7C, + .debug_status_1 = 0x00001C80, + .comp_group = CAM_TFE_BUS_COMP_GRP_0, + .client_name = "BAYER", + }, + /* BUS Client 1 IDEAL RAW*/ + { + .cfg = 0x00001D00, + .image_addr = 0x00001D04, + .frame_incr = 0x00001D08, + .image_cfg_0 = 0x00001D0C, + .image_cfg_1 = 0x00001D10, + .image_cfg_2 = 0x00001D14, + .packer_cfg = 0x00001D18, + .bw_limit = 0x00001D1C, + .frame_header_addr = 0x00001D20, + .frame_header_incr = 0x00001D24, + .frame_header_cfg = 0x00001D28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00001D30, + .irq_subsample_pattern = 0x00001D34, + .framedrop_period = 0x00001D38, + .framedrop_pattern = 0x00001D3C, + .addr_status_0 = 0x00001D68, + .addr_status_1 = 0x00001D6C, + .addr_status_2 = 0x00001D70, + .addr_status_3 = 0x00001D74, + .debug_status_cfg = 0x00001D78, + .debug_status_0 = 0x00001D7C, + .debug_status_1 = 0x00001D80, + .comp_group = CAM_TFE_BUS_COMP_GRP_1, + .client_name = "IDEAL_RAW", + }, + /* BUS Client 2 Stats BE Tintless */ + { + .cfg = 0x00001E00, + .image_addr = 0x00001E04, + .frame_incr = 0x00001E08, + .image_cfg_0 = 0x00001E0C, + .image_cfg_1 = 0x00001E10, + .image_cfg_2 = 0x00001E14, + .packer_cfg = 0x00001E18, + .bw_limit = 0x00001E1C, + .frame_header_addr = 0x00001E20, + .frame_header_incr = 0x00001E24, + .frame_header_cfg = 0x00001E28, + .line_done_cfg = 0x00001E00, + .irq_subsample_period = 0x00001E30, + .irq_subsample_pattern = 0x00000E34, + .framedrop_period = 0x00001E38, + .framedrop_pattern = 0x00001E3C, + .addr_status_0 = 0x00001E68, + .addr_status_1 = 0x00001E6C, + .addr_status_2 = 0x00001E70, + .addr_status_3 = 0x00001E74, + .debug_status_cfg = 0x00001E78, + .debug_status_0 = 0x00001E7C, + .debug_status_1 = 0x00001E80, + .comp_group = CAM_TFE_BUS_COMP_GRP_2, + .client_name = "STATS BE TINTLESS", + }, + /* BUS Client 3 Stats Bhist */ + { + .cfg = 0x00001F00, + .image_addr = 0x00001F04, + .frame_incr = 0x00001F08, + .image_cfg_0 = 0x00001F0C, + .image_cfg_1 = 0x00001F10, + .image_cfg_2 = 0x00001F14, + .packer_cfg = 0x00001F18, + .bw_limit = 0x00001F1C, + .frame_header_addr = 0x00001F20, + .frame_header_incr = 0x00001F24, + .frame_header_cfg = 0x00001F28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00001F30, + .irq_subsample_pattern = 0x00001F34, + .framedrop_period = 0x00001F38, + .framedrop_pattern = 0x00001F3C, + .addr_status_0 = 0x00001F68, + .addr_status_1 = 0x00001F6C, + .addr_status_2 = 0x00001F70, + .addr_status_3 = 0x00001F74, + .debug_status_cfg = 0x00001F78, + .debug_status_0 = 0x00001F7C, + .debug_status_1 = 0x00001F80, + .comp_group = CAM_TFE_BUS_COMP_GRP_2, + .client_name = "STATS BHIST", + }, + /* BUS Client 4 Stats AWB BG */ + { + .cfg = 0x00002000, + .image_addr = 0x00002004, + .frame_incr = 0x00002008, + .image_cfg_0 = 0x0000200C, + .image_cfg_1 = 0x00002010, + .image_cfg_2 = 0x00002014, + .packer_cfg = 0x00002018, + .bw_limit = 0x0000201C, + .frame_header_addr = 0x00002020, + .frame_header_incr = 0x00002024, + .frame_header_cfg = 0x00002028, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00002030, + .irq_subsample_pattern = 0x00002034, + .framedrop_period = 0x00002038, + .framedrop_pattern = 0x0000203C, + .addr_status_0 = 0x00002068, + .addr_status_1 = 0x0000206C, + .addr_status_2 = 0x00002070, + .addr_status_3 = 0x00002074, + .debug_status_cfg = 0x00002078, + .debug_status_0 = 0x0000207C, + .debug_status_1 = 0x00002080, + .comp_group = CAM_TFE_BUS_COMP_GRP_3, + .client_name = "STATS AWB BG", + }, + /* BUS Client 5 Stats AEC BG */ + { + .cfg = 0x00002100, + .image_addr = 0x00002104, + .frame_incr = 0x00002108, + .image_cfg_0 = 0x0000210C, + .image_cfg_1 = 0x00002110, + .image_cfg_2 = 0x00002114, + .packer_cfg = 0x00002118, + .bw_limit = 0x0000211C, + .frame_header_addr = 0x00002120, + .frame_header_incr = 0x00002124, + .frame_header_cfg = 0x00002128, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00002130, + .irq_subsample_pattern = 0x00002134, + .framedrop_period = 0x00002138, + .framedrop_pattern = 0x0000213C, + .addr_status_0 = 0x00002168, + .addr_status_1 = 0x0000216C, + .addr_status_2 = 0x00002170, + .addr_status_3 = 0x00002174, + .debug_status_cfg = 0x00002178, + .debug_status_0 = 0x0000217C, + .debug_status_1 = 0x00002180, + .comp_group = CAM_TFE_BUS_COMP_GRP_3, + .client_name = "STATS AEC BG", + }, + /* BUS Client 6 Stats BAF */ + { + .cfg = 0x00002200, + .image_addr = 0x00002204, + .frame_incr = 0x00002208, + .image_cfg_0 = 0x0000220C, + .image_cfg_1 = 0x00002210, + .image_cfg_2 = 0x00002214, + .packer_cfg = 0x00002218, + .bw_limit = 0x0000221C, + .frame_header_addr = 0x00002220, + .frame_header_incr = 0x00002224, + .frame_header_cfg = 0x00002228, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00002230, + .irq_subsample_pattern = 0x00002234, + .framedrop_period = 0x00002238, + .framedrop_pattern = 0x0000223C, + .addr_status_0 = 0x00002268, + .addr_status_1 = 0x0000226C, + .addr_status_2 = 0x00002270, + .addr_status_3 = 0x00002274, + .debug_status_cfg = 0x00002278, + .debug_status_0 = 0x0000227C, + .debug_status_1 = 0x00002280, + .comp_group = CAM_TFE_BUS_COMP_GRP_4, + .client_name = "STATS BAF", + }, + /* BUS Client 7 RDI0 */ + { + .cfg = 0x00002300, + .image_addr = 0x00002304, + .frame_incr = 0x00002308, + .image_cfg_0 = 0x0000230C, + .image_cfg_1 = 0x00002310, + .image_cfg_2 = 0x00002314, + .packer_cfg = 0x00002318, + .bw_limit = 0x0000231C, + .frame_header_addr = 0x00002320, + .frame_header_incr = 0x00002324, + .frame_header_cfg = 0x00002328, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00002330, + .irq_subsample_pattern = 0x00002334, + .framedrop_period = 0x00002338, + .framedrop_pattern = 0x0000233C, + .addr_status_0 = 0x00002368, + .addr_status_1 = 0x0000236C, + .addr_status_2 = 0x00002370, + .addr_status_3 = 0x00002374, + .debug_status_cfg = 0x00002378, + .debug_status_0 = 0x0000237C, + .debug_status_1 = 0x00002380, + .comp_group = CAM_TFE_BUS_COMP_GRP_5, + .client_name = "RDI0", + }, + /* BUS Client 8 RDI1 */ + { + .cfg = 0x00002400, + .image_addr = 0x00002404, + .frame_incr = 0x00002408, + .image_cfg_0 = 0x0000240C, + .image_cfg_1 = 0x00002410, + .image_cfg_2 = 0x00002414, + .packer_cfg = 0x00002418, + .bw_limit = 0x0000241C, + .frame_header_addr = 0x00002420, + .frame_header_incr = 0x00002424, + .frame_header_cfg = 0x00002428, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00002430, + .irq_subsample_pattern = 0x00002434, + .framedrop_period = 0x00002438, + .framedrop_pattern = 0x0000243C, + .addr_status_0 = 0x00002468, + .addr_status_1 = 0x0000246C, + .addr_status_2 = 0x00002470, + .addr_status_3 = 0x00002474, + .debug_status_cfg = 0x00002478, + .debug_status_0 = 0x0000247C, + .debug_status_1 = 0x00002480, + .comp_group = CAM_TFE_BUS_COMP_GRP_6, + .client_name = "RDI1", + }, + /* BUS Client 9 PDAF/RDI2*/ + { + .cfg = 0x00002500, + .image_addr = 0x00002504, + .frame_incr = 0x00002508, + .image_cfg_0 = 0x0000250C, + .image_cfg_1 = 0x00002510, + .image_cfg_2 = 0x00002514, + .packer_cfg = 0x00002518, + .bw_limit = 0x0000251C, + .frame_header_addr = 0x00002520, + .frame_header_incr = 0x00002524, + .frame_header_cfg = 0x00002528, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00002530, + .irq_subsample_pattern = 0x00002534, + .framedrop_period = 0x00002538, + .framedrop_pattern = 0x0000253C, + .addr_status_0 = 0x00002568, + .addr_status_1 = 0x0000256C, + .addr_status_2 = 0x00002570, + .addr_status_3 = 0x00002574, + .debug_status_cfg = 0x00002578, + .debug_status_0 = 0x0000257C, + .debug_status_1 = 0x00002580, + .comp_group = CAM_TFE_BUS_COMP_GRP_7, + .client_name = "RDI2/PADF", + }, + }, + .num_out = CAM_TFE_BUS_TFE_OUT_MAX, + .tfe_out_hw_info = { + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI0, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_5, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_1, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI1, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_6, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_2, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI2, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_7, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_3, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_FULL, + .max_width = 4096, + .max_height = 4096, + .composite_group = CAM_TFE_BUS_COMP_GRP_0, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RAW_DUMP, + .max_width = 4096, + .max_height = 4096, + .composite_group = CAM_TFE_BUS_COMP_GRP_1, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_PDAF, + .max_width = 4096, + .max_height = 4096, + .composite_group = CAM_TFE_BUS_COMP_GRP_7, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_3, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_3, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_2, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_TL_BG, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_2, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_3, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_BF, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_4, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + }, + .comp_done_shift = 8, + .top_bus_wr_irq_shift = 1, + .comp_buf_done_mask = 0xFF00, + .comp_rup_done_mask = 0xF, + .bus_irq_error_mask = { + 0xD0000000, + 0x00000000, + }, +}; + +struct cam_tfe_hw_info cam_tfe530 = { + .top_irq_mask = { + 0x00001034, + 0x00001038, + 0x0000103C, + }, + .top_irq_clear = { + 0x00001040, + 0x00001044, + 0x00001048, + }, + .top_irq_status = { + 0x0000104C, + 0x00001050, + 0x00001054, + }, + .top_irq_cmd = 0x00001030, + .global_clear_bitmask = 0x00000001, + + .bus_irq_mask = { + 0x00001A18, + 0x00001A1C, + }, + .bus_irq_clear = { + 0x00001A20, + 0x00001A24, + }, + .bus_irq_status = { + 0x00001A28, + 0x00001A2C, + }, + .bus_irq_cmd = 0x00001A30, + .bus_violation_reg = 0x00001A64, + .bus_overflow_reg = 0x00001A68, + .bus_image_size_vilation_reg = 0x1A70, + .bus_overflow_clear_cmd = 0x1A60, + .debug_status_top = 0x1AD8, + + .reset_irq_mask = { + 0x00000001, + 0x00000000, + 0x00000000, + }, + .error_irq_mask = { + 0x000F0F00, + 0x00000000, + 0x0000003F, + }, + .bus_reg_irq_mask = { + 0x00000002, + 0x00000000, + }, + .bus_error_irq_mask = { + 0xC0000000, + 0x00000000, + }, + + .num_clc = 14, + .clc_hw_status_info = tfe530_clc_hw_info, + .bus_version = CAM_TFE_BUS_1_0, + .bus_hw_info = &tfe530_bus_hw_info, + + .top_version = CAM_TFE_TOP_1_0, + .top_hw_info = &tfe530_top_hw_info, +}; + +#endif /* _CAM_TFE530_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c new file mode 100644 index 0000000000000000000000000000000000000000..91ce4e542e3b1d9c23a91ecd07c78e2729b0e2f5 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c @@ -0,0 +1,2365 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include "cam_io_util.h" +#include "cam_debug_util.h" +#include "cam_cdm_util.h" +#include "cam_hw_intf.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_tfe_hw_intf.h" +#include "cam_irq_controller.h" +#include "cam_tasklet_util.h" +#include "cam_tfe_bus.h" +#include "cam_tfe_irq.h" +#include "cam_tfe_soc.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" + + +static const char drv_name[] = "tfe_bus"; + +#define CAM_TFE_BUS_IRQ_REG0 0 +#define CAM_TFE_BUS_IRQ_REG1 1 + +#define CAM_TFE_BUS_PAYLOAD_MAX 256 + +#define CAM_TFE_RDI_BUS_DEFAULT_WIDTH 0xFFFF +#define CAM_TFE_RDI_BUS_DEFAULT_STRIDE 0xFFFF + +#define CAM_TFE_MAX_OUT_RES_PER_COMP_GRP 2 + +#define MAX_BUF_UPDATE_REG_NUM \ + (sizeof(struct cam_tfe_bus_reg_offset_bus_client) / 4) +#define MAX_REG_VAL_PAIR_SIZE \ + (MAX_BUF_UPDATE_REG_NUM * 2 * CAM_PACKET_MAX_PLANES) + +enum cam_tfe_bus_packer_format { + PACKER_FMT_PLAIN_128, + PACKER_FMT_PLAIN_8, + PACKER_FMT_PLAIN_8_ODD_EVEN, + PACKER_FMT_PLAIN_8_LSB_MSB_10, + PACKER_FMT_PLAIN_8_LSB_MSB_10_ODD_EVEN, + PACKER_FMT_PLAIN_16_10BPP, + PACKER_FMT_PLAIN_16_12BPP, + PACKER_FMT_PLAIN_16_14BPP, + PACKER_FMT_PLAIN_16_16BPP, + PACKER_FMT_PLAIN_32, + PACKER_FMT_PLAIN_64, + PACKER_FMT_TP_10, + PACKET_FMT_MIPI10, + PACKET_FMT_MIPI12, + PACKER_FMT_MAX, +}; + +struct cam_tfe_bus_common_data { + uint32_t core_index; + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + void *tfe_core_data; + struct cam_tfe_bus_reg_offset_common *common_reg; + uint32_t io_buf_update[MAX_REG_VAL_PAIR_SIZE]; + + spinlock_t spin_lock; + struct mutex bus_mutex; + uint32_t secure_mode; + uint32_t num_sec_out; + uint32_t comp_done_shift; + bool is_lite; + cam_hw_mgr_event_cb_func event_cb; + bool rup_irq_enable[CAM_TFE_BUS_RUP_GRP_MAX]; +}; + +struct cam_tfe_bus_wm_resource_data { + uint32_t index; + uint32_t out_id; + struct cam_tfe_bus_common_data *common_data; + struct cam_tfe_bus_reg_offset_bus_client *hw_regs; + + uint32_t offset; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t format; + uint32_t pack_fmt; + uint32_t burst_len; + uint32_t mode; + + uint32_t irq_subsample_period; + uint32_t irq_subsample_pattern; + uint32_t framedrop_period; + uint32_t framedrop_pattern; + + uint32_t en_cfg; + uint32_t is_dual; + + uint32_t acquired_width; + uint32_t acquired_height; + uint32_t acquired_stride; +}; + +struct cam_tfe_bus_comp_grp_data { + enum cam_tfe_bus_comp_grp_id comp_grp_id; + struct cam_tfe_bus_common_data *common_data; + + uint32_t is_master; + uint32_t is_dual; + uint32_t addr_sync_mode; + uint32_t composite_mask; + + uint32_t acquire_dev_cnt; + uint32_t source_grp; + + struct cam_isp_resource_node + *out_rsrc[CAM_TFE_MAX_OUT_RES_PER_COMP_GRP]; +}; + +struct cam_tfe_bus_tfe_out_data { + uint32_t out_id; + uint32_t composite_group; + uint32_t rup_group_id; + uint32_t source_group; + struct cam_tfe_bus_common_data *common_data; + + uint32_t num_wm; + struct cam_isp_resource_node *wm_res[PLANE_MAX]; + + struct cam_isp_resource_node *comp_grp; + struct list_head tfe_out_list; + + uint32_t is_master; + uint32_t is_dual; + + uint32_t format; + uint32_t max_width; + uint32_t max_height; + struct cam_cdm_utils_ops *cdm_util_ops; + uint32_t secure_mode; + void *priv; + cam_hw_mgr_event_cb_func event_cb; +}; + +struct cam_tfe_bus_priv { + struct cam_tfe_bus_common_data common_data; + uint32_t num_client; + uint32_t num_out; + uint32_t top_bus_wr_irq_shift; + + struct cam_isp_resource_node bus_client[CAM_TFE_BUS_MAX_CLIENTS]; + struct cam_isp_resource_node comp_grp[CAM_TFE_BUS_COMP_GRP_MAX]; + struct cam_isp_resource_node tfe_out[CAM_TFE_BUS_TFE_OUT_MAX]; + + struct list_head free_comp_grp; + struct list_head used_comp_grp; + + void *tasklet_info; + uint32_t comp_buf_done_mask; + uint32_t comp_rup_done_mask; + uint32_t bus_irq_error_mask[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; +}; + +static bool cam_tfe_bus_can_be_secure(uint32_t out_id) +{ + switch (out_id) { + case CAM_TFE_BUS_TFE_OUT_FULL: + case CAM_TFE_BUS_TFE_OUT_RAW_DUMP: + case CAM_TFE_BUS_TFE_OUT_RDI0: + case CAM_TFE_BUS_TFE_OUT_RDI1: + case CAM_TFE_BUS_TFE_OUT_RDI2: + return true; + + case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE: + case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST: + case CAM_TFE_BUS_TFE_OUT_STATS_TL_BG: + case CAM_TFE_BUS_TFE_OUT_STATS_BF: + case CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG: + default: + return false; + } +} + +static enum cam_tfe_bus_tfe_out_id + cam_tfe_bus_get_out_res_id(uint32_t out_res_id) +{ + switch (out_res_id) { + case CAM_ISP_TFE_OUT_RES_FULL: + return CAM_TFE_BUS_TFE_OUT_FULL; + case CAM_ISP_TFE_OUT_RES_RAW_DUMP: + return CAM_TFE_BUS_TFE_OUT_RAW_DUMP; + case CAM_ISP_TFE_OUT_RES_PDAF: + return CAM_TFE_BUS_TFE_OUT_PDAF; + case CAM_ISP_TFE_OUT_RES_RDI_0: + return CAM_TFE_BUS_TFE_OUT_RDI0; + case CAM_ISP_TFE_OUT_RES_RDI_1: + return CAM_TFE_BUS_TFE_OUT_RDI1; + case CAM_ISP_TFE_OUT_RES_RDI_2: + return CAM_TFE_BUS_TFE_OUT_RDI2; + case CAM_ISP_TFE_OUT_RES_STATS_HDR_BE: + return CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE; + case CAM_ISP_TFE_OUT_RES_STATS_HDR_BHIST: + return CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST; + case CAM_ISP_TFE_OUT_RES_STATS_TL_BG: + return CAM_TFE_BUS_TFE_OUT_STATS_TL_BG; + case CAM_ISP_TFE_OUT_RES_STATS_BF: + return CAM_TFE_BUS_TFE_OUT_STATS_BF; + case CAM_ISP_TFE_OUT_RES_STATS_AWB_BG: + return CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG; + default: + return CAM_TFE_BUS_TFE_OUT_MAX; + } +} + +static int cam_tfe_bus_get_num_wm( + enum cam_tfe_bus_tfe_out_id out_res_id, + uint32_t format) +{ + switch (out_res_id) { + case CAM_TFE_BUS_TFE_OUT_RDI0: + case CAM_TFE_BUS_TFE_OUT_RDI1: + case CAM_TFE_BUS_TFE_OUT_RDI2: + switch (format) { + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_PLAIN16_16: + case CAM_FORMAT_PLAIN128: + return 1; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_PDAF: + switch (format) { + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + return 1; + default: + break; + } + break; + + case CAM_TFE_BUS_TFE_OUT_FULL: + switch (format) { + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + return 1; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_RAW_DUMP: + switch (format) { + case CAM_FORMAT_ARGB_14: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + return 1; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE: + case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST: + case CAM_TFE_BUS_TFE_OUT_STATS_TL_BG: + case CAM_TFE_BUS_TFE_OUT_STATS_BF: + case CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG: + switch (format) { + case CAM_FORMAT_PLAIN64: + return 1; + default: + break; + } + break; + default: + break; + } + + CAM_ERR(CAM_ISP, "Unsupported format %u for resource id %u", + format, out_res_id); + + return -EINVAL; +} + +static int cam_tfe_bus_get_wm_idx( + enum cam_tfe_bus_tfe_out_id tfe_out_res_id, + enum cam_tfe_bus_plane_type plane) +{ + int wm_idx = -1; + + switch (tfe_out_res_id) { + case CAM_TFE_BUS_TFE_OUT_RDI0: + switch (plane) { + case PLANE_Y: + wm_idx = 7; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_RDI1: + switch (plane) { + case PLANE_Y: + wm_idx = 8; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_RDI2: + switch (plane) { + case PLANE_Y: + wm_idx = 9; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_PDAF: + switch (plane) { + case PLANE_Y: + wm_idx = 9; + break; + default: + break; + } + break; + + case CAM_TFE_BUS_TFE_OUT_FULL: + switch (plane) { + case PLANE_Y: + wm_idx = 0; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_RAW_DUMP: + switch (plane) { + case PLANE_Y: + wm_idx = 1; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE: + switch (plane) { + case PLANE_Y: + wm_idx = 5; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST: + switch (plane) { + case PLANE_Y: + wm_idx = 3; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG: + switch (plane) { + case PLANE_Y: + wm_idx = 4; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_STATS_TL_BG: + switch (plane) { + case PLANE_Y: + wm_idx = 2; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_STATS_BF: + switch (plane) { + case PLANE_Y: + wm_idx = 6; + break; + default: + break; + } + break; + + default: + break; + } + + return wm_idx; +} + +static enum cam_tfe_bus_packer_format + cam_tfe_bus_get_packer_fmt(uint32_t out_fmt, int wm_index) +{ + switch (out_fmt) { + case CAM_FORMAT_MIPI_RAW_6: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_MIPI_RAW_20: + case CAM_FORMAT_PLAIN16_8: + case CAM_FORMAT_PLAIN128: + case CAM_FORMAT_PD8: + return PACKER_FMT_PLAIN_128; + case CAM_FORMAT_PLAIN8: + return PACKER_FMT_PLAIN_8; + case CAM_FORMAT_Y_ONLY: + return PACKER_FMT_PLAIN_8_LSB_MSB_10; + case CAM_FORMAT_PLAIN16_10: + return PACKER_FMT_PLAIN_16_10BPP; + case CAM_FORMAT_PLAIN16_12: + return PACKER_FMT_PLAIN_16_12BPP; + case CAM_FORMAT_PLAIN16_14: + return PACKER_FMT_PLAIN_16_14BPP; + case CAM_FORMAT_PLAIN16_16: + return PACKER_FMT_PLAIN_16_16BPP; + case CAM_FORMAT_ARGB: + return PACKER_FMT_PLAIN_32; + case CAM_FORMAT_PLAIN64: + case CAM_FORMAT_PD10: + return PACKER_FMT_PLAIN_64; + case CAM_FORMAT_TP10: + return PACKER_FMT_TP_10; + default: + return PACKER_FMT_MAX; + } +} + +static int cam_tfe_bus_acquire_rdi_wm( + struct cam_tfe_bus_wm_resource_data *rsrc_data) +{ + switch (rsrc_data->format) { + case CAM_FORMAT_MIPI_RAW_6: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 6, 64) / 64; + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_PLAIN8: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 8, 64) / 64; + + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + case CAM_FORMAT_MIPI_RAW_10: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 10, 64) / 64; + + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + case CAM_FORMAT_MIPI_RAW_12: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 12, 64) / 64; + + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + case CAM_FORMAT_MIPI_RAW_14: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 14, 64) / 64; + + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_PLAIN16_16: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 16, 64) / 64; + + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + + case CAM_FORMAT_PLAIN128: + case CAM_FORMAT_PLAIN64: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 64, 64) / 64; + + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + default: + CAM_ERR(CAM_ISP, "Unsupported RDI:%d format %d", + rsrc_data->index, rsrc_data->format); + return -EINVAL; + } + + return 0; +} + +static int cam_tfe_bus_acquire_wm( + struct cam_tfe_bus_priv *bus_priv, + struct cam_isp_tfe_out_port_info *out_port_info, + struct cam_isp_resource_node **wm_res, + void *tasklet, + enum cam_tfe_bus_tfe_out_id tfe_out_res_id, + enum cam_tfe_bus_plane_type plane, + uint32_t *client_done_mask, + uint32_t is_dual, + enum cam_tfe_bus_comp_grp_id *comp_grp_id) +{ + struct cam_isp_resource_node *wm_res_local = NULL; + struct cam_tfe_bus_wm_resource_data *rsrc_data = NULL; + uint32_t wm_idx = 0; + int rc = 0; + + *wm_res = NULL; + /* No need to allocate for BUS TFE OUT to WM is fixed. */ + wm_idx = cam_tfe_bus_get_wm_idx(tfe_out_res_id, plane); + if (wm_idx < 0 || wm_idx >= bus_priv->num_client) { + CAM_ERR(CAM_ISP, "Unsupported TFE out %d plane %d", + tfe_out_res_id, plane); + return -EINVAL; + } + + wm_res_local = &bus_priv->bus_client[wm_idx]; + if (wm_res_local->res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, "WM:%d not available state:%d", + wm_idx, wm_res_local->res_state); + return -EALREADY; + } + wm_res_local->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + wm_res_local->tasklet_info = tasklet; + + rsrc_data = wm_res_local->res_priv; + rsrc_data->format = out_port_info->format; + rsrc_data->pack_fmt = cam_tfe_bus_get_packer_fmt(rsrc_data->format, + wm_idx); + + rsrc_data->width = out_port_info->width; + rsrc_data->height = out_port_info->height; + rsrc_data->stride = out_port_info->stride; + rsrc_data->mode = out_port_info->wm_mode; + rsrc_data->out_id = tfe_out_res_id; + + /* + * Store the acquire width, height separately. For frame based ports + * width and height modified again + */ + rsrc_data->acquired_width = out_port_info->width; + rsrc_data->acquired_height = out_port_info->height; + rsrc_data->acquired_stride = out_port_info->stride; + + rsrc_data->is_dual = is_dual; + /* Set WM offset value to default */ + rsrc_data->offset = 0; + + if ((rsrc_data->index > 6) && + (tfe_out_res_id != CAM_TFE_BUS_TFE_OUT_PDAF)) { + /* WM 7-9 refers to RDI 0/ RDI 1/RDI 2 */ + rc = cam_tfe_bus_acquire_rdi_wm(rsrc_data); + if (rc) + return rc; + + } else if (rsrc_data->index == 0 || rsrc_data->index == 1 || + (tfe_out_res_id == CAM_TFE_BUS_TFE_OUT_PDAF)) { + /* WM 0 FULL_OUT WM 1 IDEAL RAW WM9 for pdaf */ + switch (rsrc_data->format) { + case CAM_FORMAT_MIPI_RAW_8: + rsrc_data->pack_fmt = 0x1; + break; + case CAM_FORMAT_MIPI_RAW_10: + rsrc_data->pack_fmt = 0xc; + break; + case CAM_FORMAT_MIPI_RAW_12: + rsrc_data->pack_fmt = 0xd; + break; + case CAM_FORMAT_PLAIN8: + rsrc_data->pack_fmt = 0x1; + break; + case CAM_FORMAT_PLAIN16_10: + rsrc_data->pack_fmt = 0x5; + rsrc_data->pack_fmt |= 0x10; + break; + case CAM_FORMAT_PLAIN16_12: + rsrc_data->pack_fmt = 0x6; + rsrc_data->pack_fmt |= 0x10; + break; + default: + CAM_ERR(CAM_ISP, "Invalid format %d", + rsrc_data->format); + return -EINVAL; + } + + rsrc_data->en_cfg = 0x1; + } else if (rsrc_data->index >= 2 && rsrc_data->index <= 6) { + /* WM 2-6 stats */ + rsrc_data->width = 0; + rsrc_data->height = 0; + rsrc_data->stride = 1; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } else { + CAM_ERR(CAM_ISP, "Invalid WM:%d requested", rsrc_data->index); + return -EINVAL; + } + + *wm_res = wm_res_local; + *comp_grp_id = rsrc_data->hw_regs->comp_group; + *client_done_mask |= (1 << wm_idx); + + CAM_DBG(CAM_ISP, + "WM:%d processed width:%d height:%d format:0x%x comp_group:%d packt format:0x%x wm mode:%d", + rsrc_data->index, rsrc_data->width, rsrc_data->height, + rsrc_data->format, *comp_grp_id, rsrc_data->pack_fmt, + rsrc_data->mode); + return 0; +} + +static int cam_tfe_bus_release_wm(void *bus_priv, + struct cam_isp_resource_node *wm_res) +{ + struct cam_tfe_bus_wm_resource_data *rsrc_data = wm_res->res_priv; + + rsrc_data->offset = 0; + rsrc_data->width = 0; + rsrc_data->height = 0; + rsrc_data->stride = 0; + rsrc_data->format = 0; + rsrc_data->pack_fmt = 0; + rsrc_data->burst_len = 0; + rsrc_data->irq_subsample_period = 0; + rsrc_data->irq_subsample_pattern = 0; + rsrc_data->framedrop_period = 0; + rsrc_data->framedrop_pattern = 0; + rsrc_data->en_cfg = 0; + rsrc_data->is_dual = 0; + + wm_res->tasklet_info = NULL; + wm_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + CAM_DBG(CAM_ISP, "TFE:%dRelease WM:%d", + rsrc_data->common_data->core_index, rsrc_data->index); + + return 0; +} + +static int cam_tfe_bus_start_wm(struct cam_isp_resource_node *wm_res) +{ + struct cam_tfe_bus_wm_resource_data *rsrc_data = + wm_res->res_priv; + struct cam_tfe_bus_common_data *common_data = + rsrc_data->common_data; + + cam_io_w(0xf, common_data->mem_base + rsrc_data->hw_regs->bw_limit); + + cam_io_w((rsrc_data->height << 16) | rsrc_data->width, + common_data->mem_base + rsrc_data->hw_regs->image_cfg_0); + cam_io_w(rsrc_data->pack_fmt, + common_data->mem_base + rsrc_data->hw_regs->packer_cfg); + + /* Configure stride for RDIs on full TFE and TFE lite */ + if ((rsrc_data->index > 6) && + ((rsrc_data->mode != CAM_ISP_TFE_WM_LINE_BASED_MODE) && + (rsrc_data->out_id != CAM_TFE_BUS_TFE_OUT_PDAF))) { + cam_io_w_mb(rsrc_data->stride, (common_data->mem_base + + rsrc_data->hw_regs->image_cfg_2)); + CAM_DBG(CAM_ISP, "WM:%d configure stride reg :0x%x", + rsrc_data->index, + rsrc_data->stride); + } + + /* Enable WM */ + cam_io_w_mb(rsrc_data->en_cfg, common_data->mem_base + + rsrc_data->hw_regs->cfg); + + CAM_DBG(CAM_ISP, "TFE:%d WM:%d width = %d, height = %d", + common_data->core_index, rsrc_data->index, + rsrc_data->width, rsrc_data->height); + CAM_DBG(CAM_ISP, "WM:%d pk_fmt = %d", rsrc_data->index, + rsrc_data->pack_fmt); + CAM_DBG(CAM_ISP, "WM:%d stride = %d, burst len = %d", + rsrc_data->index, rsrc_data->stride, 0xf); + CAM_DBG(CAM_ISP, "TFE:%d Start WM:%d offset 0x%x val 0x%x", + common_data->core_index, rsrc_data->index, + (uint32_t) rsrc_data->hw_regs->cfg, rsrc_data->en_cfg); + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return 0; +} + +static int cam_tfe_bus_stop_wm(struct cam_isp_resource_node *wm_res) +{ + struct cam_tfe_bus_wm_resource_data *rsrc_data = + wm_res->res_priv; + struct cam_tfe_bus_common_data *common_data = + rsrc_data->common_data; + + /* Disable WM */ + cam_io_w_mb(0x0, common_data->mem_base + rsrc_data->hw_regs->cfg); + CAM_DBG(CAM_ISP, "TFE:%d Stop WM:%d", + rsrc_data->common_data->core_index, rsrc_data->index); + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + return 0; +} + +static int cam_tfe_bus_init_wm_resource(uint32_t index, + struct cam_tfe_bus_priv *bus_priv, + struct cam_tfe_bus_hw_info *hw_info, + struct cam_isp_resource_node *wm_res) +{ + struct cam_tfe_bus_wm_resource_data *rsrc_data; + + rsrc_data = kzalloc(sizeof(struct cam_tfe_bus_wm_resource_data), + GFP_KERNEL); + if (!rsrc_data) { + CAM_DBG(CAM_ISP, "Failed to alloc for WM res priv"); + return -ENOMEM; + } + wm_res->res_priv = rsrc_data; + + rsrc_data->index = index; + rsrc_data->hw_regs = &hw_info->bus_client_reg[index]; + rsrc_data->common_data = &bus_priv->common_data; + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&wm_res->list); + + wm_res->start = cam_tfe_bus_start_wm; + wm_res->stop = cam_tfe_bus_stop_wm; + wm_res->hw_intf = bus_priv->common_data.hw_intf; + + return 0; +} + +static int cam_tfe_bus_deinit_wm_resource( + struct cam_isp_resource_node *wm_res) +{ + struct cam_tfe_bus_wm_resource_data *rsrc_data; + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + INIT_LIST_HEAD(&wm_res->list); + + wm_res->start = NULL; + wm_res->stop = NULL; + wm_res->top_half_handler = NULL; + wm_res->bottom_half_handler = NULL; + wm_res->hw_intf = NULL; + + rsrc_data = wm_res->res_priv; + wm_res->res_priv = NULL; + if (!rsrc_data) + return -ENOMEM; + kfree(rsrc_data); + + return 0; +} + +static void cam_tfe_bus_add_wm_to_comp_grp( + struct cam_isp_resource_node *comp_grp, + uint32_t composite_mask) +{ + struct cam_tfe_bus_comp_grp_data *rsrc_data = comp_grp->res_priv; + + rsrc_data->composite_mask |= composite_mask; +} + +static bool cam_tfe_bus_match_comp_grp( + struct cam_tfe_bus_priv *bus_priv, + struct cam_isp_resource_node **comp_grp, + uint32_t comp_grp_id) +{ + struct cam_tfe_bus_comp_grp_data *rsrc_data = NULL; + struct cam_isp_resource_node *comp_grp_local = NULL; + + list_for_each_entry(comp_grp_local, + &bus_priv->used_comp_grp, list) { + rsrc_data = comp_grp_local->res_priv; + if (rsrc_data->comp_grp_id == comp_grp_id) { + /* Match found */ + *comp_grp = comp_grp_local; + return true; + } + } + + list_for_each_entry(comp_grp_local, + &bus_priv->free_comp_grp, list) { + rsrc_data = comp_grp_local->res_priv; + if (rsrc_data->comp_grp_id == comp_grp_id) { + /* Match found */ + *comp_grp = comp_grp_local; + list_del(&comp_grp_local->list); + list_add_tail(&comp_grp_local->list, + &bus_priv->used_comp_grp); + return false; + } + } + + *comp_grp = NULL; + return false; +} + +static int cam_tfe_bus_acquire_comp_grp( + struct cam_tfe_bus_priv *bus_priv, + struct cam_isp_tfe_out_port_info *out_port_info, + void *tasklet, + uint32_t is_dual, + uint32_t is_master, + struct cam_isp_resource_node **comp_grp, + enum cam_tfe_bus_comp_grp_id comp_grp_id, + struct cam_isp_resource_node *out_rsrc, + uint32_t source_group) +{ + int rc = 0; + struct cam_isp_resource_node *comp_grp_local = NULL; + struct cam_tfe_bus_comp_grp_data *rsrc_data = NULL; + bool previously_acquired = false; + + if (comp_grp_id >= CAM_TFE_BUS_COMP_GRP_0 && + comp_grp_id <= CAM_TFE_BUS_COMP_GRP_7) { + /* Check if matching comp_grp has already been acquired */ + previously_acquired = cam_tfe_bus_match_comp_grp( + bus_priv, &comp_grp_local, comp_grp_id); + } + + if (!comp_grp_local) { + CAM_ERR(CAM_ISP, "Invalid comp_grp_id:%d", comp_grp_id); + return -ENODEV; + } + + rsrc_data = comp_grp_local->res_priv; + if (rsrc_data->acquire_dev_cnt > CAM_TFE_MAX_OUT_RES_PER_COMP_GRP) { + CAM_ERR(CAM_ISP, "Many acquires comp_grp_id:%d", comp_grp_id); + return -ENODEV; + } + + if (!previously_acquired) { + comp_grp_local->tasklet_info = tasklet; + comp_grp_local->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + rsrc_data->is_master = is_master; + rsrc_data->is_dual = is_dual; + + if (is_master) + rsrc_data->addr_sync_mode = 0; + else + rsrc_data->addr_sync_mode = 1; + } else { + rsrc_data = comp_grp_local->res_priv; + /* Do not support runtime change in composite mask */ + if (comp_grp_local->res_state == + CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_ERR(CAM_ISP, "Invalid State %d Comp Grp %u", + comp_grp_local->res_state, + rsrc_data->comp_grp_id); + return -EBUSY; + } + } + + CAM_DBG(CAM_ISP, "Acquire comp_grp id:%u", rsrc_data->comp_grp_id); + rsrc_data->source_grp = source_group; + rsrc_data->out_rsrc[rsrc_data->acquire_dev_cnt] = out_rsrc; + rsrc_data->acquire_dev_cnt++; + *comp_grp = comp_grp_local; + + return rc; +} + +static int cam_tfe_bus_release_comp_grp( + struct cam_tfe_bus_priv *bus_priv, + struct cam_isp_resource_node *comp_grp) +{ + struct cam_isp_resource_node *comp_grp_local = NULL; + struct cam_tfe_bus_comp_grp_data *comp_rsrc_data = NULL; + int match_found = 0; + + if (!comp_grp) { + CAM_ERR(CAM_ISP, "Invalid Params Comp Grp %pK", comp_grp); + return -EINVAL; + } + + if (comp_grp->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, "Already released Comp Grp"); + return 0; + } + + if (comp_grp->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_ERR(CAM_ISP, "Invalid State %d", + comp_grp->res_state); + return -EBUSY; + } + + comp_rsrc_data = comp_grp->res_priv; + CAM_DBG(CAM_ISP, "Comp Grp id %u", comp_rsrc_data->comp_grp_id); + + list_for_each_entry(comp_grp_local, &bus_priv->used_comp_grp, list) { + if (comp_grp_local == comp_grp) { + match_found = 1; + break; + } + } + + if (!match_found) { + CAM_ERR(CAM_ISP, "Could not find comp_grp_id:%u", + comp_rsrc_data->comp_grp_id); + return -ENODEV; + } + + comp_rsrc_data->acquire_dev_cnt--; + if (comp_rsrc_data->acquire_dev_cnt == 0) { + list_del(&comp_grp_local->list); + + comp_rsrc_data->addr_sync_mode = 0; + comp_rsrc_data->composite_mask = 0; + + comp_grp_local->tasklet_info = NULL; + comp_grp_local->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + list_add_tail(&comp_grp_local->list, &bus_priv->free_comp_grp); + CAM_DBG(CAM_ISP, "Comp Grp id %u released", + comp_rsrc_data->comp_grp_id); + } + + return 0; +} + +static int cam_tfe_bus_start_comp_grp( + struct cam_isp_resource_node *comp_grp) +{ + int rc = 0; + uint32_t val; + struct cam_tfe_bus_comp_grp_data *rsrc_data = NULL; + struct cam_tfe_bus_common_data *common_data = NULL; + uint32_t bus_irq_reg_mask_0 = 0; + + rsrc_data = comp_grp->res_priv; + common_data = rsrc_data->common_data; + + CAM_DBG(CAM_ISP, "TFE:%d comp_grp_id:%d streaming state:%d mask:0x%x", + common_data->core_index, rsrc_data->comp_grp_id, + comp_grp->res_state, rsrc_data->composite_mask); + + if (comp_grp->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + return 0; + + if (rsrc_data->is_dual) { + if (rsrc_data->is_master) { + val = cam_io_r(common_data->mem_base + + common_data->common_reg->comp_cfg_0); + val |= (0x1 << (rsrc_data->comp_grp_id + 16)); + cam_io_w_mb(val, common_data->mem_base + + common_data->common_reg->comp_cfg_0); + + val = cam_io_r(common_data->mem_base + + common_data->common_reg->comp_cfg_1); + val |= (0x1 << rsrc_data->comp_grp_id); + cam_io_w_mb(val, common_data->mem_base + + common_data->common_reg->comp_cfg_1); + } else { + val = cam_io_r(common_data->mem_base + + common_data->common_reg->comp_cfg_0); + val |= (0x1 << rsrc_data->comp_grp_id); + val |= (0x1 << (rsrc_data->comp_grp_id + 16)); + cam_io_w(val, common_data->mem_base + + common_data->common_reg->comp_cfg_0); + + val = cam_io_r(common_data->mem_base + + common_data->common_reg->comp_cfg_1); + val |= (0x1 << rsrc_data->comp_grp_id); + cam_io_w(val, common_data->mem_base + + common_data->common_reg->comp_cfg_1); + } + } + + if (rsrc_data->is_dual && !rsrc_data->is_master) + goto end; + + /* Update the composite done mask in bus irq mask*/ + bus_irq_reg_mask_0 = cam_io_r(common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + bus_irq_reg_mask_0 |= (0x1 << (rsrc_data->comp_grp_id + + rsrc_data->common_data->comp_done_shift)); + cam_io_w_mb(bus_irq_reg_mask_0, common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + + CAM_DBG(CAM_ISP, "TFE:%d start COMP_GRP:%d bus_irq_mask_0 0x%x", + common_data->core_index, rsrc_data->comp_grp_id, + bus_irq_reg_mask_0); + +end: + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return rc; +} + +static int cam_tfe_bus_stop_comp_grp( + struct cam_isp_resource_node *comp_grp) +{ + struct cam_tfe_bus_comp_grp_data *rsrc_data = NULL; + struct cam_tfe_bus_common_data *common_data = NULL; + uint32_t bus_irq_reg_mask_0 = 0; + + if (comp_grp->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) + return 0; + + rsrc_data = (struct cam_tfe_bus_comp_grp_data *)comp_grp->res_priv; + common_data = rsrc_data->common_data; + + /* Update the composite done mask in bus irq mask*/ + bus_irq_reg_mask_0 = cam_io_r(common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + bus_irq_reg_mask_0 &= ~(0x1 << (rsrc_data->comp_grp_id + + rsrc_data->common_data->comp_done_shift)); + cam_io_w_mb(bus_irq_reg_mask_0, common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + return 0; +} + +static int cam_tfe_bus_init_comp_grp(uint32_t index, + struct cam_hw_soc_info *soc_info, + struct cam_tfe_bus_priv *bus_priv, + struct cam_tfe_bus_hw_info *hw_info, + struct cam_isp_resource_node *comp_grp) +{ + struct cam_tfe_bus_comp_grp_data *rsrc_data = NULL; + + rsrc_data = kzalloc(sizeof(struct cam_tfe_bus_comp_grp_data), + GFP_KERNEL); + if (!rsrc_data) + return -ENOMEM; + + comp_grp->res_priv = rsrc_data; + + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&comp_grp->list); + + comp_grp->res_id = index; + rsrc_data->comp_grp_id = index; + rsrc_data->common_data = &bus_priv->common_data; + + list_add_tail(&comp_grp->list, &bus_priv->free_comp_grp); + + comp_grp->hw_intf = bus_priv->common_data.hw_intf; + + return 0; +} + +static int cam_tfe_bus_deinit_comp_grp( + struct cam_isp_resource_node *comp_grp) +{ + struct cam_tfe_bus_comp_grp_data *rsrc_data = + comp_grp->res_priv; + + comp_grp->start = NULL; + comp_grp->stop = NULL; + comp_grp->top_half_handler = NULL; + comp_grp->bottom_half_handler = NULL; + comp_grp->hw_intf = NULL; + + list_del_init(&comp_grp->list); + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + + comp_grp->res_priv = NULL; + + if (!rsrc_data) { + CAM_ERR(CAM_ISP, "comp_grp_priv is NULL"); + return -ENODEV; + } + kfree(rsrc_data); + + return 0; +} + +static int cam_tfe_bus_get_secure_mode(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_isp_hw_get_cmd_update *secure_mode = cmd_args; + struct cam_tfe_bus_tfe_out_data *rsrc_data; + uint32_t *mode; + + rsrc_data = (struct cam_tfe_bus_tfe_out_data *) + secure_mode->res->res_priv; + mode = (uint32_t *)secure_mode->data; + *mode = (rsrc_data->secure_mode == CAM_SECURE_MODE_SECURE) ? + true : false; + + return 0; +} + +static int cam_tfe_bus_acquire_tfe_out(void *priv, void *acquire_args, + uint32_t args_size) +{ + struct cam_tfe_bus_priv *bus_priv = priv; + struct cam_tfe_acquire_args *acq_args = acquire_args; + struct cam_tfe_hw_tfe_out_acquire_args *out_acquire_args; + struct cam_isp_resource_node *rsrc_node = NULL; + struct cam_tfe_bus_tfe_out_data *rsrc_data = NULL; + enum cam_tfe_bus_tfe_out_id tfe_out_res_id; + enum cam_tfe_bus_comp_grp_id comp_grp_id; + int i, rc = -ENODEV; + uint32_t secure_caps = 0, mode; + uint32_t format, num_wm, client_done_mask = 0; + + if (!bus_priv || !acquire_args) { + CAM_ERR(CAM_ISP, "Invalid Param"); + return -EINVAL; + } + + out_acquire_args = &acq_args->tfe_out; + format = out_acquire_args->out_port_info->format; + + CAM_DBG(CAM_ISP, "resid 0x%x fmt:%d, sec mode:%d wm mode:%d", + out_acquire_args->out_port_info->res_id, format, + out_acquire_args->out_port_info->secure_mode, + out_acquire_args->out_port_info->wm_mode); + CAM_DBG(CAM_ISP, "width:%d, height:%d stride:%d", + out_acquire_args->out_port_info->width, + out_acquire_args->out_port_info->height, + out_acquire_args->out_port_info->stride); + + tfe_out_res_id = cam_tfe_bus_get_out_res_id( + out_acquire_args->out_port_info->res_id); + if (tfe_out_res_id == CAM_TFE_BUS_TFE_OUT_MAX) + return -ENODEV; + + num_wm = cam_tfe_bus_get_num_wm(tfe_out_res_id, format); + if (num_wm < 1) + return -EINVAL; + + rsrc_node = &bus_priv->tfe_out[tfe_out_res_id]; + if (rsrc_node->res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, "Resource not available: Res_id %d state:%d", + tfe_out_res_id, rsrc_node->res_state); + return -EBUSY; + } + + rsrc_data = rsrc_node->res_priv; + rsrc_data->common_data->event_cb = acq_args->event_cb; + rsrc_data->event_cb = acq_args->event_cb; + rsrc_data->priv = acq_args->priv; + + secure_caps = cam_tfe_bus_can_be_secure(rsrc_data->out_id); + mode = out_acquire_args->out_port_info->secure_mode; + mutex_lock(&rsrc_data->common_data->bus_mutex); + if (secure_caps) { + if (!rsrc_data->common_data->num_sec_out) { + rsrc_data->secure_mode = mode; + rsrc_data->common_data->secure_mode = mode; + } else { + if (mode == rsrc_data->common_data->secure_mode) { + rsrc_data->secure_mode = + rsrc_data->common_data->secure_mode; + } else { + rc = -EINVAL; + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Mismatch: Acquire mode[%d], drvr mode[%d]", + rsrc_data->common_data->secure_mode, + mode); + mutex_unlock( + &rsrc_data->common_data->bus_mutex); + return -EINVAL; + } + } + rsrc_data->common_data->num_sec_out++; + } + mutex_unlock(&rsrc_data->common_data->bus_mutex); + + bus_priv->tasklet_info = acq_args->tasklet; + rsrc_data->num_wm = num_wm; + rsrc_node->rdi_only_ctx = 0; + rsrc_node->res_id = out_acquire_args->out_port_info->res_id; + rsrc_node->cdm_ops = out_acquire_args->cdm_ops; + rsrc_data->cdm_util_ops = out_acquire_args->cdm_ops; + + /* Acquire WM and retrieve COMP GRP ID */ + for (i = 0; i < num_wm; i++) { + rc = cam_tfe_bus_acquire_wm(bus_priv, + out_acquire_args->out_port_info, + &rsrc_data->wm_res[i], + acq_args->tasklet, + tfe_out_res_id, + i, + &client_done_mask, + out_acquire_args->is_dual, + &comp_grp_id); + if (rc) { + CAM_ERR(CAM_ISP, + "TFE:%d WM acquire failed for Out %d rc=%d", + rsrc_data->common_data->core_index, + tfe_out_res_id, rc); + goto release_wm; + } + } + + /* Acquire composite group using COMP GRP ID */ + rc = cam_tfe_bus_acquire_comp_grp(bus_priv, + out_acquire_args->out_port_info, + acq_args->tasklet, + out_acquire_args->is_dual, + out_acquire_args->is_master, + &rsrc_data->comp_grp, + comp_grp_id, + rsrc_node, + rsrc_data->source_group); + if (rc) { + CAM_ERR(CAM_ISP, + "TFE%d Comp_Grp acquire fail for Out %d rc=%d", + rsrc_data->common_data->core_index, + tfe_out_res_id, rc); + return rc; + } + + rsrc_data->is_dual = out_acquire_args->is_dual; + rsrc_data->is_master = out_acquire_args->is_master; + + cam_tfe_bus_add_wm_to_comp_grp(rsrc_data->comp_grp, + client_done_mask); + + rsrc_node->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + out_acquire_args->rsrc_node = rsrc_node; + + return rc; + +release_wm: + for (i--; i >= 0; i--) + cam_tfe_bus_release_wm(bus_priv, rsrc_data->wm_res[i]); + + if (rsrc_data->comp_grp) + cam_tfe_bus_release_comp_grp(bus_priv, rsrc_data->comp_grp); + + return rc; +} + +static int cam_tfe_bus_release_tfe_out(void *priv, void *release_args, + uint32_t args_size) +{ + struct cam_tfe_bus_priv *bus_priv = priv; + struct cam_isp_resource_node *tfe_out = NULL; + struct cam_tfe_bus_tfe_out_data *rsrc_data = NULL; + uint32_t secure_caps = 0; + uint32_t i; + + if (!bus_priv || !release_args) { + CAM_ERR(CAM_ISP, "Invalid input bus_priv %pK release_args %pK", + bus_priv, release_args); + return -EINVAL; + } + + tfe_out = (struct cam_isp_resource_node *)release_args; + rsrc_data = (struct cam_tfe_bus_tfe_out_data *)tfe_out->res_priv; + + if (tfe_out->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Invalid resource state:%d res id:%d", + tfe_out->res_state, tfe_out->res_id); + } + + for (i = 0; i < rsrc_data->num_wm; i++) + cam_tfe_bus_release_wm(bus_priv, rsrc_data->wm_res[i]); + + rsrc_data->num_wm = 0; + + if (rsrc_data->comp_grp) + cam_tfe_bus_release_comp_grp(bus_priv, rsrc_data->comp_grp); + + rsrc_data->comp_grp = NULL; + + tfe_out->tasklet_info = NULL; + tfe_out->cdm_ops = NULL; + rsrc_data->cdm_util_ops = NULL; + + secure_caps = cam_tfe_bus_can_be_secure(rsrc_data->out_id); + mutex_lock(&rsrc_data->common_data->bus_mutex); + if (secure_caps) { + if (rsrc_data->secure_mode == + rsrc_data->common_data->secure_mode) { + rsrc_data->common_data->num_sec_out--; + rsrc_data->secure_mode = + CAM_SECURE_MODE_NON_SECURE; + } else { + /* + * The validity of the mode is properly + * checked while acquiring the output port. + * not expected to reach here, unless there is + * some corruption. + */ + CAM_ERR(CAM_ISP, "driver[%d],resource[%d] mismatch", + rsrc_data->common_data->secure_mode, + rsrc_data->secure_mode); + } + + if (!rsrc_data->common_data->num_sec_out) + rsrc_data->common_data->secure_mode = + CAM_SECURE_MODE_NON_SECURE; + } + mutex_unlock(&rsrc_data->common_data->bus_mutex); + + if (tfe_out->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) + tfe_out->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + return 0; +} + +static int cam_tfe_bus_start_tfe_out(void *hw_priv, + void *start_hw_args, uint32_t arg_size) +{ + struct cam_isp_resource_node *tfe_out = hw_priv; + struct cam_tfe_bus_tfe_out_data *rsrc_data = NULL; + struct cam_tfe_bus_common_data *common_data = NULL; + uint32_t bus_irq_reg_mask_0 = 0; + uint32_t rup_group_id = 0; + int rc = 0, i; + + if (!tfe_out) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + + rsrc_data = tfe_out->res_priv; + common_data = rsrc_data->common_data; + rup_group_id = rsrc_data->rup_group_id; + + CAM_DBG(CAM_ISP, "TFE:%d Start resource index %d", + common_data->core_index, rsrc_data->out_id); + + if (tfe_out->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "TFE:%d Invalid resource state:%d", + common_data->core_index, tfe_out->res_state); + return -EACCES; + } + + for (i = 0; i < rsrc_data->num_wm; i++) + rc = cam_tfe_bus_start_wm(rsrc_data->wm_res[i]); + + rc = cam_tfe_bus_start_comp_grp(rsrc_data->comp_grp); + + if (rsrc_data->is_dual && !rsrc_data->is_master && + !tfe_out->rdi_only_ctx) + goto end; + + if (common_data->rup_irq_enable[rup_group_id]) + goto end; + + /* Update the composite regupdate mask in bus irq mask*/ + bus_irq_reg_mask_0 = cam_io_r(common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + bus_irq_reg_mask_0 |= (0x1 << rup_group_id); + cam_io_w_mb(bus_irq_reg_mask_0, common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + common_data->rup_irq_enable[rup_group_id] = true; + +end: + tfe_out->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + return rc; +} + +static int cam_tfe_bus_stop_tfe_out(void *hw_priv, + void *stop_hw_args, uint32_t arg_size) +{ + struct cam_isp_resource_node *tfe_out = hw_priv; + struct cam_tfe_bus_tfe_out_data *rsrc_data = NULL; + struct cam_tfe_bus_common_data *common_data = NULL; + uint32_t bus_irq_reg_mask_0 = 0, rup_group = 0; + int rc = 0, i; + + if (!tfe_out) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + + rsrc_data = tfe_out->res_priv; + common_data = rsrc_data->common_data; + rup_group = rsrc_data->rup_group_id; + + if (tfe_out->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE || + tfe_out->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_DBG(CAM_ISP, "tfe_out res_state is %d", tfe_out->res_state); + return rc; + } + + rc = cam_tfe_bus_stop_comp_grp(rsrc_data->comp_grp); + + for (i = 0; i < rsrc_data->num_wm; i++) + rc = cam_tfe_bus_stop_wm(rsrc_data->wm_res[i]); + + + if (!common_data->rup_irq_enable[rup_group]) + goto end; + + /* disable composite regupdate mask in bus irq mask register*/ + bus_irq_reg_mask_0 = cam_io_r(common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + bus_irq_reg_mask_0 &= ~(0x1 << rup_group); + cam_io_w_mb(bus_irq_reg_mask_0, common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + common_data->rup_irq_enable[rup_group] = false; + +end: + tfe_out->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + return rc; +} + +static int cam_tfe_bus_init_tfe_out_resource(uint32_t index, + struct cam_tfe_bus_priv *bus_priv, + struct cam_tfe_bus_hw_info *hw_info) +{ + struct cam_isp_resource_node *tfe_out = NULL; + struct cam_tfe_bus_tfe_out_data *rsrc_data = NULL; + int rc = 0; + int32_t tfe_out_id = hw_info->tfe_out_hw_info[index].tfe_out_id; + + if (tfe_out_id < 0 || + tfe_out_id >= CAM_TFE_BUS_TFE_OUT_MAX) { + CAM_ERR(CAM_ISP, "Init TFE Out failed, Invalid type=%d", + tfe_out_id); + return -EINVAL; + } + + tfe_out = &bus_priv->tfe_out[tfe_out_id]; + if (tfe_out->res_state != CAM_ISP_RESOURCE_STATE_UNAVAILABLE || + tfe_out->res_priv) { + CAM_ERR(CAM_ISP, "tfe_out_id %d has already been initialized", + tfe_out_id); + return -EFAULT; + } + + rsrc_data = kzalloc(sizeof(struct cam_tfe_bus_tfe_out_data), + GFP_KERNEL); + if (!rsrc_data) { + rc = -ENOMEM; + return rc; + } + + tfe_out->res_priv = rsrc_data; + + tfe_out->res_type = CAM_ISP_RESOURCE_TFE_OUT; + tfe_out->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&tfe_out->list); + + rsrc_data->composite_group = + hw_info->tfe_out_hw_info[index].composite_group; + rsrc_data->rup_group_id = + hw_info->tfe_out_hw_info[index].rup_group_id; + rsrc_data->out_id = + hw_info->tfe_out_hw_info[index].tfe_out_id; + rsrc_data->common_data = &bus_priv->common_data; + rsrc_data->max_width = + hw_info->tfe_out_hw_info[index].max_width; + rsrc_data->max_height = + hw_info->tfe_out_hw_info[index].max_height; + rsrc_data->secure_mode = CAM_SECURE_MODE_NON_SECURE; + + tfe_out->hw_intf = bus_priv->common_data.hw_intf; + + return 0; +} + +static int cam_tfe_bus_deinit_tfe_out_resource( + struct cam_isp_resource_node *tfe_out) +{ + struct cam_tfe_bus_tfe_out_data *rsrc_data = tfe_out->res_priv; + + if (tfe_out->res_state == CAM_ISP_RESOURCE_STATE_UNAVAILABLE) { + /* + * This is not error. It can happen if the resource is + * never supported in the HW. + */ + CAM_DBG(CAM_ISP, "HW%d Res %d already deinitialized"); + return 0; + } + + tfe_out->start = NULL; + tfe_out->stop = NULL; + tfe_out->top_half_handler = NULL; + tfe_out->bottom_half_handler = NULL; + tfe_out->hw_intf = NULL; + + tfe_out->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + INIT_LIST_HEAD(&tfe_out->list); + tfe_out->res_priv = NULL; + + if (!rsrc_data) + return -ENOMEM; + kfree(rsrc_data); + + return 0; +} + +static const char *cam_tfe_bus_rup_type( + uint32_t group_id) +{ + switch (group_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + return "CAMIF RUP"; + case CAM_ISP_HW_TFE_IN_RDI0: + return "RDI0 RUP"; + case CAM_ISP_HW_TFE_IN_RDI1: + return "RDI1 RUP"; + case CAM_ISP_HW_TFE_IN_RDI2: + return "RDI2 RUP"; + default: + return "invalid rup group"; + } +} +static int cam_tfe_bus_rup_bottom_half( + struct cam_tfe_bus_priv *bus_priv, + struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_bus_common_data *common_data; + struct cam_tfe_bus_tfe_out_data *out_rsrc_data; + struct cam_isp_hw_event_info evt_info; + uint32_t i, j; + + common_data = &bus_priv->common_data; + evt_info.hw_idx = bus_priv->common_data.core_index; + evt_info.res_type = CAM_ISP_RESOURCE_TFE_OUT; + + for (i = 0; i < CAM_TFE_BUS_RUP_GRP_MAX; i++) { + if (!(evt_payload->bus_irq_val[0] & + bus_priv->comp_rup_done_mask)) + break; + + if (evt_payload->bus_irq_val[0] & BIT(i)) { + for (j = 0; j < CAM_TFE_BUS_TFE_OUT_MAX; j++) { + out_rsrc_data = + (struct cam_tfe_bus_tfe_out_data *) + bus_priv->tfe_out[j].res_priv; + if ((out_rsrc_data->rup_group_id == i) && + (bus_priv->tfe_out[j].res_state == + CAM_ISP_RESOURCE_STATE_STREAMING)) + break; + } + + if (j == CAM_TFE_BUS_TFE_OUT_MAX) { + CAM_ERR(CAM_ISP, + "TFE:%d out rsc active status[0]:0x%x", + bus_priv->common_data.core_index, + evt_payload->bus_irq_val[0]); + continue; + } + + CAM_DBG(CAM_ISP, "TFE:%d Received %s", + bus_priv->common_data.core_index, + cam_tfe_bus_rup_type(i)); + evt_info.res_id = i; + if (out_rsrc_data->event_cb) { + out_rsrc_data->event_cb( + out_rsrc_data->priv, + CAM_ISP_HW_EVENT_REG_UPDATE, + (void *)&evt_info); + /* reset the rup bit */ + evt_payload->bus_irq_val[0] &= ~BIT(i); + } else + CAM_ERR(CAM_ISP, + "TFE:%d No event cb id:%lld evt id:%d", + bus_priv->common_data.core_index, + out_rsrc_data->out_id, evt_info.res_id); + } + } + + return 0; +} + +static int cam_tfe_bus_bufdone_bottom_half( + struct cam_tfe_bus_priv *bus_priv, + struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_bus_common_data *common_data; + struct cam_tfe_bus_tfe_out_data *out_rsrc_data; + struct cam_isp_hw_event_info evt_info; + struct cam_isp_resource_node *out_rsrc = NULL; + struct cam_tfe_bus_comp_grp_data *comp_rsrc_data; + uint32_t i, j; + + common_data = &bus_priv->common_data; + + for (i = 0; i < CAM_TFE_BUS_COMP_GRP_MAX; i++) { + if (!(evt_payload->bus_irq_val[0] & + bus_priv->comp_buf_done_mask)) + break; + + comp_rsrc_data = (struct cam_tfe_bus_comp_grp_data *) + bus_priv->comp_grp[i].res_priv; + + if (evt_payload->bus_irq_val[0] & + BIT(comp_rsrc_data->comp_grp_id + + bus_priv->common_data.comp_done_shift)) { + for (j = 0; j < comp_rsrc_data->acquire_dev_cnt; j++) { + out_rsrc = comp_rsrc_data->out_rsrc[j]; + out_rsrc_data = out_rsrc->res_priv; + evt_info.res_type = out_rsrc->res_type; + evt_info.hw_idx = out_rsrc->hw_intf->hw_idx; + evt_info.res_id = out_rsrc->res_id; + out_rsrc_data->event_cb(out_rsrc_data->priv, + CAM_ISP_HW_EVENT_DONE, + (void *)&evt_info); + } + + evt_payload->bus_irq_val[0] &= + ~BIT(comp_rsrc_data->comp_grp_id + + bus_priv->common_data.comp_done_shift); + } + } + + return 0; +} + +static void cam_tfe_bus_error_bottom_half( + struct cam_tfe_bus_priv *bus_priv, + struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_bus_wm_resource_data *rsrc_data; + struct cam_tfe_bus_reg_offset_common *common_reg; + uint32_t i, overflow_status, image_size_violation_status; + uint32_t ccif_violation_status; + + common_reg = bus_priv->common_data.common_reg; + + CAM_INFO(CAM_ISP, "BUS IRQ[0]:0x%x BUS IRQ[1]:0x%x", + evt_payload->bus_irq_val[0], evt_payload->bus_irq_val[1]); + + overflow_status = cam_io_r_mb(bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->overflow_status); + + image_size_violation_status = cam_io_r_mb( + bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->image_size_violation_status); + + ccif_violation_status = cam_io_r_mb(bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->ccif_violation_status); + + CAM_INFO(CAM_ISP, + "ccif violation status:0x%x image size violation:0x%x overflow status:0x%x", + ccif_violation_status, + image_size_violation_status, + overflow_status); + + /* Check the bus errors */ + if (evt_payload->bus_irq_val[0] & BIT(common_reg->cons_violation_shift)) + CAM_INFO(CAM_ISP, "CONS_VIOLATION"); + + if (evt_payload->bus_irq_val[0] & BIT(common_reg->violation_shift)) + CAM_INFO(CAM_ISP, "VIOLATION"); + + if (evt_payload->bus_irq_val[0] & + BIT(common_reg->image_size_violation)) { + CAM_INFO(CAM_ISP, "IMAGE_SIZE_VIOLATION val :0x%x", + evt_payload->image_size_violation_status); + + for (i = 0; i < CAM_TFE_BUS_MAX_CLIENTS; i++) { + if (!(evt_payload->image_size_violation_status >> i)) + break; + + if (evt_payload->image_size_violation_status & BIT(i)) { + rsrc_data = bus_priv->bus_client[i].res_priv; + CAM_INFO(CAM_ISP, + "WM:%d width 0x%x height:0x%x format:%d stride:0x%x offset:0x%x encfg:0x%x", + i, + rsrc_data->acquired_width, + rsrc_data->acquired_height, + rsrc_data->format, + rsrc_data->acquired_stride, + rsrc_data->offset, + rsrc_data->en_cfg); + + CAM_INFO(CAM_ISP, + "WM:%d current width 0x%x height:0x%x stride:0x%x", + i, + rsrc_data->width, + rsrc_data->height, + rsrc_data->stride); + + } + } + } + + if (overflow_status) { + for (i = 0; i < CAM_TFE_BUS_MAX_CLIENTS; i++) { + + if (!(evt_payload->overflow_status >> i)) + break; + + if (evt_payload->overflow_status & BIT(i)) { + rsrc_data = bus_priv->bus_client[i].res_priv; + CAM_INFO(CAM_ISP, + "WM:%d %s BUS OVERFLOW width0x%x height:0x%x format:%d stride:0x%x offset:0x%x encfg:%x", + i, + rsrc_data->hw_regs->client_name, + rsrc_data->acquired_width, + rsrc_data->acquired_height, + rsrc_data->format, + rsrc_data->acquired_stride, + rsrc_data->offset, + rsrc_data->en_cfg); + + CAM_INFO(CAM_ISP, + "WM:%d current width:0x%x height:0x%x stride:0x%x", + i, + rsrc_data->width, + rsrc_data->height, + rsrc_data->stride); + } + } + } +} + +static int cam_tfe_bus_bottom_half(void *priv, + bool rup_process, struct cam_tfe_irq_evt_payload *evt_payload, + bool error_process) +{ + struct cam_tfe_bus_priv *bus_priv; + uint32_t val; + + if (!priv || !evt_payload) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid priv param"); + return -EINVAL; + } + bus_priv = (struct cam_tfe_bus_priv *) priv; + + if (error_process) { + cam_tfe_bus_error_bottom_half(bus_priv, evt_payload); + goto end; + } + + /* if bus errors are there, mask all bus errors */ + if (evt_payload->bus_irq_val[0] & bus_priv->bus_irq_error_mask[0]) { + val = cam_io_r(bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[0]); + val &= ~bus_priv->bus_irq_error_mask[0]; + cam_io_w(val, bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[0]); + + } + + if (rup_process) { + if (evt_payload->bus_irq_val[0] & + bus_priv->comp_rup_done_mask) + cam_tfe_bus_rup_bottom_half(bus_priv, evt_payload); + } else { + if (evt_payload->bus_irq_val[0] & + bus_priv->comp_buf_done_mask) + cam_tfe_bus_bufdone_bottom_half(bus_priv, evt_payload); + } + +end: + return 0; + +} + +static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv; + struct cam_isp_hw_get_cmd_update *update_buf; + struct cam_buf_io_cfg *io_cfg; + struct cam_tfe_bus_tfe_out_data *tfe_out_data = NULL; + struct cam_tfe_bus_wm_resource_data *wm_data = NULL; + uint32_t *reg_val_pair; + uint32_t i, j, size = 0; + uint32_t frame_inc = 0, val; + + bus_priv = (struct cam_tfe_bus_priv *) priv; + update_buf = (struct cam_isp_hw_get_cmd_update *) cmd_args; + + tfe_out_data = (struct cam_tfe_bus_tfe_out_data *) + update_buf->res->res_priv; + + if (!tfe_out_data || !tfe_out_data->cdm_util_ops) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + if (update_buf->wm_update->num_buf != tfe_out_data->num_wm) { + CAM_ERR(CAM_ISP, + "Failed! Invalid number buffers:%d required:%d", + update_buf->wm_update->num_buf, tfe_out_data->num_wm); + return -EINVAL; + } + + reg_val_pair = &tfe_out_data->common_data->io_buf_update[0]; + io_cfg = update_buf->wm_update->io_cfg; + + for (i = 0, j = 0; i < tfe_out_data->num_wm; i++) { + if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { + CAM_ERR(CAM_ISP, + "reg_val_pair %d exceeds the array limit %zu", + j, MAX_REG_VAL_PAIR_SIZE); + return -ENOMEM; + } + + wm_data = tfe_out_data->wm_res[i]->res_priv; + /* update width register */ + val = ((wm_data->height << 16) | (wm_data->width & 0xFFFF)); + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_cfg_0, val); + CAM_DBG(CAM_ISP, "WM:%d image height and width 0x%x", + wm_data->index, reg_val_pair[j-1]); + + val = wm_data->offset; + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_cfg_1, val); + CAM_DBG(CAM_ISP, "WM:%d xinit 0x%x", + wm_data->index, reg_val_pair[j-1]); + + if ((wm_data->index < 7) || ((wm_data->index >= 7) && + (wm_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE)) || + (wm_data->out_id == CAM_TFE_BUS_TFE_OUT_PDAF)) { + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_cfg_2, + io_cfg->planes[i].plane_stride); + wm_data->stride = io_cfg->planes[i].plane_stride; + CAM_DBG(CAM_ISP, "WM %d image stride 0x%x", + wm_data->index, reg_val_pair[j-1]); + } + + frame_inc = io_cfg->planes[i].plane_stride * + io_cfg->planes[i].slice_height; + + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_addr, + update_buf->wm_update->image_buf[i]); + CAM_DBG(CAM_ISP, "WM %d image address 0x%x", + wm_data->index, reg_val_pair[j-1]); + + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->frame_incr, frame_inc); + CAM_DBG(CAM_ISP, "WM %d frame_inc %d", + wm_data->index, reg_val_pair[j-1]); + + /* enable the WM */ + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->cfg, + wm_data->en_cfg); + } + + size = tfe_out_data->cdm_util_ops->cdm_required_size_reg_random(j/2); + + /* cdm util returns dwords, need to convert to bytes */ + if ((size * 4) > update_buf->cmd.size) { + CAM_ERR(CAM_ISP, + "Failed! Buf size:%d insufficient, expected size:%d", + update_buf->cmd.size, size); + return -ENOMEM; + } + + tfe_out_data->cdm_util_ops->cdm_write_regrandom( + update_buf->cmd.cmd_buf_addr, j/2, reg_val_pair); + + /* cdm util returns dwords, need to convert to bytes */ + update_buf->cmd.used_bytes = size * 4; + + return 0; +} + +static int cam_tfe_bus_update_hfr(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv; + struct cam_isp_hw_get_cmd_update *update_hfr; + struct cam_tfe_bus_tfe_out_data *tfe_out_data = NULL; + struct cam_tfe_bus_wm_resource_data *wm_data = NULL; + struct cam_isp_tfe_port_hfr_config *hfr_cfg = NULL; + uint32_t *reg_val_pair; + uint32_t i, j, size = 0; + + bus_priv = (struct cam_tfe_bus_priv *) priv; + update_hfr = (struct cam_isp_hw_get_cmd_update *) cmd_args; + + tfe_out_data = (struct cam_tfe_bus_tfe_out_data *) + update_hfr->res->res_priv; + + if (!tfe_out_data || !tfe_out_data->cdm_util_ops) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + reg_val_pair = &tfe_out_data->common_data->io_buf_update[0]; + hfr_cfg = (struct cam_isp_tfe_port_hfr_config *)update_hfr->data; + + for (i = 0, j = 0; i < tfe_out_data->num_wm; i++) { + if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { + CAM_ERR(CAM_ISP, + "reg_val_pair %d exceeds the array limit %zu", + j, MAX_REG_VAL_PAIR_SIZE); + return -ENOMEM; + } + + wm_data = tfe_out_data->wm_res[i]->res_priv; + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->framedrop_pattern, + hfr_cfg->framedrop_pattern); + wm_data->framedrop_pattern = hfr_cfg->framedrop_pattern; + CAM_DBG(CAM_ISP, "WM:%d framedrop pattern 0x%x", + wm_data->index, wm_data->framedrop_pattern); + + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->framedrop_period, + hfr_cfg->framedrop_period); + wm_data->framedrop_period = hfr_cfg->framedrop_period; + CAM_DBG(CAM_ISP, "WM:%d framedrop period 0x%x", + wm_data->index, wm_data->framedrop_period); + + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->irq_subsample_period, + hfr_cfg->subsample_period); + wm_data->irq_subsample_period = hfr_cfg->subsample_period; + CAM_DBG(CAM_ISP, "WM:%d irq subsample period 0x%x", + wm_data->index, wm_data->irq_subsample_period); + + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->irq_subsample_pattern, + hfr_cfg->subsample_pattern); + wm_data->irq_subsample_pattern = hfr_cfg->subsample_pattern; + CAM_DBG(CAM_ISP, "WM:%d irq subsample pattern 0x%x", + wm_data->index, wm_data->irq_subsample_pattern); + } + + size = tfe_out_data->cdm_util_ops->cdm_required_size_reg_random(j/2); + + /* cdm util returns dwords, need to convert to bytes */ + if ((size * 4) > update_hfr->cmd.size) { + CAM_ERR(CAM_ISP, + "Failed! Buf size:%d insufficient, expected size:%d", + update_hfr->cmd.size, size); + return -ENOMEM; + } + + tfe_out_data->cdm_util_ops->cdm_write_regrandom( + update_hfr->cmd.cmd_buf_addr, j/2, reg_val_pair); + + /* cdm util returns dwords, need to convert to bytes */ + update_hfr->cmd.used_bytes = size * 4; + + return 0; +} + +static int cam_tfe_bus_update_stripe_cfg(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv; + struct cam_tfe_dual_update_args *stripe_args; + struct cam_tfe_bus_tfe_out_data *tfe_out_data = NULL; + struct cam_tfe_bus_wm_resource_data *wm_data = NULL; + struct cam_isp_tfe_dual_stripe_config *stripe_config; + uint32_t i; + + bus_priv = (struct cam_tfe_bus_priv *) priv; + stripe_args = (struct cam_tfe_dual_update_args *)cmd_args; + + tfe_out_data = (struct cam_tfe_bus_tfe_out_data *) + stripe_args->res->res_priv; + + if (!tfe_out_data) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + if (stripe_args->res->res_id < CAM_ISP_TFE_OUT_RES_BASE || + stripe_args->res->res_id >= CAM_ISP_TFE_OUT_RES_MAX) + return 0; + + stripe_config = (struct cam_isp_tfe_dual_stripe_config *) + stripe_args->stripe_config; + + for (i = 0; i < tfe_out_data->num_wm; i++) { + stripe_config = &stripe_args->stripe_config[i]; + wm_data = tfe_out_data->wm_res[i]->res_priv; + wm_data->width = stripe_config->width; + wm_data->offset = stripe_config->offset; + CAM_DBG(CAM_ISP, "id:%x WM:%d width:0x%x offset:0x%x", + stripe_args->res->res_id, wm_data->index, + wm_data->width, wm_data->offset); + } + + return 0; +} + +static int cam_tfe_bus_init_hw(void *hw_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv = hw_priv; + uint32_t i, top_irq_reg_mask[3] = {0}; + int rc = -EINVAL; + + if (!bus_priv) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + top_irq_reg_mask[0] = (1 << bus_priv->top_bus_wr_irq_shift); + + rc = cam_tfe_irq_config(bus_priv->common_data.tfe_core_data, + top_irq_reg_mask, CAM_TFE_TOP_IRQ_REG_NUM, true); + if (rc) + return rc; + + /* configure the error irq */ + for (i = 0; i < CAM_TFE_BUS_IRQ_REGISTERS_MAX; i++) + cam_io_w(bus_priv->bus_irq_error_mask[i], + bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[i]); + + return 0; +} + +static int cam_tfe_bus_deinit_hw(void *hw_priv, + void *deinit_hw_args, uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv = hw_priv; + uint32_t top_irq_reg_mask[3] = {0}; + int rc = 0; + + if (!bus_priv) { + CAM_ERR(CAM_ISP, "Error: Invalid args"); + return -EINVAL; + } + top_irq_reg_mask[0] = (1 << bus_priv->top_bus_wr_irq_shift); + rc = cam_tfe_irq_config(bus_priv->common_data.tfe_core_data, + top_irq_reg_mask, CAM_TFE_TOP_IRQ_REG_NUM, false); + if (rc) + return rc; + + /* configure the error irq */ + cam_io_w(0, bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[0]); + + cam_io_w_mb(0, bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[1]); + + return rc; +} + +static int cam_tfe_bus_process_cmd(void *priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv; + int rc = -EINVAL; + uint32_t i, val; + + if (!priv || !cmd_args) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_BUF_UPDATE: + rc = cam_tfe_bus_update_wm(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_GET_HFR_UPDATE: + rc = cam_tfe_bus_update_hfr(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_GET_SECURE_MODE: + rc = cam_tfe_bus_get_secure_mode(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_STRIPE_UPDATE: + rc = cam_tfe_bus_update_stripe_cfg(priv, + cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ: + bus_priv = (struct cam_tfe_bus_priv *) priv; + /* disable the bus error interrupts */ + for (i = 0; i < CAM_TFE_BUS_IRQ_REGISTERS_MAX; i++) { + val = cam_io_r(bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[i]); + val &= ~bus_priv->bus_irq_error_mask[i]; + cam_io_w(val, bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[i]); + } + break; + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid camif process command:%d", + cmd_type); + break; + } + + return rc; +} + +int cam_tfe_bus_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *bus_hw_info, + void *core_data, + struct cam_tfe_bus **tfe_bus) +{ + int i, rc = 0; + struct cam_tfe_bus_priv *bus_priv = NULL; + struct cam_tfe_bus *tfe_bus_local; + struct cam_tfe_bus_hw_info *hw_info = bus_hw_info; + + if (!soc_info || !hw_intf || !bus_hw_info) { + CAM_ERR(CAM_ISP, + "Invalid params soc_info:%pK hw_intf:%pK hw_info%pK", + soc_info, hw_intf, bus_hw_info); + rc = -EINVAL; + goto end; + } + + tfe_bus_local = kzalloc(sizeof(struct cam_tfe_bus), GFP_KERNEL); + if (!tfe_bus_local) { + CAM_DBG(CAM_ISP, "Failed to alloc for tfe_bus"); + rc = -ENOMEM; + goto end; + } + + bus_priv = kzalloc(sizeof(struct cam_tfe_bus_priv), + GFP_KERNEL); + if (!bus_priv) { + CAM_DBG(CAM_ISP, "Failed to alloc for tfe_bus_priv"); + rc = -ENOMEM; + goto free_bus_local; + } + tfe_bus_local->bus_priv = bus_priv; + + bus_priv->num_client = hw_info->num_client; + bus_priv->num_out = hw_info->num_out; + bus_priv->top_bus_wr_irq_shift = hw_info->top_bus_wr_irq_shift; + bus_priv->common_data.comp_done_shift = hw_info->comp_done_shift; + + bus_priv->common_data.num_sec_out = 0; + bus_priv->common_data.secure_mode = CAM_SECURE_MODE_NON_SECURE; + bus_priv->common_data.core_index = soc_info->index; + bus_priv->common_data.mem_base = + CAM_SOC_GET_REG_MAP_START(soc_info, TFE_CORE_BASE_IDX); + bus_priv->common_data.hw_intf = hw_intf; + bus_priv->common_data.tfe_core_data = core_data; + bus_priv->common_data.common_reg = &hw_info->common_reg; + bus_priv->comp_buf_done_mask = hw_info->comp_buf_done_mask; + bus_priv->comp_rup_done_mask = hw_info->comp_rup_done_mask; + + for (i = 0; i < CAM_TFE_BUS_IRQ_REGISTERS_MAX; i++) + bus_priv->bus_irq_error_mask[i] = + hw_info->bus_irq_error_mask[i]; + + if (strnstr(soc_info->compatible, "lite", + strlen(soc_info->compatible)) != NULL) + bus_priv->common_data.is_lite = true; + else + bus_priv->common_data.is_lite = false; + + for (i = 0; i < CAM_TFE_BUS_RUP_GRP_MAX; i++) + bus_priv->common_data.rup_irq_enable[i] = false; + + mutex_init(&bus_priv->common_data.bus_mutex); + + INIT_LIST_HEAD(&bus_priv->free_comp_grp); + INIT_LIST_HEAD(&bus_priv->used_comp_grp); + + for (i = 0; i < bus_priv->num_client; i++) { + rc = cam_tfe_bus_init_wm_resource(i, bus_priv, bus_hw_info, + &bus_priv->bus_client[i]); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Init WM failed rc=%d", rc); + goto deinit_wm; + } + } + + for (i = 0; i < CAM_TFE_BUS_COMP_GRP_MAX; i++) { + rc = cam_tfe_bus_init_comp_grp(i, soc_info, + bus_priv, bus_hw_info, + &bus_priv->comp_grp[i]); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Init Comp Grp failed rc=%d", rc); + goto deinit_comp_grp; + } + } + + for (i = 0; i < bus_priv->num_out; i++) { + rc = cam_tfe_bus_init_tfe_out_resource(i, bus_priv, + bus_hw_info); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Init TFE Out failed rc=%d", rc); + goto deinit_tfe_out; + } + } + + spin_lock_init(&bus_priv->common_data.spin_lock); + + tfe_bus_local->hw_ops.reserve = cam_tfe_bus_acquire_tfe_out; + tfe_bus_local->hw_ops.release = cam_tfe_bus_release_tfe_out; + tfe_bus_local->hw_ops.start = cam_tfe_bus_start_tfe_out; + tfe_bus_local->hw_ops.stop = cam_tfe_bus_stop_tfe_out; + tfe_bus_local->hw_ops.init = cam_tfe_bus_init_hw; + tfe_bus_local->hw_ops.deinit = cam_tfe_bus_deinit_hw; + tfe_bus_local->bottom_half_handler = cam_tfe_bus_bottom_half; + tfe_bus_local->hw_ops.process_cmd = cam_tfe_bus_process_cmd; + + *tfe_bus = tfe_bus_local; + + return rc; + +deinit_tfe_out: + if (i < 0) + i = CAM_TFE_BUS_TFE_OUT_MAX; + for (--i; i >= 0; i--) + cam_tfe_bus_deinit_tfe_out_resource(&bus_priv->tfe_out[i]); + +deinit_comp_grp: + if (i < 0) + i = CAM_TFE_BUS_COMP_GRP_MAX; + for (--i; i >= 0; i--) + cam_tfe_bus_deinit_comp_grp(&bus_priv->comp_grp[i]); + +deinit_wm: + if (i < 0) + i = bus_priv->num_client; + for (--i; i >= 0; i--) + cam_tfe_bus_deinit_wm_resource(&bus_priv->bus_client[i]); + + kfree(tfe_bus_local->bus_priv); + +free_bus_local: + kfree(tfe_bus_local); + +end: + return rc; +} + +int cam_tfe_bus_deinit( + struct cam_tfe_bus **tfe_bus) +{ + int i, rc = 0; + struct cam_tfe_bus_priv *bus_priv = NULL; + struct cam_tfe_bus *tfe_bus_local; + + if (!tfe_bus || !*tfe_bus) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + tfe_bus_local = *tfe_bus; + bus_priv = tfe_bus_local->bus_priv; + + if (!bus_priv) { + CAM_ERR(CAM_ISP, "bus_priv is NULL"); + rc = -ENODEV; + goto free_bus_local; + } + + for (i = 0; i < bus_priv->num_client; i++) { + rc = cam_tfe_bus_deinit_wm_resource( + &bus_priv->bus_client[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Deinit WM failed rc=%d", rc); + } + + for (i = 0; i < CAM_TFE_BUS_COMP_GRP_MAX; i++) { + rc = cam_tfe_bus_deinit_comp_grp(&bus_priv->comp_grp[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Deinit Comp Grp failed rc=%d", rc); + } + + for (i = 0; i < CAM_TFE_BUS_TFE_OUT_MAX; i++) { + rc = cam_tfe_bus_deinit_tfe_out_resource( + &bus_priv->tfe_out[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Deinit TFE Out failed rc=%d", rc); + } + + INIT_LIST_HEAD(&bus_priv->free_comp_grp); + INIT_LIST_HEAD(&bus_priv->used_comp_grp); + + mutex_destroy(&bus_priv->common_data.bus_mutex); + kfree(tfe_bus_local->bus_priv); + +free_bus_local: + kfree(tfe_bus_local); + + *tfe_bus = NULL; + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h new file mode 100644 index 0000000000000000000000000000000000000000..cc6703baf9e7626d08cfc0b977bf3b0f08490599 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + + +#ifndef _CAM_TFE_BUS_H_ +#define _CAM_TFE_BUS_H_ + +#include "cam_soc_util.h" +#include "cam_isp_hw.h" +#include "cam_tfe_hw_intf.h" + +#define CAM_TFE_BUS_MAX_CLIENTS 10 +#define CAM_TFE_BUS_MAX_SUB_GRPS 4 +#define CAM_TFE_BUS_MAX_PERF_CNT_REG 8 +#define CAM_TFE_BUS_MAX_IRQ_REGISTERS 2 +#define CAM_TFE_BUS_CLIENT_NAME_MAX_LENGTH 32 + +#define CAM_TFE_BUS_1_0 0x1000 + + +#define CAM_TFE_ADD_REG_VAL_PAIR(buf_array, index, offset, val) \ + do { \ + buf_array[(index)++] = offset; \ + buf_array[(index)++] = val; \ + } while (0) + +#define ALIGNUP(value, alignment) \ + ((value + alignment - 1) / alignment * alignment) + +typedef int (*CAM_BUS_HANDLER_BOTTOM_HALF)(void *bus_priv, + bool rup_process, struct cam_tfe_irq_evt_payload *evt_payload, + bool error_process); + +enum cam_tfe_bus_plane_type { + PLANE_Y, + PLANE_C, + PLANE_MAX, +}; + + +enum cam_tfe_bus_tfe_core_id { + CAM_TFE_BUS_TFE_CORE_0, + CAM_TFE_BUS_TFE_CORE_1, + CAM_TFE_BUS_TFE_CORE_2, + CAM_TFE_BUS_TFE_CORE_MAX, +}; + +enum cam_tfe_bus_comp_grp_id { + CAM_TFE_BUS_COMP_GRP_0, + CAM_TFE_BUS_COMP_GRP_1, + CAM_TFE_BUS_COMP_GRP_2, + CAM_TFE_BUS_COMP_GRP_3, + CAM_TFE_BUS_COMP_GRP_4, + CAM_TFE_BUS_COMP_GRP_5, + CAM_TFE_BUS_COMP_GRP_6, + CAM_TFE_BUS_COMP_GRP_7, + CAM_TFE_BUS_COMP_GRP_MAX, +}; + +enum cam_tfe_bus_rup_grp_id { + CAM_TFE_BUS_RUP_GRP_0, + CAM_TFE_BUS_RUP_GRP_1, + CAM_TFE_BUS_RUP_GRP_2, + CAM_TFE_BUS_RUP_GRP_3, + CAM_TFE_BUS_RUP_GRP_MAX, +}; + +enum cam_tfe_bus_tfe_out_id { + CAM_TFE_BUS_TFE_OUT_RDI0, + CAM_TFE_BUS_TFE_OUT_RDI1, + CAM_TFE_BUS_TFE_OUT_RDI2, + CAM_TFE_BUS_TFE_OUT_FULL, + CAM_TFE_BUS_TFE_OUT_RAW_DUMP, + CAM_TFE_BUS_TFE_OUT_PDAF, + CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE, + CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST, + CAM_TFE_BUS_TFE_OUT_STATS_TL_BG, + CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG, + CAM_TFE_BUS_TFE_OUT_STATS_BF, + CAM_TFE_BUS_TFE_OUT_MAX, +}; + +/* + * struct cam_tfe_bus_reg_offset_common: + * + * @Brief: Common registers across all BUS Clients + */ +struct cam_tfe_bus_reg_offset_common { + uint32_t hw_version; + uint32_t cgc_ovd; + uint32_t comp_cfg_0; + uint32_t comp_cfg_1; + uint32_t frameheader_cfg[4]; + uint32_t pwr_iso_cfg; + uint32_t overflow_status_clear; + uint32_t ccif_violation_status; + uint32_t overflow_status; + uint32_t image_size_violation_status; + uint32_t perf_count_cfg[CAM_TFE_BUS_MAX_PERF_CNT_REG]; + uint32_t perf_count_val[CAM_TFE_BUS_MAX_PERF_CNT_REG]; + uint32_t perf_count_status; + uint32_t debug_status_top_cfg; + uint32_t debug_status_top; + uint32_t test_bus_ctrl; + uint32_t irq_mask[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; + uint32_t irq_clear[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; + uint32_t irq_status[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; + uint32_t irq_cmd; + /* common register data */ + uint32_t cons_violation_shift; + uint32_t violation_shift; + uint32_t image_size_violation; +}; + +/* + * struct cam_tfe_bus_reg_offset_bus_client: + * + * @Brief: Register offsets for BUS Clients + */ +struct cam_tfe_bus_reg_offset_bus_client { + uint32_t cfg; + uint32_t image_addr; + uint32_t frame_incr; + uint32_t image_cfg_0; + uint32_t image_cfg_1; + uint32_t image_cfg_2; + uint32_t packer_cfg; + uint32_t bw_limit; + uint32_t frame_header_addr; + uint32_t frame_header_incr; + uint32_t frame_header_cfg; + uint32_t line_done_cfg; + uint32_t irq_subsample_period; + uint32_t irq_subsample_pattern; + uint32_t framedrop_period; + uint32_t framedrop_pattern; + uint32_t addr_status_0; + uint32_t addr_status_1; + uint32_t addr_status_2; + uint32_t addr_status_3; + uint32_t debug_status_cfg; + uint32_t debug_status_0; + uint32_t debug_status_1; + uint32_t comp_group; + /*bus data */ + uint8_t client_name[CAM_TFE_BUS_CLIENT_NAME_MAX_LENGTH]; +}; + +/* + * struct cam_tfe_bus_tfe_out_hw_info: + * + * @Brief: HW capability of TFE Bus Client + * tfe_out_id Tfe out port id + * max_width Max width supported by the outport + * max_height Max height supported by outport + * composite_group Out port composite group id + * rup_group_id Reg update group of outport id + */ +struct cam_tfe_bus_tfe_out_hw_info { + enum cam_tfe_bus_tfe_out_id tfe_out_id; + uint32_t max_width; + uint32_t max_height; + uint32_t composite_group; + uint32_t rup_group_id; +}; + +/* + * struct cam_tfe_bus_hw_info: + * + * @Brief: HW register info for entire Bus + * + * @common_reg: Common register details + * @num_client: Total number of write clients + * @bus_client_reg: Bus client register info + * @tfe_out_hw_info: TFE output capability + * @comp_done_shift: Mask shift for comp done mask + * @top_bus_wr_irq_shift: Mask shift for top level BUS WR irq + * @comp_buf_done_mask: Composite buf done bits mask + * @comp_rup_done_mask: Reg update done mask + * @bus_irq_error_mask: Bus irq error mask bits + */ +struct cam_tfe_bus_hw_info { + struct cam_tfe_bus_reg_offset_common common_reg; + uint32_t num_client; + struct cam_tfe_bus_reg_offset_bus_client + bus_client_reg[CAM_TFE_BUS_MAX_CLIENTS]; + uint32_t num_out; + struct cam_tfe_bus_tfe_out_hw_info + tfe_out_hw_info[CAM_TFE_BUS_TFE_OUT_MAX]; + uint32_t comp_done_shift; + uint32_t top_bus_wr_irq_shift; + uint32_t comp_buf_done_mask; + uint32_t comp_rup_done_mask; + uint32_t bus_irq_error_mask[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; +}; + +/* + * struct cam_tfe_bus: + * + * @Brief: Bus interface structure + * + * @bus_priv: Private data of bus + * @hw_ops: Hardware interface functions + * @bottom_half_handler: Bottom Half handler function + */ +struct cam_tfe_bus { + void *bus_priv; + struct cam_hw_ops hw_ops; + CAM_BUS_HANDLER_BOTTOM_HALF bottom_half_handler; +}; + +/* + * cam_tfe_bus_init() + * + * @Brief: Initialize Bus layer + * + * @soc_info: Soc Information for the associated HW + * @hw_intf: HW Interface of HW to which this resource belongs + * @bus_hw_info: BUS HW info that contains details of BUS registers + * @core_data: Core data pointer used for top irq config + * @tfe_bus: Pointer to tfe_bus structure which will be filled + * and returned on successful initialize + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_bus_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *bus_hw_info, + void *core_data, + struct cam_tfe_bus **tfe_bus); + +/* + * cam_tfe_bus_deinit() + * + * @Brief: Deinitialize Bus layer + * + * @tfe_bus: Pointer to tfe_bus structure to deinitialize + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_bus_deinit(struct cam_tfe_bus **tfe_bus); + +#endif /* _CAM_TFE_BUS_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c new file mode 100644 index 0000000000000000000000000000000000000000..5618d1ec6c23629fca57e3e9dbccb296b97e44b4 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -0,0 +1,2899 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "cam_cdm_util.h" +#include "cam_tasklet_util.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_tfe_soc.h" +#include "cam_tfe_core.h" +#include "cam_tfe_bus.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" +#include + +static const char drv_name[] = "tfe"; + +#define CAM_TFE_HW_RESET_HW_AND_REG_VAL 0x1 +#define CAM_TFE_HW_RESET_HW_VAL 0x10000 +#define CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES 3 +#define CAM_TFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX 2 +#define CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES 3 + +struct cam_tfe_top_common_data { + struct cam_hw_soc_info *soc_info; + struct cam_hw_intf *hw_intf; + struct cam_tfe_top_reg_offset_common *common_reg; + struct cam_tfe_reg_dump_data *reg_dump_data; +}; + +struct cam_tfe_top_priv { + struct cam_tfe_top_common_data common_data; + struct cam_isp_resource_node in_rsrc[CAM_TFE_TOP_IN_PORT_MAX]; + unsigned long hw_clk_rate; + struct cam_axi_vote applied_axi_vote; + struct cam_axi_vote req_axi_vote[CAM_TFE_TOP_IN_PORT_MAX]; + unsigned long req_clk_rate[CAM_TFE_TOP_IN_PORT_MAX]; + struct cam_axi_vote last_vote[CAM_TFE_TOP_IN_PORT_MAX * + CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES]; + uint32_t last_counter; + uint64_t total_bw_applied; + enum cam_tfe_bw_control_action + axi_vote_control[CAM_TFE_TOP_IN_PORT_MAX]; + uint32_t irq_prepared_mask[3]; + void *tasklet_info; + struct timeval sof_ts; + struct timeval epoch_ts; + struct timeval eof_ts; + struct timeval error_ts; +}; + +struct cam_tfe_camif_data { + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + struct cam_tfe_top_reg_offset_common *common_reg; + struct cam_tfe_camif_reg *camif_reg; + struct cam_tfe_camif_reg_data *reg_data; + struct cam_hw_soc_info *soc_info; + + + cam_hw_mgr_event_cb_func event_cb; + void *priv; + enum cam_isp_hw_sync_mode sync_mode; + uint32_t dsp_mode; + uint32_t pix_pattern; + uint32_t left_first_pixel; + uint32_t left_last_pixel; + uint32_t right_first_pixel; + uint32_t right_last_pixel; + uint32_t first_line; + uint32_t last_line; + bool enable_sof_irq_debug; + uint32_t irq_debug_cnt; + uint32_t camif_debug; + uint32_t camif_pd_enable; + uint32_t dual_tfe_sync_sel; +}; + +struct cam_tfe_rdi_data { + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + struct cam_tfe_top_reg_offset_common *common_reg; + struct cam_tfe_rdi_reg *rdi_reg; + struct cam_tfe_rdi_reg_data *reg_data; + cam_hw_mgr_event_cb_func event_cb; + void *priv; + enum cam_isp_hw_sync_mode sync_mode; + uint32_t pix_pattern; + uint32_t left_first_pixel; + uint32_t left_last_pixel; + uint32_t first_line; + uint32_t last_line; +}; + +static int cam_tfe_validate_pix_pattern(uint32_t pattern) +{ + int rc; + + switch (pattern) { + case CAM_ISP_TFE_PATTERN_BAYER_RGRGRG: + case CAM_ISP_TFE_PATTERN_BAYER_GRGRGR: + case CAM_ISP_TFE_PATTERN_BAYER_BGBGBG: + case CAM_ISP_TFE_PATTERN_BAYER_GBGBGB: + case CAM_ISP_TFE_PATTERN_YUV_YCBYCR: + case CAM_ISP_TFE_PATTERN_YUV_YCRYCB: + case CAM_ISP_TFE_PATTERN_YUV_CBYCRY: + case CAM_ISP_TFE_PATTERN_YUV_CRYCBY: + rc = 0; + break; + default: + CAM_ERR(CAM_ISP, "Error Invalid pix pattern:%d", pattern); + rc = -EINVAL; + break; + } + return rc; +} + +static int cam_tfe_get_evt_payload(struct cam_tfe_hw_core_info *core_info, + struct cam_tfe_irq_evt_payload **evt_payload) +{ + spin_lock(&core_info->spin_lock); + if (list_empty(&core_info->free_payload_list)) { + *evt_payload = NULL; + spin_unlock(&core_info->spin_lock); + CAM_ERR_RATE_LIMIT(CAM_ISP, "No free payload, core id 0x%x", + core_info->core_index); + return -ENODEV; + } + + *evt_payload = list_first_entry(&core_info->free_payload_list, + struct cam_tfe_irq_evt_payload, list); + list_del_init(&(*evt_payload)->list); + spin_unlock(&core_info->spin_lock); + + return 0; +} + +int cam_tfe_put_evt_payload(void *core_info, + struct cam_tfe_irq_evt_payload **evt_payload) +{ + struct cam_tfe_hw_core_info *tfe_core_info = core_info; + unsigned long flags; + + if (!core_info) { + CAM_ERR(CAM_ISP, "Invalid param core_info NULL"); + return -EINVAL; + } + if (*evt_payload == NULL) { + CAM_ERR(CAM_ISP, "No payload to put"); + return -EINVAL; + } + + spin_lock_irqsave(&tfe_core_info->spin_lock, flags); + (*evt_payload)->error_type = 0; + list_add_tail(&(*evt_payload)->list, &tfe_core_info->free_payload_list); + *evt_payload = NULL; + spin_unlock_irqrestore(&tfe_core_info->spin_lock, flags); + + return 0; +} + +int cam_tfe_get_hw_caps(void *hw_priv, void *get_hw_cap_args, + uint32_t arg_size) +{ + return -EPERM; +} + +void cam_tfe_get_timestamp(struct cam_isp_timestamp *time_stamp) +{ + struct timespec ts; + + get_monotonic_boottime(&ts); + time_stamp->mono_time.tv_sec = ts.tv_sec; + time_stamp->mono_time.tv_usec = ts.tv_nsec/1000; +} + +int cam_tfe_irq_config(void *tfe_core_data, + uint32_t *irq_mask, uint32_t num_reg, bool enable) +{ + struct cam_tfe_hw_core_info *core_info; + struct cam_tfe_top_priv *top_priv; + struct cam_hw_soc_info *soc_info; + void __iomem *mem_base; + bool need_lock; + unsigned long flags = 0; + uint32_t i, val; + + if (!tfe_core_data) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Invalid core data"); + return -EINVAL; + } + + core_info = (struct cam_tfe_hw_core_info *)tfe_core_data; + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + soc_info = (struct cam_hw_soc_info *)top_priv->common_data.soc_info; + mem_base = soc_info->reg_map[TFE_CORE_BASE_IDX].mem_base; + + need_lock = !in_irq(); + if (need_lock) + spin_lock_irqsave(&core_info->spin_lock, flags); + + for (i = 0; i < num_reg; i++) { + val = cam_io_r_mb(mem_base + + core_info->tfe_hw_info->top_irq_mask[i]); + if (enable) + val |= irq_mask[i]; + else + val &= ~irq_mask[i]; + cam_io_w_mb(val, mem_base + + core_info->tfe_hw_info->top_irq_mask[i]); + } + if (need_lock) + spin_unlock_irqrestore(&core_info->spin_lock, flags); + + return 0; +} + +static void cam_tfe_log_tfe_in_debug_status( + struct cam_tfe_top_priv *top_priv) +{ + void __iomem *mem_base; + struct cam_tfe_camif_data *camif_data; + struct cam_tfe_rdi_data *rdi_data; + uint32_t i, val_0, val_1; + + mem_base = top_priv->common_data.soc_info->reg_map[0].mem_base; + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if ((top_priv->in_rsrc[i].res_state != + CAM_ISP_RESOURCE_STATE_STREAMING)) + continue; + + if (top_priv->in_rsrc[i].res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + camif_data = (struct cam_tfe_camif_data *) + top_priv->in_rsrc[i].res_priv; + val_0 = cam_io_r(mem_base + + camif_data->camif_reg->debug_0); + val_1 = cam_io_r(mem_base + + camif_data->camif_reg->debug_1); + CAM_INFO(CAM_ISP, + "camif debug1:0x%x Height:0x%x, width:0x%x", + val_1, + ((val_0 >> 16) & 0x1FFF), + (val_0 & 0x1FFF)); + CAM_INFO(CAM_ISP, + "Acquired sync mode:%d left start pxl:0x%x end_pixel:0x%x", + camif_data->sync_mode, + camif_data->left_first_pixel, + camif_data->left_last_pixel); + + if (camif_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) + CAM_INFO(CAM_ISP, + "sync mode:%d right start pxl:0x%x end_pixel:0x%x", + camif_data->sync_mode, + camif_data->right_first_pixel, + camif_data->right_last_pixel); + + CAM_INFO(CAM_ISP, + "Acquired line start:0x%x line end:0x%x", + camif_data->first_line, + camif_data->last_line); + } else if ((top_priv->in_rsrc[i].res_id >= + CAM_ISP_HW_TFE_IN_RDI0) || + (top_priv->in_rsrc[i].res_id <= + CAM_ISP_HW_TFE_IN_RDI2)) { + rdi_data = (struct cam_tfe_rdi_data *) + top_priv->in_rsrc[i].res_priv; + val_0 = cam_io_r(mem_base + + rdi_data->rdi_reg->rdi_debug_0); + val_1 = cam_io_r(mem_base + + rdi_data->rdi_reg->rdi_debug_1); + CAM_INFO(CAM_ISP, + "RDI res id:%d debug1:0x%x Height:0x%x, width:0x%x", + top_priv->in_rsrc[i].res_id, + val_1, ((val_0 >> 16) & 0x1FFF), + (val_0 & 0x1FFF)); + CAM_INFO(CAM_ISP, + "sync mode:%d left start pxl:0x%x end_pixel:0x%x", + rdi_data->sync_mode, + rdi_data->left_first_pixel, + rdi_data->left_last_pixel); + CAM_INFO(CAM_ISP, + "sync mode:%d line start:0x%x line end:0x%x", + rdi_data->sync_mode, + rdi_data->first_line, + rdi_data->last_line); + } + } +} +static void cam_tfe_log_error_irq_status( + struct cam_tfe_hw_core_info *core_info, + struct cam_tfe_top_priv *top_priv, + struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_hw_info *hw_info; + void __iomem *mem_base; + struct cam_hw_soc_info *soc_info; + struct cam_tfe_soc_private *soc_private; + + struct cam_tfe_clc_hw_status *clc_hw_status; + struct timespec64 ts; + uint32_t i, val_0, val_1, val_2, val_3; + + + ktime_get_boottime_ts64(&ts); + hw_info = core_info->tfe_hw_info; + mem_base = top_priv->common_data.soc_info->reg_map[0].mem_base; + soc_info = top_priv->common_data.soc_info; + soc_private = top_priv->common_data.soc_info->soc_private; + + CAM_INFO(CAM_ISP, "current monotonic time stamp seconds %lld:%lld", + ts.tv_sec, ts.tv_nsec/1000); + CAM_INFO(CAM_ISP, + "ERROR time %lld:%lld SOF %lld:%lld EPOCH %lld:%lld EOF %lld:%lld", + top_priv->error_ts.tv_sec, + top_priv->error_ts.tv_usec, + top_priv->sof_ts.tv_sec, + top_priv->sof_ts.tv_usec, + top_priv->epoch_ts.tv_sec, + top_priv->epoch_ts.tv_usec, + top_priv->eof_ts.tv_sec, + top_priv->eof_ts.tv_usec); + + val_0 = cam_io_r(mem_base + + top_priv->common_data.common_reg->debug_0); + val_1 = cam_io_r(mem_base + + top_priv->common_data.common_reg->debug_1); + val_2 = cam_io_r(mem_base + + top_priv->common_data.common_reg->debug_2); + val_3 = cam_io_r(mem_base + + top_priv->common_data.common_reg->debug_3); + + CAM_INFO(CAM_ISP, "TOP IRQ[0]:0x%x IRQ[1]:0x%x IRQ[2]:0x%x", + evt_payload->irq_reg_val[0], evt_payload->irq_reg_val[1], + evt_payload->irq_reg_val[2]); + + CAM_INFO(CAM_ISP, "Top debug [0]:0x%x [1]:0x%x [2]:0x%x [3]:0x%x", + val_0, val_1, val_2, val_3); + + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x20, true, &val_0); + CAM_INFO(CAM_ISP, "tfe_niu_MaxWr_Low offset 0x20 val 0x%x", + val_0); + + val_0 = cam_io_r(mem_base + + top_priv->common_data.common_reg->perf_pixel_count); + + val_1 = cam_io_r(mem_base + + top_priv->common_data.common_reg->perf_line_count); + + val_2 = cam_io_r(mem_base + + top_priv->common_data.common_reg->perf_stall_count); + + val_3 = cam_io_r(mem_base + + top_priv->common_data.common_reg->perf_always_count); + + CAM_INFO(CAM_ISP, + "Top perf cnt pix:0x%x line:0x%x stall:0x%x always:0x%x", + val_0, val_1, val_2, val_3); + + clc_hw_status = hw_info->clc_hw_status_info; + for (i = 0; i < hw_info->num_clc; i++) { + val_0 = cam_io_r(mem_base + + clc_hw_status[i].hw_status_reg); + if (val_0) + CAM_INFO(CAM_ISP, + "CLC HW status :name:%s offset:0x%x value:0x%x", + clc_hw_status[i].name, + clc_hw_status[i].hw_status_reg, + val_0); + } + + cam_tfe_log_tfe_in_debug_status(top_priv); + + /* Check the overflow errors */ + if (evt_payload->irq_reg_val[0] & hw_info->error_irq_mask[0]) { + if (evt_payload->irq_reg_val[0] & BIT(8)) + CAM_INFO(CAM_ISP, "PP_FRAME_DROP"); + + if (evt_payload->irq_reg_val[0] & BIT(9)) + CAM_INFO(CAM_ISP, "RDI0_FRAME_DROP"); + + if (evt_payload->irq_reg_val[0] & BIT(10)) + CAM_INFO(CAM_ISP, "RDI1_FRAME_DROP"); + + if (evt_payload->irq_reg_val[0] & BIT(11)) + CAM_INFO(CAM_ISP, "RDI2_FRAME_DROP"); + + if (evt_payload->irq_reg_val[0] & BIT(16)) + CAM_INFO(CAM_ISP, "PP_OVERFLOW"); + + if (evt_payload->irq_reg_val[0] & BIT(17)) + CAM_INFO(CAM_ISP, "RDI0_OVERFLOW"); + + if (evt_payload->irq_reg_val[0] & BIT(18)) + CAM_INFO(CAM_ISP, "RDI1_OVERFLOW"); + + if (evt_payload->irq_reg_val[0] & BIT(19)) + CAM_INFO(CAM_ISP, "RDI2_OVERFLOW"); + } + + /* Check the violation errors */ + if (evt_payload->irq_reg_val[2] & hw_info->error_irq_mask[2]) { + if (evt_payload->irq_reg_val[2] & BIT(0)) + CAM_INFO(CAM_ISP, "PP_CAMIF_VIOLATION"); + + if (evt_payload->irq_reg_val[2] & BIT(1)) + CAM_INFO(CAM_ISP, "PP_VIOLATION"); + + if (evt_payload->irq_reg_val[2] & BIT(2)) + CAM_INFO(CAM_ISP, "RDI0_CAMIF_VIOLATION"); + + if (evt_payload->irq_reg_val[2] & BIT(3)) + CAM_INFO(CAM_ISP, "RDI1_CAMIF_VIOLATION"); + + if (evt_payload->irq_reg_val[2] & BIT(4)) + CAM_INFO(CAM_ISP, "RDI2_CAMIF_VIOLATION"); + + if (evt_payload->irq_reg_val[2] & BIT(5)) + CAM_INFO(CAM_ISP, "DIAG_VIOLATION"); + + val_0 = cam_io_r(mem_base + + top_priv->common_data.common_reg->violation_status); + CAM_INFO(CAM_ISP, "TOP Violation status:0x%x", val_0); + } + + core_info->tfe_bus->bottom_half_handler( + core_info->tfe_bus->bus_priv, false, evt_payload, true); + + CAM_INFO(CAM_ISP, + "TFE clock rate:%d TFE total bw applied:%lld", + top_priv->hw_clk_rate, + top_priv->total_bw_applied); + cam_cpas_log_votes(); +} + +static int cam_tfe_error_irq_bottom_half( + struct cam_tfe_hw_core_info *core_info, + struct cam_tfe_top_priv *top_priv, + struct cam_tfe_irq_evt_payload *evt_payload, + cam_hw_mgr_event_cb_func event_cb, + void *event_cb_priv) +{ + struct cam_isp_hw_event_info evt_info; + struct cam_tfe_hw_info *hw_info; + uint32_t error_detected = 0; + + hw_info = core_info->tfe_hw_info; + evt_info.hw_idx = core_info->core_index; + evt_info.res_type = CAM_ISP_RESOURCE_TFE_IN; + + if (evt_payload->irq_reg_val[0] & hw_info->error_irq_mask[0]) { + evt_info.err_type = CAM_TFE_IRQ_STATUS_OVERFLOW; + error_detected = 1; + } + + if ((evt_payload->bus_irq_val[0] & hw_info->bus_error_irq_mask[0]) || + (evt_payload->irq_reg_val[2] & hw_info->error_irq_mask[2])) { + evt_info.err_type = CAM_TFE_IRQ_STATUS_VIOLATION; + error_detected = 1; + } + + if (error_detected) { + evt_info.err_type = CAM_TFE_IRQ_STATUS_OVERFLOW; + top_priv->error_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->error_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; + + cam_tfe_log_error_irq_status(core_info, top_priv, evt_payload); + if (event_cb) + event_cb(event_cb_priv, + CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info); + else + CAM_ERR(CAM_ISP, "TFE:%d invalid eventcb:", + core_info->core_index); + } + + return 0; +} + +static int cam_tfe_rdi_irq_bottom_half( + struct cam_tfe_top_priv *top_priv, + struct cam_isp_resource_node *rdi_node, + bool epoch_process, + struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_rdi_data *rdi_priv; + struct cam_isp_hw_event_info evt_info; + struct cam_hw_info *hw_info; + + rdi_priv = (struct cam_tfe_rdi_data *)rdi_node->res_priv; + hw_info = rdi_node->hw_intf->hw_priv; + + evt_info.hw_idx = rdi_node->hw_intf->hw_idx; + evt_info.res_id = rdi_node->res_id; + evt_info.res_type = rdi_node->res_type; + + if ((!epoch_process) && (evt_payload->irq_reg_val[1] & + rdi_priv->reg_data->eof_irq_mask)) { + CAM_DBG(CAM_ISP, "Received EOF"); + top_priv->eof_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->eof_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; + + if (rdi_priv->event_cb) + rdi_priv->event_cb(rdi_priv->priv, + CAM_ISP_HW_EVENT_EOF, (void *)&evt_info); + } + + if ((!epoch_process) && (evt_payload->irq_reg_val[1] & + rdi_priv->reg_data->sof_irq_mask)) { + CAM_DBG(CAM_ISP, "Received SOF"); + top_priv->sof_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->sof_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; + + if (rdi_priv->event_cb) + rdi_priv->event_cb(rdi_priv->priv, + CAM_ISP_HW_EVENT_SOF, (void *)&evt_info); + } + + if (epoch_process && (evt_payload->irq_reg_val[1] & + rdi_priv->reg_data->epoch0_irq_mask)) { + CAM_DBG(CAM_ISP, "Received EPOCH0"); + top_priv->epoch_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->epoch_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; + + if (rdi_priv->event_cb) + rdi_priv->event_cb(rdi_priv->priv, + CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info); + } + + return 0; +} + +static int cam_tfe_camif_irq_bottom_half( + struct cam_tfe_top_priv *top_priv, + struct cam_isp_resource_node *camif_node, + bool epoch_process, + struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_camif_data *camif_priv; + struct cam_isp_hw_event_info evt_info; + struct cam_hw_info *hw_info; + uint32_t val; + + camif_priv = camif_node->res_priv; + hw_info = camif_node->hw_intf->hw_priv; + evt_info.hw_idx = camif_node->hw_intf->hw_idx; + evt_info.res_id = camif_node->res_id; + evt_info.res_type = camif_node->res_type; + + if ((!epoch_process) && (evt_payload->irq_reg_val[1] & + camif_priv->reg_data->eof_irq_mask)) { + CAM_DBG(CAM_ISP, "Received EOF"); + + top_priv->eof_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->eof_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_EOF, (void *)&evt_info); + } + + if ((!epoch_process) && (evt_payload->irq_reg_val[1] & + camif_priv->reg_data->sof_irq_mask)) { + if ((camif_priv->enable_sof_irq_debug) && + (camif_priv->irq_debug_cnt <= + CAM_TFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "Received SOF"); + + camif_priv->irq_debug_cnt++; + if (camif_priv->irq_debug_cnt == + CAM_TFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX) { + camif_priv->enable_sof_irq_debug = + false; + camif_priv->irq_debug_cnt = 0; + } + } else + CAM_DBG(CAM_ISP, "Received SOF"); + + top_priv->sof_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->sof_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_SOF, (void *)&evt_info); + } + + if (epoch_process && (evt_payload->irq_reg_val[1] & + camif_priv->reg_data->epoch0_irq_mask)) { + CAM_DBG(CAM_ISP, "Received EPOCH"); + + top_priv->epoch_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->epoch_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info); + } + + if (camif_priv->camif_debug & CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS) { + val = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->diag_sensor_status_0); + CAM_DBG(CAM_ISP, "TFE_DIAG_SENSOR_STATUS: 0x%x", + camif_priv->mem_base, val); + } + + return 0; +} + +static int cam_tfe_irq_bottom_half(void *handler_priv, + void *evt_payload_priv) +{ + struct cam_tfe_hw_core_info *core_info; + struct cam_tfe_top_priv *top_priv; + struct cam_tfe_irq_evt_payload *evt_payload; + struct cam_tfe_camif_data *camif_priv; + struct cam_tfe_rdi_data *rdi_priv; + cam_hw_mgr_event_cb_func event_cb = NULL; + void *event_cb_priv = NULL; + uint32_t i; + + if (!handler_priv || !evt_payload_priv) { + CAM_ERR(CAM_ISP, + "Invalid params handle_priv:%pK, evt_payload_priv:%pK", + handler_priv, evt_payload_priv); + return 0; + } + + core_info = (struct cam_tfe_hw_core_info *)handler_priv; + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + evt_payload = evt_payload_priv; + + /* process sof and eof */ + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if ((top_priv->in_rsrc[i].res_id == + CAM_ISP_HW_TFE_IN_CAMIF) && + (top_priv->in_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_STREAMING)) { + camif_priv = (struct cam_tfe_camif_data *) + top_priv->in_rsrc[i].res_priv; + event_cb = camif_priv->event_cb; + event_cb_priv = camif_priv->priv; + + if (camif_priv->reg_data->subscribe_irq_mask[1] & + evt_payload->irq_reg_val[1]) + cam_tfe_camif_irq_bottom_half(top_priv, + &top_priv->in_rsrc[i], false, + evt_payload); + + } else if ((top_priv->in_rsrc[i].res_id >= + CAM_ISP_HW_TFE_IN_RDI0) && + (top_priv->in_rsrc[i].res_id <= + CAM_ISP_HW_TFE_IN_RDI2) && + (top_priv->in_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_STREAMING) && + top_priv->in_rsrc[i].rdi_only_ctx) { + rdi_priv = (struct cam_tfe_rdi_data *) + top_priv->in_rsrc[i].res_priv; + event_cb = rdi_priv->event_cb; + event_cb_priv = rdi_priv->priv; + + if (rdi_priv->reg_data->subscribe_irq_mask[1] & + evt_payload->irq_reg_val[1]) + cam_tfe_rdi_irq_bottom_half(top_priv, + &top_priv->in_rsrc[i], false, + evt_payload); + } + } + + /* process the irq errors */ + cam_tfe_error_irq_bottom_half(core_info, top_priv, evt_payload, + event_cb, event_cb_priv); + + /* process the reg update in the bus */ + if (evt_payload->irq_reg_val[0] & + core_info->tfe_hw_info->bus_reg_irq_mask[0]) { + core_info->tfe_bus->bottom_half_handler( + core_info->tfe_bus->bus_priv, true, evt_payload, false); + } + + /* process the epoch */ + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if ((top_priv->in_rsrc[i].res_id == + CAM_ISP_HW_TFE_IN_CAMIF) && + (top_priv->in_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_STREAMING)) { + camif_priv = (struct cam_tfe_camif_data *) + top_priv->in_rsrc[i].res_priv; + if (camif_priv->reg_data->subscribe_irq_mask[1] & + evt_payload->irq_reg_val[1]) + cam_tfe_camif_irq_bottom_half(top_priv, + &top_priv->in_rsrc[i], true, + evt_payload); + } else if ((top_priv->in_rsrc[i].res_id >= + CAM_ISP_HW_TFE_IN_RDI0) && + (top_priv->in_rsrc[i].res_id <= + CAM_ISP_HW_TFE_IN_RDI2) && + (top_priv->in_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_STREAMING)) { + rdi_priv = (struct cam_tfe_rdi_data *) + top_priv->in_rsrc[i].res_priv; + if (rdi_priv->reg_data->subscribe_irq_mask[1] & + evt_payload->irq_reg_val[1]) + cam_tfe_rdi_irq_bottom_half(top_priv, + &top_priv->in_rsrc[i], true, + evt_payload); + } + } + + /* process the bufone */ + if (evt_payload->irq_reg_val[0] & + core_info->tfe_hw_info->bus_reg_irq_mask[0]) { + core_info->tfe_bus->bottom_half_handler( + core_info->tfe_bus->bus_priv, false, evt_payload, + false); + } + + cam_tfe_put_evt_payload(core_info, &evt_payload); + + return 0; +} + +static int cam_tfe_irq_err_top_half( + struct cam_tfe_hw_core_info *core_info, + void __iomem *mem_base, + uint32_t *top_irq_status, + uint32_t *bus_irq_status) +{ + uint32_t i; + + if ((top_irq_status[0] & core_info->tfe_hw_info->error_irq_mask[0]) || + (top_irq_status[2] & + core_info->tfe_hw_info->error_irq_mask[2]) || + (bus_irq_status[0] & + core_info->tfe_hw_info->bus_error_irq_mask[0])) { + CAM_ERR(CAM_ISP, + "Encountered Error: tfe:%d: Irq_status0=0x%x status2=0x%x", + core_info->core_index, top_irq_status[0], + top_irq_status[2]); + CAM_ERR(CAM_ISP, + "Encountered Error: tfe:%d:BUS Irq_status0=0x%x", + core_info->core_index, bus_irq_status[0]); + + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + cam_io_w(0, mem_base + + core_info->tfe_hw_info->top_irq_mask[i]); + + cam_io_w_mb(core_info->tfe_hw_info->global_clear_bitmask, + mem_base + core_info->tfe_hw_info->top_irq_cmd); + } + + return 0; +} + +irqreturn_t cam_tfe_irq(int irq_num, void *data) +{ + struct cam_hw_info *tfe_hw; + struct cam_tfe_hw_core_info *core_info; + struct cam_tfe_top_priv *top_priv; + void __iomem *mem_base; + struct cam_tfe_irq_evt_payload *evt_payload; + uint32_t top_irq_status[CAM_TFE_TOP_IRQ_REG_NUM] = {0}; + uint32_t bus_irq_status[CAM_TFE_BUS_MAX_IRQ_REGISTERS] = {0}; + uint32_t i, ccif_violation = 0, overflow_status = 0; + uint32_t image_sz_violation = 0; + void *bh_cmd = NULL; + int rc = -EINVAL; + + if (!data) + return IRQ_NONE; + + tfe_hw = (struct cam_hw_info *)data; + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + mem_base = top_priv->common_data.soc_info->reg_map[0].mem_base; + + if (tfe_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_ERR(CAM_ISP, "TFE:%d hw is not powered up", + core_info->core_index); + return IRQ_HANDLED; + } + + spin_lock(&core_info->spin_lock); + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + top_irq_status[i] = cam_io_r(mem_base + + core_info->tfe_hw_info->top_irq_status[i]); + + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + cam_io_w(top_irq_status[i], mem_base + + core_info->tfe_hw_info->top_irq_clear[i]); + + cam_io_w_mb(core_info->tfe_hw_info->global_clear_bitmask, + mem_base + core_info->tfe_hw_info->top_irq_cmd); + + CAM_DBG(CAM_ISP, "TFE:%d IRQ status_0:0x%x status_1:0x%x status_2:0x%x", + core_info->core_index, top_irq_status[0], + top_irq_status[1], top_irq_status[2]); + + if (top_irq_status[0] & core_info->tfe_hw_info->bus_reg_irq_mask[0]) { + for (i = 0; i < CAM_TFE_BUS_MAX_IRQ_REGISTERS; i++) + bus_irq_status[i] = cam_io_r(mem_base + + core_info->tfe_hw_info->bus_irq_status[i]); + + for (i = 0; i < CAM_TFE_BUS_MAX_IRQ_REGISTERS; i++) + cam_io_w(bus_irq_status[i], mem_base + + core_info->tfe_hw_info->bus_irq_clear[i]); + + ccif_violation = cam_io_r(mem_base + + core_info->tfe_hw_info->bus_violation_reg); + overflow_status = cam_io_r(mem_base + + core_info->tfe_hw_info->bus_overflow_reg); + image_sz_violation = cam_io_r(mem_base + + core_info->tfe_hw_info->bus_image_size_vilation_reg); + + cam_io_w(core_info->tfe_hw_info->global_clear_bitmask, + mem_base + core_info->tfe_hw_info->bus_irq_cmd); + + CAM_DBG(CAM_ISP, "TFE:%d BUS IRQ status_0:0x%x status_1:0x%x", + core_info->core_index, bus_irq_status[0], + bus_irq_status[1]); + } + spin_unlock(&core_info->spin_lock); + + /* check reset */ + if ((top_irq_status[0] & core_info->tfe_hw_info->reset_irq_mask[0]) || + (top_irq_status[1] & + core_info->tfe_hw_info->reset_irq_mask[1]) || + (top_irq_status[2] & + core_info->tfe_hw_info->reset_irq_mask[2])) { + /* Reset ack */ + complete(&core_info->reset_complete); + return IRQ_HANDLED; + } + + /* Check the irq errors */ + cam_tfe_irq_err_top_half(core_info, mem_base, top_irq_status, + bus_irq_status); + + rc = cam_tfe_get_evt_payload(core_info, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "No tasklet_cmd is free in queue"); + CAM_ERR_RATE_LIMIT(CAM_ISP, "IRQ status0=0x%x status2=0x%x", + top_irq_status[0], top_irq_status[1]); + goto end; + } + + cam_tfe_get_timestamp(&evt_payload->ts); + + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + evt_payload->irq_reg_val[i] = top_irq_status[i]; + + for (i = 0; i < CAM_TFE_BUS_MAX_IRQ_REGISTERS; i++) + evt_payload->bus_irq_val[i] = bus_irq_status[i]; + + evt_payload->ccif_violation_status = ccif_violation; + evt_payload->overflow_status = overflow_status; + evt_payload->image_size_violation_status = image_sz_violation; + + evt_payload->core_index = core_info->core_index; + evt_payload->core_info = core_info; + + rc = tasklet_bh_api.get_bh_payload_func( + top_priv->tasklet_info, &bh_cmd); + if (rc || !bh_cmd) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "No payload, IRQ handling frozen"); + cam_tfe_put_evt_payload(core_info, &evt_payload); + goto end; + } + + tasklet_bh_api.bottom_half_enqueue_func( + top_priv->tasklet_info, + bh_cmd, + core_info, + evt_payload, + cam_tfe_irq_bottom_half); + +end: + return IRQ_HANDLED; + +} + +static int cam_tfe_top_set_hw_clk_rate( + struct cam_tfe_top_priv *top_priv) +{ + struct cam_hw_soc_info *soc_info = NULL; + int i, rc = 0; + unsigned long max_clk_rate = 0; + + soc_info = top_priv->common_data.soc_info; + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if (top_priv->req_clk_rate[i] > max_clk_rate) + max_clk_rate = top_priv->req_clk_rate[i]; + } + if (max_clk_rate == top_priv->hw_clk_rate) + return 0; + + CAM_DBG(CAM_ISP, "TFE:%d Clock name=%s idx=%d clk=%llu", + top_priv->common_data.soc_info->index, + soc_info->clk_name[soc_info->src_clk_idx], + soc_info->src_clk_idx, max_clk_rate); + + rc = cam_soc_util_set_src_clk_rate(soc_info, max_clk_rate); + + if (!rc) + top_priv->hw_clk_rate = max_clk_rate; + else + CAM_ERR(CAM_ISP, "TFE:%d set src clock rate:%lld failed, rc=%d", + top_priv->common_data.soc_info->index, max_clk_rate, rc); + + return rc; +} + +static struct cam_axi_vote *cam_tfe_top_delay_bw_reduction( + struct cam_tfe_top_priv *top_priv, + uint64_t *to_be_applied_bw) +{ + uint32_t i, j; + int vote_idx = -1; + uint64_t max_bw = 0; + uint64_t total_bw; + struct cam_axi_vote *curr_l_vote; + + for (i = 0; i < (CAM_TFE_TOP_IN_PORT_MAX * + CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES); i++) { + total_bw = 0; + curr_l_vote = &top_priv->last_vote[i]; + for (j = 0; j < curr_l_vote->num_paths; j++) { + if (total_bw > + (U64_MAX - + curr_l_vote->axi_path[j].camnoc_bw)) { + CAM_ERR(CAM_ISP, "Overflow at idx: %d", j); + return NULL; + } + + total_bw += curr_l_vote->axi_path[j].camnoc_bw; + } + + if (total_bw > max_bw) { + vote_idx = i; + max_bw = total_bw; + } + } + + if (vote_idx < 0) + return NULL; + + *to_be_applied_bw = max_bw; + + return &top_priv->last_vote[vote_idx]; +} + +static int cam_tfe_top_set_axi_bw_vote( + struct cam_tfe_top_priv *top_priv, + bool start_stop) +{ + struct cam_axi_vote *agg_vote = NULL; + struct cam_axi_vote *to_be_applied_axi_vote = NULL; + struct cam_hw_soc_info *soc_info = top_priv->common_data.soc_info; + struct cam_tfe_soc_private *soc_private = soc_info->soc_private; + int rc = 0; + uint32_t i; + uint32_t num_paths = 0; + uint64_t total_bw_new_vote = 0; + bool bw_unchanged = true; + bool apply_bw_update = false; + + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error soc_private NULL"); + return -EINVAL; + } + + agg_vote = kzalloc(sizeof(struct cam_axi_vote), GFP_KERNEL); + if (!agg_vote) { + CAM_ERR(CAM_ISP, "Out of memory"); + return -ENOMEM; + } + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if (top_priv->axi_vote_control[i] == + CAM_TFE_BW_CONTROL_INCLUDE) { + if (num_paths + + top_priv->req_axi_vote[i].num_paths > + CAM_CPAS_MAX_PATHS_PER_CLIENT) { + CAM_ERR(CAM_ISP, + "Required paths(%d) more than max(%d)", + num_paths + + top_priv->req_axi_vote[i].num_paths, + CAM_CPAS_MAX_PATHS_PER_CLIENT); + rc = -EINVAL; + goto free_mem; + } + + memcpy(&agg_vote->axi_path[num_paths], + &top_priv->req_axi_vote[i].axi_path[0], + top_priv->req_axi_vote[i].num_paths * + sizeof( + struct cam_axi_per_path_bw_vote)); + num_paths += top_priv->req_axi_vote[i].num_paths; + } + } + + agg_vote->num_paths = num_paths; + + for (i = 0; i < agg_vote->num_paths; i++) { + CAM_DBG(CAM_PERF, + "tfe[%d] : New BW Vote : counter[%d] [%s][%s] [%llu %llu %llu]", + top_priv->common_data.hw_intf->hw_idx, + top_priv->last_counter, + cam_cpas_axi_util_path_type_to_string( + agg_vote->axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + agg_vote->axi_path[i].transac_type), + agg_vote->axi_path[i].camnoc_bw, + agg_vote->axi_path[i].mnoc_ab_bw, + agg_vote->axi_path[i].mnoc_ib_bw); + + total_bw_new_vote += agg_vote->axi_path[i].camnoc_bw; + } + + memcpy(&top_priv->last_vote[top_priv->last_counter], agg_vote, + sizeof(struct cam_axi_vote)); + top_priv->last_counter = (top_priv->last_counter + 1) % + (CAM_TFE_TOP_IN_PORT_MAX * + CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES); + + if ((agg_vote->num_paths != top_priv->applied_axi_vote.num_paths) || + (total_bw_new_vote != top_priv->total_bw_applied)) + bw_unchanged = false; + + CAM_DBG(CAM_PERF, + "tfe[%d] : applied_total=%lld, new_total=%lld unchanged=%d, start_stop=%d", + top_priv->common_data.hw_intf->hw_idx, + top_priv->total_bw_applied, total_bw_new_vote, + bw_unchanged, start_stop); + + if (bw_unchanged) { + CAM_DBG(CAM_ISP, "BW config unchanged"); + rc = 0; + goto free_mem; + } + + if (start_stop) { + /* need to vote current request immediately */ + to_be_applied_axi_vote = agg_vote; + /* Reset everything, we can start afresh */ + memset(top_priv->last_vote, 0x0, sizeof(struct cam_axi_vote) * + (CAM_TFE_TOP_IN_PORT_MAX * + CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES)); + top_priv->last_counter = 0; + top_priv->last_vote[top_priv->last_counter] = *agg_vote; + top_priv->last_counter = (top_priv->last_counter + 1) % + (CAM_TFE_TOP_IN_PORT_MAX * + CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES); + } else { + /* + * Find max bw request in last few frames. This will the bw + * that we want to vote to CPAS now. + */ + to_be_applied_axi_vote = + cam_tfe_top_delay_bw_reduction(top_priv, + &total_bw_new_vote); + if (!to_be_applied_axi_vote) { + CAM_ERR(CAM_ISP, "to_be_applied_axi_vote is NULL"); + rc = -EINVAL; + goto free_mem; + } + } + + for (i = 0; i < to_be_applied_axi_vote->num_paths; i++) { + CAM_DBG(CAM_PERF, + "tfe[%d] : Apply BW Vote : [%s][%s] [%llu %llu %llu]", + top_priv->common_data.hw_intf->hw_idx, + cam_cpas_axi_util_path_type_to_string( + to_be_applied_axi_vote->axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + to_be_applied_axi_vote->axi_path[i].transac_type), + to_be_applied_axi_vote->axi_path[i].camnoc_bw, + to_be_applied_axi_vote->axi_path[i].mnoc_ab_bw, + to_be_applied_axi_vote->axi_path[i].mnoc_ib_bw); + } + + if ((to_be_applied_axi_vote->num_paths != + top_priv->applied_axi_vote.num_paths) || + (total_bw_new_vote != top_priv->total_bw_applied)) + apply_bw_update = true; + + CAM_DBG(CAM_PERF, + "tfe[%d] : Delayed update: applied_total=%lld, new_total=%lld apply_bw_update=%d, start_stop=%d", + top_priv->common_data.hw_intf->hw_idx, + top_priv->total_bw_applied, total_bw_new_vote, + apply_bw_update, start_stop); + + if (apply_bw_update) { + rc = cam_cpas_update_axi_vote(soc_private->cpas_handle, + to_be_applied_axi_vote); + if (!rc) { + memcpy(&top_priv->applied_axi_vote, + to_be_applied_axi_vote, + sizeof(struct cam_axi_vote)); + top_priv->total_bw_applied = total_bw_new_vote; + } else { + CAM_ERR(CAM_ISP, "BW request failed, rc=%d", rc); + } + } + +free_mem: + kzfree(agg_vote); + agg_vote = NULL; + return rc; +} + +static int cam_tfe_top_get_base(struct cam_tfe_top_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + uint32_t size = 0; + uint32_t mem_base = 0; + struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; + + if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { + CAM_ERR(CAM_ISP, "Error Invalid cmd size"); + return -EINVAL; + } + + if (!cdm_args || !cdm_args->res || !top_priv || + !top_priv->common_data.soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid args"); + return -EINVAL; + } + + cdm_util_ops = + (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; + + if (!cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid CDM ops"); + return -EINVAL; + } + + size = cdm_util_ops->cdm_required_size_changebase(); + /* since cdm returns dwords, we need to convert it into bytes */ + if ((size * 4) > cdm_args->cmd.size) { + CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d", + cdm_args->cmd.size, size); + return -EINVAL; + } + + mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE( + top_priv->common_data.soc_info, TFE_CORE_BASE_IDX); + + cdm_util_ops->cdm_write_changebase( + cdm_args->cmd.cmd_buf_addr, mem_base); + cdm_args->cmd.used_bytes = (size * 4); + + return 0; +} + +static int cam_tfe_top_get_reg_update( + struct cam_tfe_top_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + uint32_t size = 0; + uint32_t reg_val_pair[2]; + struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; + struct cam_tfe_camif_data *camif_rsrc_data = NULL; + struct cam_tfe_rdi_data *rdi_rsrc_data = NULL; + struct cam_isp_resource_node *in_res; + + if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { + CAM_ERR(CAM_ISP, "Invalid cmd size"); + return -EINVAL; + } + + if (!cdm_args || !cdm_args->res) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + cdm_util_ops = (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; + + if (!cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid CDM ops"); + return -EINVAL; + } + + in_res = cdm_args->res; + size = cdm_util_ops->cdm_required_size_reg_random(1); + /* since cdm returns dwords, we need to convert it into bytes */ + if ((size * 4) > cdm_args->cmd.size) { + CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d", + cdm_args->cmd.size, size); + return -EINVAL; + } + + if (in_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + camif_rsrc_data = in_res->res_priv; + reg_val_pair[0] = camif_rsrc_data->camif_reg->reg_update_cmd; + reg_val_pair[1] = + camif_rsrc_data->reg_data->reg_update_cmd_data; + } else if ((in_res->res_id >= CAM_ISP_HW_TFE_IN_RDI0) && + (in_res->res_id <= CAM_ISP_HW_TFE_IN_RDI2)) { + rdi_rsrc_data = in_res->res_priv; + reg_val_pair[0] = rdi_rsrc_data->rdi_reg->reg_update_cmd; + reg_val_pair[1] = rdi_rsrc_data->reg_data->reg_update_cmd_data; + } + + cdm_util_ops->cdm_write_regrandom(cdm_args->cmd.cmd_buf_addr, + 1, reg_val_pair); + + cdm_args->cmd.used_bytes = size * 4; + + return 0; +} + +static int cam_tfe_top_clock_update( + struct cam_tfe_top_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_tfe_clock_update_args *clk_update = NULL; + struct cam_isp_resource_node *res = NULL; + struct cam_hw_info *hw_info = NULL; + int i, rc = 0; + + clk_update = + (struct cam_tfe_clock_update_args *)cmd_args; + res = clk_update->node_res; + + if (!res || !res->hw_intf->hw_priv) { + CAM_ERR(CAM_ISP, "Invalid input res %pK", res); + return -EINVAL; + } + + hw_info = res->hw_intf->hw_priv; + + if (res->res_type != CAM_ISP_RESOURCE_TFE_IN || + res->res_id >= CAM_ISP_HW_TFE_IN_MAX) { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res_type:%d res id%d", + res->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if (top_priv->in_rsrc[i].res_id == res->res_id) { + top_priv->req_clk_rate[i] = clk_update->clk_rate; + break; + } + } + + if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_DBG(CAM_ISP, + "TFE:%d Not ready to set clocks yet :%d", + res->hw_intf->hw_idx, + hw_info->hw_state); + } else + rc = cam_tfe_top_set_hw_clk_rate(top_priv); + + return rc; +} + +static int cam_tfe_top_bw_update( + struct cam_tfe_top_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_tfe_bw_update_args *bw_update = NULL; + struct cam_isp_resource_node *res = NULL; + struct cam_hw_info *hw_info = NULL; + int rc = 0; + int i; + + bw_update = (struct cam_tfe_bw_update_args *)cmd_args; + res = bw_update->node_res; + + if (!res || !res->hw_intf || !res->hw_intf->hw_priv) + return -EINVAL; + + hw_info = res->hw_intf->hw_priv; + + if (res->res_type != CAM_ISP_RESOURCE_TFE_IN || + res->res_id >= CAM_ISP_HW_TFE_IN_MAX) { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res_type:%d res id%d", + res->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + for (i = 0; i < CAM_ISP_HW_TFE_IN_MAX; i++) { + if (top_priv->in_rsrc[i].res_id == res->res_id) { + memcpy(&top_priv->req_axi_vote[i], &bw_update->isp_vote, + sizeof(struct cam_axi_vote)); + top_priv->axi_vote_control[i] = + CAM_TFE_BW_CONTROL_INCLUDE; + break; + } + } + + if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "TFE:%d Not ready to set BW yet :%d", + res->hw_intf->hw_idx, + hw_info->hw_state); + } else { + rc = cam_tfe_top_set_axi_bw_vote(top_priv, false); + } + + return rc; +} + +static int cam_tfe_top_bw_control( + struct cam_tfe_top_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_tfe_bw_control_args *bw_ctrl = NULL; + struct cam_isp_resource_node *res = NULL; + struct cam_hw_info *hw_info = NULL; + int rc = 0; + int i; + + bw_ctrl = (struct cam_tfe_bw_control_args *)cmd_args; + res = bw_ctrl->node_res; + + if (!res || !res->hw_intf->hw_priv) + return -EINVAL; + + hw_info = res->hw_intf->hw_priv; + + if (res->res_type != CAM_ISP_RESOURCE_TFE_IN || + res->res_id >= CAM_ISP_HW_TFE_IN_MAX) { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res_type:%d res id%d", + res->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if (top_priv->in_rsrc[i].res_id == res->res_id) { + top_priv->axi_vote_control[i] = bw_ctrl->action; + break; + } + } + + if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "TFE:%d Not ready to set BW yet :%d", + res->hw_intf->hw_idx, + hw_info->hw_state); + } else { + rc = cam_tfe_top_set_axi_bw_vote(top_priv, true); + } + + return rc; +} + +static int cam_tfe_top_get_reg_dump( + struct cam_tfe_top_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_isp_hw_get_cmd_update *reg_dump_cmd = cmd_args; + struct cam_tfe_soc_private *soc_private; + struct cam_tfe_reg_dump_data *reg_dump_data; + struct cam_hw_soc_info *soc_info; + void __iomem *mem_base; + int i, j, num_reg_dump_entries; + uint32_t val_0, val_1, val_2, val_3, wm_offset, start_offset; + uint32_t end_offset, lut_word_size, lut_size, lut_bank_sel, lut_dmi_reg; + + if (!reg_dump_cmd) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + if ((reg_dump_cmd->res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) || + (reg_dump_cmd->res->res_state == + CAM_ISP_RESOURCE_STATE_AVAILABLE)) + return 0; + + soc_info = top_priv->common_data.soc_info; + soc_private = top_priv->common_data.soc_info->soc_private; + mem_base = soc_info->reg_map[TFE_CORE_BASE_IDX].mem_base; + CAM_INFO(CAM_ISP, "dump tfe:%d registers", + top_priv->common_data.hw_intf->hw_idx); + + reg_dump_data = top_priv->common_data.reg_dump_data; + num_reg_dump_entries = reg_dump_data->num_reg_dump_entries; + for (i = 0; i < num_reg_dump_entries; i++) { + start_offset = reg_dump_data->reg_entry[i].start_offset; + end_offset = reg_dump_data->reg_entry[i].end_offset; + + for (j = start_offset; (j + 0xc) <= end_offset; j += 0x10) { + val_0 = cam_io_r_mb(mem_base + j); + val_1 = cam_io_r_mb(mem_base + j + 4); + val_2 = cam_io_r_mb(mem_base + j + 0x8); + val_3 = cam_io_r_mb(mem_base + j + 0xc); + CAM_INFO(CAM_ISP, "0x%04x=0x%08x 0x%08x 0x%08x 0x%08x", + j, val_0, val_1, val_2, val_3); + } + } + + num_reg_dump_entries = reg_dump_data->num_lut_dump_entries; + for (i = 0; i < num_reg_dump_entries; i++) { + lut_bank_sel = reg_dump_data->lut_entry[i].lut_bank_sel; + lut_size = reg_dump_data->lut_entry[i].lut_addr_size; + lut_word_size = reg_dump_data->lut_entry[i].lut_word_size; + lut_dmi_reg = reg_dump_data->lut_entry[i].dmi_reg_offset; + + cam_io_w_mb(lut_bank_sel, mem_base + lut_dmi_reg + 4); + cam_io_w_mb(0, mem_base + 0xC28); + + for (j = 0; j < lut_size; j++) { + val_0 = cam_io_r_mb(mem_base + 0xC30); + CAM_INFO(CAM_ISP, "Bank%d:0x%x LO: 0x%x", + lut_bank_sel, j, val_0); + } + } + /* No mem selected */ + cam_io_w_mb(0, mem_base + 0xC24); + cam_io_w_mb(0, mem_base + 0xC28); + + start_offset = reg_dump_data->bus_start_addr; + end_offset = reg_dump_data->bus_write_top_end_addr; + + CAM_INFO(CAM_ISP, "bus start addr:0x%x end_offset:0x%x", + start_offset, end_offset); + + for (i = start_offset; (i + 0xc) <= end_offset; i += 0x10) { + val_0 = cam_io_r_mb(mem_base + i); + val_1 = cam_io_r_mb(mem_base + i + 4); + val_2 = cam_io_r_mb(mem_base + i + 0x8); + val_3 = cam_io_r_mb(mem_base + i + 0xc); + CAM_INFO(CAM_ISP, "0x%04x=0x%08x 0x%08x 0x%08x 0x%08x", + i, val_0, val_1, val_2, val_3); + } + + wm_offset = reg_dump_data->bus_client_start_addr; + + CAM_INFO(CAM_ISP, "bus wm offset:0x%x", + wm_offset); + + for (j = 0; j < reg_dump_data->num_bus_clients; j++) { + for (i = 0x0; (i + 0xc) <= 0x3C; i += 0x10) { + val_0 = cam_io_r_mb(mem_base + wm_offset + i); + val_1 = cam_io_r_mb(mem_base + wm_offset + i + 4); + val_2 = cam_io_r_mb(mem_base + wm_offset + i + 0x8); + val_3 = cam_io_r_mb(mem_base + wm_offset + i + 0xc); + CAM_INFO(CAM_ISP, "0x%04x=0x%08x 0x%08x 0x%08x 0x%08x", + (wm_offset + i), val_0, val_1, val_2, val_3); + } + for (i = 0x60; (i + 0xc) <= 0x80; i += 0x10) { + val_0 = cam_io_r_mb(mem_base + wm_offset + i); + val_1 = cam_io_r_mb(mem_base + wm_offset + i + 4); + val_2 = cam_io_r_mb(mem_base + wm_offset + i + 0x8); + val_3 = cam_io_r_mb(mem_base + wm_offset + i + 0xc); + CAM_INFO(CAM_ISP, "0x%04x=0x%08x 0x%08x 0x%08x 0x%08x", + (wm_offset + i), val_0, val_1, val_2, val_3); + } + wm_offset += reg_dump_data->bus_client_offset; + } + + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x20, true, &val_0); + CAM_INFO(CAM_ISP, "tfe_niu_MaxWr_Low offset 0x20 val 0x%x", + val_0); + + /* dump the clock votings */ + CAM_INFO(CAM_ISP, "TFE:%d clk=%ld", + top_priv->common_data.hw_intf->hw_idx, + top_priv->hw_clk_rate); + + return 0; +} + +static int cam_tfe_hw_dump( + struct cam_tfe_hw_core_info *core_info, + void *cmd_args, + uint32_t arg_size) +{ + int i, j; + uint8_t *dst; + uint32_t reg_start_offset; + uint32_t reg_dump_size = 0; + uint32_t lut_dump_size = 0; + uint32_t num_lut_dump_entries = 0; + uint32_t num_reg; + uint32_t lut_word_size, lut_size; + uint32_t lut_bank_sel, lut_dmi_reg; + uint32_t val; + void __iomem *reg_base; + void __iomem *mem_base; + uint32_t *addr, *start; + uint64_t *clk_waddr, *clk_wstart; + size_t remain_len; + uint32_t min_len; + struct cam_hw_info *tfe_hw_info; + struct cam_hw_soc_info *soc_info; + struct cam_tfe_top_priv *top_priv; + struct cam_tfe_soc_private *soc_private; + struct cam_tfe_reg_dump_data *reg_dump_data; + struct cam_isp_hw_dump_header *hdr; + struct cam_isp_hw_dump_args *dump_args = + (struct cam_isp_hw_dump_args *)cmd_args; + + if (!dump_args || !core_info) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + if (!dump_args->cpu_addr || !dump_args->buf_len) { + CAM_ERR(CAM_ISP, + "Invalid params %pK %zu", + (void *)dump_args->cpu_addr, + dump_args->buf_len); + return -EINVAL; + } + + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_ISP, + "Dump offset overshoot offset %zu buf_len %zu", + dump_args->offset, dump_args->buf_len); + return -ENOSPC; + } + + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + tfe_hw_info = + (struct cam_hw_info *)(top_priv->common_data.hw_intf->hw_priv); + reg_dump_data = top_priv->common_data.reg_dump_data; + soc_info = top_priv->common_data.soc_info; + soc_private = top_priv->common_data.soc_info->soc_private; + mem_base = soc_info->reg_map[TFE_CORE_BASE_IDX].mem_base; + + if (dump_args->is_dump_all) { + + /*Dump registers size*/ + for (i = 0; i < reg_dump_data->num_reg_dump_entries; i++) + reg_dump_size += + (reg_dump_data->reg_entry[i].end_offset - + reg_dump_data->reg_entry[i].start_offset); + + /* + * We dump the offset as well, so the total size dumped becomes + * multiplied by 2 + */ + reg_dump_size *= 2; + + /* LUT dump size */ + for (i = 0; i < reg_dump_data->num_lut_dump_entries; i++) + lut_dump_size += + ((reg_dump_data->lut_entry[i].lut_addr_size) * + (reg_dump_data->lut_entry[i].lut_word_size/8)); + + num_lut_dump_entries = reg_dump_data->num_lut_dump_entries; + } + + /*Minimum len comprises of: + * lut_dump_size + reg_dump_size + sizeof dump_header + + * (num_lut_dump_entries--> represents number of banks) + + * (misc number of words) * sizeof(uint32_t) + */ + min_len = lut_dump_size + reg_dump_size + + sizeof(struct cam_isp_hw_dump_header) + + (num_lut_dump_entries * sizeof(uint32_t)) + + (sizeof(uint32_t) * CAM_TFE_CORE_DUMP_MISC_NUM_WORDS); + + remain_len = dump_args->buf_len - dump_args->offset; + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu, min %u", + remain_len, min_len); + return -ENOSPC; + } + + mutex_lock(&tfe_hw_info->hw_mutex); + if (tfe_hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "TFE:%d HW not powered up", + core_info->core_index); + mutex_unlock(&tfe_hw_info->hw_mutex); + return -EPERM; + } + + if (!dump_args->is_dump_all) + goto dump_bw; + + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + hdr->word_size = sizeof(uint32_t); + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "TFE_REG:"); + addr = (uint32_t *)(dst + sizeof(struct cam_isp_hw_dump_header)); + start = addr; + *addr++ = soc_info->index; + for (i = 0; i < reg_dump_data->num_reg_dump_entries; i++) { + num_reg = (reg_dump_data->reg_entry[i].end_offset - + reg_dump_data->reg_entry[i].start_offset)/4; + reg_start_offset = reg_dump_data->reg_entry[i].start_offset; + reg_base = mem_base + reg_start_offset; + for (j = 0; j < num_reg; j++) { + addr[0] = + soc_info->mem_block[TFE_CORE_BASE_IDX]->start + + reg_start_offset + (j*4); + addr[1] = cam_io_r(reg_base + (j*4)); + addr += 2; + } + } + + /*Dump bus top registers*/ + num_reg = (reg_dump_data->bus_write_top_end_addr - + reg_dump_data->bus_start_addr)/4; + reg_base = mem_base + reg_dump_data->bus_start_addr; + reg_start_offset = soc_info->mem_block[TFE_CORE_BASE_IDX]->start + + reg_dump_data->bus_start_addr; + for (i = 0; i < num_reg; i++) { + addr[0] = reg_start_offset + (i*4); + addr[1] = cam_io_r(reg_base + (i*4)); + addr += 2; + } + + /* Dump bus clients */ + reg_base = mem_base + reg_dump_data->bus_client_start_addr; + reg_start_offset = soc_info->mem_block[TFE_CORE_BASE_IDX]->start + + reg_dump_data->bus_client_start_addr; + for (j = 0; j < reg_dump_data->num_bus_clients; j++) { + + for (i = 0; i <= 0x3c; i += 4) { + addr[0] = reg_start_offset + i; + addr[1] = cam_io_r(reg_base + i); + addr += 2; + } + for (i = 0x60; i <= 0x80; i += 4) { + addr[0] = reg_start_offset + (i*4); + addr[1] = cam_io_r(reg_base + (i*4)); + addr += 2; + } + reg_base += reg_dump_data->bus_client_offset; + reg_start_offset += reg_dump_data->bus_client_offset; + } + + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + + /* Dump LUT entries */ + for (i = 0; i < reg_dump_data->num_lut_dump_entries; i++) { + + lut_bank_sel = reg_dump_data->lut_entry[i].lut_bank_sel; + lut_size = reg_dump_data->lut_entry[i].lut_addr_size; + lut_word_size = reg_dump_data->lut_entry[i].lut_word_size; + lut_dmi_reg = reg_dump_data->lut_entry[i].dmi_reg_offset; + dst = (char *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "LUT_REG:"); + hdr->word_size = lut_word_size/8; + addr = (uint32_t *)(dst + + sizeof(struct cam_isp_hw_dump_header)); + start = addr; + *addr++ = lut_bank_sel; + cam_io_w_mb(lut_bank_sel, mem_base + lut_dmi_reg + 4); + cam_io_w_mb(0, mem_base + 0xC28); + for (j = 0; j < lut_size; j++) { + *addr = cam_io_r_mb(mem_base + 0xc30); + addr++; + } + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + } + cam_io_w_mb(0, mem_base + 0xC24); + cam_io_w_mb(0, mem_base + 0xC28); + +dump_bw: + dst = (char *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "TFE_CLK_RATE_BW:"); + clk_waddr = (uint64_t *)(dst + + sizeof(struct cam_isp_hw_dump_header)); + clk_wstart = clk_waddr; + hdr->word_size = sizeof(uint64_t); + *clk_waddr++ = top_priv->hw_clk_rate; + *clk_waddr++ = top_priv->total_bw_applied; + + hdr->size = hdr->word_size * (clk_waddr - clk_wstart); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + + dst = (char *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "TFE_NIU_MAXWR:"); + addr = (uint32_t *)(dst + + sizeof(struct cam_isp_hw_dump_header)); + start = addr; + hdr->word_size = sizeof(uint32_t); + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x20, true, &val); + *addr++ = val; + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + mutex_unlock(&tfe_hw_info->hw_mutex); + + CAM_DBG(CAM_ISP, "offset %zu", dump_args->offset); + return 0; +} + +static int cam_tfe_camif_irq_reg_dump( + struct cam_tfe_hw_core_info *core_info, + void *cmd_args, uint32_t arg_size) +{ + struct cam_tfe_top_priv *top_priv; + struct cam_isp_hw_get_cmd_update *cmd_update; + struct cam_isp_resource_node *camif_res = NULL; + void __iomem *mem_base; + uint32_t i; + + int rc = 0; + + if (!cmd_args) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments\n"); + return -EINVAL; + } + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + cmd_update = (struct cam_isp_hw_get_cmd_update *)cmd_args; + camif_res = cmd_update->res; + mem_base = top_priv->common_data.soc_info->reg_map[0].mem_base; + if ((camif_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) || + (camif_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE)) { + CAM_ERR(CAM_ISP, "Error! Invalid state\n"); + return 0; + } + + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) { + CAM_INFO(CAM_ISP, + "Core Id =%d TOP IRQ status[%d ] val 0x%x", + core_info->core_index, i, + cam_io_r_mb(mem_base + + core_info->tfe_hw_info->top_irq_status[i])); + } + + for (i = 0; i < CAM_TFE_BUS_MAX_IRQ_REGISTERS; i++) { + CAM_INFO(CAM_ISP, + "Core Id =%d BUS IRQ status[%d ] val:0x%x", + core_info->core_index, i, + cam_io_r_mb(mem_base + + core_info->tfe_hw_info->bus_irq_status[i])); + } + + return rc; +} + +int cam_tfe_top_reserve(void *device_priv, + void *reserve_args, uint32_t arg_size) +{ + struct cam_tfe_top_priv *top_priv; + struct cam_tfe_acquire_args *args; + struct cam_tfe_hw_tfe_in_acquire_args *acquire_args; + struct cam_tfe_camif_data *camif_data; + struct cam_tfe_rdi_data *rdi_data; + uint32_t i; + int rc = -EINVAL; + + if (!device_priv || !reserve_args) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + top_priv = (struct cam_tfe_top_priv *)device_priv; + args = (struct cam_tfe_acquire_args *)reserve_args; + acquire_args = &args->tfe_in; + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + CAM_DBG(CAM_ISP, "i :%d res_id:%d state:%d", i, + acquire_args->res_id, top_priv->in_rsrc[i].res_state); + + if ((top_priv->in_rsrc[i].res_id == acquire_args->res_id) && + (top_priv->in_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_AVAILABLE)) { + rc = cam_tfe_validate_pix_pattern( + acquire_args->in_port->pix_pattern); + if (rc) + return rc; + + if (acquire_args->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + camif_data = (struct cam_tfe_camif_data *) + top_priv->in_rsrc[i].res_priv; + camif_data->pix_pattern = + acquire_args->in_port->pix_pattern; + camif_data->dsp_mode = + acquire_args->in_port->dsp_mode; + camif_data->left_first_pixel = + acquire_args->in_port->left_start; + camif_data->left_last_pixel = + acquire_args->in_port->left_end; + camif_data->right_first_pixel = + acquire_args->in_port->right_start; + camif_data->right_last_pixel = + acquire_args->in_port->right_end; + camif_data->first_line = + acquire_args->in_port->line_start; + camif_data->last_line = + acquire_args->in_port->line_end; + camif_data->camif_pd_enable = + acquire_args->camif_pd_enable; + camif_data->dual_tfe_sync_sel = + acquire_args->dual_tfe_sync_sel_idx; + camif_data->sync_mode = acquire_args->sync_mode; + camif_data->event_cb = args->event_cb; + camif_data->priv = args->priv; + + CAM_DBG(CAM_ISP, + "TFE:%d pix_pattern:%d dsp_mode=%d", + top_priv->in_rsrc[i].hw_intf->hw_idx, + camif_data->pix_pattern, + camif_data->dsp_mode); + } else { + rdi_data = (struct cam_tfe_rdi_data *) + top_priv->in_rsrc[i].res_priv; + rdi_data->pix_pattern = + acquire_args->in_port->pix_pattern; + rdi_data->sync_mode = acquire_args->sync_mode; + rdi_data->event_cb = args->event_cb; + rdi_data->priv = args->priv; + rdi_data->left_first_pixel = + acquire_args->in_port->left_start; + rdi_data->left_last_pixel = + acquire_args->in_port->left_end; + rdi_data->first_line = + acquire_args->in_port->line_start; + rdi_data->last_line = + acquire_args->in_port->line_end; + } + + top_priv->in_rsrc[i].cdm_ops = acquire_args->cdm_ops; + top_priv->in_rsrc[i].tasklet_info = args->tasklet; + top_priv->in_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_RESERVED; + top_priv->tasklet_info = args->tasklet; + acquire_args->rsrc_node = + &top_priv->in_rsrc[i]; + rc = 0; + break; + } + } + + return rc; +} + +int cam_tfe_top_release(void *device_priv, + void *release_args, uint32_t arg_size) +{ + struct cam_tfe_top_priv *top_priv; + struct cam_isp_resource_node *in_res; + + if (!device_priv || !release_args) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + top_priv = (struct cam_tfe_top_priv *)device_priv; + in_res = (struct cam_isp_resource_node *)release_args; + + CAM_DBG(CAM_ISP, "TFE:%d resource id:%d in state %d", + in_res->hw_intf->hw_idx, in_res->res_id, + in_res->res_state); + if (in_res->res_state < CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "TFE:%d Error Resource Invalid res_state :%d", + in_res->hw_intf->hw_idx, in_res->res_state); + return -EINVAL; + } + in_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + in_res->cdm_ops = NULL; + in_res->tasklet_info = NULL; + in_res->rdi_only_ctx = 0; + + return 0; +} + +static int cam_tfe_camif_resource_start( + struct cam_tfe_hw_core_info *core_info, + struct cam_isp_resource_node *camif_res) +{ + struct cam_tfe_camif_data *rsrc_data; + struct cam_tfe_soc_private *soc_private; + uint32_t val = 0; + uint32_t epoch0_irq_mask; + uint32_t epoch1_irq_mask; + uint32_t computed_epoch_line_cfg; + uint32_t camera_hw_version = 0; + + if (!camif_res || !core_info) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + if (camif_res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "TFE:%d Error Invalid camif res res_state:%d", + core_info->core_index, camif_res->res_state); + return -EINVAL; + } + + rsrc_data = (struct cam_tfe_camif_data *)camif_res->res_priv; + soc_private = rsrc_data->soc_info->soc_private; + + if (!soc_private) { + CAM_ERR(CAM_ISP, "TFE:%d Error soc_private NULL", + core_info->core_index); + return -ENODEV; + } + + /* Config tfe core*/ + val = 0; + if (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) + val = (1 << rsrc_data->reg_data->extern_reg_update_shift); + + if ((rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) || + (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_MASTER)) { + val |= (1 << rsrc_data->reg_data->dual_tfe_pix_en_shift); + val |= ((rsrc_data->dual_tfe_sync_sel + 1) << + rsrc_data->reg_data->dual_tfe_sync_sel_shift); + } + + if (!rsrc_data->camif_pd_enable) + val |= (1 << rsrc_data->reg_data->camif_pd_rdi2_src_sel_shift); + + /* enables the Delay Line CLC in the pixel pipeline */ + val |= BIT(rsrc_data->reg_data->delay_line_en_shift); + + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg_0); + + CAM_DBG(CAM_ISP, "TFE:%d core_cfg 0 val:0x%x", core_info->core_index, + val); + + if (cam_cpas_get_cpas_hw_version(&camera_hw_version)) + CAM_ERR(CAM_ISP, "Failed to get HW version"); + + if (camera_hw_version == CAM_CPAS_TITAN_540_V100) { + val = cam_io_r(rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg_1); + val &= ~BIT(0); + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg_1); + CAM_DBG(CAM_ISP, "TFE:%d core_cfg 1 val:0x%x", + core_info->core_index, val); + } + + /* Epoch config */ + epoch0_irq_mask = ((rsrc_data->last_line - + rsrc_data->first_line) / 2) + + rsrc_data->first_line; + epoch1_irq_mask = rsrc_data->reg_data->epoch_line_cfg & + 0xFFFF; + computed_epoch_line_cfg = (epoch0_irq_mask << 16) | + epoch1_irq_mask; + cam_io_w_mb(computed_epoch_line_cfg, + rsrc_data->mem_base + + rsrc_data->camif_reg->epoch_irq_cfg); + CAM_DBG(CAM_ISP, "TFE:%d first_line: %u\n" + "last_line: %u\n" + "epoch_line_cfg: 0x%x", + core_info->core_index, + rsrc_data->first_line, + rsrc_data->last_line, + computed_epoch_line_cfg); + + camif_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + /* Reg Update */ + cam_io_w_mb(rsrc_data->reg_data->reg_update_cmd_data, + rsrc_data->mem_base + rsrc_data->camif_reg->reg_update_cmd); + CAM_DBG(CAM_ISP, "hw id:%d RUP val:%d", camif_res->hw_intf->hw_idx, + rsrc_data->reg_data->reg_update_cmd_data); + + /* Disable sof irq debug flag */ + rsrc_data->enable_sof_irq_debug = false; + rsrc_data->irq_debug_cnt = 0; + + if (rsrc_data->camif_debug & CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS) { + val = cam_io_r_mb(rsrc_data->mem_base + + rsrc_data->common_reg->diag_config); + val |= rsrc_data->reg_data->enable_diagnostic_hw; + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->common_reg->diag_config); + } + + /* Enable the irq */ + cam_tfe_irq_config(core_info, rsrc_data->reg_data->subscribe_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, true); + + /* Program perf counters */ + val = (1 << rsrc_data->reg_data->perf_cnt_start_cmd_shift) | + (1 << rsrc_data->reg_data->perf_cnt_continuous_shift) | + (1 << rsrc_data->reg_data->perf_client_sel_shift) | + (1 << rsrc_data->reg_data->perf_window_start_shift) | + (2 << rsrc_data->reg_data->perf_window_end_shift); + cam_io_w_mb(val, + rsrc_data->mem_base + rsrc_data->common_reg->perf_cnt_cfg); + CAM_DBG(CAM_ISP, "TFE:%d perf_cfg val:%d", core_info->core_index, + val); + + /* Enable the top debug registers */ + cam_io_w_mb(0x1, + rsrc_data->mem_base + rsrc_data->common_reg->debug_cfg); + + CAM_DBG(CAM_ISP, "Start Camif TFE %d Done", core_info->core_index); + return 0; +} + +int cam_tfe_top_start(struct cam_tfe_hw_core_info *core_info, + void *start_args, uint32_t arg_size) +{ + struct cam_tfe_top_priv *top_priv; + struct cam_isp_resource_node *in_res; + struct cam_hw_info *hw_info = NULL; + struct cam_tfe_rdi_data *rsrc_rdi_data; + uint32_t val; + int rc = 0; + + if (!start_args) { + CAM_ERR(CAM_ISP, "TFE:%d Error Invalid input arguments", + core_info->core_index); + return -EINVAL; + } + + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + in_res = (struct cam_isp_resource_node *)start_args; + hw_info = (struct cam_hw_info *)in_res->hw_intf->hw_priv; + + if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "TFE:%d HW not powered up", + core_info->core_index); + rc = -EPERM; + goto end; + } + + rc = cam_tfe_top_set_hw_clk_rate(top_priv); + if (rc) { + CAM_ERR(CAM_ISP, "TFE:%d set_hw_clk_rate failed, rc=%d", + hw_info->soc_info.index, rc); + return rc; + } + + rc = cam_tfe_top_set_axi_bw_vote(top_priv, true); + if (rc) { + CAM_ERR(CAM_ISP, "TFE:%d set_axi_bw_vote failed, rc=%d", + core_info->core_index, rc); + return rc; + } + + if (in_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + cam_tfe_camif_resource_start(core_info, in_res); + } else if (in_res->res_id >= CAM_ISP_HW_TFE_IN_RDI0 || + in_res->res_id <= CAM_ISP_HW_TFE_IN_RDI2) { + rsrc_rdi_data = (struct cam_tfe_rdi_data *) in_res->res_priv; + val = (rsrc_rdi_data->pix_pattern << + rsrc_rdi_data->reg_data->pixel_pattern_shift); + + val |= (1 << rsrc_rdi_data->reg_data->rdi_out_enable_shift); + cam_io_w_mb(val, rsrc_rdi_data->mem_base + + rsrc_rdi_data->rdi_reg->rdi_module_config); + + /* Epoch config */ + cam_io_w_mb(rsrc_rdi_data->reg_data->epoch_line_cfg, + rsrc_rdi_data->mem_base + + rsrc_rdi_data->rdi_reg->rdi_epoch_irq); + + /* Reg Update */ + cam_io_w_mb(rsrc_rdi_data->reg_data->reg_update_cmd_data, + rsrc_rdi_data->mem_base + + rsrc_rdi_data->rdi_reg->reg_update_cmd); + in_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + /* Enable the irq */ + if (in_res->rdi_only_ctx) + cam_tfe_irq_config(core_info, + rsrc_rdi_data->reg_data->subscribe_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, true); + + CAM_DBG(CAM_ISP, "TFE:%d Start RDI %d", core_info->core_index, + in_res->res_id - CAM_ISP_HW_TFE_IN_RDI0); + } + + core_info->irq_err_config_cnt++; + if (core_info->irq_err_config_cnt == 1) { + cam_tfe_irq_config(core_info, + core_info->tfe_hw_info->error_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, true); + top_priv->error_ts.tv_sec = 0; + top_priv->error_ts.tv_usec = 0; + top_priv->sof_ts.tv_sec = 0; + top_priv->sof_ts.tv_usec = 0; + top_priv->epoch_ts.tv_sec = 0; + top_priv->epoch_ts.tv_usec = 0; + top_priv->eof_ts.tv_sec = 0; + top_priv->eof_ts.tv_usec = 0; + } + +end: + return rc; +} + +int cam_tfe_top_stop(struct cam_tfe_hw_core_info *core_info, + void *stop_args, uint32_t arg_size) +{ + struct cam_tfe_top_priv *top_priv; + struct cam_isp_resource_node *in_res; + struct cam_hw_info *hw_info = NULL; + struct cam_tfe_camif_data *camif_data; + struct cam_tfe_rdi_data *rsrc_rdi_data; + uint32_t val = 0; + int i, rc = 0; + + if (!stop_args) { + CAM_ERR(CAM_ISP, "TFE:%d Error Invalid input arguments", + core_info->core_index); + return -EINVAL; + } + + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + in_res = (struct cam_isp_resource_node *)stop_args; + hw_info = (struct cam_hw_info *)in_res->hw_intf->hw_priv; + + if (in_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED || + in_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE) + return 0; + + if (in_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + camif_data = (struct cam_tfe_camif_data *)in_res->res_priv; + + cam_io_w_mb(0, camif_data->mem_base + + camif_data->camif_reg->module_cfg); + + cam_tfe_irq_config(core_info, + camif_data->reg_data->subscribe_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, false); + + if (in_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + in_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + val = cam_io_r_mb(camif_data->mem_base + + camif_data->common_reg->diag_config); + if (val & camif_data->reg_data->enable_diagnostic_hw) { + val &= ~camif_data->reg_data->enable_diagnostic_hw; + cam_io_w_mb(val, camif_data->mem_base + + camif_data->common_reg->diag_config); + } + } else if ((in_res->res_id >= CAM_ISP_HW_TFE_IN_RDI0) && + (in_res->res_id <= CAM_ISP_HW_TFE_IN_RDI2)) { + rsrc_rdi_data = (struct cam_tfe_rdi_data *) in_res->res_priv; + cam_io_w_mb(0x0, rsrc_rdi_data->mem_base + + rsrc_rdi_data->rdi_reg->rdi_module_config); + + if (in_res->rdi_only_ctx) + cam_tfe_irq_config(core_info, + rsrc_rdi_data->reg_data->subscribe_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, false); + + if (in_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + in_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + } else { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res id:%d", + core_info->core_index, in_res->res_id); + return -EINVAL; + } + + if (!rc) { + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if (top_priv->in_rsrc[i].res_id == in_res->res_id) { + top_priv->req_clk_rate[i] = 0; + memset(&top_priv->req_axi_vote[i], 0, + sizeof(struct cam_axi_vote)); + top_priv->axi_vote_control[i] = + CAM_TFE_BW_CONTROL_EXCLUDE; + break; + } + } + } + + core_info->irq_err_config_cnt--; + if (!core_info->irq_err_config_cnt) + cam_tfe_irq_config(core_info, + core_info->tfe_hw_info->error_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, false); + + return rc; +} + +int cam_tfe_top_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *top_hw_info, + struct cam_tfe_hw_core_info *core_info) +{ + struct cam_tfe_top_priv *top_priv = NULL; + struct cam_tfe_top_hw_info *hw_info = top_hw_info; + struct cam_tfe_soc_private *soc_private = NULL; + struct cam_tfe_camif_data *camif_priv = NULL; + struct cam_tfe_rdi_data *rdi_priv = NULL; + int i, j, rc = 0; + + top_priv = kzalloc(sizeof(struct cam_tfe_top_priv), + GFP_KERNEL); + if (!top_priv) { + CAM_DBG(CAM_ISP, "TFE:%DError Failed to alloc for tfe_top_priv", + core_info->core_index); + rc = -ENOMEM; + goto end; + } + core_info->top_priv = top_priv; + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "TFE:%d Error soc_private NULL", + core_info->core_index); + rc = -ENODEV; + goto free_tfe_top_priv; + } + + top_priv->hw_clk_rate = 0; + memset(top_priv->last_vote, 0x0, sizeof(struct cam_axi_vote) * + (CAM_TFE_TOP_IN_PORT_MAX * + CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES)); + top_priv->last_counter = 0; + + for (i = 0, j = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + top_priv->in_rsrc[i].res_type = CAM_ISP_RESOURCE_TFE_IN; + top_priv->in_rsrc[i].hw_intf = hw_intf; + top_priv->in_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + top_priv->req_clk_rate[i] = 0; + memset(&top_priv->req_axi_vote[i], 0, + sizeof(struct cam_axi_vote)); + top_priv->axi_vote_control[i] = + CAM_TFE_BW_CONTROL_EXCLUDE; + + if (hw_info->in_port[i] == CAM_TFE_CAMIF_VER_1_0) { + top_priv->in_rsrc[i].res_id = + CAM_ISP_HW_TFE_IN_CAMIF; + + camif_priv = kzalloc(sizeof(struct cam_tfe_camif_data), + GFP_KERNEL); + if (!camif_priv) { + CAM_DBG(CAM_ISP, + "TFE:%dError Failed to alloc for camif_priv", + core_info->core_index); + goto free_tfe_top_priv; + } + + top_priv->in_rsrc[i].res_priv = camif_priv; + + camif_priv->mem_base = + soc_info->reg_map[TFE_CORE_BASE_IDX].mem_base; + camif_priv->camif_reg = + hw_info->camif_hw_info.camif_reg; + camif_priv->common_reg = hw_info->common_reg; + camif_priv->reg_data = + hw_info->camif_hw_info.reg_data; + camif_priv->hw_intf = hw_intf; + camif_priv->soc_info = soc_info; + + } else if (hw_info->in_port[i] == + CAM_TFE_RDI_VER_1_0) { + top_priv->in_rsrc[i].res_id = + CAM_ISP_HW_TFE_IN_RDI0 + j; + + rdi_priv = kzalloc(sizeof(struct cam_tfe_rdi_data), + GFP_KERNEL); + if (!rdi_priv) { + CAM_DBG(CAM_ISP, + "TFE:%d Error Failed to alloc for rdi_priv", + core_info->core_index); + goto deinit_resources; + } + + top_priv->in_rsrc[i].res_priv = rdi_priv; + + rdi_priv->mem_base = + soc_info->reg_map[TFE_CORE_BASE_IDX].mem_base; + rdi_priv->hw_intf = hw_intf; + rdi_priv->common_reg = hw_info->common_reg; + rdi_priv->rdi_reg = + hw_info->rdi_hw_info[j].rdi_reg; + rdi_priv->reg_data = + hw_info->rdi_hw_info[j++].reg_data; + } else { + CAM_WARN(CAM_ISP, "TFE:%d Invalid inport type: %u", + core_info->core_index, hw_info->in_port[i]); + } + } + + top_priv->common_data.soc_info = soc_info; + top_priv->common_data.hw_intf = hw_intf; + top_priv->common_data.common_reg = hw_info->common_reg; + top_priv->common_data.reg_dump_data = &hw_info->reg_dump_data; + + return rc; + +deinit_resources: + for (--i; i >= 0; i--) { + + top_priv->in_rsrc[i].start = NULL; + top_priv->in_rsrc[i].stop = NULL; + top_priv->in_rsrc[i].process_cmd = NULL; + top_priv->in_rsrc[i].top_half_handler = NULL; + top_priv->in_rsrc[i].bottom_half_handler = NULL; + + if (!top_priv->in_rsrc[i].res_priv) + continue; + + kfree(top_priv->in_rsrc[i].res_priv); + top_priv->in_rsrc[i].res_priv = NULL; + top_priv->in_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + } +free_tfe_top_priv: + kfree(core_info->top_priv); + core_info->top_priv = NULL; +end: + return rc; +} + + +int cam_tfe_top_deinit(struct cam_tfe_top_priv *top_priv) +{ + int i, rc = 0; + + if (!top_priv) { + CAM_ERR(CAM_ISP, "Error Invalid input"); + return -EINVAL; + } + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + top_priv->in_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + + top_priv->in_rsrc[i].start = NULL; + top_priv->in_rsrc[i].stop = NULL; + top_priv->in_rsrc[i].process_cmd = NULL; + top_priv->in_rsrc[i].top_half_handler = NULL; + top_priv->in_rsrc[i].bottom_half_handler = NULL; + + if (!top_priv->in_rsrc[i].res_priv) { + CAM_ERR(CAM_ISP, "Error res_priv is NULL"); + return -ENODEV; + } + + kfree(top_priv->in_rsrc[i].res_priv); + top_priv->in_rsrc[i].res_priv = NULL; + } + + return rc; +} + +int cam_tfe_reset(void *hw_priv, void *reset_core_args, uint32_t arg_size) +{ + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_tfe_top_priv *top_priv = NULL; + struct cam_tfe_hw_info *hw_info = NULL; + void __iomem *mem_base; + uint32_t *reset_reg_args = reset_core_args; + uint32_t i, reset_reg_val, irq_status[3]; + int rc; + + CAM_DBG(CAM_ISP, "Enter"); + + if (!hw_priv) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + soc_info = &tfe_hw->soc_info; + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + top_priv = core_info->top_priv; + hw_info = core_info->tfe_hw_info; + mem_base = tfe_hw->soc_info.reg_map[TFE_CORE_BASE_IDX].mem_base; + + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + irq_status[i] = cam_io_r(mem_base + + core_info->tfe_hw_info->top_irq_status[i]); + + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + cam_io_w(irq_status[i], mem_base + + core_info->tfe_hw_info->top_irq_clear[i]); + + cam_io_w_mb(core_info->tfe_hw_info->global_clear_bitmask, + mem_base + core_info->tfe_hw_info->top_irq_cmd); + + /* Mask all irq registers */ + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + cam_io_w(0, mem_base + + core_info->tfe_hw_info->top_irq_mask[i]); + + cam_tfe_irq_config(core_info, hw_info->reset_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, true); + + reinit_completion(&core_info->reset_complete); + + CAM_DBG(CAM_ISP, "calling RESET on tfe %d", soc_info->index); + + switch (*reset_reg_args) { + case CAM_TFE_HW_RESET_HW_AND_REG: + reset_reg_val = CAM_TFE_HW_RESET_HW_AND_REG_VAL; + break; + default: + reset_reg_val = CAM_TFE_HW_RESET_HW_VAL; + break; + } + + cam_io_w_mb(reset_reg_val, mem_base + + top_priv->common_data.common_reg->global_reset_cmd); + + CAM_DBG(CAM_ISP, "TFE:%d waiting for tfe reset complete", + core_info->core_index); + /* Wait for Completion or Timeout of 100ms */ + rc = wait_for_completion_timeout(&core_info->reset_complete, + msecs_to_jiffies(100)); + if (rc <= 0) { + CAM_ERR(CAM_ISP, "TFE:%d Error Reset Timeout", + core_info->core_index); + rc = -ETIMEDOUT; + } else { + rc = 0; + CAM_DBG(CAM_ISP, "TFE:%d reset complete done (%d)", + core_info->core_index, rc); + } + + CAM_DBG(CAM_ISP, "TFE:%d reset complete done (%d)", + core_info->core_index, rc); + + cam_tfe_irq_config(core_info, hw_info->reset_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, false); + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +int cam_tfe_init_hw(void *hw_priv, void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_tfe_top_priv *top_priv; + void __iomem *mem_base; + int rc = 0; + uint32_t reset_core_args = + CAM_TFE_HW_RESET_HW_AND_REG; + + CAM_DBG(CAM_ISP, "Enter"); + if (!hw_priv) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + soc_info = &tfe_hw->soc_info; + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + + mutex_lock(&tfe_hw->hw_mutex); + tfe_hw->open_count++; + if (tfe_hw->open_count > 1) { + mutex_unlock(&tfe_hw->hw_mutex); + CAM_DBG(CAM_ISP, "TFE:%d has already been initialized cnt %d", + core_info->core_index, tfe_hw->open_count); + return 0; + } + mutex_unlock(&tfe_hw->hw_mutex); + + /* Turn ON Regulators, Clocks and other SOC resources */ + rc = cam_tfe_enable_soc_resources(soc_info); + if (rc) { + CAM_ERR(CAM_ISP, "Enable SOC failed"); + rc = -EFAULT; + goto decrement_open_cnt; + } + tfe_hw->hw_state = CAM_HW_STATE_POWER_UP; + + mem_base = tfe_hw->soc_info.reg_map[TFE_CORE_BASE_IDX].mem_base; + CAM_DBG(CAM_ISP, "TFE:%d Enable soc done", core_info->core_index); + + /* Do HW Reset */ + rc = cam_tfe_reset(hw_priv, &reset_core_args, sizeof(uint32_t)); + if (rc) { + CAM_ERR(CAM_ISP, "TFE:%d Reset Failed rc=%d", + core_info->core_index, rc); + goto disable_soc; + } + + top_priv->hw_clk_rate = 0; + core_info->irq_err_config_cnt = 0; + core_info->irq_err_config = false; + rc = core_info->tfe_bus->hw_ops.init(core_info->tfe_bus->bus_priv, + NULL, 0); + if (rc) { + CAM_ERR(CAM_ISP, "TFE:%d Top HW init Failed rc=%d", + core_info->core_index, rc); + goto disable_soc; + } + + return rc; + +disable_soc: + cam_tfe_disable_soc_resources(soc_info); + tfe_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + +decrement_open_cnt: + mutex_lock(&tfe_hw->hw_mutex); + tfe_hw->open_count--; + mutex_unlock(&tfe_hw->hw_mutex); + return rc; +} + +int cam_tfe_deinit_hw(void *hw_priv, void *deinit_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_tfe_hw_core_info *core_info = NULL; + int rc = 0; + uint32_t reset_core_args = + CAM_TFE_HW_RESET_HW_AND_REG; + + CAM_DBG(CAM_ISP, "Enter"); + if (!hw_priv) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + soc_info = &tfe_hw->soc_info; + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + + mutex_lock(&tfe_hw->hw_mutex); + if (!tfe_hw->open_count) { + mutex_unlock(&tfe_hw->hw_mutex); + CAM_ERR_RATE_LIMIT(CAM_ISP, "TFE:%d Error Unbalanced deinit", + core_info->core_index); + return -EFAULT; + } + tfe_hw->open_count--; + if (tfe_hw->open_count) { + mutex_unlock(&tfe_hw->hw_mutex); + CAM_DBG(CAM_ISP, "TFE:%d open_cnt non-zero =%d", + core_info->core_index, tfe_hw->open_count); + return 0; + } + mutex_unlock(&tfe_hw->hw_mutex); + + rc = core_info->tfe_bus->hw_ops.deinit(core_info->tfe_bus->bus_priv, + NULL, 0); + if (rc) + CAM_ERR(CAM_ISP, "TFE:%d Bus HW deinit Failed rc=%d", + core_info->core_index, rc); + + rc = cam_tfe_reset(hw_priv, &reset_core_args, sizeof(uint32_t)); + + /* Turn OFF Regulators, Clocks and other SOC resources */ + CAM_DBG(CAM_ISP, "TFE:%d Disable SOC resource", core_info->core_index); + rc = cam_tfe_disable_soc_resources(soc_info); + if (rc) + CAM_ERR(CAM_ISP, " TFE:%d Disable SOC failed", + core_info->core_index); + + tfe_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +int cam_tfe_reserve(void *hw_priv, void *reserve_args, uint32_t arg_size) +{ + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_tfe_acquire_args *acquire; + int rc = -ENODEV; + + if (!hw_priv || !reserve_args || (arg_size != + sizeof(struct cam_tfe_acquire_args))) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + acquire = (struct cam_tfe_acquire_args *)reserve_args; + + CAM_DBG(CAM_ISP, "TFE:%d acquire res type: %d", + core_info->core_index, acquire->rsrc_type); + mutex_lock(&tfe_hw->hw_mutex); + if (acquire->rsrc_type == CAM_ISP_RESOURCE_TFE_IN) { + rc = cam_tfe_top_reserve(core_info->top_priv, + reserve_args, arg_size); + } else if (acquire->rsrc_type == CAM_ISP_RESOURCE_TFE_OUT) { + rc = core_info->tfe_bus->hw_ops.reserve( + core_info->tfe_bus->bus_priv, acquire, + sizeof(*acquire)); + } else { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res type:%d", + core_info->core_index, acquire->rsrc_type); + } + + mutex_unlock(&tfe_hw->hw_mutex); + + return rc; +} + + +int cam_tfe_release(void *hw_priv, void *release_args, uint32_t arg_size) +{ + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_isp_resource_node *isp_res; + int rc = -ENODEV; + + if (!hw_priv || !release_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + isp_res = (struct cam_isp_resource_node *) release_args; + + mutex_lock(&tfe_hw->hw_mutex); + if (isp_res->res_type == CAM_ISP_RESOURCE_TFE_IN) + rc = cam_tfe_top_release(core_info->top_priv, isp_res, + sizeof(*isp_res)); + else if (isp_res->res_type == CAM_ISP_RESOURCE_TFE_OUT) { + rc = core_info->tfe_bus->hw_ops.release( + core_info->tfe_bus->bus_priv, isp_res, + sizeof(*isp_res)); + } else { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res type:%d", + core_info->core_index, isp_res->res_type); + } + + mutex_unlock(&tfe_hw->hw_mutex); + + return rc; +} + +int cam_tfe_start(void *hw_priv, void *start_args, uint32_t arg_size) +{ + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_isp_resource_node *start_res; + + int rc = 0; + + if (!hw_priv || !start_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + start_res = (struct cam_isp_resource_node *)start_args; + core_info->tasklet_info = start_res->tasklet_info; + + mutex_lock(&tfe_hw->hw_mutex); + if (start_res->res_type == CAM_ISP_RESOURCE_TFE_IN) { + rc = cam_tfe_top_start(core_info, start_args, + arg_size); + if (rc) + CAM_ERR(CAM_ISP, "TFE:%d Start failed. type:%d", + core_info->core_index, start_res->res_type); + + } else if (start_res->res_type == CAM_ISP_RESOURCE_TFE_OUT) { + rc = core_info->tfe_bus->hw_ops.start(start_res, NULL, 0); + } else { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res type:%d", + core_info->core_index, start_res->res_type); + rc = -EFAULT; + } + + mutex_unlock(&tfe_hw->hw_mutex); + + return rc; +} + +int cam_tfe_stop(void *hw_priv, void *stop_args, uint32_t arg_size) +{ + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_isp_resource_node *isp_res; + int rc = -EINVAL; + + if (!hw_priv || !stop_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + isp_res = (struct cam_isp_resource_node *)stop_args; + + mutex_lock(&tfe_hw->hw_mutex); + if (isp_res->res_type == CAM_ISP_RESOURCE_TFE_IN) { + rc = cam_tfe_top_stop(core_info, isp_res, + sizeof(struct cam_isp_resource_node)); + } else if (isp_res->res_type == CAM_ISP_RESOURCE_TFE_OUT) { + rc = core_info->tfe_bus->hw_ops.stop(isp_res, NULL, 0); + } else { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res type:%d", + core_info->core_index, isp_res->res_type); + } + + CAM_DBG(CAM_ISP, "TFE:%d stopped res type:%d res id:%d res_state:%d ", + core_info->core_index, isp_res->res_type, + isp_res->res_id, isp_res->res_state); + + mutex_unlock(&tfe_hw->hw_mutex); + + return rc; +} + +int cam_tfe_read(void *hw_priv, void *read_args, uint32_t arg_size) +{ + return -EPERM; +} + +int cam_tfe_write(void *hw_priv, void *write_args, uint32_t arg_size) +{ + return -EPERM; +} + +int cam_tfe_process_cmd(void *hw_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_tfe_hw_info *hw_info = NULL; + int rc = 0; + + if (!hw_priv) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + soc_info = &tfe_hw->soc_info; + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + hw_info = core_info->tfe_hw_info; + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_CHANGE_BASE: + rc = cam_tfe_top_get_base(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_GET_REG_UPDATE: + rc = cam_tfe_top_get_reg_update(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_CLOCK_UPDATE: + rc = cam_tfe_top_clock_update(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_BW_UPDATE_V2: + rc = cam_tfe_top_bw_update(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_BW_CONTROL: + rc = cam_tfe_top_bw_control(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_GET_REG_DUMP: + rc = cam_tfe_top_get_reg_dump(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP: + rc = cam_tfe_camif_irq_reg_dump(core_info, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA: + *((struct cam_hw_soc_info **)cmd_args) = soc_info; + break; + case CAM_ISP_HW_CMD_DUMP_HW: + rc = cam_tfe_hw_dump(core_info, + cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_GET_BUF_UPDATE: + case CAM_ISP_HW_CMD_GET_HFR_UPDATE: + case CAM_ISP_HW_CMD_STRIPE_UPDATE: + case CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ: + case CAM_ISP_HW_CMD_GET_SECURE_MODE: + rc = core_info->tfe_bus->hw_ops.process_cmd( + core_info->tfe_bus->bus_priv, cmd_type, cmd_args, + arg_size); + break; + default: + CAM_ERR(CAM_ISP, "TFE:%d Invalid cmd type:%d", + core_info->core_index, cmd_type); + rc = -EINVAL; + break; + } + return rc; +} + +int cam_tfe_core_init(struct cam_tfe_hw_core_info *core_info, + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + struct cam_tfe_hw_info *tfe_hw_info) +{ + int rc = -EINVAL; + int i; + + if (!cam_cpas_is_feature_supported(CAM_CPAS_ISP_FUSE_ID, + hw_intf->hw_idx)) { + CAM_INFO(CAM_ISP, "TFE:%d is not supported", + hw_intf->hw_idx); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ISP, "TFE:%d is supported", + hw_intf->hw_idx); + + rc = cam_tfe_top_init(soc_info, hw_intf, tfe_hw_info->top_hw_info, + core_info); + if (rc) { + CAM_ERR(CAM_ISP, "TFE:%d Error cam_tfe_top_init failed", + core_info->core_index); + goto end; + } + + rc = cam_tfe_bus_init(soc_info, hw_intf, + tfe_hw_info->bus_hw_info, core_info, + &core_info->tfe_bus); + if (rc) { + CAM_ERR(CAM_ISP, "TFE:%d Error cam_tfe_bus_init failed", + core_info->core_index); + goto deinit_top; + } + + INIT_LIST_HEAD(&core_info->free_payload_list); + for (i = 0; i < CAM_TFE_EVT_MAX; i++) { + INIT_LIST_HEAD(&core_info->evt_payload[i].list); + list_add_tail(&core_info->evt_payload[i].list, + &core_info->free_payload_list); + } + + core_info->irq_err_config = false; + core_info->irq_err_config_cnt = 0; + spin_lock_init(&core_info->spin_lock); + init_completion(&core_info->reset_complete); + + return rc; + +deinit_top: + cam_tfe_top_deinit(core_info->top_priv); + +end: + return rc; +} + +int cam_tfe_core_deinit(struct cam_tfe_hw_core_info *core_info, + struct cam_tfe_hw_info *tfe_hw_info) +{ + int rc = -EINVAL; + int i; + unsigned long flags; + + spin_lock_irqsave(&core_info->spin_lock, flags); + + INIT_LIST_HEAD(&core_info->free_payload_list); + for (i = 0; i < CAM_TFE_EVT_MAX; i++) + INIT_LIST_HEAD(&core_info->evt_payload[i].list); + + rc = cam_tfe_bus_deinit(&core_info->tfe_bus); + if (rc) + CAM_ERR(CAM_ISP, "TFE:%d Error cam_tfe_bus_deinit failed rc=%d", + core_info->core_index, rc); + + rc = cam_tfe_top_deinit(core_info->top_priv); + kfree(core_info->top_priv); + core_info->top_priv = NULL; + + if (rc) + CAM_ERR(CAM_ISP, "Error cam_tfe_top_deinit failed rc=%d", rc); + + spin_unlock_irqrestore(&core_info->spin_lock, flags); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h new file mode 100644 index 0000000000000000000000000000000000000000..2418831d00c1d165aeb48a44f708059ccfa62718 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h @@ -0,0 +1,293 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + + +#ifndef _CAM_TFE_CORE_H_ +#define _CAM_TFE_CORE_H_ + +#include +#include "cam_hw_intf.h" +#include "cam_tfe_bus.h" +#include "cam_tfe_hw_intf.h" +#include "cam_tfe_irq.h" + +#define CAM_TFE_CAMIF_VER_1_0 0x10 +#define CAM_TFE_RDI_VER_1_0 0x1000 +#define CAM_TFE_TOP_1_0 0x1000 +#define CAM_TFE_TOP_IN_PORT_MAX 4 +#define CAM_TFE_RDI_MAX 4 + +#define CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS BIT(0) +#define CAM_TFE_EVT_MAX 256 + +#define CAM_TFE_MAX_REG_DUMP_ENTRIES 20 +#define CAM_TFE_MAX_LUT_DUMP_ENTRIES 10 + +#define CAM_TFE_MAX_CLC 30 +#define CAM_TFE_CLC_NAME_LENGTH_MAX 32 + +/*we take each word as uint32_t, for dumping uint64_t count as 2 words + * soc index + * clk_rate--> uint64_t--> count as 2 words + * BW--> uint64_t --> count as 2 words + * MAX_NIU + */ +#define CAM_TFE_CORE_DUMP_MISC_NUM_WORDS 4 + +enum cam_tfe_lut_word_size { + CAM_TFE_LUT_WORD_SIZE_32, + CAM_TFE_LUT_WORD_SIZE_64, + CAM_TFE_LUT_WORD_SIZE_MAX, +}; + +struct cam_tfe_reg_dump_entry { + uint32_t start_offset; + uint32_t end_offset; +}; + +struct cam_tfe_lut_dump_entry { + enum cam_tfe_lut_word_size lut_word_size; + uint32_t lut_bank_sel; + uint32_t lut_addr_size; + uint32_t dmi_reg_offset; +}; +struct cam_tfe_reg_dump_data { + uint32_t num_reg_dump_entries; + uint32_t num_lut_dump_entries; + uint32_t bus_start_addr; + uint32_t bus_write_top_end_addr; + uint32_t bus_client_start_addr; + uint32_t bus_client_offset; + uint32_t num_bus_clients; + struct cam_tfe_reg_dump_entry + reg_entry[CAM_TFE_MAX_REG_DUMP_ENTRIES]; + struct cam_tfe_lut_dump_entry + lut_entry[CAM_TFE_MAX_LUT_DUMP_ENTRIES]; +}; + +struct cam_tfe_top_reg_offset_common { + uint32_t hw_version; + uint32_t hw_capability; + uint32_t lens_feature; + uint32_t stats_feature; + uint32_t zoom_feature; + uint32_t global_reset_cmd; + uint32_t core_cgc_ctrl; + uint32_t ahb_cgc_ctrl; + uint32_t core_cfg_0; + uint32_t core_cfg_1; + uint32_t reg_update_cmd; + uint32_t diag_config; + uint32_t diag_sensor_status_0; + uint32_t diag_sensor_status_1; + uint32_t diag_sensor_frame_cnt_status; + uint32_t violation_status; + uint32_t stats_throttle_cnt_cfg_0; + uint32_t stats_throttle_cnt_cfg_1; + uint32_t debug_0; + uint32_t debug_1; + uint32_t debug_2; + uint32_t debug_3; + uint32_t debug_cfg; + uint32_t perf_cnt_cfg; + uint32_t perf_pixel_count; + uint32_t perf_line_count; + uint32_t perf_stall_count; + uint32_t perf_always_count; + uint32_t perf_count_status; +}; + +struct cam_tfe_camif_reg { + uint32_t hw_version; + uint32_t hw_status; + uint32_t module_cfg; + uint32_t pdaf_raw_crop_width_cfg; + uint32_t pdaf_raw_crop_height_cfg; + uint32_t line_skip_pattern; + uint32_t pixel_skip_pattern; + uint32_t period_cfg; + uint32_t irq_subsample_pattern; + uint32_t epoch_irq_cfg; + uint32_t debug_1; + uint32_t debug_0; + uint32_t test_bus_ctrl; + uint32_t spare; + uint32_t reg_update_cmd; +}; + +struct cam_tfe_camif_reg_data { + uint32_t extern_reg_update_mask; + uint32_t dual_tfe_pix_en_shift; + uint32_t extern_reg_update_shift; + uint32_t camif_pd_rdi2_src_sel_shift; + uint32_t dual_tfe_sync_sel_shift; + uint32_t delay_line_en_shift; + + uint32_t pixel_pattern_shift; + uint32_t pixel_pattern_mask; + uint32_t module_enable_shift; + uint32_t pix_out_enable_shift; + uint32_t pdaf_output_enable_shift; + + uint32_t dsp_mode_shift; + uint32_t dsp_mode_mask; + uint32_t dsp_en_shift; + uint32_t dsp_en_mask; + + uint32_t reg_update_cmd_data; + uint32_t epoch_line_cfg; + uint32_t sof_irq_mask; + uint32_t epoch0_irq_mask; + uint32_t epoch1_irq_mask; + uint32_t eof_irq_mask; + uint32_t reg_update_irq_mask; + uint32_t error_irq_mask0; + uint32_t error_irq_mask2; + uint32_t subscribe_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + + uint32_t enable_diagnostic_hw; + uint32_t perf_cnt_start_cmd_shift; + uint32_t perf_cnt_continuous_shift; + uint32_t perf_client_sel_shift; + uint32_t perf_window_start_shift; + uint32_t perf_window_end_shift; +}; + +struct cam_tfe_camif_hw_info { + struct cam_tfe_camif_reg *camif_reg; + struct cam_tfe_camif_reg_data *reg_data; +}; + +struct cam_tfe_rdi_reg { + uint32_t rdi_hw_version; + uint32_t rdi_hw_status; + uint32_t rdi_module_config; + uint32_t rdi_skip_period; + uint32_t rdi_irq_subsample_pattern; + uint32_t rdi_epoch_irq; + uint32_t rdi_debug_1; + uint32_t rdi_debug_0; + uint32_t rdi_test_bus_ctrl; + uint32_t rdi_spare; + uint32_t reg_update_cmd; +}; + +struct cam_tfe_rdi_reg_data { + uint32_t reg_update_cmd_data; + uint32_t epoch_line_cfg; + + uint32_t pixel_pattern_shift; + uint32_t pixel_pattern_mask; + uint32_t rdi_out_enable_shift; + + uint32_t sof_irq_mask; + uint32_t epoch0_irq_mask; + uint32_t epoch1_irq_mask; + uint32_t eof_irq_mask; + uint32_t error_irq_mask0; + uint32_t error_irq_mask2; + uint32_t subscribe_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t enable_diagnostic_hw; +}; + +struct cam_tfe_clc_hw_status { + uint8_t name[CAM_TFE_CLC_NAME_LENGTH_MAX]; + uint32_t hw_status_reg; +}; + +struct cam_tfe_rdi_hw_info { + struct cam_tfe_rdi_reg *rdi_reg; + struct cam_tfe_rdi_reg_data *reg_data; +}; + +struct cam_tfe_top_hw_info { + struct cam_tfe_top_reg_offset_common *common_reg; + struct cam_tfe_camif_hw_info camif_hw_info; + struct cam_tfe_rdi_hw_info rdi_hw_info[CAM_TFE_RDI_MAX]; + uint32_t in_port[CAM_TFE_TOP_IN_PORT_MAX]; + struct cam_tfe_reg_dump_data reg_dump_data; +}; + +struct cam_tfe_hw_info { + uint32_t top_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t top_irq_clear[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t top_irq_status[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t top_irq_cmd; + uint32_t global_clear_bitmask; + + uint32_t bus_irq_mask[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; + uint32_t bus_irq_clear[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; + uint32_t bus_irq_status[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; + uint32_t bus_irq_cmd; + + uint32_t bus_violation_reg; + uint32_t bus_overflow_reg; + uint32_t bus_image_size_vilation_reg; + uint32_t bus_overflow_clear_cmd; + uint32_t debug_status_top; + + uint32_t reset_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t error_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t bus_reg_irq_mask[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; + uint32_t bus_error_irq_mask[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; + + uint32_t num_clc; + struct cam_tfe_clc_hw_status *clc_hw_status_info; + + uint32_t top_version; + void *top_hw_info; + + uint32_t bus_version; + void *bus_hw_info; +}; + +struct cam_tfe_hw_core_info { + uint32_t core_index; + struct cam_tfe_hw_info *tfe_hw_info; + void *top_priv; + struct cam_tfe_bus *tfe_bus; + void *tasklet_info; + struct cam_tfe_irq_evt_payload evt_payload[CAM_TFE_EVT_MAX]; + struct list_head free_payload_list; + bool irq_err_config; + uint32_t irq_err_config_cnt; + spinlock_t spin_lock; + struct completion reset_complete; +}; + +int cam_tfe_get_hw_caps(void *device_priv, + void *get_hw_cap_args, uint32_t arg_size); +int cam_tfe_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_tfe_deinit_hw(void *hw_priv, + void *deinit_hw_args, uint32_t arg_size); +int cam_tfe_reset(void *device_priv, + void *reset_core_args, uint32_t arg_size); +int cam_tfe_reserve(void *device_priv, + void *reserve_args, uint32_t arg_size); +int cam_tfe_release(void *device_priv, + void *reserve_args, uint32_t arg_size); +int cam_tfe_start(void *device_priv, + void *start_args, uint32_t arg_size); +int cam_tfe_stop(void *device_priv, + void *stop_args, uint32_t arg_size); +int cam_tfe_read(void *device_priv, + void *read_args, uint32_t arg_size); +int cam_tfe_write(void *device_priv, + void *write_args, uint32_t arg_size); +int cam_tfe_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size); + +irqreturn_t cam_tfe_irq(int irq_num, void *data); + +int cam_tfe_core_init(struct cam_tfe_hw_core_info *core_info, + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + struct cam_tfe_hw_info *tfe_hw_info); + +int cam_tfe_core_deinit(struct cam_tfe_hw_core_info *core_info, + struct cam_tfe_hw_info *tfe_hw_info); + +#endif /* _CAM_TFE_CORE_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..6666e295552348eed68ea74c0629dbae5fc887d3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include "cam_tfe_dev.h" +#include "cam_tfe_core.h" +#include "cam_tfe_soc.h" +#include "cam_debug_util.h" + +static struct cam_hw_intf *cam_tfe_hw_list[CAM_TFE_HW_NUM_MAX] = {0, 0, 0}; + +static char tfe_dev_name[8]; + +int cam_tfe_probe(struct platform_device *pdev) +{ + struct cam_hw_info *tfe_hw = NULL; + struct cam_hw_intf *tfe_hw_intf = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_tfe_hw_info *hw_info = NULL; + int rc = 0; + + tfe_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!tfe_hw_intf) { + rc = -ENOMEM; + goto end; + } + + of_property_read_u32(pdev->dev.of_node, + "cell-index", &tfe_hw_intf->hw_idx); + + tfe_hw = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!tfe_hw) { + rc = -ENOMEM; + goto free_tfe_hw_intf; + } + + memset(tfe_dev_name, 0, sizeof(tfe_dev_name)); + snprintf(tfe_dev_name, sizeof(tfe_dev_name), + "tfe%1u", tfe_hw_intf->hw_idx); + + tfe_hw->soc_info.pdev = pdev; + tfe_hw->soc_info.dev = &pdev->dev; + tfe_hw->soc_info.dev_name = tfe_dev_name; + tfe_hw_intf->hw_priv = tfe_hw; + tfe_hw_intf->hw_ops.get_hw_caps = cam_tfe_get_hw_caps; + tfe_hw_intf->hw_ops.init = cam_tfe_init_hw; + tfe_hw_intf->hw_ops.deinit = cam_tfe_deinit_hw; + tfe_hw_intf->hw_ops.reset = cam_tfe_reset; + tfe_hw_intf->hw_ops.reserve = cam_tfe_reserve; + tfe_hw_intf->hw_ops.release = cam_tfe_release; + tfe_hw_intf->hw_ops.start = cam_tfe_start; + tfe_hw_intf->hw_ops.stop = cam_tfe_stop; + tfe_hw_intf->hw_ops.read = cam_tfe_read; + tfe_hw_intf->hw_ops.write = cam_tfe_write; + tfe_hw_intf->hw_ops.process_cmd = cam_tfe_process_cmd; + tfe_hw_intf->hw_type = CAM_ISP_HW_TYPE_TFE; + + CAM_DBG(CAM_ISP, "type %d index %d", + tfe_hw_intf->hw_type, tfe_hw_intf->hw_idx); + + platform_set_drvdata(pdev, tfe_hw_intf); + + tfe_hw->core_info = kzalloc(sizeof(struct cam_tfe_hw_core_info), + GFP_KERNEL); + if (!tfe_hw->core_info) { + CAM_DBG(CAM_ISP, "Failed to alloc for core"); + rc = -ENOMEM; + goto free_tfe_hw; + } + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_ISP, "Of_match Failed"); + rc = -EINVAL; + goto free_core_info; + } + hw_info = (struct cam_tfe_hw_info *)match_dev->data; + core_info->tfe_hw_info = hw_info; + core_info->core_index = tfe_hw_intf->hw_idx; + + rc = cam_tfe_init_soc_resources(&tfe_hw->soc_info, cam_tfe_irq, + tfe_hw); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Failed to init soc rc=%d", rc); + goto free_core_info; + } + + rc = cam_tfe_core_init(core_info, &tfe_hw->soc_info, + tfe_hw_intf, hw_info); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Failed to init core rc=%d", rc); + goto deinit_soc; + } + + tfe_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + mutex_init(&tfe_hw->hw_mutex); + spin_lock_init(&tfe_hw->hw_lock); + init_completion(&tfe_hw->hw_complete); + + if (tfe_hw_intf->hw_idx < CAM_TFE_HW_NUM_MAX) + cam_tfe_hw_list[tfe_hw_intf->hw_idx] = tfe_hw_intf; + + cam_tfe_init_hw(tfe_hw, NULL, 0); + cam_tfe_deinit_hw(tfe_hw, NULL, 0); + + CAM_DBG(CAM_ISP, "TFE%d probe successful", tfe_hw_intf->hw_idx); + + return rc; + +deinit_soc: + if (cam_tfe_deinit_soc_resources(&tfe_hw->soc_info)) + CAM_ERR(CAM_ISP, "Failed to deinit soc"); +free_core_info: + kfree(tfe_hw->core_info); +free_tfe_hw: + kfree(tfe_hw); +free_tfe_hw_intf: + kfree(tfe_hw_intf); +end: + return rc; +} + +int cam_tfe_remove(struct platform_device *pdev) +{ + struct cam_hw_info *tfe_hw = NULL; + struct cam_hw_intf *tfe_hw_intf = NULL; + struct cam_tfe_hw_core_info *core_info = NULL; + int rc = 0; + + tfe_hw_intf = platform_get_drvdata(pdev); + if (!tfe_hw_intf) { + CAM_ERR(CAM_ISP, "Error! No data in pdev"); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "type %d index %d", + tfe_hw_intf->hw_type, tfe_hw_intf->hw_idx); + + if (tfe_hw_intf->hw_idx < CAM_TFE_HW_NUM_MAX) + cam_tfe_hw_list[tfe_hw_intf->hw_idx] = NULL; + + tfe_hw = tfe_hw_intf->hw_priv; + if (!tfe_hw) { + CAM_ERR(CAM_ISP, "Error! HW data is NULL"); + rc = -ENODEV; + goto free_tfe_hw_intf; + } + + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + if (!core_info) { + CAM_ERR(CAM_ISP, "Error! core data NULL"); + rc = -EINVAL; + goto deinit_soc; + } + + rc = cam_tfe_core_deinit(core_info, core_info->tfe_hw_info); + if (rc < 0) + CAM_ERR(CAM_ISP, "Failed to deinit core rc=%d", rc); + + kfree(tfe_hw->core_info); + +deinit_soc: + rc = cam_tfe_deinit_soc_resources(&tfe_hw->soc_info); + if (rc < 0) + CAM_ERR(CAM_ISP, "Failed to deinit soc rc=%d", rc); + + mutex_destroy(&tfe_hw->hw_mutex); + kfree(tfe_hw); + + CAM_DBG(CAM_ISP, "TFE%d remove successful", tfe_hw_intf->hw_idx); + +free_tfe_hw_intf: + kfree(tfe_hw_intf); + + return rc; +} + +int cam_tfe_hw_init(struct cam_hw_intf **tfe_hw, uint32_t hw_idx) +{ + int rc = 0; + + if (cam_tfe_hw_list[hw_idx]) { + *tfe_hw = cam_tfe_hw_list[hw_idx]; + rc = 0; + } else { + *tfe_hw = NULL; + rc = -ENODEV; + } + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..41816285a611a91906a20da8e46363a689902091 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_DEV_H_ +#define _CAM_TFE_DEV_H_ + +#include + +/* + * cam_tfe_probe() + * + * @brief: Driver probe function called on Boot + * + * @pdev: Platform Device pointer + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_probe(struct platform_device *pdev); + +/* + * cam_tfe_remove() + * + * @brief: Driver remove function + * + * @pdev: Platform Device pointer + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_remove(struct platform_device *pdev); + +#endif /* _CAM_TFE_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_irq.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_irq.h new file mode 100644 index 0000000000000000000000000000000000000000..4b77f0eb2a251997d8f1bab20c2c6694879d63a2 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_irq.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_IRQ_H_ +#define _CAM_TFE_IRQ_H_ + +#include + +#define CAM_TFE_TOP_IRQ_REG_NUM 3 + +/* + * cam_tfe_irq_config() + * + * @brief: Tfe hw irq configuration + * + * @tfe_core_data: tfe core pointer + * @irq_mask: Irq mask for enable interrupts or disable + * @num_reg: Number irq mask registers + * @enable: enable = 1, enable the given irq mask interrupts + * enable = 0 disable the given irq mask interrupts + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_irq_config(void *tfe_core_data, + uint32_t *irq_mask, uint32_t num_reg, bool enable); + + +#endif /* _CAM_TFE_IRQ_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..267c2c0755ad9eb06622716ca1736e4a7847fb75 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_cpas_api.h" +#include "cam_tfe_soc.h" +#include "cam_debug_util.h" + +static bool cam_tfe_cpas_cb(uint32_t client_handle, void *userdata, + struct cam_cpas_irq_data *irq_data) +{ + bool error_handled = false; + + if (!irq_data) + return error_handled; + + CAM_DBG(CAM_ISP, "CPSS error type=%d ", + irq_data->irq_type); + + return error_handled; +} + +int cam_tfe_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t tfe_irq_handler, void *irq_data) +{ + int rc = 0; + struct cam_tfe_soc_private *soc_private; + struct cam_cpas_register_params cpas_register_param; + + soc_private = kzalloc(sizeof(struct cam_tfe_soc_private), + GFP_KERNEL); + if (!soc_private) { + CAM_DBG(CAM_ISP, "Error! soc_private Alloc Failed"); + return -ENOMEM; + } + soc_info->soc_private = soc_private; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc) { + CAM_ERR(CAM_ISP, "Error! get DT properties failed rc=%d", rc); + goto free_soc_private; + } + + rc = cam_soc_util_get_option_clk_by_name(soc_info, + CAM_TFE_DSP_CLK_NAME, &soc_private->dsp_clk, + &soc_private->dsp_clk_index, &soc_private->dsp_clk_rate); + if (rc) + CAM_WARN(CAM_ISP, "Option clk get failed with rc %d", rc); + + rc = cam_soc_util_request_platform_resource(soc_info, tfe_irq_handler, + irq_data); + + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Error! Request platform resources failed rc=%d", rc); + goto free_soc_private; + } + + memset(&cpas_register_param, 0, sizeof(cpas_register_param)); + strlcpy(cpas_register_param.identifier, "tfe", + CAM_HW_IDENTIFIER_LENGTH); + cpas_register_param.cell_index = soc_info->index; + cpas_register_param.dev = soc_info->dev; + cpas_register_param.cam_cpas_client_cb = cam_tfe_cpas_cb; + cpas_register_param.userdata = soc_info; + rc = cam_cpas_register_client(&cpas_register_param); + if (rc) { + CAM_ERR(CAM_ISP, "CPAS registration failed rc=%d", rc); + goto release_soc; + } + + soc_private->cpas_handle = cpas_register_param.client_handle; + + return rc; + +release_soc: + cam_soc_util_release_platform_resource(soc_info); +free_soc_private: + kfree(soc_private); + + return rc; +} + +int cam_tfe_deinit_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_tfe_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error! soc_info NULL"); + return -ENODEV; + } + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error! soc_private NULL"); + return -ENODEV; + } + rc = cam_cpas_unregister_client(soc_private->cpas_handle); + if (rc) + CAM_ERR(CAM_ISP, "CPAS0 unregistration failed rc=%d", rc); + + rc = cam_soc_util_release_platform_resource(soc_info); + if (rc) + CAM_ERR(CAM_ISP, + "Error! Release platform resource failed rc=%d", rc); + + + rc = cam_soc_util_clk_put(&soc_private->dsp_clk); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Error Put dsp clk failed rc=%d", rc); + + kfree(soc_private); + + return rc; +} + +int cam_tfe_enable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_tfe_soc_private *soc_private; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error! Invalid params"); + rc = -EINVAL; + goto end; + } + soc_private = soc_info->soc_private; + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_SVS_VOTE; + axi_vote.num_paths = 1; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_IFE_VID; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_WRITE; + axi_vote.axi_path[0].camnoc_bw = 10640000000L; + axi_vote.axi_path[0].mnoc_ab_bw = 10640000000L; + axi_vote.axi_path[0].mnoc_ib_bw = 10640000000L; + + rc = cam_cpas_start(soc_private->cpas_handle, &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_ISP, "Error! CPAS0 start failed rc=%d", rc); + rc = -EFAULT; + goto end; + } + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_TURBO_VOTE, true); + if (rc) { + CAM_ERR(CAM_ISP, "Error! enable platform failed rc=%d", rc); + goto stop_cpas; + } + + return rc; + +stop_cpas: + cam_cpas_stop(soc_private->cpas_handle); +end: + return rc; +} + +int cam_tfe_soc_enable_clk(struct cam_hw_soc_info *soc_info, + const char *clk_name) +{ + int rc = 0; + struct cam_tfe_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + rc = -EINVAL; + return rc; + } + soc_private = soc_info->soc_private; + + if (strcmp(clk_name, CAM_TFE_DSP_CLK_NAME) == 0) { + rc = cam_soc_util_clk_enable(soc_private->dsp_clk, + CAM_TFE_DSP_CLK_NAME, soc_private->dsp_clk_rate); + if (rc) + CAM_ERR(CAM_ISP, + "Error enable dsp clk failed rc=%d", rc); + } + + return rc; +} + +int cam_tfe_soc_disable_clk(struct cam_hw_soc_info *soc_info, + const char *clk_name) +{ + int rc = 0; + struct cam_tfe_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + rc = -EINVAL; + return rc; + } + soc_private = soc_info->soc_private; + + if (strcmp(clk_name, CAM_TFE_DSP_CLK_NAME) == 0) { + rc = cam_soc_util_clk_disable(soc_private->dsp_clk, + CAM_TFE_DSP_CLK_NAME); + if (rc) + CAM_ERR(CAM_ISP, + "Error enable dsp clk failed rc=%d", rc); + } + + return rc; +} + + +int cam_tfe_disable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_tfe_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error! Invalid params"); + rc = -EINVAL; + return rc; + } + soc_private = soc_info->soc_private; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) { + CAM_ERR(CAM_ISP, "Disable platform failed rc=%d", rc); + return rc; + } + + rc = cam_cpas_stop(soc_private->cpas_handle); + if (rc) { + CAM_ERR(CAM_ISP, "Error! CPAS stop failed rc=%d", rc); + return rc; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..2e6e47d8561d79d768f0bc6cf66cb74ff3d176b7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_SOC_H_ +#define _CAM_TFE_SOC_H_ + +#include "cam_soc_util.h" +#include "cam_isp_hw.h" + +#define CAM_TFE_DSP_CLK_NAME "tfe_dsp_clk" + +enum cam_cpas_handle_id { + CAM_CPAS_HANDLE_CAMIF, + CAM_CPAS_HANDLE_RAW, + CAM_CPAS_HANDLE_MAX, +}; + +/* + * struct cam_tfe_soc_private: + * + * @Brief: Private SOC data specific to TFE HW Driver + * + * @cpas_handle: Handle returned on registering with CPAS driver. + * This handle is used for all further interface + * with CPAS. + * @cpas_version: Has cpas version read from Hardware + */ +struct cam_tfe_soc_private { + uint32_t cpas_handle; + uint32_t cpas_version; + struct clk *dsp_clk; + int32_t dsp_clk_index; + int32_t dsp_clk_rate; +}; + +/* + * cam_tfe_init_soc_resources() + * + * @Brief: Initialize SOC resources including private data + * + * @soc_info: Device soc information + * @handler: Irq handler function pointer + * @irq_data: Irq handler function Callback data + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t tfe_irq_handler, void *irq_data); + +/* + * cam_tfe_deinit_soc_resources() + * + * @Brief: Deinitialize SOC resources including private data + * + * @soc_info: Device soc information + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_deinit_soc_resources(struct cam_hw_soc_info *soc_info); + +/* + * cam_tfe_enable_soc_resources() + * + * @brief: Enable regulator, irq resources, start CPAS + * + * @soc_info: Device soc information + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_enable_soc_resources(struct cam_hw_soc_info *soc_info); + +/* + * cam_tfe_disable_soc_resources() + * + * @brief: Disable regulator, irq resources, stop CPAS + * + * @soc_info: Device soc information + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_disable_soc_resources(struct cam_hw_soc_info *soc_info); + +/* + * cam_tfe_soc_enable_clk() + * + * @brief: Enable clock with given name + * + * @soc_info: Device soc information + * @clk_name: Name of clock to enable + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_soc_enable_clk(struct cam_hw_soc_info *soc_info, + const char *clk_name); + +/* + * cam_tfe_soc_disable_dsp_clk() + * + * @brief: Disable clock with given name + * + * @soc_info: Device soc information + * @clk_name: Name of clock to enable + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_soc_disable_clk(struct cam_hw_soc_info *soc_info, + const char *clk_name); + +#endif /* _CAM_TFE_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..295eb696b595c703408d3d47be8c1386bef6e801 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_top_tpg_dev.o cam_top_tpg_soc.o cam_top_tpg_core.o +obj-$(CONFIG_SPECTRA_CAMERA) += cam_top_tpg_v1.o \ No newline at end of file diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c new file mode 100644 index 0000000000000000000000000000000000000000..7322301f69be1c20ed511f6a343269b4e4456722 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c @@ -0,0 +1,767 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "cam_top_tpg_core.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" + + +static uint32_t tpg_num_dt_map[CAM_TOP_TPG_MAX_SUPPORTED_DT] = { + 0, + 3, + 1, + 2 +}; + +static int cam_top_tpg_get_format(uint32_t in_format, + uint32_t *tpg_encode_format) +{ + int rc = 0; + + switch (in_format) { + case CAM_FORMAT_MIPI_RAW_6: + *tpg_encode_format = 0; + break; + case CAM_FORMAT_MIPI_RAW_8: + *tpg_encode_format = 1; + break; + case CAM_FORMAT_MIPI_RAW_10: + *tpg_encode_format = 2; + break; + case CAM_FORMAT_MIPI_RAW_12: + *tpg_encode_format = 3; + break; + case CAM_FORMAT_MIPI_RAW_14: + *tpg_encode_format = 4; + break; + case CAM_FORMAT_MIPI_RAW_16: + *tpg_encode_format = 4; + break; + default: + CAM_ERR(CAM_ISP, "Unsupported input encode format %d", + in_format); + rc = -EINVAL; + } + return rc; +} + +static int cam_top_tpg_get_hw_caps(void *hw_priv, + void *get_hw_cap_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw_caps *hw_caps; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + + if (!hw_priv || !get_hw_cap_args) { + CAM_ERR(CAM_ISP, "TPG: Invalid args"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + hw_caps = (struct cam_top_tpg_hw_caps *) get_hw_cap_args; + + hw_caps->major_version = tpg_hw->tpg_info->tpg_reg->major_version; + hw_caps->minor_version = tpg_hw->tpg_info->tpg_reg->minor_version; + hw_caps->version_incr = tpg_hw->tpg_info->tpg_reg->version_incr; + + CAM_DBG(CAM_ISP, + "TPG:%d major:%d minor:%d ver :%d", + tpg_hw->hw_intf->hw_idx, hw_caps->major_version, + hw_caps->minor_version, hw_caps->version_incr); + + return rc; +} + +static int cam_top_tpg_reserve(void *hw_priv, + void *reserve_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + struct cam_top_tpg_hw_reserve_resource_args *reserv; + struct cam_top_tpg_cfg *tpg_data; + uint32_t encode_format = 0; + uint32_t i; + + if (!hw_priv || !reserve_args || (arg_size != + sizeof(struct cam_top_tpg_hw_reserve_resource_args))) { + CAM_ERR(CAM_ISP, "TPG: Invalid args"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + reserv = (struct cam_top_tpg_hw_reserve_resource_args *)reserve_args; + + if (reserv->num_inport <= 0 || + reserv->num_inport > CAM_TOP_TPG_MAX_SUPPORTED_DT) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "TPG: %u invalid input num port:%d", + tpg_hw->hw_intf->hw_idx, reserv->num_inport); + return -EINVAL; + } + + mutex_lock(&tpg_hw->hw_info->hw_mutex); + if (tpg_hw->tpg_res.res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return -EINVAL; + } + + if ((reserv->in_port[0]->vc > 0xF) || + (reserv->in_port[0]->lane_num <= 0 || + reserv->in_port[0]->lane_num > 4) || + (reserv->in_port[0]->pix_pattern > 4) || + (reserv->in_port[0]->lane_type >= 2)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "TPG:%u invalid input %d %d %d %d", + tpg_hw->hw_intf->hw_idx, reserv->in_port[0]->vc, + reserv->in_port[0]->lane_num, + reserv->in_port[0]->pix_pattern, + reserv->in_port[0]->lane_type); + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return -EINVAL; + } + rc = cam_top_tpg_get_format(reserv->in_port[0]->format, + &encode_format); + if (rc) + return rc; + + CAM_DBG(CAM_ISP, "TPG: %u enter", tpg_hw->hw_intf->hw_idx); + + tpg_data = (struct cam_top_tpg_cfg *)tpg_hw->tpg_res.res_priv; + tpg_data->vc_num = reserv->in_port[0]->vc; + tpg_data->phy_sel = reserv->in_port[0]->lane_type; + tpg_data->num_active_lanes = reserv->in_port[0]->lane_num; + tpg_data->h_blank_count = reserv->in_port[0]->sensor_hbi; + tpg_data->v_blank_count = reserv->in_port[0]->sensor_vbi; + tpg_data->pix_pattern = reserv->in_port[0]->pix_pattern; + tpg_data->dt_cfg[0].data_type = reserv->in_port[0]->dt; + tpg_data->dt_cfg[0].frame_height = reserv->in_port[0]->height; + if (reserv->in_port[0]->usage_type) + tpg_data->dt_cfg[0].frame_width = + ((reserv->in_port[0]->right_end - + reserv->in_port[0]->left_start) + 1); + else + tpg_data->dt_cfg[0].frame_width = + reserv->in_port[0]->left_width; + tpg_data->dt_cfg[0].encode_format = encode_format; + tpg_data->num_active_dts = 1; + + CAM_DBG(CAM_ISP, + "TPG:%u vc_num:%d dt:%d phy:%d lines:%d pattern:%d format:%d", + tpg_hw->hw_intf->hw_idx, + tpg_data->vc_num, tpg_data->dt_cfg[0].data_type, + tpg_data->phy_sel, tpg_data->num_active_lanes, + tpg_data->pix_pattern, + tpg_data->dt_cfg[0].encode_format); + + CAM_DBG(CAM_ISP, "TPG:%u height:%d width:%d h blank:%d v blank:%d", + tpg_hw->hw_intf->hw_idx, + tpg_data->dt_cfg[0].frame_height, + tpg_data->dt_cfg[0].frame_width, + tpg_data->h_blank_count, + tpg_data->v_blank_count); + + if (reserv->num_inport == 1) + goto end; + + for (i = 1; i < reserv->num_inport; i++) { + if ((tpg_data->vc_num != reserv->in_port[i]->vc) || + (tpg_data->phy_sel != reserv->in_port[i]->lane_type) || + (tpg_data->num_active_lanes != + reserv->in_port[i]->lane_num) || + (tpg_data->pix_pattern != + reserv->in_port[i]->pix_pattern)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "TPG: %u invalid DT config for tpg", + tpg_hw->hw_intf->hw_idx); + rc = -EINVAL; + goto error; + } + rc = cam_top_tpg_get_format(reserv->in_port[0]->format, + &encode_format); + if (rc) + return rc; + + tpg_data->dt_cfg[i].data_type = reserv->in_port[i]->dt; + tpg_data->dt_cfg[i].frame_height = + reserv->in_port[i]->height; + tpg_data->dt_cfg[i].frame_width = + reserv->in_port[i]->left_width; + tpg_data->dt_cfg[i].encode_format = encode_format; + tpg_data->num_active_dts++; + + CAM_DBG(CAM_ISP, "TPG:%u height:%d width:%d dt:%d format:%d", + tpg_hw->hw_intf->hw_idx, + tpg_data->dt_cfg[i].frame_height, + tpg_data->dt_cfg[i].frame_width, + tpg_data->dt_cfg[i].data_type, + tpg_data->dt_cfg[i].encode_format); + + } +end: + reserv->node_res = &tpg_hw->tpg_res; + tpg_hw->tpg_res.res_state = CAM_ISP_RESOURCE_STATE_RESERVED; +error: + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + CAM_DBG(CAM_ISP, "exit rc %u", rc); + + return rc; +} + +static int cam_top_tpg_release(void *hw_priv, + void *release_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + struct cam_top_tpg_cfg *tpg_data; + struct cam_isp_resource_node *tpg_res; + + if (!hw_priv || !release_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "TPG: Invalid args"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + tpg_res = (struct cam_isp_resource_node *)release_args; + + mutex_lock(&tpg_hw->hw_info->hw_mutex); + if ((tpg_res->res_type != CAM_ISP_RESOURCE_TPG) || + (tpg_res->res_state <= CAM_ISP_RESOURCE_STATE_AVAILABLE)) { + CAM_ERR(CAM_ISP, "TPG:%d Invalid res type:%d res_state:%d", + tpg_hw->hw_intf->hw_idx, tpg_res->res_type, + tpg_res->res_state); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ISP, "TPG:%d res type :%d", + tpg_hw->hw_intf->hw_idx, tpg_res->res_type); + + tpg_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + tpg_data = (struct cam_top_tpg_cfg *)tpg_res->res_priv; + memset(tpg_data, 0, sizeof(struct cam_top_tpg_cfg)); + +end: + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_top_tpg_init_hw(void *hw_priv, + void *init_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + struct cam_isp_resource_node *tpg_res; + const struct cam_top_tpg_reg_offset *tpg_reg; + struct cam_hw_soc_info *soc_info; + uint32_t val, clk_lvl; + + if (!hw_priv || !init_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "TPG: Invalid args"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + tpg_res = (struct cam_isp_resource_node *)init_args; + tpg_reg = tpg_hw->tpg_info->tpg_reg; + soc_info = &tpg_hw->hw_info->soc_info; + + if (tpg_res->res_type != CAM_ISP_RESOURCE_TPG) { + CAM_ERR(CAM_ISP, "TPG:%d Invalid res type state %d", + tpg_hw->hw_intf->hw_idx, + tpg_res->res_type); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "TPG:%d init HW res type :%d", + tpg_hw->hw_intf->hw_idx, tpg_res->res_type); + mutex_lock(&tpg_hw->hw_info->hw_mutex); + /* overflow check before increment */ + if (tpg_hw->hw_info->open_count == UINT_MAX) { + CAM_ERR(CAM_ISP, "TPG:%d Open count reached max", + tpg_hw->hw_intf->hw_idx); + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return -EINVAL; + } + + /* Increment ref Count */ + tpg_hw->hw_info->open_count++; + if (tpg_hw->hw_info->open_count > 1) { + CAM_DBG(CAM_ISP, "TPG hw has already been enabled"); + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return rc; + } + + rc = cam_soc_util_get_clk_level(soc_info, tpg_hw->clk_rate, + soc_info->src_clk_idx, &clk_lvl); + CAM_DBG(CAM_ISP, "TPG phy clock level %u", clk_lvl); + + rc = cam_top_tpg_enable_soc_resources(soc_info, clk_lvl); + if (rc) { + CAM_ERR(CAM_ISP, "TPG:%d Enable SOC failed", + tpg_hw->hw_intf->hw_idx); + goto err; + } + + tpg_hw->hw_info->hw_state = CAM_HW_STATE_POWER_UP; + + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + tpg_reg->tpg_hw_version); + CAM_DBG(CAM_ISP, "TPG:%d TPG HW version: 0x%x", + tpg_hw->hw_intf->hw_idx, val); + + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return rc; + +err: + tpg_hw->hw_info->open_count--; + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_top_tpg_deinit_hw(void *hw_priv, + void *deinit_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + struct cam_isp_resource_node *tpg_res; + struct cam_hw_soc_info *soc_info; + + if (!hw_priv || !deinit_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "TPG:Invalid arguments"); + return -EINVAL; + } + + tpg_res = (struct cam_isp_resource_node *)deinit_args; + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + + if (tpg_res->res_type != CAM_ISP_RESOURCE_TPG) { + CAM_ERR(CAM_ISP, "TPG:%d Invalid Res type %d", + tpg_hw->hw_intf->hw_idx, + tpg_res->res_type); + return -EINVAL; + } + + mutex_lock(&tpg_hw->hw_info->hw_mutex); + /* Check for refcount */ + if (!tpg_hw->hw_info->open_count) { + CAM_WARN(CAM_ISP, "Unbalanced disable_hw"); + goto end; + } + + /* Decrement ref Count */ + tpg_hw->hw_info->open_count--; + if (tpg_hw->hw_info->open_count) { + rc = 0; + goto end; + } + + soc_info = &tpg_hw->hw_info->soc_info; + rc = cam_top_tpg_disable_soc_resources(soc_info); + if (rc) + CAM_ERR(CAM_ISP, "TPG:%d Disable SOC failed", + tpg_hw->hw_intf->hw_idx); + + tpg_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; + CAM_DBG(CAM_ISP, "TPG:%d deint completed", tpg_hw->hw_intf->hw_idx); + +end: + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_top_tpg_start(void *hw_priv, void *start_args, + uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + struct cam_hw_soc_info *soc_info; + struct cam_isp_resource_node *tpg_res; + const struct cam_top_tpg_reg_offset *tpg_reg; + struct cam_top_tpg_cfg *tpg_data; + uint32_t i, val; + uint32_t in_format = 0; + + if (!hw_priv || !start_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "TPG: Invalid args"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + tpg_reg = tpg_hw->tpg_info->tpg_reg; + tpg_res = (struct cam_isp_resource_node *)start_args; + tpg_data = (struct cam_top_tpg_cfg *)tpg_res->res_priv; + soc_info = &tpg_hw->hw_info->soc_info; + + if ((tpg_res->res_type != CAM_ISP_RESOURCE_TPG) || + (tpg_res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED)) { + CAM_ERR(CAM_ISP, "TPG:%d Invalid Res type:%d res_state:%d", + tpg_hw->hw_intf->hw_idx, + tpg_res->res_type, tpg_res->res_state); + rc = -EINVAL; + goto end; + } + cam_io_w_mb(0x12345678, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_lfsr_seed); + + for (i = 0; i < tpg_data->num_active_dts; i++) { + val = (((tpg_data->dt_cfg[i].frame_width & 0xFFFF) << 16) | + (tpg_data->dt_cfg[i].frame_height & 0x3FFF)); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_dt_0_cfg_0 + 0x10 * i); + cam_io_w_mb(tpg_data->dt_cfg[i].data_type, + soc_info->reg_map[0].mem_base + + tpg_reg->tpg_dt_0_cfg_1 + 0x10 * i); + val = ((tpg_data->dt_cfg[i].encode_format & 0xF) << + tpg_reg->tpg_dt_encode_format_shift) | + tpg_reg->tpg_payload_mode_color; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_dt_0_cfg_2 + 0x10 * i); + } + + val = (tpg_num_dt_map[tpg_data->num_active_dts-1] << + tpg_reg->tpg_num_dts_shift_val) | tpg_data->vc_num; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg0); + + /* + * if hblank is notset configureHBlank count 500 and + * V blank count is 600 + */ + + if (tpg_data->h_blank_count) + cam_io_w_mb(tpg_data->h_blank_count, + soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg1); + else + cam_io_w_mb(0x2581F4, + soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg1); + + /* configure tpg pattern */ + in_format = tpg_data->dt_cfg[0].encode_format & 0xF; + val = in_format << tpg_reg->tpg_dt_encode_format_shift; + + switch (tpg_hw->tpg_pattern) { + case 0x0: + val = val | tpg_hw->tpg_pattern; + break; + case 0x1: + val = val | tpg_hw->tpg_pattern; + break; + case 0x2: + val = val | tpg_hw->tpg_pattern; + break; + case 0x3: + val = val | tpg_hw->tpg_pattern; + break; + case 0x4: + val = val | tpg_hw->tpg_pattern; + break; + case 0x5: + val = val | tpg_hw->tpg_pattern; + break; + case 0x6: + val = val | tpg_hw->tpg_pattern; + break; + case 0x7: + val = val | tpg_hw->tpg_pattern; + break; + case 0x8: + /* unicolor bar selection */ + val = 0x1 | (1 << tpg_reg->top_unicolor_bar_shift); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_color_bar_cfg); + val = (in_format << tpg_reg->tpg_dt_encode_format_shift) | + tpg_hw->tpg_pattern; + break; + default: + /* frame with split color bar */ + val = 1 << tpg_reg->tpg_split_en_shift; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_color_bar_cfg); + val = (in_format << tpg_reg->tpg_dt_encode_format_shift) | + CAM_TOP_TPG_DEFAULT_PATTERN; + break; + } + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_dt_0_cfg_2); + + val = (1 << tpg_reg->tpg_split_en_shift); + cam_io_w_mb(tpg_data->pix_pattern, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_common_gen_cfg); + + /* if VBI is notset configureVBI to 0xAFF */ + if (tpg_data->v_blank_count) + cam_io_w_mb(tpg_data->v_blank_count, + soc_info->reg_map[0].mem_base + tpg_reg->tpg_vbi_cfg); + else + cam_io_w_mb(0xAFFF, + soc_info->reg_map[0].mem_base + tpg_reg->tpg_vbi_cfg); + + /* Set the TOP tpg mux sel*/ + val = cam_io_r_mb(soc_info->reg_map[1].mem_base + + tpg_reg->top_mux_reg_offset); + val |= (1 << tpg_hw->hw_intf->hw_idx); + + cam_io_w_mb(val, + soc_info->reg_map[1].mem_base + tpg_reg->top_mux_reg_offset); + CAM_DBG(CAM_ISP, "TPG:%d Set top Mux: 0x%x", + tpg_hw->hw_intf->hw_idx, val); + + val = ((tpg_data->num_active_lanes - 1) << + tpg_reg->tpg_num_active_lines_shift) | + (1 << tpg_reg->tpg_fe_pkt_en_shift) | + (1 << tpg_reg->tpg_fs_pkt_en_shift) | + (tpg_data->phy_sel << tpg_reg->tpg_phy_sel_shift_val) | + (1 << tpg_reg->tpg_en_shift_val); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + tpg_reg->tpg_ctrl); + + tpg_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + CAM_DBG(CAM_ISP, "TPG:%d started", tpg_hw->hw_intf->hw_idx); + +end: + return rc; +} + +static int cam_top_tpg_stop(void *hw_priv, + void *stop_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + struct cam_hw_soc_info *soc_info; + struct cam_isp_resource_node *tpg_res; + const struct cam_top_tpg_reg_offset *tpg_reg; + struct cam_top_tpg_cfg *tpg_data; + uint32_t val; + + if (!hw_priv || !stop_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "TPG: Invalid args"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + tpg_reg = tpg_hw->tpg_info->tpg_reg; + tpg_res = (struct cam_isp_resource_node *) stop_args; + tpg_data = (struct cam_top_tpg_cfg *)tpg_res->res_state; + soc_info = &tpg_hw->hw_info->soc_info; + + if ((tpg_res->res_type != CAM_ISP_RESOURCE_TPG) || + (tpg_res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING)) { + CAM_DBG(CAM_ISP, "TPG:%d Invalid Res type:%d res_state:%d", + tpg_hw->hw_intf->hw_idx, + tpg_res->res_type, tpg_res->res_state); + rc = -EINVAL; + goto end; + } + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_ctrl); + + /* Reset the TOP tpg mux sel*/ + val = cam_io_r_mb(soc_info->reg_map[1].mem_base + + tpg_reg->top_mux_reg_offset); + val &= ~(1 << tpg_hw->hw_intf->hw_idx); + + cam_io_w_mb(val, + soc_info->reg_map[1].mem_base + tpg_reg->top_mux_reg_offset); + CAM_DBG(CAM_ISP, "TPG:%d Reset Top Mux: 0x%x", + tpg_hw->hw_intf->hw_idx, val); + + tpg_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + CAM_DBG(CAM_ISP, "TPG:%d stopped", tpg_hw->hw_intf->hw_idx); +end: + return rc; +} + +static int cam_top_tpg_read(void *hw_priv, + void *read_args, uint32_t arg_size) +{ + CAM_ERR(CAM_ISP, "TPG: un supported"); + + return -EINVAL; +} + +static int cam_top_tpg_write(void *hw_priv, + void *write_args, uint32_t arg_size) +{ + CAM_ERR(CAM_ISP, "TPG: un supported"); + return -EINVAL; +} + +static int cam_top_tpg_set_phy_clock( + struct cam_top_tpg_hw *csid_hw, void *cmd_args) +{ + struct cam_top_tpg_clock_update_args *clk_update = NULL; + + if (!csid_hw) + return -EINVAL; + + clk_update = + (struct cam_top_tpg_clock_update_args *)cmd_args; + + csid_hw->clk_rate = clk_update->clk_rate; + CAM_DBG(CAM_ISP, "CSI PHY clock rate %llu", csid_hw->clk_rate); + + return 0; +} + +static int cam_top_tpg_set_top_tpg_pattern(struct cam_top_tpg_hw *tpg_hw, + void *cmd_args) +{ + uint32_t *top_tpg_pattern; + + top_tpg_pattern = (uint32_t *) cmd_args; + tpg_hw->tpg_pattern = *top_tpg_pattern; + CAM_DBG(CAM_ISP, "TPG:%d set tpg debug value:%d", + tpg_hw->hw_intf->hw_idx, tpg_hw->tpg_pattern); + + return 0; +} + +static int cam_top_tpg_process_cmd(void *hw_priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + + if (!hw_priv || !cmd_args) { + CAM_ERR(CAM_ISP, "CSID: Invalid arguments"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + + switch (cmd_type) { + case CAM_ISP_HW_CMD_TPG_PHY_CLOCK_UPDATE: + rc = cam_top_tpg_set_phy_clock(tpg_hw, cmd_args); + break; + case CAM_ISP_HW_CMD_TPG_SET_PATTERN: + rc = cam_top_tpg_set_top_tpg_pattern(tpg_hw, cmd_args); + break; + default: + CAM_ERR(CAM_ISP, "TPG:%d unsupported cmd:%d", + tpg_hw->hw_intf->hw_idx, cmd_type); + rc = -EINVAL; + break; + } + + return 0; +} + +int cam_top_tpg_hw_probe_init(struct cam_hw_intf *tpg_hw_intf, + uint32_t tpg_idx) +{ + int rc = -EINVAL; + struct cam_top_tpg_cfg *tpg_data; + struct cam_hw_info *tpg_hw_info; + struct cam_top_tpg_hw *tpg_hw = NULL; + uint32_t val = 0; + + if (tpg_idx >= CAM_TOP_TPG_HW_NUM_MAX) { + CAM_ERR(CAM_ISP, "Invalid tpg index:%d", tpg_idx); + return rc; + } + + tpg_hw_info = (struct cam_hw_info *)tpg_hw_intf->hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + + tpg_hw->hw_intf = tpg_hw_intf; + tpg_hw->hw_info = tpg_hw_info; + + CAM_DBG(CAM_ISP, "type %d index %d", + tpg_hw->hw_intf->hw_type, tpg_idx); + + tpg_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; + mutex_init(&tpg_hw->hw_info->hw_mutex); + spin_lock_init(&tpg_hw->hw_info->hw_lock); + spin_lock_init(&tpg_hw->lock_state); + init_completion(&tpg_hw->hw_info->hw_complete); + + init_completion(&tpg_hw->tpg_complete); + + rc = cam_top_tpg_init_soc_resources(&tpg_hw->hw_info->soc_info, + tpg_hw); + if (rc < 0) { + CAM_ERR(CAM_ISP, "TPG:%d Failed to init_soc", tpg_idx); + goto err; + } + + tpg_hw->hw_intf->hw_ops.get_hw_caps = cam_top_tpg_get_hw_caps; + tpg_hw->hw_intf->hw_ops.init = cam_top_tpg_init_hw; + tpg_hw->hw_intf->hw_ops.deinit = cam_top_tpg_deinit_hw; + tpg_hw->hw_intf->hw_ops.reset = NULL; + tpg_hw->hw_intf->hw_ops.reserve = cam_top_tpg_reserve; + tpg_hw->hw_intf->hw_ops.release = cam_top_tpg_release; + tpg_hw->hw_intf->hw_ops.start = cam_top_tpg_start; + tpg_hw->hw_intf->hw_ops.stop = cam_top_tpg_stop; + tpg_hw->hw_intf->hw_ops.read = cam_top_tpg_read; + tpg_hw->hw_intf->hw_ops.write = cam_top_tpg_write; + tpg_hw->hw_intf->hw_ops.process_cmd = cam_top_tpg_process_cmd; + + tpg_hw->tpg_res.res_type = CAM_ISP_RESOURCE_TPG; + tpg_hw->tpg_res.res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + tpg_hw->tpg_res.hw_intf = tpg_hw->hw_intf; + tpg_data = kzalloc(sizeof(*tpg_data), GFP_KERNEL); + if (!tpg_data) { + rc = -ENOMEM; + goto err; + } + tpg_hw->tpg_res.res_priv = tpg_data; + + cam_top_tpg_enable_soc_resources(&tpg_hw->hw_info->soc_info, + CAM_SVS_VOTE); + + val = cam_io_r_mb(tpg_hw->hw_info->soc_info.reg_map[0].mem_base + + tpg_hw->tpg_info->tpg_reg->tpg_hw_version); + CAM_DBG(CAM_ISP, "TPG:%d TPG HW version: 0x%x", + tpg_hw->hw_intf->hw_idx, val); + + cam_top_tpg_disable_soc_resources(&tpg_hw->hw_info->soc_info); +err: + + return rc; +} + +int cam_top_tpg_hw_deinit(struct cam_top_tpg_hw *top_tpg_hw) +{ + int rc = -EINVAL; + + if (!top_tpg_hw) { + CAM_ERR(CAM_ISP, "Invalid param"); + return rc; + } + + /* release the privdate data memory from resources */ + kfree(top_tpg_hw->tpg_res.res_priv); + cam_top_tpg_deinit_soc_resources(&top_tpg_hw->hw_info->soc_info); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.h new file mode 100644 index 0000000000000000000000000000000000000000..c3aeb228a5bbda7268cfd3a8ee1f0aaef16ddb2e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TOP_TPG_HW_H_ +#define _CAM_TOP_TPG_HW_H_ + +#include "cam_hw.h" +#include "cam_top_tpg_hw_intf.h" +#include "cam_top_tpg_soc.h" + +enum cam_top_tpg_encode_format { + CAM_TOP_TPG_ENCODE_FORMAT_RAW6, + CAM_TOP_TPG_ENCODE_FORMAT_RAW8, + CAM_TOP_TPG_ENCODE_FORMAT_RAW10, + CAM_TOP_TPG_ENCODE_FORMAT_RAW12, + CAM_TOP_TPG_ENCODE_FORMAT_RAW14, + CAM_TOP_TPG_ENCODE_FORMAT_RAW16, + CAM_TOP_TPG_ENCODE_FORMAT_MAX, +}; + +struct cam_top_tpg_reg_offset { + uint32_t tpg_hw_version; + uint32_t tpg_hw_status; + uint32_t tpg_ctrl; + uint32_t tpg_vc_cfg0; + uint32_t tpg_vc_cfg1; + uint32_t tpg_lfsr_seed; + uint32_t tpg_dt_0_cfg_0; + uint32_t tpg_dt_1_cfg_0; + uint32_t tpg_dt_2_cfg_0; + uint32_t tpg_dt_3_cfg_0; + uint32_t tpg_dt_0_cfg_1; + uint32_t tpg_dt_1_cfg_1; + uint32_t tpg_dt_2_cfg_1; + uint32_t tpg_dt_3_cfg_1; + uint32_t tpg_dt_0_cfg_2; + uint32_t tpg_dt_1_cfg_2; + uint32_t tpg_dt_2_cfg_2; + uint32_t tpg_dt_3_cfg_2; + uint32_t tpg_color_bar_cfg; + uint32_t tpg_common_gen_cfg; + uint32_t tpg_vbi_cfg; + uint32_t tpg_test_bus_crtl; + uint32_t tpg_spare; + /* configurations */ + uint32_t major_version; + uint32_t minor_version; + uint32_t version_incr; + uint32_t tpg_en_shift_val; + uint32_t tpg_phy_sel_shift_val; + uint32_t tpg_num_active_lines_shift; + uint32_t tpg_fe_pkt_en_shift; + uint32_t tpg_fs_pkt_en_shift; + uint32_t tpg_line_interleaving_mode_shift; + uint32_t tpg_num_dts_shift_val; + uint32_t tpg_v_blank_cnt_shift; + uint32_t tpg_dt_encode_format_shift; + uint32_t tpg_payload_mode_color; + uint32_t tpg_split_en_shift; + uint32_t top_mux_reg_offset; + uint32_t top_unicolor_bar_shift; +}; + +/** + * struct cam_top_tpg_hw_info- tpg hardware info + * + * @tpg_reg: tpg register offsets + * @hw_dts_version: HW DTS version + * @csid_max_clk: maximum csid clock + * @phy_max_clk maximum phy clock + * + */ +struct cam_top_tpg_hw_info { + const struct cam_top_tpg_reg_offset *tpg_reg; + uint32_t hw_dts_version; + uint32_t csid_max_clk; + uint32_t phy_max_clk; +}; + +/** + * struct cam_top_tpg_dt_cfg- tpg data type(dt) configuration + * + * @frame_width: frame width in pixel + * @frame_height: frame height in pixel + * @data_type: data type(dt) value + * @encode_format: encode format for this data type + * @payload_mode payload data, such color bar, color box etc + * + */ + +struct cam_top_tpg_dt_cfg { + uint32_t frame_width; + uint32_t frame_height; + uint32_t data_type; + uint32_t encode_format; + uint32_t payload_mode; +}; + +/** + * struct cam_top_tpg_cfg- tpg congiguration + * @pix_pattern : pixel pattern output of the tpg + * @phy_sel : phy selection 0:dphy or 1:cphy + * @num_active_lanes Number of active lines + * @vc_num: Virtual channel number + * @h_blank_count: horizontal blanking count value + * @h_blank_count: vertical blanking count value + * @vbi_cnt: vbi count + * @num_active_dts: number of active dts need to configure + * @dt_cfg: dt configuration values + * + */ +struct cam_top_tpg_cfg { + uint32_t pix_pattern; + uint32_t phy_sel; + uint32_t num_active_lanes; + uint32_t vc_num; + uint32_t v_blank_count; + uint32_t h_blank_count; + uint32_t vbi_cnt; + uint32_t num_active_dts; + struct cam_top_tpg_dt_cfg dt_cfg[4]; +}; + +/** + * struct cam_top_tpg_hw- tpg hw device resources data + * + * @hw_intf: contain the tpg hw interface information + * @hw_info: tpg hw device information + * @tpg_info: tpg hw specific information + * @tpg_res: tpg resource + * @tpg_pattern: tpg pattern configuration + * @clk_rate clock rate + * @lock_state lock state + * @tpg_complete tpg completion + * + */ +struct cam_top_tpg_hw { + struct cam_hw_intf *hw_intf; + struct cam_hw_info *hw_info; + struct cam_top_tpg_hw_info *tpg_info; + struct cam_isp_resource_node tpg_res; + uint32_t tpg_pattern; + uint64_t clk_rate; + spinlock_t lock_state; + struct completion tpg_complete; +}; + +int cam_top_tpg_hw_probe_init(struct cam_hw_intf *tpg_hw_intf, + uint32_t tpg_idx); + +int cam_top_tpg_hw_deinit(struct cam_top_tpg_hw *top_tpg_hw); + +#endif /* _CAM_TOP_TPG_HW_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..fd7dc87fb79a354a090828df942bd686cea0f222 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include "cam_top_tpg_core.h" +#include "cam_top_tpg_dev.h" +#include "cam_top_tpg_hw_intf.h" +#include "cam_debug_util.h" + +static struct cam_hw_intf *cam_top_tpg_hw_list[CAM_TOP_TPG_HW_NUM_MAX] = { + 0, 0}; + +static char tpg_dev_name[8]; + +int cam_top_tpg_probe(struct platform_device *pdev) +{ + + struct cam_hw_intf *tpg_hw_intf; + struct cam_hw_info *tpg_hw_info; + struct cam_top_tpg_hw *tpg_dev = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_top_tpg_hw_info *tpg_hw_data = NULL; + uint32_t tpg_dev_idx; + int rc = 0; + + CAM_DBG(CAM_ISP, "probe called"); + + tpg_hw_intf = kzalloc(sizeof(*tpg_hw_intf), GFP_KERNEL); + if (!tpg_hw_intf) { + rc = -ENOMEM; + goto err; + } + + tpg_hw_info = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!tpg_hw_info) { + rc = -ENOMEM; + goto free_hw_intf; + } + + tpg_dev = kzalloc(sizeof(struct cam_top_tpg_hw), GFP_KERNEL); + if (!tpg_dev) { + rc = -ENOMEM; + goto free_hw_info; + } + + /* get top tpg hw index */ + of_property_read_u32(pdev->dev.of_node, "cell-index", &tpg_dev_idx); + /* get top tpg hw information */ + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_ISP, "No matching table for the top tpg hw"); + rc = -EINVAL; + goto free_dev; + } + + memset(tpg_dev_name, 0, sizeof(tpg_dev_name)); + snprintf(tpg_dev_name, sizeof(tpg_dev_name), + "tpg%1u", tpg_dev_idx); + + tpg_hw_intf->hw_idx = tpg_dev_idx; + tpg_hw_intf->hw_type = CAM_ISP_HW_TYPE_TPG; + tpg_hw_intf->hw_priv = tpg_hw_info; + + tpg_hw_info->core_info = tpg_dev; + tpg_hw_info->soc_info.pdev = pdev; + tpg_hw_info->soc_info.dev = &pdev->dev; + tpg_hw_info->soc_info.dev_name = tpg_dev_name; + tpg_hw_info->soc_info.index = tpg_dev_idx; + + tpg_hw_data = (struct cam_top_tpg_hw_info *)match_dev->data; + /* need to setup the pdev before call the tfe hw probe init */ + tpg_dev->tpg_info = tpg_hw_data; + + rc = cam_top_tpg_hw_probe_init(tpg_hw_intf, tpg_dev_idx); + if (rc) + goto free_dev; + + platform_set_drvdata(pdev, tpg_dev); + CAM_DBG(CAM_ISP, "TPG:%d probe successful", + tpg_hw_intf->hw_idx); + + + if (tpg_hw_intf->hw_idx < CAM_TOP_TPG_HW_NUM_MAX) + cam_top_tpg_hw_list[tpg_hw_intf->hw_idx] = tpg_hw_intf; + else + goto free_dev; + + return 0; + +free_dev: + kfree(tpg_dev); +free_hw_info: + kfree(tpg_hw_info); +free_hw_intf: + kfree(tpg_hw_intf); +err: + return rc; +} + +int cam_top_tpg_remove(struct platform_device *pdev) +{ + struct cam_top_tpg_hw *tpg_dev = NULL; + struct cam_hw_intf *tpg_hw_intf; + struct cam_hw_info *tpg_hw_info; + + tpg_dev = (struct cam_top_tpg_hw *)platform_get_drvdata(pdev); + tpg_hw_intf = tpg_dev->hw_intf; + tpg_hw_info = tpg_dev->hw_info; + + CAM_DBG(CAM_ISP, "TPG:%d remove", + tpg_dev->hw_intf->hw_idx); + + cam_top_tpg_hw_deinit(tpg_dev); + + /*release the tpg device memory */ + kfree(tpg_dev); + kfree(tpg_hw_info); + kfree(tpg_hw_intf); + return 0; +} + +int cam_top_tpg_hw_init(struct cam_hw_intf **top_tpg_hw, + uint32_t hw_idx) +{ + int rc = 0; + + if (cam_top_tpg_hw_list[hw_idx]) { + *top_tpg_hw = cam_top_tpg_hw_list[hw_idx]; + } else { + *top_tpg_hw = NULL; + rc = -1; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..7d921a315a90a4289a5dd96005dcb70cfab19577 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TOP_TPG_DEV_H_ +#define _CAM_TOP_TPG_DEV_H_ + +int cam_top_tpg_probe(struct platform_device *pdev); +int cam_top_tpg_remove(struct platform_device *pdev); + +#endif /*_CAM_TOP_TPG_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..7a4e941cb4ada18197ea227a9a5b8c420cdd7bbd --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#include +#include "cam_top_tpg_soc.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" + +int cam_top_tpg_init_soc_resources(struct cam_hw_soc_info *soc_info, + void *irq_data) +{ + int rc = 0; + struct cam_cpas_register_params cpas_register_param; + struct cam_top_tpg_soc_private *soc_private; + + soc_private = kzalloc(sizeof(struct cam_top_tpg_soc_private), + GFP_KERNEL); + if (!soc_private) + return -ENOMEM; + + soc_info->soc_private = soc_private; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) + return rc; + + /* Need to see if we want post process the clock list */ + rc = cam_soc_util_request_platform_resource(soc_info, NULL, + irq_data); + + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Error Request platform resources failed rc=%d", rc); + goto free_soc_private; + } + + memset(&cpas_register_param, 0, sizeof(cpas_register_param)); + strlcpy(cpas_register_param.identifier, "tpg", + CAM_HW_IDENTIFIER_LENGTH); + cpas_register_param.cell_index = soc_info->index; + cpas_register_param.dev = soc_info->dev; + rc = cam_cpas_register_client(&cpas_register_param); + if (rc) { + CAM_ERR(CAM_ISP, "CPAS registration failed rc=%d", rc); + goto release_soc; + } else { + soc_private->cpas_handle = cpas_register_param.client_handle; + } + + return rc; + +release_soc: + cam_soc_util_release_platform_resource(soc_info); +free_soc_private: + kfree(soc_private); + + return rc; +} + +int cam_top_tpg_deinit_soc_resources( + struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_top_tpg_soc_private *soc_private; + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error soc_private NULL"); + return -ENODEV; + } + + rc = cam_cpas_unregister_client(soc_private->cpas_handle); + if (rc) + CAM_ERR(CAM_ISP, "CPAS unregistration failed rc=%d", rc); + + rc = cam_soc_util_release_platform_resource(soc_info); + + return rc; +} + +int cam_top_tpg_enable_soc_resources( + struct cam_hw_soc_info *soc_info, enum cam_vote_level clk_level) +{ + int rc = 0; + struct cam_top_tpg_soc_private *soc_private; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + + soc_private = soc_info->soc_private; + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_SVS_VOTE; + axi_vote.num_paths = 1; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_WRITE; + + axi_vote.axi_path[0].camnoc_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ab_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW; + + CAM_DBG(CAM_ISP, "csid camnoc_bw:%lld mnoc_ab_bw:%lld mnoc_ib_bw:%lld ", + axi_vote.axi_path[0].camnoc_bw, + axi_vote.axi_path[0].mnoc_ab_bw, + axi_vote.axi_path[0].mnoc_ib_bw); + + rc = cam_cpas_start(soc_private->cpas_handle, &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_ISP, "Error CPAS start failed"); + rc = -EFAULT; + goto end; + } + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + clk_level, false); + if (rc) { + CAM_ERR(CAM_ISP, "enable platform failed"); + goto stop_cpas; + } + + return rc; + +stop_cpas: + cam_cpas_stop(soc_private->cpas_handle); +end: + return rc; +} + +int cam_top_tpg_disable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_top_tpg_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + return -EINVAL; + } + soc_private = soc_info->soc_private; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, false); + if (rc) + CAM_ERR(CAM_ISP, "Disable platform failed"); + + rc = cam_cpas_stop(soc_private->cpas_handle); + if (rc) { + CAM_ERR(CAM_ISP, "Error CPAS stop failed rc=%d", rc); + return rc; + } + + return rc; +} + diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..0838c68745de8f243758ba1579725798784f80a1 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TOP_TPG_SOC_H_ +#define _CAM_TOP_TPG_SOC_H_ + +#include "cam_isp_hw.h" + +/* + * struct cam_top_tpg_soc_private: + * + * @Brief: Private SOC data specific to TPG HW Driver + * + * @cpas_handle: Handle returned on registering with CPAS driver. + * This handle is used for all further interface + * with CPAS. + */ +struct cam_top_tpg_soc_private { + uint32_t cpas_handle; +}; + +/** + * struct cam_top_tpg_device_soc_info - tpg soc SOC info object + * + * @csi_vdd_voltage: csi vdd voltage value + * + */ +struct cam_top_tpg_device_soc_info { + int csi_vdd_voltage; +}; + +/** + * cam_top_tpg_init_soc_resources() + * + * @brief: csid initialization function for the soc info + * + * @soc_info: soc info structure pointer + * @irq_data: irq data for the callback function + * + */ +int cam_top_tpg_init_soc_resources(struct cam_hw_soc_info *soc_info, + void *irq_data); + +/** + * cam_top_tpg_deinit_soc_resources() + * + * @brief: tpg de initialization function for the soc info + * + * @soc_info: soc info structure pointer + * + */ +int cam_top_tpg_deinit_soc_resources(struct cam_hw_soc_info *soc_info); + +/** + * cam_top_tpg_enable_soc_resources() + * + * @brief: tpg soc resource enable function + * + * @soc_info: soc info structure pointer + * @clk_lvl: vote level to start with + * + */ +int cam_top_tpg_enable_soc_resources(struct cam_hw_soc_info *soc_info, + uint32_t clk_lvl); + +/** + * cam_top_tpg_disable_soc_resources() + * + * @brief: csid soc resource disable function + * + * @soc_info: soc info structure pointer + * + */ +int cam_top_tpg_disable_soc_resources(struct cam_hw_soc_info *soc_info); + +#endif /* _CAM_TOP_TPG_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.c new file mode 100644 index 0000000000000000000000000000000000000000..ce56d38fcea03bb2dc5b5c9d284cceb61d95d742 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + + +#include +#include "cam_top_tpg_core.h" +#include "cam_top_tpg_v1.h" +#include "cam_top_tpg_dev.h" + +#define CAM_TOP_TPG_DRV_NAME "tpg_v1" +#define CAM_TOP_TPG_VERSION_V1 0x10000000 + +static struct cam_top_tpg_hw_info cam_top_tpg_v1_hw_info = { + .tpg_reg = &cam_top_tpg_v1_reg_offset, + .hw_dts_version = CAM_TOP_TPG_VERSION_V1, + .csid_max_clk = 426400000, + .phy_max_clk = 384000000, +}; + +static const struct of_device_id cam_top_tpg_v1_dt_match[] = { + { + .compatible = "qcom,tpgv1", + .data = &cam_top_tpg_v1_hw_info, + }, + {} +}; + +MODULE_DEVICE_TABLE(of, cam_top_tpg_v1_dt_match); + +static struct platform_driver cam_top_tpg_v1_driver = { + .probe = cam_top_tpg_probe, + .remove = cam_top_tpg_remove, + .driver = { + .name = CAM_TOP_TPG_DRV_NAME, + .of_match_table = cam_top_tpg_v1_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_top_tpg_v1_init_module(void) +{ + return platform_driver_register(&cam_top_tpg_v1_driver); +} + +static void __exit cam_top_tpg_v1_exit_module(void) +{ + platform_driver_unregister(&cam_top_tpg_v1_driver); +} + +module_init(cam_top_tpg_v1_init_module); +module_exit(cam_top_tpg_v1_exit_module); +MODULE_DESCRIPTION("CAM TOP TPG driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.h new file mode 100644 index 0000000000000000000000000000000000000000..aedc666bb7921b5c07ddeab06e8a736855f2ffc8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TOP_TPG_V1_H_ +#define _CAM_TOP_TPG_V1_H_ + +#include "cam_top_tpg_core.h" + +static struct cam_top_tpg_reg_offset cam_top_tpg_v1_reg_offset = { + .tpg_hw_version = 0x0, + .tpg_hw_status = 0x4, + .tpg_ctrl = 0x60, + .tpg_vc_cfg0 = 0x64, + .tpg_vc_cfg1 = 0x68, + .tpg_lfsr_seed = 0x6c, + .tpg_dt_0_cfg_0 = 0x70, + .tpg_dt_1_cfg_0 = 0x74, + .tpg_dt_2_cfg_0 = 0x78, + .tpg_dt_3_cfg_0 = 0x7C, + .tpg_dt_0_cfg_1 = 0x80, + .tpg_dt_1_cfg_1 = 0x84, + .tpg_dt_2_cfg_1 = 0x88, + .tpg_dt_3_cfg_1 = 0x8C, + .tpg_dt_0_cfg_2 = 0x90, + .tpg_dt_1_cfg_2 = 0x94, + .tpg_dt_2_cfg_2 = 0x98, + .tpg_dt_3_cfg_2 = 0x9C, + .tpg_color_bar_cfg = 0xA0, + .tpg_common_gen_cfg = 0xA4, + .tpg_vbi_cfg = 0xA8, + .tpg_test_bus_crtl = 0xF8, + .tpg_spare = 0xFC, + /* configurations */ + .major_version = 1, + .minor_version = 0, + .version_incr = 0, + .tpg_en_shift_val = 0, + .tpg_phy_sel_shift_val = 3, + .tpg_num_active_lines_shift = 4, + .tpg_fe_pkt_en_shift = 2, + .tpg_fs_pkt_en_shift = 1, + .tpg_line_interleaving_mode_shift = 10, + .tpg_num_dts_shift_val = 8, + .tpg_v_blank_cnt_shift = 12, + .tpg_dt_encode_format_shift = 16, + .tpg_payload_mode_color = 0x8, + .tpg_split_en_shift = 5, + .top_mux_reg_offset = 0x1C, + .top_unicolor_bar_shift = 2, +}; + +#endif /*_CAM_TOP_TPG_V1_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..7f9e109364f993c810daa488e0b175d832ea9d1f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe_soc.o cam_vfe_dev.o cam_vfe_core.o +obj-$(CONFIG_SPECTRA_CAMERA) += vfe_bus/ vfe_top/ vfe17x/ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c new file mode 100644 index 0000000000000000000000000000000000000000..8fdbbd33b8977c6cb9fdff36ef4c08a1558ff12c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c @@ -0,0 +1,751 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "cam_tasklet_util.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_vfe_soc.h" +#include "cam_vfe_core.h" +#include "cam_vfe_bus.h" +#include "cam_vfe_top.h" +#include "cam_ife_hw_mgr.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" + +static const char drv_name[] = "vfe"; + +#define CAM_VFE_17X_CLEAR_0_REG_OFFSET 0x00000064 +#define CAM_VFE_17X_CLEAR_1_REG_OFFSET 0x00000068 +#define CAM_VFE_17X_IRQ_CMD_REG_OFFSET 0x00000058 +#define CAM_VFE_17X_TOP_RESET_MASK 0x80000000 + +#define CAM_VFE_48X_CLEAR_0_REG_OFFSET 0x00000048 +#define CAM_VFE_48X_CLEAR_1_REG_OFFSET 0x0000004C +#define CAM_VFE_48X_CLEAR_2_REG_OFFSET 0x00000050 +#define CAM_VFE_48X_IRQ_CMD_REG_OFFSET 0x00000038 +#define CAM_VFE_48X_TOP_RESET_MASK 0x00000001 + +#define CAM_VFE_LITE_48X_CLEAR_0_REG_OFFSET 0x00000034 +#define CAM_VFE_LITE_48X_CLEAR_1_REG_OFFSET 0x00000038 +#define CAM_VFE_LITE_48X_CLEAR_2_REG_OFFSET 0x0000003C +#define CAM_VFE_LITE_48X_IRQ_CMD_REG_OFFSET 0x00000024 +#define CAM_VFE_LITE_48X_TOP_RESET_MASK 0x00020000 + +int cam_vfe_get_hw_caps(void *hw_priv, void *get_hw_cap_args, uint32_t arg_size) +{ + struct cam_hw_info *vfe_dev = hw_priv; + struct cam_vfe_hw_core_info *core_info = NULL; + int rc = 0; + + CAM_DBG(CAM_ISP, "Enter"); + if (!hw_priv) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + core_info = (struct cam_vfe_hw_core_info *)vfe_dev->core_info; + + if (core_info->vfe_top->hw_ops.get_hw_caps) + core_info->vfe_top->hw_ops.get_hw_caps( + core_info->vfe_top->top_priv, + get_hw_cap_args, arg_size); + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +int cam_vfe_reset_irq_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc = -EINVAL; + struct cam_hw_info *vfe_hw; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_vfe_soc_private *soc_private = NULL; + void __iomem *mem_base; + + vfe_hw = th_payload->handler_priv; + soc_info = &vfe_hw->soc_info; + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Invalid soc_private"); + return -ENODEV; + } + + CAM_DBG(CAM_ISP, "Enter"); + + /* + * Clear All IRQs to avoid spurious IRQs immediately + * after Reset Done. + */ + CAM_DBG(CAM_ISP, "TOP_IRQ_STATUS_0 = 0x%x", + th_payload->evt_status_arr[0]); + + mem_base = soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base; + + switch (soc_info->hw_version) { + case CAM_CPAS_TITAN_480_V100: + if (!soc_private->is_ife_lite) { + if (th_payload->evt_status_arr[0] & 0x1) { + cam_io_w(0xFFFFFFFF, mem_base + + CAM_VFE_48X_CLEAR_0_REG_OFFSET); + cam_io_w(0xFFFFFFFF, mem_base + + CAM_VFE_48X_CLEAR_1_REG_OFFSET); + cam_io_w(0xFFFFFFFF, mem_base + + CAM_VFE_48X_CLEAR_2_REG_OFFSET); + cam_io_w(0x00000001, mem_base + + CAM_VFE_48X_IRQ_CMD_REG_OFFSET); + CAM_DBG(CAM_ISP, + "Calling Complete for RESET CMD"); + complete(&vfe_hw->hw_complete); + rc = 0; + } + } else { + if (th_payload->evt_status_arr[0] & (1<<17)) { + cam_io_w(0xFFFFFFFF, mem_base + + CAM_VFE_LITE_48X_CLEAR_0_REG_OFFSET); + cam_io_w(0xFFFFFFFF, mem_base + + CAM_VFE_LITE_48X_CLEAR_1_REG_OFFSET); + cam_io_w(0xFFFFFFFF, mem_base + + CAM_VFE_LITE_48X_CLEAR_2_REG_OFFSET); + cam_io_w(0x00000001, mem_base + + CAM_VFE_LITE_48X_IRQ_CMD_REG_OFFSET); + CAM_DBG(CAM_ISP, + "Calling Complete for RESET CMD"); + complete(&vfe_hw->hw_complete); + rc = 0; + } + } + break; + default: + if (th_payload->evt_status_arr[0] & (1<<31)) { + cam_io_w(0xFFFFFFFF, mem_base + + CAM_VFE_17X_CLEAR_0_REG_OFFSET); + cam_io_w(0xFFFFFFFF, mem_base + + CAM_VFE_17X_CLEAR_1_REG_OFFSET); + cam_io_w(0x00000001, mem_base + + CAM_VFE_17X_IRQ_CMD_REG_OFFSET); + CAM_DBG(CAM_ISP, "Calling Complete for RESET CMD"); + complete(&vfe_hw->hw_complete); + rc = 0; + } + break; + } + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +int cam_vfe_init_hw(void *hw_priv, void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *vfe_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_vfe_hw_core_info *core_info = NULL; + struct cam_isp_resource_node *isp_res = NULL; + int rc = 0; + uint32_t reset_core_args = + CAM_VFE_HW_RESET_HW_AND_REG; + + CAM_DBG(CAM_ISP, "Enter"); + if (!hw_priv) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + mutex_lock(&vfe_hw->hw_mutex); + vfe_hw->open_count++; + if (vfe_hw->open_count > 1) { + mutex_unlock(&vfe_hw->hw_mutex); + CAM_DBG(CAM_ISP, "VFE has already been initialized cnt %d", + vfe_hw->open_count); + return 0; + } + mutex_unlock(&vfe_hw->hw_mutex); + + soc_info = &vfe_hw->soc_info; + core_info = (struct cam_vfe_hw_core_info *)vfe_hw->core_info; + + /* Turn ON Regulators, Clocks and other SOC resources */ + rc = cam_vfe_enable_soc_resources(soc_info); + if (rc) { + CAM_ERR(CAM_ISP, "Enable SOC failed"); + rc = -EFAULT; + goto decrement_open_cnt; + } + + isp_res = (struct cam_isp_resource_node *)init_hw_args; + if (isp_res && isp_res->init) { + rc = isp_res->init(isp_res, NULL, 0); + if (rc) { + CAM_ERR(CAM_ISP, "init Failed rc=%d", rc); + goto disable_soc; + } + } + + CAM_DBG(CAM_ISP, "Enable soc done"); + + /* Do HW Reset */ + rc = cam_vfe_reset(hw_priv, &reset_core_args, sizeof(uint32_t)); + if (rc) { + CAM_ERR(CAM_ISP, "Reset Failed rc=%d", rc); + goto deinint_vfe_res; + } + + rc = core_info->vfe_bus->hw_ops.init(core_info->vfe_bus->bus_priv, + NULL, 0); + if (rc) { + CAM_ERR(CAM_ISP, "Bus HW init Failed rc=%d", rc); + goto deinint_vfe_res; + } + + rc = core_info->vfe_top->hw_ops.init(core_info->vfe_top->top_priv, + NULL, 0); + if (rc) { + CAM_ERR(CAM_ISP, "Top HW init Failed rc=%d", rc); + goto deinint_vfe_res; + } + + if (core_info->vfe_rd_bus) { + rc = core_info->vfe_rd_bus->hw_ops.init( + core_info->vfe_rd_bus->bus_priv, + NULL, 0); + if (rc) { + CAM_ERR(CAM_ISP, "Bus RD HW init Failed rc=%d", rc); + goto deinint_vfe_res; + } + } + + vfe_hw->hw_state = CAM_HW_STATE_POWER_UP; + return rc; + +deinint_vfe_res: + if (isp_res && isp_res->deinit) + isp_res->deinit(isp_res, NULL, 0); +disable_soc: + cam_vfe_disable_soc_resources(soc_info); +decrement_open_cnt: + mutex_lock(&vfe_hw->hw_mutex); + vfe_hw->open_count--; + mutex_unlock(&vfe_hw->hw_mutex); + return rc; +} + +int cam_vfe_deinit_hw(void *hw_priv, void *deinit_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *vfe_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_vfe_hw_core_info *core_info = NULL; + struct cam_isp_resource_node *isp_res = NULL; + int rc = 0; + uint32_t reset_core_args = + CAM_VFE_HW_RESET_HW_AND_REG; + + CAM_DBG(CAM_ISP, "Enter"); + if (!hw_priv) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + isp_res = (struct cam_isp_resource_node *)deinit_hw_args; + if (isp_res && isp_res->deinit) { + rc = isp_res->deinit(isp_res, NULL, 0); + if (rc) + CAM_ERR(CAM_ISP, "deinit failed"); + } + + mutex_lock(&vfe_hw->hw_mutex); + if (!vfe_hw->open_count) { + mutex_unlock(&vfe_hw->hw_mutex); + CAM_ERR(CAM_ISP, "Error. Unbalanced deinit"); + return -EFAULT; + } + vfe_hw->open_count--; + if (vfe_hw->open_count) { + mutex_unlock(&vfe_hw->hw_mutex); + CAM_DBG(CAM_ISP, "open_cnt non-zero =%d", vfe_hw->open_count); + return 0; + } + mutex_unlock(&vfe_hw->hw_mutex); + + soc_info = &vfe_hw->soc_info; + core_info = (struct cam_vfe_hw_core_info *)vfe_hw->core_info; + + rc = core_info->vfe_bus->hw_ops.deinit(core_info->vfe_bus->bus_priv, + NULL, 0); + if (rc) + CAM_ERR(CAM_ISP, "Bus HW deinit Failed rc=%d", rc); + + if (core_info->vfe_rd_bus) { + rc = core_info->vfe_rd_bus->hw_ops.deinit( + core_info->vfe_rd_bus->bus_priv, + NULL, 0); + if (rc) + CAM_ERR(CAM_ISP, "Bus HW deinit Failed rc=%d", rc); + } + + rc = cam_vfe_reset(hw_priv, &reset_core_args, sizeof(uint32_t)); + + /* Turn OFF Regulators, Clocks and other SOC resources */ + CAM_DBG(CAM_ISP, "Disable SOC resource"); + rc = cam_vfe_disable_soc_resources(soc_info); + if (rc) + CAM_ERR(CAM_ISP, "Disable SOC failed"); + + vfe_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +int cam_vfe_reset(void *hw_priv, void *reset_core_args, uint32_t arg_size) +{ + struct cam_hw_info *vfe_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_vfe_soc_private *soc_private = NULL; + struct cam_vfe_hw_core_info *core_info = NULL; + uint32_t top_reset_irq_reg_mask[CAM_IFE_IRQ_REGISTERS_MAX]; + int rc; + + CAM_DBG(CAM_ISP, "Enter"); + + if (!hw_priv) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + soc_info = &vfe_hw->soc_info; + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Invalid soc_private"); + return -ENODEV; + } + core_info = (struct cam_vfe_hw_core_info *)vfe_hw->core_info; + + memset(top_reset_irq_reg_mask, 0, sizeof(top_reset_irq_reg_mask)); + + switch (soc_info->hw_version) { + case CAM_CPAS_TITAN_480_V100: + if (!soc_private->is_ife_lite) + top_reset_irq_reg_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0] + = CAM_VFE_48X_TOP_RESET_MASK; + else + top_reset_irq_reg_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0] + = CAM_VFE_LITE_48X_TOP_RESET_MASK; + break; + default: + top_reset_irq_reg_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0] + = CAM_VFE_17X_TOP_RESET_MASK; + break; + } + + core_info->reset_irq_handle = cam_irq_controller_subscribe_irq( + core_info->vfe_irq_controller, CAM_IRQ_PRIORITY_0, + top_reset_irq_reg_mask, vfe_hw, + cam_vfe_reset_irq_top_half, NULL, NULL, NULL); + if (core_info->reset_irq_handle < 1) { + CAM_ERR(CAM_ISP, "subscribe irq controller failed"); + core_info->reset_irq_handle = 0; + return -EFAULT; + } + + reinit_completion(&vfe_hw->hw_complete); + + CAM_DBG(CAM_ISP, "calling RESET on VFE:%d", soc_info->index); + + core_info->vfe_top->hw_ops.reset(core_info->vfe_top->top_priv, + reset_core_args, arg_size); + + /* Wait for Completion or Timeout of 500ms */ + rc = wait_for_completion_timeout(&vfe_hw->hw_complete, 500); + + if (!rc) + CAM_ERR(CAM_ISP, "Reset Timeout"); + else + CAM_DBG(CAM_ISP, "reset complete done (%d)", rc); + + rc = cam_irq_controller_unsubscribe_irq( + core_info->vfe_irq_controller, core_info->reset_irq_handle); + if (rc) + CAM_ERR(CAM_ISP, "Error. Unsubscribe failed"); + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +void cam_isp_hw_get_timestamp(struct cam_isp_timestamp *time_stamp) +{ + struct timespec ts; + + get_monotonic_boottime(&ts); + time_stamp->mono_time.tv_sec = ts.tv_sec; + time_stamp->mono_time.tv_usec = ts.tv_nsec/1000; +} + +int cam_vfe_reserve(void *hw_priv, void *reserve_args, uint32_t arg_size) +{ + struct cam_vfe_hw_core_info *core_info = NULL; + struct cam_hw_info *vfe_hw = hw_priv; + struct cam_vfe_acquire_args *acquire; + int rc = -ENODEV; + + if (!hw_priv || !reserve_args || (arg_size != + sizeof(struct cam_vfe_acquire_args))) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + core_info = (struct cam_vfe_hw_core_info *)vfe_hw->core_info; + acquire = (struct cam_vfe_acquire_args *)reserve_args; + + CAM_DBG(CAM_ISP, "acq res type: %d", acquire->rsrc_type); + mutex_lock(&vfe_hw->hw_mutex); + if (acquire->rsrc_type == CAM_ISP_RESOURCE_VFE_IN) { + rc = core_info->vfe_top->hw_ops.reserve( + core_info->vfe_top->top_priv, + acquire, sizeof(*acquire)); + } else if (acquire->rsrc_type == CAM_ISP_RESOURCE_VFE_OUT) { + rc = core_info->vfe_bus->hw_ops.reserve( + core_info->vfe_bus->bus_priv, acquire, + sizeof(*acquire)); + } else if (acquire->rsrc_type == CAM_ISP_RESOURCE_VFE_BUS_RD) { + if (core_info->vfe_rd_bus) + rc = core_info->vfe_rd_bus->hw_ops.reserve( + core_info->vfe_rd_bus->bus_priv, acquire, + sizeof(*acquire)); + } else + CAM_ERR(CAM_ISP, "Invalid res type:%d", acquire->rsrc_type); + + mutex_unlock(&vfe_hw->hw_mutex); + + return rc; +} + +int cam_vfe_release(void *hw_priv, void *release_args, uint32_t arg_size) +{ + struct cam_vfe_hw_core_info *core_info = NULL; + struct cam_hw_info *vfe_hw = hw_priv; + struct cam_isp_resource_node *isp_res; + int rc = -ENODEV; + + if (!hw_priv || !release_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + core_info = (struct cam_vfe_hw_core_info *)vfe_hw->core_info; + isp_res = (struct cam_isp_resource_node *) release_args; + + mutex_lock(&vfe_hw->hw_mutex); + if (isp_res->res_type == CAM_ISP_RESOURCE_VFE_IN) + rc = core_info->vfe_top->hw_ops.release( + core_info->vfe_top->top_priv, isp_res, + sizeof(*isp_res)); + else if (isp_res->res_type == CAM_ISP_RESOURCE_VFE_OUT) + rc = core_info->vfe_bus->hw_ops.release( + core_info->vfe_bus->bus_priv, isp_res, + sizeof(*isp_res)); + else if (isp_res->res_type == CAM_ISP_RESOURCE_VFE_BUS_RD) { + if (core_info->vfe_rd_bus) + rc = core_info->vfe_rd_bus->hw_ops.release( + core_info->vfe_rd_bus->bus_priv, isp_res, + sizeof(*isp_res)); + } else { + CAM_ERR(CAM_ISP, "Invalid res type:%d", isp_res->res_type); + } + + mutex_unlock(&vfe_hw->hw_mutex); + + return rc; +} + + +int cam_vfe_start(void *hw_priv, void *start_args, uint32_t arg_size) +{ + struct cam_vfe_hw_core_info *core_info = NULL; + struct cam_hw_info *vfe_hw = hw_priv; + struct cam_isp_resource_node *isp_res; + struct cam_hw_soc_info *soc_info = NULL; + int rc = 0; + + if (!hw_priv || !start_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + soc_info = &vfe_hw->soc_info; + core_info = (struct cam_vfe_hw_core_info *)vfe_hw->core_info; + isp_res = (struct cam_isp_resource_node *)start_args; + core_info->tasklet_info = isp_res->tasklet_info; + + mutex_lock(&vfe_hw->hw_mutex); + if (isp_res->res_type == CAM_ISP_RESOURCE_VFE_IN) { + rc = core_info->vfe_top->hw_ops.start( + core_info->vfe_top->top_priv, isp_res, + sizeof(struct cam_isp_resource_node)); + + if (rc) + CAM_ERR(CAM_ISP, "Failed to start VFE IN"); + } else if (isp_res->res_type == CAM_ISP_RESOURCE_VFE_OUT) { + rc = core_info->vfe_bus->hw_ops.start(isp_res, NULL, 0); + + if (rc) + CAM_ERR(CAM_ISP, "Failed to start VFE OUT"); + } else if (isp_res->res_type == CAM_ISP_RESOURCE_VFE_BUS_RD) { + if (core_info->vfe_rd_bus) { + rc = core_info->vfe_rd_bus->hw_ops.start(isp_res, + NULL, 0); + + if (rc) + CAM_ERR(CAM_ISP, "Failed to start BUS RD"); + } + } else { + CAM_ERR(CAM_ISP, "Invalid res type:%d", isp_res->res_type); + rc = -EFAULT; + } + + mutex_unlock(&vfe_hw->hw_mutex); + + return rc; +} + +int cam_vfe_stop(void *hw_priv, void *stop_args, uint32_t arg_size) +{ + struct cam_vfe_hw_core_info *core_info = NULL; + struct cam_hw_info *vfe_hw = hw_priv; + struct cam_isp_resource_node *isp_res; + int rc = -EINVAL; + + if (!hw_priv || !stop_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + core_info = (struct cam_vfe_hw_core_info *)vfe_hw->core_info; + isp_res = (struct cam_isp_resource_node *)stop_args; + + mutex_lock(&vfe_hw->hw_mutex); + if (isp_res->res_type == CAM_ISP_RESOURCE_VFE_IN) { + rc = core_info->vfe_top->hw_ops.stop( + core_info->vfe_top->top_priv, isp_res, + sizeof(struct cam_isp_resource_node)); + } else if (isp_res->res_type == CAM_ISP_RESOURCE_VFE_OUT) { + rc = core_info->vfe_bus->hw_ops.stop(isp_res, NULL, 0); + } else if (isp_res->res_type == CAM_ISP_RESOURCE_VFE_BUS_RD) { + if (core_info->vfe_rd_bus) + rc = core_info->vfe_rd_bus->hw_ops.stop(isp_res, + NULL, 0); + } else { + CAM_ERR(CAM_ISP, "Invalid res type:%d", isp_res->res_type); + } + + if (core_info->reset_irq_handle > 0) { + cam_irq_controller_unsubscribe_irq( + core_info->vfe_irq_controller, + core_info->reset_irq_handle); + core_info->reset_irq_handle = 0; + } + + mutex_unlock(&vfe_hw->hw_mutex); + + return rc; +} + +int cam_vfe_read(void *hw_priv, void *read_args, uint32_t arg_size) +{ + return -EPERM; +} + +int cam_vfe_write(void *hw_priv, void *write_args, uint32_t arg_size) +{ + return -EPERM; +} + +int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + struct cam_hw_info *vfe_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_vfe_hw_core_info *core_info = NULL; + struct cam_vfe_hw_info *hw_info = NULL; + int rc = 0; + + if (!hw_priv) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + soc_info = &vfe_hw->soc_info; + core_info = (struct cam_vfe_hw_core_info *)vfe_hw->core_info; + hw_info = core_info->vfe_hw_info; + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_CHANGE_BASE: + case CAM_ISP_HW_CMD_GET_REG_UPDATE: + case CAM_ISP_HW_CMD_CLOCK_UPDATE: + case CAM_ISP_HW_CMD_BW_UPDATE: + case CAM_ISP_HW_CMD_BW_CONTROL: + case CAM_ISP_HW_CMD_CORE_CONFIG: + case CAM_ISP_HW_CMD_BW_UPDATE_V2: + case CAM_ISP_HW_CMD_DUMP_HW: + rc = core_info->vfe_top->hw_ops.process_cmd( + core_info->vfe_top->top_priv, cmd_type, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_GET_BUF_UPDATE: + case CAM_ISP_HW_CMD_GET_HFR_UPDATE: + case CAM_ISP_HW_CMD_STRIPE_UPDATE: + case CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ: + case CAM_ISP_HW_CMD_UBWC_UPDATE: + case CAM_ISP_HW_CMD_UBWC_UPDATE_V2: + case CAM_ISP_HW_CMD_WM_CONFIG_UPDATE: + case CAM_ISP_HW_CMD_GET_SECURE_MODE: + rc = core_info->vfe_bus->hw_ops.process_cmd( + core_info->vfe_bus->bus_priv, cmd_type, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_GET_HFR_UPDATE_RM: + case CAM_ISP_HW_CMD_GET_BUF_UPDATE_RM: + if (core_info->vfe_rd_bus) + rc = core_info->vfe_rd_bus->hw_ops.process_cmd( + core_info->vfe_rd_bus->bus_priv, cmd_type, + cmd_args, arg_size); + break; + + case CAM_ISP_HW_CMD_FE_UPDATE_IN_RD: + rc = core_info->vfe_top->hw_ops.process_cmd( + core_info->vfe_top->top_priv, cmd_type, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_FE_UPDATE_BUS_RD: + if (core_info->vfe_rd_bus) { + rc = core_info->vfe_rd_bus->hw_ops.process_cmd( + core_info->vfe_rd_bus->bus_priv, cmd_type, + cmd_args, arg_size); + } + break; + default: + CAM_ERR(CAM_ISP, "Invalid cmd type:%d", cmd_type); + rc = -EINVAL; + break; + } + return rc; +} + +irqreturn_t cam_vfe_irq(int irq_num, void *data) +{ + struct cam_hw_info *vfe_hw; + struct cam_vfe_hw_core_info *core_info; + + if (!data) + return IRQ_NONE; + + vfe_hw = (struct cam_hw_info *)data; + core_info = (struct cam_vfe_hw_core_info *)vfe_hw->core_info; + + return cam_irq_controller_handle_irq(irq_num, + core_info->vfe_irq_controller); +} + +int cam_vfe_core_init(struct cam_vfe_hw_core_info *core_info, + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + struct cam_vfe_hw_info *vfe_hw_info) +{ + int rc = -EINVAL; + struct cam_vfe_soc_private *soc_private = NULL; + + CAM_DBG(CAM_ISP, "Enter"); + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Invalid soc_private"); + return -ENODEV; + } + + rc = cam_irq_controller_init(drv_name, + CAM_SOC_GET_REG_MAP_START(soc_info, VFE_CORE_BASE_IDX), + vfe_hw_info->irq_reg_info, &core_info->vfe_irq_controller, + true); + if (rc) { + CAM_ERR(CAM_ISP, + "Error, cam_irq_controller_init failed rc = %d", rc); + return rc; + } + + rc = cam_vfe_top_init(vfe_hw_info->top_version, soc_info, hw_intf, + vfe_hw_info->top_hw_info, core_info->vfe_irq_controller, + &core_info->vfe_top); + if (rc) { + CAM_ERR(CAM_ISP, "Error, cam_vfe_top_init failed rc = %d", rc); + goto deinit_controller; + } + + rc = cam_vfe_bus_init(vfe_hw_info->bus_version, BUS_TYPE_WR, + soc_info, hw_intf, vfe_hw_info->bus_hw_info, + core_info->vfe_irq_controller, &core_info->vfe_bus); + if (rc) { + CAM_ERR(CAM_ISP, "Error, cam_vfe_bus_init failed rc = %d", rc); + goto deinit_top; + } + + /* Read Bus is not valid for vfe-lite */ + if (!soc_private->is_ife_lite) { + rc = cam_vfe_bus_init(vfe_hw_info->bus_rd_version, BUS_TYPE_RD, + soc_info, hw_intf, vfe_hw_info->bus_rd_hw_info, + core_info->vfe_irq_controller, &core_info->vfe_rd_bus); + if (rc) { + CAM_WARN(CAM_ISP, "Error, RD cam_vfe_bus_init failed"); + rc = 0; + } + CAM_DBG(CAM_ISP, "vfe_bus_rd %pK hw_idx %d", + core_info->vfe_rd_bus, hw_intf->hw_idx); + } + + spin_lock_init(&core_info->spin_lock); + + return rc; + +deinit_top: + cam_vfe_top_deinit(vfe_hw_info->top_version, + &core_info->vfe_top); + +deinit_controller: + cam_irq_controller_deinit(&core_info->vfe_irq_controller); + + return rc; +} + +int cam_vfe_core_deinit(struct cam_vfe_hw_core_info *core_info, + struct cam_vfe_hw_info *vfe_hw_info) +{ + int rc = -EINVAL; + unsigned long flags; + + spin_lock_irqsave(&core_info->spin_lock, flags); + + rc = cam_vfe_bus_deinit(vfe_hw_info->bus_version, + &core_info->vfe_bus); + if (rc) + CAM_ERR(CAM_ISP, "Error cam_vfe_bus_deinit failed rc=%d", rc); + + rc = cam_vfe_top_deinit(vfe_hw_info->top_version, + &core_info->vfe_top); + if (rc) + CAM_ERR(CAM_ISP, "Error cam_vfe_top_deinit failed rc=%d", rc); + + rc = cam_irq_controller_deinit(&core_info->vfe_irq_controller); + if (rc) + CAM_ERR(CAM_ISP, + "Error cam_irq_controller_deinit failed rc=%d", rc); + + spin_unlock_irqrestore(&core_info->spin_lock, flags); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.h new file mode 100644 index 0000000000000000000000000000000000000000..43afd0377057e3c66b5547bca2e7541429a29221 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_CORE_H_ +#define _CAM_VFE_CORE_H_ + +#include +#include "cam_hw_intf.h" +#include "cam_vfe_top.h" +#include "cam_vfe_bus.h" +#include "cam_vfe_hw_intf.h" + +struct cam_vfe_hw_info { + struct cam_irq_controller_reg_info *irq_reg_info; + + uint32_t bus_version; + void *bus_hw_info; + + uint32_t bus_rd_version; + void *bus_rd_hw_info; + + uint32_t top_version; + void *top_hw_info; + uint32_t camif_version; + void *camif_reg; + + uint32_t camif_lite_version; + void *camif_lite_reg; + + uint32_t testgen_version; + void *testgen_reg; + + uint32_t num_qos_settings; + struct cam_isp_reg_val_pair *qos_settings; + + uint32_t num_ds_settings; + struct cam_isp_reg_val_pair *ds_settings; + + uint32_t num_vbif_settings; + struct cam_isp_reg_val_pair *vbif_settings; +}; + +#define CAM_VFE_EVT_MAX 256 + +struct cam_vfe_hw_core_info { + struct cam_vfe_hw_info *vfe_hw_info; + void *vfe_irq_controller; + struct cam_vfe_top *vfe_top; + struct cam_vfe_bus *vfe_bus; + struct cam_vfe_bus *vfe_rd_bus; + void *tasklet_info; + spinlock_t spin_lock; + int reset_irq_handle; +}; + +int cam_vfe_get_hw_caps(void *device_priv, + void *get_hw_cap_args, uint32_t arg_size); +int cam_vfe_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_vfe_deinit_hw(void *hw_priv, + void *deinit_hw_args, uint32_t arg_size); +int cam_vfe_reset(void *device_priv, + void *reset_core_args, uint32_t arg_size); +int cam_vfe_reserve(void *device_priv, + void *reserve_args, uint32_t arg_size); +int cam_vfe_release(void *device_priv, + void *reserve_args, uint32_t arg_size); +int cam_vfe_start(void *device_priv, + void *start_args, uint32_t arg_size); +int cam_vfe_stop(void *device_priv, + void *stop_args, uint32_t arg_size); +int cam_vfe_read(void *device_priv, + void *read_args, uint32_t arg_size); +int cam_vfe_write(void *device_priv, + void *write_args, uint32_t arg_size); +int cam_vfe_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size); + +irqreturn_t cam_vfe_irq(int irq_num, void *data); + +int cam_vfe_core_init(struct cam_vfe_hw_core_info *core_info, + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + struct cam_vfe_hw_info *vfe_hw_info); + +int cam_vfe_core_deinit(struct cam_vfe_hw_core_info *core_info, + struct cam_vfe_hw_info *vfe_hw_info); + +#endif /* _CAM_VFE_CORE_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_dev.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..362d513c6a8f8b5fedbfdc789e3f5837e3475933 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_dev.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + + +#include +#include +#include +#include "cam_vfe_dev.h" +#include "cam_vfe_core.h" +#include "cam_vfe_soc.h" +#include "cam_debug_util.h" + +static struct cam_hw_intf *cam_vfe_hw_list[CAM_VFE_HW_NUM_MAX] = {0, 0, 0, 0}; + +static char vfe_dev_name[8]; + +int cam_vfe_probe(struct platform_device *pdev) +{ + struct cam_hw_info *vfe_hw = NULL; + struct cam_hw_intf *vfe_hw_intf = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_vfe_hw_core_info *core_info = NULL; + struct cam_vfe_hw_info *hw_info = NULL; + int rc = 0; + + vfe_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!vfe_hw_intf) { + rc = -ENOMEM; + goto end; + } + + of_property_read_u32(pdev->dev.of_node, + "cell-index", &vfe_hw_intf->hw_idx); + + vfe_hw = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!vfe_hw) { + rc = -ENOMEM; + goto free_vfe_hw_intf; + } + + memset(vfe_dev_name, 0, sizeof(vfe_dev_name)); + snprintf(vfe_dev_name, sizeof(vfe_dev_name), + "vfe%1u", vfe_hw_intf->hw_idx); + + vfe_hw->soc_info.pdev = pdev; + vfe_hw->soc_info.dev = &pdev->dev; + vfe_hw->soc_info.dev_name = vfe_dev_name; + vfe_hw_intf->hw_priv = vfe_hw; + vfe_hw_intf->hw_ops.get_hw_caps = cam_vfe_get_hw_caps; + vfe_hw_intf->hw_ops.init = cam_vfe_init_hw; + vfe_hw_intf->hw_ops.deinit = cam_vfe_deinit_hw; + vfe_hw_intf->hw_ops.reset = cam_vfe_reset; + vfe_hw_intf->hw_ops.reserve = cam_vfe_reserve; + vfe_hw_intf->hw_ops.release = cam_vfe_release; + vfe_hw_intf->hw_ops.start = cam_vfe_start; + vfe_hw_intf->hw_ops.stop = cam_vfe_stop; + vfe_hw_intf->hw_ops.read = cam_vfe_read; + vfe_hw_intf->hw_ops.write = cam_vfe_write; + vfe_hw_intf->hw_ops.process_cmd = cam_vfe_process_cmd; + vfe_hw_intf->hw_type = CAM_ISP_HW_TYPE_VFE; + + CAM_DBG(CAM_ISP, "type %d index %d", + vfe_hw_intf->hw_type, vfe_hw_intf->hw_idx); + + platform_set_drvdata(pdev, vfe_hw_intf); + + vfe_hw->core_info = kzalloc(sizeof(struct cam_vfe_hw_core_info), + GFP_KERNEL); + if (!vfe_hw->core_info) { + CAM_DBG(CAM_ISP, "Failed to alloc for core"); + rc = -ENOMEM; + goto free_vfe_hw; + } + core_info = (struct cam_vfe_hw_core_info *)vfe_hw->core_info; + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_ISP, "Of_match Failed"); + rc = -EINVAL; + goto free_core_info; + } + hw_info = (struct cam_vfe_hw_info *)match_dev->data; + core_info->vfe_hw_info = hw_info; + + rc = cam_vfe_init_soc_resources(&vfe_hw->soc_info, cam_vfe_irq, + vfe_hw); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Failed to init soc rc=%d", rc); + goto free_core_info; + } + + rc = cam_vfe_core_init(core_info, &vfe_hw->soc_info, + vfe_hw_intf, hw_info); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Failed to init core rc=%d", rc); + goto deinit_soc; + } + + vfe_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + mutex_init(&vfe_hw->hw_mutex); + spin_lock_init(&vfe_hw->hw_lock); + init_completion(&vfe_hw->hw_complete); + + if (vfe_hw_intf->hw_idx < CAM_VFE_HW_NUM_MAX) + cam_vfe_hw_list[vfe_hw_intf->hw_idx] = vfe_hw_intf; + + cam_vfe_init_hw(vfe_hw, NULL, 0); + cam_vfe_deinit_hw(vfe_hw, NULL, 0); + + CAM_DBG(CAM_ISP, "VFE%d probe successful", vfe_hw_intf->hw_idx); + + return rc; + +deinit_soc: + if (cam_vfe_deinit_soc_resources(&vfe_hw->soc_info)) + CAM_ERR(CAM_ISP, "Failed to deinit soc"); +free_core_info: + kfree(vfe_hw->core_info); +free_vfe_hw: + kfree(vfe_hw); +free_vfe_hw_intf: + kfree(vfe_hw_intf); +end: + return rc; +} + +int cam_vfe_remove(struct platform_device *pdev) +{ + struct cam_hw_info *vfe_hw = NULL; + struct cam_hw_intf *vfe_hw_intf = NULL; + struct cam_vfe_hw_core_info *core_info = NULL; + int rc = 0; + + vfe_hw_intf = platform_get_drvdata(pdev); + if (!vfe_hw_intf) { + CAM_ERR(CAM_ISP, "Error! No data in pdev"); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "type %d index %d", + vfe_hw_intf->hw_type, vfe_hw_intf->hw_idx); + + if (vfe_hw_intf->hw_idx < CAM_VFE_HW_NUM_MAX) + cam_vfe_hw_list[vfe_hw_intf->hw_idx] = NULL; + + vfe_hw = vfe_hw_intf->hw_priv; + if (!vfe_hw) { + CAM_ERR(CAM_ISP, "Error! HW data is NULL"); + rc = -ENODEV; + goto free_vfe_hw_intf; + } + + core_info = (struct cam_vfe_hw_core_info *)vfe_hw->core_info; + if (!core_info) { + CAM_ERR(CAM_ISP, "Error! core data NULL"); + rc = -EINVAL; + goto deinit_soc; + } + + rc = cam_vfe_core_deinit(core_info, core_info->vfe_hw_info); + if (rc < 0) + CAM_ERR(CAM_ISP, "Failed to deinit core rc=%d", rc); + + kfree(vfe_hw->core_info); + +deinit_soc: + rc = cam_vfe_deinit_soc_resources(&vfe_hw->soc_info); + if (rc < 0) + CAM_ERR(CAM_ISP, "Failed to deinit soc rc=%d", rc); + + mutex_destroy(&vfe_hw->hw_mutex); + kfree(vfe_hw); + + CAM_DBG(CAM_ISP, "VFE%d remove successful", vfe_hw_intf->hw_idx); + +free_vfe_hw_intf: + kfree(vfe_hw_intf); + + return rc; +} + +int cam_vfe_hw_init(struct cam_hw_intf **vfe_hw, uint32_t hw_idx) +{ + int rc = 0; + + if (cam_vfe_hw_list[hw_idx]) { + *vfe_hw = cam_vfe_hw_list[hw_idx]; + rc = 0; + } else { + *vfe_hw = NULL; + rc = -ENODEV; + } + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_dev.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..c2d78b69c684947a3881314c938a3659a509c94c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_dev.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_DEV_H_ +#define _CAM_VFE_DEV_H_ + +#include + +/* + * cam_vfe_probe() + * + * @brief: Driver probe function called on Boot + * + * @pdev: Platform Device pointer + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_probe(struct platform_device *pdev); + +/* + * cam_vfe_remove() + * + * @brief: Driver remove function + * + * @pdev: Platform Device pointer + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_remove(struct platform_device *pdev); + +#endif /* _CAM_VFE_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..77e2a059af57edc54d5921d40d4c65a759ac6666 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_cpas_api.h" +#include "cam_vfe_soc.h" +#include "cam_debug_util.h" + +static bool cam_vfe_cpas_cb(uint32_t client_handle, void *userdata, + struct cam_cpas_irq_data *irq_data) +{ + bool error_handled = false; + + if (!irq_data) + return error_handled; + + switch (irq_data->irq_type) { + case CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR: + case CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR: + case CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR: + case CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR: + CAM_ERR_RATE_LIMIT(CAM_ISP, + "IFE UBWC Encode error type=%d status=%x", + irq_data->irq_type, + irq_data->u.enc_err.encerr_status.value); + error_handled = true; + break; + default: + break; + } + + return error_handled; +} + +static int cam_vfe_get_dt_properties(struct cam_hw_soc_info *soc_info) +{ + int rc = 0, num_ubwc_cfg = 0, i = 0; + struct device_node *of_node = NULL; + struct platform_device *pdev = NULL; + struct cam_vfe_soc_private *vfe_soc_private; + + pdev = soc_info->pdev; + of_node = pdev->dev.of_node; + vfe_soc_private = soc_info->soc_private; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc) { + CAM_ERR(CAM_ISP, "Error! get DT properties failed rc=%d", rc); + return rc; + } + + vfe_soc_private->is_ife_lite = false; + if (strnstr(soc_info->compatible, "lite", + strlen(soc_info->compatible)) != NULL) { + vfe_soc_private->is_ife_lite = true; + goto end; + } + + switch (soc_info->hw_version) { + case CAM_CPAS_TITAN_480_V100: + num_ubwc_cfg = of_property_count_u32_elems(of_node, + "ubwc-static-cfg"); + + if (num_ubwc_cfg < 0 || num_ubwc_cfg > UBWC_STATIC_CONFIG_MAX) { + CAM_ERR(CAM_ISP, "wrong num_ubwc_cfg: %d", + num_ubwc_cfg); + rc = num_ubwc_cfg; + goto end; + } + + for (i = 0; i < num_ubwc_cfg; i++) { + rc = of_property_read_u32_index(of_node, + "ubwc-static-cfg", i, + &vfe_soc_private->ubwc_static_ctrl[i]); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "unable to read ubwc static config"); + break; + } + } + break; + default: + break; + } + +end: + return rc; +} + +static int cam_vfe_request_platform_resource( + struct cam_hw_soc_info *soc_info, + irq_handler_t vfe_irq_handler, void *irq_data) +{ + int rc = 0; + + rc = cam_soc_util_request_platform_resource(soc_info, vfe_irq_handler, + irq_data); + if (rc) + CAM_ERR(CAM_ISP, + "Error! Request platform resource failed rc=%d", rc); + + return rc; +} + +static int cam_vfe_release_platform_resource(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + + rc = cam_soc_util_release_platform_resource(soc_info); + if (rc) + CAM_ERR(CAM_ISP, + "Error! Release platform resource failed rc=%d", rc); + + return rc; +} + +int cam_vfe_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t vfe_irq_handler, void *irq_data) +{ + int rc = 0; + struct cam_vfe_soc_private *soc_private; + struct cam_cpas_register_params cpas_register_param; + + soc_private = kzalloc(sizeof(struct cam_vfe_soc_private), + GFP_KERNEL); + if (!soc_private) { + CAM_DBG(CAM_ISP, "Error! soc_private Alloc Failed"); + return -ENOMEM; + } + soc_info->soc_private = soc_private; + + rc = cam_cpas_get_cpas_hw_version(&soc_private->cpas_version); + if (rc) { + CAM_ERR(CAM_ISP, "Error! Invalid cpas version rc=%d", rc); + goto free_soc_private; + } + soc_info->hw_version = soc_private->cpas_version; + + rc = cam_vfe_get_dt_properties(soc_info); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Error! Get DT properties failed rc=%d", rc); + goto free_soc_private; + } + + rc = cam_soc_util_get_option_clk_by_name(soc_info, + CAM_VFE_DSP_CLK_NAME, &soc_private->dsp_clk, + &soc_private->dsp_clk_index, &soc_private->dsp_clk_rate); + if (rc) + CAM_WARN(CAM_ISP, "Option clk get failed with rc %d", rc); + + rc = cam_vfe_request_platform_resource(soc_info, vfe_irq_handler, + irq_data); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Error! Request platform resources failed rc=%d", rc); + goto free_soc_private; + } + + memset(&cpas_register_param, 0, sizeof(cpas_register_param)); + strlcpy(cpas_register_param.identifier, "ife", + CAM_HW_IDENTIFIER_LENGTH); + cpas_register_param.cell_index = soc_info->index; + cpas_register_param.dev = soc_info->dev; + cpas_register_param.cam_cpas_client_cb = cam_vfe_cpas_cb; + cpas_register_param.userdata = soc_info; + rc = cam_cpas_register_client(&cpas_register_param); + if (rc) { + CAM_ERR(CAM_ISP, "CPAS registration failed rc=%d", rc); + goto release_soc; + } else { + soc_private->cpas_handle = cpas_register_param.client_handle; + } + return rc; + +release_soc: + cam_soc_util_release_platform_resource(soc_info); +free_soc_private: + kfree(soc_private); + + return rc; +} + +int cam_vfe_deinit_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_vfe_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error! soc_info NULL"); + return -ENODEV; + } + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error! soc_private NULL"); + return -ENODEV; + } + + rc = cam_cpas_unregister_client(soc_private->cpas_handle); + if (rc) + CAM_ERR(CAM_ISP, "CPAS unregistration failed rc=%d", rc); + + rc = cam_vfe_release_platform_resource(soc_info); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Error! Release platform resources failed rc=%d", rc); + + rc = cam_soc_util_clk_put(&soc_private->dsp_clk); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Error Put dsp clk failed rc=%d", rc); + + kfree(soc_private); + + return rc; +} + +int cam_vfe_enable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_vfe_soc_private *soc_private; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error! Invalid params"); + rc = -EINVAL; + goto end; + } + soc_private = soc_info->soc_private; + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_LOWSVS_VOTE; + axi_vote.num_paths = 1; + if (strnstr(soc_info->compatible, "lite", + strlen(soc_info->compatible))) { + axi_vote.axi_path[0].path_data_type = + CAM_AXI_PATH_DATA_IFE_RDI1; + } else { + axi_vote.axi_path[0].path_data_type = + CAM_AXI_PATH_DATA_IFE_VID; + } + + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_WRITE; + axi_vote.axi_path[0].camnoc_bw = 10640000000L; + axi_vote.axi_path[0].mnoc_ab_bw = 10640000000L; + axi_vote.axi_path[0].mnoc_ib_bw = 10640000000L; + + rc = cam_cpas_start(soc_private->cpas_handle, &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_ISP, "Error! CPAS start failed rc=%d", rc); + rc = -EFAULT; + goto end; + } + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_TURBO_VOTE, true); + if (rc) { + CAM_ERR(CAM_ISP, "Error! enable platform failed rc=%d", rc); + goto stop_cpas; + } + + return rc; + +stop_cpas: + cam_cpas_stop(soc_private->cpas_handle); +end: + return rc; +} + +int cam_vfe_soc_enable_clk(struct cam_hw_soc_info *soc_info, + const char *clk_name) +{ + int rc = 0; + struct cam_vfe_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + rc = -EINVAL; + return rc; + } + soc_private = soc_info->soc_private; + + if (strcmp(clk_name, CAM_VFE_DSP_CLK_NAME) == 0) { + rc = cam_soc_util_clk_enable(soc_private->dsp_clk, + CAM_VFE_DSP_CLK_NAME, soc_private->dsp_clk_rate); + if (rc) + CAM_ERR(CAM_ISP, + "Error enable dsp clk failed rc=%d", rc); + } + + return rc; +} + +int cam_vfe_soc_disable_clk(struct cam_hw_soc_info *soc_info, + const char *clk_name) +{ + int rc = 0; + struct cam_vfe_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + rc = -EINVAL; + return rc; + } + soc_private = soc_info->soc_private; + + if (strcmp(clk_name, CAM_VFE_DSP_CLK_NAME) == 0) { + rc = cam_soc_util_clk_disable(soc_private->dsp_clk, + CAM_VFE_DSP_CLK_NAME); + if (rc) + CAM_ERR(CAM_ISP, + "Error enable dsp clk failed rc=%d", rc); + } + + return rc; +} + + +int cam_vfe_disable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_vfe_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error! Invalid params"); + rc = -EINVAL; + return rc; + } + soc_private = soc_info->soc_private; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) { + CAM_ERR(CAM_ISP, "Disable platform failed rc=%d", rc); + return rc; + } + + rc = cam_cpas_stop(soc_private->cpas_handle); + if (rc) { + CAM_ERR(CAM_ISP, "Error! CPAS stop failed rc=%d", rc); + return rc; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..64d9de084ec1e6b91a5385ed4590200ad2d049b9 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_SOC_H_ +#define _CAM_VFE_SOC_H_ + +#include "cam_soc_util.h" +#include "cam_isp_hw.h" + +#define CAM_VFE_DSP_CLK_NAME "ife_dsp_clk" + +#define UBWC_STATIC_CONFIG_MAX 2 + +/* + * struct cam_vfe_soc_private: + * + * @Brief: Private SOC data specific to VFE HW Driver + * + * @cpas_handle: Handle returned on registering with CPAS driver. + * This handle is used for all further interface + * with CPAS. + * @cpas_version: Has cpas version read from Hardware + * @ubwc_static_ctrl: UBWC static control configuration + * @is_ife_lite: Flag to indicate full vs lite IFE + */ +struct cam_vfe_soc_private { + uint32_t cpas_handle; + uint32_t cpas_version; + struct clk *dsp_clk; + int32_t dsp_clk_index; + int32_t dsp_clk_rate; + uint32_t ubwc_static_ctrl[UBWC_STATIC_CONFIG_MAX]; + bool is_ife_lite; +}; + +/* + * cam_vfe_init_soc_resources() + * + * @Brief: Initialize SOC resources including private data + * + * @soc_info: Device soc information + * @handler: Irq handler function pointer + * @irq_data: Irq handler function Callback data + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t vfe_irq_handler, void *irq_data); + +/* + * cam_vfe_deinit_soc_resources() + * + * @Brief: Deinitialize SOC resources including private data + * + * @soc_info: Device soc information + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_deinit_soc_resources(struct cam_hw_soc_info *soc_info); + +/* + * cam_vfe_enable_soc_resources() + * + * @brief: Enable regulator, irq resources, start CPAS + * + * @soc_info: Device soc information + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_enable_soc_resources(struct cam_hw_soc_info *soc_info); + +/* + * cam_vfe_disable_soc_resources() + * + * @brief: Disable regulator, irq resources, stop CPAS + * + * @soc_info: Device soc information + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_disable_soc_resources(struct cam_hw_soc_info *soc_info); + +/* + * cam_vfe_soc_enable_clk() + * + * @brief: Enable clock with given name + * + * @soc_info: Device soc information + * @clk_name: Name of clock to enable + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_soc_enable_clk(struct cam_hw_soc_info *soc_info, + const char *clk_name); + +/* + * cam_vfe_soc_disable_dsp_clk() + * + * @brief: Disable clock with given name + * + * @soc_info: Device soc information + * @clk_name: Name of clock to enable + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_soc_disable_clk(struct cam_hw_soc_info *soc_info, + const char *clk_name); + +#endif /* _CAM_VFE_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..4b8ac355608f6c3241d944d8e74e3b743c3a72f8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.c new file mode 100644 index 0000000000000000000000000000000000000000..5336352a479780d93b5e90c69d38966c5827b532 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_vfe170.h" +#include "cam_vfe175.h" +#include "cam_vfe175_130.h" +#include "cam_vfe480.h" +#include "cam_vfe_lite17x.h" +#include "cam_vfe_lite48x.h" +#include "cam_vfe_hw_intf.h" +#include "cam_vfe_core.h" +#include "cam_vfe_dev.h" + +static const struct of_device_id cam_vfe_dt_match[] = { + { + .compatible = "qcom,vfe170", + .data = &cam_vfe170_hw_info, + }, + { + .compatible = "qcom,vfe175", + .data = &cam_vfe175_hw_info, + }, + { + .compatible = "qcom,vfe175_130", + .data = &cam_vfe175_130_hw_info, + }, + { + .compatible = "qcom,vfe480", + .data = &cam_vfe480_hw_info, + }, + { + .compatible = "qcom,vfe-lite170", + .data = &cam_vfe_lite17x_hw_info, + }, + { + .compatible = "qcom,vfe-lite175", + .data = &cam_vfe_lite17x_hw_info, + }, + { + .compatible = "qcom,vfe-lite480", + .data = &cam_vfe_lite48x_hw_info, + }, + {} +}; +MODULE_DEVICE_TABLE(of, cam_vfe_dt_match); + +static struct platform_driver cam_vfe_driver = { + .probe = cam_vfe_probe, + .remove = cam_vfe_remove, + .driver = { + .name = "cam_vfe", + .owner = THIS_MODULE, + .of_match_table = cam_vfe_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_vfe_init_module(void) +{ + return platform_driver_register(&cam_vfe_driver); +} + +static void __exit cam_vfe_exit_module(void) +{ + platform_driver_unregister(&cam_vfe_driver); +} + +module_init(cam_vfe_init_module); +module_exit(cam_vfe_exit_module); +MODULE_DESCRIPTION("CAM VFE driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe170.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe170.h new file mode 100644 index 0000000000000000000000000000000000000000..63df625221cc4beb4afcbcef18f0010f8b765782 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe170.h @@ -0,0 +1,871 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE170_H_ +#define _CAM_VFE170_H_ + +#include "cam_vfe_camif_ver2.h" +#include "cam_vfe_bus_ver2.h" +#include "cam_irq_controller.h" +#include "cam_vfe_top_ver2.h" +#include "cam_vfe_core.h" + +static struct cam_irq_register_set vfe170_top_irq_reg_set[2] = { + { + .mask_reg_offset = 0x0000005C, + .clear_reg_offset = 0x00000064, + .status_reg_offset = 0x0000006C, + }, + { + .mask_reg_offset = 0x00000060, + .clear_reg_offset = 0x00000068, + .status_reg_offset = 0x00000070, + }, +}; + +static struct cam_irq_controller_reg_info vfe170_top_irq_reg_info = { + .num_registers = 2, + .irq_reg_set = vfe170_top_irq_reg_set, + .global_clear_offset = 0x00000058, + .global_clear_bitmask = 0x00000001, +}; + +static struct cam_vfe_camif_ver2_reg vfe170_camif_reg = { + .camif_cmd = 0x00000478, + .camif_config = 0x0000047C, + .line_skip_pattern = 0x00000488, + .pixel_skip_pattern = 0x0000048C, + .skip_period = 0x00000490, + .irq_subsample_pattern = 0x0000049C, + .epoch_irq = 0x000004A0, + .raw_crop_width_cfg = 0x00000CE4, + .raw_crop_height_cfg = 0x00000CE8, + .reg_update_cmd = 0x000004AC, + .vfe_diag_config = 0x00000C48, + .vfe_diag_sensor_status = 0x00000C4C, +}; + +static struct cam_vfe_camif_reg_data vfe_170_camif_reg_data = { + .raw_crop_first_pixel_shift = 16, + .raw_crop_first_pixel_mask = 0xFFFF, + .raw_crop_last_pixel_shift = 0x0, + .raw_crop_last_pixel_mask = 0x3FFF, + .raw_crop_first_line_shift = 16, + .raw_crop_first_line_mask = 0xFFFF, + .raw_crop_last_line_shift = 0, + .raw_crop_last_line_mask = 0x3FFF, + .input_mux_sel_shift = 5, + .input_mux_sel_mask = 0x3, + .extern_reg_update_shift = 4, + .extern_reg_update_mask = 1, + .pixel_pattern_shift = 0, + .pixel_pattern_mask = 0x7, + .dsp_mode_shift = 23, + .dsp_mode_mask = 0x1, + .dsp_en_shift = 3, + .dsp_en_mask = 0x1, + .reg_update_cmd_data = 0x1, + .epoch_line_cfg = 0x00140014, + .sof_irq_mask = 0x00000001, + .epoch0_irq_mask = 0x00000004, + .reg_update_irq_mask = 0x00000010, + .eof_irq_mask = 0x00000002, + .error_irq_mask0 = 0x0003FC00, + .error_irq_mask1 = 0x0FFF7E80, + .enable_diagnostic_hw = 0x1, +}; + +struct cam_vfe_top_ver2_reg_offset_module_ctrl lens_170_reg = { + .reset = 0x0000001C, + .cgc_ovd = 0x0000002C, + .enable = 0x00000040, +}; + +struct cam_vfe_top_ver2_reg_offset_module_ctrl stats_170_reg = { + .reset = 0x00000020, + .cgc_ovd = 0x00000030, + .enable = 0x00000044, +}; + +struct cam_vfe_top_ver2_reg_offset_module_ctrl color_170_reg = { + .reset = 0x00000024, + .cgc_ovd = 0x00000034, + .enable = 0x00000048, +}; + +struct cam_vfe_top_ver2_reg_offset_module_ctrl zoom_170_reg = { + .reset = 0x00000028, + .cgc_ovd = 0x00000038, + .enable = 0x0000004C, +}; + +static struct cam_vfe_top_ver2_reg_offset_common vfe170_top_common_reg = { + .hw_version = 0x00000000, + .hw_capability = 0x00000004, + .lens_feature = 0x00000008, + .stats_feature = 0x0000000C, + .color_feature = 0x00000010, + .zoom_feature = 0x00000014, + .global_reset_cmd = 0x00000018, + .module_ctrl = { + &lens_170_reg, + &stats_170_reg, + &color_170_reg, + &zoom_170_reg, + }, + .bus_cgc_ovd = 0x0000003C, + .core_cfg = 0x00000050, + .three_D_cfg = 0x00000054, + .violation_status = 0x0000007C, + .reg_update_cmd = 0x000004AC, +}; + +static struct cam_vfe_rdi_ver2_reg vfe170_rdi_reg = { + .reg_update_cmd = 0x000004AC, +}; + +static struct cam_vfe_rdi_reg_data vfe_170_rdi_0_data = { + .reg_update_cmd_data = 0x2, + .sof_irq_mask = 0x8000000, + .reg_update_irq_mask = 0x20, +}; + +static struct cam_vfe_rdi_reg_data vfe_170_rdi_1_data = { + .reg_update_cmd_data = 0x4, + .sof_irq_mask = 0x10000000, + .reg_update_irq_mask = 0x40, +}; + +static struct cam_vfe_rdi_reg_data vfe_170_rdi_2_data = { + .reg_update_cmd_data = 0x8, + .sof_irq_mask = 0x20000000, + .reg_update_irq_mask = 0x80, +}; + +struct cam_vfe_top_dump_data vfe170_dump_data = { + .num_reg_dump_entries = 2, + .num_lut_dump_entries = 1, + .dmi_cfg = 0xc24, + .dmi_addr = 0xc28, + .dmi_data_path_hi = 0xc2C, + .dmi_data_path_lo = 0xc30, + .reg_entry = { + { + .reg_dump_start = 0x0, + .reg_dump_end = 0x1164, + }, + { + .reg_dump_start = 0x2000, + .reg_dump_end = 0x397C, + }, + }, + .lut_entry = { + { + .lut_word_size = 64, + .lut_bank_sel = 0x40, + .lut_addr_size = 180, + }, + }, +}; + +static struct cam_vfe_top_ver2_hw_info vfe170_top_hw_info = { + .common_reg = &vfe170_top_common_reg, + .camif_hw_info = { + .common_reg = &vfe170_top_common_reg, + .camif_reg = &vfe170_camif_reg, + .reg_data = &vfe_170_camif_reg_data, + }, + .camif_lite_hw_info = { + .common_reg = NULL, + .camif_lite_reg = NULL, + .reg_data = NULL, + }, + .rdi_hw_info = { + .common_reg = &vfe170_top_common_reg, + .rdi_reg = &vfe170_rdi_reg, + .reg_data = { + &vfe_170_rdi_0_data, + &vfe_170_rdi_1_data, + &vfe_170_rdi_2_data, + NULL, + }, + }, + .num_mux = 4, + .mux_type = { + CAM_VFE_CAMIF_VER_2_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + }, + .dump_data = &vfe170_dump_data, +}; + +static struct cam_irq_register_set vfe170_bus_irq_reg[3] = { + { + .mask_reg_offset = 0x00002044, + .clear_reg_offset = 0x00002050, + .status_reg_offset = 0x0000205C, + }, + { + .mask_reg_offset = 0x00002048, + .clear_reg_offset = 0x00002054, + .status_reg_offset = 0x00002060, + }, + { + .mask_reg_offset = 0x0000204C, + .clear_reg_offset = 0x00002058, + .status_reg_offset = 0x00002064, + }, +}; + +static struct cam_vfe_bus_ver2_reg_offset_ubwc_client ubwc_regs_client_3 = { + .tile_cfg = 0x0000252C, + .h_init = 0x00002530, + .v_init = 0x00002534, + .meta_addr = 0x00002538, + .meta_offset = 0x0000253C, + .meta_stride = 0x00002540, + .mode_cfg_0 = 0x00002544, + .bw_limit = 0x000025A0, +}; + +static struct cam_vfe_bus_ver2_reg_offset_ubwc_client ubwc_regs_client_4 = { + .tile_cfg = 0x0000262C, + .h_init = 0x00002630, + .v_init = 0x00002634, + .meta_addr = 0x00002638, + .meta_offset = 0x0000263C, + .meta_stride = 0x00002640, + .mode_cfg_0 = 0x00002644, + .bw_limit = 0x000026A0, +}; + +static struct cam_vfe_bus_ver2_hw_info vfe170_bus_hw_info = { + .common_reg = { + .hw_version = 0x00002000, + .hw_capability = 0x00002004, + .sw_reset = 0x00002008, + .cgc_ovd = 0x0000200C, + .pwr_iso_cfg = 0x000020CC, + .dual_master_comp_cfg = 0x00002028, + .irq_reg_info = { + .num_registers = 3, + .irq_reg_set = vfe170_bus_irq_reg, + .global_clear_offset = 0x00002068, + .global_clear_bitmask = 0x00000001, + }, + .comp_error_status = 0x0000206C, + .comp_ovrwr_status = 0x00002070, + .dual_comp_error_status = 0x00002074, + .dual_comp_ovrwr_status = 0x00002078, + .addr_sync_cfg = 0x0000207C, + .addr_sync_frame_hdr = 0x00002080, + .addr_sync_no_sync = 0x00002084, + .debug_status_cfg = 0x0000226C, + .debug_status_0 = 0x00002270, + }, + .num_client = 20, + .bus_client_reg = { + /* BUS Client 0 */ + { + .status0 = 0x00002200, + .status1 = 0x00002204, + .cfg = 0x00002208, + .header_addr = 0x0000220C, + .header_cfg = 0x00002210, + .image_addr = 0x00002214, + .image_addr_offset = 0x00002218, + .buffer_width_cfg = 0x0000221C, + .buffer_height_cfg = 0x00002220, + .packer_cfg = 0x00002224, + .stride = 0x00002228, + .irq_subsample_period = 0x00002248, + .irq_subsample_pattern = 0x0000224C, + .framedrop_period = 0x00002250, + .framedrop_pattern = 0x00002254, + .frame_inc = 0x00002258, + .burst_limit = 0x0000225C, + .ubwc_regs = NULL, + }, + /* BUS Client 1 */ + { + .status0 = 0x00002300, + .status1 = 0x00002304, + .cfg = 0x00002308, + .header_addr = 0x0000230C, + .header_cfg = 0x00002310, + .image_addr = 0x00002314, + .image_addr_offset = 0x00002318, + .buffer_width_cfg = 0x0000231C, + .buffer_height_cfg = 0x00002320, + .packer_cfg = 0x00002324, + .stride = 0x00002328, + .irq_subsample_period = 0x00002348, + .irq_subsample_pattern = 0x0000234C, + .framedrop_period = 0x00002350, + .framedrop_pattern = 0x00002354, + .frame_inc = 0x00002358, + .burst_limit = 0x0000235C, + .ubwc_regs = NULL, + }, + /* BUS Client 2 */ + { + .status0 = 0x00002400, + .status1 = 0x00002404, + .cfg = 0x00002408, + .header_addr = 0x0000240C, + .header_cfg = 0x00002410, + .image_addr = 0x00002414, + .image_addr_offset = 0x00002418, + .buffer_width_cfg = 0x0000241C, + .buffer_height_cfg = 0x00002420, + .packer_cfg = 0x00002424, + .stride = 0x00002428, + .irq_subsample_period = 0x00002448, + .irq_subsample_pattern = 0x0000244C, + .framedrop_period = 0x00002450, + .framedrop_pattern = 0x00002454, + .frame_inc = 0x00002458, + .burst_limit = 0x0000245C, + .ubwc_regs = NULL, + }, + /* BUS Client 3 */ + { + .status0 = 0x00002500, + .status1 = 0x00002504, + .cfg = 0x00002508, + .header_addr = 0x0000250C, + .header_cfg = 0x00002510, + .image_addr = 0x00002514, + .image_addr_offset = 0x00002518, + .buffer_width_cfg = 0x0000251C, + .buffer_height_cfg = 0x00002520, + .packer_cfg = 0x00002524, + .stride = 0x00002528, + .irq_subsample_period = 0x00002548, + .irq_subsample_pattern = 0x0000254C, + .framedrop_period = 0x00002550, + .framedrop_pattern = 0x00002554, + .frame_inc = 0x00002558, + .burst_limit = 0x0000255C, + .ubwc_regs = &ubwc_regs_client_3, + }, + /* BUS Client 4 */ + { + .status0 = 0x00002600, + .status1 = 0x00002604, + .cfg = 0x00002608, + .header_addr = 0x0000260C, + .header_cfg = 0x00002610, + .image_addr = 0x00002614, + .image_addr_offset = 0x00002618, + .buffer_width_cfg = 0x0000261C, + .buffer_height_cfg = 0x00002620, + .packer_cfg = 0x00002624, + .stride = 0x00002628, + .irq_subsample_period = 0x00002648, + .irq_subsample_pattern = 0x0000264C, + .framedrop_period = 0x00002650, + .framedrop_pattern = 0x00002654, + .frame_inc = 0x00002658, + .burst_limit = 0x0000265C, + .ubwc_regs = &ubwc_regs_client_4, + }, + /* BUS Client 5 */ + { + .status0 = 0x00002700, + .status1 = 0x00002704, + .cfg = 0x00002708, + .header_addr = 0x0000270C, + .header_cfg = 0x00002710, + .image_addr = 0x00002714, + .image_addr_offset = 0x00002718, + .buffer_width_cfg = 0x0000271C, + .buffer_height_cfg = 0x00002720, + .packer_cfg = 0x00002724, + .stride = 0x00002728, + .irq_subsample_period = 0x00002748, + .irq_subsample_pattern = 0x0000274C, + .framedrop_period = 0x00002750, + .framedrop_pattern = 0x00002754, + .frame_inc = 0x00002758, + .burst_limit = 0x0000275C, + .ubwc_regs = NULL, + }, + /* BUS Client 6 */ + { + .status0 = 0x00002800, + .status1 = 0x00002804, + .cfg = 0x00002808, + .header_addr = 0x0000280C, + .header_cfg = 0x00002810, + .image_addr = 0x00002814, + .image_addr_offset = 0x00002818, + .buffer_width_cfg = 0x0000281C, + .buffer_height_cfg = 0x00002820, + .packer_cfg = 0x00002824, + .stride = 0x00002828, + .irq_subsample_period = 0x00002848, + .irq_subsample_pattern = 0x0000284C, + .framedrop_period = 0x00002850, + .framedrop_pattern = 0x00002854, + .frame_inc = 0x00002858, + .burst_limit = 0x0000285C, + .ubwc_regs = NULL, + }, + /* BUS Client 7 */ + { + .status0 = 0x00002900, + .status1 = 0x00002904, + .cfg = 0x00002908, + .header_addr = 0x0000290C, + .header_cfg = 0x00002910, + .image_addr = 0x00002914, + .image_addr_offset = 0x00002918, + .buffer_width_cfg = 0x0000291C, + .buffer_height_cfg = 0x00002920, + .packer_cfg = 0x00002924, + .stride = 0x00002928, + .irq_subsample_period = 0x00002948, + .irq_subsample_pattern = 0x0000294C, + .framedrop_period = 0x00002950, + .framedrop_pattern = 0x00002954, + .frame_inc = 0x00002958, + .burst_limit = 0x0000295C, + .ubwc_regs = NULL, + }, + /* BUS Client 8 */ + { + .status0 = 0x00002A00, + .status1 = 0x00002A04, + .cfg = 0x00002A08, + .header_addr = 0x00002A0C, + .header_cfg = 0x00002A10, + .image_addr = 0x00002A14, + .image_addr_offset = 0x00002A18, + .buffer_width_cfg = 0x00002A1C, + .buffer_height_cfg = 0x00002A20, + .packer_cfg = 0x00002A24, + .stride = 0x00002A28, + .irq_subsample_period = 0x00002A48, + .irq_subsample_pattern = 0x00002A4C, + .framedrop_period = 0x00002A50, + .framedrop_pattern = 0x00002A54, + .frame_inc = 0x00002A58, + .burst_limit = 0x00002A5C, + .ubwc_regs = NULL, + }, + /* BUS Client 9 */ + { + .status0 = 0x00002B00, + .status1 = 0x00002B04, + .cfg = 0x00002B08, + .header_addr = 0x00002B0C, + .header_cfg = 0x00002B10, + .image_addr = 0x00002B14, + .image_addr_offset = 0x00002B18, + .buffer_width_cfg = 0x00002B1C, + .buffer_height_cfg = 0x00002B20, + .packer_cfg = 0x00002B24, + .stride = 0x00002B28, + .irq_subsample_period = 0x00002B48, + .irq_subsample_pattern = 0x00002B4C, + .framedrop_period = 0x00002B50, + .framedrop_pattern = 0x00002B54, + .frame_inc = 0x00002B58, + .burst_limit = 0x00002B5C, + .ubwc_regs = NULL, + }, + /* BUS Client 10 */ + { + .status0 = 0x00002C00, + .status1 = 0x00002C04, + .cfg = 0x00002C08, + .header_addr = 0x00002C0C, + .header_cfg = 0x00002C10, + .image_addr = 0x00002C14, + .image_addr_offset = 0x00002C18, + .buffer_width_cfg = 0x00002C1C, + .buffer_height_cfg = 0x00002C20, + .packer_cfg = 0x00002C24, + .stride = 0x00002C28, + .irq_subsample_period = 0x00002C48, + .irq_subsample_pattern = 0x00002C4C, + .framedrop_period = 0x00002C50, + .framedrop_pattern = 0x00002C54, + .frame_inc = 0x00002C58, + .burst_limit = 0x00002C5C, + .ubwc_regs = NULL, + }, + /* BUS Client 11 */ + { + .status0 = 0x00002D00, + .status1 = 0x00002D04, + .cfg = 0x00002D08, + .header_addr = 0x00002D0C, + .header_cfg = 0x00002D10, + .image_addr = 0x00002D14, + .image_addr_offset = 0x00002D18, + .buffer_width_cfg = 0x00002D1C, + .buffer_height_cfg = 0x00002D20, + .packer_cfg = 0x00002D24, + .stride = 0x00002D28, + .irq_subsample_period = 0x00002D48, + .irq_subsample_pattern = 0x00002D4C, + .framedrop_period = 0x00002D50, + .framedrop_pattern = 0x00002D54, + .frame_inc = 0x00002D58, + .burst_limit = 0x00002D5C, + .ubwc_regs = NULL, + }, + /* BUS Client 12 */ + { + .status0 = 0x00002E00, + .status1 = 0x00002E04, + .cfg = 0x00002E08, + .header_addr = 0x00002E0C, + .header_cfg = 0x00002E10, + .image_addr = 0x00002E14, + .image_addr_offset = 0x00002E18, + .buffer_width_cfg = 0x00002E1C, + .buffer_height_cfg = 0x00002E20, + .packer_cfg = 0x00002E24, + .stride = 0x00002E28, + .irq_subsample_period = 0x00002E48, + .irq_subsample_pattern = 0x00002E4C, + .framedrop_period = 0x00002E50, + .framedrop_pattern = 0x00002E54, + .frame_inc = 0x00002E58, + .burst_limit = 0x00002E5C, + .ubwc_regs = NULL, + }, + /* BUS Client 13 */ + { + .status0 = 0x00002F00, + .status1 = 0x00002F04, + .cfg = 0x00002F08, + .header_addr = 0x00002F0C, + .header_cfg = 0x00002F10, + .image_addr = 0x00002F14, + .image_addr_offset = 0x00002F18, + .buffer_width_cfg = 0x00002F1C, + .buffer_height_cfg = 0x00002F20, + .packer_cfg = 0x00002F24, + .stride = 0x00002F28, + .irq_subsample_period = 0x00002F48, + .irq_subsample_pattern = 0x00002F4C, + .framedrop_period = 0x00002F50, + .framedrop_pattern = 0x00002F54, + .frame_inc = 0x00002F58, + .burst_limit = 0x00002F5C, + .ubwc_regs = NULL, + }, + /* BUS Client 14 */ + { + .status0 = 0x00003000, + .status1 = 0x00003004, + .cfg = 0x00003008, + .header_addr = 0x0000300C, + .header_cfg = 0x00003010, + .image_addr = 0x00003014, + .image_addr_offset = 0x00003018, + .buffer_width_cfg = 0x0000301C, + .buffer_height_cfg = 0x00003020, + .packer_cfg = 0x00003024, + .stride = 0x00003028, + .irq_subsample_period = 0x00003048, + .irq_subsample_pattern = 0x0000304C, + .framedrop_period = 0x00003050, + .framedrop_pattern = 0x00003054, + .frame_inc = 0x00003058, + .burst_limit = 0x0000305C, + .ubwc_regs = NULL, + }, + /* BUS Client 15 */ + { + .status0 = 0x00003100, + .status1 = 0x00003104, + .cfg = 0x00003108, + .header_addr = 0x0000310C, + .header_cfg = 0x00003110, + .image_addr = 0x00003114, + .image_addr_offset = 0x00003118, + .buffer_width_cfg = 0x0000311C, + .buffer_height_cfg = 0x00003120, + .packer_cfg = 0x00003124, + .stride = 0x00003128, + .irq_subsample_period = 0x00003148, + .irq_subsample_pattern = 0x0000314C, + .framedrop_period = 0x00003150, + .framedrop_pattern = 0x00003154, + .frame_inc = 0x00003158, + .burst_limit = 0x0000315C, + .ubwc_regs = NULL, + }, + /* BUS Client 16 */ + { + .status0 = 0x00003200, + .status1 = 0x00003204, + .cfg = 0x00003208, + .header_addr = 0x0000320C, + .header_cfg = 0x00003210, + .image_addr = 0x00003214, + .image_addr_offset = 0x00003218, + .buffer_width_cfg = 0x0000321C, + .buffer_height_cfg = 0x00003220, + .packer_cfg = 0x00003224, + .stride = 0x00003228, + .irq_subsample_period = 0x00003248, + .irq_subsample_pattern = 0x0000324C, + .framedrop_period = 0x00003250, + .framedrop_pattern = 0x00003254, + .frame_inc = 0x00003258, + .burst_limit = 0x0000325C, + .ubwc_regs = NULL, + }, + /* BUS Client 17 */ + { + .status0 = 0x00003300, + .status1 = 0x00003304, + .cfg = 0x00003308, + .header_addr = 0x0000330C, + .header_cfg = 0x00003310, + .image_addr = 0x00003314, + .image_addr_offset = 0x00003318, + .buffer_width_cfg = 0x0000331C, + .buffer_height_cfg = 0x00003320, + .packer_cfg = 0x00003324, + .stride = 0x00003328, + .irq_subsample_period = 0x00003348, + .irq_subsample_pattern = 0x0000334C, + .framedrop_period = 0x00003350, + .framedrop_pattern = 0x00003354, + .frame_inc = 0x00003358, + .burst_limit = 0x0000335C, + .ubwc_regs = NULL, + }, + /* BUS Client 18 */ + { + .status0 = 0x00003400, + .status1 = 0x00003404, + .cfg = 0x00003408, + .header_addr = 0x0000340C, + .header_cfg = 0x00003410, + .image_addr = 0x00003414, + .image_addr_offset = 0x00003418, + .buffer_width_cfg = 0x0000341C, + .buffer_height_cfg = 0x00003420, + .packer_cfg = 0x00003424, + .stride = 0x00003428, + .irq_subsample_period = 0x00003448, + .irq_subsample_pattern = 0x0000344C, + .framedrop_period = 0x00003450, + .framedrop_pattern = 0x00003454, + .frame_inc = 0x00003458, + .burst_limit = 0x0000345C, + .ubwc_regs = NULL, + }, + /* BUS Client 19 */ + { + .status0 = 0x00003500, + .status1 = 0x00003504, + .cfg = 0x00003508, + .header_addr = 0x0000350C, + .header_cfg = 0x00003510, + .image_addr = 0x00003514, + .image_addr_offset = 0x00003518, + .buffer_width_cfg = 0x0000351C, + .buffer_height_cfg = 0x00003520, + .packer_cfg = 0x00003524, + .stride = 0x00003528, + .irq_subsample_period = 0x00003548, + .irq_subsample_pattern = 0x0000354C, + .framedrop_period = 0x00003550, + .framedrop_pattern = 0x00003554, + .frame_inc = 0x00003558, + .burst_limit = 0x0000355C, + .ubwc_regs = NULL, + }, + }, + .comp_grp_reg = { + /* CAM_VFE_BUS_VER2_COMP_GRP_0 */ + { + .comp_mask = 0x00002010, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_1 */ + { + .comp_mask = 0x00002014, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_2 */ + { + .comp_mask = 0x00002018, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_3 */ + { + .comp_mask = 0x0000201C, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_4 */ + { + .comp_mask = 0x00002020, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_5 */ + { + .comp_mask = 0x00002024, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0 */ + { + .comp_mask = 0x0000202C, + .addr_sync_mask = 0x00002088, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_1 */ + { + .comp_mask = 0x00002030, + .addr_sync_mask = 0x0000208C, + + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_2 */ + { + .comp_mask = 0x00002034, + .addr_sync_mask = 0x00002090, + + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_3 */ + { + .comp_mask = 0x00002038, + .addr_sync_mask = 0x00002094, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_4 */ + { + .comp_mask = 0x0000203C, + .addr_sync_mask = 0x00002098, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_5 */ + { + .comp_mask = 0x00002040, + .addr_sync_mask = 0x0000209C, + }, + }, + .num_out = 18, + .vfe_out_hw_info = { + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI0, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI1, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI2, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_FULL, + .max_width = 4096, + .max_height = 4096, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_DS4, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_DS16, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RAW_DUMP, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_FD, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_PDAF, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_TL_BG, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_AWB_BG, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_RS, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_CS, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_IHIST, + .max_width = -1, + .max_height = -1, + }, + }, +}; + +struct cam_vfe_hw_info cam_vfe170_hw_info = { + .irq_reg_info = &vfe170_top_irq_reg_info, + + .bus_version = CAM_VFE_BUS_VER_2_0, + .bus_hw_info = &vfe170_bus_hw_info, + + .top_version = CAM_VFE_TOP_VER_2_0, + .top_hw_info = &vfe170_top_hw_info, + + .camif_version = CAM_VFE_CAMIF_VER_2_0, + .camif_reg = &vfe170_camif_reg, + + .camif_lite_version = 0, + .camif_reg = NULL, + +}; + +#endif /* _CAM_VFE170_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175.h new file mode 100644 index 0000000000000000000000000000000000000000..4e9a1e23286086cab492f7b2969e23665795cfef --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175.h @@ -0,0 +1,1041 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE175_H_ +#define _CAM_VFE175_H_ + +#include "cam_vfe_camif_ver2.h" +#include "cam_vfe_camif_lite_ver2.h" +#include "cam_vfe_bus_ver2.h" +#include "cam_irq_controller.h" +#include "cam_vfe_top_ver2.h" +#include "cam_vfe_core.h" + +static struct cam_irq_register_set vfe175_top_irq_reg_set[2] = { + { + .mask_reg_offset = 0x0000005C, + .clear_reg_offset = 0x00000064, + .status_reg_offset = 0x0000006C, + }, + { + .mask_reg_offset = 0x00000060, + .clear_reg_offset = 0x00000068, + .status_reg_offset = 0x00000070, + }, +}; + +static struct cam_irq_controller_reg_info vfe175_top_irq_reg_info = { + .num_registers = 2, + .irq_reg_set = vfe175_top_irq_reg_set, + .global_clear_offset = 0x00000058, + .global_clear_bitmask = 0x00000001, +}; + +static struct cam_vfe_camif_ver2_reg vfe175_camif_reg = { + .camif_cmd = 0x00000478, + .camif_config = 0x0000047C, + .line_skip_pattern = 0x00000488, + .pixel_skip_pattern = 0x0000048C, + .skip_period = 0x00000490, + .irq_subsample_pattern = 0x0000049C, + .epoch_irq = 0x000004A0, + .raw_crop_width_cfg = 0x00000CE4, + .raw_crop_height_cfg = 0x00000CE8, + .reg_update_cmd = 0x000004AC, + .vfe_diag_config = 0x00000C48, + .vfe_diag_sensor_status = 0x00000C4C, +}; + +static struct cam_vfe_camif_reg_data vfe_175_camif_reg_data = { + .raw_crop_first_pixel_shift = 16, + .raw_crop_first_pixel_mask = 0xFFFF, + .raw_crop_last_pixel_shift = 0x0, + .raw_crop_last_pixel_mask = 0x3FFF, + .raw_crop_first_line_shift = 16, + .raw_crop_first_line_mask = 0xFFFF, + .raw_crop_last_line_shift = 0, + .raw_crop_last_line_mask = 0x3FFF, + .input_mux_sel_shift = 5, + .input_mux_sel_mask = 0x3, + .extern_reg_update_shift = 4, + .extern_reg_update_mask = 1, + .pixel_pattern_shift = 0, + .pixel_pattern_mask = 0x7, + .dsp_mode_shift = 23, + .dsp_mode_mask = 0x1, + .dsp_en_shift = 3, + .dsp_en_mask = 0x1, + .reg_update_cmd_data = 0x1, + .epoch_line_cfg = 0x00140014, + .sof_irq_mask = 0x00000001, + .epoch0_irq_mask = 0x00000004, + .reg_update_irq_mask = 0x00000010, + .eof_irq_mask = 0x00000002, + .error_irq_mask0 = 0x0003FC00, + .error_irq_mask1 = 0xEFFF7E80, + .subscribe_irq_mask0 = 0x00000017, + .subscribe_irq_mask1 = 0x00000000, + .enable_diagnostic_hw = 0x1, +}; + +static struct cam_vfe_camif_lite_ver2_reg vfe175_camif_lite_reg = { + .camif_lite_cmd = 0x00000FC0, + .camif_lite_config = 0x00000FC4, + .lite_skip_period = 0x00000FC8, + .lite_irq_subsample_pattern = 0x00000FCC, + .lite_epoch_irq = 0x00000FD0, + .reg_update_cmd = 0x000004AC, +}; + +static struct cam_vfe_camif_lite_ver2_reg_data vfe175_camif_lite_reg_data = { + .dual_pd_reg_update_cmd_data = 0x20, + .lite_epoch_line_cfg = 0x00140014, + .lite_sof_irq_mask = 0x00040000, + .lite_epoch0_irq_mask = 0x00100000, + .dual_pd_reg_upd_irq_mask = 0x04000000, + .lite_eof_irq_mask = 0x00080000, + .lite_err_irq_mask0 = 0x00400000, + .lite_err_irq_mask1 = 0x00004100, + .lite_subscribe_irq_mask0 = 0x001C0000, + .lite_subscribe_irq_mask1 = 0x0, + .extern_reg_update_shift = 4, + .dual_pd_path_sel_shift = 24, +}; + +struct cam_vfe_top_ver2_reg_offset_module_ctrl lens_175_reg = { + .reset = 0x0000001C, + .cgc_ovd = 0x0000002C, + .enable = 0x00000040, +}; + +struct cam_vfe_top_ver2_reg_offset_module_ctrl stats_175_reg = { + .reset = 0x00000020, + .cgc_ovd = 0x00000030, + .enable = 0x00000044, +}; + +struct cam_vfe_top_ver2_reg_offset_module_ctrl color_175_reg = { + .reset = 0x00000024, + .cgc_ovd = 0x00000034, + .enable = 0x00000048, +}; + +struct cam_vfe_top_ver2_reg_offset_module_ctrl zoom_175_reg = { + .reset = 0x00000028, + .cgc_ovd = 0x00000038, + .enable = 0x0000004C, +}; + +static struct cam_vfe_top_ver2_reg_offset_common vfe175_top_common_reg = { + .hw_version = 0x00000000, + .hw_capability = 0x00000004, + .lens_feature = 0x00000008, + .stats_feature = 0x0000000C, + .color_feature = 0x00000010, + .zoom_feature = 0x00000014, + .global_reset_cmd = 0x00000018, + .module_ctrl = { + &lens_175_reg, + &stats_175_reg, + &color_175_reg, + &zoom_175_reg, + }, + .bus_cgc_ovd = 0x0000003C, + .core_cfg = 0x00000050, + .three_D_cfg = 0x00000054, + .violation_status = 0x0000007C, + .reg_update_cmd = 0x000004AC, +}; + +static struct cam_vfe_rdi_ver2_reg vfe175_rdi_reg = { + .reg_update_cmd = 0x000004AC, +}; + +static struct cam_vfe_rdi_common_reg_data vfe175_rdi_reg_data = { + .subscribe_irq_mask0 = 0x780001E0, + .subscribe_irq_mask1 = 0x0, + .error_irq_mask0 = 0x0, + .error_irq_mask1 = 0x3C, +}; + +static struct cam_vfe_rdi_reg_data vfe_175_rdi_0_data = { + .reg_update_cmd_data = 0x2, + .sof_irq_mask = 0x8000000, + .reg_update_irq_mask = 0x20, +}; + +static struct cam_vfe_rdi_reg_data vfe_175_rdi_1_data = { + .reg_update_cmd_data = 0x4, + .sof_irq_mask = 0x10000000, + .reg_update_irq_mask = 0x40, +}; + +static struct cam_vfe_rdi_reg_data vfe_175_rdi_2_data = { + .reg_update_cmd_data = 0x8, + .sof_irq_mask = 0x20000000, + .reg_update_irq_mask = 0x80, +}; + +struct cam_vfe_top_dump_data vfe175_dump_data = { + .num_reg_dump_entries = 2, + .num_lut_dump_entries = 1, + .dmi_cfg = 0xc24, + .dmi_addr = 0xc28, + .dmi_data_path_hi = 0xc2C, + .dmi_data_path_lo = 0xc30, + .reg_entry = { + { + .reg_dump_start = 0x0, + .reg_dump_end = 0x1164, + }, + { + .reg_dump_start = 0x2000, + .reg_dump_end = 0x397C, + }, + }, + .lut_entry = { + { + .lut_word_size = 64, + .lut_bank_sel = 0x40, + .lut_addr_size = 180, + }, + }, +}; + +static struct cam_vfe_top_ver2_hw_info vfe175_top_hw_info = { + .common_reg = &vfe175_top_common_reg, + .camif_hw_info = { + .common_reg = &vfe175_top_common_reg, + .camif_reg = &vfe175_camif_reg, + .reg_data = &vfe_175_camif_reg_data, + }, + .camif_lite_hw_info = { + .common_reg = &vfe175_top_common_reg, + .camif_lite_reg = &vfe175_camif_lite_reg, + .reg_data = &vfe175_camif_lite_reg_data, + }, + .rdi_hw_info = { + .common_reg = &vfe175_top_common_reg, + .rdi_reg = &vfe175_rdi_reg, + .common_reg_data = &vfe175_rdi_reg_data, + .reg_data = { + &vfe_175_rdi_0_data, + &vfe_175_rdi_1_data, + &vfe_175_rdi_2_data, + NULL, + }, + }, + .num_mux = 5, + .mux_type = { + CAM_VFE_CAMIF_VER_2_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_CAMIF_LITE_VER_2_0, + }, + .dump_data = &vfe175_dump_data, +}; + +static struct cam_irq_register_set vfe175_bus_irq_reg[3] = { + { + .mask_reg_offset = 0x00002044, + .clear_reg_offset = 0x00002050, + .status_reg_offset = 0x0000205C, + }, + { + .mask_reg_offset = 0x00002048, + .clear_reg_offset = 0x00002054, + .status_reg_offset = 0x00002060, + }, + { + .mask_reg_offset = 0x0000204C, + .clear_reg_offset = 0x00002058, + .status_reg_offset = 0x00002064, + }, +}; + +static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client + vfe175_ubwc_regs_client_3 = { + .tile_cfg = 0x0000252C, + .h_init = 0x00002530, + .v_init = 0x00002534, + .meta_addr = 0x00002538, + .meta_offset = 0x0000253C, + .meta_stride = 0x00002540, + .mode_cfg_0 = 0x00002544, + .mode_cfg_1 = 0x000025A4, + .bw_limit = 0x000025A0, +}; + +static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client + vfe175_ubwc_regs_client_4 = { + .tile_cfg = 0x0000262C, + .h_init = 0x00002630, + .v_init = 0x00002634, + .meta_addr = 0x00002638, + .meta_offset = 0x0000263C, + .meta_stride = 0x00002640, + .mode_cfg_0 = 0x00002644, + .mode_cfg_1 = 0x000026A4, + .bw_limit = 0x000026A0, +}; + +static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client + vfe175_ubwc_regs_client_20 = { + .tile_cfg = 0x0000362C, + .h_init = 0x00003630, + .v_init = 0x00003634, + .meta_addr = 0x00003638, + .meta_offset = 0x0000363C, + .meta_stride = 0x00003640, + .mode_cfg_0 = 0x00003644, + .mode_cfg_1 = 0x000036A4, + .bw_limit = 0x000036A0, +}; + +static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client + vfe175_ubwc_regs_client_21 = { + .tile_cfg = 0x0000372C, + .h_init = 0x00003730, + .v_init = 0x00003734, + .meta_addr = 0x00003738, + .meta_offset = 0x0000373C, + .meta_stride = 0x00003740, + .mode_cfg_0 = 0x00003744, + .mode_cfg_1 = 0x000037A4, + .bw_limit = 0x000037A0, +}; + +static struct cam_vfe_bus_ver2_hw_info vfe175_bus_hw_info = { + .common_reg = { + .hw_version = 0x00002000, + .hw_capability = 0x00002004, + .sw_reset = 0x00002008, + .cgc_ovd = 0x0000200C, + .pwr_iso_cfg = 0x000020CC, + .dual_master_comp_cfg = 0x00002028, + .irq_reg_info = { + .num_registers = 3, + .irq_reg_set = vfe175_bus_irq_reg, + .global_clear_offset = 0x00002068, + .global_clear_bitmask = 0x00000001, + }, + .comp_error_status = 0x0000206C, + .comp_ovrwr_status = 0x00002070, + .dual_comp_error_status = 0x00002074, + .dual_comp_ovrwr_status = 0x00002078, + .addr_sync_cfg = 0x0000207C, + .addr_sync_frame_hdr = 0x00002080, + .addr_sync_no_sync = 0x00002084, + .debug_status_cfg = 0x0000226C, + .debug_status_0 = 0x00002270, + }, + .num_client = 24, + .bus_client_reg = { + /* BUS Client 0 */ + { + .status0 = 0x00002200, + .status1 = 0x00002204, + .cfg = 0x00002208, + .header_addr = 0x0000220C, + .header_cfg = 0x00002210, + .image_addr = 0x00002214, + .image_addr_offset = 0x00002218, + .buffer_width_cfg = 0x0000221C, + .buffer_height_cfg = 0x00002220, + .packer_cfg = 0x00002224, + .stride = 0x00002228, + .irq_subsample_period = 0x00002248, + .irq_subsample_pattern = 0x0000224C, + .framedrop_period = 0x00002250, + .framedrop_pattern = 0x00002254, + .frame_inc = 0x00002258, + .burst_limit = 0x0000225C, + .ubwc_regs = NULL, + }, + /* BUS Client 1 */ + { + .status0 = 0x00002300, + .status1 = 0x00002304, + .cfg = 0x00002308, + .header_addr = 0x0000230C, + .header_cfg = 0x00002310, + .image_addr = 0x00002314, + .image_addr_offset = 0x00002318, + .buffer_width_cfg = 0x0000231C, + .buffer_height_cfg = 0x00002320, + .packer_cfg = 0x00002324, + .stride = 0x00002328, + .irq_subsample_period = 0x00002348, + .irq_subsample_pattern = 0x0000234C, + .framedrop_period = 0x00002350, + .framedrop_pattern = 0x00002354, + .frame_inc = 0x00002358, + .burst_limit = 0x0000235C, + .ubwc_regs = NULL, + }, + /* BUS Client 2 */ + { + .status0 = 0x00002400, + .status1 = 0x00002404, + .cfg = 0x00002408, + .header_addr = 0x0000240C, + .header_cfg = 0x00002410, + .image_addr = 0x00002414, + .image_addr_offset = 0x00002418, + .buffer_width_cfg = 0x0000241C, + .buffer_height_cfg = 0x00002420, + .packer_cfg = 0x00002424, + .stride = 0x00002428, + .irq_subsample_period = 0x00002448, + .irq_subsample_pattern = 0x0000244C, + .framedrop_period = 0x00002450, + .framedrop_pattern = 0x00002454, + .frame_inc = 0x00002458, + .burst_limit = 0x0000245C, + .ubwc_regs = NULL, + }, + /* BUS Client 3 */ + { + .status0 = 0x00002500, + .status1 = 0x00002504, + .cfg = 0x00002508, + .header_addr = 0x0000250C, + .header_cfg = 0x00002510, + .image_addr = 0x00002514, + .image_addr_offset = 0x00002518, + .buffer_width_cfg = 0x0000251C, + .buffer_height_cfg = 0x00002520, + .packer_cfg = 0x00002524, + .stride = 0x00002528, + .irq_subsample_period = 0x00002548, + .irq_subsample_pattern = 0x0000254C, + .framedrop_period = 0x00002550, + .framedrop_pattern = 0x00002554, + .frame_inc = 0x00002558, + .burst_limit = 0x0000255C, + .ubwc_regs = &vfe175_ubwc_regs_client_3, + }, + /* BUS Client 4 */ + { + .status0 = 0x00002600, + .status1 = 0x00002604, + .cfg = 0x00002608, + .header_addr = 0x0000260C, + .header_cfg = 0x00002610, + .image_addr = 0x00002614, + .image_addr_offset = 0x00002618, + .buffer_width_cfg = 0x0000261C, + .buffer_height_cfg = 0x00002620, + .packer_cfg = 0x00002624, + .stride = 0x00002628, + .irq_subsample_period = 0x00002648, + .irq_subsample_pattern = 0x0000264C, + .framedrop_period = 0x00002650, + .framedrop_pattern = 0x00002654, + .frame_inc = 0x00002658, + .burst_limit = 0x0000265C, + .ubwc_regs = &vfe175_ubwc_regs_client_4, + }, + /* BUS Client 5 */ + { + .status0 = 0x00002700, + .status1 = 0x00002704, + .cfg = 0x00002708, + .header_addr = 0x0000270C, + .header_cfg = 0x00002710, + .image_addr = 0x00002714, + .image_addr_offset = 0x00002718, + .buffer_width_cfg = 0x0000271C, + .buffer_height_cfg = 0x00002720, + .packer_cfg = 0x00002724, + .stride = 0x00002728, + .irq_subsample_period = 0x00002748, + .irq_subsample_pattern = 0x0000274C, + .framedrop_period = 0x00002750, + .framedrop_pattern = 0x00002754, + .frame_inc = 0x00002758, + .burst_limit = 0x0000275C, + .ubwc_regs = NULL, + }, + /* BUS Client 6 */ + { + .status0 = 0x00002800, + .status1 = 0x00002804, + .cfg = 0x00002808, + .header_addr = 0x0000280C, + .header_cfg = 0x00002810, + .image_addr = 0x00002814, + .image_addr_offset = 0x00002818, + .buffer_width_cfg = 0x0000281C, + .buffer_height_cfg = 0x00002820, + .packer_cfg = 0x00002824, + .stride = 0x00002828, + .irq_subsample_period = 0x00002848, + .irq_subsample_pattern = 0x0000284C, + .framedrop_period = 0x00002850, + .framedrop_pattern = 0x00002854, + .frame_inc = 0x00002858, + .burst_limit = 0x0000285C, + .ubwc_regs = NULL, + }, + /* BUS Client 7 */ + { + .status0 = 0x00002900, + .status1 = 0x00002904, + .cfg = 0x00002908, + .header_addr = 0x0000290C, + .header_cfg = 0x00002910, + .image_addr = 0x00002914, + .image_addr_offset = 0x00002918, + .buffer_width_cfg = 0x0000291C, + .buffer_height_cfg = 0x00002920, + .packer_cfg = 0x00002924, + .stride = 0x00002928, + .irq_subsample_period = 0x00002948, + .irq_subsample_pattern = 0x0000294C, + .framedrop_period = 0x00002950, + .framedrop_pattern = 0x00002954, + .frame_inc = 0x00002958, + .burst_limit = 0x0000295C, + .ubwc_regs = NULL, + }, + /* BUS Client 8 */ + { + .status0 = 0x00002A00, + .status1 = 0x00002A04, + .cfg = 0x00002A08, + .header_addr = 0x00002A0C, + .header_cfg = 0x00002A10, + .image_addr = 0x00002A14, + .image_addr_offset = 0x00002A18, + .buffer_width_cfg = 0x00002A1C, + .buffer_height_cfg = 0x00002A20, + .packer_cfg = 0x00002A24, + .stride = 0x00002A28, + .irq_subsample_period = 0x00002A48, + .irq_subsample_pattern = 0x00002A4C, + .framedrop_period = 0x00002A50, + .framedrop_pattern = 0x00002A54, + .frame_inc = 0x00002A58, + .burst_limit = 0x00002A5C, + .ubwc_regs = NULL, + }, + /* BUS Client 9 */ + { + .status0 = 0x00002B00, + .status1 = 0x00002B04, + .cfg = 0x00002B08, + .header_addr = 0x00002B0C, + .header_cfg = 0x00002B10, + .image_addr = 0x00002B14, + .image_addr_offset = 0x00002B18, + .buffer_width_cfg = 0x00002B1C, + .buffer_height_cfg = 0x00002B20, + .packer_cfg = 0x00002B24, + .stride = 0x00002B28, + .irq_subsample_period = 0x00002B48, + .irq_subsample_pattern = 0x00002B4C, + .framedrop_period = 0x00002B50, + .framedrop_pattern = 0x00002B54, + .frame_inc = 0x00002B58, + .burst_limit = 0x00002B5C, + .ubwc_regs = NULL, + }, + /* BUS Client 10 */ + { + .status0 = 0x00002C00, + .status1 = 0x00002C04, + .cfg = 0x00002C08, + .header_addr = 0x00002C0C, + .header_cfg = 0x00002C10, + .image_addr = 0x00002C14, + .image_addr_offset = 0x00002C18, + .buffer_width_cfg = 0x00002C1C, + .buffer_height_cfg = 0x00002C20, + .packer_cfg = 0x00002C24, + .stride = 0x00002C28, + .irq_subsample_period = 0x00002C48, + .irq_subsample_pattern = 0x00002C4C, + .framedrop_period = 0x00002C50, + .framedrop_pattern = 0x00002C54, + .frame_inc = 0x00002C58, + .burst_limit = 0x00002C5C, + .ubwc_regs = NULL, + }, + /* BUS Client 11 */ + { + .status0 = 0x00002D00, + .status1 = 0x00002D04, + .cfg = 0x00002D08, + .header_addr = 0x00002D0C, + .header_cfg = 0x00002D10, + .image_addr = 0x00002D14, + .image_addr_offset = 0x00002D18, + .buffer_width_cfg = 0x00002D1C, + .buffer_height_cfg = 0x00002D20, + .packer_cfg = 0x00002D24, + .stride = 0x00002D28, + .irq_subsample_period = 0x00002D48, + .irq_subsample_pattern = 0x00002D4C, + .framedrop_period = 0x00002D50, + .framedrop_pattern = 0x00002D54, + .frame_inc = 0x00002D58, + .burst_limit = 0x00002D5C, + .ubwc_regs = NULL, + }, + /* BUS Client 12 */ + { + .status0 = 0x00002E00, + .status1 = 0x00002E04, + .cfg = 0x00002E08, + .header_addr = 0x00002E0C, + .header_cfg = 0x00002E10, + .image_addr = 0x00002E14, + .image_addr_offset = 0x00002E18, + .buffer_width_cfg = 0x00002E1C, + .buffer_height_cfg = 0x00002E20, + .packer_cfg = 0x00002E24, + .stride = 0x00002E28, + .irq_subsample_period = 0x00002E48, + .irq_subsample_pattern = 0x00002E4C, + .framedrop_period = 0x00002E50, + .framedrop_pattern = 0x00002E54, + .frame_inc = 0x00002E58, + .burst_limit = 0x00002E5C, + .ubwc_regs = NULL, + }, + /* BUS Client 13 */ + { + .status0 = 0x00002F00, + .status1 = 0x00002F04, + .cfg = 0x00002F08, + .header_addr = 0x00002F0C, + .header_cfg = 0x00002F10, + .image_addr = 0x00002F14, + .image_addr_offset = 0x00002F18, + .buffer_width_cfg = 0x00002F1C, + .buffer_height_cfg = 0x00002F20, + .packer_cfg = 0x00002F24, + .stride = 0x00002F28, + .irq_subsample_period = 0x00002F48, + .irq_subsample_pattern = 0x00002F4C, + .framedrop_period = 0x00002F50, + .framedrop_pattern = 0x00002F54, + .frame_inc = 0x00002F58, + .burst_limit = 0x00002F5C, + .ubwc_regs = NULL, + }, + /* BUS Client 14 */ + { + .status0 = 0x00003000, + .status1 = 0x00003004, + .cfg = 0x00003008, + .header_addr = 0x0000300C, + .header_cfg = 0x00003010, + .image_addr = 0x00003014, + .image_addr_offset = 0x00003018, + .buffer_width_cfg = 0x0000301C, + .buffer_height_cfg = 0x00003020, + .packer_cfg = 0x00003024, + .stride = 0x00003028, + .irq_subsample_period = 0x00003048, + .irq_subsample_pattern = 0x0000304C, + .framedrop_period = 0x00003050, + .framedrop_pattern = 0x00003054, + .frame_inc = 0x00003058, + .burst_limit = 0x0000305C, + .ubwc_regs = NULL, + }, + /* BUS Client 15 */ + { + .status0 = 0x00003100, + .status1 = 0x00003104, + .cfg = 0x00003108, + .header_addr = 0x0000310C, + .header_cfg = 0x00003110, + .image_addr = 0x00003114, + .image_addr_offset = 0x00003118, + .buffer_width_cfg = 0x0000311C, + .buffer_height_cfg = 0x00003120, + .packer_cfg = 0x00003124, + .stride = 0x00003128, + .irq_subsample_period = 0x00003148, + .irq_subsample_pattern = 0x0000314C, + .framedrop_period = 0x00003150, + .framedrop_pattern = 0x00003154, + .frame_inc = 0x00003158, + .burst_limit = 0x0000315C, + .ubwc_regs = NULL, + }, + /* BUS Client 16 */ + { + .status0 = 0x00003200, + .status1 = 0x00003204, + .cfg = 0x00003208, + .header_addr = 0x0000320C, + .header_cfg = 0x00003210, + .image_addr = 0x00003214, + .image_addr_offset = 0x00003218, + .buffer_width_cfg = 0x0000321C, + .buffer_height_cfg = 0x00003220, + .packer_cfg = 0x00003224, + .stride = 0x00003228, + .irq_subsample_period = 0x00003248, + .irq_subsample_pattern = 0x0000324C, + .framedrop_period = 0x00003250, + .framedrop_pattern = 0x00003254, + .frame_inc = 0x00003258, + .burst_limit = 0x0000325C, + .ubwc_regs = NULL, + }, + /* BUS Client 17 */ + { + .status0 = 0x00003300, + .status1 = 0x00003304, + .cfg = 0x00003308, + .header_addr = 0x0000330C, + .header_cfg = 0x00003310, + .image_addr = 0x00003314, + .image_addr_offset = 0x00003318, + .buffer_width_cfg = 0x0000331C, + .buffer_height_cfg = 0x00003320, + .packer_cfg = 0x00003324, + .stride = 0x00003328, + .irq_subsample_period = 0x00003348, + .irq_subsample_pattern = 0x0000334C, + .framedrop_period = 0x00003350, + .framedrop_pattern = 0x00003354, + .frame_inc = 0x00003358, + .burst_limit = 0x0000335C, + .ubwc_regs = NULL, + }, + /* BUS Client 18 */ + { + .status0 = 0x00003400, + .status1 = 0x00003404, + .cfg = 0x00003408, + .header_addr = 0x0000340C, + .header_cfg = 0x00003410, + .image_addr = 0x00003414, + .image_addr_offset = 0x00003418, + .buffer_width_cfg = 0x0000341C, + .buffer_height_cfg = 0x00003420, + .packer_cfg = 0x00003424, + .stride = 0x00003428, + .irq_subsample_period = 0x00003448, + .irq_subsample_pattern = 0x0000344C, + .framedrop_period = 0x00003450, + .framedrop_pattern = 0x00003454, + .frame_inc = 0x00003458, + .burst_limit = 0x0000345C, + .ubwc_regs = NULL, + }, + /* BUS Client 19 */ + { + .status0 = 0x00003500, + .status1 = 0x00003504, + .cfg = 0x00003508, + .header_addr = 0x0000350C, + .header_cfg = 0x00003510, + .image_addr = 0x00003514, + .image_addr_offset = 0x00003518, + .buffer_width_cfg = 0x0000351C, + .buffer_height_cfg = 0x00003520, + .packer_cfg = 0x00003524, + .stride = 0x00003528, + .irq_subsample_period = 0x00003548, + .irq_subsample_pattern = 0x0000354C, + .framedrop_period = 0x00003550, + .framedrop_pattern = 0x00003554, + .frame_inc = 0x00003558, + .burst_limit = 0x0000355C, + .ubwc_regs = NULL, + }, + /* BUS Client 20 */ + { + .status0 = 0x00003600, + .status1 = 0x00003604, + .cfg = 0x00003608, + .header_addr = 0x0000360C, + .header_cfg = 0x00003610, + .image_addr = 0x00003614, + .image_addr_offset = 0x00003618, + .buffer_width_cfg = 0x0000361C, + .buffer_height_cfg = 0x00003620, + .packer_cfg = 0x00003624, + .stride = 0x00003628, + .irq_subsample_period = 0x00003648, + .irq_subsample_pattern = 0x0000364C, + .framedrop_period = 0x00003650, + .framedrop_pattern = 0x00003654, + .frame_inc = 0x00003658, + .burst_limit = 0x0000365C, + .ubwc_regs = &vfe175_ubwc_regs_client_20, + }, + /* BUS Client 21 */ + { + .status0 = 0x00003700, + .status1 = 0x00003704, + .cfg = 0x00003708, + .header_addr = 0x0000370C, + .header_cfg = 0x00003710, + .image_addr = 0x00003714, + .image_addr_offset = 0x00003718, + .buffer_width_cfg = 0x0000371C, + .buffer_height_cfg = 0x00003720, + .packer_cfg = 0x00003724, + .stride = 0x00003728, + .irq_subsample_period = 0x00003748, + .irq_subsample_pattern = 0x0000374C, + .framedrop_period = 0x00003750, + .framedrop_pattern = 0x00003754, + .frame_inc = 0x00003758, + .burst_limit = 0x0000375C, + .ubwc_regs = &vfe175_ubwc_regs_client_21, + }, + /* BUS Client 22 */ + { + .status0 = 0x00003800, + .status1 = 0x00003804, + .cfg = 0x00003808, + .header_addr = 0x0000380C, + .header_cfg = 0x00003810, + .image_addr = 0x00003814, + .image_addr_offset = 0x00003818, + .buffer_width_cfg = 0x0000381C, + .buffer_height_cfg = 0x00003820, + .packer_cfg = 0x00003824, + .stride = 0x00003828, + .irq_subsample_period = 0x00003848, + .irq_subsample_pattern = 0x0000384C, + .framedrop_period = 0x00003850, + .framedrop_pattern = 0x00003854, + .frame_inc = 0x00003858, + .burst_limit = 0x0000385C, + .ubwc_regs = NULL, + }, + /* BUS Client 23 */ + { + .status0 = 0x00003900, + .status1 = 0x00003904, + .cfg = 0x00003908, + .header_addr = 0x0000390C, + .header_cfg = 0x00003910, + .image_addr = 0x00003914, + .image_addr_offset = 0x00003918, + .buffer_width_cfg = 0x0000391C, + .buffer_height_cfg = 0x00003920, + .packer_cfg = 0x00003924, + .stride = 0x00003928, + .irq_subsample_period = 0x00003948, + .irq_subsample_pattern = 0x0000394C, + .framedrop_period = 0x00003950, + .framedrop_pattern = 0x00003954, + .frame_inc = 0x00003958, + .burst_limit = 0x0000395C, + .ubwc_regs = NULL, + }, + }, + .comp_grp_reg = { + /* CAM_VFE_BUS_VER2_COMP_GRP_0 */ + { + .comp_mask = 0x00002010, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_1 */ + { + .comp_mask = 0x00002014, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_2 */ + { + .comp_mask = 0x00002018, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_3 */ + { + .comp_mask = 0x0000201C, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_4 */ + { + .comp_mask = 0x00002020, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_5 */ + { + .comp_mask = 0x00002024, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0 */ + { + .comp_mask = 0x0000202C, + .addr_sync_mask = 0x00002088, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_1 */ + { + .comp_mask = 0x00002030, + .addr_sync_mask = 0x0000208C, + + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_2 */ + { + .comp_mask = 0x00002034, + .addr_sync_mask = 0x00002090, + + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_3 */ + { + .comp_mask = 0x00002038, + .addr_sync_mask = 0x00002094, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_4 */ + { + .comp_mask = 0x0000203C, + .addr_sync_mask = 0x00002098, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_5 */ + { + .comp_mask = 0x00002040, + .addr_sync_mask = 0x0000209C, + }, + }, + .num_out = 22, + .vfe_out_hw_info = { + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI0, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI1, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI2, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_FULL, + .max_width = 4096, + .max_height = 4096, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_DS4, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_DS16, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RAW_DUMP, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_FD, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_PDAF, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_TL_BG, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_AWB_BG, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_RS, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_CS, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_IHIST, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_FULL_DISP, + .max_width = 4096, + .max_height = 4096, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_DS4_DISP, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_DS16_DISP, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_2PD, + .max_width = 1920, + .max_height = 1080, + }, + }, +}; + +struct cam_vfe_hw_info cam_vfe175_hw_info = { + .irq_reg_info = &vfe175_top_irq_reg_info, + + .bus_version = CAM_VFE_BUS_VER_2_0, + .bus_hw_info = &vfe175_bus_hw_info, + + .top_version = CAM_VFE_TOP_VER_2_0, + .top_hw_info = &vfe175_top_hw_info, + + .camif_version = CAM_VFE_CAMIF_VER_2_0, + .camif_reg = &vfe175_camif_reg, + + .camif_lite_version = CAM_VFE_CAMIF_LITE_VER_2_0, + .camif_lite_reg = &vfe175_camif_lite_reg, + +}; + +#endif /* _CAM_VFE175_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175_130.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175_130.h new file mode 100644 index 0000000000000000000000000000000000000000..1a80dc7f8f2ee75ef85aa651169be9dcec164eae --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175_130.h @@ -0,0 +1,1149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE175_130_H_ +#define _CAM_VFE175_130_H_ + +#include "cam_vfe_camif_ver2.h" +#include "cam_vfe_camif_lite_ver2.h" +#include "cam_vfe_bus_ver2.h" +#include "cam_vfe_bus_rd_ver1.h" +#include "cam_irq_controller.h" +#include "cam_vfe_top_ver2.h" +#include "cam_vfe_core.h" + +static struct cam_irq_register_set vfe175_130_top_irq_reg_set[2] = { + { + .mask_reg_offset = 0x0000005C, + .clear_reg_offset = 0x00000064, + .status_reg_offset = 0x0000006C, + }, + { + .mask_reg_offset = 0x00000060, + .clear_reg_offset = 0x00000068, + .status_reg_offset = 0x00000070, + }, +}; + +static struct cam_irq_controller_reg_info vfe175_130_top_irq_reg_info = { + .num_registers = 2, + .irq_reg_set = vfe175_130_top_irq_reg_set, + .global_clear_offset = 0x00000058, + .global_clear_bitmask = 0x00000001, +}; + +static struct cam_vfe_camif_ver2_reg vfe175_130_camif_reg = { + .camif_cmd = 0x00000478, + .camif_config = 0x0000047C, + .line_skip_pattern = 0x00000488, + .pixel_skip_pattern = 0x0000048C, + .skip_period = 0x00000490, + .irq_subsample_pattern = 0x0000049C, + .epoch_irq = 0x000004A0, + .raw_crop_width_cfg = 0x00000CE4, + .raw_crop_height_cfg = 0x00000CE8, + .reg_update_cmd = 0x000004AC, + .vfe_diag_config = 0x00000C48, + .vfe_diag_sensor_status = 0x00000C4C, +}; + +static struct cam_vfe_camif_reg_data vfe_175_130_camif_reg_data = { + .raw_crop_first_pixel_shift = 16, + .raw_crop_first_pixel_mask = 0xFFFF, + .raw_crop_last_pixel_shift = 0x0, + .raw_crop_last_pixel_mask = 0x3FFF, + .raw_crop_first_line_shift = 16, + .raw_crop_first_line_mask = 0xFFFF, + .raw_crop_last_line_shift = 0, + .raw_crop_last_line_mask = 0x3FFF, + .input_mux_sel_shift = 5, + .input_mux_sel_mask = 0x3, + .extern_reg_update_shift = 4, + .extern_reg_update_mask = 1, + .pixel_pattern_shift = 0, + .pixel_pattern_mask = 0x7, + .dsp_mode_shift = 23, + .dsp_mode_mask = 0x1, + .dsp_en_shift = 3, + .dsp_en_mask = 0x1, + .reg_update_cmd_data = 0x1, + .epoch_line_cfg = 0x00140014, + .sof_irq_mask = 0x00000001, + .epoch0_irq_mask = 0x00000004, + .reg_update_irq_mask = 0x00000010, + .eof_irq_mask = 0x00000002, + .error_irq_mask0 = 0x0003FC00, + .error_irq_mask1 = 0xEFFF7E80, + .subscribe_irq_mask0 = 0x00000017, + .subscribe_irq_mask1 = 0x00000000, + .enable_diagnostic_hw = 0x1, +}; + +static struct cam_vfe_fe_ver1_reg vfe175_130_fe_reg = { + .camif_cmd = 0x00000478, + .camif_config = 0x0000047C, + .line_skip_pattern = 0x00000488, + .pixel_skip_pattern = 0x0000048C, + .skip_period = 0x00000490, + .irq_subsample_pattern = 0x0000049C, + .epoch_irq = 0x000004A0, + .raw_crop_width_cfg = 0x00000CE4, + .raw_crop_height_cfg = 0x00000CE8, + .reg_update_cmd = 0x000004AC, + .vfe_diag_config = 0x00000C48, + .vfe_diag_sensor_status = 0x00000C4C, + .fe_cfg = 0x00000084, +}; + +static struct cam_vfe_fe_reg_data vfe_175_130_fe_reg_data = { + .raw_crop_first_pixel_shift = 16, + .raw_crop_first_pixel_mask = 0xFFFF, + .raw_crop_last_pixel_shift = 0x0, + .raw_crop_last_pixel_mask = 0x3FFF, + .raw_crop_first_line_shift = 16, + .raw_crop_first_line_mask = 0xFFFF, + .raw_crop_last_line_shift = 0, + .raw_crop_last_line_mask = 0x3FFF, + .input_mux_sel_shift = 5, + .input_mux_sel_mask = 0x3, + .extern_reg_update_shift = 4, + .extern_reg_update_mask = 1, + .pixel_pattern_shift = 0, + .pixel_pattern_mask = 0x7, + .dsp_mode_shift = 23, + .dsp_mode_mask = 0x1, + .dsp_en_shift = 3, + .dsp_en_mask = 0x1, + .reg_update_cmd_data = 0x1, + .epoch_line_cfg = 0x00140014, + .sof_irq_mask = 0x00000001, + .epoch0_irq_mask = 0x00000004, + .reg_update_irq_mask = 0x00000010, + .eof_irq_mask = 0x00000002, + .error_irq_mask0 = 0x0003FC00, + .error_irq_mask1 = 0xEFFF7E80, + .enable_diagnostic_hw = 0x1, + .fe_mux_data = 0x2, + .hbi_cnt_shift = 0x8, +}; + +static struct cam_vfe_camif_lite_ver2_reg vfe175_130_camif_lite_reg = { + .camif_lite_cmd = 0x00000FC0, + .camif_lite_config = 0x00000FC4, + .lite_skip_period = 0x00000FC8, + .lite_irq_subsample_pattern = 0x00000FCC, + .lite_epoch_irq = 0x00000FD0, + .reg_update_cmd = 0x000004AC, +}; + +static struct cam_vfe_camif_lite_ver2_reg_data + vfe175_130_camif_lite_reg_data = { + .dual_pd_reg_update_cmd_data = 0x20, + .lite_epoch_line_cfg = 0x00140014, + .lite_sof_irq_mask = 0x00040000, + .lite_epoch0_irq_mask = 0x00100000, + .dual_pd_reg_upd_irq_mask = 0x04000000, + .lite_eof_irq_mask = 0x00080000, + .lite_err_irq_mask0 = 0x00400000, + .lite_err_irq_mask1 = 0x00004100, + .extern_reg_update_shift = 4, + .dual_pd_path_sel_shift = 24, +}; + +struct cam_vfe_top_ver2_reg_offset_module_ctrl lens_175_130_reg = { + .reset = 0x0000001C, + .cgc_ovd = 0x0000002C, + .enable = 0x00000040, +}; + +struct cam_vfe_top_ver2_reg_offset_module_ctrl stats_175_130_reg = { + .reset = 0x00000020, + .cgc_ovd = 0x00000030, + .enable = 0x00000044, +}; + +struct cam_vfe_top_ver2_reg_offset_module_ctrl color_175_130_reg = { + .reset = 0x00000024, + .cgc_ovd = 0x00000034, + .enable = 0x00000048, +}; + +struct cam_vfe_top_ver2_reg_offset_module_ctrl zoom_175_130_reg = { + .reset = 0x00000028, + .cgc_ovd = 0x00000038, + .enable = 0x0000004C, +}; + +static struct cam_vfe_top_ver2_reg_offset_common vfe175_130_top_common_reg = { + .hw_version = 0x00000000, + .hw_capability = 0x00000004, + .lens_feature = 0x00000008, + .stats_feature = 0x0000000C, + .color_feature = 0x00000010, + .zoom_feature = 0x00000014, + .global_reset_cmd = 0x00000018, + .module_ctrl = { + &lens_175_130_reg, + &stats_175_130_reg, + &color_175_130_reg, + &zoom_175_130_reg, + }, + .bus_cgc_ovd = 0x0000003C, + .core_cfg = 0x00000050, + .three_D_cfg = 0x00000054, + .violation_status = 0x0000007C, + .reg_update_cmd = 0x000004AC, +}; + +static struct cam_vfe_rdi_ver2_reg vfe175_130_rdi_reg = { + .reg_update_cmd = 0x000004AC, +}; + +static struct cam_vfe_rdi_common_reg_data vfe175_130_rdi_reg_data = { + .subscribe_irq_mask0 = 0x780001E0, + .subscribe_irq_mask1 = 0x0, + .error_irq_mask0 = 0x0, + .error_irq_mask1 = 0x3C, +}; + +static struct cam_vfe_rdi_reg_data vfe_175_130_rdi_0_data = { + .reg_update_cmd_data = 0x2, + .sof_irq_mask = 0x8000000, + .reg_update_irq_mask = 0x20, +}; + +static struct cam_vfe_rdi_reg_data vfe_175_130_rdi_1_data = { + .reg_update_cmd_data = 0x4, + .sof_irq_mask = 0x10000000, + .reg_update_irq_mask = 0x40, +}; + +static struct cam_vfe_rdi_reg_data vfe_175_130_rdi_2_data = { + .reg_update_cmd_data = 0x8, + .sof_irq_mask = 0x20000000, + .reg_update_irq_mask = 0x80, +}; + +struct cam_vfe_top_dump_data vfe175_130_dump_data = { + .num_reg_dump_entries = 2, + .num_lut_dump_entries = 1, + .dmi_cfg = 0xc24, + .dmi_addr = 0xc28, + .dmi_data_path_hi = 0xc2C, + .dmi_data_path_lo = 0xc30, + .reg_entry = { + { + .reg_dump_start = 0x0, + .reg_dump_end = 0x1164, + }, + { + .reg_dump_start = 0x2000, + .reg_dump_end = 0x397C, + }, + }, + .lut_entry = { + { + .lut_word_size = 64, + .lut_bank_sel = 0x40, + .lut_addr_size = 180, + }, + }, +}; + +static struct cam_vfe_top_ver2_hw_info vfe175_130_top_hw_info = { + .common_reg = &vfe175_130_top_common_reg, + .camif_hw_info = { + .common_reg = &vfe175_130_top_common_reg, + .camif_reg = &vfe175_130_camif_reg, + .reg_data = &vfe_175_130_camif_reg_data, + }, + .camif_lite_hw_info = { + .common_reg = &vfe175_130_top_common_reg, + .camif_lite_reg = &vfe175_130_camif_lite_reg, + .reg_data = &vfe175_130_camif_lite_reg_data, + }, + .rdi_hw_info = { + .common_reg = &vfe175_130_top_common_reg, + .rdi_reg = &vfe175_130_rdi_reg, + .common_reg_data = &vfe175_130_rdi_reg_data, + .reg_data = { + &vfe_175_130_rdi_0_data, + &vfe_175_130_rdi_1_data, + &vfe_175_130_rdi_2_data, + NULL, + }, + }, + .fe_hw_info = { + .common_reg = &vfe175_130_top_common_reg, + .fe_reg = &vfe175_130_fe_reg, + .reg_data = &vfe_175_130_fe_reg_data, + }, + .num_mux = 6, + .mux_type = { + CAM_VFE_CAMIF_VER_2_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_CAMIF_LITE_VER_2_0, + CAM_VFE_IN_RD_VER_1_0, + }, + .dump_data = &vfe175_130_dump_data, +}; + +static struct cam_irq_register_set vfe175_130_bus_rd_irq_reg[1] = { + { + .mask_reg_offset = 0x00005010, + .clear_reg_offset = 0x00005014, + .status_reg_offset = 0x0000501C, + }, +}; + +static struct cam_irq_register_set vfe175_130_bus_irq_reg[3] = { + { + .mask_reg_offset = 0x00002044, + .clear_reg_offset = 0x00002050, + .status_reg_offset = 0x0000205C, + }, + { + .mask_reg_offset = 0x00002048, + .clear_reg_offset = 0x00002054, + .status_reg_offset = 0x00002060, + }, + { + .mask_reg_offset = 0x0000204C, + .clear_reg_offset = 0x00002058, + .status_reg_offset = 0x00002064, + }, +}; + +static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client + vfe175_130_ubwc_regs_client_3 = { + .tile_cfg = 0x0000252C, + .h_init = 0x00002530, + .v_init = 0x00002534, + .meta_addr = 0x00002538, + .meta_offset = 0x0000253C, + .meta_stride = 0x00002540, + .mode_cfg_0 = 0x00002544, + .mode_cfg_1 = 0x000025A4, + .bw_limit = 0x000025A0, +}; + +static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client + vfe175_130_ubwc_regs_client_4 = { + .tile_cfg = 0x0000262C, + .h_init = 0x00002630, + .v_init = 0x00002634, + .meta_addr = 0x00002638, + .meta_offset = 0x0000263C, + .meta_stride = 0x00002640, + .mode_cfg_0 = 0x00002644, + .mode_cfg_1 = 0x000026A4, + .bw_limit = 0x000026A0, +}; + +static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client + vfe175_130_ubwc_regs_client_20 = { + .tile_cfg = 0x0000362C, + .h_init = 0x00003630, + .v_init = 0x00003634, + .meta_addr = 0x00003638, + .meta_offset = 0x0000363C, + .meta_stride = 0x00003640, + .mode_cfg_0 = 0x00003644, + .mode_cfg_1 = 0x000036A4, + .bw_limit = 0x000036A0, +}; + +static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client + vfe175_130_ubwc_regs_client_21 = { + .tile_cfg = 0x0000372C, + .h_init = 0x00003730, + .v_init = 0x00003734, + .meta_addr = 0x00003738, + .meta_offset = 0x0000373C, + .meta_stride = 0x00003740, + .mode_cfg_0 = 0x00003744, + .mode_cfg_1 = 0x000037A4, + .bw_limit = 0x000037A0, +}; + +static struct cam_vfe_bus_rd_ver1_hw_info vfe175_130_bus_rd_hw_info = { + .common_reg = { + .hw_version = 0x00005000, + .hw_capability = 0x00005004, + .sw_reset = 0x00005008, + .cgc_ovd = 0x0000500C, + .pwr_iso_cfg = 0x000050CC, + .input_if_cmd = 0x00005020, + .test_bus_ctrl = 0x00005048, + .irq_reg_info = { + .num_registers = 1, + .irq_reg_set = vfe175_130_bus_rd_irq_reg, + .global_clear_offset = 0x00005018, + .global_clear_bitmask = 0x00000001, + }, + }, + .num_client = 1, + .bus_client_reg = { + /* BUS Client 0 */ + { + .cfg = 0x00005050, + .image_addr = 0x00005058, + .buf_size = 0x0000505C, + .stride = 0x00005060, + .unpacker_cfg = 0x00005064, + .latency_buf_allocation = 0x00005078, + .burst_limit = 0x00005080, + }, + }, + .num_bus_rd_resc = 1, + .vfe_bus_rd_hw_info = { + { + .vfe_bus_rd_type = CAM_VFE_BUS_RD_VER1_VFE_BUSRD_RDI0, + .max_width = -1, + .max_height = -1, + }, + }, +}; + +static struct cam_vfe_bus_ver2_hw_info vfe175_130_bus_hw_info = { + .common_reg = { + .hw_version = 0x00002000, + .hw_capability = 0x00002004, + .sw_reset = 0x00002008, + .cgc_ovd = 0x0000200C, + .pwr_iso_cfg = 0x000020CC, + .dual_master_comp_cfg = 0x00002028, + .irq_reg_info = { + .num_registers = 3, + .irq_reg_set = vfe175_130_bus_irq_reg, + .global_clear_offset = 0x00002068, + .global_clear_bitmask = 0x00000001, + }, + .comp_error_status = 0x0000206C, + .comp_ovrwr_status = 0x00002070, + .dual_comp_error_status = 0x00002074, + .dual_comp_ovrwr_status = 0x00002078, + .addr_sync_cfg = 0x0000207C, + .addr_sync_frame_hdr = 0x00002080, + .addr_sync_no_sync = 0x00002084, + .debug_status_cfg = 0x0000226C, + .debug_status_0 = 0x00002270, + }, + .num_client = 24, + .bus_client_reg = { + /* BUS Client 0 */ + { + .status0 = 0x00002200, + .status1 = 0x00002204, + .cfg = 0x00002208, + .header_addr = 0x0000220C, + .header_cfg = 0x00002210, + .image_addr = 0x00002214, + .image_addr_offset = 0x00002218, + .buffer_width_cfg = 0x0000221C, + .buffer_height_cfg = 0x00002220, + .packer_cfg = 0x00002224, + .stride = 0x00002228, + .irq_subsample_period = 0x00002248, + .irq_subsample_pattern = 0x0000224C, + .framedrop_period = 0x00002250, + .framedrop_pattern = 0x00002254, + .frame_inc = 0x00002258, + .burst_limit = 0x0000225C, + .ubwc_regs = NULL, + }, + /* BUS Client 1 */ + { + .status0 = 0x00002300, + .status1 = 0x00002304, + .cfg = 0x00002308, + .header_addr = 0x0000230C, + .header_cfg = 0x00002310, + .image_addr = 0x00002314, + .image_addr_offset = 0x00002318, + .buffer_width_cfg = 0x0000231C, + .buffer_height_cfg = 0x00002320, + .packer_cfg = 0x00002324, + .stride = 0x00002328, + .irq_subsample_period = 0x00002348, + .irq_subsample_pattern = 0x0000234C, + .framedrop_period = 0x00002350, + .framedrop_pattern = 0x00002354, + .frame_inc = 0x00002358, + .burst_limit = 0x0000235C, + .ubwc_regs = NULL, + }, + /* BUS Client 2 */ + { + .status0 = 0x00002400, + .status1 = 0x00002404, + .cfg = 0x00002408, + .header_addr = 0x0000240C, + .header_cfg = 0x00002410, + .image_addr = 0x00002414, + .image_addr_offset = 0x00002418, + .buffer_width_cfg = 0x0000241C, + .buffer_height_cfg = 0x00002420, + .packer_cfg = 0x00002424, + .stride = 0x00002428, + .irq_subsample_period = 0x00002448, + .irq_subsample_pattern = 0x0000244C, + .framedrop_period = 0x00002450, + .framedrop_pattern = 0x00002454, + .frame_inc = 0x00002458, + .burst_limit = 0x0000245C, + .ubwc_regs = NULL, + }, + /* BUS Client 3 */ + { + .status0 = 0x00002500, + .status1 = 0x00002504, + .cfg = 0x00002508, + .header_addr = 0x0000250C, + .header_cfg = 0x00002510, + .image_addr = 0x00002514, + .image_addr_offset = 0x00002518, + .buffer_width_cfg = 0x0000251C, + .buffer_height_cfg = 0x00002520, + .packer_cfg = 0x00002524, + .stride = 0x00002528, + .irq_subsample_period = 0x00002548, + .irq_subsample_pattern = 0x0000254C, + .framedrop_period = 0x00002550, + .framedrop_pattern = 0x00002554, + .frame_inc = 0x00002558, + .burst_limit = 0x0000255C, + .ubwc_regs = + &vfe175_130_ubwc_regs_client_3, + }, + /* BUS Client 4 */ + { + .status0 = 0x00002600, + .status1 = 0x00002604, + .cfg = 0x00002608, + .header_addr = 0x0000260C, + .header_cfg = 0x00002610, + .image_addr = 0x00002614, + .image_addr_offset = 0x00002618, + .buffer_width_cfg = 0x0000261C, + .buffer_height_cfg = 0x00002620, + .packer_cfg = 0x00002624, + .stride = 0x00002628, + .irq_subsample_period = 0x00002648, + .irq_subsample_pattern = 0x0000264C, + .framedrop_period = 0x00002650, + .framedrop_pattern = 0x00002654, + .frame_inc = 0x00002658, + .burst_limit = 0x0000265C, + .ubwc_regs = + &vfe175_130_ubwc_regs_client_4, + }, + /* BUS Client 5 */ + { + .status0 = 0x00002700, + .status1 = 0x00002704, + .cfg = 0x00002708, + .header_addr = 0x0000270C, + .header_cfg = 0x00002710, + .image_addr = 0x00002714, + .image_addr_offset = 0x00002718, + .buffer_width_cfg = 0x0000271C, + .buffer_height_cfg = 0x00002720, + .packer_cfg = 0x00002724, + .stride = 0x00002728, + .irq_subsample_period = 0x00002748, + .irq_subsample_pattern = 0x0000274C, + .framedrop_period = 0x00002750, + .framedrop_pattern = 0x00002754, + .frame_inc = 0x00002758, + .burst_limit = 0x0000275C, + .ubwc_regs = NULL, + }, + /* BUS Client 6 */ + { + .status0 = 0x00002800, + .status1 = 0x00002804, + .cfg = 0x00002808, + .header_addr = 0x0000280C, + .header_cfg = 0x00002810, + .image_addr = 0x00002814, + .image_addr_offset = 0x00002818, + .buffer_width_cfg = 0x0000281C, + .buffer_height_cfg = 0x00002820, + .packer_cfg = 0x00002824, + .stride = 0x00002828, + .irq_subsample_period = 0x00002848, + .irq_subsample_pattern = 0x0000284C, + .framedrop_period = 0x00002850, + .framedrop_pattern = 0x00002854, + .frame_inc = 0x00002858, + .burst_limit = 0x0000285C, + .ubwc_regs = NULL, + }, + /* BUS Client 7 */ + { + .status0 = 0x00002900, + .status1 = 0x00002904, + .cfg = 0x00002908, + .header_addr = 0x0000290C, + .header_cfg = 0x00002910, + .image_addr = 0x00002914, + .image_addr_offset = 0x00002918, + .buffer_width_cfg = 0x0000291C, + .buffer_height_cfg = 0x00002920, + .packer_cfg = 0x00002924, + .stride = 0x00002928, + .irq_subsample_period = 0x00002948, + .irq_subsample_pattern = 0x0000294C, + .framedrop_period = 0x00002950, + .framedrop_pattern = 0x00002954, + .frame_inc = 0x00002958, + .burst_limit = 0x0000295C, + .ubwc_regs = NULL, + }, + /* BUS Client 8 */ + { + .status0 = 0x00002A00, + .status1 = 0x00002A04, + .cfg = 0x00002A08, + .header_addr = 0x00002A0C, + .header_cfg = 0x00002A10, + .image_addr = 0x00002A14, + .image_addr_offset = 0x00002A18, + .buffer_width_cfg = 0x00002A1C, + .buffer_height_cfg = 0x00002A20, + .packer_cfg = 0x00002A24, + .stride = 0x00002A28, + .irq_subsample_period = 0x00002A48, + .irq_subsample_pattern = 0x00002A4C, + .framedrop_period = 0x00002A50, + .framedrop_pattern = 0x00002A54, + .frame_inc = 0x00002A58, + .burst_limit = 0x00002A5C, + .ubwc_regs = NULL, + }, + /* BUS Client 9 */ + { + .status0 = 0x00002B00, + .status1 = 0x00002B04, + .cfg = 0x00002B08, + .header_addr = 0x00002B0C, + .header_cfg = 0x00002B10, + .image_addr = 0x00002B14, + .image_addr_offset = 0x00002B18, + .buffer_width_cfg = 0x00002B1C, + .buffer_height_cfg = 0x00002B20, + .packer_cfg = 0x00002B24, + .stride = 0x00002B28, + .irq_subsample_period = 0x00002B48, + .irq_subsample_pattern = 0x00002B4C, + .framedrop_period = 0x00002B50, + .framedrop_pattern = 0x00002B54, + .frame_inc = 0x00002B58, + .burst_limit = 0x00002B5C, + .ubwc_regs = NULL, + }, + /* BUS Client 10 */ + { + .status0 = 0x00002C00, + .status1 = 0x00002C04, + .cfg = 0x00002C08, + .header_addr = 0x00002C0C, + .header_cfg = 0x00002C10, + .image_addr = 0x00002C14, + .image_addr_offset = 0x00002C18, + .buffer_width_cfg = 0x00002C1C, + .buffer_height_cfg = 0x00002C20, + .packer_cfg = 0x00002C24, + .stride = 0x00002C28, + .irq_subsample_period = 0x00002C48, + .irq_subsample_pattern = 0x00002C4C, + .framedrop_period = 0x00002C50, + .framedrop_pattern = 0x00002C54, + .frame_inc = 0x00002C58, + .burst_limit = 0x00002C5C, + .ubwc_regs = NULL, + }, + /* BUS Client 11 */ + { + .status0 = 0x00002D00, + .status1 = 0x00002D04, + .cfg = 0x00002D08, + .header_addr = 0x00002D0C, + .header_cfg = 0x00002D10, + .image_addr = 0x00002D14, + .image_addr_offset = 0x00002D18, + .buffer_width_cfg = 0x00002D1C, + .buffer_height_cfg = 0x00002D20, + .packer_cfg = 0x00002D24, + .stride = 0x00002D28, + .irq_subsample_period = 0x00002D48, + .irq_subsample_pattern = 0x00002D4C, + .framedrop_period = 0x00002D50, + .framedrop_pattern = 0x00002D54, + .frame_inc = 0x00002D58, + .burst_limit = 0x00002D5C, + .ubwc_regs = NULL, + }, + /* BUS Client 12 */ + { + .status0 = 0x00002E00, + .status1 = 0x00002E04, + .cfg = 0x00002E08, + .header_addr = 0x00002E0C, + .header_cfg = 0x00002E10, + .image_addr = 0x00002E14, + .image_addr_offset = 0x00002E18, + .buffer_width_cfg = 0x00002E1C, + .buffer_height_cfg = 0x00002E20, + .packer_cfg = 0x00002E24, + .stride = 0x00002E28, + .irq_subsample_period = 0x00002E48, + .irq_subsample_pattern = 0x00002E4C, + .framedrop_period = 0x00002E50, + .framedrop_pattern = 0x00002E54, + .frame_inc = 0x00002E58, + .burst_limit = 0x00002E5C, + .ubwc_regs = NULL, + }, + /* BUS Client 13 */ + { + .status0 = 0x00002F00, + .status1 = 0x00002F04, + .cfg = 0x00002F08, + .header_addr = 0x00002F0C, + .header_cfg = 0x00002F10, + .image_addr = 0x00002F14, + .image_addr_offset = 0x00002F18, + .buffer_width_cfg = 0x00002F1C, + .buffer_height_cfg = 0x00002F20, + .packer_cfg = 0x00002F24, + .stride = 0x00002F28, + .irq_subsample_period = 0x00002F48, + .irq_subsample_pattern = 0x00002F4C, + .framedrop_period = 0x00002F50, + .framedrop_pattern = 0x00002F54, + .frame_inc = 0x00002F58, + .burst_limit = 0x00002F5C, + .ubwc_regs = NULL, + }, + /* BUS Client 14 */ + { + .status0 = 0x00003000, + .status1 = 0x00003004, + .cfg = 0x00003008, + .header_addr = 0x0000300C, + .header_cfg = 0x00003010, + .image_addr = 0x00003014, + .image_addr_offset = 0x00003018, + .buffer_width_cfg = 0x0000301C, + .buffer_height_cfg = 0x00003020, + .packer_cfg = 0x00003024, + .stride = 0x00003028, + .irq_subsample_period = 0x00003048, + .irq_subsample_pattern = 0x0000304C, + .framedrop_period = 0x00003050, + .framedrop_pattern = 0x00003054, + .frame_inc = 0x00003058, + .burst_limit = 0x0000305C, + .ubwc_regs = NULL, + }, + /* BUS Client 15 */ + { + .status0 = 0x00003100, + .status1 = 0x00003104, + .cfg = 0x00003108, + .header_addr = 0x0000310C, + .header_cfg = 0x00003110, + .image_addr = 0x00003114, + .image_addr_offset = 0x00003118, + .buffer_width_cfg = 0x0000311C, + .buffer_height_cfg = 0x00003120, + .packer_cfg = 0x00003124, + .stride = 0x00003128, + .irq_subsample_period = 0x00003148, + .irq_subsample_pattern = 0x0000314C, + .framedrop_period = 0x00003150, + .framedrop_pattern = 0x00003154, + .frame_inc = 0x00003158, + .burst_limit = 0x0000315C, + .ubwc_regs = NULL, + }, + /* BUS Client 16 */ + { + .status0 = 0x00003200, + .status1 = 0x00003204, + .cfg = 0x00003208, + .header_addr = 0x0000320C, + .header_cfg = 0x00003210, + .image_addr = 0x00003214, + .image_addr_offset = 0x00003218, + .buffer_width_cfg = 0x0000321C, + .buffer_height_cfg = 0x00003220, + .packer_cfg = 0x00003224, + .stride = 0x00003228, + .irq_subsample_period = 0x00003248, + .irq_subsample_pattern = 0x0000324C, + .framedrop_period = 0x00003250, + .framedrop_pattern = 0x00003254, + .frame_inc = 0x00003258, + .burst_limit = 0x0000325C, + .ubwc_regs = NULL, + }, + /* BUS Client 17 */ + { + .status0 = 0x00003300, + .status1 = 0x00003304, + .cfg = 0x00003308, + .header_addr = 0x0000330C, + .header_cfg = 0x00003310, + .image_addr = 0x00003314, + .image_addr_offset = 0x00003318, + .buffer_width_cfg = 0x0000331C, + .buffer_height_cfg = 0x00003320, + .packer_cfg = 0x00003324, + .stride = 0x00003328, + .irq_subsample_period = 0x00003348, + .irq_subsample_pattern = 0x0000334C, + .framedrop_period = 0x00003350, + .framedrop_pattern = 0x00003354, + .frame_inc = 0x00003358, + .burst_limit = 0x0000335C, + .ubwc_regs = NULL, + }, + /* BUS Client 18 */ + { + .status0 = 0x00003400, + .status1 = 0x00003404, + .cfg = 0x00003408, + .header_addr = 0x0000340C, + .header_cfg = 0x00003410, + .image_addr = 0x00003414, + .image_addr_offset = 0x00003418, + .buffer_width_cfg = 0x0000341C, + .buffer_height_cfg = 0x00003420, + .packer_cfg = 0x00003424, + .stride = 0x00003428, + .irq_subsample_period = 0x00003448, + .irq_subsample_pattern = 0x0000344C, + .framedrop_period = 0x00003450, + .framedrop_pattern = 0x00003454, + .frame_inc = 0x00003458, + .burst_limit = 0x0000345C, + .ubwc_regs = NULL, + }, + /* BUS Client 19 */ + { + .status0 = 0x00003500, + .status1 = 0x00003504, + .cfg = 0x00003508, + .header_addr = 0x0000350C, + .header_cfg = 0x00003510, + .image_addr = 0x00003514, + .image_addr_offset = 0x00003518, + .buffer_width_cfg = 0x0000351C, + .buffer_height_cfg = 0x00003520, + .packer_cfg = 0x00003524, + .stride = 0x00003528, + .irq_subsample_period = 0x00003548, + .irq_subsample_pattern = 0x0000354C, + .framedrop_period = 0x00003550, + .framedrop_pattern = 0x00003554, + .frame_inc = 0x00003558, + .burst_limit = 0x0000355C, + .ubwc_regs = NULL, + }, + /* BUS Client 20 */ + { + .status0 = 0x00003600, + .status1 = 0x00003604, + .cfg = 0x00003608, + .header_addr = 0x0000360C, + .header_cfg = 0x00003610, + .image_addr = 0x00003614, + .image_addr_offset = 0x00003618, + .buffer_width_cfg = 0x0000361C, + .buffer_height_cfg = 0x00003620, + .packer_cfg = 0x00003624, + .stride = 0x00003628, + .irq_subsample_period = 0x00003648, + .irq_subsample_pattern = 0x0000364C, + .framedrop_period = 0x00003650, + .framedrop_pattern = 0x00003654, + .frame_inc = 0x00003658, + .burst_limit = 0x0000365C, + .ubwc_regs = + &vfe175_130_ubwc_regs_client_20, + }, + /* BUS Client 21 */ + { + .status0 = 0x00003700, + .status1 = 0x00003704, + .cfg = 0x00003708, + .header_addr = 0x0000370C, + .header_cfg = 0x00003710, + .image_addr = 0x00003714, + .image_addr_offset = 0x00003718, + .buffer_width_cfg = 0x0000371C, + .buffer_height_cfg = 0x00003720, + .packer_cfg = 0x00003724, + .stride = 0x00003728, + .irq_subsample_period = 0x00003748, + .irq_subsample_pattern = 0x0000374C, + .framedrop_period = 0x00003750, + .framedrop_pattern = 0x00003754, + .frame_inc = 0x00003758, + .burst_limit = 0x0000375C, + .ubwc_regs = + &vfe175_130_ubwc_regs_client_21, + }, + /* BUS Client 22 */ + { + .status0 = 0x00003800, + .status1 = 0x00003804, + .cfg = 0x00003808, + .header_addr = 0x0000380C, + .header_cfg = 0x00003810, + .image_addr = 0x00003814, + .image_addr_offset = 0x00003818, + .buffer_width_cfg = 0x0000381C, + .buffer_height_cfg = 0x00003820, + .packer_cfg = 0x00003824, + .stride = 0x00003828, + .irq_subsample_period = 0x00003848, + .irq_subsample_pattern = 0x0000384C, + .framedrop_period = 0x00003850, + .framedrop_pattern = 0x00003854, + .frame_inc = 0x00003858, + .burst_limit = 0x0000385C, + .ubwc_regs = NULL, + }, + /* BUS Client 23 */ + { + .status0 = 0x00003900, + .status1 = 0x00003904, + .cfg = 0x00003908, + .header_addr = 0x0000390C, + .header_cfg = 0x00003910, + .image_addr = 0x00003914, + .image_addr_offset = 0x00003918, + .buffer_width_cfg = 0x0000391C, + .buffer_height_cfg = 0x00003920, + .packer_cfg = 0x00003924, + .stride = 0x00003928, + .irq_subsample_period = 0x00003948, + .irq_subsample_pattern = 0x0000394C, + .framedrop_period = 0x00003950, + .framedrop_pattern = 0x00003954, + .frame_inc = 0x00003958, + .burst_limit = 0x0000395C, + .ubwc_regs = NULL, + }, + }, + .comp_grp_reg = { + /* CAM_VFE_BUS_VER2_COMP_GRP_0 */ + { + .comp_mask = 0x00002010, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_1 */ + { + .comp_mask = 0x00002014, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_2 */ + { + .comp_mask = 0x00002018, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_3 */ + { + .comp_mask = 0x0000201C, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_4 */ + { + .comp_mask = 0x00002020, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_5 */ + { + .comp_mask = 0x00002024, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0 */ + { + .comp_mask = 0x0000202C, + .addr_sync_mask = 0x00002088, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_1 */ + { + .comp_mask = 0x00002030, + .addr_sync_mask = 0x0000208C, + + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_2 */ + { + .comp_mask = 0x00002034, + .addr_sync_mask = 0x00002090, + + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_3 */ + { + .comp_mask = 0x00002038, + .addr_sync_mask = 0x00002094, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_4 */ + { + .comp_mask = 0x0000203C, + .addr_sync_mask = 0x00002098, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_5 */ + { + .comp_mask = 0x00002040, + .addr_sync_mask = 0x0000209C, + }, + }, + .num_out = 22, + .vfe_out_hw_info = { + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI0, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI1, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI2, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_FULL, + .max_width = 4096, + .max_height = 4096, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_DS4, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_DS16, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RAW_DUMP, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_FD, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_PDAF, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_TL_BG, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_AWB_BG, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_RS, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_CS, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER2_VFE_OUT_STATS_IHIST, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_FULL_DISP, + .max_width = 4096, + .max_height = 4096, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_DS4_DISP, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_DS16_DISP, + .max_width = 1920, + .max_height = 1080, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_2PD, + .max_width = 1920, + .max_height = 1080, + }, + }, +}; + +struct cam_vfe_hw_info cam_vfe175_130_hw_info = { + .irq_reg_info = &vfe175_130_top_irq_reg_info, + + .bus_version = CAM_VFE_BUS_VER_2_0, + .bus_hw_info = &vfe175_130_bus_hw_info, + + .bus_rd_version = CAM_VFE_BUS_RD_VER_1_0, + .bus_rd_hw_info = &vfe175_130_bus_rd_hw_info, + + .top_version = CAM_VFE_TOP_VER_2_0, + .top_hw_info = &vfe175_130_top_hw_info, + + .camif_version = CAM_VFE_CAMIF_VER_2_0, + .camif_reg = &vfe175_130_camif_reg, + + .camif_lite_version = CAM_VFE_CAMIF_LITE_VER_2_0, + .camif_lite_reg = &vfe175_130_camif_lite_reg, + +}; + +#endif /* _CAM_VFE175_130_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe480.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe480.h new file mode 100644 index 0000000000000000000000000000000000000000..0cd59de02f462d06686816693184283bf6775467 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe480.h @@ -0,0 +1,1378 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + + +#ifndef _CAM_VFE480_H_ +#define _CAM_VFE480_H_ +#include "cam_vfe_camif_ver3.h" +#include "cam_vfe_top_ver3.h" +#include "cam_vfe_core.h" +#include "cam_vfe_bus_ver3.h" +#include "cam_irq_controller.h" + +static struct cam_irq_register_set vfe480_top_irq_reg_set[3] = { + { + .mask_reg_offset = 0x0000003C, + .clear_reg_offset = 0x00000048, + .status_reg_offset = 0x00000054, + }, + { + .mask_reg_offset = 0x00000040, + .clear_reg_offset = 0x0000004C, + .status_reg_offset = 0x00000058, + }, + { + .mask_reg_offset = 0x00000044, + .clear_reg_offset = 0x00000050, + .status_reg_offset = 0x0000005C, + }, +}; + +static struct cam_irq_controller_reg_info vfe480_top_irq_reg_info = { + .num_registers = 3, + .irq_reg_set = vfe480_top_irq_reg_set, + .global_clear_offset = 0x00000038, + .global_clear_bitmask = 0x00000001, +}; + +static struct cam_vfe_camif_ver3_pp_clc_reg vfe480_camif_reg = { + .hw_version = 0x00002600, + .hw_status = 0x00002604, + .module_cfg = 0x00002660, + .pdaf_raw_crop_width_cfg = 0x00002668, + .pdaf_raw_crop_height_cfg = 0x0000266C, + .line_skip_pattern = 0x00002670, + .pixel_skip_pattern = 0x00002674, + .period_cfg = 0x00002678, + .irq_subsample_pattern = 0x0000267C, + .epoch_irq_cfg = 0x00002680, + .debug_1 = 0x000027F0, + .debug_0 = 0x000027F4, + .test_bus_ctrl = 0x000027F8, + .spare = 0x000027FC, + .reg_update_cmd = 0x00000034, +}; + +static struct cam_vfe_camif_ver3_reg_data vfe_480_camif_reg_data = { + .pp_extern_reg_update_shift = 4, + .dual_pd_extern_reg_update_shift = 17, + .extern_reg_update_mask = 1, + .dual_ife_pix_en_shift = 3, + .operating_mode_shift = 11, + .input_mux_sel_shift = 5, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x7, + .dsp_mode_shift = 24, + .dsp_mode_mask = 0x1, + .dsp_en_shift = 23, + .dsp_en_mask = 0x1, + .reg_update_cmd_data = 0x41, + .epoch_line_cfg = 0x00000014, + .sof_irq_mask = 0x00000001, + .epoch0_irq_mask = 0x00000004, + .epoch1_irq_mask = 0x00000008, + .eof_irq_mask = 0x00000002, + .error_irq_mask0 = 0x82000200, + .error_irq_mask2 = 0x30301F80, + .subscribe_irq_mask1 = 0x00000007, + .frame_id_irq_mask = 0x400, + .enable_diagnostic_hw = 0x1, + .pp_camif_cfg_en_shift = 0, + .pp_camif_cfg_ife_out_en_shift = 8, + .top_debug_cfg_en = 1, +}; + +static struct cam_vfe_top_ver3_reg_offset_common vfe480_top_common_reg = { + .hw_version = 0x00000000, + .titan_version = 0x00000004, + .hw_capability = 0x00000008, + .lens_feature = 0x0000000C, + .stats_feature = 0x00000010, + .color_feature = 0x00000014, + .zoom_feature = 0x00000018, + .global_reset_cmd = 0x0000001C, + .core_cfg_0 = 0x0000002C, + .core_cfg_1 = 0x00000030, + .reg_update_cmd = 0x00000034, + .violation_status = 0x00000074, + .core_cgc_ovd_0 = 0x00000020, + .core_cgc_ovd_1 = 0x00000094, + .ahb_cgc_ovd = 0x00000024, + .noc_cgc_ovd = 0x00000028, + .trigger_cdm_events = 0x00000090, + .custom_frame_idx = 0x00000110, + .dsp_status = 0x0000007C, + .diag_config = 0x00000064, + .diag_sensor_status_0 = 0x00000068, + .diag_sensor_status_1 = 0x00000098, + .bus_overflow_status = 0x0000AA68, + .top_debug_cfg = 0x000000DC, + .top_debug_0 = 0x00000080, + .top_debug_1 = 0x00000084, + .top_debug_2 = 0x00000088, + .top_debug_3 = 0x0000008C, + .top_debug_4 = 0x0000009C, + .top_debug_5 = 0x000000A0, + .top_debug_6 = 0x000000A4, + .top_debug_7 = 0x000000A8, + .top_debug_8 = 0x000000AC, + .top_debug_9 = 0x000000B0, + .top_debug_10 = 0x000000B4, + .top_debug_11 = 0x000000B8, + .top_debug_12 = 0x000000BC, + .top_debug_13 = 0x000000C0, +}; + +static struct cam_vfe_camif_lite_ver3_reg vfe480_camif_rdi[3] = { + { + .lite_hw_version = 0x9A00, + .lite_hw_status = 0x9A04, + .lite_module_config = 0x9A60, + .lite_skip_period = 0x9A68, + .lite_irq_subsample_pattern = 0x9A6C, + .lite_epoch_irq = 0x9A70, + .lite_debug_1 = 0x9BF0, + .lite_debug_0 = 0x9BF4, + .lite_test_bus_ctrl = 0x9BF8, + .camif_lite_spare = 0x9BFC, + .reg_update_cmd = 0x34, + }, + { + .lite_hw_version = 0x9C00, + .lite_hw_status = 0x9C04, + .lite_module_config = 0x9C60, + .lite_skip_period = 0x9C68, + .lite_irq_subsample_pattern = 0x9C6C, + .lite_epoch_irq = 0x9C70, + .lite_debug_1 = 0x9DF0, + .lite_debug_0 = 0x9DF4, + .lite_test_bus_ctrl = 0x9DF8, + .camif_lite_spare = 0x9DFC, + .reg_update_cmd = 0x34, + }, + { + .lite_hw_version = 0x9E00, + .lite_hw_status = 0x9E04, + .lite_module_config = 0x9E60, + .lite_skip_period = 0x9E68, + .lite_irq_subsample_pattern = 0x9E6C, + .lite_epoch_irq = 0x9E70, + .lite_debug_1 = 0x9FF0, + .lite_debug_0 = 0x9FF4, + .lite_test_bus_ctrl = 0x9FF8, + .camif_lite_spare = 0x9FFC, + .reg_update_cmd = 0x34, + }, +}; + +static struct cam_vfe_camif_lite_ver3_reg_data vfe480_camif_rdi_reg_data[3] = { + { + .extern_reg_update_shift = 0, + .reg_update_cmd_data = 0x2, + .epoch_line_cfg = 0x0, + .sof_irq_mask = 0x10, + .epoch0_irq_mask = 0x40, + .epoch1_irq_mask = 0x80, + .eof_irq_mask = 0x20, + .error_irq_mask0 = 0x20000000, + .error_irq_mask2 = 0x20000, + .subscribe_irq_mask1 = 0x30, + .enable_diagnostic_hw = 0x1, + }, + { + .extern_reg_update_shift = 0, + .reg_update_cmd_data = 0x4, + .epoch_line_cfg = 0x0, + .sof_irq_mask = 0x100, + .epoch0_irq_mask = 0x400, + .epoch1_irq_mask = 0x800, + .eof_irq_mask = 0x200, + .error_irq_mask0 = 0x10000000, + .error_irq_mask2 = 0x40000, + .subscribe_irq_mask1 = 0x300, + .enable_diagnostic_hw = 0x1, + }, + { + .extern_reg_update_shift = 0, + .reg_update_cmd_data = 0x8, + .epoch_line_cfg = 0x0, + .sof_irq_mask = 0x1000, + .epoch0_irq_mask = 0x4000, + .epoch1_irq_mask = 0x8000, + .eof_irq_mask = 0x2000, + .error_irq_mask0 = 0x8000000, + .error_irq_mask2 = 0x80000, + .subscribe_irq_mask1 = 0x3000, + .enable_diagnostic_hw = 0x1, + }, +}; + +static struct cam_vfe_camif_lite_ver3_reg vfe480_camif_lcr = { + .lite_hw_version = 0xA000, + .lite_hw_status = 0xA004, + .lite_module_config = 0xA060, + .lite_skip_period = 0xA068, + .lite_irq_subsample_pattern = 0xA06C, + .lite_epoch_irq = 0xA070, + .lite_debug_1 = 0xA1F0, + .lite_debug_0 = 0xA1F4, + .lite_test_bus_ctrl = 0xA1F8, + .camif_lite_spare = 0xA1FC, + .reg_update_cmd = 0x0034, +}; + +static struct cam_vfe_camif_lite_ver3_reg_data vfe480_camif_lcr_reg_data = { + .extern_reg_update_shift = 16, + .reg_update_cmd_data = 0x40, + .epoch_line_cfg = 0x00140014, + .sof_irq_mask = 0x100000, + .epoch0_irq_mask = 0x400000, + .epoch1_irq_mask = 0x800000, + .eof_irq_mask = 0x200000, + .error_irq_mask0 = 0x0, + .error_irq_mask2 = 0x18000, + .subscribe_irq_mask1 = 0x300000, + .enable_diagnostic_hw = 0x1, +}; + +static struct cam_vfe_camif_lite_ver3_reg vfe480_camif_pd = { + .lite_hw_version = 0xA400, + .lite_hw_status = 0xA404, + .lite_module_config = 0xA460, + .lite_skip_period = 0xA468, + .lite_irq_subsample_pattern = 0xA46C, + .lite_epoch_irq = 0xA470, + .lite_debug_1 = 0xA5F0, + .lite_debug_0 = 0xA5F4, + .lite_test_bus_ctrl = 0xA5F8, + .camif_lite_spare = 0xA5FC, + .reg_update_cmd = 0x0034, +}; + +static struct cam_vfe_camif_lite_ver3_reg_data vfe480_camif_pd_reg_data = { + .extern_reg_update_shift = 17, + .operating_mode_shift = 13, + .input_mux_sel_shift = 31, + .reg_update_cmd_data = 0x20, + .epoch_line_cfg = 0x00140014, + .sof_irq_mask = 0x10000, + .epoch0_irq_mask = 0x40000, + .epoch1_irq_mask = 0x80000, + .eof_irq_mask = 0x20000, + .error_irq_mask0 = 0x40000000, + .error_irq_mask2 = 0x6000, + .subscribe_irq_mask1 = 0x30000, + .enable_diagnostic_hw = 0x1, +}; + +struct cam_vfe_camif_lite_ver3_hw_info rdi_hw_info_arr[CAM_VFE_RDI_VER2_MAX] = { + { + .common_reg = &vfe480_top_common_reg, + .camif_lite_reg = &vfe480_camif_rdi[0], + .reg_data = &vfe480_camif_rdi_reg_data[0], + }, + { + .common_reg = &vfe480_top_common_reg, + .camif_lite_reg = &vfe480_camif_rdi[1], + .reg_data = &vfe480_camif_rdi_reg_data[1], + }, + { + .common_reg = &vfe480_top_common_reg, + .camif_lite_reg = &vfe480_camif_rdi[2], + .reg_data = &vfe480_camif_rdi_reg_data[2], + }, +}; + +static struct cam_vfe_top_ver3_hw_info vfe480_top_hw_info = { + .common_reg = &vfe480_top_common_reg, + .camif_hw_info = { + .common_reg = &vfe480_top_common_reg, + .camif_reg = &vfe480_camif_reg, + .reg_data = &vfe_480_camif_reg_data, + }, + .pdlib_hw_info = { + .common_reg = &vfe480_top_common_reg, + .camif_lite_reg = &vfe480_camif_pd, + .reg_data = &vfe480_camif_pd_reg_data, + }, + .rdi_hw_info[0] = &rdi_hw_info_arr[0], + .rdi_hw_info[1] = &rdi_hw_info_arr[1], + .rdi_hw_info[2] = &rdi_hw_info_arr[2], + .lcr_hw_info = { + .common_reg = &vfe480_top_common_reg, + .camif_lite_reg = &vfe480_camif_lcr, + .reg_data = &vfe480_camif_lcr_reg_data, + }, + .num_mux = 6, + .mux_type = { + CAM_VFE_CAMIF_VER_3_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_PDLIB_VER_1_0, + CAM_VFE_LCR_VER_1_0, + }, +}; + +static struct cam_irq_register_set vfe480_bus_irq_reg[2] = { + { + .mask_reg_offset = 0x0000AA18, + .clear_reg_offset = 0x0000AA20, + .status_reg_offset = 0x0000AA28, + }, + { + .mask_reg_offset = 0x0000AA1C, + .clear_reg_offset = 0x0000AA24, + .status_reg_offset = 0x0000AA2C, + }, +}; + +static struct cam_vfe_bus_ver3_reg_offset_ubwc_client + vfe480_ubwc_regs_client_0 = { + .meta_addr = 0x0000AC40, + .meta_cfg = 0x0000AC44, + .mode_cfg = 0x0000AC48, + .stats_ctrl = 0x0000AC4C, + .ctrl_2 = 0x0000AC50, + .lossy_thresh0 = 0x0000AC54, + .lossy_thresh1 = 0x0000AC58, + .off_lossy_var = 0x0000AC5C, + .bw_limit = 0x0000AC1C, +}; + +static struct cam_vfe_bus_ver3_reg_offset_ubwc_client + vfe480_ubwc_regs_client_1 = { + .meta_addr = 0x0000AD40, + .meta_cfg = 0x0000AD44, + .mode_cfg = 0x0000AD48, + .stats_ctrl = 0x0000AD4C, + .ctrl_2 = 0x0000AD50, + .lossy_thresh0 = 0x0000AD54, + .lossy_thresh1 = 0x0000AD58, + .off_lossy_var = 0x0000AD5C, + .bw_limit = 0x0000AD1C, +}; + +static struct cam_vfe_bus_ver3_reg_offset_ubwc_client + vfe480_ubwc_regs_client_4 = { + .meta_addr = 0x0000B040, + .meta_cfg = 0x0000B044, + .mode_cfg = 0x0000B048, + .stats_ctrl = 0x0000B04C, + .ctrl_2 = 0x0000B050, + .lossy_thresh0 = 0x0000B054, + .lossy_thresh1 = 0x0000B058, + .off_lossy_var = 0x0000B05C, + .bw_limit = 0x0000B01C, +}; + +static struct cam_vfe_bus_ver3_reg_offset_ubwc_client + vfe480_ubwc_regs_client_5 = { + .meta_addr = 0x0000B140, + .meta_cfg = 0x0000B144, + .mode_cfg = 0x0000B148, + .stats_ctrl = 0x0000B14C, + .ctrl_2 = 0x0000B150, + .lossy_thresh0 = 0x0000B154, + .lossy_thresh1 = 0x0000B158, + .off_lossy_var = 0x0000B15C, + .bw_limit = 0x0000B11C, +}; + +static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = { + .common_reg = { + .hw_version = 0x0000AA00, + .cgc_ovd = 0x0000AA08, + .comp_cfg_0 = 0x0000AA0C, + .comp_cfg_1 = 0x0000AA10, + .if_frameheader_cfg = { + 0x0000AA34, + 0x0000AA38, + 0x0000AA3C, + 0x0000AA40, + 0x0000AA44, + 0x0000AA48, + }, + .ubwc_static_ctrl = 0x0000AA58, + .pwr_iso_cfg = 0x0000AA5C, + .overflow_status_clear = 0x0000AA60, + .ccif_violation_status = 0x0000AA64, + .overflow_status = 0x0000AA68, + .image_size_violation_status = 0x0000AA70, + .debug_status_top_cfg = 0x0000AAD4, + .debug_status_top = 0x0000AAD8, + .test_bus_ctrl = 0x0000AADC, + .irq_reg_info = { + .num_registers = 2, + .irq_reg_set = vfe480_bus_irq_reg, + .global_clear_offset = 0x0000AA30, + .global_clear_bitmask = 0x00000001, + }, + }, + .num_client = CAM_VFE_BUS_VER3_MAX_CLIENTS, + .bus_client_reg = { + /* BUS Client 0 FULL Y */ + { + .cfg = 0x0000AC00, + .image_addr = 0x0000AC04, + .frame_incr = 0x0000AC08, + .image_cfg_0 = 0x0000AC0C, + .image_cfg_1 = 0x0000AC10, + .image_cfg_2 = 0x0000AC14, + .packer_cfg = 0x0000AC18, + .frame_header_addr = 0x0000AC20, + .frame_header_incr = 0x0000AC24, + .frame_header_cfg = 0x0000AC28, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000AC30, + .irq_subsample_pattern = 0x0000AC34, + .framedrop_period = 0x0000AC38, + .framedrop_pattern = 0x0000AC3C, + .system_cache_cfg = 0x0000AC60, + .burst_limit = 0x0000AC64, + .addr_status_0 = 0x0000AC68, + .addr_status_1 = 0x0000AC6C, + .addr_status_2 = 0x0000AC70, + .addr_status_3 = 0x0000AC74, + .debug_status_cfg = 0x0000AC78, + .debug_status_0 = 0x0000AC7C, + .debug_status_1 = 0x0000AC80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_0, + .ubwc_regs = &vfe480_ubwc_regs_client_0, + }, + /* BUS Client 1 FULL C */ + { + .cfg = 0x0000AD00, + .image_addr = 0x0000AD04, + .frame_incr = 0x0000AD08, + .image_cfg_0 = 0x0000AD0C, + .image_cfg_1 = 0x0000AD10, + .image_cfg_2 = 0x0000AD14, + .packer_cfg = 0x0000AD18, + .frame_header_addr = 0x0000AD20, + .frame_header_incr = 0x0000AD24, + .frame_header_cfg = 0x0000AD28, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000AD30, + .irq_subsample_pattern = 0x0000AD34, + .framedrop_period = 0x0000AD38, + .framedrop_pattern = 0x0000AD3C, + .system_cache_cfg = 0x0000AD60, + .burst_limit = 0x0000AD64, + .addr_status_0 = 0x0000AD68, + .addr_status_1 = 0x0000AD6C, + .addr_status_2 = 0x0000AD70, + .addr_status_3 = 0x0000AD74, + .debug_status_cfg = 0x0000AD78, + .debug_status_0 = 0x0000AD7C, + .debug_status_1 = 0x0000AD80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_0, + .ubwc_regs = &vfe480_ubwc_regs_client_1, + }, + /* BUS Client 2 DS4 */ + { + .cfg = 0x0000AE00, + .image_addr = 0x0000AE04, + .frame_incr = 0x0000AE08, + .image_cfg_0 = 0x0000AE0C, + .image_cfg_1 = 0x0000AE10, + .image_cfg_2 = 0x0000AE14, + .packer_cfg = 0x0000AE18, + .frame_header_addr = 0x0000AE20, + .frame_header_incr = 0x0000AE24, + .frame_header_cfg = 0x0000AE28, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000AE30, + .irq_subsample_pattern = 0x0000AE34, + .framedrop_period = 0x0000AE38, + .framedrop_pattern = 0x0000AE3C, + .system_cache_cfg = 0x0000AE60, + .burst_limit = 0x0000AE64, + .addr_status_0 = 0x0000AE68, + .addr_status_1 = 0x0000AE6C, + .addr_status_2 = 0x0000AE70, + .addr_status_3 = 0x0000AE74, + .debug_status_cfg = 0x0000AE78, + .debug_status_0 = 0x0000AE7C, + .debug_status_1 = 0x0000AE80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_0, + .ubwc_regs = NULL, + }, + /* BUS Client 3 DS16 */ + { + .cfg = 0x0000AF00, + .image_addr = 0x0000AF04, + .frame_incr = 0x0000AF08, + .image_cfg_0 = 0x0000AF0C, + .image_cfg_1 = 0x0000AF10, + .image_cfg_2 = 0x0000AF14, + .packer_cfg = 0x0000AF18, + .frame_header_addr = 0x0000AF20, + .frame_header_incr = 0x0000AF24, + .frame_header_cfg = 0x0000AF28, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000AF30, + .irq_subsample_pattern = 0x0000AF34, + .framedrop_period = 0x0000AF38, + .framedrop_pattern = 0x0000AF3C, + .system_cache_cfg = 0x0000AF60, + .burst_limit = 0x0000AF64, + .addr_status_0 = 0x0000AF68, + .addr_status_1 = 0x0000AF6C, + .addr_status_2 = 0x0000AF70, + .addr_status_3 = 0x0000AF74, + .debug_status_cfg = 0x0000AF78, + .debug_status_0 = 0x0000AF7C, + .debug_status_1 = 0x0000AF80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_0, + .ubwc_regs = NULL, + }, + /* BUS Client 4 DISP Y */ + { + .cfg = 0x0000B000, + .image_addr = 0x0000B004, + .frame_incr = 0x0000B008, + .image_cfg_0 = 0x0000B00C, + .image_cfg_1 = 0x0000B010, + .image_cfg_2 = 0x0000B014, + .packer_cfg = 0x0000B018, + .frame_header_addr = 0x0000B020, + .frame_header_incr = 0x0000B024, + .frame_header_cfg = 0x0000B028, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000B030, + .irq_subsample_pattern = 0x0000B034, + .framedrop_period = 0x0000B038, + .framedrop_pattern = 0x0000B03C, + .system_cache_cfg = 0x0000B060, + .burst_limit = 0x0000B064, + .addr_status_0 = 0x0000B068, + .addr_status_1 = 0x0000B06C, + .addr_status_2 = 0x0000B070, + .addr_status_3 = 0x0000B074, + .debug_status_cfg = 0x0000B078, + .debug_status_0 = 0x0000B07C, + .debug_status_1 = 0x0000B080, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_1, + .ubwc_regs = &vfe480_ubwc_regs_client_4, + }, + /* BUS Client 5 DISP C */ + { + .cfg = 0x0000B100, + .image_addr = 0x0000B104, + .frame_incr = 0x0000B108, + .image_cfg_0 = 0x0000B10C, + .image_cfg_1 = 0x0000B110, + .image_cfg_2 = 0x0000B114, + .packer_cfg = 0x0000B118, + .frame_header_addr = 0x0000B120, + .frame_header_incr = 0x0000B124, + .frame_header_cfg = 0x0000B128, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000B130, + .irq_subsample_pattern = 0x0000B134, + .framedrop_period = 0x0000B138, + .framedrop_pattern = 0x0000B13C, + .system_cache_cfg = 0x0000B160, + .burst_limit = 0x0000B164, + .addr_status_0 = 0x0000B168, + .addr_status_1 = 0x0000B16C, + .addr_status_2 = 0x0000B170, + .addr_status_3 = 0x0000B174, + .debug_status_cfg = 0x0000B178, + .debug_status_0 = 0x0000B17C, + .debug_status_1 = 0x0000B180, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_1, + .ubwc_regs = &vfe480_ubwc_regs_client_5, + }, + /* BUS Client 6 DISP DS4 */ + { + .cfg = 0x0000B200, + .image_addr = 0x0000B204, + .frame_incr = 0x0000B208, + .image_cfg_0 = 0x0000B20C, + .image_cfg_1 = 0x0000B210, + .image_cfg_2 = 0x0000B214, + .packer_cfg = 0x0000B218, + .frame_header_addr = 0x0000B220, + .frame_header_incr = 0x0000B224, + .frame_header_cfg = 0x0000B228, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000B230, + .irq_subsample_pattern = 0x0000B234, + .framedrop_period = 0x0000B238, + .framedrop_pattern = 0x0000B23C, + .system_cache_cfg = 0x0000B260, + .burst_limit = 0x0000B264, + .addr_status_0 = 0x0000B268, + .addr_status_1 = 0x0000B26C, + .addr_status_2 = 0x0000B270, + .addr_status_3 = 0x0000B274, + .debug_status_cfg = 0x0000B278, + .debug_status_0 = 0x0000B27C, + .debug_status_1 = 0x0000B280, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_1, + .ubwc_regs = NULL, + }, + /* BUS Client 7 DISP DS16 */ + { + .cfg = 0x0000B300, + .image_addr = 0x0000B304, + .frame_incr = 0x0000B308, + .image_cfg_0 = 0x0000B30C, + .image_cfg_1 = 0x0000B310, + .image_cfg_2 = 0x0000B314, + .packer_cfg = 0x0000B318, + .frame_header_addr = 0x0000B320, + .frame_header_incr = 0x0000B324, + .frame_header_cfg = 0x0000B328, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000B330, + .irq_subsample_pattern = 0x0000B334, + .framedrop_period = 0x0000B338, + .framedrop_pattern = 0x0000B33C, + .system_cache_cfg = 0x0000B360, + .burst_limit = 0x0000B364, + .addr_status_0 = 0x0000B368, + .addr_status_1 = 0x0000B36C, + .addr_status_2 = 0x0000B370, + .addr_status_3 = 0x0000B374, + .debug_status_cfg = 0x0000B378, + .debug_status_0 = 0x0000B37C, + .debug_status_1 = 0x0000B380, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_1, + .ubwc_regs = NULL, + }, + /* BUS Client 8 FD Y */ + { + .cfg = 0x0000B400, + .image_addr = 0x0000B404, + .frame_incr = 0x0000B408, + .image_cfg_0 = 0x0000B40C, + .image_cfg_1 = 0x0000B410, + .image_cfg_2 = 0x0000B414, + .packer_cfg = 0x0000B418, + .frame_header_addr = 0x0000B420, + .frame_header_incr = 0x0000B424, + .frame_header_cfg = 0x0000B428, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000B430, + .irq_subsample_pattern = 0x0000B434, + .framedrop_period = 0x0000B438, + .framedrop_pattern = 0x0000B43C, + .system_cache_cfg = 0x0000B460, + .burst_limit = 0x0000B464, + .addr_status_0 = 0x0000B468, + .addr_status_1 = 0x0000B46C, + .addr_status_2 = 0x0000B470, + .addr_status_3 = 0x0000B474, + .debug_status_cfg = 0x0000B478, + .debug_status_0 = 0x0000B47C, + .debug_status_1 = 0x0000B480, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_2, + .ubwc_regs = NULL, + }, + /* BUS Client 9 FD C */ + { + .cfg = 0x0000B500, + .image_addr = 0x0000B504, + .frame_incr = 0x0000B508, + .image_cfg_0 = 0x0000B50C, + .image_cfg_1 = 0x0000B510, + .image_cfg_2 = 0x0000B514, + .packer_cfg = 0x0000B518, + .frame_header_addr = 0x0000B520, + .frame_header_incr = 0x0000B524, + .frame_header_cfg = 0x0000B528, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000B530, + .irq_subsample_pattern = 0x0000B534, + .framedrop_period = 0x0000B538, + .framedrop_pattern = 0x0000B53C, + .system_cache_cfg = 0x0000B560, + .burst_limit = 0x0000B564, + .addr_status_0 = 0x0000B568, + .addr_status_1 = 0x0000B56C, + .addr_status_2 = 0x0000B570, + .addr_status_3 = 0x0000B574, + .debug_status_cfg = 0x0000B578, + .debug_status_0 = 0x0000B57C, + .debug_status_1 = 0x0000B580, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_2, + .ubwc_regs = NULL, + }, + /* BUS Client 10 PIXEL RAW */ + { + .cfg = 0x0000B600, + .image_addr = 0x0000B604, + .frame_incr = 0x0000B608, + .image_cfg_0 = 0x0000B60C, + .image_cfg_1 = 0x0000B610, + .image_cfg_2 = 0x0000B614, + .packer_cfg = 0x0000B618, + .frame_header_addr = 0x0000B620, + .frame_header_incr = 0x0000B624, + .frame_header_cfg = 0x0000B628, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000B630, + .irq_subsample_pattern = 0x0000B634, + .framedrop_period = 0x0000B638, + .framedrop_pattern = 0x0000B63C, + .system_cache_cfg = 0x0000B660, + .burst_limit = 0x0000B664, + .addr_status_0 = 0x0000B668, + .addr_status_1 = 0x0000B66C, + .addr_status_2 = 0x0000B670, + .addr_status_3 = 0x0000B674, + .debug_status_cfg = 0x0000B678, + .debug_status_0 = 0x0000B67C, + .debug_status_1 = 0x0000B680, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_3, + .ubwc_regs = NULL, + }, + /* BUS Client 11 CAMIF PD */ + { + .cfg = 0x0000B700, + .image_addr = 0x0000B704, + .frame_incr = 0x0000B708, + .image_cfg_0 = 0x0000B70C, + .image_cfg_1 = 0x0000B710, + .image_cfg_2 = 0x0000B714, + .packer_cfg = 0x0000B718, + .frame_header_addr = 0x0000B720, + .frame_header_incr = 0x0000B724, + .frame_header_cfg = 0x0000B728, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000B730, + .irq_subsample_pattern = 0x0000B734, + .framedrop_period = 0x0000B738, + .framedrop_pattern = 0x0000B73C, + .system_cache_cfg = 0x0000B760, + .burst_limit = 0x0000B764, + .addr_status_0 = 0x0000B768, + .addr_status_1 = 0x0000B76C, + .addr_status_2 = 0x0000B770, + .addr_status_3 = 0x0000B774, + .debug_status_cfg = 0x0000B778, + .debug_status_0 = 0x0000B77C, + .debug_status_1 = 0x0000B780, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_4, + .ubwc_regs = NULL, + }, + /* BUS Client 12 STATS HDR BE */ + { + .cfg = 0x0000B800, + .image_addr = 0x0000B804, + .frame_incr = 0x0000B808, + .image_cfg_0 = 0x0000B80C, + .image_cfg_1 = 0x0000B810, + .image_cfg_2 = 0x0000B814, + .packer_cfg = 0x0000B818, + .frame_header_addr = 0x0000B820, + .frame_header_incr = 0x0000B824, + .frame_header_cfg = 0x0000B828, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000B830, + .irq_subsample_pattern = 0x0000B834, + .framedrop_period = 0x0000B838, + .framedrop_pattern = 0x0000B83C, + .system_cache_cfg = 0x0000B860, + .burst_limit = 0x0000B864, + .addr_status_0 = 0x0000B868, + .addr_status_1 = 0x0000B86C, + .addr_status_2 = 0x0000B870, + .addr_status_3 = 0x0000B874, + .debug_status_cfg = 0x0000B878, + .debug_status_0 = 0x0000B87C, + .debug_status_1 = 0x0000B880, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_5, + .ubwc_regs = NULL, + }, + /* BUS Client 13 STATS HDR BHIST */ + { + .cfg = 0x0000B900, + .image_addr = 0x0000B904, + .frame_incr = 0x0000B908, + .image_cfg_0 = 0x0000B90C, + .image_cfg_1 = 0x0000B910, + .image_cfg_2 = 0x0000B914, + .packer_cfg = 0x0000B918, + .frame_header_addr = 0x0000B920, + .frame_header_incr = 0x0000B924, + .frame_header_cfg = 0x0000B928, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000B930, + .irq_subsample_pattern = 0x0000B934, + .framedrop_period = 0x0000B938, + .framedrop_pattern = 0x0000B93C, + .system_cache_cfg = 0x0000B960, + .burst_limit = 0x0000B964, + .addr_status_0 = 0x0000B968, + .addr_status_1 = 0x0000B96C, + .addr_status_2 = 0x0000B970, + .addr_status_3 = 0x0000B974, + .debug_status_cfg = 0x0000B978, + .debug_status_0 = 0x0000B97C, + .debug_status_1 = 0x0000B980, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_5, + .ubwc_regs = NULL, + }, + /* BUS Client 14 STATS TINTLESS BG */ + { + .cfg = 0x0000BA00, + .image_addr = 0x0000BA04, + .frame_incr = 0x0000BA08, + .image_cfg_0 = 0x0000BA0C, + .image_cfg_1 = 0x0000BA10, + .image_cfg_2 = 0x0000BA14, + .packer_cfg = 0x0000BA18, + .frame_header_addr = 0x0000BA20, + .frame_header_incr = 0x0000BA24, + .frame_header_cfg = 0x0000BA28, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000BA30, + .irq_subsample_pattern = 0x0000BA34, + .framedrop_period = 0x0000BA38, + .framedrop_pattern = 0x0000BA3C, + .system_cache_cfg = 0x0000BA60, + .burst_limit = 0x0000BA64, + .addr_status_0 = 0x0000BA68, + .addr_status_1 = 0x0000BA6C, + .addr_status_2 = 0x0000BA70, + .addr_status_3 = 0x0000BA74, + .debug_status_cfg = 0x0000BA78, + .debug_status_0 = 0x0000BA7C, + .debug_status_1 = 0x0000BA80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_6, + .ubwc_regs = NULL, + }, + /* BUS Client 15 STATS AWB BG */ + { + .cfg = 0x0000BB00, + .image_addr = 0x0000BB04, + .frame_incr = 0x0000BB08, + .image_cfg_0 = 0x0000BB0C, + .image_cfg_1 = 0x0000BB10, + .image_cfg_2 = 0x0000BB14, + .packer_cfg = 0x0000BB18, + .frame_header_addr = 0x0000BB20, + .frame_header_incr = 0x0000BB24, + .frame_header_cfg = 0x0000BB28, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000BB30, + .irq_subsample_pattern = 0x0000BB34, + .framedrop_period = 0x0000BB38, + .framedrop_pattern = 0x0000BB3C, + .system_cache_cfg = 0x0000BB60, + .burst_limit = 0x0000BB64, + .addr_status_0 = 0x0000BB68, + .addr_status_1 = 0x0000BB6C, + .addr_status_2 = 0x0000BB70, + .addr_status_3 = 0x0000BB74, + .debug_status_cfg = 0x0000BB78, + .debug_status_0 = 0x0000BB7C, + .debug_status_1 = 0x0000BB80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_6, + .ubwc_regs = NULL, + }, + /* BUS Client 16 STATS BHIST */ + { + .cfg = 0x0000BC00, + .image_addr = 0x0000BC04, + .frame_incr = 0x0000BC08, + .image_cfg_0 = 0x0000BC0C, + .image_cfg_1 = 0x0000BC10, + .image_cfg_2 = 0x0000BC14, + .packer_cfg = 0x0000BC18, + .frame_header_addr = 0x0000BC20, + .frame_header_incr = 0x0000BC24, + .frame_header_cfg = 0x0000BC28, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000BC30, + .irq_subsample_pattern = 0x0000BC34, + .framedrop_period = 0x0000BC38, + .framedrop_pattern = 0x0000BC3C, + .system_cache_cfg = 0x0000BC60, + .burst_limit = 0x0000BC64, + .addr_status_0 = 0x0000BC68, + .addr_status_1 = 0x0000BC6C, + .addr_status_2 = 0x0000BC70, + .addr_status_3 = 0x0000BC74, + .debug_status_cfg = 0x0000BC78, + .debug_status_0 = 0x0000BC7C, + .debug_status_1 = 0x0000BC80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_7, + .ubwc_regs = NULL, + }, + /* BUS Client 17 STATS RS */ + { + .cfg = 0x0000BD00, + .image_addr = 0x0000BD04, + .frame_incr = 0x0000BD08, + .image_cfg_0 = 0x0000BD0C, + .image_cfg_1 = 0x0000BD10, + .image_cfg_2 = 0x0000BD14, + .packer_cfg = 0x0000BD18, + .frame_header_addr = 0x0000BD20, + .frame_header_incr = 0x0000BD24, + .frame_header_cfg = 0x0000BD28, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000BD30, + .irq_subsample_pattern = 0x0000BD34, + .framedrop_period = 0x0000BD38, + .framedrop_pattern = 0x0000BD3C, + .system_cache_cfg = 0x0000BD60, + .burst_limit = 0x0000BD64, + .addr_status_0 = 0x0000BD68, + .addr_status_1 = 0x0000BD6C, + .addr_status_2 = 0x0000BD70, + .addr_status_3 = 0x0000BD74, + .debug_status_cfg = 0x0000BD78, + .debug_status_0 = 0x0000BD7C, + .debug_status_1 = 0x0000BD80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_7, + .ubwc_regs = NULL, + }, + /* BUS Client 18 STATS CS */ + { + .cfg = 0x0000BE00, + .image_addr = 0x0000BE04, + .frame_incr = 0x0000BE08, + .image_cfg_0 = 0x0000BE0C, + .image_cfg_1 = 0x0000BE10, + .image_cfg_2 = 0x0000BE14, + .packer_cfg = 0x0000BE18, + .frame_header_addr = 0x0000BE20, + .frame_header_incr = 0x0000BE24, + .frame_header_cfg = 0x0000BE28, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000BE30, + .irq_subsample_pattern = 0x0000BE34, + .framedrop_period = 0x0000BE38, + .framedrop_pattern = 0x0000BE3C, + .system_cache_cfg = 0x0000BE60, + .burst_limit = 0x0000BE64, + .addr_status_0 = 0x0000BE68, + .addr_status_1 = 0x0000BE6C, + .addr_status_2 = 0x0000BE70, + .addr_status_3 = 0x0000BE74, + .debug_status_cfg = 0x0000BE78, + .debug_status_0 = 0x0000BE7C, + .debug_status_1 = 0x0000BE80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_7, + .ubwc_regs = NULL, + }, + /* BUS Client 19 STATS IHIST */ + { + .cfg = 0x0000BF00, + .image_addr = 0x0000BF04, + .frame_incr = 0x0000BF08, + .image_cfg_0 = 0x0000BF0C, + .image_cfg_1 = 0x0000BF10, + .image_cfg_2 = 0x0000BF14, + .packer_cfg = 0x0000BF18, + .frame_header_addr = 0x0000BF20, + .frame_header_incr = 0x0000BF24, + .frame_header_cfg = 0x0000BF28, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000BF30, + .irq_subsample_pattern = 0x0000BF34, + .framedrop_period = 0x0000BF38, + .framedrop_pattern = 0x0000BF3C, + .system_cache_cfg = 0x0000BF60, + .burst_limit = 0x0000BF64, + .addr_status_0 = 0x0000BF68, + .addr_status_1 = 0x0000BF6C, + .addr_status_2 = 0x0000BF70, + .addr_status_3 = 0x0000BF74, + .debug_status_cfg = 0x0000BF78, + .debug_status_0 = 0x0000BF7C, + .debug_status_1 = 0x0000BF80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_7, + .ubwc_regs = NULL, + }, + /* BUS Client 20 STATS BF */ + { + .cfg = 0x0000C000, + .image_addr = 0x0000C004, + .frame_incr = 0x0000C008, + .image_cfg_0 = 0x0000C00C, + .image_cfg_1 = 0x0000C010, + .image_cfg_2 = 0x0000C014, + .packer_cfg = 0x0000C018, + .frame_header_addr = 0x0000C020, + .frame_header_incr = 0x0000C024, + .frame_header_cfg = 0x0000C028, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000C030, + .irq_subsample_pattern = 0x0000C034, + .framedrop_period = 0x0000C038, + .framedrop_pattern = 0x0000C03C, + .system_cache_cfg = 0x0000C060, + .burst_limit = 0x0000C064, + .addr_status_0 = 0x0000C068, + .addr_status_1 = 0x0000C06C, + .addr_status_2 = 0x0000C070, + .addr_status_3 = 0x0000C074, + .debug_status_cfg = 0x0000C078, + .debug_status_0 = 0x0000C07C, + .debug_status_1 = 0x0000C080, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_8, + .ubwc_regs = NULL, + }, + /* BUS Client 21 PDAF V2.0 */ + { + .cfg = 0x0000C100, + .image_addr = 0x0000C104, + .frame_incr = 0x0000C108, + .image_cfg_0 = 0x0000C10C, + .image_cfg_1 = 0x0000C110, + .image_cfg_2 = 0x0000C114, + .packer_cfg = 0x0000C118, + .frame_header_addr = 0x0000C120, + .frame_header_incr = 0x0000C124, + .frame_header_cfg = 0x0000C128, + .line_done_cfg = 0x0000C12C, + .irq_subsample_period = 0x0000C130, + .irq_subsample_pattern = 0x0000C134, + .framedrop_period = 0x0000C138, + .framedrop_pattern = 0x0000C13C, + .system_cache_cfg = 0x0000C160, + .burst_limit = 0x0000C164, + .addr_status_0 = 0x0000C168, + .addr_status_1 = 0x0000C16C, + .addr_status_2 = 0x0000C170, + .addr_status_3 = 0x0000C174, + .debug_status_cfg = 0x0000C178, + .debug_status_0 = 0x0000C17C, + .debug_status_1 = 0x0000C180, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_9, + .ubwc_regs = NULL, + }, + /* BUS Client 22 LCR */ + { + .cfg = 0x0000C200, + .image_addr = 0x0000C204, + .frame_incr = 0x0000C208, + .image_cfg_0 = 0x0000C20C, + .image_cfg_1 = 0x0000C210, + .image_cfg_2 = 0x0000C214, + .packer_cfg = 0x0000C218, + .frame_header_addr = 0x0000C220, + .frame_header_incr = 0x0000C224, + .frame_header_cfg = 0x0000C228, + .line_done_cfg = 0, + .irq_subsample_period = 0x0000C230, + .irq_subsample_pattern = 0x0000C234, + .framedrop_period = 0x0000C238, + .framedrop_pattern = 0x0000C23C, + .system_cache_cfg = 0x0000C260, + .burst_limit = 0x0000C264, + .addr_status_0 = 0x0000C268, + .addr_status_1 = 0x0000C26C, + .addr_status_2 = 0x0000C270, + .addr_status_3 = 0x0000C274, + .debug_status_cfg = 0x0000C278, + .debug_status_0 = 0x0000C27C, + .debug_status_1 = 0x0000C280, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_10, + .ubwc_regs = NULL, + }, + /* BUS Client 23 RDI0 */ + { + .cfg = 0x0000C300, + .image_addr = 0x0000C304, + .frame_incr = 0x0000C308, + .image_cfg_0 = 0x0000C30C, + .image_cfg_1 = 0x0000C310, + .image_cfg_2 = 0x0000C314, + .packer_cfg = 0x0000C318, + .frame_header_addr = 0x0000C320, + .frame_header_incr = 0x0000C324, + .frame_header_cfg = 0x0000C328, + .line_done_cfg = 0x0000C32C, + .irq_subsample_period = 0x0000C330, + .irq_subsample_pattern = 0x0000C334, + .framedrop_period = 0x0000C338, + .framedrop_pattern = 0x0000C33C, + .system_cache_cfg = 0x0000C360, + .burst_limit = 0x0000C364, + .addr_status_0 = 0x0000C368, + .addr_status_1 = 0x0000C36C, + .addr_status_2 = 0x0000C370, + .addr_status_3 = 0x0000C374, + .debug_status_cfg = 0x0000C378, + .debug_status_0 = 0x0000C37C, + .debug_status_1 = 0x0000C380, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_11, + .ubwc_regs = NULL, + }, + /* BUS Client 24 RDI1 */ + { + .cfg = 0x0000C400, + .image_addr = 0x0000C404, + .frame_incr = 0x0000C408, + .image_cfg_0 = 0x0000C40C, + .image_cfg_1 = 0x0000C410, + .image_cfg_2 = 0x0000C414, + .packer_cfg = 0x0000C418, + .frame_header_addr = 0x0000C420, + .frame_header_incr = 0x0000C424, + .frame_header_cfg = 0x0000C428, + .line_done_cfg = 0x0000C42C, + .irq_subsample_period = 0x0000C430, + .irq_subsample_pattern = 0x0000C434, + .framedrop_period = 0x0000C438, + .framedrop_pattern = 0x0000C43C, + .system_cache_cfg = 0x0000C460, + .burst_limit = 0x0000C464, + .addr_status_0 = 0x0000C468, + .addr_status_1 = 0x0000C46C, + .addr_status_2 = 0x0000C470, + .addr_status_3 = 0x0000C474, + .debug_status_cfg = 0x0000C478, + .debug_status_0 = 0x0000C47C, + .debug_status_1 = 0x0000C480, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_12, + .ubwc_regs = NULL, + }, + /* BUS Client 25 RDI2 */ + { + .cfg = 0x0000C500, + .image_addr = 0x0000C504, + .frame_incr = 0x0000C508, + .image_cfg_0 = 0x0000C50C, + .image_cfg_1 = 0x0000C510, + .image_cfg_2 = 0x0000C514, + .packer_cfg = 0x0000C518, + .frame_header_addr = 0x0000C520, + .frame_header_incr = 0x0000C524, + .frame_header_cfg = 0x0000C528, + .line_done_cfg = 0x0000C52C, + .irq_subsample_period = 0x0000C530, + .irq_subsample_pattern = 0x0000C534, + .framedrop_period = 0x0000C538, + .framedrop_pattern = 0x0000C53C, + .system_cache_cfg = 0x0000C560, + .burst_limit = 0x0000C564, + .addr_status_0 = 0x0000C568, + .addr_status_1 = 0x0000C56C, + .addr_status_2 = 0x0000C570, + .addr_status_3 = 0x0000C574, + .debug_status_cfg = 0x0000C578, + .debug_status_0 = 0x0000C57C, + .debug_status_1 = 0x0000C580, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_13, + .ubwc_regs = NULL, + }, + }, + .num_out = 23, + .vfe_out_hw_info = { + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RDI0, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_3, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RDI1, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_4, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RDI2, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_5, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_FULL, + .max_width = 4096, + .max_height = 4096, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_DS4, + .max_width = 1920, + .max_height = 1080, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_DS16, + .max_width = 1920, + .max_height = 1080, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RAW_DUMP, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_FD, + .max_width = 1920, + .max_height = 1080, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_PDAF, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BE, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BHIST, + .max_width = 1920, + .max_height = 1080, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = + CAM_VFE_BUS_VER3_VFE_OUT_STATS_TL_BG, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_BF, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_AWB_BG, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_BHIST, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_RS, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_CS, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_STATS_IHIST, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_FULL_DISP, + .max_width = 4096, + .max_height = 4096, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_DS4_DISP, + .max_width = 1920, + .max_height = 1080, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_DS16_DISP, + .max_width = 1920, + .max_height = 1080, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_2PD, + .max_width = 1920, + .max_height = 1080, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_LCR, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_2, + }, + }, + .comp_done_shift = 6, + .top_irq_shift = 7, +}; + +static struct cam_irq_register_set vfe480_bus_rd_irq_reg[1] = { + { + .mask_reg_offset = 0x0000A810, + .clear_reg_offset = 0x0000A814, + .status_reg_offset = 0x0000A81C, + }, +}; + +static struct cam_vfe_bus_rd_ver1_hw_info vfe480_bus_rd_hw_info = { + .common_reg = { + .hw_version = 0x0000A800, + .hw_capability = 0x0000A804, + .sw_reset = 0x0000A808, + .cgc_ovd = 0x0000A80C, + .pwr_iso_cfg = 0x0000A834, + .input_if_cmd = 0x0000A820, + .test_bus_ctrl = 0x0000A848, + .irq_reg_info = { + .num_registers = 1, + .irq_reg_set = vfe480_bus_rd_irq_reg, + .global_clear_offset = 0x0000A818, + .global_clear_bitmask = 0x00000001, + }, + }, + .num_client = 1, + .bus_client_reg = { + /* BUS Client 0 */ + { + .cfg = 0x0000A850, + .image_addr = 0x0000A858, + .buf_size = 0x0000A85C, + .stride = 0x0000A860, + .unpacker_cfg = 0x0000A864, + .latency_buf_allocation = 0x0000A878, + .burst_limit = 0x0000A880, + }, + }, + .num_bus_rd_resc = 1, + .vfe_bus_rd_hw_info = { + { + .vfe_bus_rd_type = CAM_VFE_BUS_RD_VER1_VFE_BUSRD_RDI0, + .max_width = -1, + .max_height = -1, + }, + }, +}; + +struct cam_vfe_hw_info cam_vfe480_hw_info = { + .irq_reg_info = &vfe480_top_irq_reg_info, + + .bus_version = CAM_VFE_BUS_VER_3_0, + .bus_hw_info = &vfe480_bus_hw_info, + + .bus_rd_version = CAM_VFE_BUS_RD_VER_1_0, + .bus_rd_hw_info = &vfe480_bus_rd_hw_info, + + .top_version = CAM_VFE_TOP_VER_3_0, + .top_hw_info = &vfe480_top_hw_info, +}; + +#endif /* _CAM_VFE480_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite17x.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite17x.h new file mode 100644 index 0000000000000000000000000000000000000000..aab38c791637ccc41cd7e13aa76ac74e046d5d8f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite17x.h @@ -0,0 +1,338 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_LITE17X_H_ +#define _CAM_VFE_LITE17X_H_ + +#include "cam_vfe_bus_ver2.h" +#include "cam_irq_controller.h" +#include "cam_vfe_top_ver2.h" +#include "cam_vfe_core.h" + +static struct cam_irq_register_set vfe17x_top_irq_reg_set[2] = { + { + .mask_reg_offset = 0x0000005C, + .clear_reg_offset = 0x00000064, + .status_reg_offset = 0x0000006C, + }, + { + .mask_reg_offset = 0x00000060, + .clear_reg_offset = 0x00000068, + .status_reg_offset = 0x00000070, + }, +}; + +static struct cam_irq_controller_reg_info vfe17x_top_irq_reg_info = { + .num_registers = 2, + .irq_reg_set = vfe17x_top_irq_reg_set, + .global_clear_offset = 0x00000058, + .global_clear_bitmask = 0x00000001, +}; + +static struct cam_vfe_top_ver2_reg_offset_common vfe17x_top_common_reg = { + .hw_version = 0x00000000, + .hw_capability = 0x00000004, + .lens_feature = 0x00000008, + .stats_feature = 0x0000000C, + .color_feature = 0x00000010, + .zoom_feature = 0x00000014, + .global_reset_cmd = 0x00000018, + .module_ctrl = { + NULL, + NULL, + NULL, + NULL, + }, + .bus_cgc_ovd = 0x0000003C, + .core_cfg = 0x00000000, + .three_D_cfg = 0x00000000, + .violation_status = 0x0000007C, + .reg_update_cmd = 0x000004AC, +}; + +static struct cam_vfe_rdi_ver2_reg vfe17x_rdi_reg = { + .reg_update_cmd = 0x000004AC, +}; + +static struct cam_vfe_rdi_common_reg_data vfe17x_rdi_reg_data = { + .subscribe_irq_mask0 = 0x780001E0, + .subscribe_irq_mask1 = 0x0, + .error_irq_mask0 = 0x0, + .error_irq_mask1 = 0x3C, +}; + +static struct cam_vfe_rdi_reg_data vfe17x_rdi_0_data = { + .reg_update_cmd_data = 0x2, + .sof_irq_mask = 0x8000000, + .reg_update_irq_mask = 0x20, +}; + +static struct cam_vfe_rdi_reg_data vfe17x_rdi_1_data = { + .reg_update_cmd_data = 0x4, + .sof_irq_mask = 0x10000000, + .reg_update_irq_mask = 0x40, +}; + +static struct cam_vfe_rdi_reg_data vfe17x_rdi_2_data = { + .reg_update_cmd_data = 0x8, + .sof_irq_mask = 0x20000000, + .reg_update_irq_mask = 0x80, +}; + +static struct cam_vfe_rdi_reg_data vfe17x_rdi_3_data = { + .reg_update_cmd_data = 0x10, + .sof_irq_mask = 0x40000000, + .reg_update_irq_mask = 0x100, +}; + +static struct cam_vfe_top_ver2_hw_info vfe17x_top_hw_info = { + .common_reg = &vfe17x_top_common_reg, + .camif_hw_info = { + .common_reg = NULL, + .camif_reg = NULL, + .reg_data = NULL, + }, + .rdi_hw_info = { + .common_reg = &vfe17x_top_common_reg, + .rdi_reg = &vfe17x_rdi_reg, + .common_reg_data = &vfe17x_rdi_reg_data, + .reg_data = { + &vfe17x_rdi_0_data, + &vfe17x_rdi_1_data, + &vfe17x_rdi_2_data, + &vfe17x_rdi_3_data, + }, + }, + .num_mux = 4, + .mux_type = { + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + }, +}; + +static struct cam_irq_register_set vfe17x_bus_irq_reg[3] = { + { + .mask_reg_offset = 0x00002044, + .clear_reg_offset = 0x00002050, + .status_reg_offset = 0x0000205C, + }, + { + .mask_reg_offset = 0x00002048, + .clear_reg_offset = 0x00002054, + .status_reg_offset = 0x00002060, + }, + { + .mask_reg_offset = 0x0000204C, + .clear_reg_offset = 0x00002058, + .status_reg_offset = 0x00002064, + }, +}; + +static struct cam_vfe_bus_ver2_hw_info vfe17x_bus_hw_info = { + .common_reg = { + .hw_version = 0x00002000, + .hw_capability = 0x00002004, + .sw_reset = 0x00002008, + .cgc_ovd = 0x0000200C, + .pwr_iso_cfg = 0x000020CC, + .dual_master_comp_cfg = 0x00002028, + .irq_reg_info = { + .num_registers = 3, + .irq_reg_set = vfe17x_bus_irq_reg, + .global_clear_offset = 0x00002068, + .global_clear_bitmask = 0x00000001, + }, + .comp_error_status = 0x0000206C, + .comp_ovrwr_status = 0x00002070, + .dual_comp_error_status = 0x00002074, + .dual_comp_ovrwr_status = 0x00002078, + .addr_sync_cfg = 0x0000207C, + .addr_sync_frame_hdr = 0x00002080, + .addr_sync_no_sync = 0x00002084, + }, + .num_client = 4, + .bus_client_reg = { + /* BUS Client 0 */ + { + .status0 = 0x00002200, + .status1 = 0x00002204, + .cfg = 0x00002208, + .header_addr = 0x0000220C, + .header_cfg = 0x00002210, + .image_addr = 0x00002214, + .image_addr_offset = 0x00002218, + .buffer_width_cfg = 0x0000221C, + .buffer_height_cfg = 0x00002220, + .packer_cfg = 0x00002224, + .stride = 0x00002228, + .irq_subsample_period = 0x00002248, + .irq_subsample_pattern = 0x0000224C, + .framedrop_period = 0x00002250, + .framedrop_pattern = 0x00002254, + .frame_inc = 0x00002258, + .burst_limit = 0x0000225C, + .ubwc_regs = NULL, + }, + /* BUS Client 1 */ + { + .status0 = 0x00002300, + .status1 = 0x00002304, + .cfg = 0x00002308, + .header_addr = 0x0000230C, + .header_cfg = 0x00002310, + .image_addr = 0x00002314, + .image_addr_offset = 0x00002318, + .buffer_width_cfg = 0x0000231C, + .buffer_height_cfg = 0x00002320, + .packer_cfg = 0x00002324, + .stride = 0x00002328, + .irq_subsample_period = 0x00002348, + .irq_subsample_pattern = 0x0000234C, + .framedrop_period = 0x00002350, + .framedrop_pattern = 0x00002354, + .frame_inc = 0x00002358, + .burst_limit = 0x0000235C, + .ubwc_regs = NULL, + }, + /* BUS Client 2 */ + { + .status0 = 0x00002400, + .status1 = 0x00002404, + .cfg = 0x00002408, + .header_addr = 0x0000240C, + .header_cfg = 0x00002410, + .image_addr = 0x00002414, + .image_addr_offset = 0x00002418, + .buffer_width_cfg = 0x0000241C, + .buffer_height_cfg = 0x00002420, + .packer_cfg = 0x00002424, + .stride = 0x00002428, + .irq_subsample_period = 0x00002448, + .irq_subsample_pattern = 0x0000244C, + .framedrop_period = 0x00002450, + .framedrop_pattern = 0x00002454, + .frame_inc = 0x00002458, + .burst_limit = 0x0000245C, + .ubwc_regs = NULL, + }, + /* BUS Client 3 */ + { + .status0 = 0x00002500, + .status1 = 0x00002504, + .cfg = 0x00002508, + .header_addr = 0x0000250C, + .header_cfg = 0x00002510, + .image_addr = 0x00002514, + .image_addr_offset = 0x00002518, + .buffer_width_cfg = 0x0000251C, + .buffer_height_cfg = 0x00002520, + .packer_cfg = 0x00002524, + .stride = 0x00002528, + .irq_subsample_period = 0x00002548, + .irq_subsample_pattern = 0x0000254C, + .framedrop_period = 0x00002550, + .framedrop_pattern = 0x00002554, + .frame_inc = 0x00002558, + .burst_limit = 0x0000255C, + .ubwc_regs = NULL, + }, + }, + .comp_grp_reg = { + /* CAM_VFE_BUS_VER2_COMP_GRP_0 */ + { + .comp_mask = 0x00002010, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_1 */ + { + .comp_mask = 0x00002014, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_2 */ + { + .comp_mask = 0x00002018, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_3 */ + { + .comp_mask = 0x0000201C, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_4 */ + { + .comp_mask = 0x00002020, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_5 */ + { + .comp_mask = 0x00002024, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0 */ + { + .comp_mask = 0x0000202C, + .addr_sync_mask = 0x00002088, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_1 */ + { + .comp_mask = 0x00002030, + .addr_sync_mask = 0x0000208C, + + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_2 */ + { + .comp_mask = 0x00002034, + .addr_sync_mask = 0x00002090, + + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_3 */ + { + .comp_mask = 0x00002038, + .addr_sync_mask = 0x00002094, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_4 */ + { + .comp_mask = 0x0000203C, + .addr_sync_mask = 0x00002098, + }, + /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_5 */ + { + .comp_mask = 0x00002040, + .addr_sync_mask = 0x0000209C, + }, + }, + .num_out = 4, + .vfe_out_hw_info = { + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI0, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI1, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI2, + .max_width = -1, + .max_height = -1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI3, + .max_width = -1, + .max_height = -1, + }, + }, +}; + +static struct cam_vfe_hw_info cam_vfe_lite17x_hw_info = { + .irq_reg_info = &vfe17x_top_irq_reg_info, + + .bus_version = CAM_VFE_BUS_VER_2_0, + .bus_hw_info = &vfe17x_bus_hw_info, + + .top_version = CAM_VFE_TOP_VER_2_0, + .top_hw_info = &vfe17x_top_hw_info, + +}; + +#endif /* _CAM_VFE_LITE17X_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite48x.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite48x.h new file mode 100644 index 0000000000000000000000000000000000000000..c19ade50bec969f3944b23ee82b5a4a9639a28e8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite48x.h @@ -0,0 +1,410 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_LITE48x_H_ +#define _CAM_VFE_LITE48x_H_ + +#include "cam_vfe_bus_ver3.h" +#include "cam_irq_controller.h" +#include "cam_vfe_top_ver3.h" +#include "cam_vfe_core.h" + +static struct cam_irq_register_set vfe48x_top_irq_reg_set[3] = { + { + .mask_reg_offset = 0x00000028, + .clear_reg_offset = 0x00000034, + .status_reg_offset = 0x00000040, + }, + { + .mask_reg_offset = 0x0000002C, + .clear_reg_offset = 0x00000038, + .status_reg_offset = 0x00000044, + }, + { + .mask_reg_offset = 0x00000030, + .clear_reg_offset = 0x0000003C, + .status_reg_offset = 0x00000048, + }, +}; + +static struct cam_irq_controller_reg_info vfe48x_top_irq_reg_info = { + .num_registers = 3, + .irq_reg_set = vfe48x_top_irq_reg_set, + .global_clear_offset = 0x00000024, + .global_clear_bitmask = 0x00000001, +}; + +static struct cam_vfe_top_ver3_reg_offset_common vfe48x_top_common_reg = { + .hw_version = 0x00000000, + .titan_version = 0x00000004, + .hw_capability = 0x00000008, + .global_reset_cmd = 0x0000000C, + .core_cgc_ovd_0 = 0x00000010, + .ahb_cgc_ovd = 0x00000014, + .noc_cgc_ovd = 0x00000018, + .reg_update_cmd = 0x00000020, + .diag_config = 0x00000050, + .diag_sensor_status_0 = 0x00000054, + .bus_overflow_status = 0x00001A68, + .top_debug_cfg = 0x00000074, + .top_debug_0 = 0x0000005C, + .top_debug_1 = 0x00000068, + .top_debug_2 = 0x0000006C, + .top_debug_3 = 0x00000070, +}; + +static struct cam_vfe_camif_lite_ver3_reg vfe48x_camif_rdi[4] = { + { + .lite_hw_version = 0x1200, + .lite_hw_status = 0x1204, + .lite_module_config = 0x1260, + .lite_skip_period = 0x1268, + .lite_irq_subsample_pattern = 0x126C, + .lite_epoch_irq = 0x1270, + .lite_debug_1 = 0x13F0, + .lite_debug_0 = 0x13F4, + .lite_test_bus_ctrl = 0x13F8, + .camif_lite_spare = 0x13FC, + .reg_update_cmd = 0x0020, + }, + { + .lite_hw_version = 0x1400, + .lite_hw_status = 0x1404, + .lite_module_config = 0x1460, + .lite_skip_period = 0x1468, + .lite_irq_subsample_pattern = 0x146C, + .lite_epoch_irq = 0x1470, + .lite_debug_1 = 0x15F0, + .lite_debug_0 = 0x15F4, + .lite_test_bus_ctrl = 0x15F8, + .camif_lite_spare = 0x15FC, + .reg_update_cmd = 0x0020, + }, + { + .lite_hw_version = 0x1600, + .lite_hw_status = 0x1604, + .lite_module_config = 0x1660, + .lite_skip_period = 0x1668, + .lite_irq_subsample_pattern = 0x166C, + .lite_epoch_irq = 0x1670, + .lite_debug_1 = 0x17F0, + .lite_debug_0 = 0x17F4, + .lite_test_bus_ctrl = 0x17F8, + .camif_lite_spare = 0x17FC, + .reg_update_cmd = 0x0020, + }, + { + .lite_hw_version = 0x1800, + .lite_hw_status = 0x1804, + .lite_module_config = 0x1860, + .lite_skip_period = 0x1868, + .lite_irq_subsample_pattern = 0x186C, + .lite_epoch_irq = 0x1870, + .lite_debug_1 = 0x19F0, + .lite_debug_0 = 0x19F4, + .lite_test_bus_ctrl = 0x19F8, + .camif_lite_spare = 0x19FC, + .reg_update_cmd = 0x0020, + }, +}; + +static struct cam_vfe_camif_lite_ver3_reg_data vfe48x_camif_rdi_reg_data[4] = { + { + .extern_reg_update_shift = 0, + .reg_update_cmd_data = 0x1, + .epoch_line_cfg = 0x0, + .sof_irq_mask = 0x1, + .epoch0_irq_mask = 0x4, + .epoch1_irq_mask = 0x8, + .eof_irq_mask = 0x02, + .error_irq_mask0 = 0x1, + .error_irq_mask2 = 0x100, + .subscribe_irq_mask1 = 0x3, + .enable_diagnostic_hw = 0x1, + .top_debug_cfg_en = 0x1, + }, + { + .extern_reg_update_shift = 0, + .reg_update_cmd_data = 0x2, + .epoch_line_cfg = 0x0, + .sof_irq_mask = 0x10, + .epoch0_irq_mask = 0x40, + .epoch1_irq_mask = 0x80, + .eof_irq_mask = 0x20, + .error_irq_mask0 = 0x2, + .error_irq_mask2 = 0x200, + .subscribe_irq_mask1 = 0x30, + .enable_diagnostic_hw = 0x1, + .top_debug_cfg_en = 0x1, + }, + { + .extern_reg_update_shift = 0, + .reg_update_cmd_data = 0x4, + .epoch_line_cfg = 0x0, + .sof_irq_mask = 0x100, + .epoch0_irq_mask = 0x400, + .epoch1_irq_mask = 0x800, + .eof_irq_mask = 0x200, + .error_irq_mask0 = 0x4, + .error_irq_mask2 = 0x400, + .subscribe_irq_mask1 = 0x300, + .enable_diagnostic_hw = 0x1, + .top_debug_cfg_en = 0x1, + }, + { + .extern_reg_update_shift = 0, + .reg_update_cmd_data = 0x8, + .epoch_line_cfg = 0x0, + .sof_irq_mask = 0x1000, + .epoch0_irq_mask = 0x4000, + .epoch1_irq_mask = 0x8000, + .eof_irq_mask = 0x2000, + .error_irq_mask0 = 0x8, + .error_irq_mask2 = 0x800, + .subscribe_irq_mask1 = 0x3000, + .enable_diagnostic_hw = 0x1, + .top_debug_cfg_en = 0x1, + }, +}; + +static struct cam_vfe_camif_lite_ver3_hw_info + vfe48x_rdi_hw_info[CAM_VFE_RDI_VER2_MAX] = { + { + .common_reg = &vfe48x_top_common_reg, + .camif_lite_reg = &vfe48x_camif_rdi[0], + .reg_data = &vfe48x_camif_rdi_reg_data[0], + }, + { + .common_reg = &vfe48x_top_common_reg, + .camif_lite_reg = &vfe48x_camif_rdi[1], + .reg_data = &vfe48x_camif_rdi_reg_data[1], + }, + { + .common_reg = &vfe48x_top_common_reg, + .camif_lite_reg = &vfe48x_camif_rdi[2], + .reg_data = &vfe48x_camif_rdi_reg_data[2], + }, + { + .common_reg = &vfe48x_top_common_reg, + .camif_lite_reg = &vfe48x_camif_rdi[3], + .reg_data = &vfe48x_camif_rdi_reg_data[3], + }, +}; + +static struct cam_vfe_top_ver3_hw_info vfe48x_top_hw_info = { + .common_reg = &vfe48x_top_common_reg, + .rdi_hw_info[0] = &vfe48x_rdi_hw_info[0], + .rdi_hw_info[1] = &vfe48x_rdi_hw_info[1], + .rdi_hw_info[2] = &vfe48x_rdi_hw_info[2], + .rdi_hw_info[3] = &vfe48x_rdi_hw_info[3], + .num_mux = 4, + .mux_type = { + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + CAM_VFE_RDI_VER_1_0, + }, +}; + +static struct cam_irq_register_set vfe48x_bus_irq_reg[2] = { + { + .mask_reg_offset = 0x00001A18, + .clear_reg_offset = 0x00001A20, + .status_reg_offset = 0x00001A28, + }, + { + .mask_reg_offset = 0x00001A1C, + .clear_reg_offset = 0x00001A24, + .status_reg_offset = 0x00001A2C, + }, +}; + +static struct cam_vfe_bus_ver3_hw_info vfe48x_bus_hw_info = { + .common_reg = { + .hw_version = 0x00001A00, + .cgc_ovd = 0x00001A08, + .if_frameheader_cfg = { + 0x00001A34, + 0x00001A38, + 0x00001A3C, + 0x00001A40, + }, + .pwr_iso_cfg = 0x00001A5C, + .overflow_status_clear = 0x00001A60, + .ccif_violation_status = 0x00001A64, + .overflow_status = 0x00001A68, + .image_size_violation_status = 0x00001A70, + .debug_status_top_cfg = 0x00001AD4, + .debug_status_top = 0x00001AD8, + .test_bus_ctrl = 0x00001ADC, + .irq_reg_info = { + .num_registers = 2, + .irq_reg_set = vfe48x_bus_irq_reg, + .global_clear_offset = 0x00001A30, + .global_clear_bitmask = 0x00000001, + }, + }, + .num_client = 4, + .bus_client_reg = { + /* RDI 0 */ + { + .cfg = 0x00001C00, + .image_addr = 0x00001C04, + .frame_incr = 0x00001C08, + .image_cfg_0 = 0x00001C0C, + .image_cfg_1 = 0x00001C10, + .image_cfg_2 = 0x00001C14, + .packer_cfg = 0x00001C18, + .frame_header_addr = 0x00001C20, + .frame_header_incr = 0x00001C24, + .frame_header_cfg = 0x00001C28, + .line_done_cfg = 0x00001C2C, + .irq_subsample_period = 0x00001C30, + .irq_subsample_pattern = 0x00001C34, + .framedrop_period = 0x00001C38, + .framedrop_pattern = 0x00001C3C, + .system_cache_cfg = 0x00001C60, + .burst_limit = 0x00001C64, + .addr_status_0 = 0x00001C68, + .addr_status_1 = 0x00001C6C, + .addr_status_2 = 0x00001C70, + .addr_status_3 = 0x00001C74, + .debug_status_cfg = 0x00001C78, + .debug_status_0 = 0x00001C7C, + .debug_status_1 = 0x00001C80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_0, + .ubwc_regs = NULL, + }, + /* RDI 1 */ + { + .cfg = 0x00001D00, + .image_addr = 0x00001D04, + .frame_incr = 0x00001D08, + .image_cfg_0 = 0x00001D0C, + .image_cfg_1 = 0x00001D10, + .image_cfg_2 = 0x00001D14, + .packer_cfg = 0x00001D18, + .frame_header_addr = 0x00001D20, + .frame_header_incr = 0x00001D24, + .frame_header_cfg = 0x00001D28, + .line_done_cfg = 0x00001D2C, + .irq_subsample_period = 0x00001D30, + .irq_subsample_pattern = 0x00001D34, + .framedrop_period = 0x00001D38, + .framedrop_pattern = 0x00001D3C, + .system_cache_cfg = 0x00001D60, + .burst_limit = 0x00001D64, + .addr_status_0 = 0x00001D68, + .addr_status_1 = 0x00001D6C, + .addr_status_2 = 0x00001D70, + .addr_status_3 = 0x00001D74, + .debug_status_cfg = 0x00001D78, + .debug_status_0 = 0x00001D7C, + .debug_status_1 = 0x00001D80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_1, + .ubwc_regs = NULL, + }, + /* RDI 2 */ + { + .cfg = 0x00001E00, + .image_addr = 0x00001E04, + .frame_incr = 0x00001E08, + .image_cfg_0 = 0x00001E0C, + .image_cfg_1 = 0x00001E10, + .image_cfg_2 = 0x00001E14, + .packer_cfg = 0x00001E18, + .frame_header_addr = 0x00001E20, + .frame_header_incr = 0x00001E24, + .frame_header_cfg = 0x00001E28, + .line_done_cfg = 0x00001E2C, + .irq_subsample_period = 0x00001E30, + .irq_subsample_pattern = 0x00001E34, + .framedrop_period = 0x00001E38, + .framedrop_pattern = 0x00001E3C, + .system_cache_cfg = 0x00001E60, + .burst_limit = 0x00001E64, + .addr_status_0 = 0x00001E68, + .addr_status_1 = 0x00001E6C, + .addr_status_2 = 0x00001E70, + .addr_status_3 = 0x00001E74, + .debug_status_cfg = 0x00001E78, + .debug_status_0 = 0x00001E7C, + .debug_status_1 = 0x00001E80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_2, + .ubwc_regs = NULL, + }, + /* RDI 3 */ + { + .cfg = 0x00001F00, + .image_addr = 0x00001F04, + .frame_incr = 0x00001F08, + .image_cfg_0 = 0x00001F0C, + .image_cfg_1 = 0x00001F10, + .image_cfg_2 = 0x00001F14, + .packer_cfg = 0x00001F18, + .frame_header_addr = 0x00001F20, + .frame_header_incr = 0x00001F24, + .frame_header_cfg = 0x00001F28, + .line_done_cfg = 0x00001F2C, + .irq_subsample_period = 0x00001F30, + .irq_subsample_pattern = 0x00001F34, + .framedrop_period = 0x00001F38, + .framedrop_pattern = 0x00001F3C, + .system_cache_cfg = 0x00001F60, + .burst_limit = 0x00001F64, + .addr_status_0 = 0x00001F68, + .addr_status_1 = 0x00001F6C, + .addr_status_2 = 0x00001F70, + .addr_status_3 = 0x00001F74, + .debug_status_cfg = 0x00001F78, + .debug_status_0 = 0x00001F7C, + .debug_status_1 = 0x00001F80, + .comp_group = CAM_VFE_BUS_VER3_COMP_GRP_3, + .ubwc_regs = NULL, + }, + }, + .num_out = 4, + .vfe_out_hw_info = { + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RDI0, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_0, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RDI1, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_1, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RDI2, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_2, + }, + { + .vfe_out_type = CAM_VFE_BUS_VER3_VFE_OUT_RDI3, + .max_width = -1, + .max_height = -1, + .source_group = CAM_VFE_BUS_VER3_SRC_GRP_3, + }, + }, + .comp_done_shift = 4, + .top_irq_shift = 4, +}; + +static struct cam_vfe_hw_info cam_vfe_lite48x_hw_info = { + .irq_reg_info = &vfe48x_top_irq_reg_info, + + .bus_version = CAM_VFE_BUS_VER_3_0, + .bus_hw_info = &vfe48x_bus_hw_info, + + .top_version = CAM_VFE_TOP_VER_3_0, + .top_hw_info = &vfe48x_top_hw_info, + +}; + +#endif /* _CAM_VFE_LITE48x_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..d9240a48597e4f01c7f21c5c7a323e46841573f9 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe_bus.o cam_vfe_bus_ver2.o cam_vfe_bus_rd_ver1.o cam_vfe_bus_ver3.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus.c new file mode 100644 index 0000000000000000000000000000000000000000..2b902d753ad26ba966a8f2938201bbc949b720e2 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_vfe_bus.h" +#include "cam_vfe_bus_ver1.h" +#include "cam_vfe_bus_ver2.h" +#include "cam_vfe_bus_rd_ver1.h" +#include "cam_vfe_bus_ver3.h" +#include "cam_debug_util.h" + +int cam_vfe_bus_init(uint32_t bus_version, + int bus_type, + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *bus_hw_info, + void *vfe_irq_controller, + struct cam_vfe_bus **vfe_bus) +{ + int rc = -ENODEV; + + switch (bus_type) { + case BUS_TYPE_WR: + switch (bus_version) { + case CAM_VFE_BUS_VER_2_0: + rc = cam_vfe_bus_ver2_init(soc_info, hw_intf, + bus_hw_info, vfe_irq_controller, vfe_bus); + break; + case CAM_VFE_BUS_VER_3_0: + rc = cam_vfe_bus_ver3_init(soc_info, hw_intf, + bus_hw_info, vfe_irq_controller, vfe_bus); + break; + default: + CAM_ERR(CAM_ISP, "Unsupported Bus WR Version 0x%x", + bus_version); + break; + } + break; + case BUS_TYPE_RD: + switch (bus_version) { + case CAM_VFE_BUS_RD_VER_1_0: + /* Call vfe bus rd init function */ + rc = cam_vfe_bus_rd_ver1_init(soc_info, hw_intf, + bus_hw_info, vfe_irq_controller, vfe_bus); + break; + default: + CAM_ERR(CAM_ISP, "Unsupported Bus RD Version 0x%x", + bus_version); + break; + } + break; + default: + CAM_ERR(CAM_ISP, "Unsupported Bus type %d", bus_type); + break; + } + + return rc; +} + +int cam_vfe_bus_deinit(uint32_t bus_version, + struct cam_vfe_bus **vfe_bus) +{ + int rc = -ENODEV; + + switch (bus_version) { + case CAM_VFE_BUS_VER_2_0: + rc = cam_vfe_bus_ver2_deinit(vfe_bus); + break; + case CAM_VFE_BUS_VER_3_0: + rc = cam_vfe_bus_ver3_deinit(vfe_bus); + break; + default: + CAM_ERR(CAM_ISP, "Unsupported Bus Version %x", bus_version); + break; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_rd_ver1.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_rd_ver1.c new file mode 100644 index 0000000000000000000000000000000000000000..314ebff70fc0ba0d029e8daf749db90445111f45 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_rd_ver1.c @@ -0,0 +1,1221 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include "cam_io_util.h" +#include "cam_debug_util.h" +#include "cam_cdm_util.h" +#include "cam_hw_intf.h" +#include "cam_ife_hw_mgr.h" +#include "cam_vfe_hw_intf.h" +#include "cam_irq_controller.h" +#include "cam_tasklet_util.h" +#include "cam_vfe_bus.h" +#include "cam_vfe_bus_rd_ver1.h" +#include "cam_vfe_core.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" + +static const char drv_name[] = "vfe_bus_rd"; + +#define ALIGNUP(value, alignment) \ + ((value + alignment - 1) / alignment * alignment) + +#define MAX_BUF_UPDATE_REG_NUM \ + (sizeof(struct cam_vfe_bus_rd_ver1_reg_offset_bus_client)/4) + +#define MAX_REG_VAL_PAIR_SIZE \ + (MAX_BUF_UPDATE_REG_NUM * 2 * CAM_PACKET_MAX_PLANES) + +#define CAM_VFE_ADD_REG_VAL_PAIR(buf_array, index, offset, val) \ + do { \ + buf_array[(index)++] = offset; \ + buf_array[(index)++] = val; \ + } while (0) + +enum cam_vfe_bus_rd_ver1_unpacker_format { + BUS_RD_VER1_PACKER_FMT_PLAIN_128 = 0x0, + BUS_RD_VER1_PACKER_FMT_PLAIN_8 = 0x1, + BUS_RD_VER1_PACKER_FMT_PLAIN_16_10BPP = 0x2, + BUS_RD_VER1_PACKER_FMT_PLAIN_16_12BPP = 0x3, + BUS_RD_VER1_PACKER_FMT_PLAIN_16_14BPP = 0x4, + BUS_RD_VER1_PACKER_FMT_PLAIN_16_16BPP = 0x5, + BUS_RD_VER1_PACKER_FMT_ARGB_10 = 0x6, + BUS_RD_VER1_PACKER_FMT_ARGB_12 = 0x7, + BUS_RD_VER1_PACKER_FMT_ARGB_14 = 0x8, + BUS_RD_VER1_PACKER_FMT_PLAIN_32_20BPP = 0x9, + BUS_RD_VER1_PACKER_FMT_PLAIN_64 = 0xA, + BUS_RD_VER1_PACKER_FMT_TP_10 = 0xB, + BUS_RD_VER1_PACKER_FMT_PLAIN_32_32BPP = 0xC, + BUS_RD_VER1_PACKER_FMT_PLAIN_8_ODD_EVEN = 0xD, + BUS_RD_VER1_PACKER_FMT_PLAIN_8_LSB_MSB_10 = 0xE, + BUS_RD_VER1_PACKER_FMT_PLAIN_8_LSB_MSB_10_ODD_EVEN = 0xF, + BUS_RD_VER1_PACKER_FMT_MAX = 0xF, +}; + +struct cam_vfe_bus_rd_ver1_common_data { + uint32_t core_index; + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + void *bus_irq_controller; + void *vfe_irq_controller; + struct cam_vfe_bus_rd_ver1_reg_offset_common *common_reg; + uint32_t io_buf_update[ + MAX_REG_VAL_PAIR_SIZE]; + + struct list_head free_payload_list; + spinlock_t spin_lock; + struct mutex bus_mutex; + uint32_t secure_mode; + uint32_t num_sec_out; + uint32_t fs_sync_enable; + uint32_t go_cmd_sel; +}; + +struct cam_vfe_bus_rd_ver1_rm_resource_data { + uint32_t index; + struct cam_vfe_bus_rd_ver1_common_data *common_data; + struct cam_vfe_bus_rd_ver1_reg_offset_bus_client *hw_regs; + void *ctx; + + bool init_cfg_done; + bool hfr_cfg_done; + + uint32_t offset; + + uint32_t min_vbi; + uint32_t fs_mode; + uint32_t hbi_count; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t format; + uint32_t latency_buf_allocation; + uint32_t unpacker_cfg; + uint32_t burst_len; + + uint32_t go_cmd_sel; + uint32_t fs_sync_enable; + uint32_t fs_line_sync_en; + + uint32_t en_cfg; + uint32_t is_dual; + uint32_t img_addr; + uint32_t input_if_cmd; +}; + +struct cam_vfe_bus_rd_ver1_vfe_bus_rd_data { + uint32_t bus_rd_type; + struct cam_vfe_bus_rd_ver1_common_data *common_data; + + uint32_t num_rm; + struct cam_isp_resource_node *rm_res[PLANE_MAX]; + + struct cam_isp_resource_node *comp_grp; + enum cam_isp_hw_sync_mode dual_comp_sync_mode; + uint32_t dual_hw_alternate_vfe_id; + struct list_head vfe_bus_rd_list; + + uint32_t format; + uint32_t max_width; + uint32_t max_height; + struct cam_cdm_utils_ops *cdm_util_ops; + uint32_t secure_mode; +}; + +struct cam_vfe_bus_rd_ver1_priv { + struct cam_vfe_bus_rd_ver1_common_data common_data; + uint32_t num_client; + uint32_t num_bus_rd_resc; + + struct cam_isp_resource_node bus_client[ + CAM_VFE_BUS_RD_VER1_MAX_CLIENTS]; + struct cam_isp_resource_node vfe_bus_rd[ + CAM_VFE_BUS_RD_VER1_VFE_BUSRD_MAX]; + + int irq_handle; + int error_irq_handle; +}; + +static int cam_vfe_bus_process_cmd( + struct cam_isp_resource_node *priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size); + +static enum cam_vfe_bus_rd_ver1_unpacker_format + cam_vfe_bus_get_unpacker_fmt(uint32_t unpack_fmt) +{ + switch (unpack_fmt) { + case CAM_FORMAT_MIPI_RAW_10: + return BUS_RD_VER1_PACKER_FMT_PLAIN_8_ODD_EVEN; + default: + return BUS_RD_VER1_PACKER_FMT_MAX; + } +} + +static bool cam_vfe_bus_can_be_secure(uint32_t out_type) +{ + switch (out_type) { + case CAM_VFE_BUS_RD_VER1_VFE_BUSRD_RDI0: + return false; + + default: + return false; + } +} + +static enum cam_vfe_bus_rd_ver1_vfe_bus_rd_type + cam_vfe_bus_get_bus_rd_res_id(uint32_t res_type) +{ + switch (res_type) { + case CAM_ISP_RESOURCE_VFE_BUS_RD: + return CAM_VFE_BUS_RD_VER1_VFE_BUSRD_RDI0; + default: + return CAM_VFE_BUS_RD_VER1_VFE_BUSRD_MAX; + } +} + +static int cam_vfe_bus_get_num_rm( + enum cam_vfe_bus_rd_ver1_vfe_bus_rd_type res_type) +{ + switch (res_type) { + case CAM_VFE_BUS_RD_VER1_VFE_BUSRD_RDI0: + return 1; + default: + break; + } + + CAM_ERR(CAM_ISP, "Unsupported resource_type %u", + res_type); + return -EINVAL; +} + +static int cam_vfe_bus_get_rm_idx( + enum cam_vfe_bus_rd_ver1_vfe_bus_rd_type vfe_bus_rd_res_id, + enum cam_vfe_bus_plane_type plane) +{ + int rm_idx = -1; + + switch (vfe_bus_rd_res_id) { + case CAM_VFE_BUS_RD_VER1_VFE_BUSRD_RDI0: + switch (plane) { + case PLANE_Y: + rm_idx = 0; + break; + default: + break; + } + break; + default: + break; + } + + return rm_idx; +} + +static int cam_vfe_bus_acquire_rm( + struct cam_vfe_bus_rd_ver1_priv *ver1_bus_rd_priv, + struct cam_isp_out_port_generic_info *out_port_info, + void *tasklet, + void *ctx, + enum cam_vfe_bus_rd_ver1_vfe_bus_rd_type vfe_bus_rd_res_id, + enum cam_vfe_bus_plane_type plane, + uint32_t subscribe_irq, + struct cam_isp_resource_node **rm_res, + uint32_t *client_done_mask, + uint32_t is_dual) +{ + uint32_t rm_idx = 0; + struct cam_isp_resource_node *rm_res_local = NULL; + struct cam_vfe_bus_rd_ver1_rm_resource_data *rsrc_data = NULL; + + *rm_res = NULL; + *client_done_mask = 0; + + /* No need to allocate for BUS VER2. VFE OUT to RM is fixed. */ + rm_idx = cam_vfe_bus_get_rm_idx(vfe_bus_rd_res_id, plane); + if (rm_idx < 0 || rm_idx >= ver1_bus_rd_priv->num_client) { + CAM_ERR(CAM_ISP, "Unsupported VFE out %d plane %d", + vfe_bus_rd_res_id, plane); + return -EINVAL; + } + + rm_res_local = &ver1_bus_rd_priv->bus_client[rm_idx]; + if (rm_res_local->res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, "RM res not available state:%d", + rm_res_local->res_state); + return -EALREADY; + } + rm_res_local->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + rm_res_local->tasklet_info = tasklet; + + rsrc_data = rm_res_local->res_priv; + rsrc_data->ctx = ctx; + rsrc_data->is_dual = is_dual; + /* Set RM offset value to default */ + rsrc_data->offset = 0; + + *client_done_mask = (1 << rm_idx); + *rm_res = rm_res_local; + + CAM_DBG(CAM_ISP, "RM %d: Acquired"); + return 0; +} + +static int cam_vfe_bus_release_rm(void *bus_priv, + struct cam_isp_resource_node *rm_res) +{ + struct cam_vfe_bus_rd_ver1_rm_resource_data *rsrc_data = + rm_res->res_priv; + + rsrc_data->offset = 0; + rsrc_data->width = 0; + rsrc_data->height = 0; + rsrc_data->stride = 0; + rsrc_data->format = 0; + rsrc_data->unpacker_cfg = 0; + rsrc_data->burst_len = 0; + rsrc_data->init_cfg_done = false; + rsrc_data->hfr_cfg_done = false; + rsrc_data->en_cfg = 0; + rsrc_data->is_dual = 0; + + rm_res->tasklet_info = NULL; + rm_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + return 0; +} + +static int cam_vfe_bus_start_rm(struct cam_isp_resource_node *rm_res) +{ + int rc = 0; + struct cam_vfe_bus_rd_ver1_rm_resource_data *rm_data = + rm_res->res_priv; + struct cam_vfe_bus_rd_ver1_common_data *common_data = + rm_data->common_data; + uint32_t buf_size; + uint32_t val; + uint32_t offset; + + CAM_DBG(CAM_ISP, "w: 0x%x", rm_data->width); + CAM_DBG(CAM_ISP, "h: 0x%x", rm_data->height); + CAM_DBG(CAM_ISP, "format: 0x%x", rm_data->format); + CAM_DBG(CAM_ISP, "unpacker_cfg: 0x%x", rm_data->unpacker_cfg); + CAM_DBG(CAM_ISP, "latency_buf_allocation: 0x%x", + rm_data->latency_buf_allocation); + CAM_DBG(CAM_ISP, "stride: 0x%x", rm_data->stride); + CAM_DBG(CAM_ISP, "go_cmd_sel: 0x%x", rm_data->go_cmd_sel); + CAM_DBG(CAM_ISP, "fs_sync_enable: 0x%x", rm_data->fs_sync_enable); + CAM_DBG(CAM_ISP, "hbi_count: 0x%x", rm_data->hbi_count); + CAM_DBG(CAM_ISP, "fs_line_sync_en: 0x%x", rm_data->fs_line_sync_en); + CAM_DBG(CAM_ISP, "fs_mode: 0x%x", rm_data->fs_mode); + CAM_DBG(CAM_ISP, "min_vbi: 0x%x", rm_data->min_vbi); + + /* Write All the values*/ + offset = rm_data->hw_regs->buf_size; + buf_size = ((rm_data->width)&(0x0000FFFF)) | + ((rm_data->height<<16)&(0xFFFF0000)); + cam_io_w_mb(buf_size, common_data->mem_base + offset); + CAM_DBG(CAM_ISP, "buf_size: 0x%x", buf_size); + + val = rm_data->width; + offset = rm_data->hw_regs->stride; + CAM_DBG(CAM_ISP, "offset:0x%x, value:0x%x", offset, val); + cam_io_w_mb(val, common_data->mem_base + offset); + + CAM_DBG(CAM_ISP, "rm_data->unpacker_cfg:0x%x", rm_data->unpacker_cfg); + val = cam_vfe_bus_get_unpacker_fmt(rm_data->unpacker_cfg); + CAM_DBG(CAM_ISP, " value:0x%x", val); + offset = rm_data->hw_regs->unpacker_cfg; + CAM_DBG(CAM_ISP, "offset:0x%x, value:0x%x", offset, val); + cam_io_w_mb(val, common_data->mem_base + offset); + + val = rm_data->latency_buf_allocation; + offset = rm_data->hw_regs->latency_buf_allocation; + CAM_DBG(CAM_ISP, "offset:0x%x, value:0x%x", offset, val); + cam_io_w_mb(val, common_data->mem_base + offset); + + cam_io_w_mb(0x1, common_data->mem_base + + rm_data->hw_regs->cfg); + return rc; +} + +static int cam_vfe_bus_stop_rm(struct cam_isp_resource_node *rm_res) +{ + int rc = 0; + struct cam_vfe_bus_rd_ver1_rm_resource_data *rsrc_data = + rm_res->res_priv; + struct cam_vfe_bus_rd_ver1_common_data *common_data = + rsrc_data->common_data; + + /* Disable RM */ + cam_io_w_mb(0x0, + common_data->mem_base + rsrc_data->hw_regs->cfg); + + rm_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + rsrc_data->init_cfg_done = false; + rsrc_data->hfr_cfg_done = false; + + return rc; +} + +static int cam_vfe_bus_init_rm_resource(uint32_t index, + struct cam_vfe_bus_rd_ver1_priv *ver1_bus_rd_priv, + struct cam_vfe_bus_rd_ver1_hw_info *bus_rd_hw_info, + struct cam_isp_resource_node *rm_res) +{ + struct cam_vfe_bus_rd_ver1_rm_resource_data *rsrc_data; + + rsrc_data = kzalloc(sizeof(struct cam_vfe_bus_rd_ver1_rm_resource_data), + GFP_KERNEL); + if (!rsrc_data) { + CAM_DBG(CAM_ISP, "Failed to alloc for RM res priv"); + return -ENOMEM; + } + rm_res->res_priv = rsrc_data; + + rsrc_data->index = index; + rsrc_data->hw_regs = &bus_rd_hw_info->bus_client_reg[index]; + rsrc_data->common_data = &ver1_bus_rd_priv->common_data; + + rm_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&rm_res->list); + + rm_res->start = cam_vfe_bus_start_rm; + rm_res->stop = cam_vfe_bus_stop_rm; + rm_res->hw_intf = ver1_bus_rd_priv->common_data.hw_intf; + + + return 0; +} + +static int cam_vfe_bus_deinit_rm_resource( + struct cam_isp_resource_node *rm_res) +{ + struct cam_vfe_bus_rd_ver1_rm_resource_data *rsrc_data; + + rm_res->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + INIT_LIST_HEAD(&rm_res->list); + + rm_res->start = NULL; + rm_res->stop = NULL; + rm_res->top_half_handler = NULL; + rm_res->bottom_half_handler = NULL; + rm_res->hw_intf = NULL; + + rsrc_data = rm_res->res_priv; + rm_res->res_priv = NULL; + if (!rsrc_data) + return -ENOMEM; + kfree(rsrc_data); + + return 0; +} + +static int cam_vfe_bus_rd_get_secure_mode(void *priv, void *cmd_args, + uint32_t arg_size) +{ + return 0; +} + +static int cam_vfe_bus_acquire_vfe_bus_rd(void *bus_priv, void *acquire_args, + uint32_t args_size) +{ + int rc = -ENODEV; + int i; + enum cam_vfe_bus_rd_ver1_vfe_bus_rd_type bus_rd_res_id; + int num_rm; + uint32_t subscribe_irq; + uint32_t client_done_mask; + struct cam_vfe_bus_rd_ver1_priv *ver1_bus_rd_priv = + bus_priv; + struct cam_vfe_acquire_args *acq_args = acquire_args; + struct cam_vfe_hw_vfe_out_acquire_args *bus_rd_acquire_args; + struct cam_isp_resource_node *rsrc_node = NULL; + struct cam_vfe_bus_rd_ver1_vfe_bus_rd_data *rsrc_data = NULL; + uint32_t secure_caps = 0, mode; + + if (!bus_priv || !acquire_args) { + CAM_ERR(CAM_ISP, "Invalid Param"); + return -EINVAL; + } + + bus_rd_acquire_args = &acq_args->vfe_bus_rd; + + CAM_DBG(CAM_ISP, "Acquiring resource type 0x%x", + acq_args->rsrc_type); + + bus_rd_res_id = cam_vfe_bus_get_bus_rd_res_id( + acq_args->rsrc_type); + if (bus_rd_res_id == CAM_VFE_BUS_RD_VER1_VFE_BUSRD_MAX) + return -ENODEV; + + num_rm = cam_vfe_bus_get_num_rm(bus_rd_res_id); + if (num_rm < 1) + return -EINVAL; + + rsrc_node = &ver1_bus_rd_priv->vfe_bus_rd[bus_rd_res_id]; + if (rsrc_node->res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, "Resource not available: Res_id %d state:%d", + bus_rd_res_id, rsrc_node->res_state); + return -EBUSY; + } + + rsrc_data = rsrc_node->res_priv; + secure_caps = cam_vfe_bus_can_be_secure( + rsrc_data->bus_rd_type); + + mode = bus_rd_acquire_args->out_port_info->secure_mode; + mutex_lock(&rsrc_data->common_data->bus_mutex); + if (secure_caps) { + if (!rsrc_data->common_data->num_sec_out) { + rsrc_data->secure_mode = mode; + rsrc_data->common_data->secure_mode = mode; + } else { + if (mode == rsrc_data->common_data->secure_mode) { + rsrc_data->secure_mode = + rsrc_data->common_data->secure_mode; + } else { + rc = -EINVAL; + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Mismatch: Acquire mode[%d], drvr mode[%d]", + rsrc_data->common_data->secure_mode, + mode); + mutex_unlock( + &rsrc_data->common_data->bus_mutex); + return -EINVAL; + } + } + rsrc_data->common_data->num_sec_out++; + } + mutex_unlock(&rsrc_data->common_data->bus_mutex); + + rsrc_data->num_rm = num_rm; + rsrc_node->tasklet_info = acq_args->tasklet; + rsrc_node->cdm_ops = bus_rd_acquire_args->cdm_ops; + rsrc_data->cdm_util_ops = bus_rd_acquire_args->cdm_ops; + + subscribe_irq = 1; + + for (i = 0; i < num_rm; i++) { + rc = cam_vfe_bus_acquire_rm(ver1_bus_rd_priv, + bus_rd_acquire_args->out_port_info, + acq_args->tasklet, + acq_args->priv, + bus_rd_res_id, + i, + subscribe_irq, + &rsrc_data->rm_res[i], + &client_done_mask, + bus_rd_acquire_args->is_dual); + if (rc) { + CAM_ERR(CAM_ISP, + "VFE%d RM acquire failed for Out %d rc=%d", + rsrc_data->common_data->core_index, + bus_rd_res_id, rc); + goto release_rm; + } + } + + rsrc_node->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + bus_rd_acquire_args->rsrc_node = rsrc_node; + + CAM_DBG(CAM_ISP, "Acquire successful"); + return rc; + +release_rm: + for (i--; i >= 0; i--) + cam_vfe_bus_release_rm(ver1_bus_rd_priv, rsrc_data->rm_res[i]); + return rc; +} + +static int cam_vfe_bus_release_vfe_bus_rd(void *bus_priv, void *release_args, + uint32_t args_size) +{ + uint32_t i; + struct cam_isp_resource_node *vfe_bus_rd = NULL; + struct cam_vfe_bus_rd_ver1_vfe_bus_rd_data *rsrc_data = NULL; + uint32_t secure_caps = 0; + + if (!bus_priv || !release_args) { + CAM_ERR(CAM_ISP, "Invalid input bus_priv %pK release_args %pK", + bus_priv, release_args); + return -EINVAL; + } + + vfe_bus_rd = release_args; + rsrc_data = vfe_bus_rd->res_priv; + + if (vfe_bus_rd->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Invalid resource state:%d", + vfe_bus_rd->res_state); + } + + for (i = 0; i < rsrc_data->num_rm; i++) + cam_vfe_bus_release_rm(bus_priv, rsrc_data->rm_res[i]); + rsrc_data->num_rm = 0; + + vfe_bus_rd->tasklet_info = NULL; + vfe_bus_rd->cdm_ops = NULL; + rsrc_data->cdm_util_ops = NULL; + + secure_caps = cam_vfe_bus_can_be_secure(rsrc_data->bus_rd_type); + mutex_lock(&rsrc_data->common_data->bus_mutex); + if (secure_caps) { + if (rsrc_data->secure_mode == + rsrc_data->common_data->secure_mode) { + rsrc_data->common_data->num_sec_out--; + rsrc_data->secure_mode = + CAM_SECURE_MODE_NON_SECURE; + } else { + /* + * The validity of the mode is properly + * checked while acquiring the output port. + * not expected to reach here, unless there is + * some corruption. + */ + CAM_ERR(CAM_ISP, "driver[%d],resource[%d] mismatch", + rsrc_data->common_data->secure_mode, + rsrc_data->secure_mode); + } + + if (!rsrc_data->common_data->num_sec_out) + rsrc_data->common_data->secure_mode = + CAM_SECURE_MODE_NON_SECURE; + } + mutex_unlock(&rsrc_data->common_data->bus_mutex); + + if (vfe_bus_rd->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) + vfe_bus_rd->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + return 0; +} + +static int cam_vfe_bus_start_vfe_bus_rd( + struct cam_isp_resource_node *vfe_out) +{ + int rc = 0, i; + struct cam_vfe_bus_rd_ver1_vfe_bus_rd_data *rsrc_data = NULL; + struct cam_vfe_bus_rd_ver1_common_data *common_data = NULL; + + if (!vfe_out) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + + rsrc_data = vfe_out->res_priv; + common_data = rsrc_data->common_data; + + CAM_DBG(CAM_ISP, "Start resource type: %x", rsrc_data->bus_rd_type); + + if (vfe_out->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Invalid resource state:%d", + vfe_out->res_state); + return -EACCES; + } + + for (i = 0; i < rsrc_data->num_rm; i++) + rc = cam_vfe_bus_start_rm(rsrc_data->rm_res[i]); + vfe_out->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + return rc; +} + +static int cam_vfe_bus_stop_vfe_bus_rd( + struct cam_isp_resource_node *vfe_bus_rd) +{ + int rc = 0, i; + struct cam_vfe_bus_rd_ver1_vfe_bus_rd_data *rsrc_data = NULL; + + CAM_DBG(CAM_ISP, "E:Stop rd Res"); + if (!vfe_bus_rd) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + + rsrc_data = vfe_bus_rd->res_priv; + + if (vfe_bus_rd->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE || + vfe_bus_rd->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_DBG(CAM_ISP, "vfe_out res_state is %d", + vfe_bus_rd->res_state); + return rc; + } + for (i = 0; i < rsrc_data->num_rm; i++) + rc = cam_vfe_bus_stop_rm(rsrc_data->rm_res[i]); + + vfe_bus_rd->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + return rc; +} + +static int cam_vfe_bus_init_vfe_bus_read_resource(uint32_t index, + struct cam_vfe_bus_rd_ver1_priv *bus_rd_priv, + struct cam_vfe_bus_rd_ver1_hw_info *bus_rd_hw_info) +{ + struct cam_isp_resource_node *vfe_bus_rd = NULL; + struct cam_vfe_bus_rd_ver1_vfe_bus_rd_data *rsrc_data = NULL; + int rc = 0; + int32_t vfe_bus_rd_resc_type = + bus_rd_hw_info->vfe_bus_rd_hw_info[index].vfe_bus_rd_type; + + if (vfe_bus_rd_resc_type < 0 || + vfe_bus_rd_resc_type > CAM_VFE_BUS_RD_VER1_VFE_BUSRD_RDI0) { + CAM_ERR(CAM_ISP, "Init VFE Out failed, Invalid type=%d", + vfe_bus_rd_resc_type); + return -EINVAL; + } + + vfe_bus_rd = &bus_rd_priv->vfe_bus_rd[vfe_bus_rd_resc_type]; + if (vfe_bus_rd->res_state != CAM_ISP_RESOURCE_STATE_UNAVAILABLE || + vfe_bus_rd->res_priv) { + CAM_ERR(CAM_ISP, + "Error. Looks like same resource is init again"); + return -EFAULT; + } + + rsrc_data = kzalloc(sizeof(struct cam_vfe_bus_rd_ver1_vfe_bus_rd_data), + GFP_KERNEL); + if (!rsrc_data) { + rc = -ENOMEM; + return rc; + } + + vfe_bus_rd->res_priv = rsrc_data; + + vfe_bus_rd->res_type = CAM_ISP_RESOURCE_VFE_BUS_RD; + vfe_bus_rd->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&vfe_bus_rd->list); + + rsrc_data->bus_rd_type = + bus_rd_hw_info->vfe_bus_rd_hw_info[index].vfe_bus_rd_type; + rsrc_data->common_data = &bus_rd_priv->common_data; + rsrc_data->max_width = + bus_rd_hw_info->vfe_bus_rd_hw_info[index].max_width; + rsrc_data->max_height = + bus_rd_hw_info->vfe_bus_rd_hw_info[index].max_height; + rsrc_data->secure_mode = CAM_SECURE_MODE_NON_SECURE; + + vfe_bus_rd->start = cam_vfe_bus_start_vfe_bus_rd; + vfe_bus_rd->stop = cam_vfe_bus_stop_vfe_bus_rd; + vfe_bus_rd->process_cmd = cam_vfe_bus_process_cmd; + vfe_bus_rd->hw_intf = bus_rd_priv->common_data.hw_intf; + + return 0; +} + +static int cam_vfe_bus_deinit_vfe_bus_rd_resource( + struct cam_isp_resource_node *vfe_bus_rd_res) +{ + struct cam_vfe_bus_ver2_vfe_out_data *rsrc_data = + vfe_bus_rd_res->res_priv; + + if (vfe_bus_rd_res->res_state == CAM_ISP_RESOURCE_STATE_UNAVAILABLE) { + /* + * This is not error. It can happen if the resource is + * never supported in the HW. + */ + CAM_DBG(CAM_ISP, "HW%d Res %d already deinitialized"); + return 0; + } + + vfe_bus_rd_res->start = NULL; + vfe_bus_rd_res->stop = NULL; + vfe_bus_rd_res->top_half_handler = NULL; + vfe_bus_rd_res->bottom_half_handler = NULL; + vfe_bus_rd_res->hw_intf = NULL; + + vfe_bus_rd_res->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + INIT_LIST_HEAD(&vfe_bus_rd_res->list); + vfe_bus_rd_res->res_priv = NULL; + + if (!rsrc_data) + return -ENOMEM; + kfree(rsrc_data); + + return 0; +} + +static int cam_vfe_bus_rd_ver1_handle_irq(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + struct cam_vfe_bus_rd_ver1_priv *bus_priv; + + bus_priv = th_payload->handler_priv; + CAM_DBG(CAM_ISP, "BUS READ IRQ Received"); + return 0; +} + +static int cam_vfe_bus_rd_update_rm(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_vfe_bus_rd_ver1_priv *bus_priv; + struct cam_isp_hw_get_cmd_update *update_buf; + struct cam_buf_io_cfg *io_cfg; + struct cam_vfe_bus_rd_ver1_vfe_bus_rd_data *vfe_bus_rd_data = NULL; + struct cam_vfe_bus_rd_ver1_rm_resource_data *rm_data = NULL; + uint32_t *reg_val_pair; + uint32_t i, j, size = 0; + uint32_t val; + uint32_t buf_size = 0; + + bus_priv = (struct cam_vfe_bus_rd_ver1_priv *) priv; + update_buf = (struct cam_isp_hw_get_cmd_update *) cmd_args; + + vfe_bus_rd_data = (struct cam_vfe_bus_rd_ver1_vfe_bus_rd_data *) + update_buf->res->res_priv; + + if (!vfe_bus_rd_data || !vfe_bus_rd_data->cdm_util_ops) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "#of RM: %d", vfe_bus_rd_data->num_rm); + if (update_buf->rm_update->num_buf != vfe_bus_rd_data->num_rm) { + CAM_ERR(CAM_ISP, + "Failed! Invalid number buffers:%d required:%d", + update_buf->rm_update->num_buf, + vfe_bus_rd_data->num_rm); + return -EINVAL; + } + + reg_val_pair = &vfe_bus_rd_data->common_data->io_buf_update[0]; + io_cfg = update_buf->rm_update->io_cfg; + + for (i = 0, j = 0; i < vfe_bus_rd_data->num_rm; i++) { + if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { + CAM_ERR(CAM_ISP, + "reg_val_pair %d exceeds the array limit %lu", + j, MAX_REG_VAL_PAIR_SIZE); + return -ENOMEM; + } + + rm_data = vfe_bus_rd_data->rm_res[i]->res_priv; + + /* update size register */ + rm_data->width = io_cfg->planes[i].width; + rm_data->height = io_cfg->planes[i].height; + CAM_DBG(CAM_ISP, "RM %d image w 0x%x h 0x%x image size 0x%x", + rm_data->index, rm_data->width, rm_data->height, + buf_size); + + buf_size = ((rm_data->width)&(0x0000FFFF)) | + ((rm_data->height<<16)&(0xFFFF0000)); + + CAM_DBG(CAM_ISP, "size offset 0x%x buf_size 0x%x", + rm_data->hw_regs->buf_size, buf_size); + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + rm_data->hw_regs->buf_size, buf_size); + CAM_DBG(CAM_ISP, "RM %d image size 0x%x", + rm_data->index, reg_val_pair[j-1]); + + val = rm_data->width; + CAM_DBG(CAM_ISP, "io_cfg stride 0x%x", val); + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + rm_data->hw_regs->stride, + val); + rm_data->stride = val; + CAM_DBG(CAM_ISP, "RM %d image stride 0x%x", + rm_data->index, reg_val_pair[j-1]); + + /* RM Image address */ + CAM_DBG(CAM_ISP, "image_addr offset %x", + rm_data->hw_regs->image_addr); + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + rm_data->hw_regs->image_addr, + update_buf->rm_update->image_buf[i] + + rm_data->offset); + CAM_DBG(CAM_ISP, "RM %d image address 0x%x", + rm_data->index, reg_val_pair[j-1]); + rm_data->img_addr = reg_val_pair[j-1]; + + } + + size = vfe_bus_rd_data->cdm_util_ops->cdm_required_size_reg_random(j/2); + + /* cdm util returns dwords, need to convert to bytes */ + if ((size * 4) > update_buf->cmd.size) { + CAM_ERR(CAM_ISP, + "Failed! Buf size:%d insufficient, expected size:%d", + update_buf->cmd.size, size); + return -ENOMEM; + } + + vfe_bus_rd_data->cdm_util_ops->cdm_write_regrandom( + update_buf->cmd.cmd_buf_addr, j/2, reg_val_pair); + + /* cdm util returns dwords, need to convert to bytes */ + update_buf->cmd.used_bytes = size * 4; + + return 0; +} + +static int cam_vfe_bus_rd_update_hfr(void *priv, void *cmd_args, + uint32_t arg_size) +{ + return 0; +} + +static int cam_vfe_bus_rd_update_fs_cfg(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_vfe_bus_rd_ver1_priv *bus_priv; + struct cam_vfe_bus_rd_ver1_vfe_bus_rd_data *vfe_bus_rd_data = NULL; + struct cam_vfe_bus_rd_ver1_rm_resource_data *rm_data = NULL; + struct cam_vfe_fe_update_args *fe_upd_args; + struct cam_fe_config *fe_cfg; + struct cam_vfe_bus_rd_ver1_common_data *common_data; + int i = 0; + + bus_priv = (struct cam_vfe_bus_rd_ver1_priv *) priv; + fe_upd_args = (struct cam_vfe_fe_update_args *)cmd_args; + + vfe_bus_rd_data = (struct cam_vfe_bus_rd_ver1_vfe_bus_rd_data *) + fe_upd_args->node_res->res_priv; + + if (!vfe_bus_rd_data || !vfe_bus_rd_data->cdm_util_ops) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + fe_cfg = &fe_upd_args->fe_config; + + for (i = 0; i < vfe_bus_rd_data->num_rm; i++) { + + rm_data = vfe_bus_rd_data->rm_res[i]->res_priv; + common_data = rm_data->common_data; + + rm_data->format = fe_cfg->format; + CAM_DBG(CAM_ISP, "format: 0x%x", rm_data->format); + + rm_data->unpacker_cfg = fe_cfg->unpacker_cfg; + CAM_DBG(CAM_ISP, "unpacker_cfg: 0x%x", rm_data->unpacker_cfg); + + rm_data->latency_buf_allocation = fe_cfg->latency_buf_size; + CAM_DBG(CAM_ISP, "latency_buf_allocation: 0x%x", + rm_data->latency_buf_allocation); + + rm_data->stride = fe_cfg->stride; + CAM_DBG(CAM_ISP, "stride: 0x%x", rm_data->stride); + + rm_data->go_cmd_sel = fe_cfg->go_cmd_sel; + CAM_DBG(CAM_ISP, "go_cmd_sel: 0x%x", rm_data->go_cmd_sel); + + rm_data->fs_sync_enable = fe_cfg->fs_sync_enable; + CAM_DBG(CAM_ISP, "fs_sync_enable: 0x%x", + rm_data->fs_sync_enable); + + rm_data->hbi_count = fe_cfg->hbi_count; + CAM_DBG(CAM_ISP, "hbi_count: 0x%x", rm_data->hbi_count); + + rm_data->fs_line_sync_en = fe_cfg->fs_line_sync_en; + CAM_DBG(CAM_ISP, "fs_line_sync_en: 0x%x", + rm_data->fs_line_sync_en); + + rm_data->fs_mode = fe_cfg->fs_mode; + CAM_DBG(CAM_ISP, "fs_mode: 0x%x", rm_data->fs_mode); + + rm_data->min_vbi = fe_cfg->min_vbi; + CAM_DBG(CAM_ISP, "min_vbi: 0x%x", rm_data->min_vbi); + } + bus_priv->common_data.fs_sync_enable = fe_cfg->fs_sync_enable; + bus_priv->common_data.go_cmd_sel = fe_cfg->go_cmd_sel; + return 0; +} + +static int cam_vfe_bus_start_hw(void *hw_priv, + void *start_hw_args, uint32_t arg_size) +{ + return cam_vfe_bus_start_vfe_bus_rd(hw_priv); +} + +static int cam_vfe_bus_stop_hw(void *hw_priv, + void *stop_hw_args, uint32_t arg_size) +{ + return cam_vfe_bus_stop_vfe_bus_rd(hw_priv); +} + +static int cam_vfe_bus_init_hw(void *hw_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_vfe_bus_rd_ver1_priv *bus_priv = hw_priv; + uint32_t top_irq_reg_mask[3] = {0}; + uint32_t offset = 0, val = 0; + struct cam_vfe_bus_rd_ver1_reg_offset_common *common_reg; + + if (!bus_priv) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + common_reg = bus_priv->common_data.common_reg; + top_irq_reg_mask[0] = (1 << 23); + + bus_priv->irq_handle = cam_irq_controller_subscribe_irq( + bus_priv->common_data.vfe_irq_controller, + CAM_IRQ_PRIORITY_2, + top_irq_reg_mask, + bus_priv, + cam_vfe_bus_rd_ver1_handle_irq, + NULL, + NULL, + NULL); + + if (bus_priv->irq_handle < 1) { + CAM_ERR(CAM_ISP, "Failed to subscribe BUS IRQ"); + bus_priv->irq_handle = 0; + return -EFAULT; + } + /* no clock gating at bus input */ + offset = common_reg->cgc_ovd; + cam_io_w_mb(0x0, bus_priv->common_data.mem_base + offset); + + /* BUS_RD_TEST_BUS_CTRL */ + offset = common_reg->test_bus_ctrl; + cam_io_w_mb(0x0, bus_priv->common_data.mem_base + offset); + + /* Read irq mask */ + offset = common_reg->irq_reg_info.irq_reg_set->mask_reg_offset; + cam_io_w_mb(0x5, bus_priv->common_data.mem_base + offset); + + /* INPUT_IF_CMD */ + val = (bus_priv->common_data.fs_sync_enable << 5) | + (bus_priv->common_data.go_cmd_sel << 4); + offset = common_reg->input_if_cmd; + cam_io_w_mb(val, bus_priv->common_data.mem_base + offset); + return 0; +} + +static int cam_vfe_bus_deinit_hw(void *hw_priv, + void *deinit_hw_args, uint32_t arg_size) +{ + struct cam_vfe_bus_rd_ver1_priv *bus_priv = hw_priv; + int rc = 0; + + if (!bus_priv) { + CAM_ERR(CAM_ISP, "Error: Invalid args"); + return -EINVAL; + } + + if (bus_priv->error_irq_handle) { + rc = cam_irq_controller_unsubscribe_irq( + bus_priv->common_data.bus_irq_controller, + bus_priv->error_irq_handle); + bus_priv->error_irq_handle = 0; + } + + if (bus_priv->irq_handle) { + rc = cam_irq_controller_unsubscribe_irq( + bus_priv->common_data.vfe_irq_controller, + bus_priv->irq_handle); + bus_priv->irq_handle = 0; + } + + return rc; +} + +static int __cam_vfe_bus_process_cmd(void *priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + return cam_vfe_bus_process_cmd(priv, cmd_type, cmd_args, arg_size); +} + +static int cam_vfe_bus_process_cmd( + struct cam_isp_resource_node *priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = -EINVAL; + + if (!priv || !cmd_args) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_BUF_UPDATE_RM: + rc = cam_vfe_bus_rd_update_rm(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_GET_HFR_UPDATE_RM: + rc = cam_vfe_bus_rd_update_hfr(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_GET_SECURE_MODE: + rc = cam_vfe_bus_rd_get_secure_mode(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_FE_UPDATE_BUS_RD: + rc = cam_vfe_bus_rd_update_fs_cfg(priv, cmd_args, arg_size); + break; + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid camif process command:%d", + cmd_type); + break; + } + + return rc; +} + +int cam_vfe_bus_rd_ver1_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *bus_hw_info, + void *vfe_irq_controller, + struct cam_vfe_bus **vfe_bus) +{ + int i, rc = 0; + struct cam_vfe_bus_rd_ver1_priv *bus_priv = NULL; + struct cam_vfe_bus *vfe_bus_local; + struct cam_vfe_bus_rd_ver1_hw_info *bus_rd_hw_info = bus_hw_info; + + if (!soc_info || !hw_intf || !bus_hw_info || !vfe_irq_controller) { + CAM_ERR(CAM_ISP, + "Inval_prms soc_info:%pK hw_intf:%pK hw_info%pK", + soc_info, hw_intf, bus_rd_hw_info); + CAM_ERR(CAM_ISP, "controller: %pK", vfe_irq_controller); + rc = -EINVAL; + goto end; + } + + vfe_bus_local = kzalloc(sizeof(struct cam_vfe_bus), GFP_KERNEL); + if (!vfe_bus_local) { + CAM_DBG(CAM_ISP, "Failed to alloc for vfe_bus"); + rc = -ENOMEM; + goto end; + } + + bus_priv = kzalloc(sizeof(struct cam_vfe_bus_rd_ver1_priv), + GFP_KERNEL); + if (!bus_priv) { + CAM_DBG(CAM_ISP, "Failed to alloc for vfe_bus_priv"); + rc = -ENOMEM; + goto free_bus_local; + } + + vfe_bus_local->bus_priv = bus_priv; + + bus_priv->num_client = bus_rd_hw_info->num_client; + bus_priv->num_bus_rd_resc = + bus_rd_hw_info->num_bus_rd_resc; + bus_priv->common_data.num_sec_out = 0; + bus_priv->common_data.secure_mode = CAM_SECURE_MODE_NON_SECURE; + bus_priv->common_data.core_index = soc_info->index; + bus_priv->common_data.mem_base = + CAM_SOC_GET_REG_MAP_START(soc_info, VFE_CORE_BASE_IDX); + bus_priv->common_data.hw_intf = hw_intf; + bus_priv->common_data.vfe_irq_controller = vfe_irq_controller; + bus_priv->common_data.common_reg = &bus_rd_hw_info->common_reg; + + mutex_init(&bus_priv->common_data.bus_mutex); + + rc = cam_irq_controller_init(drv_name, bus_priv->common_data.mem_base, + &bus_rd_hw_info->common_reg.irq_reg_info, + &bus_priv->common_data.bus_irq_controller, true); + if (rc) { + CAM_ERR(CAM_ISP, "cam_irq_controller_init failed"); + goto free_bus_priv; + } + + for (i = 0; i < bus_priv->num_client; i++) { + rc = cam_vfe_bus_init_rm_resource(i, bus_priv, bus_hw_info, + &bus_priv->bus_client[i]); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Init RM failed rc=%d", rc); + goto deinit_rm; + } + } + + for (i = 0; i < bus_priv->num_bus_rd_resc; i++) { + rc = cam_vfe_bus_init_vfe_bus_read_resource(i, bus_priv, + bus_rd_hw_info); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Init VFE Out failed rc=%d", rc); + goto deinit_vfe_bus_rd; + } + } + + spin_lock_init(&bus_priv->common_data.spin_lock); + + vfe_bus_local->hw_ops.reserve = cam_vfe_bus_acquire_vfe_bus_rd; + vfe_bus_local->hw_ops.release = cam_vfe_bus_release_vfe_bus_rd; + vfe_bus_local->hw_ops.start = cam_vfe_bus_start_hw; + vfe_bus_local->hw_ops.stop = cam_vfe_bus_stop_hw; + vfe_bus_local->hw_ops.init = cam_vfe_bus_init_hw; + vfe_bus_local->hw_ops.deinit = cam_vfe_bus_deinit_hw; + vfe_bus_local->top_half_handler = cam_vfe_bus_rd_ver1_handle_irq; + vfe_bus_local->bottom_half_handler = NULL; + vfe_bus_local->hw_ops.process_cmd = __cam_vfe_bus_process_cmd; + + *vfe_bus = vfe_bus_local; + + return rc; + +deinit_vfe_bus_rd: + if (i < 0) + i = CAM_VFE_BUS_RD_VER1_VFE_BUSRD_MAX; + for (--i; i >= 0; i--) + cam_vfe_bus_deinit_vfe_bus_rd_resource( + &bus_priv->vfe_bus_rd[i]); +deinit_rm: + if (i < 0) + i = bus_priv->num_client; + for (--i; i >= 0; i--) + cam_vfe_bus_deinit_rm_resource(&bus_priv->bus_client[i]); + +free_bus_priv: + kfree(vfe_bus_local->bus_priv); + +free_bus_local: + kfree(vfe_bus_local); + +end: + return rc; +} + +int cam_vfe_bus_rd_bus_ver1_deinit( + struct cam_vfe_bus **vfe_bus) +{ + int i, rc = 0; + struct cam_vfe_bus_rd_ver1_priv *bus_priv = NULL; + struct cam_vfe_bus *vfe_bus_local; + + if (!vfe_bus || !*vfe_bus) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + vfe_bus_local = *vfe_bus; + + bus_priv = vfe_bus_local->bus_priv; + if (!bus_priv) { + CAM_ERR(CAM_ISP, "bus_priv is NULL"); + rc = -ENODEV; + goto free_bus_local; + } + + for (i = 0; i < bus_priv->num_client; i++) { + rc = cam_vfe_bus_deinit_rm_resource(&bus_priv->bus_client[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Deinit RM failed rc=%d", rc); + } + for (i = 0; i < CAM_VFE_BUS_RD_VER1_VFE_BUSRD_MAX; i++) { + rc = cam_vfe_bus_deinit_vfe_bus_rd_resource( + &bus_priv->vfe_bus_rd[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Deinit VFE Out failed rc=%d", rc); + } + + rc = cam_irq_controller_deinit( + &bus_priv->common_data.bus_irq_controller); + if (rc) + CAM_ERR(CAM_ISP, + "Deinit IRQ Controller failed rc=%d", rc); + + mutex_destroy(&bus_priv->common_data.bus_mutex); + kfree(vfe_bus_local->bus_priv); + +free_bus_local: + kfree(vfe_bus_local); + + *vfe_bus = NULL; + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_rd_ver1.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_rd_ver1.h new file mode 100644 index 0000000000000000000000000000000000000000..19cc86496371b51bc310aa4c818dd8726d5cf847 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_rd_ver1.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_BUS_R_VER1_H_ +#define _CAM_VFE_BUS_R_VER1_H_ + +#include "cam_irq_controller.h" +#include "cam_vfe_bus.h" + +#define CAM_VFE_BUS_RD_VER1_MAX_CLIENTS 1 + +enum cam_vfe_bus_rd_ver1_vfe_core_id { + CAM_VFE_BUS_RD_VER1_VFE_CORE_0, + CAM_VFE_BUS_RD_VER1_VFE_CORE_1, + CAM_VFE_BUS_RD_VER1_VFE_CORE_MAX, +}; + +enum cam_vfe_bus_rd_ver1_comp_grp_type { + CAM_VFE_BUS_RD_VER1_COMP_GRP_0, + CAM_VFE_BUS_RD_VER1_COMP_GRP_MAX, +}; + + +enum cam_vfe_bus_rd_ver1_vfe_bus_rd_type { + CAM_VFE_BUS_RD_VER1_VFE_BUSRD_RDI0, + CAM_VFE_BUS_RD_VER1_VFE_BUSRD_MAX, +}; + +/* + * struct cam_vfe_bus_rd_ver1_reg_offset_common: + * + * @Brief: Common registers across all BUS Clients + */ +struct cam_vfe_bus_rd_ver1_reg_offset_common { + uint32_t hw_version; + uint32_t hw_capability; + uint32_t sw_reset; + uint32_t cgc_ovd; + uint32_t pwr_iso_cfg; + uint32_t input_if_cmd; + uint32_t test_bus_ctrl; + struct cam_irq_controller_reg_info irq_reg_info; +}; + +/* + * struct cam_vfe_bus_rd_ver1_reg_offset_bus_client: + * + * @Brief: Register offsets for BUS Clients + */ +struct cam_vfe_bus_rd_ver1_reg_offset_bus_client { + uint32_t cfg; + uint32_t image_addr; + uint32_t buf_size; + uint32_t stride; + uint32_t unpacker_cfg; + uint32_t latency_buf_allocation; + uint32_t burst_limit; +}; + +/* + * struct cam_vfe_bus_rd_ver1_vfe_bus_hw_info: + * + * @Brief: HW capability of VFE Bus Client + */ +struct cam_vfe_bus_rd_ver1_vfe_bus_hw_info { + enum cam_vfe_bus_rd_ver1_vfe_bus_rd_type vfe_bus_rd_type; + uint32_t max_width; + uint32_t max_height; +}; + +/* + * struct cam_vfe_bus_rd_ver1_hw_info: + * + * @Brief: HW register info for entire Bus + * + * @common_reg: Common register details + * @bus_client_reg: Bus client register info + * @comp_reg_grp: Composite group register info + * @vfe_out_hw_info: VFE output capability + */ +struct cam_vfe_bus_rd_ver1_hw_info { + struct cam_vfe_bus_rd_ver1_reg_offset_common common_reg; + uint32_t num_client; + struct cam_vfe_bus_rd_ver1_reg_offset_bus_client + bus_client_reg[CAM_VFE_BUS_RD_VER1_MAX_CLIENTS]; + uint32_t num_bus_rd_resc; + struct cam_vfe_bus_rd_ver1_vfe_bus_hw_info + vfe_bus_rd_hw_info[CAM_VFE_BUS_RD_VER1_VFE_BUSRD_MAX]; +}; + +/* + * cam_vfe_bus_rd_ver1_init() + * + * @Brief: Initialize Bus layer + * + * @soc_info: Soc Information for the associated HW + * @hw_intf: HW Interface of HW to which this resource belongs + * @bus_hw_info: BUS HW info that contains details of BUS registers + * @vfe_irq_controller: VFE IRQ Controller to use for subscribing to Top + * level IRQs + * @vfe_bus: Pointer to vfe_bus structure which will be filled + * and returned on successful initialize + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_bus_rd_ver1_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *bus_hw_info, + void *vfe_irq_controller, + struct cam_vfe_bus **vfe_bus); + +/* + * cam_vfe_bus_rd_bus_ver1_deinit() + * + * @Brief: Deinitialize Bus layer + * + * @vfe_bus: Pointer to vfe_bus structure to deinitialize + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_bus_rd_bus_ver1_deinit(struct cam_vfe_bus **vfe_bus); + +#endif /* _CAM_VFE_BUS_R_VER1_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver1.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver1.h new file mode 100644 index 0000000000000000000000000000000000000000..2783ddccf2d82a163a7a871ba5b4cc03d0cb4126 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver1.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_BUS_VER1_H_ +#define _CAM_VFE_BUS_VER1_H_ + +enum cam_vfe_bus_ver1_pingpong_id { + CAM_VFE_BUS_VER1_PING, + CAM_VFE_BUS_VER1_PONG, + CAM_VFE_BUS_VER1_PINGPONG_MAX, +}; + +enum cam_vfe_bus_ver1_wm_type { + CAM_VFE_BUS_WM_TYPE_IMAGE, + CAM_VFE_BUS_WM_TYPE_STATS, + CAM_VFE_BUS_WM_TYPE_MAX, +}; + +enum cam_vfe_bus_ver1_comp_grp_type { + CAM_VFE_BUS_VER1_COMP_GRP_IMG0, + CAM_VFE_BUS_VER1_COMP_GRP_IMG1, + CAM_VFE_BUS_VER1_COMP_GRP_IMG2, + CAM_VFE_BUS_VER1_COMP_GRP_IMG3, + CAM_VFE_BUS_VER1_COMP_GRP_STATS0, + CAM_VFE_BUS_VER1_COMP_GRP_STATS1, + CAM_VFE_BUS_VER1_COMP_GRP_MAX, +}; + +struct cam_vfe_bus_ver1_common_reg { + uint32_t cmd_offset; + uint32_t cfg_offset; + uint32_t io_fmt_offset; + uint32_t argb_cfg_offset; + uint32_t xbar_cfg0_offset; + uint32_t xbar_cfg1_offset; + uint32_t xbar_cfg2_offset; + uint32_t xbar_cfg3_offset; + uint32_t ping_pong_status_reg; +}; + +struct cam_vfe_bus_ver1_wm_reg { + uint32_t wm_cfg_offset; + uint32_t ping_addr_offset; + uint32_t ping_max_addr_offset; + uint32_t pong_addr_offset; + uint32_t pong_max_addr_offset; + uint32_t addr_cfg_offset; + uint32_t ub_cfg_offset; + uint32_t image_size_offset; + uint32_t buffer_cfg_offset; + uint32_t framedrop_pattern_offset; + uint32_t irq_subsample_pattern_offset; + uint32_t ping_pong_status_bit; /* 0 - 31 */ + uint32_t composite_bit; /* 0 -31 */ +}; + +struct cam_vfe_bus_ver1_wm_resource_data { + uint32_t index; + uint32_t wm_type; + uint32_t res_type; + + uint32_t offset; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t scanline; + + uint32_t burst_len; + + uint32_t framedrop_period; + uint32_t framedrop_pattern; + + uint32_t buf_valid[CAM_VFE_BUS_VER1_PINGPONG_MAX]; + uint32_t ub_size; + uint32_t ub_offset; + + struct cam_vfe_bus_ver1_wm_reg hw_regs; +}; + +struct cam_vfe_bus_ver1_comp_grp_reg { + enum cam_vfe_bus_ver1_comp_grp_type comp_grp_type; + uint32_t comp_grp_offset; +}; + +struct cam_vfe_bus_ver1_comp_grp { + struct cam_vfe_bus_ver1_comp_grp_reg reg_info; + struct list_head wm_list; + uint32_t cur_bit_mask; +}; + +/* + * cam_vfe_bus_ver1_init() + * + * @Brief: Initialize Bus layer + * + * @mem_base: Mapped base address of register space + * @hw_intf: HW Interface of HW to which this resource belongs + * @bus_hw_info: BUS HW info that contains details of BUS registers + * @vfe_irq_controller: VFE IRQ Controller to use for subscribing to Top + * level IRQs + * @vfe_bus: Pointer to vfe_bus structure which will be filled + * and returned on successful initialize + */ +int cam_vfe_bus_ver1_init( + void __iomem *mem_base, + struct cam_hw_intf *hw_intf, + void *bus_hw_info, + void *vfe_irq_controller, + struct cam_vfe_bus **vfe_bus); + +#endif /* _CAM_VFE_BUS_VER1_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c new file mode 100644 index 0000000000000000000000000000000000000000..7dc3b88e1cb60612b05215b45a13f23eff853252 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c @@ -0,0 +1,3784 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include "cam_io_util.h" +#include "cam_debug_util.h" +#include "cam_cdm_util.h" +#include "cam_hw_intf.h" +#include "cam_ife_hw_mgr.h" +#include "cam_vfe_hw_intf.h" +#include "cam_irq_controller.h" +#include "cam_tasklet_util.h" +#include "cam_vfe_bus.h" +#include "cam_vfe_bus_ver2.h" +#include "cam_vfe_core.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" + +static const char drv_name[] = "vfe_bus"; + +#define CAM_VFE_BUS_IRQ_REG0 0 +#define CAM_VFE_BUS_IRQ_REG1 1 +#define CAM_VFE_BUS_IRQ_REG2 2 +#define CAM_VFE_BUS_IRQ_MAX 3 + +#define CAM_VFE_BUS_VER2_PAYLOAD_MAX 256 + +#define CAM_VFE_BUS_SET_DEBUG_REG 0x82 + +#define CAM_VFE_RDI_BUS_DEFAULT_WIDTH 0xFF01 +#define CAM_VFE_RDI_BUS_DEFAULT_STRIDE 0xFF01 +#define CAM_VFE_BUS_INTRA_CLIENT_MASK 0x3 +#define CAM_VFE_BUS_ADDR_SYNC_INTRA_CLIENT_SHIFT 8 +#define CAM_VFE_BUS_ADDR_NO_SYNC_DEFAULT_VAL \ + ((1 << CAM_VFE_BUS_VER2_MAX_CLIENTS) - 1) + +#define MAX_BUF_UPDATE_REG_NUM \ + ((sizeof(struct cam_vfe_bus_ver2_reg_offset_bus_client) + \ + sizeof(struct cam_vfe_bus_ver2_reg_offset_ubwc_client))/4) +#define MAX_REG_VAL_PAIR_SIZE \ + (MAX_BUF_UPDATE_REG_NUM * 2 * CAM_PACKET_MAX_PLANES) + +static uint32_t bus_error_irq_mask[3] = { + 0x7800, + 0x0000, + 0x0040, +}; + +enum cam_vfe_bus_packer_format { + PACKER_FMT_PLAIN_128 = 0x0, + PACKER_FMT_PLAIN_8 = 0x1, + PACKER_FMT_PLAIN_16_10BPP = 0x2, + PACKER_FMT_PLAIN_16_12BPP = 0x3, + PACKER_FMT_PLAIN_16_14BPP = 0x4, + PACKER_FMT_PLAIN_16_16BPP = 0x5, + PACKER_FMT_ARGB_10 = 0x6, + PACKER_FMT_ARGB_12 = 0x7, + PACKER_FMT_ARGB_14 = 0x8, + PACKER_FMT_PLAIN_32_20BPP = 0x9, + PACKER_FMT_PLAIN_64 = 0xA, + PACKER_FMT_TP_10 = 0xB, + PACKER_FMT_PLAIN_32_32BPP = 0xC, + PACKER_FMT_PLAIN_8_ODD_EVEN = 0xD, + PACKER_FMT_PLAIN_8_LSB_MSB_10 = 0xE, + PACKER_FMT_PLAIN_8_LSB_MSB_10_ODD_EVEN = 0xF, + PACKER_FMT_MAX = 0xF, +}; + +enum cam_vfe_bus_comp_grp_id { + CAM_VFE_BUS_COMP_GROUP_NONE = -EINVAL, + CAM_VFE_BUS_COMP_GROUP_ID_0 = 0x0, + CAM_VFE_BUS_COMP_GROUP_ID_1 = 0x1, + CAM_VFE_BUS_COMP_GROUP_ID_2 = 0x2, + CAM_VFE_BUS_COMP_GROUP_ID_3 = 0x3, + CAM_VFE_BUS_COMP_GROUP_ID_4 = 0x4, + CAM_VFE_BUS_COMP_GROUP_ID_5 = 0x5, +}; + +struct cam_vfe_bus_ver2_common_data { + uint32_t core_index; + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + void *bus_irq_controller; + void *vfe_irq_controller; + struct cam_vfe_bus_ver2_reg_offset_common *common_reg; + uint32_t io_buf_update[ + MAX_REG_VAL_PAIR_SIZE]; + + struct cam_vfe_bus_irq_evt_payload evt_payload[ + CAM_VFE_BUS_VER2_PAYLOAD_MAX]; + struct list_head free_payload_list; + spinlock_t spin_lock; + struct mutex bus_mutex; + uint32_t secure_mode; + uint32_t num_sec_out; + uint32_t addr_no_sync; + cam_hw_mgr_event_cb_func event_cb; + bool hw_init; +}; + +struct cam_vfe_bus_ver2_wm_resource_data { + uint32_t index; + struct cam_vfe_bus_ver2_common_data *common_data; + struct cam_vfe_bus_ver2_reg_offset_bus_client *hw_regs; + + bool init_cfg_done; + bool hfr_cfg_done; + + uint32_t offset; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t format; + enum cam_vfe_bus_packer_format pack_fmt; + + uint32_t burst_len; + + uint32_t en_ubwc; + bool ubwc_updated; + uint32_t packer_cfg; + uint32_t tile_cfg; + uint32_t h_init; + uint32_t v_init; + uint32_t ubwc_meta_stride; + uint32_t ubwc_mode_cfg_0; + uint32_t ubwc_mode_cfg_1; + uint32_t ubwc_meta_offset; + + uint32_t irq_subsample_period; + uint32_t irq_subsample_pattern; + uint32_t framedrop_period; + uint32_t framedrop_pattern; + + uint32_t en_cfg; + uint32_t is_dual; + uint32_t ubwc_lossy_threshold_0; + uint32_t ubwc_lossy_threshold_1; + uint32_t ubwc_bandwidth_limit; +}; + +struct cam_vfe_bus_ver2_comp_grp_data { + enum cam_vfe_bus_ver2_comp_grp_type comp_grp_type; + struct cam_vfe_bus_ver2_common_data *common_data; + struct cam_vfe_bus_ver2_reg_offset_comp_grp *hw_regs; + + uint32_t comp_grp_local_idx; + uint32_t unique_id; + + uint32_t is_master; + uint32_t dual_slave_core; + uint32_t intra_client_mask; + uint32_t composite_mask; + uint32_t addr_sync_mode; + + uint32_t acquire_dev_cnt; +}; + +struct cam_vfe_bus_ver2_vfe_out_data { + uint32_t out_type; + struct cam_vfe_bus_ver2_common_data *common_data; + + uint32_t num_wm; + struct cam_isp_resource_node *wm_res[PLANE_MAX]; + + struct cam_isp_resource_node *comp_grp; + enum cam_isp_hw_sync_mode dual_comp_sync_mode; + uint32_t dual_hw_alternate_vfe_id; + struct list_head vfe_out_list; + + uint32_t format; + uint32_t max_width; + uint32_t max_height; + struct cam_cdm_utils_ops *cdm_util_ops; + uint32_t secure_mode; + void *priv; +}; + +struct cam_vfe_bus_ver2_priv { + struct cam_vfe_bus_ver2_common_data common_data; + uint32_t num_client; + uint32_t num_out; + + struct cam_isp_resource_node bus_client[CAM_VFE_BUS_VER2_MAX_CLIENTS]; + struct cam_isp_resource_node comp_grp[CAM_VFE_BUS_VER2_COMP_GRP_MAX]; + struct cam_isp_resource_node vfe_out[CAM_VFE_BUS_VER2_VFE_OUT_MAX]; + + struct list_head free_comp_grp; + struct list_head free_dual_comp_grp; + struct list_head used_comp_grp; + + int irq_handle; + int error_irq_handle; + void *tasklet_info; +}; + +static int cam_vfe_bus_process_cmd( + struct cam_isp_resource_node *priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size); + +static int cam_vfe_bus_get_evt_payload( + struct cam_vfe_bus_ver2_common_data *common_data, + struct cam_vfe_bus_irq_evt_payload **evt_payload) +{ + int rc; + + spin_lock(&common_data->spin_lock); + + if (!common_data->hw_init) { + *evt_payload = NULL; + CAM_ERR_RATE_LIMIT(CAM_ISP, "VFE:%d Bus uninitialized", + common_data->core_index); + rc = -EPERM; + goto done; + } + + if (list_empty(&common_data->free_payload_list)) { + *evt_payload = NULL; + CAM_ERR_RATE_LIMIT(CAM_ISP, "No free payload"); + rc = -ENODEV; + goto done; + } + + *evt_payload = list_first_entry(&common_data->free_payload_list, + struct cam_vfe_bus_irq_evt_payload, list); + list_del_init(&(*evt_payload)->list); + rc = 0; +done: + spin_unlock(&common_data->spin_lock); + return rc; +} + +static enum cam_vfe_bus_comp_grp_id + cam_vfe_bus_comp_grp_id_convert(uint32_t comp_grp) +{ + switch (comp_grp) { + case CAM_ISP_RES_COMP_GROUP_ID_0: + return CAM_VFE_BUS_COMP_GROUP_ID_0; + case CAM_ISP_RES_COMP_GROUP_ID_1: + return CAM_VFE_BUS_COMP_GROUP_ID_1; + case CAM_ISP_RES_COMP_GROUP_ID_2: + return CAM_VFE_BUS_COMP_GROUP_ID_2; + case CAM_ISP_RES_COMP_GROUP_ID_3: + return CAM_VFE_BUS_COMP_GROUP_ID_3; + case CAM_ISP_RES_COMP_GROUP_ID_4: + return CAM_VFE_BUS_COMP_GROUP_ID_4; + case CAM_ISP_RES_COMP_GROUP_ID_5: + return CAM_VFE_BUS_COMP_GROUP_ID_5; + case CAM_ISP_RES_COMP_GROUP_NONE: + default: + return CAM_VFE_BUS_COMP_GROUP_NONE; + } +} + +static int cam_vfe_bus_put_evt_payload( + struct cam_vfe_bus_ver2_common_data *common_data, + struct cam_vfe_bus_irq_evt_payload **evt_payload) +{ + unsigned long flags; + + if (!common_data) { + CAM_ERR(CAM_ISP, "Invalid param core_info NULL"); + return -EINVAL; + } + + if (*evt_payload == NULL) { + CAM_ERR(CAM_ISP, "No payload to put"); + return -EINVAL; + } + + spin_lock_irqsave(&common_data->spin_lock, flags); + if (common_data->hw_init) + list_add_tail(&(*evt_payload)->list, + &common_data->free_payload_list); + spin_unlock_irqrestore(&common_data->spin_lock, flags); + + *evt_payload = NULL; + + CAM_DBG(CAM_ISP, "Done"); + return 0; +} + +static int cam_vfe_bus_ver2_get_intra_client_mask( + enum cam_vfe_bus_ver2_vfe_core_id dual_slave_core, + enum cam_vfe_bus_ver2_vfe_core_id current_core, + uint32_t *intra_client_mask) +{ + int rc = 0; + uint32_t camera_hw_version = 0; + uint32_t version_based_intra_client_mask = 0x1; + + *intra_client_mask = 0; + + + if (dual_slave_core == current_core) { + CAM_ERR(CAM_ISP, + "Invalid params. Same core as Master and Slave"); + return -EINVAL; + } + + rc = cam_cpas_get_cpas_hw_version(&camera_hw_version); + + CAM_DBG(CAM_ISP, "CPAS VERSION %d", camera_hw_version); + + switch (camera_hw_version) { + case CAM_CPAS_TITAN_170_V100: + version_based_intra_client_mask = 0x3; + break; + default: + version_based_intra_client_mask = 0x1; + break; + } + + + switch (current_core) { + case CAM_VFE_BUS_VER2_VFE_CORE_0: + switch (dual_slave_core) { + case CAM_VFE_BUS_VER2_VFE_CORE_1: + *intra_client_mask = version_based_intra_client_mask; + break; + default: + CAM_ERR(CAM_ISP, "Invalid value for slave core %u", + dual_slave_core); + rc = -EINVAL; + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_CORE_1: + switch (dual_slave_core) { + case CAM_VFE_BUS_VER2_VFE_CORE_0: + *intra_client_mask = version_based_intra_client_mask; + break; + default: + CAM_ERR(CAM_ISP, "Invalid value for slave core %u", + dual_slave_core); + rc = -EINVAL; + break; + } + break; + default: + CAM_ERR(CAM_ISP, + "Invalid value for master core %u", current_core); + rc = -EINVAL; + break; + } + + return rc; +} + +static bool cam_vfe_bus_can_be_secure(uint32_t out_type) +{ + switch (out_type) { + case CAM_VFE_BUS_VER2_VFE_OUT_FULL: + case CAM_VFE_BUS_VER2_VFE_OUT_DS4: + case CAM_VFE_BUS_VER2_VFE_OUT_DS16: + case CAM_VFE_BUS_VER2_VFE_OUT_FD: + case CAM_VFE_BUS_VER2_VFE_OUT_RAW_DUMP: + case CAM_VFE_BUS_VER2_VFE_OUT_RDI0: + case CAM_VFE_BUS_VER2_VFE_OUT_RDI1: + case CAM_VFE_BUS_VER2_VFE_OUT_RDI2: + case CAM_VFE_BUS_VER2_VFE_OUT_FULL_DISP: + case CAM_VFE_BUS_VER2_VFE_OUT_DS4_DISP: + case CAM_VFE_BUS_VER2_VFE_OUT_DS16_DISP: + return true; + + case CAM_VFE_BUS_VER2_VFE_OUT_PDAF: + case CAM_VFE_BUS_VER2_VFE_OUT_2PD: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_TL_BG: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_AWB_BG: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_RS: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_CS: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_IHIST: + default: + return false; + } +} + +static enum cam_vfe_bus_ver2_vfe_out_type + cam_vfe_bus_get_out_res_id(uint32_t res_type) +{ + switch (res_type) { + case CAM_ISP_IFE_OUT_RES_FULL: + return CAM_VFE_BUS_VER2_VFE_OUT_FULL; + case CAM_ISP_IFE_OUT_RES_DS4: + return CAM_VFE_BUS_VER2_VFE_OUT_DS4; + case CAM_ISP_IFE_OUT_RES_DS16: + return CAM_VFE_BUS_VER2_VFE_OUT_DS16; + case CAM_ISP_IFE_OUT_RES_FD: + return CAM_VFE_BUS_VER2_VFE_OUT_FD; + case CAM_ISP_IFE_OUT_RES_RAW_DUMP: + return CAM_VFE_BUS_VER2_VFE_OUT_RAW_DUMP; + case CAM_ISP_IFE_OUT_RES_PDAF: + return CAM_VFE_BUS_VER2_VFE_OUT_PDAF; + case CAM_ISP_IFE_OUT_RES_2PD: + return CAM_VFE_BUS_VER2_VFE_OUT_2PD; + case CAM_ISP_IFE_OUT_RES_RDI_0: + return CAM_VFE_BUS_VER2_VFE_OUT_RDI0; + case CAM_ISP_IFE_OUT_RES_RDI_1: + return CAM_VFE_BUS_VER2_VFE_OUT_RDI1; + case CAM_ISP_IFE_OUT_RES_RDI_2: + return CAM_VFE_BUS_VER2_VFE_OUT_RDI2; + case CAM_ISP_IFE_OUT_RES_RDI_3: + return CAM_VFE_BUS_VER2_VFE_OUT_RDI3; + case CAM_ISP_IFE_OUT_RES_STATS_HDR_BE: + return CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE; + case CAM_ISP_IFE_OUT_RES_STATS_HDR_BHIST: + return CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST; + case CAM_ISP_IFE_OUT_RES_STATS_TL_BG: + return CAM_VFE_BUS_VER2_VFE_OUT_STATS_TL_BG; + case CAM_ISP_IFE_OUT_RES_STATS_BF: + return CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF; + case CAM_ISP_IFE_OUT_RES_STATS_AWB_BG: + return CAM_VFE_BUS_VER2_VFE_OUT_STATS_AWB_BG; + case CAM_ISP_IFE_OUT_RES_STATS_BHIST: + return CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST; + case CAM_ISP_IFE_OUT_RES_STATS_RS: + return CAM_VFE_BUS_VER2_VFE_OUT_STATS_RS; + case CAM_ISP_IFE_OUT_RES_STATS_CS: + return CAM_VFE_BUS_VER2_VFE_OUT_STATS_CS; + case CAM_ISP_IFE_OUT_RES_STATS_IHIST: + return CAM_VFE_BUS_VER2_VFE_OUT_STATS_IHIST; + case CAM_ISP_IFE_OUT_RES_FULL_DISP: + return CAM_VFE_BUS_VER2_VFE_OUT_FULL_DISP; + case CAM_ISP_IFE_OUT_RES_DS4_DISP: + return CAM_VFE_BUS_VER2_VFE_OUT_DS4_DISP; + case CAM_ISP_IFE_OUT_RES_DS16_DISP: + return CAM_VFE_BUS_VER2_VFE_OUT_DS16_DISP; + default: + return CAM_VFE_BUS_VER2_VFE_OUT_MAX; + } +} + +static int cam_vfe_bus_get_num_wm( + enum cam_vfe_bus_ver2_vfe_out_type res_type, + uint32_t format) +{ + switch (res_type) { + case CAM_VFE_BUS_VER2_VFE_OUT_RDI0: + case CAM_VFE_BUS_VER2_VFE_OUT_RDI1: + case CAM_VFE_BUS_VER2_VFE_OUT_RDI2: + case CAM_VFE_BUS_VER2_VFE_OUT_RDI3: + switch (format) { + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_MIPI_RAW_20: + case CAM_FORMAT_DPCM_10_6_10: + case CAM_FORMAT_DPCM_10_8_10: + case CAM_FORMAT_DPCM_12_6_12: + case CAM_FORMAT_DPCM_12_8_12: + case CAM_FORMAT_DPCM_14_8_14: + case CAM_FORMAT_DPCM_14_10_14: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_PLAIN16_16: + case CAM_FORMAT_PLAIN32_20: + case CAM_FORMAT_PLAIN128: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_FULL: + case CAM_VFE_BUS_VER2_VFE_OUT_FULL_DISP: + switch (format) { + case CAM_FORMAT_NV21: + case CAM_FORMAT_NV12: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_TP10: + case CAM_FORMAT_UBWC_NV12: + case CAM_FORMAT_UBWC_NV12_4R: + case CAM_FORMAT_UBWC_TP10: + case CAM_FORMAT_UBWC_P010: + case CAM_FORMAT_PLAIN16_10: + return 2; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_FD: + switch (format) { + case CAM_FORMAT_NV21: + case CAM_FORMAT_NV12: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_TP10: + case CAM_FORMAT_PLAIN16_10: + return 2; + case CAM_FORMAT_Y_ONLY: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_DS4: + case CAM_VFE_BUS_VER2_VFE_OUT_DS4_DISP: + case CAM_VFE_BUS_VER2_VFE_OUT_DS16: + case CAM_VFE_BUS_VER2_VFE_OUT_DS16_DISP: + switch (format) { + case CAM_FORMAT_PD8: + case CAM_FORMAT_PD10: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_RAW_DUMP: + switch (format) { + case CAM_FORMAT_ARGB_14: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_PDAF: + switch (format) { + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_2PD: + switch (format) { + case CAM_FORMAT_PLAIN16_8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_PLAIN16_16: + case CAM_FORMAT_PLAIN64: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_TL_BG: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_AWB_BG: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_CS: + switch (format) { + case CAM_FORMAT_PLAIN64: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_RS: + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_IHIST: + switch (format) { + case CAM_FORMAT_PLAIN16_16: + return 1; + default: + break; + } + break; + default: + break; + } + + CAM_ERR(CAM_ISP, "Unsupported format %u for resource_type %u", + format, res_type); + + return -EINVAL; +} + +static int cam_vfe_bus_get_wm_idx( + enum cam_vfe_bus_ver2_vfe_out_type vfe_out_res_id, + enum cam_vfe_bus_plane_type plane) +{ + int wm_idx = -1; + + switch (vfe_out_res_id) { + case CAM_VFE_BUS_VER2_VFE_OUT_RDI0: + switch (plane) { + case PLANE_Y: + wm_idx = 0; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_RDI1: + switch (plane) { + case PLANE_Y: + wm_idx = 1; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_RDI2: + switch (plane) { + case PLANE_Y: + wm_idx = 2; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_RDI3: + switch (plane) { + case PLANE_Y: + wm_idx = 3; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_FULL: + switch (plane) { + case PLANE_Y: + wm_idx = 3; + break; + case PLANE_C: + wm_idx = 4; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_DS4: + switch (plane) { + case PLANE_Y: + wm_idx = 5; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_DS16: + switch (plane) { + case PLANE_Y: + wm_idx = 6; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_FD: + switch (plane) { + case PLANE_Y: + wm_idx = 7; + break; + case PLANE_C: + wm_idx = 8; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_RAW_DUMP: + switch (plane) { + case PLANE_Y: + wm_idx = 9; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_PDAF: + case CAM_VFE_BUS_VER2_VFE_OUT_2PD: + switch (plane) { + case PLANE_Y: + wm_idx = 10; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE: + switch (plane) { + case PLANE_Y: + wm_idx = 11; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST: + switch (plane) { + case PLANE_Y: + wm_idx = 12; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_TL_BG: + switch (plane) { + case PLANE_Y: + wm_idx = 13; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF: + switch (plane) { + case PLANE_Y: + wm_idx = 14; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_AWB_BG: + switch (plane) { + case PLANE_Y: + wm_idx = 15; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST: + switch (plane) { + case PLANE_Y: + wm_idx = 16; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_RS: + switch (plane) { + case PLANE_Y: + wm_idx = 17; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_CS: + switch (plane) { + case PLANE_Y: + wm_idx = 18; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_STATS_IHIST: + switch (plane) { + case PLANE_Y: + wm_idx = 19; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_FULL_DISP: + switch (plane) { + case PLANE_Y: + wm_idx = 20; + break; + case PLANE_C: + wm_idx = 21; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_DS4_DISP: + switch (plane) { + case PLANE_Y: + wm_idx = 22; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER2_VFE_OUT_DS16_DISP: + switch (plane) { + case PLANE_Y: + wm_idx = 23; + break; + default: + break; + } + break; + + default: + break; + } + + return wm_idx; +} + +static void cam_vfe_bus_get_comp_vfe_out_res_id_list( + uint32_t comp_mask, uint32_t *out_list, int *num_out) +{ + int count = 0; + + if (comp_mask & 0x1) + out_list[count++] = CAM_ISP_IFE_OUT_RES_RDI_0; + + if (comp_mask & 0x2) + out_list[count++] = CAM_ISP_IFE_OUT_RES_RDI_1; + + if (comp_mask & 0x4) + out_list[count++] = CAM_ISP_IFE_OUT_RES_RDI_2; + + if ((comp_mask & 0x8) && (((comp_mask >> 4) & 0x1) == 0)) + out_list[count++] = CAM_ISP_IFE_OUT_RES_RDI_3; + + if (comp_mask & 0x18) + out_list[count++] = CAM_ISP_IFE_OUT_RES_FULL; + + if (comp_mask & 0x20) + out_list[count++] = CAM_ISP_IFE_OUT_RES_DS4; + + if (comp_mask & 0x40) + out_list[count++] = CAM_ISP_IFE_OUT_RES_DS16; + + if (comp_mask & 0x180) + out_list[count++] = CAM_ISP_IFE_OUT_RES_FD; + + if (comp_mask & 0x200) + out_list[count++] = CAM_ISP_IFE_OUT_RES_RAW_DUMP; + + if (comp_mask & 0x800) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_HDR_BE; + + if (comp_mask & 0x1000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_HDR_BHIST; + + if (comp_mask & 0x2000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_TL_BG; + + if (comp_mask & 0x4000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_BF; + + if (comp_mask & 0x8000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_AWB_BG; + + if (comp_mask & 0x10000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_BHIST; + + if (comp_mask & 0x20000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_RS; + + if (comp_mask & 0x40000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_CS; + + if (comp_mask & 0x80000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_IHIST; + + if (comp_mask & 0x300000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_FULL_DISP; + + if (comp_mask & 0x400000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_DS4_DISP; + + if (comp_mask & 0x800000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_DS16_DISP; + + *num_out = count; + +} + +static enum cam_vfe_bus_packer_format + cam_vfe_bus_get_packer_fmt(uint32_t out_fmt, int wm_index) +{ + switch (out_fmt) { + case CAM_FORMAT_NV21: + if ((wm_index == 4) || (wm_index == 6) || (wm_index == 21)) + return PACKER_FMT_PLAIN_8_LSB_MSB_10_ODD_EVEN; + case CAM_FORMAT_NV12: + case CAM_FORMAT_UBWC_NV12: + case CAM_FORMAT_UBWC_NV12_4R: + case CAM_FORMAT_Y_ONLY: + return PACKER_FMT_PLAIN_8_LSB_MSB_10; + case CAM_FORMAT_PLAIN16_16: + return PACKER_FMT_PLAIN_16_16BPP; + case CAM_FORMAT_PLAIN64: + return PACKER_FMT_PLAIN_64; + case CAM_FORMAT_PLAIN8: + return PACKER_FMT_PLAIN_8; + case CAM_FORMAT_PLAIN16_10: + return PACKER_FMT_PLAIN_16_10BPP; + case CAM_FORMAT_PLAIN16_12: + return PACKER_FMT_PLAIN_16_12BPP; + case CAM_FORMAT_PLAIN16_14: + return PACKER_FMT_PLAIN_16_14BPP; + case CAM_FORMAT_PLAIN32_20: + return PACKER_FMT_PLAIN_32_20BPP; + case CAM_FORMAT_MIPI_RAW_6: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_MIPI_RAW_20: + case CAM_FORMAT_PLAIN16_8: + case CAM_FORMAT_PLAIN128: + case CAM_FORMAT_PD8: + case CAM_FORMAT_PD10: + return PACKER_FMT_PLAIN_128; + case CAM_FORMAT_UBWC_TP10: + case CAM_FORMAT_TP10: + return PACKER_FMT_TP_10; + case CAM_FORMAT_ARGB_14: + return PACKER_FMT_ARGB_14; + default: + return PACKER_FMT_MAX; + } +} + +static int cam_vfe_bus_acquire_wm( + struct cam_vfe_bus_ver2_priv *ver2_bus_priv, + struct cam_isp_out_port_generic_info *out_port_info, + void *tasklet, + enum cam_vfe_bus_ver2_vfe_out_type vfe_out_res_id, + enum cam_vfe_bus_plane_type plane, + struct cam_isp_resource_node **wm_res, + uint32_t *client_done_mask, + uint32_t is_dual) +{ + uint32_t wm_idx = 0; + struct cam_isp_resource_node *wm_res_local = NULL; + struct cam_vfe_bus_ver2_wm_resource_data *rsrc_data = NULL; + + *wm_res = NULL; + *client_done_mask = 0; + + /* No need to allocate for BUS VER2. VFE OUT to WM is fixed. */ + wm_idx = cam_vfe_bus_get_wm_idx(vfe_out_res_id, plane); + if (wm_idx < 0 || wm_idx >= ver2_bus_priv->num_client) { + CAM_ERR(CAM_ISP, "Unsupported VFE out %d plane %d", + vfe_out_res_id, plane); + return -EINVAL; + } + + wm_res_local = &ver2_bus_priv->bus_client[wm_idx]; + if (wm_res_local->res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, "WM res not available state:%d", + wm_res_local->res_state); + return -EALREADY; + } + wm_res_local->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + wm_res_local->tasklet_info = tasklet; + + rsrc_data = wm_res_local->res_priv; + rsrc_data->format = out_port_info->format; + rsrc_data->pack_fmt = cam_vfe_bus_get_packer_fmt(rsrc_data->format, + wm_idx); + + rsrc_data->width = out_port_info->width; + rsrc_data->height = out_port_info->height; + rsrc_data->is_dual = is_dual; + /* Set WM offset value to default */ + rsrc_data->offset = 0; + CAM_DBG(CAM_ISP, "WM %d width %d height %d", rsrc_data->index, + rsrc_data->width, rsrc_data->height); + + if (rsrc_data->index < 3) { + /* Write master 0-2 refers to RDI 0/ RDI 1/RDI 2 */ + switch (rsrc_data->format) { + case CAM_FORMAT_MIPI_RAW_6: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_MIPI_RAW_20: + case CAM_FORMAT_PLAIN128: + rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->pack_fmt = 0x0; + rsrc_data->en_cfg = 0x3; + break; + case CAM_FORMAT_PLAIN8: + rsrc_data->en_cfg = 0x1; + rsrc_data->pack_fmt = 0x1; + rsrc_data->width = rsrc_data->width * 2; + rsrc_data->stride = rsrc_data->width; + break; + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_PLAIN16_16: + case CAM_FORMAT_PLAIN32_20: + rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->pack_fmt = 0x0; + rsrc_data->en_cfg = 0x3; + break; + case CAM_FORMAT_PLAIN64: + rsrc_data->en_cfg = 0x1; + rsrc_data->pack_fmt = 0xA; + break; + default: + CAM_ERR(CAM_ISP, "Unsupported RDI format %d", + rsrc_data->format); + return -EINVAL; + } + } else if ((rsrc_data->index < 5) || + (rsrc_data->index == 7) || (rsrc_data->index == 8) || + (rsrc_data->index == 20) || (rsrc_data->index == 21)) { + /* + * Write master 3, 4 - for Full OUT , 7-8 FD OUT, + * WM 20-21 = FULL_DISP + */ + switch (rsrc_data->format) { + case CAM_FORMAT_UBWC_NV12_4R: + rsrc_data->en_ubwc = 1; + rsrc_data->width = ALIGNUP(rsrc_data->width, 64); + switch (plane) { + case PLANE_C: + rsrc_data->height /= 2; + break; + case PLANE_Y: + break; + default: + CAM_ERR(CAM_ISP, "Invalid plane %d", plane); + return -EINVAL; + } + break; + case CAM_FORMAT_UBWC_NV12: + rsrc_data->en_ubwc = 1; + /* Fall through for NV12 */ + case CAM_FORMAT_NV21: + case CAM_FORMAT_NV12: + case CAM_FORMAT_Y_ONLY: + switch (plane) { + case PLANE_C: + rsrc_data->height /= 2; + break; + case PLANE_Y: + break; + default: + CAM_ERR(CAM_ISP, "Invalid plane %d", plane); + return -EINVAL; + } + break; + case CAM_FORMAT_UBWC_TP10: + rsrc_data->en_ubwc = 1; + rsrc_data->width = + ALIGNUP(rsrc_data->width, 48) * 4 / 3; + switch (plane) { + case PLANE_C: + rsrc_data->height /= 2; + break; + case PLANE_Y: + break; + default: + CAM_ERR(CAM_ISP, "Invalid plane %d", plane); + return -EINVAL; + } + break; + case CAM_FORMAT_TP10: + rsrc_data->width = + ALIGNUP(rsrc_data->width, 3) * 4 / 3; + switch (plane) { + case PLANE_C: + rsrc_data->height /= 2; + break; + case PLANE_Y: + break; + default: + CAM_ERR(CAM_ISP, "Invalid plane %d", plane); + return -EINVAL; + } + break; + case CAM_FORMAT_PLAIN16_10: + switch (plane) { + case PLANE_C: + rsrc_data->height /= 2; + break; + case PLANE_Y: + break; + default: + CAM_ERR(CAM_ISP, "Invalid plane %d", plane); + return -EINVAL; + } + rsrc_data->width *= 2; + break; + default: + CAM_ERR(CAM_ISP, "Invalid format %d", + rsrc_data->format); + return -EINVAL; + } + rsrc_data->en_cfg = 0x1; + } else if (rsrc_data->index >= 11 && rsrc_data->index < 20) { + /* Write master 11 - 19 stats */ + rsrc_data->width = 0; + rsrc_data->height = 0; + rsrc_data->stride = 1; + rsrc_data->en_cfg = 0x3; + } else if (rsrc_data->index == 10) { + /* Write master 10 - PDAF/2PD */ + rsrc_data->width = 0; + rsrc_data->height = 0; + rsrc_data->stride = 1; + rsrc_data->en_cfg = 0x3; + if (vfe_out_res_id == CAM_VFE_BUS_VER2_VFE_OUT_PDAF) + /* LSB aligned */ + rsrc_data->pack_fmt |= 0x10; + } else if (rsrc_data->index == 9) { + /* Write master 9 - Raw dump */ + rsrc_data->width = rsrc_data->width * 2; + rsrc_data->stride = rsrc_data->width; + rsrc_data->en_cfg = 0x1; + /* LSB aligned */ + rsrc_data->pack_fmt |= 0x10; + } else { + /* Write master 5-6 DS ports */ + uint32_t align_width; + + rsrc_data->width = rsrc_data->width * 4; + rsrc_data->height = rsrc_data->height / 2; + rsrc_data->en_cfg = 0x1; + CAM_DBG(CAM_ISP, "before width %d", rsrc_data->width); + align_width = ALIGNUP(rsrc_data->width, 16); + if (align_width != rsrc_data->width) { + CAM_WARN(CAM_ISP, + "Override width %u with expected %u", + rsrc_data->width, align_width); + rsrc_data->width = align_width; + } + } + + *client_done_mask = (1 << wm_idx); + *wm_res = wm_res_local; + + CAM_DBG(CAM_ISP, "WM %d: processed width %d, processed height %d", + rsrc_data->index, rsrc_data->width, rsrc_data->height); + return 0; +} + +static int cam_vfe_bus_release_wm(void *bus_priv, + struct cam_isp_resource_node *wm_res) +{ + struct cam_vfe_bus_ver2_wm_resource_data *rsrc_data = + wm_res->res_priv; + + rsrc_data->offset = 0; + rsrc_data->width = 0; + rsrc_data->height = 0; + rsrc_data->stride = 0; + rsrc_data->format = 0; + rsrc_data->pack_fmt = 0; + rsrc_data->burst_len = 0; + rsrc_data->irq_subsample_period = 0; + rsrc_data->irq_subsample_pattern = 0; + rsrc_data->framedrop_period = 0; + rsrc_data->framedrop_pattern = 0; + rsrc_data->packer_cfg = 0; + rsrc_data->en_ubwc = 0; + rsrc_data->tile_cfg = 0; + rsrc_data->h_init = 0; + rsrc_data->v_init = 0; + rsrc_data->ubwc_meta_stride = 0; + rsrc_data->ubwc_mode_cfg_0 = 0; + rsrc_data->ubwc_mode_cfg_1 = 0; + rsrc_data->ubwc_meta_offset = 0; + rsrc_data->init_cfg_done = false; + rsrc_data->hfr_cfg_done = false; + rsrc_data->en_cfg = 0; + rsrc_data->is_dual = 0; + + rsrc_data->ubwc_lossy_threshold_0 = 0; + rsrc_data->ubwc_lossy_threshold_1 = 0; + rsrc_data->ubwc_bandwidth_limit = 0; + wm_res->tasklet_info = NULL; + wm_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + return 0; +} + +static int cam_vfe_bus_start_wm( + struct cam_isp_resource_node *wm_res, + uint32_t *bus_irq_reg_mask) +{ + int rc = 0, val = 0; + struct cam_vfe_bus_ver2_wm_resource_data *rsrc_data = + wm_res->res_priv; + struct cam_vfe_bus_ver2_common_data *common_data = + rsrc_data->common_data; + uint32_t camera_hw_version; + + cam_io_w(0xf, common_data->mem_base + rsrc_data->hw_regs->burst_limit); + + cam_io_w_mb(rsrc_data->width, + common_data->mem_base + rsrc_data->hw_regs->buffer_width_cfg); + cam_io_w(rsrc_data->height, + common_data->mem_base + rsrc_data->hw_regs->buffer_height_cfg); + cam_io_w(rsrc_data->pack_fmt, + common_data->mem_base + rsrc_data->hw_regs->packer_cfg); + + /* Configure stride for RDIs */ + if (rsrc_data->index < 3) + cam_io_w_mb(rsrc_data->stride, (common_data->mem_base + + rsrc_data->hw_regs->stride)); + + bus_irq_reg_mask[CAM_VFE_BUS_IRQ_REG1] = (1 << rsrc_data->index); + + /* enable ubwc if needed*/ + if (rsrc_data->en_ubwc) { + rc = cam_cpas_get_cpas_hw_version(&camera_hw_version); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to get HW version:%d rc:%d", + camera_hw_version, rc); + return rc; + } + if ((camera_hw_version > CAM_CPAS_TITAN_NONE) && + (camera_hw_version < CAM_CPAS_TITAN_175_V100)) { + struct cam_vfe_bus_ver2_reg_offset_ubwc_client + *ubwc_regs; + + ubwc_regs = + (struct + cam_vfe_bus_ver2_reg_offset_ubwc_client *) + rsrc_data->hw_regs->ubwc_regs; + val = cam_io_r_mb(common_data->mem_base + + ubwc_regs->mode_cfg_0); + val |= 0x1; + cam_io_w_mb(val, common_data->mem_base + + ubwc_regs->mode_cfg_0); + } else if ((camera_hw_version == CAM_CPAS_TITAN_175_V100) || + (camera_hw_version == CAM_CPAS_TITAN_175_V101) || + (camera_hw_version == CAM_CPAS_TITAN_175_V120) || + (camera_hw_version == CAM_CPAS_TITAN_175_V130)) { + struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client + *ubwc_regs; + + ubwc_regs = + (struct + cam_vfe_bus_ver2_reg_offset_ubwc_3_client *) + rsrc_data->hw_regs->ubwc_regs; + val = cam_io_r_mb(common_data->mem_base + + ubwc_regs->mode_cfg_0); + val |= 0x1; + cam_io_w_mb(val, common_data->mem_base + + ubwc_regs->mode_cfg_0); + } else { + CAM_ERR(CAM_ISP, "Invalid HW version: %d", + camera_hw_version); + return -EINVAL; + } + } + + /* Enable WM */ + cam_io_w_mb(rsrc_data->en_cfg, common_data->mem_base + + rsrc_data->hw_regs->cfg); + + CAM_DBG(CAM_ISP, "WM res %d width = %d, height = %d", rsrc_data->index, + rsrc_data->width, rsrc_data->height); + CAM_DBG(CAM_ISP, "WM res %d pk_fmt = %d", rsrc_data->index, + rsrc_data->pack_fmt & PACKER_FMT_MAX); + CAM_DBG(CAM_ISP, "WM res %d stride = %d, burst len = %d", + rsrc_data->index, rsrc_data->stride, 0xf); + CAM_DBG(CAM_ISP, "enable WM res %d offset 0x%x val 0x%x", + rsrc_data->index, (uint32_t) rsrc_data->hw_regs->cfg, + rsrc_data->en_cfg); + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return rc; +} + +static int cam_vfe_bus_stop_wm(struct cam_isp_resource_node *wm_res) +{ + int rc = 0; + struct cam_vfe_bus_ver2_wm_resource_data *rsrc_data = + wm_res->res_priv; + struct cam_vfe_bus_ver2_common_data *common_data = + rsrc_data->common_data; + + /* Disable WM */ + cam_io_w_mb(0x0, + common_data->mem_base + rsrc_data->hw_regs->cfg); + + /* Disable all register access, reply on global reset */ + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + rsrc_data->init_cfg_done = false; + rsrc_data->hfr_cfg_done = false; + + return rc; +} + +static int cam_vfe_bus_handle_wm_done_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + return -EPERM; +} + +static int cam_vfe_bus_handle_wm_done_bottom_half(void *handler_priv, + void *evt_payload_priv) +{ + int rc = CAM_VFE_IRQ_STATUS_ERR; + struct cam_isp_resource_node *wm_res = handler_priv; + struct cam_vfe_bus_irq_evt_payload *evt_payload = evt_payload_priv; + struct cam_vfe_bus_ver2_wm_resource_data *rsrc_data = + (wm_res == NULL) ? NULL : wm_res->res_priv; + uint32_t *cam_ife_irq_regs; + uint32_t status_reg; + + if (!evt_payload || !wm_res || !rsrc_data) + return rc; + + CAM_DBG(CAM_ISP, "addr of evt_payload = %llx core index:0x%x", + (uint64_t)evt_payload, evt_payload->core_index); + CAM_DBG(CAM_ISP, "bus_irq_status_0: = %x", evt_payload->irq_reg_val[0]); + CAM_DBG(CAM_ISP, "bus_irq_status_1: = %x", evt_payload->irq_reg_val[1]); + CAM_DBG(CAM_ISP, "bus_irq_status_2: = %x", evt_payload->irq_reg_val[2]); + CAM_DBG(CAM_ISP, "bus_irq_comp_err: = %x", evt_payload->irq_reg_val[3]); + CAM_DBG(CAM_ISP, "bus_irq_comp_owrt: = %x", + evt_payload->irq_reg_val[4]); + CAM_DBG(CAM_ISP, "bus_irq_dual_comp_err: = %x", + evt_payload->irq_reg_val[5]); + CAM_DBG(CAM_ISP, "bus_irq_dual_comp_owrt: = %x", + evt_payload->irq_reg_val[6]); + + cam_ife_irq_regs = evt_payload->irq_reg_val; + status_reg = cam_ife_irq_regs[CAM_IFE_IRQ_BUS_REG_STATUS1]; + + if (status_reg & BIT(rsrc_data->index)) { + cam_ife_irq_regs[CAM_IFE_IRQ_BUS_REG_STATUS1] &= + ~BIT(rsrc_data->index); + rc = CAM_VFE_IRQ_STATUS_SUCCESS; + evt_payload->evt_id = CAM_ISP_HW_EVENT_DONE; + } + CAM_DBG(CAM_ISP, "status_reg %x rc %d wm_idx %d", + status_reg, rc, rsrc_data->index); + + return rc; +} + + +static int cam_vfe_bus_err_bottom_half(void *handler_priv, + void *evt_payload_priv) +{ + struct cam_vfe_bus_irq_evt_payload *evt_payload = evt_payload_priv; + struct cam_vfe_bus_ver2_priv *bus_priv = handler_priv; + struct cam_vfe_bus_ver2_common_data *common_data; + struct cam_isp_hw_event_info evt_info; + uint32_t val = 0; + + if (!handler_priv || !evt_payload_priv) + return -EINVAL; + + evt_payload = evt_payload_priv; + common_data = &bus_priv->common_data; + + val = evt_payload->debug_status_0; + CAM_ERR(CAM_ISP, "Bus Violation: debug_status_0 = 0x%x", val); + + if (val & 0x01) + CAM_INFO(CAM_ISP, "RDI 0 violation"); + + if (val & 0x02) + CAM_INFO(CAM_ISP, "RDI 1 violation"); + + if (val & 0x04) + CAM_INFO(CAM_ISP, "RDI 2 violation"); + + if (val & 0x08) + CAM_INFO(CAM_ISP, "VID Y 1:1 UBWC violation"); + + if (val & 0x010) + CAM_INFO(CAM_ISP, "VID C 1:1 UBWC violation"); + + if (val & 0x020) + CAM_INFO(CAM_ISP, "VID YC 4:1 violation"); + + if (val & 0x040) + CAM_INFO(CAM_ISP, "VID YC 16:1 violation"); + + if (val & 0x080) + CAM_INFO(CAM_ISP, "FD Y violation"); + + if (val & 0x0100) + CAM_INFO(CAM_ISP, "FD C violation"); + + if (val & 0x0200) + CAM_INFO(CAM_ISP, "RAW DUMP violation"); + + if (val & 0x0400) + CAM_INFO(CAM_ISP, "PDAF violation"); + + if (val & 0x0800) + CAM_INFO(CAM_ISP, "STATs HDR BE violation"); + + if (val & 0x01000) + CAM_INFO(CAM_ISP, "STATs HDR BHIST violation"); + + if (val & 0x02000) + CAM_INFO(CAM_ISP, "STATs TINTLESS BG violation"); + + if (val & 0x04000) + CAM_INFO(CAM_ISP, "STATs BF violation"); + + if (val & 0x08000) + CAM_INFO(CAM_ISP, "STATs AWB BG UBWC violation"); + + if (val & 0x010000) + CAM_INFO(CAM_ISP, "STATs BHIST violation"); + + if (val & 0x020000) + CAM_INFO(CAM_ISP, "STATs RS violation"); + + if (val & 0x040000) + CAM_INFO(CAM_ISP, "STATs CS violation"); + + if (val & 0x080000) + CAM_INFO(CAM_ISP, "STATs IHIST violation"); + + if (val & 0x0100000) + CAM_INFO(CAM_ISP, "DISP Y 1:1 UBWC violation"); + + if (val & 0x0200000) + CAM_INFO(CAM_ISP, "DISP C 1:1 UBWC violation"); + + if (val & 0x0400000) + CAM_INFO(CAM_ISP, "DISP YC 4:1 violation"); + + if (val & 0x0800000) + CAM_INFO(CAM_ISP, "DISP YC 16:1 violation"); + + cam_vfe_bus_put_evt_payload(common_data, &evt_payload); + + evt_info.hw_idx = common_data->core_index; + evt_info.res_type = CAM_ISP_RESOURCE_VFE_OUT; + evt_info.res_id = CAM_VFE_BUS_VER2_VFE_OUT_MAX; + + if (common_data->event_cb) + common_data->event_cb(NULL, CAM_ISP_HW_EVENT_ERROR, + (void *)&evt_info); + + return 0; +} + +static int cam_vfe_bus_init_wm_resource(uint32_t index, + struct cam_vfe_bus_ver2_priv *ver2_bus_priv, + struct cam_vfe_bus_ver2_hw_info *ver2_hw_info, + struct cam_isp_resource_node *wm_res) +{ + struct cam_vfe_bus_ver2_wm_resource_data *rsrc_data; + + rsrc_data = kzalloc(sizeof(struct cam_vfe_bus_ver2_wm_resource_data), + GFP_KERNEL); + if (!rsrc_data) { + CAM_DBG(CAM_ISP, "Failed to alloc for WM res priv"); + return -ENOMEM; + } + wm_res->res_priv = rsrc_data; + + rsrc_data->index = index; + rsrc_data->hw_regs = &ver2_hw_info->bus_client_reg[index]; + rsrc_data->common_data = &ver2_bus_priv->common_data; + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&wm_res->list); + + wm_res->start = NULL; + wm_res->stop = NULL; + wm_res->top_half_handler = cam_vfe_bus_handle_wm_done_top_half; + wm_res->bottom_half_handler = cam_vfe_bus_handle_wm_done_bottom_half; + wm_res->hw_intf = ver2_bus_priv->common_data.hw_intf; + + return 0; +} + +static int cam_vfe_bus_deinit_wm_resource( + struct cam_isp_resource_node *wm_res) +{ + struct cam_vfe_bus_ver2_wm_resource_data *rsrc_data; + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + INIT_LIST_HEAD(&wm_res->list); + + wm_res->start = NULL; + wm_res->stop = NULL; + wm_res->top_half_handler = NULL; + wm_res->bottom_half_handler = NULL; + wm_res->hw_intf = NULL; + + rsrc_data = wm_res->res_priv; + wm_res->res_priv = NULL; + if (!rsrc_data) + return -ENOMEM; + kfree(rsrc_data); + + return 0; +} + +static void cam_vfe_bus_add_wm_to_comp_grp( + struct cam_isp_resource_node *comp_grp, + uint32_t composite_mask) +{ + struct cam_vfe_bus_ver2_comp_grp_data *rsrc_data = comp_grp->res_priv; + + rsrc_data->composite_mask |= composite_mask; +} + +static void cam_vfe_bus_match_comp_grp( + struct cam_vfe_bus_ver2_priv *ver2_bus_priv, + struct cam_isp_resource_node **comp_grp, + uint32_t comp_grp_local_idx, + uint32_t unique_id) +{ + struct cam_vfe_bus_ver2_comp_grp_data *rsrc_data = NULL; + struct cam_isp_resource_node *comp_grp_local = NULL; + + list_for_each_entry(comp_grp_local, + &ver2_bus_priv->used_comp_grp, list) { + rsrc_data = comp_grp_local->res_priv; + if (rsrc_data->comp_grp_local_idx == comp_grp_local_idx && + rsrc_data->unique_id == unique_id) { + /* Match found */ + *comp_grp = comp_grp_local; + return; + } + } + + *comp_grp = NULL; +} + +static int cam_vfe_bus_acquire_comp_grp( + struct cam_vfe_bus_ver2_priv *ver2_bus_priv, + struct cam_isp_out_port_generic_info *out_port_info, + void *tasklet, + uint32_t unique_id, + uint32_t is_dual, + uint32_t is_master, + enum cam_vfe_bus_ver2_vfe_core_id dual_slave_core, + struct cam_isp_resource_node **comp_grp) +{ + int rc = 0; + uint32_t bus_comp_grp_id; + struct cam_isp_resource_node *comp_grp_local = NULL; + struct cam_vfe_bus_ver2_comp_grp_data *rsrc_data = NULL; + + bus_comp_grp_id = cam_vfe_bus_comp_grp_id_convert( + out_port_info->comp_grp_id); + /* Perform match only if there is valid comp grp request */ + if (out_port_info->comp_grp_id != CAM_ISP_RES_COMP_GROUP_NONE) { + /* Check if matching comp_grp already acquired */ + cam_vfe_bus_match_comp_grp(ver2_bus_priv, &comp_grp_local, + bus_comp_grp_id, unique_id); + } + + if (!comp_grp_local) { + /* First find a free group */ + if (is_dual) { + CAM_DBG(CAM_ISP, "Acquire dual comp group"); + if (list_empty(&ver2_bus_priv->free_dual_comp_grp)) { + CAM_ERR(CAM_ISP, "No Free Composite Group"); + return -ENODEV; + } + comp_grp_local = list_first_entry( + &ver2_bus_priv->free_dual_comp_grp, + struct cam_isp_resource_node, list); + rsrc_data = comp_grp_local->res_priv; + rc = cam_vfe_bus_ver2_get_intra_client_mask( + dual_slave_core, + comp_grp_local->hw_intf->hw_idx, + &rsrc_data->intra_client_mask); + if (rc) + return rc; + } else { + CAM_DBG(CAM_ISP, "Acquire comp group"); + if (list_empty(&ver2_bus_priv->free_comp_grp)) { + CAM_ERR(CAM_ISP, "No Free Composite Group"); + return -ENODEV; + } + comp_grp_local = list_first_entry( + &ver2_bus_priv->free_comp_grp, + struct cam_isp_resource_node, list); + rsrc_data = comp_grp_local->res_priv; + } + + list_del(&comp_grp_local->list); + comp_grp_local->tasklet_info = tasklet; + comp_grp_local->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + rsrc_data->is_master = is_master; + rsrc_data->composite_mask = 0; + rsrc_data->unique_id = unique_id; + rsrc_data->comp_grp_local_idx = bus_comp_grp_id; + + if (is_master) + rsrc_data->addr_sync_mode = 0; + else + rsrc_data->addr_sync_mode = 1; + + list_add_tail(&comp_grp_local->list, + &ver2_bus_priv->used_comp_grp); + + } else { + rsrc_data = comp_grp_local->res_priv; + /* Do not support runtime change in composite mask */ + if (comp_grp_local->res_state == + CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_ERR(CAM_ISP, "Invalid State %d Comp Grp %u", + comp_grp_local->res_state, + rsrc_data->comp_grp_type); + return -EBUSY; + } + } + + CAM_DBG(CAM_ISP, "Comp Grp type %u", rsrc_data->comp_grp_type); + + rsrc_data->acquire_dev_cnt++; + *comp_grp = comp_grp_local; + + return rc; +} + +static int cam_vfe_bus_release_comp_grp( + struct cam_vfe_bus_ver2_priv *ver2_bus_priv, + struct cam_isp_resource_node *in_comp_grp) +{ + struct cam_isp_resource_node *comp_grp = NULL; + struct cam_vfe_bus_ver2_comp_grp_data *in_rsrc_data = NULL; + int match_found = 0; + + if (!in_comp_grp) { + CAM_ERR(CAM_ISP, "Invalid Params Comp Grp %pK", in_comp_grp); + return -EINVAL; + } + + if (in_comp_grp->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, "Already released Comp Grp"); + return 0; + } + + if (in_comp_grp->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_ERR(CAM_ISP, "Invalid State %d", + in_comp_grp->res_state); + return -EBUSY; + } + + in_rsrc_data = in_comp_grp->res_priv; + CAM_DBG(CAM_ISP, "Comp Grp type %u", in_rsrc_data->comp_grp_type); + + list_for_each_entry(comp_grp, &ver2_bus_priv->used_comp_grp, list) { + if (comp_grp == in_comp_grp) { + match_found = 1; + break; + } + } + + if (!match_found) { + CAM_ERR(CAM_ISP, "Could not find matching Comp Grp type %u", + in_rsrc_data->comp_grp_type); + return -ENODEV; + } + + in_rsrc_data->acquire_dev_cnt--; + if (in_rsrc_data->acquire_dev_cnt == 0) { + list_del(&comp_grp->list); + + in_rsrc_data->unique_id = 0; + in_rsrc_data->comp_grp_local_idx = CAM_VFE_BUS_COMP_GROUP_NONE; + in_rsrc_data->composite_mask = 0; + in_rsrc_data->dual_slave_core = CAM_VFE_BUS_VER2_VFE_CORE_MAX; + in_rsrc_data->addr_sync_mode = 0; + + comp_grp->tasklet_info = NULL; + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + if (in_rsrc_data->comp_grp_type >= + CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0 && + in_rsrc_data->comp_grp_type <= + CAM_VFE_BUS_VER2_COMP_GRP_DUAL_5) + list_add_tail(&comp_grp->list, + &ver2_bus_priv->free_dual_comp_grp); + else if (in_rsrc_data->comp_grp_type >= + CAM_VFE_BUS_VER2_COMP_GRP_0 && + in_rsrc_data->comp_grp_type <= + CAM_VFE_BUS_VER2_COMP_GRP_5) + list_add_tail(&comp_grp->list, + &ver2_bus_priv->free_comp_grp); + } + + return 0; +} + +static int cam_vfe_bus_start_comp_grp( + struct cam_isp_resource_node *comp_grp, + uint32_t *bus_irq_reg_mask) +{ + int rc = 0; + uint32_t addr_sync_cfg; + struct cam_vfe_bus_ver2_comp_grp_data *rsrc_data = + comp_grp->res_priv; + struct cam_vfe_bus_ver2_common_data *common_data = + rsrc_data->common_data; + + CAM_DBG(CAM_ISP, "comp group id:%d streaming state:%d", + rsrc_data->comp_grp_type, comp_grp->res_state); + + cam_io_w_mb(rsrc_data->composite_mask, common_data->mem_base + + rsrc_data->hw_regs->comp_mask); + if (comp_grp->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + return 0; + + CAM_DBG(CAM_ISP, "composite_mask is 0x%x", rsrc_data->composite_mask); + CAM_DBG(CAM_ISP, "composite_mask addr 0x%x", + rsrc_data->hw_regs->comp_mask); + + if (rsrc_data->comp_grp_type >= CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0 && + rsrc_data->comp_grp_type <= CAM_VFE_BUS_VER2_COMP_GRP_DUAL_5) { + int dual_comp_grp = (rsrc_data->comp_grp_type - + CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0); + + if (rsrc_data->is_master) { + int intra_client_en = cam_io_r_mb( + common_data->mem_base + + common_data->common_reg->dual_master_comp_cfg); + + /* + * 2 Bits per comp_grp. Hence left shift by + * comp_grp * 2 + */ + intra_client_en |= + (rsrc_data->intra_client_mask << + (dual_comp_grp * 2)); + + cam_io_w_mb(intra_client_en, common_data->mem_base + + common_data->common_reg->dual_master_comp_cfg); + + bus_irq_reg_mask[CAM_VFE_BUS_IRQ_REG2] = + (1 << dual_comp_grp); + } + + CAM_DBG(CAM_ISP, "addr_sync_mask addr 0x%x", + rsrc_data->hw_regs->addr_sync_mask); + cam_io_w_mb(rsrc_data->composite_mask, common_data->mem_base + + rsrc_data->hw_regs->addr_sync_mask); + + addr_sync_cfg = cam_io_r_mb(common_data->mem_base + + common_data->common_reg->addr_sync_cfg); + addr_sync_cfg |= (rsrc_data->addr_sync_mode << dual_comp_grp); + /* + * 2 Bits per dual_comp_grp. dual_comp_grp stats at bit number + * 8. Hence left shift cdual_comp_grp dual comp_grp * 2 and + * add 8 + */ + addr_sync_cfg |= + (rsrc_data->intra_client_mask << + ((dual_comp_grp * 2) + + CAM_VFE_BUS_ADDR_SYNC_INTRA_CLIENT_SHIFT)); + cam_io_w_mb(addr_sync_cfg, common_data->mem_base + + common_data->common_reg->addr_sync_cfg); + + common_data->addr_no_sync &= ~(rsrc_data->composite_mask); + cam_io_w_mb(common_data->addr_no_sync, common_data->mem_base + + common_data->common_reg->addr_sync_no_sync); + CAM_DBG(CAM_ISP, "addr_sync_cfg: 0x%x addr_no_sync_cfg: 0x%x", + addr_sync_cfg, common_data->addr_no_sync); + } else { + /* IRQ bits for COMP GRP start at 5. So add 5 to the shift */ + bus_irq_reg_mask[CAM_VFE_BUS_IRQ_REG0] = + (1 << (rsrc_data->comp_grp_type + 5)); + } + + CAM_DBG(CAM_ISP, "VFE start COMP_GRP%d", rsrc_data->comp_grp_type); + + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return rc; +} + +static int cam_vfe_bus_stop_comp_grp(struct cam_isp_resource_node *comp_grp) +{ + int rc = 0; + + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + return rc; +} + +static int cam_vfe_bus_handle_comp_done_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + return -EPERM; +} + +static int cam_vfe_bus_handle_comp_done_bottom_half(void *handler_priv, + void *evt_payload_priv, uint32_t *comp_mask) +{ + int rc = CAM_VFE_IRQ_STATUS_ERR; + struct cam_isp_resource_node *comp_grp = handler_priv; + struct cam_vfe_bus_irq_evt_payload *evt_payload = evt_payload_priv; + struct cam_vfe_bus_ver2_comp_grp_data *rsrc_data = comp_grp->res_priv; + uint32_t *cam_ife_irq_regs; + uint32_t status_reg; + uint32_t comp_err_reg; + uint32_t comp_grp_id; + + CAM_DBG(CAM_ISP, "comp grp type %d", rsrc_data->comp_grp_type); + + if (!evt_payload) + return rc; + + cam_ife_irq_regs = evt_payload->irq_reg_val; + + switch (rsrc_data->comp_grp_type) { + case CAM_VFE_BUS_VER2_COMP_GRP_0: + case CAM_VFE_BUS_VER2_COMP_GRP_1: + case CAM_VFE_BUS_VER2_COMP_GRP_2: + case CAM_VFE_BUS_VER2_COMP_GRP_3: + case CAM_VFE_BUS_VER2_COMP_GRP_4: + case CAM_VFE_BUS_VER2_COMP_GRP_5: + comp_grp_id = (rsrc_data->comp_grp_type - + CAM_VFE_BUS_VER2_COMP_GRP_0); + + /* Check for Regular composite error */ + status_reg = cam_ife_irq_regs[CAM_IFE_IRQ_BUS_REG_STATUS0]; + + comp_err_reg = cam_ife_irq_regs[CAM_IFE_IRQ_BUS_REG_COMP_ERR]; + if ((status_reg & BIT(11)) && + (comp_err_reg & rsrc_data->composite_mask)) { + /* Check for Regular composite error */ + evt_payload->evt_id = CAM_ISP_HW_EVENT_ERROR; + rc = CAM_VFE_IRQ_STATUS_ERR_COMP; + break; + } + + comp_err_reg = cam_ife_irq_regs[CAM_IFE_IRQ_BUS_REG_COMP_OWRT]; + /* Check for Regular composite Overwrite */ + if ((status_reg & BIT(12)) && + (comp_err_reg & rsrc_data->composite_mask)) { + evt_payload->evt_id = CAM_ISP_HW_EVENT_ERROR; + rc = CAM_VFE_IRQ_STATUS_COMP_OWRT; + break; + } + + /* Regular Composite SUCCESS */ + if (status_reg & BIT(comp_grp_id + 5)) { + evt_payload->evt_id = CAM_ISP_HW_EVENT_DONE; + rc = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + CAM_DBG(CAM_ISP, "status reg = 0x%x, bit index = %d rc %d", + status_reg, (comp_grp_id + 5), rc); + break; + + case CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0: + case CAM_VFE_BUS_VER2_COMP_GRP_DUAL_1: + case CAM_VFE_BUS_VER2_COMP_GRP_DUAL_2: + case CAM_VFE_BUS_VER2_COMP_GRP_DUAL_3: + case CAM_VFE_BUS_VER2_COMP_GRP_DUAL_4: + case CAM_VFE_BUS_VER2_COMP_GRP_DUAL_5: + comp_grp_id = (rsrc_data->comp_grp_type - + CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0); + + /* Check for DUAL composite error */ + status_reg = cam_ife_irq_regs[CAM_IFE_IRQ_BUS_REG_STATUS2]; + + comp_err_reg = cam_ife_irq_regs[CAM_IFE_IRQ_BUS_DUAL_COMP_ERR]; + if ((status_reg & BIT(6)) && + (comp_err_reg & rsrc_data->composite_mask)) { + /* Check for DUAL composite error */ + evt_payload->evt_id = CAM_ISP_HW_EVENT_ERROR; + rc = CAM_VFE_IRQ_STATUS_ERR_COMP; + break; + } + + /* Check for Dual composite Overwrite */ + comp_err_reg = cam_ife_irq_regs[CAM_IFE_IRQ_BUS_DUAL_COMP_OWRT]; + if ((status_reg & BIT(7)) && + (comp_err_reg & rsrc_data->composite_mask)) { + evt_payload->evt_id = CAM_ISP_HW_EVENT_ERROR; + rc = CAM_VFE_IRQ_STATUS_COMP_OWRT; + break; + } + + /* DUAL Composite SUCCESS */ + if (status_reg & BIT(comp_grp_id)) { + evt_payload->evt_id = CAM_ISP_HW_EVENT_DONE; + rc = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + break; + default: + rc = CAM_VFE_IRQ_STATUS_ERR; + CAM_ERR(CAM_ISP, "Invalid comp_grp_type %u", + rsrc_data->comp_grp_type); + break; + } + + *comp_mask = rsrc_data->composite_mask; + + return rc; +} + +static int cam_vfe_bus_init_comp_grp(uint32_t index, + struct cam_vfe_bus_ver2_priv *ver2_bus_priv, + struct cam_vfe_bus_ver2_hw_info *ver2_hw_info, + struct cam_isp_resource_node *comp_grp) +{ + struct cam_vfe_bus_ver2_comp_grp_data *rsrc_data = NULL; + + rsrc_data = kzalloc(sizeof(struct cam_vfe_bus_ver2_comp_grp_data), + GFP_KERNEL); + if (!rsrc_data) + return -ENOMEM; + + comp_grp->res_priv = rsrc_data; + + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&comp_grp->list); + + rsrc_data->comp_grp_type = index; + rsrc_data->common_data = &ver2_bus_priv->common_data; + rsrc_data->hw_regs = &ver2_hw_info->comp_grp_reg[index]; + rsrc_data->dual_slave_core = CAM_VFE_BUS_VER2_VFE_CORE_MAX; + + if (rsrc_data->comp_grp_type >= CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0 && + rsrc_data->comp_grp_type <= CAM_VFE_BUS_VER2_COMP_GRP_DUAL_5) + list_add_tail(&comp_grp->list, + &ver2_bus_priv->free_dual_comp_grp); + else if (rsrc_data->comp_grp_type >= CAM_VFE_BUS_VER2_COMP_GRP_0 + && rsrc_data->comp_grp_type <= CAM_VFE_BUS_VER2_COMP_GRP_5) + list_add_tail(&comp_grp->list, &ver2_bus_priv->free_comp_grp); + + comp_grp->start = NULL; + comp_grp->stop = NULL; + comp_grp->top_half_handler = cam_vfe_bus_handle_comp_done_top_half; + comp_grp->bottom_half_handler = NULL; + comp_grp->hw_intf = ver2_bus_priv->common_data.hw_intf; + + return 0; +} + +static int cam_vfe_bus_deinit_comp_grp( + struct cam_isp_resource_node *comp_grp) +{ + struct cam_vfe_bus_ver2_comp_grp_data *rsrc_data = + comp_grp->res_priv; + + comp_grp->start = NULL; + comp_grp->stop = NULL; + comp_grp->top_half_handler = NULL; + comp_grp->bottom_half_handler = NULL; + comp_grp->hw_intf = NULL; + + list_del_init(&comp_grp->list); + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + + comp_grp->res_priv = NULL; + + if (!rsrc_data) { + CAM_ERR(CAM_ISP, "comp_grp_priv is NULL"); + return -ENODEV; + } + kfree(rsrc_data); + + return 0; +} + +static int cam_vfe_bus_get_secure_mode(void *priv, void *cmd_args, + uint32_t arg_size) +{ + + struct cam_isp_hw_get_cmd_update *secure_mode = cmd_args; + struct cam_vfe_bus_ver2_vfe_out_data *rsrc_data; + uint32_t *mode; + + rsrc_data = (struct cam_vfe_bus_ver2_vfe_out_data *) + secure_mode->res->res_priv; + mode = (uint32_t *)secure_mode->data; + *mode = + (rsrc_data->secure_mode == CAM_SECURE_MODE_SECURE) ? + true : false; + + return 0; +} + +static int cam_vfe_bus_acquire_vfe_out(void *bus_priv, void *acquire_args, + uint32_t args_size) +{ + int rc = -ENODEV; + int i; + enum cam_vfe_bus_ver2_vfe_out_type vfe_out_res_id; + uint32_t format; + int num_wm; + uint32_t client_done_mask; + struct cam_vfe_bus_ver2_priv *ver2_bus_priv = bus_priv; + struct cam_vfe_acquire_args *acq_args = acquire_args; + struct cam_vfe_hw_vfe_out_acquire_args *out_acquire_args; + struct cam_isp_resource_node *rsrc_node = NULL; + struct cam_vfe_bus_ver2_vfe_out_data *rsrc_data = NULL; + uint32_t secure_caps = 0, mode; + + if (!bus_priv || !acquire_args) { + CAM_ERR(CAM_ISP, "Invalid Param"); + return -EINVAL; + } + + out_acquire_args = &acq_args->vfe_out; + format = out_acquire_args->out_port_info->format; + + CAM_DBG(CAM_ISP, "Acquiring resource type 0x%x", + out_acquire_args->out_port_info->res_type); + + vfe_out_res_id = cam_vfe_bus_get_out_res_id( + out_acquire_args->out_port_info->res_type); + if (vfe_out_res_id == CAM_VFE_BUS_VER2_VFE_OUT_MAX) + return -ENODEV; + + num_wm = cam_vfe_bus_get_num_wm(vfe_out_res_id, format); + if (num_wm < 1) + return -EINVAL; + + rsrc_node = &ver2_bus_priv->vfe_out[vfe_out_res_id]; + if (rsrc_node->res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, "Resource not available: Res_id %d state:%d", + vfe_out_res_id, rsrc_node->res_state); + return -EBUSY; + } + + rsrc_data = rsrc_node->res_priv; + rsrc_data->common_data->event_cb = acq_args->event_cb; + rsrc_data->priv = acq_args->priv; + + secure_caps = cam_vfe_bus_can_be_secure(rsrc_data->out_type); + mode = out_acquire_args->out_port_info->secure_mode; + mutex_lock(&rsrc_data->common_data->bus_mutex); + if (secure_caps) { + if (!rsrc_data->common_data->num_sec_out) { + rsrc_data->secure_mode = mode; + rsrc_data->common_data->secure_mode = mode; + } else { + if (mode == rsrc_data->common_data->secure_mode) { + rsrc_data->secure_mode = + rsrc_data->common_data->secure_mode; + } else { + rc = -EINVAL; + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Mismatch: Acquire mode[%d], drvr mode[%d]", + rsrc_data->common_data->secure_mode, + mode); + mutex_unlock( + &rsrc_data->common_data->bus_mutex); + return -EINVAL; + } + } + rsrc_data->common_data->num_sec_out++; + } + mutex_unlock(&rsrc_data->common_data->bus_mutex); + + ver2_bus_priv->tasklet_info = acq_args->tasklet; + rsrc_data->num_wm = num_wm; + rsrc_node->res_id = out_acquire_args->out_port_info->res_type; + rsrc_node->tasklet_info = acq_args->tasklet; + rsrc_node->cdm_ops = out_acquire_args->cdm_ops; + rsrc_data->cdm_util_ops = out_acquire_args->cdm_ops; + + /* Reserve Composite Group */ + if (num_wm > 1 || (out_acquire_args->is_dual) || + (out_acquire_args->out_port_info->comp_grp_id > + CAM_ISP_RES_COMP_GROUP_NONE && + out_acquire_args->out_port_info->comp_grp_id < + CAM_ISP_RES_COMP_GROUP_ID_MAX)) { + + rc = cam_vfe_bus_acquire_comp_grp(ver2_bus_priv, + out_acquire_args->out_port_info, + acq_args->tasklet, + out_acquire_args->unique_id, + out_acquire_args->is_dual, + out_acquire_args->is_master, + out_acquire_args->dual_slave_core, + &rsrc_data->comp_grp); + if (rc) { + CAM_ERR(CAM_ISP, + "VFE%d Comp_Grp acquire fail for Out %d rc=%d", + rsrc_data->common_data->core_index, + vfe_out_res_id, rc); + return rc; + } + } + + /* Reserve WM */ + for (i = 0; i < num_wm; i++) { + rc = cam_vfe_bus_acquire_wm(ver2_bus_priv, + out_acquire_args->out_port_info, + acq_args->tasklet, + vfe_out_res_id, + i, + &rsrc_data->wm_res[i], + &client_done_mask, + out_acquire_args->is_dual); + if (rc) { + CAM_ERR(CAM_ISP, + "VFE%d WM acquire failed for Out %d rc=%d", + rsrc_data->common_data->core_index, + vfe_out_res_id, rc); + goto release_wm; + } + + if (rsrc_data->comp_grp) + cam_vfe_bus_add_wm_to_comp_grp(rsrc_data->comp_grp, + client_done_mask); + } + + rsrc_node->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + out_acquire_args->rsrc_node = rsrc_node; + + CAM_DBG(CAM_ISP, "Acquire successful"); + return rc; + +release_wm: + for (i--; i >= 0; i--) + cam_vfe_bus_release_wm(ver2_bus_priv, rsrc_data->wm_res[i]); + + cam_vfe_bus_release_comp_grp(ver2_bus_priv, + rsrc_data->comp_grp); + + return rc; +} + +static int cam_vfe_bus_release_vfe_out(void *bus_priv, void *release_args, + uint32_t args_size) +{ + uint32_t i; + struct cam_isp_resource_node *vfe_out = NULL; + struct cam_vfe_bus_ver2_vfe_out_data *rsrc_data = NULL; + uint32_t secure_caps = 0; + + if (!bus_priv || !release_args) { + CAM_ERR(CAM_ISP, "Invalid input bus_priv %pK release_args %pK", + bus_priv, release_args); + return -EINVAL; + } + + vfe_out = release_args; + rsrc_data = vfe_out->res_priv; + + if (vfe_out->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Invalid resource state:%d", + vfe_out->res_state); + } + + for (i = 0; i < rsrc_data->num_wm; i++) + cam_vfe_bus_release_wm(bus_priv, rsrc_data->wm_res[i]); + rsrc_data->num_wm = 0; + + if (rsrc_data->comp_grp) + cam_vfe_bus_release_comp_grp(bus_priv, rsrc_data->comp_grp); + rsrc_data->comp_grp = NULL; + + vfe_out->tasklet_info = NULL; + vfe_out->cdm_ops = NULL; + rsrc_data->cdm_util_ops = NULL; + + secure_caps = cam_vfe_bus_can_be_secure(rsrc_data->out_type); + mutex_lock(&rsrc_data->common_data->bus_mutex); + if (secure_caps) { + if (rsrc_data->secure_mode == + rsrc_data->common_data->secure_mode) { + rsrc_data->common_data->num_sec_out--; + rsrc_data->secure_mode = + CAM_SECURE_MODE_NON_SECURE; + } else { + /* + * The validity of the mode is properly + * checked while acquiring the output port. + * not expected to reach here, unless there is + * some corruption. + */ + CAM_ERR(CAM_ISP, "driver[%d],resource[%d] mismatch", + rsrc_data->common_data->secure_mode, + rsrc_data->secure_mode); + } + + if (!rsrc_data->common_data->num_sec_out) + rsrc_data->common_data->secure_mode = + CAM_SECURE_MODE_NON_SECURE; + } + mutex_unlock(&rsrc_data->common_data->bus_mutex); + + if (vfe_out->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) + vfe_out->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + return 0; +} + +static int cam_vfe_bus_start_vfe_out( + struct cam_isp_resource_node *vfe_out) +{ + int rc = 0, i; + struct cam_vfe_bus_ver2_vfe_out_data *rsrc_data = NULL; + struct cam_vfe_bus_ver2_common_data *common_data = NULL; + uint32_t bus_irq_reg_mask[CAM_VFE_BUS_IRQ_MAX]; + + if (!vfe_out) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + + rsrc_data = vfe_out->res_priv; + common_data = rsrc_data->common_data; + + CAM_DBG(CAM_ISP, "Start resource index %d", rsrc_data->out_type); + + if (vfe_out->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Invalid resource state:%d", + vfe_out->res_state); + return -EACCES; + } + + memset(bus_irq_reg_mask, 0, sizeof(bus_irq_reg_mask)); + for (i = 0; i < rsrc_data->num_wm; i++) + rc = cam_vfe_bus_start_wm(rsrc_data->wm_res[i], + bus_irq_reg_mask); + + if (rsrc_data->comp_grp) { + memset(bus_irq_reg_mask, 0, sizeof(bus_irq_reg_mask)); + rc = cam_vfe_bus_start_comp_grp(rsrc_data->comp_grp, + bus_irq_reg_mask); + } + + vfe_out->irq_handle = cam_irq_controller_subscribe_irq( + common_data->bus_irq_controller, CAM_IRQ_PRIORITY_1, + bus_irq_reg_mask, vfe_out, vfe_out->top_half_handler, + vfe_out->bottom_half_handler, vfe_out->tasklet_info, + &tasklet_bh_api); + + if (vfe_out->irq_handle < 1) { + CAM_ERR(CAM_ISP, "Subscribe IRQ failed for res_id %d", + vfe_out->res_id); + vfe_out->irq_handle = 0; + return -EFAULT; + } + + vfe_out->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + return rc; +} + +static int cam_vfe_bus_stop_vfe_out( + struct cam_isp_resource_node *vfe_out) +{ + int rc = 0, i; + struct cam_vfe_bus_ver2_vfe_out_data *rsrc_data = NULL; + struct cam_vfe_bus_ver2_common_data *common_data = NULL; + + if (!vfe_out) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + + rsrc_data = vfe_out->res_priv; + common_data = rsrc_data->common_data; + + if (vfe_out->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE || + vfe_out->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_DBG(CAM_ISP, "vfe_out res_state is %d", vfe_out->res_state); + return rc; + } + + if (rsrc_data->comp_grp) + rc = cam_vfe_bus_stop_comp_grp(rsrc_data->comp_grp); + + for (i = 0; i < rsrc_data->num_wm; i++) + rc = cam_vfe_bus_stop_wm(rsrc_data->wm_res[i]); + + if (vfe_out->irq_handle) { + rc = cam_irq_controller_unsubscribe_irq( + common_data->bus_irq_controller, + vfe_out->irq_handle); + vfe_out->irq_handle = 0; + } + + vfe_out->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + return rc; +} + +static int cam_vfe_bus_handle_vfe_out_done_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc; + int i; + struct cam_isp_resource_node *vfe_out = NULL; + struct cam_vfe_bus_ver2_vfe_out_data *rsrc_data = NULL; + struct cam_vfe_bus_irq_evt_payload *evt_payload; + + vfe_out = th_payload->handler_priv; + if (!vfe_out) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No resource"); + return -ENODEV; + } + + rsrc_data = vfe_out->res_priv; + + CAM_DBG(CAM_ISP, "IRQ status_0 = 0x%x", th_payload->evt_status_arr[0]); + CAM_DBG(CAM_ISP, "IRQ status_1 = 0x%x", th_payload->evt_status_arr[1]); + CAM_DBG(CAM_ISP, "IRQ status_2 = 0x%x", th_payload->evt_status_arr[2]); + + rc = cam_vfe_bus_get_evt_payload(rsrc_data->common_data, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "No tasklet_cmd is free in queue"); + CAM_ERR_RATE_LIMIT(CAM_ISP, + "IRQ status_0 = 0x%x status_1 = 0x%x status_2 = 0x%x", + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1], + th_payload->evt_status_arr[2]); + + return rc; + } + + cam_isp_hw_get_timestamp(&evt_payload->ts); + + evt_payload->core_index = rsrc_data->common_data->core_index; + evt_payload->evt_id = evt_id; + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + th_payload->evt_payload_priv = evt_payload; + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +static int cam_vfe_bus_handle_vfe_out_done_bottom_half( + void *handler_priv, + void *evt_payload_priv) +{ + int rc = -EINVAL; + struct cam_isp_resource_node *vfe_out = handler_priv; + struct cam_vfe_bus_ver2_vfe_out_data *rsrc_data = vfe_out->res_priv; + struct cam_isp_hw_event_info evt_info; + void *ctx = NULL; + uint32_t evt_id = 0; + uint32_t comp_mask = 0; + int num_out = 0, i = 0; + struct cam_vfe_bus_irq_evt_payload *evt_payload = + evt_payload_priv; + uint32_t out_list[CAM_VFE_BUS_VER2_VFE_OUT_MAX] = {0}; + + /* + * If this resource has Composite Group then we only handle + * Composite done. We acquire Composite if number of WM > 1. + * So Else case is only one individual buf_done = WM[0]. + */ + if (rsrc_data->comp_grp) { + rc = cam_vfe_bus_handle_comp_done_bottom_half( + rsrc_data->comp_grp, evt_payload_priv, &comp_mask); + } else { + rc = rsrc_data->wm_res[0]->bottom_half_handler( + rsrc_data->wm_res[0], evt_payload_priv); + } + + ctx = rsrc_data->priv; + + switch (rc) { + case CAM_VFE_IRQ_STATUS_SUCCESS: + evt_id = evt_payload->evt_id; + + evt_info.res_type = vfe_out->res_type; + evt_info.hw_idx = vfe_out->hw_intf->hw_idx; + if (rsrc_data->comp_grp) { + cam_vfe_bus_get_comp_vfe_out_res_id_list( + comp_mask, out_list, &num_out); + for (i = 0; i < num_out; i++) { + evt_info.res_id = out_list[i]; + if (rsrc_data->common_data->event_cb) + rsrc_data->common_data->event_cb(ctx, + evt_id, (void *)&evt_info); + } + } else { + evt_info.res_id = vfe_out->res_id; + if (rsrc_data->common_data->event_cb) + rsrc_data->common_data->event_cb(ctx, evt_id, + (void *)&evt_info); + } + break; + default: + break; + } + + cam_vfe_bus_put_evt_payload(rsrc_data->common_data, &evt_payload); + CAM_DBG(CAM_ISP, "vfe_out %d rc %d", rsrc_data->out_type, rc); + + return rc; +} + +static int cam_vfe_bus_init_vfe_out_resource(uint32_t index, + struct cam_vfe_bus_ver2_priv *ver2_bus_priv, + struct cam_vfe_bus_ver2_hw_info *ver2_hw_info) +{ + struct cam_isp_resource_node *vfe_out = NULL; + struct cam_vfe_bus_ver2_vfe_out_data *rsrc_data = NULL; + int rc = 0; + int32_t vfe_out_type = + ver2_hw_info->vfe_out_hw_info[index].vfe_out_type; + + if (vfe_out_type < 0 || + vfe_out_type >= CAM_VFE_BUS_VER2_VFE_OUT_MAX) { + CAM_ERR(CAM_ISP, "Init VFE Out failed, Invalid type=%d", + vfe_out_type); + return -EINVAL; + } + + vfe_out = &ver2_bus_priv->vfe_out[vfe_out_type]; + if (vfe_out->res_state != CAM_ISP_RESOURCE_STATE_UNAVAILABLE || + vfe_out->res_priv) { + CAM_ERR(CAM_ISP, + "Error. Looks like same resource is init again"); + return -EFAULT; + } + + rsrc_data = kzalloc(sizeof(struct cam_vfe_bus_ver2_vfe_out_data), + GFP_KERNEL); + if (!rsrc_data) { + rc = -ENOMEM; + return rc; + } + + vfe_out->res_priv = rsrc_data; + + vfe_out->res_type = CAM_ISP_RESOURCE_VFE_OUT; + vfe_out->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&vfe_out->list); + + rsrc_data->out_type = + ver2_hw_info->vfe_out_hw_info[index].vfe_out_type; + rsrc_data->common_data = &ver2_bus_priv->common_data; + rsrc_data->max_width = + ver2_hw_info->vfe_out_hw_info[index].max_width; + rsrc_data->max_height = + ver2_hw_info->vfe_out_hw_info[index].max_height; + rsrc_data->secure_mode = CAM_SECURE_MODE_NON_SECURE; + + vfe_out->start = cam_vfe_bus_start_vfe_out; + vfe_out->stop = cam_vfe_bus_stop_vfe_out; + vfe_out->top_half_handler = cam_vfe_bus_handle_vfe_out_done_top_half; + vfe_out->bottom_half_handler = + cam_vfe_bus_handle_vfe_out_done_bottom_half; + vfe_out->process_cmd = cam_vfe_bus_process_cmd; + vfe_out->hw_intf = ver2_bus_priv->common_data.hw_intf; + vfe_out->irq_handle = 0; + + return 0; +} + +static int cam_vfe_bus_deinit_vfe_out_resource( + struct cam_isp_resource_node *vfe_out) +{ + struct cam_vfe_bus_ver2_vfe_out_data *rsrc_data = vfe_out->res_priv; + + if (vfe_out->res_state == CAM_ISP_RESOURCE_STATE_UNAVAILABLE) { + /* + * This is not error. It can happen if the resource is + * never supported in the HW. + */ + CAM_DBG(CAM_ISP, "HW%d Res %d already deinitialized"); + return 0; + } + + vfe_out->start = NULL; + vfe_out->stop = NULL; + vfe_out->top_half_handler = NULL; + vfe_out->bottom_half_handler = NULL; + vfe_out->hw_intf = NULL; + vfe_out->irq_handle = 0; + + vfe_out->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + INIT_LIST_HEAD(&vfe_out->list); + vfe_out->res_priv = NULL; + + if (!rsrc_data) + return -ENOMEM; + kfree(rsrc_data); + + return 0; +} + +static int cam_vfe_bus_ver2_handle_irq(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + struct cam_vfe_bus_ver2_priv *bus_priv; + int rc = 0; + + bus_priv = th_payload->handler_priv; + CAM_DBG(CAM_ISP, "Enter"); + rc = cam_irq_controller_handle_irq(evt_id, + bus_priv->common_data.bus_irq_controller); + return (rc == IRQ_HANDLED) ? 0 : -EINVAL; +} + +static int cam_vfe_bus_error_irq_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int i = 0, rc = 0; + struct cam_vfe_bus_ver2_priv *bus_priv = + th_payload->handler_priv; + struct cam_vfe_bus_irq_evt_payload *evt_payload; + + CAM_ERR_RATE_LIMIT(CAM_ISP, "Bus Err IRQ"); + for (i = 0; i < th_payload->num_registers; i++) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "vfe:%d: IRQ_Status%d: 0x%x", + bus_priv->common_data.core_index, i, + th_payload->evt_status_arr[i]); + } + cam_irq_controller_disable_irq(bus_priv->common_data.bus_irq_controller, + bus_priv->error_irq_handle); + + rc = cam_vfe_bus_get_evt_payload(&bus_priv->common_data, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Cannot get payload"); + return rc; + } + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + evt_payload->core_index = bus_priv->common_data.core_index; + evt_payload->evt_id = evt_id; + evt_payload->debug_status_0 = cam_io_r_mb( + bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->debug_status_0); + + th_payload->evt_payload_priv = evt_payload; + + return rc; +} + +static void cam_vfe_bus_update_ubwc_meta_addr( + uint32_t *reg_val_pair, + uint32_t *j, + void *regs, + uint64_t image_buf) +{ + uint32_t camera_hw_version; + struct cam_vfe_bus_ver2_reg_offset_ubwc_client *ubwc_regs; + struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client *ubwc_3_regs; + int rc = 0; + + if (!regs || !reg_val_pair || !j) { + CAM_ERR(CAM_ISP, "Invalid args"); + rc = -EINVAL; + goto end; + } + + rc = cam_cpas_get_cpas_hw_version(&camera_hw_version); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to get HW version rc: %d", rc); + goto end; + } else if ((camera_hw_version < CAM_CPAS_TITAN_170_V100) || + (camera_hw_version > CAM_CPAS_TITAN_175_V130)) { + CAM_ERR(CAM_ISP, "Invalid HW version: %d", + camera_hw_version); + goto end; + } + + switch (camera_hw_version) { + case CAM_CPAS_TITAN_170_V100: + case CAM_CPAS_TITAN_170_V110: + case CAM_CPAS_TITAN_170_V120: + ubwc_regs = + (struct cam_vfe_bus_ver2_reg_offset_ubwc_client *)regs; + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->meta_addr, + image_buf); + break; + case CAM_CPAS_TITAN_175_V100: + case CAM_CPAS_TITAN_175_V101: + case CAM_CPAS_TITAN_175_V120: + case CAM_CPAS_TITAN_175_V130: + ubwc_3_regs = + (struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client *) + regs; + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_3_regs->meta_addr, + image_buf); + break; + default: + break; + } +end: + return; +} + +static int cam_vfe_bus_update_ubwc_3_regs( + struct cam_vfe_bus_ver2_wm_resource_data *wm_data, + uint32_t *reg_val_pair, uint32_t i, uint32_t *j) +{ + struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client *ubwc_regs; + int rc = 0; + + if (!wm_data || !reg_val_pair || !j) { + CAM_ERR(CAM_ISP, "Invalid args"); + rc = -EINVAL; + goto end; + } + + ubwc_regs = (struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client *) + wm_data->hw_regs->ubwc_regs; + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + wm_data->hw_regs->packer_cfg, wm_data->packer_cfg); + CAM_DBG(CAM_ISP, "WM %d packer cfg 0x%x", + wm_data->index, reg_val_pair[*j-1]); + + if (wm_data->is_dual) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->tile_cfg, wm_data->tile_cfg); + } else { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->tile_cfg, wm_data->tile_cfg); + CAM_DBG(CAM_ISP, "WM %d tile cfg 0x%x", + wm_data->index, reg_val_pair[*j-1]); + } + + if (wm_data->is_dual) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->h_init, wm_data->offset); + } else { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->h_init, wm_data->h_init); + CAM_DBG(CAM_ISP, "WM %d h_init 0x%x", + wm_data->index, reg_val_pair[*j-1]); + } + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->v_init, wm_data->v_init); + CAM_DBG(CAM_ISP, "WM %d v_init 0x%x", + wm_data->index, reg_val_pair[*j-1]); + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->meta_stride, wm_data->ubwc_meta_stride); + CAM_DBG(CAM_ISP, "WM %d meta stride 0x%x", + wm_data->index, reg_val_pair[*j-1]); + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->mode_cfg_0, wm_data->ubwc_mode_cfg_0); + CAM_DBG(CAM_ISP, "WM %d ubwc_mode_cfg_0 0x%x", + wm_data->index, reg_val_pair[*j-1]); + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->mode_cfg_1, wm_data->ubwc_mode_cfg_1); + CAM_DBG(CAM_ISP, "WM %d ubwc_mode_cfg_1 0x%x", + wm_data->index, reg_val_pair[*j-1]); + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->meta_offset, wm_data->ubwc_meta_offset); + CAM_DBG(CAM_ISP, "WM %d ubwc meta offset 0x%x", + wm_data->index, reg_val_pair[*j-1]); + + if (wm_data->ubwc_bandwidth_limit) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->bw_limit, wm_data->ubwc_bandwidth_limit); + CAM_DBG(CAM_ISP, "WM %d ubwc bw limit 0x%x", + wm_data->index, wm_data->ubwc_bandwidth_limit); + } + +end: + return rc; +} + +static int cam_vfe_bus_update_ubwc_legacy_regs( + struct cam_vfe_bus_ver2_wm_resource_data *wm_data, + uint32_t camera_hw_version, uint32_t *reg_val_pair, + uint32_t i, uint32_t *j) +{ + struct cam_vfe_bus_ver2_reg_offset_ubwc_client *ubwc_regs; + uint32_t ubwc_bw_limit = 0; + int rc = 0; + + if (!wm_data || !reg_val_pair || !j) { + CAM_ERR(CAM_ISP, "Invalid args"); + rc = -EINVAL; + goto end; + } + + ubwc_regs = (struct cam_vfe_bus_ver2_reg_offset_ubwc_client *) + wm_data->hw_regs->ubwc_regs; + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + wm_data->hw_regs->packer_cfg, wm_data->packer_cfg); + CAM_DBG(CAM_ISP, "WM %d packer cfg 0x%x", + wm_data->index, reg_val_pair[*j-1]); + + if (wm_data->is_dual) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->tile_cfg, wm_data->tile_cfg); + } else { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->tile_cfg, wm_data->tile_cfg); + CAM_DBG(CAM_ISP, "WM %d tile cfg 0x%x", + wm_data->index, reg_val_pair[*j-1]); + } + + if (wm_data->is_dual) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->h_init, wm_data->offset); + } else { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->h_init, wm_data->h_init); + CAM_DBG(CAM_ISP, "WM %d h_init 0x%x", + wm_data->index, reg_val_pair[*j-1]); + } + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->v_init, wm_data->v_init); + CAM_DBG(CAM_ISP, "WM %d v_init 0x%x", + wm_data->index, reg_val_pair[*j-1]); + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->meta_stride, wm_data->ubwc_meta_stride); + CAM_DBG(CAM_ISP, "WM %d meta stride 0x%x", + wm_data->index, reg_val_pair[*j-1]); + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->mode_cfg_0, wm_data->ubwc_mode_cfg_0); + CAM_DBG(CAM_ISP, "WM %d ubwc_mode_cfg_0 0x%x", + wm_data->index, reg_val_pair[*j-1]); + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->meta_offset, wm_data->ubwc_meta_offset); + CAM_DBG(CAM_ISP, "WM %d ubwc meta offset 0x%x", + wm_data->index, reg_val_pair[*j-1]); + + if (camera_hw_version == CAM_CPAS_TITAN_170_V110) { + switch (wm_data->format) { + case CAM_FORMAT_UBWC_TP10: + ubwc_bw_limit = 0x8 | BIT(0); + break; + case CAM_FORMAT_UBWC_NV12_4R: + ubwc_bw_limit = 0xB | BIT(0); + break; + default: + ubwc_bw_limit = 0; + break; + } + } + + if (ubwc_bw_limit) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->bw_limit, ubwc_bw_limit); + CAM_DBG(CAM_ISP, "WM %d ubwc bw limit 0x%x", + wm_data->index, ubwc_bw_limit); + } + +end: + return rc; +} + +static int cam_vfe_bus_update_ubwc_regs( + struct cam_vfe_bus_ver2_wm_resource_data *wm_data, + uint32_t *reg_val_pair, uint32_t i, uint32_t *j) +{ + uint32_t camera_hw_version; + int rc = 0; + + if (!wm_data || !reg_val_pair || !j) { + CAM_ERR(CAM_ISP, "Invalid args"); + rc = -EINVAL; + goto end; + } + + rc = cam_cpas_get_cpas_hw_version(&camera_hw_version); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to get HW version rc: %d", rc); + goto end; + } else if ((camera_hw_version <= CAM_CPAS_TITAN_NONE) || + (camera_hw_version >= CAM_CPAS_TITAN_MAX)) { + CAM_ERR(CAM_ISP, "Invalid HW version: %d", + camera_hw_version); + rc = -EINVAL; + goto end; + } + switch (camera_hw_version) { + case CAM_CPAS_TITAN_170_V100: + case CAM_CPAS_TITAN_170_V110: + case CAM_CPAS_TITAN_170_V120: + rc = cam_vfe_bus_update_ubwc_legacy_regs( + wm_data, camera_hw_version, reg_val_pair, i, j); + break; + case CAM_CPAS_TITAN_175_V100: + case CAM_CPAS_TITAN_175_V101: + case CAM_CPAS_TITAN_175_V120: + case CAM_CPAS_TITAN_175_V130: + rc = cam_vfe_bus_update_ubwc_3_regs( + wm_data, reg_val_pair, i, j); + break; + default: + break; + } + + if (rc) + CAM_ERR(CAM_ISP, "Failed to update ubwc regs rc:%d", rc); + +end: + return rc; +} + +static int cam_vfe_bus_update_wm(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_vfe_bus_ver2_priv *bus_priv; + struct cam_isp_hw_get_cmd_update *update_buf; + struct cam_buf_io_cfg *io_cfg; + struct cam_vfe_bus_ver2_vfe_out_data *vfe_out_data = NULL; + struct cam_vfe_bus_ver2_wm_resource_data *wm_data = NULL; + struct cam_vfe_bus_ver2_reg_offset_ubwc_client *ubwc_client = NULL; + uint32_t *reg_val_pair; + uint32_t i, j, k, size = 0; + uint32_t frame_inc = 0, val; + uint32_t loop_size = 0; + + bus_priv = (struct cam_vfe_bus_ver2_priv *) priv; + update_buf = (struct cam_isp_hw_get_cmd_update *) cmd_args; + + vfe_out_data = (struct cam_vfe_bus_ver2_vfe_out_data *) + update_buf->res->res_priv; + + if (!vfe_out_data || !vfe_out_data->cdm_util_ops) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + if (update_buf->wm_update->num_buf != vfe_out_data->num_wm) { + CAM_ERR(CAM_ISP, + "Failed! Invalid number buffers:%d required:%d", + update_buf->wm_update->num_buf, vfe_out_data->num_wm); + return -EINVAL; + } + + reg_val_pair = &vfe_out_data->common_data->io_buf_update[0]; + io_cfg = update_buf->wm_update->io_cfg; + + for (i = 0, j = 0; i < vfe_out_data->num_wm; i++) { + if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { + CAM_ERR(CAM_ISP, + "reg_val_pair %d exceeds the array limit %zu", + j, MAX_REG_VAL_PAIR_SIZE); + return -ENOMEM; + } + + wm_data = vfe_out_data->wm_res[i]->res_priv; + ubwc_client = wm_data->hw_regs->ubwc_regs; + /* update width register */ + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->buffer_width_cfg, + wm_data->width); + CAM_DBG(CAM_ISP, "WM %d image width 0x%x", + wm_data->index, reg_val_pair[j-1]); + + /* For initial configuration program all bus registers */ + val = io_cfg->planes[i].plane_stride; + CAM_DBG(CAM_ISP, "before stride %d", val); + val = ALIGNUP(val, 16); + if (val != io_cfg->planes[i].plane_stride && + val != wm_data->stride) + CAM_WARN(CAM_ISP, + "Warning stride %u expected %u", + io_cfg->planes[i].plane_stride, + val); + + if ((wm_data->stride != val || + !wm_data->init_cfg_done) && (wm_data->index >= 3)) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->stride, + io_cfg->planes[i].plane_stride); + wm_data->stride = val; + CAM_DBG(CAM_ISP, "WM %d image stride 0x%x", + wm_data->index, reg_val_pair[j-1]); + } + + if (wm_data->en_ubwc) { + if (!wm_data->hw_regs->ubwc_regs) { + CAM_ERR(CAM_ISP, + "No UBWC register to configure."); + return -EINVAL; + } + if (wm_data->ubwc_updated) { + wm_data->ubwc_updated = false; + cam_vfe_bus_update_ubwc_regs( + wm_data, reg_val_pair, i, &j); + } + + /* UBWC meta address */ + cam_vfe_bus_update_ubwc_meta_addr( + reg_val_pair, &j, + wm_data->hw_regs->ubwc_regs, + update_buf->wm_update->image_buf[i]); + CAM_DBG(CAM_ISP, "WM %d ubwc meta addr 0x%llx", + wm_data->index, + update_buf->wm_update->image_buf[i]); + } + + if (wm_data->en_ubwc) { + frame_inc = ALIGNUP(io_cfg->planes[i].plane_stride * + io_cfg->planes[i].slice_height, 4096); + frame_inc += io_cfg->planes[i].meta_size; + CAM_DBG(CAM_ISP, + "WM %d frm %d: ht: %d stride %d meta: %d", + wm_data->index, frame_inc, + io_cfg->planes[i].slice_height, + io_cfg->planes[i].plane_stride, + io_cfg->planes[i].meta_size); + } else { + frame_inc = io_cfg->planes[i].plane_stride * + io_cfg->planes[i].slice_height; + } + + if (wm_data->index < 3) + loop_size = wm_data->irq_subsample_period + 1; + else + loop_size = 1; + + /* WM Image address */ + for (k = 0; k < loop_size; k++) { + if (wm_data->en_ubwc) + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_addr, + update_buf->wm_update->image_buf[i] + + io_cfg->planes[i].meta_size + + k * frame_inc); + else + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_addr, + update_buf->wm_update->image_buf[i] + + wm_data->offset + k * frame_inc); + CAM_DBG(CAM_ISP, "WM %d image address 0x%x", + wm_data->index, reg_val_pair[j-1]); + } + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->frame_inc, frame_inc); + CAM_DBG(CAM_ISP, "WM %d frame_inc %d", + wm_data->index, reg_val_pair[j-1]); + + + /* enable the WM */ + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->cfg, + wm_data->en_cfg); + + /* set initial configuration done */ + if (!wm_data->init_cfg_done) + wm_data->init_cfg_done = true; + } + + size = vfe_out_data->cdm_util_ops->cdm_required_size_reg_random(j/2); + + /* cdm util returns dwords, need to convert to bytes */ + if ((size * 4) > update_buf->cmd.size) { + CAM_ERR(CAM_ISP, + "Failed! Buf size:%d insufficient, expected size:%d", + update_buf->cmd.size, size); + return -ENOMEM; + } + + vfe_out_data->cdm_util_ops->cdm_write_regrandom( + update_buf->cmd.cmd_buf_addr, j/2, reg_val_pair); + + /* cdm util returns dwords, need to convert to bytes */ + update_buf->cmd.used_bytes = size * 4; + + return 0; +} + +static int cam_vfe_bus_update_hfr(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_vfe_bus_ver2_priv *bus_priv; + struct cam_isp_hw_get_cmd_update *update_hfr; + struct cam_vfe_bus_ver2_vfe_out_data *vfe_out_data = NULL; + struct cam_vfe_bus_ver2_wm_resource_data *wm_data = NULL; + struct cam_isp_port_hfr_config *hfr_cfg = NULL; + uint32_t *reg_val_pair; + uint32_t i, j, size = 0; + + bus_priv = (struct cam_vfe_bus_ver2_priv *) priv; + update_hfr = (struct cam_isp_hw_get_cmd_update *) cmd_args; + + vfe_out_data = (struct cam_vfe_bus_ver2_vfe_out_data *) + update_hfr->res->res_priv; + + if (!vfe_out_data || !vfe_out_data->cdm_util_ops) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + reg_val_pair = &vfe_out_data->common_data->io_buf_update[0]; + hfr_cfg = (struct cam_isp_port_hfr_config *)update_hfr->data; + + for (i = 0, j = 0; i < vfe_out_data->num_wm; i++) { + if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { + CAM_ERR(CAM_ISP, + "reg_val_pair %d exceeds the array limit %zu", + j, MAX_REG_VAL_PAIR_SIZE); + return -ENOMEM; + } + + wm_data = vfe_out_data->wm_res[i]->res_priv; + + if (wm_data->index <= 2 && hfr_cfg->subsample_period > 3) { + CAM_ERR(CAM_ISP, + "RDI doesn't support irq subsample period %d", + hfr_cfg->subsample_period); + return -EINVAL; + } + + if ((wm_data->framedrop_pattern != + hfr_cfg->framedrop_pattern) || + !wm_data->hfr_cfg_done) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->framedrop_pattern, + hfr_cfg->framedrop_pattern); + wm_data->framedrop_pattern = hfr_cfg->framedrop_pattern; + CAM_DBG(CAM_ISP, "WM %d framedrop pattern 0x%x", + wm_data->index, wm_data->framedrop_pattern); + } + + if (wm_data->framedrop_period != hfr_cfg->framedrop_period || + !wm_data->hfr_cfg_done) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->framedrop_period, + hfr_cfg->framedrop_period); + wm_data->framedrop_period = hfr_cfg->framedrop_period; + CAM_DBG(CAM_ISP, "WM %d framedrop period 0x%x", + wm_data->index, wm_data->framedrop_period); + } + + if (wm_data->irq_subsample_period != hfr_cfg->subsample_period + || !wm_data->hfr_cfg_done) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->irq_subsample_period, + hfr_cfg->subsample_period); + wm_data->irq_subsample_period = + hfr_cfg->subsample_period; + CAM_DBG(CAM_ISP, "WM %d irq subsample period 0x%x", + wm_data->index, wm_data->irq_subsample_period); + } + + if (wm_data->irq_subsample_pattern != hfr_cfg->subsample_pattern + || !wm_data->hfr_cfg_done) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->irq_subsample_pattern, + hfr_cfg->subsample_pattern); + wm_data->irq_subsample_pattern = + hfr_cfg->subsample_pattern; + CAM_DBG(CAM_ISP, "WM %d irq subsample pattern 0x%x", + wm_data->index, wm_data->irq_subsample_pattern); + } + + /* set initial configuration done */ + if (!wm_data->hfr_cfg_done) + wm_data->hfr_cfg_done = true; + } + + size = vfe_out_data->cdm_util_ops->cdm_required_size_reg_random(j/2); + + /* cdm util returns dwords, need to convert to bytes */ + if ((size * 4) > update_hfr->cmd.size) { + CAM_ERR(CAM_ISP, + "Failed! Buf size:%d insufficient, expected size:%d", + update_hfr->cmd.size, size); + return -ENOMEM; + } + + vfe_out_data->cdm_util_ops->cdm_write_regrandom( + update_hfr->cmd.cmd_buf_addr, j/2, reg_val_pair); + + /* cdm util returns dwords, need to convert to bytes */ + update_hfr->cmd.used_bytes = size * 4; + + return 0; +} + +static int cam_vfe_bus_update_ubwc_config(void *cmd_args) +{ + struct cam_isp_hw_get_cmd_update *update_ubwc; + struct cam_vfe_bus_ver2_vfe_out_data *vfe_out_data = NULL; + struct cam_vfe_bus_ver2_wm_resource_data *wm_data = NULL; + struct cam_ubwc_plane_cfg_v1 *ubwc_plane_cfg = NULL; + uint32_t i; + int rc = 0; + + if (!cmd_args) { + CAM_ERR(CAM_ISP, "Invalid args"); + rc = -EINVAL; + goto end; + } + + update_ubwc = (struct cam_isp_hw_get_cmd_update *) cmd_args; + + vfe_out_data = (struct cam_vfe_bus_ver2_vfe_out_data *) + update_ubwc->res->res_priv; + + if (!vfe_out_data || !vfe_out_data->cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid data"); + rc = -EINVAL; + goto end; + } + + ubwc_plane_cfg = (struct cam_ubwc_plane_cfg_v1 *)update_ubwc->data; + + for (i = 0; i < vfe_out_data->num_wm; i++) { + + wm_data = vfe_out_data->wm_res[i]->res_priv; + if (i > 0) + ubwc_plane_cfg++; + + if (!wm_data->hw_regs->ubwc_regs) { + CAM_ERR(CAM_ISP, + "No UBWC register to configure."); + rc = -EINVAL; + goto end; + } + + if (!wm_data->en_ubwc) { + CAM_ERR(CAM_ISP, "UBWC Disabled"); + rc = -EINVAL; + goto end; + } + + if (wm_data->packer_cfg != + ubwc_plane_cfg->packer_config || + !wm_data->init_cfg_done) { + wm_data->packer_cfg = ubwc_plane_cfg->packer_config; + wm_data->ubwc_updated = true; + } + + if ((!wm_data->is_dual) && ((wm_data->tile_cfg != + ubwc_plane_cfg->tile_config) + || !wm_data->init_cfg_done)) { + wm_data->tile_cfg = ubwc_plane_cfg->tile_config; + wm_data->ubwc_updated = true; + } + + if ((!wm_data->is_dual) && ((wm_data->h_init != + ubwc_plane_cfg->h_init) || + !wm_data->init_cfg_done)) { + wm_data->h_init = ubwc_plane_cfg->h_init; + wm_data->ubwc_updated = true; + } + + if (wm_data->v_init != ubwc_plane_cfg->v_init || + !wm_data->init_cfg_done) { + wm_data->v_init = ubwc_plane_cfg->v_init; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_meta_stride != + ubwc_plane_cfg->meta_stride || + !wm_data->init_cfg_done) { + wm_data->ubwc_meta_stride = ubwc_plane_cfg->meta_stride; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_mode_cfg_0 != + ubwc_plane_cfg->mode_config_0 || + !wm_data->init_cfg_done) { + wm_data->ubwc_mode_cfg_0 = + ubwc_plane_cfg->mode_config_0; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_mode_cfg_1 != + ubwc_plane_cfg->mode_config_1 || + !wm_data->init_cfg_done) { + wm_data->ubwc_mode_cfg_1 = + ubwc_plane_cfg->mode_config_1; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_meta_offset != + ubwc_plane_cfg->meta_offset || + !wm_data->init_cfg_done) { + wm_data->ubwc_meta_offset = ubwc_plane_cfg->meta_offset; + wm_data->ubwc_updated = true; + } + } + +end: + return rc; +} + +static int cam_vfe_bus_update_ubwc_config_v2(void *cmd_args) +{ + struct cam_isp_hw_get_cmd_update *update_ubwc; + struct cam_vfe_bus_ver2_vfe_out_data *vfe_out_data = NULL; + struct cam_vfe_bus_ver2_wm_resource_data *wm_data = NULL; + struct cam_vfe_generic_ubwc_config *ubwc_generic_cfg = NULL; + struct cam_vfe_generic_ubwc_plane_config *ubwc_generic_plane_cfg = NULL; + uint32_t i; + int rc = 0; + + if (!cmd_args) { + CAM_ERR(CAM_ISP, "Invalid args"); + rc = -EINVAL; + goto end; + } + + update_ubwc = (struct cam_isp_hw_get_cmd_update *) cmd_args; + + vfe_out_data = (struct cam_vfe_bus_ver2_vfe_out_data *) + update_ubwc->res->res_priv; + + if (!vfe_out_data || !vfe_out_data->cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid data"); + rc = -EINVAL; + goto end; + } + + ubwc_generic_cfg = (struct cam_vfe_generic_ubwc_config *) + update_ubwc->data; + + for (i = 0; i < vfe_out_data->num_wm; i++) { + + wm_data = vfe_out_data->wm_res[i]->res_priv; + ubwc_generic_plane_cfg = &ubwc_generic_cfg->ubwc_plane_cfg[i]; + + if (!wm_data->hw_regs->ubwc_regs) { + CAM_ERR(CAM_ISP, + "No UBWC register to configure."); + rc = -EINVAL; + goto end; + } + + if (!wm_data->en_ubwc) { + CAM_ERR(CAM_ISP, "UBWC Disabled"); + rc = -EINVAL; + goto end; + } + + if (wm_data->packer_cfg != + ubwc_generic_plane_cfg->packer_config || + !wm_data->init_cfg_done) { + wm_data->packer_cfg = + ubwc_generic_plane_cfg->packer_config; + wm_data->ubwc_updated = true; + } + + if ((!wm_data->is_dual) && ((wm_data->tile_cfg != + ubwc_generic_plane_cfg->tile_config) + || !wm_data->init_cfg_done)) { + wm_data->tile_cfg = ubwc_generic_plane_cfg->tile_config; + wm_data->ubwc_updated = true; + } + + if ((!wm_data->is_dual) && ((wm_data->h_init != + ubwc_generic_plane_cfg->h_init) || + !wm_data->init_cfg_done)) { + wm_data->h_init = ubwc_generic_plane_cfg->h_init; + wm_data->ubwc_updated = true; + } + + if (wm_data->v_init != ubwc_generic_plane_cfg->v_init || + !wm_data->init_cfg_done) { + wm_data->v_init = ubwc_generic_plane_cfg->v_init; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_meta_stride != + ubwc_generic_plane_cfg->meta_stride || + !wm_data->init_cfg_done) { + wm_data->ubwc_meta_stride = + ubwc_generic_plane_cfg->meta_stride; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_mode_cfg_0 != + ubwc_generic_plane_cfg->mode_config_0 || + !wm_data->init_cfg_done) { + wm_data->ubwc_mode_cfg_0 = + ubwc_generic_plane_cfg->mode_config_0; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_mode_cfg_1 != + ubwc_generic_plane_cfg->mode_config_1 || + !wm_data->init_cfg_done) { + wm_data->ubwc_mode_cfg_1 = + ubwc_generic_plane_cfg->mode_config_1; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_meta_offset != + ubwc_generic_plane_cfg->meta_offset || + !wm_data->init_cfg_done) { + wm_data->ubwc_meta_offset = + ubwc_generic_plane_cfg->meta_offset; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_lossy_threshold_0 != + ubwc_generic_plane_cfg->lossy_threshold_0 || + !wm_data->init_cfg_done) { + wm_data->ubwc_lossy_threshold_0 = + ubwc_generic_plane_cfg->lossy_threshold_0; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_lossy_threshold_1 != + ubwc_generic_plane_cfg->lossy_threshold_1 || + !wm_data->init_cfg_done) { + wm_data->ubwc_lossy_threshold_1 = + ubwc_generic_plane_cfg->lossy_threshold_1; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_bandwidth_limit != + ubwc_generic_plane_cfg->bandwidth_limit || + !wm_data->init_cfg_done) { + wm_data->ubwc_bandwidth_limit = + ubwc_generic_plane_cfg->bandwidth_limit; + wm_data->ubwc_updated = true; + } + } + +end: + return rc; +} + + +static int cam_vfe_bus_update_stripe_cfg(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_vfe_bus_ver2_priv *bus_priv; + struct cam_isp_hw_dual_isp_update_args *stripe_args; + struct cam_vfe_bus_ver2_vfe_out_data *vfe_out_data = NULL; + struct cam_vfe_bus_ver2_wm_resource_data *wm_data = NULL; + struct cam_isp_dual_stripe_config *stripe_config; + uint32_t outport_id, ports_plane_idx, i; + + bus_priv = (struct cam_vfe_bus_ver2_priv *) priv; + stripe_args = (struct cam_isp_hw_dual_isp_update_args *)cmd_args; + + vfe_out_data = (struct cam_vfe_bus_ver2_vfe_out_data *) + stripe_args->res->res_priv; + + if (!vfe_out_data) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + outport_id = stripe_args->res->res_id & 0xFF; + if (stripe_args->res->res_id < CAM_ISP_IFE_OUT_RES_BASE || + stripe_args->res->res_id >= CAM_ISP_IFE_OUT_RES_MAX) + return 0; + + ports_plane_idx = (stripe_args->split_id * + (stripe_args->dual_cfg->num_ports * CAM_PACKET_MAX_PLANES)) + + (outport_id * CAM_PACKET_MAX_PLANES); + for (i = 0; i < vfe_out_data->num_wm; i++) { + wm_data = vfe_out_data->wm_res[i]->res_priv; + stripe_config = (struct cam_isp_dual_stripe_config *) + &stripe_args->dual_cfg->stripes[ports_plane_idx + i]; + wm_data->width = stripe_config->width; + wm_data->offset = stripe_config->offset; + wm_data->tile_cfg = stripe_config->tileconfig; + CAM_DBG(CAM_ISP, "id:%x wm:%d width:0x%x offset:%x tilecfg:%x", + stripe_args->res->res_id, i, wm_data->width, + wm_data->offset, wm_data->tile_cfg); + } + + return 0; +} + +static int cam_vfe_bus_start_hw(void *hw_priv, + void *start_hw_args, uint32_t arg_size) +{ + return cam_vfe_bus_start_vfe_out(hw_priv); +} + +static int cam_vfe_bus_stop_hw(void *hw_priv, + void *stop_hw_args, uint32_t arg_size) +{ + return cam_vfe_bus_stop_vfe_out(hw_priv); +} + +static int cam_vfe_bus_init_hw(void *hw_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_vfe_bus_ver2_priv *bus_priv = hw_priv; + uint32_t top_irq_reg_mask[2] = {0}; + + if (!bus_priv) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + if (bus_priv->common_data.hw_init) + return 0; + + top_irq_reg_mask[0] = (1 << 9); + + bus_priv->irq_handle = cam_irq_controller_subscribe_irq( + bus_priv->common_data.vfe_irq_controller, + CAM_IRQ_PRIORITY_2, + top_irq_reg_mask, + bus_priv, + cam_vfe_bus_ver2_handle_irq, + NULL, + NULL, + NULL); + + if (bus_priv->irq_handle < 1) { + CAM_ERR(CAM_ISP, "Failed to subscribe BUS IRQ"); + bus_priv->irq_handle = 0; + return -EFAULT; + } + + if (bus_priv->tasklet_info != NULL) { + bus_priv->error_irq_handle = cam_irq_controller_subscribe_irq( + bus_priv->common_data.bus_irq_controller, + CAM_IRQ_PRIORITY_0, + bus_error_irq_mask, + bus_priv, + cam_vfe_bus_error_irq_top_half, + cam_vfe_bus_err_bottom_half, + bus_priv->tasklet_info, + &tasklet_bh_api); + + if (bus_priv->error_irq_handle < 1) { + CAM_ERR(CAM_ISP, "Failed to subscribe BUS error IRQ %d", + bus_priv->error_irq_handle); + bus_priv->error_irq_handle = 0; + return -EFAULT; + } + } + + /*Set Debug Registers*/ + cam_io_w_mb(CAM_VFE_BUS_SET_DEBUG_REG, bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->debug_status_cfg); + + /* BUS_WR_INPUT_IF_ADDR_SYNC_FRAME_HEADER */ + cam_io_w_mb(0x0, bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->addr_sync_frame_hdr); + + /* no clock gating at bus input */ + cam_io_w_mb(0xFFFFF, bus_priv->common_data.mem_base + 0x0000200C); + + /* BUS_WR_TEST_BUS_CTRL */ + cam_io_w_mb(0x0, bus_priv->common_data.mem_base + 0x0000211C); + + /* if addr_no_sync has default value then config the addr no sync reg */ + cam_io_w_mb(CAM_VFE_BUS_ADDR_NO_SYNC_DEFAULT_VAL, + bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->addr_sync_no_sync); + + bus_priv->common_data.hw_init = true; + + return 0; +} + +static int cam_vfe_bus_deinit_hw(void *hw_priv, + void *deinit_hw_args, uint32_t arg_size) +{ + struct cam_vfe_bus_ver2_priv *bus_priv = hw_priv; + int rc = 0, i; + unsigned long flags; + + if (!bus_priv) { + CAM_ERR(CAM_ISP, "Error: Invalid args"); + return -EINVAL; + } + + if (!bus_priv->common_data.hw_init) + return 0; + + if (bus_priv->error_irq_handle) { + rc = cam_irq_controller_unsubscribe_irq( + bus_priv->common_data.bus_irq_controller, + bus_priv->error_irq_handle); + bus_priv->error_irq_handle = 0; + } + + if (bus_priv->irq_handle) { + rc = cam_irq_controller_unsubscribe_irq( + bus_priv->common_data.vfe_irq_controller, + bus_priv->irq_handle); + bus_priv->irq_handle = 0; + } + + spin_lock_irqsave(&bus_priv->common_data.spin_lock, flags); + INIT_LIST_HEAD(&bus_priv->common_data.free_payload_list); + for (i = 0; i < CAM_VFE_BUS_VER2_PAYLOAD_MAX; i++) { + INIT_LIST_HEAD(&bus_priv->common_data.evt_payload[i].list); + list_add_tail(&bus_priv->common_data.evt_payload[i].list, + &bus_priv->common_data.free_payload_list); + } + bus_priv->common_data.hw_init = false; + spin_unlock_irqrestore(&bus_priv->common_data.spin_lock, flags); + + return rc; +} + +static int __cam_vfe_bus_process_cmd(void *priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + return cam_vfe_bus_process_cmd(priv, cmd_type, cmd_args, arg_size); +} + +static int cam_vfe_bus_process_cmd( + struct cam_isp_resource_node *priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = -EINVAL; + struct cam_vfe_bus_ver2_priv *bus_priv; + + if (!priv || !cmd_args) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_BUF_UPDATE: + rc = cam_vfe_bus_update_wm(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_GET_HFR_UPDATE: + rc = cam_vfe_bus_update_hfr(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_GET_SECURE_MODE: + rc = cam_vfe_bus_get_secure_mode(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_STRIPE_UPDATE: + rc = cam_vfe_bus_update_stripe_cfg(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ: + bus_priv = (struct cam_vfe_bus_ver2_priv *) priv; + if (bus_priv->error_irq_handle) { + CAM_DBG(CAM_ISP, "Mask off bus error irq handler"); + rc = cam_irq_controller_unsubscribe_irq( + bus_priv->common_data.bus_irq_controller, + bus_priv->error_irq_handle); + bus_priv->error_irq_handle = 0; + } + break; + case CAM_ISP_HW_CMD_UBWC_UPDATE: + rc = cam_vfe_bus_update_ubwc_config(cmd_args); + break; + case CAM_ISP_HW_CMD_UBWC_UPDATE_V2: + rc = cam_vfe_bus_update_ubwc_config_v2(cmd_args); + break; + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid camif process command:%d", + cmd_type); + break; + } + + return rc; +} + +int cam_vfe_bus_ver2_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *bus_hw_info, + void *vfe_irq_controller, + struct cam_vfe_bus **vfe_bus) +{ + int i, rc = 0; + struct cam_vfe_bus_ver2_priv *bus_priv = NULL; + struct cam_vfe_bus *vfe_bus_local; + struct cam_vfe_bus_ver2_hw_info *ver2_hw_info = bus_hw_info; + + CAM_DBG(CAM_ISP, "Enter"); + + if (!soc_info || !hw_intf || !bus_hw_info || !vfe_irq_controller) { + CAM_ERR(CAM_ISP, + "Inval_prms soc_info:%pK hw_intf:%pK hw_info%pK", + soc_info, hw_intf, bus_hw_info); + CAM_ERR(CAM_ISP, "controller: %pK", vfe_irq_controller); + rc = -EINVAL; + goto end; + } + + vfe_bus_local = kzalloc(sizeof(struct cam_vfe_bus), GFP_KERNEL); + if (!vfe_bus_local) { + CAM_DBG(CAM_ISP, "Failed to alloc for vfe_bus"); + rc = -ENOMEM; + goto end; + } + + bus_priv = kzalloc(sizeof(struct cam_vfe_bus_ver2_priv), + GFP_KERNEL); + if (!bus_priv) { + CAM_DBG(CAM_ISP, "Failed to alloc for vfe_bus_priv"); + rc = -ENOMEM; + goto free_bus_local; + } + vfe_bus_local->bus_priv = bus_priv; + + bus_priv->num_client = ver2_hw_info->num_client; + bus_priv->num_out = ver2_hw_info->num_out; + bus_priv->common_data.num_sec_out = 0; + bus_priv->common_data.secure_mode = CAM_SECURE_MODE_NON_SECURE; + bus_priv->common_data.core_index = soc_info->index; + bus_priv->common_data.mem_base = + CAM_SOC_GET_REG_MAP_START(soc_info, VFE_CORE_BASE_IDX); + bus_priv->common_data.hw_intf = hw_intf; + bus_priv->common_data.vfe_irq_controller = vfe_irq_controller; + bus_priv->common_data.common_reg = &ver2_hw_info->common_reg; + bus_priv->common_data.addr_no_sync = + CAM_VFE_BUS_ADDR_NO_SYNC_DEFAULT_VAL; + bus_priv->common_data.hw_init = false; + + mutex_init(&bus_priv->common_data.bus_mutex); + + rc = cam_irq_controller_init(drv_name, bus_priv->common_data.mem_base, + &ver2_hw_info->common_reg.irq_reg_info, + &bus_priv->common_data.bus_irq_controller, true); + if (rc) { + CAM_ERR(CAM_ISP, "cam_irq_controller_init failed"); + goto free_bus_priv; + } + + INIT_LIST_HEAD(&bus_priv->free_comp_grp); + INIT_LIST_HEAD(&bus_priv->free_dual_comp_grp); + INIT_LIST_HEAD(&bus_priv->used_comp_grp); + + for (i = 0; i < bus_priv->num_client; i++) { + rc = cam_vfe_bus_init_wm_resource(i, bus_priv, bus_hw_info, + &bus_priv->bus_client[i]); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Init WM failed rc=%d", rc); + goto deinit_wm; + } + } + + for (i = 0; i < CAM_VFE_BUS_VER2_COMP_GRP_MAX; i++) { + rc = cam_vfe_bus_init_comp_grp(i, bus_priv, bus_hw_info, + &bus_priv->comp_grp[i]); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Init Comp Grp failed rc=%d", rc); + goto deinit_comp_grp; + } + } + + for (i = 0; i < bus_priv->num_out; i++) { + rc = cam_vfe_bus_init_vfe_out_resource(i, bus_priv, + bus_hw_info); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Init VFE Out failed rc=%d", rc); + goto deinit_vfe_out; + } + } + + spin_lock_init(&bus_priv->common_data.spin_lock); + INIT_LIST_HEAD(&bus_priv->common_data.free_payload_list); + for (i = 0; i < CAM_VFE_BUS_VER2_PAYLOAD_MAX; i++) { + INIT_LIST_HEAD(&bus_priv->common_data.evt_payload[i].list); + list_add_tail(&bus_priv->common_data.evt_payload[i].list, + &bus_priv->common_data.free_payload_list); + } + + vfe_bus_local->hw_ops.reserve = cam_vfe_bus_acquire_vfe_out; + vfe_bus_local->hw_ops.release = cam_vfe_bus_release_vfe_out; + vfe_bus_local->hw_ops.start = cam_vfe_bus_start_hw; + vfe_bus_local->hw_ops.stop = cam_vfe_bus_stop_hw; + vfe_bus_local->hw_ops.init = cam_vfe_bus_init_hw; + vfe_bus_local->hw_ops.deinit = cam_vfe_bus_deinit_hw; + vfe_bus_local->top_half_handler = cam_vfe_bus_ver2_handle_irq; + vfe_bus_local->bottom_half_handler = NULL; + vfe_bus_local->hw_ops.process_cmd = __cam_vfe_bus_process_cmd; + + *vfe_bus = vfe_bus_local; + + CAM_DBG(CAM_ISP, "Exit"); + return rc; + +deinit_vfe_out: + if (i < 0) + i = CAM_VFE_BUS_VER2_VFE_OUT_MAX; + for (--i; i >= 0; i--) + cam_vfe_bus_deinit_vfe_out_resource(&bus_priv->vfe_out[i]); + +deinit_comp_grp: + if (i < 0) + i = CAM_VFE_BUS_VER2_COMP_GRP_MAX; + for (--i; i >= 0; i--) + cam_vfe_bus_deinit_comp_grp(&bus_priv->comp_grp[i]); + +deinit_wm: + if (i < 0) + i = bus_priv->num_client; + for (--i; i >= 0; i--) + cam_vfe_bus_deinit_wm_resource(&bus_priv->bus_client[i]); + +free_bus_priv: + kfree(vfe_bus_local->bus_priv); + +free_bus_local: + kfree(vfe_bus_local); + +end: + return rc; +} + +int cam_vfe_bus_ver2_deinit( + struct cam_vfe_bus **vfe_bus) +{ + int i, rc = 0; + struct cam_vfe_bus_ver2_priv *bus_priv = NULL; + struct cam_vfe_bus *vfe_bus_local; + unsigned long flags; + + if (!vfe_bus || !*vfe_bus) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + vfe_bus_local = *vfe_bus; + + bus_priv = vfe_bus_local->bus_priv; + if (!bus_priv) { + CAM_ERR(CAM_ISP, "bus_priv is NULL"); + rc = -ENODEV; + goto free_bus_local; + } + + spin_lock_irqsave(&bus_priv->common_data.spin_lock, flags); + INIT_LIST_HEAD(&bus_priv->common_data.free_payload_list); + for (i = 0; i < CAM_VFE_BUS_VER2_PAYLOAD_MAX; i++) + INIT_LIST_HEAD(&bus_priv->common_data.evt_payload[i].list); + bus_priv->common_data.hw_init = false; + spin_unlock_irqrestore(&bus_priv->common_data.spin_lock, flags); + + for (i = 0; i < bus_priv->num_client; i++) { + rc = cam_vfe_bus_deinit_wm_resource(&bus_priv->bus_client[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Deinit WM failed rc=%d", rc); + } + + for (i = 0; i < CAM_VFE_BUS_VER2_COMP_GRP_MAX; i++) { + rc = cam_vfe_bus_deinit_comp_grp(&bus_priv->comp_grp[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Deinit Comp Grp failed rc=%d", rc); + } + + for (i = 0; i < CAM_VFE_BUS_VER2_VFE_OUT_MAX; i++) { + rc = cam_vfe_bus_deinit_vfe_out_resource(&bus_priv->vfe_out[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Deinit VFE Out failed rc=%d", rc); + } + + INIT_LIST_HEAD(&bus_priv->free_comp_grp); + INIT_LIST_HEAD(&bus_priv->free_dual_comp_grp); + INIT_LIST_HEAD(&bus_priv->used_comp_grp); + + rc = cam_irq_controller_deinit( + &bus_priv->common_data.bus_irq_controller); + if (rc) + CAM_ERR(CAM_ISP, + "Deinit IRQ Controller failed rc=%d", rc); + + mutex_destroy(&bus_priv->common_data.bus_mutex); + kfree(vfe_bus_local->bus_priv); + +free_bus_local: + kfree(vfe_bus_local); + + *vfe_bus = NULL; + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.h new file mode 100644 index 0000000000000000000000000000000000000000..cac3adf65a9385165262dee8c16f5829dbb1f459 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.h @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_BUS_VER2_H_ +#define _CAM_VFE_BUS_VER2_H_ + +#include "cam_irq_controller.h" +#include "cam_vfe_bus.h" + +#define CAM_VFE_BUS_VER2_MAX_CLIENTS 24 + +enum cam_vfe_bus_ver2_vfe_core_id { + CAM_VFE_BUS_VER2_VFE_CORE_0, + CAM_VFE_BUS_VER2_VFE_CORE_1, + CAM_VFE_BUS_VER2_VFE_CORE_MAX, +}; + +enum cam_vfe_bus_ver2_comp_grp_type { + CAM_VFE_BUS_VER2_COMP_GRP_0, + CAM_VFE_BUS_VER2_COMP_GRP_1, + CAM_VFE_BUS_VER2_COMP_GRP_2, + CAM_VFE_BUS_VER2_COMP_GRP_3, + CAM_VFE_BUS_VER2_COMP_GRP_4, + CAM_VFE_BUS_VER2_COMP_GRP_5, + CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0, + CAM_VFE_BUS_VER2_COMP_GRP_DUAL_1, + CAM_VFE_BUS_VER2_COMP_GRP_DUAL_2, + CAM_VFE_BUS_VER2_COMP_GRP_DUAL_3, + CAM_VFE_BUS_VER2_COMP_GRP_DUAL_4, + CAM_VFE_BUS_VER2_COMP_GRP_DUAL_5, + CAM_VFE_BUS_VER2_COMP_GRP_MAX, +}; + +enum cam_vfe_bus_ver2_vfe_out_type { + CAM_VFE_BUS_VER2_VFE_OUT_RDI0, + CAM_VFE_BUS_VER2_VFE_OUT_RDI1, + CAM_VFE_BUS_VER2_VFE_OUT_RDI2, + CAM_VFE_BUS_VER2_VFE_OUT_RDI3, + CAM_VFE_BUS_VER2_VFE_OUT_FULL, + CAM_VFE_BUS_VER2_VFE_OUT_DS4, + CAM_VFE_BUS_VER2_VFE_OUT_DS16, + CAM_VFE_BUS_VER2_VFE_OUT_RAW_DUMP, + CAM_VFE_BUS_VER2_VFE_OUT_FD, + CAM_VFE_BUS_VER2_VFE_OUT_PDAF, + CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE, + CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST, + CAM_VFE_BUS_VER2_VFE_OUT_STATS_TL_BG, + CAM_VFE_BUS_VER2_VFE_OUT_STATS_BF, + CAM_VFE_BUS_VER2_VFE_OUT_STATS_AWB_BG, + CAM_VFE_BUS_VER2_VFE_OUT_STATS_BHIST, + CAM_VFE_BUS_VER2_VFE_OUT_STATS_RS, + CAM_VFE_BUS_VER2_VFE_OUT_STATS_CS, + CAM_VFE_BUS_VER2_VFE_OUT_STATS_IHIST, + CAM_VFE_BUS_VER2_VFE_OUT_FULL_DISP, + CAM_VFE_BUS_VER2_VFE_OUT_DS4_DISP, + CAM_VFE_BUS_VER2_VFE_OUT_DS16_DISP, + CAM_VFE_BUS_VER2_VFE_OUT_2PD, + CAM_VFE_BUS_VER2_VFE_OUT_MAX, +}; + +/* + * struct cam_vfe_bus_ver2_reg_offset_common: + * + * @Brief: Common registers across all BUS Clients + */ +struct cam_vfe_bus_ver2_reg_offset_common { + uint32_t hw_version; + uint32_t hw_capability; + uint32_t sw_reset; + uint32_t cgc_ovd; + uint32_t pwr_iso_cfg; + uint32_t dual_master_comp_cfg; + struct cam_irq_controller_reg_info irq_reg_info; + uint32_t comp_error_status; + uint32_t comp_ovrwr_status; + uint32_t dual_comp_error_status; + uint32_t dual_comp_ovrwr_status; + uint32_t addr_sync_cfg; + uint32_t addr_sync_frame_hdr; + uint32_t addr_sync_no_sync; + uint32_t debug_status_cfg; + uint32_t debug_status_0; +}; + +/* + * struct cam_vfe_bus_ver2_reg_offset_ubwc_client: + * + * @Brief: UBWC register offsets for BUS Clients + */ +struct cam_vfe_bus_ver2_reg_offset_ubwc_client { + uint32_t tile_cfg; + uint32_t h_init; + uint32_t v_init; + uint32_t meta_addr; + uint32_t meta_offset; + uint32_t meta_stride; + uint32_t mode_cfg_0; + uint32_t bw_limit; +}; + +/* + * struct cam_vfe_bus_ver2_reg_offset_ubwc_client: + * + * @Brief: UBWC register offsets for BUS Clients + */ +struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client { + uint32_t tile_cfg; + uint32_t h_init; + uint32_t v_init; + uint32_t meta_addr; + uint32_t meta_offset; + uint32_t meta_stride; + uint32_t mode_cfg_0; + uint32_t mode_cfg_1; + uint32_t bw_limit; +}; + + +/* + * struct cam_vfe_bus_ver2_reg_offset_bus_client: + * + * @Brief: Register offsets for BUS Clients + */ +struct cam_vfe_bus_ver2_reg_offset_bus_client { + uint32_t status0; + uint32_t status1; + uint32_t cfg; + uint32_t header_addr; + uint32_t header_cfg; + uint32_t image_addr; + uint32_t image_addr_offset; + uint32_t buffer_width_cfg; + uint32_t buffer_height_cfg; + uint32_t packer_cfg; + uint32_t stride; + uint32_t irq_subsample_period; + uint32_t irq_subsample_pattern; + uint32_t framedrop_period; + uint32_t framedrop_pattern; + uint32_t frame_inc; + uint32_t burst_limit; + void *ubwc_regs; +}; + +/* + * struct cam_vfe_bus_ver2_reg_offset_comp_grp: + * + * @Brief: Register offsets for Composite Group registers + * comp_mask: Comp group register address + * addr_sync_mask:Address sync group register address + */ +struct cam_vfe_bus_ver2_reg_offset_comp_grp { + uint32_t comp_mask; + uint32_t addr_sync_mask; +}; + +/* + * struct cam_vfe_bus_ver2_vfe_out_hw_info: + * + * @Brief: HW capability of VFE Bus Client + */ +struct cam_vfe_bus_ver2_vfe_out_hw_info { + enum cam_vfe_bus_ver2_vfe_out_type vfe_out_type; + uint32_t max_width; + uint32_t max_height; +}; + +/* + * struct cam_vfe_bus_ver2_hw_info: + * + * @Brief: HW register info for entire Bus + * + * @common_reg: Common register details + * @bus_client_reg: Bus client register info + * @comp_reg_grp: Composite group register info + * @vfe_out_hw_info: VFE output capability + */ +struct cam_vfe_bus_ver2_hw_info { + struct cam_vfe_bus_ver2_reg_offset_common common_reg; + uint32_t num_client; + struct cam_vfe_bus_ver2_reg_offset_bus_client + bus_client_reg[CAM_VFE_BUS_VER2_MAX_CLIENTS]; + struct cam_vfe_bus_ver2_reg_offset_comp_grp + comp_grp_reg[CAM_VFE_BUS_VER2_COMP_GRP_MAX]; + uint32_t num_out; + struct cam_vfe_bus_ver2_vfe_out_hw_info + vfe_out_hw_info[CAM_VFE_BUS_VER2_VFE_OUT_MAX]; +}; + +/* + * cam_vfe_bus_ver2_init() + * + * @Brief: Initialize Bus layer + * + * @soc_info: Soc Information for the associated HW + * @hw_intf: HW Interface of HW to which this resource belongs + * @bus_hw_info: BUS HW info that contains details of BUS registers + * @vfe_irq_controller: VFE IRQ Controller to use for subscribing to Top + * level IRQs + * @vfe_bus: Pointer to vfe_bus structure which will be filled + * and returned on successful initialize + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_bus_ver2_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *bus_hw_info, + void *vfe_irq_controller, + struct cam_vfe_bus **vfe_bus); + +/* + * cam_vfe_bus_ver2_deinit() + * + * @Brief: Deinitialize Bus layer + * + * @vfe_bus: Pointer to vfe_bus structure to deinitialize + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_bus_ver2_deinit(struct cam_vfe_bus **vfe_bus); + +#endif /* _CAM_VFE_BUS_VER2_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c new file mode 100644 index 0000000000000000000000000000000000000000..7ad42e8480bdd43d2618d70fe7faff8ba7102a30 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c @@ -0,0 +1,3992 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + + +#include +#include +#include +#include "cam_io_util.h" +#include "cam_debug_util.h" +#include "cam_cdm_util.h" +#include "cam_hw_intf.h" +#include "cam_ife_hw_mgr.h" +#include "cam_vfe_hw_intf.h" +#include "cam_irq_controller.h" +#include "cam_tasklet_util.h" +#include "cam_vfe_bus.h" +#include "cam_vfe_bus_ver3.h" +#include "cam_vfe_core.h" +#include "cam_vfe_soc.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" +#include "cam_trace.h" + +static const char drv_name[] = "vfe_bus"; +static char rup_controller_name[32] = ""; + +#define CAM_VFE_BUS_VER3_IRQ_REG0 0 +#define CAM_VFE_BUS_VER3_IRQ_REG1 1 +#define CAM_VFE_BUS_VER3_IRQ_MAX 2 + +#define CAM_VFE_BUS_VER3_PAYLOAD_MAX 256 + +#define CAM_VFE_RDI_BUS_DEFAULT_WIDTH 0xFFFF +#define CAM_VFE_RDI_BUS_DEFAULT_STRIDE 0xFFFF +#define CAM_VFE_BUS_VER3_INTRA_CLIENT_MASK 0x3 + +#define MAX_BUF_UPDATE_REG_NUM \ + ((sizeof(struct cam_vfe_bus_ver3_reg_offset_bus_client) + \ + sizeof(struct cam_vfe_bus_ver3_reg_offset_ubwc_client))/4) +#define MAX_REG_VAL_PAIR_SIZE \ + (MAX_BUF_UPDATE_REG_NUM * 2 * CAM_PACKET_MAX_PLANES) + +static uint32_t bus_error_irq_mask[2] = { + 0xC0000000, + 0x00000000, +}; + +enum cam_vfe_bus_ver3_packer_format { + PACKER_FMT_VER3_PLAIN_128, + PACKER_FMT_VER3_PLAIN_8, + PACKER_FMT_VER3_PLAIN_8_ODD_EVEN, + PACKER_FMT_VER3_PLAIN_8_LSB_MSB_10, + PACKER_FMT_VER3_PLAIN_8_LSB_MSB_10_ODD_EVEN, + PACKER_FMT_VER3_PLAIN_16_10BPP, + PACKER_FMT_VER3_PLAIN_16_12BPP, + PACKER_FMT_VER3_PLAIN_16_14BPP, + PACKER_FMT_VER3_PLAIN_16_16BPP, + PACKER_FMT_VER3_PLAIN_32, + PACKER_FMT_VER3_PLAIN_64, + PACKER_FMT_VER3_TP_10, + PACKER_FMT_VER3_MAX, +}; + +struct cam_vfe_bus_ver3_common_data { + uint32_t core_index; + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + void *bus_irq_controller; + void *rup_irq_controller; + void *vfe_irq_controller; + struct cam_vfe_bus_ver3_reg_offset_common *common_reg; + uint32_t io_buf_update[ + MAX_REG_VAL_PAIR_SIZE]; + + struct cam_vfe_bus_irq_evt_payload evt_payload[ + CAM_VFE_BUS_VER3_PAYLOAD_MAX]; + struct list_head free_payload_list; + spinlock_t spin_lock; + struct mutex bus_mutex; + uint32_t secure_mode; + uint32_t num_sec_out; + uint32_t addr_no_sync; + uint32_t comp_done_shift; + bool is_lite; + bool hw_init; + cam_hw_mgr_event_cb_func event_cb; + int rup_irq_handle[CAM_VFE_BUS_VER3_SRC_GRP_MAX]; +}; + +struct cam_vfe_bus_ver3_wm_resource_data { + uint32_t index; + struct cam_vfe_bus_ver3_common_data *common_data; + struct cam_vfe_bus_ver3_reg_offset_bus_client *hw_regs; + + bool init_cfg_done; + bool hfr_cfg_done; + + uint32_t offset; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t format; + enum cam_vfe_bus_ver3_packer_format pack_fmt; + + uint32_t burst_len; + + uint32_t en_ubwc; + bool ubwc_updated; + uint32_t packer_cfg; + uint32_t h_init; + uint32_t ubwc_meta_addr; + uint32_t ubwc_meta_cfg; + uint32_t ubwc_mode_cfg; + uint32_t ubwc_stats_ctrl; + uint32_t ubwc_ctrl_2; + + uint32_t irq_subsample_period; + uint32_t irq_subsample_pattern; + uint32_t framedrop_period; + uint32_t framedrop_pattern; + + uint32_t en_cfg; + uint32_t is_dual; + + uint32_t ubwc_lossy_threshold_0; + uint32_t ubwc_lossy_threshold_1; + uint32_t ubwc_offset_lossy_variance; + uint32_t ubwc_bandwidth_limit; +}; + +struct cam_vfe_bus_ver3_comp_grp_data { + enum cam_vfe_bus_ver3_comp_grp_type comp_grp_type; + struct cam_vfe_bus_ver3_common_data *common_data; + + uint32_t is_master; + uint32_t is_dual; + uint32_t dual_slave_core; + uint32_t intra_client_mask; + uint32_t addr_sync_mode; + uint32_t composite_mask; + + uint32_t acquire_dev_cnt; + uint32_t irq_trigger_cnt; + uint32_t ubwc_static_ctrl; +}; + +struct cam_vfe_bus_ver3_vfe_out_data { + uint32_t out_type; + uint32_t source_group; + struct cam_vfe_bus_ver3_common_data *common_data; + + uint32_t num_wm; + struct cam_isp_resource_node *wm_res[PLANE_MAX]; + + struct cam_isp_resource_node *comp_grp; + enum cam_isp_hw_sync_mode dual_comp_sync_mode; + uint32_t dual_hw_alternate_vfe_id; + struct list_head vfe_out_list; + + uint32_t is_master; + uint32_t is_dual; + + uint32_t format; + uint32_t max_width; + uint32_t max_height; + struct cam_cdm_utils_ops *cdm_util_ops; + uint32_t secure_mode; + void *priv; +}; + +struct cam_vfe_bus_ver3_priv { + struct cam_vfe_bus_ver3_common_data common_data; + uint32_t num_client; + uint32_t num_out; + uint32_t top_irq_shift; + + struct cam_isp_resource_node bus_client[CAM_VFE_BUS_VER3_MAX_CLIENTS]; + struct cam_isp_resource_node comp_grp[CAM_VFE_BUS_VER3_COMP_GRP_MAX]; + struct cam_isp_resource_node vfe_out[CAM_VFE_BUS_VER3_VFE_OUT_MAX]; + + struct list_head free_comp_grp; + struct list_head used_comp_grp; + + int bus_irq_handle; + int rup_irq_handle; + int error_irq_handle; + void *tasklet_info; +}; + +static int cam_vfe_bus_ver3_process_cmd( + struct cam_isp_resource_node *priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size); + +static int cam_vfe_bus_ver3_get_evt_payload( + struct cam_vfe_bus_ver3_common_data *common_data, + struct cam_vfe_bus_irq_evt_payload **evt_payload) +{ + int rc; + + spin_lock(&common_data->spin_lock); + + if (!common_data->hw_init) { + *evt_payload = NULL; + CAM_ERR_RATE_LIMIT(CAM_ISP, "VFE:%d Bus uninitialized", + common_data->core_index); + rc = -EPERM; + goto done; + } + + if (list_empty(&common_data->free_payload_list)) { + *evt_payload = NULL; + CAM_ERR_RATE_LIMIT(CAM_ISP, "No free BUS event payload"); + rc = -ENODEV; + goto done; + } + + *evt_payload = list_first_entry(&common_data->free_payload_list, + struct cam_vfe_bus_irq_evt_payload, list); + list_del_init(&(*evt_payload)->list); + rc = 0; +done: + spin_unlock(&common_data->spin_lock); + return rc; +} + +static int cam_vfe_bus_ver3_put_evt_payload( + struct cam_vfe_bus_ver3_common_data *common_data, + struct cam_vfe_bus_irq_evt_payload **evt_payload) +{ + unsigned long flags; + + if (!common_data) { + CAM_ERR(CAM_ISP, "Invalid param common_data NULL"); + return -EINVAL; + } + + if (*evt_payload == NULL) { + CAM_ERR(CAM_ISP, "No payload to put"); + return -EINVAL; + } + + spin_lock_irqsave(&common_data->spin_lock, flags); + if (common_data->hw_init) + list_add_tail(&(*evt_payload)->list, + &common_data->free_payload_list); + spin_unlock_irqrestore(&common_data->spin_lock, flags); + + *evt_payload = NULL; + + CAM_DBG(CAM_ISP, "Done"); + return 0; +} + +static int cam_vfe_bus_ver3_get_intra_client_mask( + enum cam_vfe_bus_ver3_vfe_core_id dual_slave_core, + enum cam_vfe_bus_ver3_vfe_core_id current_core, + uint32_t *intra_client_mask) +{ + int rc = 0; + uint32_t version_based_intra_client_mask = 0x1; + + *intra_client_mask = 0; + + if (dual_slave_core == current_core) { + CAM_ERR(CAM_ISP, + "Invalid params. Same core as Master and Slave"); + return -EINVAL; + } + + switch (current_core) { + case CAM_VFE_BUS_VER3_VFE_CORE_0: + switch (dual_slave_core) { + case CAM_VFE_BUS_VER3_VFE_CORE_1: + *intra_client_mask = version_based_intra_client_mask; + break; + default: + CAM_ERR(CAM_ISP, "Invalid value for slave core %u", + dual_slave_core); + rc = -EINVAL; + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_CORE_1: + switch (dual_slave_core) { + case CAM_VFE_BUS_VER3_VFE_CORE_0: + *intra_client_mask = version_based_intra_client_mask; + break; + default: + CAM_ERR(CAM_ISP, "Invalid value for slave core %u", + dual_slave_core); + rc = -EINVAL; + break; + } + break; + default: + CAM_ERR(CAM_ISP, + "Invalid value for master core %u", current_core); + rc = -EINVAL; + break; + } + + return rc; +} + +static bool cam_vfe_bus_ver3_can_be_secure(uint32_t out_type) +{ + switch (out_type) { + case CAM_VFE_BUS_VER3_VFE_OUT_FULL: + case CAM_VFE_BUS_VER3_VFE_OUT_DS4: + case CAM_VFE_BUS_VER3_VFE_OUT_DS16: + case CAM_VFE_BUS_VER3_VFE_OUT_FD: + case CAM_VFE_BUS_VER3_VFE_OUT_RAW_DUMP: + case CAM_VFE_BUS_VER3_VFE_OUT_RDI0: + case CAM_VFE_BUS_VER3_VFE_OUT_RDI1: + case CAM_VFE_BUS_VER3_VFE_OUT_RDI2: + case CAM_VFE_BUS_VER3_VFE_OUT_FULL_DISP: + case CAM_VFE_BUS_VER3_VFE_OUT_DS4_DISP: + case CAM_VFE_BUS_VER3_VFE_OUT_DS16_DISP: + return true; + + case CAM_VFE_BUS_VER3_VFE_OUT_2PD: + case CAM_VFE_BUS_VER3_VFE_OUT_LCR: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BE: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BHIST: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_TL_BG: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_BF: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_AWB_BG: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_BHIST: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_RS: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_CS: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_IHIST: + default: + return false; + } +} + +static enum cam_vfe_bus_ver3_vfe_out_type + cam_vfe_bus_ver3_get_out_res_id(uint32_t res_type) +{ + switch (res_type) { + case CAM_ISP_IFE_OUT_RES_FULL: + return CAM_VFE_BUS_VER3_VFE_OUT_FULL; + case CAM_ISP_IFE_OUT_RES_DS4: + return CAM_VFE_BUS_VER3_VFE_OUT_DS4; + case CAM_ISP_IFE_OUT_RES_DS16: + return CAM_VFE_BUS_VER3_VFE_OUT_DS16; + case CAM_ISP_IFE_OUT_RES_FD: + return CAM_VFE_BUS_VER3_VFE_OUT_FD; + case CAM_ISP_IFE_OUT_RES_RAW_DUMP: + return CAM_VFE_BUS_VER3_VFE_OUT_RAW_DUMP; + case CAM_ISP_IFE_OUT_RES_2PD: + return CAM_VFE_BUS_VER3_VFE_OUT_2PD; + case CAM_ISP_IFE_OUT_RES_RDI_0: + return CAM_VFE_BUS_VER3_VFE_OUT_RDI0; + case CAM_ISP_IFE_OUT_RES_RDI_1: + return CAM_VFE_BUS_VER3_VFE_OUT_RDI1; + case CAM_ISP_IFE_OUT_RES_RDI_2: + return CAM_VFE_BUS_VER3_VFE_OUT_RDI2; + case CAM_ISP_IFE_OUT_RES_RDI_3: + return CAM_VFE_BUS_VER3_VFE_OUT_RDI3; + case CAM_ISP_IFE_OUT_RES_STATS_HDR_BE: + return CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BE; + case CAM_ISP_IFE_OUT_RES_STATS_HDR_BHIST: + return CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BHIST; + case CAM_ISP_IFE_OUT_RES_STATS_TL_BG: + return CAM_VFE_BUS_VER3_VFE_OUT_STATS_TL_BG; + case CAM_ISP_IFE_OUT_RES_STATS_BF: + return CAM_VFE_BUS_VER3_VFE_OUT_STATS_BF; + case CAM_ISP_IFE_OUT_RES_STATS_AWB_BG: + return CAM_VFE_BUS_VER3_VFE_OUT_STATS_AWB_BG; + case CAM_ISP_IFE_OUT_RES_STATS_BHIST: + return CAM_VFE_BUS_VER3_VFE_OUT_STATS_BHIST; + case CAM_ISP_IFE_OUT_RES_STATS_RS: + return CAM_VFE_BUS_VER3_VFE_OUT_STATS_RS; + case CAM_ISP_IFE_OUT_RES_STATS_CS: + return CAM_VFE_BUS_VER3_VFE_OUT_STATS_CS; + case CAM_ISP_IFE_OUT_RES_STATS_IHIST: + return CAM_VFE_BUS_VER3_VFE_OUT_STATS_IHIST; + case CAM_ISP_IFE_OUT_RES_FULL_DISP: + return CAM_VFE_BUS_VER3_VFE_OUT_FULL_DISP; + case CAM_ISP_IFE_OUT_RES_DS4_DISP: + return CAM_VFE_BUS_VER3_VFE_OUT_DS4_DISP; + case CAM_ISP_IFE_OUT_RES_DS16_DISP: + return CAM_VFE_BUS_VER3_VFE_OUT_DS16_DISP; + case CAM_ISP_IFE_OUT_RES_LCR: + return CAM_VFE_BUS_VER3_VFE_OUT_LCR; + default: + return CAM_VFE_BUS_VER3_VFE_OUT_MAX; + } +} + +static int cam_vfe_bus_ver3_get_num_wm( + enum cam_vfe_bus_ver3_vfe_out_type res_type, + uint32_t format) +{ + switch (res_type) { + case CAM_VFE_BUS_VER3_VFE_OUT_RDI0: + case CAM_VFE_BUS_VER3_VFE_OUT_RDI1: + case CAM_VFE_BUS_VER3_VFE_OUT_RDI2: + case CAM_VFE_BUS_VER3_VFE_OUT_RDI3: + switch (format) { + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_MIPI_RAW_20: + case CAM_FORMAT_DPCM_10_6_10: + case CAM_FORMAT_DPCM_10_8_10: + case CAM_FORMAT_DPCM_12_6_12: + case CAM_FORMAT_DPCM_12_8_12: + case CAM_FORMAT_DPCM_14_8_14: + case CAM_FORMAT_DPCM_14_10_14: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_PLAIN16_16: + case CAM_FORMAT_PLAIN32_20: + case CAM_FORMAT_PLAIN128: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_FULL: + case CAM_VFE_BUS_VER3_VFE_OUT_FULL_DISP: + switch (format) { + case CAM_FORMAT_NV21: + case CAM_FORMAT_NV12: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_TP10: + case CAM_FORMAT_UBWC_NV12: + case CAM_FORMAT_UBWC_NV12_4R: + case CAM_FORMAT_UBWC_TP10: + case CAM_FORMAT_UBWC_P010: + case CAM_FORMAT_PLAIN16_10: + return 2; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_FD: + switch (format) { + case CAM_FORMAT_NV21: + case CAM_FORMAT_NV12: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_TP10: + case CAM_FORMAT_PLAIN16_10: + return 2; + case CAM_FORMAT_Y_ONLY: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_DS4: + case CAM_VFE_BUS_VER3_VFE_OUT_DS4_DISP: + case CAM_VFE_BUS_VER3_VFE_OUT_DS16: + case CAM_VFE_BUS_VER3_VFE_OUT_DS16_DISP: + switch (format) { + case CAM_FORMAT_PD8: + case CAM_FORMAT_PD10: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_RAW_DUMP: + switch (format) { + case CAM_FORMAT_ARGB_14: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_2PD: + switch (format) { + case CAM_FORMAT_PLAIN16_8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_PLAIN16_16: + case CAM_FORMAT_PLAIN64: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BE: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BHIST: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_TL_BG: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_BF: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_AWB_BG: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_BHIST: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_CS: + switch (format) { + case CAM_FORMAT_PLAIN64: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_RS: + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_IHIST: + switch (format) { + case CAM_FORMAT_PLAIN16_16: + return 1; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_LCR: + return 1; + default: + break; + } + + CAM_ERR(CAM_ISP, "Unsupported format %u for out_type:0x%X", + format, res_type); + + return -EINVAL; +} + +static int cam_vfe_bus_ver3_get_wm_idx( + enum cam_vfe_bus_ver3_vfe_out_type vfe_out_res_id, + enum cam_vfe_bus_plane_type plane, + bool is_lite) +{ + int wm_idx = -1; + + switch (vfe_out_res_id) { + case CAM_VFE_BUS_VER3_VFE_OUT_RDI0: + switch (plane) { + case PLANE_Y: + if (is_lite) + wm_idx = 0; + else + wm_idx = 23; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_RDI1: + switch (plane) { + case PLANE_Y: + if (is_lite) + wm_idx = 1; + else + wm_idx = 24; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_RDI2: + switch (plane) { + case PLANE_Y: + if (is_lite) + wm_idx = 2; + else + wm_idx = 25; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_RDI3: + switch (plane) { + case PLANE_Y: + wm_idx = 3; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_FULL: + switch (plane) { + case PLANE_Y: + wm_idx = 0; + break; + case PLANE_C: + wm_idx = 1; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_DS4: + switch (plane) { + case PLANE_Y: + wm_idx = 2; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_DS16: + switch (plane) { + case PLANE_Y: + wm_idx = 3; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_FD: + switch (plane) { + case PLANE_Y: + wm_idx = 8; + break; + case PLANE_C: + wm_idx = 9; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_RAW_DUMP: + switch (plane) { + case PLANE_Y: + wm_idx = 10; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_2PD: + switch (plane) { + case PLANE_Y: + wm_idx = 21; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BE: + switch (plane) { + case PLANE_Y: + wm_idx = 12; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BHIST: + switch (plane) { + case PLANE_Y: + wm_idx = 13; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_TL_BG: + switch (plane) { + case PLANE_Y: + wm_idx = 14; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_BF: + switch (plane) { + case PLANE_Y: + wm_idx = 20; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_AWB_BG: + switch (plane) { + case PLANE_Y: + wm_idx = 15; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_BHIST: + switch (plane) { + case PLANE_Y: + wm_idx = 16; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_RS: + switch (plane) { + case PLANE_Y: + wm_idx = 17; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_CS: + switch (plane) { + case PLANE_Y: + wm_idx = 18; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_STATS_IHIST: + switch (plane) { + case PLANE_Y: + wm_idx = 19; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_FULL_DISP: + switch (plane) { + case PLANE_Y: + wm_idx = 4; + break; + case PLANE_C: + wm_idx = 5; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_DS4_DISP: + switch (plane) { + case PLANE_Y: + wm_idx = 6; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_DS16_DISP: + switch (plane) { + case PLANE_Y: + wm_idx = 7; + break; + default: + break; + } + break; + case CAM_VFE_BUS_VER3_VFE_OUT_LCR: + switch (plane) { + case PLANE_Y: + wm_idx = 22; + break; + default: + break; + } + default: + break; + } + + return wm_idx; +} + +static int cam_vfe_bus_ver3_get_comp_vfe_out_res_id_list( + uint32_t comp_mask, uint32_t *out_list, int *num_out, bool is_lite) +{ + int count = 0; + + if (is_lite) + goto vfe_lite; + + if (comp_mask & 0x3) + out_list[count++] = CAM_ISP_IFE_OUT_RES_FULL; + + if (comp_mask & 0x4) + out_list[count++] = CAM_ISP_IFE_OUT_RES_DS4; + + if (comp_mask & 0x8) + out_list[count++] = CAM_ISP_IFE_OUT_RES_DS16; + + if (comp_mask & 0x30) + out_list[count++] = CAM_ISP_IFE_OUT_RES_FULL_DISP; + + if (comp_mask & 0x40) + out_list[count++] = CAM_ISP_IFE_OUT_RES_DS4_DISP; + + if (comp_mask & 0x80) + out_list[count++] = CAM_ISP_IFE_OUT_RES_DS16_DISP; + + if (comp_mask & 0x300) + out_list[count++] = CAM_ISP_IFE_OUT_RES_FD; + + if (comp_mask & 0x400) + out_list[count++] = CAM_ISP_IFE_OUT_RES_RAW_DUMP; + + if (comp_mask & 0x1000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_HDR_BE; + + if (comp_mask & 0x2000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_HDR_BHIST; + + if (comp_mask & 0x4000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_TL_BG; + + if (comp_mask & 0x8000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_AWB_BG; + + if (comp_mask & 0x10000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_BHIST; + + if (comp_mask & 0x20000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_RS; + + if (comp_mask & 0x40000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_CS; + + if (comp_mask & 0x80000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_IHIST; + + if (comp_mask & 0x100000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_STATS_BF; + + if (comp_mask & 0x200000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_2PD; + + if (comp_mask & 0x400000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_LCR; + + if (comp_mask & 0x800000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_RDI_0; + + if (comp_mask & 0x1000000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_RDI_1; + + if (comp_mask & 0x2000000) + out_list[count++] = CAM_ISP_IFE_OUT_RES_RDI_2; + + *num_out = count; + return 0; + +vfe_lite: + if (comp_mask & 0x1) + out_list[count++] = CAM_ISP_IFE_OUT_RES_RDI_0; + + if (comp_mask & 0x2) + out_list[count++] = CAM_ISP_IFE_OUT_RES_RDI_1; + + if (comp_mask & 0x4) + out_list[count++] = CAM_ISP_IFE_OUT_RES_RDI_2; + + if (comp_mask & 0x8) + out_list[count++] = CAM_ISP_IFE_OUT_RES_RDI_3; + + *num_out = count; + return 0; +} + +static enum cam_vfe_bus_ver3_packer_format + cam_vfe_bus_ver3_get_packer_fmt(uint32_t out_fmt, int wm_index) +{ + switch (out_fmt) { + case CAM_FORMAT_MIPI_RAW_6: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_MIPI_RAW_20: + case CAM_FORMAT_PLAIN16_8: + case CAM_FORMAT_PLAIN128: + case CAM_FORMAT_PD8: + return PACKER_FMT_VER3_PLAIN_128; + case CAM_FORMAT_PLAIN8: + return PACKER_FMT_VER3_PLAIN_8; + case CAM_FORMAT_NV21: + if ((wm_index == 1) || (wm_index == 3) || (wm_index == 5)) + return PACKER_FMT_VER3_PLAIN_8_LSB_MSB_10_ODD_EVEN; + case CAM_FORMAT_NV12: + case CAM_FORMAT_UBWC_NV12: + case CAM_FORMAT_UBWC_NV12_4R: + case CAM_FORMAT_Y_ONLY: + return PACKER_FMT_VER3_PLAIN_8_LSB_MSB_10; + case CAM_FORMAT_PLAIN16_10: + return PACKER_FMT_VER3_PLAIN_16_10BPP; + case CAM_FORMAT_PLAIN16_12: + return PACKER_FMT_VER3_PLAIN_16_12BPP; + case CAM_FORMAT_PLAIN16_14: + return PACKER_FMT_VER3_PLAIN_16_14BPP; + case CAM_FORMAT_PLAIN16_16: + return PACKER_FMT_VER3_PLAIN_16_16BPP; + case CAM_FORMAT_PLAIN32: + case CAM_FORMAT_ARGB: + return PACKER_FMT_VER3_PLAIN_32; + case CAM_FORMAT_PLAIN64: + case CAM_FORMAT_ARGB_16: + case CAM_FORMAT_PD10: + return PACKER_FMT_VER3_PLAIN_64; + case CAM_FORMAT_UBWC_TP10: + case CAM_FORMAT_TP10: + return PACKER_FMT_VER3_TP_10; + default: + return PACKER_FMT_VER3_MAX; + } +} + +static int cam_vfe_bus_ver3_handle_rup_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc; + int i; + struct cam_isp_resource_node *vfe_out = NULL; + struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data = NULL; + struct cam_vfe_bus_irq_evt_payload *evt_payload; + uint32_t irq_status; + + vfe_out = th_payload->handler_priv; + if (!vfe_out) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No resource"); + return -ENODEV; + } + + rsrc_data = vfe_out->res_priv; + + CAM_DBG(CAM_ISP, "VFE:%d Bus IRQ status_0: 0x%X", + rsrc_data->common_data->core_index, + th_payload->evt_status_arr[0]); + + rc = cam_vfe_bus_ver3_get_evt_payload(rsrc_data->common_data, + &evt_payload); + + if (rc) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "VFE:%d Bus IRQ status_0: 0x%X", + rsrc_data->common_data->core_index, + th_payload->evt_status_arr[0]); + return rc; + } + + evt_payload->core_index = rsrc_data->common_data->core_index; + evt_payload->evt_id = evt_id; + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + irq_status = + th_payload->evt_status_arr[CAM_IFE_IRQ_BUS_VER3_REG_STATUS0]; + + trace_cam_log_event("RUP", "RUP_IRQ", irq_status, 0); + + th_payload->evt_payload_priv = evt_payload; + + return rc; +} + +static int cam_vfe_bus_ver3_handle_rup_bottom_half(void *handler_priv, + void *evt_payload_priv) +{ + int ret = CAM_VFE_IRQ_STATUS_ERR; + struct cam_vfe_bus_irq_evt_payload *payload; + struct cam_isp_resource_node *vfe_out = NULL; + struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data = NULL; + struct cam_isp_hw_event_info evt_info; + uint32_t irq_status; + + if (!handler_priv || !evt_payload_priv) { + CAM_ERR(CAM_ISP, "Invalid params"); + return ret; + } + + payload = evt_payload_priv; + vfe_out = handler_priv; + rsrc_data = vfe_out->res_priv; + + if (!rsrc_data->common_data->event_cb) { + CAM_ERR(CAM_ISP, "Callback to HW MGR not found"); + return ret; + } + + irq_status = payload->irq_reg_val[CAM_IFE_IRQ_BUS_VER3_REG_STATUS0]; + + evt_info.hw_idx = rsrc_data->common_data->core_index; + evt_info.res_type = CAM_ISP_RESOURCE_VFE_IN; + + if (!rsrc_data->common_data->is_lite) { + if (irq_status & 0x1) { + CAM_DBG(CAM_ISP, "VFE:%d Received CAMIF RUP", + evt_info.hw_idx); + evt_info.res_id = CAM_ISP_HW_VFE_IN_CAMIF; + rsrc_data->common_data->event_cb( + rsrc_data->priv, CAM_ISP_HW_EVENT_REG_UPDATE, + (void *)&evt_info); + } + + if (irq_status & 0x2) { + CAM_DBG(CAM_ISP, "VFE:%d Received PDLIB RUP", + evt_info.hw_idx); + evt_info.res_id = CAM_ISP_HW_VFE_IN_PDLIB; + rsrc_data->common_data->event_cb( + rsrc_data->priv, CAM_ISP_HW_EVENT_REG_UPDATE, + (void *)&evt_info); + } + + if (irq_status & 0x4) + CAM_DBG(CAM_ISP, "VFE:%d Received LCR RUP", + evt_info.hw_idx); + + if (irq_status & 0x8) { + CAM_DBG(CAM_ISP, "VFE:%d Received RDI0 RUP", + evt_info.hw_idx); + evt_info.res_id = CAM_ISP_HW_VFE_IN_RDI0; + rsrc_data->common_data->event_cb( + rsrc_data->priv, CAM_ISP_HW_EVENT_REG_UPDATE, + (void *)&evt_info); + } + + if (irq_status & 0x10) { + CAM_DBG(CAM_ISP, "VFE:%d Received RDI1 RUP", + evt_info.hw_idx); + evt_info.res_id = CAM_ISP_HW_VFE_IN_RDI1; + rsrc_data->common_data->event_cb( + rsrc_data->priv, CAM_ISP_HW_EVENT_REG_UPDATE, + (void *)&evt_info); + } + + if (irq_status & 0x20) { + CAM_DBG(CAM_ISP, "VFE:%d Received RDI2 RUP", + evt_info.hw_idx); + evt_info.res_id = CAM_ISP_HW_VFE_IN_RDI2; + rsrc_data->common_data->event_cb( + rsrc_data->priv, CAM_ISP_HW_EVENT_REG_UPDATE, + (void *)&evt_info); + } + } else { + if (irq_status & 0x1) { + CAM_DBG(CAM_ISP, "VFE:%d Received RDI0 RUP", + evt_info.hw_idx); + evt_info.res_id = CAM_ISP_HW_VFE_IN_RDI0; + rsrc_data->common_data->event_cb( + rsrc_data->priv, CAM_ISP_HW_EVENT_REG_UPDATE, + (void *)&evt_info); + } + + if (irq_status & 0x2) { + CAM_DBG(CAM_ISP, "VFE:%d Received RDI1 RUP", + evt_info.hw_idx); + evt_info.res_id = CAM_ISP_HW_VFE_IN_RDI1; + rsrc_data->common_data->event_cb( + rsrc_data->priv, CAM_ISP_HW_EVENT_REG_UPDATE, + (void *)&evt_info); + } + + if (irq_status & 0x4) { + CAM_DBG(CAM_ISP, "VFE:%d Received RDI2 RUP", + evt_info.hw_idx); + evt_info.res_id = CAM_ISP_HW_VFE_IN_RDI2; + rsrc_data->common_data->event_cb( + rsrc_data->priv, CAM_ISP_HW_EVENT_REG_UPDATE, + (void *)&evt_info); + } + + if (irq_status & 0x8) { + CAM_DBG(CAM_ISP, "VFE:%d Received RDI3 RUP", + evt_info.hw_idx); + evt_info.res_id = CAM_ISP_HW_VFE_IN_RDI3; + rsrc_data->common_data->event_cb( + rsrc_data->priv, CAM_ISP_HW_EVENT_REG_UPDATE, + (void *)&evt_info); + } + } + + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + + CAM_DBG(CAM_ISP, + "VFE:%d Bus RUP IRQ status_0:0x%X rc:%d", + evt_info.hw_idx, CAM_ISP_HW_EVENT_REG_UPDATE, irq_status, ret); + + cam_vfe_bus_ver3_put_evt_payload(rsrc_data->common_data, &payload); + + return ret; +} + +static int cam_vfe_bus_ver3_acquire_wm( + struct cam_vfe_bus_ver3_priv *ver3_bus_priv, + struct cam_isp_out_port_generic_info *out_port_info, + void *tasklet, + enum cam_vfe_bus_ver3_vfe_out_type vfe_out_res_id, + enum cam_vfe_bus_plane_type plane, + struct cam_isp_resource_node **wm_res, + uint32_t *client_done_mask, + uint32_t is_dual, + enum cam_vfe_bus_ver3_comp_grp_type *comp_grp_id) +{ + int32_t wm_idx = 0; + struct cam_isp_resource_node *wm_res_local = NULL; + struct cam_vfe_bus_ver3_wm_resource_data *rsrc_data = NULL; + + *wm_res = NULL; + + /* VFE OUT to WM is fixed. */ + wm_idx = cam_vfe_bus_ver3_get_wm_idx(vfe_out_res_id, plane, + ver3_bus_priv->common_data.is_lite); + if (wm_idx < 0 || wm_idx >= ver3_bus_priv->num_client || + plane > PLANE_C) { + CAM_ERR(CAM_ISP, + "Unsupported VFE out_type:0x%X plane:%d wm_idx:%d max_idx:%d", + vfe_out_res_id, plane, wm_idx, + ver3_bus_priv->num_client - 1); + return -EINVAL; + } + + wm_res_local = &ver3_bus_priv->bus_client[wm_idx]; + if (wm_res_local->res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, "WM:%d not available state:%d", + wm_idx, wm_res_local->res_state); + return -EALREADY; + } + wm_res_local->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + wm_res_local->tasklet_info = tasklet; + + rsrc_data = wm_res_local->res_priv; + rsrc_data->format = out_port_info->format; + rsrc_data->pack_fmt = cam_vfe_bus_ver3_get_packer_fmt(rsrc_data->format, + wm_idx); + + rsrc_data->width = out_port_info->width; + rsrc_data->height = out_port_info->height; + rsrc_data->is_dual = is_dual; + /* Set WM offset value to default */ + rsrc_data->offset = 0; + CAM_DBG(CAM_ISP, "WM:%d width %d height %d", rsrc_data->index, + rsrc_data->width, rsrc_data->height); + + if (ver3_bus_priv->common_data.is_lite || (rsrc_data->index > 22)) { + rsrc_data->pack_fmt = 0x0; + /* WM 23-25 refers to RDI 0/ RDI 1/RDI 2 */ + switch (rsrc_data->format) { + case CAM_FORMAT_MIPI_RAW_6: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_MIPI_RAW_20: + case CAM_FORMAT_PLAIN128: + case CAM_FORMAT_PLAIN32_20: + rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + break; + case CAM_FORMAT_PLAIN8: + rsrc_data->en_cfg = 0x1; + rsrc_data->stride = rsrc_data->width * 2; + break; + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_PLAIN16_16: + rsrc_data->width = + ALIGNUP(rsrc_data->width * 2, 16) / 16; + rsrc_data->en_cfg = 0x1; + break; + case CAM_FORMAT_PLAIN64: + rsrc_data->width = + ALIGNUP(rsrc_data->width * 8, 16) / 16; + rsrc_data->en_cfg = 0x1; + break; + default: + CAM_ERR(CAM_ISP, "Unsupported RDI format %d", + rsrc_data->format); + return -EINVAL; + } + } else if ((rsrc_data->index < 2) || + (rsrc_data->index == 8) || (rsrc_data->index == 9) || + (rsrc_data->index == 4) || (rsrc_data->index == 5)) { + /* + * WM 0-1 FULL_OUT, WM 8-9 FD_OUT, + * WM 4-5 FULL_DISP + */ + switch (rsrc_data->format) { + case CAM_FORMAT_UBWC_NV12_4R: + rsrc_data->en_ubwc = 1; + switch (plane) { + case PLANE_C: + rsrc_data->height /= 2; + break; + case PLANE_Y: + break; + default: + CAM_ERR(CAM_ISP, "Invalid plane %d", plane); + return -EINVAL; + } + break; + case CAM_FORMAT_UBWC_NV12: + rsrc_data->en_ubwc = 1; + /* Fall through for NV12 */ + case CAM_FORMAT_NV21: + case CAM_FORMAT_NV12: + case CAM_FORMAT_Y_ONLY: + switch (plane) { + case PLANE_C: + rsrc_data->height /= 2; + break; + case PLANE_Y: + break; + default: + CAM_ERR(CAM_ISP, "Invalid plane %d", plane); + return -EINVAL; + } + break; + case CAM_FORMAT_UBWC_TP10: + rsrc_data->en_ubwc = 1; + switch (plane) { + case PLANE_C: + rsrc_data->height /= 2; + break; + case PLANE_Y: + break; + default: + CAM_ERR(CAM_ISP, "Invalid plane %d", plane); + return -EINVAL; + } + break; + case CAM_FORMAT_TP10: + switch (plane) { + case PLANE_C: + rsrc_data->height /= 2; + break; + case PLANE_Y: + break; + default: + CAM_ERR(CAM_ISP, "Invalid plane %d", plane); + return -EINVAL; + } + break; + case CAM_FORMAT_PLAIN16_10: + switch (plane) { + case PLANE_C: + rsrc_data->height /= 2; + break; + case PLANE_Y: + break; + default: + CAM_ERR(CAM_ISP, "Invalid plane %d", plane); + return -EINVAL; + } + break; + default: + CAM_ERR(CAM_ISP, "Invalid format %d", + rsrc_data->format); + return -EINVAL; + } + rsrc_data->en_cfg = 0x1; + } else if (rsrc_data->index == 20) { + /* WM 20 stats BAF */ + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } else if (rsrc_data->index > 11 && rsrc_data->index < 20) { + /* WM 12-19 stats */ + rsrc_data->width = 0; + rsrc_data->height = 0; + rsrc_data->stride = 1; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } else if (rsrc_data->index == 21) { + /* WM 21 PD */ + rsrc_data->width = 0; + rsrc_data->height = 0; + rsrc_data->stride = 1; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } else if (rsrc_data->index == 10) { + /* WM 10 Raw dump */ + rsrc_data->stride = rsrc_data->width; + rsrc_data->en_cfg = 0x1; + /* LSB aligned */ + rsrc_data->pack_fmt |= 0x10; + } else if (rsrc_data->index == 22) { + switch (rsrc_data->format) { + case CAM_FORMAT_PLAIN16_16: + rsrc_data->stride = ALIGNUP(rsrc_data->width * 2, 8); + rsrc_data->en_cfg = 0x1; + /* LSB aligned */ + rsrc_data->pack_fmt |= 0x10; + break; + default: + CAM_ERR(CAM_ISP, "Invalid format %d", + rsrc_data->format); + return -EINVAL; + } + } else if ((rsrc_data->index == 2) || (rsrc_data->index == 3) || + (rsrc_data->index == 6) || (rsrc_data->index == 7)) { + /* Write master 2-3 and 6-7 DS ports */ + + rsrc_data->height = rsrc_data->height / 2; + rsrc_data->width = rsrc_data->width / 2; + rsrc_data->en_cfg = 0x1; + + } else { + CAM_ERR(CAM_ISP, "Invalid WM:%d requested", rsrc_data->index); + return -EINVAL; + } + + *wm_res = wm_res_local; + *comp_grp_id = rsrc_data->hw_regs->comp_group; + *client_done_mask |= (1 << wm_idx); + + CAM_DBG(CAM_ISP, + "VFE:%d WM:%d processed width:%d height:%d format:0x%X en_ubwc:%d", + rsrc_data->common_data->core_index, rsrc_data->index, + rsrc_data->width, rsrc_data->height, rsrc_data->format, + rsrc_data->en_ubwc); + return 0; +} + +static int cam_vfe_bus_ver3_release_wm(void *bus_priv, + struct cam_isp_resource_node *wm_res) +{ + struct cam_vfe_bus_ver3_wm_resource_data *rsrc_data = + wm_res->res_priv; + + rsrc_data->offset = 0; + rsrc_data->width = 0; + rsrc_data->height = 0; + rsrc_data->stride = 0; + rsrc_data->format = 0; + rsrc_data->pack_fmt = 0; + rsrc_data->burst_len = 0; + rsrc_data->irq_subsample_period = 0; + rsrc_data->irq_subsample_pattern = 0; + rsrc_data->framedrop_period = 0; + rsrc_data->framedrop_pattern = 0; + rsrc_data->packer_cfg = 0; + rsrc_data->en_ubwc = 0; + rsrc_data->h_init = 0; + rsrc_data->ubwc_meta_addr = 0; + rsrc_data->ubwc_meta_cfg = 0; + rsrc_data->ubwc_mode_cfg = 0; + rsrc_data->ubwc_stats_ctrl = 0; + rsrc_data->ubwc_ctrl_2 = 0; + rsrc_data->init_cfg_done = false; + rsrc_data->hfr_cfg_done = false; + rsrc_data->ubwc_updated = false; + rsrc_data->en_cfg = 0; + rsrc_data->is_dual = 0; + + rsrc_data->ubwc_lossy_threshold_0 = 0; + rsrc_data->ubwc_lossy_threshold_1 = 0; + rsrc_data->ubwc_offset_lossy_variance = 0; + rsrc_data->ubwc_bandwidth_limit = 0; + wm_res->tasklet_info = NULL; + wm_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + CAM_DBG(CAM_ISP, "VFE:%d Release WM:%d", + rsrc_data->common_data->core_index, rsrc_data->index); + + return 0; +} + +static int cam_vfe_bus_ver3_start_wm(struct cam_isp_resource_node *wm_res) +{ + int val = 0; + struct cam_vfe_bus_ver3_wm_resource_data *rsrc_data = + wm_res->res_priv; + struct cam_vfe_bus_ver3_common_data *common_data = + rsrc_data->common_data; + struct cam_vfe_bus_ver3_reg_offset_ubwc_client *ubwc_regs; + + ubwc_regs = (struct cam_vfe_bus_ver3_reg_offset_ubwc_client *) + rsrc_data->hw_regs->ubwc_regs; + + cam_io_w(0xf, common_data->mem_base + rsrc_data->hw_regs->burst_limit); + + cam_io_w((rsrc_data->height << 16) | rsrc_data->width, + common_data->mem_base + rsrc_data->hw_regs->image_cfg_0); + cam_io_w(rsrc_data->pack_fmt, + common_data->mem_base + rsrc_data->hw_regs->packer_cfg); + + /* enable ubwc if needed*/ + if (rsrc_data->en_ubwc) { + val = cam_io_r_mb(common_data->mem_base + ubwc_regs->mode_cfg); + val |= 0x1; + cam_io_w_mb(val, common_data->mem_base + ubwc_regs->mode_cfg); + } + + /* Enable WM */ + cam_io_w_mb(rsrc_data->en_cfg, common_data->mem_base + + rsrc_data->hw_regs->cfg); + + CAM_DBG(CAM_ISP, + "Start VFE:%d WM:%d offset:0x%X en_cfg:0x%X width:%d height:%d", + rsrc_data->common_data->core_index, rsrc_data->index, + (uint32_t) rsrc_data->hw_regs->cfg, rsrc_data->en_cfg, + rsrc_data->width, rsrc_data->height); + CAM_DBG(CAM_ISP, "WM:%d pk_fmt:%d stride:%d burst len:%d", + rsrc_data->index, rsrc_data->pack_fmt & PACKER_FMT_VER3_MAX, + rsrc_data->stride, 0xF); + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return 0; +} + +static int cam_vfe_bus_ver3_stop_wm(struct cam_isp_resource_node *wm_res) +{ + struct cam_vfe_bus_ver3_wm_resource_data *rsrc_data = + wm_res->res_priv; + struct cam_vfe_bus_ver3_common_data *common_data = + rsrc_data->common_data; + + /* Disable WM */ + cam_io_w_mb(0x0, common_data->mem_base + rsrc_data->hw_regs->cfg); + CAM_DBG(CAM_ISP, "Stop VFE:%d WM:%d", + rsrc_data->common_data->core_index, rsrc_data->index); + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + rsrc_data->init_cfg_done = false; + rsrc_data->hfr_cfg_done = false; + rsrc_data->ubwc_updated = false; + + return 0; +} + +static int cam_vfe_bus_ver3_handle_wm_done_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + return -EPERM; +} + +static int cam_vfe_bus_ver3_handle_wm_done_bottom_half(void *wm_node, + void *evt_payload_priv) +{ + return -EPERM; +} + +static int cam_vfe_bus_ver3_init_wm_resource(uint32_t index, + struct cam_vfe_bus_ver3_priv *ver3_bus_priv, + struct cam_vfe_bus_ver3_hw_info *ver3_hw_info, + struct cam_isp_resource_node *wm_res) +{ + struct cam_vfe_bus_ver3_wm_resource_data *rsrc_data; + + rsrc_data = kzalloc(sizeof(struct cam_vfe_bus_ver3_wm_resource_data), + GFP_KERNEL); + if (!rsrc_data) { + CAM_DBG(CAM_ISP, "Failed to alloc for WM res priv"); + return -ENOMEM; + } + wm_res->res_priv = rsrc_data; + + rsrc_data->index = index; + rsrc_data->hw_regs = &ver3_hw_info->bus_client_reg[index]; + rsrc_data->common_data = &ver3_bus_priv->common_data; + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&wm_res->list); + + wm_res->start = cam_vfe_bus_ver3_start_wm; + wm_res->stop = cam_vfe_bus_ver3_stop_wm; + wm_res->top_half_handler = cam_vfe_bus_ver3_handle_wm_done_top_half; + wm_res->bottom_half_handler = + cam_vfe_bus_ver3_handle_wm_done_bottom_half; + wm_res->hw_intf = ver3_bus_priv->common_data.hw_intf; + + return 0; +} + +static int cam_vfe_bus_ver3_deinit_wm_resource( + struct cam_isp_resource_node *wm_res) +{ + struct cam_vfe_bus_ver3_wm_resource_data *rsrc_data; + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + INIT_LIST_HEAD(&wm_res->list); + + wm_res->start = NULL; + wm_res->stop = NULL; + wm_res->top_half_handler = NULL; + wm_res->bottom_half_handler = NULL; + wm_res->hw_intf = NULL; + + rsrc_data = wm_res->res_priv; + wm_res->res_priv = NULL; + if (!rsrc_data) + return -ENOMEM; + kfree(rsrc_data); + + return 0; +} + +static void cam_vfe_bus_ver3_add_wm_to_comp_grp( + struct cam_isp_resource_node *comp_grp, + uint32_t composite_mask) +{ + struct cam_vfe_bus_ver3_comp_grp_data *rsrc_data = comp_grp->res_priv; + + rsrc_data->composite_mask |= composite_mask; +} + +static bool cam_vfe_bus_ver3_match_comp_grp( + struct cam_vfe_bus_ver3_priv *ver3_bus_priv, + struct cam_isp_resource_node **comp_grp, + uint32_t comp_grp_id) +{ + struct cam_vfe_bus_ver3_comp_grp_data *rsrc_data = NULL; + struct cam_isp_resource_node *comp_grp_local = NULL; + + list_for_each_entry(comp_grp_local, + &ver3_bus_priv->used_comp_grp, list) { + rsrc_data = comp_grp_local->res_priv; + if (rsrc_data->comp_grp_type == comp_grp_id) { + /* Match found */ + *comp_grp = comp_grp_local; + return true; + } + } + + list_for_each_entry(comp_grp_local, + &ver3_bus_priv->free_comp_grp, list) { + rsrc_data = comp_grp_local->res_priv; + if (rsrc_data->comp_grp_type == comp_grp_id) { + /* Match found */ + *comp_grp = comp_grp_local; + list_del(&comp_grp_local->list); + list_add_tail(&comp_grp_local->list, + &ver3_bus_priv->used_comp_grp); + return false; + } + } + + *comp_grp = NULL; + return false; +} + +static int cam_vfe_bus_ver3_acquire_comp_grp( + struct cam_vfe_bus_ver3_priv *ver3_bus_priv, + struct cam_isp_out_port_generic_info *out_port_info, + void *tasklet, + uint32_t is_dual, + uint32_t is_master, + enum cam_vfe_bus_ver3_vfe_core_id dual_slave_core, + struct cam_isp_resource_node **comp_grp, + enum cam_vfe_bus_ver3_comp_grp_type comp_grp_id) +{ + int rc = 0; + struct cam_isp_resource_node *comp_grp_local = NULL; + struct cam_vfe_bus_ver3_comp_grp_data *rsrc_data = NULL; + bool previously_acquired = false; + + if (comp_grp_id >= CAM_VFE_BUS_VER3_COMP_GRP_0 && + comp_grp_id <= CAM_VFE_BUS_VER3_COMP_GRP_13) { + /* Check if matching comp_grp has already been acquired */ + previously_acquired = cam_vfe_bus_ver3_match_comp_grp( + ver3_bus_priv, &comp_grp_local, comp_grp_id); + } + + if (!comp_grp_local) { + CAM_ERR(CAM_ISP, "Invalid comp_grp:%d", comp_grp_id); + return -ENODEV; + } + + rsrc_data = comp_grp_local->res_priv; + + if (!previously_acquired) { + if (is_dual) { + rc = cam_vfe_bus_ver3_get_intra_client_mask( + dual_slave_core, + comp_grp_local->hw_intf->hw_idx, + &rsrc_data->intra_client_mask); + if (rc) + return rc; + } + + comp_grp_local->tasklet_info = tasklet; + comp_grp_local->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + rsrc_data->is_master = is_master; + rsrc_data->is_dual = is_dual; + + if (is_master) + rsrc_data->addr_sync_mode = 0; + else + rsrc_data->addr_sync_mode = 1; + + } else { + rsrc_data = comp_grp_local->res_priv; + /* Do not support runtime change in composite mask */ + if (comp_grp_local->res_state == + CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_ERR(CAM_ISP, "Invalid State %d comp_grp:%u", + comp_grp_local->res_state, + rsrc_data->comp_grp_type); + return -EBUSY; + } + } + + CAM_DBG(CAM_ISP, "Acquire VFE:%d comp_grp:%u", + rsrc_data->common_data->core_index, rsrc_data->comp_grp_type); + + rsrc_data->acquire_dev_cnt++; + *comp_grp = comp_grp_local; + + return rc; +} + +static int cam_vfe_bus_ver3_release_comp_grp( + struct cam_vfe_bus_ver3_priv *ver3_bus_priv, + struct cam_isp_resource_node *in_comp_grp) +{ + struct cam_isp_resource_node *comp_grp = NULL; + struct cam_vfe_bus_ver3_comp_grp_data *in_rsrc_data = NULL; + int match_found = 0; + + if (!in_comp_grp) { + CAM_ERR(CAM_ISP, "Invalid Params comp_grp %pK", in_comp_grp); + return -EINVAL; + } + + if (in_comp_grp->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, "Already released comp_grp"); + return 0; + } + + if (in_comp_grp->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_ERR(CAM_ISP, "Invalid State %d", + in_comp_grp->res_state); + return -EBUSY; + } + + in_rsrc_data = in_comp_grp->res_priv; + CAM_DBG(CAM_ISP, "Release VFE:%d comp_grp:%u", + ver3_bus_priv->common_data.core_index, + in_rsrc_data->comp_grp_type); + + list_for_each_entry(comp_grp, &ver3_bus_priv->used_comp_grp, list) { + if (comp_grp == in_comp_grp) { + match_found = 1; + break; + } + } + + if (!match_found) { + CAM_ERR(CAM_ISP, "Could not find comp_grp:%u", + in_rsrc_data->comp_grp_type); + return -ENODEV; + } + + in_rsrc_data->acquire_dev_cnt--; + if (in_rsrc_data->acquire_dev_cnt == 0) { + list_del(&comp_grp->list); + + in_rsrc_data->dual_slave_core = CAM_VFE_BUS_VER3_VFE_CORE_MAX; + in_rsrc_data->addr_sync_mode = 0; + in_rsrc_data->composite_mask = 0; + + comp_grp->tasklet_info = NULL; + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + list_add_tail(&comp_grp->list, &ver3_bus_priv->free_comp_grp); + } + + return 0; +} + +static int cam_vfe_bus_ver3_start_comp_grp( + struct cam_isp_resource_node *comp_grp, uint32_t *bus_irq_reg_mask) +{ + int rc = 0; + uint32_t val; + struct cam_vfe_bus_ver3_comp_grp_data *rsrc_data = NULL; + struct cam_vfe_bus_ver3_common_data *common_data = NULL; + + rsrc_data = comp_grp->res_priv; + common_data = rsrc_data->common_data; + + CAM_DBG(CAM_ISP, + "Start VFE:%d comp_grp:%d streaming state:%d comp_mask:0x%X", + rsrc_data->common_data->core_index, + rsrc_data->comp_grp_type, comp_grp->res_state, + rsrc_data->composite_mask); + + if (comp_grp->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + return 0; + + if (rsrc_data->is_dual) { + if (rsrc_data->is_master) { + val = cam_io_r_mb(common_data->mem_base + + common_data->common_reg->comp_cfg_0); + + val |= (0x1 << (rsrc_data->comp_grp_type + 14)); + + cam_io_w_mb(val, common_data->mem_base + + common_data->common_reg->comp_cfg_0); + + val = cam_io_r_mb(common_data->mem_base + + common_data->common_reg->comp_cfg_1); + + val |= (0x1 << rsrc_data->comp_grp_type); + + cam_io_w_mb(val, common_data->mem_base + + common_data->common_reg->comp_cfg_1); + } else { + val = cam_io_r_mb(common_data->mem_base + + common_data->common_reg->comp_cfg_0); + + val |= (0x1 << rsrc_data->comp_grp_type); + val |= (0x1 << (rsrc_data->comp_grp_type + 14)); + + cam_io_w_mb(val, common_data->mem_base + + common_data->common_reg->comp_cfg_0); + + val = cam_io_r_mb(common_data->mem_base + + common_data->common_reg->comp_cfg_1); + + val |= (0x1 << rsrc_data->comp_grp_type); + + cam_io_w_mb(val, common_data->mem_base + + common_data->common_reg->comp_cfg_1); + } + } + + if (rsrc_data->ubwc_static_ctrl) { + val = cam_io_r_mb(common_data->mem_base + + common_data->common_reg->ubwc_static_ctrl); + val |= rsrc_data->ubwc_static_ctrl; + cam_io_w_mb(val, common_data->mem_base + + common_data->common_reg->ubwc_static_ctrl); + } + + bus_irq_reg_mask[CAM_VFE_BUS_VER3_IRQ_REG0] = + (0x1 << (rsrc_data->comp_grp_type + + rsrc_data->common_data->comp_done_shift)); + + CAM_DBG(CAM_ISP, "Start Done VFE:%d comp_grp:%d bus_irq_mask_0: 0x%X", + rsrc_data->common_data->core_index, + rsrc_data->comp_grp_type, + bus_irq_reg_mask[CAM_VFE_BUS_VER3_IRQ_REG0]); + + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return rc; +} + +static int cam_vfe_bus_ver3_stop_comp_grp( + struct cam_isp_resource_node *comp_grp) +{ + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + return 0; +} + +static int cam_vfe_bus_ver3_handle_comp_done_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + return -EPERM; +} + +static int cam_vfe_bus_ver3_handle_comp_done_bottom_half( + void *handler_priv, + void *evt_payload_priv, + uint32_t *comp_mask) +{ + int rc = CAM_VFE_IRQ_STATUS_ERR; + struct cam_isp_resource_node *comp_grp = handler_priv; + struct cam_vfe_bus_irq_evt_payload *evt_payload = evt_payload_priv; + struct cam_vfe_bus_ver3_comp_grp_data *rsrc_data = comp_grp->res_priv; + uint32_t *cam_ife_irq_regs; + uint32_t status_0; + + if (!evt_payload) + return rc; + + if (rsrc_data->is_dual && (!rsrc_data->is_master)) { + CAM_ERR(CAM_ISP, "Invalid comp_grp:%u is_master:%u", + rsrc_data->comp_grp_type, rsrc_data->is_master); + return rc; + } + + cam_ife_irq_regs = evt_payload->irq_reg_val; + status_0 = cam_ife_irq_regs[CAM_IFE_IRQ_BUS_VER3_REG_STATUS0]; + + if (status_0 & BIT(rsrc_data->comp_grp_type + + rsrc_data->common_data->comp_done_shift)) { + evt_payload->evt_id = CAM_ISP_HW_EVENT_DONE; + rc = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + CAM_DBG(CAM_ISP, "VFE:%d comp_grp:%d Bus IRQ status_0: 0x%X rc:%d", + rsrc_data->common_data->core_index, rsrc_data->comp_grp_type, + status_0, rc); + + *comp_mask = rsrc_data->composite_mask; + + return rc; +} + +static int cam_vfe_bus_ver3_init_comp_grp(uint32_t index, + struct cam_hw_soc_info *soc_info, + struct cam_vfe_bus_ver3_priv *ver3_bus_priv, + struct cam_vfe_bus_ver3_hw_info *ver3_hw_info, + struct cam_isp_resource_node *comp_grp) +{ + struct cam_vfe_bus_ver3_comp_grp_data *rsrc_data = NULL; + struct cam_vfe_soc_private *vfe_soc_private = soc_info->soc_private; + int ddr_type = 0; + + rsrc_data = kzalloc(sizeof(struct cam_vfe_bus_ver3_comp_grp_data), + GFP_KERNEL); + if (!rsrc_data) + return -ENOMEM; + + comp_grp->res_priv = rsrc_data; + + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&comp_grp->list); + + rsrc_data->comp_grp_type = index; + rsrc_data->common_data = &ver3_bus_priv->common_data; + rsrc_data->dual_slave_core = CAM_VFE_BUS_VER3_VFE_CORE_MAX; + + if (rsrc_data->comp_grp_type != CAM_VFE_BUS_VER3_COMP_GRP_0 && + rsrc_data->comp_grp_type != CAM_VFE_BUS_VER3_COMP_GRP_1) + rsrc_data->ubwc_static_ctrl = 0; + else { + ddr_type = of_fdt_get_ddrtype(); + if ((ddr_type == DDR_TYPE_LPDDR5) || + (ddr_type == DDR_TYPE_LPDDR5X)) + rsrc_data->ubwc_static_ctrl = + vfe_soc_private->ubwc_static_ctrl[1]; + else + rsrc_data->ubwc_static_ctrl = + vfe_soc_private->ubwc_static_ctrl[0]; + } + + list_add_tail(&comp_grp->list, &ver3_bus_priv->free_comp_grp); + + comp_grp->top_half_handler = cam_vfe_bus_ver3_handle_comp_done_top_half; + comp_grp->hw_intf = ver3_bus_priv->common_data.hw_intf; + + return 0; +} + +static int cam_vfe_bus_ver3_deinit_comp_grp( + struct cam_isp_resource_node *comp_grp) +{ + struct cam_vfe_bus_ver3_comp_grp_data *rsrc_data = + comp_grp->res_priv; + + comp_grp->start = NULL; + comp_grp->stop = NULL; + comp_grp->top_half_handler = NULL; + comp_grp->bottom_half_handler = NULL; + comp_grp->hw_intf = NULL; + + list_del_init(&comp_grp->list); + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + + comp_grp->res_priv = NULL; + + if (!rsrc_data) { + CAM_ERR(CAM_ISP, "comp_grp_priv is NULL"); + return -ENODEV; + } + kfree(rsrc_data); + + return 0; +} + +static int cam_vfe_bus_ver3_get_secure_mode(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_isp_hw_get_cmd_update *secure_mode = cmd_args; + struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data; + uint32_t *mode; + + rsrc_data = (struct cam_vfe_bus_ver3_vfe_out_data *) + secure_mode->res->res_priv; + mode = (uint32_t *)secure_mode->data; + *mode = (rsrc_data->secure_mode == CAM_SECURE_MODE_SECURE) ? + true : false; + + return 0; +} + +static int cam_vfe_bus_ver3_acquire_vfe_out(void *bus_priv, void *acquire_args, + uint32_t args_size) +{ + int rc = -ENODEV; + int i; + enum cam_vfe_bus_ver3_vfe_out_type vfe_out_res_id; + uint32_t format; + int num_wm; + struct cam_vfe_bus_ver3_priv *ver3_bus_priv = bus_priv; + struct cam_vfe_acquire_args *acq_args = acquire_args; + struct cam_vfe_hw_vfe_out_acquire_args *out_acquire_args; + struct cam_isp_resource_node *rsrc_node = NULL; + struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data = NULL; + uint32_t secure_caps = 0, mode; + enum cam_vfe_bus_ver3_comp_grp_type comp_grp_id; + uint32_t client_done_mask = 0; + + if (!bus_priv || !acquire_args) { + CAM_ERR(CAM_ISP, "Invalid Param"); + return -EINVAL; + } + + out_acquire_args = &acq_args->vfe_out; + format = out_acquire_args->out_port_info->format; + + CAM_DBG(CAM_ISP, "VFE:%d Acquire out_type:0x%X", + ver3_bus_priv->common_data.core_index, + out_acquire_args->out_port_info->res_type); + + vfe_out_res_id = cam_vfe_bus_ver3_get_out_res_id( + out_acquire_args->out_port_info->res_type); + if (vfe_out_res_id == CAM_VFE_BUS_VER3_VFE_OUT_MAX) + return -ENODEV; + + num_wm = cam_vfe_bus_ver3_get_num_wm(vfe_out_res_id, format); + if (num_wm < 1) + return -EINVAL; + + rsrc_node = &ver3_bus_priv->vfe_out[vfe_out_res_id]; + if (rsrc_node->res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, + "VFE:%d out_type:0x%X resource not available state:%d", + ver3_bus_priv->common_data.core_index, + vfe_out_res_id, rsrc_node->res_state); + return -EBUSY; + } + + rsrc_data = rsrc_node->res_priv; + rsrc_data->common_data->event_cb = acq_args->event_cb; + rsrc_data->priv = acq_args->priv; + + secure_caps = cam_vfe_bus_ver3_can_be_secure( + rsrc_data->out_type); + mode = out_acquire_args->out_port_info->secure_mode; + mutex_lock(&rsrc_data->common_data->bus_mutex); + if (secure_caps) { + if (!rsrc_data->common_data->num_sec_out) { + rsrc_data->secure_mode = mode; + rsrc_data->common_data->secure_mode = mode; + } else { + if (mode == rsrc_data->common_data->secure_mode) { + rsrc_data->secure_mode = + rsrc_data->common_data->secure_mode; + } else { + rc = -EINVAL; + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Mismatch: Acquire mode[%d], drvr mode[%d]", + rsrc_data->common_data->secure_mode, + mode); + mutex_unlock( + &rsrc_data->common_data->bus_mutex); + return -EINVAL; + } + } + rsrc_data->common_data->num_sec_out++; + } + mutex_unlock(&rsrc_data->common_data->bus_mutex); + + ver3_bus_priv->tasklet_info = acq_args->tasklet; + rsrc_data->num_wm = num_wm; + rsrc_node->rdi_only_ctx = 0; + rsrc_node->res_id = out_acquire_args->out_port_info->res_type; + rsrc_node->tasklet_info = acq_args->tasklet; + rsrc_node->cdm_ops = out_acquire_args->cdm_ops; + rsrc_data->cdm_util_ops = out_acquire_args->cdm_ops; + + /* Acquire WM and retrieve COMP GRP ID */ + for (i = 0; i < num_wm; i++) { + rc = cam_vfe_bus_ver3_acquire_wm(ver3_bus_priv, + out_acquire_args->out_port_info, + acq_args->tasklet, + vfe_out_res_id, + i, + &rsrc_data->wm_res[i], + &client_done_mask, + out_acquire_args->is_dual, + &comp_grp_id); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed to acquire WM VFE:%d out_type:%d rc:%d", + rsrc_data->common_data->core_index, + vfe_out_res_id, rc); + goto release_wm; + } + } + + /* Acquire composite group using COMP GRP ID */ + rc = cam_vfe_bus_ver3_acquire_comp_grp(ver3_bus_priv, + out_acquire_args->out_port_info, + acq_args->tasklet, + out_acquire_args->is_dual, + out_acquire_args->is_master, + out_acquire_args->dual_slave_core, + &rsrc_data->comp_grp, + comp_grp_id); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed to acquire comp_grp VFE:%d out_typp:%d rc:%d", + rsrc_data->common_data->core_index, + vfe_out_res_id, rc); + return rc; + } + + rsrc_data->is_dual = out_acquire_args->is_dual; + rsrc_data->is_master = out_acquire_args->is_master; + + cam_vfe_bus_ver3_add_wm_to_comp_grp(rsrc_data->comp_grp, + client_done_mask); + + rsrc_node->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + out_acquire_args->rsrc_node = rsrc_node; + + CAM_DBG(CAM_ISP, "Acquire successful"); + return rc; + +release_wm: + for (i--; i >= 0; i--) + cam_vfe_bus_ver3_release_wm(ver3_bus_priv, + rsrc_data->wm_res[i]); + + cam_vfe_bus_ver3_release_comp_grp(ver3_bus_priv, rsrc_data->comp_grp); + + return rc; +} + +static int cam_vfe_bus_ver3_release_vfe_out(void *bus_priv, void *release_args, + uint32_t args_size) +{ + uint32_t i; + struct cam_isp_resource_node *vfe_out = NULL; + struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data = NULL; + uint32_t secure_caps = 0; + + if (!bus_priv || !release_args) { + CAM_ERR(CAM_ISP, "Invalid input bus_priv %pK release_args %pK", + bus_priv, release_args); + return -EINVAL; + } + + vfe_out = release_args; + rsrc_data = vfe_out->res_priv; + + if (vfe_out->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, + "Invalid resource state:%d VFE:%d out_type:0x%X", + vfe_out->res_state, rsrc_data->common_data->core_index, + vfe_out->res_id); + } + + for (i = 0; i < rsrc_data->num_wm; i++) + cam_vfe_bus_ver3_release_wm(bus_priv, rsrc_data->wm_res[i]); + rsrc_data->num_wm = 0; + + if (rsrc_data->comp_grp) + cam_vfe_bus_ver3_release_comp_grp(bus_priv, + rsrc_data->comp_grp); + rsrc_data->comp_grp = NULL; + + vfe_out->tasklet_info = NULL; + vfe_out->cdm_ops = NULL; + rsrc_data->cdm_util_ops = NULL; + + secure_caps = cam_vfe_bus_ver3_can_be_secure(rsrc_data->out_type); + mutex_lock(&rsrc_data->common_data->bus_mutex); + if (secure_caps) { + if (rsrc_data->secure_mode == + rsrc_data->common_data->secure_mode) { + rsrc_data->common_data->num_sec_out--; + rsrc_data->secure_mode = + CAM_SECURE_MODE_NON_SECURE; + } else { + /* + * The validity of the mode is properly + * checked while acquiring the output port. + * not expected to reach here, unless there is + * some corruption. + */ + CAM_ERR(CAM_ISP, "driver[%d],resource[%d] mismatch", + rsrc_data->common_data->secure_mode, + rsrc_data->secure_mode); + } + + if (!rsrc_data->common_data->num_sec_out) + rsrc_data->common_data->secure_mode = + CAM_SECURE_MODE_NON_SECURE; + } + mutex_unlock(&rsrc_data->common_data->bus_mutex); + + if (vfe_out->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) + vfe_out->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + return 0; +} + +static int cam_vfe_bus_ver3_start_vfe_out( + struct cam_isp_resource_node *vfe_out) +{ + int rc = 0, i; + struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data = NULL; + struct cam_vfe_bus_ver3_common_data *common_data = NULL; + uint32_t bus_irq_reg_mask[CAM_VFE_BUS_VER3_IRQ_MAX]; + uint32_t rup_irq_reg_mask[CAM_VFE_BUS_VER3_IRQ_MAX]; + uint32_t source_group = 0; + + if (!vfe_out) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + + rsrc_data = vfe_out->res_priv; + common_data = rsrc_data->common_data; + source_group = rsrc_data->source_group; + + CAM_DBG(CAM_ISP, "Start VFE:%d out_type:0x%X", + rsrc_data->common_data->core_index, rsrc_data->out_type); + + if (vfe_out->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, + "Invalid resource state:%d VFE:%d out_type:0x%X", + vfe_out->res_state, rsrc_data->common_data->core_index, + rsrc_data->out_type); + return -EACCES; + } + + for (i = 0; i < rsrc_data->num_wm; i++) + rc = cam_vfe_bus_ver3_start_wm(rsrc_data->wm_res[i]); + + memset(bus_irq_reg_mask, 0, sizeof(bus_irq_reg_mask)); + rc = cam_vfe_bus_ver3_start_comp_grp(rsrc_data->comp_grp, + bus_irq_reg_mask); + + if (rsrc_data->is_dual && !rsrc_data->is_master) + goto end; + + vfe_out->irq_handle = cam_irq_controller_subscribe_irq( + common_data->bus_irq_controller, + CAM_IRQ_PRIORITY_1, + bus_irq_reg_mask, + vfe_out, + vfe_out->top_half_handler, + vfe_out->bottom_half_handler, + vfe_out->tasklet_info, + &tasklet_bh_api); + + if (vfe_out->irq_handle < 1) { + CAM_ERR(CAM_ISP, "Subscribe IRQ failed for VFE out_res %d", + vfe_out->res_id); + vfe_out->irq_handle = 0; + return -EFAULT; + } + + if ((common_data->is_lite || source_group > CAM_VFE_BUS_VER3_SRC_GRP_0) + && !vfe_out->rdi_only_ctx) + goto end; + + if (!common_data->rup_irq_handle[source_group]) { + memset(rup_irq_reg_mask, 0, sizeof(rup_irq_reg_mask)); + rup_irq_reg_mask[CAM_VFE_BUS_VER3_IRQ_REG0] |= + 0x1 << source_group; + + CAM_DBG(CAM_ISP, + "VFE:%d out_type:0x%X bus_irq_mask_0:0x%X for RUP", + rsrc_data->common_data->core_index, rsrc_data->out_type, + rup_irq_reg_mask[CAM_VFE_BUS_VER3_IRQ_REG0]); + + common_data->rup_irq_handle[source_group] = + cam_irq_controller_subscribe_irq( + common_data->rup_irq_controller, + CAM_IRQ_PRIORITY_0, + rup_irq_reg_mask, + vfe_out, + cam_vfe_bus_ver3_handle_rup_top_half, + cam_vfe_bus_ver3_handle_rup_bottom_half, + vfe_out->tasklet_info, + &tasklet_bh_api); + + if (common_data->rup_irq_handle[source_group] < 1) { + CAM_ERR(CAM_ISP, "Failed to subscribe RUP IRQ"); + common_data->rup_irq_handle[source_group] = 0; + return -EFAULT; + } + } + +end: + vfe_out->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + return rc; +} + +static int cam_vfe_bus_ver3_stop_vfe_out( + struct cam_isp_resource_node *vfe_out) +{ + int rc = 0, i; + struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data = NULL; + struct cam_vfe_bus_ver3_common_data *common_data = NULL; + + if (!vfe_out) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + + rsrc_data = vfe_out->res_priv; + common_data = rsrc_data->common_data; + + if (vfe_out->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE || + vfe_out->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_DBG(CAM_ISP, "Stop VFE:%d out_type:0x%X state:%d", + rsrc_data->common_data->core_index, rsrc_data->out_type, + vfe_out->res_state); + return rc; + } + + rc = cam_vfe_bus_ver3_stop_comp_grp(rsrc_data->comp_grp); + + for (i = 0; i < rsrc_data->num_wm; i++) + rc = cam_vfe_bus_ver3_stop_wm(rsrc_data->wm_res[i]); + + if (common_data->rup_irq_handle[rsrc_data->source_group]) { + rc = cam_irq_controller_unsubscribe_irq( + common_data->rup_irq_controller, + common_data->rup_irq_handle[rsrc_data->source_group]); + common_data->rup_irq_handle[rsrc_data->source_group] = 0; + } + + if (vfe_out->irq_handle) { + rc = cam_irq_controller_unsubscribe_irq( + common_data->bus_irq_controller, + vfe_out->irq_handle); + vfe_out->irq_handle = 0; + } + + vfe_out->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + return rc; +} + +static int cam_vfe_bus_ver3_handle_vfe_out_done_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc; + int i; + struct cam_isp_resource_node *vfe_out = NULL; + struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data = NULL; + struct cam_vfe_bus_irq_evt_payload *evt_payload; + struct cam_vfe_bus_ver3_comp_grp_data *resource_data; + uint32_t status_0; + + vfe_out = th_payload->handler_priv; + if (!vfe_out) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No resource"); + return -ENODEV; + } + + rsrc_data = vfe_out->res_priv; + resource_data = rsrc_data->comp_grp->res_priv; + + CAM_DBG(CAM_ISP, "VFE:%d Bus IRQ status_0: 0x%X status_1: 0x%X", + rsrc_data->common_data->core_index, + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1]); + + rc = cam_vfe_bus_ver3_get_evt_payload(rsrc_data->common_data, + &evt_payload); + + if (rc) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "VFE:%d Bus IRQ status_0: 0x%X status_1: 0x%X", + rsrc_data->common_data->core_index, + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1]); + return rc; + } + + cam_isp_hw_get_timestamp(&evt_payload->ts); + + evt_payload->core_index = rsrc_data->common_data->core_index; + evt_payload->evt_id = evt_id; + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + th_payload->evt_payload_priv = evt_payload; + + status_0 = th_payload->evt_status_arr[CAM_IFE_IRQ_BUS_VER3_REG_STATUS0]; + + if (status_0 & BIT(resource_data->comp_grp_type + + rsrc_data->common_data->comp_done_shift)) { + trace_cam_log_event("bufdone", "bufdone_IRQ", + status_0, resource_data->comp_grp_type); + } + + if (status_0 & 0x1) + trace_cam_log_event("UnexpectedRUP", "RUP_IRQ", status_0, 40); + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +static int cam_vfe_bus_ver3_handle_vfe_out_done_bottom_half( + void *handler_priv, + void *evt_payload_priv) +{ + int rc = -EINVAL, num_out = 0, i = 0; + struct cam_isp_resource_node *vfe_out = handler_priv; + struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data = vfe_out->res_priv; + struct cam_vfe_bus_irq_evt_payload *evt_payload = evt_payload_priv; + struct cam_isp_hw_event_info evt_info; + void *ctx = NULL; + uint32_t evt_id = 0, comp_mask = 0; + uint32_t out_list[CAM_VFE_BUS_VER3_VFE_OUT_MAX]; + + rc = cam_vfe_bus_ver3_handle_comp_done_bottom_half( + rsrc_data->comp_grp, evt_payload_priv, &comp_mask); + CAM_DBG(CAM_ISP, "VFE:%d out_type:0x%X rc:%d", + rsrc_data->common_data->core_index, rsrc_data->out_type, + rsrc_data->out_type, rc); + + ctx = rsrc_data->priv; + memset(out_list, 0, sizeof(out_list)); + + switch (rc) { + case CAM_VFE_IRQ_STATUS_SUCCESS: + evt_id = evt_payload->evt_id; + + evt_info.res_type = vfe_out->res_type; + evt_info.hw_idx = vfe_out->hw_intf->hw_idx; + + rc = cam_vfe_bus_ver3_get_comp_vfe_out_res_id_list( + comp_mask, out_list, &num_out, + rsrc_data->common_data->is_lite); + for (i = 0; i < num_out; i++) { + evt_info.res_id = out_list[i]; + if (rsrc_data->common_data->event_cb) + rsrc_data->common_data->event_cb(ctx, evt_id, + (void *)&evt_info); + } + break; + default: + break; + } + + cam_vfe_bus_ver3_put_evt_payload(rsrc_data->common_data, &evt_payload); + + return rc; +} + +static int cam_vfe_bus_ver3_init_vfe_out_resource(uint32_t index, + struct cam_vfe_bus_ver3_priv *ver3_bus_priv, + struct cam_vfe_bus_ver3_hw_info *ver3_hw_info) +{ + struct cam_isp_resource_node *vfe_out = NULL; + struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data = NULL; + int rc = 0; + int32_t vfe_out_type = + ver3_hw_info->vfe_out_hw_info[index].vfe_out_type; + + if (vfe_out_type < 0 || + vfe_out_type >= CAM_VFE_BUS_VER3_VFE_OUT_MAX) { + CAM_ERR(CAM_ISP, "Init VFE Out failed, Invalid type=%d", + vfe_out_type); + return -EINVAL; + } + + vfe_out = &ver3_bus_priv->vfe_out[vfe_out_type]; + if (vfe_out->res_state != CAM_ISP_RESOURCE_STATE_UNAVAILABLE || + vfe_out->res_priv) { + CAM_ERR(CAM_ISP, "vfe_out_type %d has already been initialized", + vfe_out_type); + return -EFAULT; + } + + rsrc_data = kzalloc(sizeof(struct cam_vfe_bus_ver3_vfe_out_data), + GFP_KERNEL); + if (!rsrc_data) { + rc = -ENOMEM; + return rc; + } + + vfe_out->res_priv = rsrc_data; + + vfe_out->res_type = CAM_ISP_RESOURCE_VFE_OUT; + vfe_out->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&vfe_out->list); + + rsrc_data->source_group = + ver3_hw_info->vfe_out_hw_info[index].source_group; + rsrc_data->out_type = + ver3_hw_info->vfe_out_hw_info[index].vfe_out_type; + rsrc_data->common_data = &ver3_bus_priv->common_data; + rsrc_data->max_width = + ver3_hw_info->vfe_out_hw_info[index].max_width; + rsrc_data->max_height = + ver3_hw_info->vfe_out_hw_info[index].max_height; + rsrc_data->secure_mode = CAM_SECURE_MODE_NON_SECURE; + + vfe_out->start = cam_vfe_bus_ver3_start_vfe_out; + vfe_out->stop = cam_vfe_bus_ver3_stop_vfe_out; + vfe_out->top_half_handler = + cam_vfe_bus_ver3_handle_vfe_out_done_top_half; + vfe_out->bottom_half_handler = + cam_vfe_bus_ver3_handle_vfe_out_done_bottom_half; + vfe_out->process_cmd = cam_vfe_bus_ver3_process_cmd; + vfe_out->hw_intf = ver3_bus_priv->common_data.hw_intf; + vfe_out->irq_handle = 0; + + return 0; +} + +static int cam_vfe_bus_ver3_deinit_vfe_out_resource( + struct cam_isp_resource_node *vfe_out) +{ + struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data = vfe_out->res_priv; + + if (vfe_out->res_state == CAM_ISP_RESOURCE_STATE_UNAVAILABLE) { + /* + * This is not error. It can happen if the resource is + * never supported in the HW. + */ + CAM_DBG(CAM_ISP, "VFE:%d out_type:%d already deinitialized", + rsrc_data->common_data->core_index, + rsrc_data->out_type); + return 0; + } + + vfe_out->start = NULL; + vfe_out->stop = NULL; + vfe_out->top_half_handler = NULL; + vfe_out->bottom_half_handler = NULL; + vfe_out->hw_intf = NULL; + vfe_out->irq_handle = 0; + + vfe_out->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + INIT_LIST_HEAD(&vfe_out->list); + vfe_out->res_priv = NULL; + + if (!rsrc_data) + return -ENOMEM; + kfree(rsrc_data); + + return 0; +} + +static void cam_vfe_bus_ver3_print_dimensions( + enum cam_vfe_bus_ver3_vfe_out_type vfe_out_res_id, + enum cam_vfe_bus_plane_type plane, + struct cam_vfe_bus_ver3_priv *bus_priv) +{ + struct cam_isp_resource_node *wm_res = NULL; + struct cam_vfe_bus_ver3_wm_resource_data *wm_data = NULL; + int wm_idx = 0; + + wm_idx = cam_vfe_bus_ver3_get_wm_idx(vfe_out_res_id, plane, + bus_priv->common_data.is_lite); + + if (wm_idx < 0 || wm_idx >= bus_priv->num_client || plane > PLANE_C) { + CAM_ERR(CAM_ISP, + "Unsupported VFE out_type:0x%X plane:%d wm_idx:%d max_idx:%d", + vfe_out_res_id, plane, wm_idx, + bus_priv->num_client - 1); + return; + } + + wm_res = &bus_priv->bus_client[wm_idx]; + wm_data = wm_res->res_priv; + + CAM_INFO(CAM_ISP, + "VFE:%d WM:%d width:%u height:%u stride:%u x_init:%u en_cfg:%u", + wm_data->common_data->core_index, wm_idx, wm_data->width, + wm_data->height, wm_data->stride, wm_data->h_init, + wm_data->en_cfg); +} + +static int cam_vfe_bus_ver3_handle_bus_irq(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + struct cam_vfe_bus_ver3_priv *bus_priv; + int rc = 0; + + bus_priv = th_payload->handler_priv; + CAM_DBG(CAM_ISP, "Enter"); + rc = cam_irq_controller_handle_irq(evt_id, + bus_priv->common_data.bus_irq_controller); + return (rc == IRQ_HANDLED) ? 0 : -EINVAL; +} + +static int cam_vfe_bus_ver3_handle_rup_irq(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + struct cam_vfe_bus_ver3_priv *bus_priv; + int rc = 0; + + bus_priv = th_payload->handler_priv; + CAM_DBG(CAM_ISP, "Enter"); + rc = cam_irq_controller_handle_irq(evt_id, + bus_priv->common_data.rup_irq_controller); + return (rc == IRQ_HANDLED) ? 0 : -EINVAL; +} + +static int cam_vfe_bus_ver3_err_irq_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int i = 0, rc = 0; + struct cam_vfe_bus_ver3_priv *bus_priv = + th_payload->handler_priv; + struct cam_vfe_bus_irq_evt_payload *evt_payload; + + CAM_ERR_RATE_LIMIT(CAM_ISP, "VFE:%d BUS Err IRQ", + bus_priv->common_data.core_index); + for (i = 0; i < th_payload->num_registers; i++) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "VFE:%d BUS IRQ status_%d: 0x%X", + bus_priv->common_data.core_index, i, + th_payload->evt_status_arr[i]); + } + cam_irq_controller_disable_irq(bus_priv->common_data.bus_irq_controller, + bus_priv->error_irq_handle); + + rc = cam_vfe_bus_ver3_get_evt_payload(&bus_priv->common_data, + &evt_payload); + if (rc) + return rc; + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + evt_payload->core_index = bus_priv->common_data.core_index; + + evt_payload->ccif_violation_status = cam_io_r_mb( + bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->ccif_violation_status); + + evt_payload->image_size_violation_status = cam_io_r_mb( + bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->image_size_violation_status); + + th_payload->evt_payload_priv = evt_payload; + + return rc; +} + +static int cam_vfe_bus_ver3_err_irq_bottom_half( + void *handler_priv, void *evt_payload_priv) +{ + struct cam_vfe_bus_irq_evt_payload *evt_payload = evt_payload_priv; + struct cam_vfe_bus_ver3_priv *bus_priv = handler_priv; + struct cam_vfe_bus_ver3_common_data *common_data; + struct cam_isp_hw_event_info evt_info; + uint32_t val = 0, image_size_violation = 0, ccif_violation = 0; + + if (!handler_priv || !evt_payload_priv) + return -EINVAL; + + common_data = &bus_priv->common_data; + + val = evt_payload->irq_reg_val[CAM_IFE_IRQ_BUS_VER3_REG_STATUS0]; + image_size_violation = (val >> 31) & 0x1; + ccif_violation = (val >> 30) & 0x1; + + CAM_ERR(CAM_ISP, + "VFE:%d BUS Violation image_size_violation %d ccif_violation %d", + bus_priv->common_data.core_index, image_size_violation, + ccif_violation); + CAM_INFO(CAM_ISP, + "image_size_violation_status 0x%X ccif_violation_status 0x%X", + evt_payload->image_size_violation_status, + evt_payload->ccif_violation_status); + + if (common_data->is_lite) { + if (image_size_violation) { + val = evt_payload->image_size_violation_status; + + if (val & 0x01) { + CAM_INFO(CAM_ISP, + "RDI 0 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_RDI0, + PLANE_Y, + bus_priv); + } + + if (val & 0x02) { + CAM_INFO(CAM_ISP, + "RDI 1 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_RDI1, + PLANE_Y, + bus_priv); + } + + if (val & 0x04) { + CAM_INFO(CAM_ISP, + "RDI 2 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_RDI2, + PLANE_Y, + bus_priv); + } + + if (val & 0x08) { + CAM_INFO(CAM_ISP, + "RDI 3 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_RDI3, + PLANE_Y, + bus_priv); + } + } + + if (ccif_violation) { + val = evt_payload->ccif_violation_status; + + if (val & 0x01) + CAM_INFO(CAM_ISP, + "RDI 0 ccif violation"); + + if (val & 0x02) + CAM_INFO(CAM_ISP, + "RDI 1 ccif violation"); + + if (val & 0x04) + CAM_INFO(CAM_ISP, + "RDI 2 ccif violation"); + + if (val & 0x08) + CAM_INFO(CAM_ISP, + "RDI 3 ccif violation"); + } + + goto end; + } + + if (image_size_violation) { + val = evt_payload->image_size_violation_status; + + if (val & 0x01) { + CAM_INFO(CAM_ISP, "VID Y 1:1 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_FULL, + PLANE_Y, + bus_priv); + } + + if (val & 0x02) { + CAM_INFO(CAM_ISP, "VID C 1:1 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_FULL, + PLANE_C, + bus_priv); + } + + if (val & 0x04) { + CAM_INFO(CAM_ISP, "VID YC 4:1 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_DS4, + PLANE_Y, + bus_priv); + } + + if (val & 0x08) { + CAM_INFO(CAM_ISP, "VID YC 16:1 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_DS16, + PLANE_Y, + bus_priv); + } + + if (val & 0x010) { + CAM_INFO(CAM_ISP, "DISP Y 1:1 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_FULL_DISP, + PLANE_Y, + bus_priv); + } + + if (val & 0x020) { + CAM_INFO(CAM_ISP, "DISP C 1:1 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_FULL_DISP, + PLANE_C, + bus_priv); + } + + if (val & 0x040) { + CAM_INFO(CAM_ISP, "DISP YC 4:1 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_DS4_DISP, + PLANE_Y, + bus_priv); + } + + if (val & 0x080) { + CAM_INFO(CAM_ISP, "DISP YC 16:1 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_DS16_DISP, + PLANE_Y, + bus_priv); + } + + if (val & 0x0100) { + CAM_INFO(CAM_ISP, "FD Y image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_FD, + PLANE_Y, + bus_priv); + } + + if (val & 0x0200) { + CAM_INFO(CAM_ISP, "FD C image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_FD, + PLANE_C, + bus_priv); + } + + if (val & 0x0400) { + CAM_INFO(CAM_ISP, + "PIXEL RAW DUMP image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_RAW_DUMP, + PLANE_Y, + bus_priv); + } + + if (val & 0x01000) { + CAM_INFO(CAM_ISP, "STATS HDR BE image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BE, + PLANE_Y, + bus_priv); + } + + if (val & 0x02000) { + CAM_INFO(CAM_ISP, + "STATS HDR BHIST image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BHIST, + PLANE_Y, + bus_priv); + } + + if (val & 0x04000) { + CAM_INFO(CAM_ISP, + "STATS TINTLESS BG image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_STATS_TL_BG, + PLANE_Y, + bus_priv); + } + + if (val & 0x08000) { + CAM_INFO(CAM_ISP, "STATS AWB BG image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_STATS_AWB_BG, + PLANE_Y, + bus_priv); + } + + if (val & 0x010000) { + CAM_INFO(CAM_ISP, "STATS BHIST image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_STATS_BHIST, + PLANE_Y, + bus_priv); + } + + if (val & 0x020000) { + CAM_INFO(CAM_ISP, "STATS RS image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_STATS_RS, + PLANE_Y, + bus_priv); + } + + if (val & 0x040000) { + CAM_INFO(CAM_ISP, "STATS CS image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_STATS_CS, + PLANE_Y, + bus_priv); + } + + if (val & 0x080000) { + CAM_INFO(CAM_ISP, "STATS IHIST image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_STATS_IHIST, + PLANE_Y, + bus_priv); + } + + if (val & 0x0100000) { + CAM_INFO(CAM_ISP, "STATS BAF image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_STATS_BF, + PLANE_Y, + bus_priv); + } + + if (val & 0x0200000) { + CAM_INFO(CAM_ISP, "PD image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_2PD, + PLANE_Y, + bus_priv); + } + + if (val & 0x0400000) { + CAM_INFO(CAM_ISP, "LCR image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_LCR, + PLANE_Y, + bus_priv); + } + + if (val & 0x0800000) { + CAM_INFO(CAM_ISP, "RDI 0 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_RDI0, + PLANE_Y, + bus_priv); + } + + if (val & 0x01000000) { + CAM_INFO(CAM_ISP, "RDI 1 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_RDI1, + PLANE_Y, + bus_priv); + } + + if (val & 0x02000000) { + CAM_INFO(CAM_ISP, "RDI 2 image size violation"); + cam_vfe_bus_ver3_print_dimensions( + CAM_VFE_BUS_VER3_VFE_OUT_RDI2, + PLANE_Y, + bus_priv); + } + + } + + if (ccif_violation) { + val = evt_payload->ccif_violation_status; + + if (val & 0x01) + CAM_INFO(CAM_ISP, "VID Y 1:1 ccif violation"); + + if (val & 0x02) + CAM_INFO(CAM_ISP, "VID C 1:1 ccif violation"); + + if (val & 0x04) + CAM_INFO(CAM_ISP, "VID YC 4:1 ccif violation"); + + if (val & 0x08) + CAM_INFO(CAM_ISP, "VID YC 16:1 ccif violation"); + + if (val & 0x010) + CAM_INFO(CAM_ISP, "DISP Y 1:1 ccif violation"); + + if (val & 0x020) + CAM_INFO(CAM_ISP, "DISP C 1:1 ccif violation"); + + if (val & 0x040) + CAM_INFO(CAM_ISP, "DISP YC 4:1 ccif violation"); + + if (val & 0x080) + CAM_INFO(CAM_ISP, "DISP YC 16:1 ccif violation"); + + if (val & 0x0100) + CAM_INFO(CAM_ISP, "FD Y ccif violation"); + + if (val & 0x0200) + CAM_INFO(CAM_ISP, "FD C ccif violation"); + + if (val & 0x0400) + CAM_INFO(CAM_ISP, "PIXEL RAW DUMP ccif violation"); + + if (val & 0x01000) + CAM_INFO(CAM_ISP, "STATS HDR BE ccif violation"); + + if (val & 0x02000) + CAM_INFO(CAM_ISP, "STATS HDR BHIST ccif violation"); + + if (val & 0x04000) + CAM_INFO(CAM_ISP, "STATS TINTLESS BG ccif violation"); + + if (val & 0x08000) + CAM_INFO(CAM_ISP, "STATS AWB BG ccif violation"); + + if (val & 0x010000) + CAM_INFO(CAM_ISP, "STATS BHIST ccif violation"); + + if (val & 0x020000) + CAM_INFO(CAM_ISP, "STATS RS ccif violation"); + + if (val & 0x040000) + CAM_INFO(CAM_ISP, "STATS CS ccif violation"); + + if (val & 0x080000) + CAM_INFO(CAM_ISP, "STATS IHIST ccif violation"); + + if (val & 0x0100000) + CAM_INFO(CAM_ISP, "STATS BAF ccif violation"); + + if (val & 0x0200000) + CAM_INFO(CAM_ISP, "PD ccif violation"); + + if (val & 0x0400000) + CAM_INFO(CAM_ISP, "LCR ccif violation"); + + if (val & 0x0800000) + CAM_INFO(CAM_ISP, "RDI 0 ccif violation"); + + if (val & 0x01000000) + CAM_INFO(CAM_ISP, "RDI 1 ccif violation"); + + if (val & 0x02000000) + CAM_INFO(CAM_ISP, "RDI 2 ccif violation"); + + } + +end: + cam_vfe_bus_ver3_put_evt_payload(common_data, &evt_payload); + + evt_info.hw_idx = common_data->core_index; + evt_info.res_type = CAM_ISP_RESOURCE_VFE_OUT; + evt_info.res_id = CAM_VFE_BUS_VER3_VFE_OUT_MAX; + evt_info.err_type = CAM_VFE_IRQ_STATUS_VIOLATION; + + if (common_data->event_cb) + common_data->event_cb(NULL, CAM_ISP_HW_EVENT_ERROR, + (void *)&evt_info); + return 0; +} + +static void cam_vfe_bus_ver3_update_ubwc_meta_addr( + uint32_t *reg_val_pair, + uint32_t *j, + void *regs, + uint64_t image_buf) +{ + struct cam_vfe_bus_ver3_reg_offset_ubwc_client *ubwc_regs; + + if (!regs || !reg_val_pair || !j) { + CAM_ERR(CAM_ISP, "Invalid args"); + goto end; + } + + ubwc_regs = (struct cam_vfe_bus_ver3_reg_offset_ubwc_client *)regs; + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->meta_addr, image_buf); + +end: + return; +} + +static int cam_vfe_bus_ver3_update_ubwc_regs( + struct cam_vfe_bus_ver3_wm_resource_data *wm_data, + uint32_t *reg_val_pair, uint32_t i, uint32_t *j) +{ + struct cam_vfe_bus_ver3_reg_offset_ubwc_client *ubwc_regs; + int rc = 0; + + if (!wm_data || !reg_val_pair || !j) { + CAM_ERR(CAM_ISP, "Invalid args"); + rc = -EINVAL; + goto end; + } + + ubwc_regs = (struct cam_vfe_bus_ver3_reg_offset_ubwc_client *) + wm_data->hw_regs->ubwc_regs; + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + wm_data->hw_regs->packer_cfg, wm_data->packer_cfg); + CAM_DBG(CAM_ISP, "WM:%d packer cfg 0x%X", + wm_data->index, reg_val_pair[*j-1]); + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->meta_cfg, wm_data->ubwc_meta_cfg); + CAM_DBG(CAM_ISP, "WM:%d meta stride 0x%X", + wm_data->index, reg_val_pair[*j-1]); + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->mode_cfg, wm_data->ubwc_mode_cfg); + CAM_DBG(CAM_ISP, "WM:%d ubwc_mode_cfg 0x%X", + wm_data->index, reg_val_pair[*j-1]); + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->ctrl_2, wm_data->ubwc_ctrl_2); + CAM_DBG(CAM_ISP, "WM:%d ubwc_ctrl_2 0x%X", + wm_data->index, reg_val_pair[*j-1]); + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->lossy_thresh0, wm_data->ubwc_lossy_threshold_0); + CAM_DBG(CAM_ISP, "WM:%d lossy_thresh0 0x%X", + wm_data->index, reg_val_pair[*j-1]); + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->lossy_thresh1, wm_data->ubwc_lossy_threshold_1); + CAM_DBG(CAM_ISP, "WM:%d lossy_thresh1 0x%X", + wm_data->index, reg_val_pair[*j-1]); + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->off_lossy_var, wm_data->ubwc_offset_lossy_variance); + CAM_DBG(CAM_ISP, "WM:%d off_lossy_var 0x%X", + wm_data->index, reg_val_pair[*j-1]); + + if (wm_data->ubwc_bandwidth_limit) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j, + ubwc_regs->bw_limit, wm_data->ubwc_bandwidth_limit); + CAM_DBG(CAM_ISP, "WM:%d ubwc bw limit 0x%X", + wm_data->index, wm_data->ubwc_bandwidth_limit); + } + +end: + return rc; +} + +static int cam_vfe_bus_ver3_update_wm(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_vfe_bus_ver3_priv *bus_priv; + struct cam_isp_hw_get_cmd_update *update_buf; + struct cam_buf_io_cfg *io_cfg; + struct cam_vfe_bus_ver3_vfe_out_data *vfe_out_data = NULL; + struct cam_vfe_bus_ver3_wm_resource_data *wm_data = NULL; + struct cam_vfe_bus_ver3_reg_offset_ubwc_client *ubwc_client = NULL; + uint32_t *reg_val_pair; + uint32_t i, j, k, size = 0; + uint32_t frame_inc = 0, val; + uint32_t loop_size = 0; + + bus_priv = (struct cam_vfe_bus_ver3_priv *) priv; + update_buf = (struct cam_isp_hw_get_cmd_update *) cmd_args; + + vfe_out_data = (struct cam_vfe_bus_ver3_vfe_out_data *) + update_buf->res->res_priv; + + if (!vfe_out_data || !vfe_out_data->cdm_util_ops) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + if (update_buf->wm_update->num_buf != vfe_out_data->num_wm) { + CAM_ERR(CAM_ISP, + "Failed! Invalid number buffers:%d required:%d", + update_buf->wm_update->num_buf, vfe_out_data->num_wm); + return -EINVAL; + } + + reg_val_pair = &vfe_out_data->common_data->io_buf_update[0]; + io_cfg = update_buf->wm_update->io_cfg; + + for (i = 0, j = 0; i < vfe_out_data->num_wm; i++) { + if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { + CAM_ERR(CAM_ISP, + "reg_val_pair %d exceeds the array limit %zu", + j, MAX_REG_VAL_PAIR_SIZE); + return -ENOMEM; + } + + wm_data = vfe_out_data->wm_res[i]->res_priv; + ubwc_client = wm_data->hw_regs->ubwc_regs; + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->cfg, wm_data->en_cfg); + CAM_DBG(CAM_ISP, "WM:%d en_cfg 0x%X", + wm_data->index, reg_val_pair[j-1]); + + val = (wm_data->height << 16) | wm_data->width; + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_cfg_0, val); + CAM_DBG(CAM_ISP, "WM:%d image height and width 0x%X", + wm_data->index, reg_val_pair[j-1]); + + /* For initial configuration program all bus registers */ + val = io_cfg->planes[i].plane_stride; + CAM_DBG(CAM_ISP, "before stride %d", val); + val = ALIGNUP(val, 16); + if (val != io_cfg->planes[i].plane_stride && + val != wm_data->stride) + CAM_WARN(CAM_ISP, "Warning stride %u expected %u", + io_cfg->planes[i].plane_stride, val); + + if (wm_data->stride != val || !wm_data->init_cfg_done) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_cfg_2, + io_cfg->planes[i].plane_stride); + wm_data->stride = val; + CAM_DBG(CAM_ISP, "WM:%d image stride 0x%X", + wm_data->index, reg_val_pair[j-1]); + } + + if (wm_data->en_ubwc) { + if (!wm_data->hw_regs->ubwc_regs) { + CAM_ERR(CAM_ISP, + "No UBWC register to configure."); + return -EINVAL; + } + if (wm_data->ubwc_updated) { + wm_data->ubwc_updated = false; + cam_vfe_bus_ver3_update_ubwc_regs( + wm_data, reg_val_pair, i, &j); + } + + /* UBWC meta address */ + cam_vfe_bus_ver3_update_ubwc_meta_addr( + reg_val_pair, &j, + wm_data->hw_regs->ubwc_regs, + update_buf->wm_update->image_buf[i]); + CAM_DBG(CAM_ISP, "WM:%d ubwc meta addr 0x%llx", + wm_data->index, + update_buf->wm_update->image_buf[i]); + } + + if (wm_data->en_ubwc) { + frame_inc = ALIGNUP(io_cfg->planes[i].plane_stride * + io_cfg->planes[i].slice_height, 4096); + frame_inc += io_cfg->planes[i].meta_size; + CAM_DBG(CAM_ISP, + "WM:%d frm %d: ht: %d stride %d meta: %d", + wm_data->index, frame_inc, + io_cfg->planes[i].slice_height, + io_cfg->planes[i].plane_stride, + io_cfg->planes[i].meta_size); + } else { + frame_inc = io_cfg->planes[i].plane_stride * + io_cfg->planes[i].slice_height; + } + + if (!(wm_data->en_cfg & (0x3 << 16))) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_cfg_1, wm_data->h_init); + CAM_DBG(CAM_ISP, "WM:%d h_init 0x%X", + wm_data->index, reg_val_pair[j-1]); + } + + if ((!bus_priv->common_data.is_lite && wm_data->index > 22) || + bus_priv->common_data.is_lite) + loop_size = wm_data->irq_subsample_period + 1; + else + loop_size = 1; + + /* WM Image address */ + for (k = 0; k < loop_size; k++) { + if (wm_data->en_ubwc) + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_addr, + update_buf->wm_update->image_buf[i] + + io_cfg->planes[i].meta_size + + k * frame_inc); + else if (wm_data->en_cfg & (0x3 << 16)) + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_addr, + (update_buf->wm_update->image_buf[i] + + wm_data->offset + k * frame_inc)); + else + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_addr, + (update_buf->wm_update->image_buf[i] + + k * frame_inc)); + + CAM_DBG(CAM_ISP, "WM:%d image address 0x%X", + wm_data->index, reg_val_pair[j-1]); + } + + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->frame_incr, frame_inc); + CAM_DBG(CAM_ISP, "WM:%d frame_inc %d", + wm_data->index, reg_val_pair[j-1]); + + + /* enable the WM */ + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->cfg, + wm_data->en_cfg); + + /* set initial configuration done */ + if (!wm_data->init_cfg_done) + wm_data->init_cfg_done = true; + } + + size = vfe_out_data->cdm_util_ops->cdm_required_size_reg_random(j/2); + + /* cdm util returns dwords, need to convert to bytes */ + if ((size * 4) > update_buf->cmd.size) { + CAM_ERR(CAM_ISP, + "Failed! Buf size:%d insufficient, expected size:%d", + update_buf->cmd.size, size); + return -ENOMEM; + } + + vfe_out_data->cdm_util_ops->cdm_write_regrandom( + update_buf->cmd.cmd_buf_addr, j/2, reg_val_pair); + + /* cdm util returns dwords, need to convert to bytes */ + update_buf->cmd.used_bytes = size * 4; + + return 0; +} + +static int cam_vfe_bus_ver3_update_hfr(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_vfe_bus_ver3_priv *bus_priv; + struct cam_isp_hw_get_cmd_update *update_hfr; + struct cam_vfe_bus_ver3_vfe_out_data *vfe_out_data = NULL; + struct cam_vfe_bus_ver3_wm_resource_data *wm_data = NULL; + struct cam_isp_port_hfr_config *hfr_cfg = NULL; + uint32_t *reg_val_pair; + uint32_t i, j, size = 0; + + bus_priv = (struct cam_vfe_bus_ver3_priv *) priv; + update_hfr = (struct cam_isp_hw_get_cmd_update *) cmd_args; + + vfe_out_data = (struct cam_vfe_bus_ver3_vfe_out_data *) + update_hfr->res->res_priv; + + if (!vfe_out_data || !vfe_out_data->cdm_util_ops) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + reg_val_pair = &vfe_out_data->common_data->io_buf_update[0]; + hfr_cfg = (struct cam_isp_port_hfr_config *)update_hfr->data; + + for (i = 0, j = 0; i < vfe_out_data->num_wm; i++) { + if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { + CAM_ERR(CAM_ISP, + "reg_val_pair %d exceeds the array limit %zu", + j, MAX_REG_VAL_PAIR_SIZE); + return -ENOMEM; + } + + wm_data = vfe_out_data->wm_res[i]->res_priv; + + if (((!bus_priv->common_data.is_lite && wm_data->index > 22) || + bus_priv->common_data.is_lite) && + hfr_cfg->subsample_period > 3) { + CAM_ERR(CAM_ISP, + "RDI doesn't support irq subsample period %d", + hfr_cfg->subsample_period); + return -EINVAL; + } + + if ((wm_data->framedrop_pattern != + hfr_cfg->framedrop_pattern) || + !wm_data->hfr_cfg_done) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->framedrop_pattern, + hfr_cfg->framedrop_pattern); + wm_data->framedrop_pattern = hfr_cfg->framedrop_pattern; + CAM_DBG(CAM_ISP, "WM:%d framedrop pattern 0x%X", + wm_data->index, wm_data->framedrop_pattern); + } + + if (wm_data->framedrop_period != hfr_cfg->framedrop_period || + !wm_data->hfr_cfg_done) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->framedrop_period, + hfr_cfg->framedrop_period); + wm_data->framedrop_period = hfr_cfg->framedrop_period; + CAM_DBG(CAM_ISP, "WM:%d framedrop period 0x%X", + wm_data->index, wm_data->framedrop_period); + } + + if (wm_data->irq_subsample_period != hfr_cfg->subsample_period + || !wm_data->hfr_cfg_done) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->irq_subsample_period, + hfr_cfg->subsample_period); + wm_data->irq_subsample_period = + hfr_cfg->subsample_period; + CAM_DBG(CAM_ISP, "WM:%d irq subsample period 0x%X", + wm_data->index, wm_data->irq_subsample_period); + } + + if (wm_data->irq_subsample_pattern != hfr_cfg->subsample_pattern + || !wm_data->hfr_cfg_done) { + CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->irq_subsample_pattern, + hfr_cfg->subsample_pattern); + wm_data->irq_subsample_pattern = + hfr_cfg->subsample_pattern; + CAM_DBG(CAM_ISP, "WM:%d irq subsample pattern 0x%X", + wm_data->index, wm_data->irq_subsample_pattern); + } + + /* set initial configuration done */ + if (!wm_data->hfr_cfg_done) + wm_data->hfr_cfg_done = true; + } + + size = vfe_out_data->cdm_util_ops->cdm_required_size_reg_random(j/2); + + /* cdm util returns dwords, need to convert to bytes */ + if ((size * 4) > update_hfr->cmd.size) { + CAM_ERR(CAM_ISP, + "Failed! Buf size:%d insufficient, expected size:%d", + update_hfr->cmd.size, size); + return -ENOMEM; + } + + vfe_out_data->cdm_util_ops->cdm_write_regrandom( + update_hfr->cmd.cmd_buf_addr, j/2, reg_val_pair); + + /* cdm util returns dwords, need to convert to bytes */ + update_hfr->cmd.used_bytes = size * 4; + + return 0; +} + +static int cam_vfe_bus_ver3_update_ubwc_config_v2(void *cmd_args) +{ + struct cam_isp_hw_get_cmd_update *update_ubwc; + struct cam_vfe_bus_ver3_vfe_out_data *vfe_out_data = NULL; + struct cam_vfe_bus_ver3_wm_resource_data *wm_data = NULL; + struct cam_vfe_generic_ubwc_config *ubwc_generic_cfg = NULL; + struct cam_vfe_generic_ubwc_plane_config *ubwc_generic_plane_cfg = NULL; + uint32_t i; + int rc = 0; + + if (!cmd_args) { + CAM_ERR(CAM_ISP, "Invalid args"); + rc = -EINVAL; + goto end; + } + + update_ubwc = (struct cam_isp_hw_get_cmd_update *) cmd_args; + + vfe_out_data = (struct cam_vfe_bus_ver3_vfe_out_data *) + update_ubwc->res->res_priv; + + if (!vfe_out_data || !vfe_out_data->cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid data"); + rc = -EINVAL; + goto end; + } + + ubwc_generic_cfg = (struct cam_vfe_generic_ubwc_config *) + update_ubwc->data; + + for (i = 0; i < vfe_out_data->num_wm; i++) { + + wm_data = vfe_out_data->wm_res[i]->res_priv; + ubwc_generic_plane_cfg = &ubwc_generic_cfg->ubwc_plane_cfg[i]; + + if (!wm_data->hw_regs->ubwc_regs) { + CAM_ERR(CAM_ISP, + "No UBWC register to configure."); + rc = -EINVAL; + goto end; + } + + if (!wm_data->en_ubwc) { + CAM_ERR(CAM_ISP, "UBWC Disabled"); + rc = -EINVAL; + goto end; + } + + if (wm_data->packer_cfg != + ubwc_generic_plane_cfg->packer_config || + !wm_data->init_cfg_done) { + wm_data->packer_cfg = + ubwc_generic_plane_cfg->packer_config; + wm_data->ubwc_updated = true; + } + + if ((!wm_data->is_dual) && ((wm_data->h_init != + ubwc_generic_plane_cfg->h_init) || + !wm_data->init_cfg_done)) { + wm_data->h_init = ubwc_generic_plane_cfg->h_init; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_meta_cfg != + ubwc_generic_plane_cfg->meta_stride || + !wm_data->init_cfg_done) { + wm_data->ubwc_meta_cfg = + ubwc_generic_plane_cfg->meta_stride; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_mode_cfg != + ubwc_generic_plane_cfg->mode_config_0 || + !wm_data->init_cfg_done) { + wm_data->ubwc_mode_cfg = + ubwc_generic_plane_cfg->mode_config_0; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_ctrl_2 != + ubwc_generic_plane_cfg->ctrl_2 || + !wm_data->init_cfg_done) { + wm_data->ubwc_ctrl_2 = + ubwc_generic_plane_cfg->ctrl_2; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_lossy_threshold_0 != + ubwc_generic_plane_cfg->lossy_threshold_0 || + !wm_data->init_cfg_done) { + wm_data->ubwc_lossy_threshold_0 = + ubwc_generic_plane_cfg->lossy_threshold_0; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_lossy_threshold_1 != + ubwc_generic_plane_cfg->lossy_threshold_1 || + !wm_data->init_cfg_done) { + wm_data->ubwc_lossy_threshold_1 = + ubwc_generic_plane_cfg->lossy_threshold_1; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_offset_lossy_variance != + ubwc_generic_plane_cfg->lossy_var_offset || + !wm_data->init_cfg_done) { + wm_data->ubwc_offset_lossy_variance = + ubwc_generic_plane_cfg->lossy_var_offset; + wm_data->ubwc_updated = true; + } + + if (wm_data->ubwc_bandwidth_limit != + ubwc_generic_plane_cfg->bandwidth_limit || + !wm_data->init_cfg_done) { + wm_data->ubwc_bandwidth_limit = + ubwc_generic_plane_cfg->bandwidth_limit; + wm_data->ubwc_updated = true; + } + } + +end: + return rc; +} + +static int cam_vfe_bus_ver3_update_stripe_cfg(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_vfe_bus_ver3_priv *bus_priv; + struct cam_isp_hw_dual_isp_update_args *stripe_args; + struct cam_vfe_bus_ver3_vfe_out_data *vfe_out_data = NULL; + struct cam_vfe_bus_ver3_wm_resource_data *wm_data = NULL; + struct cam_isp_dual_stripe_config *stripe_config; + uint32_t outport_id, ports_plane_idx, i; + + bus_priv = (struct cam_vfe_bus_ver3_priv *) priv; + stripe_args = (struct cam_isp_hw_dual_isp_update_args *)cmd_args; + + vfe_out_data = (struct cam_vfe_bus_ver3_vfe_out_data *) + stripe_args->res->res_priv; + + if (!vfe_out_data) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + outport_id = stripe_args->res->res_id & 0xFF; + if (stripe_args->res->res_id < CAM_ISP_IFE_OUT_RES_BASE || + stripe_args->res->res_id >= CAM_ISP_IFE_OUT_RES_MAX) + return 0; + + ports_plane_idx = (stripe_args->split_id * + (stripe_args->dual_cfg->num_ports * CAM_PACKET_MAX_PLANES)) + + (outport_id * CAM_PACKET_MAX_PLANES); + for (i = 0; i < vfe_out_data->num_wm; i++) { + wm_data = vfe_out_data->wm_res[i]->res_priv; + stripe_config = (struct cam_isp_dual_stripe_config *) + &stripe_args->dual_cfg->stripes[ports_plane_idx + i]; + wm_data->width = stripe_config->width; + + /* + * UMD sends buffer offset address as offset for clients + * programmed to operate in frame/index based mode and h_init + * value as offset for clients programmed to operate in line + * based mode. + */ + + if (wm_data->en_cfg & (0x3 << 16)) + wm_data->offset = stripe_config->offset; + else + wm_data->h_init = stripe_config->offset; + + CAM_DBG(CAM_ISP, + "out_type:0x%X WM:%d width:%d offset:0x%X h_init:%d", + stripe_args->res->res_id, wm_data->index, + wm_data->width, wm_data->offset, wm_data->h_init); + } + + return 0; +} + +static int cam_vfe_bus_ver3_update_wm_config( + void *cmd_args) +{ + int i; + struct cam_isp_hw_get_cmd_update *wm_config_update; + struct cam_vfe_bus_ver3_vfe_out_data *vfe_out_data = NULL; + struct cam_vfe_bus_ver3_wm_resource_data *wm_data = NULL; + struct cam_isp_vfe_wm_config *wm_config = NULL; + + if (!cmd_args) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + wm_config_update = cmd_args; + vfe_out_data = wm_config_update->res->res_priv; + wm_config = (struct cam_isp_vfe_wm_config *) + wm_config_update->data; + + if (!vfe_out_data || !vfe_out_data->cdm_util_ops || !wm_config) { + CAM_ERR(CAM_ISP, "Invalid data"); + return -EINVAL; + } + + for (i = 0; i < vfe_out_data->num_wm; i++) { + wm_data = vfe_out_data->wm_res[i]->res_priv; + + if (wm_config->wm_mode > 0x2) { + CAM_ERR(CAM_ISP, "Invalid wm_mode: 0x%X WM:%d", + wm_config->wm_mode, wm_data->index); + return -EINVAL; + } + + wm_data->en_cfg = (wm_config->wm_mode << 16) | 0x1; + wm_data->height = wm_config->height; + wm_data->width = wm_config->width; + + CAM_DBG(CAM_ISP, + "WM:%d en_cfg:0x%X height:%d width:%d", + wm_data->index, wm_data->en_cfg, wm_data->height, + wm_data->width); + } + + return 0; +} + +static int cam_vfe_bus_ver3_start_hw(void *hw_priv, + void *start_hw_args, uint32_t arg_size) +{ + return cam_vfe_bus_ver3_start_vfe_out(hw_priv); +} + +static int cam_vfe_bus_ver3_stop_hw(void *hw_priv, + void *stop_hw_args, uint32_t arg_size) +{ + return cam_vfe_bus_ver3_stop_vfe_out(hw_priv); +} + +static int cam_vfe_bus_ver3_init_hw(void *hw_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_vfe_bus_ver3_priv *bus_priv = hw_priv; + uint32_t top_irq_reg_mask[3] = {0}; + + if (!bus_priv) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + if (bus_priv->common_data.hw_init) + return 0; + + top_irq_reg_mask[0] = (1 << bus_priv->top_irq_shift); + + bus_priv->bus_irq_handle = cam_irq_controller_subscribe_irq( + bus_priv->common_data.vfe_irq_controller, + CAM_IRQ_PRIORITY_4, + top_irq_reg_mask, + bus_priv, + cam_vfe_bus_ver3_handle_bus_irq, + NULL, + NULL, + NULL); + + if (bus_priv->bus_irq_handle < 1) { + CAM_ERR(CAM_ISP, "Failed to subscribe BUS (buf_done) IRQ"); + bus_priv->bus_irq_handle = 0; + return -EFAULT; + } + + bus_priv->rup_irq_handle = cam_irq_controller_subscribe_irq( + bus_priv->common_data.vfe_irq_controller, + CAM_IRQ_PRIORITY_2, + top_irq_reg_mask, + bus_priv, + cam_vfe_bus_ver3_handle_rup_irq, + NULL, + NULL, + NULL); + + if (bus_priv->rup_irq_handle < 1) { + CAM_ERR(CAM_ISP, "Failed to subscribe BUS (rup) IRQ"); + bus_priv->rup_irq_handle = 0; + return -EFAULT; + } + + if (bus_priv->tasklet_info != NULL) { + bus_priv->error_irq_handle = cam_irq_controller_subscribe_irq( + bus_priv->common_data.bus_irq_controller, + CAM_IRQ_PRIORITY_0, + bus_error_irq_mask, + bus_priv, + cam_vfe_bus_ver3_err_irq_top_half, + cam_vfe_bus_ver3_err_irq_bottom_half, + bus_priv->tasklet_info, + &tasklet_bh_api); + + if (bus_priv->error_irq_handle < 1) { + CAM_ERR(CAM_ISP, "Failed to subscribe BUS Error IRQ"); + bus_priv->error_irq_handle = 0; + return -EFAULT; + } + } + + /* no clock gating at bus input */ + CAM_INFO(CAM_ISP, "Overriding clock gating at bus input"); + cam_io_w_mb(0x3FFFFFF, bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->cgc_ovd); + + /* BUS_WR_TEST_BUS_CTRL */ + cam_io_w_mb(0x0, bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->test_bus_ctrl); + + bus_priv->common_data.hw_init = true; + + return 0; +} + +static int cam_vfe_bus_ver3_deinit_hw(void *hw_priv, + void *deinit_hw_args, uint32_t arg_size) +{ + struct cam_vfe_bus_ver3_priv *bus_priv = hw_priv; + int rc = 0, i; + unsigned long flags; + + if (!bus_priv) { + CAM_ERR(CAM_ISP, "Error: Invalid args"); + return -EINVAL; + } + + if (!bus_priv->common_data.hw_init) + return 0; + + if (bus_priv->error_irq_handle) { + rc = cam_irq_controller_unsubscribe_irq( + bus_priv->common_data.bus_irq_controller, + bus_priv->error_irq_handle); + bus_priv->error_irq_handle = 0; + } + + if (bus_priv->bus_irq_handle) { + rc = cam_irq_controller_unsubscribe_irq( + bus_priv->common_data.vfe_irq_controller, + bus_priv->bus_irq_handle); + bus_priv->bus_irq_handle = 0; + } + + if (bus_priv->rup_irq_handle) { + rc = cam_irq_controller_unsubscribe_irq( + bus_priv->common_data.vfe_irq_controller, + bus_priv->rup_irq_handle); + bus_priv->rup_irq_handle = 0; + } + + spin_lock_irqsave(&bus_priv->common_data.spin_lock, flags); + INIT_LIST_HEAD(&bus_priv->common_data.free_payload_list); + for (i = 0; i < CAM_VFE_BUS_VER3_PAYLOAD_MAX; i++) { + INIT_LIST_HEAD(&bus_priv->common_data.evt_payload[i].list); + list_add_tail(&bus_priv->common_data.evt_payload[i].list, + &bus_priv->common_data.free_payload_list); + } + bus_priv->common_data.hw_init = false; + spin_unlock_irqrestore(&bus_priv->common_data.spin_lock, flags); + + return rc; +} + +static int __cam_vfe_bus_ver3_process_cmd(void *priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + return cam_vfe_bus_ver3_process_cmd(priv, cmd_type, cmd_args, arg_size); +} + +static int cam_vfe_bus_ver3_process_cmd( + struct cam_isp_resource_node *priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = -EINVAL; + struct cam_vfe_bus_ver3_priv *bus_priv; + + if (!priv || !cmd_args) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_BUF_UPDATE: + rc = cam_vfe_bus_ver3_update_wm(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_GET_HFR_UPDATE: + rc = cam_vfe_bus_ver3_update_hfr(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_GET_SECURE_MODE: + rc = cam_vfe_bus_ver3_get_secure_mode(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_STRIPE_UPDATE: + rc = cam_vfe_bus_ver3_update_stripe_cfg(priv, + cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ: + bus_priv = (struct cam_vfe_bus_ver3_priv *) priv; + if (bus_priv->error_irq_handle) { + CAM_DBG(CAM_ISP, "Mask off bus error irq handler"); + rc = cam_irq_controller_unsubscribe_irq( + bus_priv->common_data.bus_irq_controller, + bus_priv->error_irq_handle); + bus_priv->error_irq_handle = 0; + } + break; + case CAM_ISP_HW_CMD_UBWC_UPDATE_V2: + rc = cam_vfe_bus_ver3_update_ubwc_config_v2(cmd_args); + break; + case CAM_ISP_HW_CMD_WM_CONFIG_UPDATE: + rc = cam_vfe_bus_ver3_update_wm_config(cmd_args); + break; + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid camif process command:%d", + cmd_type); + break; + } + + return rc; +} + +int cam_vfe_bus_ver3_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *bus_hw_info, + void *vfe_irq_controller, + struct cam_vfe_bus **vfe_bus) +{ + int i, rc = 0; + struct cam_vfe_bus_ver3_priv *bus_priv = NULL; + struct cam_vfe_bus *vfe_bus_local; + struct cam_vfe_bus_ver3_hw_info *ver3_hw_info = bus_hw_info; + struct cam_vfe_soc_private *soc_private = NULL; + + CAM_DBG(CAM_ISP, "Enter"); + + if (!soc_info || !hw_intf || !bus_hw_info || !vfe_irq_controller) { + CAM_ERR(CAM_ISP, + "Inval_prms soc_info:%pK hw_intf:%pK hw_info%pK", + soc_info, hw_intf, bus_hw_info); + CAM_ERR(CAM_ISP, "controller: %pK", vfe_irq_controller); + rc = -EINVAL; + goto end; + } + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Invalid soc_private"); + rc = -ENODEV; + goto end; + } + + vfe_bus_local = kzalloc(sizeof(struct cam_vfe_bus), GFP_KERNEL); + if (!vfe_bus_local) { + CAM_DBG(CAM_ISP, "Failed to alloc for vfe_bus"); + rc = -ENOMEM; + goto end; + } + + bus_priv = kzalloc(sizeof(struct cam_vfe_bus_ver3_priv), + GFP_KERNEL); + if (!bus_priv) { + CAM_DBG(CAM_ISP, "Failed to alloc for vfe_bus_priv"); + rc = -ENOMEM; + goto free_bus_local; + } + vfe_bus_local->bus_priv = bus_priv; + + bus_priv->num_client = ver3_hw_info->num_client; + bus_priv->num_out = ver3_hw_info->num_out; + bus_priv->top_irq_shift = ver3_hw_info->top_irq_shift; + bus_priv->common_data.num_sec_out = 0; + bus_priv->common_data.secure_mode = CAM_SECURE_MODE_NON_SECURE; + bus_priv->common_data.core_index = soc_info->index; + bus_priv->common_data.mem_base = + CAM_SOC_GET_REG_MAP_START(soc_info, VFE_CORE_BASE_IDX); + bus_priv->common_data.hw_intf = hw_intf; + bus_priv->common_data.vfe_irq_controller = vfe_irq_controller; + bus_priv->common_data.common_reg = &ver3_hw_info->common_reg; + bus_priv->common_data.comp_done_shift = + ver3_hw_info->comp_done_shift; + bus_priv->common_data.hw_init = false; + + bus_priv->common_data.is_lite = soc_private->is_ife_lite; + + for (i = 0; i < CAM_VFE_BUS_VER3_SRC_GRP_MAX; i++) + bus_priv->common_data.rup_irq_handle[i] = 0; + + mutex_init(&bus_priv->common_data.bus_mutex); + + rc = cam_irq_controller_init(drv_name, bus_priv->common_data.mem_base, + &ver3_hw_info->common_reg.irq_reg_info, + &bus_priv->common_data.bus_irq_controller, false); + if (rc) { + CAM_ERR(CAM_ISP, "Init bus_irq_controller failed"); + goto free_bus_priv; + } + + strlcat(rup_controller_name, drv_name, sizeof(rup_controller_name)); + strlcat(rup_controller_name, "_rup", sizeof(rup_controller_name)); + + rc = cam_irq_controller_init(rup_controller_name, + bus_priv->common_data.mem_base, + &ver3_hw_info->common_reg.irq_reg_info, + &bus_priv->common_data.rup_irq_controller, false); + if (rc) { + CAM_ERR(CAM_ISP, "Init rup_irq_controller failed"); + goto free_bus_priv; + } + + INIT_LIST_HEAD(&bus_priv->free_comp_grp); + INIT_LIST_HEAD(&bus_priv->used_comp_grp); + + for (i = 0; i < bus_priv->num_client; i++) { + rc = cam_vfe_bus_ver3_init_wm_resource(i, bus_priv, bus_hw_info, + &bus_priv->bus_client[i]); + if (rc < 0) { + CAM_ERR(CAM_ISP, "VFE:%d init WM:%d failed rc:%d", + bus_priv->common_data.core_index, i, rc); + goto deinit_wm; + } + } + + for (i = 0; i < CAM_VFE_BUS_VER3_COMP_GRP_MAX; i++) { + rc = cam_vfe_bus_ver3_init_comp_grp(i, soc_info, + bus_priv, bus_hw_info, + &bus_priv->comp_grp[i]); + if (rc < 0) { + CAM_ERR(CAM_ISP, "VFE:%d init comp_grp:%d failed rc:%d", + bus_priv->common_data.core_index, i, rc); + goto deinit_comp_grp; + } + } + + for (i = 0; i < bus_priv->num_out; i++) { + rc = cam_vfe_bus_ver3_init_vfe_out_resource(i, bus_priv, + bus_hw_info); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "VFE:%d init out_type:0x%X failed rc:%d", + bus_priv->common_data.core_index, i, rc); + goto deinit_vfe_out; + } + } + + spin_lock_init(&bus_priv->common_data.spin_lock); + INIT_LIST_HEAD(&bus_priv->common_data.free_payload_list); + for (i = 0; i < CAM_VFE_BUS_VER3_PAYLOAD_MAX; i++) { + INIT_LIST_HEAD(&bus_priv->common_data.evt_payload[i].list); + list_add_tail(&bus_priv->common_data.evt_payload[i].list, + &bus_priv->common_data.free_payload_list); + } + + vfe_bus_local->hw_ops.reserve = cam_vfe_bus_ver3_acquire_vfe_out; + vfe_bus_local->hw_ops.release = cam_vfe_bus_ver3_release_vfe_out; + vfe_bus_local->hw_ops.start = cam_vfe_bus_ver3_start_hw; + vfe_bus_local->hw_ops.stop = cam_vfe_bus_ver3_stop_hw; + vfe_bus_local->hw_ops.init = cam_vfe_bus_ver3_init_hw; + vfe_bus_local->hw_ops.deinit = cam_vfe_bus_ver3_deinit_hw; + vfe_bus_local->top_half_handler = NULL; + vfe_bus_local->bottom_half_handler = NULL; + vfe_bus_local->hw_ops.process_cmd = __cam_vfe_bus_ver3_process_cmd; + + *vfe_bus = vfe_bus_local; + + CAM_DBG(CAM_ISP, "Exit"); + return rc; + +deinit_vfe_out: + if (i < 0) + i = CAM_VFE_BUS_VER3_VFE_OUT_MAX; + for (--i; i >= 0; i--) + cam_vfe_bus_ver3_deinit_vfe_out_resource(&bus_priv->vfe_out[i]); + +deinit_comp_grp: + if (i < 0) + i = CAM_VFE_BUS_VER3_COMP_GRP_MAX; + for (--i; i >= 0; i--) + cam_vfe_bus_ver3_deinit_comp_grp(&bus_priv->comp_grp[i]); + +deinit_wm: + if (i < 0) + i = bus_priv->num_client; + for (--i; i >= 0; i--) + cam_vfe_bus_ver3_deinit_wm_resource(&bus_priv->bus_client[i]); + +free_bus_priv: + kfree(vfe_bus_local->bus_priv); + +free_bus_local: + kfree(vfe_bus_local); + +end: + return rc; +} + +int cam_vfe_bus_ver3_deinit( + struct cam_vfe_bus **vfe_bus) +{ + int i, rc = 0; + struct cam_vfe_bus_ver3_priv *bus_priv = NULL; + struct cam_vfe_bus *vfe_bus_local; + unsigned long flags; + + if (!vfe_bus || !*vfe_bus) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + vfe_bus_local = *vfe_bus; + + bus_priv = vfe_bus_local->bus_priv; + if (!bus_priv) { + CAM_ERR(CAM_ISP, "bus_priv is NULL"); + rc = -ENODEV; + goto free_bus_local; + } + + spin_lock_irqsave(&bus_priv->common_data.spin_lock, flags); + INIT_LIST_HEAD(&bus_priv->common_data.free_payload_list); + for (i = 0; i < CAM_VFE_BUS_VER3_PAYLOAD_MAX; i++) + INIT_LIST_HEAD(&bus_priv->common_data.evt_payload[i].list); + bus_priv->common_data.hw_init = false; + spin_unlock_irqrestore(&bus_priv->common_data.spin_lock, flags); + + for (i = 0; i < bus_priv->num_client; i++) { + rc = cam_vfe_bus_ver3_deinit_wm_resource( + &bus_priv->bus_client[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "VFE:%d deinit WM:%d failed rc:%d", + bus_priv->common_data.core_index, i, rc); + } + + for (i = 0; i < CAM_VFE_BUS_VER3_COMP_GRP_MAX; i++) { + rc = cam_vfe_bus_ver3_deinit_comp_grp(&bus_priv->comp_grp[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "VFE:%d deinit comp_grp:%d failed rc:%d", + bus_priv->common_data.core_index, i, rc); + } + + for (i = 0; i < CAM_VFE_BUS_VER3_VFE_OUT_MAX; i++) { + rc = cam_vfe_bus_ver3_deinit_vfe_out_resource( + &bus_priv->vfe_out[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "VFE:%d deinit out_type:0x%X failed rc:%d", + bus_priv->common_data.core_index, i, rc); + } + + INIT_LIST_HEAD(&bus_priv->free_comp_grp); + INIT_LIST_HEAD(&bus_priv->used_comp_grp); + + rc = cam_irq_controller_deinit( + &bus_priv->common_data.bus_irq_controller); + if (rc) + CAM_ERR(CAM_ISP, + "Deinit BUS IRQ Controller failed rc=%d", rc); + + rc = cam_irq_controller_deinit( + &bus_priv->common_data.rup_irq_controller); + if (rc) + CAM_ERR(CAM_ISP, + "Deinit RUP IRQ Controller failed rc=%d", rc); + + mutex_destroy(&bus_priv->common_data.bus_mutex); + kfree(vfe_bus_local->bus_priv); + +free_bus_local: + kfree(vfe_bus_local); + + *vfe_bus = NULL; + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.h new file mode 100644 index 0000000000000000000000000000000000000000..c5b4ab69fa9f503b03e9e074d2421aa737e4738f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.h @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + + +#ifndef _CAM_VFE_BUS_VER3_H_ +#define _CAM_VFE_BUS_VER3_H_ + +#include "cam_irq_controller.h" +#include "cam_vfe_bus.h" + +#define CAM_VFE_BUS_VER3_MAX_CLIENTS 26 +#define CAM_VFE_BUS_VER3_MAX_SUB_GRPS 6 + +enum cam_vfe_bus_ver3_vfe_core_id { + CAM_VFE_BUS_VER3_VFE_CORE_0, + CAM_VFE_BUS_VER3_VFE_CORE_1, + CAM_VFE_BUS_VER3_VFE_CORE_MAX, +}; + +enum cam_vfe_bus_ver3_src_grp { + CAM_VFE_BUS_VER3_SRC_GRP_0, + CAM_VFE_BUS_VER3_SRC_GRP_1, + CAM_VFE_BUS_VER3_SRC_GRP_2, + CAM_VFE_BUS_VER3_SRC_GRP_3, + CAM_VFE_BUS_VER3_SRC_GRP_4, + CAM_VFE_BUS_VER3_SRC_GRP_5, + CAM_VFE_BUS_VER3_SRC_GRP_MAX, +}; + +enum cam_vfe_bus_ver3_comp_grp_type { + CAM_VFE_BUS_VER3_COMP_GRP_0, + CAM_VFE_BUS_VER3_COMP_GRP_1, + CAM_VFE_BUS_VER3_COMP_GRP_2, + CAM_VFE_BUS_VER3_COMP_GRP_3, + CAM_VFE_BUS_VER3_COMP_GRP_4, + CAM_VFE_BUS_VER3_COMP_GRP_5, + CAM_VFE_BUS_VER3_COMP_GRP_6, + CAM_VFE_BUS_VER3_COMP_GRP_7, + CAM_VFE_BUS_VER3_COMP_GRP_8, + CAM_VFE_BUS_VER3_COMP_GRP_9, + CAM_VFE_BUS_VER3_COMP_GRP_10, + CAM_VFE_BUS_VER3_COMP_GRP_11, + CAM_VFE_BUS_VER3_COMP_GRP_12, + CAM_VFE_BUS_VER3_COMP_GRP_13, + CAM_VFE_BUS_VER3_COMP_GRP_MAX, +}; + +enum cam_vfe_bus_ver3_vfe_out_type { + CAM_VFE_BUS_VER3_VFE_OUT_RDI0, + CAM_VFE_BUS_VER3_VFE_OUT_RDI1, + CAM_VFE_BUS_VER3_VFE_OUT_RDI2, + CAM_VFE_BUS_VER3_VFE_OUT_RDI3, + CAM_VFE_BUS_VER3_VFE_OUT_FULL, + CAM_VFE_BUS_VER3_VFE_OUT_DS4, + CAM_VFE_BUS_VER3_VFE_OUT_DS16, + CAM_VFE_BUS_VER3_VFE_OUT_RAW_DUMP, + CAM_VFE_BUS_VER3_VFE_OUT_FD, + CAM_VFE_BUS_VER3_VFE_OUT_PDAF, + CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BE, + CAM_VFE_BUS_VER3_VFE_OUT_STATS_HDR_BHIST, + CAM_VFE_BUS_VER3_VFE_OUT_STATS_TL_BG, + CAM_VFE_BUS_VER3_VFE_OUT_STATS_BF, + CAM_VFE_BUS_VER3_VFE_OUT_STATS_AWB_BG, + CAM_VFE_BUS_VER3_VFE_OUT_STATS_BHIST, + CAM_VFE_BUS_VER3_VFE_OUT_STATS_RS, + CAM_VFE_BUS_VER3_VFE_OUT_STATS_CS, + CAM_VFE_BUS_VER3_VFE_OUT_STATS_IHIST, + CAM_VFE_BUS_VER3_VFE_OUT_FULL_DISP, + CAM_VFE_BUS_VER3_VFE_OUT_DS4_DISP, + CAM_VFE_BUS_VER3_VFE_OUT_DS16_DISP, + CAM_VFE_BUS_VER3_VFE_OUT_2PD, + CAM_VFE_BUS_VER3_VFE_OUT_LCR, + CAM_VFE_BUS_VER3_VFE_OUT_MAX, +}; + +/* + * struct cam_vfe_bus_ver3_reg_offset_common: + * + * @Brief: Common registers across all BUS Clients + */ +struct cam_vfe_bus_ver3_reg_offset_common { + uint32_t hw_version; + uint32_t cgc_ovd; + uint32_t comp_cfg_0; + uint32_t comp_cfg_1; + uint32_t if_frameheader_cfg[CAM_VFE_BUS_VER3_MAX_SUB_GRPS]; + uint32_t ubwc_static_ctrl; + uint32_t pwr_iso_cfg; + uint32_t overflow_status_clear; + uint32_t ccif_violation_status; + uint32_t overflow_status; + uint32_t image_size_violation_status; + uint32_t debug_status_top_cfg; + uint32_t debug_status_top; + uint32_t test_bus_ctrl; + struct cam_irq_controller_reg_info irq_reg_info; +}; + +/* + * struct cam_vfe_bus_ver3_reg_offset_ubwc_client: + * + * @Brief: UBWC register offsets for BUS Clients + */ +struct cam_vfe_bus_ver3_reg_offset_ubwc_client { + uint32_t meta_addr; + uint32_t meta_cfg; + uint32_t mode_cfg; + uint32_t stats_ctrl; + uint32_t ctrl_2; + uint32_t lossy_thresh0; + uint32_t lossy_thresh1; + uint32_t off_lossy_var; + uint32_t bw_limit; +}; + +/* + * struct cam_vfe_bus_ver3_reg_offset_bus_client: + * + * @Brief: Register offsets for BUS Clients + */ +struct cam_vfe_bus_ver3_reg_offset_bus_client { + uint32_t cfg; + uint32_t image_addr; + uint32_t frame_incr; + uint32_t image_cfg_0; + uint32_t image_cfg_1; + uint32_t image_cfg_2; + uint32_t packer_cfg; + uint32_t frame_header_addr; + uint32_t frame_header_incr; + uint32_t frame_header_cfg; + uint32_t line_done_cfg; + uint32_t irq_subsample_period; + uint32_t irq_subsample_pattern; + uint32_t framedrop_period; + uint32_t framedrop_pattern; + uint32_t burst_limit; + uint32_t system_cache_cfg; + void *ubwc_regs; + uint32_t addr_status_0; + uint32_t addr_status_1; + uint32_t addr_status_2; + uint32_t addr_status_3; + uint32_t debug_status_cfg; + uint32_t debug_status_0; + uint32_t debug_status_1; + uint32_t comp_group; +}; + +/* + * struct cam_vfe_bus_ver3_vfe_out_hw_info: + * + * @Brief: HW capability of VFE Bus Client + */ +struct cam_vfe_bus_ver3_vfe_out_hw_info { + enum cam_vfe_bus_ver3_vfe_out_type vfe_out_type; + uint32_t max_width; + uint32_t max_height; + uint32_t source_group; +}; + +/* + * struct cam_vfe_bus_ver3_hw_info: + * + * @Brief: HW register info for entire Bus + * + * @common_reg: Common register details + * @num_client: Total number of write clients + * @bus_client_reg: Bus client register info + * @vfe_out_hw_info: VFE output capability + * @comp_done_shift: Mask shift for comp done mask + * @top_irq_shift: Mask shift for top level BUS WR irq + */ +struct cam_vfe_bus_ver3_hw_info { + struct cam_vfe_bus_ver3_reg_offset_common common_reg; + uint32_t num_client; + struct cam_vfe_bus_ver3_reg_offset_bus_client + bus_client_reg[CAM_VFE_BUS_VER3_MAX_CLIENTS]; + uint32_t num_out; + struct cam_vfe_bus_ver3_vfe_out_hw_info + vfe_out_hw_info[CAM_VFE_BUS_VER3_VFE_OUT_MAX]; + uint32_t comp_done_shift; + uint32_t top_irq_shift; +}; + +/* + * cam_vfe_bus_ver3_init() + * + * @Brief: Initialize Bus layer + * + * @soc_info: Soc Information for the associated HW + * @hw_intf: HW Interface of HW to which this resource belongs + * @bus_hw_info: BUS HW info that contains details of BUS registers + * @vfe_irq_controller: VFE IRQ Controller to use for subscribing to Top + * level IRQs + * @vfe_bus: Pointer to vfe_bus structure which will be filled + * and returned on successful initialize + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_bus_ver3_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *bus_hw_info, + void *vfe_irq_controller, + struct cam_vfe_bus **vfe_bus); + +/* + * cam_vfe_bus_ver3_deinit() + * + * @Brief: Deinitialize Bus layer + * + * @vfe_bus: Pointer to vfe_bus structure to deinitialize + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_bus_ver3_deinit(struct cam_vfe_bus **vfe_bus); + +#endif /* _CAM_VFE_BUS_VER3_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include/cam_vfe_bus.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include/cam_vfe_bus.h new file mode 100644 index 0000000000000000000000000000000000000000..97336a2da3b89104b5ece0210c4f935b9d92321b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include/cam_vfe_bus.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_BUS_H_ +#define _CAM_VFE_BUS_H_ + +#include +#include "cam_hw_intf.h" +#include "cam_isp_hw.h" + +#define CAM_VFE_BUS_VER_1_0 0x1000 +#define CAM_VFE_BUS_VER_2_0 0x2000 +#define CAM_VFE_BUS_VER_3_0 0x3000 + +#define CAM_VFE_BUS_RD_VER_1_0 0x1000 + +#define CAM_VFE_ADD_REG_VAL_PAIR(buf_array, index, offset, val) \ + do { \ + buf_array[(index)++] = offset; \ + buf_array[(index)++] = val; \ + } while (0) + +#define ALIGNUP(value, alignment) \ + ((value + alignment - 1) / alignment * alignment) + +enum cam_vfe_bus_plane_type { + PLANE_Y, + PLANE_C, + PLANE_MAX, +}; + +enum cam_vfe_bus_type { + BUS_TYPE_WR, + BUS_TYPE_RD, + BUS_TYPE_MAX, +}; + +/* + * struct cam_vfe_bus: + * + * @Brief: Bus interface structure + * + * @bus_priv: Private data of BUS + * @hw_ops: Hardware interface functions + * @top_half_handler: Top Half handler function + * @bottom_half_handler: Bottom Half handler function + */ +struct cam_vfe_bus { + void *bus_priv; + + struct cam_hw_ops hw_ops; + CAM_IRQ_HANDLER_TOP_HALF top_half_handler; + CAM_IRQ_HANDLER_BOTTOM_HALF bottom_half_handler; +}; + +/* + * cam_vfe_bus_init() + * + * @Brief: Initialize Bus layer + * + * @bus_version: Version of BUS to initialize + * @bus_type: Bus Type RD/WR + * @soc_info: Soc Information for the associated HW + * @hw_intf: HW Interface of HW to which this resource belongs + * @bus_hw_info: BUS HW info that contains details of BUS registers + * @vfe_irq_controller: VFE IRQ Controller to use for subscribing to Top + * level IRQs + * @vfe_bus: Pointer to vfe_bus structure which will be filled + * and returned on successful initialize + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_bus_init(uint32_t bus_version, + int bus_type, + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *bus_hw_info, + void *vfe_irq_controller, + struct cam_vfe_bus **vfe_bus); + +/* + * cam_vfe_bus_deinit() + * + * @Brief: Deinitialize Bus layer + * + * @bus_version: Version of BUS to deinitialize + * @vfe_bus: Pointer to vfe_bus structure to deinitialize + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_vfe_bus_deinit(uint32_t bus_version, + struct cam_vfe_bus **vfe_bus); + +#endif /* _CAM_VFE_BUS_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..0d4876af11590e811a0079583ba8dab14acbc86c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe_camif_lite_ver2.o cam_vfe_top.o cam_vfe_top_common.o +obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe_top_ver3.o cam_vfe_top_ver2.o cam_vfe_camif_ver2.o +obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe_camif_ver3.o cam_vfe_rdi.o cam_vfe_fe_ver1.o cam_vfe_camif_lite_ver3.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c new file mode 100644 index 0000000000000000000000000000000000000000..9ea8d74a35caa00a5e9acc0512a95abacf473745 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.c @@ -0,0 +1,556 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include "cam_io_util.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_isp_hw.h" +#include "cam_vfe_hw_intf.h" +#include "cam_vfe_soc.h" +#include "cam_vfe_top.h" +#include "cam_vfe_top_ver2.h" +#include "cam_irq_controller.h" +#include "cam_tasklet_util.h" +#include "cam_vfe_camif_lite_ver2.h" +#include "cam_debug_util.h" +#include "cam_cdm_util.h" + +struct cam_vfe_mux_camif_lite_data { + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + struct cam_vfe_camif_lite_ver2_reg *camif_lite_reg; + struct cam_vfe_top_ver2_reg_offset_common *common_reg; + struct cam_vfe_camif_lite_ver2_reg_data *reg_data; + struct cam_hw_soc_info *soc_info; + enum cam_isp_hw_sync_mode sync_mode; + + cam_hw_mgr_event_cb_func event_cb; + void *priv; + int irq_err_handle; + int irq_handle; + void *vfe_irq_controller; + struct cam_vfe_top_irq_evt_payload + evt_payload[CAM_VFE_CAMIF_LITE_EVT_MAX]; + struct list_head free_payload_list; + spinlock_t spin_lock; +}; + +static int cam_vfe_camif_lite_get_evt_payload( + struct cam_vfe_mux_camif_lite_data *camif_lite_priv, + struct cam_vfe_top_irq_evt_payload **evt_payload) +{ + int rc = 0; + + spin_lock(&camif_lite_priv->spin_lock); + if (list_empty(&camif_lite_priv->free_payload_list)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No free payload"); + rc = -ENODEV; + goto done; + } + + *evt_payload = list_first_entry(&camif_lite_priv->free_payload_list, + struct cam_vfe_top_irq_evt_payload, list); + list_del_init(&(*evt_payload)->list); + rc = 0; +done: + spin_unlock(&camif_lite_priv->spin_lock); + return rc; +} + +static int cam_vfe_camif_lite_put_evt_payload( + struct cam_vfe_mux_camif_lite_data *camif_lite_priv, + struct cam_vfe_top_irq_evt_payload **evt_payload) +{ + unsigned long flags; + + if (!camif_lite_priv) { + CAM_ERR(CAM_ISP, "Invalid param core_info NULL"); + return -EINVAL; + } + if (*evt_payload == NULL) { + CAM_ERR(CAM_ISP, "No payload to put"); + return -EINVAL; + } + + spin_lock_irqsave(&camif_lite_priv->spin_lock, flags); + list_add_tail(&(*evt_payload)->list, + &camif_lite_priv->free_payload_list); + *evt_payload = NULL; + spin_unlock_irqrestore(&camif_lite_priv->spin_lock, flags); + + CAM_DBG(CAM_ISP, "Done"); + return 0; +} + +static int cam_vfe_camif_lite_err_irq_top_half( + uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc; + int i; + struct cam_isp_resource_node *camif_lite_node; + struct cam_vfe_mux_camif_lite_data *camif_lite_priv; + struct cam_vfe_top_irq_evt_payload *evt_payload; + bool error_flag = false; + + CAM_DBG(CAM_ISP, "IRQ status_0 = %x, IRQ status_1 = %x", + th_payload->evt_status_arr[0], th_payload->evt_status_arr[1]); + + camif_lite_node = th_payload->handler_priv; + camif_lite_priv = camif_lite_node->res_priv; + /* + * need to handle overflow condition here, otherwise irq storm + * will block everything + */ + if (th_payload->evt_status_arr[1] || (th_payload->evt_status_arr[0] & + camif_lite_priv->reg_data->lite_err_irq_mask0)) { + CAM_ERR(CAM_ISP, + "CAMIF LITE ERR VFE:%d IRQ STATUS_0=0x%x STATUS_1=0x%x", + camif_lite_node->hw_intf->hw_idx, + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1]); + CAM_ERR(CAM_ISP, "Stopping further IRQ processing from VFE:%d", + camif_lite_node->hw_intf->hw_idx); + cam_irq_controller_disable_irq( + camif_lite_priv->vfe_irq_controller, + camif_lite_priv->irq_err_handle); + cam_irq_controller_clear_and_mask(evt_id, + camif_lite_priv->vfe_irq_controller); + error_flag = true; + } + + rc = cam_vfe_camif_lite_get_evt_payload(camif_lite_priv, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "No tasklet_cmd is free in queue"); + CAM_ERR_RATE_LIMIT(CAM_ISP, "IRQ STATUS_0=0x%x STATUS_1=0x%x", + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1]); + return rc; + } + + cam_isp_hw_get_timestamp(&evt_payload->ts); + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + evt_payload->irq_reg_val[i] = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->violation_status); + + if (error_flag) + CAM_INFO(CAM_ISP, "Violation status = 0x%x", + evt_payload->irq_reg_val[i]); + + th_payload->evt_payload_priv = evt_payload; + + return rc; +} + + +static int cam_vfe_camif_lite_get_reg_update( + struct cam_isp_resource_node *camif_lite_res, + void *cmd_args, + uint32_t arg_size) +{ + uint32_t size = 0; + uint32_t reg_val_pair[2]; + struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; + struct cam_vfe_mux_camif_lite_data *rsrc_data = NULL; + + if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { + CAM_ERR(CAM_ISP, "Invalid cmd size"); + return -EINVAL; + } + + if (!cdm_args || !cdm_args->res) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + cdm_util_ops = (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; + + if (!cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid CDM ops"); + return -EINVAL; + } + + size = cdm_util_ops->cdm_required_size_reg_random(1); + /* since cdm returns dwords, we need to convert it into bytes */ + if ((size * 4) > cdm_args->cmd.size) { + CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d", + cdm_args->cmd.size, size); + return -EINVAL; + } + + rsrc_data = camif_lite_res->res_priv; + reg_val_pair[0] = rsrc_data->camif_lite_reg->reg_update_cmd; + reg_val_pair[1] = rsrc_data->reg_data->dual_pd_reg_update_cmd_data; + CAM_DBG(CAM_ISP, "CAMIF Lite reg_update_cmd %x offset %x", + reg_val_pair[1], reg_val_pair[0]); + + cdm_util_ops->cdm_write_regrandom(cdm_args->cmd.cmd_buf_addr, + 1, reg_val_pair); + + cdm_args->cmd.used_bytes = size * 4; + + return 0; +} + +int cam_vfe_camif_lite_ver2_acquire_resource( + struct cam_isp_resource_node *camif_lite_res, + void *acquire_param) +{ + struct cam_vfe_mux_camif_lite_data *camif_lite_data; + struct cam_vfe_acquire_args *acquire_data; + int rc = 0; + + if (!camif_lite_res) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + camif_lite_data = (struct cam_vfe_mux_camif_lite_data *) + camif_lite_res->res_priv; + acquire_data = (struct cam_vfe_acquire_args *)acquire_param; + + camif_lite_data->sync_mode = acquire_data->vfe_in.sync_mode; + camif_lite_data->event_cb = acquire_data->event_cb; + camif_lite_data->priv = acquire_data->priv; + + CAM_DBG(CAM_ISP, "hw id:%d sync_mode=%d", + camif_lite_res->hw_intf->hw_idx, + camif_lite_data->sync_mode); + return rc; +} + +static int cam_vfe_camif_lite_resource_start( + struct cam_isp_resource_node *camif_lite_res) +{ + struct cam_vfe_mux_camif_lite_data *rsrc_data; + uint32_t val = 0; + int rc = 0; + uint32_t err_irq_mask[CAM_IFE_IRQ_REGISTERS_MAX]; + + if (!camif_lite_res) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + if (camif_lite_res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Error! Invalid camif lite res res_state:%d", + camif_lite_res->res_state); + return -EINVAL; + } + + rsrc_data = (struct cam_vfe_mux_camif_lite_data *) + camif_lite_res->res_priv; + + err_irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0] = + rsrc_data->reg_data->lite_err_irq_mask0; + err_irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = + rsrc_data->reg_data->lite_err_irq_mask1; + + /* vfe core config */ + val = cam_io_r_mb(rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg); + + if (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) + val |= (1 << rsrc_data->reg_data->extern_reg_update_shift); + + val |= (1 << rsrc_data->reg_data->dual_pd_path_sel_shift); + + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg); + + CAM_DBG(CAM_ISP, "hw id:%d core_cfg val:%d", + camif_lite_res->hw_intf->hw_idx, val); + + /* epoch config with 20 line */ + cam_io_w_mb(rsrc_data->reg_data->lite_epoch_line_cfg, + rsrc_data->mem_base + + rsrc_data->camif_lite_reg->lite_epoch_irq); + + camif_lite_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + /* Reg Update */ + cam_io_w_mb(rsrc_data->reg_data->dual_pd_reg_update_cmd_data, + rsrc_data->mem_base + + rsrc_data->camif_lite_reg->reg_update_cmd); + CAM_DBG(CAM_ISP, "hw id:%d RUP val:%d", + camif_lite_res->hw_intf->hw_idx, + rsrc_data->reg_data->dual_pd_reg_update_cmd_data); + + if (!rsrc_data->irq_err_handle) { + rsrc_data->irq_err_handle = cam_irq_controller_subscribe_irq( + rsrc_data->vfe_irq_controller, + CAM_IRQ_PRIORITY_0, + err_irq_mask, + camif_lite_res, + cam_vfe_camif_lite_err_irq_top_half, + camif_lite_res->bottom_half_handler, + camif_lite_res->tasklet_info, + &tasklet_bh_api); + if (rsrc_data->irq_err_handle < 1) { + CAM_ERR(CAM_ISP, "Error IRQ handle subscribe failure"); + rc = -ENOMEM; + rsrc_data->irq_err_handle = 0; + } + } + + CAM_DBG(CAM_ISP, "Start Camif Lite IFE %d Done", + camif_lite_res->hw_intf->hw_idx); + return rc; +} + +static int cam_vfe_camif_lite_resource_stop( + struct cam_isp_resource_node *camif_lite_res) +{ + struct cam_vfe_mux_camif_lite_data *camif_lite_priv; + int rc = 0; + + if (!camif_lite_res) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + if ((camif_lite_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) || + (camif_lite_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE)) + return 0; + + camif_lite_priv = (struct cam_vfe_mux_camif_lite_data *)camif_lite_res; + + if (camif_lite_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + camif_lite_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + if (camif_lite_priv->irq_handle) { + cam_irq_controller_unsubscribe_irq( + camif_lite_priv->vfe_irq_controller, + camif_lite_priv->irq_handle); + camif_lite_priv->irq_handle = 0; + } + + if (camif_lite_priv->irq_err_handle) { + cam_irq_controller_unsubscribe_irq( + camif_lite_priv->vfe_irq_controller, + camif_lite_priv->irq_err_handle); + camif_lite_priv->irq_err_handle = 0; + } + + return rc; +} + +static int cam_vfe_camif_lite_process_cmd( + struct cam_isp_resource_node *rsrc_node, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = -EINVAL; + + if (!rsrc_node || !cmd_args) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_REG_UPDATE: + rc = cam_vfe_camif_lite_get_reg_update(rsrc_node, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_SET_CAMIF_DEBUG: + break; + default: + CAM_ERR(CAM_ISP, + "unsupported process command:%d", cmd_type); + break; + } + + return rc; +} + +static int cam_vfe_camif_lite_handle_irq_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc; + int i; + struct cam_isp_resource_node *camif_lite_node; + struct cam_vfe_mux_camif_lite_data *camif_lite_priv; + struct cam_vfe_top_irq_evt_payload *evt_payload; + + camif_lite_node = th_payload->handler_priv; + camif_lite_priv = camif_lite_node->res_priv; + + CAM_DBG(CAM_ISP, "IRQ status_0 = %x", th_payload->evt_status_arr[0]); + CAM_DBG(CAM_ISP, "IRQ status_1 = %x", th_payload->evt_status_arr[1]); + + rc = cam_vfe_camif_lite_get_evt_payload(camif_lite_priv, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No tasklet_cmd is free in queue"); + CAM_ERR_RATE_LIMIT(CAM_ISP, "IRQ status0=0x%x status1=0x%x", + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1]); + return rc; + } + + cam_isp_hw_get_timestamp(&evt_payload->ts); + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + th_payload->evt_payload_priv = evt_payload; + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +static int cam_vfe_camif_lite_handle_irq_bottom_half( + void *handler_priv, + void *evt_payload_priv) +{ + int ret = CAM_VFE_IRQ_STATUS_MAX; + struct cam_isp_resource_node *camif_lite_node; + struct cam_vfe_mux_camif_lite_data *camif_lite_priv; + struct cam_vfe_top_irq_evt_payload *payload; + struct cam_isp_hw_event_info evt_info; + uint32_t irq_status0; + uint32_t irq_status1; + + if (!handler_priv || !evt_payload_priv) { + CAM_ERR(CAM_ISP, "Invalid params"); + return ret; + } + + camif_lite_node = handler_priv; + camif_lite_priv = camif_lite_node->res_priv; + payload = evt_payload_priv; + irq_status0 = payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS0]; + irq_status1 = payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS1]; + + evt_info.hw_idx = camif_lite_node->hw_intf->hw_idx; + evt_info.res_id = camif_lite_node->res_id; + evt_info.res_type = camif_lite_node->res_type; + + CAM_DBG(CAM_ISP, "irq_status_0 = 0x%x irq_status_1 = 0x%x", + irq_status0, irq_status1); + + if (irq_status0 & camif_lite_priv->reg_data->lite_sof_irq_mask) { + CAM_DBG(CAM_ISP, "VFE:%d CAMIF Lite Received SOF", + evt_info.hw_idx); + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status0 & camif_lite_priv->reg_data->lite_epoch0_irq_mask) { + CAM_DBG(CAM_ISP, "VFE:%d CAMIF Lite Received EPOCH", + evt_info.hw_idx); + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status0 & camif_lite_priv->reg_data->dual_pd_reg_upd_irq_mask) { + CAM_DBG(CAM_ISP, "VFE:%d CAMIF Lite Received REG_UPDATE_ACK", + evt_info.hw_idx); + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status0 & camif_lite_priv->reg_data->lite_eof_irq_mask) { + CAM_DBG(CAM_ISP, "VFE:%d CAMIF Lite Received EOF", + evt_info.hw_idx); + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if ((irq_status0 & camif_lite_priv->reg_data->lite_err_irq_mask0) || + (irq_status1 & camif_lite_priv->reg_data->lite_err_irq_mask1)) { + CAM_DBG(CAM_ISP, "VFE:%d CAMIF LITE Received ERROR", + evt_info.hw_idx); + + if (camif_lite_priv->event_cb) + camif_lite_priv->event_cb(camif_lite_priv->priv, + CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_OVERFLOW; + } + + cam_vfe_camif_lite_put_evt_payload(camif_lite_priv, &payload); + + CAM_DBG(CAM_ISP, "returning status = %d", ret); + return ret; +} + +int cam_vfe_camif_lite_ver2_init( + struct cam_hw_intf *hw_intf, + struct cam_hw_soc_info *soc_info, + void *camif_lite_hw_info, + struct cam_isp_resource_node *camif_lite_node, + void *vfe_irq_controller) +{ + struct cam_vfe_mux_camif_lite_data *camif_lite_priv = NULL; + struct cam_vfe_camif_lite_ver2_hw_info *camif_lite_info = + camif_lite_hw_info; + int i = 0; + + camif_lite_priv = kzalloc(sizeof(*camif_lite_priv), + GFP_KERNEL); + if (!camif_lite_priv) + return -ENOMEM; + + camif_lite_node->res_priv = camif_lite_priv; + + camif_lite_priv->mem_base = + soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base; + camif_lite_priv->camif_lite_reg = camif_lite_info->camif_lite_reg; + camif_lite_priv->common_reg = camif_lite_info->common_reg; + camif_lite_priv->reg_data = camif_lite_info->reg_data; + camif_lite_priv->hw_intf = hw_intf; + camif_lite_priv->soc_info = soc_info; + camif_lite_priv->vfe_irq_controller = vfe_irq_controller; + + camif_lite_node->init = NULL; + camif_lite_node->deinit = NULL; + camif_lite_node->start = cam_vfe_camif_lite_resource_start; + camif_lite_node->stop = cam_vfe_camif_lite_resource_stop; + camif_lite_node->process_cmd = cam_vfe_camif_lite_process_cmd; + camif_lite_node->top_half_handler = + cam_vfe_camif_lite_handle_irq_top_half; + camif_lite_node->bottom_half_handler = + cam_vfe_camif_lite_handle_irq_bottom_half; + + spin_lock_init(&camif_lite_priv->spin_lock); + INIT_LIST_HEAD(&camif_lite_priv->free_payload_list); + for (i = 0; i < CAM_VFE_CAMIF_LITE_EVT_MAX; i++) { + INIT_LIST_HEAD(&camif_lite_priv->evt_payload[i].list); + list_add_tail(&camif_lite_priv->evt_payload[i].list, + &camif_lite_priv->free_payload_list); + } + + return 0; +} + +int cam_vfe_camif_lite_ver2_deinit( + struct cam_isp_resource_node *camif_lite_node) +{ + struct cam_vfe_mux_camif_lite_data *camif_lite_priv = + camif_lite_node->res_priv; + int i = 0; + + INIT_LIST_HEAD(&camif_lite_priv->free_payload_list); + for (i = 0; i < CAM_VFE_CAMIF_LITE_EVT_MAX; i++) + INIT_LIST_HEAD(&camif_lite_priv->evt_payload[i].list); + + camif_lite_node->start = NULL; + camif_lite_node->stop = NULL; + camif_lite_node->process_cmd = NULL; + camif_lite_node->top_half_handler = NULL; + camif_lite_node->bottom_half_handler = NULL; + + camif_lite_node->res_priv = NULL; + + if (!camif_lite_priv) { + CAM_ERR(CAM_ISP, "Error! camif_priv is NULL"); + return -ENODEV; + } + + kfree(camif_lite_priv); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.h new file mode 100644 index 0000000000000000000000000000000000000000..7813e55f508bf45382a02c23971caa65d44c2c61 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver2.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_CAMIF_LITE_VER2_H_ +#define _CAM_VFE_CAMIF_LITE_VER2_H_ + +#include "cam_isp_hw.h" +#include "cam_vfe_top.h" + +#define CAM_VFE_CAMIF_LITE_EVT_MAX 256 + +struct cam_vfe_camif_lite_ver2_reg { + uint32_t camif_lite_cmd; + uint32_t camif_lite_config; + uint32_t lite_skip_period; + uint32_t lite_irq_subsample_pattern; + uint32_t lite_epoch_irq; + uint32_t reg_update_cmd; +}; + +struct cam_vfe_camif_lite_ver2_reg_data { + uint32_t dual_pd_reg_update_cmd_data; + uint32_t lite_epoch_line_cfg; + uint32_t lite_sof_irq_mask; + uint32_t lite_epoch0_irq_mask; + uint32_t dual_pd_reg_upd_irq_mask; + uint32_t lite_eof_irq_mask; + uint32_t lite_err_irq_mask0; + uint32_t lite_err_irq_mask1; + uint32_t lite_subscribe_irq_mask0; + uint32_t lite_subscribe_irq_mask1; + uint32_t extern_reg_update_shift; + uint32_t dual_pd_path_sel_shift; +}; + +struct cam_vfe_camif_lite_ver2_hw_info { + struct cam_vfe_top_ver2_reg_offset_common *common_reg; + struct cam_vfe_camif_lite_ver2_reg *camif_lite_reg; + struct cam_vfe_camif_lite_ver2_reg_data *reg_data; +}; + +int cam_vfe_camif_lite_ver2_acquire_resource( + struct cam_isp_resource_node *camif_lite_res, + void *acquire_param); + +int cam_vfe_camif_lite_ver2_init( + struct cam_hw_intf *hw_intf, + struct cam_hw_soc_info *soc_info, + void *camif_lite_hw_info, + struct cam_isp_resource_node *camif_lite_node, + void *vfe_irq_controller); + +int cam_vfe_camif_lite_ver2_deinit( + struct cam_isp_resource_node *camif_node); + +#endif /* _CAM_VFE_CAMIF_LITE_VER2_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.c new file mode 100644 index 0000000000000000000000000000000000000000..e0032b7b5b53525cbe9bbf58a8f14ae2f497ba92 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.c @@ -0,0 +1,1257 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include "cam_io_util.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_isp_hw.h" +#include "cam_vfe_hw_intf.h" +#include "cam_vfe_soc.h" +#include "cam_vfe_top.h" +#include "cam_vfe_top_ver3.h" +#include "cam_irq_controller.h" +#include "cam_tasklet_util.h" +#include "cam_vfe_camif_lite_ver3.h" +#include "cam_debug_util.h" +#include "cam_cdm_util.h" +#include "cam_cpas_api.h" + +struct cam_vfe_mux_camif_lite_data { + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + struct cam_vfe_camif_lite_ver3_reg *camif_lite_reg; + struct cam_vfe_top_ver3_reg_offset_common *common_reg; + struct cam_vfe_camif_lite_ver3_reg_data *reg_data; + struct cam_hw_soc_info *soc_info; + enum cam_isp_hw_sync_mode sync_mode; + struct cam_vfe_camif_common_cfg cam_common_cfg; + + cam_hw_mgr_event_cb_func event_cb; + void *priv; + int irq_err_handle; + int irq_handle; + int sof_irq_handle; + void *vfe_irq_controller; + struct list_head free_payload_list; + spinlock_t spin_lock; + uint32_t camif_debug; + struct cam_vfe_top_irq_evt_payload + evt_payload[CAM_VFE_CAMIF_LITE_EVT_MAX]; +}; + +static int cam_vfe_camif_lite_get_evt_payload( + struct cam_vfe_mux_camif_lite_data *camif_lite_priv, + struct cam_vfe_top_irq_evt_payload **evt_payload) +{ + int rc = 0; + + spin_lock(&camif_lite_priv->spin_lock); + if (list_empty(&camif_lite_priv->free_payload_list)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No free CAMIF LITE event payload"); + rc = -ENODEV; + goto done; + } + + *evt_payload = list_first_entry(&camif_lite_priv->free_payload_list, + struct cam_vfe_top_irq_evt_payload, list); + list_del_init(&(*evt_payload)->list); + rc = 0; +done: + spin_unlock(&camif_lite_priv->spin_lock); + return rc; +} + +static int cam_vfe_camif_lite_put_evt_payload( + struct cam_vfe_mux_camif_lite_data *camif_lite_priv, + struct cam_vfe_top_irq_evt_payload **evt_payload) +{ + unsigned long flags; + + if (!camif_lite_priv) { + CAM_ERR(CAM_ISP, "Invalid param core_info NULL"); + return -EINVAL; + } + if (*evt_payload == NULL) { + CAM_ERR(CAM_ISP, "No payload to put"); + return -EINVAL; + } + + spin_lock_irqsave(&camif_lite_priv->spin_lock, flags); + list_add_tail(&(*evt_payload)->list, + &camif_lite_priv->free_payload_list); + *evt_payload = NULL; + spin_unlock_irqrestore(&camif_lite_priv->spin_lock, flags); + + CAM_DBG(CAM_ISP, "Done"); + return 0; +} + +static int cam_vfe_camif_lite_err_irq_top_half( + uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc; + int i; + struct cam_isp_resource_node *camif_lite_node; + struct cam_vfe_mux_camif_lite_data *camif_lite_priv; + struct cam_vfe_top_irq_evt_payload *evt_payload; + struct cam_vfe_soc_private *soc_private = NULL; + bool error_flag = false; + + camif_lite_node = th_payload->handler_priv; + camif_lite_priv = camif_lite_node->res_priv; + + soc_private = camif_lite_priv->soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Invalid soc_private"); + return -ENODEV; + } + + /* + * need to handle overflow condition here, otherwise irq storm + * will block everything + */ + if (th_payload->evt_status_arr[2] || (th_payload->evt_status_arr[0] & + camif_lite_priv->reg_data->error_irq_mask0)) { + CAM_ERR(CAM_ISP, + "VFE:%d CAMIF LITE:%d Err IRQ status_1: 0x%X status_2: 0x%X", + camif_lite_node->hw_intf->hw_idx, + camif_lite_node->res_id, + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[2]); + CAM_ERR(CAM_ISP, "Stopping further IRQ processing from VFE:%d", + camif_lite_node->hw_intf->hw_idx); + cam_irq_controller_disable_irq( + camif_lite_priv->vfe_irq_controller, + camif_lite_priv->irq_err_handle); + cam_irq_controller_clear_and_mask(evt_id, + camif_lite_priv->vfe_irq_controller); + error_flag = true; + } + + rc = cam_vfe_camif_lite_get_evt_payload(camif_lite_priv, &evt_payload); + if (rc) + return rc; + + cam_isp_hw_get_timestamp(&evt_payload->ts); + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + evt_payload->irq_reg_val[i] = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->violation_status); + + evt_payload->irq_reg_val[++i] = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->bus_overflow_status); + + th_payload->evt_payload_priv = evt_payload; + + return rc; +} + + +static int cam_vfe_camif_lite_get_reg_update( + struct cam_isp_resource_node *camif_lite_res, + void *cmd_args, + uint32_t arg_size) +{ + uint32_t size = 0; + uint32_t reg_val_pair[2]; + struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; + struct cam_vfe_mux_camif_lite_data *rsrc_data = NULL; + + if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { + CAM_ERR(CAM_ISP, "Invalid cmd size"); + return -EINVAL; + } + + if (!cdm_args || !cdm_args->res) { + CAM_ERR(CAM_ISP, + "Invalid args: cdm args %pK", cdm_args); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "CAMIF LITE:%d get RUP", camif_lite_res->res_id); + + cdm_util_ops = (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; + + if (!cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid CDM ops"); + return -EINVAL; + } + + size = cdm_util_ops->cdm_required_size_reg_random(1); + /* since cdm returns dwords, we need to convert it into bytes */ + if ((size * 4) > cdm_args->cmd.size) { + CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d", + cdm_args->cmd.size, size); + return -EINVAL; + } + + rsrc_data = camif_lite_res->res_priv; + reg_val_pair[0] = rsrc_data->camif_lite_reg->reg_update_cmd; + reg_val_pair[1] = rsrc_data->reg_data->reg_update_cmd_data; + CAM_DBG(CAM_ISP, "CAMIF LITE:%d reg_update_cmd 0x%X offset 0x%X", + camif_lite_res->res_id, reg_val_pair[1], reg_val_pair[0]); + + cdm_util_ops->cdm_write_regrandom(cdm_args->cmd.cmd_buf_addr, + 1, reg_val_pair); + + cdm_args->cmd.used_bytes = size * 4; + + return 0; +} + +int cam_vfe_camif_lite_ver3_acquire_resource( + struct cam_isp_resource_node *camif_lite_res, + void *acquire_param) +{ + struct cam_vfe_mux_camif_lite_data *camif_lite_data; + struct cam_vfe_acquire_args *acquire_data; + + if (!camif_lite_res) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + camif_lite_data = (struct cam_vfe_mux_camif_lite_data *) + camif_lite_res->res_priv; + acquire_data = (struct cam_vfe_acquire_args *)acquire_param; + + camif_lite_data->sync_mode = acquire_data->vfe_in.sync_mode; + camif_lite_data->event_cb = acquire_data->event_cb; + camif_lite_data->priv = acquire_data->priv; + camif_lite_res->rdi_only_ctx = 0; + CAM_DBG(CAM_ISP, "Acquired VFE:%d CAMIF LITE:%d sync_mode=%d", + camif_lite_res->hw_intf->hw_idx, + camif_lite_res->res_id, + camif_lite_data->sync_mode); + return 0; +} + +static int cam_vfe_camif_lite_resource_start( + struct cam_isp_resource_node *camif_lite_res) +{ + struct cam_vfe_mux_camif_lite_data *rsrc_data; + struct cam_vfe_soc_private *soc_private = NULL; + uint32_t val = 0; + int rc = 0; + uint32_t err_irq_mask[CAM_IFE_IRQ_REGISTERS_MAX]; + uint32_t irq_mask[CAM_IFE_IRQ_REGISTERS_MAX]; + + if (!camif_lite_res) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + if (camif_lite_res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Invalid camif lite res res_state:%d", + camif_lite_res->res_state); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "CAMIF LITE:%d Start", camif_lite_res->res_id); + + rsrc_data = (struct cam_vfe_mux_camif_lite_data *) + camif_lite_res->res_priv; + + soc_private = rsrc_data->soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Invalid soc_private"); + return -ENODEV; + } + + if (soc_private->is_ife_lite) + goto skip_core_cfg; + + /* vfe core config */ + val = cam_io_r_mb(rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg_0); + + if (camif_lite_res->res_id == CAM_ISP_HW_VFE_IN_LCR && + rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) + val |= (1 << rsrc_data->reg_data->extern_reg_update_shift); + + if (camif_lite_res->res_id == CAM_ISP_HW_VFE_IN_PDLIB) { + val |= (1 << rsrc_data->reg_data->operating_mode_shift); + val |= (rsrc_data->cam_common_cfg.input_mux_sel_pdaf & 0x1) << + CAM_SHIFT_TOP_CORE_CFG_MUXSEL_PDAF; + } + + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg_0); + + CAM_DBG(CAM_ISP, "VFE:%d core_cfg val:%d", + camif_lite_res->hw_intf->hw_idx, val); + + /* epoch config */ + cam_io_w_mb(rsrc_data->reg_data->epoch_line_cfg, + rsrc_data->mem_base + + rsrc_data->camif_lite_reg->lite_epoch_irq); + +skip_core_cfg: + + camif_lite_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + /* Reg Update */ + cam_io_w_mb(rsrc_data->reg_data->reg_update_cmd_data, + rsrc_data->mem_base + + rsrc_data->camif_lite_reg->reg_update_cmd); + + memset(err_irq_mask, 0, sizeof(err_irq_mask)); + memset(irq_mask, 0, sizeof(irq_mask)); + + /* config debug status registers */ + cam_io_w_mb(rsrc_data->reg_data->top_debug_cfg_en, rsrc_data->mem_base + + rsrc_data->common_reg->top_debug_cfg); + + if (!camif_lite_res->rdi_only_ctx) + goto subscribe_err; + + irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = + rsrc_data->reg_data->epoch0_irq_mask | + rsrc_data->reg_data->eof_irq_mask; + + if (!rsrc_data->irq_handle) { + rsrc_data->irq_handle = cam_irq_controller_subscribe_irq( + rsrc_data->vfe_irq_controller, + CAM_IRQ_PRIORITY_3, + irq_mask, + camif_lite_res, + camif_lite_res->top_half_handler, + camif_lite_res->bottom_half_handler, + camif_lite_res->tasklet_info, + &tasklet_bh_api); + if (rsrc_data->irq_handle < 1) { + CAM_ERR(CAM_ISP, "IRQ handle subscribe failure"); + rc = -ENOMEM; + rsrc_data->irq_handle = 0; + } + } + + irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = + rsrc_data->reg_data->sof_irq_mask; + + if (!rsrc_data->sof_irq_handle) { + rsrc_data->sof_irq_handle = cam_irq_controller_subscribe_irq( + rsrc_data->vfe_irq_controller, + CAM_IRQ_PRIORITY_1, + irq_mask, + camif_lite_res, + camif_lite_res->top_half_handler, + camif_lite_res->bottom_half_handler, + camif_lite_res->tasklet_info, + &tasklet_bh_api); + if (rsrc_data->sof_irq_handle < 1) { + CAM_ERR(CAM_ISP, "IRQ handle subscribe failure"); + rc = -ENOMEM; + rsrc_data->sof_irq_handle = 0; + } + } + +subscribe_err: + + err_irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0] = + rsrc_data->reg_data->error_irq_mask0; + err_irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS2] = + rsrc_data->reg_data->error_irq_mask2; + + if (!rsrc_data->irq_err_handle) { + rsrc_data->irq_err_handle = cam_irq_controller_subscribe_irq( + rsrc_data->vfe_irq_controller, + CAM_IRQ_PRIORITY_0, + err_irq_mask, + camif_lite_res, + cam_vfe_camif_lite_err_irq_top_half, + camif_lite_res->bottom_half_handler, + camif_lite_res->tasklet_info, + &tasklet_bh_api); + + if (rsrc_data->irq_err_handle < 1) { + CAM_ERR(CAM_ISP, "Error IRQ handle subscribe failure"); + rc = -ENOMEM; + rsrc_data->irq_err_handle = 0; + } + } + + CAM_DBG(CAM_ISP, "VFE:%d CAMIF LITE:%d Start Done", + camif_lite_res->hw_intf->hw_idx, + camif_lite_res->res_id); + return rc; +} + +static int cam_vfe_camif_lite_reg_dump( + struct cam_isp_resource_node *camif_lite_res) +{ + struct cam_vfe_mux_camif_lite_data *camif_lite_priv; + struct cam_vfe_soc_private *soc_private = NULL; + uint32_t offset, val, wm_idx; + + if (!camif_lite_res) { + CAM_ERR(CAM_ISP, "Error, Invalid input arguments"); + return -EINVAL; + } + + if ((camif_lite_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) || + (camif_lite_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE)) + return 0; + + camif_lite_priv = + (struct cam_vfe_mux_camif_lite_data *)camif_lite_res->res_priv; + + soc_private = camif_lite_priv->soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Invalid soc_private"); + return -ENODEV; + } + + CAM_INFO(CAM_ISP, "IFE:%d TOP", camif_lite_priv->hw_intf->hw_idx); + if (!soc_private->is_ife_lite) { + for (offset = 0x0; offset <= 0x1FC; offset += 0x4) { + if (offset == 0x1C || offset == 0x34 || + offset == 0x38 || offset == 0x90) + continue; + val = cam_soc_util_r(camif_lite_priv->soc_info, + 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + } + } else { + for (offset = 0x0; offset <= 0x74; offset += 0x4) { + if (offset == 0xC || offset == 0x20 || offset == 0x24) + continue; + val = cam_soc_util_r(camif_lite_priv->soc_info, + 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + } + } + + if (camif_lite_res->res_id != CAM_ISP_HW_VFE_IN_RDI0) + goto dump_rdi_1; + + CAM_INFO(CAM_ISP, "IFE:%d RDI0 CAMIF", + camif_lite_priv->hw_intf->hw_idx); + if (!soc_private->is_ife_lite) { + for (offset = 0x9A00; offset <= 0x9BFC; offset += 0x4) { + if (offset == 0x9A08) + offset = 0x9A60; + val = cam_soc_util_r(camif_lite_priv->soc_info, + 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + if (offset == 0x9A60) + offset = 0x9A64; + else if (offset == 0x9A70) + offset = 0x9AEC; + } + } else { + for (offset = 0x1200; offset <= 0x13FC; offset += 0x4) { + if (offset == 0x1208) + offset = 0x1260; + val = cam_soc_util_r(camif_lite_priv->soc_info, + 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + if (offset == 0x1260) + offset = 0x1264; + else if (offset == 0x1270) + offset = 0x12EC; + } + } + + goto wr_dump; + +dump_rdi_1: + if (camif_lite_res->res_id != CAM_ISP_HW_VFE_IN_RDI1) + goto dump_rdi_2; + + CAM_INFO(CAM_ISP, "IFE:%d RDI1 CAMIF", + camif_lite_priv->hw_intf->hw_idx); + if (!soc_private->is_ife_lite) { + for (offset = 0x9C00; offset <= 0x9DFC; offset += 0x4) { + if (offset == 0x9A08) + offset = 0x9A60; + val = cam_soc_util_r(camif_lite_priv->soc_info, + 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + if (offset == 0x9A60) + offset = 0x9A64; + else if (offset == 0x9A70) + offset = 0x9BEC; + } + } else { + for (offset = 0x1400; offset <= 0x15FC; offset += 0x4) { + if (offset == 0x1408) + offset = 0x1460; + val = cam_soc_util_r(camif_lite_priv->soc_info, + 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + if (offset == 0x1460) + offset = 0x1464; + else if (offset == 0x1470) + offset = 0x15EC; + } + } + + goto wr_dump; + +dump_rdi_2: + if (camif_lite_res->res_id != CAM_ISP_HW_VFE_IN_RDI2) + goto dump_rdi_3; + + CAM_INFO(CAM_ISP, "IFE:%d RDI2 CAMIF", + camif_lite_priv->hw_intf->hw_idx); + if (!soc_private->is_ife_lite) { + for (offset = 0x9E00; offset <= 0x9FFC; offset += 0x4) { + if (offset == 0x9E08) + offset = 0x9E60; + val = cam_soc_util_r(camif_lite_priv->soc_info, + 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + if (offset == 0x9E60) + offset = 0x9E64; + else if (offset == 0x9E80) + offset = 0x9FEC; + } + } else { + for (offset = 0x1600; offset <= 0x17FC; offset += 0x4) { + if (offset == 0x1608) + offset = 0x1660; + val = cam_soc_util_r(camif_lite_priv->soc_info, + 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + if (offset == 0x1660) + offset = 0x1664; + else if (offset == 0x1670) + offset = 0x17EC; + } + } + + goto wr_dump; + +dump_rdi_3: + if (camif_lite_res->res_id != CAM_ISP_HW_VFE_IN_RDI3) + goto dump_pdlib; + + CAM_INFO(CAM_ISP, "IFE:%d RDI3 CAMIF", + camif_lite_priv->hw_intf->hw_idx); + if (soc_private->is_ife_lite) { + for (offset = 0x1800; offset <= 0x19FC; offset += 0x4) { + if (offset == 0x1808) + offset = 0x1860; + val = cam_soc_util_r(camif_lite_priv->soc_info, + 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + if (offset == 0x1860) + offset = 0x1864; + else if (offset == 0x1870) + offset = 0x19EC; + } + } + + goto wr_dump; + +dump_pdlib: + if (camif_lite_res->res_id != CAM_ISP_HW_VFE_IN_PDLIB) + goto dump_lcr; + + CAM_INFO(CAM_ISP, "IFE:%d PDLIB CAMIF", + camif_lite_priv->hw_intf->hw_idx); + for (offset = 0xA400; offset <= 0xA5FC; offset += 0x4) { + if (offset == 0xA408) + offset = 0xA460; + val = cam_soc_util_r(camif_lite_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + if (offset == 0xA460) + offset = 0xA464; + else if (offset == 0xA470) + offset = 0xA5EC; + } + + CAM_INFO(CAM_ISP, "IFE:%d CLC PDLIB", + camif_lite_priv->hw_intf->hw_idx); + for (offset = 0xA600; offset <= 0xA718; offset += 0x4) { + val = cam_soc_util_r(camif_lite_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", offset, val); + } + + goto wr_dump; + +dump_lcr: + CAM_INFO(CAM_ISP, "IFE:%d LCR CAMIF", camif_lite_priv->hw_intf->hw_idx); + for (offset = 0xA000; offset <= 0xA1FC; offset += 0x4) { + if (offset == 0xA008) + offset = 0xA060; + val = cam_soc_util_r(camif_lite_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + if (offset == 0xA060) + offset = 0xA064; + else if (offset == 0xA070) + offset = 0xA1EC; + } + + CAM_INFO(CAM_ISP, "IFE:%d CLC LCR", camif_lite_priv->hw_intf->hw_idx); + for (offset = 0xA200; offset <= 0xA3FC; offset += 0x4) { + if (offset == 0xA208) + offset = 0xA260; + else if (offset == 0xA288) + offset = 0xA3F8; + val = cam_soc_util_r(camif_lite_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + if (offset == 0xA260) + offset = 0xA264; + else if (offset == 0xA280) + offset = 0xA1EC; + } + +wr_dump: + if (!soc_private->is_ife_lite) + goto end_dump; + + CAM_INFO(CAM_ISP, "IFE:%d LITE BUS WR", + camif_lite_priv->hw_intf->hw_idx); + for (offset = 0x1A00; offset <= 0x1AE0; offset += 0x4) { + val = cam_soc_util_r(camif_lite_priv->soc_info, 0, offset); + CAM_DBG(CAM_ISP, "offset 0x%X value 0x%X", offset, val); + } + + for (wm_idx = 0; wm_idx <= 3; wm_idx++) { + for (offset = 0x1C00 + 0x100 * wm_idx; offset < (0x1C00 + + 0x100 * wm_idx + 0x84); offset += 0x4) { + val = cam_soc_util_r(camif_lite_priv->soc_info, + 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + } + } + +end_dump: + return 0; +} + +static int cam_vfe_camif_lite_resource_stop( + struct cam_isp_resource_node *camif_lite_res) +{ + struct cam_vfe_mux_camif_lite_data *rsrc_data; + int rc = 0; + + if (!camif_lite_res) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "VFE:%d CAMIF LITE:%d Stop", + camif_lite_res->hw_intf->hw_idx, + camif_lite_res->res_id); + + if ((camif_lite_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) || + (camif_lite_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE)) + return 0; + + rsrc_data = + (struct cam_vfe_mux_camif_lite_data *)camif_lite_res->res_priv; + + /* Disable Camif */ + cam_io_w_mb(0x0, rsrc_data->mem_base + + rsrc_data->camif_lite_reg->lite_module_config); + + if (camif_lite_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + camif_lite_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + if (rsrc_data->irq_handle > 0) { + cam_irq_controller_unsubscribe_irq( + rsrc_data->vfe_irq_controller, + rsrc_data->irq_handle); + rsrc_data->irq_handle = 0; + } + + if (rsrc_data->sof_irq_handle > 0) { + cam_irq_controller_unsubscribe_irq( + rsrc_data->vfe_irq_controller, + rsrc_data->sof_irq_handle); + rsrc_data->sof_irq_handle = 0; + } + + if (rsrc_data->irq_err_handle > 0) { + cam_irq_controller_unsubscribe_irq( + rsrc_data->vfe_irq_controller, + rsrc_data->irq_err_handle); + rsrc_data->irq_err_handle = 0; + } + + return rc; +} + +static int cam_vfe_camif_lite_ver3_core_config( + struct cam_isp_resource_node *rsrc_node, void *cmd_args) +{ + struct cam_vfe_mux_camif_lite_data *camif_lite_priv; + struct cam_vfe_core_config_args *vfe_core_cfg = + (struct cam_vfe_core_config_args *)cmd_args; + + camif_lite_priv = + (struct cam_vfe_mux_camif_lite_data *)rsrc_node->res_priv; + camif_lite_priv->cam_common_cfg.vid_ds16_r2pd = + vfe_core_cfg->core_config.vid_ds16_r2pd; + camif_lite_priv->cam_common_cfg.vid_ds4_r2pd = + vfe_core_cfg->core_config.vid_ds4_r2pd; + camif_lite_priv->cam_common_cfg.disp_ds16_r2pd = + vfe_core_cfg->core_config.disp_ds16_r2pd; + camif_lite_priv->cam_common_cfg.disp_ds4_r2pd = + vfe_core_cfg->core_config.disp_ds4_r2pd; + camif_lite_priv->cam_common_cfg.dsp_streaming_tap_point = + vfe_core_cfg->core_config.dsp_streaming_tap_point; + camif_lite_priv->cam_common_cfg.ihist_src_sel = + vfe_core_cfg->core_config.ihist_src_sel; + camif_lite_priv->cam_common_cfg.hdr_be_src_sel = + vfe_core_cfg->core_config.hdr_be_src_sel; + camif_lite_priv->cam_common_cfg.hdr_bhist_src_sel = + vfe_core_cfg->core_config.hdr_bhist_src_sel; + camif_lite_priv->cam_common_cfg.input_mux_sel_pdaf = + vfe_core_cfg->core_config.input_mux_sel_pdaf; + camif_lite_priv->cam_common_cfg.input_mux_sel_pp = + vfe_core_cfg->core_config.input_mux_sel_pp; + + return 0; +} + +static int cam_vfe_camif_lite_process_cmd( + struct cam_isp_resource_node *rsrc_node, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = -EINVAL; + struct cam_vfe_mux_camif_lite_data *camif_lite_priv = NULL; + + if (!rsrc_node || !cmd_args) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_REG_UPDATE: + rc = cam_vfe_camif_lite_get_reg_update(rsrc_node, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_CORE_CONFIG: + rc = cam_vfe_camif_lite_ver3_core_config(rsrc_node, cmd_args); + break; + case CAM_ISP_HW_CMD_SET_CAMIF_DEBUG: + camif_lite_priv = (struct cam_vfe_mux_camif_lite_data *) + rsrc_node->res_priv; + camif_lite_priv->camif_debug = *((uint32_t *)cmd_args); + break; + default: + CAM_ERR(CAM_ISP, + "unsupported process command:%d", cmd_type); + break; + } + + return rc; +} + +static void cam_vfe_camif_lite_overflow_debug_info( + struct cam_vfe_mux_camif_lite_data *camif_lite_priv) +{ + struct cam_vfe_soc_private *soc_private = NULL; + uint32_t val0, val1, val2, val3; + + soc_private = camif_lite_priv->soc_info->soc_private; + + val0 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_0); + val1 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_1); + val2 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_2); + val3 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_3); + CAM_INFO(CAM_ISP, + "status_0: 0x%X status_1: 0x%X status_2: 0x%X status_3: 0x%X", + val0, val1, val2, val3); + + if (soc_private->is_ife_lite) + return; + + val0 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_4); + val1 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_5); + val2 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_6); + val3 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_7); + CAM_INFO(CAM_ISP, + "status_4: 0x%X status_5: 0x%X status_6: 0x%X status_7: 0x%X", + val0, val1, val2, val3); + val0 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_8); + val1 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_9); + val2 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_10); + val3 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_11); + CAM_INFO(CAM_ISP, + "status_8: 0x%X status_9: 0x%X status_10: 0x%X status_11: 0x%X", + val0, val1, val2, val3); + val0 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_12); + val1 = cam_io_r(camif_lite_priv->mem_base + + camif_lite_priv->common_reg->top_debug_13); + CAM_INFO(CAM_ISP, "status_12: 0x%X status_13: 0x%X", + val0, val1); +} + +static void cam_vfe_camif_lite_print_status(uint32_t *status, + int err_type, struct cam_vfe_mux_camif_lite_data *camif_lite_priv) +{ + uint32_t violation_mask = 0x3F00, violation_status = 0; + uint32_t bus_overflow_status = 0, status_0 = 0, status_2 = 0; + struct cam_vfe_soc_private *soc_private = NULL; + uint32_t val0, val1, val2; + + if (!status) { + CAM_ERR(CAM_ISP, "Invalid params"); + return; + } + + bus_overflow_status = status[CAM_IFE_IRQ_BUS_OVERFLOW_STATUS]; + violation_status = status[CAM_IFE_IRQ_VIOLATION_STATUS]; + status_0 = status[CAM_IFE_IRQ_CAMIF_REG_STATUS0]; + status_2 = status[CAM_IFE_IRQ_CAMIF_REG_STATUS2]; + soc_private = camif_lite_priv->soc_info->soc_private; + + if (soc_private->is_ife_lite) + goto ife_lite; + + if (err_type == CAM_VFE_IRQ_STATUS_OVERFLOW) { + if (status_0 & 0x200000) + CAM_INFO(CAM_ISP, "RDI2 FRAME DROP"); + + if (status_0 & 0x400000) + CAM_INFO(CAM_ISP, "RDI1 FRAME DROP"); + + if (status_0 & 0x800000) + CAM_INFO(CAM_ISP, "RDI0 FRAME DROP"); + + if (status_0 & 0x1000000) + CAM_INFO(CAM_ISP, "PD PIPE FRAME DROP"); + + if (status_0 & 0x8000000) + CAM_INFO(CAM_ISP, "RDI2 OVERFLOW"); + + if (status_0 & 0x10000000) + CAM_INFO(CAM_ISP, "RDI1 OVERFLOW"); + + if (status_0 & 0x20000000) + CAM_INFO(CAM_ISP, "RDI0 OVERFLOW"); + + if (status_0 & 0x40000000) + CAM_INFO(CAM_ISP, "PD PIPE OVERFLOW"); + } + + if (err_type == CAM_VFE_IRQ_STATUS_OVERFLOW && bus_overflow_status) { + if (bus_overflow_status & 0x0800) + CAM_INFO(CAM_ISP, "CAMIF PD BUS OVERFLOW"); + + if (bus_overflow_status & 0x0400000) + CAM_INFO(CAM_ISP, "LCR BUS OVERFLOW"); + + if (bus_overflow_status & 0x0800000) + CAM_INFO(CAM_ISP, "RDI0 BUS OVERFLOW"); + + if (bus_overflow_status & 0x01000000) + CAM_INFO(CAM_ISP, "RDI1 BUS OVERFLOW"); + + if (bus_overflow_status & 0x02000000) + CAM_INFO(CAM_ISP, "RDI2 BUS OVERFLOW"); + + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0xA20, true, &val0); + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x1420, true, &val1); + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x1A20, true, &val2); + CAM_INFO(CAM_ISP, + "CAMNOC REG ife_linear: 0x%X ife_rdi_wr: 0x%X ife_ubwc_stats: 0x%X", + val0, val1, val2); + cam_cpas_log_votes(); + } + + if (err_type == CAM_VFE_IRQ_STATUS_OVERFLOW && !bus_overflow_status) { + CAM_INFO(CAM_ISP, "PDLIB / LCR Module hang"); + /* print debug registers */ + cam_vfe_camif_lite_overflow_debug_info(camif_lite_priv); + return; + } + + if (err_type == CAM_VFE_IRQ_STATUS_VIOLATION) { + if (status_2 & 0x02000) + CAM_INFO(CAM_ISP, "PD CAMIF VIOLATION"); + + if (status_2 & 0x04000) + CAM_INFO(CAM_ISP, "PD VIOLATION"); + + if (status_2 & 0x08000) + CAM_INFO(CAM_ISP, "LCR CAMIF VIOLATION"); + + if (status_2 & 0x010000) + CAM_INFO(CAM_ISP, "LCR VIOLATION"); + + if (status_2 & 0x020000) + CAM_INFO(CAM_ISP, "RDI0 CAMIF VIOLATION"); + + if (status_2 & 0x040000) + CAM_INFO(CAM_ISP, "RDI1 CAMIF VIOLATION"); + + if (status_2 & 0x080000) + CAM_INFO(CAM_ISP, "RDI2 CAMIF VIOLATION"); + } + + if (err_type == CAM_VFE_IRQ_STATUS_VIOLATION && violation_status) { + if (violation_mask & violation_status) + CAM_INFO(CAM_ISP, "LCR VIOLATION Module ID:%d", + violation_mask & violation_status); + + violation_mask = 0x0F0000; + if (violation_mask & violation_status) + CAM_INFO(CAM_ISP, "PD VIOLATION Module ID:%d", + violation_mask & violation_status); + + } + + return; + +ife_lite: + if (err_type == CAM_VFE_IRQ_STATUS_OVERFLOW) { + if (status_0 & 0x100) + CAM_INFO(CAM_ISP, "RDI3 FRAME DROP"); + + if (status_0 & 0x80) + CAM_INFO(CAM_ISP, "RDI2 FRAME DROP"); + + if (status_0 & 0x40) + CAM_INFO(CAM_ISP, "RDI1 FRAME DROP"); + + if (status_0 & 0x20) + CAM_INFO(CAM_ISP, "RDI0 FRAME DROP"); + + if (status_0 & 0x8) + CAM_INFO(CAM_ISP, "RDI3 OVERFLOW"); + + if (status_0 & 0x4) + CAM_INFO(CAM_ISP, "RDI2 OVERFLOW"); + + if (status_0 & 0x2) + CAM_INFO(CAM_ISP, "RDI1 OVERFLOW"); + + if (status_0 & 0x1) + CAM_INFO(CAM_ISP, "RDI0 OVERFLOW"); + } + + if (err_type == CAM_VFE_IRQ_STATUS_OVERFLOW && bus_overflow_status) { + if (bus_overflow_status & 0x01) + CAM_INFO(CAM_ISP, "RDI0 BUS OVERFLOW"); + + if (bus_overflow_status & 0x02) + CAM_INFO(CAM_ISP, "RDI1 BUS OVERFLOW"); + + if (bus_overflow_status & 0x04) + CAM_INFO(CAM_ISP, "RDI2 BUS OVERFLOW"); + + if (bus_overflow_status & 0x08) + CAM_INFO(CAM_ISP, "RDI3 BUS OVERFLOW"); + + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0xA20, true, &val0); + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x1420, true, &val1); + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x1A20, true, &val2); + CAM_INFO(CAM_ISP, + "CAMNOC REG ife_linear: 0x%X ife_rdi_wr: 0x%X ife_ubwc_stats: 0x%X", + val0, val1, val2); + } + + if (err_type == CAM_VFE_IRQ_STATUS_OVERFLOW && !bus_overflow_status) { + CAM_INFO(CAM_ISP, "RDI hang"); + /* print debug registers */ + cam_vfe_camif_lite_overflow_debug_info(camif_lite_priv); + return; + } + + if (err_type == CAM_VFE_IRQ_STATUS_VIOLATION) { + if (status_2 & 0x100) + CAM_INFO(CAM_ISP, "RDI0 CAMIF VIOLATION"); + + if (status_2 & 0x200) + CAM_INFO(CAM_ISP, "RDI1 CAMIF VIOLATION"); + + if (status_2 & 0x400) + CAM_INFO(CAM_ISP, "RDI2 CAMIF VIOLATION"); + + if (status_2 & 0x800) + CAM_INFO(CAM_ISP, "RDI3 CAMIF VIOLATION"); + } +} + +static int cam_vfe_camif_lite_handle_irq_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc; + int i; + struct cam_isp_resource_node *camif_lite_node; + struct cam_vfe_mux_camif_lite_data *camif_lite_priv; + struct cam_vfe_top_irq_evt_payload *evt_payload; + + camif_lite_node = th_payload->handler_priv; + camif_lite_priv = camif_lite_node->res_priv; + + CAM_DBG(CAM_ISP, + "VFE:%d CAMIF LITE:%d IRQ status_0: 0x%X status_1: 0x%X status_2: 0x%X", + camif_lite_node->hw_intf->hw_idx, + camif_lite_node->res_id, + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1], + th_payload->evt_status_arr[2]); + + rc = cam_vfe_camif_lite_get_evt_payload(camif_lite_priv, &evt_payload); + if (rc) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "VFE:%d CAMIF LITE:%d IRQ status_0: 0x%X status_1: 0x%X status_2: 0x%X", + camif_lite_node->hw_intf->hw_idx, + camif_lite_node->res_id, + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1], + th_payload->evt_status_arr[2]); + return rc; + } + + cam_isp_hw_get_timestamp(&evt_payload->ts); + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + th_payload->evt_payload_priv = evt_payload; + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +static int cam_vfe_camif_lite_handle_irq_bottom_half( + void *handler_priv, + void *evt_payload_priv) +{ + int ret = CAM_VFE_IRQ_STATUS_MAX; + struct cam_isp_resource_node *camif_lite_node; + struct cam_vfe_mux_camif_lite_data *camif_lite_priv; + struct cam_vfe_top_irq_evt_payload *payload; + struct cam_isp_hw_event_info evt_info; + struct cam_vfe_soc_private *soc_private = NULL; + uint32_t irq_status[CAM_IFE_IRQ_REGISTERS_MAX] = {0}; + int i = 0; + + if (!handler_priv || !evt_payload_priv) { + CAM_ERR(CAM_ISP, "Invalid params"); + return ret; + } + + camif_lite_node = handler_priv; + camif_lite_priv = camif_lite_node->res_priv; + payload = evt_payload_priv; + + soc_private = camif_lite_priv->soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Invalid soc_private"); + return -ENODEV; + } + + for (i = 0; i < CAM_IFE_IRQ_REGISTERS_MAX; i++) + irq_status[i] = payload->irq_reg_val[i]; + + evt_info.hw_idx = camif_lite_node->hw_intf->hw_idx; + evt_info.res_id = camif_lite_node->res_id; + evt_info.res_type = camif_lite_node->res_type; + + CAM_DBG(CAM_ISP, + "VFE:%d CAMIF LITE:%d IRQ status_0: 0x%X status_1: 0x%X status_2: 0x%X", + evt_info.hw_idx, evt_info.res_id, + irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS0], + irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1], + irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS2]); + + if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_lite_priv->reg_data->sof_irq_mask) { + CAM_DBG(CAM_ISP, "VFE:%d CAMIF LITE:%d Received SOF", + evt_info.hw_idx, evt_info.res_id); + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + + if (camif_lite_priv->event_cb) + camif_lite_priv->event_cb(camif_lite_priv->priv, + CAM_ISP_HW_EVENT_SOF, (void *)&evt_info); + } + + if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_lite_priv->reg_data->epoch0_irq_mask) { + CAM_DBG(CAM_ISP, "VFE:%d CAMIF LITE:%d Received EPOCH", + evt_info.hw_idx, evt_info.res_id); + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + + if (camif_lite_priv->event_cb) + camif_lite_priv->event_cb(camif_lite_priv->priv, + CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info); + } + + if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_lite_priv->reg_data->eof_irq_mask) { + CAM_DBG(CAM_ISP, "VFE:%d CAMIF LITE:%d Received EOF", + evt_info.hw_idx, evt_info.res_id); + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + + if (camif_lite_priv->event_cb) + camif_lite_priv->event_cb(camif_lite_priv->priv, + CAM_ISP_HW_EVENT_EOF, (void *)&evt_info); + } + + if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS0] + & camif_lite_priv->reg_data->error_irq_mask0) { + CAM_ERR(CAM_ISP, "VFE:%d Overflow", + camif_lite_node->hw_intf->hw_idx); + + evt_info.err_type = CAM_VFE_IRQ_STATUS_OVERFLOW; + + if (camif_lite_priv->event_cb) + camif_lite_priv->event_cb(camif_lite_priv->priv, + CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_OVERFLOW; + + cam_vfe_camif_lite_print_status(irq_status, ret, + camif_lite_priv); + + if (camif_lite_priv->camif_debug & CAMIF_DEBUG_ENABLE_REG_DUMP) + cam_vfe_camif_lite_reg_dump(camif_lite_node); + } + + if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS2]) { + CAM_ERR(CAM_ISP, "VFE:%d Violation", + camif_lite_node->hw_intf->hw_idx); + + evt_info.err_type = CAM_VFE_IRQ_STATUS_VIOLATION; + + if (camif_lite_priv->event_cb) + camif_lite_priv->event_cb(camif_lite_priv->priv, + CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_VIOLATION; + + cam_vfe_camif_lite_print_status(irq_status, ret, + camif_lite_priv); + + if (camif_lite_priv->camif_debug & CAMIF_DEBUG_ENABLE_REG_DUMP) + cam_vfe_camif_lite_reg_dump(camif_lite_node); + } + + cam_vfe_camif_lite_put_evt_payload(camif_lite_priv, &payload); + + CAM_DBG(CAM_ISP, "returning status = %d", ret); + return ret; +} + +int cam_vfe_camif_lite_ver3_init( + struct cam_hw_intf *hw_intf, + struct cam_hw_soc_info *soc_info, + void *camif_lite_hw_info, + struct cam_isp_resource_node *camif_lite_node, + void *vfe_irq_controller) +{ + struct cam_vfe_mux_camif_lite_data *camif_lite_priv = NULL; + struct cam_vfe_camif_lite_ver3_hw_info *camif_lite_info = + camif_lite_hw_info; + int i = 0; + + CAM_DBG(CAM_ISP, "VFE:%d CAMIF LITE:%d Init", + camif_lite_node->res_id, camif_lite_node->res_id); + + camif_lite_priv = kzalloc(sizeof(*camif_lite_priv), + GFP_KERNEL); + if (!camif_lite_priv) + return -ENOMEM; + + camif_lite_node->res_priv = camif_lite_priv; + + camif_lite_priv->mem_base = + soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base; + camif_lite_priv->camif_lite_reg = camif_lite_info->camif_lite_reg; + camif_lite_priv->common_reg = camif_lite_info->common_reg; + camif_lite_priv->reg_data = camif_lite_info->reg_data; + camif_lite_priv->hw_intf = hw_intf; + camif_lite_priv->soc_info = soc_info; + camif_lite_priv->vfe_irq_controller = vfe_irq_controller; + + camif_lite_node->init = NULL; + camif_lite_node->deinit = NULL; + camif_lite_node->start = cam_vfe_camif_lite_resource_start; + camif_lite_node->stop = cam_vfe_camif_lite_resource_stop; + camif_lite_node->process_cmd = cam_vfe_camif_lite_process_cmd; + camif_lite_node->top_half_handler = + cam_vfe_camif_lite_handle_irq_top_half; + camif_lite_node->bottom_half_handler = + cam_vfe_camif_lite_handle_irq_bottom_half; + + spin_lock_init(&camif_lite_priv->spin_lock); + INIT_LIST_HEAD(&camif_lite_priv->free_payload_list); + for (i = 0; i < CAM_VFE_CAMIF_LITE_EVT_MAX; i++) { + INIT_LIST_HEAD(&camif_lite_priv->evt_payload[i].list); + list_add_tail(&camif_lite_priv->evt_payload[i].list, + &camif_lite_priv->free_payload_list); + } + + return 0; +} + +int cam_vfe_camif_lite_ver3_deinit( + struct cam_isp_resource_node *camif_lite_node) +{ + struct cam_vfe_mux_camif_lite_data *camif_lite_priv = + camif_lite_node->res_priv; + int i = 0; + + CAM_DBG(CAM_ISP, "VFE:%d CAMIF LITE:%d Deinit", + camif_lite_node->hw_intf->hw_idx, camif_lite_node->res_id); + + INIT_LIST_HEAD(&camif_lite_priv->free_payload_list); + for (i = 0; i < CAM_VFE_CAMIF_LITE_EVT_MAX; i++) + INIT_LIST_HEAD(&camif_lite_priv->evt_payload[i].list); + + camif_lite_node->start = NULL; + camif_lite_node->stop = NULL; + camif_lite_node->process_cmd = NULL; + camif_lite_node->top_half_handler = NULL; + camif_lite_node->bottom_half_handler = NULL; + + camif_lite_node->res_priv = NULL; + + if (!camif_lite_priv) { + CAM_ERR(CAM_ISP, "Error. camif_priv is NULL"); + return -ENODEV; + } + + kfree(camif_lite_priv); + + return 0; +} + diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.h new file mode 100644 index 0000000000000000000000000000000000000000..54a38bdf41ca587c63d40ca5aead86a355a29aa1 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_CAMIF_LITE_VER3_H_ +#define _CAM_VFE_CAMIF_LITE_VER3_H_ + +#include "cam_isp_hw.h" +#include "cam_vfe_top.h" + +#define CAM_VFE_RDI_VER2_MAX 4 +#define CAM_VFE_CAMIF_LITE_EVT_MAX 256 + +struct cam_vfe_camif_lite_ver3_reg { + uint32_t lite_hw_version; + uint32_t lite_hw_status; + uint32_t lite_module_config; + uint32_t lite_skip_period; + uint32_t lite_irq_subsample_pattern; + uint32_t lite_epoch_irq; + uint32_t lite_debug_1; + uint32_t lite_debug_0; + uint32_t lite_test_bus_ctrl; + uint32_t camif_lite_spare; + uint32_t reg_update_cmd; +}; + +struct cam_vfe_camif_lite_ver3_reg_data { + uint32_t extern_reg_update_shift; + uint32_t operating_mode_shift; + uint32_t input_mux_sel_shift; + uint32_t reg_update_cmd_data; + uint32_t epoch_line_cfg; + uint32_t sof_irq_mask; + uint32_t epoch0_irq_mask; + uint32_t epoch1_irq_mask; + uint32_t eof_irq_mask; + uint32_t error_irq_mask0; + uint32_t error_irq_mask2; + uint32_t subscribe_irq_mask1; + uint32_t enable_diagnostic_hw; + uint32_t top_debug_cfg_en; +}; + +struct cam_vfe_camif_lite_ver3_hw_info { + struct cam_vfe_top_ver3_reg_offset_common *common_reg; + struct cam_vfe_camif_lite_ver3_reg *camif_lite_reg; + struct cam_vfe_camif_lite_ver3_reg_data *reg_data; +}; + +int cam_vfe_camif_lite_ver3_acquire_resource( + struct cam_isp_resource_node *camif_lite_res, + void *acquire_param); + +int cam_vfe_camif_lite_ver3_init( + struct cam_hw_intf *hw_intf, + struct cam_hw_soc_info *soc_info, + void *camif_lite_hw_info, + struct cam_isp_resource_node *camif_lite_node, + void *vfe_irq_controller); + +int cam_vfe_camif_lite_ver3_deinit( + struct cam_isp_resource_node *camif_node); + +#endif /* _CAM_VFE_CAMIF_LITE_VER3_H_ */ + diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c new file mode 100644 index 0000000000000000000000000000000000000000..c776888c9871101165a96a01540dec4722b72e02 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c @@ -0,0 +1,881 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include "cam_io_util.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_isp_hw.h" +#include "cam_vfe_hw_intf.h" +#include "cam_vfe_soc.h" +#include "cam_vfe_top.h" +#include "cam_vfe_top_ver2.h" +#include "cam_irq_controller.h" +#include "cam_tasklet_util.h" +#include "cam_vfe_camif_ver2.h" +#include "cam_debug_util.h" +#include "cam_cdm_util.h" +#include "cam_cpas_api.h" + +#define CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX 2 + +struct cam_vfe_mux_camif_data { + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + struct cam_vfe_camif_ver2_reg *camif_reg; + struct cam_vfe_top_ver2_reg_offset_common *common_reg; + struct cam_vfe_camif_reg_data *reg_data; + struct cam_hw_soc_info *soc_info; + + cam_hw_mgr_event_cb_func event_cb; + void *priv; + int irq_err_handle; + int irq_handle; + void *vfe_irq_controller; + struct cam_vfe_top_irq_evt_payload evt_payload[CAM_VFE_CAMIF_EVT_MAX]; + struct list_head free_payload_list; + spinlock_t spin_lock; + + enum cam_isp_hw_sync_mode sync_mode; + uint32_t dsp_mode; + uint32_t pix_pattern; + uint32_t first_pixel; + uint32_t first_line; + uint32_t last_pixel; + uint32_t last_line; + bool enable_sof_irq_debug; + uint32_t irq_debug_cnt; + uint32_t camif_debug; +}; + +static int cam_vfe_camif_get_evt_payload( + struct cam_vfe_mux_camif_data *camif_priv, + struct cam_vfe_top_irq_evt_payload **evt_payload) +{ + int rc = 0; + + spin_lock(&camif_priv->spin_lock); + if (list_empty(&camif_priv->free_payload_list)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No free payload"); + rc = -ENODEV; + goto done; + } + + *evt_payload = list_first_entry(&camif_priv->free_payload_list, + struct cam_vfe_top_irq_evt_payload, list); + list_del_init(&(*evt_payload)->list); +done: + spin_unlock(&camif_priv->spin_lock); + return rc; +} + +static int cam_vfe_camif_put_evt_payload( + struct cam_vfe_mux_camif_data *camif_priv, + struct cam_vfe_top_irq_evt_payload **evt_payload) +{ + unsigned long flags; + + if (!camif_priv) { + CAM_ERR(CAM_ISP, "Invalid param core_info NULL"); + return -EINVAL; + } + if (*evt_payload == NULL) { + CAM_ERR(CAM_ISP, "No payload to put"); + return -EINVAL; + } + + spin_lock_irqsave(&camif_priv->spin_lock, flags); + list_add_tail(&(*evt_payload)->list, &camif_priv->free_payload_list); + *evt_payload = NULL; + spin_unlock_irqrestore(&camif_priv->spin_lock, flags); + + CAM_DBG(CAM_ISP, "Done"); + return 0; +} + +static int cam_vfe_camif_err_irq_top_half( + uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc; + int i; + struct cam_isp_resource_node *camif_node; + struct cam_vfe_mux_camif_data *camif_priv; + struct cam_vfe_top_irq_evt_payload *evt_payload; + bool error_flag = false; + + CAM_DBG(CAM_ISP, "IRQ status_0 = %x, IRQ status_1 = %x", + th_payload->evt_status_arr[0], th_payload->evt_status_arr[1]); + + camif_node = th_payload->handler_priv; + camif_priv = camif_node->res_priv; + /* + * need to handle overflow condition here, otherwise irq storm + * will block everything + */ + if (th_payload->evt_status_arr[1] || (th_payload->evt_status_arr[0] & + camif_priv->reg_data->error_irq_mask0)) { + CAM_ERR(CAM_ISP, + "Camif Error: vfe:%d: IRQ STATUS_0=0x%x STATUS_1=0x%x", + camif_node->hw_intf->hw_idx, + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1]); + CAM_ERR(CAM_ISP, "Stopping further IRQ processing from vfe=%d", + camif_node->hw_intf->hw_idx); + cam_irq_controller_disable_irq(camif_priv->vfe_irq_controller, + camif_priv->irq_err_handle); + cam_irq_controller_clear_and_mask(evt_id, + camif_priv->vfe_irq_controller); + error_flag = true; + } + + rc = cam_vfe_camif_get_evt_payload(camif_priv, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "No tasklet_cmd is free in queue"); + CAM_ERR_RATE_LIMIT(CAM_ISP, "IRQ STATUS_0=0x%x STATUS_1=0x%x", + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1]); + return rc; + } + + cam_isp_hw_get_timestamp(&evt_payload->ts); + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + evt_payload->irq_reg_val[i] = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->violation_status); + + if (error_flag) + CAM_INFO(CAM_ISP, "Violation status = 0x%x", + evt_payload->irq_reg_val[2]); + + th_payload->evt_payload_priv = evt_payload; + + return rc; +} + +static int cam_vfe_camif_validate_pix_pattern(uint32_t pattern) +{ + int rc; + + switch (pattern) { + case CAM_ISP_PATTERN_BAYER_RGRGRG: + case CAM_ISP_PATTERN_BAYER_GRGRGR: + case CAM_ISP_PATTERN_BAYER_BGBGBG: + case CAM_ISP_PATTERN_BAYER_GBGBGB: + case CAM_ISP_PATTERN_YUV_YCBYCR: + case CAM_ISP_PATTERN_YUV_YCRYCB: + case CAM_ISP_PATTERN_YUV_CBYCRY: + case CAM_ISP_PATTERN_YUV_CRYCBY: + rc = 0; + break; + default: + CAM_ERR(CAM_ISP, "Error! Invalid pix pattern:%d", pattern); + rc = -EINVAL; + break; + } + return rc; +} + +static int cam_vfe_camif_get_reg_update( + struct cam_isp_resource_node *camif_res, + void *cmd_args, uint32_t arg_size) +{ + uint32_t size = 0; + uint32_t reg_val_pair[2]; + struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; + struct cam_vfe_mux_camif_data *rsrc_data = NULL; + + if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { + CAM_ERR(CAM_ISP, "Invalid cmd size"); + return -EINVAL; + } + + if (!cdm_args || !cdm_args->res) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + cdm_util_ops = (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; + + if (!cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid CDM ops"); + return -EINVAL; + } + + size = cdm_util_ops->cdm_required_size_reg_random(1); + /* since cdm returns dwords, we need to convert it into bytes */ + if ((size * 4) > cdm_args->cmd.size) { + CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d", + cdm_args->cmd.size, size); + return -EINVAL; + } + + rsrc_data = camif_res->res_priv; + reg_val_pair[0] = rsrc_data->camif_reg->reg_update_cmd; + reg_val_pair[1] = rsrc_data->reg_data->reg_update_cmd_data; + CAM_DBG(CAM_ISP, "CAMIF reg_update_cmd %x offset %x", + reg_val_pair[1], reg_val_pair[0]); + + cdm_util_ops->cdm_write_regrandom(cdm_args->cmd.cmd_buf_addr, + 1, reg_val_pair); + + cdm_args->cmd.used_bytes = size * 4; + + return 0; +} + +int cam_vfe_camif_ver2_acquire_resource( + struct cam_isp_resource_node *camif_res, + void *acquire_param) +{ + struct cam_vfe_mux_camif_data *camif_data; + struct cam_vfe_acquire_args *acquire_data; + + int rc = 0; + + camif_data = (struct cam_vfe_mux_camif_data *)camif_res->res_priv; + acquire_data = (struct cam_vfe_acquire_args *)acquire_param; + + rc = cam_vfe_camif_validate_pix_pattern( + acquire_data->vfe_in.in_port->test_pattern); + if (rc) + return rc; + + camif_data->sync_mode = acquire_data->vfe_in.sync_mode; + camif_data->pix_pattern = acquire_data->vfe_in.in_port->test_pattern; + camif_data->dsp_mode = acquire_data->vfe_in.in_port->dsp_mode; + camif_data->first_pixel = acquire_data->vfe_in.in_port->left_start; + camif_data->last_pixel = acquire_data->vfe_in.in_port->left_stop; + camif_data->first_line = acquire_data->vfe_in.in_port->line_start; + camif_data->last_line = acquire_data->vfe_in.in_port->line_stop; + camif_data->event_cb = acquire_data->event_cb; + camif_data->priv = acquire_data->priv; + + CAM_DBG(CAM_ISP, "hw id:%d pix_pattern:%d dsp_mode=%d", + camif_res->hw_intf->hw_idx, + camif_data->pix_pattern, camif_data->dsp_mode); + return rc; +} + +static int cam_vfe_camif_resource_init( + struct cam_isp_resource_node *camif_res, + void *init_args, uint32_t arg_size) +{ + struct cam_vfe_mux_camif_data *camif_data; + struct cam_hw_soc_info *soc_info; + int rc = 0; + + if (!camif_res) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + camif_data = (struct cam_vfe_mux_camif_data *)camif_res->res_priv; + + soc_info = camif_data->soc_info; + + if ((camif_data->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) && + (camif_data->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) { + rc = cam_vfe_soc_enable_clk(soc_info, CAM_VFE_DSP_CLK_NAME); + if (rc) + CAM_ERR(CAM_ISP, "failed to enable dsp clk"); + } + + return rc; +} + +static int cam_vfe_camif_resource_deinit( + struct cam_isp_resource_node *camif_res, + void *init_args, uint32_t arg_size) +{ + struct cam_vfe_mux_camif_data *camif_data; + struct cam_hw_soc_info *soc_info; + int rc = 0; + + if (!camif_res) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + camif_data = (struct cam_vfe_mux_camif_data *)camif_res->res_priv; + + soc_info = camif_data->soc_info; + + if ((camif_data->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) && + (camif_data->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) { + rc = cam_vfe_soc_disable_clk(soc_info, CAM_VFE_DSP_CLK_NAME); + if (rc) + CAM_ERR(CAM_ISP, "failed to disable dsp clk"); + } + + return rc; +} + +static int cam_vfe_camif_resource_start( + struct cam_isp_resource_node *camif_res) +{ + struct cam_vfe_mux_camif_data *rsrc_data; + uint32_t val = 0; + uint32_t epoch0_irq_mask; + uint32_t epoch1_irq_mask; + uint32_t computed_epoch_line_cfg; + int rc = 0; + uint32_t err_irq_mask[CAM_IFE_IRQ_REGISTERS_MAX]; + uint32_t irq_mask[CAM_IFE_IRQ_REGISTERS_MAX]; + struct cam_vfe_soc_private *soc_private; + + if (!camif_res) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + if (camif_res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Error! Invalid camif res res_state:%d", + camif_res->res_state); + return -EINVAL; + } + + rsrc_data = (struct cam_vfe_mux_camif_data *)camif_res->res_priv; + err_irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0] = + rsrc_data->reg_data->error_irq_mask0; + err_irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = + rsrc_data->reg_data->error_irq_mask1; + irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0] = + rsrc_data->reg_data->subscribe_irq_mask0; + irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = + rsrc_data->reg_data->subscribe_irq_mask1; + + soc_private = rsrc_data->soc_info->soc_private; + + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error! soc_private NULL"); + return -ENODEV; + } + + /*config vfe core*/ + val = (rsrc_data->pix_pattern << + rsrc_data->reg_data->pixel_pattern_shift); + if (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) + val |= (1 << rsrc_data->reg_data->extern_reg_update_shift); + + if ((rsrc_data->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) && + (rsrc_data->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) { + /* DSP mode reg val is CAM_ISP_DSP_MODE - 1 */ + val |= (((rsrc_data->dsp_mode - 1) & + rsrc_data->reg_data->dsp_mode_mask) << + rsrc_data->reg_data->dsp_mode_shift); + val |= (0x1 << rsrc_data->reg_data->dsp_en_shift); + } + + cam_io_w_mb(val, rsrc_data->mem_base + rsrc_data->common_reg->core_cfg); + + CAM_DBG(CAM_ISP, "hw id:%d core_cfg val:%d", camif_res->hw_intf->hw_idx, + val); + + /* disable the CGC for stats */ + cam_io_w_mb(0xFFFFFFFF, rsrc_data->mem_base + + rsrc_data->common_reg->module_ctrl[ + CAM_VFE_TOP_VER2_MODULE_STATS]->cgc_ovd); + + /* epoch config */ + switch (soc_private->cpas_version) { + case CAM_CPAS_TITAN_170_V100: + case CAM_CPAS_TITAN_170_V110: + case CAM_CPAS_TITAN_170_V120: + cam_io_w_mb(rsrc_data->reg_data->epoch_line_cfg, + rsrc_data->mem_base + + rsrc_data->camif_reg->epoch_irq); + break; + default: + epoch0_irq_mask = ((rsrc_data->last_line - + rsrc_data->first_line) / 2) + + rsrc_data->first_line; + epoch1_irq_mask = rsrc_data->reg_data->epoch_line_cfg & + 0xFFFF; + computed_epoch_line_cfg = (epoch0_irq_mask << 16) | + epoch1_irq_mask; + cam_io_w_mb(computed_epoch_line_cfg, + rsrc_data->mem_base + + rsrc_data->camif_reg->epoch_irq); + CAM_DBG(CAM_ISP, "first_line: %u\n" + "last_line: %u\n" + "epoch_line_cfg: 0x%x", + rsrc_data->first_line, + rsrc_data->last_line, + computed_epoch_line_cfg); + break; + } + + camif_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + /* Reg Update */ + cam_io_w_mb(rsrc_data->reg_data->reg_update_cmd_data, + rsrc_data->mem_base + rsrc_data->camif_reg->reg_update_cmd); + CAM_DBG(CAM_ISP, "hw id:%d RUP val:%d", camif_res->hw_intf->hw_idx, + rsrc_data->reg_data->reg_update_cmd_data); + + /* disable sof irq debug flag */ + rsrc_data->enable_sof_irq_debug = false; + rsrc_data->irq_debug_cnt = 0; + + if (rsrc_data->camif_debug & + CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS) { + val = cam_io_r_mb(rsrc_data->mem_base + + rsrc_data->camif_reg->vfe_diag_config); + val |= rsrc_data->reg_data->enable_diagnostic_hw; + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->camif_reg->vfe_diag_config); + } + + if (!rsrc_data->irq_handle) { + rsrc_data->irq_handle = cam_irq_controller_subscribe_irq( + rsrc_data->vfe_irq_controller, + CAM_IRQ_PRIORITY_1, + irq_mask, + camif_res, + camif_res->top_half_handler, + camif_res->bottom_half_handler, + camif_res->tasklet_info, + &tasklet_bh_api); + if (rsrc_data->irq_handle < 1) { + CAM_ERR(CAM_ISP, "IRQ handle subscribe failure"); + rc = -ENOMEM; + rsrc_data->irq_handle = 0; + } + } + + if (!rsrc_data->irq_err_handle) { + rsrc_data->irq_err_handle = cam_irq_controller_subscribe_irq( + rsrc_data->vfe_irq_controller, + CAM_IRQ_PRIORITY_0, + err_irq_mask, + camif_res, + cam_vfe_camif_err_irq_top_half, + camif_res->bottom_half_handler, + camif_res->tasklet_info, + &tasklet_bh_api); + if (rsrc_data->irq_err_handle < 1) { + CAM_ERR(CAM_ISP, "Error IRQ handle subscribe failure"); + rc = -ENOMEM; + rsrc_data->irq_err_handle = 0; + } + } + + CAM_DBG(CAM_ISP, "Start Camif IFE %d Done", camif_res->hw_intf->hw_idx); + return 0; +} + +static int cam_vfe_camif_reg_dump( + struct cam_isp_resource_node *camif_res) +{ + struct cam_vfe_mux_camif_data *camif_priv; + struct cam_vfe_soc_private *soc_private; + uint32_t offset, val, wm_idx; + + if (!camif_res) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + if ((camif_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) || + (camif_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE)) + return 0; + + camif_priv = (struct cam_vfe_mux_camif_data *)camif_res->res_priv; + for (offset = 0x0; offset < 0x1160; offset += 0x4) { + val = cam_soc_util_r(camif_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%x value 0x%x", offset, val); + } + + for (offset = 0x2000; offset <= 0x20B8; offset += 0x4) { + val = cam_soc_util_r(camif_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%x value 0x%x", offset, val); + } + + for (wm_idx = 0; wm_idx <= 23; wm_idx++) { + for (offset = 0x2200 + 0x100 * wm_idx; + offset < 0x2278 + 0x100 * wm_idx; offset += 0x4) { + val = cam_soc_util_r(camif_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, + "offset 0x%x value 0x%x", offset, val); + } + } + + soc_private = camif_priv->soc_info->soc_private; + if (soc_private->cpas_version == CAM_CPAS_TITAN_175_V120 || + soc_private->cpas_version == CAM_CPAS_TITAN_175_V130) { + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x3A20, true, &val); + CAM_INFO(CAM_ISP, "IFE0_nRDI_MAXWR_LOW offset 0x3A20 val 0x%x", + val); + + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x5420, true, &val); + CAM_INFO(CAM_ISP, "IFE1_nRDI_MAXWR_LOW offset 0x5420 val 0x%x", + val); + + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x3620, true, &val); + CAM_INFO(CAM_ISP, + "IFE0123_RDI_WR_MAXWR_LOW offset 0x3620 val 0x%x", val); + + } else if (soc_private->cpas_version < CAM_CPAS_TITAN_175_V120) { + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x420, true, &val); + CAM_INFO(CAM_ISP, "IFE02_MAXWR_LOW offset 0x420 val 0x%x", val); + + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x820, true, &val); + CAM_INFO(CAM_ISP, "IFE13_MAXWR_LOW offset 0x820 val 0x%x", val); + } + + return 0; +} + +static int cam_vfe_camif_resource_stop( + struct cam_isp_resource_node *camif_res) +{ + struct cam_vfe_mux_camif_data *camif_priv; + struct cam_vfe_camif_ver2_reg *camif_reg; + int rc = 0; + uint32_t val = 0; + + if (!camif_res) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + if (camif_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED || + camif_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE) + return 0; + + camif_priv = (struct cam_vfe_mux_camif_data *)camif_res->res_priv; + camif_reg = camif_priv->camif_reg; + + if ((camif_priv->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) && + (camif_priv->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) { + val = cam_io_r_mb(camif_priv->mem_base + + camif_priv->common_reg->core_cfg); + val &= (~(1 << camif_priv->reg_data->dsp_en_shift)); + cam_io_w_mb(val, camif_priv->mem_base + + camif_priv->common_reg->core_cfg); + } + + if (camif_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + camif_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + val = cam_io_r_mb(camif_priv->mem_base + + camif_priv->camif_reg->vfe_diag_config); + if (val & camif_priv->reg_data->enable_diagnostic_hw) { + val &= ~camif_priv->reg_data->enable_diagnostic_hw; + cam_io_w_mb(val, camif_priv->mem_base + + camif_priv->camif_reg->vfe_diag_config); + } + + if (camif_priv->irq_handle) { + cam_irq_controller_unsubscribe_irq( + camif_priv->vfe_irq_controller, camif_priv->irq_handle); + camif_priv->irq_handle = 0; + } + + if (camif_priv->irq_err_handle) { + cam_irq_controller_unsubscribe_irq( + camif_priv->vfe_irq_controller, + camif_priv->irq_err_handle); + camif_priv->irq_err_handle = 0; + } + + return rc; +} + +static int cam_vfe_camif_sof_irq_debug( + struct cam_isp_resource_node *rsrc_node, void *cmd_args) +{ + struct cam_vfe_mux_camif_data *camif_priv; + uint32_t *enable_sof_irq = (uint32_t *)cmd_args; + + camif_priv = + (struct cam_vfe_mux_camif_data *)rsrc_node->res_priv; + + if (*enable_sof_irq == 1) + camif_priv->enable_sof_irq_debug = true; + else + camif_priv->enable_sof_irq_debug = false; + + return 0; +} + +static int cam_vfe_camif_process_cmd(struct cam_isp_resource_node *rsrc_node, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = -EINVAL; + struct cam_vfe_mux_camif_data *camif_priv = NULL; + + if (!rsrc_node || !cmd_args) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_REG_UPDATE: + rc = cam_vfe_camif_get_reg_update(rsrc_node, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_SOF_IRQ_DEBUG: + rc = cam_vfe_camif_sof_irq_debug(rsrc_node, cmd_args); + break; + case CAM_ISP_HW_CMD_SET_CAMIF_DEBUG: + camif_priv = + (struct cam_vfe_mux_camif_data *)rsrc_node->res_priv; + camif_priv->camif_debug = *((uint32_t *)cmd_args); + break; + default: + CAM_ERR(CAM_ISP, + "unsupported process command:%d", cmd_type); + break; + } + + return rc; +} + +static int cam_vfe_camif_handle_irq_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc; + int i; + struct cam_isp_resource_node *camif_node; + struct cam_vfe_mux_camif_data *camif_priv; + struct cam_vfe_top_irq_evt_payload *evt_payload; + + camif_node = th_payload->handler_priv; + camif_priv = camif_node->res_priv; + + CAM_DBG(CAM_ISP, "IRQ status_0 = %x", th_payload->evt_status_arr[0]); + CAM_DBG(CAM_ISP, "IRQ status_1 = %x", th_payload->evt_status_arr[1]); + + rc = cam_vfe_camif_get_evt_payload(camif_priv, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No tasklet_cmd is free in queue"); + CAM_ERR_RATE_LIMIT(CAM_ISP, "IRQ status0=0x%x status1=0x%x", + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1]); + return rc; + } + + cam_isp_hw_get_timestamp(&evt_payload->ts); + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + th_payload->evt_payload_priv = evt_payload; + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +static int cam_vfe_camif_handle_irq_bottom_half(void *handler_priv, + void *evt_payload_priv) +{ + int ret = CAM_VFE_IRQ_STATUS_MAX; + struct cam_isp_resource_node *camif_node; + struct cam_vfe_mux_camif_data *camif_priv; + struct cam_vfe_top_irq_evt_payload *payload; + struct cam_isp_hw_event_info evt_info; + uint32_t irq_status0; + uint32_t irq_status1; + uint32_t val; + + if (!handler_priv || !evt_payload_priv) { + CAM_ERR(CAM_ISP, "Invalid params"); + return ret; + } + + camif_node = handler_priv; + camif_priv = camif_node->res_priv; + payload = evt_payload_priv; + irq_status0 = payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS0]; + irq_status1 = payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS1]; + + evt_info.hw_idx = camif_node->hw_intf->hw_idx; + evt_info.res_id = camif_node->res_id; + evt_info.res_type = camif_node->res_type; + + CAM_DBG(CAM_ISP, "irq_status_0 = 0x%x irq_status_1 = 0x%x", + irq_status0, irq_status1); + + if (irq_status0 & camif_priv->reg_data->eof_irq_mask) { + CAM_DBG(CAM_ISP, "Received EOF"); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_EOF, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status0 & camif_priv->reg_data->sof_irq_mask) { + if ((camif_priv->enable_sof_irq_debug) && + (camif_priv->irq_debug_cnt <= + CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "Received SOF"); + + camif_priv->irq_debug_cnt++; + if (camif_priv->irq_debug_cnt == + CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX) { + camif_priv->enable_sof_irq_debug = + false; + camif_priv->irq_debug_cnt = 0; + } + } else + CAM_DBG(CAM_ISP, "Received SOF"); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_SOF, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status0 & camif_priv->reg_data->reg_update_irq_mask) { + CAM_DBG(CAM_ISP, "Received REG_UPDATE_ACK"); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_REG_UPDATE, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status0 & camif_priv->reg_data->epoch0_irq_mask) { + CAM_DBG(CAM_ISP, "Received EPOCH"); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status0 & camif_priv->reg_data->error_irq_mask0) { + CAM_DBG(CAM_ISP, "Received ERROR"); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info); + + CAM_INFO(CAM_ISP, "Violation status = %x", + payload->irq_reg_val[2]); + + ret = CAM_VFE_IRQ_STATUS_OVERFLOW; + if (camif_priv->camif_debug & CAMIF_DEBUG_ENABLE_REG_DUMP) + cam_vfe_camif_reg_dump(camif_node->res_priv); + } + + if (irq_status1 & camif_priv->reg_data->error_irq_mask1) { + CAM_DBG(CAM_ISP, "Received ERROR"); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info); + + CAM_INFO(CAM_ISP, "Violation status = %x", + payload->irq_reg_val[2]); + + ret = CAM_VFE_IRQ_STATUS_OVERFLOW; + if (camif_priv->camif_debug & CAMIF_DEBUG_ENABLE_REG_DUMP) + cam_vfe_camif_reg_dump(camif_node->res_priv); + } + + if (camif_priv->camif_debug & CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS) { + val = cam_io_r(camif_priv->mem_base + + camif_priv->camif_reg->vfe_diag_sensor_status); + CAM_DBG(CAM_ISP, "VFE_DIAG_SENSOR_STATUS: 0x%x", + camif_priv->mem_base, val); + } + + cam_vfe_camif_put_evt_payload(camif_priv, &payload); + + CAM_DBG(CAM_ISP, "returning status = %d", ret); + return ret; +} + +int cam_vfe_camif_ver2_init( + struct cam_hw_intf *hw_intf, + struct cam_hw_soc_info *soc_info, + void *camif_hw_info, + struct cam_isp_resource_node *camif_node, + void *vfe_irq_controller) +{ + struct cam_vfe_mux_camif_data *camif_priv = NULL; + struct cam_vfe_camif_ver2_hw_info *camif_info = camif_hw_info; + int i = 0; + + camif_priv = kzalloc(sizeof(struct cam_vfe_mux_camif_data), + GFP_KERNEL); + if (!camif_priv) { + CAM_DBG(CAM_ISP, "Error! Failed to alloc for camif_priv"); + return -ENOMEM; + } + + camif_node->res_priv = camif_priv; + + camif_priv->mem_base = soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base; + camif_priv->camif_reg = camif_info->camif_reg; + camif_priv->common_reg = camif_info->common_reg; + camif_priv->reg_data = camif_info->reg_data; + camif_priv->hw_intf = hw_intf; + camif_priv->soc_info = soc_info; + camif_priv->vfe_irq_controller = vfe_irq_controller; + + camif_node->init = cam_vfe_camif_resource_init; + camif_node->deinit = cam_vfe_camif_resource_deinit; + camif_node->start = cam_vfe_camif_resource_start; + camif_node->stop = cam_vfe_camif_resource_stop; + camif_node->process_cmd = cam_vfe_camif_process_cmd; + camif_node->top_half_handler = cam_vfe_camif_handle_irq_top_half; + camif_node->bottom_half_handler = cam_vfe_camif_handle_irq_bottom_half; + + spin_lock_init(&camif_priv->spin_lock); + INIT_LIST_HEAD(&camif_priv->free_payload_list); + for (i = 0; i < CAM_VFE_CAMIF_EVT_MAX; i++) { + INIT_LIST_HEAD(&camif_priv->evt_payload[i].list); + list_add_tail(&camif_priv->evt_payload[i].list, + &camif_priv->free_payload_list); + } + + return 0; +} + +int cam_vfe_camif_ver2_deinit( + struct cam_isp_resource_node *camif_node) +{ + struct cam_vfe_mux_camif_data *camif_priv = camif_node->res_priv; + int i = 0; + + INIT_LIST_HEAD(&camif_priv->free_payload_list); + for (i = 0; i < CAM_VFE_CAMIF_EVT_MAX; i++) + INIT_LIST_HEAD(&camif_priv->evt_payload[i].list); + + camif_node->start = NULL; + camif_node->stop = NULL; + camif_node->process_cmd = NULL; + camif_node->top_half_handler = NULL; + camif_node->bottom_half_handler = NULL; + + camif_node->res_priv = NULL; + + if (!camif_priv) { + CAM_ERR(CAM_ISP, "Error! camif_priv is NULL"); + return -ENODEV; + } + + kfree(camif_priv); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.h new file mode 100644 index 0000000000000000000000000000000000000000..f071a0627bbcb83612c9deec8de68e99d5cc13a8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_CAMIF_VER2_H_ +#define _CAM_VFE_CAMIF_VER2_H_ + +#include "cam_isp_hw.h" +#include "cam_vfe_top.h" + +struct cam_vfe_camif_ver2_reg { + uint32_t camif_cmd; + uint32_t camif_config; + uint32_t line_skip_pattern; + uint32_t pixel_skip_pattern; + uint32_t skip_period; + uint32_t irq_subsample_pattern; + uint32_t epoch_irq; + uint32_t raw_crop_width_cfg; + uint32_t raw_crop_height_cfg; + uint32_t reg_update_cmd; + uint32_t vfe_diag_config; + uint32_t vfe_diag_sensor_status; +}; + +struct cam_vfe_camif_reg_data { + uint32_t raw_crop_first_pixel_shift; + uint32_t raw_crop_first_pixel_mask; + + uint32_t raw_crop_last_pixel_shift; + uint32_t raw_crop_last_pixel_mask; + + uint32_t raw_crop_first_line_shift; + uint32_t raw_crop_first_line_mask; + + uint32_t raw_crop_last_line_shift; + uint32_t raw_crop_last_line_mask; + + uint32_t input_mux_sel_shift; + uint32_t input_mux_sel_mask; + uint32_t extern_reg_update_shift; + uint32_t extern_reg_update_mask; + + uint32_t pixel_pattern_shift; + uint32_t pixel_pattern_mask; + + uint32_t dsp_mode_shift; + uint32_t dsp_mode_mask; + uint32_t dsp_en_shift; + uint32_t dsp_en_mask; + + uint32_t reg_update_cmd_data; + uint32_t epoch_line_cfg; + uint32_t sof_irq_mask; + uint32_t epoch0_irq_mask; + uint32_t reg_update_irq_mask; + uint32_t eof_irq_mask; + uint32_t error_irq_mask0; + uint32_t error_irq_mask1; + uint32_t subscribe_irq_mask0; + uint32_t subscribe_irq_mask1; + + uint32_t enable_diagnostic_hw; +}; + +struct cam_vfe_camif_ver2_hw_info { + struct cam_vfe_top_ver2_reg_offset_common *common_reg; + struct cam_vfe_camif_ver2_reg *camif_reg; + struct cam_vfe_camif_reg_data *reg_data; +}; + +int cam_vfe_camif_ver2_acquire_resource( + struct cam_isp_resource_node *camif_res, + void *acquire_param); + +int cam_vfe_camif_ver2_init( + struct cam_hw_intf *hw_intf, + struct cam_hw_soc_info *soc_info, + void *camif_hw_info, + struct cam_isp_resource_node *camif_node, + void *vfe_irq_controller); + +int cam_vfe_camif_ver2_deinit( + struct cam_isp_resource_node *camif_node); + +#endif /* _CAM_VFE_CAMIF_VER2_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c new file mode 100644 index 0000000000000000000000000000000000000000..12cc394d51b343984c973d6cec32236c38a54c27 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c @@ -0,0 +1,1434 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include "cam_io_util.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_isp_hw.h" +#include "cam_vfe_hw_intf.h" +#include "cam_vfe_soc.h" +#include "cam_vfe_top.h" +#include "cam_vfe_top_ver3.h" +#include "cam_irq_controller.h" +#include "cam_tasklet_util.h" +#include "cam_vfe_camif_ver3.h" +#include "cam_debug_util.h" +#include "cam_cdm_util.h" +#include "cam_cpas_api.h" +#include "cam_trace.h" + +#define CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX 2 + +struct cam_vfe_mux_camif_ver3_data { + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + struct cam_vfe_camif_ver3_pp_clc_reg *camif_reg; + struct cam_vfe_top_ver3_reg_offset_common *common_reg; + struct cam_vfe_camif_ver3_reg_data *reg_data; + struct cam_hw_soc_info *soc_info; + struct cam_vfe_camif_common_cfg cam_common_cfg; + + cam_hw_mgr_event_cb_func event_cb; + void *priv; + int irq_err_handle; + int irq_handle; + int sof_irq_handle; + void *vfe_irq_controller; + struct cam_vfe_top_irq_evt_payload evt_payload[CAM_VFE_CAMIF_EVT_MAX]; + struct list_head free_payload_list; + spinlock_t spin_lock; + + enum cam_isp_hw_sync_mode sync_mode; + uint32_t dsp_mode; + uint32_t pix_pattern; + uint32_t first_pixel; + uint32_t first_line; + uint32_t last_pixel; + uint32_t last_line; + bool enable_sof_irq_debug; + uint32_t irq_debug_cnt; + uint32_t camif_debug; + uint32_t horizontal_bin; + uint32_t qcfa_bin; +}; + +static int cam_vfe_camif_ver3_get_evt_payload( + struct cam_vfe_mux_camif_ver3_data *camif_priv, + struct cam_vfe_top_irq_evt_payload **evt_payload) +{ + int rc = 0; + + spin_lock(&camif_priv->spin_lock); + if (list_empty(&camif_priv->free_payload_list)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No free CAMIF event payload"); + rc = -ENODEV; + goto done; + } + + *evt_payload = list_first_entry(&camif_priv->free_payload_list, + struct cam_vfe_top_irq_evt_payload, list); + list_del_init(&(*evt_payload)->list); +done: + spin_unlock(&camif_priv->spin_lock); + return rc; +} + +static int cam_vfe_camif_ver3_put_evt_payload( + struct cam_vfe_mux_camif_ver3_data *camif_priv, + struct cam_vfe_top_irq_evt_payload **evt_payload) +{ + unsigned long flags; + + if (!camif_priv) { + CAM_ERR(CAM_ISP, "Invalid param core_info NULL"); + return -EINVAL; + } + if (*evt_payload == NULL) { + CAM_ERR(CAM_ISP, "No payload to put"); + return -EINVAL; + } + + spin_lock_irqsave(&camif_priv->spin_lock, flags); + list_add_tail(&(*evt_payload)->list, &camif_priv->free_payload_list); + *evt_payload = NULL; + spin_unlock_irqrestore(&camif_priv->spin_lock, flags); + + CAM_DBG(CAM_ISP, "Done"); + return 0; +} + +static int cam_vfe_camif_ver3_err_irq_top_half( + uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc; + int i; + struct cam_isp_resource_node *camif_node; + struct cam_vfe_mux_camif_ver3_data *camif_priv; + struct cam_vfe_top_irq_evt_payload *evt_payload; + bool error_flag = false; + + camif_node = th_payload->handler_priv; + camif_priv = camif_node->res_priv; + /* + * need to handle overflow condition here, otherwise irq storm + * will block everything + */ + if (th_payload->evt_status_arr[2] || (th_payload->evt_status_arr[0] & + camif_priv->reg_data->error_irq_mask0)) { + CAM_ERR(CAM_ISP, + "VFE:%d CAMIF Err IRQ status_0: 0x%X status_2: 0x%X", + camif_node->hw_intf->hw_idx, + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[2]); + CAM_ERR(CAM_ISP, "Stopping further IRQ processing from VFE:%d", + camif_node->hw_intf->hw_idx); + cam_irq_controller_disable_irq(camif_priv->vfe_irq_controller, + camif_priv->irq_err_handle); + cam_irq_controller_clear_and_mask(evt_id, + camif_priv->vfe_irq_controller); + error_flag = true; + } + + rc = cam_vfe_camif_ver3_get_evt_payload(camif_priv, &evt_payload); + if (rc) + return rc; + + cam_isp_hw_get_timestamp(&evt_payload->ts); + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + evt_payload->irq_reg_val[i] = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->violation_status); + + evt_payload->irq_reg_val[++i] = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->bus_overflow_status); + + th_payload->evt_payload_priv = evt_payload; + + return rc; +} + +static int cam_vfe_camif_ver3_validate_pix_pattern(uint32_t pattern) +{ + int rc; + + switch (pattern) { + case CAM_ISP_PATTERN_BAYER_RGRGRG: + case CAM_ISP_PATTERN_BAYER_GRGRGR: + case CAM_ISP_PATTERN_BAYER_BGBGBG: + case CAM_ISP_PATTERN_BAYER_GBGBGB: + case CAM_ISP_PATTERN_YUV_YCBYCR: + case CAM_ISP_PATTERN_YUV_YCRYCB: + case CAM_ISP_PATTERN_YUV_CBYCRY: + case CAM_ISP_PATTERN_YUV_CRYCBY: + rc = 0; + break; + default: + CAM_ERR(CAM_ISP, "Error, Invalid pix pattern:%d", pattern); + rc = -EINVAL; + break; + } + return rc; +} + +static int cam_vfe_camif_ver3_get_reg_update( + struct cam_isp_resource_node *camif_res, + void *cmd_args, uint32_t arg_size) +{ + uint32_t size = 0; + uint32_t reg_val_pair[2]; + struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; + struct cam_vfe_mux_camif_ver3_data *rsrc_data = NULL; + + if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { + CAM_ERR(CAM_ISP, "Invalid arg size: %d expected:%ld", + arg_size, sizeof(struct cam_isp_hw_get_cmd_update)); + return -EINVAL; + } + + if (!cdm_args || !cdm_args->res) { + CAM_ERR(CAM_ISP, "Invalid args: %pK", cdm_args); + return -EINVAL; + } + + cdm_util_ops = (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; + + if (!cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid CDM ops"); + return -EINVAL; + } + + size = cdm_util_ops->cdm_required_size_reg_random(1); + /* since cdm returns dwords, we need to convert it into bytes */ + if ((size * 4) > cdm_args->cmd.size) { + CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d", + cdm_args->cmd.size, (size*4)); + return -EINVAL; + } + + rsrc_data = camif_res->res_priv; + reg_val_pair[0] = rsrc_data->camif_reg->reg_update_cmd; + reg_val_pair[1] = rsrc_data->reg_data->reg_update_cmd_data; + CAM_DBG(CAM_ISP, "VFE:%d CAMIF reg_update_cmd 0x%X offset 0x%X", + camif_res->hw_intf->hw_idx, + reg_val_pair[1], reg_val_pair[0]); + + cdm_util_ops->cdm_write_regrandom(cdm_args->cmd.cmd_buf_addr, + 1, reg_val_pair); + + cdm_args->cmd.used_bytes = size * 4; + + return 0; +} + +int cam_vfe_camif_ver3_acquire_resource( + struct cam_isp_resource_node *camif_res, + void *acquire_param) +{ + struct cam_vfe_mux_camif_ver3_data *camif_data; + struct cam_vfe_acquire_args *acquire_data; + int rc = 0; + + camif_data = (struct cam_vfe_mux_camif_ver3_data *) + camif_res->res_priv; + acquire_data = (struct cam_vfe_acquire_args *)acquire_param; + + rc = cam_vfe_camif_ver3_validate_pix_pattern( + acquire_data->vfe_in.in_port->test_pattern); + + if (rc) { + CAM_ERR(CAM_ISP, "Validate pix pattern failed, rc = %d", rc); + return rc; + } + + camif_data->sync_mode = acquire_data->vfe_in.sync_mode; + camif_data->pix_pattern = acquire_data->vfe_in.in_port->test_pattern; + camif_data->dsp_mode = acquire_data->vfe_in.in_port->dsp_mode; + camif_data->first_pixel = acquire_data->vfe_in.in_port->left_start; + camif_data->last_pixel = acquire_data->vfe_in.in_port->left_stop; + camif_data->first_line = acquire_data->vfe_in.in_port->line_start; + camif_data->last_line = acquire_data->vfe_in.in_port->line_stop; + camif_data->horizontal_bin = + acquire_data->vfe_in.in_port->horizontal_bin; + camif_data->qcfa_bin = acquire_data->vfe_in.in_port->qcfa_bin; + camif_data->event_cb = acquire_data->event_cb; + camif_data->priv = acquire_data->priv; + + CAM_DBG(CAM_ISP, "VFE:%d CAMIF pix_pattern:%d dsp_mode=%d", + camif_res->hw_intf->hw_idx, + camif_data->pix_pattern, camif_data->dsp_mode); + + return rc; +} + +static int cam_vfe_camif_ver3_resource_init( + struct cam_isp_resource_node *camif_res, + void *init_args, uint32_t arg_size) +{ + struct cam_vfe_mux_camif_ver3_data *camif_data; + struct cam_hw_soc_info *soc_info; + int rc = 0; + + if (!camif_res) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + camif_data = (struct cam_vfe_mux_camif_ver3_data *) + camif_res->res_priv; + + soc_info = camif_data->soc_info; + + if ((camif_data->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) && + (camif_data->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) { + rc = cam_vfe_soc_enable_clk(soc_info, CAM_VFE_DSP_CLK_NAME); + if (rc) + CAM_ERR(CAM_ISP, + "failed to enable dsp clk, rc = %d", rc); + } + + return rc; +} + +static int cam_vfe_camif_ver3_resource_deinit( + struct cam_isp_resource_node *camif_res, + void *init_args, uint32_t arg_size) +{ + struct cam_vfe_mux_camif_ver3_data *camif_data; + struct cam_hw_soc_info *soc_info; + int rc = 0; + + if (!camif_res) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + camif_data = (struct cam_vfe_mux_camif_ver3_data *) + camif_res->res_priv; + + soc_info = camif_data->soc_info; + + if ((camif_data->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) && + (camif_data->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) { + rc = cam_vfe_soc_disable_clk(soc_info, CAM_VFE_DSP_CLK_NAME); + if (rc) + CAM_ERR(CAM_ISP, "failed to disable dsp clk"); + } + + return rc; +} + +static int cam_vfe_camif_ver3_resource_start( + struct cam_isp_resource_node *camif_res) +{ + struct cam_vfe_mux_camif_ver3_data *rsrc_data; + uint32_t val = 0; + uint32_t epoch0_line_cfg; + uint32_t epoch1_line_cfg; + uint32_t computed_epoch_line_cfg; + int rc = 0; + uint32_t err_irq_mask[CAM_IFE_IRQ_REGISTERS_MAX]; + uint32_t irq_mask[CAM_IFE_IRQ_REGISTERS_MAX]; + struct cam_vfe_soc_private *soc_private; + + if (!camif_res) { + CAM_ERR(CAM_ISP, "Error, Invalid input arguments"); + return -EINVAL; + } + + if (camif_res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Error, Invalid camif res res_state:%d", + camif_res->res_state); + return -EINVAL; + } + + memset(err_irq_mask, 0, sizeof(err_irq_mask)); + memset(irq_mask, 0, sizeof(irq_mask)); + + rsrc_data = (struct cam_vfe_mux_camif_ver3_data *)camif_res->res_priv; + + soc_private = rsrc_data->soc_info->soc_private; + + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error, soc_private NULL"); + return -ENODEV; + } + + /* config debug status registers */ + cam_io_w_mb(rsrc_data->reg_data->top_debug_cfg_en, rsrc_data->mem_base + + rsrc_data->common_reg->top_debug_cfg); + + val = cam_io_r_mb(rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg_0); + + /* AF stitching by hw disabled by default + * PP CAMIF currently operates only in offline mode + */ + + if ((rsrc_data->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) && + (rsrc_data->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) { + /* DSP mode reg val is CAM_ISP_DSP_MODE - 1 */ + val |= (((rsrc_data->dsp_mode - 1) & + rsrc_data->reg_data->dsp_mode_mask) << + rsrc_data->reg_data->dsp_mode_shift); + val |= (0x1 << rsrc_data->reg_data->dsp_en_shift); + } + + if (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) + val |= (1 << rsrc_data->reg_data->pp_extern_reg_update_shift); + + if ((rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) || + (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_MASTER)) + val |= (1 << rsrc_data->reg_data->dual_ife_pix_en_shift); + + val |= (~rsrc_data->cam_common_cfg.vid_ds16_r2pd & 0x1) << + CAM_SHIFT_TOP_CORE_CFG_VID_DS16_R2PD; + val |= (~rsrc_data->cam_common_cfg.vid_ds4_r2pd & 0x1) << + CAM_SHIFT_TOP_CORE_CFG_VID_DS4_R2PD; + val |= (~rsrc_data->cam_common_cfg.disp_ds16_r2pd & 0x1) << + CAM_SHIFT_TOP_CORE_CFG_DISP_DS16_R2PD; + val |= (~rsrc_data->cam_common_cfg.disp_ds4_r2pd & 0x1) << + CAM_SHIFT_TOP_CORE_CFG_DISP_DS4_R2PD; + val |= (rsrc_data->cam_common_cfg.dsp_streaming_tap_point & 0x3) << + CAM_SHIFT_TOP_CORE_CFG_DSP_STREAMING; + val |= (rsrc_data->cam_common_cfg.ihist_src_sel & 0x1) << + CAM_SHIFT_TOP_CORE_CFG_STATS_IHIST; + val |= (rsrc_data->cam_common_cfg.hdr_be_src_sel & 0x1) << + CAM_SHIFT_TOP_CORE_CFG_STATS_HDR_BE; + val |= (rsrc_data->cam_common_cfg.hdr_bhist_src_sel & 0x1) << + CAM_SHIFT_TOP_CORE_CFG_STATS_HDR_BHIST; + val |= (rsrc_data->cam_common_cfg.input_mux_sel_pp & 0x3) << + CAM_SHIFT_TOP_CORE_CFG_INPUTMUX_PP; + + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg_0); + + /* epoch config */ + switch (soc_private->cpas_version) { + case CAM_CPAS_TITAN_480_V100: + epoch0_line_cfg = (rsrc_data->last_line - + rsrc_data->first_line) / 4; + /* epoch line cfg will still be configured at midpoint of the + * frame width. We use '/ 4' instead of '/ 2' + * cause it is multipixel path + */ + if (rsrc_data->horizontal_bin || rsrc_data->qcfa_bin) + epoch0_line_cfg >>= 1; + + epoch1_line_cfg = rsrc_data->reg_data->epoch_line_cfg & + 0xFFFF; + computed_epoch_line_cfg = (epoch1_line_cfg << 16) | + epoch0_line_cfg; + cam_io_w_mb(computed_epoch_line_cfg, + rsrc_data->mem_base + + rsrc_data->camif_reg->epoch_irq_cfg); + CAM_DBG(CAM_ISP, "epoch_line_cfg: 0x%X", + computed_epoch_line_cfg); + break; + default: + CAM_ERR(CAM_ISP, "Hardware version not proper: 0x%X", + soc_private->cpas_version); + return -EINVAL; + break; + } + + camif_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + /* Reg Update */ + cam_io_w_mb(rsrc_data->reg_data->reg_update_cmd_data, + rsrc_data->mem_base + rsrc_data->camif_reg->reg_update_cmd); + CAM_DBG(CAM_ISP, "VFE:%d CAMIF RUP val:0x%X", + camif_res->hw_intf->hw_idx, + rsrc_data->reg_data->reg_update_cmd_data); + + /* disable sof irq debug flag */ + rsrc_data->enable_sof_irq_debug = false; + rsrc_data->irq_debug_cnt = 0; + + if (rsrc_data->camif_debug & + CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS) { + val = cam_io_r_mb(rsrc_data->mem_base + + rsrc_data->common_reg->diag_config); + val |= rsrc_data->reg_data->enable_diagnostic_hw; + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->common_reg->diag_config); + } + + err_irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0] = + rsrc_data->reg_data->error_irq_mask0; + err_irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS2] = + rsrc_data->reg_data->error_irq_mask2; + + irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = + rsrc_data->reg_data->epoch0_irq_mask | + rsrc_data->reg_data->eof_irq_mask; + + if (!rsrc_data->irq_handle) { + rsrc_data->irq_handle = cam_irq_controller_subscribe_irq( + rsrc_data->vfe_irq_controller, + CAM_IRQ_PRIORITY_3, + irq_mask, + camif_res, + camif_res->top_half_handler, + camif_res->bottom_half_handler, + camif_res->tasklet_info, + &tasklet_bh_api); + + if (rsrc_data->irq_handle < 1) { + CAM_ERR(CAM_ISP, "IRQ handle subscribe failure"); + rc = -ENOMEM; + rsrc_data->irq_handle = 0; + } + } + + irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = + rsrc_data->reg_data->sof_irq_mask; + if (rsrc_data->cam_common_cfg.input_mux_sel_pp & 0x3) + irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0] = + rsrc_data->reg_data->frame_id_irq_mask; + + if (!rsrc_data->sof_irq_handle) { + rsrc_data->sof_irq_handle = cam_irq_controller_subscribe_irq( + rsrc_data->vfe_irq_controller, + CAM_IRQ_PRIORITY_1, + irq_mask, + camif_res, + camif_res->top_half_handler, + camif_res->bottom_half_handler, + camif_res->tasklet_info, + &tasklet_bh_api); + + if (rsrc_data->sof_irq_handle < 1) { + CAM_ERR(CAM_ISP, "SOF IRQ handle subscribe failure"); + rc = -ENOMEM; + rsrc_data->sof_irq_handle = 0; + } + } + + if (!rsrc_data->irq_err_handle) { + rsrc_data->irq_err_handle = cam_irq_controller_subscribe_irq( + rsrc_data->vfe_irq_controller, + CAM_IRQ_PRIORITY_0, + err_irq_mask, + camif_res, + cam_vfe_camif_ver3_err_irq_top_half, + camif_res->bottom_half_handler, + camif_res->tasklet_info, + &tasklet_bh_api); + + if (rsrc_data->irq_err_handle < 1) { + CAM_ERR(CAM_ISP, "Error IRQ handle subscribe failure"); + rc = -ENOMEM; + rsrc_data->irq_err_handle = 0; + } + } + + CAM_DBG(CAM_ISP, "VFE:%d CAMIF Start Done", camif_res->hw_intf->hw_idx); + return 0; +} + +static int cam_vfe_camif_ver3_reg_dump( + struct cam_isp_resource_node *camif_res) +{ + struct cam_vfe_mux_camif_ver3_data *camif_priv; + uint32_t offset, val, wm_idx; + + if (!camif_res) { + CAM_ERR(CAM_ISP, "Error, Invalid input arguments"); + return -EINVAL; + } + + if ((camif_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) || + (camif_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE)) + return 0; + + camif_priv = (struct cam_vfe_mux_camif_ver3_data *)camif_res->res_priv; + + CAM_INFO(CAM_ISP, "IFE:%d TOP", camif_res->hw_intf->hw_idx); + for (offset = 0x0; offset <= 0x1FC; offset += 0x4) { + if (offset == 0x1C || offset == 0x34 || + offset == 0x38 || offset == 0x90) + continue; + val = cam_soc_util_r(camif_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", offset, val); + } + + CAM_INFO(CAM_ISP, "IFE:%d PP CLC PREPROCESS", + camif_res->hw_intf->hw_idx); + for (offset = 0x2200; offset <= 0x23FC; offset += 0x4) { + if (offset == 0x2208) + offset = 0x2260; + val = cam_soc_util_r(camif_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", offset, val); + if (offset == 0x2260) + offset = 0x23F4; + } + + CAM_INFO(CAM_ISP, "IFE:%d PP CLC CAMIF", camif_res->hw_intf->hw_idx); + for (offset = 0x2600; offset <= 0x27FC; offset += 0x4) { + if (offset == 0x2608) + offset = 0x2660; + val = cam_soc_util_r(camif_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", offset, val); + if (offset == 0x2660) + offset = 0x2664; + else if (offset == 0x2680) + offset = 0x27EC; + } + + CAM_INFO(CAM_ISP, "IFE:%d PP CLC Modules", camif_res->hw_intf->hw_idx); + for (offset = 0x2800; offset <= 0x8FFC; offset += 0x4) { + val = cam_soc_util_r(camif_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", offset, val); + } + + CAM_INFO(CAM_ISP, "IFE:%d BUS WR", camif_res->hw_intf->hw_idx); + for (offset = 0xAA00; offset <= 0xAADC; offset += 0x4) { + val = cam_soc_util_r(camif_priv->soc_info, 0, offset); + CAM_DBG(CAM_ISP, "offset 0x%X value 0x%X", offset, val); + } + + for (wm_idx = 0; wm_idx <= 25; wm_idx++) { + for (offset = 0xAC00 + 0x100 * wm_idx; + offset < 0xAC84 + 0x100 * wm_idx; offset += 0x4) { + val = cam_soc_util_r(camif_priv->soc_info, 0, offset); + CAM_INFO(CAM_ISP, "offset 0x%X value 0x%X", + offset, val); + } + } + + return 0; +} + +static int cam_vfe_camif_ver3_resource_stop( + struct cam_isp_resource_node *camif_res) +{ + struct cam_vfe_mux_camif_ver3_data *camif_priv; + struct cam_vfe_camif_ver3_pp_clc_reg *camif_reg; + int rc = 0; + uint32_t val = 0; + + if (!camif_res) { + CAM_ERR(CAM_ISP, "Error, Invalid input arguments"); + return -EINVAL; + } + + if ((camif_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) || + (camif_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE)) + return 0; + + camif_priv = (struct cam_vfe_mux_camif_ver3_data *)camif_res->res_priv; + camif_reg = camif_priv->camif_reg; + + if ((camif_priv->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) && + (camif_priv->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) { + val = cam_io_r_mb(camif_priv->mem_base + + camif_priv->common_reg->core_cfg_0); + val &= (~(1 << camif_priv->reg_data->dsp_en_shift)); + cam_io_w_mb(val, camif_priv->mem_base + + camif_priv->common_reg->core_cfg_0); + } + + if (camif_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + camif_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + val = cam_io_r_mb(camif_priv->mem_base + + camif_priv->common_reg->diag_config); + if (val & camif_priv->reg_data->enable_diagnostic_hw) { + val &= ~camif_priv->reg_data->enable_diagnostic_hw; + cam_io_w_mb(val, camif_priv->mem_base + + camif_priv->common_reg->diag_config); + } + + if (camif_priv->irq_handle) { + cam_irq_controller_unsubscribe_irq( + camif_priv->vfe_irq_controller, camif_priv->irq_handle); + camif_priv->irq_handle = 0; + } + + if (camif_priv->sof_irq_handle) { + cam_irq_controller_unsubscribe_irq( + camif_priv->vfe_irq_controller, + camif_priv->sof_irq_handle); + camif_priv->sof_irq_handle = 0; + } + + if (camif_priv->irq_err_handle) { + cam_irq_controller_unsubscribe_irq( + camif_priv->vfe_irq_controller, + camif_priv->irq_err_handle); + camif_priv->irq_err_handle = 0; + } + + return rc; +} + +static int cam_vfe_camif_ver3_core_config( + struct cam_isp_resource_node *rsrc_node, void *cmd_args) +{ + struct cam_vfe_mux_camif_ver3_data *camif_priv; + struct cam_vfe_core_config_args *vfe_core_cfg = + (struct cam_vfe_core_config_args *)cmd_args; + + camif_priv = + (struct cam_vfe_mux_camif_ver3_data *)rsrc_node->res_priv; + camif_priv->cam_common_cfg.vid_ds16_r2pd = + vfe_core_cfg->core_config.vid_ds16_r2pd; + camif_priv->cam_common_cfg.vid_ds4_r2pd = + vfe_core_cfg->core_config.vid_ds4_r2pd; + camif_priv->cam_common_cfg.disp_ds16_r2pd = + vfe_core_cfg->core_config.disp_ds16_r2pd; + camif_priv->cam_common_cfg.disp_ds4_r2pd = + vfe_core_cfg->core_config.disp_ds4_r2pd; + camif_priv->cam_common_cfg.dsp_streaming_tap_point = + vfe_core_cfg->core_config.dsp_streaming_tap_point; + camif_priv->cam_common_cfg.ihist_src_sel = + vfe_core_cfg->core_config.ihist_src_sel; + camif_priv->cam_common_cfg.hdr_be_src_sel = + vfe_core_cfg->core_config.hdr_be_src_sel; + camif_priv->cam_common_cfg.hdr_bhist_src_sel = + vfe_core_cfg->core_config.hdr_bhist_src_sel; + camif_priv->cam_common_cfg.input_mux_sel_pdaf = + vfe_core_cfg->core_config.input_mux_sel_pdaf; + camif_priv->cam_common_cfg.input_mux_sel_pp = + vfe_core_cfg->core_config.input_mux_sel_pp; + + return 0; +} + +static int cam_vfe_camif_ver3_sof_irq_debug( + struct cam_isp_resource_node *rsrc_node, void *cmd_args) +{ + struct cam_vfe_mux_camif_ver3_data *camif_priv; + uint32_t *enable_sof_irq = (uint32_t *)cmd_args; + + camif_priv = + (struct cam_vfe_mux_camif_ver3_data *)rsrc_node->res_priv; + + if (*enable_sof_irq == 1) + camif_priv->enable_sof_irq_debug = true; + else + camif_priv->enable_sof_irq_debug = false; + + return 0; +} + +static int cam_vfe_camif_ver3_process_cmd( + struct cam_isp_resource_node *rsrc_node, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = -EINVAL; + struct cam_vfe_mux_camif_ver3_data *camif_priv = NULL; + + if (!rsrc_node || !cmd_args) { + CAM_ERR(CAM_ISP, + "Invalid input arguments rsesource node:%pK cmd_args:%pK", + rsrc_node, cmd_args); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_REG_UPDATE: + rc = cam_vfe_camif_ver3_get_reg_update(rsrc_node, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_SOF_IRQ_DEBUG: + rc = cam_vfe_camif_ver3_sof_irq_debug(rsrc_node, cmd_args); + break; + case CAM_ISP_HW_CMD_CORE_CONFIG: + rc = cam_vfe_camif_ver3_core_config(rsrc_node, cmd_args); + break; + case CAM_ISP_HW_CMD_SET_CAMIF_DEBUG: + camif_priv = (struct cam_vfe_mux_camif_ver3_data *) + rsrc_node->res_priv; + camif_priv->camif_debug = *((uint32_t *)cmd_args); + break; + case CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA: + camif_priv = (struct cam_vfe_mux_camif_ver3_data *) + rsrc_node->res_priv; + *((struct cam_hw_soc_info **)cmd_args) = camif_priv->soc_info; + rc = 0; + break; + default: + CAM_ERR(CAM_ISP, + "unsupported process command:%d", cmd_type); + break; + } + + return rc; +} + + +static void cam_vfe_camif_ver3_overflow_debug_info( + struct cam_vfe_mux_camif_ver3_data *camif_priv) +{ + uint32_t val0, val1, val2, val3; + + val0 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_0); + val1 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_1); + val2 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_2); + val3 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_3); + CAM_INFO(CAM_ISP, + "status_0: 0x%X status_1: 0x%X status_2: 0x%X status_3: 0x%X", + val0, val1, val2, val3); + + val0 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_4); + val1 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_5); + val2 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_6); + val3 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_7); + CAM_INFO(CAM_ISP, + "status_4: 0x%X status_5: 0x%X status_6: 0x%X status_7: 0x%X", + val0, val1, val2, val3); + + val0 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_8); + val1 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_9); + val2 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_10); + val3 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_11); + CAM_INFO(CAM_ISP, + "status_8: 0x%X status_9: 0x%X status_10: 0x%X status_11: 0x%X", + val0, val1, val2, val3); + + val0 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_12); + val1 = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->top_debug_13); + CAM_INFO(CAM_ISP, "status_12: 0x%X status_13: 0x%X", + val0, val1); +} + +static void cam_vfe_camif_ver3_print_status(uint32_t *status, + int err_type, struct cam_vfe_mux_camif_ver3_data *camif_priv) +{ + uint32_t violation_mask = 0x3F, module_id = 0; + uint32_t bus_overflow_status = 0, status_0 = 0, status_2 = 0; + struct cam_vfe_soc_private *soc_private; + uint32_t val0, val1, val2; + + if (!status) { + CAM_ERR(CAM_ISP, "Invalid params"); + return; + } + + bus_overflow_status = status[CAM_IFE_IRQ_BUS_OVERFLOW_STATUS]; + status_0 = status[CAM_IFE_IRQ_CAMIF_REG_STATUS0]; + status_2 = status[CAM_IFE_IRQ_CAMIF_REG_STATUS2]; + + if (err_type == CAM_VFE_IRQ_STATUS_OVERFLOW) { + if (status_0 & 0x0200) + CAM_INFO(CAM_ISP, "DSP OVERFLOW"); + + if (status_0 & 0x2000000) + CAM_INFO(CAM_ISP, "PIXEL PIPE FRAME DROP"); + + if (status_0 & 0x80000000) + CAM_INFO(CAM_ISP, "PIXEL PIPE OVERFLOW"); + } + + if (err_type == CAM_VFE_IRQ_STATUS_OVERFLOW && bus_overflow_status) { + if (bus_overflow_status & 0x01) + CAM_INFO(CAM_ISP, "VID Y 1:1 BUS OVERFLOW"); + + if (bus_overflow_status & 0x02) + CAM_INFO(CAM_ISP, "VID C 1:1 BUS OVERFLOW"); + + if (bus_overflow_status & 0x04) + CAM_INFO(CAM_ISP, "VID YC 4:1 BUS OVERFLOW"); + + if (bus_overflow_status & 0x08) + CAM_INFO(CAM_ISP, "VID YC 16:1 BUS OVERFLOW"); + + if (bus_overflow_status & 0x010) + CAM_INFO(CAM_ISP, "DISP Y 1:1 BUS OVERFLOW"); + + if (bus_overflow_status & 0x020) + CAM_INFO(CAM_ISP, "DISP C 1:1 BUS OVERFLOW"); + + if (bus_overflow_status & 0x040) + CAM_INFO(CAM_ISP, "DISP YC 4:1 BUS OVERFLOW"); + + if (bus_overflow_status & 0x080) + CAM_INFO(CAM_ISP, "DISP YC 16:1 BUS OVERFLOW"); + + if (bus_overflow_status & 0x0100) + CAM_INFO(CAM_ISP, "FD Y BUS OVERFLOW"); + + if (bus_overflow_status & 0x0200) + CAM_INFO(CAM_ISP, "FD C BUS OVERFLOW"); + + if (bus_overflow_status & 0x0400) + CAM_INFO(CAM_ISP, "PIXEL RAW DUMP BUS OVERFLOW"); + + if (bus_overflow_status & 0x01000) + CAM_INFO(CAM_ISP, "STATS HDR BE BUS OVERFLOW"); + + if (bus_overflow_status & 0x02000) + CAM_INFO(CAM_ISP, "STATS HDR BHIST BUS OVERFLOW"); + + if (bus_overflow_status & 0x04000) + CAM_INFO(CAM_ISP, "STATS TINTLESS BG BUS OVERFLOW"); + + if (bus_overflow_status & 0x08000) + CAM_INFO(CAM_ISP, "STATS AWB BG BUS OVERFLOW"); + + if (bus_overflow_status & 0x010000) + CAM_INFO(CAM_ISP, "STATS BHIST BUS OVERFLOW"); + + if (bus_overflow_status & 0x020000) + CAM_INFO(CAM_ISP, "STATS RS BUS OVERFLOW"); + + if (bus_overflow_status & 0x040000) + CAM_INFO(CAM_ISP, "STATS CS BUS OVERFLOW"); + + if (bus_overflow_status & 0x080000) + CAM_INFO(CAM_ISP, "STATS IHIST BUS OVERFLOW"); + + if (bus_overflow_status & 0x0100000) + CAM_INFO(CAM_ISP, "STATS BAF BUS OVERFLOW"); + + if (bus_overflow_status & 0x0200000) + CAM_INFO(CAM_ISP, "PDAF BUS OVERFLOW"); + + soc_private = camif_priv->soc_info->soc_private; + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0xA20, true, &val0); + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x1420, true, &val1); + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x1A20, true, &val2); + CAM_INFO(CAM_ISP, + "CAMNOC REG ife_linear: 0x%X ife_rdi_wr: 0x%X ife_ubwc_stats: 0x%X", + val0, val1, val2); + cam_cpas_log_votes(); + return; + } + + if (err_type == CAM_VFE_IRQ_STATUS_OVERFLOW && !bus_overflow_status) { + CAM_INFO(CAM_ISP, "PIXEL PIPE Module hang"); + /* print debug registers */ + cam_vfe_camif_ver3_overflow_debug_info(camif_priv); + return; + } + + if (err_type == CAM_VFE_IRQ_STATUS_VIOLATION) { + if (status_2 & 0x080) + CAM_INFO(CAM_ISP, "DSP IFE PROTOCOL VIOLATION"); + + if (status_2 & 0x0100) + CAM_INFO(CAM_ISP, "IFE DSP TX PROTOCOL VIOLATION"); + + if (status_2 & 0x0200) + CAM_INFO(CAM_ISP, "DSP IFE RX PROTOCOL VIOLATION"); + + if (status_2 & 0x0400) + CAM_INFO(CAM_ISP, "PP PREPROCESS VIOLATION"); + + if (status_2 & 0x0800) + CAM_INFO(CAM_ISP, "PP CAMIF VIOLATION"); + + if (status_2 & 0x01000) + CAM_INFO(CAM_ISP, "PP VIOLATION"); + + if (status_2 & 0x0100000) + CAM_INFO(CAM_ISP, + "DSP_TX_VIOLATION:overflow on DSP interface TX path FIFO"); + + if (status_2 & 0x0200000) + CAM_INFO(CAM_ISP, + "DSP_RX_VIOLATION:overflow on DSP interface RX path FIFO"); + + if (status_2 & 0x10000000) + CAM_INFO(CAM_ISP, "DSP ERROR VIOLATION"); + + if (status_2 & 0x20000000) + CAM_INFO(CAM_ISP, + "DIAG VIOLATION: HBI is less than the minimum required HBI"); + } + + if (err_type == CAM_VFE_IRQ_STATUS_VIOLATION && + status[CAM_IFE_IRQ_VIOLATION_STATUS]) { + module_id = + violation_mask & status[CAM_IFE_IRQ_VIOLATION_STATUS]; + CAM_INFO(CAM_ISP, "PIXEL PIPE VIOLATION Module ID:%d", + module_id); + + switch (module_id) { + case 0: + CAM_INFO(CAM_ISP, "DEMUX"); + break; + case 1: + CAM_INFO(CAM_ISP, "CHROMA_UP"); + break; + case 2: + CAM_INFO(CAM_ISP, "PEDESTAL"); + break; + case 3: + CAM_INFO(CAM_ISP, "LINEARIZATION"); + break; + case 4: + CAM_INFO(CAM_ISP, "BPC_PDPC"); + break; + case 5: + CAM_INFO(CAM_ISP, "HDR_BINCORRECT"); + break; + case 6: + CAM_INFO(CAM_ISP, "ABF"); + break; + case 7: + CAM_INFO(CAM_ISP, "LSC"); + break; + case 8: + CAM_INFO(CAM_ISP, "DEMOSAIC"); + break; + case 9: + CAM_INFO(CAM_ISP, "COLOR_CORRECT"); + break; + case 10: + CAM_INFO(CAM_ISP, "GTM"); + break; + case 11: + CAM_INFO(CAM_ISP, "GLUT"); + break; + case 12: + CAM_INFO(CAM_ISP, "COLOR_XFORM"); + break; + case 13: + CAM_INFO(CAM_ISP, "CROP_RND_CLAMP_PIXEL_RAW_OUT"); + break; + case 14: + CAM_INFO(CAM_ISP, "DOWNSCALE_MN_Y_FD_OUT"); + break; + case 15: + CAM_INFO(CAM_ISP, "DOWNSCALE_MN_C_FD_OUT"); + break; + case 16: + CAM_INFO(CAM_ISP, + "CROP_RND_CLAMP_POST_DOWNSCALE_MN_Y_FD_OUT"); + break; + case 17: + CAM_INFO(CAM_ISP, + "CROP_RND_CLAMP_POST_DOWNSCALE_MN_C_FD_OUT"); + break; + case 18: + CAM_INFO(CAM_ISP, "DOWNSCALE_MN_Y_DISP_OUT"); + break; + case 19: + CAM_INFO(CAM_ISP, "DOWNSCALE_MN_C_DISP_OUT"); + break; + case 20: + CAM_INFO(CAM_ISP, + "module: CROP_RND_CLAMP_POST_DOWNSCALE_MN_Y_DISP_OUT"); + break; + case 21: + CAM_INFO(CAM_ISP, + "CROP_RND_CLAMP_POST_DOWNSCALE_MN_C_DISP_OUT"); + break; + case 22: + CAM_INFO(CAM_ISP, "DOWNSCALE_4TO1_Y_DISP_DS4_OUT"); + break; + case 23: + CAM_INFO(CAM_ISP, "DOWNSCALE_4TO1_C_DISP_DS4_OUT"); + break; + case 24: + CAM_INFO(CAM_ISP, + "CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_Y_DISP_DS4_OUT"); + break; + case 25: + CAM_INFO(CAM_ISP, + "CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_C_DISP_DS4_OUT"); + break; + case 26: + CAM_INFO(CAM_ISP, "DOWNSCALE_4TO1_Y_DISP_DS16_OUT"); + break; + case 27: + CAM_INFO(CAM_ISP, "DOWNSCALE_4TO1_C_DISP_DS16_OUT"); + break; + case 28: + CAM_INFO(CAM_ISP, + "CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_Y_DISP_DS16_OUT"); + break; + case 29: + CAM_INFO(CAM_ISP, + "CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_C_DISP_DS16_OUT"); + break; + case 30: + CAM_INFO(CAM_ISP, "DOWNSCALE_MN_Y_VID_OUT"); + break; + case 31: + CAM_INFO(CAM_ISP, "DOWNSCALE_MN_C_VID_OUT"); + break; + case 32: + CAM_INFO(CAM_ISP, + "CROP_RND_CLAMP_POST_DOWNSCALE_MN_Y_VID_OUT"); + break; + case 33: + CAM_INFO(CAM_ISP, + "CROP_RND_CLAMP_POST_DOWNSCALE_MN_C_VID_OUT"); + break; + case 34: + CAM_INFO(CAM_ISP, "DSX_Y_VID_OUT"); + break; + case 35: + CAM_INFO(CAM_ISP, "DSX_C_VID_OUT"); + break; + case 36: + CAM_INFO(CAM_ISP, + "CROP_RND_CLAMP_POST_DSX_Y_VID_OUT"); + break; + case 37: + CAM_INFO(CAM_ISP, + "CROP_RND_CLAMP_POST_DSX_C_VID_OUT"); + break; + case 38: + CAM_INFO(CAM_ISP, + "DOWNSCALE_4TO1_Y_VID_DS16_OUT"); + break; + case 39: + CAM_INFO(CAM_ISP, + "DOWNSCALE_4TO1_C_VID_DS16_OUT"); + break; + case 40: + CAM_INFO(CAM_ISP, + "CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_Y_VID_DS16_OUT"); + break; + case 41: + CAM_INFO(CAM_ISP, + "CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_C_VID_DS16_OUT"); + break; + case 42: + CAM_INFO(CAM_ISP, "BLS"); + break; + case 43: + CAM_INFO(CAM_ISP, "STATS_TINTLESS_BG"); + break; + case 44: + CAM_INFO(CAM_ISP, "STATS_HDR_BHIST"); + break; + case 45: + CAM_INFO(CAM_ISP, "STATS_HDR_BE"); + break; + case 46: + CAM_INFO(CAM_ISP, "STATS_AWB_BG"); + break; + case 47: + CAM_INFO(CAM_ISP, "STATS_BHIST"); + break; + case 48: + CAM_INFO(CAM_ISP, "STATS_BAF"); + break; + case 49: + CAM_INFO(CAM_ISP, "STATS_RS"); + break; + case 50: + CAM_INFO(CAM_ISP, "STATS_CS"); + break; + case 51: + CAM_INFO(CAM_ISP, "STATS_IHIST"); + break; + default: + CAM_ERR(CAM_ISP, + "Invalid Module ID:%d", module_id); + break; + } + } +} + +static int cam_vfe_camif_ver3_handle_irq_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc; + int i; + struct cam_isp_resource_node *camif_node; + struct cam_vfe_mux_camif_ver3_data *camif_priv; + struct cam_vfe_top_irq_evt_payload *evt_payload; + + camif_node = th_payload->handler_priv; + camif_priv = camif_node->res_priv; + + CAM_DBG(CAM_ISP, + "VFE:%d CAMIF IRQ status_0: 0x%X status_1: 0x%X status_2: 0x%X", + camif_node->hw_intf->hw_idx, th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1], th_payload->evt_status_arr[2]); + + rc = cam_vfe_camif_ver3_get_evt_payload(camif_priv, &evt_payload); + if (rc) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "VFE:%d CAMIF IRQ status_0: 0x%X status_1: 0x%X status_2: 0x%X", + camif_node->hw_intf->hw_idx, th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1], th_payload->evt_status_arr[2]); + return rc; + } + + cam_isp_hw_get_timestamp(&evt_payload->ts); + evt_payload->th_reg_val = 0; + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + /* Read frame_id meta at every epoch if custom hw is enabled */ + if (evt_payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_priv->reg_data->epoch0_irq_mask) { + if ((camif_priv->common_reg->custom_frame_idx) && + (camif_priv->cam_common_cfg.input_mux_sel_pp & 0x3)) + evt_payload->th_reg_val = cam_io_r_mb( + camif_priv->mem_base + + camif_priv->common_reg->custom_frame_idx); + } + + th_payload->evt_payload_priv = evt_payload; + + if (th_payload->evt_status_arr[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_priv->reg_data->sof_irq_mask) { + trace_cam_log_event("SOF", "TOP_HALF", + th_payload->evt_status_arr[CAM_IFE_IRQ_CAMIF_REG_STATUS1], + camif_node->hw_intf->hw_idx); + } + + if (th_payload->evt_status_arr[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_priv->reg_data->epoch0_irq_mask) { + trace_cam_log_event("EPOCH0", "TOP_HALF", + th_payload->evt_status_arr[CAM_IFE_IRQ_CAMIF_REG_STATUS1], + camif_node->hw_intf->hw_idx); + } + + if (th_payload->evt_status_arr[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_priv->reg_data->eof_irq_mask) { + trace_cam_log_event("EOF", "TOP_HALF", + th_payload->evt_status_arr[CAM_IFE_IRQ_CAMIF_REG_STATUS1], + camif_node->hw_intf->hw_idx); + } + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +static int cam_vfe_camif_ver3_handle_irq_bottom_half(void *handler_priv, + void *evt_payload_priv) +{ + int ret = CAM_VFE_IRQ_STATUS_ERR; + struct cam_isp_resource_node *camif_node; + struct cam_vfe_mux_camif_ver3_data *camif_priv; + struct cam_vfe_top_irq_evt_payload *payload; + struct cam_isp_hw_event_info evt_info; + uint32_t irq_status[CAM_IFE_IRQ_REGISTERS_MAX] = {0}; + uint32_t val = 0; + int i = 0; + + if (!handler_priv || !evt_payload_priv) { + CAM_ERR(CAM_ISP, + "Invalid params handle_priv:%pK, evt_payload_priv:%pK", + handler_priv, evt_payload_priv); + return ret; + } + + camif_node = handler_priv; + camif_priv = camif_node->res_priv; + payload = evt_payload_priv; + + for (i = 0; i < CAM_IFE_IRQ_REGISTERS_MAX; i++) + irq_status[i] = payload->irq_reg_val[i]; + + evt_info.hw_idx = camif_node->hw_intf->hw_idx; + evt_info.res_id = camif_node->res_id; + evt_info.res_type = camif_node->res_type; + evt_info.th_reg_val = 0; + + if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_priv->reg_data->sof_irq_mask) { + if ((camif_priv->enable_sof_irq_debug) && + (camif_priv->irq_debug_cnt <= + CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "VFE:%d Received SOF", + evt_info.hw_idx); + + camif_priv->irq_debug_cnt++; + if (camif_priv->irq_debug_cnt == + CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX) { + camif_priv->enable_sof_irq_debug = + false; + camif_priv->irq_debug_cnt = 0; + } + } else + CAM_DBG(CAM_ISP, "VFE:%d Received SOF", + evt_info.hw_idx); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_SOF, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_priv->reg_data->epoch0_irq_mask) { + CAM_DBG(CAM_ISP, "VFE:%d Received EPOCH", evt_info.hw_idx); + evt_info.th_reg_val = payload->th_reg_val; + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_priv->reg_data->eof_irq_mask) { + CAM_DBG(CAM_ISP, "VFE:%d Received EOF", evt_info.hw_idx); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_EOF, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS0] + & camif_priv->reg_data->error_irq_mask0) { + CAM_ERR(CAM_ISP, "VFE:%d Overflow", evt_info.hw_idx); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_OVERFLOW; + + cam_vfe_camif_ver3_print_status(irq_status, ret, camif_priv); + + if (camif_priv->camif_debug & CAMIF_DEBUG_ENABLE_REG_DUMP) + cam_vfe_camif_ver3_reg_dump(camif_node); + } + + if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS0] + & camif_priv->reg_data->frame_id_irq_mask) { + val = cam_io_r_mb(camif_priv->mem_base + + camif_priv->common_reg->custom_frame_idx); + CAM_DBG(CAM_ISP, + "VFE:%d Frame id change to: %u", evt_info.hw_idx, + val); + } + + if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS2]) { + CAM_ERR(CAM_ISP, "VFE:%d Violation", evt_info.hw_idx); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_VIOLATION; + + cam_vfe_camif_ver3_print_status(irq_status, ret, camif_priv); + + if (camif_priv->camif_debug & CAMIF_DEBUG_ENABLE_REG_DUMP) + cam_vfe_camif_ver3_reg_dump(camif_node); + } + + if (camif_priv->camif_debug & CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS) { + CAM_DBG(CAM_ISP, "VFE:%d VFE_DIAG_SENSOR_STATUS: 0x%X", + evt_info.hw_idx, camif_priv->mem_base, + cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->diag_sensor_status_0)); + } + + cam_vfe_camif_ver3_put_evt_payload(camif_priv, &payload); + + CAM_DBG(CAM_ISP, "returning status = %d", ret); + return ret; +} + +int cam_vfe_camif_ver3_init( + struct cam_hw_intf *hw_intf, + struct cam_hw_soc_info *soc_info, + void *camif_hw_info, + struct cam_isp_resource_node *camif_node, + void *vfe_irq_controller) +{ + struct cam_vfe_mux_camif_ver3_data *camif_priv = NULL; + struct cam_vfe_camif_ver3_hw_info *camif_info = camif_hw_info; + int i = 0; + + camif_priv = kzalloc(sizeof(struct cam_vfe_mux_camif_ver3_data), + GFP_KERNEL); + if (!camif_priv) + return -ENOMEM; + + camif_node->res_priv = camif_priv; + + camif_priv->mem_base = soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base; + camif_priv->camif_reg = camif_info->camif_reg; + camif_priv->common_reg = camif_info->common_reg; + camif_priv->reg_data = camif_info->reg_data; + camif_priv->hw_intf = hw_intf; + camif_priv->soc_info = soc_info; + camif_priv->vfe_irq_controller = vfe_irq_controller; + + camif_node->init = cam_vfe_camif_ver3_resource_init; + camif_node->deinit = cam_vfe_camif_ver3_resource_deinit; + camif_node->start = cam_vfe_camif_ver3_resource_start; + camif_node->stop = cam_vfe_camif_ver3_resource_stop; + camif_node->process_cmd = cam_vfe_camif_ver3_process_cmd; + camif_node->top_half_handler = cam_vfe_camif_ver3_handle_irq_top_half; + camif_node->bottom_half_handler = + cam_vfe_camif_ver3_handle_irq_bottom_half; + spin_lock_init(&camif_priv->spin_lock); + INIT_LIST_HEAD(&camif_priv->free_payload_list); + for (i = 0; i < CAM_VFE_CAMIF_EVT_MAX; i++) { + INIT_LIST_HEAD(&camif_priv->evt_payload[i].list); + list_add_tail(&camif_priv->evt_payload[i].list, + &camif_priv->free_payload_list); + } + + return 0; +} + +int cam_vfe_camif_ver3_deinit( + struct cam_isp_resource_node *camif_node) +{ + struct cam_vfe_mux_camif_ver3_data *camif_priv; + int i = 0; + + if (!camif_node) { + CAM_ERR(CAM_ISP, "Error, camif_node is NULL %pK", camif_node); + return -ENODEV; + } + + camif_priv = camif_node->res_priv; + + INIT_LIST_HEAD(&camif_priv->free_payload_list); + for (i = 0; i < CAM_VFE_CAMIF_EVT_MAX; i++) + INIT_LIST_HEAD(&camif_priv->evt_payload[i].list); + + camif_priv = camif_node->res_priv; + + camif_node->start = NULL; + camif_node->stop = NULL; + camif_node->process_cmd = NULL; + camif_node->top_half_handler = NULL; + camif_node->bottom_half_handler = NULL; + camif_node->res_priv = NULL; + + if (!camif_priv) { + CAM_ERR(CAM_ISP, "Error, camif_priv is NULL %pK", camif_priv); + return -ENODEV; + } + + kfree(camif_priv); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.h new file mode 100644 index 0000000000000000000000000000000000000000..303a9e5b0a6abe2bb17c53bd090a26f185dc34c6 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_CAMIF_VER3_H_ +#define _CAM_VFE_CAMIF_VER3_H_ + +#include "cam_isp_hw.h" +#include "cam_vfe_top.h" + +struct cam_vfe_camif_ver3_pp_clc_reg { + uint32_t hw_version; + uint32_t hw_status; + uint32_t module_cfg; + uint32_t pdaf_raw_crop_width_cfg; + uint32_t pdaf_raw_crop_height_cfg; + uint32_t line_skip_pattern; + uint32_t pixel_skip_pattern; + uint32_t period_cfg; + uint32_t irq_subsample_pattern; + uint32_t epoch_irq_cfg; + uint32_t debug_1; + uint32_t debug_0; + uint32_t test_bus_ctrl; + uint32_t spare; + uint32_t reg_update_cmd; +}; + +struct cam_vfe_camif_ver3_reg_data { + uint32_t pp_extern_reg_update_shift; + uint32_t dual_pd_extern_reg_update_shift; + uint32_t extern_reg_update_mask; + uint32_t dual_ife_pix_en_shift; + uint32_t operating_mode_shift; + uint32_t input_mux_sel_shift; + + uint32_t pixel_pattern_shift; + uint32_t pixel_pattern_mask; + + uint32_t dsp_mode_shift; + uint32_t dsp_mode_mask; + uint32_t dsp_en_shift; + uint32_t dsp_en_mask; + + uint32_t reg_update_cmd_data; + uint32_t epoch_line_cfg; + uint32_t sof_irq_mask; + uint32_t epoch0_irq_mask; + uint32_t epoch1_irq_mask; + uint32_t eof_irq_mask; + uint32_t error_irq_mask0; + uint32_t error_irq_mask2; + uint32_t subscribe_irq_mask1; + uint32_t frame_id_irq_mask; + + uint32_t enable_diagnostic_hw; + uint32_t pp_camif_cfg_en_shift; + uint32_t pp_camif_cfg_ife_out_en_shift; + uint32_t top_debug_cfg_en; +}; + +struct cam_vfe_camif_ver3_hw_info { + struct cam_vfe_top_ver3_reg_offset_common *common_reg; + struct cam_vfe_camif_ver3_pp_clc_reg *camif_reg; + struct cam_vfe_camif_ver3_reg_data *reg_data; +}; + +int cam_vfe_camif_ver3_acquire_resource( + struct cam_isp_resource_node *camif_res, + void *acquire_param); + +int cam_vfe_camif_ver3_init( + struct cam_hw_intf *hw_intf, + struct cam_hw_soc_info *soc_info, + void *camif_hw_info, + struct cam_isp_resource_node *camif_node, + void *vfe_irq_controller); + +int cam_vfe_camif_ver3_deinit( + struct cam_isp_resource_node *camif_node); + +#endif /* _CAM_VFE_CAMIF_VER3_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_fe_ver1.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_fe_ver1.c new file mode 100644 index 0000000000000000000000000000000000000000..98c84ad77d9334feffcd391124b197d107c0c30e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_fe_ver1.c @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include "cam_io_util.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_isp_hw.h" +#include "cam_vfe_hw_intf.h" +#include "cam_vfe_soc.h" +#include "cam_vfe_top.h" +#include "cam_vfe_top_ver2.h" +#include "cam_vfe_fe_ver1.h" +#include "cam_debug_util.h" +#include "cam_cdm_util.h" +#include "cam_cpas_api.h" + +#define CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX 2 + +struct cam_vfe_mux_fe_data { + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + struct cam_vfe_fe_ver1_reg *fe_reg; + struct cam_vfe_top_ver2_reg_offset_common *common_reg; + struct cam_vfe_fe_reg_data *reg_data; + struct cam_hw_soc_info *soc_info; + + enum cam_isp_hw_sync_mode sync_mode; + uint32_t dsp_mode; + uint32_t pix_pattern; + uint32_t first_pixel; + uint32_t first_line; + uint32_t last_pixel; + uint32_t last_line; + bool enable_sof_irq_debug; + uint32_t irq_debug_cnt; + uint32_t fe_cfg_data; + uint32_t hbi_count; +}; + +static int cam_vfe_fe_validate_pix_pattern(uint32_t pattern) +{ + int rc; + + switch (pattern) { + case CAM_ISP_PATTERN_BAYER_RGRGRG: + case CAM_ISP_PATTERN_BAYER_GRGRGR: + case CAM_ISP_PATTERN_BAYER_BGBGBG: + case CAM_ISP_PATTERN_BAYER_GBGBGB: + case CAM_ISP_PATTERN_YUV_YCBYCR: + case CAM_ISP_PATTERN_YUV_YCRYCB: + case CAM_ISP_PATTERN_YUV_CBYCRY: + case CAM_ISP_PATTERN_YUV_CRYCBY: + rc = 0; + break; + default: + CAM_ERR(CAM_ISP, "Error! Invalid pix pattern:%d", pattern); + rc = -EINVAL; + break; + } + return rc; +} + +static int cam_vfe_fe_update( + struct cam_isp_resource_node *fe_res, + void *cmd_data, uint32_t arg_size) +{ + struct cam_vfe_mux_fe_data *rsrc_data = NULL; + struct cam_vfe_fe_update_args *args = cmd_data; + uint32_t fe_cfg_data; + + if (arg_size != sizeof(struct cam_vfe_fe_update_args)) { + CAM_ERR(CAM_ISP, "Invalid cmd size"); + return -EINVAL; + } + + if (!args) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "fe_update->min_vbi = 0x%x", args->fe_config.min_vbi); + CAM_DBG(CAM_ISP, "fe_update->hbi_count = 0x%x", + args->fe_config.hbi_count); + CAM_DBG(CAM_ISP, "fe_update->fs_mode = 0x%x", args->fe_config.fs_mode); + CAM_DBG(CAM_ISP, "fe_update->fs_line_sync_en = 0x%x", + args->fe_config.fs_line_sync_en); + + fe_cfg_data = args->fe_config.min_vbi | + args->fe_config.fs_mode << 8 | + args->fe_config.fs_line_sync_en; + + rsrc_data = fe_res->res_priv; + rsrc_data->fe_cfg_data = fe_cfg_data; + rsrc_data->hbi_count = args->fe_config.hbi_count; + + CAM_DBG(CAM_ISP, "fe_cfg_data = 0x%x", fe_cfg_data); + return 0; +} + +static int cam_vfe_fe_get_reg_update( + struct cam_isp_resource_node *fe_res, + void *cmd_args, uint32_t arg_size) +{ + uint32_t size = 0; + uint32_t reg_val_pair[2]; + struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; + struct cam_vfe_mux_fe_data *rsrc_data = NULL; + + if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { + CAM_ERR(CAM_ISP, "Invalid cmd size"); + return -EINVAL; + } + + if (!cdm_args || !cdm_args->res) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + cdm_util_ops = (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; + + if (!cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid CDM ops"); + return -EINVAL; + } + + size = cdm_util_ops->cdm_required_size_reg_random(1); + /* since cdm returns dwords, we need to convert it into bytes */ + if ((size * 4) > cdm_args->cmd.size) { + CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d", + cdm_args->cmd.size, size); + return -EINVAL; + } + + rsrc_data = fe_res->res_priv; + reg_val_pair[0] = rsrc_data->fe_reg->reg_update_cmd; + reg_val_pair[1] = rsrc_data->reg_data->reg_update_cmd_data; + CAM_DBG(CAM_ISP, "CAMIF reg_update_cmd 0x%x offset 0x%x", + reg_val_pair[1], reg_val_pair[0]); + + cdm_util_ops->cdm_write_regrandom(cdm_args->cmd.cmd_buf_addr, + 1, reg_val_pair); + + cdm_args->cmd.used_bytes = size * 4; + + return 0; +} + +int cam_vfe_fe_ver1_acquire_resource( + struct cam_isp_resource_node *fe_res, + void *acquire_param) +{ + struct cam_vfe_mux_fe_data *fe_data; + struct cam_vfe_acquire_args *acquire_data; + + int rc = 0; + + fe_data = (struct cam_vfe_mux_fe_data *)fe_res->res_priv; + acquire_data = (struct cam_vfe_acquire_args *)acquire_param; + + rc = cam_vfe_fe_validate_pix_pattern( + acquire_data->vfe_in.in_port->test_pattern); + if (rc) { + CAM_ERR(CAM_ISP, "pix validation failed: id:%d pix_pattern %d", + fe_res->hw_intf->hw_idx, + acquire_data->vfe_in.in_port->test_pattern); + return rc; + } + + fe_data->sync_mode = acquire_data->vfe_in.sync_mode; + fe_data->pix_pattern = acquire_data->vfe_in.in_port->test_pattern; + fe_data->dsp_mode = acquire_data->vfe_in.in_port->dsp_mode; + fe_data->first_pixel = acquire_data->vfe_in.in_port->left_start; + fe_data->last_pixel = acquire_data->vfe_in.in_port->left_stop; + fe_data->first_line = acquire_data->vfe_in.in_port->line_start; + fe_data->last_line = acquire_data->vfe_in.in_port->line_stop; + + CAM_DBG(CAM_ISP, "hw id:%d pix_pattern:%d dsp_mode=%d", + fe_res->hw_intf->hw_idx, + fe_data->pix_pattern, fe_data->dsp_mode); + return rc; +} + +static int cam_vfe_fe_resource_init( + struct cam_isp_resource_node *fe_res, + void *init_args, uint32_t arg_size) +{ + struct cam_vfe_mux_fe_data *fe_data; + struct cam_hw_soc_info *soc_info; + int rc = 0; + + if (!fe_res) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + fe_data = (struct cam_vfe_mux_fe_data *)fe_res->res_priv; + + soc_info = fe_data->soc_info; + + if ((fe_data->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) && + (fe_data->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) { + rc = cam_vfe_soc_enable_clk(soc_info, CAM_VFE_DSP_CLK_NAME); + if (rc) + CAM_ERR(CAM_ISP, "failed to enable dsp clk"); + } + + return rc; +} + +static int cam_vfe_fe_resource_deinit( + struct cam_isp_resource_node *fe_res, + void *init_args, uint32_t arg_size) +{ + struct cam_vfe_mux_fe_data *fe_data; + struct cam_hw_soc_info *soc_info; + int rc = 0; + + if (!fe_res) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + fe_data = (struct cam_vfe_mux_fe_data *)fe_res->res_priv; + + soc_info = fe_data->soc_info; + + if ((fe_data->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) && + (fe_data->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) { + rc = cam_vfe_soc_disable_clk(soc_info, CAM_VFE_DSP_CLK_NAME); + if (rc) + CAM_ERR(CAM_ISP, "failed to disable dsp clk"); + } + + return rc; + +} + +static int cam_vfe_fe_resource_start( + struct cam_isp_resource_node *fe_res) +{ + struct cam_vfe_mux_fe_data *rsrc_data; + uint32_t val = 0; + uint32_t epoch0_irq_mask; + uint32_t epoch1_irq_mask; + uint32_t computed_epoch_line_cfg; + + if (!fe_res) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + if (fe_res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Error! Invalid fe res res_state:%d", + fe_res->res_state); + return -EINVAL; + } + + rsrc_data = (struct cam_vfe_mux_fe_data *)fe_res->res_priv; + + /* config vfe core */ + val = (rsrc_data->pix_pattern << + rsrc_data->reg_data->pixel_pattern_shift); + if (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) + val |= (1 << rsrc_data->reg_data->extern_reg_update_shift); + + if ((rsrc_data->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) && + (rsrc_data->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) { + /* DSP mode reg val is CAM_ISP_DSP_MODE - 1 */ + val |= (((rsrc_data->dsp_mode - 1) & + rsrc_data->reg_data->dsp_mode_mask) << + rsrc_data->reg_data->dsp_mode_shift); + val |= (0x1 << rsrc_data->reg_data->dsp_en_shift); + } + + if (rsrc_data->fe_cfg_data) { + /*set Mux mode value to EXT_RD_PATH */ + val |= (rsrc_data->reg_data->fe_mux_data << + rsrc_data->reg_data->input_mux_sel_shift); + } + + if (rsrc_data->hbi_count) { + /*set hbi count*/ + val |= (rsrc_data->hbi_count << + rsrc_data->reg_data->hbi_cnt_shift); + } + cam_io_w_mb(val, rsrc_data->mem_base + rsrc_data->common_reg->core_cfg); + + CAM_DBG(CAM_ISP, "hw id:%d core_cfg (off:0x%x, val:0x%x)", + fe_res->hw_intf->hw_idx, + rsrc_data->common_reg->core_cfg, + val); + + /* disable the CGC for stats */ + cam_io_w_mb(0xFFFFFFFF, rsrc_data->mem_base + + rsrc_data->common_reg->module_ctrl[ + CAM_VFE_TOP_VER2_MODULE_STATS]->cgc_ovd); + + /* epoch config */ + epoch0_irq_mask = ((rsrc_data->last_line - rsrc_data->first_line) / 2) + + rsrc_data->first_line; + + epoch1_irq_mask = rsrc_data->reg_data->epoch_line_cfg & 0xFFFF; + computed_epoch_line_cfg = (epoch0_irq_mask << 16) | epoch1_irq_mask; + cam_io_w_mb(computed_epoch_line_cfg, + rsrc_data->mem_base + rsrc_data->fe_reg->epoch_irq); + CAM_DBG(CAM_ISP, "first_line:0x%x last_line:0x%x epoch_line_cfg: 0x%x", + rsrc_data->first_line, rsrc_data->last_line, + computed_epoch_line_cfg); + + fe_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + /* Read Back cfg */ + cam_io_w_mb(rsrc_data->fe_cfg_data, + rsrc_data->mem_base + rsrc_data->fe_reg->fe_cfg); + CAM_DBG(CAM_ISP, "hw id:%d fe_cfg_data(off:0x%x val:0x%x)", + fe_res->hw_intf->hw_idx, + rsrc_data->fe_reg->fe_cfg, + rsrc_data->fe_cfg_data); + + /* Reg Update */ + cam_io_w_mb(rsrc_data->reg_data->reg_update_cmd_data, + rsrc_data->mem_base + rsrc_data->fe_reg->reg_update_cmd); + CAM_DBG(CAM_ISP, "hw id:%d RUP (off:0x%x, val:0x%x)", + fe_res->hw_intf->hw_idx, + rsrc_data->fe_reg->reg_update_cmd, + rsrc_data->reg_data->reg_update_cmd_data); + + /* disable sof irq debug flag */ + rsrc_data->enable_sof_irq_debug = false; + rsrc_data->irq_debug_cnt = 0; + + CAM_DBG(CAM_ISP, "Start Camif IFE %d Done", fe_res->hw_intf->hw_idx); + return 0; +} + +static int cam_vfe_fe_reg_dump( + struct cam_isp_resource_node *fe_res) +{ + struct cam_vfe_mux_fe_data *fe_priv; + struct cam_vfe_soc_private *soc_private; + int rc = 0, i; + uint32_t val = 0; + + if (!fe_res) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + if ((fe_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) || + (fe_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE)) + return 0; + + fe_priv = (struct cam_vfe_mux_fe_data *)fe_res->res_priv; + soc_private = fe_priv->soc_info->soc_private; + for (i = 0xA3C; i <= 0xA90; i += 4) { + val = cam_io_r_mb(fe_priv->mem_base + i); + CAM_INFO(CAM_ISP, "offset 0x%x val 0x%x", i, val); + } + + for (i = 0xE0C; i <= 0xE3C; i += 4) { + val = cam_io_r_mb(fe_priv->mem_base + i); + CAM_INFO(CAM_ISP, "offset 0x%x val 0x%x", i, val); + } + + for (i = 0x2000; i <= 0x20B8; i += 4) { + val = cam_io_r_mb(fe_priv->mem_base + i); + CAM_INFO(CAM_ISP, "offset 0x%x val 0x%x", i, val); + } + + for (i = 0x2500; i <= 0x255C; i += 4) { + val = cam_io_r_mb(fe_priv->mem_base + i); + CAM_INFO(CAM_ISP, "offset 0x%x val 0x%x", i, val); + } + + for (i = 0x2600; i <= 0x265C; i += 4) { + val = cam_io_r_mb(fe_priv->mem_base + i); + CAM_INFO(CAM_ISP, "offset 0x%x val 0x%x", i, val); + } + + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x420, true, &val); + CAM_INFO(CAM_ISP, "IFE02_MAXWR_LOW offset 0x420 val 0x%x", val); + + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x820, true, &val); + CAM_INFO(CAM_ISP, "IFE13_MAXWR_LOW offset 0x820 val 0x%x", val); + + return rc; +} + +static int cam_vfe_fe_resource_stop( + struct cam_isp_resource_node *fe_res) +{ + struct cam_vfe_mux_fe_data *fe_priv; + struct cam_vfe_fe_ver1_reg *fe_reg; + int rc = 0; + uint32_t val = 0; + + if (!fe_res) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + if (fe_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED || + fe_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE) + return 0; + + fe_priv = (struct cam_vfe_mux_fe_data *)fe_res->res_priv; + fe_reg = fe_priv->fe_reg; + + if ((fe_priv->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) && + (fe_priv->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) { + val = cam_io_r_mb(fe_priv->mem_base + + fe_priv->common_reg->core_cfg); + val &= (~(1 << fe_priv->reg_data->dsp_en_shift)); + cam_io_w_mb(val, fe_priv->mem_base + + fe_priv->common_reg->core_cfg); + } + + if (fe_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + fe_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + return rc; +} + +static int cam_vfe_fe_sof_irq_debug( + struct cam_isp_resource_node *rsrc_node, void *cmd_args) +{ + struct cam_vfe_mux_fe_data *fe_priv; + uint32_t *enable_sof_irq = (uint32_t *)cmd_args; + + fe_priv = + (struct cam_vfe_mux_fe_data *)rsrc_node->res_priv; + + if (*enable_sof_irq == 1) + fe_priv->enable_sof_irq_debug = true; + else + fe_priv->enable_sof_irq_debug = false; + + return 0; +} + +static int cam_vfe_fe_process_cmd(struct cam_isp_resource_node *rsrc_node, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = -EINVAL; + + if (!rsrc_node || !cmd_args) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_REG_UPDATE: + rc = cam_vfe_fe_get_reg_update(rsrc_node, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_SOF_IRQ_DEBUG: + rc = cam_vfe_fe_sof_irq_debug(rsrc_node, cmd_args); + break; + case CAM_ISP_HW_CMD_FE_UPDATE_IN_RD: + rc = cam_vfe_fe_update(rsrc_node, cmd_args, arg_size); + break; + default: + CAM_ERR(CAM_ISP, + "unsupported process command:%d", cmd_type); + break; + } + + return rc; +} + +static int cam_vfe_fe_handle_irq_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + return -EPERM; +} + +static int cam_vfe_fe_handle_irq_bottom_half(void *handler_priv, + void *evt_payload_priv) +{ + int ret = CAM_VFE_IRQ_STATUS_ERR; + struct cam_isp_resource_node *fe_node; + struct cam_vfe_mux_fe_data *fe_priv; + struct cam_vfe_top_irq_evt_payload *payload; + struct cam_isp_hw_event_info evt_info; + uint32_t irq_status0; + uint32_t irq_status1; + + if (!handler_priv || !evt_payload_priv) { + CAM_ERR(CAM_ISP, "Invalid params"); + return ret; + } + + fe_node = handler_priv; + fe_priv = fe_node->res_priv; + payload = evt_payload_priv; + irq_status0 = payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS0]; + irq_status1 = payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS1]; + + evt_info.hw_idx = fe_node->hw_intf->hw_idx; + evt_info.res_id = fe_node->res_id; + evt_info.res_type = fe_node->res_type; + + CAM_DBG(CAM_ISP, "event ID, irq_status_0 = 0x%x", irq_status0); + + if (irq_status0 & fe_priv->reg_data->sof_irq_mask) { + if ((fe_priv->enable_sof_irq_debug) && + (fe_priv->irq_debug_cnt <= + CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "Received SOF"); + + fe_priv->irq_debug_cnt++; + if (fe_priv->irq_debug_cnt == + CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX) { + fe_priv->enable_sof_irq_debug = + false; + fe_priv->irq_debug_cnt = 0; + } + } else { + CAM_DBG(CAM_ISP, "Received SOF"); + } + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status0 & fe_priv->reg_data->epoch0_irq_mask) { + CAM_DBG(CAM_ISP, "Received EPOCH"); + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status0 & fe_priv->reg_data->reg_update_irq_mask) { + CAM_DBG(CAM_ISP, "Received REG_UPDATE_ACK"); + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status0 & fe_priv->reg_data->eof_irq_mask) { + CAM_DBG(CAM_ISP, "Received EOF"); + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status1 & fe_priv->reg_data->error_irq_mask1) { + CAM_DBG(CAM_ISP, "Received ERROR"); + ret = CAM_ISP_HW_ERROR_OVERFLOW; + evt_info.err_type = CAM_VFE_IRQ_STATUS_OVERFLOW; + cam_vfe_fe_reg_dump(fe_node); + } else { + ret = CAM_ISP_HW_ERROR_NONE; + } + + CAM_DBG(CAM_ISP, "returing status = %d", ret); + return ret; +} + +int cam_vfe_fe_ver1_init( + struct cam_hw_intf *hw_intf, + struct cam_hw_soc_info *soc_info, + void *fe_hw_info, + struct cam_isp_resource_node *fe_node) +{ + struct cam_vfe_mux_fe_data *fe_priv = NULL; + struct cam_vfe_fe_ver1_hw_info *fe_info = fe_hw_info; + + fe_priv = kzalloc(sizeof(struct cam_vfe_mux_fe_data), + GFP_KERNEL); + if (!fe_priv) { + CAM_ERR(CAM_ISP, "Error! Failed to alloc for fe_priv"); + return -ENOMEM; + } + + fe_node->res_priv = fe_priv; + + fe_priv->mem_base = soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base; + fe_priv->fe_reg = fe_info->fe_reg; + fe_priv->common_reg = fe_info->common_reg; + fe_priv->reg_data = fe_info->reg_data; + fe_priv->hw_intf = hw_intf; + fe_priv->soc_info = soc_info; + + fe_node->init = cam_vfe_fe_resource_init; + fe_node->deinit = cam_vfe_fe_resource_deinit; + fe_node->start = cam_vfe_fe_resource_start; + fe_node->stop = cam_vfe_fe_resource_stop; + fe_node->process_cmd = cam_vfe_fe_process_cmd; + fe_node->top_half_handler = cam_vfe_fe_handle_irq_top_half; + fe_node->bottom_half_handler = cam_vfe_fe_handle_irq_bottom_half; + + return 0; +} + +int cam_vfe_fe_ver1_deinit( + struct cam_isp_resource_node *fe_node) +{ + struct cam_vfe_mux_fe_data *fe_priv = fe_node->res_priv; + + fe_node->start = NULL; + fe_node->stop = NULL; + fe_node->process_cmd = NULL; + fe_node->top_half_handler = NULL; + fe_node->bottom_half_handler = NULL; + + fe_node->res_priv = NULL; + + if (!fe_priv) { + CAM_ERR(CAM_ISP, "Error! fe_priv is NULL"); + return -ENODEV; + } + + kfree(fe_priv); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_fe_ver1.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_fe_ver1.h new file mode 100644 index 0000000000000000000000000000000000000000..6974a568fd6c02eeb386c7bae38748430588b71f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_fe_ver1.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_FE_VER1_H_ +#define _CAM_VFE_FE_VER1_H_ + +#include "cam_isp_hw.h" +#include "cam_vfe_top.h" + +struct cam_vfe_fe_ver1_reg { + uint32_t camif_cmd; + uint32_t camif_config; + uint32_t line_skip_pattern; + uint32_t pixel_skip_pattern; + uint32_t skip_period; + uint32_t irq_subsample_pattern; + uint32_t epoch_irq; + uint32_t raw_crop_width_cfg; + uint32_t raw_crop_height_cfg; + uint32_t reg_update_cmd; + uint32_t vfe_diag_config; + uint32_t vfe_diag_sensor_status; + uint32_t fe_cfg; +}; + +struct cam_vfe_fe_reg_data { + uint32_t raw_crop_first_pixel_shift; + uint32_t raw_crop_first_pixel_mask; + + uint32_t raw_crop_last_pixel_shift; + uint32_t raw_crop_last_pixel_mask; + + uint32_t raw_crop_first_line_shift; + uint32_t raw_crop_first_line_mask; + + uint32_t raw_crop_last_line_shift; + uint32_t raw_crop_last_line_mask; + + uint32_t input_mux_sel_shift; + uint32_t input_mux_sel_mask; + uint32_t extern_reg_update_shift; + uint32_t extern_reg_update_mask; + + uint32_t pixel_pattern_shift; + uint32_t pixel_pattern_mask; + + uint32_t dsp_mode_shift; + uint32_t dsp_mode_mask; + uint32_t dsp_en_shift; + uint32_t dsp_en_mask; + + uint32_t reg_update_cmd_data; + uint32_t epoch_line_cfg; + uint32_t sof_irq_mask; + uint32_t epoch0_irq_mask; + uint32_t reg_update_irq_mask; + uint32_t eof_irq_mask; + uint32_t error_irq_mask0; + uint32_t error_irq_mask1; + + uint32_t enable_diagnostic_hw; + uint32_t fe_mux_data; + uint32_t hbi_cnt_shift; +}; + +struct cam_vfe_fe_ver1_hw_info { + struct cam_vfe_top_ver2_reg_offset_common *common_reg; + struct cam_vfe_fe_ver1_reg *fe_reg; + struct cam_vfe_fe_reg_data *reg_data; +}; + +int cam_vfe_fe_ver1_acquire_resource( + struct cam_isp_resource_node *camif_res, + void *acquire_param); + +int cam_vfe_fe_ver1_init( + struct cam_hw_intf *hw_intf, + struct cam_hw_soc_info *soc_info, + void *camif_hw_info, + struct cam_isp_resource_node *camif_node); + +int cam_vfe_fe_ver1_deinit( + struct cam_isp_resource_node *camif_node); + +#endif /* _CAM_VFE_FE_VER1_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c new file mode 100644 index 0000000000000000000000000000000000000000..a0e7741e55056692987f143273b3c879a37add8e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_vfe_rdi.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_isp_hw.h" +#include "cam_vfe_hw_intf.h" +#include "cam_vfe_top_ver2.h" +#include "cam_io_util.h" +#include "cam_debug_util.h" +#include "cam_cdm_util.h" +#include "cam_irq_controller.h" +#include "cam_tasklet_util.h" + +struct cam_vfe_mux_rdi_data { + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + struct cam_vfe_top_ver2_reg_offset_common *common_reg; + struct cam_vfe_rdi_ver2_reg *rdi_reg; + struct cam_vfe_rdi_common_reg_data *rdi_common_reg_data; + struct cam_vfe_rdi_reg_data *reg_data; + + cam_hw_mgr_event_cb_func event_cb; + void *priv; + int irq_err_handle; + int irq_handle; + void *vfe_irq_controller; + struct cam_vfe_top_irq_evt_payload evt_payload[CAM_VFE_RDI_EVT_MAX]; + struct list_head free_payload_list; + spinlock_t spin_lock; + + enum cam_isp_hw_sync_mode sync_mode; +}; + +static int cam_vfe_rdi_get_evt_payload( + struct cam_vfe_mux_rdi_data *rdi_priv, + struct cam_vfe_top_irq_evt_payload **evt_payload) +{ + int rc = 0; + + spin_lock(&rdi_priv->spin_lock); + if (list_empty(&rdi_priv->free_payload_list)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No free payload"); + rc = -ENODEV; + goto done; + } + + *evt_payload = list_first_entry(&rdi_priv->free_payload_list, + struct cam_vfe_top_irq_evt_payload, list); + list_del_init(&(*evt_payload)->list); + rc = 0; +done: + spin_unlock(&rdi_priv->spin_lock); + return rc; +} + +static int cam_vfe_rdi_put_evt_payload( + struct cam_vfe_mux_rdi_data *rdi_priv, + struct cam_vfe_top_irq_evt_payload **evt_payload) +{ + unsigned long flags; + + if (!rdi_priv) { + CAM_ERR(CAM_ISP, "Invalid param core_info NULL"); + return -EINVAL; + } + if (*evt_payload == NULL) { + CAM_ERR(CAM_ISP, "No payload to put"); + return -EINVAL; + } + + spin_lock_irqsave(&rdi_priv->spin_lock, flags); + list_add_tail(&(*evt_payload)->list, &rdi_priv->free_payload_list); + *evt_payload = NULL; + spin_unlock_irqrestore(&rdi_priv->spin_lock, flags); + + CAM_DBG(CAM_ISP, "Done"); + return 0; +} + +static int cam_vfe_rdi_err_irq_top_half( + uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc; + int i; + struct cam_isp_resource_node *rdi_node; + struct cam_vfe_mux_rdi_data *rdi_priv; + struct cam_vfe_top_irq_evt_payload *evt_payload; + bool error_flag = false; + + CAM_DBG(CAM_ISP, "IRQ status_1 = %x", th_payload->evt_status_arr[1]); + + rdi_node = th_payload->handler_priv; + rdi_priv = rdi_node->res_priv; + /* + * need to handle overflow condition here, otherwise irq storm + * will block everything + */ + if (th_payload->evt_status_arr[1]) { + CAM_ERR(CAM_ISP, + "RDI Error: vfe:%d: STATUS_1=0x%x", + rdi_node->hw_intf->hw_idx, + th_payload->evt_status_arr[1]); + CAM_ERR(CAM_ISP, "Stopping further IRQ processing from vfe=%d", + rdi_node->hw_intf->hw_idx); + cam_irq_controller_disable_irq(rdi_priv->vfe_irq_controller, + rdi_priv->irq_err_handle); + cam_irq_controller_clear_and_mask(evt_id, + rdi_priv->vfe_irq_controller); + error_flag = true; + } + + rc = cam_vfe_rdi_get_evt_payload(rdi_priv, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "No tasklet_cmd is free in queue"); + CAM_ERR_RATE_LIMIT(CAM_ISP, "STATUS_1=0x%x", + th_payload->evt_status_arr[1]); + return rc; + } + + cam_isp_hw_get_timestamp(&evt_payload->ts); + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + evt_payload->irq_reg_val[i] = cam_io_r(rdi_priv->mem_base + + rdi_priv->common_reg->violation_status); + + if (error_flag) + CAM_INFO(CAM_ISP, "Violation status = 0x%x", + evt_payload->irq_reg_val[i]); + + th_payload->evt_payload_priv = evt_payload; + + return rc; +} + +static int cam_vfe_rdi_get_reg_update( + struct cam_isp_resource_node *rdi_res, + void *cmd_args, uint32_t arg_size) +{ + uint32_t size = 0; + uint32_t reg_val_pair[2]; + struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; + struct cam_vfe_mux_rdi_data *rsrc_data = NULL; + + if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { + CAM_ERR(CAM_ISP, "Error - Invalid cmd size"); + return -EINVAL; + } + + if (!cdm_args || !cdm_args->res) { + CAM_ERR(CAM_ISP, "Error - Invalid args"); + return -EINVAL; + } + + cdm_util_ops = (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; + if (!cdm_util_ops) { + CAM_ERR(CAM_ISP, "Error - Invalid CDM ops"); + return -EINVAL; + } + + size = cdm_util_ops->cdm_required_size_reg_random(1); + /* since cdm returns dwords, we need to convert it into bytes */ + if ((size * 4) > cdm_args->cmd.size) { + CAM_ERR(CAM_ISP, + "Error - buf size:%d is not sufficient, expected: %d", + cdm_args->cmd.size, size * 4); + return -EINVAL; + } + + rsrc_data = rdi_res->res_priv; + reg_val_pair[0] = rsrc_data->rdi_reg->reg_update_cmd; + reg_val_pair[1] = rsrc_data->reg_data->reg_update_cmd_data; + CAM_DBG(CAM_ISP, "RDI%d reg_update_cmd %x", + rdi_res->res_id - CAM_ISP_HW_VFE_IN_RDI0, reg_val_pair[1]); + + cdm_util_ops->cdm_write_regrandom(cdm_args->cmd.cmd_buf_addr, + 1, reg_val_pair); + cdm_args->cmd.used_bytes = size * 4; + + return 0; +} + +int cam_vfe_rdi_ver2_acquire_resource( + struct cam_isp_resource_node *rdi_res, + void *acquire_param) +{ + struct cam_vfe_mux_rdi_data *rdi_data; + struct cam_vfe_acquire_args *acquire_data; + + rdi_data = (struct cam_vfe_mux_rdi_data *)rdi_res->res_priv; + acquire_data = (struct cam_vfe_acquire_args *)acquire_param; + + rdi_data->event_cb = acquire_data->event_cb; + rdi_data->priv = acquire_data->priv; + rdi_data->sync_mode = acquire_data->vfe_in.sync_mode; + rdi_res->rdi_only_ctx = 0; + + return 0; +} + +static int cam_vfe_rdi_resource_start( + struct cam_isp_resource_node *rdi_res) +{ + struct cam_vfe_mux_rdi_data *rsrc_data; + int rc = 0; + uint32_t err_irq_mask[CAM_IFE_IRQ_REGISTERS_MAX]; + uint32_t rdi_irq_mask[CAM_IFE_IRQ_REGISTERS_MAX] = {0}; + + if (!rdi_res) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + if (rdi_res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Error! Invalid rdi res res_state:%d", + rdi_res->res_state); + return -EINVAL; + } + + rsrc_data = (struct cam_vfe_mux_rdi_data *)rdi_res->res_priv; + err_irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0] = + rsrc_data->rdi_common_reg_data->error_irq_mask0; + err_irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = + rsrc_data->rdi_common_reg_data->error_irq_mask1; + + rdi_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + /* Reg Update */ + cam_io_w_mb(rsrc_data->reg_data->reg_update_cmd_data, + rsrc_data->mem_base + rsrc_data->rdi_reg->reg_update_cmd); + + if (!rsrc_data->irq_err_handle) { + rsrc_data->irq_err_handle = cam_irq_controller_subscribe_irq( + rsrc_data->vfe_irq_controller, + CAM_IRQ_PRIORITY_0, + err_irq_mask, + rdi_res, + cam_vfe_rdi_err_irq_top_half, + rdi_res->bottom_half_handler, + rdi_res->tasklet_info, + &tasklet_bh_api); + if (rsrc_data->irq_err_handle < 1) { + CAM_ERR(CAM_ISP, "Error IRQ handle subscribe failure"); + rc = -ENOMEM; + rsrc_data->irq_err_handle = 0; + } + } + + if (!rdi_res->rdi_only_ctx) + goto end; + + rdi_irq_mask[0] = + (rsrc_data->reg_data->reg_update_irq_mask | + rsrc_data->reg_data->sof_irq_mask); + + CAM_DBG(CAM_ISP, "RDI%d irq_mask 0x%x", + rdi_res->res_id - CAM_ISP_HW_VFE_IN_RDI0, + rdi_irq_mask[0]); + + if (!rsrc_data->irq_handle) { + rsrc_data->irq_handle = cam_irq_controller_subscribe_irq( + rsrc_data->vfe_irq_controller, + CAM_IRQ_PRIORITY_1, + rdi_irq_mask, + rdi_res, + rdi_res->top_half_handler, + rdi_res->bottom_half_handler, + rdi_res->tasklet_info, + &tasklet_bh_api); + if (rsrc_data->irq_handle < 1) { + CAM_ERR(CAM_ISP, "IRQ handle subscribe failure"); + rc = -ENOMEM; + rsrc_data->irq_handle = 0; + } + } + + CAM_DBG(CAM_ISP, "Start RDI %d", + rdi_res->res_id - CAM_ISP_HW_VFE_IN_RDI0); +end: + return rc; +} + + +static int cam_vfe_rdi_resource_stop( + struct cam_isp_resource_node *rdi_res) +{ + struct cam_vfe_mux_rdi_data *rdi_priv; + int rc = 0; + + if (!rdi_res) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + if (rdi_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED || + rdi_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE) + return 0; + + rdi_priv = (struct cam_vfe_mux_rdi_data *)rdi_res->res_priv; + + if (rdi_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + rdi_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + if (rdi_priv->irq_handle) { + cam_irq_controller_unsubscribe_irq( + rdi_priv->vfe_irq_controller, rdi_priv->irq_handle); + rdi_priv->irq_handle = 0; + } + + if (rdi_priv->irq_err_handle) { + cam_irq_controller_unsubscribe_irq( + rdi_priv->vfe_irq_controller, rdi_priv->irq_err_handle); + rdi_priv->irq_err_handle = 0; + } + + return rc; +} + +static int cam_vfe_rdi_process_cmd(struct cam_isp_resource_node *rsrc_node, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = -EINVAL; + + if (!rsrc_node || !cmd_args) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_REG_UPDATE: + rc = cam_vfe_rdi_get_reg_update(rsrc_node, cmd_args, + arg_size); + break; + default: + CAM_ERR(CAM_ISP, + "unsupported RDI process command:%d", cmd_type); + break; + } + + return rc; +} + +static int cam_vfe_rdi_handle_irq_top_half(uint32_t evt_id, + struct cam_irq_th_payload *th_payload) +{ + int32_t rc; + int i; + struct cam_isp_resource_node *rdi_node; + struct cam_vfe_mux_rdi_data *rdi_priv; + struct cam_vfe_top_irq_evt_payload *evt_payload; + + rdi_node = th_payload->handler_priv; + rdi_priv = rdi_node->res_priv; + + CAM_DBG(CAM_ISP, "IRQ status_0 = %x", th_payload->evt_status_arr[0]); + CAM_DBG(CAM_ISP, "IRQ status_1 = %x", th_payload->evt_status_arr[1]); + + rc = cam_vfe_rdi_get_evt_payload(rdi_priv, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No tasklet_cmd is free in queue"); + CAM_ERR_RATE_LIMIT(CAM_ISP, "IRQ status0=0x%x status1=0x%x", + th_payload->evt_status_arr[0], + th_payload->evt_status_arr[1]); + return rc; + } + + cam_isp_hw_get_timestamp(&evt_payload->ts); + + for (i = 0; i < th_payload->num_registers; i++) + evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + th_payload->evt_payload_priv = evt_payload; + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +static int cam_vfe_rdi_handle_irq_bottom_half(void *handler_priv, + void *evt_payload_priv) +{ + int ret = CAM_VFE_IRQ_STATUS_ERR; + struct cam_isp_resource_node *rdi_node; + struct cam_vfe_mux_rdi_data *rdi_priv; + struct cam_vfe_top_irq_evt_payload *payload; + struct cam_isp_hw_event_info evt_info; + uint32_t irq_status0; + + if (!handler_priv || !evt_payload_priv) { + CAM_ERR(CAM_ISP, "Invalid params"); + return ret; + } + + rdi_node = handler_priv; + rdi_priv = rdi_node->res_priv; + payload = evt_payload_priv; + + irq_status0 = payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS0]; + + evt_info.hw_idx = rdi_node->hw_intf->hw_idx; + evt_info.res_id = rdi_node->res_id; + evt_info.res_type = rdi_node->res_type; + + CAM_DBG(CAM_ISP, "irq_status_0 = %x", irq_status0); + + if (irq_status0 & rdi_priv->reg_data->sof_irq_mask) { + CAM_DBG(CAM_ISP, "Received SOF"); + + if (rdi_priv->event_cb) + rdi_priv->event_cb(rdi_priv->priv, + CAM_ISP_HW_EVENT_SOF, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + if (irq_status0 & rdi_priv->reg_data->reg_update_irq_mask) { + CAM_DBG(CAM_ISP, "Received REG UPDATE"); + + if (rdi_priv->event_cb) + rdi_priv->event_cb(rdi_priv->priv, + CAM_ISP_HW_EVENT_REG_UPDATE, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + + cam_vfe_rdi_put_evt_payload(rdi_priv, &payload); + CAM_DBG(CAM_ISP, "returing status = %d", ret); + return ret; +} + +int cam_vfe_rdi_ver2_init( + struct cam_hw_intf *hw_intf, + struct cam_hw_soc_info *soc_info, + void *rdi_hw_info, + struct cam_isp_resource_node *rdi_node, + void *vfe_irq_controller) +{ + struct cam_vfe_mux_rdi_data *rdi_priv = NULL; + struct cam_vfe_rdi_ver2_hw_info *rdi_info = rdi_hw_info; + int i = 0; + + rdi_priv = kzalloc(sizeof(struct cam_vfe_mux_rdi_data), + GFP_KERNEL); + if (!rdi_priv) { + CAM_DBG(CAM_ISP, "Error! Failed to alloc for rdi_priv"); + return -ENOMEM; + } + + rdi_node->res_priv = rdi_priv; + + rdi_priv->mem_base = soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base; + rdi_priv->hw_intf = hw_intf; + rdi_priv->common_reg = rdi_info->common_reg; + rdi_priv->rdi_reg = rdi_info->rdi_reg; + rdi_priv->vfe_irq_controller = vfe_irq_controller; + rdi_priv->rdi_common_reg_data = rdi_info->common_reg_data; + + switch (rdi_node->res_id) { + case CAM_ISP_HW_VFE_IN_RDI0: + rdi_priv->reg_data = rdi_info->reg_data[0]; + break; + case CAM_ISP_HW_VFE_IN_RDI1: + rdi_priv->reg_data = rdi_info->reg_data[1]; + break; + case CAM_ISP_HW_VFE_IN_RDI2: + rdi_priv->reg_data = rdi_info->reg_data[2]; + break; + case CAM_ISP_HW_VFE_IN_RDI3: + if (rdi_info->reg_data[3]) { + rdi_priv->reg_data = rdi_info->reg_data[3]; + } else { + CAM_ERR(CAM_ISP, "Error! RDI3 is not supported"); + goto err_init; + } + break; + default: + CAM_DBG(CAM_ISP, "invalid Resource id:%d", rdi_node->res_id); + goto err_init; + } + + rdi_node->start = cam_vfe_rdi_resource_start; + rdi_node->stop = cam_vfe_rdi_resource_stop; + rdi_node->process_cmd = cam_vfe_rdi_process_cmd; + rdi_node->top_half_handler = cam_vfe_rdi_handle_irq_top_half; + rdi_node->bottom_half_handler = cam_vfe_rdi_handle_irq_bottom_half; + + spin_lock_init(&rdi_priv->spin_lock); + INIT_LIST_HEAD(&rdi_priv->free_payload_list); + for (i = 0; i < CAM_VFE_RDI_EVT_MAX; i++) { + INIT_LIST_HEAD(&rdi_priv->evt_payload[i].list); + list_add_tail(&rdi_priv->evt_payload[i].list, + &rdi_priv->free_payload_list); + } + + return 0; +err_init: + kfree(rdi_priv); + return -EINVAL; +} + +int cam_vfe_rdi_ver2_deinit( + struct cam_isp_resource_node *rdi_node) +{ + struct cam_vfe_mux_rdi_data *rdi_priv = rdi_node->res_priv; + int i = 0; + + INIT_LIST_HEAD(&rdi_priv->free_payload_list); + for (i = 0; i < CAM_VFE_RDI_EVT_MAX; i++) + INIT_LIST_HEAD(&rdi_priv->evt_payload[i].list); + + rdi_node->start = NULL; + rdi_node->stop = NULL; + rdi_node->process_cmd = NULL; + rdi_node->top_half_handler = NULL; + rdi_node->bottom_half_handler = NULL; + + rdi_node->res_priv = NULL; + + if (!rdi_priv) { + CAM_ERR(CAM_ISP, "Error! rdi_priv NULL"); + return -ENODEV; + } + kfree(rdi_priv); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.h new file mode 100644 index 0000000000000000000000000000000000000000..c570e84a011ceb8129613a7e0bf87e3c0c2cc55a --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_RDI_H_ +#define _CAM_VFE_RDI_H_ + +#include "cam_isp_hw.h" +#include "cam_vfe_top.h" + +#define CAM_VFE_RDI_VER2_MAX 4 + +#define CAM_VFE_RDI_EVT_MAX 256 + +struct cam_vfe_rdi_ver2_reg { + uint32_t reg_update_cmd; +}; + +struct cam_vfe_rdi_common_reg_data { + uint32_t subscribe_irq_mask0; + uint32_t subscribe_irq_mask1; + uint32_t error_irq_mask0; + uint32_t error_irq_mask1; + uint32_t error_irq_mask2; + uint32_t rdi_frame_drop_mask; +}; + +struct cam_vfe_rdi_reg_data { + uint32_t reg_update_cmd_data; + uint32_t sof_irq_mask; + uint32_t reg_update_irq_mask; +}; +struct cam_vfe_rdi_ver2_hw_info { + struct cam_vfe_top_ver2_reg_offset_common *common_reg; + struct cam_vfe_rdi_ver2_reg *rdi_reg; + struct cam_vfe_rdi_common_reg_data *common_reg_data; + struct cam_vfe_rdi_reg_data *reg_data[CAM_VFE_RDI_VER2_MAX]; +}; + +int cam_vfe_rdi_ver2_acquire_resource( + struct cam_isp_resource_node *rdi_res, + void *acquire_param); + +int cam_vfe_rdi_ver2_init( + struct cam_hw_intf *hw_intf, + struct cam_hw_soc_info *soc_info, + void *rdi_hw_info, + struct cam_isp_resource_node *rdi_node, + void *vfe_irq_controller); + +int cam_vfe_rdi_ver2_deinit( + struct cam_isp_resource_node *rdi_node); + +#endif /* _CAM_VFE_RDI_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top.c new file mode 100644 index 0000000000000000000000000000000000000000..077f89060bca5a2bba0d1a8b09776a16256e6334 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_vfe_top.h" +#include "cam_vfe_top_ver2.h" +#include "cam_vfe_top_ver3.h" +#include "cam_debug_util.h" + +int cam_vfe_top_init(uint32_t top_version, + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *top_hw_info, + void *vfe_irq_controller, + struct cam_vfe_top **vfe_top) +{ + int rc = -EINVAL; + + switch (top_version) { + case CAM_VFE_TOP_VER_2_0: + rc = cam_vfe_top_ver2_init(soc_info, hw_intf, top_hw_info, + vfe_irq_controller, vfe_top); + break; + case CAM_VFE_TOP_VER_3_0: + rc = cam_vfe_top_ver3_init(soc_info, hw_intf, top_hw_info, + vfe_irq_controller, vfe_top); + break; + default: + CAM_ERR(CAM_ISP, "Error! Unsupported Version %x", top_version); + break; + } + + return rc; +} + +int cam_vfe_top_deinit(uint32_t top_version, + struct cam_vfe_top **vfe_top) +{ + int rc = -EINVAL; + + switch (top_version) { + case CAM_VFE_TOP_VER_2_0: + rc = cam_vfe_top_ver2_deinit(vfe_top); + break; + case CAM_VFE_TOP_VER_3_0: + rc = cam_vfe_top_ver3_deinit(vfe_top); + break; + default: + CAM_ERR(CAM_ISP, "Error! Unsupported Version %x", top_version); + break; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.c new file mode 100644 index 0000000000000000000000000000000000000000..2eae53205c8c6ea3535ca500988e711292ac08f8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.c @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_vfe_top_common.h" +#include "cam_debug_util.h" + +static struct cam_axi_vote *cam_vfe_top_delay_bw_reduction( + struct cam_vfe_top_priv_common *top_common, + uint64_t *to_be_applied_bw) +{ + uint32_t i, j; + int vote_idx = -1; + uint64_t max_bw = 0; + uint64_t total_bw; + struct cam_axi_vote *curr_l_vote; + + for (i = 0; i < CAM_VFE_DELAY_BW_REDUCTION_NUM_FRAMES; i++) { + total_bw = 0; + curr_l_vote = &top_common->last_vote[i]; + for (j = 0; j < curr_l_vote->num_paths; j++) { + if (total_bw > + (U64_MAX - + curr_l_vote->axi_path[j].camnoc_bw)) { + CAM_ERR(CAM_PERF, + "ife[%d] : Integer overflow at hist idx: %d, path: %d, total_bw = %llu, camnoc_bw = %llu", + top_common->hw_idx, i, j, total_bw, + curr_l_vote->axi_path[j].camnoc_bw); + return NULL; + } + + total_bw += curr_l_vote->axi_path[j].camnoc_bw; + } + + if (total_bw > max_bw) { + vote_idx = i; + max_bw = total_bw; + } + } + + if (vote_idx < 0) + return NULL; + + *to_be_applied_bw = max_bw; + + return &top_common->last_vote[vote_idx]; +} + +int cam_vfe_top_set_axi_bw_vote(struct cam_vfe_soc_private *soc_private, + struct cam_vfe_top_priv_common *top_common, bool start_stop) +{ + struct cam_axi_vote agg_vote = {0}; + struct cam_axi_vote *to_be_applied_axi_vote = NULL; + int rc = 0; + uint32_t i; + uint32_t num_paths = 0; + uint64_t total_bw_new_vote = 0; + bool bw_unchanged = true; + bool apply_bw_update = false; + + for (i = 0; i < top_common->num_mux; i++) { + if (top_common->axi_vote_control[i] == + CAM_VFE_BW_CONTROL_INCLUDE) { + if (num_paths + + top_common->req_axi_vote[i].num_paths > + CAM_CPAS_MAX_PATHS_PER_CLIENT) { + CAM_ERR(CAM_PERF, + "Required paths(%d) more than max(%d)", + num_paths + + top_common->req_axi_vote[i].num_paths, + CAM_CPAS_MAX_PATHS_PER_CLIENT); + return -EINVAL; + } + + memcpy(&agg_vote.axi_path[num_paths], + &top_common->req_axi_vote[i].axi_path[0], + top_common->req_axi_vote[i].num_paths * + sizeof( + struct cam_axi_per_path_bw_vote)); + num_paths += top_common->req_axi_vote[i].num_paths; + } + } + + agg_vote.num_paths = num_paths; + + for (i = 0; i < agg_vote.num_paths; i++) { + CAM_DBG(CAM_PERF, + "ife[%d] : New BW Vote : counter[%d] [%s][%s] [%llu %llu %llu]", + top_common->hw_idx, + top_common->last_counter, + cam_cpas_axi_util_path_type_to_string( + agg_vote.axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + agg_vote.axi_path[i].transac_type), + agg_vote.axi_path[i].camnoc_bw, + agg_vote.axi_path[i].mnoc_ab_bw, + agg_vote.axi_path[i].mnoc_ib_bw); + + total_bw_new_vote += agg_vote.axi_path[i].camnoc_bw; + } + + memcpy(&top_common->last_vote[top_common->last_counter], &agg_vote, + sizeof(struct cam_axi_vote)); + top_common->last_counter = (top_common->last_counter + 1) % + CAM_VFE_DELAY_BW_REDUCTION_NUM_FRAMES; + + if ((agg_vote.num_paths != top_common->applied_axi_vote.num_paths) || + (total_bw_new_vote != top_common->total_bw_applied)) + bw_unchanged = false; + + CAM_DBG(CAM_PERF, + "ife[%d] : applied_total=%lld, new_total=%lld unchanged=%d, start_stop=%d", + top_common->hw_idx, top_common->total_bw_applied, + total_bw_new_vote, bw_unchanged, start_stop); + + if (bw_unchanged) { + CAM_DBG(CAM_PERF, "BW config unchanged"); + return 0; + } + + if (start_stop) { + /* need to vote current request immediately */ + to_be_applied_axi_vote = &agg_vote; + /* Reset everything, we can start afresh */ + memset(top_common->last_vote, 0x0, sizeof(struct cam_axi_vote) * + CAM_VFE_DELAY_BW_REDUCTION_NUM_FRAMES); + top_common->last_counter = 0; + top_common->last_vote[top_common->last_counter] = agg_vote; + top_common->last_counter = (top_common->last_counter + 1) % + CAM_VFE_DELAY_BW_REDUCTION_NUM_FRAMES; + } else { + /* + * Find max bw request in last few frames. This will the bw + * that we want to vote to CPAS now. + */ + to_be_applied_axi_vote = + cam_vfe_top_delay_bw_reduction(top_common, + &total_bw_new_vote); + if (!to_be_applied_axi_vote) { + CAM_ERR(CAM_PERF, "to_be_applied_axi_vote is NULL"); + return -EINVAL; + } + } + + for (i = 0; i < to_be_applied_axi_vote->num_paths; i++) { + CAM_DBG(CAM_PERF, + "ife[%d] : Apply BW Vote : [%s][%s] [%llu %llu %llu]", + top_common->hw_idx, + cam_cpas_axi_util_path_type_to_string( + to_be_applied_axi_vote->axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + to_be_applied_axi_vote->axi_path[i].transac_type), + to_be_applied_axi_vote->axi_path[i].camnoc_bw, + to_be_applied_axi_vote->axi_path[i].mnoc_ab_bw, + to_be_applied_axi_vote->axi_path[i].mnoc_ib_bw); + } + + if ((to_be_applied_axi_vote->num_paths != + top_common->applied_axi_vote.num_paths) || + (total_bw_new_vote != top_common->total_bw_applied)) + apply_bw_update = true; + + CAM_DBG(CAM_PERF, + "ife[%d] : Delayed update: applied_total=%lld, new_total=%lld apply_bw_update=%d, start_stop=%d", + top_common->hw_idx, top_common->total_bw_applied, + total_bw_new_vote, apply_bw_update, start_stop); + + if (apply_bw_update) { + rc = cam_cpas_update_axi_vote(soc_private->cpas_handle, + to_be_applied_axi_vote); + if (!rc) { + memcpy(&top_common->applied_axi_vote, + to_be_applied_axi_vote, + sizeof(struct cam_axi_vote)); + top_common->total_bw_applied = total_bw_new_vote; + } else { + CAM_ERR(CAM_PERF, "BW request failed, rc=%d", rc); + } + } + + return rc; +} + +int cam_vfe_top_bw_update_v2(struct cam_vfe_soc_private *soc_private, + struct cam_vfe_top_priv_common *top_common, void *cmd_args, + uint32_t arg_size) +{ + struct cam_vfe_bw_update_args_v2 *bw_update = NULL; + struct cam_isp_resource_node *res = NULL; + struct cam_hw_info *hw_info = NULL; + int rc = 0; + int i; + + bw_update = (struct cam_vfe_bw_update_args_v2 *)cmd_args; + res = bw_update->node_res; + + if (!res || !res->hw_intf || !res->hw_intf->hw_priv) + return -EINVAL; + + hw_info = res->hw_intf->hw_priv; + + if (res->res_type != CAM_ISP_RESOURCE_VFE_IN || + res->res_id >= CAM_ISP_HW_VFE_IN_MAX) { + CAM_ERR(CAM_ISP, "VFE:%d Invalid res_type:%d res id%d", + res->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + for (i = 0; i < top_common->num_mux; i++) { + if (top_common->mux_rsrc[i].res_id == res->res_id) { + memcpy(&top_common->req_axi_vote[i], + &bw_update->isp_vote, + sizeof(struct cam_axi_vote)); + top_common->axi_vote_control[i] = + CAM_VFE_BW_CONTROL_INCLUDE; + break; + } + } + + if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR_RATE_LIMIT(CAM_PERF, + "VFE:%d Not ready to set BW yet :%d", + res->hw_intf->hw_idx, + hw_info->hw_state); + } else { + rc = cam_vfe_top_set_axi_bw_vote(soc_private, top_common, + false); + } + + return rc; +} + +int cam_vfe_top_bw_update(struct cam_vfe_soc_private *soc_private, + struct cam_vfe_top_priv_common *top_common, void *cmd_args, + uint32_t arg_size) +{ + struct cam_vfe_bw_update_args *bw_update = NULL; + struct cam_isp_resource_node *res = NULL; + struct cam_hw_info *hw_info = NULL; + int rc = 0; + int i; + struct cam_axi_vote *mux_axi_vote; + bool vid_exists = false; + bool rdi_exists = false; + + bw_update = (struct cam_vfe_bw_update_args *)cmd_args; + res = bw_update->node_res; + + if (!res || !res->hw_intf || !res->hw_intf->hw_priv) + return -EINVAL; + + hw_info = res->hw_intf->hw_priv; + + CAM_DBG(CAM_PERF, "res_id=%d, BW=[%lld %lld]", + res->res_id, bw_update->camnoc_bw_bytes, + bw_update->external_bw_bytes); + + if (res->res_type != CAM_ISP_RESOURCE_VFE_IN || + res->res_id >= CAM_ISP_HW_VFE_IN_MAX) { + CAM_ERR(CAM_ISP, "VFE:%d Invalid res_type:%d res id%d", + res->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + for (i = 0; i < top_common->num_mux; i++) { + mux_axi_vote = &top_common->req_axi_vote[i]; + if (top_common->mux_rsrc[i].res_id == res->res_id) { + mux_axi_vote->num_paths = 1; + if ((res->res_id >= CAM_ISP_HW_VFE_IN_RDI0) && + (res->res_id <= CAM_ISP_HW_VFE_IN_RDI3)) { + mux_axi_vote->axi_path[0].path_data_type = + CAM_AXI_PATH_DATA_IFE_RDI0 + + (res->res_id - CAM_ISP_HW_VFE_IN_RDI0); + } else { + /* + * Vote all bw into VIDEO path as we cannot + * differentiate to which path this has to go + */ + mux_axi_vote->axi_path[0].path_data_type = + CAM_AXI_PATH_DATA_IFE_VID; + } + + mux_axi_vote->axi_path[0].transac_type = + CAM_AXI_TRANSACTION_WRITE; + mux_axi_vote->axi_path[0].camnoc_bw = + bw_update->camnoc_bw_bytes; + mux_axi_vote->axi_path[0].mnoc_ab_bw = + bw_update->external_bw_bytes; + mux_axi_vote->axi_path[0].mnoc_ib_bw = + bw_update->external_bw_bytes; + /* Make ddr bw same as mnoc bw */ + mux_axi_vote->axi_path[0].ddr_ab_bw = + bw_update->external_bw_bytes; + mux_axi_vote->axi_path[0].ddr_ib_bw = + bw_update->external_bw_bytes; + + top_common->axi_vote_control[i] = + CAM_VFE_BW_CONTROL_INCLUDE; + break; + } + + if (mux_axi_vote->num_paths == 1) { + if (mux_axi_vote->axi_path[0].path_data_type == + CAM_AXI_PATH_DATA_IFE_VID) + vid_exists = true; + else if ((mux_axi_vote->axi_path[0].path_data_type >= + CAM_AXI_PATH_DATA_IFE_RDI0) && + (mux_axi_vote->axi_path[0].path_data_type <= + CAM_AXI_PATH_DATA_IFE_RDI3)) + rdi_exists = true; + } + } + + if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR_RATE_LIMIT(CAM_PERF, + "VFE:%d Not ready to set BW yet :%d", + res->hw_intf->hw_idx, + hw_info->hw_state); + } else { + rc = cam_vfe_top_set_axi_bw_vote(soc_private, top_common, + false); + } + + return rc; +} + +int cam_vfe_top_bw_control(struct cam_vfe_soc_private *soc_private, + struct cam_vfe_top_priv_common *top_common, void *cmd_args, + uint32_t arg_size) +{ + struct cam_vfe_bw_control_args *bw_ctrl = NULL; + struct cam_isp_resource_node *res = NULL; + struct cam_hw_info *hw_info = NULL; + int rc = 0; + int i; + + bw_ctrl = (struct cam_vfe_bw_control_args *)cmd_args; + res = bw_ctrl->node_res; + + if (!res || !res->hw_intf->hw_priv) + return -EINVAL; + + hw_info = res->hw_intf->hw_priv; + + if (res->res_type != CAM_ISP_RESOURCE_VFE_IN || + res->res_id >= CAM_ISP_HW_VFE_IN_MAX) { + CAM_ERR(CAM_ISP, "VFE:%d Invalid res_type:%d res id%d", + res->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + for (i = 0; i < top_common->num_mux; i++) { + if (top_common->mux_rsrc[i].res_id == res->res_id) { + top_common->axi_vote_control[i] = bw_ctrl->action; + break; + } + } + + if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR_RATE_LIMIT(CAM_PERF, + "VFE:%d Not ready to set BW yet :%d", + res->hw_intf->hw_idx, + hw_info->hw_state); + } else { + rc = cam_vfe_top_set_axi_bw_vote(soc_private, top_common, true); + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.h new file mode 100644 index 0000000000000000000000000000000000000000..55607b6d886f298b8cf062870e1786ac61573e0d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_TOP_COMMON_H_ +#define _CAM_VFE_TOP_COMMON_H_ + +#define CAM_VFE_TOP_MUX_MAX 6 +#define CAM_VFE_DELAY_BW_REDUCTION_NUM_FRAMES 18 + +#include "cam_cpas_api.h" +#include "cam_vfe_hw_intf.h" +#include "cam_vfe_soc.h" + +#define CAM_VFE_TOP_MAX_REG_DUMP_ENTRIES 70 + +#define CAM_VFE_TOP_MAX_LUT_DUMP_ENTRIES 6 + +struct cam_vfe_top_priv_common { + struct cam_isp_resource_node mux_rsrc[CAM_VFE_TOP_MUX_MAX]; + uint32_t num_mux; + uint32_t hw_idx; + struct cam_axi_vote applied_axi_vote; + struct cam_axi_vote req_axi_vote[CAM_VFE_TOP_MUX_MAX]; + struct cam_axi_vote last_vote[ + CAM_VFE_DELAY_BW_REDUCTION_NUM_FRAMES]; + uint32_t last_counter; + uint64_t total_bw_applied; + enum cam_vfe_bw_control_action axi_vote_control[CAM_VFE_TOP_MUX_MAX]; +}; + +struct cam_vfe_top_reg_dump_entry { + uint32_t reg_dump_start; + uint32_t reg_dump_end; +}; + +struct cam_vfe_top_lut_dump_entry { + uint32_t lut_word_size; + uint32_t lut_bank_sel; + uint32_t lut_addr_size; +}; + +struct cam_vfe_top_dump_data { + uint32_t num_reg_dump_entries; + uint32_t num_lut_dump_entries; + uint32_t dmi_cfg; + uint32_t dmi_addr; + uint32_t dmi_data_path_hi; + uint32_t dmi_data_path_lo; + struct cam_vfe_top_reg_dump_entry + reg_entry[CAM_VFE_TOP_MAX_REG_DUMP_ENTRIES]; + struct cam_vfe_top_lut_dump_entry + lut_entry[CAM_VFE_TOP_MAX_LUT_DUMP_ENTRIES]; +}; + +int cam_vfe_top_set_axi_bw_vote(struct cam_vfe_soc_private *soc_private, + struct cam_vfe_top_priv_common *top_common, bool start_stop); + +int cam_vfe_top_bw_update_v2(struct cam_vfe_soc_private *soc_private, + struct cam_vfe_top_priv_common *top_common, void *cmd_args, + uint32_t arg_size); + +int cam_vfe_top_bw_update(struct cam_vfe_soc_private *soc_private, + struct cam_vfe_top_priv_common *top_common, void *cmd_args, + uint32_t arg_size); + +int cam_vfe_top_bw_control(struct cam_vfe_soc_private *soc_private, + struct cam_vfe_top_priv_common *top_common, void *cmd_args, + uint32_t arg_size); + +#endif /* _CAM_VFE_TOP_COMMON_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c new file mode 100644 index 0000000000000000000000000000000000000000..6774be8cda3dfb62f2e9bf96065f6db583daed96 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c @@ -0,0 +1,870 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_io_util.h" +#include "cam_cdm_util.h" +#include "cam_vfe_hw_intf.h" +#include "cam_vfe_top.h" +#include "cam_vfe_top_ver2.h" +#include "cam_debug_util.h" +#include "cam_vfe_soc.h" + +#define CAM_VFE_HW_RESET_HW_AND_REG_VAL 0x00003F9F +#define CAM_VFE_HW_RESET_HW_VAL 0x00003F87 + +struct cam_vfe_top_ver2_common_data { + struct cam_hw_soc_info *soc_info; + struct cam_hw_intf *hw_intf; + struct cam_vfe_top_ver2_reg_offset_common *common_reg; + struct cam_vfe_top_dump_data *dump_data; +}; + +struct cam_vfe_top_ver2_priv { + struct cam_vfe_top_ver2_common_data common_data; + unsigned long hw_clk_rate; + unsigned long req_clk_rate[ + CAM_VFE_TOP_MUX_MAX]; + struct cam_vfe_top_priv_common top_common; +}; + +static int cam_vfe_top_mux_get_base(struct cam_vfe_top_ver2_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + uint32_t size = 0; + uint32_t mem_base = 0; + struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; + + if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { + CAM_ERR(CAM_ISP, "Error! Invalid cmd size"); + return -EINVAL; + } + + if (!cdm_args || !cdm_args->res || !top_priv || + !top_priv->common_data.soc_info) { + CAM_ERR(CAM_ISP, "Error! Invalid args"); + return -EINVAL; + } + + cdm_util_ops = + (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; + + if (!cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid CDM ops"); + return -EINVAL; + } + + size = cdm_util_ops->cdm_required_size_changebase(); + /* since cdm returns dwords, we need to convert it into bytes */ + if ((size * 4) > cdm_args->cmd.size) { + CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d", + cdm_args->cmd.size, size); + return -EINVAL; + } + + mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE( + top_priv->common_data.soc_info, VFE_CORE_BASE_IDX); + CAM_DBG(CAM_ISP, "core %d mem_base 0x%x", + top_priv->common_data.soc_info->index, mem_base); + + cdm_util_ops->cdm_write_changebase( + cdm_args->cmd.cmd_buf_addr, mem_base); + cdm_args->cmd.used_bytes = (size * 4); + + return 0; +} + +static int cam_vfe_top_set_hw_clk_rate( + struct cam_vfe_top_ver2_priv *top_priv) +{ + struct cam_hw_soc_info *soc_info = NULL; + int i, rc = 0; + unsigned long max_clk_rate = 0; + + soc_info = top_priv->common_data.soc_info; + + for (i = 0; i < top_priv->top_common.num_mux; i++) { + if (top_priv->req_clk_rate[i] > max_clk_rate) + max_clk_rate = top_priv->req_clk_rate[i]; + } + if (max_clk_rate == top_priv->hw_clk_rate) + return 0; + + CAM_DBG(CAM_PERF, "VFE: Clock name=%s idx=%d clk=%llu", + soc_info->clk_name[soc_info->src_clk_idx], + soc_info->src_clk_idx, max_clk_rate); + + rc = cam_soc_util_set_src_clk_rate(soc_info, max_clk_rate); + + if (!rc) + top_priv->hw_clk_rate = max_clk_rate; + else + CAM_ERR(CAM_PERF, "Set Clock rate failed, rc=%d", rc); + + return rc; +} + +static int cam_vfe_top_fs_update( + struct cam_vfe_top_ver2_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_vfe_fe_update_args *cmd_update = cmd_args; + + if (cmd_update->node_res->process_cmd) + return cmd_update->node_res->process_cmd(cmd_update->node_res, + CAM_ISP_HW_CMD_FE_UPDATE_IN_RD, cmd_args, arg_size); + + return 0; +} + +static int cam_vfe_top_clock_update( + struct cam_vfe_top_ver2_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_vfe_clock_update_args *clk_update = NULL; + struct cam_isp_resource_node *res = NULL; + struct cam_hw_info *hw_info = NULL; + int i, rc = 0; + + clk_update = + (struct cam_vfe_clock_update_args *)cmd_args; + res = clk_update->node_res; + + if (!res || !res->hw_intf->hw_priv) { + CAM_ERR(CAM_PERF, "Invalid input res %pK", res); + return -EINVAL; + } + + hw_info = res->hw_intf->hw_priv; + + if (res->res_type != CAM_ISP_RESOURCE_VFE_IN || + res->res_id >= CAM_ISP_HW_VFE_IN_MAX) { + CAM_ERR(CAM_PERF, "VFE:%d Invalid res_type:%d res id%d", + res->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + for (i = 0; i < top_priv->top_common.num_mux; i++) { + if (top_priv->top_common.mux_rsrc[i].res_id == res->res_id) { + top_priv->req_clk_rate[i] = clk_update->clk_rate; + break; + } + } + + if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_DBG(CAM_PERF, + "VFE:%d Not ready to set clocks yet :%d", + res->hw_intf->hw_idx, + hw_info->hw_state); + } else + rc = cam_vfe_top_set_hw_clk_rate(top_priv); + + return rc; +} + +static int cam_vfe_top_mux_get_reg_update( + struct cam_vfe_top_ver2_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_isp_hw_get_cmd_update *cmd_update = cmd_args; + + if (cmd_update->res->process_cmd) + return cmd_update->res->process_cmd(cmd_update->res, + CAM_ISP_HW_CMD_GET_REG_UPDATE, cmd_args, arg_size); + + return -EINVAL; +} + +int cam_vfe_top_get_hw_caps(void *device_priv, + void *get_hw_cap_args, uint32_t arg_size) +{ + return -EPERM; +} + +static int cam_vfe_hw_dump( + struct cam_vfe_top_ver2_priv *top_priv, + void *cmd_args, + uint32_t arg_size) +{ + int i, j; + uint8_t *dst; + uint32_t reg_start_offset; + uint32_t reg_dump_size = 0; + uint32_t lut_dump_size = 0; + uint32_t val; + uint32_t num_reg; + void __iomem *reg_base; + uint32_t *addr, *start; + size_t remain_len; + uint32_t min_len; + struct cam_hw_soc_info *soc_info; + struct cam_vfe_top_dump_data *dump_data; + struct cam_isp_hw_dump_header *hdr; + struct cam_isp_hw_dump_args *dump_args = + (struct cam_isp_hw_dump_args *)cmd_args; + + if (!dump_args) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + if (!dump_args->cpu_addr || !dump_args->buf_len) { + CAM_ERR(CAM_ISP, + "Invalid params %pK %zu", + (void *)dump_args->cpu_addr, + dump_args->buf_len); + return -EINVAL; + } + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_ISP, + "Dump offset overshoot offset %zu buf_len %zu", + dump_args->offset, dump_args->buf_len); + return -ENOSPC; + } + dump_data = top_priv->common_data.dump_data; + soc_info = top_priv->common_data.soc_info; + + /*Dump registers */ + for (i = 0; i < dump_data->num_reg_dump_entries; i++) + reg_dump_size += (dump_data->reg_entry[i].reg_dump_end - + dump_data->reg_entry[i].reg_dump_start); + /* + * We dump the offset as well, so the total size dumped becomes + * multiplied by 2 + */ + reg_dump_size *= 2; + for (i = 0; i < dump_data->num_lut_dump_entries; i++) + lut_dump_size += ((dump_data->lut_entry[i].lut_addr_size) * + (dump_data->lut_entry[i].lut_word_size/8)); + + /*Minimum len comprises of: + * soc_index + * lut_dump_size + reg_dump_size + sizeof dump_header + + * (num_lut_dump_entries--> represents number of banks) + */ + min_len = sizeof(uint32_t) + lut_dump_size + reg_dump_size + + sizeof(struct cam_isp_hw_dump_header) + + (dump_data->num_lut_dump_entries * sizeof(uint32_t)); + remain_len = dump_args->buf_len - dump_args->offset; + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu, min %u", + remain_len, min_len); + return -ENOSPC; + } + + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + hdr->word_size = sizeof(uint32_t); + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "VFE_REG:"); + addr = (uint32_t *)(dst + sizeof(struct cam_isp_hw_dump_header)); + start = addr; + *addr++ = soc_info->index; + for (i = 0; i < dump_data->num_reg_dump_entries; i++) { + num_reg = (dump_data->reg_entry[i].reg_dump_end - + dump_data->reg_entry[i].reg_dump_start)/4; + reg_start_offset = dump_data->reg_entry[i].reg_dump_start; + reg_base = soc_info->reg_map[0].mem_base + reg_start_offset; + for (j = 0; j < num_reg; j++) { + addr[0] = soc_info->mem_block[0]->start + + reg_start_offset + (j*4); + addr[1] = cam_io_r(reg_base + (j*4)); + addr += 2; + } + } + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + + /*dump LUT*/ + for (i = 0; i < dump_data->num_lut_dump_entries; i++) { + + dst = (char *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "LUT_REG:"); + hdr->word_size = dump_data->lut_entry[i].lut_word_size/8; + addr = (uint32_t *)(dst + + sizeof(struct cam_isp_hw_dump_header)); + start = addr; + *addr++ = dump_data->lut_entry[i].lut_bank_sel; + val = 0x100 | dump_data->lut_entry[i].lut_bank_sel; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + dump_data->dmi_cfg); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + dump_data->dmi_addr); + for (j = 0; j < dump_data->lut_entry[i].lut_addr_size; + j++) { + if (dump_data->lut_entry[i].lut_word_size == 64) { + addr[0] = cam_io_r( + soc_info->reg_map[0].mem_base + + dump_data->dmi_data_path_lo); + addr[1] = cam_io_r( + soc_info->reg_map[0].mem_base + + dump_data->dmi_data_path_hi); + addr += 2; + } else { + *addr = cam_io_r( + soc_info->reg_map[0].mem_base + + dump_data->dmi_data_path_lo); + addr++; + } + } + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + } + CAM_DBG(CAM_ISP, "offset %zu", dump_args->offset); + return 0; +} + +int cam_vfe_top_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_vfe_top_ver2_priv *top_priv = device_priv; + + top_priv->hw_clk_rate = 0; + + return 0; +} + +int cam_vfe_top_reset(void *device_priv, + void *reset_core_args, uint32_t arg_size) +{ + struct cam_vfe_top_ver2_priv *top_priv = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_vfe_top_ver2_reg_offset_common *reg_common = NULL; + uint32_t *reset_reg_args = reset_core_args; + uint32_t reset_reg_val; + + if (!top_priv || !reset_reg_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + switch (*reset_reg_args) { + case CAM_VFE_HW_RESET_HW_AND_REG: + reset_reg_val = CAM_VFE_HW_RESET_HW_AND_REG_VAL; + break; + default: + reset_reg_val = CAM_VFE_HW_RESET_HW_VAL; + break; + } + + CAM_DBG(CAM_ISP, "reset reg value: %x", reset_reg_val); + soc_info = top_priv->common_data.soc_info; + reg_common = top_priv->common_data.common_reg; + + /* Mask All the IRQs except RESET */ + cam_io_w_mb((1 << 31), + CAM_SOC_GET_REG_MAP_START(soc_info, VFE_CORE_BASE_IDX) + 0x5C); + + /* Reset HW */ + cam_io_w_mb(reset_reg_val, + CAM_SOC_GET_REG_MAP_START(soc_info, VFE_CORE_BASE_IDX) + + reg_common->global_reset_cmd); + + CAM_DBG(CAM_ISP, "Reset HW exit"); + return 0; +} + +int cam_vfe_top_reserve(void *device_priv, + void *reserve_args, uint32_t arg_size) +{ + struct cam_vfe_top_ver2_priv *top_priv; + struct cam_vfe_acquire_args *args; + struct cam_vfe_hw_vfe_in_acquire_args *acquire_args; + uint32_t i; + int rc = -EINVAL; + + if (!device_priv || !reserve_args) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + top_priv = (struct cam_vfe_top_ver2_priv *)device_priv; + args = (struct cam_vfe_acquire_args *)reserve_args; + acquire_args = &args->vfe_in; + + + for (i = 0; i < top_priv->top_common.num_mux; i++) { + if (top_priv->top_common.mux_rsrc[i].res_id == + acquire_args->res_id && + top_priv->top_common.mux_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + + if (acquire_args->res_id == CAM_ISP_HW_VFE_IN_CAMIF) { + rc = cam_vfe_camif_ver2_acquire_resource( + &top_priv->top_common.mux_rsrc[i], + args); + if (rc) + break; + } + + if (acquire_args->res_id == + CAM_ISP_HW_VFE_IN_PDLIB) { + rc = cam_vfe_camif_lite_ver2_acquire_resource( + &top_priv->top_common.mux_rsrc[i], + args); + if (rc) + break; + } + + if ((acquire_args->res_id >= + CAM_ISP_HW_VFE_IN_RDI0) && + (acquire_args->res_id <= + CAM_ISP_HW_VFE_IN_RDI3)) { + rc = cam_vfe_rdi_ver2_acquire_resource( + &top_priv->top_common.mux_rsrc[i], + args); + if (rc) + break; + } + + if (acquire_args->res_id == CAM_ISP_HW_VFE_IN_RD) { + rc = cam_vfe_fe_ver1_acquire_resource( + &top_priv->top_common.mux_rsrc[i], + args); + if (rc) + break; + } + + top_priv->top_common.mux_rsrc[i].cdm_ops = + acquire_args->cdm_ops; + top_priv->top_common.mux_rsrc[i].tasklet_info = + args->tasklet; + top_priv->top_common.mux_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_RESERVED; + acquire_args->rsrc_node = + &top_priv->top_common.mux_rsrc[i]; + + rc = 0; + break; + } + } + + return rc; + +} + +int cam_vfe_top_release(void *device_priv, + void *release_args, uint32_t arg_size) +{ + struct cam_vfe_top_ver2_priv *top_priv; + struct cam_isp_resource_node *mux_res; + + if (!device_priv || !release_args) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + top_priv = (struct cam_vfe_top_ver2_priv *)device_priv; + mux_res = (struct cam_isp_resource_node *)release_args; + + CAM_DBG(CAM_ISP, "Resource in state %d", mux_res->res_state); + if (mux_res->res_state < CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Error! Resource in Invalid res_state :%d", + mux_res->res_state); + return -EINVAL; + } + mux_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + return 0; +} + +int cam_vfe_top_start(void *device_priv, + void *start_args, uint32_t arg_size) +{ + struct cam_vfe_top_ver2_priv *top_priv; + struct cam_isp_resource_node *mux_res; + struct cam_hw_info *hw_info = NULL; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_vfe_soc_private *soc_private = NULL; + int rc = 0; + + if (!device_priv || !start_args) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + top_priv = (struct cam_vfe_top_ver2_priv *)device_priv; + soc_info = top_priv->common_data.soc_info; + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error soc_private NULL"); + return -EINVAL; + } + + mux_res = (struct cam_isp_resource_node *)start_args; + hw_info = (struct cam_hw_info *)mux_res->hw_intf->hw_priv; + + if (hw_info->hw_state == CAM_HW_STATE_POWER_UP) { + rc = cam_vfe_top_set_hw_clk_rate(top_priv); + if (rc) { + CAM_ERR(CAM_ISP, + "set_hw_clk_rate failed, rc=%d", rc); + return rc; + } + + rc = cam_vfe_top_set_axi_bw_vote(soc_private, + &top_priv->top_common, true); + if (rc) { + CAM_ERR(CAM_ISP, + "set_axi_bw_vote failed, rc=%d", rc); + return rc; + } + + if (mux_res->start) { + rc = mux_res->start(mux_res); + } else { + CAM_ERR(CAM_ISP, + "Invalid res id:%d", mux_res->res_id); + rc = -EINVAL; + } + } else { + CAM_ERR(CAM_ISP, "VFE HW not powered up"); + rc = -EPERM; + } + + return rc; +} + +int cam_vfe_top_stop(void *device_priv, + void *stop_args, uint32_t arg_size) +{ + struct cam_vfe_top_ver2_priv *top_priv; + struct cam_isp_resource_node *mux_res; + struct cam_hw_info *hw_info = NULL; + int i, rc = 0; + + if (!device_priv || !stop_args) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + top_priv = (struct cam_vfe_top_ver2_priv *)device_priv; + mux_res = (struct cam_isp_resource_node *)stop_args; + hw_info = (struct cam_hw_info *)mux_res->hw_intf->hw_priv; + + if ((mux_res->res_id == CAM_ISP_HW_VFE_IN_CAMIF) || + (mux_res->res_id == CAM_ISP_HW_VFE_IN_PDLIB) || + (mux_res->res_id == CAM_ISP_HW_VFE_IN_RD) || + ((mux_res->res_id >= CAM_ISP_HW_VFE_IN_RDI0) && + (mux_res->res_id <= CAM_ISP_HW_VFE_IN_RDI3))) { + rc = mux_res->stop(mux_res); + } else { + CAM_ERR(CAM_ISP, "Invalid res id:%d", mux_res->res_id); + return -EINVAL; + } + + if (!rc) { + for (i = 0; i < top_priv->top_common.num_mux; i++) { + if (top_priv->top_common.mux_rsrc[i].res_id == + mux_res->res_id) { + top_priv->req_clk_rate[i] = 0; + top_priv->req_clk_rate[i] = 0; + top_priv->top_common.req_axi_vote[i] + .axi_path[0].camnoc_bw = 0; + top_priv->top_common.req_axi_vote[i] + .axi_path[0].mnoc_ab_bw = 0; + top_priv->top_common.req_axi_vote[i] + .axi_path[0].mnoc_ib_bw = 0; + top_priv->top_common.axi_vote_control[i] = + CAM_VFE_BW_CONTROL_EXCLUDE; + break; + } + } + } + + return rc; +} + +int cam_vfe_top_read(void *device_priv, + void *read_args, uint32_t arg_size) +{ + return -EPERM; +} + +int cam_vfe_top_write(void *device_priv, + void *write_args, uint32_t arg_size) +{ + return -EPERM; +} + +int cam_vfe_top_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_vfe_top_ver2_priv *top_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_vfe_soc_private *soc_private = NULL; + + if (!device_priv || !cmd_args) { + CAM_ERR(CAM_ISP, "Error! Invalid arguments"); + return -EINVAL; + } + top_priv = (struct cam_vfe_top_ver2_priv *)device_priv; + soc_info = top_priv->common_data.soc_info; + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error soc_private NULL"); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_CHANGE_BASE: + rc = cam_vfe_top_mux_get_base(top_priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_GET_REG_UPDATE: + rc = cam_vfe_top_mux_get_reg_update(top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_CLOCK_UPDATE: + rc = cam_vfe_top_clock_update(top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_FE_UPDATE_IN_RD: + rc = cam_vfe_top_fs_update(top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_BW_UPDATE: + rc = cam_vfe_top_bw_update(soc_private, &top_priv->top_common, + cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_BW_UPDATE_V2: + rc = cam_vfe_top_bw_update_v2(soc_private, + &top_priv->top_common, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_BW_CONTROL: + rc = cam_vfe_top_bw_control(soc_private, &top_priv->top_common, + cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_DUMP_HW: + rc = cam_vfe_hw_dump(top_priv, + cmd_args, arg_size); + break; + default: + rc = -EINVAL; + CAM_ERR(CAM_ISP, "Error! Invalid cmd:%d", cmd_type); + break; + } + + return rc; +} + +int cam_vfe_top_ver2_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *top_hw_info, + void *vfe_irq_controller, + struct cam_vfe_top **vfe_top_ptr) +{ + int i, j, rc = 0; + struct cam_vfe_top_ver2_priv *top_priv = NULL; + struct cam_vfe_top_ver2_hw_info *ver2_hw_info = top_hw_info; + struct cam_vfe_top *vfe_top; + + vfe_top = kzalloc(sizeof(struct cam_vfe_top), GFP_KERNEL); + if (!vfe_top) { + CAM_DBG(CAM_ISP, "Error! Failed to alloc for vfe_top"); + rc = -ENOMEM; + goto end; + } + + top_priv = kzalloc(sizeof(struct cam_vfe_top_ver2_priv), + GFP_KERNEL); + if (!top_priv) { + CAM_DBG(CAM_ISP, "Error! Failed to alloc for vfe_top_priv"); + rc = -ENOMEM; + goto free_vfe_top; + } + + vfe_top->top_priv = top_priv; + top_priv->hw_clk_rate = 0; + if (ver2_hw_info->num_mux > CAM_VFE_TOP_MUX_MAX) { + CAM_ERR(CAM_ISP, "Invalid number of input rsrc: %d, max: %d", + ver2_hw_info->num_mux, CAM_VFE_TOP_MUX_MAX); + rc = -EINVAL; + goto free_top_priv; + } + + top_priv->top_common.num_mux = ver2_hw_info->num_mux; + + for (i = 0, j = 0; i < top_priv->top_common.num_mux; i++) { + top_priv->top_common.mux_rsrc[i].res_type = + CAM_ISP_RESOURCE_VFE_IN; + top_priv->top_common.mux_rsrc[i].hw_intf = hw_intf; + top_priv->top_common.mux_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + top_priv->req_clk_rate[i] = 0; + + if (ver2_hw_info->mux_type[i] == CAM_VFE_CAMIF_VER_2_0) { + top_priv->top_common.mux_rsrc[i].res_id = + CAM_ISP_HW_VFE_IN_CAMIF; + + rc = cam_vfe_camif_ver2_init(hw_intf, soc_info, + &ver2_hw_info->camif_hw_info, + &top_priv->top_common.mux_rsrc[i], + vfe_irq_controller); + if (rc) + goto deinit_resources; + } else if (ver2_hw_info->mux_type[i] == + CAM_VFE_CAMIF_LITE_VER_2_0) { + top_priv->top_common.mux_rsrc[i].res_id = + CAM_ISP_HW_VFE_IN_PDLIB; + + rc = cam_vfe_camif_lite_ver2_init(hw_intf, soc_info, + &ver2_hw_info->camif_lite_hw_info, + &top_priv->top_common.mux_rsrc[i], + vfe_irq_controller); + + if (rc) + goto deinit_resources; + } else if (ver2_hw_info->mux_type[i] == + CAM_VFE_RDI_VER_1_0) { + /* set the RDI resource id */ + top_priv->top_common.mux_rsrc[i].res_id = + CAM_ISP_HW_VFE_IN_RDI0 + j++; + + rc = cam_vfe_rdi_ver2_init(hw_intf, soc_info, + &ver2_hw_info->rdi_hw_info, + &top_priv->top_common.mux_rsrc[i], + vfe_irq_controller); + if (rc) + goto deinit_resources; + } else if (ver2_hw_info->mux_type[i] == + CAM_VFE_IN_RD_VER_1_0) { + /* set the RD resource id */ + top_priv->top_common.mux_rsrc[i].res_id = + CAM_ISP_HW_VFE_IN_RD; + + rc = cam_vfe_fe_ver1_init(hw_intf, soc_info, + &ver2_hw_info->fe_hw_info, + &top_priv->top_common.mux_rsrc[i]); + if (rc) + goto deinit_resources; + } else { + CAM_WARN(CAM_ISP, "Invalid mux type: %u", + ver2_hw_info->mux_type[i]); + } + } + + vfe_top->hw_ops.get_hw_caps = cam_vfe_top_get_hw_caps; + vfe_top->hw_ops.init = cam_vfe_top_init_hw; + vfe_top->hw_ops.reset = cam_vfe_top_reset; + vfe_top->hw_ops.reserve = cam_vfe_top_reserve; + vfe_top->hw_ops.release = cam_vfe_top_release; + vfe_top->hw_ops.start = cam_vfe_top_start; + vfe_top->hw_ops.stop = cam_vfe_top_stop; + vfe_top->hw_ops.read = cam_vfe_top_read; + vfe_top->hw_ops.write = cam_vfe_top_write; + vfe_top->hw_ops.process_cmd = cam_vfe_top_process_cmd; + *vfe_top_ptr = vfe_top; + + top_priv->common_data.soc_info = soc_info; + top_priv->common_data.hw_intf = hw_intf; + top_priv->top_common.hw_idx = hw_intf->hw_idx; + top_priv->common_data.common_reg = ver2_hw_info->common_reg; + top_priv->common_data.dump_data = ver2_hw_info->dump_data; + + return rc; + +deinit_resources: + for (--i; i >= 0; i--) { + if (ver2_hw_info->mux_type[i] == CAM_VFE_CAMIF_VER_2_0) { + if (cam_vfe_camif_ver2_deinit( + &top_priv->top_common.mux_rsrc[i])) + CAM_ERR(CAM_ISP, "Camif Deinit failed"); + } else if (ver2_hw_info->mux_type[i] == + CAM_VFE_CAMIF_LITE_VER_2_0) { + if (cam_vfe_camif_lite_ver2_deinit( + &top_priv->top_common.mux_rsrc[i])) + CAM_ERR(CAM_ISP, "Camif lite deinit failed"); + } else if (ver2_hw_info->mux_type[i] == + CAM_VFE_IN_RD_VER_1_0) { + if (cam_vfe_fe_ver1_deinit( + &top_priv->top_common.mux_rsrc[i])) + CAM_ERR(CAM_ISP, "VFE FE deinit failed"); + } else { + if (cam_vfe_rdi_ver2_deinit( + &top_priv->top_common.mux_rsrc[i])) + CAM_ERR(CAM_ISP, "RDI Deinit failed"); + } + top_priv->top_common.mux_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + } + +free_top_priv: + kfree(vfe_top->top_priv); +free_vfe_top: + kfree(vfe_top); +end: + return rc; +} + +int cam_vfe_top_ver2_deinit(struct cam_vfe_top **vfe_top_ptr) +{ + int i, rc = 0; + struct cam_vfe_top_ver2_priv *top_priv = NULL; + struct cam_vfe_top *vfe_top; + + if (!vfe_top_ptr) { + CAM_ERR(CAM_ISP, "Error! Invalid input"); + return -EINVAL; + } + + vfe_top = *vfe_top_ptr; + if (!vfe_top) { + CAM_ERR(CAM_ISP, "Error! vfe_top NULL"); + return -ENODEV; + } + + top_priv = vfe_top->top_priv; + if (!top_priv) { + CAM_ERR(CAM_ISP, "Error! vfe_top_priv NULL"); + rc = -ENODEV; + goto free_vfe_top; + } + + for (i = 0; i < top_priv->top_common.num_mux; i++) { + top_priv->top_common.mux_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + if (top_priv->top_common.mux_rsrc[i].res_type == + CAM_VFE_CAMIF_VER_2_0) { + rc = cam_vfe_camif_ver2_deinit( + &top_priv->top_common.mux_rsrc[i]); + if (rc) + CAM_ERR(CAM_ISP, "Camif deinit failed rc=%d", + rc); + } else if (top_priv->top_common.mux_rsrc[i].res_type == + CAM_VFE_CAMIF_LITE_VER_2_0) { + rc = cam_vfe_camif_lite_ver2_deinit( + &top_priv->top_common.mux_rsrc[i]); + if (rc) + CAM_ERR(CAM_ISP, + "Camif lite deinit failed rc=%d", rc); + } else if (top_priv->top_common.mux_rsrc[i].res_type == + CAM_VFE_RDI_VER_1_0) { + rc = cam_vfe_rdi_ver2_deinit( + &top_priv->top_common.mux_rsrc[i]); + if (rc) + CAM_ERR(CAM_ISP, "RDI deinit failed rc=%d", rc); + } else if (top_priv->top_common.mux_rsrc[i].res_type == + CAM_VFE_IN_RD_VER_1_0) { + rc = cam_vfe_fe_ver1_deinit( + &top_priv->top_common.mux_rsrc[i]); + if (rc) + CAM_ERR(CAM_ISP, "Camif deinit failed rc=%d", + rc); + } + } + + kfree(vfe_top->top_priv); + +free_vfe_top: + kfree(vfe_top); + *vfe_top_ptr = NULL; + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.h new file mode 100644 index 0000000000000000000000000000000000000000..65d01da159eceb89ec75daf7e24c2e9087b913ac --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_TOP_VER2_H_ +#define _CAM_VFE_TOP_VER2_H_ + +#include "cam_vfe_camif_ver2.h" +#include "cam_vfe_camif_lite_ver2.h" +#include "cam_vfe_rdi.h" +#include "cam_vfe_fe_ver1.h" +#include "cam_vfe_top_common.h" + +enum cam_vfe_top_ver2_module_type { + CAM_VFE_TOP_VER2_MODULE_LENS, + CAM_VFE_TOP_VER2_MODULE_STATS, + CAM_VFE_TOP_VER2_MODULE_COLOR, + CAM_VFE_TOP_VER2_MODULE_ZOOM, + CAM_VFE_TOP_VER2_MODULE_MAX, +}; + +struct cam_vfe_top_ver2_reg_offset_module_ctrl { + uint32_t reset; + uint32_t cgc_ovd; + uint32_t enable; +}; + +struct cam_vfe_top_ver2_reg_offset_common { + uint32_t hw_version; + uint32_t hw_capability; + uint32_t lens_feature; + uint32_t stats_feature; + uint32_t color_feature; + uint32_t zoom_feature; + uint32_t global_reset_cmd; + struct cam_vfe_top_ver2_reg_offset_module_ctrl + *module_ctrl[CAM_VFE_TOP_VER2_MODULE_MAX]; + uint32_t bus_cgc_ovd; + uint32_t core_cfg; + uint32_t three_D_cfg; + uint32_t violation_status; + uint32_t reg_update_cmd; +}; + +struct cam_vfe_top_ver2_hw_info { + struct cam_vfe_top_ver2_reg_offset_common *common_reg; + struct cam_vfe_camif_ver2_hw_info camif_hw_info; + struct cam_vfe_camif_lite_ver2_hw_info camif_lite_hw_info; + struct cam_vfe_rdi_ver2_hw_info rdi_hw_info; + struct cam_vfe_fe_ver1_hw_info fe_hw_info; + struct cam_vfe_top_dump_data *dump_data; + uint32_t num_mux; + uint32_t mux_type[CAM_VFE_TOP_MUX_MAX]; +}; + +int cam_vfe_top_ver2_init(struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *top_hw_info, + void *vfe_irq_controller, + struct cam_vfe_top **vfe_top_ptr); + +int cam_vfe_top_ver2_deinit(struct cam_vfe_top **vfe_top); + +#endif /* _CAM_VFE_TOP_VER2_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c new file mode 100644 index 0000000000000000000000000000000000000000..2bd393fc97a8b69d031ad59004f77f96e90034d5 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c @@ -0,0 +1,796 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_io_util.h" +#include "cam_cdm_util.h" +#include "cam_vfe_hw_intf.h" +#include "cam_vfe_top.h" +#include "cam_vfe_top_ver3.h" +#include "cam_debug_util.h" +#include "cam_vfe_soc.h" + +#define CAM_VFE_HW_RESET_HW_AND_REG_VAL 0x00000003 +#define CAM_VFE_HW_RESET_HW_VAL 0x007F0000 +#define CAM_VFE_LITE_HW_RESET_AND_REG_VAL 0x00000002 +#define CAM_VFE_LITE_HW_RESET_HW_VAL 0x0000003D + +struct cam_vfe_top_ver3_common_data { + struct cam_hw_soc_info *soc_info; + struct cam_hw_intf *hw_intf; + struct cam_vfe_top_ver3_reg_offset_common *common_reg; +}; + +struct cam_vfe_top_ver3_priv { + struct cam_vfe_top_ver3_common_data common_data; + unsigned long hw_clk_rate; + unsigned long req_clk_rate[ + CAM_VFE_TOP_MUX_MAX]; + struct cam_vfe_top_priv_common top_common; +}; + +static int cam_vfe_top_ver3_mux_get_base(struct cam_vfe_top_ver3_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + uint32_t size = 0; + uint32_t mem_base = 0; + struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; + + if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { + CAM_ERR(CAM_ISP, "Error, Invalid cmd size"); + return -EINVAL; + } + + if (!cdm_args || !cdm_args->res || !top_priv || + !top_priv->common_data.soc_info) { + CAM_ERR(CAM_ISP, "Error, Invalid args"); + return -EINVAL; + } + + cdm_util_ops = + (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; + + if (!cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid CDM ops"); + return -EINVAL; + } + + size = cdm_util_ops->cdm_required_size_changebase(); + /* since cdm returns dwords, we need to convert it into bytes */ + if ((size * 4) > cdm_args->cmd.size) { + CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d", + cdm_args->cmd.size, size); + return -EINVAL; + } + + mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE( + top_priv->common_data.soc_info, VFE_CORE_BASE_IDX); + CAM_DBG(CAM_ISP, "core %d mem_base 0x%x", + top_priv->common_data.soc_info->index, mem_base); + + cdm_util_ops->cdm_write_changebase( + cdm_args->cmd.cmd_buf_addr, mem_base); + cdm_args->cmd.used_bytes = (size * 4); + + return 0; +} + +static int cam_vfe_top_ver3_set_hw_clk_rate( + struct cam_vfe_top_ver3_priv *top_priv) +{ + struct cam_hw_soc_info *soc_info = NULL; + struct cam_vfe_soc_private *soc_private = NULL; + struct cam_ahb_vote ahb_vote; + int i, rc = 0, clk_lvl = -1; + unsigned long max_clk_rate = 0; + + soc_info = top_priv->common_data.soc_info; + soc_private = + (struct cam_vfe_soc_private *)soc_info->soc_private; + + for (i = 0; i < top_priv->top_common.num_mux; i++) { + if (top_priv->req_clk_rate[i] > max_clk_rate) + max_clk_rate = top_priv->req_clk_rate[i]; + } + if (max_clk_rate == top_priv->hw_clk_rate) + return 0; + + CAM_DBG(CAM_PERF, "VFE: Clock name=%s idx=%d clk=%llu", + soc_info->clk_name[soc_info->src_clk_idx], + soc_info->src_clk_idx, max_clk_rate); + + rc = cam_soc_util_set_src_clk_rate(soc_info, max_clk_rate); + + if (!rc) { + top_priv->hw_clk_rate = max_clk_rate; + rc = cam_soc_util_get_clk_level(soc_info, max_clk_rate, + soc_info->src_clk_idx, &clk_lvl); + if (rc) { + CAM_WARN(CAM_ISP, + "Failed to get clk level for %s with clk_rate %llu src_idx %d rc %d", + soc_info->dev_name, max_clk_rate, + soc_info->src_clk_idx, rc); + rc = 0; + goto end; + } + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = clk_lvl; + cam_cpas_update_ahb_vote(soc_private->cpas_handle, &ahb_vote); + } else { + CAM_ERR(CAM_PERF, "Set Clock rate failed, rc=%d", rc); + } + +end: + return rc; +} + +static int cam_vfe_top_fs_update( + struct cam_vfe_top_ver3_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_vfe_fe_update_args *cmd_update = cmd_args; + + if (cmd_update->node_res->process_cmd) + return cmd_update->node_res->process_cmd(cmd_update->node_res, + CAM_ISP_HW_CMD_FE_UPDATE_IN_RD, cmd_args, arg_size); + + return 0; +} + +static int cam_vfe_top_ver3_clock_update( + struct cam_vfe_top_ver3_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_vfe_clock_update_args *clk_update = NULL; + struct cam_isp_resource_node *res = NULL; + struct cam_hw_info *hw_info = NULL; + int i, rc = 0; + + clk_update = + (struct cam_vfe_clock_update_args *)cmd_args; + res = clk_update->node_res; + + if (!res || !res->hw_intf->hw_priv) { + CAM_ERR(CAM_PERF, "Invalid input res %pK", res); + return -EINVAL; + } + + hw_info = res->hw_intf->hw_priv; + + if (res->res_type != CAM_ISP_RESOURCE_VFE_IN || + res->res_id >= CAM_ISP_HW_VFE_IN_MAX) { + CAM_ERR(CAM_PERF, "VFE:%d Invalid res_type:%d res id%d", + res->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + for (i = 0; i < top_priv->top_common.num_mux; i++) { + if (top_priv->top_common.mux_rsrc[i].res_id == res->res_id) { + top_priv->req_clk_rate[i] = clk_update->clk_rate; + break; + } + } + + if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_DBG(CAM_PERF, + "VFE:%d Not ready to set clocks yet :%d", + res->hw_intf->hw_idx, + hw_info->hw_state); + } else + rc = cam_vfe_top_ver3_set_hw_clk_rate(top_priv); + + return rc; +} + +static int cam_vfe_core_config_control( + struct cam_vfe_top_ver3_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_vfe_core_config_args *core_config = cmd_args; + + if (core_config->node_res->process_cmd) + return core_config->node_res->process_cmd(core_config->node_res, + CAM_ISP_HW_CMD_CORE_CONFIG, cmd_args, arg_size); + + return -EINVAL; +} + +static int cam_vfe_top_ver3_mux_get_reg_update( + struct cam_vfe_top_ver3_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_isp_hw_get_cmd_update *cmd_update = cmd_args; + + if (cmd_update->res->process_cmd) + return cmd_update->res->process_cmd(cmd_update->res, + CAM_ISP_HW_CMD_GET_REG_UPDATE, cmd_args, arg_size); + + return -EINVAL; +} + +int cam_vfe_top_ver3_get_hw_caps(void *device_priv, + void *get_hw_cap_args, uint32_t arg_size) +{ + return -EPERM; +} + +int cam_vfe_top_ver3_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_vfe_top_ver3_priv *top_priv = device_priv; + struct cam_vfe_top_ver3_common_data common_data = top_priv->common_data; + + top_priv->hw_clk_rate = 0; + + /* Disable clock gating at IFE top */ + CAM_INFO(CAM_ISP, "Disable clock gating at IFE top"); + cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, + common_data.common_reg->core_cgc_ovd_0, 0xFFFFFFFF); + + cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, + common_data.common_reg->core_cgc_ovd_1, 0xFF); + + cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, + common_data.common_reg->ahb_cgc_ovd, 0x1); + + cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, + common_data.common_reg->noc_cgc_ovd, 0x1); + + return 0; +} + +int cam_vfe_top_ver3_reset(void *device_priv, + void *reset_core_args, uint32_t arg_size) +{ + struct cam_vfe_top_ver3_priv *top_priv = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_vfe_soc_private *soc_private = NULL; + struct cam_vfe_top_ver3_reg_offset_common *reg_common = NULL; + uint32_t *reset_reg_args = reset_core_args; + uint32_t reset_reg_val; + + if (!top_priv || !reset_reg_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + soc_info = top_priv->common_data.soc_info; + reg_common = top_priv->common_data.common_reg; + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Invalid soc_private"); + return -ENODEV; + } + + switch (*reset_reg_args) { + case CAM_VFE_HW_RESET_HW_AND_REG: + if (!soc_private->is_ife_lite) + reset_reg_val = CAM_VFE_HW_RESET_HW_AND_REG_VAL; + else + reset_reg_val = CAM_VFE_LITE_HW_RESET_AND_REG_VAL; + break; + default: + if (!soc_private->is_ife_lite) + reset_reg_val = CAM_VFE_HW_RESET_HW_VAL; + else + reset_reg_val = CAM_VFE_LITE_HW_RESET_HW_VAL; + break; + } + /* override due to hw limitation */ + if (!soc_private->is_ife_lite) + reset_reg_val = CAM_VFE_HW_RESET_HW_AND_REG_VAL; + else + reset_reg_val = CAM_VFE_LITE_HW_RESET_AND_REG_VAL; + + CAM_DBG(CAM_ISP, "reset reg value: 0x%x", reset_reg_val); + + /* Mask All the IRQs except RESET */ + if (!soc_private->is_ife_lite) + cam_io_w_mb(0x00000001, + CAM_SOC_GET_REG_MAP_START(soc_info, VFE_CORE_BASE_IDX) + + 0x3C); + else + cam_io_w_mb(0x00020000, + CAM_SOC_GET_REG_MAP_START(soc_info, VFE_CORE_BASE_IDX) + + 0x28); + + /* Reset HW */ + cam_io_w_mb(reset_reg_val, + CAM_SOC_GET_REG_MAP_START(soc_info, VFE_CORE_BASE_IDX) + + reg_common->global_reset_cmd); + + CAM_DBG(CAM_ISP, "Reset HW exit"); + return 0; +} + +int cam_vfe_top_ver3_reserve(void *device_priv, + void *reserve_args, uint32_t arg_size) +{ + struct cam_vfe_top_ver3_priv *top_priv; + struct cam_vfe_acquire_args *args; + struct cam_vfe_hw_vfe_in_acquire_args *acquire_args; + uint32_t i; + int rc = -EINVAL; + + if (!device_priv || !reserve_args) { + CAM_ERR(CAM_ISP, "Error, Invalid input arguments"); + return -EINVAL; + } + + top_priv = (struct cam_vfe_top_ver3_priv *)device_priv; + args = (struct cam_vfe_acquire_args *)reserve_args; + acquire_args = &args->vfe_in; + + CAM_DBG(CAM_ISP, "res id %d", acquire_args->res_id); + + + for (i = 0; i < top_priv->top_common.num_mux; i++) { + if (top_priv->top_common.mux_rsrc[i].res_id == + acquire_args->res_id && + top_priv->top_common.mux_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + + if (acquire_args->res_id == CAM_ISP_HW_VFE_IN_CAMIF) { + rc = cam_vfe_camif_ver3_acquire_resource( + &top_priv->top_common.mux_rsrc[i], + args); + if (rc) + break; + } + + if (acquire_args->res_id >= CAM_ISP_HW_VFE_IN_RDI0 && + acquire_args->res_id < CAM_ISP_HW_VFE_IN_MAX) { + rc = cam_vfe_camif_lite_ver3_acquire_resource( + &top_priv->top_common.mux_rsrc[i], + args); + if (rc) + break; + } + + if (acquire_args->res_id == CAM_ISP_HW_VFE_IN_RD) { + rc = cam_vfe_fe_ver1_acquire_resource( + &top_priv->top_common.mux_rsrc[i], + args); + if (rc) + break; + } + + top_priv->top_common.mux_rsrc[i].cdm_ops = + acquire_args->cdm_ops; + top_priv->top_common.mux_rsrc[i].tasklet_info = + args->tasklet; + top_priv->top_common.mux_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_RESERVED; + acquire_args->rsrc_node = + &top_priv->top_common.mux_rsrc[i]; + + rc = 0; + break; + } + } + + return rc; + +} + +int cam_vfe_top_ver3_release(void *device_priv, + void *release_args, uint32_t arg_size) +{ + struct cam_vfe_top_ver3_priv *top_priv; + struct cam_isp_resource_node *mux_res; + + if (!device_priv || !release_args) { + CAM_ERR(CAM_ISP, "Error, Invalid input arguments"); + return -EINVAL; + } + + top_priv = (struct cam_vfe_top_ver3_priv *)device_priv; + mux_res = (struct cam_isp_resource_node *)release_args; + + CAM_DBG(CAM_ISP, "Resource in state %d", mux_res->res_state); + if (mux_res->res_state < CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Error, Resource in Invalid res_state :%d", + mux_res->res_state); + return -EINVAL; + } + mux_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + return 0; +} + +int cam_vfe_top_ver3_start(void *device_priv, + void *start_args, uint32_t arg_size) +{ + struct cam_vfe_top_ver3_priv *top_priv; + struct cam_isp_resource_node *mux_res; + struct cam_hw_info *hw_info = NULL; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_vfe_soc_private *soc_private = NULL; + int rc = 0; + + if (!device_priv || !start_args) { + CAM_ERR(CAM_ISP, "Error, Invalid input arguments"); + return -EINVAL; + } + + top_priv = (struct cam_vfe_top_ver3_priv *)device_priv; + soc_info = top_priv->common_data.soc_info; + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error soc_private NULL"); + return -EINVAL; + } + + mux_res = (struct cam_isp_resource_node *)start_args; + hw_info = (struct cam_hw_info *)mux_res->hw_intf->hw_priv; + + if (hw_info->hw_state == CAM_HW_STATE_POWER_UP) { + rc = cam_vfe_top_ver3_set_hw_clk_rate(top_priv); + if (rc) { + CAM_ERR(CAM_ISP, + "set_hw_clk_rate failed, rc=%d", rc); + return rc; + } + + rc = cam_vfe_top_set_axi_bw_vote(soc_private, + &top_priv->top_common, true); + if (rc) { + CAM_ERR(CAM_ISP, + "set_axi_bw_vote failed, rc=%d", rc); + return rc; + } + + if (mux_res->start) { + rc = mux_res->start(mux_res); + } else { + CAM_ERR(CAM_ISP, + "Invalid res id:%d", mux_res->res_id); + rc = -EINVAL; + } + } else { + CAM_ERR(CAM_ISP, "VFE HW not powered up"); + rc = -EPERM; + } + + return rc; +} + +int cam_vfe_top_ver3_stop(void *device_priv, + void *stop_args, uint32_t arg_size) +{ + struct cam_vfe_top_ver3_priv *top_priv; + struct cam_isp_resource_node *mux_res; + struct cam_hw_info *hw_info = NULL; + int i, rc = 0; + + if (!device_priv || !stop_args) { + CAM_ERR(CAM_ISP, "Error, Invalid input arguments"); + return -EINVAL; + } + + top_priv = (struct cam_vfe_top_ver3_priv *)device_priv; + mux_res = (struct cam_isp_resource_node *)stop_args; + hw_info = (struct cam_hw_info *)mux_res->hw_intf->hw_priv; + + if (mux_res->res_id < CAM_ISP_HW_VFE_IN_MAX) { + rc = mux_res->stop(mux_res); + } else { + CAM_ERR(CAM_ISP, "Invalid res id:%d", mux_res->res_id); + return -EINVAL; + } + + if (!rc) { + for (i = 0; i < top_priv->top_common.num_mux; i++) { + if (top_priv->top_common.mux_rsrc[i].res_id == + mux_res->res_id) { + top_priv->req_clk_rate[i] = 0; + memset(&top_priv->top_common.req_axi_vote[i], + 0, sizeof(struct cam_axi_vote)); + top_priv->top_common.axi_vote_control[i] = + CAM_VFE_BW_CONTROL_EXCLUDE; + break; + } + } + } + + return rc; +} + +int cam_vfe_top_ver3_read(void *device_priv, + void *read_args, uint32_t arg_size) +{ + return -EPERM; +} + +int cam_vfe_top_ver3_write(void *device_priv, + void *write_args, uint32_t arg_size) +{ + return -EPERM; +} + +int cam_vfe_top_ver3_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_vfe_top_ver3_priv *top_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_vfe_soc_private *soc_private = NULL; + + if (!device_priv || !cmd_args) { + CAM_ERR(CAM_ISP, "Error, Invalid arguments"); + return -EINVAL; + } + + top_priv = (struct cam_vfe_top_ver3_priv *)device_priv; + soc_info = top_priv->common_data.soc_info; + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error soc_private NULL"); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_CHANGE_BASE: + rc = cam_vfe_top_ver3_mux_get_base(top_priv, + cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_GET_REG_UPDATE: + rc = cam_vfe_top_ver3_mux_get_reg_update(top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_CLOCK_UPDATE: + rc = cam_vfe_top_ver3_clock_update(top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_FE_UPDATE_IN_RD: + rc = cam_vfe_top_fs_update(top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_BW_UPDATE: + rc = cam_vfe_top_bw_update(soc_private, &top_priv->top_common, + cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_BW_UPDATE_V2: + rc = cam_vfe_top_bw_update_v2(soc_private, + &top_priv->top_common, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_BW_CONTROL: + rc = cam_vfe_top_bw_control(soc_private, &top_priv->top_common, + cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_CORE_CONFIG: + rc = cam_vfe_core_config_control(top_priv, cmd_args, arg_size); + break; + default: + rc = -EINVAL; + CAM_ERR(CAM_ISP, "Error, Invalid cmd:%d", cmd_type); + break; + } + + return rc; +} + +int cam_vfe_top_ver3_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *top_hw_info, + void *vfe_irq_controller, + struct cam_vfe_top **vfe_top_ptr) +{ + int i, j, rc = 0; + struct cam_vfe_top_ver3_priv *top_priv = NULL; + struct cam_vfe_top_ver3_hw_info *ver3_hw_info = top_hw_info; + struct cam_vfe_top *vfe_top; + + vfe_top = kzalloc(sizeof(struct cam_vfe_top), GFP_KERNEL); + if (!vfe_top) { + CAM_DBG(CAM_ISP, "Error, Failed to alloc for vfe_top"); + rc = -ENOMEM; + goto end; + } + + top_priv = kzalloc(sizeof(struct cam_vfe_top_ver3_priv), + GFP_KERNEL); + if (!top_priv) { + CAM_DBG(CAM_ISP, "Error, Failed to alloc for vfe_top_priv"); + rc = -ENOMEM; + goto free_vfe_top; + } + + vfe_top->top_priv = top_priv; + top_priv->hw_clk_rate = 0; + if (ver3_hw_info->num_mux > CAM_VFE_TOP_MUX_MAX) { + CAM_ERR(CAM_ISP, "Invalid number of input rsrc: %d, max: %d", + ver3_hw_info->num_mux, CAM_VFE_TOP_MUX_MAX); + rc = -EINVAL; + goto free_top_priv; + } + + top_priv->top_common.num_mux = ver3_hw_info->num_mux; + + for (i = 0, j = 0; i < top_priv->top_common.num_mux && + j < CAM_VFE_RDI_VER2_MAX; i++) { + top_priv->top_common.mux_rsrc[i].res_type = + CAM_ISP_RESOURCE_VFE_IN; + top_priv->top_common.mux_rsrc[i].hw_intf = hw_intf; + top_priv->top_common.mux_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + top_priv->req_clk_rate[i] = 0; + + if (ver3_hw_info->mux_type[i] == CAM_VFE_CAMIF_VER_3_0) { + top_priv->top_common.mux_rsrc[i].res_id = + CAM_ISP_HW_VFE_IN_CAMIF; + + rc = cam_vfe_camif_ver3_init(hw_intf, soc_info, + &ver3_hw_info->camif_hw_info, + &top_priv->top_common.mux_rsrc[i], + vfe_irq_controller); + if (rc) + goto deinit_resources; + } else if (ver3_hw_info->mux_type[i] == + CAM_VFE_PDLIB_VER_1_0) { + /* set the PDLIB resource id */ + top_priv->top_common.mux_rsrc[i].res_id = + CAM_ISP_HW_VFE_IN_PDLIB; + + rc = cam_vfe_camif_lite_ver3_init(hw_intf, soc_info, + &ver3_hw_info->pdlib_hw_info, + &top_priv->top_common.mux_rsrc[i], + vfe_irq_controller); + if (rc) + goto deinit_resources; + } else if (ver3_hw_info->mux_type[i] == + CAM_VFE_IN_RD_VER_1_0) { + /* set the RD resource id */ + top_priv->top_common.mux_rsrc[i].res_id = + CAM_ISP_HW_VFE_IN_RD; + + rc = cam_vfe_fe_ver1_init(hw_intf, soc_info, + &ver3_hw_info->fe_hw_info, + &top_priv->top_common.mux_rsrc[i]); + if (rc) + goto deinit_resources; + } else if (ver3_hw_info->mux_type[i] == + CAM_VFE_RDI_VER_1_0) { + /* set the RDI resource id */ + top_priv->top_common.mux_rsrc[i].res_id = + CAM_ISP_HW_VFE_IN_RDI0 + j; + + rc = cam_vfe_camif_lite_ver3_init(hw_intf, soc_info, + ver3_hw_info->rdi_hw_info[j++], + &top_priv->top_common.mux_rsrc[i], + vfe_irq_controller); + if (rc) + goto deinit_resources; + } else if (ver3_hw_info->mux_type[i] == + CAM_VFE_LCR_VER_1_0) { + /* set the LCR resource id */ + top_priv->top_common.mux_rsrc[i].res_id = + CAM_ISP_HW_VFE_IN_LCR; + + rc = cam_vfe_camif_lite_ver3_init(hw_intf, soc_info, + &ver3_hw_info->lcr_hw_info, + &top_priv->top_common.mux_rsrc[i], + vfe_irq_controller); + if (rc) + goto deinit_resources; + } else { + CAM_WARN(CAM_ISP, "Invalid mux type: %u", + ver3_hw_info->mux_type[i]); + } + } + + vfe_top->hw_ops.get_hw_caps = cam_vfe_top_ver3_get_hw_caps; + vfe_top->hw_ops.init = cam_vfe_top_ver3_init_hw; + vfe_top->hw_ops.reset = cam_vfe_top_ver3_reset; + vfe_top->hw_ops.reserve = cam_vfe_top_ver3_reserve; + vfe_top->hw_ops.release = cam_vfe_top_ver3_release; + vfe_top->hw_ops.start = cam_vfe_top_ver3_start; + vfe_top->hw_ops.stop = cam_vfe_top_ver3_stop; + vfe_top->hw_ops.read = cam_vfe_top_ver3_read; + vfe_top->hw_ops.write = cam_vfe_top_ver3_write; + vfe_top->hw_ops.process_cmd = cam_vfe_top_ver3_process_cmd; + *vfe_top_ptr = vfe_top; + + top_priv->common_data.soc_info = soc_info; + top_priv->common_data.hw_intf = hw_intf; + top_priv->top_common.hw_idx = hw_intf->hw_idx; + top_priv->common_data.common_reg = ver3_hw_info->common_reg; + + return rc; + +deinit_resources: + for (--i; i >= 0; i--) { + if (ver3_hw_info->mux_type[i] == CAM_VFE_CAMIF_VER_3_0) { + if (cam_vfe_camif_ver3_deinit( + &top_priv->top_common.mux_rsrc[i])) + CAM_ERR(CAM_ISP, "Camif Deinit failed"); + } else if (ver3_hw_info->mux_type[i] == CAM_VFE_IN_RD_VER_1_0) { + if (cam_vfe_fe_ver1_deinit( + &top_priv->top_common.mux_rsrc[i])) + CAM_ERR(CAM_ISP, "Camif fe Deinit failed"); + } else { + if (cam_vfe_camif_lite_ver3_deinit( + &top_priv->top_common.mux_rsrc[i])) + CAM_ERR(CAM_ISP, + "Camif lite res id %d Deinit failed", + top_priv->top_common.mux_rsrc[i] + .res_id); + } + top_priv->top_common.mux_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + } + +free_top_priv: + kfree(vfe_top->top_priv); +free_vfe_top: + kfree(vfe_top); +end: + return rc; +} + +int cam_vfe_top_ver3_deinit(struct cam_vfe_top **vfe_top_ptr) +{ + int i, rc = 0; + struct cam_vfe_top_ver3_priv *top_priv = NULL; + struct cam_vfe_top *vfe_top; + + if (!vfe_top_ptr) { + CAM_ERR(CAM_ISP, "Error, Invalid input"); + return -EINVAL; + } + + vfe_top = *vfe_top_ptr; + if (!vfe_top) { + CAM_ERR(CAM_ISP, "Error, vfe_top NULL"); + return -ENODEV; + } + + top_priv = vfe_top->top_priv; + if (!top_priv) { + CAM_ERR(CAM_ISP, "Error, vfe_top_priv NULL"); + rc = -ENODEV; + goto free_vfe_top; + } + + for (i = 0; i < top_priv->top_common.num_mux; i++) { + top_priv->top_common.mux_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + if (top_priv->top_common.mux_rsrc[i].res_type == + CAM_VFE_CAMIF_VER_3_0) { + rc = cam_vfe_camif_ver3_deinit( + &top_priv->top_common.mux_rsrc[i]); + if (rc) + CAM_ERR(CAM_ISP, "Camif deinit failed rc=%d", + rc); + } else if (top_priv->top_common.mux_rsrc[i].res_type == + CAM_VFE_IN_RD_VER_1_0) { + rc = cam_vfe_fe_ver1_deinit( + &top_priv->top_common.mux_rsrc[i]); + if (rc) + CAM_ERR(CAM_ISP, "Camif deinit failed rc=%d", + rc); + } else { + rc = cam_vfe_camif_lite_ver3_deinit( + &top_priv->top_common.mux_rsrc[i]); + if (rc) + CAM_ERR(CAM_ISP, + "Camif lite res id %d Deinit failed", + top_priv->top_common.mux_rsrc[i] + .res_id); + } + } + + kfree(vfe_top->top_priv); + +free_vfe_top: + kfree(vfe_top); + *vfe_top_ptr = NULL; + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.h new file mode 100644 index 0000000000000000000000000000000000000000..4a24ba6ddf76aa43071c84be357f5f0e6cdb3963 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_TOP_VER3_H_ +#define _CAM_VFE_TOP_VER3_H_ + +#include "cam_vfe_camif_ver3.h" +#include "cam_vfe_camif_lite_ver3.h" +#include "cam_vfe_fe_ver1.h" +#include "cam_vfe_top_common.h" + +#define CAM_SHIFT_TOP_CORE_CFG_MUXSEL_PDAF 31 +#define CAM_SHIFT_TOP_CORE_CFG_VID_DS16_R2PD 30 +#define CAM_SHIFT_TOP_CORE_CFG_VID_DS4_R2PD 29 +#define CAM_SHIFT_TOP_CORE_CFG_DISP_DS16_R2PD 28 +#define CAM_SHIFT_TOP_CORE_CFG_DISP_DS4_R2PD 27 +#define CAM_SHIFT_TOP_CORE_CFG_DSP_STREAMING 25 +#define CAM_SHIFT_TOP_CORE_CFG_STATS_IHIST 10 +#define CAM_SHIFT_TOP_CORE_CFG_STATS_HDR_BE 9 +#define CAM_SHIFT_TOP_CORE_CFG_STATS_HDR_BHIST 8 +#define CAM_SHIFT_TOP_CORE_CFG_INPUTMUX_PP 5 + +struct cam_vfe_top_ver3_reg_offset_common { + uint32_t hw_version; + uint32_t titan_version; + uint32_t hw_capability; + uint32_t lens_feature; + uint32_t stats_feature; + uint32_t color_feature; + uint32_t zoom_feature; + uint32_t global_reset_cmd; + uint32_t core_cgc_ovd_0; + uint32_t core_cgc_ovd_1; + uint32_t ahb_cgc_ovd; + uint32_t noc_cgc_ovd; + uint32_t bus_cgc_ovd; + uint32_t core_cfg_0; + uint32_t core_cfg_1; + uint32_t reg_update_cmd; + uint32_t trigger_cdm_events; + uint32_t violation_status; + uint32_t custom_frame_idx; + uint32_t dsp_status; + uint32_t diag_config; + uint32_t diag_sensor_status_0; + uint32_t diag_sensor_status_1; + uint32_t bus_overflow_status; + uint32_t top_debug_cfg; + uint32_t top_debug_0; + uint32_t top_debug_1; + uint32_t top_debug_2; + uint32_t top_debug_3; + uint32_t top_debug_4; + uint32_t top_debug_5; + uint32_t top_debug_6; + uint32_t top_debug_7; + uint32_t top_debug_8; + uint32_t top_debug_9; + uint32_t top_debug_10; + uint32_t top_debug_11; + uint32_t top_debug_12; + uint32_t top_debug_13; +}; + +struct cam_vfe_camif_common_cfg { + uint32_t vid_ds16_r2pd; + uint32_t vid_ds4_r2pd; + uint32_t disp_ds16_r2pd; + uint32_t disp_ds4_r2pd; + uint32_t dsp_streaming_tap_point; + uint32_t ihist_src_sel; + uint32_t hdr_be_src_sel; + uint32_t hdr_bhist_src_sel; + uint32_t input_mux_sel_pdaf; + uint32_t input_mux_sel_pp; +}; + +struct cam_vfe_top_ver3_hw_info { + struct cam_vfe_top_ver3_reg_offset_common *common_reg; + struct cam_vfe_camif_ver3_hw_info camif_hw_info; + struct cam_vfe_camif_lite_ver3_hw_info pdlib_hw_info; + struct cam_vfe_camif_lite_ver3_hw_info + *rdi_hw_info[CAM_VFE_RDI_VER2_MAX]; + struct cam_vfe_camif_lite_ver3_hw_info lcr_hw_info; + struct cam_vfe_fe_ver1_hw_info fe_hw_info; + uint32_t num_mux; + uint32_t mux_type[CAM_VFE_TOP_MUX_MAX]; +}; + +int cam_vfe_top_ver3_init(struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *top_hw_info, + void *vfe_irq_controller, + struct cam_vfe_top **vfe_top); + +int cam_vfe_top_ver3_deinit(struct cam_vfe_top **vfe_top); + +#endif /* _CAM_VFE_TOP_VER3_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include/cam_vfe_top.h b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include/cam_vfe_top.h new file mode 100644 index 0000000000000000000000000000000000000000..932cab858a7094a0b094d9bd43e45fa95f904657 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include/cam_vfe_top.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_VFE_TOP_H_ +#define _CAM_VFE_TOP_H_ + +#include "cam_hw_intf.h" +#include "cam_isp_hw.h" + +#define CAM_VFE_TOP_VER_1_0 0x100000 +#define CAM_VFE_TOP_VER_2_0 0x200000 +#define CAM_VFE_TOP_VER_3_0 0x300000 + +#define CAM_VFE_CAMIF_VER_1_0 0x10 +#define CAM_VFE_CAMIF_VER_2_0 0x20 +#define CAM_VFE_CAMIF_VER_3_0 0x30 + +#define CAM_VFE_CAMIF_LITE_VER_2_0 0x02 + +#define CAM_VFE_RDI_VER_1_0 0x1000 +#define CAM_VFE_IN_RD_VER_1_0 0x2000 + +#define CAM_VFE_LCR_VER_1_0 0x100 +#define CAM_VFE_PDLIB_VER_1_0 0x10000 + +/* + * Debug values for camif module + */ +#define CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS BIT(0) +#define CAMIF_DEBUG_ENABLE_REG_DUMP BIT(1) +#define CAM_VFE_CAMIF_EVT_MAX 256 + +struct cam_vfe_top { + void *top_priv; + struct cam_hw_ops hw_ops; +}; + +int cam_vfe_top_init(uint32_t top_version, + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *top_hw_info, + void *vfe_irq_controller, + struct cam_vfe_top **vfe_top); + +int cam_vfe_top_deinit(uint32_t top_version, + struct cam_vfe_top **vfe_top); + +#endif /* _CAM_VFE_TOP_H_*/ diff --git a/techpack/camera-bengal/drivers/cam_jpeg/Makefile b/techpack/camera-bengal/drivers/cam_jpeg/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..b24a1281ea9ab0fe7a36ba3a457e58062aeef436 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include/ + +obj-$(CONFIG_SPECTRA_CAMERA) += jpeg_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_jpeg_dev.o cam_jpeg_context.o diff --git a/techpack/camera-bengal/drivers/cam_jpeg/cam_jpeg_context.c b/techpack/camera-bengal/drivers/cam_jpeg/cam_jpeg_context.c new file mode 100644 index 0000000000000000000000000000000000000000..b28f8b6672393ffdb185e4dd66548f6778b6f52c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/cam_jpeg_context.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "cam_mem_mgr.h" +#include "cam_jpeg_context.h" +#include "cam_context_utils.h" +#include "cam_debug_util.h" +#include "cam_packet_util.h" + +static const char jpeg_dev_name[] = "cam-jpeg"; + +static int cam_jpeg_context_dump_active_request(void *data, unsigned long iova, + uint32_t buf_info) +{ + + struct cam_context *ctx = (struct cam_context *)data; + struct cam_ctx_request *req = NULL; + struct cam_ctx_request *req_temp = NULL; + struct cam_hw_mgr_dump_pf_data *pf_dbg_entry = NULL; + int rc = 0; + int closest_port; + bool b_mem_found = false; + + + if (!ctx) { + CAM_ERR(CAM_JPEG, "Invalid ctx"); + return -EINVAL; + } + + CAM_INFO(CAM_JPEG, "iommu fault for jpeg ctx %d state %d", + ctx->ctx_id, ctx->state); + + list_for_each_entry_safe(req, req_temp, + &ctx->active_req_list, list) { + pf_dbg_entry = &(req->pf_data); + closest_port = -1; + CAM_INFO(CAM_JPEG, "req_id : %lld ", req->request_id); + + rc = cam_context_dump_pf_info_to_hw(ctx, pf_dbg_entry->packet, + iova, buf_info, &b_mem_found); + if (rc) + CAM_ERR(CAM_JPEG, "Failed to dump pf info"); + + if (b_mem_found) + CAM_ERR(CAM_JPEG, "Found page fault in req %lld %d", + req->request_id, rc); + } + return rc; +} + +static int __cam_jpeg_ctx_acquire_dev_in_available(struct cam_context *ctx, + struct cam_acquire_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_acquire_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_JPEG, "Unable to Acquire device %d", rc); + else + ctx->state = CAM_CTX_ACQUIRED; + + return rc; +} + +static int __cam_jpeg_ctx_release_dev_in_acquired(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_release_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_JPEG, "Unable to release device %d", rc); + + ctx->state = CAM_CTX_AVAILABLE; + + return rc; +} + +static int __cam_jpeg_ctx_dump_dev_in_acquired( + struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc; + + rc = cam_context_dump_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_JPEG, "Failed to dump device, rc=%d", rc); + + return rc; +} + +static int __cam_jpeg_ctx_flush_dev_in_acquired(struct cam_context *ctx, + struct cam_flush_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_flush_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_ICP, "Failed to flush device"); + + return rc; +} + +static int __cam_jpeg_ctx_config_dev_in_acquired(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + return cam_context_prepare_dev_to_hw(ctx, cmd); +} + +static int __cam_jpeg_ctx_handle_buf_done_in_acquired(void *ctx, + uint32_t evt_id, void *done) +{ + return cam_context_buf_done_from_hw(ctx, done, evt_id); +} + +static int __cam_jpeg_ctx_stop_dev_in_acquired(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_stop_dev_to_hw(ctx); + if (rc) { + CAM_ERR(CAM_JPEG, "Failed in Stop dev, rc=%d", rc); + return rc; + } + + return rc; +} + +/* top state machine */ +static struct cam_ctx_ops + cam_jpeg_ctx_state_machine[CAM_CTX_STATE_MAX] = { + /* Uninit */ + { + .ioctl_ops = { }, + .crm_ops = { }, + .irq_ops = NULL, + }, + /* Available */ + { + .ioctl_ops = { + .acquire_dev = __cam_jpeg_ctx_acquire_dev_in_available, + }, + .crm_ops = { }, + .irq_ops = NULL, + }, + /* Acquired */ + { + .ioctl_ops = { + .release_dev = __cam_jpeg_ctx_release_dev_in_acquired, + .config_dev = __cam_jpeg_ctx_config_dev_in_acquired, + .stop_dev = __cam_jpeg_ctx_stop_dev_in_acquired, + .flush_dev = __cam_jpeg_ctx_flush_dev_in_acquired, + .dump_dev = __cam_jpeg_ctx_dump_dev_in_acquired, + }, + .crm_ops = { }, + .irq_ops = __cam_jpeg_ctx_handle_buf_done_in_acquired, + .pagefault_ops = cam_jpeg_context_dump_active_request, + }, +}; + +int cam_jpeg_context_init(struct cam_jpeg_context *ctx, + struct cam_context *ctx_base, + struct cam_hw_mgr_intf *hw_intf, + uint32_t ctx_id) +{ + int rc; + int i; + + if (!ctx || !ctx_base) { + CAM_ERR(CAM_JPEG, "Invalid Context"); + rc = -EFAULT; + goto err; + } + + memset(ctx, 0, sizeof(*ctx)); + + ctx->base = ctx_base; + + for (i = 0; i < CAM_CTX_REQ_MAX; i++) + ctx->req_base[i].req_priv = ctx; + + rc = cam_context_init(ctx_base, jpeg_dev_name, CAM_JPEG, ctx_id, + NULL, hw_intf, ctx->req_base, CAM_CTX_REQ_MAX); + if (rc) { + CAM_ERR(CAM_JPEG, "Camera Context Base init failed"); + goto err; + } + + ctx_base->state_machine = cam_jpeg_ctx_state_machine; + ctx_base->ctx_priv = ctx; + +err: + return rc; +} + +int cam_jpeg_context_deinit(struct cam_jpeg_context *ctx) +{ + if (!ctx || !ctx->base) { + CAM_ERR(CAM_JPEG, "Invalid params: %pK", ctx); + return -EINVAL; + } + + cam_context_deinit(ctx->base); + + memset(ctx, 0, sizeof(*ctx)); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_jpeg/cam_jpeg_context.h b/techpack/camera-bengal/drivers/cam_jpeg/cam_jpeg_context.h new file mode 100644 index 0000000000000000000000000000000000000000..3a11865a605139b204e42a09c7e188eacbac1b10 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/cam_jpeg_context.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_JPEG_CONTEXT_H_ +#define _CAM_JPEG_CONTEXT_H_ + +#include + +#include "cam_context.h" +#include "cam_jpeg_hw_mgr_intf.h" + +#define CAM_JPEG_HW_EVENT_MAX 20 + +/** + * struct cam_jpeg_context - Jpeg context + * @base: Base jpeg cam context object + * @req_base: Common request structure + */ +struct cam_jpeg_context { + struct cam_context *base; + struct cam_ctx_request req_base[CAM_CTX_REQ_MAX]; +}; + +/* cam jpeg context irq handling function type */ +typedef int (*cam_jpeg_hw_event_cb_func)( + struct cam_jpeg_context *ctx_jpeg, + void *evt_data); + +/** + * struct cam_jpeg_ctx_irq_ops - Function table for handling IRQ callbacks + * + * @irq_ops: Array of handle function pointers. + * + */ +struct cam_jpeg_ctx_irq_ops { + cam_jpeg_hw_event_cb_func irq_ops[CAM_JPEG_HW_EVENT_MAX]; +}; + +/** + * cam_jpeg_context_init() + * + * @brief: Initialization function for the JPEG context + * + * @ctx: JPEG context obj to be initialized + * @ctx_base: Context base from cam_context + * @hw_intf: JPEG hw manager interface + * @ctx_id: ID for this context + * + */ +int cam_jpeg_context_init(struct cam_jpeg_context *ctx, + struct cam_context *ctx_base, + struct cam_hw_mgr_intf *hw_intf, + uint32_t ctx_id); + +/** + * cam_jpeg_context_deinit() + * + * @brief: Deinitialize function for the JPEG context + * + * @ctx: JPEG context obj to be deinitialized + * + */ +int cam_jpeg_context_deinit(struct cam_jpeg_context *ctx); + +#endif /* __CAM_JPEG_CONTEXT_H__ */ diff --git a/techpack/camera-bengal/drivers/cam_jpeg/cam_jpeg_dev.c b/techpack/camera-bengal/drivers/cam_jpeg/cam_jpeg_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..b123ebe8059a94d5a948fd76bd2b1afb62696bd0 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/cam_jpeg_dev.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "cam_node.h" +#include "cam_hw_mgr_intf.h" +#include "cam_jpeg_hw_mgr_intf.h" +#include "cam_jpeg_dev.h" +#include "cam_debug_util.h" +#include "cam_smmu_api.h" + +#define CAM_JPEG_DEV_NAME "cam-jpeg" + +static struct cam_jpeg_dev g_jpeg_dev; + +static void cam_jpeg_dev_iommu_fault_handler( + struct iommu_domain *domain, struct device *dev, unsigned long iova, + int flags, void *token, uint32_t buf_info) +{ + int i = 0; + struct cam_node *node = NULL; + + if (!token) { + CAM_ERR(CAM_JPEG, "invalid token in page handler cb"); + return; + } + + node = (struct cam_node *)token; + + for (i = 0; i < node->ctx_size; i++) + cam_context_dump_pf_info(&(node->ctx_list[i]), iova, + buf_info); +} + +static const struct of_device_id cam_jpeg_dt_match[] = { + { + .compatible = "qcom,cam-jpeg" + }, + { } +}; + +static int cam_jpeg_subdev_open(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); + + mutex_lock(&g_jpeg_dev.jpeg_mutex); + g_jpeg_dev.open_cnt++; + mutex_unlock(&g_jpeg_dev.jpeg_mutex); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); + + return 0; +} + +static int cam_jpeg_subdev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + int rc = 0; + struct cam_node *node = v4l2_get_subdevdata(sd); + + + mutex_lock(&g_jpeg_dev.jpeg_mutex); + if (g_jpeg_dev.open_cnt <= 0) { + CAM_DBG(CAM_JPEG, "JPEG subdev is already closed"); + rc = -EINVAL; + goto end; + } + + g_jpeg_dev.open_cnt--; + + if (!node) { + CAM_ERR(CAM_JPEG, "Node ptr is NULL"); + rc = -EINVAL; + goto end; + } + + if (g_jpeg_dev.open_cnt == 0) + cam_node_shutdown(node); + +end: + mutex_unlock(&g_jpeg_dev.jpeg_mutex); + return rc; +} + +static const struct v4l2_subdev_internal_ops cam_jpeg_subdev_internal_ops = { + .close = cam_jpeg_subdev_close, + .open = cam_jpeg_subdev_open, +}; + +static int cam_jpeg_dev_remove(struct platform_device *pdev) +{ + int rc; + int i; + + for (i = 0; i < CAM_JPEG_CTX_MAX; i++) { + rc = cam_jpeg_context_deinit(&g_jpeg_dev.ctx_jpeg[i]); + if (rc) + CAM_ERR(CAM_JPEG, "JPEG context %d deinit failed %d", + i, rc); + } + + rc = cam_subdev_remove(&g_jpeg_dev.sd); + if (rc) + CAM_ERR(CAM_JPEG, "Unregister failed %d", rc); + + return rc; +} + +static int cam_jpeg_dev_probe(struct platform_device *pdev) +{ + int rc; + int i; + struct cam_hw_mgr_intf hw_mgr_intf; + struct cam_node *node; + int iommu_hdl = -1; + + g_jpeg_dev.sd.internal_ops = &cam_jpeg_subdev_internal_ops; + rc = cam_subdev_probe(&g_jpeg_dev.sd, pdev, CAM_JPEG_DEV_NAME, + CAM_JPEG_DEVICE_TYPE); + if (rc) { + CAM_ERR(CAM_JPEG, "JPEG cam_subdev_probe failed %d", rc); + goto err; + } + node = (struct cam_node *)g_jpeg_dev.sd.token; + + rc = cam_jpeg_hw_mgr_init(pdev->dev.of_node, + (uint64_t *)&hw_mgr_intf, &iommu_hdl); + if (rc) { + CAM_ERR(CAM_JPEG, "Can not initialize JPEG HWmanager %d", rc); + goto unregister; + } + + for (i = 0; i < CAM_JPEG_CTX_MAX; i++) { + rc = cam_jpeg_context_init(&g_jpeg_dev.ctx_jpeg[i], + &g_jpeg_dev.ctx[i], + &node->hw_mgr_intf, + i); + if (rc) { + CAM_ERR(CAM_JPEG, "JPEG context init failed %d %d", + i, rc); + goto ctx_init_fail; + } + } + + rc = cam_node_init(node, &hw_mgr_intf, g_jpeg_dev.ctx, CAM_JPEG_CTX_MAX, + CAM_JPEG_DEV_NAME); + if (rc) { + CAM_ERR(CAM_JPEG, "JPEG node init failed %d", rc); + goto ctx_init_fail; + } + + cam_smmu_set_client_page_fault_handler(iommu_hdl, + cam_jpeg_dev_iommu_fault_handler, node); + + mutex_init(&g_jpeg_dev.jpeg_mutex); + + CAM_INFO(CAM_JPEG, "Camera JPEG probe complete"); + + return rc; + +ctx_init_fail: + for (--i; i >= 0; i--) + if (cam_jpeg_context_deinit(&g_jpeg_dev.ctx_jpeg[i])) + CAM_ERR(CAM_JPEG, "deinit fail %d %d", i, rc); +unregister: + if (cam_subdev_remove(&g_jpeg_dev.sd)) + CAM_ERR(CAM_JPEG, "remove fail %d", rc); +err: + return rc; +} + +static struct platform_driver jpeg_driver = { + .probe = cam_jpeg_dev_probe, + .remove = cam_jpeg_dev_remove, + .driver = { + .name = "cam_jpeg", + .owner = THIS_MODULE, + .of_match_table = cam_jpeg_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_jpeg_dev_init_module(void) +{ + return platform_driver_register(&jpeg_driver); +} + +static void __exit cam_jpeg_dev_exit_module(void) +{ + platform_driver_unregister(&jpeg_driver); +} + +module_init(cam_jpeg_dev_init_module); +module_exit(cam_jpeg_dev_exit_module); +MODULE_DESCRIPTION("MSM JPEG driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_jpeg/cam_jpeg_dev.h b/techpack/camera-bengal/drivers/cam_jpeg/cam_jpeg_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..d07a1f94b4258978baea902d405d219b3811d1b2 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/cam_jpeg_dev.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_JPEG_DEV_H_ +#define _CAM_JPEG_DEV_H_ + +#include "cam_subdev.h" +#include "cam_hw_mgr_intf.h" +#include "cam_context.h" +#include "cam_jpeg_context.h" + +/** + * struct cam_jpeg_dev - Camera JPEG V4l2 device node + * + * @sd: Commone camera subdevice node + * @node: Pointer to jpeg subdevice + * @ctx: JPEG base context storage + * @ctx_jpeg: JPEG private context storage + * @jpeg_mutex: Jpeg dev mutex + * @open_cnt: Open device count + */ +struct cam_jpeg_dev { + struct cam_subdev sd; + struct cam_node *node; + struct cam_context ctx[CAM_JPEG_CTX_MAX]; + struct cam_jpeg_context ctx_jpeg[CAM_JPEG_CTX_MAX]; + struct mutex jpeg_mutex; + int32_t open_cnt; +}; +#endif /* __CAM_JPEG_DEV_H__ */ diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/Makefile b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..123ca5dfb18ac1160d50bef55377c1b13d8d3e6f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include/ + +obj-$(CONFIG_SPECTRA_CAMERA) += jpeg_enc_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += jpeg_dma_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_jpeg_hw_mgr.o diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c new file mode 100644 index 0000000000000000000000000000000000000000..f5995e9cdefb9daf1310f290051cdc095a53283b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -0,0 +1,1771 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cam_packet_util.h" +#include "cam_hw.h" +#include "cam_hw_mgr_intf.h" +#include "cam_jpeg_hw_mgr_intf.h" +#include "cam_jpeg_hw_mgr.h" +#include "cam_smmu_api.h" +#include "cam_mem_mgr.h" +#include "cam_req_mgr_workq.h" +#include "cam_mem_mgr.h" +#include "cam_cdm_intf_api.h" +#include "cam_debug_util.h" +#include "cam_common_util.h" + +#define CAM_JPEG_HW_ENTRIES_MAX 20 +#define CAM_JPEG_CHBASE 0 +#define CAM_JPEG_CFG 1 +#define CAM_JPEG_PARAM 2 + +static struct cam_jpeg_hw_mgr g_jpeg_hw_mgr; + +static int32_t cam_jpeg_hw_mgr_cb(uint32_t irq_status, + int32_t result_size, void *data); +static int cam_jpeg_mgr_process_cmd(void *priv, void *data); + +static int cam_jpeg_mgr_process_irq(void *priv, void *data) +{ + int rc = 0; + int mem_hdl = 0; + struct cam_jpeg_process_irq_work_data_t *task_data; + struct cam_jpeg_hw_mgr *hw_mgr; + int32_t i; + struct cam_jpeg_hw_ctx_data *ctx_data = NULL; + struct cam_hw_done_event_data buf_data; + struct cam_jpeg_set_irq_cb irq_cb; + uintptr_t dev_type = 0; + uintptr_t kaddr; + uint32_t *cmd_buf_kaddr; + size_t cmd_buf_len; + struct cam_jpeg_config_inout_param_info *p_params; + struct cam_jpeg_hw_cfg_req *p_cfg_req = NULL; + struct crm_workq_task *task; + struct cam_jpeg_process_frame_work_data_t *wq_task_data; + + if (!data || !priv) { + CAM_ERR(CAM_JPEG, "Invalid data"); + return -EINVAL; + } + + task_data = data; + hw_mgr = &g_jpeg_hw_mgr; + + ctx_data = (struct cam_jpeg_hw_ctx_data *)task_data->data; + if (!ctx_data->in_use) { + CAM_ERR(CAM_JPEG, "ctx is not in use"); + return -EINVAL; + } + + dev_type = ctx_data->jpeg_dev_acquire_info.dev_type; + + mutex_lock(&g_jpeg_hw_mgr.hw_mgr_mutex); + + p_cfg_req = hw_mgr->dev_hw_cfg_args[dev_type][0]; + + if (hw_mgr->device_in_use[dev_type][0] == false || + p_cfg_req == NULL) { + CAM_ERR(CAM_JPEG, "irq for old request %d", rc); + mutex_unlock(&g_jpeg_hw_mgr.hw_mgr_mutex); + return -EINVAL; + } + + irq_cb.jpeg_hw_mgr_cb = cam_jpeg_hw_mgr_cb; + irq_cb.data = NULL; + irq_cb.b_set_cb = false; + if (!hw_mgr->devices[dev_type][0]->hw_ops.process_cmd) { + CAM_ERR(CAM_JPEG, "process_cmd null "); + mutex_unlock(&g_jpeg_hw_mgr.hw_mgr_mutex); + return -EINVAL; + } + rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd( + hw_mgr->devices[dev_type][0]->hw_priv, + CAM_JPEG_CMD_SET_IRQ_CB, + &irq_cb, sizeof(irq_cb)); + if (rc) { + CAM_ERR(CAM_JPEG, "CMD_SET_IRQ_CB failed %d", rc); + mutex_unlock(&g_jpeg_hw_mgr.hw_mgr_mutex); + return rc; + } + + if (hw_mgr->devices[dev_type][0]->hw_ops.deinit) { + rc = hw_mgr->devices[dev_type][0]->hw_ops.deinit( + hw_mgr->devices[dev_type][0]->hw_priv, NULL, 0); + if (rc) + CAM_ERR(CAM_JPEG, "Failed to Deinit %lu HW", dev_type); + } + + hw_mgr->device_in_use[dev_type][0] = false; + hw_mgr->dev_hw_cfg_args[dev_type][0] = NULL; + mutex_unlock(&g_jpeg_hw_mgr.hw_mgr_mutex); + + task = cam_req_mgr_workq_get_task( + g_jpeg_hw_mgr.work_process_frame); + if (!task) { + CAM_ERR(CAM_JPEG, "no empty task"); + return -EINVAL; + } + + wq_task_data = (struct cam_jpeg_process_frame_work_data_t *) + task->payload; + if (!task_data) { + CAM_ERR(CAM_JPEG, "task_data is NULL"); + return -EINVAL; + } + wq_task_data->data = (void *)dev_type; + wq_task_data->request_id = 0; + wq_task_data->type = CAM_JPEG_WORKQ_TASK_CMD_TYPE; + task->process_cb = cam_jpeg_mgr_process_cmd; + rc = cam_req_mgr_workq_enqueue_task(task, &g_jpeg_hw_mgr, + CRM_TASK_PRIORITY_0); + if (rc) { + CAM_ERR(CAM_JPEG, "could not enque task %d", rc); + return rc; + } + + mem_hdl = + p_cfg_req->hw_cfg_args.hw_update_entries[CAM_JPEG_PARAM].handle; + rc = cam_mem_get_cpu_buf(mem_hdl, &kaddr, &cmd_buf_len); + if (rc) { + CAM_ERR(CAM_JPEG, "unable to get info for cmd buf: %x %d", + hw_mgr->iommu_hdl, rc); + return rc; + } + + cmd_buf_kaddr = (uint32_t *)kaddr; + + if ((p_cfg_req->hw_cfg_args.hw_update_entries[CAM_JPEG_PARAM].offset / + sizeof(uint32_t)) >= cmd_buf_len) { + CAM_ERR(CAM_JPEG, "Invalid offset: %u cmd buf len: %zu", + p_cfg_req->hw_cfg_args.hw_update_entries[ + CAM_JPEG_PARAM].offset, cmd_buf_len); + cam_mem_put_cpu_buf(mem_hdl); + return -EINVAL; + } + + cmd_buf_kaddr = + (cmd_buf_kaddr + + (p_cfg_req->hw_cfg_args.hw_update_entries[CAM_JPEG_PARAM].offset + / sizeof(uint32_t))); + + p_params = (struct cam_jpeg_config_inout_param_info *)cmd_buf_kaddr; + + p_params->output_size = task_data->result_size; + CAM_DBG(CAM_JPEG, "Encoded Size %d", task_data->result_size); + + buf_data.num_handles = + p_cfg_req->hw_cfg_args.num_out_map_entries; + for (i = 0; i < buf_data.num_handles; i++) { + buf_data.resource_handle[i] = + p_cfg_req->hw_cfg_args.out_map_entries[i].resource_handle; + } + buf_data.request_id = + PTR_TO_U64(p_cfg_req->hw_cfg_args.priv); + ctx_data->ctxt_event_cb(ctx_data->context_priv, 0, &buf_data); + + mutex_lock(&g_jpeg_hw_mgr.hw_mgr_mutex); + list_add_tail(&p_cfg_req->list, &hw_mgr->free_req_list); + mutex_unlock(&g_jpeg_hw_mgr.hw_mgr_mutex); + cam_mem_put_cpu_buf(mem_hdl); + return rc; +} + +static int cam_jpeg_hw_mgr_cb( + uint32_t irq_status, int32_t result_size, void *data) +{ + int32_t rc; + unsigned long flags; + struct cam_jpeg_hw_mgr *hw_mgr = &g_jpeg_hw_mgr; + struct crm_workq_task *task; + struct cam_jpeg_process_irq_work_data_t *task_data; + + spin_lock_irqsave(&hw_mgr->hw_mgr_lock, flags); + task = cam_req_mgr_workq_get_task( + g_jpeg_hw_mgr.work_process_irq_cb); + if (!task) { + CAM_ERR(CAM_JPEG, "no empty task"); + spin_unlock_irqrestore(&hw_mgr->hw_mgr_lock, flags); + return -ENOMEM; + } + + task_data = (struct cam_jpeg_process_irq_work_data_t *)task->payload; + task_data->data = data; + task_data->irq_status = irq_status; + task_data->result_size = result_size; + task_data->type = CAM_JPEG_WORKQ_TASK_MSG_TYPE; + task->process_cb = cam_jpeg_mgr_process_irq; + + rc = cam_req_mgr_workq_enqueue_task(task, &g_jpeg_hw_mgr, + CRM_TASK_PRIORITY_0); + spin_unlock_irqrestore(&hw_mgr->hw_mgr_lock, flags); + + return rc; +} + +static int cam_jpeg_mgr_get_free_ctx(struct cam_jpeg_hw_mgr *hw_mgr) +{ + int i = 0; + int num_ctx = CAM_JPEG_CTX_MAX; + + for (i = 0; i < num_ctx; i++) { + mutex_lock(&hw_mgr->ctx_data[i].ctx_mutex); + if (hw_mgr->ctx_data[i].in_use == false) { + hw_mgr->ctx_data[i].in_use = true; + mutex_unlock(&hw_mgr->ctx_data[i].ctx_mutex); + break; + } + mutex_unlock(&hw_mgr->ctx_data[i].ctx_mutex); + } + + return i; +} + + +static int cam_jpeg_mgr_release_ctx( + struct cam_jpeg_hw_mgr *hw_mgr, struct cam_jpeg_hw_ctx_data *ctx_data) +{ + if (!ctx_data) { + CAM_ERR(CAM_JPEG, "invalid ctx_data %pK", ctx_data); + return -EINVAL; + } + + mutex_lock(&ctx_data->ctx_mutex); + if (!ctx_data->in_use) { + CAM_ERR(CAM_JPEG, "ctx is already un-used: %pK", ctx_data); + mutex_unlock(&ctx_data->ctx_mutex); + return -EINVAL; + } + + ctx_data->in_use = false; + mutex_unlock(&ctx_data->ctx_mutex); + + return 0; +} + +static int cam_jpeg_insert_cdm_change_base( + struct cam_hw_config_args *config_args, + struct cam_jpeg_hw_ctx_data *ctx_data, + struct cam_jpeg_hw_mgr *hw_mgr) +{ + int rc = 0; + uint32_t dev_type; + struct cam_cdm_bl_request *cdm_cmd; + uint32_t size; + uint32_t mem_cam_base; + uintptr_t iova_addr; + uint32_t *ch_base_iova_addr; + size_t ch_base_len; + + rc = cam_mem_get_cpu_buf( + config_args->hw_update_entries[CAM_JPEG_CHBASE].handle, + &iova_addr, &ch_base_len); + if (rc) { + CAM_ERR(CAM_JPEG, + "unable to get src buf info for cmd buf: %d", rc); + return rc; + } + + if (config_args->hw_update_entries[CAM_JPEG_CHBASE].offset >= + ch_base_len) { + CAM_ERR(CAM_JPEG, "Not enough buf offset %d len %d", + config_args->hw_update_entries[CAM_JPEG_CHBASE].offset, + ch_base_len); + cam_mem_put_cpu_buf( + config_args->hw_update_entries[CAM_JPEG_CHBASE].handle); + return -EINVAL; + } + CAM_DBG(CAM_JPEG, "iova %pK len %zu offset %d", + (void *)iova_addr, ch_base_len, + config_args->hw_update_entries[CAM_JPEG_CHBASE].offset); + ch_base_iova_addr = (uint32_t *)iova_addr; + ch_base_iova_addr = (ch_base_iova_addr + + (config_args->hw_update_entries[CAM_JPEG_CHBASE].offset / + sizeof(uint32_t))); + + dev_type = ctx_data->jpeg_dev_acquire_info.dev_type; + mem_cam_base = hw_mgr->cdm_reg_map[dev_type][0]->mem_cam_base; + size = + hw_mgr->cdm_info[dev_type][0].cdm_ops->cdm_required_size_changebase(); + hw_mgr->cdm_info[dev_type][0].cdm_ops->cdm_write_changebase( + ch_base_iova_addr, mem_cam_base); + + cdm_cmd = ctx_data->cdm_cmd; + cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].bl_addr.mem_handle = + config_args->hw_update_entries[CAM_JPEG_CHBASE].handle; + cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].offset = + config_args->hw_update_entries[CAM_JPEG_CHBASE].offset; + cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].len = size * sizeof(uint32_t); + cdm_cmd->cmd_arrary_count++; + cdm_cmd->gen_irq_arb = false; + + ch_base_iova_addr += size; + *ch_base_iova_addr = 0; + ch_base_iova_addr += size; + *ch_base_iova_addr = 0; + + cam_mem_put_cpu_buf( + config_args->hw_update_entries[CAM_JPEG_CHBASE].handle); + + return rc; +} + +static int cam_jpeg_mgr_process_cmd(void *priv, void *data) +{ + int rc; + int i = 0; + struct cam_jpeg_hw_mgr *hw_mgr = priv; + struct cam_hw_update_entry *cmd; + struct cam_cdm_bl_request *cdm_cmd; + struct cam_hw_config_args *config_args = NULL; + struct cam_jpeg_hw_ctx_data *ctx_data = NULL; + uintptr_t request_id = 0; + struct cam_jpeg_process_frame_work_data_t *task_data = + (struct cam_jpeg_process_frame_work_data_t *)data; + uint32_t dev_type; + struct cam_jpeg_set_irq_cb irq_cb; + struct cam_jpeg_hw_cfg_req *p_cfg_req = NULL; + struct cam_hw_done_event_data buf_data; + struct cam_hw_config_args *hw_cfg_args = NULL; + + if (!hw_mgr || !task_data) { + CAM_ERR(CAM_JPEG, "Invalid arguments %pK %pK", + hw_mgr, task_data); + return -EINVAL; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + + if (list_empty(&hw_mgr->hw_config_req_list)) { + CAM_DBG(CAM_JPEG, "no available request"); + rc = -EFAULT; + goto end; + } + + p_cfg_req = list_first_entry(&hw_mgr->hw_config_req_list, + struct cam_jpeg_hw_cfg_req, list); + if (!p_cfg_req) { + CAM_ERR(CAM_JPEG, "no request"); + rc = -EFAULT; + goto end; + } + + if (false == hw_mgr->device_in_use[p_cfg_req->dev_type][0]) { + hw_mgr->device_in_use[p_cfg_req->dev_type][0] = true; + hw_mgr->dev_hw_cfg_args[p_cfg_req->dev_type][0] = p_cfg_req; + list_del_init(&p_cfg_req->list); + } else { + CAM_DBG(CAM_JPEG, "Not dequeing, just return"); + rc = -EFAULT; + goto end; + } + + config_args = (struct cam_hw_config_args *)&p_cfg_req->hw_cfg_args; + request_id = task_data->request_id; + if (request_id != (uintptr_t)config_args->priv) { + CAM_DBG(CAM_JPEG, "not a recent req %zd %zd", + request_id, (uintptr_t)config_args->priv); + } + + if (!config_args->num_hw_update_entries) { + CAM_ERR(CAM_JPEG, "No hw update enteries are available"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + rc = -EINVAL; + goto end_unusedev; + } + + ctx_data = (struct cam_jpeg_hw_ctx_data *)config_args->ctxt_to_hw_map; + if (!ctx_data->in_use) { + CAM_ERR(CAM_JPEG, "ctx is not in use"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + rc = -EINVAL; + goto end_unusedev; + } + + dev_type = ctx_data->jpeg_dev_acquire_info.dev_type; + + if (dev_type != p_cfg_req->dev_type) + CAM_WARN(CAM_JPEG, "dev types not same something wrong"); + + if (!hw_mgr->devices[dev_type][0]->hw_ops.init) { + CAM_ERR(CAM_JPEG, "hw op init null "); + rc = -EFAULT; + goto end; + } + rc = hw_mgr->devices[dev_type][0]->hw_ops.init( + hw_mgr->devices[dev_type][0]->hw_priv, + ctx_data, + sizeof(ctx_data)); + if (rc) { + CAM_ERR(CAM_JPEG, "Failed to Init %d HW", dev_type); + goto end; + } + + irq_cb.jpeg_hw_mgr_cb = cam_jpeg_hw_mgr_cb; + irq_cb.data = (void *)ctx_data; + irq_cb.b_set_cb = true; + if (!hw_mgr->devices[dev_type][0]->hw_ops.process_cmd) { + CAM_ERR(CAM_JPEG, "op process_cmd null "); + rc = -EFAULT; + goto end_callcb; + } + rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd( + hw_mgr->devices[dev_type][0]->hw_priv, + CAM_JPEG_CMD_SET_IRQ_CB, + &irq_cb, sizeof(irq_cb)); + if (rc) { + CAM_ERR(CAM_JPEG, "SET_IRQ_CB failed %d", rc); + goto end_callcb; + } + + if (!hw_mgr->devices[dev_type][0]->hw_ops.reset) { + CAM_ERR(CAM_JPEG, "op reset null "); + rc = -EFAULT; + goto end_callcb; + } + rc = hw_mgr->devices[dev_type][0]->hw_ops.reset( + hw_mgr->devices[dev_type][0]->hw_priv, + NULL, 0); + if (rc) { + CAM_ERR(CAM_JPEG, "jpeg hw reset failed %d", rc); + goto end_callcb; + } + + cdm_cmd = ctx_data->cdm_cmd; + cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE; + cdm_cmd->flag = false; + cdm_cmd->userdata = NULL; + cdm_cmd->cookie = 0; + cdm_cmd->cmd_arrary_count = 0; + cdm_cmd->gen_irq_arb = false; + + rc = cam_jpeg_insert_cdm_change_base(config_args, + ctx_data, hw_mgr); + if (rc) { + CAM_ERR(CAM_JPEG, "insert change base failed %d", rc); + goto end_callcb; + } + + CAM_DBG(CAM_JPEG, "num hw up %d", config_args->num_hw_update_entries); + for (i = CAM_JPEG_CFG; i < (config_args->num_hw_update_entries - 1); + i++) { + cmd = (config_args->hw_update_entries + i); + cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].bl_addr.mem_handle + = cmd->handle; + cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].offset = + cmd->offset; + cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].len = + cmd->len; + cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].arbitrate = + false; + CAM_DBG(CAM_JPEG, "i %d entry h %d o %d l %d", + i, cmd->handle, cmd->offset, cmd->len); + cdm_cmd->cmd_arrary_count++; + } + + rc = cam_cdm_submit_bls( + hw_mgr->cdm_info[dev_type][0].cdm_handle, cdm_cmd); + if (rc) { + CAM_ERR(CAM_JPEG, "Failed to apply the configs %d", rc); + goto end_callcb; + } + + if (!hw_mgr->devices[dev_type][0]->hw_ops.start) { + CAM_ERR(CAM_JPEG, "op start null "); + rc = -EINVAL; + goto end_callcb; + } + rc = hw_mgr->devices[dev_type][0]->hw_ops.start( + hw_mgr->devices[dev_type][0]->hw_priv, + NULL, 0); + if (rc) { + CAM_ERR(CAM_JPEG, "Failed to start hw %d", + rc); + goto end_callcb; + } + p_cfg_req->submit_timestamp = ktime_get(); + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; + +end_callcb: + mutex_unlock(&hw_mgr->hw_mgr_mutex); + if (p_cfg_req) { + hw_cfg_args = &p_cfg_req->hw_cfg_args; + buf_data.num_handles = + hw_cfg_args->num_out_map_entries; + for (i = 0; i < buf_data.num_handles; i++) { + buf_data.resource_handle[i] = + hw_cfg_args->out_map_entries[i].resource_handle; + } + buf_data.request_id = + (uintptr_t)p_cfg_req->hw_cfg_args.priv; + ctx_data->ctxt_event_cb(ctx_data->context_priv, 0, &buf_data); + } +end_unusedev: + mutex_lock(&hw_mgr->hw_mgr_mutex); + hw_mgr->device_in_use[p_cfg_req->dev_type][0] = false; + hw_mgr->dev_hw_cfg_args[p_cfg_req->dev_type][0] = NULL; + +end: + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static int cam_jpeg_mgr_config_hw(void *hw_mgr_priv, void *config_hw_args) +{ + int rc; + struct cam_jpeg_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_config_args *config_args = config_hw_args; + struct cam_jpeg_hw_ctx_data *ctx_data = NULL; + uintptr_t request_id = 0; + struct cam_hw_update_entry *hw_update_entries; + struct crm_workq_task *task; + struct cam_jpeg_process_frame_work_data_t *task_data; + struct cam_jpeg_hw_cfg_req *p_cfg_req = NULL; + + if (!hw_mgr || !config_args) { + CAM_ERR(CAM_JPEG, "Invalid arguments %pK %pK", + hw_mgr, config_args); + return -EINVAL; + } + + if (!config_args->num_hw_update_entries) { + CAM_ERR(CAM_JPEG, "No hw update enteries are available"); + return -EINVAL; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + + ctx_data = (struct cam_jpeg_hw_ctx_data *)config_args->ctxt_to_hw_map; + if (!ctx_data->in_use) { + CAM_ERR(CAM_JPEG, "ctx is not in use"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EINVAL; + } + + if (list_empty(&hw_mgr->free_req_list)) { + mutex_unlock(&hw_mgr->hw_mgr_mutex); + CAM_ERR(CAM_JPEG, "list empty"); + return -ENOMEM; + } + + p_cfg_req = list_first_entry(&hw_mgr->free_req_list, + struct cam_jpeg_hw_cfg_req, list); + list_del_init(&p_cfg_req->list); + + /* Update Currently Processing Config Request */ + p_cfg_req->hw_cfg_args = *config_args; + p_cfg_req->dev_type = ctx_data->jpeg_dev_acquire_info.dev_type; + + request_id = (uintptr_t)config_args->priv; + p_cfg_req->req_id = request_id; + hw_update_entries = config_args->hw_update_entries; + CAM_DBG(CAM_JPEG, "ctx_data = %pK req_id = %lld %zd", + ctx_data, request_id, (uintptr_t)config_args->priv); + task = cam_req_mgr_workq_get_task(g_jpeg_hw_mgr.work_process_frame); + if (!task) { + CAM_ERR(CAM_JPEG, "no empty task"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + rc = -ENOMEM; + goto err_after_dq_free_list; + } + + + task_data = (struct cam_jpeg_process_frame_work_data_t *) + task->payload; + if (!task_data) { + CAM_ERR(CAM_JPEG, "task_data is NULL"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + rc = -EINVAL; + goto err_after_dq_free_list; + } + CAM_DBG(CAM_JPEG, "cfge %pK num %d", + p_cfg_req->hw_cfg_args.hw_update_entries, + p_cfg_req->hw_cfg_args.num_hw_update_entries); + + list_add_tail(&p_cfg_req->list, &hw_mgr->hw_config_req_list); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + task_data->data = (void *)(uintptr_t)p_cfg_req->dev_type; + task_data->request_id = request_id; + task_data->type = CAM_JPEG_WORKQ_TASK_CMD_TYPE; + task->process_cb = cam_jpeg_mgr_process_cmd; + + rc = cam_req_mgr_workq_enqueue_task(task, &g_jpeg_hw_mgr, + CRM_TASK_PRIORITY_0); + if (rc) { + CAM_ERR(CAM_JPEG, "failed to enqueue task %d", rc); + goto err_after_get_task; + } + + return rc; + +err_after_get_task: + list_del_init(&p_cfg_req->list); +err_after_dq_free_list: + list_add_tail(&p_cfg_req->list, &hw_mgr->free_req_list); + + return rc; +} + +static void cam_jpeg_mgr_print_io_bufs(struct cam_packet *packet, + int32_t iommu_hdl, int32_t sec_mmu_hdl, uint32_t pf_buf_info, + bool *mem_found) +{ + dma_addr_t iova_addr; + size_t src_buf_size; + int i; + int j; + int rc = 0; + int32_t mmu_hdl; + struct cam_buf_io_cfg *io_cfg = NULL; + + if (mem_found) + *mem_found = false; + + io_cfg = (struct cam_buf_io_cfg *)((uint32_t *)&packet->payload + + packet->io_configs_offset / 4); + + for (i = 0; i < packet->num_io_configs; i++) { + for (j = 0; j < CAM_PACKET_MAX_PLANES; j++) { + if (!io_cfg[i].mem_handle[j]) + break; + + if (GET_FD_FROM_HANDLE(io_cfg[i].mem_handle[j]) == + GET_FD_FROM_HANDLE(pf_buf_info)) { + CAM_INFO(CAM_JPEG, + "Found PF at port: %d mem %x fd: %x", + io_cfg[i].resource_type, + io_cfg[i].mem_handle[j], + pf_buf_info); + if (mem_found) + *mem_found = true; + } + + CAM_INFO(CAM_JPEG, "port: %d f: %u format: %d dir %d", + io_cfg[i].resource_type, + io_cfg[i].fence, + io_cfg[i].format, + io_cfg[i].direction); + + mmu_hdl = cam_mem_is_secure_buf( + io_cfg[i].mem_handle[j]) ? sec_mmu_hdl : + iommu_hdl; + rc = cam_mem_get_io_buf(io_cfg[i].mem_handle[j], + mmu_hdl, &iova_addr, &src_buf_size); + if (rc < 0) { + CAM_ERR(CAM_UTIL, "get src buf address fail"); + continue; + } + if ((iova_addr & 0xFFFFFFFF) != iova_addr) { + CAM_ERR(CAM_JPEG, "Invalid mapped address"); + rc = -EINVAL; + continue; + } + + CAM_INFO(CAM_JPEG, + "pln %u w %u h %u stride %u slice %u size %d addr 0x%x offset 0x%x memh %x", + j, io_cfg[i].planes[j].width, + io_cfg[i].planes[j].height, + io_cfg[i].planes[j].plane_stride, + io_cfg[i].planes[j].slice_height, + (int32_t)src_buf_size, + (unsigned int)iova_addr, + io_cfg[i].offsets[j], + io_cfg[i].mem_handle[j]); + } + } +} + +static int cam_jpeg_mgr_prepare_hw_update(void *hw_mgr_priv, + void *prepare_hw_update_args) +{ + int rc, i, j, k; + struct cam_hw_prepare_update_args *prepare_args = + prepare_hw_update_args; + struct cam_jpeg_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_jpeg_hw_ctx_data *ctx_data = NULL; + struct cam_packet *packet = NULL; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct cam_buf_io_cfg *io_cfg_ptr = NULL; + struct cam_kmd_buf_info kmd_buf; + + if (!prepare_args || !hw_mgr) { + CAM_ERR(CAM_JPEG, "Invalid args %pK %pK", + prepare_args, hw_mgr); + return -EINVAL; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + ctx_data = (struct cam_jpeg_hw_ctx_data *)prepare_args->ctxt_to_hw_map; + if (!ctx_data->in_use) { + CAM_ERR(CAM_JPEG, "ctx is not in use"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EINVAL; + } + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + packet = prepare_args->packet; + if (!packet) { + CAM_ERR(CAM_JPEG, "received packet is NULL"); + return -EINVAL; + } + + if (((packet->header.op_code & 0xff) != CAM_JPEG_OPCODE_ENC_UPDATE) && + ((packet->header.op_code + & 0xff) != CAM_JPEG_OPCODE_DMA_UPDATE)) { + CAM_ERR(CAM_JPEG, "Invalid Opcode in pkt: %d", + packet->header.op_code & 0xff); + return -EINVAL; + } + + rc = cam_packet_util_validate_packet(packet, prepare_args->remain_len); + if (rc) { + CAM_ERR(CAM_JPEG, "invalid packet %d", rc); + return rc; + } + + if ((packet->num_cmd_buf > 5) || !packet->num_patches || + !packet->num_io_configs || + (packet->num_io_configs > CAM_JPEG_IMAGE_MAX)) { + CAM_ERR(CAM_JPEG, + "wrong number of cmd/patch/io_configs info: %u %u %u", + packet->num_cmd_buf, packet->num_patches, + packet->num_io_configs); + return -EINVAL; + } + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *)&packet->payload + + (packet->cmd_buf_offset / 4)); + CAM_DBG(CAM_JPEG, "packet = %pK cmd_desc = %pK size = %lu", + (void *)packet, (void *)cmd_desc, + sizeof(struct cam_cmd_buf_desc)); + + rc = cam_packet_util_process_patches(packet, hw_mgr->iommu_hdl, -1); + if (rc) { + CAM_ERR(CAM_JPEG, "Patch processing failed %d", rc); + return rc; + } + + io_cfg_ptr = (struct cam_buf_io_cfg *)((uint32_t *)&packet->payload + + packet->io_configs_offset / 4); + CAM_DBG(CAM_JPEG, "packet = %pK io_cfg_ptr = %pK size = %lu", + (void *)packet, (void *)io_cfg_ptr, + sizeof(struct cam_buf_io_cfg)); + prepare_args->pf_data->packet = packet; + + prepare_args->num_out_map_entries = 0; + + for (i = 0, j = 0, k = 0; i < packet->num_io_configs; i++) { + if (io_cfg_ptr[i].direction == CAM_BUF_INPUT) { + prepare_args->in_map_entries[j].resource_handle = + io_cfg_ptr[i].resource_type; + prepare_args->in_map_entries[j++].sync_id = + io_cfg_ptr[i].fence; + prepare_args->num_in_map_entries++; + } else { + prepare_args->in_map_entries[k].resource_handle = + io_cfg_ptr[i].resource_type; + prepare_args->out_map_entries[k++].sync_id = + io_cfg_ptr[i].fence; + prepare_args->num_out_map_entries++; + } + CAM_DBG(CAM_JPEG, "dir[%d]: %u, fence: %u", + i, io_cfg_ptr[i].direction, io_cfg_ptr[i].fence); + } + + + j = prepare_args->num_hw_update_entries; + rc = cam_packet_util_get_kmd_buffer(packet, &kmd_buf); + if (rc) { + CAM_ERR(CAM_JPEG, "get kmd buf failed %d", rc); + return rc; + } + /* fill kmd buf info into 1st hw update entry */ + prepare_args->hw_update_entries[j].len = + (uint32_t)kmd_buf.used_bytes; + prepare_args->hw_update_entries[j].handle = + (uint32_t)kmd_buf.handle; + prepare_args->hw_update_entries[j].offset = + (uint32_t)kmd_buf.offset; + j++; + + for (i = 0; i < packet->num_cmd_buf; i++, j++) { + prepare_args->hw_update_entries[j].len = + (uint32_t)cmd_desc[i].length; + prepare_args->hw_update_entries[j].handle = + (uint32_t)cmd_desc[i].mem_handle; + prepare_args->hw_update_entries[j].offset = + (uint32_t)cmd_desc[i].offset; + } + prepare_args->num_hw_update_entries = j; + prepare_args->priv = (void *)(uintptr_t)packet->header.request_id; + + CAM_DBG(CAM_JPEG, "will wait on input sync sync_id %d", + prepare_args->in_map_entries[0].sync_id); + + return rc; +} + +static void cam_jpeg_mgr_stop_deinit_dev(struct cam_jpeg_hw_mgr *hw_mgr, + struct cam_jpeg_hw_cfg_req *p_cfg_req, uint32_t dev_type) +{ + int rc = 0; + struct cam_jpeg_set_irq_cb irq_cb; + + /* stop reset Unregister CB and deinit */ + irq_cb.jpeg_hw_mgr_cb = cam_jpeg_hw_mgr_cb; + irq_cb.data = NULL; + irq_cb.b_set_cb = false; + if (hw_mgr->devices[dev_type][0]->hw_ops.process_cmd) { + rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd( + hw_mgr->devices[dev_type][0]->hw_priv, + CAM_JPEG_CMD_SET_IRQ_CB, + &irq_cb, sizeof(irq_cb)); + if (rc) + CAM_ERR(CAM_JPEG, "SET_IRQ_CB fail %d", rc); + } else { + CAM_ERR(CAM_JPEG, "process_cmd null %d", dev_type); + } + + if (hw_mgr->devices[dev_type][0]->hw_ops.stop) { + rc = hw_mgr->devices[dev_type][0]->hw_ops.stop( + hw_mgr->devices[dev_type][0]->hw_priv, + NULL, 0); + if (rc) + CAM_ERR(CAM_JPEG, "stop fail %d", rc); + } else { + CAM_ERR(CAM_JPEG, "op stop null %d", dev_type); + } + + if (hw_mgr->devices[dev_type][0]->hw_ops.deinit) { + rc = hw_mgr->devices[dev_type][0]->hw_ops.deinit( + hw_mgr->devices[dev_type][0]->hw_priv, + NULL, 0); + if (rc) + CAM_ERR(CAM_JPEG, "Failed to Deinit %d HW %d", + dev_type, rc); + } else { + CAM_ERR(CAM_JPEG, "op deinit null %d", dev_type); + } + + hw_mgr->device_in_use[dev_type][0] = false; + hw_mgr->dev_hw_cfg_args[dev_type][0] = NULL; +} + +static int cam_jpeg_mgr_flush(void *hw_mgr_priv, + struct cam_jpeg_hw_ctx_data *ctx_data) +{ + struct cam_jpeg_hw_mgr *hw_mgr = hw_mgr_priv; + uint32_t dev_type; + struct cam_jpeg_hw_cfg_req *p_cfg_req = NULL; + struct cam_jpeg_hw_cfg_req *cfg_req = NULL, *req_temp = NULL; + + CAM_DBG(CAM_JPEG, "E: JPEG flush ctx"); + + if (!hw_mgr || !ctx_data) { + CAM_ERR(CAM_JPEG, "Invalid args"); + return -EINVAL; + } + + dev_type = ctx_data->jpeg_dev_acquire_info.dev_type; + + p_cfg_req = hw_mgr->dev_hw_cfg_args[dev_type][0]; + if (hw_mgr->device_in_use[dev_type][0] == true && + p_cfg_req != NULL) { + if ((struct cam_jpeg_hw_ctx_data *) + p_cfg_req->hw_cfg_args.ctxt_to_hw_map == ctx_data) { + cam_jpeg_mgr_stop_deinit_dev(hw_mgr, p_cfg_req, + dev_type); + list_del_init(&p_cfg_req->list); + list_add_tail(&p_cfg_req->list, + &hw_mgr->free_req_list); + } + } + + list_for_each_entry_safe(cfg_req, req_temp, + &hw_mgr->hw_config_req_list, list) { + if ((struct cam_jpeg_hw_ctx_data *) + cfg_req->hw_cfg_args.ctxt_to_hw_map != ctx_data) + continue; + + list_del_init(&cfg_req->list); + list_add_tail(&cfg_req->list, &hw_mgr->free_req_list); + } + + CAM_DBG(CAM_JPEG, "X: JPEG flush ctx"); + + return 0; +} + +static int cam_jpeg_mgr_flush_req(void *hw_mgr_priv, + struct cam_jpeg_hw_ctx_data *ctx_data, + struct cam_hw_flush_args *flush_args) +{ + struct cam_jpeg_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_jpeg_hw_cfg_req *cfg_req = NULL; + struct cam_jpeg_hw_cfg_req *req_temp = NULL; + long request_id = 0; + uint32_t dev_type; + struct cam_jpeg_hw_cfg_req *p_cfg_req = NULL; + bool b_req_found = false; + + CAM_DBG(CAM_JPEG, "E: JPEG flush req"); + + if (!hw_mgr || !ctx_data || !flush_args) { + CAM_ERR(CAM_JPEG, "Invalid args"); + return -EINVAL; + } + + if (flush_args->num_req_pending) + return 0; + + request_id = (uintptr_t)flush_args->flush_req_active[0]; + + if (!flush_args->num_req_active) + return 0; + + if (request_id <= 0) { + CAM_ERR(CAM_JPEG, "Invalid red id %ld", request_id); + return -EINVAL; + } + + dev_type = ctx_data->jpeg_dev_acquire_info.dev_type; + + p_cfg_req = hw_mgr->dev_hw_cfg_args[dev_type][0]; + if (hw_mgr->device_in_use[dev_type][0] == true && + p_cfg_req != NULL) { + if (((struct cam_jpeg_hw_ctx_data *) + p_cfg_req->hw_cfg_args.ctxt_to_hw_map == ctx_data) && + (p_cfg_req->req_id == request_id)) { + cam_jpeg_mgr_stop_deinit_dev(hw_mgr, p_cfg_req, + dev_type); + list_del_init(&p_cfg_req->list); + list_add_tail(&p_cfg_req->list, + &hw_mgr->free_req_list); + b_req_found = true; + } + } + + list_for_each_entry_safe(cfg_req, req_temp, + &hw_mgr->hw_config_req_list, list) { + if ((struct cam_jpeg_hw_ctx_data *) + cfg_req->hw_cfg_args.ctxt_to_hw_map != ctx_data) + continue; + + if (cfg_req->req_id != request_id) + continue; + + list_del_init(&cfg_req->list); + list_add_tail(&cfg_req->list, &hw_mgr->free_req_list); + b_req_found = true; + break; + } + + if (!b_req_found) { + CAM_ERR(CAM_JPEG, "req not found %ld", request_id); + return -EINVAL; + } + + CAM_DBG(CAM_JPEG, "X: JPEG flush req"); + return 0; +} + +static int cam_jpeg_mgr_hw_flush(void *hw_mgr_priv, void *flush_hw_args) +{ + int rc = 0; + struct cam_hw_flush_args *flush_args = flush_hw_args; + struct cam_jpeg_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_jpeg_hw_ctx_data *ctx_data = NULL; + + if (!hw_mgr || !flush_args || !flush_args->ctxt_to_hw_map) { + CAM_ERR(CAM_JPEG, "Invalid args"); + return -EINVAL; + } + mutex_lock(&hw_mgr->hw_mgr_mutex); + + ctx_data = (struct cam_jpeg_hw_ctx_data *)flush_args->ctxt_to_hw_map; + if (!ctx_data->in_use) { + CAM_ERR(CAM_JPEG, "ctx is not in use"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EINVAL; + } + + if ((flush_args->flush_type >= CAM_FLUSH_TYPE_MAX) || + (flush_args->flush_type < CAM_FLUSH_TYPE_REQ)) { + CAM_ERR(CAM_JPEG, "Invalid flush type: %d", + flush_args->flush_type); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EINVAL; + } + + switch (flush_args->flush_type) { + case CAM_FLUSH_TYPE_ALL: + rc = cam_jpeg_mgr_flush(hw_mgr_priv, ctx_data); + if ((rc)) + CAM_ERR(CAM_JPEG, "Flush failed %d", rc); + break; + case CAM_FLUSH_TYPE_REQ: + rc = cam_jpeg_mgr_flush_req(hw_mgr_priv, ctx_data, flush_args); + break; + default: + CAM_ERR(CAM_JPEG, "Invalid flush type: %d", + flush_args->flush_type); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EINVAL; + } + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + return rc; +} + +static int cam_jpeg_mgr_hw_stop(void *hw_mgr_priv, void *stop_hw_args) +{ + int rc; + struct cam_hw_stop_args *stop_args = + (struct cam_hw_stop_args *)stop_hw_args; + struct cam_jpeg_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_jpeg_hw_ctx_data *ctx_data = NULL; + + if (!hw_mgr || !stop_args || !stop_args->ctxt_to_hw_map) { + CAM_ERR(CAM_JPEG, "Invalid args"); + return -EINVAL; + } + mutex_lock(&hw_mgr->hw_mgr_mutex); + + ctx_data = (struct cam_jpeg_hw_ctx_data *)stop_args->ctxt_to_hw_map; + if (!ctx_data->in_use) { + CAM_ERR(CAM_JPEG, "ctx is not in use"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EINVAL; + } + + rc = cam_jpeg_mgr_flush(hw_mgr_priv, ctx_data); + if ((rc)) + CAM_ERR(CAM_JPEG, "flush failed %d", rc); + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + return rc; +} + +static int cam_jpeg_mgr_release_hw(void *hw_mgr_priv, void *release_hw_args) +{ + int rc; + struct cam_hw_release_args *release_hw = release_hw_args; + struct cam_jpeg_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_jpeg_hw_ctx_data *ctx_data = NULL; + uint32_t dev_type; + + if (!hw_mgr || !release_hw || !release_hw->ctxt_to_hw_map) { + CAM_ERR(CAM_JPEG, "Invalid args"); + return -EINVAL; + } + + ctx_data = (struct cam_jpeg_hw_ctx_data *)release_hw->ctxt_to_hw_map; + if (!ctx_data->in_use) { + CAM_ERR(CAM_JPEG, "ctx is not in use"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EINVAL; + } + dev_type = ctx_data->jpeg_dev_acquire_info.dev_type; + + mutex_lock(&hw_mgr->hw_mgr_mutex); + if (hw_mgr->cdm_info[dev_type][0].ref_cnt == 0) { + mutex_unlock(&hw_mgr->hw_mgr_mutex); + CAM_ERR(CAM_JPEG, "Error Unbalanced deinit"); + return -EFAULT; + } + + hw_mgr->cdm_info[dev_type][0].ref_cnt--; + if (!(hw_mgr->cdm_info[dev_type][0].ref_cnt)) { + if (cam_cdm_stream_off( + hw_mgr->cdm_info[dev_type][0].cdm_handle)) { + CAM_ERR(CAM_JPEG, "CDM stream off failed %d", + hw_mgr->cdm_info[dev_type][0].cdm_handle); + } + /* release cdm handle */ + cam_cdm_release(hw_mgr->cdm_info[dev_type][0].cdm_handle); + } + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + rc = cam_jpeg_mgr_release_ctx(hw_mgr, ctx_data); + if (rc) { + mutex_unlock(&hw_mgr->hw_mgr_mutex); + CAM_ERR(CAM_JPEG, "JPEG release ctx failed"); + kfree(ctx_data->cdm_cmd); + ctx_data->cdm_cmd = NULL; + + return -EINVAL; + } + + kfree(ctx_data->cdm_cmd); + ctx_data->cdm_cmd = NULL; + CAM_DBG(CAM_JPEG, "handle %llu", ctx_data); + + return rc; +} + +static int cam_jpeg_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) +{ + int rc = 0; + int32_t ctx_id = 0; + struct cam_jpeg_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_jpeg_hw_ctx_data *ctx_data = NULL; + struct cam_hw_acquire_args *args = acquire_hw_args; + struct cam_jpeg_acquire_dev_info jpeg_dev_acquire_info; + struct cam_cdm_acquire_data cdm_acquire; + uint32_t dev_type; + uint32_t size = 0; + + if ((!hw_mgr_priv) || (!acquire_hw_args)) { + CAM_ERR(CAM_JPEG, "Invalid params: %pK %pK", hw_mgr_priv, + acquire_hw_args); + return -EINVAL; + } + + if (args->num_acq > 1) { + CAM_ERR(CAM_JPEG, + "number of resources are wrong: %u", + args->num_acq); + return -EINVAL; + } + + if (copy_from_user(&jpeg_dev_acquire_info, + (void __user *)args->acquire_info, + sizeof(jpeg_dev_acquire_info))) { + CAM_ERR(CAM_JPEG, "copy failed"); + return -EFAULT; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + ctx_id = cam_jpeg_mgr_get_free_ctx(hw_mgr); + if (ctx_id >= CAM_JPEG_CTX_MAX) { + CAM_ERR(CAM_JPEG, "No free ctx space in hw_mgr"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EFAULT; + } + + ctx_data = &hw_mgr->ctx_data[ctx_id]; + + ctx_data->cdm_cmd = + kzalloc(((sizeof(struct cam_cdm_bl_request)) + + ((CAM_JPEG_HW_ENTRIES_MAX - 1) * + sizeof(struct cam_cdm_bl_cmd))), GFP_KERNEL); + if (!ctx_data->cdm_cmd) { + rc = -ENOMEM; + goto jpeg_release_ctx; + } + + mutex_lock(&ctx_data->ctx_mutex); + ctx_data->jpeg_dev_acquire_info = jpeg_dev_acquire_info; + mutex_unlock(&ctx_data->ctx_mutex); + + if (ctx_data->jpeg_dev_acquire_info.dev_type >= + CAM_JPEG_RES_TYPE_MAX) { + rc = -EINVAL; + goto acq_cdm_hdl_failed; + } + dev_type = ctx_data->jpeg_dev_acquire_info.dev_type; + if (!hw_mgr->cdm_info[dev_type][0].ref_cnt) { + + if (dev_type == CAM_JPEG_RES_TYPE_ENC) { + memcpy(cdm_acquire.identifier, + "jpegenc", sizeof("jpegenc")); + } else { + memcpy(cdm_acquire.identifier, + "jpegdma", sizeof("jpegdma")); + } + cdm_acquire.cell_index = 0; + cdm_acquire.handle = 0; + cdm_acquire.userdata = ctx_data; + if (hw_mgr->cdm_reg_map[dev_type][0]) { + cdm_acquire.base_array[0] = + hw_mgr->cdm_reg_map[dev_type][0]; + } + cdm_acquire.base_array_cnt = 1; + cdm_acquire.id = CAM_CDM_VIRTUAL; + cdm_acquire.cam_cdm_callback = NULL; + cdm_acquire.priority = CAM_CDM_BL_FIFO_0; + + rc = cam_cdm_acquire(&cdm_acquire); + if (rc) { + CAM_ERR(CAM_JPEG, "Failed to acquire the CDM HW %d", + rc); + rc = -EFAULT; + goto acq_cdm_hdl_failed; + } + hw_mgr->cdm_info[dev_type][0].cdm_handle = cdm_acquire.handle; + hw_mgr->cdm_info[dev_type][0].cdm_ops = cdm_acquire.ops; + hw_mgr->cdm_info[dev_type][0].ref_cnt++; + } else { + hw_mgr->cdm_info[dev_type][0].ref_cnt++; + } + + size = + hw_mgr->cdm_info[dev_type][0].cdm_ops->cdm_required_size_changebase(); + + if (hw_mgr->cdm_info[dev_type][0].ref_cnt == 1) + if (cam_cdm_stream_on( + hw_mgr->cdm_info[dev_type][0].cdm_handle)) { + CAM_ERR(CAM_JPEG, "Can not start cdm (%d)!", + hw_mgr->cdm_info[dev_type][0].cdm_handle); + rc = -EFAULT; + goto start_cdm_hdl_failed; + } + + mutex_lock(&ctx_data->ctx_mutex); + ctx_data->context_priv = args->context_data; + + args->ctxt_to_hw_map = (void *)&(hw_mgr->ctx_data[ctx_id]); + + mutex_unlock(&ctx_data->ctx_mutex); + + hw_mgr->ctx_data[ctx_id].ctxt_event_cb = args->event_cb; + + + if (copy_to_user((void __user *)args->acquire_info, + &jpeg_dev_acquire_info, + sizeof(jpeg_dev_acquire_info))) { + rc = -EFAULT; + goto copy_to_user_failed; + } + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + CAM_DBG(CAM_JPEG, "success ctx_data= %pK", ctx_data); + + return rc; + +copy_to_user_failed: + if (hw_mgr->cdm_info[dev_type][0].ref_cnt == 1) + cam_cdm_stream_off(hw_mgr->cdm_info[dev_type][0].cdm_handle); +start_cdm_hdl_failed: + if (hw_mgr->cdm_info[dev_type][0].ref_cnt == 1) + cam_cdm_release(hw_mgr->cdm_info[dev_type][0].cdm_handle); + hw_mgr->cdm_info[dev_type][0].ref_cnt--; +acq_cdm_hdl_failed: + kfree(ctx_data->cdm_cmd); +jpeg_release_ctx: + cam_jpeg_mgr_release_ctx(hw_mgr, ctx_data); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + return rc; +} + +static int cam_jpeg_mgr_get_hw_caps(void *hw_mgr_priv, void *hw_caps_args) +{ + int rc; + struct cam_jpeg_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_query_cap_cmd *query_cap = hw_caps_args; + + if (!hw_mgr_priv || !hw_caps_args) { + CAM_ERR(CAM_JPEG, "Invalid params: %pK %pK", + hw_mgr_priv, hw_caps_args); + return -EINVAL; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + + if (copy_to_user(u64_to_user_ptr(query_cap->caps_handle), + &g_jpeg_hw_mgr.jpeg_caps, + sizeof(struct cam_jpeg_query_cap_cmd))) { + CAM_ERR(CAM_JPEG, "copy_to_user failed"); + rc = -EFAULT; + goto copy_error; + } + CAM_DBG(CAM_JPEG, "Success"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + return 0; + +copy_error: + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static int cam_jpeg_setup_workqs(void) +{ + int rc, i; + + rc = cam_req_mgr_workq_create( + "jpeg_command_queue", + CAM_JPEG_WORKQ_NUM_TASK, + &g_jpeg_hw_mgr.work_process_frame, + CRM_WORKQ_USAGE_NON_IRQ, 0); + if (rc) { + CAM_ERR(CAM_JPEG, "unable to create a worker %d", rc); + goto work_process_frame_failed; + } + + rc = cam_req_mgr_workq_create( + "jpeg_message_queue", + CAM_JPEG_WORKQ_NUM_TASK, + &g_jpeg_hw_mgr.work_process_irq_cb, + CRM_WORKQ_USAGE_IRQ, 0); + if (rc) { + CAM_ERR(CAM_JPEG, "unable to create a worker %d", rc); + goto work_process_irq_cb_failed; + } + + g_jpeg_hw_mgr.process_frame_work_data = + kzalloc(sizeof(struct cam_jpeg_process_frame_work_data_t) * + CAM_JPEG_WORKQ_NUM_TASK, GFP_KERNEL); + if (!g_jpeg_hw_mgr.process_frame_work_data) { + rc = -ENOMEM; + goto work_process_frame_data_failed; + } + + g_jpeg_hw_mgr.process_irq_cb_work_data = + kzalloc(sizeof(struct cam_jpeg_process_irq_work_data_t) * + CAM_JPEG_WORKQ_NUM_TASK, GFP_KERNEL); + if (!g_jpeg_hw_mgr.process_irq_cb_work_data) { + rc = -ENOMEM; + goto work_process_irq_cb_data_failed; + } + + for (i = 0; i < CAM_JPEG_WORKQ_NUM_TASK; i++) + g_jpeg_hw_mgr.work_process_irq_cb->task.pool[i].payload = + &g_jpeg_hw_mgr.process_irq_cb_work_data[i]; + + for (i = 0; i < CAM_JPEG_WORKQ_NUM_TASK; i++) + g_jpeg_hw_mgr.work_process_frame->task.pool[i].payload = + &g_jpeg_hw_mgr.process_frame_work_data[i]; + + INIT_LIST_HEAD(&g_jpeg_hw_mgr.hw_config_req_list); + INIT_LIST_HEAD(&g_jpeg_hw_mgr.free_req_list); + for (i = 0; i < CAM_JPEG_HW_CFG_Q_MAX; i++) { + INIT_LIST_HEAD(&(g_jpeg_hw_mgr.req_list[i].list)); + list_add_tail(&(g_jpeg_hw_mgr.req_list[i].list), + &(g_jpeg_hw_mgr.free_req_list)); + } + + return rc; + +work_process_irq_cb_data_failed: + kfree(g_jpeg_hw_mgr.process_frame_work_data); +work_process_frame_data_failed: + cam_req_mgr_workq_destroy(&g_jpeg_hw_mgr.work_process_irq_cb); +work_process_irq_cb_failed: + cam_req_mgr_workq_destroy(&g_jpeg_hw_mgr.work_process_frame); +work_process_frame_failed: + + return rc; +} + +static int cam_jpeg_init_devices(struct device_node *of_node, + uint32_t *p_num_enc_dev, + uint32_t *p_num_dma_dev) +{ + int count, i, rc; + uint32_t num_dev; + uint32_t num_dma_dev; + const char *name = NULL; + struct device_node *child_node = NULL; + struct platform_device *child_pdev = NULL; + struct cam_hw_intf *child_dev_intf = NULL; + struct cam_hw_info *enc_hw = NULL; + struct cam_hw_info *dma_hw = NULL; + struct cam_hw_soc_info *enc_soc_info = NULL; + struct cam_hw_soc_info *dma_soc_info = NULL; + + if (!p_num_enc_dev || !p_num_dma_dev) { + rc = -EINVAL; + goto num_dev_failed; + } + count = of_property_count_strings(of_node, "compat-hw-name"); + if (!count) { + CAM_ERR(CAM_JPEG, + "no compat hw found in dev tree, count = %d", + count); + rc = -EINVAL; + goto num_dev_failed; + } + + rc = of_property_read_u32(of_node, "num-jpeg-enc", &num_dev); + if (rc) { + CAM_ERR(CAM_JPEG, "read num enc devices failed %d", rc); + goto num_enc_failed; + } + g_jpeg_hw_mgr.devices[CAM_JPEG_DEV_ENC] = kzalloc( + sizeof(struct cam_hw_intf *) * num_dev, GFP_KERNEL); + if (!g_jpeg_hw_mgr.devices[CAM_JPEG_DEV_ENC]) { + rc = -ENOMEM; + CAM_ERR(CAM_JPEG, "getting number of dma dev nodes failed"); + goto num_enc_failed; + } + + rc = of_property_read_u32(of_node, "num-jpeg-dma", &num_dma_dev); + if (rc) { + CAM_ERR(CAM_JPEG, "get num dma dev nodes failed %d", rc); + goto num_dma_failed; + } + + g_jpeg_hw_mgr.devices[CAM_JPEG_DEV_DMA] = kzalloc( + sizeof(struct cam_hw_intf *) * num_dma_dev, GFP_KERNEL); + if (!g_jpeg_hw_mgr.devices[CAM_JPEG_DEV_DMA]) { + rc = -ENOMEM; + goto num_dma_failed; + } + + for (i = 0; i < count; i++) { + rc = of_property_read_string_index(of_node, "compat-hw-name", + i, &name); + if (rc) { + CAM_ERR(CAM_JPEG, "getting dev object name failed"); + goto compat_hw_name_failed; + } + + child_node = of_find_node_by_name(NULL, name); + if (!child_node) { + CAM_ERR(CAM_JPEG, + "error! Cannot find node in dtsi %s", name); + rc = -ENODEV; + goto compat_hw_name_failed; + } + + child_pdev = of_find_device_by_node(child_node); + if (!child_pdev) { + CAM_ERR(CAM_JPEG, "failed to find device on bus %s", + child_node->name); + rc = -ENODEV; + of_node_put(child_node); + goto compat_hw_name_failed; + } + + child_dev_intf = (struct cam_hw_intf *)platform_get_drvdata( + child_pdev); + if (!child_dev_intf) { + CAM_ERR(CAM_JPEG, "no child device"); + of_node_put(child_node); + rc = -ENODEV; + goto compat_hw_name_failed; + } + CAM_DBG(CAM_JPEG, "child_intf %pK type %d id %d", + child_dev_intf, + child_dev_intf->hw_type, + child_dev_intf->hw_idx); + + if ((child_dev_intf->hw_type == CAM_JPEG_DEV_ENC && + child_dev_intf->hw_idx >= num_dev) || + (child_dev_intf->hw_type == CAM_JPEG_DEV_DMA && + child_dev_intf->hw_idx >= num_dma_dev)) { + CAM_ERR(CAM_JPEG, "index out of range"); + rc = -ENODEV; + goto compat_hw_name_failed; + } + g_jpeg_hw_mgr.devices[child_dev_intf->hw_type] + [child_dev_intf->hw_idx] = child_dev_intf; + + of_node_put(child_node); + } + + enc_hw = (struct cam_hw_info *) + g_jpeg_hw_mgr.devices[CAM_JPEG_DEV_ENC][0]->hw_priv; + enc_soc_info = &enc_hw->soc_info; + g_jpeg_hw_mgr.cdm_reg_map[CAM_JPEG_DEV_ENC][0] = + &enc_soc_info->reg_map[0]; + dma_hw = (struct cam_hw_info *) + g_jpeg_hw_mgr.devices[CAM_JPEG_DEV_DMA][0]->hw_priv; + dma_soc_info = &dma_hw->soc_info; + g_jpeg_hw_mgr.cdm_reg_map[CAM_JPEG_DEV_DMA][0] = + &dma_soc_info->reg_map[0]; + + *p_num_enc_dev = num_dev; + *p_num_dma_dev = num_dma_dev; + + return rc; + +compat_hw_name_failed: + kfree(g_jpeg_hw_mgr.devices[CAM_JPEG_DEV_DMA]); +num_dma_failed: + kfree(g_jpeg_hw_mgr.devices[CAM_JPEG_DEV_ENC]); +num_enc_failed: +num_dev_failed: + + return rc; +} + +static int cam_jpeg_mgr_hw_dump(void *hw_mgr_priv, void *dump_hw_args) +{ + int rc; + uint8_t *dst; + ktime_t cur_time; + size_t remain_len; + uint32_t min_len; + uint32_t dev_type; + uint64_t diff; + uint64_t *addr, *start; + struct timespec64 cur_ts; + struct timespec64 req_ts; + struct cam_jpeg_hw_mgr *hw_mgr; + struct cam_hw_dump_args *dump_args; + struct cam_jpeg_hw_cfg_req *p_cfg_req; + struct cam_jpeg_hw_ctx_data *ctx_data; + struct cam_jpeg_hw_dump_args jpeg_dump_args; + struct cam_jpeg_hw_dump_header *hdr; + + if (!hw_mgr_priv || !dump_hw_args) { + CAM_ERR(CAM_JPEG, "Invalid args %pK %pK", + hw_mgr_priv, dump_hw_args); + return -EINVAL; + } + + hw_mgr = hw_mgr_priv; + dump_args = (struct cam_hw_dump_args *)dump_hw_args; + ctx_data = (struct cam_jpeg_hw_ctx_data *)dump_args->ctxt_to_hw_map; + + if (!ctx_data) { + CAM_ERR(CAM_JPEG, "Invalid context"); + return -EINVAL; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + + if (!ctx_data->in_use) { + CAM_ERR(CAM_JPEG, "ctx is not in use"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EINVAL; + } + + dev_type = ctx_data->jpeg_dev_acquire_info.dev_type; + + if (true == hw_mgr->device_in_use[dev_type][0]) { + p_cfg_req = hw_mgr->dev_hw_cfg_args[dev_type][0]; + if (p_cfg_req && p_cfg_req->req_id == + (uintptr_t)dump_args->request_id) + goto hw_dump; + } + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return 0; + +hw_dump: + cur_time = ktime_get(); + diff = ktime_us_delta(p_cfg_req->submit_timestamp, cur_time); + cur_ts = ktime_to_timespec64(cur_time); + req_ts = ktime_to_timespec64(p_cfg_req->submit_timestamp); + + if (diff < CAM_JPEG_RESPONSE_TIME_THRESHOLD) { + CAM_INFO(CAM_JPEG, + "No error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return 0; + } + + CAM_INFO(CAM_JPEG, + "Error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &jpeg_dump_args.cpu_addr, &jpeg_dump_args.buf_len); + if (rc) { + CAM_ERR(CAM_JPEG, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -rc; + } + + if (jpeg_dump_args.buf_len <= dump_args->offset) { + CAM_WARN(CAM_JPEG, "dump offset overshoot len %zu offset %zu", + jpeg_dump_args.buf_len, dump_args->offset); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return -ENOSPC; + } + + remain_len = jpeg_dump_args.buf_len - dump_args->offset; + min_len = sizeof(struct cam_jpeg_hw_dump_header) + + (CAM_JPEG_HW_DUMP_NUM_WORDS * sizeof(uint64_t)); + if (remain_len < min_len) { + CAM_WARN(CAM_JPEG, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + cam_mem_put_cpu_buf(dump_args->buf_handle); + return -ENOSPC; + } + + dst = (uint8_t *)jpeg_dump_args.cpu_addr + dump_args->offset; + hdr = (struct cam_jpeg_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_JPEG_HW_DUMP_TAG_MAX_LEN, + "JPEG_REQ:"); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + sizeof(struct cam_jpeg_hw_dump_header)); + start = addr; + *addr++ = dump_args->request_id; + *addr++ = req_ts.tv_sec; + *addr++ = req_ts.tv_nsec/NSEC_PER_USEC; + *addr++ = cur_ts.tv_sec; + *addr++ = cur_ts.tv_nsec/NSEC_PER_USEC; + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_jpeg_hw_dump_header); + jpeg_dump_args.request_id = dump_args->request_id; + jpeg_dump_args.offset = dump_args->offset; + + if (hw_mgr->devices[dev_type][0]->hw_ops.process_cmd) { + rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd( + hw_mgr->devices[dev_type][0]->hw_priv, + CAM_JPEG_CMD_HW_DUMP, + &jpeg_dump_args, sizeof(jpeg_dump_args)); + } + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + CAM_DBG(CAM_JPEG, "Offset before %u after %u", + dump_args->offset, jpeg_dump_args.offset); + dump_args->offset = jpeg_dump_args.offset; + cam_mem_put_cpu_buf(dump_args->buf_handle); + return rc; +} + +static int cam_jpeg_mgr_cmd(void *hw_mgr_priv, void *cmd_args) +{ + int rc = 0; + struct cam_hw_cmd_args *hw_cmd_args = cmd_args; + struct cam_jpeg_hw_mgr *hw_mgr = hw_mgr_priv; + + if (!hw_mgr_priv || !cmd_args) { + CAM_ERR(CAM_JPEG, "Invalid arguments"); + return -EINVAL; + } + + switch (hw_cmd_args->cmd_type) { + case CAM_HW_MGR_CMD_DUMP_PF_INFO: + cam_jpeg_mgr_print_io_bufs( + hw_cmd_args->u.pf_args.pf_data.packet, + hw_mgr->iommu_hdl, + hw_mgr->iommu_sec_hdl, + hw_cmd_args->u.pf_args.buf_info, + hw_cmd_args->u.pf_args.mem_found); + break; + default: + CAM_ERR(CAM_JPEG, "Invalid cmd"); + } + + return rc; +} + +int cam_jpeg_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, + int *iommu_hdl) +{ + int i, rc; + uint32_t num_dev; + uint32_t num_dma_dev; + struct cam_hw_mgr_intf *hw_mgr_intf; + struct cam_iommu_handle cdm_handles; + + hw_mgr_intf = (struct cam_hw_mgr_intf *)hw_mgr_hdl; + if (!of_node || !hw_mgr_intf) { + CAM_ERR(CAM_JPEG, "Invalid args of_node %pK hw_mgr %pK", + of_node, hw_mgr_intf); + return -EINVAL; + } + + memset(hw_mgr_hdl, 0x0, sizeof(struct cam_hw_mgr_intf)); + hw_mgr_intf->hw_mgr_priv = &g_jpeg_hw_mgr; + hw_mgr_intf->hw_get_caps = cam_jpeg_mgr_get_hw_caps; + hw_mgr_intf->hw_acquire = cam_jpeg_mgr_acquire_hw; + hw_mgr_intf->hw_release = cam_jpeg_mgr_release_hw; + hw_mgr_intf->hw_prepare_update = cam_jpeg_mgr_prepare_hw_update; + hw_mgr_intf->hw_config = cam_jpeg_mgr_config_hw; + hw_mgr_intf->hw_flush = cam_jpeg_mgr_hw_flush; + hw_mgr_intf->hw_stop = cam_jpeg_mgr_hw_stop; + hw_mgr_intf->hw_cmd = cam_jpeg_mgr_cmd; + hw_mgr_intf->hw_dump = cam_jpeg_mgr_hw_dump; + + mutex_init(&g_jpeg_hw_mgr.hw_mgr_mutex); + spin_lock_init(&g_jpeg_hw_mgr.hw_mgr_lock); + + for (i = 0; i < CAM_JPEG_CTX_MAX; i++) + mutex_init(&g_jpeg_hw_mgr.ctx_data[i].ctx_mutex); + + rc = cam_jpeg_init_devices(of_node, &num_dev, &num_dma_dev); + if (rc) { + CAM_ERR(CAM_JPEG, "jpeg init devices %d", rc); + goto smmu_get_failed; + } + + rc = cam_smmu_get_handle("jpeg", &g_jpeg_hw_mgr.iommu_hdl); + if (rc) { + CAM_ERR(CAM_JPEG, "jpeg get iommu handle failed %d", rc); + goto smmu_get_failed; + } + + CAM_DBG(CAM_JPEG, "mmu handle :%d", g_jpeg_hw_mgr.iommu_hdl); + + rc = cam_cdm_get_iommu_handle("jpegenc", &cdm_handles); + if (rc) { + CAM_ERR(CAM_JPEG, "acquire cdm iommu handle Fail %d", rc); + g_jpeg_hw_mgr.cdm_iommu_hdl = -1; + g_jpeg_hw_mgr.cdm_iommu_hdl_secure = -1; + goto cdm_iommu_failed; + } + g_jpeg_hw_mgr.cdm_iommu_hdl = cdm_handles.non_secure; + g_jpeg_hw_mgr.cdm_iommu_hdl_secure = cdm_handles.secure; + + g_jpeg_hw_mgr.jpeg_caps.dev_iommu_handle.non_secure = + g_jpeg_hw_mgr.iommu_hdl; + g_jpeg_hw_mgr.jpeg_caps.dev_iommu_handle.secure = + g_jpeg_hw_mgr.iommu_sec_hdl; + g_jpeg_hw_mgr.jpeg_caps.cdm_iommu_handle.non_secure = + g_jpeg_hw_mgr.cdm_iommu_hdl; + g_jpeg_hw_mgr.jpeg_caps.cdm_iommu_handle.secure = + g_jpeg_hw_mgr.cdm_iommu_hdl_secure; + g_jpeg_hw_mgr.jpeg_caps.num_enc = num_dev; + g_jpeg_hw_mgr.jpeg_caps.num_dma = num_dma_dev; + g_jpeg_hw_mgr.jpeg_caps.dev_ver[CAM_JPEG_DEV_ENC].hw_ver.major = 4; + g_jpeg_hw_mgr.jpeg_caps.dev_ver[CAM_JPEG_DEV_ENC].hw_ver.minor = 2; + g_jpeg_hw_mgr.jpeg_caps.dev_ver[CAM_JPEG_DEV_ENC].hw_ver.incr = 0; + g_jpeg_hw_mgr.jpeg_caps.dev_ver[CAM_JPEG_DEV_ENC].hw_ver.reserved = 0; + g_jpeg_hw_mgr.jpeg_caps.dev_ver[CAM_JPEG_DEV_DMA].hw_ver.major = 4; + g_jpeg_hw_mgr.jpeg_caps.dev_ver[CAM_JPEG_DEV_DMA].hw_ver.minor = 2; + g_jpeg_hw_mgr.jpeg_caps.dev_ver[CAM_JPEG_DEV_DMA].hw_ver.incr = 0; + g_jpeg_hw_mgr.jpeg_caps.dev_ver[CAM_JPEG_DEV_DMA].hw_ver.reserved = 0; + + rc = cam_jpeg_setup_workqs(); + if (rc) { + CAM_ERR(CAM_JPEG, "setup work qs failed %d", rc); + goto cdm_iommu_failed; + } + + if (iommu_hdl) + *iommu_hdl = g_jpeg_hw_mgr.iommu_hdl; + + return rc; + +cdm_iommu_failed: + cam_smmu_destroy_handle(g_jpeg_hw_mgr.iommu_hdl); + g_jpeg_hw_mgr.iommu_hdl = 0; +smmu_get_failed: + mutex_destroy(&g_jpeg_hw_mgr.hw_mgr_mutex); + for (i = 0; i < CAM_JPEG_CTX_MAX; i++) + mutex_destroy(&g_jpeg_hw_mgr.ctx_data[i].ctx_mutex); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h new file mode 100644 index 0000000000000000000000000000000000000000..3a00e424ebc9fe2e0aa55a301dff28352ec4ea14 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_JPEG_HW_MGR_H +#define CAM_JPEG_HW_MGR_H + +#include +#include +#include + +#include "cam_jpeg_hw_intf.h" +#include "cam_hw_mgr_intf.h" +#include "cam_hw_intf.h" +#include "cam_req_mgr_workq.h" +#include "cam_mem_mgr.h" + +#define CAM_JPEG_WORKQ_NUM_TASK 30 +#define CAM_JPEG_WORKQ_TASK_CMD_TYPE 1 +#define CAM_JPEG_WORKQ_TASK_MSG_TYPE 2 +#define CAM_JPEG_HW_CFG_Q_MAX 50 + +/* + * Response time threshold in ms beyond which a request is not expected + * to be with JPEG hw + */ +#define CAM_JPEG_RESPONSE_TIME_THRESHOLD 100000 + +/** + * struct cam_jpeg_process_frame_work_data_t + * + * @type: Task type + * @data: Pointer to command data + * @request_id: Request id + */ +struct cam_jpeg_process_frame_work_data_t { + uint32_t type; + void *data; + uintptr_t request_id; +}; + +/** + * struct cam_jpeg_process_irq_work_data_t + * + * @type: Task type + * @data: Pointer to message data + * @result_size: Result size of enc/dma + * @irq_status: IRQ status + */ +struct cam_jpeg_process_irq_work_data_t { + uint32_t type; + void *data; + int32_t result_size; + uint32_t irq_status; +}; + +/** + * struct cam_jpeg_hw_cdm_info_t + * + * @ref_cnt: Ref count of how many times device type is acquired + * @cdm_handle: Cdm handle + * @cdm_ops: Cdm ops struct + */ +struct cam_jpeg_hw_cdm_info_t { + int ref_cnt; + uint32_t cdm_handle; + struct cam_cdm_utils_ops *cdm_ops; +}; + +/** + * struct cam_jpeg_hw_cfg_req_t + * + * @list_head: List head + * @hw_cfg_args: Hw config args + * @dev_type: Dev type for cfg request + * @req_id: Request Id + * @submit_timestamp: Timestamp of submitting request + */ +struct cam_jpeg_hw_cfg_req { + struct list_head list; + struct cam_hw_config_args hw_cfg_args; + uint32_t dev_type; + uintptr_t req_id; + ktime_t submit_timestamp; +}; + +/** + * struct cam_jpeg_hw_ctx_data + * + * @context_priv: Context private data, cam_context from + * acquire. + * @ctx_mutex: Mutex for context + * @jpeg_dev_acquire_info: Acquire device info + * @ctxt_event_cb: Context callback function + * @in_use: Flag for context usage + * @wait_complete: Completion info + * @cdm_cmd: Cdm cmd submitted for that context. + */ +struct cam_jpeg_hw_ctx_data { + void *context_priv; + struct mutex ctx_mutex; + struct cam_jpeg_acquire_dev_info jpeg_dev_acquire_info; + cam_hw_event_cb_func ctxt_event_cb; + bool in_use; + struct completion wait_complete; + struct cam_cdm_bl_request *cdm_cmd; +}; + +/** + * struct cam_jpeg_hw_mgr + * @hw_mgr_mutex: Mutex for JPEG hardware manager + * @hw_mgr_lock: Spinlock for JPEG hardware manager + * @ctx_data: Context data + * @jpeg_caps: JPEG capabilities + * @iommu_hdl: Non secure IOMMU handle + * @iommu_sec_hdl: Secure IOMMU handle + * @work_process_frame: Work queue for hw config requests + * @work_process_irq_cb: Work queue for processing IRQs. + * @process_frame_work_data: Work data pool for hw config + * requests + * @process_irq_cb_work_data: Work data pool for irq requests + * @cdm_iommu_hdl: Iommu handle received from cdm + * @cdm_iommu_hdl_secure: Secure iommu handle received from cdm + * @devices: Core hw Devices of JPEG hardware manager + * @cdm_info: Cdm info for each core device. + * @cdm_reg_map: Regmap of each device for cdm. + * @device_in_use: Flag device being used for an active request + * @dev_hw_cfg_args: Current cfg request per core dev + * @hw_config_req_list: Pending hw update requests list + * @free_req_list: Free nodes for above list + * @req_list: Nodes of hw update list + */ +struct cam_jpeg_hw_mgr { + struct mutex hw_mgr_mutex; + spinlock_t hw_mgr_lock; + struct cam_jpeg_hw_ctx_data ctx_data[CAM_JPEG_CTX_MAX]; + struct cam_jpeg_query_cap_cmd jpeg_caps; + int32_t iommu_hdl; + int32_t iommu_sec_hdl; + struct cam_req_mgr_core_workq *work_process_frame; + struct cam_req_mgr_core_workq *work_process_irq_cb; + struct cam_jpeg_process_frame_work_data_t *process_frame_work_data; + struct cam_jpeg_process_irq_work_data_t *process_irq_cb_work_data; + int cdm_iommu_hdl; + int cdm_iommu_hdl_secure; + + struct cam_hw_intf **devices[CAM_JPEG_DEV_TYPE_MAX]; + struct cam_jpeg_hw_cdm_info_t cdm_info[CAM_JPEG_DEV_TYPE_MAX] + [CAM_JPEG_NUM_DEV_PER_RES_MAX]; + struct cam_soc_reg_map *cdm_reg_map[CAM_JPEG_DEV_TYPE_MAX] + [CAM_JPEG_NUM_DEV_PER_RES_MAX]; + uint32_t device_in_use[CAM_JPEG_DEV_TYPE_MAX] + [CAM_JPEG_NUM_DEV_PER_RES_MAX]; + struct cam_jpeg_hw_cfg_req *dev_hw_cfg_args[CAM_JPEG_DEV_TYPE_MAX] + [CAM_JPEG_NUM_DEV_PER_RES_MAX]; + + struct list_head hw_config_req_list; + struct list_head free_req_list; + struct cam_jpeg_hw_cfg_req req_list[CAM_JPEG_HW_CFG_Q_MAX]; +}; + +#endif /* CAM_JPEG_HW_MGR_H */ diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..df552c4d04cf893f5b4e126981712683226be2d1 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_JPEG_HW_INTF_H +#define CAM_JPEG_HW_INTF_H + +#include "cam_cpas_api.h" + +#define CAM_JPEG_DEV_PER_TYPE_MAX 1 + +#define CAM_JPEG_CMD_BUF_MAX_SIZE 128 +#define CAM_JPEG_MSG_BUF_MAX_SIZE CAM_JPEG_CMD_BUF_MAX_SIZE + +#define JPEG_VOTE 640000000 + +#define CAM_JPEG_HW_DUMP_TAG_MAX_LEN 32 +#define CAM_JPEG_HW_DUMP_NUM_WORDS 5 + +enum cam_jpeg_hw_type { + CAM_JPEG_DEV_ENC, + CAM_JPEG_DEV_DMA, +}; + +struct cam_jpeg_set_irq_cb { + int32_t (*jpeg_hw_mgr_cb)(uint32_t irq_status, + int32_t result_size, void *data); + void *data; + uint32_t b_set_cb; +}; + +struct cam_jpeg_hw_dump_args { + uint64_t request_id; + uintptr_t cpu_addr; + size_t offset; + size_t buf_len; +}; + +struct cam_jpeg_hw_dump_header { + uint8_t tag[CAM_JPEG_HW_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + +enum cam_jpeg_cmd_type { + CAM_JPEG_CMD_CDM_CFG, + CAM_JPEG_CMD_SET_IRQ_CB, + CAM_JPEG_CMD_HW_DUMP, + CAM_JPEG_CMD_MAX, +}; + +#endif diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..b83a308f7d7836a6349f2c7dfb97a7d8a4ddd12d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_JPEG_HW_MGR_INTF_H +#define CAM_JPEG_HW_MGR_INTF_H + +#include +#include +#include + +#define CAM_JPEG_CTX_MAX 16 + +int cam_jpeg_hw_mgr_init(struct device_node *of_node, + uint64_t *hw_mgr_hdl, int *iommu_hdl); + +#endif /* CAM_JPEG_HW_MGR_INTF_H */ diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/Makefile b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..05f84fb945edfb7711830ab739be6b992d1acfa7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw + +obj-$(CONFIG_SPECTRA_CAMERA) += jpeg_dma_dev.o jpeg_dma_core.o jpeg_dma_soc.o diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c new file mode 100644 index 0000000000000000000000000000000000000000..1304bbc71d389daa5ee9de31df72fe5ceab1a0b0 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "cam_io_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "jpeg_dma_core.h" +#include "jpeg_dma_soc.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_jpeg_hw_intf.h" +#include "cam_jpeg_hw_mgr_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" + +int cam_jpeg_dma_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *jpeg_dma_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_jpeg_dma_device_core_info *core_info = NULL; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + int rc; + + if (!device_priv) { + CAM_ERR(CAM_JPEG, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &jpeg_dma_dev->soc_info; + core_info = (struct cam_jpeg_dma_device_core_info *) + jpeg_dma_dev->core_info; + + if (!soc_info || !core_info) { + CAM_ERR(CAM_JPEG, "soc_info = %pK core_info = %pK", + soc_info, core_info); + return -EINVAL; + } + + mutex_lock(&core_info->core_mutex); + if (++core_info->ref_count > 1) { + mutex_unlock(&core_info->core_mutex); + return 0; + } + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_LOWSVS_VOTE; + axi_vote.num_paths = 2; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_READ; + axi_vote.axi_path[0].camnoc_bw = JPEG_VOTE; + axi_vote.axi_path[0].mnoc_ab_bw = JPEG_VOTE; + axi_vote.axi_path[0].mnoc_ib_bw = JPEG_VOTE; + axi_vote.axi_path[1].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[1].transac_type = CAM_AXI_TRANSACTION_WRITE; + axi_vote.axi_path[1].camnoc_bw = JPEG_VOTE; + axi_vote.axi_path[1].mnoc_ab_bw = JPEG_VOTE; + axi_vote.axi_path[1].mnoc_ib_bw = JPEG_VOTE; + + + rc = cam_cpas_start(core_info->cpas_handle, + &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_JPEG, "cpass start failed: %d", rc); + goto cpas_failed; + } + + rc = cam_jpeg_dma_enable_soc_resources(soc_info); + if (rc) { + CAM_ERR(CAM_JPEG, "soc enable is failed %d", rc); + goto soc_failed; + } + + mutex_unlock(&core_info->core_mutex); + + return 0; + +soc_failed: + cam_cpas_stop(core_info->cpas_handle); +cpas_failed: + --core_info->ref_count; + mutex_unlock(&core_info->core_mutex); + + return rc; +} + +int cam_jpeg_dma_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *jpeg_dma_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_jpeg_dma_device_core_info *core_info = NULL; + int rc; + + if (!device_priv) { + CAM_ERR(CAM_JPEG, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &jpeg_dma_dev->soc_info; + core_info = (struct cam_jpeg_dma_device_core_info *) + jpeg_dma_dev->core_info; + if (!soc_info || !core_info) { + CAM_ERR(CAM_JPEG, "soc_info = %pK core_info = %pK", + soc_info, core_info); + return -EINVAL; + } + + mutex_lock(&core_info->core_mutex); + if (--core_info->ref_count > 0) { + mutex_unlock(&core_info->core_mutex); + return 0; + } + + if (core_info->ref_count < 0) { + CAM_ERR(CAM_JPEG, "ref cnt %d", core_info->ref_count); + core_info->ref_count = 0; + mutex_unlock(&core_info->core_mutex); + return -EFAULT; + } + + rc = cam_jpeg_dma_disable_soc_resources(soc_info); + if (rc) + CAM_ERR(CAM_JPEG, "soc enable failed %d", rc); + + rc = cam_cpas_stop(core_info->cpas_handle); + if (rc) + CAM_ERR(CAM_JPEG, "cpas stop failed: %d", rc); + + mutex_unlock(&core_info->core_mutex); + + return 0; +} + +int cam_jpeg_dma_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + struct cam_hw_info *jpeg_dma_dev = device_priv; + struct cam_jpeg_dma_device_core_info *core_info = NULL; + int rc; + + if (!device_priv) { + CAM_ERR(CAM_JPEG, "Invalid arguments"); + return -EINVAL; + } + + if (cmd_type >= CAM_JPEG_CMD_MAX) { + CAM_ERR(CAM_JPEG, "Invalid command : %x", cmd_type); + return -EINVAL; + } + + core_info = (struct cam_jpeg_dma_device_core_info *) + jpeg_dma_dev->core_info; + + switch (cmd_type) { + case CAM_JPEG_CMD_SET_IRQ_CB: + { + struct cam_jpeg_set_irq_cb *irq_cb = cmd_args; + + if (!cmd_args) { + CAM_ERR(CAM_JPEG, "cmd args NULL"); + return -EINVAL; + } + if (irq_cb->b_set_cb) { + core_info->irq_cb.jpeg_hw_mgr_cb = + irq_cb->jpeg_hw_mgr_cb; + core_info->irq_cb.data = irq_cb->data; + } else { + core_info->irq_cb.jpeg_hw_mgr_cb = NULL; + core_info->irq_cb.data = NULL; + } + rc = 0; + break; + } + default: + rc = -EINVAL; + break; + } + + return rc; +} + +irqreturn_t cam_jpeg_dma_irq(int irq_num, void *data) +{ + return IRQ_HANDLED; +} diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.h b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.h new file mode 100644 index 0000000000000000000000000000000000000000..dc3a1c13fe829b6120efc80a1f5722013180530f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_JPEG_DMA_CORE_H +#define CAM_JPEG_DMA_CORE_H + +#include +#include +#include +#include + +#include "cam_jpeg_hw_intf.h" + +struct cam_jpeg_dma_device_hw_info { + uint32_t reserved; +}; + +enum cam_jpeg_dma_core_state { + CAM_JPEG_DMA_CORE_NOT_READY, + CAM_JPEG_DMA_CORE_READY, + CAM_JPEG_DMA_CORE_RESETTING, + CAM_JPEG_DMA_CORE_STATE_MAX, +}; + +struct cam_jpeg_dma_device_core_info { + enum cam_jpeg_dma_core_state core_state; + struct cam_jpeg_dma_device_hw_info *jpeg_dma_hw_info; + uint32_t cpas_handle; + struct cam_jpeg_set_irq_cb irq_cb; + int32_t ref_count; + struct mutex core_mutex; +}; + +int cam_jpeg_dma_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_jpeg_dma_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_jpeg_dma_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size); +irqreturn_t cam_jpeg_dma_irq(int irq_num, void *data); + +#endif /* CAM_JPEG_DMA_CORE_H */ diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_dev.c b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..ce82c5e799c5fe1c8ead1694326271df0cc7eab5 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_dev.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "jpeg_dma_core.h" +#include "jpeg_dma_soc.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "cam_io_util.h" +#include "cam_jpeg_hw_intf.h" +#include "cam_jpeg_hw_mgr_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" + +static struct cam_jpeg_dma_device_hw_info cam_jpeg_dma_hw_info = { + .reserved = 0, +}; +EXPORT_SYMBOL(cam_jpeg_dma_hw_info); + +static int cam_jpeg_dma_register_cpas(struct cam_hw_soc_info *soc_info, + struct cam_jpeg_dma_device_core_info *core_info, + uint32_t hw_idx) +{ + struct cam_cpas_register_params cpas_register_params; + int rc; + + cpas_register_params.dev = soc_info->dev; + memcpy(cpas_register_params.identifier, "jpeg-dma", + sizeof("jpeg-dma")); + cpas_register_params.cam_cpas_client_cb = NULL; + cpas_register_params.cell_index = hw_idx; + cpas_register_params.userdata = NULL; + + rc = cam_cpas_register_client(&cpas_register_params); + if (rc) { + CAM_ERR(CAM_JPEG, "cpas_register failed: %d", rc); + return rc; + } + core_info->cpas_handle = cpas_register_params.client_handle; + + return rc; +} + +static int cam_jpeg_dma_unregister_cpas( + struct cam_jpeg_dma_device_core_info *core_info) +{ + int rc; + + rc = cam_cpas_unregister_client(core_info->cpas_handle); + if (rc) + CAM_ERR(CAM_JPEG, "cpas unregister failed: %d", rc); + core_info->cpas_handle = 0; + + return rc; +} + +static int cam_jpeg_dma_remove(struct platform_device *pdev) +{ + struct cam_hw_info *jpeg_dma_dev = NULL; + struct cam_hw_intf *jpeg_dma_dev_intf = NULL; + struct cam_jpeg_dma_device_core_info *core_info = NULL; + int rc; + + jpeg_dma_dev_intf = platform_get_drvdata(pdev); + if (!jpeg_dma_dev_intf) { + CAM_ERR(CAM_JPEG, "error No data in pdev"); + return -EINVAL; + } + + jpeg_dma_dev = jpeg_dma_dev_intf->hw_priv; + if (!jpeg_dma_dev) { + CAM_ERR(CAM_JPEG, "error HW data is NULL"); + rc = -ENODEV; + goto free_jpeg_hw_intf; + } + + core_info = (struct cam_jpeg_dma_device_core_info *) + jpeg_dma_dev->core_info; + if (!core_info) { + CAM_ERR(CAM_JPEG, "error core data NULL"); + goto deinit_soc; + } + + rc = cam_jpeg_dma_unregister_cpas(core_info); + if (rc) + CAM_ERR(CAM_JPEG, " unreg failed to reg cpas %d", rc); + + mutex_destroy(&core_info->core_mutex); + kfree(core_info); + +deinit_soc: + rc = cam_soc_util_release_platform_resource(&jpeg_dma_dev->soc_info); + if (rc) + CAM_ERR(CAM_JPEG, "Failed to deinit soc rc=%d", rc); + + mutex_destroy(&jpeg_dma_dev->hw_mutex); + kfree(jpeg_dma_dev); + +free_jpeg_hw_intf: + kfree(jpeg_dma_dev_intf); + return rc; +} + +static int cam_jpeg_dma_probe(struct platform_device *pdev) +{ + struct cam_hw_info *jpeg_dma_dev = NULL; + struct cam_hw_intf *jpeg_dma_dev_intf = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_jpeg_dma_device_core_info *core_info = NULL; + struct cam_jpeg_dma_device_hw_info *hw_info = NULL; + int rc; + + jpeg_dma_dev_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!jpeg_dma_dev_intf) + return -ENOMEM; + + of_property_read_u32(pdev->dev.of_node, + "cell-index", &jpeg_dma_dev_intf->hw_idx); + + jpeg_dma_dev = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!jpeg_dma_dev) { + rc = -ENOMEM; + goto error_alloc_dev; + } + jpeg_dma_dev->soc_info.pdev = pdev; + jpeg_dma_dev->soc_info.dev = &pdev->dev; + jpeg_dma_dev->soc_info.dev_name = pdev->name; + jpeg_dma_dev_intf->hw_priv = jpeg_dma_dev; + jpeg_dma_dev_intf->hw_ops.init = cam_jpeg_dma_init_hw; + jpeg_dma_dev_intf->hw_ops.deinit = cam_jpeg_dma_deinit_hw; + jpeg_dma_dev_intf->hw_ops.process_cmd = cam_jpeg_dma_process_cmd; + jpeg_dma_dev_intf->hw_type = CAM_JPEG_DEV_DMA; + + platform_set_drvdata(pdev, jpeg_dma_dev_intf); + jpeg_dma_dev->core_info = + kzalloc(sizeof(struct cam_jpeg_dma_device_core_info), + GFP_KERNEL); + if (!jpeg_dma_dev->core_info) { + rc = -ENOMEM; + goto error_alloc_core; + } + core_info = (struct cam_jpeg_dma_device_core_info *) + jpeg_dma_dev->core_info; + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_JPEG, " No jpeg_dma hardware info"); + rc = -EINVAL; + goto error_match_dev; + } + hw_info = (struct cam_jpeg_dma_device_hw_info *)match_dev->data; + core_info->jpeg_dma_hw_info = hw_info; + core_info->core_state = CAM_JPEG_DMA_CORE_NOT_READY; + mutex_init(&core_info->core_mutex); + + rc = cam_jpeg_dma_init_soc_resources(&jpeg_dma_dev->soc_info, + cam_jpeg_dma_irq, + jpeg_dma_dev); + if (rc) { + CAM_ERR(CAM_JPEG, "failed to init_soc %d", rc); + goto error_init_soc; + } + + rc = cam_jpeg_dma_register_cpas(&jpeg_dma_dev->soc_info, + core_info, jpeg_dma_dev_intf->hw_idx); + if (rc) { + CAM_ERR(CAM_JPEG, " failed to reg cpas %d", rc); + goto error_reg_cpas; + } + jpeg_dma_dev->hw_state = CAM_HW_STATE_POWER_DOWN; + mutex_init(&jpeg_dma_dev->hw_mutex); + spin_lock_init(&jpeg_dma_dev->hw_lock); + init_completion(&jpeg_dma_dev->hw_complete); + + CAM_DBG(CAM_JPEG, " hwidx %d", jpeg_dma_dev_intf->hw_idx); + + return rc; + +error_reg_cpas: + rc = cam_soc_util_release_platform_resource(&jpeg_dma_dev->soc_info); +error_init_soc: + mutex_destroy(&core_info->core_mutex); +error_match_dev: + kfree(jpeg_dma_dev->core_info); +error_alloc_core: + kfree(jpeg_dma_dev); +error_alloc_dev: + kfree(jpeg_dma_dev_intf); + return rc; +} + +static const struct of_device_id cam_jpeg_dma_dt_match[] = { + { + .compatible = "qcom,cam_jpeg_dma", + .data = &cam_jpeg_dma_hw_info, + }, + {} +}; +MODULE_DEVICE_TABLE(of, cam_jpeg_dma_dt_match); + +static struct platform_driver cam_jpeg_dma_driver = { + .probe = cam_jpeg_dma_probe, + .remove = cam_jpeg_dma_remove, + .driver = { + .name = "cam-jpeg-dma", + .owner = THIS_MODULE, + .of_match_table = cam_jpeg_dma_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_jpeg_dma_init_module(void) +{ + return platform_driver_register(&cam_jpeg_dma_driver); +} + +static void __exit cam_jpeg_dma_exit_module(void) +{ + platform_driver_unregister(&cam_jpeg_dma_driver); +} + +module_init(cam_jpeg_dma_init_module); +module_exit(cam_jpeg_dma_exit_module); +MODULE_DESCRIPTION("CAM JPEG_DMA driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_soc.c b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..9dda8f284c354ea8d9f0925693f058e84364723f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_soc.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "jpeg_dma_soc.h" +#include "cam_soc_util.h" +#include "cam_debug_util.h" + +int cam_jpeg_dma_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t jpeg_dma_irq_handler, void *irq_data) +{ + int rc; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc) + return rc; + + rc = cam_soc_util_request_platform_resource(soc_info, + jpeg_dma_irq_handler, + irq_data); + if (rc) + CAM_ERR(CAM_JPEG, "init soc failed %d", rc); + + return rc; +} + +int cam_jpeg_dma_enable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc; + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_SVS_VOTE, true); + if (rc) + CAM_ERR(CAM_JPEG, "enable platform failed %d", rc); + + return rc; +} + +int cam_jpeg_dma_disable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) + CAM_ERR(CAM_JPEG, "disable platform failed %d", rc); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_soc.h b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..a0c07489ee77e71226a825a6041b6fb736865ff3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_soc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_JPEG_DMA_SOC_H_ +#define _CAM_JPEG_DMA_SOC_H_ + +#include "cam_soc_util.h" + +int cam_jpeg_dma_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t jpeg_dma_irq_handler, void *irq_data); + +int cam_jpeg_dma_enable_soc_resources(struct cam_hw_soc_info *soc_info); + +int cam_jpeg_dma_disable_soc_resources(struct cam_hw_soc_info *soc_info); + +#endif /* _CAM_JPEG_DMA_SOC_H_*/ diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/Makefile b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..baa3b06d52b9d1ae661570ce37af42c0003c13a8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw + +obj-$(CONFIG_SPECTRA_CAMERA) += jpeg_enc_dev.o jpeg_enc_core.o jpeg_enc_soc.o diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h new file mode 100644 index 0000000000000000000000000000000000000000..b75998bc586cd2697d6bbd578e91f2ebc1f7fe31 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_JPEG_ENC_HW_INFO_TITAN170_H +#define CAM_JPEG_ENC_HW_INFO_TITAN170_H + +#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK 0x00000001 +#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_SHIFT 0x00000000 + +#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK 0x10000000 +#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_SHIFT 0x0000000a + +#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK 0x8000000 +#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_SHIFT 0x0000001b + +#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_MASK 0x00000800 +#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_SHIFT 0x0000000b + +#define CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF (0x1<<19) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR (0x1<<20) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR (0x1<<21) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF (0x1<<22) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW (0x1<<23) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM (0x1<<24) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ (0x1<<25) +#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM (0x1<<26) +#define CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK (0x1<<29) + +#define CAM_JPEG_HW_MASK_COMP_FRAMEDONE \ + CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK +#define CAM_JPEG_HW_MASK_COMP_RESET_ACK \ + CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK +#define CAM_JPEG_HW_MASK_COMP_ERR \ + (CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ | \ + CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM | \ + CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK) + +static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_hw_info = { + .reg_offset = { + .hw_version = 0x0, + .int_clr = 0x1c, + .int_status = 0x20, + .int_mask = 0x18, + .hw_cmd = 0x10, + .reset_cmd = 0x8, + .encode_size = 0x180, + }, + .reg_val = { + .int_clr_clearall = 0xFFFFFFFF, + .int_mask_disable_all = 0x00000000, + .int_mask_enable_all = 0xFFFFFFFF, + .hw_cmd_start = 0x00000001, + .reset_cmd = 0x200320D3, + .hw_cmd_stop = 0x00000002, + }, + .int_status = { + .framedone = CAM_JPEG_HW_MASK_COMP_FRAMEDONE, + .resetdone = CAM_JPEG_HW_MASK_COMP_RESET_ACK, + .iserror = CAM_JPEG_HW_MASK_COMP_ERR, + .stopdone = CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK, + }, + .reg_dump = { + .start_offset = 0x0, + .end_offset = 0x33C, + } +}; + +#endif /* CAM_JPEG_ENC_HW_INFO_TITAN170_H */ diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c new file mode 100644 index 0000000000000000000000000000000000000000..c0cfbe7a76e442e994693e53ff50986d5004ffb7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c @@ -0,0 +1,547 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "cam_io_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "jpeg_enc_core.h" +#include "jpeg_enc_soc.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_jpeg_hw_intf.h" +#include "cam_jpeg_hw_mgr_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" + +#define CAM_JPEG_HW_IRQ_IS_FRAME_DONE(jpeg_irq_status, hi) \ + ((jpeg_irq_status) & (hi)->int_status.framedone) +#define CAM_JPEG_HW_IRQ_IS_RESET_ACK(jpeg_irq_status, hi) \ + ((jpeg_irq_status) & (hi)->int_status.resetdone) +#define CAM_JPEG_HW_IRQ_IS_ERR(jpeg_irq_status, hi) \ + ((jpeg_irq_status) & (hi)->int_status.iserror) +#define CAM_JPEG_HW_IRQ_IS_STOP_DONE(jpeg_irq_status, hi) \ + ((jpeg_irq_status) & (hi)->int_status.stopdone) + +#define CAM_JPEG_ENC_RESET_TIMEOUT msecs_to_jiffies(500) + +int cam_jpeg_enc_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *jpeg_enc_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_jpeg_enc_device_core_info *core_info = NULL; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + unsigned long flags; + int rc; + + if (!device_priv) { + CAM_ERR(CAM_JPEG, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &jpeg_enc_dev->soc_info; + core_info = (struct cam_jpeg_enc_device_core_info *) + jpeg_enc_dev->core_info; + + if (!soc_info || !core_info) { + CAM_ERR(CAM_JPEG, "soc_info = %pK core_info = %pK", + soc_info, core_info); + return -EINVAL; + } + + mutex_lock(&core_info->core_mutex); + if (++core_info->ref_count > 1) { + mutex_unlock(&core_info->core_mutex); + return 0; + } + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_LOWSVS_VOTE; + axi_vote.num_paths = 2; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_READ; + axi_vote.axi_path[0].camnoc_bw = JPEG_VOTE; + axi_vote.axi_path[0].mnoc_ab_bw = JPEG_VOTE; + axi_vote.axi_path[0].mnoc_ib_bw = JPEG_VOTE; + axi_vote.axi_path[1].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[1].transac_type = CAM_AXI_TRANSACTION_WRITE; + axi_vote.axi_path[1].camnoc_bw = JPEG_VOTE; + axi_vote.axi_path[1].mnoc_ab_bw = JPEG_VOTE; + axi_vote.axi_path[1].mnoc_ib_bw = JPEG_VOTE; + + + rc = cam_cpas_start(core_info->cpas_handle, + &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_JPEG, "cpass start failed: %d", rc); + goto cpas_failed; + } + + rc = cam_jpeg_enc_enable_soc_resources(soc_info); + if (rc) { + CAM_ERR(CAM_JPEG, "soc enable is failed %d", rc); + goto soc_failed; + } + spin_lock_irqsave(&jpeg_enc_dev->hw_lock, flags); + jpeg_enc_dev->hw_state = CAM_HW_STATE_POWER_UP; + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + + mutex_unlock(&core_info->core_mutex); + + return 0; + +soc_failed: + cam_cpas_stop(core_info->cpas_handle); +cpas_failed: + --core_info->ref_count; + mutex_unlock(&core_info->core_mutex); + + return rc; +} + +int cam_jpeg_enc_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *jpeg_enc_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_jpeg_enc_device_core_info *core_info = NULL; + unsigned long flags; + int rc; + + if (!device_priv) { + CAM_ERR(CAM_JPEG, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &jpeg_enc_dev->soc_info; + core_info = (struct cam_jpeg_enc_device_core_info *) + jpeg_enc_dev->core_info; + if (!soc_info || !core_info) { + CAM_ERR(CAM_JPEG, "soc_info = %pK core_info = %pK", + soc_info, core_info); + return -EINVAL; + } + + mutex_lock(&core_info->core_mutex); + if (--core_info->ref_count > 0) { + mutex_unlock(&core_info->core_mutex); + return 0; + } + + if (core_info->ref_count < 0) { + CAM_ERR(CAM_JPEG, "ref cnt %d", core_info->ref_count); + core_info->ref_count = 0; + mutex_unlock(&core_info->core_mutex); + return -EFAULT; + } + + spin_lock_irqsave(&jpeg_enc_dev->hw_lock, flags); + jpeg_enc_dev->hw_state = CAM_HW_STATE_POWER_DOWN; + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + rc = cam_jpeg_enc_disable_soc_resources(soc_info); + if (rc) + CAM_ERR(CAM_JPEG, "soc disable failed %d", rc); + + rc = cam_cpas_stop(core_info->cpas_handle); + if (rc) + CAM_ERR(CAM_JPEG, "cpas stop failed: %d", rc); + + mutex_unlock(&core_info->core_mutex); + + return 0; +} + +irqreturn_t cam_jpeg_enc_irq(int irq_num, void *data) +{ + struct cam_hw_info *jpeg_enc_dev = data; + struct cam_jpeg_enc_device_core_info *core_info = NULL; + uint32_t irq_status = 0; + uint32_t encoded_size = 0; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_jpeg_enc_device_hw_info *hw_info = NULL; + void __iomem *mem_base; + + if (!jpeg_enc_dev) { + CAM_ERR(CAM_JPEG, "Invalid args"); + return IRQ_HANDLED; + } + soc_info = &jpeg_enc_dev->soc_info; + core_info = (struct cam_jpeg_enc_device_core_info *) + jpeg_enc_dev->core_info; + hw_info = core_info->jpeg_enc_hw_info; + mem_base = soc_info->reg_map[0].mem_base; + + spin_lock(&jpeg_enc_dev->hw_lock); + if (jpeg_enc_dev->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_ERR(CAM_JPEG, "JPEG HW is in off state"); + spin_unlock(&jpeg_enc_dev->hw_lock); + return IRQ_HANDLED; + } + irq_status = cam_io_r_mb(mem_base + + core_info->jpeg_enc_hw_info->reg_offset.int_status); + + cam_io_w_mb(irq_status, + soc_info->reg_map[0].mem_base + + core_info->jpeg_enc_hw_info->reg_offset.int_clr); + spin_unlock(&jpeg_enc_dev->hw_lock); + + CAM_DBG(CAM_JPEG, "irq_num %d irq_status = %x , core_state %d", + irq_num, irq_status, core_info->core_state); + + if (CAM_JPEG_HW_IRQ_IS_FRAME_DONE(irq_status, hw_info)) { + spin_lock(&jpeg_enc_dev->hw_lock); + if (core_info->core_state == CAM_JPEG_ENC_CORE_READY) { + encoded_size = cam_io_r_mb(mem_base + + core_info->jpeg_enc_hw_info->reg_offset.encode_size); + if (core_info->irq_cb.jpeg_hw_mgr_cb) { + core_info->irq_cb.jpeg_hw_mgr_cb(irq_status, + encoded_size, + core_info->irq_cb.data); + } else { + CAM_ERR(CAM_JPEG, "unexpected done, no cb"); + } + } else { + CAM_ERR(CAM_JPEG, "unexpected done irq"); + } + core_info->core_state = CAM_JPEG_ENC_CORE_NOT_READY; + spin_unlock(&jpeg_enc_dev->hw_lock); + } + if (CAM_JPEG_HW_IRQ_IS_RESET_ACK(irq_status, hw_info)) { + spin_lock(&jpeg_enc_dev->hw_lock); + if (core_info->core_state == CAM_JPEG_ENC_CORE_RESETTING) { + core_info->core_state = CAM_JPEG_ENC_CORE_READY; + complete(&jpeg_enc_dev->hw_complete); + } else { + CAM_ERR(CAM_JPEG, "unexpected reset irq"); + } + spin_unlock(&jpeg_enc_dev->hw_lock); + } + if (CAM_JPEG_HW_IRQ_IS_STOP_DONE(irq_status, hw_info)) { + spin_lock(&jpeg_enc_dev->hw_lock); + if (core_info->core_state == CAM_JPEG_ENC_CORE_ABORTING) { + core_info->core_state = CAM_JPEG_ENC_CORE_NOT_READY; + complete(&jpeg_enc_dev->hw_complete); + if (core_info->irq_cb.jpeg_hw_mgr_cb) { + core_info->irq_cb.jpeg_hw_mgr_cb(irq_status, + -1, + core_info->irq_cb.data); + } + } else { + CAM_ERR(CAM_JPEG, "unexpected abort irq"); + } + spin_unlock(&jpeg_enc_dev->hw_lock); + } + /* Unexpected/unintended HW interrupt */ + if (CAM_JPEG_HW_IRQ_IS_ERR(irq_status, hw_info)) { + spin_lock(&jpeg_enc_dev->hw_lock); + core_info->core_state = CAM_JPEG_ENC_CORE_NOT_READY; + CAM_ERR_RATE_LIMIT(CAM_JPEG, + "error irq_num %d irq_status = %x , core_state %d", + irq_num, irq_status, core_info->core_state); + + if (core_info->irq_cb.jpeg_hw_mgr_cb) { + core_info->irq_cb.jpeg_hw_mgr_cb(irq_status, + -1, + core_info->irq_cb.data); + } + spin_unlock(&jpeg_enc_dev->hw_lock); + } + + return IRQ_HANDLED; +} + +int cam_jpeg_enc_reset_hw(void *data, + void *start_args, uint32_t arg_size) +{ + struct cam_hw_info *jpeg_enc_dev = data; + struct cam_jpeg_enc_device_core_info *core_info = NULL; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_jpeg_enc_device_hw_info *hw_info = NULL; + void __iomem *mem_base; + unsigned long rem_jiffies; + unsigned long flags; + + if (!jpeg_enc_dev) { + CAM_ERR(CAM_JPEG, "Invalid args"); + return -EINVAL; + } + /* maskdisable.clrirq.maskenable.resetcmd */ + soc_info = &jpeg_enc_dev->soc_info; + core_info = (struct cam_jpeg_enc_device_core_info *) + jpeg_enc_dev->core_info; + hw_info = core_info->jpeg_enc_hw_info; + mem_base = soc_info->reg_map[0].mem_base; + + mutex_lock(&core_info->core_mutex); + spin_lock_irqsave(&jpeg_enc_dev->hw_lock, flags); + if (jpeg_enc_dev->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_ERR(CAM_JPEG, "JPEG HW is in off state"); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + mutex_unlock(&core_info->core_mutex); + return -EINVAL; + } + if (core_info->core_state == CAM_JPEG_ENC_CORE_RESETTING) { + CAM_ERR(CAM_JPEG, "alrady resetting"); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + mutex_unlock(&core_info->core_mutex); + return 0; + } + + reinit_completion(&jpeg_enc_dev->hw_complete); + core_info->core_state = CAM_JPEG_ENC_CORE_RESETTING; + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + + cam_io_w_mb(hw_info->reg_val.int_mask_disable_all, + mem_base + hw_info->reg_offset.int_mask); + cam_io_w_mb(hw_info->reg_val.int_clr_clearall, + mem_base + hw_info->reg_offset.int_clr); + cam_io_w_mb(hw_info->reg_val.int_mask_enable_all, + mem_base + hw_info->reg_offset.int_mask); + cam_io_w_mb(hw_info->reg_val.reset_cmd, + mem_base + hw_info->reg_offset.reset_cmd); + + rem_jiffies = wait_for_completion_timeout(&jpeg_enc_dev->hw_complete, + CAM_JPEG_ENC_RESET_TIMEOUT); + if (!rem_jiffies) { + CAM_ERR(CAM_JPEG, "error Reset Timeout"); + core_info->core_state = CAM_JPEG_ENC_CORE_NOT_READY; + } + + mutex_unlock(&core_info->core_mutex); + return 0; +} + +int cam_jpeg_enc_start_hw(void *data, + void *start_args, uint32_t arg_size) +{ + struct cam_hw_info *jpeg_enc_dev = data; + struct cam_jpeg_enc_device_core_info *core_info = NULL; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_jpeg_enc_device_hw_info *hw_info = NULL; + void __iomem *mem_base; + unsigned long flags; + + if (!jpeg_enc_dev) { + CAM_ERR(CAM_JPEG, "Invalid args"); + return -EINVAL; + } + + soc_info = &jpeg_enc_dev->soc_info; + core_info = (struct cam_jpeg_enc_device_core_info *) + jpeg_enc_dev->core_info; + hw_info = core_info->jpeg_enc_hw_info; + mem_base = soc_info->reg_map[0].mem_base; + + spin_lock_irqsave(&jpeg_enc_dev->hw_lock, flags); + if (jpeg_enc_dev->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_ERR(CAM_JPEG, "JPEG HW is in off state"); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + return -EINVAL; + } + if (core_info->core_state != CAM_JPEG_ENC_CORE_READY) { + CAM_ERR(CAM_JPEG, "Error not ready: %d", core_info->core_state); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + return -EINVAL; + } + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + + cam_io_w_mb(hw_info->reg_val.hw_cmd_start, + mem_base + hw_info->reg_offset.hw_cmd); + + return 0; +} + +int cam_jpeg_enc_stop_hw(void *data, + void *stop_args, uint32_t arg_size) +{ + struct cam_hw_info *jpeg_enc_dev = data; + struct cam_jpeg_enc_device_core_info *core_info = NULL; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_jpeg_enc_device_hw_info *hw_info = NULL; + void __iomem *mem_base; + unsigned long rem_jiffies; + unsigned long flags; + + if (!jpeg_enc_dev) { + CAM_ERR(CAM_JPEG, "Invalid args"); + return -EINVAL; + } + soc_info = &jpeg_enc_dev->soc_info; + core_info = (struct cam_jpeg_enc_device_core_info *) + jpeg_enc_dev->core_info; + hw_info = core_info->jpeg_enc_hw_info; + mem_base = soc_info->reg_map[0].mem_base; + + mutex_lock(&core_info->core_mutex); + spin_lock_irqsave(&jpeg_enc_dev->hw_lock, flags); + if (jpeg_enc_dev->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_ERR(CAM_JPEG, "JPEG HW is in off state"); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + mutex_unlock(&core_info->core_mutex); + return -EINVAL; + } + if (core_info->core_state == CAM_JPEG_ENC_CORE_ABORTING) { + CAM_ERR(CAM_JPEG, "alrady stopping"); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + mutex_unlock(&core_info->core_mutex); + return 0; + } + + reinit_completion(&jpeg_enc_dev->hw_complete); + core_info->core_state = CAM_JPEG_ENC_CORE_ABORTING; + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + + cam_io_w_mb(hw_info->reg_val.hw_cmd_stop, + mem_base + hw_info->reg_offset.hw_cmd); + + rem_jiffies = wait_for_completion_timeout(&jpeg_enc_dev->hw_complete, + CAM_JPEG_ENC_RESET_TIMEOUT); + if (!rem_jiffies) { + CAM_ERR(CAM_JPEG, "error Reset Timeout"); + core_info->core_state = CAM_JPEG_ENC_CORE_NOT_READY; + } + + mutex_unlock(&core_info->core_mutex); + return 0; +} + +int cam_jpeg_enc_hw_dump( + struct cam_hw_info *jpeg_enc_dev, + struct cam_jpeg_hw_dump_args *dump_args) +{ + + int i; + uint8_t *dst; + uint32_t *addr, *start; + uint32_t num_reg, min_len; + uint32_t reg_start_offset; + size_t remain_len; + struct cam_hw_soc_info *soc_info; + struct cam_jpeg_hw_dump_header *hdr; + struct cam_jpeg_enc_device_hw_info *hw_info; + struct cam_jpeg_enc_device_core_info *core_info; + + soc_info = &jpeg_enc_dev->soc_info; + core_info = (struct cam_jpeg_enc_device_core_info *) + jpeg_enc_dev->core_info; + hw_info = core_info->jpeg_enc_hw_info; + mutex_lock(&core_info->core_mutex); + spin_lock(&jpeg_enc_dev->hw_lock); + + if (jpeg_enc_dev->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_ERR(CAM_JPEG, "JPEG HW is in off state"); + spin_unlock(&jpeg_enc_dev->hw_lock); + mutex_unlock(&core_info->core_mutex); + return -EINVAL; + } + + spin_unlock(&jpeg_enc_dev->hw_lock); + + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_JPEG, "dump buffer overshoot %zu %zu", + dump_args->buf_len, dump_args->offset); + mutex_unlock(&core_info->core_mutex); + return -ENOSPC; + } + + remain_len = dump_args->buf_len - dump_args->offset; + min_len = sizeof(struct cam_jpeg_hw_dump_header) + + soc_info->reg_map[0].size + sizeof(uint32_t); + if (remain_len < min_len) { + CAM_WARN(CAM_JPEG, "dump buffer exhaust %zu %u", + remain_len, min_len); + mutex_unlock(&core_info->core_mutex); + return -ENOSPC; + } + + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_jpeg_hw_dump_header *)dst; + snprintf(hdr->tag, CAM_JPEG_HW_DUMP_TAG_MAX_LEN, + "JPEG_REG:"); + hdr->word_size = sizeof(uint32_t); + addr = (uint32_t *)(dst + sizeof(struct cam_jpeg_hw_dump_header)); + start = addr; + *addr++ = soc_info->index; + num_reg = (hw_info->reg_dump.end_offset - + hw_info->reg_dump.start_offset)/4; + reg_start_offset = hw_info->reg_dump.start_offset; + for (i = 0; i < num_reg; i++) { + *addr++ = soc_info->mem_block[0]->start + + reg_start_offset + i*4; + *addr++ = cam_io_r(soc_info->reg_map[0].mem_base + (i*4)); + } + + mutex_unlock(&core_info->core_mutex); + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_jpeg_hw_dump_header); + CAM_DBG(CAM_JPEG, "offset %zu", dump_args->offset); + + return 0; +} + +int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + struct cam_hw_info *jpeg_enc_dev = device_priv; + struct cam_jpeg_enc_device_core_info *core_info = NULL; + int rc; + + if (!device_priv) { + CAM_ERR(CAM_JPEG, "Invalid arguments"); + return -EINVAL; + } + + if (cmd_type >= CAM_JPEG_CMD_MAX) { + CAM_ERR(CAM_JPEG, "Invalid command : %x", cmd_type); + return -EINVAL; + } + + core_info = (struct cam_jpeg_enc_device_core_info *) + jpeg_enc_dev->core_info; + + switch (cmd_type) { + case CAM_JPEG_CMD_SET_IRQ_CB: + { + struct cam_jpeg_set_irq_cb *irq_cb = cmd_args; + + if (!cmd_args) { + CAM_ERR(CAM_JPEG, "cmd args NULL"); + return -EINVAL; + } + if (irq_cb->b_set_cb) { + core_info->irq_cb.jpeg_hw_mgr_cb = + irq_cb->jpeg_hw_mgr_cb; + core_info->irq_cb.data = irq_cb->data; + } else { + core_info->irq_cb.jpeg_hw_mgr_cb = NULL; + core_info->irq_cb.data = NULL; + } + rc = 0; + break; + } + case CAM_JPEG_CMD_HW_DUMP: + { + rc = cam_jpeg_enc_hw_dump(jpeg_enc_dev, + cmd_args); + break; + } + default: + rc = -EINVAL; + break; + } + if (rc) + CAM_ERR(CAM_JPEG, "error cmdtype %d rc = %d", cmd_type, rc); + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h new file mode 100644 index 0000000000000000000000000000000000000000..ca83dccb193f8827b250adbb6f430aa721c85e4d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_JPEG_ENC_CORE_H +#define CAM_JPEG_ENC_CORE_H + +#include +#include +#include +#include + +#include "cam_jpeg_hw_intf.h" + +struct cam_jpeg_enc_reg_offsets { + uint32_t hw_version; + uint32_t int_status; + uint32_t int_clr; + uint32_t int_mask; + uint32_t hw_cmd; + uint32_t reset_cmd; + uint32_t encode_size; +}; + +struct cam_jpeg_enc_regval { + uint32_t int_clr_clearall; + uint32_t int_mask_disable_all; + uint32_t int_mask_enable_all; + uint32_t hw_cmd_start; + uint32_t reset_cmd; + uint32_t hw_cmd_stop; +}; + +struct cam_jpeg_enc_int_status { + uint32_t framedone; + uint32_t resetdone; + uint32_t iserror; + uint32_t stopdone; +}; + +struct cam_jpeg_enc_reg_dump { + uint32_t start_offset; + uint32_t end_offset; +}; + +struct cam_jpeg_enc_device_hw_info { + struct cam_jpeg_enc_reg_offsets reg_offset; + struct cam_jpeg_enc_regval reg_val; + struct cam_jpeg_enc_int_status int_status; + struct cam_jpeg_enc_reg_dump reg_dump; +}; + +enum cam_jpeg_enc_core_state { + CAM_JPEG_ENC_CORE_NOT_READY, + CAM_JPEG_ENC_CORE_READY, + CAM_JPEG_ENC_CORE_RESETTING, + CAM_JPEG_ENC_CORE_ABORTING, + CAM_JPEG_ENC_CORE_STATE_MAX, +}; + +struct cam_jpeg_enc_device_core_info { + enum cam_jpeg_enc_core_state core_state; + struct cam_jpeg_enc_device_hw_info *jpeg_enc_hw_info; + uint32_t cpas_handle; + struct cam_jpeg_set_irq_cb irq_cb; + int32_t ref_count; + struct mutex core_mutex; +}; + +int cam_jpeg_enc_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_jpeg_enc_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_jpeg_enc_start_hw(void *device_priv, + void *start_hw_args, uint32_t arg_size); +int cam_jpeg_enc_stop_hw(void *device_priv, + void *stop_hw_args, uint32_t arg_size); +int cam_jpeg_enc_reset_hw(void *device_priv, + void *reset_hw_args, uint32_t arg_size); +int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size); +irqreturn_t cam_jpeg_enc_irq(int irq_num, void *data); + +#endif /* CAM_JPEG_ENC_CORE_H */ diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..8eb8ec36785082d29dee6075bd19f626170dcfe5 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "jpeg_enc_core.h" +#include "jpeg_enc_soc.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "cam_io_util.h" +#include "cam_jpeg_hw_intf.h" +#include "cam_jpeg_hw_mgr_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "cam_jpeg_enc_hw_info_ver_4_2_0.h" + +static int cam_jpeg_enc_register_cpas(struct cam_hw_soc_info *soc_info, + struct cam_jpeg_enc_device_core_info *core_info, + uint32_t hw_idx) +{ + struct cam_cpas_register_params cpas_register_params; + int rc; + + cpas_register_params.dev = soc_info->dev; + memcpy(cpas_register_params.identifier, "jpeg-enc", + sizeof("jpeg-enc")); + cpas_register_params.cam_cpas_client_cb = NULL; + cpas_register_params.cell_index = hw_idx; + cpas_register_params.userdata = NULL; + + rc = cam_cpas_register_client(&cpas_register_params); + if (rc) { + CAM_ERR(CAM_JPEG, "cpas_register failed: %d", rc); + return rc; + } + core_info->cpas_handle = cpas_register_params.client_handle; + + return rc; +} + +static int cam_jpeg_enc_unregister_cpas( + struct cam_jpeg_enc_device_core_info *core_info) +{ + int rc; + + rc = cam_cpas_unregister_client(core_info->cpas_handle); + if (rc) + CAM_ERR(CAM_JPEG, "cpas unregister failed: %d", rc); + core_info->cpas_handle = 0; + + return rc; +} + +static int cam_jpeg_enc_remove(struct platform_device *pdev) +{ + struct cam_hw_info *jpeg_enc_dev = NULL; + struct cam_hw_intf *jpeg_enc_dev_intf = NULL; + struct cam_jpeg_enc_device_core_info *core_info = NULL; + int rc; + + jpeg_enc_dev_intf = platform_get_drvdata(pdev); + if (!jpeg_enc_dev_intf) { + CAM_ERR(CAM_JPEG, "error No data in pdev"); + return -EINVAL; + } + + jpeg_enc_dev = jpeg_enc_dev_intf->hw_priv; + if (!jpeg_enc_dev) { + CAM_ERR(CAM_JPEG, "error HW data is NULL"); + rc = -ENODEV; + goto free_jpeg_hw_intf; + } + + core_info = (struct cam_jpeg_enc_device_core_info *) + jpeg_enc_dev->core_info; + if (!core_info) { + CAM_ERR(CAM_JPEG, "error core data NULL"); + goto deinit_soc; + } + + rc = cam_jpeg_enc_unregister_cpas(core_info); + if (rc) + CAM_ERR(CAM_JPEG, " unreg failed to reg cpas %d", rc); + + mutex_destroy(&core_info->core_mutex); + kfree(core_info); + +deinit_soc: + rc = cam_soc_util_release_platform_resource(&jpeg_enc_dev->soc_info); + if (rc) + CAM_ERR(CAM_JPEG, "Failed to deinit soc rc=%d", rc); + + mutex_destroy(&jpeg_enc_dev->hw_mutex); + kfree(jpeg_enc_dev); + +free_jpeg_hw_intf: + kfree(jpeg_enc_dev_intf); + return rc; +} + +static int cam_jpeg_enc_probe(struct platform_device *pdev) +{ + struct cam_hw_info *jpeg_enc_dev = NULL; + struct cam_hw_intf *jpeg_enc_dev_intf = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_jpeg_enc_device_core_info *core_info = NULL; + struct cam_jpeg_enc_device_hw_info *hw_info = NULL; + int rc; + + jpeg_enc_dev_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!jpeg_enc_dev_intf) + return -ENOMEM; + + of_property_read_u32(pdev->dev.of_node, + "cell-index", &jpeg_enc_dev_intf->hw_idx); + + jpeg_enc_dev = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!jpeg_enc_dev) { + rc = -ENOMEM; + goto error_alloc_dev; + } + jpeg_enc_dev->soc_info.pdev = pdev; + jpeg_enc_dev->soc_info.dev = &pdev->dev; + jpeg_enc_dev->soc_info.dev_name = pdev->name; + jpeg_enc_dev_intf->hw_priv = jpeg_enc_dev; + jpeg_enc_dev_intf->hw_ops.init = cam_jpeg_enc_init_hw; + jpeg_enc_dev_intf->hw_ops.deinit = cam_jpeg_enc_deinit_hw; + jpeg_enc_dev_intf->hw_ops.start = cam_jpeg_enc_start_hw; + jpeg_enc_dev_intf->hw_ops.stop = cam_jpeg_enc_stop_hw; + jpeg_enc_dev_intf->hw_ops.reset = cam_jpeg_enc_reset_hw; + jpeg_enc_dev_intf->hw_ops.process_cmd = cam_jpeg_enc_process_cmd; + jpeg_enc_dev_intf->hw_type = CAM_JPEG_DEV_ENC; + + platform_set_drvdata(pdev, jpeg_enc_dev_intf); + jpeg_enc_dev->core_info = + kzalloc(sizeof(struct cam_jpeg_enc_device_core_info), + GFP_KERNEL); + if (!jpeg_enc_dev->core_info) { + rc = -ENOMEM; + goto error_alloc_core; + } + core_info = (struct cam_jpeg_enc_device_core_info *) + jpeg_enc_dev->core_info; + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_JPEG, " No jpeg_enc hardware info"); + rc = -EINVAL; + goto error_match_dev; + } + hw_info = (struct cam_jpeg_enc_device_hw_info *)match_dev->data; + core_info->jpeg_enc_hw_info = hw_info; + core_info->core_state = CAM_JPEG_ENC_CORE_NOT_READY; + mutex_init(&core_info->core_mutex); + + rc = cam_jpeg_enc_init_soc_resources(&jpeg_enc_dev->soc_info, + cam_jpeg_enc_irq, + jpeg_enc_dev); + if (rc) { + CAM_ERR(CAM_JPEG, " failed to init_soc %d", rc); + goto error_init_soc; + } + + rc = cam_jpeg_enc_register_cpas(&jpeg_enc_dev->soc_info, + core_info, jpeg_enc_dev_intf->hw_idx); + if (rc) { + CAM_ERR(CAM_JPEG, " failed to reg cpas %d", rc); + goto error_reg_cpas; + } + jpeg_enc_dev->hw_state = CAM_HW_STATE_POWER_DOWN; + mutex_init(&jpeg_enc_dev->hw_mutex); + spin_lock_init(&jpeg_enc_dev->hw_lock); + init_completion(&jpeg_enc_dev->hw_complete); + + return rc; + +error_reg_cpas: + cam_soc_util_release_platform_resource(&jpeg_enc_dev->soc_info); +error_init_soc: + mutex_destroy(&core_info->core_mutex); +error_match_dev: + kfree(jpeg_enc_dev->core_info); +error_alloc_core: + kfree(jpeg_enc_dev); +error_alloc_dev: + kfree(jpeg_enc_dev_intf); + + return rc; +} + +static const struct of_device_id cam_jpeg_enc_dt_match[] = { + { + .compatible = "qcom,cam_jpeg_enc", + .data = &cam_jpeg_enc_hw_info, + }, + {} +}; +MODULE_DEVICE_TABLE(of, cam_jpeg_enc_dt_match); + +static struct platform_driver cam_jpeg_enc_driver = { + .probe = cam_jpeg_enc_probe, + .remove = cam_jpeg_enc_remove, + .driver = { + .name = "cam-jpeg-enc", + .owner = THIS_MODULE, + .of_match_table = cam_jpeg_enc_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_jpeg_enc_init_module(void) +{ + return platform_driver_register(&cam_jpeg_enc_driver); +} + +static void __exit cam_jpeg_enc_exit_module(void) +{ + platform_driver_unregister(&cam_jpeg_enc_driver); +} + +module_init(cam_jpeg_enc_init_module); +module_exit(cam_jpeg_enc_exit_module); +MODULE_DESCRIPTION("CAM JPEG_ENC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_soc.c b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..4a5d9e0a9b600998583e39d12ff34f0530d003f0 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_soc.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "jpeg_enc_soc.h" +#include "cam_soc_util.h" +#include "cam_debug_util.h" + +int cam_jpeg_enc_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t jpeg_enc_irq_handler, void *irq_data) +{ + int rc; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc) + return rc; + + rc = cam_soc_util_request_platform_resource(soc_info, + jpeg_enc_irq_handler, + irq_data); + if (rc) + CAM_ERR(CAM_JPEG, "init soc failed %d", rc); + + return rc; +} + +int cam_jpeg_enc_enable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc; + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_SVS_VOTE, true); + if (rc) + CAM_ERR(CAM_JPEG, "enable platform failed %d", rc); + + return rc; +} + +int cam_jpeg_enc_disable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) + CAM_ERR(CAM_JPEG, "disable platform failed %d", rc); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_soc.h b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..e0fb0103de7557b7c64f7307b06273bf4324987c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_soc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_JPEG_ENC_SOC_H_ +#define _CAM_JPEG_ENC_SOC_H_ + +#include "cam_soc_util.h" + +int cam_jpeg_enc_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t jpeg_enc_irq_handler, void *irq_data); + +int cam_jpeg_enc_enable_soc_resources(struct cam_hw_soc_info *soc_info); + +int cam_jpeg_enc_disable_soc_resources(struct cam_hw_soc_info *soc_info); + +#endif /* _CAM_JPEG_ENC_SOC_H_*/ diff --git a/techpack/camera-bengal/drivers/cam_lrme/Makefile b/techpack/camera-bengal/drivers/cam_lrme/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..32e2d4fd30e00a1bd987676d4bf8d5ac37235725 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include/ + +obj-$(CONFIG_SPECTRA_CAMERA) += lrme_hw_mgr/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_lrme_dev.o cam_lrme_context.o diff --git a/techpack/camera-bengal/drivers/cam_lrme/cam_lrme_context.c b/techpack/camera-bengal/drivers/cam_lrme/cam_lrme_context.c new file mode 100644 index 0000000000000000000000000000000000000000..857aab9dd476e2e20babcefd2365cf2862077df0 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/cam_lrme_context.c @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include + +#include "cam_debug_util.h" +#include "cam_lrme_context.h" + +static const char lrme_dev_name[] = "cam-lrme"; + +static int __cam_lrme_ctx_acquire_dev_in_available(struct cam_context *ctx, + struct cam_acquire_dev_cmd *cmd) +{ + int rc = 0; + uintptr_t ctxt_to_hw_map = (uintptr_t)ctx->ctxt_to_hw_map; + struct cam_lrme_context *lrme_ctx = ctx->ctx_priv; + + CAM_DBG(CAM_LRME, "Enter ctx %d", ctx->ctx_id); + + rc = cam_context_acquire_dev_to_hw(ctx, cmd); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to acquire"); + return rc; + } + + ctxt_to_hw_map |= (lrme_ctx->index << CAM_LRME_CTX_INDEX_SHIFT); + ctx->ctxt_to_hw_map = (void *)ctxt_to_hw_map; + + ctx->state = CAM_CTX_ACQUIRED; + + return rc; +} + +static int __cam_lrme_ctx_release_dev_in_acquired(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc = 0; + + CAM_DBG(CAM_LRME, "Enter ctx %d", ctx->ctx_id); + + rc = cam_context_release_dev_to_hw(ctx, cmd); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to release"); + return rc; + } + + ctx->state = CAM_CTX_AVAILABLE; + + return rc; +} + +static int __cam_lrme_ctx_start_dev_in_acquired(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc = 0; + + CAM_DBG(CAM_LRME, "Enter ctx %d", ctx->ctx_id); + + rc = cam_context_start_dev_to_hw(ctx, cmd); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to start"); + return rc; + } + + ctx->state = CAM_CTX_ACTIVATED; + + return rc; +} + +static int __cam_lrme_ctx_config_dev_in_activated(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + int rc; + + CAM_DBG(CAM_LRME, "Enter ctx %d", ctx->ctx_id); + + rc = cam_context_prepare_dev_to_hw(ctx, cmd); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to config"); + return rc; + } + + return rc; +} + +static int __cam_lrme_ctx_dump_dev_in_activated( + struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc = 0; + + CAM_DBG(CAM_LRME, "Enter ctx %d", ctx->ctx_id); + + rc = cam_context_dump_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_LRME, "Failed to dump device"); + + return rc; +} + +static int __cam_lrme_ctx_flush_dev_in_activated(struct cam_context *ctx, + struct cam_flush_dev_cmd *cmd) +{ + int rc; + + CAM_DBG(CAM_LRME, "Enter ctx %d", ctx->ctx_id); + + rc = cam_context_flush_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_LRME, "Failed to flush device"); + + return rc; +} +static int __cam_lrme_ctx_stop_dev_in_activated(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc = 0; + + CAM_DBG(CAM_LRME, "Enter ctx %d", ctx->ctx_id); + + rc = cam_context_stop_dev_to_hw(ctx); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to stop dev"); + return rc; + } + + ctx->state = CAM_CTX_ACQUIRED; + + return rc; +} + +static int __cam_lrme_ctx_release_dev_in_activated(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc = 0; + + CAM_DBG(CAM_LRME, "Enter ctx %d", ctx->ctx_id); + + rc = __cam_lrme_ctx_stop_dev_in_activated(ctx, NULL); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to stop"); + return rc; + } + + rc = cam_context_release_dev_to_hw(ctx, cmd); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to release"); + return rc; + } + + ctx->state = CAM_CTX_AVAILABLE; + + return rc; +} + +static int __cam_lrme_ctx_handle_irq_in_activated(void *context, + uint32_t evt_id, void *evt_data) +{ + int rc; + + CAM_DBG(CAM_LRME, "Enter"); + + rc = cam_context_buf_done_from_hw(context, evt_data, evt_id); + if (rc) { + CAM_ERR(CAM_LRME, "Failed in buf done, rc=%d", rc); + return rc; + } + + return rc; +} + +/* top state machine */ +static struct cam_ctx_ops + cam_lrme_ctx_state_machine[CAM_CTX_STATE_MAX] = { + /* Uninit */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Available */ + { + .ioctl_ops = { + .acquire_dev = __cam_lrme_ctx_acquire_dev_in_available, + }, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Acquired */ + { + .ioctl_ops = { + .config_dev = __cam_lrme_ctx_config_dev_in_activated, + .release_dev = __cam_lrme_ctx_release_dev_in_acquired, + .start_dev = __cam_lrme_ctx_start_dev_in_acquired, + }, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Ready */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Flushed */ + {}, + /* Activate */ + { + .ioctl_ops = { + .config_dev = __cam_lrme_ctx_config_dev_in_activated, + .release_dev = __cam_lrme_ctx_release_dev_in_activated, + .stop_dev = __cam_lrme_ctx_stop_dev_in_activated, + .flush_dev = __cam_lrme_ctx_flush_dev_in_activated, + .dump_dev = __cam_lrme_ctx_dump_dev_in_activated, + }, + .crm_ops = {}, + .irq_ops = __cam_lrme_ctx_handle_irq_in_activated, + }, +}; + +int cam_lrme_context_init(struct cam_lrme_context *lrme_ctx, + struct cam_context *base_ctx, + struct cam_hw_mgr_intf *hw_intf, + uint32_t index) +{ + int rc = 0; + + CAM_DBG(CAM_LRME, "Enter"); + + if (!base_ctx || !lrme_ctx) { + CAM_ERR(CAM_LRME, "Invalid input"); + return -EINVAL; + } + + memset(lrme_ctx, 0, sizeof(*lrme_ctx)); + + rc = cam_context_init(base_ctx, lrme_dev_name, CAM_LRME, index, + NULL, hw_intf, lrme_ctx->req_base, CAM_CTX_REQ_MAX); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to init context"); + return rc; + } + lrme_ctx->base = base_ctx; + lrme_ctx->index = index; + base_ctx->ctx_priv = lrme_ctx; + base_ctx->state_machine = cam_lrme_ctx_state_machine; + + return rc; +} + +int cam_lrme_context_deinit(struct cam_lrme_context *lrme_ctx) +{ + int rc = 0; + + CAM_DBG(CAM_LRME, "Enter"); + + if (!lrme_ctx) { + CAM_ERR(CAM_LRME, "No ctx to deinit"); + return -EINVAL; + } + + rc = cam_context_deinit(lrme_ctx->base); + + memset(lrme_ctx, 0, sizeof(*lrme_ctx)); + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_lrme/cam_lrme_context.h b/techpack/camera-bengal/drivers/cam_lrme/cam_lrme_context.h new file mode 100644 index 0000000000000000000000000000000000000000..9fb88ed85f1b6cd6b3fc5dd0becc26b538d2e81f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/cam_lrme_context.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_LRME_CONTEXT_H_ +#define _CAM_LRME_CONTEXT_H_ + +#include "cam_context.h" +#include "cam_context_utils.h" +#include "cam_hw_mgr_intf.h" +#include "cam_req_mgr_interface.h" + +#define CAM_LRME_CTX_INDEX_SHIFT 16 + +/** + * struct cam_lrme_context + * + * @base : Base context pointer for this LRME context + * @req_base : List of base request for this LRME context + */ +struct cam_lrme_context { + struct cam_context *base; + struct cam_ctx_request req_base[CAM_CTX_REQ_MAX]; + uint64_t index; +}; + +int cam_lrme_context_init(struct cam_lrme_context *lrme_ctx, + struct cam_context *base_ctx, struct cam_hw_mgr_intf *hw_intf, + uint32_t index); +int cam_lrme_context_deinit(struct cam_lrme_context *lrme_ctx); + +#endif /* _CAM_LRME_CONTEXT_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_lrme/cam_lrme_dev.c b/techpack/camera-bengal/drivers/cam_lrme/cam_lrme_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..656a4dbd726bf372a0b021a4ced0486e31f8dacf --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/cam_lrme_dev.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "cam_subdev.h" +#include "cam_node.h" +#include "cam_lrme_context.h" +#include "cam_lrme_hw_mgr.h" +#include "cam_lrme_hw_mgr_intf.h" + +#define CAM_LRME_DEV_NAME "cam-lrme" + +/** + * struct cam_lrme_dev + * + * @sd : Subdev information + * @ctx : List of base contexts + * @lrme_ctx : List of LRME contexts + * @lock : Mutex for LRME subdev + * @open_cnt : Open count of LRME subdev + */ +struct cam_lrme_dev { + struct cam_subdev sd; + struct cam_context ctx[CAM_CTX_MAX]; + struct cam_lrme_context lrme_ctx[CAM_CTX_MAX]; + struct mutex lock; + uint32_t open_cnt; +}; + +static struct cam_lrme_dev *g_lrme_dev; + +static int cam_lrme_dev_buf_done_cb(void *ctxt_to_hw_map, uint32_t evt_id, + void *evt_data) +{ + uint64_t index; + struct cam_context *ctx; + int rc; + + index = CAM_LRME_DECODE_CTX_INDEX(ctxt_to_hw_map); + CAM_DBG(CAM_LRME, "ctx index %llu, evt_id %u\n", index, evt_id); + ctx = &g_lrme_dev->ctx[index]; + rc = ctx->irq_cb_intf(ctx, evt_id, evt_data); + if (rc) + CAM_ERR(CAM_LRME, "irq callback failed"); + + return rc; +} + +static int cam_lrme_dev_open(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct cam_lrme_dev *lrme_dev = g_lrme_dev; + + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); + + if (!lrme_dev) { + CAM_ERR(CAM_LRME, + "LRME Dev not initialized, dev=%pK", lrme_dev); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); + return -ENODEV; + } + + mutex_lock(&lrme_dev->lock); + lrme_dev->open_cnt++; + mutex_unlock(&lrme_dev->lock); + + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); + + return 0; +} + +static int cam_lrme_dev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + int rc = 0; + struct cam_lrme_dev *lrme_dev = g_lrme_dev; + struct cam_node *node = v4l2_get_subdevdata(sd); + + if (!lrme_dev) { + CAM_ERR(CAM_LRME, "Invalid args"); + return -ENODEV; + } + + mutex_lock(&lrme_dev->lock); + if (lrme_dev->open_cnt <= 0) { + CAM_DBG(CAM_LRME, "LRME subdev is already closed"); + rc = -EINVAL; + goto end; + } + + lrme_dev->open_cnt--; + if (!node) { + CAM_ERR(CAM_LRME, "Node is NULL"); + rc = -EINVAL; + goto end; + } + + if (lrme_dev->open_cnt == 0) + cam_node_shutdown(node); + +end: + mutex_unlock(&lrme_dev->lock); + return rc; +} + +static const struct v4l2_subdev_internal_ops cam_lrme_subdev_internal_ops = { + .open = cam_lrme_dev_open, + .close = cam_lrme_dev_close, +}; + +static int cam_lrme_dev_probe(struct platform_device *pdev) +{ + int rc; + int i; + struct cam_hw_mgr_intf hw_mgr_intf; + struct cam_node *node; + + g_lrme_dev = kzalloc(sizeof(struct cam_lrme_dev), GFP_KERNEL); + if (!g_lrme_dev) { + CAM_ERR(CAM_LRME, "No memory"); + return -ENOMEM; + } + g_lrme_dev->sd.internal_ops = &cam_lrme_subdev_internal_ops; + + mutex_init(&g_lrme_dev->lock); + + rc = cam_subdev_probe(&g_lrme_dev->sd, pdev, CAM_LRME_DEV_NAME, + CAM_LRME_DEVICE_TYPE); + if (rc) { + CAM_ERR(CAM_LRME, "LRME cam_subdev_probe failed"); + goto free_mem; + } + node = (struct cam_node *)g_lrme_dev->sd.token; + + rc = cam_lrme_hw_mgr_init(&hw_mgr_intf, cam_lrme_dev_buf_done_cb); + if (rc) { + CAM_ERR(CAM_LRME, "Can not initialized LRME HW manager"); + goto unregister; + } + + for (i = 0; i < CAM_CTX_MAX; i++) { + rc = cam_lrme_context_init(&g_lrme_dev->lrme_ctx[i], + &g_lrme_dev->ctx[i], + &node->hw_mgr_intf, i); + if (rc) { + CAM_ERR(CAM_LRME, "LRME context init failed"); + goto deinit_ctx; + } + } + + rc = cam_node_init(node, &hw_mgr_intf, g_lrme_dev->ctx, CAM_CTX_MAX, + CAM_LRME_DEV_NAME); + if (rc) { + CAM_ERR(CAM_LRME, "LRME node init failed"); + goto deinit_ctx; + } + + CAM_DBG(CAM_LRME, "%s probe complete", g_lrme_dev->sd.name); + + return 0; + +deinit_ctx: + for (--i; i >= 0; i--) { + if (cam_lrme_context_deinit(&g_lrme_dev->lrme_ctx[i])) + CAM_ERR(CAM_LRME, "LRME context %d deinit failed", i); + } +unregister: + if (cam_subdev_remove(&g_lrme_dev->sd)) + CAM_ERR(CAM_LRME, "Failed in subdev remove"); +free_mem: + kfree(g_lrme_dev); + + return rc; +} + +static int cam_lrme_dev_remove(struct platform_device *pdev) +{ + int i; + int rc = 0; + + for (i = 0; i < CAM_CTX_MAX; i++) { + rc = cam_lrme_context_deinit(&g_lrme_dev->lrme_ctx[i]); + if (rc) + CAM_ERR(CAM_LRME, "LRME context %d deinit failed", i); + } + + rc = cam_lrme_hw_mgr_deinit(); + if (rc) + CAM_ERR(CAM_LRME, "Failed in hw mgr deinit, rc=%d", rc); + + rc = cam_subdev_remove(&g_lrme_dev->sd); + if (rc) + CAM_ERR(CAM_LRME, "Unregister failed"); + + mutex_destroy(&g_lrme_dev->lock); + kfree(g_lrme_dev); + g_lrme_dev = NULL; + + return rc; +} + +static const struct of_device_id cam_lrme_dt_match[] = { + { + .compatible = "qcom,cam-lrme" + }, + {} +}; + +static struct platform_driver cam_lrme_driver = { + .probe = cam_lrme_dev_probe, + .remove = cam_lrme_dev_remove, + .driver = { + .name = "cam_lrme", + .owner = THIS_MODULE, + .of_match_table = cam_lrme_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_lrme_dev_init_module(void) +{ + return platform_driver_register(&cam_lrme_driver); +} + +static void __exit cam_lrme_dev_exit_module(void) +{ + platform_driver_unregister(&cam_lrme_driver); +} + +module_init(cam_lrme_dev_init_module); +module_exit(cam_lrme_dev_exit_module); +MODULE_DESCRIPTION("MSM LRME driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/Makefile b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..e5b3990a54de81f702b43f39b6197f3eabf0a12c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += lrme_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_lrme_hw_mgr.o diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c new file mode 100644 index 0000000000000000000000000000000000000000..3d1857f05b633ce16a3499eac8c22aae45a69abd --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c @@ -0,0 +1,1202 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include "cam_io_util.h" +#include "cam_soc_util.h" +#include "cam_mem_mgr_api.h" +#include "cam_smmu_api.h" +#include "cam_packet_util.h" +#include "cam_lrme_context.h" +#include "cam_lrme_hw_intf.h" +#include "cam_lrme_hw_core.h" +#include "cam_lrme_hw_soc.h" +#include "cam_lrme_hw_mgr_intf.h" +#include "cam_lrme_hw_mgr.h" + +static struct cam_lrme_hw_mgr g_lrme_hw_mgr; + +static int cam_lrme_mgr_util_reserve_device(struct cam_lrme_hw_mgr *hw_mgr, + struct cam_lrme_acquire_args *lrme_acquire_args) +{ + int i, index = 0; + uint32_t min_ctx = UINT_MAX; + struct cam_lrme_device *hw_device = NULL; + + mutex_lock(&hw_mgr->hw_mgr_mutex); + if (!hw_mgr->device_count) { + mutex_unlock(&hw_mgr->hw_mgr_mutex); + CAM_ERR(CAM_LRME, "No device is registered"); + return -EINVAL; + } + + for (i = 0; i < hw_mgr->device_count && i < CAM_LRME_HW_MAX; i++) { + hw_device = &hw_mgr->hw_device[i]; + if (!hw_device->num_context) { + index = i; + break; + } + if (hw_device->num_context < min_ctx) { + min_ctx = hw_device->num_context; + index = i; + } + } + + hw_device = &hw_mgr->hw_device[index]; + hw_device->num_context++; + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + CAM_DBG(CAM_LRME, "reserve device index %d", index); + + return index; +} + +static int cam_lrme_mgr_util_get_device(struct cam_lrme_hw_mgr *hw_mgr, + uint32_t device_index, struct cam_lrme_device **hw_device) +{ + if (!hw_mgr) { + CAM_ERR(CAM_LRME, "invalid params hw_mgr %pK", hw_mgr); + return -EINVAL; + } + + if (device_index >= CAM_LRME_HW_MAX) { + CAM_ERR(CAM_LRME, "Wrong device index %d", device_index); + return -EINVAL; + } + + *hw_device = &hw_mgr->hw_device[device_index]; + + return 0; +} + +static int cam_lrme_mgr_util_packet_validate(struct cam_packet *packet, + size_t remain_len) +{ + struct cam_cmd_buf_desc *cmd_desc = NULL; + int i, rc; + + if (!packet) { + CAM_ERR(CAM_LRME, "Invalid args"); + return -EINVAL; + } + + CAM_DBG(CAM_LRME, "Packet request=%d, op_code=0x%x, size=%d, flags=%d", + packet->header.request_id, packet->header.op_code, + packet->header.size, packet->header.flags); + CAM_DBG(CAM_LRME, + "Packet cmdbuf(offset=%d, num=%d) io(offset=%d, num=%d)", + packet->cmd_buf_offset, packet->num_cmd_buf, + packet->io_configs_offset, packet->num_io_configs); + CAM_DBG(CAM_LRME, + "Packet Patch(offset=%d, num=%d) kmd(offset=%d, num=%d)", + packet->patch_offset, packet->num_patches, + packet->kmd_cmd_buf_offset, packet->kmd_cmd_buf_index); + + if (cam_packet_util_validate_packet(packet, remain_len)) { + CAM_ERR(CAM_LRME, "invalid packet:%d %d %d %d %d", + packet->kmd_cmd_buf_index, + packet->num_cmd_buf, packet->cmd_buf_offset, + packet->io_configs_offset, packet->header.size); + return -EINVAL; + } + + if (!packet->num_io_configs) { + CAM_ERR(CAM_LRME, "no io configs"); + return -EINVAL; + } + + cmd_desc = (struct cam_cmd_buf_desc *)((uint8_t *)&packet->payload + + packet->cmd_buf_offset); + + for (i = 0; i < packet->num_cmd_buf; i++) { + if (!cmd_desc[i].length) + continue; + + CAM_DBG(CAM_LRME, + "CmdBuf[%d] hdl=%d, offset=%d, size=%d, len=%d, type=%d, meta_data=%d", + i, + cmd_desc[i].mem_handle, cmd_desc[i].offset, + cmd_desc[i].size, cmd_desc[i].length, cmd_desc[i].type, + cmd_desc[i].meta_data); + + rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]); + if (rc) { + CAM_ERR(CAM_LRME, "Invalid cmd buffer %d", i); + return rc; + } + } + + return 0; +} + +static int cam_lrme_mgr_util_prepare_io_buffer(int32_t iommu_hdl, + struct cam_hw_prepare_update_args *prepare, + struct cam_lrme_hw_io_buffer *input_buf, + struct cam_lrme_hw_io_buffer *output_buf, uint32_t io_buf_size) +{ + int rc = -EINVAL; + uint32_t num_in_buf, num_out_buf, i, j, plane; + struct cam_buf_io_cfg *io_cfg; + dma_addr_t io_addr[CAM_PACKET_MAX_PLANES]; + size_t size; + + num_in_buf = 0; + num_out_buf = 0; + io_cfg = (struct cam_buf_io_cfg *)((uint8_t *) + &prepare->packet->payload + + prepare->packet->io_configs_offset); + + for (i = 0; i < prepare->packet->num_io_configs; i++) { + CAM_DBG(CAM_LRME, + "IOConfig[%d] : handle[%d] Dir[%d] Res[%d] Fence[%d], Format[%d]", + i, io_cfg[i].mem_handle[0], io_cfg[i].direction, + io_cfg[i].resource_type, + io_cfg[i].fence, io_cfg[i].format); + + memset(io_addr, 0, sizeof(io_addr)); + for (plane = 0; plane < CAM_PACKET_MAX_PLANES; plane++) { + if (!io_cfg[i].mem_handle[plane]) + break; + + rc = cam_mem_get_io_buf(io_cfg[i].mem_handle[plane], + iommu_hdl, &io_addr[plane], &size); + if (rc) { + CAM_ERR(CAM_LRME, "Cannot get io buf for %d %d", + plane, rc); + return -ENOMEM; + } + + if ((size_t)io_cfg[i].offsets[plane] >= size) { + CAM_ERR(CAM_LRME, "Invalid plane offset: %zu", + (size_t)io_cfg[i].offsets[plane]); + return -EINVAL; + } + + io_addr[plane] += io_cfg[i].offsets[plane]; + + CAM_DBG(CAM_LRME, "IO Address[%d][%d] : %llu", + io_cfg[i].direction, plane, io_addr[plane]); + } + + switch (io_cfg[i].direction) { + case CAM_BUF_INPUT: { + if (num_in_buf >= io_buf_size) { + CAM_ERR(CAM_LRME, + "Invalid number of buffers %d %d %d", + num_in_buf, num_out_buf, io_buf_size); + return -EINVAL; + } + prepare->in_map_entries[num_in_buf].resource_handle = + io_cfg[i].resource_type; + prepare->in_map_entries[num_in_buf].sync_id = + io_cfg[i].fence; + + input_buf[num_in_buf].valid = true; + for (j = 0; j < plane; j++) + input_buf[num_in_buf].io_addr[j] = io_addr[j]; + input_buf[num_in_buf].num_plane = plane; + input_buf[num_in_buf].io_cfg = &io_cfg[i]; + + num_in_buf++; + break; + } + case CAM_BUF_OUTPUT: { + if (num_out_buf >= io_buf_size) { + CAM_ERR(CAM_LRME, + "Invalid number of buffers %d %d %d", + num_in_buf, num_out_buf, io_buf_size); + return -EINVAL; + } + prepare->out_map_entries[num_out_buf].resource_handle = + io_cfg[i].resource_type; + prepare->out_map_entries[num_out_buf].sync_id = + io_cfg[i].fence; + + output_buf[num_out_buf].valid = true; + for (j = 0; j < plane; j++) + output_buf[num_out_buf].io_addr[j] = io_addr[j]; + output_buf[num_out_buf].num_plane = plane; + output_buf[num_out_buf].io_cfg = &io_cfg[i]; + + num_out_buf++; + break; + } + default: + CAM_ERR(CAM_LRME, "Unsupported io direction %d", + io_cfg[i].direction); + return -EINVAL; + } + } + prepare->num_in_map_entries = num_in_buf; + prepare->num_out_map_entries = num_out_buf; + + return 0; +} + +static int cam_lrme_mgr_util_prepare_hw_update_entries( + struct cam_lrme_hw_mgr *hw_mgr, + struct cam_hw_prepare_update_args *prepare, + struct cam_lrme_hw_cmd_config_args *config_args, + struct cam_kmd_buf_info *kmd_buf_info) +{ + int i, rc = 0; + struct cam_lrme_device *hw_device = NULL; + uint32_t *kmd_buf_addr; + uint32_t num_entry; + uint32_t kmd_buf_max_size; + uint32_t kmd_buf_used_bytes = 0; + struct cam_hw_update_entry *hw_entry; + struct cam_cmd_buf_desc *cmd_desc = NULL; + + hw_device = config_args->hw_device; + if (!hw_device) { + CAM_ERR(CAM_LRME, "Invalid hw_device"); + return -EINVAL; + } + + kmd_buf_addr = (uint32_t *)((uint8_t *)kmd_buf_info->cpu_addr + + kmd_buf_info->used_bytes); + kmd_buf_max_size = kmd_buf_info->size - kmd_buf_info->used_bytes; + + config_args->cmd_buf_addr = kmd_buf_addr; + config_args->size = kmd_buf_max_size; + config_args->config_buf_size = 0; + + if (hw_device->hw_intf.hw_ops.process_cmd) { + rc = hw_device->hw_intf.hw_ops.process_cmd( + hw_device->hw_intf.hw_priv, + CAM_LRME_HW_CMD_PREPARE_HW_UPDATE, + config_args, + sizeof(struct cam_lrme_hw_cmd_config_args)); + if (rc) { + CAM_ERR(CAM_LRME, + "Failed in CMD_PREPARE_HW_UPDATE %d", rc); + return rc; + } + } else { + CAM_ERR(CAM_LRME, "Can't find handle function"); + return -EINVAL; + } + + kmd_buf_used_bytes += config_args->config_buf_size; + + if (!kmd_buf_used_bytes || (kmd_buf_used_bytes > kmd_buf_max_size)) { + CAM_ERR(CAM_LRME, "Invalid kmd used bytes %d (%d)", + kmd_buf_used_bytes, kmd_buf_max_size); + return -ENOMEM; + } + + hw_entry = prepare->hw_update_entries; + num_entry = 0; + + if (config_args->config_buf_size) { + if ((num_entry + 1) >= prepare->max_hw_update_entries) { + CAM_ERR(CAM_LRME, "Insufficient HW entries :%d %d", + num_entry, prepare->max_hw_update_entries); + return -EINVAL; + } + + hw_entry[num_entry].handle = kmd_buf_info->handle; + hw_entry[num_entry].len = config_args->config_buf_size; + hw_entry[num_entry].offset = kmd_buf_info->offset; + + kmd_buf_info->used_bytes += config_args->config_buf_size; + kmd_buf_info->offset += config_args->config_buf_size; + num_entry++; + } + + cmd_desc = (struct cam_cmd_buf_desc *)((uint8_t *) + &prepare->packet->payload + prepare->packet->cmd_buf_offset); + + for (i = 0; i < prepare->packet->num_cmd_buf; i++) { + if (!cmd_desc[i].length) + continue; + + if ((num_entry + 1) >= prepare->max_hw_update_entries) { + CAM_ERR(CAM_LRME, "Exceed max num of entry"); + return -EINVAL; + } + + hw_entry[num_entry].handle = cmd_desc[i].mem_handle; + hw_entry[num_entry].len = cmd_desc[i].length; + hw_entry[num_entry].offset = cmd_desc[i].offset; + num_entry++; + } + prepare->num_hw_update_entries = num_entry; + + CAM_DBG(CAM_LRME, "FinalConfig : hw_entries=%d, Sync(in=%d, out=%d)", + prepare->num_hw_update_entries, prepare->num_in_map_entries, + prepare->num_out_map_entries); + + return rc; +} + +static void cam_lrme_mgr_util_put_frame_req( + struct list_head *src_list, + struct list_head *list, + spinlock_t *lock) +{ + spin_lock(lock); + list_add_tail(list, src_list); + spin_unlock(lock); +} + +static int cam_lrme_mgr_util_get_frame_req( + struct list_head *src_list, + struct cam_lrme_frame_request **frame_req, + spinlock_t *lock) +{ + int rc = 0; + struct cam_lrme_frame_request *req_ptr = NULL; + + spin_lock(lock); + if (!list_empty(src_list)) { + req_ptr = list_first_entry(src_list, + struct cam_lrme_frame_request, frame_list); + list_del_init(&req_ptr->frame_list); + } else { + rc = -ENOENT; + } + *frame_req = req_ptr; + spin_unlock(lock); + + return rc; +} + + +static int cam_lrme_mgr_util_submit_req(void *priv, void *data) +{ + struct cam_lrme_device *hw_device; + struct cam_lrme_hw_mgr *hw_mgr; + struct cam_lrme_frame_request *frame_req = NULL; + struct cam_lrme_hw_submit_args submit_args; + struct cam_lrme_mgr_work_data *work_data; + int rc; + int req_prio = 0; + + if (!priv) { + CAM_ERR(CAM_LRME, "worker doesn't have private data"); + return -EINVAL; + } + + hw_mgr = (struct cam_lrme_hw_mgr *)priv; + work_data = (struct cam_lrme_mgr_work_data *)data; + hw_device = work_data->hw_device; + + rc = cam_lrme_mgr_util_get_frame_req( + &hw_device->frame_pending_list_high, &frame_req, + &hw_device->high_req_lock); + + if (!frame_req) { + rc = cam_lrme_mgr_util_get_frame_req( + &hw_device->frame_pending_list_normal, &frame_req, + &hw_device->normal_req_lock); + if (frame_req) + req_prio = 1; + } + + if (!frame_req) { + CAM_DBG(CAM_LRME, "No pending request"); + return 0; + } + + if (hw_device->hw_intf.hw_ops.process_cmd) { + submit_args.hw_update_entries = frame_req->hw_update_entries; + submit_args.num_hw_update_entries = + frame_req->num_hw_update_entries; + submit_args.frame_req = frame_req; + + rc = hw_device->hw_intf.hw_ops.process_cmd( + hw_device->hw_intf.hw_priv, + CAM_LRME_HW_CMD_SUBMIT, + &submit_args, sizeof(struct cam_lrme_hw_submit_args)); + + if (rc == -EBUSY) + CAM_DBG(CAM_LRME, "device busy"); + else if (rc) + CAM_ERR(CAM_LRME, "submit request failed rc %d", rc); + if (rc) { + req_prio == 0 ? spin_lock(&hw_device->high_req_lock) : + spin_lock(&hw_device->normal_req_lock); + list_add(&frame_req->frame_list, + (req_prio == 0 ? + &hw_device->frame_pending_list_high : + &hw_device->frame_pending_list_normal)); + req_prio == 0 ? spin_unlock(&hw_device->high_req_lock) : + spin_unlock(&hw_device->normal_req_lock); + } + if (rc == -EBUSY) + rc = 0; + } else { + req_prio == 0 ? spin_lock(&hw_device->high_req_lock) : + spin_lock(&hw_device->normal_req_lock); + list_add(&frame_req->frame_list, + (req_prio == 0 ? + &hw_device->frame_pending_list_high : + &hw_device->frame_pending_list_normal)); + req_prio == 0 ? spin_unlock(&hw_device->high_req_lock) : + spin_unlock(&hw_device->normal_req_lock); + rc = -EINVAL; + } + + CAM_DBG(CAM_LRME, "End of submit, rc %d", rc); + + return rc; +} + +static int cam_lrme_mgr_util_schedule_frame_req( + struct cam_lrme_hw_mgr *hw_mgr, struct cam_lrme_device *hw_device) +{ + int rc = 0; + struct crm_workq_task *task; + struct cam_lrme_mgr_work_data *work_data; + + task = cam_req_mgr_workq_get_task(hw_device->work); + if (!task) { + CAM_ERR(CAM_LRME, "Can not get task for worker"); + return -ENOMEM; + } + + work_data = (struct cam_lrme_mgr_work_data *)task->payload; + work_data->hw_device = hw_device; + + task->process_cb = cam_lrme_mgr_util_submit_req; + CAM_DBG(CAM_LRME, "enqueue submit task"); + rc = cam_req_mgr_workq_enqueue_task(task, hw_mgr, CRM_TASK_PRIORITY_0); + + return rc; +} + +static int cam_lrme_mgr_util_release(struct cam_lrme_hw_mgr *hw_mgr, + uint32_t device_index) +{ + int rc = 0; + struct cam_lrme_device *hw_device; + + rc = cam_lrme_mgr_util_get_device(hw_mgr, device_index, &hw_device); + if (rc) { + CAM_ERR(CAM_LRME, "Error in getting device %d", rc); + return rc; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + hw_device->num_context--; + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + return rc; +} + +static int cam_lrme_mgr_cb(void *data, + struct cam_lrme_hw_cb_args *cb_args) +{ + struct cam_lrme_hw_mgr *hw_mgr = &g_lrme_hw_mgr; + int rc = 0; + bool frame_abort = true; + struct cam_lrme_frame_request *frame_req; + struct cam_lrme_device *hw_device; + + if (!data || !cb_args) { + CAM_ERR(CAM_LRME, "Invalid input args"); + return -EINVAL; + } + + hw_device = (struct cam_lrme_device *)data; + frame_req = cb_args->frame_req; + + if (cb_args->cb_type & CAM_LRME_CB_PUT_FRAME) { + memset(frame_req, 0x0, sizeof(*frame_req)); + INIT_LIST_HEAD(&frame_req->frame_list); + cam_lrme_mgr_util_put_frame_req(&hw_mgr->frame_free_list, + &frame_req->frame_list, + &hw_mgr->free_req_lock); + cb_args->cb_type &= ~CAM_LRME_CB_PUT_FRAME; + frame_req = NULL; + } + + if (cb_args->cb_type & CAM_LRME_CB_COMP_REG_UPDATE) { + cb_args->cb_type &= ~CAM_LRME_CB_COMP_REG_UPDATE; + CAM_DBG(CAM_LRME, "Reg update"); + } + + if (!frame_req) + return rc; + + if (cb_args->cb_type & CAM_LRME_CB_BUF_DONE) { + cb_args->cb_type &= ~CAM_LRME_CB_BUF_DONE; + frame_abort = false; + } else if (cb_args->cb_type & CAM_LRME_CB_ERROR) { + cb_args->cb_type &= ~CAM_LRME_CB_ERROR; + frame_abort = true; + } else { + CAM_ERR(CAM_LRME, "Wrong cb type %d, req %lld", + cb_args->cb_type, frame_req->req_id); + return -EINVAL; + } + + if (hw_mgr->event_cb) { + struct cam_hw_done_event_data buf_data; + + buf_data.request_id = frame_req->req_id; + CAM_DBG(CAM_LRME, "frame req %llu, frame_abort %d", + frame_req->req_id, frame_abort); + rc = hw_mgr->event_cb(frame_req->ctxt_to_hw_map, + frame_abort, &buf_data); + } else { + CAM_ERR(CAM_LRME, "No cb function"); + } + memset(frame_req, 0x0, sizeof(*frame_req)); + INIT_LIST_HEAD(&frame_req->frame_list); + cam_lrme_mgr_util_put_frame_req(&hw_mgr->frame_free_list, + &frame_req->frame_list, + &hw_mgr->free_req_lock); + + rc = cam_lrme_mgr_util_schedule_frame_req(hw_mgr, hw_device); + + return rc; +} + +static int cam_lrme_mgr_get_caps(void *hw_mgr_priv, void *hw_get_caps_args) +{ + int rc = 0; + struct cam_lrme_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_query_cap_cmd *args = hw_get_caps_args; + + if (sizeof(struct cam_lrme_query_cap_cmd) != args->size) { + CAM_ERR(CAM_LRME, + "sizeof(struct cam_query_cap_cmd) = %zu, args->size = %d", + sizeof(struct cam_query_cap_cmd), args->size); + return -EFAULT; + } + + if (copy_to_user(u64_to_user_ptr(args->caps_handle), + &(hw_mgr->lrme_caps), + sizeof(struct cam_lrme_query_cap_cmd))) { + CAM_ERR(CAM_LRME, "copy to user failed"); + return -EFAULT; + } + + return rc; +} + +static int cam_lrme_mgr_hw_acquire(void *hw_mgr_priv, void *hw_acquire_args) +{ + struct cam_lrme_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_acquire_args *args = + (struct cam_hw_acquire_args *)hw_acquire_args; + struct cam_lrme_acquire_args lrme_acquire_args; + uintptr_t device_index; + + if (!hw_mgr_priv || !args) { + CAM_ERR(CAM_LRME, + "Invalid input params hw_mgr_priv %pK, acquire_args %pK", + hw_mgr_priv, args); + return -EINVAL; + } + + if (copy_from_user(&lrme_acquire_args, + (void __user *)args->acquire_info, + sizeof(struct cam_lrme_acquire_args))) { + CAM_ERR(CAM_LRME, "Failed to copy acquire args from user"); + return -EFAULT; + } + + device_index = cam_lrme_mgr_util_reserve_device(hw_mgr, + &lrme_acquire_args); + CAM_DBG(CAM_LRME, "Get device id %llu", device_index); + + if (device_index >= hw_mgr->device_count) { + CAM_ERR(CAM_LRME, "Get wrong device id %lu", device_index); + return -EINVAL; + } + + /* device_index is the right 4 bit in ctxt_to_hw_map */ + args->ctxt_to_hw_map = (void *)device_index; + + return 0; +} + +static int cam_lrme_mgr_hw_release(void *hw_mgr_priv, void *hw_release_args) +{ + int rc = 0; + struct cam_lrme_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_release_args *args = + (struct cam_hw_release_args *)hw_release_args; + uint64_t device_index; + + if (!hw_mgr_priv || !hw_release_args) { + CAM_ERR(CAM_LRME, "Invalid arguments %pK, %pK", + hw_mgr_priv, hw_release_args); + return -EINVAL; + } + + device_index = CAM_LRME_DECODE_DEVICE_INDEX(args->ctxt_to_hw_map); + if (device_index >= hw_mgr->device_count) { + CAM_ERR(CAM_LRME, "Invalid device index %llu", device_index); + return -EPERM; + } + + rc = cam_lrme_mgr_util_release(hw_mgr, device_index); + if (rc) + CAM_ERR(CAM_LRME, "Failed in release device, rc=%d", rc); + + return rc; +} + +static int cam_lrme_mgr_hw_dump(void *hw_mgr_priv, void *hw_dump_args) +{ + struct cam_hw_dump_args *dump_args = hw_dump_args; + struct cam_lrme_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_lrme_device *hw_device; + int rc = 0; + uint32_t device_index; + struct cam_lrme_hw_dump_args lrme_dump_args; + + device_index = CAM_LRME_DECODE_DEVICE_INDEX(dump_args->ctxt_to_hw_map); + if (device_index >= hw_mgr->device_count) { + CAM_ERR(CAM_LRME, "Invalid device index %d", device_index); + return -EPERM; + } + + CAM_DBG(CAM_LRME, "Start device index %d", device_index); + + rc = cam_lrme_mgr_util_get_device(hw_mgr, device_index, &hw_device); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to get hw device"); + return rc; + } + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &lrme_dump_args.cpu_addr, + &lrme_dump_args.buf_len); + if (rc) { + CAM_ERR(CAM_LRME, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + return rc; + } + lrme_dump_args.offset = dump_args->offset; + lrme_dump_args.request_id = dump_args->request_id; + + rc = hw_device->hw_intf.hw_ops.process_cmd( + hw_device->hw_intf.hw_priv, + CAM_LRME_HW_CMD_DUMP, + &lrme_dump_args, + sizeof(struct cam_lrme_hw_dump_args)); + CAM_DBG(CAM_LRME, "Offset before %zu after %zu", + dump_args->offset, lrme_dump_args.offset); + dump_args->offset = lrme_dump_args.offset; + cam_mem_put_cpu_buf(dump_args->buf_handle); + return rc; +} + +static int cam_lrme_mgr_hw_flush(void *hw_mgr_priv, void *hw_flush_args) +{ int rc = 0, i; + struct cam_lrme_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_flush_args *args; + struct cam_lrme_device *hw_device; + struct cam_lrme_frame_request *frame_req = NULL, *req_to_flush = NULL; + struct cam_lrme_frame_request **req_list = NULL; + uint32_t device_index; + struct cam_lrme_hw_flush_args lrme_flush_args; + uint32_t priority; + + if (!hw_mgr_priv || !hw_flush_args) { + CAM_ERR(CAM_LRME, "Invalid args %pK %pK", + hw_mgr_priv, hw_flush_args); + return -EINVAL; + } + + args = (struct cam_hw_flush_args *)hw_flush_args; + device_index = ((uintptr_t)args->ctxt_to_hw_map & 0xF); + if (device_index >= hw_mgr->device_count) { + CAM_ERR(CAM_LRME, "Invalid device index %d", device_index); + return -EPERM; + } + + rc = cam_lrme_mgr_util_get_device(hw_mgr, device_index, &hw_device); + if (rc) { + CAM_ERR(CAM_LRME, "Error in getting device %d", rc); + goto end; + } + + req_list = (struct cam_lrme_frame_request **)args->flush_req_pending; + for (i = 0; i < args->num_req_pending; i++) { + frame_req = req_list[i]; + memset(frame_req, 0x0, sizeof(*frame_req)); + cam_lrme_mgr_util_put_frame_req(&hw_mgr->frame_free_list, + &frame_req->frame_list, &hw_mgr->free_req_lock); + } + + req_list = (struct cam_lrme_frame_request **)args->flush_req_active; + for (i = 0; i < args->num_req_active; i++) { + frame_req = req_list[i]; + priority = CAM_LRME_DECODE_PRIORITY(args->ctxt_to_hw_map); + spin_lock((priority == CAM_LRME_PRIORITY_HIGH) ? + &hw_device->high_req_lock : + &hw_device->normal_req_lock); + if (!list_empty(&frame_req->frame_list)) { + list_del_init(&frame_req->frame_list); + cam_lrme_mgr_util_put_frame_req( + &hw_mgr->frame_free_list, + &frame_req->frame_list, + &hw_mgr->free_req_lock); + } else + req_to_flush = frame_req; + spin_unlock((priority == CAM_LRME_PRIORITY_HIGH) ? + &hw_device->high_req_lock : + &hw_device->normal_req_lock); + } + if (!req_to_flush) + goto end; + if (hw_device->hw_intf.hw_ops.flush) { + lrme_flush_args.ctxt_to_hw_map = req_to_flush->ctxt_to_hw_map; + lrme_flush_args.flush_type = args->flush_type; + lrme_flush_args.req_to_flush = req_to_flush; + rc = hw_device->hw_intf.hw_ops.flush(hw_device->hw_intf.hw_priv, + &lrme_flush_args, + sizeof(lrme_flush_args)); + if (rc) { + CAM_ERR(CAM_LRME, "Failed in HW Stop %d", rc); + goto end; + } + } else { + CAM_ERR(CAM_LRME, "No stop ops"); + goto end; + } + +end: + return rc; +} + + +static int cam_lrme_mgr_hw_start(void *hw_mgr_priv, void *hw_start_args) +{ + int rc = 0; + struct cam_lrme_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_start_args *args = + (struct cam_hw_start_args *)hw_start_args; + struct cam_lrme_device *hw_device; + uint32_t device_index; + + if (!hw_mgr || !args) { + CAM_ERR(CAM_LRME, "Invalid input params"); + return -EINVAL; + } + + device_index = CAM_LRME_DECODE_DEVICE_INDEX(args->ctxt_to_hw_map); + if (device_index >= hw_mgr->device_count) { + CAM_ERR(CAM_LRME, "Invalid device index %d", device_index); + return -EPERM; + } + + CAM_DBG(CAM_LRME, "Start device index %d", device_index); + + rc = cam_lrme_mgr_util_get_device(hw_mgr, device_index, &hw_device); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to get hw device"); + return rc; + } + + if (hw_device->hw_intf.hw_ops.start) { + rc = hw_device->hw_intf.hw_ops.start( + hw_device->hw_intf.hw_priv, NULL, 0); + } else { + CAM_ERR(CAM_LRME, "Invalid start function"); + return -EINVAL; + } + + rc = hw_device->hw_intf.hw_ops.process_cmd( + hw_device->hw_intf.hw_priv, + CAM_LRME_HW_CMD_DUMP_REGISTER, + &g_lrme_hw_mgr.debugfs_entry.dump_register, + sizeof(bool)); + + return rc; +} + +static int cam_lrme_mgr_hw_stop(void *hw_mgr_priv, void *stop_args) +{ + int rc = 0; + struct cam_lrme_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_stop_args *args = + (struct cam_hw_stop_args *)stop_args; + struct cam_lrme_device *hw_device; + uint32_t device_index; + + if (!hw_mgr_priv || !stop_args) { + CAM_ERR(CAM_LRME, "Invalid arguments"); + return -EINVAL; + } + + device_index = CAM_LRME_DECODE_DEVICE_INDEX(args->ctxt_to_hw_map); + if (device_index >= hw_mgr->device_count) { + CAM_ERR(CAM_LRME, "Invalid device index %d", device_index); + return -EPERM; + } + + CAM_DBG(CAM_LRME, "Stop device index %d", device_index); + + rc = cam_lrme_mgr_util_get_device(hw_mgr, device_index, &hw_device); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to get hw device"); + return rc; + } + + if (hw_device->hw_intf.hw_ops.stop) { + rc = hw_device->hw_intf.hw_ops.stop( + hw_device->hw_intf.hw_priv, NULL, 0); + if (rc) { + CAM_ERR(CAM_LRME, "Failed in HW stop %d", rc); + goto end; + } + } + +end: + return rc; +} + +static int cam_lrme_mgr_hw_prepare_update(void *hw_mgr_priv, + void *hw_prepare_update_args) +{ + int rc = 0, i; + struct cam_lrme_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_prepare_update_args *args = + (struct cam_hw_prepare_update_args *)hw_prepare_update_args; + struct cam_lrme_device *hw_device; + struct cam_kmd_buf_info kmd_buf; + struct cam_lrme_hw_cmd_config_args config_args; + struct cam_lrme_frame_request *frame_req = NULL; + uint32_t device_index; + + if (!hw_mgr_priv || !hw_prepare_update_args) { + CAM_ERR(CAM_LRME, "Invalid args %pK %pK", + hw_mgr_priv, hw_prepare_update_args); + return -EINVAL; + } + + device_index = CAM_LRME_DECODE_DEVICE_INDEX(args->ctxt_to_hw_map); + if (device_index >= hw_mgr->device_count) { + CAM_ERR(CAM_LRME, "Invalid device index %d", device_index); + return -EPERM; + } + + rc = cam_lrme_mgr_util_get_device(hw_mgr, device_index, &hw_device); + if (rc) { + CAM_ERR(CAM_LRME, "Error in getting device %d", rc); + goto error; + } + + rc = cam_lrme_mgr_util_packet_validate(args->packet, args->remain_len); + if (rc) { + CAM_ERR(CAM_LRME, "Error in packet validation %d", rc); + goto error; + } + + rc = cam_packet_util_get_kmd_buffer(args->packet, &kmd_buf); + if (rc) { + CAM_ERR(CAM_LRME, "Error in get kmd buf buffer %d", rc); + goto error; + } + + CAM_DBG(CAM_LRME, + "KMD Buf : hdl=%d, cpu_addr=%pK, offset=%d, size=%d, used=%d", + kmd_buf.handle, kmd_buf.cpu_addr, kmd_buf.offset, + kmd_buf.size, kmd_buf.used_bytes); + + rc = cam_packet_util_process_patches(args->packet, + hw_mgr->device_iommu.non_secure, hw_mgr->device_iommu.secure); + if (rc) { + CAM_ERR(CAM_LRME, "Patch packet failed, rc=%d", rc); + return rc; + } + + memset(&config_args, 0, sizeof(config_args)); + config_args.hw_device = hw_device; + + rc = cam_lrme_mgr_util_prepare_io_buffer( + hw_mgr->device_iommu.non_secure, args, + config_args.input_buf, config_args.output_buf, + CAM_LRME_MAX_IO_BUFFER); + if (rc) { + CAM_ERR(CAM_LRME, "Error in prepare IO Buf %d", rc); + goto error; + } + /* Check port number */ + if (args->num_in_map_entries == 0 || args->num_out_map_entries == 0) { + CAM_ERR(CAM_LRME, "Error in port number in %d, out %d", + args->num_in_map_entries, args->num_out_map_entries); + rc = -EINVAL; + goto error; + } + + rc = cam_lrme_mgr_util_prepare_hw_update_entries(hw_mgr, args, + &config_args, &kmd_buf); + if (rc) { + CAM_ERR(CAM_LRME, "Error in hw update entries %d", rc); + goto error; + } + + rc = cam_lrme_mgr_util_get_frame_req(&hw_mgr->frame_free_list, + &frame_req, &hw_mgr->free_req_lock); + if (rc || !frame_req) { + CAM_ERR(CAM_LRME, "Can not get free frame request"); + goto error; + } + + frame_req->ctxt_to_hw_map = args->ctxt_to_hw_map; + frame_req->req_id = args->packet->header.request_id; + frame_req->hw_device = hw_device; + frame_req->num_hw_update_entries = args->num_hw_update_entries; + for (i = 0; i < args->num_hw_update_entries; i++) + frame_req->hw_update_entries[i] = args->hw_update_entries[i]; + + args->priv = frame_req; + + CAM_DBG(CAM_LRME, "FramePrepare : Frame[%lld]", frame_req->req_id); + + return 0; + +error: + return rc; +} + +static int cam_lrme_mgr_hw_config(void *hw_mgr_priv, + void *hw_config_args) +{ + int rc = 0; + struct cam_lrme_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_config_args *args = + (struct cam_hw_config_args *)hw_config_args; + struct cam_lrme_frame_request *frame_req; + struct cam_lrme_device *hw_device = NULL; + enum cam_lrme_hw_mgr_ctx_priority priority; + + if (!hw_mgr_priv || !hw_config_args) { + CAM_ERR(CAM_LRME, "Invalid arguments, hw_mgr %pK, config %pK", + hw_mgr_priv, hw_config_args); + return -EINVAL; + } + + if (!args->num_hw_update_entries) { + CAM_ERR(CAM_LRME, "No hw update entries"); + return -EINVAL; + } + + frame_req = (struct cam_lrme_frame_request *)args->priv; + if (!frame_req) { + CAM_ERR(CAM_LRME, "No frame request"); + return -EINVAL; + } + + hw_device = frame_req->hw_device; + if (!hw_device) + return -EINVAL; + + priority = CAM_LRME_DECODE_PRIORITY(args->ctxt_to_hw_map); + if (priority == CAM_LRME_PRIORITY_HIGH) { + cam_lrme_mgr_util_put_frame_req( + &hw_device->frame_pending_list_high, + &frame_req->frame_list, &hw_device->high_req_lock); + } else { + cam_lrme_mgr_util_put_frame_req( + &hw_device->frame_pending_list_normal, + &frame_req->frame_list, &hw_device->normal_req_lock); + } + + CAM_DBG(CAM_LRME, "schedule req %llu", frame_req->req_id); + rc = cam_lrme_mgr_util_schedule_frame_req(hw_mgr, hw_device); + + return rc; +} + +static int cam_lrme_mgr_create_debugfs_entry(void) +{ + int rc = 0; + + g_lrme_hw_mgr.debugfs_entry.dentry = + debugfs_create_dir("camera_lrme", NULL); + if (!g_lrme_hw_mgr.debugfs_entry.dentry) { + CAM_ERR(CAM_LRME, "failed to create dentry"); + return -ENOMEM; + } + + if (!debugfs_create_bool("dump_register", + 0644, + g_lrme_hw_mgr.debugfs_entry.dentry, + &g_lrme_hw_mgr.debugfs_entry.dump_register)) { + CAM_ERR(CAM_LRME, "failed to create dump register entry"); + rc = -ENOMEM; + goto err; + } + + return rc; + +err: + debugfs_remove_recursive(g_lrme_hw_mgr.debugfs_entry.dentry); + g_lrme_hw_mgr.debugfs_entry.dentry = NULL; + return rc; +} + + +int cam_lrme_mgr_register_device( + struct cam_hw_intf *lrme_hw_intf, + struct cam_iommu_handle *device_iommu, + struct cam_iommu_handle *cdm_iommu) +{ + struct cam_lrme_device *hw_device; + char buf[128]; + int i, rc; + + hw_device = &g_lrme_hw_mgr.hw_device[lrme_hw_intf->hw_idx]; + + g_lrme_hw_mgr.device_iommu = *device_iommu; + g_lrme_hw_mgr.cdm_iommu = *cdm_iommu; + + memcpy(&hw_device->hw_intf, lrme_hw_intf, sizeof(struct cam_hw_intf)); + + spin_lock_init(&hw_device->high_req_lock); + spin_lock_init(&hw_device->normal_req_lock); + INIT_LIST_HEAD(&hw_device->frame_pending_list_high); + INIT_LIST_HEAD(&hw_device->frame_pending_list_normal); + + rc = snprintf(buf, sizeof(buf), "cam_lrme_device_submit_worker%d", + lrme_hw_intf->hw_idx); + CAM_DBG(CAM_LRME, "Create submit workq for %s", buf); + rc = cam_req_mgr_workq_create(buf, + CAM_LRME_WORKQ_NUM_TASK, + &hw_device->work, CRM_WORKQ_USAGE_NON_IRQ, + 0); + if (rc) { + CAM_ERR(CAM_LRME, + "Unable to create a worker, rc=%d", rc); + return rc; + } + + for (i = 0; i < CAM_LRME_WORKQ_NUM_TASK; i++) + hw_device->work->task.pool[i].payload = + &hw_device->work_data[i]; + + if (hw_device->hw_intf.hw_ops.process_cmd) { + struct cam_lrme_hw_cmd_set_cb cb_args; + + cb_args.cam_lrme_hw_mgr_cb = cam_lrme_mgr_cb; + cb_args.data = hw_device; + + rc = hw_device->hw_intf.hw_ops.process_cmd( + hw_device->hw_intf.hw_priv, + CAM_LRME_HW_CMD_REGISTER_CB, + &cb_args, sizeof(cb_args)); + if (rc) { + CAM_ERR(CAM_LRME, "Register cb failed"); + goto destroy_workqueue; + } + CAM_DBG(CAM_LRME, "cb registered"); + } + + if (hw_device->hw_intf.hw_ops.get_hw_caps) { + rc = hw_device->hw_intf.hw_ops.get_hw_caps( + hw_device->hw_intf.hw_priv, &hw_device->hw_caps, + sizeof(hw_device->hw_caps)); + if (rc) + CAM_ERR(CAM_LRME, "Get caps failed"); + } else { + CAM_ERR(CAM_LRME, "No get_hw_caps function"); + goto destroy_workqueue; + } + g_lrme_hw_mgr.lrme_caps.dev_caps[lrme_hw_intf->hw_idx] = + hw_device->hw_caps; + g_lrme_hw_mgr.device_count++; + g_lrme_hw_mgr.lrme_caps.device_iommu = g_lrme_hw_mgr.device_iommu; + g_lrme_hw_mgr.lrme_caps.cdm_iommu = g_lrme_hw_mgr.cdm_iommu; + g_lrme_hw_mgr.lrme_caps.num_devices = g_lrme_hw_mgr.device_count; + + hw_device->valid = true; + + CAM_DBG(CAM_LRME, "device registration done"); + return 0; + +destroy_workqueue: + cam_req_mgr_workq_destroy(&hw_device->work); + + return rc; +} + +int cam_lrme_mgr_deregister_device(int device_index) +{ + struct cam_lrme_device *hw_device; + + hw_device = &g_lrme_hw_mgr.hw_device[device_index]; + cam_req_mgr_workq_destroy(&hw_device->work); + memset(hw_device, 0x0, sizeof(struct cam_lrme_device)); + g_lrme_hw_mgr.device_count--; + + return 0; +} + +int cam_lrme_hw_mgr_deinit(void) +{ + mutex_destroy(&g_lrme_hw_mgr.hw_mgr_mutex); + memset(&g_lrme_hw_mgr, 0x0, sizeof(g_lrme_hw_mgr)); + + return 0; +} + +int cam_lrme_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, + cam_hw_event_cb_func cam_lrme_dev_buf_done_cb) +{ + int i, rc = 0; + struct cam_lrme_frame_request *frame_req; + + if (!hw_mgr_intf) + return -EINVAL; + + CAM_DBG(CAM_LRME, "device count %d", g_lrme_hw_mgr.device_count); + if (g_lrme_hw_mgr.device_count > CAM_LRME_HW_MAX) { + CAM_ERR(CAM_LRME, "Invalid count of devices"); + return -EINVAL; + } + + memset(hw_mgr_intf, 0, sizeof(*hw_mgr_intf)); + + mutex_init(&g_lrme_hw_mgr.hw_mgr_mutex); + spin_lock_init(&g_lrme_hw_mgr.free_req_lock); + INIT_LIST_HEAD(&g_lrme_hw_mgr.frame_free_list); + + /* Init hw mgr frame requests and add to free list */ + for (i = 0; i < CAM_CTX_REQ_MAX * CAM_CTX_MAX; i++) { + frame_req = &g_lrme_hw_mgr.frame_req[i]; + + memset(frame_req, 0x0, sizeof(*frame_req)); + INIT_LIST_HEAD(&frame_req->frame_list); + + list_add_tail(&frame_req->frame_list, + &g_lrme_hw_mgr.frame_free_list); + } + + hw_mgr_intf->hw_mgr_priv = &g_lrme_hw_mgr; + hw_mgr_intf->hw_get_caps = cam_lrme_mgr_get_caps; + hw_mgr_intf->hw_acquire = cam_lrme_mgr_hw_acquire; + hw_mgr_intf->hw_release = cam_lrme_mgr_hw_release; + hw_mgr_intf->hw_start = cam_lrme_mgr_hw_start; + hw_mgr_intf->hw_stop = cam_lrme_mgr_hw_stop; + hw_mgr_intf->hw_prepare_update = cam_lrme_mgr_hw_prepare_update; + hw_mgr_intf->hw_config = cam_lrme_mgr_hw_config; + hw_mgr_intf->hw_read = NULL; + hw_mgr_intf->hw_write = NULL; + hw_mgr_intf->hw_close = NULL; + hw_mgr_intf->hw_flush = cam_lrme_mgr_hw_flush; + + g_lrme_hw_mgr.event_cb = cam_lrme_dev_buf_done_cb; + hw_mgr_intf->hw_dump = cam_lrme_mgr_hw_dump; + + cam_lrme_mgr_create_debugfs_entry(); + + CAM_DBG(CAM_LRME, "Hw mgr init done"); + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.h b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.h new file mode 100644 index 0000000000000000000000000000000000000000..bc77e726d3e6f1e2df9313af1f22f46711a6e0a8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_LRME_HW_MGR_H_ +#define _CAM_LRME_HW_MGR_H_ + +#include +#include + +#include +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "cam_hw_mgr_intf.h" +#include "cam_req_mgr_workq.h" +#include "cam_lrme_hw_intf.h" +#include "cam_context.h" + +#define CAM_LRME_HW_MAX 1 +#define CAM_LRME_WORKQ_NUM_TASK 10 + +#define CAM_LRME_DECODE_DEVICE_INDEX(ctxt_to_hw_map) \ + ((uintptr_t)ctxt_to_hw_map & 0xF) + +#define CAM_LRME_DECODE_PRIORITY(ctxt_to_hw_map) \ + (((uintptr_t)ctxt_to_hw_map & 0xF0) >> 4) + +#define CAM_LRME_DECODE_CTX_INDEX(ctxt_to_hw_map) \ + ((uint64_t)(uintptr_t)ctxt_to_hw_map >> CAM_LRME_CTX_INDEX_SHIFT) + +/** + * enum cam_lrme_hw_mgr_ctx_priority + * + * CAM_LRME_PRIORITY_HIGH : High priority client + * CAM_LRME_PRIORITY_NORMAL : Normal priority client + */ +enum cam_lrme_hw_mgr_ctx_priority { + CAM_LRME_PRIORITY_HIGH, + CAM_LRME_PRIORITY_NORMAL, +}; + +/** + * struct cam_lrme_mgr_work_data : HW Mgr work data + * + * @hw_device : Pointer to the hw device + */ +struct cam_lrme_mgr_work_data { + struct cam_lrme_device *hw_device; +}; + +/** + * struct cam_lrme_debugfs_entry : debugfs entry struct + * + * @dentry : entry of debugfs + * @dump_register : flag to dump registers + */ +struct cam_lrme_debugfs_entry { + struct dentry *dentry; + bool dump_register; +}; + +/** + * struct cam_lrme_device : LRME HW device + * + * @hw_caps : HW device's capabilities + * @hw_intf : HW device's interface information + * @num_context : Number of contexts using this device + * @valid : Whether this device is valid + * @work : HW device's work queue + * @work_data : HW device's work data + * @frame_pending_list_high : High priority request queue + * @frame_pending_list_normal : Normal priority request queue + * @high_req_lock : Spinlock of high priority queue + * @normal_req_lock : Spinlock of normal priority queue + */ +struct cam_lrme_device { + struct cam_lrme_dev_cap hw_caps; + struct cam_hw_intf hw_intf; + uint32_t num_context; + bool valid; + struct cam_req_mgr_core_workq *work; + struct cam_lrme_mgr_work_data work_data[CAM_LRME_WORKQ_NUM_TASK]; + struct list_head frame_pending_list_high; + struct list_head frame_pending_list_normal; + spinlock_t high_req_lock; + spinlock_t normal_req_lock; +}; + +/** + * struct cam_lrme_hw_mgr : LRME HW manager + * + * @device_count : Number of HW devices + * @frame_free_list : List of free frame request + * @hw_mgr_mutex : Mutex to protect HW manager data + * @free_req_lock :Spinlock to protect frame_free_list + * @hw_device : List of HW devices + * @device_iommu : Device iommu + * @cdm_iommu : cdm iommu + * @frame_req : List of frame request to use + * @lrme_caps : LRME capabilities + * @event_cb : IRQ callback function + * @debugfs_entry : debugfs entry to set debug prop + */ +struct cam_lrme_hw_mgr { + uint32_t device_count; + struct list_head frame_free_list; + struct mutex hw_mgr_mutex; + spinlock_t free_req_lock; + struct cam_lrme_device hw_device[CAM_LRME_HW_MAX]; + struct cam_iommu_handle device_iommu; + struct cam_iommu_handle cdm_iommu; + struct cam_lrme_frame_request frame_req[CAM_CTX_REQ_MAX * CAM_CTX_MAX]; + struct cam_lrme_query_cap_cmd lrme_caps; + cam_hw_event_cb_func event_cb; + struct cam_lrme_debugfs_entry debugfs_entry; +}; + +int cam_lrme_mgr_register_device(struct cam_hw_intf *lrme_hw_intf, + struct cam_iommu_handle *device_iommu, + struct cam_iommu_handle *cdm_iommu); +int cam_lrme_mgr_deregister_device(int device_index); + +#endif /* _CAM_LRME_HW_MGR_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr_intf.h b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..df6ea0eac798e6ececae363b30a50103fe58f56e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr_intf.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_LRME_HW_MGR_INTF_H_ +#define _CAM_LRME_HW_MGR_INTF_H_ + +#include + +#include "cam_debug_util.h" +#include "cam_hw_mgr_intf.h" + +int cam_lrme_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, + cam_hw_event_cb_func cam_lrme_dev_buf_done_cb); +int cam_lrme_hw_mgr_deinit(void); + +#endif /* _CAM_LRME_HW_MGR_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/Makefile b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..42871c0295ce8f5b68e1eafb36a90d399c3bfe72 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal0 +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_lrme_hw_dev.o cam_lrme_hw_core.o cam_lrme_hw_soc.o diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c new file mode 100644 index 0000000000000000000000000000000000000000..dc4df1c579313aa73ae713c9fb0e4f9fd55ec47a --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c @@ -0,0 +1,1438 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_lrme_hw_core.h" +#include "cam_lrme_hw_soc.h" +#include "cam_smmu_api.h" + +static void cam_lrme_dump_registers(void __iomem *base) +{ + /* dump the clc registers */ + cam_io_dump(base, 0x60, (0xc0 - 0x60) / 0x4); + /* dump the fe and we registers */ + cam_io_dump(base, 0x200, (0x29c - 0x200) / 0x4); + cam_io_dump(base, 0x2f0, (0x330 - 0x2f0) / 0x4); + cam_io_dump(base, 0x500, (0x5b4 - 0x500) / 0x4); + cam_io_dump(base, 0x700, (0x778 - 0x700) / 0x4); + cam_io_dump(base, 0x800, (0x878 - 0x800) / 0x4); + /* dump lrme sw registers, interrupts */ + cam_io_dump(base, 0x900, (0x928 - 0x900) / 0x4); +} + +static int cam_lrme_dump_regs_to_buf( + struct cam_lrme_frame_request *req, + struct cam_hw_info *lrme_hw, + struct cam_lrme_hw_dump_args *dump_args) +{ + int i; + uint8_t *dst; + uint32_t *addr, *start; + uint32_t num_reg, min_len; + size_t remain_len; + struct cam_hw_soc_info *soc_info; + struct cam_lrme_hw_dump_header *hdr; + + if (!lrme_hw || !req || !dump_args) { + CAM_ERR(CAM_LRME, "Invalid params %pK, %pK, %pK", + lrme_hw, req, dump_args); + return -EINVAL; + } + soc_info = &lrme_hw->soc_info; + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_LRME, "dump buffer overshoot len %zu offset %zu", + dump_args->buf_len, dump_args->offset); + return -ENOSPC; + } + remain_len = dump_args->buf_len - dump_args->offset; + min_len = sizeof(struct cam_lrme_hw_dump_header) + + soc_info->reg_map[0].size + sizeof(uint32_t); + + if (remain_len < min_len) { + CAM_WARN(CAM_LRME, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return -ENOSPC; + } + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_lrme_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_LRME_HW_DUMP_TAG_MAX_LEN, + "LRME_REG:"); + hdr->word_size = sizeof(uint32_t); + addr = (uint32_t *)(dst + sizeof(struct cam_lrme_hw_dump_header)); + start = addr; + *addr++ = soc_info->index; + num_reg = soc_info->reg_map[0].size/4; + for (i = 0; i < num_reg; i++) { + *addr++ = soc_info->mem_block[0]->start + (i*4); + *addr++ = cam_io_r(soc_info->reg_map[0].mem_base + (i*4)); + } + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_lrme_hw_dump_header); + CAM_DBG(CAM_LRME, "offset %zu", dump_args->offset); + return 0; +} + +static int cam_lrme_hw_dump( + struct cam_hw_info *lrme_hw, + struct cam_lrme_hw_dump_args *dump_args) +{ + uint8_t *dst; + ktime_t cur_time; + size_t remain_len; + uint32_t min_len; + uint64_t diff; + uint64_t *addr, *start; + struct timespec64 cur_ts; + struct timespec64 req_ts; + struct cam_lrme_core *lrme_core; + struct cam_lrme_frame_request *req = NULL; + struct cam_lrme_hw_dump_header *hdr; + + mutex_lock(&lrme_hw->hw_mutex); + if (lrme_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_DBG(CAM_LRME, "LRME HW is in off state"); + mutex_unlock(&lrme_hw->hw_mutex); + return 0; + } + + lrme_core = (struct cam_lrme_core *)lrme_hw->core_info; + + if (lrme_core->req_submit && + lrme_core->req_submit->req_id == dump_args->request_id) + req = lrme_core->req_submit; + else if (lrme_core->req_proc && + lrme_core->req_proc->req_id == dump_args->request_id) + req = lrme_core->req_proc; + + if (!req) { + CAM_DBG(CAM_LRME, "LRME req %lld not with hw", + dump_args->request_id); + mutex_unlock(&lrme_hw->hw_mutex); + return 0; + } + + cur_time = ktime_get(); + diff = ktime_us_delta(req->submit_timestamp, cur_time); + cur_ts = ktime_to_timespec64(cur_time); + req_ts = ktime_to_timespec64(req->submit_timestamp); + + if (diff < CAM_LRME_RESPONSE_TIME_THRESHOLD) { + CAM_INFO(CAM_LRME, "No error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + mutex_unlock(&lrme_hw->hw_mutex); + return 0; + } + + CAM_INFO(CAM_LRME, "Error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_LRME, "dump buffer overshoot len %zu offset %zu", + dump_args->buf_len, dump_args->offset); + mutex_unlock(&lrme_hw->hw_mutex); + return 0; + } + + remain_len = dump_args->buf_len - dump_args->offset; + min_len = sizeof(struct cam_lrme_hw_dump_header) + + (CAM_LRME_HW_DUMP_NUM_WORDS * sizeof(uint64_t)); + + if (remain_len < min_len) { + CAM_WARN(CAM_LRME, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + mutex_unlock(&lrme_hw->hw_mutex); + return 0; + } + + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_lrme_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_LRME_HW_DUMP_TAG_MAX_LEN, + "LRME_REQ:"); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + sizeof(struct cam_lrme_hw_dump_header)); + start = addr; + *addr++ = req->req_id; + *addr++ = req_ts.tv_sec; + *addr++ = req_ts.tv_nsec/NSEC_PER_USEC; + *addr++ = cur_ts.tv_sec; + *addr++ = cur_ts.tv_nsec/NSEC_PER_USEC; + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_lrme_hw_dump_header); + cam_lrme_dump_regs_to_buf(req, lrme_hw, dump_args); + mutex_unlock(&lrme_hw->hw_mutex); + return 0; +} + +static void cam_lrme_cdm_write_reg_val_pair(uint32_t *buffer, + uint32_t *index, uint32_t reg_offset, uint32_t reg_value) +{ + buffer[(*index)++] = reg_offset; + buffer[(*index)++] = reg_value; +} + +static void cam_lrme_hw_util_fill_fe_reg(struct cam_lrme_hw_io_buffer *io_buf, + uint32_t index, uint32_t *reg_val_pair, uint32_t *num_cmd, + struct cam_lrme_hw_info *hw_info) +{ + uint32_t reg_val; + + /* 1. config buffer size */ + if (io_buf->io_cfg->format == CAM_FORMAT_PLAIN16_10) + reg_val = io_buf->io_cfg->planes[0].width * 2; + else + reg_val = io_buf->io_cfg->planes[0].width; + reg_val |= (io_buf->io_cfg->planes[0].height << 16); + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, + hw_info->bus_rd_reg.bus_client_reg[index].rd_buffer_size, + reg_val); + + CAM_DBG(CAM_LRME, + "width %d", io_buf->io_cfg->planes[0].width); + CAM_DBG(CAM_LRME, + "height %d", io_buf->io_cfg->planes[0].height); + + /* 2. config image address */ + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, + hw_info->bus_rd_reg.bus_client_reg[index].addr_image, + io_buf->io_addr[0]); + + CAM_DBG(CAM_LRME, "io addr %llu", io_buf->io_addr[0]); + + /* 3. config stride */ + reg_val = io_buf->io_cfg->planes[0].plane_stride; + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, + hw_info->bus_rd_reg.bus_client_reg[index].rd_stride, + reg_val); + + CAM_DBG(CAM_LRME, "plane_stride %d", + io_buf->io_cfg->planes[0].plane_stride); + + /* 4. enable client */ + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, + hw_info->bus_rd_reg.bus_client_reg[index].core_cfg, 0x1); + + /* 5. unpack_cfg */ + if (io_buf->io_cfg->format == CAM_FORMAT_PD10) + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, + hw_info->bus_rd_reg.bus_client_reg[index].unpack_cfg_0, + 0x0); + else if (io_buf->io_cfg->format == CAM_FORMAT_Y_ONLY || + io_buf->io_cfg->format == CAM_FORMAT_PLAIN8 || + io_buf->io_cfg->format == CAM_FORMAT_NV12 || + io_buf->io_cfg->format == CAM_FORMAT_NV21) + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, + hw_info->bus_rd_reg.bus_client_reg[index].unpack_cfg_0, + 0x1); + else if (io_buf->io_cfg->format == CAM_FORMAT_PLAIN16_10) + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, + hw_info->bus_rd_reg.bus_client_reg[index].unpack_cfg_0, + 0x22); + else + CAM_ERR(CAM_LRME, "Unsupported format %d", + io_buf->io_cfg->format); +} + +static void cam_lrme_hw_util_fill_we_reg(struct cam_lrme_hw_io_buffer *io_buf, + uint32_t index, uint32_t *reg_val_pair, uint32_t *num_cmd, + struct cam_lrme_hw_info *hw_info) +{ + /* config client mode */ + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, + hw_info->bus_wr_reg.bus_client_reg[index].cfg, + 0x1); + + /* image address */ + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, + hw_info->bus_wr_reg.bus_client_reg[index].addr_image, + io_buf->io_addr[0]); + CAM_DBG(CAM_LRME, "io addr %llu", io_buf->io_addr[0]); + + /* buffer width and height */ + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, + hw_info->bus_wr_reg.bus_client_reg[index].buffer_width_cfg, + io_buf->io_cfg->planes[0].width); + CAM_DBG(CAM_LRME, "width %d", io_buf->io_cfg->planes[0].width); + + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, + hw_info->bus_wr_reg.bus_client_reg[index].buffer_height_cfg, + io_buf->io_cfg->planes[0].height); + CAM_DBG(CAM_LRME, "height %d", io_buf->io_cfg->planes[0].height); + + /* packer cfg */ + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, + hw_info->bus_wr_reg.bus_client_reg[index].packer_cfg, + (index == 0) ? 0x1 : 0x5); + + /* client stride */ + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, num_cmd, + hw_info->bus_wr_reg.bus_client_reg[index].wr_stride, + io_buf->io_cfg->planes[0].plane_stride); + CAM_DBG(CAM_LRME, "plane_stride %d", + io_buf->io_cfg->planes[0].plane_stride); +} + + +static int cam_lrme_hw_util_process_config_hw(struct cam_hw_info *lrme_hw, + struct cam_lrme_hw_cmd_config_args *config_args) +{ + int i; + struct cam_hw_soc_info *soc_info = &lrme_hw->soc_info; + struct cam_lrme_cdm_info *hw_cdm_info; + uint32_t *cmd_buf_addr = config_args->cmd_buf_addr; + uint32_t reg_val_pair[CAM_LRME_MAX_REG_PAIR_NUM]; + struct cam_lrme_hw_io_buffer *io_buf; + struct cam_lrme_hw_info *hw_info = + ((struct cam_lrme_core *)lrme_hw->core_info)->hw_info; + uint32_t num_cmd = 0; + uint32_t size; + uint32_t mem_base, available_size = config_args->size; + uint32_t output_res_mask = 0, input_res_mask = 0; + + + if (!cmd_buf_addr) { + CAM_ERR(CAM_LRME, "Invalid input args"); + return -EINVAL; + } + + hw_cdm_info = + ((struct cam_lrme_core *)lrme_hw->core_info)->hw_cdm_info; + + for (i = 0; i < CAM_LRME_MAX_IO_BUFFER; i++) { + io_buf = &config_args->input_buf[i]; + + if (io_buf->valid == false) + break; + + if (io_buf->io_cfg->direction != CAM_BUF_INPUT) { + CAM_ERR(CAM_LRME, "Incorrect direction %d %d", + io_buf->io_cfg->direction, CAM_BUF_INPUT); + return -EINVAL; + } + CAM_DBG(CAM_LRME, + "resource_type %d", io_buf->io_cfg->resource_type); + + switch (io_buf->io_cfg->resource_type) { + case CAM_LRME_IO_TYPE_TAR: + cam_lrme_hw_util_fill_fe_reg(io_buf, 0, reg_val_pair, + &num_cmd, hw_info); + + input_res_mask |= CAM_LRME_INPUT_PORT_TYPE_TAR; + break; + case CAM_LRME_IO_TYPE_REF: + cam_lrme_hw_util_fill_fe_reg(io_buf, 1, reg_val_pair, + &num_cmd, hw_info); + + input_res_mask |= CAM_LRME_INPUT_PORT_TYPE_REF; + break; + default: + CAM_ERR(CAM_LRME, "wrong resource_type %d", + io_buf->io_cfg->resource_type); + return -EINVAL; + } + } + + for (i = 0; i < CAM_LRME_BUS_RD_MAX_CLIENTS; i++) + if (!((input_res_mask >> i) & 0x1)) + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, &num_cmd, + hw_info->bus_rd_reg.bus_client_reg[i].core_cfg, + 0x0); + + for (i = 0; i < CAM_LRME_MAX_IO_BUFFER; i++) { + io_buf = &config_args->output_buf[i]; + + if (io_buf->valid == false) + break; + + if (io_buf->io_cfg->direction != CAM_BUF_OUTPUT) { + CAM_ERR(CAM_LRME, "Incorrect direction %d %d", + io_buf->io_cfg->direction, CAM_BUF_INPUT); + return -EINVAL; + } + + CAM_DBG(CAM_LRME, "resource_type %d", + io_buf->io_cfg->resource_type); + switch (io_buf->io_cfg->resource_type) { + case CAM_LRME_IO_TYPE_DS2: + cam_lrme_hw_util_fill_we_reg(io_buf, 0, reg_val_pair, + &num_cmd, hw_info); + + output_res_mask |= CAM_LRME_OUTPUT_PORT_TYPE_DS2; + break; + case CAM_LRME_IO_TYPE_RES: + cam_lrme_hw_util_fill_we_reg(io_buf, 1, reg_val_pair, + &num_cmd, hw_info); + + output_res_mask |= CAM_LRME_OUTPUT_PORT_TYPE_RES; + break; + + default: + CAM_ERR(CAM_LRME, "wrong resource_type %d", + io_buf->io_cfg->resource_type); + return -EINVAL; + } + } + + for (i = 0; i < CAM_LRME_BUS_RD_MAX_CLIENTS; i++) + if (!((output_res_mask >> i) & 0x1)) + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, &num_cmd, + hw_info->bus_wr_reg.bus_client_reg[i].cfg, 0x0); + + if (output_res_mask) { + /* write composite mask */ + cam_lrme_cdm_write_reg_val_pair(reg_val_pair, &num_cmd, + hw_info->bus_wr_reg.common_reg.composite_mask_0, + output_res_mask); + } + + size = hw_cdm_info->cdm_ops->cdm_required_size_changebase(); + if ((size * 4) > available_size) { + CAM_ERR(CAM_LRME, "buf size:%d is not sufficient, expected: %d", + available_size, size); + return -EINVAL; + } + + mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE(soc_info, CAM_LRME_BASE_IDX); + + hw_cdm_info->cdm_ops->cdm_write_changebase(cmd_buf_addr, mem_base); + cmd_buf_addr += size; + available_size -= (size * 4); + + size = hw_cdm_info->cdm_ops->cdm_required_size_reg_random( + num_cmd / 2); + + if ((size * 4) > available_size) { + CAM_ERR(CAM_LRME, "buf size:%d is not sufficient, expected: %d", + available_size, size); + return -ENOMEM; + } + + hw_cdm_info->cdm_ops->cdm_write_regrandom(cmd_buf_addr, num_cmd / 2, + reg_val_pair); + cmd_buf_addr += size; + available_size -= (size * 4); + + config_args->config_buf_size = + config_args->size - available_size; + + return 0; +} + +static int cam_lrme_hw_util_submit_go(struct cam_hw_info *lrme_hw) +{ + struct cam_lrme_core *lrme_core; + struct cam_hw_soc_info *soc_info; + struct cam_lrme_hw_info *hw_info; + + lrme_core = (struct cam_lrme_core *)lrme_hw->core_info; + hw_info = lrme_core->hw_info; + soc_info = &lrme_hw->soc_info; + + cam_io_w_mb(0x1, soc_info->reg_map[0].mem_base + + hw_info->bus_rd_reg.common_reg.cmd); + + return 0; +} + +static int cam_lrme_hw_util_reset(struct cam_hw_info *lrme_hw, + uint32_t reset_type) +{ + struct cam_lrme_core *lrme_core; + struct cam_hw_soc_info *soc_info = &lrme_hw->soc_info; + struct cam_lrme_hw_info *hw_info; + long time_left; + + lrme_core = lrme_hw->core_info; + hw_info = lrme_core->hw_info; + + switch (reset_type) { + case CAM_LRME_HW_RESET_TYPE_HW_RESET: + reinit_completion(&lrme_core->reset_complete); + cam_io_w_mb(0x1, soc_info->reg_map[0].mem_base + + hw_info->titan_reg.top_rst_cmd); + time_left = wait_for_completion_timeout( + &lrme_core->reset_complete, + msecs_to_jiffies(CAM_LRME_HW_RESET_TIMEOUT)); + if (time_left <= 0) { + CAM_ERR(CAM_LRME, + "HW reset wait failed time_left=%ld", + time_left); + return -ETIMEDOUT; + } + break; + case CAM_LRME_HW_RESET_TYPE_SW_RESET: + cam_io_w_mb(0x3, soc_info->reg_map[0].mem_base + + hw_info->bus_wr_reg.common_reg.sw_reset); + cam_io_w_mb(0x3, soc_info->reg_map[0].mem_base + + hw_info->bus_rd_reg.common_reg.sw_reset); + reinit_completion(&lrme_core->reset_complete); + cam_io_w_mb(0x2, soc_info->reg_map[0].mem_base + + hw_info->titan_reg.top_rst_cmd); + time_left = wait_for_completion_timeout( + &lrme_core->reset_complete, + msecs_to_jiffies(CAM_LRME_HW_RESET_TIMEOUT)); + if (time_left <= 0) { + CAM_ERR(CAM_LRME, + "SW reset wait failed time_left=%ld", + time_left); + return -ETIMEDOUT; + } + break; + } + + return 0; +} + +int cam_lrme_hw_util_get_caps(struct cam_hw_info *lrme_hw, + struct cam_lrme_dev_cap *hw_caps) +{ + struct cam_hw_soc_info *soc_info = &lrme_hw->soc_info; + struct cam_lrme_hw_info *hw_info = + ((struct cam_lrme_core *)lrme_hw->core_info)->hw_info; + uint32_t reg_value; + + if (!hw_info) { + CAM_ERR(CAM_LRME, "Invalid hw info data"); + return -EINVAL; + } + + reg_value = cam_io_r_mb(soc_info->reg_map[0].mem_base + + hw_info->clc_reg.clc_hw_version); + hw_caps->clc_hw_version.gen = + CAM_BITS_MASK_SHIFT(reg_value, 0xf0000000, 0x1C); + hw_caps->clc_hw_version.rev = + CAM_BITS_MASK_SHIFT(reg_value, 0xfff0000, 0x10); + hw_caps->clc_hw_version.step = + CAM_BITS_MASK_SHIFT(reg_value, 0xffff, 0x0); + + reg_value = cam_io_r_mb(soc_info->reg_map[0].mem_base + + hw_info->bus_rd_reg.common_reg.hw_version); + hw_caps->bus_rd_hw_version.gen = + CAM_BITS_MASK_SHIFT(reg_value, 0xf0000000, 0x1C); + hw_caps->bus_rd_hw_version.rev = + CAM_BITS_MASK_SHIFT(reg_value, 0xfff0000, 0x10); + hw_caps->bus_rd_hw_version.step = + CAM_BITS_MASK_SHIFT(reg_value, 0xffff, 0x0); + + reg_value = cam_io_r_mb(soc_info->reg_map[0].mem_base + + hw_info->bus_wr_reg.common_reg.hw_version); + hw_caps->bus_wr_hw_version.gen = + CAM_BITS_MASK_SHIFT(reg_value, 0xf0000000, 0x1C); + hw_caps->bus_wr_hw_version.rev = + CAM_BITS_MASK_SHIFT(reg_value, 0xfff0000, 0x10); + hw_caps->bus_wr_hw_version.step = + CAM_BITS_MASK_SHIFT(reg_value, 0xffff, 0x0); + + reg_value = cam_io_r_mb(soc_info->reg_map[0].mem_base + + hw_info->titan_reg.top_hw_version); + hw_caps->top_hw_version.gen = + CAM_BITS_MASK_SHIFT(reg_value, 0xf0000000, 0x1C); + hw_caps->top_hw_version.rev = + CAM_BITS_MASK_SHIFT(reg_value, 0xfff0000, 0x10); + hw_caps->top_hw_version.step = + CAM_BITS_MASK_SHIFT(reg_value, 0xffff, 0x0); + + reg_value = cam_io_r_mb(soc_info->reg_map[0].mem_base + + hw_info->titan_reg.top_titan_version); + hw_caps->top_titan_version.gen = + CAM_BITS_MASK_SHIFT(reg_value, 0xf0000000, 0x1C); + hw_caps->top_titan_version.rev = + CAM_BITS_MASK_SHIFT(reg_value, 0xfff0000, 0x10); + hw_caps->top_titan_version.step = + CAM_BITS_MASK_SHIFT(reg_value, 0xffff, 0x0); + + return 0; +} + +static int cam_lrme_hw_util_submit_req(struct cam_lrme_core *lrme_core, + struct cam_lrme_frame_request *frame_req) +{ + struct cam_lrme_cdm_info *hw_cdm_info = + lrme_core->hw_cdm_info; + struct cam_cdm_bl_request *cdm_cmd = hw_cdm_info->cdm_cmd; + struct cam_hw_update_entry *cmd; + int i, rc = 0; + + if (frame_req->num_hw_update_entries > 0) { + cdm_cmd->cmd_arrary_count = frame_req->num_hw_update_entries; + cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE; + cdm_cmd->flag = false; + cdm_cmd->userdata = NULL; + cdm_cmd->cookie = 0; + cdm_cmd->gen_irq_arb = false; + + for (i = 0; i <= frame_req->num_hw_update_entries; i++) { + cmd = (frame_req->hw_update_entries + i); + cdm_cmd->cmd[i].bl_addr.mem_handle = cmd->handle; + cdm_cmd->cmd[i].offset = cmd->offset; + cdm_cmd->cmd[i].len = cmd->len; + cdm_cmd->cmd[i].arbitrate = false; + } + + rc = cam_cdm_submit_bls(hw_cdm_info->cdm_handle, cdm_cmd); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to submit cdm commands"); + return -EINVAL; + } + } else { + CAM_ERR(CAM_LRME, "No hw update entry"); + rc = -EINVAL; + } + + return rc; +} + +static int cam_lrme_hw_util_flush_ctx(struct cam_hw_info *lrme_hw, + void *ctxt_to_hw_map) +{ + int rc = -ENODEV; + struct cam_lrme_core *lrme_core = lrme_hw->core_info; + struct cam_lrme_hw_cb_args cb_args; + struct cam_lrme_frame_request *req_proc, *req_submit; + struct cam_lrme_hw_submit_args submit_args; + + rc = cam_lrme_hw_util_reset(lrme_hw, CAM_LRME_HW_RESET_TYPE_HW_RESET); + if (rc) { + CAM_ERR(CAM_LRME, "reset failed"); + return rc; + } + + lrme_core->state = CAM_LRME_CORE_STATE_IDLE; + req_proc = lrme_core->req_proc; + req_submit = lrme_core->req_submit; + lrme_core->req_proc = NULL; + lrme_core->req_submit = NULL; + + if (req_submit && req_submit->ctxt_to_hw_map == ctxt_to_hw_map) { + cb_args.cb_type = CAM_LRME_CB_PUT_FRAME; + cb_args.frame_req = req_submit; + if (lrme_core->hw_mgr_cb.cam_lrme_hw_mgr_cb) + lrme_core->hw_mgr_cb.cam_lrme_hw_mgr_cb( + lrme_core->hw_mgr_cb.data, &cb_args); + } else if (req_submit) { + submit_args.frame_req = req_submit; + submit_args.hw_update_entries = req_submit->hw_update_entries; + submit_args.num_hw_update_entries = + req_submit->num_hw_update_entries; + rc = cam_lrme_hw_util_submit_req(lrme_core, req_submit); + if (rc) + CAM_ERR(CAM_LRME, "Submit failed"); + lrme_core->req_submit = req_submit; + cam_lrme_hw_util_submit_go(lrme_hw); + lrme_core->state = CAM_LRME_CORE_STATE_REQ_PENDING; + } + + if (req_proc && req_proc->ctxt_to_hw_map == ctxt_to_hw_map) { + cb_args.cb_type = CAM_LRME_CB_PUT_FRAME; + cb_args.frame_req = req_proc; + if (lrme_core->hw_mgr_cb.cam_lrme_hw_mgr_cb) + lrme_core->hw_mgr_cb.cam_lrme_hw_mgr_cb( + lrme_core->hw_mgr_cb.data, &cb_args); + } else if (req_proc) { + submit_args.frame_req = req_proc; + submit_args.hw_update_entries = req_proc->hw_update_entries; + submit_args.num_hw_update_entries = + req_proc->num_hw_update_entries; + rc = cam_lrme_hw_util_submit_req(lrme_core, req_proc); + if (rc) + CAM_ERR(CAM_LRME, "Submit failed"); + lrme_core->req_submit = req_proc; + cam_lrme_hw_util_submit_go(lrme_hw); + lrme_core->state = CAM_LRME_CORE_STATE_REQ_PENDING; + } + + return rc; +} + +static int cam_lrme_hw_util_flush_req(struct cam_hw_info *lrme_hw, + struct cam_lrme_frame_request *req_to_flush) +{ + int rc = -ENODEV; + struct cam_lrme_core *lrme_core = lrme_hw->core_info; + struct cam_lrme_hw_cb_args cb_args; + struct cam_lrme_frame_request *req_proc, *req_submit; + struct cam_lrme_hw_submit_args submit_args; + + rc = cam_lrme_hw_util_reset(lrme_hw, CAM_LRME_HW_RESET_TYPE_HW_RESET); + if (rc) { + CAM_ERR(CAM_LRME, "reset failed"); + return rc; + } + + lrme_core->state = CAM_LRME_CORE_STATE_IDLE; + req_proc = lrme_core->req_proc; + req_submit = lrme_core->req_submit; + lrme_core->req_proc = NULL; + lrme_core->req_submit = NULL; + + if (req_submit && req_submit == req_to_flush) { + cb_args.cb_type = CAM_LRME_CB_PUT_FRAME; + cb_args.frame_req = req_submit; + if (lrme_core->hw_mgr_cb.cam_lrme_hw_mgr_cb) + lrme_core->hw_mgr_cb.cam_lrme_hw_mgr_cb( + lrme_core->hw_mgr_cb.data, &cb_args); + } else if (req_submit) { + submit_args.frame_req = req_submit; + submit_args.hw_update_entries = req_submit->hw_update_entries; + submit_args.num_hw_update_entries = + req_submit->num_hw_update_entries; + rc = cam_lrme_hw_util_submit_req(lrme_core, req_submit); + if (rc) + CAM_ERR(CAM_LRME, "Submit failed"); + lrme_core->req_submit = req_submit; + cam_lrme_hw_util_submit_go(lrme_hw); + lrme_core->state = CAM_LRME_CORE_STATE_REQ_PENDING; + } + + if (req_proc && req_proc == req_to_flush) { + cb_args.cb_type = CAM_LRME_CB_PUT_FRAME; + cb_args.frame_req = req_proc; + if (lrme_core->hw_mgr_cb.cam_lrme_hw_mgr_cb) + lrme_core->hw_mgr_cb.cam_lrme_hw_mgr_cb( + lrme_core->hw_mgr_cb.data, &cb_args); + } else if (req_proc) { + submit_args.frame_req = req_proc; + submit_args.hw_update_entries = req_proc->hw_update_entries; + submit_args.num_hw_update_entries = + req_proc->num_hw_update_entries; + rc = cam_lrme_hw_util_submit_req(lrme_core, req_proc); + if (rc) + CAM_ERR(CAM_LRME, "Submit failed"); + lrme_core->req_submit = req_proc; + cam_lrme_hw_util_submit_go(lrme_hw); + lrme_core->state = CAM_LRME_CORE_STATE_REQ_PENDING; + } + + return rc; +} + + +static int cam_lrme_hw_util_process_err(struct cam_hw_info *lrme_hw) +{ + struct cam_lrme_core *lrme_core = lrme_hw->core_info; + struct cam_lrme_frame_request *req_proc, *req_submit; + struct cam_lrme_hw_cb_args cb_args; + int rc; + + req_proc = lrme_core->req_proc; + req_submit = lrme_core->req_submit; + cb_args.cb_type = CAM_LRME_CB_ERROR; + + if ((lrme_core->state != CAM_LRME_CORE_STATE_PROCESSING) && + (lrme_core->state != CAM_LRME_CORE_STATE_REQ_PENDING) && + (lrme_core->state != CAM_LRME_CORE_STATE_REQ_PROC_PEND)) { + CAM_ERR(CAM_LRME, "Get error irq in wrong state %d", + lrme_core->state); + } + + cam_lrme_dump_registers(lrme_hw->soc_info.reg_map[0].mem_base); + + CAM_ERR_RATE_LIMIT(CAM_LRME, "Start recovery"); + lrme_core->state = CAM_LRME_CORE_STATE_RECOVERY; + rc = cam_lrme_hw_util_reset(lrme_hw, CAM_LRME_HW_RESET_TYPE_HW_RESET); + if (rc) + CAM_ERR(CAM_LRME, "Failed to reset"); + + lrme_core->req_proc = NULL; + lrme_core->req_submit = NULL; + if (!rc) + lrme_core->state = CAM_LRME_CORE_STATE_IDLE; + + cb_args.frame_req = req_proc; + lrme_core->hw_mgr_cb.cam_lrme_hw_mgr_cb(lrme_core->hw_mgr_cb.data, + &cb_args); + + cb_args.frame_req = req_submit; + lrme_core->hw_mgr_cb.cam_lrme_hw_mgr_cb(lrme_core->hw_mgr_cb.data, + &cb_args); + + return rc; +} + +static int cam_lrme_hw_util_process_reg_update( + struct cam_hw_info *lrme_hw, struct cam_lrme_hw_cb_args *cb_args) +{ + struct cam_lrme_core *lrme_core = lrme_hw->core_info; + int rc = 0; + + cb_args->cb_type |= CAM_LRME_CB_COMP_REG_UPDATE; + if (lrme_core->state == CAM_LRME_CORE_STATE_REQ_PENDING) { + lrme_core->state = CAM_LRME_CORE_STATE_PROCESSING; + } else { + CAM_ERR(CAM_LRME, "Reg update in wrong state %d", + lrme_core->state); + rc = cam_lrme_hw_util_process_err(lrme_hw); + if (rc) + CAM_ERR(CAM_LRME, "Failed to reset"); + return -EINVAL; + } + + lrme_core->req_proc = lrme_core->req_submit; + lrme_core->req_submit = NULL; + + if (lrme_core->dump_flag) + cam_lrme_dump_registers(lrme_hw->soc_info.reg_map[0].mem_base); + + return 0; +} + +static int cam_lrme_hw_util_process_idle( + struct cam_hw_info *lrme_hw, struct cam_lrme_hw_cb_args *cb_args) +{ + struct cam_lrme_core *lrme_core = lrme_hw->core_info; + int rc = 0; + + cb_args->cb_type |= CAM_LRME_CB_BUF_DONE; + switch (lrme_core->state) { + case CAM_LRME_CORE_STATE_REQ_PROC_PEND: + cam_lrme_hw_util_submit_go(lrme_hw); + lrme_core->state = CAM_LRME_CORE_STATE_REQ_PENDING; + break; + + case CAM_LRME_CORE_STATE_PROCESSING: + lrme_core->state = CAM_LRME_CORE_STATE_IDLE; + break; + + default: + CAM_ERR(CAM_LRME, "Idle in wrong state %d", + lrme_core->state); + rc = cam_lrme_hw_util_process_err(lrme_hw); + return rc; + } + cb_args->frame_req = lrme_core->req_proc; + lrme_core->req_proc = NULL; + + return 0; +} + +void cam_lrme_set_irq(struct cam_hw_info *lrme_hw, + enum cam_lrme_irq_set set) +{ + struct cam_hw_soc_info *soc_info = &lrme_hw->soc_info; + struct cam_lrme_core *lrme_core = lrme_hw->core_info; + struct cam_lrme_hw_info *hw_info = lrme_core->hw_info; + + switch (set) { + case CAM_LRME_IRQ_ENABLE: + cam_io_w_mb(0xFFFF, + soc_info->reg_map[0].mem_base + + hw_info->titan_reg.top_irq_mask); + cam_io_w_mb(0xFFFFF, + soc_info->reg_map[0].mem_base + + hw_info->bus_wr_reg.common_reg.irq_mask_0); + cam_io_w_mb(0xFFFFF, + soc_info->reg_map[0].mem_base + + hw_info->bus_wr_reg.common_reg.irq_mask_1); + cam_io_w_mb(0xFFFFF, + soc_info->reg_map[0].mem_base + + hw_info->bus_rd_reg.common_reg.irq_mask); + break; + + case CAM_LRME_IRQ_DISABLE: + cam_io_w_mb(0x0, + soc_info->reg_map[0].mem_base + + hw_info->titan_reg.top_irq_mask); + cam_io_w_mb(0x0, + soc_info->reg_map[0].mem_base + + hw_info->bus_wr_reg.common_reg.irq_mask_0); + cam_io_w_mb(0x0, + soc_info->reg_map[0].mem_base + + hw_info->bus_wr_reg.common_reg.irq_mask_1); + cam_io_w_mb(0x0, + soc_info->reg_map[0].mem_base + + hw_info->bus_rd_reg.common_reg.irq_mask); + break; + } +} + + +int cam_lrme_hw_process_irq(void *priv, void *data) +{ + struct cam_lrme_hw_work_data *work_data; + struct cam_hw_info *lrme_hw; + struct cam_lrme_core *lrme_core; + int rc = 0; + uint32_t top_irq_status, fe_irq_status; + uint32_t *we_irq_status; + struct cam_lrme_hw_cb_args cb_args; + + if (!data || !priv) { + CAM_ERR(CAM_LRME, "Invalid data %pK %pK", data, priv); + return -EINVAL; + } + + memset(&cb_args, 0, sizeof(struct cam_lrme_hw_cb_args)); + lrme_hw = (struct cam_hw_info *)priv; + work_data = (struct cam_lrme_hw_work_data *)data; + lrme_core = (struct cam_lrme_core *)lrme_hw->core_info; + top_irq_status = work_data->top_irq_status; + fe_irq_status = work_data->fe_irq_status; + we_irq_status = work_data->we_irq_status; + + CAM_DBG(CAM_LRME, + "top status %x, fe status %x, we status0 %x, we status1 %x", + top_irq_status, fe_irq_status, we_irq_status[0], + we_irq_status[1]); + CAM_DBG(CAM_LRME, "Current state %d", lrme_core->state); + + mutex_lock(&lrme_hw->hw_mutex); + + if (lrme_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_DBG(CAM_LRME, "LRME HW is in off state"); + goto end; + } + + if (top_irq_status & (1 << 3)) { + CAM_DBG(CAM_LRME, "Error"); + rc = cam_lrme_hw_util_process_err(lrme_hw); + if (rc) + CAM_ERR(CAM_LRME, "Process error failed"); + goto end; + } + + if (we_irq_status[0] & (1 << 1)) { + CAM_DBG(CAM_LRME, "reg update"); + rc = cam_lrme_hw_util_process_reg_update(lrme_hw, &cb_args); + if (rc) { + CAM_ERR(CAM_LRME, "Process reg_update failed"); + goto end; + } + } + + if (top_irq_status & (1 << 4)) { + CAM_DBG(CAM_LRME, "IDLE"); + if (!lrme_core->req_proc) { + CAM_DBG(CAM_LRME, "No frame request to process idle"); + goto end; + } + rc = cam_lrme_hw_util_process_idle(lrme_hw, &cb_args); + if (rc) { + CAM_ERR(CAM_LRME, "Process idle failed"); + goto end; + } + } + + if (lrme_core->hw_mgr_cb.cam_lrme_hw_mgr_cb) { + lrme_core->hw_mgr_cb.cam_lrme_hw_mgr_cb( + lrme_core->hw_mgr_cb.data, &cb_args); + } else { + CAM_ERR(CAM_LRME, "No hw mgr cb"); + rc = -EINVAL; + } + +end: + mutex_unlock(&lrme_hw->hw_mutex); + return rc; +} + +int cam_lrme_hw_start(void *hw_priv, void *hw_start_args, uint32_t arg_size) +{ + struct cam_hw_info *lrme_hw = (struct cam_hw_info *)hw_priv; + int rc = 0; + struct cam_lrme_core *lrme_core; + + if (!lrme_hw) { + CAM_ERR(CAM_LRME, + "Invalid input params, lrme_hw %pK", + lrme_hw); + return -EINVAL; + } + + lrme_core = (struct cam_lrme_core *)lrme_hw->core_info; + + mutex_lock(&lrme_hw->hw_mutex); + + if (lrme_hw->open_count > 0) { + lrme_hw->open_count++; + CAM_DBG(CAM_LRME, "This device is activated before"); + goto unlock; + } + + rc = cam_lrme_soc_enable_resources(lrme_hw); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to enable soc resources"); + goto unlock; + } + + rc = cam_lrme_hw_util_reset(lrme_hw, CAM_LRME_HW_RESET_TYPE_HW_RESET); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to reset hw"); + goto disable_soc; + } + + if (lrme_core->hw_cdm_info) { + struct cam_lrme_cdm_info *hw_cdm_info = + lrme_core->hw_cdm_info; + + rc = cam_cdm_stream_on(hw_cdm_info->cdm_handle); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to stream on cdm"); + goto disable_soc; + } + } + + lrme_hw->hw_state = CAM_HW_STATE_POWER_UP; + lrme_hw->open_count++; + lrme_core->state = CAM_LRME_CORE_STATE_IDLE; + + CAM_DBG(CAM_LRME, "open count %d", lrme_hw->open_count); + mutex_unlock(&lrme_hw->hw_mutex); + return rc; + +disable_soc: + if (cam_lrme_soc_disable_resources(lrme_hw)) + CAM_ERR(CAM_LRME, "Error in disable soc resources"); +unlock: + CAM_DBG(CAM_LRME, "open count %d", lrme_hw->open_count); + mutex_unlock(&lrme_hw->hw_mutex); + return rc; +} + +int cam_lrme_hw_stop(void *hw_priv, void *hw_stop_args, uint32_t arg_size) +{ + struct cam_hw_info *lrme_hw = (struct cam_hw_info *)hw_priv; + int rc = 0; + struct cam_lrme_core *lrme_core; + + if (!lrme_hw) { + CAM_ERR(CAM_LRME, "Invalid argument"); + return -EINVAL; + } + + lrme_core = (struct cam_lrme_core *)lrme_hw->core_info; + + mutex_lock(&lrme_hw->hw_mutex); + + if (lrme_hw->open_count == 0 || + lrme_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { + mutex_unlock(&lrme_hw->hw_mutex); + CAM_ERR(CAM_LRME, "Error Unbalanced stop"); + return -EINVAL; + } + lrme_hw->open_count--; + + CAM_DBG(CAM_LRME, "open count %d", lrme_hw->open_count); + + if (lrme_hw->open_count) + goto unlock; + + lrme_core->req_proc = NULL; + lrme_core->req_submit = NULL; + + if (lrme_core->hw_cdm_info) { + struct cam_lrme_cdm_info *hw_cdm_info = + lrme_core->hw_cdm_info; + + rc = cam_cdm_stream_off(hw_cdm_info->cdm_handle); + if (rc) { + CAM_ERR(CAM_LRME, + "Failed in CDM StreamOff, handle=0x%x, rc=%d", + hw_cdm_info->cdm_handle, rc); + goto unlock; + } + } + + rc = cam_lrme_soc_disable_resources(lrme_hw); + if (rc) + CAM_ERR(CAM_LRME, "Failed in Disable SOC, rc=%d", rc); + + lrme_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + if (lrme_core->state == CAM_LRME_CORE_STATE_IDLE) { + lrme_core->state = CAM_LRME_CORE_STATE_INIT; + } else { + CAM_ERR(CAM_LRME, "HW in wrong state %d", lrme_core->state); + rc = -EINVAL; + } + +unlock: + mutex_unlock(&lrme_hw->hw_mutex); + return rc; +} + +int cam_lrme_hw_submit_req(void *hw_priv, void *hw_submit_args, + uint32_t arg_size) +{ + struct cam_hw_info *lrme_hw = (struct cam_hw_info *)hw_priv; + struct cam_lrme_core *lrme_core; + struct cam_lrme_hw_submit_args *args = + (struct cam_lrme_hw_submit_args *)hw_submit_args; + int rc = 0; + struct cam_lrme_frame_request *frame_req; + + + if (!hw_priv || !hw_submit_args) { + CAM_ERR(CAM_LRME, "Invalid input"); + return -EINVAL; + } + + if (sizeof(struct cam_lrme_hw_submit_args) != arg_size) { + CAM_ERR(CAM_LRME, + "size of args %zu, arg_size %d", + sizeof(struct cam_lrme_hw_submit_args), arg_size); + return -EINVAL; + } + + frame_req = args->frame_req; + + mutex_lock(&lrme_hw->hw_mutex); + + if (lrme_hw->open_count == 0) { + CAM_ERR(CAM_LRME, "HW is not open"); + mutex_unlock(&lrme_hw->hw_mutex); + return -EINVAL; + } + + lrme_core = (struct cam_lrme_core *)lrme_hw->core_info; + if (lrme_core->state != CAM_LRME_CORE_STATE_IDLE && + lrme_core->state != CAM_LRME_CORE_STATE_PROCESSING) { + mutex_unlock(&lrme_hw->hw_mutex); + CAM_DBG(CAM_LRME, "device busy, can not submit, state %d", + lrme_core->state); + return -EBUSY; + } + + if (lrme_core->req_submit != NULL) { + CAM_ERR(CAM_LRME, "req_submit is not NULL"); + return -EBUSY; + } + + rc = cam_lrme_hw_util_submit_req(lrme_core, frame_req); + if (rc) { + CAM_ERR(CAM_LRME, "Submit req failed"); + goto error; + } + + frame_req->submit_timestamp = ktime_get(); + + switch (lrme_core->state) { + case CAM_LRME_CORE_STATE_PROCESSING: + lrme_core->state = CAM_LRME_CORE_STATE_REQ_PROC_PEND; + break; + + case CAM_LRME_CORE_STATE_IDLE: + cam_lrme_hw_util_submit_go(lrme_hw); + lrme_core->state = CAM_LRME_CORE_STATE_REQ_PENDING; + break; + + default: + CAM_ERR(CAM_LRME, "Wrong hw state"); + rc = -EINVAL; + goto error; + } + + lrme_core->req_submit = frame_req; + + mutex_unlock(&lrme_hw->hw_mutex); + CAM_DBG(CAM_LRME, "Release lock, submit done for req %llu", + frame_req->req_id); + + return 0; + +error: + mutex_unlock(&lrme_hw->hw_mutex); + + return rc; + +} + +int cam_lrme_hw_reset(void *hw_priv, void *reset_core_args, uint32_t arg_size) +{ + struct cam_hw_info *lrme_hw = hw_priv; + struct cam_lrme_core *lrme_core; + struct cam_lrme_hw_reset_args *lrme_reset_args = reset_core_args; + int rc; + + if (!hw_priv) { + CAM_ERR(CAM_LRME, "Invalid input args"); + return -EINVAL; + } + + if (!reset_core_args || + sizeof(struct cam_lrme_hw_reset_args) != arg_size) { + CAM_ERR(CAM_LRME, "Invalid reset args"); + return -EINVAL; + } + + lrme_core = lrme_hw->core_info; + + mutex_lock(&lrme_hw->hw_mutex); + if (lrme_core->state == CAM_LRME_CORE_STATE_RECOVERY) { + mutex_unlock(&lrme_hw->hw_mutex); + CAM_ERR(CAM_LRME, "Reset not allowed in %d state", + lrme_core->state); + return -EINVAL; + } + + lrme_core->state = CAM_LRME_CORE_STATE_RECOVERY; + + rc = cam_lrme_hw_util_reset(lrme_hw, lrme_reset_args->reset_type); + if (rc) { + mutex_unlock(&lrme_hw->hw_mutex); + CAM_ERR(CAM_FD, "Failed to reset"); + return rc; + } + + lrme_core->state = CAM_LRME_CORE_STATE_IDLE; + + mutex_unlock(&lrme_hw->hw_mutex); + + return 0; +} + +int cam_lrme_hw_flush(void *hw_priv, void *hw_flush_args, uint32_t arg_size) +{ + struct cam_lrme_core *lrme_core = NULL; + struct cam_hw_info *lrme_hw = hw_priv; + struct cam_lrme_hw_flush_args *flush_args = + (struct cam_lrme_hw_flush_args *)hw_flush_args; + int rc = -ENODEV; + + if (!hw_priv) { + CAM_ERR(CAM_LRME, "Invalid arguments %pK", hw_priv); + return -EINVAL; + } + + lrme_core = (struct cam_lrme_core *)lrme_hw->core_info; + + mutex_lock(&lrme_hw->hw_mutex); + + if (lrme_core->state != CAM_LRME_CORE_STATE_PROCESSING && + lrme_core->state != CAM_LRME_CORE_STATE_REQ_PENDING && + lrme_core->state != CAM_LRME_CORE_STATE_REQ_PROC_PEND) { + mutex_unlock(&lrme_hw->hw_mutex); + CAM_DBG(CAM_LRME, "Flush is not needed in %d state", + lrme_core->state); + return 0; + } + + if (!lrme_core->req_proc && !lrme_core->req_submit) { + mutex_unlock(&lrme_hw->hw_mutex); + CAM_DBG(CAM_LRME, "no req in device"); + return 0; + } + + switch (flush_args->flush_type) { + case CAM_FLUSH_TYPE_ALL: + if ((!lrme_core->req_submit || + lrme_core->req_submit->ctxt_to_hw_map != + flush_args->ctxt_to_hw_map) && + (!lrme_core->req_proc || + lrme_core->req_proc->ctxt_to_hw_map != + flush_args->ctxt_to_hw_map)) { + mutex_unlock(&lrme_hw->hw_mutex); + CAM_DBG(CAM_LRME, "hw running on different ctx"); + return 0; + } + rc = cam_lrme_hw_util_flush_ctx(lrme_hw, + flush_args->ctxt_to_hw_map); + if (rc) + CAM_ERR(CAM_LRME, "Flush all failed"); + break; + + case CAM_FLUSH_TYPE_REQ: + if ((!lrme_core->req_submit || + lrme_core->req_submit != flush_args->req_to_flush) && + (!lrme_core->req_proc || + lrme_core->req_proc != flush_args->req_to_flush)) { + mutex_unlock(&lrme_hw->hw_mutex); + CAM_DBG(CAM_LRME, "hw running on different ctx"); + return 0; + } + rc = cam_lrme_hw_util_flush_req(lrme_hw, + flush_args->req_to_flush); + if (rc) + CAM_ERR(CAM_LRME, "Flush req failed"); + break; + + default: + CAM_ERR(CAM_LRME, "Unsupported flush type"); + break; + } + + mutex_unlock(&lrme_hw->hw_mutex); + + return rc; +} + +int cam_lrme_hw_get_caps(void *hw_priv, void *get_hw_cap_args, + uint32_t arg_size) +{ + struct cam_hw_info *lrme_hw; + struct cam_lrme_core *lrme_core; + struct cam_lrme_dev_cap *lrme_hw_caps = + (struct cam_lrme_dev_cap *)get_hw_cap_args; + + if (!hw_priv || !get_hw_cap_args) { + CAM_ERR(CAM_LRME, "Invalid input pointers %pK %pK", + hw_priv, get_hw_cap_args); + return -EINVAL; + } + + lrme_hw = (struct cam_hw_info *)hw_priv; + lrme_core = (struct cam_lrme_core *)lrme_hw->core_info; + *lrme_hw_caps = lrme_core->hw_caps; + + return 0; +} + +irqreturn_t cam_lrme_hw_irq(int irq_num, void *data) +{ + struct cam_hw_info *lrme_hw; + struct cam_lrme_core *lrme_core; + struct cam_hw_soc_info *soc_info; + struct cam_lrme_hw_info *hw_info; + struct crm_workq_task *task; + struct cam_lrme_hw_work_data *work_data; + uint32_t top_irq_status, fe_irq_status, we_irq_status0, we_irq_status1; + int rc; + + if (!data) { + CAM_ERR(CAM_LRME, "Invalid data in IRQ callback"); + return IRQ_NONE; + } + + lrme_hw = (struct cam_hw_info *)data; + lrme_core = (struct cam_lrme_core *)lrme_hw->core_info; + soc_info = &lrme_hw->soc_info; + hw_info = lrme_core->hw_info; + + top_irq_status = cam_io_r_mb( + soc_info->reg_map[0].mem_base + + hw_info->titan_reg.top_irq_status); + CAM_DBG(CAM_LRME, "top_irq_status %x", top_irq_status); + cam_io_w_mb(top_irq_status, + soc_info->reg_map[0].mem_base + + hw_info->titan_reg.top_irq_clear); + top_irq_status &= CAM_LRME_TOP_IRQ_MASK; + + fe_irq_status = cam_io_r_mb( + soc_info->reg_map[0].mem_base + + hw_info->bus_rd_reg.common_reg.irq_status); + CAM_DBG(CAM_LRME, "fe_irq_status %x", fe_irq_status); + cam_io_w_mb(fe_irq_status, + soc_info->reg_map[0].mem_base + + hw_info->bus_rd_reg.common_reg.irq_clear); + fe_irq_status &= CAM_LRME_FE_IRQ_MASK; + + we_irq_status0 = cam_io_r_mb( + soc_info->reg_map[0].mem_base + + hw_info->bus_wr_reg.common_reg.irq_status_0); + CAM_DBG(CAM_LRME, "we_irq_status[0] %x", we_irq_status0); + cam_io_w_mb(we_irq_status0, + soc_info->reg_map[0].mem_base + + hw_info->bus_wr_reg.common_reg.irq_clear_0); + we_irq_status0 &= CAM_LRME_WE_IRQ_MASK_0; + + we_irq_status1 = cam_io_r_mb( + soc_info->reg_map[0].mem_base + + hw_info->bus_wr_reg.common_reg.irq_status_1); + CAM_DBG(CAM_LRME, "we_irq_status[1] %x", we_irq_status1); + cam_io_w_mb(we_irq_status1, + soc_info->reg_map[0].mem_base + + hw_info->bus_wr_reg.common_reg.irq_clear_1); + we_irq_status1 &= CAM_LRME_WE_IRQ_MASK_1; + + cam_io_w_mb(0x1, soc_info->reg_map[0].mem_base + + hw_info->titan_reg.top_irq_cmd); + cam_io_w_mb(0x1, soc_info->reg_map[0].mem_base + + hw_info->bus_wr_reg.common_reg.irq_cmd); + cam_io_w_mb(0x1, soc_info->reg_map[0].mem_base + + hw_info->bus_rd_reg.common_reg.irq_cmd); + + if (top_irq_status & 0x1) { + complete(&lrme_core->reset_complete); + top_irq_status &= (~0x1); + } + + if (top_irq_status || fe_irq_status || + we_irq_status0 || we_irq_status1) { + task = cam_req_mgr_workq_get_task(lrme_core->work); + if (!task) { + CAM_ERR(CAM_LRME, "no empty task available"); + return IRQ_NONE; + } + work_data = (struct cam_lrme_hw_work_data *)task->payload; + work_data->top_irq_status = top_irq_status; + work_data->fe_irq_status = fe_irq_status; + work_data->we_irq_status[0] = we_irq_status0; + work_data->we_irq_status[1] = we_irq_status1; + task->process_cb = cam_lrme_hw_process_irq; + rc = cam_req_mgr_workq_enqueue_task(task, data, + CRM_TASK_PRIORITY_0); + if (rc) + CAM_ERR(CAM_LRME, + "Failed in enqueue work task, rc=%d", rc); + } + + return IRQ_HANDLED; +} + +int cam_lrme_hw_process_cmd(void *hw_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + struct cam_hw_info *lrme_hw = (struct cam_hw_info *)hw_priv; + int rc = 0; + + switch (cmd_type) { + case CAM_LRME_HW_CMD_PREPARE_HW_UPDATE: { + struct cam_lrme_hw_cmd_config_args *config_args; + + config_args = (struct cam_lrme_hw_cmd_config_args *)cmd_args; + rc = cam_lrme_hw_util_process_config_hw(lrme_hw, config_args); + break; + } + + case CAM_LRME_HW_CMD_REGISTER_CB: { + struct cam_lrme_hw_cmd_set_cb *cb_args; + struct cam_lrme_device *hw_device; + struct cam_lrme_core *lrme_core = + (struct cam_lrme_core *)lrme_hw->core_info; + cb_args = (struct cam_lrme_hw_cmd_set_cb *)cmd_args; + lrme_core->hw_mgr_cb.cam_lrme_hw_mgr_cb = + cb_args->cam_lrme_hw_mgr_cb; + lrme_core->hw_mgr_cb.data = cb_args->data; + hw_device = cb_args->data; + rc = 0; + break; + } + + case CAM_LRME_HW_CMD_SUBMIT: { + struct cam_lrme_hw_submit_args *submit_args; + + submit_args = (struct cam_lrme_hw_submit_args *)cmd_args; + rc = cam_lrme_hw_submit_req(hw_priv, + submit_args, arg_size); + break; + } + + case CAM_LRME_HW_CMD_DUMP_REGISTER: { + struct cam_lrme_core *lrme_core = + (struct cam_lrme_core *)lrme_hw->core_info; + lrme_core->dump_flag = *(bool *)cmd_args; + CAM_DBG(CAM_LRME, "dump_flag %d", lrme_core->dump_flag); + break; + } + + case CAM_LRME_HW_CMD_DUMP: { + struct cam_lrme_hw_dump_args *dump_args = + (struct cam_lrme_hw_dump_args *)cmd_args; + rc = cam_lrme_hw_dump(lrme_hw, dump_args); + break; + } + default: + break; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.h b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.h new file mode 100644 index 0000000000000000000000000000000000000000..4c9386c9f046cbbc40e4793015887df7b5c10728 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.h @@ -0,0 +1,469 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_LRME_HW_CORE_H_ +#define _CAM_LRME_HW_CORE_H_ + +#include +#include +#include +#include +#include + +#include "cam_common_util.h" +#include "cam_debug_util.h" +#include "cam_io_util.h" +#include "cam_cpas_api.h" +#include "cam_cdm_intf_api.h" +#include "cam_lrme_hw_intf.h" +#include "cam_lrme_hw_soc.h" +#include "cam_req_mgr_workq.h" + +#define CAM_LRME_HW_RESET_TIMEOUT 3000 + +#define CAM_LRME_BUS_RD_MAX_CLIENTS 2 +#define CAM_LRME_BUS_WR_MAX_CLIENTS 2 + +#define CAM_LRME_HW_WORKQ_NUM_TASK 30 + +#define CAM_LRME_TOP_IRQ_MASK 0x19 +#define CAM_LRME_WE_IRQ_MASK_0 0x2 +#define CAM_LRME_WE_IRQ_MASK_1 0x0 +#define CAM_LRME_FE_IRQ_MASK 0x0 + +#define CAM_LRME_MAX_REG_PAIR_NUM 60 + +#define CAM_LRME_RESPONSE_TIME_THRESHOLD 100000 +#define CAM_LRME_HW_DUMP_TAG_MAX_LEN 32 +#define CAM_LRME_HW_DUMP_NUM_WORDS 5 + +/** + * enum cam_lrme_irq_set + * + * @CAM_LRME_IRQ_ENABLE : Enable irqs + * @CAM_LRME_IRQ_DISABLE : Disable irqs + */ +enum cam_lrme_irq_set { + CAM_LRME_IRQ_ENABLE, + CAM_LRME_IRQ_DISABLE, +}; + +/** + * struct cam_lrme_cdm_info : information used to submit cdm command + * + * @cdm_handle : CDM handle for this device + * @cdm_ops : CDM ops + * @cdm_cmd : CDM command pointer + */ +struct cam_lrme_cdm_info { + uint32_t cdm_handle; + struct cam_cdm_utils_ops *cdm_ops; + struct cam_cdm_bl_request *cdm_cmd; +}; + +/** + * struct cam_lrme_hw_work_data : Work data for HW work queue + * + * @top_irq_status : Top registers irq status + * @fe_irq_status : FE engine irq status + * @we_irq_status : WE engine irq status + */ +struct cam_lrme_hw_work_data { + uint32_t top_irq_status; + uint32_t fe_irq_status; + uint32_t we_irq_status[2]; +}; + +/** + * enum cam_lrme_core_state : LRME core states + * + * @CAM_LRME_CORE_STATE_UNINIT : LRME is in uninit state + * @CAM_LRME_CORE_STATE_INIT : LRME is in init state after probe + * @ CAM_LRME_CORE_STATE_IDLE : LRME is in idle state. Hardware is in + * this state when no frame is processing + * or waiting for this core. + * @CAM_LRME_CORE_STATE_REQ_PENDING : LRME is in pending state. One frame is + * waiting for processing + * @CAM_LRME_CORE_STATE_PROCESSING : LRME is in processing state. HW manager + * can submit one more frame to HW + * @CAM_LRME_CORE_STATE_REQ_PROC_PEND : Indicate two frames are inside HW. + * @CAM_LRME_CORE_STATE_RECOVERY : Indicate core is in the process of reset + * @CAM_LRME_CORE_STATE_MAX : upper limit of states + */ +enum cam_lrme_core_state { + CAM_LRME_CORE_STATE_UNINIT, + CAM_LRME_CORE_STATE_INIT, + CAM_LRME_CORE_STATE_IDLE, + CAM_LRME_CORE_STATE_REQ_PENDING, + CAM_LRME_CORE_STATE_PROCESSING, + CAM_LRME_CORE_STATE_REQ_PROC_PEND, + CAM_LRME_CORE_STATE_RECOVERY, + CAM_LRME_CORE_STATE_MAX, +}; + +/** + * struct cam_lrme_core : LRME HW core information + * + * @hw_info : Pointer to base HW information structure + * @device_iommu : Device iommu handle + * @cdm_iommu : CDM iommu handle + * @hw_caps : Hardware capabilities + * @state : Hardware state + * @reset_complete : Reset completion + * @work : Hardware workqueue to handle irq events + * @work_data : Work data used by hardware workqueue + * @hw_mgr_cb : Hw manager callback + * @req_proc : Pointer to the processing frame request + * @req_submit : Pointer to the frame request waiting for processing + * @hw_cdm_info : CDM information used by this device + * @hw_idx : Hardware index + */ +struct cam_lrme_core { + struct cam_lrme_hw_info *hw_info; + struct cam_iommu_handle device_iommu; + struct cam_iommu_handle cdm_iommu; + struct cam_lrme_dev_cap hw_caps; + enum cam_lrme_core_state state; + struct completion reset_complete; + struct cam_req_mgr_core_workq *work; + struct cam_lrme_hw_work_data work_data[CAM_LRME_HW_WORKQ_NUM_TASK]; + struct cam_lrme_hw_cmd_set_cb hw_mgr_cb; + struct cam_lrme_frame_request *req_proc; + struct cam_lrme_frame_request *req_submit; + struct cam_lrme_cdm_info *hw_cdm_info; + uint32_t hw_idx; + bool dump_flag; +}; + +/** + * struct cam_lrme_bus_rd_reg_common : Offsets of FE common registers + * + * @hw_version : Offset of hw_version register + * @hw_capability : Offset of hw_capability register + * @sw_reset : Offset of sw_reset register + * @cgc_override : Offset of cgc_override register + * @irq_mask : Offset of irq_mask register + * @irq_clear : Offset of irq_clear register + * @irq_cmd : Offset of irq_cmd register + * @irq_status : Offset of irq_status register + * @cmd : Offset of cmd register + * @irq_set : Offset of irq_set register + * @misr_reset : Offset of misr_reset register + * @security_cfg : Offset of security_cfg register + * @pwr_iso_cfg : Offset of pwr_iso_cfg register + * @pwr_iso_seed : Offset of pwr_iso_seed register + * @test_bus_ctrl : Offset of test_bus_ctrl register + * @spare : Offset of spare register + */ +struct cam_lrme_bus_rd_reg_common { + uint32_t hw_version; + uint32_t hw_capability; + uint32_t sw_reset; + uint32_t cgc_override; + uint32_t irq_mask; + uint32_t irq_clear; + uint32_t irq_cmd; + uint32_t irq_status; + uint32_t cmd; + uint32_t irq_set; + uint32_t misr_reset; + uint32_t security_cfg; + uint32_t pwr_iso_cfg; + uint32_t pwr_iso_seed; + uint32_t test_bus_ctrl; + uint32_t spare; +}; + +/** + * struct cam_lrme_bus_wr_reg_common : Offset of WE common registers + * @hw_version : Offset of hw_version register + * @hw_capability : Offset of hw_capability register + * @sw_reset : Offset of sw_reset register + * @cgc_override : Offset of cgc_override register + * @misr_reset : Offset of misr_reset register + * @pwr_iso_cfg : Offset of pwr_iso_cfg register + * @test_bus_ctrl : Offset of test_bus_ctrl register + * @composite_mask_0 : Offset of composite_mask_0 register + * @irq_mask_0 : Offset of irq_mask_0 register + * @irq_mask_1 : Offset of irq_mask_1 register + * @irq_clear_0 : Offset of irq_clear_0 register + * @irq_clear_1 : Offset of irq_clear_1 register + * @irq_status_0 : Offset of irq_status_0 register + * @irq_status_1 : Offset of irq_status_1 register + * @irq_cmd : Offset of irq_cmd register + * @irq_set_0 : Offset of irq_set_0 register + * @irq_set_1 : Offset of irq_set_1 register + * @addr_fifo_status : Offset of addr_fifo_status register + * @frame_header_cfg0 : Offset of frame_header_cfg0 register + * @frame_header_cfg1 : Offset of frame_header_cfg1 register + * @spare : Offset of spare register + */ +struct cam_lrme_bus_wr_reg_common { + uint32_t hw_version; + uint32_t hw_capability; + uint32_t sw_reset; + uint32_t cgc_override; + uint32_t misr_reset; + uint32_t pwr_iso_cfg; + uint32_t test_bus_ctrl; + uint32_t composite_mask_0; + uint32_t irq_mask_0; + uint32_t irq_mask_1; + uint32_t irq_clear_0; + uint32_t irq_clear_1; + uint32_t irq_status_0; + uint32_t irq_status_1; + uint32_t irq_cmd; + uint32_t irq_set_0; + uint32_t irq_set_1; + uint32_t addr_fifo_status; + uint32_t frame_header_cfg0; + uint32_t frame_header_cfg1; + uint32_t spare; +}; + +/** + * struct cam_lrme_bus_rd_bus_client : Offset of FE registers + * + * @core_cfg : Offset of core_cfg register + * @ccif_meta_data : Offset of ccif_meta_data register + * @addr_image : Offset of addr_image register + * @rd_buffer_size : Offset of rd_buffer_size register + * @rd_stride : Offset of rd_stride register + * @unpack_cfg_0 : Offset of unpack_cfg_0 register + * @latency_buff_allocation : Offset of latency_buff_allocation register + * @burst_limit_cfg : Offset of burst_limit_cfg register + * @misr_cfg_0 : Offset of misr_cfg_0 register + * @misr_cfg_1 : Offset of misr_cfg_1 register + * @misr_rd_val : Offset of misr_rd_val register + * @debug_status_cfg : Offset of debug_status_cfg register + * @debug_status_0 : Offset of debug_status_0 register + * @debug_status_1 : Offset of debug_status_1 register + */ +struct cam_lrme_bus_rd_bus_client { + uint32_t core_cfg; + uint32_t ccif_meta_data; + uint32_t addr_image; + uint32_t rd_buffer_size; + uint32_t rd_stride; + uint32_t unpack_cfg_0; + uint32_t latency_buff_allocation; + uint32_t burst_limit_cfg; + uint32_t misr_cfg_0; + uint32_t misr_cfg_1; + uint32_t misr_rd_val; + uint32_t debug_status_cfg; + uint32_t debug_status_0; + uint32_t debug_status_1; +}; + +/** + * struct cam_lrme_bus_wr_bus_client : Offset of WE registers + * + * @status_0 : Offset of status_0 register + * @status_1 : Offset of status_1 register + * @cfg : Offset of cfg register + * @addr_frame_header : Offset of addr_frame_header register + * @frame_header_cfg : Offset of frame_header_cfg register + * @addr_image : Offset of addr_image register + * @addr_image_offset : Offset of addr_image_offset register + * @buffer_width_cfg : Offset of buffer_width_cfg register + * @buffer_height_cfg : Offset of buffer_height_cfg register + * @packer_cfg : Offset of packer_cfg register + * @wr_stride : Offset of wr_stride register + * @irq_subsample_cfg_period : Offset of irq_subsample_cfg_period register + * @irq_subsample_cfg_pattern : Offset of irq_subsample_cfg_pattern register + * @burst_limit_cfg : Offset of burst_limit_cfg register + * @misr_cfg : Offset of misr_cfg register + * @misr_rd_word_sel : Offset of misr_rd_word_sel register + * @misr_val : Offset of misr_val register + * @debug_status_cfg : Offset of debug_status_cfg register + * @debug_status_0 : Offset of debug_status_0 register + * @debug_status_1 : Offset of debug_status_1 register + */ +struct cam_lrme_bus_wr_bus_client { + uint32_t status_0; + uint32_t status_1; + uint32_t cfg; + uint32_t addr_frame_header; + uint32_t frame_header_cfg; + uint32_t addr_image; + uint32_t addr_image_offset; + uint32_t buffer_width_cfg; + uint32_t buffer_height_cfg; + uint32_t packer_cfg; + uint32_t wr_stride; + uint32_t irq_subsample_cfg_period; + uint32_t irq_subsample_cfg_pattern; + uint32_t burst_limit_cfg; + uint32_t misr_cfg; + uint32_t misr_rd_word_sel; + uint32_t misr_val; + uint32_t debug_status_cfg; + uint32_t debug_status_0; + uint32_t debug_status_1; +}; + +/** + * struct cam_lrme_bus_rd_hw_info : FE registers information + * + * @common_reg : FE common register + * @bus_client_reg : List of FE bus registers information + */ +struct cam_lrme_bus_rd_hw_info { + struct cam_lrme_bus_rd_reg_common common_reg; + struct cam_lrme_bus_rd_bus_client + bus_client_reg[CAM_LRME_BUS_RD_MAX_CLIENTS]; +}; + +/** + * struct cam_lrme_bus_wr_hw_info : WE engine registers information + * + * @common_reg : WE common register + * @bus_client_reg : List of WE bus registers information + */ +struct cam_lrme_bus_wr_hw_info { + struct cam_lrme_bus_wr_reg_common common_reg; + struct cam_lrme_bus_wr_bus_client + bus_client_reg[CAM_LRME_BUS_WR_MAX_CLIENTS]; +}; + +/** + * struct cam_lrme_clc_reg : Offset of clc registers + * + * @clc_hw_version : Offset of clc_hw_version register + * @clc_hw_status : Offset of clc_hw_status register + * @clc_hw_status_dbg : Offset of clc_hw_status_dbg register + * @clc_module_cfg : Offset of clc_module_cfg register + * @clc_moduleformat : Offset of clc_moduleformat register + * @clc_rangestep : Offset of clc_rangestep register + * @clc_offset : Offset of clc_offset register + * @clc_maxallowedsad : Offset of clc_maxallowedsad register + * @clc_minallowedtarmad : Offset of clc_minallowedtarmad register + * @clc_meaningfulsaddiff : Offset of clc_meaningfulsaddiff register + * @clc_minsaddiffdenom : Offset of clc_minsaddiffdenom register + * @clc_robustnessmeasuredistmap_0 : Offset of measuredistmap_0 register + * @clc_robustnessmeasuredistmap_1 : Offset of measuredistmap_1 register + * @clc_robustnessmeasuredistmap_2 : Offset of measuredistmap_2 register + * @clc_robustnessmeasuredistmap_3 : Offset of measuredistmap_3 register + * @clc_robustnessmeasuredistmap_4 : Offset of measuredistmap_4 register + * @clc_robustnessmeasuredistmap_5 : Offset of measuredistmap_5 register + * @clc_robustnessmeasuredistmap_6 : Offset of measuredistmap_6 register + * @clc_robustnessmeasuredistmap_7 : Offset of measuredistmap_7 register + * @clc_ds_crop_horizontal : Offset of clc_ds_crop_horizontal register + * @clc_ds_crop_vertical : Offset of clc_ds_crop_vertical register + * @clc_tar_pd_unpacker : Offset of clc_tar_pd_unpacker register + * @clc_ref_pd_unpacker : Offset of clc_ref_pd_unpacker register + * @clc_sw_override : Offset of clc_sw_override register + * @clc_tar_height : Offset of clc_tar_height register + * @clc_test_bus_ctrl : Offset of clc_test_bus_ctrl register + * @clc_spare : Offset of clc_spare register + */ +struct cam_lrme_clc_reg { + uint32_t clc_hw_version; + uint32_t clc_hw_status; + uint32_t clc_hw_status_dbg; + uint32_t clc_module_cfg; + uint32_t clc_moduleformat; + uint32_t clc_rangestep; + uint32_t clc_offset; + uint32_t clc_maxallowedsad; + uint32_t clc_minallowedtarmad; + uint32_t clc_meaningfulsaddiff; + uint32_t clc_minsaddiffdenom; + uint32_t clc_robustnessmeasuredistmap_0; + uint32_t clc_robustnessmeasuredistmap_1; + uint32_t clc_robustnessmeasuredistmap_2; + uint32_t clc_robustnessmeasuredistmap_3; + uint32_t clc_robustnessmeasuredistmap_4; + uint32_t clc_robustnessmeasuredistmap_5; + uint32_t clc_robustnessmeasuredistmap_6; + uint32_t clc_robustnessmeasuredistmap_7; + uint32_t clc_ds_crop_horizontal; + uint32_t clc_ds_crop_vertical; + uint32_t clc_tar_pd_unpacker; + uint32_t clc_ref_pd_unpacker; + uint32_t clc_sw_override; + uint32_t clc_tar_height; + uint32_t clc_ref_height; + uint32_t clc_test_bus_ctrl; + uint32_t clc_spare; +}; + +/** + * struct cam_lrme_titan_reg : Offset of LRME top registers + * + * @top_hw_version : Offset of top_hw_version register + * @top_titan_version : Offset of top_titan_version register + * @top_rst_cmd : Offset of top_rst_cmd register + * @top_core_clk_cfg : Offset of top_core_clk_cfg register + * @top_irq_status : Offset of top_irq_status register + * @top_irq_mask : Offset of top_irq_mask register + * @top_irq_clear : Offset of top_irq_clear register + * @top_irq_set : Offset of top_irq_set register + * @top_irq_cmd : Offset of top_irq_cmd register + * @top_violation_status : Offset of top_violation_status register + * @top_spare : Offset of top_spare register + */ +struct cam_lrme_titan_reg { + uint32_t top_hw_version; + uint32_t top_titan_version; + uint32_t top_rst_cmd; + uint32_t top_core_clk_cfg; + uint32_t top_irq_status; + uint32_t top_irq_mask; + uint32_t top_irq_clear; + uint32_t top_irq_set; + uint32_t top_irq_cmd; + uint32_t top_violation_status; + uint32_t top_spare; +}; + +/** + * struct cam_lrme_hw_info : LRME registers information + * + * @clc_reg : LRME CLC registers + * @bus_rd_reg : LRME FE registers + * @bus_wr_reg : LRME WE registers + * @titan_reg : LRME top reisters + */ +struct cam_lrme_hw_info { + struct cam_lrme_clc_reg clc_reg; + struct cam_lrme_bus_rd_hw_info bus_rd_reg; + struct cam_lrme_bus_wr_hw_info bus_wr_reg; + struct cam_lrme_titan_reg titan_reg; +}; + +/** + * struct cam_lrme_hw_dump_header : LRME hw dump header + * + * @tag : LRME hw dump header tag + * @size : Size of data + * @word_size : size of each word + */ + +struct cam_lrme_hw_dump_header { + uint8_t tag[CAM_LRME_HW_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + +int cam_lrme_hw_process_irq(void *priv, void *data); +int cam_lrme_hw_submit_req(void *hw_priv, void *hw_submit_args, + uint32_t arg_size); +int cam_lrme_hw_reset(void *hw_priv, void *reset_core_args, uint32_t arg_size); +int cam_lrme_hw_stop(void *hw_priv, void *stop_args, uint32_t arg_size); +int cam_lrme_hw_get_caps(void *hw_priv, void *get_hw_cap_args, + uint32_t arg_size); +irqreturn_t cam_lrme_hw_irq(int irq_num, void *data); +int cam_lrme_hw_process_cmd(void *hw_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size); +int cam_lrme_hw_util_get_caps(struct cam_hw_info *lrme_hw, + struct cam_lrme_dev_cap *hw_caps); +int cam_lrme_hw_start(void *hw_priv, void *hw_init_args, uint32_t arg_size); +int cam_lrme_hw_flush(void *hw_priv, void *hw_flush_args, uint32_t arg_size); +void cam_lrme_set_irq(struct cam_hw_info *lrme_hw, enum cam_lrme_irq_set set); + +#endif /* _CAM_LRME_HW_CORE_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_dev.c b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..5276f74c31f93821624b0d272b22396f18ccf89b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_dev.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "cam_subdev.h" +#include "cam_lrme_hw_intf.h" +#include "cam_lrme_hw_core.h" +#include "cam_lrme_hw_soc.h" +#include "cam_lrme_hw_reg.h" +#include "cam_req_mgr_workq.h" +#include "cam_lrme_hw_mgr.h" +#include "cam_mem_mgr_api.h" +#include "cam_smmu_api.h" + +static int cam_lrme_hw_dev_util_cdm_acquire(struct cam_lrme_core *lrme_core, + struct cam_hw_info *lrme_hw) +{ + int rc, i; + struct cam_cdm_bl_request *cdm_cmd; + struct cam_cdm_acquire_data cdm_acquire; + struct cam_lrme_cdm_info *hw_cdm_info; + + hw_cdm_info = kzalloc(sizeof(struct cam_lrme_cdm_info), + GFP_KERNEL); + if (!hw_cdm_info) { + CAM_ERR(CAM_LRME, "No memory for hw_cdm_info"); + return -ENOMEM; + } + + cdm_cmd = kzalloc((sizeof(struct cam_cdm_bl_request) + + ((CAM_LRME_MAX_HW_ENTRIES - 1) * + sizeof(struct cam_cdm_bl_cmd))), GFP_KERNEL); + if (!cdm_cmd) { + CAM_ERR(CAM_LRME, "No memory for cdm_cmd"); + kfree(hw_cdm_info); + return -ENOMEM; + } + + memset(&cdm_acquire, 0, sizeof(cdm_acquire)); + strlcpy(cdm_acquire.identifier, "lrmecdm", sizeof("lrmecdm")); + cdm_acquire.cell_index = lrme_hw->soc_info.index; + cdm_acquire.handle = 0; + cdm_acquire.userdata = hw_cdm_info; + cdm_acquire.cam_cdm_callback = NULL; + cdm_acquire.id = CAM_CDM_VIRTUAL; + cdm_acquire.base_array_cnt = lrme_hw->soc_info.num_reg_map; + cdm_acquire.priority = CAM_CDM_BL_FIFO_0; + for (i = 0; i < lrme_hw->soc_info.num_reg_map; i++) + cdm_acquire.base_array[i] = &lrme_hw->soc_info.reg_map[i]; + + rc = cam_cdm_acquire(&cdm_acquire); + if (rc) { + CAM_ERR(CAM_LRME, "Can't acquire cdm"); + goto error; + } + + hw_cdm_info->cdm_cmd = cdm_cmd; + hw_cdm_info->cdm_ops = cdm_acquire.ops; + hw_cdm_info->cdm_handle = cdm_acquire.handle; + + lrme_core->hw_cdm_info = hw_cdm_info; + CAM_DBG(CAM_LRME, "cdm acquire done"); + + return 0; +error: + kfree(cdm_cmd); + kfree(hw_cdm_info); + return rc; +} + +static int cam_lrme_hw_dev_probe(struct platform_device *pdev) +{ + struct cam_hw_info *lrme_hw; + struct cam_hw_intf lrme_hw_intf; + struct cam_lrme_core *lrme_core; + const struct of_device_id *match_dev = NULL; + struct cam_lrme_hw_info *hw_info; + int rc, i; + + lrme_hw = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!lrme_hw) { + CAM_ERR(CAM_LRME, "No memory to create lrme_hw"); + return -ENOMEM; + } + + lrme_core = kzalloc(sizeof(struct cam_lrme_core), GFP_KERNEL); + if (!lrme_core) { + CAM_ERR(CAM_LRME, "No memory to create lrme_core"); + kfree(lrme_hw); + return -ENOMEM; + } + + lrme_hw->core_info = lrme_core; + lrme_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + lrme_hw->soc_info.pdev = pdev; + lrme_hw->soc_info.dev = &pdev->dev; + lrme_hw->soc_info.dev_name = pdev->name; + lrme_hw->open_count = 0; + lrme_core->state = CAM_LRME_CORE_STATE_INIT; + + mutex_init(&lrme_hw->hw_mutex); + spin_lock_init(&lrme_hw->hw_lock); + init_completion(&lrme_hw->hw_complete); + init_completion(&lrme_core->reset_complete); + + rc = cam_req_mgr_workq_create("cam_lrme_hw_worker", + CAM_LRME_HW_WORKQ_NUM_TASK, + &lrme_core->work, CRM_WORKQ_USAGE_IRQ, 0); + if (rc) { + CAM_ERR(CAM_LRME, "Unable to create a workq, rc=%d", rc); + goto free_memory; + } + + for (i = 0; i < CAM_LRME_HW_WORKQ_NUM_TASK; i++) + lrme_core->work->task.pool[i].payload = + &lrme_core->work_data[i]; + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev || !match_dev->data) { + CAM_ERR(CAM_LRME, "No Of_match data, %pK", match_dev); + rc = -EINVAL; + goto destroy_workqueue; + } + hw_info = (struct cam_lrme_hw_info *)match_dev->data; + lrme_core->hw_info = hw_info; + + rc = cam_lrme_soc_init_resources(&lrme_hw->soc_info, + cam_lrme_hw_irq, lrme_hw); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to init soc, rc=%d", rc); + goto destroy_workqueue; + } + + rc = cam_lrme_hw_dev_util_cdm_acquire(lrme_core, lrme_hw); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to acquire cdm"); + goto deinit_platform_res; + } + + rc = cam_smmu_get_handle("lrme", &lrme_core->device_iommu.non_secure); + if (rc) { + CAM_ERR(CAM_LRME, "Get iommu handle failed"); + goto release_cdm; + } + + rc = cam_lrme_hw_start(lrme_hw, NULL, 0); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to hw init, rc=%d", rc); + goto detach_smmu; + } + + rc = cam_lrme_hw_util_get_caps(lrme_hw, &lrme_core->hw_caps); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to get hw caps, rc=%d", rc); + if (cam_lrme_hw_stop(lrme_hw, NULL, 0)) + CAM_ERR(CAM_LRME, "Failed in hw deinit"); + goto detach_smmu; + } + + rc = cam_lrme_hw_stop(lrme_hw, NULL, 0); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to deinit hw, rc=%d", rc); + goto detach_smmu; + } + + lrme_core->hw_idx = lrme_hw->soc_info.index; + lrme_hw_intf.hw_priv = lrme_hw; + lrme_hw_intf.hw_idx = lrme_hw->soc_info.index; + lrme_hw_intf.hw_ops.get_hw_caps = cam_lrme_hw_get_caps; + lrme_hw_intf.hw_ops.init = NULL; + lrme_hw_intf.hw_ops.deinit = NULL; + lrme_hw_intf.hw_ops.reset = cam_lrme_hw_reset; + lrme_hw_intf.hw_ops.reserve = NULL; + lrme_hw_intf.hw_ops.release = NULL; + lrme_hw_intf.hw_ops.start = cam_lrme_hw_start; + lrme_hw_intf.hw_ops.stop = cam_lrme_hw_stop; + lrme_hw_intf.hw_ops.read = NULL; + lrme_hw_intf.hw_ops.write = NULL; + lrme_hw_intf.hw_ops.process_cmd = cam_lrme_hw_process_cmd; + lrme_hw_intf.hw_ops.flush = cam_lrme_hw_flush; + lrme_hw_intf.hw_type = CAM_HW_LRME; + + rc = cam_cdm_get_iommu_handle("lrmecdm", &lrme_core->cdm_iommu); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to acquire the CDM iommu handles"); + goto detach_smmu; + } + + rc = cam_lrme_mgr_register_device(&lrme_hw_intf, + &lrme_core->device_iommu, + &lrme_core->cdm_iommu); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to register device"); + goto detach_smmu; + } + + platform_set_drvdata(pdev, lrme_hw); + CAM_DBG(CAM_LRME, "LRME-%d probe successful", lrme_hw_intf.hw_idx); + + return rc; + +detach_smmu: + cam_smmu_destroy_handle(lrme_core->device_iommu.non_secure); +release_cdm: + cam_cdm_release(lrme_core->hw_cdm_info->cdm_handle); + kfree(lrme_core->hw_cdm_info->cdm_cmd); + kfree(lrme_core->hw_cdm_info); +deinit_platform_res: + if (cam_lrme_soc_deinit_resources(&lrme_hw->soc_info)) + CAM_ERR(CAM_LRME, "Failed in soc deinit"); + mutex_destroy(&lrme_hw->hw_mutex); +destroy_workqueue: + cam_req_mgr_workq_destroy(&lrme_core->work); +free_memory: + mutex_destroy(&lrme_hw->hw_mutex); + kfree(lrme_hw); + kfree(lrme_core); + + return rc; +} + +static int cam_lrme_hw_dev_remove(struct platform_device *pdev) +{ + int rc = 0; + struct cam_hw_info *lrme_hw; + struct cam_lrme_core *lrme_core; + + lrme_hw = platform_get_drvdata(pdev); + if (!lrme_hw) { + CAM_ERR(CAM_LRME, "Invalid lrme_hw from fd_hw_intf"); + return -ENODEV; + } + + lrme_core = (struct cam_lrme_core *)lrme_hw->core_info; + if (!lrme_core) { + CAM_ERR(CAM_LRME, "Invalid lrme_core from fd_hw"); + rc = -EINVAL; + goto deinit_platform_res; + } + + cam_smmu_destroy_handle(lrme_core->device_iommu.non_secure); + cam_cdm_release(lrme_core->hw_cdm_info->cdm_handle); + cam_lrme_mgr_deregister_device(lrme_core->hw_idx); + + kfree(lrme_core->hw_cdm_info->cdm_cmd); + kfree(lrme_core->hw_cdm_info); + kfree(lrme_core); + +deinit_platform_res: + rc = cam_lrme_soc_deinit_resources(&lrme_hw->soc_info); + if (rc) + CAM_ERR(CAM_LRME, "Error in LRME soc deinit, rc=%d", rc); + + mutex_destroy(&lrme_hw->hw_mutex); + kfree(lrme_hw); + + return rc; +} + +static const struct of_device_id cam_lrme_hw_dt_match[] = { + { + .compatible = "qcom,lrme", + .data = &cam_lrme10_hw_info, + }, + {} +}; + +MODULE_DEVICE_TABLE(of, cam_lrme_hw_dt_match); + +static struct platform_driver cam_lrme_hw_driver = { + .probe = cam_lrme_hw_dev_probe, + .remove = cam_lrme_hw_dev_remove, + .driver = { + .name = "cam_lrme_hw", + .owner = THIS_MODULE, + .of_match_table = cam_lrme_hw_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_lrme_hw_init_module(void) +{ + return platform_driver_register(&cam_lrme_hw_driver); +} + +static void __exit cam_lrme_hw_exit_module(void) +{ + platform_driver_unregister(&cam_lrme_hw_driver); +} + +module_init(cam_lrme_hw_init_module); +module_exit(cam_lrme_hw_exit_module); +MODULE_DESCRIPTION("CAM LRME HW driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_intf.h b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..cd4d64b18f67f4792946daaec282da0f13e3c32c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_intf.h @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_LRME_HW_INTF_H_ +#define _CAM_LRME_HW_INTF_H_ + +#include +#include +#include +#include +#include +#include + +#include "cam_io_util.h" +#include "cam_soc_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "cam_subdev.h" +#include "cam_cpas_api.h" +#include "cam_hw_mgr_intf.h" +#include "cam_debug_util.h" + + +#define CAM_LRME_MAX_IO_BUFFER 2 +#define CAM_LRME_MAX_HW_ENTRIES 5 + +#define CAM_LRME_BASE_IDX 0 + +/** + * enum cam_lrme_hw_type : Enum for LRME HW type + * + * @CAM_HW_LRME : LRME HW type + */ +enum cam_lrme_hw_type { + CAM_HW_LRME, +}; + +/** + * enum cam_lrme_cb_type : HW manager call back type + * + * @CAM_LRME_CB_BUF_DONE : Indicate buf done has been generated + * @CAM_LRME_CB_COMP_REG_UPDATE : Indicate receiving WE comp reg update + * @CAM_LRME_CB_PUT_FRAME : Request HW manager to put back the frame + * @CAM_LRME_CB_ERROR : Indicate error irq has been generated + */ +enum cam_lrme_cb_type { + CAM_LRME_CB_BUF_DONE = 1, + CAM_LRME_CB_COMP_REG_UPDATE = 1 << 1, + CAM_LRME_CB_PUT_FRAME = 1 << 2, + CAM_LRME_CB_ERROR = 1 << 3, +}; + +/** + * enum cam_lrme_hw_cmd_type : HW CMD type + * + * @CAM_LRME_HW_CMD_prepare_hw_update : Prepare HW update + * @CAM_LRME_HW_CMD_REGISTER_CB : register HW manager callback + * @CAM_LRME_HW_CMD_SUBMIT : Submit frame to HW + * @CAM_LRME_HW_CMD_DUMP_REGISTER : dump register values + * @CAM_LRME_HW_CMD_DUMP : dump register values to buffer + */ +enum cam_lrme_hw_cmd_type { + CAM_LRME_HW_CMD_PREPARE_HW_UPDATE, + CAM_LRME_HW_CMD_REGISTER_CB, + CAM_LRME_HW_CMD_SUBMIT, + CAM_LRME_HW_CMD_DUMP_REGISTER, + CAM_LRME_HW_CMD_DUMP, +}; + +/** + * enum cam_lrme_hw_reset_type : Type of reset + * + * @CAM_LRME_HW_RESET_TYPE_HW_RESET : HW reset + * @CAM_LRME_HW_RESET_TYPE_SW_RESET : SW reset + */ +enum cam_lrme_hw_reset_type { + CAM_LRME_HW_RESET_TYPE_HW_RESET, + CAM_LRME_HW_RESET_TYPE_SW_RESET, +}; + +/** + *struct cam_lrme_frame_request : LRME frame request + * + * @frame_list : List head + * @req_id : Request ID + * @ctxt_to_hw_map : Information about context id, priority and device id + * @hw_device : Pointer to HW device + * @hw_update_entries : List of hw_update_entries + * @num_hw_update_entries : number of hw_update_entries + * @submit_timestamp : timestamp of submitting request with hw + */ +struct cam_lrme_frame_request { + struct list_head frame_list; + uint64_t req_id; + void *ctxt_to_hw_map; + struct cam_lrme_device *hw_device; + struct cam_hw_update_entry hw_update_entries[CAM_LRME_MAX_HW_ENTRIES]; + uint32_t num_hw_update_entries; + ktime_t submit_timestamp; +}; + +/** + * struct cam_lrme_hw_io_buffer : IO buffer information + * + * @valid : Indicate whether this IO config is valid + * @io_cfg : Pointer to IO configuration + * @num_buf : Number of buffers + * @num_plane : Number of planes + * @io_addr : List of IO address + */ +struct cam_lrme_hw_io_buffer { + bool valid; + struct cam_buf_io_cfg *io_cfg; + uint32_t num_buf; + uint32_t num_plane; + uint64_t io_addr[CAM_PACKET_MAX_PLANES]; +}; + +/** + * struct cam_lrme_hw_cmd_config_args : Args for prepare HW update + * + * @hw_device : Pointer to HW device + * @input_buf : List of input buffers + * @output_buf : List of output buffers + * @cmd_buf_addr : Pointer to available KMD buffer + * @size : Available KMD buffer size + * @config_buf_size : Size used to prepare update + */ +struct cam_lrme_hw_cmd_config_args { + struct cam_lrme_device *hw_device; + struct cam_lrme_hw_io_buffer input_buf[CAM_LRME_MAX_IO_BUFFER]; + struct cam_lrme_hw_io_buffer output_buf[CAM_LRME_MAX_IO_BUFFER]; + uint32_t *cmd_buf_addr; + uint32_t size; + uint32_t config_buf_size; +}; + +/** + * struct cam_lrme_hw_flush_args : Args for flush HW + * + * @ctxt_to_hw_map : Identity of context + * @req_to_flush : Pointer to the frame need to flush in + * case of single frame flush + * @flush_type : Flush type + */ +struct cam_lrme_hw_flush_args { + void *ctxt_to_hw_map; + struct cam_lrme_frame_request *req_to_flush; + uint32_t flush_type; +}; + +/** + * struct cam_lrme_hw_reset_args : Args for reset HW + * + * @reset_type : Enum cam_lrme_hw_reset_type + */ +struct cam_lrme_hw_reset_args { + uint32_t reset_type; +}; + +/** + * struct cam_lrme_hw_cb_args : HW manager callback args + * + * @cb_type : Callback event type + * @frame_req : Pointer to the frame associated with the cb + */ +struct cam_lrme_hw_cb_args { + uint32_t cb_type; + struct cam_lrme_frame_request *frame_req; +}; + +/** + * struct cam_lrme_hw_cmd_set_cb : Args for set callback function + * + * @cam_lrme_hw_mgr_cb : Callback function pointer + * @data : Data sent along with callback function + */ +struct cam_lrme_hw_cmd_set_cb { + int (*cam_lrme_hw_mgr_cb)(void *data, + struct cam_lrme_hw_cb_args *args); + void *data; +}; + +/** + * struct cam_lrme_hw_submit_args : Args for submit request + * + * @hw_update_entries : List of hw update entries used to program registers + * @num_hw_update_entries : Number of hw update entries + * @frame_req : Pointer to the frame request + */ +struct cam_lrme_hw_submit_args { + struct cam_hw_update_entry *hw_update_entries; + uint32_t num_hw_update_entries; + struct cam_lrme_frame_request *frame_req; +}; + +/** + * struct cam_lrme_hw_dump_args : Args for dump request + * + * @request_id : Issue request id + * @cpu_addr : start address of the target buffer + * @offset : offset of the buffer + * @buf_len : Length of target buffer + */ +struct cam_lrme_hw_dump_args { + uint64_t request_id; + uintptr_t cpu_addr; + size_t offset; + size_t buf_len; +}; + +#endif /* _CAM_LRME_HW_INTF_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_reg.h b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..17eb25b0facfa71af1df429f11a2066d96d45277 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_reg.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_LRME_HW_REG_H_ +#define _CAM_LRME_HW_REG_H_ + +#include "cam_lrme_hw_core.h" + +static struct cam_lrme_hw_info cam_lrme10_hw_info = { + .clc_reg = { + .clc_hw_version = 0x00000000, + .clc_hw_status = 0x00000004, + .clc_hw_status_dbg = 0x00000008, + .clc_module_cfg = 0x00000060, + .clc_moduleformat = 0x000000A8, + .clc_rangestep = 0x00000068, + .clc_offset = 0x0000006C, + .clc_maxallowedsad = 0x00000070, + .clc_minallowedtarmad = 0x00000074, + .clc_meaningfulsaddiff = 0x00000078, + .clc_minsaddiffdenom = 0x0000007C, + .clc_robustnessmeasuredistmap_0 = 0x00000080, + .clc_robustnessmeasuredistmap_1 = 0x00000084, + .clc_robustnessmeasuredistmap_2 = 0x00000088, + .clc_robustnessmeasuredistmap_3 = 0x0000008C, + .clc_robustnessmeasuredistmap_4 = 0x00000090, + .clc_robustnessmeasuredistmap_5 = 0x00000094, + .clc_robustnessmeasuredistmap_6 = 0x00000098, + .clc_robustnessmeasuredistmap_7 = 0x0000009C, + .clc_ds_crop_horizontal = 0x000000A0, + .clc_ds_crop_vertical = 0x000000A4, + .clc_tar_pd_unpacker = 0x000000AC, + .clc_ref_pd_unpacker = 0x000000B0, + .clc_sw_override = 0x000000B4, + .clc_tar_height = 0x000000B8, + .clc_ref_height = 0x000000BC, + .clc_test_bus_ctrl = 0x000001F8, + .clc_spare = 0x000001FC, + }, + .bus_rd_reg = { + .common_reg = { + .hw_version = 0x00000200, + .hw_capability = 0x00000204, + .sw_reset = 0x00000208, + .cgc_override = 0x0000020C, + .irq_mask = 0x00000210, + .irq_clear = 0x00000214, + .irq_cmd = 0x00000218, + .irq_status = 0x0000021C, + .cmd = 0x00000220, + .irq_set = 0x00000224, + .misr_reset = 0x0000022C, + .security_cfg = 0x00000230, + .pwr_iso_cfg = 0x00000234, + .pwr_iso_seed = 0x00000238, + .test_bus_ctrl = 0x00000248, + .spare = 0x0000024C, + }, + .bus_client_reg = { + /* bus client 0 */ + { + .core_cfg = 0x00000250, + .ccif_meta_data = 0x00000254, + .addr_image = 0x00000258, + .rd_buffer_size = 0x0000025C, + .rd_stride = 0x00000260, + .unpack_cfg_0 = 0x00000264, + .latency_buff_allocation = 0x00000278, + .burst_limit_cfg = 0x00000280, + .misr_cfg_0 = 0x00000284, + .misr_cfg_1 = 0x00000288, + .misr_rd_val = 0x0000028C, + .debug_status_cfg = 0x00000290, + .debug_status_0 = 0x00000294, + .debug_status_1 = 0x00000298, + }, + /* bus client 1 */ + { + .core_cfg = 0x000002F0, + .ccif_meta_data = 0x000002F4, + .addr_image = 0x000002F8, + .rd_buffer_size = 0x000002FC, + .rd_stride = 0x00000300, + .unpack_cfg_0 = 0x00000304, + .latency_buff_allocation = 0x00000318, + .burst_limit_cfg = 0x00000320, + .misr_cfg_0 = 0x00000324, + .misr_cfg_1 = 0x00000328, + .misr_rd_val = 0x0000032C, + .debug_status_cfg = 0x00000330, + .debug_status_0 = 0x00000334, + .debug_status_1 = 0x00000338, + }, + }, + }, + .bus_wr_reg = { + .common_reg = { + .hw_version = 0x00000500, + .hw_capability = 0x00000504, + .sw_reset = 0x00000508, + .cgc_override = 0x0000050C, + .misr_reset = 0x000005C8, + .pwr_iso_cfg = 0x000005CC, + .test_bus_ctrl = 0x0000061C, + .composite_mask_0 = 0x00000510, + .irq_mask_0 = 0x00000544, + .irq_mask_1 = 0x00000548, + .irq_clear_0 = 0x00000550, + .irq_clear_1 = 0x00000554, + .irq_status_0 = 0x0000055C, + .irq_status_1 = 0x00000560, + .irq_cmd = 0x00000568, + .irq_set_0 = 0x000005BC, + .irq_set_1 = 0x000005C0, + .addr_fifo_status = 0x000005A8, + .frame_header_cfg0 = 0x000005AC, + .frame_header_cfg1 = 0x000005B0, + .spare = 0x00000620, + }, + .bus_client_reg = { + /* bus client 0 */ + { + .status_0 = 0x00000700, + .status_1 = 0x00000704, + .cfg = 0x00000708, + .addr_frame_header = 0x0000070C, + .frame_header_cfg = 0x00000710, + .addr_image = 0x00000714, + .addr_image_offset = 0x00000718, + .buffer_width_cfg = 0x0000071C, + .buffer_height_cfg = 0x00000720, + .packer_cfg = 0x00000724, + .wr_stride = 0x00000728, + .irq_subsample_cfg_period = 0x00000748, + .irq_subsample_cfg_pattern = 0x0000074C, + .burst_limit_cfg = 0x0000075C, + .misr_cfg = 0x00000760, + .misr_rd_word_sel = 0x00000764, + .misr_val = 0x00000768, + .debug_status_cfg = 0x0000076C, + .debug_status_0 = 0x00000770, + .debug_status_1 = 0x00000774, + }, + /* bus client 1 */ + { + .status_0 = 0x00000800, + .status_1 = 0x00000804, + .cfg = 0x00000808, + .addr_frame_header = 0x0000080C, + .frame_header_cfg = 0x00000810, + .addr_image = 0x00000814, + .addr_image_offset = 0x00000818, + .buffer_width_cfg = 0x0000081C, + .buffer_height_cfg = 0x00000820, + .packer_cfg = 0x00000824, + .wr_stride = 0x00000828, + .irq_subsample_cfg_period = 0x00000848, + .irq_subsample_cfg_pattern = 0x0000084C, + .burst_limit_cfg = 0x0000085C, + .misr_cfg = 0x00000860, + .misr_rd_word_sel = 0x00000864, + .misr_val = 0x00000868, + .debug_status_cfg = 0x0000086C, + .debug_status_0 = 0x00000870, + .debug_status_1 = 0x00000874, + }, + }, + }, + .titan_reg = { + .top_hw_version = 0x00000900, + .top_titan_version = 0x00000904, + .top_rst_cmd = 0x00000908, + .top_core_clk_cfg = 0x00000920, + .top_irq_status = 0x0000090C, + .top_irq_mask = 0x00000910, + .top_irq_clear = 0x00000914, + .top_irq_set = 0x00000918, + .top_irq_cmd = 0x0000091C, + .top_violation_status = 0x00000924, + .top_spare = 0x000009FC, + }, +}; + +#endif /* _CAM_LRME_HW_REG_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_soc.c b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..5ef984cba883374ca5d8d85c1330e8c0a75b9a10 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_soc.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "cam_lrme_hw_core.h" +#include "cam_lrme_hw_soc.h" + + +int cam_lrme_soc_enable_resources(struct cam_hw_info *lrme_hw) +{ + struct cam_hw_soc_info *soc_info = &lrme_hw->soc_info; + struct cam_lrme_soc_private *soc_private = + (struct cam_lrme_soc_private *)soc_info->soc_private; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + int rc = 0; + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_LOWSVS_VOTE; + axi_vote.num_paths = 2; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_READ; + axi_vote.axi_path[0].camnoc_bw = 7200000; + axi_vote.axi_path[0].mnoc_ab_bw = 7200000; + axi_vote.axi_path[0].mnoc_ib_bw = 7200000; + axi_vote.axi_path[1].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[1].transac_type = CAM_AXI_TRANSACTION_WRITE; + axi_vote.axi_path[1].camnoc_bw = 7200000; + axi_vote.axi_path[1].mnoc_ab_bw = 7200000; + axi_vote.axi_path[1].mnoc_ib_bw = 7200000; + + rc = cam_cpas_start(soc_private->cpas_handle, &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to start cpas, rc %d", rc); + return -EFAULT; + } + + rc = cam_soc_util_enable_platform_resource(soc_info, true, CAM_SVS_VOTE, + true); + if (rc) { + CAM_ERR(CAM_LRME, + "Failed to enable platform resource, rc %d", rc); + goto stop_cpas; + } + + cam_lrme_set_irq(lrme_hw, CAM_LRME_IRQ_ENABLE); + + return rc; + +stop_cpas: + if (cam_cpas_stop(soc_private->cpas_handle)) + CAM_ERR(CAM_LRME, "Failed to stop cpas"); + + return rc; +} + +int cam_lrme_soc_disable_resources(struct cam_hw_info *lrme_hw) +{ + struct cam_hw_soc_info *soc_info = &lrme_hw->soc_info; + struct cam_lrme_soc_private *soc_private; + int rc = 0; + + soc_private = soc_info->soc_private; + + cam_lrme_set_irq(lrme_hw, CAM_LRME_IRQ_DISABLE); + + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to disable platform resource"); + return rc; + } + rc = cam_cpas_stop(soc_private->cpas_handle); + if (rc) + CAM_ERR(CAM_LRME, "Failed to stop cpas"); + + return rc; +} + +int cam_lrme_soc_init_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t irq_handler, void *private_data) +{ + struct cam_lrme_soc_private *soc_private; + struct cam_cpas_register_params cpas_register_param; + int rc; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc) { + CAM_ERR(CAM_LRME, "Failed in get_dt_properties, rc=%d", rc); + return rc; + } + + rc = cam_soc_util_request_platform_resource(soc_info, irq_handler, + private_data); + if (rc) { + CAM_ERR(CAM_LRME, "Failed in request_platform_resource rc=%d", + rc); + return rc; + } + + soc_private = kzalloc(sizeof(struct cam_lrme_soc_private), GFP_KERNEL); + if (!soc_private) { + rc = -ENOMEM; + goto release_res; + } + soc_info->soc_private = soc_private; + + memset(&cpas_register_param, 0, sizeof(cpas_register_param)); + strlcpy(cpas_register_param.identifier, + "lrmecpas", CAM_HW_IDENTIFIER_LENGTH); + cpas_register_param.cell_index = soc_info->index; + cpas_register_param.dev = &soc_info->pdev->dev; + cpas_register_param.userdata = private_data; + cpas_register_param.cam_cpas_client_cb = NULL; + + rc = cam_cpas_register_client(&cpas_register_param); + if (rc) { + CAM_ERR(CAM_LRME, "CPAS registration failed"); + goto free_soc_private; + } + soc_private->cpas_handle = cpas_register_param.client_handle; + CAM_DBG(CAM_LRME, "CPAS handle=%d", soc_private->cpas_handle); + + return rc; + +free_soc_private: + kfree(soc_info->soc_private); + soc_info->soc_private = NULL; +release_res: + cam_soc_util_release_platform_resource(soc_info); + + return rc; +} + +int cam_lrme_soc_deinit_resources(struct cam_hw_soc_info *soc_info) +{ + struct cam_lrme_soc_private *soc_private = + (struct cam_lrme_soc_private *)soc_info->soc_private; + int rc; + + rc = cam_cpas_unregister_client(soc_private->cpas_handle); + if (rc) + CAM_ERR(CAM_LRME, "Unregister cpas failed, handle=%d, rc=%d", + soc_private->cpas_handle, rc); + + rc = cam_soc_util_release_platform_resource(soc_info); + if (rc) + CAM_ERR(CAM_LRME, "release platform failed, rc=%d", rc); + + kfree(soc_info->soc_private); + soc_info->soc_private = NULL; + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_soc.h b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..d77ac2bfdb63c90e34832ae769de4bc6a551f1aa --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_soc.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_LRME_HW_SOC_H_ +#define _CAM_LRME_HW_SOC_H_ + +#include "cam_soc_util.h" + +struct cam_lrme_soc_private { + uint32_t cpas_handle; +}; + +int cam_lrme_soc_enable_resources(struct cam_hw_info *lrme_hw); +int cam_lrme_soc_disable_resources(struct cam_hw_info *lrme_hw); +int cam_lrme_soc_init_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t irq_handler, void *private_data); +int cam_lrme_soc_deinit_resources(struct cam_hw_soc_info *soc_info); + +#endif /* _CAM_LRME_HW_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_ope/Makefile b/techpack/camera-bengal/drivers/cam_ope/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..7b44f4f0c3621a97f10f23844a90bcfc596b4a9d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += ope_hw_mgr/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_ope_subdev.o cam_ope_context.o + diff --git a/techpack/camera-bengal/drivers/cam_ope/cam_ope_context.c b/techpack/camera-bengal/drivers/cam_ope/cam_ope_context.c new file mode 100644 index 0000000000000000000000000000000000000000..d7c1e9481f9cbe8611dca50f3b68aae1c3361168 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/cam_ope_context.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "cam_sync_api.h" +#include "cam_node.h" +#include "cam_context.h" +#include "cam_context_utils.h" +#include "cam_ope_context.h" +#include "cam_req_mgr_util.h" +#include "cam_mem_mgr.h" +#include "cam_trace.h" +#include "cam_debug_util.h" +#include "cam_packet_util.h" + +static const char ope_dev_name[] = "cam-ope"; + +static int cam_ope_context_dump_active_request(void *data, unsigned long iova, + uint32_t buf_info) +{ + struct cam_context *ctx = (struct cam_context *)data; + struct cam_ctx_request *req = NULL; + struct cam_ctx_request *req_temp = NULL; + struct cam_hw_mgr_dump_pf_data *pf_dbg_entry = NULL; + int rc = 0; + bool b_mem_found = false; + + if (!ctx) { + CAM_ERR(CAM_OPE, "Invalid ctx"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state < CAM_CTX_ACQUIRED || ctx->state > CAM_CTX_ACTIVATED) { + CAM_ERR(CAM_OPE, "Invalid state ope ctx %d state %d", + ctx->ctx_id, ctx->state); + goto end; + } + + CAM_INFO(CAM_OPE, "iommu fault for ope ctx %d state %d", + ctx->ctx_id, ctx->state); + + list_for_each_entry_safe(req, req_temp, + &ctx->active_req_list, list) { + pf_dbg_entry = &(req->pf_data); + CAM_INFO(CAM_OPE, "req_id : %lld", req->request_id); + + rc = cam_context_dump_pf_info_to_hw(ctx, pf_dbg_entry->packet, + iova, buf_info, &b_mem_found); + if (rc) + CAM_ERR(CAM_OPE, "Failed to dump pf info"); + + if (b_mem_found) + CAM_ERR(CAM_OPE, "Found page fault in req %lld %d", + req->request_id, rc); + } + +end: + mutex_unlock(&ctx->ctx_mutex); + return rc; +} + +static int __cam_ope_acquire_dev_in_available(struct cam_context *ctx, + struct cam_acquire_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_acquire_dev_to_hw(ctx, cmd); + if (!rc) { + ctx->state = CAM_CTX_ACQUIRED; + trace_cam_context_state("OPE", ctx); + } + + return rc; +} + +static int __cam_ope_release_dev_in_acquired(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_release_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_OPE, "Unable to release device"); + + ctx->state = CAM_CTX_AVAILABLE; + trace_cam_context_state("OPE", ctx); + return rc; +} + +static int __cam_ope_start_dev_in_acquired(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_start_dev_to_hw(ctx, cmd); + if (!rc) { + ctx->state = CAM_CTX_READY; + trace_cam_context_state("OPE", ctx); + } + + return rc; +} + +static int __cam_ope_flush_dev_in_ready(struct cam_context *ctx, + struct cam_flush_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_flush_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_OPE, "Failed to flush device"); + + return rc; +} + +static int __cam_ope_dump_dev_in_ready(struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc; + + rc = cam_context_dump_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_OPE, "Failed to dump device"); + + return rc; +} + +static int __cam_ope_config_dev_in_ready(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + int rc; + size_t len; + uintptr_t packet_addr; + + rc = cam_mem_get_cpu_buf((int32_t) cmd->packet_handle, + &packet_addr, &len); + if (rc) { + CAM_ERR(CAM_OPE, "[%s][%d] Can not get packet address", + ctx->dev_name, ctx->ctx_id); + rc = -EINVAL; + return rc; + } + + rc = cam_context_prepare_dev_to_hw(ctx, cmd); + + if (rc) + CAM_ERR(CAM_OPE, "Failed to prepare device"); + + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); + return rc; +} + +static int __cam_ope_stop_dev_in_ready(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_stop_dev_to_hw(ctx); + if (rc) + CAM_ERR(CAM_OPE, "Failed to stop device"); + + ctx->state = CAM_CTX_ACQUIRED; + trace_cam_context_state("OPE", ctx); + return rc; +} + +static int __cam_ope_release_dev_in_ready(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc; + + rc = __cam_ope_stop_dev_in_ready(ctx, NULL); + if (rc) + CAM_ERR(CAM_OPE, "Failed to stop device"); + + rc = __cam_ope_release_dev_in_acquired(ctx, cmd); + if (rc) + CAM_ERR(CAM_OPE, "Failed to release device"); + + return rc; +} + +static int __cam_ope_handle_buf_done_in_ready(void *ctx, + uint32_t evt_id, void *done) +{ + return cam_context_buf_done_from_hw(ctx, done, evt_id); +} + +static struct cam_ctx_ops + cam_ope_ctx_state_machine[CAM_CTX_STATE_MAX] = { + /* Uninit */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Available */ + { + .ioctl_ops = { + .acquire_dev = __cam_ope_acquire_dev_in_available, + }, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Acquired */ + { + .ioctl_ops = { + .release_dev = __cam_ope_release_dev_in_acquired, + .start_dev = __cam_ope_start_dev_in_acquired, + .config_dev = __cam_ope_config_dev_in_ready, + .flush_dev = __cam_ope_flush_dev_in_ready, + .dump_dev = __cam_ope_dump_dev_in_ready, + }, + .crm_ops = {}, + .irq_ops = __cam_ope_handle_buf_done_in_ready, + .pagefault_ops = cam_ope_context_dump_active_request, + }, + /* Ready */ + { + .ioctl_ops = { + .stop_dev = __cam_ope_stop_dev_in_ready, + .release_dev = __cam_ope_release_dev_in_ready, + .config_dev = __cam_ope_config_dev_in_ready, + .flush_dev = __cam_ope_flush_dev_in_ready, + .dump_dev = __cam_ope_dump_dev_in_ready, + }, + .crm_ops = {}, + .irq_ops = __cam_ope_handle_buf_done_in_ready, + .pagefault_ops = cam_ope_context_dump_active_request, + }, + /* Activated */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + .pagefault_ops = cam_ope_context_dump_active_request, + }, +}; + +int cam_ope_context_init(struct cam_ope_context *ctx, + struct cam_hw_mgr_intf *hw_intf, uint32_t ctx_id) +{ + int rc; + + if ((!ctx) || (!ctx->base) || (!hw_intf)) { + CAM_ERR(CAM_OPE, "Invalid params: %pK %pK", ctx, hw_intf); + rc = -EINVAL; + goto err; + } + + rc = cam_context_init(ctx->base, ope_dev_name, CAM_OPE, ctx_id, + NULL, hw_intf, ctx->req_base, CAM_CTX_REQ_MAX); + if (rc) { + CAM_ERR(CAM_OPE, "Camera Context Base init failed"); + goto err; + } + + ctx->base->state_machine = cam_ope_ctx_state_machine; + ctx->base->ctx_priv = ctx; + ctx->ctxt_to_hw_map = NULL; + +err: + return rc; +} + +int cam_ope_context_deinit(struct cam_ope_context *ctx) +{ + if ((!ctx) || (!ctx->base)) { + CAM_ERR(CAM_OPE, "Invalid params: %pK", ctx); + return -EINVAL; + } + + cam_context_deinit(ctx->base); + memset(ctx, 0, sizeof(*ctx)); + + return 0; +} + + diff --git a/techpack/camera-bengal/drivers/cam_ope/cam_ope_context.h b/techpack/camera-bengal/drivers/cam_ope/cam_ope_context.h new file mode 100644 index 0000000000000000000000000000000000000000..59b2c2748e80f0ca1e24330433d6316ef89e4c70 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/cam_ope_context.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_OPE_CONTEXT_H_ +#define _CAM_OPE_CONTEXT_H_ + +#include "cam_context.h" + +#define OPE_CTX_MAX 32 + +/** + * struct cam_ope_context - ope context + * @base: ope context object + * @state_machine: state machine for OPE context + * @req_base: common request structure + * @state: ope context state + * @ctxt_to_hw_map: context to FW handle mapping + */ +struct cam_ope_context { + struct cam_context *base; + struct cam_ctx_ops *state_machine; + struct cam_ctx_request req_base[CAM_CTX_REQ_MAX]; + uint32_t state; + void *ctxt_to_hw_map; +}; + +/** + * cam_ope_context_init() - OPE context init + * @ctx: Pointer to context + * @hw_intf: Pointer to OPE hardware interface + * @ctx_id: ID for this context + */ +int cam_ope_context_init(struct cam_ope_context *ctx, + struct cam_hw_mgr_intf *hw_intf, uint32_t ctx_id); + +/** + * cam_ope_context_deinit() - OPE context deinit + * @ctx: Pointer to context + */ +int cam_ope_context_deinit(struct cam_ope_context *ctx); + +#endif /* _CAM_OPE_CONTEXT_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_ope/cam_ope_subdev.c b/techpack/camera-bengal/drivers/cam_ope/cam_ope_subdev.c new file mode 100644 index 0000000000000000000000000000000000000000..3a09b71a085dca2d504eb2178a258ff696c52222 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/cam_ope_subdev.c @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_req_mgr_dev.h" +#include "cam_subdev.h" +#include "cam_node.h" +#include "cam_context.h" +#include "cam_ope_context.h" +#include "cam_ope_hw_mgr_intf.h" +#include "cam_hw_mgr_intf.h" +#include "cam_debug_util.h" +#include "cam_smmu_api.h" + +#define OPE_DEV_NAME "cam-ope" + +struct cam_ope_subdev { + struct cam_subdev sd; + struct cam_node *node; + struct cam_context ctx[OPE_CTX_MAX]; + struct cam_ope_context ctx_ope[OPE_CTX_MAX]; + struct mutex ope_lock; + int32_t open_cnt; + int32_t reserved; +}; + +static struct cam_ope_subdev g_ope_dev; + +static void cam_ope_dev_iommu_fault_handler( + struct iommu_domain *domain, struct device *dev, unsigned long iova, + int flags, void *token, uint32_t buf_info) +{ + int i = 0; + struct cam_node *node = NULL; + + if (!token) { + CAM_ERR(CAM_OPE, "invalid token in page handler cb"); + return; + } + + node = (struct cam_node *)token; + + for (i = 0; i < node->ctx_size; i++) + cam_context_dump_pf_info(&(node->ctx_list[i]), iova, + buf_info); +} + +static int cam_ope_subdev_open(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct cam_hw_mgr_intf *hw_mgr_intf = NULL; + struct cam_node *node = v4l2_get_subdevdata(sd); + int rc = 0; + + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); + + mutex_lock(&g_ope_dev.ope_lock); + if (g_ope_dev.open_cnt >= 1) { + CAM_ERR(CAM_OPE, "OPE subdev is already opened"); + rc = -EALREADY; + goto end; + } + + if (!node) { + CAM_ERR(CAM_OPE, "Invalid args"); + rc = -EINVAL; + goto end; + } + + hw_mgr_intf = &node->hw_mgr_intf; + rc = hw_mgr_intf->hw_open(hw_mgr_intf->hw_mgr_priv, NULL); + if (rc < 0) { + CAM_ERR(CAM_OPE, "OPE HW open failed: %d", rc); + goto end; + } + g_ope_dev.open_cnt++; + CAM_DBG(CAM_OPE, "OPE HW open success: %d", rc); +end: + mutex_unlock(&g_ope_dev.ope_lock); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); + return rc; +} + +static int cam_ope_subdev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + int rc = 0; + struct cam_hw_mgr_intf *hw_mgr_intf = NULL; + struct cam_node *node = v4l2_get_subdevdata(sd); + + mutex_lock(&g_ope_dev.ope_lock); + if (g_ope_dev.open_cnt <= 0) { + CAM_DBG(CAM_OPE, "OPE subdev is already closed"); + rc = -EINVAL; + goto end; + } + g_ope_dev.open_cnt--; + if (!node) { + CAM_ERR(CAM_OPE, "Invalid args"); + rc = -EINVAL; + goto end; + } + + hw_mgr_intf = &node->hw_mgr_intf; + if (!hw_mgr_intf) { + CAM_ERR(CAM_OPE, "hw_mgr_intf is not initialized"); + rc = -EINVAL; + goto end; + } + + rc = cam_node_shutdown(node); + if (rc < 0) { + CAM_ERR(CAM_OPE, "HW close failed"); + goto end; + } + CAM_DBG(CAM_OPE, "OPE HW close success: %d", rc); + +end: + mutex_unlock(&g_ope_dev.ope_lock); + return rc; +} + +const struct v4l2_subdev_internal_ops cam_ope_subdev_internal_ops = { + .open = cam_ope_subdev_open, + .close = cam_ope_subdev_close, +}; + +static int cam_ope_subdev_probe(struct platform_device *pdev) +{ + int rc = 0, i = 0; + struct cam_node *node; + struct cam_hw_mgr_intf *hw_mgr_intf; + int iommu_hdl = -1; + + CAM_DBG(CAM_OPE, "OPE subdev probe start"); + if (!pdev) { + CAM_ERR(CAM_OPE, "pdev is NULL"); + return -EINVAL; + } + + g_ope_dev.sd.pdev = pdev; + g_ope_dev.sd.internal_ops = &cam_ope_subdev_internal_ops; + rc = cam_subdev_probe(&g_ope_dev.sd, pdev, OPE_DEV_NAME, + CAM_OPE_DEVICE_TYPE); + if (rc) { + CAM_ERR(CAM_OPE, "OPE cam_subdev_probe failed:%d", rc); + return rc; + } + + node = (struct cam_node *) g_ope_dev.sd.token; + + hw_mgr_intf = kzalloc(sizeof(*hw_mgr_intf), GFP_KERNEL); + if (!hw_mgr_intf) { + rc = -EINVAL; + goto hw_alloc_fail; + } + + rc = cam_ope_hw_mgr_init(pdev->dev.of_node, (uint64_t *)hw_mgr_intf, + &iommu_hdl); + if (rc) { + CAM_ERR(CAM_OPE, "OPE HW manager init failed: %d", rc); + goto hw_init_fail; + } + + for (i = 0; i < OPE_CTX_MAX; i++) { + g_ope_dev.ctx_ope[i].base = &g_ope_dev.ctx[i]; + rc = cam_ope_context_init(&g_ope_dev.ctx_ope[i], + hw_mgr_intf, i); + if (rc) { + CAM_ERR(CAM_OPE, "OPE context init failed"); + goto ctx_fail; + } + } + + rc = cam_node_init(node, hw_mgr_intf, g_ope_dev.ctx, + OPE_CTX_MAX, OPE_DEV_NAME); + if (rc) { + CAM_ERR(CAM_OPE, "OPE node init failed"); + goto ctx_fail; + } + + cam_smmu_set_client_page_fault_handler(iommu_hdl, + cam_ope_dev_iommu_fault_handler, node); + + g_ope_dev.open_cnt = 0; + mutex_init(&g_ope_dev.ope_lock); + + CAM_DBG(CAM_OPE, "OPE subdev probe complete"); + + return rc; + +ctx_fail: + for (--i; i >= 0; i--) + cam_ope_context_deinit(&g_ope_dev.ctx_ope[i]); +hw_init_fail: + kfree(hw_mgr_intf); +hw_alloc_fail: + cam_subdev_remove(&g_ope_dev.sd); + return rc; +} + +static int cam_ope_subdev_remove(struct platform_device *pdev) +{ + int i; + struct v4l2_subdev *sd; + struct cam_subdev *subdev; + + if (!pdev) { + CAM_ERR(CAM_OPE, "pdev is NULL"); + return -ENODEV; + } + + sd = platform_get_drvdata(pdev); + if (!sd) { + CAM_ERR(CAM_OPE, "V4l2 subdev is NULL"); + return -ENODEV; + } + + subdev = v4l2_get_subdevdata(sd); + if (!subdev) { + CAM_ERR(CAM_OPE, "cam subdev is NULL"); + return -ENODEV; + } + + for (i = 0; i < OPE_CTX_MAX; i++) + cam_ope_context_deinit(&g_ope_dev.ctx_ope[i]); + cam_node_deinit(g_ope_dev.node); + cam_subdev_remove(&g_ope_dev.sd); + mutex_destroy(&g_ope_dev.ope_lock); + + return 0; +} + +static const struct of_device_id cam_ope_dt_match[] = { + {.compatible = "qcom,cam-ope"}, + {} +}; + + +static struct platform_driver cam_ope_driver = { + .probe = cam_ope_subdev_probe, + .remove = cam_ope_subdev_remove, + .driver = { + .name = "cam_ope", + .of_match_table = cam_ope_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_ope_init_module(void) +{ + return platform_driver_register(&cam_ope_driver); +} + +static void __exit cam_ope_exit_module(void) +{ + platform_driver_unregister(&cam_ope_driver); +} +module_init(cam_ope_init_module); +module_exit(cam_ope_exit_module); +MODULE_DESCRIPTION("MSM OPE driver"); +MODULE_LICENSE("GPL v2"); + diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/Makefile b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..632e2c706a5584049e00358867bb65d5ea365a98 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/Makefile @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += ope_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_ope_hw_mgr.o + + diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c new file mode 100644 index 0000000000000000000000000000000000000000..d9350ca3086313b0fd6d2c1a64fa6c9a20493d38 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -0,0 +1,4163 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cam_sync_api.h" +#include "cam_packet_util.h" +#include "cam_hw.h" +#include "cam_hw_mgr_intf.h" +#include "cam_ope_hw_mgr_intf.h" +#include "cam_ope_hw_mgr.h" +#include "ope_hw.h" +#include "cam_smmu_api.h" +#include "cam_mem_mgr.h" +#include "cam_req_mgr_workq.h" +#include "cam_mem_mgr.h" +#include "cam_debug_util.h" +#include "cam_soc_util.h" +#include "cam_trace.h" +#include "cam_cpas_api.h" +#include "cam_common_util.h" +#include "cam_cdm_intf_api.h" +#include "cam_cdm_util.h" +#include "cam_cdm.h" +#include "ope_dev_intf.h" + +static struct cam_ope_hw_mgr *ope_hw_mgr; + +static int cam_ope_req_timer_reset(struct cam_ope_ctx *ctx_data); + +static int cam_ope_mgr_get_rsc_idx(struct cam_ope_ctx *ctx_data, + struct ope_io_buf_info *in_io_buf) +{ + int k = 0; + int rsc_idx = -EINVAL; + + if (in_io_buf->direction == CAM_BUF_INPUT) { + for (k = 0; k < OPE_IN_RES_MAX; k++) { + if (ctx_data->ope_acquire.in_res[k].res_id == + in_io_buf->resource_type) + break; + } + if (k == OPE_IN_RES_MAX) { + CAM_ERR(CAM_OPE, "Invalid res_id %d", + in_io_buf->resource_type); + goto end; + } + rsc_idx = k; + } else if (in_io_buf->direction == CAM_BUF_OUTPUT) { + for (k = 0; k < OPE_OUT_RES_MAX; k++) { + if (ctx_data->ope_acquire.out_res[k].res_id == + in_io_buf->resource_type) + break; + } + if (k == OPE_OUT_RES_MAX) { + CAM_ERR(CAM_OPE, "Invalid res_id %d", + in_io_buf->resource_type); + goto end; + } + rsc_idx = k; + } + +end: + return rsc_idx; +} + +static bool cam_ope_is_pending_request(struct cam_ope_ctx *ctx_data) +{ + return !bitmap_empty(ctx_data->bitmap, CAM_CTX_REQ_MAX); +} + +static int cam_ope_mgr_process_cmd(void *priv, void *data) +{ + int rc; + struct ope_cmd_work_data *task_data = NULL; + struct cam_ope_ctx *ctx_data; + struct cam_cdm_bl_request *cdm_cmd; + struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; + + if (!data || !priv) { + CAM_ERR(CAM_OPE, "Invalid params%pK %pK", data, priv); + return -EINVAL; + } + + ctx_data = priv; + task_data = (struct ope_cmd_work_data *)data; + + mutex_lock(&hw_mgr->hw_mgr_mutex); + cdm_cmd = task_data->data; + + if (!cdm_cmd) { + CAM_ERR(CAM_OPE, "Invalid params%pK", cdm_cmd); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EINVAL; + } + + if (ctx_data->ctx_state != OPE_CTX_STATE_ACQUIRED) { + mutex_unlock(&hw_mgr->hw_mgr_mutex); + CAM_ERR(CAM_OPE, "ctx id :%u is not in use", + ctx_data->ctx_id); + return -EINVAL; + } + + if (task_data->req_id <= ctx_data->last_flush_req) { + CAM_WARN(CAM_OPE, + "request %lld has been flushed, reject packet", + task_data->req_id, ctx_data->last_flush_req); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EINVAL; + } + + if (!cam_ope_is_pending_request(ctx_data)) { + CAM_WARN(CAM_OPE, "no pending req, req %lld last flush %lld", + task_data->req_id, ctx_data->last_flush_req); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EINVAL; + } + + CAM_DBG(CAM_OPE, + "cam_cdm_submit_bls: handle 0x%x, ctx_id %d req %d cookie %d", + ctx_data->ope_cdm.cdm_handle, ctx_data->ctx_id, + task_data->req_id, cdm_cmd->cookie); + + if (task_data->req_id > ctx_data->last_flush_req) + ctx_data->last_flush_req = 0; + + cam_ope_req_timer_reset(ctx_data); + + rc = cam_cdm_submit_bls(ctx_data->ope_cdm.cdm_handle, cdm_cmd); + + if (!rc) + ctx_data->req_cnt++; + else + CAM_ERR(CAM_OPE, "submit failed for %lld", cdm_cmd->cookie); + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + return rc; +} + +static int cam_ope_mgr_reset_hw(void) +{ + struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; + int i, rc = 0; + + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RESET, + NULL, 0); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Reset failed: %d", rc); + return rc; + } + } + + return rc; +} + +static void cam_ope_free_io_config(struct cam_ope_request *req) +{ + int i, j; + + for (i = 0; i < OPE_MAX_BATCH_SIZE; i++) { + for (j = 0; j < OPE_MAX_IO_BUFS; j++) { + if (req->io_buf[i][j]) { + kzfree(req->io_buf[i][j]); + req->io_buf[i][j] = NULL; + } + } + } +} + +static void cam_ope_device_timer_stop(struct cam_ope_hw_mgr *hw_mgr) +{ + if (hw_mgr->clk_info.watch_dog) { + hw_mgr->clk_info.watch_dog_reset_counter = 0; + crm_timer_exit(&hw_mgr->clk_info.watch_dog); + hw_mgr->clk_info.watch_dog = NULL; + } +} + +static void cam_ope_device_timer_reset(struct cam_ope_hw_mgr *hw_mgr) +{ + + if (hw_mgr->clk_info.watch_dog) { + CAM_DBG(CAM_OPE, "reset timer"); + crm_timer_reset(hw_mgr->clk_info.watch_dog); + hw_mgr->clk_info.watch_dog_reset_counter++; + } +} + +static int cam_ope_req_timer_modify(struct cam_ope_ctx *ctx_data, + int32_t expires) +{ + if (ctx_data->req_watch_dog) { + CAM_DBG(CAM_OPE, "stop timer : ctx_id = %d", ctx_data->ctx_id); + crm_timer_modify(ctx_data->req_watch_dog, expires); + } + return 0; +} + +static int cam_ope_req_timer_stop(struct cam_ope_ctx *ctx_data) +{ + if (ctx_data->req_watch_dog) { + CAM_DBG(CAM_OPE, "stop timer : ctx_id = %d", ctx_data->ctx_id); + ctx_data->req_watch_dog_reset_counter = 0; + crm_timer_exit(&ctx_data->req_watch_dog); + ctx_data->req_watch_dog = NULL; + } + return 0; +} + +static int cam_ope_req_timer_reset(struct cam_ope_ctx *ctx_data) +{ + if (ctx_data && ctx_data->req_watch_dog) { + ctx_data->req_watch_dog_reset_counter++; + CAM_DBG(CAM_OPE, "reset timer : ctx_id = %d, counter=%d", + ctx_data->ctx_id, + ctx_data->req_watch_dog_reset_counter); + crm_timer_reset(ctx_data->req_watch_dog); + } + + return 0; +} + + +static int cam_ope_mgr_reapply_config(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_ope_request *ope_req) +{ + int rc = 0; + uint64_t request_id = 0; + struct crm_workq_task *task; + struct ope_cmd_work_data *task_data; + + request_id = ope_req->request_id; + CAM_DBG(CAM_OPE, "reapply req_id = %lld", request_id); + + task = cam_req_mgr_workq_get_task(ope_hw_mgr->cmd_work); + if (!task) { + CAM_ERR(CAM_OPE, "no empty task"); + return -ENOMEM; + } + + task_data = (struct ope_cmd_work_data *)task->payload; + task_data->data = (void *)ope_req->cdm_cmd; + task_data->req_id = request_id; + task_data->type = OPE_WORKQ_TASK_CMD_TYPE; + task->process_cb = cam_ope_mgr_process_cmd; + rc = cam_req_mgr_workq_enqueue_task(task, ctx_data, + CRM_TASK_PRIORITY_0); + + return rc; +} + +static int cam_get_valid_ctx_id(void) +{ + struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; + int i; + + for (i = 0; i < OPE_CTX_MAX; i++) { + if (hw_mgr->ctx[i].ctx_state == OPE_CTX_STATE_ACQUIRED) + break; + } + + if (i == OPE_CTX_MAX) + return -EINVAL; + + return i; +} + +static int32_t cam_ope_mgr_process_msg(void *priv, void *data) +{ + struct ope_msg_work_data *task_data; + struct cam_ope_hw_mgr *hw_mgr; + struct cam_ope_ctx *ctx; + uint32_t irq_status; + int32_t ctx_id; + int rc = 0, i; + + if (!data || !priv) { + CAM_ERR(CAM_OPE, "Invalid data"); + return -EINVAL; + } + + task_data = data; + hw_mgr = priv; + irq_status = task_data->irq_status; + ctx_id = cam_get_valid_ctx_id(); + if (ctx_id < 0) { + CAM_ERR(CAM_OPE, "No valid context to handle error"); + return ctx_id; + } + + ctx = &hw_mgr->ctx[ctx_id]; + + /* Indicate about this error to CDM and reset OPE*/ + rc = cam_cdm_handle_error(ctx->ope_cdm.cdm_handle); + + mutex_lock(&ctx->ctx_mutex); + if (ctx->ctx_state != OPE_CTX_STATE_ACQUIRED) { + CAM_DBG(CAM_OPE, "ctx id: %d not in right state: %d", + ctx_id, ctx->ctx_state); + mutex_unlock(&ctx->ctx_mutex); + return -EINVAL; + } + + for (i = 0; i < hw_mgr->num_ope; i++) { + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RESET, + NULL, 0); + if (rc) + CAM_ERR(CAM_OPE, "OPE Dev acquire failed: %d", rc); + } + + mutex_unlock(&ctx->ctx_mutex); + return rc; +} + +static int cam_ope_dump_hang_patches(struct cam_packet *packet, + struct cam_ope_hang_dump *dump) +{ + struct cam_patch_desc *patch_desc = NULL; + dma_addr_t iova_addr; + size_t src_buf_size; + int i, rc = 0; + int32_t iommu_hdl = ope_hw_mgr->iommu_hdl; + + /* process patch descriptor */ + patch_desc = (struct cam_patch_desc *) + ((uint32_t *) &packet->payload + + packet->patch_offset/4); + + for (i = 0; i < packet->num_patches; i++) { + rc = cam_mem_get_io_buf(patch_desc[i].src_buf_hdl, + iommu_hdl, &iova_addr, &src_buf_size); + if (rc < 0) { + CAM_ERR(CAM_UTIL, + "get src buf address failed for handle 0x%x", + patch_desc[i].src_buf_hdl); + return rc; + } + dump->entries[dump->num_bufs].memhdl = + patch_desc[i].src_buf_hdl; + dump->entries[dump->num_bufs].iova = iova_addr; + dump->entries[dump->num_bufs].offset = patch_desc[i].src_offset; + dump->entries[dump->num_bufs].len = 0; + dump->entries[dump->num_bufs].size = src_buf_size; + dump->num_bufs++; + } + return rc; +} + +static int cam_ope_dump_direct(struct ope_cmd_buf_info *cmd_buf_info, + struct cam_ope_hang_dump *dump) +{ + dma_addr_t iova_addr; + size_t size; + int rc = 0; + + rc = cam_mem_get_io_buf(cmd_buf_info->mem_handle, + ope_hw_mgr->iommu_hdl, &iova_addr, &size); + if (rc < 0) { + CAM_ERR(CAM_UTIL, "get cmd buf addressfailed for handle 0x%x", + cmd_buf_info->mem_handle); + return rc; + } + dump->entries[dump->num_bufs].memhdl = cmd_buf_info->mem_handle; + dump->entries[dump->num_bufs].iova = iova_addr; + dump->entries[dump->num_bufs].offset = cmd_buf_info->offset; + dump->entries[dump->num_bufs].len = cmd_buf_info->length; + dump->entries[dump->num_bufs].size = size; + dump->num_bufs++; + return 0; +} + +static void cam_ope_dump_dmi(struct cam_ope_hang_dump *dump, uint32_t addr, + uint32_t length) +{ + int i; + uint32_t memhdl = 0, iova = 0, size; + + for (i = 0; i < dump->num_bufs; i++) { + if (dump->entries[i].iova + dump->entries[i].offset == addr) { + if (dump->entries[i].len == length) + goto end; + else if (dump->entries[i].len == 0) { + dump->entries[i].len = length; + goto end; + } else { + iova = dump->entries[i].iova; + memhdl = dump->entries[i].memhdl; + size = dump->entries[i].size; + } + } + } + if (memhdl && iova) { + dump->entries[dump->num_bufs].memhdl = memhdl; + dump->entries[dump->num_bufs].iova = iova; + dump->entries[dump->num_bufs].offset = addr - iova; + dump->entries[dump->num_bufs].len = length; + dump->entries[dump->num_bufs].size = size; + dump->num_bufs++; + } +end: + return; +} + +static int cam_ope_mgr_put_cmd_buf(struct cam_packet *packet) +{ + int i = 0; + struct cam_cmd_buf_desc *cmd_desc = NULL; + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); + + for (i = 0; i < packet->num_cmd_buf; i++) { + if (cmd_desc[i].type != CAM_CMD_BUF_GENERIC || + cmd_desc[i].meta_data == OPE_CMD_META_GENERIC_BLOB) + continue; + + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + } + + return 0; +} + +static int cam_ope_dump_indirect(struct ope_cmd_buf_info *cmd_buf_info, + struct cam_ope_hang_dump *dump) +{ + int rc = 0; + uintptr_t cpu_addr; + size_t buf_len; + uint32_t num_dmi; + struct cdm_dmi_cmd dmi_cmd; + uint32_t *print_ptr, print_idx; + + rc = cam_mem_get_cpu_buf(cmd_buf_info->mem_handle, + &cpu_addr, &buf_len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buf fail 0x%x", + cmd_buf_info->mem_handle); + return rc; + } + cpu_addr = cpu_addr + cmd_buf_info->offset; + + num_dmi = cmd_buf_info->length / + sizeof(struct cdm_dmi_cmd); + print_ptr = (uint32_t *)cpu_addr; + for (print_idx = 0; print_idx < num_dmi; print_idx++) { + memcpy(&dmi_cmd, (const void *)print_ptr, + sizeof(struct cdm_dmi_cmd)); + cam_ope_dump_dmi(dump, dmi_cmd.addr, dmi_cmd.length+1); + print_ptr += sizeof(struct cdm_dmi_cmd) / + sizeof(uint32_t); + } + cam_mem_put_cpu_buf((int32_t) cmd_buf_info->mem_handle); + return rc; +} + +static int cam_ope_mgr_dump_cmd_buf(uintptr_t frame_process_addr, + struct cam_ope_hang_dump *dump) +{ + int rc = 0; + int i, j; + struct ope_frame_process *frame_process; + struct ope_cmd_buf_info *cmd_buf; + + frame_process = (struct ope_frame_process *)frame_process_addr; + for (i = 0; i < frame_process->batch_size; i++) { + for (j = 0; j < frame_process->num_cmd_bufs[i]; j++) { + cmd_buf = &frame_process->cmd_buf[i][j]; + if (cmd_buf->type == OPE_CMD_BUF_TYPE_DIRECT) { + if (cmd_buf->cmd_buf_usage == OPE_CMD_BUF_DEBUG) + continue; + cam_ope_dump_direct(cmd_buf, dump); + } else if (cmd_buf->type == OPE_CMD_BUF_TYPE_INDIRECT) + cam_ope_dump_indirect(cmd_buf, dump); + } + } + return rc; +} + +static int cam_ope_mgr_dump_frame_set(uintptr_t frame_process_addr, + struct cam_ope_hang_dump *dump) +{ + int i, j, rc = 0; + dma_addr_t iova_addr; + size_t size; + struct ope_frame_process *frame_process; + struct ope_io_buf_info *io_buf; + struct cam_ope_buf_entry *buf_entry; + struct cam_ope_output_info *output_info; + + frame_process = (struct ope_frame_process *)frame_process_addr; + for (j = 0; j < frame_process->batch_size; j++) { + for (i = 0; i < frame_process->frame_set[j].num_io_bufs; i++) { + io_buf = &frame_process->frame_set[j].io_buf[i]; + rc = cam_mem_get_io_buf(io_buf->mem_handle[0], + ope_hw_mgr->iommu_hdl, &iova_addr, &size); + if (rc) { + CAM_ERR(CAM_OPE, "get io buf fail 0x%x", + io_buf->mem_handle[0]); + return rc; + } + buf_entry = &dump->entries[dump->num_bufs]; + buf_entry->memhdl = io_buf->mem_handle[0]; + buf_entry->iova = iova_addr; + buf_entry->offset = io_buf->plane_offset[0]; + buf_entry->len = size - io_buf->plane_offset[0]; + buf_entry->size = size; + dump->num_bufs++; + if (io_buf->direction == 2) { + output_info = + &dump->outputs[dump->num_outputs]; + output_info->iova = iova_addr; + output_info->offset = io_buf->plane_offset[0]; + output_info->len = size - + io_buf->plane_offset[0]; + dump->num_outputs++; + } + } + } + return rc; +} + +static int cam_ope_dump_frame_process(struct cam_packet *packet, + struct cam_ope_hang_dump *dump) +{ + int rc = 0; + int i; + size_t len; + struct cam_cmd_buf_desc *cmd_desc = NULL; + uintptr_t cpu_addr = 0; + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); + for (i = 0; i < packet->num_cmd_buf; i++) { + if (cmd_desc[i].type != CAM_CMD_BUF_GENERIC || + cmd_desc[i].meta_data == OPE_CMD_META_GENERIC_BLOB) + continue; + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, + &cpu_addr, &len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + cmd_desc[i].mem_handle); + return rc; + } + cpu_addr = cpu_addr + cmd_desc[i].offset; + break; + } + + if (!cpu_addr) { + CAM_ERR(CAM_OPE, "invalid number of cmd buf"); + return -EINVAL; + } + + cam_ope_mgr_dump_cmd_buf(cpu_addr, dump); + cam_ope_mgr_dump_frame_set(cpu_addr, dump); + cam_ope_mgr_put_cmd_buf(packet); + return rc; +} + +static int cam_ope_dump_bls(struct cam_ope_request *ope_req, + struct cam_ope_hang_dump *dump) +{ + struct cam_cdm_bl_request *cdm_cmd; + size_t size; + int i, rc; + dma_addr_t iova_addr; + + cdm_cmd = ope_req->cdm_cmd; + for (i = 0; i < cdm_cmd->cmd_arrary_count; i++) { + rc = cam_mem_get_io_buf(cdm_cmd->cmd[i].bl_addr.mem_handle, + ope_hw_mgr->iommu_hdl, &iova_addr, &size); + if (rc) { + CAM_ERR(CAM_OPE, "get io buf fail 0x%x", + cdm_cmd->cmd[i].bl_addr.mem_handle); + return rc; + } + dump->bl_entries[dump->num_bls].base = + (uint32_t)iova_addr + cdm_cmd->cmd[i].offset; + dump->bl_entries[dump->num_bls].len = cdm_cmd->cmd[i].len; + dump->bl_entries[dump->num_bls].arbitration = + cdm_cmd->cmd[i].arbitrate; + dump->num_bls++; + } + return 0; +} + +static void cam_ope_dump_req_data(struct cam_ope_request *ope_req) +{ + struct cam_ope_hang_dump *dump; + struct cam_packet *packet = + (struct cam_packet *)ope_req->hang_data.packet; + + if (!ope_req->ope_debug_buf.cpu_addr || + ope_req->ope_debug_buf.len < sizeof(struct cam_ope_hang_dump) || + (ope_req->ope_debug_buf.offset + ope_req->ope_debug_buf.len) + > ope_req->ope_debug_buf.size) { + CAM_ERR(CAM_OPE, "Invalid debug buf, size %d %d len %d off %d", + sizeof(struct cam_ope_hang_dump), + ope_req->ope_debug_buf.size, + ope_req->ope_debug_buf.len, + ope_req->ope_debug_buf.offset); + return; + } + + dump = (struct cam_ope_hang_dump *)ope_req->ope_debug_buf.cpu_addr; + memset(dump, 0, sizeof(struct cam_ope_hang_dump)); + dump->num_bufs = 0; + cam_ope_dump_hang_patches(packet, dump); + cam_ope_dump_frame_process(packet, dump); + cam_ope_dump_bls(ope_req, dump); +} + +static bool cam_ope_check_req_delay(struct cam_ope_ctx *ctx_data, + uint64_t req_time) +{ + struct timespec64 ts; + uint64_t ts_ns; + + get_monotonic_boottime64(&ts); + ts_ns = (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); + + if (ts_ns - req_time < + ((ctx_data->req_timer_timeout - + div_u64(ctx_data->req_timer_timeout, 10)) * 1000000)) { + CAM_INFO(CAM_OPE, "ctx: %d, ts_ns : %llu", + ctx_data->ctx_id, ts_ns); + cam_ope_req_timer_reset(ctx_data); + return true; + } + + return false; +} + +static int32_t cam_ope_process_request_timer(void *priv, void *data) +{ + struct ope_clk_work_data *clk_data = (struct ope_clk_work_data *)data; + struct cam_ope_ctx *ctx_data = (struct cam_ope_ctx *)clk_data->data; + struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; + uint32_t id; + struct cam_hw_intf *dev_intf = NULL; + struct cam_ope_clk_info *clk_info; + struct cam_ope_dev_bw_update clk_update; + int i = 0; + int device_share_ratio = 1; + int path_index; + struct crm_workq_task *task; + struct ope_msg_work_data *task_data; + + if (!ctx_data) { + CAM_ERR(CAM_OPE, "ctx_data is NULL, failed to update clk"); + return -EINVAL; + } + + mutex_lock(&ctx_data->ctx_mutex); + if ((ctx_data->ctx_state != OPE_CTX_STATE_ACQUIRED) || + (ctx_data->req_watch_dog_reset_counter == 0)) { + CAM_DBG(CAM_OPE, "state %d counter = %d", ctx_data->ctx_state, + ctx_data->req_watch_dog_reset_counter); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + + if (cam_ope_is_pending_request(ctx_data)) { + + if (cam_ope_check_req_delay(ctx_data, + ctx_data->last_req_time)) { + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + + if (cam_ope_check_req_delay(ctx_data, + ope_hw_mgr->last_callback_time)) { + CAM_WARN(CAM_OPE, + "ope ctx: %d stuck due to other contexts", + ctx_data->ctx_id); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + + if (!cam_cdm_detect_hang_error(ctx_data->ope_cdm.cdm_handle)) { + cam_ope_req_timer_reset(ctx_data); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + + /* Try checking ctx struck again */ + if (cam_ope_check_req_delay(ctx_data, + ope_hw_mgr->last_callback_time)) { + CAM_WARN(CAM_OPE, + "ope ctx: %d stuck due to other contexts", + ctx_data->ctx_id); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + + CAM_ERR(CAM_OPE, + "pending req at HW, ctx %d lrt %llu lct %llu", + ctx_data->ctx_id, ctx_data->last_req_time, + ope_hw_mgr->last_callback_time); + hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_DUMP_DEBUG, + NULL, 0); + + task = cam_req_mgr_workq_get_task(ope_hw_mgr->msg_work); + if (!task) { + CAM_ERR(CAM_OPE, "no empty task"); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + task_data = (struct ope_msg_work_data *)task->payload; + task_data->data = hw_mgr; + task_data->irq_status = 1; + task_data->type = OPE_WORKQ_TASK_MSG_TYPE; + task->process_cb = cam_ope_mgr_process_msg; + cam_req_mgr_workq_enqueue_task(task, ope_hw_mgr, + CRM_TASK_PRIORITY_0); + cam_ope_req_timer_reset(ctx_data); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + + cam_ope_req_timer_modify(ctx_data, ~0); + /* Remove context BW */ + dev_intf = hw_mgr->ope_dev_intf[0]; + if (!dev_intf) { + CAM_ERR(CAM_OPE, "OPE dev intf is NULL"); + mutex_unlock(&ctx_data->ctx_mutex); + return -EINVAL; + } + + clk_info = &hw_mgr->clk_info; + id = OPE_HW_BW_UPDATE; + device_share_ratio = hw_mgr->num_ope; + + clk_update.ahb_vote.type = CAM_VOTE_DYNAMIC; + clk_update.ahb_vote.vote.freq = 0; + clk_update.ahb_vote_valid = false; + + /* + * Remove previous vote of this context from hw mgr first. + * hw_mgr_clk_info has all valid paths, with each path in its + * own index. BW that we wanted to vote now is after removing + * current context's vote from hw mgr consolidated vote + */ + for (i = 0; i < ctx_data->clk_info.num_paths; i++) { + path_index = ctx_data->clk_info.axi_path[i] + .path_data_type - + CAM_AXI_PATH_DATA_OPE_START_OFFSET; + + if (path_index >= CAM_OPE_MAX_PER_PATH_VOTES) { + CAM_WARN(CAM_OPE, + "Invalid path %d, start offset=%d, max=%d", + ctx_data->clk_info.axi_path[i] + .path_data_type, + CAM_AXI_PATH_DATA_OPE_START_OFFSET, + CAM_OPE_MAX_PER_PATH_VOTES); + continue; + } + + clk_info->axi_path[path_index].camnoc_bw -= + ctx_data->clk_info.axi_path[i].camnoc_bw; + clk_info->axi_path[path_index].mnoc_ab_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ab_bw; + clk_info->axi_path[path_index].mnoc_ib_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ib_bw; + clk_info->axi_path[path_index].ddr_ab_bw -= + ctx_data->clk_info.axi_path[i].ddr_ab_bw; + clk_info->axi_path[path_index].ddr_ib_bw -= + ctx_data->clk_info.axi_path[i].ddr_ib_bw; + } + + memset(&ctx_data->clk_info.axi_path[0], 0, + CAM_OPE_MAX_PER_PATH_VOTES * + sizeof(struct cam_axi_per_path_bw_vote)); + ctx_data->clk_info.curr_fc = 0; + ctx_data->clk_info.base_clk = 0; + + clk_update.axi_vote.num_paths = clk_info->num_paths; + memcpy(&clk_update.axi_vote.axi_path[0], + &clk_info->axi_path[0], + clk_update.axi_vote.num_paths * + sizeof(struct cam_axi_per_path_bw_vote)); + + if (device_share_ratio > 1) { + for (i = 0; i < clk_update.axi_vote.num_paths; i++) { + do_div( + clk_update.axi_vote.axi_path[i].camnoc_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].mnoc_ab_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].mnoc_ib_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].ddr_ab_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].ddr_ib_bw, + device_share_ratio); + } + } + + clk_update.axi_vote_valid = true; + dev_intf->hw_ops.process_cmd(dev_intf->hw_priv, id, + &clk_update, sizeof(clk_update)); + + CAM_DBG(CAM_OPE, "X :ctx_id = %d curr_fc = %u bc = %u", + ctx_data->ctx_id, ctx_data->clk_info.curr_fc, + ctx_data->clk_info.base_clk); + mutex_unlock(&ctx_data->ctx_mutex); + + return 0; +} + +static void cam_ope_req_timer_cb(struct timer_list *timer_data) +{ + unsigned long flags; + struct crm_workq_task *task; + struct ope_clk_work_data *task_data; + struct cam_req_mgr_timer *timer = + container_of(timer_data, struct cam_req_mgr_timer, sys_timer); + + spin_lock_irqsave(&ope_hw_mgr->hw_mgr_lock, flags); + task = cam_req_mgr_workq_get_task(ope_hw_mgr->timer_work); + if (!task) { + CAM_ERR(CAM_OPE, "no empty task"); + spin_unlock_irqrestore(&ope_hw_mgr->hw_mgr_lock, flags); + return; + } + + task_data = (struct ope_clk_work_data *)task->payload; + task_data->data = timer->parent; + task_data->type = OPE_WORKQ_TASK_MSG_TYPE; + task->process_cb = cam_ope_process_request_timer; + cam_req_mgr_workq_enqueue_task(task, ope_hw_mgr, + CRM_TASK_PRIORITY_0); + spin_unlock_irqrestore(&ope_hw_mgr->hw_mgr_lock, flags); +} + +static int cam_ope_start_req_timer(struct cam_ope_ctx *ctx_data) +{ + int rc = 0; + + rc = crm_timer_init(&ctx_data->req_watch_dog, + ctx_data->req_timer_timeout, ctx_data, &cam_ope_req_timer_cb); + if (rc) + CAM_ERR(CAM_OPE, "Failed to start timer"); + + ctx_data->req_watch_dog_reset_counter = 0; + + return rc; +} + +static int cam_ope_supported_clk_rates(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data) +{ + int i; + struct cam_hw_soc_info *soc_info; + struct cam_hw_intf *dev_intf = NULL; + struct cam_hw_info *dev = NULL; + + dev_intf = hw_mgr->ope_dev_intf[0]; + if (!dev_intf) { + CAM_ERR(CAM_OPE, "dev_intf is invalid"); + return -EINVAL; + } + + dev = (struct cam_hw_info *)dev_intf->hw_priv; + soc_info = &dev->soc_info; + + for (i = 0; i < CAM_MAX_VOTE; i++) { + ctx_data->clk_info.clk_rate[i] = + soc_info->clk_rate[i][soc_info->src_clk_idx]; + CAM_DBG(CAM_OPE, "clk_info[%d] = %d", + i, ctx_data->clk_info.clk_rate[i]); + } + + return 0; +} + +static int cam_ope_ctx_clk_info_init(struct cam_ope_ctx *ctx_data) +{ + int i; + + ctx_data->clk_info.curr_fc = 0; + ctx_data->clk_info.base_clk = 0; + ctx_data->clk_info.uncompressed_bw = 0; + ctx_data->clk_info.compressed_bw = 0; + + for (i = 0; i < CAM_OPE_MAX_PER_PATH_VOTES; i++) { + ctx_data->clk_info.axi_path[i].camnoc_bw = 0; + ctx_data->clk_info.axi_path[i].mnoc_ab_bw = 0; + ctx_data->clk_info.axi_path[i].mnoc_ib_bw = 0; + } + + cam_ope_supported_clk_rates(ope_hw_mgr, ctx_data); + + return 0; +} + +static int32_t cam_ope_deinit_idle_clk(void *priv, void *data) +{ + struct cam_ope_hw_mgr *hw_mgr = (struct cam_ope_hw_mgr *)priv; + struct ope_clk_work_data *task_data = (struct ope_clk_work_data *)data; + struct cam_ope_clk_info *clk_info = + (struct cam_ope_clk_info *)task_data->data; + uint32_t id; + uint32_t i; + struct cam_ope_ctx *ctx_data; + struct cam_hw_intf *dev_intf = NULL; + int rc = 0; + bool busy = false; + + clk_info->base_clk = 0; + clk_info->curr_clk = 0; + clk_info->over_clked = 0; + + mutex_lock(&hw_mgr->hw_mgr_mutex); + + for (i = 0; i < OPE_CTX_MAX; i++) { + ctx_data = &hw_mgr->ctx[i]; + mutex_lock(&ctx_data->ctx_mutex); + if (ctx_data->ctx_state == OPE_CTX_STATE_ACQUIRED) { + busy = cam_ope_is_pending_request(ctx_data); + if (busy) { + mutex_unlock(&ctx_data->ctx_mutex); + break; + } + cam_ope_ctx_clk_info_init(ctx_data); + } + mutex_unlock(&ctx_data->ctx_mutex); + } + + if (busy) { + cam_ope_device_timer_reset(hw_mgr); + rc = -EBUSY; + goto done; + } + + dev_intf = hw_mgr->ope_dev_intf[0]; + id = OPE_HW_CLK_DISABLE; + + CAM_DBG(CAM_OPE, "Disable %d", clk_info->hw_type); + + dev_intf->hw_ops.process_cmd(dev_intf->hw_priv, id, NULL, 0); + +done: + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static void cam_ope_device_timer_cb(struct timer_list *timer_data) +{ + unsigned long flags; + struct crm_workq_task *task; + struct ope_clk_work_data *task_data; + struct cam_req_mgr_timer *timer = + container_of(timer_data, struct cam_req_mgr_timer, sys_timer); + + spin_lock_irqsave(&ope_hw_mgr->hw_mgr_lock, flags); + task = cam_req_mgr_workq_get_task(ope_hw_mgr->timer_work); + if (!task) { + CAM_ERR(CAM_OPE, "no empty task"); + spin_unlock_irqrestore(&ope_hw_mgr->hw_mgr_lock, flags); + return; + } + + task_data = (struct ope_clk_work_data *)task->payload; + task_data->data = timer->parent; + task_data->type = OPE_WORKQ_TASK_MSG_TYPE; + task->process_cb = cam_ope_deinit_idle_clk; + cam_req_mgr_workq_enqueue_task(task, ope_hw_mgr, + CRM_TASK_PRIORITY_0); + spin_unlock_irqrestore(&ope_hw_mgr->hw_mgr_lock, flags); +} + +static int cam_ope_device_timer_start(struct cam_ope_hw_mgr *hw_mgr) +{ + int rc = 0; + int i; + + for (i = 0; i < CLK_HW_MAX; i++) { + if (!hw_mgr->clk_info.watch_dog) { + rc = crm_timer_init(&hw_mgr->clk_info.watch_dog, + OPE_DEVICE_IDLE_TIMEOUT, &hw_mgr->clk_info, + &cam_ope_device_timer_cb); + + if (rc) + CAM_ERR(CAM_OPE, "Failed to start timer %d", i); + + hw_mgr->clk_info.watch_dog_reset_counter = 0; + } + } + + return rc; +} + +static int cam_ope_get_actual_clk_rate_idx( + struct cam_ope_ctx *ctx_data, uint32_t base_clk) +{ + int i; + + for (i = 0; i < CAM_MAX_VOTE; i++) + if (ctx_data->clk_info.clk_rate[i] >= base_clk) + return i; + + /* + * Caller has to ensure returned index is within array + * size bounds while accessing that index. + */ + + return i; +} + +static bool cam_ope_is_over_clk(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_ope_clk_info *hw_mgr_clk_info) +{ + int base_clk_idx; + int curr_clk_idx; + + base_clk_idx = cam_ope_get_actual_clk_rate_idx(ctx_data, + hw_mgr_clk_info->base_clk); + + curr_clk_idx = cam_ope_get_actual_clk_rate_idx(ctx_data, + hw_mgr_clk_info->curr_clk); + + CAM_DBG(CAM_OPE, "bc_idx = %d cc_idx = %d %d %d", + base_clk_idx, curr_clk_idx, hw_mgr_clk_info->base_clk, + hw_mgr_clk_info->curr_clk); + + if (curr_clk_idx > base_clk_idx) + return true; + + return false; +} + + +static int cam_ope_get_lower_clk_rate(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t base_clk) +{ + int i; + + i = cam_ope_get_actual_clk_rate_idx(ctx_data, base_clk); + + while (i > 0) { + if (ctx_data->clk_info.clk_rate[i - 1]) + return ctx_data->clk_info.clk_rate[i - 1]; + i--; + } + + CAM_DBG(CAM_OPE, "Already clk at lower level"); + + return base_clk; +} + +static int cam_ope_get_next_clk_rate(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t base_clk) +{ + int i; + + i = cam_ope_get_actual_clk_rate_idx(ctx_data, base_clk); + + while (i < CAM_MAX_VOTE - 1) { + if (ctx_data->clk_info.clk_rate[i + 1]) + return ctx_data->clk_info.clk_rate[i + 1]; + i++; + } + + CAM_DBG(CAM_OPE, "Already clk at higher level"); + + return base_clk; +} + +static int cam_ope_get_actual_clk_rate(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t base_clk) +{ + int i; + + for (i = 0; i < CAM_MAX_VOTE; i++) + if (ctx_data->clk_info.clk_rate[i] >= base_clk) + return ctx_data->clk_info.clk_rate[i]; + + return base_clk; +} + +static int cam_ope_calc_total_clk(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_clk_info *hw_mgr_clk_info, uint32_t dev_type) +{ + int i; + struct cam_ope_ctx *ctx_data; + + hw_mgr_clk_info->base_clk = 0; + for (i = 0; i < OPE_CTX_MAX; i++) { + ctx_data = &hw_mgr->ctx[i]; + if (ctx_data->ctx_state == OPE_CTX_STATE_ACQUIRED) + hw_mgr_clk_info->base_clk += + ctx_data->clk_info.base_clk; + } + + return 0; +} + +static uint32_t cam_ope_mgr_calc_base_clk(uint32_t frame_cycles, + uint64_t budget) +{ + uint64_t mul = 1000000000; + uint64_t base_clk = frame_cycles * mul; + + do_div(base_clk, budget); + + CAM_DBG(CAM_OPE, "budget = %lld fc = %d ib = %lld base_clk = %lld", + budget, frame_cycles, + (long long)(frame_cycles * mul), base_clk); + + return base_clk; +} + +static bool cam_ope_update_clk_overclk_free(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_ope_clk_info *hw_mgr_clk_info, + struct cam_ope_clk_bw_request *clk_info, + uint32_t base_clk) +{ + int rc = false; + + /* + * In caseof no pending packets case + * 1. In caseof overclk cnt is less than threshold, increase + * overclk count and no update in the clock rate + * 2. In caseof overclk cnt is greater than or equal to threshold + * then lower clock rate by one level and update hw_mgr current + * clock value. + * a. In case of new clock rate greater than sum of clock + * rates, reset overclk count value to zero if it is + * overclock + * b. if it is less than sum of base clocks then go to next + * level of clock and make overclk count to zero + * c. if it is same as sum of base clock rates update overclock + * cnt to 0 + */ + if (hw_mgr_clk_info->over_clked < hw_mgr_clk_info->threshold) { + hw_mgr_clk_info->over_clked++; + rc = false; + } else { + hw_mgr_clk_info->curr_clk = + cam_ope_get_lower_clk_rate(hw_mgr, ctx_data, + hw_mgr_clk_info->curr_clk); + if (hw_mgr_clk_info->curr_clk > hw_mgr_clk_info->base_clk) { + if (cam_ope_is_over_clk(hw_mgr, ctx_data, + hw_mgr_clk_info)) + hw_mgr_clk_info->over_clked = 0; + } else if (hw_mgr_clk_info->curr_clk < + hw_mgr_clk_info->base_clk) { + hw_mgr_clk_info->curr_clk = + cam_ope_get_next_clk_rate(hw_mgr, ctx_data, + hw_mgr_clk_info->curr_clk); + hw_mgr_clk_info->over_clked = 0; + } else if (hw_mgr_clk_info->curr_clk == + hw_mgr_clk_info->base_clk) { + hw_mgr_clk_info->over_clked = 0; + } + rc = true; + } + + return rc; +} + +static bool cam_ope_update_clk_free(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_ope_clk_info *hw_mgr_clk_info, + struct cam_ope_clk_bw_request *clk_info, + uint32_t base_clk) +{ + int rc = false; + bool over_clocked = false; + + ctx_data->clk_info.curr_fc = clk_info->frame_cycles; + ctx_data->clk_info.base_clk = base_clk; + cam_ope_calc_total_clk(hw_mgr, hw_mgr_clk_info, + ctx_data->ope_acquire.dev_type); + + /* + * Current clock is not always sum of base clocks, due to + * clock scales update to next higher or lower levels, it + * equals to one of discrete clock values supported by hardware. + * So even current clock is higher than sum of base clocks, we + * can not consider it is over clocked. if it is greater than + * discrete clock level then only it is considered as over clock. + * 1. Handle over clock case + * 2. If current clock is less than sum of base clocks + * update current clock + * 3. If current clock is same as sum of base clocks no action + */ + + over_clocked = cam_ope_is_over_clk(hw_mgr, ctx_data, + hw_mgr_clk_info); + + if (hw_mgr_clk_info->curr_clk > hw_mgr_clk_info->base_clk && + over_clocked) { + rc = cam_ope_update_clk_overclk_free(hw_mgr, ctx_data, + hw_mgr_clk_info, clk_info, base_clk); + } else if (hw_mgr_clk_info->curr_clk > hw_mgr_clk_info->base_clk) { + hw_mgr_clk_info->over_clked = 0; + rc = false; + } else if (hw_mgr_clk_info->curr_clk < hw_mgr_clk_info->base_clk) { + hw_mgr_clk_info->curr_clk = cam_ope_get_actual_clk_rate(hw_mgr, + ctx_data, hw_mgr_clk_info->base_clk); + rc = true; + } + + return rc; +} + +static bool cam_ope_update_clk_busy(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_ope_clk_info *hw_mgr_clk_info, + struct cam_ope_clk_bw_request *clk_info, + uint32_t base_clk) +{ + uint32_t next_clk_level; + uint32_t actual_clk; + bool rc = false; + + /* 1. if current request frame cycles(fc) are more than previous + * frame fc + * Calculate the new base clock. + * if sum of base clocks are more than next available clk level + * Update clock rate, change curr_clk_rate to sum of base clock + * rates and make over_clked to zero + * else + * Update clock rate to next level, update curr_clk_rate and make + * overclked cnt to zero + * 2. if current fc is less than or equal to previous frame fc + * Still Bump up the clock to next available level + * if it is available, then update clock, make overclk cnt to + * zero. If the clock is already at highest clock rate then + * no need to update the clock + */ + ctx_data->clk_info.base_clk = base_clk; + hw_mgr_clk_info->over_clked = 0; + if (clk_info->frame_cycles > ctx_data->clk_info.curr_fc) { + cam_ope_calc_total_clk(hw_mgr, hw_mgr_clk_info, + ctx_data->ope_acquire.dev_type); + actual_clk = cam_ope_get_actual_clk_rate(hw_mgr, + ctx_data, base_clk); + if (hw_mgr_clk_info->base_clk > actual_clk) { + hw_mgr_clk_info->curr_clk = hw_mgr_clk_info->base_clk; + } else { + next_clk_level = cam_ope_get_next_clk_rate(hw_mgr, + ctx_data, hw_mgr_clk_info->curr_clk); + hw_mgr_clk_info->curr_clk = next_clk_level; + } + rc = true; + } else { + next_clk_level = + cam_ope_get_next_clk_rate(hw_mgr, ctx_data, + hw_mgr_clk_info->curr_clk); + if (hw_mgr_clk_info->curr_clk < next_clk_level) { + hw_mgr_clk_info->curr_clk = next_clk_level; + rc = true; + } + } + ctx_data->clk_info.curr_fc = clk_info->frame_cycles; + + return rc; +} + +static bool cam_ope_check_clk_update(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, int idx) +{ + bool busy = false, rc = false; + uint32_t base_clk; + struct cam_ope_clk_bw_request *clk_info; + uint64_t req_id; + struct cam_ope_clk_info *hw_mgr_clk_info; + + /* TODO: Have default clock rates update */ + /* TODO: Add support for debug clock updates */ + cam_ope_req_timer_reset(ctx_data); + cam_ope_device_timer_reset(hw_mgr); + hw_mgr_clk_info = &hw_mgr->clk_info; + req_id = ctx_data->req_list[idx]->request_id; + if (ctx_data->req_cnt > 1) + busy = true; + + CAM_DBG(CAM_OPE, "busy = %d req_id = %lld", busy, req_id); + + clk_info = &ctx_data->req_list[idx]->clk_info; + + /* Calculate base clk rate */ + base_clk = cam_ope_mgr_calc_base_clk( + clk_info->frame_cycles, clk_info->budget_ns); + ctx_data->clk_info.rt_flag = clk_info->rt_flag; + + if (busy) + rc = cam_ope_update_clk_busy(hw_mgr, ctx_data, + hw_mgr_clk_info, clk_info, base_clk); + else + rc = cam_ope_update_clk_free(hw_mgr, ctx_data, + hw_mgr_clk_info, clk_info, base_clk); + + CAM_DBG(CAM_OPE, "bc = %d cc = %d busy = %d overclk = %d uc = %d", + hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk, + busy, hw_mgr_clk_info->over_clked, rc); + + return rc; +} + +static int cam_ope_mgr_update_clk_rate(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data) +{ + struct cam_ope_dev_clk_update clk_upd_cmd; + int i; + + clk_upd_cmd.clk_rate = hw_mgr->clk_info.curr_clk; + + CAM_DBG(CAM_PERF, "clk_rate %u for dev_type %d", clk_upd_cmd.clk_rate, + ctx_data->ope_acquire.dev_type); + + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_CLK_UPDATE, + &clk_upd_cmd, sizeof(clk_upd_cmd)); + } + + return 0; +} + +static int cam_ope_mgr_calculate_num_path( + struct cam_ope_clk_bw_req_internal_v2 *clk_info, + struct cam_ope_ctx *ctx_data) +{ + int i, path_index = 0; + + for (i = 0; i < CAM_OPE_MAX_PER_PATH_VOTES; i++) { + if ((clk_info->axi_path[i].path_data_type < + CAM_AXI_PATH_DATA_OPE_START_OFFSET) || + (clk_info->axi_path[i].path_data_type > + CAM_AXI_PATH_DATA_OPE_MAX_OFFSET) || + ((clk_info->axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_OPE_START_OFFSET) >= + CAM_OPE_MAX_PER_PATH_VOTES)) { + CAM_DBG(CAM_OPE, + "Invalid path %d, start offset=%d, max=%d", + ctx_data->clk_info.axi_path[i].path_data_type, + CAM_AXI_PATH_DATA_OPE_START_OFFSET, + CAM_OPE_MAX_PER_PATH_VOTES); + continue; + } + + path_index = clk_info->axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_OPE_START_OFFSET; + + CAM_DBG(CAM_OPE, + "clk_info: i[%d]: [%s %s] bw [%lld %lld] num_path: %d", + i, + cam_cpas_axi_util_trans_type_to_string( + clk_info->axi_path[i].transac_type), + cam_cpas_axi_util_path_type_to_string( + clk_info->axi_path[i].path_data_type), + clk_info->axi_path[i].camnoc_bw, + clk_info->axi_path[i].mnoc_ab_bw, + clk_info->num_paths); + } + + return (path_index+1); +} + +static bool cam_ope_update_bw_v2(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_ope_clk_info *hw_mgr_clk_info, + struct cam_ope_clk_bw_req_internal_v2 *clk_info, + bool busy) +{ + int i, path_index; + bool update_required = true; + + /* + * If current request bandwidth is different from previous frames, then + * recalculate bandwidth of all contexts of same hardware and update + * voting of bandwidth + */ + + for (i = 0; i < clk_info->num_paths; i++) + CAM_DBG(CAM_OPE, "clk_info camnoc = %lld busy = %d", + clk_info->axi_path[i].camnoc_bw, busy); + + if (clk_info->num_paths == ctx_data->clk_info.num_paths) { + update_required = false; + for (i = 0; i < clk_info->num_paths; i++) { + if ((clk_info->axi_path[i].transac_type == + ctx_data->clk_info.axi_path[i].transac_type) && + (clk_info->axi_path[i].path_data_type == + ctx_data->clk_info.axi_path[i].path_data_type) && + (clk_info->axi_path[i].camnoc_bw == + ctx_data->clk_info.axi_path[i].camnoc_bw) && + (clk_info->axi_path[i].mnoc_ab_bw == + ctx_data->clk_info.axi_path[i].mnoc_ab_bw)) { + continue; + } else { + update_required = true; + break; + } + } + } + + if (!update_required) { + CAM_DBG(CAM_OPE, + "Incoming BW hasn't changed, no update required"); + return false; + } + + if (busy) { + for (i = 0; i < clk_info->num_paths; i++) { + if (ctx_data->clk_info.axi_path[i].camnoc_bw > + clk_info->axi_path[i].camnoc_bw) + return false; + } + } + + /* + * Remove previous vote of this context from hw mgr first. + * hw_mgr_clk_info has all valid paths, with each path in its own index + */ + for (i = 0; i < ctx_data->clk_info.num_paths; i++) { + path_index = + ctx_data->clk_info.axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_OPE_START_OFFSET; + + if (path_index >= CAM_OPE_MAX_PER_PATH_VOTES) { + CAM_WARN(CAM_OPE, + "Invalid path %d, start offset=%d, max=%d", + ctx_data->clk_info.axi_path[i].path_data_type, + CAM_AXI_PATH_DATA_OPE_START_OFFSET, + CAM_OPE_MAX_PER_PATH_VOTES); + continue; + } + + hw_mgr_clk_info->axi_path[path_index].camnoc_bw -= + ctx_data->clk_info.axi_path[i].camnoc_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ab_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ab_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ib_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw -= + ctx_data->clk_info.axi_path[i].ddr_ab_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw -= + ctx_data->clk_info.axi_path[i].ddr_ib_bw; + } + + ctx_data->clk_info.num_paths = + cam_ope_mgr_calculate_num_path(clk_info, ctx_data); + + memcpy(&ctx_data->clk_info.axi_path[0], + &clk_info->axi_path[0], + clk_info->num_paths * sizeof(struct cam_axi_per_path_bw_vote)); + + /* + * Add new vote of this context in hw mgr. + * hw_mgr_clk_info has all paths, with each path in its own index + */ + for (i = 0; i < ctx_data->clk_info.num_paths; i++) { + path_index = + ctx_data->clk_info.axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_OPE_START_OFFSET; + + if (path_index >= CAM_OPE_MAX_PER_PATH_VOTES) { + CAM_WARN(CAM_OPE, + "Invalid path %d, start offset=%d, max=%d", + ctx_data->clk_info.axi_path[i].path_data_type, + CAM_AXI_PATH_DATA_OPE_START_OFFSET, + CAM_OPE_MAX_PER_PATH_VOTES); + continue; + } + + hw_mgr_clk_info->axi_path[path_index].path_data_type = + ctx_data->clk_info.axi_path[i].path_data_type; + hw_mgr_clk_info->axi_path[path_index].transac_type = + ctx_data->clk_info.axi_path[i].transac_type; + hw_mgr_clk_info->axi_path[path_index].camnoc_bw += + ctx_data->clk_info.axi_path[i].camnoc_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ab_bw += + ctx_data->clk_info.axi_path[i].mnoc_ab_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw += + ctx_data->clk_info.axi_path[i].mnoc_ib_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw += + ctx_data->clk_info.axi_path[i].ddr_ab_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw += + ctx_data->clk_info.axi_path[i].ddr_ib_bw; + CAM_DBG(CAM_OPE, + "Consolidate Path Vote : Dev[%s] i[%d] path_idx[%d] : [%s %s] [%lld %lld]", + ctx_data->ope_acquire.dev_name, + i, path_index, + cam_cpas_axi_util_trans_type_to_string( + hw_mgr_clk_info->axi_path[path_index].transac_type), + cam_cpas_axi_util_path_type_to_string( + hw_mgr_clk_info->axi_path[path_index].path_data_type), + hw_mgr_clk_info->axi_path[path_index].camnoc_bw, + hw_mgr_clk_info->axi_path[path_index].mnoc_ab_bw); + } + + if (hw_mgr_clk_info->num_paths < ctx_data->clk_info.num_paths) + hw_mgr_clk_info->num_paths = ctx_data->clk_info.num_paths; + + return true; +} + +static bool cam_ope_check_bw_update(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, int idx) +{ + bool busy = false, bw_updated = false; + int i; + struct cam_ope_clk_bw_req_internal_v2 *clk_info_v2; + struct cam_ope_clk_info *hw_mgr_clk_info; + uint64_t req_id; + + hw_mgr_clk_info = &hw_mgr->clk_info; + req_id = ctx_data->req_list[idx]->request_id; + if (ctx_data->req_cnt > 1) + busy = true; + + clk_info_v2 = &ctx_data->req_list[idx]->clk_info_v2; + + bw_updated = cam_ope_update_bw_v2(hw_mgr, ctx_data, + hw_mgr_clk_info, clk_info_v2, busy); + + for (i = 0; i < hw_mgr_clk_info->num_paths; i++) { + CAM_DBG(CAM_OPE, + "Final path_type: %s, transac_type: %s, camnoc_bw = %lld mnoc_ab_bw = %lld, mnoc_ib_bw = %lld, device: %s", + cam_cpas_axi_util_path_type_to_string( + hw_mgr_clk_info->axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + hw_mgr_clk_info->axi_path[i].transac_type), + hw_mgr_clk_info->axi_path[i].camnoc_bw, + hw_mgr_clk_info->axi_path[i].mnoc_ab_bw, + hw_mgr_clk_info->axi_path[i].mnoc_ib_bw, + ctx_data->ope_acquire.dev_name); + } + + return bw_updated; +} + +static int cam_ope_update_cpas_vote(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data) +{ + int i = 0; + struct cam_ope_clk_info *clk_info; + struct cam_ope_dev_bw_update bw_update = {{0}, {0}, 0, 0}; + + clk_info = &hw_mgr->clk_info; + + bw_update.ahb_vote.type = CAM_VOTE_DYNAMIC; + bw_update.ahb_vote.vote.freq = 0; + bw_update.ahb_vote_valid = false; + + + bw_update.axi_vote.num_paths = clk_info->num_paths; + memcpy(&bw_update.axi_vote.axi_path[0], + &clk_info->axi_path[0], + bw_update.axi_vote.num_paths * + sizeof(struct cam_axi_per_path_bw_vote)); + + bw_update.axi_vote_valid = true; + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_BW_UPDATE, + &bw_update, sizeof(bw_update)); + } + + return 0; +} + +static int cam_ope_mgr_ope_clk_update(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, int idx) +{ + int rc = 0; + + if (cam_ope_check_clk_update(hw_mgr, ctx_data, idx)) + rc = cam_ope_mgr_update_clk_rate(hw_mgr, ctx_data); + + if (cam_ope_check_bw_update(hw_mgr, ctx_data, idx)) + rc |= cam_ope_update_cpas_vote(hw_mgr, ctx_data); + + return rc; +} + +static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, + enum cam_cdm_cb_status status, uint64_t cookie) +{ + int rc = 0; + struct cam_ope_ctx *ctx; + struct cam_ope_request *ope_req; + struct cam_hw_done_event_data buf_data; + struct timespec64 ts; + bool flag = false; + bool dump_flag = true; + int i; + + if (!userdata) { + CAM_ERR(CAM_OPE, "Invalid ctx from CDM callback"); + return; + } + + if (cookie >= CAM_CTX_REQ_MAX) { + CAM_ERR(CAM_OPE, "Invalid reqIdx = %llu", cookie); + return; + } + + ctx = userdata; + mutex_lock(&ctx->ctx_mutex); + + if (!test_bit(cookie, ctx->bitmap)) { + CAM_ERR(CAM_OPE, "Req not present reqIdx = %d for ctx_id = %d", + cookie, ctx->ctx_id); + goto end; + } + + ope_req = ctx->req_list[cookie]; + + get_monotonic_boottime64(&ts); + ope_hw_mgr->last_callback_time = (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); + + CAM_DBG(CAM_REQ, + "hdl=%x, udata=%pK, status=%d, cookie=%d", + handle, userdata, status, cookie); + CAM_DBG(CAM_REQ, "req_id= %llu ctx_id= %d lcb=%llu", + ope_req->request_id, ctx->ctx_id, + ope_hw_mgr->last_callback_time); + + if (ctx->ctx_state != OPE_CTX_STATE_ACQUIRED) { + CAM_ERR(CAM_OPE, "ctx %u is in %d state", + ctx->ctx_id, ctx->ctx_state); + mutex_unlock(&ctx->ctx_mutex); + return; + } + + if (status == CAM_CDM_CB_STATUS_BL_SUCCESS) { + CAM_DBG(CAM_OPE, + "hdl=%x, udata=%pK, status=%d, cookie=%d req_id=%llu ctx_id=%d", + handle, userdata, status, cookie, + ope_req->request_id, ctx->ctx_id); + cam_ope_req_timer_reset(ctx); + cam_ope_device_timer_reset(ope_hw_mgr); + } else if (status == CAM_CDM_CB_STATUS_HW_RESUBMIT) { + CAM_INFO(CAM_OPE, "After reset of CDM and OPE, reapply req"); + rc = cam_ope_mgr_reapply_config(ope_hw_mgr, ctx, ope_req); + if (!rc) + goto end; + } else { + CAM_INFO(CAM_OPE, + "CDM hdl=%x, udata=%pK, status=%d, cookie=%d req_id = %llu ctx_id=%d", + handle, userdata, status, cookie, + ope_req->request_id, ctx->ctx_id); + CAM_INFO(CAM_OPE, "Rst of CDM and OPE for error reqid = %lld", + ope_req->request_id); + + if (status != CAM_CDM_CB_STATUS_HW_FLUSH) { + cam_ope_dump_req_data(ope_req); + dump_flag = false; + + CAM_INFO(CAM_OPE, "bach_size: %d", + ctx->req_list[cookie]->num_batch); + for (i = 0; i < ctx->req_list[cookie]->num_batch; i++) + CAM_INFO(CAM_OPE, "i: %d num_stripes: %d", + i, + ctx->req_list[cookie]->num_stripes[i]); + } + rc = cam_ope_mgr_reset_hw(); + flag = true; + } + + if (ope_hw_mgr->dump_req_data_enable && dump_flag) + cam_ope_dump_req_data(ope_req); + + ctx->req_cnt--; + + buf_data.request_id = ope_req->request_id; + ope_req->request_id = 0; + kzfree(ctx->req_list[cookie]->cdm_cmd); + ctx->req_list[cookie]->cdm_cmd = NULL; + cam_ope_free_io_config(ctx->req_list[cookie]); + kzfree(ctx->req_list[cookie]); + ctx->req_list[cookie] = NULL; + clear_bit(cookie, ctx->bitmap); + ctx->ctxt_event_cb(ctx->context_priv, flag, &buf_data); + +end: + mutex_unlock(&ctx->ctx_mutex); +} + +int32_t cam_ope_hw_mgr_cb(uint32_t irq_status, void *data) +{ + int32_t rc = 0; + unsigned long flags; + struct cam_ope_hw_mgr *hw_mgr = data; + struct crm_workq_task *task; + struct ope_msg_work_data *task_data; + + if (!data) { + CAM_ERR(CAM_OPE, "irq cb data is NULL"); + return rc; + } + + spin_lock_irqsave(&hw_mgr->hw_mgr_lock, flags); + task = cam_req_mgr_workq_get_task(ope_hw_mgr->msg_work); + if (!task) { + CAM_ERR(CAM_OPE, "no empty task"); + spin_unlock_irqrestore(&hw_mgr->hw_mgr_lock, flags); + return -ENOMEM; + } + + task_data = (struct ope_msg_work_data *)task->payload; + task_data->data = hw_mgr; + task_data->irq_status = irq_status; + task_data->type = OPE_WORKQ_TASK_MSG_TYPE; + task->process_cb = cam_ope_mgr_process_msg; + rc = cam_req_mgr_workq_enqueue_task(task, ope_hw_mgr, + CRM_TASK_PRIORITY_0); + spin_unlock_irqrestore(&hw_mgr->hw_mgr_lock, flags); + + return rc; +} + +static int cam_ope_mgr_create_kmd_buf(struct cam_ope_hw_mgr *hw_mgr, + struct cam_packet *packet, + struct cam_hw_prepare_update_args *prepare_args, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uintptr_t ope_cmd_buf_addr) +{ + int i, rc = 0; + struct cam_ope_dev_prepare_req prepare_req; + + prepare_req.ctx_data = ctx_data; + prepare_req.hw_mgr = hw_mgr; + prepare_req.packet = packet; + prepare_req.prepare_args = prepare_args; + prepare_req.req_idx = req_idx; + prepare_req.kmd_buf_offset = 0; + prepare_req.frame_process = + (struct ope_frame_process *)ope_cmd_buf_addr; + + for (i = 0; i < ope_hw_mgr->num_ope; i++) + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_PREPARE, &prepare_req, sizeof(prepare_req)); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Dev prepare failed: %d", rc); + goto end; + } + +end: + return rc; +} + +static int cam_ope_mgr_process_io_cfg(struct cam_ope_hw_mgr *hw_mgr, + struct cam_packet *packet, + struct cam_hw_prepare_update_args *prep_arg, + struct cam_ope_ctx *ctx_data, uint32_t req_idx) +{ + + int i, j = 0, k = 0, l, rc = 0; + struct ope_io_buf *io_buf; + int32_t sync_in_obj[CAM_MAX_IN_RES]; + int32_t merged_sync_in_obj; + struct cam_ope_request *ope_request; + + ope_request = ctx_data->req_list[req_idx]; + prep_arg->num_out_map_entries = 0; + prep_arg->num_in_map_entries = 0; + + ope_request = ctx_data->req_list[req_idx]; + CAM_DBG(CAM_OPE, "E: req_idx = %u %x", req_idx, packet); + + for (i = 0; i < ope_request->num_batch; i++) { + for (l = 0; l < ope_request->num_io_bufs[i]; l++) { + io_buf = ope_request->io_buf[i][l]; + if (io_buf->direction == CAM_BUF_INPUT) { + if (io_buf->fence != -1) { + if (j < CAM_MAX_IN_RES) { + sync_in_obj[j++] = + io_buf->fence; + prep_arg->num_in_map_entries++; + } else { + CAM_ERR(CAM_OPE, + "reached max in_res %d %d", + io_buf->resource_type, + ope_request->request_id); + } + } else { + CAM_ERR(CAM_OPE, "Invalid fence %d %d", + io_buf->resource_type, + ope_request->request_id); + } + } else { + if (io_buf->fence != -1) { + prep_arg->out_map_entries[k].sync_id = + io_buf->fence; + k++; + prep_arg->num_out_map_entries++; + } else { + if (io_buf->resource_type + != OPE_OUT_RES_STATS_LTM) { + CAM_ERR(CAM_OPE, + "Invalid fence %d %d", + io_buf->resource_type, + ope_request->request_id); + } + } + } + CAM_DBG(CAM_REQ, + "ctx_id: %u req_id: %llu dir[%d] %u, fence: %d", + ctx_data->ctx_id, packet->header.request_id, i, + io_buf->direction, io_buf->fence); + CAM_DBG(CAM_REQ, "rsc_type = %u fmt = %d", + io_buf->resource_type, + io_buf->format); + } + } + + if (prep_arg->num_in_map_entries > 1 && + prep_arg->num_in_map_entries <= CAM_MAX_IN_RES) + prep_arg->num_in_map_entries = + cam_common_util_remove_duplicate_arr( + sync_in_obj, prep_arg->num_in_map_entries); + + if (prep_arg->num_in_map_entries > 1 && + prep_arg->num_in_map_entries <= CAM_MAX_IN_RES) { + rc = cam_sync_merge(&sync_in_obj[0], + prep_arg->num_in_map_entries, &merged_sync_in_obj); + if (rc) { + prep_arg->num_out_map_entries = 0; + prep_arg->num_in_map_entries = 0; + return rc; + } + + ope_request->in_resource = merged_sync_in_obj; + + prep_arg->in_map_entries[0].sync_id = merged_sync_in_obj; + prep_arg->num_in_map_entries = 1; + CAM_DBG(CAM_REQ, "ctx_id: %u req_id: %llu Merged Sync obj: %d", + ctx_data->ctx_id, packet->header.request_id, + merged_sync_in_obj); + } else if (prep_arg->num_in_map_entries == 1) { + prep_arg->in_map_entries[0].sync_id = sync_in_obj[0]; + prep_arg->num_in_map_entries = 1; + ope_request->in_resource = 0; + CAM_DBG(CAM_OPE, "fence = %d", sync_in_obj[0]); + } else { + CAM_DBG(CAM_OPE, "Invalid count of input fences, count: %d", + prep_arg->num_in_map_entries); + prep_arg->num_in_map_entries = 0; + ope_request->in_resource = 0; + rc = -EINVAL; + } + return rc; +} + +static void cam_ope_mgr_print_stripe_info(uint32_t batch, + uint32_t io_buf, uint32_t plane, uint32_t stripe, + struct ope_stripe_io *stripe_info, uint64_t iova_addr) +{ + CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d: E", + batch, io_buf, plane, stripe); + CAM_DBG(CAM_OPE, "width: %d s_h: %u s_s: %u", + stripe_info->width, stripe_info->height, + stripe_info->stride); + CAM_DBG(CAM_OPE, "s_xinit = %u iova = %x s_loc = %u", + stripe_info->x_init, iova_addr, stripe_info->s_location); + CAM_DBG(CAM_OPE, "s_off = %u s_format = %u s_len = %u d_bus %d", + stripe_info->offset, stripe_info->format, + stripe_info->len, stripe_info->disable_bus); + CAM_DBG(CAM_OPE, "s_align = %u s_pack = %u s_unpack = %u", + stripe_info->alignment, stripe_info->pack_format, + stripe_info->unpack_format); + CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d: E", + batch, io_buf, plane, stripe); +} + +static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, + struct cam_packet *packet, struct cam_ope_ctx *ctx_data, + uintptr_t frame_process_addr, size_t length, uint32_t req_idx) +{ + int rc = 0; + int i, j, k, l; + dma_addr_t iova_addr; + size_t len; + struct ope_frame_process *in_frame_process; + struct ope_frame_set *in_frame_set; + struct ope_io_buf_info *in_io_buf; + struct ope_stripe_info *in_stripe_info; + struct cam_ope_request *ope_request; + struct ope_io_buf *io_buf; + struct ope_stripe_io *stripe_info; + uint32_t alignment; + uint32_t rsc_idx; + uint32_t pack_format; + uint32_t unpack_format; + struct ope_in_res_info *in_res; + struct ope_out_res_info *out_res; + bool is_secure; + + in_frame_process = (struct ope_frame_process *)frame_process_addr; + + ope_request = ctx_data->req_list[req_idx]; + ope_request->num_batch = in_frame_process->batch_size; + + for (i = 0; i < in_frame_process->batch_size; i++) { + in_frame_set = &in_frame_process->frame_set[i]; + for (j = 0; j < in_frame_set->num_io_bufs; j++) { + in_io_buf = &in_frame_set->io_buf[j]; + for (k = 0; k < in_io_buf->num_planes; k++) { + if (!in_io_buf->num_stripes[k]) { + CAM_ERR(CAM_OPE, "Null num_stripes"); + return -EINVAL; + } + for (l = 0; l < in_io_buf->num_stripes[k]; + l++) { + in_stripe_info = + &in_io_buf->stripe_info[k][l]; + } + } + } + } + + for (i = 0; i < ope_request->num_batch; i++) { + in_frame_set = &in_frame_process->frame_set[i]; + ope_request->num_io_bufs[i] = in_frame_set->num_io_bufs; + if (in_frame_set->num_io_bufs > OPE_MAX_IO_BUFS) { + CAM_ERR(CAM_OPE, "Wrong number of io buffers: %d", + in_frame_set->num_io_bufs); + return -EINVAL; + } + + for (j = 0; j < in_frame_set->num_io_bufs; j++) { + in_io_buf = &in_frame_set->io_buf[j]; + ope_request->io_buf[i][j] = + kzalloc(sizeof(struct ope_io_buf), GFP_KERNEL); + if (!ope_request->io_buf[i][j]) { + CAM_ERR(CAM_OPE, + "IO config allocation failure"); + cam_ope_free_io_config(ope_request); + return -ENOMEM; + } + io_buf = ope_request->io_buf[i][j]; + if (in_io_buf->num_planes > OPE_MAX_PLANES) { + CAM_ERR(CAM_OPE, "wrong number of planes: %u", + in_io_buf->num_planes); + return -EINVAL; + } + + io_buf->num_planes = in_io_buf->num_planes; + io_buf->resource_type = in_io_buf->resource_type; + io_buf->direction = in_io_buf->direction; + io_buf->fence = in_io_buf->fence; + io_buf->format = in_io_buf->format; + + rc = cam_ope_mgr_get_rsc_idx(ctx_data, in_io_buf); + if (rc < 0) { + CAM_ERR(CAM_OPE, "Invalid rsc idx = %d", rc); + return rc; + } + rsc_idx = rc; + if (in_io_buf->direction == CAM_BUF_INPUT) { + in_res = + &ctx_data->ope_acquire.in_res[rsc_idx]; + alignment = in_res->alignment; + unpack_format = in_res->unpacker_format; + pack_format = 0; + if (in_io_buf->pix_pattern > + PIXEL_PATTERN_CRYCBY) { + CAM_ERR(CAM_OPE, + "Invalid pix pattern = %u", + in_io_buf->pix_pattern); + return -EINVAL; + } + io_buf->pix_pattern = in_io_buf->pix_pattern; + } else if (in_io_buf->direction == CAM_BUF_OUTPUT) { + out_res = + &ctx_data->ope_acquire.out_res[rsc_idx]; + alignment = out_res->alignment; + pack_format = out_res->packer_format; + unpack_format = 0; + } + + for (k = 0; k < in_io_buf->num_planes; k++) { + io_buf->num_stripes[k] = + in_io_buf->num_stripes[k]; + is_secure = cam_mem_is_secure_buf( + in_io_buf->mem_handle[k]); + if (is_secure) + rc = cam_mem_get_io_buf( + in_io_buf->mem_handle[k], + hw_mgr->iommu_sec_hdl, + &iova_addr, &len); + else + rc = cam_mem_get_io_buf( + in_io_buf->mem_handle[k], + hw_mgr->iommu_hdl, + &iova_addr, &len); + + if (rc) { + CAM_ERR(CAM_OPE, "get buf failed: %d", + rc); + return -EINVAL; + } + if (len < in_io_buf->length[k]) { + CAM_ERR(CAM_OPE, "Invalid length"); + return -EINVAL; + } + iova_addr += in_io_buf->plane_offset[k]; + CAM_DBG(CAM_OPE, + "E rsc %d stripes %d dir %d plane %d", + in_io_buf->resource_type, + in_io_buf->direction, + in_io_buf->num_stripes[k], k); + for (l = 0; l < in_io_buf->num_stripes[k]; + l++) { + in_stripe_info = + &in_io_buf->stripe_info[k][l]; + stripe_info = &io_buf->s_io[k][l]; + stripe_info->offset = + in_stripe_info->offset; + stripe_info->format = in_io_buf->format; + stripe_info->s_location = + in_stripe_info->stripe_location; + stripe_info->iova_addr = + iova_addr + stripe_info->offset; + stripe_info->width = + in_stripe_info->width; + stripe_info->height = + in_stripe_info->height; + stripe_info->stride = + in_io_buf->plane_stride[k]; + stripe_info->x_init = + in_stripe_info->x_init; + stripe_info->len = len; + stripe_info->alignment = alignment; + stripe_info->pack_format = pack_format; + stripe_info->unpack_format = + unpack_format; + stripe_info->disable_bus = + in_stripe_info->disable_bus; + cam_ope_mgr_print_stripe_info(i, j, + k, l, stripe_info, iova_addr); + } + CAM_DBG(CAM_OPE, + "X rsc %d stripes %d dir %d plane %d", + in_io_buf->resource_type, + in_io_buf->direction, + in_io_buf->num_stripes[k], k); + } + } + } + + return rc; +} + +static int cam_ope_mgr_process_cmd_buf_req(struct cam_ope_hw_mgr *hw_mgr, + struct cam_packet *packet, struct cam_ope_ctx *ctx_data, + uintptr_t frame_process_addr, size_t length, uint32_t req_idx) +{ + int rc = 0; + int i, j; + dma_addr_t iova_addr; + dma_addr_t iova_cdm_addr; + uintptr_t cpu_addr; + size_t len; + struct ope_frame_process *frame_process; + struct ope_cmd_buf_info *cmd_buf; + struct cam_ope_request *ope_request; + bool is_kmd_buf_valid = false; + + frame_process = (struct ope_frame_process *)frame_process_addr; + + if (frame_process->batch_size > OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch: %d", + frame_process->batch_size); + return -EINVAL; + } + + for (i = 0; i < frame_process->batch_size; i++) { + if (frame_process->num_cmd_bufs[i] > OPE_MAX_CMD_BUFS) { + CAM_ERR(CAM_OPE, "Invalid cmd bufs for batch %d %d", + i, frame_process->num_cmd_bufs[i]); + return -EINVAL; + } + } + + CAM_DBG(CAM_OPE, "cmd buf for req id = %lld b_size = %d", + packet->header.request_id, frame_process->batch_size); + + for (i = 0; i < frame_process->batch_size; i++) { + CAM_DBG(CAM_OPE, "batch: %d count %d", i, + frame_process->num_cmd_bufs[i]); + for (j = 0; j < frame_process->num_cmd_bufs[i]; j++) { + CAM_DBG(CAM_OPE, "batch: %d cmd_buf_idx :%d mem_hdl:%x", + i, j, frame_process->cmd_buf[i][j].mem_handle); + CAM_DBG(CAM_OPE, "size = %u scope = %d buf_type = %d", + frame_process->cmd_buf[i][j].size, + frame_process->cmd_buf[i][j].cmd_buf_scope, + frame_process->cmd_buf[i][j].type); + CAM_DBG(CAM_OPE, "usage = %d buffered = %d s_idx = %d", + frame_process->cmd_buf[i][j].cmd_buf_usage, + frame_process->cmd_buf[i][j].cmd_buf_buffered, + frame_process->cmd_buf[i][j].stripe_idx); + } + } + + ope_request = ctx_data->req_list[req_idx]; + ope_request->num_batch = frame_process->batch_size; + + for (i = 0; i < frame_process->batch_size; i++) { + for (j = 0; j < frame_process->num_cmd_bufs[i]; j++) { + cmd_buf = &frame_process->cmd_buf[i][j]; + + switch (cmd_buf->cmd_buf_scope) { + case OPE_CMD_BUF_SCOPE_FRAME: { + rc = cam_mem_get_io_buf(cmd_buf->mem_handle, + hw_mgr->iommu_hdl, &iova_addr, &len); + if (rc) { + CAM_ERR(CAM_OPE, "get cmd buffailed %x", + hw_mgr->iommu_hdl); + goto end; + } + iova_addr = iova_addr + cmd_buf->offset; + + rc = cam_mem_get_io_buf(cmd_buf->mem_handle, + hw_mgr->iommu_cdm_hdl, + &iova_cdm_addr, &len); + if (rc) { + CAM_ERR(CAM_OPE, "get cmd buffailed %x", + hw_mgr->iommu_hdl); + goto end; + } + iova_cdm_addr = iova_cdm_addr + cmd_buf->offset; + + rc = cam_mem_get_cpu_buf(cmd_buf->mem_handle, + &cpu_addr, &len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buffailed %x", + hw_mgr->iommu_hdl); + goto end; + } + cpu_addr = cpu_addr + + frame_process->cmd_buf[i][j].offset; + CAM_DBG(CAM_OPE, "Hdl %x size %d len %d off %d", + cmd_buf->mem_handle, cmd_buf->size, + cmd_buf->length, + cmd_buf->offset); + if (cmd_buf->cmd_buf_usage == OPE_CMD_BUF_KMD) { + ope_request->ope_kmd_buf.mem_handle = + cmd_buf->mem_handle; + ope_request->ope_kmd_buf.cpu_addr = + cpu_addr; + ope_request->ope_kmd_buf.iova_addr = + iova_addr; + ope_request->ope_kmd_buf.iova_cdm_addr = + iova_cdm_addr; + ope_request->ope_kmd_buf.len = len; + ope_request->ope_kmd_buf.offset = + cmd_buf->offset; + ope_request->ope_kmd_buf.size = + cmd_buf->size; + is_kmd_buf_valid = true; + CAM_DBG(CAM_OPE, "kbuf:%x io:%x cdm:%x", + ope_request->ope_kmd_buf.cpu_addr, + ope_request->ope_kmd_buf.iova_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + cam_mem_put_cpu_buf( + cmd_buf->mem_handle); + break; + } else if (cmd_buf->cmd_buf_usage == + OPE_CMD_BUF_DEBUG) { + ope_request->ope_debug_buf.cpu_addr = + cpu_addr; + ope_request->ope_debug_buf.iova_addr = + iova_addr; + ope_request->ope_debug_buf.len = + cmd_buf->length; + ope_request->ope_debug_buf.size = + len; + ope_request->ope_debug_buf.offset = + cmd_buf->offset; + CAM_DBG(CAM_OPE, "dbg buf = %x", + ope_request->ope_debug_buf.cpu_addr); + cam_mem_put_cpu_buf( + cmd_buf->mem_handle); + break; + } + cam_mem_put_cpu_buf(cmd_buf->mem_handle); + break; + } + case OPE_CMD_BUF_SCOPE_STRIPE: { + uint32_t num_cmd_bufs = 0; + uint32_t s_idx = 0; + + s_idx = cmd_buf->stripe_idx; + num_cmd_bufs = + ope_request->num_stripe_cmd_bufs[i][s_idx]; + + if (!num_cmd_bufs) + ope_request->num_stripes[i]++; + + ope_request->num_stripe_cmd_bufs[i][s_idx]++; + break; + } + + default: + break; + } + } + } + + + for (i = 0; i < frame_process->batch_size; i++) { + CAM_DBG(CAM_OPE, "num of stripes for batch %d is %d", + i, ope_request->num_stripes[i]); + for (j = 0; j < ope_request->num_stripes[i]; j++) { + CAM_DBG(CAM_OPE, "cmd buffers for stripe: %d:%d is %d", + i, j, ope_request->num_stripe_cmd_bufs[i][j]); + } + } + + if (!is_kmd_buf_valid) { + CAM_DBG(CAM_OPE, "Invalid kmd buffer"); + rc = -EINVAL; + } +end: + return rc; +} + +static int cam_ope_mgr_process_cmd_desc(struct cam_ope_hw_mgr *hw_mgr, + struct cam_packet *packet, struct cam_ope_ctx *ctx_data, + uintptr_t *ope_cmd_buf_addr, uint32_t req_idx) +{ + int rc = 0; + int i; + int num_cmd_buf = 0; + size_t len; + struct cam_cmd_buf_desc *cmd_desc = NULL; + uintptr_t cpu_addr = 0; + struct cam_ope_request *ope_request; + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); + + *ope_cmd_buf_addr = 0; + for (i = 0; i < packet->num_cmd_buf; i++, num_cmd_buf++) { + if (cmd_desc[i].type != CAM_CMD_BUF_GENERIC || + cmd_desc[i].meta_data == OPE_CMD_META_GENERIC_BLOB) + continue; + + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, + &cpu_addr, &len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + num_cmd_buf = (num_cmd_buf > 0) ? + num_cmd_buf-- : 0; + goto end; + } + if ((len <= cmd_desc[i].offset) || + (cmd_desc[i].size < cmd_desc[i].length) || + ((len - cmd_desc[i].offset) < + cmd_desc[i].length)) { + CAM_ERR(CAM_OPE, "Invalid offset or length"); + goto end; + } + cpu_addr = cpu_addr + cmd_desc[i].offset; + *ope_cmd_buf_addr = cpu_addr; + } + + if (!cpu_addr) { + CAM_ERR(CAM_OPE, "invalid number of cmd buf"); + *ope_cmd_buf_addr = 0; + return -EINVAL; + } + + ope_request = ctx_data->req_list[req_idx]; + ope_request->request_id = packet->header.request_id; + ope_request->req_idx = req_idx; + + rc = cam_ope_mgr_process_cmd_buf_req(hw_mgr, packet, ctx_data, + cpu_addr, len, req_idx); + if (rc) { + CAM_ERR(CAM_OPE, "Process OPE cmd request is failed: %d", rc); + goto end; + } + + rc = cam_ope_mgr_process_cmd_io_buf_req(hw_mgr, packet, ctx_data, + cpu_addr, len, req_idx); + if (rc) { + CAM_ERR(CAM_OPE, "Process OPE cmd io request is failed: %d", + rc); + goto end; + } + + return rc; + +end: + *ope_cmd_buf_addr = 0; + return rc; +} + +static bool cam_ope_mgr_is_valid_inconfig(struct cam_packet *packet) +{ + int i, num_in_map_entries = 0; + bool in_config_valid = false; + struct cam_buf_io_cfg *io_cfg_ptr = NULL; + + io_cfg_ptr = (struct cam_buf_io_cfg *) ((uint32_t *) &packet->payload + + packet->io_configs_offset/4); + + for (i = 0 ; i < packet->num_io_configs; i++) + if (io_cfg_ptr[i].direction == CAM_BUF_INPUT) + num_in_map_entries++; + + if (num_in_map_entries <= OPE_IN_RES_MAX) { + in_config_valid = true; + } else { + CAM_ERR(CAM_OPE, "In config entries(%u) more than allowed(%u)", + num_in_map_entries, OPE_IN_RES_MAX); + } + + CAM_DBG(CAM_OPE, "number of in_config info: %u %u %u %u", + packet->num_io_configs, OPE_MAX_IO_BUFS, + num_in_map_entries, OPE_IN_RES_MAX); + + return in_config_valid; +} + +static bool cam_ope_mgr_is_valid_outconfig(struct cam_packet *packet) +{ + int i, num_out_map_entries = 0; + bool out_config_valid = false; + struct cam_buf_io_cfg *io_cfg_ptr = NULL; + + io_cfg_ptr = (struct cam_buf_io_cfg *) ((uint32_t *) &packet->payload + + packet->io_configs_offset/4); + + for (i = 0 ; i < packet->num_io_configs; i++) + if (io_cfg_ptr[i].direction == CAM_BUF_OUTPUT) + num_out_map_entries++; + + if (num_out_map_entries <= OPE_OUT_RES_MAX) { + out_config_valid = true; + } else { + CAM_ERR(CAM_OPE, "Out config entries(%u) more than allowed(%u)", + num_out_map_entries, OPE_OUT_RES_MAX); + } + + CAM_DBG(CAM_OPE, "number of out_config info: %u %u %u %u", + packet->num_io_configs, OPE_MAX_IO_BUFS, + num_out_map_entries, OPE_OUT_RES_MAX); + + return out_config_valid; +} + +static int cam_ope_mgr_pkt_validation(struct cam_packet *packet) +{ + if ((packet->header.op_code & 0xff) != + OPE_OPCODE_CONFIG) { + CAM_ERR(CAM_OPE, "Invalid Opcode in pkt: %d", + packet->header.op_code & 0xff); + return -EINVAL; + } + + if (packet->num_io_configs > OPE_MAX_IO_BUFS) { + CAM_ERR(CAM_OPE, "Invalid number of io configs: %d %d", + OPE_MAX_IO_BUFS, packet->num_io_configs); + return -EINVAL; + } + + if (packet->num_cmd_buf > OPE_PACKET_MAX_CMD_BUFS) { + CAM_ERR(CAM_OPE, "Invalid number of cmd buffers: %d %d", + OPE_PACKET_MAX_CMD_BUFS, packet->num_cmd_buf); + return -EINVAL; + } + + if (!cam_ope_mgr_is_valid_inconfig(packet) || + !cam_ope_mgr_is_valid_outconfig(packet)) { + return -EINVAL; + } + + CAM_DBG(CAM_OPE, "number of cmd/patch info: %u %u %u %u", + packet->num_cmd_buf, + packet->num_io_configs, OPE_MAX_IO_BUFS, + packet->num_patches); + return 0; +} + +static int cam_ope_get_acquire_info(struct cam_ope_hw_mgr *hw_mgr, + struct cam_hw_acquire_args *args, + struct cam_ope_ctx *ctx) +{ + int i = 0; + + if (args->num_acq > 1) { + CAM_ERR(CAM_OPE, "Invalid number of resources: %d", + args->num_acq); + return -EINVAL; + } + + if (copy_from_user(&ctx->ope_acquire, + (void __user *)args->acquire_info, + sizeof(struct ope_acquire_dev_info))) { + CAM_ERR(CAM_OPE, "Failed in acquire"); + return -EFAULT; + } + + if (ctx->ope_acquire.secure_mode > CAM_SECURE_MODE_SECURE) { + CAM_ERR(CAM_OPE, "Invalid mode:%d", + ctx->ope_acquire.secure_mode); + return -EINVAL; + } + + if (ctx->ope_acquire.num_out_res > OPE_OUT_RES_MAX) { + CAM_ERR(CAM_OPE, "num of out resources exceeding : %u", + ctx->ope_acquire.num_out_res); + return -EINVAL; + } + + if (ctx->ope_acquire.num_in_res > OPE_IN_RES_MAX) { + CAM_ERR(CAM_OPE, "num of in resources exceeding : %u", + ctx->ope_acquire.num_in_res); + return -EINVAL; + } + + if (ctx->ope_acquire.dev_type >= OPE_DEV_TYPE_MAX) { + CAM_ERR(CAM_OPE, "Invalid device type: %d", + ctx->ope_acquire.dev_type); + return -EFAULT; + } + + if (ctx->ope_acquire.hw_type >= OPE_HW_TYPE_MAX) { + CAM_ERR(CAM_OPE, "Invalid HW type: %d", + ctx->ope_acquire.hw_type); + return -EFAULT; + } + + CAM_DBG(CAM_OPE, "top: %u %u %s %u %u %u %u %u", + ctx->ope_acquire.hw_type, ctx->ope_acquire.dev_type, + ctx->ope_acquire.dev_name, + ctx->ope_acquire.nrt_stripes_for_arb, + ctx->ope_acquire.secure_mode, ctx->ope_acquire.batch_size, + ctx->ope_acquire.num_in_res, ctx->ope_acquire.num_out_res); + + for (i = 0; i < ctx->ope_acquire.num_in_res; i++) { + CAM_DBG(CAM_OPE, "IN: %u %u %u %u %u %u %u %u", + ctx->ope_acquire.in_res[i].res_id, + ctx->ope_acquire.in_res[i].format, + ctx->ope_acquire.in_res[i].width, + ctx->ope_acquire.in_res[i].height, + ctx->ope_acquire.in_res[i].alignment, + ctx->ope_acquire.in_res[i].unpacker_format, + ctx->ope_acquire.in_res[i].max_stripe_size, + ctx->ope_acquire.in_res[i].fps); + } + + for (i = 0; i < ctx->ope_acquire.num_out_res; i++) { + CAM_DBG(CAM_OPE, "OUT: %u %u %u %u %u %u %u %u", + ctx->ope_acquire.out_res[i].res_id, + ctx->ope_acquire.out_res[i].format, + ctx->ope_acquire.out_res[i].width, + ctx->ope_acquire.out_res[i].height, + ctx->ope_acquire.out_res[i].alignment, + ctx->ope_acquire.out_res[i].packer_format, + ctx->ope_acquire.out_res[i].subsample_period, + ctx->ope_acquire.out_res[i].subsample_pattern); + } + + return 0; +} + +static int cam_ope_get_free_ctx(struct cam_ope_hw_mgr *hw_mgr) +{ + int i; + + i = find_first_zero_bit(hw_mgr->ctx_bitmap, hw_mgr->ctx_bits); + if (i >= OPE_CTX_MAX || i < 0) { + CAM_ERR(CAM_OPE, "Invalid ctx id = %d", i); + return -EINVAL; + } + + mutex_lock(&hw_mgr->ctx[i].ctx_mutex); + if (hw_mgr->ctx[i].ctx_state != OPE_CTX_STATE_FREE) { + CAM_ERR(CAM_OPE, "Invalid ctx %d state %d", + i, hw_mgr->ctx[i].ctx_state); + mutex_unlock(&hw_mgr->ctx[i].ctx_mutex); + return -EINVAL; + } + set_bit(i, hw_mgr->ctx_bitmap); + mutex_unlock(&hw_mgr->ctx[i].ctx_mutex); + + return i; +} + + +static int cam_ope_put_free_ctx(struct cam_ope_hw_mgr *hw_mgr, uint32_t ctx_id) +{ + if (ctx_id >= OPE_CTX_MAX) { + CAM_ERR(CAM_OPE, "Invalid ctx_id: %d", ctx_id); + return 0; + } + + hw_mgr->ctx[ctx_id].ctx_state = OPE_CTX_STATE_FREE; + clear_bit(ctx_id, hw_mgr->ctx_bitmap); + + return 0; +} + +static int cam_ope_mgr_get_hw_caps(void *hw_priv, void *hw_caps_args) +{ + struct cam_ope_hw_mgr *hw_mgr; + struct cam_query_cap_cmd *query_cap = hw_caps_args; + struct ope_hw_ver hw_ver; + int rc = 0, i; + + if (!hw_priv || !hw_caps_args) { + CAM_ERR(CAM_OPE, "Invalid args: %x %x", hw_priv, hw_caps_args); + return -EINVAL; + } + + hw_mgr = hw_priv; + mutex_lock(&hw_mgr->hw_mgr_mutex); + if (copy_from_user(&hw_mgr->ope_caps, + u64_to_user_ptr(query_cap->caps_handle), + sizeof(struct ope_query_cap_cmd))) { + CAM_ERR(CAM_OPE, "copy_from_user failed: size = %d", + sizeof(struct ope_query_cap_cmd)); + rc = -EFAULT; + goto end; + } + + for (i = 0; i < hw_mgr->num_ope; i++) { + rc = hw_mgr->ope_dev_intf[i]->hw_ops.get_hw_caps( + hw_mgr->ope_dev_intf[i]->hw_priv, + &hw_ver, sizeof(hw_ver)); + if (rc) + goto end; + + hw_mgr->ope_caps.hw_ver[i] = hw_ver; + } + + hw_mgr->ope_caps.dev_iommu_handle.non_secure = hw_mgr->iommu_hdl; + hw_mgr->ope_caps.dev_iommu_handle.secure = hw_mgr->iommu_sec_hdl; + hw_mgr->ope_caps.cdm_iommu_handle.non_secure = hw_mgr->iommu_cdm_hdl; + hw_mgr->ope_caps.cdm_iommu_handle.secure = hw_mgr->iommu_sec_cdm_hdl; + hw_mgr->ope_caps.num_ope = hw_mgr->num_ope; + + CAM_DBG(CAM_OPE, "iommu sec %d iommu ns %d cdm s %d cdm ns %d", + hw_mgr->ope_caps.dev_iommu_handle.secure, + hw_mgr->ope_caps.dev_iommu_handle.non_secure, + hw_mgr->ope_caps.cdm_iommu_handle.secure, + hw_mgr->ope_caps.cdm_iommu_handle.non_secure); + + if (copy_to_user(u64_to_user_ptr(query_cap->caps_handle), + &hw_mgr->ope_caps, sizeof(struct ope_query_cap_cmd))) { + CAM_ERR(CAM_OPE, "copy_to_user failed: size = %d", + sizeof(struct ope_query_cap_cmd)); + rc = -EFAULT; + } + +end: + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) +{ + int rc = 0, i; + int ctx_id; + struct cam_ope_hw_mgr *hw_mgr = hw_priv; + struct cam_ope_ctx *ctx; + struct cam_hw_acquire_args *args = hw_acquire_args; + struct cam_ope_dev_acquire ope_dev_acquire; + struct cam_ope_dev_release ope_dev_release; + struct cam_cdm_acquire_data *cdm_acquire; + struct cam_ope_dev_init init; + struct cam_ope_dev_clk_update clk_update; + struct cam_ope_dev_bw_update *bw_update; + struct cam_ope_set_irq_cb irq_cb; + struct cam_hw_info *dev = NULL; + struct cam_hw_soc_info *soc_info = NULL; + int32_t idx; + + if ((!hw_priv) || (!hw_acquire_args)) { + CAM_ERR(CAM_OPE, "Invalid args: %x %x", + hw_priv, hw_acquire_args); + return -EINVAL; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + ctx_id = cam_ope_get_free_ctx(hw_mgr); + if (ctx_id < 0) { + CAM_ERR(CAM_OPE, "No free ctx"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return ctx_id; + } + + ctx = &hw_mgr->ctx[ctx_id]; + ctx->ctx_id = ctx_id; + mutex_lock(&ctx->ctx_mutex); + rc = cam_ope_get_acquire_info(hw_mgr, args, ctx); + if (rc < 0) { + CAM_ERR(CAM_OPE, "get_acquire info failed: %d", rc); + goto end; + } + + cdm_acquire = kzalloc(sizeof(struct cam_cdm_acquire_data), GFP_KERNEL); + if (!cdm_acquire) { + CAM_ERR(CAM_ISP, "Out of memory"); + goto end; + } + strlcpy(cdm_acquire->identifier, "ope", sizeof("ope")); + if (ctx->ope_acquire.dev_type == OPE_DEV_TYPE_OPE_RT) { + cdm_acquire->priority = CAM_CDM_BL_FIFO_3; + ctx->req_timer_timeout = OPE_REQUEST_RT_TIMEOUT; + } + else if (ctx->ope_acquire.dev_type == + OPE_DEV_TYPE_OPE_NRT) { + cdm_acquire->priority = CAM_CDM_BL_FIFO_0; + ctx->req_timer_timeout = OPE_REQUEST_NRT_TIMEOUT; + } + else + goto free_cdm_acquire; + + cdm_acquire->cell_index = 0; + cdm_acquire->handle = 0; + cdm_acquire->userdata = ctx; + cdm_acquire->cam_cdm_callback = cam_ope_ctx_cdm_callback; + cdm_acquire->id = CAM_CDM_VIRTUAL; + cdm_acquire->base_array_cnt = 1; + cdm_acquire->base_array[0] = hw_mgr->cdm_reg_map[OPE_DEV_OPE][0]; + + rc = cam_cdm_acquire(cdm_acquire); + if (rc) { + CAM_ERR(CAM_OPE, "cdm_acquire is failed: %d", rc); + goto cdm_acquire_failed; + } + + ctx->ope_cdm.cdm_ops = cdm_acquire->ops; + ctx->ope_cdm.cdm_handle = cdm_acquire->handle; + + rc = cam_cdm_stream_on(cdm_acquire->handle); + if (rc) { + CAM_ERR(CAM_OPE, "cdm stream on failure: %d", rc); + goto cdm_stream_on_failure; + } + + if (!hw_mgr->ope_ctx_cnt) { + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + init.hfi_en = ope_hw_mgr->hfi_en; + rc = hw_mgr->ope_dev_intf[i]->hw_ops.init( + hw_mgr->ope_dev_intf[i]->hw_priv, &init, + sizeof(init)); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Dev init failed: %d", rc); + goto ope_dev_init_failure; + } + } + + /* Install IRQ CB */ + irq_cb.ope_hw_mgr_cb = cam_ope_hw_mgr_cb; + irq_cb.data = hw_mgr; + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + init.hfi_en = ope_hw_mgr->hfi_en; + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_SET_IRQ_CB, + &irq_cb, sizeof(irq_cb)); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Dev init failed: %d", rc); + goto ope_irq_set_failed; + } + } + + dev = (struct cam_hw_info *)hw_mgr->ope_dev_intf[0]->hw_priv; + soc_info = &dev->soc_info; + idx = soc_info->src_clk_idx; + + hw_mgr->clk_info.base_clk = + soc_info->clk_rate[CAM_TURBO_VOTE][idx]; + hw_mgr->clk_info.threshold = 5; + hw_mgr->clk_info.over_clked = 0; + + for (i = 0; i < CAM_OPE_MAX_PER_PATH_VOTES; i++) { + hw_mgr->clk_info.axi_path[i].camnoc_bw = 0; + hw_mgr->clk_info.axi_path[i].mnoc_ab_bw = 0; + hw_mgr->clk_info.axi_path[i].mnoc_ib_bw = 0; + hw_mgr->clk_info.axi_path[i].ddr_ab_bw = 0; + hw_mgr->clk_info.axi_path[i].ddr_ib_bw = 0; + } + } + + ope_dev_acquire.ctx_id = ctx_id; + ope_dev_acquire.ope_acquire = &ctx->ope_acquire; + + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_ACQUIRE, + &ope_dev_acquire, sizeof(ope_dev_acquire)); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Dev acquire failed: %d", rc); + goto ope_dev_acquire_failed; + } + } + + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + dev = (struct cam_hw_info *)hw_mgr->ope_dev_intf[i]->hw_priv; + soc_info = &dev->soc_info; + idx = soc_info->src_clk_idx; + clk_update.clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][idx]; + hw_mgr->clk_info.curr_clk = + soc_info->clk_rate[CAM_TURBO_VOTE][idx]; + + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_CLK_UPDATE, + &clk_update, sizeof(clk_update)); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Dev clk update failed: %d", rc); + goto ope_clk_update_failed; + } + } + + bw_update = kzalloc(sizeof(struct cam_ope_dev_bw_update), GFP_KERNEL); + if (!bw_update) { + CAM_ERR(CAM_ISP, "Out of memory"); + goto ope_clk_update_failed; + } + bw_update->ahb_vote_valid = false; + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + bw_update->axi_vote.num_paths = 1; + bw_update->axi_vote_valid = true; + bw_update->axi_vote.axi_path[0].camnoc_bw = 600000000; + bw_update->axi_vote.axi_path[0].mnoc_ab_bw = 600000000; + bw_update->axi_vote.axi_path[0].mnoc_ib_bw = 600000000; + bw_update->axi_vote.axi_path[0].ddr_ab_bw = 600000000; + bw_update->axi_vote.axi_path[0].ddr_ib_bw = 600000000; + bw_update->axi_vote.axi_path[0].transac_type = + CAM_AXI_TRANSACTION_WRITE; + bw_update->axi_vote.axi_path[0].path_data_type = + CAM_AXI_PATH_DATA_ALL; + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_BW_UPDATE, + bw_update, sizeof(*bw_update)); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Dev clk update failed: %d", rc); + goto free_bw_update; + } + } + + cam_ope_start_req_timer(ctx); + cam_ope_device_timer_start(hw_mgr); + hw_mgr->ope_ctx_cnt++; + ctx->context_priv = args->context_data; + args->ctxt_to_hw_map = ctx; + ctx->ctxt_event_cb = args->event_cb; + cam_ope_ctx_clk_info_init(ctx); + ctx->ctx_state = OPE_CTX_STATE_ACQUIRED; + kzfree(cdm_acquire); + cdm_acquire = NULL; + kzfree(bw_update); + bw_update = NULL; + + mutex_unlock(&ctx->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + CAM_INFO(CAM_OPE, "OPE: %d acquire succesfull rc %d", ctx_id, rc); + return rc; + +free_bw_update: + kzfree(bw_update); + bw_update = NULL; +ope_clk_update_failed: + ope_dev_release.ctx_id = ctx_id; + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + if (hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RELEASE, + &ope_dev_release, sizeof(ope_dev_release))) + CAM_ERR(CAM_OPE, "OPE Dev release failed"); + } +ope_dev_acquire_failed: + if (!hw_mgr->ope_ctx_cnt) { + irq_cb.ope_hw_mgr_cb = NULL; + irq_cb.data = hw_mgr; + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + init.hfi_en = ope_hw_mgr->hfi_en; + if (hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_SET_IRQ_CB, + &irq_cb, sizeof(irq_cb))) + CAM_ERR(CAM_OPE, + "OPE IRQ de register failed"); + } + } +ope_irq_set_failed: + if (!hw_mgr->ope_ctx_cnt) { + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + if (hw_mgr->ope_dev_intf[i]->hw_ops.deinit( + hw_mgr->ope_dev_intf[i]->hw_priv, NULL, 0)) + CAM_ERR(CAM_OPE, "OPE deinit fail"); + if (hw_mgr->ope_dev_intf[i]->hw_ops.stop( + hw_mgr->ope_dev_intf[i]->hw_priv, + NULL, 0)) + CAM_ERR(CAM_OPE, "OPE stop fail"); + } + } +ope_dev_init_failure: +cdm_stream_on_failure: + cam_cdm_release(cdm_acquire->handle); + ctx->ope_cdm.cdm_ops = NULL; + ctx->ope_cdm.cdm_handle = 0; + +cdm_acquire_failed: +free_cdm_acquire: + kzfree(cdm_acquire); + cdm_acquire = NULL; +end: + args->ctxt_to_hw_map = NULL; + cam_ope_put_free_ctx(hw_mgr, ctx_id); + mutex_unlock(&ctx->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static int cam_ope_mgr_remove_bw(struct cam_ope_hw_mgr *hw_mgr, int ctx_id) +{ + int i, path_index, rc = 0; + struct cam_ope_ctx *ctx_data = NULL; + struct cam_ope_clk_info *hw_mgr_clk_info; + + ctx_data = &hw_mgr->ctx[ctx_id]; + hw_mgr_clk_info = &hw_mgr->clk_info; + + for (i = 0; i < ctx_data->clk_info.num_paths; i++) { + path_index = + ctx_data->clk_info.axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_OPE_START_OFFSET; + + if (path_index >= CAM_OPE_MAX_PER_PATH_VOTES) { + CAM_WARN(CAM_OPE, + "Invalid path %d, start offset=%d, max=%d", + ctx_data->clk_info.axi_path[i].path_data_type, + CAM_AXI_PATH_DATA_OPE_START_OFFSET, + CAM_OPE_MAX_PER_PATH_VOTES); + continue; + } + + hw_mgr_clk_info->axi_path[path_index].camnoc_bw -= + ctx_data->clk_info.axi_path[i].camnoc_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ab_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ab_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ib_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw -= + ctx_data->clk_info.axi_path[i].ddr_ab_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw -= + ctx_data->clk_info.axi_path[i].ddr_ib_bw; + } + + rc = cam_ope_update_cpas_vote(hw_mgr, ctx_data); + + return rc; +} + +static int cam_ope_mgr_ope_clk_remove(struct cam_ope_hw_mgr *hw_mgr, int ctx_id) +{ + struct cam_ope_ctx *ctx_data = NULL; + struct cam_ope_clk_info *hw_mgr_clk_info; + + ctx_data = &hw_mgr->ctx[ctx_id]; + hw_mgr_clk_info = &hw_mgr->clk_info; + + if (hw_mgr_clk_info->base_clk >= ctx_data->clk_info.base_clk) + hw_mgr_clk_info->base_clk -= ctx_data->clk_info.base_clk; + + /* reset clock info */ + ctx_data->clk_info.curr_fc = 0; + ctx_data->clk_info.base_clk = 0; + + return 0; +} + +static int cam_ope_mgr_release_ctx(struct cam_ope_hw_mgr *hw_mgr, int ctx_id) +{ + int i = 0, rc = 0; + struct cam_ope_dev_release ope_dev_release; + + if (ctx_id >= OPE_CTX_MAX) { + CAM_ERR(CAM_OPE, "ctx_id is wrong: %d", ctx_id); + return -EINVAL; + } + + mutex_lock(&hw_mgr->ctx[ctx_id].ctx_mutex); + if (hw_mgr->ctx[ctx_id].ctx_state != + OPE_CTX_STATE_ACQUIRED) { + mutex_unlock(&hw_mgr->ctx[ctx_id].ctx_mutex); + CAM_DBG(CAM_OPE, "ctx id: %d not in right state: %d", + ctx_id, hw_mgr->ctx[ctx_id].ctx_state); + return 0; + } + + hw_mgr->ctx[ctx_id].ctx_state = OPE_CTX_STATE_RELEASE; + + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + ope_dev_release.ctx_id = ctx_id; + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RELEASE, + &ope_dev_release, sizeof(ope_dev_release)); + if (rc) + CAM_ERR(CAM_OPE, "OPE Dev release failed: %d", rc); + } + + rc = cam_cdm_stream_off(hw_mgr->ctx[ctx_id].ope_cdm.cdm_handle); + if (rc) + CAM_ERR(CAM_OPE, "OPE CDM streamoff failed: %d", rc); + + rc = cam_cdm_release(hw_mgr->ctx[ctx_id].ope_cdm.cdm_handle); + if (rc) + CAM_ERR(CAM_OPE, "OPE CDM relase failed: %d", rc); + + + for (i = 0; i < CAM_CTX_REQ_MAX; i++) { + if (!hw_mgr->ctx[ctx_id].req_list[i]) + continue; + + if (hw_mgr->ctx[ctx_id].req_list[i]->cdm_cmd) { + kzfree(hw_mgr->ctx[ctx_id].req_list[i]->cdm_cmd); + hw_mgr->ctx[ctx_id].req_list[i]->cdm_cmd = NULL; + } + cam_ope_free_io_config(hw_mgr->ctx[ctx_id].req_list[i]); + kzfree(hw_mgr->ctx[ctx_id].req_list[i]); + hw_mgr->ctx[ctx_id].req_list[i] = NULL; + clear_bit(i, hw_mgr->ctx[ctx_id].bitmap); + } + + cam_ope_req_timer_stop(&hw_mgr->ctx[ctx_id]); + hw_mgr->ctx[ctx_id].ope_cdm.cdm_handle = 0; + hw_mgr->ctx[ctx_id].req_cnt = 0; + hw_mgr->ctx[ctx_id].last_flush_req = 0; + cam_ope_put_free_ctx(hw_mgr, ctx_id); + + rc = cam_ope_mgr_ope_clk_remove(hw_mgr, ctx_id); + if (rc) + CAM_ERR(CAM_OPE, "OPE clk update failed: %d", rc); + + hw_mgr->ope_ctx_cnt--; + mutex_unlock(&hw_mgr->ctx[ctx_id].ctx_mutex); + CAM_DBG(CAM_OPE, "X: ctx_id = %d", ctx_id); + + return 0; +} + +static int cam_ope_mgr_release_hw(void *hw_priv, void *hw_release_args) +{ + int i, rc = 0; + int ctx_id = 0; + struct cam_hw_release_args *release_hw = hw_release_args; + struct cam_ope_hw_mgr *hw_mgr = hw_priv; + struct cam_ope_ctx *ctx_data = NULL; + struct cam_ope_set_irq_cb irq_cb; + struct cam_hw_intf *dev_intf; + + if (!release_hw || !hw_mgr) { + CAM_ERR(CAM_OPE, "Invalid args: %pK %pK", release_hw, hw_mgr); + return -EINVAL; + } + + ctx_data = release_hw->ctxt_to_hw_map; + if (!ctx_data) { + CAM_ERR(CAM_OPE, "NULL ctx data"); + return -EINVAL; + } + + ctx_id = ctx_data->ctx_id; + if (ctx_id < 0 || ctx_id >= OPE_CTX_MAX) { + CAM_ERR(CAM_OPE, "Invalid ctx id: %d", ctx_id); + return -EINVAL; + } + + mutex_lock(&hw_mgr->ctx[ctx_id].ctx_mutex); + if (hw_mgr->ctx[ctx_id].ctx_state != OPE_CTX_STATE_ACQUIRED) { + CAM_DBG(CAM_OPE, "ctx is not in use: %d", ctx_id); + mutex_unlock(&hw_mgr->ctx[ctx_id].ctx_mutex); + return -EINVAL; + } + mutex_unlock(&hw_mgr->ctx[ctx_id].ctx_mutex); + + mutex_lock(&hw_mgr->hw_mgr_mutex); + rc = cam_ope_mgr_release_ctx(hw_mgr, ctx_id); + if (!hw_mgr->ope_ctx_cnt) { + CAM_DBG(CAM_OPE, "Last Release"); + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + dev_intf = hw_mgr->ope_dev_intf[i]; + irq_cb.ope_hw_mgr_cb = NULL; + irq_cb.data = NULL; + rc = dev_intf->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_SET_IRQ_CB, + &irq_cb, sizeof(irq_cb)); + if (rc) + CAM_ERR(CAM_OPE, "IRQ dereg failed: %d", rc); + } + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + dev_intf = hw_mgr->ope_dev_intf[i]; + rc = dev_intf->hw_ops.deinit( + hw_mgr->ope_dev_intf[i]->hw_priv, + NULL, 0); + if (rc) + CAM_ERR(CAM_OPE, "deinit failed: %d", rc); + } + cam_ope_device_timer_stop(hw_mgr); + } + + rc = cam_ope_mgr_remove_bw(hw_mgr, ctx_id); + if (rc) + CAM_ERR(CAM_OPE, "OPE remove bw failed: %d", rc); + + if (!hw_mgr->ope_ctx_cnt) { + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + dev_intf = hw_mgr->ope_dev_intf[i]; + rc = dev_intf->hw_ops.stop( + hw_mgr->ope_dev_intf[i]->hw_priv, + NULL, 0); + if (rc) + CAM_ERR(CAM_OPE, "stop failed: %d", rc); + } + } + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + CAM_DBG(CAM_OPE, "Release done for ctx_id %d", ctx_id); + return rc; +} + + +static int cam_ope_packet_generic_blob_handler(void *user_data, + uint32_t blob_type, uint32_t blob_size, uint8_t *blob_data) +{ + struct cam_ope_clk_bw_request *clk_info; + struct ope_clk_bw_request_v2 *soc_req_v2; + struct cam_ope_clk_bw_req_internal_v2 *clk_info_v2; + struct ope_cmd_generic_blob *blob; + struct cam_ope_ctx *ctx_data; + uint32_t index; + size_t clk_update_size; + int rc = 0; + + if (!blob_data || (blob_size == 0)) { + CAM_ERR(CAM_OPE, "Invalid blob info %pK %d", blob_data, + blob_size); + return -EINVAL; + } + + blob = (struct ope_cmd_generic_blob *)user_data; + ctx_data = blob->ctx; + index = blob->req_idx; + + switch (blob_type) { + case OPE_CMD_GENERIC_BLOB_CLK_V2: + if (blob_size < sizeof(struct ope_clk_bw_request_v2)) { + CAM_ERR(CAM_OPE, "Mismatch blob size %d expected %lu", + blob_size, + sizeof(struct ope_clk_bw_request_v2)); + return -EINVAL; + } + + soc_req_v2 = (struct ope_clk_bw_request_v2 *)blob_data; + if (soc_req_v2->num_paths > CAM_OPE_MAX_PER_PATH_VOTES) { + CAM_ERR(CAM_OPE, "Invalid num paths: %d", + soc_req_v2->num_paths); + return -EINVAL; + } + + /* Check for integer overflow */ + if (soc_req_v2->num_paths != 1) { + if (sizeof(struct cam_axi_per_path_bw_vote) > + ((UINT_MAX - + sizeof(struct ope_clk_bw_request_v2)) / + (soc_req_v2->num_paths - 1))) { + CAM_ERR(CAM_OPE, + "Size exceeds limit paths:%u size per path:%lu", + soc_req_v2->num_paths - 1, + sizeof( + struct cam_axi_per_path_bw_vote)); + return -EINVAL; + } + } + + clk_update_size = sizeof(struct ope_clk_bw_request_v2) + + ((soc_req_v2->num_paths - 1) * + sizeof(struct cam_axi_per_path_bw_vote)); + if (blob_size < clk_update_size) { + CAM_ERR(CAM_OPE, "Invalid blob size: %u", + blob_size); + return -EINVAL; + } + + clk_info = &ctx_data->req_list[index]->clk_info; + clk_info_v2 = &ctx_data->req_list[index]->clk_info_v2; + + memcpy(clk_info_v2, soc_req_v2, clk_update_size); + + /* Use v1 structure for clk fields */ + clk_info->budget_ns = clk_info_v2->budget_ns; + clk_info->frame_cycles = clk_info_v2->frame_cycles; + clk_info->rt_flag = clk_info_v2->rt_flag; + + CAM_DBG(CAM_OPE, "budget=%llu, frame_cycle=%llu, rt_flag=%d", + clk_info_v2->budget_ns, clk_info_v2->frame_cycles, + clk_info_v2->rt_flag); + break; + + default: + CAM_WARN(CAM_OPE, "Invalid blob type %d", blob_type); + break; + } + return rc; +} + +static int cam_ope_process_generic_cmd_buffer( + struct cam_packet *packet, + struct cam_ope_ctx *ctx_data, + int32_t index, + uint64_t *io_buf_addr) +{ + int i, rc = 0; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct ope_cmd_generic_blob cmd_generic_blob; + + cmd_generic_blob.ctx = ctx_data; + cmd_generic_blob.req_idx = index; + cmd_generic_blob.io_buf_addr = io_buf_addr; + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); + + for (i = 0; i < packet->num_cmd_buf; i++) { + if (!cmd_desc[i].length) + continue; + + if (cmd_desc[i].meta_data != OPE_CMD_META_GENERIC_BLOB) + continue; + + rc = cam_packet_util_process_generic_cmd_buffer(&cmd_desc[i], + cam_ope_packet_generic_blob_handler, &cmd_generic_blob); + if (rc) + CAM_ERR(CAM_OPE, "Failed in processing blobs %d", rc); + } + + return rc; +} + +static int cam_ope_mgr_prepare_hw_update(void *hw_priv, + void *hw_prepare_update_args) +{ + int rc = 0; + struct cam_packet *packet = NULL; + struct cam_ope_hw_mgr *hw_mgr = hw_priv; + struct cam_hw_prepare_update_args *prepare_args = + hw_prepare_update_args; + struct cam_ope_ctx *ctx_data = NULL; + uintptr_t ope_cmd_buf_addr; + uint32_t request_idx = 0; + struct cam_ope_request *ope_req; + struct timespec64 ts; + + if ((!prepare_args) || (!hw_mgr) || (!prepare_args->packet)) { + CAM_ERR(CAM_OPE, "Invalid args: %x %x", + prepare_args, hw_mgr); + return -EINVAL; + } + + ctx_data = prepare_args->ctxt_to_hw_map; + if (!ctx_data) { + CAM_ERR(CAM_OPE, "Invalid Context"); + return -EINVAL; + } + + mutex_lock(&ctx_data->ctx_mutex); + if (ctx_data->ctx_state != OPE_CTX_STATE_ACQUIRED) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, "ctx id %u is not acquired state: %d", + ctx_data->ctx_id, ctx_data->ctx_state); + return -EINVAL; + } + + packet = prepare_args->packet; + rc = cam_packet_util_validate_packet(packet, prepare_args->remain_len); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, + "packet validation failed: %d req_id: %d ctx: %d", + rc, packet->header.request_id, ctx_data->ctx_id); + return rc; + } + + rc = cam_ope_mgr_pkt_validation(packet); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, + "ope packet validation failed: %d req_id: %d ctx: %d", + rc, packet->header.request_id, ctx_data->ctx_id); + return -EINVAL; + } + + rc = cam_packet_util_process_patches(packet, hw_mgr->iommu_cdm_hdl, + hw_mgr->iommu_sec_cdm_hdl); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, "Patching failed: %d req_id: %d ctx: %d", + rc, packet->header.request_id, ctx_data->ctx_id); + return -EINVAL; + } + + request_idx = find_first_zero_bit(ctx_data->bitmap, ctx_data->bits); + if (request_idx >= CAM_CTX_REQ_MAX || request_idx < 0) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, "Invalid ctx req slot = %d", request_idx); + return -EINVAL; + } + ctx_data->req_list[request_idx] = + kzalloc(sizeof(struct cam_ope_request), GFP_KERNEL); + if (!ctx_data->req_list[request_idx]) { + CAM_ERR(CAM_OPE, "mem allocation failed ctx:%d req_idx:%d", + ctx_data->ctx_id, request_idx); + rc = -ENOMEM; + goto req_mem_alloc_failed; + } + + ope_req = ctx_data->req_list[request_idx]; + ope_req->cdm_cmd = + kzalloc(((sizeof(struct cam_cdm_bl_request)) + + ((OPE_MAX_CDM_BLS - 1) * + sizeof(struct cam_cdm_bl_cmd))), + GFP_KERNEL); + if (!ope_req->cdm_cmd) { + CAM_ERR(CAM_OPE, "Cdm mem alloc failed ctx:%d req_idx:%d", + ctx_data->ctx_id, request_idx); + rc = -ENOMEM; + goto req_cdm_mem_alloc_failed; + } + + rc = cam_ope_mgr_process_cmd_desc(hw_mgr, packet, + ctx_data, &ope_cmd_buf_addr, request_idx); + if (rc) { + CAM_ERR(CAM_OPE, + "cmd desc processing failed :%d ctx: %d req_id:%d", + rc, ctx_data->ctx_id, packet->header.request_id); + goto end; + } + + rc = cam_ope_mgr_process_io_cfg(hw_mgr, packet, prepare_args, + ctx_data, request_idx); + if (rc) { + CAM_ERR(CAM_OPE, + "IO cfg processing failed: %d ctx: %d req_id:%d", + rc, ctx_data->ctx_id, packet->header.request_id); + goto end; + } + + rc = cam_ope_mgr_create_kmd_buf(hw_mgr, packet, prepare_args, + ctx_data, request_idx, ope_cmd_buf_addr); + if (rc) { + CAM_ERR(CAM_OPE, + "create kmd buf failed: %d ctx: %d request_id:%d", + rc, ctx_data->ctx_id, packet->header.request_id); + goto end; + } + + rc = cam_ope_process_generic_cmd_buffer(packet, ctx_data, + request_idx, NULL); + if (rc) { + CAM_ERR(CAM_OPE, "Failed: %d ctx: %d req_id: %d req_idx: %d", + rc, ctx_data->ctx_id, packet->header.request_id, + request_idx); + goto end; + } + prepare_args->num_hw_update_entries = 1; + prepare_args->hw_update_entries[0].addr = + (uintptr_t)ctx_data->req_list[request_idx]->cdm_cmd; + prepare_args->priv = ctx_data->req_list[request_idx]; + prepare_args->pf_data->packet = packet; + ope_req->hang_data.packet = packet; + get_monotonic_boottime64(&ts); + ctx_data->last_req_time = (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); + CAM_DBG(CAM_REQ, "req_id= %llu ctx_id= %d lrt=%llu", + packet->header.request_id, ctx_data->ctx_id, + ctx_data->last_req_time); + cam_ope_req_timer_modify(ctx_data, ctx_data->req_timer_timeout); + set_bit(request_idx, ctx_data->bitmap); + cam_ope_mgr_put_cmd_buf(packet); + mutex_unlock(&ctx_data->ctx_mutex); + CAM_DBG(CAM_REQ, "Prepare Hw update Successful request_id: %d ctx: %d", + packet->header.request_id, ctx_data->ctx_id); + return rc; + +end: + kzfree(ctx_data->req_list[request_idx]->cdm_cmd); + cam_ope_mgr_put_cmd_buf(packet); + ctx_data->req_list[request_idx]->cdm_cmd = NULL; +req_cdm_mem_alloc_failed: + kzfree(ctx_data->req_list[request_idx]); + ctx_data->req_list[request_idx] = NULL; +req_mem_alloc_failed: + clear_bit(request_idx, ctx_data->bitmap); + mutex_unlock(&ctx_data->ctx_mutex); + return rc; +} + +static int cam_ope_mgr_handle_config_err( + struct cam_hw_config_args *config_args, + struct cam_ope_ctx *ctx_data) +{ + struct cam_hw_done_event_data buf_data; + struct cam_ope_request *ope_req; + uint32_t req_idx; + + ope_req = config_args->priv; + + buf_data.request_id = ope_req->request_id; + ctx_data->ctxt_event_cb(ctx_data->context_priv, false, &buf_data); + + req_idx = ope_req->req_idx; + ope_req->request_id = 0; + kzfree(ctx_data->req_list[req_idx]->cdm_cmd); + ctx_data->req_list[req_idx]->cdm_cmd = NULL; + cam_ope_free_io_config(ctx_data->req_list[req_idx]); + kzfree(ctx_data->req_list[req_idx]); + ctx_data->req_list[req_idx] = NULL; + clear_bit(req_idx, ctx_data->bitmap); + + return 0; +} + +static int cam_ope_mgr_enqueue_config(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_hw_config_args *config_args) +{ + int rc = 0; + uint64_t request_id = 0; + struct crm_workq_task *task; + struct ope_cmd_work_data *task_data; + struct cam_hw_update_entry *hw_update_entries; + struct cam_ope_request *ope_req = NULL; + + ope_req = config_args->priv; + request_id = config_args->request_id; + hw_update_entries = config_args->hw_update_entries; + + CAM_DBG(CAM_OPE, "req_id = %lld %pK", request_id, config_args->priv); + + task = cam_req_mgr_workq_get_task(ope_hw_mgr->cmd_work); + if (!task) { + CAM_ERR(CAM_OPE, "no empty task"); + return -ENOMEM; + } + + task_data = (struct ope_cmd_work_data *)task->payload; + task_data->data = (void *)hw_update_entries->addr; + task_data->req_id = request_id; + task_data->type = OPE_WORKQ_TASK_CMD_TYPE; + task->process_cb = cam_ope_mgr_process_cmd; + rc = cam_req_mgr_workq_enqueue_task(task, ctx_data, + CRM_TASK_PRIORITY_0); + + return rc; +} + +static int cam_ope_mgr_config_hw(void *hw_priv, void *hw_config_args) +{ + int rc = 0; + struct cam_ope_hw_mgr *hw_mgr = hw_priv; + struct cam_hw_config_args *config_args = hw_config_args; + struct cam_ope_ctx *ctx_data = NULL; + struct cam_ope_request *ope_req = NULL; + struct cam_cdm_bl_request *cdm_cmd; + + CAM_DBG(CAM_OPE, "E"); + if (!hw_mgr || !config_args) { + CAM_ERR(CAM_OPE, "Invalid arguments %pK %pK", + hw_mgr, config_args); + return -EINVAL; + } + + if (!config_args->num_hw_update_entries) { + CAM_ERR(CAM_OPE, "No hw update enteries are available"); + return -EINVAL; + } + + ctx_data = config_args->ctxt_to_hw_map; + mutex_lock(&hw_mgr->hw_mgr_mutex); + mutex_lock(&ctx_data->ctx_mutex); + if (ctx_data->ctx_state != OPE_CTX_STATE_ACQUIRED) { + mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + CAM_ERR(CAM_OPE, "ctx id :%u is not in use", + ctx_data->ctx_id); + return -EINVAL; + } + + ope_req = config_args->priv; + cdm_cmd = (struct cam_cdm_bl_request *) + config_args->hw_update_entries->addr; + cdm_cmd->cookie = ope_req->req_idx; + + cam_ope_mgr_ope_clk_update(hw_mgr, ctx_data, ope_req->req_idx); + ctx_data->req_list[ope_req->req_idx]->submit_timestamp = ktime_get(); + + if (ope_req->request_id <= ctx_data->last_flush_req) + CAM_WARN(CAM_OPE, + "Anomaly submitting flushed req %llu [last_flush %llu] in ctx %u", + ope_req->request_id, ctx_data->last_flush_req, + ctx_data->ctx_id); + + rc = cam_ope_mgr_enqueue_config(hw_mgr, ctx_data, config_args); + if (rc) + goto config_err; + + CAM_DBG(CAM_REQ, "req_id %llu, ctx_id %u io config", + ope_req->request_id, ctx_data->ctx_id); + + mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + return rc; +config_err: + cam_ope_mgr_handle_config_err(config_args, ctx_data); + mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static void cam_ope_mgr_print_io_bufs(struct cam_packet *packet, + int32_t iommu_hdl, int32_t sec_mmu_hdl, uint32_t pf_buf_info, + bool *mem_found) +{ + dma_addr_t iova_addr; + size_t src_buf_size; + int i; + int j; + int rc = 0; + int32_t mmu_hdl; + + struct cam_buf_io_cfg *io_cfg = NULL; + + if (mem_found) + *mem_found = false; + + io_cfg = (struct cam_buf_io_cfg *)((uint32_t *)&packet->payload + + packet->io_configs_offset / 4); + + for (i = 0; i < packet->num_io_configs; i++) { + for (j = 0; j < CAM_PACKET_MAX_PLANES; j++) { + if (!io_cfg[i].mem_handle[j]) + break; + + if (GET_FD_FROM_HANDLE(io_cfg[i].mem_handle[j]) == + GET_FD_FROM_HANDLE(pf_buf_info)) { + CAM_INFO(CAM_OPE, + "Found PF at port: %d mem %x fd: %x", + io_cfg[i].resource_type, + io_cfg[i].mem_handle[j], + pf_buf_info); + if (mem_found) + *mem_found = true; + } + + CAM_INFO(CAM_OPE, "port: %d f: %u format: %d dir %d", + io_cfg[i].resource_type, + io_cfg[i].fence, + io_cfg[i].format, + io_cfg[i].direction); + + mmu_hdl = cam_mem_is_secure_buf( + io_cfg[i].mem_handle[j]) ? sec_mmu_hdl : + iommu_hdl; + rc = cam_mem_get_io_buf(io_cfg[i].mem_handle[j], + mmu_hdl, &iova_addr, &src_buf_size); + if (rc < 0) { + CAM_ERR(CAM_UTIL, + "get src buf address fail rc %d mem %x", + rc, io_cfg[i].mem_handle[j]); + continue; + } + if ((iova_addr & 0xFFFFFFFF) != iova_addr) { + CAM_ERR(CAM_OPE, "Invalid mapped address"); + rc = -EINVAL; + continue; + } + + CAM_INFO(CAM_OPE, + "pln %d dir %d w %d h %d s %u sh %u sz %d addr 0x%x off 0x%x memh %x", + j, io_cfg[i].direction, + io_cfg[i].planes[j].width, + io_cfg[i].planes[j].height, + io_cfg[i].planes[j].plane_stride, + io_cfg[i].planes[j].slice_height, + (int32_t)src_buf_size, + (unsigned int)iova_addr, + io_cfg[i].offsets[j], + io_cfg[i].mem_handle[j]); + + iova_addr += io_cfg[i].offsets[j]; + + } + } + cam_packet_dump_patch_info(packet, ope_hw_mgr->iommu_hdl, + ope_hw_mgr->iommu_sec_hdl); +} + +static int cam_ope_mgr_cmd(void *hw_mgr_priv, void *cmd_args) +{ + int rc = 0; + struct cam_hw_cmd_args *hw_cmd_args = cmd_args; + struct cam_ope_hw_mgr *hw_mgr = hw_mgr_priv; + + if (!hw_mgr_priv || !cmd_args) { + CAM_ERR(CAM_OPE, "Invalid arguments"); + return -EINVAL; + } + + switch (hw_cmd_args->cmd_type) { + case CAM_HW_MGR_CMD_DUMP_PF_INFO: + cam_ope_mgr_print_io_bufs( + hw_cmd_args->u.pf_args.pf_data.packet, + hw_mgr->iommu_hdl, + hw_mgr->iommu_sec_hdl, + hw_cmd_args->u.pf_args.buf_info, + hw_cmd_args->u.pf_args.mem_found); + + break; + default: + CAM_ERR(CAM_OPE, "Invalid cmd"); + } + + return rc; +} + +static int cam_ope_mgr_hw_open_u(void *hw_priv, void *fw_download_args) +{ + struct cam_ope_hw_mgr *hw_mgr; + int rc = 0; + + if (!hw_priv) { + CAM_ERR(CAM_OPE, "Invalid args: %pK", hw_priv); + return -EINVAL; + } + + hw_mgr = hw_priv; + if (!hw_mgr->open_cnt) { + hw_mgr->open_cnt++; + } else { + rc = -EBUSY; + CAM_ERR(CAM_OPE, "Multiple opens are not supported"); + } + + return rc; +} + +static int cam_ope_mgr_hw_close_u(void *hw_priv, void *hw_close_args) +{ + struct cam_ope_hw_mgr *hw_mgr; + int rc = 0; + + if (!hw_priv) { + CAM_ERR(CAM_OPE, "Invalid args: %pK", hw_priv); + return -EINVAL; + } + + hw_mgr = hw_priv; + if (!hw_mgr->open_cnt) { + rc = -EINVAL; + CAM_ERR(CAM_OPE, "device is already closed"); + } else { + hw_mgr->open_cnt--; + } + + return rc; +} + +static int cam_ope_mgr_flush_req(struct cam_ope_ctx *ctx_data, + struct cam_hw_flush_args *flush_args) +{ + int idx; + int64_t request_id; + + request_id = *(int64_t *)flush_args->flush_req_pending[0]; + for (idx = 0; idx < CAM_CTX_REQ_MAX; idx++) { + if (!ctx_data->req_list[idx]) + continue; + + if (ctx_data->req_list[idx]->request_id != request_id) + continue; + + ctx_data->req_list[idx]->request_id = 0; + kzfree(ctx_data->req_list[idx]->cdm_cmd); + ctx_data->req_list[idx]->cdm_cmd = NULL; + cam_ope_free_io_config(ctx_data->req_list[idx]); + kzfree(ctx_data->req_list[idx]); + ctx_data->req_list[idx] = NULL; + clear_bit(idx, ctx_data->bitmap); + } + + return 0; +} + +static int cam_ope_mgr_flush_all(struct cam_ope_ctx *ctx_data, + struct cam_hw_flush_args *flush_args) +{ + int i, rc; + struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; + + rc = cam_cdm_flush_hw(ctx_data->ope_cdm.cdm_handle); + + mutex_lock(&ctx_data->ctx_mutex); + for (i = 0; i < hw_mgr->num_ope; i++) { + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RESET, + NULL, 0); + if (rc) + CAM_ERR(CAM_OPE, "OPE Dev reset failed: %d", rc); + } + + for (i = 0; i < CAM_CTX_REQ_MAX; i++) { + if (!ctx_data->req_list[i]) + continue; + + ctx_data->req_list[i]->request_id = 0; + kzfree(ctx_data->req_list[i]->cdm_cmd); + ctx_data->req_list[i]->cdm_cmd = NULL; + cam_ope_free_io_config(ctx_data->req_list[i]); + kzfree(ctx_data->req_list[i]); + ctx_data->req_list[i] = NULL; + clear_bit(i, ctx_data->bitmap); + } + mutex_unlock(&ctx_data->ctx_mutex); + + return rc; +} + +static int cam_ope_mgr_hw_dump(void *hw_priv, void *hw_dump_args) +{ + struct cam_ope_ctx *ctx_data; + struct cam_ope_hw_mgr *hw_mgr = hw_priv; + struct cam_hw_dump_args *dump_args; + int idx; + ktime_t cur_time; + struct timespec64 cur_ts, req_ts; + uint64_t diff; + + if ((!hw_priv) || (!hw_dump_args)) { + CAM_ERR(CAM_OPE, "Invalid params %pK %pK", + hw_priv, hw_dump_args); + return -EINVAL; + } + + dump_args = (struct cam_hw_dump_args *)hw_dump_args; + ctx_data = dump_args->ctxt_to_hw_map; + + if (!ctx_data) { + CAM_ERR(CAM_OPE, "Invalid context"); + return -EINVAL; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + mutex_lock(&ctx_data->ctx_mutex); + + CAM_INFO(CAM_OPE, "Req %lld", dump_args->request_id); + for (idx = 0; idx < CAM_CTX_REQ_MAX; idx++) { + if (!ctx_data->req_list[idx]) + continue; + + if (ctx_data->req_list[idx]->request_id == + dump_args->request_id) + break; + } + + /* no matching request found */ + if (idx == CAM_CTX_REQ_MAX) { + mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return 0; + } + + cur_time = ktime_get(); + diff = ktime_us_delta(cur_time, + ctx_data->req_list[idx]->submit_timestamp); + cur_ts = ktime_to_timespec64(cur_time); + req_ts = ktime_to_timespec64(ctx_data->req_list[idx]->submit_timestamp); + + if (diff < (ctx_data->req_timer_timeout * 1000)) { + CAM_INFO(CAM_OPE, "No Error req %llu %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return 0; + } + + CAM_ERR(CAM_OPE, "Error req %llu %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + + mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return 0; +} + +static int cam_ope_mgr_hw_flush(void *hw_priv, void *hw_flush_args) +{ + struct cam_hw_flush_args *flush_args = hw_flush_args; + struct cam_ope_ctx *ctx_data; + struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; + + if ((!hw_priv) || (!hw_flush_args)) { + CAM_ERR(CAM_OPE, "Input params are Null"); + return -EINVAL; + } + + ctx_data = flush_args->ctxt_to_hw_map; + if (!ctx_data) { + CAM_ERR(CAM_OPE, "Ctx data is NULL"); + return -EINVAL; + } + + if ((flush_args->flush_type >= CAM_FLUSH_TYPE_MAX) || + (flush_args->flush_type < CAM_FLUSH_TYPE_REQ)) { + CAM_ERR(CAM_OPE, "Invalid flush type: %d", + flush_args->flush_type); + return -EINVAL; + } + + switch (flush_args->flush_type) { + case CAM_FLUSH_TYPE_ALL: + mutex_lock(&hw_mgr->hw_mgr_mutex); + ctx_data->last_flush_req = flush_args->last_flush_req; + + CAM_DBG(CAM_REQ, "ctx_id %d Flush type %d last_flush_req %u", + ctx_data->ctx_id, flush_args->flush_type, + ctx_data->last_flush_req); + + cam_ope_mgr_flush_all(ctx_data, flush_args); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + break; + case CAM_FLUSH_TYPE_REQ: + mutex_lock(&ctx_data->ctx_mutex); + if (flush_args->num_req_active) { + CAM_ERR(CAM_OPE, "Flush request is not supported"); + mutex_unlock(&ctx_data->ctx_mutex); + return -EINVAL; + } + if (flush_args->num_req_pending) + cam_ope_mgr_flush_req(ctx_data, flush_args); + mutex_unlock(&ctx_data->ctx_mutex); + break; + default: + CAM_ERR(CAM_OPE, "Invalid flush type: %d", + flush_args->flush_type); + return -EINVAL; + } + + return 0; +} + +static int cam_ope_mgr_alloc_devs(struct device_node *of_node) +{ + int rc; + uint32_t num_dev; + + rc = of_property_read_u32(of_node, "num-ope", &num_dev); + if (rc) { + CAM_ERR(CAM_OPE, "getting num of ope failed: %d", rc); + return -EINVAL; + } + + ope_hw_mgr->devices[OPE_DEV_OPE] = kzalloc( + sizeof(struct cam_hw_intf *) * num_dev, GFP_KERNEL); + if (!ope_hw_mgr->devices[OPE_DEV_OPE]) + return -ENOMEM; + + return 0; +} + +static int cam_ope_mgr_init_devs(struct device_node *of_node) +{ + int rc = 0; + int count, i; + const char *name = NULL; + struct device_node *child_node = NULL; + struct platform_device *child_pdev = NULL; + struct cam_hw_intf *child_dev_intf = NULL; + struct cam_hw_info *ope_dev; + struct cam_hw_soc_info *soc_info = NULL; + + rc = cam_ope_mgr_alloc_devs(of_node); + if (rc) + return rc; + + count = of_property_count_strings(of_node, "compat-hw-name"); + if (!count) { + CAM_ERR(CAM_OPE, "no compat hw found in dev tree, cnt = %d", + count); + rc = -EINVAL; + goto compat_hw_name_failed; + } + + for (i = 0; i < count; i++) { + rc = of_property_read_string_index(of_node, "compat-hw-name", + i, &name); + if (rc) { + CAM_ERR(CAM_OPE, "getting dev object name failed"); + goto compat_hw_name_failed; + } + + child_node = of_find_node_by_name(NULL, name); + if (!child_node) { + CAM_ERR(CAM_OPE, "Cannot find node in dtsi %s", name); + rc = -ENODEV; + goto compat_hw_name_failed; + } + + child_pdev = of_find_device_by_node(child_node); + if (!child_pdev) { + CAM_ERR(CAM_OPE, "failed to find device on bus %s", + child_node->name); + rc = -ENODEV; + of_node_put(child_node); + goto compat_hw_name_failed; + } + + child_dev_intf = (struct cam_hw_intf *)platform_get_drvdata( + child_pdev); + if (!child_dev_intf) { + CAM_ERR(CAM_OPE, "no child device"); + of_node_put(child_node); + goto compat_hw_name_failed; + } + ope_hw_mgr->devices[child_dev_intf->hw_type] + [child_dev_intf->hw_idx] = child_dev_intf; + + if (!child_dev_intf->hw_ops.process_cmd) + goto compat_hw_name_failed; + + of_node_put(child_node); + } + + ope_hw_mgr->num_ope = count; + for (i = 0; i < count; i++) { + ope_hw_mgr->ope_dev_intf[i] = + ope_hw_mgr->devices[OPE_DEV_OPE][i]; + ope_dev = ope_hw_mgr->ope_dev_intf[i]->hw_priv; + soc_info = &ope_dev->soc_info; + ope_hw_mgr->cdm_reg_map[i][0] = + soc_info->reg_map[0].mem_base; + } + + ope_hw_mgr->hfi_en = of_property_read_bool(of_node, "hfi_en"); + + return 0; +compat_hw_name_failed: + kfree(ope_hw_mgr->devices[OPE_DEV_OPE]); + ope_hw_mgr->devices[OPE_DEV_OPE] = NULL; + return rc; +} + +static int cam_ope_mgr_create_wq(void) +{ + + int rc; + int i; + + rc = cam_req_mgr_workq_create("ope_command_queue", OPE_WORKQ_NUM_TASK, + &ope_hw_mgr->cmd_work, CRM_WORKQ_USAGE_NON_IRQ, + 0); + if (rc) { + CAM_ERR(CAM_OPE, "unable to create a command worker"); + goto cmd_work_failed; + } + + rc = cam_req_mgr_workq_create("ope_message_queue", OPE_WORKQ_NUM_TASK, + &ope_hw_mgr->msg_work, CRM_WORKQ_USAGE_IRQ, 0); + if (rc) { + CAM_ERR(CAM_OPE, "unable to create a message worker"); + goto msg_work_failed; + } + + rc = cam_req_mgr_workq_create("ope_timer_queue", OPE_WORKQ_NUM_TASK, + &ope_hw_mgr->timer_work, CRM_WORKQ_USAGE_IRQ, 0); + if (rc) { + CAM_ERR(CAM_OPE, "unable to create a timer worker"); + goto timer_work_failed; + } + + ope_hw_mgr->cmd_work_data = + kzalloc(sizeof(struct ope_cmd_work_data) * OPE_WORKQ_NUM_TASK, + GFP_KERNEL); + if (!ope_hw_mgr->cmd_work_data) { + rc = -ENOMEM; + goto cmd_work_data_failed; + } + + ope_hw_mgr->msg_work_data = + kzalloc(sizeof(struct ope_msg_work_data) * OPE_WORKQ_NUM_TASK, + GFP_KERNEL); + if (!ope_hw_mgr->msg_work_data) { + rc = -ENOMEM; + goto msg_work_data_failed; + } + + ope_hw_mgr->timer_work_data = + kzalloc(sizeof(struct ope_clk_work_data) * OPE_WORKQ_NUM_TASK, + GFP_KERNEL); + if (!ope_hw_mgr->timer_work_data) { + rc = -ENOMEM; + goto timer_work_data_failed; + } + + for (i = 0; i < OPE_WORKQ_NUM_TASK; i++) + ope_hw_mgr->msg_work->task.pool[i].payload = + &ope_hw_mgr->msg_work_data[i]; + + for (i = 0; i < OPE_WORKQ_NUM_TASK; i++) + ope_hw_mgr->cmd_work->task.pool[i].payload = + &ope_hw_mgr->cmd_work_data[i]; + + for (i = 0; i < OPE_WORKQ_NUM_TASK; i++) + ope_hw_mgr->timer_work->task.pool[i].payload = + &ope_hw_mgr->timer_work_data[i]; + return 0; + + +timer_work_data_failed: + kfree(ope_hw_mgr->msg_work_data); +msg_work_data_failed: + kfree(ope_hw_mgr->cmd_work_data); +cmd_work_data_failed: + cam_req_mgr_workq_destroy(&ope_hw_mgr->timer_work); +timer_work_failed: + cam_req_mgr_workq_destroy(&ope_hw_mgr->msg_work); +msg_work_failed: + cam_req_mgr_workq_destroy(&ope_hw_mgr->cmd_work); +cmd_work_failed: + return rc; +} + +static int cam_ope_create_debug_fs(void) +{ + ope_hw_mgr->dentry = debugfs_create_dir("camera_ope", + NULL); + + if (!ope_hw_mgr->dentry) { + CAM_ERR(CAM_OPE, "failed to create dentry"); + return -ENOMEM; + } + + if (!debugfs_create_bool("frame_dump_enable", + 0644, + ope_hw_mgr->dentry, + &ope_hw_mgr->frame_dump_enable)) { + CAM_ERR(CAM_OPE, + "failed to create dump_enable_debug"); + goto err; + } + + if (!debugfs_create_bool("dump_req_data_enable", + 0644, + ope_hw_mgr->dentry, + &ope_hw_mgr->dump_req_data_enable)) { + CAM_ERR(CAM_OPE, + "failed to create dump_enable_debug"); + goto err; + } + + return 0; +err: + debugfs_remove_recursive(ope_hw_mgr->dentry); + return -ENOMEM; +} + + +int cam_ope_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, + int *iommu_hdl) +{ + int i, rc = 0, j; + struct cam_hw_mgr_intf *hw_mgr_intf; + struct cam_iommu_handle cdm_handles; + + if (!of_node || !hw_mgr_hdl) { + CAM_ERR(CAM_OPE, "Invalid args of_node %pK hw_mgr %pK", + of_node, hw_mgr_hdl); + return -EINVAL; + } + hw_mgr_intf = (struct cam_hw_mgr_intf *)hw_mgr_hdl; + + ope_hw_mgr = kzalloc(sizeof(struct cam_ope_hw_mgr), GFP_KERNEL); + if (!ope_hw_mgr) { + CAM_ERR(CAM_OPE, "Unable to allocate mem for: size = %d", + sizeof(struct cam_ope_hw_mgr)); + return -ENOMEM; + } + + hw_mgr_intf->hw_mgr_priv = ope_hw_mgr; + hw_mgr_intf->hw_get_caps = cam_ope_mgr_get_hw_caps; + hw_mgr_intf->hw_acquire = cam_ope_mgr_acquire_hw; + hw_mgr_intf->hw_release = cam_ope_mgr_release_hw; + hw_mgr_intf->hw_start = NULL; + hw_mgr_intf->hw_stop = NULL; + hw_mgr_intf->hw_prepare_update = cam_ope_mgr_prepare_hw_update; + hw_mgr_intf->hw_config_stream_settings = NULL; + hw_mgr_intf->hw_config = cam_ope_mgr_config_hw; + hw_mgr_intf->hw_read = NULL; + hw_mgr_intf->hw_write = NULL; + hw_mgr_intf->hw_cmd = cam_ope_mgr_cmd; + hw_mgr_intf->hw_open = cam_ope_mgr_hw_open_u; + hw_mgr_intf->hw_close = cam_ope_mgr_hw_close_u; + hw_mgr_intf->hw_flush = cam_ope_mgr_hw_flush; + hw_mgr_intf->hw_dump = cam_ope_mgr_hw_dump; + + ope_hw_mgr->secure_mode = false; + mutex_init(&ope_hw_mgr->hw_mgr_mutex); + spin_lock_init(&ope_hw_mgr->hw_mgr_lock); + + for (i = 0; i < OPE_CTX_MAX; i++) { + ope_hw_mgr->ctx[i].bitmap_size = + BITS_TO_LONGS(CAM_CTX_REQ_MAX) * + sizeof(long); + ope_hw_mgr->ctx[i].bitmap = kzalloc( + ope_hw_mgr->ctx[i].bitmap_size, GFP_KERNEL); + if (!ope_hw_mgr->ctx[i].bitmap) { + CAM_ERR(CAM_OPE, "bitmap allocation failed: size = %d", + ope_hw_mgr->ctx[i].bitmap_size); + rc = -ENOMEM; + goto ope_ctx_bitmap_failed; + } + ope_hw_mgr->ctx[i].bits = ope_hw_mgr->ctx[i].bitmap_size * + BITS_PER_BYTE; + mutex_init(&ope_hw_mgr->ctx[i].ctx_mutex); + } + + rc = cam_ope_mgr_init_devs(of_node); + if (rc) + goto dev_init_failed; + + ope_hw_mgr->ctx_bitmap_size = + BITS_TO_LONGS(OPE_CTX_MAX) * sizeof(long); + ope_hw_mgr->ctx_bitmap = kzalloc(ope_hw_mgr->ctx_bitmap_size, + GFP_KERNEL); + if (!ope_hw_mgr->ctx_bitmap) { + rc = -ENOMEM; + goto ctx_bitmap_alloc_failed; + } + + ope_hw_mgr->ctx_bits = ope_hw_mgr->ctx_bitmap_size * + BITS_PER_BYTE; + + rc = cam_smmu_get_handle("ope", &ope_hw_mgr->iommu_hdl); + if (rc) { + CAM_ERR(CAM_OPE, "get mmu handle failed: %d", rc); + goto ope_get_hdl_failed; + } + + rc = cam_smmu_get_handle("cam-secure", &ope_hw_mgr->iommu_sec_hdl); + if (rc) { + CAM_ERR(CAM_OPE, "get secure mmu handle failed: %d", rc); + goto secure_hdl_failed; + } + + rc = cam_cdm_get_iommu_handle("ope", &cdm_handles); + if (rc) { + CAM_ERR(CAM_OPE, "ope cdm handle get is failed: %d", rc); + goto ope_cdm_hdl_failed; + } + + ope_hw_mgr->iommu_cdm_hdl = cdm_handles.non_secure; + ope_hw_mgr->iommu_sec_cdm_hdl = cdm_handles.secure; + CAM_DBG(CAM_OPE, "iommu hdls %x %x cdm %x %x", + ope_hw_mgr->iommu_hdl, ope_hw_mgr->iommu_sec_hdl, + ope_hw_mgr->iommu_cdm_hdl, + ope_hw_mgr->iommu_sec_cdm_hdl); + + rc = cam_ope_mgr_create_wq(); + if (rc) + goto ope_wq_create_failed; + + cam_ope_create_debug_fs(); + + if (iommu_hdl) + *iommu_hdl = ope_hw_mgr->iommu_hdl; + + return rc; + +ope_wq_create_failed: + ope_hw_mgr->iommu_cdm_hdl = -1; + ope_hw_mgr->iommu_sec_cdm_hdl = -1; +ope_cdm_hdl_failed: + cam_smmu_destroy_handle(ope_hw_mgr->iommu_sec_hdl); + ope_hw_mgr->iommu_sec_hdl = -1; +secure_hdl_failed: + cam_smmu_destroy_handle(ope_hw_mgr->iommu_hdl); + ope_hw_mgr->iommu_hdl = -1; +ope_get_hdl_failed: + kzfree(ope_hw_mgr->ctx_bitmap); + ope_hw_mgr->ctx_bitmap = NULL; + ope_hw_mgr->ctx_bitmap_size = 0; + ope_hw_mgr->ctx_bits = 0; +ctx_bitmap_alloc_failed: + kzfree(ope_hw_mgr->devices[OPE_DEV_OPE]); + ope_hw_mgr->devices[OPE_DEV_OPE] = NULL; +dev_init_failed: +ope_ctx_bitmap_failed: + mutex_destroy(&ope_hw_mgr->hw_mgr_mutex); + for (j = i - 1; j >= 0; j--) { + mutex_destroy(&ope_hw_mgr->ctx[j].ctx_mutex); + kzfree(ope_hw_mgr->ctx[j].bitmap); + ope_hw_mgr->ctx[j].bitmap = NULL; + ope_hw_mgr->ctx[j].bitmap_size = 0; + ope_hw_mgr->ctx[j].bits = 0; + } + kzfree(ope_hw_mgr); + ope_hw_mgr = NULL; + + return rc; +} + diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h new file mode 100644 index 0000000000000000000000000000000000000000..244c2d727dbecd07124d5ac7cbeb0f17b935abd2 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -0,0 +1,609 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef CAM_OPE_HW_MGR_H +#define CAM_OPE_HW_MGR_H + +#include +#include +#include +#include "ope_hw.h" +#include "cam_hw_mgr_intf.h" +#include "cam_hw_intf.h" +#include "cam_req_mgr_workq.h" +#include "cam_mem_mgr.h" +#include "cam_smmu_api.h" +#include "cam_soc_util.h" +#include "cam_req_mgr_timer.h" +#include "cam_context.h" +#include "ope_hw.h" +#include "cam_cdm_intf_api.h" +#include "cam_req_mgr_timer.h" + +#define OPE_CTX_MAX 32 +#define CAM_FRAME_CMD_MAX 20 + + +#define OPE_WORKQ_NUM_TASK 100 +#define OPE_WORKQ_TASK_CMD_TYPE 1 +#define OPE_WORKQ_TASK_MSG_TYPE 2 + +#define OPE_PACKET_SIZE 0 +#define OPE_PACKET_TYPE 1 +#define OPE_PACKET_OPCODE 2 + +#define OPE_PACKET_MAX_CMD_BUFS 4 + +#define OPE_MAX_OUTPUT_SUPPORTED 8 +#define OPE_MAX_INPUT_SUPPORTED 3 + +#define OPE_FRAME_PROCESS_SUCCESS 0 +#define OPE_FRAME_PROCESS_FAILURE 1 + +#define OPE_CTX_STATE_FREE 0 +#define OPE_CTX_STATE_IN_USE 1 +#define OPE_CTX_STATE_ACQUIRED 2 +#define OPE_CTX_STATE_RELEASE 3 + +#define OPE_CMDS OPE_MAX_CMD_BUFS +#define CAM_MAX_IN_RES 8 + +#define OPE_MAX_CDM_BLS 32 + +#define CAM_OPE_MAX_PER_PATH_VOTES 6 +#define CAM_OPE_BW_CONFIG_UNKNOWN 0 +#define CAM_OPE_BW_CONFIG_V2 2 + +#define CLK_HW_OPE 0x0 +#define CLK_HW_MAX 0x1 + +#define OPE_DEVICE_IDLE_TIMEOUT 400 +#define OPE_REQUEST_RT_TIMEOUT 200 +#define OPE_REQUEST_NRT_TIMEOUT 400 + +/** + * struct cam_ope_clk_bw_request_v2 + * @budget_ns: Time required to process frame + * @frame_cycles: Frame cycles needed to process the frame + * @rt_flag: Flag to indicate real time stream + * @reserved: Reserved for future use + * @num_paths: Number of paths for per path bw vote + * @axi_path: Per path vote info for OPE + */ +struct cam_ope_clk_bw_req_internal_v2 { + uint64_t budget_ns; + uint32_t frame_cycles; + uint32_t rt_flag; + uint32_t reserved; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[CAM_OPE_MAX_PER_PATH_VOTES]; +}; + +/** + * struct cam_ope_clk_bw_request + * @budget_ns: Time required to process frame + * @frame_cycles: Frame cycles needed to process the frame + * @rt_flag: Flag to indicate real time stream + * @uncompressed_bw: Bandwidth required to process frame + * @compressed_bw: Compressed bandwidth to process frame + */ +struct cam_ope_clk_bw_request { + uint64_t budget_ns; + uint32_t frame_cycles; + uint32_t rt_flag; + uint64_t uncompressed_bw; + uint64_t compressed_bw; +}; + +/** + * struct cam_ctx_clk_info + * @curr_fc: Context latest request frame cycles + * @rt_flag: Flag to indicate real time request + * @base_clk: Base clock to process the request + * @reserved: Reserved field + * @uncompressed_bw: Current bandwidth voting + * @compressed_bw: Current compressed bandwidth voting + * @clk_rate: Supported clock rates for the context + * @num_paths: Number of valid AXI paths + * @axi_path: ctx based per path bw vote + */ +struct cam_ctx_clk_info { + uint32_t curr_fc; + uint32_t rt_flag; + uint32_t base_clk; + uint32_t reserved; + uint64_t uncompressed_bw; + uint64_t compressed_bw; + int32_t clk_rate[CAM_MAX_VOTE]; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[CAM_OPE_MAX_PER_PATH_VOTES]; +}; + +/** + * struct ope_cmd_generic_blob + * @ctx: Current context info + * @req_info_idx: Index used for request + * @io_buf_addr: pointer to io buffer address + */ +struct ope_cmd_generic_blob { + struct cam_ope_ctx *ctx; + uint32_t req_idx; + uint64_t *io_buf_addr; +}; + +/** + * struct cam_ope_clk_info + * @base_clk: Base clock to process request + * @curr_clk: Current clock of hadrware + * @threshold: Threshold for overclk count + * @over_clked: Over clock count + * @uncompressed_bw: Current bandwidth voting + * @compressed_bw: Current compressed bandwidth voting + * @num_paths: Number of AXI vote paths + * @axi_path: Current per path bw vote info + * @hw_type: IPE/BPS device type + * @watch_dog: watchdog timer handle + * @watch_dog_reset_counter: Counter for watch dog reset + */ +struct cam_ope_clk_info { + uint32_t base_clk; + uint32_t curr_clk; + uint32_t threshold; + uint32_t over_clked; + uint64_t uncompressed_bw; + uint64_t compressed_bw; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[CAM_OPE_MAX_PER_PATH_VOTES]; + uint32_t hw_type; + struct cam_req_mgr_timer *watch_dog; + uint32_t watch_dog_reset_counter; +}; + +/** + * struct ope_cmd_work_data + * + * @type: Type of work data + * @data: Private data + * @req_id: Request Id + */ +struct ope_cmd_work_data { + uint32_t type; + void *data; + int64_t req_id; +}; + +/** + * struct ope_msg_work_data + * + * @type: Type of work data + * @data: Private data + * @irq_status: IRQ status + */ +struct ope_msg_work_data { + uint32_t type; + void *data; + uint32_t irq_status; +}; + +/** + * struct ope_clk_work_data + * + * @type: Type of work data + * @data: Private data + */ +struct ope_clk_work_data { + uint32_t type; + void *data; +}; + +/** + * struct cdm_dmi_cmd + * + * @length: Number of bytes in LUT + * @reserved: reserved bits + * @cmd: Command ID (CDMCmd) + * @addr: Address of the LUT in memory + * @DMIAddr: Address of the target DMI config register + * @DMISel: DMI identifier + */ +struct cdm_dmi_cmd { + unsigned int length : 16; + unsigned int reserved : 8; + unsigned int cmd : 8; + unsigned int addr; + unsigned int DMIAddr : 24; + unsigned int DMISel : 8; +} __attribute__((__packed__)); + +/** + * struct ope_debug_buffer + * + * @cpu_addr: CPU address + * @iova_addr: IOVA address + * @len: Buffer length + * @size: Buffer Size + * @offset: buffer offset + */ +struct ope_debug_buffer { + uintptr_t cpu_addr; + dma_addr_t iova_addr; + size_t len; + uint32_t size; + uint32_t offset; +}; + +/** + * struct ope_kmd_buffer + * + * @mem_handle: Memory handle + * @cpu_addr: CPU address + * @iova_addr: IOVA address + * @iova_cdm_addr: CDM IOVA address + * @offset: Offset of buffer + * @len: Buffer length + * @size: Buffer Size + */ +struct ope_kmd_buffer { + uint32_t mem_handle; + uintptr_t cpu_addr; + dma_addr_t iova_addr; + dma_addr_t iova_cdm_addr; + uint32_t offset; + size_t len; + uint32_t size; +}; + +struct ope_stripe_settings { + uintptr_t cpu_addr; + dma_addr_t iova_addr; + size_t len; + uint32_t size; + uint32_t buf_type; + uint32_t type_buffered; +}; + +/** + * struct ope_pass_settings + * + * @cpu_addr: CPU address + * @iova_addr: IOVA address + * @len: Buffer length + * @size: Buffer Size + * @idx: Pass Index + * @buf_type: Direct/Indirect type + * @type_buffered: SB/DB types + */ +struct ope_pass_settings { + uintptr_t cpu_addr; + dma_addr_t iova_addr; + size_t len; + uint32_t size; + uint32_t idx; + uint32_t buf_type; + uint32_t type_buffered; +}; + +/** + * struct ope_frame_settings + * + * @cpu_addr: CPU address + * @iova_addr: IOVA address + * @offset: offset + * @len: Buffer length + * @size: Buffer Size + * @buf_type: Direct/Indirect type + * @type_buffered: SB/DB types + * @prefecth_disable: Disable prefetch + */ +struct ope_frame_settings { + uintptr_t cpu_addr; + dma_addr_t iova_addr; + uint32_t offset; + size_t len; + uint32_t size; + uint32_t buf_type; + uint32_t type_buffered; + uint32_t prefecth_disable; +}; + +/** + * struct ope_stripe_io + * + * @format: Stripe format + * @s_location: Stripe location + * @cpu_addr: Stripe CPU address + * @iova_addr: Stripe IOVA address + * @width: Stripe width + * @height: Stripe height + * @stride: Stripe stride + * @unpack_format: Unpack format + * @pack_format: Packing format + * @alignment: Stripe alignment + * @offset: Stripe offset + * @x_init: X_init + * @subsample_period: Subsample period + * @subsample_pattern: Subsample pattern + * @len: Stripe buffer length + * @disable_bus: disable bus for the stripe + */ +struct ope_stripe_io { + uint32_t format; + uint32_t s_location; + uintptr_t cpu_addr; + dma_addr_t iova_addr; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t unpack_format; + uint32_t pack_format; + uint32_t alignment; + uint32_t offset; + uint32_t x_init; + uint32_t subsample_period; + uint32_t subsample_pattern; + size_t len; + uint32_t disable_bus; +}; + +/** + * struct ope_io_buf + * + * @direction: Direction of a buffer + * @resource_type: Resource type of IO Buffer + * @format: Format + * @fence: Fence + * @num_planes: Number of planes + * @num_stripes: Number of stripes + * @s_io: Stripe info + */ +struct ope_io_buf { + uint32_t direction; + uint32_t resource_type; + uint32_t format; + uint32_t fence; + uint32_t num_planes; + uint32_t pix_pattern; + uint32_t num_stripes[OPE_MAX_PLANES]; + struct ope_stripe_io s_io[OPE_MAX_PLANES][OPE_MAX_STRIPES]; +}; + +/** + * struct cam_ope_request + * + * @request_id: Request Id + * @req_idx: Index in request list + * @state: Request state + * @num_batch: Number of batches + * @num_cmd_bufs: Number of command buffers + * @num_frame_bufs: Number of frame buffers + * @num_pass_bufs: Number of pass Buffers + * @num_stripes: Number of Stripes + * @num_io_bufs: Number of IO Buffers + * @in_resource: Input resource + * @num_stripe_cmd_bufs: Command buffers per stripe + * @ope_kmd_buf: KMD buffer for OPE programming + * @ope_debug_buf: Debug buffer + * @io_buf: IO config info of a request + * @cdm_cmd: CDM command for OPE CDM + * @clk_info: Clock Info V1 + * @clk_info_v2: Clock Info V2 + * @hang_data: Debug data for HW error + * @submit_timestamp: Submit timestamp to hw + */ +struct cam_ope_request { + uint64_t request_id; + uint32_t req_idx; + uint32_t state; + uint32_t num_batch; + uint32_t num_cmd_bufs; + uint32_t num_frame_bufs; + uint32_t num_pass_bufs; + uint32_t num_stripes[OPE_MAX_BATCH_SIZE]; + uint32_t num_io_bufs[OPE_MAX_BATCH_SIZE]; + uint32_t in_resource; + uint8_t num_stripe_cmd_bufs[OPE_MAX_BATCH_SIZE][OPE_MAX_STRIPES]; + struct ope_kmd_buffer ope_kmd_buf; + struct ope_debug_buffer ope_debug_buf; + struct ope_io_buf *io_buf[OPE_MAX_BATCH_SIZE][OPE_MAX_IO_BUFS]; + struct cam_cdm_bl_request *cdm_cmd; + struct cam_ope_clk_bw_request clk_info; + struct cam_ope_clk_bw_req_internal_v2 clk_info_v2; + struct cam_hw_mgr_dump_pf_data hang_data; + ktime_t submit_timestamp; +}; + +/** + * struct cam_ope_cdm + * + * @cdm_handle: OPE CDM Handle + * @cdm_ops: OPE CDM Operations + */ +struct cam_ope_cdm { + uint32_t cdm_handle; + struct cam_cdm_utils_ops *cdm_ops; +}; + +/** + * struct cam_ope_ctx + * + * @context_priv: Private data of context + * @bitmap: Context bit map + * @bitmap_size: Context bit map size + * @bits: Context bit map bits + * @ctx_id: Context ID + * @ctx_state: State of a context + * @req_cnt: Requests count + * @ctx_mutex: Mutex for context + * @acquire_dev_cmd: Cam acquire command + * @ope_acquire: OPE acquire command + * @ctxt_event_cb: Callback of a context + * @req_list: Request List + * @ope_cdm: OPE CDM info + * @last_req_time: Timestamp of last request + * @req_watch_dog: Watchdog for requests + * @req_watch_dog_reset_counter: Request reset counter + * @clk_info: OPE Ctx clock info + * @clk_watch_dog: Clock watchdog + * @clk_watch_dog_reset_counter: Reset counter + * @last_flush_req: last flush req for this ctx + * @req_timer_timeout: req timer timeout value + */ +struct cam_ope_ctx { + void *context_priv; + size_t bitmap_size; + void *bitmap; + size_t bits; + uint32_t ctx_id; + uint32_t ctx_state; + uint32_t req_cnt; + struct mutex ctx_mutex; + struct cam_acquire_dev_cmd acquire_dev_cmd; + struct ope_acquire_dev_info ope_acquire; + cam_hw_event_cb_func ctxt_event_cb; + struct cam_ope_request *req_list[CAM_CTX_REQ_MAX]; + struct cam_ope_cdm ope_cdm; + uint64_t last_req_time; + struct cam_req_mgr_timer *req_watch_dog; + uint32_t req_watch_dog_reset_counter; + struct cam_ctx_clk_info clk_info; + struct cam_req_mgr_timer *clk_watch_dog; + uint32_t clk_watch_dog_reset_counter; + uint64_t last_flush_req; + uint64_t req_timer_timeout; +}; + +/** + * struct cam_ope_hw_mgr + * + * @open_cnt: OPE device open count + * @ope_ctx_cnt: Open context count + * @hw_mgr_mutex: Mutex for HW manager + * @hw_mgr_lock: Spinlock for HW manager + * @hfi_en: Flag for HFI + * @iommu_hdl: OPE Handle + * @iommu_sec_hdl: OPE Handle for secure + * @iommu_cdm_hdl: CDM Handle + * @iommu_sec_cdm_hdl: CDM Handle for secure + * @num_ope: Number of OPE + * @secure_mode: Mode of OPE operation + * @ctx_bitmap: Context bit map + * @ctx_bitmap_size: Context bit map size + * @ctx_bits: Context bit map bits + * @ctx: OPE context + * @devices: OPE devices + * @ope_caps: OPE capabilities + * @cmd_work: Command work + * @msg_work: Message work + * @timer_work: Timer work + * @cmd_work_data: Command work data + * @msg_work_data: Message work data + * @timer_work_data: Timer work data + * @ope_dev_intf: OPE device interface + * @cdm_reg_map: OPE CDM register map + * @clk_info: OPE clock Info for HW manager + * @dentry: Pointer to OPE debugfs directory + * @frame_dump_enable: OPE frame setting dump enablement + * @dump_req_data_enable: OPE hang dump enablement + */ +struct cam_ope_hw_mgr { + int32_t open_cnt; + uint32_t ope_ctx_cnt; + struct mutex hw_mgr_mutex; + spinlock_t hw_mgr_lock; + bool hfi_en; + int32_t iommu_hdl; + int32_t iommu_sec_hdl; + int32_t iommu_cdm_hdl; + int32_t iommu_sec_cdm_hdl; + uint32_t num_ope; + bool secure_mode; + void *ctx_bitmap; + size_t ctx_bitmap_size; + size_t ctx_bits; + struct cam_ope_ctx ctx[OPE_CTX_MAX]; + struct cam_hw_intf **devices[OPE_DEV_MAX]; + struct ope_query_cap_cmd ope_caps; + uint64_t last_callback_time; + + struct cam_req_mgr_core_workq *cmd_work; + struct cam_req_mgr_core_workq *msg_work; + struct cam_req_mgr_core_workq *timer_work; + struct ope_cmd_work_data *cmd_work_data; + struct ope_msg_work_data *msg_work_data; + struct ope_clk_work_data *timer_work_data; + struct cam_hw_intf *ope_dev_intf[OPE_DEV_MAX]; + struct cam_soc_reg_map *cdm_reg_map[OPE_DEV_MAX][OPE_BASE_MAX]; + struct cam_ope_clk_info clk_info; + struct dentry *dentry; + bool frame_dump_enable; + bool dump_req_data_enable; +}; + +/** + * struct cam_ope_buf_entry + * + * @fd: FD of cmd buffer + * @memhdl: Memhandle of cmd buffer + * @iova: IOVA address of cmd buffer + * @offset: Offset of cmd buffer + * @len: Length of cmd buffer + * @size: Size of cmd buffer + */ +struct cam_ope_buf_entry { + uint32_t fd; + uint64_t memhdl; + uint64_t iova; + uint64_t offset; + uint64_t len; + uint64_t size; +}; + +/** + * struct cam_ope_bl_entry + * + * @base: Base IOVA address of BL + * @len: Length of BL + * @arbitration: Arbitration bit + */ +struct cam_ope_bl_entry { + uint32_t base; + uint32_t len; + uint32_t arbitration; +}; + +/** + * struct cam_ope_output_info + * + * @iova: IOVA address of output buffer + * @offset: Offset of buffer + * @len: Length of buffer + */ +struct cam_ope_output_info { + uint64_t iova; + uint64_t offset; + uint64_t len; +}; + +/** + * struct cam_ope_hang_dump + * + * @num_bls: count of BLs for request + * @num_bufs: Count of buffer related to request + * @num_outputs: Count of output beffers + * @entries: Buffers info + * @bl_entries: BLs info + * @outputs: Output info + */ +struct cam_ope_hang_dump { + uint32_t num_bls; + uint32_t num_bufs; + uint64_t num_outputs; + struct cam_ope_buf_entry entries[OPE_MAX_BATCH_SIZE * OPE_MAX_CMD_BUFS]; + struct cam_ope_bl_entry bl_entries[OPE_MAX_CDM_BLS]; + struct cam_ope_output_info outputs + [OPE_MAX_BATCH_SIZE * OPE_OUT_RES_MAX]; +}; +#endif /* CAM_OPE_HW_MGR_H */ diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr_intf.h b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..9ab06daac0c7360885f8f80153fca1f73132fc47 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr_intf.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_OPE_HW_MGR_INTF_H +#define CAM_OPE_HW_MGR_INTF_H + +#include +#include +#include + +int cam_ope_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, + int *iommu_hdl); + +#endif /* CAM_OPE_HW_MGR_INTF_H */ diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/Makefile b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..a9633d63623d4904389f9760576ebf82dca7b1a7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/fw_inc +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += ope_dev.o ope_soc.o ope_core.o top/ bus_rd/ bus_wr/ diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/Makefile b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..972da01edb5df4392b57e650bdca416e7b6bc6af --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += ope_bus_rd.o diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c new file mode 100644 index 0000000000000000000000000000000000000000..033df2b6666d54ac312e4f8c1078b159bee488eb --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c @@ -0,0 +1,874 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_io_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "ope_core.h" +#include "ope_soc.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "cam_cdm_util.h" +#include "ope_hw.h" +#include "ope_dev_intf.h" +#include "ope_bus_rd.h" + +static struct ope_bus_rd *bus_rd; + +enum cam_ope_bus_unpacker_format { + UNPACKER_FMT_PLAIN_128 = 0x0, + UNPACKER_FMT_PLAIN_8 = 0x1, + UNPACKER_FMT_PLAIN_16_10BPP = 0x2, + UNPACKER_FMT_PLAIN_16_12BPP = 0x3, + UNPACKER_FMT_PLAIN_16_14BPP = 0x4, + UNPACKER_FMT_PLAIN_32_20BPP = 0x5, + UNPACKER_FMT_ARGB_16_10BPP = 0x6, + UNPACKER_FMT_ARGB_16_12BPP = 0x7, + UNPACKER_FMT_ARGB_16_14BPP = 0x8, + UNPACKER_FMT_PLAIN_32 = 0x9, + UNPACKER_FMT_PLAIN_64 = 0xA, + UNPACKER_FMT_TP_10 = 0xB, + UNPACKER_FMT_MIPI_8 = 0xC, + UNPACKER_FMT_MIPI_10 = 0xD, + UNPACKER_FMT_MIPI_12 = 0xE, + UNPACKER_FMT_MIPI_14 = 0xF, + UNPACKER_FMT_PLAIN_16_16BPP = 0x10, + UNPACKER_FMT_PLAIN_128_ODD_EVEN = 0x11, + UNPACKER_FMT_PLAIN_8_ODD_EVEN = 0x12, + UNPACKER_FMT_MAX = 0x13, +}; + +static int cam_ope_bus_rd_in_port_idx(uint32_t input_port_id) +{ + int i; + + for (i = 0; i < OPE_IN_RES_MAX; i++) + if (bus_rd->in_port_to_rm[i].input_port_id == + input_port_id) + return i; + + return -EINVAL; +} + +static int cam_ope_bus_rd_combo_idx(uint32_t format) +{ + int rc = -EINVAL; + + switch (format) { + case CAM_FORMAT_YUV422: + case CAM_FORMAT_NV21: + case CAM_FORMAT_NV12: + rc = BUS_RD_YUV; + break; + case CAM_FORMAT_MIPI_RAW_6: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_MIPI_RAW_20: + case CAM_FORMAT_QTI_RAW_8: + case CAM_FORMAT_QTI_RAW_10: + case CAM_FORMAT_QTI_RAW_12: + case CAM_FORMAT_QTI_RAW_14: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_PLAIN16_16: + case CAM_FORMAT_PLAIN32_20: + case CAM_FORMAT_PLAIN64: + case CAM_FORMAT_PLAIN128: + rc = BUS_RD_BAYER; + break; + default: + break; + } + + CAM_DBG(CAM_OPE, "Input format = %u rc = %d", + format, rc); + return rc; +} + +static int cam_ope_bus_is_rm_enabled( + struct cam_ope_request *ope_request, + uint32_t batch_idx, + uint32_t rm_id) +{ + int i, k; + int32_t combo_idx; + struct ope_io_buf *io_buf; + struct ope_bus_in_port_to_rm *in_port_to_rm; + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch idx: %d", batch_idx); + return -EINVAL; + } + + for (i = 0; i < ope_request->num_io_bufs[batch_idx]; i++) { + io_buf = ope_request->io_buf[batch_idx][i]; + if (io_buf->direction != CAM_BUF_INPUT) + continue; + in_port_to_rm = + &bus_rd->in_port_to_rm[io_buf->resource_type - 1]; + combo_idx = cam_ope_bus_rd_combo_idx(io_buf->format); + if (combo_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid combo_idx"); + return -EINVAL; + } + for (k = 0; k < io_buf->num_planes; k++) { + if (rm_id == + in_port_to_rm->rm_port_id[combo_idx][k]) + return true; + } + } + + return false; +} + +static uint32_t *cam_ope_bus_rd_update(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t *kmd_buf, int batch_idx, + int io_idx, struct cam_ope_dev_prepare_req *prepare, + int32_t *num_stripes) +{ + int k, l, m; + uint32_t idx; + int32_t combo_idx; + uint32_t req_idx, count = 0, temp; + uint32_t temp_reg[128] = {0}; + uint32_t rm_id, header_size; + uint32_t rsc_type; + struct cam_hw_prepare_update_args *prepare_args; + struct cam_ope_ctx *ctx_data; + struct cam_ope_request *ope_request; + struct ope_io_buf *io_buf; + struct ope_stripe_io *stripe_io; + struct ope_bus_rd_ctx *bus_rd_ctx; + struct cam_ope_bus_rd_reg *rd_reg; + struct cam_ope_bus_rd_client_reg *rd_reg_client; + struct cam_ope_bus_rd_reg_val *rd_reg_val; + struct cam_ope_bus_rd_client_reg_val *rd_res_val_client; + struct ope_bus_in_port_to_rm *in_port_to_rm; + struct ope_bus_rd_io_port_cdm_info *io_port_cdm; + struct cam_cdm_utils_ops *cdm_ops; + struct ope_bus_rd_io_port_info *io_port_info; + + + if (ctx_id < 0 || !prepare) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, prepare); + return NULL; + } + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch idx: %d", batch_idx); + return NULL; + } + + if (io_idx >= OPE_MAX_IO_BUFS) { + CAM_ERR(CAM_OPE, "Invalid IO idx: %d", io_idx); + return NULL; + } + + prepare_args = prepare->prepare_args; + ctx_data = prepare->ctx_data; + req_idx = prepare->req_idx; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + ope_request = ctx_data->req_list[req_idx]; + CAM_DBG(CAM_OPE, "req_idx = %d req_id = %lld KMDbuf %x offset %d", + req_idx, ope_request->request_id, + kmd_buf, prepare->kmd_buf_offset); + bus_rd_ctx = bus_rd->bus_rd_ctx[ctx_id]; + io_port_info = &bus_rd_ctx->io_port_info; + rd_reg = ope_hw_info->bus_rd_reg; + rd_reg_val = ope_hw_info->bus_rd_reg_val; + io_buf = ope_request->io_buf[batch_idx][io_idx]; + + CAM_DBG(CAM_OPE, + "req_idx = %d req_id = %lld KMDbuf 0x%x offset %d rsc %d", + req_idx, ope_request->request_id, + kmd_buf, prepare->kmd_buf_offset, + io_buf->resource_type); + CAM_DBG(CAM_OPE, "batch:%d iobuf:%d direction:%d", + batch_idx, io_idx, io_buf->direction); + io_port_cdm = + &bus_rd_ctx->io_port_cdm_batch.io_port_cdm[batch_idx]; + in_port_to_rm = + &bus_rd->in_port_to_rm[io_buf->resource_type - 1]; + combo_idx = cam_ope_bus_rd_combo_idx(io_buf->format); + if (combo_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid combo_idx"); + return NULL; + } + + for (k = 0; k < io_buf->num_planes; k++) { + for (l = 0; l < io_buf->num_stripes[k]; l++) { + *num_stripes = io_buf->num_stripes[k]; + stripe_io = &io_buf->s_io[k][l]; + rsc_type = io_buf->resource_type - 1; + /* frame level info */ + /* stripe level info */ + rm_id = in_port_to_rm->rm_port_id[combo_idx][k]; + rd_reg_client = &rd_reg->rd_clients[rm_id]; + rd_res_val_client = &rd_reg_val->rd_clients[rm_id]; + + /* security cfg */ + temp_reg[count++] = rd_reg->offset + + rd_reg->security_cfg; + temp_reg[count++] = + ctx_data->ope_acquire.secure_mode; + + /* enable client */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->core_cfg; + temp_reg[count++] = 1; + + /* ccif meta data */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->ccif_meta_data; + temp = 0; + temp |= stripe_io->s_location & + rd_res_val_client->stripe_location_mask; + temp |= (io_buf->pix_pattern & + rd_res_val_client->pix_pattern_mask) << + rd_res_val_client->pix_pattern_shift; + temp_reg[count++] = temp; + + /* Address of the Image */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->img_addr; + temp_reg[count++] = stripe_io->iova_addr; + + /* Buffer size */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->img_cfg; + temp = 0; + temp = stripe_io->height; + temp |= + (stripe_io->width & + rd_res_val_client->img_width_mask) << + rd_res_val_client->img_width_shift; + temp_reg[count++] = temp; + + /* stride */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->stride; + temp_reg[count++] = stripe_io->stride; + + /* + * In case of NV12, change the unpacker format of + * chroma plane to odd even byte swapped format. + */ + if (k == 1 && stripe_io->format == CAM_FORMAT_NV12) + stripe_io->unpack_format = + UNPACKER_FMT_PLAIN_8_ODD_EVEN; + + /* Unpack cfg : Mode and alignment */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->unpack_cfg; + temp = 0; + temp |= (stripe_io->unpack_format & + rd_res_val_client->mode_mask) << + rd_res_val_client->mode_shift; + temp |= (stripe_io->alignment & + rd_res_val_client->alignment_mask) << + rd_res_val_client->alignment_shift; + temp_reg[count++] = temp; + + /* latency buffer allocation */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->latency_buf_allocation; + temp_reg[count++] = io_port_info->latency_buf_size; + + header_size = cdm_ops->cdm_get_cmd_header_size( + CAM_CDM_CMD_REG_RANDOM); + idx = io_port_cdm->num_s_cmd_bufs[l]; + io_port_cdm->s_cdm_info[l][idx].len = sizeof(temp) * + (count + header_size); + io_port_cdm->s_cdm_info[l][idx].offset = + prepare->kmd_buf_offset; + io_port_cdm->s_cdm_info[l][idx].addr = kmd_buf; + io_port_cdm->num_s_cmd_bufs[l]++; + + kmd_buf = cdm_ops->cdm_write_regrandom( + kmd_buf, count/2, temp_reg); + prepare->kmd_buf_offset += ((count + header_size) * + sizeof(temp)); + CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", + batch_idx, io_idx, k, l); + for (m = 0; m < count; m += 2) + CAM_DBG(CAM_OPE, "%d: off: 0x%x val: 0x%x", + m, temp_reg[m], temp_reg[m+1]); + CAM_DBG(CAM_OPE, "kmd_buf:%x offset:%d", + kmd_buf, prepare->kmd_buf_offset); + CAM_DBG(CAM_OPE, "RD cmdbufs:%d off:%d len %d", + io_port_cdm->num_s_cmd_bufs[l], + io_port_cdm->s_cdm_info[l][idx].offset, + io_port_cdm->s_cdm_info[l][idx].len); + count = 0; + } + } + + return kmd_buf; +} + +static uint32_t *cam_ope_bus_rm_disable(struct ope_hw *ope_hw_info, + int32_t ctx_id, struct cam_ope_dev_prepare_req *prepare, + int batch_idx, int rm_idx, + uint32_t *kmd_buf, uint32_t num_stripes) +{ + int l; + uint32_t idx; + uint32_t req_idx; + uint32_t temp_reg[128]; + uint32_t count = 0; + uint32_t temp = 0; + uint32_t header_size; + struct cam_ope_ctx *ctx_data; + struct ope_bus_rd_ctx *bus_rd_ctx; + struct cam_ope_bus_rd_reg *rd_reg; + struct cam_ope_bus_rd_client_reg *rd_reg_client; + struct ope_bus_rd_io_port_cdm_batch *io_port_cdm_batch; + struct ope_bus_rd_io_port_cdm_info *io_port_cdm; + struct cam_cdm_utils_ops *cdm_ops; + + + if (ctx_id < 0 || !prepare) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, prepare); + return NULL; + } + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch idx: %d", batch_idx); + return NULL; + } + + if (rm_idx >= MAX_RD_CLIENTS) { + CAM_ERR(CAM_OPE, "Invalid read client: %d", rm_idx); + return NULL; + } + + ctx_data = prepare->ctx_data; + req_idx = prepare->req_idx; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + bus_rd_ctx = bus_rd->bus_rd_ctx[ctx_id]; + io_port_cdm_batch = &bus_rd_ctx->io_port_cdm_batch; + rd_reg = ope_hw_info->bus_rd_reg; + + CAM_DBG(CAM_OPE, + "kmd_buf = 0x%x req_idx = %d offset = %d rd_idx %d b %d", + kmd_buf, req_idx, prepare->kmd_buf_offset, rm_idx, batch_idx); + + io_port_cdm = + &bus_rd_ctx->io_port_cdm_batch.io_port_cdm[batch_idx]; + + for (l = 0; l < num_stripes; l++) { + /* stripe level info */ + rd_reg_client = &rd_reg->rd_clients[rm_idx]; + + /* Core cfg: enable, Mode */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->core_cfg; + temp_reg[count++] = 0; + + header_size = cdm_ops->cdm_get_cmd_header_size( + CAM_CDM_CMD_REG_RANDOM); + idx = io_port_cdm->num_s_cmd_bufs[l]; + io_port_cdm->s_cdm_info[l][idx].len = + sizeof(temp) * (count + header_size); + io_port_cdm->s_cdm_info[l][idx].offset = + prepare->kmd_buf_offset; + io_port_cdm->s_cdm_info[l][idx].addr = kmd_buf; + io_port_cdm->num_s_cmd_bufs[l]++; + + kmd_buf = cdm_ops->cdm_write_regrandom( + kmd_buf, count/2, temp_reg); + prepare->kmd_buf_offset += ((count + header_size) * + sizeof(temp)); + + CAM_DBG(CAM_OPE, "RD cmd bufs = %d", + io_port_cdm->num_s_cmd_bufs[l]); + CAM_DBG(CAM_OPE, "stripe %d off:%d len:%d", + l, io_port_cdm->s_cdm_info[l][idx].offset, + io_port_cdm->s_cdm_info[l][idx].len); + count = 0; + } + + prepare->rd_cdm_batch = &bus_rd_ctx->io_port_cdm_batch; + + return kmd_buf; +} + +static int cam_ope_bus_rd_prepare(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + int i, j; + int32_t combo_idx; + uint32_t req_idx, count = 0, temp; + uint32_t temp_reg[32] = {0}; + uint32_t header_size; + uint32_t *kmd_buf; + int is_rm_enabled; + struct cam_ope_dev_prepare_req *prepare; + struct cam_ope_ctx *ctx_data; + struct cam_ope_request *ope_request; + struct ope_io_buf *io_buf; + struct ope_bus_rd_ctx *bus_rd_ctx; + struct cam_ope_bus_rd_reg *rd_reg; + struct cam_ope_bus_rd_reg_val *rd_reg_val; + struct ope_bus_rd_io_port_cdm_batch *io_port_cdm_batch; + struct ope_bus_rd_io_port_cdm_info *io_port_cdm = NULL; + struct cam_cdm_utils_ops *cdm_ops; + int32_t num_stripes = 0; + + if (ctx_id < 0 || !data) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, data); + return -EINVAL; + } + prepare = data; + + ctx_data = prepare->ctx_data; + req_idx = prepare->req_idx; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + ope_request = ctx_data->req_list[req_idx]; + kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + + prepare->kmd_buf_offset; + CAM_DBG(CAM_OPE, "req_idx = %d req_id = %lld", + req_idx, ope_request->request_id); + CAM_DBG(CAM_OPE, "KMD buf and offset = %x %d", + kmd_buf, prepare->kmd_buf_offset); + bus_rd_ctx = bus_rd->bus_rd_ctx[ctx_id]; + io_port_cdm_batch = + &bus_rd_ctx->io_port_cdm_batch; + memset(io_port_cdm_batch, 0, + sizeof(struct ope_bus_rd_io_port_cdm_batch)); + rd_reg = ope_hw_info->bus_rd_reg; + rd_reg_val = ope_hw_info->bus_rd_reg_val; + + for (i = 0; i < ope_request->num_batch; i++) { + for (j = 0; j < ope_request->num_io_bufs[i]; j++) { + io_buf = ope_request->io_buf[i][j]; + if (io_buf->direction != CAM_BUF_INPUT) + continue; + + CAM_DBG(CAM_OPE, "batch:%d iobuf:%d direction:%d", + i, j, io_buf->direction); + io_port_cdm = + &bus_rd_ctx->io_port_cdm_batch.io_port_cdm[i]; + + combo_idx = cam_ope_bus_rd_combo_idx(io_buf->format); + if (combo_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid combo_idx"); + return combo_idx; + } + + kmd_buf = cam_ope_bus_rd_update(ope_hw_info, + ctx_id, kmd_buf, i, j, prepare, + &num_stripes); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + } + } + + if (!io_port_cdm) { + rc = -EINVAL; + goto end; + } + + /* Disable RMs which are not enabled */ + for (i = 0; i < ope_request->num_batch; i++) { + for (j = 0; j < rd_reg_val->num_clients; j++) { + is_rm_enabled = cam_ope_bus_is_rm_enabled( + ope_request, i, j); + if (is_rm_enabled < 0) { + rc = -EINVAL; + goto end; + } + if (is_rm_enabled) + continue; + + kmd_buf = cam_ope_bus_rm_disable(ope_hw_info, + ctx_id, prepare, i, j, + kmd_buf, num_stripes); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + } + } + + /* Go command */ + count = 0; + temp_reg[count++] = rd_reg->offset + + rd_reg->input_if_cmd; + temp = 0; + temp |= rd_reg_val->go_cmd; + temp_reg[count++] = temp; + + header_size = + cdm_ops->cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM); + for (i = 0; i < ope_request->num_batch; i++) { + io_port_cdm = + &bus_rd_ctx->io_port_cdm_batch.io_port_cdm[i]; + io_port_cdm->go_cmd_addr = kmd_buf; + io_port_cdm->go_cmd_len = + sizeof(temp) * (count + header_size); + io_port_cdm->go_cmd_offset = + prepare->kmd_buf_offset; + } + kmd_buf = cdm_ops->cdm_write_regrandom( + kmd_buf, count/2, temp_reg); + prepare->kmd_buf_offset += + ((count + header_size) * sizeof(temp)); + CAM_DBG(CAM_OPE, "kmd_buf:%x,offset:%d", + kmd_buf, prepare->kmd_buf_offset); + CAM_DBG(CAM_OPE, "t_reg:%xcount: %d size:%d", + temp_reg, count, header_size); + prepare->rd_cdm_batch = &bus_rd_ctx->io_port_cdm_batch; + +end: + return rc; +} + +static int cam_ope_bus_rd_release(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + + if (ctx_id < 0 || ctx_id >= OPE_CTX_MAX) { + CAM_ERR(CAM_OPE, "Invalid data: %d", ctx_id); + return -EINVAL; + } + + vfree(bus_rd->bus_rd_ctx[ctx_id]); + bus_rd->bus_rd_ctx[ctx_id] = NULL; + + return rc; +} + +static int cam_ope_bus_rd_acquire(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0, i; + struct ope_acquire_dev_info *in_acquire; + struct ope_bus_rd_ctx *bus_rd_ctx; + struct ope_bus_in_port_to_rm *in_port_to_rm; + struct cam_ope_bus_rd_reg_val *bus_rd_reg_val; + int combo_idx; + int in_port_idx; + + + if (ctx_id < 0 || !data || !ope_hw_info || ctx_id >= OPE_CTX_MAX) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x %x", + ctx_id, data, ope_hw_info); + return -EINVAL; + } + + bus_rd->bus_rd_ctx[ctx_id] = vzalloc(sizeof(struct ope_bus_rd_ctx)); + if (!bus_rd->bus_rd_ctx[ctx_id]) { + CAM_ERR(CAM_OPE, "Out of memory"); + return -ENOMEM; + } + + bus_rd->bus_rd_ctx[ctx_id]->ope_acquire = data; + in_acquire = data; + bus_rd_ctx = bus_rd->bus_rd_ctx[ctx_id]; + bus_rd_ctx->num_in_ports = in_acquire->num_in_res; + bus_rd_ctx->security_flag = in_acquire->secure_mode; + bus_rd_reg_val = ope_hw_info->bus_rd_reg_val; + + for (i = 0; i < in_acquire->num_in_res; i++) { + if (!in_acquire->in_res[i].width) + continue; + + CAM_DBG(CAM_OPE, "i = %d format = %u width = %x height = %x", + i, in_acquire->in_res[i].format, + in_acquire->in_res[i].width, + in_acquire->in_res[i].height); + CAM_DBG(CAM_OPE, "pix_pattern:%u alignment:%u unpack_format:%u", + in_acquire->in_res[i].pixel_pattern, + in_acquire->in_res[i].alignment, + in_acquire->in_res[i].unpacker_format); + CAM_DBG(CAM_OPE, "max_stripe = %u fps = %u", + in_acquire->in_res[i].max_stripe_size, + in_acquire->in_res[i].fps); + + in_port_idx = cam_ope_bus_rd_in_port_idx(i + 1); + if (in_port_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid in_port_idx: %d", i + 1); + rc = -EINVAL; + goto end; + } + + in_port_to_rm = &bus_rd->in_port_to_rm[in_port_idx]; + combo_idx = cam_ope_bus_rd_combo_idx( + in_acquire->in_res[i].format); + if (combo_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid format: %d", + in_acquire->in_res[i].format); + rc = -EINVAL; + goto end; + } + + if (!in_port_to_rm->num_rm[combo_idx]) { + CAM_ERR(CAM_OPE, "Invalid format for Input port"); + rc = -EINVAL; + goto end; + } + + bus_rd_ctx->io_port_info.input_port_id[i] = + in_acquire->in_res[i].res_id; + bus_rd_ctx->io_port_info.input_format_type[i] = + in_acquire->in_res[i].format; + if (in_acquire->in_res[i].pixel_pattern > + PIXEL_PATTERN_CRYCBY) { + CAM_ERR(CAM_OPE, "Invalid pix pattern = %u", + in_acquire->in_res[i].pixel_pattern); + rc = -EINVAL; + goto end; + } + + bus_rd_ctx->io_port_info.pixel_pattern[i] = + in_acquire->in_res[i].pixel_pattern; + bus_rd_ctx->io_port_info.latency_buf_size = + bus_rd_reg_val->latency_buf_size; + + CAM_DBG(CAM_OPE, "i:%d port_id = %u format %u pix_pattern = %u", + i, bus_rd_ctx->io_port_info.input_port_id[i], + bus_rd_ctx->io_port_info.input_format_type[i], + bus_rd_ctx->io_port_info.pixel_pattern[i]); + CAM_DBG(CAM_OPE, "latency_buf_size = %u", + bus_rd_ctx->io_port_info.latency_buf_size); + } + +end: + return rc; +} + +static int cam_ope_bus_rd_init(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + struct cam_ope_bus_rd_reg_val *bus_rd_reg_val; + struct cam_ope_bus_rd_reg *bus_rd_reg; + struct cam_ope_dev_init *dev_init = data; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + bus_rd_reg_val = ope_hw_info->bus_rd_reg_val; + bus_rd_reg = ope_hw_info->bus_rd_reg; + bus_rd_reg->base = dev_init->core_info->ope_hw_info->ope_bus_rd_base; + + /* OPE SW RESET */ + init_completion(&bus_rd->reset_complete); + + /* enable interrupt mask */ + cam_io_w_mb(bus_rd_reg_val->irq_mask, + ope_hw_info->bus_rd_reg->base + bus_rd_reg->irq_mask); + + cam_io_w_mb(bus_rd_reg_val->sw_reset, + ope_hw_info->bus_rd_reg->base + bus_rd_reg->sw_reset); + + rc = wait_for_completion_timeout( + &bus_rd->reset_complete, msecs_to_jiffies(30000)); + + if (!rc || rc < 0) { + CAM_ERR(CAM_OPE, "reset error result = %d", rc); + if (!rc) + rc = -ETIMEDOUT; + } else { + rc = 0; + } + + cam_io_w_mb(bus_rd_reg_val->irq_mask, + ope_hw_info->bus_rd_reg->base + bus_rd_reg->irq_mask); + + return rc; +} + +static int cam_ope_bus_rd_probe(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0, i, j, combo_idx, k; + struct cam_ope_bus_rd_reg_val *bus_rd_reg_val; + struct cam_ope_bus_rd_reg *bus_rd_reg; + struct ope_bus_in_port_to_rm *in_port_to_rm; + uint32_t input_port_idx; + uint32_t rm_idx; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + bus_rd = kzalloc(sizeof(struct ope_bus_rd), GFP_KERNEL); + if (!bus_rd) { + CAM_ERR(CAM_OPE, "Out of memory"); + return -ENOMEM; + } + bus_rd->ope_hw_info = ope_hw_info; + bus_rd_reg_val = ope_hw_info->bus_rd_reg_val; + bus_rd_reg = ope_hw_info->bus_rd_reg; + + for (i = 0; i < bus_rd_reg_val->num_clients; i++) { + input_port_idx = + bus_rd_reg_val->rd_clients[i].input_port_id - 1; + in_port_to_rm = &bus_rd->in_port_to_rm[input_port_idx]; + if (bus_rd_reg_val->rd_clients[i].format_type & + BUS_RD_COMBO_BAYER_MASK) { + combo_idx = BUS_RD_BAYER; + rm_idx = in_port_to_rm->num_rm[combo_idx]; + in_port_to_rm->input_port_id = + bus_rd_reg_val->rd_clients[i].input_port_id; + in_port_to_rm->rm_port_id[combo_idx][rm_idx] = + bus_rd_reg_val->rd_clients[i].rm_port_id; + if (!in_port_to_rm->num_rm[combo_idx]) + in_port_to_rm->num_combos++; + in_port_to_rm->num_rm[combo_idx]++; + } + if (bus_rd_reg_val->rd_clients[i].format_type & + BUS_RD_COMBO_YUV_MASK) { + combo_idx = BUS_RD_YUV; + rm_idx = in_port_to_rm->num_rm[combo_idx]; + in_port_to_rm->input_port_id = + bus_rd_reg_val->rd_clients[i].input_port_id; + in_port_to_rm->rm_port_id[combo_idx][rm_idx] = + bus_rd_reg_val->rd_clients[i].rm_port_id; + if (!in_port_to_rm->num_rm[combo_idx]) + in_port_to_rm->num_combos++; + in_port_to_rm->num_rm[combo_idx]++; + } + } + + for (i = 0; i < OPE_IN_RES_MAX; i++) { + in_port_to_rm = &bus_rd->in_port_to_rm[i]; + CAM_DBG(CAM_OPE, "input port id = %d num_combos = %d", + in_port_to_rm->input_port_id, + in_port_to_rm->num_combos); + for (j = 0; j < in_port_to_rm->num_combos; j++) { + CAM_DBG(CAM_OPE, "combo idx = %d num_rms = %d", + j, in_port_to_rm->num_rm[j]); + for (k = 0; k < in_port_to_rm->num_rm[j]; k++) { + CAM_DBG(CAM_OPE, "rm port id = %d", + in_port_to_rm->rm_port_id[j][k]); + } + } + } + + return rc; +} + +static int cam_ope_bus_rd_isr(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + uint32_t irq_status; + struct cam_ope_bus_rd_reg *bus_rd_reg; + struct cam_ope_bus_rd_reg_val *bus_rd_reg_val; + struct cam_ope_irq_data *irq_data = data; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + bus_rd_reg = ope_hw_info->bus_rd_reg; + bus_rd_reg_val = ope_hw_info->bus_rd_reg_val; + + /* Read and Clear Top Interrupt status */ + irq_status = cam_io_r_mb(bus_rd_reg->base + bus_rd_reg->irq_status); + cam_io_w_mb(irq_status, + bus_rd_reg->base + bus_rd_reg->irq_clear); + + cam_io_w_mb(bus_rd_reg_val->irq_set_clear, + bus_rd_reg->base + bus_rd_reg->irq_cmd); + + if (irq_status & bus_rd_reg_val->rst_done) { + complete(&bus_rd->reset_complete); + CAM_DBG(CAM_OPE, "ope bus rd reset done"); + } + + if ((irq_status & bus_rd_reg_val->violation) == + bus_rd_reg_val->violation) { + irq_data->error = 1; + CAM_ERR(CAM_OPE, "ope bus rd CCIF vioalation"); + } + + return rc; +} + +int cam_ope_bus_rd_process(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t cmd_id, void *data) +{ + int rc = -EINVAL; + + switch (cmd_id) { + case OPE_HW_PROBE: + CAM_DBG(CAM_OPE, "OPE_HW_PROBE: E"); + rc = cam_ope_bus_rd_probe(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_PROBE: X"); + break; + case OPE_HW_INIT: + CAM_DBG(CAM_OPE, "OPE_HW_INIT: E"); + rc = cam_ope_bus_rd_init(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_INIT: X"); + break; + case OPE_HW_ACQUIRE: + CAM_DBG(CAM_OPE, "OPE_HW_ACQUIRE: E"); + rc = cam_ope_bus_rd_acquire(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_ACQUIRE: X"); + break; + case OPE_HW_RELEASE: + CAM_DBG(CAM_OPE, "OPE_HW_RELEASE: E"); + rc = cam_ope_bus_rd_release(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_RELEASE: X"); + break; + case OPE_HW_PREPARE: + CAM_DBG(CAM_OPE, "OPE_HW_PREPARE: E"); + rc = cam_ope_bus_rd_prepare(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_PREPARE: X"); + break; + case OPE_HW_ISR: + rc = cam_ope_bus_rd_isr(ope_hw_info, 0, data); + break; + case OPE_HW_DEINIT: + case OPE_HW_START: + case OPE_HW_STOP: + case OPE_HW_FLUSH: + case OPE_HW_CLK_UPDATE: + case OPE_HW_BW_UPDATE: + case OPE_HW_RESET: + case OPE_HW_SET_IRQ_CB: + rc = 0; + CAM_DBG(CAM_OPE, "Unhandled cmds: %d", cmd_id); + break; + default: + CAM_ERR(CAM_OPE, "Unsupported cmd: %d", cmd_id); + break; + } + + return rc; +} + diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.h b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.h new file mode 100644 index 0000000000000000000000000000000000000000..b461374c2a637e997c2e6b55197f7f0a091d1fb0 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef OPE_BUS_RD_H +#define OPE_BUS_RD_H + +#include +#include +#include +#include "ope_hw.h" +#include "cam_hw_mgr_intf.h" +#include "cam_hw_intf.h" +#include "cam_soc_util.h" +#include "cam_context.h" +#include "cam_ope_context.h" +#include "cam_ope_hw_mgr.h" + + +/** + * struct ope_bus_rd_cdm_info + * + * @offset: Offset + * @addr: Address + * @len: Length + */ +struct ope_bus_rd_cdm_info { + uint32_t offset; + uint32_t *addr; + uint32_t len; +}; + +/** + * struct ope_bus_rd_io_port_cdm_info + * + * @num_frames_cmds: Number of frame commands + * @f_cdm_info: Frame cdm info + * @num_stripes: Number of stripes + * @num_s_cmd_bufs: Number of stripe commands + * @s_cdm_info: Stripe cdm info + * @go_cmd_addr: GO command address + * @go_cmd_len: GO command length + */ +struct ope_bus_rd_io_port_cdm_info { + uint32_t num_frames_cmds; + struct ope_bus_rd_cdm_info f_cdm_info[MAX_RD_CLIENTS]; + uint32_t num_stripes; + uint32_t num_s_cmd_bufs[OPE_MAX_STRIPES]; + struct ope_bus_rd_cdm_info s_cdm_info[OPE_MAX_STRIPES][MAX_RD_CLIENTS]; + uint32_t go_cmd_offset; + uint32_t *go_cmd_addr; + uint32_t go_cmd_len; +}; + +/** + * struct ope_bus_rd_io_port_cdm_batch + * + * num_batch: Number of batches + * io_port_cdm: CDM IO Port Info + */ +struct ope_bus_rd_io_port_cdm_batch { + uint32_t num_batch; + struct ope_bus_rd_io_port_cdm_info io_port_cdm[OPE_MAX_BATCH_SIZE]; +}; + +/** + * struct ope_bus_rd_rm + * + * @rm_port_id: RM port ID + * @format_type: Format type + */ +struct ope_bus_rd_rm { + uint32_t rm_port_id; + uint32_t format_type; +}; + +/** + * struct ope_bus_in_port_to_rm + * + * @input_port_id: Intput port ID + * @num_combos: Number of combos + * @num_rm: Number of RMs + * @rm_port_id: RM port Id + */ +struct ope_bus_in_port_to_rm { + uint32_t input_port_id; + uint32_t num_combos; + uint32_t num_rm[BUS_RD_COMBO_MAX]; + uint32_t rm_port_id[BUS_RD_COMBO_MAX][MAX_RD_CLIENTS]; +}; + +/** + * struct ope_bus_rd_io_port_info + * + * @pixel_pattern: Pixel pattern + * @input_port_id: Port Id + * @input_format_type: Format type + * @latency_buf_size: Latency buffer size + */ +struct ope_bus_rd_io_port_info { + uint32_t pixel_pattern[OPE_IN_RES_MAX]; + uint32_t input_port_id[OPE_IN_RES_MAX]; + uint32_t input_format_type[OPE_IN_RES_MAX]; + uint32_t latency_buf_size; +}; + +/** + * struct ope_bus_rd_ctx + * + * @ope_acquire: OPE acquire structure + * @security_flag: security flag + * @num_in_ports: Number of in ports + * @io_port_info: IO port info + * @io_port_cdm_batch: IO port cdm info + */ +struct ope_bus_rd_ctx { + struct ope_acquire_dev_info *ope_acquire; + bool security_flag; + uint32_t num_in_ports; + struct ope_bus_rd_io_port_info io_port_info; + struct ope_bus_rd_io_port_cdm_batch io_port_cdm_batch; +}; + +/** + * struct ope_bus_rd + * + * @ope_hw_info: OPE hardware info + * @in_port_to_rm: IO port to RM mapping + * @bus_rd_ctx: RM context + */ +struct ope_bus_rd { + struct ope_hw *ope_hw_info; + struct ope_bus_in_port_to_rm in_port_to_rm[OPE_IN_RES_MAX]; + struct ope_bus_rd_ctx *bus_rd_ctx[OPE_CTX_MAX]; + struct completion reset_complete; +}; +#endif /* OPE_BUS_RD_H */ + diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/Makefile b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..751711147de0c3683c563a41113f43707618f9b5 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += ope_bus_wr.o diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c new file mode 100644 index 0000000000000000000000000000000000000000..df5cb89b1eea0308afcedb4cfb2bd28a9db92833 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c @@ -0,0 +1,802 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_io_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "ope_core.h" +#include "ope_soc.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "ope_hw.h" +#include "ope_dev_intf.h" +#include "ope_bus_wr.h" +#include "cam_cdm_util.h" + +static struct ope_bus_wr *wr_info; + +enum cam_ope_bus_packer_format { + PACKER_FMT_PLAIN_128 = 0x0, + PACKER_FMT_PLAIN_8 = 0x1, + PACKER_FMT_PLAIN_8_ODD_EVEN = 0x2, + PACKER_FMT_PLAIN_8_LSB_MSB_10 = 0x3, + PACKER_FMT_PLAIN_8_LSB_MSB_10_ODD_EVEN = 0x4, + PACKER_FMT_PLAIN_16_10BPP = 0x5, + PACKER_FMT_PLAIN_16_12BPP = 0x6, + PACKER_FMT_PLAIN_16_14BPP = 0x7, + PACKER_FMT_PLAIN_16_16BPP = 0x8, + PACKER_FMT_PLAIN_32 = 0x9, + PACKER_FMT_PLAIN_64 = 0xA, + PACKER_FMT_TP_10 = 0xB, + PACKER_FMT_MIPI_10 = 0xC, + PACKER_FMT_MIPI_12 = 0xD, + PACKER_FMT_MAX = 0xE, +}; + +static int cam_ope_bus_en_port_idx( + struct cam_ope_request *ope_request, + uint32_t batch_idx, + uint32_t output_port_id) +{ + int i; + struct ope_io_buf *io_buf; + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch idx: %d", batch_idx); + return -EINVAL; + } + + for (i = 0; i < ope_request->num_io_bufs[batch_idx]; i++) { + io_buf = ope_request->io_buf[batch_idx][i]; + if (io_buf->direction != CAM_BUF_OUTPUT) + continue; + if (io_buf->resource_type == output_port_id) + return i; + } + + return -EINVAL; +} +static int cam_ope_bus_wr_out_port_idx(uint32_t output_port_id) +{ + int i; + + for (i = 0; i < OPE_OUT_RES_MAX; i++) + if (wr_info->out_port_to_wm[i].output_port_id == output_port_id) + return i; + + return -EINVAL; +} + + +static int cam_ope_bus_wr_subsample( + struct cam_ope_ctx *ctx_data, + struct ope_hw *ope_hw_info, + struct cam_ope_bus_wr_client_reg *wr_reg_client, + struct ope_io_buf *io_buf, + uint32_t *temp_reg, uint32_t count, + int plane_idx, int stripe_idx) +{ + int k, l; + struct cam_ope_bus_wr_reg *wr_reg; + struct cam_ope_bus_wr_reg_val *wr_reg_val; + + wr_reg = ope_hw_info->bus_wr_reg; + wr_reg_val = ope_hw_info->bus_wr_reg_val; + + if (plane_idx >= OPE_MAX_PLANES) { + CAM_ERR(CAM_OPE, "Invalid plane idx: %d", plane_idx); + return count; + } + k = plane_idx; + l = stripe_idx; + + /* subsample period and pattern */ + if ((ctx_data->ope_acquire.dev_type == + OPE_DEV_TYPE_OPE_RT) && l == 0) { + temp_reg[count++] = wr_reg->offset + + wr_reg_client->subsample_period; + temp_reg[count++] = io_buf->num_stripes[k]; + + temp_reg[count++] = wr_reg->offset + + wr_reg_client->subsample_pattern; + temp_reg[count++] = 1 << + (io_buf->num_stripes[k] - 1); + } else if ((ctx_data->ope_acquire.dev_type == + OPE_DEV_TYPE_OPE_NRT) && + ((l % + ctx_data->ope_acquire.nrt_stripes_for_arb) == + 0)) { + if (io_buf->num_stripes[k] >= + (l + + ctx_data->ope_acquire.nrt_stripes_for_arb)){ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->subsample_period; + temp_reg[count++] = + ctx_data->ope_acquire.nrt_stripes_for_arb; + + temp_reg[count++] = wr_reg->offset + + wr_reg_client->subsample_pattern; + temp_reg[count++] = 1 << + (ctx_data->ope_acquire.nrt_stripes_for_arb - + 1); + } else { + temp_reg[count++] = wr_reg->offset + + wr_reg_client->subsample_period; + temp_reg[count++] = io_buf->num_stripes[k] - l; + + /* subsample pattern */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->subsample_pattern; + temp_reg[count++] = 1 << (io_buf->num_stripes[k] - + l - 1); + } + } + return count; +} + +static int cam_ope_bus_wr_release(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + + if (ctx_id < 0 || ctx_id >= OPE_CTX_MAX) { + CAM_ERR(CAM_OPE, "Invalid data: %d", ctx_id); + return -EINVAL; + } + + vfree(wr_info->bus_wr_ctx[ctx_id]); + wr_info->bus_wr_ctx[ctx_id] = NULL; + + return rc; +} + +static uint32_t *cam_ope_bus_wr_update(struct ope_hw *ope_hw_info, + int32_t ctx_id, struct cam_ope_dev_prepare_req *prepare, + int batch_idx, int io_idx, + uint32_t *kmd_buf, uint32_t *num_stripes) +{ + int k, l, m, out_port_idx; + uint32_t idx; + uint32_t num_wm_ports; + uint32_t comb_idx; + uint32_t req_idx; + uint32_t temp_reg[128]; + uint32_t count = 0; + uint32_t temp = 0; + uint32_t wm_port_id; + uint32_t header_size; + struct cam_hw_prepare_update_args *prepare_args; + struct cam_ope_ctx *ctx_data; + struct cam_ope_request *ope_request; + struct ope_io_buf *io_buf; + struct ope_stripe_io *stripe_io; + struct ope_bus_wr_ctx *bus_wr_ctx; + struct cam_ope_bus_wr_reg *wr_reg; + struct cam_ope_bus_wr_client_reg *wr_reg_client; + struct cam_ope_bus_wr_reg_val *wr_reg_val; + struct cam_ope_bus_wr_client_reg_val *wr_res_val_client; + struct ope_bus_out_port_to_wm *out_port_to_wm; + struct ope_bus_wr_io_port_cdm_batch *io_port_cdm_batch; + struct ope_bus_wr_io_port_cdm_info *io_port_cdm; + struct cam_cdm_utils_ops *cdm_ops; + + + if (ctx_id < 0 || !prepare) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, prepare); + return NULL; + } + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch idx: %d", batch_idx); + return NULL; + } + + if (io_idx >= OPE_MAX_IO_BUFS) { + CAM_ERR(CAM_OPE, "Invalid IO idx: %d", io_idx); + return NULL; + } + + prepare_args = prepare->prepare_args; + ctx_data = prepare->ctx_data; + req_idx = prepare->req_idx; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + ope_request = ctx_data->req_list[req_idx]; + bus_wr_ctx = wr_info->bus_wr_ctx[ctx_id]; + io_port_cdm_batch = &bus_wr_ctx->io_port_cdm_batch; + wr_reg = ope_hw_info->bus_wr_reg; + wr_reg_val = ope_hw_info->bus_wr_reg_val; + + CAM_DBG(CAM_OPE, "kmd_buf = %x req_idx = %d req_id = %lld offset = %d", + kmd_buf, req_idx, ope_request->request_id, + prepare->kmd_buf_offset); + + io_buf = ope_request->io_buf[batch_idx][io_idx]; + CAM_DBG(CAM_OPE, "batch = %d io buf num = %d dir = %d rsc %d", + batch_idx, io_idx, io_buf->direction, io_buf->resource_type); + + io_port_cdm = + &bus_wr_ctx->io_port_cdm_batch.io_port_cdm[batch_idx]; + out_port_idx = + cam_ope_bus_wr_out_port_idx(io_buf->resource_type); + if (out_port_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid idx for rsc type: %d", + io_buf->resource_type); + return NULL; + } + out_port_to_wm = &wr_info->out_port_to_wm[out_port_idx]; + comb_idx = BUS_WR_YUV; + num_wm_ports = out_port_to_wm->num_wm[comb_idx]; + + for (k = 0; k < io_buf->num_planes; k++) { + *num_stripes = io_buf->num_stripes[k]; + for (l = 0; l < io_buf->num_stripes[k]; l++) { + stripe_io = &io_buf->s_io[k][l]; + CAM_DBG(CAM_OPE, "comb_idx = %d p_idx = %d s_idx = %d", + comb_idx, k, l); + /* frame level info */ + /* stripe level info */ + wm_port_id = out_port_to_wm->wm_port_id[comb_idx][k]; + wr_reg_client = &wr_reg->wr_clients[wm_port_id]; + wr_res_val_client = &wr_reg_val->wr_clients[wm_port_id]; + + /* Core cfg: enable, Mode */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->core_cfg; + temp = 0; + if (!stripe_io->disable_bus) + temp = wr_res_val_client->core_cfg_en; + temp |= ((wr_res_val_client->mode & + wr_res_val_client->mode_mask) << + wr_res_val_client->mode_shift); + temp_reg[count++] = temp; + + /* Address of the Image */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->img_addr; + temp_reg[count++] = stripe_io->iova_addr; + + /* Buffer size */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->img_cfg; + temp = 0; + temp = stripe_io->width; + temp |= (stripe_io->height & + wr_res_val_client->height_mask) << + wr_res_val_client->height_shift; + temp_reg[count++] = temp; + + /* x_init */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->x_init; + temp_reg[count++] = stripe_io->x_init; + + /* stride */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->stride; + temp_reg[count++] = stripe_io->stride; + + /* pack cfg : Format and alignment */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->pack_cfg; + temp = 0; + + /* + * In case of NV12, change the packer format of chroma + * plane to odd even byte swapped format + */ + + if (k == 1 && stripe_io->format == CAM_FORMAT_NV12) + stripe_io->pack_format = + PACKER_FMT_PLAIN_8_ODD_EVEN; + + temp |= ((stripe_io->pack_format & + wr_res_val_client->format_mask) << + wr_res_val_client->format_shift); + temp |= ((stripe_io->alignment & + wr_res_val_client->alignment_mask) << + wr_res_val_client->alignment_shift); + temp_reg[count++] = temp; + + /* subsample period and pattern */ + count = cam_ope_bus_wr_subsample( + ctx_data, ope_hw_info, + wr_reg_client, io_buf, + temp_reg, count, k, l); + + header_size = cdm_ops->cdm_get_cmd_header_size( + CAM_CDM_CMD_REG_RANDOM); + idx = io_port_cdm->num_s_cmd_bufs[l]; + io_port_cdm->s_cdm_info[l][idx].len = + sizeof(temp) * (count + header_size); + io_port_cdm->s_cdm_info[l][idx].offset = + prepare->kmd_buf_offset; + io_port_cdm->s_cdm_info[l][idx].addr = kmd_buf; + io_port_cdm->num_s_cmd_bufs[l]++; + + kmd_buf = cdm_ops->cdm_write_regrandom( + kmd_buf, count/2, temp_reg); + prepare->kmd_buf_offset += ((count + header_size) * + sizeof(temp)); + + CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", + batch_idx, io_idx, k, l); + for (m = 0; m < count; m += 2) + CAM_DBG(CAM_OPE, "%d: off: 0x%x val: 0x%x", + m, temp_reg[m], temp_reg[m+1]); + CAM_DBG(CAM_OPE, "kmdbuf:%x, offset:%d", + kmd_buf, prepare->kmd_buf_offset); + CAM_DBG(CAM_OPE, "WR cmd bufs = %d off:%d len:%d", + io_port_cdm->num_s_cmd_bufs[l], + io_port_cdm->s_cdm_info[l][idx].offset, + io_port_cdm->s_cdm_info[l][idx].len); + count = 0; + } + } + + return kmd_buf; +} + +static uint32_t *cam_ope_bus_wm_disable(struct ope_hw *ope_hw_info, + int32_t ctx_id, struct cam_ope_dev_prepare_req *prepare, + int batch_idx, int io_idx, + uint32_t *kmd_buf, uint32_t num_stripes) +{ + int k, l; + uint32_t idx; + uint32_t num_wm_ports; + uint32_t comb_idx; + uint32_t req_idx; + uint32_t temp_reg[128]; + uint32_t count = 0; + uint32_t temp = 0; + uint32_t wm_port_id; + uint32_t header_size; + struct cam_ope_ctx *ctx_data; + struct ope_bus_wr_ctx *bus_wr_ctx; + struct cam_ope_bus_wr_reg *wr_reg; + struct cam_ope_bus_wr_client_reg *wr_reg_client; + struct ope_bus_out_port_to_wm *out_port_to_wm; + struct ope_bus_wr_io_port_cdm_batch *io_port_cdm_batch; + struct ope_bus_wr_io_port_cdm_info *io_port_cdm; + struct cam_cdm_utils_ops *cdm_ops; + + + if (ctx_id < 0 || !prepare) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, prepare); + return NULL; + } + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch idx: %d", batch_idx); + return NULL; + } + + ctx_data = prepare->ctx_data; + req_idx = prepare->req_idx; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + bus_wr_ctx = wr_info->bus_wr_ctx[ctx_id]; + io_port_cdm_batch = &bus_wr_ctx->io_port_cdm_batch; + wr_reg = ope_hw_info->bus_wr_reg; + + CAM_DBG(CAM_OPE, + "kmd_buf = %x req_idx = %d offset = %d out_idx %d b %d", + kmd_buf, req_idx, prepare->kmd_buf_offset, io_idx, batch_idx); + + io_port_cdm = + &bus_wr_ctx->io_port_cdm_batch.io_port_cdm[batch_idx]; + out_port_to_wm = &wr_info->out_port_to_wm[io_idx]; + comb_idx = BUS_WR_YUV; + num_wm_ports = out_port_to_wm->num_wm[comb_idx]; + + for (k = 0; k < num_wm_ports; k++) { + for (l = 0; l < num_stripes; l++) { + /* frame level info */ + /* stripe level info */ + wm_port_id = out_port_to_wm->wm_port_id[comb_idx][k]; + wr_reg_client = &wr_reg->wr_clients[wm_port_id]; + + /* Core cfg: enable, Mode */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->core_cfg; + temp_reg[count++] = 0; + + header_size = cdm_ops->cdm_get_cmd_header_size( + CAM_CDM_CMD_REG_RANDOM); + idx = io_port_cdm->num_s_cmd_bufs[l]; + io_port_cdm->s_cdm_info[l][idx].len = + sizeof(temp) * (count + header_size); + io_port_cdm->s_cdm_info[l][idx].offset = + prepare->kmd_buf_offset; + io_port_cdm->s_cdm_info[l][idx].addr = kmd_buf; + io_port_cdm->num_s_cmd_bufs[l]++; + + kmd_buf = cdm_ops->cdm_write_regrandom( + kmd_buf, count/2, temp_reg); + prepare->kmd_buf_offset += ((count + header_size) * + sizeof(temp)); + + CAM_DBG(CAM_OPE, "WR cmd bufs = %d", + io_port_cdm->num_s_cmd_bufs[l]); + CAM_DBG(CAM_OPE, "s:%d off:%d len:%d", + l, io_port_cdm->s_cdm_info[l][idx].offset, + io_port_cdm->s_cdm_info[l][idx].len); + count = 0; + } + } + + prepare->wr_cdm_batch = &bus_wr_ctx->io_port_cdm_batch; + + return kmd_buf; +} + +static int cam_ope_bus_wr_prepare(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + int i, j = 0; + uint32_t req_idx; + uint32_t *kmd_buf; + struct cam_ope_dev_prepare_req *prepare; + struct cam_ope_ctx *ctx_data; + struct cam_ope_request *ope_request; + struct ope_io_buf *io_buf; + uint32_t temp; + int io_buf_idx; + uint32_t num_stripes = 0; + struct ope_bus_wr_io_port_cdm_batch *io_port_cdm_batch; + struct ope_bus_wr_ctx *bus_wr_ctx; + + if (ctx_id < 0 || !data) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, data); + return -EINVAL; + } + prepare = data; + ctx_data = prepare->ctx_data; + req_idx = prepare->req_idx; + bus_wr_ctx = wr_info->bus_wr_ctx[ctx_id]; + + ope_request = ctx_data->req_list[req_idx]; + kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + + (prepare->kmd_buf_offset / sizeof(temp)); + + + CAM_DBG(CAM_OPE, "kmd_buf = %x req_idx = %d req_id = %lld offset = %d", + kmd_buf, req_idx, ope_request->request_id, + prepare->kmd_buf_offset); + + io_port_cdm_batch = &wr_info->bus_wr_ctx[ctx_id]->io_port_cdm_batch; + memset(io_port_cdm_batch, 0, + sizeof(struct ope_bus_wr_io_port_cdm_batch)); + + for (i = 0; i < ope_request->num_batch; i++) { + for (j = 0; j < ope_request->num_io_bufs[i]; j++) { + io_buf = ope_request->io_buf[i][j]; + CAM_DBG(CAM_OPE, "batch = %d io buf num = %d dir = %d", + i, j, io_buf->direction); + if (io_buf->direction != CAM_BUF_OUTPUT) + continue; + + kmd_buf = cam_ope_bus_wr_update(ope_hw_info, + ctx_id, prepare, i, j, + kmd_buf, &num_stripes); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + } + } + + /* Disable WMs which are not enabled */ + for (i = 0; i < ope_request->num_batch; i++) { + for (j = OPE_OUT_RES_VIDEO; j <= OPE_OUT_RES_MAX; j++) { + io_buf_idx = cam_ope_bus_en_port_idx(ope_request, i, j); + if (io_buf_idx >= 0) + continue; + + io_buf_idx = cam_ope_bus_wr_out_port_idx(j); + if (io_buf_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid idx for rsc type:%d", + j); + return io_buf_idx; + } + kmd_buf = cam_ope_bus_wm_disable(ope_hw_info, + ctx_id, prepare, i, io_buf_idx, + kmd_buf, num_stripes); + } + } + prepare->wr_cdm_batch = &bus_wr_ctx->io_port_cdm_batch; + +end: + return rc; +} + +static int cam_ope_bus_wr_acquire(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0, i; + struct ope_acquire_dev_info *in_acquire; + struct ope_bus_wr_ctx *bus_wr_ctx; + struct ope_bus_out_port_to_wm *out_port_to_wr; + int combo_idx; + int out_port_idx; + + if (ctx_id < 0 || !data || ctx_id >= OPE_CTX_MAX) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, data); + return -EINVAL; + } + + wr_info->bus_wr_ctx[ctx_id] = vzalloc(sizeof(struct ope_bus_wr_ctx)); + if (!wr_info->bus_wr_ctx[ctx_id]) { + CAM_ERR(CAM_OPE, "Out of memory"); + return -ENOMEM; + } + + wr_info->bus_wr_ctx[ctx_id]->ope_acquire = data; + in_acquire = data; + bus_wr_ctx = wr_info->bus_wr_ctx[ctx_id]; + bus_wr_ctx->num_out_ports = in_acquire->num_out_res; + bus_wr_ctx->security_flag = in_acquire->secure_mode; + + for (i = 0; i < in_acquire->num_out_res; i++) { + if (!in_acquire->out_res[i].width) + continue; + + CAM_DBG(CAM_OPE, "i = %d format = %u width = %x height = %x", + i, in_acquire->out_res[i].format, + in_acquire->out_res[i].width, + in_acquire->out_res[i].height); + CAM_DBG(CAM_OPE, "pix_pattern:%u alignment:%u packer_format:%u", + in_acquire->out_res[i].pixel_pattern, + in_acquire->out_res[i].alignment, + in_acquire->out_res[i].packer_format); + CAM_DBG(CAM_OPE, "subsample_period = %u subsample_pattern = %u", + in_acquire->out_res[i].subsample_period, + in_acquire->out_res[i].subsample_pattern); + + out_port_idx = + cam_ope_bus_wr_out_port_idx(in_acquire->out_res[i].res_id); + if (out_port_idx < 0) { + CAM_DBG(CAM_OPE, "Invalid in_port_idx: %d", + in_acquire->out_res[i].res_id); + rc = -EINVAL; + goto end; + } + out_port_to_wr = &wr_info->out_port_to_wm[out_port_idx]; + combo_idx = BUS_WR_YUV; + if (!out_port_to_wr->num_wm[combo_idx]) { + CAM_DBG(CAM_OPE, "Invalid format for Input port"); + rc = -EINVAL; + goto end; + } + + bus_wr_ctx->io_port_info.output_port_id[i] = + in_acquire->out_res[i].res_id; + bus_wr_ctx->io_port_info.output_format_type[i] = + in_acquire->out_res[i].format; + if (in_acquire->out_res[i].pixel_pattern > + PIXEL_PATTERN_CRYCBY) { + CAM_DBG(CAM_OPE, "Invalid pix pattern = %u", + in_acquire->out_res[i].pixel_pattern); + rc = -EINVAL; + goto end; + } + + bus_wr_ctx->io_port_info.pixel_pattern[i] = + in_acquire->out_res[i].pixel_pattern; + bus_wr_ctx->io_port_info.latency_buf_size = 4096; + CAM_DBG(CAM_OPE, "i:%d port_id = %u format %u pix_pattern = %u", + i, bus_wr_ctx->io_port_info.output_port_id[i], + bus_wr_ctx->io_port_info.output_format_type[i], + bus_wr_ctx->io_port_info.pixel_pattern[i]); + CAM_DBG(CAM_OPE, "latency_buf_size = %u", + bus_wr_ctx->io_port_info.latency_buf_size); + } + +end: + return rc; +} + +static int cam_ope_bus_wr_init(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + struct cam_ope_bus_wr_reg_val *bus_wr_reg_val; + struct cam_ope_bus_wr_reg *bus_wr_reg; + struct cam_ope_dev_init *dev_init = data; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + wr_info->ope_hw_info = ope_hw_info; + bus_wr_reg_val = ope_hw_info->bus_wr_reg_val; + bus_wr_reg = ope_hw_info->bus_wr_reg; + bus_wr_reg->base = dev_init->core_info->ope_hw_info->ope_bus_wr_base; + + cam_io_w_mb(bus_wr_reg_val->irq_mask_0, + ope_hw_info->bus_wr_reg->base + bus_wr_reg->irq_mask_0); + cam_io_w_mb(bus_wr_reg_val->irq_mask_1, + ope_hw_info->bus_wr_reg->base + bus_wr_reg->irq_mask_1); + + return rc; +} + +static int cam_ope_bus_wr_probe(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0, i, j, combo_idx, k; + struct cam_ope_bus_wr_reg_val *bus_wr_reg_val; + struct ope_bus_out_port_to_wm *out_port_to_wm; + uint32_t output_port_idx; + uint32_t wm_idx; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + wr_info = kzalloc(sizeof(struct ope_bus_wr), GFP_KERNEL); + if (!wr_info) { + CAM_ERR(CAM_OPE, "Out of memory"); + return -ENOMEM; + } + + wr_info->ope_hw_info = ope_hw_info; + bus_wr_reg_val = ope_hw_info->bus_wr_reg_val; + + for (i = 0; i < bus_wr_reg_val->num_clients; i++) { + output_port_idx = + bus_wr_reg_val->wr_clients[i].output_port_id - 1; + out_port_to_wm = &wr_info->out_port_to_wm[output_port_idx]; + combo_idx = BUS_WR_YUV; + wm_idx = out_port_to_wm->num_wm[combo_idx]; + out_port_to_wm->output_port_id = + bus_wr_reg_val->wr_clients[i].output_port_id; + out_port_to_wm->wm_port_id[combo_idx][wm_idx] = + bus_wr_reg_val->wr_clients[i].wm_port_id; + if (!out_port_to_wm->num_wm[combo_idx]) + out_port_to_wm->num_combos++; + out_port_to_wm->num_wm[combo_idx]++; + } + + for (i = 0; i < OPE_OUT_RES_MAX; i++) { + out_port_to_wm = &wr_info->out_port_to_wm[i]; + CAM_DBG(CAM_OPE, "output port id = %d num_combos = %d", + out_port_to_wm->output_port_id, + out_port_to_wm->num_combos); + for (j = 0; j < out_port_to_wm->num_combos; j++) { + CAM_DBG(CAM_OPE, "combo idx = %d num_wms = %d", + j, out_port_to_wm->num_wm[j]); + for (k = 0; k < out_port_to_wm->num_wm[j]; k++) { + CAM_DBG(CAM_OPE, "wm port id = %d", + out_port_to_wm->wm_port_id[j][k]); + } + } + } + + return rc; +} + +static int cam_ope_bus_wr_isr(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + uint32_t irq_status_0, irq_status_1, violation_status; + struct cam_ope_bus_wr_reg *bus_wr_reg; + struct cam_ope_bus_wr_reg_val *bus_wr_reg_val; + struct cam_ope_irq_data *irq_data = data; + + if (!ope_hw_info || !irq_data) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + bus_wr_reg = ope_hw_info->bus_wr_reg; + bus_wr_reg_val = ope_hw_info->bus_wr_reg_val; + + /* Read and Clear Top Interrupt status */ + irq_status_0 = cam_io_r_mb(bus_wr_reg->base + bus_wr_reg->irq_status_0); + irq_status_1 = cam_io_r_mb(bus_wr_reg->base + bus_wr_reg->irq_status_1); + cam_io_w_mb(irq_status_0, + bus_wr_reg->base + bus_wr_reg->irq_clear_0); + cam_io_w_mb(irq_status_1, + bus_wr_reg->base + bus_wr_reg->irq_clear_1); + + cam_io_w_mb(bus_wr_reg_val->irq_set_clear, + bus_wr_reg->base + bus_wr_reg->irq_cmd); + + if (irq_status_0 & bus_wr_reg_val->cons_violation) { + irq_data->error = 1; + CAM_ERR(CAM_OPE, "ope bus wr cons_violation"); + } + + if (irq_status_0 & bus_wr_reg_val->violation) { + irq_data->error = 1; + violation_status = cam_io_r_mb(bus_wr_reg->base + + bus_wr_reg->violation_status); + CAM_ERR(CAM_OPE, + "ope bus wr violation, violation_status 0x%x", + violation_status); + } + + if (irq_status_0 & bus_wr_reg_val->img_size_violation) { + irq_data->error = 1; + violation_status = cam_io_r_mb(bus_wr_reg->base + + bus_wr_reg->image_size_violation_status); + CAM_ERR(CAM_OPE, + "ope bus wr img_size_violation, violation_status 0x%x", + violation_status); + } + + return rc; +} + +int cam_ope_bus_wr_process(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t cmd_id, void *data) +{ + int rc = 0; + + switch (cmd_id) { + case OPE_HW_PROBE: + CAM_DBG(CAM_OPE, "OPE_HW_PROBE: E"); + rc = cam_ope_bus_wr_probe(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_PROBE: X"); + break; + case OPE_HW_INIT: + CAM_DBG(CAM_OPE, "OPE_HW_INIT: E"); + rc = cam_ope_bus_wr_init(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_INIT: X"); + break; + case OPE_HW_ACQUIRE: + CAM_DBG(CAM_OPE, "OPE_HW_ACQUIRE: E"); + rc = cam_ope_bus_wr_acquire(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_ACQUIRE: X"); + break; + case OPE_HW_RELEASE: + CAM_DBG(CAM_OPE, "OPE_HW_RELEASE: E"); + rc = cam_ope_bus_wr_release(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_RELEASE: X"); + break; + case OPE_HW_PREPARE: + CAM_DBG(CAM_OPE, "OPE_HW_PREPARE: E"); + rc = cam_ope_bus_wr_prepare(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_PREPARE: X"); + break; + case OPE_HW_DEINIT: + case OPE_HW_START: + case OPE_HW_STOP: + case OPE_HW_FLUSH: + case OPE_HW_CLK_UPDATE: + case OPE_HW_BW_UPDATE: + case OPE_HW_RESET: + case OPE_HW_SET_IRQ_CB: + rc = 0; + CAM_DBG(CAM_OPE, "Unhandled cmds: %d", cmd_id); + break; + case OPE_HW_ISR: + rc = cam_ope_bus_wr_isr(ope_hw_info, 0, data); + break; + default: + CAM_ERR(CAM_OPE, "Unsupported cmd: %d", cmd_id); + break; + } + + return rc; +} + diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.h b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.h new file mode 100644 index 0000000000000000000000000000000000000000..ed9b8cca68df475915e1664f37d0cb2f48e08273 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef OPE_BUS_WR_H +#define OPE_BUS_WR_H + +#include +#include +#include +#include "ope_hw.h" +#include "cam_hw_mgr_intf.h" +#include "cam_hw_intf.h" +#include "cam_soc_util.h" +#include "cam_context.h" +#include "cam_ope_context.h" +#include "cam_ope_hw_mgr.h" + +/** + * struct ope_bus_wr_cdm_info + * + * @offset: Offset + * @addr: Address + * @len: Length + */ +struct ope_bus_wr_cdm_info { + uint32_t offset; + uint32_t *addr; + uint32_t len; +}; + +/** + * struct ope_bus_wr_io_port_cdm_info + * + * @num_frames_cmds: Number of frame commands + * @f_cdm_info: Frame cdm info + * @num_stripes: Number of stripes + * @num_s_cmd_bufs: Number of stripe commands + * @s_cdm_info: Stripe cdm info + * @go_cmd_addr: GO command address + * @go_cmd_len: GO command length + */ +struct ope_bus_wr_io_port_cdm_info { + uint32_t num_frames_cmds; + struct ope_bus_wr_cdm_info f_cdm_info[MAX_WR_CLIENTS]; + uint32_t num_stripes; + uint32_t num_s_cmd_bufs[OPE_MAX_STRIPES]; + struct ope_bus_wr_cdm_info s_cdm_info[OPE_MAX_STRIPES][MAX_WR_CLIENTS]; + uint32_t *go_cmd_addr; + uint32_t go_cmd_len; +}; + +/** + * struct ope_bus_wr_io_port_cdm_batch + * + * num_batch: Number of batches + * io_port_cdm: CDM IO Port Info + */ +struct ope_bus_wr_io_port_cdm_batch { + uint32_t num_batch; + struct ope_bus_wr_io_port_cdm_info io_port_cdm[OPE_MAX_BATCH_SIZE]; +}; + +/** + * struct ope_bus_wr_wm + * + * @wm_port_id: WM port ID + * @format_type: Format type + */ +struct ope_bus_wr_wm { + uint32_t wm_port_id; + uint32_t format_type; +}; + +/** + * struct ope_bus_out_port_to_wm + * + * @output_port_id: Output port ID + * @num_combos: Number of combos + * @num_wm: Number of WMs + * @wm_port_id: WM port Id + */ +struct ope_bus_out_port_to_wm { + uint32_t output_port_id; + uint32_t num_combos; + uint32_t num_wm[BUS_WR_COMBO_MAX]; + uint32_t wm_port_id[BUS_WR_COMBO_MAX][MAX_WR_CLIENTS]; +}; + +/** + * struct ope_bus_wr_io_port_info + * + * @pixel_pattern: Pixel pattern + * @output_port_id: Port Id + * @output_format_type: Format type + * @latency_buf_size: Latency buffer size + */ +struct ope_bus_wr_io_port_info { + uint32_t pixel_pattern[OPE_OUT_RES_MAX]; + uint32_t output_port_id[OPE_OUT_RES_MAX]; + uint32_t output_format_type[OPE_OUT_RES_MAX]; + uint32_t latency_buf_size; +}; + +/** + * struct ope_bus_wr_ctx + * + * @ope_acquire: OPE acquire structure + * @security_flag: security flag + * @num_out_ports: Number of out ports + * @io_port_info: IO port info + * @io_port_cdm_batch: IO port cdm info + */ +struct ope_bus_wr_ctx { + struct ope_acquire_dev_info *ope_acquire; + bool security_flag; + uint32_t num_out_ports; + struct ope_bus_wr_io_port_info io_port_info; + struct ope_bus_wr_io_port_cdm_batch io_port_cdm_batch; +}; + +/** + * struct ope_bus_wr + * + * @ope_hw_info: OPE hardware info + * @out_port_to_wm: IO port to WM mapping + * @bus_wr_ctx: WM context + */ +struct ope_bus_wr { + struct ope_hw *ope_hw_info; + struct ope_bus_out_port_to_wm out_port_to_wm[OPE_OUT_RES_MAX]; + struct ope_bus_wr_ctx *bus_wr_ctx[OPE_CTX_MAX]; +}; + +#endif /* OPE_BUS_WR_H */ + diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c new file mode 100644 index 0000000000000000000000000000000000000000..38ec15dded428ca3bc38c5358ecc1804258bce3c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -0,0 +1,1787 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_io_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "ope_core.h" +#include "ope_soc.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "ope_hw.h" +#include "ope_dev_intf.h" +#include "cam_cdm_util.h" +#include "ope_bus_rd.h" +#include "ope_bus_wr.h" + +static int cam_ope_caps_vote(struct cam_ope_device_core_info *core_info, + struct cam_ope_dev_bw_update *cpas_vote) +{ + int rc = 0; + + if (cpas_vote->ahb_vote_valid) + rc = cam_cpas_update_ahb_vote(core_info->cpas_handle, + &cpas_vote->ahb_vote); + if (cpas_vote->axi_vote_valid) + rc = cam_cpas_update_axi_vote(core_info->cpas_handle, + &cpas_vote->axi_vote); + if (rc) + CAM_ERR(CAM_OPE, "cpas vote is failed: %d", rc); + + return rc; +} + +int cam_ope_get_hw_caps(void *hw_priv, void *get_hw_cap_args, + uint32_t arg_size) +{ + struct cam_hw_info *ope_dev = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ope_device_core_info *core_info = NULL; + struct ope_hw_ver *ope_hw_ver; + struct cam_ope_top_reg_val *top_reg_val; + + if (!hw_priv) { + CAM_ERR(CAM_OPE, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &ope_dev->soc_info; + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_OPE, "soc_info = %x core_info = %x", + soc_info, core_info); + return -EINVAL; + } + + if (!get_hw_cap_args) { + CAM_ERR(CAM_OPE, "Invalid caps"); + return -EINVAL; + } + + top_reg_val = core_info->ope_hw_info->ope_hw->top_reg_val; + ope_hw_ver = get_hw_cap_args; + ope_hw_ver->hw_type = core_info->hw_type; + ope_hw_ver->hw_ver.major = + (core_info->hw_version & top_reg_val->major_mask) >> + top_reg_val->major_shift; + ope_hw_ver->hw_ver.minor = + (core_info->hw_version & top_reg_val->minor_mask) >> + top_reg_val->minor_shift; + ope_hw_ver->hw_ver.incr = + (core_info->hw_version & top_reg_val->incr_mask) >> + top_reg_val->incr_shift; + + return 0; +} + +int cam_ope_start(void *hw_priv, void *start_args, uint32_t arg_size) +{ + return 0; +} + +int cam_ope_stop(void *hw_priv, void *start_args, uint32_t arg_size) +{ + struct cam_hw_info *ope_dev = hw_priv; + struct cam_ope_device_core_info *core_info = NULL; + int rc = 0; + + if (!hw_priv) { + CAM_ERR(CAM_OPE, "Invalid cam_dev_info"); + return -EINVAL; + } + + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + if (!core_info) { + CAM_ERR(CAM_OPE, "core_info = %pK", core_info); + return -EINVAL; + } + + if (core_info->cpas_start) { + if (cam_cpas_stop(core_info->cpas_handle)) + CAM_ERR(CAM_OPE, "cpas stop is failed"); + else + core_info->cpas_start = false; + } + + return rc; +} + +int cam_ope_flush(void *hw_priv, void *flush_args, uint32_t arg_size) +{ + return 0; +} + +static int cam_ope_dev_process_init(struct ope_hw *ope_hw, + void *cmd_args) +{ + int rc = 0; + + rc = cam_ope_top_process(ope_hw, 0, OPE_HW_INIT, cmd_args); + if (rc) + goto top_init_fail; + + rc = cam_ope_bus_rd_process(ope_hw, 0, OPE_HW_INIT, cmd_args); + if (rc) + goto bus_rd_init_fail; + + rc = cam_ope_bus_wr_process(ope_hw, 0, OPE_HW_INIT, cmd_args); + if (rc) + goto bus_wr_init_fail; + + return rc; + +bus_wr_init_fail: + rc = cam_ope_bus_rd_process(ope_hw, 0, + OPE_HW_DEINIT, NULL); +bus_rd_init_fail: + rc = cam_ope_top_process(ope_hw, 0, + OPE_HW_DEINIT, NULL); +top_init_fail: + return rc; +} + +static int cam_ope_process_init(struct ope_hw *ope_hw, + void *cmd_args, bool hfi_en) +{ + if (!hfi_en) + return cam_ope_dev_process_init(ope_hw, cmd_args); + + CAM_ERR(CAM_OPE, "hfi_en is not supported"); + return -EINVAL; +} + +int cam_ope_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *ope_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ope_device_core_info *core_info = NULL; + struct cam_ope_cpas_vote *cpas_vote; + int rc = 0; + struct cam_ope_dev_init *init; + struct ope_hw *ope_hw; + + if (!device_priv) { + CAM_ERR(CAM_OPE, "Invalid cam_dev_info"); + rc = -EINVAL; + goto end; + } + + soc_info = &ope_dev->soc_info; + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_OPE, "soc_info = %pK core_info = %pK", + soc_info, core_info); + rc = -EINVAL; + goto end; + } + ope_hw = core_info->ope_hw_info->ope_hw; + + cpas_vote = kzalloc(sizeof(struct cam_ope_cpas_vote), GFP_KERNEL); + if (!cpas_vote) { + CAM_ERR(CAM_ISP, "Out of memory"); + rc = -ENOMEM; + goto end; + } + + cpas_vote->ahb_vote.type = CAM_VOTE_ABSOLUTE; + cpas_vote->ahb_vote.vote.level = CAM_SVS_VOTE; + cpas_vote->axi_vote.num_paths = 1; + cpas_vote->axi_vote.axi_path[0].path_data_type = + CAM_AXI_PATH_DATA_ALL; + cpas_vote->axi_vote.axi_path[0].transac_type = + CAM_AXI_TRANSACTION_WRITE; + cpas_vote->axi_vote.axi_path[0].camnoc_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote->axi_vote.axi_path[0].mnoc_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote->axi_vote.axi_path[0].mnoc_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote->axi_vote.axi_path[0].ddr_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote->axi_vote.axi_path[0].ddr_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + + rc = cam_cpas_start(core_info->cpas_handle, + &cpas_vote->ahb_vote, &cpas_vote->axi_vote); + if (rc) { + CAM_ERR(CAM_OPE, "cpass start failed: %d", rc); + goto free_cpas_vote; + } + core_info->cpas_start = true; + + rc = cam_ope_enable_soc_resources(soc_info); + if (rc) + goto enable_soc_resource_failed; + else + core_info->clk_enable = true; + + init = init_hw_args; + + core_info->ope_hw_info->hfi_en = init->hfi_en; + init->core_info = core_info; + rc = cam_ope_process_init(ope_hw, init_hw_args, init->hfi_en); + if (rc) + goto process_init_failed; + else + goto free_cpas_vote; + +process_init_failed: + if (cam_ope_disable_soc_resources(soc_info, core_info->clk_enable)) + CAM_ERR(CAM_OPE, "disable soc resource failed"); +enable_soc_resource_failed: + if (cam_cpas_stop(core_info->cpas_handle)) + CAM_ERR(CAM_OPE, "cpas stop is failed"); + else + core_info->cpas_start = false; +free_cpas_vote: + kzfree(cpas_vote); + cpas_vote = NULL; +end: + return rc; +} + +int cam_ope_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *ope_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ope_device_core_info *core_info = NULL; + int rc = 0; + + if (!device_priv) { + CAM_ERR(CAM_OPE, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &ope_dev->soc_info; + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_OPE, "soc_info = %pK core_info = %pK", + soc_info, core_info); + return -EINVAL; + } + + rc = cam_ope_disable_soc_resources(soc_info, core_info->clk_enable); + if (rc) + CAM_ERR(CAM_OPE, "soc disable is failed : %d", rc); + core_info->clk_enable = false; + + return rc; +} + +static int cam_ope_dev_process_dump_debug_reg(struct ope_hw *ope_hw) +{ + int rc = 0; + + rc = cam_ope_top_process(ope_hw, -1, + OPE_HW_DUMP_DEBUG, NULL); + + return rc; +} + +static int cam_ope_dev_process_reset(struct ope_hw *ope_hw, void *cmd_args) +{ + int rc = 0; + + rc = cam_ope_top_process(ope_hw, -1, + OPE_HW_RESET, NULL); + + return rc; +} + +static int cam_ope_dev_process_release(struct ope_hw *ope_hw, void *cmd_args) +{ + int rc = 0; + struct cam_ope_dev_release *ope_dev_release; + + ope_dev_release = cmd_args; + rc = cam_ope_top_process(ope_hw, ope_dev_release->ctx_id, + OPE_HW_RELEASE, NULL); + + rc |= cam_ope_bus_rd_process(ope_hw, ope_dev_release->ctx_id, + OPE_HW_RELEASE, NULL); + + rc |= cam_ope_bus_wr_process(ope_hw, ope_dev_release->ctx_id, + OPE_HW_RELEASE, NULL); + + return rc; +} + +static int cam_ope_dev_process_acquire(struct ope_hw *ope_hw, void *cmd_args) +{ + int rc = 0; + struct cam_ope_dev_acquire *ope_dev_acquire; + + if (!cmd_args || !ope_hw) { + CAM_ERR(CAM_OPE, "Invalid arguments: %pK %pK", + cmd_args, ope_hw); + return -EINVAL; + } + + ope_dev_acquire = cmd_args; + rc = cam_ope_top_process(ope_hw, ope_dev_acquire->ctx_id, + OPE_HW_ACQUIRE, ope_dev_acquire->ope_acquire); + if (rc) + goto top_acquire_fail; + + rc = cam_ope_bus_rd_process(ope_hw, ope_dev_acquire->ctx_id, + OPE_HW_ACQUIRE, ope_dev_acquire->ope_acquire); + if (rc) + goto bus_rd_acquire_fail; + + rc = cam_ope_bus_wr_process(ope_hw, ope_dev_acquire->ctx_id, + OPE_HW_ACQUIRE, ope_dev_acquire->ope_acquire); + if (rc) + goto bus_wr_acquire_fail; + + return 0; + +bus_wr_acquire_fail: + cam_ope_bus_rd_process(ope_hw, ope_dev_acquire->ctx_id, + OPE_HW_RELEASE, ope_dev_acquire->ope_acquire); +bus_rd_acquire_fail: + cam_ope_top_process(ope_hw, ope_dev_acquire->ctx_id, + OPE_HW_RELEASE, ope_dev_acquire->ope_acquire); +top_acquire_fail: + return rc; +} + +static int cam_ope_dev_prepare_cdm_request( + struct cam_ope_hw_mgr *hw_mgr, + struct cam_hw_prepare_update_args *prepare_args, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t kmd_buf_offset, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req, + uint32_t len, bool arbitrate) +{ + int i; + struct cam_ope_request *ope_request; + struct cam_cdm_bl_request *cdm_cmd; + uint32_t *kmd_buf; + + ope_request = ctx_data->req_list[req_idx]; + cdm_cmd = ope_request->cdm_cmd; + kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + + kmd_buf_offset; + + cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE; + cdm_cmd->flag = true; + cdm_cmd->userdata = ctx_data; + cdm_cmd->cookie = req_idx; + cdm_cmd->gen_irq_arb = true; + + i = cdm_cmd->cmd_arrary_count; + cdm_cmd->cmd[i].bl_addr.mem_handle = + ope_request->ope_kmd_buf.mem_handle; + cdm_cmd->cmd[i].offset = kmd_buf_offset + + ope_request->ope_kmd_buf.offset; + cdm_cmd->cmd[i].len = len; + cdm_cmd->cmd[i].arbitrate = arbitrate; + cdm_cmd->cmd[i].enable_debug_gen_irq = false; + + cdm_cmd->cmd_arrary_count++; + + CAM_DBG(CAM_OPE, "CDM cmd:Req idx = %d req_id = %lld array cnt = %d", + cdm_cmd->cookie, ope_request->request_id, + cdm_cmd->cmd_arrary_count); + CAM_DBG(CAM_OPE, "CDM cmd:mem_hdl = %d offset = %d len = %d, iova 0x%x", + ope_request->ope_kmd_buf.mem_handle, kmd_buf_offset, len, + cdm_cmd->cmd[i].bl_addr.hw_iova); + + return 0; +} + + +static int dump_dmi_cmd(uint32_t print_idx, + uint32_t *print_ptr, struct cdm_dmi_cmd *dmi_cmd, + uint32_t *temp) +{ + CAM_DBG(CAM_OPE, "%d:dma_ptr:%x l:%d", + print_idx, print_ptr, + dmi_cmd->length); + CAM_DBG(CAM_OPE, "%d:cmd:%hhx addr:%x", + print_ptr, dmi_cmd->cmd, + dmi_cmd->addr); + CAM_DBG(CAM_OPE, "%d: dmiadr:%x sel:%d", + print_idx, dmi_cmd->DMIAddr, + dmi_cmd->DMISel); + CAM_DBG(CAM_OPE, "%d: %x %x %x", + print_idx, + temp[0], temp[1], temp[2]); + + return 0; +} + +static int dump_direct_cmd(uint32_t print_idx, + uint32_t *print_ptr, + struct ope_frame_process *frm_proc, + int batch_idx, int cmd_buf_idx) +{ + int len; + + if (cmd_buf_idx >= OPE_MAX_CMD_BUFS || + batch_idx >= OPE_MAX_BATCH_SIZE) + return 0; + + len = frm_proc->cmd_buf[batch_idx][cmd_buf_idx].length / 4; + CAM_DBG(CAM_OPE, "Frame DB : direct: E"); + for (print_idx = 0; print_idx < len; print_idx++) + CAM_DBG(CAM_OPE, "%d: %x", print_idx, print_ptr[print_idx]); + CAM_DBG(CAM_OPE, "Frame DB : direct: X"); + + return 0; +} + +static int dump_frame_cmd(struct ope_frame_process *frm_proc, + int i, int j, uint64_t iova_addr, uint32_t *kmd_buf, uint32_t buf_len) +{ + if (j >= OPE_MAX_CMD_BUFS || i >= OPE_MAX_BATCH_SIZE) + return 0; + + CAM_DBG(CAM_OPE, "Frame DB:scope:%d buffer:%d type:%d", + frm_proc->cmd_buf[i][j].cmd_buf_scope, + frm_proc->cmd_buf[i][j].cmd_buf_buffered, + frm_proc->cmd_buf[i][j].type); + CAM_DBG(CAM_OPE, "kmdbuf:%x memhdl:%x iova:%x %pK", + kmd_buf, + frm_proc->cmd_buf[i][j].mem_handle, + iova_addr, iova_addr); + CAM_DBG(CAM_OPE, "buflen:%d len:%d offset:%d", + buf_len, + frm_proc->cmd_buf[i][j].length, + frm_proc->cmd_buf[i][j].offset); + + return 0; +} + +static int dump_stripe_cmd(struct ope_frame_process *frm_proc, + uint32_t stripe_idx, int i, int k, uint64_t iova_addr, + uint32_t *kmd_buf, uint32_t buf_len) +{ + if (k >= OPE_MAX_CMD_BUFS) + return 0; + + CAM_DBG(CAM_OPE, "Stripe:%d scope:%d buffer:%d", + stripe_idx, + frm_proc->cmd_buf[i][k].cmd_buf_scope, + frm_proc->cmd_buf[i][k].cmd_buf_buffered); + CAM_DBG(CAM_OPE, "type:%d kmdbuf:%x memhdl:%x", + frm_proc->cmd_buf[i][k].type, kmd_buf, + frm_proc->cmd_buf[i][k].mem_handle); + CAM_DBG(CAM_OPE, "iova:%x %pK buflen:%d len:%d", + iova_addr, iova_addr, buf_len, + frm_proc->cmd_buf[i][k].length); + CAM_DBG(CAM_OPE, "offset:%d", + frm_proc->cmd_buf[i][k].offset); + return 0; +} + +static uint32_t *ope_create_frame_cmd_batch(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t *kmd_buf, uint32_t buffered, int batch_idx, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int rc = 0, i, j; + uint32_t temp[3]; + struct cam_ope_request *ope_request; + struct cdm_dmi_cmd *dmi_cmd; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + dma_addr_t iova_addr; + uintptr_t cpu_addr; + size_t buf_len; + uint32_t print_idx; + uint32_t *print_ptr; + int num_dmi = 0; + struct cam_cdm_utils_ops *cdm_ops; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[0]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[0]; + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid input: %d", batch_idx); + return NULL; + } + i = batch_idx; + + for (j = 0; j < frm_proc->num_cmd_bufs[i]; j++) { + if (frm_proc->cmd_buf[i][j].cmd_buf_scope != + OPE_CMD_BUF_SCOPE_FRAME) + continue; + + if (frm_proc->cmd_buf[i][j].cmd_buf_usage == + OPE_CMD_BUF_KMD || + frm_proc->cmd_buf[i][j].cmd_buf_usage == + OPE_CMD_BUF_DEBUG) + continue; + + if (frm_proc->cmd_buf[i][j].cmd_buf_buffered != + buffered) + continue; + + if (!frm_proc->cmd_buf[i][j].mem_handle) + continue; + + rc = cam_mem_get_io_buf( + frm_proc->cmd_buf[i][j].mem_handle, + hw_mgr->iommu_cdm_hdl, &iova_addr, &buf_len); + if (rc) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + return NULL; + } + iova_addr = iova_addr + frm_proc->cmd_buf[i][j].offset; + + rc = cam_mem_get_cpu_buf( + frm_proc->cmd_buf[i][j].mem_handle, + &cpu_addr, &buf_len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + return NULL; + } + + cpu_addr = cpu_addr + frm_proc->cmd_buf[i][j].offset; + if (frm_proc->cmd_buf[i][j].type == + OPE_CMD_BUF_TYPE_DIRECT) { + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + iova_addr, + frm_proc->cmd_buf[i][j].length); + print_ptr = (uint32_t *)cpu_addr; + dump_direct_cmd(print_idx, print_ptr, + frm_proc, i, j); + } else { + num_dmi = frm_proc->cmd_buf[i][j].length / + sizeof(struct cdm_dmi_cmd); + CAM_DBG(CAM_OPE, "Frame DB : In direct: E"); + print_ptr = (uint32_t *)cpu_addr; + for (print_idx = 0; + print_idx < num_dmi; print_idx++) { + memcpy(temp, (const void *)print_ptr, + sizeof(struct cdm_dmi_cmd)); + dmi_cmd = (struct cdm_dmi_cmd *)temp; + if (!dmi_cmd->addr) { + CAM_ERR(CAM_OPE, "Null dmi cmd addr"); + cam_mem_put_cpu_buf( + frm_proc->cmd_buf[i][j].mem_handle); + return NULL; + } + + kmd_buf = cdm_ops->cdm_write_dmi( + kmd_buf, + 0, dmi_cmd->DMIAddr, + dmi_cmd->DMISel, dmi_cmd->addr, + dmi_cmd->length); + if (hw_mgr->frame_dump_enable) + dump_dmi_cmd(print_idx, + print_ptr, dmi_cmd, temp); + print_ptr += + sizeof(struct cdm_dmi_cmd) / + sizeof(uint32_t); + } + CAM_DBG(CAM_OPE, "Frame DB : In direct: X"); + } + if (hw_mgr->frame_dump_enable) + dump_frame_cmd(frm_proc, i, j, + iova_addr, kmd_buf, buf_len); + + cam_mem_put_cpu_buf(frm_proc->cmd_buf[i][j].mem_handle); + } + return kmd_buf; + +} + +static uint32_t *ope_create_frame_wr(struct cam_ope_ctx *ctx_data, + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info, + uint32_t *kmd_buf, struct cam_ope_request *ope_request) +{ + struct cam_cdm_utils_ops *cdm_ops; + int i; + + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + for (i = 0; i < wr_cdm_info->num_frames_cmds; i++) { + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + wr_cdm_info->f_cdm_info[i].offset, + wr_cdm_info->f_cdm_info[i].len); + CAM_DBG(CAM_OPE, "FrameWR:i:%d kmdbuf:%x len:%d iova:%x %pK", + i, kmd_buf, wr_cdm_info->f_cdm_info[i].len, + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + } + return kmd_buf; +} + +static uint32_t *ope_create_frame_rd(struct cam_ope_ctx *ctx_data, + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info, + uint32_t *kmd_buf, struct cam_ope_request *ope_request) +{ + struct cam_cdm_utils_ops *cdm_ops; + int i; + + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + /* Frame 0 RD */ + for (i = 0; i < rd_cdm_info->num_frames_cmds; i++) { + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + rd_cdm_info->f_cdm_info[i].offset, + rd_cdm_info->f_cdm_info[i].len); + CAM_DBG(CAM_OPE, "FrameRD:i:%d kmdbuf:%x len:%d iova:%x %pK", + i, kmd_buf, rd_cdm_info->f_cdm_info[i].len, + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + } + return kmd_buf; +} + +static uint32_t *ope_create_frame_cmd(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t *kmd_buf, uint32_t buffered, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int rc = 0, i, j; + uint32_t temp[3]; + struct cam_ope_request *ope_request; + struct cdm_dmi_cmd *dmi_cmd; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + dma_addr_t iova_addr; + uintptr_t cpu_addr; + size_t buf_len; + uint32_t print_idx; + uint32_t *print_ptr; + int num_dmi = 0; + struct cam_cdm_utils_ops *cdm_ops; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[0]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[0]; + + for (i = 0; i < frm_proc->batch_size; i++) { + for (j = 0; j < frm_proc->num_cmd_bufs[i]; j++) { + if (frm_proc->cmd_buf[i][j].cmd_buf_scope != + OPE_CMD_BUF_SCOPE_FRAME) + continue; + + if (frm_proc->cmd_buf[i][j].cmd_buf_usage == + OPE_CMD_BUF_KMD || + frm_proc->cmd_buf[i][j].cmd_buf_usage == + OPE_CMD_BUF_DEBUG) + continue; + + if (frm_proc->cmd_buf[i][j].cmd_buf_buffered != + buffered) + continue; + + if (!frm_proc->cmd_buf[i][j].mem_handle) + continue; + + rc = cam_mem_get_io_buf( + frm_proc->cmd_buf[i][j].mem_handle, + hw_mgr->iommu_cdm_hdl, &iova_addr, &buf_len); + if (rc) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + return NULL; + } + iova_addr = iova_addr + frm_proc->cmd_buf[i][j].offset; + + rc = cam_mem_get_cpu_buf( + frm_proc->cmd_buf[i][j].mem_handle, + &cpu_addr, &buf_len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + return NULL; + } + + cpu_addr = cpu_addr + frm_proc->cmd_buf[i][j].offset; + if (frm_proc->cmd_buf[i][j].type == + OPE_CMD_BUF_TYPE_DIRECT) { + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + iova_addr, + frm_proc->cmd_buf[i][j].length); + print_ptr = (uint32_t *)cpu_addr; + if (hw_mgr->frame_dump_enable) + dump_direct_cmd(print_idx, print_ptr, + frm_proc, i, j); + } else { + num_dmi = frm_proc->cmd_buf[i][j].length / + sizeof(struct cdm_dmi_cmd); + CAM_DBG(CAM_OPE, "Frame DB : In direct: E"); + print_ptr = (uint32_t *)cpu_addr; + for (print_idx = 0; + print_idx < num_dmi; print_idx++) { + memcpy(temp, (const void *)print_ptr, + sizeof(struct cdm_dmi_cmd)); + dmi_cmd = (struct cdm_dmi_cmd *)temp; + if (!dmi_cmd->addr) { + CAM_ERR(CAM_OPE, + "Null dmi cmd addr"); + cam_mem_put_cpu_buf( + frm_proc->cmd_buf[i][j].mem_handle); + return NULL; + } + + kmd_buf = cdm_ops->cdm_write_dmi( + kmd_buf, + 0, dmi_cmd->DMIAddr, + dmi_cmd->DMISel, dmi_cmd->addr, + dmi_cmd->length); + if (hw_mgr->frame_dump_enable) + dump_dmi_cmd(print_idx, + print_ptr, dmi_cmd, + temp); + print_ptr += + sizeof(struct cdm_dmi_cmd) / + sizeof(uint32_t); + } + CAM_DBG(CAM_OPE, "Frame DB : In direct: X"); + } + if (hw_mgr->frame_dump_enable) + dump_frame_cmd(frm_proc, i, j, + iova_addr, kmd_buf, buf_len); + + cam_mem_put_cpu_buf(frm_proc->cmd_buf[i][j].mem_handle); + } + } + return kmd_buf; +} + +static uint32_t *ope_create_stripe_cmd(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + uint32_t *kmd_buf, + int batch_idx, + int s_idx, + uint32_t stripe_idx, + struct ope_frame_process *frm_proc) +{ + int rc = 0, i, j, k; + uint32_t temp[3]; + struct cdm_dmi_cmd *dmi_cmd; + dma_addr_t iova_addr; + uintptr_t cpu_addr; + size_t buf_len; + uint32_t print_idx; + uint32_t *print_ptr; + int num_dmi = 0; + struct cam_cdm_utils_ops *cdm_ops; + uint32_t reg_val_pair[2]; + struct cam_hw_info *ope_dev; + struct cam_ope_device_core_info *core_info; + struct ope_hw *ope_hw; + struct cam_ope_top_reg *top_reg; + + if (s_idx >= OPE_MAX_CMD_BUFS || + batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid inputs: %d %d", + batch_idx, s_idx); + return NULL; + } + + i = batch_idx; + j = s_idx; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + /* cmd buffer stripes */ + for (k = 0; k < frm_proc->num_cmd_bufs[i]; k++) { + if (frm_proc->cmd_buf[i][k].cmd_buf_scope != + OPE_CMD_BUF_SCOPE_STRIPE) + continue; + + if (frm_proc->cmd_buf[i][k].stripe_idx != + stripe_idx) + continue; + + if (!frm_proc->cmd_buf[i][k].mem_handle) + continue; + + CAM_DBG(CAM_OPE, "process stripe %d", stripe_idx); + rc = cam_mem_get_io_buf(frm_proc->cmd_buf[i][k].mem_handle, + hw_mgr->iommu_cdm_hdl, + &iova_addr, &buf_len); + if (rc) { + CAM_DBG(CAM_OPE, "get cmd buf fail %x", + hw_mgr->iommu_hdl); + return NULL; + } + iova_addr = iova_addr + frm_proc->cmd_buf[i][k].offset; + rc = cam_mem_get_cpu_buf(frm_proc->cmd_buf[i][k].mem_handle, + &cpu_addr, &buf_len); + if (rc || !cpu_addr) { + CAM_DBG(CAM_OPE, "get cmd buf fail %x", + hw_mgr->iommu_hdl); + return NULL; + } + cpu_addr = cpu_addr + frm_proc->cmd_buf[i][k].offset; + + if (frm_proc->cmd_buf[i][k].type == OPE_CMD_BUF_TYPE_DIRECT) { + kmd_buf = cdm_ops->cdm_write_indirect( + kmd_buf, + iova_addr, + frm_proc->cmd_buf[i][k].length); + print_ptr = (uint32_t *)cpu_addr; + CAM_DBG(CAM_OPE, "Stripe:%d direct:E", + stripe_idx); + if (hw_mgr->frame_dump_enable) + dump_direct_cmd(print_idx, print_ptr, + frm_proc, i, k); + CAM_DBG(CAM_OPE, "Stripe:%d direct:X", stripe_idx); + } else if (frm_proc->cmd_buf[i][k].type == + OPE_CMD_BUF_TYPE_INDIRECT) { + num_dmi = frm_proc->cmd_buf[i][j].length / + sizeof(struct cdm_dmi_cmd); + CAM_DBG(CAM_OPE, "Stripe:%d Indirect:E", stripe_idx); + print_ptr = (uint32_t *)cpu_addr; + for (print_idx = 0; print_idx < num_dmi; print_idx++) { + memcpy(temp, (const void *)print_ptr, + sizeof(struct cdm_dmi_cmd)); + dmi_cmd = (struct cdm_dmi_cmd *)temp; + if (!dmi_cmd->addr) { + CAM_ERR(CAM_OPE, "Null dmi cmd addr"); + cam_mem_put_cpu_buf( + frm_proc->cmd_buf[i][k].mem_handle); + return NULL; + } + + kmd_buf = cdm_ops->cdm_write_dmi(kmd_buf, + 0, dmi_cmd->DMIAddr, dmi_cmd->DMISel, + dmi_cmd->addr, dmi_cmd->length); + if (hw_mgr->frame_dump_enable) + dump_dmi_cmd(print_idx, + print_ptr, dmi_cmd, temp); + print_ptr += sizeof(struct cdm_dmi_cmd) / + sizeof(uint32_t); + } + CAM_DBG(CAM_OPE, "Stripe:%d Indirect:X", stripe_idx); + } + + if (hw_mgr->frame_dump_enable) + dump_stripe_cmd(frm_proc, stripe_idx, i, k, + iova_addr, kmd_buf, buf_len); + + cam_mem_put_cpu_buf(frm_proc->cmd_buf[i][k].mem_handle); + } + + ope_dev = hw_mgr->ope_dev_intf[0]->hw_priv; + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + ope_hw = core_info->ope_hw_info->ope_hw; + top_reg = ope_hw->top_reg; + + reg_val_pair[0] = top_reg->offset + top_reg->scratch_reg; + reg_val_pair[1] = stripe_idx; + kmd_buf = cdm_ops->cdm_write_regrandom(kmd_buf, 1, reg_val_pair); + + return kmd_buf; +} + +static uint32_t *ope_create_stripe_wr(struct cam_ope_ctx *ctx_data, + uint32_t stripe_idx, struct ope_bus_wr_io_port_cdm_info *wr_cdm_info, + struct cam_ope_request *ope_request, uint32_t *kmd_buf) +{ + struct cam_cdm_utils_ops *cdm_ops; + int k; + + if (stripe_idx >= OPE_MAX_STRIPES) { + CAM_ERR(CAM_OPE, "invalid s_idx = %d", stripe_idx); + return NULL; + } + + cdm_ops = ctx_data->ope_cdm.cdm_ops; + for (k = 0; k < wr_cdm_info->num_s_cmd_bufs[stripe_idx]; k++) { + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + wr_cdm_info->s_cdm_info[stripe_idx][k].offset, + wr_cdm_info->s_cdm_info[stripe_idx][k].len); + CAM_DBG(CAM_OPE, "WR stripe:%d %d kmdbuf:%x", + stripe_idx, k, kmd_buf); + CAM_DBG(CAM_OPE, "offset:%d len:%d iova:%x %pK", + wr_cdm_info->s_cdm_info[stripe_idx][k].offset, + wr_cdm_info->s_cdm_info[stripe_idx][k].len, + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + } + return kmd_buf; +} + +static uint32_t *ope_create_stripe_rd(struct cam_ope_ctx *ctx_data, + uint32_t stripe_idx, struct ope_bus_rd_io_port_cdm_info *rd_cdm_info, + struct cam_ope_request *ope_request, uint32_t *kmd_buf) +{ + struct cam_cdm_utils_ops *cdm_ops; + int k; + + if (stripe_idx >= OPE_MAX_STRIPES) { + CAM_ERR(CAM_OPE, "invalid s_idx = %d", stripe_idx); + return NULL; + } + + cdm_ops = ctx_data->ope_cdm.cdm_ops; + for (k = 0; k < rd_cdm_info->num_s_cmd_bufs[stripe_idx]; k++) { + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + rd_cdm_info->s_cdm_info[stripe_idx][k].offset, + rd_cdm_info->s_cdm_info[stripe_idx][k].len); + CAM_DBG(CAM_OPE, "WR stripe:%d %d kmdbuf:%x", + stripe_idx, k, kmd_buf); + CAM_DBG(CAM_OPE, "offset:%d len:%d iova:%x %pK", + rd_cdm_info->s_cdm_info[stripe_idx][k].offset, + rd_cdm_info->s_cdm_info[stripe_idx][k].len, + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + } + return kmd_buf; +} + +static uint32_t *ope_create_stripes_batch(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t *kmd_buf, int batch_idx, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int i, j; + struct cam_ope_request *ope_request; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + uint32_t stripe_idx = 0; + struct cam_cdm_utils_ops *cdm_ops; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid input: %d", batch_idx); + return NULL; + } + i = batch_idx; + /* Stripes */ + + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[i]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[i]; + for (j = 0; j < ope_request->num_stripes[i]; j++) { + /* cmd buffer stripes */ + kmd_buf = ope_create_stripe_cmd(hw_mgr, ctx_data, + kmd_buf, i, j, stripe_idx, frm_proc); + if (!kmd_buf) + goto end; + + /* WR stripes */ + kmd_buf = ope_create_stripe_wr(ctx_data, stripe_idx, + wr_cdm_info, ope_request, kmd_buf); + if (!kmd_buf) + goto end; + + /* RD stripes */ + kmd_buf = ope_create_stripe_rd(ctx_data, stripe_idx, + rd_cdm_info, ope_request, kmd_buf); + if (!kmd_buf) + goto end; + + /* add go command */ + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + rd_cdm_info->go_cmd_offset, + rd_cdm_info->go_cmd_len); + + CAM_DBG(CAM_OPE, "Go cmd for stripe:%d kmd_buf:%x", + stripe_idx, kmd_buf); + CAM_DBG(CAM_OPE, "iova:%x %pK", + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + + /* wait for RUP done */ + kmd_buf = cdm_ops->cdm_write_wait_comp_event(kmd_buf, + OPE_WAIT_COMP_RUP, 0x0); + CAM_DBG(CAM_OPE, "wait RUP cmd stripe:%d kmd_buf:%x", + stripe_idx, kmd_buf); + stripe_idx++; + } + +end: + return kmd_buf; +} + +static uint32_t *ope_create_stripes(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t *kmd_buf, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int i, j; + struct cam_ope_request *ope_request; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + uint32_t stripe_idx = 0; + struct cam_cdm_utils_ops *cdm_ops; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + /* Stripes */ + for (i = 0; i < frm_proc->batch_size; i++) { + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[i]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[i]; + for (j = 0; j < ope_request->num_stripes[i]; j++) { + /* cmd buffer stripes */ + kmd_buf = ope_create_stripe_cmd(hw_mgr, ctx_data, + kmd_buf, i, j, stripe_idx, frm_proc); + if (!kmd_buf) + goto end; + + /* WR stripes */ + kmd_buf = ope_create_stripe_wr(ctx_data, stripe_idx, + wr_cdm_info, ope_request, kmd_buf); + if (!kmd_buf) + goto end; + + /* RD stripes */ + kmd_buf = ope_create_stripe_rd(ctx_data, stripe_idx, + rd_cdm_info, ope_request, kmd_buf); + if (!kmd_buf) + goto end; + + /* add go command */ + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + rd_cdm_info->go_cmd_offset, + rd_cdm_info->go_cmd_len); + + CAM_DBG(CAM_OPE, "Go cmd for stripe:%d kmd_buf:%x", + stripe_idx, kmd_buf); + CAM_DBG(CAM_OPE, "iova:%x %pK", + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + + /* wait for RUP done */ + kmd_buf = cdm_ops->cdm_write_wait_comp_event(kmd_buf, + OPE_WAIT_COMP_RUP, 0x0); + CAM_DBG(CAM_OPE, "wait RUP cmd stripe:%d kmd_buf:%x", + stripe_idx, kmd_buf); + stripe_idx++; + } + } +end: + return kmd_buf; +} + +static uint32_t *ope_create_stripes_nrt(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t *kmd_buf, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req, + uint32_t *kmd_buf_offset, uint32_t **cdm_kmd_start_addr) +{ + int i, j; + struct cam_ope_request *ope_request; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + uint32_t stripe_idx = 0; + struct cam_cdm_utils_ops *cdm_ops; + uint32_t len; + int num_nrt_stripes, num_arb; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + num_nrt_stripes = ctx_data->ope_acquire.nrt_stripes_for_arb; + num_arb = ope_request->num_stripes[0] / + ctx_data->ope_acquire.nrt_stripes_for_arb; + if (ope_request->num_stripes[0] % + ctx_data->ope_acquire.nrt_stripes_for_arb) + num_arb++; + CAM_DBG(CAM_OPE, "Number of ARB for snap: %d", num_arb); + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + /* Stripes */ + for (i = 0; i < frm_proc->batch_size; i++) { + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[i]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[i]; + for (j = 0; j < ope_request->num_stripes[i]; j++) { + CAM_DBG(CAM_OPE, "num_nrt_stripes = %d num_arb = %d", + num_nrt_stripes, num_arb); + if (!num_nrt_stripes) { + kmd_buf = cdm_ops->cdm_write_wait_comp_event( + kmd_buf, + OPE_WAIT_COMP_IDLE, 0x0); + len = (kmd_buf - *cdm_kmd_start_addr) * + sizeof(uint32_t); + cam_ope_dev_prepare_cdm_request( + ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, + ope_dev_prepare_req->req_idx, + *kmd_buf_offset, ope_dev_prepare_req, + len, true); + *cdm_kmd_start_addr = kmd_buf; + *kmd_buf_offset += len; + } + /* cmd buffer stripes */ + kmd_buf = ope_create_stripe_cmd(hw_mgr, ctx_data, + kmd_buf, i, j, stripe_idx, frm_proc); + if (!kmd_buf) + goto end; + + /* WR stripes */ + kmd_buf = ope_create_stripe_wr(ctx_data, stripe_idx, + wr_cdm_info, ope_request, kmd_buf); + if (!kmd_buf) + goto end; + + /* RD stripes */ + kmd_buf = ope_create_stripe_rd(ctx_data, stripe_idx, + rd_cdm_info, ope_request, kmd_buf); + if (!kmd_buf) + goto end; + + if (!num_nrt_stripes) { + /* For num_nrt_stripes create CDM BL with ARB */ + /* Add Frame level cmds in this condition */ + /* Frame 0 DB */ + kmd_buf = ope_create_frame_cmd(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_DOUBLE_BUFFERED, + ope_dev_prepare_req); + if (!kmd_buf) + goto end; + + /* Frame 0 SB */ + kmd_buf = ope_create_frame_cmd(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_SINGLE_BUFFERED, + ope_dev_prepare_req); + if (!kmd_buf) + goto end; + + /* Frame 0 WR */ + kmd_buf = ope_create_frame_wr(ctx_data, + wr_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) + goto end; + + /* Frame 0 RD */ + kmd_buf = ope_create_frame_rd(ctx_data, + rd_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) + goto end; + num_arb--; + num_nrt_stripes = + ctx_data->ope_acquire.nrt_stripes_for_arb; + } + // add go command + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + rd_cdm_info->go_cmd_offset, + rd_cdm_info->go_cmd_len); + + CAM_DBG(CAM_OPE, "Go cmd for stripe:%d kmd_buf:%x", + stripe_idx, kmd_buf); + CAM_DBG(CAM_OPE, "iova:%x %pK", + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + + // wait for RUP done + kmd_buf = cdm_ops->cdm_write_wait_comp_event(kmd_buf, + OPE_WAIT_COMP_RUP, 0x0); + CAM_DBG(CAM_OPE, "wait RUP cmd stripe:%d kmd_buf:%x", + stripe_idx, kmd_buf); + stripe_idx++; + num_nrt_stripes--; + } + } +end: + return kmd_buf; +} + +static int cam_ope_dev_create_kmd_buf_nrt(struct cam_ope_hw_mgr *hw_mgr, + struct cam_hw_prepare_update_args *prepare_args, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t kmd_buf_offset, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int rc = 0; + uint32_t len; + struct cam_ope_request *ope_request; + uint32_t *kmd_buf; + uint32_t *cdm_kmd_start_addr; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + struct cam_cdm_utils_ops *cdm_ops; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + + (kmd_buf_offset / sizeof(len)); + cdm_kmd_start_addr = kmd_buf; + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[0]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[0]; + + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + kmd_buf = cdm_ops->cdm_write_clear_comp_event(kmd_buf, + OPE_WAIT_COMP_IDLE|OPE_WAIT_COMP_RUP, 0x0); + + /* Frame 0 DB */ + kmd_buf = ope_create_frame_cmd(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_DOUBLE_BUFFERED, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame 0 SB */ + kmd_buf = ope_create_frame_cmd(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_SINGLE_BUFFERED, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame 0 WR */ + kmd_buf = ope_create_frame_wr(ctx_data, + wr_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame 0 RD */ + kmd_buf = ope_create_frame_rd(ctx_data, + rd_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Stripes */ + kmd_buf = ope_create_stripes_nrt(hw_mgr, ctx_data, req_idx, kmd_buf, + ope_dev_prepare_req, &kmd_buf_offset, &cdm_kmd_start_addr); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Last arbitration if there are odd number of stripes */ + /* wait_idle_irq */ + kmd_buf = cdm_ops->cdm_write_wait_comp_event(kmd_buf, + OPE_WAIT_COMP_IDLE, 0x0); + + /* prepare CDM submit packet */ + len = (kmd_buf - cdm_kmd_start_addr) * sizeof(uint32_t); + cam_ope_dev_prepare_cdm_request(ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, ope_dev_prepare_req->req_idx, + kmd_buf_offset, ope_dev_prepare_req, + len, false); +end: + return rc; +} + +static int cam_ope_dev_create_kmd_buf_batch(struct cam_ope_hw_mgr *hw_mgr, + struct cam_hw_prepare_update_args *prepare_args, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t kmd_buf_offset, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int rc = 0, i; + uint32_t len; + struct cam_ope_request *ope_request; + uint32_t *kmd_buf; + uint32_t *cdm_kmd_start_addr; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + struct cam_cdm_utils_ops *cdm_ops; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + + (kmd_buf_offset / sizeof(len)); + cdm_kmd_start_addr = kmd_buf; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + kmd_buf = cdm_ops->cdm_write_clear_comp_event(kmd_buf, + OPE_WAIT_COMP_IDLE|OPE_WAIT_COMP_RUP, 0x0); + + for (i = 0; i < frm_proc->batch_size; i++) { + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[i]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[i]; + + /* After second batch DB programming add prefecth dis */ + if (i) { + kmd_buf = + cdm_ops->cdm_write_wait_prefetch_disable( + kmd_buf, 0x0, + OPE_WAIT_COMP_IDLE, 0x0); + } + + /* Frame i DB */ + kmd_buf = ope_create_frame_cmd_batch(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_DOUBLE_BUFFERED, i, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame i SB */ + kmd_buf = ope_create_frame_cmd_batch(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_SINGLE_BUFFERED, i, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame i WR */ + kmd_buf = ope_create_frame_wr(ctx_data, + wr_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame i RD */ + kmd_buf = ope_create_frame_rd(ctx_data, + rd_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Stripe level programming for batch i */ + /* Stripes */ + kmd_buf = ope_create_stripes_batch(hw_mgr, ctx_data, req_idx, + kmd_buf, i, ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + } + + /* wait_idle_irq */ + kmd_buf = cdm_ops->cdm_write_wait_comp_event(kmd_buf, + OPE_WAIT_COMP_IDLE, 0x0); + + /* prepare CDM submit packet */ + len = (kmd_buf - cdm_kmd_start_addr) * sizeof(uint32_t); + cam_ope_dev_prepare_cdm_request(ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, ope_dev_prepare_req->req_idx, + kmd_buf_offset, ope_dev_prepare_req, + len, false); + +end: + return rc; +} + +static int cam_ope_dev_create_kmd_buf(struct cam_ope_hw_mgr *hw_mgr, + struct cam_hw_prepare_update_args *prepare_args, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t kmd_buf_offset, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int rc = 0; + uint32_t len; + struct cam_ope_request *ope_request; + uint32_t *kmd_buf; + uint32_t *cdm_kmd_start_addr; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct cam_cdm_utils_ops *cdm_ops; + + + if (ctx_data->ope_acquire.dev_type == OPE_DEV_TYPE_OPE_NRT) { + return cam_ope_dev_create_kmd_buf_nrt( + ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, + ope_dev_prepare_req->req_idx, + ope_dev_prepare_req->kmd_buf_offset, + ope_dev_prepare_req); + } + + if (ctx_data->ope_acquire.batch_size > 1) { + return cam_ope_dev_create_kmd_buf_batch( + ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, + ope_dev_prepare_req->req_idx, + ope_dev_prepare_req->kmd_buf_offset, + ope_dev_prepare_req); + } + + ope_request = ctx_data->req_list[req_idx]; + kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + + (kmd_buf_offset / sizeof(len)); + cdm_kmd_start_addr = kmd_buf; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[0]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[0]; + + + CAM_DBG(CAM_OPE, "kmd_buf:%x req_idx:%d req_id:%lld offset:%d", + kmd_buf, req_idx, ope_request->request_id, kmd_buf_offset); + + kmd_buf = cdm_ops->cdm_write_clear_comp_event(kmd_buf, + OPE_WAIT_COMP_IDLE|OPE_WAIT_COMP_RUP, 0x0); + /* Frame 0 DB */ + kmd_buf = ope_create_frame_cmd(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_DOUBLE_BUFFERED, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame 0 SB */ + kmd_buf = ope_create_frame_cmd(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_SINGLE_BUFFERED, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame 0 WR */ + kmd_buf = ope_create_frame_wr(ctx_data, + wr_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame 0 RD */ + kmd_buf = ope_create_frame_rd(ctx_data, + rd_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Stripes */ + kmd_buf = ope_create_stripes(hw_mgr, ctx_data, req_idx, kmd_buf, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* wait_idle_irq */ + kmd_buf = cdm_ops->cdm_write_wait_comp_event(kmd_buf, + OPE_WAIT_COMP_IDLE, 0x0); + + CAM_DBG(CAM_OPE, "wait for idle IRQ: kmd_buf:%x", kmd_buf); + + /* prepare CDM submit packet */ + len = (kmd_buf - cdm_kmd_start_addr) * sizeof(uint32_t); + CAM_DBG(CAM_OPE, "kmd_start_addr:%x kmdbuf_addr:%x len:%d", + cdm_kmd_start_addr, kmd_buf, len); + cam_ope_dev_prepare_cdm_request( + ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, + ope_dev_prepare_req->req_idx, + ope_dev_prepare_req->kmd_buf_offset, + ope_dev_prepare_req, + len, false); +end: + return rc; +} + +static int cam_ope_dev_process_prepare(struct ope_hw *ope_hw, void *cmd_args) +{ + int rc = 0; + struct cam_ope_dev_prepare_req *ope_dev_prepare_req; + + ope_dev_prepare_req = cmd_args; + + rc = cam_ope_top_process(ope_hw, ope_dev_prepare_req->ctx_data->ctx_id, + OPE_HW_PREPARE, ope_dev_prepare_req); + if (rc) + goto end; + + rc = cam_ope_bus_rd_process(ope_hw, + ope_dev_prepare_req->ctx_data->ctx_id, + OPE_HW_PREPARE, ope_dev_prepare_req); + if (rc) + goto end; + + rc = cam_ope_bus_wr_process(ope_hw, + ope_dev_prepare_req->ctx_data->ctx_id, + OPE_HW_PREPARE, ope_dev_prepare_req); + if (rc) + goto end; + + rc = cam_ope_dev_create_kmd_buf(ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, + ope_dev_prepare_req->req_idx, + ope_dev_prepare_req->kmd_buf_offset, + ope_dev_prepare_req); + +end: + return rc; +} + +static int cam_ope_dev_process_probe(struct ope_hw *ope_hw, + void *cmd_args) +{ + cam_ope_top_process(ope_hw, -1, OPE_HW_PROBE, NULL); + cam_ope_bus_rd_process(ope_hw, -1, OPE_HW_PROBE, NULL); + cam_ope_bus_wr_process(ope_hw, -1, OPE_HW_PROBE, NULL); + + return 0; +} + +static int cam_ope_process_probe(struct ope_hw *ope_hw, + void *cmd_args, bool hfi_en) +{ + struct cam_ope_dev_probe *ope_probe = cmd_args; + + if (!ope_probe->hfi_en) + return cam_ope_dev_process_probe(ope_hw, cmd_args); + + return -EINVAL; +} + +static int cam_ope_process_dump_debug_reg(struct ope_hw *ope_hw, + bool hfi_en) +{ + if (!hfi_en) + return cam_ope_dev_process_dump_debug_reg(ope_hw); + + return -EINVAL; +} + +static int cam_ope_process_reset(struct ope_hw *ope_hw, + void *cmd_args, bool hfi_en) +{ + if (!hfi_en) + return cam_ope_dev_process_reset(ope_hw, cmd_args); + + return -EINVAL; +} + +static int cam_ope_process_release(struct ope_hw *ope_hw, + void *cmd_args, bool hfi_en) +{ + if (!hfi_en) + return cam_ope_dev_process_release(ope_hw, cmd_args); + + return -EINVAL; +} + +static int cam_ope_process_acquire(struct ope_hw *ope_hw, + void *cmd_args, bool hfi_en) +{ + if (!hfi_en) + return cam_ope_dev_process_acquire(ope_hw, cmd_args); + + return -EINVAL; +} + +static int cam_ope_process_prepare(struct ope_hw *ope_hw, + void *cmd_args, bool hfi_en) +{ + if (!hfi_en) + return cam_ope_dev_process_prepare(ope_hw, cmd_args); + + return -EINVAL; +} + +int cam_ope_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_hw_info *ope_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ope_device_core_info *core_info = NULL; + struct ope_hw *ope_hw; + bool hfi_en; + unsigned long flags; + + if (!device_priv) { + CAM_ERR(CAM_OPE, "Invalid args %x for cmd %u", + device_priv, cmd_type); + return -EINVAL; + } + + soc_info = &ope_dev->soc_info; + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_OPE, "soc_info = %x core_info = %x", + soc_info, core_info); + return -EINVAL; + } + + hfi_en = core_info->ope_hw_info->hfi_en; + ope_hw = core_info->ope_hw_info->ope_hw; + if (!ope_hw) { + CAM_ERR(CAM_OPE, "Invalid ope hw info"); + return -EINVAL; + } + + switch (cmd_type) { + case OPE_HW_PROBE: + rc = cam_ope_process_probe(ope_hw, cmd_args, hfi_en); + break; + case OPE_HW_ACQUIRE: + rc = cam_ope_process_acquire(ope_hw, cmd_args, hfi_en); + break; + case OPE_HW_RELEASE: + rc = cam_ope_process_release(ope_hw, cmd_args, hfi_en); + break; + case OPE_HW_PREPARE: + rc = cam_ope_process_prepare(ope_hw, cmd_args, hfi_en); + break; + case OPE_HW_START: + break; + case OPE_HW_STOP: + break; + case OPE_HW_FLUSH: + break; + case OPE_HW_RESET: + rc = cam_ope_process_reset(ope_hw, cmd_args, hfi_en); + break; + case OPE_HW_CLK_UPDATE: { + struct cam_ope_dev_clk_update *clk_upd_cmd = + (struct cam_ope_dev_clk_update *)cmd_args; + + if (core_info->clk_enable == false) { + rc = cam_soc_util_clk_enable_default(soc_info, + CAM_SVS_VOTE); + if (rc) { + CAM_ERR(CAM_OPE, "Clock enable is failed"); + return rc; + } + core_info->clk_enable = true; + } + + rc = cam_ope_update_clk_rate(soc_info, clk_upd_cmd->clk_rate); + if (rc) + CAM_ERR(CAM_OPE, "Failed to update clk: %d", rc); + } + break; + case OPE_HW_CLK_DISABLE: { + if (core_info->clk_enable == true) + cam_soc_util_clk_disable_default(soc_info); + + core_info->clk_enable = false; + } + break; + case OPE_HW_BW_UPDATE: { + struct cam_ope_dev_bw_update *cpas_vote = cmd_args; + + if (!cmd_args) + return -EINVAL; + + rc = cam_ope_caps_vote(core_info, cpas_vote); + if (rc) + CAM_ERR(CAM_OPE, "failed to update bw: %d", rc); + } + break; + case OPE_HW_SET_IRQ_CB: { + struct cam_ope_set_irq_cb *irq_cb = cmd_args; + + if (!cmd_args) { + CAM_ERR(CAM_OPE, "cmd args NULL"); + return -EINVAL; + } + + spin_lock_irqsave(&ope_dev->hw_lock, flags); + core_info->irq_cb.ope_hw_mgr_cb = irq_cb->ope_hw_mgr_cb; + core_info->irq_cb.data = irq_cb->data; + spin_unlock_irqrestore(&ope_dev->hw_lock, flags); + } + break; + case OPE_HW_DUMP_DEBUG: + rc = cam_ope_process_dump_debug_reg(ope_hw, hfi_en); + break; + default: + break; + } + + return rc; +} + +irqreturn_t cam_ope_irq(int irq_num, void *data) +{ + struct cam_hw_info *ope_dev = data; + struct cam_ope_device_core_info *core_info = NULL; + struct ope_hw *ope_hw; + struct cam_ope_irq_data irq_data; + + if (!data) { + CAM_ERR(CAM_OPE, "Invalid cam_dev_info or query_cap args"); + return IRQ_HANDLED; + } + + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + ope_hw = core_info->ope_hw_info->ope_hw; + + irq_data.error = 0; + cam_ope_top_process(ope_hw, 0, OPE_HW_ISR, &irq_data); + cam_ope_bus_rd_process(ope_hw, 0, OPE_HW_ISR, &irq_data); + cam_ope_bus_wr_process(ope_hw, 0, OPE_HW_ISR, &irq_data); + + + spin_lock(&ope_dev->hw_lock); + if (core_info->irq_cb.ope_hw_mgr_cb && core_info->irq_cb.data) + if (irq_data.error) + core_info->irq_cb.ope_hw_mgr_cb(irq_data.error, + core_info->irq_cb.data); + spin_unlock(&ope_dev->hw_lock); + + + return IRQ_HANDLED; +} diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.h b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.h new file mode 100644 index 0000000000000000000000000000000000000000..cc0bfd89fc273379961d78d875b8569f46878926 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_OPE_CORE_H +#define CAM_OPE_CORE_H + +#include +#include +#include +#include +#include +#include +#include "cam_cpas_api.h" +#include "ope_hw.h" +#include "ope_dev_intf.h" +/** + * struct cam_ope_cpas_vote + * @ahb_vote: AHB vote info + * @axi_vote: AXI vote info + * @ahb_vote_valid: Flag for ahb vote data + * @axi_vote_valid: flag for axi vote data + */ +struct cam_ope_cpas_vote { + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote; + uint32_t ahb_vote_valid; + uint32_t axi_vote_valid; +}; + +/** + * struct cam_ope_device_hw_info + * + * @ope_hw: OPE hardware + * @hw_idx: Hardware index + * @ope_cdm_base: Base address of CDM + * @ope_top_base: Base address of top + * @ope_qos_base: Base address of QOS + * @ope_pp_base: Base address of PP + * @ope_bus_rd_base: Base address of RD + * @ope_bus_wr_base: Base address of WM + * @hfi_en: HFI flag enable + * @reserved: Reserved + */ +struct cam_ope_device_hw_info { + struct ope_hw *ope_hw; + uint32_t hw_idx; + void *ope_cdm_base; + void *ope_top_base; + void *ope_qos_base; + void *ope_pp_base; + void *ope_bus_rd_base; + void *ope_bus_wr_base; + bool hfi_en; + uint32_t reserved; +}; + +/** + * struct cam_ope_device_core_info + * + * @ope_hw_info: OPE hardware info + * @hw_version: Hardware version + * @hw_idx: Hardware Index + * @hw_type: Hardware Type + * @cpas_handle: CPAS Handle + * @cpas_start: CPAS start flag + * @clk_enable: Clock enable flag + * @irq_cb: IRQ Callback + */ +struct cam_ope_device_core_info { + struct cam_ope_device_hw_info *ope_hw_info; + uint32_t hw_version; + uint32_t hw_idx; + uint32_t hw_type; + uint32_t cpas_handle; + bool cpas_start; + bool clk_enable; + struct cam_ope_set_irq_cb irq_cb; +}; + + +int cam_ope_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_ope_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_ope_start(void *device_priv, + void *start_args, uint32_t arg_size); +int cam_ope_stop(void *device_priv, + void *stop_args, uint32_t arg_size); +int cam_ope_flush(void *device_priv, + void *flush_args, uint32_t arg_size); +int cam_ope_get_hw_caps(void *device_priv, + void *get_hw_cap_args, uint32_t arg_size); +int cam_ope_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size); +irqreturn_t cam_ope_irq(int irq_num, void *data); + +#endif /* CAM_OPE_CORE_H */ diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..8a5f629e7fd90efacfb804646799461daa29dc1d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "ope_core.h" +#include "ope_soc.h" +#include "cam_hw.h" +#include "ope_hw.h" +#include "cam_hw_intf.h" +#include "cam_io_util.h" +#include "cam_ope_hw_mgr_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "ope_hw_100.h" +#include "ope_dev_intf.h" + +static struct cam_ope_device_hw_info ope_hw_info; +static struct ope_dev_soc ope_soc_info; +EXPORT_SYMBOL(ope_soc_info); + +static struct hw_version_reg ope_hw_version_reg = { + .hw_ver = 0x0, +}; + +static char ope_dev_name[8]; + +static int cam_ope_init_hw_version(struct cam_hw_soc_info *soc_info, + struct cam_ope_device_core_info *core_info) +{ + int rc = 0; + + CAM_DBG(CAM_OPE, "soc_info = %x core_info = %x", + soc_info, core_info); + CAM_DBG(CAM_OPE, "CDM:%x TOP: %x QOS: %x PP: %x RD: %x WR: %x", + soc_info->reg_map[OPE_CDM_BASE].mem_base, + soc_info->reg_map[OPE_TOP_BASE].mem_base, + soc_info->reg_map[OPE_QOS_BASE].mem_base, + soc_info->reg_map[OPE_PP_BASE].mem_base, + soc_info->reg_map[OPE_BUS_RD].mem_base, + soc_info->reg_map[OPE_BUS_WR].mem_base); + CAM_DBG(CAM_OPE, "core: %x", + core_info->ope_hw_info->ope_cdm_base); + + core_info->ope_hw_info->ope_cdm_base = + soc_info->reg_map[OPE_CDM_BASE].mem_base; + core_info->ope_hw_info->ope_top_base = + soc_info->reg_map[OPE_TOP_BASE].mem_base; + core_info->ope_hw_info->ope_qos_base = + soc_info->reg_map[OPE_QOS_BASE].mem_base; + core_info->ope_hw_info->ope_pp_base = + soc_info->reg_map[OPE_PP_BASE].mem_base; + core_info->ope_hw_info->ope_bus_rd_base = + soc_info->reg_map[OPE_BUS_RD].mem_base; + core_info->ope_hw_info->ope_bus_wr_base = + soc_info->reg_map[OPE_BUS_WR].mem_base; + + core_info->hw_version = cam_io_r_mb( + core_info->ope_hw_info->ope_top_base + + ope_hw_version_reg.hw_ver); + + switch (core_info->hw_version) { + case OPE_HW_VER_1_0_0: + case OPE_HW_VER_1_1_0: + core_info->ope_hw_info->ope_hw = &ope_hw_100; + break; + default: + CAM_ERR(CAM_OPE, "Unsupported version : %u", + core_info->hw_version); + rc = -EINVAL; + break; + } + + ope_hw_100.top_reg->base = core_info->ope_hw_info->ope_top_base; + ope_hw_100.bus_rd_reg->base = core_info->ope_hw_info->ope_bus_rd_base; + ope_hw_100.bus_wr_reg->base = core_info->ope_hw_info->ope_bus_wr_base; + ope_hw_100.pp_reg->base = core_info->ope_hw_info->ope_pp_base; + + return rc; +} + +int cam_ope_register_cpas(struct cam_hw_soc_info *soc_info, + struct cam_ope_device_core_info *core_info, + uint32_t hw_idx) +{ + struct cam_cpas_register_params cpas_register_params; + int rc; + + cpas_register_params.dev = &soc_info->pdev->dev; + memcpy(cpas_register_params.identifier, "ope", sizeof("ope")); + cpas_register_params.cam_cpas_client_cb = NULL; + cpas_register_params.cell_index = hw_idx; + cpas_register_params.userdata = NULL; + + rc = cam_cpas_register_client(&cpas_register_params); + if (rc < 0) { + CAM_ERR(CAM_OPE, "failed: %d", rc); + return rc; + } + core_info->cpas_handle = cpas_register_params.client_handle; + + return rc; +} + +int cam_ope_probe(struct platform_device *pdev) +{ + struct cam_hw_intf *ope_dev_intf = NULL; + struct cam_hw_info *ope_dev = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_ope_device_core_info *core_info = NULL; + int rc = 0; + uint32_t hw_idx; + struct cam_ope_dev_probe ope_probe; + struct cam_ope_cpas_vote cpas_vote; + + of_property_read_u32(pdev->dev.of_node, + "cell-index", &hw_idx); + + ope_dev_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!ope_dev_intf) + return -ENOMEM; + + ope_dev_intf->hw_idx = hw_idx; + ope_dev_intf->hw_type = OPE_DEV_OPE; + ope_dev = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!ope_dev) { + rc = -ENOMEM; + goto ope_dev_alloc_failed; + } + + memset(ope_dev_name, 0, sizeof(ope_dev_name)); + snprintf(ope_dev_name, sizeof(ope_dev_name), + "ope%1u", ope_dev_intf->hw_idx); + + ope_dev->soc_info.pdev = pdev; + ope_dev->soc_info.dev = &pdev->dev; + ope_dev->soc_info.dev_name = ope_dev_name; + ope_dev_intf->hw_priv = ope_dev; + ope_dev_intf->hw_ops.init = cam_ope_init_hw; + ope_dev_intf->hw_ops.deinit = cam_ope_deinit_hw; + ope_dev_intf->hw_ops.get_hw_caps = cam_ope_get_hw_caps; + ope_dev_intf->hw_ops.start = cam_ope_start; + ope_dev_intf->hw_ops.stop = cam_ope_stop; + ope_dev_intf->hw_ops.flush = cam_ope_flush; + ope_dev_intf->hw_ops.process_cmd = cam_ope_process_cmd; + + CAM_DBG(CAM_OPE, "type %d index %d", + ope_dev_intf->hw_type, + ope_dev_intf->hw_idx); + + platform_set_drvdata(pdev, ope_dev_intf); + + ope_dev->core_info = kzalloc(sizeof(struct cam_ope_device_core_info), + GFP_KERNEL); + if (!ope_dev->core_info) { + rc = -ENOMEM; + goto ope_core_alloc_failed; + } + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + core_info->ope_hw_info = &ope_hw_info; + ope_dev->soc_info.soc_private = &ope_soc_info; + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + rc = -EINVAL; + CAM_DBG(CAM_OPE, "No ope hardware info"); + goto ope_match_dev_failed; + } + + rc = cam_ope_init_soc_resources(&ope_dev->soc_info, cam_ope_irq, + ope_dev); + if (rc < 0) { + CAM_ERR(CAM_OPE, "failed to init_soc"); + goto init_soc_failed; + } + core_info->hw_type = OPE_DEV_OPE; + core_info->hw_idx = hw_idx; + rc = cam_ope_register_cpas(&ope_dev->soc_info, + core_info, ope_dev_intf->hw_idx); + if (rc < 0) + goto register_cpas_failed; + + rc = cam_ope_enable_soc_resources(&ope_dev->soc_info); + if (rc < 0) { + CAM_ERR(CAM_OPE, "enable soc resorce failed: %d", rc); + goto enable_soc_failed; + } + cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE; + cpas_vote.ahb_vote.vote.level = CAM_SVS_VOTE; + cpas_vote.axi_vote.num_paths = 1; + cpas_vote.axi_vote.axi_path[0].path_data_type = + CAM_AXI_PATH_DATA_OPE_WR_VID; + cpas_vote.axi_vote.axi_path[0].transac_type = + CAM_AXI_TRANSACTION_WRITE; + cpas_vote.axi_vote.axi_path[0].camnoc_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].mnoc_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].mnoc_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].ddr_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].ddr_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + + rc = cam_cpas_start(core_info->cpas_handle, + &cpas_vote.ahb_vote, &cpas_vote.axi_vote); + if (rc) { + CAM_ERR(CAM_OPE, "cam_cpas_start failed, rc=%d", rc); + goto init_hw_failure; + } + + rc = cam_ope_init_hw_version(&ope_dev->soc_info, ope_dev->core_info); + if (rc) + goto init_hw_failure; + + cam_ope_disable_soc_resources(&ope_dev->soc_info, true); + cam_cpas_stop(core_info->cpas_handle); + ope_dev->hw_state = CAM_HW_STATE_POWER_DOWN; + + ope_probe.hfi_en = ope_soc_info.hfi_en; + cam_ope_process_cmd(ope_dev, OPE_HW_PROBE, + &ope_probe, sizeof(ope_probe)); + mutex_init(&ope_dev->hw_mutex); + spin_lock_init(&ope_dev->hw_lock); + init_completion(&ope_dev->hw_complete); + + CAM_DBG(CAM_OPE, "OPE%d probe successful", + ope_dev_intf->hw_idx); + return rc; + +init_hw_failure: +enable_soc_failed: +register_cpas_failed: +init_soc_failed: +ope_match_dev_failed: + kfree(ope_dev->core_info); +ope_core_alloc_failed: + kfree(ope_dev); +ope_dev_alloc_failed: + kfree(ope_dev_intf); + return rc; +} + +static const struct of_device_id cam_ope_dt_match[] = { + { + .compatible = "qcom,ope", + .data = &ope_hw_version_reg, + }, + {} +}; +MODULE_DEVICE_TABLE(of, cam_ope_dt_match); + +static struct platform_driver cam_ope_driver = { + .probe = cam_ope_probe, + .driver = { + .name = "ope", + .of_match_table = cam_ope_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_ope_init_module(void) +{ + return platform_driver_register(&cam_ope_driver); +} + +static void __exit cam_ope_exit_module(void) +{ + platform_driver_unregister(&cam_ope_driver); +} + +module_init(cam_ope_init_module); +module_exit(cam_ope_exit_module); +MODULE_DESCRIPTION("CAM OPE driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h new file mode 100644 index 0000000000000000000000000000000000000000..aeeca5e7bbd9192731f5407b4935f0524780549c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_OPE_DEV_INTF_H +#define CAM_OPE_DEV_INTF_H + +#include +#include "cam_ope_hw_mgr.h" +#include "cam_cdm_intf_api.h" +#include "cam_cpas_api.h" + + +#define OPE_HW_INIT 0x1 +#define OPE_HW_DEINIT 0x2 +#define OPE_HW_ACQUIRE 0x3 +#define OPE_HW_RELEASE 0x4 +#define OPE_HW_START 0x5 +#define OPE_HW_STOP 0x6 +#define OPE_HW_FLUSH 0x7 +#define OPE_HW_PREPARE 0x8 +#define OPE_HW_ISR 0x9 +#define OPE_HW_PROBE 0xA +#define OPE_HW_CLK_UPDATE 0xB +#define OPE_HW_BW_UPDATE 0xC +#define OPE_HW_RESET 0xD +#define OPE_HW_SET_IRQ_CB 0xE +#define OPE_HW_CLK_DISABLE 0xF +#define OPE_HW_CLK_ENABLE 0x10 +#define OPE_HW_DUMP_DEBUG 0x11 + +/** + * struct cam_ope_dev_probe + * + * @hfi_en: HFI enable flag + */ +struct cam_ope_dev_probe { + bool hfi_en; +}; + +/** + * struct cam_ope_dev_init + * + * @hfi_en: HFI enable flag + * @core_info: OPE core info + */ +struct cam_ope_dev_init { + bool hfi_en; + struct cam_ope_device_core_info *core_info; +}; + +/** + * struct cam_ope_dev_clk_update + * + * @clk_rate: Clock rate + */ +struct cam_ope_dev_clk_update { + uint32_t clk_rate; +}; + +/** + * struct cam_ope_dev_bw_update + * + * @ahb_vote: AHB vote info + * @axi_vote: AXI vote info + * @ahb_vote_valid: Flag for ahb vote + * @axi_vote_valid: Flag for axi vote + */ +struct cam_ope_dev_bw_update { + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote; + uint32_t ahb_vote_valid; + uint32_t axi_vote_valid; +}; + +/** + * struct cam_ope_dev_caps + * + * @hw_idx: Hardware index + * @hw_ver: Hardware version info + */ +struct cam_ope_dev_caps { + uint32_t hw_idx; + struct ope_hw_ver hw_ver; +}; + +/** + * struct cam_ope_dev_acquire + * + * @ctx_id: Context id + * @ope_acquire: OPE acquire info + * @bus_wr_ctx: Bus Write context + * @bus_rd_ctx: Bus Read context + */ +struct cam_ope_dev_acquire { + uint32_t ctx_id; + struct ope_acquire_dev_info *ope_acquire; + struct ope_bus_wr_ctx *bus_wr_ctx; + struct ope_bus_rd_ctx *bus_rd_ctx; +}; + +/** + * struct cam_ope_dev_release + * + * @ctx_id: Context id + * @bus_wr_ctx: Bus Write context + * @bus_rd_ctx: Bus Read context + */ +struct cam_ope_dev_release { + uint32_t ctx_id; + struct ope_bus_wr_ctx *bus_wr_ctx; + struct ope_bus_rd_ctx *bus_rd_ctx; +}; + +/** + * struct cam_ope_set_irq_cb + * + * @ope_hw_mgr_cb: Callback to hardware manager + * @data: Private data + */ +struct cam_ope_set_irq_cb { + int32_t (*ope_hw_mgr_cb)(uint32_t irq_status, void *data); + void *data; +}; + +/** + * struct cam_ope_irq_data + * + * @error: IRQ error + */ +struct cam_ope_irq_data { + uint32_t error; +}; + +/** + * struct cam_ope_dev_prepare_req + * + * @hw_mgr: OPE hardware manager + * @packet: Packet + * @prepare_args: Prepare request args + * @ctx_data: Context data + * @wr_cdm_batch: WM request + * @rd_cdm_batch: RD master request + * @frame_process: Frame process command + * @req_idx: Request Index + * @kmd_buf_offset: KMD buffer offset + */ +struct cam_ope_dev_prepare_req { + struct cam_ope_hw_mgr *hw_mgr; + struct cam_packet *packet; + struct cam_hw_prepare_update_args *prepare_args; + struct cam_ope_ctx *ctx_data; + struct ope_bus_wr_io_port_cdm_batch *wr_cdm_batch; + struct ope_bus_rd_io_port_cdm_batch *rd_cdm_batch; + struct ope_frame_process *frame_process; + uint32_t req_idx; + uint32_t kmd_buf_offset; +}; + +int cam_ope_top_process(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t cmd_id, void *data); + +int cam_ope_bus_rd_process(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t cmd_id, void *data); + +int cam_ope_bus_wr_process(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t cmd_id, void *data); + +#endif /* CAM_OPE_DEV_INTF_H */ + diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h new file mode 100644 index 0000000000000000000000000000000000000000..fc188e69546c10b07babbce7ec20a5f514203c81 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h @@ -0,0 +1,426 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_OPE_HW_H +#define CAM_OPE_HW_H + +#define OPE_HW_VER_1_0_0 0x10000000 +#define OPE_HW_VER_1_1_0 0x10010000 + +#define OPE_DEV_OPE 0 +#define OPE_DEV_MAX 1 + +#define MAX_RD_CLIENTS 2 +#define MAX_WR_CLIENTS 8 +#define MAX_PP_CLIENTS 29 + +#define OPE_CDM_BASE 0x0 +#define OPE_TOP_BASE 0x1 +#define OPE_QOS_BASE 0x2 +#define OPE_PP_BASE 0x3 +#define OPE_BUS_RD 0x4 +#define OPE_BUS_WR 0x5 +#define OPE_BASE_MAX 0x6 + + +#define BUS_RD_COMBO_BAYER_MASK 0x1 +#define BUS_RD_COMBO_YUV_MASK 0x2 +#define BUS_RD_COMBO_MAX 0x2 + +#define BUS_RD_BAYER 0x0 +#define BUS_RD_YUV 0x1 + +#define BUS_WR_COMBO_YUV_MASK 0x1 +#define BUS_WR_COMBO_MAX 0x1 + +#define BUS_WR_YUV 0x0 + +#define BUS_WR_VIDEO_Y 0x0 +#define BUS_WR_VIDEO_C 0x1 +#define BUS_WR_DISP_Y 0x2 +#define BUS_WR_DISP_C 0x3 +#define BUS_WR_ARGB 0x4 +#define BUS_WR_STATS_RS 0x5 +#define BUS_WR_STATS_IHIST 0x6 +#define BUS_WR_STATS_LTM 0x7 + +#define OPE_WAIT_COMP_RUP 0x1 +#define OPE_WAIT_COMP_WR_DONE 0x2 +#define OPE_WAIT_COMP_IDLE 0x4 +#define OPE_WAIT_COMP_GEN_IRQ 0x8 + +#define OPE_MAX_DEBUG_REGISTER 30 + +struct cam_ope_common { + uint32_t mode[CAM_FORMAT_MAX]; +}; + +struct cam_ope_top_reg { + void *base; + uint32_t offset; + uint32_t hw_version; + uint32_t reset_cmd; + uint32_t core_clk_cfg_ctrl_0; + uint32_t ahb_clk_cgc_ctrl; + uint32_t core_cfg; + uint32_t irq_status; + uint32_t irq_mask; + uint32_t irq_clear; + uint32_t irq_set; + uint32_t irq_cmd; + uint32_t violation_status; + uint32_t throttle_cnt_cfg; + uint32_t debug_cfg; + uint32_t scratch_reg; + uint32_t num_debug_registers; + struct cam_ope_debug_register *debug_regs; +}; + +struct cam_ope_top_reg_val { + uint32_t hw_version; + uint32_t major_mask; + uint32_t major_shift; + uint32_t minor_mask; + uint32_t minor_shift; + uint32_t incr_mask; + uint32_t incr_shift; + uint32_t irq_mask; + uint32_t irq_set_clear; + uint32_t sw_reset_cmd; + uint32_t hw_reset_cmd; + uint32_t core_clk_cfg_ctrl_0; + uint32_t ahb_clk_cgc_ctrl; + uint32_t input_format; + uint32_t input_format_mask; + uint32_t color_correct_src_sel; + uint32_t color_correct_src_sel_mask; + uint32_t stats_ihist_src_sel; + uint32_t stats_ihist_src_sel_mask; + uint32_t chroma_up_src_sel; + uint32_t chroma_up_src_sel_mask; + uint32_t argb_alpha; + uint32_t argb_alpha_mask; + uint32_t rs_throttle_cnt; + uint32_t rs_throttle_cnt_mask; + uint32_t ihist_throttle_cnt; + uint32_t ihist_throttle_cnt_mask; + uint32_t rst_done; + uint32_t we_done; + uint32_t fe_done; + uint32_t ope_violation; + uint32_t idle; + uint32_t debug_cfg_val; +}; + +struct cam_ope_qos_reg { + void *base; + uint32_t offset; + uint32_t hw_version; + uint32_t hw_status; + uint32_t module_cfg; + uint32_t curve_cfg_0; + uint32_t curve_cfg_1; + uint32_t window_cfg; + uint32_t eos_status_0; + uint32_t eos_status_1; + uint32_t eos_status_2; +}; + +struct cam_ope_qos_reg_val { + uint32_t hw_version; + uint32_t proc_interval; + uint32_t proc_interval_mask; + uint32_t static_health; + uint32_t static_health_mask; + uint32_t module_cfg_en; + uint32_t module_cfg_en_mask; + uint32_t yexp_ymin_dec; + uint32_t yexp_ymin_dec_mask; + uint32_t ymin_inc; + uint32_t ymin_inc_mask; + uint32_t initial_delta; + uint32_t initial_delta_mask; + uint32_t window_cfg; +}; + +struct cam_ope_bus_rd_client_reg { + uint32_t core_cfg; + uint32_t ccif_meta_data; + uint32_t img_addr; + uint32_t img_cfg; + uint32_t stride; + uint32_t unpack_cfg; + uint32_t latency_buf_allocation; + uint32_t misr_cfg_0; + uint32_t misr_cfg_1; + uint32_t misr_rd_val; +}; + +struct cam_ope_bus_rd_reg { + void *base; + uint32_t offset; + uint32_t hw_version; + uint32_t sw_reset; + uint32_t cgc_override; + uint32_t irq_mask; + uint32_t irq_clear; + uint32_t irq_cmd; + uint32_t irq_status; + uint32_t input_if_cmd; + uint32_t irq_set; + uint32_t misr_reset; + uint32_t security_cfg; + uint32_t iso_cfg; + uint32_t iso_seed; + + uint32_t num_clients; + struct cam_ope_bus_rd_client_reg rd_clients[MAX_RD_CLIENTS]; +}; + +struct cam_ope_bus_rd_client_reg_val { + uint32_t core_cfg; + uint32_t stripe_location; + uint32_t stripe_location_mask; + uint32_t stripe_location_shift; + uint32_t pix_pattern; + uint32_t pix_pattern_mask; + uint32_t pix_pattern_shift; + uint32_t img_addr; + uint32_t img_width; + uint32_t img_width_mask; + uint32_t img_width_shift; + uint32_t img_height; + uint32_t img_height_mask; + uint32_t img_height_shift; + uint32_t stride; + uint32_t mode; + uint32_t mode_mask; + uint32_t mode_shift; + uint32_t alignment; + uint32_t alignment_mask; + uint32_t alignment_shift; + uint32_t latency_buf_allocation; + uint32_t misr_cfg_samp_mode; + uint32_t misr_cfg_samp_mode_mask; + uint32_t misr_cfg_en; + uint32_t misr_cfg_en_mask; + uint32_t misr_cfg_1; + uint32_t misr_rd_val; + uint32_t input_port_id; + uint32_t rm_port_id; + uint32_t format_type; + uint32_t num_combos_supported; +}; + +struct cam_ope_bus_rd_reg_val { + uint32_t hw_version; + uint32_t sw_reset; + uint32_t cgc_override; + uint32_t irq_mask; + uint32_t go_cmd; + uint32_t go_cmd_mask; + uint32_t ica_en; + uint32_t ica_en_mask; + uint32_t static_prg; + uint32_t static_prg_mask; + uint32_t go_cmd_sel; + uint32_t go_cmd_sel_mask; + uint32_t fs_sync_en; + uint32_t fs_sync_en_mask; + uint32_t misr_reset; + uint32_t security_cfg; + uint32_t iso_bpp_select; + uint32_t iso_bpp_select_mask; + uint32_t iso_pattern_select; + uint32_t iso_pattern_select_mask; + uint32_t iso_en; + uint32_t iso_en_mask; + uint32_t iso_seed; + uint32_t irq_set_clear; + uint32_t rst_done; + uint32_t rup_done; + uint32_t rd_buf_done; + uint32_t violation; + uint32_t latency_buf_size; + + uint32_t num_clients; + struct cam_ope_bus_rd_client_reg_val rd_clients[MAX_RD_CLIENTS]; +}; + +struct cam_ope_bus_wr_client_reg { + uint32_t core_cfg; + uint32_t img_addr; + uint32_t img_cfg; + uint32_t x_init; + uint32_t stride; + uint32_t pack_cfg; + uint32_t bw_limit; + uint32_t frame_header_addr; + uint32_t subsample_period; + uint32_t subsample_pattern; +}; + +struct cam_ope_bus_wr_reg { + void *base; + uint32_t offset; + uint32_t hw_version; + uint32_t cgc_override; + uint32_t irq_mask_0; + uint32_t irq_mask_1; + uint32_t irq_clear_0; + uint32_t irq_clear_1; + uint32_t irq_status_0; + uint32_t irq_status_1; + uint32_t irq_cmd; + uint32_t frame_header_cfg_0; + uint32_t local_frame_header_cfg_0; + uint32_t irq_set_0; + uint32_t irq_set_1; + uint32_t iso_cfg; + uint32_t violation_status; + uint32_t image_size_violation_status; + uint32_t misr_cfg_0; + uint32_t misr_cfg_1; + uint32_t misr_rd_sel; + uint32_t misr_reset; + uint32_t misr_val; + uint32_t num_clients; + struct cam_ope_bus_wr_client_reg wr_clients[MAX_WR_CLIENTS]; +}; + +struct cam_ope_bus_wr_client_reg_val { + uint32_t core_cfg_en; + uint32_t core_cfg_en_mask; + uint32_t core_cfg_en_shift; + uint32_t virtual_frame_en; + uint32_t virtual_frame_en_mask; + uint32_t virtual_frame_en_shift; + uint32_t frame_header_en; + uint32_t frame_header_en_mask; + uint32_t frame_header_en_shift; + uint32_t auto_recovery_en; + uint32_t auto_recovery_en_mask; + uint32_t auto_recovery_en_shift; + uint32_t mode; + uint32_t mode_mask; + uint32_t mode_shift; + uint32_t img_addr; + uint32_t width; + uint32_t width_mask; + uint32_t width_shift; + uint32_t height; + uint32_t height_mask; + uint32_t height_shift; + uint32_t x_init; + uint32_t stride; + uint32_t format; + uint32_t format_mask; + uint32_t format_shift; + uint32_t alignment; + uint32_t alignment_mask; + uint32_t alignment_shift; + uint32_t bw_limit_en; + uint32_t bw_limit_en_mask; + uint32_t bw_limit_counter; + uint32_t bw_limit_counter_mask; + uint32_t frame_header_addr; + uint32_t subsample_period; + uint32_t subsample_pattern; + uint32_t output_port_id; + uint32_t wm_port_id; + uint32_t format_type; + uint32_t num_combos_supported; +}; + +struct cam_ope_bus_wr_reg_val { + uint32_t hw_version; + uint32_t cgc_override; + uint32_t irq_mask_0; + uint32_t irq_mask_1; + uint32_t irq_set_clear; + uint32_t comp_rup_done; + uint32_t comp_buf_done; + uint32_t cons_violation; + uint32_t violation; + uint32_t img_size_violation; + uint32_t frame_header_cfg_0; + uint32_t local_frame_header_cfg_0; + uint32_t iso_cfg; + uint32_t misr_0_en; + uint32_t misr_0_en_mask; + uint32_t misr_1_en; + uint32_t misr_1_en_mask; + uint32_t misr_2_en; + uint32_t misr_2_en_mask; + uint32_t misr_3_en; + uint32_t misr_3_en_mask; + uint32_t misr_0_samp_mode; + uint32_t misr_0_samp_mode_mask; + uint32_t misr_1_samp_mode; + uint32_t misr_1_samp_mode_mask; + uint32_t misr_2_samp_mode; + uint32_t misr_2_samp_mode_mask; + uint32_t misr_3_samp_mode; + uint32_t misr_3_samp_mode_mask; + uint32_t misr_0_id; + uint32_t misr_0_id_mask; + uint32_t misr_1_id; + uint32_t misr_1_id_mask; + uint32_t misr_2_id; + uint32_t misr_2_id_mask; + uint32_t misr_3_id; + uint32_t misr_3_id_mask; + uint32_t misr_rd_misr_sel; + uint32_t misr_rd_misr_sel_mask; + uint32_t misr_rd_word_sel; + uint32_t misr_rd_word_sel_mask; + uint32_t misr_reset; + uint32_t misr_val; + + + uint32_t num_clients; + struct cam_ope_bus_wr_client_reg_val wr_clients[MAX_WR_CLIENTS]; +}; + +struct cam_ope_debug_register { + uint32_t offset; +}; + +struct cam_ope_bus_pp_client_reg { + uint32_t hw_status; +}; + +struct cam_ope_pp_reg { + void *base; + uint32_t offset; + + uint32_t num_clients; + struct cam_ope_bus_pp_client_reg pp_clients[MAX_PP_CLIENTS]; +}; + +struct ope_hw { + struct cam_ope_top_reg *top_reg; + struct cam_ope_top_reg_val *top_reg_val; + + struct cam_ope_bus_rd_reg *bus_rd_reg; + struct cam_ope_bus_rd_reg_val *bus_rd_reg_val; + + struct cam_ope_bus_wr_reg *bus_wr_reg; + struct cam_ope_bus_wr_reg_val *bus_wr_reg_val; + + struct cam_ope_qos_reg *qos_reg; + struct cam_ope_qos_reg_val *qos_reg_val; + + struct cam_ope_common *common; + + struct cam_ope_pp_reg *pp_reg; +}; + +struct hw_version_reg { + uint32_t hw_ver; + uint32_t reserved; +}; + +#endif /* CAM_OPE_HW_H */ diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h new file mode 100644 index 0000000000000000000000000000000000000000..cdf9c2d64b1146e3b798fb9020d1f2e44e4ddb3e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h @@ -0,0 +1,666 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_OPE_HW_100_H +#define CAM_OPE_HW_100_H + +#define OPE_BUS_RD_TYPE_BAYER 0x0 +#define OPE_BUS_RD_TYPE_YUV_Y 0x0 +#define OPE_BUS_RD_TYPE_YUC_C 0x1 + +#define OPE_BUS_WR_TYPE_VID_Y 0x0 +#define OPE_BUS_WR_TYPE_VID_C 0x1 +#define OPE_BUS_WR_TYPE_DISP_Y 0x2 +#define OPE_BUS_WR_TYPE_DISP_C 0x3 +#define OPE_BUS_WR_TYPE_ARGB 0x4 +#define OPE_BUS_WR_TYPE_RS 0x5 +#define OPE_BUS_WR_TYPE_IHIST 0x6 +#define OPE_BUS_WR_TYPE_LTM 0x7 + +enum cam_ope_bus_rd_unpacker_format { + BUS_RD_VER1_PACKER_FMT_PLAIN_128_BYPASS = 0x0, + BUS_RD_VER1_PACKER_FMT_PLAIN_8 = 0x1, + BUS_RD_VER1_PACKER_FMT_PLAIN_16_10BPP = 0x2, + BUS_RD_VER1_PACKER_FMT_PLAIN_16_12BPP = 0x3, + BUS_RD_VER1_PACKER_FMT_PLAIN_16_14BPP = 0x4, + BUS_RD_VER1_PACKER_FMT_PLAIN_32_20BPP = 0x5, + BUS_RD_VER1_PACKER_FMT_ARGB16_10 = 0x6, + BUS_RD_VER1_PACKER_FMT_ARGB16_12 = 0x7, + BUS_RD_VER1_PACKER_FMT_ARGB16_14 = 0x8, + BUS_RD_VER1_PACKER_FMT_PLAIN_32 = 0x9, + BUS_RD_VER1_PACKER_FMT_PLAIN_64 = 0xA, + BUS_RD_VER1_PACKER_FMT_TP_10 = 0xB, + BUS_RD_VER1_PACKER_FMT_MIPI_8 = 0xC, + BUS_RD_VER1_PACKER_FMT_MIPI_10 = 0xD, + BUS_RD_VER1_PACKER_FMT_MIPI_12 = 0xE, + BUS_RD_VER1_PACKER_FMT_MIPI_14 = 0xF, + BUS_RD_VER1_PACKER_FMT_PLAIN_16_16BPP = 0x10, + BUS_RD_VER1_PACKER_FMT_BYPASS_SWAP = 0x11, + BUS_RD_VER1_PACKER_FMT_PLAIN_8_SWAP = 0x12, + BUS_RD_VER1_PACKER_FMT_MAX = 0x13, +}; + +static struct cam_ope_debug_register ope_debug_regs[OPE_MAX_DEBUG_REGISTER] = { + { + .offset = 0xA0, + }, + { + .offset = 0xA4 + }, + { + .offset = 0xA8, + }, + { + .offset = 0xAC, + }, + { + .offset = 0xB0, + }, + { + .offset = 0xB4, + }, + { + .offset = 0xB8, + }, + { + .offset = 0xBC, + }, + { + .offset = 0xD0, + }, + { + .offset = 0xD4, + }, +}; + +static struct cam_ope_top_reg ope_top_reg = { + .offset = 0x400, + .hw_version = 0x0, + .reset_cmd = 0x4, + .core_clk_cfg_ctrl_0 = 0x8, + .ahb_clk_cgc_ctrl = 0xC, + .core_cfg = 0x10, + .irq_status = 0x14, + .irq_mask = 0x18, + .irq_clear = 0x1C, + .irq_set = 0x20, + .irq_cmd = 0x24, + .violation_status = 0x28, + .throttle_cnt_cfg = 0x2C, + .debug_cfg = 0xDC, + .scratch_reg = 0x1F0, + .num_debug_registers = 10, + .debug_regs = ope_debug_regs, +}; + +static struct cam_ope_top_reg_val ope_top_reg_val = { + .hw_version = 0x10000000, + .major_mask = 0xFFFF, + .major_shift = 0x0, + .minor_mask = 0x0FFF0000, + .minor_shift = 0xF, + .incr_mask = 0xF0000000, + .incr_shift = 0x1B, + .irq_mask = 0x0000000F, + .sw_reset_cmd = 0x2, + .hw_reset_cmd = 0x1, + .irq_set_clear = 0x1, + .rst_done = 0x1, + .we_done = 0x2, + .fe_done = 0x4, + .ope_violation = 0x8, + .idle = 0x10, + .debug_cfg_val = 0x1, +}; + + +static struct cam_ope_bus_rd_reg_val ope_bus_rd_reg_val = { + .hw_version = 0x00050000, + .sw_reset = 0x1, + .cgc_override = 0x0, + .irq_mask = 0x30001, + .irq_set_clear = 0x1, + .rst_done = 0x1, + .rup_done = 0x2, + .rd_buf_done = 0xC, + .violation = 0x3000, + .go_cmd = 0x1, + .security_cfg = 0x0, + .latency_buf_size = 4096, + .num_clients = 0x2, + .rd_clients = { + { + .core_cfg = 0x1, + .stripe_location_mask = 0x3, + .stripe_location_shift = 0x0, + .pix_pattern_mask = 0x3F, + .pix_pattern_shift = 0x2, + .img_width_mask = 0xFFFF, + .img_width_shift = 0x10, + .img_height_mask = 0xFFFF, + .img_height_shift = 0x0, + .mode_mask = 0x1F, + .mode_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x5, + .latency_buf_allocation = 4096, + .input_port_id = OPE_IN_RES_FULL, + .rm_port_id = 0, + .format_type = BUS_RD_COMBO_BAYER_MASK | + BUS_RD_COMBO_YUV_MASK, + .num_combos_supported = 2, + }, + { + .core_cfg = 0x1, + .stripe_location_mask = 0x3, + .stripe_location_shift = 0x0, + .pix_pattern_mask = 0x3F, + .pix_pattern_shift = 0x2, + .img_width_mask = 0xFFFF, + .img_width_shift = 0x10, + .img_height_mask = 0xFFFF, + .img_height_shift = 0x0, + .mode_mask = 0x1F, + .mode_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x5, + .latency_buf_allocation = 4096, + .input_port_id = OPE_IN_RES_FULL, + .rm_port_id = 1, + .format_type = BUS_RD_COMBO_YUV_MASK, + .num_combos_supported = 1, + + }, + }, +}; + +static struct cam_ope_bus_rd_reg ope_bus_rd_reg = { + .offset = 0x4C00, + .hw_version = 0x0, + .sw_reset = 0x4, + .cgc_override = 0x8, + .irq_mask = 0xC, + .irq_clear = 0x10, + .irq_cmd = 0x14, + .irq_status = 0x18, + .input_if_cmd = 0x1C, + .irq_set = 0x20, + .misr_reset = 0x24, + .security_cfg = 0x28, + .iso_cfg = 0x2C, + .iso_seed = 0x30, + .num_clients = 0x2, + .rd_clients = { + { + .core_cfg = 0x50, + .ccif_meta_data = 0x54, + .img_addr = 0x58, + .img_cfg = 0x5C, + .stride = 0x60, + .unpack_cfg = 0x64, + .latency_buf_allocation = 0x78, + .misr_cfg_0 = 0x80, + .misr_cfg_1 = 0x84, + .misr_rd_val = 0x88, + }, + { + .core_cfg = 0xF0, + .ccif_meta_data = 0xF4, + .img_addr = 0xF8, + .img_cfg = 0xFC, + .stride = 0x100, + .unpack_cfg = 0x104, + .latency_buf_allocation = 0x118, + .misr_cfg_0 = 0x120, + .misr_cfg_1 = 0x124, + .misr_rd_val = 0x128, + }, + }, +}; + +static struct cam_ope_bus_wr_reg ope_bus_wr_reg = { + .offset = 0x4D90, + .hw_version = 0x0, + .cgc_override = 0x8, + .irq_mask_0 = 0x18, + .irq_mask_1 = 0x1C, + .irq_clear_0 = 0x20, + .irq_clear_1 = 0x24, + .irq_status_0 = 0x28, + .irq_status_1 = 0x2C, + .irq_cmd = 0x30, + .frame_header_cfg_0 = 0x34, + .local_frame_header_cfg_0 = 0x4C, + .irq_set_0 = 0x50, + .irq_set_1 = 0x54, + .iso_cfg = 0x5C, + .violation_status = 0x64, + .image_size_violation_status = 0x70, + .misr_cfg_0 = 0xB8, + .misr_cfg_1 = 0xBC, + .misr_rd_sel = 0xC8, + .misr_reset = 0xCC, + .misr_val = 0xD0, + .num_clients = 0x8, + .wr_clients = { + { + .core_cfg = 0x200, + .img_addr = 0x204, + .img_cfg = 0x20C, + .x_init = 0x210, + .stride = 0x214, + .pack_cfg = 0x218, + .bw_limit = 0x21C, + .frame_header_addr = 0x220, + .subsample_period = 0x230, + .subsample_pattern = 0x234, + }, + { + .core_cfg = 0x300, + .img_addr = 0x304, + .img_cfg = 0x30C, + .x_init = 0x310, + .stride = 0x314, + .pack_cfg = 0x318, + .bw_limit = 0x31C, + .frame_header_addr = 0x320, + .subsample_period = 0x330, + .subsample_pattern = 0x334, + }, + { + .core_cfg = 0x400, + .img_addr = 0x404, + .img_cfg = 0x40C, + .x_init = 0x410, + .stride = 0x414, + .pack_cfg = 0x418, + .bw_limit = 0x41C, + .frame_header_addr = 0x420, + .subsample_period = 0x430, + .subsample_pattern = 0x434, + }, + { + .core_cfg = 0x500, + .img_addr = 0x504, + .img_cfg = 0x50C, + .x_init = 0x510, + .stride = 0x514, + .pack_cfg = 0x518, + .bw_limit = 0x51C, + .frame_header_addr = 0x520, + .subsample_period = 0x530, + .subsample_pattern = 0x534, + }, + { + .core_cfg = 0x600, + .img_addr = 0x604, + .img_cfg = 0x60C, + .x_init = 0x610, + .stride = 0x614, + .pack_cfg = 0x618, + .bw_limit = 0x61C, + .frame_header_addr = 0x620, + .subsample_period = 0x630, + .subsample_pattern = 0x634, + }, + { + .core_cfg = 0x700, + .img_addr = 0x704, + .img_cfg = 0x70C, + .x_init = 0x710, + .stride = 0x714, + .pack_cfg = 0x718, + .bw_limit = 0x71C, + .frame_header_addr = 0x720, + .subsample_period = 0x730, + .subsample_pattern = 0x734, + }, + { + .core_cfg = 0x800, + .img_addr = 0x804, + .img_cfg = 0x80C, + .x_init = 0x810, + .stride = 0x814, + .pack_cfg = 0x818, + .bw_limit = 0x81C, + .frame_header_addr = 0x820, + .subsample_period = 0x830, + .subsample_pattern = 0x834, + }, + { + .core_cfg = 0x900, + .img_addr = 0x904, + .img_cfg = 0x90C, + .x_init = 0x910, + .stride = 0x914, + .pack_cfg = 0x918, + .bw_limit = 0x91C, + .frame_header_addr = 0x920, + .subsample_period = 0x930, + .subsample_pattern = 0x934, + }, + }, +}; + +static struct cam_ope_bus_wr_reg_val ope_bus_wr_reg_val = { + .hw_version = 0x20010000, + .irq_mask_0 = 0xD0000000, + .irq_mask_1 = 0x0, + .irq_set_clear = 0x1, + .comp_rup_done = 0x1, + .comp_buf_done = 0x100, + .cons_violation = 0x10000000, + .violation = 0x40000000, + .img_size_violation = 0x80000000, + .num_clients = 0x8, + .wr_clients = { + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_VIDEO, + .wm_port_id = BUS_WR_VIDEO_Y, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_VIDEO, + .wm_port_id = BUS_WR_VIDEO_C, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_DISP, + .wm_port_id = BUS_WR_DISP_Y, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_DISP, + .wm_port_id = BUS_WR_DISP_C, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_ARGB, + .wm_port_id = BUS_WR_ARGB, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_STATS_RS, + .wm_port_id = BUS_WR_STATS_RS, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_STATS_IHIST, + .wm_port_id = BUS_WR_STATS_IHIST, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_STATS_LTM, + .wm_port_id = BUS_WR_STATS_LTM, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + }, +}; + +static struct cam_ope_pp_reg ope_pp_reg = { + .offset = 0x800, + .num_clients = MAX_PP_CLIENTS, + .pp_clients = { + { + .hw_status = 0x4, + }, + { + .hw_status = 0x204, + }, + { + .hw_status = 0x404, + }, + { + .hw_status = 0x604, + }, + { + .hw_status = 0x804, + }, + { + .hw_status = 0xA04, + }, + { + .hw_status = 0xC04, + }, + { + .hw_status = 0xE04, + }, + { + .hw_status = 0x1004, + }, + { + .hw_status = 0x1204, + }, + { + .hw_status = 0x1404, + }, + { + .hw_status = 0x1604, + }, + { + .hw_status = 0x1804, + }, + { + .hw_status = 0x1A04, + }, + { + .hw_status = 0x1C04, + }, + { + .hw_status = 0x1E04, + }, + { + .hw_status = 0x2204, + }, + { + .hw_status = 0x2604, + }, + { + .hw_status = 0x2804, + }, + { + .hw_status = 0x2A04, + }, + { + .hw_status = 0x2C04, + }, + { + .hw_status = 0x2E04, + }, + { + .hw_status = 0x3004, + }, + { + .hw_status = 0x3204, + }, + { + .hw_status = 0x3404, + }, + { + .hw_status = 0x3604, + }, + { + .hw_status = 0x3804, + }, + { + .hw_status = 0x3A04, + }, + { + .hw_status = 0x3C04, + }, + }, +}; + +static struct ope_hw ope_hw_100 = { + .top_reg = &ope_top_reg, + .top_reg_val = &ope_top_reg_val, + .bus_rd_reg = &ope_bus_rd_reg, + .bus_rd_reg_val = &ope_bus_rd_reg_val, + .bus_wr_reg = &ope_bus_wr_reg, + .bus_wr_reg_val = &ope_bus_wr_reg_val, + .pp_reg = &ope_pp_reg, +}; + +#endif /* CAM_OPE_HW_100_H */ diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.c b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..0fbd46a73b7048d830b3a7427a96fbbb9339a8cf --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "ope_soc.h" +#include "cam_soc_util.h" +#include "cam_debug_util.h" + + +static int cam_ope_get_dt_properties(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct platform_device *pdev = NULL; + struct device_node *of_node = NULL; + struct ope_dev_soc *ope_soc_info; + + if (!soc_info) { + CAM_ERR(CAM_OPE, "soc_info is NULL"); + return -EINVAL; + } + + pdev = soc_info->pdev; + of_node = pdev->dev.of_node; + ope_soc_info = soc_info->soc_private; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) + CAM_ERR(CAM_OPE, "get ope dt prop is failed: %d", rc); + + ope_soc_info->hfi_en = of_property_read_bool(of_node, "hfi_en"); + + return rc; +} + +static int cam_ope_request_platform_resource( + struct cam_hw_soc_info *soc_info, + irq_handler_t ope_irq_handler, void *irq_data) +{ + int rc = 0; + + rc = cam_soc_util_request_platform_resource(soc_info, ope_irq_handler, + irq_data); + + return rc; +} + +int cam_ope_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t ope_irq_handler, void *irq_data) +{ + int rc = 0; + + rc = cam_ope_get_dt_properties(soc_info); + if (rc < 0) + return rc; + + rc = cam_ope_request_platform_resource(soc_info, ope_irq_handler, + irq_data); + if (rc < 0) + return rc; + + return rc; +} + +int cam_ope_enable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_SVS_VOTE, true); + if (rc) { + CAM_ERR(CAM_OPE, "enable platform failed"); + return rc; + } + + return rc; +} + +int cam_ope_disable_soc_resources(struct cam_hw_soc_info *soc_info, + bool disable_clk) +{ + int rc = 0; + + rc = cam_soc_util_disable_platform_resource(soc_info, disable_clk, + true); + if (rc) + CAM_ERR(CAM_OPE, "enable platform failed"); + + return rc; +} + +int cam_ope_update_clk_rate(struct cam_hw_soc_info *soc_info, + uint32_t clk_rate) +{ + int32_t src_clk_idx; + + if (!soc_info) { + CAM_ERR(CAM_OPE, "Invalid soc info"); + return -EINVAL; + } + + src_clk_idx = soc_info->src_clk_idx; + + CAM_DBG(CAM_OPE, "clk_rate = %u src_clk_index = %d", + clk_rate, src_clk_idx); + if ((soc_info->clk_level_valid[CAM_TURBO_VOTE] == true) && + (soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx] != 0) && + (clk_rate > soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx])) { + CAM_DBG(CAM_OPE, "clk_rate %d greater than max, reset to %d", + clk_rate, + soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]); + clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]; + } + + CAM_DBG(CAM_OPE, "clk_rate = %u src_clk_index = %d", + clk_rate, src_clk_idx); + return cam_soc_util_set_src_clk_rate(soc_info, clk_rate); +} + +int cam_ope_toggle_clk(struct cam_hw_soc_info *soc_info, bool clk_enable) +{ + int rc = 0; + + if (clk_enable) + rc = cam_soc_util_clk_enable_default(soc_info, CAM_SVS_VOTE); + else + cam_soc_util_clk_disable_default(soc_info); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.h b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..4582f19bf42449406dbd813a3e39b7a7baeb84fd --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_OPE_SOC_H +#define CAM_OPE_SOC_H + +#include "cam_soc_util.h" + +/** + * struct ope_dev_soc + * + * @hfi_en: HFI enable flag + */ +struct ope_dev_soc { + uint32_t hfi_en; +}; + +int cam_ope_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t ope_irq_handler, void *irq_data); + + +int cam_ope_enable_soc_resources(struct cam_hw_soc_info *soc_info); + +int cam_ope_disable_soc_resources(struct cam_hw_soc_info *soc_info, + bool disable_clk); + +int cam_ope_update_clk_rate(struct cam_hw_soc_info *soc_info, + uint32_t clk_rate); + +int cam_ope_toggle_clk(struct cam_hw_soc_info *soc_info, bool clk_enable); +#endif /* CAM_OPE_SOC_H */ diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top/Makefile b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..a0f431f10b41de257171cd8443447abc5912e3ee --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += ope_top.o diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c new file mode 100644 index 0000000000000000000000000000000000000000..35f4d85e96328770ef8f1e07568750ae020cbb7c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_io_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "ope_core.h" +#include "ope_soc.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "ope_hw.h" +#include "ope_dev_intf.h" +#include "ope_top.h" + +static struct ope_top ope_top_info; + +static int cam_ope_top_dump_debug_reg(struct ope_hw *ope_hw_info) +{ + uint32_t i, val[3]; + struct cam_ope_top_reg *top_reg; + + top_reg = ope_hw_info->top_reg; + for (i = 0; i < top_reg->num_debug_registers; i = i+3) { + val[0] = cam_io_r_mb(top_reg->base + + top_reg->debug_regs[i].offset); + val[1] = ((i+1) < top_reg->num_debug_registers) ? + cam_io_r_mb(top_reg->base + + top_reg->debug_regs[i+1].offset) : 0; + val[2] = ((i+2) < top_reg->num_debug_registers) ? + cam_io_r_mb(top_reg->base + + top_reg->debug_regs[i+2].offset) : 0; + + CAM_INFO(CAM_OPE, "status[%d-%d] : 0x%x 0x%x 0x%x", + i, i+2, val[0], val[1], val[2]); + } + + CAM_INFO(CAM_OPE, "scrath reg: 0x%x, stripe_idx: %d", + top_reg->offset + top_reg->scratch_reg, + cam_io_r_mb(top_reg->base + top_reg->scratch_reg)); + return 0; +} + +static int cam_ope_top_reset(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + struct cam_ope_top_reg *top_reg; + struct cam_ope_top_reg_val *top_reg_val; + uint32_t irq_mask, irq_status; + unsigned long flags; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + top_reg = ope_hw_info->top_reg; + top_reg_val = ope_hw_info->top_reg_val; + + mutex_lock(&ope_top_info.ope_hw_mutex); + reinit_completion(&ope_top_info.reset_complete); + + /* enable interrupt mask */ + cam_io_w_mb(top_reg_val->irq_mask, + ope_hw_info->top_reg->base + top_reg->irq_mask); + + /* OPE SW RESET */ + cam_io_w_mb(top_reg_val->sw_reset_cmd, + ope_hw_info->top_reg->base + top_reg->reset_cmd); + + rc = wait_for_completion_timeout( + &ope_top_info.reset_complete, + msecs_to_jiffies(60)); + + cam_io_w_mb(top_reg_val->debug_cfg_val, + top_reg->base + top_reg->debug_cfg); + + if (!rc || rc < 0) { + spin_lock_irqsave(&ope_top_info.hw_lock, flags); + if (!completion_done(&ope_top_info.reset_complete)) { + CAM_DBG(CAM_OPE, + "IRQ delayed, checking the status registers"); + irq_mask = cam_io_r_mb(ope_hw_info->top_reg->base + + top_reg->irq_mask); + irq_status = cam_io_r_mb(ope_hw_info->top_reg->base + + top_reg->irq_status); + if (irq_status & top_reg_val->rst_done) { + CAM_DBG(CAM_OPE, "ope reset done"); + cam_io_w_mb(irq_status, + top_reg->base + top_reg->irq_clear); + cam_io_w_mb(top_reg_val->irq_set_clear, + top_reg->base + top_reg->irq_cmd); + } else { + CAM_ERR(CAM_OPE, + "irq mask 0x%x irq status 0x%x", + irq_mask, irq_status); + cam_ope_top_dump_debug_reg(ope_hw_info); + rc = -ETIMEDOUT; + } + } else { + rc = 0; + } + spin_unlock_irqrestore(&ope_top_info.hw_lock, flags); + } else { + rc = 0; + } + + /* enable interrupt mask */ + cam_io_w_mb(top_reg_val->irq_mask, + ope_hw_info->top_reg->base + top_reg->irq_mask); + + mutex_unlock(&ope_top_info.ope_hw_mutex); + return rc; +} + +static int cam_ope_top_release(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + + if (ctx_id < 0) { + CAM_ERR(CAM_OPE, "Invalid data: %d", ctx_id); + return -EINVAL; + } + + ope_top_info.top_ctx[ctx_id].ope_acquire = NULL; + + return rc; +} + +static int cam_ope_top_acquire(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + + if (ctx_id < 0 || !data) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, data); + return -EINVAL; + } + + ope_top_info.top_ctx[ctx_id].ope_acquire = data; + + return rc; +} + +static int cam_ope_top_init(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + struct cam_ope_top_reg *top_reg; + struct cam_ope_top_reg_val *top_reg_val; + struct cam_ope_dev_init *dev_init = data; + uint32_t irq_mask, irq_status; + unsigned long flags; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + top_reg = ope_hw_info->top_reg; + top_reg_val = ope_hw_info->top_reg_val; + + top_reg->base = dev_init->core_info->ope_hw_info->ope_top_base; + + mutex_init(&ope_top_info.ope_hw_mutex); + /* OPE SW RESET */ + init_completion(&ope_top_info.reset_complete); + + /* enable interrupt mask */ + cam_io_w_mb(top_reg_val->irq_mask, + ope_hw_info->top_reg->base + top_reg->irq_mask); + cam_io_w_mb(top_reg_val->sw_reset_cmd, + ope_hw_info->top_reg->base + top_reg->reset_cmd); + + rc = wait_for_completion_timeout( + &ope_top_info.reset_complete, + msecs_to_jiffies(60)); + + cam_io_w_mb(top_reg_val->debug_cfg_val, + top_reg->base + top_reg->debug_cfg); + + if (!rc || rc < 0) { + spin_lock_irqsave(&ope_top_info.hw_lock, flags); + if (!completion_done(&ope_top_info.reset_complete)) { + CAM_DBG(CAM_OPE, + "IRQ delayed, checking the status registers"); + irq_mask = cam_io_r_mb(ope_hw_info->top_reg->base + + top_reg->irq_mask); + irq_status = cam_io_r_mb(ope_hw_info->top_reg->base + + top_reg->irq_status); + if (irq_status & top_reg_val->rst_done) { + CAM_DBG(CAM_OPE, "ope reset done"); + cam_io_w_mb(irq_status, + top_reg->base + top_reg->irq_clear); + cam_io_w_mb(top_reg_val->irq_set_clear, + top_reg->base + top_reg->irq_cmd); + } else { + CAM_ERR(CAM_OPE, + "irq mask 0x%x irq status 0x%x", + irq_mask, irq_status); + cam_ope_top_dump_debug_reg(ope_hw_info); + rc = -ETIMEDOUT; + } + } else { + CAM_DBG(CAM_OPE, "reset done"); + rc = 0; + } + spin_unlock_irqrestore(&ope_top_info.hw_lock, flags); + } else { + rc = 0; + } + /* enable interrupt mask */ + cam_io_w_mb(top_reg_val->irq_mask, + ope_hw_info->top_reg->base + top_reg->irq_mask); + + return rc; +} + +static int cam_ope_top_probe(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + ope_top_info.ope_hw_info = ope_hw_info; + spin_lock_init(&ope_top_info.hw_lock); + + return rc; +} + +static int cam_ope_top_isr(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + uint32_t irq_status; + uint32_t violation_status; + uint32_t pp_hw_status = 0; + struct cam_ope_top_reg *top_reg; + struct cam_ope_top_reg_val *top_reg_val; + struct cam_ope_pp_reg *pp_reg; + struct cam_ope_irq_data *irq_data = data; + int i; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + top_reg = ope_hw_info->top_reg; + top_reg_val = ope_hw_info->top_reg_val; + pp_reg = ope_hw_info->pp_reg; + + spin_lock(&ope_top_info.hw_lock); + /* Read and Clear Top Interrupt status */ + irq_status = cam_io_r_mb(top_reg->base + top_reg->irq_status); + cam_io_w_mb(irq_status, + top_reg->base + top_reg->irq_clear); + + cam_io_w_mb(top_reg_val->irq_set_clear, + top_reg->base + top_reg->irq_cmd); + + if (irq_status & top_reg_val->rst_done) { + CAM_DBG(CAM_OPE, "ope reset done"); + complete(&ope_top_info.reset_complete); + } + + if (irq_status & top_reg_val->ope_violation) { + violation_status = cam_io_r_mb(top_reg->base + + top_reg->violation_status); + irq_data->error = 1; + CAM_ERR(CAM_OPE, "ope violation: %x", violation_status); + + for (i = 0; i < pp_reg->num_clients ; i++) { + pp_hw_status = 0; + pp_hw_status = + cam_io_r_mb(pp_reg->base + + pp_reg->pp_clients[i] + .hw_status); + + if (pp_hw_status) + CAM_ERR(CAM_OPE, + "ope pp hw_status offset 0x%x val 0x%x", + pp_reg->pp_clients[i].hw_status, + pp_hw_status); + } + } + spin_unlock(&ope_top_info.hw_lock); + + return rc; +} + +int cam_ope_top_process(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t cmd_id, void *data) +{ + int rc = 0; + + switch (cmd_id) { + case OPE_HW_PROBE: + CAM_DBG(CAM_OPE, "OPE_HW_PROBE: E"); + rc = cam_ope_top_probe(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_PROBE: X"); + break; + case OPE_HW_INIT: + CAM_DBG(CAM_OPE, "OPE_HW_INIT: E"); + rc = cam_ope_top_init(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_INIT: X"); + break; + case OPE_HW_DEINIT: + break; + case OPE_HW_ACQUIRE: + CAM_DBG(CAM_OPE, "OPE_HW_ACQUIRE: E"); + rc = cam_ope_top_acquire(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_ACQUIRE: X"); + break; + case OPE_HW_PREPARE: + break; + case OPE_HW_RELEASE: + rc = cam_ope_top_release(ope_hw_info, ctx_id, data); + break; + case OPE_HW_START: + break; + case OPE_HW_STOP: + break; + case OPE_HW_FLUSH: + break; + case OPE_HW_ISR: + rc = cam_ope_top_isr(ope_hw_info, 0, data); + break; + case OPE_HW_RESET: + rc = cam_ope_top_reset(ope_hw_info, 0, 0); + break; + case OPE_HW_DUMP_DEBUG: + rc - cam_ope_top_dump_debug_reg(ope_hw_info); + default: + break; + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h new file mode 100644 index 0000000000000000000000000000000000000000..57d90712bdebb76255c85797bb4746a3eb445a73 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef OPE_TOP_H +#define OPE_TOP_H + +#include +#include +#include +#include "ope_hw.h" +#include "cam_hw_mgr_intf.h" +#include "cam_hw_intf.h" +#include "cam_soc_util.h" +#include "cam_context.h" +#include "cam_ope_context.h" +#include "cam_ope_hw_mgr.h" + +/** + * struct ope_top_ctx + * + * @ope_acquire: OPE acquire info + */ +struct ope_top_ctx { + struct ope_acquire_dev_info *ope_acquire; +}; + +/** + * struct ope_top + * + * @ope_hw_info: OPE hardware info + * @top_ctx: OPE top context + * @reset_complete: Reset complete flag + * @ope_mutex: OPE hardware mutex + * @hw_lock: OPE hardware spinlock + */ +struct ope_top { + struct ope_hw *ope_hw_info; + struct ope_top_ctx top_ctx[OPE_CTX_MAX]; + struct completion reset_complete; + struct mutex ope_hw_mutex; + spinlock_t hw_lock; +}; +#endif /* OPE_TOP_H */ diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/Makefile b/techpack/camera-bengal/drivers/cam_req_mgr/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..542648a28b31b2b53b31da3c77b1cf1c707176ee --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/ + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_req_mgr_core.o\ + cam_req_mgr_dev.o \ + cam_req_mgr_util.o \ + cam_req_mgr_workq.o \ + cam_mem_mgr.o \ + cam_req_mgr_timer.o \ + cam_req_mgr_debug.o diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_mem_mgr.c b/techpack/camera-bengal/drivers/cam_req_mgr/cam_mem_mgr.c new file mode 100644 index 0000000000000000000000000000000000000000..9d7b68921e8f428c1cc7738912d238e587e591a1 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_mem_mgr.c @@ -0,0 +1,1513 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cam_req_mgr_util.h" +#include "cam_mem_mgr.h" +#include "cam_smmu_api.h" +#include "cam_debug_util.h" +#include "cam_trace.h" +#include "cam_common_util.h" + +static struct cam_mem_table tbl; +static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED); + +static int cam_mem_util_get_dma_dir(uint32_t flags) +{ + int rc = -EINVAL; + + if (flags & CAM_MEM_FLAG_HW_READ_ONLY) + rc = DMA_TO_DEVICE; + else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY) + rc = DMA_FROM_DEVICE; + else if (flags & CAM_MEM_FLAG_HW_READ_WRITE) + rc = DMA_BIDIRECTIONAL; + else if (flags & CAM_MEM_FLAG_PROTECTED_MODE) + rc = DMA_BIDIRECTIONAL; + + return rc; +} + +static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf, + uintptr_t *vaddr, + size_t *len) +{ + int i, j, rc; + void *addr; + + /* + * dma_buf_begin_cpu_access() and dma_buf_end_cpu_access() + * need to be called in pair to avoid stability issue. + */ + rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL); + if (rc) { + CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc); + return rc; + } + + /* + * Code could be simplified if ION support of dma_buf_vmap is + * available. This workaround takes the avandaage that ion_alloc + * returns a virtually contiguous memory region, so we just need + * to _kmap each individual page and then only use the virtual + * address returned from the first call to _kmap. + */ + for (i = 0; i < PAGE_ALIGN(dmabuf->size) / PAGE_SIZE; i++) { + addr = dma_buf_kmap(dmabuf, i); + if (IS_ERR_OR_NULL(addr)) { + CAM_ERR(CAM_MEM, "kernel map fail"); + for (j = 0; j < i; j++) + dma_buf_kunmap(dmabuf, + j, + (void *)(*vaddr + (j * PAGE_SIZE))); + *vaddr = 0; + *len = 0; + rc = -ENOSPC; + goto fail; + } + if (i == 0) + *vaddr = (uint64_t)addr; + } + + *len = dmabuf->size; + + return 0; + +fail: + dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL); + return rc; +} +static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf, + uint64_t vaddr) +{ + int i, rc = 0, page_num; + + if (!dmabuf || !vaddr) { + CAM_ERR(CAM_MEM, "Invalid input args %pK %llX", dmabuf, vaddr); + return -EINVAL; + } + + page_num = PAGE_ALIGN(dmabuf->size) / PAGE_SIZE; + + for (i = 0; i < page_num; i++) { + dma_buf_kunmap(dmabuf, i, + (void *)(vaddr + (i * PAGE_SIZE))); + } + + /* + * dma_buf_begin_cpu_access() and + * dma_buf_end_cpu_access() need to be called in pair + * to avoid stability issue. + */ + rc = dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL); + if (rc) { + CAM_ERR(CAM_MEM, "Failed in end cpu access, dmabuf=%pK", + dmabuf); + return rc; + } + + return rc; +} + +static int cam_mem_mgr_create_debug_fs(void) +{ + tbl.dentry = debugfs_create_dir("camera_memmgr", NULL); + if (!tbl.dentry) { + CAM_ERR(CAM_MEM, "failed to create dentry"); + return -ENOMEM; + } + + if (!debugfs_create_bool("alloc_profile_enable", + 0644, + tbl.dentry, + &tbl.alloc_profile_enable)) { + CAM_ERR(CAM_MEM, + "failed to create alloc_profile_enable"); + goto err; + } + + return 0; +err: + debugfs_remove_recursive(tbl.dentry); + return -ENOMEM; +} + +int cam_mem_mgr_init(void) +{ + int i; + int bitmap_size; + + memset(tbl.bufq, 0, sizeof(tbl.bufq)); + + bitmap_size = BITS_TO_LONGS(CAM_MEM_BUFQ_MAX) * sizeof(long); + tbl.bitmap = kzalloc(bitmap_size, GFP_KERNEL); + if (!tbl.bitmap) + return -ENOMEM; + + tbl.bits = bitmap_size * BITS_PER_BYTE; + bitmap_zero(tbl.bitmap, tbl.bits); + /* We need to reserve slot 0 because 0 is invalid */ + set_bit(0, tbl.bitmap); + + for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) { + tbl.bufq[i].fd = -1; + tbl.bufq[i].buf_handle = -1; + } + mutex_init(&tbl.m_lock); + + atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED); + + cam_mem_mgr_create_debug_fs(); + + return 0; +} + +static int32_t cam_mem_get_slot(void) +{ + int32_t idx; + + mutex_lock(&tbl.m_lock); + idx = find_first_zero_bit(tbl.bitmap, tbl.bits); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { + mutex_unlock(&tbl.m_lock); + return -ENOMEM; + } + + set_bit(idx, tbl.bitmap); + tbl.bufq[idx].active = true; + mutex_init(&tbl.bufq[idx].q_lock); + mutex_unlock(&tbl.m_lock); + + return idx; +} + +static void cam_mem_put_slot(int32_t idx) +{ + mutex_lock(&tbl.m_lock); + mutex_lock(&tbl.bufq[idx].q_lock); + tbl.bufq[idx].active = false; + mutex_unlock(&tbl.bufq[idx].q_lock); + mutex_destroy(&tbl.bufq[idx].q_lock); + clear_bit(idx, tbl.bitmap); + mutex_unlock(&tbl.m_lock); +} + +int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle, + dma_addr_t *iova_ptr, size_t *len_ptr) +{ + int rc = 0, idx; + + *len_ptr = 0; + + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + + idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) + return -ENOENT; + + if (!tbl.bufq[idx].active) + return -EAGAIN; + + mutex_lock(&tbl.bufq[idx].q_lock); + if (buf_handle != tbl.bufq[idx].buf_handle) { + rc = -EINVAL; + goto handle_mismatch; + } + + if (CAM_MEM_MGR_IS_SECURE_HDL(buf_handle)) + rc = cam_smmu_get_stage2_iova(mmu_handle, + tbl.bufq[idx].fd, + iova_ptr, + len_ptr); + else + rc = cam_smmu_get_iova(mmu_handle, + tbl.bufq[idx].fd, + iova_ptr, + len_ptr); + if (rc) { + CAM_ERR(CAM_MEM, + "fail to map buf_hdl:0x%x, mmu_hdl: 0x%x for fd:%d", + buf_handle, mmu_handle, tbl.bufq[idx].fd); + goto handle_mismatch; + } + + CAM_DBG(CAM_MEM, + "handle:0x%x fd:%d iova_ptr:%pK len_ptr:%llu", + mmu_handle, tbl.bufq[idx].fd, iova_ptr, *len_ptr); +handle_mismatch: + mutex_unlock(&tbl.bufq[idx].q_lock); + return rc; +} +EXPORT_SYMBOL(cam_mem_get_io_buf); + +int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len) +{ + int idx; + + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + + if (!buf_handle || !vaddr_ptr || !len) + return -EINVAL; + + idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle); + + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) + return -EINVAL; + + if (!tbl.bufq[idx].active) + return -EPERM; + + if (buf_handle != tbl.bufq[idx].buf_handle) { + CAM_ERR(CAM_MEM, "idx: %d Invalid buf handle %d", + idx, buf_handle); + return -EINVAL; + } + + if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)) { + CAM_ERR(CAM_MEM, "idx: %d Invalid flag 0x%x", + idx, tbl.bufq[idx].flags); + return -EINVAL; + } + + if (tbl.bufq[idx].kmdvaddr && + kref_get_unless_zero(&tbl.bufq[idx].krefcount)) { + *vaddr_ptr = tbl.bufq[idx].kmdvaddr; + *len = tbl.bufq[idx].len; + } else { + CAM_ERR(CAM_MEM, + "No KMD access request, vddr= %p, idx= %d, handle= %d", + tbl.bufq[idx].kmdvaddr, idx, buf_handle); + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(cam_mem_get_cpu_buf); + +int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd) +{ + int rc = 0, idx; + uint32_t cache_dir; + unsigned long dmabuf_flag = 0; + + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + + if (!cmd) + return -EINVAL; + + idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) + return -EINVAL; + + mutex_lock(&tbl.bufq[idx].q_lock); + + if (!tbl.bufq[idx].active) { + rc = -EINVAL; + goto end; + } + + if (cmd->buf_handle != tbl.bufq[idx].buf_handle) { + rc = -EINVAL; + goto end; + } + + rc = dma_buf_get_flags(tbl.bufq[idx].dma_buf, &dmabuf_flag); + if (rc) { + CAM_ERR(CAM_MEM, "cache get flags failed %d", rc); + goto end; + } + + if (dmabuf_flag & ION_FLAG_CACHED) { + switch (cmd->mem_cache_ops) { + case CAM_MEM_CLEAN_CACHE: + cache_dir = DMA_TO_DEVICE; + break; + case CAM_MEM_INV_CACHE: + cache_dir = DMA_FROM_DEVICE; + break; + case CAM_MEM_CLEAN_INV_CACHE: + cache_dir = DMA_BIDIRECTIONAL; + break; + default: + CAM_ERR(CAM_MEM, + "invalid cache ops :%d", cmd->mem_cache_ops); + rc = -EINVAL; + goto end; + } + } else { + CAM_DBG(CAM_MEM, "BUF is not cached"); + goto end; + } + + rc = dma_buf_begin_cpu_access(tbl.bufq[idx].dma_buf, + (cmd->mem_cache_ops == CAM_MEM_CLEAN_INV_CACHE) ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE); + if (rc) { + CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc); + goto end; + } + + rc = dma_buf_end_cpu_access(tbl.bufq[idx].dma_buf, + cache_dir); + if (rc) { + CAM_ERR(CAM_MEM, "dma end access failed rc=%d", rc); + goto end; + } + +end: + mutex_unlock(&tbl.bufq[idx].q_lock); + return rc; +} +EXPORT_SYMBOL(cam_mem_mgr_cache_ops); + +static int cam_mem_util_get_dma_buf(size_t len, + unsigned int heap_id_mask, + unsigned int flags, + struct dma_buf **buf) +{ + int rc = 0; + + if (!buf) { + CAM_ERR(CAM_MEM, "Invalid params"); + return -EINVAL; + } + + *buf = ion_alloc(len, heap_id_mask, flags); + if (IS_ERR_OR_NULL(*buf)) + return -ENOMEM; + + return rc; +} + +static int cam_mem_util_get_dma_buf_fd(size_t len, + size_t align, + unsigned int heap_id_mask, + unsigned int flags, + struct dma_buf **buf, + int *fd) +{ + int rc = 0; + struct timespec64 ts1, ts2; + long microsec = 0; + + if (!buf || !fd) { + CAM_ERR(CAM_MEM, "Invalid params, buf=%pK, fd=%pK", buf, fd); + return -EINVAL; + } + + if (tbl.alloc_profile_enable) + CAM_GET_TIMESTAMP(ts1); + + *buf = ion_alloc(len, heap_id_mask, flags); + if (IS_ERR_OR_NULL(*buf)) + return -ENOMEM; + /* + * increment the ref count so that ref count becomes 2 here + * when we close fd, refcount becomes 1 and when we do + * dmap_put_buf, ref count becomes 0 and memory will be freed. + */ + get_dma_buf(*buf); + + *fd = dma_buf_fd(*buf, O_CLOEXEC); + if (*fd < 0) { + CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd); + rc = -EINVAL; + goto get_fd_fail; + } + + if (tbl.alloc_profile_enable) { + CAM_GET_TIMESTAMP(ts2); + CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec); + trace_cam_log_event("IONAllocProfile", "size and time in micro", + len, microsec); + } + + return rc; + +get_fd_fail: + dma_buf_put(*buf); + return rc; +} + +static int cam_mem_util_ion_alloc(struct cam_mem_mgr_alloc_cmd *cmd, + struct dma_buf **dmabuf, + int *fd) +{ + uint32_t heap_id; + uint32_t ion_flag = 0; + int rc; + + if ((cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) && + (cmd->flags & CAM_MEM_FLAG_CDSP_OUTPUT)) { + heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID); + ion_flag |= + ION_FLAG_SECURE | ION_FLAG_CP_CAMERA | ION_FLAG_CP_CDSP; + } else if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) { + heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID); + ion_flag |= ION_FLAG_SECURE | ION_FLAG_CP_CAMERA; + } else { + heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) | + ION_HEAP(ION_CAMERA_HEAP_ID); + } + + if (cmd->flags & CAM_MEM_FLAG_CACHE) + ion_flag |= ION_FLAG_CACHED; + else + ion_flag &= ~ION_FLAG_CACHED; + + rc = cam_mem_util_get_dma_buf_fd(cmd->len, + cmd->align, + heap_id, + ion_flag, + dmabuf, + fd); + + return rc; +} + + +static int cam_mem_util_check_alloc_flags(struct cam_mem_mgr_alloc_cmd *cmd) +{ + if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) { + CAM_ERR(CAM_MEM, "Num of mmu hdl exceeded maximum(%d)", + CAM_MEM_MMU_MAX_HANDLE); + return -EINVAL; + } + + if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE && + cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) { + CAM_ERR(CAM_MEM, "Kernel mapping in secure mode not allowed"); + return -EINVAL; + } + + return 0; +} + +static int cam_mem_util_check_map_flags(struct cam_mem_mgr_map_cmd *cmd) +{ + if (!cmd->flags) { + CAM_ERR(CAM_MEM, "Invalid flags"); + return -EINVAL; + } + + if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) { + CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)", + cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE); + return -EINVAL; + } + + if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE && + cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) { + CAM_ERR(CAM_MEM, + "Kernel mapping in secure mode not allowed, flags=0x%x", + cmd->flags); + return -EINVAL; + } + + if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) { + CAM_ERR(CAM_MEM, + "Shared memory buffers are not allowed to be mapped"); + return -EINVAL; + } + + return 0; +} + +static int cam_mem_util_map_hw_va(uint32_t flags, + int32_t *mmu_hdls, + int32_t num_hdls, + int fd, + dma_addr_t *hw_vaddr, + size_t *len, + enum cam_smmu_region_id region) +{ + int i; + int rc = -1; + int dir = cam_mem_util_get_dma_dir(flags); + bool dis_delayed_unmap = false; + + if (dir < 0) { + CAM_ERR(CAM_MEM, "fail to map DMA direction, dir=%d", dir); + return dir; + } + + if (flags & CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP) + dis_delayed_unmap = true; + + CAM_DBG(CAM_MEM, + "map_hw_va : fd = %d, flags = 0x%x, dir=%d, num_hdls=%d", + fd, flags, dir, num_hdls); + + if (flags & CAM_MEM_FLAG_PROTECTED_MODE) { + for (i = 0; i < num_hdls; i++) { + rc = cam_smmu_map_stage2_iova(mmu_hdls[i], + fd, + dir, + hw_vaddr, + len); + + if (rc < 0) { + CAM_ERR(CAM_MEM, + "Failed to securely map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, rc=%d", + i, fd, dir, mmu_hdls[i], rc); + goto multi_map_fail; + } + } + } else { + for (i = 0; i < num_hdls; i++) { + rc = cam_smmu_map_user_iova(mmu_hdls[i], + fd, + dis_delayed_unmap, + dir, + (dma_addr_t *)hw_vaddr, + len, + region); + + if (rc < 0) { + CAM_ERR(CAM_MEM, + "Failed to map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, region=%d, rc=%d", + i, fd, dir, mmu_hdls[i], region, rc); + goto multi_map_fail; + } + } + } + + return rc; +multi_map_fail: + if (flags & CAM_MEM_FLAG_PROTECTED_MODE) + for (--i; i > 0; i--) + cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd); + else + for (--i; i > 0; i--) + cam_smmu_unmap_user_iova(mmu_hdls[i], + fd, + CAM_SMMU_REGION_IO); + return rc; + +} + +int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) +{ + int rc; + int32_t idx; + struct dma_buf *dmabuf = NULL; + int fd = -1; + dma_addr_t hw_vaddr = 0; + size_t len; + uintptr_t kvaddr = 0; + size_t klen; + + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + + if (!cmd) { + CAM_ERR(CAM_MEM, " Invalid argument"); + return -EINVAL; + } + len = cmd->len; + + rc = cam_mem_util_check_alloc_flags(cmd); + if (rc) { + CAM_ERR(CAM_MEM, "Invalid flags: flags = 0x%X, rc=%d", + cmd->flags, rc); + return rc; + } + + rc = cam_mem_util_ion_alloc(cmd, + &dmabuf, + &fd); + if (rc) { + CAM_ERR(CAM_MEM, + "Ion Alloc failed, len=%llu, align=%llu, flags=0x%x, num_hdl=%d", + cmd->len, cmd->align, cmd->flags, cmd->num_hdl); + return rc; + } + + idx = cam_mem_get_slot(); + if (idx < 0) { + CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx); + rc = -ENOMEM; + goto slot_fail; + } + + if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) || + (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) || + (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) { + + enum cam_smmu_region_id region; + + if (cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) + region = CAM_SMMU_REGION_IO; + + + if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) + region = CAM_SMMU_REGION_SHARED; + + if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) + region = CAM_SMMU_REGION_SECHEAP; + + rc = cam_mem_util_map_hw_va(cmd->flags, + cmd->mmu_hdls, + cmd->num_hdl, + fd, + &hw_vaddr, + &len, + region); + + if (rc) { + CAM_ERR(CAM_MEM, + "Failed in map_hw_va, len=%llu, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d", + len, cmd->flags, fd, region, + cmd->num_hdl, rc); + goto map_hw_fail; + } + } + + mutex_lock(&tbl.bufq[idx].q_lock); + tbl.bufq[idx].fd = fd; + tbl.bufq[idx].dma_buf = NULL; + tbl.bufq[idx].flags = cmd->flags; + tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, fd); + if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) + CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true); + + if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) { + rc = cam_mem_util_map_cpu_va(dmabuf, &kvaddr, &klen); + if (rc) { + CAM_ERR(CAM_MEM, "dmabuf: %pK mapping failed: %d", + dmabuf, rc); + goto map_kernel_fail; + } + } + + if (cmd->flags & CAM_MEM_FLAG_KMD_DEBUG_FLAG) + tbl.dbg_buf_idx = idx; + + tbl.bufq[idx].kmdvaddr = kvaddr; + tbl.bufq[idx].vaddr = hw_vaddr; + tbl.bufq[idx].dma_buf = dmabuf; + tbl.bufq[idx].len = len; + tbl.bufq[idx].num_hdl = cmd->num_hdl; + memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls, + sizeof(int32_t) * cmd->num_hdl); + tbl.bufq[idx].is_imported = false; + kref_init(&tbl.bufq[idx].krefcount); + tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_USER; + mutex_unlock(&tbl.bufq[idx].q_lock); + + cmd->out.buf_handle = tbl.bufq[idx].buf_handle; + cmd->out.fd = tbl.bufq[idx].fd; + cmd->out.vaddr = 0; + + CAM_DBG(CAM_MEM, + "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu", + cmd->out.fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle, + tbl.bufq[idx].len); + + return rc; + +map_kernel_fail: + mutex_unlock(&tbl.bufq[idx].q_lock); +map_hw_fail: + cam_mem_put_slot(idx); +slot_fail: + dma_buf_put(dmabuf); + return rc; +} + +int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd) +{ + int32_t idx; + int rc; + struct dma_buf *dmabuf; + dma_addr_t hw_vaddr = 0; + size_t len = 0; + + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + + if (!cmd || (cmd->fd < 0)) { + CAM_ERR(CAM_MEM, "Invalid argument"); + return -EINVAL; + } + + if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) { + CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)", + cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE); + return -EINVAL; + } + + rc = cam_mem_util_check_map_flags(cmd); + if (rc) { + CAM_ERR(CAM_MEM, "Invalid flags: flags = %X", cmd->flags); + return rc; + } + + dmabuf = dma_buf_get(cmd->fd); + if (IS_ERR_OR_NULL((void *)(dmabuf))) { + CAM_ERR(CAM_MEM, "Failed to import dma_buf fd"); + return -EINVAL; + } + + if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) || + (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) { + rc = cam_mem_util_map_hw_va(cmd->flags, + cmd->mmu_hdls, + cmd->num_hdl, + cmd->fd, + &hw_vaddr, + &len, + CAM_SMMU_REGION_IO); + if (rc) { + CAM_ERR(CAM_MEM, + "Failed in map_hw_va, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d", + cmd->flags, cmd->fd, CAM_SMMU_REGION_IO, + cmd->num_hdl, rc); + goto map_fail; + } + } + + idx = cam_mem_get_slot(); + if (idx < 0) { + rc = -ENOMEM; + goto map_fail; + } + + mutex_lock(&tbl.bufq[idx].q_lock); + tbl.bufq[idx].fd = cmd->fd; + tbl.bufq[idx].dma_buf = NULL; + tbl.bufq[idx].flags = cmd->flags; + tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, cmd->fd); + if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE) + CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true); + tbl.bufq[idx].kmdvaddr = 0; + + if (cmd->num_hdl > 0) + tbl.bufq[idx].vaddr = hw_vaddr; + else + tbl.bufq[idx].vaddr = 0; + + tbl.bufq[idx].dma_buf = dmabuf; + tbl.bufq[idx].len = len; + tbl.bufq[idx].num_hdl = cmd->num_hdl; + memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls, + sizeof(int32_t) * cmd->num_hdl); + tbl.bufq[idx].is_imported = true; + kref_init(&tbl.bufq[idx].krefcount); + tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_USER; + mutex_unlock(&tbl.bufq[idx].q_lock); + + cmd->out.buf_handle = tbl.bufq[idx].buf_handle; + cmd->out.vaddr = 0; + + CAM_DBG(CAM_MEM, + "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu", + cmd->fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle, + tbl.bufq[idx].len); + + return rc; + +map_fail: + dma_buf_put(dmabuf); + return rc; +} + +static int cam_mem_util_unmap_hw_va(int32_t idx, + enum cam_smmu_region_id region, + enum cam_smmu_mapping_client client) +{ + int i; + uint32_t flags; + int32_t *mmu_hdls; + int num_hdls; + int fd; + int rc = 0; + + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { + CAM_ERR(CAM_MEM, "Incorrect index"); + return -EINVAL; + } + + flags = tbl.bufq[idx].flags; + mmu_hdls = tbl.bufq[idx].hdls; + num_hdls = tbl.bufq[idx].num_hdl; + fd = tbl.bufq[idx].fd; + + CAM_DBG(CAM_MEM, + "unmap_hw_va : idx=%d, fd=%x, flags=0x%x, num_hdls=%d, client=%d", + idx, fd, flags, num_hdls, client); + + if (flags & CAM_MEM_FLAG_PROTECTED_MODE) { + for (i = 0; i < num_hdls; i++) { + rc = cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd); + if (rc < 0) { + CAM_ERR(CAM_MEM, + "Failed in secure unmap, i=%d, fd=%d, mmu_hdl=%d, rc=%d", + i, fd, mmu_hdls[i], rc); + goto unmap_end; + } + } + } else { + for (i = 0; i < num_hdls; i++) { + if (client == CAM_SMMU_MAPPING_USER) { + rc = cam_smmu_unmap_user_iova(mmu_hdls[i], + fd, region); + } else if (client == CAM_SMMU_MAPPING_KERNEL) { + rc = cam_smmu_unmap_kernel_iova(mmu_hdls[i], + tbl.bufq[idx].dma_buf, region); + } else { + CAM_ERR(CAM_MEM, + "invalid caller for unmapping : %d", + client); + rc = -EINVAL; + } + if (rc < 0) { + CAM_ERR(CAM_MEM, + "Failed in unmap, i=%d, fd=%d, mmu_hdl=%d, region=%d, rc=%d", + i, fd, mmu_hdls[i], region, rc); + goto unmap_end; + } + } + } + + return rc; + +unmap_end: + CAM_ERR(CAM_MEM, "unmapping failed"); + return rc; +} + +static void cam_mem_mgr_unmap_active_buf(int idx) +{ + enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED; + + if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) + region = CAM_SMMU_REGION_SHARED; + else if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) + region = CAM_SMMU_REGION_IO; + + cam_mem_util_unmap_hw_va(idx, region, CAM_SMMU_MAPPING_USER); +} + +static int cam_mem_mgr_cleanup_table(void) +{ + int i; + + mutex_lock(&tbl.m_lock); + for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) { + if (!tbl.bufq[i].active) { + CAM_DBG(CAM_MEM, + "Buffer inactive at idx=%d, continuing", i); + continue; + } else { + CAM_DBG(CAM_MEM, + "Active buffer at idx=%d, possible leak needs unmapping", + i); + cam_mem_mgr_unmap_active_buf(i); + } + + mutex_lock(&tbl.bufq[i].q_lock); + if (tbl.bufq[i].dma_buf) { + dma_buf_put(tbl.bufq[i].dma_buf); + tbl.bufq[i].dma_buf = NULL; + } + tbl.bufq[i].fd = -1; + tbl.bufq[i].flags = 0; + tbl.bufq[i].buf_handle = -1; + tbl.bufq[i].vaddr = 0; + tbl.bufq[i].len = 0; + memset(tbl.bufq[i].hdls, 0, + sizeof(int32_t) * tbl.bufq[i].num_hdl); + tbl.bufq[i].num_hdl = 0; + tbl.bufq[i].dma_buf = NULL; + tbl.bufq[i].active = false; + mutex_unlock(&tbl.bufq[i].q_lock); + mutex_destroy(&tbl.bufq[i].q_lock); + } + + bitmap_zero(tbl.bitmap, tbl.bits); + /* We need to reserve slot 0 because 0 is invalid */ + set_bit(0, tbl.bitmap); + mutex_unlock(&tbl.m_lock); + + return 0; +} + +void cam_mem_mgr_deinit(void) +{ + atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED); + cam_mem_mgr_cleanup_table(); + mutex_lock(&tbl.m_lock); + bitmap_zero(tbl.bitmap, tbl.bits); + kfree(tbl.bitmap); + tbl.bitmap = NULL; + tbl.dbg_buf_idx = -1; + mutex_unlock(&tbl.m_lock); + mutex_destroy(&tbl.m_lock); +} + +static void cam_mem_util_unmap(struct kref *kref) +{ + int rc = 0; + int32_t idx; + enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED; + enum cam_smmu_mapping_client client; + struct cam_mem_buf_queue *bufq = + container_of(kref, typeof(*bufq), krefcount); + + idx = CAM_MEM_MGR_GET_HDL_IDX(bufq->buf_handle); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { + CAM_ERR(CAM_MEM, "Incorrect index"); + return; + } + + client = tbl.bufq[idx].smmu_mapping_client; + + CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx); + + mutex_lock(&tbl.m_lock); + if ((!tbl.bufq[idx].active) && + (tbl.bufq[idx].vaddr) == 0) { + CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,", + idx); + mutex_unlock(&tbl.m_lock); + return; + } + + if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) { + if (tbl.bufq[idx].dma_buf && tbl.bufq[idx].kmdvaddr) { + rc = cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf, + tbl.bufq[idx].kmdvaddr); + if (rc) + CAM_ERR(CAM_MEM, + "Failed, dmabuf=%pK, kmdvaddr=%pK", + tbl.bufq[idx].dma_buf, + (void *) tbl.bufq[idx].kmdvaddr); + } + } + + /* SHARED flag gets precedence, all other flags after it */ + if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) { + region = CAM_SMMU_REGION_SHARED; + } else { + if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) + region = CAM_SMMU_REGION_IO; + } + + if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) || + (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) || + (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) { + if (cam_mem_util_unmap_hw_va(idx, region, client)) + CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK", + tbl.bufq[idx].dma_buf); + if (client == CAM_SMMU_MAPPING_KERNEL) + tbl.bufq[idx].dma_buf = NULL; + } + + mutex_lock(&tbl.bufq[idx].q_lock); + tbl.bufq[idx].flags = 0; + tbl.bufq[idx].buf_handle = -1; + tbl.bufq[idx].vaddr = 0; + memset(tbl.bufq[idx].hdls, 0, + sizeof(int32_t) * CAM_MEM_MMU_MAX_HANDLE); + + CAM_DBG(CAM_MEM, + "Ion buf at idx = %d freeing fd = %d, imported %d, dma_buf %pK", + idx, tbl.bufq[idx].fd, + tbl.bufq[idx].is_imported, + tbl.bufq[idx].dma_buf); + + if (tbl.bufq[idx].dma_buf) + dma_buf_put(tbl.bufq[idx].dma_buf); + + tbl.bufq[idx].fd = -1; + tbl.bufq[idx].dma_buf = NULL; + tbl.bufq[idx].is_imported = false; + tbl.bufq[idx].len = 0; + tbl.bufq[idx].num_hdl = 0; + tbl.bufq[idx].active = false; + mutex_unlock(&tbl.bufq[idx].q_lock); + mutex_destroy(&tbl.bufq[idx].q_lock); + clear_bit(idx, tbl.bitmap); + mutex_unlock(&tbl.m_lock); + +} + +void cam_mem_put_cpu_buf(int32_t buf_handle) +{ + int rc = 0; + int idx; + + if (!buf_handle) { + CAM_ERR(CAM_MEM, "Invalid buf_handle"); + return; + } + + idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { + CAM_ERR(CAM_MEM, "idx: %d not valid", idx); + return; + } + + if (!tbl.bufq[idx].active) { + CAM_ERR(CAM_MEM, "idx: %d not active", idx); + rc = -EPERM; + return; + } + + if (buf_handle != tbl.bufq[idx].buf_handle) { + CAM_ERR(CAM_MEM, "idx: %d Invalid buf handle %d", + idx, buf_handle); + rc = -EINVAL; + return; + } + + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + CAM_DBG(CAM_MEM, + "Called unmap from here, buf_handle: %u, idx: %d", + buf_handle, idx); + +} +EXPORT_SYMBOL(cam_mem_put_cpu_buf); + + +int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd) +{ + int idx; + int rc = 0; + + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + + if (!cmd) { + CAM_ERR(CAM_MEM, "Invalid argument"); + return -EINVAL; + } + + idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { + CAM_ERR(CAM_MEM, "Incorrect index %d extracted from mem handle", + idx); + return -EINVAL; + } + + if (!tbl.bufq[idx].active) { + CAM_ERR(CAM_MEM, "Released buffer state should be active"); + return -EINVAL; + } + + if (tbl.bufq[idx].buf_handle != cmd->buf_handle) { + CAM_ERR(CAM_MEM, + "Released buf handle %d not matching within table %d, idx=%d", + cmd->buf_handle, tbl.bufq[idx].buf_handle, idx); + return -EINVAL; + } + + CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx); + + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + CAM_DBG(CAM_MEM, + "Called unmap from here, buf_handle: %u, idx: %d", + cmd->buf_handle, idx); + + return rc; +} + +int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp, + struct cam_mem_mgr_memory_desc *out) +{ + struct dma_buf *buf = NULL; + int ion_fd = -1; + int rc = 0; + uint32_t heap_id; + int32_t ion_flag = 0; + uintptr_t kvaddr; + dma_addr_t iova = 0; + size_t request_len = 0; + uint32_t mem_handle; + int32_t idx; + int32_t smmu_hdl = 0; + int32_t num_hdl = 0; + + enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED; + + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + + if (!inp || !out) { + CAM_ERR(CAM_MEM, "Invalid params"); + return -EINVAL; + } + + if (!(inp->flags & CAM_MEM_FLAG_HW_READ_WRITE || + inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS || + inp->flags & CAM_MEM_FLAG_CACHE)) { + CAM_ERR(CAM_MEM, "Invalid flags for request mem"); + return -EINVAL; + } + + if (inp->flags & CAM_MEM_FLAG_CACHE) + ion_flag |= ION_FLAG_CACHED; + else + ion_flag &= ~ION_FLAG_CACHED; + + heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) | + ION_HEAP(ION_CAMERA_HEAP_ID); + + rc = cam_mem_util_get_dma_buf(inp->size, + heap_id, + ion_flag, + &buf); + + if (rc) { + CAM_ERR(CAM_MEM, "ION alloc failed for shared buffer"); + goto ion_fail; + } else { + CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf); + } + + /* + * we are mapping kva always here, + * update flags so that we do unmap properly + */ + inp->flags |= CAM_MEM_FLAG_KMD_ACCESS; + rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len); + if (rc) { + CAM_ERR(CAM_MEM, "Failed to get kernel vaddr"); + goto map_fail; + } + + if (!inp->smmu_hdl) { + CAM_ERR(CAM_MEM, "Invalid SMMU handle"); + rc = -EINVAL; + goto smmu_fail; + } + + /* SHARED flag gets precedence, all other flags after it */ + if (inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) { + region = CAM_SMMU_REGION_SHARED; + } else { + if (inp->flags & CAM_MEM_FLAG_HW_READ_WRITE) + region = CAM_SMMU_REGION_IO; + } + + rc = cam_smmu_map_kernel_iova(inp->smmu_hdl, + buf, + CAM_SMMU_MAP_RW, + &iova, + &request_len, + region); + + if (rc < 0) { + CAM_ERR(CAM_MEM, "SMMU mapping failed"); + goto smmu_fail; + } + + smmu_hdl = inp->smmu_hdl; + num_hdl = 1; + + idx = cam_mem_get_slot(); + if (idx < 0) { + rc = -ENOMEM; + goto slot_fail; + } + + mutex_lock(&tbl.bufq[idx].q_lock); + mem_handle = GET_MEM_HANDLE(idx, ion_fd); + tbl.bufq[idx].dma_buf = buf; + tbl.bufq[idx].fd = -1; + tbl.bufq[idx].flags = inp->flags; + tbl.bufq[idx].buf_handle = mem_handle; + tbl.bufq[idx].kmdvaddr = kvaddr; + + tbl.bufq[idx].vaddr = iova; + + tbl.bufq[idx].len = inp->size; + tbl.bufq[idx].num_hdl = num_hdl; + memcpy(tbl.bufq[idx].hdls, &smmu_hdl, + sizeof(int32_t)); + tbl.bufq[idx].is_imported = false; + kref_init(&tbl.bufq[idx].krefcount); + tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_KERNEL; + mutex_unlock(&tbl.bufq[idx].q_lock); + + out->kva = kvaddr; + out->iova = (uint32_t)iova; + out->smmu_hdl = smmu_hdl; + out->mem_handle = mem_handle; + out->len = inp->size; + out->region = region; + + return rc; +slot_fail: + cam_smmu_unmap_kernel_iova(inp->smmu_hdl, + buf, region); +smmu_fail: + cam_mem_util_unmap_cpu_va(buf, kvaddr); +map_fail: + dma_buf_put(buf); +ion_fail: + return rc; +} +EXPORT_SYMBOL(cam_mem_mgr_request_mem); + +int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp) +{ + int32_t idx; + int rc = 0; + + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + + if (!inp) { + CAM_ERR(CAM_MEM, "Invalid argument"); + return -EINVAL; + } + + idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { + CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle"); + return -EINVAL; + } + + if (!tbl.bufq[idx].active) { + if (tbl.bufq[idx].vaddr == 0) { + CAM_ERR(CAM_MEM, "buffer is released already"); + return 0; + } + CAM_ERR(CAM_MEM, "Released buffer state should be active"); + return -EINVAL; + } + + if (tbl.bufq[idx].buf_handle != inp->mem_handle) { + CAM_ERR(CAM_MEM, + "Released buf handle not matching within table"); + return -EINVAL; + } + + CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle); + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + CAM_DBG(CAM_MEM, + "Called unmap from here, buf_handle: %u, idx: %d", + tbl.bufq[idx].buf_handle, idx); + else + rc = -EINVAL; + + return rc; +} +EXPORT_SYMBOL(cam_mem_mgr_release_mem); + +int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp, + enum cam_smmu_region_id region, + struct cam_mem_mgr_memory_desc *out) +{ + struct dma_buf *buf = NULL; + int rc = 0; + int ion_fd = -1; + uint32_t heap_id; + dma_addr_t iova = 0; + size_t request_len = 0; + uint32_t mem_handle; + int32_t idx; + int32_t smmu_hdl = 0; + int32_t num_hdl = 0; + + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + + if (!inp || !out) { + CAM_ERR(CAM_MEM, "Invalid param(s)"); + return -EINVAL; + } + + if (!inp->smmu_hdl) { + CAM_ERR(CAM_MEM, "Invalid SMMU handle"); + return -EINVAL; + } + + if (region != CAM_SMMU_REGION_SECHEAP) { + CAM_ERR(CAM_MEM, "Only secondary heap supported"); + return -EINVAL; + } + + heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) | + ION_HEAP(ION_CAMERA_HEAP_ID); + rc = cam_mem_util_get_dma_buf(inp->size, + heap_id, + 0, + &buf); + + if (rc) { + CAM_ERR(CAM_MEM, "ION alloc failed for sec heap buffer"); + goto ion_fail; + } else { + CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf); + } + + rc = cam_smmu_reserve_sec_heap(inp->smmu_hdl, + buf, + &iova, + &request_len); + + if (rc) { + CAM_ERR(CAM_MEM, "Reserving secondary heap failed"); + goto smmu_fail; + } + + smmu_hdl = inp->smmu_hdl; + num_hdl = 1; + + idx = cam_mem_get_slot(); + if (idx < 0) { + rc = -ENOMEM; + goto slot_fail; + } + + mutex_lock(&tbl.bufq[idx].q_lock); + mem_handle = GET_MEM_HANDLE(idx, ion_fd); + tbl.bufq[idx].fd = -1; + tbl.bufq[idx].dma_buf = buf; + tbl.bufq[idx].flags = inp->flags; + tbl.bufq[idx].buf_handle = mem_handle; + tbl.bufq[idx].kmdvaddr = 0; + + tbl.bufq[idx].vaddr = iova; + + tbl.bufq[idx].len = request_len; + tbl.bufq[idx].num_hdl = num_hdl; + memcpy(tbl.bufq[idx].hdls, &smmu_hdl, + sizeof(int32_t)); + tbl.bufq[idx].is_imported = false; + kref_init(&tbl.bufq[idx].krefcount); + tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_KERNEL; + mutex_unlock(&tbl.bufq[idx].q_lock); + + out->kva = 0; + out->iova = (uint32_t)iova; + out->smmu_hdl = smmu_hdl; + out->mem_handle = mem_handle; + out->len = request_len; + out->region = region; + + return rc; + +slot_fail: + cam_smmu_release_sec_heap(smmu_hdl); +smmu_fail: + dma_buf_put(buf); +ion_fail: + return rc; +} +EXPORT_SYMBOL(cam_mem_mgr_reserve_memory_region); + +int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp) +{ + int32_t idx; + int rc; + int32_t smmu_hdl; + + if (!atomic_read(&cam_mem_mgr_state)) { + CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); + return -EINVAL; + } + + if (!inp) { + CAM_ERR(CAM_MEM, "Invalid argument"); + return -EINVAL; + } + + if (inp->region != CAM_SMMU_REGION_SECHEAP) { + CAM_ERR(CAM_MEM, "Only secondary heap supported"); + return -EINVAL; + } + + idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { + CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle"); + return -EINVAL; + } + + if (!tbl.bufq[idx].active) { + if (tbl.bufq[idx].vaddr == 0) { + CAM_ERR(CAM_MEM, "buffer is released already"); + return 0; + } + CAM_ERR(CAM_MEM, "Released buffer state should be active"); + return -EINVAL; + } + + if (tbl.bufq[idx].buf_handle != inp->mem_handle) { + CAM_ERR(CAM_MEM, + "Released buf handle not matching within table"); + return -EINVAL; + } + + if (tbl.bufq[idx].num_hdl != 1) { + CAM_ERR(CAM_MEM, + "Sec heap region should have only one smmu hdl"); + return -ENODEV; + } + + memcpy(&smmu_hdl, tbl.bufq[idx].hdls, + sizeof(int32_t)); + if (inp->smmu_hdl != smmu_hdl) { + CAM_ERR(CAM_MEM, + "Passed SMMU handle doesn't match with internal hdl"); + return -ENODEV; + } + + rc = cam_smmu_release_sec_heap(inp->smmu_hdl); + if (rc) { + CAM_ERR(CAM_MEM, + "Sec heap region release failed"); + return -ENODEV; + } + + CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle); + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + CAM_DBG(CAM_MEM, + "Called unmap from here, buf_handle: %u, idx: %d", + inp->mem_handle, idx); + else + rc = -EINVAL; + + return rc; +} +EXPORT_SYMBOL(cam_mem_mgr_free_memory_region); diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_mem_mgr.h b/techpack/camera-bengal/drivers/cam_req_mgr/cam_mem_mgr.h new file mode 100644 index 0000000000000000000000000000000000000000..84b3ce43eb81d9989ebc4e240c7977808a0b1ab2 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_mem_mgr.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CAM_MEM_MGR_H_ +#define _CAM_MEM_MGR_H_ + +#include +#include +#include +#include "cam_mem_mgr_api.h" + +#define CAM_MEM_BUFQ_MAX 1024 + +/* Enum for possible mem mgr states */ +enum cam_mem_mgr_state { + CAM_MEM_MGR_UNINITIALIZED, + CAM_MEM_MGR_INITIALIZED, +}; + +/*Enum for possible SMMU operations */ +enum cam_smmu_mapping_client { + CAM_SMMU_MAPPING_USER, + CAM_SMMU_MAPPING_KERNEL, +}; + +/** + * struct cam_mem_buf_queue + * + * @dma_buf: pointer to the allocated dma_buf in the table + * @q_lock: mutex lock for buffer + * @hdls: list of mapped handles + * @num_hdl: number of handles + * @fd: file descriptor of buffer + * @buf_handle: unique handle for buffer + * @align: alignment for allocation + * @len: size of buffer + * @flags: attributes of buffer + * @vaddr: IOVA of buffer + * @kmdvaddr: Kernel virtual address + * @active: state of the buffer + * @is_imported: Flag indicating if buffer is imported from an FD + * in user space + * @krefcount: Reference counter to track whether the buffer is + * mapped and in use + * @smmu_mapping_client: Client buffer (User or kernel) + */ +struct cam_mem_buf_queue { + struct dma_buf *dma_buf; + struct mutex q_lock; + int32_t hdls[CAM_MEM_MMU_MAX_HANDLE]; + int32_t num_hdl; + int32_t fd; + int32_t buf_handle; + int32_t align; + size_t len; + uint32_t flags; + uint64_t vaddr; + uintptr_t kmdvaddr; + bool active; + bool is_imported; + struct kref krefcount; + enum cam_smmu_mapping_client smmu_mapping_client; +}; + +/** + * struct cam_mem_table + * + * @m_lock: mutex lock for table + * @bitmap: bitmap of the mem mgr utility + * @bits: max bits of the utility + * @bufq: array of buffers + * @dentry: Debugfs entry + * @alloc_profile_enable: Whether to enable alloc profiling + * @dbg_buf_idx: debug buffer index to get usecases info + */ +struct cam_mem_table { + struct mutex m_lock; + void *bitmap; + size_t bits; + struct cam_mem_buf_queue bufq[CAM_MEM_BUFQ_MAX]; + struct dentry *dentry; + bool alloc_profile_enable; + size_t dbg_buf_idx; +}; + +/** + * @brief: Allocates and maps buffer + * + * @cmd: Allocation information + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd); + +/** + * @brief: Releases a buffer reference + * + * @cmd: Buffer release information + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd); + +/** + * @brief Maps a buffer + * + * @cmd: Buffer mapping information + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd); + +/** + * @brief: Perform cache ops on the buffer + * + * @cmd: Cache ops information + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd); + +/** + * @brief: Initializes the memory manager + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_mem_mgr_init(void); + +/** + * @brief: Tears down the memory manager + * + * @return None + */ +void cam_mem_mgr_deinit(void); + +#endif /* _CAM_MEM_MGR_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_mem_mgr_api.h b/techpack/camera-bengal/drivers/cam_req_mgr/cam_mem_mgr_api.h new file mode 100644 index 0000000000000000000000000000000000000000..6e28550e885b88b086a846b2aac1ffdf4a8546ab --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_mem_mgr_api.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CAM_MEM_MGR_API_H_ +#define _CAM_MEM_MGR_API_H_ + +#include +#include "cam_smmu_api.h" + +/** + * struct cam_mem_mgr_request_desc + * + * @size : Size of memory requested for allocation + * @align : Alignment of requested memory + * @smmu_hdl: SMMU handle to identify context bank where memory will be mapped + * @flags : Flags to indicate cached/uncached property + * @region : Region where memory should be allocated + */ +struct cam_mem_mgr_request_desc { + uint64_t size; + uint64_t align; + int32_t smmu_hdl; + uint32_t flags; +}; + +/** + * struct cam_mem_mgr_memory_desc + * + * @kva : Kernel virtual address of allocated memory + * @iova : IOVA of allocated memory + * @smmu_hdl : SMMU handle of allocated memory + * @mem_handle : Mem handle identifying allocated memory + * @len : Length of allocated memory + * @region : Region to which allocated memory belongs + */ +struct cam_mem_mgr_memory_desc { + uintptr_t kva; + uint32_t iova; + int32_t smmu_hdl; + uint32_t mem_handle; + uint64_t len; + enum cam_smmu_region_id region; +}; + +/** + * @brief: Requests a memory buffer + * + * @inp: Information specifying requested buffer properties + * @out: Information about allocated buffer + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp, + struct cam_mem_mgr_memory_desc *out); + +/** + * @brief: Releases a memory buffer + * + * @inp: Information specifying buffer to be released + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp); + +/** + * @brief: Returns IOVA information about buffer + * + * @buf_handle: Handle of the buffer + * @mmu_handle: SMMU handle where buffer is mapped + * @iova_ptr : Pointer to mmu's iova + * @len_ptr : Length of the buffer + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle, + dma_addr_t *iova_ptr, size_t *len_ptr); + +/** + * @brief: This indicates begin of CPU access. + * Also returns CPU address information about DMA buffer + * + * @buf_handle: Handle for the buffer + * @vaddr_ptr : pointer to kernel virtual address + * @len_ptr : Length of the buffer + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, + size_t *len); + +/** + * @brief: This indicates end of CPU access + * + * @buf_handle: Handle for the buffer + * + */ +void cam_mem_put_cpu_buf(int32_t buf_handle); + +static inline bool cam_mem_is_secure_buf(int32_t buf_handle) +{ + return CAM_MEM_MGR_IS_SECURE_HDL(buf_handle); +} + +/** + * @brief: Reserves a memory region + * + * @inp: Information specifying requested region properties + * @region : Region which is to be reserved + * @out : Information about reserved region + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp, + enum cam_smmu_region_id region, + struct cam_mem_mgr_memory_desc *out); + +/** + * @brief: Frees a memory region + * + * @inp : Information about region which is to be freed + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp); + +#endif /* _CAM_MEM_MGR_API_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_core.c b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_core.c new file mode 100644 index 0000000000000000000000000000000000000000..74be9570ae1311081a253b4d31f822405b028841 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -0,0 +1,4043 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include "cam_req_mgr_interface.h" +#include "cam_req_mgr_util.h" +#include "cam_req_mgr_core.h" +#include "cam_req_mgr_workq.h" +#include "cam_req_mgr_debug.h" +#include "cam_trace.h" +#include "cam_debug_util.h" +#include "cam_req_mgr_dev.h" +#include "cam_req_mgr_debug.h" + +static struct cam_req_mgr_core_device *g_crm_core_dev; +static struct cam_req_mgr_core_link g_links[MAXIMUM_LINKS_PER_SESSION]; + +void cam_req_mgr_core_link_reset(struct cam_req_mgr_core_link *link) +{ + link->link_hdl = 0; + link->num_devs = 0; + link->max_delay = CAM_PIPELINE_DELAY_0; + link->workq = NULL; + link->pd_mask = 0; + link->l_dev = NULL; + link->req.in_q = NULL; + link->req.l_tbl = NULL; + link->req.num_tbl = 0; + link->watchdog = NULL; + link->state = CAM_CRM_LINK_STATE_AVAILABLE; + link->parent = NULL; + link->subscribe_event = 0; + link->trigger_mask = 0; + link->sync_link = 0; + link->sync_link_sof_skip = false; + link->open_req_cnt = 0; + link->last_flush_id = 0; + link->initial_sync_req = -1; + link->in_msync_mode = false; + link->retry_cnt = 0; + link->is_shutdown = false; + link->initial_skip = true; + link->sof_timestamp = 0; + link->prev_sof_timestamp = 0; +} + +void cam_req_mgr_handle_core_shutdown(void) +{ + struct cam_req_mgr_core_session *session; + struct cam_req_mgr_core_session *tsession; + struct cam_req_mgr_session_info ses_info; + + if (!list_empty(&g_crm_core_dev->session_head)) { + list_for_each_entry_safe(session, tsession, + &g_crm_core_dev->session_head, entry) { + ses_info.session_hdl = + session->session_hdl; + cam_req_mgr_destroy_session(&ses_info, true); + } + } +} + +static int __cam_req_mgr_setup_payload(struct cam_req_mgr_core_workq *workq) +{ + int32_t i = 0; + int rc = 0; + struct crm_task_payload *task_data = NULL; + + task_data = kcalloc( + workq->task.num_task, sizeof(*task_data), + GFP_KERNEL); + if (!task_data) { + rc = -ENOMEM; + } else { + for (i = 0; i < workq->task.num_task; i++) + workq->task.pool[i].payload = &task_data[i]; + } + + return rc; +} + +/** + * __cam_req_mgr_find_pd_tbl() + * + * @brief : Find pipeline delay based table pointer which matches delay + * @tbl : Pointer to list of request table + * @delay : Pipeline delay value to be searched for comparison + * + * @return : pointer to request table for matching pipeline delay table. + * + */ +static struct cam_req_mgr_req_tbl *__cam_req_mgr_find_pd_tbl( + struct cam_req_mgr_req_tbl *tbl, int32_t delay) +{ + if (!tbl) + return NULL; + + do { + if (delay != tbl->pd) + tbl = tbl->next; + else + return tbl; + } while (tbl != NULL); + + return NULL; +} + +/** + * __cam_req_mgr_inc_idx() + * + * @brief : Increment val passed by step size and rollover after max_val + * @val : value to be incremented + * @step : amount/step by which val is incremented + * @max_val : max val after which idx will roll over + * + */ +static void __cam_req_mgr_inc_idx(int32_t *val, int32_t step, int32_t max_val) +{ + *val = (*val + step) % max_val; +} + +/** + * __cam_req_mgr_dec_idx() + * + * @brief : Decrement val passed by step size and rollover after max_val + * @val : value to be decremented + * @step : amount/step by which val is decremented + * @max_val : after zero value will roll over to max val + * + */ +static void __cam_req_mgr_dec_idx(int32_t *val, int32_t step, int32_t max_val) +{ + *val = *val - step; + if (*val < 0) + *val = max_val + (*val); +} + +/** + * __cam_req_mgr_inject_delay() + * + * @brief : Check if any pd device is injecting delay + * @tbl : cam_req_mgr_req_tbl + * @curr_idx : slot idx + * + * @return : 0 for success, negative for failure + */ +static int __cam_req_mgr_inject_delay( + struct cam_req_mgr_req_tbl *tbl, + int32_t curr_idx) +{ + struct cam_req_mgr_tbl_slot *slot = NULL; + int rc = 0; + + while (tbl) { + slot = &tbl->slot[curr_idx]; + if (slot->inject_delay > 0) { + slot->inject_delay--; + CAM_DBG(CAM_CRM, + "Delay injected by pd %d device", + tbl->pd); + rc = -EAGAIN; + } + __cam_req_mgr_dec_idx(&curr_idx, tbl->pd_delta, + tbl->num_slots); + tbl = tbl->next; + } + return rc; +} + +/** + * __cam_req_mgr_find_dev_name() + * + * @brief : Find the dev name whose req is not ready + * @link : link info + * @req_id : req_id which is not ready + * @pd : pipeline delay + * @masked_val : masked value holds the bit for all devices + * that don't have the req_id ready for a given + * pipeline delay + * @pd : pipeline delay + * + */ +static void __cam_req_mgr_find_dev_name( + struct cam_req_mgr_core_link *link, + int64_t req_id, uint32_t pd, uint32_t masked_val) +{ + int i = 0; + struct cam_req_mgr_connected_device *dev = NULL; + + for (i = 0; i < link->num_devs; i++) { + dev = &link->l_dev[i]; + if (dev->dev_info.p_delay == pd) { + if (masked_val & (1 << dev->dev_bit)) + continue; + + if (link->wq_congestion) + CAM_INFO_RATE_LIMIT(CAM_CRM, + "WQ congestion, Skip Frame: req: %lld not ready on link: 0x%x for pd: %d dev: %s open_req count: %d", + req_id, link->link_hdl, pd, + dev->dev_info.name, link->open_req_cnt); + else + CAM_INFO(CAM_CRM, + "Skip Frame: req: %lld not ready on link: 0x%x for pd: %d dev: %s open_req count: %d", + req_id, link->link_hdl, pd, + dev->dev_info.name, link->open_req_cnt); + } + } +} + +/** + * __cam_req_mgr_notify_error_on_link() + * + * @brief : Notify userspace on exceeding max retry + * attempts to apply same req + * @link : link on which the req could not be applied + * + */ +static int __cam_req_mgr_notify_error_on_link( + struct cam_req_mgr_core_link *link, + struct cam_req_mgr_connected_device *dev) +{ + struct cam_req_mgr_core_session *session = NULL; + struct cam_req_mgr_message msg; + int rc = 0, pd; + + session = (struct cam_req_mgr_core_session *)link->parent; + + pd = dev->dev_info.p_delay; + if (pd >= CAM_PIPELINE_DELAY_MAX) { + CAM_ERR(CAM_CRM, "pd : %d is more than expected", pd); + return -EINVAL; + } + + CAM_ERR(CAM_CRM, + "Notifying userspace to trigger recovery on link 0x%x for session %d", + link->link_hdl, session->session_hdl); + + memset(&msg, 0, sizeof(msg)); + + msg.session_hdl = session->session_hdl; + msg.u.err_msg.error_type = CAM_REQ_MGR_ERROR_TYPE_RECOVERY; + msg.u.err_msg.request_id = + link->req.apply_data[pd].req_id; + msg.u.err_msg.link_hdl = link->link_hdl; + + CAM_DBG(CAM_CRM, "Failed for device: %s while applying request: %lld", + dev->dev_info.name, link->req.apply_data[pd].req_id); + + rc = cam_req_mgr_notify_message(&msg, + V4L_EVENT_CAM_REQ_MGR_ERROR, + V4L_EVENT_CAM_REQ_MGR_EVENT); + + if (rc) + CAM_ERR(CAM_CRM, + "Error in notifying recovery for session %d link 0x%x rc %d", + session->session_hdl, link->link_hdl, rc); + + return rc; +} + +/** + * __cam_req_mgr_traverse() + * + * @brief : Traverse through pd tables, it will internally cover all linked + * pd tables. Each pd table visited will check if idx passed to its + * in ready state. If ready means all devices linked to the pd table + * have this request id packet ready. Then it calls subsequent pd + * tbl with new idx. New idx value takes into account the delta + * between current pd table and next one. + * @traverse_data: contains all the info to traverse through pd tables + * + * @return: 0 for success, negative for failure + * + */ +static int __cam_req_mgr_traverse(struct cam_req_mgr_traverse *traverse_data) +{ + int rc = 0; + int32_t next_idx = traverse_data->idx; + int32_t curr_idx = traverse_data->idx; + struct cam_req_mgr_req_tbl *tbl; + struct cam_req_mgr_apply *apply_data; + struct cam_req_mgr_tbl_slot *slot = NULL; + + if (!traverse_data->tbl || !traverse_data->apply_data) { + CAM_ERR(CAM_CRM, "NULL pointer %pK %pK", + traverse_data->tbl, traverse_data->apply_data); + traverse_data->result = 0; + return -EINVAL; + } + + tbl = traverse_data->tbl; + apply_data = traverse_data->apply_data; + slot = &tbl->slot[curr_idx]; + CAM_DBG(CAM_CRM, + "Enter pd %d idx %d state %d skip %d status %d skip_idx %d", + tbl->pd, curr_idx, tbl->slot[curr_idx].state, + tbl->skip_traverse, traverse_data->in_q->slot[curr_idx].status, + traverse_data->in_q->slot[curr_idx].skip_idx); + + /* Check if req is ready or in skip mode or pd tbl is in skip mode */ + if (tbl->slot[curr_idx].state == CRM_REQ_STATE_READY || + traverse_data->in_q->slot[curr_idx].skip_idx == 1 || + tbl->skip_traverse > 0) { + if (tbl->next) { + __cam_req_mgr_dec_idx(&next_idx, tbl->pd_delta, + tbl->num_slots); + traverse_data->idx = next_idx; + traverse_data->tbl = tbl->next; + rc = __cam_req_mgr_traverse(traverse_data); + } + if (rc >= 0) { + SET_SUCCESS_BIT(traverse_data->result, tbl->pd); + + if (traverse_data->validate_only == false) { + apply_data[tbl->pd].pd = tbl->pd; + apply_data[tbl->pd].req_id = + CRM_GET_REQ_ID( + traverse_data->in_q, curr_idx); + apply_data[tbl->pd].idx = curr_idx; + + CAM_DBG(CAM_CRM, "req_id: %lld with pd of %d", + apply_data[tbl->pd].req_id, + apply_data[tbl->pd].pd); + /* + * If traverse is successful decrement + * traverse skip + */ + if (tbl->skip_traverse > 0) { + apply_data[tbl->pd].req_id = -1; + tbl->skip_traverse--; + } + } + } else { + /* linked pd table is not ready for this traverse yet */ + return rc; + } + } else { + /* This pd table is not ready to proceed with asked idx */ + traverse_data->result_data.req_id = + CRM_GET_REQ_ID(traverse_data->in_q, curr_idx); + traverse_data->result_data.pd = tbl->pd; + traverse_data->result_data.masked_value = + (tbl->dev_mask & slot->req_ready_map); + SET_FAILURE_BIT(traverse_data->result, tbl->pd); + return -EAGAIN; + } + + return 0; +} + +/** + * __cam_req_mgr_in_q_skip_idx() + * + * @brief : Decrement val passed by step size and rollover after max_val + * @in_q : input queue pointer + * @idx : Sets skip_idx bit of the particular slot to true so when traverse + * happens for this idx, no req will be submitted for devices + * handling this idx. + * + */ +static void __cam_req_mgr_in_q_skip_idx(struct cam_req_mgr_req_queue *in_q, + int32_t idx) +{ + in_q->slot[idx].req_id = -1; + in_q->slot[idx].skip_idx = 1; + in_q->slot[idx].status = CRM_SLOT_STATUS_REQ_ADDED; + CAM_DBG(CAM_CRM, "SET IDX SKIP on slot= %d", idx); +} + +/** + * __cam_req_mgr_tbl_set_id() + * + * @brief : Set unique id to table + * @tbl : pipeline based table which requires new id + * @req : pointer to request data wihch contains num_tables counter + * + */ +static void __cam_req_mgr_tbl_set_id(struct cam_req_mgr_req_tbl *tbl, + struct cam_req_mgr_req_data *req) +{ + if (!tbl) + return; + do { + tbl->id = req->num_tbl++; + CAM_DBG(CAM_CRM, "%d: pd %d skip_traverse %d delta %d", + tbl->id, tbl->pd, tbl->skip_traverse, + tbl->pd_delta); + tbl = tbl->next; + } while (tbl != NULL); +} + +/** + * __cam_req_mgr_tbl_set_all_skip_cnt() + * + * @brief : Each pd table sets skip value based on delta between itself and + * max pd value. During initial streamon or bubble case this is + * used. That way each pd table skips required num of traverse and + * align themselve with req mgr connected devs. + * @l_tbl : iterates through list of pd tables and sets skip traverse + * + */ +static void __cam_req_mgr_tbl_set_all_skip_cnt( + struct cam_req_mgr_req_tbl **l_tbl) +{ + struct cam_req_mgr_req_tbl *tbl = *l_tbl; + int32_t max_pd; + + if (!tbl) + return; + + max_pd = tbl->pd; + do { + tbl->skip_traverse = max_pd - tbl->pd; + CAM_DBG(CAM_CRM, "%d: pd %d skip_traverse %d delta %d", + tbl->id, tbl->pd, tbl->skip_traverse, + tbl->pd_delta); + tbl = tbl->next; + } while (tbl != NULL); +} + +/** + * __cam_req_mgr_flush_req_slot() + * + * @brief : reset all the slots/pd tables when flush is + * invoked + * @link : link pointer + * + */ +static void __cam_req_mgr_flush_req_slot( + struct cam_req_mgr_core_link *link) +{ + int idx = 0; + struct cam_req_mgr_slot *slot; + struct cam_req_mgr_req_tbl *tbl; + struct cam_req_mgr_req_queue *in_q = link->req.in_q; + + for (idx = 0; idx < in_q->num_slots; idx++) { + slot = &in_q->slot[idx]; + tbl = link->req.l_tbl; + CAM_DBG(CAM_CRM, + "RESET idx: %d req_id: %lld slot->status: %d", + idx, slot->req_id, slot->status); + + /* Reset input queue slot */ + slot->req_id = -1; + slot->skip_idx = 1; + slot->recover = 0; + slot->additional_timeout = 0; + slot->sync_mode = CAM_REQ_MGR_SYNC_MODE_NO_SYNC; + slot->status = CRM_SLOT_STATUS_NO_REQ; + + /* Reset all pd table slot */ + while (tbl != NULL) { + CAM_DBG(CAM_CRM, "pd: %d: idx %d state %d", + tbl->pd, idx, tbl->slot[idx].state); + tbl->slot[idx].req_ready_map = 0; + tbl->slot[idx].state = CRM_REQ_STATE_EMPTY; + tbl = tbl->next; + } + } + + in_q->wr_idx = 0; + in_q->rd_idx = 0; +} + +/** + * __cam_req_mgr_reset_req_slot() + * + * @brief : reset specified idx/slot in input queue as well as all pd tables + * @link : link pointer + * @idx : slot index which will be reset + * + */ +static void __cam_req_mgr_reset_req_slot(struct cam_req_mgr_core_link *link, + int32_t idx) +{ + struct cam_req_mgr_slot *slot; + struct cam_req_mgr_req_tbl *tbl = link->req.l_tbl; + struct cam_req_mgr_req_queue *in_q = link->req.in_q; + + slot = &in_q->slot[idx]; + CAM_DBG(CAM_CRM, "RESET: idx: %d: slot->status %d", idx, slot->status); + + /* Check if CSL has already pushed new request*/ + if (slot->status == CRM_SLOT_STATUS_REQ_ADDED || + in_q->last_applied_idx == idx || + idx < 0) + return; + + /* Reset input queue slot */ + slot->req_id = -1; + slot->skip_idx = 0; + slot->recover = 0; + slot->additional_timeout = 0; + slot->sync_mode = CAM_REQ_MGR_SYNC_MODE_NO_SYNC; + slot->status = CRM_SLOT_STATUS_NO_REQ; + + /* Reset all pd table slot */ + while (tbl != NULL) { + CAM_DBG(CAM_CRM, "pd: %d: idx %d state %d", + tbl->pd, idx, tbl->slot[idx].state); + tbl->slot[idx].req_ready_map = 0; + tbl->slot[idx].state = CRM_REQ_STATE_EMPTY; + tbl = tbl->next; + } +} + +/** + * __cam_req_mgr_validate_crm_wd_timer() + * + * @brief : Validate/modify the wd timer based on associated + * timeout with the request + * @link : link pointer + * + */ +static void __cam_req_mgr_validate_crm_wd_timer( + struct cam_req_mgr_core_link *link) +{ + int idx = 0; + int next_frame_timeout = 0, current_frame_timeout = 0; + struct cam_req_mgr_req_queue *in_q = link->req.in_q; + + idx = in_q->rd_idx; + __cam_req_mgr_dec_idx( + &idx, (link->max_delay - 1), + in_q->num_slots); + next_frame_timeout = in_q->slot[idx].additional_timeout; + CAM_DBG(CAM_CRM, + "rd_idx: %d idx: %d next_frame_timeout: %d ms", + in_q->rd_idx, idx, next_frame_timeout); + + idx = in_q->rd_idx; + __cam_req_mgr_dec_idx( + &idx, link->max_delay, + in_q->num_slots); + current_frame_timeout = in_q->slot[idx].additional_timeout; + CAM_DBG(CAM_CRM, + "rd_idx: %d idx: %d current_frame_timeout: %d ms", + in_q->rd_idx, idx, current_frame_timeout); + spin_lock_bh(&link->link_state_spin_lock); + if (link->watchdog) { + if ((next_frame_timeout + CAM_REQ_MGR_WATCHDOG_TIMEOUT) > + link->watchdog->expires) { + CAM_DBG(CAM_CRM, + "Modifying wd timer expiry from %d ms to %d ms", + link->watchdog->expires, + (next_frame_timeout + + CAM_REQ_MGR_WATCHDOG_TIMEOUT)); + crm_timer_modify(link->watchdog, + next_frame_timeout + + CAM_REQ_MGR_WATCHDOG_TIMEOUT); + } else if (current_frame_timeout) { + CAM_DBG(CAM_CRM, + "Reset wd timer to frame from %d ms to %d ms", + link->watchdog->expires, + (current_frame_timeout + + CAM_REQ_MGR_WATCHDOG_TIMEOUT)); + crm_timer_modify(link->watchdog, + current_frame_timeout + + CAM_REQ_MGR_WATCHDOG_TIMEOUT); + } else if (link->watchdog->expires > + CAM_REQ_MGR_WATCHDOG_TIMEOUT) { + CAM_DBG(CAM_CRM, + "Reset wd timer to default from %d ms to %d ms", + link->watchdog->expires, + CAM_REQ_MGR_WATCHDOG_TIMEOUT); + crm_timer_modify(link->watchdog, + CAM_REQ_MGR_WATCHDOG_TIMEOUT); + } + } else { + CAM_WARN(CAM_CRM, "Watchdog timer exited already"); + } + spin_unlock_bh(&link->link_state_spin_lock); +} + +/** + * __cam_req_mgr_check_for_lower_pd_devices() + * + * @brief : Checks if there are any devices on the link having a lesser + * pd than the max pd of the link + * @link : Pointer to link which needs to be checked + * + * @return : 0 if a lower pd device is found negative otherwise + */ +static int __cam_req_mgr_check_for_lower_pd_devices( + struct cam_req_mgr_core_link *link) +{ + int i = 0; + struct cam_req_mgr_connected_device *dev = NULL; + + for (i = 0; i < link->num_devs; i++) { + dev = &link->l_dev[i]; + if (dev->dev_info.p_delay < link->max_delay) + return 0; + } + + return -EAGAIN; +} + +/** + * __cam_req_mgr_check_next_req_slot() + * + * @brief : While streaming if input queue does not contain any pending + * request, req mgr still needs to submit pending request ids to + * devices with lower pipeline delay value. + * @in_q : Pointer to input queue where req mgr wil peep into + * + * @return : 0 for success, negative for failure + */ +static int __cam_req_mgr_check_next_req_slot( + struct cam_req_mgr_core_link *link) +{ + int rc = 0; + struct cam_req_mgr_req_queue *in_q = link->req.in_q; + int32_t idx = in_q->rd_idx; + struct cam_req_mgr_slot *slot; + + __cam_req_mgr_inc_idx(&idx, 1, in_q->num_slots); + slot = &in_q->slot[idx]; + + CAM_DBG(CAM_CRM, "idx: %d: slot->status %d", idx, slot->status); + + /* Check if there is new req from CSL, if not complete req */ + if (slot->status == CRM_SLOT_STATUS_NO_REQ) { + rc = __cam_req_mgr_check_for_lower_pd_devices(link); + if (rc) { + CAM_DBG(CAM_CRM, "No lower pd devices on link 0x%x", + link->link_hdl); + return rc; + } + __cam_req_mgr_in_q_skip_idx(in_q, idx); + if (in_q->wr_idx != idx) + CAM_WARN(CAM_CRM, + "CHECK here wr %d, rd %d", in_q->wr_idx, idx); + __cam_req_mgr_inc_idx(&in_q->wr_idx, 1, in_q->num_slots); + } + + return rc; +} + +/** + * __cam_req_mgr_send_req() + * + * @brief : send request id to be applied to each device connected on link + * @link : pointer to link whose input queue and req tbl are + * traversed through + * @in_q : pointer to input request queue + * + * @return : 0 for success, negative for failure + * + */ +static int __cam_req_mgr_send_req(struct cam_req_mgr_core_link *link, + struct cam_req_mgr_req_queue *in_q, uint32_t trigger, + struct cam_req_mgr_connected_device **failed_dev) +{ + int rc = 0, pd, i, idx; + struct cam_req_mgr_connected_device *dev = NULL; + struct cam_req_mgr_apply_request apply_req; + struct cam_req_mgr_link_evt_data evt_data; + struct cam_req_mgr_tbl_slot *slot = NULL; + + apply_req.link_hdl = link->link_hdl; + apply_req.report_if_bubble = 0; + + for (i = 0; i < link->num_devs; i++) { + dev = &link->l_dev[i]; + if (!dev) + continue; + pd = dev->dev_info.p_delay; + if (pd >= CAM_PIPELINE_DELAY_MAX) { + CAM_WARN(CAM_CRM, "pd %d greater than max", + pd); + continue; + } + + idx = link->req.apply_data[pd].idx; + slot = &dev->pd_tbl->slot[idx]; + /* + * Just let flash go for this request and other + * device get restricted + */ + + if ((slot->skip_next_frame != true) || + (slot->dev_hdl != dev->dev_hdl)) + continue; + + if (!(dev->dev_info.trigger & trigger)) + continue; + + apply_req.dev_hdl = dev->dev_hdl; + apply_req.request_id = + link->req.apply_data[pd].req_id; + apply_req.trigger_point = trigger; + if (dev->ops && dev->ops->apply_req) { + rc = dev->ops->apply_req(&apply_req); + if (rc) { + *failed_dev = dev; + return rc; + } + CAM_DBG(CAM_REQ, + "SEND: link_hdl: %x pd: %d req_id %lld", + link->link_hdl, pd, apply_req.request_id); + slot->skip_next_frame = false; + slot->is_applied = true; + return -EAGAIN; + } + } + + for (i = 0; i < link->num_devs; i++) { + dev = &link->l_dev[i]; + if (dev) { + pd = dev->dev_info.p_delay; + if (pd >= CAM_PIPELINE_DELAY_MAX) { + CAM_WARN(CAM_CRM, "pd %d greater than max", + pd); + continue; + } + if (link->req.apply_data[pd].skip_idx || + link->req.apply_data[pd].req_id < 0) { + CAM_DBG(CAM_CRM, "skip %d req_id %lld", + link->req.apply_data[pd].skip_idx, + link->req.apply_data[pd].req_id); + continue; + } + if (!(dev->dev_info.trigger & trigger)) + continue; + + apply_req.dev_hdl = dev->dev_hdl; + apply_req.request_id = + link->req.apply_data[pd].req_id; + idx = link->req.apply_data[pd].idx; + slot = &dev->pd_tbl->slot[idx]; + apply_req.report_if_bubble = + in_q->slot[idx].recover; + + if ((slot->dev_hdl == dev->dev_hdl) && + (slot->is_applied == true)) { + slot->is_applied = false; + continue; + } + + apply_req.trigger_point = trigger; + CAM_DBG(CAM_REQ, + "SEND: link_hdl: %x pd %d req_id %lld", + link->link_hdl, pd, apply_req.request_id); + if (dev->ops && dev->ops->apply_req) { + rc = dev->ops->apply_req(&apply_req); + if (rc < 0) { + *failed_dev = dev; + break; + } + } + trace_cam_req_mgr_apply_request(link, &apply_req, dev); + } + } + if (rc < 0) { + CAM_WARN_RATE_LIMIT(CAM_CRM, "APPLY FAILED pd %d req_id %lld", + dev->dev_info.p_delay, apply_req.request_id); + /* Apply req failed notify already applied devs */ + for (; i >= 0; i--) { + dev = &link->l_dev[i]; + evt_data.evt_type = CAM_REQ_MGR_LINK_EVT_ERR; + evt_data.dev_hdl = dev->dev_hdl; + evt_data.link_hdl = link->link_hdl; + evt_data.req_id = apply_req.request_id; + evt_data.u.error = CRM_KMD_ERR_BUBBLE; + if (dev->ops && dev->ops->process_evt) + dev->ops->process_evt(&evt_data); + } + } + return rc; +} + +/** + * __cam_req_mgr_check_link_is_ready() + * + * @brief : traverse through all request tables and see if all devices are + * ready to apply request settings. + * @link : pointer to link whose input queue and req tbl are + * traversed through + * @idx : index within input request queue + * @validate_only : Whether to validate only and/or update settings + * + * @return : 0 for success, negative for failure + * + */ +static int __cam_req_mgr_check_link_is_ready(struct cam_req_mgr_core_link *link, + int32_t idx, bool validate_only) +{ + int rc; + struct cam_req_mgr_traverse traverse_data; + struct cam_req_mgr_req_queue *in_q; + struct cam_req_mgr_apply *apply_data; + + in_q = link->req.in_q; + + apply_data = link->req.apply_data; + + if (validate_only == false) { + memset(apply_data, 0, + sizeof(struct cam_req_mgr_apply) * CAM_PIPELINE_DELAY_MAX); + } + + traverse_data.apply_data = apply_data; + traverse_data.idx = idx; + traverse_data.tbl = link->req.l_tbl; + traverse_data.in_q = in_q; + traverse_data.result = 0; + traverse_data.result_data.masked_value = 0; + traverse_data.result_data.pd = 0; + traverse_data.result_data.req_id = 0; + traverse_data.validate_only = validate_only; + traverse_data.open_req_cnt = link->open_req_cnt; + + /* + * Some no-sync mode requests are processed after link config, + * then process the sync mode requests after no-sync mode requests + * are handled, the initial_skip should be false when processing + * the sync mode requests. + */ + if (link->initial_skip) { + CAM_DBG(CAM_CRM, + "Set initial_skip to false for link %x", + link->link_hdl); + link->initial_skip = false; + } + + /* + * Traverse through all pd tables, if result is success, + * apply the settings + */ + rc = __cam_req_mgr_traverse(&traverse_data); + CAM_DBG(CAM_CRM, + "SOF: idx %d result %x pd_mask %x rc %d", + idx, traverse_data.result, link->pd_mask, rc); + + if (!rc && traverse_data.result == link->pd_mask) { + CAM_DBG(CAM_CRM, + "READY: link_hdl= %x idx= %d, req_id= %lld :%lld :%lld", + link->link_hdl, idx, + apply_data[2].req_id, + apply_data[1].req_id, + apply_data[0].req_id); + } else { + rc = -EAGAIN; + __cam_req_mgr_find_dev_name(link, + traverse_data.result_data.req_id, + traverse_data.result_data.pd, + traverse_data.result_data.masked_value); + } + + return rc; +} + +/** + * __cam_req_mgr_find_slot_for_req() + * + * @brief : Find idx from input queue at which req id is enqueued + * @in_q : input request queue pointer + * @req_id : request id which needs to be searched in input queue + * + * @return : slot index where passed request id is stored, -1 for failure + * + */ +static int32_t __cam_req_mgr_find_slot_for_req( + struct cam_req_mgr_req_queue *in_q, int64_t req_id) +{ + int32_t idx, i; + struct cam_req_mgr_slot *slot; + + idx = in_q->rd_idx; + for (i = 0; i < in_q->num_slots; i++) { + slot = &in_q->slot[idx]; + if (slot->req_id == req_id) { + CAM_DBG(CAM_CRM, + "req: %lld found at idx: %d status: %d sync_mode: %d", + req_id, idx, slot->status, slot->sync_mode); + break; + } + __cam_req_mgr_dec_idx(&idx, 1, in_q->num_slots); + } + if (i >= in_q->num_slots) + idx = -1; + + return idx; +} + +/** + * __cam_req_mgr_check_sync_for_mslave() + * + * @brief : Processes requests during sync mode [master-slave] + * Here master corresponds to the link having a higher + * max_delay (pd) compared to the slave link. + * @link : Pointer to link whose input queue and req tbl are + * traversed through + * @slot : Pointer to the current slot being processed + * @return : 0 for success, negative for failure + * + */ +static int __cam_req_mgr_check_sync_for_mslave( + struct cam_req_mgr_core_link *link, + struct cam_req_mgr_slot *slot) +{ + struct cam_req_mgr_core_link *sync_link = NULL; + struct cam_req_mgr_slot *sync_slot = NULL; + int sync_slot_idx = 0, prev_idx, next_idx, rd_idx, sync_rd_idx, rc = 0; + int64_t req_id = 0, sync_req_id = 0; + int32_t sync_num_slots = 0; + + if (!link->sync_link) { + CAM_ERR(CAM_CRM, "Sync link null"); + return -EINVAL; + } + + sync_link = link->sync_link; + req_id = slot->req_id; + sync_num_slots = sync_link->req.in_q->num_slots; + sync_rd_idx = sync_link->req.in_q->rd_idx; + + CAM_DBG(CAM_CRM, + "link_hdl %x req %lld frame_skip_flag %d open_req_cnt:%d initial_sync_req [%lld,%lld] is_master:%d", + link->link_hdl, req_id, link->sync_link_sof_skip, + link->open_req_cnt, link->initial_sync_req, + sync_link->initial_sync_req, link->is_master); + + if (sync_link->sync_link_sof_skip) { + CAM_DBG(CAM_CRM, + "No req applied on corresponding SOF on sync link: %x", + sync_link->link_hdl); + sync_link->sync_link_sof_skip = false; + __cam_req_mgr_inject_delay(link->req.l_tbl, slot->idx); + return -EAGAIN; + } + + if (link->in_msync_mode && + sync_link->in_msync_mode && + (req_id - sync_link->req.in_q->slot[sync_rd_idx].req_id > + link->max_delay - sync_link->max_delay)) { + CAM_DBG(CAM_CRM, + "Req: %lld on link:%x need to hold for link: %x req:%d", + req_id, + link->link_hdl, + sync_link->link_hdl, + sync_link->req.in_q->slot[sync_rd_idx].req_id); + return -EINVAL; + } + + if (link->is_master) { + rc = __cam_req_mgr_inject_delay(link->req.l_tbl, slot->idx); + if (rc) { + CAM_DBG(CAM_CRM, + "Skip Process Req: %lld on link: %x", + req_id, link->link_hdl); + link->sync_link_sof_skip = true; + return rc; + } + + if (sync_link->initial_skip) { + CAM_DBG(CAM_CRM, "Link 0x%x [slave] not streamed on", + sync_link->link_hdl); + return -EAGAIN; + } + + rc = __cam_req_mgr_check_link_is_ready(link, slot->idx, true); + if (rc) { + CAM_DBG(CAM_CRM, + "Req: %lld [master] not ready on link: %x, rc=%d", + req_id, link->link_hdl, rc); + link->sync_link_sof_skip = true; + return rc; + } + + prev_idx = slot->idx; + __cam_req_mgr_dec_idx(&prev_idx, + (link->max_delay - sync_link->max_delay), + link->req.in_q->num_slots); + + rd_idx = sync_link->req.in_q->rd_idx; + sync_req_id = link->req.in_q->slot[prev_idx].req_id; + if ((sync_link->initial_sync_req != -1) && + (sync_link->initial_sync_req <= sync_req_id)) { + sync_slot_idx = __cam_req_mgr_find_slot_for_req( + sync_link->req.in_q, sync_req_id); + + if (sync_slot_idx == -1) { + CAM_DBG(CAM_CRM, + "Prev Req: %lld [master] not found on link: %x [slave]", + sync_req_id, sync_link->link_hdl); + link->sync_link_sof_skip = true; + return -EINVAL; + } + + if ((sync_link->req.in_q->slot[sync_slot_idx].status != + CRM_SLOT_STATUS_REQ_APPLIED) && + (((sync_slot_idx - rd_idx + sync_num_slots) % + sync_num_slots) >= 1) && + (sync_link->req.in_q->slot[rd_idx].status != + CRM_SLOT_STATUS_REQ_APPLIED)) { + CAM_DBG(CAM_CRM, + "Prev Req: %lld [master] not next on link: %x [slave]", + sync_req_id, + sync_link->link_hdl); + return -EINVAL; + } + + rc = __cam_req_mgr_check_link_is_ready(sync_link, + sync_slot_idx, true); + if (rc && + (sync_link->req.in_q->slot[sync_slot_idx].status + != CRM_SLOT_STATUS_REQ_APPLIED)) { + CAM_DBG(CAM_CRM, + "Req: %lld not ready on [slave] link: %x, rc=%d", + sync_req_id, sync_link->link_hdl, rc); + link->sync_link_sof_skip = true; + return rc; + } + } + } else { + if (link->initial_skip) + link->initial_skip = false; + + rc = __cam_req_mgr_inject_delay(link->req.l_tbl, slot->idx); + if (rc) { + CAM_DBG(CAM_CRM, + "Skip Process Req: %lld on link: %x", + req_id, link->link_hdl); + link->sync_link_sof_skip = true; + return rc; + } + + rc = __cam_req_mgr_check_link_is_ready(link, slot->idx, true); + if (rc) { + CAM_DBG(CAM_CRM, + "Req: %lld [slave] not ready on link: %x, rc=%d", + req_id, link->link_hdl, rc); + link->sync_link_sof_skip = true; + return rc; + } + + next_idx = link->req.in_q->rd_idx; + rd_idx = sync_link->req.in_q->rd_idx; + __cam_req_mgr_inc_idx(&next_idx, + (sync_link->max_delay - link->max_delay), + link->req.in_q->num_slots); + + sync_req_id = link->req.in_q->slot[next_idx].req_id; + + if ((sync_link->initial_sync_req != -1) && + (sync_link->initial_sync_req <= sync_req_id)) { + sync_slot_idx = __cam_req_mgr_find_slot_for_req( + sync_link->req.in_q, sync_req_id); + if (sync_slot_idx == -1) { + CAM_DBG(CAM_CRM, + "Next Req: %lld [slave] not found on link: %x [master]", + sync_req_id, sync_link->link_hdl); + link->sync_link_sof_skip = true; + return -EINVAL; + } + + if ((sync_link->req.in_q->slot[sync_slot_idx].status != + CRM_SLOT_STATUS_REQ_APPLIED) && + (((sync_slot_idx - rd_idx + sync_num_slots) % + sync_num_slots) >= 1) && + (sync_link->req.in_q->slot[rd_idx].status != + CRM_SLOT_STATUS_REQ_APPLIED)) { + CAM_DBG(CAM_CRM, + "Next Req: %lld [slave] not next on link: %x [master]", + sync_req_id, sync_link->link_hdl); + return -EINVAL; + } + + sync_slot = &sync_link->req.in_q->slot[sync_slot_idx]; + rc = __cam_req_mgr_check_link_is_ready(sync_link, + sync_slot_idx, true); + if (rc && (sync_slot->status != + CRM_SLOT_STATUS_REQ_APPLIED)) { + CAM_DBG(CAM_CRM, + "Next Req: %lld [slave] not ready on [master] link: %x, rc=%d", + sync_req_id, sync_link->link_hdl, rc); + link->sync_link_sof_skip = true; + return rc; + } + } + } + + CAM_DBG(CAM_REQ, + "Req: %lld ready to apply on link: %x [validation successful]", + req_id, link->link_hdl); + + /* + * At this point all validation is successfully done + * and we can proceed to apply the given request. + * Ideally the next call should return success. + */ + rc = __cam_req_mgr_check_link_is_ready(link, slot->idx, false); + if (rc) + CAM_WARN(CAM_CRM, "Unexpected return value rc: %d", rc); + + return 0; +} + + +/** + * __cam_req_mgr_check_sync_request_is_ready() + * + * @brief : processes requests during sync mode + * @link : pointer to link whose input queue and req tbl are + * traversed through + * @slot : pointer to the current slot being processed + * @return : 0 for success, negative for failure + * + */ +static int __cam_req_mgr_check_sync_req_is_ready( + struct cam_req_mgr_core_link *link, + struct cam_req_mgr_slot *slot) +{ + struct cam_req_mgr_core_link *sync_link = NULL; + struct cam_req_mgr_slot *sync_rd_slot = NULL; + int64_t req_id = 0, sync_req_id = 0; + int sync_slot_idx = 0, sync_rd_idx = 0, rc = 0; + int32_t sync_num_slots = 0; + uint64_t sync_frame_duration = 0; + uint64_t sof_timestamp_delta = 0; + uint64_t master_slave_diff = 0; + bool ready = true, sync_ready = true; + + if (!link->sync_link) { + CAM_ERR(CAM_CRM, "Sync link null"); + return -EINVAL; + } + + sync_link = link->sync_link; + req_id = slot->req_id; + sync_num_slots = sync_link->req.in_q->num_slots; + sync_rd_idx = sync_link->req.in_q->rd_idx; + sync_rd_slot = &sync_link->req.in_q->slot[sync_rd_idx]; + sync_req_id = sync_rd_slot->req_id; + + CAM_DBG(CAM_REQ, + "link_hdl %x req %lld frame_skip_flag %d ", + link->link_hdl, req_id, link->sync_link_sof_skip); + + if (sync_link->initial_skip) { + link->initial_skip = false; + __cam_req_mgr_inject_delay(link->req.l_tbl, slot->idx); + CAM_DBG(CAM_CRM, + "sync link %x not streamed on", + sync_link->link_hdl); + return -EAGAIN; + } + + if (sync_link->prev_sof_timestamp) + sync_frame_duration = sync_link->sof_timestamp - + sync_link->prev_sof_timestamp; + else + sync_frame_duration = DEFAULT_FRAME_DURATION; + + sof_timestamp_delta = + link->sof_timestamp >= sync_link->sof_timestamp + ? link->sof_timestamp - sync_link->sof_timestamp + : sync_link->sof_timestamp - link->sof_timestamp; + + CAM_DBG(CAM_CRM, + "sync link %x last frame_duration is %d ns", + sync_link->link_hdl, sync_frame_duration); + + if (link->initial_skip) { + link->initial_skip = false; + + if ((link->sof_timestamp > sync_link->sof_timestamp) && + (sync_link->sof_timestamp > 0) && + (link->sof_timestamp - sync_link->sof_timestamp) < + (sync_frame_duration / 2)) { + /* + * If this frame sync with the previous frame of sync + * link, then we need to skip this frame, since the + * previous frame of sync link is also skipped. + */ + __cam_req_mgr_inject_delay(link->req.l_tbl, slot->idx); + CAM_DBG(CAM_CRM, + "This frame sync with previous sync_link %x frame", + sync_link->link_hdl); + return -EAGAIN; + } else if (link->sof_timestamp <= sync_link->sof_timestamp) { + /* + * Sometimes, link receives the SOF event is eariler + * than sync link in IFE CSID side, but link's SOF + * event is processed later than sync link's, then + * we need to skip this SOF event since the sync + * link's SOF event is also skipped. + */ + __cam_req_mgr_inject_delay(link->req.l_tbl, slot->idx); + CAM_DBG(CAM_CRM, + "The previous frame of sync link is skipped"); + return -EAGAIN; + } + } + + if (sync_link->sync_link_sof_skip) { + CAM_DBG(CAM_REQ, + "No req applied on corresponding SOF on sync link: %x", + sync_link->link_hdl); + sync_link->sync_link_sof_skip = false; + __cam_req_mgr_inject_delay(link->req.l_tbl, slot->idx); + return -EAGAIN; + } + + rc = __cam_req_mgr_inject_delay(link->req.l_tbl, slot->idx); + if (rc) { + CAM_DBG(CAM_CRM, + "Skip Process Req: %lld on link: %x", + req_id, link->link_hdl); + ready = false; + } + + sync_slot_idx = __cam_req_mgr_find_slot_for_req( + sync_link->req.in_q, req_id); + if (sync_slot_idx == -1) { + CAM_DBG(CAM_CRM, "Req: %lld not found on link: %x [other link]", + req_id, sync_link->link_hdl); + sync_ready = false; + return -EAGAIN; + } + + if ((sync_link->req.in_q->slot[sync_slot_idx].status != + CRM_SLOT_STATUS_REQ_APPLIED) && + (((sync_slot_idx - sync_rd_idx + sync_num_slots) % + sync_num_slots) >= 1) && + (sync_rd_slot->status != + CRM_SLOT_STATUS_REQ_APPLIED)) { + CAM_DBG(CAM_CRM, + "Req: %lld [other link] not next req to be applied on link: %x", + req_id, sync_link->link_hdl); + return -EAGAIN; + } + + rc = __cam_req_mgr_check_link_is_ready(link, slot->idx, true); + if (rc) { + CAM_DBG(CAM_CRM, + "Req: %lld [My link] not ready on link: %x, rc=%d", + req_id, link->link_hdl, rc); + ready = false; + } + + rc = __cam_req_mgr_check_link_is_ready(sync_link, sync_slot_idx, true); + if (rc && (sync_link->req.in_q->slot[sync_slot_idx].status != + CRM_SLOT_STATUS_REQ_APPLIED)) { + CAM_DBG(CAM_CRM, + "Req: %lld not ready on [other link] link: %x, rc=%d", + req_id, sync_link->link_hdl, rc); + sync_ready = false; + } + + /* + * If both of them are ready or not ready, then just + * skip this sof and don't skip sync link next SOF. + */ + if (sync_ready != ready) { + CAM_DBG(CAM_CRM, + "Req: %lld ready %d sync_ready %d, ignore sync link next SOF", + req_id, ready, sync_ready); + + /* + * Only skip the frames if current frame sync with + * next frame of sync link. + */ + if (link->sof_timestamp - sync_link->sof_timestamp > + sync_frame_duration / 2) + link->sync_link_sof_skip = true; + return -EINVAL; + } else if (ready == false) { + CAM_DBG(CAM_CRM, + "Req: %lld not ready on link: %x", + req_id, link->link_hdl); + return -EINVAL; + } + + /* + * Do the self-correction when the frames are sync, + * we consider that the frames are synced if the + * difference of two SOF timestamp less than + * (sync_frame_duration / 5). + */ + master_slave_diff = sync_frame_duration; + do_div(master_slave_diff, 5); + if ((sync_link->sof_timestamp > 0) && + (sof_timestamp_delta < master_slave_diff) && + (sync_rd_slot->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC)) { + + /* + * This means current frame should sync with next + * frame of sync link, then the request id of in + * rd slot of two links should be same. + */ + CAM_DBG(CAM_CRM, + "link %x req_id %lld, sync_link %x req_id %lld", + link->link_hdl, req_id, + sync_link->link_hdl, sync_req_id); + + if (req_id > sync_req_id) { + CAM_DBG(CAM_CRM, + "link %x too quickly, skip this frame", + link->link_hdl); + return -EAGAIN; + } else if (req_id < sync_req_id) { + CAM_DBG(CAM_CRM, + "sync link %x too quickly, skip next frame of sync link", + sync_link->link_hdl); + link->sync_link_sof_skip = true; + } else if (sync_link->req.in_q->slot[sync_slot_idx].status != + CRM_SLOT_STATUS_REQ_APPLIED) { + CAM_DBG(CAM_CRM, + "link %x other not applied", link->link_hdl); + return -EAGAIN; + } + } + + CAM_DBG(CAM_REQ, + "Req: %lld ready to apply on link: %x [validation successful]", + req_id, link->link_hdl); + + /* + * At this point all validation is successfully done + * and we can proceed to apply the given request. + * Ideally the next call should return success. + */ + rc = __cam_req_mgr_check_link_is_ready(link, slot->idx, false); + if (rc) + CAM_WARN(CAM_CRM, "Unexpected return value rc: %d", rc); + + return 0; +} + +/** + * __cam_req_mgr_process_req() + * + * @brief : processes read index in request queue and traverse through table + * @link : pointer to link whose input queue and req tbl are + * traversed through + * + * @return : 0 for success, negative for failure + * + */ +static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, + struct cam_req_mgr_trigger_notify *trigger_data) +{ + int rc = 0, idx; + int reset_step = 0; + uint32_t trigger = trigger_data->trigger; + struct cam_req_mgr_slot *slot = NULL; + struct cam_req_mgr_req_queue *in_q; + struct cam_req_mgr_core_session *session; + struct cam_req_mgr_connected_device *dev; + + in_q = link->req.in_q; + session = (struct cam_req_mgr_core_session *)link->parent; + mutex_lock(&session->lock); + /* + * Check if new read index, + * - if in pending state, traverse again to complete + * transaction of this read index. + * - if in applied_state, somthign wrong. + * - if in no_req state, no new req + */ + CAM_DBG(CAM_REQ, + "SOF Req[%lld] idx %d req_status %d link_hdl %x wd_timeout %d ms", + in_q->slot[in_q->rd_idx].req_id, in_q->rd_idx, + in_q->slot[in_q->rd_idx].status, link->link_hdl, + in_q->slot[in_q->rd_idx].additional_timeout); + + slot = &in_q->slot[in_q->rd_idx]; + if (slot->status == CRM_SLOT_STATUS_NO_REQ) { + CAM_DBG(CAM_CRM, "No Pending req"); + rc = 0; + goto end; + } + + if ((trigger != CAM_TRIGGER_POINT_SOF) && + (trigger != CAM_TRIGGER_POINT_EOF)) + goto end; + + if ((trigger == CAM_TRIGGER_POINT_EOF) && + (!(link->trigger_mask & CAM_TRIGGER_POINT_SOF))) { + CAM_DBG(CAM_CRM, "Applying for last SOF fails"); + rc = -EINVAL; + goto end; + } + + if (trigger == CAM_TRIGGER_POINT_SOF) { + /* + * Update the timestamp in session lock protection + * to avoid timing issue. + */ + link->prev_sof_timestamp = link->sof_timestamp; + link->sof_timestamp = trigger_data->sof_timestamp_val; + + /* Check for WQ congestion */ + if (jiffies_to_msecs(jiffies - + link->last_sof_trigger_jiffies) < + MINIMUM_WORKQUEUE_SCHED_TIME_IN_MS) + link->wq_congestion = true; + else + link->wq_congestion = false; + + if (link->trigger_mask) { + CAM_ERR_RATE_LIMIT(CAM_CRM, + "Applying for last EOF fails"); + rc = -EINVAL; + goto end; + } + + if ((slot->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC) && + (link->sync_link)) { + if (link->is_master || link->sync_link->is_master) { + if (!link->in_msync_mode) { + CAM_DBG(CAM_CRM, + "Settings master-slave sync mode for link 0x%x", + link->link_hdl); + link->in_msync_mode = true; + } + + rc = __cam_req_mgr_check_sync_for_mslave( + link, slot); + } else { + rc = __cam_req_mgr_check_sync_req_is_ready( + link, slot); + } + } else { + if (link->in_msync_mode) { + CAM_DBG(CAM_CRM, + "Settings master-slave non sync mode for link 0x%x", + link->link_hdl); + link->in_msync_mode = false; + link->initial_sync_req = -1; + if (link->sync_link) { + link->sync_link->initial_sync_req = -1; + link->sync_link->in_msync_mode = false; + } + } + + rc = __cam_req_mgr_inject_delay(link->req.l_tbl, + slot->idx); + if (!rc) + rc = __cam_req_mgr_check_link_is_ready(link, + slot->idx, false); + } + + if (rc < 0) { + /* + * If traverse result is not success, then some devices + * are not ready with packet for the asked request id, + * hence try again in next sof + */ + slot->status = CRM_SLOT_STATUS_REQ_PENDING; + spin_lock_bh(&link->link_state_spin_lock); + if (link->state == CAM_CRM_LINK_STATE_ERR) { + /* + * During error recovery all tables should be + * ready, don't expect to enter here. + * @TODO: gracefully handle if recovery fails. + */ + CAM_ERR_RATE_LIMIT(CAM_CRM, + "FATAL recovery cant finish idx %d status %d", + in_q->rd_idx, + in_q->slot[in_q->rd_idx].status); + rc = -EPERM; + } + spin_unlock_bh(&link->link_state_spin_lock); + goto end; + } + } + + rc = __cam_req_mgr_send_req(link, link->req.in_q, trigger, &dev); + if (rc < 0) { + /* Apply req failed retry at next sof */ + slot->status = CRM_SLOT_STATUS_REQ_PENDING; + + if (!link->wq_congestion && dev) { + link->retry_cnt++; + if (link->retry_cnt == MAXIMUM_RETRY_ATTEMPTS) { + CAM_DBG(CAM_CRM, + "Max retry attempts reached on link[0x%x] for req [%lld]", + link->link_hdl, + in_q->slot[in_q->rd_idx].req_id); + + cam_req_mgr_debug_delay_detect(); + trace_cam_delay_detect("CRM", + "Max retry attempts reached", + in_q->slot[in_q->rd_idx].req_id, + CAM_DEFAULT_VALUE, + link->link_hdl, + CAM_DEFAULT_VALUE, rc); + + __cam_req_mgr_notify_error_on_link(link, dev); + link->retry_cnt = 0; + } + } else + CAM_WARN_RATE_LIMIT(CAM_CRM, + "workqueue congestion, last applied idx:%d rd idx:%d", + in_q->last_applied_idx, + in_q->rd_idx); + } else { + if (link->retry_cnt) + link->retry_cnt = 0; + + link->trigger_mask |= trigger; + + /* Check for any long exposure settings */ + __cam_req_mgr_validate_crm_wd_timer(link); + + CAM_DBG(CAM_CRM, "Applied req[%lld] on link[%x] success", + slot->req_id, link->link_hdl); + spin_lock_bh(&link->link_state_spin_lock); + if (link->state == CAM_CRM_LINK_STATE_ERR) { + CAM_WARN(CAM_CRM, "Err recovery done idx %d", + in_q->rd_idx); + link->state = CAM_CRM_LINK_STATE_READY; + } + spin_unlock_bh(&link->link_state_spin_lock); + + if (link->sync_link_sof_skip) + link->sync_link_sof_skip = false; + + if (link->trigger_mask == link->subscribe_event) { + slot->status = CRM_SLOT_STATUS_REQ_APPLIED; + link->trigger_mask = 0; + CAM_DBG(CAM_CRM, "req %d is applied on link %x", + slot->req_id, + link->link_hdl); + idx = in_q->rd_idx; + reset_step = link->max_delay; + if (link->sync_link) { + if ((link->in_msync_mode) && + (link->sync_link->is_master)) + reset_step = + link->sync_link->max_delay; + } + + if (slot->req_id > 0) + in_q->last_applied_idx = idx; + + __cam_req_mgr_dec_idx( + &idx, reset_step + 1, + in_q->num_slots); + __cam_req_mgr_reset_req_slot(link, idx); + link->open_req_cnt--; + } + } +end: + if (trigger == CAM_TRIGGER_POINT_SOF) + link->last_sof_trigger_jiffies = jiffies; + mutex_unlock(&session->lock); + return rc; +} + +/** + * __cam_req_mgr_add_tbl_to_link() + * + * @brief : Add table to list under link sorted by pd decremeting order + * @l_tbl : list of pipeline delay tables. + * @new_tbl : new tbl which will be appended to above list as per its pd value + * + */ +static void __cam_req_mgr_add_tbl_to_link(struct cam_req_mgr_req_tbl **l_tbl, + struct cam_req_mgr_req_tbl *new_tbl) +{ + struct cam_req_mgr_req_tbl *tbl; + + if (!(*l_tbl) || (*l_tbl)->pd < new_tbl->pd) { + new_tbl->next = *l_tbl; + if (*l_tbl) { + new_tbl->pd_delta = + new_tbl->pd - (*l_tbl)->pd; + } + *l_tbl = new_tbl; + } else { + tbl = *l_tbl; + + /* Reach existing tbl which has less pd value */ + while (tbl->next != NULL && + new_tbl->pd < tbl->next->pd) { + tbl = tbl->next; + } + if (tbl->next != NULL) { + new_tbl->pd_delta = + new_tbl->pd - tbl->next->pd; + } else { + /* This is last table in linked list*/ + new_tbl->pd_delta = 0; + } + new_tbl->next = tbl->next; + tbl->next = new_tbl; + tbl->pd_delta = tbl->pd - new_tbl->pd; + } + CAM_DBG(CAM_CRM, "added pd %d tbl to link delta %d", new_tbl->pd, + new_tbl->pd_delta); +} + +/** + * __cam_req_mgr_create_pd_tbl() + * + * @brief : Creates new request table for new delay value + * @delay : New pd table allocated will have this delay value + * + * @return : pointer to newly allocated table, NULL for failure + * + */ +static struct cam_req_mgr_req_tbl *__cam_req_mgr_create_pd_tbl(int32_t delay) +{ + struct cam_req_mgr_req_tbl *tbl = + kzalloc(sizeof(struct cam_req_mgr_req_tbl), GFP_KERNEL); + if (tbl != NULL) { + tbl->num_slots = MAX_REQ_SLOTS; + CAM_DBG(CAM_CRM, "pd= %d slots= %d", delay, tbl->num_slots); + } + + return tbl; +} + +/** + * __cam_req_mgr_destroy_all_tbl() + * + * @brief : This func will destroy all pipeline delay based req table structs + * @l_tbl : pointer to first table in list and it has max pd . + * + */ +static void __cam_req_mgr_destroy_all_tbl(struct cam_req_mgr_req_tbl **l_tbl) +{ + struct cam_req_mgr_req_tbl *tbl = *l_tbl, *temp; + + CAM_DBG(CAM_CRM, "*l_tbl %pK", tbl); + while (tbl != NULL) { + temp = tbl->next; + kfree(tbl); + tbl = temp; + } + *l_tbl = NULL; +} + +/** + * __cam_req_mgr_setup_in_q() + * + * @brief : Initialize req table data + * @req : request data pointer + * + * @return: 0 for success, negative for failure + * + */ +static int __cam_req_mgr_setup_in_q(struct cam_req_mgr_req_data *req) +{ + int i; + struct cam_req_mgr_req_queue *in_q = req->in_q; + + if (!in_q) { + CAM_ERR(CAM_CRM, "NULL in_q"); + return -EINVAL; + } + + mutex_lock(&req->lock); + in_q->num_slots = MAX_REQ_SLOTS; + + for (i = 0; i < in_q->num_slots; i++) { + in_q->slot[i].idx = i; + in_q->slot[i].req_id = -1; + in_q->slot[i].skip_idx = 0; + in_q->slot[i].status = CRM_SLOT_STATUS_NO_REQ; + } + + in_q->wr_idx = 0; + in_q->rd_idx = 0; + mutex_unlock(&req->lock); + + return 0; +} + +/** + * __cam_req_mgr_reset_req_tbl() + * + * @brief : Initialize req table data + * @req : request queue pointer + * + * @return: 0 for success, negative for failure + * + */ +static int __cam_req_mgr_reset_in_q(struct cam_req_mgr_req_data *req) +{ + struct cam_req_mgr_req_queue *in_q = req->in_q; + + if (!in_q) { + CAM_ERR(CAM_CRM, "NULL in_q"); + return -EINVAL; + } + + mutex_lock(&req->lock); + memset(in_q->slot, 0, + sizeof(struct cam_req_mgr_slot) * in_q->num_slots); + in_q->num_slots = 0; + + in_q->wr_idx = 0; + in_q->rd_idx = 0; + mutex_unlock(&req->lock); + + return 0; +} + +/** + * __cam_req_mgr_notify_sof_freeze() + * + * @brief : Notify devices on link on detecting a SOF freeze + * @link : link on which the sof freeze was detected + * + */ +static void __cam_req_mgr_notify_sof_freeze( + struct cam_req_mgr_core_link *link) +{ + int i = 0; + struct cam_req_mgr_link_evt_data evt_data; + struct cam_req_mgr_connected_device *dev = NULL; + + for (i = 0; i < link->num_devs; i++) { + dev = &link->l_dev[i]; + evt_data.evt_type = CAM_REQ_MGR_LINK_EVT_SOF_FREEZE; + evt_data.dev_hdl = dev->dev_hdl; + evt_data.link_hdl = link->link_hdl; + evt_data.req_id = 0; + evt_data.u.error = CRM_KMD_ERR_FATAL; + if (dev->ops && dev->ops->process_evt) + dev->ops->process_evt(&evt_data); + } +} + +/** + * __cam_req_mgr_process_sof_freeze() + * + * @brief : Apoptosis - Handles case when connected devices are not responding + * @priv : link information + * @data : task data + * + */ +static int __cam_req_mgr_process_sof_freeze(void *priv, void *data) +{ + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_core_session *session = NULL; + struct cam_req_mgr_message msg; + int rc = 0; + + if (!data || !priv) { + CAM_ERR(CAM_CRM, "input args NULL %pK %pK", data, priv); + return -EINVAL; + } + + link = (struct cam_req_mgr_core_link *)priv; + session = (struct cam_req_mgr_core_session *)link->parent; + + spin_lock_bh(&link->link_state_spin_lock); + if ((link->watchdog) && (link->watchdog->pause_timer)) { + CAM_INFO(CAM_CRM, "Watchdog Paused"); + spin_unlock_bh(&link->link_state_spin_lock); + return rc; + } + spin_unlock_bh(&link->link_state_spin_lock); + + CAM_ERR(CAM_CRM, "SOF freeze for session %d link 0x%x", + session->session_hdl, link->link_hdl); + + __cam_req_mgr_notify_sof_freeze(link); + memset(&msg, 0, sizeof(msg)); + + msg.session_hdl = session->session_hdl; + msg.u.err_msg.error_type = CAM_REQ_MGR_ERROR_TYPE_SOF_FREEZE; + msg.u.err_msg.request_id = 0; + msg.u.err_msg.link_hdl = link->link_hdl; + + rc = cam_req_mgr_notify_message(&msg, + V4L_EVENT_CAM_REQ_MGR_ERROR, V4L_EVENT_CAM_REQ_MGR_EVENT); + + if (rc) + CAM_ERR(CAM_CRM, + "Error notifying SOF freeze for session %d link 0x%x rc %d", + session->session_hdl, link->link_hdl, rc); + + return rc; +} + +/** + * __cam_req_mgr_sof_freeze() + * + * @brief : Callback function for timer timeout indicating SOF freeze + * @data : timer pointer + * + */ +static void __cam_req_mgr_sof_freeze(struct timer_list *timer_data) +{ + struct cam_req_mgr_timer *timer = + container_of(timer_data, struct cam_req_mgr_timer, sys_timer); + struct crm_workq_task *task = NULL; + struct cam_req_mgr_core_link *link = NULL; + struct crm_task_payload *task_data; + + if (!timer) { + CAM_ERR(CAM_CRM, "NULL timer"); + return; + } + + link = (struct cam_req_mgr_core_link *)timer->parent; + + task = cam_req_mgr_workq_get_task(link->workq); + if (!task) { + CAM_ERR(CAM_CRM, "No empty task"); + return; + } + + task_data = (struct crm_task_payload *)task->payload; + task_data->type = CRM_WORKQ_TASK_NOTIFY_FREEZE; + task->process_cb = &__cam_req_mgr_process_sof_freeze; + cam_req_mgr_workq_enqueue_task(task, link, CRM_TASK_PRIORITY_0); +} + +/** + * __cam_req_mgr_create_subdevs() + * + * @brief : Create new crm subdev to link with realtime devices + * @l_dev : list of subdevs internal to crm + * @num_dev : num of subdevs to be created for link + * + * @return : pointer to allocated list of devices + */ +static int __cam_req_mgr_create_subdevs( + struct cam_req_mgr_connected_device **l_dev, int32_t num_dev) +{ + int rc = 0; + *l_dev = kzalloc(sizeof(struct cam_req_mgr_connected_device) * + num_dev, GFP_KERNEL); + if (!*l_dev) + rc = -ENOMEM; + + return rc; +} + +/** + * __cam_req_mgr_destroy_subdev() + * + * @brief : Cleans up the subdevs allocated by crm for link + * @l_device : pointer to list of subdevs crm created + * + */ +static void __cam_req_mgr_destroy_subdev( + struct cam_req_mgr_connected_device **l_device) +{ + CAM_DBG(CAM_CRM, "*l_device %pK", *l_device); + if (*(l_device) != NULL) { + kfree(*(l_device)); + *l_device = NULL; + } +} + +/** + * __cam_req_mgr_destroy_link_info() + * + * @brief : Unlinks all devices on the link + * @link : pointer to link + * + * @return : returns if unlink for any device was success or failure + */ +static int __cam_req_mgr_disconnect_link(struct cam_req_mgr_core_link *link) +{ + int32_t i = 0; + struct cam_req_mgr_connected_device *dev; + struct cam_req_mgr_core_dev_link_setup link_data; + int rc = 0; + + link_data.link_enable = 0; + link_data.link_hdl = link->link_hdl; + link_data.crm_cb = NULL; + link_data.subscribe_event = 0; + + /* Using device ops unlink devices */ + for (i = 0; i < link->num_devs; i++) { + dev = &link->l_dev[i]; + if (dev == NULL) + continue; + + link_data.dev_hdl = dev->dev_hdl; + if (dev->ops && dev->ops->link_setup) { + rc = dev->ops->link_setup(&link_data); + if (rc) + CAM_ERR(CAM_CRM, + "Unlink failed dev name %s hdl %x", + dev->dev_info.name, + dev->dev_hdl); + } + dev->dev_hdl = 0; + dev->parent = NULL; + dev->ops = NULL; + } + + return rc; +} + +/** + * __cam_req_mgr_destroy_link_info() + * + * @brief : Cleans up the mem allocated while linking + * @link : pointer to link, mem associated with this link is freed + */ +static void __cam_req_mgr_destroy_link_info(struct cam_req_mgr_core_link *link) +{ + __cam_req_mgr_destroy_all_tbl(&link->req.l_tbl); + __cam_req_mgr_reset_in_q(&link->req); + link->req.num_tbl = 0; + mutex_destroy(&link->req.lock); + + link->pd_mask = 0; + link->num_devs = 0; + link->max_delay = 0; +} + +/** + * __cam_req_mgr_reserve_link() + * + * @brief: Reserves one link data struct within session + * @session: session identifier + * + * @return: pointer to link reserved + * + */ +static struct cam_req_mgr_core_link *__cam_req_mgr_reserve_link( + struct cam_req_mgr_core_session *session) +{ + struct cam_req_mgr_core_link *link; + struct cam_req_mgr_req_queue *in_q; + int i; + + if (!session || !g_crm_core_dev) { + CAM_ERR(CAM_CRM, "NULL session/core_dev ptr"); + return NULL; + } + + if (session->num_links >= MAXIMUM_LINKS_PER_SESSION) { + CAM_ERR(CAM_CRM, "Reached max links %d per session limit %d", + session->num_links, MAXIMUM_LINKS_PER_SESSION); + return NULL; + } + for (i = 0; i < MAXIMUM_LINKS_PER_SESSION; i++) { + if (!atomic_cmpxchg(&g_links[i].is_used, 0, 1)) { + link = &g_links[i]; + CAM_DBG(CAM_CRM, "alloc link index %d", i); + cam_req_mgr_core_link_reset(link); + break; + } + } + if (i == MAXIMUM_LINKS_PER_SESSION) + return NULL; + + in_q = kzalloc(sizeof(struct cam_req_mgr_req_queue), + GFP_KERNEL); + if (!in_q) { + CAM_ERR(CAM_CRM, "failed to create input queue, no mem"); + return NULL; + } + + mutex_lock(&link->lock); + link->num_devs = 0; + link->max_delay = 0; + memset(in_q->slot, 0, + sizeof(struct cam_req_mgr_slot) * MAX_REQ_SLOTS); + link->req.in_q = in_q; + in_q->num_slots = 0; + link->state = CAM_CRM_LINK_STATE_IDLE; + link->parent = (void *)session; + link->sync_link = NULL; + mutex_unlock(&link->lock); + + mutex_lock(&session->lock); + /* Loop through and find a free index */ + for (i = 0; i < MAXIMUM_LINKS_PER_SESSION; i++) { + if (!session->links[i]) { + CAM_DBG(CAM_CRM, + "Free link index %d found, num_links=%d", + i, session->num_links); + session->links[i] = link; + break; + } + } + + if (i == MAXIMUM_LINKS_PER_SESSION) { + CAM_ERR(CAM_CRM, "Free link index not found"); + goto error; + } + + session->num_links++; + CAM_DBG(CAM_CRM, "Active session links (%d)", + session->num_links); + mutex_unlock(&session->lock); + + return link; +error: + mutex_unlock(&session->lock); + kfree(in_q); + return NULL; +} + +/* + * __cam_req_mgr_free_link() + * + * @brief: Frees the link and its request queue + * + * @link: link identifier + * + */ +static void __cam_req_mgr_free_link(struct cam_req_mgr_core_link *link) +{ + ptrdiff_t i; + kfree(link->req.in_q); + link->req.in_q = NULL; + i = link - g_links; + CAM_DBG(CAM_CRM, "free link index %d", i); + cam_req_mgr_core_link_reset(link); + atomic_set(&g_links[i].is_used, 0); +} + +/** + * __cam_req_mgr_unreserve_link() + * + * @brief : Removes the link data struct from the session and frees it + * @session: session identifier + * @link : link identifier + * + */ +static void __cam_req_mgr_unreserve_link( + struct cam_req_mgr_core_session *session, + struct cam_req_mgr_core_link *link) +{ + int i; + + if (!session || !link) { + CAM_ERR(CAM_CRM, "NULL session/link ptr %pK %pK", + session, link); + return; + } + + mutex_lock(&session->lock); + if (!session->num_links) { + CAM_WARN(CAM_CRM, "No active link or invalid state: hdl %x", + link->link_hdl); + mutex_unlock(&session->lock); + return; + } + + for (i = 0; i < MAXIMUM_LINKS_PER_SESSION; i++) { + if (session->links[i] == link) + session->links[i] = NULL; + + if (link->sync_link) { + if (link->sync_link == session->links[i]) + session->links[i]->sync_link = NULL; + } + } + + link->sync_link = NULL; + session->num_links--; + CAM_DBG(CAM_CRM, "Active session links (%d)", session->num_links); + mutex_unlock(&session->lock); + __cam_req_mgr_free_link(link); +} + +/* Workqueue context processing section */ + +/** + * cam_req_mgr_process_send_req() + * + * @brief: This runs in workque thread context. Call core funcs to send + * apply request id to drivers. + * @priv : link information. + * @data : contains information about frame_id, link etc. + * + * @return: 0 on success. + */ +int cam_req_mgr_process_send_req(void *priv, void *data) +{ + int rc = 0; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_send_request *send_req = NULL; + struct cam_req_mgr_req_queue *in_q = NULL; + struct cam_req_mgr_connected_device *dev; + + if (!data || !priv) { + CAM_ERR(CAM_CRM, "input args NULL %pK %pK", data, priv); + rc = -EINVAL; + goto end; + } + link = (struct cam_req_mgr_core_link *)priv; + send_req = (struct cam_req_mgr_send_request *)data; + in_q = send_req->in_q; + + rc = __cam_req_mgr_send_req(link, in_q, CAM_TRIGGER_POINT_SOF, &dev); +end: + return rc; +} + +/** + * cam_req_mgr_process_flush_req() + * + * @brief: This runs in workque thread context. Call core funcs to check + * which requests need to be removed/cancelled. + * @priv : link information. + * @data : contains information about frame_id, link etc. + * + * @return: 0 on success. + */ +int cam_req_mgr_process_flush_req(void *priv, void *data) +{ + int rc = 0, i = 0, idx = -1; + struct cam_req_mgr_flush_info *flush_info = NULL; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_req_queue *in_q = NULL; + struct cam_req_mgr_slot *slot = NULL; + struct cam_req_mgr_connected_device *device = NULL; + struct cam_req_mgr_flush_request flush_req; + struct crm_task_payload *task_data = NULL; + + if (!data || !priv) { + CAM_ERR(CAM_CRM, "input args NULL %pK %pK", data, priv); + rc = -EINVAL; + goto end; + } + + link = (struct cam_req_mgr_core_link *)priv; + task_data = (struct crm_task_payload *)data; + flush_info = (struct cam_req_mgr_flush_info *)&task_data->u; + CAM_DBG(CAM_REQ, "link_hdl %x req_id %lld type %d", + flush_info->link_hdl, + flush_info->req_id, + flush_info->flush_type); + + in_q = link->req.in_q; + + trace_cam_flush_req(link, flush_info); + + mutex_lock(&link->req.lock); + if (flush_info->flush_type == CAM_REQ_MGR_FLUSH_TYPE_ALL) { + link->last_flush_id = flush_info->req_id; + CAM_INFO(CAM_CRM, "Last request id to flush is %lld", + flush_info->req_id); + __cam_req_mgr_flush_req_slot(link); + } else if (flush_info->flush_type == + CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ) { + idx = __cam_req_mgr_find_slot_for_req(in_q, flush_info->req_id); + if (idx < 0) { + CAM_ERR(CAM_CRM, "req_id %lld not found in input queue", + flush_info->req_id); + } else { + CAM_DBG(CAM_CRM, "req_id %lld found at idx %d", + flush_info->req_id, idx); + slot = &in_q->slot[idx]; + if (slot->status == CRM_SLOT_STATUS_REQ_PENDING || + slot->status == CRM_SLOT_STATUS_REQ_APPLIED) { + CAM_WARN(CAM_CRM, + "req_id %lld can not be cancelled", + flush_info->req_id); + mutex_unlock(&link->req.lock); + return -EINVAL; + } + slot->additional_timeout = 0; + __cam_req_mgr_in_q_skip_idx(in_q, idx); + } + } + + for (i = 0; i < link->num_devs; i++) { + device = &link->l_dev[i]; + flush_req.link_hdl = flush_info->link_hdl; + flush_req.dev_hdl = device->dev_hdl; + flush_req.req_id = flush_info->req_id; + flush_req.type = flush_info->flush_type; + /* @TODO: error return handling from drivers */ + if (device->ops && device->ops->flush_req) + rc = device->ops->flush_req(&flush_req); + } + complete(&link->workq_comp); + mutex_unlock(&link->req.lock); + +end: + return rc; +} + +/** + * cam_req_mgr_process_sched_req() + * + * @brief: This runs in workque thread context. Call core funcs to check + * which peding requests can be processed. + * @priv : link information. + * @data : contains information about frame_id, link etc. + * + * @return: 0 on success. + */ +int cam_req_mgr_process_sched_req(void *priv, void *data) +{ + int rc = 0; + struct cam_req_mgr_sched_request *sched_req = NULL; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_req_queue *in_q = NULL; + struct cam_req_mgr_slot *slot = NULL; + struct crm_task_payload *task_data = NULL; + + if (!data || !priv) { + CAM_ERR(CAM_CRM, "input args NULL %pK %pK", data, priv); + rc = -EINVAL; + goto end; + } + link = (struct cam_req_mgr_core_link *)priv; + task_data = (struct crm_task_payload *)data; + sched_req = (struct cam_req_mgr_sched_request *)&task_data->u; + in_q = link->req.in_q; + + CAM_DBG(CAM_CRM, + "link_hdl %x req_id %lld at slot %d sync_mode %d is_master %d exp_timeout_val %d ms", + sched_req->link_hdl, sched_req->req_id, + in_q->wr_idx, sched_req->sync_mode, + link->is_master, + sched_req->additional_timeout); + + mutex_lock(&link->req.lock); + slot = &in_q->slot[in_q->wr_idx]; + + if (slot->status != CRM_SLOT_STATUS_NO_REQ && + slot->status != CRM_SLOT_STATUS_REQ_APPLIED) + CAM_WARN(CAM_CRM, "in_q overwrite %d", slot->status); + + slot->status = CRM_SLOT_STATUS_REQ_ADDED; + slot->req_id = sched_req->req_id; + slot->sync_mode = sched_req->sync_mode; + slot->skip_idx = 0; + slot->recover = sched_req->bubble_enable; + if (sched_req->additional_timeout < 0) { + CAM_WARN(CAM_CRM, + "Requested timeout is invalid [%dms]", + sched_req->additional_timeout); + slot->additional_timeout = 0; + } else if (sched_req->additional_timeout > + CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX) { + CAM_WARN(CAM_CRM, + "Requested timeout [%dms] max supported timeout [%dms] resetting to max", + sched_req->additional_timeout, + CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX); + slot->additional_timeout = CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX; + } else { + slot->additional_timeout = sched_req->additional_timeout; + } + + link->open_req_cnt++; + __cam_req_mgr_inc_idx(&in_q->wr_idx, 1, in_q->num_slots); + + if (slot->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC) { + if (link->initial_sync_req == -1) + link->initial_sync_req = slot->req_id; + } else { + link->initial_sync_req = -1; + if (link->sync_link) + link->sync_link->initial_sync_req = -1; + } + + mutex_unlock(&link->req.lock); + +end: + return rc; +} + +/** + * cam_req_mgr_process_add_req() + * + * @brief: This runs in workque thread context. Call core funcs to check + * which peding requests can be processed. + * @priv : link information. + * @data : contains information about frame_id, link etc. + * + * @return: 0 on success. + */ +int cam_req_mgr_process_add_req(void *priv, void *data) +{ + int rc = 0, i = 0, idx; + struct cam_req_mgr_add_request *add_req = NULL; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_connected_device *device = NULL; + struct cam_req_mgr_req_tbl *tbl = NULL; + struct cam_req_mgr_tbl_slot *slot = NULL; + struct crm_task_payload *task_data = NULL; + + if (!data || !priv) { + CAM_ERR(CAM_CRM, "input args NULL %pK %pK", data, priv); + rc = -EINVAL; + goto end; + } + + link = (struct cam_req_mgr_core_link *)priv; + task_data = (struct crm_task_payload *)data; + add_req = (struct cam_req_mgr_add_request *)&task_data->u; + + for (i = 0; i < link->num_devs; i++) { + device = &link->l_dev[i]; + if (device->dev_hdl == add_req->dev_hdl) { + tbl = device->pd_tbl; + break; + } + } + if (!tbl) { + CAM_ERR_RATE_LIMIT(CAM_CRM, "dev_hdl not found %x, %x %x", + add_req->dev_hdl, + link->l_dev[0].dev_hdl, + link->l_dev[1].dev_hdl); + rc = -EINVAL; + goto end; + } + /* + * Go through request table and add + * request id to proper table + * 1. find req slot in in_q matching req_id.sent by dev + * 2. goto table of this device based on p_delay + * 3. mark req_ready_map with this dev_bit. + */ + + mutex_lock(&link->req.lock); + idx = __cam_req_mgr_find_slot_for_req(link->req.in_q, add_req->req_id); + if (idx < 0) { + CAM_ERR(CAM_CRM, + "req %lld not found in in_q for dev %s on link 0x%x", + add_req->req_id, device->dev_info.name, link->link_hdl); + rc = -EBADSLT; + mutex_unlock(&link->req.lock); + goto end; + } + + slot = &tbl->slot[idx]; + slot->is_applied = false; + if ((add_req->skip_before_applying & 0xFF) > slot->inject_delay) { + slot->inject_delay = (add_req->skip_before_applying & 0xFF); + slot->dev_hdl = add_req->dev_hdl; + if (add_req->skip_before_applying & SKIP_NEXT_FRAME) + slot->skip_next_frame = true; + CAM_DBG(CAM_CRM, "Req_id %llu injecting delay %llu", + add_req->req_id, + (add_req->skip_before_applying & 0xFF)); + } + + if (slot->state != CRM_REQ_STATE_PENDING && + slot->state != CRM_REQ_STATE_EMPTY) { + CAM_WARN(CAM_CRM, + "Unexpected state %d for slot %d map %x for dev %s on link 0x%x", + slot->state, idx, slot->req_ready_map, + device->dev_info.name, link->link_hdl); + } + + slot->state = CRM_REQ_STATE_PENDING; + slot->req_ready_map |= (1 << device->dev_bit); + + CAM_DBG(CAM_CRM, "idx %d dev_hdl %x req_id %lld pd %d ready_map %x", + idx, add_req->dev_hdl, add_req->req_id, tbl->pd, + slot->req_ready_map); + + trace_cam_req_mgr_add_req(link, idx, add_req, tbl, device); + + if (slot->req_ready_map == tbl->dev_mask) { + CAM_DBG(CAM_REQ, + "link 0x%x idx %d req_id %lld pd %d SLOT READY", + link->link_hdl, idx, add_req->req_id, tbl->pd); + slot->state = CRM_REQ_STATE_READY; + } + mutex_unlock(&link->req.lock); + +end: + return rc; +} + +/** + * __cam_req_mgr_apply_on_bubble() + * + * @brief : This API tries to apply settings to the device + * with highest pd on the bubbled frame + * @link : link information. + * @err_info : contains information about frame_id, trigger etc. + * + */ +void __cam_req_mgr_apply_on_bubble( + struct cam_req_mgr_core_link *link, + struct cam_req_mgr_error_notify *err_info) +{ + int rc = 0; + struct cam_req_mgr_trigger_notify trigger_data; + + trigger_data.dev_hdl = err_info->dev_hdl; + trigger_data.frame_id = err_info->frame_id; + trigger_data.link_hdl = err_info->link_hdl; + trigger_data.sof_timestamp_val = + err_info->sof_timestamp_val; + trigger_data.trigger = err_info->trigger; + + rc = __cam_req_mgr_process_req(link, &trigger_data); + if (rc) + CAM_ERR(CAM_CRM, + "Failed to apply request on bubbled frame"); +} + +/** + * cam_req_mgr_process_error() + * + * @brief: This runs in workque thread context. bubble /err recovery. + * @priv : link information. + * @data : contains information about frame_id, link etc. + * + * @return: 0 on success. + */ +int cam_req_mgr_process_error(void *priv, void *data) +{ + int rc = 0, idx = -1, i; + struct cam_req_mgr_error_notify *err_info = NULL; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_req_queue *in_q = NULL; + struct cam_req_mgr_slot *slot = NULL; + struct cam_req_mgr_connected_device *device = NULL; + struct cam_req_mgr_link_evt_data evt_data; + struct crm_task_payload *task_data = NULL; + + if (!data || !priv) { + CAM_ERR(CAM_CRM, "input args NULL %pK %pK", data, priv); + rc = -EINVAL; + goto end; + } + + link = (struct cam_req_mgr_core_link *)priv; + task_data = (struct crm_task_payload *)data; + err_info = (struct cam_req_mgr_error_notify *)&task_data->u; + CAM_DBG(CAM_CRM, "link_hdl %x req_id %lld error %d", + err_info->link_hdl, + err_info->req_id, + err_info->error); + + in_q = link->req.in_q; + + mutex_lock(&link->req.lock); + if (err_info->error == CRM_KMD_ERR_BUBBLE) { + idx = __cam_req_mgr_find_slot_for_req(in_q, err_info->req_id); + if (idx < 0) { + CAM_ERR_RATE_LIMIT(CAM_CRM, + "req_id %lld not found in input queue", + err_info->req_id); + } else { + CAM_DBG(CAM_CRM, "req_id %lld found at idx %d", + err_info->req_id, idx); + slot = &in_q->slot[idx]; + if (!slot->recover) { + CAM_WARN(CAM_CRM, + "err recovery disabled req_id %lld", + err_info->req_id); + mutex_unlock(&link->req.lock); + return 0; + } else if (slot->status != CRM_SLOT_STATUS_REQ_PENDING + && slot->status != CRM_SLOT_STATUS_REQ_APPLIED) { + CAM_WARN(CAM_CRM, + "req_id %lld can not be recovered %d", + err_info->req_id, slot->status); + mutex_unlock(&link->req.lock); + return -EINVAL; + } + /* Notify all devices in the link about error */ + for (i = 0; i < link->num_devs; i++) { + device = &link->l_dev[i]; + if (device != NULL) { + evt_data.dev_hdl = device->dev_hdl; + evt_data.evt_type = + CAM_REQ_MGR_LINK_EVT_ERR; + evt_data.link_hdl = link->link_hdl; + evt_data.req_id = err_info->req_id; + evt_data.u.error = err_info->error; + if (device->ops && + device->ops->process_evt) + rc = device->ops->process_evt( + &evt_data); + } + } + /* Bring processing pointer to bubbled req id */ + __cam_req_mgr_tbl_set_all_skip_cnt(&link->req.l_tbl); + in_q->rd_idx = idx; + in_q->slot[idx].status = CRM_SLOT_STATUS_REQ_ADDED; + if (link->sync_link) { + in_q->slot[idx].sync_mode = 0; + __cam_req_mgr_inc_idx(&idx, 1, + link->req.l_tbl->num_slots); + in_q->slot[idx].sync_mode = 0; + } + spin_lock_bh(&link->link_state_spin_lock); + link->state = CAM_CRM_LINK_STATE_ERR; + spin_unlock_bh(&link->link_state_spin_lock); + link->open_req_cnt++; + __cam_req_mgr_apply_on_bubble(link, err_info); + } + } + mutex_unlock(&link->req.lock); + +end: + return rc; +} + +/** + * cam_req_mgr_process_stop() + * + * @brief: This runs in workque thread context. stop notification. + * @priv : link information. + * @data : contains information about frame_id, link etc. + * + * @return: 0 on success. + */ +int cam_req_mgr_process_stop(void *priv, void *data) +{ + int rc = 0; + struct cam_req_mgr_core_link *link = NULL; + + if (!data || !priv) { + CAM_ERR(CAM_CRM, "input args NULL %pK %pK", data, priv); + rc = -EINVAL; + goto end; + } + + link = (struct cam_req_mgr_core_link *)priv; + __cam_req_mgr_flush_req_slot(link); +end: + return rc; +} + +/** + * cam_req_mgr_process_trigger() + * + * @brief: This runs in workque thread context. Call core funcs to check + * which peding requests can be processed. + * @priv : link information. + * @data : contains information about frame_id, link etc. + * + * @return: 0 on success. + */ +static int cam_req_mgr_process_trigger(void *priv, void *data) +{ + int rc = 0; + int32_t idx = -1; + struct cam_req_mgr_trigger_notify *trigger_data = NULL; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_req_queue *in_q = NULL; + struct crm_task_payload *task_data = NULL; + + if (!data || !priv) { + CAM_ERR(CAM_CRM, "input args NULL %pK %pK", data, priv); + rc = -EINVAL; + goto end; + } + + link = (struct cam_req_mgr_core_link *)priv; + task_data = (struct crm_task_payload *)data; + trigger_data = (struct cam_req_mgr_trigger_notify *)&task_data->u; + + CAM_DBG(CAM_REQ, "link_hdl %x frame_id %lld, trigger %x\n", + trigger_data->link_hdl, + trigger_data->frame_id, + trigger_data->trigger); + + in_q = link->req.in_q; + + mutex_lock(&link->req.lock); + + if (trigger_data->trigger == CAM_TRIGGER_POINT_SOF) { + idx = __cam_req_mgr_find_slot_for_req(in_q, + trigger_data->req_id); + if (idx >= 0) { + if (idx == in_q->last_applied_idx) + in_q->last_applied_idx = -1; + __cam_req_mgr_reset_req_slot(link, idx); + } + } + + /* + * Check if current read index is in applied state, if yes make it free + * and increment read index to next slot. + */ + CAM_DBG(CAM_CRM, "link_hdl %x curent idx %d req_status %d", + link->link_hdl, in_q->rd_idx, in_q->slot[in_q->rd_idx].status); + + spin_lock_bh(&link->link_state_spin_lock); + + if (link->state < CAM_CRM_LINK_STATE_READY) { + CAM_WARN(CAM_CRM, "invalid link state:%d", link->state); + spin_unlock_bh(&link->link_state_spin_lock); + rc = -EPERM; + goto release_lock; + } + + if (link->state == CAM_CRM_LINK_STATE_ERR) + CAM_WARN(CAM_CRM, "Error recovery idx %d status %d", + in_q->rd_idx, + in_q->slot[in_q->rd_idx].status); + + spin_unlock_bh(&link->link_state_spin_lock); + + if (in_q->slot[in_q->rd_idx].status == CRM_SLOT_STATUS_REQ_APPLIED) { + /* + * Do NOT reset req q slot data here, it can not be done + * here because we need to preserve the data to handle bubble. + * + * Check if any new req is pending in slot, if not finish the + * lower pipeline delay device with available req ids. + */ + CAM_DBG(CAM_CRM, "link[%x] Req[%lld] invalidating slot", + link->link_hdl, in_q->slot[in_q->rd_idx].req_id); + rc = __cam_req_mgr_check_next_req_slot(link); + if (rc) { + CAM_DBG(CAM_REQ, + "No pending req to apply to lower pd devices"); + rc = 0; + __cam_req_mgr_inc_idx(&in_q->rd_idx, + 1, in_q->num_slots); + goto release_lock; + } + __cam_req_mgr_inc_idx(&in_q->rd_idx, 1, in_q->num_slots); + } + + rc = __cam_req_mgr_process_req(link, trigger_data); + +release_lock: + mutex_unlock(&link->req.lock); +end: + return rc; +} + +/** + * __cam_req_mgr_dev_handle_to_name() + * + * @brief : Finds device name based on the device handle + * @dev_hdl : Device handle whose name is to be found + * @link : Link on which the device is connected + * @return : String containing the device name + * + */ +static const char *__cam_req_mgr_dev_handle_to_name( + int32_t dev_hdl, struct cam_req_mgr_core_link *link) +{ + struct cam_req_mgr_connected_device *dev = NULL; + int i = 0; + + for (i = 0; i < link->num_devs; i++) { + dev = &link->l_dev[i]; + + if (dev_hdl == dev->dev_hdl) + return dev->dev_info.name; + } + + return "Invalid dev_hdl"; +} + +/* Linked devices' Callback section */ + +/** + * cam_req_mgr_cb_add_req() + * + * @brief : Drivers call this function to notify new packet is available. + * @add_req : Information about new request available at a device. + * + * @return : 0 on success, negative in case of failure + * + */ +static int cam_req_mgr_cb_add_req(struct cam_req_mgr_add_request *add_req) +{ + int rc = 0, idx; + struct crm_workq_task *task = NULL; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_add_request *dev_req; + struct crm_task_payload *task_data; + + if (!add_req) { + CAM_ERR(CAM_CRM, "sof_data is NULL"); + return -EINVAL; + } + + link = cam_get_link_priv(add_req->link_hdl); + if (!link) { + CAM_DBG(CAM_CRM, "link ptr NULL %x", add_req->link_hdl); + return -EINVAL; + } + + CAM_DBG(CAM_REQ, "dev name %s dev_hdl %d dev req %lld", + __cam_req_mgr_dev_handle_to_name(add_req->dev_hdl, link), + add_req->dev_hdl, add_req->req_id); + + mutex_lock(&link->lock); + spin_lock_bh(&link->link_state_spin_lock); + if (link->state < CAM_CRM_LINK_STATE_READY) { + CAM_WARN(CAM_CRM, "invalid link state:%d", link->state); + rc = -EPERM; + spin_unlock_bh(&link->link_state_spin_lock); + goto end; + } + spin_unlock_bh(&link->link_state_spin_lock); + + /* Validate if req id is present in input queue */ + idx = __cam_req_mgr_find_slot_for_req(link->req.in_q, add_req->req_id); + if (idx < 0) { + CAM_ERR(CAM_CRM, "req %lld not found in in_q", add_req->req_id); + rc = -ENOENT; + goto end; + } + + task = cam_req_mgr_workq_get_task(link->workq); + if (!task) { + CAM_ERR_RATE_LIMIT(CAM_CRM, "no empty task dev %x req %lld", + add_req->dev_hdl, add_req->req_id); + rc = -EBUSY; + goto end; + } + + task_data = (struct crm_task_payload *)task->payload; + task_data->type = CRM_WORKQ_TASK_DEV_ADD_REQ; + dev_req = (struct cam_req_mgr_add_request *)&task_data->u; + dev_req->req_id = add_req->req_id; + dev_req->link_hdl = add_req->link_hdl; + dev_req->dev_hdl = add_req->dev_hdl; + dev_req->skip_before_applying = add_req->skip_before_applying; + task->process_cb = &cam_req_mgr_process_add_req; + rc = cam_req_mgr_workq_enqueue_task(task, link, CRM_TASK_PRIORITY_0); + CAM_DBG(CAM_CRM, "X: dev %x dev req %lld", + add_req->dev_hdl, add_req->req_id); + +end: + mutex_unlock(&link->lock); + return rc; +} + +/** + * cam_req_mgr_cb_notify_err() + * + * @brief : Error received from device, sends bubble recovery + * @err_info : contains information about error occurred like bubble/overflow + * + * @return : 0 on success, negative in case of failure + * + */ +static int cam_req_mgr_cb_notify_err( + struct cam_req_mgr_error_notify *err_info) +{ + int rc = 0; + struct crm_workq_task *task = NULL; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_error_notify *notify_err; + struct crm_task_payload *task_data; + + if (!err_info) { + CAM_ERR(CAM_CRM, "err_info is NULL"); + rc = -EINVAL; + goto end; + } + + link = cam_get_link_priv(err_info->link_hdl); + if (!link) { + CAM_DBG(CAM_CRM, "link ptr NULL %x", err_info->link_hdl); + rc = -EINVAL; + goto end; + } + + spin_lock_bh(&link->link_state_spin_lock); + if (link->state != CAM_CRM_LINK_STATE_READY) { + CAM_WARN(CAM_CRM, "invalid link state:%d", link->state); + spin_unlock_bh(&link->link_state_spin_lock); + rc = -EPERM; + goto end; + } + crm_timer_reset(link->watchdog); + spin_unlock_bh(&link->link_state_spin_lock); + + task = cam_req_mgr_workq_get_task(link->workq); + if (!task) { + CAM_ERR(CAM_CRM, "no empty task req_id %lld", err_info->req_id); + rc = -EBUSY; + goto end; + } + + task_data = (struct crm_task_payload *)task->payload; + task_data->type = CRM_WORKQ_TASK_NOTIFY_ERR; + notify_err = (struct cam_req_mgr_error_notify *)&task_data->u; + notify_err->req_id = err_info->req_id; + notify_err->link_hdl = err_info->link_hdl; + notify_err->dev_hdl = err_info->dev_hdl; + notify_err->error = err_info->error; + task->process_cb = &cam_req_mgr_process_error; + rc = cam_req_mgr_workq_enqueue_task(task, link, CRM_TASK_PRIORITY_0); + +end: + return rc; +} + +/** + * cam_req_mgr_cb_notify_timer() + * + * @brief : Notify SOF timer to pause after flush + * @timer_data : contains information about frame_id, link etc. + * + * @return : 0 on success + * + */ +static int cam_req_mgr_cb_notify_timer( + struct cam_req_mgr_timer_notify *timer_data) +{ + int rc = 0; + struct cam_req_mgr_core_link *link = NULL; + + if (!timer_data) { + CAM_ERR(CAM_CRM, "timer data is NULL"); + rc = -EINVAL; + goto end; + } + + link = cam_get_link_priv(timer_data->link_hdl); + if (!link) { + CAM_DBG(CAM_CRM, "link ptr NULL %x", timer_data->link_hdl); + rc = -EINVAL; + goto end; + } + + spin_lock_bh(&link->link_state_spin_lock); + if (link->state < CAM_CRM_LINK_STATE_READY) { + CAM_WARN(CAM_CRM, "invalid link state:%d", link->state); + spin_unlock_bh(&link->link_state_spin_lock); + rc = -EPERM; + goto end; + } + if ((link->watchdog) && (!timer_data->state)) + link->watchdog->pause_timer = true; + spin_unlock_bh(&link->link_state_spin_lock); + +end: + return rc; +} + +/* + * cam_req_mgr_cb_notify_stop() + * + * @brief : Stop received from device, resets the morked slots + * @err_info : contains information about error occurred like bubble/overflow + * + * @return : 0 on success, negative in case of failure + * + */ +static int cam_req_mgr_cb_notify_stop( + struct cam_req_mgr_notify_stop *stop_info) +{ + int rc = 0; + struct crm_workq_task *task = NULL; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_notify_stop *notify_stop; + struct crm_task_payload *task_data; + + if (!stop_info) { + CAM_ERR(CAM_CRM, "stop_info is NULL"); + rc = -EINVAL; + goto end; + } + + link = cam_get_link_priv(stop_info->link_hdl); + if (!link) { + CAM_DBG(CAM_CRM, "link ptr NULL %x", stop_info->link_hdl); + rc = -EINVAL; + goto end; + } + + spin_lock_bh(&link->link_state_spin_lock); + if (link->state != CAM_CRM_LINK_STATE_READY) { + CAM_WARN(CAM_CRM, "invalid link state:%d", link->state); + spin_unlock_bh(&link->link_state_spin_lock); + rc = -EPERM; + goto end; + } + crm_timer_reset(link->watchdog); + spin_unlock_bh(&link->link_state_spin_lock); + + task = cam_req_mgr_workq_get_task(link->workq); + if (!task) { + CAM_ERR(CAM_CRM, "no empty task"); + rc = -EBUSY; + goto end; + } + + task_data = (struct crm_task_payload *)task->payload; + task_data->type = CRM_WORKQ_TASK_NOTIFY_ERR; + notify_stop = (struct cam_req_mgr_notify_stop *)&task_data->u; + notify_stop->link_hdl = stop_info->link_hdl; + task->process_cb = &cam_req_mgr_process_stop; + rc = cam_req_mgr_workq_enqueue_task(task, link, CRM_TASK_PRIORITY_0); + +end: + return rc; +} + + + +/** + * cam_req_mgr_cb_notify_trigger() + * + * @brief : SOF received from device, sends trigger through workqueue + * @sof_data: contains information about frame_id, link etc. + * + * @return : 0 on success + * + */ +static int cam_req_mgr_cb_notify_trigger( + struct cam_req_mgr_trigger_notify *trigger_data) +{ + int rc = 0; + struct crm_workq_task *task = NULL; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_trigger_notify *notify_trigger; + struct crm_task_payload *task_data; + + if (!trigger_data) { + CAM_ERR(CAM_CRM, "sof_data is NULL"); + rc = -EINVAL; + goto end; + } + + link = cam_get_link_priv(trigger_data->link_hdl); + if (!link) { + CAM_DBG(CAM_CRM, "link ptr NULL %x", trigger_data->link_hdl); + rc = -EINVAL; + goto end; + } + + spin_lock_bh(&link->link_state_spin_lock); + if (link->state < CAM_CRM_LINK_STATE_READY) { + CAM_WARN(CAM_CRM, "invalid link state:%d", link->state); + spin_unlock_bh(&link->link_state_spin_lock); + rc = -EPERM; + goto end; + } + + if ((link->watchdog) && (link->watchdog->pause_timer)) + link->watchdog->pause_timer = false; + + crm_timer_reset(link->watchdog); + spin_unlock_bh(&link->link_state_spin_lock); + + task = cam_req_mgr_workq_get_task(link->workq); + if (!task) { + CAM_ERR_RATE_LIMIT(CAM_CRM, "no empty task frame %lld", + trigger_data->frame_id); + rc = -EBUSY; + goto end; + } + task_data = (struct crm_task_payload *)task->payload; + task_data->type = CRM_WORKQ_TASK_NOTIFY_SOF; + notify_trigger = (struct cam_req_mgr_trigger_notify *)&task_data->u; + notify_trigger->frame_id = trigger_data->frame_id; + notify_trigger->link_hdl = trigger_data->link_hdl; + notify_trigger->dev_hdl = trigger_data->dev_hdl; + notify_trigger->trigger = trigger_data->trigger; + notify_trigger->req_id = trigger_data->req_id; + notify_trigger->sof_timestamp_val = trigger_data->sof_timestamp_val; + task->process_cb = &cam_req_mgr_process_trigger; + rc = cam_req_mgr_workq_enqueue_task(task, link, CRM_TASK_PRIORITY_0); + +end: + return rc; +} + +static struct cam_req_mgr_crm_cb cam_req_mgr_ops = { + .notify_trigger = cam_req_mgr_cb_notify_trigger, + .notify_err = cam_req_mgr_cb_notify_err, + .add_req = cam_req_mgr_cb_add_req, + .notify_timer = cam_req_mgr_cb_notify_timer, + .notify_stop = cam_req_mgr_cb_notify_stop, +}; + +/** + * __cam_req_mgr_setup_link_info() + * + * @brief : Sets up input queue, create pd based tables, communicate with + * devs connected on this link and setup communication. + * @link : pointer to link to setup + * @link_info : link_info coming from CSL to prepare link + * + * @return : 0 on success, negative in case of failure + * + */ +static int __cam_req_mgr_setup_link_info(struct cam_req_mgr_core_link *link, + struct cam_req_mgr_ver_info *link_info) +{ + int rc = 0, i = 0, num_devices = 0; + struct cam_req_mgr_core_dev_link_setup link_data; + struct cam_req_mgr_connected_device *dev; + struct cam_req_mgr_req_tbl *pd_tbl; + enum cam_pipeline_delay max_delay; + uint32_t subscribe_event = 0; + if (link_info->version == VERSION_1) { + if (link_info->u.link_info_v1.num_devices > + CAM_REQ_MGR_MAX_HANDLES) + return -EPERM; + } + else if (link_info->version == VERSION_2) { + if (link_info->u.link_info_v2.num_devices > + CAM_REQ_MGR_MAX_HANDLES_V2) + return -EPERM; + } + mutex_init(&link->req.lock); + CAM_DBG(CAM_CRM, "LOCK_DBG in_q lock %pK", &link->req.lock); + link->req.num_tbl = 0; + + rc = __cam_req_mgr_setup_in_q(&link->req); + if (rc < 0) + return rc; + + max_delay = CAM_PIPELINE_DELAY_0; + if (link_info->version == VERSION_1) + num_devices = link_info->u.link_info_v1.num_devices; + else if (link_info->version == VERSION_2) + num_devices = link_info->u.link_info_v2.num_devices; + for (i = 0; i < num_devices; i++) { + dev = &link->l_dev[i]; + /* Using dev hdl, get ops ptr to communicate with device */ + if (link_info->version == VERSION_1) + dev->ops = (struct cam_req_mgr_kmd_ops *) + cam_get_device_ops( + link_info->u.link_info_v1.dev_hdls[i]); + else if (link_info->version == VERSION_2) + dev->ops = (struct cam_req_mgr_kmd_ops *) + cam_get_device_ops( + link_info->u.link_info_v2.dev_hdls[i]); + if (!dev->ops || + !dev->ops->get_dev_info || + !dev->ops->link_setup) { + CAM_ERR(CAM_CRM, "FATAL: device ops NULL"); + rc = -ENXIO; + goto error; + } + if (link_info->version == VERSION_1) + dev->dev_hdl = link_info->u.link_info_v1.dev_hdls[i]; + else if (link_info->version == VERSION_2) + dev->dev_hdl = link_info->u.link_info_v2.dev_hdls[i]; + dev->parent = (void *)link; + dev->dev_info.dev_hdl = dev->dev_hdl; + rc = dev->ops->get_dev_info(&dev->dev_info); + + trace_cam_req_mgr_connect_device(link, &dev->dev_info); + if (link_info->version == VERSION_1) + CAM_DBG(CAM_CRM, + "%x: connected: %s, id %d, delay %d, trigger %x", + link_info->u.link_info_v1.session_hdl, + dev->dev_info.name, + dev->dev_info.dev_id, dev->dev_info.p_delay, + dev->dev_info.trigger); + else if (link_info->version == VERSION_2) + CAM_DBG(CAM_CRM, + "%x: connected: %s, id %d, delay %d, trigger %x", + link_info->u.link_info_v2.session_hdl, + dev->dev_info.name, + dev->dev_info.dev_id, dev->dev_info.p_delay, + dev->dev_info.trigger); + if (rc < 0 || + dev->dev_info.p_delay >= + CAM_PIPELINE_DELAY_MAX || + dev->dev_info.p_delay < + CAM_PIPELINE_DELAY_0) { + CAM_ERR(CAM_CRM, "get device info failed"); + goto error; + } else { + if (link_info->version == VERSION_1) { + CAM_DBG(CAM_CRM, "%x: connected: %s, delay %d", + link_info->u.link_info_v1.session_hdl, + dev->dev_info.name, + dev->dev_info.p_delay); + } + else if (link_info->version == VERSION_2) { + CAM_DBG(CAM_CRM, "%x: connected: %s, delay %d", + link_info->u.link_info_v2.session_hdl, + dev->dev_info.name, + dev->dev_info.p_delay); + } + if (dev->dev_info.p_delay > max_delay) + max_delay = dev->dev_info.p_delay; + + subscribe_event |= (uint32_t)dev->dev_info.trigger; + } + } + + link->subscribe_event = subscribe_event; + link_data.link_enable = 1; + link_data.link_hdl = link->link_hdl; + link_data.crm_cb = &cam_req_mgr_ops; + link_data.max_delay = max_delay; + link_data.subscribe_event = subscribe_event; + + for (i = 0; i < num_devices; i++) { + dev = &link->l_dev[i]; + + link_data.dev_hdl = dev->dev_hdl; + /* + * For unique pipeline delay table create request + * tracking table + */ + if (link->pd_mask & (1 << dev->dev_info.p_delay)) { + pd_tbl = __cam_req_mgr_find_pd_tbl(link->req.l_tbl, + dev->dev_info.p_delay); + if (!pd_tbl) { + CAM_ERR(CAM_CRM, "pd %d tbl not found", + dev->dev_info.p_delay); + rc = -ENXIO; + goto error; + } + } else { + pd_tbl = __cam_req_mgr_create_pd_tbl( + dev->dev_info.p_delay); + if (pd_tbl == NULL) { + CAM_ERR(CAM_CRM, "create new pd tbl failed"); + rc = -ENXIO; + goto error; + } + pd_tbl->pd = dev->dev_info.p_delay; + link->pd_mask |= (1 << pd_tbl->pd); + /* + * Add table to list and also sort list + * from max pd to lowest + */ + __cam_req_mgr_add_tbl_to_link(&link->req.l_tbl, pd_tbl); + } + dev->dev_bit = pd_tbl->dev_count++; + dev->pd_tbl = pd_tbl; + pd_tbl->dev_mask |= (1 << dev->dev_bit); + CAM_DBG(CAM_CRM, "dev_bit %u name %s pd %u mask %d", + dev->dev_bit, dev->dev_info.name, pd_tbl->pd, + pd_tbl->dev_mask); + /* Communicate with dev to establish the link */ + dev->ops->link_setup(&link_data); + + if (link->max_delay < dev->dev_info.p_delay) + link->max_delay = dev->dev_info.p_delay; + } + link->num_devs = num_devices; + + /* Assign id for pd tables */ + __cam_req_mgr_tbl_set_id(link->req.l_tbl, &link->req); + + /* At start, expect max pd devices, all are in skip state */ + __cam_req_mgr_tbl_set_all_skip_cnt(&link->req.l_tbl); + + return 0; + +error: + __cam_req_mgr_destroy_link_info(link); + return rc; +} + +/* IOCTLs handling section */ +int cam_req_mgr_create_session( + struct cam_req_mgr_session_info *ses_info) +{ + int rc = 0; + int32_t session_hdl; + struct cam_req_mgr_core_session *cam_session = NULL; + + if (!ses_info) { + CAM_DBG(CAM_CRM, "NULL session info pointer"); + return -EINVAL; + } + mutex_lock(&g_crm_core_dev->crm_lock); + cam_session = kzalloc(sizeof(*cam_session), + GFP_KERNEL); + if (!cam_session) { + rc = -ENOMEM; + goto end; + } + + session_hdl = cam_create_session_hdl((void *)cam_session); + if (session_hdl < 0) { + CAM_ERR(CAM_CRM, "unable to create session_hdl = %x", + session_hdl); + rc = session_hdl; + kfree(cam_session); + goto end; + } + ses_info->session_hdl = session_hdl; + + mutex_init(&cam_session->lock); + CAM_DBG(CAM_CRM, "LOCK_DBG session lock %pK hdl 0x%x", + &cam_session->lock, session_hdl); + + mutex_lock(&cam_session->lock); + cam_session->session_hdl = session_hdl; + cam_session->num_links = 0; + cam_session->sync_mode = CAM_REQ_MGR_SYNC_MODE_NO_SYNC; + list_add(&cam_session->entry, &g_crm_core_dev->session_head); + mutex_unlock(&cam_session->lock); +end: + mutex_unlock(&g_crm_core_dev->crm_lock); + return rc; +} + +/** + * __cam_req_mgr_unlink() + * + * @brief : Unlink devices on a link structure from the session + * @link : Pointer to the link structure + * + * @return: 0 for success, negative for failure + * + */ +static int __cam_req_mgr_unlink(struct cam_req_mgr_core_link *link) +{ + int rc; + + spin_lock_bh(&link->link_state_spin_lock); + link->state = CAM_CRM_LINK_STATE_IDLE; + spin_unlock_bh(&link->link_state_spin_lock); + + if (!link->is_shutdown) { + rc = __cam_req_mgr_disconnect_link(link); + if (rc) + CAM_ERR(CAM_CORE, + "Unlink for all devices was not successful"); + } + + mutex_lock(&link->lock); + + /* Destroy workq of link */ + cam_req_mgr_workq_destroy(&link->workq); + spin_lock_bh(&link->link_state_spin_lock); + /* Destroy timer of link */ + crm_timer_exit(&link->watchdog); + spin_unlock_bh(&link->link_state_spin_lock); + + /* Cleanup request tables and unlink devices */ + __cam_req_mgr_destroy_link_info(link); + /* Free memory holding data of linked devs */ + + __cam_req_mgr_destroy_subdev(&link->l_dev); + + /* Destroy the link handle */ + rc = cam_destroy_link_hdl(link->link_hdl); + if (rc < 0) { + CAM_ERR(CAM_CRM, "error destroying link hdl %x rc %d", + link->link_hdl, rc); + } else + link->link_hdl = -1; + + mutex_unlock(&link->lock); + return rc; +} + +int cam_req_mgr_destroy_session( + struct cam_req_mgr_session_info *ses_info, + bool is_shutdown) +{ + int rc; + int i; + struct cam_req_mgr_core_session *cam_session = NULL; + struct cam_req_mgr_core_link *link; + + if (!ses_info) { + CAM_DBG(CAM_CRM, "NULL session info pointer"); + return -EINVAL; + } + + mutex_lock(&g_crm_core_dev->crm_lock); + cam_session = cam_get_session_priv(ses_info->session_hdl); + if (!cam_session || (cam_session->session_hdl != ses_info->session_hdl)) { + CAM_ERR(CAM_CRM, "session: %s, ses_info->ses_hdl:%x, session->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), ses_info->session_hdl, + (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : + cam_session->session_hdl); + rc = -ENOENT; + goto end; + + } + if (cam_session->num_links) { + CAM_DBG(CAM_CRM, "destroy session %x num_active_links %d", + ses_info->session_hdl, + cam_session->num_links); + + for (i = 0; i < MAXIMUM_LINKS_PER_SESSION; i++) { + link = cam_session->links[i]; + + if (!link) + continue; + + /* Ignore return value since session is going away */ + link->is_shutdown = is_shutdown; + __cam_req_mgr_unlink(link); + __cam_req_mgr_free_link(link); + } + } + list_del(&cam_session->entry); + mutex_destroy(&cam_session->lock); + kfree(cam_session); + + rc = cam_destroy_session_hdl(ses_info->session_hdl); + if (rc < 0) + CAM_ERR(CAM_CRM, "unable to destroy session_hdl = %x rc %d", + ses_info->session_hdl, rc); + +end: + mutex_unlock(&g_crm_core_dev->crm_lock); + return rc; +} + +int cam_req_mgr_link(struct cam_req_mgr_ver_info *link_info) +{ + int rc = 0; + int wq_flag = 0; + char buf[128]; + struct cam_create_dev_hdl root_dev; + struct cam_req_mgr_core_session *cam_session; + struct cam_req_mgr_core_link *link; + + if (!link_info) { + CAM_DBG(CAM_CRM, "NULL pointer"); + return -EINVAL; + } + if (link_info->u.link_info_v1.num_devices > CAM_REQ_MGR_MAX_HANDLES) { + CAM_ERR(CAM_CRM, "Invalid num devices %d", + link_info->u.link_info_v1.num_devices); + return -EINVAL; + } + + mutex_lock(&g_crm_core_dev->crm_lock); + + /* session hdl's priv data is cam session struct */ + cam_session = cam_get_session_priv(link_info->u.link_info_v1.session_hdl); + if (!cam_session || (cam_session->session_hdl != link_info->u.link_info_v1.session_hdl)) { + CAM_ERR(CAM_CRM, "session: %s, link_info->ses_hdl:%x, session->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), link_info->u.link_info_v1.session_hdl, + (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : cam_session->session_hdl); + mutex_unlock(&g_crm_core_dev->crm_lock); + return -EINVAL; + } + + /* Allocate link struct and map it with session's request queue */ + link = __cam_req_mgr_reserve_link(cam_session); + if (!link) { + CAM_ERR(CAM_CRM, "failed to reserve new link"); + mutex_unlock(&g_crm_core_dev->crm_lock); + return -EINVAL; + } + CAM_DBG(CAM_CRM, "link reserved %pK %x", link, link->link_hdl); + + memset(&root_dev, 0, sizeof(struct cam_create_dev_hdl)); + root_dev.session_hdl = link_info->u.link_info_v1.session_hdl; + root_dev.priv = (void *)link; + root_dev.dev_id = CAM_CRM; + mutex_lock(&link->lock); + /* Create unique handle for link */ + link->link_hdl = cam_create_link_hdl(&root_dev); + if (link->link_hdl < 0) { + CAM_ERR(CAM_CRM, + "Insufficient memory to create new device handle"); + rc = link->link_hdl; + goto link_hdl_fail; + } + link_info->u.link_info_v1.link_hdl = link->link_hdl; + link->last_flush_id = 0; + + /* Allocate memory to hold data of all linked devs */ + rc = __cam_req_mgr_create_subdevs(&link->l_dev, + link_info->u.link_info_v1.num_devices); + if (rc < 0) { + CAM_ERR(CAM_CRM, + "Insufficient memory to create new crm subdevs"); + goto create_subdev_failed; + } + + /* Using device ops query connected devs, prepare request tables */ + rc = __cam_req_mgr_setup_link_info(link, link_info); + if (rc < 0) + goto setup_failed; + + spin_lock_bh(&link->link_state_spin_lock); + link->state = CAM_CRM_LINK_STATE_READY; + spin_unlock_bh(&link->link_state_spin_lock); + + /* Create worker for current link */ + snprintf(buf, sizeof(buf), "%x-%x", + link_info->u.link_info_v1.session_hdl, link->link_hdl); + wq_flag = CAM_WORKQ_FLAG_HIGH_PRIORITY | CAM_WORKQ_FLAG_SERIAL; + rc = cam_req_mgr_workq_create(buf, CRM_WORKQ_NUM_TASKS, + &link->workq, CRM_WORKQ_USAGE_NON_IRQ, wq_flag); + if (rc < 0) { + CAM_ERR(CAM_CRM, "FATAL: unable to create worker"); + __cam_req_mgr_destroy_link_info(link); + goto setup_failed; + } + + /* Assign payload to workqueue tasks */ + rc = __cam_req_mgr_setup_payload(link->workq); + if (rc < 0) { + __cam_req_mgr_destroy_link_info(link); + cam_req_mgr_workq_destroy(&link->workq); + goto setup_failed; + } + + mutex_unlock(&link->lock); + mutex_unlock(&g_crm_core_dev->crm_lock); + return rc; +setup_failed: + __cam_req_mgr_destroy_subdev(&link->l_dev); +create_subdev_failed: + cam_destroy_link_hdl(link->link_hdl); + link_info->u.link_info_v1.link_hdl = -1; +link_hdl_fail: + mutex_unlock(&link->lock); + __cam_req_mgr_unreserve_link(cam_session, link); + mutex_unlock(&g_crm_core_dev->crm_lock); + return rc; +} + +int cam_req_mgr_link_v2(struct cam_req_mgr_ver_info *link_info) +{ + int rc = 0; + int wq_flag = 0; + char buf[128]; + struct cam_create_dev_hdl root_dev; + struct cam_req_mgr_core_session *cam_session; + struct cam_req_mgr_core_link *link; + + if (!link_info) { + CAM_DBG(CAM_CRM, "NULL pointer"); + return -EINVAL; + } + if (link_info->u.link_info_v2.num_devices > + CAM_REQ_MGR_MAX_HANDLES_V2) { + CAM_ERR(CAM_CRM, "Invalid num devices %d", + link_info->u.link_info_v2.num_devices); + return -EINVAL; + } + + mutex_lock(&g_crm_core_dev->crm_lock); + + /* session hdl's priv data is cam session struct */ + cam_session = cam_get_session_priv(link_info->u.link_info_v2.session_hdl); + if (!cam_session || (cam_session->session_hdl != link_info->u.link_info_v2.session_hdl)) { + CAM_ERR(CAM_CRM, "session: %s, link_info->ses_hdl:%x, session->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), link_info->u.link_info_v2.session_hdl, + (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : cam_session->session_hdl); + mutex_unlock(&g_crm_core_dev->crm_lock); + return -EINVAL; + } + + /* Allocate link struct and map it with session's request queue */ + link = __cam_req_mgr_reserve_link(cam_session); + if (!link) { + CAM_ERR(CAM_CRM, "failed to reserve new link"); + mutex_unlock(&g_crm_core_dev->crm_lock); + return -EINVAL; + } + CAM_DBG(CAM_CRM, "link reserved %pK %x", link, link->link_hdl); + + memset(&root_dev, 0, sizeof(struct cam_create_dev_hdl)); + root_dev.session_hdl = link_info->u.link_info_v2.session_hdl; + root_dev.priv = (void *)link; + root_dev.dev_id = CAM_CRM; + + mutex_lock(&link->lock); + /* Create unique handle for link */ + link->link_hdl = cam_create_link_hdl(&root_dev); + if (link->link_hdl < 0) { + CAM_ERR(CAM_CRM, + "Insufficient memory to create new device handle"); + rc = link->link_hdl; + goto link_hdl_fail; + } + link_info->u.link_info_v2.link_hdl = link->link_hdl; + link->last_flush_id = 0; + + /* Allocate memory to hold data of all linked devs */ + rc = __cam_req_mgr_create_subdevs(&link->l_dev, + link_info->u.link_info_v2.num_devices); + if (rc < 0) { + CAM_ERR(CAM_CRM, + "Insufficient memory to create new crm subdevs"); + goto create_subdev_failed; + } + + /* Using device ops query connected devs, prepare request tables */ + rc = __cam_req_mgr_setup_link_info(link, link_info); + if (rc < 0) + goto setup_failed; + + spin_lock_bh(&link->link_state_spin_lock); + link->state = CAM_CRM_LINK_STATE_READY; + spin_unlock_bh(&link->link_state_spin_lock); + + /* Create worker for current link */ + snprintf(buf, sizeof(buf), "%x-%x", + link_info->u.link_info_v2.session_hdl, link->link_hdl); + wq_flag = CAM_WORKQ_FLAG_HIGH_PRIORITY | CAM_WORKQ_FLAG_SERIAL; + rc = cam_req_mgr_workq_create(buf, CRM_WORKQ_NUM_TASKS, + &link->workq, CRM_WORKQ_USAGE_NON_IRQ, wq_flag); + if (rc < 0) { + CAM_ERR(CAM_CRM, "FATAL: unable to create worker"); + __cam_req_mgr_destroy_link_info(link); + goto setup_failed; + } + + /* Assign payload to workqueue tasks */ + rc = __cam_req_mgr_setup_payload(link->workq); + if (rc < 0) { + __cam_req_mgr_destroy_link_info(link); + cam_req_mgr_workq_destroy(&link->workq); + goto setup_failed; + } + + mutex_unlock(&link->lock); + mutex_unlock(&g_crm_core_dev->crm_lock); + return rc; +setup_failed: + __cam_req_mgr_destroy_subdev(&link->l_dev); +create_subdev_failed: + cam_destroy_link_hdl(link->link_hdl); + link_info->u.link_info_v2.link_hdl = -1; +link_hdl_fail: + mutex_unlock(&link->lock); + __cam_req_mgr_unreserve_link(cam_session, link); + mutex_unlock(&g_crm_core_dev->crm_lock); + return rc; +} + + +int cam_req_mgr_unlink(struct cam_req_mgr_unlink_info *unlink_info) +{ + int rc = 0; + struct cam_req_mgr_core_session *cam_session; + struct cam_req_mgr_core_link *link; + + if (!unlink_info) { + CAM_ERR(CAM_CRM, "NULL pointer"); + return -EINVAL; + } + + mutex_lock(&g_crm_core_dev->crm_lock); + CAM_DBG(CAM_CRM, "link_hdl %x", unlink_info->link_hdl); + + /* session hdl's priv data is cam session struct */ + cam_session = cam_get_session_priv(unlink_info->session_hdl); + if (!cam_session || (cam_session->session_hdl != unlink_info->session_hdl)) { + CAM_ERR(CAM_CRM, "session: %s, unlink_info->ses_hdl:%x, cam_session->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), unlink_info->session_hdl, + (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : cam_session->session_hdl); + mutex_unlock(&g_crm_core_dev->crm_lock); + return -EINVAL; + } + + /* link hdl's priv data is core_link struct */ + link = cam_get_link_priv(unlink_info->link_hdl); + if (!link || (link->link_hdl != unlink_info->link_hdl)) { + CAM_ERR(CAM_CRM, "link:%s unlink->lnk_hdl:%x link->lnk_hdl:%x", + CAM_IS_NULL_TO_STR(link), unlink_info->link_hdl, + (!link) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : link->link_hdl); + rc = -EINVAL; + goto done; + } + + rc = __cam_req_mgr_unlink(link); + + /* Free curent link and put back into session's free pool of links */ + __cam_req_mgr_unreserve_link(cam_session, link); + +done: + mutex_unlock(&g_crm_core_dev->crm_lock); + return rc; +} + +int cam_req_mgr_schedule_request( + struct cam_req_mgr_sched_request *sched_req) +{ + int rc = 0; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_core_session *session = NULL; + struct cam_req_mgr_sched_request *sched; + struct crm_task_payload task_data; + + if (!sched_req) { + CAM_ERR(CAM_CRM, "csl_req is NULL"); + return -EINVAL; + } + + mutex_lock(&g_crm_core_dev->crm_lock); + link = cam_get_link_priv(sched_req->link_hdl); + if (!link || (link->link_hdl != sched_req->link_hdl)) { + CAM_ERR(CAM_CRM, "link:%s sched->lnk_hdl:%x link->lnk_hdl:%x", + CAM_IS_NULL_TO_STR(link), sched_req->link_hdl, + (!link) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : link->link_hdl); + rc = -EINVAL; + goto end; + } + + session = (struct cam_req_mgr_core_session *)link->parent; + if (!session) { + CAM_WARN(CAM_CRM, "session ptr NULL %x", sched_req->link_hdl); + rc = -EINVAL; + goto end; + } + + if (sched_req->req_id <= link->last_flush_id) { + CAM_INFO(CAM_CRM, + "request %lld is flushed, last_flush_id to flush %d", + sched_req->req_id, link->last_flush_id); + rc = -EBADR; + goto end; + } + + if (sched_req->req_id > link->last_flush_id) + link->last_flush_id = 0; + + CAM_DBG(CAM_CRM, "link 0x%x req %lld, sync_mode %d", + sched_req->link_hdl, sched_req->req_id, sched_req->sync_mode); + + task_data.type = CRM_WORKQ_TASK_SCHED_REQ; + sched = (struct cam_req_mgr_sched_request *)&task_data.u; + sched->req_id = sched_req->req_id; + sched->sync_mode = sched_req->sync_mode; + sched->link_hdl = sched_req->link_hdl; + sched->additional_timeout = sched_req->additional_timeout; + if (session->force_err_recovery == AUTO_RECOVERY) { + sched->bubble_enable = sched_req->bubble_enable; + } else { + sched->bubble_enable = + (session->force_err_recovery == FORCE_ENABLE_RECOVERY) ? 1 : 0; + } + + rc = cam_req_mgr_process_sched_req(link, &task_data); + + CAM_DBG(CAM_REQ, "Open req %lld on link 0x%x with sync_mode %d", + sched_req->req_id, sched_req->link_hdl, sched_req->sync_mode); +end: + mutex_unlock(&g_crm_core_dev->crm_lock); + return rc; +} + +/** + * __cam_req_mgr_set_master_link() + * + * @brief : Each links sets its max pd delay based on the devices on the + * link. The link with higher pd is assigned master. + * @link1 : One of the sync links + * @link2 : The other sync link + */ +static void __cam_req_mgr_set_master_link( + struct cam_req_mgr_core_link *link1, + struct cam_req_mgr_core_link *link2) +{ + + if (link1->max_delay > link2->max_delay) { + link1->is_master = true; + link2->initial_skip = true; + } else if (link2->max_delay > link1->max_delay) { + link2->is_master = true; + link1->initial_skip = true; + } + + CAM_DBG(CAM_CRM, + "link_hdl1[0x%x] is_master [%u] link_hdl2[0x%x] is_master[%u]", + link1->link_hdl, link1->is_master, + link2->link_hdl, link2->is_master); +} + +int cam_req_mgr_sync_config( + struct cam_req_mgr_sync_mode *sync_info) +{ + int rc = 0; + struct cam_req_mgr_core_session *cam_session; + struct cam_req_mgr_core_link *link1 = NULL; + struct cam_req_mgr_core_link *link2 = NULL; + + if (!sync_info) { + CAM_ERR(CAM_CRM, "NULL pointer"); + return -EINVAL; + } + + if ((sync_info->num_links < 0) || + (sync_info->num_links > + MAX_LINKS_PER_SESSION)) { + CAM_ERR(CAM_CRM, "Invalid num links %d", sync_info->num_links); + return -EINVAL; + } + + if ((sync_info->sync_mode != CAM_REQ_MGR_SYNC_MODE_SYNC) && + (sync_info->sync_mode != CAM_REQ_MGR_SYNC_MODE_NO_SYNC)) { + CAM_ERR(CAM_CRM, "Invalid sync mode %d", sync_info->sync_mode); + return -EINVAL; + } + + if ((!sync_info->link_hdls[0]) || (!sync_info->link_hdls[1])) { + CAM_WARN(CAM_CRM, "Invalid link handles 0x%x 0x%x", + sync_info->link_hdls[0], sync_info->link_hdls[1]); + return -EINVAL; + } + + mutex_lock(&g_crm_core_dev->crm_lock); + /* session hdl's priv data is cam session struct */ + cam_session = cam_get_session_priv(sync_info->session_hdl); + if (!cam_session || (cam_session->session_hdl != sync_info->session_hdl)) { + CAM_ERR(CAM_CRM, "session: %s, sync_info->session_hdl:%x, session->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), sync_info->session_hdl, + (!cam_session) ? + CAM_REQ_MGR_DEFAULT_HDL_VAL : cam_session->session_hdl); + mutex_unlock(&g_crm_core_dev->crm_lock); + return -EINVAL; + } + + mutex_lock(&cam_session->lock); + + CAM_DBG(CAM_CRM, "link handles %x %x", + sync_info->link_hdls[0], sync_info->link_hdls[1]); + + /* only two links existing per session in dual cam use case*/ + link1 = cam_get_link_priv(sync_info->link_hdls[0]); + if (!link1 || (link1->link_hdl != sync_info->link_hdls[0])) { + CAM_ERR(CAM_CRM, "lnk:%s sync_info->lnk_hdl[0]:%x lnk1_hdl:%x", + CAM_IS_NULL_TO_STR(link1), sync_info->link_hdls[0], + (!link1) ? + CAM_REQ_MGR_DEFAULT_HDL_VAL : link1->link_hdl); + rc = -EINVAL; + goto done; + } + + link2 = cam_get_link_priv(sync_info->link_hdls[1]); + if (!link2 || (link2->link_hdl != sync_info->link_hdls[1])) { + CAM_ERR(CAM_CRM, "lnk:%s sync_info->lnk_hdl[1]:%x lnk2_hdl:%x", + CAM_IS_NULL_TO_STR(link2), sync_info->link_hdls[1], + (!link2) ? + CAM_REQ_MGR_DEFAULT_HDL_VAL : link2->link_hdl); + rc = -EINVAL; + goto done; + } + + link1->sync_link_sof_skip = false; + link1->sync_link = NULL; + + link2->sync_link_sof_skip = false; + link2->sync_link = NULL; + + link1->is_master = false; + link2->is_master = false; + + link1->in_msync_mode = false; + link2->in_msync_mode = false; + link1->initial_sync_req = -1; + link2->initial_sync_req = -1; + + if (sync_info->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC) { + link1->sync_link = link2; + link2->sync_link = link1; + __cam_req_mgr_set_master_link(link1, link2); + } else { + /* + * Reset below info after the mode is configured + * to NO-SYNC mode since they may be overridden + * if the sync config is invoked after SOF comes. + */ + link1->initial_skip = true; + link2->initial_skip = true; + link1->sof_timestamp = 0; + link2->sof_timestamp = 0; + } + + cam_session->sync_mode = sync_info->sync_mode; + CAM_DBG(CAM_REQ, + "Sync config on link1 0x%x & link2 0x%x with sync_mode %d", + link1->link_hdl, link2->link_hdl, cam_session->sync_mode); + +done: + mutex_unlock(&cam_session->lock); + mutex_unlock(&g_crm_core_dev->crm_lock); + return rc; +} + +int cam_req_mgr_flush_requests( + struct cam_req_mgr_flush_info *flush_info) +{ + int rc = 0; + struct crm_workq_task *task = NULL; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_flush_info *flush; + struct crm_task_payload *task_data; + struct cam_req_mgr_core_session *session = NULL; + + if (!flush_info) { + CAM_ERR(CAM_CRM, "flush req is NULL"); + return -EFAULT; + } + if (flush_info->flush_type >= CAM_REQ_MGR_FLUSH_TYPE_MAX) { + CAM_ERR(CAM_CRM, "incorrect flush type %x", + flush_info->flush_type); + return -EINVAL; + } + + mutex_lock(&g_crm_core_dev->crm_lock); + + /* session hdl's priv data is cam session struct */ + session = cam_get_session_priv(flush_info->session_hdl); + if (!session || (session->session_hdl != flush_info->session_hdl)) { + CAM_ERR(CAM_CRM, "ses:%s flush->ses_hdl:%x ses->ses_hdl:%x", + CAM_IS_NULL_TO_STR(session), flush_info->session_hdl, + (!session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : + session->session_hdl); + rc = -EINVAL; + goto end; + } + if (session->num_links <= 0) { + CAM_WARN(CAM_CRM, "No active links in session %x", + flush_info->session_hdl); + goto end; + } + + link = cam_get_link_priv(flush_info->link_hdl); + if (!link || (link->link_hdl != flush_info->link_hdl)) { + CAM_ERR(CAM_CRM, "link:%s flush->link_hdl:%x link->link_hdl:%x", + CAM_IS_NULL_TO_STR(link), flush_info->link_hdl, + (!link) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : link->link_hdl); + rc = -EINVAL; + goto end; + } + + task = cam_req_mgr_workq_get_task(link->workq); + if (!task) { + rc = -ENOMEM; + goto end; + } + + task_data = (struct crm_task_payload *)task->payload; + task_data->type = CRM_WORKQ_TASK_FLUSH_REQ; + flush = (struct cam_req_mgr_flush_info *)&task_data->u; + flush->req_id = flush_info->req_id; + flush->link_hdl = flush_info->link_hdl; + flush->flush_type = flush_info->flush_type; + task->process_cb = &cam_req_mgr_process_flush_req; + init_completion(&link->workq_comp); + rc = cam_req_mgr_workq_enqueue_task(task, link, CRM_TASK_PRIORITY_0); + + /* Blocking call */ + rc = wait_for_completion_timeout( + &link->workq_comp, + msecs_to_jiffies(CAM_REQ_MGR_SCHED_REQ_TIMEOUT)); +end: + mutex_unlock(&g_crm_core_dev->crm_lock); + return rc; +} + +int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control) +{ + int rc = 0; + int i, j; + struct cam_req_mgr_core_link *link = NULL; + + struct cam_req_mgr_connected_device *dev = NULL; + struct cam_req_mgr_link_evt_data evt_data; + + if (!control) { + CAM_ERR(CAM_CRM, "Control command is NULL"); + rc = -EINVAL; + goto end; + } + + if ((control->num_links <= 0) || + (control->num_links > MAX_LINKS_PER_SESSION)) { + CAM_ERR(CAM_CRM, "Invalid number of links %d", + control->num_links); + rc = -EINVAL; + goto end; + } + + mutex_lock(&g_crm_core_dev->crm_lock); + for (i = 0; i < control->num_links; i++) { + link = cam_get_link_priv(control->link_hdls[i]); + if (!link || (link->link_hdl != control->link_hdls[i])) { + CAM_ERR(CAM_CRM, + "link:%s control->lnk_hdl:%x link->lnk_hdl:%x", + CAM_IS_NULL_TO_STR(link), control->link_hdls[i], + (!link) ? + CAM_REQ_MGR_DEFAULT_HDL_VAL : link->link_hdl); + rc = -EINVAL; + break; + } + + mutex_lock(&link->lock); + if (control->ops == CAM_REQ_MGR_LINK_ACTIVATE) { + spin_lock_bh(&link->link_state_spin_lock); + link->state = CAM_CRM_LINK_STATE_READY; + spin_unlock_bh(&link->link_state_spin_lock); + /* Start SOF watchdog timer */ + rc = crm_timer_init(&link->watchdog, + CAM_REQ_MGR_WATCHDOG_TIMEOUT_DEFAULT, link, + &__cam_req_mgr_sof_freeze); + if (rc < 0) { + CAM_ERR(CAM_CRM, + "SOF timer start fails: link=0x%x", + link->link_hdl); + rc = -EFAULT; + } + /* notify nodes */ + for (j = 0; j < link->num_devs; j++) { + dev = &link->l_dev[j]; + evt_data.evt_type = CAM_REQ_MGR_LINK_EVT_RESUME; + evt_data.link_hdl = link->link_hdl; + evt_data.dev_hdl = dev->dev_hdl; + evt_data.req_id = 0; + if (dev->ops && dev->ops->process_evt) + dev->ops->process_evt(&evt_data); + } + } else if (control->ops == CAM_REQ_MGR_LINK_DEACTIVATE) { + /* notify nodes */ + for (j = 0; j < link->num_devs; j++) { + dev = &link->l_dev[j]; + evt_data.evt_type = CAM_REQ_MGR_LINK_EVT_PAUSE; + evt_data.link_hdl = link->link_hdl; + evt_data.dev_hdl = dev->dev_hdl; + evt_data.req_id = 0; + if (dev->ops && dev->ops->process_evt) + dev->ops->process_evt(&evt_data); + } + /* Destroy SOF watchdog timer */ + spin_lock_bh(&link->link_state_spin_lock); + link->state = CAM_CRM_LINK_STATE_IDLE; + crm_timer_exit(&link->watchdog); + spin_unlock_bh(&link->link_state_spin_lock); + } else { + CAM_ERR(CAM_CRM, "Invalid link control command"); + rc = -EINVAL; + } + mutex_unlock(&link->lock); + } + mutex_unlock(&g_crm_core_dev->crm_lock); +end: + return rc; +} + +int cam_req_mgr_dump_request(struct cam_dump_req_cmd *dump_req) +{ + int rc = 0; + int i; + struct cam_req_mgr_dump_info info; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_core_session *session = NULL; + struct cam_req_mgr_connected_device *device = NULL; + + if (!dump_req) { + CAM_ERR(CAM_CRM, "dump req is NULL"); + return -EFAULT; + } + + mutex_lock(&g_crm_core_dev->crm_lock); + /* session hdl's priv data is cam session struct */ + session = cam_get_session_priv(dump_req->session_handle); + if (!session || (session->session_hdl != dump_req->session_handle)) { + CAM_ERR(CAM_CRM, "ses:%s dump_req->ses_hdl:%x ses->ses_hdl:%x", + CAM_IS_NULL_TO_STR(session), dump_req->session_handle, + (!session) ? + CAM_REQ_MGR_DEFAULT_HDL_VAL : session->session_hdl); + rc = -EINVAL; + goto end; + } + if (session->num_links <= 0) { + CAM_WARN(CAM_CRM, "No active links in session %x", + dump_req->session_handle); + goto end; + } + + link = cam_get_link_priv(dump_req->link_hdl); + if (!link || (link->link_hdl != dump_req->link_hdl)) { + CAM_ERR(CAM_CRM, "link:%s dump_rq->lnk_hdl:%x link->lnk_hdl:%x", + CAM_IS_NULL_TO_STR(link), dump_req->link_hdl, + (!link) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : link->link_hdl); + rc = -EINVAL; + goto end; + } + info.offset = dump_req->offset; + for (i = 0; i < link->num_devs; i++) { + device = &link->l_dev[i]; + info.link_hdl = dump_req->link_hdl; + info.dev_hdl = device->dev_hdl; + info.req_id = dump_req->issue_req_id; + info.buf_handle = dump_req->buf_handle; + info.error_type = dump_req->error_type; + if (device->ops && device->ops->dump_req) { + rc = device->ops->dump_req(&info); + if (rc) + CAM_ERR(CAM_REQ, + "Fail dump req %llu dev %d rc %d", + info.req_id, device->dev_hdl, rc); + } + } + dump_req->offset = info.offset; + CAM_INFO(CAM_REQ, "req %llu, offset %zu", + dump_req->issue_req_id, dump_req->offset); +end: + mutex_unlock(&g_crm_core_dev->crm_lock); + return 0; +} + +int cam_req_mgr_core_device_init(void) +{ + int i; + CAM_DBG(CAM_CRM, "Enter g_crm_core_dev %pK", g_crm_core_dev); + + if (g_crm_core_dev) { + CAM_WARN(CAM_CRM, "core device is already initialized"); + return 0; + } + g_crm_core_dev = kzalloc(sizeof(*g_crm_core_dev), + GFP_KERNEL); + if (!g_crm_core_dev) + return -ENOMEM; + + CAM_DBG(CAM_CRM, "g_crm_core_dev %pK", g_crm_core_dev); + INIT_LIST_HEAD(&g_crm_core_dev->session_head); + mutex_init(&g_crm_core_dev->crm_lock); + cam_req_mgr_debug_register(g_crm_core_dev); + + for (i = 0; i < MAXIMUM_LINKS_PER_SESSION; i++) { + mutex_init(&g_links[i].lock); + spin_lock_init(&g_links[i].link_state_spin_lock); + atomic_set(&g_links[i].is_used, 0); + cam_req_mgr_core_link_reset(&g_links[i]); + } + return 0; +} + +int cam_req_mgr_core_device_deinit(void) +{ + if (!g_crm_core_dev) { + CAM_ERR(CAM_CRM, "NULL pointer"); + return -EINVAL; + } + + CAM_DBG(CAM_CRM, "g_crm_core_dev %pK", g_crm_core_dev); + mutex_destroy(&g_crm_core_dev->crm_lock); + kfree(g_crm_core_dev); + g_crm_core_dev = NULL; + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_core.h b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_core.h new file mode 100644 index 0000000000000000000000000000000000000000..c638f4f796ecc1b346325bcd87be3290b54244e1 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_core.h @@ -0,0 +1,523 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef _CAM_REQ_MGR_CORE_H_ +#define _CAM_REQ_MGR_CORE_H_ + +#include +#include "cam_req_mgr_interface.h" +#include "cam_req_mgr_core_defs.h" +#include "cam_req_mgr_timer.h" + +#define CAM_REQ_MGR_MAX_LINKED_DEV 16 +#define MAX_REQ_SLOTS 48 + +#define CAM_REQ_MGR_WATCHDOG_TIMEOUT 1000 +#define CAM_REQ_MGR_WATCHDOG_TIMEOUT_DEFAULT 5000 +#define CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX 50000 +#define CAM_REQ_MGR_SCHED_REQ_TIMEOUT 1000 +#define CAM_REQ_MGR_SIMULATE_SCHED_REQ 30 +#define CAM_REQ_MGR_DEFAULT_HDL_VAL 0 + +#define FORCE_DISABLE_RECOVERY 2 +#define FORCE_ENABLE_RECOVERY 1 +#define AUTO_RECOVERY 0 + +#define CRM_WORKQ_NUM_TASKS 60 + +#define MAX_SYNC_COUNT 65535 + +/* Default frame rate is 30 */ +#define DEFAULT_FRAME_DURATION 33333333 + +#define SYNC_LINK_SOF_CNT_MAX_LMT 1 + +#define MAXIMUM_LINKS_PER_SESSION 4 + +#define MAXIMUM_RETRY_ATTEMPTS 2 + +#define MINIMUM_WORKQUEUE_SCHED_TIME_IN_MS 5 + +#define VERSION_1 1 +#define VERSION_2 2 + +/** + * enum crm_workq_task_type + * @codes: to identify which type of task is present + */ +enum crm_workq_task_type { + CRM_WORKQ_TASK_GET_DEV_INFO, + CRM_WORKQ_TASK_SETUP_LINK, + CRM_WORKQ_TASK_DEV_ADD_REQ, + CRM_WORKQ_TASK_APPLY_REQ, + CRM_WORKQ_TASK_NOTIFY_SOF, + CRM_WORKQ_TASK_NOTIFY_ERR, + CRM_WORKQ_TASK_NOTIFY_FREEZE, + CRM_WORKQ_TASK_SCHED_REQ, + CRM_WORKQ_TASK_FLUSH_REQ, + CRM_WORKQ_TASK_INVALID, +}; + +/** + * struct crm_task_payload + * @type : to identify which type of task is present + * @u : union of payload of all types of tasks supported + * @sched_req : contains info of incoming reqest from CSL to CRM + * @flush_info : contains info of cancelled reqest + * @dev_req : contains tracking info of available req id at device + * @send_req : contains info of apply settings to be sent to devs in link + * @apply_req : contains info of which request is applied at device + * @notify_trigger : contains notification from IFE to CRM about trigger + * @notify_err : contains error info happened while processing request + * - + */ +struct crm_task_payload { + enum crm_workq_task_type type; + union { + struct cam_req_mgr_sched_request sched_req; + struct cam_req_mgr_flush_info flush_info; + struct cam_req_mgr_add_request dev_req; + struct cam_req_mgr_send_request send_req; + struct cam_req_mgr_trigger_notify notify_trigger; + struct cam_req_mgr_error_notify notify_err; + } u; +}; + +/** + * enum crm_req_state + * State machine for life cycle of request in pd table + * EMPTY : indicates req slot is empty + * PENDING : indicates req slot is waiting for reqs from all devs + * READY : indicates req slot is ready to be sent to devs + * INVALID : indicates req slot is not in valid state + */ +enum crm_req_state { + CRM_REQ_STATE_EMPTY, + CRM_REQ_STATE_PENDING, + CRM_REQ_STATE_READY, + CRM_REQ_STATE_INVALID, +}; + +/** + * enum crm_slot_status + * State machine for life cycle of request in input queue + * NO_REQ : empty slot + * REQ_ADDED : new entry in slot + * PENDING : waiting for next trigger to apply + * APPLIED : req is sent to all devices + * INVALID : invalid state + */ +enum crm_slot_status { + CRM_SLOT_STATUS_NO_REQ, + CRM_SLOT_STATUS_REQ_ADDED, + CRM_SLOT_STATUS_REQ_PENDING, + CRM_SLOT_STATUS_REQ_APPLIED, + CRM_SLOT_STATUS_INVALID, +}; + +/** + * enum cam_req_mgr_link_state + * State machine for life cycle of link in crm + * AVAILABLE : link available + * IDLE : link initialized but not ready yet + * READY : link is ready for use + * ERR : link has encountered error + * MAX : invalid state + */ +enum cam_req_mgr_link_state { + CAM_CRM_LINK_STATE_AVAILABLE, + CAM_CRM_LINK_STATE_IDLE, + CAM_CRM_LINK_STATE_READY, + CAM_CRM_LINK_STATE_ERR, + CAM_CRM_LINK_STATE_MAX, +}; + +/** + * struct cam_req_mgr_traverse_result + * @req_id : Req id that is not ready + * @pd : pipeline delay + * @masked_value : Holds the dev bit for devices not ready + * for the given request + */ +struct cam_req_mgr_traverse_result { + int64_t req_id; + uint32_t pd; + uint32_t masked_value; +}; + +/** + * struct cam_req_mgr_traverse + * @idx : slot index + * @result : contains which all tables were able to apply successfully + * @result_data : holds the result of traverse in case it fails + * @tbl : pointer of pipeline delay based request table + * @apply_data : pointer which various tables will update during traverse + * @in_q : input request queue pointer + * @validate_only : Whether to validate only and/or update settings + * @open_req_cnt : Count of open requests yet to be serviced in the kernel. + */ +struct cam_req_mgr_traverse { + int32_t idx; + uint32_t result; + struct cam_req_mgr_traverse_result result_data; + struct cam_req_mgr_req_tbl *tbl; + struct cam_req_mgr_apply *apply_data; + struct cam_req_mgr_req_queue *in_q; + bool validate_only; + int32_t open_req_cnt; +}; + +/** + * struct cam_req_mgr_apply + * @idx : corresponding input queue slot index + * @pd : pipeline delay of device + * @req_id : req id for dev with above pd to process + * @skip_idx: skip applying settings when this is set. + */ +struct cam_req_mgr_apply { + int32_t idx; + int32_t pd; + int64_t req_id; + int32_t skip_idx; +}; + +/** + * struct cam_req_mgr_tbl_slot + * @idx : slot index + * @req_ready_map : mask tracking which all devices have request ready + * @state : state machine for life cycle of a slot + * @inject_delay : insert extra bubbling for flash type of use cases + * @dev_hdl : stores the dev_hdl, who is having higher inject delay + * @skip_next_frame : flag to drop the frame after skip_before_apply frame + * @is_applied : flag to identify if request is already applied to + * device. + */ +struct cam_req_mgr_tbl_slot { + int32_t idx; + uint32_t req_ready_map; + enum crm_req_state state; + uint32_t inject_delay; + int32_t dev_hdl; + bool skip_next_frame; + bool is_applied; +}; + +/** + * struct cam_req_mgr_req_tbl + * @id : table indetifier + * @pd : pipeline delay of table + * @dev_count : num of devices having same pipeline delay + * @dev_mask : mask to track which devices are linked + * @skip_traverse : to indicate how many traverses need to be dropped + * by this table especially in the beginning or bubble recovery + * @next : pointer to next pipeline delay request table + * @pd_delta : differnce between this table's pipeline delay and next + * @num_slots : number of request slots present in the table + * @slot : array of slots tracking requests availability at devices + */ +struct cam_req_mgr_req_tbl { + int32_t id; + int32_t pd; + int32_t dev_count; + int32_t dev_mask; + int32_t skip_traverse; + struct cam_req_mgr_req_tbl *next; + int32_t pd_delta; + int32_t num_slots; + struct cam_req_mgr_tbl_slot slot[MAX_REQ_SLOTS]; +}; + +/** + * struct cam_req_mgr_slot + * - Internal Book keeping + * @idx : slot index + * @skip_idx : if req id in this slot needs to be skipped/not applied + * @status : state machine for life cycle of a slot + * - members updated due to external events + * @recover : if user enabled recovery for this request. + * @req_id : mask tracking which all devices have request ready + * @sync_mode : Sync mode in which req id in this slot has to applied + * @additional_timeout : Adjusted watchdog timeout value associated with + * this request + */ +struct cam_req_mgr_slot { + int32_t idx; + int32_t skip_idx; + enum crm_slot_status status; + int32_t recover; + int64_t req_id; + int32_t sync_mode; + int32_t additional_timeout; +}; + +/** + * struct cam_req_mgr_req_queue + * @num_slots : max num of input queue slots + * @slot : request slot holding incoming request id and bubble info. + * @rd_idx : indicates slot index currently in process. + * @wr_idx : indicates slot index to hold new upcoming req. + * @last_applied_idx : indicates slot index last applied successfully. + */ +struct cam_req_mgr_req_queue { + int32_t num_slots; + struct cam_req_mgr_slot slot[MAX_REQ_SLOTS]; + int32_t rd_idx; + int32_t wr_idx; + int32_t last_applied_idx; +}; + +/** + * struct cam_req_mgr_req_data + * @in_q : Poiner to Input request queue + * @l_tbl : unique pd request tables. + * @num_tbl : how many unique pd value devices are present + * @apply_data : Holds information about request id for a request + * @lock : mutex lock protecting request data ops. + */ +struct cam_req_mgr_req_data { + struct cam_req_mgr_req_queue *in_q; + struct cam_req_mgr_req_tbl *l_tbl; + int32_t num_tbl; + struct cam_req_mgr_apply apply_data[CAM_PIPELINE_DELAY_MAX]; + struct mutex lock; +}; + +/** + * struct cam_req_mgr_connected_device + * - Device Properties + * @dev_hdl : device handle + * @dev_bit : unique bit assigned to device in link + * - Device characteristics + * @pd_tbl : tracks latest available req id at this device + * @dev_info : holds dev characteristics such as pipeline delay, dev name + * @ops : holds func pointer to call methods on this device + * @parent : pvt data - like link which this dev hdl belongs to + */ +struct cam_req_mgr_connected_device { + int32_t dev_hdl; + int64_t dev_bit; + struct cam_req_mgr_req_tbl *pd_tbl; + struct cam_req_mgr_device_info dev_info; + struct cam_req_mgr_kmd_ops *ops; + void *parent; +}; + +/** + * struct cam_req_mgr_core_link + * - Link Properties + * @link_hdl : Link identifier + * @num_devs : num of connected devices to this link + * @max_delay : Max of pipeline delay of all connected devs + * @workq : Pointer to handle workq related jobs + * @pd_mask : each set bit indicates the device with pd equal to + * bit position is available. + * - List of connected devices + * @l_dev : List of connected devices to this link + * - Request handling data struct + * @req : req data holder. + * - Timer + * @watchdog : watchdog timer to recover from sof freeze + * - Link private data + * @workq_comp : conditional variable to block user thread for workq + * to finish schedule request processing + * @state : link state machine + * @parent : pvt data - link's parent is session + * @lock : mutex lock to guard link data operations + * @link_state_spin_lock : spin lock to protect link state variable + * @subscribe_event : irqs that link subscribes, IFE should send + * notification to CRM at those hw events. + * @trigger_mask : mask on which irq the req is already applied + * @sync_link : pointer to the sync link for synchronization + * @sync_link_sof_skip : flag determines if a pkt is not available for a given + * frame in a particular link skip corresponding + * frame in sync link as well. + * @open_req_cnt : Counter to keep track of open requests that are yet + * to be serviced in the kernel. + * @last_flush_id : Last request to flush + * @is_used : 1 if link is in use else 0 + * @is_master : Based on pd among links, the link with the highest pd + * is assigned as master + * @initial_skip : Flag to determine if slave has started streaming in + * master-slave sync + * @in_msync_mode : Flag to determine if a link is in master-slave mode + * @initial_sync_req : The initial req which is required to sync with the + * other link + * @retry_cnt : Counter that tracks number of attempts to apply + * the same req + * @is_shutdown : Flag to indicate if link needs to be disconnected + * as part of shutdown. + * @sof_timestamp_value : SOF timestamp value + * @prev_sof_timestamp : Previous SOF timestamp value + * @last_sof_trigger_jiffies : Record the jiffies of last sof trigger jiffies + * @wq_congestion : Indicates if WQ congestion is detected or not + */ +struct cam_req_mgr_core_link { + int32_t link_hdl; + int32_t num_devs; + enum cam_pipeline_delay max_delay; + struct cam_req_mgr_core_workq *workq; + int32_t pd_mask; + struct cam_req_mgr_connected_device *l_dev; + struct cam_req_mgr_req_data req; + struct cam_req_mgr_timer *watchdog; + struct completion workq_comp; + enum cam_req_mgr_link_state state; + void *parent; + struct mutex lock; + spinlock_t link_state_spin_lock; + uint32_t subscribe_event; + uint32_t trigger_mask; + struct cam_req_mgr_core_link *sync_link; + bool sync_link_sof_skip; + int32_t open_req_cnt; + uint32_t last_flush_id; + atomic_t is_used; + bool is_master; + bool initial_skip; + bool in_msync_mode; + int64_t initial_sync_req; + uint32_t retry_cnt; + bool is_shutdown; + uint64_t sof_timestamp; + uint64_t prev_sof_timestamp; + uint64_t last_sof_trigger_jiffies; + bool wq_congestion; +}; + +/** + * struct cam_req_mgr_core_session + * - Session Properties + * @session_hdl : session identifier + * @num_links : num of active links for current session + * - Links of this session + * @links : pointer to array of links within session + * @in_q : Input request queue one per session + * - Session private data + * @entry : pvt data - entry in the list of sessions + * @lock : pvt data - spin lock to guard session data + * - Debug data + * @force_err_recovery : For debugging, we can force bubble recovery + * to be always ON or always OFF using debugfs. + * @sync_mode : Sync mode for this session links + */ +struct cam_req_mgr_core_session { + int32_t session_hdl; + uint32_t num_links; + struct cam_req_mgr_core_link *links[MAXIMUM_LINKS_PER_SESSION]; + struct list_head entry; + struct mutex lock; + int32_t force_err_recovery; + int32_t sync_mode; +}; + +/** + * struct cam_req_mgr_core_device + * - Core camera request manager data struct + * @session_head : list head holding sessions + * @crm_lock : mutex lock to protect session creation & destruction + */ +struct cam_req_mgr_core_device { + struct list_head session_head; + struct mutex crm_lock; +}; + +/** + * cam_req_mgr_create_session() + * @brief : creates session + * @ses_info : output param for session handle + * + * called as part of session creation. + */ +int cam_req_mgr_create_session(struct cam_req_mgr_session_info *ses_info); + +/** + * cam_req_mgr_destroy_session() + * @brief : destroy session + * @ses_info : session handle info, input param + * @is_shutdown: To indicate if devices on link need to be disconnected. + * + * Called as part of session destroy + * return success/failure + */ +int cam_req_mgr_destroy_session(struct cam_req_mgr_session_info *ses_info, + bool is_shutdown); + +/** + * cam_req_mgr_link() + * @brief : creates a link for a session + * @link_info : handle and session info to create a link + * + * link is formed in a session for multiple devices. it creates + * a unique link handle for the link and is specific to a + * session. Returns link handle + */ +int cam_req_mgr_link(struct cam_req_mgr_ver_info *link_info); +int cam_req_mgr_link_v2(struct cam_req_mgr_ver_info *link_info); + + +/** + * cam_req_mgr_unlink() + * @brief : destroy a link in a session + * @unlink_info : session and link handle info + * + * link is destroyed in a session + */ +int cam_req_mgr_unlink(struct cam_req_mgr_unlink_info *unlink_info); + +/** + * cam_req_mgr_schedule_request() + * @brief: Request is scheduled + * @sched_req: request id, session and link id info, bubble recovery info + */ +int cam_req_mgr_schedule_request( + struct cam_req_mgr_sched_request *sched_req); + +/** + * cam_req_mgr_sync_mode_setup() + * @brief: sync for links in a session + * @sync_info: session, links info and master link info + */ +int cam_req_mgr_sync_config(struct cam_req_mgr_sync_mode *sync_info); + +/** + * cam_req_mgr_flush_requests() + * @brief: flush all requests + * @flush_info: requests related to link and session + */ +int cam_req_mgr_flush_requests( + struct cam_req_mgr_flush_info *flush_info); + +/** + * cam_req_mgr_core_device_init() + * @brief: initialize crm core + */ +int cam_req_mgr_core_device_init(void); + +/** + * cam_req_mgr_core_device_deinit() + * @brief: cleanp crm core + */ +int cam_req_mgr_core_device_deinit(void); + +/** + * cam_req_mgr_handle_core_shutdown() + * @brief: Handles camera close + */ +void cam_req_mgr_handle_core_shutdown(void); + +/** + * cam_req_mgr_link_control() + * @brief: Handles link control operations + * @control: Link control command + */ +int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control); + +/** + * cam_req_mgr_dump_request() + * @brief: Dumps the request information + * @dump_req: Dump request + */ +int cam_req_mgr_dump_request(struct cam_dump_req_cmd *dump_req); +#endif diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_core_defs.h b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_core_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..fbaa7de494f7225125d60c94bafe57ada0f70adb --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_core_defs.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + */ +#ifndef _CAM_REQ_MGR_CORE_DEFS_H_ +#define _CAM_REQ_MGR_CORE_DEFS_H_ + +#define CRM_TRACE_ENABLE 0 +#define CRM_DEBUG_MUTEX 0 + +#define SET_SUCCESS_BIT(ret, pd) (ret |= (1 << (pd))) + +#define SET_FAILURE_BIT(ret, pd) (ret &= (~(1 << (pd)))) + +#define CRM_GET_REQ_ID(in_q, idx) in_q->slot[idx].req_id + +#endif diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_debug.c b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_debug.c new file mode 100644 index 0000000000000000000000000000000000000000..5de86c66b360717ae1e85b1cb5481caa1fff06eb --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_debug.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + */ + +#include "cam_req_mgr_debug.h" + +#define MAX_SESS_INFO_LINE_BUFF_LEN 256 + +static char sess_info_buffer[MAX_SESS_INFO_LINE_BUFF_LEN]; +static int cam_debug_mgr_delay_detect; + +static int cam_req_mgr_debug_set_bubble_recovery(void *data, u64 val) +{ + struct cam_req_mgr_core_device *core_dev = data; + struct cam_req_mgr_core_session *session; + int rc = 0; + + mutex_lock(&core_dev->crm_lock); + + if (!list_empty(&core_dev->session_head)) { + list_for_each_entry(session, + &core_dev->session_head, entry) { + session->force_err_recovery = val; + } + } + + mutex_unlock(&core_dev->crm_lock); + + return rc; +} + +static int cam_req_mgr_debug_get_bubble_recovery(void *data, u64 *val) +{ + struct cam_req_mgr_core_device *core_dev = data; + struct cam_req_mgr_core_session *session; + + mutex_lock(&core_dev->crm_lock); + + if (!list_empty(&core_dev->session_head)) { + session = list_first_entry(&core_dev->session_head, + struct cam_req_mgr_core_session, + entry); + *val = session->force_err_recovery; + } + mutex_unlock(&core_dev->crm_lock); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(bubble_recovery, cam_req_mgr_debug_get_bubble_recovery, + cam_req_mgr_debug_set_bubble_recovery, "%lld\n"); + +static int session_info_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static ssize_t session_info_read(struct file *t_file, char *t_char, + size_t t_size_t, loff_t *t_loff_t) +{ + int i; + char *out_buffer = sess_info_buffer; + char line_buffer[MAX_SESS_INFO_LINE_BUFF_LEN] = {0}; + struct cam_req_mgr_core_device *core_dev = + (struct cam_req_mgr_core_device *) t_file->private_data; + struct cam_req_mgr_core_session *session; + + memset(out_buffer, 0, MAX_SESS_INFO_LINE_BUFF_LEN); + + mutex_lock(&core_dev->crm_lock); + + if (!list_empty(&core_dev->session_head)) { + list_for_each_entry(session, + &core_dev->session_head, entry) { + snprintf(line_buffer, sizeof(line_buffer), + "session_hdl = %x \t" + "num_links = %d\n", + session->session_hdl, session->num_links); + strlcat(out_buffer, line_buffer, + sizeof(sess_info_buffer)); + for (i = 0; i < session->num_links; i++) { + snprintf(line_buffer, sizeof(line_buffer), + "link_hdl[%d] = 0x%x, num_devs connected = %d\n", + i, session->links[i]->link_hdl, + session->links[i]->num_devs); + strlcat(out_buffer, line_buffer, + sizeof(sess_info_buffer)); + } + } + } + + mutex_unlock(&core_dev->crm_lock); + + return simple_read_from_buffer(t_char, t_size_t, + t_loff_t, out_buffer, strlen(out_buffer)); +} + +static ssize_t session_info_write(struct file *t_file, + const char *t_char, size_t t_size_t, loff_t *t_loff_t) +{ + memset(sess_info_buffer, 0, MAX_SESS_INFO_LINE_BUFF_LEN); + + return 0; +} + +static const struct file_operations session_info = { + .open = session_info_open, + .read = session_info_read, + .write = session_info_write, +}; + +int cam_req_mgr_debug_register(struct cam_req_mgr_core_device *core_dev) +{ + struct dentry *debugfs_root; + char dirname[32] = {0}; + + snprintf(dirname, sizeof(dirname), "cam_req_mgr"); + debugfs_root = debugfs_create_dir(dirname, NULL); + if (!debugfs_root) + return -ENOMEM; + + if (!debugfs_create_file("sessions_info", 0644, + debugfs_root, core_dev, &session_info)) + return -ENOMEM; + + if (!debugfs_create_file("bubble_recovery", 0644, + debugfs_root, core_dev, &bubble_recovery)) + return -ENOMEM; + + if (!debugfs_create_u32("delay_detect_count", 0644, + debugfs_root, &cam_debug_mgr_delay_detect)) + return -ENOMEM; + + return 0; +} + +void cam_req_mgr_debug_delay_detect(void) +{ + cam_debug_mgr_delay_detect += 1; +} diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_debug.h b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_debug.h new file mode 100644 index 0000000000000000000000000000000000000000..ff169baed74ceb334fd32423dd96e1a3b4f954bc --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_debug.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_REQ_MGR_DEBUG_H_ +#define _CAM_REQ_MGR_DEBUG_H_ + +#include +#include "cam_req_mgr_core.h" + +int cam_req_mgr_debug_register(struct cam_req_mgr_core_device *core_dev); + +/* cam_req_mgr_debug_delay_detect() + * @brief : increment debug_fs varaible by 1 whenever delay occurred. + */ +void cam_req_mgr_debug_delay_detect(void); +#endif diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_dev.c b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..1d2373ef7b09c73bf062f06de187c1473047b70a --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_dev.c @@ -0,0 +1,922 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include "cam_req_mgr_dev.h" +#include "cam_req_mgr_util.h" +#include "cam_req_mgr_core.h" +#include "cam_subdev.h" +#include "cam_mem_mgr.h" +#include "cam_debug_util.h" +#include "cam_common_util.h" + +#define CAM_REQ_MGR_EVENT_MAX 30 + +static struct cam_req_mgr_device g_dev; +struct kmem_cache *g_cam_req_mgr_timer_cachep; + +DECLARE_RWSEM(rwsem_lock); + +static int cam_media_device_setup(struct device *dev) +{ + int rc; + + g_dev.v4l2_dev->mdev = kzalloc(sizeof(*g_dev.v4l2_dev->mdev), + GFP_KERNEL); + if (!g_dev.v4l2_dev->mdev) { + rc = -ENOMEM; + goto mdev_fail; + } + + media_device_init(g_dev.v4l2_dev->mdev); + g_dev.v4l2_dev->mdev->dev = dev; + strlcpy(g_dev.v4l2_dev->mdev->model, CAM_REQ_MGR_VNODE_NAME, + sizeof(g_dev.v4l2_dev->mdev->model)); + + rc = media_device_register(g_dev.v4l2_dev->mdev); + if (rc) + goto media_fail; + + return rc; + +media_fail: + kfree(g_dev.v4l2_dev->mdev); + g_dev.v4l2_dev->mdev = NULL; +mdev_fail: + return rc; +} + +static void cam_media_device_cleanup(void) +{ + media_entity_cleanup(&g_dev.video->entity); + media_device_unregister(g_dev.v4l2_dev->mdev); + kfree(g_dev.v4l2_dev->mdev); + g_dev.v4l2_dev->mdev = NULL; +} + +static int cam_v4l2_device_setup(struct device *dev) +{ + int rc; + + g_dev.v4l2_dev = kzalloc(sizeof(*g_dev.v4l2_dev), + GFP_KERNEL); + if (!g_dev.v4l2_dev) + return -ENOMEM; + + rc = v4l2_device_register(dev, g_dev.v4l2_dev); + if (rc) + goto reg_fail; + + return rc; + +reg_fail: + kfree(g_dev.v4l2_dev); + g_dev.v4l2_dev = NULL; + return rc; +} + +static void cam_v4l2_device_cleanup(void) +{ + v4l2_device_unregister(g_dev.v4l2_dev); + kfree(g_dev.v4l2_dev); + g_dev.v4l2_dev = NULL; +} + +void cam_req_mgr_rwsem_read_op(enum cam_subdev_rwsem lock) +{ + if (lock == CAM_SUBDEV_LOCK) + down_read(&rwsem_lock); + else if (lock == CAM_SUBDEV_UNLOCK) + up_read(&rwsem_lock); +} + +static void cam_req_mgr_rwsem_write_op(enum cam_subdev_rwsem lock) +{ + if (lock == CAM_SUBDEV_LOCK) + down_write(&rwsem_lock); + else if (lock == CAM_SUBDEV_UNLOCK) + up_write(&rwsem_lock); +} + +static int cam_req_mgr_open(struct file *filep) +{ + int rc; + + cam_req_mgr_rwsem_write_op(CAM_SUBDEV_LOCK); + + mutex_lock(&g_dev.cam_lock); + if (g_dev.open_cnt >= 1) { + rc = -EALREADY; + goto end; + } + + rc = v4l2_fh_open(filep); + if (rc) { + CAM_ERR(CAM_CRM, "v4l2_fh_open failed: %d", rc); + goto end; + } + + spin_lock_bh(&g_dev.cam_eventq_lock); + g_dev.cam_eventq = filep->private_data; + spin_unlock_bh(&g_dev.cam_eventq_lock); + + g_dev.open_cnt++; + rc = cam_mem_mgr_init(); + if (rc) { + g_dev.open_cnt--; + CAM_ERR(CAM_CRM, "mem mgr init failed"); + goto mem_mgr_init_fail; + } + + mutex_unlock(&g_dev.cam_lock); + cam_req_mgr_rwsem_write_op(CAM_SUBDEV_UNLOCK); + return rc; + +mem_mgr_init_fail: + v4l2_fh_release(filep); +end: + mutex_unlock(&g_dev.cam_lock); + cam_req_mgr_rwsem_write_op(CAM_SUBDEV_UNLOCK); + return rc; +} + +static unsigned int cam_req_mgr_poll(struct file *f, + struct poll_table_struct *pll_table) +{ + int rc = 0; + struct v4l2_fh *eventq = f->private_data; + + if (!eventq) + return -EINVAL; + + poll_wait(f, &eventq->wait, pll_table); + if (v4l2_event_pending(eventq)) + rc = POLLPRI; + + return rc; +} + +static int cam_req_mgr_close(struct file *filep) +{ + struct v4l2_subdev *sd; + struct v4l2_fh *vfh = filep->private_data; + struct v4l2_subdev_fh *subdev_fh = to_v4l2_subdev_fh(vfh); + + CAM_WARN(CAM_CRM, + "release invoked associated userspace process has died, open_cnt: %d", + g_dev.open_cnt); + + cam_req_mgr_rwsem_write_op(CAM_SUBDEV_LOCK); + + mutex_lock(&g_dev.cam_lock); + + if (g_dev.open_cnt <= 0) { + mutex_unlock(&g_dev.cam_lock); + cam_req_mgr_rwsem_write_op(CAM_SUBDEV_UNLOCK); + return -EINVAL; + } + + cam_req_mgr_handle_core_shutdown(); + + list_for_each_entry(sd, &g_dev.v4l2_dev->subdevs, list) { + if (!(sd->flags & V4L2_SUBDEV_FL_HAS_DEVNODE)) + continue; + if (sd->internal_ops && sd->internal_ops->close) { + CAM_DBG(CAM_CRM, "Invoke subdev close for device %s", + sd->name); + sd->internal_ops->close(sd, subdev_fh); + } + } + + g_dev.open_cnt--; + v4l2_fh_release(filep); + + spin_lock_bh(&g_dev.cam_eventq_lock); + g_dev.cam_eventq = NULL; + spin_unlock_bh(&g_dev.cam_eventq_lock); + + cam_req_mgr_util_free_hdls(); + cam_mem_mgr_deinit(); + mutex_unlock(&g_dev.cam_lock); + + cam_req_mgr_rwsem_write_op(CAM_SUBDEV_UNLOCK); + + return 0; +} + +static struct v4l2_file_operations g_cam_fops = { + .owner = THIS_MODULE, + .open = cam_req_mgr_open, + .poll = cam_req_mgr_poll, + .release = cam_req_mgr_close, + .unlocked_ioctl = video_ioctl2, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = video_ioctl2, +#endif +}; + +static void cam_v4l2_event_queue_notify_error(const struct v4l2_event *old, + struct v4l2_event *new) +{ + struct cam_req_mgr_message *ev_header; + + ev_header = CAM_REQ_MGR_GET_PAYLOAD_PTR((*old), + struct cam_req_mgr_message); + + switch (old->id) { + case V4L_EVENT_CAM_REQ_MGR_SOF: + case V4L_EVENT_CAM_REQ_MGR_SOF_BOOT_TS: + if (ev_header->u.frame_msg.request_id) + CAM_ERR(CAM_CRM, + "Failed to notify %s Sess %X FrameId %lld FrameMeta %d ReqId %lld link %X", + ((old->id == V4L_EVENT_CAM_REQ_MGR_SOF) ? + "SOF_TS" : "BOOT_TS"), + ev_header->session_hdl, + ev_header->u.frame_msg.frame_id, + ev_header->u.frame_msg.frame_id_meta, + ev_header->u.frame_msg.request_id, + ev_header->u.frame_msg.link_hdl); + else + CAM_WARN_RATE_LIMIT_CUSTOM(CAM_CRM, 5, 1, + "Failed to notify %s Sess %X FrameId %lld FrameMeta %d ReqId %lld link %X", + ((old->id == V4L_EVENT_CAM_REQ_MGR_SOF) ? + "SOF_TS" : "BOOT_TS"), + ev_header->session_hdl, + ev_header->u.frame_msg.frame_id, + ev_header->u.frame_msg.frame_id_meta, + ev_header->u.frame_msg.request_id, + ev_header->u.frame_msg.link_hdl); + break; + case V4L_EVENT_CAM_REQ_MGR_ERROR: + CAM_ERR(CAM_CRM, + "Failed to notify ERROR Sess %X ReqId %d Link %X Type %d", + ev_header->session_hdl, + ev_header->u.err_msg.request_id, + ev_header->u.err_msg.link_hdl, + ev_header->u.err_msg.error_type); + break; + default: + CAM_ERR(CAM_CRM, "Failed to notify crm event id %d", + old->id); + } +} + +static struct v4l2_subscribed_event_ops g_cam_v4l2_ops = { + .merge = cam_v4l2_event_queue_notify_error, +}; + +static int cam_subscribe_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + return v4l2_event_subscribe(fh, sub, CAM_REQ_MGR_EVENT_MAX, + &g_cam_v4l2_ops); +} + +static int cam_unsubscribe_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + return v4l2_event_unsubscribe(fh, sub); +} + +static long cam_private_ioctl(struct file *file, void *fh, + bool valid_prio, unsigned int cmd, void *arg) +{ + int rc; + struct cam_control *k_ioctl; + + if ((!arg) || (cmd != VIDIOC_CAM_CONTROL)) + return -EINVAL; + + k_ioctl = (struct cam_control *)arg; + + if (!k_ioctl->handle) + return -EINVAL; + + switch (k_ioctl->op_code) { + case CAM_REQ_MGR_CREATE_SESSION: { + struct cam_req_mgr_session_info ses_info; + + if (k_ioctl->size != sizeof(ses_info)) + return -EINVAL; + + if (copy_from_user(&ses_info, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_req_mgr_session_info))) { + return -EFAULT; + } + + rc = cam_req_mgr_create_session(&ses_info); + if (!rc) + if (copy_to_user( + u64_to_user_ptr(k_ioctl->handle), + &ses_info, + sizeof(struct cam_req_mgr_session_info))) + rc = -EFAULT; + } + break; + + case CAM_REQ_MGR_DESTROY_SESSION: { + struct cam_req_mgr_session_info ses_info; + + if (k_ioctl->size != sizeof(ses_info)) + return -EINVAL; + + if (copy_from_user(&ses_info, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_req_mgr_session_info))) { + return -EFAULT; + } + + rc = cam_req_mgr_destroy_session(&ses_info, false); + } + break; + + case CAM_REQ_MGR_LINK: { + struct cam_req_mgr_ver_info ver_info; + + if (k_ioctl->size != sizeof(ver_info.u.link_info_v1)) + return -EINVAL; + + if (copy_from_user(&ver_info.u.link_info_v1, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_req_mgr_link_info))) { + return -EFAULT; + } + ver_info.version = VERSION_1; + rc = cam_req_mgr_link(&ver_info); + if (!rc) + if (copy_to_user( + u64_to_user_ptr(k_ioctl->handle), + &ver_info.u.link_info_v1, + sizeof(struct cam_req_mgr_link_info))) + rc = -EFAULT; + } + break; + + case CAM_REQ_MGR_LINK_V2: { + struct cam_req_mgr_ver_info ver_info; + + if (k_ioctl->size != sizeof(ver_info.u.link_info_v2)) + return -EINVAL; + + if (copy_from_user(&ver_info.u.link_info_v2, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_req_mgr_link_info_v2))) { + return -EFAULT; + } + + ver_info.version = VERSION_2; + rc = cam_req_mgr_link_v2(&ver_info); + if (!rc) + if (copy_to_user( + u64_to_user_ptr(k_ioctl->handle), + &ver_info.u.link_info_v2, + sizeof(struct cam_req_mgr_link_info_v2))) + rc = -EFAULT; + } + break; + + case CAM_REQ_MGR_UNLINK: { + struct cam_req_mgr_unlink_info unlink_info; + + if (k_ioctl->size != sizeof(unlink_info)) + return -EINVAL; + + if (copy_from_user(&unlink_info, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_req_mgr_unlink_info))) { + return -EFAULT; + } + + rc = cam_req_mgr_unlink(&unlink_info); + } + break; + + case CAM_REQ_MGR_SCHED_REQ: { + struct cam_req_mgr_sched_request sched_req; + + if (k_ioctl->size != sizeof(sched_req)) + return -EINVAL; + + if (copy_from_user(&sched_req, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_req_mgr_sched_request))) { + return -EFAULT; + } + + rc = cam_req_mgr_schedule_request(&sched_req); + } + break; + + case CAM_REQ_MGR_FLUSH_REQ: { + struct cam_req_mgr_flush_info flush_info; + + if (k_ioctl->size != sizeof(flush_info)) + return -EINVAL; + + if (copy_from_user(&flush_info, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_req_mgr_flush_info))) { + return -EFAULT; + } + + rc = cam_req_mgr_flush_requests(&flush_info); + } + break; + + case CAM_REQ_MGR_SYNC_MODE: { + struct cam_req_mgr_sync_mode sync_info; + + if (k_ioctl->size != sizeof(sync_info)) + return -EINVAL; + + if (copy_from_user(&sync_info, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_req_mgr_sync_mode))) { + return -EFAULT; + } + + rc = cam_req_mgr_sync_config(&sync_info); + } + break; + case CAM_REQ_MGR_ALLOC_BUF: { + struct cam_mem_mgr_alloc_cmd cmd; + + if (k_ioctl->size != sizeof(cmd)) + return -EINVAL; + + if (copy_from_user(&cmd, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_mem_mgr_alloc_cmd))) { + rc = -EFAULT; + break; + } + + rc = cam_mem_mgr_alloc_and_map(&cmd); + if (!rc) + if (copy_to_user( + u64_to_user_ptr(k_ioctl->handle), + &cmd, sizeof(struct cam_mem_mgr_alloc_cmd))) { + rc = -EFAULT; + break; + } + } + break; + case CAM_REQ_MGR_MAP_BUF: { + struct cam_mem_mgr_map_cmd cmd; + + if (k_ioctl->size != sizeof(cmd)) + return -EINVAL; + + if (copy_from_user(&cmd, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_mem_mgr_map_cmd))) { + rc = -EFAULT; + break; + } + + rc = cam_mem_mgr_map(&cmd); + if (!rc) + if (copy_to_user( + u64_to_user_ptr(k_ioctl->handle), + &cmd, sizeof(struct cam_mem_mgr_map_cmd))) { + rc = -EFAULT; + break; + } + } + break; + case CAM_REQ_MGR_RELEASE_BUF: { + struct cam_mem_mgr_release_cmd cmd; + + if (k_ioctl->size != sizeof(cmd)) + return -EINVAL; + + if (copy_from_user(&cmd, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_mem_mgr_release_cmd))) { + rc = -EFAULT; + break; + } + + rc = cam_mem_mgr_release(&cmd); + } + break; + case CAM_REQ_MGR_CACHE_OPS: { + struct cam_mem_cache_ops_cmd cmd; + + if (k_ioctl->size != sizeof(cmd)) + return -EINVAL; + + if (copy_from_user(&cmd, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_mem_cache_ops_cmd))) { + rc = -EFAULT; + break; + } + + rc = cam_mem_mgr_cache_ops(&cmd); + if (rc) + rc = -EINVAL; + } + break; + case CAM_REQ_MGR_LINK_CONTROL: { + struct cam_req_mgr_link_control cmd; + + if (k_ioctl->size != sizeof(cmd)) + return -EINVAL; + + if (copy_from_user(&cmd, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_req_mgr_link_control))) { + rc = -EFAULT; + break; + } + + rc = cam_req_mgr_link_control(&cmd); + if (rc) + rc = -EINVAL; + } + break; + case CAM_REQ_MGR_REQUEST_DUMP: { + struct cam_dump_req_cmd cmd; + + if (k_ioctl->size != sizeof(cmd)) + return -EINVAL; + + if (copy_from_user(&cmd, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_dump_req_cmd))) { + rc = -EFAULT; + break; + } + rc = cam_req_mgr_dump_request(&cmd); + if (rc) { + CAM_ERR(CAM_CORE, "dump fail for dev %d req %llu rc %d", + cmd.dev_handle, cmd.issue_req_id, rc); + break; + } + if (copy_to_user( + u64_to_user_ptr(k_ioctl->handle), + &cmd, sizeof(struct cam_dump_req_cmd))) + rc = -EFAULT; + } + break; + default: + return -ENOIOCTLCMD; + } + + return rc; +} + +static const struct v4l2_ioctl_ops g_cam_ioctl_ops = { + .vidioc_subscribe_event = cam_subscribe_event, + .vidioc_unsubscribe_event = cam_unsubscribe_event, + .vidioc_default = cam_private_ioctl, +}; + +static int cam_video_device_setup(void) +{ + int rc; + + g_dev.video = video_device_alloc(); + if (!g_dev.video) { + rc = -ENOMEM; + goto video_fail; + } + + g_dev.video->v4l2_dev = g_dev.v4l2_dev; + + strlcpy(g_dev.video->name, "cam-req-mgr", + sizeof(g_dev.video->name)); + g_dev.video->release = video_device_release; + g_dev.video->fops = &g_cam_fops; + g_dev.video->ioctl_ops = &g_cam_ioctl_ops; + g_dev.video->minor = -1; + g_dev.video->vfl_type = VFL_TYPE_GRABBER; + rc = video_register_device(g_dev.video, VFL_TYPE_GRABBER, -1); + if (rc) + goto v4l2_fail; + + rc = media_entity_pads_init(&g_dev.video->entity, 0, NULL); + if (rc) + goto entity_fail; + + g_dev.video->entity.function = CAM_VNODE_DEVICE_TYPE; + g_dev.video->entity.name = video_device_node_name(g_dev.video); + + return rc; + +entity_fail: + video_unregister_device(g_dev.video); +v4l2_fail: + video_device_release(g_dev.video); + g_dev.video = NULL; +video_fail: + return rc; +} + +int cam_req_mgr_notify_message(struct cam_req_mgr_message *msg, + uint32_t id, + uint32_t type) +{ + struct v4l2_event event; + struct cam_req_mgr_message *ev_header; + + if (!msg) + return -EINVAL; + + event.id = id; + event.type = type; + ev_header = CAM_REQ_MGR_GET_PAYLOAD_PTR(event, + struct cam_req_mgr_message); + memcpy(ev_header, msg, sizeof(struct cam_req_mgr_message)); + v4l2_event_queue(g_dev.video, &event); + + return 0; +} +EXPORT_SYMBOL(cam_req_mgr_notify_message); + +void cam_video_device_cleanup(void) +{ + video_unregister_device(g_dev.video); + video_device_release(g_dev.video); + g_dev.video = NULL; +} + +void cam_register_subdev_fops(struct v4l2_file_operations *fops) +{ + *fops = v4l2_subdev_fops; +} +EXPORT_SYMBOL(cam_register_subdev_fops); + +void cam_subdev_notify_message(u32 subdev_type, + enum cam_subdev_message_type_t message_type, + uint32_t data) +{ + struct v4l2_subdev *sd = NULL; + struct cam_subdev *csd = NULL; + + list_for_each_entry(sd, &g_dev.v4l2_dev->subdevs, list) { + if (sd->entity.function == subdev_type) { + csd = container_of(sd, struct cam_subdev, sd); + if (csd->msg_cb != NULL) + csd->msg_cb(sd, message_type, data); + } + } +} +EXPORT_SYMBOL(cam_subdev_notify_message); + +bool cam_req_mgr_is_open(void) +{ + bool crm_status = false; + + mutex_lock(&g_dev.cam_lock); + crm_status = g_dev.open_cnt ? true : false; + mutex_unlock(&g_dev.cam_lock); + + return crm_status; +} +EXPORT_SYMBOL(cam_req_mgr_is_open); + +bool cam_req_mgr_is_shutdown(void) +{ + return g_dev.shutdown_state; +} +EXPORT_SYMBOL(cam_req_mgr_is_shutdown); + +int cam_register_subdev(struct cam_subdev *csd) +{ + struct v4l2_subdev *sd; + int rc; + + if (g_dev.state != true) { + CAM_ERR(CAM_CRM, "camera root device not ready yet"); + return -ENODEV; + } + + if (!csd || !csd->name) { + CAM_ERR(CAM_CRM, "invalid arguments"); + return -EINVAL; + } + + mutex_lock(&g_dev.dev_lock); + if ((g_dev.subdev_nodes_created) && + (csd->sd_flags & V4L2_SUBDEV_FL_HAS_DEVNODE)) { + CAM_ERR(CAM_CRM, + "dynamic node is not allowed, name: %s, type :%d", + csd->name, csd->ent_function); + rc = -EINVAL; + goto reg_fail; + } + + sd = &csd->sd; + v4l2_subdev_init(sd, csd->ops); + sd->internal_ops = csd->internal_ops; + snprintf(sd->name, V4L2_SUBDEV_NAME_SIZE, "%s", csd->name); + v4l2_set_subdevdata(sd, csd->token); + + sd->flags = csd->sd_flags; + sd->entity.num_pads = 0; + sd->entity.pads = NULL; + sd->entity.function = csd->ent_function; + + rc = v4l2_device_register_subdev(g_dev.v4l2_dev, sd); + if (rc) { + CAM_ERR(CAM_CRM, "register subdev failed"); + goto reg_fail; + } + g_dev.count++; + +reg_fail: + mutex_unlock(&g_dev.dev_lock); + return rc; +} +EXPORT_SYMBOL(cam_register_subdev); + +int cam_unregister_subdev(struct cam_subdev *csd) +{ + if (g_dev.state != true) { + CAM_ERR(CAM_CRM, "camera root device not ready yet"); + return -ENODEV; + } + + mutex_lock(&g_dev.dev_lock); + v4l2_device_unregister_subdev(&csd->sd); + g_dev.count--; + mutex_unlock(&g_dev.dev_lock); + + return 0; +} +EXPORT_SYMBOL(cam_unregister_subdev); + +static int cam_req_mgr_remove(struct platform_device *pdev) +{ + cam_req_mgr_core_device_deinit(); + cam_req_mgr_util_deinit(); + cam_media_device_cleanup(); + cam_video_device_cleanup(); + cam_v4l2_device_cleanup(); + mutex_destroy(&g_dev.dev_lock); + g_dev.state = false; + g_dev.subdev_nodes_created = false; + + return 0; +} + +static int cam_req_mgr_probe(struct platform_device *pdev) +{ + int rc; + + rc = cam_v4l2_device_setup(&pdev->dev); + if (rc) + return rc; + + rc = cam_media_device_setup(&pdev->dev); + if (rc) + goto media_setup_fail; + + rc = cam_video_device_setup(); + if (rc) + goto video_setup_fail; + + g_dev.open_cnt = 0; + mutex_init(&g_dev.cam_lock); + spin_lock_init(&g_dev.cam_eventq_lock); + g_dev.subdev_nodes_created = false; + mutex_init(&g_dev.dev_lock); + + rc = cam_req_mgr_util_init(); + if (rc) { + CAM_ERR(CAM_CRM, "cam req mgr util init is failed"); + goto req_mgr_util_fail; + } + + rc = cam_req_mgr_core_device_init(); + if (rc) { + CAM_ERR(CAM_CRM, "core device setup failed"); + goto req_mgr_core_fail; + } + + g_dev.state = true; + + if (g_cam_req_mgr_timer_cachep == NULL) { + g_cam_req_mgr_timer_cachep = kmem_cache_create("crm_timer", + sizeof(struct cam_req_mgr_timer), 64, + SLAB_CONSISTENCY_CHECKS | SLAB_RED_ZONE | + SLAB_POISON | SLAB_STORE_USER, NULL); + if (!g_cam_req_mgr_timer_cachep) + CAM_ERR(CAM_CRM, + "Failed to create kmem_cache for crm_timer"); + else + CAM_DBG(CAM_CRM, "Name : %s", + g_cam_req_mgr_timer_cachep->name); + } + + return rc; + +req_mgr_core_fail: + cam_req_mgr_util_deinit(); +req_mgr_util_fail: + mutex_destroy(&g_dev.dev_lock); + mutex_destroy(&g_dev.cam_lock); + cam_video_device_cleanup(); +video_setup_fail: + cam_media_device_cleanup(); +media_setup_fail: + cam_v4l2_device_cleanup(); + return rc; +} + +static const struct of_device_id cam_req_mgr_dt_match[] = { + {.compatible = "qcom,cam-req-mgr"}, + {} +}; +MODULE_DEVICE_TABLE(of, cam_dt_match); + +static struct platform_driver cam_req_mgr_driver = { + .probe = cam_req_mgr_probe, + .remove = cam_req_mgr_remove, + .driver = { + .name = "cam_req_mgr", + .owner = THIS_MODULE, + .of_match_table = cam_req_mgr_dt_match, + .suppress_bind_attrs = true, + }, +}; + +int cam_dev_mgr_create_subdev_nodes(void) +{ + int rc; + struct v4l2_subdev *sd; + + if (!g_dev.v4l2_dev) + return -EINVAL; + + if (g_dev.state != true) { + CAM_ERR(CAM_CRM, "camera root device not ready yet"); + return -ENODEV; + } + + mutex_lock(&g_dev.dev_lock); + if (g_dev.subdev_nodes_created) { + rc = -EEXIST; + goto create_fail; + } + + rc = v4l2_device_register_subdev_nodes(g_dev.v4l2_dev); + if (rc) { + CAM_ERR(CAM_CRM, "failed to register the sub devices"); + goto create_fail; + } + + list_for_each_entry(sd, &g_dev.v4l2_dev->subdevs, list) { + if (!(sd->flags & V4L2_SUBDEV_FL_HAS_DEVNODE)) + continue; + sd->entity.name = video_device_node_name(sd->devnode); + CAM_DBG(CAM_CRM, "created node :%s", sd->entity.name); + } + + g_dev.subdev_nodes_created = true; + +create_fail: + mutex_unlock(&g_dev.dev_lock); + return rc; +} + +static int __init cam_req_mgr_init(void) +{ + return platform_driver_register(&cam_req_mgr_driver); +} + +static int __init cam_req_mgr_late_init(void) +{ + return cam_dev_mgr_create_subdev_nodes(); +} + +static void __exit cam_req_mgr_exit(void) +{ + platform_driver_unregister(&cam_req_mgr_driver); +} + +module_init(cam_req_mgr_init); +late_initcall(cam_req_mgr_late_init); +module_exit(cam_req_mgr_exit); +MODULE_DESCRIPTION("Camera Request Manager"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_dev.h b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..ccf4854a03d20d4205b0b95d2d2bcf8915e4baac --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_dev.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_REQ_MGR_DEV_H_ +#define _CAM_REQ_MGR_DEV_H_ + +/** + * struct cam_req_mgr_device - a camera request manager device + * + * @video: pointer to struct video device. + * @v4l2_dev: pointer to struct v4l2 device. + * @subdev_nodes_created: flag to check the created state. + * @count: number of subdevices registered. + * @dev_lock: lock for the subdevice count. + * @state: state of the root device. + * @open_cnt: open count of subdev + * @cam_lock: per file handle lock + * @cam_eventq: event queue + * @cam_eventq_lock: lock for event queue + * @shutdown_state: shutdown state + */ +struct cam_req_mgr_device { + struct video_device *video; + struct v4l2_device *v4l2_dev; + bool subdev_nodes_created; + int count; + struct mutex dev_lock; + bool state; + int32_t open_cnt; + struct mutex cam_lock; + struct v4l2_fh *cam_eventq; + spinlock_t cam_eventq_lock; + bool shutdown_state; +}; + +#define CAM_REQ_MGR_GET_PAYLOAD_PTR(ev, type) \ + (type *)((char *)ev.u.data) + +int cam_req_mgr_notify_message(struct cam_req_mgr_message *msg, + uint32_t id, + uint32_t type); + +#endif /* _CAM_REQ_MGR_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_interface.h b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_interface.h new file mode 100644 index 0000000000000000000000000000000000000000..7c184d675c6f11fe8c169fda2286288c677a40c3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_interface.h @@ -0,0 +1,399 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_REQ_MGR_INTERFACE_H +#define _CAM_REQ_MGR_INTERFACE_H + +#include +#include +#include "cam_req_mgr_core_defs.h" +#include "cam_req_mgr_util.h" + +struct cam_req_mgr_trigger_notify; +struct cam_req_mgr_error_notify; +struct cam_req_mgr_add_request; +struct cam_req_mgr_timer_notify; +struct cam_req_mgr_notify_stop; +struct cam_req_mgr_device_info; +struct cam_req_mgr_core_dev_link_setup; +struct cam_req_mgr_apply_request; +struct cam_req_mgr_flush_request; +struct cam_req_mgr_link_evt_data; +struct cam_req_mgr_dump_info; + +#define SKIP_NEXT_FRAME 0x100 + +/* Request Manager -- camera device driver interface */ +/** + * @brief: camera kernel drivers to cam req mgr communication + * + * @cam_req_mgr_notify_trigger: for device which generates trigger to inform CRM + * @cam_req_mgr_notify_err : device use this to inform about different errors + * @cam_req_mgr_add_req : to info CRm about new rqeuest received from + * userspace + */ +typedef int (*cam_req_mgr_notify_trigger)( + struct cam_req_mgr_trigger_notify *); +typedef int (*cam_req_mgr_notify_err)(struct cam_req_mgr_error_notify *); +typedef int (*cam_req_mgr_add_req)(struct cam_req_mgr_add_request *); +typedef int (*cam_req_mgr_notify_timer)(struct cam_req_mgr_timer_notify *); +typedef int (*cam_req_mgr_notify_stop)(struct cam_req_mgr_notify_stop *); + +/** + * @brief: cam req mgr to camera device drivers + * + * @cam_req_mgr_get_dev_info: to fetch details about device linked + * @cam_req_mgr_link_setup : to establish link with device for a session + * @cam_req_mgr_notify_err : to broadcast error happened on link for request id + * @cam_req_mgr_apply_req : CRM asks device to apply certain request id. + * @cam_req_mgr_flush_req : Flush or cancel request + * cam_req_mgr_process_evt : generic events + * @cam_req_mgr_dump_req : dump request + */ +typedef int (*cam_req_mgr_get_dev_info) (struct cam_req_mgr_device_info *); +typedef int (*cam_req_mgr_link_setup)( + struct cam_req_mgr_core_dev_link_setup *); +typedef int (*cam_req_mgr_apply_req)(struct cam_req_mgr_apply_request *); +typedef int (*cam_req_mgr_flush_req)(struct cam_req_mgr_flush_request *); +typedef int (*cam_req_mgr_process_evt)(struct cam_req_mgr_link_evt_data *); +typedef int (*cam_req_mgr_dump_req)(struct cam_req_mgr_dump_info *); + +/** + * @brief : cam_req_mgr_crm_cb - func table + * + * @notify_trigger : payload for trigger indication event + * @notify_err : payload for different error occurred at device + * @add_req : payload to inform which device and what request is received + * @notify_stop : payload to inform stop event + */ +struct cam_req_mgr_crm_cb { + cam_req_mgr_notify_trigger notify_trigger; + cam_req_mgr_notify_err notify_err; + cam_req_mgr_add_req add_req; + cam_req_mgr_notify_timer notify_timer; + cam_req_mgr_notify_stop notify_stop; +}; + +/** + * @brief : cam_req_mgr_kmd_ops - func table + * + * @get_dev_info : payload to fetch device details + * @link_setup : payload to establish link with device + * @apply_req : payload to apply request id on a device linked + * @flush_req : payload to flush request + * @process_evt : payload to generic event + * @dump_req : payload to dump request + */ +struct cam_req_mgr_kmd_ops { + cam_req_mgr_get_dev_info get_dev_info; + cam_req_mgr_link_setup link_setup; + cam_req_mgr_apply_req apply_req; + cam_req_mgr_flush_req flush_req; + cam_req_mgr_process_evt process_evt; + cam_req_mgr_dump_req dump_req; +}; + +/** + * enum cam_pipeline_delay + * @brief : enumerator for different pipeline delays in camera + * + * @DELAY_0 : device processed settings on same frame + * @DELAY_1 : device processed settings after 1 frame + * @DELAY_2 : device processed settings after 2 frames + * @DELAY_MAX : maximum supported pipeline delay + */ +enum cam_pipeline_delay { + CAM_PIPELINE_DELAY_0, + CAM_PIPELINE_DELAY_1, + CAM_PIPELINE_DELAY_2, + CAM_PIPELINE_DELAY_MAX, +}; + +/** + * @CAM_TRIGGER_POINT_SOF : Trigger point for SOF + * @CAM_TRIGGER_POINT_EOF : Trigger point for EOF + */ +#define CAM_TRIGGER_POINT_SOF (1 << 0) +#define CAM_TRIGGER_POINT_EOF (1 << 1) + +/** + * enum cam_req_status + * @brief : enumerator for request status + * + * @SUCCESS : device processed settings successfully + * @FAILED : device processed settings failed + * @MAX : invalid status value + */ +enum cam_req_status { + CAM_REQ_STATUS_SUCCESS, + CAM_REQ_STATUS_FAILED, + CAM_REQ_STATUS_MAX, +}; + +/** + * enum cam_req_mgr_device_error + * @brief : enumerator for different errors occurred at device + * + * @NOT_FOUND : settings asked by request manager is not found + * @BUBBLE : device hit timing issue and is able to recover + * @FATAL : device is in bad shape and can not recover from error + * @PAGE_FAULT : Page fault while accessing memory + * @OVERFLOW : Bus Overflow for IFE/VFE + * @TIMEOUT : Timeout from cci or bus. + * @MAX : Invalid error value + */ +enum cam_req_mgr_device_error { + CRM_KMD_ERR_NOT_FOUND, + CRM_KMD_ERR_BUBBLE, + CRM_KMD_ERR_FATAL, + CRM_KMD_ERR_PAGE_FAULT, + CRM_KMD_ERR_OVERFLOW, + CRM_KMD_ERR_TIMEOUT, + CRM_KMD_ERR_STOPPED, + CRM_KMD_ERR_MAX, +}; + +/** + * enum cam_req_mgr_device_id + * @brief : enumerator for different devices in subsystem + * + * @CAM_REQ_MGR : request manager itself + * @SENSOR : sensor device + * @FLASH : LED flash or dual LED device + * @ACTUATOR : lens mover + * @IFE : Image processing device + * @CUSTOM : Custom HW block + * @EXTERNAL_1 : third party device + * @EXTERNAL_2 : third party device + * @EXTERNAL_3 : third party device + * @MAX : invalid device id + */ +enum cam_req_mgr_device_id { + CAM_REQ_MGR_DEVICE, + CAM_REQ_MGR_DEVICE_SENSOR, + CAM_REQ_MGR_DEVICE_FLASH, + CAM_REQ_MGR_DEVICE_ACTUATOR, + CAM_REQ_MGR_DEVICE_IFE, + CAM_REQ_MGR_DEVICE_CUSTOM_HW, + CAM_REQ_MGR_DEVICE_EXTERNAL_1, + CAM_REQ_MGR_DEVICE_EXTERNAL_2, + CAM_REQ_MGR_DEVICE_EXTERNAL_3, + CAM_REQ_MGR_DEVICE_ID_MAX, +}; + +/* Camera device driver to Req Mgr device interface */ + +/** + * enum cam_req_mgr_link_evt_type + * @CAM_REQ_MGR_LINK_EVT_ERR : error on the link from any of the + * connected devices + * @CAM_REQ_MGR_LINK_EVT_PAUSE : to pause the link + * @CAM_REQ_MGR_LINK_EVT_RESUME : resumes the link which was paused + * @CAM_REQ_MGR_LINK_EVT_SOF_FREEZE : request manager has detected an sof freeze + * @CAM_REQ_MGR_LINK_EVT_MAX : invalid event type + */ +enum cam_req_mgr_link_evt_type { + CAM_REQ_MGR_LINK_EVT_ERR, + CAM_REQ_MGR_LINK_EVT_PAUSE, + CAM_REQ_MGR_LINK_EVT_RESUME, + CAM_REQ_MGR_LINK_EVT_SOF_FREEZE, + CAM_REQ_MGR_LINK_EVT_MAX, +}; + +/** + * struct cam_req_mgr_trigger_notify + * @link_hdl : link identifier + * @dev_hdl : device handle which has sent this req id + * @frame_id : frame id for internal tracking + * @trigger : trigger point of this notification, CRM will send apply + * only to the devices which subscribe to this point. + * @sof_timestamp_val: Captured time stamp value at sof hw event + * @req_id : req id which returned buf_done + */ +struct cam_req_mgr_trigger_notify { + int32_t link_hdl; + int32_t dev_hdl; + int64_t frame_id; + uint32_t trigger; + uint64_t sof_timestamp_val; + uint64_t req_id; +}; + +/** + * struct cam_req_mgr_timer_notify + * @link_hdl : link identifier + * @dev_hdl : device handle which has sent this req id + * @frame_id : frame id for internal tracking + * @state : timer state i.e ON or OFF + */ +struct cam_req_mgr_timer_notify { + int32_t link_hdl; + int32_t dev_hdl; + bool state; +}; + +/** + * struct cam_req_mgr_error_notify + * @link_hdl : link identifier + * @dev_hdl : device handle which has sent this req id + * @req_id : req id which hit error + * @frame_id : frame id for internal tracking + * @trigger : trigger point of this notification, CRM will send apply + * @sof_timestamp_val : Captured time stamp value at sof hw event + * @error : what error device hit while processing this req + */ +struct cam_req_mgr_error_notify { + int32_t link_hdl; + int32_t dev_hdl; + uint64_t req_id; + int64_t frame_id; + uint32_t trigger; + uint64_t sof_timestamp_val; + enum cam_req_mgr_device_error error; +}; + +/** + * struct cam_req_mgr_add_request + * @link_hdl : link identifier + * @dev_hdl : device handle which has sent this req id + * @req_id : req id which device is ready to process + * @skip_before_applying : before applying req mgr introduce bubble + * by not sending request to device/s. + * ex: IFE and Flash + */ +struct cam_req_mgr_add_request { + int32_t link_hdl; + int32_t dev_hdl; + uint64_t req_id; + uint32_t skip_before_applying; +}; + + +/** + * struct cam_req_mgr_notify_stop + * @link_hdl : link identifier + * + */ +struct cam_req_mgr_notify_stop { + int32_t link_hdl; +}; + + +/* CRM to KMD devices */ +/** + * struct cam_req_mgr_device_info + * @dev_hdl : Input_param : device handle for reference + * @name : link link or unlink + * @dev_id : device id info + * @p_delay : delay between time settings applied and take effect + * @trigger : Trigger point for the client + * + */ +struct cam_req_mgr_device_info { + int32_t dev_hdl; + char name[256]; + enum cam_req_mgr_device_id dev_id; + enum cam_pipeline_delay p_delay; + uint32_t trigger; +}; + +/** + * struct cam_req_mgr_core_dev_link_setup + * @link_enable : link link or unlink + * @link_hdl : link identifier + * @dev_hdl : device handle for reference + * @max_delay : max pipeline delay on this link + * @crm_cb : callback funcs to communicate with req mgr + * @subscribe_event : the mask of trigger points this link subscribes + * + */ +struct cam_req_mgr_core_dev_link_setup { + int32_t link_enable; + int32_t link_hdl; + int32_t dev_hdl; + enum cam_pipeline_delay max_delay; + struct cam_req_mgr_crm_cb *crm_cb; + uint32_t subscribe_event; +}; + +/** + * struct cam_req_mgr_apply_request + * @link_hdl : link identifier + * @dev_hdl : device handle for cross check + * @request_id : request id settings to apply + * @report_if_bubble : report to crm if failure in applying + * @trigger_point : the trigger point of this apply + * + */ +struct cam_req_mgr_apply_request { + int32_t link_hdl; + int32_t dev_hdl; + uint64_t request_id; + int32_t report_if_bubble; + uint32_t trigger_point; +}; + +/** + * struct cam_req_mgr_flush_request + * @link_hdl : link identifier + * @dev_hdl : device handle for cross check + * @type : cancel request type flush all or a request + * @request_id : request id to cancel + * + */ +struct cam_req_mgr_flush_request { + int32_t link_hdl; + int32_t dev_hdl; + uint32_t type; + uint64_t req_id; +}; + +/** + * struct cam_req_mgr_event_data + * @link_hdl : link handle + * @req_id : request id + * + */ +struct cam_req_mgr_link_evt_data { + int32_t link_hdl; + int32_t dev_hdl; + uint64_t req_id; + + enum cam_req_mgr_link_evt_type evt_type; + union { + enum cam_req_mgr_device_error error; + } u; +}; + +/** + * struct cam_req_mgr_send_request + * @link_hdl : link identifier + * @idx : slot idx + * + */ +struct cam_req_mgr_send_request { + int32_t link_hdl; + struct cam_req_mgr_req_queue *in_q; +}; + +/** + * struct cam_req_mgr_dump_info + * @req_id : request id to dump + * @offset : offset of buffer + * @error_type : error type + * @buf_handle : buf handle + * @link_hdl : link identifier + * @dev_hdl : device handle for cross check + * + */ +struct cam_req_mgr_dump_info { + uint64_t req_id; + size_t offset; + uint32_t error_type; + uint32_t buf_handle; + int32_t link_hdl; + int32_t dev_hdl; +}; +#endif diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_timer.c b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..eb2a6d599b0fbc42ae0b2197b1bf46aa1c1e08d0 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_timer.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_req_mgr_timer.h" +#include "cam_debug_util.h" + +extern struct kmem_cache *g_cam_req_mgr_timer_cachep; + +void crm_timer_reset(struct cam_req_mgr_timer *crm_timer) +{ + if (!crm_timer) + return; + CAM_DBG(CAM_CRM, "Starting timer to fire in %d ms. (jiffies=%lu)\n", + crm_timer->expires, jiffies); + mod_timer(&crm_timer->sys_timer, + (jiffies + msecs_to_jiffies(crm_timer->expires))); +} + +void crm_timer_callback(struct timer_list *timer_data) +{ + struct cam_req_mgr_timer *timer = + container_of(timer_data, struct cam_req_mgr_timer, sys_timer); + if (!timer) { + CAM_ERR(CAM_CRM, "NULL timer"); + return; + } + CAM_DBG(CAM_CRM, "timer %pK parent %pK", timer, timer->parent); + crm_timer_reset(timer); +} + +void crm_timer_modify(struct cam_req_mgr_timer *crm_timer, + int32_t expires) +{ + CAM_DBG(CAM_CRM, "new time %d", expires); + if (crm_timer) { + crm_timer->expires = expires; + crm_timer_reset(crm_timer); + } +} + +int crm_timer_init(struct cam_req_mgr_timer **timer, + int32_t expires, void *parent, void (*timer_cb)(struct timer_list *)) +{ + int ret = 0; + struct cam_req_mgr_timer *crm_timer = NULL; + + CAM_DBG(CAM_CRM, "init timer %d %pK", expires, *timer); + if (*timer == NULL) { + if (g_cam_req_mgr_timer_cachep) { + crm_timer = kmem_cache_alloc(g_cam_req_mgr_timer_cachep, + __GFP_ZERO | GFP_KERNEL); + if (!crm_timer) { + ret = -ENOMEM; + goto end; + } + } + + else { + ret = -ENOMEM; + goto end; + } + + if (timer_cb != NULL) + crm_timer->timer_cb = timer_cb; + else + crm_timer->timer_cb = crm_timer_callback; + + crm_timer->expires = expires; + crm_timer->parent = parent; + timer_setup(&crm_timer->sys_timer, + crm_timer->timer_cb, 0); + crm_timer_reset(crm_timer); + *timer = crm_timer; + } else { + CAM_WARN(CAM_CRM, "Timer already exists!!"); + ret = -EINVAL; + } +end: + return ret; +} +void crm_timer_exit(struct cam_req_mgr_timer **crm_timer) +{ + CAM_DBG(CAM_CRM, "destroy timer %pK @ %pK", *crm_timer, crm_timer); + if (*crm_timer) { + del_timer_sync(&(*crm_timer)->sys_timer); + if (g_cam_req_mgr_timer_cachep) + kmem_cache_free(g_cam_req_mgr_timer_cachep, *crm_timer); + *crm_timer = NULL; + } +} diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_timer.h b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..d2e20498df9a6ce50fc2ba764bd7af05fa762407 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_timer.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_REQ_MGR_TIMER_H_ +#define _CAM_REQ_MGR_TIMER_H_ + +#include +#include + +#include "cam_req_mgr_core_defs.h" + +/** struct cam_req_mgr_timer + * @expires : timeout value for timer + * @sys_timer : system timer variable + * @parent : priv data - link pointer + * @timer_cb : callback func which will be called when timeout expires + * @pause_timer : flag to pause SOF timer + */ +struct cam_req_mgr_timer { + int32_t expires; + struct timer_list sys_timer; + void *parent; + void (*timer_cb)(struct timer_list *timer_data); + bool pause_timer; +}; + +/** + * crm_timer_modify() + * @brief : allows ser to modify expiry time. + * @timer : timer which will be reset to expires values + */ +void crm_timer_modify(struct cam_req_mgr_timer *crm_timer, + int32_t expires); + +/** + * crm_timer_reset() + * @brief : destroys the timer allocated. + * @timer : timer which will be reset to expires values + */ +void crm_timer_reset(struct cam_req_mgr_timer *timer); + +/** + * crm_timer_init() + * @brief : create a new general purpose timer. + * timer utility takes care of allocating memory and deleting + * @timer : double pointer to new timer allocated + * @expires : Timeout value to fire callback + * @parent : void pointer which caller can use for book keeping + * @timer_cb : caller can chose to use its own callback function when + * timer fires the timeout. If no value is set timer util + * will use default. + */ +int crm_timer_init(struct cam_req_mgr_timer **timer, + int32_t expires, void *parent, void (*timer_cb)(struct timer_list *)); + +/** + * crm_timer_exit() + * @brief : destroys the timer allocated. + * @timer : timer pointer which will be freed + */ +void crm_timer_exit(struct cam_req_mgr_timer **timer); + +#endif diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_util.c b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_util.c new file mode 100644 index 0000000000000000000000000000000000000000..a3eb168a68029076883a89ebfda3576f0c1e432b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_util.c @@ -0,0 +1,432 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define pr_fmt(fmt) "CAM-REQ-MGR_UTIL %s:%d " fmt, __func__, __LINE__ + +#include +#include +#include +#include +#include +#include +#include +#include "cam_req_mgr_util.h" +#include "cam_debug_util.h" +#include "cam_subdev.h" + +static struct cam_req_mgr_util_hdl_tbl *hdl_tbl; +static DEFINE_SPINLOCK(hdl_tbl_lock); + +int cam_req_mgr_util_init(void) +{ + int rc = 0; + int bitmap_size; + static struct cam_req_mgr_util_hdl_tbl *hdl_tbl_local; + + if (hdl_tbl) { + rc = -EINVAL; + CAM_ERR(CAM_CRM, "Hdl_tbl is already present"); + goto hdl_tbl_check_failed; + } + + hdl_tbl_local = kzalloc(sizeof(*hdl_tbl), GFP_KERNEL); + if (!hdl_tbl_local) { + rc = -ENOMEM; + goto hdl_tbl_alloc_failed; + } + bitmap_size = BITS_TO_LONGS(CAM_REQ_MGR_MAX_HANDLES_V2) * sizeof(long); + hdl_tbl_local->bitmap = kzalloc(bitmap_size, GFP_KERNEL); + if (!hdl_tbl_local->bitmap) { + rc = -ENOMEM; + goto bitmap_alloc_fail; + } + hdl_tbl_local->bits = bitmap_size * BITS_PER_BYTE; + + spin_lock_bh(&hdl_tbl_lock); + if (hdl_tbl) { + spin_unlock_bh(&hdl_tbl_lock); + rc = -EEXIST; + kfree(hdl_tbl_local->bitmap); + kfree(hdl_tbl_local); + goto hdl_tbl_check_failed; + } + hdl_tbl = hdl_tbl_local; + spin_unlock_bh(&hdl_tbl_lock); + + return rc; + +bitmap_alloc_fail: + kfree(hdl_tbl_local); + hdl_tbl = NULL; +hdl_tbl_alloc_failed: +hdl_tbl_check_failed: + return rc; +} + +int cam_req_mgr_util_deinit(void) +{ + spin_lock_bh(&hdl_tbl_lock); + if (!hdl_tbl) { + CAM_ERR(CAM_CRM, "Hdl tbl is NULL"); + spin_unlock_bh(&hdl_tbl_lock); + return -EINVAL; + } + + kfree(hdl_tbl->bitmap); + hdl_tbl->bitmap = NULL; + kfree(hdl_tbl); + hdl_tbl = NULL; + spin_unlock_bh(&hdl_tbl_lock); + + return 0; +} + +int cam_req_mgr_util_free_hdls(void) +{ + int i = 0; + + spin_lock_bh(&hdl_tbl_lock); + if (!hdl_tbl) { + CAM_ERR(CAM_CRM, "Hdl tbl is NULL"); + spin_unlock_bh(&hdl_tbl_lock); + return -EINVAL; + } + + for (i = 0; i < CAM_REQ_MGR_MAX_HANDLES_V2; i++) { + if (hdl_tbl->hdl[i].state == HDL_ACTIVE) { + CAM_WARN(CAM_CRM, "Dev handle = %x session_handle = %x", + hdl_tbl->hdl[i].hdl_value, + hdl_tbl->hdl[i].session_hdl); + hdl_tbl->hdl[i].state = HDL_FREE; + clear_bit(i, hdl_tbl->bitmap); + } + } + bitmap_zero(hdl_tbl->bitmap, CAM_REQ_MGR_MAX_HANDLES_V2); + spin_unlock_bh(&hdl_tbl_lock); + + return 0; +} + +static int32_t cam_get_free_handle_index(void) +{ + int idx; + + idx = find_first_zero_bit(hdl_tbl->bitmap, hdl_tbl->bits); + + if (idx >= CAM_REQ_MGR_MAX_HANDLES_V2 || idx < 0) { + CAM_ERR(CAM_CRM, "No free index found idx: %d", idx); + return -ENOSR; + } + + set_bit(idx, hdl_tbl->bitmap); + + return idx; +} + +static void cam_dump_tbl_info(void) +{ + int i; + + for (i = 0; i < CAM_REQ_MGR_MAX_HANDLES_V2; i++) + CAM_INFO_RATE_LIMIT_CUSTOM(CAM_CRM, CAM_RATE_LIMIT_INTERVAL_5SEC, + CAM_REQ_MGR_MAX_HANDLES_V2, + "session_hdl=%x hdl_value=%x type=%d state=%d dev_id=%lld", + hdl_tbl->hdl[i].session_hdl, hdl_tbl->hdl[i].hdl_value, + hdl_tbl->hdl[i].type, hdl_tbl->hdl[i].state, hdl_tbl->hdl[i].dev_id); +} + +int32_t cam_create_session_hdl(void *priv) +{ + int idx; + int rand = 0; + int32_t handle = 0; + + spin_lock_bh(&hdl_tbl_lock); + if (!hdl_tbl) { + CAM_ERR(CAM_CRM, "Hdl tbl is NULL"); + spin_unlock_bh(&hdl_tbl_lock); + return -EINVAL; + } + + idx = cam_get_free_handle_index(); + if (idx < 0) { + CAM_ERR(CAM_CRM, "Unable to create session handle(idx = %d)", idx); + cam_dump_tbl_info(); + spin_unlock_bh(&hdl_tbl_lock); + return idx; + } + + get_random_bytes(&rand, CAM_REQ_MGR_RND1_BYTES); + handle = GET_DEV_HANDLE(rand, HDL_TYPE_SESSION, idx); + hdl_tbl->hdl[idx].session_hdl = handle; + hdl_tbl->hdl[idx].hdl_value = handle; + hdl_tbl->hdl[idx].type = HDL_TYPE_SESSION; + hdl_tbl->hdl[idx].state = HDL_ACTIVE; + hdl_tbl->hdl[idx].priv = priv; + hdl_tbl->hdl[idx].ops = NULL; + hdl_tbl->hdl[idx].dev_id = CAM_CRM; + spin_unlock_bh(&hdl_tbl_lock); + + return handle; +} + +int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data) +{ + int idx; + int rand = 0; + int32_t handle; + bool crm_active; + + crm_active = cam_req_mgr_is_open(); + if (!crm_active) { + CAM_ERR(CAM_ICP, "CRM is not ACTIVE"); + spin_unlock_bh(&hdl_tbl_lock); + return -EINVAL; + } + + spin_lock_bh(&hdl_tbl_lock); + if (!hdl_tbl) { + CAM_ERR(CAM_CRM, "Hdl tbl is NULL"); + spin_unlock_bh(&hdl_tbl_lock); + return -EINVAL; + } + + idx = cam_get_free_handle_index(); + if (idx < 0) { + CAM_ERR(CAM_CRM, "Unable to create device handle(idx= %d)", idx); + cam_dump_tbl_info(); + spin_unlock_bh(&hdl_tbl_lock); + return idx; + } + + get_random_bytes(&rand, CAM_REQ_MGR_RND1_BYTES); + handle = GET_DEV_HANDLE(rand, HDL_TYPE_DEV, idx); + hdl_tbl->hdl[idx].session_hdl = hdl_data->session_hdl; + hdl_tbl->hdl[idx].hdl_value = handle; + hdl_tbl->hdl[idx].type = HDL_TYPE_DEV; + hdl_tbl->hdl[idx].state = HDL_ACTIVE; + hdl_tbl->hdl[idx].priv = hdl_data->priv; + hdl_tbl->hdl[idx].ops = hdl_data->ops; + hdl_tbl->hdl[idx].dev_id = hdl_data->dev_id; + spin_unlock_bh(&hdl_tbl_lock); + + pr_debug("%s: handle = 0x%x idx = %d\n", __func__, handle, idx); + return handle; +} + +int32_t cam_create_link_hdl(struct cam_create_dev_hdl *hdl_data) +{ + int idx; + int rand = 0; + int32_t handle; + + spin_lock_bh(&hdl_tbl_lock); + if (!hdl_tbl) { + CAM_ERR(CAM_CRM, "Hdl tbl is NULL"); + spin_unlock_bh(&hdl_tbl_lock); + return -EINVAL; + } + + idx = cam_get_free_handle_index(); + if (idx < 0) { + CAM_ERR(CAM_CRM, "Unable to create link handle(idx = %d)", idx); + cam_dump_tbl_info(); + spin_unlock_bh(&hdl_tbl_lock); + return idx; + } + + get_random_bytes(&rand, CAM_REQ_MGR_RND1_BYTES); + handle = GET_DEV_HANDLE(rand, HDL_TYPE_LINK, idx); + hdl_tbl->hdl[idx].session_hdl = hdl_data->session_hdl; + hdl_tbl->hdl[idx].hdl_value = handle; + hdl_tbl->hdl[idx].type = HDL_TYPE_LINK; + hdl_tbl->hdl[idx].state = HDL_ACTIVE; + hdl_tbl->hdl[idx].priv = hdl_data->priv; + hdl_tbl->hdl[idx].ops = NULL; + hdl_tbl->hdl[idx].dev_id = hdl_data->dev_id; + spin_unlock_bh(&hdl_tbl_lock); + + CAM_DBG(CAM_CRM, "handle = %x", handle); + return handle; +} + +void *cam_get_priv(int32_t dev_hdl, int handle_type) +{ + int idx; + int type; + void *priv; + + spin_lock_bh(&hdl_tbl_lock); + if (!hdl_tbl) { + CAM_ERR_RATE_LIMIT(CAM_CRM, "Hdl tbl is NULL"); + goto device_priv_fail; + } + + idx = CAM_REQ_MGR_GET_HDL_IDX(dev_hdl); + if (idx >= CAM_REQ_MGR_MAX_HANDLES_V2) { + CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid idx: %d", idx); + goto device_priv_fail; + } + + if (hdl_tbl->hdl[idx].state != HDL_ACTIVE) { + CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid state: %d", hdl_tbl->hdl[idx].state); + goto device_priv_fail; + } + + type = CAM_REQ_MGR_GET_HDL_TYPE(dev_hdl); + if (type != handle_type) { + CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid type:%d", type); + goto device_priv_fail; + } + + if (hdl_tbl->hdl[idx].hdl_value != dev_hdl) { + CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid hdl"); + goto device_priv_fail; + } + + priv = hdl_tbl->hdl[idx].priv; + spin_unlock_bh(&hdl_tbl_lock); + + return priv; + +device_priv_fail: + spin_unlock_bh(&hdl_tbl_lock); + return NULL; +} + +void *cam_get_device_priv(int32_t dev_hdl) +{ + void *priv; + + priv = cam_get_priv(dev_hdl, HDL_TYPE_DEV); + return priv; +} + +struct cam_req_mgr_core_session *cam_get_session_priv(int32_t dev_hdl) +{ + struct cam_req_mgr_core_session *priv; + + priv = (struct cam_req_mgr_core_session *) + cam_get_priv(dev_hdl, HDL_TYPE_SESSION); + + return priv; +} + +struct cam_req_mgr_core_link *cam_get_link_priv(int32_t dev_hdl) +{ + struct cam_req_mgr_core_link *priv; + + priv = (struct cam_req_mgr_core_link *) + cam_get_priv(dev_hdl, HDL_TYPE_LINK); + + return priv; +} + +void *cam_get_device_ops(int32_t dev_hdl) +{ + int idx; + int type; + void *ops; + + spin_lock_bh(&hdl_tbl_lock); + if (!hdl_tbl) { + CAM_ERR(CAM_CRM, "Hdl tbl is NULL"); + goto device_ops_fail; + } + + idx = CAM_REQ_MGR_GET_HDL_IDX(dev_hdl); + if (idx >= CAM_REQ_MGR_MAX_HANDLES_V2) { + CAM_ERR(CAM_CRM, "Invalid idx"); + goto device_ops_fail; + } + + if (hdl_tbl->hdl[idx].state != HDL_ACTIVE) { + CAM_ERR(CAM_CRM, "Invalid state"); + goto device_ops_fail; + } + + type = CAM_REQ_MGR_GET_HDL_TYPE(dev_hdl); + if (HDL_TYPE_DEV != type && HDL_TYPE_SESSION != type && HDL_TYPE_LINK != type) { + CAM_ERR(CAM_CRM, "Invalid type"); + goto device_ops_fail; + } + + if (hdl_tbl->hdl[idx].hdl_value != dev_hdl) { + CAM_ERR(CAM_CRM, "Invalid hdl"); + goto device_ops_fail; + } + + ops = hdl_tbl->hdl[idx].ops; + spin_unlock_bh(&hdl_tbl_lock); + + return ops; + +device_ops_fail: + spin_unlock_bh(&hdl_tbl_lock); + return NULL; +} + +static int cam_destroy_hdl(int32_t dev_hdl, int dev_hdl_type) +{ + int idx; + int type; + + spin_lock_bh(&hdl_tbl_lock); + if (!hdl_tbl) { + CAM_ERR(CAM_CRM, "Hdl tbl is NULL"); + goto destroy_hdl_fail; + } + + idx = CAM_REQ_MGR_GET_HDL_IDX(dev_hdl); + if (idx >= CAM_REQ_MGR_MAX_HANDLES_V2) { + CAM_ERR(CAM_CRM, "Invalid idx %d", idx); + goto destroy_hdl_fail; + } + + if (hdl_tbl->hdl[idx].state != HDL_ACTIVE) { + CAM_ERR(CAM_CRM, "Invalid state"); + goto destroy_hdl_fail; + } + + type = CAM_REQ_MGR_GET_HDL_TYPE(dev_hdl); + if (type != dev_hdl_type) { + CAM_ERR(CAM_CRM, "Invalid type %d, %d", type, dev_hdl_type); + goto destroy_hdl_fail; + } + + if (hdl_tbl->hdl[idx].hdl_value != dev_hdl) { + CAM_ERR(CAM_CRM, "Invalid hdl"); + goto destroy_hdl_fail; + } + + hdl_tbl->hdl[idx].state = HDL_FREE; + hdl_tbl->hdl[idx].ops = NULL; + hdl_tbl->hdl[idx].priv = NULL; + clear_bit(idx, hdl_tbl->bitmap); + spin_unlock_bh(&hdl_tbl_lock); + + return 0; + +destroy_hdl_fail: + spin_unlock_bh(&hdl_tbl_lock); + return -EINVAL; +} + +int cam_destroy_device_hdl(int32_t dev_hdl) +{ + return cam_destroy_hdl(dev_hdl, HDL_TYPE_DEV); +} + +int cam_destroy_link_hdl(int32_t dev_hdl) +{ + CAM_DBG(CAM_CRM, "handle = %x", dev_hdl); + return cam_destroy_hdl(dev_hdl, HDL_TYPE_LINK); +} + +int cam_destroy_session_hdl(int32_t dev_hdl) +{ + return cam_destroy_hdl(dev_hdl, HDL_TYPE_SESSION); +} diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_util.h b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_util.h new file mode 100644 index 0000000000000000000000000000000000000000..7fbaad2447a082474356c17f362466ac46e27327 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_util.h @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CAM_REQ_MGR_UTIL_API_H_ +#define _CAM_REQ_MGR_UTIL_API_H_ + +#include +#include "cam_req_mgr_util_priv.h" + +/* Interval for cam_info_rate_limit_custom() */ +#define CAM_RATE_LIMIT_INTERVAL_5SEC 5 + +/** + * state of a handle(session/device) + * @HDL_FREE: free handle + * @HDL_ACTIVE: active handles + */ +enum hdl_state { + HDL_FREE, + HDL_ACTIVE +}; + +/** + * handle type + * @HDL_TYPE_DEV: for device + * @HDL_TYPE_SESSION: for session + * @HDL_TYPE_LINK: for link + */ +enum hdl_type { + HDL_TYPE_DEV = 1, + HDL_TYPE_SESSION, + HDL_TYPE_LINK +}; + +/** + * struct handle + * @session_hdl: session handle + * @hdl_value: Allocated handle + * @type: session/device handle + * @state: free/used + * @dev_id: device id for handle + * @ops: ops structure + * @priv: private data of a handle + */ +struct handle { + int32_t session_hdl; + uint32_t hdl_value; + enum hdl_type type; + enum hdl_state state; + uint64_t dev_id; + void *ops; + void *priv; +}; + +/** + * struct cam_req_mgr_util_hdl_tbl + * @hdl: row of handles + * @bitmap: bit map to get free hdl row idx + * @bits: size of bit map in bits + */ +struct cam_req_mgr_util_hdl_tbl { + struct handle hdl[CAM_REQ_MGR_MAX_HANDLES_V2]; + void *bitmap; + size_t bits; +}; + +/** + * cam_req_mgr_util APIs for KMD drivers and cam_req_mgr + * @session_hdl: session_hdl info + * @v4l2_sub_dev_flag: flag to create v4l2 sub device + * @media_entity_flag: flag for media entity + * @reserved: reserved field + * @dev_id: device id for handle + * @ops: ops pointer for a device handle + * @priv: private data for a device handle + */ +struct cam_create_dev_hdl { + int32_t session_hdl; + int32_t v4l2_sub_dev_flag; + int32_t media_entity_flag; + int32_t reserved; + uint64_t dev_id; + void *ops; + void *priv; +}; + +/** + * cam_create_session_hdl() - create a session handle + * @priv: private data for a session handle + * + * cam_req_mgr core calls this function to get + * a unique session handle. Returns a unique session + * handle + */ +int32_t cam_create_session_hdl(void *priv); + +/** + * cam_create_device_hdl() - create a device handle + * @hdl_data: session hdl, flags, ops and priv dara as input + * + * cam_req_mgr_core calls this function to get + * session and link handles + * KMD drivers calls this function to create + * a device handle. Returns a unique device handle + */ +int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data); + +/** + * cam_create_link_hdl() - create a link handle + * @hdl_data: session hdl, flags, ops and priv dara as input + * + * cam_req_mgr_core calls this function to get + * session and link handles + * KMD drivers calls this function to create + * a link handle. Returns a unique link handle + */ +int32_t cam_create_link_hdl(struct cam_create_dev_hdl *hdl_data); + +/** + * cam_get_device_priv() - get private data of a device handle + * @dev_hdl: handle for a device + * + * cam_req_mgr_core and KMD drivers use this function to + * get private data of a handle. Returns a private data + * structure pointer. + */ +void *cam_get_device_priv(int32_t dev_hdl); + +/** + * cam_get_session_priv() - get private data of a session handle + * @dev_hdl: handle for a session + * + * cam_req_mgr_core and KMD drivers use this function to + * get private data of a handle. Returns a private data + * structure pointer. + */ +struct cam_req_mgr_core_session *cam_get_session_priv(int32_t dev_hdl); + +/** + * cam_get_link_priv() - get private data of a link handle + * @dev_hdl: handle for a link + * + * cam_req_mgr_core and KMD drivers use this function to + * get private data of a handle. Returns a private data + * structure pointer. + */ +struct cam_req_mgr_core_link *cam_get_link_priv(int32_t dev_hdl); + +/** + * cam_get_device_ops() - get ops of a handle + * @dev_hdl: handle for a session/link/device + * + * cam_req_mgr_core and KMD drivers use this function to + * get ops of a handle. Returns a pointer to ops. + */ +void *cam_get_device_ops(int32_t dev_hdl); + +/** + * cam_destroy_device_hdl() - destroy device handle + * @dev_hdl: handle for a device. + * + * Returns success/failure + */ +int32_t cam_destroy_device_hdl(int32_t dev_hdl); + +/** + * cam_destroy_link_hdl() - destroy link handle + * @dev_hdl: handle for a link. + * + * Returns success/failure + */ +int32_t cam_destroy_link_hdl(int32_t dev_hdl); + +/** + * cam_destroy_session_hdl() - destroy device handle + * @dev_hdl: handle for a session + * + * Returns success/failure + */ +int32_t cam_destroy_session_hdl(int32_t dev_hdl); + + +/* Internal functions */ +/** + * cam_req_mgr_util_init() - init function of cam_req_mgr_util + * + * This is called as part of probe function to initialize + * handle table, bitmap, locks + */ +int cam_req_mgr_util_init(void); + +/** + * cam_req_mgr_util_deinit() - deinit function of cam_req_mgr_util + * + * This function is called in case of probe failure + */ +int32_t cam_req_mgr_util_deinit(void); + +/** + * cam_req_mgr_util_free_hdls() - free handles in case of crash + * + * Called from cam_req_mgr_dev release function to make sure + * all data structures are cleaned to avoid leaks + * + * cam_req_mgr core can call this function at the end of + * camera to make sure all stale entries are printed and + * cleaned + */ +int32_t cam_req_mgr_util_free_hdls(void); + +#endif /* _CAM_REQ_MGR_UTIL_API_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_util_priv.h b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_util_priv.h new file mode 100644 index 0000000000000000000000000000000000000000..075f5c34702d109916f99bd635bf4beb2f36bc05 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_util_priv.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_REQ_MGR_UTIL_PRIV_H_ +#define _CAM_REQ_MGR_UTIL_PRIV_H_ + +/** + * handle format: + * @bits (0-7): handle index + * @bits (8-11): handle type + * @bits (12-15): reserved + * @bits (16-23): random bits + * @bits (24-31): zeros + */ + +#define CAM_REQ_MGR_HDL_SIZE 32 +#define CAM_REQ_MGR_RND1_SIZE 8 +#define CAM_REQ_MGR_RVD_SIZE 4 +#define CAM_REQ_MGR_HDL_TYPE_SIZE 4 +#define CAM_REQ_MGR_HDL_IDX_SIZE 8 + +#define CAM_REQ_MGR_RND1_POS 24 +#define CAM_REQ_MGR_RVD_POS 16 +#define CAM_REQ_MGR_HDL_TYPE_POS 12 + +#define CAM_REQ_MGR_RND1_BYTES 1 + +#define CAM_REQ_MGR_HDL_TYPE_MASK ((1 << CAM_REQ_MGR_HDL_TYPE_SIZE) - 1) + +#define GET_DEV_HANDLE(rnd1, type, idx) \ + ((rnd1 << (CAM_REQ_MGR_RND1_POS - CAM_REQ_MGR_RND1_SIZE)) | \ + (0x0 << (CAM_REQ_MGR_RVD_POS - CAM_REQ_MGR_RVD_SIZE)) | \ + (type << (CAM_REQ_MGR_HDL_TYPE_POS - CAM_REQ_MGR_HDL_TYPE_SIZE)) | \ + (idx << (CAM_REQ_MGR_HDL_IDX_POS - CAM_REQ_MGR_HDL_IDX_SIZE))) \ + +#define CAM_REQ_MGR_GET_HDL_IDX(hdl) (hdl & CAM_REQ_MGR_HDL_IDX_MASK) +#define CAM_REQ_MGR_GET_HDL_TYPE(hdl) \ + ((hdl >> CAM_REQ_MGR_HDL_IDX_POS) & CAM_REQ_MGR_HDL_TYPE_MASK) + +#endif diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_workq.c b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_workq.c new file mode 100644 index 0000000000000000000000000000000000000000..79fc47f40d62682183acf4a94238de23b0bd7778 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_workq.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + */ + +#include "cam_req_mgr_workq.h" +#include "cam_debug_util.h" + +#define WORKQ_ACQUIRE_LOCK(workq, flags) {\ + if ((workq)->in_irq) \ + spin_lock_irqsave(&(workq)->lock_bh, (flags)); \ + else \ + spin_lock_bh(&(workq)->lock_bh); \ +} + +#define WORKQ_RELEASE_LOCK(workq, flags) {\ + if ((workq)->in_irq) \ + spin_unlock_irqrestore(&(workq)->lock_bh, (flags)); \ + else \ + spin_unlock_bh(&(workq)->lock_bh); \ +} + +struct crm_workq_task *cam_req_mgr_workq_get_task( + struct cam_req_mgr_core_workq *workq) +{ + struct crm_workq_task *task = NULL; + unsigned long flags = 0; + + if (!workq) + return NULL; + + WORKQ_ACQUIRE_LOCK(workq, flags); + if (list_empty(&workq->task.empty_head)) + goto end; + + task = list_first_entry(&workq->task.empty_head, + struct crm_workq_task, entry); + if (task) { + atomic_sub(1, &workq->task.free_cnt); + list_del_init(&task->entry); + } + +end: + WORKQ_RELEASE_LOCK(workq, flags); + + return task; +} + +static void cam_req_mgr_workq_put_task(struct crm_workq_task *task) +{ + struct cam_req_mgr_core_workq *workq = + (struct cam_req_mgr_core_workq *)task->parent; + unsigned long flags = 0; + + list_del_init(&task->entry); + task->cancel = 0; + task->process_cb = NULL; + task->priv = NULL; + WORKQ_ACQUIRE_LOCK(workq, flags); + list_add_tail(&task->entry, + &workq->task.empty_head); + atomic_add(1, &workq->task.free_cnt); + WORKQ_RELEASE_LOCK(workq, flags); +} + +/** + * cam_req_mgr_process_task() - Process the enqueued task + * @task: pointer to task workq thread shall process + */ +static int cam_req_mgr_process_task(struct crm_workq_task *task) +{ + struct cam_req_mgr_core_workq *workq = NULL; + + if (!task) + return -EINVAL; + + workq = (struct cam_req_mgr_core_workq *)task->parent; + if (task->process_cb) + task->process_cb(task->priv, task->payload); + else + CAM_WARN(CAM_CRM, "FATAL:no task handler registered for workq"); + cam_req_mgr_workq_put_task(task); + + return 0; +} + +/** + * cam_req_mgr_process_workq() - main loop handling + * @w: workqueue task pointer + */ +static void cam_req_mgr_process_workq(struct work_struct *w) +{ + struct cam_req_mgr_core_workq *workq = NULL; + struct crm_workq_task *task; + int32_t i = CRM_TASK_PRIORITY_0; + unsigned long flags = 0; + + if (!w) { + CAM_ERR(CAM_CRM, "NULL task pointer can not schedule"); + return; + } + workq = (struct cam_req_mgr_core_workq *) + container_of(w, struct cam_req_mgr_core_workq, work); + + cam_req_mgr_thread_switch_delay_detect(workq->workq_scheduled_ts); + while (i < CRM_TASK_PRIORITY_MAX) { + WORKQ_ACQUIRE_LOCK(workq, flags); + while (!list_empty(&workq->task.process_head[i])) { + task = list_first_entry(&workq->task.process_head[i], + struct crm_workq_task, entry); + atomic_sub(1, &workq->task.pending_cnt); + list_del_init(&task->entry); + WORKQ_RELEASE_LOCK(workq, flags); + cam_req_mgr_process_task(task); + CAM_DBG(CAM_CRM, "processed task %pK free_cnt %d", + task, atomic_read(&workq->task.free_cnt)); + WORKQ_ACQUIRE_LOCK(workq, flags); + } + WORKQ_RELEASE_LOCK(workq, flags); + i++; + } +} + +int cam_req_mgr_workq_enqueue_task(struct crm_workq_task *task, + void *priv, int32_t prio) +{ + int rc = 0; + struct cam_req_mgr_core_workq *workq = NULL; + unsigned long flags = 0; + + if (!task) { + CAM_WARN(CAM_CRM, "NULL task pointer can not schedule"); + rc = -EINVAL; + goto end; + } + workq = (struct cam_req_mgr_core_workq *)task->parent; + if (!workq) { + CAM_DBG(CAM_CRM, "NULL workq pointer suspect mem corruption"); + rc = -EINVAL; + goto end; + } + + if (task->cancel == 1) { + cam_req_mgr_workq_put_task(task); + CAM_WARN(CAM_CRM, "task aborted and queued back to pool"); + rc = 0; + goto end; + } + task->priv = priv; + task->priority = + (prio < CRM_TASK_PRIORITY_MAX && prio >= CRM_TASK_PRIORITY_0) + ? prio : CRM_TASK_PRIORITY_0; + + WORKQ_ACQUIRE_LOCK(workq, flags); + if (!workq->job) { + rc = -EINVAL; + WORKQ_RELEASE_LOCK(workq, flags); + goto end; + } + + list_add_tail(&task->entry, + &workq->task.process_head[task->priority]); + + atomic_add(1, &workq->task.pending_cnt); + CAM_DBG(CAM_CRM, "enq task %pK pending_cnt %d", + task, atomic_read(&workq->task.pending_cnt)); + + workq->workq_scheduled_ts = ktime_get(); + queue_work(workq->job, &workq->work); + WORKQ_RELEASE_LOCK(workq, flags); +end: + return rc; +} + +int cam_req_mgr_workq_create(char *name, int32_t num_tasks, + struct cam_req_mgr_core_workq **workq, enum crm_workq_context in_irq, + int flags) +{ + int32_t i, wq_flags = 0, max_active_tasks = 0; + struct crm_workq_task *task; + struct cam_req_mgr_core_workq *crm_workq = NULL; + char buf[128] = "crm_workq-"; + + if (!*workq) { + crm_workq = kzalloc(sizeof(struct cam_req_mgr_core_workq), + GFP_KERNEL); + if (crm_workq == NULL) + return -ENOMEM; + + wq_flags |= WQ_UNBOUND; + if (flags & CAM_WORKQ_FLAG_HIGH_PRIORITY) + wq_flags |= WQ_HIGHPRI; + + if (flags & CAM_WORKQ_FLAG_SERIAL) + max_active_tasks = 1; + + strlcat(buf, name, sizeof(buf)); + CAM_DBG(CAM_CRM, "create workque crm_workq-%s", name); + crm_workq->job = alloc_workqueue(buf, + wq_flags, max_active_tasks, NULL); + if (!crm_workq->job) { + kfree(crm_workq); + return -ENOMEM; + } + + /* Workq attributes initialization */ + INIT_WORK(&crm_workq->work, cam_req_mgr_process_workq); + spin_lock_init(&crm_workq->lock_bh); + CAM_DBG(CAM_CRM, "LOCK_DBG workq %s lock %pK", + name, &crm_workq->lock_bh); + + /* Task attributes initialization */ + atomic_set(&crm_workq->task.pending_cnt, 0); + atomic_set(&crm_workq->task.free_cnt, 0); + for (i = CRM_TASK_PRIORITY_0; i < CRM_TASK_PRIORITY_MAX; i++) + INIT_LIST_HEAD(&crm_workq->task.process_head[i]); + INIT_LIST_HEAD(&crm_workq->task.empty_head); + crm_workq->in_irq = in_irq; + crm_workq->task.num_task = num_tasks; + crm_workq->task.pool = kcalloc(crm_workq->task.num_task, + sizeof(struct crm_workq_task), GFP_KERNEL); + if (!crm_workq->task.pool) { + CAM_WARN(CAM_CRM, "Insufficient memory %zu", + sizeof(struct crm_workq_task) * + crm_workq->task.num_task); + kfree(crm_workq); + return -ENOMEM; + } + + for (i = 0; i < crm_workq->task.num_task; i++) { + task = &crm_workq->task.pool[i]; + task->parent = (void *)crm_workq; + /* Put all tasks in free pool */ + INIT_LIST_HEAD(&task->entry); + cam_req_mgr_workq_put_task(task); + } + *workq = crm_workq; + CAM_DBG(CAM_CRM, "free tasks %d", + atomic_read(&crm_workq->task.free_cnt)); + } + + return 0; +} + +void cam_req_mgr_workq_destroy(struct cam_req_mgr_core_workq **crm_workq) +{ + unsigned long flags = 0; + struct workqueue_struct *job; + + CAM_DBG(CAM_CRM, "destroy workque %pK", crm_workq); + if (*crm_workq) { + WORKQ_ACQUIRE_LOCK(*crm_workq, flags); + if ((*crm_workq)->job) { + job = (*crm_workq)->job; + (*crm_workq)->job = NULL; + WORKQ_RELEASE_LOCK(*crm_workq, flags); + destroy_workqueue(job); + } else { + WORKQ_RELEASE_LOCK(*crm_workq, flags); + } + + /* Destroy workq payload data */ + kfree((*crm_workq)->task.pool[0].payload); + (*crm_workq)->task.pool[0].payload = NULL; + kfree((*crm_workq)->task.pool); + kfree(*crm_workq); + *crm_workq = NULL; + } +} + +void cam_req_mgr_thread_switch_delay_detect(ktime_t workq_scheduled) +{ + uint64_t diff; + ktime_t cur_time; + struct timespec64 cur_ts; + struct timespec64 workq_scheduled_ts; + + cur_time = ktime_get(); + diff = ktime_ms_delta(cur_time, workq_scheduled); + workq_scheduled_ts = ktime_to_timespec64(workq_scheduled); + cur_ts = ktime_to_timespec64(cur_time); + + if (diff > CAM_WORKQ_RESPONSE_TIME_THRESHOLD) { + CAM_ERR(CAM_CRM, + "Workq delay detected %ld:%06ld %ld:%06ld %ld:", + workq_scheduled_ts.tv_sec, + workq_scheduled_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, cur_ts.tv_nsec/NSEC_PER_USEC, + diff); + } +} diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_workq.h b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_workq.h new file mode 100644 index 0000000000000000000000000000000000000000..5956b1a233c493dba92835dc4f4d77186d6dba4f --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_req_mgr_workq.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_REQ_MGR_WORKQ_H_ +#define _CAM_REQ_MGR_WORKQ_H_ + +#include +#include +#include +#include +#include +#include +#include + +#include "cam_req_mgr_core.h" + +/* Flag to create a high priority workq */ +#define CAM_WORKQ_FLAG_HIGH_PRIORITY (1 << 0) + +/* + * This flag ensures only one task from a given + * workq will execute at any given point on any + * given CPU. + */ +#define CAM_WORKQ_FLAG_SERIAL (1 << 1) + +/* + * Response time threshold in ms beyond which it is considered + * as workq scheduling/processing delay. + */ +#define CAM_WORKQ_RESPONSE_TIME_THRESHOLD 5 + + +/* Task priorities, lower the number higher the priority*/ +enum crm_task_priority { + CRM_TASK_PRIORITY_0, + CRM_TASK_PRIORITY_1, + CRM_TASK_PRIORITY_MAX, +}; + +/* workqueue will be used from irq context or not */ +enum crm_workq_context { + CRM_WORKQ_USAGE_NON_IRQ, + CRM_WORKQ_USAGE_IRQ, + CRM_WORKQ_USAGE_INVALID, +}; + +/** struct crm_workq_task + * @priority : caller can assign priority to task based on type. + * @payload : depending of user of task this payload type will change + * @process_cb : registered callback called by workq when task enqueued is + * ready for processing in workq thread context + * @parent : workq's parent is link which is enqqueing taks to this workq + * @entry : list head of this list entry is worker's empty_head + * @cancel : if caller has got free task from pool but wants to abort + * or put back without using it + * @priv : when task is enqueuer caller can attach priv along which + * it will get in process callback + * @ret : return value in future to use for blocking calls + */ +struct crm_workq_task { + int32_t priority; + void *payload; + int32_t (*process_cb)(void *priv, void *data); + void *parent; + struct list_head entry; + uint8_t cancel; + void *priv; + int32_t ret; +}; + +/** struct cam_req_mgr_core_workq + * @work : work token used by workqueue + * @job : workqueue internal job struct + * @workq_scheduled_ts: workqueue scheduled timestamp + * task - + * @lock_bh : lock for task structs + * @in_irq : set true if workque can be used in irq context + * @free_cnt : num of free/available tasks + * @empty_head : list head of available taska which can be used + * or acquired in order to enqueue a task to workq + * @pool : pool of tasks used for handling events in workq context + * @num_task : size of tasks pool + * - + */ +struct cam_req_mgr_core_workq { + struct work_struct work; + struct workqueue_struct *job; + spinlock_t lock_bh; + uint32_t in_irq; + ktime_t workq_scheduled_ts; + + /* tasks */ + struct { + struct mutex lock; + atomic_t pending_cnt; + atomic_t free_cnt; + + struct list_head process_head[CRM_TASK_PRIORITY_MAX]; + struct list_head empty_head; + struct crm_workq_task *pool; + uint32_t num_task; + } task; +}; + +/** + * cam_req_mgr_workq_create() + * @brief : create a workqueue + * @name : Name of the workque to be allocated, it is combination + * of session handle and link handle + * @num_task : Num_tasks to be allocated for workq + * @workq : Double pointer worker + * @in_irq : Set to one if workq might be used in irq context + * @flags : Bitwise OR of Flags for workq behavior. + * e.g. CAM_REQ_MGR_WORKQ_HIGH_PRIORITY | CAM_REQ_MGR_WORKQ_SERIAL + * This function will allocate and create workqueue and pass + * the workq pointer to caller. + */ +int cam_req_mgr_workq_create(char *name, int32_t num_tasks, + struct cam_req_mgr_core_workq **workq, enum crm_workq_context in_irq, + int flags); + +/** + * cam_req_mgr_workq_destroy() + * @brief: destroy workqueue + * @workq: pointer to worker data struct + * this function will destroy workqueue and clean up resources + * associated with worker such as tasks. + */ +void cam_req_mgr_workq_destroy(struct cam_req_mgr_core_workq **workq); + +/** + * cam_req_mgr_workq_enqueue_task() + * @brief: Enqueue task in worker queue + * @task : task to be processed by worker + * @priv : clients private data + * @prio : task priority + * process callback func + */ +int cam_req_mgr_workq_enqueue_task(struct crm_workq_task *task, + void *priv, int32_t prio); + +/** + * cam_req_mgr_thread_switch_delay_detect() + * @brief: Detects if workq delay has occurred or not + * @timestamp: workq scheduled timestamp + */ +void cam_req_mgr_thread_switch_delay_detect( + ktime_t timestamp); + +/** + * cam_req_mgr_workq_get_task() + * @brief: Returns empty task pointer for use + * @workq: workque used for processing + */ +struct crm_workq_task *cam_req_mgr_workq_get_task( + struct cam_req_mgr_core_workq *workq); + +#endif diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/cam_subdev.h b/techpack/camera-bengal/drivers/cam_req_mgr/cam_subdev.h new file mode 100644 index 0000000000000000000000000000000000000000..783b33a55f1770451b2250baafdf3da3c213d133 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_req_mgr/cam_subdev.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_SUBDEV_H_ +#define _CAM_SUBDEV_H_ + +#include +#include +#include +#include +#include +#include +#include + +#define CAM_SUBDEVICE_EVENT_MAX 30 + +enum cam_subdev_message_type_t { + CAM_SUBDEV_MESSAGE_IRQ_ERR = 0x1 +}; + +enum cam_subdev_rwsem { + CAM_SUBDEV_LOCK = 1, + CAM_SUBDEV_UNLOCK, +}; + +/** + * struct cam_subdev - describes a camera sub-device + * + * @pdev: Pointer to the platform device + * @sd: V4l2 subdevice + * @ops: V4l2 subdecie operations + * @internal_ops: V4l2 subdevice internal operations + * @name: Name of the sub-device. Please notice that the name + * must be unique. + * @sd_flags: Subdev flags. Can be: + * %V4L2_SUBDEV_FL_HAS_DEVNODE - Set this flag if + * this subdev needs a device node. + * %V4L2_SUBDEV_FL_HAS_EVENTS - Set this flag if + * this subdev generates events. + * @token: Pointer to cookie of the client driver + * @ent_function: Media entity function type. Can be: + * %CAM_IFE_DEVICE_TYPE - identifies as IFE device. + * %CAM_ICP_DEVICE_TYPE - identifies as ICP device. + * + * Each instance of a subdev driver should create this struct, either + * stand-alone or embedded in a larger struct. This structure should be + * initialized/registered by cam_register_subdev + * + */ +struct cam_subdev { + struct platform_device *pdev; + struct v4l2_subdev sd; + const struct v4l2_subdev_ops *ops; + const struct v4l2_subdev_internal_ops *internal_ops; + char *name; + u32 sd_flags; + void *token; + u32 ent_function; + void (*msg_cb)( + struct v4l2_subdev *sd, + enum cam_subdev_message_type_t msg_type, + uint32_t data); +}; + +/** + * cam_subdev_notify_message() + * + * @brief: Notify message to a subdevs of specific type + * + * @subdev_type: Subdev type + * @message_type: message type + * @data: data to be delivered. + * + */ +void cam_subdev_notify_message(u32 subdev_type, + enum cam_subdev_message_type_t message_type, + uint32_t data); + +/** + * cam_subdev_probe() + * + * @brief: Camera Subdevice node probe function for v4l2 setup + * + * @sd: Camera subdevice object + * @name: Name of the subdevice node + * @dev_type: Subdevice node type + * + */ +int cam_subdev_probe(struct cam_subdev *sd, struct platform_device *pdev, + char *name, uint32_t dev_type); + +/** + * cam_subdev_remove() + * + * @brief: Called when subdevice node is unloaded + * + * @sd: Camera subdevice node object + * + */ +int cam_subdev_remove(struct cam_subdev *sd); + +/** + * cam_register_subdev_fops() + * + * @brief: This common utility function assigns subdev ops + * + * @fops: v4l file operations + */ +void cam_register_subdev_fops(struct v4l2_file_operations *fops); + +/** + * cam_register_subdev() + * + * @brief: This is the common utility function to be called by each camera + * subdevice node when it tries to register itself to the camera + * request manager + * + * @sd: Pointer to struct cam_subdev. + */ +int cam_register_subdev(struct cam_subdev *sd); + +/** + * cam_unregister_subdev() + * + * @brief: This is the common utility function to be called by each camera + * subdevice node when it tries to unregister itself from the + * camera request manger + * + * @sd: Pointer to struct cam_subdev. + */ +int cam_unregister_subdev(struct cam_subdev *sd); + +/** + * cam_req_mgr_rwsem_read_op() + * + * @brief : API to acquire read semaphore lock to platform framework. + * + * @lock : value indicates to lock or unlock the read lock + */ +void cam_req_mgr_rwsem_read_op(enum cam_subdev_rwsem lock); + +/** + * cam_req_mgr_is_open() + * + * @brief: This common utility function returns the crm active status + * + */ +bool cam_req_mgr_is_open(void); + +/** + * cam_req_mgr_is_shutdown() + * + * @brief: This common utility function returns the shutdown state + */ +bool cam_req_mgr_is_shutdown(void); + +#endif /* _CAM_SUBDEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..6925b3aba80f1a9fe6e373a4970a174753860103 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_res_mgr/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_utils/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_cci/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_io/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_csiphy/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_actuator/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_eeprom/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_ois/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_flash/ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..7fcf2ffb2cdacdf2318c20cd097cdf60bf6e6509 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils + + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_actuator_dev.o cam_actuator_core.o cam_actuator_soc.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c new file mode 100644 index 0000000000000000000000000000000000000000..8159ea75a1eb5dc208f4983fd0c26bf0fc91232a --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -0,0 +1,1061 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "cam_actuator_core.h" +#include "cam_sensor_util.h" +#include "cam_trace.h" +#include "cam_common_util.h" +#include "cam_packet_util.h" + +int32_t cam_actuator_construct_default_power_setting( + struct cam_sensor_power_ctrl_t *power_info) +{ + int rc = 0; + + power_info->power_setting_size = 1; + power_info->power_setting = + kzalloc(sizeof(struct cam_sensor_power_setting), + GFP_KERNEL); + if (!power_info->power_setting) + return -ENOMEM; + + power_info->power_setting[0].seq_type = SENSOR_VAF; + power_info->power_setting[0].seq_val = CAM_VAF; + power_info->power_setting[0].config_val = 1; + power_info->power_setting[0].delay = 2; + + power_info->power_down_setting_size = 1; + power_info->power_down_setting = + kzalloc(sizeof(struct cam_sensor_power_setting), + GFP_KERNEL); + if (!power_info->power_down_setting) { + rc = -ENOMEM; + goto free_power_settings; + } + + power_info->power_down_setting[0].seq_type = SENSOR_VAF; + power_info->power_down_setting[0].seq_val = CAM_VAF; + power_info->power_down_setting[0].config_val = 0; + + return rc; + +free_power_settings: + kfree(power_info->power_setting); + power_info->power_setting = NULL; + power_info->power_setting_size = 0; + return rc; +} + +static int32_t cam_actuator_power_up(struct cam_actuator_ctrl_t *a_ctrl) +{ + int rc = 0; + struct cam_hw_soc_info *soc_info = + &a_ctrl->soc_info; + struct cam_actuator_soc_private *soc_private; + struct cam_sensor_power_ctrl_t *power_info; + + soc_private = + (struct cam_actuator_soc_private *)a_ctrl->soc_info.soc_private; + power_info = &soc_private->power_info; + + if ((power_info->power_setting == NULL) && + (power_info->power_down_setting == NULL)) { + CAM_INFO(CAM_ACTUATOR, + "Using default power settings"); + rc = cam_actuator_construct_default_power_setting(power_info); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Construct default actuator power setting failed."); + return rc; + } + } + + /* Parse and fill vreg params for power up settings */ + rc = msm_camera_fill_vreg_params( + &a_ctrl->soc_info, + power_info->power_setting, + power_info->power_setting_size); + if (rc) { + CAM_ERR(CAM_ACTUATOR, + "failed to fill vreg params for power up rc:%d", rc); + return rc; + } + + /* Parse and fill vreg params for power down settings*/ + rc = msm_camera_fill_vreg_params( + &a_ctrl->soc_info, + power_info->power_down_setting, + power_info->power_down_setting_size); + if (rc) { + CAM_ERR(CAM_ACTUATOR, + "failed to fill vreg params power down rc:%d", rc); + return rc; + } + + power_info->dev = soc_info->dev; + + rc = cam_sensor_core_power_up(power_info, soc_info); + if (rc) { + CAM_ERR(CAM_ACTUATOR, + "failed in actuator power up rc %d", rc); + return rc; + } + + rc = camera_io_init(&a_ctrl->io_master_info); + if (rc < 0) + CAM_ERR(CAM_ACTUATOR, "cci init failed: rc: %d", rc); + + return rc; +} + +static int32_t cam_actuator_power_down(struct cam_actuator_ctrl_t *a_ctrl) +{ + int32_t rc = 0; + struct cam_sensor_power_ctrl_t *power_info; + struct cam_hw_soc_info *soc_info = &a_ctrl->soc_info; + struct cam_actuator_soc_private *soc_private; + + if (!a_ctrl) { + CAM_ERR(CAM_ACTUATOR, "failed: a_ctrl %pK", a_ctrl); + return -EINVAL; + } + + soc_private = + (struct cam_actuator_soc_private *)a_ctrl->soc_info.soc_private; + power_info = &soc_private->power_info; + soc_info = &a_ctrl->soc_info; + + if (!power_info) { + CAM_ERR(CAM_ACTUATOR, "failed: power_info %pK", power_info); + return -EINVAL; + } + rc = cam_sensor_util_power_down(power_info, soc_info); + if (rc) { + CAM_ERR(CAM_ACTUATOR, "power down the core is failed:%d", rc); + return rc; + } + + camera_io_release(&a_ctrl->io_master_info); + + return rc; +} + +static int32_t cam_actuator_i2c_modes_util( + struct camera_io_master *io_master_info, + struct i2c_settings_list *i2c_list) +{ + int32_t rc = 0; + uint32_t i, size; + + if (i2c_list->op_code == CAM_SENSOR_I2C_WRITE_RANDOM) { + rc = camera_io_dev_write(io_master_info, + &(i2c_list->i2c_settings)); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Failed to random write I2C settings: %d", + rc); + return rc; + } + } else if (i2c_list->op_code == CAM_SENSOR_I2C_WRITE_SEQ) { + rc = camera_io_dev_write_continuous( + io_master_info, + &(i2c_list->i2c_settings), + 0); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Failed to seq write I2C settings: %d", + rc); + return rc; + } + } else if (i2c_list->op_code == CAM_SENSOR_I2C_WRITE_BURST) { + rc = camera_io_dev_write_continuous( + io_master_info, + &(i2c_list->i2c_settings), + 1); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Failed to burst write I2C settings: %d", + rc); + return rc; + } + } else if (i2c_list->op_code == CAM_SENSOR_I2C_POLL) { + size = i2c_list->i2c_settings.size; + for (i = 0; i < size; i++) { + rc = camera_io_dev_poll( + io_master_info, + i2c_list->i2c_settings.reg_setting[i].reg_addr, + i2c_list->i2c_settings.reg_setting[i].reg_data, + i2c_list->i2c_settings.reg_setting[i].data_mask, + i2c_list->i2c_settings.addr_type, + i2c_list->i2c_settings.data_type, + i2c_list->i2c_settings.reg_setting[i].delay); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "i2c poll apply setting Fail: %d", rc); + return rc; + } + } + } + + return rc; +} + +int32_t cam_actuator_slaveInfo_pkt_parser(struct cam_actuator_ctrl_t *a_ctrl, + uint32_t *cmd_buf, size_t len) +{ + int32_t rc = 0; + struct cam_cmd_i2c_info *i2c_info; + + if (!a_ctrl || !cmd_buf || (len < sizeof(struct cam_cmd_i2c_info))) { + CAM_ERR(CAM_ACTUATOR, "Invalid Args"); + return -EINVAL; + } + + i2c_info = (struct cam_cmd_i2c_info *)cmd_buf; + if (a_ctrl->io_master_info.master_type == CCI_MASTER) { + a_ctrl->io_master_info.cci_client->cci_i2c_master = + a_ctrl->cci_i2c_master; + a_ctrl->io_master_info.cci_client->i2c_freq_mode = + i2c_info->i2c_freq_mode; + a_ctrl->io_master_info.cci_client->sid = + i2c_info->slave_addr >> 1; + CAM_DBG(CAM_ACTUATOR, "Slave addr: 0x%x Freq Mode: %d", + i2c_info->slave_addr, i2c_info->i2c_freq_mode); + } else if (a_ctrl->io_master_info.master_type == I2C_MASTER) { + a_ctrl->io_master_info.client->addr = i2c_info->slave_addr; + CAM_DBG(CAM_ACTUATOR, "Slave addr: 0x%x", i2c_info->slave_addr); + } else { + CAM_ERR(CAM_ACTUATOR, "Invalid Master type: %d", + a_ctrl->io_master_info.master_type); + rc = -EINVAL; + } + + return rc; +} + +int32_t cam_actuator_apply_settings(struct cam_actuator_ctrl_t *a_ctrl, + struct i2c_settings_array *i2c_set) +{ + struct i2c_settings_list *i2c_list; + int32_t rc = 0; + + if (a_ctrl == NULL || i2c_set == NULL) { + CAM_ERR(CAM_ACTUATOR, "Invalid Args"); + return -EINVAL; + } + + if (i2c_set->is_settings_valid != 1) { + CAM_ERR(CAM_ACTUATOR, " Invalid settings"); + return -EINVAL; + } + + list_for_each_entry(i2c_list, + &(i2c_set->list_head), list) { + rc = cam_actuator_i2c_modes_util( + &(a_ctrl->io_master_info), + i2c_list); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Failed to apply settings: %d", + rc); + } else { + CAM_DBG(CAM_ACTUATOR, + "Success:request ID: %d", + i2c_set->request_id); + } + } + + return rc; +} + +int32_t cam_actuator_apply_request(struct cam_req_mgr_apply_request *apply) +{ + int32_t rc = 0, request_id, del_req_id; + struct cam_actuator_ctrl_t *a_ctrl = NULL; + + if (!apply) { + CAM_ERR(CAM_ACTUATOR, "Invalid Input Args"); + return -EINVAL; + } + + a_ctrl = (struct cam_actuator_ctrl_t *) + cam_get_device_priv(apply->dev_hdl); + if (!a_ctrl) { + CAM_ERR(CAM_ACTUATOR, "Device data is NULL"); + return -EINVAL; + } + request_id = apply->request_id % MAX_PER_FRAME_ARRAY; + + trace_cam_apply_req("Actuator", apply->request_id); + + CAM_DBG(CAM_ACTUATOR, "Request Id: %lld", apply->request_id); + mutex_lock(&(a_ctrl->actuator_mutex)); + if ((apply->request_id == + a_ctrl->i2c_data.per_frame[request_id].request_id) && + (a_ctrl->i2c_data.per_frame[request_id].is_settings_valid) + == 1) { + rc = cam_actuator_apply_settings(a_ctrl, + &a_ctrl->i2c_data.per_frame[request_id]); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Failed in applying the request: %lld\n", + apply->request_id); + goto release_mutex; + } + } + del_req_id = (request_id + + MAX_PER_FRAME_ARRAY - MAX_SYSTEM_PIPELINE_DELAY) % + MAX_PER_FRAME_ARRAY; + + if (apply->request_id > + a_ctrl->i2c_data.per_frame[del_req_id].request_id) { + a_ctrl->i2c_data.per_frame[del_req_id].request_id = 0; + rc = delete_request(&a_ctrl->i2c_data.per_frame[del_req_id]); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Fail deleting the req: %d err: %d\n", + del_req_id, rc); + goto release_mutex; + } + } else { + CAM_DBG(CAM_ACTUATOR, "No Valid Req to clean Up"); + } + +release_mutex: + mutex_unlock(&(a_ctrl->actuator_mutex)); + return rc; +} + +int32_t cam_actuator_establish_link( + struct cam_req_mgr_core_dev_link_setup *link) +{ + struct cam_actuator_ctrl_t *a_ctrl = NULL; + + if (!link) { + CAM_ERR(CAM_ACTUATOR, "Invalid Args"); + return -EINVAL; + } + + a_ctrl = (struct cam_actuator_ctrl_t *) + cam_get_device_priv(link->dev_hdl); + if (!a_ctrl) { + CAM_ERR(CAM_ACTUATOR, "Device data is NULL"); + return -EINVAL; + } + + mutex_lock(&(a_ctrl->actuator_mutex)); + if (link->link_enable) { + a_ctrl->bridge_intf.link_hdl = link->link_hdl; + a_ctrl->bridge_intf.crm_cb = link->crm_cb; + } else { + a_ctrl->bridge_intf.link_hdl = -1; + a_ctrl->bridge_intf.crm_cb = NULL; + } + mutex_unlock(&(a_ctrl->actuator_mutex)); + + return 0; +} + +static void cam_actuator_update_req_mgr( + struct cam_actuator_ctrl_t *a_ctrl, + struct cam_packet *csl_packet) +{ + struct cam_req_mgr_add_request add_req; + + add_req.link_hdl = a_ctrl->bridge_intf.link_hdl; + add_req.req_id = csl_packet->header.request_id; + add_req.dev_hdl = a_ctrl->bridge_intf.device_hdl; + add_req.skip_before_applying = 0; + + if (a_ctrl->bridge_intf.crm_cb && + a_ctrl->bridge_intf.crm_cb->add_req) { + a_ctrl->bridge_intf.crm_cb->add_req(&add_req); + CAM_DBG(CAM_ACTUATOR, "Request Id: %lld added to CRM", + add_req.req_id); + } else { + CAM_ERR(CAM_ACTUATOR, "Can't add Request ID: %lld to CRM", + csl_packet->header.request_id); + } +} + +int32_t cam_actuator_publish_dev_info(struct cam_req_mgr_device_info *info) +{ + if (!info) { + CAM_ERR(CAM_ACTUATOR, "Invalid Args"); + return -EINVAL; + } + + info->dev_id = CAM_REQ_MGR_DEVICE_ACTUATOR; + strlcpy(info->name, CAM_ACTUATOR_NAME, sizeof(info->name)); + info->p_delay = 1; + info->trigger = CAM_TRIGGER_POINT_SOF; + + return 0; +} + +int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, + void *arg) +{ + int32_t rc = 0; + int32_t i = 0; + uint32_t total_cmd_buf_in_bytes = 0; + size_t len_of_buff = 0; + size_t remain_len = 0; + uint32_t *offset = NULL; + uint32_t *cmd_buf = NULL; + uintptr_t generic_ptr; + uintptr_t generic_pkt_ptr; + struct common_header *cmm_hdr = NULL; + struct cam_control *ioctl_ctrl = NULL; + struct cam_packet *csl_packet = NULL; + struct cam_config_dev_cmd config; + struct i2c_data_settings *i2c_data = NULL; + struct i2c_settings_array *i2c_reg_settings = NULL; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct cam_actuator_soc_private *soc_private = NULL; + struct cam_sensor_power_ctrl_t *power_info = NULL; + + if (!a_ctrl || !arg) { + CAM_ERR(CAM_ACTUATOR, "Invalid Args"); + return -EINVAL; + } + + soc_private = + (struct cam_actuator_soc_private *)a_ctrl->soc_info.soc_private; + + power_info = &soc_private->power_info; + + ioctl_ctrl = (struct cam_control *)arg; + if (copy_from_user(&config, + u64_to_user_ptr(ioctl_ctrl->handle), + sizeof(config))) + return -EFAULT; + rc = cam_mem_get_cpu_buf(config.packet_handle, + &generic_pkt_ptr, &len_of_buff); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, "Error in converting command Handle %d", + rc); + return rc; + } + + remain_len = len_of_buff; + if ((sizeof(struct cam_packet) > len_of_buff) || + ((size_t)config.offset >= len_of_buff - + sizeof(struct cam_packet))) { + CAM_ERR(CAM_ACTUATOR, + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), len_of_buff); + rc = -EINVAL; + goto end; + } + + remain_len -= (size_t)config.offset; + csl_packet = (struct cam_packet *) + (generic_pkt_ptr + (uint32_t)config.offset); + + if (cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_ACTUATOR, "Invalid packet params"); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ACTUATOR, "Pkt opcode: %d", csl_packet->header.op_code); + + if ((csl_packet->header.op_code & 0xFFFFFF) != + CAM_ACTUATOR_PACKET_OPCODE_INIT && + csl_packet->header.request_id <= a_ctrl->last_flush_req + && a_ctrl->last_flush_req != 0) { + CAM_DBG(CAM_ACTUATOR, + "reject request %lld, last request to flush %lld", + csl_packet->header.request_id, a_ctrl->last_flush_req); + rc = -EINVAL; + goto end; + } + + if (csl_packet->header.request_id > a_ctrl->last_flush_req) + a_ctrl->last_flush_req = 0; + + switch (csl_packet->header.op_code & 0xFFFFFF) { + case CAM_ACTUATOR_PACKET_OPCODE_INIT: + offset = (uint32_t *)&csl_packet->payload; + offset += (csl_packet->cmd_buf_offset / sizeof(uint32_t)); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + + /* Loop through multiple command buffers */ + for (i = 0; i < csl_packet->num_cmd_buf; i++) { + total_cmd_buf_in_bytes = cmd_desc[i].length; + if (!total_cmd_buf_in_bytes) + continue; + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, + &generic_ptr, &len_of_buff); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, "Failed to get cpu buf"); + goto end; + } + cmd_buf = (uint32_t *)generic_ptr; + if (!cmd_buf) { + CAM_ERR(CAM_ACTUATOR, "invalid cmd buf"); + rc = -EINVAL; + goto end; + } + if ((len_of_buff < sizeof(struct common_header)) || + (cmd_desc[i].offset > (len_of_buff - + sizeof(struct common_header)))) { + CAM_ERR(CAM_ACTUATOR, + "Invalid length for sensor cmd"); + rc = -EINVAL; + goto end; + } + remain_len = len_of_buff - cmd_desc[i].offset; + cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); + cmm_hdr = (struct common_header *)cmd_buf; + + switch (cmm_hdr->cmd_type) { + case CAMERA_SENSOR_CMD_TYPE_I2C_INFO: + CAM_DBG(CAM_ACTUATOR, + "Received slave info buffer"); + rc = cam_actuator_slaveInfo_pkt_parser( + a_ctrl, cmd_buf, remain_len); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Failed to parse slave info: %d", rc); + goto end; + } + break; + case CAMERA_SENSOR_CMD_TYPE_PWR_UP: + case CAMERA_SENSOR_CMD_TYPE_PWR_DOWN: + CAM_DBG(CAM_ACTUATOR, + "Received power settings buffer"); + rc = cam_sensor_update_power_settings( + cmd_buf, + total_cmd_buf_in_bytes, + power_info, remain_len); + if (rc) { + CAM_ERR(CAM_ACTUATOR, + "Failed:parse power settings: %d", + rc); + goto end; + } + break; + default: + CAM_DBG(CAM_ACTUATOR, + "Received initSettings buffer"); + i2c_data = &(a_ctrl->i2c_data); + i2c_reg_settings = + &i2c_data->init_settings; + + i2c_reg_settings->request_id = 0; + i2c_reg_settings->is_settings_valid = 1; + rc = cam_sensor_i2c_command_parser( + &a_ctrl->io_master_info, + i2c_reg_settings, + &cmd_desc[i], 1, NULL); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Failed:parse init settings: %d", + rc); + goto end; + } + break; + } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + } + + if (a_ctrl->cam_act_state == CAM_ACTUATOR_ACQUIRE) { + rc = cam_actuator_power_up(a_ctrl); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + " Actuator Power up failed"); + goto end; + } + a_ctrl->cam_act_state = CAM_ACTUATOR_CONFIG; + } + + rc = cam_actuator_apply_settings(a_ctrl, + &a_ctrl->i2c_data.init_settings); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, "Cannot apply Init settings"); + goto end; + } + + /* Delete the request even if the apply is failed */ + rc = delete_request(&a_ctrl->i2c_data.init_settings); + if (rc < 0) { + CAM_WARN(CAM_ACTUATOR, + "Fail in deleting the Init settings"); + rc = 0; + } + break; + case CAM_ACTUATOR_PACKET_AUTO_MOVE_LENS: + if (a_ctrl->cam_act_state < CAM_ACTUATOR_CONFIG) { + rc = -EINVAL; + CAM_WARN(CAM_ACTUATOR, + "Not in right state to move lens: %d", + a_ctrl->cam_act_state); + goto end; + } + a_ctrl->setting_apply_state = ACT_APPLY_SETTINGS_NOW; + + i2c_data = &(a_ctrl->i2c_data); + i2c_reg_settings = &i2c_data->init_settings; + + i2c_data->init_settings.request_id = + csl_packet->header.request_id; + i2c_reg_settings->is_settings_valid = 1; + offset = (uint32_t *)&csl_packet->payload; + offset += csl_packet->cmd_buf_offset / sizeof(uint32_t); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + rc = cam_sensor_i2c_command_parser( + &a_ctrl->io_master_info, + i2c_reg_settings, + cmd_desc, 1, NULL); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Auto move lens parsing failed: %d", rc); + goto end; + } + cam_actuator_update_req_mgr(a_ctrl, csl_packet); + break; + case CAM_ACTUATOR_PACKET_MANUAL_MOVE_LENS: + if (a_ctrl->cam_act_state < CAM_ACTUATOR_CONFIG) { + rc = -EINVAL; + CAM_WARN(CAM_ACTUATOR, + "Not in right state to move lens: %d", + a_ctrl->cam_act_state); + goto end; + } + + a_ctrl->setting_apply_state = ACT_APPLY_SETTINGS_LATER; + i2c_data = &(a_ctrl->i2c_data); + i2c_reg_settings = &i2c_data->per_frame[ + csl_packet->header.request_id % MAX_PER_FRAME_ARRAY]; + + i2c_reg_settings->request_id = + csl_packet->header.request_id; + i2c_reg_settings->is_settings_valid = 1; + offset = (uint32_t *)&csl_packet->payload; + offset += csl_packet->cmd_buf_offset / sizeof(uint32_t); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + rc = cam_sensor_i2c_command_parser( + &a_ctrl->io_master_info, + i2c_reg_settings, + cmd_desc, 1, NULL); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Manual move lens parsing failed: %d", rc); + goto end; + } + + cam_actuator_update_req_mgr(a_ctrl, csl_packet); + break; + case CAM_PKT_NOP_OPCODE: + if (a_ctrl->cam_act_state < CAM_ACTUATOR_CONFIG) { + CAM_WARN(CAM_ACTUATOR, + "Received NOP packets in invalid state: %d", + a_ctrl->cam_act_state); + rc = -EINVAL; + goto end; + } + cam_actuator_update_req_mgr(a_ctrl, csl_packet); + break; + case CAM_ACTUATOR_PACKET_OPCODE_READ: { + struct cam_buf_io_cfg *io_cfg; + struct i2c_settings_array i2c_read_settings; + + if (a_ctrl->cam_act_state < CAM_ACTUATOR_CONFIG) { + rc = -EINVAL; + CAM_WARN(CAM_ACTUATOR, + "Not in right state to read actuator: %d", + a_ctrl->cam_act_state); + goto end; + } + CAM_DBG(CAM_ACTUATOR, "number of I/O configs: %d:", + csl_packet->num_io_configs); + if (csl_packet->num_io_configs == 0) { + CAM_ERR(CAM_ACTUATOR, "No I/O configs to process"); + rc = -EINVAL; + goto end; + } + + INIT_LIST_HEAD(&(i2c_read_settings.list_head)); + + io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) + &csl_packet->payload + + csl_packet->io_configs_offset); + + if (io_cfg == NULL) { + CAM_ERR(CAM_ACTUATOR, "I/O config is invalid(NULL)"); + rc = -EINVAL; + goto end; + } + + offset = (uint32_t *)&csl_packet->payload; + offset += (csl_packet->cmd_buf_offset / sizeof(uint32_t)); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + i2c_read_settings.is_settings_valid = 1; + i2c_read_settings.request_id = 0; + rc = cam_sensor_i2c_command_parser(&a_ctrl->io_master_info, + &i2c_read_settings, + cmd_desc, 1, io_cfg); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "actuator read pkt parsing failed: %d", rc); + goto end; + } + + rc = cam_sensor_i2c_read_data( + &i2c_read_settings, + &a_ctrl->io_master_info); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, "cannot read data, rc:%d", rc); + delete_request(&i2c_read_settings); + goto end; + } + + rc = delete_request(&i2c_read_settings); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Failed in deleting the read settings"); + goto end; + } + break; + } + default: + CAM_ERR(CAM_ACTUATOR, "Wrong Opcode: %d", + csl_packet->header.op_code & 0xFFFFFF); + rc = -EINVAL; + goto end; + } + +end: + cam_mem_put_cpu_buf(config.packet_handle); + return rc; +} + +void cam_actuator_shutdown(struct cam_actuator_ctrl_t *a_ctrl) +{ + int rc = 0; + struct cam_actuator_soc_private *soc_private = + (struct cam_actuator_soc_private *)a_ctrl->soc_info.soc_private; + struct cam_sensor_power_ctrl_t *power_info = + &soc_private->power_info; + + if (a_ctrl->cam_act_state == CAM_ACTUATOR_INIT) + return; + + if (a_ctrl->cam_act_state >= CAM_ACTUATOR_CONFIG) { + rc = cam_actuator_power_down(a_ctrl); + if (rc < 0) + CAM_ERR(CAM_ACTUATOR, "Actuator Power down failed"); + a_ctrl->cam_act_state = CAM_ACTUATOR_ACQUIRE; + } + + if (a_ctrl->cam_act_state >= CAM_ACTUATOR_ACQUIRE) { + rc = cam_destroy_device_hdl(a_ctrl->bridge_intf.device_hdl); + if (rc < 0) + CAM_ERR(CAM_ACTUATOR, "destroying dhdl failed"); + a_ctrl->bridge_intf.device_hdl = -1; + a_ctrl->bridge_intf.link_hdl = -1; + a_ctrl->bridge_intf.session_hdl = -1; + } + + kfree(power_info->power_setting); + kfree(power_info->power_down_setting); + power_info->power_setting = NULL; + power_info->power_down_setting = NULL; + power_info->power_setting_size = 0; + power_info->power_down_setting_size = 0; + + a_ctrl->cam_act_state = CAM_ACTUATOR_INIT; +} + +int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl, + void *arg) +{ + int rc = 0; + struct cam_control *cmd = (struct cam_control *)arg; + struct cam_actuator_soc_private *soc_private = NULL; + struct cam_sensor_power_ctrl_t *power_info = NULL; + + if (!a_ctrl || !cmd) { + CAM_ERR(CAM_ACTUATOR, "Invalid Args"); + return -EINVAL; + } + + soc_private = + (struct cam_actuator_soc_private *)a_ctrl->soc_info.soc_private; + + power_info = &soc_private->power_info; + + if (cmd->handle_type != CAM_HANDLE_USER_POINTER) { + CAM_ERR(CAM_ACTUATOR, "Invalid handle type: %d", + cmd->handle_type); + return -EINVAL; + } + + CAM_DBG(CAM_ACTUATOR, "Opcode to Actuator: %d", cmd->op_code); + + mutex_lock(&(a_ctrl->actuator_mutex)); + switch (cmd->op_code) { + case CAM_ACQUIRE_DEV: { + struct cam_sensor_acquire_dev actuator_acq_dev; + struct cam_create_dev_hdl bridge_params; + + if (a_ctrl->bridge_intf.device_hdl != -1) { + CAM_ERR(CAM_ACTUATOR, "Device is already acquired"); + rc = -EINVAL; + goto release_mutex; + } + rc = copy_from_user(&actuator_acq_dev, + u64_to_user_ptr(cmd->handle), + sizeof(actuator_acq_dev)); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, "Failed Copying from user\n"); + goto release_mutex; + } + + bridge_params.session_hdl = actuator_acq_dev.session_handle; + bridge_params.ops = &a_ctrl->bridge_intf.ops; + bridge_params.v4l2_sub_dev_flag = 0; + bridge_params.media_entity_flag = 0; + bridge_params.priv = a_ctrl; + bridge_params.dev_id = CAM_ACTUATOR; + + actuator_acq_dev.device_handle = + cam_create_device_hdl(&bridge_params); + if (actuator_acq_dev.device_handle <= 0) { + rc = -EFAULT; + CAM_ERR(CAM_ACTUATOR, "Can not create device handle"); + goto release_mutex; + } + a_ctrl->bridge_intf.device_hdl = actuator_acq_dev.device_handle; + a_ctrl->bridge_intf.session_hdl = + actuator_acq_dev.session_handle; + + CAM_DBG(CAM_ACTUATOR, "Device Handle: %d", + actuator_acq_dev.device_handle); + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &actuator_acq_dev, + sizeof(struct cam_sensor_acquire_dev))) { + CAM_ERR(CAM_ACTUATOR, "Failed Copy to User"); + rc = -EFAULT; + goto release_mutex; + } + + a_ctrl->cam_act_state = CAM_ACTUATOR_ACQUIRE; + } + break; + case CAM_RELEASE_DEV: { + if (a_ctrl->cam_act_state == CAM_ACTUATOR_START) { + rc = -EINVAL; + CAM_WARN(CAM_ACTUATOR, + "Cant release actuator: in start state"); + goto release_mutex; + } + + if (a_ctrl->cam_act_state == CAM_ACTUATOR_CONFIG) { + rc = cam_actuator_power_down(a_ctrl); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Actuator Power down failed"); + goto release_mutex; + } + } + + if (a_ctrl->bridge_intf.device_hdl == -1) { + CAM_ERR(CAM_ACTUATOR, "link hdl: %d device hdl: %d", + a_ctrl->bridge_intf.device_hdl, + a_ctrl->bridge_intf.link_hdl); + rc = -EINVAL; + goto release_mutex; + } + + if (a_ctrl->bridge_intf.link_hdl != -1) { + CAM_ERR(CAM_ACTUATOR, + "Device [%d] still active on link 0x%x", + a_ctrl->cam_act_state, + a_ctrl->bridge_intf.link_hdl); + rc = -EAGAIN; + goto release_mutex; + } + + rc = cam_destroy_device_hdl(a_ctrl->bridge_intf.device_hdl); + if (rc < 0) + CAM_ERR(CAM_ACTUATOR, "destroying the device hdl"); + a_ctrl->bridge_intf.device_hdl = -1; + a_ctrl->bridge_intf.link_hdl = -1; + a_ctrl->bridge_intf.session_hdl = -1; + a_ctrl->cam_act_state = CAM_ACTUATOR_INIT; + a_ctrl->last_flush_req = 0; + kfree(power_info->power_setting); + kfree(power_info->power_down_setting); + power_info->power_setting = NULL; + power_info->power_down_setting = NULL; + power_info->power_down_setting_size = 0; + power_info->power_setting_size = 0; + } + break; + case CAM_QUERY_CAP: { + struct cam_actuator_query_cap actuator_cap = {0}; + + actuator_cap.slot_info = a_ctrl->soc_info.index; + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &actuator_cap, + sizeof(struct cam_actuator_query_cap))) { + CAM_ERR(CAM_ACTUATOR, "Failed Copy to User"); + rc = -EFAULT; + goto release_mutex; + } + } + break; + case CAM_START_DEV: { + if (a_ctrl->cam_act_state != CAM_ACTUATOR_CONFIG) { + rc = -EINVAL; + CAM_WARN(CAM_ACTUATOR, + "Not in right state to start : %d", + a_ctrl->cam_act_state); + goto release_mutex; + } + a_ctrl->cam_act_state = CAM_ACTUATOR_START; + a_ctrl->last_flush_req = 0; + } + break; + case CAM_STOP_DEV: { + struct i2c_settings_array *i2c_set = NULL; + int i; + + if (a_ctrl->cam_act_state != CAM_ACTUATOR_START) { + rc = -EINVAL; + CAM_WARN(CAM_ACTUATOR, + "Not in right state to stop : %d", + a_ctrl->cam_act_state); + goto release_mutex; + } + + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { + i2c_set = &(a_ctrl->i2c_data.per_frame[i]); + + if (i2c_set->is_settings_valid == 1) { + rc = delete_request(i2c_set); + if (rc < 0) + CAM_ERR(CAM_SENSOR, + "delete request: %lld rc: %d", + i2c_set->request_id, rc); + } + } + a_ctrl->last_flush_req = 0; + a_ctrl->cam_act_state = CAM_ACTUATOR_CONFIG; + } + break; + case CAM_CONFIG_DEV: { + a_ctrl->setting_apply_state = + ACT_APPLY_SETTINGS_LATER; + rc = cam_actuator_i2c_pkt_parse(a_ctrl, arg); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, "Failed in actuator Parsing"); + goto release_mutex; + } + + if (a_ctrl->setting_apply_state == + ACT_APPLY_SETTINGS_NOW) { + rc = cam_actuator_apply_settings(a_ctrl, + &a_ctrl->i2c_data.init_settings); + if ((rc == -EAGAIN) && + (a_ctrl->io_master_info.master_type == CCI_MASTER)) { + CAM_WARN(CAM_ACTUATOR, + "CCI HW is in resetting mode:: Reapplying Init settings"); + usleep_range(1000, 1010); + rc = cam_actuator_apply_settings(a_ctrl, + &a_ctrl->i2c_data.init_settings); + } + + if (rc < 0) + CAM_ERR(CAM_ACTUATOR, + "Failed to apply Init settings: rc = %d", + rc); + /* Delete the request even if the apply is failed */ + rc = delete_request(&a_ctrl->i2c_data.init_settings); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Failed in Deleting the Init Pkt: %d", + rc); + goto release_mutex; + } + } + } + break; + default: + CAM_ERR(CAM_ACTUATOR, "Invalid Opcode %d", cmd->op_code); + } + +release_mutex: + mutex_unlock(&(a_ctrl->actuator_mutex)); + + return rc; +} + +int32_t cam_actuator_flush_request(struct cam_req_mgr_flush_request *flush_req) +{ + int32_t rc = 0, i; + uint32_t cancel_req_id_found = 0; + struct cam_actuator_ctrl_t *a_ctrl = NULL; + struct i2c_settings_array *i2c_set = NULL; + + if (!flush_req) + return -EINVAL; + + a_ctrl = (struct cam_actuator_ctrl_t *) + cam_get_device_priv(flush_req->dev_hdl); + if (!a_ctrl) { + CAM_ERR(CAM_ACTUATOR, "Device data is NULL"); + return -EINVAL; + } + + if (a_ctrl->i2c_data.per_frame == NULL) { + CAM_ERR(CAM_ACTUATOR, "i2c frame data is NULL"); + return -EINVAL; + } + + mutex_lock(&(a_ctrl->actuator_mutex)); + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) { + a_ctrl->last_flush_req = flush_req->req_id; + CAM_DBG(CAM_ACTUATOR, "last reqest to flush is %lld", + flush_req->req_id); + } + + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { + i2c_set = &(a_ctrl->i2c_data.per_frame[i]); + + if ((flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ) + && (i2c_set->request_id != flush_req->req_id)) + continue; + + if (i2c_set->is_settings_valid == 1) { + rc = delete_request(i2c_set); + if (rc < 0) + CAM_ERR(CAM_ACTUATOR, + "delete request: %lld rc: %d", + i2c_set->request_id, rc); + + if (flush_req->type == + CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ) { + cancel_req_id_found = 1; + break; + } + } + } + + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ && + !cancel_req_id_found) + CAM_DBG(CAM_ACTUATOR, + "Flush request id:%lld not found in the pending list", + flush_req->req_id); + mutex_unlock(&(a_ctrl->actuator_mutex)); + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.h new file mode 100644 index 0000000000000000000000000000000000000000..e5636f26ce36ecd9ae88fdafa55a5c1643b8fe4b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_ACTUATOR_CORE_H_ +#define _CAM_ACTUATOR_CORE_H_ + +#include "cam_actuator_dev.h" + +/** + * @power_info: power setting info to control the power + * + * This API construct the default actuator power setting. + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int32_t cam_actuator_construct_default_power_setting( + struct cam_sensor_power_ctrl_t *power_info); + +/** + * @apply: Req mgr structure for applying request + * + * This API applies the request that is mentioned + */ +int32_t cam_actuator_apply_request(struct cam_req_mgr_apply_request *apply); + +/** + * @info: Sub device info to req mgr + * + * This API publish the subdevice info to req mgr + */ +int32_t cam_actuator_publish_dev_info(struct cam_req_mgr_device_info *info); + +/** + * @flush: Req mgr structure for flushing request + * + * This API flushes the request that is mentioned + */ +int cam_actuator_flush_request(struct cam_req_mgr_flush_request *flush); + + +/** + * @link: Link setup info + * + * This API establishes link actuator subdevice with req mgr + */ +int32_t cam_actuator_establish_link( + struct cam_req_mgr_core_dev_link_setup *link); + +/** + * @a_ctrl: Actuator ctrl structure + * @arg: Camera control command argument + * + * This API handles the camera control argument reached to actuator + */ +int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl, void *arg); + +/** + * @a_ctrl: Actuator ctrl structure + * + * This API handles the shutdown ioctl/close + */ +void cam_actuator_shutdown(struct cam_actuator_ctrl_t *a_ctrl); + +#endif /* _CAM_ACTUATOR_CORE_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..46bd99fc9e292c4ae288d3929109760e5c87c01e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.c @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#include "cam_actuator_dev.h" +#include "cam_req_mgr_dev.h" +#include "cam_actuator_soc.h" +#include "cam_actuator_core.h" +#include "cam_trace.h" + +static long cam_actuator_subdev_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + int rc = 0; + struct cam_actuator_ctrl_t *a_ctrl = + v4l2_get_subdevdata(sd); + + switch (cmd) { + case VIDIOC_CAM_CONTROL: + rc = cam_actuator_driver_cmd(a_ctrl, arg); + break; + default: + CAM_ERR(CAM_ACTUATOR, "Invalid ioctl cmd"); + rc = -EINVAL; + break; + } + return rc; +} + +#ifdef CONFIG_COMPAT +static long cam_actuator_init_subdev_do_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + struct cam_control cmd_data; + int32_t rc = 0; + + if (copy_from_user(&cmd_data, (void __user *)arg, + sizeof(cmd_data))) { + CAM_ERR(CAM_ACTUATOR, + "Failed to copy from user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + return -EFAULT; + } + + switch (cmd) { + case VIDIOC_CAM_CONTROL: + cmd = VIDIOC_CAM_CONTROL; + rc = cam_actuator_subdev_ioctl(sd, cmd, &cmd_data); + if (rc) { + CAM_ERR(CAM_ACTUATOR, + "Failed in actuator subdev handling rc: %d", + rc); + return rc; + } + break; + default: + CAM_ERR(CAM_ACTUATOR, "Invalid compat ioctl: %d", cmd); + rc = -EINVAL; + } + + if (!rc) { + if (copy_to_user((void __user *)arg, &cmd_data, + sizeof(cmd_data))) { + CAM_ERR(CAM_ACTUATOR, + "Failed to copy to user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + rc = -EFAULT; + } + } + return rc; +} +#endif + +static int cam_actuator_subdev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct cam_actuator_ctrl_t *a_ctrl = + v4l2_get_subdevdata(sd); + + if (!a_ctrl) { + CAM_ERR(CAM_ACTUATOR, "a_ctrl ptr is NULL"); + return -EINVAL; + } + + mutex_lock(&(a_ctrl->actuator_mutex)); + cam_actuator_shutdown(a_ctrl); + mutex_unlock(&(a_ctrl->actuator_mutex)); + + return 0; +} + +static struct v4l2_subdev_core_ops cam_actuator_subdev_core_ops = { + .ioctl = cam_actuator_subdev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = cam_actuator_init_subdev_do_ioctl, +#endif +}; + +static struct v4l2_subdev_ops cam_actuator_subdev_ops = { + .core = &cam_actuator_subdev_core_ops, +}; + +static const struct v4l2_subdev_internal_ops cam_actuator_internal_ops = { + .close = cam_actuator_subdev_close, +}; + +static int cam_actuator_init_subdev(struct cam_actuator_ctrl_t *a_ctrl) +{ + int rc = 0; + + a_ctrl->v4l2_dev_str.internal_ops = + &cam_actuator_internal_ops; + a_ctrl->v4l2_dev_str.ops = + &cam_actuator_subdev_ops; + strlcpy(a_ctrl->device_name, CAMX_ACTUATOR_DEV_NAME, + sizeof(a_ctrl->device_name)); + a_ctrl->v4l2_dev_str.name = + a_ctrl->device_name; + a_ctrl->v4l2_dev_str.sd_flags = + (V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS); + a_ctrl->v4l2_dev_str.ent_function = + CAM_ACTUATOR_DEVICE_TYPE; + a_ctrl->v4l2_dev_str.token = a_ctrl; + + rc = cam_register_subdev(&(a_ctrl->v4l2_dev_str)); + if (rc) + CAM_ERR(CAM_SENSOR, "Fail with cam_register_subdev rc: %d", rc); + + return rc; +} + +static int32_t cam_actuator_driver_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int32_t rc = 0; + int32_t i = 0; + struct cam_actuator_ctrl_t *a_ctrl; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_actuator_soc_private *soc_private = NULL; + + if (client == NULL || id == NULL) { + CAM_ERR(CAM_ACTUATOR, "Invalid Args client: %pK id: %pK", + client, id); + return -EINVAL; + } + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + CAM_ERR(CAM_ACTUATOR, "%s :: i2c_check_functionality failed", + client->name); + rc = -EFAULT; + return rc; + } + + /* Create sensor control structure */ + a_ctrl = kzalloc(sizeof(*a_ctrl), GFP_KERNEL); + if (!a_ctrl) + return -ENOMEM; + + i2c_set_clientdata(client, a_ctrl); + + soc_private = kzalloc(sizeof(struct cam_actuator_soc_private), + GFP_KERNEL); + if (!soc_private) { + rc = -ENOMEM; + goto free_ctrl; + } + a_ctrl->soc_info.soc_private = soc_private; + + a_ctrl->io_master_info.client = client; + soc_info = &a_ctrl->soc_info; + soc_info->dev = &client->dev; + soc_info->dev_name = client->name; + a_ctrl->io_master_info.master_type = I2C_MASTER; + + rc = cam_actuator_parse_dt(a_ctrl, &client->dev); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, "failed: cam_sensor_parse_dt rc %d", rc); + goto free_soc; + } + + rc = cam_actuator_init_subdev(a_ctrl); + if (rc) + goto free_soc; + + if (soc_private->i2c_info.slave_addr != 0) + a_ctrl->io_master_info.client->addr = + soc_private->i2c_info.slave_addr; + + a_ctrl->i2c_data.per_frame = + kzalloc(sizeof(struct i2c_settings_array) * + MAX_PER_FRAME_ARRAY, GFP_KERNEL); + if (a_ctrl->i2c_data.per_frame == NULL) { + rc = -ENOMEM; + goto unreg_subdev; + } + + INIT_LIST_HEAD(&(a_ctrl->i2c_data.init_settings.list_head)); + + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) + INIT_LIST_HEAD(&(a_ctrl->i2c_data.per_frame[i].list_head)); + + a_ctrl->bridge_intf.device_hdl = -1; + a_ctrl->bridge_intf.link_hdl = -1; + a_ctrl->bridge_intf.ops.get_dev_info = + cam_actuator_publish_dev_info; + a_ctrl->bridge_intf.ops.link_setup = + cam_actuator_establish_link; + a_ctrl->bridge_intf.ops.apply_req = + cam_actuator_apply_request; + a_ctrl->last_flush_req = 0; + a_ctrl->cam_act_state = CAM_ACTUATOR_INIT; + + return rc; + +unreg_subdev: + cam_unregister_subdev(&(a_ctrl->v4l2_dev_str)); +free_soc: + kfree(soc_private); +free_ctrl: + kfree(a_ctrl); + return rc; +} + +static int32_t cam_actuator_platform_remove(struct platform_device *pdev) +{ + int32_t rc = 0; + struct cam_actuator_ctrl_t *a_ctrl; + struct cam_actuator_soc_private *soc_private; + struct cam_sensor_power_ctrl_t *power_info; + + a_ctrl = platform_get_drvdata(pdev); + if (!a_ctrl) { + CAM_ERR(CAM_ACTUATOR, "Actuator device is NULL"); + return 0; + } + + CAM_INFO(CAM_ACTUATOR, "platform remove invoked"); + mutex_lock(&(a_ctrl->actuator_mutex)); + cam_actuator_shutdown(a_ctrl); + mutex_unlock(&(a_ctrl->actuator_mutex)); + cam_unregister_subdev(&(a_ctrl->v4l2_dev_str)); + + soc_private = + (struct cam_actuator_soc_private *)a_ctrl->soc_info.soc_private; + power_info = &soc_private->power_info; + + kfree(a_ctrl->io_master_info.cci_client); + a_ctrl->io_master_info.cci_client = NULL; + kfree(a_ctrl->soc_info.soc_private); + a_ctrl->soc_info.soc_private = NULL; + kfree(a_ctrl->i2c_data.per_frame); + a_ctrl->i2c_data.per_frame = NULL; + v4l2_set_subdevdata(&a_ctrl->v4l2_dev_str.sd, NULL); + platform_set_drvdata(pdev, NULL); + devm_kfree(&pdev->dev, a_ctrl); + + return rc; +} + +static int32_t cam_actuator_driver_i2c_remove(struct i2c_client *client) +{ + struct cam_actuator_ctrl_t *a_ctrl = + i2c_get_clientdata(client); + struct cam_actuator_soc_private *soc_private; + struct cam_sensor_power_ctrl_t *power_info; + + /* Handle I2C Devices */ + if (!a_ctrl) { + CAM_ERR(CAM_ACTUATOR, "Actuator device is NULL"); + return -EINVAL; + } + + CAM_INFO(CAM_ACTUATOR, "i2c remove invoked"); + mutex_lock(&(a_ctrl->actuator_mutex)); + cam_actuator_shutdown(a_ctrl); + mutex_unlock(&(a_ctrl->actuator_mutex)); + cam_unregister_subdev(&(a_ctrl->v4l2_dev_str)); + soc_private = + (struct cam_actuator_soc_private *)a_ctrl->soc_info.soc_private; + power_info = &soc_private->power_info; + + /*Free Allocated Mem */ + kfree(a_ctrl->i2c_data.per_frame); + a_ctrl->i2c_data.per_frame = NULL; + a_ctrl->soc_info.soc_private = NULL; + v4l2_set_subdevdata(&a_ctrl->v4l2_dev_str.sd, NULL); + kfree(a_ctrl); + + return 0; +} + +static const struct of_device_id cam_actuator_driver_dt_match[] = { + {.compatible = "qcom,actuator"}, + {} +}; + +static int32_t cam_actuator_driver_platform_probe( + struct platform_device *pdev) +{ + int32_t rc = 0; + int32_t i = 0; + struct cam_actuator_ctrl_t *a_ctrl = NULL; + struct cam_actuator_soc_private *soc_private = NULL; + + /* Create actuator control structure */ + a_ctrl = devm_kzalloc(&pdev->dev, + sizeof(struct cam_actuator_ctrl_t), GFP_KERNEL); + if (!a_ctrl) + return -ENOMEM; + + /*fill in platform device*/ + a_ctrl->v4l2_dev_str.pdev = pdev; + a_ctrl->soc_info.pdev = pdev; + a_ctrl->soc_info.dev = &pdev->dev; + a_ctrl->soc_info.dev_name = pdev->name; + a_ctrl->io_master_info.master_type = CCI_MASTER; + + a_ctrl->io_master_info.cci_client = kzalloc(sizeof( + struct cam_sensor_cci_client), GFP_KERNEL); + if (!(a_ctrl->io_master_info.cci_client)) { + rc = -ENOMEM; + goto free_ctrl; + } + + soc_private = kzalloc(sizeof(struct cam_actuator_soc_private), + GFP_KERNEL); + if (!soc_private) { + rc = -ENOMEM; + goto free_cci_client; + } + a_ctrl->soc_info.soc_private = soc_private; + soc_private->power_info.dev = &pdev->dev; + + a_ctrl->i2c_data.per_frame = + kzalloc(sizeof(struct i2c_settings_array) * + MAX_PER_FRAME_ARRAY, GFP_KERNEL); + if (a_ctrl->i2c_data.per_frame == NULL) { + rc = -ENOMEM; + goto free_soc; + } + + INIT_LIST_HEAD(&(a_ctrl->i2c_data.init_settings.list_head)); + + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) + INIT_LIST_HEAD(&(a_ctrl->i2c_data.per_frame[i].list_head)); + + rc = cam_actuator_parse_dt(a_ctrl, &(pdev->dev)); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, "Paring actuator dt failed rc %d", rc); + goto free_mem; + } + + /* Fill platform device id*/ + pdev->id = a_ctrl->soc_info.index; + + rc = cam_actuator_init_subdev(a_ctrl); + if (rc) + goto free_mem; + + a_ctrl->bridge_intf.device_hdl = -1; + a_ctrl->bridge_intf.link_hdl = -1; + a_ctrl->bridge_intf.ops.get_dev_info = + cam_actuator_publish_dev_info; + a_ctrl->bridge_intf.ops.link_setup = + cam_actuator_establish_link; + a_ctrl->bridge_intf.ops.apply_req = + cam_actuator_apply_request; + a_ctrl->bridge_intf.ops.flush_req = + cam_actuator_flush_request; + a_ctrl->last_flush_req = 0; + + platform_set_drvdata(pdev, a_ctrl); + a_ctrl->cam_act_state = CAM_ACTUATOR_INIT; + + return rc; + +free_mem: + kfree(a_ctrl->i2c_data.per_frame); +free_soc: + kfree(soc_private); +free_cci_client: + kfree(a_ctrl->io_master_info.cci_client); +free_ctrl: + devm_kfree(&pdev->dev, a_ctrl); + return rc; +} + +MODULE_DEVICE_TABLE(of, cam_actuator_driver_dt_match); + +static struct platform_driver cam_actuator_platform_driver = { + .probe = cam_actuator_driver_platform_probe, + .driver = { + .name = "qcom,actuator", + .owner = THIS_MODULE, + .of_match_table = cam_actuator_driver_dt_match, + .suppress_bind_attrs = true, + }, + .remove = cam_actuator_platform_remove, +}; + +static const struct i2c_device_id i2c_id[] = { + {ACTUATOR_DRIVER_I2C, (kernel_ulong_t)NULL}, + { } +}; + +static struct i2c_driver cam_actuator_driver_i2c = { + .id_table = i2c_id, + .probe = cam_actuator_driver_i2c_probe, + .remove = cam_actuator_driver_i2c_remove, + .driver = { + .name = ACTUATOR_DRIVER_I2C, + }, +}; + +static int __init cam_actuator_driver_init(void) +{ + int32_t rc = 0; + + rc = platform_driver_register(&cam_actuator_platform_driver); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "platform_driver_register failed rc = %d", rc); + return rc; + } + rc = i2c_add_driver(&cam_actuator_driver_i2c); + if (rc) + CAM_ERR(CAM_ACTUATOR, "i2c_add_driver failed rc = %d", rc); + + return rc; +} + +static void __exit cam_actuator_driver_exit(void) +{ + platform_driver_unregister(&cam_actuator_platform_driver); + i2c_del_driver(&cam_actuator_driver_i2c); +} + +module_init(cam_actuator_driver_init); +module_exit(cam_actuator_driver_exit); +MODULE_DESCRIPTION("cam_actuator_driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..e4bfaed4414ff2111fae6ca372450fae24451052 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + + +#ifndef _CAM_ACTUATOR_DEV_H_ +#define _CAM_ACTUATOR_DEV_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_sensor_util.h" +#include "cam_soc_util.h" +#include "cam_debug_util.h" +#include "cam_context.h" + +#define NUM_MASTERS 2 +#define NUM_QUEUES 2 + +#define ACTUATOR_DRIVER_I2C "i2c_actuator" +#define CAMX_ACTUATOR_DEV_NAME "cam-actuator-driver" + +#define MSM_ACTUATOR_MAX_VREGS (10) +#define ACTUATOR_MAX_POLL_COUNT 10 + +enum cam_actuator_apply_state_t { + ACT_APPLY_SETTINGS_NOW, + ACT_APPLY_SETTINGS_LATER, +}; + +enum cam_actuator_state { + CAM_ACTUATOR_INIT, + CAM_ACTUATOR_ACQUIRE, + CAM_ACTUATOR_CONFIG, + CAM_ACTUATOR_START, +}; + +/** + * struct cam_actuator_i2c_info_t - I2C info + * @slave_addr : slave address + * @i2c_freq_mode : i2c frequency mode + */ +struct cam_actuator_i2c_info_t { + uint16_t slave_addr; + uint8_t i2c_freq_mode; +}; + +struct cam_actuator_soc_private { + struct cam_actuator_i2c_info_t i2c_info; + struct cam_sensor_power_ctrl_t power_info; +}; + +/** + * struct intf_params + * @device_hdl: Device Handle + * @session_hdl: Session Handle + * @ops: KMD operations + * @crm_cb: Callback API pointers + */ +struct intf_params { + int32_t device_hdl; + int32_t session_hdl; + int32_t link_hdl; + struct cam_req_mgr_kmd_ops ops; + struct cam_req_mgr_crm_cb *crm_cb; +}; + +/** + * struct cam_actuator_ctrl_t + * @device_name: Device name + * @i2c_driver: I2C device info + * @pdev: Platform device + * @cci_i2c_master: I2C structure + * @io_master_info: Information about the communication master + * @actuator_mutex: Actuator mutex + * @act_apply_state: Actuator settings aRegulator config + * @id: Cell Index + * @res_apply_state: Actuator settings apply state + * @cam_act_state: Actuator state + * @gconf: GPIO config + * @pinctrl_info: Pinctrl information + * @v4l2_dev_str: V4L2 device structure + * @i2c_data: I2C register settings structure + * @act_info: Sensor query cap structure + * @of_node: Node ptr + * @last_flush_req: Last request to flush + */ +struct cam_actuator_ctrl_t { + char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH]; + struct i2c_driver *i2c_driver; + enum cci_i2c_master_t cci_i2c_master; + enum cci_device_num cci_num; + struct camera_io_master io_master_info; + struct cam_hw_soc_info soc_info; + struct mutex actuator_mutex; + uint32_t id; + enum cam_actuator_apply_state_t setting_apply_state; + enum cam_actuator_state cam_act_state; + uint8_t cam_pinctrl_status; + struct cam_subdev v4l2_dev_str; + struct i2c_data_settings i2c_data; + struct cam_actuator_query_cap act_info; + struct intf_params bridge_intf; + uint32_t last_flush_req; +}; + +#endif /* _CAM_ACTUATOR_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_soc.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..3ee629e3f1ca835f42632fbe3f4a1b697962b4e2 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_soc.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "cam_actuator_soc.h" +#include "cam_soc_util.h" + +int32_t cam_actuator_parse_dt(struct cam_actuator_ctrl_t *a_ctrl, + struct device *dev) +{ + int32_t rc = 0; + struct cam_hw_soc_info *soc_info = &a_ctrl->soc_info; + struct cam_actuator_soc_private *soc_private = + (struct cam_actuator_soc_private *)a_ctrl->soc_info.soc_private; + struct cam_sensor_power_ctrl_t *power_info = &soc_private->power_info; + struct device_node *of_node = NULL; + struct device_node *of_parent = NULL; + + /* Initialize mutex */ + mutex_init(&(a_ctrl->actuator_mutex)); + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, "parsing common soc dt(rc %d)", rc); + return rc; + } + + of_node = soc_info->dev->of_node; + + if (a_ctrl->io_master_info.master_type == CCI_MASTER) { + rc = of_property_read_u32(of_node, "cci-master", + &(a_ctrl->cci_i2c_master)); + CAM_DBG(CAM_ACTUATOR, "cci-master %d, rc %d", + a_ctrl->cci_i2c_master, rc); + if ((rc < 0) || (a_ctrl->cci_i2c_master >= MASTER_MAX)) { + CAM_ERR(CAM_ACTUATOR, + "Wrong info: rc: %d, dt CCI master:%d", + rc, a_ctrl->cci_i2c_master); + rc = -EFAULT; + return rc; + } + + of_parent = of_get_parent(of_node); + if (of_property_read_u32(of_parent, "cell-index", + &a_ctrl->cci_num) < 0) + /* Set default master 0 */ + a_ctrl->cci_num = CCI_DEVICE_0; + a_ctrl->io_master_info.cci_client->cci_device = a_ctrl->cci_num; + CAM_DBG(CAM_ACTUATOR, "cci-device %d", a_ctrl->cci_num); + } + + if (!soc_info->gpio_data) { + CAM_INFO(CAM_ACTUATOR, "No GPIO found"); + rc = 0; + return rc; + } + + if (!soc_info->gpio_data->cam_gpio_common_tbl_size) { + CAM_INFO(CAM_ACTUATOR, "No GPIO found"); + return -EINVAL; + } + + rc = cam_sensor_util_init_gpio_pin_tbl(soc_info, + &power_info->gpio_num_info); + if ((rc < 0) || (!power_info->gpio_num_info)) { + CAM_ERR(CAM_ACTUATOR, "No/Error Actuator GPIOs"); + return -EINVAL; + } + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_soc.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..65b4fb99fa0337350c62ad905833fde34b5e1976 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/cam_actuator_soc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_ACTUATOR_SOC_H_ +#define _CAM_ACTUATOR_SOC_H_ + +#include "cam_actuator_dev.h" + +/** + * @a_ctrl: Actuator ctrl structure + * + * This API parses actuator device tree + */ +int cam_actuator_parse_dt(struct cam_actuator_ctrl_t *a_ctrl, + struct device *dev); + +#endif /* _CAM_ACTUATOR_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..df2920a5cccfc6fcac2358b41d0913298e5573cc --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree) + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_cci_dev.o cam_cci_core.o cam_cci_soc.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_core.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_core.c new file mode 100644 index 0000000000000000000000000000000000000000..c34e7ccebedcead1698d2b57c0fb02cf090e0c32 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_core.c @@ -0,0 +1,1828 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_cci_core.h" +#include "cam_cci_dev.h" +#include "cam_req_mgr_workq.h" + +static int32_t cam_cci_convert_type_to_num_bytes( + enum camera_sensor_i2c_type type) +{ + int32_t num_bytes; + + switch (type) { + case CAMERA_SENSOR_I2C_TYPE_BYTE: + num_bytes = 1; + break; + case CAMERA_SENSOR_I2C_TYPE_WORD: + num_bytes = 2; + break; + case CAMERA_SENSOR_I2C_TYPE_3B: + num_bytes = 3; + break; + case CAMERA_SENSOR_I2C_TYPE_DWORD: + num_bytes = 4; + break; + default: + CAM_ERR(CAM_CCI, "failed: %d", type); + num_bytes = 0; + break; + } + return num_bytes; +} + +static void cam_cci_flush_queue(struct cci_device *cci_dev, + enum cci_i2c_master_t master) +{ + int32_t rc = 0; + struct cam_hw_soc_info *soc_info = + &cci_dev->soc_info; + void __iomem *base = soc_info->reg_map[0].mem_base; + + cam_io_w_mb(1 << master, base + CCI_HALT_REQ_ADDR); + rc = wait_for_completion_timeout( + &cci_dev->cci_master_info[master].reset_complete, CCI_TIMEOUT); + if (rc < 0) { + CAM_ERR(CAM_CCI, "wait failed"); + } else if (rc == 0) { + CAM_ERR(CAM_CCI, "wait timeout"); + + /* Set reset pending flag to true */ + cci_dev->cci_master_info[master].reset_pending = true; + + /* Set proper mask to RESET CMD address based on MASTER */ + if (master == MASTER_0) + cam_io_w_mb(CCI_M0_RESET_RMSK, + base + CCI_RESET_CMD_ADDR); + else + cam_io_w_mb(CCI_M1_RESET_RMSK, + base + CCI_RESET_CMD_ADDR); + + /* wait for reset done irq */ + rc = wait_for_completion_timeout( + &cci_dev->cci_master_info[master].reset_complete, + CCI_TIMEOUT); + if (rc <= 0) + CAM_ERR(CAM_CCI, "wait failed %d", rc); + } +} + +static int32_t cam_cci_validate_queue(struct cci_device *cci_dev, + uint32_t len, + enum cci_i2c_master_t master, + enum cci_i2c_queue_t queue) +{ + int32_t rc = 0; + uint32_t read_val = 0; + uint32_t reg_offset = master * 0x200 + queue * 0x100; + struct cam_hw_soc_info *soc_info = + &cci_dev->soc_info; + void __iomem *base = soc_info->reg_map[0].mem_base; + unsigned long flags; + + read_val = cam_io_r_mb(base + + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset); + CAM_DBG(CAM_CCI, "CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR %d len %d max %d", + read_val, len, + cci_dev->cci_i2c_queue_info[master][queue].max_queue_size); + if ((read_val + len + 1) > + cci_dev->cci_i2c_queue_info[master][queue].max_queue_size) { + uint32_t reg_val = 0; + uint32_t report_val = CCI_I2C_REPORT_CMD | (1 << 8); + + CAM_DBG(CAM_CCI, "CCI_I2C_REPORT_CMD"); + cam_io_w_mb(report_val, + base + CCI_I2C_M0_Q0_LOAD_DATA_ADDR + + reg_offset); + read_val++; + CAM_DBG(CAM_CCI, + "CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR %d, queue: %d", + read_val, queue); + cam_io_w_mb(read_val, base + + CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + reg_offset); + reg_val = 1 << ((master * 2) + queue); + CAM_DBG(CAM_CCI, "CCI_QUEUE_START_ADDR"); + spin_lock_irqsave( + &cci_dev->cci_master_info[master].lock_q[queue], flags); + atomic_set( + &cci_dev->cci_master_info[master].done_pending[queue], + 1); + cam_io_w_mb(reg_val, base + + CCI_QUEUE_START_ADDR); + CAM_DBG(CAM_CCI, "wait_for_completion_timeout"); + atomic_set(&cci_dev->cci_master_info[master].q_free[queue], 1); + spin_unlock_irqrestore( + &cci_dev->cci_master_info[master].lock_q[queue], flags); + rc = wait_for_completion_timeout( + &cci_dev->cci_master_info[master].report_q[queue], + CCI_TIMEOUT); + if (rc <= 0) { + CAM_ERR(CAM_CCI, "Wait_for_completion_timeout: rc: %d", + rc); + if (rc == 0) + rc = -ETIMEDOUT; + cam_cci_flush_queue(cci_dev, master); + return rc; + } + rc = cci_dev->cci_master_info[master].status; + if (rc < 0) + CAM_ERR(CAM_CCI, "Failed rc %d", rc); + } + + return rc; +} + +static int32_t cam_cci_write_i2c_queue(struct cci_device *cci_dev, + uint32_t val, + enum cci_i2c_master_t master, + enum cci_i2c_queue_t queue) +{ + int32_t rc = 0; + uint32_t reg_offset = master * 0x200 + queue * 0x100; + struct cam_hw_soc_info *soc_info = + &cci_dev->soc_info; + void __iomem *base = soc_info->reg_map[0].mem_base; + + if (!cci_dev) { + CAM_ERR(CAM_CCI, "Failed"); + return -EINVAL; + } + + rc = cam_cci_validate_queue(cci_dev, 1, master, queue); + if (rc < 0) { + CAM_ERR(CAM_CCI, "Failed %d", rc); + return rc; + } + CAM_DBG(CAM_CCI, "CCI_I2C_M0_Q0_LOAD_DATA_ADDR:val 0x%x:0x%x", + CCI_I2C_M0_Q0_LOAD_DATA_ADDR + + reg_offset, val); + cam_io_w_mb(val, base + CCI_I2C_M0_Q0_LOAD_DATA_ADDR + + reg_offset); + return rc; +} + +static int32_t cam_cci_lock_queue(struct cci_device *cci_dev, + enum cci_i2c_master_t master, + enum cci_i2c_queue_t queue, uint32_t en) +{ + uint32_t val; + + if (queue != PRIORITY_QUEUE) + return 0; + + val = en ? CCI_I2C_LOCK_CMD : CCI_I2C_UNLOCK_CMD; + return cam_cci_write_i2c_queue(cci_dev, val, master, queue); +} + + +void cam_cci_dump_registers(struct cci_device *cci_dev, + enum cci_i2c_master_t master, enum cci_i2c_queue_t queue) +{ + uint32_t dump_en = 0; + uint32_t read_val = 0; + uint32_t i = 0; + uint32_t reg_offset = 0; + uint32_t read_buf_level = 0; + uint32_t read_data_reg_offset = 0x0; + void __iomem *base = cci_dev->soc_info.reg_map[0].mem_base; + + dump_en = cci_dev->dump_en; + if (!(dump_en & CAM_CCI_NACK_DUMP_EN) && + !(dump_en & CAM_CCI_TIMEOUT_DUMP_EN)) { + CAM_DBG(CAM_CCI, + "Nack and Timeout dump is not enabled"); + return; + } + + /* CCI Top Registers */ + CAM_INFO(CAM_CCI, "****CCI TOP Registers ****"); + for (i = 0; i < DEBUG_TOP_REG_COUNT; i++) { + reg_offset = DEBUG_TOP_REG_START + i * 4; + read_val = cam_io_r_mb(base + reg_offset); + CAM_INFO(CAM_CCI, "offset = 0x%X value = 0x%X", + reg_offset, read_val); + } + + /* CCI Master registers */ + CAM_INFO(CAM_CCI, "****CCI MASTER %d Registers ****", + master); + read_buf_level = cam_io_r_mb(base + + CCI_I2C_M0_READ_BUF_LEVEL_ADDR + master * 0x100); + read_data_reg_offset = CCI_I2C_M0_READ_DATA_ADDR + master * 0x100; + for (i = 0; i < DEBUG_MASTER_REG_COUNT; i++) { + reg_offset = DEBUG_MASTER_REG_START + master*0x100 + i * 4; + /* + * Don't read from READ_DATA_ADDR if + * i2c read fifo is empty, this may lead to + * read underflow status bits getting set + */ + if ((read_buf_level == 0) && + (reg_offset == read_data_reg_offset)) + continue; + read_val = cam_io_r_mb(base + reg_offset); + CAM_INFO(CAM_CCI, "offset = 0x%X value = 0x%X", + reg_offset, read_val); + } + + /* CCI Master Queue registers */ + CAM_INFO(CAM_CCI, " **** CCI MASTER%d QUEUE%d Registers ****", + master, queue); + for (i = 0; i < DEBUG_MASTER_QUEUE_REG_COUNT; i++) { + reg_offset = DEBUG_MASTER_QUEUE_REG_START + master*0x200 + + queue*0x100 + i * 4; + read_val = cam_io_r_mb(base + reg_offset); + CAM_INFO(CAM_CCI, "offset = 0x%X value = 0x%X", + reg_offset, read_val); + } + + /* CCI Interrupt registers */ + CAM_INFO(CAM_CCI, " ****CCI Interrupt Registers ****"); + for (i = 0; i < DEBUG_INTR_REG_COUNT; i++) { + reg_offset = DEBUG_INTR_REG_START + i * 4; + read_val = cam_io_r_mb(base + reg_offset); + CAM_INFO(CAM_CCI, "offset = 0x%X value = 0x%X", + reg_offset, read_val); + } +} +EXPORT_SYMBOL(cam_cci_dump_registers); + +static uint32_t cam_cci_wait(struct cci_device *cci_dev, + enum cci_i2c_master_t master, + enum cci_i2c_queue_t queue) +{ + int32_t rc = 0; + + if (!cci_dev) { + CAM_ERR(CAM_CCI, "failed"); + return -EINVAL; + } + + rc = wait_for_completion_timeout( + &cci_dev->cci_master_info[master].report_q[queue], CCI_TIMEOUT); + CAM_DBG(CAM_CCI, "wait DONE_for_completion_timeout"); + + if (rc <= 0) { + cam_cci_dump_registers(cci_dev, master, queue); + + CAM_ERR(CAM_CCI, "wait for queue: %d", queue); + if (rc == 0) + rc = -ETIMEDOUT; + cam_cci_flush_queue(cci_dev, master); + return rc; + } + rc = cci_dev->cci_master_info[master].status; + if (rc < 0) { + CAM_ERR(CAM_CCI, "failed rc %d", rc); + return rc; + } + + return 0; +} + +static void cam_cci_load_report_cmd(struct cci_device *cci_dev, + enum cci_i2c_master_t master, + enum cci_i2c_queue_t queue) +{ + struct cam_hw_soc_info *soc_info = + &cci_dev->soc_info; + void __iomem *base = soc_info->reg_map[0].mem_base; + + uint32_t reg_offset = master * 0x200 + queue * 0x100; + uint32_t read_val = cam_io_r_mb(base + + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset); + uint32_t report_val = CCI_I2C_REPORT_CMD | (1 << 8); + + CAM_DBG(CAM_CCI, "CCI_I2C_REPORT_CMD curr_w_cnt: %d", read_val); + cam_io_w_mb(report_val, + base + CCI_I2C_M0_Q0_LOAD_DATA_ADDR + + reg_offset); + read_val++; + + CAM_DBG(CAM_CCI, "CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR %d", read_val); + cam_io_w_mb(read_val, base + + CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + reg_offset); +} + +static int32_t cam_cci_wait_report_cmd(struct cci_device *cci_dev, + enum cci_i2c_master_t master, + enum cci_i2c_queue_t queue) +{ + unsigned long flags; + struct cam_hw_soc_info *soc_info = + &cci_dev->soc_info; + void __iomem *base = soc_info->reg_map[0].mem_base; + + uint32_t reg_val = 1 << ((master * 2) + queue); + + cam_cci_load_report_cmd(cci_dev, master, queue); + spin_lock_irqsave( + &cci_dev->cci_master_info[master].lock_q[queue], flags); + atomic_set(&cci_dev->cci_master_info[master].q_free[queue], 1); + atomic_set(&cci_dev->cci_master_info[master].done_pending[queue], 1); + spin_unlock_irqrestore( + &cci_dev->cci_master_info[master].lock_q[queue], flags); + cam_io_w_mb(reg_val, base + + CCI_QUEUE_START_ADDR); + + return cam_cci_wait(cci_dev, master, queue); +} + +static int32_t cam_cci_transfer_end(struct cci_device *cci_dev, + enum cci_i2c_master_t master, + enum cci_i2c_queue_t queue) +{ + int32_t rc = 0; + unsigned long flags; + + spin_lock_irqsave( + &cci_dev->cci_master_info[master].lock_q[queue], flags); + if (atomic_read(&cci_dev->cci_master_info[master].q_free[queue]) == 0) { + spin_unlock_irqrestore( + &cci_dev->cci_master_info[master].lock_q[queue], flags); + rc = cam_cci_lock_queue(cci_dev, master, queue, 0); + if (rc < 0) { + CAM_ERR(CAM_CCI, "failed rc: %d", rc); + return rc; + } + rc = cam_cci_wait_report_cmd(cci_dev, master, queue); + if (rc < 0) { + CAM_ERR(CAM_CCI, "failed rc %d", rc); + return rc; + } + } else { + atomic_set( + &cci_dev->cci_master_info[master].done_pending[queue], + 1); + spin_unlock_irqrestore( + &cci_dev->cci_master_info[master].lock_q[queue], flags); + rc = cam_cci_wait(cci_dev, master, queue); + if (rc < 0) { + CAM_ERR(CAM_CCI, "failed rc %d", rc); + return rc; + } + rc = cam_cci_lock_queue(cci_dev, master, queue, 0); + if (rc < 0) { + CAM_ERR(CAM_CCI, "failed rc %d", rc); + return rc; + } + rc = cam_cci_wait_report_cmd(cci_dev, master, queue); + if (rc < 0) { + CAM_ERR(CAM_CCI, "Failed rc %d", rc); + return rc; + } + } + + return rc; +} + +static int32_t cam_cci_get_queue_free_size(struct cci_device *cci_dev, + enum cci_i2c_master_t master, + enum cci_i2c_queue_t queue) +{ + uint32_t read_val = 0; + uint32_t reg_offset = master * 0x200 + queue * 0x100; + struct cam_hw_soc_info *soc_info = + &cci_dev->soc_info; + void __iomem *base = soc_info->reg_map[0].mem_base; + + read_val = cam_io_r_mb(base + + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset); + CAM_DBG(CAM_CCI, "CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR %d max %d", read_val, + cci_dev->cci_i2c_queue_info[master][queue].max_queue_size); + return ((cci_dev->cci_i2c_queue_info[master][queue].max_queue_size) - + read_val); +} + +static void cam_cci_process_half_q(struct cci_device *cci_dev, + enum cci_i2c_master_t master, + enum cci_i2c_queue_t queue) +{ + unsigned long flags; + struct cam_hw_soc_info *soc_info = + &cci_dev->soc_info; + void __iomem *base = soc_info->reg_map[0].mem_base; + uint32_t reg_val = 1 << ((master * 2) + queue); + + spin_lock_irqsave(&cci_dev->cci_master_info[master].lock_q[queue], + flags); + if (atomic_read(&cci_dev->cci_master_info[master].q_free[queue]) == 0) { + cam_cci_load_report_cmd(cci_dev, master, queue); + atomic_set(&cci_dev->cci_master_info[master].q_free[queue], 1); + cam_io_w_mb(reg_val, base + + CCI_QUEUE_START_ADDR); + } + spin_unlock_irqrestore(&cci_dev->cci_master_info[master].lock_q[queue], + flags); +} + +static int32_t cam_cci_process_full_q(struct cci_device *cci_dev, + enum cci_i2c_master_t master, + enum cci_i2c_queue_t queue) +{ + int32_t rc = 0; + unsigned long flags; + + + spin_lock_irqsave(&cci_dev->cci_master_info[master].lock_q[queue], + flags); + if (atomic_read(&cci_dev->cci_master_info[master].q_free[queue]) == 1) { + atomic_set( + &cci_dev->cci_master_info[master].done_pending[queue], + 1); + spin_unlock_irqrestore( + &cci_dev->cci_master_info[master].lock_q[queue], flags); + rc = cam_cci_wait(cci_dev, master, queue); + if (rc < 0) { + CAM_ERR(CAM_CCI, "failed rc %d", rc); + return rc; + } + } else { + spin_unlock_irqrestore( + &cci_dev->cci_master_info[master].lock_q[queue], flags); + rc = cam_cci_wait_report_cmd(cci_dev, master, queue); + if (rc < 0) { + CAM_ERR(CAM_CCI, "failed rc %d", rc); + return rc; + } + } + + return rc; +} + +static int32_t cam_cci_calc_cmd_len(struct cci_device *cci_dev, + struct cam_cci_ctrl *c_ctrl, uint32_t cmd_size, + struct cam_sensor_i2c_reg_array *i2c_cmd, uint32_t *pack) +{ + uint8_t i; + uint32_t len = 0; + uint8_t data_len = 0, addr_len = 0; + uint8_t pack_max_len; + struct cam_sensor_i2c_reg_setting *msg; + struct cam_sensor_i2c_reg_array *cmd = i2c_cmd; + uint32_t size = cmd_size; + + if (!cci_dev || !c_ctrl) { + CAM_ERR(CAM_CCI, "failed"); + return -EINVAL; + } + + msg = &c_ctrl->cfg.cci_i2c_write_cfg; + *pack = 0; + + if (c_ctrl->cmd == MSM_CCI_I2C_WRITE_SEQ || + c_ctrl->cmd == MSM_CCI_I2C_WRITE_BURST) { + addr_len = cam_cci_convert_type_to_num_bytes(msg->addr_type); + len = (size + addr_len) <= (cci_dev->payload_size) ? + (size + addr_len):cci_dev->payload_size; + } else { + addr_len = cam_cci_convert_type_to_num_bytes(msg->addr_type); + data_len = cam_cci_convert_type_to_num_bytes(msg->data_type); + len = data_len + addr_len; + pack_max_len = size < (cci_dev->payload_size-len) ? + size : (cci_dev->payload_size-len); + for (i = 0; i < pack_max_len;) { + if (cmd->delay || ((cmd - i2c_cmd) >= (cmd_size - 1))) + break; + if (cmd->reg_addr + 1 == + (cmd+1)->reg_addr) { + len += data_len; + if (len > cci_dev->payload_size) { + len = len - data_len; + break; + } + (*pack)++; + } else { + break; + } + i += data_len; + cmd++; + } + } + + if (len > cci_dev->payload_size) { + CAM_ERR(CAM_CCI, "Len error: %d", len); + return -EINVAL; + } + + len += 1; /*add i2c WR command*/ + len = len/4 + 1; + + return len; +} + +static uint32_t cam_cci_cycles_per_ms(unsigned long clk) +{ + uint32_t cycles_per_us; + + if (clk) { + cycles_per_us = ((clk/1000)*256)/1000; + } else { + CAM_ERR(CAM_CCI, "failed: Can use default: %d", + CYCLES_PER_MICRO_SEC_DEFAULT); + cycles_per_us = CYCLES_PER_MICRO_SEC_DEFAULT; + } + + return cycles_per_us; +} + +void cam_cci_get_clk_rates(struct cci_device *cci_dev, + struct cam_cci_ctrl *c_ctrl) + +{ + int32_t src_clk_idx, j; + uint32_t cci_clk_src; + unsigned long clk; + struct cam_cci_clk_params_t *clk_params = NULL; + + enum i2c_freq_mode i2c_freq_mode = c_ctrl->cci_info->i2c_freq_mode; + struct cam_hw_soc_info *soc_info = &cci_dev->soc_info; + + if (i2c_freq_mode >= I2C_MAX_MODES || + i2c_freq_mode < I2C_STANDARD_MODE) { + CAM_ERR(CAM_CCI, "Invalid frequency mode: %d", + (int32_t)i2c_freq_mode); + cci_dev->clk_level_index = -1; + return; + } + + clk_params = &cci_dev->cci_clk_params[i2c_freq_mode]; + cci_clk_src = clk_params->cci_clk_src; + + src_clk_idx = soc_info->src_clk_idx; + + if (src_clk_idx < 0) { + cci_dev->cycles_per_us = CYCLES_PER_MICRO_SEC_DEFAULT; + cci_dev->clk_level_index = 0; + return; + } + + if (cci_clk_src == 0) { + clk = soc_info->clk_rate[0][src_clk_idx]; + cci_dev->cycles_per_us = cam_cci_cycles_per_ms(clk); + cci_dev->clk_level_index = 0; + return; + } + + for (j = 0; j < CAM_MAX_VOTE; j++) { + clk = soc_info->clk_rate[j][src_clk_idx]; + if (clk == cci_clk_src) { + cci_dev->cycles_per_us = cam_cci_cycles_per_ms(clk); + cci_dev->clk_level_index = j; + return; + } + } +} + +static int32_t cam_cci_set_clk_param(struct cci_device *cci_dev, + struct cam_cci_ctrl *c_ctrl) +{ + struct cam_cci_clk_params_t *clk_params = NULL; + enum cci_i2c_master_t master = c_ctrl->cci_info->cci_i2c_master; + enum i2c_freq_mode i2c_freq_mode = c_ctrl->cci_info->i2c_freq_mode; + struct cam_hw_soc_info *soc_info = + &cci_dev->soc_info; + void __iomem *base = soc_info->reg_map[0].mem_base; + + if ((i2c_freq_mode >= I2C_MAX_MODES) || (i2c_freq_mode < 0)) { + CAM_ERR(CAM_CCI, "invalid i2c_freq_mode = %d", i2c_freq_mode); + return -EINVAL; + } + + clk_params = &cci_dev->cci_clk_params[i2c_freq_mode]; + + if (cci_dev->i2c_freq_mode[master] == i2c_freq_mode) + return 0; + if (master == MASTER_0) { + cam_io_w_mb(clk_params->hw_thigh << 16 | + clk_params->hw_tlow, + base + CCI_I2C_M0_SCL_CTL_ADDR); + cam_io_w_mb(clk_params->hw_tsu_sto << 16 | + clk_params->hw_tsu_sta, + base + CCI_I2C_M0_SDA_CTL_0_ADDR); + cam_io_w_mb(clk_params->hw_thd_dat << 16 | + clk_params->hw_thd_sta, + base + CCI_I2C_M0_SDA_CTL_1_ADDR); + cam_io_w_mb(clk_params->hw_tbuf, + base + CCI_I2C_M0_SDA_CTL_2_ADDR); + cam_io_w_mb(clk_params->hw_scl_stretch_en << 8 | + clk_params->hw_trdhld << 4 | clk_params->hw_tsp, + base + CCI_I2C_M0_MISC_CTL_ADDR); + } else if (master == MASTER_1) { + cam_io_w_mb(clk_params->hw_thigh << 16 | + clk_params->hw_tlow, + base + CCI_I2C_M1_SCL_CTL_ADDR); + cam_io_w_mb(clk_params->hw_tsu_sto << 16 | + clk_params->hw_tsu_sta, + base + CCI_I2C_M1_SDA_CTL_0_ADDR); + cam_io_w_mb(clk_params->hw_thd_dat << 16 | + clk_params->hw_thd_sta, + base + CCI_I2C_M1_SDA_CTL_1_ADDR); + cam_io_w_mb(clk_params->hw_tbuf, + base + CCI_I2C_M1_SDA_CTL_2_ADDR); + cam_io_w_mb(clk_params->hw_scl_stretch_en << 8 | + clk_params->hw_trdhld << 4 | clk_params->hw_tsp, + base + CCI_I2C_M1_MISC_CTL_ADDR); + } + cci_dev->i2c_freq_mode[master] = i2c_freq_mode; + + return 0; +} + +static int32_t cam_cci_data_queue(struct cci_device *cci_dev, + struct cam_cci_ctrl *c_ctrl, enum cci_i2c_queue_t queue, + enum cci_i2c_sync sync_en) +{ + uint16_t i = 0, j = 0, k = 0, h = 0, len = 0; + int32_t rc = 0, free_size = 0, en_seq_write = 0; + uint8_t data[12]; + struct cam_sensor_i2c_reg_setting *i2c_msg = + &c_ctrl->cfg.cci_i2c_write_cfg; + struct cam_sensor_i2c_reg_array *i2c_cmd = i2c_msg->reg_setting; + enum cci_i2c_master_t master = c_ctrl->cci_info->cci_i2c_master; + uint16_t reg_addr = 0, cmd_size = i2c_msg->size; + uint32_t read_val = 0, reg_offset, val, delay = 0; + uint32_t max_queue_size, queue_size = 0, cmd = 0; + struct cam_hw_soc_info *soc_info = + &cci_dev->soc_info; + void __iomem *base = soc_info->reg_map[0].mem_base; + unsigned long flags; + + if (i2c_cmd == NULL) { + CAM_ERR(CAM_CCI, "Failed: i2c cmd is NULL"); + return -EINVAL; + } + + if ((!cmd_size) || (cmd_size > CCI_I2C_MAX_WRITE)) { + CAM_ERR(CAM_CCI, "failed: invalid cmd_size %d", + cmd_size); + return -EINVAL; + } + + CAM_DBG(CAM_CCI, "addr type %d data type %d cmd_size %d", + i2c_msg->addr_type, i2c_msg->data_type, cmd_size); + + if (i2c_msg->addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX) { + CAM_ERR(CAM_CCI, "failed: invalid addr_type 0x%X", + i2c_msg->addr_type); + return -EINVAL; + } + if (i2c_msg->data_type >= CAMERA_SENSOR_I2C_TYPE_MAX) { + CAM_ERR(CAM_CCI, "failed: invalid data_type 0x%X", + i2c_msg->data_type); + return -EINVAL; + } + reg_offset = master * 0x200 + queue * 0x100; + + cam_io_w_mb(cci_dev->cci_wait_sync_cfg.cid, + base + CCI_SET_CID_SYNC_TIMER_ADDR + + cci_dev->cci_wait_sync_cfg.csid * + CCI_SET_CID_SYNC_TIMER_OFFSET); + + val = CCI_I2C_SET_PARAM_CMD | c_ctrl->cci_info->sid << 4 | + c_ctrl->cci_info->retries << 16 | + c_ctrl->cci_info->id_map << 18; + + CAM_DBG(CAM_CCI, "CCI_I2C_M0_Q0_LOAD_DATA_ADDR:val 0x%x:0x%x", + CCI_I2C_M0_Q0_LOAD_DATA_ADDR + + reg_offset, val); + cam_io_w_mb(val, base + CCI_I2C_M0_Q0_LOAD_DATA_ADDR + + reg_offset); + + spin_lock_irqsave(&cci_dev->cci_master_info[master].lock_q[queue], + flags); + atomic_set(&cci_dev->cci_master_info[master].q_free[queue], 0); + spin_unlock_irqrestore(&cci_dev->cci_master_info[master].lock_q[queue], + flags); + + max_queue_size = + cci_dev->cci_i2c_queue_info[master][queue].max_queue_size; + + if (c_ctrl->cmd == MSM_CCI_I2C_WRITE_SEQ) + queue_size = max_queue_size; + else + queue_size = max_queue_size/2; + reg_addr = i2c_cmd->reg_addr; + + if (sync_en == MSM_SYNC_ENABLE && cci_dev->valid_sync && + cmd_size < max_queue_size) { + val = CCI_I2C_WAIT_SYNC_CMD | + ((cci_dev->cci_wait_sync_cfg.line) << 4); + cam_io_w_mb(val, + base + CCI_I2C_M0_Q0_LOAD_DATA_ADDR + + reg_offset); + } + + rc = cam_cci_lock_queue(cci_dev, master, queue, 1); + if (rc < 0) { + CAM_ERR(CAM_CCI, "failed line %d", rc); + return rc; + } + + while (cmd_size) { + uint32_t pack = 0; + + len = cam_cci_calc_cmd_len(cci_dev, c_ctrl, cmd_size, + i2c_cmd, &pack); + if (len <= 0) { + CAM_ERR(CAM_CCI, "failed"); + return -EINVAL; + } + + read_val = cam_io_r_mb(base + + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset); + CAM_DBG(CAM_CCI, "CUR_WORD_CNT_ADDR %d len %d max %d", + read_val, len, max_queue_size); + /* + 1 - space alocation for Report CMD */ + if ((read_val + len + 1) > queue_size) { + if ((read_val + len + 1) > max_queue_size) { + rc = cam_cci_process_full_q(cci_dev, + master, queue); + if (rc < 0) { + CAM_ERR(CAM_CCI, "failed rc: %d", rc); + return rc; + } + continue; + } + cam_cci_process_half_q(cci_dev, master, queue); + } + + CAM_DBG(CAM_CCI, "cmd_size %d addr 0x%x data 0x%x", + cmd_size, i2c_cmd->reg_addr, i2c_cmd->reg_data); + delay = i2c_cmd->delay; + i = 0; + data[i++] = CCI_I2C_WRITE_CMD; + + /* + * in case of multiple command + * MSM_CCI_I2C_WRITE : address is not continuous, so update + * address for a new packet. + * MSM_CCI_I2C_WRITE_SEQ : address is continuous, need to keep + * the incremented address for a + * new packet + */ + if (c_ctrl->cmd == MSM_CCI_I2C_WRITE || + c_ctrl->cmd == MSM_CCI_I2C_WRITE_ASYNC || + c_ctrl->cmd == MSM_CCI_I2C_WRITE_SYNC || + c_ctrl->cmd == MSM_CCI_I2C_WRITE_SYNC_BLOCK) + reg_addr = i2c_cmd->reg_addr; + + if (en_seq_write == 0) { + /* either byte or word addr */ + if (i2c_msg->addr_type == CAMERA_SENSOR_I2C_TYPE_BYTE) + data[i++] = reg_addr; + else { + data[i++] = (reg_addr & 0xFF00) >> 8; + data[i++] = reg_addr & 0x00FF; + } + } + /* max of 10 data bytes */ + do { + if (i2c_msg->data_type == CAMERA_SENSOR_I2C_TYPE_BYTE) { + data[i++] = i2c_cmd->reg_data; + if (c_ctrl->cmd == MSM_CCI_I2C_WRITE_SEQ) + reg_addr++; + } else { + if ((i + 1) <= cci_dev->payload_size) { + switch (i2c_msg->data_type) { + case CAMERA_SENSOR_I2C_TYPE_DWORD: + data[i++] = (i2c_cmd->reg_data & + 0xFF000000) >> 24; + /* fallthrough */ + case CAMERA_SENSOR_I2C_TYPE_3B: + data[i++] = (i2c_cmd->reg_data & + 0x00FF0000) >> 16; + /* fallthrough */ + case CAMERA_SENSOR_I2C_TYPE_WORD: + data[i++] = (i2c_cmd->reg_data & + 0x0000FF00) >> 8; + /* fallthrough */ + case CAMERA_SENSOR_I2C_TYPE_BYTE: + data[i++] = i2c_cmd->reg_data & + 0x000000FF; + break; + default: + CAM_ERR(CAM_CCI, + "invalid data type: %d", + i2c_msg->data_type); + return -EINVAL; + } + + if (c_ctrl->cmd == + MSM_CCI_I2C_WRITE_SEQ) + reg_addr++; + } else + break; + } + i2c_cmd++; + --cmd_size; + } while (((c_ctrl->cmd == MSM_CCI_I2C_WRITE_SEQ || + c_ctrl->cmd == MSM_CCI_I2C_WRITE_BURST) || pack--) && + (cmd_size > 0) && (i <= cci_dev->payload_size)); + free_size = cam_cci_get_queue_free_size(cci_dev, master, + queue); + if ((c_ctrl->cmd == MSM_CCI_I2C_WRITE_SEQ || + c_ctrl->cmd == MSM_CCI_I2C_WRITE_BURST) && + ((i-1) == MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_11) && + cci_dev->support_seq_write && cmd_size > 0 && + free_size > BURST_MIN_FREE_SIZE) { + data[0] |= 0xF0; + en_seq_write = 1; + } else { + data[0] |= ((i-1) << 4); + en_seq_write = 0; + } + len = ((i-1)/4) + 1; + + read_val = cam_io_r_mb(base + + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset); + for (h = 0, k = 0; h < len; h++) { + cmd = 0; + for (j = 0; (j < 4 && k < i); j++) + cmd |= (data[k++] << (j * 8)); + CAM_DBG(CAM_CCI, + "LOAD_DATA_ADDR 0x%x, q: %d, len:%d, cnt: %d", + cmd, queue, len, read_val); + cam_io_w_mb(cmd, base + + CCI_I2C_M0_Q0_LOAD_DATA_ADDR + + master * 0x200 + queue * 0x100); + + read_val += 1; + cam_io_w_mb(read_val, base + + CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + reg_offset); + } + + if ((delay > 0) && (delay < CCI_MAX_DELAY) && + en_seq_write == 0) { + cmd = (uint32_t)((delay * cci_dev->cycles_per_us) / + 0x100); + cmd <<= 4; + cmd |= CCI_I2C_WAIT_CMD; + CAM_DBG(CAM_CCI, + "CCI_I2C_M0_Q0_LOAD_DATA_ADDR 0x%x", cmd); + cam_io_w_mb(cmd, base + + CCI_I2C_M0_Q0_LOAD_DATA_ADDR + + master * 0x200 + queue * 0x100); + read_val += 1; + cam_io_w_mb(read_val, base + + CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + reg_offset); + } + } + + rc = cam_cci_transfer_end(cci_dev, master, queue); + if (rc < 0) { + CAM_ERR(CAM_CCI, "failed rc %d", rc); + return rc; + } + + return rc; +} + +static int32_t cam_cci_burst_read(struct v4l2_subdev *sd, + struct cam_cci_ctrl *c_ctrl) +{ + int32_t rc = 0; + uint32_t val = 0, i = 0, j = 0, irq_mask_update = 0; + unsigned long rem_jiffies, flags; + int32_t read_words = 0, exp_words = 0; + int32_t index = 0, first_byte = 0, total_read_words = 0; + enum cci_i2c_master_t master; + enum cci_i2c_queue_t queue = QUEUE_1; + struct cci_device *cci_dev = NULL; + struct cam_cci_read_cfg *read_cfg = NULL; + struct cam_hw_soc_info *soc_info = NULL; + void __iomem *base = NULL; + + cci_dev = v4l2_get_subdevdata(sd); + master = c_ctrl->cci_info->cci_i2c_master; + read_cfg = &c_ctrl->cfg.cci_i2c_read_cfg; + + if (c_ctrl->cci_info->cci_i2c_master >= MASTER_MAX + || c_ctrl->cci_info->cci_i2c_master < 0) { + CAM_ERR(CAM_CCI, "Invalid I2C master addr"); + return -EINVAL; + } + + soc_info = &cci_dev->soc_info; + base = soc_info->reg_map[0].mem_base; + + mutex_lock(&cci_dev->cci_master_info[master].mutex); + if (cci_dev->cci_master_info[master].is_first_req) { + cci_dev->cci_master_info[master].is_first_req = false; + CAM_DBG(CAM_CCI, "Master: %d, curr_freq: %d, req_freq: %d", + master, cci_dev->i2c_freq_mode[master], + c_ctrl->cci_info->i2c_freq_mode); + down(&cci_dev->cci_master_info[master].master_sem); + } else if (c_ctrl->cci_info->i2c_freq_mode + != cci_dev->i2c_freq_mode[master]) { + CAM_DBG(CAM_CCI, "Master: %d, curr_freq: %d, req_freq: %d", + master, cci_dev->i2c_freq_mode[master], + c_ctrl->cci_info->i2c_freq_mode); + down(&cci_dev->cci_master_info[master].master_sem); + } else { + CAM_DBG(CAM_CCI, "Master: %d, curr_freq: %d, req_freq: %d", + master, cci_dev->i2c_freq_mode[master], + c_ctrl->cci_info->i2c_freq_mode); + spin_lock(&cci_dev->cci_master_info[master].freq_cnt); + cci_dev->cci_master_info[master].freq_ref_cnt++; + spin_unlock(&cci_dev->cci_master_info[master].freq_cnt); + } + + /* Set the I2C Frequency */ + rc = cam_cci_set_clk_param(cci_dev, c_ctrl); + if (rc < 0) { + CAM_ERR(CAM_CCI, "cam_cci_set_clk_param failed rc = %d", rc); + mutex_unlock(&cci_dev->cci_master_info[master].mutex); + goto rel_master; + } + mutex_unlock(&cci_dev->cci_master_info[master].mutex); + + mutex_lock(&cci_dev->cci_master_info[master].mutex_q[queue]); + /* + * Call validate queue to make sure queue is empty before starting. + * If this call fails, don't proceed with i2c_read call. This is to + * avoid overflow / underflow of queue + */ + rc = cam_cci_validate_queue(cci_dev, + cci_dev->cci_i2c_queue_info[master][queue].max_queue_size - 1, + master, queue); + if (rc < 0) { + CAM_ERR(CAM_CCI, "Initial validataion failed rc %d", rc); + goto rel_mutex_q; + } + + if (c_ctrl->cci_info->retries > CCI_I2C_READ_MAX_RETRIES) { + CAM_ERR(CAM_CCI, "More than max retries"); + goto rel_mutex_q; + } + + if (read_cfg->data == NULL) { + CAM_ERR(CAM_CCI, "Data ptr is NULL"); + goto rel_mutex_q; + } + + if (read_cfg->addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX) { + CAM_ERR(CAM_CCI, "failed : Invalid addr type: %u", + read_cfg->addr_type); + rc = -EINVAL; + goto rel_mutex_q; + } + + CAM_DBG(CAM_CCI, "set param sid 0x%x retries %d id_map %d", + c_ctrl->cci_info->sid, c_ctrl->cci_info->retries, + c_ctrl->cci_info->id_map); + val = CCI_I2C_SET_PARAM_CMD | c_ctrl->cci_info->sid << 4 | + c_ctrl->cci_info->retries << 16 | + c_ctrl->cci_info->id_map << 18; + rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); + if (rc < 0) { + CAM_DBG(CAM_CCI, "failed rc: %d", rc); + goto rel_mutex_q; + } + + val = CCI_I2C_LOCK_CMD; + rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); + if (rc < 0) { + CAM_DBG(CAM_CCI, "failed rc: %d", rc); + goto rel_mutex_q; + } + + val = CCI_I2C_WRITE_DISABLE_P_CMD | (read_cfg->addr_type << 4); + for (i = 0; i < read_cfg->addr_type; i++) { + val |= ((read_cfg->addr >> (i << 3)) & 0xFF) << + ((read_cfg->addr_type - i) << 3); + } + + rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); + if (rc < 0) { + CAM_DBG(CAM_CCI, "failed rc: %d", rc); + goto rel_mutex_q; + } + + val = CCI_I2C_READ_CMD | (read_cfg->num_byte << 4); + rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); + if (rc < 0) { + CAM_DBG(CAM_CCI, "failed rc: %d", rc); + goto rel_mutex_q; + } + + val = CCI_I2C_UNLOCK_CMD; + rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); + if (rc < 0) { + CAM_DBG(CAM_CCI, "failed rc: %d", rc); + goto rel_mutex_q; + } + + val = cam_io_r_mb(base + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + + master * 0x200 + queue * 0x100); + CAM_DBG(CAM_CCI, "cur word cnt 0x%x", val); + cam_io_w_mb(val, base + CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + + master * 0x200 + queue * 0x100); + + val = 1 << ((master * 2) + queue); + cam_io_w_mb(val, base + CCI_QUEUE_START_ADDR); + + exp_words = ((read_cfg->num_byte / 4) + 1); + CAM_DBG(CAM_CCI, "waiting for threshold [exp_words %d]", exp_words); + + while (total_read_words != exp_words) { + rem_jiffies = wait_for_completion_timeout( + &cci_dev->cci_master_info[master].th_complete, + CCI_TIMEOUT); + if (!rem_jiffies) { + rc = -ETIMEDOUT; + val = cam_io_r_mb(base + + CCI_I2C_M0_READ_BUF_LEVEL_ADDR + + master * 0x100); + CAM_ERR(CAM_CCI, + "wait_for_completion_timeout rc = %d FIFO buf_lvl:0x%x", + rc, val); + cam_cci_dump_registers(cci_dev, master, queue); + + cam_cci_flush_queue(cci_dev, master); + goto rel_mutex_q; + } + + read_words = cam_io_r_mb(base + + CCI_I2C_M0_READ_BUF_LEVEL_ADDR + master * 0x100); + if (read_words <= 0) { + CAM_DBG(CAM_CCI, "FIFO Buffer lvl is 0"); + continue; + } + + j++; + CAM_DBG(CAM_CCI, "Iteration: %u read_words %d", j, read_words); + + total_read_words += read_words; + while (read_words > 0) { + val = cam_io_r_mb(base + + CCI_I2C_M0_READ_DATA_ADDR + master * 0x100); + for (i = 0; (i < 4) && + (index < read_cfg->num_byte); i++) { + CAM_DBG(CAM_CCI, "i:%d index:%d", i, index); + if (!first_byte) { + CAM_DBG(CAM_CCI, "sid 0x%x", + val & 0xFF); + first_byte++; + } else { + read_cfg->data[index] = + (val >> (i * 8)) & 0xFF; + CAM_DBG(CAM_CCI, "data[%d] 0x%x", index, + read_cfg->data[index]); + index++; + } + } + read_words--; + } + + CAM_DBG(CAM_CCI, "Iteraion:%u total_read_words %d", + j, total_read_words); + + spin_lock_irqsave(&cci_dev->lock_status, flags); + if (cci_dev->irqs_disabled) { + irq_mask_update = + cam_io_r_mb(base + CCI_IRQ_MASK_1_ADDR) | + CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD; + if (master == MASTER_0 && cci_dev->irqs_disabled & + CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD) + irq_mask_update |= + CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD; + else if (master == MASTER_1 && cci_dev->irqs_disabled & + CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD) + irq_mask_update |= + CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD; + cam_io_w_mb(irq_mask_update, + base + CCI_IRQ_MASK_1_ADDR); + } + spin_unlock_irqrestore(&cci_dev->lock_status, flags); + + if (total_read_words == exp_words) { + /* + * This wait is for RD_DONE irq, if RD_DONE is + * triggered we will call complete on both threshold + * & read done waits. As part of the threshold wait + * we will be draining the entire buffer out. This + * wait is to compensate for the complete invoked for + * RD_DONE exclusively. + */ + rem_jiffies = wait_for_completion_timeout( + &cci_dev->cci_master_info[master].rd_done, + CCI_TIMEOUT); + if (!rem_jiffies) { + rc = -ETIMEDOUT; + val = cam_io_r_mb(base + + CCI_I2C_M0_READ_BUF_LEVEL_ADDR + + master * 0x100); + CAM_ERR(CAM_CCI, + "Failed to receive RD_DONE irq rc = %d FIFO buf_lvl:0x%x", + rc, val); + cam_cci_dump_registers(cci_dev, + master, queue); + + cam_cci_flush_queue(cci_dev, master); + goto rel_mutex_q; + } + break; + } + } + + CAM_DBG(CAM_CCI, "Burst read successful words_read %d", + total_read_words); + +rel_mutex_q: + mutex_unlock(&cci_dev->cci_master_info[master].mutex_q[queue]); +rel_master: + spin_lock(&cci_dev->cci_master_info[master].freq_cnt); + if (cci_dev->cci_master_info[master].freq_ref_cnt == 0) + up(&cci_dev->cci_master_info[master].master_sem); + else + cci_dev->cci_master_info[master].freq_ref_cnt--; + spin_unlock(&cci_dev->cci_master_info[master].freq_cnt); + return rc; +} + +static int32_t cam_cci_read(struct v4l2_subdev *sd, + struct cam_cci_ctrl *c_ctrl) +{ + int32_t rc = 0; + uint32_t val = 0; + int32_t read_words = 0, exp_words = 0; + int32_t index = 0, first_byte = 0; + uint32_t i = 0; + enum cci_i2c_master_t master; + enum cci_i2c_queue_t queue = QUEUE_1; + struct cci_device *cci_dev = NULL; + struct cam_cci_read_cfg *read_cfg = NULL; + struct cam_hw_soc_info *soc_info = NULL; + void __iomem *base = NULL; + + cci_dev = v4l2_get_subdevdata(sd); + master = c_ctrl->cci_info->cci_i2c_master; + read_cfg = &c_ctrl->cfg.cci_i2c_read_cfg; + + if (c_ctrl->cci_info->cci_i2c_master >= MASTER_MAX + || c_ctrl->cci_info->cci_i2c_master < 0) { + CAM_ERR(CAM_CCI, "Invalid I2C master addr"); + return -EINVAL; + } + + soc_info = &cci_dev->soc_info; + base = soc_info->reg_map[0].mem_base; + + mutex_lock(&cci_dev->cci_master_info[master].mutex); + if (cci_dev->cci_master_info[master].is_first_req) { + cci_dev->cci_master_info[master].is_first_req = false; + CAM_DBG(CAM_CCI, "Master: %d, curr_freq: %d, req_freq: %d", + master, cci_dev->i2c_freq_mode[master], + c_ctrl->cci_info->i2c_freq_mode); + down(&cci_dev->cci_master_info[master].master_sem); + } else if (c_ctrl->cci_info->i2c_freq_mode + != cci_dev->i2c_freq_mode[master]) { + CAM_DBG(CAM_CCI, "Master: %d, curr_freq: %d, req_freq: %d", + master, cci_dev->i2c_freq_mode[master], + c_ctrl->cci_info->i2c_freq_mode); + down(&cci_dev->cci_master_info[master].master_sem); + } else { + CAM_DBG(CAM_CCI, "Master: %d, curr_freq: %d, req_freq: %d", + master, cci_dev->i2c_freq_mode[master], + c_ctrl->cci_info->i2c_freq_mode); + spin_lock(&cci_dev->cci_master_info[master].freq_cnt); + cci_dev->cci_master_info[master].freq_ref_cnt++; + spin_unlock(&cci_dev->cci_master_info[master].freq_cnt); + } + + /* Set the I2C Frequency */ + rc = cam_cci_set_clk_param(cci_dev, c_ctrl); + if (rc < 0) { + mutex_unlock(&cci_dev->cci_master_info[master].mutex); + CAM_ERR(CAM_CCI, "cam_cci_set_clk_param failed rc = %d", rc); + goto rel_master; + } + mutex_unlock(&cci_dev->cci_master_info[master].mutex); + + mutex_lock(&cci_dev->cci_master_info[master].mutex_q[queue]); + /* + * Call validate queue to make sure queue is empty before starting. + * If this call fails, don't proceed with i2c_read call. This is to + * avoid overflow / underflow of queue + */ + rc = cam_cci_validate_queue(cci_dev, + cci_dev->cci_i2c_queue_info[master][queue].max_queue_size - 1, + master, queue); + if (rc < 0) { + CAM_ERR(CAM_CCI, "Initial validataion failed rc %d", rc); + goto rel_mutex_q; + } + + if (c_ctrl->cci_info->retries > CCI_I2C_READ_MAX_RETRIES) { + CAM_ERR(CAM_CCI, "More than max retries"); + goto rel_mutex_q; + } + + if (read_cfg->data == NULL) { + CAM_ERR(CAM_CCI, "Data ptr is NULL"); + goto rel_mutex_q; + } + + CAM_DBG(CAM_CCI, "master %d, queue %d", master, queue); + CAM_DBG(CAM_CCI, "set param sid 0x%x retries %d id_map %d", + c_ctrl->cci_info->sid, c_ctrl->cci_info->retries, + c_ctrl->cci_info->id_map); + val = CCI_I2C_SET_PARAM_CMD | c_ctrl->cci_info->sid << 4 | + c_ctrl->cci_info->retries << 16 | + c_ctrl->cci_info->id_map << 18; + rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); + if (rc < 0) { + CAM_DBG(CAM_CCI, "failed rc: %d", rc); + goto rel_mutex_q; + } + + val = CCI_I2C_LOCK_CMD; + rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); + if (rc < 0) { + CAM_DBG(CAM_CCI, "failed rc: %d", rc); + goto rel_mutex_q; + } + + if (read_cfg->addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX) { + CAM_ERR(CAM_CCI, "failed : Invalid addr type: %u", + read_cfg->addr_type); + rc = -EINVAL; + goto rel_mutex_q; + } + + val = CCI_I2C_WRITE_DISABLE_P_CMD | (read_cfg->addr_type << 4); + for (i = 0; i < read_cfg->addr_type; i++) { + val |= ((read_cfg->addr >> (i << 3)) & 0xFF) << + ((read_cfg->addr_type - i) << 3); + } + + rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); + if (rc < 0) { + CAM_DBG(CAM_CCI, "failed rc: %d", rc); + goto rel_mutex_q; + } + + val = CCI_I2C_READ_CMD | (read_cfg->num_byte << 4); + rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); + if (rc < 0) { + CAM_DBG(CAM_CCI, "failed rc: %d", rc); + goto rel_mutex_q; + } + + val = CCI_I2C_UNLOCK_CMD; + rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); + if (rc < 0) { + CAM_DBG(CAM_CCI, "failed rc: %d", rc); + goto rel_mutex_q; + } + + val = cam_io_r_mb(base + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + + master * 0x200 + queue * 0x100); + CAM_DBG(CAM_CCI, "cur word cnt 0x%x", val); + cam_io_w_mb(val, base + CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + + master * 0x200 + queue * 0x100); + + val = 1 << ((master * 2) + queue); + cam_io_w_mb(val, base + CCI_QUEUE_START_ADDR); + CAM_DBG(CAM_CCI, + "waiting_for_rd_done [exp_words: %d]", + ((read_cfg->num_byte / 4) + 1)); + + rc = wait_for_completion_timeout( + &cci_dev->cci_master_info[master].rd_done, CCI_TIMEOUT); + if (rc <= 0) { + cam_cci_dump_registers(cci_dev, master, queue); + + if (rc == 0) + rc = -ETIMEDOUT; + val = cam_io_r_mb(base + + CCI_I2C_M0_READ_BUF_LEVEL_ADDR + master * 0x100); + CAM_ERR(CAM_CCI, + "wait_for_completion_timeout rc = %d FIFO buf_lvl: 0x%x", + rc, val); + cam_cci_flush_queue(cci_dev, master); + goto rel_mutex_q; + } else { + rc = 0; + } + + read_words = cam_io_r_mb(base + + CCI_I2C_M0_READ_BUF_LEVEL_ADDR + master * 0x100); + exp_words = ((read_cfg->num_byte / 4) + 1); + if (read_words != exp_words) { + CAM_ERR(CAM_CCI, "read_words = %d, exp words = %d", + read_words, exp_words); + memset(read_cfg->data, 0, read_cfg->num_byte); + rc = -EINVAL; + goto rel_mutex_q; + } + index = 0; + CAM_DBG(CAM_CCI, "index %d num_type %d", index, read_cfg->num_byte); + first_byte = 0; + while (read_words > 0) { + val = cam_io_r_mb(base + + CCI_I2C_M0_READ_DATA_ADDR + master * 0x100); + CAM_DBG(CAM_CCI, "read val 0x%x", val); + for (i = 0; (i < 4) && (index < read_cfg->num_byte); i++) { + CAM_DBG(CAM_CCI, "i:%d index:%d", i, index); + if (!first_byte) { + CAM_DBG(CAM_CCI, "sid 0x%x", val & 0xFF); + first_byte++; + } else { + read_cfg->data[index] = + (val >> (i * 8)) & 0xFF; + CAM_DBG(CAM_CCI, "data[%d] 0x%x", index, + read_cfg->data[index]); + index++; + } + } + read_words--; + } +rel_mutex_q: + mutex_unlock(&cci_dev->cci_master_info[master].mutex_q[queue]); +rel_master: + spin_lock(&cci_dev->cci_master_info[master].freq_cnt); + if (cci_dev->cci_master_info[master].freq_ref_cnt == 0) + up(&cci_dev->cci_master_info[master].master_sem); + else + cci_dev->cci_master_info[master].freq_ref_cnt--; + spin_unlock(&cci_dev->cci_master_info[master].freq_cnt); + return rc; +} + +static int32_t cam_cci_i2c_write(struct v4l2_subdev *sd, + struct cam_cci_ctrl *c_ctrl, enum cci_i2c_queue_t queue, + enum cci_i2c_sync sync_en) +{ + int32_t rc = 0; + struct cci_device *cci_dev; + enum cci_i2c_master_t master; + + cci_dev = v4l2_get_subdevdata(sd); + + if (cci_dev->cci_state != CCI_STATE_ENABLED) { + CAM_ERR(CAM_CCI, "invalid cci state %d", + cci_dev->cci_state); + return -EINVAL; + } + master = c_ctrl->cci_info->cci_i2c_master; + CAM_DBG(CAM_CCI, "set param sid 0x%x retries %d id_map %d", + c_ctrl->cci_info->sid, c_ctrl->cci_info->retries, + c_ctrl->cci_info->id_map); + + mutex_lock(&cci_dev->cci_master_info[master].mutex); + if (cci_dev->cci_master_info[master].is_first_req) { + cci_dev->cci_master_info[master].is_first_req = false; + CAM_DBG(CAM_CCI, "Master: %d, curr_freq: %d, req_freq: %d", + master, cci_dev->i2c_freq_mode[master], + c_ctrl->cci_info->i2c_freq_mode); + down(&cci_dev->cci_master_info[master].master_sem); + } else if (c_ctrl->cci_info->i2c_freq_mode + != cci_dev->i2c_freq_mode[master]) { + CAM_DBG(CAM_CCI, "Master: %d, curr_freq: %d, req_freq: %d", + master, cci_dev->i2c_freq_mode[master], + c_ctrl->cci_info->i2c_freq_mode); + down(&cci_dev->cci_master_info[master].master_sem); + } else { + CAM_DBG(CAM_CCI, "Master: %d, curr_freq: %d, req_freq: %d", + master, cci_dev->i2c_freq_mode[master], + c_ctrl->cci_info->i2c_freq_mode); + spin_lock(&cci_dev->cci_master_info[master].freq_cnt); + cci_dev->cci_master_info[master].freq_ref_cnt++; + spin_unlock(&cci_dev->cci_master_info[master].freq_cnt); + } + + /* Set the I2C Frequency */ + rc = cam_cci_set_clk_param(cci_dev, c_ctrl); + if (rc < 0) { + CAM_ERR(CAM_CCI, "cam_cci_set_clk_param failed rc = %d", rc); + mutex_unlock(&cci_dev->cci_master_info[master].mutex); + goto ERROR; + } + mutex_unlock(&cci_dev->cci_master_info[master].mutex); + /* + * Call validate queue to make sure queue is empty before starting. + * If this call fails, don't proceed with i2c_write call. This is to + * avoid overflow / underflow of queue + */ + rc = cam_cci_validate_queue(cci_dev, + cci_dev->cci_i2c_queue_info[master][queue].max_queue_size-1, + master, queue); + if (rc < 0) { + CAM_ERR(CAM_CCI, "Initial validataion failed rc %d", + rc); + goto ERROR; + } + if (c_ctrl->cci_info->retries > CCI_I2C_READ_MAX_RETRIES) { + CAM_ERR(CAM_CCI, "More than max retries"); + goto ERROR; + } + rc = cam_cci_data_queue(cci_dev, c_ctrl, queue, sync_en); + if (rc < 0) { + CAM_ERR(CAM_CCI, "failed rc: %d", rc); + goto ERROR; + } + +ERROR: + spin_lock(&cci_dev->cci_master_info[master].freq_cnt); + if (cci_dev->cci_master_info[master].freq_ref_cnt == 0) + up(&cci_dev->cci_master_info[master].master_sem); + else + cci_dev->cci_master_info[master].freq_ref_cnt--; + spin_unlock(&cci_dev->cci_master_info[master].freq_cnt); + return rc; +} + +static void cam_cci_write_async_helper(struct work_struct *work) +{ + int rc; + struct cci_device *cci_dev; + struct cci_write_async *write_async = + container_of(work, struct cci_write_async, work); + struct cam_sensor_i2c_reg_setting *i2c_msg; + enum cci_i2c_master_t master; + struct cam_cci_master_info *cci_master_info; + + cam_req_mgr_thread_switch_delay_detect( + write_async->workq_scheduled_ts); + cci_dev = write_async->cci_dev; + i2c_msg = &write_async->c_ctrl.cfg.cci_i2c_write_cfg; + master = write_async->c_ctrl.cci_info->cci_i2c_master; + cci_master_info = &cci_dev->cci_master_info[master]; + + mutex_lock(&cci_master_info->mutex_q[write_async->queue]); + rc = cam_cci_i2c_write(&(cci_dev->v4l2_dev_str.sd), + &write_async->c_ctrl, write_async->queue, write_async->sync_en); + mutex_unlock(&cci_master_info->mutex_q[write_async->queue]); + if (rc < 0) + CAM_ERR(CAM_CCI, "failed rc: %d", rc); + + kfree(write_async->c_ctrl.cfg.cci_i2c_write_cfg.reg_setting); + kfree(write_async); +} + +static int32_t cam_cci_i2c_write_async(struct v4l2_subdev *sd, + struct cam_cci_ctrl *c_ctrl, enum cci_i2c_queue_t queue, + enum cci_i2c_sync sync_en) +{ + int32_t rc = 0; + struct cci_write_async *write_async; + struct cci_device *cci_dev; + struct cam_sensor_i2c_reg_setting *cci_i2c_write_cfg; + struct cam_sensor_i2c_reg_setting *cci_i2c_write_cfg_w; + + cci_dev = v4l2_get_subdevdata(sd); + + write_async = kzalloc(sizeof(*write_async), GFP_KERNEL); + if (!write_async) + return -ENOMEM; + + + INIT_WORK(&write_async->work, cam_cci_write_async_helper); + write_async->cci_dev = cci_dev; + write_async->c_ctrl = *c_ctrl; + write_async->queue = queue; + write_async->sync_en = sync_en; + + cci_i2c_write_cfg = &c_ctrl->cfg.cci_i2c_write_cfg; + cci_i2c_write_cfg_w = &write_async->c_ctrl.cfg.cci_i2c_write_cfg; + + if (cci_i2c_write_cfg->size == 0) { + kfree(write_async); + return -EINVAL; + } + + cci_i2c_write_cfg_w->reg_setting = + kzalloc(sizeof(struct cam_sensor_i2c_reg_array)* + cci_i2c_write_cfg->size, GFP_KERNEL); + if (!cci_i2c_write_cfg_w->reg_setting) { + CAM_ERR(CAM_CCI, "Couldn't allocate memory"); + kfree(write_async); + return -ENOMEM; + } + memcpy(cci_i2c_write_cfg_w->reg_setting, + cci_i2c_write_cfg->reg_setting, + (sizeof(struct cam_sensor_i2c_reg_array)* + cci_i2c_write_cfg->size)); + + cci_i2c_write_cfg_w->addr_type = cci_i2c_write_cfg->addr_type; + cci_i2c_write_cfg_w->addr_type = cci_i2c_write_cfg->addr_type; + cci_i2c_write_cfg_w->data_type = cci_i2c_write_cfg->data_type; + cci_i2c_write_cfg_w->size = cci_i2c_write_cfg->size; + cci_i2c_write_cfg_w->delay = cci_i2c_write_cfg->delay; + + write_async->workq_scheduled_ts = ktime_get(); + queue_work(cci_dev->write_wq[write_async->queue], &write_async->work); + + return rc; +} + +static int32_t cam_cci_read_bytes_v_1_2(struct v4l2_subdev *sd, + struct cam_cci_ctrl *c_ctrl) +{ + int32_t rc = 0; + struct cci_device *cci_dev = NULL; + enum cci_i2c_master_t master; + struct cam_cci_read_cfg *read_cfg = NULL; + uint16_t read_bytes = 0; + + if (!sd || !c_ctrl) { + CAM_ERR(CAM_CCI, "sd %pK c_ctrl %pK", sd, c_ctrl); + return -EINVAL; + } + if (!c_ctrl->cci_info) { + CAM_ERR(CAM_CCI, "cci_info NULL"); + return -EINVAL; + } + cci_dev = v4l2_get_subdevdata(sd); + if (!cci_dev) { + CAM_ERR(CAM_CCI, "cci_dev NULL"); + return -EINVAL; + } + if (cci_dev->cci_state != CCI_STATE_ENABLED) { + CAM_ERR(CAM_CCI, "invalid cci state %d", cci_dev->cci_state); + return -EINVAL; + } + + if (c_ctrl->cci_info->cci_i2c_master >= MASTER_MAX + || c_ctrl->cci_info->cci_i2c_master < 0) { + CAM_ERR(CAM_CCI, "Invalid I2C master addr"); + return -EINVAL; + } + + master = c_ctrl->cci_info->cci_i2c_master; + read_cfg = &c_ctrl->cfg.cci_i2c_read_cfg; + if ((!read_cfg->num_byte) || (read_cfg->num_byte > CCI_I2C_MAX_READ)) { + CAM_ERR(CAM_CCI, "read num bytes 0"); + rc = -EINVAL; + goto ERROR; + } + + read_bytes = read_cfg->num_byte; + CAM_DBG(CAM_CCI, "Bytes to read %u", read_bytes); + do { + if (read_bytes >= CCI_READ_MAX_V_1_2) + read_cfg->num_byte = CCI_READ_MAX_V_1_2; + else + read_cfg->num_byte = read_bytes; + + cci_dev->is_burst_read = false; + rc = cam_cci_read(sd, c_ctrl); + if (rc) { + CAM_ERR(CAM_CCI, "failed to read rc:%d", rc); + goto ERROR; + } + + if (read_bytes >= CCI_READ_MAX_V_1_2) { + read_cfg->addr += CCI_READ_MAX_V_1_2; + read_cfg->data += CCI_READ_MAX_V_1_2; + read_bytes -= CCI_READ_MAX_V_1_2; + } else { + read_bytes = 0; + } + } while (read_bytes); + +ERROR: + cci_dev->is_burst_read = false; + return rc; +} + +static int32_t cam_cci_read_bytes(struct v4l2_subdev *sd, + struct cam_cci_ctrl *c_ctrl) +{ + int32_t rc = 0; + struct cci_device *cci_dev = NULL; + enum cci_i2c_master_t master; + struct cam_cci_read_cfg *read_cfg = NULL; + uint16_t read_bytes = 0; + + if (!sd || !c_ctrl) { + CAM_ERR(CAM_CCI, "sd %pK c_ctrl %pK", sd, c_ctrl); + return -EINVAL; + } + if (!c_ctrl->cci_info) { + CAM_ERR(CAM_CCI, "cci_info NULL"); + return -EINVAL; + } + cci_dev = v4l2_get_subdevdata(sd); + if (!cci_dev) { + CAM_ERR(CAM_CCI, "cci_dev NULL"); + return -EINVAL; + } + if (cci_dev->cci_state != CCI_STATE_ENABLED) { + CAM_ERR(CAM_CCI, "invalid cci state %d", cci_dev->cci_state); + return -EINVAL; + } + + if (c_ctrl->cci_info->cci_i2c_master >= MASTER_MAX + || c_ctrl->cci_info->cci_i2c_master < 0) { + CAM_ERR(CAM_CCI, "Invalid I2C master addr"); + return -EINVAL; + } + + master = c_ctrl->cci_info->cci_i2c_master; + read_cfg = &c_ctrl->cfg.cci_i2c_read_cfg; + if ((!read_cfg->num_byte) || (read_cfg->num_byte > CCI_I2C_MAX_READ)) { + CAM_ERR(CAM_CCI, "read num bytes 0"); + rc = -EINVAL; + goto ERROR; + } + + read_bytes = read_cfg->num_byte; + + /* + * To avoid any conflicts due to back to back trigger of + * THRESHOLD irq's, we reinit the threshold wait before + * we load the burst read cmd. + */ + reinit_completion(&cci_dev->cci_master_info[master].th_complete); + + CAM_DBG(CAM_CCI, "Bytes to read %u", read_bytes); + do { + if (read_bytes >= CCI_I2C_MAX_BYTE_COUNT) + read_cfg->num_byte = CCI_I2C_MAX_BYTE_COUNT; + else + read_cfg->num_byte = read_bytes; + + if (read_cfg->num_byte >= CCI_READ_MAX) { + cci_dev->is_burst_read = true; + rc = cam_cci_burst_read(sd, c_ctrl); + } else { + cci_dev->is_burst_read = false; + rc = cam_cci_read(sd, c_ctrl); + } + if (rc) { + CAM_ERR(CAM_CCI, "failed to read rc:%d", rc); + goto ERROR; + } + + if (read_bytes >= CCI_I2C_MAX_BYTE_COUNT) { + read_cfg->addr += (CCI_I2C_MAX_BYTE_COUNT / + read_cfg->data_type); + read_cfg->data += CCI_I2C_MAX_BYTE_COUNT; + read_bytes -= CCI_I2C_MAX_BYTE_COUNT; + } else { + read_bytes = 0; + } + } while (read_bytes); + +ERROR: + cci_dev->is_burst_read = false; + return rc; +} + +static int32_t cam_cci_i2c_set_sync_prms(struct v4l2_subdev *sd, + struct cam_cci_ctrl *c_ctrl) +{ + int32_t rc = 0; + struct cci_device *cci_dev; + + cci_dev = v4l2_get_subdevdata(sd); + if (!cci_dev || !c_ctrl) { + CAM_ERR(CAM_CCI, "failed: invalid params %pK %pK", + cci_dev, c_ctrl); + rc = -EINVAL; + return rc; + } + cci_dev->cci_wait_sync_cfg = c_ctrl->cfg.cci_wait_sync_cfg; + cci_dev->valid_sync = cci_dev->cci_wait_sync_cfg.csid < 0 ? 0 : 1; + + return rc; +} + +static int32_t cam_cci_release(struct v4l2_subdev *sd) +{ + uint8_t rc = 0; + struct cci_device *cci_dev; + + cci_dev = v4l2_get_subdevdata(sd); + + rc = cam_cci_soc_release(cci_dev); + if (rc < 0) { + CAM_ERR(CAM_CCI, "Failed in releasing the cci: %d", rc); + return rc; + } + + return rc; +} + +static int32_t cam_cci_write(struct v4l2_subdev *sd, + struct cam_cci_ctrl *c_ctrl) +{ + int32_t rc = 0; + struct cci_device *cci_dev; + enum cci_i2c_master_t master; + struct cam_cci_master_info *cci_master_info; + uint32_t i; + + cci_dev = v4l2_get_subdevdata(sd); + if (!cci_dev || !c_ctrl) { + CAM_ERR(CAM_CCI, "failed: invalid params %pK %pK", + cci_dev, c_ctrl); + rc = -EINVAL; + return rc; + } + + master = c_ctrl->cci_info->cci_i2c_master; + + if (c_ctrl->cci_info->cci_i2c_master >= MASTER_MAX + || c_ctrl->cci_info->cci_i2c_master < 0) { + CAM_ERR(CAM_CCI, "Invalid I2C master addr"); + return -EINVAL; + } + + cci_master_info = &cci_dev->cci_master_info[master]; + + switch (c_ctrl->cmd) { + case MSM_CCI_I2C_WRITE_SYNC_BLOCK: + mutex_lock(&cci_master_info->mutex_q[SYNC_QUEUE]); + rc = cam_cci_i2c_write(sd, c_ctrl, + SYNC_QUEUE, MSM_SYNC_ENABLE); + mutex_unlock(&cci_master_info->mutex_q[SYNC_QUEUE]); + break; + case MSM_CCI_I2C_WRITE_SYNC: + rc = cam_cci_i2c_write_async(sd, c_ctrl, + SYNC_QUEUE, MSM_SYNC_ENABLE); + break; + case MSM_CCI_I2C_WRITE: + case MSM_CCI_I2C_WRITE_SEQ: + case MSM_CCI_I2C_WRITE_BURST: + for (i = 0; i < NUM_QUEUES; i++) { + if (mutex_trylock(&cci_master_info->mutex_q[i])) { + rc = cam_cci_i2c_write(sd, c_ctrl, i, + MSM_SYNC_DISABLE); + mutex_unlock(&cci_master_info->mutex_q[i]); + return rc; + } + } + mutex_lock(&cci_master_info->mutex_q[PRIORITY_QUEUE]); + rc = cam_cci_i2c_write(sd, c_ctrl, + PRIORITY_QUEUE, MSM_SYNC_DISABLE); + mutex_unlock(&cci_master_info->mutex_q[PRIORITY_QUEUE]); + break; + case MSM_CCI_I2C_WRITE_ASYNC: + rc = cam_cci_i2c_write_async(sd, c_ctrl, + PRIORITY_QUEUE, MSM_SYNC_DISABLE); + break; + default: + rc = -ENOIOCTLCMD; + } + + return rc; +} + +int32_t cam_cci_core_cfg(struct v4l2_subdev *sd, + struct cam_cci_ctrl *cci_ctrl) +{ + int32_t rc = 0; + struct cci_device *cci_dev = v4l2_get_subdevdata(sd); + CAM_DBG(CAM_CCI, "cmd %d", cci_ctrl->cmd); + + switch (cci_ctrl->cmd) { + case MSM_CCI_INIT: + mutex_lock(&cci_dev->init_mutex); + rc = cam_cci_init(sd, cci_ctrl); + mutex_unlock(&cci_dev->init_mutex); + break; + case MSM_CCI_RELEASE: + mutex_lock(&cci_dev->init_mutex); + rc = cam_cci_release(sd); + mutex_unlock(&cci_dev->init_mutex); + break; + case MSM_CCI_I2C_READ: + /* + * CCI version 1.2 does not support burst read + * due to the absence of the read threshold register + */ + if (cci_dev->hw_version == CCI_VERSION_1_2_9) { + CAM_DBG(CAM_CCI, "cci-v1.2 no burst read"); + rc = cam_cci_read_bytes_v_1_2(sd, cci_ctrl); + } else { + rc = cam_cci_read_bytes(sd, cci_ctrl); + } + break; + case MSM_CCI_I2C_WRITE: + case MSM_CCI_I2C_WRITE_SEQ: + case MSM_CCI_I2C_WRITE_BURST: + case MSM_CCI_I2C_WRITE_SYNC: + case MSM_CCI_I2C_WRITE_ASYNC: + case MSM_CCI_I2C_WRITE_SYNC_BLOCK: + rc = cam_cci_write(sd, cci_ctrl); + break; + case MSM_CCI_GPIO_WRITE: + break; + case MSM_CCI_SET_SYNC_CID: + rc = cam_cci_i2c_set_sync_prms(sd, cci_ctrl); + break; + + default: + rc = -ENOIOCTLCMD; + } + + cci_ctrl->status = rc; + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_core.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_core.h new file mode 100644 index 0000000000000000000000000000000000000000..739fd303b236ca18123ac6e960a4442ab0f74e36 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_core.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ +#ifndef _CAM_CCI_CORE_H_ +#define _CAM_CCI_CORE_H_ + +#include +#include +#include "cam_cci_dev.h" +#include "cam_cci_soc.h" + +/** + * @cci_dev: CCI device structure + * @c_ctrl: CCI control structure + * + * This API gets CCI clk rates + */ +void cam_cci_get_clk_rates(struct cci_device *cci_dev, + struct cam_cci_ctrl *c_ctrl); + +/** + * @sd: V4L2 sub device + * @c_ctrl: CCI control structure + * + * This API handles I2C operations for CCI + */ +int32_t cam_cci_core_cfg(struct v4l2_subdev *sd, + struct cam_cci_ctrl *cci_ctrl); + +/** + * @irq_num: IRQ number + * @data: CCI private structure + * + * This API handles CCI IRQs + */ +irqreturn_t cam_cci_irq(int irq_num, void *data); + +#endif /* _CAM_CCI_CORE_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..4ce815b6394a0ce1d95a741f12b47cc23c785bd4 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include "cam_cci_dev.h" +#include "cam_req_mgr_dev.h" +#include "cam_cci_soc.h" +#include "cam_cci_core.h" + +#define CCI_MAX_DELAY 1000000 + +static struct v4l2_subdev *g_cci_subdev[MAX_CCI]; +static struct dentry *debugfs_root; + +struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index) +{ + struct v4l2_subdev *sub_device = NULL; + + if (cci_dev_index < MAX_CCI) + sub_device = g_cci_subdev[cci_dev_index]; + else + CAM_WARN(CAM_CCI, "Index: %u is beyond max num CCI allowed: %u", + cci_dev_index, + MAX_CCI); + + return sub_device; +} + +static long cam_cci_subdev_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + int32_t rc = 0; + + if (arg == NULL) { + CAM_ERR(CAM_CCI, "Invalid Args"); + return rc; + } + + switch (cmd) { + case VIDIOC_MSM_CCI_CFG: + rc = cam_cci_core_cfg(sd, arg); + break; + case VIDIOC_CAM_CONTROL: + break; + default: + CAM_ERR(CAM_CCI, "Invalid ioctl cmd: %d", cmd); + rc = -ENOIOCTLCMD; + } + + return rc; +} + +#ifdef CONFIG_COMPAT +static long cam_cci_subdev_compat_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + return cam_cci_subdev_ioctl(sd, cmd, NULL); +} +#endif + +irqreturn_t cam_cci_irq(int irq_num, void *data) +{ + uint32_t irq_status0, irq_status1, reg_bmsk; + uint32_t irq_update_rd_done = 0; + struct cci_device *cci_dev = data; + struct cam_hw_soc_info *soc_info = + &cci_dev->soc_info; + void __iomem *base = soc_info->reg_map[0].mem_base; + unsigned long flags; + bool rd_done_th_assert = false; + + irq_status0 = cam_io_r_mb(base + CCI_IRQ_STATUS_0_ADDR); + irq_status1 = cam_io_r_mb(base + CCI_IRQ_STATUS_1_ADDR); + CAM_DBG(CAM_CCI, "BASE: %pK", base); + CAM_DBG(CAM_CCI, "irq0:%x irq1:%x", irq_status0, irq_status1); + + if (irq_status0 & CCI_IRQ_STATUS_0_RST_DONE_ACK_BMSK) { + struct cam_cci_master_info *cci_master_info; + if (cci_dev->cci_master_info[MASTER_0].reset_pending == true) { + cci_master_info = &cci_dev->cci_master_info[MASTER_0]; + cci_dev->cci_master_info[MASTER_0].reset_pending = + false; + if (!cci_master_info->status) + complete(&cci_master_info->reset_complete); + cci_master_info->status = 0; + } + if (cci_dev->cci_master_info[MASTER_1].reset_pending == true) { + cci_master_info = &cci_dev->cci_master_info[MASTER_1]; + cci_dev->cci_master_info[MASTER_1].reset_pending = + false; + if (!cci_master_info->status) + complete(&cci_master_info->reset_complete); + cci_master_info->status = 0; + } + } + + if ((irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE_BMSK) && + (irq_status1 & CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD)) { + cci_dev->cci_master_info[MASTER_0].status = 0; + rd_done_th_assert = true; + complete(&cci_dev->cci_master_info[MASTER_0].th_complete); + complete(&cci_dev->cci_master_info[MASTER_0].rd_done); + } + if ((irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE_BMSK) && + (!rd_done_th_assert)) { + cci_dev->cci_master_info[MASTER_0].status = 0; + rd_done_th_assert = true; + if (cci_dev->is_burst_read) + complete( + &cci_dev->cci_master_info[MASTER_0].th_complete); + complete(&cci_dev->cci_master_info[MASTER_0].rd_done); + } + if ((irq_status1 & CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD) && + (!rd_done_th_assert)) { + cci_dev->cci_master_info[MASTER_0].status = 0; + complete(&cci_dev->cci_master_info[MASTER_0].th_complete); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT_BMSK) { + struct cam_cci_master_info *cci_master_info; + + cci_master_info = &cci_dev->cci_master_info[MASTER_0]; + spin_lock_irqsave( + &cci_dev->cci_master_info[MASTER_0].lock_q[QUEUE_0], + flags); + atomic_set(&cci_master_info->q_free[QUEUE_0], 0); + cci_master_info->status = 0; + if (atomic_read(&cci_master_info->done_pending[QUEUE_0]) == 1) { + complete(&cci_master_info->report_q[QUEUE_0]); + atomic_set(&cci_master_info->done_pending[QUEUE_0], 0); + } + spin_unlock_irqrestore( + &cci_dev->cci_master_info[MASTER_0].lock_q[QUEUE_0], + flags); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT_BMSK) { + struct cam_cci_master_info *cci_master_info; + + cci_master_info = &cci_dev->cci_master_info[MASTER_0]; + spin_lock_irqsave( + &cci_dev->cci_master_info[MASTER_0].lock_q[QUEUE_1], + flags); + atomic_set(&cci_master_info->q_free[QUEUE_1], 0); + cci_master_info->status = 0; + if (atomic_read(&cci_master_info->done_pending[QUEUE_1]) == 1) { + complete(&cci_master_info->report_q[QUEUE_1]); + atomic_set(&cci_master_info->done_pending[QUEUE_1], 0); + } + spin_unlock_irqrestore( + &cci_dev->cci_master_info[MASTER_0].lock_q[QUEUE_1], + flags); + } + rd_done_th_assert = false; + if ((irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE_BMSK) && + (irq_status1 & CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD)) { + cci_dev->cci_master_info[MASTER_1].status = 0; + rd_done_th_assert = true; + complete(&cci_dev->cci_master_info[MASTER_1].th_complete); + complete(&cci_dev->cci_master_info[MASTER_1].rd_done); + } + if ((irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE_BMSK) && + (!rd_done_th_assert)) { + cci_dev->cci_master_info[MASTER_1].status = 0; + rd_done_th_assert = true; + if (cci_dev->is_burst_read) + complete( + &cci_dev->cci_master_info[MASTER_1].th_complete); + complete(&cci_dev->cci_master_info[MASTER_1].rd_done); + } + if ((irq_status1 & CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD) && + (!rd_done_th_assert)) { + cci_dev->cci_master_info[MASTER_1].status = 0; + complete(&cci_dev->cci_master_info[MASTER_1].th_complete); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT_BMSK) { + struct cam_cci_master_info *cci_master_info; + + cci_master_info = &cci_dev->cci_master_info[MASTER_1]; + spin_lock_irqsave( + &cci_dev->cci_master_info[MASTER_1].lock_q[QUEUE_0], + flags); + atomic_set(&cci_master_info->q_free[QUEUE_0], 0); + cci_master_info->status = 0; + if (atomic_read(&cci_master_info->done_pending[QUEUE_0]) == 1) { + complete(&cci_master_info->report_q[QUEUE_0]); + atomic_set(&cci_master_info->done_pending[QUEUE_0], 0); + } + spin_unlock_irqrestore( + &cci_dev->cci_master_info[MASTER_1].lock_q[QUEUE_0], + flags); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT_BMSK) { + struct cam_cci_master_info *cci_master_info; + + cci_master_info = &cci_dev->cci_master_info[MASTER_1]; + spin_lock_irqsave( + &cci_dev->cci_master_info[MASTER_1].lock_q[QUEUE_1], + flags); + atomic_set(&cci_master_info->q_free[QUEUE_1], 0); + cci_master_info->status = 0; + if (atomic_read(&cci_master_info->done_pending[QUEUE_1]) == 1) { + complete(&cci_master_info->report_q[QUEUE_1]); + atomic_set(&cci_master_info->done_pending[QUEUE_1], 0); + } + spin_unlock_irqrestore( + &cci_dev->cci_master_info[MASTER_1].lock_q[QUEUE_1], + flags); + } + if (irq_status1 & CCI_IRQ_STATUS_1_I2C_M0_RD_PAUSE) + CAM_DBG(CAM_CCI, "RD_PAUSE ON MASTER_0"); + + if (irq_status1 & CCI_IRQ_STATUS_1_I2C_M1_RD_PAUSE) + CAM_DBG(CAM_CCI, "RD_PAUSE ON MASTER_1"); + + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK_BMSK) { + cci_dev->cci_master_info[MASTER_0].reset_pending = true; + cam_io_w_mb(CCI_M0_RESET_RMSK, + base + CCI_RESET_CMD_ADDR); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK_BMSK) { + cci_dev->cci_master_info[MASTER_1].reset_pending = true; + cam_io_w_mb(CCI_M1_RESET_RMSK, + base + CCI_RESET_CMD_ADDR); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_ERROR_BMSK) { + cci_dev->cci_master_info[MASTER_0].status = -EINVAL; + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERROR_BMSK) { + CAM_ERR(CAM_CCI, "Base:%pK, M0_Q0 NACK ERROR: 0x%x", + base, irq_status0); + cam_cci_dump_registers(cci_dev, MASTER_0, + QUEUE_0); + complete_all(&cci_dev->cci_master_info[MASTER_0] + .report_q[QUEUE_0]); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERROR_BMSK) { + CAM_ERR(CAM_CCI, "Base:%pK, M0_Q1 NACK ERROR: 0x%x", + base, irq_status0); + cam_cci_dump_registers(cci_dev, MASTER_0, + QUEUE_1); + complete_all(&cci_dev->cci_master_info[MASTER_0] + .report_q[QUEUE_1]); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_ERROR_BMSK) + CAM_ERR(CAM_CCI, + "Base:%pK, M0 QUEUE_OVER/UNDER_FLOW OR CMD ERR: 0x%x", + base, irq_status0); + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_RD_ERROR_BMSK) + CAM_ERR(CAM_CCI, + "Base: %pK, M0 RD_OVER/UNDER_FLOW ERROR: 0x%x", + base, irq_status0); + cam_io_w_mb(CCI_M0_HALT_REQ_RMSK, base + CCI_HALT_REQ_ADDR); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_ERROR_BMSK) { + cci_dev->cci_master_info[MASTER_1].status = -EINVAL; + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERROR_BMSK) { + CAM_ERR(CAM_CCI, "Base:%pK, M1_Q0 NACK ERROR: 0x%x", + base, irq_status0); + cam_cci_dump_registers(cci_dev, MASTER_1, + QUEUE_0); + complete_all(&cci_dev->cci_master_info[MASTER_1] + .report_q[QUEUE_0]); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERROR_BMSK) { + CAM_ERR(CAM_CCI, "Base:%pK, M1_Q1 NACK ERROR: 0x%x", + base, irq_status0); + cam_cci_dump_registers(cci_dev, MASTER_1, + QUEUE_1); + complete_all(&cci_dev->cci_master_info[MASTER_1] + .report_q[QUEUE_1]); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_ERROR_BMSK) + CAM_ERR(CAM_CCI, + "Base:%pK, M1 QUEUE_OVER_UNDER_FLOW OR CMD ERROR:0x%x", + base, irq_status0); + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_RD_ERROR_BMSK) + CAM_ERR(CAM_CCI, + "Base:%pK, M1 RD_OVER/UNDER_FLOW ERROR: 0x%x", + base, irq_status0); + cam_io_w_mb(CCI_M1_HALT_REQ_RMSK, base + CCI_HALT_REQ_ADDR); + } + + cam_io_w_mb(irq_status0, base + CCI_IRQ_CLEAR_0_ADDR); + + reg_bmsk = CCI_IRQ_MASK_1_RMSK; + if ((irq_status1 & CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD) && + !(irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE_BMSK)) { + reg_bmsk &= ~CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD; + spin_lock_irqsave(&cci_dev->lock_status, flags); + cci_dev->irqs_disabled |= + CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD; + spin_unlock_irqrestore(&cci_dev->lock_status, flags); + } + + if ((irq_status1 & CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD) && + !(irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE_BMSK)) { + reg_bmsk &= ~CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD; + spin_lock_irqsave(&cci_dev->lock_status, flags); + cci_dev->irqs_disabled |= + CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD; + spin_unlock_irqrestore(&cci_dev->lock_status, flags); + } + + if (reg_bmsk != CCI_IRQ_MASK_1_RMSK) { + cam_io_w_mb(reg_bmsk, base + CCI_IRQ_MASK_1_ADDR); + CAM_DBG(CAM_CCI, "Updating the reg mask for irq1: 0x%x", + reg_bmsk); + } else if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE_BMSK || + irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE_BMSK) { + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE_BMSK) { + spin_lock_irqsave(&cci_dev->lock_status, flags); + if (cci_dev->irqs_disabled & + CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD) { + irq_update_rd_done |= + CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD; + cci_dev->irqs_disabled &= + ~CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD; + } + spin_unlock_irqrestore(&cci_dev->lock_status, flags); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE_BMSK) { + spin_lock_irqsave(&cci_dev->lock_status, flags); + if (cci_dev->irqs_disabled & + CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD) { + irq_update_rd_done |= + CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD; + cci_dev->irqs_disabled &= + ~CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD; + } + spin_unlock_irqrestore(&cci_dev->lock_status, flags); + } + } + + if (irq_update_rd_done != 0) { + irq_update_rd_done |= cam_io_r_mb(base + CCI_IRQ_MASK_1_ADDR); + cam_io_w_mb(irq_update_rd_done, base + CCI_IRQ_MASK_1_ADDR); + } + + + cam_io_w_mb(irq_status1, base + CCI_IRQ_CLEAR_1_ADDR); + cam_io_w_mb(0x1, base + CCI_IRQ_GLOBAL_CLEAR_CMD_ADDR); + return IRQ_HANDLED; +} + +static int cam_cci_irq_routine(struct v4l2_subdev *sd, u32 status, + bool *handled) +{ + struct cci_device *cci_dev = v4l2_get_subdevdata(sd); + irqreturn_t ret; + struct cam_hw_soc_info *soc_info = + &cci_dev->soc_info; + + ret = cam_cci_irq(soc_info->irq_line->start, cci_dev); + *handled = true; + return 0; +} + +static struct v4l2_subdev_core_ops cci_subdev_core_ops = { + .ioctl = cam_cci_subdev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = cam_cci_subdev_compat_ioctl, +#endif + .interrupt_service_routine = cam_cci_irq_routine, +}; + +static const struct v4l2_subdev_ops cci_subdev_ops = { + .core = &cci_subdev_core_ops, +}; + +static const struct v4l2_subdev_internal_ops cci_subdev_intern_ops; + +static struct v4l2_file_operations cci_v4l2_subdev_fops; + +static long cam_cci_subdev_do_ioctl( + struct file *file, unsigned int cmd, void *arg) +{ + struct video_device *vdev = video_devdata(file); + struct v4l2_subdev *sd = vdev_to_v4l2_subdev(vdev); + + return cam_cci_subdev_ioctl(sd, cmd, NULL); +} + +static long cam_cci_subdev_fops_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + return video_usercopy(file, cmd, arg, cam_cci_subdev_do_ioctl); +} + +#ifdef CONFIG_COMPAT +static long cam_cci_subdev_fops_compat_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + struct video_device *vdev = video_devdata(file); + struct v4l2_subdev *sd = vdev_to_v4l2_subdev(vdev); + + return v4l2_subdev_call(sd, core, ioctl, cmd, NULL); +} +#endif + +static int cam_cci_get_debug(void *data, u64 *val) +{ + struct cci_device *cci_dev = (struct cci_device *)data; + + *val = cci_dev->dump_en; + + return 0; +} + +static int cam_cci_set_debug(void *data, u64 val) +{ + struct cci_device *cci_dev = (struct cci_device *)data; + + cci_dev->dump_en = val; + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(cam_cci_debug, + cam_cci_get_debug, + cam_cci_set_debug, "%16llu\n"); + +static int cam_cci_create_debugfs_entry(struct cci_device *cci_dev) +{ + int rc = 0; + struct dentry *dbgfileptr = NULL; + + if (!debugfs_root) { + dbgfileptr = debugfs_create_dir("cam_cci", NULL); + if (!dbgfileptr) { + CAM_ERR(CAM_CCI, "debugfs directory creation fail"); + rc = -ENOENT; + goto end; + } + debugfs_root = dbgfileptr; + } + + if (cci_dev->soc_info.index == 0) { + dbgfileptr = debugfs_create_file("en_dump_cci0", 0644, + debugfs_root, cci_dev, &cam_cci_debug); + if (IS_ERR(dbgfileptr)) { + if (PTR_ERR(dbgfileptr) == -ENODEV) + CAM_WARN(CAM_CCI, "DebugFS not enabled"); + else { + rc = PTR_ERR(dbgfileptr); + goto end; + } + } + } else { + dbgfileptr = debugfs_create_file("en_dump_cci1", 0644, + debugfs_root, cci_dev, &cam_cci_debug); + if (IS_ERR(dbgfileptr)) { + if (PTR_ERR(dbgfileptr) == -ENODEV) + CAM_WARN(CAM_CCI, "DebugFS not enabled"); + else { + rc = PTR_ERR(dbgfileptr); + goto end; + } + } + } +end: + return rc; +} + +static int cam_cci_platform_probe(struct platform_device *pdev) +{ + struct cam_cpas_register_params cpas_parms; + struct cci_device *new_cci_dev; + struct cam_hw_soc_info *soc_info = NULL; + int rc = 0; + + new_cci_dev = kzalloc(sizeof(struct cci_device), + GFP_KERNEL); + if (!new_cci_dev) + return -ENOMEM; + + soc_info = &new_cci_dev->soc_info; + + new_cci_dev->v4l2_dev_str.pdev = pdev; + + soc_info->pdev = pdev; + soc_info->dev = &pdev->dev; + soc_info->dev_name = pdev->name; + + rc = cam_cci_parse_dt_info(pdev, new_cci_dev); + if (rc < 0) { + CAM_ERR(CAM_CCI, "Resource get Failed: %d", rc); + goto cci_no_resource; + } + + new_cci_dev->v4l2_dev_str.internal_ops = + &cci_subdev_intern_ops; + new_cci_dev->v4l2_dev_str.ops = + &cci_subdev_ops; + strlcpy(new_cci_dev->device_name, CAMX_CCI_DEV_NAME, + sizeof(new_cci_dev->device_name)); + new_cci_dev->v4l2_dev_str.name = + new_cci_dev->device_name; + new_cci_dev->v4l2_dev_str.sd_flags = V4L2_SUBDEV_FL_HAS_EVENTS; + new_cci_dev->v4l2_dev_str.ent_function = + CAM_CCI_DEVICE_TYPE; + new_cci_dev->v4l2_dev_str.token = + new_cci_dev; + + rc = cam_register_subdev(&(new_cci_dev->v4l2_dev_str)); + if (rc < 0) { + CAM_ERR(CAM_CCI, "Fail with cam_register_subdev"); + goto cci_no_resource; + } + + platform_set_drvdata(pdev, &(new_cci_dev->v4l2_dev_str.sd)); + v4l2_set_subdevdata(&new_cci_dev->v4l2_dev_str.sd, new_cci_dev); + if (soc_info->index >= MAX_CCI) { + CAM_ERR(CAM_CCI, "Invalid index: %d max supported:%d", + soc_info->index, MAX_CCI-1); + goto cci_no_resource; + } + + g_cci_subdev[soc_info->index] = &new_cci_dev->v4l2_dev_str.sd; + mutex_init(&(new_cci_dev->init_mutex)); + CAM_INFO(CAM_CCI, "Device Type :%d", soc_info->index); + + cam_register_subdev_fops(&cci_v4l2_subdev_fops); + cci_v4l2_subdev_fops.unlocked_ioctl = cam_cci_subdev_fops_ioctl; +#ifdef CONFIG_COMPAT + cci_v4l2_subdev_fops.compat_ioctl32 = + cam_cci_subdev_fops_compat_ioctl; +#endif + + cpas_parms.cam_cpas_client_cb = NULL; + cpas_parms.cell_index = soc_info->index; + cpas_parms.dev = &pdev->dev; + cpas_parms.userdata = new_cci_dev; + strlcpy(cpas_parms.identifier, "cci", CAM_HW_IDENTIFIER_LENGTH); + rc = cam_cpas_register_client(&cpas_parms); + if (rc) { + CAM_ERR(CAM_CCI, "CPAS registration failed"); + goto cci_unregister_subdev; + } + CAM_DBG(CAM_CCI, "CPAS registration successful handle=%d", + cpas_parms.client_handle); + new_cci_dev->cpas_handle = cpas_parms.client_handle; + + rc = cam_cci_create_debugfs_entry(new_cci_dev); + if (rc) { + CAM_WARN(CAM_CCI, "debugfs creation failed"); + rc = 0; + } + return rc; + +cci_unregister_subdev: + cam_unregister_subdev(&(new_cci_dev->v4l2_dev_str)); +cci_no_resource: + kfree(new_cci_dev); + return rc; +} + +static int cam_cci_device_remove(struct platform_device *pdev) +{ + struct v4l2_subdev *subdev = platform_get_drvdata(pdev); + struct cci_device *cci_dev = + v4l2_get_subdevdata(subdev); + + cam_cpas_unregister_client(cci_dev->cpas_handle); + debugfs_remove_recursive(debugfs_root); + cam_cci_soc_remove(pdev, cci_dev); + devm_kfree(&pdev->dev, cci_dev); + return 0; +} + +static const struct of_device_id cam_cci_dt_match[] = { + {.compatible = "qcom,cci"}, + {} +}; + +MODULE_DEVICE_TABLE(of, cam_cci_dt_match); + +static struct platform_driver cci_driver = { + .probe = cam_cci_platform_probe, + .remove = cam_cci_device_remove, + .driver = { + .name = CAMX_CCI_DEV_NAME, + .owner = THIS_MODULE, + .of_match_table = cam_cci_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int cam_cci_assign_fops(void) +{ + struct v4l2_subdev *sd; + int i = 0; + + for (; i < MAX_CCI; i++) { + sd = g_cci_subdev[i]; + if (!sd) + return 0; + if (!(sd->devnode)) { + CAM_ERR(CAM_CCI, + "Invalid dev node:%pK offset: %d", + sd->devnode, i); + return -EINVAL; + } + sd->devnode->fops = &cci_v4l2_subdev_fops; + } + + return 0; +} + +static int __init cam_cci_late_init(void) +{ + return cam_cci_assign_fops(); +} + +static int __init cam_cci_init_module(void) +{ + return platform_driver_register(&cci_driver); +} + +static void __exit cam_cci_exit_module(void) +{ + platform_driver_unregister(&cci_driver); +} + +module_init(cam_cci_init_module); +late_initcall(cam_cci_late_init); +module_exit(cam_cci_exit_module); +MODULE_DESCRIPTION("MSM CCI driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..00dabdfd625610267c3226db0726532e058afa08 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h @@ -0,0 +1,318 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CCI_DEV_H_ +#define _CAM_CCI_DEV_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_subdev.h" +#include +#include "cam_cci_hwreg.h" +#include "cam_soc_util.h" +#include "cam_debug_util.h" +#include "cam_req_mgr_workq.h" + +#define V4L2_IDENT_CCI 50005 +#define CCI_I2C_QUEUE_0_SIZE 128 +#define CCI_I2C_QUEUE_1_SIZE 32 +#define CCI_I2C_QUEUE_0_SIZE_V_1_2 64 +#define CCI_I2C_QUEUE_1_SIZE_V_1_2 16 +#define CYCLES_PER_MICRO_SEC_DEFAULT 4915 +#define CCI_MAX_DELAY 1000000 + +#define CCI_TIMEOUT msecs_to_jiffies(1500) + +#define NUM_MASTERS 2 +#define NUM_QUEUES 2 + +#define CCI_PINCTRL_STATE_DEFAULT "cci_default" +#define CCI_PINCTRL_STATE_SLEEP "cci_suspend" + +#define CCI_NUM_CLK_MAX 16 +#define CCI_NUM_CLK_CASES 5 +#define CCI_CLK_SRC_NAME "cci_src_clk" +#define MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_10 10 +#define MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_11 11 +#define BURST_MIN_FREE_SIZE 8 +#define MAX_LRME_V4l2_EVENTS 30 + +/* Max bytes that can be read per CCI read transaction */ +#define CCI_READ_MAX 256 +#define CCI_READ_MAX_V_1_2 0xE +#define CCI_I2C_READ_MAX_RETRIES 3 +#define CCI_I2C_MAX_READ 8192 +#define CCI_I2C_MAX_WRITE 8192 +#define CCI_I2C_MAX_BYTE_COUNT 65535 + +#define CAMX_CCI_DEV_NAME "cam-cci-driver" + +#define MAX_CCI 2 + +#define PRIORITY_QUEUE (QUEUE_0) +#define SYNC_QUEUE (QUEUE_1) + +#define CAM_CCI_NACK_DUMP_EN BIT(1) +#define CAM_CCI_TIMEOUT_DUMP_EN BIT(2) + +#define CCI_VERSION_1_2_9 0x10020009 + +enum cci_i2c_sync { + MSM_SYNC_DISABLE, + MSM_SYNC_ENABLE, +}; + +enum cam_cci_cmd_type { + MSM_CCI_INIT, + MSM_CCI_RELEASE, + MSM_CCI_SET_SID, + MSM_CCI_SET_FREQ, + MSM_CCI_SET_SYNC_CID, + MSM_CCI_I2C_READ, + MSM_CCI_I2C_WRITE, + MSM_CCI_I2C_WRITE_SEQ, + MSM_CCI_I2C_WRITE_BURST, + MSM_CCI_I2C_WRITE_ASYNC, + MSM_CCI_GPIO_WRITE, + MSM_CCI_I2C_WRITE_SYNC, + MSM_CCI_I2C_WRITE_SYNC_BLOCK, +}; + +enum cci_i2c_queue_t { + QUEUE_0, + QUEUE_1, + QUEUE_INVALID, +}; + +struct cam_cci_wait_sync_cfg { + uint16_t cid; + int16_t csid; + uint16_t line; + uint16_t delay; +}; + +struct cam_cci_gpio_cfg { + uint16_t gpio_queue; + uint16_t i2c_queue; +}; + +struct cam_cci_read_cfg { + uint32_t addr; + uint16_t addr_type; + uint8_t *data; + uint16_t num_byte; + uint16_t data_type; +}; + +struct cam_cci_i2c_queue_info { + uint32_t max_queue_size; + uint32_t report_id; + uint32_t irq_en; + uint32_t capture_rep_data; +}; + +struct cam_cci_master_info { + uint32_t status; + atomic_t q_free[NUM_QUEUES]; + uint8_t q_lock[NUM_QUEUES]; + uint8_t reset_pending; + struct mutex mutex; + struct completion reset_complete; + struct completion rd_done; + struct completion th_complete; + struct mutex mutex_q[NUM_QUEUES]; + struct completion report_q[NUM_QUEUES]; + atomic_t done_pending[NUM_QUEUES]; + spinlock_t lock_q[NUM_QUEUES]; + spinlock_t freq_cnt; + struct semaphore master_sem; + bool is_first_req; + uint16_t freq_ref_cnt; +}; + +struct cam_cci_clk_params_t { + uint16_t hw_thigh; + uint16_t hw_tlow; + uint16_t hw_tsu_sto; + uint16_t hw_tsu_sta; + uint16_t hw_thd_dat; + uint16_t hw_thd_sta; + uint16_t hw_tbuf; + uint8_t hw_scl_stretch_en; + uint8_t hw_trdhld; + uint8_t hw_tsp; + uint32_t cci_clk_src; +}; + +enum cam_cci_state_t { + CCI_STATE_ENABLED, + CCI_STATE_DISABLED, +}; + +/** + * struct cci_device + * @pdev: Platform device + * @subdev: V4L2 sub device + * @base: Base address of CCI device + * @hw_version: Hardware version + * @ref_count: Reference Count + * @cci_state: CCI state machine + * @num_clk: Number of CCI clock + * @cci_clk: CCI clock structure + * @cci_clk_info: CCI clock information + * @cam_cci_i2c_queue_info: CCI queue information + * @i2c_freq_mode: I2C frequency of operations + * @cci_clk_params: CCI hw clk params + * @cci_gpio_tbl: CCI GPIO table + * @cci_gpio_tbl_size: GPIO table size + * @cci_pinctrl: Pinctrl structure + * @cci_pinctrl_status: CCI pinctrl status + * @cci_clk_src: CCI clk src rate + * @cci_vreg: CCI regulator structure + * @cci_reg_ptr: CCI individual regulator structure + * @regulator_count: Regulator count + * @support_seq_write: Set this flag when sequential write is enabled + * @write_wq: Work queue structure + * @valid_sync: Is it a valid sync with CSID + * @v4l2_dev_str: V4L2 device structure + * @cci_wait_sync_cfg: CCI sync config + * @cycles_per_us: Cycles per micro sec + * @payload_size: CCI packet payload size + * @irq_status1: Store irq_status1 to be cleared after + * draining FIFO buffer for burst read + * @lock_status: to protect changes to irq_status1 + * @is_burst_read: Flag to determine if we are performing + * a burst read operation or not + * @irqs_disabled: Mask for IRQs that are disabled + * @init_mutex: Mutex for maintaining refcount for attached + * devices to cci during init/deinit. + * @dump_en: To enable the selective dump + */ +struct cci_device { + struct v4l2_subdev subdev; + struct cam_hw_soc_info soc_info; + uint32_t hw_version; + uint8_t ref_count; + enum cam_cci_state_t cci_state; + struct cam_cci_i2c_queue_info + cci_i2c_queue_info[NUM_MASTERS][NUM_QUEUES]; + struct cam_cci_master_info cci_master_info[NUM_MASTERS]; + enum i2c_freq_mode i2c_freq_mode[NUM_MASTERS]; + struct cam_cci_clk_params_t cci_clk_params[I2C_MAX_MODES]; + struct msm_pinctrl_info cci_pinctrl; + uint8_t cci_pinctrl_status; + uint8_t support_seq_write; + struct workqueue_struct *write_wq[MASTER_MAX]; + struct cam_cci_wait_sync_cfg cci_wait_sync_cfg; + uint8_t valid_sync; + struct cam_subdev v4l2_dev_str; + uint32_t cycles_per_us; + int32_t clk_level_index; + uint8_t payload_size; + char device_name[20]; + uint32_t cpas_handle; + uint32_t irq_status1; + spinlock_t lock_status; + bool is_burst_read; + uint32_t irqs_disabled; + struct mutex init_mutex; + uint64_t dump_en; +}; + +enum cam_cci_i2c_cmd_type { + CCI_I2C_SET_PARAM_CMD = 1, + CCI_I2C_WAIT_CMD, + CCI_I2C_WAIT_SYNC_CMD, + CCI_I2C_WAIT_GPIO_EVENT_CMD, + CCI_I2C_TRIG_I2C_EVENT_CMD, + CCI_I2C_LOCK_CMD, + CCI_I2C_UNLOCK_CMD, + CCI_I2C_REPORT_CMD, + CCI_I2C_WRITE_CMD, + CCI_I2C_READ_CMD, + CCI_I2C_WRITE_DISABLE_P_CMD, + CCI_I2C_READ_DISABLE_P_CMD, + CCI_I2C_WRITE_CMD2, + CCI_I2C_WRITE_CMD3, + CCI_I2C_REPEAT_CMD, + CCI_I2C_INVALID_CMD, +}; + +enum cam_cci_gpio_cmd_type { + CCI_GPIO_SET_PARAM_CMD = 1, + CCI_GPIO_WAIT_CMD, + CCI_GPIO_WAIT_SYNC_CMD, + CCI_GPIO_WAIT_GPIO_IN_EVENT_CMD, + CCI_GPIO_WAIT_I2C_Q_TRIG_EVENT_CMD, + CCI_GPIO_OUT_CMD, + CCI_GPIO_TRIG_EVENT_CMD, + CCI_GPIO_REPORT_CMD, + CCI_GPIO_REPEAT_CMD, + CCI_GPIO_CONTINUE_CMD, + CCI_GPIO_INVALID_CMD, +}; + +struct cam_sensor_cci_client { + struct v4l2_subdev *cci_subdev; + uint32_t freq; + enum i2c_freq_mode i2c_freq_mode; + enum cci_i2c_master_t cci_i2c_master; + uint16_t sid; + uint16_t cid; + uint32_t timeout; + uint16_t retries; + uint16_t id_map; + uint16_t cci_device; +}; + +struct cam_cci_ctrl { + int32_t status; + struct cam_sensor_cci_client *cci_info; + enum cam_cci_cmd_type cmd; + union { + struct cam_sensor_i2c_reg_setting cci_i2c_write_cfg; + struct cam_cci_read_cfg cci_i2c_read_cfg; + struct cam_cci_wait_sync_cfg cci_wait_sync_cfg; + struct cam_cci_gpio_cfg gpio_cfg; + } cfg; +}; + +struct cci_write_async { + struct cci_device *cci_dev; + struct cam_cci_ctrl c_ctrl; + enum cci_i2c_queue_t queue; + struct work_struct work; + ktime_t workq_scheduled_ts; + enum cci_i2c_sync sync_en; +}; + +irqreturn_t cam_cci_irq(int irq_num, void *data); + +struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index); +void cam_cci_dump_registers(struct cci_device *cci_dev, + enum cci_i2c_master_t master, enum cci_i2c_queue_t queue); + +#define VIDIOC_MSM_CCI_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 23, struct cam_cci_ctrl) + +#endif /* _CAM_CCI_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_hwreg.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_hwreg.h new file mode 100644 index 0000000000000000000000000000000000000000..069a1ac01c1fd23cfdcb6fd328e3ea01a8326fe1 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_hwreg.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2012-2015, 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CCI_HWREG_ +#define _CAM_CCI_HWREG_ + +#define CCI_HW_VERSION_ADDR 0x00000000 +#define CCI_RESET_CMD_ADDR 0x00000004 +#define CCI_RESET_CMD_RMSK 0x0f73f3f7 +#define CCI_M0_RESET_RMSK 0x3F1 +#define CCI_M1_RESET_RMSK 0x3F001 +#define CCI_QUEUE_START_ADDR 0x00000008 +#define CCI_SET_CID_SYNC_TIMER_ADDR 0x00000010 +#define CCI_SET_CID_SYNC_TIMER_OFFSET 0x00000004 +#define CCI_I2C_M0_SCL_CTL_ADDR 0x00000100 +#define CCI_I2C_M0_SDA_CTL_0_ADDR 0x00000104 +#define CCI_I2C_M0_SDA_CTL_1_ADDR 0x00000108 +#define CCI_I2C_M0_SDA_CTL_2_ADDR 0x0000010c +#define CCI_I2C_M0_READ_DATA_ADDR 0x00000118 +#define CCI_I2C_M0_MISC_CTL_ADDR 0x00000110 +#define CCI_I2C_M0_READ_BUF_LEVEL_ADDR 0x0000011C +#define CCI_HALT_REQ_ADDR 0x00000034 +#define CCI_M0_HALT_REQ_RMSK 0x1 +#define CCI_M1_HALT_REQ_RMSK 0x2 +#define CCI_I2C_M1_SCL_CTL_ADDR 0x00000200 +#define CCI_I2C_M1_SDA_CTL_0_ADDR 0x00000204 +#define CCI_I2C_M1_SDA_CTL_1_ADDR 0x00000208 +#define CCI_I2C_M1_SDA_CTL_2_ADDR 0x0000020c +#define CCI_I2C_M1_MISC_CTL_ADDR 0x00000210 +#define CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR 0x00000304 +#define CCI_I2C_M0_Q0_CUR_CMD_ADDR 0x00000308 +#define CCI_I2C_M0_Q0_REPORT_STATUS_ADDR 0x0000030c +#define CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR 0x00000300 +#define CCI_I2C_M0_Q0_LOAD_DATA_ADDR 0x00000310 +#define CCI_IRQ_MASK_0_ADDR 0x00000c04 +#define CCI_IRQ_MASK_0_RMSK 0x7fff7ff7 +#define CCI_IRQ_MASK_1_ADDR 0x00000c10 +#define CCI_IRQ_MASK_1_RMSK 0x00110000 +#define CCI_IRQ_CLEAR_0_ADDR 0x00000c08 +#define CCI_IRQ_CLEAR_1_ADDR 0x00000c14 +#define CCI_IRQ_STATUS_0_ADDR 0x00000c0c +#define CCI_IRQ_STATUS_1_ADDR 0x00000c18 +#define CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK_BMSK 0x4000000 +#define CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK_BMSK 0x2000000 +#define CCI_IRQ_STATUS_0_RST_DONE_ACK_BMSK 0x1000000 +#define CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT_BMSK 0x100000 +#define CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT_BMSK 0x10000 +#define CCI_IRQ_STATUS_0_I2C_M1_RD_DONE_BMSK 0x1000 +#define CCI_IRQ_STATUS_1_I2C_M1_RD_THRESHOLD 0x100000 +#define CCI_IRQ_STATUS_1_I2C_M1_RD_PAUSE 0x200000 +#define CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT_BMSK 0x100 +#define CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT_BMSK 0x10 +#define CCI_IRQ_STATUS_0_I2C_M0_ERROR_BMSK 0x18000EE6 +#define CCI_IRQ_STATUS_0_I2C_M1_ERROR_BMSK 0x60EE6000 +#define CCI_IRQ_STATUS_0_I2C_M0_NACK_ERROR_BMSK 0x18000000 +#define CCI_IRQ_STATUS_0_I2C_M1_NACK_ERROR_BMSK 0x60000000 +#define CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERROR_BMSK 0x8000000 +#define CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERROR_BMSK 0x10000000 +#define CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERROR_BMSK 0x20000000 +#define CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERROR_BMSK 0x40000000 +#define CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_ERROR_BMSK 0xEE0 +#define CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_ERROR_BMSK 0xEE0000 +#define CCI_IRQ_STATUS_0_I2C_M0_RD_ERROR_BMSK 0x6 +#define CCI_IRQ_STATUS_0_I2C_M1_RD_ERROR_BMSK 0x6000 +#define CCI_IRQ_STATUS_0_I2C_M0_RD_DONE_BMSK 0x1 +#define CCI_IRQ_STATUS_1_I2C_M0_RD_THRESHOLD 0x10000 +#define CCI_IRQ_STATUS_1_I2C_M0_RD_PAUSE 0x20000 +#define CCI_I2C_M0_RD_THRESHOLD_ADDR 0x00000120 +#define CCI_I2C_M1_RD_THRESHOLD_ADDR 0x00000220 +#define CCI_I2C_RD_THRESHOLD_VALUE 0x30 +#define CCI_IRQ_GLOBAL_CLEAR_CMD_ADDR 0x00000c00 + +#define DEBUG_TOP_REG_START 0x0 +#define DEBUG_TOP_REG_COUNT 14 +#define DEBUG_MASTER_REG_START 0x100 +#define DEBUG_MASTER_REG_COUNT 9 +#define DEBUG_MASTER_QUEUE_REG_START 0x300 +#define DEBUG_MASTER_QUEUE_REG_COUNT 7 +#define DEBUG_INTR_REG_START 0xC00 +#define DEBUG_INTR_REG_COUNT 7 +#endif /* _CAM_CCI_HWREG_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..05f9e1240bad770abeacc6409cb7dab229e0677e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include "cam_cci_dev.h" +#include "cam_cci_core.h" + +int cam_cci_init(struct v4l2_subdev *sd, + struct cam_cci_ctrl *c_ctrl) +{ + uint8_t i = 0, j = 0; + int32_t rc = 0; + struct cci_device *cci_dev; + enum cci_i2c_master_t master = c_ctrl->cci_info->cci_i2c_master; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + struct cam_hw_soc_info *soc_info = NULL; + void __iomem *base = NULL; + uint32_t max_queue_0_size = 0, max_queue_1_size = 0; + + cci_dev = v4l2_get_subdevdata(sd); + if (!cci_dev || !c_ctrl) { + CAM_ERR(CAM_CCI, "failed: invalid params %pK %pK", + cci_dev, c_ctrl); + rc = -EINVAL; + return rc; + } + + soc_info = &cci_dev->soc_info; + base = soc_info->reg_map[0].mem_base; + + if (!soc_info || !base) { + CAM_ERR(CAM_CCI, "failed: invalid params %pK %pK", + soc_info, base); + rc = -EINVAL; + return rc; + } + + CAM_DBG(CAM_CCI, "Base address %pK", base); + + if (cci_dev->ref_count++) { + CAM_DBG(CAM_CCI, "ref_count %d", cci_dev->ref_count); + CAM_DBG(CAM_CCI, "master %d", master); + if (master < MASTER_MAX && master >= 0) { + mutex_lock(&cci_dev->cci_master_info[master].mutex); + flush_workqueue(cci_dev->write_wq[master]); + /* Re-initialize the completion */ + reinit_completion( + &cci_dev->cci_master_info[master].reset_complete); + reinit_completion( + &cci_dev->cci_master_info[master].rd_done); + for (i = 0; i < NUM_QUEUES; i++) + reinit_completion( + &cci_dev->cci_master_info[master].report_q[i]); + /* Set reset pending flag to true */ + cci_dev->cci_master_info[master].reset_pending = true; + /* Set proper mask to RESET CMD address */ + if (master == MASTER_0) + cam_io_w_mb(CCI_M0_RESET_RMSK, + base + CCI_RESET_CMD_ADDR); + else + cam_io_w_mb(CCI_M1_RESET_RMSK, + base + CCI_RESET_CMD_ADDR); + /* wait for reset done irq */ + rc = wait_for_completion_timeout( + &cci_dev->cci_master_info[master].reset_complete, + CCI_TIMEOUT); + if (rc <= 0) + CAM_ERR(CAM_CCI, "wait failed %d", rc); + mutex_unlock(&cci_dev->cci_master_info[master].mutex); + } + return 0; + } + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_LOWSVS_VOTE; + axi_vote.num_paths = 1; + axi_vote.axi_path[0].path_data_type = + CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = + CAM_AXI_TRANSACTION_WRITE; + axi_vote.axi_path[0].camnoc_bw = + CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + + rc = cam_cpas_start(cci_dev->cpas_handle, + &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_CCI, "CPAS start failed"); + cci_dev->ref_count--; + return rc; + } + + cam_cci_get_clk_rates(cci_dev, c_ctrl); + + /* Re-initialize the completion */ + reinit_completion(&cci_dev->cci_master_info[master].reset_complete); + reinit_completion(&cci_dev->cci_master_info[master].rd_done); + for (i = 0; i < NUM_QUEUES; i++) + reinit_completion( + &cci_dev->cci_master_info[master].report_q[i]); + + /* Enable Regulators and IRQ*/ + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_LOWSVS_VOTE, true); + if (rc < 0) { + CAM_DBG(CAM_CCI, "request platform resources failed"); + goto platform_enable_failed; + } + + cci_dev->hw_version = cam_io_r_mb(base + + CCI_HW_VERSION_ADDR); + CAM_DBG(CAM_CCI, "hw_version = 0x%x", cci_dev->hw_version); + + cci_dev->payload_size = + MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_11; + cci_dev->support_seq_write = 1; + + if (cci_dev->hw_version == CCI_VERSION_1_2_9) { + max_queue_0_size = CCI_I2C_QUEUE_0_SIZE_V_1_2; + max_queue_1_size = CCI_I2C_QUEUE_1_SIZE_V_1_2; + } else { + max_queue_0_size = CCI_I2C_QUEUE_0_SIZE; + max_queue_1_size = CCI_I2C_QUEUE_1_SIZE; + } + + for (i = 0; i < NUM_MASTERS; i++) { + for (j = 0; j < NUM_QUEUES; j++) { + if (j == QUEUE_0) + cci_dev->cci_i2c_queue_info[i][j].max_queue_size + = max_queue_0_size; + else + cci_dev->cci_i2c_queue_info[i][j].max_queue_size + = max_queue_1_size; + + CAM_DBG(CAM_CCI, "CCI Master[%d] :: Q0 : %d Q1 : %d", i, + cci_dev->cci_i2c_queue_info[i][j].max_queue_size, + cci_dev->cci_i2c_queue_info[i][j].max_queue_size); + } + } + + cci_dev->cci_master_info[master].reset_pending = true; + cam_io_w_mb(CCI_RESET_CMD_RMSK, base + + CCI_RESET_CMD_ADDR); + cam_io_w_mb(0x1, base + CCI_RESET_CMD_ADDR); + rc = wait_for_completion_timeout( + &cci_dev->cci_master_info[master].reset_complete, + CCI_TIMEOUT); + if (rc <= 0) { + CAM_ERR(CAM_CCI, "wait_for_completion_timeout"); + if (rc == 0) + rc = -ETIMEDOUT; + goto reset_complete_failed; + } + for (i = 0; i < MASTER_MAX; i++) + cci_dev->i2c_freq_mode[i] = I2C_MAX_MODES; + cam_io_w_mb(CCI_IRQ_MASK_0_RMSK, + base + CCI_IRQ_MASK_0_ADDR); + cam_io_w_mb(CCI_IRQ_MASK_0_RMSK, + base + CCI_IRQ_CLEAR_0_ADDR); + cam_io_w_mb(CCI_IRQ_MASK_1_RMSK, + base + CCI_IRQ_MASK_1_ADDR); + cam_io_w_mb(CCI_IRQ_MASK_1_RMSK, + base + CCI_IRQ_CLEAR_1_ADDR); + cam_io_w_mb(0x1, base + CCI_IRQ_GLOBAL_CLEAR_CMD_ADDR); + + for (i = 0; i < MASTER_MAX; i++) { + if (!cci_dev->write_wq[i]) { + CAM_ERR(CAM_CCI, "Failed to flush write wq"); + rc = -ENOMEM; + goto reset_complete_failed; + } else { + flush_workqueue(cci_dev->write_wq[i]); + } + } + + /* Set RD FIFO threshold for M0 & M1 */ + if (cci_dev->hw_version != CCI_VERSION_1_2_9) { + cam_io_w_mb(CCI_I2C_RD_THRESHOLD_VALUE, + base + CCI_I2C_M0_RD_THRESHOLD_ADDR); + cam_io_w_mb(CCI_I2C_RD_THRESHOLD_VALUE, + base + CCI_I2C_M1_RD_THRESHOLD_ADDR); + } + + cci_dev->cci_state = CCI_STATE_ENABLED; + + return 0; + +reset_complete_failed: + cam_soc_util_disable_platform_resource(soc_info, 1, 1); + +platform_enable_failed: + cci_dev->ref_count--; + cam_cpas_stop(cci_dev->cpas_handle); + + return rc; +} + +void cam_cci_soc_remove(struct platform_device *pdev, + struct cci_device *cci_dev) +{ + struct cam_hw_soc_info *soc_info = &cci_dev->soc_info; + + cam_soc_util_release_platform_resource(soc_info); +} + +static void cam_cci_init_cci_params(struct cci_device *new_cci_dev) +{ + uint8_t i = 0, j = 0; + + for (i = 0; i < NUM_MASTERS; i++) { + new_cci_dev->cci_master_info[i].status = 0; + new_cci_dev->cci_master_info[i].is_first_req = true; + mutex_init(&new_cci_dev->cci_master_info[i].mutex); + sema_init(&new_cci_dev->cci_master_info[i].master_sem, 1); + spin_lock_init(&new_cci_dev->cci_master_info[i].freq_cnt); + init_completion( + &new_cci_dev->cci_master_info[i].reset_complete); + init_completion( + &new_cci_dev->cci_master_info[i].th_complete); + init_completion( + &new_cci_dev->cci_master_info[i].rd_done); + + for (j = 0; j < NUM_QUEUES; j++) { + mutex_init(&new_cci_dev->cci_master_info[i].mutex_q[j]); + init_completion( + &new_cci_dev->cci_master_info[i].report_q[j]); + spin_lock_init( + &new_cci_dev->cci_master_info[i].lock_q[j]); + } + } + spin_lock_init(&new_cci_dev->lock_status); +} + +static void cam_cci_init_default_clk_params(struct cci_device *cci_dev, + uint8_t index) +{ + /* default clock params are for 100Khz */ + cci_dev->cci_clk_params[index].hw_thigh = 201; + cci_dev->cci_clk_params[index].hw_tlow = 174; + cci_dev->cci_clk_params[index].hw_tsu_sto = 204; + cci_dev->cci_clk_params[index].hw_tsu_sta = 231; + cci_dev->cci_clk_params[index].hw_thd_dat = 22; + cci_dev->cci_clk_params[index].hw_thd_sta = 162; + cci_dev->cci_clk_params[index].hw_tbuf = 227; + cci_dev->cci_clk_params[index].hw_scl_stretch_en = 0; + cci_dev->cci_clk_params[index].hw_trdhld = 6; + cci_dev->cci_clk_params[index].hw_tsp = 3; + cci_dev->cci_clk_params[index].cci_clk_src = 37500000; +} + +static void cam_cci_init_clk_params(struct cci_device *cci_dev) +{ + int32_t rc = 0; + uint32_t val = 0; + uint8_t count = 0; + struct device_node *of_node = cci_dev->v4l2_dev_str.pdev->dev.of_node; + struct device_node *src_node = NULL; + + for (count = 0; count < I2C_MAX_MODES; count++) { + + if (count == I2C_STANDARD_MODE) + src_node = of_find_node_by_name(of_node, + "qcom,i2c_standard_mode"); + else if (count == I2C_FAST_MODE) + src_node = of_find_node_by_name(of_node, + "qcom,i2c_fast_mode"); + else if (count == I2C_FAST_PLUS_MODE) + src_node = of_find_node_by_name(of_node, + "qcom,i2c_fast_plus_mode"); + else + src_node = of_find_node_by_name(of_node, + "qcom,i2c_custom_mode"); + + rc = of_property_read_u32(src_node, "hw-thigh", &val); + CAM_DBG(CAM_CCI, "hw-thigh %d, rc %d", val, rc); + if (!rc) { + cci_dev->cci_clk_params[count].hw_thigh = val; + rc = of_property_read_u32(src_node, "hw-tlow", + &val); + CAM_DBG(CAM_CCI, "hw-tlow %d, rc %d", + val, rc); + } + if (!rc) { + cci_dev->cci_clk_params[count].hw_tlow = val; + rc = of_property_read_u32(src_node, "hw-tsu-sto", + &val); + CAM_DBG(CAM_CCI, "hw-tsu-sto %d, rc %d", + val, rc); + } + if (!rc) { + cci_dev->cci_clk_params[count].hw_tsu_sto = val; + rc = of_property_read_u32(src_node, "hw-tsu-sta", + &val); + CAM_DBG(CAM_CCI, "hw-tsu-sta %d, rc %d", + val, rc); + } + if (!rc) { + cci_dev->cci_clk_params[count].hw_tsu_sta = val; + rc = of_property_read_u32(src_node, "hw-thd-dat", + &val); + CAM_DBG(CAM_CCI, "hw-thd-dat %d, rc %d", + val, rc); + } + if (!rc) { + cci_dev->cci_clk_params[count].hw_thd_dat = val; + rc = of_property_read_u32(src_node, "hw-thd-sta", + &val); + CAM_DBG(CAM_CCI, "hw-thd-sta %d, rc %d", + val, rc); + } + if (!rc) { + cci_dev->cci_clk_params[count].hw_thd_sta = val; + rc = of_property_read_u32(src_node, "hw-tbuf", + &val); + CAM_DBG(CAM_CCI, "hw-tbuf %d, rc %d", + val, rc); + } + if (!rc) { + cci_dev->cci_clk_params[count].hw_tbuf = val; + rc = of_property_read_u32(src_node, + "hw-scl-stretch-en", &val); + CAM_DBG(CAM_CCI, "hw-scl-stretch-en %d, rc %d", + val, rc); + } + if (!rc) { + cci_dev->cci_clk_params[count].hw_scl_stretch_en = val; + rc = of_property_read_u32(src_node, "hw-trdhld", + &val); + CAM_DBG(CAM_CCI, "hw-trdhld %d, rc %d", + val, rc); + } + if (!rc) { + cci_dev->cci_clk_params[count].hw_trdhld = val; + rc = of_property_read_u32(src_node, "hw-tsp", + &val); + CAM_DBG(CAM_CCI, "hw-tsp %d, rc %d", val, rc); + } + if (!rc) { + cci_dev->cci_clk_params[count].hw_tsp = val; + val = 0; + rc = of_property_read_u32(src_node, "cci-clk-src", + &val); + CAM_DBG(CAM_CCI, "cci-clk-src %d, rc %d", val, rc); + cci_dev->cci_clk_params[count].cci_clk_src = val; + } else + cam_cci_init_default_clk_params(cci_dev, count); + + of_node_put(src_node); + } +} + +int cam_cci_parse_dt_info(struct platform_device *pdev, + struct cci_device *new_cci_dev) +{ + int rc = 0, i = 0; + struct cam_hw_soc_info *soc_info = + &new_cci_dev->soc_info; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) { + CAM_ERR(CAM_CCI, "Parsing DT data failed:%d", rc); + return -EINVAL; + } + + new_cci_dev->ref_count = 0; + + rc = cam_soc_util_request_platform_resource(soc_info, + cam_cci_irq, new_cci_dev); + if (rc < 0) { + CAM_ERR(CAM_CCI, "requesting platform resources failed:%d", rc); + return -EINVAL; + } + new_cci_dev->v4l2_dev_str.pdev = pdev; + cam_cci_init_cci_params(new_cci_dev); + cam_cci_init_clk_params(new_cci_dev); + + rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + if (rc) + CAM_ERR(CAM_CCI, "failed to add child nodes, rc=%d", rc); + + for (i = 0; i < MASTER_MAX; i++) { + new_cci_dev->write_wq[i] = create_singlethread_workqueue( + "cam_cci_wq"); + if (!new_cci_dev->write_wq[i]) + CAM_ERR(CAM_CCI, "Failed to create write wq"); + } + CAM_DBG(CAM_CCI, "Exit"); + return 0; +} + +int cam_cci_soc_release(struct cci_device *cci_dev) +{ + uint8_t i = 0, rc = 0; + struct cam_hw_soc_info *soc_info = + &cci_dev->soc_info; + + if (!cci_dev->ref_count || cci_dev->cci_state != CCI_STATE_ENABLED) { + CAM_ERR(CAM_CCI, "invalid ref count %d / cci state %d", + cci_dev->ref_count, cci_dev->cci_state); + return -EINVAL; + } + if (--cci_dev->ref_count) { + CAM_DBG(CAM_CCI, "ref_count Exit %d", cci_dev->ref_count); + return 0; + } + for (i = 0; i < MASTER_MAX; i++) + if (cci_dev->write_wq[i]) + flush_workqueue(cci_dev->write_wq[i]); + + for (i = 0; i < MASTER_MAX; i++) + cci_dev->i2c_freq_mode[i] = I2C_MAX_MODES; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) { + CAM_ERR(CAM_CCI, "platform resources disable failed, rc=%d", + rc); + return rc; + } + + cci_dev->cci_state = CCI_STATE_DISABLED; + cci_dev->cycles_per_us = 0; + + cam_cpas_stop(cci_dev->cpas_handle); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_soc.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..f0cdfe822cd37624346c7c008c2b3db16c08aa0b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/cam_cci_soc.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CCI_SOC_H_ +#define _CAM_CCI_SOC_H_ + +#include "cam_cci_core.h" +#include "cam_soc_util.h" + +/** + * @sd: V4L2 sub device + * @c_ctrl: CCI control structure + * + * This API initializes the CCI and acquires SOC resources + */ +int cam_cci_init(struct v4l2_subdev *sd, + struct cam_cci_ctrl *c_ctrl); + +/** + * @cci_dev: CCI device structure + * + * This API releases the CCI and its SOC resources + */ +int cam_cci_soc_release(struct cci_device *cci_dev); + +/** + * @pdev: Platform device + * @new_cci_dev: CCI device structure + * + * This API parses CCI device tree + */ +int cam_cci_parse_dt_info(struct platform_device *pdev, + struct cci_device *new_cci_dev); + +/** + * @pdev: Platform device + * @cci_dev: CCI device structure + * + * This API puts all SOC resources + */ +void cam_cci_soc_remove(struct platform_device *pdev, + struct cci_device *cci_dev); +#endif /* _CAM_CCI_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..633b90f2b911701e57d24f1005ea9208cab4542c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_csiphy_soc.o cam_csiphy_dev.o cam_csiphy_core.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c new file mode 100644 index 0000000000000000000000000000000000000000..e5e2a3e26df7db97aaae3358741e1aab502d87d4 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -0,0 +1,1075 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "cam_csiphy_core.h" +#include "cam_csiphy_dev.h" +#include "cam_csiphy_soc.h" +#include "cam_common_util.h" +#include "cam_packet_util.h" + +#include + +#include +#include +#include + +#define SCM_SVC_CAMERASS 0x18 +#define SECURE_SYSCALL_ID 0x6 +#define SECURE_SYSCALL_ID_2 0x7 + +#define LANE_MASK_2PH 0x1F +#define LANE_MASK_3PH 0x7 + +#define SEC_LANE_CP_REG_LEN 32 +#define MAX_PHY_MSK_PER_REG 4 + +static int csiphy_dump; +module_param(csiphy_dump, int, 0644); + +static int cam_csiphy_notify_secure_mode(struct csiphy_device *csiphy_dev, + bool protect, int32_t offset) +{ + struct scm_desc desc = {0}; + + if (offset >= CSIPHY_MAX_INSTANCES) { + CAM_ERR(CAM_CSIPHY, "Invalid CSIPHY offset"); + return -EINVAL; + } + + desc.arginfo = SCM_ARGS(2, SCM_VAL, SCM_VAL); + desc.args[0] = protect; + desc.args[1] = csiphy_dev->csiphy_cpas_cp_reg_mask[offset]; + + if (scm_call2(SCM_SIP_FNID(SCM_SVC_CAMERASS, SECURE_SYSCALL_ID_2), + &desc)) { + CAM_ERR(CAM_CSIPHY, "scm call to hypervisor failed"); + return -EINVAL; + } + CAM_INFO(CAM_CSIPHY, "PHY : %d offset: %d SEC: %d Mask: %d", + csiphy_dev->soc_info.index, + offset, + protect, + csiphy_dev->csiphy_cpas_cp_reg_mask[offset]); + + return 0; +} + +int32_t cam_csiphy_get_instance_offset( + struct csiphy_device *csiphy_dev, + int32_t dev_handle) +{ + int32_t i; + + if (csiphy_dev->acquire_count > + CSIPHY_MAX_INSTANCES) { + CAM_ERR(CAM_CSIPHY, "Invalid acquire count"); + return -EINVAL; + } + + for (i = 0; i < csiphy_dev->acquire_count; i++) { + if (dev_handle == + csiphy_dev->bridge_intf.device_hdl[i]) + break; + } + + return i; +} + +void cam_csiphy_query_cap(struct csiphy_device *csiphy_dev, + struct cam_csiphy_query_cap *csiphy_cap) +{ + struct cam_hw_soc_info *soc_info = &csiphy_dev->soc_info; + + csiphy_cap->slot_info = soc_info->index; + csiphy_cap->version = csiphy_dev->hw_version; + csiphy_cap->clk_lane = csiphy_dev->clk_lane; +} + +void cam_csiphy_reset(struct csiphy_device *csiphy_dev) +{ + int32_t i; + void __iomem *base = NULL; + uint32_t size = + csiphy_dev->ctrl_reg->csiphy_reg.csiphy_reset_array_size; + struct cam_hw_soc_info *soc_info = &csiphy_dev->soc_info; + + base = soc_info->reg_map[0].mem_base; + + for (i = 0; i < size; i++) { + cam_io_w_mb( + csiphy_dev->ctrl_reg->csiphy_reset_reg[i].reg_data, + base + + csiphy_dev->ctrl_reg->csiphy_reset_reg[i].reg_addr); + + usleep_range(csiphy_dev->ctrl_reg->csiphy_reset_reg[i].delay + * 1000, csiphy_dev->ctrl_reg->csiphy_reset_reg[i].delay + * 1000 + 10); + } +} + +int32_t cam_csiphy_update_secure_info( + struct csiphy_device *csiphy_dev, + struct cam_csiphy_info *cam_cmd_csiphy_info, + struct cam_config_dev_cmd *cfg_dev) +{ + uint32_t clock_lane, adj_lane_mask, temp, phy_mask_len; + int32_t offset; + + if (csiphy_dev->acquire_count >= + CSIPHY_MAX_INSTANCES) { + CAM_ERR(CAM_CSIPHY, "Invalid acquire count"); + return -EINVAL; + } + + offset = cam_csiphy_get_instance_offset(csiphy_dev, + cfg_dev->dev_handle); + if (offset < 0 || offset >= CSIPHY_MAX_INSTANCES) { + CAM_ERR(CAM_CSIPHY, "Invalid offset"); + return -EINVAL; + } + + if (cam_cmd_csiphy_info->combo_mode) + clock_lane = + csiphy_dev->ctrl_reg->csiphy_reg.csiphy_2ph_combo_ck_ln; + else + clock_lane = + csiphy_dev->ctrl_reg->csiphy_reg.csiphy_2ph_clock_lane; + + adj_lane_mask = cam_cmd_csiphy_info->lane_mask & LANE_MASK_2PH & + ~clock_lane; + temp = adj_lane_mask & (clock_lane - 1); + adj_lane_mask = + ((adj_lane_mask & (~(clock_lane - 1))) >> 1) | temp; + + if (cam_cmd_csiphy_info->csiphy_3phase) + adj_lane_mask = cam_cmd_csiphy_info->lane_mask & LANE_MASK_3PH; + + csiphy_dev->csiphy_info.secure_mode[offset] = 1; + + if (csiphy_dev->hw_version == CSIPHY_VERSION_V201) { + phy_mask_len = CAM_CSIPHY_MAX_DPHY_LANES + + CAM_CSIPHY_MAX_CPHY_LANES + 1; + } else if (csiphy_dev->hw_version == CSIPHY_VERSION_V121) { + phy_mask_len = + (csiphy_dev->soc_info.index < MAX_PHY_MSK_PER_REG) ? + CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES : + CAM_CSIPHY_MAX_DPHY_LANES + + CAM_CSIPHY_MAX_CPHY_LANES + 1; + } else { + phy_mask_len = CAM_CSIPHY_MAX_DPHY_LANES + + CAM_CSIPHY_MAX_CPHY_LANES; + } + + if (csiphy_dev->soc_info.index < MAX_PHY_MSK_PER_REG) { + csiphy_dev->csiphy_cpas_cp_reg_mask[offset] = + ((uint64_t)adj_lane_mask) << + (csiphy_dev->soc_info.index * phy_mask_len + + (!cam_cmd_csiphy_info->csiphy_3phase) * + (CAM_CSIPHY_MAX_CPHY_LANES)); + } else { + csiphy_dev->csiphy_cpas_cp_reg_mask[offset] = + ((uint64_t)adj_lane_mask) << + ((csiphy_dev->soc_info.index - MAX_PHY_MSK_PER_REG) * + phy_mask_len + SEC_LANE_CP_REG_LEN + + (!cam_cmd_csiphy_info->csiphy_3phase) * + (CAM_CSIPHY_MAX_CPHY_LANES)); + } + CAM_DBG(CAM_CSIPHY, "csi phy idx:%d, cp_reg_mask:0x%lx", + csiphy_dev->soc_info.index, + csiphy_dev->csiphy_cpas_cp_reg_mask[offset]); + return 0; +} + +int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, + struct cam_config_dev_cmd *cfg_dev) +{ + int32_t rc = 0; + uintptr_t generic_ptr; + uintptr_t generic_pkt_ptr; + struct cam_packet *csl_packet = NULL; + struct cam_cmd_buf_desc *cmd_desc = NULL; + uint32_t *cmd_buf = NULL; + struct cam_csiphy_info *cam_cmd_csiphy_info = NULL; + size_t len; + size_t remain_len; + + if (!cfg_dev || !csiphy_dev) { + CAM_ERR(CAM_CSIPHY, "Invalid Args"); + return -EINVAL; + } + + rc = cam_mem_get_cpu_buf((int32_t) cfg_dev->packet_handle, + &generic_pkt_ptr, &len); + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, "Failed to get packet Mem address: %d", rc); + return rc; + } + + remain_len = len; + if ((sizeof(struct cam_packet) > len) || + ((size_t)cfg_dev->offset >= len - sizeof(struct cam_packet))) { + CAM_ERR(CAM_CSIPHY, + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), len); + rc = -EINVAL; + return rc; + } + + remain_len -= (size_t)cfg_dev->offset; + csl_packet = (struct cam_packet *) + (generic_pkt_ptr + (uint32_t)cfg_dev->offset); + + if (cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_CSIPHY, "Invalid packet params"); + rc = -EINVAL; + return rc; + } + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *)&csl_packet->payload + + csl_packet->cmd_buf_offset / 4); + + rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, + &generic_ptr, &len); + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, + "Failed to get cmd buf Mem address : %d", rc); + return rc; + } + + if ((len < sizeof(struct cam_csiphy_info)) || + (cmd_desc->offset > (len - sizeof(struct cam_csiphy_info)))) { + CAM_ERR(CAM_CSIPHY, + "Not enough buffer provided for cam_cisphy_info"); + rc = -EINVAL; + return rc; + } + + cmd_buf = (uint32_t *)generic_ptr; + cmd_buf += cmd_desc->offset / 4; + cam_cmd_csiphy_info = (struct cam_csiphy_info *)cmd_buf; + + csiphy_dev->config_count++; + csiphy_dev->csiphy_info.lane_cnt += cam_cmd_csiphy_info->lane_cnt; + csiphy_dev->csiphy_info.lane_mask |= cam_cmd_csiphy_info->lane_mask; + csiphy_dev->csiphy_info.csiphy_3phase = + cam_cmd_csiphy_info->csiphy_3phase; + csiphy_dev->csiphy_info.combo_mode |= cam_cmd_csiphy_info->combo_mode; + if (cam_cmd_csiphy_info->combo_mode == 1) { + csiphy_dev->csiphy_info.settle_time_combo_sensor = + cam_cmd_csiphy_info->settle_time; + csiphy_dev->csiphy_info.data_rate_combo_sensor = + cam_cmd_csiphy_info->data_rate; + } else { + csiphy_dev->csiphy_info.settle_time = + cam_cmd_csiphy_info->settle_time; + csiphy_dev->csiphy_info.data_rate = + cam_cmd_csiphy_info->data_rate; + } + + + if (cam_cmd_csiphy_info->secure_mode == 1) + cam_csiphy_update_secure_info(csiphy_dev, + cam_cmd_csiphy_info, cfg_dev); + + CAM_DBG(CAM_CSIPHY, + "phy version_%d, lane count:%d, mask:0x%x", + csiphy_dev->hw_version, + csiphy_dev->csiphy_info.lane_cnt, + csiphy_dev->csiphy_info.lane_mask + ); + CAM_DBG(CAM_CSIPHY, + "3phase:%d, combo mode:%d, secure mode:%d", + csiphy_dev->csiphy_info.csiphy_3phase, + csiphy_dev->csiphy_info.combo_mode, + cam_cmd_csiphy_info->secure_mode + ); + CAM_DBG(CAM_CSIPHY, + "phy idx:%d, settle time:%d, datarate:%d", + csiphy_dev->soc_info.index, + csiphy_dev->csiphy_info.settle_time, + csiphy_dev->csiphy_info.data_rate); + + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(cfg_dev->packet_handle); + return rc; + +} + +void cam_csiphy_cphy_irq_config(struct csiphy_device *csiphy_dev) +{ + int32_t i; + void __iomem *csiphybase = + csiphy_dev->soc_info.reg_map[0].mem_base; + + for (i = 0; i < csiphy_dev->num_irq_registers; i++) + cam_io_w_mb( + csiphy_dev->ctrl_reg->csiphy_irq_reg[i].reg_data, + csiphybase + + csiphy_dev->ctrl_reg->csiphy_irq_reg[i].reg_addr); +} + +void cam_csiphy_cphy_data_rate_config(struct csiphy_device *csiphy_device) +{ + int i = 0, j = 0; + uint64_t phy_data_rate = 0; + void __iomem *csiphybase = NULL; + ssize_t num_table_entries = 0; + struct data_rate_settings_t *settings_table = NULL; + + if ((csiphy_device == NULL) || + (csiphy_device->ctrl_reg == NULL) || + (csiphy_device->ctrl_reg->data_rates_settings_table == NULL)) { + CAM_DBG(CAM_CSIPHY, + "Data rate specific register table not found"); + return; + } + + phy_data_rate = csiphy_device->csiphy_info.data_rate; + csiphybase = + csiphy_device->soc_info.reg_map[0].mem_base; + settings_table = + csiphy_device->ctrl_reg->data_rates_settings_table; + num_table_entries = + settings_table->num_data_rate_settings; + + CAM_DBG(CAM_CSIPHY, "required data rate : %llu", phy_data_rate); + for (i = 0; i < num_table_entries; i++) { + struct data_rate_reg_info_t *drate_settings = + settings_table->data_rate_settings; + uint64_t bandwidth = + drate_settings[i].bandwidth; + ssize_t num_reg_entries = + drate_settings[i].data_rate_reg_array_size; + + if (phy_data_rate > bandwidth) { + CAM_DBG(CAM_CSIPHY, + "Skipping table [%d] %llu required: %llu", + i, bandwidth, phy_data_rate); + continue; + } + + CAM_DBG(CAM_CSIPHY, + "table[%d] BW : %llu Selected", i, bandwidth); + for (j = 0; j < num_reg_entries; j++) { + uint32_t reg_addr = + drate_settings[i].csiphy_data_rate_regs[j].reg_addr; + + uint32_t reg_data = + drate_settings[i].csiphy_data_rate_regs[j].reg_data; + + CAM_DBG(CAM_CSIPHY, + "writing reg : %x val : %x", + reg_addr, reg_data); + cam_io_w_mb(reg_data, + csiphybase + reg_addr); + } + break; + } +} + +void cam_csiphy_cphy_irq_disable(struct csiphy_device *csiphy_dev) +{ + int32_t i; + void __iomem *csiphybase = + csiphy_dev->soc_info.reg_map[0].mem_base; + + for (i = 0; i < csiphy_dev->num_irq_registers; i++) + cam_io_w_mb(0x0, csiphybase + + csiphy_dev->ctrl_reg->csiphy_irq_reg[i].reg_addr); +} + +irqreturn_t cam_csiphy_irq(int irq_num, void *data) +{ + uint32_t irq; + uint8_t i; + struct csiphy_device *csiphy_dev = + (struct csiphy_device *)data; + struct cam_hw_soc_info *soc_info = NULL; + struct csiphy_reg_parms_t *csiphy_reg = NULL; + void __iomem *base = NULL; + + if (!csiphy_dev) { + CAM_ERR(CAM_CSIPHY, "Invalid Args"); + return IRQ_NONE; + } + + soc_info = &csiphy_dev->soc_info; + base = csiphy_dev->soc_info.reg_map[0].mem_base; + csiphy_reg = &csiphy_dev->ctrl_reg->csiphy_reg; + + for (i = 0; i < csiphy_dev->num_irq_registers; i++) { + irq = cam_io_r(base + + csiphy_reg->mipi_csiphy_interrupt_status0_addr + + (0x4 * i)); + cam_io_w_mb(irq, base + + csiphy_reg->mipi_csiphy_interrupt_clear0_addr + + (0x4 * i)); + CAM_ERR_RATE_LIMIT(CAM_CSIPHY, + "CSIPHY%d_IRQ_STATUS_ADDR%d = 0x%x", + soc_info->index, i, irq); + cam_io_w_mb(0x0, base + + csiphy_reg->mipi_csiphy_interrupt_clear0_addr + + (0x4 * i)); + } + cam_io_w_mb(0x1, base + csiphy_reg->mipi_csiphy_glbl_irq_cmd_addr); + cam_io_w_mb(0x0, base + csiphy_reg->mipi_csiphy_glbl_irq_cmd_addr); + + return IRQ_HANDLED; +} + +int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev) +{ + int32_t rc = 0; + uint32_t lane_enable = 0, mask = 1, size = 0; + uint16_t lane_mask = 0, i = 0, cfg_size = 0, temp = 0; + uint8_t lane_cnt, lane_pos = 0; + uint16_t settle_cnt = 0; + uint64_t intermediate_var; + void __iomem *csiphybase; + struct csiphy_reg_t *csiphy_common_reg = NULL; + struct csiphy_reg_t (*reg_array)[MAX_SETTINGS_PER_LANE]; + + lane_cnt = csiphy_dev->csiphy_info.lane_cnt; + csiphybase = csiphy_dev->soc_info.reg_map[0].mem_base; + + if (!csiphybase) { + CAM_ERR(CAM_CSIPHY, "csiphybase NULL"); + return -EINVAL; + } + + if (!csiphy_dev->csiphy_info.csiphy_3phase) { + if (csiphy_dev->csiphy_info.combo_mode == 1) + reg_array = + csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg; + else + reg_array = + csiphy_dev->ctrl_reg->csiphy_2ph_reg; + csiphy_dev->num_irq_registers = 11; + cfg_size = + csiphy_dev->ctrl_reg->csiphy_reg.csiphy_2ph_config_array_size; + + lane_mask = csiphy_dev->csiphy_info.lane_mask & LANE_MASK_2PH; + for (i = 0; i < MAX_DPHY_DATA_LN; i++) { + if (mask == 0x2) { + if (lane_mask & mask) + lane_enable |= 0x80; + i--; + } else if (lane_mask & mask) { + lane_enable |= 0x1 << (i<<1); + } + mask <<= 1; + } + } else { + if (csiphy_dev->csiphy_info.combo_mode == 1) { + if (csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg) + reg_array = + csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg; + else { + reg_array = + csiphy_dev->ctrl_reg->csiphy_3ph_reg; + CAM_ERR(CAM_CSIPHY, + "Unsupported configuration, Falling back to CPHY mode"); + } + } else + reg_array = + csiphy_dev->ctrl_reg->csiphy_3ph_reg; + csiphy_dev->num_irq_registers = 11; + cfg_size = + csiphy_dev->ctrl_reg->csiphy_reg.csiphy_3ph_config_array_size; + + lane_mask = csiphy_dev->csiphy_info.lane_mask & LANE_MASK_3PH; + mask = lane_mask; + while (mask != 0) { + temp = (i << 1)+1; + lane_enable |= ((mask & 0x1) << temp); + mask >>= 1; + i++; + } + } + + size = csiphy_dev->ctrl_reg->csiphy_reg.csiphy_common_array_size; + + for (i = 0; i < size; i++) { + csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_common_reg[i]; + switch (csiphy_common_reg->csiphy_param_type) { + case CSIPHY_LANE_ENABLE: + cam_io_w_mb(lane_enable, + csiphybase + csiphy_common_reg->reg_addr); + usleep_range(csiphy_common_reg->delay * 1000, + csiphy_common_reg->delay * 1000 + 10); + break; + case CSIPHY_DEFAULT_PARAMS: + cam_io_w_mb(csiphy_common_reg->reg_data, + csiphybase + csiphy_common_reg->reg_addr); + usleep_range(csiphy_common_reg->delay * 1000, + csiphy_common_reg->delay * 1000 + 10); + break; + case CSIPHY_2PH_REGS: + if (!csiphy_dev->csiphy_info.csiphy_3phase) { + cam_io_w_mb(csiphy_common_reg->reg_data, + csiphybase + + csiphy_common_reg->reg_addr); + usleep_range(csiphy_common_reg->delay * 1000, + csiphy_common_reg->delay * 1000 + 10); + } + break; + case CSIPHY_3PH_REGS: + if (csiphy_dev->csiphy_info.csiphy_3phase) { + cam_io_w_mb(csiphy_common_reg->reg_data, + csiphybase + + csiphy_common_reg->reg_addr); + usleep_range(csiphy_common_reg->delay * 1000, + csiphy_common_reg->delay * 1000 + 10); + } + break; + default: + break; + } + } + + while (lane_mask) { + if (!(lane_mask & 0x1)) { + lane_pos++; + lane_mask >>= 1; + continue; + } + + intermediate_var = csiphy_dev->csiphy_info.settle_time; + do_div(intermediate_var, 200000000); + settle_cnt = intermediate_var; + if (csiphy_dev->csiphy_info.combo_mode == 1 && + (lane_pos >= 3)) { + intermediate_var = + csiphy_dev->csiphy_info.settle_time_combo_sensor; + do_div(intermediate_var, 200000000); + settle_cnt = intermediate_var; + } + for (i = 0; i < cfg_size; i++) { + switch (reg_array[lane_pos][i].csiphy_param_type) { + case CSIPHY_LANE_ENABLE: + cam_io_w_mb(lane_enable, + csiphybase + + reg_array[lane_pos][i].reg_addr); + break; + case CSIPHY_DEFAULT_PARAMS: + cam_io_w_mb(reg_array[lane_pos][i].reg_data, + csiphybase + + reg_array[lane_pos][i].reg_addr); + break; + case CSIPHY_SETTLE_CNT_LOWER_BYTE: + cam_io_w_mb(settle_cnt & 0xFF, + csiphybase + + reg_array[lane_pos][i].reg_addr); + break; + case CSIPHY_SETTLE_CNT_HIGHER_BYTE: + cam_io_w_mb((settle_cnt >> 8) & 0xFF, + csiphybase + + reg_array[lane_pos][i].reg_addr); + break; + default: + CAM_DBG(CAM_CSIPHY, "Do Nothing"); + break; + } + if (reg_array[lane_pos][i].delay > 0) { + usleep_range(reg_array[lane_pos][i].delay*1000, + reg_array[lane_pos][i].delay*1000 + 10); + } + } + lane_mask >>= 1; + lane_pos++; + } + + if (csiphy_dev->csiphy_info.csiphy_3phase) + cam_csiphy_cphy_data_rate_config(csiphy_dev); + + cam_csiphy_cphy_irq_config(csiphy_dev); + + return rc; +} + +void cam_csiphy_clear_secbits(struct csiphy_device *csiphy_dev) +{ + int32_t i = 0; + + for (i = 0; i < csiphy_dev->acquire_count; i++) { + if (csiphy_dev->csiphy_info.secure_mode[i]) + cam_csiphy_notify_secure_mode( + csiphy_dev, + CAM_SECURE_MODE_NON_SECURE, i); + + csiphy_dev->csiphy_info.secure_mode[i] = + CAM_SECURE_MODE_NON_SECURE; + + csiphy_dev->csiphy_cpas_cp_reg_mask[i] = 0; + } +} + +void cam_csiphy_shutdown(struct csiphy_device *csiphy_dev) +{ + struct cam_hw_soc_info *soc_info; + + if (csiphy_dev->csiphy_state == CAM_CSIPHY_INIT) + return; + + /* + * clear the secure bits if the provider crashed + */ + cam_csiphy_clear_secbits(csiphy_dev); + if (csiphy_dev->csiphy_state == CAM_CSIPHY_START) { + soc_info = &csiphy_dev->soc_info; + + cam_csiphy_reset(csiphy_dev); + cam_soc_util_disable_platform_resource(soc_info, true, true); + + cam_cpas_stop(csiphy_dev->cpas_handle); + csiphy_dev->csiphy_state = CAM_CSIPHY_ACQUIRE; + } + + if (csiphy_dev->csiphy_state == CAM_CSIPHY_ACQUIRE) { + if (csiphy_dev->bridge_intf.device_hdl[0] != -1) + cam_destroy_device_hdl( + csiphy_dev->bridge_intf.device_hdl[0]); + if (csiphy_dev->bridge_intf.device_hdl[1] != -1) + cam_destroy_device_hdl( + csiphy_dev->bridge_intf.device_hdl[1]); + csiphy_dev->bridge_intf.device_hdl[0] = -1; + csiphy_dev->bridge_intf.device_hdl[1] = -1; + csiphy_dev->bridge_intf.link_hdl[0] = -1; + csiphy_dev->bridge_intf.link_hdl[1] = -1; + csiphy_dev->bridge_intf.session_hdl[0] = -1; + csiphy_dev->bridge_intf.session_hdl[1] = -1; + } + + csiphy_dev->ref_count = 0; + csiphy_dev->is_acquired_dev_combo_mode = 0; + csiphy_dev->acquire_count = 0; + csiphy_dev->start_dev_count = 0; + csiphy_dev->csiphy_state = CAM_CSIPHY_INIT; +} + +static int32_t cam_csiphy_external_cmd(struct csiphy_device *csiphy_dev, + struct cam_config_dev_cmd *p_submit_cmd) +{ + struct cam_csiphy_info cam_cmd_csiphy_info; + int32_t rc = 0; + + if (copy_from_user(&cam_cmd_csiphy_info, + u64_to_user_ptr(p_submit_cmd->packet_handle), + sizeof(struct cam_csiphy_info))) { + CAM_ERR(CAM_CSIPHY, "failed to copy cam_csiphy_info\n"); + rc = -EFAULT; + } else { + csiphy_dev->csiphy_info.lane_cnt = + cam_cmd_csiphy_info.lane_cnt; + csiphy_dev->csiphy_info.lane_cnt = + cam_cmd_csiphy_info.lane_cnt; + csiphy_dev->csiphy_info.lane_mask = + cam_cmd_csiphy_info.lane_mask; + csiphy_dev->csiphy_info.csiphy_3phase = + cam_cmd_csiphy_info.csiphy_3phase; + csiphy_dev->csiphy_info.combo_mode = + cam_cmd_csiphy_info.combo_mode; + csiphy_dev->csiphy_info.settle_time = + cam_cmd_csiphy_info.settle_time; + csiphy_dev->csiphy_info.data_rate = + cam_cmd_csiphy_info.data_rate; + CAM_DBG(CAM_CSIPHY, + "%s CONFIG_DEV_EXT settle_time= %lld lane_cnt=%d lane_mask=0x%x", + __func__, + csiphy_dev->csiphy_info.settle_time, + csiphy_dev->csiphy_info.lane_cnt, + csiphy_dev->csiphy_info.lane_mask); + } + + return rc; +} + +int32_t cam_csiphy_core_cfg(void *phy_dev, + void *arg) +{ + struct csiphy_device *csiphy_dev = + (struct csiphy_device *)phy_dev; + struct intf_params *bridge_intf = NULL; + struct cam_control *cmd = (struct cam_control *)arg; + int32_t rc = 0; + + if (!csiphy_dev || !cmd) { + CAM_ERR(CAM_CSIPHY, "Invalid input args"); + return -EINVAL; + } + + if (cmd->handle_type != CAM_HANDLE_USER_POINTER) { + CAM_ERR(CAM_CSIPHY, "Invalid handle type: %d", + cmd->handle_type); + return -EINVAL; + } + + CAM_DBG(CAM_CSIPHY, "Opcode received: %d", cmd->op_code); + mutex_lock(&csiphy_dev->mutex); + switch (cmd->op_code) { + case CAM_ACQUIRE_DEV: { + struct cam_sensor_acquire_dev csiphy_acq_dev; + struct cam_csiphy_acquire_dev_info csiphy_acq_params; + + struct cam_create_dev_hdl bridge_params; + + if (csiphy_dev->csiphy_state == CAM_CSIPHY_START) { + CAM_ERR(CAM_CSIPHY, + "Not in right state to acquire : %d", + csiphy_dev->csiphy_state); + rc = -EINVAL; + goto release_mutex; + } + + rc = copy_from_user(&csiphy_acq_dev, + u64_to_user_ptr(cmd->handle), + sizeof(csiphy_acq_dev)); + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, "Failed copying from User"); + goto release_mutex; + } + + csiphy_acq_params.combo_mode = 0; + + if (copy_from_user(&csiphy_acq_params, + u64_to_user_ptr(csiphy_acq_dev.info_handle), + sizeof(csiphy_acq_params))) { + CAM_ERR(CAM_CSIPHY, + "Failed copying from User"); + goto release_mutex; + } + + if (csiphy_dev->acquire_count == 2) { + CAM_ERR(CAM_CSIPHY, + "CSIPHY device do not allow more than 2 acquires"); + rc = -EINVAL; + goto release_mutex; + } + + if ((csiphy_acq_params.combo_mode == 1) && + (csiphy_dev->is_acquired_dev_combo_mode == 1)) { + CAM_ERR(CAM_CSIPHY, + "Multiple Combo Acq are not allowed: cm: %d, acm: %d", + csiphy_acq_params.combo_mode, + csiphy_dev->is_acquired_dev_combo_mode); + rc = -EINVAL; + goto release_mutex; + } + + if ((csiphy_acq_params.combo_mode != 1) && + (csiphy_dev->is_acquired_dev_combo_mode != 1) && + (csiphy_dev->acquire_count == 1)) { + CAM_ERR(CAM_CSIPHY, + "Multiple Acquires are not allowed cm: %d acm: %d", + csiphy_acq_params.combo_mode, + csiphy_dev->is_acquired_dev_combo_mode); + rc = -EINVAL; + goto release_mutex; + } + + bridge_params.ops = NULL; + bridge_params.session_hdl = csiphy_acq_dev.session_handle; + bridge_params.v4l2_sub_dev_flag = 0; + bridge_params.media_entity_flag = 0; + bridge_params.priv = csiphy_dev; + bridge_params.dev_id = CAM_CSIPHY; + + if (csiphy_acq_params.combo_mode >= 2) { + CAM_ERR(CAM_CSIPHY, "Invalid combo_mode %d", + csiphy_acq_params.combo_mode); + rc = -EINVAL; + goto release_mutex; + } + + csiphy_acq_dev.device_handle = + cam_create_device_hdl(&bridge_params); + if (csiphy_acq_dev.device_handle <= 0) { + rc = -EFAULT; + CAM_ERR(CAM_CSIPHY, "Can not create device handle"); + goto release_mutex; + } + bridge_intf = &csiphy_dev->bridge_intf; + bridge_intf->device_hdl[csiphy_acq_params.combo_mode] + = csiphy_acq_dev.device_handle; + bridge_intf->session_hdl[csiphy_acq_params.combo_mode] = + csiphy_acq_dev.session_handle; + + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &csiphy_acq_dev, + sizeof(struct cam_sensor_acquire_dev))) { + CAM_ERR(CAM_CSIPHY, "Failed copying from User"); + rc = -EINVAL; + goto release_mutex; + } + if (csiphy_acq_params.combo_mode == 1) + csiphy_dev->is_acquired_dev_combo_mode = 1; + + csiphy_dev->acquire_count++; + csiphy_dev->csiphy_state = CAM_CSIPHY_ACQUIRE; + } + break; + case CAM_QUERY_CAP: { + struct cam_csiphy_query_cap csiphy_cap = {0}; + + cam_csiphy_query_cap(csiphy_dev, &csiphy_cap); + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &csiphy_cap, sizeof(struct cam_csiphy_query_cap))) { + CAM_ERR(CAM_CSIPHY, "Failed copying from User"); + rc = -EINVAL; + goto release_mutex; + } + } + break; + case CAM_STOP_DEV: { + int32_t offset, rc = 0; + struct cam_start_stop_dev_cmd config; + + rc = copy_from_user(&config, (void __user *)cmd->handle, + sizeof(config)); + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, "Failed copying from User"); + goto release_mutex; + } + + if ((csiphy_dev->csiphy_state != CAM_CSIPHY_START) || + !csiphy_dev->start_dev_count) { + CAM_ERR(CAM_CSIPHY, "Not in right state to stop : %d", + csiphy_dev->csiphy_state); + goto release_mutex; + } + + offset = cam_csiphy_get_instance_offset(csiphy_dev, + config.dev_handle); + if (offset < 0 || offset >= CSIPHY_MAX_INSTANCES) { + CAM_ERR(CAM_CSIPHY, "Invalid offset"); + goto release_mutex; + } + + if (--csiphy_dev->start_dev_count) { + CAM_DBG(CAM_CSIPHY, "Stop Dev ref Cnt: %d", + csiphy_dev->start_dev_count); + if (csiphy_dev->csiphy_info.secure_mode[offset]) + cam_csiphy_notify_secure_mode( + csiphy_dev, + CAM_SECURE_MODE_NON_SECURE, offset); + + csiphy_dev->csiphy_info.secure_mode[offset] = + CAM_SECURE_MODE_NON_SECURE; + csiphy_dev->csiphy_cpas_cp_reg_mask[offset] = 0; + + goto release_mutex; + } + + if (csiphy_dev->csiphy_info.secure_mode[offset]) + cam_csiphy_notify_secure_mode( + csiphy_dev, + CAM_SECURE_MODE_NON_SECURE, offset); + + csiphy_dev->csiphy_info.secure_mode[offset] = + CAM_SECURE_MODE_NON_SECURE; + + csiphy_dev->csiphy_cpas_cp_reg_mask[offset] = 0x0; + + rc = cam_csiphy_disable_hw(csiphy_dev); + if (rc < 0) + CAM_ERR(CAM_CSIPHY, "Failed in csiphy release"); + + rc = cam_cpas_stop(csiphy_dev->cpas_handle); + if (rc < 0) + CAM_ERR(CAM_CSIPHY, "de-voting CPAS: %d", rc); + + csiphy_dev->csiphy_state = CAM_CSIPHY_ACQUIRE; + } + break; + case CAM_RELEASE_DEV: { + int32_t offset; + struct cam_release_dev_cmd release; + + if (!csiphy_dev->acquire_count) { + CAM_ERR(CAM_CSIPHY, "No valid devices to release"); + rc = -EINVAL; + goto release_mutex; + } + + if (copy_from_user(&release, + u64_to_user_ptr(cmd->handle), + sizeof(release))) { + rc = -EFAULT; + goto release_mutex; + } + + offset = cam_csiphy_get_instance_offset(csiphy_dev, + release.dev_handle); + if (offset < 0 || offset >= CSIPHY_MAX_INSTANCES) { + CAM_ERR(CAM_CSIPHY, "Invalid offset"); + goto release_mutex; + } + + if (csiphy_dev->csiphy_info.secure_mode[offset]) + cam_csiphy_notify_secure_mode( + csiphy_dev, + CAM_SECURE_MODE_NON_SECURE, offset); + + csiphy_dev->csiphy_info.secure_mode[offset] = + CAM_SECURE_MODE_NON_SECURE; + + csiphy_dev->csiphy_cpas_cp_reg_mask[offset] = 0x0; + + rc = cam_destroy_device_hdl(release.dev_handle); + if (rc < 0) + CAM_ERR(CAM_CSIPHY, "destroying the device hdl"); + if (release.dev_handle == + csiphy_dev->bridge_intf.device_hdl[0]) { + csiphy_dev->bridge_intf.device_hdl[0] = -1; + csiphy_dev->bridge_intf.link_hdl[0] = -1; + csiphy_dev->bridge_intf.session_hdl[0] = -1; + } else { + csiphy_dev->bridge_intf.device_hdl[1] = -1; + csiphy_dev->bridge_intf.link_hdl[1] = -1; + csiphy_dev->bridge_intf.session_hdl[1] = -1; + csiphy_dev->is_acquired_dev_combo_mode = 0; + } + + csiphy_dev->config_count--; + csiphy_dev->acquire_count--; + + if (csiphy_dev->acquire_count == 0) + csiphy_dev->csiphy_state = CAM_CSIPHY_INIT; + + if (csiphy_dev->config_count == 0) { + CAM_DBG(CAM_CSIPHY, "reset csiphy_info"); + csiphy_dev->csiphy_info.lane_mask = 0; + csiphy_dev->csiphy_info.lane_cnt = 0; + csiphy_dev->csiphy_info.combo_mode = 0; + } + } + break; + case CAM_CONFIG_DEV: { + struct cam_config_dev_cmd config; + + if (copy_from_user(&config, + u64_to_user_ptr(cmd->handle), + sizeof(config))) { + rc = -EFAULT; + } else { + rc = cam_cmd_buf_parser(csiphy_dev, &config); + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, "Fail in cmd buf parser"); + goto release_mutex; + } + } + break; + } + case CAM_START_DEV: { + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + struct cam_start_stop_dev_cmd config; + int32_t offset; + + rc = copy_from_user(&config, (void __user *)cmd->handle, + sizeof(config)); + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, "Failed copying from User"); + goto release_mutex; + } + + if (csiphy_dev->csiphy_state == CAM_CSIPHY_START) { + csiphy_dev->start_dev_count++; + goto release_mutex; + } + + offset = cam_csiphy_get_instance_offset(csiphy_dev, + config.dev_handle); + if (offset < 0 || offset >= CSIPHY_MAX_INSTANCES) { + CAM_ERR(CAM_CSIPHY, "Invalid offset"); + goto release_mutex; + } + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_LOWSVS_VOTE; + axi_vote.num_paths = 1; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_WRITE; + axi_vote.axi_path[0].camnoc_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ab_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW; + + rc = cam_cpas_start(csiphy_dev->cpas_handle, + &ahb_vote, &axi_vote); + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, "voting CPAS: %d", rc); + goto release_mutex; + } + + if (csiphy_dev->csiphy_info.secure_mode[offset] == 1) { + if (cam_cpas_is_feature_supported( + CAM_CPAS_SECURE_CAMERA_ENABLE, + 0) != true) { + CAM_ERR(CAM_CSIPHY, + "sec_cam: camera fuse bit not set"); + cam_cpas_stop(csiphy_dev->cpas_handle); + rc = -1; + goto release_mutex; + } + + rc = cam_csiphy_notify_secure_mode( + csiphy_dev, + CAM_SECURE_MODE_SECURE, offset); + if (rc < 0) { + csiphy_dev->csiphy_info.secure_mode[offset] = + CAM_SECURE_MODE_NON_SECURE; + cam_cpas_stop(csiphy_dev->cpas_handle); + goto release_mutex; + } + } + + rc = cam_csiphy_enable_hw(csiphy_dev); + if (rc != 0) { + CAM_ERR(CAM_CSIPHY, "cam_csiphy_enable_hw failed"); + cam_cpas_stop(csiphy_dev->cpas_handle); + goto release_mutex; + } + rc = cam_csiphy_config_dev(csiphy_dev); + if (csiphy_dump == 1) + cam_csiphy_mem_dmp(&csiphy_dev->soc_info); + + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, "cam_csiphy_config_dev failed"); + cam_csiphy_disable_hw(csiphy_dev); + cam_cpas_stop(csiphy_dev->cpas_handle); + goto release_mutex; + } + csiphy_dev->start_dev_count++; + csiphy_dev->csiphy_state = CAM_CSIPHY_START; + } + break; + case CAM_CONFIG_DEV_EXTERNAL: { + struct cam_config_dev_cmd submit_cmd; + + if (copy_from_user(&submit_cmd, + u64_to_user_ptr(cmd->handle), + sizeof(struct cam_config_dev_cmd))) { + CAM_ERR(CAM_CSIPHY, "failed copy config ext\n"); + rc = -EFAULT; + } else { + rc = cam_csiphy_external_cmd(csiphy_dev, &submit_cmd); + } + break; + } + default: + CAM_ERR(CAM_CSIPHY, "Invalid Opcode: %d", cmd->op_code); + rc = -EINVAL; + goto release_mutex; + } + +release_mutex: + mutex_unlock(&csiphy_dev->mutex); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.h new file mode 100644 index 0000000000000000000000000000000000000000..237fa787f2268745f5634e257552c4625854cdfa --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSIPHY_CORE_H_ +#define _CAM_CSIPHY_CORE_H_ + +#include +#include "cam_csiphy_dev.h" +#include +#include +#include + +/** + * @csiphy_dev: CSIPhy device structure + * + * This API programs CSIPhy IRQ registers + */ +void cam_csiphy_cphy_irq_config(struct csiphy_device *csiphy_dev); + +/** + * @csiphy_dev: CSIPhy device structure + * + * This API resets CSIPhy hardware + */ +void cam_csiphy_reset(struct csiphy_device *csiphy_dev); + +/** + * @csiphy_dev: CSIPhy device structure + * @arg: Camera control command argument + * + * This API handles the camera control argument reached to CSIPhy + */ +int cam_csiphy_core_cfg(void *csiphy_dev, void *arg); + +/** + * @irq_num: IRQ number + * @data: CSIPhy device structure + * + * This API handles CSIPhy IRQs + */ +irqreturn_t cam_csiphy_irq(int irq_num, void *data); + +/** + * @csiphy_dev: CSIPhy device structure + * + * This API handles the CSIPhy close + */ +void cam_csiphy_shutdown(struct csiphy_device *csiphy_dev); + +#endif /* _CAM_CSIPHY_CORE_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..987da8efbd215c069edd8ea3ff9698aac46c981c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include "cam_csiphy_dev.h" +#include "cam_req_mgr_dev.h" +#include "cam_csiphy_soc.h" +#include "cam_csiphy_core.h" +#include + +static void cam_csiphy_subdev_handle_message( + struct v4l2_subdev *sd, + enum cam_subdev_message_type_t message_type, + uint32_t data) +{ + struct csiphy_device *csiphy_dev = v4l2_get_subdevdata(sd); + + switch (message_type) { + case CAM_SUBDEV_MESSAGE_IRQ_ERR: + CAM_INFO(CAM_CSIPHY, "subdev index : %d CSIPHY index: %d", + csiphy_dev->soc_info.index, data); + if (data == csiphy_dev->soc_info.index) + cam_csiphy_status_dmp(csiphy_dev); + break; + default: + break; + } +} + +static long cam_csiphy_subdev_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + struct csiphy_device *csiphy_dev = v4l2_get_subdevdata(sd); + int rc = 0; + + switch (cmd) { + case VIDIOC_CAM_CONTROL: + rc = cam_csiphy_core_cfg(csiphy_dev, arg); + if (rc != 0) { + CAM_ERR(CAM_CSIPHY, "in configuring the device"); + return rc; + } + break; + default: + CAM_ERR(CAM_CSIPHY, "Wrong ioctl : %d", cmd); + break; + } + + return rc; +} + +static int cam_csiphy_subdev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct csiphy_device *csiphy_dev = + v4l2_get_subdevdata(sd); + + if (!csiphy_dev) { + CAM_ERR(CAM_CSIPHY, "csiphy_dev ptr is NULL"); + return -EINVAL; + } + + mutex_lock(&csiphy_dev->mutex); + cam_csiphy_shutdown(csiphy_dev); + mutex_unlock(&csiphy_dev->mutex); + + return 0; +} + +#ifdef CONFIG_COMPAT +static long cam_csiphy_subdev_compat_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + int32_t rc = 0; + struct cam_control cmd_data; + + if (copy_from_user(&cmd_data, (void __user *)arg, + sizeof(cmd_data))) { + CAM_ERR(CAM_CSIPHY, "Failed to copy from user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + return -EFAULT; + } + + /* All the arguments converted to 64 bit here + * Passed to the api in core.c + */ + switch (cmd) { + case VIDIOC_CAM_CONTROL: + rc = cam_csiphy_subdev_ioctl(sd, cmd, &cmd_data); + break; + default: + CAM_ERR(CAM_CSIPHY, "Invalid compat ioctl cmd: %d", cmd); + rc = -EINVAL; + } + + if (!rc) { + if (copy_to_user((void __user *)arg, &cmd_data, + sizeof(cmd_data))) { + CAM_ERR(CAM_CSIPHY, + "Failed to copy to user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + rc = -EFAULT; + } + } + + return rc; +} +#endif + +static struct v4l2_subdev_core_ops csiphy_subdev_core_ops = { + .ioctl = cam_csiphy_subdev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = cam_csiphy_subdev_compat_ioctl, +#endif +}; + +static const struct v4l2_subdev_ops csiphy_subdev_ops = { + .core = &csiphy_subdev_core_ops, +}; + +static const struct v4l2_subdev_internal_ops csiphy_subdev_intern_ops = { + .close = cam_csiphy_subdev_close, +}; + +static int32_t cam_csiphy_platform_probe(struct platform_device *pdev) +{ + struct cam_cpas_register_params cpas_parms; + struct csiphy_device *new_csiphy_dev; + int32_t rc = 0; + + new_csiphy_dev = devm_kzalloc(&pdev->dev, + sizeof(struct csiphy_device), GFP_KERNEL); + if (!new_csiphy_dev) + return -ENOMEM; + + new_csiphy_dev->ctrl_reg = kzalloc(sizeof(struct csiphy_ctrl_t), + GFP_KERNEL); + if (!new_csiphy_dev->ctrl_reg) { + devm_kfree(&pdev->dev, new_csiphy_dev); + return -ENOMEM; + } + + mutex_init(&new_csiphy_dev->mutex); + new_csiphy_dev->v4l2_dev_str.pdev = pdev; + + new_csiphy_dev->soc_info.pdev = pdev; + new_csiphy_dev->soc_info.dev = &pdev->dev; + new_csiphy_dev->soc_info.dev_name = pdev->name; + new_csiphy_dev->ref_count = 0; + + rc = cam_csiphy_parse_dt_info(pdev, new_csiphy_dev); + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, "DT parsing failed: %d", rc); + goto csiphy_no_resource; + } + + new_csiphy_dev->v4l2_dev_str.internal_ops = + &csiphy_subdev_intern_ops; + new_csiphy_dev->v4l2_dev_str.ops = + &csiphy_subdev_ops; + strlcpy(new_csiphy_dev->device_name, CAMX_CSIPHY_DEV_NAME, + sizeof(new_csiphy_dev->device_name)); + new_csiphy_dev->v4l2_dev_str.name = + new_csiphy_dev->device_name; + new_csiphy_dev->v4l2_dev_str.sd_flags = + (V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS); + new_csiphy_dev->v4l2_dev_str.ent_function = + CAM_CSIPHY_DEVICE_TYPE; + new_csiphy_dev->v4l2_dev_str.msg_cb = + cam_csiphy_subdev_handle_message; + new_csiphy_dev->v4l2_dev_str.token = + new_csiphy_dev; + + rc = cam_register_subdev(&(new_csiphy_dev->v4l2_dev_str)); + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, "cam_register_subdev Failed rc: %d", rc); + goto csiphy_no_resource; + } + + platform_set_drvdata(pdev, &(new_csiphy_dev->v4l2_dev_str.sd)); + + new_csiphy_dev->bridge_intf.device_hdl[0] = -1; + new_csiphy_dev->bridge_intf.device_hdl[1] = -1; + new_csiphy_dev->bridge_intf.ops.get_dev_info = + NULL; + new_csiphy_dev->bridge_intf.ops.link_setup = + NULL; + new_csiphy_dev->bridge_intf.ops.apply_req = + NULL; + + new_csiphy_dev->acquire_count = 0; + new_csiphy_dev->start_dev_count = 0; + new_csiphy_dev->is_acquired_dev_combo_mode = 0; + + cpas_parms.cam_cpas_client_cb = NULL; + cpas_parms.cell_index = new_csiphy_dev->soc_info.index; + cpas_parms.dev = &pdev->dev; + cpas_parms.userdata = new_csiphy_dev; + + strlcpy(cpas_parms.identifier, "csiphy", CAM_HW_IDENTIFIER_LENGTH); + rc = cam_cpas_register_client(&cpas_parms); + if (rc) { + CAM_ERR(CAM_CSIPHY, "CPAS registration failed rc: %d", rc); + goto csiphy_unregister_subdev; + } + CAM_DBG(CAM_CSIPHY, "CPAS registration successful handle=%d", + cpas_parms.client_handle); + new_csiphy_dev->cpas_handle = cpas_parms.client_handle; + + return rc; + +csiphy_unregister_subdev: + cam_unregister_subdev(&(new_csiphy_dev->v4l2_dev_str)); +csiphy_no_resource: + mutex_destroy(&new_csiphy_dev->mutex); + kfree(new_csiphy_dev->ctrl_reg); + devm_kfree(&pdev->dev, new_csiphy_dev); + return rc; +} + + +static int32_t cam_csiphy_device_remove(struct platform_device *pdev) +{ + struct v4l2_subdev *subdev = + platform_get_drvdata(pdev); + struct csiphy_device *csiphy_dev = + v4l2_get_subdevdata(subdev); + + CAM_INFO(CAM_CSIPHY, "device remove invoked"); + cam_cpas_unregister_client(csiphy_dev->cpas_handle); + cam_csiphy_soc_release(csiphy_dev); + mutex_lock(&csiphy_dev->mutex); + cam_csiphy_shutdown(csiphy_dev); + mutex_unlock(&csiphy_dev->mutex); + cam_unregister_subdev(&(csiphy_dev->v4l2_dev_str)); + kfree(csiphy_dev->ctrl_reg); + csiphy_dev->ctrl_reg = NULL; + platform_set_drvdata(pdev, NULL); + v4l2_set_subdevdata(&(csiphy_dev->v4l2_dev_str.sd), NULL); + devm_kfree(&pdev->dev, csiphy_dev); + + return 0; +} + +static const struct of_device_id cam_csiphy_dt_match[] = { + {.compatible = "qcom,csiphy"}, + {} +}; + +MODULE_DEVICE_TABLE(of, cam_csiphy_dt_match); + +static struct platform_driver csiphy_driver = { + .probe = cam_csiphy_platform_probe, + .remove = cam_csiphy_device_remove, + .driver = { + .name = CAMX_CSIPHY_DEV_NAME, + .owner = THIS_MODULE, + .of_match_table = cam_csiphy_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int32_t __init cam_csiphy_init_module(void) +{ + return platform_driver_register(&csiphy_driver); +} + +static void __exit cam_csiphy_exit_module(void) +{ + platform_driver_unregister(&csiphy_driver); +} + +module_init(cam_csiphy_init_module); +module_exit(cam_csiphy_exit_module); +MODULE_DESCRIPTION("CAM CSIPHY driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..a2b07380385f2e3817b72f2edacb622f3f857517 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h @@ -0,0 +1,296 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSIPHY_DEV_H_ +#define _CAM_CSIPHY_DEV_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_soc_util.h" +#include "cam_debug_util.h" +#include "cam_context.h" + +#define MAX_CSIPHY 6 +#define MAX_DPHY_DATA_LN 4 +#define MAX_LRME_V4l2_EVENTS 30 +#define CSIPHY_NUM_CLK_MAX 16 +#define MAX_CSIPHY_REG_ARRAY 70 +#define MAX_CSIPHY_CMN_REG_ARRAY 5 + +#define MAX_LANES 5 +#define MAX_SETTINGS_PER_LANE 43 +#define MAX_DATA_RATES 3 +#define MAX_DATA_RATE_REGS 30 + +#define MAX_REGULATOR 5 +#define CAMX_CSIPHY_DEV_NAME "cam-csiphy-driver" + +#define CSIPHY_POWER_UP 0 +#define CSIPHY_POWER_DOWN 1 + +#define CSIPHY_DEFAULT_PARAMS 0 +#define CSIPHY_LANE_ENABLE 1 +#define CSIPHY_SETTLE_CNT_LOWER_BYTE 2 +#define CSIPHY_SETTLE_CNT_HIGHER_BYTE 3 +#define CSIPHY_DNP_PARAMS 4 +#define CSIPHY_2PH_REGS 5 +#define CSIPHY_3PH_REGS 6 + +#define CSIPHY_MAX_INSTANCES 2 + +#define CAM_CSIPHY_MAX_DPHY_LANES 4 +#define CAM_CSIPHY_MAX_CPHY_LANES 3 + +#define ENABLE_IRQ false + +#undef CDBG +#ifdef CAM_CSIPHY_CORE_DEBUG +#define CDBG(fmt, args...) pr_err(fmt, ##args) +#else +#define CDBG(fmt, args...) pr_debug(fmt, ##args) +#endif + +enum cam_csiphy_state { + CAM_CSIPHY_INIT, + CAM_CSIPHY_ACQUIRE, + CAM_CSIPHY_START, +}; + +/** + * struct csiphy_reg_parms_t + * @mipi_csiphy_glbl_irq_cmd_addr: CSIPhy irq addr + * @mipi_csiphy_interrupt_status0_addr: + * CSIPhy interrupt status addr + * @mipi_csiphy_interrupt_mask0_addr: + * CSIPhy interrupt mask addr + * @mipi_csiphy_interrupt_mask_val: + * CSIPhy interrupt mask val + * @mipi_csiphy_interrupt_clear0_addr: + * CSIPhy interrupt clear addr + * @csiphy_version: CSIPhy Version + * @csiphy_common_array_size: CSIPhy common array size + * @csiphy_reset_array_size: CSIPhy reset array size + * @csiphy_2ph_config_array_size: 2ph settings size + * @csiphy_3ph_config_array_size: 3ph settings size + * @csiphy_cpas_cp_bits_per_phy: CP bits per phy + * @csiphy_cpas_cp_is_interleaved: checks whether cp bits + * are interleaved or not + * @csiphy_cpas_cp_2ph_offset: cp register 2ph offset + * @csiphy_cpas_cp_3ph_offset: cp register 3ph offset + * @csiphy_2ph_clock_lane: clock lane in 2ph + * @csiphy_2ph_combo_ck_ln: clk lane in combo 2ph + */ +struct csiphy_reg_parms_t { +/*MIPI CSI PHY registers*/ + uint32_t mipi_csiphy_glbl_irq_cmd_addr; + uint32_t mipi_csiphy_interrupt_status0_addr; + uint32_t mipi_csiphy_interrupt_mask0_addr; + uint32_t mipi_csiphy_interrupt_mask_val; + uint32_t mipi_csiphy_interrupt_mask_addr; + uint32_t mipi_csiphy_interrupt_clear0_addr; + uint32_t csiphy_version; + uint32_t csiphy_interrupt_status_size; + uint32_t csiphy_common_array_size; + uint32_t csiphy_reset_array_size; + uint32_t csiphy_2ph_config_array_size; + uint32_t csiphy_3ph_config_array_size; + uint32_t csiphy_cpas_cp_bits_per_phy; + uint32_t csiphy_cpas_cp_is_interleaved; + uint32_t csiphy_cpas_cp_2ph_offset; + uint32_t csiphy_cpas_cp_3ph_offset; + uint32_t csiphy_2ph_clock_lane; + uint32_t csiphy_2ph_combo_ck_ln; +}; + +/** + * struct intf_params + * @device_hdl: Device Handle + * @session_hdl: Session Handle + * @ops: KMD operations + * @crm_cb: Callback API pointers + */ +struct intf_params { + int32_t device_hdl[CSIPHY_MAX_INSTANCES]; + int32_t session_hdl[CSIPHY_MAX_INSTANCES]; + int32_t link_hdl[CSIPHY_MAX_INSTANCES]; + struct cam_req_mgr_kmd_ops ops; + struct cam_req_mgr_crm_cb *crm_cb; +}; + +/** + * struct csiphy_reg_t + * @reg_addr: Register address + * @reg_data: Register data + * @delay: Delay + * @csiphy_param_type: CSIPhy parameter type + */ +struct csiphy_reg_t { + int32_t reg_addr; + int32_t reg_data; + int32_t delay; + uint32_t csiphy_param_type; +}; + +struct csiphy_device; + +/* + * struct data_rate_reg_info_t + * @bandwidth: max bandwidth supported by this reg settings + * @data_rate_reg_array_size: number of reg value pairs in the array + * @csiphy_data_rate_regs: array of data rate specific reg value pairs + */ +struct data_rate_reg_info_t { + uint64_t bandwidth; + ssize_t data_rate_reg_array_size; + struct csiphy_reg_t csiphy_data_rate_regs[MAX_DATA_RATE_REGS]; +}; + +/** + * struct data_rate_settings_t + * @num_data_rate_settings: number of valid settings + * present in the data rate settings array + * @data_rate_settings: array of regsettings which are specific to + * data rate + */ +struct data_rate_settings_t { + ssize_t num_data_rate_settings; + struct data_rate_reg_info_t data_rate_settings[MAX_DATA_RATES]; +}; + +/** + * struct csiphy_ctrl_t + * @csiphy_reg: Register address + * @csiphy_common_reg: Common register set + * @csiphy_reset_reg: Reset register set + * @csiphy_2ph_reg: 2phase register set + * @csiphy_2ph_combo_mode_reg: + * 2phase combo register set + * @csiphy_3ph_reg: 3phase register set + * @csiphy_2ph_3ph_mode_reg: + * 2 phase 3phase combo register set + * @getclockvoting: function pointer which + * is used to find the clock voting + * for the sensor output data rate + * @data_rate_settings_table: + * Table which maintains the resgister + * settings specific to data rate + */ +struct csiphy_ctrl_t { + struct csiphy_reg_parms_t csiphy_reg; + struct csiphy_reg_t *csiphy_common_reg; + struct csiphy_reg_t *csiphy_irq_reg; + struct csiphy_reg_t *csiphy_reset_reg; + struct csiphy_reg_t (*csiphy_2ph_reg)[MAX_SETTINGS_PER_LANE]; + struct csiphy_reg_t (*csiphy_2ph_combo_mode_reg)[MAX_SETTINGS_PER_LANE]; + struct csiphy_reg_t (*csiphy_3ph_reg)[MAX_SETTINGS_PER_LANE]; + struct csiphy_reg_t (*csiphy_2ph_3ph_mode_reg)[MAX_SETTINGS_PER_LANE]; + enum cam_vote_level (*getclockvoting)(struct csiphy_device *phy_dev); + struct data_rate_settings_t *data_rates_settings_table; +}; + +/** + * cam_csiphy_param: Provides cmdbuffer structre + * @lane_mask : Lane mask details + * @lane_assign : Lane sensor will be using + * @csiphy_3phase : Mentions DPHY or CPHY + * @combo_mode : Info regarding combo_mode is enable / disable + * @lane_cnt : Total number of lanes + * @reserved + * @3phase : Details whether 3Phase / 2Phase operation + * @settle_time : Settling time in ms + * @settle_time_combo_sensor : Settling time in ms + * @data_rate : Data rate in mbps + * @data_rate_combo_sensor: data rate of combo sensor + * in the the same phy + * + */ +struct cam_csiphy_param { + uint16_t lane_mask; + uint16_t lane_assign; + uint8_t csiphy_3phase; + uint8_t combo_mode; + uint8_t lane_cnt; + uint8_t secure_mode[CSIPHY_MAX_INSTANCES]; + uint64_t settle_time; + uint64_t settle_time_combo_sensor; + uint64_t data_rate; + uint64_t data_rate_combo_sensor; +}; + +/** + * struct csiphy_device + * @device_name: Device name + * @pdev: Platform device + * @irq: Interrupt structure + * @base: Base address + * @hw_version: Hardware Version + * @csiphy_state: CSIPhy state + * @ctrl_reg: CSIPhy control registers + * @num_clk: Number of clocks + * @csiphy_max_clk: Max timer clock rate + * @num_vreg: Number of regulators + * @csiphy_clk: Clock structure + * @csiphy_clk_info: Clock information structure + * @csiphy_vreg: Regulator structure + * @csiphy_reg_ptr: Regulator structure + * @csiphy_3p_clk_info: 3Phase clock information + * @csiphy_3p_clk: 3Phase clocks structure + * @csi_3phase: Is it a 3Phase mode + * @ref_count: Reference count + * @clk_lane: Clock lane + * @acquire_count: Acquire device count + * @start_dev_count: Start count + * @is_acquired_dev_combo_mode: Flag that mentions whether already acquired + * device is for combo mode + * @soc_info: SOC information + * @cpas_handle: CPAS handle + * @config_count: Config reg count + * @csiphy_cpas_cp_reg_mask: CP reg mask for phy instance + */ +struct csiphy_device { + char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH]; + struct mutex mutex; + uint32_t hw_version; + enum cam_csiphy_state csiphy_state; + struct csiphy_ctrl_t *ctrl_reg; + uint32_t csiphy_max_clk; + struct msm_cam_clk_info csiphy_3p_clk_info[2]; + struct clk *csiphy_3p_clk[2]; + unsigned char csi_3phase; + int32_t ref_count; + uint16_t lane_mask[MAX_CSIPHY]; + uint8_t is_csiphy_3phase_hw; + uint8_t is_divisor_32_comp; + uint8_t num_irq_registers; + struct cam_subdev v4l2_dev_str; + struct cam_csiphy_param csiphy_info; + struct intf_params bridge_intf; + uint32_t clk_lane; + uint32_t acquire_count; + uint32_t start_dev_count; + uint32_t is_acquired_dev_combo_mode; + struct cam_hw_soc_info soc_info; + uint32_t cpas_handle; + uint32_t config_count; + uint64_t csiphy_cpas_cp_reg_mask[CSIPHY_MAX_INSTANCES]; +}; + +#endif /* _CAM_CSIPHY_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..c0240184d9f0f83334ddcb30ee3aa5415aafe5e7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c @@ -0,0 +1,475 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include "cam_csiphy_soc.h" +#include "cam_csiphy_core.h" +#include "include/cam_csiphy_1_1_hwreg.h" +#include "include/cam_csiphy_1_0_hwreg.h" +#include "include/cam_csiphy_1_2_hwreg.h" +#include "include/cam_csiphy_1_2_1_hwreg.h" +#include "include/cam_csiphy_1_2_2_hwreg.h" +#include "include/cam_csiphy_2_0_hwreg.h" + +#define CSIPHY_DIVISOR_16 16 +#define CSIPHY_DIVISOR_32 32 +#define CSIPHY_DIVISOR_8 8 +#define BYTES_PER_REGISTER 4 +#define NUM_REGISTER_PER_LINE 4 +#define REG_OFFSET(__start, __i) ((__start) + ((__i) * BYTES_PER_REGISTER)) + +static int cam_io_phy_dump(void __iomem *base_addr, + uint32_t start_offset, int size) +{ + char line_str[128]; + char *p_str; + int i; + uint32_t data; + + CAM_INFO(CAM_CSIPHY, "addr=%pK offset=0x%x size=%d", + base_addr, start_offset, size); + + if (!base_addr || (size <= 0)) + return -EINVAL; + + line_str[0] = '\0'; + p_str = line_str; + for (i = 0; i < size; i++) { + if (i % NUM_REGISTER_PER_LINE == 0) { + snprintf(p_str, 12, "0x%08x: ", + REG_OFFSET(start_offset, i)); + p_str += 11; + } + data = readl_relaxed(base_addr + REG_OFFSET(start_offset, i)); + snprintf(p_str, 9, "%08x ", data); + p_str += 8; + if ((i + 1) % NUM_REGISTER_PER_LINE == 0) { + CAM_ERR(CAM_CSIPHY, "%s", line_str); + line_str[0] = '\0'; + p_str = line_str; + } + } + if (line_str[0] != '\0') + CAM_ERR(CAM_CSIPHY, "%s", line_str); + + return 0; +} + +int32_t cam_csiphy_mem_dmp(struct cam_hw_soc_info *soc_info) +{ + int32_t rc = 0; + resource_size_t size = 0; + void __iomem *addr = NULL; + + if (!soc_info) { + rc = -EINVAL; + CAM_ERR(CAM_CSIPHY, "invalid input %d", rc); + return rc; + } + addr = soc_info->reg_map[0].mem_base; + size = resource_size(soc_info->mem_block[0]); + rc = cam_io_phy_dump(addr, 0, (size >> 2)); + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, "generating dump failed %d", rc); + return rc; + } + return rc; +} + +int32_t cam_csiphy_status_dmp(struct csiphy_device *csiphy_dev) +{ + struct csiphy_reg_parms_t *csiphy_reg = NULL; + int32_t rc = 0; + resource_size_t size = 0; + void __iomem *phy_base = NULL; + int reg_id = 0; + uint32_t irq, status_reg, clear_reg; + + if (!csiphy_dev) { + rc = -EINVAL; + CAM_ERR(CAM_CSIPHY, "invalid input %d", rc); + return rc; + } + + csiphy_reg = &csiphy_dev->ctrl_reg->csiphy_reg; + phy_base = csiphy_dev->soc_info.reg_map[0].mem_base; + status_reg = csiphy_reg->mipi_csiphy_interrupt_status0_addr; + clear_reg = csiphy_reg->mipi_csiphy_interrupt_clear0_addr; + size = csiphy_reg->csiphy_interrupt_status_size; + + CAM_INFO(CAM_CSIPHY, "PHY base addr=%pK offset=0x%x size=%d", + phy_base, status_reg, size); + + if (phy_base != NULL) { + for (reg_id = 0; reg_id < size; reg_id++) { + uint32_t offset; + + offset = status_reg + (0x4 * reg_id); + irq = cam_io_r(phy_base + offset); + offset = clear_reg + (0x4 * reg_id); + cam_io_w_mb(irq, phy_base + offset); + cam_io_w_mb(0, phy_base + offset); + + CAM_INFO(CAM_CSIPHY, + "CSIPHY%d_IRQ_STATUS_ADDR%d = 0x%x", + csiphy_dev->soc_info.index, reg_id, irq); + } + } else { + rc = -EINVAL; + CAM_ERR(CAM_CSIPHY, "phy base is NULL %d", rc); + return rc; + } + return rc; +} + + + +enum cam_vote_level get_clk_vote_default(struct csiphy_device *csiphy_dev) +{ + CAM_DBG(CAM_CSIPHY, "voting for SVS"); + return CAM_SVS_VOTE; +} + +enum cam_vote_level get_clk_voting_dynamic(struct csiphy_device *csiphy_dev) +{ + uint32_t cam_vote_level = 0; + uint32_t last_valid_vote = 0; + struct cam_hw_soc_info *soc_info; + uint64_t phy_data_rate = csiphy_dev->csiphy_info.data_rate; + + soc_info = &csiphy_dev->soc_info; + + if (csiphy_dev->is_acquired_dev_combo_mode) + phy_data_rate = max(phy_data_rate, + csiphy_dev->csiphy_info.data_rate_combo_sensor); + + if (csiphy_dev->csiphy_info.csiphy_3phase) { + if (csiphy_dev->is_divisor_32_comp) + do_div(phy_data_rate, CSIPHY_DIVISOR_32); + else + do_div(phy_data_rate, CSIPHY_DIVISOR_16); + } else { + do_div(phy_data_rate, CSIPHY_DIVISOR_8); + } + + /* round off to next integer */ + phy_data_rate += 1; + + for (cam_vote_level = 0; + cam_vote_level < CAM_MAX_VOTE; cam_vote_level++) { + if (soc_info->clk_level_valid[cam_vote_level] != true) + continue; + + if (soc_info->clk_rate[cam_vote_level][0] > + phy_data_rate) { + CAM_DBG(CAM_CSIPHY, + "match detected %s : %llu:%d level : %d", + soc_info->clk_name[0], + phy_data_rate, + soc_info->clk_rate[cam_vote_level][0], + cam_vote_level); + return cam_vote_level; + } + last_valid_vote = cam_vote_level; + } + return last_valid_vote; +} + +int32_t cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev) +{ + int32_t rc = 0; + struct cam_hw_soc_info *soc_info; + enum cam_vote_level vote_level = CAM_SVS_VOTE; + + soc_info = &csiphy_dev->soc_info; + + if (csiphy_dev->ref_count++) { + CAM_ERR(CAM_CSIPHY, "csiphy refcount = %d", + csiphy_dev->ref_count); + return rc; + } + + vote_level = csiphy_dev->ctrl_reg->getclockvoting(csiphy_dev); + rc = cam_soc_util_enable_platform_resource(soc_info, true, + vote_level, ENABLE_IRQ); + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, "failed to enable platform resources %d", + rc); + return rc; + } + + rc = cam_soc_util_set_src_clk_rate(soc_info, + soc_info->clk_rate[0][soc_info->src_clk_idx]); + + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, "csiphy_clk_set_rate failed rc: %d", rc); + goto csiphy_disable_platform_resource; + } + + cam_csiphy_reset(csiphy_dev); + + return rc; + + +csiphy_disable_platform_resource: + cam_soc_util_disable_platform_resource(soc_info, true, true); + + return rc; +} + +int32_t cam_csiphy_disable_hw(struct csiphy_device *csiphy_dev) +{ + struct cam_hw_soc_info *soc_info; + + if (!csiphy_dev || !csiphy_dev->ref_count) { + CAM_ERR(CAM_CSIPHY, "csiphy dev NULL / ref_count ZERO"); + return 0; + } + soc_info = &csiphy_dev->soc_info; + + if (--csiphy_dev->ref_count) { + CAM_ERR(CAM_CSIPHY, "csiphy refcount = %d", + csiphy_dev->ref_count); + return 0; + } + + cam_csiphy_reset(csiphy_dev); + + cam_soc_util_disable_platform_resource(soc_info, true, true); + + return 0; +} + +int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, + struct csiphy_device *csiphy_dev) +{ + int32_t rc = 0, i = 0; + uint32_t clk_cnt = 0; + char *csi_3p_clk_name = "csi_phy_3p_clk"; + char *csi_3p_clk_src_name = "csiphy_3p_clk_src"; + struct cam_hw_soc_info *soc_info; + + csiphy_dev->is_csiphy_3phase_hw = 0; + soc_info = &csiphy_dev->soc_info; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) { + CAM_ERR(CAM_CSIPHY, "parsing common soc dt(rc %d)", rc); + return rc; + } + + csiphy_dev->is_csiphy_3phase_hw = 0; + + if (of_device_is_compatible(soc_info->dev->of_node, + "qcom,csiphy-v1.0")) { + csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_0_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = + csiphy_2ph_v1_0_combo_mode_reg; + csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_0_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = + csiphy_3ph_v1_0_combo_mode_reg; + csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_0; + csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_1_0; + csiphy_dev->ctrl_reg->csiphy_reset_reg = csiphy_reset_reg_1_0; + csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_0; + csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default; + csiphy_dev->hw_version = CSIPHY_VERSION_V10; + csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; + csiphy_dev->is_divisor_32_comp = false; + csiphy_dev->clk_lane = 0; + csiphy_dev->ctrl_reg->data_rates_settings_table = NULL; + } else if (of_device_is_compatible(soc_info->dev->of_node, + "qcom,csiphy-v1.1")) { + csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_1_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = + csiphy_2ph_v1_1_combo_mode_reg; + csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_1_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = + csiphy_3ph_v1_1_combo_mode_reg; + csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_1; + csiphy_dev->ctrl_reg->csiphy_common_reg = + csiphy_common_reg_1_1; + csiphy_dev->ctrl_reg->csiphy_reset_reg = + csiphy_reset_reg_1_1; + csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_1; + csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default; + csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; + csiphy_dev->is_divisor_32_comp = false; + csiphy_dev->hw_version = CSIPHY_VERSION_V11; + csiphy_dev->clk_lane = 0; + csiphy_dev->ctrl_reg->data_rates_settings_table = NULL; + } else if (of_device_is_compatible(soc_info->dev->of_node, + "qcom,csiphy-v1.2")) { + csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = + csiphy_2ph_v1_2_combo_mode_reg; + csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL; + csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2; + csiphy_dev->ctrl_reg->csiphy_common_reg = + csiphy_common_reg_1_2; + csiphy_dev->ctrl_reg->csiphy_reset_reg = + csiphy_reset_reg_1_2; + csiphy_dev->ctrl_reg->getclockvoting = get_clk_voting_dynamic; + csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2; + csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; + csiphy_dev->is_divisor_32_comp = true; + csiphy_dev->hw_version = CSIPHY_VERSION_V12; + csiphy_dev->clk_lane = 0; + csiphy_dev->ctrl_reg->data_rates_settings_table = + &data_rate_delta_table_1_2; + } else if (of_device_is_compatible(soc_info->dev->of_node, + "qcom,csiphy-v1.2.1")) { + csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_1_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = + csiphy_2ph_v1_2_1_combo_mode_reg; + csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_1_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL; + csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2_1; + csiphy_dev->ctrl_reg->csiphy_common_reg = + csiphy_common_reg_1_2_1; + csiphy_dev->ctrl_reg->csiphy_reset_reg = + csiphy_reset_reg_1_2_1; + csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2_1; + csiphy_dev->ctrl_reg->getclockvoting = get_clk_voting_dynamic; + csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; + csiphy_dev->is_divisor_32_comp = true; + csiphy_dev->hw_version = CSIPHY_VERSION_V121; + csiphy_dev->clk_lane = 0; + csiphy_dev->ctrl_reg->data_rates_settings_table = + &data_rate_delta_table_1_2_1; + } else if (of_device_is_compatible(soc_info->dev->of_node, + "qcom,csiphy-v1.2.2")) { + csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = + csiphy_2ph_v1_2_combo_mode_reg; + csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL; + csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2; + csiphy_dev->ctrl_reg->csiphy_common_reg = + csiphy_common_reg_1_2; + csiphy_dev->ctrl_reg->csiphy_reset_reg = + csiphy_reset_reg_1_2; + csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default; + csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2; + csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; + csiphy_dev->is_divisor_32_comp = false; + csiphy_dev->hw_version = CSIPHY_VERSION_V12; + csiphy_dev->clk_lane = 0; + csiphy_dev->ctrl_reg->data_rates_settings_table = + &data_rate_delta_table_1_2; + } else if (of_device_is_compatible(soc_info->dev->of_node, + "qcom,csiphy-v1.2.2.2")) { + /* settings for lito v2 */ + csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = + csiphy_2ph_v1_2_2_combo_mode_reg; + csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL; + csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2; + csiphy_dev->ctrl_reg->csiphy_common_reg = + csiphy_common_reg_1_2_2; + csiphy_dev->ctrl_reg->csiphy_reset_reg = + csiphy_reset_reg_1_2; + csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default; + csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2_2; + csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; + csiphy_dev->is_divisor_32_comp = false; + csiphy_dev->hw_version = CSIPHY_VERSION_V12; + csiphy_dev->clk_lane = 0; + csiphy_dev->ctrl_reg->data_rates_settings_table = + &data_rate_delta_table_1_2; + } else if (of_device_is_compatible(soc_info->dev->of_node, + "qcom,csiphy-v2.0")) { + csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_0_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = + csiphy_2ph_v2_0_combo_mode_reg; + csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v2_0_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL; + csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_2_0; + csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_2_0; + csiphy_dev->ctrl_reg->csiphy_reset_reg = csiphy_reset_reg_2_0; + csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v2_0; + csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default; + csiphy_dev->hw_version = CSIPHY_VERSION_V20; + csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; + csiphy_dev->is_divisor_32_comp = false; + csiphy_dev->clk_lane = 0; + csiphy_dev->ctrl_reg->data_rates_settings_table = NULL; + } else if (of_device_is_compatible(soc_info->dev->of_node, + "qcom,csiphy-v2.0.1")) { + csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_0_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = + csiphy_2ph_v2_0_combo_mode_reg; + csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v2_0_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL; + csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_2_0; + csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_2_0; + csiphy_dev->ctrl_reg->csiphy_reset_reg = csiphy_reset_reg_2_0; + csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v2_0; + csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default; + csiphy_dev->hw_version = CSIPHY_VERSION_V201; + csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; + csiphy_dev->is_divisor_32_comp = false; + csiphy_dev->clk_lane = 0; + csiphy_dev->ctrl_reg->data_rates_settings_table = + &data_rate_delta_table_2_0; + } else { + CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x", + csiphy_dev->hw_version); + rc = -EINVAL; + return rc; + } + + if (soc_info->num_clk > CSIPHY_NUM_CLK_MAX) { + CAM_ERR(CAM_CSIPHY, "invalid clk count=%d, max is %d", + soc_info->num_clk, CSIPHY_NUM_CLK_MAX); + return -EINVAL; + } + for (i = 0; i < soc_info->num_clk; i++) { + if (!strcmp(soc_info->clk_name[i], + csi_3p_clk_src_name)) { + csiphy_dev->csiphy_3p_clk_info[0].clk_name = + soc_info->clk_name[i]; + csiphy_dev->csiphy_3p_clk_info[0].clk_rate = + soc_info->clk_rate[0][i]; + csiphy_dev->csiphy_3p_clk[0] = + soc_info->clk[i]; + continue; + } else if (!strcmp(soc_info->clk_name[i], + csi_3p_clk_name)) { + csiphy_dev->csiphy_3p_clk_info[1].clk_name = + soc_info->clk_name[i]; + csiphy_dev->csiphy_3p_clk_info[1].clk_rate = + soc_info->clk_rate[0][i]; + csiphy_dev->csiphy_3p_clk[1] = + soc_info->clk[i]; + continue; + } + + CAM_DBG(CAM_CSIPHY, "clk_rate[%d] = %d", clk_cnt, + soc_info->clk_rate[0][clk_cnt]); + clk_cnt++; + } + + csiphy_dev->csiphy_max_clk = + soc_info->clk_rate[0][soc_info->src_clk_idx]; + + rc = cam_soc_util_request_platform_resource(&csiphy_dev->soc_info, + cam_csiphy_irq, csiphy_dev); + + return rc; +} + +int32_t cam_csiphy_soc_release(struct csiphy_device *csiphy_dev) +{ + if (!csiphy_dev) { + CAM_ERR(CAM_CSIPHY, "csiphy dev NULL"); + return 0; + } + + cam_soc_util_release_platform_resource(&csiphy_dev->soc_info); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..3a909e6eb6b90f4bc9a400572f744865076904b3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSIPHY_SOC_H_ +#define _CAM_CSIPHY_SOC_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_csiphy_dev.h" +#include "cam_csiphy_core.h" + +#undef CDBG +#define CDBG(fmt, args...) pr_debug(fmt, ##args) + +#define CSI_3PHASE_HW 1 +#define CSIPHY_VERSION_V35 0x35 +#define CSIPHY_VERSION_V10 0x10 +#define CSIPHY_VERSION_V11 0x11 +#define CSIPHY_VERSION_V12 0x12 +#define CSIPHY_VERSION_V121 0x121 +#define CSIPHY_VERSION_V20 0x20 +#define CSIPHY_VERSION_V201 0x201 + +/** + * @csiphy_dev: CSIPhy device structure + * + * This API release SOC related parameters + */ +int cam_csiphy_soc_release(struct csiphy_device *csiphy_dev); + +/** + * @pdev: Platform device + * @csiphy_dev: CSIPhy device structure + * + * This API parses csiphy device tree information + */ +int cam_csiphy_parse_dt_info(struct platform_device *pdev, + struct csiphy_device *csiphy_dev); + +/** + * @csiphy_dev: CSIPhy device structure + * + * This API enables SOC related parameters + */ +int cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev); + +/** + * @csiphy_dev: CSIPhy device structure + * + * This API disables SOC related parameters + */ +int cam_csiphy_disable_hw(struct csiphy_device *csiphy_dev); + +/** + * @soc_info: Soc info of cam hw driver module + * + * This API dumps memory for the entire mapped region + * (needs to be macro enabled before use) + */ +int cam_csiphy_mem_dmp(struct cam_hw_soc_info *soc_info); + +/** + * @csiphy_dev: CSIPhy device structure + * + * This API dumps memory for the entire status region + */ +int32_t cam_csiphy_status_dmp(struct csiphy_device *csiphy_dev); +#endif /* _CAM_CSIPHY_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_0_hwreg.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_0_hwreg.h new file mode 100644 index 0000000000000000000000000000000000000000..eaedc7b672a88d000293a3d16ba2f5e972244524 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_0_hwreg.h @@ -0,0 +1,349 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSIPHY_1_0_HWREG_H_ +#define _CAM_CSIPHY_1_0_HWREG_H_ + +#include "../cam_csiphy_dev.h" + +struct csiphy_reg_parms_t csiphy_v1_0 = { + .mipi_csiphy_interrupt_status0_addr = 0x8B0, + .mipi_csiphy_interrupt_clear0_addr = 0x858, + .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_interrupt_status_size = 11, + .csiphy_common_array_size = 5, + .csiphy_reset_array_size = 5, + .csiphy_2ph_config_array_size = 14, + .csiphy_3ph_config_array_size = 19, +}; + +struct csiphy_reg_t csiphy_common_reg_1_0[] = { + {0x0814, 0x00, 0x00, CSIPHY_LANE_ENABLE}, + {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_reset_reg_1_0[] = { + {0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE}, + {0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_irq_reg_1_0[] = { + {0x082c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0xFB, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083c, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0840, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0844, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0848, 0xEF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x084c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0850, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0854, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_2ph_v1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x14, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct csiphy_reg_t + csiphy_2ph_v1_0_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x0A, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x14, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x0A, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct csiphy_reg_t csiphy_3ph_v1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x015C, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x035C, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x055C, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct csiphy_reg_t + csiphy_3ph_v1_0_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x015C, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x035C, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x055C, 0x63, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +#endif /* _CAM_CSIPHY_1_0_HWREG_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h new file mode 100644 index 0000000000000000000000000000000000000000..e1db638da5f09ea5645a93b8056b2300e05c7823 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h @@ -0,0 +1,500 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSIPHY_1_1_HWREG_H_ +#define _CAM_CSIPHY_1_1_HWREG_H_ + +#include "../cam_csiphy_dev.h" + +struct csiphy_reg_parms_t csiphy_v1_1 = { + .mipi_csiphy_interrupt_status0_addr = 0x8B0, + .mipi_csiphy_interrupt_clear0_addr = 0x858, + .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_interrupt_status_size = 11, + .csiphy_common_array_size = 5, + .csiphy_reset_array_size = 5, + .csiphy_2ph_config_array_size = 14, + .csiphy_3ph_config_array_size = 43, + .csiphy_2ph_clock_lane = 0x1, + .csiphy_2ph_combo_ck_ln = 0x10, +}; + +struct csiphy_reg_t csiphy_common_reg_1_1[] = { + {0x0814, 0xd5, 0x00, CSIPHY_LANE_ENABLE}, + {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_reset_reg_1_1[] = { + {0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE}, + {0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_irq_reg_1_1[] = { + {0x082c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0xFB, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083c, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0840, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0844, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0848, 0xEF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x084c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0850, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0854, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct +csiphy_reg_t csiphy_2ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct csiphy_reg_t + csiphy_2ph_v1_1_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0760, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct +csiphy_reg_t csiphy_3ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0144, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0188, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x018C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0190, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0980, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x24, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0984, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0988, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09AC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0344, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0388, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x038C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0390, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x24, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0544, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0588, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x058C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0590, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x24, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct csiphy_reg_t + csiphy_3ph_v1_1_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0144, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0188, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x018C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0190, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0980, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0984, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0988, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09AC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0344, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0388, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x038C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0390, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0544, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0588, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x058C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0590, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +#endif /* _CAM_CSIPHY_D5_0_HWREG_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h new file mode 100644 index 0000000000000000000000000000000000000000..2c273b9d5dd9c7cb90124134cb6532b1f47f382b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h @@ -0,0 +1,453 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSIPHY_1_2_1_HWREG_H_ +#define _CAM_CSIPHY_1_2_1_HWREG_H_ + +#include "../cam_csiphy_dev.h" + +struct csiphy_reg_parms_t csiphy_v1_2_1 = { + .mipi_csiphy_interrupt_status0_addr = 0x8B0, + .mipi_csiphy_interrupt_clear0_addr = 0x858, + .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_interrupt_status_size = 11, + .csiphy_common_array_size = 7, + .csiphy_reset_array_size = 5, + .csiphy_2ph_config_array_size = 20, + .csiphy_3ph_config_array_size = 33, + .csiphy_2ph_clock_lane = 0x1, + .csiphy_2ph_combo_ck_ln = 0x10, +}; + +struct csiphy_reg_t csiphy_common_reg_1_2_1[] = { + {0x0814, 0xd5, 0x00, CSIPHY_LANE_ENABLE}, + {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x02, 0x00, CSIPHY_2PH_REGS}, + {0x081C, 0x52, 0x00, CSIPHY_3PH_REGS}, + {0x0800, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_2PH_REGS}, + {0x0800, 0x0E, 0x00, CSIPHY_3PH_REGS}, +}; + +struct csiphy_reg_t csiphy_reset_reg_1_2_1[] = { + {0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE}, + {0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_irq_reg_1_2_1[] = { + {0x082c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0xFB, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083c, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0840, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0844, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0848, 0xEF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x084c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0850, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0854, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct +csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0624, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct csiphy_reg_t + csiphy_2ph_v1_2_1_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0600, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0624, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct +csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0xAF, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0188, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x018C, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0190, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0984, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09AC, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0A90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0xAF, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0388, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x038C, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0390, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AAC, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0B90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0xAF, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0588, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x058C, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0590, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BAC, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct data_rate_settings_t data_rate_delta_table_1_2_1 = { + .num_data_rate_settings = 3, + .data_rate_settings = { + { + /* (2.5 * 10**3 * 2.28) rounded value*/ + .bandwidth = 5700000000, + .data_rate_reg_array_size = 9, + .csiphy_data_rate_regs = { + {0x164, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x364, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x564, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x144, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x344, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x544, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x16C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x36C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x56C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + } + }, + { + /* (3.5 * 10**3 * 2.28) rounded value */ + .bandwidth = 7980000000, + .data_rate_reg_array_size = 12, + .csiphy_data_rate_regs = { + {0x9B4, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0xAB4, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0xBB4, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x164, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x16C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x36C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x56C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + }, + { + /* (4.5 * 10**3 * 2.28) rounded value */ + .bandwidth = 10260000000, + .data_rate_reg_array_size = 12, + .csiphy_data_rate_regs = { + {0x9B4, 0x02, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0xAB4, 0x02, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0xBB4, 0x02, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x164, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x16C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x36C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x56C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + } + } +}; + +#endif /* _CAM_CSIPHY_1_2_1_HWREG_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h new file mode 100644 index 0000000000000000000000000000000000000000..00e6bb30392b174b026edb0a65f9949c90c59af7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSIPHY_1_2_2_HWREG_H_ +#define _CAM_CSIPHY_1_2_2_HWREG_H_ + +#include "../cam_csiphy_dev.h" + +struct csiphy_reg_parms_t csiphy_v1_2_2 = { + .mipi_csiphy_interrupt_status0_addr = 0x8B0, + .mipi_csiphy_interrupt_clear0_addr = 0x858, + .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_interrupt_status_size = 11, + .csiphy_common_array_size = 8, + .csiphy_reset_array_size = 5, + .csiphy_2ph_config_array_size = 18, + .csiphy_3ph_config_array_size = 33, + .csiphy_2ph_clock_lane = 0x1, + .csiphy_2ph_combo_ck_ln = 0x10, +}; + +struct csiphy_reg_t csiphy_common_reg_1_2_2[] = { + {0x0814, 0xd5, 0x00, CSIPHY_LANE_ENABLE}, + {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x5A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x088C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0824, 0x72, 0x00, CSIPHY_2PH_REGS}, +}; + +struct csiphy_reg_t +csiphy_2ph_v1_2_2_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0024, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x005C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0724, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0224, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x025C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0424, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x045C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0624, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, +}; + +#endif /* _CAM_CSIPHY_1_2_2_HWREG_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h new file mode 100644 index 0000000000000000000000000000000000000000..446c8197df8aebdc828deb7a7e80a258a8339716 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h @@ -0,0 +1,432 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSIPHY_1_2_HWREG_H_ +#define _CAM_CSIPHY_1_2_HWREG_H_ + +#include "../cam_csiphy_dev.h" + +struct csiphy_reg_parms_t csiphy_v1_2 = { + .mipi_csiphy_interrupt_status0_addr = 0x8B0, + .mipi_csiphy_interrupt_clear0_addr = 0x858, + .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_interrupt_status_size = 11, + .csiphy_common_array_size = 7, + .csiphy_reset_array_size = 5, + .csiphy_2ph_config_array_size = 18, + .csiphy_3ph_config_array_size = 33, + .csiphy_2ph_clock_lane = 0x1, + .csiphy_2ph_combo_ck_ln = 0x10, +}; + +struct csiphy_reg_t csiphy_common_reg_1_2[] = { + {0x0814, 0xd5, 0x00, CSIPHY_LANE_ENABLE}, + {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x5A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0824, 0x72, 0x00, CSIPHY_2PH_REGS}, +}; + +struct csiphy_reg_t csiphy_reset_reg_1_2[] = { + {0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE}, + {0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_irq_reg_1_2[] = { + {0x082c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0xFB, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083c, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0840, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0844, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0848, 0xEF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x084c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0850, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0854, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct +csiphy_reg_t csiphy_2ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0024, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x005C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0724, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0224, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x025C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0424, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x045C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0624, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x065C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, + }, +}; + +struct csiphy_reg_t +csiphy_2ph_v1_2_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0024, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x005C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0724, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0224, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x025C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0424, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x045C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0624, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, +}; + +struct +csiphy_reg_t csiphy_3ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x015C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0xAF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0188, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x018C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0190, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0984, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x035C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0xAF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0388, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x038C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0390, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x055C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0xAF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0588, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x058C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0590, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct data_rate_settings_t data_rate_delta_table_1_2 = { + .num_data_rate_settings = 3, + .data_rate_settings = { + { + /* (2.5 * 10**3 * 2.28) rounded value*/ + .bandwidth = 5700000000, + .data_rate_reg_array_size = 3, + .csiphy_data_rate_regs = { + {0x144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, + } + }, + { + /* (3.5 * 10**3 * 2.28) rounded value */ + .bandwidth = 7980000000, + .data_rate_reg_array_size = 15, + .csiphy_data_rate_regs = { + {0x9B4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xAB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xBB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xA88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xA80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xB88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xB80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x10C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x30C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x50C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + }, + { + /* (4.5 * 10**3 * 2.28) rounded value */ + .bandwidth = 10260000000, + .data_rate_reg_array_size = 15, + .csiphy_data_rate_regs = { + {0x9B4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xAB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xBB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xA88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xA80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xB88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xB80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x10C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x30C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x50C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + } + } +}; +#endif /* _CAM_CSIPHY_1_2_HWREG_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h new file mode 100644 index 0000000000000000000000000000000000000000..2cd752b44216d66ee6eca2f46d4ddcc0a7834855 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h @@ -0,0 +1,320 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSIPHY_2_0_HWREG_H_ +#define _CAM_CSIPHY_2_0_HWREG_H_ + +#include "../cam_csiphy_dev.h" + +struct csiphy_reg_parms_t csiphy_v2_0 = { + .mipi_csiphy_interrupt_status0_addr = 0x8B0, + .mipi_csiphy_interrupt_clear0_addr = 0x858, + .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_interrupt_status_size = 11, + .csiphy_common_array_size = 8, + .csiphy_reset_array_size = 5, + .csiphy_2ph_config_array_size = 15, + .csiphy_3ph_config_array_size = 17, + .csiphy_2ph_clock_lane = 0x1, + .csiphy_2ph_combo_ck_ln = 0x10, +}; + +struct csiphy_reg_t csiphy_common_reg_2_0[] = { + {0x0814, 0x00, 0x00, CSIPHY_LANE_ENABLE}, + {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x06, 0x00, CSIPHY_3PH_REGS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x00, 0x00, CSIPHY_2PH_REGS}, + {0x0364, 0x00, 0x00, CSIPHY_2PH_REGS}, + {0x0564, 0x00, 0x00, CSIPHY_2PH_REGS}, +}; + +struct csiphy_reg_t csiphy_reset_reg_2_0[] = { + {0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE}, + {0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_irq_reg_2_0[] = { + {0x082c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0xff, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0xfb, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0840, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0844, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0848, 0xef, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x084c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0850, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0854, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_2ph_v2_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0030, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x04, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000C, 0xFF, 0x00, CSIPHY_DNP_PARAMS}, + {0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x3F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0730, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x3F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0230, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x04, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020C, 0xFF, 0x00, CSIPHY_DNP_PARAMS}, + {0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x3F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0430, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x04, 0x00, CSIPHY_DNP_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040C, 0xFF, 0x00, CSIPHY_DNP_PARAMS}, + {0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x3F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0630, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x04, 0x00, CSIPHY_DNP_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0xFF, 0x00, CSIPHY_DNP_PARAMS}, + {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x3F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct csiphy_reg_t + csiphy_2ph_v2_0_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0030, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x04, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000C, 0xFF, 0x00, CSIPHY_DNP_PARAMS}, + {0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x3F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0730, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x3F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0230, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x04, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020C, 0xFF, 0x00, CSIPHY_DNP_PARAMS}, + {0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x3F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0430, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040C, 0xFF, 0x00, CSIPHY_DNP_PARAMS}, + {0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x3F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0630, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x3F, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct csiphy_reg_t csiphy_3ph_v2_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x015C, 0x23, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0x70, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016C, 0x17, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x035C, 0x23, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0x70, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036C, 0x17, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x055C, 0x23, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0x70, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056C, 0x17, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct data_rate_settings_t data_rate_delta_table_2_0 = { + .num_data_rate_settings = 2, + .data_rate_settings = { + { + /* (2 * 10**9 * 2.28) rounded value*/ + .bandwidth = 4560000000, + .data_rate_reg_array_size = 3, + .csiphy_data_rate_regs = { + {0x164, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x364, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x564, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + } + }, + { + /* (2.5 * 10**9 * 2.28) rounded value*/ + .bandwidth = 5700000000, + .data_rate_reg_array_size = 3, + .csiphy_data_rate_regs = { + {0x164, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x364, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x564, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + } + }, + } +}; + +#endif /* _CAM_CSIPHY_2_0_HWREG_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..a0544de6674cae2ccb316609308c75e7318054f6 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_eeprom_dev.o cam_eeprom_core.o cam_eeprom_soc.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c new file mode 100644 index 0000000000000000000000000000000000000000..3e5b3c45ead2346e29a0c41f8940f2d3da600dfc --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c @@ -0,0 +1,1531 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +#include "cam_eeprom_core.h" +#include "cam_eeprom_soc.h" +#include "cam_debug_util.h" +#include "cam_common_util.h" +#include "cam_packet_util.h" + +#define MAX_READ_SIZE 0x7FFFF + +/** + * cam_eeprom_read_memory() - read map data into buffer + * @e_ctrl: eeprom control struct + * @block: block to be read + * + * This function iterates through blocks stored in block->map, reads each + * region and concatenate them into the pre-allocated block->mapdata + */ +static int cam_eeprom_read_memory(struct cam_eeprom_ctrl_t *e_ctrl, + struct cam_eeprom_memory_block_t *block) +{ + int rc = 0; + int j; + struct cam_sensor_i2c_reg_setting i2c_reg_settings = {0}; + struct cam_sensor_i2c_reg_array i2c_reg_array = {0}; + struct cam_eeprom_memory_map_t *emap = block->map; + struct cam_eeprom_soc_private *eb_info = NULL; + uint8_t *memptr = block->mapdata; + + if (!e_ctrl) { + CAM_ERR(CAM_EEPROM, "e_ctrl is NULL"); + return -EINVAL; + } + + eb_info = (struct cam_eeprom_soc_private *)e_ctrl->soc_info.soc_private; + + for (j = 0; j < block->num_map; j++) { + CAM_DBG(CAM_EEPROM, "slave-addr = 0x%X", emap[j].saddr); + if (emap[j].saddr) { + eb_info->i2c_info.slave_addr = emap[j].saddr; + rc = cam_eeprom_update_i2c_info(e_ctrl, + &eb_info->i2c_info); + if (rc) { + CAM_ERR(CAM_EEPROM, + "failed: to update i2c info rc %d", + rc); + return rc; + } + } + + if (emap[j].page.valid_size) { + i2c_reg_settings.addr_type = emap[j].page.addr_type; + i2c_reg_settings.data_type = emap[j].page.data_type; + i2c_reg_settings.size = 1; + i2c_reg_array.reg_addr = emap[j].page.addr; + i2c_reg_array.reg_data = emap[j].page.data; + i2c_reg_array.delay = emap[j].page.delay; + i2c_reg_settings.reg_setting = &i2c_reg_array; + rc = camera_io_dev_write(&e_ctrl->io_master_info, + &i2c_reg_settings); + if (rc) { + CAM_ERR(CAM_EEPROM, "page write failed rc %d", + rc); + return rc; + } + } + + if (emap[j].pageen.valid_size) { + i2c_reg_settings.addr_type = emap[j].pageen.addr_type; + i2c_reg_settings.data_type = emap[j].pageen.data_type; + i2c_reg_settings.size = 1; + i2c_reg_array.reg_addr = emap[j].pageen.addr; + i2c_reg_array.reg_data = emap[j].pageen.data; + i2c_reg_array.delay = emap[j].pageen.delay; + i2c_reg_settings.reg_setting = &i2c_reg_array; + rc = camera_io_dev_write(&e_ctrl->io_master_info, + &i2c_reg_settings); + if (rc) { + CAM_ERR(CAM_EEPROM, "page enable failed rc %d", + rc); + return rc; + } + } + + if (emap[j].poll.valid_size) { + rc = camera_io_dev_poll(&e_ctrl->io_master_info, + emap[j].poll.addr, emap[j].poll.data, + 0, emap[j].poll.addr_type, + emap[j].poll.data_type, + emap[j].poll.delay); + if (rc) { + CAM_ERR(CAM_EEPROM, "poll failed rc %d", + rc); + return rc; + } + } + + if (emap[j].mem.valid_size) { + rc = camera_io_dev_read_seq(&e_ctrl->io_master_info, + emap[j].mem.addr, memptr, + emap[j].mem.addr_type, + emap[j].mem.data_type, + emap[j].mem.valid_size); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "read failed rc %d", + rc); + return rc; + } + memptr += emap[j].mem.valid_size; + } + + if (emap[j].pageen.valid_size) { + i2c_reg_settings.addr_type = emap[j].pageen.addr_type; + i2c_reg_settings.data_type = emap[j].pageen.data_type; + i2c_reg_settings.size = 1; + i2c_reg_array.reg_addr = emap[j].pageen.addr; + i2c_reg_array.reg_data = 0; + i2c_reg_array.delay = emap[j].pageen.delay; + i2c_reg_settings.reg_setting = &i2c_reg_array; + rc = camera_io_dev_write(&e_ctrl->io_master_info, + &i2c_reg_settings); + if (rc) { + CAM_ERR(CAM_EEPROM, + "page disable failed rc %d", + rc); + return rc; + } + } + } + return rc; +} + +/** + * cam_eeprom_power_up - Power up eeprom hardware + * @e_ctrl: ctrl structure + * @power_info: power up/down info for eeprom + * + * Returns success or failure + */ +static int cam_eeprom_power_up(struct cam_eeprom_ctrl_t *e_ctrl, + struct cam_sensor_power_ctrl_t *power_info) +{ + int32_t rc = 0; + struct cam_hw_soc_info *soc_info = + &e_ctrl->soc_info; + + /* Parse and fill vreg params for power up settings */ + rc = msm_camera_fill_vreg_params( + &e_ctrl->soc_info, + power_info->power_setting, + power_info->power_setting_size); + if (rc) { + CAM_ERR(CAM_EEPROM, + "failed to fill power up vreg params rc:%d", rc); + return rc; + } + + /* Parse and fill vreg params for power down settings*/ + rc = msm_camera_fill_vreg_params( + &e_ctrl->soc_info, + power_info->power_down_setting, + power_info->power_down_setting_size); + if (rc) { + CAM_ERR(CAM_EEPROM, + "failed to fill power down vreg params rc:%d", rc); + return rc; + } + + power_info->dev = soc_info->dev; + + rc = cam_sensor_core_power_up(power_info, soc_info); + if (rc) { + CAM_ERR(CAM_EEPROM, "failed in eeprom power up rc %d", rc); + return rc; + } + + if (e_ctrl->io_master_info.master_type == CCI_MASTER) { + rc = camera_io_init(&(e_ctrl->io_master_info)); + if (rc) { + CAM_ERR(CAM_EEPROM, "cci_init failed"); + return -EINVAL; + } + } + return rc; +} + +/** + * cam_eeprom_power_down - Power down eeprom hardware + * @e_ctrl: ctrl structure + * + * Returns success or failure + */ +static int cam_eeprom_power_down(struct cam_eeprom_ctrl_t *e_ctrl) +{ + struct cam_sensor_power_ctrl_t *power_info; + struct cam_hw_soc_info *soc_info; + struct cam_eeprom_soc_private *soc_private; + int rc = 0; + + if (!e_ctrl) { + CAM_ERR(CAM_EEPROM, "failed: e_ctrl %pK", e_ctrl); + return -EINVAL; + } + + soc_private = + (struct cam_eeprom_soc_private *)e_ctrl->soc_info.soc_private; + power_info = &soc_private->power_info; + soc_info = &e_ctrl->soc_info; + + if (!power_info) { + CAM_ERR(CAM_EEPROM, "failed: power_info %pK", power_info); + return -EINVAL; + } + rc = cam_sensor_util_power_down(power_info, soc_info); + if (rc) { + CAM_ERR(CAM_EEPROM, "power down the core is failed:%d", rc); + return rc; + } + + if (e_ctrl->io_master_info.master_type == CCI_MASTER) + camera_io_release(&(e_ctrl->io_master_info)); + + return rc; +} + +/** + * cam_eeprom_match_id - match eeprom id + * @e_ctrl: ctrl structure + * + * Returns success or failure + */ +static int cam_eeprom_match_id(struct cam_eeprom_ctrl_t *e_ctrl) +{ + int rc; + struct camera_io_master *client = &e_ctrl->io_master_info; + uint8_t id[2]; + + rc = cam_spi_query_id(client, 0, CAMERA_SENSOR_I2C_TYPE_WORD, + &id[0], 2); + if (rc) + return rc; + CAM_DBG(CAM_EEPROM, "read 0x%x 0x%x, check 0x%x 0x%x", + id[0], id[1], client->spi_client->mfr_id0, + client->spi_client->device_id0); + if (id[0] != client->spi_client->mfr_id0 + || id[1] != client->spi_client->device_id0) + return -ENODEV; + return 0; +} + +/** + * cam_eeprom_parse_read_memory_map - Parse memory map + * @of_node: device node + * @e_ctrl: ctrl structure + * + * Returns success or failure + */ +int32_t cam_eeprom_parse_read_memory_map(struct device_node *of_node, + struct cam_eeprom_ctrl_t *e_ctrl) +{ + int32_t rc = 0; + struct cam_eeprom_soc_private *soc_private; + struct cam_sensor_power_ctrl_t *power_info; + + if (!e_ctrl) { + CAM_ERR(CAM_EEPROM, "failed: e_ctrl is NULL"); + return -EINVAL; + } + + soc_private = + (struct cam_eeprom_soc_private *)e_ctrl->soc_info.soc_private; + power_info = &soc_private->power_info; + + rc = cam_eeprom_parse_dt_memory_map(of_node, &e_ctrl->cal_data); + if (rc) { + CAM_ERR(CAM_EEPROM, "failed: eeprom dt parse rc %d", rc); + return rc; + } + rc = cam_eeprom_power_up(e_ctrl, power_info); + if (rc) { + CAM_ERR(CAM_EEPROM, "failed: eeprom power up rc %d", rc); + goto data_mem_free; + } + + e_ctrl->cam_eeprom_state = CAM_EEPROM_CONFIG; + if (e_ctrl->eeprom_device_type == MSM_CAMERA_SPI_DEVICE) { + rc = cam_eeprom_match_id(e_ctrl); + if (rc) { + CAM_DBG(CAM_EEPROM, "eeprom not matching %d", rc); + goto power_down; + } + } + rc = cam_eeprom_read_memory(e_ctrl, &e_ctrl->cal_data); + if (rc) { + CAM_ERR(CAM_EEPROM, "read_eeprom_memory failed"); + goto power_down; + } + + rc = cam_eeprom_power_down(e_ctrl); + if (rc) + CAM_ERR(CAM_EEPROM, "failed: eeprom power down rc %d", rc); + + e_ctrl->cam_eeprom_state = CAM_EEPROM_ACQUIRE; + return rc; +power_down: + cam_eeprom_power_down(e_ctrl); +data_mem_free: + vfree(e_ctrl->cal_data.mapdata); + vfree(e_ctrl->cal_data.map); + e_ctrl->cal_data.num_data = 0; + e_ctrl->cal_data.num_map = 0; + e_ctrl->cam_eeprom_state = CAM_EEPROM_ACQUIRE; + return rc; +} + +/** + * cam_eeprom_get_dev_handle - get device handle + * @e_ctrl: ctrl structure + * @arg: Camera control command argument + * + * Returns success or failure + */ +static int32_t cam_eeprom_get_dev_handle(struct cam_eeprom_ctrl_t *e_ctrl, + void *arg) +{ + struct cam_sensor_acquire_dev eeprom_acq_dev; + struct cam_create_dev_hdl bridge_params; + struct cam_control *cmd = (struct cam_control *)arg; + + if (e_ctrl->bridge_intf.device_hdl != -1) { + CAM_ERR(CAM_EEPROM, "Device is already acquired"); + return -EFAULT; + } + if (copy_from_user(&eeprom_acq_dev, + u64_to_user_ptr(cmd->handle), + sizeof(eeprom_acq_dev))) { + CAM_ERR(CAM_EEPROM, + "EEPROM:ACQUIRE_DEV: copy from user failed"); + return -EFAULT; + } + + bridge_params.session_hdl = eeprom_acq_dev.session_handle; + bridge_params.ops = &e_ctrl->bridge_intf.ops; + bridge_params.v4l2_sub_dev_flag = 0; + bridge_params.media_entity_flag = 0; + bridge_params.priv = e_ctrl; + bridge_params.dev_id = CAM_EEPROM; + + eeprom_acq_dev.device_handle = + cam_create_device_hdl(&bridge_params); + if (eeprom_acq_dev.device_handle <= 0) { + CAM_ERR(CAM_EEPROM, "Can not create device handle"); + return -EFAULT; + } + e_ctrl->bridge_intf.device_hdl = eeprom_acq_dev.device_handle; + e_ctrl->bridge_intf.session_hdl = eeprom_acq_dev.session_handle; + + CAM_DBG(CAM_EEPROM, "Device Handle: %d", eeprom_acq_dev.device_handle); + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &eeprom_acq_dev, sizeof(struct cam_sensor_acquire_dev))) { + CAM_ERR(CAM_EEPROM, "EEPROM:ACQUIRE_DEV: copy to user failed"); + return -EFAULT; + } + return 0; +} + +/** + * cam_eeprom_update_slaveInfo - Update slave info + * @e_ctrl: ctrl structure + * @cmd_buf: command buffer + * + * Returns success or failure + */ +static int32_t cam_eeprom_update_slaveInfo(struct cam_eeprom_ctrl_t *e_ctrl, + void *cmd_buf) +{ + int32_t rc = 0; + struct cam_eeprom_soc_private *soc_private; + struct cam_cmd_i2c_info *cmd_i2c_info = NULL; + + soc_private = + (struct cam_eeprom_soc_private *)e_ctrl->soc_info.soc_private; + cmd_i2c_info = (struct cam_cmd_i2c_info *)cmd_buf; + soc_private->i2c_info.slave_addr = cmd_i2c_info->slave_addr; + soc_private->i2c_info.i2c_freq_mode = cmd_i2c_info->i2c_freq_mode; + + rc = cam_eeprom_update_i2c_info(e_ctrl, + &soc_private->i2c_info); + CAM_DBG(CAM_EEPROM, "Slave addr: 0x%x Freq Mode: %d", + soc_private->i2c_info.slave_addr, + soc_private->i2c_info.i2c_freq_mode); + + return rc; +} + +/** + * cam_eeprom_parse_memory_map - Parse memory map info + * @data: memory block data + * @cmd_buf: command buffer + * @cmd_length: command buffer length + * @num_map: memory map size + * @cmd_length_bytes: command length processed in this function + * + * Returns success or failure + */ +static int32_t cam_eeprom_parse_memory_map( + struct cam_eeprom_memory_block_t *data, + void *cmd_buf, int cmd_length, uint32_t *cmd_length_bytes, + int *num_map, size_t remain_buf_len) +{ + int32_t rc = 0; + int32_t cnt = 0; + int32_t processed_size = 0; + uint8_t generic_op_code; + struct cam_eeprom_memory_map_t *map = data->map; + struct common_header *cmm_hdr = + (struct common_header *)cmd_buf; + uint16_t cmd_length_in_bytes = 0; + struct cam_cmd_i2c_random_wr *i2c_random_wr = NULL; + struct cam_cmd_i2c_continuous_rd *i2c_cont_rd = NULL; + struct cam_cmd_conditional_wait *i2c_poll = NULL; + struct cam_cmd_unconditional_wait *i2c_uncond_wait = NULL; + size_t validate_size = 0; + + generic_op_code = cmm_hdr->fifth_byte; + + if (cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_WR) + validate_size = sizeof(struct cam_cmd_i2c_random_wr); + else if (cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_I2C_CONT_RD) + validate_size = sizeof(struct cam_cmd_i2c_continuous_rd); + else if (cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_WAIT) + validate_size = sizeof(struct cam_cmd_unconditional_wait); + + if (remain_buf_len < validate_size || + *num_map >= (MSM_EEPROM_MAX_MEM_MAP_CNT * + MSM_EEPROM_MEMORY_MAP_MAX_SIZE)) { + CAM_ERR(CAM_EEPROM, "not enough buffer"); + return -EINVAL; + } + switch (cmm_hdr->cmd_type) { + case CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_WR: + i2c_random_wr = (struct cam_cmd_i2c_random_wr *)cmd_buf; + + if (i2c_random_wr->header.count == 0 || + i2c_random_wr->header.count >= MSM_EEPROM_MAX_MEM_MAP_CNT || + (size_t)*num_map >= ((MSM_EEPROM_MAX_MEM_MAP_CNT * + MSM_EEPROM_MEMORY_MAP_MAX_SIZE) - + i2c_random_wr->header.count)) { + CAM_ERR(CAM_EEPROM, "OOB Error"); + return -EINVAL; + } + cmd_length_in_bytes = sizeof(struct cam_cmd_i2c_random_wr) + + ((i2c_random_wr->header.count - 1) * + sizeof(struct i2c_random_wr_payload)); + + if (cmd_length_in_bytes > remain_buf_len) { + CAM_ERR(CAM_EEPROM, "Not enough buffer remaining"); + return -EINVAL; + } + for (cnt = 0; cnt < (i2c_random_wr->header.count); + cnt++) { + map[*num_map + cnt].page.addr = + i2c_random_wr->random_wr_payload[cnt].reg_addr; + map[*num_map + cnt].page.addr_type = + i2c_random_wr->header.addr_type; + map[*num_map + cnt].page.data = + i2c_random_wr->random_wr_payload[cnt].reg_data; + map[*num_map + cnt].page.data_type = + i2c_random_wr->header.data_type; + map[*num_map + cnt].page.valid_size = 1; + } + + *num_map += (i2c_random_wr->header.count - 1); + cmd_buf += cmd_length_in_bytes / sizeof(int32_t); + processed_size += + cmd_length_in_bytes; + break; + case CAMERA_SENSOR_CMD_TYPE_I2C_CONT_RD: + i2c_cont_rd = (struct cam_cmd_i2c_continuous_rd *)cmd_buf; + cmd_length_in_bytes = sizeof(struct cam_cmd_i2c_continuous_rd); + + if (i2c_cont_rd->header.count >= U32_MAX - data->num_data) { + CAM_ERR(CAM_EEPROM, + "int overflow on eeprom memory block"); + return -EINVAL; + } + map[*num_map].mem.addr = i2c_cont_rd->reg_addr; + map[*num_map].mem.addr_type = i2c_cont_rd->header.addr_type; + map[*num_map].mem.data_type = i2c_cont_rd->header.data_type; + map[*num_map].mem.valid_size = + i2c_cont_rd->header.count; + cmd_buf += cmd_length_in_bytes / sizeof(int32_t); + processed_size += + cmd_length_in_bytes; + data->num_data += map[*num_map].mem.valid_size; + break; + case CAMERA_SENSOR_CMD_TYPE_WAIT: + if (generic_op_code == + CAMERA_SENSOR_WAIT_OP_HW_UCND || + generic_op_code == + CAMERA_SENSOR_WAIT_OP_SW_UCND) { + i2c_uncond_wait = + (struct cam_cmd_unconditional_wait *)cmd_buf; + cmd_length_in_bytes = + sizeof(struct cam_cmd_unconditional_wait); + + if (*num_map < 1) { + CAM_ERR(CAM_EEPROM, + "invalid map number, num_map=%d", + *num_map); + return -EINVAL; + } + + /* + * Though delay is added all of them, but delay will + * be applicable to only one of them as only one of + * them will have valid_size set to >= 1. + */ + map[*num_map - 1].mem.delay = i2c_uncond_wait->delay; + map[*num_map - 1].page.delay = i2c_uncond_wait->delay; + map[*num_map - 1].pageen.delay = i2c_uncond_wait->delay; + } else if (generic_op_code == + CAMERA_SENSOR_WAIT_OP_COND) { + i2c_poll = (struct cam_cmd_conditional_wait *)cmd_buf; + cmd_length_in_bytes = + sizeof(struct cam_cmd_conditional_wait); + + map[*num_map].poll.addr = i2c_poll->reg_addr; + map[*num_map].poll.addr_type = i2c_poll->addr_type; + map[*num_map].poll.data = i2c_poll->reg_data; + map[*num_map].poll.data_type = i2c_poll->data_type; + map[*num_map].poll.delay = i2c_poll->timeout; + map[*num_map].poll.valid_size = 1; + } + cmd_buf += cmd_length_in_bytes / sizeof(int32_t); + processed_size += + cmd_length_in_bytes; + break; + default: + break; + } + + *cmd_length_bytes = processed_size; + return rc; +} + +static struct i2c_settings_list* + cam_eeprom_get_i2c_ptr(struct i2c_settings_array *i2c_reg_settings, + uint32_t size) +{ + struct i2c_settings_list *tmp; + + tmp = kzalloc(sizeof(struct i2c_settings_list), GFP_KERNEL); + + if (tmp != NULL) + list_add_tail(&(tmp->list), + &(i2c_reg_settings->list_head)); + else + return NULL; + + tmp->seq_settings.reg_data = + kcalloc(size, sizeof(uint8_t), GFP_KERNEL); + if (tmp->seq_settings.reg_data == NULL) { + list_del(&(tmp->list)); + kfree(tmp); + tmp = NULL; + return NULL; + } + tmp->seq_settings.size = size; + + return tmp; +} + +static int32_t cam_eeprom_handle_continuous_write( + struct cam_eeprom_ctrl_t *e_ctrl, + struct cam_cmd_i2c_continuous_wr *cam_cmd_i2c_continuous_wr, + struct i2c_settings_array *i2c_reg_settings, + uint32_t *cmd_length_in_bytes, int32_t *offset, + struct list_head **list) +{ + struct i2c_settings_list *i2c_list; + int32_t rc = 0, cnt = 0; + + + CAM_DBG(CAM_EEPROM, "Total Size: %d", + cam_cmd_i2c_continuous_wr->header.count); + + i2c_list = cam_eeprom_get_i2c_ptr(i2c_reg_settings, + cam_cmd_i2c_continuous_wr->header.count); + if (i2c_list == NULL || + i2c_list->seq_settings.reg_data == NULL) { + CAM_ERR(CAM_SENSOR, "Failed in allocating i2c_list"); + return -ENOMEM; + } + + *cmd_length_in_bytes = (sizeof(struct i2c_rdwr_header) + + sizeof(cam_cmd_i2c_continuous_wr->reg_addr) + + sizeof(struct cam_cmd_read) * + (cam_cmd_i2c_continuous_wr->header.count)); + if (cam_cmd_i2c_continuous_wr->header.op_code == + CAMERA_SENSOR_I2C_OP_CONT_WR_BRST) + i2c_list->op_code = CAM_SENSOR_I2C_WRITE_BURST; + else if (cam_cmd_i2c_continuous_wr->header.op_code == + CAMERA_SENSOR_I2C_OP_CONT_WR_SEQN) + i2c_list->op_code = CAM_SENSOR_I2C_WRITE_SEQ; + else { + rc = -EINVAL; + goto deallocate_i2c_list; + } + + i2c_list->seq_settings.addr_type = + cam_cmd_i2c_continuous_wr->header.addr_type; + + CAM_ERR(CAM_EEPROM, "Write Address: 0x%x", + cam_cmd_i2c_continuous_wr->reg_addr); + if (i2c_list->op_code == CAM_SENSOR_I2C_WRITE_SEQ) { + i2c_list->op_code = CAM_SENSOR_I2C_WRITE_RANDOM; + e_ctrl->eebin_info.start_address = + cam_cmd_i2c_continuous_wr->reg_addr; + e_ctrl->eebin_info.size = + cam_cmd_i2c_continuous_wr->header.count; + CAM_DBG(CAM_EEPROM, "Header Count: %d", + cam_cmd_i2c_continuous_wr->header.count); + e_ctrl->eebin_info.is_valid = 1; + + i2c_list->seq_settings.reg_addr = + cam_cmd_i2c_continuous_wr->reg_addr; + } else + CAM_ERR(CAM_EEPROM, "Burst Mode Not Supported\n"); + + (*offset) += cnt; + *list = &(i2c_list->list); + return rc; +deallocate_i2c_list: + kfree(i2c_list); + return rc; +} + +static int32_t cam_eeprom_handle_delay( + uint32_t **cmd_buf, + uint16_t generic_op_code, + struct i2c_settings_array *i2c_reg_settings, + uint32_t offset, uint32_t *byte_cnt, + struct list_head *list_ptr, + size_t remain_buf_len) +{ + int32_t rc = 0; + struct i2c_settings_list *i2c_list = NULL; + struct cam_cmd_unconditional_wait *cmd_uncond_wait = + (struct cam_cmd_unconditional_wait *) *cmd_buf; + + if (remain_buf_len < (sizeof(struct cam_cmd_unconditional_wait))) { + CAM_ERR(CAM_EEPROM, "Not Enough buffer"); + return -EINVAL; + } + + if (list_ptr == NULL) { + CAM_ERR(CAM_SENSOR, "Invalid list ptr"); + return -EINVAL; + } + + if (offset > 0) { + i2c_list = + list_entry(list_ptr, struct i2c_settings_list, list); + if (generic_op_code == + CAMERA_SENSOR_WAIT_OP_HW_UCND) + i2c_list->i2c_settings.reg_setting[offset - 1].delay = + cmd_uncond_wait->delay; + else + i2c_list->i2c_settings.delay = + cmd_uncond_wait->delay; + (*cmd_buf) += + sizeof( + struct cam_cmd_unconditional_wait) / sizeof(uint32_t); + (*byte_cnt) += + sizeof( + struct cam_cmd_unconditional_wait); + } else { + CAM_ERR(CAM_SENSOR, "Delay Rxed before any buffer: %d", offset); + return -EINVAL; + } + + return rc; +} + +/** + * cam_eeprom_parse_write_memory_packet - Write eeprom packet + * @csl_packet: csl packet received + * @e_ctrl: ctrl structure + * + * Returns success or failure + */ +static int32_t cam_eeprom_parse_write_memory_packet( + struct cam_packet *csl_packet, + struct cam_eeprom_ctrl_t *e_ctrl) +{ + struct cam_cmd_buf_desc *cmd_desc = NULL; + uint32_t *offset = NULL; + int32_t i, rc = 0; + uint32_t *cmd_buf = NULL; + uintptr_t generic_pkt_addr; + size_t pkt_len = 0; + size_t remain_len = 0; + uint32_t total_cmd_buf_in_bytes = 0; + uint32_t processed_cmd_buf_in_bytes = 0; + struct common_header *cmm_hdr = NULL; + uint32_t cmd_length_in_bytes = 0; + struct cam_cmd_i2c_info *i2c_info = NULL; + + + offset = (uint32_t *)&csl_packet->payload; + offset += (csl_packet->cmd_buf_offset / sizeof(uint32_t)); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + + CAM_DBG(CAM_EEPROM, "Number of Command Buffers: %d", + csl_packet->num_cmd_buf); + for (i = 0; i < csl_packet->num_cmd_buf; i++) { + struct list_head *list = NULL; + uint16_t generic_op_code; + uint32_t off = 0; + int master; + struct cam_sensor_cci_client *cci; + + total_cmd_buf_in_bytes = cmd_desc[i].length; + processed_cmd_buf_in_bytes = 0; + + if (!total_cmd_buf_in_bytes) + continue; + + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, + &generic_pkt_addr, &pkt_len); + if (rc) { + CAM_ERR(CAM_EEPROM, "Failed to get cpu buf"); + return rc; + } + + cmd_buf = (uint32_t *)generic_pkt_addr; + if (!cmd_buf) { + CAM_ERR(CAM_EEPROM, "invalid cmd buf"); + rc = -EINVAL; + goto end; + } + + if ((pkt_len < sizeof(struct common_header) || + (cmd_desc[i].offset) > (pkt_len - + sizeof(struct common_header)))) { + CAM_ERR(CAM_EEPROM, "Not enough buffer"); + rc = -EINVAL; + goto end; + } + + remain_len = pkt_len - cmd_desc[i].offset; + cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); + + if (total_cmd_buf_in_bytes > remain_len) { + CAM_ERR(CAM_EEPROM, "Not enough buffer for command"); + rc = -EINVAL; + goto end; + } + + master = e_ctrl->io_master_info.master_type; + cci = e_ctrl->io_master_info.cci_client; + while (processed_cmd_buf_in_bytes < total_cmd_buf_in_bytes) { + if ((remain_len - processed_cmd_buf_in_bytes) < + sizeof(struct common_header)) { + CAM_ERR(CAM_EEPROM, "Not Enough buffer"); + rc = -EINVAL; + goto end; + } + cmm_hdr = (struct common_header *)cmd_buf; + generic_op_code = cmm_hdr->fifth_byte; + + switch (cmm_hdr->cmd_type) { + case CAMERA_SENSOR_CMD_TYPE_I2C_INFO: + i2c_info = (struct cam_cmd_i2c_info *)cmd_buf; + if ((remain_len - processed_cmd_buf_in_bytes) < + sizeof(struct cam_cmd_i2c_info)) { + CAM_ERR(CAM_EEPROM, "Not enough buf"); + rc = -EINVAL; + goto end; + } + if (master == CCI_MASTER) { + cci->cci_i2c_master = + e_ctrl->cci_i2c_master; + cci->i2c_freq_mode = + i2c_info->i2c_freq_mode; + cci->sid = + i2c_info->slave_addr >> 1; + CAM_DBG(CAM_EEPROM, + "Slave addr: 0x%x Freq Mode: %d", + i2c_info->slave_addr, + i2c_info->i2c_freq_mode); + } else if (master == I2C_MASTER) { + e_ctrl->io_master_info.client->addr = + i2c_info->slave_addr; + CAM_DBG(CAM_EEPROM, + "Slave addr: 0x%x", + i2c_info->slave_addr); + } else if (master == SPI_MASTER) { + CAM_ERR(CAM_EEPROM, + "No Need of Slave Info"); + } else { + CAM_ERR(CAM_EEPROM, + "Invalid Master type: %d", + master); + rc = -EINVAL; + goto end; + } + cmd_length_in_bytes = + sizeof(struct cam_cmd_i2c_info); + processed_cmd_buf_in_bytes += + cmd_length_in_bytes; + cmd_buf += cmd_length_in_bytes/4; + break; + case CAMERA_SENSOR_CMD_TYPE_I2C_CONT_WR: { + struct cam_cmd_i2c_continuous_wr + *cam_cmd_i2c_continuous_wr = + (struct cam_cmd_i2c_continuous_wr *) + cmd_buf; + if ((remain_len - processed_cmd_buf_in_bytes) < + sizeof(struct cam_cmd_i2c_continuous_wr)) { + CAM_ERR(CAM_EEPROM, "Not enough buf"); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_EEPROM, + "CAMERA_SENSOR_CMD_TYPE_I2C_CONT_WR"); + rc = cam_eeprom_handle_continuous_write( + e_ctrl, + cam_cmd_i2c_continuous_wr, + &(e_ctrl->wr_settings), + &cmd_length_in_bytes, &off, &list); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed in continuous write %d", rc); + goto end; + } + + processed_cmd_buf_in_bytes += + cmd_length_in_bytes; + cmd_buf += cmd_length_in_bytes / + sizeof(uint32_t); + break; + } + case CAMERA_SENSOR_CMD_TYPE_WAIT: { + CAM_DBG(CAM_EEPROM, + "CAMERA_SENSOR_CMD_TYPE_WAIT"); + if (generic_op_code == + CAMERA_SENSOR_WAIT_OP_HW_UCND || + generic_op_code == + CAMERA_SENSOR_WAIT_OP_SW_UCND) { + + rc = cam_eeprom_handle_delay( + &cmd_buf, generic_op_code, + &(e_ctrl->wr_settings), off, + &cmd_length_in_bytes, + list, (remain_len - + processed_cmd_buf_in_bytes)); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, + "delay hdl failed: %d", + rc); + goto end; + } + processed_cmd_buf_in_bytes += + cmd_length_in_bytes; + cmd_buf += cmd_length_in_bytes / + sizeof(uint32_t); + } else { + CAM_ERR(CAM_EEPROM, + "Wrong Wait Command: %d", + generic_op_code); + rc = -EINVAL; + goto end; + } + break; + } + default: + CAM_ERR(CAM_EEPROM, + "Invalid Cmd_type rxed: %d\n", + cmm_hdr->cmd_type); + rc = -EINVAL; + break; + } + } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + } + return rc; + +end: + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + return rc; +} + +/** + * cam_eeprom_init_pkt_parser - Parse eeprom packet + * @e_ctrl: ctrl structure + * @csl_packet: csl packet received + * + * Returns success or failure + */ +static int32_t cam_eeprom_init_pkt_parser(struct cam_eeprom_ctrl_t *e_ctrl, + struct cam_packet *csl_packet) +{ + int32_t rc = 0; + int i = 0; + struct cam_cmd_buf_desc *cmd_desc = NULL; + uint32_t *offset = NULL; + uint32_t *cmd_buf = NULL; + uintptr_t generic_pkt_addr; + size_t pkt_len = 0; + size_t remain_len = 0; + uint32_t total_cmd_buf_in_bytes = 0; + uint32_t processed_cmd_buf_in_bytes = 0; + struct common_header *cmm_hdr = NULL; + uint32_t cmd_length_in_bytes = 0; + struct cam_cmd_i2c_info *i2c_info = NULL; + int num_map = -1; + struct cam_eeprom_memory_map_t *map = NULL; + struct cam_eeprom_soc_private *soc_private = + (struct cam_eeprom_soc_private *)e_ctrl->soc_info.soc_private; + struct cam_sensor_power_ctrl_t *power_info = &soc_private->power_info; + + e_ctrl->cal_data.map = vzalloc((MSM_EEPROM_MEMORY_MAP_MAX_SIZE * + MSM_EEPROM_MAX_MEM_MAP_CNT) * + (sizeof(struct cam_eeprom_memory_map_t))); + if (!e_ctrl->cal_data.map) { + rc = -ENOMEM; + CAM_ERR(CAM_EEPROM, "failed"); + return rc; + } + map = e_ctrl->cal_data.map; + + offset = (uint32_t *)&csl_packet->payload; + offset += (csl_packet->cmd_buf_offset / sizeof(uint32_t)); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + + /* Loop through multiple command buffers */ + for (i = 0; i < csl_packet->num_cmd_buf; i++) { + total_cmd_buf_in_bytes = cmd_desc[i].length; + processed_cmd_buf_in_bytes = 0; + if (!total_cmd_buf_in_bytes) + continue; + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, + &generic_pkt_addr, &pkt_len); + if (rc) { + CAM_ERR(CAM_EEPROM, "Failed to get cpu buf"); + return rc; + } + cmd_buf = (uint32_t *)generic_pkt_addr; + if (!cmd_buf) { + CAM_ERR(CAM_EEPROM, "invalid cmd buf"); + rc = -EINVAL; + goto end; + } + + if ((pkt_len < sizeof(struct common_header)) || + (cmd_desc[i].offset > (pkt_len - + sizeof(struct common_header)))) { + CAM_ERR(CAM_EEPROM, "Not enough buffer"); + rc = -EINVAL; + goto end; + } + remain_len = pkt_len - cmd_desc[i].offset; + cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); + + if (total_cmd_buf_in_bytes > remain_len) { + CAM_ERR(CAM_EEPROM, "Not enough buffer for command"); + rc = -EINVAL; + goto end; + } + /* Loop through multiple cmd formats in one cmd buffer */ + while (processed_cmd_buf_in_bytes < total_cmd_buf_in_bytes) { + if ((remain_len - processed_cmd_buf_in_bytes) < + sizeof(struct common_header)) { + CAM_ERR(CAM_EEPROM, "Not enough buf"); + rc = -EINVAL; + goto end; + } + cmm_hdr = (struct common_header *)cmd_buf; + switch (cmm_hdr->cmd_type) { + case CAMERA_SENSOR_CMD_TYPE_I2C_INFO: + i2c_info = (struct cam_cmd_i2c_info *)cmd_buf; + if ((remain_len - processed_cmd_buf_in_bytes) < + sizeof(struct cam_cmd_i2c_info)) { + CAM_ERR(CAM_EEPROM, "Not enough buf"); + rc = -EINVAL; + goto end; + } + + if ((num_map + 1) >= + (MSM_EEPROM_MAX_MEM_MAP_CNT * + MSM_EEPROM_MEMORY_MAP_MAX_SIZE)) { + CAM_ERR(CAM_EEPROM, "OOB error"); + rc = -EINVAL; + goto end; + } + /* Configure the following map slave address */ + + map[num_map + 1].saddr = i2c_info->slave_addr; + rc = cam_eeprom_update_slaveInfo(e_ctrl, + cmd_buf); + cmd_length_in_bytes = + sizeof(struct cam_cmd_i2c_info); + processed_cmd_buf_in_bytes += + cmd_length_in_bytes; + cmd_buf += cmd_length_in_bytes/ + sizeof(uint32_t); + break; + case CAMERA_SENSOR_CMD_TYPE_PWR_UP: + case CAMERA_SENSOR_CMD_TYPE_PWR_DOWN: + cmd_length_in_bytes = total_cmd_buf_in_bytes; + rc = cam_sensor_update_power_settings(cmd_buf, + cmd_length_in_bytes, power_info, + (remain_len - + processed_cmd_buf_in_bytes)); + processed_cmd_buf_in_bytes += + cmd_length_in_bytes; + cmd_buf += cmd_length_in_bytes/ + sizeof(uint32_t); + if (rc) { + CAM_ERR(CAM_EEPROM, "Failed"); + goto end; + } + break; + case CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_WR: + case CAMERA_SENSOR_CMD_TYPE_I2C_CONT_RD: + case CAMERA_SENSOR_CMD_TYPE_WAIT: + num_map++; + rc = cam_eeprom_parse_memory_map( + &e_ctrl->cal_data, cmd_buf, + total_cmd_buf_in_bytes, + &cmd_length_in_bytes, &num_map, + (remain_len - + processed_cmd_buf_in_bytes)); + processed_cmd_buf_in_bytes += + cmd_length_in_bytes; + cmd_buf += cmd_length_in_bytes/sizeof(uint32_t); + break; + default: + CAM_ERR(CAM_EEPROM, "Invalid cmd_type 0x%x", + cmm_hdr->cmd_type); + rc = -EINVAL; + goto end; + } + } + e_ctrl->cal_data.num_map = num_map + 1; + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + } + return rc; + +end: + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + return rc; +} + +/** + * cam_eeprom_get_cal_data - parse the userspace IO config and + * copy read data to share with userspace + * @e_ctrl: ctrl structure + * @csl_packet: csl packet received + * + * Returns success or failure + */ +static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, + struct cam_packet *csl_packet) +{ + struct cam_buf_io_cfg *io_cfg; + uint32_t i = 0; + int rc = 0; + uintptr_t buf_addr; + size_t buf_size; + uint8_t *read_buffer; + size_t remain_len = 0; + + io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) + &csl_packet->payload + + csl_packet->io_configs_offset); + + CAM_DBG(CAM_EEPROM, "number of IO configs: %d:", + csl_packet->num_io_configs); + + for (i = 0; i < csl_packet->num_io_configs; i++) { + CAM_DBG(CAM_EEPROM, "Direction: %d:", io_cfg->direction); + if (io_cfg->direction == CAM_BUF_OUTPUT) { + rc = cam_mem_get_cpu_buf(io_cfg->mem_handle[0], + &buf_addr, &buf_size); + if (rc) { + CAM_ERR(CAM_EEPROM, "Fail in get buffer: %d", + rc); + return rc; + } + if (buf_size <= io_cfg->offsets[0]) { + CAM_ERR(CAM_EEPROM, "Not enough buffer"); + rc = -EINVAL; + return rc; + } + + remain_len = buf_size - io_cfg->offsets[0]; + CAM_DBG(CAM_EEPROM, "buf_addr : %pK, buf_size : %zu\n", + (void *)buf_addr, buf_size); + + read_buffer = (uint8_t *)buf_addr; + if (!read_buffer) { + CAM_ERR(CAM_EEPROM, + "invalid buffer to copy data"); + rc = -EINVAL; + return rc; + } + read_buffer += io_cfg->offsets[0]; + + if (remain_len < e_ctrl->cal_data.num_data) { + CAM_ERR(CAM_EEPROM, + "failed to copy, Invalid size"); + rc = -EINVAL; + return rc; + } + + CAM_DBG(CAM_EEPROM, "copy the data, len:%d", + e_ctrl->cal_data.num_data); + memcpy(read_buffer, e_ctrl->cal_data.mapdata, + e_ctrl->cal_data.num_data); + cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); + } else { + CAM_ERR(CAM_EEPROM, "Invalid direction"); + rc = -EINVAL; + } + } + + return rc; +} + +static int32_t delete_eeprom_request(struct i2c_settings_array *i2c_array) +{ + struct i2c_settings_list *i2c_list = NULL, *i2c_next = NULL; + int32_t rc = 0; + + if (i2c_array == NULL) { + CAM_ERR(CAM_SENSOR, "FATAL:: Invalid argument"); + return -EINVAL; + } + + list_for_each_entry_safe(i2c_list, i2c_next, + &(i2c_array->list_head), list) { + kfree(i2c_list->seq_settings.reg_data); + list_del(&(i2c_list->list)); + kfree(i2c_list); + } + INIT_LIST_HEAD(&(i2c_array->list_head)); + i2c_array->is_settings_valid = 0; + + return rc; +} + +/** + * cam_eeprom_write - Write Packet + * @e_ctrl: ctrl structure + * + * Returns success or failure + */ +static int32_t cam_eeprom_write(struct cam_eeprom_ctrl_t *e_ctrl) +{ + int32_t rc = 0; + struct i2c_settings_array *i2c_set = NULL; + struct i2c_settings_list *i2c_list = NULL; + + i2c_set = &e_ctrl->wr_settings; + + if (i2c_set->is_settings_valid == 1) { + list_for_each_entry(i2c_list, + &(i2c_set->list_head), list) { + rc = camera_io_dev_write_continuous( + &e_ctrl->io_master_info, + &i2c_list->i2c_settings, 1); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, + "Error in EEPROM write"); + goto del_req; + } + } + } + +del_req: + delete_eeprom_request(i2c_set); + return rc; +} + +/** + * cam_eeprom_pkt_parse - Parse csl packet + * @e_ctrl: ctrl structure + * @arg: Camera control command argument + * + * Returns success or failure + */ +static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) +{ + int32_t rc = 0; + struct cam_control *ioctl_ctrl = NULL; + struct cam_config_dev_cmd dev_config; + uintptr_t generic_pkt_addr; + size_t pkt_len; + size_t remain_len = 0; + struct cam_packet *csl_packet = NULL; + struct cam_eeprom_soc_private *soc_private = + (struct cam_eeprom_soc_private *)e_ctrl->soc_info.soc_private; + struct cam_sensor_power_ctrl_t *power_info = &soc_private->power_info; + + ioctl_ctrl = (struct cam_control *)arg; + + if (copy_from_user(&dev_config, + u64_to_user_ptr(ioctl_ctrl->handle), + sizeof(dev_config))) + return -EFAULT; + rc = cam_mem_get_cpu_buf(dev_config.packet_handle, + &generic_pkt_addr, &pkt_len); + if (rc) { + CAM_ERR(CAM_EEPROM, + "error in converting command Handle Error: %d", rc); + return rc; + } + + remain_len = pkt_len; + if ((sizeof(struct cam_packet) > pkt_len) || + ((size_t)dev_config.offset >= pkt_len - + sizeof(struct cam_packet))) { + CAM_ERR(CAM_EEPROM, + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), pkt_len); + rc = -EINVAL; + return rc; + } + + remain_len -= (size_t)dev_config.offset; + csl_packet = (struct cam_packet *) + (generic_pkt_addr + (uint32_t)dev_config.offset); + + if (cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_EEPROM, "Invalid packet params"); + rc = -EINVAL; + return rc; + } + + switch (csl_packet->header.op_code & 0xFFFFFF) { + case CAM_EEPROM_PACKET_OPCODE_INIT: + if (e_ctrl->userspace_probe == false) { + rc = cam_eeprom_parse_read_memory_map( + e_ctrl->soc_info.dev->of_node, e_ctrl); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "Failed: rc : %d", rc); + return rc; + } + rc = cam_eeprom_get_cal_data(e_ctrl, csl_packet); + vfree(e_ctrl->cal_data.mapdata); + vfree(e_ctrl->cal_data.map); + e_ctrl->cal_data.num_data = 0; + e_ctrl->cal_data.num_map = 0; + CAM_DBG(CAM_EEPROM, + "Returning the data using kernel probe"); + break; + } + rc = cam_eeprom_init_pkt_parser(e_ctrl, csl_packet); + if (rc) { + CAM_ERR(CAM_EEPROM, + "Failed in parsing the pkt"); + return rc; + } + + e_ctrl->cal_data.mapdata = + vzalloc(e_ctrl->cal_data.num_data); + if (!e_ctrl->cal_data.mapdata) { + rc = -ENOMEM; + CAM_ERR(CAM_EEPROM, "failed"); + goto error; + } + + if (e_ctrl->eeprom_device_type == MSM_CAMERA_SPI_DEVICE) { + rc = cam_eeprom_match_id(e_ctrl); + if (rc) { + CAM_DBG(CAM_EEPROM, + "eeprom not matching %d", rc); + goto memdata_free; + } + } + + rc = cam_eeprom_power_up(e_ctrl, + &soc_private->power_info); + if (rc) { + CAM_ERR(CAM_EEPROM, "failed rc %d", rc); + goto memdata_free; + } + + e_ctrl->cam_eeprom_state = CAM_EEPROM_CONFIG; + rc = cam_eeprom_read_memory(e_ctrl, &e_ctrl->cal_data); + if (rc) { + CAM_ERR(CAM_EEPROM, + "read_eeprom_memory failed"); + goto power_down; + } + + rc = cam_eeprom_get_cal_data(e_ctrl, csl_packet); + rc = cam_eeprom_power_down(e_ctrl); + e_ctrl->cam_eeprom_state = CAM_EEPROM_ACQUIRE; + vfree(e_ctrl->cal_data.mapdata); + vfree(e_ctrl->cal_data.map); + kfree(power_info->power_setting); + kfree(power_info->power_down_setting); + power_info->power_setting = NULL; + power_info->power_down_setting = NULL; + power_info->power_setting_size = 0; + power_info->power_down_setting_size = 0; + e_ctrl->cal_data.num_data = 0; + e_ctrl->cal_data.num_map = 0; + break; + case CAM_EEPROM_WRITE: { + struct i2c_settings_array *i2c_reg_settings = + &e_ctrl->wr_settings; + + i2c_reg_settings->is_settings_valid = 1; + rc = cam_eeprom_parse_write_memory_packet( + csl_packet, e_ctrl); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "Failed: rc : %d", rc); + return rc; + } + + rc = cam_eeprom_power_up(e_ctrl, + &soc_private->power_info); + if (rc) { + CAM_ERR(CAM_EEPROM, "failed power up rc %d", rc); + goto memdata_free; + } + + usleep_range(10*1000, 11*1000); + CAM_DBG(CAM_EEPROM, + "Calling Erase : %d start Address: 0x%x size: %d", + rc, e_ctrl->eebin_info.start_address, + e_ctrl->eebin_info.size); + + rc = camera_io_dev_erase(&e_ctrl->io_master_info, + e_ctrl->eebin_info.start_address, + e_ctrl->eebin_info.size); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "Failed in erase : %d", rc); + return rc; + } + + /* Buffer time margin */ + usleep_range(10*1000, 11*1000); + + rc = cam_eeprom_write(e_ctrl); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "Failed: rc : %d", rc); + return rc; + } + + rc = cam_eeprom_power_down(e_ctrl); + if (rc) { + CAM_ERR(CAM_EEPROM, "failed power down rc %d", rc); + goto memdata_free; + } + + break; + } + default: + CAM_ERR(CAM_EEPROM, "Invalid op-code 0x%x", + csl_packet->header.op_code & 0xFFFFFF); + rc = -EINVAL; + break; + } + + cam_mem_put_cpu_buf(dev_config.packet_handle); + return rc; +power_down: + cam_eeprom_power_down(e_ctrl); +memdata_free: + vfree(e_ctrl->cal_data.mapdata); +error: + kfree(power_info->power_setting); + kfree(power_info->power_down_setting); + power_info->power_setting = NULL; + power_info->power_down_setting = NULL; + vfree(e_ctrl->cal_data.map); + e_ctrl->cal_data.num_data = 0; + e_ctrl->cal_data.num_map = 0; + e_ctrl->cam_eeprom_state = CAM_EEPROM_ACQUIRE; + return rc; +} + +void cam_eeprom_shutdown(struct cam_eeprom_ctrl_t *e_ctrl) +{ + int rc; + struct cam_eeprom_soc_private *soc_private = + (struct cam_eeprom_soc_private *)e_ctrl->soc_info.soc_private; + struct cam_sensor_power_ctrl_t *power_info = &soc_private->power_info; + + if (e_ctrl->cam_eeprom_state == CAM_EEPROM_INIT) + return; + + if (e_ctrl->cam_eeprom_state == CAM_EEPROM_CONFIG) { + rc = cam_eeprom_power_down(e_ctrl); + if (rc < 0) + CAM_ERR(CAM_EEPROM, "EEPROM Power down failed"); + e_ctrl->cam_eeprom_state = CAM_EEPROM_ACQUIRE; + } + + if (e_ctrl->cam_eeprom_state == CAM_EEPROM_ACQUIRE) { + rc = cam_destroy_device_hdl(e_ctrl->bridge_intf.device_hdl); + if (rc < 0) + CAM_ERR(CAM_EEPROM, "destroying the device hdl"); + + e_ctrl->bridge_intf.device_hdl = -1; + e_ctrl->bridge_intf.link_hdl = -1; + e_ctrl->bridge_intf.session_hdl = -1; + + kfree(power_info->power_setting); + kfree(power_info->power_down_setting); + power_info->power_setting = NULL; + power_info->power_down_setting = NULL; + power_info->power_setting_size = 0; + power_info->power_down_setting_size = 0; + } + + e_ctrl->cam_eeprom_state = CAM_EEPROM_INIT; +} + +/** + * cam_eeprom_driver_cmd - Handle eeprom cmds + * @e_ctrl: ctrl structure + * @arg: Camera control command argument + * + * Returns success or failure + */ +int32_t cam_eeprom_driver_cmd(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) +{ + int rc = 0; + struct cam_eeprom_query_cap_t eeprom_cap = {0}; + struct cam_control *cmd = (struct cam_control *)arg; + + if (!e_ctrl || !cmd) { + CAM_ERR(CAM_EEPROM, "Invalid Arguments"); + return -EINVAL; + } + + if (cmd->handle_type != CAM_HANDLE_USER_POINTER) { + CAM_ERR(CAM_EEPROM, "Invalid handle type: %d", + cmd->handle_type); + return -EINVAL; + } + + mutex_lock(&(e_ctrl->eeprom_mutex)); + switch (cmd->op_code) { + case CAM_QUERY_CAP: + eeprom_cap.slot_info = e_ctrl->soc_info.index; + if (e_ctrl->userspace_probe == false) + eeprom_cap.eeprom_kernel_probe = true; + else + eeprom_cap.eeprom_kernel_probe = false; + + eeprom_cap.is_multimodule_mode = + e_ctrl->is_multimodule_mode; + + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &eeprom_cap, + sizeof(struct cam_eeprom_query_cap_t))) { + CAM_ERR(CAM_EEPROM, "Failed Copy to User"); + rc = -EFAULT; + goto release_mutex; + } + CAM_DBG(CAM_EEPROM, "eeprom_cap: ID: %d", eeprom_cap.slot_info); + break; + case CAM_ACQUIRE_DEV: + rc = cam_eeprom_get_dev_handle(e_ctrl, arg); + if (rc) { + CAM_ERR(CAM_EEPROM, "Failed to acquire dev"); + goto release_mutex; + } + e_ctrl->cam_eeprom_state = CAM_EEPROM_ACQUIRE; + break; + case CAM_RELEASE_DEV: + if (e_ctrl->cam_eeprom_state != CAM_EEPROM_ACQUIRE) { + rc = -EINVAL; + CAM_WARN(CAM_EEPROM, + "Not in right state to release : %d", + e_ctrl->cam_eeprom_state); + goto release_mutex; + } + + if (e_ctrl->bridge_intf.device_hdl == -1) { + CAM_ERR(CAM_EEPROM, + "Invalid Handles: link hdl: %d device hdl: %d", + e_ctrl->bridge_intf.device_hdl, + e_ctrl->bridge_intf.link_hdl); + rc = -EINVAL; + goto release_mutex; + } + rc = cam_destroy_device_hdl(e_ctrl->bridge_intf.device_hdl); + if (rc < 0) + CAM_ERR(CAM_EEPROM, + "failed in destroying the device hdl"); + e_ctrl->bridge_intf.device_hdl = -1; + e_ctrl->bridge_intf.link_hdl = -1; + e_ctrl->bridge_intf.session_hdl = -1; + e_ctrl->cam_eeprom_state = CAM_EEPROM_INIT; + break; + case CAM_CONFIG_DEV: + rc = cam_eeprom_pkt_parse(e_ctrl, arg); + if (rc) { + CAM_ERR(CAM_EEPROM, "Failed in eeprom pkt Parsing"); + goto release_mutex; + } + break; + default: + CAM_DBG(CAM_EEPROM, "invalid opcode"); + break; + } + +release_mutex: + mutex_unlock(&(e_ctrl->eeprom_mutex)); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.h new file mode 100644 index 0000000000000000000000000000000000000000..6a1e867542cb129fd9a90695ea02a43a635f1df9 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ +#ifndef _CAM_EEPROM_CORE_H_ +#define _CAM_EEPROM_CORE_H_ + +#include "cam_eeprom_dev.h" + +int32_t cam_eeprom_driver_cmd(struct cam_eeprom_ctrl_t *e_ctrl, void *arg); +int32_t cam_eeprom_parse_read_memory_map(struct device_node *of_node, + struct cam_eeprom_ctrl_t *e_ctrl); +/** + * @e_ctrl: EEPROM ctrl structure + * + * This API handles the shutdown ioctl/close + */ +void cam_eeprom_shutdown(struct cam_eeprom_ctrl_t *e_ctrl); + +#endif +/* _CAM_EEPROM_CORE_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_dev.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..328541553b59ad5f09cd95d4714d274e51fe30f4 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_dev.c @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_eeprom_dev.h" +#include "cam_req_mgr_dev.h" +#include "cam_eeprom_soc.h" +#include "cam_eeprom_core.h" +#include "cam_debug_util.h" + +static long cam_eeprom_subdev_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + int rc = 0; + struct cam_eeprom_ctrl_t *e_ctrl = v4l2_get_subdevdata(sd); + + switch (cmd) { + case VIDIOC_CAM_CONTROL: + rc = cam_eeprom_driver_cmd(e_ctrl, arg); + break; + default: + rc = -ENOIOCTLCMD; + break; + } + + return rc; +} + +static int cam_eeprom_subdev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct cam_eeprom_ctrl_t *e_ctrl = + v4l2_get_subdevdata(sd); + + if (!e_ctrl) { + CAM_ERR(CAM_EEPROM, "e_ctrl ptr is NULL"); + return -EINVAL; + } + + mutex_lock(&(e_ctrl->eeprom_mutex)); + cam_eeprom_shutdown(e_ctrl); + mutex_unlock(&(e_ctrl->eeprom_mutex)); + + return 0; +} + +int32_t cam_eeprom_update_i2c_info(struct cam_eeprom_ctrl_t *e_ctrl, + struct cam_eeprom_i2c_info_t *i2c_info) +{ + struct cam_sensor_cci_client *cci_client = NULL; + + if (e_ctrl->io_master_info.master_type == CCI_MASTER) { + cci_client = e_ctrl->io_master_info.cci_client; + if (!cci_client) { + CAM_ERR(CAM_EEPROM, "failed: cci_client %pK", + cci_client); + return -EINVAL; + } + cci_client->cci_i2c_master = e_ctrl->cci_i2c_master; + cci_client->sid = (i2c_info->slave_addr) >> 1; + cci_client->retries = 3; + cci_client->id_map = 0; + cci_client->i2c_freq_mode = i2c_info->i2c_freq_mode; + } else if (e_ctrl->io_master_info.master_type == I2C_MASTER) { + e_ctrl->io_master_info.client->addr = i2c_info->slave_addr; + CAM_DBG(CAM_EEPROM, "Slave addr: 0x%x", i2c_info->slave_addr); + } else if (e_ctrl->io_master_info.master_type == SPI_MASTER) { + CAM_ERR(CAM_EEPROM, "Slave addr: 0x%x Freq Mode: %d", + i2c_info->slave_addr, i2c_info->i2c_freq_mode); + } + return 0; +} + +#ifdef CONFIG_COMPAT +static long cam_eeprom_init_subdev_do_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + struct cam_control cmd_data; + int32_t rc = 0; + + if (copy_from_user(&cmd_data, (void __user *)arg, + sizeof(cmd_data))) { + CAM_ERR(CAM_EEPROM, + "Failed to copy from user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + return -EFAULT; + } + + switch (cmd) { + case VIDIOC_CAM_CONTROL: + rc = cam_eeprom_subdev_ioctl(sd, cmd, &cmd_data); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, + "Failed in eeprom suddev handling rc %d", + rc); + return rc; + } + break; + default: + CAM_ERR(CAM_EEPROM, "Invalid compat ioctl: %d", cmd); + rc = -EINVAL; + } + + if (!rc) { + if (copy_to_user((void __user *)arg, &cmd_data, + sizeof(cmd_data))) { + CAM_ERR(CAM_EEPROM, + "Failed to copy from user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + rc = -EFAULT; + } + } + return rc; +} +#endif + +static const struct v4l2_subdev_internal_ops cam_eeprom_internal_ops = { + .close = cam_eeprom_subdev_close, +}; + +static struct v4l2_subdev_core_ops cam_eeprom_subdev_core_ops = { + .ioctl = cam_eeprom_subdev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = cam_eeprom_init_subdev_do_ioctl, +#endif +}; + +static struct v4l2_subdev_ops cam_eeprom_subdev_ops = { + .core = &cam_eeprom_subdev_core_ops, +}; + +static int cam_eeprom_init_subdev(struct cam_eeprom_ctrl_t *e_ctrl) +{ + int rc = 0; + + e_ctrl->v4l2_dev_str.internal_ops = &cam_eeprom_internal_ops; + e_ctrl->v4l2_dev_str.ops = &cam_eeprom_subdev_ops; + strlcpy(e_ctrl->device_name, CAM_EEPROM_NAME, + sizeof(e_ctrl->device_name)); + e_ctrl->v4l2_dev_str.name = e_ctrl->device_name; + e_ctrl->v4l2_dev_str.sd_flags = + (V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS); + e_ctrl->v4l2_dev_str.ent_function = CAM_EEPROM_DEVICE_TYPE; + e_ctrl->v4l2_dev_str.token = e_ctrl; + + rc = cam_register_subdev(&(e_ctrl->v4l2_dev_str)); + if (rc) + CAM_ERR(CAM_SENSOR, "Fail with cam_register_subdev"); + + return rc; +} + +static int cam_eeprom_i2c_driver_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int rc = 0; + struct cam_eeprom_ctrl_t *e_ctrl = NULL; + struct cam_eeprom_soc_private *soc_private = NULL; + struct cam_hw_soc_info *soc_info = NULL; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + CAM_ERR(CAM_EEPROM, "i2c_check_functionality failed"); + goto probe_failure; + } + + e_ctrl = kzalloc(sizeof(*e_ctrl), GFP_KERNEL); + if (!e_ctrl) { + CAM_ERR(CAM_EEPROM, "kzalloc failed"); + rc = -ENOMEM; + goto probe_failure; + } + + soc_private = kzalloc(sizeof(*soc_private), GFP_KERNEL); + if (!soc_private) + goto ectrl_free; + + e_ctrl->soc_info.soc_private = soc_private; + + i2c_set_clientdata(client, e_ctrl); + + mutex_init(&(e_ctrl->eeprom_mutex)); + + INIT_LIST_HEAD(&(e_ctrl->wr_settings.list_head)); + soc_info = &e_ctrl->soc_info; + soc_info->dev = &client->dev; + soc_info->dev_name = client->name; + e_ctrl->io_master_info.master_type = I2C_MASTER; + e_ctrl->io_master_info.client = client; + e_ctrl->eeprom_device_type = MSM_CAMERA_I2C_DEVICE; + e_ctrl->cal_data.mapdata = NULL; + e_ctrl->cal_data.map = NULL; + e_ctrl->userspace_probe = false; + + rc = cam_eeprom_parse_dt(e_ctrl); + if (rc) { + CAM_ERR(CAM_EEPROM, "failed: soc init rc %d", rc); + goto free_soc; + } + + rc = cam_eeprom_update_i2c_info(e_ctrl, &soc_private->i2c_info); + if (rc) { + CAM_ERR(CAM_EEPROM, "failed: to update i2c info rc %d", rc); + goto free_soc; + } + + rc = cam_eeprom_init_subdev(e_ctrl); + if (rc) + goto free_soc; + + if (soc_private->i2c_info.slave_addr != 0) + e_ctrl->io_master_info.client->addr = + soc_private->i2c_info.slave_addr; + + e_ctrl->bridge_intf.device_hdl = -1; + e_ctrl->bridge_intf.ops.get_dev_info = NULL; + e_ctrl->bridge_intf.ops.link_setup = NULL; + e_ctrl->bridge_intf.ops.apply_req = NULL; + e_ctrl->cam_eeprom_state = CAM_EEPROM_INIT; + + return rc; +free_soc: + kfree(soc_private); +ectrl_free: + kfree(e_ctrl); +probe_failure: + return rc; +} + +static int cam_eeprom_i2c_driver_remove(struct i2c_client *client) +{ + int i; + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct cam_eeprom_ctrl_t *e_ctrl; + struct cam_eeprom_soc_private *soc_private; + struct cam_hw_soc_info *soc_info; + + if (!sd) { + CAM_ERR(CAM_EEPROM, "Subdevice is NULL"); + return -EINVAL; + } + + e_ctrl = (struct cam_eeprom_ctrl_t *)v4l2_get_subdevdata(sd); + if (!e_ctrl) { + CAM_ERR(CAM_EEPROM, "eeprom device is NULL"); + return -EINVAL; + } + + soc_private = + (struct cam_eeprom_soc_private *)e_ctrl->soc_info.soc_private; + if (!soc_private) { + CAM_ERR(CAM_EEPROM, "soc_info.soc_private is NULL"); + return -EINVAL; + } + + CAM_INFO(CAM_EEPROM, "i2c driver remove invoked"); + soc_info = &e_ctrl->soc_info; + for (i = 0; i < soc_info->num_clk; i++) + devm_clk_put(soc_info->dev, soc_info->clk[i]); + + mutex_lock(&(e_ctrl->eeprom_mutex)); + cam_eeprom_shutdown(e_ctrl); + mutex_unlock(&(e_ctrl->eeprom_mutex)); + mutex_destroy(&(e_ctrl->eeprom_mutex)); + cam_unregister_subdev(&(e_ctrl->v4l2_dev_str)); + kfree(soc_private); + v4l2_set_subdevdata(&e_ctrl->v4l2_dev_str.sd, NULL); + kfree(e_ctrl); + + return 0; +} + +static int cam_eeprom_spi_setup(struct spi_device *spi) +{ + struct cam_eeprom_ctrl_t *e_ctrl = NULL; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_sensor_spi_client *spi_client; + struct cam_eeprom_soc_private *eb_info; + struct cam_sensor_power_ctrl_t *power_info = NULL; + int rc = 0; + + e_ctrl = kzalloc(sizeof(*e_ctrl), GFP_KERNEL); + if (!e_ctrl) + return -ENOMEM; + + soc_info = &e_ctrl->soc_info; + soc_info->dev = &spi->dev; + soc_info->dev_name = spi->modalias; + + e_ctrl->v4l2_dev_str.ops = &cam_eeprom_subdev_ops; + e_ctrl->userspace_probe = false; + e_ctrl->cal_data.mapdata = NULL; + e_ctrl->cal_data.map = NULL; + + spi_client = kzalloc(sizeof(*spi_client), GFP_KERNEL); + if (!spi_client) { + kfree(e_ctrl); + return -ENOMEM; + } + + eb_info = kzalloc(sizeof(*eb_info), GFP_KERNEL); + if (!eb_info) + goto spi_free; + e_ctrl->soc_info.soc_private = eb_info; + + e_ctrl->eeprom_device_type = MSM_CAMERA_SPI_DEVICE; + e_ctrl->io_master_info.spi_client = spi_client; + e_ctrl->io_master_info.master_type = SPI_MASTER; + spi_client->spi_master = spi; + INIT_LIST_HEAD(&(e_ctrl->wr_settings.list_head)); + power_info = &eb_info->power_info; + power_info->dev = &spi->dev; + + /* set spi instruction info */ + spi_client->retry_delay = 1; + spi_client->retries = 0; + + /* Initialize mutex */ + mutex_init(&(e_ctrl->eeprom_mutex)); + + e_ctrl->bridge_intf.device_hdl = -1; + rc = cam_eeprom_parse_dt(e_ctrl); + if (rc) { + CAM_ERR(CAM_EEPROM, "failed: spi soc init rc %d", rc); + goto board_free; + } + + rc = cam_eeprom_spi_parse_of(spi_client); + if (rc) { + CAM_ERR(CAM_EEPROM, "Device tree parsing error"); + goto board_free; + } + + rc = cam_eeprom_init_subdev(e_ctrl); + if (rc) + goto board_free; + + e_ctrl->bridge_intf.ops.get_dev_info = NULL; + e_ctrl->bridge_intf.ops.link_setup = NULL; + e_ctrl->bridge_intf.ops.apply_req = NULL; + + v4l2_set_subdevdata(&e_ctrl->v4l2_dev_str.sd, e_ctrl); + return rc; + +board_free: + kfree(e_ctrl->soc_info.soc_private); +spi_free: + kfree(spi_client); + kfree(e_ctrl); + return rc; +} + +static int cam_eeprom_spi_driver_probe(struct spi_device *spi) +{ + spi->bits_per_word = 8; + spi->mode = SPI_MODE_0; + spi_setup(spi); + + CAM_DBG(CAM_EEPROM, "irq[%d] cs[%x] CPHA[%x] CPOL[%x] CS_HIGH[%x]", + spi->irq, spi->chip_select, (spi->mode & SPI_CPHA) ? 1 : 0, + (spi->mode & SPI_CPOL) ? 1 : 0, + (spi->mode & SPI_CS_HIGH) ? 1 : 0); + CAM_DBG(CAM_EEPROM, "max_speed[%u]", spi->max_speed_hz); + + return cam_eeprom_spi_setup(spi); +} + +static int cam_eeprom_spi_driver_remove(struct spi_device *sdev) +{ + int i; + struct v4l2_subdev *sd = spi_get_drvdata(sdev); + struct cam_eeprom_ctrl_t *e_ctrl; + struct cam_eeprom_soc_private *soc_private; + struct cam_hw_soc_info *soc_info; + + if (!sd) { + CAM_ERR(CAM_EEPROM, "Subdevice is NULL"); + return -EINVAL; + } + + e_ctrl = (struct cam_eeprom_ctrl_t *)v4l2_get_subdevdata(sd); + if (!e_ctrl) { + CAM_ERR(CAM_EEPROM, "eeprom device is NULL"); + return -EINVAL; + } + + soc_info = &e_ctrl->soc_info; + for (i = 0; i < soc_info->num_clk; i++) + devm_clk_put(soc_info->dev, soc_info->clk[i]); + + mutex_lock(&(e_ctrl->eeprom_mutex)); + cam_eeprom_shutdown(e_ctrl); + mutex_unlock(&(e_ctrl->eeprom_mutex)); + mutex_destroy(&(e_ctrl->eeprom_mutex)); + cam_unregister_subdev(&(e_ctrl->v4l2_dev_str)); + kfree(e_ctrl->io_master_info.spi_client); + e_ctrl->io_master_info.spi_client = NULL; + soc_private = + (struct cam_eeprom_soc_private *)e_ctrl->soc_info.soc_private; + if (soc_private) { + kfree(soc_private->power_info.gpio_num_info); + soc_private->power_info.gpio_num_info = NULL; + kfree(soc_private); + soc_private = NULL; + } + v4l2_set_subdevdata(&e_ctrl->v4l2_dev_str.sd, NULL); + kfree(e_ctrl); + + return 0; +} + +static int32_t cam_eeprom_platform_driver_probe( + struct platform_device *pdev) +{ + int32_t rc = 0; + struct cam_eeprom_ctrl_t *e_ctrl = NULL; + struct cam_eeprom_soc_private *soc_private = NULL; + + e_ctrl = kzalloc(sizeof(struct cam_eeprom_ctrl_t), GFP_KERNEL); + if (!e_ctrl) + return -ENOMEM; + + e_ctrl->soc_info.pdev = pdev; + e_ctrl->soc_info.dev = &pdev->dev; + e_ctrl->soc_info.dev_name = pdev->name; + e_ctrl->eeprom_device_type = MSM_CAMERA_PLATFORM_DEVICE; + e_ctrl->cal_data.mapdata = NULL; + e_ctrl->cal_data.map = NULL; + e_ctrl->userspace_probe = false; + + e_ctrl->io_master_info.master_type = CCI_MASTER; + e_ctrl->io_master_info.cci_client = kzalloc( + sizeof(struct cam_sensor_cci_client), GFP_KERNEL); + if (!e_ctrl->io_master_info.cci_client) { + rc = -ENOMEM; + goto free_e_ctrl; + } + + soc_private = kzalloc(sizeof(struct cam_eeprom_soc_private), + GFP_KERNEL); + if (!soc_private) { + rc = -ENOMEM; + goto free_cci_client; + } + e_ctrl->soc_info.soc_private = soc_private; + soc_private->power_info.dev = &pdev->dev; + + /* Initialize mutex */ + mutex_init(&(e_ctrl->eeprom_mutex)); + rc = cam_eeprom_parse_dt(e_ctrl); + if (rc) { + CAM_ERR(CAM_EEPROM, "failed: soc init rc %d", rc); + goto free_soc; + } + rc = cam_eeprom_update_i2c_info(e_ctrl, &soc_private->i2c_info); + if (rc) { + CAM_ERR(CAM_EEPROM, "failed: to update i2c info rc %d", rc); + goto free_soc; + } + + INIT_LIST_HEAD(&(e_ctrl->wr_settings.list_head)); + rc = cam_eeprom_init_subdev(e_ctrl); + if (rc) + goto free_soc; + + e_ctrl->bridge_intf.device_hdl = -1; + e_ctrl->bridge_intf.ops.get_dev_info = NULL; + e_ctrl->bridge_intf.ops.link_setup = NULL; + e_ctrl->bridge_intf.ops.apply_req = NULL; + platform_set_drvdata(pdev, e_ctrl); + e_ctrl->cam_eeprom_state = CAM_EEPROM_INIT; + + return rc; +free_soc: + kfree(soc_private); +free_cci_client: + kfree(e_ctrl->io_master_info.cci_client); +free_e_ctrl: + kfree(e_ctrl); + + return rc; +} + +static int cam_eeprom_platform_driver_remove(struct platform_device *pdev) +{ + int i; + struct cam_eeprom_ctrl_t *e_ctrl; + struct cam_hw_soc_info *soc_info; + + e_ctrl = platform_get_drvdata(pdev); + if (!e_ctrl) { + CAM_ERR(CAM_EEPROM, "eeprom device is NULL"); + return -EINVAL; + } + + CAM_INFO(CAM_EEPROM, "Platform driver remove invoked"); + soc_info = &e_ctrl->soc_info; + + for (i = 0; i < soc_info->num_clk; i++) + devm_clk_put(soc_info->dev, soc_info->clk[i]); + + mutex_lock(&(e_ctrl->eeprom_mutex)); + cam_eeprom_shutdown(e_ctrl); + mutex_unlock(&(e_ctrl->eeprom_mutex)); + mutex_destroy(&(e_ctrl->eeprom_mutex)); + cam_unregister_subdev(&(e_ctrl->v4l2_dev_str)); + kfree(soc_info->soc_private); + kfree(e_ctrl->io_master_info.cci_client); + platform_set_drvdata(pdev, NULL); + v4l2_set_subdevdata(&e_ctrl->v4l2_dev_str.sd, NULL); + kfree(e_ctrl); + + return 0; +} + +static const struct of_device_id cam_eeprom_dt_match[] = { + { .compatible = "qcom,eeprom" }, + { } +}; + + +MODULE_DEVICE_TABLE(of, cam_eeprom_dt_match); + +static struct platform_driver cam_eeprom_platform_driver = { + .driver = { + .name = "qcom,eeprom", + .owner = THIS_MODULE, + .of_match_table = cam_eeprom_dt_match, + .suppress_bind_attrs = true, + }, + .probe = cam_eeprom_platform_driver_probe, + .remove = cam_eeprom_platform_driver_remove, +}; + +static const struct i2c_device_id cam_eeprom_i2c_id[] = { + { "msm_eeprom", (kernel_ulong_t)NULL}, + { } +}; + +static struct i2c_driver cam_eeprom_i2c_driver = { + .id_table = cam_eeprom_i2c_id, + .probe = cam_eeprom_i2c_driver_probe, + .remove = cam_eeprom_i2c_driver_remove, + .driver = { + .name = "msm_eeprom", + }, +}; + +static struct spi_driver cam_eeprom_spi_driver = { + .driver = { + .name = "qcom_eeprom", + .owner = THIS_MODULE, + .of_match_table = cam_eeprom_dt_match, + }, + .probe = cam_eeprom_spi_driver_probe, + .remove = cam_eeprom_spi_driver_remove, +}; +static int __init cam_eeprom_driver_init(void) +{ + int rc = 0; + + rc = platform_driver_register(&cam_eeprom_platform_driver); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "platform_driver_register failed rc = %d", + rc); + return rc; + } + + rc = spi_register_driver(&cam_eeprom_spi_driver); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "spi_register_driver failed rc = %d", rc); + return rc; + } + + rc = i2c_add_driver(&cam_eeprom_i2c_driver); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "i2c_add_driver failed rc = %d", rc); + return rc; + } + + return rc; +} + +static void __exit cam_eeprom_driver_exit(void) +{ + platform_driver_unregister(&cam_eeprom_platform_driver); + spi_unregister_driver(&cam_eeprom_spi_driver); + i2c_del_driver(&cam_eeprom_i2c_driver); +} + +module_init(cam_eeprom_driver_init); +module_exit(cam_eeprom_driver_exit); +MODULE_DESCRIPTION("CAM EEPROM driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_dev.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..66f8aaddc9589afb98f6b5eaab7c268349654736 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_dev.h @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ +#ifndef _CAM_EEPROM_DEV_H_ +#define _CAM_EEPROM_DEV_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_soc_util.h" +#include "cam_context.h" + +#define DEFINE_MSM_MUTEX(mutexname) \ + static struct mutex mutexname = __MUTEX_INITIALIZER(mutexname) + +#define PROPERTY_MAXSIZE 32 + +#define MSM_EEPROM_MEMORY_MAP_MAX_SIZE 80 +#define MSM_EEPROM_MAX_MEM_MAP_CNT 100 +#define MSM_EEPROM_MEM_MAP_PROPERTIES_CNT 8 + +enum cam_eeprom_state { + CAM_EEPROM_INIT, + CAM_EEPROM_ACQUIRE, + CAM_EEPROM_CONFIG, +}; + +/** + * struct cam_eeprom_map_t - eeprom map + * @data_type : Data type + * @addr_type : Address type + * @addr : Address + * @data : data + * @delay : Delay + * + */ +struct cam_eeprom_map_t { + uint32_t valid_size; + uint32_t addr; + uint32_t addr_type; + uint32_t data; + uint32_t data_type; + uint32_t delay; +}; + +/** + * struct cam_eeprom_memory_map_t - eeprom memory map types + * @page : page memory + * @pageen : pageen memory + * @poll : poll memory + * @mem : mem + * @saddr : slave addr + * + */ +struct cam_eeprom_memory_map_t { + struct cam_eeprom_map_t page; + struct cam_eeprom_map_t pageen; + struct cam_eeprom_map_t poll; + struct cam_eeprom_map_t mem; + uint32_t saddr; +}; + +/** + * struct cam_eeprom_memory_block_t - eeprom mem block info + * @map : eeprom memory map + * @num_map : number of map blocks + * @mapdata : map data + * @cmd_type : size of total mapdata + * + */ +struct cam_eeprom_memory_block_t { + struct cam_eeprom_memory_map_t *map; + uint32_t num_map; + uint8_t *mapdata; + uint32_t num_data; +}; + +/** + * struct cam_eeprom_cmm_t - camera multimodule + * @cmm_support : cmm support flag + * @cmm_compression : cmm compression flag + * @cmm_offset : cmm data start offset + * @cmm_size : cmm data size + * + */ +struct cam_eeprom_cmm_t { + uint32_t cmm_support; + uint32_t cmm_compression; + uint32_t cmm_offset; + uint32_t cmm_size; +}; + +/** + * struct cam_eeprom_i2c_info_t - I2C info + * @slave_addr : slave address + * @i2c_freq_mode : i2c frequency mode + * + */ +struct cam_eeprom_i2c_info_t { + uint16_t slave_addr; + uint8_t i2c_freq_mode; +}; + +/** + * struct cam_eeprom_soc_private - eeprom soc private data structure + * @eeprom_name : eeprom name + * @i2c_info : i2c info structure + * @power_info : eeprom power info + * @cmm_data : cmm data + * + */ +struct cam_eeprom_soc_private { + const char *eeprom_name; + struct cam_eeprom_i2c_info_t i2c_info; + struct cam_sensor_power_ctrl_t power_info; + struct cam_eeprom_cmm_t cmm_data; +}; + +/** + * struct cam_eeprom_intf_params - bridge interface params + * @device_hdl : Device Handle + * @session_hdl : Session Handle + * @ops : KMD operations + * @crm_cb : Callback API pointers + */ +struct cam_eeprom_intf_params { + int32_t device_hdl; + int32_t session_hdl; + int32_t link_hdl; + struct cam_req_mgr_kmd_ops ops; + struct cam_req_mgr_crm_cb *crm_cb; +}; + +struct eebin_info { + uint32_t start_address; + uint32_t size; + uint32_t is_valid; +}; + +/** + * struct cam_eeprom_ctrl_t - EEPROM control structure + * @device_name : Device name + * @pdev : platform device + * @spi : spi device + * @eeprom_mutex : eeprom mutex + * @soc_info : eeprom soc related info + * @io_master_info : Information about the communication master + * @gpio_num_info : gpio info + * @cci_i2c_master : I2C structure + * @v4l2_dev_str : V4L2 device structure + * @bridge_intf : bridge interface params + * @cam_eeprom_state : eeprom_device_state + * @userspace_probe : flag indicates userspace or kernel probe + * @cal_data : Calibration data + * @device_name : Device name + * @is_multimodule_mode : To identify multimodule node + * @wr_settings : I2C write settings + * @eebin_info : EEBIN address, size info + */ +struct cam_eeprom_ctrl_t { + char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH]; + struct platform_device *pdev; + struct spi_device *spi; + struct mutex eeprom_mutex; + struct cam_hw_soc_info soc_info; + struct camera_io_master io_master_info; + struct msm_camera_gpio_num_info *gpio_num_info; + enum cci_i2c_master_t cci_i2c_master; + enum cci_device_num cci_num; + struct cam_subdev v4l2_dev_str; + struct cam_eeprom_intf_params bridge_intf; + enum msm_camera_device_type_t eeprom_device_type; + enum cam_eeprom_state cam_eeprom_state; + bool userspace_probe; + struct cam_eeprom_memory_block_t cal_data; + uint16_t is_multimodule_mode; + struct i2c_settings_array wr_settings; + struct eebin_info eebin_info; +}; + +int32_t cam_eeprom_update_i2c_info(struct cam_eeprom_ctrl_t *e_ctrl, + struct cam_eeprom_i2c_info_t *i2c_info); + +#endif /*_CAM_EEPROM_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_soc.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..33f80b0c9716fa3190377862268524cf5e7a0dc9 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_soc.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "cam_eeprom_soc.h" +#include "cam_debug_util.h" + +#define cam_eeprom_spi_parse_cmd(spi_dev, name, out) \ + { \ + spi_dev->cmd_tbl.name.opcode = out[0]; \ + spi_dev->cmd_tbl.name.addr_len = out[1]; \ + spi_dev->cmd_tbl.name.dummy_len = out[2]; \ + spi_dev->cmd_tbl.name.delay_intv = out[3]; \ + spi_dev->cmd_tbl.name.delay_count = out[4]; \ + } + +int cam_eeprom_spi_parse_of(struct cam_sensor_spi_client *spi_dev) +{ + int rc = -EFAULT; + uint32_t tmp[5]; + + rc = of_property_read_u32_array(spi_dev->spi_master->dev.of_node, + "spiop-read", tmp, 5); + if (!rc) { + cam_eeprom_spi_parse_cmd(spi_dev, read, tmp); + } else { + CAM_ERR(CAM_EEPROM, "Failed to get read data"); + return -EFAULT; + } + + rc = of_property_read_u32_array(spi_dev->spi_master->dev.of_node, + "spiop-readseq", tmp, 5); + if (!rc) { + cam_eeprom_spi_parse_cmd(spi_dev, read_seq, tmp); + } else { + CAM_ERR(CAM_EEPROM, "Failed to get readseq data"); + return -EFAULT; + } + + rc = of_property_read_u32_array(spi_dev->spi_master->dev.of_node, + "spiop-queryid", tmp, 5); + if (!rc) { + cam_eeprom_spi_parse_cmd(spi_dev, query_id, tmp); + } else { + CAM_ERR(CAM_EEPROM, "Failed to get queryid data"); + return -EFAULT; + } + + rc = of_property_read_u32_array(spi_dev->spi_master->dev.of_node, + "spiop-pprog", tmp, 5); + if (!rc) { + cam_eeprom_spi_parse_cmd(spi_dev, page_program, tmp); + } else { + CAM_ERR(CAM_EEPROM, "Failed to get page program data"); + return -EFAULT; + } + + rc = of_property_read_u32_array(spi_dev->spi_master->dev.of_node, + "spiop-wenable", tmp, 5); + if (!rc) { + cam_eeprom_spi_parse_cmd(spi_dev, write_enable, tmp); + } else { + CAM_ERR(CAM_EEPROM, "Failed to get write enable data"); + return rc; + } + + rc = of_property_read_u32_array(spi_dev->spi_master->dev.of_node, + "spiop-readst", tmp, 5); + if (!rc) { + cam_eeprom_spi_parse_cmd(spi_dev, read_status, tmp); + } else { + CAM_ERR(CAM_EEPROM, "Failed to get readdst data"); + return rc; + } + + rc = of_property_read_u32_array(spi_dev->spi_master->dev.of_node, + "spiop-erase", tmp, 5); + if (!rc) { + cam_eeprom_spi_parse_cmd(spi_dev, erase, tmp); + } else { + CAM_ERR(CAM_EEPROM, "Failed to get erase data"); + return rc; + } + + rc = of_property_read_u32_array(spi_dev->spi_master->dev.of_node, + "eeprom-id", tmp, 2); + if (rc) { + CAM_ERR(CAM_EEPROM, "Failed to get eeprom id"); + return rc; + } + + spi_dev->mfr_id0 = tmp[0]; + spi_dev->device_id0 = tmp[1]; + + return 0; +} + +/* + * cam_eeprom_parse_memory_map() - parse memory map in device node + * @of: device node + * @data: memory block for output + * + * This functions parses @of to fill @data. It allocates map itself, parses + * the @of node, calculate total data length, and allocates required buffer. + * It only fills the map, but does not perform actual reading. + */ +int cam_eeprom_parse_dt_memory_map(struct device_node *node, + struct cam_eeprom_memory_block_t *data) +{ + int i, rc = 0; + char property[PROPERTY_MAXSIZE]; + uint32_t count = MSM_EEPROM_MEM_MAP_PROPERTIES_CNT; + struct cam_eeprom_memory_map_t *map; + + snprintf(property, PROPERTY_MAXSIZE, "num-blocks"); + rc = of_property_read_u32(node, property, &data->num_map); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "failed: num-blocks not available rc %d", + rc); + return rc; + } + + map = vzalloc((sizeof(*map) * data->num_map)); + if (!map) { + rc = -ENOMEM; + return rc; + } + data->map = map; + + for (i = 0; i < data->num_map; i++) { + snprintf(property, PROPERTY_MAXSIZE, "page%d", i); + rc = of_property_read_u32_array(node, property, + (uint32_t *) &map[i].page, count); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "failed: page not available rc %d", + rc); + goto ERROR; + } + + snprintf(property, PROPERTY_MAXSIZE, "pageen%d", i); + rc = of_property_read_u32_array(node, property, + (uint32_t *) &map[i].pageen, count); + if (rc < 0) + CAM_DBG(CAM_EEPROM, "pageen not needed"); + + snprintf(property, PROPERTY_MAXSIZE, "saddr%d", i); + rc = of_property_read_u32_array(node, property, + (uint32_t *) &map[i].saddr, 1); + if (rc < 0) + CAM_DBG(CAM_EEPROM, "saddr not needed - block %d", i); + + snprintf(property, PROPERTY_MAXSIZE, "poll%d", i); + rc = of_property_read_u32_array(node, property, + (uint32_t *) &map[i].poll, count); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "failed: poll not available rc %d", + rc); + goto ERROR; + } + + snprintf(property, PROPERTY_MAXSIZE, "mem%d", i); + rc = of_property_read_u32_array(node, property, + (uint32_t *) &map[i].mem, count); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "failed: mem not available rc %d", + rc); + goto ERROR; + } + data->num_data += map[i].mem.valid_size; + } + + data->mapdata = vzalloc(data->num_data); + if (!data->mapdata) { + rc = -ENOMEM; + goto ERROR; + } + return rc; + +ERROR: + vfree(data->map); + memset(data, 0, sizeof(*data)); + return rc; +} + +/** + * @e_ctrl: ctrl structure + * + * Parses eeprom dt + */ +static int cam_eeprom_get_dt_data(struct cam_eeprom_ctrl_t *e_ctrl) +{ + int rc = 0; + struct cam_hw_soc_info *soc_info = &e_ctrl->soc_info; + struct cam_eeprom_soc_private *soc_private = + (struct cam_eeprom_soc_private *)e_ctrl->soc_info.soc_private; + struct cam_sensor_power_ctrl_t *power_info = &soc_private->power_info; + struct device_node *of_node = NULL; + + of_node = soc_info->dev->of_node; + + if (e_ctrl->userspace_probe == false) { + rc = cam_get_dt_power_setting_data(of_node, + soc_info, power_info); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "failed in getting power settings"); + return rc; + } + } + + if (!soc_info->gpio_data) { + CAM_INFO(CAM_EEPROM, "No GPIO found"); + return 0; + } + + if (!soc_info->gpio_data->cam_gpio_common_tbl_size) { + CAM_INFO(CAM_EEPROM, "No GPIO found"); + return -EINVAL; + } + + rc = cam_sensor_util_init_gpio_pin_tbl(soc_info, + &power_info->gpio_num_info); + if ((rc < 0) || (!power_info->gpio_num_info)) { + CAM_ERR(CAM_EEPROM, "No/Error EEPROM GPIOs"); + return -EINVAL; + } + + return rc; +} + +/** + * @eb_info: eeprom private data structure + * @of_node: eeprom device node + * + * This function parses the eeprom dt to get the MM data + */ +static int cam_eeprom_cmm_dts(struct cam_eeprom_soc_private *eb_info, + struct device_node *of_node) +{ + int rc = 0; + struct cam_eeprom_cmm_t *cmm_data = &eb_info->cmm_data; + + cmm_data->cmm_support = + of_property_read_bool(of_node, "cmm-data-support"); + if (!cmm_data->cmm_support) { + CAM_DBG(CAM_EEPROM, "No cmm support"); + return 0; + } + + cmm_data->cmm_compression = + of_property_read_bool(of_node, "cmm-data-compressed"); + + rc = of_property_read_u32(of_node, "cmm-data-offset", + &cmm_data->cmm_offset); + if (rc < 0) + CAM_DBG(CAM_EEPROM, "No MM offset data rc %d", rc); + + rc = of_property_read_u32(of_node, "cmm-data-size", + &cmm_data->cmm_size); + if (rc < 0) + CAM_DBG(CAM_EEPROM, "No MM size data rc %d", rc); + + CAM_DBG(CAM_EEPROM, "cmm_compr %d, cmm_offset %d, cmm_size %d", + cmm_data->cmm_compression, cmm_data->cmm_offset, + cmm_data->cmm_size); + return 0; +} + +/** + * @e_ctrl: ctrl structure + * + * This function is called from cam_eeprom_platform/i2c/spi_driver_probe + * it parses the eeprom dt node and decides for userspace or kernel probe. + */ +int cam_eeprom_parse_dt(struct cam_eeprom_ctrl_t *e_ctrl) +{ + int i, rc = 0; + struct cam_hw_soc_info *soc_info = &e_ctrl->soc_info; + struct device_node *of_node = NULL; + struct device_node *of_parent = NULL; + struct cam_eeprom_soc_private *soc_private = + (struct cam_eeprom_soc_private *)e_ctrl->soc_info.soc_private; + uint32_t temp; + + if (!soc_info->dev) { + CAM_ERR(CAM_EEPROM, "Dev is NULL"); + return -EINVAL; + } + + e_ctrl->is_multimodule_mode = false; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "Failed to read DT properties rc : %d", rc); + return rc; + } + + of_node = soc_info->dev->of_node; + + if (of_property_read_bool(of_node, "multimodule-support")) { + CAM_DBG(CAM_UTIL, "Multi Module is Supported"); + e_ctrl->is_multimodule_mode = true; + } + + rc = of_property_read_string(of_node, "eeprom-name", + &soc_private->eeprom_name); + if (rc < 0) { + CAM_DBG(CAM_EEPROM, "kernel probe is not enabled"); + e_ctrl->userspace_probe = true; + } + + if (e_ctrl->io_master_info.master_type == CCI_MASTER) { + rc = of_property_read_u32(of_node, "cci-master", + &e_ctrl->cci_i2c_master); + if (rc < 0 || (e_ctrl->cci_i2c_master >= MASTER_MAX)) { + CAM_DBG(CAM_EEPROM, "failed rc %d", rc); + rc = -EFAULT; + return rc; + } + + of_parent = of_get_parent(of_node); + if (of_property_read_u32(of_parent, "cell-index", + &e_ctrl->cci_num) < 0) + /* Set default master 0 */ + e_ctrl->cci_num = CCI_DEVICE_0; + + e_ctrl->io_master_info.cci_client->cci_device = e_ctrl->cci_num; + CAM_DBG(CAM_EEPROM, "cci-index %d", e_ctrl->cci_num, rc); + } + + if (e_ctrl->io_master_info.master_type == SPI_MASTER) { + rc = cam_eeprom_cmm_dts(soc_private, soc_info->dev->of_node); + if (rc < 0) + CAM_DBG(CAM_EEPROM, "MM data not available rc %d", rc); + } + + rc = cam_eeprom_get_dt_data(e_ctrl); + if (rc < 0) + CAM_DBG(CAM_EEPROM, "failed: eeprom get dt data rc %d", rc); + + if ((e_ctrl->userspace_probe == false) && + (e_ctrl->io_master_info.master_type != SPI_MASTER)) { + rc = of_property_read_u32(of_node, "slave-addr", &temp); + if (rc < 0) + CAM_DBG(CAM_EEPROM, "failed: no slave-addr rc %d", rc); + + soc_private->i2c_info.slave_addr = temp; + + rc = of_property_read_u32(of_node, "i2c-freq-mode", &temp); + soc_private->i2c_info.i2c_freq_mode = temp; + if (rc < 0) { + CAM_ERR(CAM_EEPROM, + "i2c-freq-mode read fail %d", rc); + soc_private->i2c_info.i2c_freq_mode = 0; + } + if (soc_private->i2c_info.i2c_freq_mode >= I2C_MAX_MODES) { + CAM_ERR(CAM_EEPROM, "invalid i2c_freq_mode = %d", + soc_private->i2c_info.i2c_freq_mode); + soc_private->i2c_info.i2c_freq_mode = 0; + } + CAM_DBG(CAM_EEPROM, "slave-addr = 0x%X", + soc_private->i2c_info.slave_addr); + } + + for (i = 0; i < soc_info->num_clk; i++) { + soc_info->clk[i] = devm_clk_get(soc_info->dev, + soc_info->clk_name[i]); + if (!soc_info->clk[i]) { + CAM_ERR(CAM_EEPROM, "get failed for %s", + soc_info->clk_name[i]); + rc = -ENOENT; + return rc; + } + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_soc.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..ed37989eb2d7047ae1e09a6ad332c7b596c045b0 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_soc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ +#ifndef _CAM_EEPROM_SOC_H_ +#define _CAM_EEPROM_SOC_H_ + +#include "cam_eeprom_dev.h" + +int cam_eeprom_spi_parse_of(struct cam_sensor_spi_client *client); + +int cam_eeprom_parse_dt_memory_map(struct device_node *of, + struct cam_eeprom_memory_block_t *data); + +int cam_eeprom_parse_dt(struct cam_eeprom_ctrl_t *e_ctrl); +#endif/* _CAM_EEPROM_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..f3c68f296ed577920b5180903c0a7fb01504ac76 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_flash_dev.o cam_flash_core.o cam_flash_soc.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_core.c new file mode 100644 index 0000000000000000000000000000000000000000..9007e5642fdd60063e3c8d712da5267621cc7bc6 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_core.c @@ -0,0 +1,1981 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +#include "cam_sensor_cmn_header.h" +#include "cam_flash_core.h" +#include "cam_res_mgr_api.h" +#include "cam_common_util.h" +#include "cam_packet_util.h" + +static int cam_flash_prepare(struct cam_flash_ctrl *flash_ctrl, + bool regulator_enable) +{ + int rc = 0; + struct cam_flash_private_soc *soc_private = + (struct cam_flash_private_soc *) + flash_ctrl->soc_info.soc_private; + + if (!(flash_ctrl->switch_trigger)) { + CAM_ERR(CAM_FLASH, "Invalid argument"); + return -EINVAL; + } + + if (soc_private->is_wled_flash) { + if (regulator_enable && + flash_ctrl->is_regulator_enabled == false) { + rc = wled_flash_led_prepare(flash_ctrl->switch_trigger, + ENABLE_REGULATOR, NULL); + if (rc) { + CAM_ERR(CAM_FLASH, "enable reg failed: rc: %d", + rc); + return rc; + } + + flash_ctrl->is_regulator_enabled = true; + } else if (!regulator_enable && + flash_ctrl->is_regulator_enabled == true) { + rc = wled_flash_led_prepare(flash_ctrl->switch_trigger, + DISABLE_REGULATOR, NULL); + if (rc) { + CAM_ERR(CAM_FLASH, "disalbe reg fail: rc: %d", + rc); + return rc; + } + + flash_ctrl->is_regulator_enabled = false; + } else { + CAM_ERR(CAM_FLASH, "Wrong Wled flash state: %d", + flash_ctrl->flash_state); + rc = -EINVAL; + } + } else { + if (regulator_enable && + (flash_ctrl->is_regulator_enabled == false)) { + rc = qpnp_flash_led_prepare(flash_ctrl->switch_trigger, + ENABLE_REGULATOR, NULL); + if (rc) { + CAM_ERR(CAM_FLASH, + "Regulator enable failed rc = %d", rc); + return rc; + } + + flash_ctrl->is_regulator_enabled = true; + } else if ((!regulator_enable) && + (flash_ctrl->is_regulator_enabled == true)) { + rc = qpnp_flash_led_prepare(flash_ctrl->switch_trigger, + DISABLE_REGULATOR, NULL); + if (rc) { + CAM_ERR(CAM_FLASH, + "Regulator disable failed rc = %d", rc); + return rc; + } + + flash_ctrl->is_regulator_enabled = false; + } else { + CAM_ERR(CAM_FLASH, "Wrong Flash State : %d", + flash_ctrl->flash_state); + rc = -EINVAL; + } + } + return rc; +} + +static int cam_flash_pmic_flush_nrt(struct cam_flash_ctrl *fctrl) +{ + int j = 0; + struct cam_flash_frame_setting *nrt_settings; + + if (!fctrl) + return -EINVAL; + + nrt_settings = &fctrl->nrt_info; + + if (nrt_settings->cmn_attr.cmd_type == + CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_INFO) { + fctrl->flash_init_setting.cmn_attr.is_settings_valid = false; + } else if ((nrt_settings->cmn_attr.cmd_type == + CAMERA_SENSOR_FLASH_CMD_TYPE_WIDGET) || + (nrt_settings->cmn_attr.cmd_type == + CAMERA_SENSOR_FLASH_CMD_TYPE_RER) || + (nrt_settings->cmn_attr.cmd_type == + CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_FIRE)) { + fctrl->nrt_info.cmn_attr.is_settings_valid = false; + fctrl->nrt_info.cmn_attr.count = 0; + fctrl->nrt_info.num_iterations = 0; + fctrl->nrt_info.led_on_delay_ms = 0; + fctrl->nrt_info.led_off_delay_ms = 0; + for (j = 0; j < CAM_FLASH_MAX_LED_TRIGGERS; j++) + fctrl->nrt_info.led_current_ma[j] = 0; + } + + return 0; +} + +static int cam_flash_i2c_flush_nrt(struct cam_flash_ctrl *fctrl) +{ + int rc = 0; + + if (fctrl->i2c_data.init_settings.is_settings_valid == true) { + rc = delete_request(&fctrl->i2c_data.init_settings); + if (rc) { + CAM_WARN(CAM_FLASH, + "Failed to delete Init i2c_setting: %d", + rc); + return rc; + } + } + if (fctrl->i2c_data.config_settings.is_settings_valid == true) { + rc = delete_request(&fctrl->i2c_data.config_settings); + if (rc) { + CAM_WARN(CAM_FLASH, + "Failed to delete NRT i2c_setting: %d", + rc); + return rc; + } + } + + return rc; +} + +static int cam_flash_construct_default_power_setting( + struct cam_sensor_power_ctrl_t *power_info) +{ + int rc = 0; + + power_info->power_setting_size = 1; + power_info->power_setting = + kzalloc(sizeof(struct cam_sensor_power_setting), + GFP_KERNEL); + if (!power_info->power_setting) + return -ENOMEM; + + power_info->power_setting[0].seq_type = SENSOR_CUSTOM_REG1; + power_info->power_setting[0].seq_val = CAM_V_CUSTOM1; + power_info->power_setting[0].config_val = 0; + power_info->power_setting[0].delay = 2; + + power_info->power_down_setting_size = 1; + power_info->power_down_setting = + kzalloc(sizeof(struct cam_sensor_power_setting), + GFP_KERNEL); + if (!power_info->power_down_setting) { + rc = -ENOMEM; + goto free_power_settings; + } + + power_info->power_down_setting[0].seq_type = SENSOR_CUSTOM_REG1; + power_info->power_down_setting[0].seq_val = CAM_V_CUSTOM1; + power_info->power_down_setting[0].config_val = 0; + + return rc; + +free_power_settings: + kfree(power_info->power_setting); + power_info->power_setting = NULL; + power_info->power_setting_size = 0; + return rc; +} + +int cam_flash_pmic_power_ops(struct cam_flash_ctrl *fctrl, + bool regulator_enable) +{ + int rc = 0; + + if (!(fctrl->switch_trigger)) { + CAM_ERR(CAM_FLASH, "Invalid argument"); + return -EINVAL; + } + + if (regulator_enable) { + rc = cam_flash_prepare(fctrl, true); + if (rc) { + CAM_ERR(CAM_FLASH, + "Enable Regulator Failed rc = %d", rc); + return rc; + } + fctrl->last_flush_req = 0; + } + + if (!regulator_enable) { + if (((fctrl->flash_state == CAM_FLASH_STATE_START) || + (fctrl->flash_state == CAM_FLASH_STATE_ACQUIRE)) && + (fctrl->is_regulator_enabled == true)) { + /* + * Release dev is called after stop dev and in + * stop dev flash state is set to acquire dev. + */ + rc = cam_flash_prepare(fctrl, false); + if (rc) + CAM_ERR(CAM_FLASH, + "Disable Regulator Failed rc: %d", rc); + } + } + + return rc; +} + +int cam_flash_i2c_power_ops(struct cam_flash_ctrl *fctrl, + bool regulator_enable) +{ + int rc = 0; + struct cam_hw_soc_info *soc_info = &fctrl->soc_info; + struct cam_sensor_power_ctrl_t *power_info = + &fctrl->power_info; + + if (!power_info || !soc_info) { + CAM_ERR(CAM_FLASH, "Power Info is NULL"); + return -EINVAL; + } + power_info->dev = soc_info->dev; + + if (regulator_enable && (fctrl->is_regulator_enabled == false)) { + if ((power_info->power_setting == NULL) && + (power_info->power_down_setting == NULL)) { + CAM_INFO(CAM_FLASH, + "Using default power settings"); + rc = cam_flash_construct_default_power_setting( + power_info); + if (rc < 0) { + CAM_ERR(CAM_FLASH, + "Construct default pwr setting failed rc: %d", + rc); + return rc; + } + } + + rc = cam_sensor_core_power_up(power_info, soc_info); + if (rc) { + CAM_ERR(CAM_FLASH, "power up the core is failed:%d", + rc); + goto free_pwr_settings; + } + + rc = camera_io_init(&(fctrl->io_master_info)); + if (rc) { + CAM_ERR(CAM_FLASH, "cci_init failed: rc: %d", rc); + cam_sensor_util_power_down(power_info, soc_info); + goto free_pwr_settings; + } + fctrl->is_regulator_enabled = true; + } else if ((!regulator_enable) && + (fctrl->is_regulator_enabled == true)) { + rc = cam_sensor_util_power_down(power_info, soc_info); + if (rc) { + CAM_ERR(CAM_FLASH, "power down the core is failed:%d", + rc); + return rc; + } + camera_io_release(&(fctrl->io_master_info)); + fctrl->is_regulator_enabled = false; + goto free_pwr_settings; + } + return rc; + +free_pwr_settings: + kfree(power_info->power_setting); + kfree(power_info->power_down_setting); + power_info->power_setting = NULL; + power_info->power_down_setting = NULL; + power_info->power_setting_size = 0; + power_info->power_down_setting_size = 0; + + return rc; +} + +int cam_flash_pmic_flush_request(struct cam_flash_ctrl *fctrl, + enum cam_flash_flush_type type, uint64_t req_id) +{ + int rc = 0; + int i = 0, j = 0; + int frame_offset = 0; + bool is_off_needed = false; + struct cam_flash_frame_setting *flash_data = NULL; + + if (!fctrl) { + CAM_ERR(CAM_FLASH, "Device data is NULL"); + return -EINVAL; + } + + if (type == FLUSH_ALL) { + /* flush all requests*/ + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { + flash_data = + &fctrl->per_frame[i]; + if ((flash_data->opcode == + CAMERA_SENSOR_FLASH_OP_OFF) && + (flash_data->cmn_attr.request_id > 0) && + (flash_data->cmn_attr.request_id <= req_id) && + flash_data->cmn_attr.is_settings_valid) { + is_off_needed = true; + CAM_DBG(CAM_FLASH, + "FLASH_ALL: Turn off the flash for req %llu", + flash_data->cmn_attr.request_id); + } + + flash_data->cmn_attr.request_id = 0; + flash_data->cmn_attr.is_settings_valid = false; + flash_data->cmn_attr.count = 0; + for (j = 0; j < CAM_FLASH_MAX_LED_TRIGGERS; j++) + flash_data->led_current_ma[j] = 0; + } + + cam_flash_pmic_flush_nrt(fctrl); + } else if ((type == FLUSH_REQ) && (req_id != 0)) { + /* flush request with req_id*/ + frame_offset = req_id % MAX_PER_FRAME_ARRAY; + flash_data = + &fctrl->per_frame[frame_offset]; + + if (flash_data->opcode == + CAMERA_SENSOR_FLASH_OP_OFF) { + is_off_needed = true; + CAM_DBG(CAM_FLASH, + "FLASH_REQ: Turn off the flash for req %llu", + flash_data->cmn_attr.request_id); + } + + flash_data->cmn_attr.request_id = 0; + flash_data->cmn_attr.is_settings_valid = + false; + flash_data->cmn_attr.count = 0; + for (i = 0; i < CAM_FLASH_MAX_LED_TRIGGERS; i++) + flash_data->led_current_ma[i] = 0; + } else if ((type == FLUSH_REQ) && (req_id == 0)) { + /* Handels NonRealTime usecase */ + cam_flash_pmic_flush_nrt(fctrl); + } else { + CAM_ERR(CAM_FLASH, "Invalid arguments"); + return -EINVAL; + } + + if (is_off_needed) + cam_flash_off(fctrl); + + return rc; +} + +int cam_flash_i2c_flush_request(struct cam_flash_ctrl *fctrl, + enum cam_flash_flush_type type, uint64_t req_id) +{ + int rc = 0; + int i = 0; + uint32_t cancel_req_id_found = 0; + struct i2c_settings_array *i2c_set = NULL; + + if (!fctrl) { + CAM_ERR(CAM_FLASH, "Device data is NULL"); + return -EINVAL; + } + if ((type == FLUSH_REQ) && (req_id == 0)) { + /* This setting will be called only when NonRealTime + * settings needs to clean. + */ + cam_flash_i2c_flush_nrt(fctrl); + } else { + /* All other usecase will be handle here */ + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { + i2c_set = &(fctrl->i2c_data.per_frame[i]); + + if ((type == FLUSH_REQ) && + (i2c_set->request_id != req_id)) + continue; + + if (i2c_set->is_settings_valid == 1) { + rc = delete_request(i2c_set); + if (rc < 0) + CAM_ERR(CAM_FLASH, + "delete request: %lld rc: %d", + i2c_set->request_id, rc); + + if (type == FLUSH_REQ) { + cancel_req_id_found = 1; + break; + } + } + } + } + + if ((type == FLUSH_REQ) && (req_id != 0) && + (!cancel_req_id_found)) + CAM_DBG(CAM_FLASH, + "Flush request id:%lld not found in the pending list", + req_id); + + return rc; +} + +int cam_flash_flush_request(struct cam_req_mgr_flush_request *flush) +{ + int rc = 0; + struct cam_flash_ctrl *fctrl = NULL; + + fctrl = (struct cam_flash_ctrl *) cam_get_device_priv(flush->dev_hdl); + if (!fctrl) { + CAM_ERR(CAM_FLASH, "Device data is NULL"); + return -EINVAL; + } + + mutex_lock(&fctrl->flash_mutex); + if (fctrl->flash_state == CAM_FLASH_STATE_INIT) + goto end; + + if (flush->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) { + fctrl->last_flush_req = flush->req_id; + CAM_DBG(CAM_FLASH, "last reqest to flush is %lld", + flush->req_id); + rc = fctrl->func_tbl.flush_req(fctrl, FLUSH_ALL, 0); + if (rc) { + CAM_ERR(CAM_FLASH, "FLUSH_TYPE_ALL failed rc: %d", rc); + goto end; + } + } else if (flush->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ) { + rc = fctrl->func_tbl.flush_req(fctrl, + FLUSH_REQ, flush->req_id); + if (rc) { + CAM_ERR(CAM_FLASH, "FLUSH_REQ failed rc: %d", rc); + goto end; + } + } +end: + mutex_unlock(&fctrl->flash_mutex); + return rc; +} + +static int cam_flash_ops(struct cam_flash_ctrl *flash_ctrl, + struct cam_flash_frame_setting *flash_data, enum camera_flash_opcode op) +{ + uint32_t curr = 0, max_current = 0; + struct cam_flash_private_soc *soc_private = NULL; + int i = 0; + + if (!flash_ctrl || !flash_data) { + CAM_ERR(CAM_FLASH, "Fctrl or Data NULL"); + return -EINVAL; + } + + soc_private = (struct cam_flash_private_soc *) + flash_ctrl->soc_info.soc_private; + + if (op == CAMERA_SENSOR_FLASH_OP_FIRELOW) { + for (i = 0; i < flash_ctrl->torch_num_sources; i++) { + if (flash_ctrl->torch_trigger[i]) { + max_current = soc_private->torch_max_current[i]; + if (flash_data->led_current_ma[i] <= + max_current) + curr = flash_data->led_current_ma[i]; + else + curr = max_current; + } + CAM_DBG(CAM_FLASH, "Led_Torch[%d]: Current: %d", + i, curr); + cam_res_mgr_led_trigger_event( + flash_ctrl->torch_trigger[i], curr); + } + } else if (op == CAMERA_SENSOR_FLASH_OP_FIREHIGH) { + for (i = 0; i < flash_ctrl->flash_num_sources; i++) { + if (flash_ctrl->flash_trigger[i]) { + max_current = soc_private->flash_max_current[i]; + if (flash_data->led_current_ma[i] <= + max_current) + curr = flash_data->led_current_ma[i]; + else + curr = max_current; + } + CAM_DBG(CAM_FLASH, "LED_Flash[%d]: Current: %d", + i, curr); + cam_res_mgr_led_trigger_event( + flash_ctrl->flash_trigger[i], curr); + } + } else { + CAM_ERR(CAM_FLASH, "Wrong Operation: %d", op); + return -EINVAL; + } + + if (flash_ctrl->switch_trigger) + cam_res_mgr_led_trigger_event( + flash_ctrl->switch_trigger, + (enum led_brightness)LED_SWITCH_ON); + + return 0; +} + +int cam_flash_off(struct cam_flash_ctrl *flash_ctrl) +{ + int rc = 0; + + if (!flash_ctrl) { + CAM_ERR(CAM_FLASH, "Flash control Null"); + return -EINVAL; + } + + if (flash_ctrl->switch_trigger) + cam_res_mgr_led_trigger_event(flash_ctrl->switch_trigger, + (enum led_brightness)LED_SWITCH_OFF); + + flash_ctrl->flash_state = CAM_FLASH_STATE_START; + + if ((flash_ctrl->i2c_data.streamoff_settings.is_settings_valid) && + (flash_ctrl->i2c_data.streamoff_settings.request_id == 0)) { + flash_ctrl->apply_streamoff = true; + rc = cam_flash_i2c_apply_setting(flash_ctrl, 0); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "cannot apply streamoff settings"); + } + flash_ctrl->flash_state = CAM_FLASH_STATE_CONFIG; + } + + return 0; +} + +static int cam_flash_low( + struct cam_flash_ctrl *flash_ctrl, + struct cam_flash_frame_setting *flash_data) +{ + int i = 0, rc = 0; + + if (!flash_data) { + CAM_ERR(CAM_FLASH, "Flash Data Null"); + return -EINVAL; + } + + for (i = 0; i < flash_ctrl->flash_num_sources; i++) + if (flash_ctrl->flash_trigger[i]) + cam_res_mgr_led_trigger_event( + flash_ctrl->flash_trigger[i], + LED_OFF); + + rc = cam_flash_ops(flash_ctrl, flash_data, + CAMERA_SENSOR_FLASH_OP_FIRELOW); + if (rc) + CAM_ERR(CAM_FLASH, "Fire Torch failed: %d", rc); + + return rc; +} + +static int cam_flash_high( + struct cam_flash_ctrl *flash_ctrl, + struct cam_flash_frame_setting *flash_data) +{ + int i = 0, rc = 0; + + if (!flash_data) { + CAM_ERR(CAM_FLASH, "Flash Data Null"); + return -EINVAL; + } + + for (i = 0; i < flash_ctrl->torch_num_sources; i++) + if (flash_ctrl->torch_trigger[i]) + cam_res_mgr_led_trigger_event( + flash_ctrl->torch_trigger[i], + LED_OFF); + + rc = cam_flash_ops(flash_ctrl, flash_data, + CAMERA_SENSOR_FLASH_OP_FIREHIGH); + if (rc) + CAM_ERR(CAM_FLASH, "Fire Flash Failed: %d", rc); + + return rc; +} + +static int cam_flash_i2c_delete_req(struct cam_flash_ctrl *fctrl, + uint64_t req_id) +{ + int i = 0, rc = 0; + uint64_t top = 0, del_req_id = 0; + + if (req_id != 0) { + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { + if ((req_id >= + fctrl->i2c_data.per_frame[i].request_id) && + (top < + fctrl->i2c_data.per_frame[i].request_id) && + (fctrl->i2c_data.per_frame[i].is_settings_valid + == 1)) { + del_req_id = top; + top = fctrl->i2c_data.per_frame[i].request_id; + } + } + + if (top < req_id) { + if ((((top % MAX_PER_FRAME_ARRAY) - (req_id % + MAX_PER_FRAME_ARRAY)) >= BATCH_SIZE_MAX) || + (((top % MAX_PER_FRAME_ARRAY) - (req_id % + MAX_PER_FRAME_ARRAY)) <= -BATCH_SIZE_MAX)) + del_req_id = req_id; + } + + if (!del_req_id) + return rc; + + CAM_DBG(CAM_FLASH, "top: %llu, del_req_id:%llu", + top, del_req_id); + + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { + if ((del_req_id > + fctrl->i2c_data.per_frame[i].request_id) && ( + fctrl->i2c_data.per_frame[i].is_settings_valid + == 1)) { + fctrl->i2c_data.per_frame[i].request_id = 0; + rc = delete_request( + &(fctrl->i2c_data.per_frame[i])); + if (rc < 0) + CAM_ERR(CAM_SENSOR, + "Delete request Fail:%lld rc:%d", + del_req_id, rc); + } + } + } + + cam_flash_i2c_flush_nrt(fctrl); + + return 0; +} + +static int cam_flash_pmic_delete_req(struct cam_flash_ctrl *fctrl, + uint64_t req_id) +{ + int i = 0; + struct cam_flash_frame_setting *flash_data = NULL; + uint64_t top = 0, del_req_id = 0; + int frame_offset = 0; + + if (req_id != 0) { + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { + flash_data = &fctrl->per_frame[i]; + if (req_id >= flash_data->cmn_attr.request_id && + flash_data->cmn_attr.is_settings_valid + == 1) { + if (top < flash_data->cmn_attr.request_id) { + del_req_id = top; + top = flash_data->cmn_attr.request_id; + } else if (top > + flash_data->cmn_attr.request_id && + del_req_id < + flash_data->cmn_attr.request_id) { + del_req_id = + flash_data->cmn_attr.request_id; + } + } + } + + if (top < req_id) { + if ((((top % MAX_PER_FRAME_ARRAY) - (req_id % + MAX_PER_FRAME_ARRAY)) >= BATCH_SIZE_MAX) || + (((top % MAX_PER_FRAME_ARRAY) - (req_id % + MAX_PER_FRAME_ARRAY)) <= -BATCH_SIZE_MAX)) + del_req_id = req_id; + } + + if (!del_req_id) + return 0; + + CAM_DBG(CAM_FLASH, "top: %llu, del_req_id:%llu", + top, del_req_id); + } + + /* delete the request */ + frame_offset = del_req_id % MAX_PER_FRAME_ARRAY; + flash_data = &fctrl->per_frame[frame_offset]; + flash_data->cmn_attr.request_id = 0; + flash_data->cmn_attr.is_settings_valid = false; + flash_data->cmn_attr.count = 0; + + for (i = 0; i < CAM_FLASH_MAX_LED_TRIGGERS; i++) + flash_data->led_current_ma[i] = 0; + + return 0; +} + +static int32_t cam_flash_slaveInfo_pkt_parser(struct cam_flash_ctrl *fctrl, + uint32_t *cmd_buf, size_t len) +{ + int32_t rc = 0; + struct cam_cmd_i2c_info *i2c_info = (struct cam_cmd_i2c_info *)cmd_buf; + + if (len < sizeof(struct cam_cmd_i2c_info)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + return -EINVAL; + } + if (fctrl->io_master_info.master_type == CCI_MASTER) { + fctrl->io_master_info.cci_client->cci_i2c_master = + fctrl->cci_i2c_master; + fctrl->io_master_info.cci_client->i2c_freq_mode = + i2c_info->i2c_freq_mode; + fctrl->io_master_info.cci_client->sid = + i2c_info->slave_addr >> 1; + CAM_DBG(CAM_FLASH, "Slave addr: 0x%x Freq Mode: %d", + i2c_info->slave_addr, i2c_info->i2c_freq_mode); + } else if (fctrl->io_master_info.master_type == I2C_MASTER) { + fctrl->io_master_info.client->addr = i2c_info->slave_addr; + CAM_DBG(CAM_FLASH, "Slave addr: 0x%x", i2c_info->slave_addr); + } else { + CAM_ERR(CAM_FLASH, "Invalid Master type: %d", + fctrl->io_master_info.master_type); + rc = -EINVAL; + } + + return rc; +} + +int cam_flash_i2c_apply_setting(struct cam_flash_ctrl *fctrl, + uint64_t req_id) +{ + struct i2c_settings_list *i2c_list; + struct i2c_settings_array *i2c_set = NULL; + int frame_offset = 0, rc = 0; + CAM_DBG(CAM_FLASH, "req_id=%llu", req_id); + if (req_id == 0) { + /* NonRealTime Init settings*/ + if (fctrl->apply_streamoff == true) { + fctrl->apply_streamoff = false; + i2c_set = &fctrl->i2c_data.streamoff_settings; + list_for_each_entry(i2c_list, + &(i2c_set->list_head), + list) { + rc = cam_sensor_util_i2c_apply_setting + (&(fctrl->io_master_info), i2c_list); + if (rc) { + CAM_ERR(CAM_FLASH, + "Failed to apply stream on settings: %d", + rc); + return rc; + } + break; + } + } else if (fctrl->i2c_data.init_settings.is_settings_valid == + true) { + list_for_each_entry(i2c_list, + &(fctrl->i2c_data.init_settings.list_head), + list) { + rc = cam_sensor_util_i2c_apply_setting + (&(fctrl->io_master_info), i2c_list); + if ((rc == -EAGAIN) && + (fctrl->io_master_info.master_type == + CCI_MASTER)) { + CAM_WARN(CAM_FLASH, + "CCI HW is in reset mode: Reapplying Init settings"); + usleep_range(1000, 1010); + rc = cam_sensor_util_i2c_apply_setting + (&(fctrl->io_master_info), i2c_list); + } + + if (rc) { + CAM_ERR(CAM_FLASH, + "Failed to apply init settings: %d", + rc); + return rc; + } + } + } + /* NonRealTime (Widget/RER/INIT_FIRE settings) */ + if (fctrl->i2c_data.config_settings.is_settings_valid == true) { + list_for_each_entry(i2c_list, + &(fctrl->i2c_data.config_settings.list_head), + list) { + rc = cam_sensor_util_i2c_apply_setting + (&(fctrl->io_master_info), i2c_list); + if (rc) { + CAM_ERR(CAM_FLASH, + "Failed to apply NRT settings: %d", rc); + return rc; + } + } + } + } else { + /* RealTime */ + frame_offset = req_id % MAX_PER_FRAME_ARRAY; + i2c_set = &fctrl->i2c_data.per_frame[frame_offset]; + if ((i2c_set->is_settings_valid == true) && + (i2c_set->request_id == req_id)) { + list_for_each_entry(i2c_list, + &(i2c_set->list_head), list) { + rc = cam_sensor_util_i2c_apply_setting( + &(fctrl->io_master_info), i2c_list); + if (rc) { + CAM_ERR(CAM_FLASH, + "Failed to apply settings: %d", rc); + return rc; + } + } + } + } + + cam_flash_i2c_delete_req(fctrl, req_id); + return rc; +} + +int cam_flash_pmic_apply_setting(struct cam_flash_ctrl *fctrl, + uint64_t req_id) +{ + int rc = 0, i = 0; + int frame_offset = 0; + uint16_t num_iterations; + struct cam_flash_frame_setting *flash_data = NULL; + + if (req_id == 0) { + if (fctrl->nrt_info.cmn_attr.cmd_type == + CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_FIRE) { + flash_data = &fctrl->nrt_info; + CAM_DBG(CAM_REQ, + "FLASH_INIT_FIRE req_id: %u flash_opcode: %d", + req_id, flash_data->opcode); + + if (flash_data->opcode == + CAMERA_SENSOR_FLASH_OP_FIREHIGH) { + if (fctrl->flash_state == + CAM_FLASH_STATE_START) { + CAM_WARN(CAM_FLASH, + "Wrong state :Prev state: %d", + fctrl->flash_state); + return -EINVAL; + } + + rc = cam_flash_high(fctrl, flash_data); + if (rc) + CAM_ERR(CAM_FLASH, + "FLASH ON failed : %d", rc); + } + if (flash_data->opcode == + CAMERA_SENSOR_FLASH_OP_FIRELOW) { + if (fctrl->flash_state == + CAM_FLASH_STATE_START) { + CAM_WARN(CAM_FLASH, + "Wrong state :Prev state: %d", + fctrl->flash_state); + return -EINVAL; + } + + rc = cam_flash_low(fctrl, flash_data); + if (rc) + CAM_ERR(CAM_FLASH, + "TORCH ON failed : %d", rc); + } + if (flash_data->opcode == + CAMERA_SENSOR_FLASH_OP_OFF) { + rc = cam_flash_off(fctrl); + if (rc) { + CAM_ERR(CAM_FLASH, + "LED OFF FAILED: %d", + rc); + return rc; + } + } + } else if (fctrl->nrt_info.cmn_attr.cmd_type == + CAMERA_SENSOR_FLASH_CMD_TYPE_WIDGET) { + flash_data = &fctrl->nrt_info; + CAM_DBG(CAM_REQ, + "FLASH_WIDGET req_id: %u flash_opcode: %d", + req_id, flash_data->opcode); + + if (flash_data->opcode == + CAMERA_SENSOR_FLASH_OP_FIRELOW) { + rc = cam_flash_low(fctrl, flash_data); + if (rc) { + CAM_ERR(CAM_FLASH, + "Torch ON failed : %d", + rc); + goto nrt_del_req; + } + } else if (flash_data->opcode == + CAMERA_SENSOR_FLASH_OP_OFF) { + rc = cam_flash_off(fctrl); + if (rc) + CAM_ERR(CAM_FLASH, + "LED off failed: %d", + rc); + } + } else if (fctrl->nrt_info.cmn_attr.cmd_type == + CAMERA_SENSOR_FLASH_CMD_TYPE_RER) { + flash_data = &fctrl->nrt_info; + if (fctrl->flash_state != CAM_FLASH_STATE_START) { + rc = cam_flash_off(fctrl); + if (rc) { + CAM_ERR(CAM_FLASH, + "Flash off failed: %d", + rc); + goto nrt_del_req; + } + } + CAM_DBG(CAM_REQ, "FLASH_RER req_id: %u", req_id); + + num_iterations = flash_data->num_iterations; + for (i = 0; i < num_iterations; i++) { + /* Turn On Torch */ + if (fctrl->flash_state == + CAM_FLASH_STATE_START) { + rc = cam_flash_low(fctrl, flash_data); + if (rc) { + CAM_ERR(CAM_FLASH, + "Fire Torch Failed"); + goto nrt_del_req; + } + + usleep_range( + flash_data->led_on_delay_ms * 1000, + flash_data->led_on_delay_ms * 1000 + + 100); + } + /* Turn Off Torch */ + rc = cam_flash_off(fctrl); + if (rc) { + CAM_ERR(CAM_FLASH, + "Flash off failed: %d", rc); + continue; + } + fctrl->flash_state = CAM_FLASH_STATE_START; + usleep_range( + flash_data->led_off_delay_ms * 1000, + flash_data->led_off_delay_ms * 1000 + 100); + } + } + } else { + frame_offset = req_id % MAX_PER_FRAME_ARRAY; + flash_data = &fctrl->per_frame[frame_offset]; + CAM_DBG(CAM_REQ, "FLASH_RT req_id: %u flash_opcode: %d", + req_id, flash_data->opcode); + + if ((flash_data->opcode == CAMERA_SENSOR_FLASH_OP_FIREHIGH) && + (flash_data->cmn_attr.is_settings_valid) && + (flash_data->cmn_attr.request_id == req_id)) { + /* Turn On Flash */ + if (fctrl->flash_state == CAM_FLASH_STATE_START) { + rc = cam_flash_high(fctrl, flash_data); + if (rc) { + CAM_ERR(CAM_FLASH, + "Flash ON failed: rc= %d", + rc); + goto apply_setting_err; + } + } + } else if ((flash_data->opcode == + CAMERA_SENSOR_FLASH_OP_FIRELOW) && + (flash_data->cmn_attr.is_settings_valid) && + (flash_data->cmn_attr.request_id == req_id)) { + /* Turn On Torch */ + if (fctrl->flash_state == CAM_FLASH_STATE_START) { + rc = cam_flash_low(fctrl, flash_data); + if (rc) { + CAM_ERR(CAM_FLASH, + "Torch ON failed: rc= %d", + rc); + goto apply_setting_err; + } + } + } else if ((flash_data->opcode == CAMERA_SENSOR_FLASH_OP_OFF) && + (flash_data->cmn_attr.is_settings_valid) && + (flash_data->cmn_attr.request_id == req_id)) { + rc = cam_flash_off(fctrl); + if (rc) { + CAM_ERR(CAM_FLASH, + "Flash off failed %d", rc); + goto apply_setting_err; + } + } else if (flash_data->opcode == CAM_PKT_NOP_OPCODE) { + CAM_DBG(CAM_FLASH, "NOP Packet"); + } else { + rc = -EINVAL; + CAM_ERR(CAM_FLASH, "Invalid opcode: %d req_id: %llu", + flash_data->opcode, req_id); + goto apply_setting_err; + } + } + +nrt_del_req: + cam_flash_pmic_delete_req(fctrl, req_id); +apply_setting_err: + return rc; +} + +int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) +{ + int rc = 0, i = 0; + uintptr_t generic_ptr; + uint32_t total_cmd_buf_in_bytes = 0; + uint32_t processed_cmd_buf_in_bytes = 0; + uint16_t cmd_length_in_bytes = 0; + uint32_t *cmd_buf = NULL; + uint32_t *offset = NULL; + uint32_t frm_offset = 0; + size_t len_of_buffer; + size_t remain_len; + struct cam_flash_init *flash_init = NULL; + struct common_header *cmn_hdr = NULL; + struct cam_control *ioctl_ctrl = NULL; + struct cam_packet *csl_packet = NULL; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct cam_config_dev_cmd config; + struct cam_req_mgr_add_request add_req; + struct i2c_data_settings *i2c_data = NULL; + struct i2c_settings_array *i2c_reg_settings = NULL; + struct cam_sensor_power_ctrl_t *power_info = NULL; + + if (!fctrl || !arg) { + CAM_ERR(CAM_FLASH, "fctrl/arg is NULL"); + return -EINVAL; + } + /* getting CSL Packet */ + ioctl_ctrl = (struct cam_control *)arg; + + if (copy_from_user((&config), (void __user *) ioctl_ctrl->handle, + sizeof(config))) { + CAM_ERR(CAM_FLASH, "Copy cmd handle from user failed"); + return -EFAULT; + } + + rc = cam_mem_get_cpu_buf(config.packet_handle, + &generic_ptr, &len_of_buffer); + if (rc) { + CAM_ERR(CAM_FLASH, "Failed in getting the packet : %d", rc); + return rc; + } + remain_len = len_of_buffer; + if ((sizeof(struct cam_packet) > len_of_buffer) || + ((size_t)config.offset >= len_of_buffer - + sizeof(struct cam_packet))) { + CAM_ERR(CAM_FLASH, + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), len_of_buffer); + return -EINVAL; + } + + remain_len -= (size_t)config.offset; + /* Add offset to the flash csl header */ + csl_packet = (struct cam_packet *)(generic_ptr + config.offset); + + if (cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_FLASH, "Invalid packet params"); + return -EINVAL; + } + + if ((csl_packet->header.op_code & 0xFFFFFF) != + CAM_FLASH_PACKET_OPCODE_INIT && + csl_packet->header.request_id <= fctrl->last_flush_req + && fctrl->last_flush_req != 0) { + CAM_DBG(CAM_FLASH, + "reject request %lld, last request to flush %lld", + csl_packet->header.request_id, fctrl->last_flush_req); + return -EINVAL; + } + + if (csl_packet->header.request_id > fctrl->last_flush_req) + fctrl->last_flush_req = 0; + + switch (csl_packet->header.op_code & 0xFFFFFF) { + case CAM_FLASH_PACKET_OPCODE_INIT: { + /* INIT packet*/ + offset = (uint32_t *)((uint8_t *)&csl_packet->payload + + csl_packet->cmd_buf_offset); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + + /* Loop through multiple command buffers */ + for (i = 1; i < csl_packet->num_cmd_buf; i++) { + total_cmd_buf_in_bytes = cmd_desc[i].length; + processed_cmd_buf_in_bytes = 0; + if (!total_cmd_buf_in_bytes) + continue; + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, + &generic_ptr, &len_of_buffer); + if (rc < 0) { + CAM_ERR(CAM_FLASH, "Failed to get cpu buf"); + return rc; + } + cmd_buf = (uint32_t *)generic_ptr; + if (!cmd_buf) { + CAM_ERR(CAM_FLASH, "invalid cmd buf"); + return -EINVAL; + } + + if ((len_of_buffer < sizeof(struct common_header)) || + (cmd_desc[i].offset > + (len_of_buffer - + sizeof(struct common_header)))) { + CAM_ERR(CAM_FLASH, "invalid cmd buf length"); + return -EINVAL; + } + remain_len = len_of_buffer - cmd_desc[i].offset; + cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); + cmn_hdr = (struct common_header *)cmd_buf; + + /* Loop through cmd formats in one cmd buffer */ + CAM_DBG(CAM_FLASH, + "command Type: %d,Processed: %d,Total: %d", + cmn_hdr->cmd_type, processed_cmd_buf_in_bytes, + total_cmd_buf_in_bytes); + switch (cmn_hdr->cmd_type) { + case CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_INFO: + if (len_of_buffer < + sizeof(struct cam_flash_init)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + return -EINVAL; + } + + flash_init = (struct cam_flash_init *)cmd_buf; + fctrl->flash_type = flash_init->flash_type; + cmd_length_in_bytes = + sizeof(struct cam_flash_init); + processed_cmd_buf_in_bytes += + cmd_length_in_bytes; + cmd_buf += cmd_length_in_bytes/ + sizeof(uint32_t); + break; + case CAMERA_SENSOR_CMD_TYPE_I2C_INFO: + rc = cam_flash_slaveInfo_pkt_parser( + fctrl, cmd_buf, remain_len); + if (rc < 0) { + CAM_ERR(CAM_FLASH, + "Failed parsing slave info: rc: %d", + rc); + return rc; + } + cmd_length_in_bytes = + sizeof(struct cam_cmd_i2c_info); + processed_cmd_buf_in_bytes += + cmd_length_in_bytes; + cmd_buf += cmd_length_in_bytes/ + sizeof(uint32_t); + break; + case CAMERA_SENSOR_CMD_TYPE_PWR_UP: + case CAMERA_SENSOR_CMD_TYPE_PWR_DOWN: + CAM_DBG(CAM_FLASH, + "Received power settings"); + cmd_length_in_bytes = + total_cmd_buf_in_bytes; + rc = cam_sensor_update_power_settings( + cmd_buf, + total_cmd_buf_in_bytes, + &fctrl->power_info, remain_len); + processed_cmd_buf_in_bytes += + cmd_length_in_bytes; + cmd_buf += cmd_length_in_bytes/ + sizeof(uint32_t); + if (rc) { + CAM_ERR(CAM_FLASH, + "Failed update power settings"); + return rc; + } + break; + default: + CAM_DBG(CAM_FLASH, + "Received initSettings"); + i2c_data = &(fctrl->i2c_data); + i2c_reg_settings = + &fctrl->i2c_data.init_settings; + + i2c_reg_settings->request_id = 0; + i2c_reg_settings->is_settings_valid = 1; + rc = cam_sensor_i2c_command_parser( + &fctrl->io_master_info, + i2c_reg_settings, + &cmd_desc[i], 1, NULL); + if (rc < 0) { + CAM_ERR(CAM_FLASH, + "pkt parsing failed: %d", rc); + return rc; + } + cmd_length_in_bytes = + cmd_desc[i].length; + processed_cmd_buf_in_bytes += + cmd_length_in_bytes; + cmd_buf += cmd_length_in_bytes/ + sizeof(uint32_t); + + break; + } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + } + power_info = &fctrl->power_info; + if (!power_info) { + CAM_ERR(CAM_FLASH, "Power_info is NULL"); + return -EINVAL; + } + + /* Parse and fill vreg params for power up settings */ + rc = msm_camera_fill_vreg_params(&fctrl->soc_info, + power_info->power_setting, + power_info->power_setting_size); + if (rc) { + CAM_ERR(CAM_FLASH, + "failed to fill vreg params for power up rc:%d", + rc); + return rc; + } + + /* Parse and fill vreg params for power down settings*/ + rc = msm_camera_fill_vreg_params( + &fctrl->soc_info, + power_info->power_down_setting, + power_info->power_down_setting_size); + if (rc) { + CAM_ERR(CAM_FLASH, + "failed to fill vreg params power down rc:%d", + rc); + return rc; + } + + rc = fctrl->func_tbl.power_ops(fctrl, true); + if (rc) { + CAM_ERR(CAM_FLASH, + "Enable Regulator Failed rc = %d", rc); + return rc; + } + + rc = fctrl->func_tbl.apply_setting(fctrl, 0); + if (rc) { + CAM_ERR(CAM_FLASH, + "cannot apply settings rc = %d", rc); + return rc; + } + + fctrl->flash_state = CAM_FLASH_STATE_CONFIG; + break; + } + case CAM_FLASH_PACKET_OPCODE_SET_OPS: { + offset = (uint32_t *)((uint8_t *)&csl_packet->payload + + csl_packet->cmd_buf_offset); + frm_offset = csl_packet->header.request_id % + MAX_PER_FRAME_ARRAY; + /* add support for handling i2c_data*/ + i2c_reg_settings = + &fctrl->i2c_data.per_frame[frm_offset]; + if (i2c_reg_settings->is_settings_valid == true) { + CAM_DBG(CAM_FLASH, "settings already valid"); + i2c_reg_settings->request_id = 0; + i2c_reg_settings->is_settings_valid = false; + goto update_req_mgr; + } + i2c_reg_settings->is_settings_valid = true; + i2c_reg_settings->request_id = + csl_packet->header.request_id; + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + rc = cam_sensor_i2c_command_parser( + &fctrl->io_master_info, + i2c_reg_settings, cmd_desc, 1, NULL); + if (rc) { + CAM_ERR(CAM_FLASH, + "Failed in parsing i2c packets"); + return rc; + } + if ((fctrl->flash_state == CAM_FLASH_STATE_ACQUIRE) || + (fctrl->flash_state == CAM_FLASH_STATE_CONFIG)) { + fctrl->flash_state = CAM_FLASH_STATE_CONFIG; + rc = fctrl->func_tbl.apply_setting(fctrl, 1); + if (rc) { + CAM_ERR(CAM_FLASH, + "cannot apply fire settings rc = %d", + rc); + return rc; + } + return rc; + } + break; + } + case CAM_FLASH_PACKET_OPCODE_NON_REALTIME_SET_OPS: { + offset = (uint32_t *)((uint8_t *)&csl_packet->payload + + csl_packet->cmd_buf_offset); + + /* add support for handling i2c_data*/ + i2c_reg_settings = &fctrl->i2c_data.config_settings; + if (i2c_reg_settings->is_settings_valid == true) { + i2c_reg_settings->request_id = 0; + i2c_reg_settings->is_settings_valid = false; + + rc = delete_request(i2c_reg_settings); + if (rc) { + CAM_ERR(CAM_FLASH, + "Failed in Deleting the err: %d", rc); + return rc; + } + } + i2c_reg_settings->is_settings_valid = true; + i2c_reg_settings->request_id = + csl_packet->header.request_id; + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + rc = cam_sensor_i2c_command_parser( + &fctrl->io_master_info, + i2c_reg_settings, cmd_desc, 1, NULL); + if (rc) { + CAM_ERR(CAM_FLASH, + "Failed in parsing i2c NRT packets"); + return rc; + } + rc = fctrl->func_tbl.apply_setting(fctrl, 0); + if (rc) + CAM_ERR(CAM_FLASH, + "Apply setting failed: %d", rc); + return rc; + } + case CAM_PKT_NOP_OPCODE: { + frm_offset = csl_packet->header.request_id % + MAX_PER_FRAME_ARRAY; + if ((fctrl->flash_state == CAM_FLASH_STATE_INIT) || + (fctrl->flash_state == CAM_FLASH_STATE_ACQUIRE)) { + CAM_WARN(CAM_FLASH, + "Rxed NOP packets without linking"); + fctrl->i2c_data.per_frame[frm_offset].is_settings_valid + = false; + return 0; + } + i2c_reg_settings = + &fctrl->i2c_data.per_frame[frm_offset]; + i2c_reg_settings->is_settings_valid = true; + i2c_reg_settings->request_id = + csl_packet->header.request_id; + CAM_DBG(CAM_FLASH, "NOP Packet is Received: req_id: %u", + csl_packet->header.request_id); + goto update_req_mgr; + } + case CAM_FLASH_PACKET_OPCODE_STREAM_OFF: { + if (fctrl->streamoff_count > 0) + return rc; + + CAM_DBG(CAM_FLASH, "Received Stream off Settings"); + i2c_data = &(fctrl->i2c_data); + fctrl->streamoff_count = fctrl->streamoff_count + 1; + i2c_reg_settings = &i2c_data->streamoff_settings; + i2c_reg_settings->request_id = 0; + i2c_reg_settings->is_settings_valid = 1; + offset = (uint32_t *)((uint8_t *)&csl_packet->payload + + csl_packet->cmd_buf_offset); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + rc = cam_sensor_i2c_command_parser(&fctrl->io_master_info, + i2c_reg_settings, + cmd_desc, 1, NULL); + if (rc) { + CAM_ERR(CAM_FLASH, + "Failed in parsing i2c Stream off packets"); + return rc; + } + break; + } + default: + CAM_ERR(CAM_FLASH, "Wrong Opcode : %d", + (csl_packet->header.op_code & 0xFFFFFF)); + return -EINVAL; + } +update_req_mgr: + if (((csl_packet->header.op_code & 0xFFFFF) == + CAM_PKT_NOP_OPCODE) || + ((csl_packet->header.op_code & 0xFFFFF) == + CAM_FLASH_PACKET_OPCODE_SET_OPS)) { + add_req.link_hdl = fctrl->bridge_intf.link_hdl; + add_req.req_id = csl_packet->header.request_id; + add_req.dev_hdl = fctrl->bridge_intf.device_hdl; + + if ((csl_packet->header.op_code & 0xFFFFF) == + CAM_FLASH_PACKET_OPCODE_SET_OPS) + add_req.skip_before_applying = 1; + else + add_req.skip_before_applying = 0; + + if (fctrl->bridge_intf.crm_cb && + fctrl->bridge_intf.crm_cb->add_req) + fctrl->bridge_intf.crm_cb->add_req(&add_req); + CAM_DBG(CAM_FLASH, "add req to req_mgr= %lld", add_req.req_id); + } + cam_mem_put_cpu_buf(config.packet_handle); + return rc; +} + +int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) +{ + int rc = 0, i = 0; + uintptr_t generic_ptr, cmd_buf_ptr; + uint32_t *cmd_buf = NULL; + uint32_t *offset = NULL; + uint32_t frm_offset = 0; + size_t len_of_buffer; + size_t remain_len; + struct cam_control *ioctl_ctrl = NULL; + struct cam_packet *csl_packet = NULL; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct common_header *cmn_hdr; + struct cam_config_dev_cmd config; + struct cam_req_mgr_add_request add_req = {0}; + struct cam_flash_init *cam_flash_info = NULL; + struct cam_flash_set_rer *flash_rer_info = NULL; + struct cam_flash_set_on_off *flash_operation_info = NULL; + struct cam_flash_query_curr *flash_query_info = NULL; + struct cam_flash_frame_setting *flash_data = NULL; + struct cam_flash_private_soc *soc_private = NULL; + + if (!fctrl || !arg) { + CAM_ERR(CAM_FLASH, "fctrl/arg is NULL"); + return -EINVAL; + } + + soc_private = (struct cam_flash_private_soc *) + fctrl->soc_info.soc_private; + + /* getting CSL Packet */ + ioctl_ctrl = (struct cam_control *)arg; + + if (copy_from_user((&config), + u64_to_user_ptr(ioctl_ctrl->handle), + sizeof(config))) { + CAM_ERR(CAM_FLASH, "Copy cmd handle from user failed"); + rc = -EFAULT; + return rc; + } + + rc = cam_mem_get_cpu_buf(config.packet_handle, + &generic_ptr, &len_of_buffer); + if (rc) { + CAM_ERR(CAM_FLASH, "Failed in getting the packet: %d", rc); + return rc; + } + + remain_len = len_of_buffer; + if ((sizeof(struct cam_packet) > len_of_buffer) || + ((size_t)config.offset >= len_of_buffer - + sizeof(struct cam_packet))) { + CAM_ERR(CAM_FLASH, + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), len_of_buffer); + rc = -EINVAL; + return rc; + } + + remain_len -= (size_t)config.offset; + /* Add offset to the flash csl header */ + csl_packet = (struct cam_packet *)(generic_ptr + config.offset); + + if (cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_FLASH, "Invalid packet params"); + rc = -EINVAL; + return rc; + } + + if ((csl_packet->header.op_code & 0xFFFFFF) != + CAM_FLASH_PACKET_OPCODE_INIT && + csl_packet->header.request_id <= fctrl->last_flush_req + && fctrl->last_flush_req != 0) { + CAM_WARN(CAM_FLASH, + "reject request %lld, last request to flush %d", + csl_packet->header.request_id, fctrl->last_flush_req); + rc = -EINVAL; + return rc; + } + + if (csl_packet->header.request_id > fctrl->last_flush_req) + fctrl->last_flush_req = 0; + + switch (csl_packet->header.op_code & 0xFFFFFF) { + case CAM_FLASH_PACKET_OPCODE_INIT: { + /* INIT packet*/ + offset = (uint32_t *)((uint8_t *)&csl_packet->payload + + csl_packet->cmd_buf_offset); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, + &cmd_buf_ptr, &len_of_buffer); + if (rc) { + CAM_ERR(CAM_FLASH, "Fail in get buffer: %d", rc); + return rc; + } + if ((len_of_buffer < sizeof(struct cam_flash_init)) || + (cmd_desc->offset > + (len_of_buffer - sizeof(struct cam_flash_init)))) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + return rc; + } + remain_len = len_of_buffer - cmd_desc->offset; + cmd_buf = (uint32_t *)((uint8_t *)cmd_buf_ptr + + cmd_desc->offset); + cam_flash_info = (struct cam_flash_init *)cmd_buf; + + switch (cam_flash_info->cmd_type) { + case CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_INFO: { + CAM_DBG(CAM_FLASH, "INIT_INFO CMD CALLED"); + fctrl->flash_init_setting.cmn_attr.request_id = 0; + fctrl->flash_init_setting.cmn_attr.is_settings_valid = + true; + fctrl->flash_type = cam_flash_info->flash_type; + fctrl->is_regulator_enabled = false; + fctrl->nrt_info.cmn_attr.cmd_type = + CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_INFO; + + rc = fctrl->func_tbl.power_ops(fctrl, true); + if (rc) { + CAM_ERR(CAM_FLASH, + "Enable Regulator Failed rc = %d", rc); + return rc; + } + + fctrl->flash_state = + CAM_FLASH_STATE_CONFIG; + break; + } + case CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_FIRE: { + CAM_DBG(CAM_FLASH, "INIT_FIRE Operation"); + + if (remain_len < sizeof(struct cam_flash_set_on_off)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + return rc; + } + + flash_operation_info = + (struct cam_flash_set_on_off *) cmd_buf; + if (!flash_operation_info) { + CAM_ERR(CAM_FLASH, + "flash_operation_info Null"); + rc = -EINVAL; + return rc; + } + if (flash_operation_info->count > + CAM_FLASH_MAX_LED_TRIGGERS) { + CAM_ERR(CAM_FLASH, "led count out of limit"); + rc = -EINVAL; + return rc; + } + fctrl->nrt_info.cmn_attr.count = + flash_operation_info->count; + fctrl->nrt_info.cmn_attr.request_id = 0; + fctrl->nrt_info.opcode = + flash_operation_info->opcode; + fctrl->nrt_info.cmn_attr.cmd_type = + CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_FIRE; + for (i = 0; + i < flash_operation_info->count; i++) + fctrl->nrt_info.led_current_ma[i] = + flash_operation_info->led_current_ma[i]; + + rc = fctrl->func_tbl.apply_setting(fctrl, 0); + if (rc) + CAM_ERR(CAM_FLASH, + "Apply setting failed: %d", + rc); + + fctrl->flash_state = CAM_FLASH_STATE_CONFIG; + break; + } + default: + CAM_ERR(CAM_FLASH, "Wrong cmd_type = %d", + cam_flash_info->cmd_type); + rc = -EINVAL; + return rc; + } + + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + break; + } + case CAM_FLASH_PACKET_OPCODE_SET_OPS: { + offset = (uint32_t *)((uint8_t *)&csl_packet->payload + + csl_packet->cmd_buf_offset); + frm_offset = csl_packet->header.request_id % + MAX_PER_FRAME_ARRAY; + flash_data = &fctrl->per_frame[frm_offset]; + + if (flash_data->cmn_attr.is_settings_valid == true) { + flash_data->cmn_attr.request_id = 0; + flash_data->cmn_attr.is_settings_valid = false; + for (i = 0; i < flash_data->cmn_attr.count; i++) + flash_data->led_current_ma[i] = 0; + } + + flash_data->cmn_attr.request_id = csl_packet->header.request_id; + flash_data->cmn_attr.is_settings_valid = true; + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, + &cmd_buf_ptr, &len_of_buffer); + if (rc) { + CAM_ERR(CAM_FLASH, "Fail in get buffer: 0x%x", + cmd_desc->mem_handle); + return rc; + } + + if ((len_of_buffer < sizeof(struct common_header)) || + (cmd_desc->offset > + (len_of_buffer - sizeof(struct common_header)))) { + CAM_ERR(CAM_FLASH, "not enough buffer"); + rc = -EINVAL; + return rc; + } + remain_len = len_of_buffer - cmd_desc->offset; + + cmd_buf = (uint32_t *)((uint8_t *)cmd_buf_ptr + + cmd_desc->offset); + if (!cmd_buf) { + rc = -EINVAL; + return rc; + } + cmn_hdr = (struct common_header *)cmd_buf; + + switch (cmn_hdr->cmd_type) { + case CAMERA_SENSOR_FLASH_CMD_TYPE_FIRE: { + CAM_DBG(CAM_FLASH, + "CAMERA_SENSOR_FLASH_CMD_TYPE_FIRE cmd called"); + if ((fctrl->flash_state == CAM_FLASH_STATE_INIT) || + (fctrl->flash_state == + CAM_FLASH_STATE_ACQUIRE)) { + CAM_WARN(CAM_FLASH, + "Rxed Flash fire ops without linking"); + flash_data->cmn_attr.is_settings_valid = false; + return -EINVAL; + } + if (remain_len < sizeof(struct cam_flash_set_on_off)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + return rc; + } + + flash_operation_info = + (struct cam_flash_set_on_off *) cmd_buf; + if (!flash_operation_info) { + CAM_ERR(CAM_FLASH, + "flash_operation_info Null"); + rc = -EINVAL; + return rc; + } + if (flash_operation_info->count > + CAM_FLASH_MAX_LED_TRIGGERS) { + CAM_ERR(CAM_FLASH, "led count out of limit"); + rc = -EINVAL; + return rc; + } + + flash_data->opcode = flash_operation_info->opcode; + flash_data->cmn_attr.count = + flash_operation_info->count; + for (i = 0; i < flash_operation_info->count; i++) + flash_data->led_current_ma[i] + = flash_operation_info->led_current_ma[i]; + + if (flash_data->opcode == CAMERA_SENSOR_FLASH_OP_OFF) + add_req.skip_before_applying |= SKIP_NEXT_FRAME; + } + break; + default: + CAM_ERR(CAM_FLASH, "Wrong cmd_type = %d", + cmn_hdr->cmd_type); + rc = -EINVAL; + return rc; + } + + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + break; + } + case CAM_FLASH_PACKET_OPCODE_NON_REALTIME_SET_OPS: { + offset = (uint32_t *)((uint8_t *)&csl_packet->payload + + csl_packet->cmd_buf_offset); + fctrl->nrt_info.cmn_attr.is_settings_valid = true; + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, + &cmd_buf_ptr, &len_of_buffer); + if (rc) { + CAM_ERR(CAM_FLASH, "Fail in get buffer: %d", rc); + return rc; + } + + if ((len_of_buffer < sizeof(struct common_header)) || + (cmd_desc->offset > + (len_of_buffer - sizeof(struct common_header)))) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + return rc; + } + remain_len = len_of_buffer - cmd_desc->offset; + cmd_buf = (uint32_t *)((uint8_t *)cmd_buf_ptr + + cmd_desc->offset); + cmn_hdr = (struct common_header *)cmd_buf; + + switch (cmn_hdr->cmd_type) { + case CAMERA_SENSOR_FLASH_CMD_TYPE_WIDGET: { + CAM_DBG(CAM_FLASH, "Widget Flash Operation"); + if (remain_len < sizeof(struct cam_flash_set_on_off)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + return rc; + } + flash_operation_info = + (struct cam_flash_set_on_off *) cmd_buf; + if (!flash_operation_info) { + CAM_ERR(CAM_FLASH, + "flash_operation_info Null"); + rc = -EINVAL; + return rc; + } + if (flash_operation_info->count > + CAM_FLASH_MAX_LED_TRIGGERS) { + CAM_ERR(CAM_FLASH, "led count out of limit"); + rc = -EINVAL; + return rc; + } + + fctrl->nrt_info.cmn_attr.count = + flash_operation_info->count; + fctrl->nrt_info.cmn_attr.request_id = 0; + fctrl->nrt_info.opcode = + flash_operation_info->opcode; + fctrl->nrt_info.cmn_attr.cmd_type = + CAMERA_SENSOR_FLASH_CMD_TYPE_WIDGET; + + for (i = 0; i < flash_operation_info->count; i++) + fctrl->nrt_info.led_current_ma[i] = + flash_operation_info->led_current_ma[i]; + + rc = fctrl->func_tbl.apply_setting(fctrl, 0); + if (rc) + CAM_ERR(CAM_FLASH, "Apply setting failed: %d", + rc); + return rc; + } + case CAMERA_SENSOR_FLASH_CMD_TYPE_QUERYCURR: { + int query_curr_ma = 0; + + if (remain_len < sizeof(struct cam_flash_query_curr)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + return rc; + } + flash_query_info = + (struct cam_flash_query_curr *)cmd_buf; + + if (soc_private->is_wled_flash) + rc = wled_flash_led_prepare( + fctrl->switch_trigger, + QUERY_MAX_AVAIL_CURRENT, + &query_curr_ma); + else + rc = qpnp_flash_led_prepare( + fctrl->switch_trigger, + QUERY_MAX_AVAIL_CURRENT, + &query_curr_ma); + + CAM_DBG(CAM_FLASH, "query_curr_ma = %d", + query_curr_ma); + if (rc) { + CAM_ERR(CAM_FLASH, + "Query current failed with rc=%d", rc); + return rc; + } + flash_query_info->query_current_ma = query_curr_ma; + break; + } + case CAMERA_SENSOR_FLASH_CMD_TYPE_RER: { + rc = 0; + if (remain_len < sizeof(struct cam_flash_set_rer)) { + CAM_ERR(CAM_FLASH, "Not enough buffer"); + rc = -EINVAL; + return rc; + } + flash_rer_info = (struct cam_flash_set_rer *)cmd_buf; + if (!flash_rer_info) { + CAM_ERR(CAM_FLASH, + "flash_rer_info Null"); + rc = -EINVAL; + return rc; + } + if (flash_rer_info->count > + CAM_FLASH_MAX_LED_TRIGGERS) { + CAM_ERR(CAM_FLASH, "led count out of limit"); + rc = -EINVAL; + return rc; + } + + fctrl->nrt_info.cmn_attr.cmd_type = + CAMERA_SENSOR_FLASH_CMD_TYPE_RER; + fctrl->nrt_info.opcode = flash_rer_info->opcode; + fctrl->nrt_info.cmn_attr.count = flash_rer_info->count; + fctrl->nrt_info.cmn_attr.request_id = 0; + fctrl->nrt_info.num_iterations = + flash_rer_info->num_iteration; + fctrl->nrt_info.led_on_delay_ms = + flash_rer_info->led_on_delay_ms; + fctrl->nrt_info.led_off_delay_ms = + flash_rer_info->led_off_delay_ms; + + for (i = 0; i < flash_rer_info->count; i++) + fctrl->nrt_info.led_current_ma[i] = + flash_rer_info->led_current_ma[i]; + + rc = fctrl->func_tbl.apply_setting(fctrl, 0); + if (rc) + CAM_ERR(CAM_FLASH, "apply_setting failed: %d", + rc); + return rc; + } + default: + CAM_ERR(CAM_FLASH, "Wrong cmd_type : %d", + cmn_hdr->cmd_type); + rc = -EINVAL; + return rc; + } + + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + break; + } + case CAM_PKT_NOP_OPCODE: { + frm_offset = csl_packet->header.request_id % + MAX_PER_FRAME_ARRAY; + if ((fctrl->flash_state == CAM_FLASH_STATE_INIT) || + (fctrl->flash_state == CAM_FLASH_STATE_ACQUIRE)) { + CAM_WARN(CAM_FLASH, + "Rxed NOP packets without linking"); + fctrl->per_frame[frm_offset].cmn_attr.is_settings_valid + = false; + return -EINVAL; + } + + fctrl->per_frame[frm_offset].cmn_attr.is_settings_valid = false; + fctrl->per_frame[frm_offset].cmn_attr.request_id = 0; + fctrl->per_frame[frm_offset].opcode = CAM_PKT_NOP_OPCODE; + CAM_DBG(CAM_FLASH, "NOP Packet is Received: req_id: %llu", + csl_packet->header.request_id); + break; + } + default: + CAM_ERR(CAM_FLASH, "Wrong Opcode : %d", + (csl_packet->header.op_code & 0xFFFFFF)); + rc = -EINVAL; + return rc; + } + + if (((csl_packet->header.op_code & 0xFFFFF) == + CAM_PKT_NOP_OPCODE) || + ((csl_packet->header.op_code & 0xFFFFF) == + CAM_FLASH_PACKET_OPCODE_SET_OPS)) { + add_req.link_hdl = fctrl->bridge_intf.link_hdl; + add_req.req_id = csl_packet->header.request_id; + add_req.dev_hdl = fctrl->bridge_intf.device_hdl; + + if ((csl_packet->header.op_code & 0xFFFFF) == + CAM_FLASH_PACKET_OPCODE_SET_OPS) + add_req.skip_before_applying |= 1; + else + add_req.skip_before_applying = 0; + + if (fctrl->bridge_intf.crm_cb && + fctrl->bridge_intf.crm_cb->add_req) + fctrl->bridge_intf.crm_cb->add_req(&add_req); + CAM_DBG(CAM_FLASH, "add req to req_mgr= %lld", add_req.req_id); + } + + cam_mem_put_cpu_buf(config.packet_handle); + return rc; +} + +int cam_flash_publish_dev_info(struct cam_req_mgr_device_info *info) +{ + info->dev_id = CAM_REQ_MGR_DEVICE_FLASH; + strlcpy(info->name, CAM_FLASH_NAME, sizeof(info->name)); + info->p_delay = CAM_FLASH_PIPELINE_DELAY; + info->trigger = CAM_TRIGGER_POINT_SOF; + return 0; +} + +int cam_flash_establish_link(struct cam_req_mgr_core_dev_link_setup *link) +{ + struct cam_flash_ctrl *fctrl = NULL; + + if (!link) + return -EINVAL; + + fctrl = (struct cam_flash_ctrl *)cam_get_device_priv(link->dev_hdl); + if (!fctrl) { + CAM_ERR(CAM_FLASH, " Device data is NULL"); + return -EINVAL; + } + mutex_lock(&fctrl->flash_mutex); + if (link->link_enable) { + fctrl->bridge_intf.link_hdl = link->link_hdl; + fctrl->bridge_intf.crm_cb = link->crm_cb; + } else { + fctrl->bridge_intf.link_hdl = -1; + fctrl->bridge_intf.crm_cb = NULL; + } + mutex_unlock(&fctrl->flash_mutex); + + return 0; +} + +int cam_flash_release_dev(struct cam_flash_ctrl *fctrl) +{ + int rc = 0; + + if (fctrl->i2c_data.streamoff_settings.is_settings_valid == true) { + fctrl->i2c_data.streamoff_settings.is_settings_valid = false; + rc = delete_request(&fctrl->i2c_data.streamoff_settings); + if (rc) { + CAM_WARN(CAM_FLASH, + "Failed to delete Stream off i2c_setting: %d", + rc); + } + } + + if (fctrl->bridge_intf.device_hdl != 1) { + rc = cam_destroy_device_hdl(fctrl->bridge_intf.device_hdl); + if (rc) + CAM_ERR(CAM_FLASH, + "Failed in destroying device handle rc = %d", + rc); + fctrl->bridge_intf.device_hdl = -1; + fctrl->bridge_intf.link_hdl = -1; + fctrl->bridge_intf.session_hdl = -1; + fctrl->last_flush_req = 0; + fctrl->streamoff_count = 0; + } + + return rc; +} + +void cam_flash_shutdown(struct cam_flash_ctrl *fctrl) +{ + int rc; + + if (fctrl->flash_state == CAM_FLASH_STATE_INIT) + return; + + if ((fctrl->flash_state == CAM_FLASH_STATE_CONFIG) || + (fctrl->flash_state == CAM_FLASH_STATE_START)) { + fctrl->func_tbl.flush_req(fctrl, FLUSH_ALL, 0); + rc = cam_flash_off(fctrl); + if (rc) { + CAM_ERR(CAM_FLASH, + "LED OFF FAILED: %d", + rc); + } + rc = fctrl->func_tbl.power_ops(fctrl, false); + if (rc) + CAM_ERR(CAM_FLASH, "Power Down Failed rc: %d", + rc); + } + + rc = cam_flash_release_dev(fctrl); + if (rc) + CAM_ERR(CAM_FLASH, "Release failed rc: %d", rc); + + fctrl->flash_state = CAM_FLASH_STATE_INIT; +} + +int cam_flash_apply_request(struct cam_req_mgr_apply_request *apply) +{ + int rc = 0; + struct cam_flash_ctrl *fctrl = NULL; + + if (!apply) + return -EINVAL; + + fctrl = (struct cam_flash_ctrl *) cam_get_device_priv(apply->dev_hdl); + if (!fctrl) { + CAM_ERR(CAM_FLASH, "Device data is NULL"); + return -EINVAL; + } + + mutex_lock(&fctrl->flash_mutex); + rc = fctrl->func_tbl.apply_setting(fctrl, apply->request_id); + if (rc) + CAM_ERR(CAM_FLASH, "apply_setting failed with rc=%d", + rc); + mutex_unlock(&fctrl->flash_mutex); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_core.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_core.h new file mode 100644 index 0000000000000000000000000000000000000000..c382809dbb92199df12dead139795e7632cb8bcc --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_core.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_FLASH_CORE_H_ +#define _CAM_FLASH_CORE_H_ + +#include +#include "cam_flash_dev.h" + +int cam_flash_publish_dev_info(struct cam_req_mgr_device_info *info); +int cam_flash_establish_link(struct cam_req_mgr_core_dev_link_setup *link); +int cam_flash_apply_request(struct cam_req_mgr_apply_request *apply); +int cam_flash_process_evt(struct cam_req_mgr_link_evt_data *event_data); +int cam_flash_flush_request(struct cam_req_mgr_flush_request *flush); + + +#endif /*_CAM_FLASH_CORE_H_*/ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..947117c3342a7dcce9079877ad35b361c9ed9b56 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c @@ -0,0 +1,720 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_flash_dev.h" +#include "cam_flash_soc.h" +#include "cam_flash_core.h" +#include "cam_common_util.h" + +static int32_t cam_flash_driver_cmd(struct cam_flash_ctrl *fctrl, + void *arg, struct cam_flash_private_soc *soc_private) +{ + int rc = 0; + int i = 0; + struct cam_control *cmd = (struct cam_control *)arg; + + if (!fctrl || !arg) { + CAM_ERR(CAM_FLASH, "fctrl/arg is NULL with arg:%pK fctrl%pK", + fctrl, arg); + return -EINVAL; + } + + if (cmd->handle_type != CAM_HANDLE_USER_POINTER) { + CAM_ERR(CAM_FLASH, "Invalid handle type: %d", + cmd->handle_type); + return -EINVAL; + } + + mutex_lock(&(fctrl->flash_mutex)); + switch (cmd->op_code) { + case CAM_ACQUIRE_DEV: { + struct cam_sensor_acquire_dev flash_acq_dev; + struct cam_create_dev_hdl bridge_params; + + CAM_DBG(CAM_FLASH, "CAM_ACQUIRE_DEV"); + + if (fctrl->flash_state != CAM_FLASH_STATE_INIT) { + CAM_ERR(CAM_FLASH, + "Cannot apply Acquire dev: Prev state: %d", + fctrl->flash_state); + rc = -EINVAL; + goto release_mutex; + } + + if (fctrl->bridge_intf.device_hdl != -1) { + CAM_ERR(CAM_FLASH, "Device is already acquired"); + rc = -EINVAL; + goto release_mutex; + } + + rc = copy_from_user(&flash_acq_dev, + u64_to_user_ptr(cmd->handle), + sizeof(flash_acq_dev)); + if (rc) { + CAM_ERR(CAM_FLASH, "Failed Copying from User"); + goto release_mutex; + } + + bridge_params.session_hdl = flash_acq_dev.session_handle; + bridge_params.ops = &fctrl->bridge_intf.ops; + bridge_params.v4l2_sub_dev_flag = 0; + bridge_params.media_entity_flag = 0; + bridge_params.priv = fctrl; + bridge_params.dev_id = CAM_FLASH; + + flash_acq_dev.device_handle = + cam_create_device_hdl(&bridge_params); + if (flash_acq_dev.device_handle <= 0) { + rc = -EFAULT; + CAM_ERR(CAM_FLASH, "Can not create device handle"); + goto release_mutex; + } + fctrl->bridge_intf.device_hdl = + flash_acq_dev.device_handle; + fctrl->bridge_intf.session_hdl = + flash_acq_dev.session_handle; + fctrl->apply_streamoff = false; + + rc = copy_to_user(u64_to_user_ptr(cmd->handle), + &flash_acq_dev, + sizeof(struct cam_sensor_acquire_dev)); + if (rc) { + CAM_ERR(CAM_FLASH, "Failed Copy to User with rc = %d", + rc); + rc = -EFAULT; + goto release_mutex; + } + fctrl->flash_state = CAM_FLASH_STATE_ACQUIRE; + break; + } + case CAM_RELEASE_DEV: { + CAM_DBG(CAM_FLASH, "CAM_RELEASE_DEV"); + if ((fctrl->flash_state == CAM_FLASH_STATE_INIT) || + (fctrl->flash_state == CAM_FLASH_STATE_START)) { + CAM_WARN(CAM_FLASH, + "Wrong state for Release dev: Prev state:%d", + fctrl->flash_state); + } + + if (fctrl->bridge_intf.device_hdl == -1 && + fctrl->flash_state == CAM_FLASH_STATE_ACQUIRE) { + CAM_ERR(CAM_FLASH, + "Invalid Handle: Link Hdl: %d device hdl: %d", + fctrl->bridge_intf.device_hdl, + fctrl->bridge_intf.link_hdl); + rc = -EINVAL; + goto release_mutex; + } + + if (fctrl->bridge_intf.link_hdl != -1) { + CAM_ERR(CAM_FLASH, + "Device [%d] still active on link 0x%x", + fctrl->flash_state, + fctrl->bridge_intf.link_hdl); + rc = -EAGAIN; + goto release_mutex; + } + + if ((fctrl->flash_state == CAM_FLASH_STATE_CONFIG) || + (fctrl->flash_state == CAM_FLASH_STATE_START)) + fctrl->func_tbl.flush_req(fctrl, FLUSH_ALL, 0); + + if (cam_flash_release_dev(fctrl)) + CAM_WARN(CAM_FLASH, + "Failed in destroying the device Handle"); + + if (fctrl->func_tbl.power_ops(fctrl, false)) + CAM_WARN(CAM_FLASH, "Power Down Failed"); + + fctrl->streamoff_count = 0; + fctrl->flash_state = CAM_FLASH_STATE_INIT; + break; + } + case CAM_QUERY_CAP: { + struct cam_flash_query_cap_info flash_cap = {0}; + + CAM_DBG(CAM_FLASH, "CAM_QUERY_CAP"); + flash_cap.slot_info = fctrl->soc_info.index; + flash_cap.flash_type = soc_private->flash_type; + for (i = 0; i < fctrl->flash_num_sources; i++) { + flash_cap.max_current_flash[i] = + soc_private->flash_max_current[i]; + flash_cap.max_duration_flash[i] = + soc_private->flash_max_duration[i]; + } + + for (i = 0; i < fctrl->torch_num_sources; i++) + flash_cap.max_current_torch[i] = + soc_private->torch_max_current[i]; + + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &flash_cap, sizeof(struct cam_flash_query_cap_info))) { + CAM_ERR(CAM_FLASH, "Failed Copy to User"); + rc = -EFAULT; + goto release_mutex; + } + break; + } + case CAM_START_DEV: { + CAM_DBG(CAM_FLASH, "CAM_START_DEV"); + if ((fctrl->flash_state == CAM_FLASH_STATE_INIT) || + (fctrl->flash_state == CAM_FLASH_STATE_START)) { + CAM_WARN(CAM_FLASH, + "Cannot apply Start Dev: Prev state: %d", + fctrl->flash_state); + rc = -EINVAL; + goto release_mutex; + } + + fctrl->apply_streamoff = false; + fctrl->flash_state = CAM_FLASH_STATE_START; + break; + } + case CAM_STOP_DEV: { + CAM_DBG(CAM_FLASH, "CAM_STOP_DEV ENTER"); + if (fctrl->flash_state != CAM_FLASH_STATE_START) { + CAM_WARN(CAM_FLASH, + "Cannot apply Stop dev: Prev state is: %d", + fctrl->flash_state); + rc = -EINVAL; + goto release_mutex; + } + + cam_flash_off(fctrl); + fctrl->func_tbl.flush_req(fctrl, FLUSH_ALL, 0); + fctrl->last_flush_req = 0; + fctrl->flash_state = CAM_FLASH_STATE_ACQUIRE; + break; + } + case CAM_CONFIG_DEV: { + CAM_DBG(CAM_FLASH, "CAM_CONFIG_DEV"); + rc = fctrl->func_tbl.parser(fctrl, arg); + if (rc) { + CAM_ERR(CAM_FLASH, "Failed Flash Config: rc=%d\n", rc); + goto release_mutex; + } + break; + } + default: + CAM_ERR(CAM_FLASH, "Invalid Opcode: %d", cmd->op_code); + rc = -EINVAL; + } + +release_mutex: + mutex_unlock(&(fctrl->flash_mutex)); + return rc; +} + +static int32_t cam_flash_init_default_params(struct cam_flash_ctrl *fctrl) +{ + /* Validate input parameters */ + if (!fctrl) { + CAM_ERR(CAM_FLASH, "failed: invalid params fctrl %pK", + fctrl); + return -EINVAL; + } + + CAM_DBG(CAM_FLASH, + "master_type: %d", fctrl->io_master_info.master_type); + /* Initialize cci_client */ + if (fctrl->io_master_info.master_type == CCI_MASTER) { + fctrl->io_master_info.cci_client = kzalloc(sizeof( + struct cam_sensor_cci_client), GFP_KERNEL); + if (!(fctrl->io_master_info.cci_client)) + return -ENOMEM; + } else if (fctrl->io_master_info.master_type == I2C_MASTER) { + if (!(fctrl->io_master_info.client)) + return -EINVAL; + } else { + CAM_ERR(CAM_FLASH, + "Invalid master / Master type Not supported"); + return -EINVAL; + } + + return 0; +} + +static const struct of_device_id cam_flash_dt_match[] = { + {.compatible = "qcom,camera-flash", .data = NULL}, + {} +}; + +static long cam_flash_subdev_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + int rc = 0; + struct cam_flash_ctrl *fctrl = NULL; + struct cam_flash_private_soc *soc_private = NULL; + + CAM_DBG(CAM_FLASH, "Enter"); + + fctrl = v4l2_get_subdevdata(sd); + soc_private = fctrl->soc_info.soc_private; + + switch (cmd) { + case VIDIOC_CAM_CONTROL: { + rc = cam_flash_driver_cmd(fctrl, arg, + soc_private); + break; + } + default: + CAM_ERR(CAM_FLASH, "Invalid ioctl cmd type"); + rc = -EINVAL; + break; + } + + CAM_DBG(CAM_FLASH, "Exit"); + return rc; +} + +#ifdef CONFIG_COMPAT +static long cam_flash_subdev_do_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + struct cam_control cmd_data; + int32_t rc = 0; + + if (copy_from_user(&cmd_data, (void __user *)arg, + sizeof(cmd_data))) { + CAM_ERR(CAM_FLASH, + "Failed to copy from user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + return -EFAULT; + } + + switch (cmd) { + case VIDIOC_CAM_CONTROL: { + rc = cam_flash_subdev_ioctl(sd, cmd, &cmd_data); + if (rc) + CAM_ERR(CAM_FLASH, "cam_flash_ioctl failed"); + break; + } + default: + CAM_ERR(CAM_FLASH, "Invalid compat ioctl cmd_type:%d", + cmd); + rc = -EINVAL; + } + + if (!rc) { + if (copy_to_user((void __user *)arg, &cmd_data, + sizeof(cmd_data))) { + CAM_ERR(CAM_FLASH, + "Failed to copy to user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + rc = -EFAULT; + } + } + + return rc; +} +#endif + +static int cam_flash_platform_remove(struct platform_device *pdev) +{ + struct cam_flash_ctrl *fctrl; + + fctrl = platform_get_drvdata(pdev); + if (!fctrl) { + CAM_ERR(CAM_FLASH, "Flash device is NULL"); + return 0; + } + + CAM_INFO(CAM_FLASH, "Platform remove invoked"); + mutex_lock(&fctrl->flash_mutex); + cam_flash_shutdown(fctrl); + mutex_unlock(&fctrl->flash_mutex); + cam_unregister_subdev(&(fctrl->v4l2_dev_str)); + platform_set_drvdata(pdev, NULL); + v4l2_set_subdevdata(&fctrl->v4l2_dev_str.sd, NULL); + kfree(fctrl); + + return 0; +} + +static int32_t cam_flash_i2c_driver_remove(struct i2c_client *client) +{ + int32_t rc = 0; + struct cam_flash_ctrl *fctrl = i2c_get_clientdata(client); + /* Handle I2C Devices */ + if (!fctrl) { + CAM_ERR(CAM_FLASH, "Flash device is NULL"); + return -EINVAL; + } + + CAM_INFO(CAM_FLASH, "i2c driver remove invoked"); + /*Free Allocated Mem */ + kfree(fctrl->i2c_data.per_frame); + fctrl->i2c_data.per_frame = NULL; + kfree(fctrl); + return rc; +} + +static int cam_flash_subdev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct cam_flash_ctrl *fctrl = + v4l2_get_subdevdata(sd); + + if (!fctrl) { + CAM_ERR(CAM_FLASH, "Flash ctrl ptr is NULL"); + return -EINVAL; + } + + mutex_lock(&fctrl->flash_mutex); + cam_flash_shutdown(fctrl); + mutex_unlock(&fctrl->flash_mutex); + + return 0; +} + +static struct v4l2_subdev_core_ops cam_flash_subdev_core_ops = { + .ioctl = cam_flash_subdev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = cam_flash_subdev_do_ioctl +#endif +}; + +static struct v4l2_subdev_ops cam_flash_subdev_ops = { + .core = &cam_flash_subdev_core_ops, +}; + +static const struct v4l2_subdev_internal_ops cam_flash_internal_ops = { + .close = cam_flash_subdev_close, +}; + +static int cam_flash_init_subdev(struct cam_flash_ctrl *fctrl) +{ + int rc = 0; + + strlcpy(fctrl->device_name, CAM_FLASH_NAME, + sizeof(fctrl->device_name)); + fctrl->v4l2_dev_str.internal_ops = + &cam_flash_internal_ops; + fctrl->v4l2_dev_str.ops = &cam_flash_subdev_ops; + fctrl->v4l2_dev_str.name = CAMX_FLASH_DEV_NAME; + fctrl->v4l2_dev_str.sd_flags = + V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; + fctrl->v4l2_dev_str.ent_function = CAM_FLASH_DEVICE_TYPE; + fctrl->v4l2_dev_str.token = fctrl; + + rc = cam_register_subdev(&(fctrl->v4l2_dev_str)); + if (rc) + CAM_ERR(CAM_FLASH, "Fail to create subdev with %d", rc); + + return rc; +} + +static int32_t cam_flash_platform_probe(struct platform_device *pdev) +{ + int32_t rc = 0, i = 0; + struct cam_flash_ctrl *fctrl = NULL; + struct device_node *of_parent = NULL; + struct cam_hw_soc_info *soc_info = NULL; + + CAM_DBG(CAM_FLASH, "Enter"); + if (!pdev->dev.of_node) { + CAM_ERR(CAM_FLASH, "of_node NULL"); + return -EINVAL; + } + + fctrl = kzalloc(sizeof(struct cam_flash_ctrl), GFP_KERNEL); + if (!fctrl) + return -ENOMEM; + + fctrl->pdev = pdev; + fctrl->soc_info.pdev = pdev; + fctrl->soc_info.dev = &pdev->dev; + fctrl->soc_info.dev_name = pdev->name; + fctrl->of_node = pdev->dev.of_node; + + platform_set_drvdata(pdev, fctrl); + + rc = cam_flash_get_dt_data(fctrl, &fctrl->soc_info); + if (rc) { + CAM_ERR(CAM_FLASH, "cam_flash_get_dt_data failed with %d", rc); + kfree(fctrl); + return -EINVAL; + } + + if (of_find_property(pdev->dev.of_node, "cci-master", NULL)) { + /* Get CCI master */ + rc = of_property_read_u32(pdev->dev.of_node, "cci-master", + &fctrl->cci_i2c_master); + CAM_DBG(CAM_FLASH, "cci-master %d, rc %d", + fctrl->cci_i2c_master, rc); + if (rc < 0) { + /* Set default master 0 */ + fctrl->cci_i2c_master = MASTER_0; + rc = 0; + } + + fctrl->io_master_info.master_type = CCI_MASTER; + rc = cam_flash_init_default_params(fctrl); + if (rc) { + CAM_ERR(CAM_FLASH, + "failed: cam_flash_init_default_params rc %d", + rc); + return rc; + } + + of_parent = of_get_parent(pdev->dev.of_node); + if (of_property_read_u32(of_parent, "cell-index", + &fctrl->cci_num) < 0) + /* Set default master 0 */ + fctrl->cci_num = CCI_DEVICE_0; + + fctrl->io_master_info.cci_client->cci_device = fctrl->cci_num; + CAM_DBG(CAM_FLASH, "cci-index %d", fctrl->cci_num, rc); + + soc_info = &fctrl->soc_info; + if (!soc_info->gpio_data) { + CAM_DBG(CAM_FLASH, "No GPIO found"); + } else { + if (!soc_info->gpio_data->cam_gpio_common_tbl_size) { + CAM_ERR(CAM_FLASH, "Invalid gpio table size"); + rc = -EINVAL; + goto free_cci_resource; + } + + rc = cam_sensor_util_init_gpio_pin_tbl(soc_info, + &fctrl->power_info.gpio_num_info); + if ((rc < 0) || (!fctrl->power_info.gpio_num_info)) { + CAM_ERR(CAM_FLASH, "No/Error Flash GPIOs"); + rc = -EINVAL; + goto free_cci_resource; + } + } + + fctrl->i2c_data.per_frame = + kzalloc(sizeof(struct i2c_settings_array) * + MAX_PER_FRAME_ARRAY, GFP_KERNEL); + if (fctrl->i2c_data.per_frame == NULL) { + CAM_ERR(CAM_FLASH, "No Memory"); + rc = -ENOMEM; + goto free_cci_resource; + } + + INIT_LIST_HEAD(&(fctrl->i2c_data.init_settings.list_head)); + INIT_LIST_HEAD(&(fctrl->i2c_data.config_settings.list_head)); + INIT_LIST_HEAD(&(fctrl->i2c_data.streamoff_settings.list_head)); + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) + INIT_LIST_HEAD( + &(fctrl->i2c_data.per_frame[i].list_head)); + + fctrl->func_tbl.parser = cam_flash_i2c_pkt_parser; + fctrl->func_tbl.apply_setting = cam_flash_i2c_apply_setting; + fctrl->func_tbl.power_ops = cam_flash_i2c_power_ops; + fctrl->func_tbl.flush_req = cam_flash_i2c_flush_request; + } else { + /* PMIC Flash */ + fctrl->func_tbl.parser = cam_flash_pmic_pkt_parser; + fctrl->func_tbl.apply_setting = cam_flash_pmic_apply_setting; + fctrl->func_tbl.power_ops = cam_flash_pmic_power_ops; + fctrl->func_tbl.flush_req = cam_flash_pmic_flush_request; + } + + rc = cam_flash_init_subdev(fctrl); + if (rc) { + if (fctrl->io_master_info.cci_client != NULL) + goto free_cci_resource; + else + goto free_resource; + } + + fctrl->bridge_intf.device_hdl = -1; + fctrl->bridge_intf.link_hdl = -1; + fctrl->bridge_intf.ops.get_dev_info = cam_flash_publish_dev_info; + fctrl->bridge_intf.ops.link_setup = cam_flash_establish_link; + fctrl->bridge_intf.ops.apply_req = cam_flash_apply_request; + fctrl->bridge_intf.ops.flush_req = cam_flash_flush_request; + fctrl->last_flush_req = 0; + + mutex_init(&(fctrl->flash_mutex)); + + fctrl->flash_state = CAM_FLASH_STATE_INIT; + CAM_DBG(CAM_FLASH, "Probe success"); + return rc; + +free_cci_resource: + kfree(fctrl->io_master_info.cci_client); + fctrl->io_master_info.cci_client = NULL; +free_resource: + kfree(fctrl->i2c_data.per_frame); + kfree(fctrl->soc_info.soc_private); + cam_soc_util_release_platform_resource(&fctrl->soc_info); + fctrl->i2c_data.per_frame = NULL; + fctrl->soc_info.soc_private = NULL; + kfree(fctrl); + fctrl = NULL; + return rc; +} + +static int32_t cam_flash_i2c_driver_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int32_t rc = 0, i = 0; + struct cam_flash_ctrl *fctrl; + struct cam_hw_soc_info *soc_info = NULL; + + if (client == NULL) { + CAM_ERR(CAM_FLASH, "Invalid Args client: %pK", client); + return -EINVAL; + } + + if (id == NULL) { + CAM_DBG(CAM_FLASH, "device id is Null"); + } + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + CAM_ERR(CAM_FLASH, "%s :: i2c_check_functionality failed", + client->name); + return -EFAULT; + } + + /* Create sensor control structure */ + fctrl = kzalloc(sizeof(*fctrl), GFP_KERNEL); + if (!fctrl) { + CAM_ERR(CAM_FLASH, "Failed to allocate memory for fctrl"); + return -ENOMEM; + } + + i2c_set_clientdata(client, fctrl); + + fctrl->io_master_info.client = client; + fctrl->of_node = client->dev.of_node; + fctrl->soc_info.dev = &client->dev; + fctrl->soc_info.dev_name = client->name; + fctrl->io_master_info.master_type = I2C_MASTER; + + rc = cam_flash_init_default_params(fctrl); + if (rc) { + CAM_ERR(CAM_FLASH, + "failed: cam_flash_init_default_params rc %d", rc); + goto free_ctrl; + } + + rc = cam_flash_get_dt_data(fctrl, &fctrl->soc_info); + if (rc) { + CAM_ERR(CAM_FLASH, "failed: cam_sensor_parse_dt rc %d", rc); + goto free_ctrl; + } + + soc_info = &fctrl->soc_info; + if (!soc_info->gpio_data) { + CAM_DBG(CAM_FLASH, "No GPIO found"); + } else { + if (!soc_info->gpio_data->cam_gpio_common_tbl_size) { + CAM_ERR(CAM_FLASH, "Invalid gpio table size"); + rc = -EINVAL; + goto free_ctrl; + } + + rc = cam_sensor_util_init_gpio_pin_tbl(soc_info, + &fctrl->power_info.gpio_num_info); + if ((rc < 0) || (!fctrl->power_info.gpio_num_info)) { + CAM_ERR(CAM_FLASH, "No/Error Flash GPIOs"); + rc = -EINVAL; + goto free_ctrl; + } + } + + rc = cam_flash_init_subdev(fctrl); + if (rc) + goto free_ctrl; + + fctrl->i2c_data.per_frame = + kzalloc(sizeof(struct i2c_settings_array) * + MAX_PER_FRAME_ARRAY, GFP_KERNEL); + if (fctrl->i2c_data.per_frame == NULL) { + rc = -ENOMEM; + goto unreg_subdev; + } + + INIT_LIST_HEAD(&(fctrl->i2c_data.init_settings.list_head)); + INIT_LIST_HEAD(&(fctrl->i2c_data.config_settings.list_head)); + INIT_LIST_HEAD(&(fctrl->i2c_data.streamoff_settings.list_head)); + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) + INIT_LIST_HEAD(&(fctrl->i2c_data.per_frame[i].list_head)); + + fctrl->func_tbl.parser = cam_flash_i2c_pkt_parser; + fctrl->func_tbl.apply_setting = cam_flash_i2c_apply_setting; + fctrl->func_tbl.power_ops = cam_flash_i2c_power_ops; + fctrl->func_tbl.flush_req = cam_flash_i2c_flush_request; + + fctrl->bridge_intf.device_hdl = -1; + fctrl->bridge_intf.link_hdl = -1; + fctrl->bridge_intf.ops.get_dev_info = cam_flash_publish_dev_info; + fctrl->bridge_intf.ops.link_setup = cam_flash_establish_link; + fctrl->bridge_intf.ops.apply_req = cam_flash_apply_request; + fctrl->bridge_intf.ops.flush_req = cam_flash_flush_request; + fctrl->last_flush_req = 0; + + mutex_init(&(fctrl->flash_mutex)); + fctrl->flash_state = CAM_FLASH_STATE_INIT; + + return rc; + +unreg_subdev: + cam_unregister_subdev(&(fctrl->v4l2_dev_str)); +free_ctrl: + kfree(fctrl); + fctrl = NULL; + return rc; +} + +MODULE_DEVICE_TABLE(of, cam_flash_dt_match); + +static struct platform_driver cam_flash_platform_driver = { + .probe = cam_flash_platform_probe, + .remove = cam_flash_platform_remove, + .driver = { + .name = "CAM-FLASH-DRIVER", + .owner = THIS_MODULE, + .of_match_table = cam_flash_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static const struct i2c_device_id i2c_id[] = { + {FLASH_DRIVER_I2C, (kernel_ulong_t)NULL}, + { } +}; + +static struct i2c_driver cam_flash_i2c_driver = { + .id_table = i2c_id, + .probe = cam_flash_i2c_driver_probe, + .remove = cam_flash_i2c_driver_remove, + .driver = { + .name = FLASH_DRIVER_I2C, + .of_match_table = cam_flash_dt_match, + }, +}; + +static int32_t __init cam_flash_init_module(void) +{ + int32_t rc = 0; + + rc = platform_driver_register(&cam_flash_platform_driver); + if (rc < 0) + CAM_ERR(CAM_FLASH, "platform probe failed rc: %d", rc); + + rc = i2c_add_driver(&cam_flash_i2c_driver); + if (rc < 0) + CAM_ERR(CAM_FLASH, "i2c_add_driver failed rc: %d", rc); + + return rc; +} + +static void __exit cam_flash_exit_module(void) +{ + platform_driver_unregister(&cam_flash_platform_driver); + i2c_del_driver(&cam_flash_i2c_driver); +} + +module_init(cam_flash_init_module); +module_exit(cam_flash_exit_module); +MODULE_DESCRIPTION("CAM FLASH"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..28f2fa14e167f7c35b05cd32712b898ab79d9640 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h @@ -0,0 +1,236 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, 2021 The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_FLASH_DEV_H_ +#define _CAM_FLASH_DEV_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_req_mgr_util.h" +#include "cam_req_mgr_interface.h" +#include "cam_subdev.h" +#include "cam_mem_mgr.h" +#include "cam_sensor_cmn_header.h" +#include "cam_sensor_util.h" +#include "cam_soc_util.h" +#include "cam_debug_util.h" +#include "cam_sensor_io.h" +#include "cam_flash_core.h" +#include "cam_context.h" + +#define CAMX_FLASH_DEV_NAME "cam-flash-dev" + +#define CAM_FLASH_PIPELINE_DELAY 1 + +#define FLASH_DRIVER_I2C "i2c_flash" + +#define CAM_FLASH_PACKET_OPCODE_INIT 0 +#define CAM_FLASH_PACKET_OPCODE_SET_OPS 1 +#define CAM_FLASH_PACKET_OPCODE_NON_REALTIME_SET_OPS 2 +#define CAM_FLASH_PACKET_OPCODE_STREAM_OFF 3 + +struct cam_flash_ctrl; + +enum cam_flash_switch_trigger_ops { + LED_SWITCH_OFF = 0, + LED_SWITCH_ON, +}; + +enum cam_flash_state { + CAM_FLASH_STATE_INIT, + CAM_FLASH_STATE_ACQUIRE, + CAM_FLASH_STATE_CONFIG, + CAM_FLASH_STATE_START, +}; + +enum cam_flash_flush_type { + FLUSH_ALL = 0, + FLUSH_REQ, + FLUSH_MAX, +}; + +/** + * struct cam_flash_intf_params + * @device_hdl : Device Handle + * @session_hdl : Session Handle + * @link_hdl : Link Handle + * @ops : KMD operations + * @crm_cb : Callback API pointers + */ +struct cam_flash_intf_params { + int32_t device_hdl; + int32_t session_hdl; + int32_t link_hdl; + struct cam_req_mgr_kmd_ops ops; + struct cam_req_mgr_crm_cb *crm_cb; +}; + +/** + * struct cam_flash_common_attr + * @is_settings_valid : Notify the valid settings + * @request_id : Request id provided by umd + * @count : Number of led count + * @cmd_type : Command buffer type + */ +struct cam_flash_common_attr { + bool is_settings_valid; + uint64_t request_id; + uint32_t count; + uint8_t cmd_type; +}; + +/** + * struct flash_init_packet + * @cmn_attr : Provides common attributes + * @flash_type : Flash type(PMIC/I2C/GPIO) + */ +struct cam_flash_init_packet { + struct cam_flash_common_attr cmn_attr; + uint32_t flash_type; +}; + +/** + * struct flash_frame_setting + * @cmn_attr : Provides common attributes + * @num_iterations : Iterations used to perform RER + * @led_on_delay_ms : LED on time in milisec + * @led_off_delay_ms : LED off time in milisec + * @opcode : Command buffer opcode + * @led_current_ma[] : LED current array in miliamps + * + */ +struct cam_flash_frame_setting { + struct cam_flash_common_attr cmn_attr; + uint16_t num_iterations; + uint16_t led_on_delay_ms; + uint16_t led_off_delay_ms; + int8_t opcode; + uint32_t led_current_ma[CAM_FLASH_MAX_LED_TRIGGERS]; +}; + +/** + * struct cam_flash_private_soc + * @switch_trigger_name : Switch trigger name + * @flash_trigger_name : Flash trigger name array + * @flash_op_current : Flash operational current + * @flash_max_current : Max supported current for LED in flash mode + * @flash_max_duration : Max turn on duration for LED in Flash mode + * @torch_trigger_name : Torch trigger name array + * @torch_op_current : Torch operational current + * @torch_max_current : Max supported current for LED in torch mode + * @is_wled_flash : Detection between WLED/LED flash + * @flash_type : Flash type + */ + +struct cam_flash_private_soc { + const char *switch_trigger_name; + const char *flash_trigger_name[CAM_FLASH_MAX_LED_TRIGGERS]; + uint32_t flash_op_current[CAM_FLASH_MAX_LED_TRIGGERS]; + uint32_t flash_max_current[CAM_FLASH_MAX_LED_TRIGGERS]; + uint32_t flash_max_duration[CAM_FLASH_MAX_LED_TRIGGERS]; + const char *torch_trigger_name[CAM_FLASH_MAX_LED_TRIGGERS]; + uint32_t torch_op_current[CAM_FLASH_MAX_LED_TRIGGERS]; + uint32_t torch_max_current[CAM_FLASH_MAX_LED_TRIGGERS]; + bool is_wled_flash; + uint32_t flash_type; +}; + +struct cam_flash_func_tbl { + int (*parser)(struct cam_flash_ctrl *fctrl, void *arg); + int (*apply_setting)(struct cam_flash_ctrl *fctrl, uint64_t req_id); + int (*power_ops)(struct cam_flash_ctrl *fctrl, bool regulator_enable); + int (*flush_req)(struct cam_flash_ctrl *fctrl, + enum cam_flash_flush_type type, uint64_t req_id); +}; + +/** + * struct cam_flash_ctrl + * @device_name : Device name + * @soc_info : Soc related information + * @pdev : Platform device + * @per_frame[] : Per_frame setting array + * @nrt_info : NonRealTime settings + * @of_node : Of Node ptr + * @v4l2_dev_str : V4L2 device structure + * @bridge_intf : CRM interface + * @flash_init_setting : Init command buffer structure + * @switch_trigger : Switch trigger ptr + * @flash_num_sources : Number of flash sources + * @torch_num_source : Number of torch sources + * @flash_mutex : Mutex for flash operations + * @flash_state : Current flash state (LOW/OFF/ON/INIT) + * @flash_type : Flash types (PMIC/I2C/GPIO) + * @is_regulator_enable : Regulator disable/enable notifier + * @func_tbl : Function table for different HW + * (e.g. i2c/pmic/gpio) + * @flash_trigger : Flash trigger ptr + * @torch_trigger : Torch trigger ptr + * @cci_i2c_master : I2C structure + * @cci_device_num : cci parent cell index + * @io_master_info : Information about the communication master + * @i2c_data : I2C register settings + * @last_flush_req : last request to flush + * @streamoff_count : Count to hold the number of times stream off called + * @apply_streamoff : variable to store when to apply stream off + */ +struct cam_flash_ctrl { + char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH]; + struct cam_hw_soc_info soc_info; + struct platform_device *pdev; + struct cam_sensor_power_ctrl_t power_info; + struct cam_flash_frame_setting per_frame[MAX_PER_FRAME_ARRAY]; + struct cam_flash_frame_setting nrt_info; + struct device_node *of_node; + struct cam_subdev v4l2_dev_str; + struct cam_flash_intf_params bridge_intf; + struct cam_flash_init_packet flash_init_setting; + struct led_trigger *switch_trigger; + uint32_t flash_num_sources; + uint32_t torch_num_sources; + struct mutex flash_mutex; + enum cam_flash_state flash_state; + uint8_t flash_type; + bool is_regulator_enabled; + struct cam_flash_func_tbl func_tbl; + struct led_trigger *flash_trigger[CAM_FLASH_MAX_LED_TRIGGERS]; + struct led_trigger *torch_trigger[CAM_FLASH_MAX_LED_TRIGGERS]; +/* I2C related setting */ + enum cci_i2c_master_t cci_i2c_master; + enum cci_device_num cci_num; + struct camera_io_master io_master_info; + struct i2c_data_settings i2c_data; + uint32_t last_flush_req; + uint32_t streamoff_count; + int32_t apply_streamoff; +}; + +int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg); +int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg); +int cam_flash_pmic_apply_setting(struct cam_flash_ctrl *fctrl, uint64_t req_id); +int cam_flash_i2c_apply_setting(struct cam_flash_ctrl *fctrl, uint64_t req_id); +int cam_flash_off(struct cam_flash_ctrl *fctrl); +int cam_flash_pmic_power_ops(struct cam_flash_ctrl *fctrl, + bool regulator_enable); +int cam_flash_i2c_power_ops(struct cam_flash_ctrl *fctrl, + bool regulator_enable); +int cam_flash_i2c_flush_request(struct cam_flash_ctrl *fctrl, + enum cam_flash_flush_type type, uint64_t req_id); +int cam_flash_pmic_flush_request(struct cam_flash_ctrl *fctrl, + enum cam_flash_flush_type, uint64_t req_id); +void cam_flash_shutdown(struct cam_flash_ctrl *fctrl); +int cam_flash_release_dev(struct cam_flash_ctrl *fctrl); + +#endif /*_CAM_FLASH_DEV_H_*/ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..4b3ee2f62e73e8d39da7c511b2e972e046c8ab0a --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, 2020, 2021 The Linux Foundation. All rights reserved. + */ + +#include +#include +#include "cam_flash_soc.h" +#include "cam_res_mgr_api.h" +#include + +static int32_t cam_get_source_node_info( + struct device_node *of_node, + struct cam_flash_ctrl *fctrl, + struct cam_flash_private_soc *soc_private) +{ + int32_t rc = 0; + uint32_t count = 0, i = 0; + struct device_node *flash_src_node = NULL; + struct device_node *torch_src_node = NULL; + struct device_node *switch_src_node = NULL; + + soc_private->is_wled_flash = + of_property_read_bool(of_node, "wled-flash-support"); + + rc = of_property_read_u32(of_node, + "flash-type", &soc_private->flash_type); + if (rc) { + CAM_ERR(CAM_FLASH, "flash-type read failed rc=%d", rc); + soc_private->flash_type = CAM_FLASH_TYPE_PMIC; + } + + switch_src_node = of_parse_phandle(of_node, "switch-source", 0); + if (!switch_src_node) { + CAM_WARN(CAM_FLASH, "switch_src_node NULL"); + } else { + rc = of_property_read_string(switch_src_node, + "qcom,default-led-trigger", + &soc_private->switch_trigger_name); + if (rc) { + CAM_ERR(CAM_FLASH, + "default-led-trigger read failed rc=%d", rc); + } else { + CAM_DBG(CAM_FLASH, "switch trigger %s", + soc_private->switch_trigger_name); + cam_res_mgr_led_trigger_register( + soc_private->switch_trigger_name, + &fctrl->switch_trigger); + } + + of_node_put(switch_src_node); + } + + if (of_get_property(of_node, "flash-source", &count)) { + count /= sizeof(uint32_t); + + if (count > CAM_FLASH_MAX_LED_TRIGGERS) { + CAM_ERR(CAM_FLASH, "Invalid LED count: %d", count); + return -EINVAL; + } + + fctrl->flash_num_sources = count; + + for (i = 0; i < count; i++) { + flash_src_node = of_parse_phandle(of_node, + "flash-source", i); + if (!flash_src_node) { + CAM_WARN(CAM_FLASH, "flash_src_node NULL"); + continue; + } + + rc = of_property_read_string(flash_src_node, + "qcom,default-led-trigger", + &soc_private->flash_trigger_name[i]); + if (rc) { + CAM_WARN(CAM_FLASH, + "defalut-led-trigger read failed rc=%d", rc); + of_node_put(flash_src_node); + continue; + } + + CAM_DBG(CAM_FLASH, "Flash default trigger %s", + soc_private->flash_trigger_name[i]); + cam_res_mgr_led_trigger_register( + soc_private->flash_trigger_name[i], + &fctrl->flash_trigger[i]); + + if (soc_private->is_wled_flash) { + rc = wled_flash_led_prepare( + fctrl->flash_trigger[i], + QUERY_MAX_CURRENT, + &soc_private->flash_max_current[i]); + if (rc) { + CAM_ERR(CAM_FLASH, + "WLED FLASH max_current read fail: %d", + rc); + of_node_put(flash_src_node); + rc = 0; + continue; + } + } else { + rc = of_property_read_u32(flash_src_node, + "qcom,max-current", + &soc_private->flash_max_current[i]); + rc &= of_property_read_u32(flash_src_node, + "qcom,max-current-ma", + &soc_private->flash_max_current[i]); + if (rc < 0) { + CAM_WARN(CAM_FLASH, + "LED FLASH max-current read fail: %d", + rc); + of_node_put(flash_src_node); + continue; + } + } + + /* Read operational-current */ + rc = of_property_read_u32(flash_src_node, + "qcom,current-ma", + &soc_private->flash_op_current[i]); + if (rc) { + CAM_INFO(CAM_FLASH, "op-current: read failed"); + rc = 0; + } + + /* Read max-duration */ + rc = of_property_read_u32(flash_src_node, + "qcom,duration-ms", + &soc_private->flash_max_duration[i]); + if (rc) { + CAM_INFO(CAM_FLASH, + "max-duration prop unavailable: %d", + rc); + rc = 0; + } + of_node_put(flash_src_node); + + CAM_DBG(CAM_FLASH, "MainFlashMaxCurrent[%d]: %d", + i, soc_private->flash_max_current[i]); + } + } + + if (of_get_property(of_node, "torch-source", &count)) { + count /= sizeof(uint32_t); + if (count > CAM_FLASH_MAX_LED_TRIGGERS) { + CAM_ERR(CAM_FLASH, "Invalid LED count : %d", count); + return -EINVAL; + } + + fctrl->torch_num_sources = count; + + CAM_DBG(CAM_FLASH, "torch_num_sources = %d", + fctrl->torch_num_sources); + for (i = 0; i < count; i++) { + torch_src_node = of_parse_phandle(of_node, + "torch-source", i); + if (!torch_src_node) { + CAM_WARN(CAM_FLASH, "torch_src_node NULL"); + continue; + } + + rc = of_property_read_string(torch_src_node, + "qcom,default-led-trigger", + &soc_private->torch_trigger_name[i]); + if (rc < 0) { + CAM_WARN(CAM_FLASH, + "default-trigger read failed"); + of_node_put(torch_src_node); + continue; + } + + CAM_DBG(CAM_FLASH, "Torch default trigger %s", + soc_private->torch_trigger_name[i]); + cam_res_mgr_led_trigger_register( + soc_private->torch_trigger_name[i], + &fctrl->torch_trigger[i]); + + if (soc_private->is_wled_flash) { + rc = wled_flash_led_prepare( + fctrl->torch_trigger[i], + QUERY_MAX_CURRENT, + &soc_private->torch_max_current[i]); + if (rc) { + CAM_ERR(CAM_FLASH, + "WLED TORCH max_current read fail: %d", + rc); + of_node_put(torch_src_node); + continue; + } + } else { + rc = of_property_read_u32(torch_src_node, + "qcom,max-current", + &soc_private->torch_max_current[i]); + rc &= of_property_read_u32(torch_src_node, + "qcom,max-current-ma", + &soc_private->torch_max_current[i]); + if (rc < 0) { + CAM_WARN(CAM_FLASH, + "LED-TORCH max-current read failed: %d", + rc); + of_node_put(torch_src_node); + continue; + } + } + + /* Read operational-current */ + rc = of_property_read_u32(torch_src_node, + "qcom,current-ma", + &soc_private->torch_op_current[i]); + if (rc < 0) { + CAM_WARN(CAM_FLASH, + "op-current prop unavailable: %d", rc); + rc = 0; + } + + of_node_put(torch_src_node); + + CAM_DBG(CAM_FLASH, "TorchMaxCurrent[%d]: %d", + i, soc_private->torch_max_current[i]); + } + } + + return rc; +} + +int cam_flash_get_dt_data(struct cam_flash_ctrl *fctrl, + struct cam_hw_soc_info *soc_info) +{ + int32_t rc = 0; + struct device_node *of_node = NULL; + + if (!fctrl) { + CAM_ERR(CAM_FLASH, "NULL flash control structure"); + return -EINVAL; + } + + soc_info->soc_private = + kzalloc(sizeof(struct cam_flash_private_soc), GFP_KERNEL); + if (!soc_info->soc_private) { + rc = -ENOMEM; + goto release_soc_res; + } + + if (fctrl->of_node == NULL) { + CAM_ERR(CAM_FLASH, "device node is NULL"); + rc = -EINVAL; + goto free_soc_private; + } + + of_node = fctrl->of_node; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc) { + CAM_ERR(CAM_FLASH, "Get_dt_properties failed rc %d", rc); + goto free_soc_private; + } + + rc = cam_get_source_node_info(of_node, fctrl, soc_info->soc_private); + if (rc) { + CAM_ERR(CAM_FLASH, + "cam_flash_get_pmic_source_info failed rc %d", rc); + goto free_soc_private; + } + return rc; + +free_soc_private: + kfree(soc_info->soc_private); + soc_info->soc_private = NULL; +release_soc_res: + cam_soc_util_release_platform_resource(soc_info); + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_soc.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..cfe7c3464f649f62b237911ec50de993101487d8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/cam_flash_soc.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_FLASH_SOC_H_ +#define _CAM_FLASH_SOC_H_ + +#include "cam_flash_dev.h" + +int cam_flash_get_dt_data(struct cam_flash_ctrl *fctrl, + struct cam_hw_soc_info *soc_info); + +#endif /*_CAM_FLASH_SOC_H_*/ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..0e32262e9059d00ad2bd6334e4a51b1e4eeaaf8b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core/ + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_ois_dev.o cam_ois_core.o cam_ois_soc.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_core.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_core.c new file mode 100644 index 0000000000000000000000000000000000000000..16c93f74624b11bdee403da9ca9c9ff0096351bb --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_core.c @@ -0,0 +1,922 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include "cam_ois_core.h" +#include "cam_ois_soc.h" +#include "cam_sensor_util.h" +#include "cam_debug_util.h" +#include "cam_res_mgr_api.h" +#include "cam_common_util.h" +#include "cam_packet_util.h" + +int32_t cam_ois_construct_default_power_setting( + struct cam_sensor_power_ctrl_t *power_info) +{ + int rc = 0; + + power_info->power_setting_size = 1; + power_info->power_setting = + kzalloc(sizeof(struct cam_sensor_power_setting), + GFP_KERNEL); + if (!power_info->power_setting) + return -ENOMEM; + + power_info->power_setting[0].seq_type = SENSOR_VAF; + power_info->power_setting[0].seq_val = CAM_VAF; + power_info->power_setting[0].config_val = 1; + power_info->power_setting[0].delay = 2; + + power_info->power_down_setting_size = 1; + power_info->power_down_setting = + kzalloc(sizeof(struct cam_sensor_power_setting), + GFP_KERNEL); + if (!power_info->power_down_setting) { + rc = -ENOMEM; + goto free_power_settings; + } + + power_info->power_down_setting[0].seq_type = SENSOR_VAF; + power_info->power_down_setting[0].seq_val = CAM_VAF; + power_info->power_down_setting[0].config_val = 0; + + return rc; + +free_power_settings: + kfree(power_info->power_setting); + power_info->power_setting = NULL; + power_info->power_setting_size = 0; + return rc; +} + + +/** + * cam_ois_get_dev_handle - get device handle + * @o_ctrl: ctrl structure + * @arg: Camera control command argument + * + * Returns success or failure + */ +static int cam_ois_get_dev_handle(struct cam_ois_ctrl_t *o_ctrl, + void *arg) +{ + struct cam_sensor_acquire_dev ois_acq_dev; + struct cam_create_dev_hdl bridge_params; + struct cam_control *cmd = (struct cam_control *)arg; + + if (o_ctrl->bridge_intf.device_hdl != -1) { + CAM_ERR(CAM_OIS, "Device is already acquired"); + return -EFAULT; + } + if (copy_from_user(&ois_acq_dev, u64_to_user_ptr(cmd->handle), + sizeof(ois_acq_dev))) + return -EFAULT; + + bridge_params.session_hdl = ois_acq_dev.session_handle; + bridge_params.ops = &o_ctrl->bridge_intf.ops; + bridge_params.v4l2_sub_dev_flag = 0; + bridge_params.media_entity_flag = 0; + bridge_params.priv = o_ctrl; + bridge_params.dev_id = CAM_OIS; + + ois_acq_dev.device_handle = + cam_create_device_hdl(&bridge_params); + if (ois_acq_dev.device_handle <= 0) { + CAM_ERR(CAM_OIS, "Can not create device handle"); + return -EFAULT; + } + o_ctrl->bridge_intf.device_hdl = ois_acq_dev.device_handle; + o_ctrl->bridge_intf.session_hdl = ois_acq_dev.session_handle; + + CAM_DBG(CAM_OIS, "Device Handle: %d", ois_acq_dev.device_handle); + if (copy_to_user(u64_to_user_ptr(cmd->handle), &ois_acq_dev, + sizeof(struct cam_sensor_acquire_dev))) { + CAM_ERR(CAM_OIS, "ACQUIRE_DEV: copy to user failed"); + return -EFAULT; + } + return 0; +} + +static int cam_ois_power_up(struct cam_ois_ctrl_t *o_ctrl) +{ + int rc = 0; + struct cam_hw_soc_info *soc_info = + &o_ctrl->soc_info; + struct cam_ois_soc_private *soc_private; + struct cam_sensor_power_ctrl_t *power_info; + + soc_private = + (struct cam_ois_soc_private *)o_ctrl->soc_info.soc_private; + power_info = &soc_private->power_info; + + if ((power_info->power_setting == NULL) && + (power_info->power_down_setting == NULL)) { + CAM_INFO(CAM_OIS, + "Using default power settings"); + rc = cam_ois_construct_default_power_setting(power_info); + if (rc < 0) { + CAM_ERR(CAM_OIS, + "Construct default ois power setting failed."); + return rc; + } + } + + /* Parse and fill vreg params for power up settings */ + rc = msm_camera_fill_vreg_params( + soc_info, + power_info->power_setting, + power_info->power_setting_size); + if (rc) { + CAM_ERR(CAM_OIS, + "failed to fill vreg params for power up rc:%d", rc); + return rc; + } + + /* Parse and fill vreg params for power down settings*/ + rc = msm_camera_fill_vreg_params( + soc_info, + power_info->power_down_setting, + power_info->power_down_setting_size); + if (rc) { + CAM_ERR(CAM_OIS, + "failed to fill vreg params for power down rc:%d", rc); + return rc; + } + + power_info->dev = soc_info->dev; + + rc = cam_sensor_core_power_up(power_info, soc_info); + if (rc) { + CAM_ERR(CAM_OIS, "failed in ois power up rc %d", rc); + return rc; + } + + rc = camera_io_init(&o_ctrl->io_master_info); + if (rc) + CAM_ERR(CAM_OIS, "cci_init failed: rc: %d", rc); + + return rc; +} + +/** + * cam_ois_power_down - power down OIS device + * @o_ctrl: ctrl structure + * + * Returns success or failure + */ +static int cam_ois_power_down(struct cam_ois_ctrl_t *o_ctrl) +{ + int32_t rc = 0; + struct cam_sensor_power_ctrl_t *power_info; + struct cam_hw_soc_info *soc_info = + &o_ctrl->soc_info; + struct cam_ois_soc_private *soc_private; + + if (!o_ctrl) { + CAM_ERR(CAM_OIS, "failed: o_ctrl %pK", o_ctrl); + return -EINVAL; + } + + soc_private = + (struct cam_ois_soc_private *)o_ctrl->soc_info.soc_private; + power_info = &soc_private->power_info; + soc_info = &o_ctrl->soc_info; + + if (!power_info) { + CAM_ERR(CAM_OIS, "failed: power_info %pK", power_info); + return -EINVAL; + } + + rc = cam_sensor_util_power_down(power_info, soc_info); + if (rc) { + CAM_ERR(CAM_OIS, "power down the core is failed:%d", rc); + return rc; + } + + camera_io_release(&o_ctrl->io_master_info); + + return rc; +} + +static int cam_ois_apply_settings(struct cam_ois_ctrl_t *o_ctrl, + struct i2c_settings_array *i2c_set) +{ + struct i2c_settings_list *i2c_list; + int32_t rc = 0; + uint32_t i, size; + + if (o_ctrl == NULL || i2c_set == NULL) { + CAM_ERR(CAM_OIS, "Invalid Args"); + return -EINVAL; + } + + if (i2c_set->is_settings_valid != 1) { + CAM_ERR(CAM_OIS, " Invalid settings"); + return -EINVAL; + } + + list_for_each_entry(i2c_list, + &(i2c_set->list_head), list) { + if (i2c_list->op_code == CAM_SENSOR_I2C_WRITE_RANDOM) { + rc = camera_io_dev_write(&(o_ctrl->io_master_info), + &(i2c_list->i2c_settings)); + if (rc < 0) { + CAM_ERR(CAM_OIS, + "Failed in Applying i2c wrt settings"); + return rc; + } + } else if (i2c_list->op_code == CAM_SENSOR_I2C_POLL) { + size = i2c_list->i2c_settings.size; + for (i = 0; i < size; i++) { + rc = camera_io_dev_poll( + &(o_ctrl->io_master_info), + i2c_list->i2c_settings.reg_setting[i].reg_addr, + i2c_list->i2c_settings.reg_setting[i].reg_data, + i2c_list->i2c_settings.reg_setting[i].data_mask, + i2c_list->i2c_settings.addr_type, + i2c_list->i2c_settings.data_type, + i2c_list->i2c_settings.reg_setting[i].delay); + if (rc < 0) { + CAM_ERR(CAM_OIS, + "i2c poll apply setting Fail"); + return rc; + } + } + } + } + + return rc; +} + +static int cam_ois_slaveInfo_pkt_parser(struct cam_ois_ctrl_t *o_ctrl, + uint32_t *cmd_buf, size_t len) +{ + int32_t rc = 0; + struct cam_cmd_ois_info *ois_info; + + if (!o_ctrl || !cmd_buf || len < sizeof(struct cam_cmd_ois_info)) { + CAM_ERR(CAM_OIS, "Invalid Args"); + return -EINVAL; + } + + ois_info = (struct cam_cmd_ois_info *)cmd_buf; + if (o_ctrl->io_master_info.master_type == CCI_MASTER) { + o_ctrl->io_master_info.cci_client->i2c_freq_mode = + ois_info->i2c_freq_mode; + o_ctrl->io_master_info.cci_client->sid = + ois_info->slave_addr >> 1; + o_ctrl->ois_fw_flag = ois_info->ois_fw_flag; + o_ctrl->is_ois_calib = ois_info->is_ois_calib; + memcpy(o_ctrl->ois_name, ois_info->ois_name, OIS_NAME_LEN); + o_ctrl->ois_name[OIS_NAME_LEN - 1] = '\0'; + o_ctrl->io_master_info.cci_client->retries = 3; + o_ctrl->io_master_info.cci_client->id_map = 0; + memcpy(&(o_ctrl->opcode), &(ois_info->opcode), + sizeof(struct cam_ois_opcode)); + CAM_DBG(CAM_OIS, "Slave addr: 0x%x Freq Mode: %d", + ois_info->slave_addr, ois_info->i2c_freq_mode); + } else if (o_ctrl->io_master_info.master_type == I2C_MASTER) { + o_ctrl->io_master_info.client->addr = ois_info->slave_addr; + CAM_DBG(CAM_OIS, "Slave addr: 0x%x", ois_info->slave_addr); + } else { + CAM_ERR(CAM_OIS, "Invalid Master type : %d", + o_ctrl->io_master_info.master_type); + rc = -EINVAL; + } + + return rc; +} + +static int cam_ois_fw_download(struct cam_ois_ctrl_t *o_ctrl) +{ + uint16_t total_bytes = 0; + uint8_t *ptr = NULL; + int32_t rc = 0, cnt; + uint32_t fw_size; + const struct firmware *fw = NULL; + const char *fw_name_prog = NULL; + const char *fw_name_coeff = NULL; + char name_prog[32] = {0}; + char name_coeff[32] = {0}; + struct device *dev = &(o_ctrl->pdev->dev); + struct cam_sensor_i2c_reg_setting i2c_reg_setting; + struct page *page = NULL; + + if (!o_ctrl) { + CAM_ERR(CAM_OIS, "Invalid Args"); + return -EINVAL; + } + + snprintf(name_coeff, 32, "%s.coeff", o_ctrl->ois_name); + + snprintf(name_prog, 32, "%s.prog", o_ctrl->ois_name); + + /* cast pointer as const pointer*/ + fw_name_prog = name_prog; + fw_name_coeff = name_coeff; + + /* Load FW */ + rc = request_firmware(&fw, fw_name_prog, dev); + if (rc) { + CAM_ERR(CAM_OIS, "Failed to locate %s", fw_name_prog); + return rc; + } + + total_bytes = fw->size; + i2c_reg_setting.addr_type = CAMERA_SENSOR_I2C_TYPE_BYTE; + i2c_reg_setting.data_type = CAMERA_SENSOR_I2C_TYPE_BYTE; + i2c_reg_setting.size = total_bytes; + i2c_reg_setting.delay = 0; + fw_size = PAGE_ALIGN(sizeof(struct cam_sensor_i2c_reg_array) * + total_bytes) >> PAGE_SHIFT; + page = cma_alloc(dev_get_cma_area((o_ctrl->soc_info.dev)), + fw_size, 0, GFP_KERNEL); + if (!page) { + CAM_ERR(CAM_OIS, "Failed in allocating i2c_array"); + release_firmware(fw); + return -ENOMEM; + } + + i2c_reg_setting.reg_setting = (struct cam_sensor_i2c_reg_array *) ( + page_address(page)); + + for (cnt = 0, ptr = (uint8_t *)fw->data; cnt < total_bytes; + cnt++, ptr++) { + i2c_reg_setting.reg_setting[cnt].reg_addr = + o_ctrl->opcode.prog; + i2c_reg_setting.reg_setting[cnt].reg_data = *ptr; + i2c_reg_setting.reg_setting[cnt].delay = 0; + i2c_reg_setting.reg_setting[cnt].data_mask = 0; + } + + rc = camera_io_dev_write_continuous(&(o_ctrl->io_master_info), + &i2c_reg_setting, 1); + if (rc < 0) { + CAM_ERR(CAM_OIS, "OIS FW download failed %d", rc); + goto release_firmware; + } + cma_release(dev_get_cma_area((o_ctrl->soc_info.dev)), + page, fw_size); + page = NULL; + fw_size = 0; + release_firmware(fw); + + rc = request_firmware(&fw, fw_name_coeff, dev); + if (rc) { + CAM_ERR(CAM_OIS, "Failed to locate %s", fw_name_coeff); + return rc; + } + + total_bytes = fw->size; + i2c_reg_setting.addr_type = CAMERA_SENSOR_I2C_TYPE_BYTE; + i2c_reg_setting.data_type = CAMERA_SENSOR_I2C_TYPE_BYTE; + i2c_reg_setting.size = total_bytes; + i2c_reg_setting.delay = 0; + fw_size = PAGE_ALIGN(sizeof(struct cam_sensor_i2c_reg_array) * + total_bytes) >> PAGE_SHIFT; + page = cma_alloc(dev_get_cma_area((o_ctrl->soc_info.dev)), + fw_size, 0, GFP_KERNEL); + if (!page) { + CAM_ERR(CAM_OIS, "Failed in allocating i2c_array"); + release_firmware(fw); + return -ENOMEM; + } + + i2c_reg_setting.reg_setting = (struct cam_sensor_i2c_reg_array *) ( + page_address(page)); + + for (cnt = 0, ptr = (uint8_t *)fw->data; cnt < total_bytes; + cnt++, ptr++) { + i2c_reg_setting.reg_setting[cnt].reg_addr = + o_ctrl->opcode.coeff; + i2c_reg_setting.reg_setting[cnt].reg_data = *ptr; + i2c_reg_setting.reg_setting[cnt].delay = 0; + i2c_reg_setting.reg_setting[cnt].data_mask = 0; + } + + rc = camera_io_dev_write_continuous(&(o_ctrl->io_master_info), + &i2c_reg_setting, 1); + if (rc < 0) + CAM_ERR(CAM_OIS, "OIS FW download failed %d", rc); + +release_firmware: + cma_release(dev_get_cma_area((o_ctrl->soc_info.dev)), + page, fw_size); + release_firmware(fw); + + return rc; +} + +/** + * cam_ois_pkt_parse - Parse csl packet + * @o_ctrl: ctrl structure + * @arg: Camera control command argument + * + * Returns success or failure + */ +static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) +{ + int32_t rc = 0; + int32_t i = 0; + uint32_t total_cmd_buf_in_bytes = 0; + struct common_header *cmm_hdr = NULL; + uintptr_t generic_ptr; + struct cam_control *ioctl_ctrl = NULL; + struct cam_config_dev_cmd dev_config; + struct i2c_settings_array *i2c_reg_settings = NULL; + struct cam_cmd_buf_desc *cmd_desc = NULL; + uintptr_t generic_pkt_addr; + size_t pkt_len; + size_t remain_len = 0; + struct cam_packet *csl_packet = NULL; + size_t len_of_buff = 0; + uint32_t *offset = NULL, *cmd_buf; + struct cam_ois_soc_private *soc_private = + (struct cam_ois_soc_private *)o_ctrl->soc_info.soc_private; + struct cam_sensor_power_ctrl_t *power_info = &soc_private->power_info; + + ioctl_ctrl = (struct cam_control *)arg; + if (copy_from_user(&dev_config, + u64_to_user_ptr(ioctl_ctrl->handle), + sizeof(dev_config))) + return -EFAULT; + rc = cam_mem_get_cpu_buf(dev_config.packet_handle, + &generic_pkt_addr, &pkt_len); + if (rc) { + CAM_ERR(CAM_OIS, + "error in converting command Handle Error: %d", rc); + return rc; + } + + remain_len = pkt_len; + if ((sizeof(struct cam_packet) > pkt_len) || + ((size_t)dev_config.offset >= pkt_len - + sizeof(struct cam_packet))) { + CAM_ERR(CAM_OIS, + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), pkt_len); + return -EINVAL; + } + + remain_len -= (size_t)dev_config.offset; + csl_packet = (struct cam_packet *) + (generic_pkt_addr + (uint32_t)dev_config.offset); + + if (cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_OIS, "Invalid packet params"); + return -EINVAL; + } + + + switch (csl_packet->header.op_code & 0xFFFFFF) { + case CAM_OIS_PACKET_OPCODE_INIT: + offset = (uint32_t *)&csl_packet->payload; + offset += (csl_packet->cmd_buf_offset / sizeof(uint32_t)); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + + /* Loop through multiple command buffers */ + for (i = 0; i < csl_packet->num_cmd_buf; i++) { + total_cmd_buf_in_bytes = cmd_desc[i].length; + if (!total_cmd_buf_in_bytes) + continue; + + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, + &generic_ptr, &len_of_buff); + if (rc < 0) { + CAM_ERR(CAM_OIS, "Failed to get cpu buf : 0x%x", + cmd_desc[i].mem_handle); + return rc; + } + cmd_buf = (uint32_t *)generic_ptr; + if (!cmd_buf) { + CAM_ERR(CAM_OIS, "invalid cmd buf"); + return -EINVAL; + } + + if ((len_of_buff < sizeof(struct common_header)) || + (cmd_desc[i].offset > (len_of_buff - + sizeof(struct common_header)))) { + CAM_ERR(CAM_OIS, + "Invalid length for sensor cmd"); + return -EINVAL; + } + remain_len = len_of_buff - cmd_desc[i].offset; + cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); + cmm_hdr = (struct common_header *)cmd_buf; + + switch (cmm_hdr->cmd_type) { + case CAMERA_SENSOR_CMD_TYPE_I2C_INFO: + rc = cam_ois_slaveInfo_pkt_parser( + o_ctrl, cmd_buf, remain_len); + if (rc < 0) { + CAM_ERR(CAM_OIS, + "Failed in parsing slave info"); + return rc; + } + break; + case CAMERA_SENSOR_CMD_TYPE_PWR_UP: + case CAMERA_SENSOR_CMD_TYPE_PWR_DOWN: + CAM_DBG(CAM_OIS, + "Received power settings buffer"); + rc = cam_sensor_update_power_settings( + cmd_buf, + total_cmd_buf_in_bytes, + power_info, remain_len); + if (rc) { + CAM_ERR(CAM_OIS, + "Failed: parse power settings"); + return rc; + } + break; + default: + if (o_ctrl->i2c_init_data.is_settings_valid == 0) { + CAM_DBG(CAM_OIS, + "Received init settings"); + i2c_reg_settings = + &(o_ctrl->i2c_init_data); + i2c_reg_settings->is_settings_valid = 1; + i2c_reg_settings->request_id = 0; + rc = cam_sensor_i2c_command_parser( + &o_ctrl->io_master_info, + i2c_reg_settings, + &cmd_desc[i], 1, NULL); + if (rc < 0) { + CAM_ERR(CAM_OIS, + "init parsing failed: %d", rc); + return rc; + } + } else if ((o_ctrl->is_ois_calib != 0) && + (o_ctrl->i2c_calib_data.is_settings_valid == + 0)) { + CAM_DBG(CAM_OIS, + "Received calib settings"); + i2c_reg_settings = &(o_ctrl->i2c_calib_data); + i2c_reg_settings->is_settings_valid = 1; + i2c_reg_settings->request_id = 0; + rc = cam_sensor_i2c_command_parser( + &o_ctrl->io_master_info, + i2c_reg_settings, + &cmd_desc[i], 1, NULL); + if (rc < 0) { + CAM_ERR(CAM_OIS, + "Calib parsing failed: %d", rc); + return rc; + } + } + break; + } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + } + + if (o_ctrl->cam_ois_state != CAM_OIS_CONFIG) { + rc = cam_ois_power_up(o_ctrl); + if (rc) { + CAM_ERR(CAM_OIS, " OIS Power up failed"); + return rc; + } + o_ctrl->cam_ois_state = CAM_OIS_CONFIG; + } + + if (o_ctrl->ois_fw_flag) { + rc = cam_ois_fw_download(o_ctrl); + if (rc) { + CAM_ERR(CAM_OIS, "Failed OIS FW Download"); + goto pwr_dwn; + } + } + + rc = cam_ois_apply_settings(o_ctrl, &o_ctrl->i2c_init_data); + if ((rc == -EAGAIN) && + (o_ctrl->io_master_info.master_type == CCI_MASTER)) { + CAM_WARN(CAM_OIS, + "CCI HW is restting: Reapplying INIT settings"); + usleep_range(1000, 1010); + rc = cam_ois_apply_settings(o_ctrl, + &o_ctrl->i2c_init_data); + } + if (rc < 0) { + CAM_ERR(CAM_OIS, + "Cannot apply Init settings: rc = %d", + rc); + goto pwr_dwn; + } + + if (o_ctrl->is_ois_calib) { + rc = cam_ois_apply_settings(o_ctrl, + &o_ctrl->i2c_calib_data); + if (rc) { + CAM_ERR(CAM_OIS, "Cannot apply calib data"); + goto pwr_dwn; + } + } + + rc = delete_request(&o_ctrl->i2c_init_data); + if (rc < 0) { + CAM_WARN(CAM_OIS, + "Fail deleting Init data: rc: %d", rc); + rc = 0; + } + rc = delete_request(&o_ctrl->i2c_calib_data); + if (rc < 0) { + CAM_WARN(CAM_OIS, + "Fail deleting Calibration data: rc: %d", rc); + rc = 0; + } + break; + case CAM_OIS_PACKET_OPCODE_OIS_CONTROL: + if (o_ctrl->cam_ois_state < CAM_OIS_CONFIG) { + rc = -EINVAL; + CAM_WARN(CAM_OIS, + "Not in right state to control OIS: %d", + o_ctrl->cam_ois_state); + return rc; + } + offset = (uint32_t *)&csl_packet->payload; + offset += (csl_packet->cmd_buf_offset / sizeof(uint32_t)); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + i2c_reg_settings = &(o_ctrl->i2c_mode_data); + i2c_reg_settings->is_settings_valid = 1; + i2c_reg_settings->request_id = 0; + rc = cam_sensor_i2c_command_parser(&o_ctrl->io_master_info, + i2c_reg_settings, + cmd_desc, 1, NULL); + if (rc < 0) { + CAM_ERR(CAM_OIS, "OIS pkt parsing failed: %d", rc); + return rc; + } + + rc = cam_ois_apply_settings(o_ctrl, i2c_reg_settings); + if (rc < 0) { + CAM_ERR(CAM_OIS, "Cannot apply mode settings"); + return rc; + } + + rc = delete_request(i2c_reg_settings); + if (rc < 0) { + CAM_ERR(CAM_OIS, + "Fail deleting Mode data: rc: %d", rc); + return rc; + } + break; + case CAM_OIS_PACKET_OPCODE_READ: { + struct cam_buf_io_cfg *io_cfg; + struct i2c_settings_array i2c_read_settings; + + if (o_ctrl->cam_ois_state < CAM_OIS_CONFIG) { + rc = -EINVAL; + CAM_WARN(CAM_OIS, + "Not in right state to read OIS: %d", + o_ctrl->cam_ois_state); + return rc; + } + CAM_DBG(CAM_OIS, "number of I/O configs: %d:", + csl_packet->num_io_configs); + if (csl_packet->num_io_configs == 0) { + CAM_ERR(CAM_OIS, "No I/O configs to process"); + rc = -EINVAL; + return rc; + } + + INIT_LIST_HEAD(&(i2c_read_settings.list_head)); + + io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) + &csl_packet->payload + + csl_packet->io_configs_offset); + + if (io_cfg == NULL) { + CAM_ERR(CAM_OIS, "I/O config is invalid(NULL)"); + rc = -EINVAL; + return rc; + } + + offset = (uint32_t *)&csl_packet->payload; + offset += (csl_packet->cmd_buf_offset / sizeof(uint32_t)); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + i2c_read_settings.is_settings_valid = 1; + i2c_read_settings.request_id = 0; + rc = cam_sensor_i2c_command_parser(&o_ctrl->io_master_info, + &i2c_read_settings, + cmd_desc, 1, io_cfg); + if (rc < 0) { + CAM_ERR(CAM_OIS, "OIS read pkt parsing failed: %d", rc); + return rc; + } + + rc = cam_sensor_i2c_read_data( + &i2c_read_settings, + &o_ctrl->io_master_info); + if (rc < 0) { + CAM_ERR(CAM_OIS, "cannot read data rc: %d", rc); + delete_request(&i2c_read_settings); + return rc; + } + + rc = delete_request(&i2c_read_settings); + if (rc < 0) { + CAM_ERR(CAM_OIS, + "Failed in deleting the read settings"); + return rc; + } + break; + } + default: + CAM_ERR(CAM_OIS, "Invalid Opcode: %d", + (csl_packet->header.op_code & 0xFFFFFF)); + return -EINVAL; + } + cam_mem_put_cpu_buf(dev_config.packet_handle); + + if (!rc) + return rc; +pwr_dwn: + cam_ois_power_down(o_ctrl); + return rc; +} + +void cam_ois_shutdown(struct cam_ois_ctrl_t *o_ctrl) +{ + int rc = 0; + struct cam_ois_soc_private *soc_private = + (struct cam_ois_soc_private *)o_ctrl->soc_info.soc_private; + struct cam_sensor_power_ctrl_t *power_info = &soc_private->power_info; + + if (o_ctrl->cam_ois_state == CAM_OIS_INIT) + return; + + if (o_ctrl->cam_ois_state >= CAM_OIS_CONFIG) { + rc = cam_ois_power_down(o_ctrl); + if (rc < 0) + CAM_ERR(CAM_OIS, "OIS Power down failed"); + o_ctrl->cam_ois_state = CAM_OIS_ACQUIRE; + } + + if (o_ctrl->cam_ois_state >= CAM_OIS_ACQUIRE) { + rc = cam_destroy_device_hdl(o_ctrl->bridge_intf.device_hdl); + if (rc < 0) + CAM_ERR(CAM_OIS, "destroying the device hdl"); + o_ctrl->bridge_intf.device_hdl = -1; + o_ctrl->bridge_intf.link_hdl = -1; + o_ctrl->bridge_intf.session_hdl = -1; + } + + if (o_ctrl->i2c_mode_data.is_settings_valid == 1) + delete_request(&o_ctrl->i2c_mode_data); + + if (o_ctrl->i2c_calib_data.is_settings_valid == 1) + delete_request(&o_ctrl->i2c_calib_data); + + if (o_ctrl->i2c_init_data.is_settings_valid == 1) + delete_request(&o_ctrl->i2c_init_data); + + kfree(power_info->power_setting); + kfree(power_info->power_down_setting); + power_info->power_setting = NULL; + power_info->power_down_setting = NULL; + power_info->power_down_setting_size = 0; + power_info->power_setting_size = 0; + + o_ctrl->cam_ois_state = CAM_OIS_INIT; +} + +/** + * cam_ois_driver_cmd - Handle ois cmds + * @e_ctrl: ctrl structure + * @arg: Camera control command argument + * + * Returns success or failure + */ +int cam_ois_driver_cmd(struct cam_ois_ctrl_t *o_ctrl, void *arg) +{ + int rc = 0; + struct cam_ois_query_cap_t ois_cap = {0}; + struct cam_control *cmd = (struct cam_control *)arg; + struct cam_ois_soc_private *soc_private = NULL; + struct cam_sensor_power_ctrl_t *power_info = NULL; + + if (!o_ctrl || !cmd) { + CAM_ERR(CAM_OIS, "Invalid arguments"); + return -EINVAL; + } + + if (cmd->handle_type != CAM_HANDLE_USER_POINTER) { + CAM_ERR(CAM_OIS, "Invalid handle type: %d", + cmd->handle_type); + return -EINVAL; + } + + soc_private = + (struct cam_ois_soc_private *)o_ctrl->soc_info.soc_private; + power_info = &soc_private->power_info; + + mutex_lock(&(o_ctrl->ois_mutex)); + switch (cmd->op_code) { + case CAM_QUERY_CAP: + ois_cap.slot_info = o_ctrl->soc_info.index; + + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &ois_cap, + sizeof(struct cam_ois_query_cap_t))) { + CAM_ERR(CAM_OIS, "Failed Copy to User"); + rc = -EFAULT; + goto release_mutex; + } + CAM_DBG(CAM_OIS, "ois_cap: ID: %d", ois_cap.slot_info); + break; + case CAM_ACQUIRE_DEV: + rc = cam_ois_get_dev_handle(o_ctrl, arg); + if (rc) { + CAM_ERR(CAM_OIS, "Failed to acquire dev"); + goto release_mutex; + } + + o_ctrl->cam_ois_state = CAM_OIS_ACQUIRE; + break; + case CAM_START_DEV: + if (o_ctrl->cam_ois_state != CAM_OIS_CONFIG) { + rc = -EINVAL; + CAM_WARN(CAM_OIS, + "Not in right state for start : %d", + o_ctrl->cam_ois_state); + goto release_mutex; + } + o_ctrl->cam_ois_state = CAM_OIS_START; + break; + case CAM_CONFIG_DEV: + rc = cam_ois_pkt_parse(o_ctrl, arg); + if (rc) { + CAM_ERR(CAM_OIS, "Failed in ois pkt Parsing"); + goto release_mutex; + } + break; + case CAM_RELEASE_DEV: + if (o_ctrl->cam_ois_state == CAM_OIS_START) { + rc = -EINVAL; + CAM_WARN(CAM_OIS, + "Cant release ois: in start state"); + goto release_mutex; + } + + if (o_ctrl->cam_ois_state == CAM_OIS_CONFIG) { + rc = cam_ois_power_down(o_ctrl); + if (rc < 0) { + CAM_ERR(CAM_OIS, "OIS Power down failed"); + goto release_mutex; + } + } + + if (o_ctrl->bridge_intf.device_hdl == -1) { + CAM_ERR(CAM_OIS, "link hdl: %d device hdl: %d", + o_ctrl->bridge_intf.device_hdl, + o_ctrl->bridge_intf.link_hdl); + rc = -EINVAL; + goto release_mutex; + } + rc = cam_destroy_device_hdl(o_ctrl->bridge_intf.device_hdl); + if (rc < 0) + CAM_ERR(CAM_OIS, "destroying the device hdl"); + o_ctrl->bridge_intf.device_hdl = -1; + o_ctrl->bridge_intf.link_hdl = -1; + o_ctrl->bridge_intf.session_hdl = -1; + o_ctrl->cam_ois_state = CAM_OIS_INIT; + + kfree(power_info->power_setting); + kfree(power_info->power_down_setting); + power_info->power_setting = NULL; + power_info->power_down_setting = NULL; + power_info->power_down_setting_size = 0; + power_info->power_setting_size = 0; + + if (o_ctrl->i2c_mode_data.is_settings_valid == 1) + delete_request(&o_ctrl->i2c_mode_data); + + if (o_ctrl->i2c_calib_data.is_settings_valid == 1) + delete_request(&o_ctrl->i2c_calib_data); + + if (o_ctrl->i2c_init_data.is_settings_valid == 1) + delete_request(&o_ctrl->i2c_init_data); + + break; + case CAM_STOP_DEV: + if (o_ctrl->cam_ois_state != CAM_OIS_START) { + rc = -EINVAL; + CAM_WARN(CAM_OIS, + "Not in right state for stop : %d", + o_ctrl->cam_ois_state); + } + o_ctrl->cam_ois_state = CAM_OIS_CONFIG; + break; + default: + CAM_ERR(CAM_OIS, "invalid opcode"); + goto release_mutex; + } +release_mutex: + mutex_unlock(&(o_ctrl->ois_mutex)); + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_core.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_core.h new file mode 100644 index 0000000000000000000000000000000000000000..33abe8b75c728c217b46e4e75625212de92624d3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_core.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ +#ifndef _CAM_OIS_CORE_H_ +#define _CAM_OIS_CORE_H_ + +#include +#include "cam_ois_dev.h" + +#define OIS_NAME_LEN 32 + +/** + * @power_info: power setting info to control the power + * + * This API construct the default ois power setting. + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int32_t cam_ois_construct_default_power_setting( + struct cam_sensor_power_ctrl_t *power_info); + + +int cam_ois_driver_cmd(struct cam_ois_ctrl_t *e_ctrl, void *arg); + +/** + * @o_ctrl: OIS ctrl structure + * + * This API handles the shutdown ioctl/close + */ +void cam_ois_shutdown(struct cam_ois_ctrl_t *o_ctrl); + +#endif +/* _CAM_OIS_CORE_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_dev.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..10044cec6efd27e8bf5d5873dc146ae3105302f5 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_dev.c @@ -0,0 +1,422 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#include "cam_ois_dev.h" +#include "cam_req_mgr_dev.h" +#include "cam_ois_soc.h" +#include "cam_ois_core.h" +#include "cam_debug_util.h" + +static long cam_ois_subdev_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + int rc = 0; + struct cam_ois_ctrl_t *o_ctrl = v4l2_get_subdevdata(sd); + + switch (cmd) { + case VIDIOC_CAM_CONTROL: + rc = cam_ois_driver_cmd(o_ctrl, arg); + break; + default: + rc = -ENOIOCTLCMD; + break; + } + + return rc; +} + +static int cam_ois_subdev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct cam_ois_ctrl_t *o_ctrl = + v4l2_get_subdevdata(sd); + + if (!o_ctrl) { + CAM_ERR(CAM_OIS, "o_ctrl ptr is NULL"); + return -EINVAL; + } + + mutex_lock(&(o_ctrl->ois_mutex)); + cam_ois_shutdown(o_ctrl); + mutex_unlock(&(o_ctrl->ois_mutex)); + + return 0; +} + +static int32_t cam_ois_update_i2c_info(struct cam_ois_ctrl_t *o_ctrl, + struct cam_ois_i2c_info_t *i2c_info) +{ + struct cam_sensor_cci_client *cci_client = NULL; + + if (o_ctrl->io_master_info.master_type == CCI_MASTER) { + cci_client = o_ctrl->io_master_info.cci_client; + if (!cci_client) { + CAM_ERR(CAM_OIS, "failed: cci_client %pK", + cci_client); + return -EINVAL; + } + cci_client->cci_i2c_master = o_ctrl->cci_i2c_master; + cci_client->sid = (i2c_info->slave_addr) >> 1; + cci_client->retries = 3; + cci_client->id_map = 0; + cci_client->i2c_freq_mode = i2c_info->i2c_freq_mode; + } + + return 0; +} + +#ifdef CONFIG_COMPAT +static long cam_ois_init_subdev_do_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + struct cam_control cmd_data; + int32_t rc = 0; + + if (copy_from_user(&cmd_data, (void __user *)arg, + sizeof(cmd_data))) { + CAM_ERR(CAM_OIS, + "Failed to copy from user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + return -EFAULT; + } + + switch (cmd) { + case VIDIOC_CAM_CONTROL: + rc = cam_ois_subdev_ioctl(sd, cmd, &cmd_data); + if (rc) { + CAM_ERR(CAM_OIS, + "Failed in ois suddev handling rc %d", + rc); + return rc; + } + break; + default: + CAM_ERR(CAM_OIS, "Invalid compat ioctl: %d", cmd); + rc = -EINVAL; + } + + if (!rc) { + if (copy_to_user((void __user *)arg, &cmd_data, + sizeof(cmd_data))) { + CAM_ERR(CAM_OIS, + "Failed to copy from user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + rc = -EFAULT; + } + } + return rc; +} +#endif + +static const struct v4l2_subdev_internal_ops cam_ois_internal_ops = { + .close = cam_ois_subdev_close, +}; + +static struct v4l2_subdev_core_ops cam_ois_subdev_core_ops = { + .ioctl = cam_ois_subdev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = cam_ois_init_subdev_do_ioctl, +#endif +}; + +static struct v4l2_subdev_ops cam_ois_subdev_ops = { + .core = &cam_ois_subdev_core_ops, +}; + +static int cam_ois_init_subdev_param(struct cam_ois_ctrl_t *o_ctrl) +{ + int rc = 0; + + o_ctrl->v4l2_dev_str.internal_ops = &cam_ois_internal_ops; + o_ctrl->v4l2_dev_str.ops = &cam_ois_subdev_ops; + strlcpy(o_ctrl->device_name, CAM_OIS_NAME, + sizeof(o_ctrl->device_name)); + o_ctrl->v4l2_dev_str.name = o_ctrl->device_name; + o_ctrl->v4l2_dev_str.sd_flags = + (V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS); + o_ctrl->v4l2_dev_str.ent_function = CAM_OIS_DEVICE_TYPE; + o_ctrl->v4l2_dev_str.token = o_ctrl; + + rc = cam_register_subdev(&(o_ctrl->v4l2_dev_str)); + if (rc) + CAM_ERR(CAM_OIS, "fail to create subdev"); + + return rc; +} + +static int cam_ois_i2c_driver_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int rc = 0; + struct cam_ois_ctrl_t *o_ctrl = NULL; + struct cam_ois_soc_private *soc_private = NULL; + + if (client == NULL || id == NULL) { + CAM_ERR(CAM_OIS, "Invalid Args client: %pK id: %pK", + client, id); + return -EINVAL; + } + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + CAM_ERR(CAM_OIS, "i2c_check_functionality failed"); + goto probe_failure; + } + + o_ctrl = kzalloc(sizeof(*o_ctrl), GFP_KERNEL); + if (!o_ctrl) { + CAM_ERR(CAM_OIS, "kzalloc failed"); + rc = -ENOMEM; + goto probe_failure; + } + + i2c_set_clientdata(client, o_ctrl); + + o_ctrl->soc_info.dev = &client->dev; + o_ctrl->soc_info.dev_name = client->name; + o_ctrl->ois_device_type = MSM_CAMERA_I2C_DEVICE; + o_ctrl->io_master_info.master_type = I2C_MASTER; + o_ctrl->io_master_info.client = client; + + soc_private = kzalloc(sizeof(struct cam_ois_soc_private), + GFP_KERNEL); + if (!soc_private) { + rc = -ENOMEM; + goto octrl_free; + } + + o_ctrl->soc_info.soc_private = soc_private; + rc = cam_ois_driver_soc_init(o_ctrl); + if (rc) { + CAM_ERR(CAM_OIS, "failed: cam_sensor_parse_dt rc %d", rc); + goto soc_free; + } + + rc = cam_ois_init_subdev_param(o_ctrl); + if (rc) + goto soc_free; + + o_ctrl->cam_ois_state = CAM_OIS_INIT; + + return rc; + +soc_free: + kfree(soc_private); +octrl_free: + kfree(o_ctrl); +probe_failure: + return rc; +} + +static int cam_ois_i2c_driver_remove(struct i2c_client *client) +{ + int i; + struct cam_ois_ctrl_t *o_ctrl = i2c_get_clientdata(client); + struct cam_hw_soc_info *soc_info; + struct cam_ois_soc_private *soc_private; + struct cam_sensor_power_ctrl_t *power_info; + + if (!o_ctrl) { + CAM_ERR(CAM_OIS, "ois device is NULL"); + return -EINVAL; + } + + CAM_INFO(CAM_OIS, "i2c driver remove invoked"); + soc_info = &o_ctrl->soc_info; + + for (i = 0; i < soc_info->num_clk; i++) + devm_clk_put(soc_info->dev, soc_info->clk[i]); + + mutex_lock(&(o_ctrl->ois_mutex)); + cam_ois_shutdown(o_ctrl); + mutex_unlock(&(o_ctrl->ois_mutex)); + cam_unregister_subdev(&(o_ctrl->v4l2_dev_str)); + + soc_private = + (struct cam_ois_soc_private *)soc_info->soc_private; + power_info = &soc_private->power_info; + + kfree(o_ctrl->soc_info.soc_private); + v4l2_set_subdevdata(&o_ctrl->v4l2_dev_str.sd, NULL); + kfree(o_ctrl); + + return 0; +} + +static int32_t cam_ois_platform_driver_probe( + struct platform_device *pdev) +{ + int32_t rc = 0; + struct cam_ois_ctrl_t *o_ctrl = NULL; + struct cam_ois_soc_private *soc_private = NULL; + + o_ctrl = kzalloc(sizeof(struct cam_ois_ctrl_t), GFP_KERNEL); + if (!o_ctrl) + return -ENOMEM; + + o_ctrl->soc_info.pdev = pdev; + o_ctrl->pdev = pdev; + o_ctrl->soc_info.dev = &pdev->dev; + o_ctrl->soc_info.dev_name = pdev->name; + + o_ctrl->ois_device_type = MSM_CAMERA_PLATFORM_DEVICE; + + o_ctrl->io_master_info.master_type = CCI_MASTER; + o_ctrl->io_master_info.cci_client = kzalloc( + sizeof(struct cam_sensor_cci_client), GFP_KERNEL); + if (!o_ctrl->io_master_info.cci_client) + goto free_o_ctrl; + + soc_private = kzalloc(sizeof(struct cam_ois_soc_private), + GFP_KERNEL); + if (!soc_private) { + rc = -ENOMEM; + goto free_cci_client; + } + o_ctrl->soc_info.soc_private = soc_private; + soc_private->power_info.dev = &pdev->dev; + + INIT_LIST_HEAD(&(o_ctrl->i2c_init_data.list_head)); + INIT_LIST_HEAD(&(o_ctrl->i2c_calib_data.list_head)); + INIT_LIST_HEAD(&(o_ctrl->i2c_mode_data.list_head)); + mutex_init(&(o_ctrl->ois_mutex)); + rc = cam_ois_driver_soc_init(o_ctrl); + if (rc) { + CAM_ERR(CAM_OIS, "failed: soc init rc %d", rc); + goto free_soc; + } + + rc = cam_ois_init_subdev_param(o_ctrl); + if (rc) + goto free_soc; + + rc = cam_ois_update_i2c_info(o_ctrl, &soc_private->i2c_info); + if (rc) { + CAM_ERR(CAM_OIS, "failed: to update i2c info rc %d", rc); + goto unreg_subdev; + } + o_ctrl->bridge_intf.device_hdl = -1; + + platform_set_drvdata(pdev, o_ctrl); + o_ctrl->cam_ois_state = CAM_OIS_INIT; + + return rc; +unreg_subdev: + cam_unregister_subdev(&(o_ctrl->v4l2_dev_str)); +free_soc: + kfree(soc_private); +free_cci_client: + kfree(o_ctrl->io_master_info.cci_client); +free_o_ctrl: + kfree(o_ctrl); + return rc; +} + +static int cam_ois_platform_driver_remove(struct platform_device *pdev) +{ + int i; + struct cam_ois_ctrl_t *o_ctrl; + struct cam_ois_soc_private *soc_private; + struct cam_sensor_power_ctrl_t *power_info; + struct cam_hw_soc_info *soc_info; + + o_ctrl = platform_get_drvdata(pdev); + if (!o_ctrl) { + CAM_ERR(CAM_OIS, "ois device is NULL"); + return -EINVAL; + } + + CAM_INFO(CAM_OIS, "platform driver remove invoked"); + soc_info = &o_ctrl->soc_info; + for (i = 0; i < soc_info->num_clk; i++) + devm_clk_put(soc_info->dev, soc_info->clk[i]); + + mutex_lock(&(o_ctrl->ois_mutex)); + cam_ois_shutdown(o_ctrl); + mutex_unlock(&(o_ctrl->ois_mutex)); + cam_unregister_subdev(&(o_ctrl->v4l2_dev_str)); + + soc_private = + (struct cam_ois_soc_private *)o_ctrl->soc_info.soc_private; + power_info = &soc_private->power_info; + + kfree(o_ctrl->soc_info.soc_private); + kfree(o_ctrl->io_master_info.cci_client); + platform_set_drvdata(pdev, NULL); + v4l2_set_subdevdata(&o_ctrl->v4l2_dev_str.sd, NULL); + kfree(o_ctrl); + + return 0; +} + +static const struct of_device_id cam_ois_dt_match[] = { + { .compatible = "qcom,ois" }, + { } +}; + + +MODULE_DEVICE_TABLE(of, cam_ois_dt_match); + +static struct platform_driver cam_ois_platform_driver = { + .driver = { + .name = "qcom,ois", + .owner = THIS_MODULE, + .of_match_table = cam_ois_dt_match, + }, + .probe = cam_ois_platform_driver_probe, + .remove = cam_ois_platform_driver_remove, +}; +static const struct i2c_device_id cam_ois_i2c_id[] = { + { "msm_ois", (kernel_ulong_t)NULL}, + { } +}; + +static struct i2c_driver cam_ois_i2c_driver = { + .id_table = cam_ois_i2c_id, + .probe = cam_ois_i2c_driver_probe, + .remove = cam_ois_i2c_driver_remove, + .driver = { + .name = "msm_ois", + }, +}; + +static struct cam_ois_registered_driver_t registered_driver = { + 0, 0}; + +static int __init cam_ois_driver_init(void) +{ + int rc = 0; + + rc = platform_driver_register(&cam_ois_platform_driver); + if (rc) { + CAM_ERR(CAM_OIS, "platform_driver_register failed rc = %d", + rc); + return rc; + } + + registered_driver.platform_driver = 1; + + rc = i2c_add_driver(&cam_ois_i2c_driver); + if (rc) { + CAM_ERR(CAM_OIS, "i2c_add_driver failed rc = %d", rc); + return rc; + } + + registered_driver.i2c_driver = 1; + return rc; +} + +static void __exit cam_ois_driver_exit(void) +{ + if (registered_driver.platform_driver) + platform_driver_unregister(&cam_ois_platform_driver); + + if (registered_driver.i2c_driver) + i2c_del_driver(&cam_ois_i2c_driver); +} + +module_init(cam_ois_driver_init); +module_exit(cam_ois_driver_exit); +MODULE_DESCRIPTION("CAM OIS driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_dev.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..788243ae9da0a35d58f19b413f7fff0053fa867c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_dev.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ +#ifndef _CAM_OIS_DEV_H_ +#define _CAM_OIS_DEV_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_soc_util.h" +#include "cam_context.h" + +#define DEFINE_MSM_MUTEX(mutexname) \ + static struct mutex mutexname = __MUTEX_INITIALIZER(mutexname) + +enum cam_ois_state { + CAM_OIS_INIT, + CAM_OIS_ACQUIRE, + CAM_OIS_CONFIG, + CAM_OIS_START, +}; + +/** + * struct cam_ois_registered_driver_t - registered driver info + * @platform_driver : flag indicates if platform driver is registered + * @i2c_driver : flag indicates if i2c driver is registered + * + */ +struct cam_ois_registered_driver_t { + bool platform_driver; + bool i2c_driver; +}; + +/** + * struct cam_ois_i2c_info_t - I2C info + * @slave_addr : slave address + * @i2c_freq_mode : i2c frequency mode + * + */ +struct cam_ois_i2c_info_t { + uint16_t slave_addr; + uint8_t i2c_freq_mode; +}; + +/** + * struct cam_ois_soc_private - ois soc private data structure + * @ois_name : ois name + * @i2c_info : i2c info structure + * @power_info : ois power info + * + */ +struct cam_ois_soc_private { + const char *ois_name; + struct cam_ois_i2c_info_t i2c_info; + struct cam_sensor_power_ctrl_t power_info; +}; + +/** + * struct cam_ois_intf_params - bridge interface params + * @device_hdl : Device Handle + * @session_hdl : Session Handle + * @ops : KMD operations + * @crm_cb : Callback API pointers + */ +struct cam_ois_intf_params { + int32_t device_hdl; + int32_t session_hdl; + int32_t link_hdl; + struct cam_req_mgr_kmd_ops ops; + struct cam_req_mgr_crm_cb *crm_cb; +}; + +/** + * struct cam_ois_ctrl_t - OIS ctrl private data + * @device_name : ois device_name + * @pdev : platform device + * @ois_mutex : ois mutex + * @soc_info : ois soc related info + * @io_master_info : Information about the communication master + * @cci_i2c_master : I2C structure + * @v4l2_dev_str : V4L2 device structure + * @bridge_intf : bridge interface params + * @i2c_init_data : ois i2c init settings + * @i2c_mode_data : ois i2c mode settings + * @i2c_calib_data : ois i2c calib settings + * @ois_device_type : ois device type + * @cam_ois_state : ois_device_state + * @ois_fw_flag : flag for firmware download + * @is_ois_calib : flag for Calibration data + * @opcode : ois opcode + * @device_name : Device name + * + */ +struct cam_ois_ctrl_t { + char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH]; + struct platform_device *pdev; + struct mutex ois_mutex; + struct cam_hw_soc_info soc_info; + struct camera_io_master io_master_info; + enum cci_i2c_master_t cci_i2c_master; + enum cci_device_num cci_num; + struct cam_subdev v4l2_dev_str; + struct cam_ois_intf_params bridge_intf; + struct i2c_settings_array i2c_init_data; + struct i2c_settings_array i2c_calib_data; + struct i2c_settings_array i2c_mode_data; + enum msm_camera_device_type_t ois_device_type; + enum cam_ois_state cam_ois_state; + char ois_name[32]; + uint8_t ois_fw_flag; + uint8_t is_ois_calib; + struct cam_ois_opcode opcode; +}; + +#endif /*_CAM_OIS_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_soc.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..9c14d87e233d4d5c4332e88cb58c6ae77155ad40 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_soc.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "cam_ois_soc.h" +#include "cam_debug_util.h" + +/** + * @e_ctrl: ctrl structure + * + * Parses ois dt + */ +static int cam_ois_get_dt_data(struct cam_ois_ctrl_t *o_ctrl) +{ + int i, rc = 0; + struct cam_hw_soc_info *soc_info = &o_ctrl->soc_info; + struct cam_ois_soc_private *soc_private = + (struct cam_ois_soc_private *)o_ctrl->soc_info.soc_private; + struct cam_sensor_power_ctrl_t *power_info = &soc_private->power_info; + struct device_node *of_node = NULL; + + of_node = soc_info->dev->of_node; + + if (!of_node) { + CAM_ERR(CAM_OIS, "of_node is NULL, device type %d", + o_ctrl->ois_device_type); + return -EINVAL; + } + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) { + CAM_ERR(CAM_OIS, "cam_soc_util_get_dt_properties rc %d", + rc); + return rc; + } + + if (!soc_info->gpio_data) { + CAM_INFO(CAM_OIS, "No GPIO found"); + return 0; + } + + if (!soc_info->gpio_data->cam_gpio_common_tbl_size) { + CAM_INFO(CAM_OIS, "No GPIO found"); + return -EINVAL; + } + + rc = cam_sensor_util_init_gpio_pin_tbl(soc_info, + &power_info->gpio_num_info); + if ((rc < 0) || (!power_info->gpio_num_info)) { + CAM_ERR(CAM_OIS, "No/Error OIS GPIOs"); + return -EINVAL; + } + + for (i = 0; i < soc_info->num_clk; i++) { + soc_info->clk[i] = devm_clk_get(soc_info->dev, + soc_info->clk_name[i]); + if (!soc_info->clk[i]) { + CAM_ERR(CAM_SENSOR, "get failed for %s", + soc_info->clk_name[i]); + rc = -ENOENT; + return rc; + } + } + + return rc; +} +/** + * @o_ctrl: ctrl structure + * + * This function is called from cam_ois_platform/i2c_driver_probe, it parses + * the ois dt node. + */ +int cam_ois_driver_soc_init(struct cam_ois_ctrl_t *o_ctrl) +{ + int rc = 0; + struct cam_hw_soc_info *soc_info = &o_ctrl->soc_info; + struct device_node *of_node = NULL; + struct device_node *of_parent = NULL; + + if (!soc_info->dev) { + CAM_ERR(CAM_OIS, "soc_info is not initialized"); + return -EINVAL; + } + + of_node = soc_info->dev->of_node; + if (!of_node) { + CAM_ERR(CAM_OIS, "dev.of_node NULL"); + return -EINVAL; + } + + if (o_ctrl->ois_device_type == MSM_CAMERA_PLATFORM_DEVICE) { + rc = of_property_read_u32(of_node, "cci-master", + &o_ctrl->cci_i2c_master); + if (rc < 0) { + CAM_DBG(CAM_OIS, "failed rc %d", rc); + return rc; + } + + of_parent = of_get_parent(of_node); + if (of_property_read_u32(of_parent, "cell-index", + &o_ctrl->cci_num) < 0) + /* Set default master 0 */ + o_ctrl->cci_num = CCI_DEVICE_0; + + o_ctrl->io_master_info.cci_client->cci_device = o_ctrl->cci_num; + CAM_DBG(CAM_OIS, "cci-device %d", o_ctrl->cci_num, rc); + + } + + rc = cam_ois_get_dt_data(o_ctrl); + if (rc < 0) + CAM_DBG(CAM_OIS, "failed: ois get dt data rc %d", rc); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_soc.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..fd2c209c7504b2cb5b54ba6840ecffcb68c535f0 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/cam_ois_soc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ +#ifndef _CAM_OIS_SOC_H_ +#define _CAM_OIS_SOC_H_ + +#include "cam_ois_dev.h" + +int cam_ois_driver_soc_init(struct cam_ois_ctrl_t *o_ctrl); + +#endif/* _CAM_OIS_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..121757196dcc4d80b2881a15a868db3d9ccd80e4 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +#ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_res_mgr.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c new file mode 100644 index 0000000000000000000000000000000000000000..58a927426d867f0e9fa5f5e60fbd4ab8e78dfd05 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c @@ -0,0 +1,741 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "cam_debug_util.h" +#include "cam_res_mgr_api.h" +#include "cam_res_mgr_private.h" + +static struct cam_res_mgr *cam_res; + +static void cam_res_mgr_free_res(void) +{ + struct cam_dev_res *dev_res, *dev_temp; + struct cam_gpio_res *gpio_res, *gpio_temp; + struct cam_flash_res *flash_res, *flash_temp; + + if (!cam_res) + return; + + mutex_lock(&cam_res->gpio_res_lock); + list_for_each_entry_safe(gpio_res, gpio_temp, + &cam_res->gpio_res_list, list) { + list_for_each_entry_safe(dev_res, dev_temp, + &gpio_res->dev_list, list) { + list_del_init(&dev_res->list); + kfree(dev_res); + } + list_del_init(&gpio_res->list); + kfree(gpio_res); + } + mutex_unlock(&cam_res->gpio_res_lock); + + mutex_lock(&cam_res->flash_res_lock); + list_for_each_entry_safe(flash_res, flash_temp, + &cam_res->flash_res_list, list) { + list_del_init(&flash_res->list); + kfree(flash_res); + } + mutex_unlock(&cam_res->flash_res_lock); + + mutex_lock(&cam_res->clk_res_lock); + cam_res->shared_clk_ref_count = 0; + mutex_unlock(&cam_res->clk_res_lock); +} + +void cam_res_mgr_led_trigger_register(const char *name, struct led_trigger **tp) +{ + bool found = false; + struct cam_flash_res *flash_res; + + if (!cam_res) { + /* + * If this driver not probed, then just register the + * led trigger. + */ + led_trigger_register_simple(name, tp); + return; + } + + mutex_lock(&cam_res->flash_res_lock); + list_for_each_entry(flash_res, &cam_res->flash_res_list, list) { + if (!strcmp(flash_res->name, name)) { + found = true; + break; + } + } + mutex_unlock(&cam_res->flash_res_lock); + + if (found) { + *tp = flash_res->trigger; + } else { + flash_res = kzalloc(sizeof(struct cam_flash_res), GFP_KERNEL); + if (!flash_res) { + CAM_ERR(CAM_RES, + "Failed to malloc memory for flash_res:%s", + name); + *tp = NULL; + return; + } + + led_trigger_register_simple(name, tp); + INIT_LIST_HEAD(&flash_res->list); + flash_res->trigger = *tp; + flash_res->name = name; + + mutex_lock(&cam_res->flash_res_lock); + list_add_tail(&flash_res->list, &cam_res->flash_res_list); + mutex_unlock(&cam_res->flash_res_lock); + } +} +EXPORT_SYMBOL(cam_res_mgr_led_trigger_register); + +void cam_res_mgr_led_trigger_unregister(struct led_trigger *tp) +{ + bool found = false; + struct cam_flash_res *flash_res; + + if (!cam_res) { + /* + * If this driver not probed, then just unregister the + * led trigger. + */ + led_trigger_unregister_simple(tp); + return; + } + + mutex_lock(&cam_res->flash_res_lock); + list_for_each_entry(flash_res, &cam_res->flash_res_list, list) { + if (flash_res->trigger == tp) { + found = true; + break; + } + } + + if (found) { + led_trigger_unregister_simple(tp); + list_del_init(&flash_res->list); + kfree(flash_res); + } + mutex_unlock(&cam_res->flash_res_lock); +} +EXPORT_SYMBOL(cam_res_mgr_led_trigger_unregister); + +void cam_res_mgr_led_trigger_event(struct led_trigger *trig, + enum led_brightness brightness) +{ + bool found = false; + struct cam_flash_res *flash_res; + + if (!cam_res) { + /* + * If this driver not probed, then just trigger + * the led event. + */ + led_trigger_event(trig, brightness); + return; + } + + mutex_lock(&cam_res->flash_res_lock); + list_for_each_entry(flash_res, &cam_res->flash_res_list, list) { + if (flash_res->trigger == trig) { + found = true; + break; + } + } + mutex_unlock(&cam_res->flash_res_lock); + + if (found) + led_trigger_event(trig, brightness); +} +EXPORT_SYMBOL(cam_res_mgr_led_trigger_event); + +int cam_res_mgr_shared_pinctrl_init(void) +{ + struct cam_soc_pinctrl_info *pinctrl_info; + + /* + * We allow the cam_res is NULL or shared_gpio_enabled + * is false, it means this driver no probed or doesn't + * have shared gpio in this device. + */ + if (!cam_res || !cam_res->shared_gpio_enabled) { + CAM_DBG(CAM_RES, "Not support shared gpio."); + return 0; + } + + mutex_lock(&cam_res->gpio_res_lock); + if (cam_res->pstatus != PINCTRL_STATUS_PUT) { + CAM_DBG(CAM_RES, "The shared pinctrl already been got."); + mutex_unlock(&cam_res->gpio_res_lock); + return 0; + } + + pinctrl_info = &cam_res->dt.pinctrl_info; + + pinctrl_info->pinctrl = + devm_pinctrl_get(cam_res->dev); + if (IS_ERR_OR_NULL(pinctrl_info->pinctrl)) { + CAM_ERR(CAM_RES, "Pinctrl not available"); + cam_res->shared_gpio_enabled = false; + mutex_unlock(&cam_res->gpio_res_lock); + return -EINVAL; + } + + pinctrl_info->gpio_state_active = + pinctrl_lookup_state(pinctrl_info->pinctrl, + CAM_RES_MGR_DEFAULT); + if (IS_ERR_OR_NULL(pinctrl_info->gpio_state_active)) { + CAM_ERR(CAM_RES, + "Failed to get the active state pinctrl handle"); + cam_res->shared_gpio_enabled = false; + mutex_unlock(&cam_res->gpio_res_lock); + return -EINVAL; + } + + pinctrl_info->gpio_state_suspend = + pinctrl_lookup_state(pinctrl_info->pinctrl, + CAM_RES_MGR_SLEEP); + if (IS_ERR_OR_NULL(pinctrl_info->gpio_state_suspend)) { + CAM_ERR(CAM_RES, + "Failed to get the active state pinctrl handle"); + cam_res->shared_gpio_enabled = false; + mutex_unlock(&cam_res->gpio_res_lock); + return -EINVAL; + } + + cam_res->pstatus = PINCTRL_STATUS_GOT; + mutex_unlock(&cam_res->gpio_res_lock); + + return 0; +} +EXPORT_SYMBOL(cam_res_mgr_shared_pinctrl_init); + +static bool cam_res_mgr_shared_pinctrl_check_hold(void) +{ + int index = 0; + int dev_num = 0; + bool hold = false; + struct list_head *list; + struct cam_gpio_res *gpio_res; + struct cam_res_mgr_dt *dt = &cam_res->dt; + + for (; index < dt->num_shared_gpio; index++) { + list_for_each_entry(gpio_res, + &cam_res->gpio_res_list, list) { + + if (gpio_res->gpio == + dt->shared_gpio[index]) { + list_for_each(list, &gpio_res->dev_list) + dev_num++; + + if (dev_num >= 2) { + hold = true; + break; + } + } + } + } + + if (cam_res->shared_clk_ref_count > 1) + hold = true; + + return hold; +} + +void cam_res_mgr_shared_pinctrl_put(void) +{ + struct cam_soc_pinctrl_info *pinctrl_info; + + if (!cam_res || !cam_res->shared_gpio_enabled) { + CAM_DBG(CAM_RES, "Not support shared gpio."); + return; + } + + mutex_lock(&cam_res->gpio_res_lock); + if (cam_res->pstatus == PINCTRL_STATUS_PUT) { + CAM_DBG(CAM_RES, "The shared pinctrl already been put"); + mutex_unlock(&cam_res->gpio_res_lock); + return; + } + + if (cam_res_mgr_shared_pinctrl_check_hold()) { + CAM_INFO(CAM_RES, "Need hold put this pinctrl"); + mutex_unlock(&cam_res->gpio_res_lock); + return; + } + + pinctrl_info = &cam_res->dt.pinctrl_info; + + devm_pinctrl_put(pinctrl_info->pinctrl); + + cam_res->pstatus = PINCTRL_STATUS_PUT; + mutex_unlock(&cam_res->gpio_res_lock); +} +EXPORT_SYMBOL(cam_res_mgr_shared_pinctrl_put); + +int cam_res_mgr_shared_pinctrl_select_state(bool active) +{ + int rc = 0; + struct cam_soc_pinctrl_info *pinctrl_info; + + if (!cam_res || !cam_res->shared_gpio_enabled) { + CAM_DBG(CAM_RES, "Not support shared gpio."); + return 0; + } + + mutex_lock(&cam_res->gpio_res_lock); + if (cam_res->pstatus == PINCTRL_STATUS_PUT) { + CAM_DBG(CAM_RES, "The shared pinctrl alerady been put.!"); + mutex_unlock(&cam_res->gpio_res_lock); + return 0; + } + + pinctrl_info = &cam_res->dt.pinctrl_info; + + if (active && (cam_res->pstatus != PINCTRL_STATUS_ACTIVE)) { + rc = pinctrl_select_state(pinctrl_info->pinctrl, + pinctrl_info->gpio_state_active); + cam_res->pstatus = PINCTRL_STATUS_ACTIVE; + } else if (!active && + !cam_res_mgr_shared_pinctrl_check_hold()) { + rc = pinctrl_select_state(pinctrl_info->pinctrl, + pinctrl_info->gpio_state_suspend); + cam_res->pstatus = PINCTRL_STATUS_SUSPEND; + } + + mutex_unlock(&cam_res->gpio_res_lock); + + return rc; +} +EXPORT_SYMBOL(cam_res_mgr_shared_pinctrl_select_state); + +int cam_res_mgr_shared_pinctrl_post_init(void) +{ + int ret = 0; + struct cam_soc_pinctrl_info *pinctrl_info; + + if (!cam_res || !cam_res->shared_gpio_enabled) { + CAM_DBG(CAM_RES, "Not support shared gpio."); + return ret; + } + + mutex_lock(&cam_res->gpio_res_lock); + if (cam_res->pstatus == PINCTRL_STATUS_PUT) { + CAM_DBG(CAM_RES, "The shared pinctrl alerady been put.!"); + mutex_unlock(&cam_res->gpio_res_lock); + return ret; + } + + pinctrl_info = &cam_res->dt.pinctrl_info; + + /* + * If no gpio resource in gpio_res_list, and + * no shared clk now, it means this device + * don't have shared gpio. + */ + if (list_empty(&cam_res->gpio_res_list) && + cam_res->shared_clk_ref_count < 1) { + ret = pinctrl_select_state(pinctrl_info->pinctrl, + pinctrl_info->gpio_state_suspend); + devm_pinctrl_put(pinctrl_info->pinctrl); + cam_res->pstatus = PINCTRL_STATUS_PUT; + } + mutex_unlock(&cam_res->gpio_res_lock); + + return ret; +} +EXPORT_SYMBOL(cam_res_mgr_shared_pinctrl_post_init); + +static int cam_res_mgr_add_device(struct device *dev, + struct cam_gpio_res *gpio_res) +{ + struct cam_dev_res *dev_res = NULL; + + dev_res = kzalloc(sizeof(struct cam_dev_res), GFP_KERNEL); + if (!dev_res) + return -ENOMEM; + + dev_res->dev = dev; + INIT_LIST_HEAD(&dev_res->list); + + list_add_tail(&dev_res->list, &gpio_res->dev_list); + + return 0; +} + +static bool cam_res_mgr_gpio_is_shared(uint gpio) +{ + int index = 0; + bool found = false; + struct cam_res_mgr_dt *dt = &cam_res->dt; + + mutex_lock(&cam_res->gpio_res_lock); + for (; index < dt->num_shared_gpio; index++) { + if (gpio == dt->shared_gpio[index]) { + found = true; + break; + } + } + mutex_unlock(&cam_res->gpio_res_lock); + + return found; +} + +int cam_res_mgr_gpio_request(struct device *dev, uint gpio, + unsigned long flags, const char *label) +{ + int rc = 0; + bool found = false; + struct cam_gpio_res *gpio_res = NULL; + + if (cam_res && cam_res->shared_gpio_enabled) { + mutex_lock(&cam_res->gpio_res_lock); + list_for_each_entry(gpio_res, &cam_res->gpio_res_list, list) { + if (gpio == gpio_res->gpio) { + found = true; + break; + } + } + mutex_unlock(&cam_res->gpio_res_lock); + } + + /* + * found equal to false has two situation: + * 1. shared gpio not enabled + * 2. shared gpio enabled, but not find this gpio + * from the gpio_res_list + * These two situation both need request gpio. + */ + if (!found) { + rc = gpio_request_one(gpio, flags, label); + if (rc) { + CAM_ERR(CAM_RES, "gpio %d:%s request fails", + gpio, label); + return rc; + } + } + + /* + * If the gpio is in the shared list, and not find + * from gpio_res_list, then insert a cam_gpio_res + * to gpio_res_list. + */ + if (!found && cam_res + && cam_res->shared_gpio_enabled && + cam_res_mgr_gpio_is_shared(gpio)) { + + gpio_res = kzalloc(sizeof(struct cam_gpio_res), GFP_KERNEL); + if (!gpio_res) + return -ENOMEM; + + gpio_res->gpio = gpio; + gpio_res->power_on_count = 0; + INIT_LIST_HEAD(&gpio_res->list); + INIT_LIST_HEAD(&gpio_res->dev_list); + + mutex_lock(&cam_res->gpio_res_lock); + rc = cam_res_mgr_add_device(dev, gpio_res); + if (rc) { + kfree(gpio_res); + mutex_unlock(&cam_res->gpio_res_lock); + return rc; + } + + list_add_tail(&gpio_res->list, &cam_res->gpio_res_list); + mutex_unlock(&cam_res->gpio_res_lock); + } + + if (found && cam_res + && cam_res->shared_gpio_enabled) { + struct cam_dev_res *dev_res = NULL; + + found = 0; + mutex_lock(&cam_res->gpio_res_lock); + list_for_each_entry(dev_res, &gpio_res->dev_list, list) { + if (dev_res->dev == dev) { + found = 1; + break; + } + } + + if (!found) + rc = cam_res_mgr_add_device(dev, gpio_res); + + mutex_unlock(&cam_res->gpio_res_lock); + } + + return rc; +} +EXPORT_SYMBOL(cam_res_mgr_gpio_request); + +static void cam_res_mgr_gpio_free(struct device *dev, uint gpio) +{ + bool found = false; + bool need_free = true; + int dev_num = 0; + struct cam_gpio_res *gpio_res = NULL; + + if (cam_res && cam_res->shared_gpio_enabled) { + mutex_lock(&cam_res->gpio_res_lock); + list_for_each_entry(gpio_res, &cam_res->gpio_res_list, list) { + if (gpio == gpio_res->gpio) { + found = true; + break; + } + } + mutex_unlock(&cam_res->gpio_res_lock); + } + + if (found && cam_res + && cam_res->shared_gpio_enabled) { + struct list_head *list; + struct cam_dev_res *dev_res = NULL; + + mutex_lock(&cam_res->gpio_res_lock); + /* Count the dev number in the dev_list */ + list_for_each(list, &gpio_res->dev_list) + dev_num++; + + /* + * Need free the gpio if only has last 1 device + * in the dev_list, otherwise, not free this + * gpio. + */ + if (dev_num == 1) { + dev_res = list_first_entry(&gpio_res->dev_list, + struct cam_dev_res, list); + list_del_init(&dev_res->list); + kfree(dev_res); + + list_del_init(&gpio_res->list); + kfree(gpio_res); + } else { + list_for_each_entry(dev_res, + &gpio_res->dev_list, list) { + if (dev_res->dev == dev) { + list_del_init(&dev_res->list); + kfree(dev_res); + need_free = false; + break; + } + } + } + mutex_unlock(&cam_res->gpio_res_lock); + } + + if (need_free) + gpio_free(gpio); +} + +void cam_res_mgr_gpio_free_arry(struct device *dev, + const struct gpio *array, size_t num) +{ + while (num--) + cam_res_mgr_gpio_free(dev, (array[num]).gpio); +} +EXPORT_SYMBOL(cam_res_mgr_gpio_free_arry); + +int cam_res_mgr_gpio_set_value(unsigned int gpio, int value) +{ + int rc = 0; + bool found = false; + struct cam_gpio_res *gpio_res = NULL; + + if (cam_res && cam_res->shared_gpio_enabled) { + mutex_lock(&cam_res->gpio_res_lock); + list_for_each_entry(gpio_res, &cam_res->gpio_res_list, list) { + if (gpio == gpio_res->gpio) { + found = true; + break; + } + } + mutex_unlock(&cam_res->gpio_res_lock); + } + + /* + * Set the value directly if can't find the gpio from + * gpio_res_list, otherwise, need add ref count support + **/ + if (!found) { + gpio_set_value_cansleep(gpio, value); + } else { + if (value) { + gpio_res->power_on_count++; + if (gpio_res->power_on_count < 2) { + gpio_set_value_cansleep(gpio, value); + CAM_DBG(CAM_RES, + "Shared GPIO(%d) : HIGH", gpio); + } + } else { + gpio_res->power_on_count--; + if (gpio_res->power_on_count < 1) { + gpio_set_value_cansleep(gpio, value); + CAM_DBG(CAM_RES, + "Shared GPIO(%d) : LOW", gpio); + } + } + } + + return rc; +} +EXPORT_SYMBOL(cam_res_mgr_gpio_set_value); + +void cam_res_mgr_shared_clk_config(bool value) +{ + if (!cam_res) + return; + + mutex_lock(&cam_res->clk_res_lock); + if (value) + cam_res->shared_clk_ref_count++; + else + cam_res->shared_clk_ref_count--; + mutex_unlock(&cam_res->clk_res_lock); +} +EXPORT_SYMBOL(cam_res_mgr_shared_clk_config); + +static int cam_res_mgr_parse_dt(struct device *dev) +{ + int rc = 0, i = 0; + struct device_node *of_node = NULL; + struct cam_res_mgr_dt *dt = &cam_res->dt; + + of_node = dev->of_node; + + dt->num_shared_gpio = of_gpio_count(of_node); + if (dt->num_shared_gpio > MAX_SHARED_GPIO_SIZE || + dt->num_shared_gpio <= 0) { + /* + * Not really an error, it means dtsi not configure + * the shared gpio. + */ + CAM_DBG(CAM_RES, "Invalid GPIO number %d. No shared gpio.", + dt->num_shared_gpio); + return -EINVAL; + } + + for (i = 0; i < dt->num_shared_gpio; i++) { + dt->shared_gpio[i] = of_get_gpio(of_node, i); + if (dt->shared_gpio[i] < 0) { + CAM_ERR(CAM_RES, "Get shared gpio array failed."); + return -EINVAL; + } + CAM_DBG(CAM_UTIL, "shared_gpio[%d] = %d", + i, dt->shared_gpio[i]); + } + + dt->pinctrl_info.pinctrl = devm_pinctrl_get(dev); + if (IS_ERR_OR_NULL(dt->pinctrl_info.pinctrl)) { + CAM_ERR(CAM_RES, "Pinctrl not available"); + return -EINVAL; + } + + /* + * Check the pinctrl state to make sure the gpio + * shared enabled. + */ + dt->pinctrl_info.gpio_state_active = + pinctrl_lookup_state(dt->pinctrl_info.pinctrl, + CAM_RES_MGR_DEFAULT); + if (IS_ERR_OR_NULL(dt->pinctrl_info.gpio_state_active)) { + CAM_ERR(CAM_RES, + "Failed to get the active state pinctrl handle"); + return -EINVAL; + } + + dt->pinctrl_info.gpio_state_suspend = + pinctrl_lookup_state(dt->pinctrl_info.pinctrl, + CAM_RES_MGR_SLEEP); + if (IS_ERR_OR_NULL(dt->pinctrl_info.gpio_state_suspend)) { + CAM_ERR(CAM_RES, + "Failed to get the active state pinctrl handle"); + return -EINVAL; + } + + devm_pinctrl_put(dt->pinctrl_info.pinctrl); + + return rc; +} + +static int cam_res_mgr_probe(struct platform_device *pdev) +{ + int rc = 0; + + cam_res = kzalloc(sizeof(*cam_res), GFP_KERNEL); + if (!cam_res) + return -ENOMEM; + + cam_res->dev = &pdev->dev; + mutex_init(&cam_res->flash_res_lock); + mutex_init(&cam_res->gpio_res_lock); + mutex_init(&cam_res->clk_res_lock); + + rc = cam_res_mgr_parse_dt(&pdev->dev); + if (rc) { + CAM_INFO(CAM_RES, "Disable shared gpio support."); + cam_res->shared_gpio_enabled = false; + } else { + CAM_INFO(CAM_RES, "Enable shared gpio support."); + cam_res->shared_gpio_enabled = true; + } + + cam_res->shared_clk_ref_count = 0; + cam_res->pstatus = PINCTRL_STATUS_PUT; + + INIT_LIST_HEAD(&cam_res->gpio_res_list); + INIT_LIST_HEAD(&cam_res->flash_res_list); + + return 0; +} + +static int cam_res_mgr_remove(struct platform_device *pdev) +{ + if (cam_res) { + cam_res_mgr_free_res(); + kfree(cam_res); + cam_res = NULL; + } + + return 0; +} + +static const struct of_device_id cam_res_mgr_dt_match[] = { + {.compatible = "qcom,cam-res-mgr"}, + {} +}; +MODULE_DEVICE_TABLE(of, cam_res_mgr_dt_match); + +static struct platform_driver cam_res_mgr_driver = { + .probe = cam_res_mgr_probe, + .remove = cam_res_mgr_remove, + .driver = { + .name = "cam_res_mgr", + .owner = THIS_MODULE, + .of_match_table = cam_res_mgr_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_res_mgr_init(void) +{ + return platform_driver_register(&cam_res_mgr_driver); +} + +static void __exit cam_res_mgr_exit(void) +{ + platform_driver_unregister(&cam_res_mgr_driver); +} + +module_init(cam_res_mgr_init); +module_exit(cam_res_mgr_exit); +MODULE_DESCRIPTION("Camera resource manager driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr_api.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr_api.h new file mode 100644 index 0000000000000000000000000000000000000000..e259ba7f2c7893d20fb8718933bc4ba1f297233d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr_api.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef __CAM_RES_MGR_API_H__ +#define __CAM_RES_MGR_API_H__ + +#include + +/** + * @brief: Register the led trigger + * + * The newly registered led trigger is assigned to flash_res_list. + * + * @name : Pointer to int led trigger name + * @tp : Save the returned led trigger + * + * @return None + */ +void cam_res_mgr_led_trigger_register(const char *name, + struct led_trigger **tp); + +/** + * @brief: Unregister the led trigger + * + * Free the flash_res if this led trigger isn't used by other device . + * + * @tp : Pointer to the led trigger + * + * @return None + */ +void cam_res_mgr_led_trigger_unregister(struct led_trigger *tp); + +/** + * @brief: Trigger the event to led core + * + * @trig : Pointer to the led trigger + * @brightness : The brightness need to fire + * + * @return None + */ +void cam_res_mgr_led_trigger_event(struct led_trigger *trig, + enum led_brightness brightness); + +/** + * @brief: Get the corresponding pinctrl of dev + * + * Init the shared pinctrl if shared pinctrl enabled. + * + * @return None + */ +int cam_res_mgr_shared_pinctrl_init(void); + +/** + * @brief: Put the pinctrl + * + * Put the shared pinctrl. + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +void cam_res_mgr_shared_pinctrl_put(void); + +/** + * @brief: Select the corresponding state + * + * Active state can be selected directly, but need hold to suspend the + * pinctrl if the gpios in this pinctrl also held by other pinctrl. + * + * @active : The flag to indicate whether active or suspend + * the shared pinctrl. + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_res_mgr_shared_pinctrl_select_state(bool active); + +/** + * @brief: Post init shared pinctrl + * + * Post init to check if the device really has shared gpio, + * suspend and put the pinctrl if not use shared gpio. + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_res_mgr_shared_pinctrl_post_init(void); + +/** + * @brief: Request a gpio + * + * Will alloc a gpio_res for the new gpio, other find the corresponding + * gpio_res. + * + * @dev : Pointer to the device + * @gpio : The GPIO number + * @flags : GPIO configuration as specified by GPIOF_* + * @label : A literal description string of this GPIO + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_res_mgr_gpio_request(struct device *dev, unsigned int gpio, + unsigned long flags, const char *label); + +/** + * @brief: Free a array GPIO + * + * Free the GPIOs and release corresponding gpio_res. + * + * @dev : Pointer to the device + * @gpio : Array of the GPIO number + * @num : The number of gpio + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +void cam_res_mgr_gpio_free_arry(struct device *dev, + const struct gpio *array, size_t num); + +/** + * @brief: Set GPIO power level + * + * Add ref count support for shared GPIOs. + * + * @gpio : The GPIO number + * @value : The power level need to setup + * + * @return Status of operation. Negative in case of error. Zero otherwise. + * -EINVAL will be returned if the gpio can't be found in gpio_res_list. + */ +int cam_res_mgr_gpio_set_value(unsigned int gpio, int value); + +/** + * @brief: Config the shared clk ref count + * + * Config the shared clk ref count.. + * + * @value : get or put the shared clk. + * + * @return None + */ +void cam_res_mgr_shared_clk_config(bool value); + +#endif /* __CAM_RES_MGR_API_H__ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr_private.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr_private.h new file mode 100644 index 0000000000000000000000000000000000000000..48611f6fbd7ecbecdffc11b7230bb0b64d1fe99c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr_private.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef __CAM_RES_MGR_PRIVATE_H__ +#define __CAM_RES_MGR_PRIVATE_H__ + +#include +#include +#include "cam_soc_util.h" + +#define MAX_SHARED_GPIO_SIZE 16 + +/* pinctrl states name */ +#define CAM_RES_MGR_SLEEP "cam_res_mgr_suspend" +#define CAM_RES_MGR_DEFAULT "cam_res_mgr_default" + +/** + * enum pinctrl_status - Enum for pinctrl status + */ +enum pinctrl_status { + PINCTRL_STATUS_GOT = 0, + PINCTRL_STATUS_ACTIVE, + PINCTRL_STATUS_SUSPEND, + PINCTRL_STATUS_PUT, +}; + +/** + * struct cam_dev_res + * + * @list : List member used to append this node to a dev list + * @dev : Device pointer associated with device + */ +struct cam_dev_res { + struct list_head list; + struct device *dev; +}; + +/** + * struct cam_gpio_res + * + * @list : List member used to append this node to a gpio list + * @dev_list : List the device which request this gpio + * @gpio : Gpio value + * @power_on_count : Record the power on times of this gpio + */ +struct cam_gpio_res { + struct list_head list; + struct list_head dev_list; + unsigned int gpio; + int power_on_count; +}; + +/** + * struct cam_pinctrl_res + * + * @list : List member used to append this node to a linked list + * @name : Pointer to the flash trigger's name. + * @trigger : Pointer to the flash trigger + */ +struct cam_flash_res { + struct list_head list; + const char *name; + struct led_trigger *trigger; +}; + +/** + * struct cam_res_mgr_dt + * + * @shared_gpio : Shared gpios list in the device tree + * @num_shared_gpio : The number of shared gpio + * @pinctrl_info : Pinctrl information + */ +struct cam_res_mgr_dt { + uint shared_gpio[MAX_SHARED_GPIO_SIZE]; + int num_shared_gpio; + struct cam_soc_pinctrl_info pinctrl_info; +}; + +/** + * struct cam_pinctrl_res + * + * @dev : Pointer to the device + * @dt : Device tree resource + * @shared_gpio_enabled : The flag to indicate if support shared gpio + * @pstatus : Shared pinctrl status + * @gpio_res_list : List head of the gpio resource + * @flash_res_list : List head of the flash resource + * @gpio_res_lock : GPIO resource lock + * @flash_res_lock : Flash resource lock + * @clk_res_lock : Clk resource lock + */ +struct cam_res_mgr { + struct device *dev; + struct cam_res_mgr_dt dt; + + bool shared_gpio_enabled; + enum pinctrl_status pstatus; + + uint shared_clk_ref_count; + + struct list_head gpio_res_list; + struct list_head flash_res_list; + struct mutex gpio_res_lock; + struct mutex flash_res_lock; + struct mutex clk_res_lock; +}; + +#endif /* __CAM_RES_MGR_PRIVATE_H__ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..3fefb656acc820ee1b7db936d75276e1a00f101b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_dev.o cam_sensor_core.o cam_sensor_soc.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c new file mode 100644 index 0000000000000000000000000000000000000000..8f454f1a24f86b292a8111e22181ca9bca1ff558 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -0,0 +1,1394 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include "cam_sensor_core.h" +#include "cam_sensor_util.h" +#include "cam_soc_util.h" +#include "cam_trace.h" +#include "cam_common_util.h" +#include "cam_packet_util.h" + + +static void cam_sensor_update_req_mgr( + struct cam_sensor_ctrl_t *s_ctrl, + struct cam_packet *csl_packet) +{ + struct cam_req_mgr_add_request add_req; + + add_req.link_hdl = s_ctrl->bridge_intf.link_hdl; + add_req.req_id = csl_packet->header.request_id; + CAM_DBG(CAM_SENSOR, " Rxed Req Id: %lld", + csl_packet->header.request_id); + add_req.dev_hdl = s_ctrl->bridge_intf.device_hdl; + add_req.skip_before_applying = 0; + if (s_ctrl->bridge_intf.crm_cb && + s_ctrl->bridge_intf.crm_cb->add_req) + s_ctrl->bridge_intf.crm_cb->add_req(&add_req); + + CAM_DBG(CAM_SENSOR, " add req to req mgr: %lld", + add_req.req_id); +} + +static void cam_sensor_release_stream_rsc( + struct cam_sensor_ctrl_t *s_ctrl) +{ + struct i2c_settings_array *i2c_set = NULL; + int rc; + + i2c_set = &(s_ctrl->i2c_data.streamoff_settings); + if (i2c_set->is_settings_valid == 1) { + i2c_set->is_settings_valid = -1; + rc = delete_request(i2c_set); + if (rc < 0) + CAM_ERR(CAM_SENSOR, + "failed while deleting Streamoff settings"); + } + + i2c_set = &(s_ctrl->i2c_data.streamon_settings); + if (i2c_set->is_settings_valid == 1) { + i2c_set->is_settings_valid = -1; + rc = delete_request(i2c_set); + if (rc < 0) + CAM_ERR(CAM_SENSOR, + "failed while deleting Streamon settings"); + } +} + +static void cam_sensor_release_per_frame_resource( + struct cam_sensor_ctrl_t *s_ctrl) +{ + struct i2c_settings_array *i2c_set = NULL; + int i, rc; + + if (s_ctrl->i2c_data.per_frame != NULL) { + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { + i2c_set = &(s_ctrl->i2c_data.per_frame[i]); + if (i2c_set->is_settings_valid == 1) { + i2c_set->is_settings_valid = -1; + rc = delete_request(i2c_set); + if (rc < 0) + CAM_ERR(CAM_SENSOR, + "delete request: %lld rc: %d", + i2c_set->request_id, rc); + } + } + } +} + +static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, + void *arg) +{ + int32_t rc = 0; + uintptr_t generic_ptr; + struct cam_control *ioctl_ctrl = NULL; + struct cam_packet *csl_packet = NULL; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct cam_buf_io_cfg *io_cfg = NULL; + struct i2c_settings_array *i2c_reg_settings = NULL; + size_t len_of_buff = 0; + size_t remain_len = 0; + uint32_t *offset = NULL; + struct cam_config_dev_cmd config; + struct i2c_data_settings *i2c_data = NULL; + + ioctl_ctrl = (struct cam_control *)arg; + + if (ioctl_ctrl->handle_type != CAM_HANDLE_USER_POINTER) { + CAM_ERR(CAM_SENSOR, "Invalid Handle Type"); + return -EINVAL; + } + + if (copy_from_user(&config, + u64_to_user_ptr(ioctl_ctrl->handle), + sizeof(config))) + return -EFAULT; + + rc = cam_mem_get_cpu_buf( + config.packet_handle, + &generic_ptr, + &len_of_buff); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Failed in getting the packet: %d", rc); + return rc; + } + + remain_len = len_of_buff; + if ((sizeof(struct cam_packet) > len_of_buff) || + ((size_t)config.offset >= len_of_buff - + sizeof(struct cam_packet))) { + CAM_ERR(CAM_SENSOR, + "Inval cam_packet strut size: %zu, len_of_buff: %zu", + sizeof(struct cam_packet), len_of_buff); + rc = -EINVAL; + goto end; + } + + remain_len -= (size_t)config.offset; + csl_packet = (struct cam_packet *)(generic_ptr + + (uint32_t)config.offset); + + if ((csl_packet == NULL) || cam_packet_util_validate_packet(csl_packet, + remain_len)) { + CAM_ERR(CAM_SENSOR, "Invalid packet params"); + rc = -EINVAL; + goto end; + + } + + if ((csl_packet->header.op_code & 0xFFFFFF) != + CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG && + csl_packet->header.request_id <= s_ctrl->last_flush_req + && s_ctrl->last_flush_req != 0) { + CAM_ERR(CAM_SENSOR, + "reject request %lld, last request to flush %u", + csl_packet->header.request_id, s_ctrl->last_flush_req); + rc = -EINVAL; + goto end; + } + + if (csl_packet->header.request_id > s_ctrl->last_flush_req) + s_ctrl->last_flush_req = 0; + + i2c_data = &(s_ctrl->i2c_data); + CAM_DBG(CAM_SENSOR, "Header OpCode: %d", csl_packet->header.op_code); + switch (csl_packet->header.op_code & 0xFFFFFF) { + case CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG: { + i2c_reg_settings = &i2c_data->init_settings; + i2c_reg_settings->request_id = 0; + i2c_reg_settings->is_settings_valid = 1; + break; + } + case CAM_SENSOR_PACKET_OPCODE_SENSOR_CONFIG: { + i2c_reg_settings = &i2c_data->config_settings; + i2c_reg_settings->request_id = 0; + i2c_reg_settings->is_settings_valid = 1; + break; + } + case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON: { + if (s_ctrl->streamon_count > 0) + goto end; + + s_ctrl->streamon_count = s_ctrl->streamon_count + 1; + i2c_reg_settings = &i2c_data->streamon_settings; + i2c_reg_settings->request_id = 0; + i2c_reg_settings->is_settings_valid = 1; + break; + } + case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF: { + if (s_ctrl->streamoff_count > 0) + goto end; + + s_ctrl->streamoff_count = s_ctrl->streamoff_count + 1; + i2c_reg_settings = &i2c_data->streamoff_settings; + i2c_reg_settings->request_id = 0; + i2c_reg_settings->is_settings_valid = 1; + break; + } + case CAM_SENSOR_PACKET_OPCODE_SENSOR_READ: { + i2c_reg_settings = &(i2c_data->read_settings); + i2c_reg_settings->request_id = 0; + i2c_reg_settings->is_settings_valid = 1; + + CAM_DBG(CAM_SENSOR, "number of IO configs: %d:", + csl_packet->num_io_configs); + if (csl_packet->num_io_configs == 0) { + CAM_ERR(CAM_SENSOR, "No I/O configs to process"); + goto end; + } + + io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) + &csl_packet->payload + + csl_packet->io_configs_offset); + + if (io_cfg == NULL) { + CAM_ERR(CAM_SENSOR, "I/O config is invalid(NULL)"); + goto end; + } + break; + } + case CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE: { + if ((s_ctrl->sensor_state == CAM_SENSOR_INIT) || + (s_ctrl->sensor_state == CAM_SENSOR_ACQUIRE)) { + CAM_WARN(CAM_SENSOR, + "Rxed Update packets without linking"); + goto end; + } + + i2c_reg_settings = + &i2c_data->per_frame[csl_packet->header.request_id % + MAX_PER_FRAME_ARRAY]; + CAM_DBG(CAM_SENSOR, "Received Packet: %lld req: %lld", + csl_packet->header.request_id % MAX_PER_FRAME_ARRAY, + csl_packet->header.request_id); + if (i2c_reg_settings->is_settings_valid == 1) { + CAM_ERR(CAM_SENSOR, + "Already some pkt in offset req : %lld", + csl_packet->header.request_id); + /* + * Update req mgr even in case of failure. + * This will help not to wait indefinitely + * and freeze. If this log is triggered then + * fix it. + */ + cam_sensor_update_req_mgr(s_ctrl, csl_packet); + goto end; + } + break; + } + case CAM_SENSOR_PACKET_OPCODE_SENSOR_NOP: { + if ((s_ctrl->sensor_state == CAM_SENSOR_INIT) || + (s_ctrl->sensor_state == CAM_SENSOR_ACQUIRE)) { + CAM_WARN(CAM_SENSOR, + "Rxed NOP packets without linking"); + goto end; + } + + cam_sensor_update_req_mgr(s_ctrl, csl_packet); + goto end; + } + default: + CAM_ERR(CAM_SENSOR, "Invalid Packet Header"); + rc = -EINVAL; + goto end; + } + + offset = (uint32_t *)&csl_packet->payload; + offset += csl_packet->cmd_buf_offset / 4; + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + + rc = cam_sensor_i2c_command_parser(&s_ctrl->io_master_info, + i2c_reg_settings, cmd_desc, 1, io_cfg); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Fail parsing I2C Pkt: %d", rc); + goto end; + } + + if ((csl_packet->header.op_code & 0xFFFFFF) == + CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE) { + i2c_reg_settings->request_id = + csl_packet->header.request_id; + cam_sensor_update_req_mgr(s_ctrl, csl_packet); + } + +end: + cam_mem_put_cpu_buf(config.packet_handle); + return rc; +} + +static int32_t cam_sensor_i2c_modes_util( + struct camera_io_master *io_master_info, + struct i2c_settings_list *i2c_list) +{ + int32_t rc = 0; + uint32_t i, size; + + if (i2c_list->op_code == CAM_SENSOR_I2C_WRITE_RANDOM) { + rc = camera_io_dev_write(io_master_info, + &(i2c_list->i2c_settings)); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed to random write I2C settings: %d", + rc); + return rc; + } + } else if (i2c_list->op_code == CAM_SENSOR_I2C_WRITE_SEQ) { + rc = camera_io_dev_write_continuous( + io_master_info, + &(i2c_list->i2c_settings), + 0); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed to seq write I2C settings: %d", + rc); + return rc; + } + } else if (i2c_list->op_code == CAM_SENSOR_I2C_WRITE_BURST) { + rc = camera_io_dev_write_continuous( + io_master_info, + &(i2c_list->i2c_settings), + 1); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed to burst write I2C settings: %d", + rc); + return rc; + } + } else if (i2c_list->op_code == CAM_SENSOR_I2C_POLL) { + size = i2c_list->i2c_settings.size; + for (i = 0; i < size; i++) { + rc = camera_io_dev_poll( + io_master_info, + i2c_list->i2c_settings.reg_setting[i].reg_addr, + i2c_list->i2c_settings.reg_setting[i].reg_data, + i2c_list->i2c_settings.reg_setting[i].data_mask, + i2c_list->i2c_settings.addr_type, + i2c_list->i2c_settings.data_type, + i2c_list->i2c_settings.reg_setting[i].delay); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "i2c poll apply setting Fail: %d", rc); + return rc; + } + } + } + + return rc; +} + +int32_t cam_sensor_update_i2c_info(struct cam_cmd_i2c_info *i2c_info, + struct cam_sensor_ctrl_t *s_ctrl) +{ + int32_t rc = 0; + struct cam_sensor_cci_client *cci_client = NULL; + + if (s_ctrl->io_master_info.master_type == CCI_MASTER) { + cci_client = s_ctrl->io_master_info.cci_client; + if (!cci_client) { + CAM_ERR(CAM_SENSOR, "failed: cci_client %pK", + cci_client); + return -EINVAL; + } + cci_client->cci_i2c_master = s_ctrl->cci_i2c_master; + cci_client->sid = i2c_info->slave_addr >> 1; + cci_client->retries = 3; + cci_client->id_map = 0; + cci_client->i2c_freq_mode = i2c_info->i2c_freq_mode; + CAM_DBG(CAM_SENSOR, " Master: %d sid: %d freq_mode: %d", + cci_client->cci_i2c_master, i2c_info->slave_addr, + i2c_info->i2c_freq_mode); + } + + s_ctrl->sensordata->slave_info.sensor_slave_addr = + i2c_info->slave_addr; + return rc; +} + +int32_t cam_sensor_update_slave_info(struct cam_cmd_probe *probe_info, + struct cam_sensor_ctrl_t *s_ctrl) +{ + int32_t rc = 0; + + s_ctrl->sensordata->slave_info.sensor_id_reg_addr = + probe_info->reg_addr; + s_ctrl->sensordata->slave_info.sensor_id = + probe_info->expected_data; + s_ctrl->sensordata->slave_info.sensor_id_mask = + probe_info->data_mask; + /* Userspace passes the pipeline delay in reserved field */ + s_ctrl->pipeline_delay = + probe_info->reserved; + + s_ctrl->sensor_probe_addr_type = probe_info->addr_type; + s_ctrl->sensor_probe_data_type = probe_info->data_type; + CAM_DBG(CAM_SENSOR, + "Sensor Addr: 0x%x sensor_id: 0x%x sensor_mask: 0x%x sensor_pipeline_delay:0x%x", + s_ctrl->sensordata->slave_info.sensor_id_reg_addr, + s_ctrl->sensordata->slave_info.sensor_id, + s_ctrl->sensordata->slave_info.sensor_id_mask, + s_ctrl->pipeline_delay); + return rc; +} + +int32_t cam_handle_cmd_buffers_for_probe(void *cmd_buf, + struct cam_sensor_ctrl_t *s_ctrl, + int32_t cmd_buf_num, uint32_t cmd_buf_length, size_t remain_len) +{ + int32_t rc = 0; + + switch (cmd_buf_num) { + case 0: { + struct cam_cmd_i2c_info *i2c_info = NULL; + struct cam_cmd_probe *probe_info; + + if (remain_len < + (sizeof(struct cam_cmd_i2c_info) + + sizeof(struct cam_cmd_probe))) { + CAM_ERR(CAM_SENSOR, + "not enough buffer for cam_cmd_i2c_info"); + return -EINVAL; + } + i2c_info = (struct cam_cmd_i2c_info *)cmd_buf; + rc = cam_sensor_update_i2c_info(i2c_info, s_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Failed in Updating the i2c Info"); + return rc; + } + probe_info = (struct cam_cmd_probe *) + (cmd_buf + sizeof(struct cam_cmd_i2c_info)); + rc = cam_sensor_update_slave_info(probe_info, s_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Updating the slave Info"); + return rc; + } + cmd_buf = probe_info; + } + break; + case 1: { + rc = cam_sensor_update_power_settings(cmd_buf, + cmd_buf_length, &s_ctrl->sensordata->power_info, + remain_len); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed in updating power settings"); + return rc; + } + } + break; + default: + CAM_ERR(CAM_SENSOR, "Invalid command buffer"); + break; + } + return rc; +} + +int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) +{ + int rc = 0, i; + uint32_t *cmd_buf; + void *ptr; + size_t len; + struct cam_packet *pkt = NULL; + struct cam_cmd_buf_desc *cmd_desc = NULL; + uintptr_t cmd_buf1 = 0; + uintptr_t packet = 0; + size_t remain_len = 0; + + rc = cam_mem_get_cpu_buf(handle, + &packet, &len); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Failed to get the command Buffer"); + return -EINVAL; + } + + pkt = (struct cam_packet *)packet; + if (pkt == NULL) { + CAM_ERR(CAM_SENSOR, "packet pos is invalid"); + rc = -EINVAL; + goto end; + } + + if ((len < sizeof(struct cam_packet)) || + (pkt->cmd_buf_offset >= (len - sizeof(struct cam_packet)))) { + CAM_ERR(CAM_SENSOR, "Not enough buf provided"); + rc = -EINVAL; + goto end; + } + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *)&pkt->payload + pkt->cmd_buf_offset/4); + if (cmd_desc == NULL) { + CAM_ERR(CAM_SENSOR, "command descriptor pos is invalid"); + rc = -EINVAL; + goto end; + } + if (pkt->num_cmd_buf != 2) { + CAM_ERR(CAM_SENSOR, "Expected More Command Buffers : %d", + pkt->num_cmd_buf); + rc = -EINVAL; + goto end; + } + + for (i = 0; i < pkt->num_cmd_buf; i++) { + if (!(cmd_desc[i].length)) + continue; + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, + &cmd_buf1, &len); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed to parse the command Buffer Header"); + goto end; + } + if (cmd_desc[i].offset >= len) { + CAM_ERR(CAM_SENSOR, + "offset past length of buffer"); + rc = -EINVAL; + goto end; + } + remain_len = len - cmd_desc[i].offset; + if (cmd_desc[i].length > remain_len) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided for cmd"); + rc = -EINVAL; + goto end; + } + cmd_buf = (uint32_t *)cmd_buf1; + cmd_buf += cmd_desc[i].offset/4; + ptr = (void *) cmd_buf; + + rc = cam_handle_cmd_buffers_for_probe(ptr, s_ctrl, + i, cmd_desc[i].length, remain_len); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed to parse the command Buffer Header"); + goto end; + } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + } + +end: + cam_mem_put_cpu_buf(handle); + return rc; +} + +void cam_sensor_query_cap(struct cam_sensor_ctrl_t *s_ctrl, + struct cam_sensor_query_cap *query_cap) +{ + query_cap->pos_roll = s_ctrl->sensordata->pos_roll; + query_cap->pos_pitch = s_ctrl->sensordata->pos_pitch; + query_cap->pos_yaw = s_ctrl->sensordata->pos_yaw; + query_cap->secure_camera = 0; + query_cap->actuator_slot_id = + s_ctrl->sensordata->subdev_id[SUB_MODULE_ACTUATOR]; + query_cap->csiphy_slot_id = + s_ctrl->sensordata->subdev_id[SUB_MODULE_CSIPHY]; + query_cap->eeprom_slot_id = + s_ctrl->sensordata->subdev_id[SUB_MODULE_EEPROM]; + query_cap->flash_slot_id = + s_ctrl->sensordata->subdev_id[SUB_MODULE_LED_FLASH]; + query_cap->ois_slot_id = + s_ctrl->sensordata->subdev_id[SUB_MODULE_OIS]; + query_cap->slot_info = + s_ctrl->soc_info.index; +} + +static uint16_t cam_sensor_id_by_mask(struct cam_sensor_ctrl_t *s_ctrl, + uint32_t chipid) +{ + uint16_t sensor_id = (uint16_t)(chipid & 0xFFFF); + int16_t sensor_id_mask = s_ctrl->sensordata->slave_info.sensor_id_mask; + + if (!sensor_id_mask) + sensor_id_mask = ~sensor_id_mask; + + sensor_id &= sensor_id_mask; + sensor_id_mask &= -sensor_id_mask; + sensor_id_mask -= 1; + while (sensor_id_mask) { + sensor_id_mask >>= 1; + sensor_id >>= 1; + } + return sensor_id; +} + +void cam_sensor_shutdown(struct cam_sensor_ctrl_t *s_ctrl) +{ + struct cam_sensor_power_ctrl_t *power_info = + &s_ctrl->sensordata->power_info; + int rc = 0; + + if ((s_ctrl->sensor_state == CAM_SENSOR_INIT) && + (s_ctrl->is_probe_succeed == 0)) + return; + + cam_sensor_release_stream_rsc(s_ctrl); + cam_sensor_release_per_frame_resource(s_ctrl); + + if (s_ctrl->sensor_state != CAM_SENSOR_INIT) + cam_sensor_power_down(s_ctrl); + + if (s_ctrl->bridge_intf.device_hdl != -1) { + rc = cam_destroy_device_hdl(s_ctrl->bridge_intf.device_hdl); + if (rc < 0) + CAM_ERR(CAM_SENSOR, + "dhdl already destroyed: rc = %d", rc); + } + + s_ctrl->bridge_intf.device_hdl = -1; + s_ctrl->bridge_intf.link_hdl = -1; + s_ctrl->bridge_intf.session_hdl = -1; + kfree(power_info->power_setting); + kfree(power_info->power_down_setting); + power_info->power_setting = NULL; + power_info->power_down_setting = NULL; + power_info->power_setting_size = 0; + power_info->power_down_setting_size = 0; + s_ctrl->streamon_count = 0; + s_ctrl->streamoff_count = 0; + s_ctrl->is_probe_succeed = 0; + s_ctrl->last_flush_req = 0; + s_ctrl->sensor_state = CAM_SENSOR_INIT; +} + +int cam_sensor_match_id(struct cam_sensor_ctrl_t *s_ctrl) +{ + int rc = 0; + uint32_t chipid = 0; + struct cam_camera_slave_info *slave_info; + + slave_info = &(s_ctrl->sensordata->slave_info); + + if (!slave_info) { + CAM_ERR(CAM_SENSOR, " failed: %pK", + slave_info); + return -EINVAL; + } + + rc = camera_io_dev_read( + &(s_ctrl->io_master_info), + slave_info->sensor_id_reg_addr, + &chipid, + s_ctrl->sensor_probe_addr_type, + s_ctrl->sensor_probe_data_type); + + CAM_DBG(CAM_SENSOR, "read id: 0x%x expected id 0x%x:", + chipid, slave_info->sensor_id); + + if (cam_sensor_id_by_mask(s_ctrl, chipid) != slave_info->sensor_id) { + CAM_WARN(CAM_SENSOR, "read id: 0x%x expected id 0x%x:", + chipid, slave_info->sensor_id); + return -ENODEV; + } + return rc; +} + +int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, + void *arg) +{ + int rc = 0, pkt_opcode = 0; + struct cam_control *cmd = (struct cam_control *)arg; + struct cam_sensor_power_ctrl_t *power_info = + &s_ctrl->sensordata->power_info; + if (!s_ctrl || !arg) { + CAM_ERR(CAM_SENSOR, "s_ctrl is NULL"); + return -EINVAL; + } + + if (cmd->op_code != CAM_SENSOR_PROBE_CMD) { + if (cmd->handle_type != CAM_HANDLE_USER_POINTER) { + CAM_ERR(CAM_SENSOR, "Invalid handle type: %d", + cmd->handle_type); + return -EINVAL; + } + } + + mutex_lock(&(s_ctrl->cam_sensor_mutex)); + switch (cmd->op_code) { + case CAM_SENSOR_PROBE_CMD: { + if (s_ctrl->is_probe_succeed == 1) { + CAM_ERR(CAM_SENSOR, + "Already Sensor Probed in the slot"); + break; + } + + if (cmd->handle_type == + CAM_HANDLE_MEM_HANDLE) { + rc = cam_handle_mem_ptr(cmd->handle, s_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Get Buffer Handle Failed"); + goto release_mutex; + } + } else { + CAM_ERR(CAM_SENSOR, "Invalid Command Type: %d", + cmd->handle_type); + rc = -EINVAL; + goto release_mutex; + } + + /* Parse and fill vreg params for powerup settings */ + rc = msm_camera_fill_vreg_params( + &s_ctrl->soc_info, + s_ctrl->sensordata->power_info.power_setting, + s_ctrl->sensordata->power_info.power_setting_size); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Fail in filling vreg params for PUP rc %d", + rc); + goto free_power_settings; + } + + /* Parse and fill vreg params for powerdown settings*/ + rc = msm_camera_fill_vreg_params( + &s_ctrl->soc_info, + s_ctrl->sensordata->power_info.power_down_setting, + s_ctrl->sensordata->power_info.power_down_setting_size); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Fail in filling vreg params for PDOWN rc %d", + rc); + goto free_power_settings; + } + + /* Power up and probe sensor */ + rc = cam_sensor_power_up(s_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "power up failed"); + goto free_power_settings; + } + + /* Match sensor ID */ + rc = cam_sensor_match_id(s_ctrl); + if (rc < 0) { + cam_sensor_power_down(s_ctrl); + msleep(20); + goto free_power_settings; + } + + CAM_INFO(CAM_SENSOR, + "Probe success,slot:%d,slave_addr:0x%x,sensor_id:0x%x", + s_ctrl->soc_info.index, + s_ctrl->sensordata->slave_info.sensor_slave_addr, + s_ctrl->sensordata->slave_info.sensor_id); + + rc = cam_sensor_power_down(s_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "fail in Sensor Power Down"); + goto free_power_settings; + } + /* + * Set probe succeeded flag to 1 so that no other camera shall + * probed on this slot + */ + s_ctrl->is_probe_succeed = 1; + s_ctrl->sensor_state = CAM_SENSOR_INIT; + } + break; + case CAM_ACQUIRE_DEV: { + struct cam_sensor_acquire_dev sensor_acq_dev; + struct cam_create_dev_hdl bridge_params; + + if ((s_ctrl->is_probe_succeed == 0) || + (s_ctrl->sensor_state != CAM_SENSOR_INIT)) { + CAM_WARN(CAM_SENSOR, + "Not in right state to aquire %d", + s_ctrl->sensor_state); + rc = -EINVAL; + goto release_mutex; + } + + if (s_ctrl->bridge_intf.device_hdl != -1) { + CAM_ERR(CAM_SENSOR, "Device is already acquired"); + rc = -EINVAL; + goto release_mutex; + } + rc = copy_from_user(&sensor_acq_dev, + u64_to_user_ptr(cmd->handle), + sizeof(sensor_acq_dev)); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Failed Copying from user"); + goto release_mutex; + } + + bridge_params.session_hdl = sensor_acq_dev.session_handle; + bridge_params.ops = &s_ctrl->bridge_intf.ops; + bridge_params.v4l2_sub_dev_flag = 0; + bridge_params.media_entity_flag = 0; + bridge_params.priv = s_ctrl; + bridge_params.dev_id = CAM_SENSOR; + + sensor_acq_dev.device_handle = + cam_create_device_hdl(&bridge_params); + if (sensor_acq_dev.device_handle <= 0) { + rc = -EFAULT; + CAM_ERR(CAM_SENSOR, "Can not create device handle"); + goto release_mutex; + } + s_ctrl->bridge_intf.device_hdl = sensor_acq_dev.device_handle; + s_ctrl->bridge_intf.session_hdl = sensor_acq_dev.session_handle; + + CAM_DBG(CAM_SENSOR, "Device Handle: %d", + sensor_acq_dev.device_handle); + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &sensor_acq_dev, + sizeof(struct cam_sensor_acquire_dev))) { + CAM_ERR(CAM_SENSOR, "Failed Copy to User"); + rc = -EFAULT; + goto release_mutex; + } + + rc = cam_sensor_power_up(s_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Sensor Power up failed"); + goto release_mutex; + } + + s_ctrl->sensor_state = CAM_SENSOR_ACQUIRE; + s_ctrl->last_flush_req = 0; + CAM_INFO(CAM_SENSOR, + "CAM_ACQUIRE_DEV Success, sensor_id:0x%x,sensor_slave_addr:0x%x", + s_ctrl->sensordata->slave_info.sensor_id, + s_ctrl->sensordata->slave_info.sensor_slave_addr); + } + break; + case CAM_RELEASE_DEV: { + if ((s_ctrl->sensor_state == CAM_SENSOR_INIT) || + (s_ctrl->sensor_state == CAM_SENSOR_START)) { + rc = -EINVAL; + CAM_WARN(CAM_SENSOR, + "Not in right state to release : %d", + s_ctrl->sensor_state); + goto release_mutex; + } + + if (s_ctrl->bridge_intf.link_hdl != -1) { + CAM_ERR(CAM_SENSOR, + "Device [%d] still active on link 0x%x", + s_ctrl->sensor_state, + s_ctrl->bridge_intf.link_hdl); + rc = -EAGAIN; + goto release_mutex; + } + + rc = cam_sensor_power_down(s_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Sensor Power Down failed"); + goto release_mutex; + } + + cam_sensor_release_per_frame_resource(s_ctrl); + cam_sensor_release_stream_rsc(s_ctrl); + if (s_ctrl->bridge_intf.device_hdl == -1) { + CAM_ERR(CAM_SENSOR, + "Invalid Handles: link hdl: %d device hdl: %d", + s_ctrl->bridge_intf.device_hdl, + s_ctrl->bridge_intf.link_hdl); + rc = -EINVAL; + goto release_mutex; + } + rc = cam_destroy_device_hdl(s_ctrl->bridge_intf.device_hdl); + if (rc < 0) + CAM_ERR(CAM_SENSOR, + "failed in destroying the device hdl"); + s_ctrl->bridge_intf.device_hdl = -1; + s_ctrl->bridge_intf.link_hdl = -1; + s_ctrl->bridge_intf.session_hdl = -1; + + s_ctrl->sensor_state = CAM_SENSOR_INIT; + CAM_INFO(CAM_SENSOR, + "CAM_RELEASE_DEV Success, sensor_id:0x%x,sensor_slave_addr:0x%x", + s_ctrl->sensordata->slave_info.sensor_id, + s_ctrl->sensordata->slave_info.sensor_slave_addr); + s_ctrl->streamon_count = 0; + s_ctrl->streamoff_count = 0; + s_ctrl->last_flush_req = 0; + } + break; + case CAM_QUERY_CAP: { + struct cam_sensor_query_cap sensor_cap; + + cam_sensor_query_cap(s_ctrl, &sensor_cap); + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &sensor_cap, sizeof(struct cam_sensor_query_cap))) { + CAM_ERR(CAM_SENSOR, "Failed Copy to User"); + rc = -EFAULT; + goto release_mutex; + } + break; + } + case CAM_START_DEV: { + if ((s_ctrl->sensor_state == CAM_SENSOR_INIT) || + (s_ctrl->sensor_state == CAM_SENSOR_START)) { + rc = -EINVAL; + CAM_WARN(CAM_SENSOR, + "Not in right state to start : %d", + s_ctrl->sensor_state); + goto release_mutex; + } + + if (s_ctrl->i2c_data.streamon_settings.is_settings_valid && + (s_ctrl->i2c_data.streamon_settings.request_id == 0)) { + rc = cam_sensor_apply_settings(s_ctrl, 0, + CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "cannot apply streamon settings"); + goto release_mutex; + } + } + s_ctrl->sensor_state = CAM_SENSOR_START; + CAM_INFO(CAM_SENSOR, + "CAM_START_DEV Success, sensor_id:0x%x,sensor_slave_addr:0x%x", + s_ctrl->sensordata->slave_info.sensor_id, + s_ctrl->sensordata->slave_info.sensor_slave_addr); + } + break; + case CAM_STOP_DEV: { + if (s_ctrl->sensor_state != CAM_SENSOR_START) { + rc = -EINVAL; + CAM_WARN(CAM_SENSOR, + "Not in right state to stop : %d", + s_ctrl->sensor_state); + goto release_mutex; + } + + if (s_ctrl->i2c_data.streamoff_settings.is_settings_valid && + (s_ctrl->i2c_data.streamoff_settings.request_id == 0)) { + rc = cam_sensor_apply_settings(s_ctrl, 0, + CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "cannot apply streamoff settings"); + } + } + + cam_sensor_release_per_frame_resource(s_ctrl); + s_ctrl->last_flush_req = 0; + s_ctrl->sensor_state = CAM_SENSOR_ACQUIRE; + CAM_INFO(CAM_SENSOR, + "CAM_STOP_DEV Success, sensor_id:0x%x,sensor_slave_addr:0x%x", + s_ctrl->sensordata->slave_info.sensor_id, + s_ctrl->sensordata->slave_info.sensor_slave_addr); + } + break; + case CAM_CONFIG_DEV: { + rc = cam_sensor_i2c_pkt_parse(s_ctrl, arg); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Failed i2c pkt parse: %d", rc); + goto release_mutex; + } + if (s_ctrl->i2c_data.init_settings.is_settings_valid && + (s_ctrl->i2c_data.init_settings.request_id == 0)) { + + pkt_opcode = + CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG; + rc = cam_sensor_apply_settings(s_ctrl, 0, + pkt_opcode); + + if ((rc == -EAGAIN) && + (s_ctrl->io_master_info.master_type == CCI_MASTER)) { + /* If CCI hardware is resetting we need to wait + * for sometime before reapply + */ + CAM_WARN(CAM_SENSOR, + "Reapplying the Init settings due to cci hw reset"); + usleep_range(1000, 1010); + rc = cam_sensor_apply_settings(s_ctrl, 0, + pkt_opcode); + } + s_ctrl->i2c_data.init_settings.request_id = -1; + + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "cannot apply init settings rc= %d", + rc); + delete_request(&s_ctrl->i2c_data.init_settings); + goto release_mutex; + } + rc = delete_request(&s_ctrl->i2c_data.init_settings); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Fail in deleting the Init settings"); + goto release_mutex; + } + } + + if (s_ctrl->i2c_data.config_settings.is_settings_valid && + (s_ctrl->i2c_data.config_settings.request_id == 0)) { + rc = cam_sensor_apply_settings(s_ctrl, 0, + CAM_SENSOR_PACKET_OPCODE_SENSOR_CONFIG); + + s_ctrl->i2c_data.config_settings.request_id = -1; + + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "cannot apply config settings"); + delete_request( + &s_ctrl->i2c_data.config_settings); + goto release_mutex; + } + rc = delete_request(&s_ctrl->i2c_data.config_settings); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Fail in deleting the config settings"); + goto release_mutex; + } + s_ctrl->sensor_state = CAM_SENSOR_CONFIG; + } + + if (s_ctrl->i2c_data.read_settings.is_settings_valid) { + rc = cam_sensor_i2c_read_data( + &s_ctrl->i2c_data.read_settings, + &s_ctrl->io_master_info); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "cannot read data: %d", rc); + delete_request(&s_ctrl->i2c_data.read_settings); + goto release_mutex; + } + rc = delete_request( + &s_ctrl->i2c_data.read_settings); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Fail in deleting the read settings"); + goto release_mutex; + } + } + } + break; + default: + CAM_ERR(CAM_SENSOR, "Invalid Opcode: %d", cmd->op_code); + rc = -EINVAL; + goto release_mutex; + } + +release_mutex: + mutex_unlock(&(s_ctrl->cam_sensor_mutex)); + return rc; + +free_power_settings: + kfree(power_info->power_setting); + kfree(power_info->power_down_setting); + power_info->power_setting = NULL; + power_info->power_down_setting = NULL; + power_info->power_down_setting_size = 0; + power_info->power_setting_size = 0; + mutex_unlock(&(s_ctrl->cam_sensor_mutex)); + return rc; +} + +int cam_sensor_publish_dev_info(struct cam_req_mgr_device_info *info) +{ + int rc = 0; + struct cam_sensor_ctrl_t *s_ctrl = NULL; + + if (!info) + return -EINVAL; + + s_ctrl = (struct cam_sensor_ctrl_t *) + cam_get_device_priv(info->dev_hdl); + + if (!s_ctrl) { + CAM_ERR(CAM_SENSOR, "Device data is NULL"); + return -EINVAL; + } + + info->dev_id = CAM_REQ_MGR_DEVICE_SENSOR; + strlcpy(info->name, CAM_SENSOR_NAME, sizeof(info->name)); + if (s_ctrl->pipeline_delay >= 1 && s_ctrl->pipeline_delay <= 3) + info->p_delay = s_ctrl->pipeline_delay; + else + info->p_delay = 2; + info->trigger = CAM_TRIGGER_POINT_SOF; + + return rc; +} + +int cam_sensor_establish_link(struct cam_req_mgr_core_dev_link_setup *link) +{ + struct cam_sensor_ctrl_t *s_ctrl = NULL; + + if (!link) + return -EINVAL; + + s_ctrl = (struct cam_sensor_ctrl_t *) + cam_get_device_priv(link->dev_hdl); + if (!s_ctrl) { + CAM_ERR(CAM_SENSOR, "Device data is NULL"); + return -EINVAL; + } + + mutex_lock(&s_ctrl->cam_sensor_mutex); + if (link->link_enable) { + s_ctrl->bridge_intf.link_hdl = link->link_hdl; + s_ctrl->bridge_intf.crm_cb = link->crm_cb; + } else { + s_ctrl->bridge_intf.link_hdl = -1; + s_ctrl->bridge_intf.crm_cb = NULL; + } + mutex_unlock(&s_ctrl->cam_sensor_mutex); + + return 0; +} + +int cam_sensor_power(struct v4l2_subdev *sd, int on) +{ + struct cam_sensor_ctrl_t *s_ctrl = v4l2_get_subdevdata(sd); + + mutex_lock(&(s_ctrl->cam_sensor_mutex)); + if (!on && s_ctrl->sensor_state == CAM_SENSOR_START) { + cam_sensor_power_down(s_ctrl); + s_ctrl->sensor_state = CAM_SENSOR_ACQUIRE; + } + mutex_unlock(&(s_ctrl->cam_sensor_mutex)); + + return 0; +} + +int cam_sensor_power_up(struct cam_sensor_ctrl_t *s_ctrl) +{ + int rc; + struct cam_sensor_power_ctrl_t *power_info; + struct cam_camera_slave_info *slave_info; + struct cam_hw_soc_info *soc_info = + &s_ctrl->soc_info; + + if (!s_ctrl) { + CAM_ERR(CAM_SENSOR, "failed: %pK", s_ctrl); + return -EINVAL; + } + + power_info = &s_ctrl->sensordata->power_info; + slave_info = &(s_ctrl->sensordata->slave_info); + + if (!power_info || !slave_info) { + CAM_ERR(CAM_SENSOR, "failed: %pK %pK", power_info, slave_info); + return -EINVAL; + } + + if (s_ctrl->bob_pwm_switch) { + rc = cam_sensor_bob_pwm_mode_switch(soc_info, + s_ctrl->bob_reg_index, true); + if (rc) { + CAM_WARN(CAM_SENSOR, + "BoB PWM setup failed rc: %d", rc); + rc = 0; + } + } + + rc = cam_sensor_core_power_up(power_info, soc_info); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "power up the core is failed:%d", rc); + return rc; + } + + rc = camera_io_init(&(s_ctrl->io_master_info)); + if (rc < 0) + CAM_ERR(CAM_SENSOR, "cci_init failed: rc: %d", rc); + + return rc; +} + +int cam_sensor_power_down(struct cam_sensor_ctrl_t *s_ctrl) +{ + struct cam_sensor_power_ctrl_t *power_info; + struct cam_hw_soc_info *soc_info; + int rc = 0; + + if (!s_ctrl) { + CAM_ERR(CAM_SENSOR, "failed: s_ctrl %pK", s_ctrl); + return -EINVAL; + } + + power_info = &s_ctrl->sensordata->power_info; + soc_info = &s_ctrl->soc_info; + + if (!power_info) { + CAM_ERR(CAM_SENSOR, "failed: power_info %pK", power_info); + return -EINVAL; + } + rc = cam_sensor_util_power_down(power_info, soc_info); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "power down the core is failed:%d", rc); + return rc; + } + + if (s_ctrl->bob_pwm_switch) { + rc = cam_sensor_bob_pwm_mode_switch(soc_info, + s_ctrl->bob_reg_index, false); + if (rc) { + CAM_WARN(CAM_SENSOR, + "BoB PWM setup failed rc: %d", rc); + rc = 0; + } + } + + camera_io_release(&(s_ctrl->io_master_info)); + + return rc; +} + +int cam_sensor_apply_settings(struct cam_sensor_ctrl_t *s_ctrl, + int64_t req_id, enum cam_sensor_packet_opcodes opcode) +{ + int rc = 0, offset, i; + uint64_t top = 0, del_req_id = 0; + struct i2c_settings_array *i2c_set = NULL; + struct i2c_settings_list *i2c_list; + + if (req_id == 0) { + switch (opcode) { + case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON: { + i2c_set = &s_ctrl->i2c_data.streamon_settings; + break; + } + case CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG: { + i2c_set = &s_ctrl->i2c_data.init_settings; + break; + } + case CAM_SENSOR_PACKET_OPCODE_SENSOR_CONFIG: { + i2c_set = &s_ctrl->i2c_data.config_settings; + break; + } + case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF: { + i2c_set = &s_ctrl->i2c_data.streamoff_settings; + break; + } + case CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE: + case CAM_SENSOR_PACKET_OPCODE_SENSOR_PROBE: + default: + return 0; + } + if (i2c_set->is_settings_valid == 1) { + list_for_each_entry(i2c_list, + &(i2c_set->list_head), list) { + rc = cam_sensor_i2c_modes_util( + &(s_ctrl->io_master_info), + i2c_list); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed to apply settings: %d", + rc); + return rc; + } + } + } + } else { + offset = req_id % MAX_PER_FRAME_ARRAY; + i2c_set = &(s_ctrl->i2c_data.per_frame[offset]); + if (i2c_set->is_settings_valid == 1 && + i2c_set->request_id == req_id) { + list_for_each_entry(i2c_list, + &(i2c_set->list_head), list) { + rc = cam_sensor_i2c_modes_util( + &(s_ctrl->io_master_info), + i2c_list); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed to apply settings: %d", + rc); + return rc; + } + } + } else { + CAM_DBG(CAM_SENSOR, + "Invalid/NOP request to apply: %lld", req_id); + } + + /* Change the logic dynamically */ + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { + if ((req_id >= + s_ctrl->i2c_data.per_frame[i].request_id) && + (top < + s_ctrl->i2c_data.per_frame[i].request_id) && + (s_ctrl->i2c_data.per_frame[i].is_settings_valid + == 1)) { + del_req_id = top; + top = s_ctrl->i2c_data.per_frame[i].request_id; + } + } + + if (top < req_id) { + if ((((top % MAX_PER_FRAME_ARRAY) - (req_id % + MAX_PER_FRAME_ARRAY)) >= BATCH_SIZE_MAX) || + (((top % MAX_PER_FRAME_ARRAY) - (req_id % + MAX_PER_FRAME_ARRAY)) <= -BATCH_SIZE_MAX)) + del_req_id = req_id; + } + + if (!del_req_id) + return rc; + + CAM_DBG(CAM_SENSOR, "top: %llu, del_req_id:%llu", + top, del_req_id); + + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { + if ((del_req_id > + s_ctrl->i2c_data.per_frame[i].request_id) && ( + s_ctrl->i2c_data.per_frame[i].is_settings_valid + == 1)) { + s_ctrl->i2c_data.per_frame[i].request_id = 0; + rc = delete_request( + &(s_ctrl->i2c_data.per_frame[i])); + if (rc < 0) + CAM_ERR(CAM_SENSOR, + "Delete request Fail:%lld rc:%d", + del_req_id, rc); + } + } + } + + return rc; +} + +int32_t cam_sensor_apply_request(struct cam_req_mgr_apply_request *apply) +{ + int32_t rc = 0; + struct cam_sensor_ctrl_t *s_ctrl = NULL; + + if (!apply) + return -EINVAL; + + s_ctrl = (struct cam_sensor_ctrl_t *) + cam_get_device_priv(apply->dev_hdl); + if (!s_ctrl) { + CAM_ERR(CAM_SENSOR, "Device data is NULL"); + return -EINVAL; + } + CAM_DBG(CAM_REQ, " Sensor update req id: %lld", apply->request_id); + trace_cam_apply_req("Sensor", apply->request_id); + mutex_lock(&(s_ctrl->cam_sensor_mutex)); + rc = cam_sensor_apply_settings(s_ctrl, apply->request_id, + CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE); + mutex_unlock(&(s_ctrl->cam_sensor_mutex)); + return rc; +} + +int32_t cam_sensor_flush_request(struct cam_req_mgr_flush_request *flush_req) +{ + int32_t rc = 0, i; + uint32_t cancel_req_id_found = 0; + struct cam_sensor_ctrl_t *s_ctrl = NULL; + struct i2c_settings_array *i2c_set = NULL; + + if (!flush_req) + return -EINVAL; + + s_ctrl = (struct cam_sensor_ctrl_t *) + cam_get_device_priv(flush_req->dev_hdl); + if (!s_ctrl) { + CAM_ERR(CAM_SENSOR, "Device data is NULL"); + return -EINVAL; + } + + mutex_lock(&(s_ctrl->cam_sensor_mutex)); + if ((s_ctrl->sensor_state != CAM_SENSOR_START) && + (s_ctrl->sensor_state != CAM_SENSOR_CONFIG)) { + mutex_unlock(&(s_ctrl->cam_sensor_mutex)); + return rc; + } + + if (s_ctrl->i2c_data.per_frame == NULL) { + CAM_ERR(CAM_SENSOR, "i2c frame data is NULL"); + mutex_unlock(&(s_ctrl->cam_sensor_mutex)); + return -EINVAL; + } + + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) { + s_ctrl->last_flush_req = flush_req->req_id; + CAM_DBG(CAM_SENSOR, "last reqest to flush is %lld", + flush_req->req_id); + } + + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { + i2c_set = &(s_ctrl->i2c_data.per_frame[i]); + + if ((flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ) + && (i2c_set->request_id != flush_req->req_id)) + continue; + + if (i2c_set->is_settings_valid == 1) { + rc = delete_request(i2c_set); + if (rc < 0) + CAM_ERR(CAM_SENSOR, + "delete request: %lld rc: %d", + i2c_set->request_id, rc); + + if (flush_req->type == + CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ) { + cancel_req_id_found = 1; + break; + } + } + } + + if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ && + !cancel_req_id_found) + CAM_DBG(CAM_SENSOR, + "Flush request id:%lld not found in the pending list", + flush_req->req_id); + mutex_unlock(&(s_ctrl->cam_sensor_mutex)); + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.h new file mode 100644 index 0000000000000000000000000000000000000000..b7a5923a6a70079243fbe9f1de7b381a31960233 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_SENSOR_CORE_H_ +#define _CAM_SENSOR_CORE_H_ + +#include "cam_sensor_dev.h" + +/** + * @s_ctrl: Sensor ctrl structure + * + * This API powers up the camera sensor module + */ +int cam_sensor_power_up(struct cam_sensor_ctrl_t *s_ctrl); + +/** + * @s_ctrl: Sensor ctrl structure + * + * This API powers down the camera sensor module + */ +int cam_sensor_power_down(struct cam_sensor_ctrl_t *s_ctrl); + +/** + * @sd: V4L2 subdevice + * @on: Turn off/on flag + * + * This API powers down the sensor module + */ +int cam_sensor_power(struct v4l2_subdev *sd, int on); + +/** + * @s_ctrl: Sensor ctrl structure + * @req_id: Request id + * @opcode: opcode for settings + * + * This API applies the req_id settings to sensor + */ +int cam_sensor_apply_settings(struct cam_sensor_ctrl_t *s_ctrl, int64_t req_id, + enum cam_sensor_packet_opcodes opcode); + +/** + * @apply: Req mgr structure for applying request + * + * This API applies the request that is mentioned + */ +int cam_sensor_apply_request(struct cam_req_mgr_apply_request *apply); + +/** + * @flush: Req mgr structure for flushing request + * + * This API flushes the request that is mentioned + */ +int cam_sensor_flush_request(struct cam_req_mgr_flush_request *flush); + +/** + * @info: Sub device info to req mgr + * + * Publish the subdevice info + */ +int cam_sensor_publish_dev_info(struct cam_req_mgr_device_info *info); + +/** + * @link: Link setup info + * + * This API establishes link with sensor subdevice with req mgr + */ +int cam_sensor_establish_link(struct cam_req_mgr_core_dev_link_setup *link); + +/** + * @s_ctrl: Sensor ctrl structure + * @arg: Camera control command argument + * + * This API handles the camera control argument reached to sensor + */ +int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, void *arg); + +/** + * @s_ctrl: Sensor ctrl structure + * + * This API handles the camera sensor close/shutdown + */ +void cam_sensor_shutdown(struct cam_sensor_ctrl_t *s_ctrl); + +#endif /* _CAM_SENSOR_CORE_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..765a1244a0aa50ab6ef62dd62b14b6ac2593bb36 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.c @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_sensor_dev.h" +#include "cam_req_mgr_dev.h" +#include "cam_sensor_soc.h" +#include "cam_sensor_core.h" + +static long cam_sensor_subdev_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + int rc = 0; + struct cam_sensor_ctrl_t *s_ctrl = + v4l2_get_subdevdata(sd); + + switch (cmd) { + case VIDIOC_CAM_CONTROL: + rc = cam_sensor_driver_cmd(s_ctrl, arg); + break; + default: + CAM_ERR(CAM_SENSOR, "Invalid ioctl cmd: %d", cmd); + rc = -EINVAL; + break; + } + return rc; +} + +static int cam_sensor_subdev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct cam_sensor_ctrl_t *s_ctrl = + v4l2_get_subdevdata(sd); + + if (!s_ctrl) { + CAM_ERR(CAM_SENSOR, "s_ctrl ptr is NULL"); + return -EINVAL; + } + + mutex_lock(&(s_ctrl->cam_sensor_mutex)); + cam_sensor_shutdown(s_ctrl); + mutex_unlock(&(s_ctrl->cam_sensor_mutex)); + + return 0; +} + +#ifdef CONFIG_COMPAT +static long cam_sensor_init_subdev_do_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + struct cam_control cmd_data; + int32_t rc = 0; + + if (copy_from_user(&cmd_data, (void __user *)arg, + sizeof(cmd_data))) { + CAM_ERR(CAM_SENSOR, "Failed to copy from user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + return -EFAULT; + } + + switch (cmd) { + case VIDIOC_CAM_CONTROL: + rc = cam_sensor_subdev_ioctl(sd, cmd, &cmd_data); + if (rc < 0) + CAM_ERR(CAM_SENSOR, "cam_sensor_subdev_ioctl failed"); + break; + default: + CAM_ERR(CAM_SENSOR, "Invalid compat ioctl cmd_type: %d", cmd); + rc = -EINVAL; + } + + if (!rc) { + if (copy_to_user((void __user *)arg, &cmd_data, + sizeof(cmd_data))) { + CAM_ERR(CAM_SENSOR, + "Failed to copy to user_ptr=%pK size=%zu", + (void __user *)arg, sizeof(cmd_data)); + rc = -EFAULT; + } + } + + return rc; +} + +#endif +static struct v4l2_subdev_core_ops cam_sensor_subdev_core_ops = { + .ioctl = cam_sensor_subdev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = cam_sensor_init_subdev_do_ioctl, +#endif + .s_power = cam_sensor_power, +}; + +static struct v4l2_subdev_ops cam_sensor_subdev_ops = { + .core = &cam_sensor_subdev_core_ops, +}; + +static const struct v4l2_subdev_internal_ops cam_sensor_internal_ops = { + .close = cam_sensor_subdev_close, +}; + +static int cam_sensor_init_subdev_params(struct cam_sensor_ctrl_t *s_ctrl) +{ + int rc = 0; + + s_ctrl->v4l2_dev_str.internal_ops = + &cam_sensor_internal_ops; + s_ctrl->v4l2_dev_str.ops = + &cam_sensor_subdev_ops; + strlcpy(s_ctrl->device_name, CAMX_SENSOR_DEV_NAME, + sizeof(s_ctrl->device_name)); + s_ctrl->v4l2_dev_str.name = + s_ctrl->device_name; + s_ctrl->v4l2_dev_str.sd_flags = + (V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS); + s_ctrl->v4l2_dev_str.ent_function = + CAM_SENSOR_DEVICE_TYPE; + s_ctrl->v4l2_dev_str.token = s_ctrl; + + rc = cam_register_subdev(&(s_ctrl->v4l2_dev_str)); + if (rc) + CAM_ERR(CAM_SENSOR, "Fail with cam_register_subdev rc: %d", rc); + + return rc; +} + +static int32_t cam_sensor_driver_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int32_t rc = 0; + int i = 0; + struct cam_sensor_ctrl_t *s_ctrl = NULL; + struct cam_hw_soc_info *soc_info = NULL; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + CAM_ERR(CAM_SENSOR, + "%s :i2c_check_functionality failed", client->name); + return -EFAULT; + } + + /* Create sensor control structure */ + s_ctrl = kzalloc(sizeof(*s_ctrl), GFP_KERNEL); + if (!s_ctrl) + return -ENOMEM; + + i2c_set_clientdata(client, s_ctrl); + + s_ctrl->io_master_info.client = client; + soc_info = &s_ctrl->soc_info; + soc_info->dev = &client->dev; + soc_info->dev_name = client->name; + + /* Initialize sensor device type */ + s_ctrl->of_node = client->dev.of_node; + s_ctrl->io_master_info.master_type = I2C_MASTER; + s_ctrl->is_probe_succeed = 0; + s_ctrl->last_flush_req = 0; + + rc = cam_sensor_parse_dt(s_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "cam_sensor_parse_dt rc %d", rc); + goto free_s_ctrl; + } + + rc = cam_sensor_init_subdev_params(s_ctrl); + if (rc) + goto free_s_ctrl; + + s_ctrl->i2c_data.per_frame = + kzalloc(sizeof(struct i2c_settings_array) * + MAX_PER_FRAME_ARRAY, GFP_KERNEL); + if (s_ctrl->i2c_data.per_frame == NULL) { + rc = -ENOMEM; + goto unreg_subdev; + } + + INIT_LIST_HEAD(&(s_ctrl->i2c_data.init_settings.list_head)); + INIT_LIST_HEAD(&(s_ctrl->i2c_data.config_settings.list_head)); + INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamon_settings.list_head)); + INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamoff_settings.list_head)); + INIT_LIST_HEAD(&(s_ctrl->i2c_data.read_settings.list_head)); + + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) + INIT_LIST_HEAD(&(s_ctrl->i2c_data.per_frame[i].list_head)); + + s_ctrl->bridge_intf.device_hdl = -1; + s_ctrl->bridge_intf.link_hdl = -1; + s_ctrl->bridge_intf.ops.get_dev_info = cam_sensor_publish_dev_info; + s_ctrl->bridge_intf.ops.link_setup = cam_sensor_establish_link; + s_ctrl->bridge_intf.ops.apply_req = cam_sensor_apply_request; + s_ctrl->bridge_intf.ops.flush_req = cam_sensor_flush_request; + + s_ctrl->sensordata->power_info.dev = soc_info->dev; + + return rc; +unreg_subdev: + cam_unregister_subdev(&(s_ctrl->v4l2_dev_str)); +free_s_ctrl: + kfree(s_ctrl); + return rc; +} + +static int cam_sensor_platform_remove(struct platform_device *pdev) +{ + int i; + struct cam_sensor_ctrl_t *s_ctrl; + struct cam_hw_soc_info *soc_info; + + s_ctrl = platform_get_drvdata(pdev); + if (!s_ctrl) { + CAM_ERR(CAM_SENSOR, "sensor device is NULL"); + return 0; + } + + CAM_INFO(CAM_SENSOR, "platform remove invoked"); + mutex_lock(&(s_ctrl->cam_sensor_mutex)); + cam_sensor_shutdown(s_ctrl); + mutex_unlock(&(s_ctrl->cam_sensor_mutex)); + cam_unregister_subdev(&(s_ctrl->v4l2_dev_str)); + soc_info = &s_ctrl->soc_info; + for (i = 0; i < soc_info->num_clk; i++) + devm_clk_put(soc_info->dev, soc_info->clk[i]); + + kfree(s_ctrl->i2c_data.per_frame); + platform_set_drvdata(pdev, NULL); + v4l2_set_subdevdata(&(s_ctrl->v4l2_dev_str.sd), NULL); + devm_kfree(&pdev->dev, s_ctrl); + + return 0; +} + +static int cam_sensor_driver_i2c_remove(struct i2c_client *client) +{ + int i; + struct cam_sensor_ctrl_t *s_ctrl = i2c_get_clientdata(client); + struct cam_hw_soc_info *soc_info; + + if (!s_ctrl) { + CAM_ERR(CAM_SENSOR, "sensor device is NULL"); + return 0; + } + + CAM_INFO(CAM_SENSOR, "i2c remove invoked"); + mutex_lock(&(s_ctrl->cam_sensor_mutex)); + cam_sensor_shutdown(s_ctrl); + mutex_unlock(&(s_ctrl->cam_sensor_mutex)); + cam_unregister_subdev(&(s_ctrl->v4l2_dev_str)); + soc_info = &s_ctrl->soc_info; + for (i = 0; i < soc_info->num_clk; i++) + devm_clk_put(soc_info->dev, soc_info->clk[i]); + + kfree(s_ctrl->i2c_data.per_frame); + v4l2_set_subdevdata(&(s_ctrl->v4l2_dev_str.sd), NULL); + kfree(s_ctrl); + + return 0; +} + +static const struct of_device_id cam_sensor_driver_dt_match[] = { + {.compatible = "qcom,cam-sensor"}, + {} +}; + +static int32_t cam_sensor_driver_platform_probe( + struct platform_device *pdev) +{ + int32_t rc = 0, i = 0; + struct cam_sensor_ctrl_t *s_ctrl = NULL; + struct cam_hw_soc_info *soc_info = NULL; + + /* Create sensor control structure */ + s_ctrl = devm_kzalloc(&pdev->dev, + sizeof(struct cam_sensor_ctrl_t), GFP_KERNEL); + if (!s_ctrl) + return -ENOMEM; + + soc_info = &s_ctrl->soc_info; + soc_info->pdev = pdev; + soc_info->dev = &pdev->dev; + soc_info->dev_name = pdev->name; + + /* Initialize sensor device type */ + s_ctrl->of_node = pdev->dev.of_node; + s_ctrl->is_probe_succeed = 0; + s_ctrl->last_flush_req = 0; + + /*fill in platform device*/ + s_ctrl->pdev = pdev; + + s_ctrl->io_master_info.master_type = CCI_MASTER; + + rc = cam_sensor_parse_dt(s_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed: cam_sensor_parse_dt rc %d", rc); + goto free_s_ctrl; + } + + /* Fill platform device id*/ + pdev->id = soc_info->index; + + rc = cam_sensor_init_subdev_params(s_ctrl); + if (rc) + goto free_s_ctrl; + + s_ctrl->i2c_data.per_frame = + kzalloc(sizeof(struct i2c_settings_array) * + MAX_PER_FRAME_ARRAY, GFP_KERNEL); + if (s_ctrl->i2c_data.per_frame == NULL) { + rc = -ENOMEM; + goto unreg_subdev; + } + + INIT_LIST_HEAD(&(s_ctrl->i2c_data.init_settings.list_head)); + INIT_LIST_HEAD(&(s_ctrl->i2c_data.config_settings.list_head)); + INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamon_settings.list_head)); + INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamoff_settings.list_head)); + INIT_LIST_HEAD(&(s_ctrl->i2c_data.read_settings.list_head)); + + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) + INIT_LIST_HEAD(&(s_ctrl->i2c_data.per_frame[i].list_head)); + + s_ctrl->bridge_intf.device_hdl = -1; + s_ctrl->bridge_intf.link_hdl = -1; + s_ctrl->bridge_intf.ops.get_dev_info = cam_sensor_publish_dev_info; + s_ctrl->bridge_intf.ops.link_setup = cam_sensor_establish_link; + s_ctrl->bridge_intf.ops.apply_req = cam_sensor_apply_request; + s_ctrl->bridge_intf.ops.flush_req = cam_sensor_flush_request; + + s_ctrl->sensordata->power_info.dev = &pdev->dev; + platform_set_drvdata(pdev, s_ctrl); + s_ctrl->sensor_state = CAM_SENSOR_INIT; + + return rc; +unreg_subdev: + cam_unregister_subdev(&(s_ctrl->v4l2_dev_str)); +free_s_ctrl: + devm_kfree(&pdev->dev, s_ctrl); + return rc; +} + +MODULE_DEVICE_TABLE(of, cam_sensor_driver_dt_match); + +static struct platform_driver cam_sensor_platform_driver = { + .probe = cam_sensor_driver_platform_probe, + .driver = { + .name = "qcom,camera", + .owner = THIS_MODULE, + .of_match_table = cam_sensor_driver_dt_match, + .suppress_bind_attrs = true, + }, + .remove = cam_sensor_platform_remove, +}; + +static const struct i2c_device_id i2c_id[] = { + {SENSOR_DRIVER_I2C, (kernel_ulong_t)NULL}, + { } +}; + +static struct i2c_driver cam_sensor_driver_i2c = { + .id_table = i2c_id, + .probe = cam_sensor_driver_i2c_probe, + .remove = cam_sensor_driver_i2c_remove, + .driver = { + .name = SENSOR_DRIVER_I2C, + }, +}; + +static int __init cam_sensor_driver_init(void) +{ + int32_t rc = 0; + + rc = platform_driver_register(&cam_sensor_platform_driver); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "platform_driver_register Failed: rc = %d", + rc); + return rc; + } + + rc = i2c_add_driver(&cam_sensor_driver_i2c); + if (rc) + CAM_ERR(CAM_SENSOR, "i2c_add_driver failed rc = %d", rc); + + return rc; +} + +static void __exit cam_sensor_driver_exit(void) +{ + platform_driver_unregister(&cam_sensor_platform_driver); + i2c_del_driver(&cam_sensor_driver_i2c); +} + +module_init(cam_sensor_driver_init); +module_exit(cam_sensor_driver_exit); +MODULE_DESCRIPTION("cam_sensor_driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..b1963e15eb5954c4ce8fcd62b47190184dcc8b23 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_SENSOR_DEV_H_ +#define _CAM_SENSOR_DEV_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_debug_util.h" +#include "cam_context.h" + +#define NUM_MASTERS 2 +#define NUM_QUEUES 2 + +#undef CDBG +#ifdef CAM_SENSOR_DEBUG +#define CDBG(fmt, args...) pr_err(fmt, ##args) +#else +#define CDBG(fmt, args...) pr_debug(fmt, ##args) +#endif + +#define SENSOR_DRIVER_I2C "i2c_camera" +#define CAMX_SENSOR_DEV_NAME "cam-sensor-driver" + +enum cam_sensor_state_t { + CAM_SENSOR_INIT, + CAM_SENSOR_ACQUIRE, + CAM_SENSOR_CONFIG, + CAM_SENSOR_START, +}; + +/** + * struct intf_params + * @device_hdl: Device Handle + * @session_hdl: Session Handle + * @link_hdl: Link Handle + * @ops: KMD operations + * @crm_cb: Callback API pointers + */ +struct intf_params { + int32_t device_hdl; + int32_t session_hdl; + int32_t link_hdl; + struct cam_req_mgr_kmd_ops ops; + struct cam_req_mgr_crm_cb *crm_cb; +}; + +/** + * struct cam_sensor_ctrl_t: Camera control structure + * @device_name: Sensor device name + * @pdev: Platform device + * @cam_sensor_mutex: Sensor mutex + * @sensordata: Sensor board Information + * @cci_i2c_master: I2C structure + * @io_master_info: Information about the communication master + * @sensor_state: Sensor states + * @is_probe_succeed: Probe succeeded or not + * @id: Cell Index + * @of_node: Of node ptr + * @v4l2_dev_str: V4L2 device structure + * @sensor_probe_addr_type: Sensor probe address type + * @sensor_probe_data_type: Sensor probe data type + * @i2c_data: Sensor I2C register settings + * @sensor_info: Sensor query cap structure + * @bridge_intf: Bridge interface structure + * @streamon_count: Count to hold the number of times stream on called + * @streamoff_count: Count to hold the number of times stream off called + * @bob_reg_index: Hold to BoB regulator index + * @bob_pwm_switch: Boolean flag to switch into PWM mode for BoB regulator + * @last_flush_req: Last request to flush + * @pipeline_delay: Sensor pipeline delay + */ +struct cam_sensor_ctrl_t { + char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH]; + struct platform_device *pdev; + struct cam_hw_soc_info soc_info; + struct mutex cam_sensor_mutex; + struct cam_sensor_board_info *sensordata; + enum cci_i2c_master_t cci_i2c_master; + enum cci_device_num cci_num; + struct camera_io_master io_master_info; + enum cam_sensor_state_t sensor_state; + uint8_t is_probe_succeed; + uint32_t id; + struct device_node *of_node; + struct cam_subdev v4l2_dev_str; + uint8_t sensor_probe_addr_type; + uint8_t sensor_probe_data_type; + struct i2c_data_settings i2c_data; + struct cam_sensor_query_cap sensor_info; + struct intf_params bridge_intf; + uint32_t streamon_count; + uint32_t streamoff_count; + int bob_reg_index; + bool bob_pwm_switch; + uint32_t last_flush_req; + uint16_t pipeline_delay; +}; + +#endif /* _CAM_SENSOR_DEV_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_soc.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_soc.c new file mode 100644 index 0000000000000000000000000000000000000000..2c25ee0aa6f0433ef9e2e912f31e979761f0892d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_soc.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "cam_sensor_soc.h" +#include "cam_soc_util.h" + +int32_t cam_sensor_get_sub_module_index(struct device_node *of_node, + struct cam_sensor_board_info *s_info) +{ + int rc = 0, i = 0; + uint32_t val = 0; + struct device_node *src_node = NULL; + struct cam_sensor_board_info *sensor_info; + + sensor_info = s_info; + + for (i = 0; i < SUB_MODULE_MAX; i++) + sensor_info->subdev_id[i] = -1; + + src_node = of_parse_phandle(of_node, "actuator-src", 0); + if (!src_node) { + CAM_DBG(CAM_SENSOR, "src_node NULL"); + } else { + rc = of_property_read_u32(src_node, "cell-index", &val); + CAM_DBG(CAM_SENSOR, "actuator cell index %d, rc %d", val, rc); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed %d", rc); + of_node_put(src_node); + return rc; + } + sensor_info->subdev_id[SUB_MODULE_ACTUATOR] = val; + of_node_put(src_node); + } + + src_node = of_parse_phandle(of_node, "ois-src", 0); + if (!src_node) { + CAM_DBG(CAM_SENSOR, "src_node NULL"); + } else { + rc = of_property_read_u32(src_node, "cell-index", &val); + CAM_DBG(CAM_SENSOR, " ois cell index %d, rc %d", val, rc); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed %d", rc); + of_node_put(src_node); + return rc; + } + sensor_info->subdev_id[SUB_MODULE_OIS] = val; + of_node_put(src_node); + } + + src_node = of_parse_phandle(of_node, "eeprom-src", 0); + if (!src_node) { + CAM_DBG(CAM_SENSOR, "eeprom src_node NULL"); + } else { + rc = of_property_read_u32(src_node, "cell-index", &val); + CAM_DBG(CAM_SENSOR, "eeprom cell index %d, rc %d", val, rc); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed %d", rc); + of_node_put(src_node); + return rc; + } + sensor_info->subdev_id[SUB_MODULE_EEPROM] = val; + of_node_put(src_node); + } + + src_node = of_parse_phandle(of_node, "led-flash-src", 0); + if (!src_node) { + CAM_DBG(CAM_SENSOR, " src_node NULL"); + } else { + rc = of_property_read_u32(src_node, "cell-index", &val); + CAM_DBG(CAM_SENSOR, "led flash cell index %d, rc %d", val, rc); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed %d", rc); + of_node_put(src_node); + return rc; + } + sensor_info->subdev_id[SUB_MODULE_LED_FLASH] = val; + of_node_put(src_node); + } + + rc = of_property_read_u32(of_node, "csiphy-sd-index", &val); + if (rc < 0) + CAM_ERR(CAM_SENSOR, "paring the dt node for csiphy rc %d", rc); + else + sensor_info->subdev_id[SUB_MODULE_CSIPHY] = val; + + return rc; +} + +static int32_t cam_sensor_driver_get_dt_data(struct cam_sensor_ctrl_t *s_ctrl) +{ + int32_t rc = 0; + int i = 0; + struct cam_sensor_board_info *sensordata = NULL; + struct device_node *of_node = s_ctrl->of_node; + struct device_node *of_parent = NULL; + struct cam_hw_soc_info *soc_info = &s_ctrl->soc_info; + + s_ctrl->sensordata = kzalloc(sizeof(*sensordata), GFP_KERNEL); + if (!s_ctrl->sensordata) + return -ENOMEM; + + sensordata = s_ctrl->sensordata; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Failed to read DT properties rc %d", rc); + goto FREE_SENSOR_DATA; + } + + rc = cam_sensor_util_init_gpio_pin_tbl(soc_info, + &sensordata->power_info.gpio_num_info); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Failed to read gpios %d", rc); + goto FREE_SENSOR_DATA; + } + + s_ctrl->id = soc_info->index; + + /* Validate cell_id */ + if (s_ctrl->id >= MAX_CAMERAS) { + CAM_ERR(CAM_SENSOR, "Failed invalid cell_id %d", s_ctrl->id); + rc = -EINVAL; + goto FREE_SENSOR_DATA; + } + + /* Store the index of BoB regulator if it is available */ + for (i = 0; i < soc_info->num_rgltr; i++) { + if (!strcmp(soc_info->rgltr_name[i], + "cam_bob")) { + CAM_DBG(CAM_SENSOR, + "i: %d cam_bob", i); + s_ctrl->bob_reg_index = i; + soc_info->rgltr[i] = devm_regulator_get(soc_info->dev, + soc_info->rgltr_name[i]); + if (IS_ERR_OR_NULL(soc_info->rgltr[i])) { + CAM_WARN(CAM_SENSOR, + "Regulator: %s get failed", + soc_info->rgltr_name[i]); + soc_info->rgltr[i] = NULL; + } else { + if (!of_property_read_bool(of_node, + "pwm-switch")) { + CAM_DBG(CAM_SENSOR, + "No BoB PWM switch param defined"); + s_ctrl->bob_pwm_switch = false; + } else { + s_ctrl->bob_pwm_switch = true; + } + } + } + } + + /* Read subdev info */ + rc = cam_sensor_get_sub_module_index(of_node, sensordata); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed to get sub module index, rc=%d", + rc); + goto FREE_SENSOR_DATA; + } + + if (s_ctrl->io_master_info.master_type == CCI_MASTER) { + /* Get CCI master */ + rc = of_property_read_u32(of_node, "cci-master", + &s_ctrl->cci_i2c_master); + CAM_DBG(CAM_SENSOR, "cci-master %d, rc %d", + s_ctrl->cci_i2c_master, rc); + if (rc < 0) { + /* Set default master 0 */ + s_ctrl->cci_i2c_master = MASTER_0; + rc = 0; + } + + of_parent = of_get_parent(of_node); + if (of_property_read_u32(of_parent, "cell-index", + &s_ctrl->cci_num) < 0) + /* Set default master 0 */ + s_ctrl->cci_num = CCI_DEVICE_0; + + CAM_DBG(CAM_SENSOR, "cci-index %d", s_ctrl->cci_num); + } + + if (of_property_read_u32(of_node, "sensor-position-pitch", + &sensordata->pos_pitch) < 0) { + CAM_DBG(CAM_SENSOR, "Invalid sensor position"); + sensordata->pos_pitch = 360; + } + if (of_property_read_u32(of_node, "sensor-position-roll", + &sensordata->pos_roll) < 0) { + CAM_DBG(CAM_SENSOR, "Invalid sensor position"); + sensordata->pos_roll = 360; + } + if (of_property_read_u32(of_node, "sensor-position-yaw", + &sensordata->pos_yaw) < 0) { + CAM_DBG(CAM_SENSOR, "Invalid sensor position"); + sensordata->pos_yaw = 360; + } + + return rc; + +FREE_SENSOR_DATA: + kfree(sensordata); + return rc; +} + +int32_t msm_sensor_init_default_params(struct cam_sensor_ctrl_t *s_ctrl) +{ + /* Validate input parameters */ + if (!s_ctrl) { + CAM_ERR(CAM_SENSOR, "failed: invalid params s_ctrl %pK", + s_ctrl); + return -EINVAL; + } + + CAM_DBG(CAM_SENSOR, + "master_type: %d", s_ctrl->io_master_info.master_type); + /* Initialize cci_client */ + if (s_ctrl->io_master_info.master_type == CCI_MASTER) { + s_ctrl->io_master_info.cci_client = kzalloc(sizeof( + struct cam_sensor_cci_client), GFP_KERNEL); + if (!(s_ctrl->io_master_info.cci_client)) + return -ENOMEM; + + s_ctrl->io_master_info.cci_client->cci_device + = s_ctrl->cci_num; + } else if (s_ctrl->io_master_info.master_type == I2C_MASTER) { + if (!(s_ctrl->io_master_info.client)) + return -EINVAL; + } else { + CAM_ERR(CAM_SENSOR, + "Invalid master / Master type Not supported"); + return -EINVAL; + } + + return 0; +} + +int32_t cam_sensor_parse_dt(struct cam_sensor_ctrl_t *s_ctrl) +{ + int32_t i, rc = 0; + struct cam_hw_soc_info *soc_info = &s_ctrl->soc_info; + + /* Parse dt information and store in sensor control structure */ + rc = cam_sensor_driver_get_dt_data(s_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Failed to get dt data rc %d", rc); + return rc; + } + + /* Initialize mutex */ + mutex_init(&(s_ctrl->cam_sensor_mutex)); + + /* Initialize default parameters */ + for (i = 0; i < soc_info->num_clk; i++) { + soc_info->clk[i] = devm_clk_get(soc_info->dev, + soc_info->clk_name[i]); + if (!soc_info->clk[i]) { + CAM_ERR(CAM_SENSOR, "get failed for %s", + soc_info->clk_name[i]); + rc = -ENOENT; + return rc; + } + } + rc = msm_sensor_init_default_params(s_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "failed: msm_sensor_init_default_params rc %d", rc); + goto FREE_DT_DATA; + } + + return rc; + +FREE_DT_DATA: + kfree(s_ctrl->sensordata); + s_ctrl->sensordata = NULL; + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_soc.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..99862da046ffa2e48c5cbf1ce6f68eb5d676994b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/cam_sensor_soc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_SENSOR_SOC_H_ +#define _CAM_SENSOR_SOC_H_ + +#include "cam_sensor_dev.h" + +/** + * @s_ctrl: Sensor ctrl structure + * + * Parses sensor dt + */ +int cam_sensor_parse_dt(struct cam_sensor_ctrl_t *s_ctrl); + +#endif /* _CAM_SENSOR_SOC_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..3cd0ca2180390493724a0cd5df78650f7e1a94de --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_io.o cam_sensor_cci_i2c.o cam_sensor_qup_i2c.o cam_sensor_spi.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_cci_i2c.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_cci_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..a5e780a2e119122f198b54b794cdf5aef1520006 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_cci_i2c.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#include "cam_sensor_cmn_header.h" +#include "cam_sensor_i2c.h" +#include "cam_cci_dev.h" + +int32_t cam_cci_i2c_read(struct cam_sensor_cci_client *cci_client, + uint32_t addr, uint32_t *data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type) +{ + int32_t rc = -EINVAL; + unsigned char buf[CAMERA_SENSOR_I2C_TYPE_DWORD]; + struct cam_cci_ctrl cci_ctrl; + + if (addr_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX + || data_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || data_type >= CAMERA_SENSOR_I2C_TYPE_MAX) + return rc; + + cci_ctrl.cmd = MSM_CCI_I2C_READ; + cci_ctrl.cci_info = cci_client; + cci_ctrl.cfg.cci_i2c_read_cfg.addr = addr; + cci_ctrl.cfg.cci_i2c_read_cfg.addr_type = addr_type; + cci_ctrl.cfg.cci_i2c_read_cfg.data_type = data_type; + cci_ctrl.cfg.cci_i2c_read_cfg.data = buf; + cci_ctrl.cfg.cci_i2c_read_cfg.num_byte = data_type; + rc = v4l2_subdev_call(cci_client->cci_subdev, + core, ioctl, VIDIOC_MSM_CCI_CFG, &cci_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "rc = %d", rc); + return rc; + } + + rc = cci_ctrl.status; + if (data_type == CAMERA_SENSOR_I2C_TYPE_BYTE) + *data = buf[0]; + else if (data_type == CAMERA_SENSOR_I2C_TYPE_WORD) + *data = buf[0] << 8 | buf[1]; + else if (data_type == CAMERA_SENSOR_I2C_TYPE_3B) + *data = buf[0] << 16 | buf[1] << 8 | buf[2]; + else + *data = buf[0] << 24 | buf[1] << 16 | + buf[2] << 8 | buf[3]; + + return rc; +} + +int32_t cam_camera_cci_i2c_read_seq(struct cam_sensor_cci_client *cci_client, + uint32_t addr, uint8_t *data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type, + uint32_t num_byte) +{ + int32_t rc = -EFAULT; + unsigned char *buf = NULL; + int i = 0; + struct cam_cci_ctrl cci_ctrl; + + if ((addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX) + || (data_type >= CAMERA_SENSOR_I2C_TYPE_MAX) + || (num_byte > I2C_REG_DATA_MAX)) { + CAM_ERR(CAM_SENSOR, "addr_type %d num_byte %d", addr_type, + num_byte); + return rc; + } + + buf = kzalloc(num_byte, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + cci_ctrl.cmd = MSM_CCI_I2C_READ; + cci_ctrl.cci_info = cci_client; + cci_ctrl.cfg.cci_i2c_read_cfg.addr = addr; + cci_ctrl.cfg.cci_i2c_read_cfg.addr_type = addr_type; + cci_ctrl.cfg.cci_i2c_read_cfg.data_type = data_type; + cci_ctrl.cfg.cci_i2c_read_cfg.data = buf; + cci_ctrl.cfg.cci_i2c_read_cfg.num_byte = num_byte; + cci_ctrl.status = -EFAULT; + rc = v4l2_subdev_call(cci_client->cci_subdev, + core, ioctl, VIDIOC_MSM_CCI_CFG, &cci_ctrl); + rc = cci_ctrl.status; + CAM_DBG(CAM_SENSOR, "addr = 0x%x, rc = %d", addr, rc); + for (i = 0; i < num_byte; i++) { + data[i] = buf[i]; + CAM_DBG(CAM_SENSOR, "Byte %d: Data: 0x%x\n", i, data[i]); + } + kfree(buf); + return rc; +} + +static int32_t cam_cci_i2c_write_table_cmd( + struct camera_io_master *client, + struct cam_sensor_i2c_reg_setting *write_setting, + enum cam_cci_cmd_type cmd) +{ + int32_t rc = -EINVAL; + struct cam_cci_ctrl cci_ctrl; + + if (!client || !write_setting) + return rc; + + if (write_setting->addr_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || write_setting->addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX + || write_setting->data_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || write_setting->data_type >= CAMERA_SENSOR_I2C_TYPE_MAX) + return rc; + + cci_ctrl.cmd = cmd; + cci_ctrl.cci_info = client->cci_client; + cci_ctrl.cfg.cci_i2c_write_cfg.reg_setting = + write_setting->reg_setting; + cci_ctrl.cfg.cci_i2c_write_cfg.data_type = write_setting->data_type; + cci_ctrl.cfg.cci_i2c_write_cfg.addr_type = write_setting->addr_type; + cci_ctrl.cfg.cci_i2c_write_cfg.size = write_setting->size; + rc = v4l2_subdev_call(client->cci_client->cci_subdev, + core, ioctl, VIDIOC_MSM_CCI_CFG, &cci_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Failed rc = %d", rc); + return rc; + } + rc = cci_ctrl.status; + if (write_setting->delay > 20) + msleep(write_setting->delay); + else if (write_setting->delay) + usleep_range(write_setting->delay * 1000, (write_setting->delay + * 1000) + 1000); + + return rc; +} + + +int32_t cam_cci_i2c_write_table( + struct camera_io_master *client, + struct cam_sensor_i2c_reg_setting *write_setting) +{ + return cam_cci_i2c_write_table_cmd(client, write_setting, + MSM_CCI_I2C_WRITE); +} + +int32_t cam_cci_i2c_write_continuous_table( + struct camera_io_master *client, + struct cam_sensor_i2c_reg_setting *write_setting, + uint8_t cam_sensor_i2c_write_flag) +{ + int32_t rc = 0; + + if (cam_sensor_i2c_write_flag == 1) + rc = cam_cci_i2c_write_table_cmd(client, write_setting, + MSM_CCI_I2C_WRITE_BURST); + else if (cam_sensor_i2c_write_flag == 0) + rc = cam_cci_i2c_write_table_cmd(client, write_setting, + MSM_CCI_I2C_WRITE_SEQ); + + return rc; +} + +static int32_t cam_cci_i2c_compare(struct cam_sensor_cci_client *client, + uint32_t addr, uint16_t data, uint16_t data_mask, + enum camera_sensor_i2c_type data_type, + enum camera_sensor_i2c_type addr_type) +{ + int32_t rc; + uint32_t reg_data = 0; + + rc = cam_cci_i2c_read(client, addr, ®_data, + addr_type, data_type); + if (rc < 0) + return rc; + + reg_data = reg_data & 0xFFFF; + if (data == (reg_data & ~data_mask)) + return I2C_COMPARE_MATCH; + return I2C_COMPARE_MISMATCH; +} + +int32_t cam_cci_i2c_poll(struct cam_sensor_cci_client *client, + uint32_t addr, uint16_t data, uint16_t data_mask, + enum camera_sensor_i2c_type data_type, + enum camera_sensor_i2c_type addr_type, + uint32_t delay_ms) +{ + int32_t rc = -EINVAL; + int32_t i = 0; + + CAM_DBG(CAM_SENSOR, "addr: 0x%x data: 0x%x dt: %d", + addr, data, data_type); + + if (delay_ms > MAX_POLL_DELAY_MS) { + CAM_ERR(CAM_SENSOR, "invalid delay = %d max_delay = %d", + delay_ms, MAX_POLL_DELAY_MS); + return -EINVAL; + } + for (i = 0; i < delay_ms; i++) { + rc = cam_cci_i2c_compare(client, + addr, data, data_mask, data_type, addr_type); + if (!rc) + return rc; + + usleep_range(1000, 1010); + } + + /* If rc is 1 then read is successful but poll is failure */ + if (rc == 1) + CAM_ERR(CAM_SENSOR, "poll failed rc=%d(non-fatal)", rc); + + if (rc < 0) + CAM_ERR(CAM_SENSOR, "poll failed rc=%d", rc); + + return rc; +} + +int32_t cam_sensor_cci_i2c_util(struct cam_sensor_cci_client *cci_client, + uint16_t cci_cmd) +{ + int32_t rc = 0; + struct cam_cci_ctrl cci_ctrl; + + cci_ctrl.cmd = cci_cmd; + cci_ctrl.cci_info = cci_client; + rc = v4l2_subdev_call(cci_client->cci_subdev, + core, ioctl, VIDIOC_MSM_CCI_CFG, &cci_ctrl); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Failed rc = %d", rc); + return rc; + } + return cci_ctrl.status; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_i2c.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..def8be55bc8b1022037a247efdf61c779e138713 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_i2c.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_SENSOR_I2C_H_ +#define _CAM_SENSOR_I2C_H_ + +#include +#include +#include +#include "cam_cci_dev.h" +#include "cam_sensor_io.h" + +#define I2C_POLL_TIME_MS 5 +#define MAX_POLL_DELAY_MS 100 + +#define I2C_COMPARE_MATCH 0 +#define I2C_COMPARE_MISMATCH 1 + +#define I2C_REG_DATA_MAX (8*1024) + +/** + * @client: CCI client structure + * @data: I2C data + * @addr_type: I2c address type + * @data_type: I2C data type + * + * This API handles CCI read + */ +int32_t cam_cci_i2c_read(struct cam_sensor_cci_client *client, + uint32_t addr, uint32_t *data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type); + +/** + * @client: CCI client structure + * @addr: I2c address + * @data: I2C data + * @addr_type: I2c address type + * @data_type: I2c data type + * @num_byte: number of bytes + * + * This API handles CCI sequential read + */ +int32_t cam_camera_cci_i2c_read_seq(struct cam_sensor_cci_client *client, + uint32_t addr, uint8_t *data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type, + uint32_t num_byte); + +/** + * @client: CCI client structure + * @write_setting: I2C register setting + * + * This API handles CCI random write + */ +int32_t cam_cci_i2c_write_table( + struct camera_io_master *client, + struct cam_sensor_i2c_reg_setting *write_setting); + +/** + * @client: CCI client structure + * @write_setting: I2C register setting + * @cam_sensor_i2c_write_flag: burst or seq write + * + * This API handles CCI continuous write + */ +int32_t cam_cci_i2c_write_continuous_table( + struct camera_io_master *client, + struct cam_sensor_i2c_reg_setting *write_setting, + uint8_t cam_sensor_i2c_write_flag); + +/** + * @cci_client: CCI client structure + * @cci_cmd: CCI command type + * + * Does I2C call to I2C functionalities + */ +int32_t cam_sensor_cci_i2c_util(struct cam_sensor_cci_client *cci_client, + uint16_t cci_cmd); + +/** + * @client: CCI client structure + * @addr: I2C address + * @data: I2C data + * @data_mask: I2C data mask + * @data_type: I2C data type + * @addr_type: I2C addr type + * @delay_ms: Delay in milli seconds + * + * This API implements CCI based I2C poll + */ +int32_t cam_cci_i2c_poll(struct cam_sensor_cci_client *client, + uint32_t addr, uint16_t data, uint16_t data_mask, + enum camera_sensor_i2c_type data_type, + enum camera_sensor_i2c_type addr_type, + uint32_t delay_ms); + + +/** + * cam_qup_i2c_read : QUP based i2c read + * @client : QUP I2C client structure + * @data : I2C data + * @addr_type : I2c address type + * @data_type : I2C data type + * + * This API handles QUP I2C read + */ + +int32_t cam_qup_i2c_read(struct i2c_client *client, + uint32_t addr, uint32_t *data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type); + +/** + * cam_qup_i2c_read_seq : QUP based I2C sequential read + * @client : QUP I2C client structure + * @data : I2C data + * @addr_type : I2c address type + * @num_bytes : number of bytes to read + * This API handles QUP I2C Sequential read + */ + +int32_t cam_qup_i2c_read_seq(struct i2c_client *client, + uint32_t addr, uint8_t *data, + enum camera_sensor_i2c_type addr_type, + uint32_t num_byte); + +/** + * cam_qup_i2c_poll : QUP based I2C poll operation + * @client : QUP I2C client structure + * @addr : I2C address + * @data : I2C data + * @data_mask : I2C data mask + * @data_type : I2C data type + * @addr_type : I2C addr type + * @delay_ms : Delay in milli seconds + * + * This API implements QUP based I2C poll + */ + +int32_t cam_qup_i2c_poll(struct i2c_client *client, + uint32_t addr, uint16_t data, uint16_t data_mask, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type, + uint32_t delay_ms); + +/** + * cam_qup_i2c_write_table : QUP based I2C write random + * @client : QUP I2C client structure + * @write_setting : I2C register settings + * + * This API handles QUP I2C random write + */ + +int32_t cam_qup_i2c_write_table( + struct camera_io_master *client, + struct cam_sensor_i2c_reg_setting *write_setting); + +/** + * cam_qup_i2c_write_continuous_write: QUP based I2C write continuous(Burst/Seq) + * @client: QUP I2C client structure + * @write_setting: I2C register setting + * @cam_sensor_i2c_write_flag: burst or seq write + * + * This API handles QUP continuous write + */ +int32_t cam_qup_i2c_write_continuous_table( + struct camera_io_master *client, + struct cam_sensor_i2c_reg_setting *write_setting, + uint8_t cam_sensor_i2c_write_flag); + +#endif /*_CAM_SENSOR_I2C_H*/ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_io.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_io.c new file mode 100644 index 0000000000000000000000000000000000000000..108c47923eb72e5c6d792dadeb054817ec481dfc --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_io.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_sensor_io.h" +#include "cam_sensor_i2c.h" + +int32_t camera_io_dev_poll(struct camera_io_master *io_master_info, + uint32_t addr, uint16_t data, uint32_t data_mask, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type, + uint32_t delay_ms) +{ + int16_t mask = data_mask & 0xFF; + + if (!io_master_info) { + CAM_ERR(CAM_SENSOR, "Invalid Args"); + return -EINVAL; + } + + if (io_master_info->master_type == CCI_MASTER) { + return cam_cci_i2c_poll(io_master_info->cci_client, + addr, data, mask, data_type, addr_type, delay_ms); + } else if (io_master_info->master_type == I2C_MASTER) { + return cam_qup_i2c_poll(io_master_info->client, + addr, data, data_mask, addr_type, data_type, + delay_ms); + } else { + CAM_ERR(CAM_SENSOR, "Invalid Comm. Master:%d", + io_master_info->master_type); + return -EINVAL; + } +} + +int32_t camera_io_dev_erase(struct camera_io_master *io_master_info, + uint32_t addr, uint32_t size) +{ + int rc = 0; + + if (!io_master_info) { + CAM_ERR(CAM_SENSOR, "Invalid Args"); + return -EINVAL; + } + + if (size == 0) + return rc; + + if (io_master_info->master_type == SPI_MASTER) { + CAM_DBG(CAM_SENSOR, "Calling SPI Erase"); + return cam_spi_erase(io_master_info, addr, + CAMERA_SENSOR_I2C_TYPE_WORD, size); + } else if (io_master_info->master_type == I2C_MASTER || + io_master_info->master_type == CCI_MASTER) { + CAM_ERR(CAM_SENSOR, "Erase not supported on master :%d", + io_master_info->master_type); + rc = -EINVAL; + } else { + CAM_ERR(CAM_SENSOR, "Invalid Comm. Master:%d", + io_master_info->master_type); + rc = -EINVAL; + } + return rc; +} + +int32_t camera_io_dev_read(struct camera_io_master *io_master_info, + uint32_t addr, uint32_t *data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type) +{ + if (!io_master_info) { + CAM_ERR(CAM_SENSOR, "Invalid Args"); + return -EINVAL; + } + + if (io_master_info->master_type == CCI_MASTER) { + return cam_cci_i2c_read(io_master_info->cci_client, + addr, data, addr_type, data_type); + } else if (io_master_info->master_type == I2C_MASTER) { + return cam_qup_i2c_read(io_master_info->client, + addr, data, addr_type, data_type); + } else if (io_master_info->master_type == SPI_MASTER) { + return cam_spi_read(io_master_info, + addr, data, addr_type, data_type); + } else { + CAM_ERR(CAM_SENSOR, "Invalid Comm. Master:%d", + io_master_info->master_type); + return -EINVAL; + } + return 0; +} + +int32_t camera_io_dev_read_seq(struct camera_io_master *io_master_info, + uint32_t addr, uint8_t *data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type, int32_t num_bytes) +{ + if (io_master_info->master_type == CCI_MASTER) { + return cam_camera_cci_i2c_read_seq(io_master_info->cci_client, + addr, data, addr_type, data_type, num_bytes); + } else if (io_master_info->master_type == I2C_MASTER) { + return cam_qup_i2c_read_seq(io_master_info->client, + addr, data, addr_type, num_bytes); + } else if (io_master_info->master_type == SPI_MASTER) { + return cam_spi_read_seq(io_master_info, + addr, data, addr_type, num_bytes); + } else if (io_master_info->master_type == SPI_MASTER) { + return cam_spi_write_seq(io_master_info, + addr, data, addr_type, num_bytes); + } else { + CAM_ERR(CAM_SENSOR, "Invalid Comm. Master:%d", + io_master_info->master_type); + return -EINVAL; + } + return 0; +} + +int32_t camera_io_dev_write(struct camera_io_master *io_master_info, + struct cam_sensor_i2c_reg_setting *write_setting) +{ + if (!write_setting || !io_master_info) { + CAM_ERR(CAM_SENSOR, + "Input parameters not valid ws: %pK ioinfo: %pK", + write_setting, io_master_info); + return -EINVAL; + } + + if (!write_setting->reg_setting) { + CAM_ERR(CAM_SENSOR, "Invalid Register Settings"); + return -EINVAL; + } + + if (io_master_info->master_type == CCI_MASTER) { + return cam_cci_i2c_write_table(io_master_info, + write_setting); + } else if (io_master_info->master_type == I2C_MASTER) { + return cam_qup_i2c_write_table(io_master_info, + write_setting); + } else if (io_master_info->master_type == SPI_MASTER) { + return cam_spi_write_table(io_master_info, + write_setting); + } else { + CAM_ERR(CAM_SENSOR, "Invalid Comm. Master:%d", + io_master_info->master_type); + return -EINVAL; + } +} + +int32_t camera_io_dev_write_continuous(struct camera_io_master *io_master_info, + struct cam_sensor_i2c_reg_setting *write_setting, + uint8_t cam_sensor_i2c_write_flag) +{ + if (!write_setting || !io_master_info) { + CAM_ERR(CAM_SENSOR, + "Input parameters not valid ws: %pK ioinfo: %pK", + write_setting, io_master_info); + return -EINVAL; + } + + if (!write_setting->reg_setting) { + CAM_ERR(CAM_SENSOR, "Invalid Register Settings"); + return -EINVAL; + } + + if (io_master_info->master_type == CCI_MASTER) { + return cam_cci_i2c_write_continuous_table(io_master_info, + write_setting, cam_sensor_i2c_write_flag); + } else if (io_master_info->master_type == I2C_MASTER) { + return cam_qup_i2c_write_continuous_table(io_master_info, + write_setting, cam_sensor_i2c_write_flag); + } else if (io_master_info->master_type == SPI_MASTER) { + return cam_spi_write_table(io_master_info, + write_setting); + } else { + CAM_ERR(CAM_SENSOR, "Invalid Comm. Master:%d", + io_master_info->master_type); + return -EINVAL; + } +} + +int32_t camera_io_init(struct camera_io_master *io_master_info) +{ + if (!io_master_info) { + CAM_ERR(CAM_SENSOR, "Invalid Args"); + return -EINVAL; + } + + if (io_master_info->master_type == CCI_MASTER) { + io_master_info->cci_client->cci_subdev = + cam_cci_get_subdev(io_master_info->cci_client->cci_device); + return cam_sensor_cci_i2c_util(io_master_info->cci_client, + MSM_CCI_INIT); + } else if ((io_master_info->master_type == I2C_MASTER) || + (io_master_info->master_type == SPI_MASTER)) { + return 0; + } + + return -EINVAL; +} + +int32_t camera_io_release(struct camera_io_master *io_master_info) +{ + if (!io_master_info) { + CAM_ERR(CAM_SENSOR, "Invalid Args"); + return -EINVAL; + } + + if (io_master_info->master_type == CCI_MASTER) { + return cam_sensor_cci_i2c_util(io_master_info->cci_client, + MSM_CCI_RELEASE); + } else if ((io_master_info->master_type == I2C_MASTER) || + (io_master_info->master_type == SPI_MASTER)) { + return 0; + } + + return -EINVAL; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_io.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_io.h new file mode 100644 index 0000000000000000000000000000000000000000..f70709997e692dc503887bb887035ee975c72d65 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_io.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_SENSOR_IO_H_ +#define _CAM_SENSOR_IO_H_ + +#include + +#include "cam_sensor_cmn_header.h" + +#define CCI_MASTER 1 +#define I2C_MASTER 2 +#define SPI_MASTER 3 + +/** + * @master_type: CCI master type + * @client: I2C client information structure + * @cci_client: CCI client information structure + * @spi_client: SPI client information structure + */ +struct camera_io_master { + int master_type; + struct i2c_client *client; + struct cam_sensor_cci_client *cci_client; + struct cam_sensor_spi_client *spi_client; +}; + +/** + * @io_master_info: I2C/SPI master information + * @addr: I2C address + * @data: I2C data + * @addr_type: I2C addr_type + * @data_type: I2C data type + * + * This API abstracts read functionality based on master type + */ +int32_t camera_io_dev_read(struct camera_io_master *io_master_info, + uint32_t addr, uint32_t *data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type); + +/** + * @io_master_info: I2C/SPI master information + * @addr: I2C address + * @data: I2C data + * @addr_type: I2C addr type + * @data_type: I2C data type + * @num_bytes: number of bytes + * + * This API abstracts read functionality based on master type + */ +int32_t camera_io_dev_read_seq(struct camera_io_master *io_master_info, + uint32_t addr, uint8_t *data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type, + int32_t num_bytes); + +/** + * @io_master_info: I2C/SPI master information + * + * This API initializes the I2C/SPI master based on master type + */ +int32_t camera_io_init(struct camera_io_master *io_master_info); + +/** + * @io_master_info: I2C/SPI master information + * + * This API releases the I2C/SPI master based on master type + */ +int32_t camera_io_release(struct camera_io_master *io_master_info); + +/** + * @io_master_info: I2C/SPI master information + * @write_setting: write settings information + * + * This API abstracts write functionality based on master type + */ +int32_t camera_io_dev_write(struct camera_io_master *io_master_info, + struct cam_sensor_i2c_reg_setting *write_setting); + +/** + * @io_master_info: I2C/SPI master information + * @write_setting: write settings information + * @cam_sensor_i2c_write_flag: differentiate between burst & seq + * + * This API abstracts write functionality based on master type and + * write flag for continuous write + */ +int32_t camera_io_dev_write_continuous(struct camera_io_master *io_master_info, + struct cam_sensor_i2c_reg_setting *write_setting, + uint8_t cam_sensor_i2c_write_flag); + +int32_t camera_io_dev_erase(struct camera_io_master *io_master_info, + uint32_t addr, uint32_t size); +/** + * @io_master_info: I2C/SPI master information + * @addr: I2C address + * @data: I2C data + * @data_mask: I2C data mask + * @data_type: I2C data type + * @addr_type: I2C address type + * @delay_ms: delay in milli seconds + * + * This API abstracts poll functionality based on master type + */ +int32_t camera_io_dev_poll(struct camera_io_master *io_master_info, + uint32_t addr, uint16_t data, uint32_t data_mask, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type, + uint32_t delay_ms); + +#include "cam_sensor_i2c.h" +#include "cam_sensor_spi.h" +#endif /* _CAM_SENSOR_IO_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..80c8cc8d9a480a86a9bcd7f75a902132e02e046c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.c @@ -0,0 +1,540 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#include "cam_sensor_cmn_header.h" +#include "cam_sensor_i2c.h" +#include "cam_sensor_io.h" + +#define I2C_REG_DATA_MAX (8*1024) +#define I2C_REG_MAX_BUF_SIZE 8 + +static int32_t cam_qup_i2c_rxdata( + struct i2c_client *dev_client, unsigned char *rxdata, + enum camera_sensor_i2c_type addr_type, + int data_length) +{ + int32_t rc = 0; + uint16_t saddr = dev_client->addr >> 1; + struct i2c_msg msgs[] = { + { + .addr = saddr, + .flags = 0, + .len = addr_type, + .buf = rxdata, + }, + { + .addr = saddr, + .flags = I2C_M_RD, + .len = data_length, + .buf = rxdata, + }, + }; + rc = i2c_transfer(dev_client->adapter, msgs, 2); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed 0x%x", saddr); + return rc; + } + /* Returns negative errno */ + /* else the number of messages executed. */ + /* So positive values are not errors. */ + return 0; +} + + +static int32_t cam_qup_i2c_txdata( + struct camera_io_master *dev_client, unsigned char *txdata, + int length) +{ + int32_t rc = 0; + uint16_t saddr = dev_client->client->addr >> 1; + struct i2c_msg msg[] = { + { + .addr = saddr, + .flags = 0, + .len = length, + .buf = txdata, + }, + }; + rc = i2c_transfer(dev_client->client->adapter, msg, 1); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed 0x%x", saddr); + return rc; + } + /* Returns negative errno, */ + /* else the number of messages executed. */ + /* So positive values are not errors. */ + return 0; +} + +int32_t cam_qup_i2c_read(struct i2c_client *client, + uint32_t addr, uint32_t *data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type) +{ + int32_t rc = -EINVAL; + unsigned char *buf = NULL; + + if (addr_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX + || data_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || data_type >= CAMERA_SENSOR_I2C_TYPE_MAX) { + CAM_ERR(CAM_SENSOR, "Failed with addr/data_type verfication"); + return rc; + } + + buf = kzalloc(addr_type + data_type, GFP_KERNEL); + + if (!buf) + return -ENOMEM; + + if (addr_type == CAMERA_SENSOR_I2C_TYPE_BYTE) { + buf[0] = addr; + } else if (addr_type == CAMERA_SENSOR_I2C_TYPE_WORD) { + buf[0] = addr >> 8; + buf[1] = addr; + } else if (addr_type == CAMERA_SENSOR_I2C_TYPE_3B) { + buf[0] = addr >> 16; + buf[1] = addr >> 8; + buf[2] = addr; + } else { + buf[0] = addr >> 24; + buf[1] = addr >> 16; + buf[2] = addr >> 8; + buf[3] = addr; + } + + rc = cam_qup_i2c_rxdata(client, buf, addr_type, data_type); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed rc: %d", rc); + goto read_fail; + } + + if (data_type == CAMERA_SENSOR_I2C_TYPE_BYTE) + *data = buf[0]; + else if (data_type == CAMERA_SENSOR_I2C_TYPE_WORD) + *data = buf[0] << 8 | buf[1]; + else if (data_type == CAMERA_SENSOR_I2C_TYPE_3B) + *data = buf[0] << 16 | buf[1] << 8 | buf[2]; + else + *data = buf[0] << 24 | buf[1] << 16 | + buf[2] << 8 | buf[3]; + + CAM_DBG(CAM_SENSOR, "addr = 0x%x data: 0x%x", addr, *data); +read_fail: + kfree(buf); + buf = NULL; + return rc; +} + +int32_t cam_qup_i2c_read_seq(struct i2c_client *client, + uint32_t addr, uint8_t *data, + enum camera_sensor_i2c_type addr_type, + uint32_t num_byte) +{ + int32_t rc = -EFAULT; + unsigned char *buf = NULL; + int i; + + if (addr_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX) { + CAM_ERR(CAM_SENSOR, "Failed with addr_type verification"); + return rc; + } + + if ((num_byte == 0) || (num_byte > I2C_REG_DATA_MAX)) { + CAM_ERR(CAM_SENSOR, "num_byte:0x%x max supported:0x%x", + num_byte, I2C_REG_DATA_MAX); + return rc; + } + + buf = kzalloc(addr_type + num_byte, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + if (addr_type == CAMERA_SENSOR_I2C_TYPE_BYTE) { + buf[0] = addr; + } else if (addr_type == CAMERA_SENSOR_I2C_TYPE_WORD) { + buf[0] = addr >> BITS_PER_BYTE; + buf[1] = addr; + } else if (addr_type == CAMERA_SENSOR_I2C_TYPE_3B) { + buf[0] = addr >> 16; + buf[1] = addr >> 8; + buf[2] = addr; + } else { + buf[0] = addr >> 24; + buf[1] = addr >> 16; + buf[2] = addr >> 8; + buf[3] = addr; + } + + rc = cam_qup_i2c_rxdata(client, buf, addr_type, num_byte); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed rc: %d", rc); + goto read_seq_fail; + } + + for (i = 0; i < num_byte; i++) + data[i] = buf[i]; + +read_seq_fail: + kfree(buf); + buf = NULL; + return rc; +} + +static int32_t cam_qup_i2c_compare(struct i2c_client *client, + uint32_t addr, uint32_t data, uint16_t data_mask, + enum camera_sensor_i2c_type data_type, + enum camera_sensor_i2c_type addr_type) +{ + int32_t rc; + uint32_t reg_data = 0; + + rc = cam_qup_i2c_read(client, addr, ®_data, + addr_type, data_type); + if (rc < 0) + return rc; + + reg_data = reg_data & 0xFFFF; + if (data != (reg_data & ~data_mask)) + return I2C_COMPARE_MISMATCH; + + return I2C_COMPARE_MATCH; +} + +int32_t cam_qup_i2c_poll(struct i2c_client *client, + uint32_t addr, uint16_t data, uint16_t data_mask, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type, + uint32_t delay_ms) +{ + int32_t rc = 0; + int i = 0; + + if ((delay_ms > MAX_POLL_DELAY_MS) || (delay_ms == 0)) { + CAM_ERR(CAM_SENSOR, "invalid delay = %d max_delay = %d", + delay_ms, MAX_POLL_DELAY_MS); + return -EINVAL; + } + + if ((addr_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX + || data_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || data_type >= CAMERA_SENSOR_I2C_TYPE_MAX)) + return -EINVAL; + + for (i = 0; i < delay_ms; i++) { + rc = cam_qup_i2c_compare(client, + addr, data, data_mask, data_type, addr_type); + if (rc == I2C_COMPARE_MATCH) + return rc; + + usleep_range(1000, 1010); + } + /* If rc is MISMATCH then read is successful but poll is failure */ + if (rc == I2C_COMPARE_MISMATCH) + CAM_ERR(CAM_SENSOR, "poll failed rc=%d(non-fatal)", rc); + if (rc < 0) + CAM_ERR(CAM_SENSOR, "poll failed rc=%d", rc); + + return rc; +} + +static int32_t cam_qup_i2c_write(struct camera_io_master *client, + struct cam_sensor_i2c_reg_array *reg_setting, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type) +{ + int32_t rc = 0; + unsigned char *buf = NULL; + uint8_t len = 0; + + buf = kzalloc(I2C_REG_MAX_BUF_SIZE, GFP_KERNEL | GFP_DMA); + if (!buf) { + CAM_ERR(CAM_SENSOR, "Buffer memory allocation failed"); + return -ENOMEM; + } + + CAM_DBG(CAM_SENSOR, "reg addr = 0x%x data type: %d", + reg_setting->reg_addr, data_type); + if (addr_type == CAMERA_SENSOR_I2C_TYPE_BYTE) { + buf[0] = reg_setting->reg_addr; + CAM_DBG(CAM_SENSOR, "byte %d: 0x%x", len, buf[len]); + len = 1; + } else if (addr_type == CAMERA_SENSOR_I2C_TYPE_WORD) { + buf[0] = reg_setting->reg_addr >> 8; + buf[1] = reg_setting->reg_addr; + CAM_DBG(CAM_SENSOR, "byte %d: 0x%x", len, buf[len]); + CAM_DBG(CAM_SENSOR, "byte %d: 0x%x", len+1, buf[len+1]); + len = 2; + } else if (addr_type == CAMERA_SENSOR_I2C_TYPE_3B) { + buf[0] = reg_setting->reg_addr >> 16; + buf[1] = reg_setting->reg_addr >> 8; + buf[2] = reg_setting->reg_addr; + len = 3; + } else if (addr_type == CAMERA_SENSOR_I2C_TYPE_DWORD) { + buf[0] = reg_setting->reg_addr >> 24; + buf[1] = reg_setting->reg_addr >> 16; + buf[2] = reg_setting->reg_addr >> 8; + buf[3] = reg_setting->reg_addr; + len = 4; + } else { + CAM_ERR(CAM_SENSOR, "Invalid I2C addr type"); + rc = -EINVAL; + goto deallocate_buffer; + } + + CAM_DBG(CAM_SENSOR, "Data: 0x%x", reg_setting->reg_data); + if (data_type == CAMERA_SENSOR_I2C_TYPE_BYTE) { + buf[len] = reg_setting->reg_data; + CAM_DBG(CAM_SENSOR, "Byte %d: 0x%x", len, buf[len]); + len += 1; + } else if (data_type == CAMERA_SENSOR_I2C_TYPE_WORD) { + buf[len] = reg_setting->reg_data >> 8; + buf[len+1] = reg_setting->reg_data; + CAM_DBG(CAM_SENSOR, "Byte %d: 0x%x", len, buf[len]); + CAM_DBG(CAM_SENSOR, "Byte %d: 0x%x", len+1, buf[len+1]); + len += 2; + } else if (data_type == CAMERA_SENSOR_I2C_TYPE_3B) { + buf[len] = reg_setting->reg_data >> 16; + buf[len + 1] = reg_setting->reg_data >> 8; + buf[len + 2] = reg_setting->reg_data; + CAM_DBG(CAM_SENSOR, "Byte %d: 0x%x", len, buf[len]); + CAM_DBG(CAM_SENSOR, "Byte %d: 0x%x", len+1, buf[len+1]); + CAM_DBG(CAM_SENSOR, "Byte %d: 0x%x", len+2, buf[len+2]); + len += 3; + } else if (data_type == CAMERA_SENSOR_I2C_TYPE_DWORD) { + buf[len] = reg_setting->reg_data >> 24; + buf[len + 1] = reg_setting->reg_data >> 16; + buf[len + 2] = reg_setting->reg_data >> 8; + buf[len + 3] = reg_setting->reg_data; + CAM_DBG(CAM_SENSOR, "Byte %d: 0x%x", len, buf[len]); + CAM_DBG(CAM_SENSOR, "Byte %d: 0x%x", len+1, buf[len+1]); + CAM_DBG(CAM_SENSOR, "Byte %d: 0x%x", len+2, buf[len+2]); + CAM_DBG(CAM_SENSOR, "Byte %d: 0x%x", len+3, buf[len+3]); + len += 4; + } else { + CAM_ERR(CAM_SENSOR, "Invalid Data Type"); + rc = -EINVAL; + goto deallocate_buffer; + } + + rc = cam_qup_i2c_txdata(client, buf, len); + if (rc < 0) + CAM_ERR(CAM_SENSOR, "failed rc: %d", rc); + +deallocate_buffer: + kfree(buf); + return rc; +} + +int32_t cam_qup_i2c_write_table(struct camera_io_master *client, + struct cam_sensor_i2c_reg_setting *write_setting) +{ + int i; + int32_t rc = -EINVAL; + struct cam_sensor_i2c_reg_array *reg_setting; + + if (!client || !write_setting) + return rc; + + if ((write_setting->addr_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || write_setting->addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX + || (write_setting->data_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || write_setting->data_type >= CAMERA_SENSOR_I2C_TYPE_MAX))) + return rc; + + reg_setting = write_setting->reg_setting; + + for (i = 0; i < write_setting->size; i++) { + CAM_DBG(CAM_SENSOR, "addr 0x%x data 0x%x", + reg_setting->reg_addr, reg_setting->reg_data); + + rc = cam_qup_i2c_write(client, reg_setting, + write_setting->addr_type, write_setting->data_type); + if (rc < 0) + break; + reg_setting++; + } + + if (write_setting->delay > 20) + msleep(write_setting->delay); + else if (write_setting->delay) + usleep_range(write_setting->delay * 1000, (write_setting->delay + * 1000) + 1000); + + return rc; +} + +static int32_t cam_qup_i2c_write_seq(struct camera_io_master *client, + struct cam_sensor_i2c_reg_setting *write_setting) +{ + int i; + int32_t rc = 0; + struct cam_sensor_i2c_reg_array *reg_setting; + + reg_setting = write_setting->reg_setting; + + for (i = 0; i < write_setting->size; i++) { + reg_setting->reg_addr += i; + rc = cam_qup_i2c_write(client, reg_setting, + write_setting->addr_type, write_setting->data_type); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Sequential i2c write failed: rc: %d", rc); + break; + } + reg_setting++; + } + + if (write_setting->delay > 20) + msleep(write_setting->delay); + else if (write_setting->delay) + usleep_range(write_setting->delay * 1000, (write_setting->delay + * 1000) + 1000); + + return rc; +} + +static int32_t cam_qup_i2c_write_burst(struct camera_io_master *client, + struct cam_sensor_i2c_reg_setting *write_setting) +{ + int i; + int32_t rc = 0; + uint32_t len = 0; + unsigned char *buf = NULL; + struct cam_sensor_i2c_reg_array *reg_setting; + enum camera_sensor_i2c_type addr_type; + enum camera_sensor_i2c_type data_type; + + buf = kzalloc((write_setting->addr_type + + (write_setting->size * write_setting->data_type)), + GFP_KERNEL); + + if (!buf) { + CAM_ERR(CAM_SENSOR, "BUF is NULL"); + return -ENOMEM; + } + + reg_setting = write_setting->reg_setting; + addr_type = write_setting->addr_type; + data_type = write_setting->data_type; + + CAM_DBG(CAM_SENSOR, "reg addr = 0x%x data type: %d", + reg_setting->reg_addr, data_type); + if (addr_type == CAMERA_SENSOR_I2C_TYPE_BYTE) { + buf[0] = reg_setting->reg_addr; + CAM_DBG(CAM_SENSOR, "byte %d: 0x%x", len, buf[len]); + len = 1; + } else if (addr_type == CAMERA_SENSOR_I2C_TYPE_WORD) { + buf[0] = reg_setting->reg_addr >> 8; + buf[1] = reg_setting->reg_addr; + CAM_DBG(CAM_SENSOR, "byte %d: 0x%x", len, buf[len]); + CAM_DBG(CAM_SENSOR, "byte %d: 0x%x", len+1, buf[len+1]); + len = 2; + } else if (addr_type == CAMERA_SENSOR_I2C_TYPE_3B) { + buf[0] = reg_setting->reg_addr >> 16; + buf[1] = reg_setting->reg_addr >> 8; + buf[2] = reg_setting->reg_addr; + len = 3; + } else if (addr_type == CAMERA_SENSOR_I2C_TYPE_DWORD) { + buf[0] = reg_setting->reg_addr >> 24; + buf[1] = reg_setting->reg_addr >> 16; + buf[2] = reg_setting->reg_addr >> 8; + buf[3] = reg_setting->reg_addr; + len = 4; + } else { + CAM_ERR(CAM_SENSOR, "Invalid I2C addr type"); + rc = -EINVAL; + goto free_res; + } + + for (i = 0; i < write_setting->size; i++) { + if (data_type == CAMERA_SENSOR_I2C_TYPE_BYTE) { + buf[len] = reg_setting->reg_data; + CAM_DBG(CAM_SENSOR, + "Byte %d: 0x%x", len, buf[len]); + len += 1; + } else if (data_type == CAMERA_SENSOR_I2C_TYPE_WORD) { + buf[len] = reg_setting->reg_data >> 8; + buf[len+1] = reg_setting->reg_data; + CAM_DBG(CAM_SENSOR, + "Byte %d: 0x%x", len, buf[len]); + CAM_DBG(CAM_SENSOR, + "Byte %d: 0x%x", len+1, buf[len+1]); + len += 2; + } else if (data_type == CAMERA_SENSOR_I2C_TYPE_3B) { + buf[len] = reg_setting->reg_data >> 16; + buf[len + 1] = reg_setting->reg_data >> 8; + buf[len + 2] = reg_setting->reg_data; + CAM_DBG(CAM_SENSOR, + "Byte %d: 0x%x", len, buf[len]); + CAM_DBG(CAM_SENSOR, + "Byte %d: 0x%x", len+1, buf[len+1]); + CAM_DBG(CAM_SENSOR, + "Byte %d: 0x%x", len+2, buf[len+2]); + len += 3; + } else if (data_type == CAMERA_SENSOR_I2C_TYPE_DWORD) { + buf[len] = reg_setting->reg_data >> 24; + buf[len + 1] = reg_setting->reg_data >> 16; + buf[len + 2] = reg_setting->reg_data >> 8; + buf[len + 3] = reg_setting->reg_data; + CAM_DBG(CAM_SENSOR, + "Byte %d: 0x%x", len, buf[len]); + CAM_DBG(CAM_SENSOR, + "Byte %d: 0x%x", len+1, buf[len+1]); + CAM_DBG(CAM_SENSOR, + "Byte %d: 0x%x", len+2, buf[len+2]); + CAM_DBG(CAM_SENSOR, + "Byte %d: 0x%x", len+3, buf[len+3]); + len += 4; + } else { + CAM_ERR(CAM_SENSOR, "Invalid Data Type"); + rc = -EINVAL; + goto free_res; + } + reg_setting++; + } + + if (len > (write_setting->addr_type + + (write_setting->size * write_setting->data_type))) { + CAM_ERR(CAM_SENSOR, "Invalid Length: %u | Expected length: %u", + len, (write_setting->addr_type + + (write_setting->size * write_setting->data_type))); + rc = -EINVAL; + goto free_res; + } + + rc = cam_qup_i2c_txdata(client, buf, len); + if (rc < 0) + CAM_ERR(CAM_SENSOR, "failed rc: %d", rc); + +free_res: + kfree(buf); + return rc; +} + +int32_t cam_qup_i2c_write_continuous_table(struct camera_io_master *client, + struct cam_sensor_i2c_reg_setting *write_settings, + uint8_t cam_sensor_i2c_write_flag) +{ + int32_t rc = 0; + + if (!client || !write_settings) + return -EINVAL; + + if ((write_settings->addr_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || write_settings->addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX + || (write_settings->data_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || write_settings->data_type >= CAMERA_SENSOR_I2C_TYPE_MAX))) + return -EINVAL; + + if (cam_sensor_i2c_write_flag == CAM_SENSOR_I2C_WRITE_BURST) + rc = cam_qup_i2c_write_burst(client, write_settings); + else if (cam_sensor_i2c_write_flag == CAM_SENSOR_I2C_WRITE_SEQ) + rc = cam_qup_i2c_write_seq(client, write_settings); + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_spi.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..cf6987b09eacfb2c7f483daa29a785e97923595d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_spi.c @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_sensor_spi.h" +#include "cam_debug_util.h" + +static int cam_spi_txfr(struct spi_device *spi, char *txbuf, + char *rxbuf, int num_byte) +{ + struct spi_transfer txfr; + struct spi_message msg; + + memset(&txfr, 0, sizeof(txfr)); + txfr.tx_buf = txbuf; + txfr.rx_buf = rxbuf; + txfr.len = num_byte; + spi_message_init(&msg); + spi_message_add_tail(&txfr, &msg); + + return spi_sync(spi, &msg); +} + +static int cam_spi_txfr_read(struct spi_device *spi, char *txbuf, + char *rxbuf, int txlen, int rxlen) +{ + struct spi_transfer tx; + struct spi_transfer rx; + struct spi_message m; + + memset(&tx, 0, sizeof(tx)); + memset(&rx, 0, sizeof(rx)); + tx.tx_buf = txbuf; + rx.rx_buf = rxbuf; + tx.len = txlen; + rx.len = rxlen; + spi_message_init(&m); + spi_message_add_tail(&tx, &m); + spi_message_add_tail(&rx, &m); + return spi_sync(spi, &m); +} + +/** + * cam_set_addr() - helper function to set transfer address + * @addr: device address + * @addr_len: the addr field length of an instruction + * @type: type (i.e. byte-length) of @addr + * @str: shifted address output, must be zeroed when passed in + * + * This helper function sets @str based on the addr field length of an + * instruction and the data length. + */ +static void cam_set_addr(uint32_t addr, uint8_t addr_len, + enum camera_sensor_i2c_type addr_type, + char *str) +{ + if (!addr_len) + return; + + if (addr_type == CAMERA_SENSOR_I2C_TYPE_BYTE) { + str[0] = addr; + } else if (addr_type == CAMERA_SENSOR_I2C_TYPE_WORD) { + str[0] = addr >> 8; + str[1] = addr; + } else if (addr_type == CAMERA_SENSOR_I2C_TYPE_3B) { + str[0] = addr >> 16; + str[1] = addr >> 8; + str[2] = addr; + } else { + str[0] = addr >> 24; + str[1] = addr >> 16; + str[2] = addr >> 8; + str[3] = addr; + } +} + +/** + * cam_spi_tx_helper() - wrapper for SPI transaction + * @client: io client + * @inst: inst of this transaction + * @addr: device addr following the inst + * @data: output byte array (could be NULL) + * @num_byte: size of @data + * @tx, rx: optional transfer buffer. It must be at least header + * + @num_byte long. + * + * This is the core function for SPI transaction, except for writes. It first + * checks address type, then allocates required memory for tx/rx buffers. + * It sends out , and optionally receives @num_byte of response, + * if @data is not NULL. This function does not check for wait conditions, + * and will return immediately once bus transaction finishes. + * + * This function will allocate buffers of header + @num_byte long. For + * large transfers, the allocation could fail. External buffer @tx, @rx + * should be passed in to bypass allocation. The size of buffer should be + * at least header + num_byte long. Since buffer is managed externally, + * @data will be ignored, and read results will be in @rx. + * @tx, @rx also can be used for repeated transfers to improve performance. + */ +static int32_t cam_spi_tx_helper(struct camera_io_master *client, + struct cam_camera_spi_inst *inst, uint32_t addr, uint8_t *data, + enum camera_sensor_i2c_type addr_type, + uint32_t num_byte, char *tx, char *rx) +{ + int32_t rc = -EINVAL; + struct spi_device *spi = client->spi_client->spi_master; + struct device *dev = NULL; + char *ctx = NULL, *crx = NULL; + uint32_t len, hlen; + uint8_t retries = client->spi_client->retries; + uint32_t txr = 0, rxr = 0; + struct page *page_tx = NULL, *page_rx = NULL; + + hlen = cam_camera_spi_get_hlen(inst); + len = hlen + num_byte; + dev = &(spi->dev); + + if (!dev) { + CAM_ERR(CAM_SENSOR, "Invalid arguments"); + return -EINVAL; + } + + if (tx) { + ctx = tx; + } else { + txr = PAGE_ALIGN(len) >> PAGE_SHIFT; + page_tx = cma_alloc(dev_get_cma_area(dev), + txr, 0, GFP_KERNEL); + if (!page_tx) + return -ENOMEM; + + ctx = page_address(page_tx); + } + + if (num_byte) { + if (rx) { + crx = rx; + } else { + rxr = PAGE_ALIGN(len) >> PAGE_SHIFT; + page_rx = cma_alloc(dev_get_cma_area(dev), + rxr, 0, GFP_KERNEL); + if (!page_rx) { + if (!tx) + cma_release(dev_get_cma_area(dev), + page_tx, txr); + + return -ENOMEM; + } + crx = page_address(page_rx); + } + } else { + crx = NULL; + } + + ctx[0] = inst->opcode; + cam_set_addr(addr, inst->addr_len, addr_type, ctx + 1); + while ((rc = cam_spi_txfr(spi, ctx, crx, len)) && retries) { + retries--; + msleep(client->spi_client->retry_delay); + } + if (rc < 0) { + CAM_ERR(CAM_EEPROM, "failed: spi txfr rc %d", rc); + goto out; + } + if (data && num_byte && !rx) + memcpy(data, crx + hlen, num_byte); + +out: + if (!tx) + cma_release(dev_get_cma_area(dev), page_tx, txr); + if (!rx) + cma_release(dev_get_cma_area(dev), page_rx, rxr); + return rc; +} + +static int32_t cam_spi_tx_read(struct camera_io_master *client, + struct cam_camera_spi_inst *inst, uint32_t addr, uint8_t *data, + enum camera_sensor_i2c_type addr_type, + uint32_t num_byte, char *tx, char *rx) +{ + int32_t rc = -EINVAL; + struct spi_device *spi = client->spi_client->spi_master; + char *ctx = NULL, *crx = NULL; + uint32_t hlen; + uint8_t retries = client->spi_client->retries; + + hlen = cam_camera_spi_get_hlen(inst); + if (tx) { + ctx = tx; + } else { + ctx = kzalloc(hlen, GFP_KERNEL | GFP_DMA); + if (!ctx) + return -ENOMEM; + } + if (num_byte) { + if (rx) { + crx = rx; + } else { + crx = kzalloc(num_byte, GFP_KERNEL | GFP_DMA); + if (!crx) { + if (!tx) + kfree(ctx); + return -ENOMEM; + } + } + } else { + crx = NULL; + } + + ctx[0] = inst->opcode; + cam_set_addr(addr, inst->addr_len, addr_type, ctx + 1); + + CAM_DBG(CAM_EEPROM, "tx(%u): %02x %02x %02x %02x", hlen, ctx[0], + ctx[1], ctx[2], ctx[3]); + while ((rc = cam_spi_txfr_read(spi, ctx, crx, hlen, num_byte)) + && retries) { + retries--; + msleep(client->spi_client->retry_delay); + } + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed %d", rc); + goto out; + } + if (data && num_byte && !rx) + memcpy(data, crx, num_byte); +out: + if (!tx) + kfree(ctx); + if (!rx) + kfree(crx); + return rc; +} + +int cam_spi_read(struct camera_io_master *client, + uint32_t addr, uint32_t *data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type) +{ + int rc = -EINVAL; + uint8_t temp[CAMERA_SENSOR_I2C_TYPE_MAX]; + + if (addr_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX + || data_type <= CAMERA_SENSOR_I2C_TYPE_INVALID + || data_type >= CAMERA_SENSOR_I2C_TYPE_MAX) { + CAM_ERR(CAM_SENSOR, "Failed with addr/data_type verification"); + return rc; + } + + rc = cam_spi_tx_read(client, + &client->spi_client->cmd_tbl.read, addr, &temp[0], + addr_type, data_type, NULL, NULL); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed %d", rc); + return rc; + } + + if (data_type == CAMERA_SENSOR_I2C_TYPE_BYTE) + *data = temp[0]; + else if (data_type == CAMERA_SENSOR_I2C_TYPE_WORD) + *data = (temp[0] << BITS_PER_BYTE) | temp[1]; + else if (data_type == CAMERA_SENSOR_I2C_TYPE_3B) + *data = (temp[0] << 16 | temp[1] << 8 | temp[2]); + else + *data = (temp[0] << 24 | temp[1] << 16 | temp[2] << 8 | + temp[3]); + + CAM_DBG(CAM_SENSOR, "addr 0x%x, data %u", addr, *data); + return rc; +} + +int32_t cam_spi_read_seq(struct camera_io_master *client, + uint32_t addr, uint8_t *data, + enum camera_sensor_i2c_type addr_type, int32_t num_bytes) +{ + if ((addr_type <= CAMERA_SENSOR_I2C_TYPE_INVALID) + || (addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX)) { + CAM_ERR(CAM_SENSOR, "Failed with addr_type verification"); + return -EINVAL; + } + + if (num_bytes == 0) { + CAM_ERR(CAM_SENSOR, "num_byte: 0x%x", num_bytes); + return -EINVAL; + } + + CAM_DBG(CAM_SENSOR, "Read Seq addr: 0x%x NB:%d", + addr, num_bytes); + return cam_spi_tx_helper(client, + &client->spi_client->cmd_tbl.read_seq, addr, data, + addr_type, num_bytes, NULL, NULL); +} + +int cam_spi_query_id(struct camera_io_master *client, + uint32_t addr, enum camera_sensor_i2c_type addr_type, + uint8_t *data, uint32_t num_byte) +{ + CAM_DBG(CAM_SENSOR, "SPI Queryid : 0x%x, addr: 0x%x", + client->spi_client->cmd_tbl.query_id, addr); + return cam_spi_tx_helper(client, + &client->spi_client->cmd_tbl.query_id, + addr, data, addr_type, num_byte, NULL, NULL); +} + +static int32_t cam_spi_read_status_reg( + struct camera_io_master *client, uint8_t *status, + enum camera_sensor_i2c_type addr_type) +{ + struct cam_camera_spi_inst *rs = + &client->spi_client->cmd_tbl.read_status; + + if (rs->addr_len != 0) { + CAM_ERR(CAM_SENSOR, "not implemented yet"); + return -ENXIO; + } + return cam_spi_tx_helper(client, rs, 0, status, + addr_type, 1, NULL, NULL); +} + +static int32_t cam_spi_device_busy(struct camera_io_master *client, + uint8_t *busy, enum camera_sensor_i2c_type addr_type) +{ + int rc; + uint8_t st = 0; + + rc = cam_spi_read_status_reg(client, &st, addr_type); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed to read status reg"); + return rc; + } + *busy = st & client->spi_client->busy_mask; + return 0; +} + +static int32_t cam_spi_wait(struct camera_io_master *client, + struct cam_camera_spi_inst *inst, + enum camera_sensor_i2c_type addr_type) +{ + uint8_t busy; + int i, rc; + + CAM_DBG(CAM_SENSOR, "op 0x%x wait start", inst->opcode); + for (i = 0; i < inst->delay_count; i++) { + rc = cam_spi_device_busy(client, &busy, addr_type); + if (rc < 0) + return rc; + if (!busy) + break; + msleep(inst->delay_intv); + CAM_DBG(CAM_SENSOR, "op 0x%x wait", inst->opcode); + } + if (i > inst->delay_count) { + CAM_ERR(CAM_SENSOR, "op %x timed out", inst->opcode); + return -ETIMEDOUT; + } + CAM_DBG(CAM_SENSOR, "op %x finished", inst->opcode); + return 0; +} + +static int32_t cam_spi_write_enable(struct camera_io_master *client, + enum camera_sensor_i2c_type addr_type) +{ + struct cam_camera_spi_inst *we = + &client->spi_client->cmd_tbl.write_enable; + int rc; + + if (we->opcode == 0) + return 0; + if (we->addr_len != 0) { + CAM_ERR(CAM_SENSOR, "not implemented yet"); + return -EINVAL; + } + rc = cam_spi_tx_helper(client, we, 0, NULL, addr_type, + 0, NULL, NULL); + if (rc < 0) + CAM_ERR(CAM_SENSOR, "write enable failed"); + return rc; +} + +/** + * cam_spi_page_program() - core function to perform write + * @client: need for obtaining SPI device + * @addr: address to program on device + * @data: data to write + * @len: size of data + * @tx: tx buffer, size >= header + len + * + * This function performs SPI write, and has no boundary check. Writing range + * should not cross page boundary, or data will be corrupted. Transaction is + * guaranteed to be finished when it returns. This function should never be + * used outside cam_spi_write_seq(). + */ +static int32_t cam_spi_page_program(struct camera_io_master *client, + uint32_t addr, uint8_t *data, + enum camera_sensor_i2c_type addr_type, + uint16_t len, uint8_t *tx) +{ + int rc; + struct cam_camera_spi_inst *pg = + &client->spi_client->cmd_tbl.page_program; + struct spi_device *spi = client->spi_client->spi_master; + uint8_t retries = client->spi_client->retries; + uint8_t header_len = sizeof(pg->opcode) + pg->addr_len + pg->dummy_len; + + CAM_DBG(CAM_SENSOR, "addr 0x%x, size 0x%x", addr, len); + rc = cam_spi_write_enable(client, addr_type); + if (rc < 0) + return rc; + memset(tx, 0, header_len); + tx[0] = pg->opcode; + cam_set_addr(addr, pg->addr_len, addr_type, tx + 1); + memcpy(tx + header_len, data, len); + CAM_DBG(CAM_SENSOR, "tx(%u): %02x %02x %02x %02x", + len, tx[0], tx[1], tx[2], tx[3]); + while ((rc = spi_write(spi, tx, len + header_len)) && retries) { + rc = cam_spi_wait(client, pg, addr_type); + msleep(client->spi_client->retry_delay); + retries--; + } + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed %d", rc); + return rc; + } + rc = cam_spi_wait(client, pg, addr_type); + return rc; +} + +int cam_spi_write(struct camera_io_master *client, + uint32_t addr, uint32_t data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type) +{ + struct cam_camera_spi_inst *pg = + &client->spi_client->cmd_tbl.page_program; + uint8_t header_len = sizeof(pg->opcode) + pg->addr_len + pg->dummy_len; + uint16_t len = 0; + char buf[CAMERA_SENSOR_I2C_TYPE_MAX]; + char *tx; + int rc = -EINVAL; + + if ((addr_type <= CAMERA_SENSOR_I2C_TYPE_INVALID) + || (addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX) + || (data_type <= CAMERA_SENSOR_I2C_TYPE_INVALID) + || (data_type != CAMERA_SENSOR_I2C_TYPE_MAX)) + return rc; + + CAM_DBG(CAM_EEPROM, "Data: 0x%x", data); + len = header_len + (uint8_t)data_type; + tx = kmalloc(len, GFP_KERNEL | GFP_DMA); + if (!tx) + goto NOMEM; + + if (data_type == CAMERA_SENSOR_I2C_TYPE_BYTE) { + buf[0] = data; + CAM_DBG(CAM_EEPROM, "Byte %d: 0x%x", len, buf[0]); + } else if (data_type == CAMERA_SENSOR_I2C_TYPE_WORD) { + buf[0] = (data >> BITS_PER_BYTE) & 0x00FF; + buf[1] = (data & 0x00FF); + } else if (data_type == CAMERA_SENSOR_I2C_TYPE_3B) { + buf[0] = (data >> 16) & 0x00FF; + buf[1] = (data >> 8) & 0x00FF; + buf[2] = (data & 0x00FF); + } else { + buf[0] = (data >> 24) & 0x00FF; + buf[1] = (data >> 16) & 0x00FF; + buf[2] = (data >> 8) & 0x00FF; + buf[3] = (data & 0x00FF); + } + + rc = cam_spi_page_program(client, addr, buf, + addr_type, data_type, tx); + if (rc < 0) + goto ERROR; + goto OUT; +NOMEM: + CAM_ERR(CAM_SENSOR, "memory allocation failed"); + return -ENOMEM; +ERROR: + CAM_ERR(CAM_SENSOR, "error write"); +OUT: + kfree(tx); + return rc; +} + +int32_t cam_spi_write_seq(struct camera_io_master *client, + uint32_t addr, uint8_t *data, + enum camera_sensor_i2c_type addr_type, uint32_t num_byte) +{ + struct cam_camera_spi_inst *pg = + &client->spi_client->cmd_tbl.page_program; + const uint32_t page_size = client->spi_client->page_size; + uint8_t header_len = sizeof(pg->opcode) + pg->addr_len + pg->dummy_len; + uint16_t len; + uint32_t cur_len, end; + char *tx, *pdata = data; + int rc = -EINVAL; + + if ((addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX) || + (addr_type <= CAMERA_SENSOR_I2C_TYPE_INVALID)) + return rc; + /* single page write */ + if ((addr % page_size) + num_byte <= page_size) { + len = header_len + num_byte; + tx = kmalloc(len, GFP_KERNEL | GFP_DMA); + if (!tx) + goto NOMEM; + rc = cam_spi_page_program(client, addr, data, addr_type, + num_byte, tx); + if (rc < 0) + goto ERROR; + goto OUT; + } + /* multi page write */ + len = header_len + page_size; + tx = kmalloc(len, GFP_KERNEL | GFP_DMA); + if (!tx) + goto NOMEM; + while (num_byte) { + end = min(page_size, (addr % page_size) + num_byte); + cur_len = end - (addr % page_size); + CAM_ERR(CAM_SENSOR, "Addr: 0x%x curr_len: 0x%x pgSize: %d", + addr, cur_len, page_size); + rc = cam_spi_page_program(client, addr, pdata, addr_type, + cur_len, tx); + if (rc < 0) + goto ERROR; + addr += cur_len; + pdata += cur_len; + num_byte -= cur_len; + } + goto OUT; +NOMEM: + pr_err("%s: memory allocation failed\n", __func__); + return -ENOMEM; +ERROR: + pr_err("%s: error write\n", __func__); +OUT: + kfree(tx); + return rc; +} + +int cam_spi_write_table(struct camera_io_master *client, + struct cam_sensor_i2c_reg_setting *write_setting) +{ + int i; + int rc = -EFAULT; + struct cam_sensor_i2c_reg_array *reg_setting; + uint16_t client_addr_type; + enum camera_sensor_i2c_type addr_type; + + if (!client || !write_setting) + return rc; + + if ((write_setting->addr_type <= CAMERA_SENSOR_I2C_TYPE_INVALID) + || (write_setting->addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX) + || (write_setting->data_type <= CAMERA_SENSOR_I2C_TYPE_INVALID) + || (write_setting->data_type >= CAMERA_SENSOR_I2C_TYPE_MAX)) + return rc; + + reg_setting = write_setting->reg_setting; + client_addr_type = write_setting->addr_type; + addr_type = write_setting->addr_type; + for (i = 0; i < write_setting->size; i++) { + CAM_DBG(CAM_SENSOR, "addr %x data %x", + reg_setting->reg_addr, reg_setting->reg_data); + rc = cam_spi_write(client, + reg_setting->reg_addr, reg_setting->reg_data, + write_setting->addr_type, write_setting->data_type); + if (rc < 0) + break; + reg_setting++; + } + if (write_setting->delay > 20) + msleep(write_setting->delay); + else if (write_setting->delay) + usleep_range(write_setting->delay * 1000, + (write_setting->delay + * 1000) + 1000); + addr_type = client_addr_type; + return rc; +} + +int cam_spi_erase(struct camera_io_master *client, uint32_t addr, + enum camera_sensor_i2c_type addr_type, uint32_t size) +{ + struct cam_camera_spi_inst *se = &client->spi_client->cmd_tbl.erase; + int rc = 0; + uint32_t cur; + uint32_t end = addr + size; + uint32_t erase_size = client->spi_client->erase_size; + + end = addr + size; + for (cur = rounddown(addr, erase_size); cur < end; cur += erase_size) { + CAM_ERR(CAM_SENSOR, "%s: erasing 0x%x size: %d\n", + __func__, cur, erase_size); + rc = cam_spi_write_enable(client, addr_type); + if (rc < 0) + return rc; + rc = cam_spi_tx_helper(client, se, cur, NULL, addr_type, 0, + NULL, NULL); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "%s: erase failed\n", __func__); + return rc; + } + rc = cam_spi_wait(client, se, addr_type); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "%s: erase timedout\n", __func__); + return rc; + } + } + + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_spi.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..73d7ea9456bad9b33adea82ff5d818d442824763 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_spi.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_SENSOR_SPI_H_ +#define _CAM_SENSOR_SPI_H_ + +#include +#include +#include +#include "cam_sensor_i2c.h" + +#define MAX_SPI_SIZE 110 +#define SPI_DYNAMIC_ALLOC + +struct cam_camera_spi_inst { + uint8_t opcode; + uint8_t addr_len; + uint8_t dummy_len; + uint8_t delay_intv; + uint8_t delay_count; +}; + +struct cam_spi_write_burst_data { + u8 data_msb; + u8 data_lsb; +}; + +struct cam_spi_write_burst_packet { + u8 cmd; + u8 addr_msb; + u8 addr_lsb; + struct cam_spi_write_burst_data data_arr[MAX_SPI_SIZE]; +}; + +struct cam_camera_burst_info { + uint32_t burst_addr; + uint32_t burst_start; + uint32_t burst_len; + uint32_t chunk_size; +}; + +struct cam_camera_spi_inst_tbl { + struct cam_camera_spi_inst read; + struct cam_camera_spi_inst read_seq; + struct cam_camera_spi_inst query_id; + struct cam_camera_spi_inst page_program; + struct cam_camera_spi_inst write_enable; + struct cam_camera_spi_inst read_status; + struct cam_camera_spi_inst erase; +}; + +struct cam_sensor_spi_client { + struct spi_device *spi_master; + struct cam_camera_spi_inst_tbl cmd_tbl; + uint8_t device_id0; + uint8_t device_id1; + uint8_t mfr_id0; + uint8_t mfr_id1; + uint8_t retry_delay; + uint8_t retries; + uint8_t busy_mask; + uint16_t page_size; + uint32_t erase_size; +}; +static __always_inline +uint16_t cam_camera_spi_get_hlen(struct cam_camera_spi_inst *inst) +{ + return sizeof(inst->opcode) + inst->addr_len + inst->dummy_len; +} + +int cam_spi_read(struct camera_io_master *client, + uint32_t addr, uint32_t *data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type); + +int cam_spi_read_seq(struct camera_io_master *client, + uint32_t addr, uint8_t *data, + enum camera_sensor_i2c_type addr_type, + int32_t num_bytes); + +int cam_spi_query_id(struct camera_io_master *client, + uint32_t addr, + enum camera_sensor_i2c_type addr_type, + uint8_t *data, uint32_t num_byte); + +int cam_spi_write(struct camera_io_master *client, + uint32_t addr, uint32_t data, + enum camera_sensor_i2c_type addr_type, + enum camera_sensor_i2c_type data_type); + +int cam_spi_write_table(struct camera_io_master *client, + struct cam_sensor_i2c_reg_setting *write_setting); + +int cam_spi_erase(struct camera_io_master *client, + uint32_t addr, enum camera_sensor_i2c_type addr_type, + uint32_t size); + +int cam_spi_write_seq(struct camera_io_master *client, + uint32_t addr, uint8_t *data, + enum camera_sensor_i2c_type addr_type, uint32_t num_byte); +#endif diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..8e22bed393c6136fcdc8bf799ab3571daff75e1a --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(src) + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_util.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h new file mode 100644 index 0000000000000000000000000000000000000000..563414e640cc0014cdc57ff7e6334e6bcecc2253 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h @@ -0,0 +1,403 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_SENSOR_CMN_HEADER_ +#define _CAM_SENSOR_CMN_HEADER_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_REGULATOR 5 +#define MAX_POWER_CONFIG 12 + +#define MAX_PER_FRAME_ARRAY 32 +#define BATCH_SIZE_MAX 16 + +#define CAM_SENSOR_NAME "cam-sensor" +#define CAM_ACTUATOR_NAME "cam-actuator" +#define CAM_CSIPHY_NAME "cam-csiphy" +#define CAM_FLASH_NAME "cam-flash" +#define CAM_EEPROM_NAME "cam-eeprom" +#define CAM_OIS_NAME "cam-ois" + +#define MAX_SYSTEM_PIPELINE_DELAY 2 + +#define CAM_PKT_NOP_OPCODE 127 + +enum camera_sensor_cmd_type { + CAMERA_SENSOR_CMD_TYPE_INVALID, + CAMERA_SENSOR_CMD_TYPE_PROBE, + CAMERA_SENSOR_CMD_TYPE_PWR_UP, + CAMERA_SENSOR_CMD_TYPE_PWR_DOWN, + CAMERA_SENSOR_CMD_TYPE_I2C_INFO, + CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_WR, + CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_RD, + CAMERA_SENSOR_CMD_TYPE_I2C_CONT_WR, + CAMERA_SENSOR_CMD_TYPE_I2C_CONT_RD, + CAMERA_SENSOR_CMD_TYPE_WAIT, + CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_INFO, + CAMERA_SENSOR_FLASH_CMD_TYPE_FIRE, + CAMERA_SENSOR_FLASH_CMD_TYPE_RER, + CAMERA_SENSOR_FLASH_CMD_TYPE_QUERYCURR, + CAMERA_SENSOR_FLASH_CMD_TYPE_WIDGET, + CAMERA_SENSOR_CMD_TYPE_RD_DATA, + CAMERA_SENSOR_FLASH_CMD_TYPE_INIT_FIRE, + CAMERA_SENSOR_CMD_TYPE_MAX, +}; + +enum camera_sensor_i2c_op_code { + CAMERA_SENSOR_I2C_OP_INVALID, + CAMERA_SENSOR_I2C_OP_RNDM_WR, + CAMERA_SENSOR_I2C_OP_RNDM_WR_VERF, + CAMERA_SENSOR_I2C_OP_CONT_WR_BRST, + CAMERA_SENSOR_I2C_OP_CONT_WR_BRST_VERF, + CAMERA_SENSOR_I2C_OP_CONT_WR_SEQN, + CAMERA_SENSOR_I2C_OP_CONT_WR_SEQN_VERF, + CAMERA_SENSOR_I2C_OP_MAX, +}; + +enum camera_sensor_wait_op_code { + CAMERA_SENSOR_WAIT_OP_INVALID, + CAMERA_SENSOR_WAIT_OP_COND, + CAMERA_SENSOR_WAIT_OP_HW_UCND, + CAMERA_SENSOR_WAIT_OP_SW_UCND, + CAMERA_SENSOR_WAIT_OP_MAX, +}; + +enum camera_flash_opcode { + CAMERA_SENSOR_FLASH_OP_INVALID, + CAMERA_SENSOR_FLASH_OP_OFF, + CAMERA_SENSOR_FLASH_OP_FIRELOW, + CAMERA_SENSOR_FLASH_OP_FIREHIGH, + CAMERA_SENSOR_FLASH_OP_MAX, +}; + +enum camera_sensor_i2c_type { + CAMERA_SENSOR_I2C_TYPE_INVALID, + CAMERA_SENSOR_I2C_TYPE_BYTE, + CAMERA_SENSOR_I2C_TYPE_WORD, + CAMERA_SENSOR_I2C_TYPE_3B, + CAMERA_SENSOR_I2C_TYPE_DWORD, + CAMERA_SENSOR_I2C_TYPE_MAX, +}; + +enum i2c_freq_mode { + I2C_STANDARD_MODE, + I2C_FAST_MODE, + I2C_CUSTOM_MODE, + I2C_FAST_PLUS_MODE, + I2C_MAX_MODES, +}; + +enum position_roll { + ROLL_0 = 0, + ROLL_90 = 90, + ROLL_180 = 180, + ROLL_270 = 270, + ROLL_INVALID = 360, +}; + +enum position_yaw { + FRONT_CAMERA_YAW = 0, + REAR_CAMERA_YAW = 180, + INVALID_YAW = 360, +}; + +enum position_pitch { + LEVEL_PITCH = 0, + INVALID_PITCH = 360, +}; + +enum sensor_sub_module { + SUB_MODULE_SENSOR, + SUB_MODULE_ACTUATOR, + SUB_MODULE_EEPROM, + SUB_MODULE_LED_FLASH, + SUB_MODULE_CSID, + SUB_MODULE_CSIPHY, + SUB_MODULE_OIS, + SUB_MODULE_EXT, + SUB_MODULE_MAX, +}; + +enum msm_camera_power_seq_type { + SENSOR_MCLK, + SENSOR_VANA, + SENSOR_VDIG, + SENSOR_VIO, + SENSOR_VAF, + SENSOR_VAF_PWDM, + SENSOR_CUSTOM_REG1, + SENSOR_CUSTOM_REG2, + SENSOR_RESET, + SENSOR_STANDBY, + SENSOR_CUSTOM_GPIO1, + SENSOR_CUSTOM_GPIO2, + SENSOR_SEQ_TYPE_MAX, +}; + +enum cam_sensor_packet_opcodes { + CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON, + CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE, + CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG, + CAM_SENSOR_PACKET_OPCODE_SENSOR_PROBE, + CAM_SENSOR_PACKET_OPCODE_SENSOR_CONFIG, + CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF, + CAM_SENSOR_PACKET_OPCODE_SENSOR_READ, + CAM_SENSOR_PACKET_OPCODE_SENSOR_NOP = 127 +}; + +enum cam_actuator_packet_opcodes { + CAM_ACTUATOR_PACKET_OPCODE_INIT, + CAM_ACTUATOR_PACKET_AUTO_MOVE_LENS, + CAM_ACTUATOR_PACKET_MANUAL_MOVE_LENS, + CAM_ACTUATOR_PACKET_OPCODE_READ +}; + +enum cam_eeprom_packet_opcodes { + CAM_EEPROM_PACKET_OPCODE_INIT, + CAM_EEPROM_WRITE +}; + +enum cam_ois_packet_opcodes { + CAM_OIS_PACKET_OPCODE_INIT, + CAM_OIS_PACKET_OPCODE_OIS_CONTROL, + CAM_OIS_PACKET_OPCODE_READ +}; + +enum msm_bus_perf_setting { + S_INIT, + S_PREVIEW, + S_VIDEO, + S_CAPTURE, + S_ZSL, + S_STEREO_VIDEO, + S_STEREO_CAPTURE, + S_DEFAULT, + S_LIVESHOT, + S_DUAL, + S_EXIT +}; + +enum msm_camera_device_type_t { + MSM_CAMERA_I2C_DEVICE, + MSM_CAMERA_PLATFORM_DEVICE, + MSM_CAMERA_SPI_DEVICE, +}; + +enum cam_flash_device_type { + CAMERA_FLASH_DEVICE_TYPE_PMIC = 0, + CAMERA_FLASH_DEVICE_TYPE_I2C, + CAMERA_FLASH_DEVICE_TYPE_GPIO, +}; + +enum cci_i2c_master_t { + MASTER_0, + MASTER_1, + MASTER_MAX, +}; + +enum cci_device_num { + CCI_DEVICE_0, + CCI_DEVICE_1, + CCI_DEVICE_MAX, +}; + +enum camera_vreg_type { + VREG_TYPE_DEFAULT, + VREG_TYPE_CUSTOM, +}; + +enum cam_sensor_i2c_cmd_type { + CAM_SENSOR_I2C_WRITE_RANDOM, + CAM_SENSOR_I2C_WRITE_BURST, + CAM_SENSOR_I2C_WRITE_SEQ, + CAM_SENSOR_I2C_READ_RANDOM, + CAM_SENSOR_I2C_READ_SEQ, + CAM_SENSOR_I2C_POLL +}; + +struct common_header { + uint32_t first_word; + uint8_t fifth_byte; + uint8_t cmd_type; + uint16_t reserved; +}; + +struct camera_vreg_t { + const char *reg_name; + int min_voltage; + int max_voltage; + int op_mode; + uint32_t delay; + const char *custom_vreg_name; + enum camera_vreg_type type; +}; + +struct msm_camera_gpio_num_info { + uint16_t gpio_num[SENSOR_SEQ_TYPE_MAX]; + uint8_t valid[SENSOR_SEQ_TYPE_MAX]; +}; + +struct msm_cam_clk_info { + const char *clk_name; + long clk_rate; + uint32_t delay; +}; + +struct msm_pinctrl_info { + struct pinctrl *pinctrl; + struct pinctrl_state *gpio_state_active; + struct pinctrl_state *gpio_state_suspend; + bool use_pinctrl; +}; + +struct cam_sensor_i2c_reg_array { + uint32_t reg_addr; + uint32_t reg_data; + uint32_t delay; + uint32_t data_mask; +}; + +struct cam_sensor_i2c_reg_setting { + struct cam_sensor_i2c_reg_array *reg_setting; + uint32_t size; + enum camera_sensor_i2c_type addr_type; + enum camera_sensor_i2c_type data_type; + unsigned short delay; + uint8_t *read_buff; + uint32_t read_buff_len; +}; + +struct cam_sensor_i2c_seq_reg { + uint32_t reg_addr; + uint8_t *reg_data; + uint32_t size; + enum camera_sensor_i2c_type addr_type; +}; + +struct i2c_settings_list { + struct cam_sensor_i2c_reg_setting i2c_settings; + struct cam_sensor_i2c_seq_reg seq_settings; + enum cam_sensor_i2c_cmd_type op_code; + struct list_head list; +}; + +struct i2c_settings_array { + struct list_head list_head; + int32_t is_settings_valid; + int64_t request_id; +}; + +struct i2c_data_settings { + struct i2c_settings_array init_settings; + struct i2c_settings_array config_settings; + struct i2c_settings_array streamon_settings; + struct i2c_settings_array streamoff_settings; + struct i2c_settings_array read_settings; + struct i2c_settings_array *per_frame; +}; + +struct cam_sensor_power_ctrl_t { + struct device *dev; + struct cam_sensor_power_setting *power_setting; + uint16_t power_setting_size; + struct cam_sensor_power_setting *power_down_setting; + uint16_t power_down_setting_size; + struct msm_camera_gpio_num_info *gpio_num_info; + struct msm_pinctrl_info pinctrl_info; + uint8_t cam_pinctrl_status; +}; + +struct cam_camera_slave_info { + uint16_t sensor_slave_addr; + uint16_t sensor_id_reg_addr; + uint16_t sensor_id; + uint16_t sensor_id_mask; +}; + +struct msm_sensor_init_params { + int modes_supported; + unsigned int sensor_mount_angle; +}; + +enum msm_sensor_camera_id_t { + CAMERA_0, + CAMERA_1, + CAMERA_2, + CAMERA_3, + CAMERA_4, + CAMERA_5, + CAMERA_6, + MAX_CAMERAS, +}; + +struct msm_sensor_id_info_t { + unsigned short sensor_id_reg_addr; + unsigned short sensor_id; + unsigned short sensor_id_mask; +}; + +enum msm_sensor_output_format_t { + MSM_SENSOR_BAYER, + MSM_SENSOR_YCBCR, + MSM_SENSOR_META, +}; + +struct cam_sensor_power_setting { + enum msm_camera_power_seq_type seq_type; + unsigned short seq_val; + long config_val; + unsigned short delay; + void *data[10]; +}; + +struct cam_sensor_board_info { + struct cam_camera_slave_info slave_info; + int32_t sensor_mount_angle; + int32_t secure_mode; + int modes_supported; + int32_t pos_roll; + int32_t pos_yaw; + int32_t pos_pitch; + int32_t subdev_id[SUB_MODULE_MAX]; + int32_t subdev_intf[SUB_MODULE_MAX]; + const char *misc_regulator; + struct cam_sensor_power_ctrl_t power_info; +}; + +enum msm_camera_vreg_name_t { + CAM_VDIG, + CAM_VIO, + CAM_VANA, + CAM_VAF, + CAM_V_CUSTOM1, + CAM_V_CUSTOM2, + CAM_VREG_MAX, +}; + +struct msm_camera_gpio_conf { + void *cam_gpiomux_conf_tbl; + uint8_t cam_gpiomux_conf_tbl_size; + struct gpio *cam_gpio_common_tbl; + uint8_t cam_gpio_common_tbl_size; + struct gpio *cam_gpio_req_tbl; + uint8_t cam_gpio_req_tbl_size; + uint32_t gpio_no_mux; + uint32_t *camera_off_table; + uint8_t camera_off_table_size; + uint32_t *camera_on_table; + uint8_t camera_on_table_size; + struct msm_camera_gpio_num_info *gpio_num_info; +}; + +#endif /* _CAM_SENSOR_CMN_HEADER_ */ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c new file mode 100644 index 0000000000000000000000000000000000000000..f50d6584684c4b3b795791982b7a9b30047332c4 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c @@ -0,0 +1,2366 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "cam_sensor_util.h" +#include "cam_mem_mgr.h" +#include "cam_res_mgr_api.h" + +#define CAM_SENSOR_PINCTRL_STATE_SLEEP "cam_suspend" +#define CAM_SENSOR_PINCTRL_STATE_DEFAULT "cam_default" + +#define VALIDATE_VOLTAGE(min, max, config_val) ((config_val) && \ + (config_val >= min) && (config_val <= max)) + +static struct i2c_settings_list* + cam_sensor_get_i2c_ptr(struct i2c_settings_array *i2c_reg_settings, + uint32_t size) +{ + struct i2c_settings_list *tmp; + + tmp = kzalloc(sizeof(struct i2c_settings_list), GFP_KERNEL); + + if (tmp != NULL) + list_add_tail(&(tmp->list), + &(i2c_reg_settings->list_head)); + else + return NULL; + + tmp->i2c_settings.reg_setting = (struct cam_sensor_i2c_reg_array *) + vzalloc(size * sizeof(struct cam_sensor_i2c_reg_array)); + if (tmp->i2c_settings.reg_setting == NULL) { + list_del(&(tmp->list)); + kfree(tmp); + return NULL; + } + tmp->i2c_settings.size = size; + + return tmp; +} + +int32_t delete_request(struct i2c_settings_array *i2c_array) +{ + struct i2c_settings_list *i2c_list = NULL, *i2c_next = NULL; + int32_t rc = 0; + + if (i2c_array == NULL) { + CAM_ERR(CAM_SENSOR, "FATAL:: Invalid argument"); + return -EINVAL; + } + + list_for_each_entry_safe(i2c_list, i2c_next, + &(i2c_array->list_head), list) { + vfree(i2c_list->i2c_settings.reg_setting); + list_del(&(i2c_list->list)); + kfree(i2c_list); + } + INIT_LIST_HEAD(&(i2c_array->list_head)); + i2c_array->is_settings_valid = 0; + + return rc; +} + +int32_t cam_sensor_handle_delay( + uint32_t **cmd_buf, + uint16_t generic_op_code, + struct i2c_settings_array *i2c_reg_settings, + uint32_t offset, uint32_t *byte_cnt, + struct list_head *list_ptr) +{ + int32_t rc = 0; + struct cam_cmd_unconditional_wait *cmd_uncond_wait = + (struct cam_cmd_unconditional_wait *) *cmd_buf; + struct i2c_settings_list *i2c_list = NULL; + + if (list_ptr == NULL) { + CAM_ERR(CAM_SENSOR, "Invalid list ptr"); + return -EINVAL; + } + + if (offset > 0) { + i2c_list = + list_entry(list_ptr, struct i2c_settings_list, list); + if (generic_op_code == + CAMERA_SENSOR_WAIT_OP_HW_UCND) + i2c_list->i2c_settings.reg_setting[offset - 1].delay = + cmd_uncond_wait->delay; + else + i2c_list->i2c_settings.delay = cmd_uncond_wait->delay; + (*cmd_buf) += + sizeof( + struct cam_cmd_unconditional_wait) / sizeof(uint32_t); + (*byte_cnt) += + sizeof( + struct cam_cmd_unconditional_wait); + } else { + CAM_ERR(CAM_SENSOR, "Delay Rxed Before any buffer: %d", offset); + return -EINVAL; + } + + return rc; +} + +int32_t cam_sensor_handle_poll( + uint32_t **cmd_buf, + struct i2c_settings_array *i2c_reg_settings, + uint32_t *byte_cnt, int32_t *offset, + struct list_head **list_ptr) +{ + struct i2c_settings_list *i2c_list; + int32_t rc = 0; + struct cam_cmd_conditional_wait *cond_wait + = (struct cam_cmd_conditional_wait *) *cmd_buf; + + i2c_list = + cam_sensor_get_i2c_ptr(i2c_reg_settings, 1); + if (!i2c_list || !i2c_list->i2c_settings.reg_setting) { + CAM_ERR(CAM_SENSOR, "Failed in allocating mem for list"); + return -ENOMEM; + } + + i2c_list->op_code = CAM_SENSOR_I2C_POLL; + i2c_list->i2c_settings.data_type = + cond_wait->data_type; + i2c_list->i2c_settings.addr_type = + cond_wait->addr_type; + i2c_list->i2c_settings.reg_setting->reg_addr = + cond_wait->reg_addr; + i2c_list->i2c_settings.reg_setting->reg_data = + cond_wait->reg_data; + i2c_list->i2c_settings.reg_setting->delay = + cond_wait->timeout; + + (*cmd_buf) += sizeof(struct cam_cmd_conditional_wait) / + sizeof(uint32_t); + (*byte_cnt) += sizeof(struct cam_cmd_conditional_wait); + + *offset = 1; + *list_ptr = &(i2c_list->list); + + return rc; +} + +int32_t cam_sensor_handle_random_write( + struct cam_cmd_i2c_random_wr *cam_cmd_i2c_random_wr, + struct i2c_settings_array *i2c_reg_settings, + uint32_t *cmd_length_in_bytes, int32_t *offset, + struct list_head **list) +{ + struct i2c_settings_list *i2c_list; + int32_t rc = 0, cnt; + + i2c_list = cam_sensor_get_i2c_ptr(i2c_reg_settings, + cam_cmd_i2c_random_wr->header.count); + if (i2c_list == NULL || + i2c_list->i2c_settings.reg_setting == NULL) { + CAM_ERR(CAM_SENSOR, "Failed in allocating i2c_list"); + return -ENOMEM; + } + + *cmd_length_in_bytes = (sizeof(struct i2c_rdwr_header) + + sizeof(struct i2c_random_wr_payload) * + (cam_cmd_i2c_random_wr->header.count)); + i2c_list->op_code = CAM_SENSOR_I2C_WRITE_RANDOM; + i2c_list->i2c_settings.addr_type = + cam_cmd_i2c_random_wr->header.addr_type; + i2c_list->i2c_settings.data_type = + cam_cmd_i2c_random_wr->header.data_type; + + for (cnt = 0; cnt < (cam_cmd_i2c_random_wr->header.count); + cnt++) { + i2c_list->i2c_settings.reg_setting[cnt].reg_addr = + cam_cmd_i2c_random_wr->random_wr_payload[cnt].reg_addr; + i2c_list->i2c_settings.reg_setting[cnt].reg_data = + cam_cmd_i2c_random_wr->random_wr_payload[cnt].reg_data; + i2c_list->i2c_settings.reg_setting[cnt].data_mask = 0; + } + *offset = cnt; + *list = &(i2c_list->list); + + return rc; +} + +static int32_t cam_sensor_handle_continuous_write( + struct cam_cmd_i2c_continuous_wr *cam_cmd_i2c_continuous_wr, + struct i2c_settings_array *i2c_reg_settings, + uint32_t *cmd_length_in_bytes, int32_t *offset, + struct list_head **list) +{ + struct i2c_settings_list *i2c_list; + int32_t rc = 0, cnt; + + i2c_list = cam_sensor_get_i2c_ptr(i2c_reg_settings, + cam_cmd_i2c_continuous_wr->header.count); + if (i2c_list == NULL || + i2c_list->i2c_settings.reg_setting == NULL) { + CAM_ERR(CAM_SENSOR, "Failed in allocating i2c_list"); + return -ENOMEM; + } + + *cmd_length_in_bytes = (sizeof(struct i2c_rdwr_header) + + sizeof(cam_cmd_i2c_continuous_wr->reg_addr) + + sizeof(struct cam_cmd_read) * + (cam_cmd_i2c_continuous_wr->header.count)); + if (cam_cmd_i2c_continuous_wr->header.op_code == + CAMERA_SENSOR_I2C_OP_CONT_WR_BRST) + i2c_list->op_code = CAM_SENSOR_I2C_WRITE_BURST; + else if (cam_cmd_i2c_continuous_wr->header.op_code == + CAMERA_SENSOR_I2C_OP_CONT_WR_SEQN) + i2c_list->op_code = CAM_SENSOR_I2C_WRITE_SEQ; + else + return -EINVAL; + + i2c_list->i2c_settings.addr_type = + cam_cmd_i2c_continuous_wr->header.addr_type; + i2c_list->i2c_settings.data_type = + cam_cmd_i2c_continuous_wr->header.data_type; + i2c_list->i2c_settings.size = + cam_cmd_i2c_continuous_wr->header.count; + + for (cnt = 0; cnt < (cam_cmd_i2c_continuous_wr->header.count); + cnt++) { + i2c_list->i2c_settings.reg_setting[cnt].reg_addr = + cam_cmd_i2c_continuous_wr->reg_addr; + i2c_list->i2c_settings.reg_setting[cnt].reg_data = + cam_cmd_i2c_continuous_wr->data_read[cnt].reg_data; + i2c_list->i2c_settings.reg_setting[cnt].data_mask = 0; + } + *offset = cnt; + *list = &(i2c_list->list); + + return rc; +} + +static int32_t cam_sensor_get_io_buffer( + struct cam_buf_io_cfg *io_cfg, + struct cam_sensor_i2c_reg_setting *i2c_settings) +{ + uintptr_t buf_addr = 0x0; + size_t buf_size = 0; + int32_t rc = 0; + + if (io_cfg == NULL || i2c_settings == NULL) { + CAM_ERR(CAM_SENSOR, + "Invalid args, io buf or i2c settings is NULL"); + return -EINVAL; + } + + if (io_cfg->direction == CAM_BUF_OUTPUT) { + rc = cam_mem_get_cpu_buf(io_cfg->mem_handle[0], + &buf_addr, &buf_size); + if ((rc < 0) || (!buf_addr)) { + CAM_ERR(CAM_SENSOR, + "invalid buffer, rc: %d, buf_addr: %pK", + rc, buf_addr); + return -EINVAL; + } + CAM_DBG(CAM_SENSOR, + "buf_addr: %pK, buf_size: %zu, offsetsize: %d", + (void *)buf_addr, buf_size, io_cfg->offsets[0]); + if (io_cfg->offsets[0] >= buf_size) { + CAM_ERR(CAM_SENSOR, + "invalid size:io_cfg->offsets[0]: %d, buf_size: %d", + io_cfg->offsets[0], buf_size); + return -EINVAL; + } + i2c_settings->read_buff = + (uint8_t *)buf_addr + io_cfg->offsets[0]; + i2c_settings->read_buff_len = + buf_size - io_cfg->offsets[0]; + } else { + CAM_ERR(CAM_SENSOR, "Invalid direction: %d", + io_cfg->direction); + rc = -EINVAL; + } + cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); + return rc; +} + +static int32_t cam_sensor_handle_random_read( + struct cam_cmd_i2c_random_rd *cmd_i2c_random_rd, + struct i2c_settings_array *i2c_reg_settings, + uint16_t *cmd_length_in_bytes, + int32_t *offset, + struct list_head **list, + struct cam_buf_io_cfg *io_cfg) +{ + struct i2c_settings_list *i2c_list; + int32_t rc = 0, cnt = 0; + + i2c_list = cam_sensor_get_i2c_ptr(i2c_reg_settings, + cmd_i2c_random_rd->header.count); + if ((i2c_list == NULL) || + (i2c_list->i2c_settings.reg_setting == NULL)) { + CAM_ERR(CAM_SENSOR, + "Failed in allocating i2c_list: %pK", + i2c_list); + return -ENOMEM; + } + + rc = cam_sensor_get_io_buffer(io_cfg, &(i2c_list->i2c_settings)); + if (rc) { + CAM_ERR(CAM_SENSOR, "Failed to get read buffer: %d", rc); + } else { + *cmd_length_in_bytes = sizeof(struct i2c_rdwr_header) + + (sizeof(struct cam_cmd_read) * + (cmd_i2c_random_rd->header.count)); + i2c_list->op_code = CAM_SENSOR_I2C_READ_RANDOM; + i2c_list->i2c_settings.addr_type = + cmd_i2c_random_rd->header.addr_type; + i2c_list->i2c_settings.data_type = + cmd_i2c_random_rd->header.data_type; + i2c_list->i2c_settings.size = + cmd_i2c_random_rd->header.count; + + for (cnt = 0; cnt < (cmd_i2c_random_rd->header.count); + cnt++) { + i2c_list->i2c_settings.reg_setting[cnt].reg_addr = + cmd_i2c_random_rd->data_read[cnt].reg_data; + } + *offset = cnt; + *list = &(i2c_list->list); + } + + return rc; +} + +static int32_t cam_sensor_handle_continuous_read( + struct cam_cmd_i2c_continuous_rd *cmd_i2c_continuous_rd, + struct i2c_settings_array *i2c_reg_settings, + uint16_t *cmd_length_in_bytes, int32_t *offset, + struct list_head **list, + struct cam_buf_io_cfg *io_cfg) +{ + struct i2c_settings_list *i2c_list; + int32_t rc = 0, cnt = 0; + + i2c_list = cam_sensor_get_i2c_ptr(i2c_reg_settings, 1); + if ((i2c_list == NULL) || + (i2c_list->i2c_settings.reg_setting == NULL)) { + CAM_ERR(CAM_SENSOR, + "Failed in allocating i2c_list: %pK", + i2c_list); + return -ENOMEM; + } + + rc = cam_sensor_get_io_buffer(io_cfg, &(i2c_list->i2c_settings)); + if (rc) { + CAM_ERR(CAM_SENSOR, "Failed to get read buffer: %d", rc); + } else { + *cmd_length_in_bytes = sizeof(struct cam_cmd_i2c_continuous_rd); + i2c_list->op_code = CAM_SENSOR_I2C_READ_SEQ; + + i2c_list->i2c_settings.addr_type = + cmd_i2c_continuous_rd->header.addr_type; + i2c_list->i2c_settings.data_type = + cmd_i2c_continuous_rd->header.data_type; + i2c_list->i2c_settings.size = + cmd_i2c_continuous_rd->header.count; + i2c_list->i2c_settings.reg_setting[0].reg_addr = + cmd_i2c_continuous_rd->reg_addr; + + *offset = cnt; + *list = &(i2c_list->list); + } + + return rc; +} + +static int cam_sensor_handle_slave_info( + struct camera_io_master *io_master, + uint32_t *cmd_buf) +{ + int rc = 0; + struct cam_cmd_i2c_info *i2c_info = (struct cam_cmd_i2c_info *)cmd_buf; + + if (io_master == NULL || cmd_buf == NULL) { + CAM_ERR(CAM_SENSOR, "Invalid args"); + return -EINVAL; + } + + switch (io_master->master_type) { + case CCI_MASTER: + io_master->cci_client->sid = (i2c_info->slave_addr >> 1); + io_master->cci_client->i2c_freq_mode = i2c_info->i2c_freq_mode; + break; + + case I2C_MASTER: + io_master->client->addr = i2c_info->slave_addr; + break; + + case SPI_MASTER: + break; + + default: + CAM_ERR(CAM_SENSOR, "Invalid master type: %d", + io_master->master_type); + rc = -EINVAL; + break; + } + + return rc; +} + +/** + * Name : cam_sensor_i2c_command_parser + * Description : Parse CSL CCI packet and apply register settings + * Parameters : io_master input master information + * i2c_reg_settings output register settings to fill + * cmd_desc input command description + * num_cmd_buffers input number of command buffers to process + * io_cfg input buffer details for read operation only + * Description : + * Handle multiple I2C RD/WR and WAIT cmd formats in one command + * buffer, for example, a command buffer of m x RND_WR + 1 x HW_ + * WAIT + n x RND_WR with num_cmd_buf = 1. Do not exepect RD/WR + * with different cmd_type and op_code in one command buffer. + */ +int cam_sensor_i2c_command_parser( + struct camera_io_master *io_master, + struct i2c_settings_array *i2c_reg_settings, + struct cam_cmd_buf_desc *cmd_desc, + int32_t num_cmd_buffers, + struct cam_buf_io_cfg *io_cfg) +{ + int16_t rc = 0, i = 0; + size_t len_of_buff = 0; + uintptr_t generic_ptr; + uint16_t cmd_length_in_bytes = 0; + size_t remain_len = 0; + size_t tot_size = 0; + + for (i = 0; i < num_cmd_buffers; i++) { + uint32_t *cmd_buf = NULL; + struct common_header *cmm_hdr; + uint16_t generic_op_code; + uint32_t byte_cnt = 0; + uint32_t j = 0; + struct list_head *list = NULL; + + /* + * It is not expected the same settings to + * be spread across multiple cmd buffers + */ + CAM_DBG(CAM_SENSOR, "Total cmd Buf in Bytes: %d", + cmd_desc[i].length); + + if (!cmd_desc[i].length) + continue; + + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, + &generic_ptr, &len_of_buff); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "cmd hdl failed:%d, Err: %d, Buffer_len: %zd", + cmd_desc[i].mem_handle, rc, len_of_buff); + return rc; + } + + remain_len = len_of_buff; + if ((len_of_buff < sizeof(struct common_header)) || + (cmd_desc[i].offset > + (len_of_buff - sizeof(struct common_header)))) { + CAM_ERR(CAM_SENSOR, "buffer provided too small"); + return -EINVAL; + } + cmd_buf = (uint32_t *)generic_ptr; + cmd_buf += cmd_desc[i].offset / sizeof(uint32_t); + + remain_len -= cmd_desc[i].offset; + if (remain_len < cmd_desc[i].length) { + CAM_ERR(CAM_SENSOR, "buffer provided too small"); + return -EINVAL; + } + + while (byte_cnt < cmd_desc[i].length) { + if ((remain_len - byte_cnt) < + sizeof(struct common_header)) { + CAM_ERR(CAM_SENSOR, "Not enough buffer"); + rc = -EINVAL; + goto end; + } + cmm_hdr = (struct common_header *)cmd_buf; + generic_op_code = cmm_hdr->fifth_byte; + switch (cmm_hdr->cmd_type) { + case CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_WR: { + uint32_t cmd_length_in_bytes = 0; + struct cam_cmd_i2c_random_wr + *cam_cmd_i2c_random_wr = + (struct cam_cmd_i2c_random_wr *)cmd_buf; + + if ((remain_len - byte_cnt) < + sizeof(struct cam_cmd_i2c_random_wr)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided"); + rc = -EINVAL; + goto end; + } + tot_size = sizeof(struct i2c_rdwr_header) + + (sizeof(struct i2c_random_wr_payload) * + cam_cmd_i2c_random_wr->header.count); + + if (tot_size > (remain_len - byte_cnt)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided"); + rc = -EINVAL; + goto end; + } + + rc = cam_sensor_handle_random_write( + cam_cmd_i2c_random_wr, + i2c_reg_settings, + &cmd_length_in_bytes, &j, &list); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed in random write %d", rc); + rc = -EINVAL; + goto end; + } + + cmd_buf += cmd_length_in_bytes / + sizeof(uint32_t); + byte_cnt += cmd_length_in_bytes; + break; + } + case CAMERA_SENSOR_CMD_TYPE_I2C_CONT_WR: { + uint32_t cmd_length_in_bytes = 0; + struct cam_cmd_i2c_continuous_wr + *cam_cmd_i2c_continuous_wr = + (struct cam_cmd_i2c_continuous_wr *) + cmd_buf; + + if ((remain_len - byte_cnt) < + sizeof(struct cam_cmd_i2c_continuous_wr)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided"); + rc = -EINVAL; + goto end; + } + + tot_size = sizeof(struct i2c_rdwr_header) + + sizeof(cam_cmd_i2c_continuous_wr->reg_addr) + + (sizeof(struct cam_cmd_read) * + cam_cmd_i2c_continuous_wr->header.count); + + if (tot_size > (remain_len - byte_cnt)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided"); + rc = -EINVAL; + goto end; + } + + rc = cam_sensor_handle_continuous_write( + cam_cmd_i2c_continuous_wr, + i2c_reg_settings, + &cmd_length_in_bytes, &j, &list); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed in continuous write %d", rc); + goto end; + } + + cmd_buf += cmd_length_in_bytes / + sizeof(uint32_t); + byte_cnt += cmd_length_in_bytes; + break; + } + case CAMERA_SENSOR_CMD_TYPE_WAIT: { + if ((remain_len - byte_cnt) < + sizeof(struct cam_cmd_unconditional_wait)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer space"); + rc = -EINVAL; + goto end; + } + if (generic_op_code == + CAMERA_SENSOR_WAIT_OP_HW_UCND || + generic_op_code == + CAMERA_SENSOR_WAIT_OP_SW_UCND) { + rc = cam_sensor_handle_delay( + &cmd_buf, generic_op_code, + i2c_reg_settings, j, &byte_cnt, + list); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "delay hdl failed: %d", + rc); + goto end; + } + + } else if (generic_op_code == + CAMERA_SENSOR_WAIT_OP_COND) { + rc = cam_sensor_handle_poll( + &cmd_buf, i2c_reg_settings, + &byte_cnt, &j, &list); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Random read fail: %d", + rc); + goto end; + } + } else { + CAM_ERR(CAM_SENSOR, + "Wrong Wait Command: %d", + generic_op_code); + rc = -EINVAL; + goto end; + } + break; + } + case CAMERA_SENSOR_CMD_TYPE_I2C_INFO: { + if (remain_len - byte_cnt < + sizeof(struct cam_cmd_i2c_info)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer space"); + rc = -EINVAL; + goto end; + } + rc = cam_sensor_handle_slave_info( + io_master, cmd_buf); + if (rc) { + CAM_ERR(CAM_SENSOR, + "Handle slave info failed with rc: %d", + rc); + goto end; + } + cmd_length_in_bytes = + sizeof(struct cam_cmd_i2c_info); + cmd_buf += + cmd_length_in_bytes / sizeof(uint32_t); + byte_cnt += cmd_length_in_bytes; + break; + } + case CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_RD: { + uint16_t cmd_length_in_bytes = 0; + struct cam_cmd_i2c_random_rd *i2c_random_rd = + (struct cam_cmd_i2c_random_rd *)cmd_buf; + + if (remain_len - byte_cnt < + sizeof(struct cam_cmd_i2c_random_rd)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer space"); + rc = -EINVAL; + goto end; + } + + tot_size = sizeof(struct i2c_rdwr_header) + + (sizeof(struct cam_cmd_read) * + i2c_random_rd->header.count); + + if (tot_size > (remain_len - byte_cnt)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided %d, %d, %d", + tot_size, remain_len, byte_cnt); + rc = -EINVAL; + goto end; + } + + rc = cam_sensor_handle_random_read( + i2c_random_rd, + i2c_reg_settings, + &cmd_length_in_bytes, &j, &list, + io_cfg); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed in random read %d", rc); + goto end; + } + + cmd_buf += cmd_length_in_bytes / + sizeof(uint32_t); + byte_cnt += cmd_length_in_bytes; + break; + } + case CAMERA_SENSOR_CMD_TYPE_I2C_CONT_RD: { + uint16_t cmd_length_in_bytes = 0; + struct cam_cmd_i2c_continuous_rd + *i2c_continuous_rd = + (struct cam_cmd_i2c_continuous_rd *)cmd_buf; + + if (remain_len - byte_cnt < + sizeof(struct cam_cmd_i2c_continuous_rd)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer space"); + rc = -EINVAL; + goto end; + } + + tot_size = + sizeof(struct cam_cmd_i2c_continuous_rd); + + if (tot_size > (remain_len - byte_cnt)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided %d, %d, %d", + tot_size, remain_len, byte_cnt); + rc = -EINVAL; + goto end; + } + + rc = cam_sensor_handle_continuous_read( + i2c_continuous_rd, + i2c_reg_settings, + &cmd_length_in_bytes, &j, &list, + io_cfg); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed in continuous read %d", rc); + goto end; + } + + cmd_buf += cmd_length_in_bytes / + sizeof(uint32_t); + byte_cnt += cmd_length_in_bytes; + break; + } + default: + CAM_ERR(CAM_SENSOR, "Invalid Command Type:%d", + cmm_hdr->cmd_type); + rc = -EINVAL; + goto end; + } + } + i2c_reg_settings->is_settings_valid = 1; + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + } + return rc; + +end: + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + return rc; +} + +int cam_sensor_util_i2c_apply_setting( + struct camera_io_master *io_master_info, + struct i2c_settings_list *i2c_list) +{ + int32_t rc = 0; + uint32_t i, size; + + switch (i2c_list->op_code) { + case CAM_SENSOR_I2C_WRITE_RANDOM: { + rc = camera_io_dev_write(io_master_info, + &(i2c_list->i2c_settings)); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed to random write I2C settings: %d", + rc); + return rc; + } + break; + } + case CAM_SENSOR_I2C_WRITE_SEQ: { + rc = camera_io_dev_write_continuous( + io_master_info, &(i2c_list->i2c_settings), 0); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed to seq write I2C settings: %d", + rc); + return rc; + } + break; + } + case CAM_SENSOR_I2C_WRITE_BURST: { + rc = camera_io_dev_write_continuous( + io_master_info, &(i2c_list->i2c_settings), 1); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed to burst write I2C settings: %d", + rc); + return rc; + } + break; + } + case CAM_SENSOR_I2C_POLL: { + size = i2c_list->i2c_settings.size; + for (i = 0; i < size; i++) { + rc = camera_io_dev_poll( + io_master_info, + i2c_list->i2c_settings.reg_setting[i].reg_addr, + i2c_list->i2c_settings.reg_setting[i].reg_data, + i2c_list->i2c_settings.reg_setting[i].data_mask, + i2c_list->i2c_settings.addr_type, + i2c_list->i2c_settings.data_type, + i2c_list->i2c_settings.reg_setting[i].delay); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "i2c poll apply setting Fail: %d", rc); + return rc; + } + } + break; + } + default: + CAM_ERR(CAM_SENSOR, "Wrong Opcode: %d", i2c_list->op_code); + rc = -EINVAL; + break; + } + + return rc; +} + +int32_t cam_sensor_i2c_read_data( + struct i2c_settings_array *i2c_settings, + struct camera_io_master *io_master_info) +{ + int32_t rc = 0; + struct i2c_settings_list *i2c_list; + uint32_t cnt = 0; + uint8_t *read_buff = NULL; + uint32_t buff_length = 0; + uint32_t read_length = 0; + + list_for_each_entry(i2c_list, + &(i2c_settings->list_head), list) { + read_buff = i2c_list->i2c_settings.read_buff; + buff_length = i2c_list->i2c_settings.read_buff_len; + if ((read_buff == NULL) || (buff_length == 0)) { + CAM_ERR(CAM_SENSOR, + "Invalid input buffer, buffer: %pK, length: %d", + read_buff, buff_length); + return -EINVAL; + } + + if (i2c_list->op_code == CAM_SENSOR_I2C_READ_RANDOM) { + read_length = i2c_list->i2c_settings.data_type * + i2c_list->i2c_settings.size; + if ((read_length > buff_length) || + (read_length < i2c_list->i2c_settings.size)) { + CAM_ERR(CAM_SENSOR, + "Invalid size, readLen:%d, bufLen:%d, size: %d", + read_length, buff_length, + i2c_list->i2c_settings.size); + return -EINVAL; + } + for (cnt = 0; cnt < (i2c_list->i2c_settings.size); + cnt++) { + struct cam_sensor_i2c_reg_array *reg_setting = + &(i2c_list->i2c_settings.reg_setting[cnt]); + rc = camera_io_dev_read(io_master_info, + reg_setting->reg_addr, + ®_setting->reg_data, + i2c_list->i2c_settings.addr_type, + i2c_list->i2c_settings.data_type); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed: random read I2C settings: %d", + rc); + return rc; + } + if (i2c_list->i2c_settings.data_type < + CAMERA_SENSOR_I2C_TYPE_MAX) { + memcpy(read_buff, + ®_setting->reg_data, + i2c_list->i2c_settings.data_type); + read_buff += + i2c_list->i2c_settings.data_type; + } + } + } else if (i2c_list->op_code == CAM_SENSOR_I2C_READ_SEQ) { + read_length = i2c_list->i2c_settings.size; + if (read_length > buff_length) { + CAM_ERR(CAM_SENSOR, + "Invalid buffer size, readLen: %d, bufLen: %d", + read_length, buff_length); + return -EINVAL; + } + rc = camera_io_dev_read_seq( + io_master_info, + i2c_list->i2c_settings.reg_setting[0].reg_addr, + read_buff, + i2c_list->i2c_settings.addr_type, + i2c_list->i2c_settings.data_type, + i2c_list->i2c_settings.size); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "failed: seq read I2C settings: %d", + rc); + return rc; + } + } + } + + return rc; +} + +int32_t msm_camera_fill_vreg_params( + struct cam_hw_soc_info *soc_info, + struct cam_sensor_power_setting *power_setting, + uint16_t power_setting_size) +{ + int32_t rc = 0, j = 0, i = 0; + int num_vreg; + + /* Validate input parameters */ + if (!soc_info || !power_setting) { + CAM_ERR(CAM_SENSOR, "failed: soc_info %pK power_setting %pK", + soc_info, power_setting); + return -EINVAL; + } + + num_vreg = soc_info->num_rgltr; + + if ((num_vreg <= 0) || (num_vreg > CAM_SOC_MAX_REGULATOR)) { + CAM_ERR(CAM_SENSOR, "failed: num_vreg %d", num_vreg); + return -EINVAL; + } + + for (i = 0; i < power_setting_size; i++) { + + if (power_setting[i].seq_type < SENSOR_MCLK || + power_setting[i].seq_type >= SENSOR_SEQ_TYPE_MAX) { + CAM_ERR(CAM_SENSOR, "failed: Invalid Seq type: %d", + power_setting[i].seq_type); + return -EINVAL; + } + + switch (power_setting[i].seq_type) { + case SENSOR_VDIG: + for (j = 0; j < num_vreg; j++) { + if (!strcmp(soc_info->rgltr_name[j], + "cam_vdig")) { + + CAM_DBG(CAM_SENSOR, + "i: %d j: %d cam_vdig", i, j); + power_setting[i].seq_val = j; + + if (VALIDATE_VOLTAGE( + soc_info->rgltr_min_volt[j], + soc_info->rgltr_max_volt[j], + power_setting[i].config_val)) { + soc_info->rgltr_min_volt[j] = + soc_info->rgltr_max_volt[j] = + power_setting[i].config_val; + } + break; + } + } + if (j == num_vreg) + power_setting[i].seq_val = INVALID_VREG; + break; + + case SENSOR_VIO: + for (j = 0; j < num_vreg; j++) { + + if (!strcmp(soc_info->rgltr_name[j], + "cam_vio")) { + CAM_DBG(CAM_SENSOR, + "i: %d j: %d cam_vio", i, j); + power_setting[i].seq_val = j; + + if (VALIDATE_VOLTAGE( + soc_info->rgltr_min_volt[j], + soc_info->rgltr_max_volt[j], + power_setting[i].config_val)) { + soc_info->rgltr_min_volt[j] = + soc_info->rgltr_max_volt[j] = + power_setting[i].config_val; + } + break; + } + + } + if (j == num_vreg) + power_setting[i].seq_val = INVALID_VREG; + break; + + case SENSOR_VANA: + for (j = 0; j < num_vreg; j++) { + + if (!strcmp(soc_info->rgltr_name[j], + "cam_vana")) { + CAM_DBG(CAM_SENSOR, + "i: %d j: %d cam_vana", i, j); + power_setting[i].seq_val = j; + + if (VALIDATE_VOLTAGE( + soc_info->rgltr_min_volt[j], + soc_info->rgltr_max_volt[j], + power_setting[i].config_val)) { + soc_info->rgltr_min_volt[j] = + soc_info->rgltr_max_volt[j] = + power_setting[i].config_val; + } + break; + } + + } + if (j == num_vreg) + power_setting[i].seq_val = INVALID_VREG; + break; + + case SENSOR_VAF: + for (j = 0; j < num_vreg; j++) { + + if (!strcmp(soc_info->rgltr_name[j], + "cam_vaf")) { + CAM_DBG(CAM_SENSOR, + "i: %d j: %d cam_vaf", i, j); + power_setting[i].seq_val = j; + + if (VALIDATE_VOLTAGE( + soc_info->rgltr_min_volt[j], + soc_info->rgltr_max_volt[j], + power_setting[i].config_val)) { + soc_info->rgltr_min_volt[j] = + soc_info->rgltr_max_volt[j] = + power_setting[i].config_val; + } + + break; + } + + } + if (j == num_vreg) + power_setting[i].seq_val = INVALID_VREG; + break; + + case SENSOR_CUSTOM_REG1: + for (j = 0; j < num_vreg; j++) { + + if (!strcmp(soc_info->rgltr_name[j], + "cam_v_custom1")) { + CAM_DBG(CAM_SENSOR, + "i:%d j:%d cam_vcustom1", i, j); + power_setting[i].seq_val = j; + + if (VALIDATE_VOLTAGE( + soc_info->rgltr_min_volt[j], + soc_info->rgltr_max_volt[j], + power_setting[i].config_val)) { + soc_info->rgltr_min_volt[j] = + soc_info->rgltr_max_volt[j] = + power_setting[i].config_val; + } + break; + } + + } + if (j == num_vreg) + power_setting[i].seq_val = INVALID_VREG; + break; + case SENSOR_CUSTOM_REG2: + for (j = 0; j < num_vreg; j++) { + + if (!strcmp(soc_info->rgltr_name[j], + "cam_v_custom2")) { + CAM_DBG(CAM_SENSOR, + "i:%d j:%d cam_vcustom2", i, j); + power_setting[i].seq_val = j; + + if (VALIDATE_VOLTAGE( + soc_info->rgltr_min_volt[j], + soc_info->rgltr_max_volt[j], + power_setting[i].config_val)) { + soc_info->rgltr_min_volt[j] = + soc_info->rgltr_max_volt[j] = + power_setting[i].config_val; + } + break; + } + } + if (j == num_vreg) + power_setting[i].seq_val = INVALID_VREG; + break; + default: + break; + } + } + + return rc; +} + +int cam_sensor_util_request_gpio_table( + struct cam_hw_soc_info *soc_info, int gpio_en) +{ + int rc = 0, i = 0; + uint8_t size = 0; + struct cam_soc_gpio_data *gpio_conf = + soc_info->gpio_data; + struct gpio *gpio_tbl = NULL; + + if (!gpio_conf) { + CAM_INFO(CAM_SENSOR, "No GPIO data"); + return 0; + } + + if (gpio_conf->cam_gpio_common_tbl_size <= 0) { + CAM_INFO(CAM_SENSOR, "No GPIO entry"); + return -EINVAL; + } + + gpio_tbl = gpio_conf->cam_gpio_req_tbl; + size = gpio_conf->cam_gpio_req_tbl_size; + + if (!gpio_tbl || !size) { + CAM_ERR(CAM_SENSOR, "invalid gpio_tbl %pK / size %d", + gpio_tbl, size); + return -EINVAL; + } + + for (i = 0; i < size; i++) { + CAM_DBG(CAM_SENSOR, "i: %d, gpio %d dir %ld", i, + gpio_tbl[i].gpio, gpio_tbl[i].flags); + } + + if (gpio_en) { + for (i = 0; i < size; i++) { + rc = cam_res_mgr_gpio_request(soc_info->dev, + gpio_tbl[i].gpio, + gpio_tbl[i].flags, gpio_tbl[i].label); + if (rc) { + /* + * After GPIO request fails, contine to + * apply new gpios, outout a error message + * for driver bringup debug + */ + CAM_ERR(CAM_SENSOR, "gpio %d:%s request fails", + gpio_tbl[i].gpio, gpio_tbl[i].label); + } + } + } else { + cam_res_mgr_gpio_free_arry(soc_info->dev, gpio_tbl, size); + } + + return rc; +} + + +static int32_t cam_sensor_validate(void *ptr, size_t remain_buf) +{ + struct common_header *cmm_hdr = (struct common_header *)ptr; + size_t validate_size = 0; + + if (remain_buf < sizeof(struct common_header)) + return -EINVAL; + + if (cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_PWR_UP || + cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_PWR_DOWN) + validate_size = sizeof(struct cam_cmd_power); + else if (cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_WAIT) + validate_size = sizeof(struct cam_cmd_unconditional_wait); + + if (remain_buf < validate_size) { + CAM_ERR(CAM_SENSOR, "Invalid cmd_buf len %zu min %zu", + remain_buf, validate_size); + return -EINVAL; + } + return 0; +} + +int32_t cam_sensor_update_power_settings(void *cmd_buf, + uint32_t cmd_length, struct cam_sensor_power_ctrl_t *power_info, + size_t cmd_buf_len) +{ + int32_t rc = 0, tot_size = 0, last_cmd_type = 0; + int32_t i = 0, pwr_up = 0, pwr_down = 0; + struct cam_sensor_power_setting *pwr_settings; + void *ptr = cmd_buf, *scr; + struct cam_cmd_power *pwr_cmd = (struct cam_cmd_power *)cmd_buf; + struct common_header *cmm_hdr = (struct common_header *)cmd_buf; + + if (!pwr_cmd || !cmd_length || cmd_buf_len < (size_t)cmd_length || + cam_sensor_validate(cmd_buf, cmd_buf_len)) { + CAM_ERR(CAM_SENSOR, "Invalid Args: pwr_cmd %pK, cmd_length: %d", + pwr_cmd, cmd_length); + return -EINVAL; + } + + power_info->power_setting_size = 0; + power_info->power_setting = + kzalloc(sizeof(struct cam_sensor_power_setting) * + MAX_POWER_CONFIG, GFP_KERNEL); + if (!power_info->power_setting) + return -ENOMEM; + + power_info->power_down_setting_size = 0; + power_info->power_down_setting = + kzalloc(sizeof(struct cam_sensor_power_setting) * + MAX_POWER_CONFIG, GFP_KERNEL); + if (!power_info->power_down_setting) { + kfree(power_info->power_setting); + power_info->power_setting = NULL; + power_info->power_setting_size = 0; + return -ENOMEM; + } + + while (tot_size < cmd_length) { + if (cam_sensor_validate(ptr, (cmd_length - tot_size))) { + rc = -EINVAL; + goto free_power_settings; + } + if (cmm_hdr->cmd_type == + CAMERA_SENSOR_CMD_TYPE_PWR_UP) { + struct cam_cmd_power *pwr_cmd = + (struct cam_cmd_power *)ptr; + + if ((U16_MAX - power_info->power_setting_size) < + pwr_cmd->count) { + CAM_ERR(CAM_SENSOR, "ERR: Overflow occurs"); + rc = -EINVAL; + goto free_power_settings; + } + + power_info->power_setting_size += pwr_cmd->count; + if ((power_info->power_setting_size > MAX_POWER_CONFIG) + || (pwr_cmd->count >= SENSOR_SEQ_TYPE_MAX)) { + CAM_ERR(CAM_SENSOR, + "pwr_up setting size %d, pwr_cmd->count: %d", + power_info->power_setting_size, + pwr_cmd->count); + rc = -EINVAL; + goto free_power_settings; + } + scr = ptr + sizeof(struct cam_cmd_power); + tot_size = tot_size + sizeof(struct cam_cmd_power); + + if (pwr_cmd->count == 0) + CAM_WARN(CAM_SENSOR, "pwr_up_size is zero"); + + for (i = 0; i < pwr_cmd->count; i++, pwr_up++) { + power_info->power_setting[pwr_up].seq_type = + pwr_cmd->power_settings[i].power_seq_type; + power_info->power_setting[pwr_up].config_val = + pwr_cmd->power_settings[i].config_val_low; + power_info->power_setting[pwr_up].delay = 0; + if (i) { + scr = scr + + sizeof( + struct cam_power_settings); + tot_size = tot_size + + sizeof( + struct cam_power_settings); + } + if (tot_size > cmd_length) { + CAM_ERR(CAM_SENSOR, + "Error: Cmd Buffer is wrong"); + rc = -EINVAL; + goto free_power_settings; + } + CAM_DBG(CAM_SENSOR, + "Seq Type[%d]: %d Config_val: %ld", pwr_up, + power_info->power_setting[pwr_up].seq_type, + power_info->power_setting[pwr_up].config_val); + } + last_cmd_type = CAMERA_SENSOR_CMD_TYPE_PWR_UP; + ptr = (void *) scr; + cmm_hdr = (struct common_header *)ptr; + } else if (cmm_hdr->cmd_type == CAMERA_SENSOR_CMD_TYPE_WAIT) { + struct cam_cmd_unconditional_wait *wait_cmd = + (struct cam_cmd_unconditional_wait *)ptr; + if ((wait_cmd->op_code == + CAMERA_SENSOR_WAIT_OP_SW_UCND) && + (last_cmd_type == + CAMERA_SENSOR_CMD_TYPE_PWR_UP)) { + if (pwr_up > 0) { + pwr_settings = + &power_info->power_setting[pwr_up - 1]; + pwr_settings->delay += + wait_cmd->delay; + } else { + CAM_ERR(CAM_SENSOR, + "Delay is expected only after valid power up setting"); + } + } else if ((wait_cmd->op_code == + CAMERA_SENSOR_WAIT_OP_SW_UCND) && + (last_cmd_type == + CAMERA_SENSOR_CMD_TYPE_PWR_DOWN)) { + if (pwr_down > 0) { + pwr_settings = + &power_info->power_down_setting[ + pwr_down - 1]; + pwr_settings->delay += + wait_cmd->delay; + } else { + CAM_ERR(CAM_SENSOR, + "Delay is expected only after valid power up setting"); + } + } else { + CAM_DBG(CAM_SENSOR, "Invalid op code: %d", + wait_cmd->op_code); + } + + tot_size = tot_size + + sizeof(struct cam_cmd_unconditional_wait); + if (tot_size > cmd_length) { + CAM_ERR(CAM_SENSOR, "Command Buffer is wrong"); + return -EINVAL; + } + scr = (void *) (wait_cmd); + ptr = (void *) + (scr + + sizeof(struct cam_cmd_unconditional_wait)); + CAM_DBG(CAM_SENSOR, "ptr: %pK sizeof: %d Next: %pK", + scr, (int32_t)sizeof( + struct cam_cmd_unconditional_wait), ptr); + + cmm_hdr = (struct common_header *)ptr; + } else if (cmm_hdr->cmd_type == + CAMERA_SENSOR_CMD_TYPE_PWR_DOWN) { + struct cam_cmd_power *pwr_cmd = + (struct cam_cmd_power *)ptr; + + scr = ptr + sizeof(struct cam_cmd_power); + tot_size = tot_size + sizeof(struct cam_cmd_power); + if ((U16_MAX - power_info->power_down_setting_size) < + pwr_cmd->count) { + CAM_ERR(CAM_SENSOR, "ERR: Overflow"); + rc = -EINVAL; + goto free_power_settings; + } + + power_info->power_down_setting_size += pwr_cmd->count; + if ((power_info->power_down_setting_size > + MAX_POWER_CONFIG) || (pwr_cmd->count >= + SENSOR_SEQ_TYPE_MAX)) { + CAM_ERR(CAM_SENSOR, + "pwr_down_setting_size %d, pwr_cmd->count: %d", + power_info->power_down_setting_size, + pwr_cmd->count); + rc = -EINVAL; + goto free_power_settings; + } + + if (pwr_cmd->count == 0) + CAM_ERR(CAM_SENSOR, "pwr_down size is zero"); + + for (i = 0; i < pwr_cmd->count; i++, pwr_down++) { + pwr_settings = + &power_info->power_down_setting[pwr_down]; + pwr_settings->seq_type = + pwr_cmd->power_settings[i].power_seq_type; + pwr_settings->config_val = + pwr_cmd->power_settings[i].config_val_low; + power_info->power_down_setting[pwr_down].delay + = 0; + if (i) { + scr = scr + + sizeof( + struct cam_power_settings); + tot_size = + tot_size + + sizeof( + struct cam_power_settings); + } + if (tot_size > cmd_length) { + CAM_ERR(CAM_SENSOR, + "Command Buffer is wrong"); + rc = -EINVAL; + goto free_power_settings; + } + CAM_DBG(CAM_SENSOR, + "Seq Type[%d]: %d Config_val: %ld", + pwr_down, pwr_settings->seq_type, + pwr_settings->config_val); + } + last_cmd_type = CAMERA_SENSOR_CMD_TYPE_PWR_DOWN; + ptr = (void *) scr; + cmm_hdr = (struct common_header *)ptr; + } else { + CAM_ERR(CAM_SENSOR, + "Error: Un expected Header Type: %d", + cmm_hdr->cmd_type); + rc = -EINVAL; + goto free_power_settings; + } + } + + return rc; +free_power_settings: + kfree(power_info->power_down_setting); + kfree(power_info->power_setting); + power_info->power_down_setting = NULL; + power_info->power_setting = NULL; + power_info->power_down_setting_size = 0; + power_info->power_setting_size = 0; + return rc; +} + +int cam_get_dt_power_setting_data(struct device_node *of_node, + struct cam_hw_soc_info *soc_info, + struct cam_sensor_power_ctrl_t *power_info) +{ + int rc = 0, i; + int count = 0; + const char *seq_name = NULL; + uint32_t *array = NULL; + struct cam_sensor_power_setting *ps; + int c, end; + + if (!power_info) + return -EINVAL; + + count = of_property_count_strings(of_node, "qcom,cam-power-seq-type"); + power_info->power_setting_size = count; + + CAM_DBG(CAM_SENSOR, "qcom,cam-power-seq-type count %d", count); + + if (count <= 0) + return 0; + + ps = kcalloc(count, sizeof(*ps), GFP_KERNEL); + if (!ps) + return -ENOMEM; + power_info->power_setting = ps; + + for (i = 0; i < count; i++) { + rc = of_property_read_string_index(of_node, + "qcom,cam-power-seq-type", i, &seq_name); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed"); + goto ERROR1; + } + CAM_DBG(CAM_SENSOR, "seq_name[%d] = %s", i, seq_name); + if (!strcmp(seq_name, "cam_vio")) { + ps[i].seq_type = SENSOR_VIO; + } else if (!strcmp(seq_name, "cam_vana")) { + ps[i].seq_type = SENSOR_VANA; + } else if (!strcmp(seq_name, "cam_clk")) { + ps[i].seq_type = SENSOR_MCLK; + } else { + CAM_ERR(CAM_SENSOR, "unrecognized seq-type %s", + seq_name); + rc = -EILSEQ; + goto ERROR1; + } + CAM_DBG(CAM_SENSOR, "seq_type[%d] %d", i, ps[i].seq_type); + } + + array = kcalloc(count, sizeof(uint32_t), GFP_KERNEL); + if (!array) { + rc = -ENOMEM; + goto ERROR1; + } + + rc = of_property_read_u32_array(of_node, "qcom,cam-power-seq-cfg-val", + array, count); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed "); + goto ERROR2; + } + + for (i = 0; i < count; i++) { + ps[i].config_val = array[i]; + CAM_DBG(CAM_SENSOR, "power_setting[%d].config_val = %ld", i, + ps[i].config_val); + } + + rc = of_property_read_u32_array(of_node, "qcom,cam-power-seq-delay", + array, count); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "failed"); + goto ERROR2; + } + for (i = 0; i < count; i++) { + ps[i].delay = array[i]; + CAM_DBG(CAM_SENSOR, "power_setting[%d].delay = %d", i, + ps[i].delay); + } + kfree(array); + + power_info->power_down_setting = + kcalloc(count, sizeof(*ps), GFP_KERNEL); + + if (!power_info->power_down_setting) { + CAM_ERR(CAM_SENSOR, "failed"); + rc = -ENOMEM; + goto ERROR1; + } + + power_info->power_down_setting_size = count; + + end = count - 1; + + for (c = 0; c < count; c++) { + power_info->power_down_setting[c] = ps[end]; + end--; + } + return rc; +ERROR2: + kfree(array); +ERROR1: + kfree(ps); + return rc; +} + +int cam_sensor_util_init_gpio_pin_tbl( + struct cam_hw_soc_info *soc_info, + struct msm_camera_gpio_num_info **pgpio_num_info) +{ + int rc = 0, val = 0; + uint32_t gpio_array_size; + struct device_node *of_node = NULL; + struct cam_soc_gpio_data *gconf = NULL; + struct msm_camera_gpio_num_info *gpio_num_info = NULL; + + if (!soc_info->dev) { + CAM_ERR(CAM_SENSOR, "device node NULL"); + return -EINVAL; + } + + of_node = soc_info->dev->of_node; + + gconf = soc_info->gpio_data; + if (!gconf) { + CAM_ERR(CAM_SENSOR, "No gpio_common_table is found"); + return -EINVAL; + } + + if (!gconf->cam_gpio_common_tbl) { + CAM_ERR(CAM_SENSOR, "gpio_common_table is not initialized"); + return -EINVAL; + } + + gpio_array_size = gconf->cam_gpio_common_tbl_size; + + if (!gpio_array_size) { + CAM_ERR(CAM_SENSOR, "invalid size of gpio table"); + return -EINVAL; + } + + *pgpio_num_info = kzalloc(sizeof(struct msm_camera_gpio_num_info), + GFP_KERNEL); + if (!*pgpio_num_info) + return -ENOMEM; + gpio_num_info = *pgpio_num_info; + + rc = of_property_read_u32(of_node, "gpio-vana", &val); + if (rc != -EINVAL) { + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "read gpio-vana failed rc %d", rc); + goto free_gpio_info; + } else if (val >= gpio_array_size) { + CAM_ERR(CAM_SENSOR, "gpio-vana invalid %d", val); + rc = -EINVAL; + goto free_gpio_info; + } + gpio_num_info->gpio_num[SENSOR_VANA] = + gconf->cam_gpio_common_tbl[val].gpio; + gpio_num_info->valid[SENSOR_VANA] = 1; + + CAM_DBG(CAM_SENSOR, "gpio-vana %d", + gpio_num_info->gpio_num[SENSOR_VANA]); + } + + rc = of_property_read_u32(of_node, "gpio-vio", &val); + if (rc != -EINVAL) { + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "read gpio-vio failed rc %d", rc); + goto free_gpio_info; + } else if (val >= gpio_array_size) { + CAM_ERR(CAM_SENSOR, "gpio-vio invalid %d", val); + goto free_gpio_info; + } + gpio_num_info->gpio_num[SENSOR_VIO] = + gconf->cam_gpio_common_tbl[val].gpio; + gpio_num_info->valid[SENSOR_VIO] = 1; + + CAM_DBG(CAM_SENSOR, "gpio-vio %d", + gpio_num_info->gpio_num[SENSOR_VIO]); + } + + rc = of_property_read_u32(of_node, "gpio-vaf", &val); + if (rc != -EINVAL) { + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "read gpio-vaf failed rc %d", rc); + goto free_gpio_info; + } else if (val >= gpio_array_size) { + CAM_ERR(CAM_SENSOR, "gpio-vaf invalid %d", val); + rc = -EINVAL; + goto free_gpio_info; + } + gpio_num_info->gpio_num[SENSOR_VAF] = + gconf->cam_gpio_common_tbl[val].gpio; + gpio_num_info->valid[SENSOR_VAF] = 1; + + CAM_DBG(CAM_SENSOR, "gpio-vaf %d", + gpio_num_info->gpio_num[SENSOR_VAF]); + } + + rc = of_property_read_u32(of_node, "gpio-vdig", &val); + if (rc != -EINVAL) { + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "read gpio-vdig failed rc %d", rc); + goto free_gpio_info; + } else if (val >= gpio_array_size) { + CAM_ERR(CAM_SENSOR, "gpio-vdig invalid %d", val); + rc = -EINVAL; + goto free_gpio_info; + } + gpio_num_info->gpio_num[SENSOR_VDIG] = + gconf->cam_gpio_common_tbl[val].gpio; + gpio_num_info->valid[SENSOR_VDIG] = 1; + + CAM_DBG(CAM_SENSOR, "gpio-vdig %d", + gpio_num_info->gpio_num[SENSOR_VDIG]); + } + + rc = of_property_read_u32(of_node, "gpio-reset", &val); + if (rc != -EINVAL) { + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "read gpio-reset failed rc %d", rc); + goto free_gpio_info; + } else if (val >= gpio_array_size) { + CAM_ERR(CAM_SENSOR, "gpio-reset invalid %d", val); + rc = -EINVAL; + goto free_gpio_info; + } + gpio_num_info->gpio_num[SENSOR_RESET] = + gconf->cam_gpio_common_tbl[val].gpio; + gpio_num_info->valid[SENSOR_RESET] = 1; + + CAM_DBG(CAM_SENSOR, "gpio-reset %d", + gpio_num_info->gpio_num[SENSOR_RESET]); + } + + rc = of_property_read_u32(of_node, "gpio-standby", &val); + if (rc != -EINVAL) { + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "read gpio-standby failed rc %d", rc); + goto free_gpio_info; + } else if (val >= gpio_array_size) { + CAM_ERR(CAM_SENSOR, "gpio-standby invalid %d", val); + rc = -EINVAL; + goto free_gpio_info; + } + gpio_num_info->gpio_num[SENSOR_STANDBY] = + gconf->cam_gpio_common_tbl[val].gpio; + gpio_num_info->valid[SENSOR_STANDBY] = 1; + + CAM_DBG(CAM_SENSOR, "gpio-standby %d", + gpio_num_info->gpio_num[SENSOR_STANDBY]); + } + + rc = of_property_read_u32(of_node, "gpio-af-pwdm", &val); + if (rc != -EINVAL) { + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "read gpio-af-pwdm failed rc %d", rc); + goto free_gpio_info; + } else if (val >= gpio_array_size) { + CAM_ERR(CAM_SENSOR, "gpio-af-pwdm invalid %d", val); + rc = -EINVAL; + goto free_gpio_info; + } + gpio_num_info->gpio_num[SENSOR_VAF_PWDM] = + gconf->cam_gpio_common_tbl[val].gpio; + gpio_num_info->valid[SENSOR_VAF_PWDM] = 1; + + CAM_DBG(CAM_SENSOR, "gpio-af-pwdm %d", + gpio_num_info->gpio_num[SENSOR_VAF_PWDM]); + } + + rc = of_property_read_u32(of_node, "gpio-custom1", &val); + if (rc != -EINVAL) { + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "read gpio-custom1 failed rc %d", rc); + goto free_gpio_info; + } else if (val >= gpio_array_size) { + CAM_ERR(CAM_SENSOR, "gpio-custom1 invalid %d", val); + rc = -EINVAL; + goto free_gpio_info; + } + gpio_num_info->gpio_num[SENSOR_CUSTOM_GPIO1] = + gconf->cam_gpio_common_tbl[val].gpio; + gpio_num_info->valid[SENSOR_CUSTOM_GPIO1] = 1; + + CAM_DBG(CAM_SENSOR, "gpio-custom1 %d", + gpio_num_info->gpio_num[SENSOR_CUSTOM_GPIO1]); + } + + rc = of_property_read_u32(of_node, "gpio-custom2", &val); + if (rc != -EINVAL) { + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "read gpio-custom2 failed rc %d", rc); + goto free_gpio_info; + } else if (val >= gpio_array_size) { + CAM_ERR(CAM_SENSOR, "gpio-custom2 invalid %d", val); + rc = -EINVAL; + goto free_gpio_info; + } + gpio_num_info->gpio_num[SENSOR_CUSTOM_GPIO2] = + gconf->cam_gpio_common_tbl[val].gpio; + gpio_num_info->valid[SENSOR_CUSTOM_GPIO2] = 1; + + CAM_DBG(CAM_SENSOR, "gpio-custom2 %d", + gpio_num_info->gpio_num[SENSOR_CUSTOM_GPIO2]); + } else { + rc = 0; + } + + return rc; + +free_gpio_info: + kfree(gpio_num_info); + gpio_num_info = NULL; + return rc; +} + +int msm_camera_pinctrl_init( + struct msm_pinctrl_info *sensor_pctrl, struct device *dev) +{ + + sensor_pctrl->pinctrl = devm_pinctrl_get(dev); + if (IS_ERR_OR_NULL(sensor_pctrl->pinctrl)) { + CAM_DBG(CAM_SENSOR, "Getting pinctrl handle failed"); + return -EINVAL; + } + sensor_pctrl->gpio_state_active = + pinctrl_lookup_state(sensor_pctrl->pinctrl, + CAM_SENSOR_PINCTRL_STATE_DEFAULT); + if (IS_ERR_OR_NULL(sensor_pctrl->gpio_state_active)) { + CAM_ERR(CAM_SENSOR, + "Failed to get the active state pinctrl handle"); + return -EINVAL; + } + sensor_pctrl->gpio_state_suspend + = pinctrl_lookup_state(sensor_pctrl->pinctrl, + CAM_SENSOR_PINCTRL_STATE_SLEEP); + if (IS_ERR_OR_NULL(sensor_pctrl->gpio_state_suspend)) { + CAM_ERR(CAM_SENSOR, + "Failed to get the suspend state pinctrl handle"); + return -EINVAL; + } + + return 0; +} + +int cam_sensor_bob_pwm_mode_switch(struct cam_hw_soc_info *soc_info, + int bob_reg_idx, bool flag) +{ + int rc = 0; + uint32_t op_current = + (flag == true) ? soc_info->rgltr_op_mode[bob_reg_idx] : 0; + + if (soc_info->rgltr[bob_reg_idx] != NULL) { + rc = regulator_set_load(soc_info->rgltr[bob_reg_idx], + op_current); + if (rc) + CAM_WARN(CAM_SENSOR, + "BoB PWM SetLoad failed rc: %d", rc); + } + + return rc; +} + +int msm_cam_sensor_handle_reg_gpio(int seq_type, + struct msm_camera_gpio_num_info *gpio_num_info, int val) +{ + int gpio_offset = -1; + + if (!gpio_num_info) { + CAM_INFO(CAM_SENSOR, "Input Parameters are not proper"); + return 0; + } + + CAM_DBG(CAM_SENSOR, "Seq type: %d, config: %d", seq_type, val); + + gpio_offset = seq_type; + + if (gpio_num_info->valid[gpio_offset] == 1) { + CAM_DBG(CAM_SENSOR, "VALID GPIO offset: %d, seqtype: %d", + gpio_offset, seq_type); + cam_res_mgr_gpio_set_value( + gpio_num_info->gpio_num + [gpio_offset], val); + } + + return 0; +} + +static int cam_config_mclk_reg(struct cam_sensor_power_ctrl_t *ctrl, + struct cam_hw_soc_info *soc_info, int32_t index) +{ + int32_t num_vreg = 0, j = 0, rc = 0, idx = 0; + struct cam_sensor_power_setting *ps = NULL; + struct cam_sensor_power_setting *pd = NULL; + + num_vreg = soc_info->num_rgltr; + + pd = &ctrl->power_down_setting[index]; + + for (j = 0; j < num_vreg; j++) { + if (!strcmp(soc_info->rgltr_name[j], "cam_clk")) { + ps = NULL; + for (idx = 0; idx < ctrl->power_setting_size; idx++) { + if (ctrl->power_setting[idx].seq_type == + pd->seq_type) { + ps = &ctrl->power_setting[idx]; + break; + } + } + + if (ps != NULL) { + CAM_DBG(CAM_SENSOR, "Disable MCLK Regulator"); + rc = cam_soc_util_regulator_disable( + soc_info->rgltr[j], + soc_info->rgltr_name[j], + soc_info->rgltr_min_volt[j], + soc_info->rgltr_max_volt[j], + soc_info->rgltr_op_mode[j], + soc_info->rgltr_delay[j]); + + if (rc) { + CAM_ERR(CAM_SENSOR, + "MCLK REG DISALBE FAILED: %d", + rc); + return rc; + } + + ps->data[0] = + soc_info->rgltr[j]; + + regulator_put( + soc_info->rgltr[j]); + soc_info->rgltr[j] = NULL; + } + } + } + + return rc; +} + +int cam_sensor_core_power_up(struct cam_sensor_power_ctrl_t *ctrl, + struct cam_hw_soc_info *soc_info) +{ + int rc = 0, index = 0, no_gpio = 0, ret = 0, num_vreg, j = 0, i = 0; + int32_t vreg_idx = -1; + struct cam_sensor_power_setting *power_setting = NULL; + struct msm_camera_gpio_num_info *gpio_num_info = NULL; + + CAM_DBG(CAM_SENSOR, "Enter"); + if (!ctrl) { + CAM_ERR(CAM_SENSOR, "Invalid ctrl handle"); + return -EINVAL; + } + + gpio_num_info = ctrl->gpio_num_info; + num_vreg = soc_info->num_rgltr; + + if ((num_vreg <= 0) || (num_vreg > CAM_SOC_MAX_REGULATOR)) { + CAM_ERR(CAM_SENSOR, "failed: num_vreg %d", num_vreg); + return -EINVAL; + } + + if (soc_info->use_shared_clk) + cam_res_mgr_shared_clk_config(true); + + ret = msm_camera_pinctrl_init(&(ctrl->pinctrl_info), ctrl->dev); + if (ret < 0) { + /* Some sensor subdev no pinctrl. */ + CAM_DBG(CAM_SENSOR, "Initialization of pinctrl failed"); + ctrl->cam_pinctrl_status = 0; + } else { + ctrl->cam_pinctrl_status = 1; + } + + if (cam_res_mgr_shared_pinctrl_init()) { + CAM_ERR(CAM_SENSOR, + "Failed to init shared pinctrl"); + return -EINVAL; + } + + rc = cam_sensor_util_request_gpio_table(soc_info, 1); + if (rc < 0) + no_gpio = rc; + + if (ctrl->cam_pinctrl_status) { + ret = pinctrl_select_state( + ctrl->pinctrl_info.pinctrl, + ctrl->pinctrl_info.gpio_state_active); + if (ret) + CAM_ERR(CAM_SENSOR, "cannot set pin to active state"); + } + + ret = cam_res_mgr_shared_pinctrl_select_state(true); + if (ret) + CAM_ERR(CAM_SENSOR, + "Cannot set shared pin to active state"); + + CAM_DBG(CAM_SENSOR, "power setting size: %d", ctrl->power_setting_size); + + for (index = 0; index < ctrl->power_setting_size; index++) { + CAM_DBG(CAM_SENSOR, "index: %d", index); + power_setting = &ctrl->power_setting[index]; + if (!power_setting) { + CAM_ERR(CAM_SENSOR, + "Invalid power up settings for index %d", + index); + return -EINVAL; + } + + CAM_DBG(CAM_SENSOR, "seq_type %d", power_setting->seq_type); + + switch (power_setting->seq_type) { + case SENSOR_MCLK: + if (power_setting->seq_val >= soc_info->num_clk) { + CAM_ERR(CAM_SENSOR, "clk index %d >= max %u", + power_setting->seq_val, + soc_info->num_clk); + goto power_up_failed; + } + for (j = 0; j < num_vreg; j++) { + if (!strcmp(soc_info->rgltr_name[j], + "cam_clk")) { + CAM_DBG(CAM_SENSOR, + "Enable cam_clk: %d", j); + + soc_info->rgltr[j] = + regulator_get( + soc_info->dev, + soc_info->rgltr_name[j]); + + if (IS_ERR_OR_NULL( + soc_info->rgltr[j])) { + rc = PTR_ERR( + soc_info->rgltr[j]); + rc = rc ? rc : -EINVAL; + CAM_ERR(CAM_SENSOR, + "vreg %s %d", + soc_info->rgltr_name[j], + rc); + soc_info->rgltr[j] = NULL; + goto power_up_failed; + } + + rc = cam_soc_util_regulator_enable( + soc_info->rgltr[j], + soc_info->rgltr_name[j], + soc_info->rgltr_min_volt[j], + soc_info->rgltr_max_volt[j], + soc_info->rgltr_op_mode[j], + soc_info->rgltr_delay[j]); + if (rc) { + CAM_ERR(CAM_SENSOR, + "Reg enable failed"); + goto power_up_failed; + } + power_setting->data[0] = + soc_info->rgltr[j]; + } + } + if (power_setting->config_val) + soc_info->clk_rate[0][power_setting->seq_val] = + power_setting->config_val; + + for (j = 0; j < soc_info->num_clk; j++) { + rc = cam_soc_util_clk_enable(soc_info->clk[j], + soc_info->clk_name[j], + soc_info->clk_rate[0][j]); + if (rc) + break; + } + + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "clk enable failed"); + goto power_up_failed; + } + break; + case SENSOR_RESET: + case SENSOR_STANDBY: + case SENSOR_CUSTOM_GPIO1: + case SENSOR_CUSTOM_GPIO2: + if (no_gpio) { + CAM_ERR(CAM_SENSOR, "request gpio failed"); + goto power_up_failed; + } + if (!gpio_num_info) { + CAM_ERR(CAM_SENSOR, "Invalid gpio_num_info"); + goto power_up_failed; + } + CAM_DBG(CAM_SENSOR, "gpio set val %d", + gpio_num_info->gpio_num + [power_setting->seq_type]); + + rc = msm_cam_sensor_handle_reg_gpio( + power_setting->seq_type, + gpio_num_info, + (int) power_setting->config_val); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Error in handling VREG GPIO"); + goto power_up_failed; + } + break; + case SENSOR_VANA: + case SENSOR_VDIG: + case SENSOR_VIO: + case SENSOR_VAF: + case SENSOR_VAF_PWDM: + case SENSOR_CUSTOM_REG1: + case SENSOR_CUSTOM_REG2: + if (power_setting->seq_val == INVALID_VREG) + break; + + if (power_setting->seq_val >= CAM_VREG_MAX) { + CAM_ERR(CAM_SENSOR, "vreg index %d >= max %d", + power_setting->seq_val, + CAM_VREG_MAX); + goto power_up_failed; + } + if (power_setting->seq_val < num_vreg) { + CAM_DBG(CAM_SENSOR, "Enable Regulator"); + vreg_idx = power_setting->seq_val; + + soc_info->rgltr[vreg_idx] = + regulator_get(soc_info->dev, + soc_info->rgltr_name[vreg_idx]); + if (IS_ERR_OR_NULL( + soc_info->rgltr[vreg_idx])) { + rc = PTR_ERR(soc_info->rgltr[vreg_idx]); + rc = rc ? rc : -EINVAL; + + CAM_ERR(CAM_SENSOR, "%s get failed %d", + soc_info->rgltr_name[vreg_idx], + rc); + + soc_info->rgltr[vreg_idx] = NULL; + goto power_up_failed; + } + + rc = cam_soc_util_regulator_enable( + soc_info->rgltr[vreg_idx], + soc_info->rgltr_name[vreg_idx], + soc_info->rgltr_min_volt[vreg_idx], + soc_info->rgltr_max_volt[vreg_idx], + soc_info->rgltr_op_mode[vreg_idx], + soc_info->rgltr_delay[vreg_idx]); + if (rc) { + CAM_ERR(CAM_SENSOR, + "Reg Enable failed for %s", + soc_info->rgltr_name[vreg_idx]); + goto power_up_failed; + } + power_setting->data[0] = + soc_info->rgltr[vreg_idx]; + } else { + CAM_ERR(CAM_SENSOR, "usr_idx:%d dts_idx:%d", + power_setting->seq_val, num_vreg); + } + + rc = msm_cam_sensor_handle_reg_gpio( + power_setting->seq_type, + gpio_num_info, 1); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Error in handling VREG GPIO"); + goto power_up_failed; + } + break; + default: + CAM_ERR(CAM_SENSOR, "error power seq type %d", + power_setting->seq_type); + break; + } + if (power_setting->delay > 20) + msleep(power_setting->delay); + else if (power_setting->delay) + usleep_range(power_setting->delay * 1000, + (power_setting->delay * 1000) + 1000); + } + + ret = cam_res_mgr_shared_pinctrl_post_init(); + if (ret) + CAM_ERR(CAM_SENSOR, + "Failed to post init shared pinctrl"); + + return 0; +power_up_failed: + CAM_ERR(CAM_SENSOR, "failed"); + for (index--; index >= 0; index--) { + CAM_DBG(CAM_SENSOR, "index %d", index); + power_setting = &ctrl->power_setting[index]; + CAM_DBG(CAM_SENSOR, "type %d", + power_setting->seq_type); + switch (power_setting->seq_type) { + case SENSOR_MCLK: + for (i = soc_info->num_clk - 1; i >= 0; i--) { + cam_soc_util_clk_disable(soc_info->clk[i], + soc_info->clk_name[i]); + } + ret = cam_config_mclk_reg(ctrl, soc_info, index); + if (ret < 0) { + CAM_ERR(CAM_SENSOR, + "config clk reg failed rc: %d", ret); + continue; + } + break; + case SENSOR_RESET: + case SENSOR_STANDBY: + case SENSOR_CUSTOM_GPIO1: + case SENSOR_CUSTOM_GPIO2: + if (!gpio_num_info) + continue; + if (!gpio_num_info->valid + [power_setting->seq_type]) + continue; + cam_res_mgr_gpio_set_value( + gpio_num_info->gpio_num + [power_setting->seq_type], GPIOF_OUT_INIT_LOW); + break; + case SENSOR_VANA: + case SENSOR_VDIG: + case SENSOR_VIO: + case SENSOR_VAF: + case SENSOR_VAF_PWDM: + case SENSOR_CUSTOM_REG1: + case SENSOR_CUSTOM_REG2: + if (power_setting->seq_val < num_vreg) { + CAM_DBG(CAM_SENSOR, "Disable Regulator"); + vreg_idx = power_setting->seq_val; + + rc = cam_soc_util_regulator_disable( + soc_info->rgltr[vreg_idx], + soc_info->rgltr_name[vreg_idx], + soc_info->rgltr_min_volt[vreg_idx], + soc_info->rgltr_max_volt[vreg_idx], + soc_info->rgltr_op_mode[vreg_idx], + soc_info->rgltr_delay[vreg_idx]); + + if (rc) { + CAM_ERR(CAM_SENSOR, + "Fail to disalbe reg: %s", + soc_info->rgltr_name[vreg_idx]); + soc_info->rgltr[vreg_idx] = NULL; + msm_cam_sensor_handle_reg_gpio( + power_setting->seq_type, + gpio_num_info, + GPIOF_OUT_INIT_LOW); + continue; + } + power_setting->data[0] = + soc_info->rgltr[vreg_idx]; + + regulator_put(soc_info->rgltr[vreg_idx]); + soc_info->rgltr[vreg_idx] = NULL; + } else { + CAM_ERR(CAM_SENSOR, "seq_val:%d > num_vreg: %d", + power_setting->seq_val, num_vreg); + } + + msm_cam_sensor_handle_reg_gpio(power_setting->seq_type, + gpio_num_info, GPIOF_OUT_INIT_LOW); + + break; + default: + CAM_ERR(CAM_SENSOR, "error power seq type %d", + power_setting->seq_type); + break; + } + if (power_setting->delay > 20) { + msleep(power_setting->delay); + } else if (power_setting->delay) { + usleep_range(power_setting->delay * 1000, + (power_setting->delay * 1000) + 1000); + } + } + + if (ctrl->cam_pinctrl_status) { + ret = pinctrl_select_state( + ctrl->pinctrl_info.pinctrl, + ctrl->pinctrl_info.gpio_state_suspend); + if (ret) + CAM_ERR(CAM_SENSOR, "cannot set pin to suspend state"); + devm_pinctrl_put(ctrl->pinctrl_info.pinctrl); + } + + if (soc_info->use_shared_clk) + cam_res_mgr_shared_clk_config(false); + + cam_res_mgr_shared_pinctrl_select_state(false); + cam_res_mgr_shared_pinctrl_put(); + + ctrl->cam_pinctrl_status = 0; + + cam_sensor_util_request_gpio_table(soc_info, 0); + + return rc; +} + +static struct cam_sensor_power_setting* +msm_camera_get_power_settings(struct cam_sensor_power_ctrl_t *ctrl, + enum msm_camera_power_seq_type seq_type, + uint16_t seq_val) +{ + struct cam_sensor_power_setting *power_setting, *ps = NULL; + int idx; + + for (idx = 0; idx < ctrl->power_setting_size; idx++) { + power_setting = &ctrl->power_setting[idx]; + if (power_setting->seq_type == seq_type && + power_setting->seq_val == seq_val) { + ps = power_setting; + return ps; + } + + } + + return ps; +} + +int cam_sensor_util_power_down(struct cam_sensor_power_ctrl_t *ctrl, + struct cam_hw_soc_info *soc_info) +{ + int index = 0, ret = 0, num_vreg = 0, i; + struct cam_sensor_power_setting *pd = NULL; + struct cam_sensor_power_setting *ps = NULL; + struct msm_camera_gpio_num_info *gpio_num_info = NULL; + + CAM_DBG(CAM_SENSOR, "Enter"); + if (!ctrl || !soc_info) { + CAM_ERR(CAM_SENSOR, "failed ctrl %pK", ctrl); + return -EINVAL; + } + + gpio_num_info = ctrl->gpio_num_info; + num_vreg = soc_info->num_rgltr; + + if ((num_vreg <= 0) || (num_vreg > CAM_SOC_MAX_REGULATOR)) { + CAM_ERR(CAM_SENSOR, "failed: num_vreg %d", num_vreg); + return -EINVAL; + } + + if (ctrl->power_down_setting_size > MAX_POWER_CONFIG) { + CAM_ERR(CAM_SENSOR, "Invalid: power setting size %d", + ctrl->power_setting_size); + return -EINVAL; + } + + for (index = 0; index < ctrl->power_down_setting_size; index++) { + CAM_DBG(CAM_SENSOR, "power_down_index %d", index); + pd = &ctrl->power_down_setting[index]; + if (!pd) { + CAM_ERR(CAM_SENSOR, + "Invalid power down settings for index %d", + index); + return -EINVAL; + } + + ps = NULL; + CAM_DBG(CAM_SENSOR, "seq_type %d", pd->seq_type); + switch (pd->seq_type) { + case SENSOR_MCLK: + for (i = soc_info->num_clk - 1; i >= 0; i--) { + cam_soc_util_clk_disable(soc_info->clk[i], + soc_info->clk_name[i]); + } + + ret = cam_config_mclk_reg(ctrl, soc_info, index); + if (ret < 0) { + CAM_ERR(CAM_SENSOR, + "config clk reg failed rc: %d", ret); + continue; + } + break; + case SENSOR_RESET: + case SENSOR_STANDBY: + case SENSOR_CUSTOM_GPIO1: + case SENSOR_CUSTOM_GPIO2: + + if (!gpio_num_info->valid[pd->seq_type]) + continue; + + cam_res_mgr_gpio_set_value( + gpio_num_info->gpio_num + [pd->seq_type], + (int) pd->config_val); + + break; + case SENSOR_VANA: + case SENSOR_VDIG: + case SENSOR_VIO: + case SENSOR_VAF: + case SENSOR_VAF_PWDM: + case SENSOR_CUSTOM_REG1: + case SENSOR_CUSTOM_REG2: + if (pd->seq_val == INVALID_VREG) + break; + + ps = msm_camera_get_power_settings( + ctrl, pd->seq_type, + pd->seq_val); + if (ps) { + if (pd->seq_val < num_vreg) { + CAM_DBG(CAM_SENSOR, + "Disable Regulator"); + ret = cam_soc_util_regulator_disable( + soc_info->rgltr[ps->seq_val], + soc_info->rgltr_name[ps->seq_val], + soc_info->rgltr_min_volt[ps->seq_val], + soc_info->rgltr_max_volt[ps->seq_val], + soc_info->rgltr_op_mode[ps->seq_val], + soc_info->rgltr_delay[ps->seq_val]); + if (ret) { + CAM_ERR(CAM_SENSOR, + "Reg: %s disable failed", + soc_info->rgltr_name[ + ps->seq_val]); + soc_info->rgltr[ps->seq_val] = + NULL; + msm_cam_sensor_handle_reg_gpio( + pd->seq_type, + gpio_num_info, + GPIOF_OUT_INIT_LOW); + continue; + } + ps->data[0] = + soc_info->rgltr[ps->seq_val]; + regulator_put( + soc_info->rgltr[ps->seq_val]); + soc_info->rgltr[ps->seq_val] = NULL; + } else { + CAM_ERR(CAM_SENSOR, + "seq_val:%d > num_vreg: %d", + pd->seq_val, + num_vreg); + } + } else + CAM_ERR(CAM_SENSOR, + "error in power up/down seq"); + + ret = msm_cam_sensor_handle_reg_gpio(pd->seq_type, + gpio_num_info, GPIOF_OUT_INIT_LOW); + + if (ret < 0) + CAM_ERR(CAM_SENSOR, + "Error disabling VREG GPIO"); + break; + default: + CAM_ERR(CAM_SENSOR, "error power seq type %d", + pd->seq_type); + break; + } + if (pd->delay > 20) + msleep(pd->delay); + else if (pd->delay) + usleep_range(pd->delay * 1000, + (pd->delay * 1000) + 1000); + } + + if (ctrl->cam_pinctrl_status) { + ret = pinctrl_select_state( + ctrl->pinctrl_info.pinctrl, + ctrl->pinctrl_info.gpio_state_suspend); + if (ret) + CAM_ERR(CAM_SENSOR, "cannot set pin to suspend state"); + + devm_pinctrl_put(ctrl->pinctrl_info.pinctrl); + } + + if (soc_info->use_shared_clk) + cam_res_mgr_shared_clk_config(false); + + cam_res_mgr_shared_pinctrl_select_state(false); + cam_res_mgr_shared_pinctrl_put(); + + ctrl->cam_pinctrl_status = 0; + + cam_sensor_util_request_gpio_table(soc_info, 0); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h new file mode 100644 index 0000000000000000000000000000000000000000..3600b5636caba5a0667ff90660c016c6b1f68fef --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_SENSOR_UTIL_H_ +#define _CAM_SENSOR_UTIL_H_ + +#include +#include +#include +#include +#include +#include "cam_sensor_cmn_header.h" +#include "cam_req_mgr_util.h" +#include "cam_req_mgr_interface.h" +#include +#include "cam_soc_util.h" +#include "cam_debug_util.h" +#include "cam_sensor_io.h" + +#define INVALID_VREG 100 + +int cam_get_dt_power_setting_data(struct device_node *of_node, + struct cam_hw_soc_info *soc_info, + struct cam_sensor_power_ctrl_t *power_info); + +int msm_camera_pinctrl_init + (struct msm_pinctrl_info *sensor_pctrl, struct device *dev); + +int cam_sensor_i2c_command_parser(struct camera_io_master *io_master, + struct i2c_settings_array *i2c_reg_settings, + struct cam_cmd_buf_desc *cmd_desc, int32_t num_cmd_buffers, + struct cam_buf_io_cfg *io_cfg); + +int cam_sensor_util_i2c_apply_setting(struct camera_io_master *io_master_info, + struct i2c_settings_list *i2c_list); + +int32_t cam_sensor_i2c_read_data( + struct i2c_settings_array *i2c_settings, + struct camera_io_master *io_master_info); + +int32_t delete_request(struct i2c_settings_array *i2c_array); +int cam_sensor_util_request_gpio_table( + struct cam_hw_soc_info *soc_info, int gpio_en); + +int cam_sensor_util_init_gpio_pin_tbl( + struct cam_hw_soc_info *soc_info, + struct msm_camera_gpio_num_info **pgpio_num_info); +int cam_sensor_core_power_up(struct cam_sensor_power_ctrl_t *ctrl, + struct cam_hw_soc_info *soc_info); + +int cam_sensor_util_power_down(struct cam_sensor_power_ctrl_t *ctrl, + struct cam_hw_soc_info *soc_info); + +int msm_camera_fill_vreg_params(struct cam_hw_soc_info *soc_info, + struct cam_sensor_power_setting *power_setting, + uint16_t power_setting_size); + +int32_t cam_sensor_update_power_settings(void *cmd_buf, + uint32_t cmd_length, struct cam_sensor_power_ctrl_t *power_info, + size_t cmd_buf_len); + +int cam_sensor_bob_pwm_mode_switch(struct cam_hw_soc_info *soc_info, + int bob_reg_idx, bool flag); +#endif /* _CAM_SENSOR_UTIL_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_smmu/Makefile b/techpack/camera-bengal/drivers/cam_smmu/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..fe210c2663ee6dff958317b82fa1af69fb83c363 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_smmu/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_smmu_api.o diff --git a/techpack/camera-bengal/drivers/cam_smmu/cam_smmu_api.c b/techpack/camera-bengal/drivers/cam_smmu/cam_smmu_api.c new file mode 100644 index 0000000000000000000000000000000000000000..49db0ec16079b2363a01a383aeb238427bdd9b6c --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_smmu/cam_smmu_api.c @@ -0,0 +1,4047 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "cam_smmu_api.h" +#include "cam_debug_util.h" +#include "cam_trace.h" +#include "cam_common_util.h" + +#define SHARED_MEM_POOL_GRANULARITY 16 + +#define IOMMU_INVALID_DIR -1 +#define BYTE_SIZE 8 +#define COOKIE_NUM_BYTE 2 +#define COOKIE_SIZE (BYTE_SIZE*COOKIE_NUM_BYTE) +#define COOKIE_MASK ((1<> COOKIE_SIZE) & COOKIE_MASK) + +#define CAM_SMMU_MONITOR_MAX_ENTRIES 100 +#define CAM_SMMU_INC_MONITOR_HEAD(head, ret) \ + div_u64_rem(atomic64_add_return(1, head),\ + CAM_SMMU_MONITOR_MAX_ENTRIES, (ret)) + +static int g_num_pf_handled = 4; +module_param(g_num_pf_handled, int, 0644); + +struct firmware_alloc_info { + struct device *fw_dev; + void *fw_kva; + dma_addr_t fw_dma_hdl; +}; + +struct firmware_alloc_info icp_fw; + +struct cam_smmu_work_payload { + int idx; + struct iommu_domain *domain; + struct device *dev; + unsigned long iova; + int flags; + void *token; + struct list_head list; +}; + +enum cam_protection_type { + CAM_PROT_INVALID, + CAM_NON_SECURE, + CAM_SECURE, + CAM_PROT_MAX, +}; + +enum cam_iommu_type { + CAM_SMMU_INVALID, + CAM_QSMMU, + CAM_ARM_SMMU, + CAM_SMMU_MAX, +}; + +enum cam_smmu_buf_state { + CAM_SMMU_BUFF_EXIST, + CAM_SMMU_BUFF_NOT_EXIST, +}; + +enum cam_smmu_init_dir { + CAM_SMMU_TABLE_INIT, + CAM_SMMU_TABLE_DEINIT, +}; + +struct scratch_mapping { + void *bitmap; + size_t bits; + unsigned int order; + dma_addr_t base; +}; + +struct secheap_buf_info { + struct dma_buf *buf; + struct dma_buf_attachment *attach; + struct sg_table *table; +}; + +struct cam_smmu_monitor { + struct timespec64 timestamp; + bool is_map; + + /* map-unmap info */ + int ion_fd; + dma_addr_t paddr; + size_t len; + enum cam_smmu_region_id region_id; +}; + +struct cam_context_bank_info { + struct device *dev; + struct iommu_domain *domain; + dma_addr_t va_start; + size_t va_len; + const char *name[CAM_SMMU_SHARED_HDL_MAX]; + bool is_secure; + uint8_t scratch_buf_support; + uint8_t firmware_support; + uint8_t shared_support; + uint8_t io_support; + uint8_t secheap_support; + uint8_t qdss_support; + dma_addr_t qdss_phy_addr; + bool is_fw_allocated; + bool is_secheap_allocated; + bool is_qdss_allocated; + + struct scratch_mapping scratch_map; + struct gen_pool *shared_mem_pool; + + struct cam_smmu_region_info scratch_info; + struct cam_smmu_region_info firmware_info; + struct cam_smmu_region_info shared_info; + struct cam_smmu_region_info io_info; + struct cam_smmu_region_info secheap_info; + struct cam_smmu_region_info qdss_info; + struct secheap_buf_info secheap_buf; + + struct list_head smmu_buf_list; + struct list_head smmu_buf_kernel_list; + struct mutex lock; + int handle; + enum cam_smmu_ops_param state; + + cam_smmu_client_page_fault_handler handler[CAM_SMMU_CB_MAX]; + void *token[CAM_SMMU_CB_MAX]; + int cb_count; + int secure_count; + int pf_count; + size_t io_mapping_size; + size_t shared_mapping_size; + bool is_mul_client; + int device_count; + int num_shared_hdl; + + /* discard iova - non-zero values are valid */ + dma_addr_t discard_iova_start; + size_t discard_iova_len; + + atomic64_t monitor_head; + struct cam_smmu_monitor monitor_entries[CAM_SMMU_MONITOR_MAX_ENTRIES]; +}; + +struct cam_iommu_cb_set { + struct cam_context_bank_info *cb_info; + u32 cb_num; + u32 cb_init_count; + struct work_struct smmu_work; + struct mutex payload_list_lock; + struct list_head payload_list; + u32 non_fatal_fault; + struct dentry *dentry; + bool cb_dump_enable; + bool map_profile_enable; +}; + +static const struct of_device_id msm_cam_smmu_dt_match[] = { + { .compatible = "qcom,msm-cam-smmu", }, + { .compatible = "qcom,msm-cam-smmu-cb", }, + { .compatible = "qcom,msm-cam-smmu-fw-dev", }, + {} +}; + +struct cam_dma_buff_info { + struct dma_buf *buf; + struct dma_buf_attachment *attach; + struct sg_table *table; + enum dma_data_direction dir; + enum cam_smmu_region_id region_id; + int iommu_dir; + int ref_count; + dma_addr_t paddr; + struct list_head list; + int ion_fd; + size_t len; + size_t phys_len; +}; + +struct cam_sec_buff_info { + struct dma_buf *buf; + struct dma_buf_attachment *attach; + struct sg_table *table; + enum dma_data_direction dir; + int ref_count; + dma_addr_t paddr; + struct list_head list; + int ion_fd; + size_t len; +}; + +static const char *qdss_region_name = "qdss"; + +static struct cam_iommu_cb_set iommu_cb_set; + +static enum dma_data_direction cam_smmu_translate_dir( + enum cam_smmu_map_dir dir); + +static int cam_smmu_check_handle_unique(int hdl); + +static int cam_smmu_create_iommu_handle(int idx); + +static int cam_smmu_create_add_handle_in_table(char *name, + int *hdl); + +static struct cam_dma_buff_info *cam_smmu_find_mapping_by_ion_index(int idx, + int ion_fd); + +static struct cam_dma_buff_info *cam_smmu_find_mapping_by_dma_buf(int idx, + struct dma_buf *buf); + +static struct cam_sec_buff_info *cam_smmu_find_mapping_by_sec_buf_idx(int idx, + int ion_fd); + +static int cam_smmu_init_scratch_map(struct scratch_mapping *scratch_map, + dma_addr_t base, size_t size, + int order); + +static int cam_smmu_alloc_scratch_va(struct scratch_mapping *mapping, + size_t size, + dma_addr_t *iova); + +static int cam_smmu_free_scratch_va(struct scratch_mapping *mapping, + dma_addr_t addr, size_t size); + +static struct cam_dma_buff_info *cam_smmu_find_mapping_by_virt_address(int idx, + dma_addr_t virt_addr); + +static int cam_smmu_map_buffer_and_add_to_list(int idx, int ion_fd, + bool dis_delayed_unmap, enum dma_data_direction dma_dir, + dma_addr_t *paddr_ptr, size_t *len_ptr, + enum cam_smmu_region_id region_id); + +static int cam_smmu_map_kernel_buffer_and_add_to_list(int idx, + struct dma_buf *buf, enum dma_data_direction dma_dir, + dma_addr_t *paddr_ptr, size_t *len_ptr, + enum cam_smmu_region_id region_id); + +static int cam_smmu_alloc_scratch_buffer_add_to_list(int idx, + size_t virt_len, + size_t phys_len, + unsigned int iommu_dir, + dma_addr_t *virt_addr); + +static int cam_smmu_unmap_buf_and_remove_from_list( + struct cam_dma_buff_info *mapping_info, int idx); + +static int cam_smmu_free_scratch_buffer_remove_from_list( + struct cam_dma_buff_info *mapping_info, + int idx); + +static void cam_smmu_clean_user_buffer_list(int idx); + +static void cam_smmu_clean_kernel_buffer_list(int idx); + +static void cam_smmu_dump_cb_info(int idx); + +static void cam_smmu_print_user_list(int idx); + +static void cam_smmu_print_kernel_list(int idx); + +static void cam_smmu_print_table(void); + +static int cam_smmu_probe(struct platform_device *pdev); + +static uint32_t cam_smmu_find_closest_mapping(int idx, void *vaddr); + +static void cam_smmu_update_monitor_array( + struct cam_context_bank_info *cb_info, + bool is_map, + struct cam_dma_buff_info *mapping_info) +{ + int iterator; + + CAM_SMMU_INC_MONITOR_HEAD(&cb_info->monitor_head, &iterator); + + ktime_get_real_ts64(&cb_info->monitor_entries[iterator].timestamp); + + cb_info->monitor_entries[iterator].is_map = is_map; + cb_info->monitor_entries[iterator].ion_fd = mapping_info->ion_fd; + cb_info->monitor_entries[iterator].paddr = mapping_info->paddr; + cb_info->monitor_entries[iterator].len = mapping_info->len; + cb_info->monitor_entries[iterator].region_id = mapping_info->region_id; +} + +static void cam_smmu_dump_monitor_array( + struct cam_context_bank_info *cb_info) +{ + int i = 0; + int64_t state_head = 0; + uint32_t index, num_entries, oldest_entry; + uint64_t ms, tmp, hrs, min, sec; + struct timespec64 *ts = NULL; + + state_head = atomic64_read(&cb_info->monitor_head); + + if (state_head == -1) { + return; + } else if (state_head < CAM_SMMU_MONITOR_MAX_ENTRIES) { + num_entries = state_head; + oldest_entry = 0; + } else { + num_entries = CAM_SMMU_MONITOR_MAX_ENTRIES; + div_u64_rem(state_head + 1, + CAM_SMMU_MONITOR_MAX_ENTRIES, &oldest_entry); + } + + CAM_INFO(CAM_SMMU, + "========Dumping monitor information for cb %s===========", + cb_info->name[0]); + + index = oldest_entry; + + for (i = 0; i < num_entries; i++) { + ts = &cb_info->monitor_entries[index].timestamp; + tmp = ts->tv_sec; + ms = (ts->tv_nsec) / 1000000; + sec = do_div(tmp, 60); + min = do_div(tmp, 60); + hrs = do_div(tmp, 24); + + CAM_INFO(CAM_SMMU, + "**** %llu:%llu:%llu.%llu : Index[%d] [%s] : ion_fd=%d start=0x%x end=0x%x len=%u region=%d", + hrs, min, sec, ms, + index, + cb_info->monitor_entries[index].is_map ? "MAP" : "UNMAP", + cb_info->monitor_entries[index].ion_fd, + (void *)cb_info->monitor_entries[index].paddr, + ((uint64_t)cb_info->monitor_entries[index].paddr + + (uint64_t)cb_info->monitor_entries[index].len), + (unsigned int)cb_info->monitor_entries[index].len, + cb_info->monitor_entries[index].region_id); + + index = (index + 1) % CAM_SMMU_MONITOR_MAX_ENTRIES; + } +} + +static void cam_smmu_page_fault_work(struct work_struct *work) +{ + int j; + int idx; + struct cam_smmu_work_payload *payload; + uint32_t buf_info; + + mutex_lock(&iommu_cb_set.payload_list_lock); + if (list_empty(&iommu_cb_set.payload_list)) { + CAM_ERR(CAM_SMMU, "Payload list empty"); + mutex_unlock(&iommu_cb_set.payload_list_lock); + return; + } + + payload = list_first_entry(&iommu_cb_set.payload_list, + struct cam_smmu_work_payload, + list); + list_del(&payload->list); + mutex_unlock(&iommu_cb_set.payload_list_lock); + + /* Dereference the payload to call the handler */ + idx = payload->idx; + buf_info = cam_smmu_find_closest_mapping(idx, (void *)payload->iova); + if (buf_info != 0) + CAM_INFO(CAM_SMMU, "closest buf 0x%x idx %d", buf_info, idx); + + for (j = 0; j < CAM_SMMU_CB_MAX; j++) { + if ((iommu_cb_set.cb_info[idx].handler[j])) { + iommu_cb_set.cb_info[idx].handler[j]( + payload->domain, + payload->dev, + payload->iova, + payload->flags, + iommu_cb_set.cb_info[idx].token[j], + buf_info); + } + } + cam_smmu_dump_cb_info(idx); + kfree(payload); +} + +static void cam_smmu_dump_cb_info(int idx) +{ + struct cam_dma_buff_info *mapping, *mapping_temp; + size_t shared_reg_len = 0, io_reg_len = 0; + size_t shared_free_len = 0, io_free_len = 0; + uint32_t i = 0; + struct cam_context_bank_info *cb_info = + &iommu_cb_set.cb_info[idx]; + + if (cb_info->shared_support) { + shared_reg_len = cb_info->shared_info.iova_len; + shared_free_len = shared_reg_len - cb_info->shared_mapping_size; + } + + if (cb_info->io_support) { + io_reg_len = cb_info->io_info.iova_len; + io_free_len = io_reg_len - cb_info->io_mapping_size; + } + + CAM_ERR(CAM_SMMU, + "********** Context bank dump for %s **********", + cb_info->name[0]); + CAM_ERR(CAM_SMMU, + "Usage: shared_usage=%u io_usage=%u shared_free=%u io_free=%u", + (unsigned int)cb_info->shared_mapping_size, + (unsigned int)cb_info->io_mapping_size, + (unsigned int)shared_free_len, + (unsigned int)io_free_len); + + if (iommu_cb_set.cb_dump_enable) { + list_for_each_entry_safe(mapping, mapping_temp, + &iommu_cb_set.cb_info[idx].smmu_buf_list, list) { + i++; + CAM_ERR(CAM_SMMU, + "%u. ion_fd=%d start=0x%x end=0x%x len=%u region=%d", + i, mapping->ion_fd, (void *)mapping->paddr, + ((uint64_t)mapping->paddr + + (uint64_t)mapping->len), + (unsigned int)mapping->len, + mapping->region_id); + } + + cam_smmu_dump_monitor_array(&iommu_cb_set.cb_info[idx]); + } +} + +static void cam_smmu_print_user_list(int idx) +{ + struct cam_dma_buff_info *mapping; + + CAM_ERR(CAM_SMMU, "index = %d", idx); + list_for_each_entry(mapping, + &iommu_cb_set.cb_info[idx].smmu_buf_list, list) { + CAM_ERR(CAM_SMMU, + "ion_fd = %d, paddr= 0x%pK, len = %u, region = %d", + mapping->ion_fd, (void *)mapping->paddr, + (unsigned int)mapping->len, + mapping->region_id); + } +} + +static void cam_smmu_print_kernel_list(int idx) +{ + struct cam_dma_buff_info *mapping; + + CAM_ERR(CAM_SMMU, "index = %d", idx); + list_for_each_entry(mapping, + &iommu_cb_set.cb_info[idx].smmu_buf_kernel_list, list) { + CAM_ERR(CAM_SMMU, + "dma_buf = %pK, paddr= 0x%pK, len = %u, region = %d", + mapping->buf, (void *)mapping->paddr, + (unsigned int)mapping->len, + mapping->region_id); + } +} + +static void cam_smmu_print_table(void) +{ + int i, j; + + for (i = 0; i < iommu_cb_set.cb_num; i++) { + for (j = 0; j < iommu_cb_set.cb_info[i].num_shared_hdl; j++) { + CAM_ERR(CAM_SMMU, + "i= %d, handle= %d, name_addr=%pK name %s", + i, (int)iommu_cb_set.cb_info[i].handle, + (void *)iommu_cb_set.cb_info[i].name[j], + iommu_cb_set.cb_info[i].name[j]); + } + CAM_ERR(CAM_SMMU, "dev = %pK", iommu_cb_set.cb_info[i].dev); + } +} + +static uint32_t cam_smmu_find_closest_mapping(int idx, void *vaddr) +{ + struct cam_dma_buff_info *mapping, *closest_mapping = NULL; + unsigned long start_addr, end_addr, current_addr; + uint32_t buf_handle = 0; + + long delta = 0, lowest_delta = 0; + + current_addr = (unsigned long)vaddr; + list_for_each_entry(mapping, + &iommu_cb_set.cb_info[idx].smmu_buf_list, list) { + start_addr = (unsigned long)mapping->paddr; + end_addr = (unsigned long)mapping->paddr + mapping->len; + + if (start_addr <= current_addr && current_addr <= end_addr) { + closest_mapping = mapping; + CAM_INFO(CAM_SMMU, + "Found va 0x%lx in:0x%lx-0x%lx, fd %d cb:%s", + current_addr, start_addr, + end_addr, mapping->ion_fd, + iommu_cb_set.cb_info[idx].name[0]); + goto end; + } else { + if (start_addr > current_addr) + delta = start_addr - current_addr; + else + delta = current_addr - end_addr - 1; + + if (delta < lowest_delta || lowest_delta == 0) { + lowest_delta = delta; + closest_mapping = mapping; + } + CAM_DBG(CAM_SMMU, + "approx va %lx not in range: %lx-%lx fd = %0x", + current_addr, start_addr, + end_addr, mapping->ion_fd); + } + } + +end: + if (closest_mapping) { + buf_handle = GET_MEM_HANDLE(idx, closest_mapping->ion_fd); + CAM_INFO(CAM_SMMU, + "Closest map fd %d 0x%lx %llu-%llu 0x%lx-0x%lx buf=%pK mem %0x", + closest_mapping->ion_fd, current_addr, + mapping->len, closest_mapping->len, + (unsigned long)closest_mapping->paddr, + (unsigned long)closest_mapping->paddr + mapping->len, + closest_mapping->buf, + buf_handle); + } else + CAM_ERR(CAM_SMMU, + "Cannot find vaddr:%lx in SMMU %s virt address", + current_addr, iommu_cb_set.cb_info[idx].name[0]); + + return buf_handle; +} + +void cam_smmu_set_client_page_fault_handler(int handle, + cam_smmu_client_page_fault_handler handler_cb, void *token) +{ + int idx, i = 0; + + if (!token || (handle == HANDLE_INIT)) { + CAM_ERR(CAM_SMMU, "Error: token is NULL or invalid handle"); + return; + } + + idx = GET_SMMU_TABLE_IDX(handle); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, handle); + return; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, handle); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return; + } + + if (handler_cb) { + if (iommu_cb_set.cb_info[idx].cb_count == CAM_SMMU_CB_MAX) { + CAM_ERR(CAM_SMMU, + "%s Should not regiester more handlers", + iommu_cb_set.cb_info[idx].name[0]); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return; + } + + iommu_cb_set.cb_info[idx].cb_count++; + + for (i = 0; i < iommu_cb_set.cb_info[idx].cb_count; i++) { + if (iommu_cb_set.cb_info[idx].token[i] == NULL) { + iommu_cb_set.cb_info[idx].token[i] = token; + iommu_cb_set.cb_info[idx].handler[i] = + handler_cb; + break; + } + } + } else { + for (i = 0; i < CAM_SMMU_CB_MAX; i++) { + if (iommu_cb_set.cb_info[idx].token[i] == token) { + iommu_cb_set.cb_info[idx].token[i] = NULL; + iommu_cb_set.cb_info[idx].handler[i] = + NULL; + iommu_cb_set.cb_info[idx].cb_count--; + break; + } + } + if (i == CAM_SMMU_CB_MAX) + CAM_ERR(CAM_SMMU, + "Error: hdl %x no matching tokens: %s", + handle, iommu_cb_set.cb_info[idx].name[0]); + } + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); +} + +void cam_smmu_unset_client_page_fault_handler(int handle, void *token) +{ + int idx, i = 0; + + if (!token || (handle == HANDLE_INIT)) { + CAM_ERR(CAM_SMMU, "Error: token is NULL or invalid handle"); + return; + } + + idx = GET_SMMU_TABLE_IDX(handle); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, handle); + return; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, handle); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return; + } + + for (i = 0; i < CAM_SMMU_CB_MAX; i++) { + if (iommu_cb_set.cb_info[idx].token[i] == token) { + iommu_cb_set.cb_info[idx].token[i] = NULL; + iommu_cb_set.cb_info[idx].handler[i] = + NULL; + iommu_cb_set.cb_info[idx].cb_count--; + break; + } + } + if (i == CAM_SMMU_CB_MAX) + CAM_ERR(CAM_SMMU, "Error: hdl %x no matching tokens: %s", + handle, iommu_cb_set.cb_info[idx].name[0]); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); +} + +static int cam_smmu_iommu_fault_handler(struct iommu_domain *domain, + struct device *dev, unsigned long iova, + int flags, void *token) +{ + char *cb_name; + int idx; + struct cam_smmu_work_payload *payload; + + if (!token) { + CAM_ERR(CAM_SMMU, "Error: token is NULL"); + CAM_ERR(CAM_SMMU, "Error: domain = %pK, device = %pK", + domain, dev); + CAM_ERR(CAM_SMMU, "iova = %lX, flags = %d", iova, flags); + return -EINVAL; + } + + cb_name = (char *)token; + /* Check whether it is in the table */ + for (idx = 0; idx < iommu_cb_set.cb_num; idx++) { + if (!strcmp(iommu_cb_set.cb_info[idx].name[0], cb_name)) + break; + } + + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: index is not valid, index = %d, token = %s", + idx, cb_name); + return -EINVAL; + } + + if (++iommu_cb_set.cb_info[idx].pf_count > g_num_pf_handled) { + CAM_INFO_RATE_LIMIT(CAM_SMMU, "PF already handled %d %d %d", + g_num_pf_handled, idx, + iommu_cb_set.cb_info[idx].pf_count); + return -EINVAL; + } + + payload = kzalloc(sizeof(struct cam_smmu_work_payload), GFP_ATOMIC); + if (!payload) + return -EINVAL; + + payload->domain = domain; + payload->dev = dev; + payload->iova = iova; + payload->flags = flags; + payload->token = token; + payload->idx = idx; + + mutex_lock(&iommu_cb_set.payload_list_lock); + list_add_tail(&payload->list, &iommu_cb_set.payload_list); + mutex_unlock(&iommu_cb_set.payload_list_lock); + + cam_smmu_page_fault_work(&iommu_cb_set.smmu_work); + + return -EINVAL; +} + +static int cam_smmu_translate_dir_to_iommu_dir( + enum cam_smmu_map_dir dir) +{ + switch (dir) { + case CAM_SMMU_MAP_READ: + return IOMMU_READ; + case CAM_SMMU_MAP_WRITE: + return IOMMU_WRITE; + case CAM_SMMU_MAP_RW: + return IOMMU_READ|IOMMU_WRITE; + case CAM_SMMU_MAP_INVALID: + default: + CAM_ERR(CAM_SMMU, "Error: Direction is invalid. dir = %d", dir); + break; + }; + return IOMMU_INVALID_DIR; +} + +static enum dma_data_direction cam_smmu_translate_dir( + enum cam_smmu_map_dir dir) +{ + switch (dir) { + case CAM_SMMU_MAP_READ: + return DMA_FROM_DEVICE; + case CAM_SMMU_MAP_WRITE: + return DMA_TO_DEVICE; + case CAM_SMMU_MAP_RW: + return DMA_BIDIRECTIONAL; + case CAM_SMMU_MAP_INVALID: + default: + CAM_ERR(CAM_SMMU, "Error: Direction is invalid. dir = %d", + (int)dir); + break; + } + return DMA_NONE; +} + +void cam_smmu_reset_iommu_table(enum cam_smmu_init_dir ops) +{ + unsigned int i; + int j = 0; + + for (i = 0; i < iommu_cb_set.cb_num; i++) { + iommu_cb_set.cb_info[i].handle = HANDLE_INIT; + INIT_LIST_HEAD(&iommu_cb_set.cb_info[i].smmu_buf_list); + INIT_LIST_HEAD(&iommu_cb_set.cb_info[i].smmu_buf_kernel_list); + iommu_cb_set.cb_info[i].state = CAM_SMMU_DETACH; + iommu_cb_set.cb_info[i].dev = NULL; + iommu_cb_set.cb_info[i].cb_count = 0; + iommu_cb_set.cb_info[i].pf_count = 0; + for (j = 0; j < CAM_SMMU_CB_MAX; j++) { + iommu_cb_set.cb_info[i].token[j] = NULL; + iommu_cb_set.cb_info[i].handler[j] = NULL; + } + if (ops == CAM_SMMU_TABLE_INIT) + mutex_init(&iommu_cb_set.cb_info[i].lock); + else + mutex_destroy(&iommu_cb_set.cb_info[i].lock); + } +} + +static int cam_smmu_check_handle_unique(int hdl) +{ + int i; + + if (hdl == HANDLE_INIT) { + CAM_DBG(CAM_SMMU, + "iommu handle is init number. Need to try again"); + return 1; + } + + for (i = 0; i < iommu_cb_set.cb_num; i++) { + if (iommu_cb_set.cb_info[i].handle == HANDLE_INIT) + continue; + + if (iommu_cb_set.cb_info[i].handle == hdl) { + CAM_DBG(CAM_SMMU, "iommu handle %d conflicts", + (int)hdl); + return 1; + } + } + return 0; +} + +/** + * use low 2 bytes for handle cookie + */ +static int cam_smmu_create_iommu_handle(int idx) +{ + int rand, hdl = 0; + + get_random_bytes(&rand, COOKIE_NUM_BYTE); + hdl = GET_SMMU_HDL(idx, rand); + CAM_DBG(CAM_SMMU, "create handle value = %x", (int)hdl); + return hdl; +} + +static int cam_smmu_attach_device(int idx) +{ + int rc; + struct cam_context_bank_info *cb = &iommu_cb_set.cb_info[idx]; + + /* attach the mapping to device */ + rc = iommu_attach_device(cb->domain, cb->dev); + if (rc < 0) { + CAM_ERR(CAM_SMMU, "Error: ARM IOMMU attach failed. ret = %d", + rc); + rc = -ENODEV; + } + + return rc; +} + +static int cam_smmu_create_add_handle_in_table(char *name, + int *hdl) +{ + int i, j; + int handle; + bool valid = false; + + /* create handle and add in the iommu hardware table */ + for (i = 0; i < iommu_cb_set.cb_num; i++) { + for (j = 0; j < iommu_cb_set.cb_info[i].num_shared_hdl; j++) { + if (!strcmp(iommu_cb_set.cb_info[i].name[j], name)) + valid = true; + + if (iommu_cb_set.cb_info[i].handle != HANDLE_INIT && + valid) { + mutex_lock(&iommu_cb_set.cb_info[i].lock); + if (iommu_cb_set.cb_info[i].is_secure) { + iommu_cb_set.cb_info[i].secure_count++; + *hdl = iommu_cb_set.cb_info[i].handle; + mutex_unlock( + &iommu_cb_set.cb_info[i].lock); + return 0; + } + + if (iommu_cb_set.cb_info[i].is_mul_client) { + iommu_cb_set.cb_info[i].device_count++; + *hdl = iommu_cb_set.cb_info[i].handle; + mutex_unlock( + &iommu_cb_set.cb_info[i].lock); + CAM_INFO(CAM_SMMU, + "%s already got handle 0x%x", + name, + iommu_cb_set.cb_info[i].handle); + return 0; + } + + CAM_ERR(CAM_SMMU, + "Error: %s already got handle 0x%x", + name, iommu_cb_set.cb_info[i].handle); + mutex_unlock(&iommu_cb_set.cb_info[i].lock); + return -EALREADY; + } + + if (iommu_cb_set.cb_info[i].handle == HANDLE_INIT && + valid) { + mutex_lock(&iommu_cb_set.cb_info[i].lock); + /* make sure handle is unique */ + do { + handle = + cam_smmu_create_iommu_handle(i); + } while (cam_smmu_check_handle_unique(handle)); + + /* put handle in the table */ + iommu_cb_set.cb_info[i].handle = handle; + iommu_cb_set.cb_info[i].cb_count = 0; + if (iommu_cb_set.cb_info[i].is_secure) + iommu_cb_set.cb_info[i].secure_count++; + + if (iommu_cb_set.cb_info[i].is_mul_client) + iommu_cb_set.cb_info[i].device_count++; + + *hdl = handle; + CAM_DBG(CAM_SMMU, "%s creates handle 0x%x", + name, handle); + mutex_unlock(&iommu_cb_set.cb_info[i].lock); + return 0; + } + } + } + + CAM_ERR(CAM_SMMU, "Error: Cannot find name %s or all handle exist", + name); + cam_smmu_print_table(); + return -EINVAL; +} + +static int cam_smmu_init_scratch_map(struct scratch_mapping *scratch_map, + dma_addr_t base, size_t size, + int order) +{ + unsigned int count = size >> (PAGE_SHIFT + order); + unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long); + int err = 0; + + if (!count) { + err = -EINVAL; + CAM_ERR(CAM_SMMU, "Page count is zero, size passed = %zu", + size); + goto bail; + } + + scratch_map->bitmap = kzalloc(bitmap_size, GFP_KERNEL); + if (!scratch_map->bitmap) { + err = -ENOMEM; + goto bail; + } + + scratch_map->base = base; + scratch_map->bits = BITS_PER_BYTE * bitmap_size; + scratch_map->order = order; + +bail: + return err; +} + +static int cam_smmu_alloc_scratch_va(struct scratch_mapping *mapping, + size_t size, + dma_addr_t *iova) +{ + unsigned int order = get_order(size); + unsigned int align = 0; + unsigned int count, start; + + count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) + + (1 << mapping->order) - 1) >> mapping->order; + + /* + * Transparently, add a guard page to the total count of pages + * to be allocated + */ + count++; + + if (order > mapping->order) + align = (1 << (order - mapping->order)) - 1; + + start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0, + count, align); + + if (start > mapping->bits) + return -ENOMEM; + + bitmap_set(mapping->bitmap, start, count); + *iova = mapping->base + (start << (mapping->order + PAGE_SHIFT)); + + return 0; +} + +static int cam_smmu_free_scratch_va(struct scratch_mapping *mapping, + dma_addr_t addr, size_t size) +{ + unsigned int start = (addr - mapping->base) >> + (mapping->order + PAGE_SHIFT); + unsigned int count = ((size >> PAGE_SHIFT) + + (1 << mapping->order) - 1) >> mapping->order; + + if (!addr) { + CAM_ERR(CAM_SMMU, "Error: Invalid address"); + return -EINVAL; + } + + if (start + count > mapping->bits) { + CAM_ERR(CAM_SMMU, "Error: Invalid page bits in scratch map"); + return -EINVAL; + } + + /* + * Transparently, add a guard page to the total count of pages + * to be freed + */ + count++; + bitmap_clear(mapping->bitmap, start, count); + + return 0; +} + +static struct cam_dma_buff_info *cam_smmu_find_mapping_by_virt_address(int idx, + dma_addr_t virt_addr) +{ + struct cam_dma_buff_info *mapping; + + list_for_each_entry(mapping, &iommu_cb_set.cb_info[idx].smmu_buf_list, + list) { + if (mapping->paddr == virt_addr) { + CAM_DBG(CAM_SMMU, "Found virtual address %lx", + (unsigned long)virt_addr); + return mapping; + } + } + + CAM_ERR(CAM_SMMU, "Error: Cannot find virtual address %lx by index %d", + (unsigned long)virt_addr, idx); + return NULL; +} + +static struct cam_dma_buff_info *cam_smmu_find_mapping_by_ion_index(int idx, + int ion_fd) +{ + struct cam_dma_buff_info *mapping; + + if (ion_fd < 0) { + CAM_ERR(CAM_SMMU, "Invalid fd %d", ion_fd); + return NULL; + } + + list_for_each_entry(mapping, + &iommu_cb_set.cb_info[idx].smmu_buf_list, + list) { + if (mapping->ion_fd == ion_fd) { + CAM_DBG(CAM_SMMU, "find ion_fd %d", ion_fd); + return mapping; + } + } + + CAM_ERR(CAM_SMMU, "Error: Cannot find entry by index %d", idx); + + return NULL; +} + +static struct cam_dma_buff_info *cam_smmu_find_mapping_by_dma_buf(int idx, + struct dma_buf *buf) +{ + struct cam_dma_buff_info *mapping; + + if (!buf) { + CAM_ERR(CAM_SMMU, "Invalid dma_buf"); + return NULL; + } + + list_for_each_entry(mapping, + &iommu_cb_set.cb_info[idx].smmu_buf_kernel_list, + list) { + if (mapping->buf == buf) { + CAM_DBG(CAM_SMMU, "find dma_buf %pK", buf); + return mapping; + } + } + + CAM_ERR(CAM_SMMU, "Error: Cannot find entry by index %d", idx); + + return NULL; +} + +static struct cam_sec_buff_info *cam_smmu_find_mapping_by_sec_buf_idx(int idx, + int ion_fd) +{ + struct cam_sec_buff_info *mapping; + + list_for_each_entry(mapping, &iommu_cb_set.cb_info[idx].smmu_buf_list, + list) { + if (mapping->ion_fd == ion_fd) { + CAM_DBG(CAM_SMMU, "find ion_fd %d", ion_fd); + return mapping; + } + } + CAM_ERR(CAM_SMMU, "Error: Cannot find fd %d by index %d", + ion_fd, idx); + return NULL; +} + +static void cam_smmu_clean_user_buffer_list(int idx) +{ + int ret; + struct cam_dma_buff_info *mapping_info, *temp; + + list_for_each_entry_safe(mapping_info, temp, + &iommu_cb_set.cb_info[idx].smmu_buf_list, list) { + CAM_DBG(CAM_SMMU, "Free mapping address %pK, i = %d, fd = %d", + (void *)mapping_info->paddr, idx, + mapping_info->ion_fd); + + if (mapping_info->ion_fd == 0xDEADBEEF) + /* Clean up scratch buffers */ + ret = cam_smmu_free_scratch_buffer_remove_from_list( + mapping_info, idx); + else + /* Clean up regular mapped buffers */ + ret = cam_smmu_unmap_buf_and_remove_from_list( + mapping_info, + idx); + + if (ret < 0) { + CAM_ERR(CAM_SMMU, "Buffer delete failed: idx = %d", + idx); + CAM_ERR(CAM_SMMU, + "Buffer delete failed: addr = %lx, fd = %d", + (unsigned long)mapping_info->paddr, + mapping_info->ion_fd); + /* + * Ignore this error and continue to delete other + * buffers in the list + */ + continue; + } + } +} + +static void cam_smmu_clean_kernel_buffer_list(int idx) +{ + int ret; + struct cam_dma_buff_info *mapping_info, *temp; + + list_for_each_entry_safe(mapping_info, temp, + &iommu_cb_set.cb_info[idx].smmu_buf_kernel_list, list) { + CAM_DBG(CAM_SMMU, + "Free mapping address %pK, i = %d, dma_buf = %pK", + (void *)mapping_info->paddr, idx, + mapping_info->buf); + + /* Clean up regular mapped buffers */ + ret = cam_smmu_unmap_buf_and_remove_from_list( + mapping_info, + idx); + + if (ret < 0) { + CAM_ERR(CAM_SMMU, + "Buffer delete in kernel list failed: idx = %d", + idx); + CAM_ERR(CAM_SMMU, + "Buffer delete failed: addr = %lx, dma_buf = %pK", + (unsigned long)mapping_info->paddr, + mapping_info->buf); + /* + * Ignore this error and continue to delete other + * buffers in the list + */ + continue; + } + } +} + +static int cam_smmu_attach(int idx) +{ + int ret; + + if (iommu_cb_set.cb_info[idx].state == CAM_SMMU_ATTACH) { + ret = -EALREADY; + } else if (iommu_cb_set.cb_info[idx].state == CAM_SMMU_DETACH) { + ret = cam_smmu_attach_device(idx); + if (ret < 0) { + CAM_ERR(CAM_SMMU, "Error: ATTACH fail"); + return -ENODEV; + } + iommu_cb_set.cb_info[idx].state = CAM_SMMU_ATTACH; + ret = 0; + } else { + CAM_ERR(CAM_SMMU, "Error: Not detach/attach: %d", + iommu_cb_set.cb_info[idx].state); + ret = -EINVAL; + } + + return ret; +} + +static int cam_smmu_detach_device(int idx) +{ + int rc = 0; + struct cam_context_bank_info *cb = &iommu_cb_set.cb_info[idx]; + + /* detach the mapping to device if not already detached */ + if (iommu_cb_set.cb_info[idx].state == CAM_SMMU_DETACH) { + rc = -EALREADY; + } else if (iommu_cb_set.cb_info[idx].state == CAM_SMMU_ATTACH) { + iommu_detach_device(cb->domain, cb->dev); + iommu_cb_set.cb_info[idx].state = CAM_SMMU_DETACH; + } + + return rc; +} + +static int cam_smmu_alloc_iova(size_t size, + int32_t smmu_hdl, uint32_t *iova) +{ + int rc = 0; + int idx; + uint32_t vaddr = 0; + + if (!iova || !size || (smmu_hdl == HANDLE_INIT)) { + CAM_ERR(CAM_SMMU, "Error: Input args are invalid"); + return -EINVAL; + } + + CAM_DBG(CAM_SMMU, "Allocating iova size = %zu for smmu hdl=%X", + size, smmu_hdl); + + idx = GET_SMMU_TABLE_IDX(smmu_hdl); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, smmu_hdl); + return -EINVAL; + } + + if (iommu_cb_set.cb_info[idx].handle != smmu_hdl) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, smmu_hdl); + rc = -EINVAL; + goto get_addr_end; + } + + if (!iommu_cb_set.cb_info[idx].shared_support) { + CAM_ERR(CAM_SMMU, + "Error: Shared memory not supported for hdl = %X", + smmu_hdl); + rc = -EINVAL; + goto get_addr_end; + } + + vaddr = gen_pool_alloc(iommu_cb_set.cb_info[idx].shared_mem_pool, size); + if (!vaddr) + return -ENOMEM; + + *iova = vaddr; + +get_addr_end: + return rc; +} + +static int cam_smmu_free_iova(uint32_t addr, size_t size, + int32_t smmu_hdl) +{ + int rc = 0; + int idx; + + if (!size || (smmu_hdl == HANDLE_INIT)) { + CAM_ERR(CAM_SMMU, "Error: Input args are invalid"); + return -EINVAL; + } + + idx = GET_SMMU_TABLE_IDX(smmu_hdl); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, smmu_hdl); + return -EINVAL; + } + + if (iommu_cb_set.cb_info[idx].handle != smmu_hdl) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, smmu_hdl); + rc = -EINVAL; + goto get_addr_end; + } + + gen_pool_free(iommu_cb_set.cb_info[idx].shared_mem_pool, addr, size); + +get_addr_end: + return rc; +} + +int cam_smmu_alloc_firmware(int32_t smmu_hdl, + dma_addr_t *iova, + uintptr_t *cpuva, + size_t *len) +{ + int rc; + int32_t idx; + size_t firmware_len = 0; + size_t firmware_start = 0; + struct iommu_domain *domain; + + if (!iova || !len || !cpuva || (smmu_hdl == HANDLE_INIT)) { + CAM_ERR(CAM_SMMU, "Error: Input args are invalid"); + return -EINVAL; + } + + idx = GET_SMMU_TABLE_IDX(smmu_hdl); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, smmu_hdl); + rc = -EINVAL; + goto end; + } + + if (!iommu_cb_set.cb_info[idx].firmware_support) { + CAM_ERR(CAM_SMMU, + "Firmware memory not supported for this SMMU handle"); + rc = -EINVAL; + goto end; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].is_fw_allocated) { + CAM_ERR(CAM_SMMU, "Trying to allocate twice"); + rc = -ENOMEM; + goto unlock_and_end; + } + + firmware_len = iommu_cb_set.cb_info[idx].firmware_info.iova_len; + firmware_start = iommu_cb_set.cb_info[idx].firmware_info.iova_start; + CAM_DBG(CAM_SMMU, "Firmware area len from DT = %zu", firmware_len); + + icp_fw.fw_kva = dma_alloc_coherent(icp_fw.fw_dev, + firmware_len, + &icp_fw.fw_dma_hdl, + GFP_KERNEL); + if (!icp_fw.fw_kva) { + CAM_ERR(CAM_SMMU, "FW memory alloc failed"); + rc = -ENOMEM; + goto unlock_and_end; + } else { + CAM_DBG(CAM_SMMU, "DMA alloc returned fw = %pK, hdl = %pK", + icp_fw.fw_kva, (void *)icp_fw.fw_dma_hdl); + } + + domain = iommu_cb_set.cb_info[idx].domain; + rc = iommu_map(domain, + firmware_start, + icp_fw.fw_dma_hdl, + firmware_len, + IOMMU_READ|IOMMU_WRITE|IOMMU_PRIV); + + if (rc) { + CAM_ERR(CAM_SMMU, "Failed to map FW into IOMMU"); + rc = -ENOMEM; + goto alloc_fail; + } + iommu_cb_set.cb_info[idx].is_fw_allocated = true; + + *iova = iommu_cb_set.cb_info[idx].firmware_info.iova_start; + *cpuva = (uintptr_t)icp_fw.fw_kva; + *len = firmware_len; + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + + return rc; + +alloc_fail: + dma_free_coherent(icp_fw.fw_dev, + firmware_len, + icp_fw.fw_kva, + icp_fw.fw_dma_hdl); +unlock_and_end: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); +end: + return rc; +} +EXPORT_SYMBOL(cam_smmu_alloc_firmware); + +int cam_smmu_dealloc_firmware(int32_t smmu_hdl) +{ + int rc = 0; + int32_t idx; + size_t firmware_len = 0; + size_t firmware_start = 0; + struct iommu_domain *domain; + size_t unmapped = 0; + + if (smmu_hdl == HANDLE_INIT) { + CAM_ERR(CAM_SMMU, "Error: Invalid handle"); + return -EINVAL; + } + + idx = GET_SMMU_TABLE_IDX(smmu_hdl); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, smmu_hdl); + rc = -EINVAL; + goto end; + } + + if (!iommu_cb_set.cb_info[idx].firmware_support) { + CAM_ERR(CAM_SMMU, + "Firmware memory not supported for this SMMU handle"); + rc = -EINVAL; + goto end; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (!iommu_cb_set.cb_info[idx].is_fw_allocated) { + CAM_ERR(CAM_SMMU, + "Trying to deallocate firmware that is not allocated"); + rc = -ENOMEM; + goto unlock_and_end; + } + + firmware_len = iommu_cb_set.cb_info[idx].firmware_info.iova_len; + firmware_start = iommu_cb_set.cb_info[idx].firmware_info.iova_start; + domain = iommu_cb_set.cb_info[idx].domain; + unmapped = iommu_unmap(domain, + firmware_start, + firmware_len); + + if (unmapped != firmware_len) { + CAM_ERR(CAM_SMMU, "Only %zu unmapped out of total %zu", + unmapped, + firmware_len); + rc = -EINVAL; + } + + dma_free_coherent(icp_fw.fw_dev, + firmware_len, + icp_fw.fw_kva, + icp_fw.fw_dma_hdl); + + icp_fw.fw_kva = 0; + icp_fw.fw_dma_hdl = 0; + + iommu_cb_set.cb_info[idx].is_fw_allocated = false; + +unlock_and_end: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); +end: + return rc; +} +EXPORT_SYMBOL(cam_smmu_dealloc_firmware); + +int cam_smmu_alloc_qdss(int32_t smmu_hdl, + dma_addr_t *iova, + size_t *len) +{ + int rc; + int32_t idx; + size_t qdss_len = 0; + size_t qdss_start = 0; + dma_addr_t qdss_phy_addr; + struct iommu_domain *domain; + + if (!iova || !len || (smmu_hdl == HANDLE_INIT)) { + CAM_ERR(CAM_SMMU, "Error: Input args are invalid"); + return -EINVAL; + } + + idx = GET_SMMU_TABLE_IDX(smmu_hdl); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, smmu_hdl); + rc = -EINVAL; + goto end; + } + + if (!iommu_cb_set.cb_info[idx].qdss_support) { + CAM_ERR(CAM_SMMU, + "QDSS memory not supported for this SMMU handle"); + rc = -EINVAL; + goto end; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].is_qdss_allocated) { + CAM_ERR(CAM_SMMU, "Trying to allocate twice"); + rc = -ENOMEM; + goto unlock_and_end; + } + + qdss_len = iommu_cb_set.cb_info[idx].qdss_info.iova_len; + qdss_start = iommu_cb_set.cb_info[idx].qdss_info.iova_start; + qdss_phy_addr = iommu_cb_set.cb_info[idx].qdss_phy_addr; + CAM_DBG(CAM_SMMU, "QDSS area len from DT = %zu", qdss_len); + + domain = iommu_cb_set.cb_info[idx].domain; + rc = iommu_map(domain, + qdss_start, + qdss_phy_addr, + qdss_len, + IOMMU_READ|IOMMU_WRITE); + + if (rc) { + CAM_ERR(CAM_SMMU, "Failed to map QDSS into IOMMU"); + goto unlock_and_end; + } + + iommu_cb_set.cb_info[idx].is_qdss_allocated = true; + + *iova = iommu_cb_set.cb_info[idx].qdss_info.iova_start; + *len = qdss_len; + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + + return rc; + +unlock_and_end: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); +end: + return rc; +} +EXPORT_SYMBOL(cam_smmu_alloc_qdss); + +int cam_smmu_dealloc_qdss(int32_t smmu_hdl) +{ + int rc = 0; + int32_t idx; + size_t qdss_len = 0; + size_t qdss_start = 0; + struct iommu_domain *domain; + size_t unmapped = 0; + + if (smmu_hdl == HANDLE_INIT) { + CAM_ERR(CAM_SMMU, "Error: Invalid handle"); + return -EINVAL; + } + + idx = GET_SMMU_TABLE_IDX(smmu_hdl); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, smmu_hdl); + rc = -EINVAL; + goto end; + } + + if (!iommu_cb_set.cb_info[idx].qdss_support) { + CAM_ERR(CAM_SMMU, + "QDSS memory not supported for this SMMU handle"); + rc = -EINVAL; + goto end; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (!iommu_cb_set.cb_info[idx].is_qdss_allocated) { + CAM_ERR(CAM_SMMU, + "Trying to deallocate qdss that is not allocated"); + rc = -ENOMEM; + goto unlock_and_end; + } + + qdss_len = iommu_cb_set.cb_info[idx].qdss_info.iova_len; + qdss_start = iommu_cb_set.cb_info[idx].qdss_info.iova_start; + domain = iommu_cb_set.cb_info[idx].domain; + unmapped = iommu_unmap(domain, qdss_start, qdss_len); + + if (unmapped != qdss_len) { + CAM_ERR(CAM_SMMU, "Only %zu unmapped out of total %zu", + unmapped, + qdss_len); + rc = -EINVAL; + } + + iommu_cb_set.cb_info[idx].is_qdss_allocated = false; + +unlock_and_end: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); +end: + return rc; +} +EXPORT_SYMBOL(cam_smmu_dealloc_qdss); + +int cam_smmu_get_io_region_info(int32_t smmu_hdl, + dma_addr_t *iova, size_t *len, + dma_addr_t *discard_iova_start, size_t *discard_iova_len) +{ + int32_t idx; + + if (!iova || !len || !discard_iova_start || !discard_iova_len || + (smmu_hdl == HANDLE_INIT)) { + CAM_ERR(CAM_SMMU, "Error: Input args are invalid"); + return -EINVAL; + } + + idx = GET_SMMU_TABLE_IDX(smmu_hdl); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, smmu_hdl); + return -EINVAL; + } + + if (!iommu_cb_set.cb_info[idx].io_support) { + CAM_ERR(CAM_SMMU, + "I/O memory not supported for this SMMU handle"); + return -EINVAL; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + *iova = iommu_cb_set.cb_info[idx].io_info.iova_start; + *len = iommu_cb_set.cb_info[idx].io_info.iova_len; + *discard_iova_start = + iommu_cb_set.cb_info[idx].io_info.discard_iova_start; + *discard_iova_len = + iommu_cb_set.cb_info[idx].io_info.discard_iova_len; + + CAM_DBG(CAM_SMMU, + "I/O area for hdl = %x Region:[%pK %zu] Discard:[%pK %zu]", + smmu_hdl, *iova, *len, + *discard_iova_start, *discard_iova_len); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + + return 0; +} + +int cam_smmu_get_region_info(int32_t smmu_hdl, + enum cam_smmu_region_id region_id, + struct cam_smmu_region_info *region_info) +{ + int32_t idx; + struct cam_context_bank_info *cb = NULL; + + if (!region_info) { + CAM_ERR(CAM_SMMU, "Invalid region_info pointer"); + return -EINVAL; + } + + if (smmu_hdl == HANDLE_INIT) { + CAM_ERR(CAM_SMMU, "Invalid handle"); + return -EINVAL; + } + + idx = GET_SMMU_TABLE_IDX(smmu_hdl); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, "Handle or index invalid. idx = %d hdl = %x", + idx, smmu_hdl); + return -EINVAL; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + cb = &iommu_cb_set.cb_info[idx]; + if (!cb) { + CAM_ERR(CAM_SMMU, "SMMU context bank pointer invalid"); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return -EINVAL; + } + + switch (region_id) { + case CAM_SMMU_REGION_FIRMWARE: + if (!cb->firmware_support) { + CAM_ERR(CAM_SMMU, "Firmware not supported"); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return -ENODEV; + } + region_info->iova_start = cb->firmware_info.iova_start; + region_info->iova_len = cb->firmware_info.iova_len; + break; + case CAM_SMMU_REGION_SHARED: + if (!cb->shared_support) { + CAM_ERR(CAM_SMMU, "Shared mem not supported"); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return -ENODEV; + } + region_info->iova_start = cb->shared_info.iova_start; + region_info->iova_len = cb->shared_info.iova_len; + break; + case CAM_SMMU_REGION_SCRATCH: + if (!cb->scratch_buf_support) { + CAM_ERR(CAM_SMMU, "Scratch memory not supported"); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return -ENODEV; + } + region_info->iova_start = cb->scratch_info.iova_start; + region_info->iova_len = cb->scratch_info.iova_len; + break; + case CAM_SMMU_REGION_IO: + if (!cb->io_support) { + CAM_ERR(CAM_SMMU, "IO memory not supported"); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return -ENODEV; + } + region_info->iova_start = cb->io_info.iova_start; + region_info->iova_len = cb->io_info.iova_len; + break; + case CAM_SMMU_REGION_SECHEAP: + if (!cb->secheap_support) { + CAM_ERR(CAM_SMMU, "Secondary heap not supported"); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return -ENODEV; + } + region_info->iova_start = cb->secheap_info.iova_start; + region_info->iova_len = cb->secheap_info.iova_len; + break; + default: + CAM_ERR(CAM_SMMU, "Invalid region id: %d for smmu hdl: %X", + smmu_hdl, region_id); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return -EINVAL; + } + + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return 0; +} +EXPORT_SYMBOL(cam_smmu_get_region_info); + +int cam_smmu_reserve_sec_heap(int32_t smmu_hdl, + struct dma_buf *buf, + dma_addr_t *iova, + size_t *request_len) +{ + struct secheap_buf_info *secheap_buf = NULL; + size_t size = 0; + uint32_t sec_heap_iova = 0; + size_t sec_heap_iova_len = 0; + int idx; + int rc = 0; + + idx = GET_SMMU_TABLE_IDX(smmu_hdl); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, smmu_hdl); + return -EINVAL; + } + + if (!iommu_cb_set.cb_info[idx].secheap_support) { + CAM_ERR(CAM_SMMU, "Secondary heap not supported"); + return -EINVAL; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + + if (iommu_cb_set.cb_info[idx].is_secheap_allocated) { + CAM_ERR(CAM_SMMU, "Trying to allocate secheap twice"); + rc = -ENOMEM; + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return rc; + } + + if (IS_ERR_OR_NULL(buf)) { + rc = PTR_ERR(buf); + CAM_ERR(CAM_SMMU, + "Error: dma get buf failed. rc = %d", rc); + goto err_out; + } + + secheap_buf = &iommu_cb_set.cb_info[idx].secheap_buf; + secheap_buf->buf = buf; + secheap_buf->attach = dma_buf_attach(secheap_buf->buf, + iommu_cb_set.cb_info[idx].dev); + if (IS_ERR_OR_NULL(secheap_buf->attach)) { + rc = PTR_ERR(secheap_buf->attach); + CAM_ERR(CAM_SMMU, "Error: dma buf attach failed"); + goto err_put; + } + + secheap_buf->table = dma_buf_map_attachment(secheap_buf->attach, + DMA_BIDIRECTIONAL); + if (IS_ERR_OR_NULL(secheap_buf->table)) { + rc = PTR_ERR(secheap_buf->table); + CAM_ERR(CAM_SMMU, "Error: dma buf map attachment failed"); + goto err_detach; + } + + sec_heap_iova = iommu_cb_set.cb_info[idx].secheap_info.iova_start; + sec_heap_iova_len = iommu_cb_set.cb_info[idx].secheap_info.iova_len; + size = iommu_map_sg(iommu_cb_set.cb_info[idx].domain, + sec_heap_iova, + secheap_buf->table->sgl, + secheap_buf->table->nents, + IOMMU_READ | IOMMU_WRITE); + if (size != sec_heap_iova_len) { + CAM_ERR(CAM_SMMU, "IOMMU mapping failed"); + goto err_unmap_sg; + } + + iommu_cb_set.cb_info[idx].is_secheap_allocated = true; + *iova = (uint32_t)sec_heap_iova; + *request_len = sec_heap_iova_len; + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + + return rc; + +err_unmap_sg: + dma_buf_unmap_attachment(secheap_buf->attach, + secheap_buf->table, + DMA_BIDIRECTIONAL); +err_detach: + dma_buf_detach(secheap_buf->buf, + secheap_buf->attach); +err_put: + dma_buf_put(secheap_buf->buf); +err_out: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return rc; +} +EXPORT_SYMBOL(cam_smmu_reserve_sec_heap); + +int cam_smmu_release_sec_heap(int32_t smmu_hdl) +{ + int idx; + size_t size = 0; + uint32_t sec_heap_iova = 0; + size_t sec_heap_iova_len = 0; + struct secheap_buf_info *secheap_buf = NULL; + + idx = GET_SMMU_TABLE_IDX(smmu_hdl); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, smmu_hdl); + return -EINVAL; + } + + if (!iommu_cb_set.cb_info[idx].secheap_support) { + CAM_ERR(CAM_SMMU, "Secondary heap not supported"); + return -EINVAL; + } + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + + if (!iommu_cb_set.cb_info[idx].is_secheap_allocated) { + CAM_ERR(CAM_SMMU, "Trying to release secheap twice"); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return -ENOMEM; + } + + secheap_buf = &iommu_cb_set.cb_info[idx].secheap_buf; + sec_heap_iova = iommu_cb_set.cb_info[idx].secheap_info.iova_start; + sec_heap_iova_len = iommu_cb_set.cb_info[idx].secheap_info.iova_len; + + size = iommu_unmap(iommu_cb_set.cb_info[idx].domain, + sec_heap_iova, + sec_heap_iova_len); + if (size != sec_heap_iova_len) { + CAM_ERR(CAM_SMMU, "Failed: Unmapped = %zu, requested = %zu", + size, + sec_heap_iova_len); + } + + dma_buf_unmap_attachment(secheap_buf->attach, + secheap_buf->table, DMA_BIDIRECTIONAL); + dma_buf_detach(secheap_buf->buf, secheap_buf->attach); + dma_buf_put(secheap_buf->buf); + iommu_cb_set.cb_info[idx].is_secheap_allocated = false; + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + + return 0; +} +EXPORT_SYMBOL(cam_smmu_release_sec_heap); + +static int cam_smmu_map_buffer_validate(struct dma_buf *buf, + int idx, enum dma_data_direction dma_dir, dma_addr_t *paddr_ptr, + size_t *len_ptr, enum cam_smmu_region_id region_id, + bool dis_delayed_unmap, struct cam_dma_buff_info **mapping_info) +{ + struct dma_buf_attachment *attach = NULL; + struct sg_table *table = NULL; + struct iommu_domain *domain; + size_t size = 0; + uint32_t iova = 0; + int rc = 0; + struct timespec64 ts1, ts2; + long microsec = 0; + + if (IS_ERR_OR_NULL(buf)) { + rc = PTR_ERR(buf); + CAM_ERR(CAM_SMMU, + "Error: dma get buf failed. rc = %d", rc); + goto err_out; + } + + if (!mapping_info) { + rc = -EINVAL; + CAM_ERR(CAM_SMMU, "Error: mapping_info is invalid"); + goto err_out; + } + + if (iommu_cb_set.map_profile_enable) + CAM_GET_TIMESTAMP(ts1); + + attach = dma_buf_attach(buf, iommu_cb_set.cb_info[idx].dev); + if (IS_ERR_OR_NULL(attach)) { + rc = PTR_ERR(attach); + CAM_ERR(CAM_SMMU, "Error: dma buf attach failed"); + goto err_put; + } + + if (region_id == CAM_SMMU_REGION_SHARED) { + table = dma_buf_map_attachment(attach, dma_dir); + if (IS_ERR_OR_NULL(table)) { + rc = PTR_ERR(table); + CAM_ERR(CAM_SMMU, "Error: dma map attachment failed"); + goto err_detach; + } + + domain = iommu_cb_set.cb_info[idx].domain; + if (!domain) { + CAM_ERR(CAM_SMMU, "CB has no domain set"); + goto err_unmap_sg; + } + + rc = cam_smmu_alloc_iova(*len_ptr, + iommu_cb_set.cb_info[idx].handle, + &iova); + + if (rc < 0) { + CAM_ERR(CAM_SMMU, + "IOVA alloc failed for shared memory, size=%zu, idx=%d, handle=%d", + *len_ptr, idx, + iommu_cb_set.cb_info[idx].handle); + goto err_unmap_sg; + } + + size = iommu_map_sg(domain, iova, table->sgl, table->nents, + IOMMU_READ | IOMMU_WRITE); + + if (size < 0) { + CAM_ERR(CAM_SMMU, "IOMMU mapping failed"); + rc = cam_smmu_free_iova(iova, + size, iommu_cb_set.cb_info[idx].handle); + if (rc) + CAM_ERR(CAM_SMMU, "IOVA free failed"); + rc = -ENOMEM; + goto err_unmap_sg; + } else { + CAM_DBG(CAM_SMMU, + "iommu_map_sg returned iova=%pK, size=%zu", + iova, size); + *paddr_ptr = iova; + *len_ptr = size; + } + iommu_cb_set.cb_info[idx].shared_mapping_size += *len_ptr; + } else if (region_id == CAM_SMMU_REGION_IO) { + if (!dis_delayed_unmap) + attach->dma_map_attrs |= DMA_ATTR_DELAYED_UNMAP; + + table = dma_buf_map_attachment(attach, dma_dir); + if (IS_ERR_OR_NULL(table)) { + rc = PTR_ERR(table); + CAM_ERR(CAM_SMMU, + "Error: dma map attachment failed, size=%zu", + buf->size); + goto err_detach; + } + + *paddr_ptr = sg_dma_address(table->sgl); + *len_ptr = (size_t)buf->size; + iommu_cb_set.cb_info[idx].io_mapping_size += *len_ptr; + } else { + CAM_ERR(CAM_SMMU, "Error: Wrong region id passed"); + rc = -EINVAL; + goto err_unmap_sg; + } + + CAM_DBG(CAM_SMMU, + "iova=%pK, region_id=%d, paddr=%pK, len=%d, dma_map_attrs=%d", + iova, region_id, *paddr_ptr, *len_ptr, attach->dma_map_attrs); + + if (iommu_cb_set.map_profile_enable) { + CAM_GET_TIMESTAMP(ts2); + CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec); + trace_cam_log_event("SMMUMapProfile", "size and time in micro", + *len_ptr, microsec); + } + + if (table->sgl) { + CAM_DBG(CAM_SMMU, + "DMA buf: %pK, device: %pK, attach: %pK, table: %pK", + (void *)buf, + (void *)iommu_cb_set.cb_info[idx].dev, + (void *)attach, (void *)table); + CAM_DBG(CAM_SMMU, "table sgl: %pK, rc: %d, dma_address: 0x%x", + (void *)table->sgl, rc, + (unsigned int)table->sgl->dma_address); + } else { + rc = -EINVAL; + CAM_ERR(CAM_SMMU, "Error: table sgl is null"); + goto err_unmap_sg; + } + + /* fill up mapping_info */ + *mapping_info = kzalloc(sizeof(struct cam_dma_buff_info), GFP_KERNEL); + if (!(*mapping_info)) { + rc = -ENOSPC; + goto err_alloc; + } + + (*mapping_info)->buf = buf; + (*mapping_info)->attach = attach; + (*mapping_info)->table = table; + (*mapping_info)->paddr = *paddr_ptr; + (*mapping_info)->len = *len_ptr; + (*mapping_info)->dir = dma_dir; + (*mapping_info)->ref_count = 1; + (*mapping_info)->region_id = region_id; + + if (!*paddr_ptr || !*len_ptr) { + CAM_ERR(CAM_SMMU, "Error: Space Allocation failed"); + kfree(*mapping_info); + *mapping_info = NULL; + rc = -ENOSPC; + goto err_alloc; + } + CAM_DBG(CAM_SMMU, "idx=%d, dma_buf=%pK, dev=%pK, paddr=%pK, len=%u", + idx, buf, (void *)iommu_cb_set.cb_info[idx].dev, + (void *)*paddr_ptr, (unsigned int)*len_ptr); + + return 0; + +err_alloc: + if (region_id == CAM_SMMU_REGION_SHARED) { + cam_smmu_free_iova(iova, + size, + iommu_cb_set.cb_info[idx].handle); + + iommu_unmap(iommu_cb_set.cb_info[idx].domain, + *paddr_ptr, + *len_ptr); + } +err_unmap_sg: + dma_buf_unmap_attachment(attach, table, dma_dir); +err_detach: + dma_buf_detach(buf, attach); +err_put: + dma_buf_put(buf); +err_out: + return rc; +} + + +static int cam_smmu_map_buffer_and_add_to_list(int idx, int ion_fd, + bool dis_delayed_unmap, enum dma_data_direction dma_dir, + dma_addr_t *paddr_ptr, size_t *len_ptr, + enum cam_smmu_region_id region_id) +{ + int rc = -1; + struct cam_dma_buff_info *mapping_info = NULL; + struct dma_buf *buf = NULL; + + /* returns the dma_buf structure related to an fd */ + buf = dma_buf_get(ion_fd); + + rc = cam_smmu_map_buffer_validate(buf, idx, dma_dir, paddr_ptr, len_ptr, + region_id, dis_delayed_unmap, &mapping_info); + + if (rc) { + CAM_ERR(CAM_SMMU, "buffer validation failure"); + return rc; + } + + mapping_info->ion_fd = ion_fd; + /* add to the list */ + list_add(&mapping_info->list, + &iommu_cb_set.cb_info[idx].smmu_buf_list); + + cam_smmu_update_monitor_array(&iommu_cb_set.cb_info[idx], true, + mapping_info); + + return 0; +} + +static int cam_smmu_map_kernel_buffer_and_add_to_list(int idx, + struct dma_buf *buf, enum dma_data_direction dma_dir, + dma_addr_t *paddr_ptr, size_t *len_ptr, + enum cam_smmu_region_id region_id) +{ + int rc = -1; + struct cam_dma_buff_info *mapping_info = NULL; + + rc = cam_smmu_map_buffer_validate(buf, idx, dma_dir, paddr_ptr, len_ptr, + region_id, false, &mapping_info); + + if (rc) { + CAM_ERR(CAM_SMMU, "buffer validation failure"); + return rc; + } + + mapping_info->ion_fd = -1; + + /* add to the list */ + list_add(&mapping_info->list, + &iommu_cb_set.cb_info[idx].smmu_buf_kernel_list); + + cam_smmu_update_monitor_array(&iommu_cb_set.cb_info[idx], true, + mapping_info); + + return 0; +} + + +static int cam_smmu_unmap_buf_and_remove_from_list( + struct cam_dma_buff_info *mapping_info, + int idx) +{ + int rc; + size_t size; + struct iommu_domain *domain; + struct timespec64 ts1, ts2; + long microsec = 0; + + if ((!mapping_info->buf) || (!mapping_info->table) || + (!mapping_info->attach)) { + CAM_ERR(CAM_SMMU, + "Error: Invalid params dev = %pK, table = %pK", + (void *)iommu_cb_set.cb_info[idx].dev, + (void *)mapping_info->table); + CAM_ERR(CAM_SMMU, "Error:dma_buf = %pK, attach = %pK", + (void *)mapping_info->buf, + (void *)mapping_info->attach); + return -EINVAL; + } + + cam_smmu_update_monitor_array(&iommu_cb_set.cb_info[idx], false, + mapping_info); + + CAM_DBG(CAM_SMMU, + "region_id=%d, paddr=%pK, len=%d, dma_map_attrs=%d", + mapping_info->region_id, mapping_info->paddr, mapping_info->len, + mapping_info->attach->dma_map_attrs); + + if (iommu_cb_set.map_profile_enable) + CAM_GET_TIMESTAMP(ts1); + + if (mapping_info->region_id == CAM_SMMU_REGION_SHARED) { + CAM_DBG(CAM_SMMU, + "Removing SHARED buffer paddr = %pK, len = %zu", + (void *)mapping_info->paddr, mapping_info->len); + + domain = iommu_cb_set.cb_info[idx].domain; + + size = iommu_unmap(domain, + mapping_info->paddr, + mapping_info->len); + + if (size != mapping_info->len) { + CAM_ERR(CAM_SMMU, "IOMMU unmap failed"); + CAM_ERR(CAM_SMMU, "Unmapped = %zu, requested = %zu", + size, + mapping_info->len); + } + + rc = cam_smmu_free_iova(mapping_info->paddr, + mapping_info->len, + iommu_cb_set.cb_info[idx].handle); + + if (rc) + CAM_ERR(CAM_SMMU, "IOVA free failed"); + + iommu_cb_set.cb_info[idx].shared_mapping_size -= + mapping_info->len; + } else if (mapping_info->region_id == CAM_SMMU_REGION_IO) { + iommu_cb_set.cb_info[idx].io_mapping_size -= mapping_info->len; + } + + dma_buf_unmap_attachment(mapping_info->attach, + mapping_info->table, mapping_info->dir); + dma_buf_detach(mapping_info->buf, mapping_info->attach); + dma_buf_put(mapping_info->buf); + + if (iommu_cb_set.map_profile_enable) { + CAM_GET_TIMESTAMP(ts2); + CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec); + trace_cam_log_event("SMMUUnmapProfile", + "size and time in micro", mapping_info->len, microsec); + } + + mapping_info->buf = NULL; + + list_del_init(&mapping_info->list); + + /* free one buffer */ + kfree(mapping_info); + return 0; +} + +static enum cam_smmu_buf_state cam_smmu_check_fd_in_list(int idx, + int ion_fd, dma_addr_t *paddr_ptr, size_t *len_ptr) +{ + struct cam_dma_buff_info *mapping; + + list_for_each_entry(mapping, + &iommu_cb_set.cb_info[idx].smmu_buf_list, list) { + if (mapping->ion_fd == ion_fd) { + *paddr_ptr = mapping->paddr; + *len_ptr = mapping->len; + return CAM_SMMU_BUFF_EXIST; + } + } + + return CAM_SMMU_BUFF_NOT_EXIST; +} + +static enum cam_smmu_buf_state cam_smmu_check_dma_buf_in_list(int idx, + struct dma_buf *buf, dma_addr_t *paddr_ptr, size_t *len_ptr) +{ + struct cam_dma_buff_info *mapping; + + list_for_each_entry(mapping, + &iommu_cb_set.cb_info[idx].smmu_buf_kernel_list, list) { + if (mapping->buf == buf) { + *paddr_ptr = mapping->paddr; + *len_ptr = mapping->len; + return CAM_SMMU_BUFF_EXIST; + } + } + + return CAM_SMMU_BUFF_NOT_EXIST; +} + +static enum cam_smmu_buf_state cam_smmu_check_secure_fd_in_list(int idx, + int ion_fd, dma_addr_t *paddr_ptr, + size_t *len_ptr) +{ + struct cam_sec_buff_info *mapping; + + list_for_each_entry(mapping, + &iommu_cb_set.cb_info[idx].smmu_buf_list, + list) { + if (mapping->ion_fd == ion_fd) { + *paddr_ptr = mapping->paddr; + *len_ptr = mapping->len; + mapping->ref_count++; + return CAM_SMMU_BUFF_EXIST; + } + } + + return CAM_SMMU_BUFF_NOT_EXIST; +} + +static enum cam_smmu_buf_state cam_smmu_validate_secure_fd_in_list(int idx, + int ion_fd, dma_addr_t *paddr_ptr, size_t *len_ptr) +{ + struct cam_sec_buff_info *mapping; + + list_for_each_entry(mapping, + &iommu_cb_set.cb_info[idx].smmu_buf_list, + list) { + if (mapping->ion_fd == ion_fd) { + *paddr_ptr = mapping->paddr; + *len_ptr = mapping->len; + return CAM_SMMU_BUFF_EXIST; + } + } + + return CAM_SMMU_BUFF_NOT_EXIST; +} + +int cam_smmu_get_handle(char *identifier, int *handle_ptr) +{ + int rc = 0; + + if (!identifier) { + CAM_ERR(CAM_SMMU, "Error: iommu hardware name is NULL"); + return -EINVAL; + } + + if (!handle_ptr) { + CAM_ERR(CAM_SMMU, "Error: handle pointer is NULL"); + return -EINVAL; + } + + /* create and put handle in the table */ + rc = cam_smmu_create_add_handle_in_table(identifier, handle_ptr); + if (rc < 0) + CAM_ERR(CAM_SMMU, "Error: %s get handle fail, rc %d", + identifier, rc); + + return rc; +} +EXPORT_SYMBOL(cam_smmu_get_handle); + +int cam_smmu_ops(int handle, enum cam_smmu_ops_param ops) +{ + int ret = 0, idx; + + if (handle == HANDLE_INIT) { + CAM_ERR(CAM_SMMU, "Error: Invalid handle"); + return -EINVAL; + } + + idx = GET_SMMU_TABLE_IDX(handle); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, "Error: Index invalid. idx = %d hdl = %x", + idx, handle); + return -EINVAL; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, handle); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return -EINVAL; + } + + switch (ops) { + case CAM_SMMU_ATTACH: { + ret = cam_smmu_attach(idx); + break; + } + case CAM_SMMU_DETACH: { + ret = cam_smmu_detach_device(idx); + break; + } + case CAM_SMMU_VOTE: + case CAM_SMMU_DEVOTE: + default: + CAM_ERR(CAM_SMMU, "Error: idx = %d, ops = %d", idx, ops); + ret = -EINVAL; + } + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return ret; +} +EXPORT_SYMBOL(cam_smmu_ops); + +static int cam_smmu_alloc_scratch_buffer_add_to_list(int idx, + size_t virt_len, + size_t phys_len, + unsigned int iommu_dir, + dma_addr_t *virt_addr) +{ + unsigned long nents = virt_len / phys_len; + struct cam_dma_buff_info *mapping_info = NULL; + size_t unmapped; + dma_addr_t iova = 0; + struct scatterlist *sg; + int i = 0; + int rc; + struct iommu_domain *domain = NULL; + struct page *page; + struct sg_table *table = NULL; + + CAM_DBG(CAM_SMMU, "nents = %lu, idx = %d, virt_len = %zx", + nents, idx, virt_len); + CAM_DBG(CAM_SMMU, "phys_len = %zx, iommu_dir = %d, virt_addr = %pK", + phys_len, iommu_dir, virt_addr); + + /* + * This table will go inside the 'mapping' structure + * where it will be held until put_scratch_buffer is called + */ + table = kzalloc(sizeof(struct sg_table), GFP_KERNEL); + if (!table) { + rc = -ENOMEM; + goto err_table_alloc; + } + + rc = sg_alloc_table(table, nents, GFP_KERNEL); + if (rc < 0) { + rc = -EINVAL; + goto err_sg_alloc; + } + + page = alloc_pages(GFP_KERNEL, get_order(phys_len)); + if (!page) { + rc = -ENOMEM; + goto err_page_alloc; + } + + /* Now we create the sg list */ + for_each_sg(table->sgl, sg, table->nents, i) + sg_set_page(sg, page, phys_len, 0); + + + /* Get the domain from within our cb_set struct and map it*/ + domain = iommu_cb_set.cb_info[idx].domain; + + rc = cam_smmu_alloc_scratch_va(&iommu_cb_set.cb_info[idx].scratch_map, + virt_len, &iova); + + if (rc < 0) { + CAM_ERR(CAM_SMMU, + "Could not find valid iova for scratch buffer"); + goto err_iommu_map; + } + + if (iommu_map_sg(domain, + iova, + table->sgl, + table->nents, + iommu_dir) != virt_len) { + CAM_ERR(CAM_SMMU, "iommu_map_sg() failed"); + goto err_iommu_map; + } + + /* Now update our mapping information within the cb_set struct */ + mapping_info = kzalloc(sizeof(struct cam_dma_buff_info), GFP_KERNEL); + if (!mapping_info) { + rc = -ENOMEM; + goto err_mapping_info; + } + + mapping_info->ion_fd = 0xDEADBEEF; + mapping_info->buf = NULL; + mapping_info->attach = NULL; + mapping_info->table = table; + mapping_info->paddr = iova; + mapping_info->len = virt_len; + mapping_info->iommu_dir = iommu_dir; + mapping_info->ref_count = 1; + mapping_info->phys_len = phys_len; + mapping_info->region_id = CAM_SMMU_REGION_SCRATCH; + + CAM_DBG(CAM_SMMU, "paddr = %pK, len = %zx, phys_len = %zx", + (void *)mapping_info->paddr, + mapping_info->len, mapping_info->phys_len); + + list_add(&mapping_info->list, &iommu_cb_set.cb_info[idx].smmu_buf_list); + + *virt_addr = (dma_addr_t)iova; + + CAM_DBG(CAM_SMMU, "mapped virtual address = %lx", + (unsigned long)*virt_addr); + return 0; + +err_mapping_info: + unmapped = iommu_unmap(domain, iova, virt_len); + if (unmapped != virt_len) + CAM_ERR(CAM_SMMU, "Unmapped only %zx instead of %zx", + unmapped, virt_len); +err_iommu_map: + __free_pages(page, get_order(phys_len)); +err_page_alloc: + sg_free_table(table); +err_sg_alloc: + kfree(table); +err_table_alloc: + return rc; +} + +static int cam_smmu_free_scratch_buffer_remove_from_list( + struct cam_dma_buff_info *mapping_info, + int idx) +{ + int rc = 0; + size_t unmapped; + struct iommu_domain *domain = + iommu_cb_set.cb_info[idx].domain; + struct scratch_mapping *scratch_map = + &iommu_cb_set.cb_info[idx].scratch_map; + + if (!mapping_info->table) { + CAM_ERR(CAM_SMMU, + "Error: Invalid params: dev = %pK, table = %pK", + (void *)iommu_cb_set.cb_info[idx].dev, + (void *)mapping_info->table); + return -EINVAL; + } + + /* Clean up the mapping_info struct from the list */ + unmapped = iommu_unmap(domain, mapping_info->paddr, mapping_info->len); + if (unmapped != mapping_info->len) + CAM_ERR(CAM_SMMU, "Unmapped only %zx instead of %zx", + unmapped, mapping_info->len); + + rc = cam_smmu_free_scratch_va(scratch_map, + mapping_info->paddr, + mapping_info->len); + if (rc < 0) { + CAM_ERR(CAM_SMMU, + "Error: Invalid iova while freeing scratch buffer"); + rc = -EINVAL; + } + + __free_pages(sg_page(mapping_info->table->sgl), + get_order(mapping_info->phys_len)); + sg_free_table(mapping_info->table); + kfree(mapping_info->table); + list_del_init(&mapping_info->list); + + kfree(mapping_info); + mapping_info = NULL; + + return rc; +} + +int cam_smmu_get_scratch_iova(int handle, + enum cam_smmu_map_dir dir, + dma_addr_t *paddr_ptr, + size_t virt_len, + size_t phys_len) +{ + int idx, rc; + unsigned int iommu_dir; + + if (!paddr_ptr || !virt_len || !phys_len) { + CAM_ERR(CAM_SMMU, "Error: Input pointer or lengths invalid"); + return -EINVAL; + } + + if (virt_len < phys_len) { + CAM_ERR(CAM_SMMU, "Error: virt_len > phys_len"); + return -EINVAL; + } + + if (handle == HANDLE_INIT) { + CAM_ERR(CAM_SMMU, "Error: Invalid handle"); + return -EINVAL; + } + + iommu_dir = cam_smmu_translate_dir_to_iommu_dir(dir); + if (iommu_dir == IOMMU_INVALID_DIR) { + CAM_ERR(CAM_SMMU, + "Error: translate direction failed. dir = %d", dir); + return -EINVAL; + } + + idx = GET_SMMU_TABLE_IDX(handle); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, handle); + return -EINVAL; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, handle); + rc = -EINVAL; + goto error; + } + + if (!iommu_cb_set.cb_info[idx].scratch_buf_support) { + CAM_ERR(CAM_SMMU, + "Error: Context bank does not support scratch bufs"); + rc = -EINVAL; + goto error; + } + + CAM_DBG(CAM_SMMU, "smmu handle = %x, idx = %d, dir = %d", + handle, idx, dir); + CAM_DBG(CAM_SMMU, "virt_len = %zx, phys_len = %zx", + phys_len, virt_len); + + if (iommu_cb_set.cb_info[idx].state != CAM_SMMU_ATTACH) { + CAM_ERR(CAM_SMMU, + "Err:Dev %s should call SMMU attach before map buffer", + iommu_cb_set.cb_info[idx].name[0]); + rc = -EINVAL; + goto error; + } + + if (!IS_ALIGNED(virt_len, PAGE_SIZE)) { + CAM_ERR(CAM_SMMU, + "Requested scratch buffer length not page aligned"); + rc = -EINVAL; + goto error; + } + + if (!IS_ALIGNED(virt_len, phys_len)) { + CAM_ERR(CAM_SMMU, + "Requested virt length not aligned with phys length"); + rc = -EINVAL; + goto error; + } + + rc = cam_smmu_alloc_scratch_buffer_add_to_list(idx, + virt_len, + phys_len, + iommu_dir, + paddr_ptr); + if (rc < 0) + CAM_ERR(CAM_SMMU, "Error: mapping or add list fail"); + +error: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return rc; +} + +int cam_smmu_put_scratch_iova(int handle, + dma_addr_t paddr) +{ + int idx; + int rc = -1; + struct cam_dma_buff_info *mapping_info; + + if (handle == HANDLE_INIT) { + CAM_ERR(CAM_SMMU, "Error: Invalid handle"); + return -EINVAL; + } + + /* find index in the iommu_cb_set.cb_info */ + idx = GET_SMMU_TABLE_IDX(handle); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, handle); + return -EINVAL; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, handle); + rc = -EINVAL; + goto handle_err; + } + + if (!iommu_cb_set.cb_info[idx].scratch_buf_support) { + CAM_ERR(CAM_SMMU, + "Error: Context bank does not support scratch buffers"); + rc = -EINVAL; + goto handle_err; + } + + /* Based on virtual address and index, we can find mapping info + * of the scratch buffer + */ + mapping_info = cam_smmu_find_mapping_by_virt_address(idx, paddr); + if (!mapping_info) { + CAM_ERR(CAM_SMMU, "Error: Invalid params"); + rc = -ENODEV; + goto handle_err; + } + + /* unmapping one buffer from device */ + rc = cam_smmu_free_scratch_buffer_remove_from_list(mapping_info, idx); + if (rc < 0) { + CAM_ERR(CAM_SMMU, "Error: unmap or remove list fail"); + goto handle_err; + } + +handle_err: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return rc; +} + +static int cam_smmu_map_stage2_buffer_and_add_to_list(int idx, int ion_fd, + enum dma_data_direction dma_dir, dma_addr_t *paddr_ptr, + size_t *len_ptr) +{ + int rc = 0; + struct dma_buf *dmabuf = NULL; + struct dma_buf_attachment *attach = NULL; + struct sg_table *table = NULL; + struct cam_sec_buff_info *mapping_info; + + /* clean the content from clients */ + *paddr_ptr = (dma_addr_t)NULL; + *len_ptr = (size_t)0; + + dmabuf = dma_buf_get(ion_fd); + if (IS_ERR_OR_NULL((void *)(dmabuf))) { + CAM_ERR(CAM_SMMU, + "Error: dma buf get failed, idx=%d, ion_fd=%d", + idx, ion_fd); + rc = PTR_ERR(dmabuf); + goto err_out; + } + + /* + * ion_phys() is deprecated. call dma_buf_attach() and + * dma_buf_map_attachment() to get the buffer's physical + * address. + */ + attach = dma_buf_attach(dmabuf, iommu_cb_set.cb_info[idx].dev); + if (IS_ERR_OR_NULL(attach)) { + CAM_ERR(CAM_SMMU, + "Error: dma buf attach failed, idx=%d, ion_fd=%d", + idx, ion_fd); + rc = PTR_ERR(attach); + goto err_put; + } + + attach->dma_map_attrs |= DMA_ATTR_SKIP_CPU_SYNC; + + table = dma_buf_map_attachment(attach, dma_dir); + if (IS_ERR_OR_NULL(table)) { + CAM_ERR(CAM_SMMU, "Error: dma buf map attachment failed"); + rc = PTR_ERR(table); + goto err_detach; + } + + /* return addr and len to client */ + *paddr_ptr = sg_phys(table->sgl); + *len_ptr = (size_t)sg_dma_len(table->sgl); + + /* fill up mapping_info */ + mapping_info = kzalloc(sizeof(struct cam_sec_buff_info), GFP_KERNEL); + if (!mapping_info) { + rc = -ENOMEM; + goto err_unmap_sg; + } + + mapping_info->ion_fd = ion_fd; + mapping_info->paddr = *paddr_ptr; + mapping_info->len = *len_ptr; + mapping_info->dir = dma_dir; + mapping_info->ref_count = 1; + mapping_info->buf = dmabuf; + mapping_info->attach = attach; + mapping_info->table = table; + + CAM_DBG(CAM_SMMU, "idx=%d, ion_fd=%d, dev=%pK, paddr=%pK, len=%u", + idx, ion_fd, + (void *)iommu_cb_set.cb_info[idx].dev, + (void *)*paddr_ptr, (unsigned int)*len_ptr); + + /* add to the list */ + list_add(&mapping_info->list, &iommu_cb_set.cb_info[idx].smmu_buf_list); + + return 0; + +err_unmap_sg: + dma_buf_unmap_attachment(attach, table, dma_dir); +err_detach: + dma_buf_detach(dmabuf, attach); +err_put: + dma_buf_put(dmabuf); +err_out: + return rc; +} + +int cam_smmu_map_stage2_iova(int handle, + int ion_fd, enum cam_smmu_map_dir dir, + dma_addr_t *paddr_ptr, size_t *len_ptr) +{ + int idx, rc; + enum dma_data_direction dma_dir; + enum cam_smmu_buf_state buf_state; + + if (!paddr_ptr || !len_ptr) { + CAM_ERR(CAM_SMMU, + "Error: Invalid inputs, paddr_ptr:%pK, len_ptr: %pK", + paddr_ptr, len_ptr); + return -EINVAL; + } + /* clean the content from clients */ + *paddr_ptr = (dma_addr_t)NULL; + *len_ptr = (size_t)0; + + dma_dir = cam_smmu_translate_dir(dir); + if (dma_dir == DMA_NONE) { + CAM_ERR(CAM_SMMU, + "Error: translate direction failed. dir = %d", dir); + return -EINVAL; + } + + idx = GET_SMMU_TABLE_IDX(handle); + if ((handle == HANDLE_INIT) || + (idx < 0) || + (idx >= iommu_cb_set.cb_num)) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, handle); + return -EINVAL; + } + + if (!iommu_cb_set.cb_info[idx].is_secure) { + CAM_ERR(CAM_SMMU, + "Error: can't map secure mem to non secure cb, idx=%d", + idx); + return -EINVAL; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, idx=%d, table_hdl=%x, hdl=%x", + idx, iommu_cb_set.cb_info[idx].handle, handle); + rc = -EINVAL; + goto get_addr_end; + } + + buf_state = cam_smmu_check_secure_fd_in_list(idx, ion_fd, paddr_ptr, + len_ptr); + if (buf_state == CAM_SMMU_BUFF_EXIST) { + CAM_DBG(CAM_SMMU, + "fd:%d already in list idx:%d, handle=%d give same addr back", + ion_fd, idx, handle); + rc = 0; + goto get_addr_end; + } + rc = cam_smmu_map_stage2_buffer_and_add_to_list(idx, ion_fd, dma_dir, + paddr_ptr, len_ptr); + if (rc < 0) { + CAM_ERR(CAM_SMMU, + "Error: mapping or add list fail, idx=%d, handle=%d, fd=%d, rc=%d", + idx, handle, ion_fd, rc); + goto get_addr_end; + } + +get_addr_end: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return rc; +} +EXPORT_SYMBOL(cam_smmu_map_stage2_iova); + +static int cam_smmu_secure_unmap_buf_and_remove_from_list( + struct cam_sec_buff_info *mapping_info, + int idx) +{ + if ((!mapping_info->buf) || (!mapping_info->table) || + (!mapping_info->attach)) { + CAM_ERR(CAM_SMMU, + "Error: Invalid params dev = %pK, table = %pK", + (void *)iommu_cb_set.cb_info[idx].dev, + (void *)mapping_info->table); + CAM_ERR(CAM_SMMU, "Error:dma_buf = %pK, attach = %pK\n", + (void *)mapping_info->buf, + (void *)mapping_info->attach); + return -EINVAL; + } + + /* skip cache operations */ + mapping_info->attach->dma_map_attrs |= DMA_ATTR_SKIP_CPU_SYNC; + + /* iommu buffer clean up */ + dma_buf_unmap_attachment(mapping_info->attach, + mapping_info->table, mapping_info->dir); + dma_buf_detach(mapping_info->buf, mapping_info->attach); + dma_buf_put(mapping_info->buf); + mapping_info->buf = NULL; + + list_del_init(&mapping_info->list); + + CAM_DBG(CAM_SMMU, "unmap fd: %d, idx : %d", mapping_info->ion_fd, idx); + + /* free one buffer */ + kfree(mapping_info); + return 0; +} + +int cam_smmu_unmap_stage2_iova(int handle, int ion_fd) +{ + int idx, rc; + struct cam_sec_buff_info *mapping_info; + + /* find index in the iommu_cb_set.cb_info */ + idx = GET_SMMU_TABLE_IDX(handle); + if ((handle == HANDLE_INIT) || + (idx < 0) || + (idx >= iommu_cb_set.cb_num)) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, handle); + return -EINVAL; + } + + if (!iommu_cb_set.cb_info[idx].is_secure) { + CAM_ERR(CAM_SMMU, + "Error: can't unmap secure mem from non secure cb"); + return -EINVAL; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, handle); + rc = -EINVAL; + goto put_addr_end; + } + + /* based on ion fd and index, we can find mapping info of buffer */ + mapping_info = cam_smmu_find_mapping_by_sec_buf_idx(idx, ion_fd); + if (!mapping_info) { + CAM_ERR(CAM_SMMU, + "Error: Invalid params! idx = %d, fd = %d", + idx, ion_fd); + rc = -EINVAL; + goto put_addr_end; + } + + mapping_info->ref_count--; + if (mapping_info->ref_count > 0) { + CAM_DBG(CAM_SMMU, + "idx: %d fd = %d ref_count: %d", + idx, ion_fd, mapping_info->ref_count); + rc = 0; + goto put_addr_end; + } + mapping_info->ref_count = 0; + + /* unmapping one buffer from device */ + rc = cam_smmu_secure_unmap_buf_and_remove_from_list(mapping_info, idx); + if (rc) { + CAM_ERR(CAM_SMMU, "Error: unmap or remove list fail"); + goto put_addr_end; + } + +put_addr_end: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return rc; +} +EXPORT_SYMBOL(cam_smmu_unmap_stage2_iova); + +static int cam_smmu_map_iova_validate_params(int handle, + enum cam_smmu_map_dir dir, + dma_addr_t *paddr_ptr, size_t *len_ptr, + enum cam_smmu_region_id region_id) +{ + int idx, rc = 0; + enum dma_data_direction dma_dir; + + if (!paddr_ptr || !len_ptr) { + CAM_ERR(CAM_SMMU, "Input pointers are invalid"); + return -EINVAL; + } + + if (handle == HANDLE_INIT) { + CAM_ERR(CAM_SMMU, "Invalid handle"); + return -EINVAL; + } + + /* clean the content from clients */ + *paddr_ptr = (dma_addr_t)NULL; + if (region_id != CAM_SMMU_REGION_SHARED) + *len_ptr = (size_t)0; + + dma_dir = cam_smmu_translate_dir(dir); + if (dma_dir == DMA_NONE) { + CAM_ERR(CAM_SMMU, "translate direction failed. dir = %d", dir); + return -EINVAL; + } + + idx = GET_SMMU_TABLE_IDX(handle); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, "handle or index invalid. idx = %d hdl = %x", + idx, handle); + return -EINVAL; + } + + return rc; +} + +int cam_smmu_map_user_iova(int handle, int ion_fd, bool dis_delayed_unmap, + enum cam_smmu_map_dir dir, dma_addr_t *paddr_ptr, + size_t *len_ptr, enum cam_smmu_region_id region_id) +{ + int idx, rc = 0; + enum cam_smmu_buf_state buf_state; + enum dma_data_direction dma_dir; + + rc = cam_smmu_map_iova_validate_params(handle, dir, paddr_ptr, + len_ptr, region_id); + if (rc) { + CAM_ERR(CAM_SMMU, "initial checks failed, unable to proceed"); + return rc; + } + + dma_dir = (enum dma_data_direction)dir; + idx = GET_SMMU_TABLE_IDX(handle); + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].is_secure) { + CAM_ERR(CAM_SMMU, + "Error: can't map non-secure mem to secure cb idx=%d", + idx); + rc = -EINVAL; + goto get_addr_end; + } + + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "hdl is not valid, idx=%d, table_hdl = %x, hdl = %x", + idx, iommu_cb_set.cb_info[idx].handle, handle); + rc = -EINVAL; + goto get_addr_end; + } + + if (iommu_cb_set.cb_info[idx].state != CAM_SMMU_ATTACH) { + CAM_ERR(CAM_SMMU, + "Err:Dev %s should call SMMU attach before map buffer", + iommu_cb_set.cb_info[idx].name[0]); + rc = -EINVAL; + goto get_addr_end; + } + + buf_state = cam_smmu_check_fd_in_list(idx, ion_fd, paddr_ptr, len_ptr); + if (buf_state == CAM_SMMU_BUFF_EXIST) { + CAM_ERR(CAM_SMMU, + "fd:%d already in list idx:%d, handle=%d, give same addr back", + ion_fd, idx, handle); + rc = -EALREADY; + goto get_addr_end; + } + + rc = cam_smmu_map_buffer_and_add_to_list(idx, ion_fd, + dis_delayed_unmap, dma_dir, paddr_ptr, len_ptr, region_id); + if (rc < 0) { + CAM_ERR(CAM_SMMU, + "mapping or add list fail, idx=%d, fd=%d, region=%d, rc=%d", + idx, ion_fd, region_id, rc); + cam_smmu_dump_cb_info(idx); + } + +get_addr_end: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return rc; +} +EXPORT_SYMBOL(cam_smmu_map_user_iova); + +int cam_smmu_map_kernel_iova(int handle, struct dma_buf *buf, + enum cam_smmu_map_dir dir, dma_addr_t *paddr_ptr, + size_t *len_ptr, enum cam_smmu_region_id region_id) +{ + int idx, rc = 0; + enum cam_smmu_buf_state buf_state; + enum dma_data_direction dma_dir; + + rc = cam_smmu_map_iova_validate_params(handle, dir, paddr_ptr, + len_ptr, region_id); + if (rc) { + CAM_ERR(CAM_SMMU, "initial checks failed, unable to proceed"); + return rc; + } + + dma_dir = cam_smmu_translate_dir(dir); + idx = GET_SMMU_TABLE_IDX(handle); + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].is_secure) { + CAM_ERR(CAM_SMMU, + "Error: can't map non-secure mem to secure cb"); + rc = -EINVAL; + goto get_addr_end; + } + + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, "hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, handle); + rc = -EINVAL; + goto get_addr_end; + } + + if (iommu_cb_set.cb_info[idx].state != CAM_SMMU_ATTACH) { + CAM_ERR(CAM_SMMU, + "Err:Dev %s should call SMMU attach before map buffer", + iommu_cb_set.cb_info[idx].name[0]); + rc = -EINVAL; + goto get_addr_end; + } + + buf_state = cam_smmu_check_dma_buf_in_list(idx, buf, + paddr_ptr, len_ptr); + if (buf_state == CAM_SMMU_BUFF_EXIST) { + CAM_ERR(CAM_SMMU, + "dma_buf :%pK already in the list", buf); + rc = -EALREADY; + goto get_addr_end; + } + + rc = cam_smmu_map_kernel_buffer_and_add_to_list(idx, buf, dma_dir, + paddr_ptr, len_ptr, region_id); + if (rc < 0) + CAM_ERR(CAM_SMMU, "mapping or add list fail"); + +get_addr_end: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return rc; +} +EXPORT_SYMBOL(cam_smmu_map_kernel_iova); + +int cam_smmu_get_iova(int handle, int ion_fd, + dma_addr_t *paddr_ptr, size_t *len_ptr) +{ + int idx, rc = 0; + enum cam_smmu_buf_state buf_state; + + if (!paddr_ptr || !len_ptr) { + CAM_ERR(CAM_SMMU, "Error: Input pointers are invalid"); + return -EINVAL; + } + + if (handle == HANDLE_INIT) { + CAM_ERR(CAM_SMMU, "Error: Invalid handle"); + return -EINVAL; + } + + /* clean the content from clients */ + *paddr_ptr = (dma_addr_t)NULL; + *len_ptr = (size_t)0; + + idx = GET_SMMU_TABLE_IDX(handle); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, handle); + return -EINVAL; + } + + if (iommu_cb_set.cb_info[idx].is_secure) { + CAM_ERR(CAM_SMMU, + "Error: can't get non-secure mem from secure cb"); + return -EINVAL; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, handle); + rc = -EINVAL; + goto get_addr_end; + } + + buf_state = cam_smmu_check_fd_in_list(idx, ion_fd, paddr_ptr, len_ptr); + if (buf_state == CAM_SMMU_BUFF_NOT_EXIST) { + CAM_ERR(CAM_SMMU, "ion_fd:%d not in the mapped list", ion_fd); + rc = -EINVAL; + cam_smmu_dump_cb_info(idx); + goto get_addr_end; + } + +get_addr_end: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return rc; +} +EXPORT_SYMBOL(cam_smmu_get_iova); + +int cam_smmu_get_stage2_iova(int handle, int ion_fd, + dma_addr_t *paddr_ptr, size_t *len_ptr) +{ + int idx, rc = 0; + enum cam_smmu_buf_state buf_state; + + if (!paddr_ptr || !len_ptr) { + CAM_ERR(CAM_SMMU, "Error: Input pointers are invalid"); + return -EINVAL; + } + + if (handle == HANDLE_INIT) { + CAM_ERR(CAM_SMMU, "Error: Invalid handle"); + return -EINVAL; + } + + /* clean the content from clients */ + *paddr_ptr = (dma_addr_t)NULL; + *len_ptr = (size_t)0; + + idx = GET_SMMU_TABLE_IDX(handle); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, handle); + return -EINVAL; + } + + if (!iommu_cb_set.cb_info[idx].is_secure) { + CAM_ERR(CAM_SMMU, + "Error: can't get secure mem from non secure cb"); + return -EINVAL; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, handle); + rc = -EINVAL; + goto get_addr_end; + } + + buf_state = cam_smmu_validate_secure_fd_in_list(idx, + ion_fd, + paddr_ptr, + len_ptr); + + if (buf_state == CAM_SMMU_BUFF_NOT_EXIST) { + CAM_ERR(CAM_SMMU, "ion_fd:%d not in the mapped list", ion_fd); + rc = -EINVAL; + goto get_addr_end; + } + +get_addr_end: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return rc; +} +EXPORT_SYMBOL(cam_smmu_get_stage2_iova); + +static int cam_smmu_unmap_validate_params(int handle) +{ + int idx; + + if (handle == HANDLE_INIT) { + CAM_ERR(CAM_SMMU, "Error: Invalid handle"); + return -EINVAL; + } + + /* find index in the iommu_cb_set.cb_info */ + idx = GET_SMMU_TABLE_IDX(handle); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, handle); + return -EINVAL; + } + + return 0; +} + +int cam_smmu_unmap_user_iova(int handle, + int ion_fd, enum cam_smmu_region_id region_id) +{ + int idx, rc; + struct cam_dma_buff_info *mapping_info; + + rc = cam_smmu_unmap_validate_params(handle); + if (rc) { + CAM_ERR(CAM_SMMU, "unmap util validation failure"); + return rc; + } + + idx = GET_SMMU_TABLE_IDX(handle); + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].is_secure) { + CAM_ERR(CAM_SMMU, + "Error: can't unmap non-secure mem from secure cb"); + rc = -EINVAL; + goto unmap_end; + } + + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, handle); + rc = -EINVAL; + goto unmap_end; + } + + /* Based on ion_fd & index, we can find mapping info of buffer */ + mapping_info = cam_smmu_find_mapping_by_ion_index(idx, ion_fd); + + if (!mapping_info) { + CAM_ERR(CAM_SMMU, + "Error: Invalid params idx = %d, fd = %d", + idx, ion_fd); + rc = -EINVAL; + goto unmap_end; + } + + /* Unmapping one buffer from device */ + CAM_DBG(CAM_SMMU, "SMMU: removing buffer idx = %d", idx); + rc = cam_smmu_unmap_buf_and_remove_from_list(mapping_info, idx); + if (rc < 0) + CAM_ERR(CAM_SMMU, "Error: unmap or remove list fail"); + +unmap_end: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return rc; +} +EXPORT_SYMBOL(cam_smmu_unmap_user_iova); + +int cam_smmu_unmap_kernel_iova(int handle, + struct dma_buf *buf, enum cam_smmu_region_id region_id) +{ + int idx, rc; + struct cam_dma_buff_info *mapping_info; + + rc = cam_smmu_unmap_validate_params(handle); + if (rc) { + CAM_ERR(CAM_SMMU, "unmap util validation failure"); + return rc; + } + + idx = GET_SMMU_TABLE_IDX(handle); + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].is_secure) { + CAM_ERR(CAM_SMMU, + "Error: can't unmap non-secure mem from secure cb"); + rc = -EINVAL; + goto unmap_end; + } + + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, handle); + rc = -EINVAL; + goto unmap_end; + } + + /* Based on dma_buf & index, we can find mapping info of buffer */ + mapping_info = cam_smmu_find_mapping_by_dma_buf(idx, buf); + + if (!mapping_info) { + CAM_ERR(CAM_SMMU, + "Error: Invalid params idx = %d, dma_buf = %pK", + idx, buf); + rc = -EINVAL; + goto unmap_end; + } + + /* Unmapping one buffer from device */ + CAM_DBG(CAM_SMMU, "SMMU: removing buffer idx = %d", idx); + rc = cam_smmu_unmap_buf_and_remove_from_list(mapping_info, idx); + if (rc < 0) + CAM_ERR(CAM_SMMU, "Error: unmap or remove list fail"); + +unmap_end: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return rc; +} +EXPORT_SYMBOL(cam_smmu_unmap_kernel_iova); + + +int cam_smmu_put_iova(int handle, int ion_fd) +{ + int idx; + int rc = 0; + struct cam_dma_buff_info *mapping_info; + + if (handle == HANDLE_INIT) { + CAM_ERR(CAM_SMMU, "Error: Invalid handle"); + return -EINVAL; + } + + /* find index in the iommu_cb_set.cb_info */ + idx = GET_SMMU_TABLE_IDX(handle); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, handle); + return -EINVAL; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, handle); + rc = -EINVAL; + goto put_addr_end; + } + + /* based on ion fd and index, we can find mapping info of buffer */ + mapping_info = cam_smmu_find_mapping_by_ion_index(idx, ion_fd); + if (!mapping_info) { + CAM_ERR(CAM_SMMU, "Error: Invalid params idx = %d, fd = %d", + idx, ion_fd); + rc = -EINVAL; + goto put_addr_end; + } + +put_addr_end: + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return rc; +} +EXPORT_SYMBOL(cam_smmu_put_iova); + +int cam_smmu_destroy_handle(int handle) +{ + int idx; + + if (handle == HANDLE_INIT) { + CAM_ERR(CAM_SMMU, "Error: Invalid handle"); + return -EINVAL; + } + + idx = GET_SMMU_TABLE_IDX(handle); + if (idx < 0 || idx >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, + "Error: handle or index invalid. idx = %d hdl = %x", + idx, handle); + return -EINVAL; + } + + mutex_lock(&iommu_cb_set.cb_info[idx].lock); + if (iommu_cb_set.cb_info[idx].handle != handle) { + CAM_ERR(CAM_SMMU, + "Error: hdl is not valid, table_hdl = %x, hdl = %x", + iommu_cb_set.cb_info[idx].handle, handle); + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return -EINVAL; + } + + if (!list_empty_careful(&iommu_cb_set.cb_info[idx].smmu_buf_list)) { + CAM_ERR(CAM_SMMU, "UMD %s buffer list is not clean", + iommu_cb_set.cb_info[idx].name[0]); + cam_smmu_print_user_list(idx); + cam_smmu_clean_user_buffer_list(idx); + } + + if (!list_empty_careful( + &iommu_cb_set.cb_info[idx].smmu_buf_kernel_list)) { + CAM_ERR(CAM_SMMU, "KMD %s buffer list is not clean", + iommu_cb_set.cb_info[idx].name[0]); + cam_smmu_print_kernel_list(idx); + cam_smmu_clean_kernel_buffer_list(idx); + } + + if (iommu_cb_set.cb_info[idx].is_secure) { + if (iommu_cb_set.cb_info[idx].secure_count == 0) { + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return -EPERM; + } + + iommu_cb_set.cb_info[idx].secure_count--; + if (iommu_cb_set.cb_info[idx].secure_count == 0) { + iommu_cb_set.cb_info[idx].cb_count = 0; + iommu_cb_set.cb_info[idx].handle = HANDLE_INIT; + } + + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return 0; + } + + if (iommu_cb_set.cb_info[idx].is_mul_client && + iommu_cb_set.cb_info[idx].device_count) { + iommu_cb_set.cb_info[idx].device_count--; + + if (!iommu_cb_set.cb_info[idx].device_count) { + iommu_cb_set.cb_info[idx].cb_count = 0; + iommu_cb_set.cb_info[idx].handle = HANDLE_INIT; + } + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return 0; + } + + iommu_cb_set.cb_info[idx].device_count = 0; + iommu_cb_set.cb_info[idx].cb_count = 0; + iommu_cb_set.cb_info[idx].handle = HANDLE_INIT; + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return 0; +} +EXPORT_SYMBOL(cam_smmu_destroy_handle); + +static void cam_smmu_deinit_cb(struct cam_context_bank_info *cb) +{ + if (cb->io_support && cb->domain) { + cb->domain = NULL; + } + + if (cb->shared_support) { + gen_pool_destroy(cb->shared_mem_pool); + cb->shared_mem_pool = NULL; + } + + if (cb->scratch_buf_support) { + kfree(cb->scratch_map.bitmap); + cb->scratch_map.bitmap = NULL; + } +} + +static void cam_smmu_release_cb(struct platform_device *pdev) +{ + int i = 0; + + for (i = 0; i < iommu_cb_set.cb_num; i++) + cam_smmu_deinit_cb(&iommu_cb_set.cb_info[i]); + + devm_kfree(&pdev->dev, iommu_cb_set.cb_info); + iommu_cb_set.cb_num = 0; +} + +static int cam_smmu_setup_cb(struct cam_context_bank_info *cb, + struct device *dev) +{ + int rc = 0; + + if (!cb || !dev) { + CAM_ERR(CAM_SMMU, "Error: invalid input params"); + return -EINVAL; + } + + cb->dev = dev; + cb->is_fw_allocated = false; + cb->is_secheap_allocated = false; + + atomic64_set(&cb->monitor_head, -1); + + /* Create a pool with 64K granularity for supporting shared memory */ + if (cb->shared_support) { + cb->shared_mem_pool = gen_pool_create( + SHARED_MEM_POOL_GRANULARITY, -1); + + if (!cb->shared_mem_pool) + return -ENOMEM; + + rc = gen_pool_add(cb->shared_mem_pool, + cb->shared_info.iova_start, + cb->shared_info.iova_len, + -1); + + CAM_DBG(CAM_SMMU, "Shared mem start->%lX", + (unsigned long)cb->shared_info.iova_start); + CAM_DBG(CAM_SMMU, "Shared mem len->%zu", + cb->shared_info.iova_len); + + if (rc) { + CAM_ERR(CAM_SMMU, "Genpool chunk creation failed"); + gen_pool_destroy(cb->shared_mem_pool); + cb->shared_mem_pool = NULL; + return rc; + } + } + + if (cb->scratch_buf_support) { + rc = cam_smmu_init_scratch_map(&cb->scratch_map, + cb->scratch_info.iova_start, + cb->scratch_info.iova_len, + 0); + if (rc < 0) { + CAM_ERR(CAM_SMMU, + "Error: failed to create scratch map"); + rc = -ENODEV; + goto end; + } + } + + /* create a virtual mapping */ + if (cb->io_support) { + cb->domain = iommu_get_domain_for_dev(dev); + if (IS_ERR(cb->domain)) { + CAM_ERR(CAM_SMMU, "Error: create domain Failed"); + rc = -ENODEV; + goto end; + } + + iommu_dma_enable_best_fit_algo(dev); + + if (cb->discard_iova_start) + iommu_dma_reserve_iova(dev, cb->discard_iova_start, + cb->discard_iova_len); + + cb->state = CAM_SMMU_ATTACH; + } else { + CAM_ERR(CAM_SMMU, "Context bank does not have IO region"); + rc = -ENODEV; + goto end; + } + + return rc; +end: + if (cb->shared_support) { + gen_pool_destroy(cb->shared_mem_pool); + cb->shared_mem_pool = NULL; + } + + if (cb->scratch_buf_support) { + kfree(cb->scratch_map.bitmap); + cb->scratch_map.bitmap = NULL; + } + + return rc; +} + +static int cam_alloc_smmu_context_banks(struct device *dev) +{ + struct device_node *domains_child_node = NULL; + + if (!dev) { + CAM_ERR(CAM_SMMU, "Error: Invalid device"); + return -ENODEV; + } + + iommu_cb_set.cb_num = 0; + + /* traverse thru all the child nodes and increment the cb count */ + for_each_available_child_of_node(dev->of_node, domains_child_node) { + if (of_device_is_compatible(domains_child_node, + "qcom,msm-cam-smmu-cb")) + iommu_cb_set.cb_num++; + + if (of_device_is_compatible(domains_child_node, + "qcom,qsmmu-cam-cb")) + iommu_cb_set.cb_num++; + } + + if (iommu_cb_set.cb_num == 0) { + CAM_ERR(CAM_SMMU, "Error: no context banks present"); + return -ENOENT; + } + + /* allocate memory for the context banks */ + iommu_cb_set.cb_info = devm_kzalloc(dev, + iommu_cb_set.cb_num * sizeof(struct cam_context_bank_info), + GFP_KERNEL); + + if (!iommu_cb_set.cb_info) { + CAM_ERR(CAM_SMMU, "Error: cannot allocate context banks"); + return -ENOMEM; + } + + cam_smmu_reset_iommu_table(CAM_SMMU_TABLE_INIT); + iommu_cb_set.cb_init_count = 0; + + CAM_DBG(CAM_SMMU, "no of context banks :%d", iommu_cb_set.cb_num); + return 0; +} + +static int cam_smmu_get_discard_memory_regions(struct device_node *of_node, + dma_addr_t *discard_iova_start, size_t *discard_iova_len) +{ + uint32_t discard_iova[2] = { 0 }; + int num_values = 0; + int rc = 0; + + if (!discard_iova_start || !discard_iova_len) + return -EINVAL; + + *discard_iova_start = 0; + *discard_iova_len = 0; + + num_values = of_property_count_u32_elems(of_node, + "iova-region-discard"); + if (num_values <= 0) { + CAM_DBG(CAM_UTIL, "No discard region specified"); + return 0; + } else if (num_values != 2) { + CAM_ERR(CAM_UTIL, "Invalid discard region specified %d", + num_values); + return -EINVAL; + } + + rc = of_property_read_u32_array(of_node, + "iova-region-discard", + discard_iova, num_values); + if (rc) { + CAM_ERR(CAM_UTIL, "Can not read discard region %d", num_values); + return rc; + } else if (!discard_iova[0] || !discard_iova[1]) { + CAM_ERR(CAM_UTIL, + "Incorrect Discard region specified [0x%x 0x%x]", + discard_iova[0], discard_iova[1]); + return -EINVAL; + } + + CAM_DBG(CAM_UTIL, "Discard region [0x%x 0x%x]", + discard_iova[0], discard_iova[0] + discard_iova[1]); + + *discard_iova_start = discard_iova[0]; + *discard_iova_len = discard_iova[1]; + + return 0; +} + +static int cam_smmu_get_memory_regions_info(struct device_node *of_node, + struct cam_context_bank_info *cb) +{ + int rc = 0; + struct device_node *mem_map_node = NULL; + struct device_node *child_node = NULL; + const char *region_name; + int num_regions = 0; + + if (!of_node || !cb) { + CAM_ERR(CAM_SMMU, "Invalid argument(s)"); + return -EINVAL; + } + + mem_map_node = of_get_child_by_name(of_node, "iova-mem-map"); + cb->is_secure = of_property_read_bool(of_node, "qcom,secure-cb"); + + /* + * We always expect a memory map node, except when it is a secure + * context bank. + */ + if (!mem_map_node) { + if (cb->is_secure) + return 0; + CAM_ERR(CAM_SMMU, "iova-mem-map not present"); + return -EINVAL; + } + + for_each_available_child_of_node(mem_map_node, child_node) { + uint32_t region_start; + uint32_t region_len; + uint32_t region_id; + uint32_t qdss_region_phy_addr = 0; + + num_regions++; + rc = of_property_read_string(child_node, + "iova-region-name", ®ion_name); + if (rc < 0) { + of_node_put(mem_map_node); + CAM_ERR(CAM_SMMU, "IOVA region not found"); + return -EINVAL; + } + + rc = of_property_read_u32(child_node, + "iova-region-start", ®ion_start); + if (rc < 0) { + of_node_put(mem_map_node); + CAM_ERR(CAM_SMMU, "Failed to read iova-region-start"); + return -EINVAL; + } + + rc = of_property_read_u32(child_node, + "iova-region-len", ®ion_len); + if (rc < 0) { + of_node_put(mem_map_node); + CAM_ERR(CAM_SMMU, "Failed to read iova-region-len"); + return -EINVAL; + } + + rc = of_property_read_u32(child_node, + "iova-region-id", ®ion_id); + if (rc < 0) { + of_node_put(mem_map_node); + CAM_ERR(CAM_SMMU, "Failed to read iova-region-id"); + return -EINVAL; + } + + if (strcmp(region_name, qdss_region_name) == 0) { + rc = of_property_read_u32(child_node, + "qdss-phy-addr", &qdss_region_phy_addr); + if (rc < 0) { + of_node_put(mem_map_node); + CAM_ERR(CAM_SMMU, + "Failed to read qdss phy addr"); + return -EINVAL; + } + } + + switch (region_id) { + case CAM_SMMU_REGION_FIRMWARE: + cb->firmware_support = 1; + cb->firmware_info.iova_start = region_start; + cb->firmware_info.iova_len = region_len; + break; + case CAM_SMMU_REGION_SHARED: + cb->shared_support = 1; + cb->shared_info.iova_start = region_start; + cb->shared_info.iova_len = region_len; + break; + case CAM_SMMU_REGION_SCRATCH: + cb->scratch_buf_support = 1; + cb->scratch_info.iova_start = region_start; + cb->scratch_info.iova_len = region_len; + break; + case CAM_SMMU_REGION_IO: + cb->io_support = 1; + cb->io_info.iova_start = region_start; + cb->io_info.iova_len = region_len; + rc = cam_smmu_get_discard_memory_regions(child_node, + &cb->io_info.discard_iova_start, + &cb->io_info.discard_iova_len); + if (rc) { + CAM_ERR(CAM_SMMU, + "Invalid Discard region specified in IO region, rc=%d", + rc); + of_node_put(mem_map_node); + return -EINVAL; + } + break; + case CAM_SMMU_REGION_SECHEAP: + cb->secheap_support = 1; + cb->secheap_info.iova_start = region_start; + cb->secheap_info.iova_len = region_len; + break; + case CAM_SMMU_REGION_QDSS: + cb->qdss_support = 1; + cb->qdss_info.iova_start = region_start; + cb->qdss_info.iova_len = region_len; + cb->qdss_phy_addr = qdss_region_phy_addr; + break; + default: + CAM_ERR(CAM_SMMU, + "Incorrect region id present in DT file: %d", + region_id); + } + + CAM_DBG(CAM_SMMU, "Found label -> %s", cb->name[0]); + CAM_DBG(CAM_SMMU, "Found region -> %s", region_name); + CAM_DBG(CAM_SMMU, "region_start -> %X", region_start); + CAM_DBG(CAM_SMMU, "region_len -> %X", region_len); + CAM_DBG(CAM_SMMU, "region_id -> %X", region_id); + } + + if (cb->io_support) { + rc = cam_smmu_get_discard_memory_regions(of_node, + &cb->discard_iova_start, + &cb->discard_iova_len); + if (rc) { + CAM_ERR(CAM_SMMU, + "Invalid Discard region specified in CB, rc=%d", + rc); + of_node_put(mem_map_node); + return -EINVAL; + } + + /* Make sure Discard region is properly specified */ + if ((cb->discard_iova_start != + cb->io_info.discard_iova_start) || + (cb->discard_iova_len != + cb->io_info.discard_iova_len)) { + CAM_ERR(CAM_SMMU, + "Mismatch Discard region specified, [0x%x 0x%x] [0x%x 0x%x]", + cb->discard_iova_start, + cb->discard_iova_len, + cb->io_info.discard_iova_start, + cb->io_info.discard_iova_len); + of_node_put(mem_map_node); + return -EINVAL; + } else if (cb->discard_iova_start && cb->discard_iova_len) { + if ((cb->discard_iova_start <= + cb->io_info.iova_start) || + (cb->discard_iova_start >= + cb->io_info.iova_start + cb->io_info.iova_len) || + (cb->discard_iova_start + cb->discard_iova_len >= + cb->io_info.iova_start + cb->io_info.iova_len)) { + CAM_ERR(CAM_SMMU, + "[%s] : Incorrect Discard region specified [0x%x 0x%x] in [0x%x 0x%x]", + cb->name[0], + cb->discard_iova_start, + cb->discard_iova_start + cb->discard_iova_len, + cb->io_info.iova_start, + cb->io_info.iova_start + cb->io_info.iova_len); + of_node_put(mem_map_node); + return -EINVAL; + } + + CAM_INFO(CAM_SMMU, + "[%s] : Discard region specified [0x%x 0x%x] in [0x%x 0x%x]", + cb->name[0], + cb->discard_iova_start, + cb->discard_iova_start + cb->discard_iova_len, + cb->io_info.iova_start, + cb->io_info.iova_start + cb->io_info.iova_len); + } + } + + of_node_put(mem_map_node); + + if (!num_regions) { + CAM_ERR(CAM_SMMU, + "No memory regions found, at least one needed"); + rc = -ENODEV; + } + + return rc; +} + +static int cam_populate_smmu_context_banks(struct device *dev, + enum cam_iommu_type type) +{ + int rc = 0; + struct cam_context_bank_info *cb; + struct device *ctx = NULL; + int i = 0; + + if (!dev) { + CAM_ERR(CAM_SMMU, "Error: Invalid device"); + return -ENODEV; + } + + /* check the bounds */ + if (iommu_cb_set.cb_init_count >= iommu_cb_set.cb_num) { + CAM_ERR(CAM_SMMU, "Error: populate more than allocated cb"); + rc = -EBADHANDLE; + goto cb_init_fail; + } + + /* read the context bank from cb set */ + cb = &iommu_cb_set.cb_info[iommu_cb_set.cb_init_count]; + + cb->is_mul_client = + of_property_read_bool(dev->of_node, "multiple-client-devices"); + + cb->num_shared_hdl = of_property_count_strings(dev->of_node, + "label"); + + if (cb->num_shared_hdl > + CAM_SMMU_SHARED_HDL_MAX) { + CAM_ERR(CAM_CDM, "Invalid count of client names count=%d", + cb->num_shared_hdl); + rc = -EINVAL; + return rc; + } + + /* set the name of the context bank */ + for (i = 0; i < cb->num_shared_hdl; i++) + rc = of_property_read_string_index(dev->of_node, + "label", i, &cb->name[i]); + if (rc < 0) { + CAM_ERR(CAM_SMMU, + "Error: failed to read label from sub device"); + goto cb_init_fail; + } + + rc = cam_smmu_get_memory_regions_info(dev->of_node, + cb); + if (rc < 0) { + CAM_ERR(CAM_SMMU, "Error: Getting region info"); + return rc; + } + + if (cb->is_secure) { + /* increment count to next bank */ + cb->dev = dev; + iommu_cb_set.cb_init_count++; + return 0; + } + + /* set up the iommu mapping for the context bank */ + if (type == CAM_QSMMU) { + CAM_ERR(CAM_SMMU, "Error: QSMMU ctx not supported for : %s", + cb->name[0]); + return -ENODEV; + } + + ctx = dev; + CAM_DBG(CAM_SMMU, "getting Arm SMMU ctx : %s", cb->name[0]); + + rc = cam_smmu_setup_cb(cb, ctx); + if (rc < 0) { + CAM_ERR(CAM_SMMU, "Error: failed to setup cb : %s", + cb->name[0]); + goto cb_init_fail; + } + if (cb->io_support && cb->domain) + iommu_set_fault_handler(cb->domain, + cam_smmu_iommu_fault_handler, + (void *)cb->name[0]); + + if (!dev->dma_parms) + dev->dma_parms = devm_kzalloc(dev, + sizeof(*dev->dma_parms), GFP_KERNEL); + + if (!dev->dma_parms) { + CAM_WARN(CAM_SMMU, + "Failed to allocate dma_params"); + dev->dma_parms = NULL; + goto end; + } + + dma_set_max_seg_size(dev, DMA_BIT_MASK(32)); + dma_set_seg_boundary(dev, (unsigned long)DMA_BIT_MASK(64)); + +end: + /* increment count to next bank */ + iommu_cb_set.cb_init_count++; + CAM_DBG(CAM_SMMU, "X: cb init count :%d", iommu_cb_set.cb_init_count); + +cb_init_fail: + return rc; +} + +static int cam_smmu_create_debug_fs(void) +{ + iommu_cb_set.dentry = debugfs_create_dir("camera_smmu", + NULL); + + if (!iommu_cb_set.dentry) { + CAM_ERR(CAM_SMMU, "failed to create dentry"); + return -ENOMEM; + } + + if (!debugfs_create_bool("cb_dump_enable", + 0644, + iommu_cb_set.dentry, + &iommu_cb_set.cb_dump_enable)) { + CAM_ERR(CAM_SMMU, + "failed to create dump_enable_debug"); + goto err; + } + + if (!debugfs_create_bool("map_profile_enable", + 0644, + iommu_cb_set.dentry, + &iommu_cb_set.map_profile_enable)) { + CAM_ERR(CAM_SMMU, + "failed to create map_profile_enable"); + goto err; + } + + return 0; +err: + debugfs_remove_recursive(iommu_cb_set.dentry); + return -ENOMEM; +} + +static int cam_smmu_probe(struct platform_device *pdev) +{ + int rc = 0; + struct device *dev = &pdev->dev; + + dev->dma_parms = NULL; + if (of_device_is_compatible(dev->of_node, "qcom,msm-cam-smmu")) { + rc = cam_alloc_smmu_context_banks(dev); + if (rc < 0) { + CAM_ERR(CAM_SMMU, "Error: allocating context banks"); + return -ENOMEM; + } + } + if (of_device_is_compatible(dev->of_node, "qcom,msm-cam-smmu-cb")) { + rc = cam_populate_smmu_context_banks(dev, CAM_ARM_SMMU); + if (rc < 0) { + CAM_ERR(CAM_SMMU, "Error: populating context banks"); + cam_smmu_release_cb(pdev); + return -ENOMEM; + } + return rc; + } + if (of_device_is_compatible(dev->of_node, "qcom,qsmmu-cam-cb")) { + rc = cam_populate_smmu_context_banks(dev, CAM_QSMMU); + if (rc < 0) { + CAM_ERR(CAM_SMMU, "Error: populating context banks"); + return -ENOMEM; + } + return rc; + } + + if (of_device_is_compatible(dev->of_node, "qcom,msm-cam-smmu-fw-dev")) { + icp_fw.fw_dev = &pdev->dev; + icp_fw.fw_kva = NULL; + icp_fw.fw_dma_hdl = 0; + return rc; + } + + /* probe through all the subdevices */ + rc = of_platform_populate(pdev->dev.of_node, msm_cam_smmu_dt_match, + NULL, &pdev->dev); + if (rc < 0) { + CAM_ERR(CAM_SMMU, "Error: populating devices"); + } else { + INIT_WORK(&iommu_cb_set.smmu_work, cam_smmu_page_fault_work); + mutex_init(&iommu_cb_set.payload_list_lock); + INIT_LIST_HEAD(&iommu_cb_set.payload_list); + } + + cam_smmu_create_debug_fs(); + return rc; +} + +static int cam_smmu_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + /* release all the context banks and memory allocated */ + cam_smmu_reset_iommu_table(CAM_SMMU_TABLE_DEINIT); + if (dev && dev->dma_parms) { + devm_kfree(dev, dev->dma_parms); + dev->dma_parms = NULL; + } + + if (of_device_is_compatible(pdev->dev.of_node, "qcom,msm-cam-smmu")) + cam_smmu_release_cb(pdev); + + debugfs_remove_recursive(iommu_cb_set.dentry); + iommu_cb_set.dentry = NULL; + return 0; +} + +static struct platform_driver cam_smmu_driver = { + .probe = cam_smmu_probe, + .remove = cam_smmu_remove, + .driver = { + .name = "msm_cam_smmu", + .owner = THIS_MODULE, + .of_match_table = msm_cam_smmu_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_smmu_init_module(void) +{ + return platform_driver_register(&cam_smmu_driver); +} + +static void __exit cam_smmu_exit_module(void) +{ + platform_driver_unregister(&cam_smmu_driver); +} + +module_init(cam_smmu_init_module); +module_exit(cam_smmu_exit_module); +MODULE_DESCRIPTION("MSM Camera SMMU driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_smmu/cam_smmu_api.h b/techpack/camera-bengal/drivers/cam_smmu/cam_smmu_api.h new file mode 100644 index 0000000000000000000000000000000000000000..4a4a0d312f9d8ff3a1e32375edfd606fbf08fca3 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_smmu/cam_smmu_api.h @@ -0,0 +1,403 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_SMMU_API_H_ +#define _CAM_SMMU_API_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*Enum for possible CAM SMMU operations */ +enum cam_smmu_ops_param { + CAM_SMMU_ATTACH, + CAM_SMMU_DETACH, + CAM_SMMU_VOTE, + CAM_SMMU_DEVOTE, + CAM_SMMU_OPS_INVALID +}; + +enum cam_smmu_map_dir { + CAM_SMMU_MAP_READ, + CAM_SMMU_MAP_WRITE, + CAM_SMMU_MAP_RW, + CAM_SMMU_MAP_INVALID +}; + +enum cam_smmu_region_id { + CAM_SMMU_REGION_FIRMWARE, + CAM_SMMU_REGION_SHARED, + CAM_SMMU_REGION_SCRATCH, + CAM_SMMU_REGION_IO, + CAM_SMMU_REGION_SECHEAP, + CAM_SMMU_REGION_QDSS +}; + +/** + * @brief : Callback function type that gets called back on cam + * smmu page fault. + * + * @param domain : Iommu domain received in iommu page fault handler + * @param dev : Device received in iommu page fault handler + * @param iova : IOVA where page fault occurred + * @param flags : Flags received in iommu page fault handler + * @param token : Userdata given during callback registration + * @param buf_info : Closest mapped buffer info + */ +typedef void (*cam_smmu_client_page_fault_handler)(struct iommu_domain *domain, + struct device *dev, unsigned long iova, int flags, void *token, + uint32_t buf_info); + +/** + * @brief : Structure to store region information + * + * @param iova_start : Start address of region + * @param iova_len : length of region + * @param discard_iova_start : iova addr start from where should not be used + * @param discard_iova_len : length of discard iova region + */ +struct cam_smmu_region_info { + dma_addr_t iova_start; + size_t iova_len; + dma_addr_t discard_iova_start; + size_t discard_iova_len; +}; + +/** + * @brief : Gets an smmu handle + * + * @param identifier: Unique identifier to be used by clients which they + * should get from device tree. CAM SMMU driver will + * not enforce how this string is obtained and will + * only validate this against the list of permitted + * identifiers + * @param handle_ptr: Based on the indentifier, CAM SMMU drivier will + * fill the handle pointed by handle_ptr + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_get_handle(char *identifier, int *handle_ptr); + +/** + * @brief : Performs IOMMU operations + * + * @param handle: Handle to identify the CAM SMMU client (VFE, CPP, FD etc.) + * @param op : Operation to be performed. Can be either CAM_SMMU_ATTACH + * or CAM_SMMU_DETACH + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_ops(int handle, enum cam_smmu_ops_param op); + +/** + * @brief : Maps user space IOVA for calling driver + * + * @param handle: Handle to identify the CAM SMMU client (VFE, CPP, FD etc.) + * @param ion_fd: ION handle identifying the memory buffer. + * @param dis_delayed_unmap: Whether to disable Delayed Unmap feature + * for this mapping + * @dir : Mapping direction: which will traslate toDMA_BIDIRECTIONAL, + * DMA_TO_DEVICE or DMA_FROM_DEVICE + * @dma_addr : Pointer to physical address where mapped address will be + * returned if region_id is CAM_SMMU_REGION_IO. If region_id is + * CAM_SMMU_REGION_SHARED, dma_addr is used as an input parameter + * which specifies the cpu virtual address to map. + * @len_ptr : Length of buffer mapped returned by CAM SMMU driver. + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_map_user_iova(int handle, int ion_fd, bool dis_delayed_unmap, + enum cam_smmu_map_dir dir, dma_addr_t *dma_addr, size_t *len_ptr, + enum cam_smmu_region_id region_id); + +/** + * @brief : Maps kernel space IOVA for calling driver + * + * @param handle : Handle to identify the CAM SMMU client (VFE, CPP, FD etc.) + * @param buf : dma_buf allocated for kernel usage in mem_mgr + * @dir : Mapping direction: which will traslate toDMA_BIDIRECTIONAL, + * DMA_TO_DEVICE or DMA_FROM_DEVICE + * @dma_addr : Pointer to physical address where mapped address will be + * returned if region_id is CAM_SMMU_REGION_IO. If region_id is + * CAM_SMMU_REGION_SHARED, dma_addr is used as an input + * parameter which specifies the cpu virtual address to map. + * @len_ptr : Length of buffer mapped returned by CAM SMMU driver. + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_map_kernel_iova(int handle, + struct dma_buf *buf, enum cam_smmu_map_dir dir, + dma_addr_t *dma_addr, size_t *len_ptr, + enum cam_smmu_region_id region_id); + +/** + * @brief : Unmaps user space IOVA for calling driver + * + * @param handle: Handle to identify the CAMSMMU client (VFE, CPP, FD etc.) + * @param ion_fd: ION handle identifying the memory buffer. + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_unmap_user_iova(int handle, + int ion_fd, enum cam_smmu_region_id region_id); + +/** + * @brief : Unmaps kernel IOVA for calling driver + * + * @param handle: Handle to identify the CAMSMMU client (VFE, CPP, FD etc.) + * @param buf : dma_buf allocated for the kernel + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_unmap_kernel_iova(int handle, + struct dma_buf *buf, enum cam_smmu_region_id region_id); + +/** + * @brief : Allocates a scratch buffer + * + * This function allocates a scratch virtual buffer of length virt_len in the + * device virtual address space mapped to phys_len physically contiguous bytes + * in that device's SMMU. + * + * virt_len and phys_len are expected to be aligned to PAGE_SIZE and with each + * other, otherwise -EINVAL is returned. + * + * -EINVAL will be returned if virt_len is less than phys_len. + * + * Passing a too large phys_len might also cause failure if that much size is + * not available for allocation in a physically contiguous way. + * + * @param handle : Handle to identify the CAMSMMU client (VFE, CPP, FD etc.) + * @param dir : Direction of mapping which will translate to IOMMU_READ + * IOMMU_WRITE or a bit mask of both. + * @param paddr_ptr: Device virtual address that the client device will be + * able to read from/write to + * @param virt_len : Virtual length of the scratch buffer + * @param phys_len : Physical length of the scratch buffer + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ + +int cam_smmu_get_scratch_iova(int handle, + enum cam_smmu_map_dir dir, + dma_addr_t *paddr_ptr, + size_t virt_len, + size_t phys_len); + +/** + * @brief : Frees a scratch buffer + * + * This function frees a scratch buffer and releases the corresponding SMMU + * mappings. + * + * @param handle : Handle to identify the CAMSMMU client (IFE, ICP, etc.) + * @param paddr : Device virtual address of client's scratch buffer that + * will be freed. + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ + +int cam_smmu_put_scratch_iova(int handle, + dma_addr_t paddr); + +/** + *@brief : Destroys an smmu handle + * + * @param handle: Handle to identify the CAM SMMU client (VFE, CPP, FD etc.) + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_destroy_handle(int handle); + +/** + * @brief : Finds index by handle in the smmu client table + * + * @param handle: Handle to identify the CAM SMMU client (VFE, CPP, FD etc.) + * @return Index of SMMU client. Nagative in case of error. + */ +int cam_smmu_find_index_by_handle(int hdl); + +/** + * @brief : Registers smmu fault handler for client + * + * @param handle: Handle to identify the CAM SMMU client (VFE, CPP, FD etc.) + * @param handler_cb: It is triggered in IOMMU page fault + * @param token: It is input param when trigger page fault handler + */ +void cam_smmu_set_client_page_fault_handler(int handle, + cam_smmu_client_page_fault_handler handler_cb, void *token); + +/** + * @brief : Unregisters smmu fault handler for client + * + * @param handle: Handle to identify the CAM SMMU client (VFE, CPP, FD etc.) + * @param token: It is input param when trigger page fault handler + */ +void cam_smmu_unset_client_page_fault_handler(int handle, void *token); + +/** + * @brief Maps memory from an ION fd into IOVA space + * + * @param handle: SMMU handle identifying the context bank to map to + * @param ion_fd: ION fd of memory to map to + * @param paddr_ptr: Pointer IOVA address that will be returned + * @param len_ptr: Length of memory mapped + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_get_iova(int handle, int ion_fd, + dma_addr_t *paddr_ptr, size_t *len_ptr); + +/** + * @brief Maps memory from an ION fd into IOVA space + * + * @param handle: SMMU handle identifying the secure context bank to map to + * @param ion_fd: ION fd of memory to map to + * @param paddr_ptr: Pointer IOVA address that will be returned + * @param len_ptr: Length of memory mapped + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_get_stage2_iova(int handle, int ion_fd, + dma_addr_t *paddr_ptr, size_t *len_ptr); + +/** + * @brief Unmaps memory from context bank + * + * @param handle: SMMU handle identifying the context bank + * @param ion_fd: ION fd of memory to unmap + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_put_iova(int handle, int ion_fd); + +/** + * @brief Maps secure memory for SMMU handle + * + * @param handle: SMMU handle identifying secure context bank + * @param ion_fd: ION fd to map securely + * @param dir: DMA Direction for the mapping + * @param dma_addr: Returned IOVA address after mapping + * @param len_ptr: Length of memory mapped + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_map_stage2_iova(int handle, + int ion_fd, enum cam_smmu_map_dir dir, dma_addr_t *dma_addr, + size_t *len_ptr); + +/** + * @brief Unmaps secure memopry for SMMU handle + * + * @param handle: SMMU handle identifying secure context bank + * @param ion_fd: ION fd to unmap + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_unmap_stage2_iova(int handle, int ion_fd); + +/** + * @brief Allocates firmware for context bank + * + * @param smmu_hdl: SMMU handle identifying context bank + * @param iova: IOVA address of allocated firmware + * @param kvaddr: CPU mapped address of allocated firmware + * @param len: Length of allocated firmware memory + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_alloc_firmware(int32_t smmu_hdl, + dma_addr_t *iova, + uintptr_t *kvaddr, + size_t *len); + +/** + * @brief Deallocates firmware memory for context bank + * + * @param smmu_hdl: SMMU handle identifying the context bank + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_dealloc_firmware(int32_t smmu_hdl); + +/** + * @brief Gets region information specified by smmu handle and region id + * + * @param smmu_hdl: SMMU handle identifying the context bank + * @param region_id: Region id for which information is desired + * @param region_info: Struct populated with region information + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_get_region_info(int32_t smmu_hdl, + enum cam_smmu_region_id region_id, + struct cam_smmu_region_info *region_info); + +/** + * @brief Reserves secondary heap + * + * @param smmu_hdl: SMMU handle identifying the context bank + * @param iova: IOVA of secondary heap after reservation has completed + * @param buf: Allocated dma_buf for secondary heap + * @param request_len: Length of secondary heap after reservation has completed + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_reserve_sec_heap(int32_t smmu_hdl, + struct dma_buf *buf, + dma_addr_t *iova, + size_t *request_len); + +/** + * @brief Releases secondary heap + * + * @param smmu_hdl: SMMU handle identifying the context bank + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_release_sec_heap(int32_t smmu_hdl); + +/** + * @brief Allocates qdss for context bank + * + * @param smmu_hdl: SMMU handle identifying context bank + * @param iova: IOVA address of allocated qdss + * @param len: Length of allocated qdss memory + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_alloc_qdss(int32_t smmu_hdl, + dma_addr_t *iova, + size_t *len); + +/** + * @brief Deallocates qdss memory for context bank + * + * @param smmu_hdl: SMMU handle identifying the context bank + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_dealloc_qdss(int32_t smmu_hdl); + +/** + * @brief Get start addr & len of I/O region for a given cb + * + * @param smmu_hdl: SMMU handle identifying the context bank + * @param iova: IOVA address of allocated I/O region + * @param len: Length of allocated I/O memory + * @param discard_iova_start: Start address of io space to discard + * @param discard_iova_len: Length of io space to discard + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_smmu_get_io_region_info(int32_t smmu_hdl, + dma_addr_t *iova, size_t *len, + dma_addr_t *discard_iova_start, size_t *discard_iova_len); + +#endif /* _CAM_SMMU_API_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_sync/Makefile b/techpack/camera-bengal/drivers/cam_sync/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..a380d8cd58e153d4778178972eec312153cfb23d --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sync/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-$(CONFIG_MSM_GLOBAL_SYNX) += -I$(srctree)/drivers/media/platform/msm/synx +ccflags-y += -I$(src) + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_sync.o cam_sync_util.o diff --git a/techpack/camera-bengal/drivers/cam_sync/cam_sync.c b/techpack/camera-bengal/drivers/cam_sync/cam_sync.c new file mode 100644 index 0000000000000000000000000000000000000000..d548933f23205bc9ccc135642dad21b94bc0e0b7 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sync/cam_sync.c @@ -0,0 +1,1192 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "cam_sync_util.h" +#include "cam_debug_util.h" +#include "cam_common_util.h" +#include "cam_req_mgr_workq.h" + +#ifdef CONFIG_MSM_GLOBAL_SYNX +#include +#endif +struct sync_device *sync_dev; + +/* + * Flag to determine whether to enqueue cb of a + * signaled fence onto the workq or invoke it + * directly in the same context + */ +static bool trigger_cb_without_switch; + +static void cam_sync_print_fence_table(void) +{ + int idx; + + for (idx = 0; idx < CAM_SYNC_MAX_OBJS; idx++) { + spin_lock_bh(&sync_dev->row_spinlocks[idx]); + CAM_INFO(CAM_SYNC, + "index[%u]: sync_id=%d, name=%s, type=%d, state=%d, ref_cnt=%d", + idx, + sync_dev->sync_table[idx].sync_id, + sync_dev->sync_table[idx].name, + sync_dev->sync_table[idx].type, + sync_dev->sync_table[idx].state, + atomic_read(&sync_dev->sync_table[idx].ref_cnt)); + spin_unlock_bh(&sync_dev->row_spinlocks[idx]); + } +} + +int cam_sync_create(int32_t *sync_obj, const char *name) +{ + int rc; + long idx; + bool bit; + + do { + idx = find_first_zero_bit(sync_dev->bitmap, CAM_SYNC_MAX_OBJS); + if (idx >= CAM_SYNC_MAX_OBJS) { + CAM_ERR(CAM_SYNC, + "Error: Unable to create sync idx = %d reached max!", + idx); + cam_sync_print_fence_table(); + return -ENOMEM; + } + CAM_DBG(CAM_SYNC, "Index location available at idx: %ld", idx); + bit = test_and_set_bit(idx, sync_dev->bitmap); + } while (bit); + + spin_lock_bh(&sync_dev->row_spinlocks[idx]); + rc = cam_sync_init_row(sync_dev->sync_table, idx, name, + CAM_SYNC_TYPE_INDV); + if (rc) { + CAM_ERR(CAM_SYNC, "Error: Unable to init row at idx = %ld", + idx); + clear_bit(idx, sync_dev->bitmap); + spin_unlock_bh(&sync_dev->row_spinlocks[idx]); + return -EINVAL; + } + + *sync_obj = idx; + CAM_DBG(CAM_SYNC, "sync_obj: %i", *sync_obj); + spin_unlock_bh(&sync_dev->row_spinlocks[idx]); + + return rc; +} + +int cam_sync_register_callback(sync_callback cb_func, + void *userdata, int32_t sync_obj) +{ + struct sync_callback_info *sync_cb; + struct sync_table_row *row = NULL; + int status = 0; + + if (sync_obj >= CAM_SYNC_MAX_OBJS || sync_obj <= 0 || !cb_func) + return -EINVAL; + + spin_lock_bh(&sync_dev->row_spinlocks[sync_obj]); + row = sync_dev->sync_table + sync_obj; + + if (row->state == CAM_SYNC_STATE_INVALID) { + CAM_ERR(CAM_SYNC, + "Error: accessing an uninitialized sync obj %d", + sync_obj); + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + return -EINVAL; + } + + sync_cb = kzalloc(sizeof(*sync_cb), GFP_ATOMIC); + if (!sync_cb) { + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + return -ENOMEM; + } + + /* Trigger callback if sync object is already in SIGNALED state */ + if ((row->state == CAM_SYNC_STATE_SIGNALED_SUCCESS || + row->state == CAM_SYNC_STATE_SIGNALED_ERROR) && + (!row->remaining)) { + if (trigger_cb_without_switch) { + CAM_DBG(CAM_SYNC, "Invoke callback for sync object:%d", + sync_obj); + status = row->state; + kfree(sync_cb); + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + cb_func(sync_obj, status, userdata); + } else { + sync_cb->callback_func = cb_func; + sync_cb->cb_data = userdata; + sync_cb->sync_obj = sync_obj; + INIT_WORK(&sync_cb->cb_dispatch_work, + cam_sync_util_cb_dispatch); + sync_cb->status = row->state; + CAM_DBG(CAM_SYNC, "Enqueue callback for sync object:%d", + sync_cb->sync_obj); + sync_cb->workq_scheduled_ts = ktime_get(); + queue_work(sync_dev->work_queue, + &sync_cb->cb_dispatch_work); + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + } + + return 0; + } + + sync_cb->callback_func = cb_func; + sync_cb->cb_data = userdata; + sync_cb->sync_obj = sync_obj; + INIT_WORK(&sync_cb->cb_dispatch_work, cam_sync_util_cb_dispatch); + list_add_tail(&sync_cb->list, &row->callback_list); + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + + return 0; +} + +int cam_sync_deregister_callback(sync_callback cb_func, + void *userdata, int32_t sync_obj) +{ + struct sync_table_row *row = NULL; + struct sync_callback_info *sync_cb, *temp; + bool found = false; + + if (sync_obj >= CAM_SYNC_MAX_OBJS || sync_obj <= 0) + return -EINVAL; + + spin_lock_bh(&sync_dev->row_spinlocks[sync_obj]); + row = sync_dev->sync_table + sync_obj; + + if (row->state == CAM_SYNC_STATE_INVALID) { + CAM_ERR(CAM_SYNC, + "Error: accessing an uninitialized sync obj = %d", + sync_obj); + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + return -EINVAL; + } + + CAM_DBG(CAM_SYNC, "deregistered callback for sync object:%d", + sync_obj); + list_for_each_entry_safe(sync_cb, temp, &row->callback_list, list) { + if (sync_cb->callback_func == cb_func && + sync_cb->cb_data == userdata) { + list_del_init(&sync_cb->list); + kfree(sync_cb); + found = true; + } + } + + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + return found ? 0 : -ENOENT; +} + +int cam_sync_signal(int32_t sync_obj, uint32_t status) +{ + struct sync_table_row *row = NULL; + struct sync_table_row *parent_row = NULL; + struct sync_parent_info *parent_info, *temp_parent_info; + struct list_head parents_list; + int rc = 0; + + if (sync_obj >= CAM_SYNC_MAX_OBJS || sync_obj <= 0) { + CAM_ERR(CAM_SYNC, "Error: Out of range sync obj (0 <= %d < %d)", + sync_obj, CAM_SYNC_MAX_OBJS); + return -EINVAL; + } + row = sync_dev->sync_table + sync_obj; + spin_lock_bh(&sync_dev->row_spinlocks[sync_obj]); + if (row->state == CAM_SYNC_STATE_INVALID) { + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + CAM_ERR(CAM_SYNC, + "Error: accessing an uninitialized sync obj = %d", + sync_obj); + return -EINVAL; + } + + if (row->type == CAM_SYNC_TYPE_GROUP) { + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + CAM_ERR(CAM_SYNC, + "Error: Signaling a GROUP sync object = %d", + sync_obj); + return -EINVAL; + } + + if (row->state != CAM_SYNC_STATE_ACTIVE) { + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + CAM_ERR(CAM_SYNC, + "Error: Sync object already signaled sync_obj = %d", + sync_obj); + return -EALREADY; + } + + if (status != CAM_SYNC_STATE_SIGNALED_SUCCESS && + status != CAM_SYNC_STATE_SIGNALED_ERROR) { + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + CAM_ERR(CAM_SYNC, + "Error: signaling with undefined status = %d", + status); + return -EINVAL; + } + + if (!atomic_dec_and_test(&row->ref_cnt)) { + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + return 0; + } + + row->state = status; + cam_sync_util_dispatch_signaled_cb(sync_obj, status); + + /* copy parent list to local and release child lock */ + INIT_LIST_HEAD(&parents_list); + list_splice_init(&row->parents_list, &parents_list); + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + + if (list_empty(&parents_list)) + return 0; + + /* + * Now iterate over all parents of this object and if they too need to + * be signaled dispatch cb's + */ + list_for_each_entry_safe(parent_info, + temp_parent_info, + &parents_list, + list) { + parent_row = sync_dev->sync_table + parent_info->sync_id; + spin_lock_bh(&sync_dev->row_spinlocks[parent_info->sync_id]); + parent_row->remaining--; + + rc = cam_sync_util_update_parent_state( + parent_row, + status); + if (rc) { + CAM_ERR(CAM_SYNC, "Invalid parent state %d", + parent_row->state); + spin_unlock_bh( + &sync_dev->row_spinlocks[parent_info->sync_id]); + kfree(parent_info); + continue; + } + + if (!parent_row->remaining) + cam_sync_util_dispatch_signaled_cb( + parent_info->sync_id, parent_row->state); + + spin_unlock_bh(&sync_dev->row_spinlocks[parent_info->sync_id]); + list_del_init(&parent_info->list); + kfree(parent_info); + } + + return 0; +} + +int cam_sync_merge(int32_t *sync_obj, uint32_t num_objs, int32_t *merged_obj) +{ + int rc; + long idx = 0; + bool bit; + int i = 0; + + if (!sync_obj || !merged_obj) { + CAM_ERR(CAM_SYNC, "Invalid pointer(s)"); + return -EINVAL; + } + + if (num_objs <= 1) { + CAM_ERR(CAM_SYNC, "Single object merge is not allowed"); + return -EINVAL; + } + + if (cam_common_util_remove_duplicate_arr(sync_obj, num_objs) + != num_objs) { + CAM_ERR(CAM_SYNC, "The obj list has duplicate fence"); + return -EINVAL; + } + + for (i = 0; i < num_objs; i++) { + rc = cam_sync_check_valid(sync_obj[i]); + if (rc) { + CAM_ERR(CAM_SYNC, "Sync_obj[%d] %d valid check fail", + i, sync_obj[i]); + return rc; + } + } + do { + idx = find_first_zero_bit(sync_dev->bitmap, CAM_SYNC_MAX_OBJS); + if (idx >= CAM_SYNC_MAX_OBJS) + return -ENOMEM; + bit = test_and_set_bit(idx, sync_dev->bitmap); + } while (bit); + + spin_lock_bh(&sync_dev->row_spinlocks[idx]); + rc = cam_sync_init_group_object(sync_dev->sync_table, + idx, sync_obj, + num_objs); + if (rc < 0) { + CAM_ERR(CAM_SYNC, "Error: Unable to init row at idx = %ld", + idx); + clear_bit(idx, sync_dev->bitmap); + spin_unlock_bh(&sync_dev->row_spinlocks[idx]); + return -EINVAL; + } + CAM_DBG(CAM_SYNC, "Init row at idx:%ld to merge objects", idx); + *merged_obj = idx; + spin_unlock_bh(&sync_dev->row_spinlocks[idx]); + + return 0; +} + +int cam_sync_get_obj_ref(int32_t sync_obj) +{ + struct sync_table_row *row = NULL; + + if (sync_obj >= CAM_SYNC_MAX_OBJS || sync_obj <= 0) + return -EINVAL; + + row = sync_dev->sync_table + sync_obj; + + spin_lock(&sync_dev->row_spinlocks[sync_obj]); + + if (row->state != CAM_SYNC_STATE_ACTIVE) { + spin_unlock(&sync_dev->row_spinlocks[sync_obj]); + CAM_ERR(CAM_SYNC, + "Error: accessing an uninitialized sync obj = %d", + sync_obj); + return -EINVAL; + } + + atomic_inc(&row->ref_cnt); + spin_unlock(&sync_dev->row_spinlocks[sync_obj]); + CAM_DBG(CAM_SYNC, "get ref for obj %d", sync_obj); + + return 0; +} + +int cam_sync_put_obj_ref(int32_t sync_obj) +{ + struct sync_table_row *row = NULL; + + if (sync_obj >= CAM_SYNC_MAX_OBJS || sync_obj <= 0) + return -EINVAL; + + row = sync_dev->sync_table + sync_obj; + atomic_dec(&row->ref_cnt); + CAM_DBG(CAM_SYNC, "put ref for obj %d", sync_obj); + + return 0; +} + +int cam_sync_destroy(int32_t sync_obj) +{ + CAM_DBG(CAM_SYNC, "sync_obj: %i", sync_obj); + return cam_sync_deinit_object(sync_dev->sync_table, sync_obj); +} + +int cam_sync_check_valid(int32_t sync_obj) +{ + struct sync_table_row *row = NULL; + + if (sync_obj >= CAM_SYNC_MAX_OBJS || sync_obj <= 0) + return -EINVAL; + + row = sync_dev->sync_table + sync_obj; + + if (!test_bit(sync_obj, sync_dev->bitmap)) { + CAM_ERR(CAM_SYNC, "Error: Released sync obj received %d", + sync_obj); + return -EINVAL; + } + + if (row->state == CAM_SYNC_STATE_INVALID) { + CAM_ERR(CAM_SYNC, + "Error: accessing an uninitialized sync obj = %d", + sync_obj); + return -EINVAL; + } + return 0; +} + +int cam_sync_wait(int32_t sync_obj, uint64_t timeout_ms) +{ + unsigned long timeleft; + int rc = -EINVAL; + struct sync_table_row *row = NULL; + + if (sync_obj >= CAM_SYNC_MAX_OBJS || sync_obj <= 0) + return -EINVAL; + + row = sync_dev->sync_table + sync_obj; + + if (row->state == CAM_SYNC_STATE_INVALID) { + CAM_ERR(CAM_SYNC, + "Error: accessing an uninitialized sync obj = %d", + sync_obj); + return -EINVAL; + } + + timeleft = wait_for_completion_timeout(&row->signaled, + msecs_to_jiffies(timeout_ms)); + + if (!timeleft) { + CAM_ERR(CAM_SYNC, + "Error: timed out for sync obj = %d", sync_obj); + rc = -ETIMEDOUT; + } else { + switch (row->state) { + case CAM_SYNC_STATE_INVALID: + case CAM_SYNC_STATE_ACTIVE: + case CAM_SYNC_STATE_SIGNALED_ERROR: + CAM_ERR(CAM_SYNC, + "Error: Wait on invalid state = %d, obj = %d", + row->state, sync_obj); + rc = -EINVAL; + break; + case CAM_SYNC_STATE_SIGNALED_SUCCESS: + rc = 0; + break; + default: + rc = -EINVAL; + break; + } + } + + return rc; +} + +static int cam_sync_handle_create(struct cam_private_ioctl_arg *k_ioctl) +{ + struct cam_sync_info sync_create; + int result; + + if (k_ioctl->size != sizeof(struct cam_sync_info)) + return -EINVAL; + + if (!k_ioctl->ioctl_ptr) + return -EINVAL; + + if (copy_from_user(&sync_create, + u64_to_user_ptr(k_ioctl->ioctl_ptr), + k_ioctl->size)) + return -EFAULT; + sync_create.name[SYNC_DEBUG_NAME_LEN] = '\0'; + + result = cam_sync_create(&sync_create.sync_obj, + sync_create.name); + + if (!result) + if (copy_to_user( + u64_to_user_ptr(k_ioctl->ioctl_ptr), + &sync_create, + k_ioctl->size)) + return -EFAULT; + + return result; +} + +static int cam_sync_handle_signal(struct cam_private_ioctl_arg *k_ioctl) +{ + int rc = 0; + struct cam_sync_signal sync_signal; + + if (k_ioctl->size != sizeof(struct cam_sync_signal)) + return -EINVAL; + + if (!k_ioctl->ioctl_ptr) + return -EINVAL; + + if (copy_from_user(&sync_signal, + u64_to_user_ptr(k_ioctl->ioctl_ptr), + k_ioctl->size)) + return -EFAULT; + + /* need to get ref for UMD signaled fences */ + rc = cam_sync_get_obj_ref(sync_signal.sync_obj); + if (rc) { + CAM_DBG(CAM_SYNC, + "Error: cannot signal an uninitialized sync obj = %d", + sync_signal.sync_obj); + return rc; + } + + return cam_sync_signal(sync_signal.sync_obj, + sync_signal.sync_state); +} + +static int cam_sync_handle_merge(struct cam_private_ioctl_arg *k_ioctl) +{ + struct cam_sync_merge sync_merge; + uint32_t *sync_objs; + uint32_t num_objs; + uint32_t size; + int result; + + if (k_ioctl->size != sizeof(struct cam_sync_merge)) + return -EINVAL; + + if (!k_ioctl->ioctl_ptr) + return -EINVAL; + + if (copy_from_user(&sync_merge, + u64_to_user_ptr(k_ioctl->ioctl_ptr), + k_ioctl->size)) + return -EFAULT; + + if (sync_merge.num_objs >= CAM_SYNC_MAX_OBJS) + return -EINVAL; + + size = sizeof(uint32_t) * sync_merge.num_objs; + sync_objs = kzalloc(size, GFP_ATOMIC); + + if (!sync_objs) + return -ENOMEM; + + if (copy_from_user(sync_objs, + u64_to_user_ptr(sync_merge.sync_objs), + sizeof(uint32_t) * sync_merge.num_objs)) { + kfree(sync_objs); + return -EFAULT; + } + + num_objs = sync_merge.num_objs; + + result = cam_sync_merge(sync_objs, + num_objs, + &sync_merge.merged); + + if (!result) + if (copy_to_user( + u64_to_user_ptr(k_ioctl->ioctl_ptr), + &sync_merge, + k_ioctl->size)) { + kfree(sync_objs); + return -EFAULT; + } + + kfree(sync_objs); + + return result; +} + +static int cam_sync_handle_wait(struct cam_private_ioctl_arg *k_ioctl) +{ + struct cam_sync_wait sync_wait; + + if (k_ioctl->size != sizeof(struct cam_sync_wait)) + return -EINVAL; + + if (!k_ioctl->ioctl_ptr) + return -EINVAL; + + if (copy_from_user(&sync_wait, + u64_to_user_ptr(k_ioctl->ioctl_ptr), + k_ioctl->size)) + return -EFAULT; + + k_ioctl->result = cam_sync_wait(sync_wait.sync_obj, + sync_wait.timeout_ms); + + return 0; +} + +static int cam_sync_handle_destroy(struct cam_private_ioctl_arg *k_ioctl) +{ + struct cam_sync_info sync_create; + + if (k_ioctl->size != sizeof(struct cam_sync_info)) + return -EINVAL; + + if (!k_ioctl->ioctl_ptr) + return -EINVAL; + + if (copy_from_user(&sync_create, + u64_to_user_ptr(k_ioctl->ioctl_ptr), + k_ioctl->size)) + return -EFAULT; + + return cam_sync_destroy(sync_create.sync_obj); +} + +static int cam_sync_handle_register_user_payload( + struct cam_private_ioctl_arg *k_ioctl) +{ + struct cam_sync_userpayload_info userpayload_info; + struct sync_user_payload *user_payload_kernel; + struct sync_user_payload *user_payload_iter; + struct sync_user_payload *temp_upayload_kernel; + uint32_t sync_obj; + struct sync_table_row *row = NULL; + + if (k_ioctl->size != sizeof(struct cam_sync_userpayload_info)) + return -EINVAL; + + if (!k_ioctl->ioctl_ptr) + return -EINVAL; + + if (copy_from_user(&userpayload_info, + u64_to_user_ptr(k_ioctl->ioctl_ptr), + k_ioctl->size)) + return -EFAULT; + + sync_obj = userpayload_info.sync_obj; + if (sync_obj >= CAM_SYNC_MAX_OBJS || sync_obj <= 0) + return -EINVAL; + + user_payload_kernel = kzalloc(sizeof(*user_payload_kernel), GFP_KERNEL); + if (!user_payload_kernel) + return -ENOMEM; + + memcpy(user_payload_kernel->payload_data, + userpayload_info.payload, + CAM_SYNC_PAYLOAD_WORDS * sizeof(__u64)); + + spin_lock_bh(&sync_dev->row_spinlocks[sync_obj]); + row = sync_dev->sync_table + sync_obj; + + if (row->state == CAM_SYNC_STATE_INVALID) { + CAM_ERR(CAM_SYNC, + "Error: accessing an uninitialized sync obj = %d", + sync_obj); + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + kfree(user_payload_kernel); + return -EINVAL; + } + + if (row->state == CAM_SYNC_STATE_SIGNALED_SUCCESS || + row->state == CAM_SYNC_STATE_SIGNALED_ERROR) { + + cam_sync_util_send_v4l2_event(CAM_SYNC_V4L_EVENT_ID_CB_TRIG, + sync_obj, + row->state, + user_payload_kernel->payload_data, + CAM_SYNC_USER_PAYLOAD_SIZE * sizeof(__u64)); + + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + kfree(user_payload_kernel); + return 0; + } + + list_for_each_entry_safe(user_payload_iter, + temp_upayload_kernel, + &row->user_payload_list, + list) { + if (user_payload_iter->payload_data[0] == + user_payload_kernel->payload_data[0] && + user_payload_iter->payload_data[1] == + user_payload_kernel->payload_data[1]) { + + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + kfree(user_payload_kernel); + return -EALREADY; + } + } + + list_add_tail(&user_payload_kernel->list, &row->user_payload_list); + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + return 0; +} + +static int cam_sync_handle_deregister_user_payload( + struct cam_private_ioctl_arg *k_ioctl) +{ + struct cam_sync_userpayload_info userpayload_info; + struct sync_user_payload *user_payload_kernel, *temp; + uint32_t sync_obj; + struct sync_table_row *row = NULL; + + if (k_ioctl->size != sizeof(struct cam_sync_userpayload_info)) { + CAM_ERR(CAM_SYNC, "Incorrect ioctl size"); + return -EINVAL; + } + + if (!k_ioctl->ioctl_ptr) { + CAM_ERR(CAM_SYNC, "Invalid embedded ioctl ptr"); + return -EINVAL; + } + + if (copy_from_user(&userpayload_info, + u64_to_user_ptr(k_ioctl->ioctl_ptr), + k_ioctl->size)) + return -EFAULT; + + sync_obj = userpayload_info.sync_obj; + if (sync_obj >= CAM_SYNC_MAX_OBJS || sync_obj <= 0) + return -EINVAL; + + spin_lock_bh(&sync_dev->row_spinlocks[sync_obj]); + row = sync_dev->sync_table + sync_obj; + + if (row->state == CAM_SYNC_STATE_INVALID) { + CAM_ERR(CAM_SYNC, + "Error: accessing an uninitialized sync obj = %d", + sync_obj); + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + return -EINVAL; + } + + list_for_each_entry_safe(user_payload_kernel, temp, + &row->user_payload_list, list) { + if (user_payload_kernel->payload_data[0] == + userpayload_info.payload[0] && + user_payload_kernel->payload_data[1] == + userpayload_info.payload[1]) { + list_del_init(&user_payload_kernel->list); + kfree(user_payload_kernel); + } + } + + spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); + return 0; +} + +static long cam_sync_dev_ioctl(struct file *filep, void *fh, + bool valid_prio, unsigned int cmd, void *arg) +{ + int32_t rc; + struct sync_device *sync_dev = video_drvdata(filep); + struct cam_private_ioctl_arg k_ioctl; + + if (!sync_dev) { + CAM_ERR(CAM_SYNC, "sync_dev NULL"); + return -EINVAL; + } + + if (!arg) + return -EINVAL; + + if (cmd != CAM_PRIVATE_IOCTL_CMD) + return -ENOIOCTLCMD; + + k_ioctl = *(struct cam_private_ioctl_arg *)arg; + + switch (k_ioctl.id) { + case CAM_SYNC_CREATE: + rc = cam_sync_handle_create(&k_ioctl); + break; + case CAM_SYNC_DESTROY: + rc = cam_sync_handle_destroy(&k_ioctl); + break; + case CAM_SYNC_REGISTER_PAYLOAD: + rc = cam_sync_handle_register_user_payload( + &k_ioctl); + break; + case CAM_SYNC_DEREGISTER_PAYLOAD: + rc = cam_sync_handle_deregister_user_payload( + &k_ioctl); + break; + case CAM_SYNC_SIGNAL: + rc = cam_sync_handle_signal(&k_ioctl); + break; + case CAM_SYNC_MERGE: + rc = cam_sync_handle_merge(&k_ioctl); + break; + case CAM_SYNC_WAIT: + rc = cam_sync_handle_wait(&k_ioctl); + ((struct cam_private_ioctl_arg *)arg)->result = + k_ioctl.result; + break; + default: + rc = -ENOIOCTLCMD; + } + + return rc; +} + +static unsigned int cam_sync_poll(struct file *f, + struct poll_table_struct *pll_table) +{ + int rc = 0; + struct v4l2_fh *eventq = f->private_data; + + if (!eventq) + return -EINVAL; + + poll_wait(f, &eventq->wait, pll_table); + + if (v4l2_event_pending(eventq)) + rc = POLLPRI; + + return rc; +} + +static int cam_sync_open(struct file *filep) +{ + int rc; + struct sync_device *sync_dev = video_drvdata(filep); + + if (!sync_dev) { + CAM_ERR(CAM_SYNC, "Sync device NULL"); + return -ENODEV; + } + + mutex_lock(&sync_dev->table_lock); + if (sync_dev->open_cnt >= 1) { + mutex_unlock(&sync_dev->table_lock); + return -EALREADY; + } + + rc = v4l2_fh_open(filep); + if (!rc) { + sync_dev->open_cnt++; + spin_lock_bh(&sync_dev->cam_sync_eventq_lock); + sync_dev->cam_sync_eventq = filep->private_data; + spin_unlock_bh(&sync_dev->cam_sync_eventq_lock); + } else { + CAM_ERR(CAM_SYNC, "v4l2_fh_open failed : %d", rc); + } + mutex_unlock(&sync_dev->table_lock); + + return rc; +} + +static int cam_sync_close(struct file *filep) +{ + int rc = 0; + int i; + struct sync_device *sync_dev = video_drvdata(filep); + + if (!sync_dev) { + CAM_ERR(CAM_SYNC, "Sync device NULL"); + rc = -ENODEV; + return rc; + } + mutex_lock(&sync_dev->table_lock); + sync_dev->open_cnt--; + if (!sync_dev->open_cnt) { + for (i = 1; i < CAM_SYNC_MAX_OBJS; i++) { + struct sync_table_row *row = + sync_dev->sync_table + i; + + /* + * Signal all ACTIVE objects as ERR, but we don't + * care about the return status here apart from logging + * it. + */ + if (row->state == CAM_SYNC_STATE_ACTIVE) { + rc = cam_sync_signal(i, + CAM_SYNC_STATE_SIGNALED_ERROR); + if (rc < 0) + CAM_ERR(CAM_SYNC, + "Cleanup signal fail idx:%d\n", + i); + } + } + + /* + * Flush the work queue to wait for pending signal callbacks to + * finish + */ + flush_workqueue(sync_dev->work_queue); + + /* + * Now that all callbacks worker threads have finished, + * destroy the sync objects + */ + for (i = 1; i < CAM_SYNC_MAX_OBJS; i++) { + struct sync_table_row *row = + sync_dev->sync_table + i; + + if (row->state != CAM_SYNC_STATE_INVALID) { + rc = cam_sync_destroy(i); + if (rc < 0) + CAM_ERR(CAM_SYNC, + "Cleanup destroy fail:idx:%d\n", + i); + } + } + } + mutex_unlock(&sync_dev->table_lock); + spin_lock_bh(&sync_dev->cam_sync_eventq_lock); + sync_dev->cam_sync_eventq = NULL; + spin_unlock_bh(&sync_dev->cam_sync_eventq_lock); + v4l2_fh_release(filep); + + return rc; +} + +static void cam_sync_event_queue_notify_error(const struct v4l2_event *old, + struct v4l2_event *new) +{ + struct cam_sync_ev_header *ev_header; + + ev_header = CAM_SYNC_GET_HEADER_PTR((*old)); + CAM_ERR(CAM_CRM, "Failed to notify event id %d fence %d statue %d", + old->id, ev_header->sync_obj, ev_header->status); +} + +static struct v4l2_subscribed_event_ops cam_sync_v4l2_ops = { + .merge = cam_sync_event_queue_notify_error, +}; + +int cam_sync_subscribe_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + return v4l2_event_subscribe(fh, sub, CAM_SYNC_MAX_V4L2_EVENTS, + &cam_sync_v4l2_ops); +} + +int cam_sync_unsubscribe_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + return v4l2_event_unsubscribe(fh, sub); +} + +static const struct v4l2_ioctl_ops g_cam_sync_ioctl_ops = { + .vidioc_subscribe_event = cam_sync_subscribe_event, + .vidioc_unsubscribe_event = cam_sync_unsubscribe_event, + .vidioc_default = cam_sync_dev_ioctl, +}; + +static struct v4l2_file_operations cam_sync_v4l2_fops = { + .owner = THIS_MODULE, + .open = cam_sync_open, + .release = cam_sync_close, + .poll = cam_sync_poll, + .unlocked_ioctl = video_ioctl2, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = video_ioctl2, +#endif +}; + +#if defined(CONFIG_MEDIA_CONTROLLER) +static int cam_sync_media_controller_init(struct sync_device *sync_dev, + struct platform_device *pdev) +{ + int rc; + + sync_dev->v4l2_dev.mdev = kzalloc(sizeof(struct media_device), + GFP_KERNEL); + if (!sync_dev->v4l2_dev.mdev) + return -ENOMEM; + + media_device_init(sync_dev->v4l2_dev.mdev); + strlcpy(sync_dev->v4l2_dev.mdev->model, CAM_SYNC_DEVICE_NAME, + sizeof(sync_dev->v4l2_dev.mdev->model)); + sync_dev->v4l2_dev.mdev->dev = &(pdev->dev); + + rc = media_device_register(sync_dev->v4l2_dev.mdev); + if (rc < 0) + goto register_fail; + + rc = media_entity_pads_init(&sync_dev->vdev->entity, 0, NULL); + if (rc < 0) + goto entity_fail; + + return 0; + +entity_fail: + media_device_unregister(sync_dev->v4l2_dev.mdev); +register_fail: + media_device_cleanup(sync_dev->v4l2_dev.mdev); + return rc; +} + +static void cam_sync_media_controller_cleanup(struct sync_device *sync_dev) +{ + media_entity_cleanup(&sync_dev->vdev->entity); + media_device_unregister(sync_dev->v4l2_dev.mdev); + media_device_cleanup(sync_dev->v4l2_dev.mdev); + kfree(sync_dev->v4l2_dev.mdev); +} + +static void cam_sync_init_entity(struct sync_device *sync_dev) +{ + sync_dev->vdev->entity.function = CAM_SYNC_DEVICE_TYPE; + sync_dev->vdev->entity.name = + video_device_node_name(sync_dev->vdev); +} +#else +static int cam_sync_media_controller_init(struct sync_device *sync_dev, + struct platform_device *pdev) +{ + return 0; +} + +static void cam_sync_media_controller_cleanup(struct sync_device *sync_dev) +{ +} + +static void cam_sync_init_entity(struct sync_device *sync_dev) +{ +} +#endif + +static int cam_sync_create_debugfs(void) +{ + sync_dev->dentry = debugfs_create_dir("camera_sync", NULL); + + if (!sync_dev->dentry) { + CAM_ERR(CAM_SYNC, "Failed to create sync dir"); + return -ENOMEM; + } + + if (!debugfs_create_bool("trigger_cb_without_switch", + 0644, sync_dev->dentry, + &trigger_cb_without_switch)) { + CAM_ERR(CAM_SYNC, + "failed to create trigger_cb_without_switch entry"); + return -ENOMEM; + } + + return 0; +} + +#ifdef CONFIG_MSM_GLOBAL_SYNX +static void cam_sync_register_synx_bind_ops(void) +{ + int rc = 0; + struct synx_register_params params; + + params.name = CAM_SYNC_NAME; + params.type = SYNX_TYPE_CSL; + params.ops.register_callback = cam_sync_register_callback; + params.ops.deregister_callback = cam_sync_deregister_callback; + params.ops.enable_signaling = cam_sync_get_obj_ref; + params.ops.signal = cam_sync_signal; + + rc = synx_register_ops(¶ms); + if (rc) + CAM_ERR(CAM_SYNC, "synx registration fail with %d", rc); +} +#endif + +static int cam_sync_probe(struct platform_device *pdev) +{ + int rc; + int idx; + + sync_dev = kzalloc(sizeof(*sync_dev), GFP_KERNEL); + if (!sync_dev) + return -ENOMEM; + + mutex_init(&sync_dev->table_lock); + spin_lock_init(&sync_dev->cam_sync_eventq_lock); + + for (idx = 0; idx < CAM_SYNC_MAX_OBJS; idx++) + spin_lock_init(&sync_dev->row_spinlocks[idx]); + + sync_dev->vdev = video_device_alloc(); + if (!sync_dev->vdev) { + rc = -ENOMEM; + goto vdev_fail; + } + + rc = cam_sync_media_controller_init(sync_dev, pdev); + if (rc < 0) + goto mcinit_fail; + + sync_dev->vdev->v4l2_dev = &sync_dev->v4l2_dev; + + rc = v4l2_device_register(&(pdev->dev), sync_dev->vdev->v4l2_dev); + if (rc < 0) + goto register_fail; + + strlcpy(sync_dev->vdev->name, CAM_SYNC_NAME, + sizeof(sync_dev->vdev->name)); + sync_dev->vdev->release = video_device_release; + sync_dev->vdev->fops = &cam_sync_v4l2_fops; + sync_dev->vdev->ioctl_ops = &g_cam_sync_ioctl_ops; + sync_dev->vdev->minor = -1; + sync_dev->vdev->vfl_type = VFL_TYPE_GRABBER; + rc = video_register_device(sync_dev->vdev, + VFL_TYPE_GRABBER, -1); + if (rc < 0) + goto v4l2_fail; + + cam_sync_init_entity(sync_dev); + video_set_drvdata(sync_dev->vdev, sync_dev); + memset(&sync_dev->sync_table, 0, sizeof(sync_dev->sync_table)); + memset(&sync_dev->bitmap, 0, sizeof(sync_dev->bitmap)); + bitmap_zero(sync_dev->bitmap, CAM_SYNC_MAX_OBJS); + + /* + * We treat zero as invalid handle, so we will keep the 0th bit set + * always + */ + set_bit(0, sync_dev->bitmap); + + sync_dev->work_queue = alloc_workqueue(CAM_SYNC_WORKQUEUE_NAME, + WQ_HIGHPRI | WQ_UNBOUND, 1); + + if (!sync_dev->work_queue) { + CAM_ERR(CAM_SYNC, + "Error: high priority work queue creation failed"); + rc = -ENOMEM; + goto v4l2_fail; + } + + trigger_cb_without_switch = false; + cam_sync_create_debugfs(); +#ifdef CONFIG_MSM_GLOBAL_SYNX + cam_sync_register_synx_bind_ops(); +#endif + return rc; + +v4l2_fail: + v4l2_device_unregister(sync_dev->vdev->v4l2_dev); +register_fail: + cam_sync_media_controller_cleanup(sync_dev); +mcinit_fail: + video_device_release(sync_dev->vdev); +vdev_fail: + mutex_destroy(&sync_dev->table_lock); + kfree(sync_dev); + return rc; +} + +static int cam_sync_remove(struct platform_device *pdev) +{ + v4l2_device_unregister(sync_dev->vdev->v4l2_dev); + cam_sync_media_controller_cleanup(sync_dev); + video_device_release(sync_dev->vdev); + debugfs_remove_recursive(sync_dev->dentry); + sync_dev->dentry = NULL; + kfree(sync_dev); + sync_dev = NULL; + + return 0; +} + +static struct platform_device cam_sync_device = { + .name = "cam_sync", + .id = -1, +}; + +static struct platform_driver cam_sync_driver = { + .probe = cam_sync_probe, + .remove = cam_sync_remove, + .driver = { + .name = "cam_sync", + .owner = THIS_MODULE, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_sync_init(void) +{ + int rc; + + rc = platform_device_register(&cam_sync_device); + if (rc) + return -ENODEV; + + return platform_driver_register(&cam_sync_driver); +} + +static void __exit cam_sync_exit(void) +{ + int idx; + + for (idx = 0; idx < CAM_SYNC_MAX_OBJS; idx++) + spin_lock_init(&sync_dev->row_spinlocks[idx]); + platform_driver_unregister(&cam_sync_driver); + platform_device_unregister(&cam_sync_device); + kfree(sync_dev); +} + +module_init(cam_sync_init); +module_exit(cam_sync_exit); +MODULE_DESCRIPTION("Camera sync driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/camera-bengal/drivers/cam_sync/cam_sync_api.h b/techpack/camera-bengal/drivers/cam_sync/cam_sync_api.h new file mode 100644 index 0000000000000000000000000000000000000000..3304acb50bbaa52de19c5bc08407357e67cc738b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sync/cam_sync_api.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __CAM_SYNC_API_H__ +#define __CAM_SYNC_API_H__ + +#include +#include +#include +#include +#include + +#define SYNC_DEBUG_NAME_LEN 63 +typedef void (*sync_callback)(int32_t sync_obj, int status, void *data); + +/* Kernel APIs */ + +/** + * @brief: Creates a sync object + * + * The newly created sync obj is assigned to sync_obj. + * sync object. + * + * @param sync_obj : Pointer to int referencing the sync object. + * @param name : Optional parameter associating a name with the sync object for + * debug purposes. Only first SYNC_DEBUG_NAME_LEN bytes are accepted, + * rest will be ignored. + * + * @return Status of operation. Zero in case of success. + * -EINVAL will be returned if sync_obj is an invalid pointer. + * -ENOMEM will be returned if the kernel can't allocate space for + * sync object. + */ +int cam_sync_create(int32_t *sync_obj, const char *name); + +/** + * @brief: Registers a callback with a sync object + * + * @param cb_func: Pointer to callback to be registered + * @param userdata: Opaque pointer which will be passed back with callback. + * @param sync_obj: int referencing the sync object. + * + * @return Status of operation. Zero in case of success. + * -EINVAL will be returned if userdata is invalid. + * -ENOMEM will be returned if cb_func is invalid. + * + */ +int cam_sync_register_callback(sync_callback cb_func, + void *userdata, int32_t sync_obj); + +/** + * @brief: De-registers a callback with a sync object + * + * @param cb_func: Pointer to callback to be de-registered + * @param userdata: Opaque pointer which will be passed back with callback. + * @param sync_obj: int referencing the sync object. + * + * @return Status of operation. Zero in case of success. + * -EINVAL will be returned if userdata is invalid. + * -ENOMEM will be returned if cb_func is invalid. + */ +int cam_sync_deregister_callback(sync_callback cb_func, + void *userdata, int32_t sync_obj); + +/** + * @brief: Signals a sync object with the status argument. + * + * This function will signal the sync object referenced by the sync_obj + * parameter and when doing so, will trigger callbacks in both user space and + * kernel. Callbacks will triggered asynchronously and their order of execution + * is not guaranteed. The status parameter will indicate whether the entity + * performing the signaling wants to convey an error case or a success case. + * + * @param sync_obj: int referencing the sync object. + * @param status: Status of the signaling. Can be either SYNC_SIGNAL_ERROR or + * SYNC_SIGNAL_SUCCESS. + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_sync_signal(int32_t sync_obj, uint32_t status); + +/** + * @brief: Merges multiple sync objects + * + * This function will merge multiple sync objects into a sync group. + * + * @param sync_obj: pointer to a block of ints to be merged + * @param num_objs: Number of ints in the block + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_sync_merge(int32_t *sync_obj, uint32_t num_objs, int32_t *merged_obj); + +/** + * @brief: get ref count of sync obj + * + * This function will increment ref count for the sync object, and the ref + * count will be decremented when this sync object is signaled. + * + * @param sync_obj: sync object + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_sync_get_obj_ref(int32_t sync_obj); + +/** + * @brief: put ref count of sync obj + * + * This function will decrement ref count for the sync object. + * + * @param sync_obj: sync object + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_sync_put_obj_ref(int32_t sync_obj); + +/** + * @brief: Destroys a sync object + * + * @param sync_obj: int referencing the sync object to be destroyed + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_sync_destroy(int32_t sync_obj); + +/** + * @brief: Waits for a sync object synchronously + * + * Does a wait on the sync object identified by sync_obj for a maximum + * of timeout_ms milliseconds. Must not be called from interrupt context as + * this API can sleep. Should be called from process context only. + * + * @param sync_obj: int referencing the sync object to be waited upon + * @timeout_ms sync_obj: Timeout in ms. + * + * @return 0 upon success, -EINVAL if sync object is in bad state or arguments + * are invalid, -ETIMEDOUT if wait times out. + */ +int cam_sync_wait(int32_t sync_obj, uint64_t timeout_ms); + +/** + * @brief: Check if sync object is valid + * + * @param sync_obj: int referencing the sync object to be checked + * + * @return 0 upon success, -EINVAL if sync object is in bad state or arguments + * are invalid + */ +int cam_sync_check_valid(int32_t sync_obj); + +#endif /* __CAM_SYNC_API_H__ */ diff --git a/techpack/camera-bengal/drivers/cam_sync/cam_sync_private.h b/techpack/camera-bengal/drivers/cam_sync/cam_sync_private.h new file mode 100644 index 0000000000000000000000000000000000000000..a77dc5f7f126ad25debee8d9d40cb577de1aff32 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sync/cam_sync_private.h @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __CAM_SYNC_PRIVATE_H__ +#define __CAM_SYNC_PRIVATE_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_CAM_SYNC_DBG +#define CDBG(fmt, args...) pr_err(fmt, ##args) +#else +#define CDBG(fmt, args...) pr_debug(fmt, ##args) +#endif + +#define CAM_SYNC_OBJ_NAME_LEN 64 +#define CAM_SYNC_MAX_OBJS 1024 +#define CAM_SYNC_MAX_V4L2_EVENTS 100 +#define CAM_SYNC_DEBUG_FILENAME "cam_debug" +#define CAM_SYNC_DEBUG_BASEDIR "cam" +#define CAM_SYNC_DEBUG_BUF_SIZE 32 +#define CAM_SYNC_PAYLOAD_WORDS 2 +#define CAM_SYNC_NAME "cam_sync" +#define CAM_SYNC_WORKQUEUE_NAME "HIPRIO_SYNC_WORK_QUEUE" + +#define CAM_SYNC_TYPE_INDV 0 +#define CAM_SYNC_TYPE_GROUP 1 + +/** + * enum sync_type - Enum to indicate the type of sync object, + * i.e. individual or group. + * + * @SYNC_TYPE_INDV : Object is an individual sync object + * @SYNC_TYPE_GROUP : Object is a group sync object + */ +enum sync_type { + SYNC_TYPE_INDV, + SYNC_TYPE_GROUP +}; + +/** + * enum sync_list_clean_type - Enum to indicate the type of list clean action + * to be peformed, i.e. specific sync ID or all list sync ids. + * + * @SYNC_CLEAN_ONE : Specific object to be cleaned in the list + * @SYNC_CLEAN_ALL : Clean all objects in the list + */ +enum sync_list_clean_type { + SYNC_LIST_CLEAN_ONE, + SYNC_LIST_CLEAN_ALL +}; + +/** + * struct sync_parent_info - Single node of information about a parent + * of a sync object, usually part of the parents linked list + * + * @sync_id : Sync object id of parent + * @list : List member used to append this node to a linked list + */ +struct sync_parent_info { + int32_t sync_id; + struct list_head list; +}; + +/** + * struct sync_parent_info - Single node of information about a child + * of a sync object, usually part of the children linked list + * + * @sync_id : Sync object id of child + * @list : List member used to append this node to a linked list + */ +struct sync_child_info { + int32_t sync_id; + struct list_head list; +}; + + +/** + * struct sync_callback_info - Single node of information about a kernel + * callback registered on a sync object + * + * @callback_func : Callback function, registered by client driver + * @cb_data : Callback data, registered by client driver + * @status : Status with which callback will be invoked in client + * @sync_obj : Sync id of the object for which callback is registered + * @workq_scheduled_ts : workqueue scheduled timestamp + * @cb_dispatch_work : Work representing the call dispatch + * @list : List member used to append this node to a linked list + */ +struct sync_callback_info { + sync_callback callback_func; + void *cb_data; + int status; + int32_t sync_obj; + ktime_t workq_scheduled_ts; + struct work_struct cb_dispatch_work; + struct list_head list; +}; + +/** + * struct sync_user_payload - Single node of information about a user space + * payload registered from user space + * + * @payload_data : Payload data, opaque to kernel + * @list : List member used to append this node to a linked list + */ +struct sync_user_payload { + uint64_t payload_data[CAM_SYNC_PAYLOAD_WORDS]; + struct list_head list; +}; + +/** + * struct sync_table_row - Single row of information about a sync object, used + * for internal book keeping in the sync driver + * + * @name : Optional string representation of the sync object + * @type : Type of the sync object (individual or group) + * @sync_id : Integer id representing this sync object + * @parents_list : Linked list of parents of this sync object + * @children_list : Linked list of children of this sync object + * @state : State (INVALID, ACTIVE, SIGNALED_SUCCESS or + * SIGNALED_ERROR) + * @remaining : Count of remaining children that not been signaled + * @signaled : Completion variable on which block calls will wait + * @callback_list : Linked list of kernel callbacks registered + * @user_payload_list : LInked list of user space payloads registered + * @ref_cnt : ref count of the number of usage of the fence. + */ +struct sync_table_row { + char name[CAM_SYNC_OBJ_NAME_LEN]; + enum sync_type type; + int32_t sync_id; + /* List of parents, which are merged objects */ + struct list_head parents_list; + /* List of children, which constitute the merged object */ + struct list_head children_list; + uint32_t state; + uint32_t remaining; + struct completion signaled; + struct list_head callback_list; + struct list_head user_payload_list; + atomic_t ref_cnt; +}; + +/** + * struct cam_signalable_info - Information for a single sync object that is + * ready to be signaled + * + * @sync_obj : Sync object id of signalable object + * @status : Status with which to signal + * @list : List member used to append this node to a linked list + */ +struct cam_signalable_info { + int32_t sync_obj; + uint32_t status; + struct list_head list; +}; + +/** + * struct sync_device - Internal struct to book keep sync driver details + * + * @vdev : Video device + * @v4l2_dev : V4L2 device + * @sync_table : Table of all sync objects + * @row_spinlocks : Spinlock array, one for each row in the table + * @table_lock : Mutex used to lock the table + * @open_cnt : Count of file open calls made on the sync driver + * @dentry : Debugfs entry + * @work_queue : Work queue used for dispatching kernel callbacks + * @cam_sync_eventq : Event queue used to dispatch user payloads to user space + * @bitmap : Bitmap representation of all sync objects + */ +struct sync_device { + struct video_device *vdev; + struct v4l2_device v4l2_dev; + struct sync_table_row sync_table[CAM_SYNC_MAX_OBJS]; + spinlock_t row_spinlocks[CAM_SYNC_MAX_OBJS]; + struct mutex table_lock; + int open_cnt; + struct dentry *dentry; + struct workqueue_struct *work_queue; + struct v4l2_fh *cam_sync_eventq; + spinlock_t cam_sync_eventq_lock; + DECLARE_BITMAP(bitmap, CAM_SYNC_MAX_OBJS); +}; + + +#endif /* __CAM_SYNC_PRIVATE_H__ */ diff --git a/techpack/camera-bengal/drivers/cam_sync/cam_sync_util.c b/techpack/camera-bengal/drivers/cam_sync/cam_sync_util.c new file mode 100644 index 0000000000000000000000000000000000000000..f632212ac7965941204644f5aac53be81f029520 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sync/cam_sync_util.c @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#include "cam_sync_util.h" +#include "cam_req_mgr_workq.h" + +int cam_sync_util_find_and_set_empty_row(struct sync_device *sync_dev, + long *idx) +{ + int rc = 0; + + mutex_lock(&sync_dev->table_lock); + + *idx = find_first_zero_bit(sync_dev->bitmap, CAM_SYNC_MAX_OBJS); + + if (*idx < CAM_SYNC_MAX_OBJS) + set_bit(*idx, sync_dev->bitmap); + else + rc = -1; + + mutex_unlock(&sync_dev->table_lock); + + return rc; +} + +int cam_sync_init_row(struct sync_table_row *table, + uint32_t idx, const char *name, uint32_t type) +{ + struct sync_table_row *row = table + idx; + + if (!table || idx <= 0 || idx >= CAM_SYNC_MAX_OBJS) + return -EINVAL; + + memset(row, 0, sizeof(*row)); + + if (name) + strlcpy(row->name, name, SYNC_DEBUG_NAME_LEN); + INIT_LIST_HEAD(&row->parents_list); + INIT_LIST_HEAD(&row->children_list); + row->type = type; + row->sync_id = idx; + row->state = CAM_SYNC_STATE_ACTIVE; + row->remaining = 0; + atomic_set(&row->ref_cnt, 0); + init_completion(&row->signaled); + INIT_LIST_HEAD(&row->callback_list); + INIT_LIST_HEAD(&row->user_payload_list); + CAM_DBG(CAM_SYNC, + "row name:%s sync_id:%i [idx:%u] row_state:%u ", + row->name, row->sync_id, idx, row->state); + + return 0; +} + +int cam_sync_init_group_object(struct sync_table_row *table, + uint32_t idx, + uint32_t *sync_objs, + uint32_t num_objs) +{ + int i, rc = 0; + struct sync_child_info *child_info; + struct sync_parent_info *parent_info; + struct sync_table_row *row = table + idx; + struct sync_table_row *child_row = NULL; + + cam_sync_init_row(table, idx, "merged_fence", CAM_SYNC_TYPE_GROUP); + + /* + * While traversing for children, parent's row list is updated with + * child info and each child's row is updated with parent info. + * If any child state is ERROR or SUCCESS, it will not be added to list. + */ + for (i = 0; i < num_objs; i++) { + child_row = table + sync_objs[i]; + spin_lock_bh(&sync_dev->row_spinlocks[sync_objs[i]]); + + /* validate child */ + if ((child_row->type == CAM_SYNC_TYPE_GROUP) || + (child_row->state == CAM_SYNC_STATE_INVALID)) { + spin_unlock_bh(&sync_dev->row_spinlocks[sync_objs[i]]); + CAM_ERR(CAM_SYNC, + "Invalid child fence:%i state:%u type:%u", + child_row->sync_id, child_row->state, + child_row->type); + rc = -EINVAL; + goto clean_children_info; + } + + /* check for child's state */ + if (child_row->state == CAM_SYNC_STATE_SIGNALED_ERROR) { + row->state = CAM_SYNC_STATE_SIGNALED_ERROR; + spin_unlock_bh(&sync_dev->row_spinlocks[sync_objs[i]]); + continue; + } + if (child_row->state != CAM_SYNC_STATE_ACTIVE) { + spin_unlock_bh(&sync_dev->row_spinlocks[sync_objs[i]]); + continue; + } + + row->remaining++; + + /* Add child info */ + child_info = kzalloc(sizeof(*child_info), GFP_ATOMIC); + if (!child_info) { + spin_unlock_bh(&sync_dev->row_spinlocks[sync_objs[i]]); + rc = -ENOMEM; + goto clean_children_info; + } + child_info->sync_id = sync_objs[i]; + list_add_tail(&child_info->list, &row->children_list); + + /* Add parent info */ + parent_info = kzalloc(sizeof(*parent_info), GFP_ATOMIC); + if (!parent_info) { + spin_unlock_bh(&sync_dev->row_spinlocks[sync_objs[i]]); + rc = -ENOMEM; + goto clean_children_info; + } + parent_info->sync_id = idx; + list_add_tail(&parent_info->list, &child_row->parents_list); + spin_unlock_bh(&sync_dev->row_spinlocks[sync_objs[i]]); + } + + if (!row->remaining) { + if (row->state != CAM_SYNC_STATE_SIGNALED_ERROR) + row->state = CAM_SYNC_STATE_SIGNALED_SUCCESS; + complete_all(&row->signaled); + } + + return 0; + +clean_children_info: + row->state = CAM_SYNC_STATE_INVALID; + for (i = i-1; i >= 0; i--) { + spin_lock_bh(&sync_dev->row_spinlocks[sync_objs[i]]); + child_row = table + sync_objs[i]; + cam_sync_util_cleanup_parents_list(child_row, + SYNC_LIST_CLEAN_ONE, idx); + spin_unlock_bh(&sync_dev->row_spinlocks[sync_objs[i]]); + } + + cam_sync_util_cleanup_children_list(row, SYNC_LIST_CLEAN_ALL, 0); + return rc; +} + +int cam_sync_deinit_object(struct sync_table_row *table, uint32_t idx) +{ + struct sync_table_row *row = table + idx; + struct sync_child_info *child_info, *temp_child; + struct sync_callback_info *sync_cb, *temp_cb; + struct sync_parent_info *parent_info, *temp_parent; + struct sync_user_payload *upayload_info, *temp_upayload; + struct sync_table_row *child_row = NULL, *parent_row = NULL; + struct list_head temp_child_list, temp_parent_list; + + if (!table || idx <= 0 || idx >= CAM_SYNC_MAX_OBJS) + return -EINVAL; + + CAM_DBG(CAM_SYNC, + "row name:%s sync_id:%i [idx:%u] row_state:%u", + row->name, row->sync_id, idx, row->state); + + spin_lock_bh(&sync_dev->row_spinlocks[idx]); + if (row->state == CAM_SYNC_STATE_INVALID) { + spin_unlock_bh(&sync_dev->row_spinlocks[idx]); + CAM_ERR(CAM_SYNC, + "Error: accessing an uninitialized sync obj: idx = %d", + idx); + return -EINVAL; + } + + if (row->state == CAM_SYNC_STATE_ACTIVE) + CAM_DBG(CAM_SYNC, + "Destroying an active sync object name:%s id:%i", + row->name, row->sync_id); + + row->state = CAM_SYNC_STATE_INVALID; + + /* Object's child and parent objects will be added into this list */ + INIT_LIST_HEAD(&temp_child_list); + INIT_LIST_HEAD(&temp_parent_list); + + list_for_each_entry_safe(child_info, temp_child, &row->children_list, + list) { + if (child_info->sync_id <= 0) + continue; + + list_del_init(&child_info->list); + list_add_tail(&child_info->list, &temp_child_list); + } + + list_for_each_entry_safe(parent_info, temp_parent, &row->parents_list, + list) { + if (parent_info->sync_id <= 0) + continue; + + list_del_init(&parent_info->list); + list_add_tail(&parent_info->list, &temp_parent_list); + } + + spin_unlock_bh(&sync_dev->row_spinlocks[idx]); + + /* Cleanup the child to parent link from child list */ + while (!list_empty(&temp_child_list)) { + child_info = list_first_entry(&temp_child_list, + struct sync_child_info, list); + child_row = sync_dev->sync_table + child_info->sync_id; + + spin_lock_bh(&sync_dev->row_spinlocks[child_info->sync_id]); + + if (child_row->state == CAM_SYNC_STATE_INVALID) { + list_del_init(&child_info->list); + spin_unlock_bh(&sync_dev->row_spinlocks[ + child_info->sync_id]); + kfree(child_info); + continue; + } + + if (child_row->state == CAM_SYNC_STATE_ACTIVE) + CAM_DBG(CAM_SYNC, + "Warning: destroying active child sync obj = %d", + child_info->sync_id); + + cam_sync_util_cleanup_parents_list(child_row, + SYNC_LIST_CLEAN_ONE, idx); + + list_del_init(&child_info->list); + spin_unlock_bh(&sync_dev->row_spinlocks[child_info->sync_id]); + kfree(child_info); + } + + /* Cleanup the parent to child link */ + while (!list_empty(&temp_parent_list)) { + parent_info = list_first_entry(&temp_parent_list, + struct sync_parent_info, list); + parent_row = sync_dev->sync_table + parent_info->sync_id; + + spin_lock_bh(&sync_dev->row_spinlocks[parent_info->sync_id]); + + if (parent_row->state == CAM_SYNC_STATE_INVALID) { + list_del_init(&parent_info->list); + spin_unlock_bh(&sync_dev->row_spinlocks[ + parent_info->sync_id]); + kfree(parent_info); + continue; + } + + if (parent_row->state == CAM_SYNC_STATE_ACTIVE) + CAM_DBG(CAM_SYNC, + "Warning: destroying active parent sync obj = %d", + parent_info->sync_id); + + cam_sync_util_cleanup_children_list(parent_row, + SYNC_LIST_CLEAN_ONE, idx); + + list_del_init(&parent_info->list); + spin_unlock_bh(&sync_dev->row_spinlocks[parent_info->sync_id]); + kfree(parent_info); + } + + spin_lock_bh(&sync_dev->row_spinlocks[idx]); + list_for_each_entry_safe(upayload_info, temp_upayload, + &row->user_payload_list, list) { + list_del_init(&upayload_info->list); + kfree(upayload_info); + } + + list_for_each_entry_safe(sync_cb, temp_cb, + &row->callback_list, list) { + list_del_init(&sync_cb->list); + kfree(sync_cb); + } + + memset(row, 0, sizeof(*row)); + clear_bit(idx, sync_dev->bitmap); + INIT_LIST_HEAD(&row->callback_list); + INIT_LIST_HEAD(&row->parents_list); + INIT_LIST_HEAD(&row->children_list); + INIT_LIST_HEAD(&row->user_payload_list); + spin_unlock_bh(&sync_dev->row_spinlocks[idx]); + + CAM_DBG(CAM_SYNC, "Destroying sync obj:%d successful", idx); + return 0; +} + +void cam_sync_util_cb_dispatch(struct work_struct *cb_dispatch_work) +{ + struct sync_callback_info *cb_info = container_of(cb_dispatch_work, + struct sync_callback_info, + cb_dispatch_work); + + cam_req_mgr_thread_switch_delay_detect( + cb_info->workq_scheduled_ts); + + cb_info->callback_func(cb_info->sync_obj, + cb_info->status, + cb_info->cb_data); + + kfree(cb_info); +} + +void cam_sync_util_dispatch_signaled_cb(int32_t sync_obj, + uint32_t status) +{ + struct sync_callback_info *sync_cb; + struct sync_user_payload *payload_info; + struct sync_callback_info *temp_sync_cb; + struct sync_table_row *signalable_row; + struct sync_user_payload *temp_payload_info; + + signalable_row = sync_dev->sync_table + sync_obj; + if (signalable_row->state == CAM_SYNC_STATE_INVALID) { + CAM_DBG(CAM_SYNC, + "Accessing invalid sync object:%i", sync_obj); + return; + } + + /* Dispatch kernel callbacks if any were registered earlier */ + list_for_each_entry_safe(sync_cb, + temp_sync_cb, &signalable_row->callback_list, list) { + sync_cb->status = status; + list_del_init(&sync_cb->list); + queue_work(sync_dev->work_queue, + &sync_cb->cb_dispatch_work); + } + + /* Dispatch user payloads if any were registered earlier */ + list_for_each_entry_safe(payload_info, temp_payload_info, + &signalable_row->user_payload_list, list) { + spin_lock_bh(&sync_dev->cam_sync_eventq_lock); + if (!sync_dev->cam_sync_eventq) { + spin_unlock_bh( + &sync_dev->cam_sync_eventq_lock); + break; + } + spin_unlock_bh(&sync_dev->cam_sync_eventq_lock); + cam_sync_util_send_v4l2_event( + CAM_SYNC_V4L_EVENT_ID_CB_TRIG, + sync_obj, + status, + payload_info->payload_data, + CAM_SYNC_PAYLOAD_WORDS * sizeof(__u64)); + + list_del_init(&payload_info->list); + /* + * We can free the list node here because + * sending V4L event will make a deep copy + * anyway + */ + kfree(payload_info); + } + + /* + * This needs to be done because we want to unblock anyone + * who might be blocked and waiting on this sync object + */ + complete_all(&signalable_row->signaled); +} + +void cam_sync_util_send_v4l2_event(uint32_t id, + uint32_t sync_obj, + int status, + void *payload, + int len) +{ + struct v4l2_event event; + __u64 *payload_data = NULL; + struct cam_sync_ev_header *ev_header = NULL; + + event.id = id; + event.type = CAM_SYNC_V4L_EVENT; + + ev_header = CAM_SYNC_GET_HEADER_PTR(event); + ev_header->sync_obj = sync_obj; + ev_header->status = status; + + payload_data = CAM_SYNC_GET_PAYLOAD_PTR(event, __u64); + memcpy(payload_data, payload, len); + + v4l2_event_queue(sync_dev->vdev, &event); + CAM_DBG(CAM_SYNC, "send v4l2 event for sync_obj :%d", + sync_obj); +} + +int cam_sync_util_update_parent_state(struct sync_table_row *parent_row, + int new_state) +{ + int rc = 0; + + switch (parent_row->state) { + case CAM_SYNC_STATE_ACTIVE: + case CAM_SYNC_STATE_SIGNALED_SUCCESS: + parent_row->state = new_state; + break; + + case CAM_SYNC_STATE_SIGNALED_ERROR: + break; + + case CAM_SYNC_STATE_INVALID: + default: + rc = -EINVAL; + break; + } + + return rc; +} + +void cam_sync_util_cleanup_children_list(struct sync_table_row *row, + uint32_t list_clean_type, uint32_t sync_obj) +{ + struct sync_child_info *child_info = NULL; + struct sync_child_info *temp_child_info = NULL; + uint32_t curr_sync_obj; + + list_for_each_entry_safe(child_info, + temp_child_info, &row->children_list, list) { + if ((list_clean_type == SYNC_LIST_CLEAN_ONE) && + (child_info->sync_id != sync_obj)) + continue; + + curr_sync_obj = child_info->sync_id; + list_del_init(&child_info->list); + kfree(child_info); + + if ((list_clean_type == SYNC_LIST_CLEAN_ONE) && + (curr_sync_obj == sync_obj)) + break; + } +} + +void cam_sync_util_cleanup_parents_list(struct sync_table_row *row, + uint32_t list_clean_type, uint32_t sync_obj) +{ + struct sync_parent_info *parent_info = NULL; + struct sync_parent_info *temp_parent_info = NULL; + uint32_t curr_sync_obj; + + list_for_each_entry_safe(parent_info, + temp_parent_info, &row->parents_list, list) { + if ((list_clean_type == SYNC_LIST_CLEAN_ONE) && + (parent_info->sync_id != sync_obj)) + continue; + + curr_sync_obj = parent_info->sync_id; + list_del_init(&parent_info->list); + kfree(parent_info); + + if ((list_clean_type == SYNC_LIST_CLEAN_ONE) && + (curr_sync_obj == sync_obj)) + break; + } +} diff --git a/techpack/camera-bengal/drivers/cam_sync/cam_sync_util.h b/techpack/camera-bengal/drivers/cam_sync/cam_sync_util.h new file mode 100644 index 0000000000000000000000000000000000000000..e114c33c655a839e19748a6df97b257d12209e58 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_sync/cam_sync_util.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef __CAM_SYNC_UTIL_H__ +#define __CAM_SYNC_UTIL_H__ + + +#include +#include "cam_sync_private.h" +#include "cam_debug_util.h" + +extern struct sync_device *sync_dev; + +/** + * @brief: Finds an empty row in the sync table and sets its corresponding bit + * in the bit array + * + * @param sync_dev : Pointer to the sync device instance + * @param idx : Pointer to an long containing the index found in the bit + * array + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_sync_util_find_and_set_empty_row(struct sync_device *sync_dev, + long *idx); + +/** + * @brief: Function to initialize an empty row in the sync table. This should be + * called only for individual sync objects. + * + * @param table : Pointer to the sync objects table + * @param idx : Index of row to initialize + * @param name : Optional string representation of the sync object. Should be + * 63 characters or less + * @param type : type of row to be initialized + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_sync_init_row(struct sync_table_row *table, + uint32_t idx, const char *name, uint32_t type); + +/** + * @brief: Function to uninitialize a row in the sync table + * + * @param table : Pointer to the sync objects table + * @param idx : Index of row to initialize + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_sync_deinit_object(struct sync_table_row *table, uint32_t idx); + +/** + * @brief: Function to initialize a row in the sync table when the object is a + * group object, also known as a merged sync object + * + * @param table : Pointer to the sync objects table + * @param idx : Index of row to initialize + * @param sync_objs : Array of sync objects which will merged + * or grouped together + * @param num_objs : Number of sync objects in the array + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ +int cam_sync_init_group_object(struct sync_table_row *table, + uint32_t idx, + uint32_t *sync_objs, + uint32_t num_objs); + +int cam_sync_deinit_object(struct sync_table_row *table, uint32_t idx); + +/** + * @brief: Function to dispatch a kernel callback for a sync callback + * + * @param cb_dispatch_work : Pointer to the work_struct that needs to be + * dispatched + * + * @return None + */ +void cam_sync_util_cb_dispatch(struct work_struct *cb_dispatch_work); + +/** + * @brief: Function to dispatch callbacks for a signaled sync object + * + * @sync_obj : Sync object that is signaled + * @status : Status of the signaled object + * + * @return None + */ +void cam_sync_util_dispatch_signaled_cb(int32_t sync_obj, + uint32_t status); + +/** + * @brief: Function to send V4L event to user space + * @param id : V4L event id to send + * @param sync_obj : Sync obj for which event needs to be sent + * @param status : Status of the event + * @payload : Payload that needs to be sent to user space + * @len : Length of the payload + * + * @return None + */ +void cam_sync_util_send_v4l2_event(uint32_t id, + uint32_t sync_obj, + int status, + void *payload, + int len); + +/** + * @brief: Function which gets the next state of the sync object based on the + * current state and the new state + * + * @param current_state : Current state of the sync object + * @param new_state : New state of the sync object + * + * @return Next state of the sync object + */ +int cam_sync_util_update_parent_state(struct sync_table_row *parent_row, + int new_state); + +/** + * @brief: Function to clean up the children of a sync object + * @row : Row whose child list to clean + * @list_clean_type : Clean specific object or clean all objects + * @sync_obj : Sync object to be clean if list clean type is + * SYNC_LIST_CLEAN_ONE + * + * @return None + */ +void cam_sync_util_cleanup_children_list(struct sync_table_row *row, + uint32_t list_clean_type, uint32_t sync_obj); + +/** + * @brief: Function to clean up the parents of a sync object + * @row : Row whose parent list to clean + * @list_clean_type : Clean specific object or clean all objects + * @sync_obj : Sync object to be clean if list clean type is + * SYNC_LIST_CLEAN_ONE + * + * @return None + */ +void cam_sync_util_cleanup_parents_list(struct sync_table_row *row, + uint32_t list_clean_type, uint32_t sync_obj); + +#endif /* __CAM_SYNC_UTIL_H__ */ diff --git a/techpack/camera-bengal/drivers/cam_utils/Makefile b/techpack/camera-bengal/drivers/cam_utils/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..ccd924fc0ce05062aa5b0226fafa7234dfad9f1e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_soc_util.o cam_io_util.o cam_packet_util.o cam_debug_util.o cam_trace.o cam_common_util.o +obj-$(CONFIG_SPECTRA_CAMERA) += cam_cx_ipeak.o diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_common_util.c b/techpack/camera-bengal/drivers/cam_utils/cam_common_util.c new file mode 100644 index 0000000000000000000000000000000000000000..dbcb31d7bf0ec49b9f8fcaa17e5ab11d5915682e --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_common_util.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include + +#include "cam_common_util.h" +#include "cam_debug_util.h" + +int cam_common_util_get_string_index(const char **strings, + uint32_t num_strings, const char *matching_string, uint32_t *index) +{ + int i; + + for (i = 0; i < num_strings; i++) { + if (strnstr(strings[i], matching_string, strlen(strings[i]))) { + CAM_DBG(CAM_UTIL, "matched %s : %d\n", + matching_string, i); + *index = i; + return 0; + } + } + + return -EINVAL; +} + +uint32_t cam_common_util_remove_duplicate_arr(int32_t *arr, uint32_t num) +{ + int i, j; + uint32_t wr_idx = 1; + + if (!arr) { + CAM_ERR(CAM_UTIL, "Null input array"); + return 0; + } + + for (i = 1; i < num; i++) { + for (j = 0; j < wr_idx ; j++) { + if (arr[i] == arr[j]) + break; + } + if (j == wr_idx) + arr[wr_idx++] = arr[i]; + } + + return wr_idx; +} diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_common_util.h b/techpack/camera-bengal/drivers/cam_utils/cam_common_util.h new file mode 100644 index 0000000000000000000000000000000000000000..ebe75f6eb5e930dc70bd6f93fee1dc4f6e750b91 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_common_util.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_COMMON_UTIL_H_ +#define _CAM_COMMON_UTIL_H_ + +#include +#include + +#define CAM_BITS_MASK_SHIFT(x, mask, shift) (((x) & (mask)) >> shift) + +#define PTR_TO_U64(ptr) ((uint64_t)(uintptr_t)ptr) +#define U64_TO_PTR(ptr) ((void *)(uintptr_t)ptr) + +#define CAM_GET_TIMESTAMP(timestamp) ktime_get_real_ts64(&(timestamp)) +#define CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts_start, ts_end, diff_microsec) \ +({ \ + diff_microsec = 0; \ + if (ts_end.tv_nsec >= ts_start.tv_nsec) { \ + diff_microsec = \ + (ts_end.tv_nsec - ts_start.tv_nsec) / 1000; \ + diff_microsec += \ + (ts_end.tv_sec - ts_start.tv_sec) * 1000 * 1000; \ + } else { \ + diff_microsec = \ + (ts_end.tv_nsec + \ + (1000*1000*1000 - ts_start.tv_nsec)) / 1000; \ + diff_microsec += \ + (ts_end.tv_sec - ts_start.tv_sec - 1) * 1000 * 1000; \ + } \ +}) + + +/** + * cam_common_util_get_string_index() + * + * @brief Match the string from list of strings to return + * matching index + * + * @strings: Pointer to list of strings + * @num_strings: Number of strings in 'strings' + * @matching_string: String to match + * @index: Pointer to index to return matching index + * + * @return: 0 for success + * -EINVAL for Fail + */ +int cam_common_util_get_string_index(const char **strings, + uint32_t num_strings, const char *matching_string, uint32_t *index); + +/** + * cam_common_util_remove_duplicate_arr() + * + * @brief Move all the unique integers to the start of + * the array and return the number of unique integers + * + * @array: Pointer to the first integer of array + * @num: Number of elements in array + * + * @return: Number of unique integers in array + */ +uint32_t cam_common_util_remove_duplicate_arr(int32_t *array, + uint32_t num); + +#endif /* _CAM_COMMON_UTIL_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_cx_ipeak.c b/techpack/camera-bengal/drivers/cam_utils/cam_cx_ipeak.c new file mode 100644 index 0000000000000000000000000000000000000000..b0f93ba045e0cd7e0c375ab161f74a276143326a --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_cx_ipeak.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "cam_soc_util.h" +#include "cam_debug_util.h" + +static struct cx_ipeak_client *cam_cx_ipeak; +static int cx_ipeak_level = CAM_NOMINAL_VOTE; +static int cx_default_ipeak_mask; +static int cx_current_ipeak_mask; +static int cam_cx_client_cnt; + +int cam_cx_ipeak_register_cx_ipeak(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + + soc_info->cam_cx_ipeak_enable = true; + soc_info->cam_cx_ipeak_bit = 1 << cam_cx_client_cnt++; + cx_default_ipeak_mask |= soc_info->cam_cx_ipeak_bit; + + if (cam_cx_ipeak) + goto exit; + + cam_cx_ipeak = cx_ipeak_register(soc_info->dev->of_node, + "qcom,cam-cx-ipeak"); + + if (cam_cx_ipeak) { + goto exit; + } else { + rc = -EINVAL; + goto exit; + } + +exit: + CAM_DBG(CAM_UTIL, "cam_cx_ipeak is enabled for %s\n" + "mask = %x cx_default_ipeak_mask = %x", + soc_info->dev_name, soc_info->cam_cx_ipeak_bit, + cx_default_ipeak_mask); + return rc; +} + +int cam_cx_ipeak_update_vote_cx_ipeak(struct cam_hw_soc_info *soc_info, + int32_t apply_level) +{ + int32_t soc_cx_ipeak_bit = soc_info->cam_cx_ipeak_bit; + int ret = 0; + + CAM_DBG(CAM_UTIL, "E: apply_level = %d cx_current_ipeak_mask = %x\n" + "soc_cx_ipeak_bit = %x", + apply_level, cx_current_ipeak_mask, soc_cx_ipeak_bit); + + if (apply_level < cx_ipeak_level && + (cx_current_ipeak_mask & soc_cx_ipeak_bit)) { + if (cx_current_ipeak_mask == cx_default_ipeak_mask) { + ret = cx_ipeak_update(cam_cx_ipeak, false); + if (ret) + goto exit; + CAM_DBG(CAM_UTIL, + "X: apply_level = %d cx_current_ipeak_mask = %x\n" + "soc_cx_ipeak_bit = %x %s UNVOTE", + apply_level, cx_current_ipeak_mask, + soc_cx_ipeak_bit, soc_info->dev_name); + } + cx_current_ipeak_mask &= (~soc_cx_ipeak_bit); + CAM_DBG(CAM_UTIL, + "X: apply_level = %d cx_current_ipeak_mask = %x\n" + "soc_cx_ipeak_bit = %x %s DISABLE_BIT", + apply_level, cx_current_ipeak_mask, + soc_cx_ipeak_bit, soc_info->dev_name); + goto exit; + } else if (apply_level < cx_ipeak_level) { + CAM_DBG(CAM_UTIL, + "X: apply_level = %d cx_current_ipeak_mask = %x\n" + "soc_cx_ipeak_bit = %x NO AI", + apply_level, cx_current_ipeak_mask, soc_cx_ipeak_bit); + goto exit; + } + + cx_current_ipeak_mask |= soc_cx_ipeak_bit; + CAM_DBG(CAM_UTIL, + "X: apply_level = %d cx_current_ipeak_mask = %x\n" + "soc_cx_ipeak_bit = %x %s ENABLE_BIT", + apply_level, cx_current_ipeak_mask, + soc_cx_ipeak_bit, soc_info->dev_name); + if (cx_current_ipeak_mask == cx_default_ipeak_mask) { + ret = cx_ipeak_update(cam_cx_ipeak, true); + if (ret) + goto exit; + CAM_DBG(CAM_UTIL, + "X: apply_level = %d cx_current_ipeak_mask = %x\n" + "soc_cx_ipeak_bit = %x %s VOTE", + apply_level, cx_current_ipeak_mask, + soc_cx_ipeak_bit, soc_info->dev_name); + } + +exit: + return ret; +} + +int cam_cx_ipeak_unvote_cx_ipeak(struct cam_hw_soc_info *soc_info) +{ + int32_t soc_cx_ipeak_bit = soc_info->cam_cx_ipeak_bit; + + CAM_DBG(CAM_UTIL, "E:cx_current_ipeak_mask = %x\n" + "soc_cx_ipeak_bit = %x", + cx_current_ipeak_mask, soc_cx_ipeak_bit); + if (cx_current_ipeak_mask == cx_default_ipeak_mask) { + if (cam_cx_ipeak) + cx_ipeak_update(cam_cx_ipeak, false); + CAM_DBG(CAM_UTIL, "X:cx_current_ipeak_mask = %x\n" + "soc_cx_ipeak_bit = %x UNVOTE", + cx_current_ipeak_mask, soc_cx_ipeak_bit); + } + cx_current_ipeak_mask &= (~soc_cx_ipeak_bit); + CAM_DBG(CAM_UTIL, "X:cx_current_ipeak_mask = %x\n" + "soc_cx_ipeak_bit = %x", + cx_current_ipeak_mask, soc_cx_ipeak_bit); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_cx_ipeak.h b/techpack/camera-bengal/drivers/cam_utils/cam_cx_ipeak.h new file mode 100644 index 0000000000000000000000000000000000000000..ab06952b86a8c649758bb95019643cb351c057e5 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_cx_ipeak.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CX_IPEAK_H_ +#define _CAM_CX_IPEAK_H_ + +#include "cam_soc_util.h" + +int cam_cx_ipeak_register_cx_ipeak(struct cam_hw_soc_info *soc_info); + +int cam_cx_ipeak_update_vote_cx_ipeak(struct cam_hw_soc_info *soc_info, + int32_t apply_level); +int cam_cx_ipeak_unvote_cx_ipeak(struct cam_hw_soc_info *soc_info); + +#endif /* _CAM_CX_IPEAK_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_debug_util.c b/techpack/camera-bengal/drivers/cam_utils/cam_debug_util.c new file mode 100644 index 0000000000000000000000000000000000000000..bc7aab55b0fee5f77e3e38cd443e6d7bc9349ace --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_debug_util.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundataion. All rights reserved. + */ + +#include +#include + +#include "cam_debug_util.h" + +static uint debug_mdl; +module_param(debug_mdl, uint, 0644); + +const char *cam_get_module_name(unsigned int module_id) +{ + const char *name = NULL; + + switch (module_id) { + case CAM_CDM: + name = "CAM-CDM"; + break; + case CAM_CORE: + name = "CAM-CORE"; + break; + case CAM_CRM: + name = "CAM-CRM"; + break; + case CAM_CPAS: + name = "CAM-CPAS"; + break; + case CAM_ISP: + name = "CAM-ISP"; + break; + case CAM_SENSOR: + name = "CAM-SENSOR"; + break; + case CAM_SMMU: + name = "CAM-SMMU"; + break; + case CAM_SYNC: + name = "CAM-SYNC"; + break; + case CAM_ICP: + name = "CAM-ICP"; + break; + case CAM_JPEG: + name = "CAM-JPEG"; + break; + case CAM_FD: + name = "CAM-FD"; + break; + case CAM_LRME: + name = "CAM-LRME"; + break; + case CAM_FLASH: + name = "CAM-FLASH"; + break; + case CAM_ACTUATOR: + name = "CAM-ACTUATOR"; + break; + case CAM_CCI: + name = "CAM-CCI"; + break; + case CAM_CSIPHY: + name = "CAM-CSIPHY"; + break; + case CAM_EEPROM: + name = "CAM-EEPROM"; + break; + case CAM_UTIL: + name = "CAM-UTIL"; + break; + case CAM_CTXT: + name = "CAM-CTXT"; + break; + case CAM_HFI: + name = "CAM-HFI"; + break; + case CAM_OIS: + name = "CAM-OIS"; + break; + case CAM_IRQ_CTRL: + name = "CAM-IRQ-CTRL"; + break; + case CAM_MEM: + name = "CAM-MEM"; + break; + case CAM_PERF: + name = "CAM-PERF"; + break; + case CAM_REQ: + name = "CAM-REQ"; + break; + case CAM_CUSTOM: + name = "CAM-CUSTOM"; + case CAM_OPE: + name = "CAM-OPE"; + break; + case CAM_PRESIL: + name = "CAM-PRESIL"; + break; + default: + name = "CAM"; + break; + } + + return name; +} + +void cam_debug_log(unsigned int module_id, const char *func, const int line, + const char *fmt, ...) +{ + char str_buffer[STR_BUFFER_MAX_LENGTH]; + va_list args; + + va_start(args, fmt); + + if (debug_mdl & module_id) { + vsnprintf(str_buffer, STR_BUFFER_MAX_LENGTH, fmt, args); + pr_info("CAM_DBG: %s: %s: %d: %s\n", + cam_get_module_name(module_id), + func, line, str_buffer); + } + + va_end(args); +} diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_debug_util.h b/techpack/camera-bengal/drivers/cam_utils/cam_debug_util.h new file mode 100644 index 0000000000000000000000000000000000000000..1b2000ac08becf8015b1f77bbb79ac9bcf036b93 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_debug_util.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CAM_DEBUG_UTIL_H_ +#define _CAM_DEBUG_UTIL_H_ + +#define CAM_IS_NULL_TO_STR(ptr) ((ptr) ? "Non-NULL" : "NULL") + +/* Module IDs used for debug logging */ +#define CAM_CDM (1 << 0) +#define CAM_CORE (1 << 1) +#define CAM_CPAS (1 << 2) +#define CAM_ISP (1 << 3) +#define CAM_CRM (1 << 4) +#define CAM_SENSOR (1 << 5) +#define CAM_SMMU (1 << 6) +#define CAM_SYNC (1 << 7) +#define CAM_ICP (1 << 8) +#define CAM_JPEG (1 << 9) +#define CAM_FD (1 << 10) +#define CAM_LRME (1 << 11) +#define CAM_FLASH (1 << 12) +#define CAM_ACTUATOR (1 << 13) +#define CAM_CCI (1 << 14) +#define CAM_CSIPHY (1 << 15) +#define CAM_EEPROM (1 << 16) +#define CAM_UTIL (1 << 17) +#define CAM_HFI (1 << 18) +#define CAM_CTXT (1 << 19) +#define CAM_OIS (1 << 20) +#define CAM_RES (1 << 21) +#define CAM_MEM (1 << 22) + +/* CAM_IRQ_CTRL: For events in irq controller */ +#define CAM_IRQ_CTRL (1 << 23) + +/* CAM_REQ: Tracks a request submitted to KMD */ +#define CAM_REQ (1 << 24) + +/* CAM_PERF: Used for performance (clock, BW etc) logs */ +#define CAM_PERF (1 << 25) +#define CAM_CUSTOM (1 << 26) +#define CAM_OPE (1 << 28) +#define CAM_PRESIL (1 << 27) + +#define STR_BUFFER_MAX_LENGTH 1024 + +/* + * cam_debug_log() + * + * @brief : Get the Module name from module ID and print + * respective debug logs + * + * @module_id : Respective Module ID which is calling this function + * @func : Function which is calling to print logs + * @line : Line number associated with the function which is calling + * to print log + * @fmt : Formatted string which needs to be print in the log + * + */ +void cam_debug_log(unsigned int module_id, const char *func, const int line, + const char *fmt, ...); + +/* + * cam_get_module_name() + * + * @brief : Get the module name from module ID + * + * @module_id : Module ID which is using this function + */ +const char *cam_get_module_name(unsigned int module_id); + +/* + * CAM_ERR + * @brief : This Macro will print error logs + * + * @__module : Respective module id which is been calling this Macro + * @fmt : Formatted string which needs to be print in log + * @args : Arguments which needs to be print in log + */ +#define CAM_ERR(__module, fmt, args...) \ + pr_info("CAM_ERR: %s: %s: %d " fmt "\n", \ + cam_get_module_name(__module), __func__, __LINE__, ##args) +/* + * CAM_WARN + * @brief : This Macro will print warning logs + * + * @__module : Respective module id which is been calling this Macro + * @fmt : Formatted string which needs to be print in log + * @args : Arguments which needs to be print in log + */ +#define CAM_WARN(__module, fmt, args...) \ + pr_info("CAM_WARN: %s: %s: %d " fmt "\n", \ + cam_get_module_name(__module), __func__, __LINE__, ##args) +/* + * CAM_INFO + * @brief : This Macro will print Information logs + * + * @__module : Respective module id which is been calling this Macro + * @fmt : Formatted string which needs to be print in log + * @args : Arguments which needs to be print in log + */ +#define CAM_INFO(__module, fmt, args...) \ + pr_info("CAM_INFO: %s: %s: %d " fmt "\n", \ + cam_get_module_name(__module), __func__, __LINE__, ##args) + +/* + * CAM_INFO_RATE_LIMIT + * @brief : This Macro will print info logs with ratelimit + * + * @__module : Respective module id which is been calling this Macro + * @fmt : Formatted string which needs to be print in log + * @args : Arguments which needs to be print in log + */ +#define CAM_INFO_RATE_LIMIT(__module, fmt, args...) \ + pr_info_ratelimited("CAM_INFO: %s: %s: %d " fmt "\n", \ + cam_get_module_name(__module), __func__, __LINE__, ##args) + +/* + * CAM_DBG + * @brief : This Macro will print debug logs when enabled using GROUP + * + * @__module : Respective module id which is been calling this Macro + * @fmt : Formatted string which needs to be print in log + * @args : Arguments which needs to be print in log + */ +#define CAM_DBG(__module, fmt, args...) \ + cam_debug_log(__module, __func__, __LINE__, fmt, ##args) + +/* + * CAM_ERR_RATE_LIMIT + * @brief : This Macro will print error print logs with ratelimit + */ +#define CAM_ERR_RATE_LIMIT(__module, fmt, args...) \ + pr_info_ratelimited("CAM_ERR: %s: %s: %d " fmt "\n", \ + cam_get_module_name(__module), __func__, __LINE__, ##args) +/* + * CAM_WARN_RATE_LIMIT + * @brief : This Macro will print warning logs with ratelimit + * + * @__module : Respective module id which is been calling this Macro + * @fmt : Formatted string which needs to be print in log + * @args : Arguments which needs to be print in log + */ +#define CAM_WARN_RATE_LIMIT(__module, fmt, args...) \ + pr_info_ratelimited("CAM_WARN: %s: %s: %d " fmt "\n", \ + cam_get_module_name(__module), __func__, __LINE__, ##args) + +/* + * CAM_WARN_RATE_LIMIT_CUSTOM + * @brief : This Macro will print warn logs with custom ratelimit + * + * @__module : Respective module id which is been calling this Macro + * @interval : Time interval in seconds + * @burst : No of logs to print in interval time + * @fmt : Formatted string which needs to be print in log + * @args : Arguments which needs to be print in log + */ +#define CAM_WARN_RATE_LIMIT_CUSTOM(__module, interval, burst, fmt, args...) \ + ({ \ + static DEFINE_RATELIMIT_STATE(_rs, \ + (interval * HZ), \ + burst); \ + if (__ratelimit(&_rs)) \ + pr_info( \ + "CAM_WARN: %s: %s: %d " fmt "\n", \ + cam_get_module_name(__module), __func__, \ + __LINE__, ##args); \ + }) + +/* + * CAM_INFO_RATE_LIMIT_CUSTOM + * @brief : This Macro will print info logs with custom ratelimit + * + * @__module : Respective module id which is been calling this Macro + * @interval : Time interval in seconds + * @burst : No of logs to print in interval time + * @fmt : Formatted string which needs to be print in log + * @args : Arguments which needs to be print in log + */ +#define CAM_INFO_RATE_LIMIT_CUSTOM(__module, interval, burst, fmt, args...) \ + ({ \ + static DEFINE_RATELIMIT_STATE(_rs, \ + (interval * HZ), \ + burst); \ + if (__ratelimit(&_rs)) \ + pr_info( \ + "CAM_INFO: %s: %s: %d " fmt "\n", \ + cam_get_module_name(__module), __func__, \ + __LINE__, ##args); \ + }) + +/* + * CAM_ERR_RATE_LIMIT_CUSTOM + * @brief : This Macro will print error logs with custom ratelimit + * + * @__module : Respective module id which is been calling this Macro + * @interval : Time interval in seconds + * @burst : No of logs to print in interval time + * @fmt : Formatted string which needs to be print in log + * @args : Arguments which needs to be print in log + */ +#define CAM_ERR_RATE_LIMIT_CUSTOM(__module, interval, burst, fmt, args...) \ + ({ \ + static DEFINE_RATELIMIT_STATE(_rs, \ + (interval * HZ), \ + burst); \ + if (__ratelimit(&_rs)) \ + pr_info( \ + "CAM_ERR: %s: %s: %d " fmt "\n", \ + cam_get_module_name(__module), __func__, \ + __LINE__, ##args); \ + }) + +#endif /* _CAM_DEBUG_UTIL_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_io_util.c b/techpack/camera-bengal/drivers/cam_utils/cam_io_util.c new file mode 100644 index 0000000000000000000000000000000000000000..fcbc4b5e00f54d74f3f6295f2b0c3b956ab31328 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_io_util.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2011-2014, 2017-2018, The Linux Foundation. + * All rights reserved. + */ + +#include +#include +#include +#include "cam_io_util.h" +#include "cam_debug_util.h" + +int cam_io_w(uint32_t data, void __iomem *addr) +{ + if (!addr) + return -EINVAL; + + CAM_DBG(CAM_UTIL, "0x%pK %08x", addr, data); + writel_relaxed_no_log(data, addr); + + return 0; +} + +int cam_io_w_mb(uint32_t data, void __iomem *addr) +{ + if (!addr) + return -EINVAL; + + CAM_DBG(CAM_UTIL, "0x%pK %08x", addr, data); + /* Ensure previous writes are done */ + wmb(); + writel_relaxed_no_log(data, addr); + /* Ensure previous writes are done */ + wmb(); + + return 0; +} + +uint32_t cam_io_r(void __iomem *addr) +{ + uint32_t data; + + if (!addr) { + CAM_ERR(CAM_UTIL, "Invalid args"); + return 0; + } + + data = readl_relaxed(addr); + CAM_DBG(CAM_UTIL, "0x%pK %08x", addr, data); + + return data; +} + +uint32_t cam_io_r_mb(void __iomem *addr) +{ + uint32_t data; + + if (!addr) { + CAM_ERR(CAM_UTIL, "Invalid args"); + return 0; + } + + /* Ensure previous read is done */ + rmb(); + data = readl_relaxed(addr); + CAM_DBG(CAM_UTIL, "0x%pK %08x", addr, data); + /* Ensure previous read is done */ + rmb(); + + return data; +} + +int cam_io_memcpy(void __iomem *dest_addr, + void __iomem *src_addr, uint32_t len) +{ + int i; + uint32_t *d = (uint32_t *) dest_addr; + uint32_t *s = (uint32_t *) src_addr; + + if (!dest_addr || !src_addr) + return -EINVAL; + + CAM_DBG(CAM_UTIL, "%pK %pK %d", dest_addr, src_addr, len); + + for (i = 0; i < len/4; i++) { + CAM_DBG(CAM_UTIL, "0x%pK %08x", d, *s); + writel_relaxed(*s++, d++); + } + + return 0; +} + +int cam_io_memcpy_mb(void __iomem *dest_addr, + void __iomem *src_addr, uint32_t len) +{ + int i; + uint32_t *d = (uint32_t *) dest_addr; + uint32_t *s = (uint32_t *) src_addr; + + if (!dest_addr || !src_addr) + return -EINVAL; + + CAM_DBG(CAM_UTIL, "%pK %pK %d", dest_addr, src_addr, len); + + /* + * Do not use cam_io_w_mb to avoid double wmb() after a write + * and before the next write. + */ + wmb(); + for (i = 0; i < (len / 4); i++) { + CAM_DBG(CAM_UTIL, "0x%pK %08x", d, *s); + writel_relaxed(*s++, d++); + } + /* Ensure previous writes are done */ + wmb(); + + return 0; +} + +int cam_io_poll_value(void __iomem *addr, uint32_t wait_data, uint32_t retry, + unsigned long min_usecs, unsigned long max_usecs) +{ + uint32_t tmp, cnt = 0; + int rc = 0; + + if (!addr) + return -EINVAL; + + tmp = readl_relaxed(addr); + while ((tmp != wait_data) && (cnt++ < retry)) { + if (min_usecs > 0 && max_usecs > 0) + usleep_range(min_usecs, max_usecs); + tmp = readl_relaxed(addr); + } + + if (cnt > retry) { + CAM_DBG(CAM_UTIL, "Poll failed by value"); + rc = -EINVAL; + } + + return rc; +} + +int cam_io_poll_value_wmask(void __iomem *addr, uint32_t wait_data, + uint32_t bmask, uint32_t retry, unsigned long min_usecs, + unsigned long max_usecs) +{ + uint32_t tmp, cnt = 0; + int rc = 0; + + if (!addr) + return -EINVAL; + + tmp = readl_relaxed(addr); + while (((tmp & bmask) != wait_data) && (cnt++ < retry)) { + if (min_usecs > 0 && max_usecs > 0) + usleep_range(min_usecs, max_usecs); + tmp = readl_relaxed(addr); + } + + if (cnt > retry) { + CAM_DBG(CAM_UTIL, "Poll failed with mask"); + rc = -EINVAL; + } + + return rc; +} + +int cam_io_w_same_offset_block(const uint32_t *data, void __iomem *addr, + uint32_t len) +{ + int i; + + if (!data || !len || !addr) + return -EINVAL; + + for (i = 0; i < len; i++) { + CAM_DBG(CAM_UTIL, "i= %d len =%d val=%x addr =%pK", + i, len, data[i], addr); + writel_relaxed(data[i], addr); + } + + return 0; +} + +int cam_io_w_mb_same_offset_block(const uint32_t *data, void __iomem *addr, + uint32_t len) +{ + int i; + + if (!data || !len || !addr) + return -EINVAL; + + for (i = 0; i < len; i++) { + CAM_DBG(CAM_UTIL, "i= %d len =%d val=%x addr =%pK", + i, len, data[i], addr); + /* Ensure previous writes are done */ + wmb(); + writel_relaxed(data[i], addr); + } + + return 0; +} + +#define __OFFSET(__i) (data[__i][0]) +#define __VAL(__i) (data[__i][1]) +int cam_io_w_offset_val_block(const uint32_t data[][2], + void __iomem *addr_base, uint32_t len) +{ + int i; + + if (!data || !len || !addr_base) + return -EINVAL; + + for (i = 0; i < len; i++) { + CAM_DBG(CAM_UTIL, "i= %d len =%d val=%x addr_base =%pK reg=%x", + i, len, __VAL(i), addr_base, __OFFSET(i)); + writel_relaxed(__VAL(i), addr_base + __OFFSET(i)); + } + + return 0; +} + +int cam_io_w_mb_offset_val_block(const uint32_t data[][2], + void __iomem *addr_base, uint32_t len) +{ + int i; + + if (!data || !len || !addr_base) + return -EINVAL; + + /* Ensure write is done */ + wmb(); + for (i = 0; i < len; i++) { + CAM_DBG(CAM_UTIL, "i= %d len =%d val=%x addr_base =%pK reg=%x", + i, len, __VAL(i), addr_base, __OFFSET(i)); + writel_relaxed(__VAL(i), addr_base + __OFFSET(i)); + } + + return 0; +} + +#define BYTES_PER_REGISTER 4 +#define NUM_REGISTER_PER_LINE 4 +#define REG_OFFSET(__start, __i) (__start + (__i * BYTES_PER_REGISTER)) +int cam_io_dump(void __iomem *base_addr, uint32_t start_offset, int size) +{ + char line_str[128]; + char *p_str; + int i; + uint32_t data; + + CAM_DBG(CAM_UTIL, "addr=%pK offset=0x%x size=%d", + base_addr, start_offset, size); + + if (!base_addr || (size <= 0)) + return -EINVAL; + + line_str[0] = '\0'; + p_str = line_str; + for (i = 0; i < size; i++) { + if (i % NUM_REGISTER_PER_LINE == 0) { + snprintf(p_str, 12, "0x%08x: ", + REG_OFFSET(start_offset, i)); + p_str += 11; + } + data = readl_relaxed(base_addr + REG_OFFSET(start_offset, i)); + snprintf(p_str, 10, "%08x ", data); + p_str += 9; + if ((i + 1) % NUM_REGISTER_PER_LINE == 0) { + CAM_ERR(CAM_UTIL, "%s", line_str); + line_str[0] = '\0'; + p_str = line_str; + } + } + if (line_str[0] != '\0') + CAM_ERR(CAM_UTIL, "%s", line_str); + + return 0; +} diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_io_util.h b/techpack/camera-bengal/drivers/cam_utils/cam_io_util.h new file mode 100644 index 0000000000000000000000000000000000000000..66aaeaa45d55eb571d6581442902e47f033d9155 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_io_util.h @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2011-2014, 2017-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_IO_UTIL_H_ +#define _CAM_IO_UTIL_H_ + +#include + +/** + * cam_io_w() + * + * @brief: Camera IO util for register write + * + * @data: Value to be written + * @addr: Address used to write the value + * + * @return: Success or Failure + */ +int cam_io_w(uint32_t data, void __iomem *addr); + +/** + * cam_io_w_mb() + * + * @brief: Camera IO util for register write with memory barrier. + * Memory Barrier is only before the write to ensure the + * order. If need to ensure this write is also flushed + * call wmb() independently in the caller. + * + * @data: Value to be written + * @addr: Address used to write the value + * + * @return: Success or Failure + */ +int cam_io_w_mb(uint32_t data, void __iomem *addr); + +/** + * cam_io_r() + * + * @brief: Camera IO util for register read + * + * @addr: Address of register to be read + * + * @return: Value read from the register address + */ +uint32_t cam_io_r(void __iomem *addr); + +/** + * cam_io_r_mb() + * + * @brief: Camera IO util for register read with memory barrier. + * Memory Barrier is only before the write to ensure the + * order. If need to ensure this write is also flushed + * call rmb() independently in the caller. + * + * @addr: Address of register to be read + * + * @return: Value read from the register address + */ +uint32_t cam_io_r_mb(void __iomem *addr); + +/** + * cam_io_memcpy() + * + * @brief: Camera IO util for memory to register copy + * + * @dest_addr: Destination register address + * @src_addr: Source regiser address + * @len: Range to be copied + * + * @return: Success or Failure + */ +int cam_io_memcpy(void __iomem *dest_addr, + void __iomem *src_addr, uint32_t len); + +/** + * cam_io_memcpy_mb() + * + * @brief: Camera IO util for memory to register copy + * with barrier. + * Memory Barrier is only before the write to ensure the + * order. If need to ensure this write is also flushed + * call wmb() independently in the caller. + * + * @dest_addr: Destination register address + * @src_addr: Source regiser address + * @len: Range to be copied + * + * @return: Success or Failure + */ +int cam_io_memcpy_mb(void __iomem *dest_addr, + void __iomem *src_addr, uint32_t len); + +/** + * cam_io_poll_value_wmask() + * + * @brief: Poll register value with bitmask. + * + * @addr: Register address to be polled + * @wait_data: Wait until @bmask read from @addr matches this data + * @bmask: Bit mask + * @retry: Number of retry + * @min_usecs: Minimum time to wait for retry + * @max_usecs: Maximum time to wait for retry + * + * @return: Success or Failure + * + * This function can sleep so it should not be called from interrupt + * handler, spin_lock etc. + */ +int cam_io_poll_value_wmask(void __iomem *addr, uint32_t wait_data, + uint32_t bmask, uint32_t retry, unsigned long min_usecs, + unsigned long max_usecs); + +/** + * cam_io_poll_value() + * + * @brief: Poll register value + * + * @addr: Register address to be polled + * @wait_data: Wait until value read from @addr matches this data + * @retry: Number of retry + * @min_usecs: Minimum time to wait for retry + * @max_usecs: Maximum time to wait for retry + * + * @return: Success or Failure + * + * This function can sleep so it should not be called from interrupt + * handler, spin_lock etc. + */ +int cam_io_poll_value(void __iomem *addr, uint32_t wait_data, uint32_t retry, + unsigned long min_usecs, unsigned long max_usecs); + +/** + * cam_io_w_same_offset_block() + * + * @brief: Write a block of data to same address + * + * @data: Block data to be written + * @addr: Register offset to be written. + * @len: Number of the data to be written + * + * @return: Success or Failure + */ +int cam_io_w_same_offset_block(const uint32_t *data, void __iomem *addr, + uint32_t len); + +/** + * cam_io_w_mb_same_offset_block() + * + * @brief: Write a block of data to same address with barrier. + * Memory Barrier is only before the write to ensure the + * order. If need to ensure this write is also flushed + * call wmb() independently in the caller. + * + * @data: Block data to be written + * @addr: Register offset to be written. + * @len: Number of the data to be written + * + * @return: Success or Failure + */ +int cam_io_w_mb_same_offset_block(const uint32_t *data, void __iomem *addr, + uint32_t len); + +/** + * cam_io_w_offset_val_block() + * + * @brief: This API is to write a block of registers + * represented by a 2 dimensional array table with + * register offset and value pair + * + * offset0, value0, + * offset1, value1, + * offset2, value2, + * and so on... + * + * @data: Pointer to 2-dimensional offset-value array + * @addr_base: Base address to which offset will be added to + * get the register address + * @len: Length of offset-value pair array to be written in + * number of uin32_t + * + * @return: Success or Failure + * + */ +int32_t cam_io_w_offset_val_block(const uint32_t data[][2], + void __iomem *addr_base, uint32_t len); + +/** + * cam_io_w_mb_offset_val_block() + * + * @brief: This API is to write a block of registers + * represented by a 2 dimensional array table with + * register offset and value pair with memory barrier. + * Memory Barrier is only before the write to ensure the + * order. If need to ensure this write is also flushed + * call wmb() independently in the caller. + * The OFFSETS NEED to be different because of the way + * barrier is used here. + * + * offset0, value0, + * offset1, value1, + * offset2, value2, + * and so on... + * + * @data: Pointer to 2-dimensional offset-value array + * @addr_base: Base address to which offset will be added to + * get the register address + * @len: Length of offset-value pair array to be written in + * number of uin32_t + * + * @return: Success or Failure + * + */ +int32_t cam_io_w_mb_offset_val_block(const uint32_t data[][2], + void __iomem *addr_base, uint32_t len); + +/** + * cam_io_dump() + * + * @brief: Camera IO util for dumping a range of register + * + * @base_addr: Start register address for the dumping + * @start_offset: Start register offset for the dump + * @size: Size specifying the range for dumping + * + * @return: Success or Failure + */ +int cam_io_dump(void __iomem *base_addr, uint32_t start_offset, int size); + +#endif /* _CAM_IO_UTIL_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_packet_util.c b/techpack/camera-bengal/drivers/cam_utils/cam_packet_util.c new file mode 100644 index 0000000000000000000000000000000000000000..818d136ca3c682691bdb51cdeb109e6e9aad4edc --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_packet_util.c @@ -0,0 +1,394 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +#include "cam_mem_mgr.h" +#include "cam_packet_util.h" +#include "cam_debug_util.h" + +int cam_packet_util_get_cmd_mem_addr(int handle, uint32_t **buf_addr, + size_t *len) +{ + int rc = 0; + uintptr_t kmd_buf_addr = 0; + + rc = cam_mem_get_cpu_buf(handle, &kmd_buf_addr, len); + if (rc) { + CAM_ERR(CAM_UTIL, "Unable to get the virtual address %d", rc); + } else { + if (kmd_buf_addr && *len) { + *buf_addr = (uint32_t *)kmd_buf_addr; + } else { + CAM_ERR(CAM_UTIL, "Invalid addr and length :%zd", *len); + rc = -ENOMEM; + } + } + return rc; +} + +int cam_packet_util_validate_cmd_desc(struct cam_cmd_buf_desc *cmd_desc) +{ + if ((cmd_desc->length > cmd_desc->size) || + (cmd_desc->mem_handle <= 0)) { + CAM_ERR(CAM_UTIL, "invalid cmd arg %d %d %d %d", + cmd_desc->offset, cmd_desc->length, + cmd_desc->mem_handle, cmd_desc->size); + return -EINVAL; + } + + return 0; +} + +int cam_packet_util_validate_packet(struct cam_packet *packet, + size_t remain_len) +{ + size_t sum_cmd_desc = 0; + size_t sum_io_cfgs = 0; + size_t sum_patch_desc = 0; + size_t pkt_wo_payload = 0; + + if (!packet) + return -EINVAL; + + if ((size_t)packet->header.size > remain_len) { + CAM_ERR(CAM_UTIL, + "Invalid packet size: %zu, CPU buf length: %zu", + (size_t)packet->header.size, remain_len); + return -EINVAL; + } + + + CAM_DBG(CAM_UTIL, "num cmd buf:%d num of io config:%d kmd buf index:%d", + packet->num_cmd_buf, packet->num_io_configs, + packet->kmd_cmd_buf_index); + + sum_cmd_desc = packet->num_cmd_buf * sizeof(struct cam_cmd_buf_desc); + sum_io_cfgs = packet->num_io_configs * sizeof(struct cam_buf_io_cfg); + sum_patch_desc = packet->num_patches * sizeof(struct cam_patch_desc); + pkt_wo_payload = offsetof(struct cam_packet, payload); + + if ((!packet->header.size) || + ((pkt_wo_payload + (size_t)packet->cmd_buf_offset + + sum_cmd_desc) > (size_t)packet->header.size) || + ((pkt_wo_payload + (size_t)packet->io_configs_offset + + sum_io_cfgs) > (size_t)packet->header.size) || + ((pkt_wo_payload + (size_t)packet->patch_offset + + sum_patch_desc) > (size_t)packet->header.size)) { + CAM_ERR(CAM_UTIL, "params not within mem len:%zu %zu %zu %zu", + (size_t)packet->header.size, sum_cmd_desc, + sum_io_cfgs, sum_patch_desc); + return -EINVAL; + } + + return 0; +} + +int cam_packet_util_get_kmd_buffer(struct cam_packet *packet, + struct cam_kmd_buf_info *kmd_buf) +{ + int rc = 0; + size_t len = 0; + size_t remain_len = 0; + struct cam_cmd_buf_desc *cmd_desc; + uint32_t *cpu_addr; + + if (!packet || !kmd_buf) { + CAM_ERR(CAM_UTIL, "Invalid arg %pK %pK", packet, kmd_buf); + return -EINVAL; + } + + if ((packet->kmd_cmd_buf_index < 0) || + (packet->kmd_cmd_buf_index >= packet->num_cmd_buf)) { + CAM_ERR(CAM_UTIL, "Invalid kmd buf index: %d", + packet->kmd_cmd_buf_index); + return -EINVAL; + } + + /* Take first command descriptor and add offset to it for kmd*/ + cmd_desc = (struct cam_cmd_buf_desc *) ((uint8_t *) + &packet->payload + packet->cmd_buf_offset); + cmd_desc += packet->kmd_cmd_buf_index; + + rc = cam_packet_util_validate_cmd_desc(cmd_desc); + if (rc) + return rc; + + rc = cam_packet_util_get_cmd_mem_addr(cmd_desc->mem_handle, &cpu_addr, + &len); + if (rc) + return rc; + + remain_len = len; + if (((size_t)cmd_desc->offset >= len) || + ((size_t)cmd_desc->size > (len - (size_t)cmd_desc->offset))) { + CAM_ERR(CAM_UTIL, "invalid memory len:%zd and cmd desc size:%d", + len, cmd_desc->size); + rc = -EINVAL; + goto rel_kmd_buf; + } + + remain_len -= (size_t)cmd_desc->offset; + if ((size_t)packet->kmd_cmd_buf_offset >= remain_len) { + CAM_ERR(CAM_UTIL, "Invalid kmd cmd buf offset: %zu", + (size_t)packet->kmd_cmd_buf_offset); + rc = -EINVAL; + goto rel_kmd_buf; + } + + cpu_addr += (cmd_desc->offset / 4) + (packet->kmd_cmd_buf_offset / 4); + CAM_DBG(CAM_UTIL, "total size %d, cmd size: %d, KMD buffer size: %d", + cmd_desc->size, cmd_desc->length, + cmd_desc->size - cmd_desc->length); + CAM_DBG(CAM_UTIL, "hdl 0x%x, cmd offset %d, kmd offset %d, addr 0x%pK", + cmd_desc->mem_handle, cmd_desc->offset, + packet->kmd_cmd_buf_offset, cpu_addr); + + kmd_buf->cpu_addr = cpu_addr; + kmd_buf->handle = cmd_desc->mem_handle; + kmd_buf->offset = cmd_desc->offset + packet->kmd_cmd_buf_offset; + kmd_buf->size = cmd_desc->size - cmd_desc->length; + kmd_buf->used_bytes = 0; + +rel_kmd_buf: + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + return rc; +} + +void cam_packet_dump_patch_info(struct cam_packet *packet, + int32_t iommu_hdl, int32_t sec_mmu_hdl) +{ + struct cam_patch_desc *patch_desc = NULL; + dma_addr_t iova_addr; + size_t dst_buf_len; + size_t src_buf_size; + int i, rc = 0; + int32_t hdl; + uintptr_t cpu_addr = 0; + uint32_t *dst_cpu_addr; + uint64_t value = 0; + + patch_desc = (struct cam_patch_desc *) + ((uint32_t *) &packet->payload + + packet->patch_offset/4); + + CAM_INFO(CAM_UTIL, "Total num of patches : %d", + packet->num_patches); + + for (i = 0; i < packet->num_patches; i++) { + hdl = cam_mem_is_secure_buf(patch_desc[i].src_buf_hdl) ? + sec_mmu_hdl : iommu_hdl; + rc = cam_mem_get_io_buf(patch_desc[i].src_buf_hdl, + hdl, &iova_addr, &src_buf_size); + if (rc < 0) { + CAM_ERR(CAM_UTIL, + "unable to get src buf address for hdl 0x%x", + hdl); + return; + } + + rc = cam_mem_get_cpu_buf(patch_desc[i].dst_buf_hdl, + &cpu_addr, &dst_buf_len); + if (rc < 0 || !cpu_addr || (dst_buf_len == 0)) { + CAM_ERR(CAM_UTIL, "unable to get dst buf address"); + return; + } + + dst_cpu_addr = (uint32_t *)cpu_addr; + dst_cpu_addr = (uint32_t *)((uint8_t *)dst_cpu_addr + + patch_desc[i].dst_offset); + value = *((uint64_t *)dst_cpu_addr); + CAM_INFO(CAM_UTIL, + "i = %d src_buf 0x%llx src_hdl 0x%x src_buf_with_offset 0x%llx size 0x%llx dst %p dst_offset %u dst_hdl 0x%x value 0x%llx", + i, iova_addr, patch_desc[i].src_buf_hdl, + (iova_addr + patch_desc[i].src_offset), + src_buf_size, dst_cpu_addr, + patch_desc[i].dst_offset, + patch_desc[i].dst_buf_hdl, value); + + if (!(*dst_cpu_addr)) + CAM_ERR(CAM_ICP, "Null at dst addr %p", dst_cpu_addr); + + cam_mem_put_cpu_buf(patch_desc[i].dst_buf_hdl); + } +} + +int cam_packet_util_process_patches(struct cam_packet *packet, + int32_t iommu_hdl, int32_t sec_mmu_hdl) +{ + struct cam_patch_desc *patch_desc = NULL; + dma_addr_t iova_addr; + uintptr_t cpu_addr = 0; + uint32_t temp; + uint32_t *dst_cpu_addr; + uint32_t *src_buf_iova_addr; + size_t dst_buf_len; + size_t src_buf_size; + int i; + int rc = 0; + int32_t hdl; + + /* process patch descriptor */ + patch_desc = (struct cam_patch_desc *) + ((uint32_t *) &packet->payload + + packet->patch_offset/4); + CAM_DBG(CAM_UTIL, "packet = %pK patch_desc = %pK size = %lu", + (void *)packet, (void *)patch_desc, + sizeof(struct cam_patch_desc)); + + for (i = 0; i < packet->num_patches; i++) { + hdl = cam_mem_is_secure_buf(patch_desc[i].src_buf_hdl) ? + sec_mmu_hdl : iommu_hdl; + rc = cam_mem_get_io_buf(patch_desc[i].src_buf_hdl, + hdl, &iova_addr, &src_buf_size); + if (rc < 0) { + CAM_ERR(CAM_UTIL, "unable to get src buf address"); + return rc; + } + src_buf_iova_addr = (uint32_t *)iova_addr; + temp = iova_addr; + + rc = cam_mem_get_cpu_buf(patch_desc[i].dst_buf_hdl, + &cpu_addr, &dst_buf_len); + if (rc < 0 || !cpu_addr || (dst_buf_len == 0)) { + CAM_ERR(CAM_UTIL, "unable to get dst buf address"); + return rc; + } + dst_cpu_addr = (uint32_t *)cpu_addr; + + CAM_DBG(CAM_UTIL, "i = %d patch info = %x %x %x %x", i, + patch_desc[i].dst_buf_hdl, patch_desc[i].dst_offset, + patch_desc[i].src_buf_hdl, patch_desc[i].src_offset); + + if ((size_t)patch_desc[i].src_offset >= src_buf_size) { + CAM_ERR(CAM_UTIL, + "Invalid src buf patch offset"); + return -EINVAL; + } + + if ((dst_buf_len < sizeof(void *)) || + ((dst_buf_len - sizeof(void *)) < + (size_t)patch_desc[i].dst_offset)) { + CAM_ERR(CAM_UTIL, + "Invalid dst buf patch offset"); + cam_mem_put_cpu_buf((int32_t)patch_desc[i].dst_buf_hdl); + return -EINVAL; + } + + dst_cpu_addr = (uint32_t *)((uint8_t *)dst_cpu_addr + + patch_desc[i].dst_offset); + temp += patch_desc[i].src_offset; + + *dst_cpu_addr = temp; + + CAM_DBG(CAM_UTIL, + "patch is done for dst %pK with src %pK value %llx", + dst_cpu_addr, src_buf_iova_addr, + *((uint64_t *)dst_cpu_addr)); + cam_mem_put_cpu_buf((int32_t)patch_desc[i].dst_buf_hdl); + } + + return rc; +} + +int cam_packet_util_process_generic_cmd_buffer( + struct cam_cmd_buf_desc *cmd_buf, + cam_packet_generic_blob_handler blob_handler_cb, void *user_data) +{ + int rc = 0; + uintptr_t cpu_addr = 0; + size_t buf_size; + size_t remain_len = 0; + uint32_t *blob_ptr; + uint32_t blob_type, blob_size, blob_block_size, len_read; + + if (!cmd_buf || !blob_handler_cb) { + CAM_ERR(CAM_UTIL, "Invalid args %pK %pK", + cmd_buf, blob_handler_cb); + return -EINVAL; + } + + if (!cmd_buf->length || !cmd_buf->size) { + CAM_ERR(CAM_UTIL, "Invalid cmd buf size %d %d", + cmd_buf->length, cmd_buf->size); + return -EINVAL; + } + + rc = cam_mem_get_cpu_buf(cmd_buf->mem_handle, &cpu_addr, &buf_size); + if (rc || !cpu_addr || (buf_size == 0)) { + CAM_ERR(CAM_UTIL, "Failed in Get cpu addr, rc=%d, cpu_addr=%pK", + rc, (void *)cpu_addr); + return rc; + } + + remain_len = buf_size; + if ((buf_size < sizeof(uint32_t)) || + ((size_t)cmd_buf->offset > (buf_size - sizeof(uint32_t)))) { + CAM_ERR(CAM_UTIL, "Invalid offset for cmd buf: %zu", + (size_t)cmd_buf->offset); + rc = -EINVAL; + goto end; + } + remain_len -= (size_t)cmd_buf->offset; + + if (remain_len < (size_t)cmd_buf->length) { + CAM_ERR(CAM_UTIL, "Invalid length for cmd buf: %zu", + (size_t)cmd_buf->length); + rc = -EINVAL; + goto end; + } + + blob_ptr = (uint32_t *)(((uint8_t *)cpu_addr) + + cmd_buf->offset); + + CAM_DBG(CAM_UTIL, + "GenericCmdBuffer cpuaddr=%pK, blobptr=%pK, len=%d", + (void *)cpu_addr, (void *)blob_ptr, cmd_buf->length); + + len_read = 0; + while (len_read < cmd_buf->length) { + blob_type = + ((*blob_ptr) & CAM_GENERIC_BLOB_CMDBUFFER_TYPE_MASK) >> + CAM_GENERIC_BLOB_CMDBUFFER_TYPE_SHIFT; + blob_size = + ((*blob_ptr) & CAM_GENERIC_BLOB_CMDBUFFER_SIZE_MASK) >> + CAM_GENERIC_BLOB_CMDBUFFER_SIZE_SHIFT; + + blob_block_size = sizeof(uint32_t) + + (((blob_size + sizeof(uint32_t) - 1) / + sizeof(uint32_t)) * sizeof(uint32_t)); + + CAM_DBG(CAM_UTIL, + "Blob type=%d size=%d block_size=%d len_read=%d total=%d", + blob_type, blob_size, blob_block_size, len_read, + cmd_buf->length); + + if (len_read + blob_block_size > cmd_buf->length) { + CAM_ERR(CAM_UTIL, "Invalid Blob %d %d %d %d", + blob_type, blob_size, len_read, + cmd_buf->length); + rc = -EINVAL; + goto end; + } + + len_read += blob_block_size; + + rc = blob_handler_cb(user_data, blob_type, blob_size, + (uint8_t *)(blob_ptr + 1)); + if (rc) { + CAM_ERR(CAM_UTIL, "Error in handling blob type %d %d", + blob_type, blob_size); + goto end; + } + + blob_ptr += (blob_block_size / sizeof(uint32_t)); + } + +end: + cam_mem_put_cpu_buf(cmd_buf->mem_handle); + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_packet_util.h b/techpack/camera-bengal/drivers/cam_utils/cam_packet_util.h new file mode 100644 index 0000000000000000000000000000000000000000..94e8fd5529ee681893f952ba1c302cf7f0c59fcd --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_packet_util.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CAM_PACKET_UTIL_H_ +#define _CAM_PACKET_UTIL_H_ + +#include + +/** + * @brief KMD scratch buffer information + * + * @handle: Memory handle + * @cpu_addr: Cpu address + * @offset: Offset from the start of the buffer + * @size: Size of the buffer + * @used_bytes: Used memory in bytes + * + */ +struct cam_kmd_buf_info { + int handle; + uint32_t *cpu_addr; + uint32_t offset; + uint32_t size; + uint32_t used_bytes; +}; + +/* Generic Cmd Buffer blob callback function type */ +typedef int (*cam_packet_generic_blob_handler)(void *user_data, + uint32_t blob_type, uint32_t blob_size, uint8_t *blob_data); + +/** + * cam_packet_util_get_cmd_mem_addr() + * + * @brief Get command buffer address + * + * @handle: Command buffer memory handle + * @buf_addr: Command buffer cpu mapped address + * @len: Command buffer length + * + * @return: 0 for success + * -EINVAL for Fail + */ +int cam_packet_util_get_cmd_mem_addr(int handle, uint32_t **buf_addr, + size_t *len); + +/** + * cam_packet_util_validate_packet() + * + * @brief Validate the packet + * + * @packet: Packet to be validated + * + * @remain_len: CPU buff length after config offset + * + * @return: 0 for success + * -EINVAL for Fail + */ +int cam_packet_util_validate_packet(struct cam_packet *packet, + size_t remain_len); + +/** + * cam_packet_util_validate_cmd_desc() + * + * @brief Validate the packet + * + * @cmd_desc: Command descriptor to be validated + * + * @return: 0 for success + * -EINVAL for Fail + */ +int cam_packet_util_validate_cmd_desc(struct cam_cmd_buf_desc *cmd_desc); + +/** + * cam_packet_util_get_kmd_buffer() + * + * @brief Get the kmd buffer from the packet command descriptor + * + * @packet: Packet data + * @kmd_buf: Extracted the KMD buffer information + * + * @return: 0 for success + * -EINVAL for Fail + */ +int cam_packet_util_get_kmd_buffer(struct cam_packet *packet, + struct cam_kmd_buf_info *kmd_buf_info); + +/** + * cam_packet_dump_patch_info() + * + * @brief: Dump patch info in case of page fault + * + * @packet: Input packet containing Command Buffers and Patches + * @iommu_hdl: IOMMU handle of the HW Device that received the packet + * @sec_iommu_hdl: Secure IOMMU handle of the HW Device that + * received the packet + * + */ +void cam_packet_dump_patch_info(struct cam_packet *packet, + int32_t iommu_hdl, int32_t sec_mmu_hdl); + +/** + * cam_packet_util_process_patches() + * + * @brief: Replace the handle in Packet to Address using the + * information from patches. + * + * @packet: Input packet containing Command Buffers and Patches + * @iommu_hdl: IOMMU handle of the HW Device that received the packet + * @sec_iommu_hdl: Secure IOMMU handle of the HW Device that + * received the packet + * + * @return: 0: Success + * Negative: Failure + */ +int cam_packet_util_process_patches(struct cam_packet *packet, + int32_t iommu_hdl, int32_t sec_mmu_hdl); + +/** + * cam_packet_util_process_generic_cmd_buffer() + * + * @brief: Process Generic Blob command buffer. This utility + * function process the command buffer and calls the + * blob_handle_cb callback for each blob that exists + * in the command buffer. + * + * @cmd_buf: Generic Blob Cmd Buffer handle + * @blob_handler_cb: Callback pointer to call for each blob exists in the + * command buffer + * @user_data: User data to be passed while callback + * + * @return: 0: Success + * Negative: Failure + */ +int cam_packet_util_process_generic_cmd_buffer( + struct cam_cmd_buf_desc *cmd_buf, + cam_packet_generic_blob_handler blob_handler_cb, void *user_data); + +#endif /* _CAM_PACKET_UTIL_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_soc_util.c b/techpack/camera-bengal/drivers/cam_utils/cam_soc_util.c new file mode 100644 index 0000000000000000000000000000000000000000..5c0ca1980a5152e0965a26a2c5cf3b8c0b5a89b8 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_soc_util.c @@ -0,0 +1,2506 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "cam_soc_util.h" +#include "cam_debug_util.h" +#include "cam_cx_ipeak.h" +#include "cam_mem_mgr.h" + +static char supported_clk_info[256]; +static char debugfs_dir_name[64]; + +int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info, + int64_t clk_rate, int clk_idx, int32_t *clk_lvl) +{ + int i; + long clk_rate_round; + + if (!soc_info || (clk_idx < 0) || (clk_idx >= CAM_SOC_MAX_CLK)) { + CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d", clk_idx); + *clk_lvl = -1; + return -EINVAL; + } + + clk_rate_round = clk_round_rate(soc_info->clk[clk_idx], clk_rate); + if (clk_rate_round < 0) { + CAM_ERR(CAM_UTIL, "round failed rc = %ld", + clk_rate_round); + *clk_lvl = -1; + return -EINVAL; + } + + for (i = 0; i < CAM_MAX_VOTE; i++) { + if ((soc_info->clk_level_valid[i]) && + (soc_info->clk_rate[i][clk_idx] >= + clk_rate_round)) { + CAM_DBG(CAM_UTIL, + "soc = %d round rate = %ld actual = %lld", + soc_info->clk_rate[i][clk_idx], + clk_rate_round, clk_rate); + *clk_lvl = i; + return 0; + } + } + + CAM_WARN(CAM_UTIL, "Invalid clock rate %ld", clk_rate_round); + *clk_lvl = -1; + return -EINVAL; +} + +/** + * cam_soc_util_get_string_from_level() + * + * @brief: Returns the string for a given clk level + * + * @level: Clock level + * + * @return: String corresponding to the clk level + */ +static const char *cam_soc_util_get_string_from_level( + enum cam_vote_level level) +{ + switch (level) { + case CAM_SUSPEND_VOTE: + return ""; + case CAM_MINSVS_VOTE: + return "MINSVS[1]"; + case CAM_LOWSVS_VOTE: + return "LOWSVS[2]"; + case CAM_SVS_VOTE: + return "SVS[3]"; + case CAM_SVSL1_VOTE: + return "SVSL1[4]"; + case CAM_NOMINAL_VOTE: + return "NOM[5]"; + case CAM_NOMINALL1_VOTE: + return "NOML1[6]"; + case CAM_TURBO_VOTE: + return "TURBO[7]"; + default: + return ""; + } +} + +/** + * cam_soc_util_get_supported_clk_levels() + * + * @brief: Returns the string of all the supported clk levels for + * the given device + * + * @soc_info: Device soc information + * + * @return: String containing all supported clk levels + */ +static const char *cam_soc_util_get_supported_clk_levels( + struct cam_hw_soc_info *soc_info) +{ + int i = 0; + + memset(supported_clk_info, 0, sizeof(supported_clk_info)); + strlcat(supported_clk_info, "Supported levels: ", + sizeof(supported_clk_info)); + + for (i = 0; i < CAM_MAX_VOTE; i++) { + if (soc_info->clk_level_valid[i] == true) { + strlcat(supported_clk_info, + cam_soc_util_get_string_from_level(i), + sizeof(supported_clk_info)); + strlcat(supported_clk_info, " ", + sizeof(supported_clk_info)); + } + } + + strlcat(supported_clk_info, "\n", sizeof(supported_clk_info)); + return supported_clk_info; +} + +static int cam_soc_util_clk_lvl_options_open(struct inode *inode, + struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static ssize_t cam_soc_util_clk_lvl_options_read(struct file *file, + char __user *clk_info, size_t size_t, loff_t *loff_t) +{ + struct cam_hw_soc_info *soc_info = + (struct cam_hw_soc_info *)file->private_data; + const char *display_string = + cam_soc_util_get_supported_clk_levels(soc_info); + + return simple_read_from_buffer(clk_info, size_t, loff_t, display_string, + strlen(display_string)); +} + +static const struct file_operations cam_soc_util_clk_lvl_options = { + .open = cam_soc_util_clk_lvl_options_open, + .read = cam_soc_util_clk_lvl_options_read, +}; + +static int cam_soc_util_set_clk_lvl(void *data, u64 val) +{ + struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data; + + if (val <= CAM_SUSPEND_VOTE || val >= CAM_MAX_VOTE) + return 0; + + if (soc_info->clk_level_valid[val] == true) + soc_info->clk_level_override = val; + else + soc_info->clk_level_override = 0; + + return 0; +} + +static int cam_soc_util_get_clk_lvl(void *data, u64 *val) +{ + struct cam_hw_soc_info *soc_info = (struct cam_hw_soc_info *)data; + + *val = soc_info->clk_level_override; + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(cam_soc_util_clk_lvl_control, + cam_soc_util_get_clk_lvl, cam_soc_util_set_clk_lvl, "%08llu"); + +/** + * cam_soc_util_create_clk_lvl_debugfs() + * + * @brief: Creates debugfs files to view/control device clk rates + * + * @soc_info: Device soc information + * + * @return: Success or failure + */ +static int cam_soc_util_create_clk_lvl_debugfs( + struct cam_hw_soc_info *soc_info) +{ + struct dentry *dentry = NULL; + + if (!soc_info) { + CAM_ERR(CAM_UTIL, "soc info is NULL"); + return -EINVAL; + } + + if (soc_info->dentry) + return 0; + + memset(debugfs_dir_name, 0, sizeof(debugfs_dir_name)); + strlcat(debugfs_dir_name, "clk_dir_", sizeof(debugfs_dir_name)); + strlcat(debugfs_dir_name, soc_info->dev_name, sizeof(debugfs_dir_name)); + + dentry = soc_info->dentry; + dentry = debugfs_create_dir(debugfs_dir_name, NULL); + if (!dentry) { + CAM_ERR(CAM_UTIL, "failed to create debug directory"); + return -ENOMEM; + } + + if (!debugfs_create_file("clk_lvl_options", 0444, + dentry, soc_info, &cam_soc_util_clk_lvl_options)) { + CAM_ERR(CAM_UTIL, "failed to create clk_lvl_options"); + goto err; + } + + if (!debugfs_create_file("clk_lvl_control", 0644, + dentry, soc_info, &cam_soc_util_clk_lvl_control)) { + CAM_ERR(CAM_UTIL, "failed to create clk_lvl_control"); + goto err; + } + + CAM_DBG(CAM_UTIL, "clk lvl debugfs for %s successfully created", + soc_info->dev_name); + + return 0; + +err: + debugfs_remove_recursive(dentry); + dentry = NULL; + return -ENOMEM; +} + +/** + * cam_soc_util_remove_clk_lvl_debugfs() + * + * @brief: Removes the debugfs files used to view/control + * device clk rates + * + * @soc_info: Device soc information + * + */ +static void cam_soc_util_remove_clk_lvl_debugfs( + struct cam_hw_soc_info *soc_info) +{ + debugfs_remove_recursive(soc_info->dentry); + soc_info->dentry = NULL; +} + +int cam_soc_util_get_level_from_string(const char *string, + enum cam_vote_level *level) +{ + if (!level) + return -EINVAL; + + if (!strcmp(string, "suspend")) { + *level = CAM_SUSPEND_VOTE; + } else if (!strcmp(string, "minsvs")) { + *level = CAM_MINSVS_VOTE; + } else if (!strcmp(string, "lowsvs")) { + *level = CAM_LOWSVS_VOTE; + } else if (!strcmp(string, "svs")) { + *level = CAM_SVS_VOTE; + } else if (!strcmp(string, "svs_l1")) { + *level = CAM_SVSL1_VOTE; + } else if (!strcmp(string, "nominal")) { + *level = CAM_NOMINAL_VOTE; + } else if (!strcmp(string, "nominal_l1")) { + *level = CAM_NOMINALL1_VOTE; + } else if (!strcmp(string, "turbo")) { + *level = CAM_TURBO_VOTE; + } else { + CAM_ERR(CAM_UTIL, "Invalid string %s", string); + return -EINVAL; + } + + return 0; +} + +/** + * cam_soc_util_get_clk_level_to_apply() + * + * @brief: Get the clock level to apply. If the requested level + * is not valid, bump the level to next available valid + * level. If no higher level found, return failure. + * + * @soc_info: Device soc struct to be populated + * @req_level: Requested level + * @apply_level Level to apply + * + * @return: success or failure + */ +static int cam_soc_util_get_clk_level_to_apply( + struct cam_hw_soc_info *soc_info, enum cam_vote_level req_level, + enum cam_vote_level *apply_level) +{ + if (req_level >= CAM_MAX_VOTE) { + CAM_ERR(CAM_UTIL, "Invalid clock level parameter %d", + req_level); + return -EINVAL; + } + + if (soc_info->clk_level_valid[req_level] == true) { + *apply_level = req_level; + } else { + int i; + + for (i = (req_level + 1); i < CAM_MAX_VOTE; i++) + if (soc_info->clk_level_valid[i] == true) { + *apply_level = i; + break; + } + + if (i == CAM_MAX_VOTE) { + CAM_ERR(CAM_UTIL, + "No valid clock level found to apply, req=%d", + req_level); + return -EINVAL; + } + } + + CAM_DBG(CAM_UTIL, "Req level %d, Applying %d", + req_level, *apply_level); + + return 0; +} + +int cam_soc_util_irq_enable(struct cam_hw_soc_info *soc_info) +{ + if (!soc_info) { + CAM_ERR(CAM_UTIL, "Invalid arguments"); + return -EINVAL; + } + + if (!soc_info->irq_line) { + CAM_ERR(CAM_UTIL, "No IRQ line available"); + return -ENODEV; + } + + enable_irq(soc_info->irq_line->start); + + return 0; +} + +int cam_soc_util_irq_disable(struct cam_hw_soc_info *soc_info) +{ + if (!soc_info) { + CAM_ERR(CAM_UTIL, "Invalid arguments"); + return -EINVAL; + } + + if (!soc_info->irq_line) { + CAM_ERR(CAM_UTIL, "No IRQ line available"); + return -ENODEV; + } + + disable_irq(soc_info->irq_line->start); + + return 0; +} + +long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info, + uint32_t clk_index, unsigned long clk_rate) +{ + if (!soc_info || (clk_index >= soc_info->num_clk) || (clk_rate == 0)) { + CAM_ERR(CAM_UTIL, "Invalid input params %pK, %d %lu", + soc_info, clk_index, clk_rate); + return clk_rate; + } + + return clk_round_rate(soc_info->clk[clk_index], clk_rate); +} + +/** + * cam_soc_util_set_clk_rate() + * + * @brief: Sets the given rate for the clk requested for + * + * @clk: Clock structure information for which rate is to be set + * @clk_name: Name of the clock for which rate is being set + * @clk_rate Clock rate to be set + * + * @return: Success or failure + */ +static int cam_soc_util_set_clk_rate(struct clk *clk, const char *clk_name, + int64_t clk_rate) +{ + int rc = 0; + long clk_rate_round; + + if (!clk || !clk_name) + return -EINVAL; + + CAM_DBG(CAM_UTIL, "set %s, rate %lld", clk_name, clk_rate); + if (clk_rate > 0) { + clk_rate_round = clk_round_rate(clk, clk_rate); + CAM_DBG(CAM_UTIL, "new_rate %ld", clk_rate_round); + if (clk_rate_round < 0) { + CAM_ERR(CAM_UTIL, "round failed for clock %s rc = %ld", + clk_name, clk_rate_round); + return clk_rate_round; + } + rc = clk_set_rate(clk, clk_rate_round); + if (rc) { + CAM_ERR(CAM_UTIL, "set_rate failed on %s", clk_name); + return rc; + } + } else if (clk_rate == INIT_RATE) { + clk_rate_round = clk_get_rate(clk); + CAM_DBG(CAM_UTIL, "init new_rate %ld", clk_rate_round); + if (clk_rate_round == 0) { + clk_rate_round = clk_round_rate(clk, 0); + if (clk_rate_round <= 0) { + CAM_ERR(CAM_UTIL, "round rate failed on %s", + clk_name); + return clk_rate_round; + } + } + rc = clk_set_rate(clk, clk_rate_round); + if (rc) { + CAM_ERR(CAM_UTIL, "set_rate failed on %s", clk_name); + return rc; + } + } + + return rc; +} + +int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info, + int64_t clk_rate) +{ + int rc = 0; + int i = 0; + int32_t src_clk_idx; + int32_t scl_clk_idx; + struct clk *clk = NULL; + int32_t apply_level; + uint32_t clk_level_override = 0; + + if (!soc_info || (soc_info->src_clk_idx < 0) || + (soc_info->src_clk_idx >= CAM_SOC_MAX_CLK)) { + CAM_ERR(CAM_UTIL, "Invalid src_clk_idx: %d", + soc_info ? soc_info->src_clk_idx : -1); + return -EINVAL; + } + + src_clk_idx = soc_info->src_clk_idx; + clk_level_override = soc_info->clk_level_override; + if (clk_level_override && clk_rate) + clk_rate = + soc_info->clk_rate[clk_level_override][src_clk_idx]; + + clk = soc_info->clk[src_clk_idx]; + rc = cam_soc_util_get_clk_level(soc_info, clk_rate, src_clk_idx, + &apply_level); + if (rc || (apply_level < 0) || (apply_level >= CAM_MAX_VOTE)) { + CAM_ERR(CAM_UTIL, + "set %s, rate %lld dev_name = %s apply level = %d", + soc_info->clk_name[src_clk_idx], clk_rate, + soc_info->dev_name, apply_level); + return -EINVAL; + } + + CAM_DBG(CAM_UTIL, "set %s, rate %lld dev_name = %s apply level = %d", + soc_info->clk_name[src_clk_idx], clk_rate, + soc_info->dev_name, apply_level); + + if ((soc_info->cam_cx_ipeak_enable) && (clk_rate >= 0)) { + cam_cx_ipeak_update_vote_cx_ipeak(soc_info, + apply_level); + } + + rc = cam_soc_util_set_clk_rate(clk, + soc_info->clk_name[src_clk_idx], clk_rate); + if (rc) { + CAM_ERR(CAM_UTIL, + "SET_RATE Failed: src clk: %s, rate %lld, dev_name = %s rc: %d", + soc_info->clk_name[src_clk_idx], clk_rate, + soc_info->dev_name, rc); + return rc; + } + + /* set clk rate for scalable clk if available */ + + for (i = 0; i < soc_info->scl_clk_count; i++) { + scl_clk_idx = soc_info->scl_clk_idx[i]; + if (scl_clk_idx < 0) { + CAM_DBG(CAM_UTIL, "Scl clk index invalid"); + continue; + } + clk = soc_info->clk[scl_clk_idx]; + rc = cam_soc_util_set_clk_rate(clk, + soc_info->clk_name[scl_clk_idx], + soc_info->clk_rate[apply_level][scl_clk_idx]); + if (rc) { + CAM_WARN(CAM_UTIL, + "SET_RATE Failed: scl clk: %s, rate %d dev_name = %s, rc: %d", + soc_info->clk_name[scl_clk_idx], + soc_info->clk_rate[apply_level][scl_clk_idx], + soc_info->dev_name, rc); + } + } + + return 0; +} + +int cam_soc_util_clk_put(struct clk **clk) +{ + if (!(*clk)) { + CAM_ERR(CAM_UTIL, "Invalid params clk"); + return -EINVAL; + } + + clk_put(*clk); + *clk = NULL; + + return 0; +} + +static struct clk *cam_soc_util_option_clk_get(struct device_node *np, + int index) +{ + struct of_phandle_args clkspec; + struct clk *clk; + int rc; + + if (index < 0) + return ERR_PTR(-EINVAL); + + rc = of_parse_phandle_with_args(np, "clocks-option", "#clock-cells", + index, &clkspec); + if (rc) + return ERR_PTR(rc); + + clk = of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); + + return clk; +} + +int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info, + const char *clk_name, struct clk **clk, int32_t *clk_index, + int32_t *clk_rate) +{ + int index = 0; + int rc = 0; + struct device_node *of_node = NULL; + + if (!soc_info || !clk_name || !clk) { + CAM_ERR(CAM_UTIL, + "Invalid params soc_info %pK clk_name %s clk %pK", + soc_info, clk_name, clk); + return -EINVAL; + } + + of_node = soc_info->dev->of_node; + + index = of_property_match_string(of_node, "clock-names-option", + clk_name); + + if (index < 0) { + CAM_INFO(CAM_UTIL, "No clk data for %s", clk_name); + *clk_index = -1; + *clk = ERR_PTR(-EINVAL); + return -EINVAL; + } + + *clk = cam_soc_util_option_clk_get(of_node, index); + if (IS_ERR(*clk)) { + CAM_ERR(CAM_UTIL, "No clk named %s found. Dev %s", clk_name, + soc_info->dev_name); + *clk_index = -1; + return -EFAULT; + } + *clk_index = index; + + rc = of_property_read_u32_index(of_node, "clock-rates-option", + index, clk_rate); + if (rc) { + CAM_ERR(CAM_UTIL, + "Error reading clock-rates clk_name %s index %d", + clk_name, index); + cam_soc_util_clk_put(clk); + *clk_rate = 0; + return rc; + } + + /* + * Option clocks are assumed to be available to single Device here. + * Hence use INIT_RATE instead of NO_SET_RATE. + */ + *clk_rate = (*clk_rate == 0) ? (int32_t)INIT_RATE : *clk_rate; + + CAM_DBG(CAM_UTIL, "clk_name %s index %d clk_rate %d", + clk_name, *clk_index, *clk_rate); + + return 0; +} + +int cam_soc_util_clk_enable(struct clk *clk, const char *clk_name, + int32_t clk_rate) +{ + int rc = 0; + + if (!clk || !clk_name) + return -EINVAL; + + rc = cam_soc_util_set_clk_rate(clk, clk_name, clk_rate); + if (rc) + return rc; + + rc = clk_prepare_enable(clk); + if (rc) { + CAM_ERR(CAM_UTIL, "enable failed for %s: rc(%d)", clk_name, rc); + return rc; + } + + return rc; +} + +int cam_soc_util_clk_disable(struct clk *clk, const char *clk_name) +{ + if (!clk || !clk_name) + return -EINVAL; + + CAM_DBG(CAM_UTIL, "disable %s", clk_name); + clk_disable_unprepare(clk); + + return 0; +} + +/** + * cam_soc_util_clk_enable_default() + * + * @brief: This function enables the default clocks present + * in soc_info + * + * @soc_info: Device soc struct to be populated + * @clk_level: Clk level to apply while enabling + * + * @return: success or failure + */ +int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info, + enum cam_vote_level clk_level) +{ + int i, rc = 0; + enum cam_vote_level apply_level; + + if ((soc_info->num_clk == 0) || + (soc_info->num_clk >= CAM_SOC_MAX_CLK)) { + CAM_ERR(CAM_UTIL, "Invalid number of clock %d", + soc_info->num_clk); + return -EINVAL; + } + + rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level, + &apply_level); + if (rc) + return rc; + + if (soc_info->cam_cx_ipeak_enable) + cam_cx_ipeak_update_vote_cx_ipeak(soc_info, apply_level); + + for (i = 0; i < soc_info->num_clk; i++) { + rc = cam_soc_util_clk_enable(soc_info->clk[i], + soc_info->clk_name[i], + soc_info->clk_rate[apply_level][i]); + if (rc) + goto clk_disable; + if (soc_info->cam_cx_ipeak_enable) { + CAM_DBG(CAM_UTIL, + "dev name = %s clk name = %s idx = %d\n" + "apply_level = %d clc idx = %d", + soc_info->dev_name, soc_info->clk_name[i], i, + apply_level, i); + } + + } + + return rc; + +clk_disable: + if (soc_info->cam_cx_ipeak_enable) + cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0); + for (i--; i >= 0; i--) { + cam_soc_util_clk_disable(soc_info->clk[i], + soc_info->clk_name[i]); + } + + return rc; +} + +/** + * cam_soc_util_clk_disable_default() + * + * @brief: This function disables the default clocks present + * in soc_info + * + * @soc_info: device soc struct to be populated + * + * @return: success or failure + */ +void cam_soc_util_clk_disable_default(struct cam_hw_soc_info *soc_info) +{ + int i; + + if (soc_info->num_clk == 0) + return; + + if (soc_info->cam_cx_ipeak_enable) + cam_cx_ipeak_unvote_cx_ipeak(soc_info); + for (i = soc_info->num_clk - 1; i >= 0; i--) + cam_soc_util_clk_disable(soc_info->clk[i], + soc_info->clk_name[i]); +} + +/** + * cam_soc_util_get_dt_clk_info() + * + * @brief: Parse the DT and populate the Clock properties + * + * @soc_info: device soc struct to be populated + * @src_clk_str name of src clock that has rate control + * + * @return: success or failure + */ +static int cam_soc_util_get_dt_clk_info(struct cam_hw_soc_info *soc_info) +{ + struct device_node *of_node = NULL; + int count; + int num_clk_rates, num_clk_levels; + int i, j, rc; + int32_t num_clk_level_strings; + const char *src_clk_str = NULL; + const char *scl_clk_str = NULL; + const char *clk_control_debugfs = NULL; + const char *clk_cntl_lvl_string = NULL; + enum cam_vote_level level; + + if (!soc_info || !soc_info->dev) + return -EINVAL; + + of_node = soc_info->dev->of_node; + + if (!of_property_read_bool(of_node, "use-shared-clk")) { + CAM_DBG(CAM_UTIL, "No shared clk parameter defined"); + soc_info->use_shared_clk = false; + } else { + soc_info->use_shared_clk = true; + } + + count = of_property_count_strings(of_node, "clock-names"); + + CAM_DBG(CAM_UTIL, "E: dev_name = %s count = %d", + soc_info->dev_name, count); + if (count > CAM_SOC_MAX_CLK) { + CAM_ERR(CAM_UTIL, "invalid count of clocks, count=%d", count); + rc = -EINVAL; + return rc; + } + if (count <= 0) { + CAM_DBG(CAM_UTIL, "No clock-names found"); + count = 0; + soc_info->num_clk = count; + return 0; + } + soc_info->num_clk = count; + + for (i = 0; i < count; i++) { + rc = of_property_read_string_index(of_node, "clock-names", + i, &(soc_info->clk_name[i])); + CAM_DBG(CAM_UTIL, "clock-names[%d] = %s", + i, soc_info->clk_name[i]); + if (rc) { + CAM_ERR(CAM_UTIL, + "i= %d count= %d reading clock-names failed", + i, count); + return rc; + } + } + + num_clk_rates = of_property_count_u32_elems(of_node, "clock-rates"); + if (num_clk_rates <= 0) { + CAM_ERR(CAM_UTIL, "reading clock-rates count failed"); + return -EINVAL; + } + + if ((num_clk_rates % soc_info->num_clk) != 0) { + CAM_ERR(CAM_UTIL, + "mismatch clk/rates, No of clocks=%d, No of rates=%d", + soc_info->num_clk, num_clk_rates); + return -EINVAL; + } + + num_clk_levels = (num_clk_rates / soc_info->num_clk); + + num_clk_level_strings = of_property_count_strings(of_node, + "clock-cntl-level"); + if (num_clk_level_strings != num_clk_levels) { + CAM_ERR(CAM_UTIL, + "Mismatch No of levels=%d, No of level string=%d", + num_clk_levels, num_clk_level_strings); + return -EINVAL; + } + + for (i = 0; i < num_clk_levels; i++) { + rc = of_property_read_string_index(of_node, + "clock-cntl-level", i, &clk_cntl_lvl_string); + if (rc) { + CAM_ERR(CAM_UTIL, + "Error reading clock-cntl-level, rc=%d", rc); + return rc; + } + + rc = cam_soc_util_get_level_from_string(clk_cntl_lvl_string, + &level); + if (rc) + return rc; + + CAM_DBG(CAM_UTIL, + "[%d] : %s %d", i, clk_cntl_lvl_string, level); + soc_info->clk_level_valid[level] = true; + for (j = 0; j < soc_info->num_clk; j++) { + rc = of_property_read_u32_index(of_node, "clock-rates", + ((i * soc_info->num_clk) + j), + &soc_info->clk_rate[level][j]); + if (rc) { + CAM_ERR(CAM_UTIL, + "Error reading clock-rates, rc=%d", + rc); + return rc; + } + + soc_info->clk_rate[level][j] = + (soc_info->clk_rate[level][j] == 0) ? + (int32_t)NO_SET_RATE : + soc_info->clk_rate[level][j]; + + CAM_DBG(CAM_UTIL, "soc_info->clk_rate[%d][%d] = %d", + level, j, + soc_info->clk_rate[level][j]); + } + } + + soc_info->src_clk_idx = -1; + rc = of_property_read_string_index(of_node, "src-clock-name", 0, + &src_clk_str); + if (rc || !src_clk_str) { + CAM_DBG(CAM_UTIL, "No src_clk_str found"); + rc = 0; + goto end; + } + + for (i = 0; i < soc_info->num_clk; i++) { + if (strcmp(soc_info->clk_name[i], src_clk_str) == 0) { + soc_info->src_clk_idx = i; + CAM_DBG(CAM_UTIL, "src clock = %s, index = %d", + src_clk_str, i); + break; + } + } + + /* scalable clk info parsing */ + soc_info->scl_clk_count = 0; + soc_info->scl_clk_count = of_property_count_strings(of_node, + "scl-clk-names"); + if ((soc_info->scl_clk_count <= 0) || + (soc_info->scl_clk_count > CAM_SOC_MAX_CLK)) { + if (soc_info->scl_clk_count == -EINVAL) { + CAM_DBG(CAM_UTIL, "scl_clk_name prop not avialable"); + } else if ((soc_info->scl_clk_count == -ENODATA) || + (soc_info->scl_clk_count > CAM_SOC_MAX_CLK)) { + CAM_ERR(CAM_UTIL, "Invalid scl_clk_count: %d", + soc_info->scl_clk_count); + return -EINVAL; + } + CAM_DBG(CAM_UTIL, "Invalid scl_clk count: %d", + soc_info->scl_clk_count); + soc_info->scl_clk_count = -1; + } else { + CAM_DBG(CAM_UTIL, "No of scalable clocks: %d", + soc_info->scl_clk_count); + for (i = 0; i < soc_info->scl_clk_count; i++) { + rc = of_property_read_string_index(of_node, + "scl-clk-names", i, + (const char **)&scl_clk_str); + if (rc || !scl_clk_str) { + CAM_WARN(CAM_UTIL, "scl_clk_str is NULL"); + soc_info->scl_clk_idx[i] = -1; + continue; + } + for (j = 0; j < soc_info->num_clk; j++) { + if (strnstr(scl_clk_str, soc_info->clk_name[j], + strlen(scl_clk_str))) { + soc_info->scl_clk_idx[i] = j; + CAM_DBG(CAM_UTIL, + "scl clock = %s, index = %d", + scl_clk_str, j); + break; + } + } + } + } + + rc = of_property_read_string_index(of_node, + "clock-control-debugfs", 0, &clk_control_debugfs); + if (rc || !clk_control_debugfs) { + CAM_DBG(CAM_UTIL, "No clock_control_debugfs property found"); + rc = 0; + goto end; + } + + if (strcmp("true", clk_control_debugfs) == 0) + soc_info->clk_control_enable = true; + + CAM_DBG(CAM_UTIL, "X: dev_name = %s count = %d", + soc_info->dev_name, count); +end: + return rc; +} + +int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info, + enum cam_vote_level clk_level) +{ + int i, rc = 0; + enum cam_vote_level apply_level; + + if ((soc_info->num_clk == 0) || + (soc_info->num_clk >= CAM_SOC_MAX_CLK)) { + CAM_ERR(CAM_UTIL, "Invalid number of clock %d", + soc_info->num_clk); + return -EINVAL; + } + + rc = cam_soc_util_get_clk_level_to_apply(soc_info, clk_level, + &apply_level); + if (rc) + return rc; + + if (soc_info->cam_cx_ipeak_enable) + cam_cx_ipeak_update_vote_cx_ipeak(soc_info, apply_level); + + for (i = 0; i < soc_info->num_clk; i++) { + rc = cam_soc_util_set_clk_rate(soc_info->clk[i], + soc_info->clk_name[i], + soc_info->clk_rate[apply_level][i]); + if (rc < 0) { + CAM_DBG(CAM_UTIL, + "dev name = %s clk_name = %s idx = %d\n" + "apply_level = %d", + soc_info->dev_name, soc_info->clk_name[i], + i, apply_level); + if (soc_info->cam_cx_ipeak_enable) + cam_cx_ipeak_update_vote_cx_ipeak(soc_info, 0); + break; + } + } + + return rc; +}; + +static int cam_soc_util_get_dt_gpio_req_tbl(struct device_node *of_node, + struct cam_soc_gpio_data *gconf, uint16_t *gpio_array, + uint16_t gpio_array_size) +{ + int32_t rc = 0, i = 0; + uint32_t count = 0; + uint32_t *val_array = NULL; + + if (!of_get_property(of_node, "gpio-req-tbl-num", &count)) + return 0; + + count /= sizeof(uint32_t); + if (!count) { + CAM_ERR(CAM_UTIL, "gpio-req-tbl-num 0"); + return 0; + } + + val_array = kcalloc(count, sizeof(uint32_t), GFP_KERNEL); + if (!val_array) + return -ENOMEM; + + gconf->cam_gpio_req_tbl = kcalloc(count, sizeof(struct gpio), + GFP_KERNEL); + if (!gconf->cam_gpio_req_tbl) { + rc = -ENOMEM; + goto free_val_array; + } + gconf->cam_gpio_req_tbl_size = count; + + rc = of_property_read_u32_array(of_node, "gpio-req-tbl-num", + val_array, count); + if (rc) { + CAM_ERR(CAM_UTIL, "failed in reading gpio-req-tbl-num, rc = %d", + rc); + goto free_gpio_req_tbl; + } + + for (i = 0; i < count; i++) { + if (val_array[i] >= gpio_array_size) { + CAM_ERR(CAM_UTIL, "gpio req tbl index %d invalid", + val_array[i]); + goto free_gpio_req_tbl; + } + gconf->cam_gpio_req_tbl[i].gpio = gpio_array[val_array[i]]; + CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].gpio = %d", i, + gconf->cam_gpio_req_tbl[i].gpio); + } + + rc = of_property_read_u32_array(of_node, "gpio-req-tbl-flags", + val_array, count); + if (rc) { + CAM_ERR(CAM_UTIL, "Failed in gpio-req-tbl-flags, rc %d", rc); + goto free_gpio_req_tbl; + } + + for (i = 0; i < count; i++) { + gconf->cam_gpio_req_tbl[i].flags = val_array[i]; + CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].flags = %ld", i, + gconf->cam_gpio_req_tbl[i].flags); + } + + for (i = 0; i < count; i++) { + rc = of_property_read_string_index(of_node, + "gpio-req-tbl-label", i, + &gconf->cam_gpio_req_tbl[i].label); + if (rc) { + CAM_ERR(CAM_UTIL, "Failed rc %d", rc); + goto free_gpio_req_tbl; + } + CAM_DBG(CAM_UTIL, "cam_gpio_req_tbl[%d].label = %s", i, + gconf->cam_gpio_req_tbl[i].label); + } + + kfree(val_array); + + return rc; + +free_gpio_req_tbl: + kfree(gconf->cam_gpio_req_tbl); +free_val_array: + kfree(val_array); + gconf->cam_gpio_req_tbl_size = 0; + + return rc; +} + +static int cam_soc_util_get_gpio_info(struct cam_hw_soc_info *soc_info) +{ + int32_t rc = 0, i = 0; + uint16_t *gpio_array = NULL; + int16_t gpio_array_size = 0; + struct cam_soc_gpio_data *gconf = NULL; + struct device_node *of_node = NULL; + + if (!soc_info || !soc_info->dev) + return -EINVAL; + + of_node = soc_info->dev->of_node; + + /* Validate input parameters */ + if (!of_node) { + CAM_ERR(CAM_UTIL, "Invalid param of_node"); + return -EINVAL; + } + + gpio_array_size = of_gpio_count(of_node); + + if (gpio_array_size <= 0) + return 0; + + CAM_DBG(CAM_UTIL, "gpio count %d", gpio_array_size); + + gpio_array = kcalloc(gpio_array_size, sizeof(uint16_t), GFP_KERNEL); + if (!gpio_array) + goto free_gpio_conf; + + for (i = 0; i < gpio_array_size; i++) { + gpio_array[i] = of_get_gpio(of_node, i); + CAM_DBG(CAM_UTIL, "gpio_array[%d] = %d", i, gpio_array[i]); + } + + gconf = kzalloc(sizeof(*gconf), GFP_KERNEL); + if (!gconf) + return -ENOMEM; + + rc = cam_soc_util_get_dt_gpio_req_tbl(of_node, gconf, gpio_array, + gpio_array_size); + if (rc) { + CAM_ERR(CAM_UTIL, "failed in msm_camera_get_dt_gpio_req_tbl"); + goto free_gpio_array; + } + + gconf->cam_gpio_common_tbl = kcalloc(gpio_array_size, + sizeof(struct gpio), GFP_KERNEL); + if (!gconf->cam_gpio_common_tbl) { + rc = -ENOMEM; + goto free_gpio_array; + } + + for (i = 0; i < gpio_array_size; i++) + gconf->cam_gpio_common_tbl[i].gpio = gpio_array[i]; + + gconf->cam_gpio_common_tbl_size = gpio_array_size; + soc_info->gpio_data = gconf; + kfree(gpio_array); + + return rc; + +free_gpio_array: + kfree(gpio_array); +free_gpio_conf: + kfree(gconf); + soc_info->gpio_data = NULL; + + return rc; +} + +static int cam_soc_util_request_gpio_table( + struct cam_hw_soc_info *soc_info, bool gpio_en) +{ + int rc = 0, i = 0; + uint8_t size = 0; + struct cam_soc_gpio_data *gpio_conf = + soc_info->gpio_data; + struct gpio *gpio_tbl = NULL; + + + if (!gpio_conf) { + CAM_DBG(CAM_UTIL, "No GPIO entry"); + return 0; + } + if (gpio_conf->cam_gpio_common_tbl_size <= 0) { + CAM_ERR(CAM_UTIL, "GPIO table size is invalid"); + return -EINVAL; + } + size = gpio_conf->cam_gpio_req_tbl_size; + gpio_tbl = gpio_conf->cam_gpio_req_tbl; + + if (!gpio_tbl || !size) { + CAM_ERR(CAM_UTIL, "Invalid gpio_tbl %pK / size %d", + gpio_tbl, size); + return -EINVAL; + } + for (i = 0; i < size; i++) { + CAM_DBG(CAM_UTIL, "i=%d, gpio=%d dir=%ld", i, + gpio_tbl[i].gpio, gpio_tbl[i].flags); + } + if (gpio_en) { + for (i = 0; i < size; i++) { + rc = gpio_request_one(gpio_tbl[i].gpio, + gpio_tbl[i].flags, gpio_tbl[i].label); + if (rc) { + /* + * After GPIO request fails, contine to + * apply new gpios, outout a error message + * for driver bringup debug + */ + CAM_ERR(CAM_UTIL, "gpio %d:%s request fails", + gpio_tbl[i].gpio, gpio_tbl[i].label); + } + } + } else { + gpio_free_array(gpio_tbl, size); + } + + return rc; +} + +static int cam_soc_util_get_dt_regulator_info + (struct cam_hw_soc_info *soc_info) +{ + int rc = 0, count = 0, i = 0; + struct device_node *of_node = NULL; + + if (!soc_info || !soc_info->dev) { + CAM_ERR(CAM_UTIL, "Invalid parameters"); + return -EINVAL; + } + + of_node = soc_info->dev->of_node; + + soc_info->num_rgltr = 0; + count = of_property_count_strings(of_node, "regulator-names"); + if (count != -EINVAL) { + if (count <= 0) { + CAM_ERR(CAM_UTIL, "no regulators found"); + count = 0; + return -EINVAL; + } + + soc_info->num_rgltr = count; + + } else { + CAM_DBG(CAM_UTIL, "No regulators node found"); + return 0; + } + + for (i = 0; i < soc_info->num_rgltr; i++) { + rc = of_property_read_string_index(of_node, + "regulator-names", i, &soc_info->rgltr_name[i]); + CAM_DBG(CAM_UTIL, "rgltr_name[%d] = %s", + i, soc_info->rgltr_name[i]); + if (rc) { + CAM_ERR(CAM_UTIL, "no regulator resource at cnt=%d", i); + return -ENODEV; + } + } + + if (!of_property_read_bool(of_node, "rgltr-cntrl-support")) { + CAM_DBG(CAM_UTIL, "No regulator control parameter defined"); + soc_info->rgltr_ctrl_support = false; + return 0; + } + + soc_info->rgltr_ctrl_support = true; + + rc = of_property_read_u32_array(of_node, "rgltr-min-voltage", + soc_info->rgltr_min_volt, soc_info->num_rgltr); + if (rc) { + CAM_ERR(CAM_UTIL, "No minimum volatage value found, rc=%d", rc); + return -EINVAL; + } + + rc = of_property_read_u32_array(of_node, "rgltr-max-voltage", + soc_info->rgltr_max_volt, soc_info->num_rgltr); + if (rc) { + CAM_ERR(CAM_UTIL, "No maximum volatage value found, rc=%d", rc); + return -EINVAL; + } + + rc = of_property_read_u32_array(of_node, "rgltr-load-current", + soc_info->rgltr_op_mode, soc_info->num_rgltr); + if (rc) { + CAM_ERR(CAM_UTIL, "No Load curent found rc=%d", rc); + return -EINVAL; + } + + return rc; +} + +int cam_soc_util_get_dt_properties(struct cam_hw_soc_info *soc_info) +{ + struct device_node *of_node = NULL; + int count = 0, i = 0, rc = 0; + + if (!soc_info || !soc_info->dev) + return -EINVAL; + + of_node = soc_info->dev->of_node; + + rc = of_property_read_u32(of_node, "cell-index", &soc_info->index); + if (rc) { + CAM_ERR(CAM_UTIL, "device %s failed to read cell-index", + soc_info->dev_name); + return rc; + } + + count = of_property_count_strings(of_node, "reg-names"); + if (count <= 0) { + CAM_DBG(CAM_UTIL, "no reg-names found for: %s", + soc_info->dev_name); + count = 0; + } + soc_info->num_mem_block = count; + + for (i = 0; i < soc_info->num_mem_block; i++) { + rc = of_property_read_string_index(of_node, "reg-names", i, + &soc_info->mem_block_name[i]); + if (rc) { + CAM_ERR(CAM_UTIL, "failed to read reg-names at %d", i); + return rc; + } + soc_info->mem_block[i] = + platform_get_resource_byname(soc_info->pdev, + IORESOURCE_MEM, soc_info->mem_block_name[i]); + + if (!soc_info->mem_block[i]) { + CAM_ERR(CAM_UTIL, "no mem resource by name %s", + soc_info->mem_block_name[i]); + rc = -ENODEV; + return rc; + } + } + + rc = of_property_read_string(of_node, "label", &soc_info->label_name); + if (rc) + CAM_DBG(CAM_UTIL, "Label is not available in the node: %d", rc); + + if (soc_info->num_mem_block > 0) { + rc = of_property_read_u32_array(of_node, "reg-cam-base", + soc_info->mem_block_cam_base, soc_info->num_mem_block); + if (rc) { + CAM_ERR(CAM_UTIL, "Error reading register offsets"); + return rc; + } + } + + rc = of_property_read_string_index(of_node, "interrupt-names", 0, + &soc_info->irq_name); + if (rc) { + CAM_DBG(CAM_UTIL, "No interrupt line preset for: %s", + soc_info->dev_name); + rc = 0; + } else { + soc_info->irq_line = + platform_get_resource_byname(soc_info->pdev, + IORESOURCE_IRQ, soc_info->irq_name); + if (!soc_info->irq_line) { + CAM_ERR(CAM_UTIL, "no irq resource"); + rc = -ENODEV; + return rc; + } + } + + rc = of_property_read_string_index(of_node, "compatible", 0, + (const char **)&soc_info->compatible); + if (rc) { + CAM_DBG(CAM_UTIL, "No compatible string present for: %s", + soc_info->dev_name); + rc = 0; + } + + rc = cam_soc_util_get_dt_regulator_info(soc_info); + if (rc) + return rc; + + rc = cam_soc_util_get_dt_clk_info(soc_info); + if (rc) + return rc; + + rc = cam_soc_util_get_gpio_info(soc_info); + if (rc) + return rc; + + if (of_find_property(of_node, "qcom,cam-cx-ipeak", NULL)) + rc = cam_cx_ipeak_register_cx_ipeak(soc_info); + + return rc; +} + +/** + * cam_soc_util_get_regulator() + * + * @brief: Get regulator resource named vdd + * + * @dev: Device associated with regulator + * @reg: Return pointer to be filled with regulator on success + * @rgltr_name: Name of regulator to get + * + * @return: 0 for Success, negative value for failure + */ +static int cam_soc_util_get_regulator(struct device *dev, + struct regulator **reg, const char *rgltr_name) +{ + int rc = 0; + *reg = regulator_get(dev, rgltr_name); + if (IS_ERR_OR_NULL(*reg)) { + rc = PTR_ERR(*reg); + rc = rc ? rc : -EINVAL; + CAM_ERR(CAM_UTIL, "Regulator %s get failed %d", rgltr_name, rc); + *reg = NULL; + } + return rc; +} + +int cam_soc_util_regulator_disable(struct regulator *rgltr, + const char *rgltr_name, uint32_t rgltr_min_volt, + uint32_t rgltr_max_volt, uint32_t rgltr_op_mode, + uint32_t rgltr_delay_ms) +{ + int32_t rc = 0; + + if (!rgltr) { + CAM_ERR(CAM_UTIL, "Invalid NULL parameter"); + return -EINVAL; + } + + rc = regulator_disable(rgltr); + if (rc) { + CAM_ERR(CAM_UTIL, "%s regulator disable failed", rgltr_name); + return rc; + } + + if (rgltr_delay_ms > 20) + msleep(rgltr_delay_ms); + else if (rgltr_delay_ms) + usleep_range(rgltr_delay_ms * 1000, + (rgltr_delay_ms * 1000) + 1000); + + if (regulator_count_voltages(rgltr) > 0) { + regulator_set_load(rgltr, 0); + regulator_set_voltage(rgltr, 0, rgltr_max_volt); + } + + return rc; +} + + +int cam_soc_util_regulator_enable(struct regulator *rgltr, + const char *rgltr_name, + uint32_t rgltr_min_volt, uint32_t rgltr_max_volt, + uint32_t rgltr_op_mode, uint32_t rgltr_delay) +{ + int32_t rc = 0; + + if (!rgltr) { + CAM_ERR(CAM_UTIL, "Invalid NULL parameter"); + return -EINVAL; + } + + if (regulator_count_voltages(rgltr) > 0) { + CAM_DBG(CAM_UTIL, "voltage min=%d, max=%d", + rgltr_min_volt, rgltr_max_volt); + + rc = regulator_set_voltage( + rgltr, rgltr_min_volt, rgltr_max_volt); + if (rc) { + CAM_ERR(CAM_UTIL, "%s set voltage failed", rgltr_name); + return rc; + } + + rc = regulator_set_load(rgltr, rgltr_op_mode); + if (rc) { + CAM_ERR(CAM_UTIL, "%s set optimum mode failed", + rgltr_name); + return rc; + } + } + + rc = regulator_enable(rgltr); + if (rc) { + CAM_ERR(CAM_UTIL, "%s regulator_enable failed", rgltr_name); + return rc; + } + + if (rgltr_delay > 20) + msleep(rgltr_delay); + else if (rgltr_delay) + usleep_range(rgltr_delay * 1000, + (rgltr_delay * 1000) + 1000); + + return rc; +} + +static int cam_soc_util_request_pinctrl( + struct cam_hw_soc_info *soc_info) +{ + + struct cam_soc_pinctrl_info *device_pctrl = &soc_info->pinctrl_info; + struct device *dev = soc_info->dev; + + device_pctrl->pinctrl = devm_pinctrl_get(dev); + if (IS_ERR_OR_NULL(device_pctrl->pinctrl)) { + CAM_DBG(CAM_UTIL, "Pinctrl not available"); + device_pctrl->pinctrl = NULL; + return 0; + } + device_pctrl->gpio_state_active = + pinctrl_lookup_state(device_pctrl->pinctrl, + CAM_SOC_PINCTRL_STATE_DEFAULT); + if (IS_ERR_OR_NULL(device_pctrl->gpio_state_active)) { + CAM_ERR(CAM_UTIL, + "Failed to get the active state pinctrl handle"); + device_pctrl->gpio_state_active = NULL; + return -EINVAL; + } + device_pctrl->gpio_state_suspend + = pinctrl_lookup_state(device_pctrl->pinctrl, + CAM_SOC_PINCTRL_STATE_SLEEP); + if (IS_ERR_OR_NULL(device_pctrl->gpio_state_suspend)) { + CAM_ERR(CAM_UTIL, + "Failed to get the suspend state pinctrl handle"); + device_pctrl->gpio_state_suspend = NULL; + return -EINVAL; + } + return 0; +} + +static void cam_soc_util_regulator_disable_default( + struct cam_hw_soc_info *soc_info) +{ + int j = 0; + uint32_t num_rgltr = soc_info->num_rgltr; + + for (j = num_rgltr-1; j >= 0; j--) { + if (soc_info->rgltr_ctrl_support == true) { + cam_soc_util_regulator_disable(soc_info->rgltr[j], + soc_info->rgltr_name[j], + soc_info->rgltr_min_volt[j], + soc_info->rgltr_max_volt[j], + soc_info->rgltr_op_mode[j], + soc_info->rgltr_delay[j]); + } else { + if (soc_info->rgltr[j]) + regulator_disable(soc_info->rgltr[j]); + } + } +} + +static int cam_soc_util_regulator_enable_default( + struct cam_hw_soc_info *soc_info) +{ + int j = 0, rc = 0; + uint32_t num_rgltr = soc_info->num_rgltr; + + for (j = 0; j < num_rgltr; j++) { + if (soc_info->rgltr_ctrl_support == true) { + rc = cam_soc_util_regulator_enable(soc_info->rgltr[j], + soc_info->rgltr_name[j], + soc_info->rgltr_min_volt[j], + soc_info->rgltr_max_volt[j], + soc_info->rgltr_op_mode[j], + soc_info->rgltr_delay[j]); + } else { + if (soc_info->rgltr[j]) + rc = regulator_enable(soc_info->rgltr[j]); + } + + if (rc) { + CAM_ERR(CAM_UTIL, "%s enable failed", + soc_info->rgltr_name[j]); + goto disable_rgltr; + } + } + + return rc; +disable_rgltr: + + for (j--; j >= 0; j--) { + if (soc_info->rgltr_ctrl_support == true) { + cam_soc_util_regulator_disable(soc_info->rgltr[j], + soc_info->rgltr_name[j], + soc_info->rgltr_min_volt[j], + soc_info->rgltr_max_volt[j], + soc_info->rgltr_op_mode[j], + soc_info->rgltr_delay[j]); + } else { + if (soc_info->rgltr[j]) + regulator_disable(soc_info->rgltr[j]); + } + } + + return rc; +} + +int cam_soc_util_request_platform_resource( + struct cam_hw_soc_info *soc_info, + irq_handler_t handler, void *irq_data) +{ + int i = 0, rc = 0; + + if (!soc_info || !soc_info->dev) { + CAM_ERR(CAM_UTIL, "Invalid parameters"); + return -EINVAL; + } + + for (i = 0; i < soc_info->num_mem_block; i++) { + if (soc_info->reserve_mem) { + if (!request_mem_region(soc_info->mem_block[i]->start, + resource_size(soc_info->mem_block[i]), + soc_info->mem_block_name[i])){ + CAM_ERR(CAM_UTIL, + "Error Mem region request Failed:%s", + soc_info->mem_block_name[i]); + rc = -ENOMEM; + goto unmap_base; + } + } + soc_info->reg_map[i].mem_base = ioremap( + soc_info->mem_block[i]->start, + resource_size(soc_info->mem_block[i])); + if (!soc_info->reg_map[i].mem_base) { + CAM_ERR(CAM_UTIL, "i= %d base NULL", i); + rc = -ENOMEM; + goto unmap_base; + } + soc_info->reg_map[i].mem_cam_base = + soc_info->mem_block_cam_base[i]; + soc_info->reg_map[i].size = + resource_size(soc_info->mem_block[i]); + soc_info->num_reg_map++; + } + + for (i = 0; i < soc_info->num_rgltr; i++) { + if (soc_info->rgltr_name[i] == NULL) { + CAM_ERR(CAM_UTIL, "can't find regulator name"); + goto put_regulator; + } + + rc = cam_soc_util_get_regulator(soc_info->dev, + &soc_info->rgltr[i], + soc_info->rgltr_name[i]); + if (rc) + goto put_regulator; + } + + if (soc_info->irq_line) { + rc = devm_request_irq(soc_info->dev, soc_info->irq_line->start, + handler, IRQF_TRIGGER_RISING, + soc_info->irq_name, irq_data); + if (rc) { + CAM_ERR(CAM_UTIL, "irq request fail"); + rc = -EBUSY; + goto put_regulator; + } + disable_irq(soc_info->irq_line->start); + soc_info->irq_data = irq_data; + } + + /* Get Clock */ + for (i = 0; i < soc_info->num_clk; i++) { + soc_info->clk[i] = clk_get(soc_info->dev, + soc_info->clk_name[i]); + if (!soc_info->clk[i]) { + CAM_ERR(CAM_UTIL, "get failed for %s", + soc_info->clk_name[i]); + rc = -ENOENT; + goto put_clk; + } + } + + rc = cam_soc_util_request_pinctrl(soc_info); + if (rc) + CAM_DBG(CAM_UTIL, "Failed in request pinctrl, rc=%d", rc); + + rc = cam_soc_util_request_gpio_table(soc_info, true); + if (rc) { + CAM_ERR(CAM_UTIL, "Failed in request gpio table, rc=%d", rc); + goto put_clk; + } + + if (soc_info->clk_control_enable) + cam_soc_util_create_clk_lvl_debugfs(soc_info); + + return rc; + +put_clk: + if (i == -1) + i = soc_info->num_clk; + for (i = i - 1; i >= 0; i--) { + if (soc_info->clk[i]) { + clk_put(soc_info->clk[i]); + soc_info->clk[i] = NULL; + } + } + + if (soc_info->irq_line) { + disable_irq(soc_info->irq_line->start); + devm_free_irq(soc_info->dev, + soc_info->irq_line->start, irq_data); + } + +put_regulator: + if (i == -1) + i = soc_info->num_rgltr; + for (i = i - 1; i >= 0; i--) { + if (soc_info->rgltr[i]) { + regulator_disable(soc_info->rgltr[i]); + regulator_put(soc_info->rgltr[i]); + soc_info->rgltr[i] = NULL; + } + } + +unmap_base: + if (i == -1) + i = soc_info->num_reg_map; + for (i = i - 1; i >= 0; i--) { + if (soc_info->reserve_mem) + release_mem_region(soc_info->mem_block[i]->start, + resource_size(soc_info->mem_block[i])); + iounmap(soc_info->reg_map[i].mem_base); + soc_info->reg_map[i].mem_base = NULL; + soc_info->reg_map[i].size = 0; + } + + return rc; +} + +int cam_soc_util_release_platform_resource(struct cam_hw_soc_info *soc_info) +{ + int i; + + if (!soc_info || !soc_info->dev) { + CAM_ERR(CAM_UTIL, "Invalid parameter"); + return -EINVAL; + } + + for (i = soc_info->num_clk - 1; i >= 0; i--) { + clk_put(soc_info->clk[i]); + soc_info->clk[i] = NULL; + } + + for (i = soc_info->num_rgltr - 1; i >= 0; i--) { + if (soc_info->rgltr[i]) { + regulator_put(soc_info->rgltr[i]); + soc_info->rgltr[i] = NULL; + } + } + + for (i = soc_info->num_reg_map - 1; i >= 0; i--) { + iounmap(soc_info->reg_map[i].mem_base); + soc_info->reg_map[i].mem_base = NULL; + soc_info->reg_map[i].size = 0; + } + + if (soc_info->irq_line) { + disable_irq(soc_info->irq_line->start); + devm_free_irq(soc_info->dev, + soc_info->irq_line->start, soc_info->irq_data); + } + + if (soc_info->pinctrl_info.pinctrl) + devm_pinctrl_put(soc_info->pinctrl_info.pinctrl); + + + /* release for gpio */ + cam_soc_util_request_gpio_table(soc_info, false); + + if (soc_info->clk_control_enable) + cam_soc_util_remove_clk_lvl_debugfs(soc_info); + + return 0; +} + +int cam_soc_util_enable_platform_resource(struct cam_hw_soc_info *soc_info, + bool enable_clocks, enum cam_vote_level clk_level, bool enable_irq) +{ + int rc = 0; + + if (!soc_info) + return -EINVAL; + + rc = cam_soc_util_regulator_enable_default(soc_info); + if (rc) { + CAM_ERR(CAM_UTIL, "Regulators enable failed"); + return rc; + } + + if (enable_clocks) { + rc = cam_soc_util_clk_enable_default(soc_info, clk_level); + if (rc) + goto disable_regulator; + } + + if (enable_irq) { + rc = cam_soc_util_irq_enable(soc_info); + if (rc) + goto disable_clk; + } + + if (soc_info->pinctrl_info.pinctrl && + soc_info->pinctrl_info.gpio_state_active) { + rc = pinctrl_select_state(soc_info->pinctrl_info.pinctrl, + soc_info->pinctrl_info.gpio_state_active); + + if (rc) + goto disable_irq; + } + + return rc; + +disable_irq: + if (enable_irq) + cam_soc_util_irq_disable(soc_info); + +disable_clk: + if (enable_clocks) + cam_soc_util_clk_disable_default(soc_info); + +disable_regulator: + cam_soc_util_regulator_disable_default(soc_info); + + + return rc; +} + +int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info, + bool disable_clocks, bool disable_irq) +{ + int rc = 0; + + if (!soc_info) + return -EINVAL; + + if (disable_irq) + rc |= cam_soc_util_irq_disable(soc_info); + + if (disable_clocks) + cam_soc_util_clk_disable_default(soc_info); + + cam_soc_util_regulator_disable_default(soc_info); + + if (soc_info->pinctrl_info.pinctrl && + soc_info->pinctrl_info.gpio_state_suspend) + rc = pinctrl_select_state(soc_info->pinctrl_info.pinctrl, + soc_info->pinctrl_info.gpio_state_suspend); + + return rc; +} + +int cam_soc_util_reg_dump(struct cam_hw_soc_info *soc_info, + uint32_t base_index, uint32_t offset, int size) +{ + void __iomem *base_addr = NULL; + + CAM_DBG(CAM_UTIL, "base_idx %u size=%d", base_index, size); + + if (!soc_info || base_index >= soc_info->num_reg_map || + size <= 0 || (offset + size) >= + CAM_SOC_GET_REG_MAP_SIZE(soc_info, base_index)) + return -EINVAL; + + base_addr = CAM_SOC_GET_REG_MAP_START(soc_info, base_index); + + /* + * All error checking already done above, + * hence ignoring the return value below. + */ + cam_io_dump(base_addr, offset, size); + + return 0; +} + +static int cam_soc_util_dump_cont_reg_range( + struct cam_hw_soc_info *soc_info, + struct cam_reg_range_read_desc *reg_read, uint32_t base_idx, + struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end) +{ + int i = 0, rc = 0; + uint32_t write_idx = 0; + + if (!soc_info || !dump_out_buf || !reg_read || !cmd_buf_end) { + CAM_ERR(CAM_UTIL, + "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK cmd_buf_end: %pK", + soc_info, dump_out_buf, reg_read, cmd_buf_end); + rc = -EINVAL; + goto end; + } + + if ((reg_read->num_values) && ((reg_read->num_values > U32_MAX / 2) || + (sizeof(uint32_t) > ((U32_MAX - + sizeof(struct cam_reg_dump_out_buffer) - + dump_out_buf->bytes_written) / + (reg_read->num_values * 2))))) { + CAM_ERR(CAM_UTIL, + "Integer Overflow bytes_written: [%u] num_values: [%u]", + dump_out_buf->bytes_written, reg_read->num_values); + rc = -EOVERFLOW; + goto end; + } + + if ((cmd_buf_end - (uintptr_t)dump_out_buf) <= + (uintptr_t)(sizeof(struct cam_reg_dump_out_buffer) + - sizeof(uint32_t) + dump_out_buf->bytes_written + + (reg_read->num_values * 2 * sizeof(uint32_t)))) { + CAM_ERR(CAM_UTIL, + "Insufficient space in out buffer num_values: [%d] cmd_buf_end: %pK dump_out_buf: %pK", + reg_read->num_values, cmd_buf_end, + (uintptr_t)dump_out_buf); + rc = -EINVAL; + goto end; + } + + write_idx = dump_out_buf->bytes_written / sizeof(uint32_t); + for (i = 0; i < reg_read->num_values; i++) { + if ((reg_read->offset + (i * sizeof(uint32_t))) > + (uint32_t)soc_info->reg_map[base_idx].size) { + CAM_ERR(CAM_UTIL, + "Reg offset out of range, offset: 0x%X reg_map size: 0x%X", + (reg_read->offset + (i * sizeof(uint32_t))), + (uint32_t)soc_info->reg_map[base_idx].size); + rc = -EINVAL; + goto end; + } + + dump_out_buf->dump_data[write_idx++] = reg_read->offset + + (i * sizeof(uint32_t)); + dump_out_buf->dump_data[write_idx++] = + cam_soc_util_r(soc_info, base_idx, + (reg_read->offset + (i * sizeof(uint32_t)))); + dump_out_buf->bytes_written += (2 * sizeof(uint32_t)); + } + +end: + return rc; +} + +static int cam_soc_util_dump_dmi_reg_range( + struct cam_hw_soc_info *soc_info, + struct cam_dmi_read_desc *dmi_read, uint32_t base_idx, + struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end) +{ + int i = 0, rc = 0; + uint32_t write_idx = 0; + + if (!soc_info || !dump_out_buf || !dmi_read || !cmd_buf_end) { + CAM_ERR(CAM_UTIL, + "Invalid input args soc_info: %pK, dump_out_buffer: %pK", + soc_info, dump_out_buf); + rc = -EINVAL; + goto end; + } + + if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX || + dmi_read->num_post_writes > CAM_REG_DUMP_DMI_CONFIG_MAX) { + CAM_ERR(CAM_UTIL, + "Invalid number of requested writes, pre: %d post: %d", + dmi_read->num_pre_writes, dmi_read->num_post_writes); + rc = -EINVAL; + goto end; + } + + if ((dmi_read->num_pre_writes + dmi_read->dmi_data_read.num_values) + && ((dmi_read->num_pre_writes > U32_MAX / 2) || + (dmi_read->dmi_data_read.num_values > U32_MAX / 2) || + ((dmi_read->num_pre_writes * 2) > U32_MAX - + (dmi_read->dmi_data_read.num_values * 2)) || + (sizeof(uint32_t) > ((U32_MAX - + sizeof(struct cam_reg_dump_out_buffer) - + dump_out_buf->bytes_written) / ((dmi_read->num_pre_writes + + dmi_read->dmi_data_read.num_values) * 2))))) { + CAM_ERR(CAM_UTIL, + "Integer Overflow bytes_written: [%u] num_pre_writes: [%u] num_values: [%u]", + dump_out_buf->bytes_written, dmi_read->num_pre_writes, + dmi_read->dmi_data_read.num_values); + rc = -EOVERFLOW; + goto end; + } + + if ((cmd_buf_end - (uintptr_t)dump_out_buf) <= + (uintptr_t)( + sizeof(struct cam_reg_dump_out_buffer) - sizeof(uint32_t) + + (dump_out_buf->bytes_written + + (dmi_read->num_pre_writes * 2 * sizeof(uint32_t)) + + (dmi_read->dmi_data_read.num_values * 2 * + sizeof(uint32_t))))) { + CAM_ERR(CAM_UTIL, + "Insufficient space in out buffer num_read_val: [%d] num_write_val: [%d] cmd_buf_end: %pK dump_out_buf: %pK", + dmi_read->dmi_data_read.num_values, + dmi_read->num_pre_writes, cmd_buf_end, + (uintptr_t)dump_out_buf); + rc = -EINVAL; + goto end; + } + + write_idx = dump_out_buf->bytes_written / sizeof(uint32_t); + for (i = 0; i < dmi_read->num_pre_writes; i++) { + if (dmi_read->pre_read_config[i].offset > + (uint32_t)soc_info->reg_map[base_idx].size) { + CAM_ERR(CAM_UTIL, + "Reg offset out of range, offset: 0x%X reg_map size: 0x%X", + dmi_read->pre_read_config[i].offset, + (uint32_t)soc_info->reg_map[base_idx].size); + rc = -EINVAL; + goto end; + } + + cam_soc_util_w_mb(soc_info, base_idx, + dmi_read->pre_read_config[i].offset, + dmi_read->pre_read_config[i].value); + dump_out_buf->dump_data[write_idx++] = + dmi_read->pre_read_config[i].offset; + dump_out_buf->dump_data[write_idx++] = + dmi_read->pre_read_config[i].value; + dump_out_buf->bytes_written += (2 * sizeof(uint32_t)); + } + + if (dmi_read->dmi_data_read.offset > + (uint32_t)soc_info->reg_map[base_idx].size) { + CAM_ERR(CAM_UTIL, + "Reg offset out of range, offset: 0x%X reg_map size: 0x%X", + dmi_read->dmi_data_read.offset, + (uint32_t)soc_info->reg_map[base_idx].size); + rc = -EINVAL; + goto end; + } + + for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) { + dump_out_buf->dump_data[write_idx++] = + dmi_read->dmi_data_read.offset; + dump_out_buf->dump_data[write_idx++] = + cam_soc_util_r_mb(soc_info, base_idx, + dmi_read->dmi_data_read.offset); + dump_out_buf->bytes_written += (2 * sizeof(uint32_t)); + } + + for (i = 0; i < dmi_read->num_post_writes; i++) { + if (dmi_read->post_read_config[i].offset > + (uint32_t)soc_info->reg_map[base_idx].size) { + CAM_ERR(CAM_UTIL, + "Reg offset out of range, offset: 0x%X reg_map size: 0x%X", + dmi_read->post_read_config[i].offset, + (uint32_t)soc_info->reg_map[base_idx].size); + rc = -EINVAL; + goto end; + } + + cam_soc_util_w_mb(soc_info, base_idx, + dmi_read->post_read_config[i].offset, + dmi_read->post_read_config[i].value); + } + +end: + return rc; +} + +static int cam_soc_util_dump_dmi_reg_range_user_buf( + struct cam_hw_soc_info *soc_info, + struct cam_dmi_read_desc *dmi_read, uint32_t base_idx, + struct cam_hw_soc_dump_args *dump_args) +{ + int i; + int rc; + size_t buf_len = 0; + uint8_t *dst; + size_t remain_len; + uint32_t min_len; + uint32_t *waddr, *start; + uintptr_t cpu_addr; + struct cam_hw_soc_dump_header *hdr; + + if (!soc_info || !dump_args || !dmi_read) { + CAM_ERR(CAM_UTIL, + "Invalid input args soc_info: %pK, dump_args: %pK", + soc_info, dump_args); + return -EINVAL; + } + + if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX || + dmi_read->num_post_writes > CAM_REG_DUMP_DMI_CONFIG_MAX) { + CAM_ERR(CAM_UTIL, + "Invalid number of requested writes, pre: %d post: %d", + dmi_read->num_pre_writes, dmi_read->num_post_writes); + return -EINVAL; + } + + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len); + if (rc) { + CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + return -EINVAL; + } + + if (buf_len <= dump_args->offset) { + CAM_WARN(CAM_UTIL, "Dump offset overshoot offset %zu len %zu", + dump_args->offset, buf_len); + rc = -ENOSPC; + goto end; + } + remain_len = buf_len - dump_args->offset; + min_len = (dmi_read->num_pre_writes * 2 * sizeof(uint32_t)) + + (dmi_read->dmi_data_read.num_values * 2 * sizeof(uint32_t)) + + sizeof(uint32_t); + if (remain_len < min_len) { + CAM_WARN(CAM_UTIL, + "Dump Buffer exhaust read %d write %d remain %zu min %u", + dmi_read->dmi_data_read.num_values, + dmi_read->num_pre_writes, remain_len, + min_len); + rc = -ENOSPC; + goto end; + } + + dst = (uint8_t *)cpu_addr + dump_args->offset; + hdr = (struct cam_hw_soc_dump_header *)dst; + memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header)); + scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN, + "DMI_DUMP:"); + waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header)); + start = waddr; + hdr->word_size = sizeof(uint32_t); + *waddr = soc_info->index; + waddr++; + for (i = 0; i < dmi_read->num_pre_writes; i++) { + if (dmi_read->pre_read_config[i].offset > + (uint32_t)soc_info->reg_map[base_idx].size) { + CAM_ERR(CAM_UTIL, + "Reg offset out of range, offset: 0x%X reg_map size: 0x%X", + dmi_read->pre_read_config[i].offset, + (uint32_t)soc_info->reg_map[base_idx].size); + rc = -EINVAL; + goto end; + } + + cam_soc_util_w_mb(soc_info, base_idx, + dmi_read->pre_read_config[i].offset, + dmi_read->pre_read_config[i].value); + *waddr++ = dmi_read->pre_read_config[i].offset; + *waddr++ = dmi_read->pre_read_config[i].value; + } + + if (dmi_read->dmi_data_read.offset > + (uint32_t)soc_info->reg_map[base_idx].size) { + CAM_ERR(CAM_UTIL, + "Reg offset out of range, offset: 0x%X reg_map size: 0x%X", + dmi_read->dmi_data_read.offset, + (uint32_t)soc_info->reg_map[base_idx].size); + rc = -EINVAL; + goto end; + } + + for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) { + *waddr++ = dmi_read->dmi_data_read.offset; + *waddr++ = cam_soc_util_r_mb(soc_info, base_idx, + dmi_read->dmi_data_read.offset); + } + + for (i = 0; i < dmi_read->num_post_writes; i++) { + if (dmi_read->post_read_config[i].offset > + (uint32_t)soc_info->reg_map[base_idx].size) { + CAM_ERR(CAM_UTIL, + "Reg offset out of range, offset: 0x%X reg_map size: 0x%X", + dmi_read->post_read_config[i].offset, + (uint32_t)soc_info->reg_map[base_idx].size); + rc = -EINVAL; + goto end; + } + cam_soc_util_w_mb(soc_info, base_idx, + dmi_read->post_read_config[i].offset, + dmi_read->post_read_config[i].value); + } + hdr->size = (waddr - start) * hdr->word_size; + dump_args->offset += hdr->size + + sizeof(struct cam_hw_soc_dump_header); + +end: + if (dump_args) + cam_mem_put_cpu_buf(dump_args->buf_handle); + return rc; +} + +static int cam_soc_util_dump_cont_reg_range_user_buf( + struct cam_hw_soc_info *soc_info, + struct cam_reg_range_read_desc *reg_read, + uint32_t base_idx, + struct cam_hw_soc_dump_args *dump_args) +{ + int i; + int rc = 0; + size_t buf_len; + uint8_t *dst; + size_t remain_len; + uint32_t min_len; + uint32_t *waddr, *start; + uintptr_t cpu_addr; + struct cam_hw_soc_dump_header *hdr; + + if (!soc_info || !dump_args || !reg_read) { + CAM_ERR(CAM_UTIL, + "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK", + soc_info, dump_args, reg_read); + rc = -EINVAL; + return rc; + } + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len); + if (rc) { + CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + return rc; + } + if (buf_len <= dump_args->offset) { + CAM_WARN(CAM_UTIL, "Dump offset overshoot %zu %zu", + dump_args->offset, buf_len); + rc = -ENOSPC; + goto end; + } + remain_len = buf_len - dump_args->offset; + min_len = (reg_read->num_values * 2 * sizeof(uint32_t)) + + sizeof(struct cam_hw_soc_dump_header) + sizeof(uint32_t); + if (remain_len < min_len) { + CAM_WARN(CAM_UTIL, + "Dump Buffer exhaust read_values %d remain %zu min %u", + reg_read->num_values, + remain_len, + min_len); + rc = -ENOSPC; + goto end; + } + dst = (uint8_t *)cpu_addr + dump_args->offset; + hdr = (struct cam_hw_soc_dump_header *)dst; + memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header)); + scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN, "%s_REG:", + soc_info->dev_name); + waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header)); + start = waddr; + hdr->word_size = sizeof(uint32_t); + *waddr = soc_info->index; + waddr++; + for (i = 0; i < reg_read->num_values; i++) { + if ((reg_read->offset + (i * sizeof(uint32_t))) > + (uint32_t)soc_info->reg_map[base_idx].size) { + CAM_ERR(CAM_UTIL, + "Reg offset out of range, offset: 0x%X reg_map size: 0x%X", + (reg_read->offset + (i * sizeof(uint32_t))), + (uint32_t)soc_info->reg_map[base_idx].size); + rc = -EINVAL; + goto end; + } + + waddr[0] = reg_read->offset + (i * sizeof(uint32_t)); + waddr[1] = cam_soc_util_r(soc_info, base_idx, + (reg_read->offset + (i * sizeof(uint32_t)))); + waddr += 2; + } + hdr->size = (waddr - start) * hdr->word_size; + dump_args->offset += hdr->size + + sizeof(struct cam_hw_soc_dump_header); +end: + if (dump_args) + cam_mem_put_cpu_buf(dump_args->buf_handle); + return rc; +} + +static int cam_soc_util_user_reg_dump( + struct cam_reg_dump_desc *reg_dump_desc, + struct cam_hw_soc_dump_args *dump_args, + struct cam_hw_soc_info *soc_info, + uint32_t reg_base_idx) +{ + int rc = 0; + int i; + struct cam_reg_read_info *reg_read_info = NULL; + + if (!dump_args || !reg_dump_desc || !soc_info) { + CAM_ERR(CAM_UTIL, + "Invalid input parameters %pK %pK %pK", + dump_args, reg_dump_desc, soc_info); + return -EINVAL; + } + for (i = 0; i < reg_dump_desc->num_read_range; i++) { + + reg_read_info = ®_dump_desc->read_range[i]; + if (reg_read_info->type == + CAM_REG_DUMP_READ_TYPE_CONT_RANGE) { + rc = cam_soc_util_dump_cont_reg_range_user_buf( + soc_info, + ®_read_info->reg_read, + reg_base_idx, + dump_args); + } else if (reg_read_info->type == + CAM_REG_DUMP_READ_TYPE_DMI) { + rc = cam_soc_util_dump_dmi_reg_range_user_buf( + soc_info, + ®_read_info->dmi_read, + reg_base_idx, + dump_args); + } else { + CAM_ERR(CAM_UTIL, + "Invalid Reg dump read type: %d", + reg_read_info->type); + rc = -EINVAL; + goto end; + } + + if (rc) { + CAM_ERR(CAM_UTIL, + "Reg range read failed rc: %d reg_base_idx: %d", + rc, reg_base_idx); + goto end; + } + } +end: + return rc; +} + +int cam_soc_util_reg_dump_to_cmd_buf(void *ctx, + struct cam_cmd_buf_desc *cmd_desc, uint64_t req_id, + cam_soc_util_regspace_data_cb reg_data_cb, + struct cam_hw_soc_dump_args *soc_dump_args, + bool user_triggered_dump) +{ + int rc = 0, i, j; + uintptr_t cpu_addr = 0; + uintptr_t cmd_buf_start = 0; + uintptr_t cmd_in_data_end = 0; + uintptr_t cmd_buf_end = 0; + uint32_t reg_base_type = 0; + size_t buf_size = 0, remain_len = 0; + struct cam_reg_dump_input_info *reg_input_info = NULL; + struct cam_reg_dump_desc *reg_dump_desc = NULL; + struct cam_reg_dump_out_buffer *dump_out_buf = NULL; + struct cam_reg_read_info *reg_read_info = NULL; + struct cam_hw_soc_info *soc_info; + uint32_t reg_base_idx = 0; + + if (!ctx || !cmd_desc || !reg_data_cb) { + CAM_ERR(CAM_UTIL, "Invalid args to reg dump [%pK] [%pK]", + cmd_desc, reg_data_cb); + return -EINVAL; + } + + if (!cmd_desc->length || !cmd_desc->size) { + CAM_ERR(CAM_UTIL, "Invalid cmd buf size %d %d", + cmd_desc->length, cmd_desc->size); + return -EINVAL; + } + + rc = cam_mem_get_cpu_buf(cmd_desc->mem_handle, &cpu_addr, &buf_size); + if (rc || !cpu_addr || (buf_size == 0)) { + CAM_ERR(CAM_UTIL, "Failed in Get cpu addr, rc=%d, cpu_addr=%pK", + rc, (void *)cpu_addr); + if (rc) + return rc; + goto end; + } + + CAM_DBG(CAM_UTIL, "Get cpu buf success req_id: %llu buf_size: %zu", + req_id, buf_size); + if ((buf_size < sizeof(uint32_t)) || + ((size_t)cmd_desc->offset > (buf_size - sizeof(uint32_t)))) { + CAM_ERR(CAM_UTIL, "Invalid offset for cmd buf: %zu", + (size_t)cmd_desc->offset); + rc = -EINVAL; + goto end; + } + + remain_len = buf_size - (size_t)cmd_desc->offset; + if ((remain_len < (size_t)cmd_desc->size) || (cmd_desc->size < + cmd_desc->length)) { + CAM_ERR(CAM_UTIL, + "Invalid params for cmd buf len: %zu size: %zu remain_len: %zu", + (size_t)cmd_desc->length, (size_t)cmd_desc->length, + remain_len); + rc = -EINVAL; + goto end; + } + + cmd_buf_start = cpu_addr + (uintptr_t)cmd_desc->offset; + cmd_in_data_end = cmd_buf_start + (uintptr_t)cmd_desc->length; + cmd_buf_end = cmd_buf_start + (uintptr_t)cmd_desc->size; + if ((cmd_buf_end <= cmd_buf_start) || + (cmd_in_data_end <= cmd_buf_start)) { + CAM_ERR(CAM_UTIL, + "Invalid length or size for cmd buf: [%zu] [%zu]", + (size_t)cmd_desc->length, (size_t)cmd_desc->size); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_UTIL, + "Buffer params start [%pK] input_end [%pK] buf_end [%pK]", + cmd_buf_start, cmd_in_data_end, cmd_buf_end); + reg_input_info = (struct cam_reg_dump_input_info *) cmd_buf_start; + if ((reg_input_info->num_dump_sets > 1) && (sizeof(uint32_t) > + ((U32_MAX - sizeof(struct cam_reg_dump_input_info)) / + (reg_input_info->num_dump_sets - 1)))) { + CAM_ERR(CAM_UTIL, + "Integer Overflow req_id: [%llu] num_dump_sets: [%u]", + req_id, reg_input_info->num_dump_sets); + rc = -EOVERFLOW; + goto end; + } + + if ((!reg_input_info->num_dump_sets) || + ((cmd_in_data_end - cmd_buf_start) <= (uintptr_t) + (sizeof(struct cam_reg_dump_input_info) + + ((reg_input_info->num_dump_sets - 1) * sizeof(uint32_t))))) { + CAM_ERR(CAM_UTIL, + "Invalid number of dump sets, req_id: [%llu] num_dump_sets: [%u]", + req_id, reg_input_info->num_dump_sets); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_UTIL, + "reg_input_info req_id: %llu ctx %pK num_dump_sets: %d", + req_id, ctx, reg_input_info->num_dump_sets); + for (i = 0; i < reg_input_info->num_dump_sets; i++) { + if ((cmd_in_data_end - cmd_buf_start) <= (uintptr_t) + reg_input_info->dump_set_offsets[i]) { + CAM_ERR(CAM_UTIL, + "Invalid dump set offset: [%pK], cmd_buf_start: [%pK] cmd_in_data_end: [%pK]", + (uintptr_t)reg_input_info->dump_set_offsets[i], + cmd_buf_start, cmd_in_data_end); + rc = -EINVAL; + goto end; + } + + reg_dump_desc = (struct cam_reg_dump_desc *) + (cmd_buf_start + + (uintptr_t)reg_input_info->dump_set_offsets[i]); + if ((reg_dump_desc->num_read_range > 1) && + (sizeof(struct cam_reg_read_info) > ((U32_MAX - + sizeof(struct cam_reg_dump_desc)) / + (reg_dump_desc->num_read_range - 1)))) { + CAM_ERR(CAM_UTIL, + "Integer Overflow req_id: [%llu] num_read_range: [%u]", + req_id, reg_dump_desc->num_read_range); + rc = -EOVERFLOW; + goto end; + } + + if ((!reg_dump_desc->num_read_range) || + ((cmd_in_data_end - (uintptr_t)reg_dump_desc) <= + (uintptr_t)(sizeof(struct cam_reg_dump_desc) + + ((reg_dump_desc->num_read_range - 1) * + sizeof(struct cam_reg_read_info))))) { + CAM_ERR(CAM_UTIL, + "Invalid number of read ranges, req_id: [%llu] num_read_range: [%d]", + req_id, reg_dump_desc->num_read_range); + rc = -EINVAL; + goto end; + } + + if ((cmd_buf_end - cmd_buf_start) <= (uintptr_t) + (reg_dump_desc->dump_buffer_offset + + sizeof(struct cam_reg_dump_out_buffer))) { + CAM_ERR(CAM_UTIL, + "Invalid out buffer offset: [%pK], cmd_buf_start: [%pK] cmd_buf_end: [%pK]", + (uintptr_t)reg_dump_desc->dump_buffer_offset, + cmd_buf_start, cmd_buf_end); + rc = -EINVAL; + goto end; + } + + reg_base_type = reg_dump_desc->reg_base_type; + if (reg_base_type == 0 || reg_base_type > + CAM_REG_DUMP_BASE_TYPE_CAMNOC) { + CAM_ERR(CAM_UTIL, + "Invalid Reg dump base type: %d", + reg_base_type); + rc = -EINVAL; + goto end; + } + + rc = reg_data_cb(reg_base_type, ctx, &soc_info, ®_base_idx); + if (rc || !soc_info) { + CAM_ERR(CAM_UTIL, + "Reg space data callback failed rc: %d soc_info: [%pK]", + rc, soc_info); + rc = -EINVAL; + goto end; + } + + if (reg_base_idx > soc_info->num_reg_map) { + CAM_ERR(CAM_UTIL, + "Invalid reg base idx: %d num reg map: %d", + reg_base_idx, soc_info->num_reg_map); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_UTIL, + "Reg data callback success req_id: %llu base_type: %d base_idx: %d num_read_range: %d", + req_id, reg_base_type, reg_base_idx, + reg_dump_desc->num_read_range); + + /* If the dump request is triggered by user space + * buffer will be different from the buffer which is received + * in init packet. In this case, dump the data to the + * user provided buffer and exit. + */ + if (user_triggered_dump) { + rc = cam_soc_util_user_reg_dump(reg_dump_desc, + soc_dump_args, soc_info, reg_base_idx); + CAM_INFO(CAM_UTIL, + "%s reg_base_idx %d dumped offset %u", + soc_info->dev_name, reg_base_idx, + soc_dump_args->offset); + goto end; + } + + /* Below code is executed when data is dumped to the + * out buffer received in init packet + */ + dump_out_buf = (struct cam_reg_dump_out_buffer *) + (cmd_buf_start + + (uintptr_t)reg_dump_desc->dump_buffer_offset); + dump_out_buf->req_id = req_id; + dump_out_buf->bytes_written = 0; + + for (j = 0; j < reg_dump_desc->num_read_range; j++) { + CAM_DBG(CAM_UTIL, + "Number of bytes written to cmd buffer: %u req_id: %llu", + dump_out_buf->bytes_written, req_id); + reg_read_info = ®_dump_desc->read_range[j]; + if (reg_read_info->type == + CAM_REG_DUMP_READ_TYPE_CONT_RANGE) { + rc = cam_soc_util_dump_cont_reg_range(soc_info, + ®_read_info->reg_read, reg_base_idx, + dump_out_buf, cmd_buf_end); + } else if (reg_read_info->type == + CAM_REG_DUMP_READ_TYPE_DMI) { + rc = cam_soc_util_dump_dmi_reg_range(soc_info, + ®_read_info->dmi_read, reg_base_idx, + dump_out_buf, cmd_buf_end); + } else { + CAM_ERR(CAM_UTIL, + "Invalid Reg dump read type: %d", + reg_read_info->type); + rc = -EINVAL; + goto end; + } + + if (rc) { + CAM_ERR(CAM_UTIL, + "Reg range read failed rc: %d reg_base_idx: %d dump_out_buf: %pK", + rc, reg_base_idx, dump_out_buf); + goto end; + } + } + } + +end: + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + return rc; +} diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_soc_util.h b/techpack/camera-bengal/drivers/cam_utils/cam_soc_util.h new file mode 100644 index 0000000000000000000000000000000000000000..bb4aff5e71ce6d6e85719e2eb7e0581ed862d788 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_soc_util.h @@ -0,0 +1,689 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_SOC_UTIL_H_ +#define _CAM_SOC_UTIL_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cam_io_util.h" +#include + +#define NO_SET_RATE -1 +#define INIT_RATE -2 + +/* maximum number of device block */ +#define CAM_SOC_MAX_BLOCK 7 + +/* maximum number of device base */ +#define CAM_SOC_MAX_BASE CAM_SOC_MAX_BLOCK + +/* maximum number of device regulator */ +#define CAM_SOC_MAX_REGULATOR 5 + +/* maximum number of device clock */ +#define CAM_SOC_MAX_CLK 32 + +/* DDR device types */ +#define DDR_TYPE_LPDDR4 6 +#define DDR_TYPE_LPDDR4X 7 +#define DDR_TYPE_LPDDR5 8 +#define DDR_TYPE_LPDDR5X 9 + +/* Maximum length of tag while dumping */ +#define CAM_SOC_HW_DUMP_TAG_MAX_LEN 32 + +/** + * enum cam_vote_level - Enum for voting level + * + * @CAM_SUSPEND_VOTE : Suspend vote + * @CAM_MINSVS_VOTE : Min SVS vote + * @CAM_LOWSVS_VOTE : Low SVS vote + * @CAM_SVS_VOTE : SVS vote + * @CAM_SVSL1_VOTE : SVS Plus vote + * @CAM_NOMINAL_VOTE : Nominal vote + * @CAM_NOMINALL1_VOTE: Nominal plus vote + * @CAM_TURBO_VOTE : Turbo vote + * @CAM_MAX_VOTE : Max voting level, This is invalid level. + */ +enum cam_vote_level { + CAM_SUSPEND_VOTE, + CAM_MINSVS_VOTE, + CAM_LOWSVS_VOTE, + CAM_SVS_VOTE, + CAM_SVSL1_VOTE, + CAM_NOMINAL_VOTE, + CAM_NOMINALL1_VOTE, + CAM_TURBO_VOTE, + CAM_MAX_VOTE, +}; + +/* pinctrl states */ +#define CAM_SOC_PINCTRL_STATE_SLEEP "cam_suspend" +#define CAM_SOC_PINCTRL_STATE_DEFAULT "cam_default" + +/** + * struct cam_soc_reg_map: Information about the mapped register space + * + * @mem_base: Starting location of MAPPED register space + * @mem_cam_base: Starting offset of this register space compared + * to ENTIRE Camera register space + * @size: Size of register space + **/ +struct cam_soc_reg_map { + void __iomem *mem_base; + uint32_t mem_cam_base; + resource_size_t size; +}; + +/** + * struct cam_soc_pinctrl_info: Information about pinctrl data + * + * @pinctrl: pintrl object + * @gpio_state_active: default pinctrl state + * @gpio_state_suspend suspend state of pinctrl + **/ +struct cam_soc_pinctrl_info { + struct pinctrl *pinctrl; + struct pinctrl_state *gpio_state_active; + struct pinctrl_state *gpio_state_suspend; +}; + +/** + * struct cam_soc_gpio_data: Information about the gpio pins + * + * @cam_gpio_common_tbl: It is list of al the gpios present in gpios node + * @cam_gpio_common_tbl_size: It is equal to number of gpios prsent in + * gpios node in DTSI + * @cam_gpio_req_tbl It is list of al the requesetd gpios + * @cam_gpio_req_tbl_size: It is size of requested gpios + **/ +struct cam_soc_gpio_data { + struct gpio *cam_gpio_common_tbl; + uint8_t cam_gpio_common_tbl_size; + struct gpio *cam_gpio_req_tbl; + uint8_t cam_gpio_req_tbl_size; +}; + +/** + * struct cam_hw_soc_info: Soc information pertaining to specific instance of + * Camera hardware driver module + * + * @pdev: Platform device pointer + * @device: Device pointer + * @hw_version: Camera device version + * @index: Instance id for the camera device + * @dev_name: Device Name + * @irq_name: Name of the irq associated with the device + * @label_name: label name + * @irq_line: Irq resource + * @irq_data: Private data that is passed when IRQ is requested + * @compatible: Compatible string associated with the device + * @num_mem_block: Number of entry in the "reg-names" + * @mem_block_name: Array of the reg block name + * @mem_block_cam_base: Array of offset of this register space compared + * to ENTIRE Camera register space + * @mem_block: Associated resource structs + * @reg_map: Array of Mapped register info for the "reg-names" + * @num_reg_map: Number of mapped register space associated + * with mem_block. num_reg_map = num_mem_block in + * most cases + * @reserve_mem: Whether to reserve memory for Mem blocks + * @num_rgltr: Number of regulators + * @rgltr_name: Array of regulator names + * @rgltr_ctrl_support: Whether regulator control is supported + * @rgltr_min_volt: Array of minimum regulator voltage + * @rgltr_max_volt: Array of maximum regulator voltage + * @rgltr_op_mode: Array of regulator operation mode + * @rgltr_type: Array of regulator names + * @rgltr: Array of associated regulator resources + * @rgltr_delay: Array of regulator delay values + * @num_clk: Number of clocks + * @clk_name: Array of clock names + * @clk: Array of associated clock resources + * @clk_rate: 2D array of clock rates representing clock rate + * values at different vote levels + * @prev_clk_level Last vote level + * @src_clk_idx: Source clock index that is rate-controllable + * @clk_level_valid: Indicates whether corresponding level is valid + * @scl_clk_count: Number of scalable clocks present + * @scl_clk_idx: Index of scalable clocks + * @gpio_data: Pointer to gpio info + * @pinctrl_info: Pointer to pinctrl info + * @dentry: Debugfs entry + * @clk_level_override: Clk level set from debugfs + * @clk_control: Enable/disable clk rate control through debugfs + * @cam_cx_ipeak_enable cx-ipeak enable/disable flag + * @cam_cx_ipeak_bit cx-ipeak mask for driver + * @soc_private: Soc private data + */ +struct cam_hw_soc_info { + struct platform_device *pdev; + struct device *dev; + uint32_t hw_version; + uint32_t index; + const char *dev_name; + const char *irq_name; + const char *label_name; + struct resource *irq_line; + void *irq_data; + const char *compatible; + + uint32_t num_mem_block; + const char *mem_block_name[CAM_SOC_MAX_BLOCK]; + uint32_t mem_block_cam_base[CAM_SOC_MAX_BLOCK]; + struct resource *mem_block[CAM_SOC_MAX_BLOCK]; + struct cam_soc_reg_map reg_map[CAM_SOC_MAX_BASE]; + uint32_t num_reg_map; + uint32_t reserve_mem; + + uint32_t num_rgltr; + const char *rgltr_name[CAM_SOC_MAX_REGULATOR]; + uint32_t rgltr_ctrl_support; + uint32_t rgltr_min_volt[CAM_SOC_MAX_REGULATOR]; + uint32_t rgltr_max_volt[CAM_SOC_MAX_REGULATOR]; + uint32_t rgltr_op_mode[CAM_SOC_MAX_REGULATOR]; + uint32_t rgltr_type[CAM_SOC_MAX_REGULATOR]; + struct regulator *rgltr[CAM_SOC_MAX_REGULATOR]; + uint32_t rgltr_delay[CAM_SOC_MAX_REGULATOR]; + + uint32_t use_shared_clk; + uint32_t num_clk; + const char *clk_name[CAM_SOC_MAX_CLK]; + struct clk *clk[CAM_SOC_MAX_CLK]; + int32_t clk_rate[CAM_MAX_VOTE][CAM_SOC_MAX_CLK]; + int32_t prev_clk_level; + int32_t src_clk_idx; + bool clk_level_valid[CAM_MAX_VOTE]; + int32_t scl_clk_count; + int32_t scl_clk_idx[CAM_SOC_MAX_CLK]; + + struct cam_soc_gpio_data *gpio_data; + struct cam_soc_pinctrl_info pinctrl_info; + + struct dentry *dentry; + uint32_t clk_level_override; + bool clk_control_enable; + bool cam_cx_ipeak_enable; + int32_t cam_cx_ipeak_bit; + + void *soc_private; +}; + +/** + * struct cam_hw_soc_dump_header - SOC dump header + * + * @Brief: soc hw dump header + * + * @tag: Tag name for the header + * @word_size: Size of each word + * @size: Total size of dumped data + */ +struct cam_hw_soc_dump_header { + uint8_t tag[CAM_SOC_HW_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + +/** + * struct cam_hw_soc_dump_args: SOC Dump args + * + * @request_id: Issue request id + * @offset: Buffer offset, updated as the informaton is dumped + * @buf_handle: Buffer handle of the out buffer + */ +struct cam_hw_soc_dump_args { + uint64_t request_id; + size_t offset; + uint32_t buf_handle; +}; + +/* + * CAM_SOC_GET_REG_MAP_START + * + * @brief: This MACRO will get the mapped starting address + * where the register space can be accessed + * + * @__soc_info: Device soc information + * @__base_index: Index of register space in the HW block + * + * @return: Returns a pointer to the mapped register memory + */ +#define CAM_SOC_GET_REG_MAP_START(__soc_info, __base_index) \ + ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \ + NULL : __soc_info->reg_map[__base_index].mem_base) + +/* + * CAM_SOC_GET_REG_MAP_CAM_BASE + * + * @brief: This MACRO will get the cam_base of the + * register space + * + * @__soc_info: Device soc information + * @__base_index: Index of register space in the HW block + * + * @return: Returns an int32_t value. + * Failure: -1 + * Success: Starting offset of register space compared + * to entire Camera Register Map + */ +#define CAM_SOC_GET_REG_MAP_CAM_BASE(__soc_info, __base_index) \ + ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \ + -1 : __soc_info->reg_map[__base_index].mem_cam_base) + +/* + * CAM_SOC_GET_REG_MAP_SIZE + * + * @brief: This MACRO will get the size of the mapped + * register space + * + * @__soc_info: Device soc information + * @__base_index: Index of register space in the HW block + * + * @return: Returns a uint32_t value. + * Failure: 0 + * Success: Non-zero size of mapped register space + */ +#define CAM_SOC_GET_REG_MAP_SIZE(__soc_info, __base_index) \ + ((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \ + 0 : __soc_info->reg_map[__base_index].size) + +/** + * cam_soc_util_get_level_from_string() + * + * @brief: Get the associated vote level for the input string + * + * @string: Input string to compare with. + * @level: Vote level corresponds to input string. + * + * @return: Success or failure + */ +int cam_soc_util_get_level_from_string(const char *string, + enum cam_vote_level *level); + +/** + * cam_soc_util_get_dt_properties() + * + * @brief: Parse the DT and populate the common properties that + * are part of the soc_info structure - register map, + * clocks, regulators, irq, etc. + * + * @soc_info: Device soc struct to be populated + * + * @return: Success or failure + */ +int cam_soc_util_get_dt_properties(struct cam_hw_soc_info *soc_info); + +/** + * cam_soc_util_request_platform_resource() + * + * @brief: Request regulator, irq, and clock resources + * + * @soc_info: Device soc information + * @handler: Irq handler function pointer + * @irq_data: Irq handler function CB data + * + * @return: Success or failure + */ +int cam_soc_util_request_platform_resource(struct cam_hw_soc_info *soc_info, + irq_handler_t handler, void *irq_data); + +/** + * cam_soc_util_release_platform_resource() + * + * @brief: Release regulator, irq, and clock resources + * + * @soc_info: Device soc information + * + * @return: Success or failure + */ +int cam_soc_util_release_platform_resource(struct cam_hw_soc_info *soc_info); + +/** + * cam_soc_util_enable_platform_resource() + * + * @brief: Enable regulator, irq resources + * + * @soc_info: Device soc information + * @enable_clocks: Boolean flag: + * TRUE: Enable all clocks in soc_info Now. + * False: Don't enable clocks Now. Driver will + * enable independently. + * @clk_level: Clock level to be applied. + * Applicable only if enable_clocks is true + * Valid range : 0 to (CAM_MAX_VOTE - 1) + * @enable_irq: Boolean flag: + * TRUE: Enable IRQ in soc_info Now. + * False: Don't enable IRQ Now. Driver will + * enable independently. + * + * @return: Success or failure + */ +int cam_soc_util_enable_platform_resource(struct cam_hw_soc_info *soc_info, + bool enable_clocks, enum cam_vote_level clk_level, bool enable_irq); + +/** + * cam_soc_util_disable_platform_resource() + * + * @brief: Disable regulator, irq resources + * + * @soc_info: Device soc information + * @disable_irq: Boolean flag: + * TRUE: Disable IRQ in soc_info Now. + * False: Don't disable IRQ Now. Driver will + * disable independently. + * + * @return: Success or failure + */ +int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info, + bool disable_clocks, bool disable_irq); + +/** + * cam_soc_util_get_clk_round_rate() + * + * @brief: Get the rounded clock rate for the given clock's + * clock rate value + * + * @soc_info: Device soc information + * @clk_index: Clock index in soc_info for which round rate is needed + * @clk_rate: Input clock rate for which rounded rate is needed + * + * @return: Rounded clock rate + */ +long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info, + uint32_t clk_index, unsigned long clk_rate); + +/** + * cam_soc_util_set_src_clk_rate() + * + * @brief: Set the rate on the source clock. + * + * @soc_info: Device soc information + * @clk_rate: Clock rate associated with the src clk + * + * @return: success or failure + */ +int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info, + int64_t clk_rate); + +/** + * cam_soc_util_get_option_clk_by_name() + * + * @brief: Get reference to optional clk using name + * + * @soc_info: Device soc information + * @clk_name: Name of clock to find reference for + * @clk: Clock reference pointer to be filled if Success + * @clk_index: Clk index in the option clk array to be returned + * @clk_rate: Clk rate in the option clk array + * + * @return: 0: Success + * Negative: Failure + */ +int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info, + const char *clk_name, struct clk **clk, int32_t *clk_index, + int32_t *clk_rate); + +/** + * cam_soc_util_clk_put() + * + * @brief: Put clock specified in params + * + * @clk: Reference to the Clock that needs to be put + * + * @return: Success or failure + */ +int cam_soc_util_clk_put(struct clk **clk); + +/** + * cam_soc_util_clk_enable() + * + * @brief: Enable clock specified in params + * + * @clk: Clock that needs to be turned ON + * @clk_name: Clocks name associated with clk + * @clk_rate: Clocks rate associated with clk + * + * @return: Success or failure + */ +int cam_soc_util_clk_enable(struct clk *clk, const char *clk_name, + int32_t clk_rate); + +/** + * cam_soc_util_set_clk_rate_level() + * + * @brief: Apply clock rates for the requested level. + * This applies the new requested level for all + * the clocks listed in DT based on their values. + * + * @soc_info: Device soc information + * @clk_level: Clock level number to set + * + * @return: Success or failure + */ +int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info, + enum cam_vote_level clk_level); + +/** + * cam_soc_util_clk_disable() + * + * @brief: Disable clock specified in params + * + * @clk: Clock that needs to be turned OFF + * @clk_name: Clocks name associated with clk + * + * @return: Success or failure + */ +int cam_soc_util_clk_disable(struct clk *clk, const char *clk_name); + +/** + * cam_soc_util_irq_enable() + * + * @brief: Enable IRQ in SOC + * + * @soc_info: Device soc information + * + * @return: Success or failure + */ +int cam_soc_util_irq_enable(struct cam_hw_soc_info *soc_info); + +/** + * cam_soc_util_irq_disable() + * + * @brief: Disable IRQ in SOC + * + * @soc_info: Device soc information + * + * @return: Success or failure + */ +int cam_soc_util_irq_disable(struct cam_hw_soc_info *soc_info); + +/** + * cam_soc_util_regulator_enable() + * + * @brief: Enable single regulator + * + * @rgltr Regulator that needs to be turned ON + * @rgltr_name Associated Regulator name + * @rgltr_min_volt: Requested minimum volatage + * @rgltr_max_volt: Requested maximum volatage + * @rgltr_op_mode: Requested Load + * @rgltr_delay: Requested delay needed aaftre enabling regulator + * + * @return: Success or failure + */ +int cam_soc_util_regulator_enable(struct regulator *rgltr, + const char *rgltr_name, + uint32_t rgltr_min_volt, uint32_t rgltr_max_volt, + uint32_t rgltr_op_mode, uint32_t rgltr_delay); + +/** + * cam_soc_util_regulator_enable() + * + * @brief: Disable single regulator + * + * @rgltr Regulator that needs to be turned ON + * @rgltr_name Associated Regulator name + * @rgltr_min_volt: Requested minimum volatage + * @rgltr_max_volt: Requested maximum volatage + * @rgltr_op_mode: Requested Load + * @rgltr_delay: Requested delay needed aaftre enabling regulator + * + * @return: Success or failure + */ +int cam_soc_util_regulator_disable(struct regulator *rgltr, + const char *rgltr_name, + uint32_t rgltr_min_volt, uint32_t rgltr_max_volt, + uint32_t rgltr_op_mode, uint32_t rgltr_delay); + + +/** + * cam_soc_util_w() + * + * @brief: Camera SOC util for register write + * + * @soc_info: Device soc information + * @base_index: Index of register space in the HW block + * @offset: Offset of register to be read + * @data: Value to be written + * + * @return: Success or Failure + */ +static inline int cam_soc_util_w(struct cam_hw_soc_info *soc_info, + uint32_t base_index, uint32_t offset, uint32_t data) +{ + if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index)) + return -EINVAL; + return cam_io_w(data, + CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset); +} + +/** + * cam_soc_util_w_mb() + * + * @brief: Camera SOC util for register write with memory barrier. + * Memory Barrier is only before the write to ensure the + * order. If need to ensure this write is also flushed + * call wmb() independently in the caller. + * + * @soc_info: Device soc information + * @base_index: Index of register space in the HW block + * @offset: Offset of register to be read + * @data: Value to be written + * + * @return: Success or Failure + */ +static inline int cam_soc_util_w_mb(struct cam_hw_soc_info *soc_info, + uint32_t base_index, uint32_t offset, uint32_t data) +{ + if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index)) + return -EINVAL; + return cam_io_w_mb(data, + CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset); +} + +/** + * cam_soc_util_r() + * + * @brief: Camera SOC util for register read + * + * @soc_info: Device soc information + * @base_index: Index of register space in the HW block + * @offset: Offset of register to be read + * + * @return: Value read from the register address + */ +static inline uint32_t cam_soc_util_r(struct cam_hw_soc_info *soc_info, + uint32_t base_index, uint32_t offset) +{ + if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index)) + return 0; + return cam_io_r( + CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset); +} + +/** + * cam_soc_util_r_mb() + * + * @brief: Camera SOC util for register read with memory barrier. + * Memory Barrier is only before the write to ensure the + * order. If need to ensure this write is also flushed + * call rmb() independently in the caller. + * + * @soc_info: Device soc information + * @base_index: Index of register space in the HW block + * @offset: Offset of register to be read + * + * @return: Value read from the register address + */ +static inline uint32_t cam_soc_util_r_mb(struct cam_hw_soc_info *soc_info, + uint32_t base_index, uint32_t offset) +{ + if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index)) + return 0; + return cam_io_r_mb( + CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset); +} + +/** + * cam_soc_util_reg_dump() + * + * @brief: Camera SOC util for dumping a range of register + * + * @soc_info: Device soc information + * @base_index: Index of register space in the HW block + * @offset: Start register offset for the dump + * @size: Size specifying the range for dump + * + * @return: Success or Failure + */ +int cam_soc_util_reg_dump(struct cam_hw_soc_info *soc_info, + uint32_t base_index, uint32_t offset, int size); + +void cam_soc_util_clk_disable_default(struct cam_hw_soc_info *soc_info); + +int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info, + enum cam_vote_level clk_level); + +int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info, + int64_t clk_rate, int clk_idx, int32_t *clk_lvl); + +/* Callback to get reg space data for specific HW */ +typedef int (*cam_soc_util_regspace_data_cb)(uint32_t reg_base_type, + void *ctx, struct cam_hw_soc_info **soc_info_ptr, + uint32_t *reg_base_idx); + +/** + * cam_soc_util_reg_dump_to_cmd_buf() + * + * @brief: Camera SOC util for dumping sets of register ranges + * command buffer + * + * @ctx: Context info from specific hardware manager + * @cmd_desc: Command buffer descriptor + * @req_id: Last applied req id for which reg dump is required + * @reg_data_cb: Callback function to get reg space info based on type + * in command buffer + * @soc_dump_args: Dump buffer args to dump the soc information. + * @user_triggered_dump: Flag to indicate if the dump request is issued by + * user. + * @return: Success or Failure + */ +int cam_soc_util_reg_dump_to_cmd_buf(void *ctx, + struct cam_cmd_buf_desc *cmd_desc, uint64_t req_id, + cam_soc_util_regspace_data_cb reg_data_cb, + struct cam_hw_soc_dump_args *soc_dump_args, + bool user_triggered_dump); + +#endif /* _CAM_SOC_UTIL_H_ */ diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_trace.c b/techpack/camera-bengal/drivers/cam_utils/cam_trace.c new file mode 100644 index 0000000000000000000000000000000000000000..9b45091b4b85f1cc28fd8cdaefb6cb938cade09b --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_trace.c @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + */ + +/* Instantiate tracepoints */ +#define CREATE_TRACE_POINTS +#include "cam_trace.h" diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_trace.h b/techpack/camera-bengal/drivers/cam_utils/cam_trace.h new file mode 100644 index 0000000000000000000000000000000000000000..8055f25c6f21cc99331c82f474ae290e0dbf61b4 --- /dev/null +++ b/techpack/camera-bengal/drivers/cam_utils/cam_trace.h @@ -0,0 +1,359 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#if !defined(_CAM_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _CAM_TRACE_H + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM camera +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE ../../techpack/camera-bengal/drivers/cam_utils/cam_trace + +#include +#include +#include "cam_req_mgr_core.h" +#include "cam_req_mgr_interface.h" +#include "cam_context.h" + +#define CAM_DEFAULT_VALUE 0xFF + +TRACE_EVENT(cam_context_state, + TP_PROTO(const char *name, struct cam_context *ctx), + TP_ARGS(name, ctx), + TP_STRUCT__entry( + __field(void*, ctx) + __field(uint32_t, state) + __string(name, name) + ), + TP_fast_assign( + __entry->ctx = ctx; + __entry->state = ctx->state; + __assign_str(name, name); + ), + TP_printk( + "%s: State ctx=%p ctx_state=%u", + __get_str(name), __entry->ctx, __entry->state + ) +); + +TRACE_EVENT(cam_isp_activated_irq, + TP_PROTO(struct cam_context *ctx, unsigned int substate, + unsigned int event, uint64_t timestamp), + TP_ARGS(ctx, substate, event, timestamp), + TP_STRUCT__entry( + __field(void*, ctx) + __field(uint32_t, state) + __field(uint32_t, substate) + __field(uint32_t, event) + __field(uint64_t, ts) + ), + TP_fast_assign( + __entry->ctx = ctx; + __entry->state = ctx->state; + __entry->substate = substate; + __entry->event = event; + __entry->ts = timestamp; + ), + TP_printk( + "ISP: IRQ ctx=%p ctx_state=%u substate=%u event=%u ts=%llu", + __entry->ctx, __entry->state, __entry->substate, + __entry->event, __entry->ts + ) +); + +TRACE_EVENT(cam_log_event, + TP_PROTO(const char *string1, const char *string2, + uint64_t val1, uint64_t val2), + TP_ARGS(string1, string2, val1, val2), + TP_STRUCT__entry( + __string(string1, string1) + __string(string2, string2) + __field(uint64_t, val1) + __field(uint64_t, val2) + ), + TP_fast_assign( + __assign_str(string1, string1); + __assign_str(string2, string2); + __entry->val1 = val1; + __entry->val2 = val2; + ), + TP_printk( + "%s: %s val1=%llu val2=%llu", + __get_str(string1), __get_str(string2), + __entry->val1, __entry->val2 + ) +); + +TRACE_EVENT(cam_icp_fw_dbg, + TP_PROTO(char *dbg_message, uint64_t timestamp), + TP_ARGS(dbg_message, timestamp), + TP_STRUCT__entry( + __string(dbg_message, dbg_message) + __field(uint64_t, timestamp) + ), + TP_fast_assign( + __assign_str(dbg_message, dbg_message); + __entry->timestamp = timestamp; + ), + TP_printk( + "%llu %s: ", + __entry->timestamp, __get_str(dbg_message) + ) +); + +TRACE_EVENT(cam_buf_done, + TP_PROTO(const char *ctx_type, struct cam_context *ctx, + struct cam_ctx_request *req), + TP_ARGS(ctx_type, ctx, req), + TP_STRUCT__entry( + __string(ctx_type, ctx_type) + __field(void*, ctx) + __field(uint64_t, request) + ), + TP_fast_assign( + __assign_str(ctx_type, ctx_type); + __entry->ctx = ctx; + __entry->request = req->request_id; + ), + TP_printk( + "%5s: BufDone ctx=%p request=%llu", + __get_str(ctx_type), __entry->ctx, __entry->request + ) +); + +TRACE_EVENT(cam_apply_req, + TP_PROTO(const char *entity, uint64_t req_id), + TP_ARGS(entity, req_id), + TP_STRUCT__entry( + __string(entity, entity) + __field(uint64_t, req_id) + ), + TP_fast_assign( + __assign_str(entity, entity); + __entry->req_id = req_id; + ), + TP_printk( + "%8s: ApplyRequest request=%llu", + __get_str(entity), __entry->req_id + ) +); + +TRACE_EVENT(cam_flush_req, + TP_PROTO(struct cam_req_mgr_core_link *link, + struct cam_req_mgr_flush_info *info), + TP_ARGS(link, info), + TP_STRUCT__entry( + __field(uint32_t, type) + __field(int64_t, req_id) + __field(void*, link) + __field(void*, session) + ), + TP_fast_assign( + __entry->type = info->flush_type; + __entry->req_id = info->req_id; + __entry->link = link; + __entry->session = link->parent; + ), + TP_printk( + "FlushRequest type=%u request=%llu link=%pK session=%pK", + __entry->type, __entry->req_id, __entry->link, + __entry->session + ) +); + +TRACE_EVENT(cam_req_mgr_connect_device, + TP_PROTO(struct cam_req_mgr_core_link *link, + struct cam_req_mgr_device_info *info), + TP_ARGS(link, info), + TP_STRUCT__entry( + __string(name, info->name) + __field(uint32_t, id) + __field(uint32_t, delay) + __field(void*, link) + __field(void*, session) + ), + TP_fast_assign( + __assign_str(name, info->name); + __entry->id = info->dev_id; + __entry->delay = info->p_delay; + __entry->link = link; + __entry->session = link->parent; + ), + TP_printk( + "ReqMgr Connect name=%s id=%u pd=%d link=%pK session=%pK", + __get_str(name), __entry->id, __entry->delay, + __entry->link, __entry->session + ) +); + +TRACE_EVENT(cam_req_mgr_apply_request, + TP_PROTO(struct cam_req_mgr_core_link *link, + struct cam_req_mgr_apply_request *req, + struct cam_req_mgr_connected_device *dev), + TP_ARGS(link, req, dev), + TP_STRUCT__entry( + __string(name, dev->dev_info.name) + __field(uint32_t, dev_id) + __field(uint64_t, req_id) + __field(void*, link) + __field(void*, session) + ), + TP_fast_assign( + __assign_str(name, dev->dev_info.name); + __entry->dev_id = dev->dev_info.dev_id; + __entry->req_id = req->request_id; + __entry->link = link; + __entry->session = link->parent; + ), + TP_printk( + "ReqMgr ApplyRequest devname=%s devid=%u request=%lld link=%pK session=%pK", + __get_str(name), __entry->dev_id, __entry->req_id, + __entry->link, __entry->session + ) +); + +TRACE_EVENT(cam_req_mgr_add_req, + TP_PROTO(struct cam_req_mgr_core_link *link, + int idx, struct cam_req_mgr_add_request *add_req, + struct cam_req_mgr_req_tbl *tbl, + struct cam_req_mgr_connected_device *dev), + TP_ARGS(link, idx, add_req, tbl, dev), + TP_STRUCT__entry( + __string(name, dev->dev_info.name) + __field(uint32_t, dev_id) + __field(uint64_t, req_id) + __field(uint32_t, slot_id) + __field(uint32_t, delay) + __field(uint32_t, readymap) + __field(uint32_t, devicemap) + __field(void*, link) + __field(void*, session) + ), + TP_fast_assign( + __assign_str(name, dev->dev_info.name); + __entry->dev_id = dev->dev_info.dev_id; + __entry->req_id = add_req->req_id; + __entry->slot_id = idx; + __entry->delay = tbl->pd; + __entry->readymap = tbl->slot[idx].req_ready_map; + __entry->devicemap = tbl->dev_mask; + __entry->link = link; + __entry->session = link->parent; + ), + TP_printk( + "ReqMgr AddRequest devname=%s devid=%d request=%lld slot=%d pd=%d readymap=%x devicemap=%d link=%pK session=%pK", + __get_str(name), __entry->dev_id, __entry->req_id, + __entry->slot_id, __entry->delay, __entry->readymap, + __entry->devicemap, __entry->link, __entry->session + ) +); + +TRACE_EVENT(cam_delay_detect, + TP_PROTO(const char *entity, + const char *text, uint64_t req_id, + uint32_t ctx_id, int32_t link_hdl, + int32_t session_hdl, int rc), + TP_ARGS(entity, text, req_id, ctx_id, + link_hdl, session_hdl, rc), + TP_STRUCT__entry( + __string(entity, entity) + __string(text, text) + __field(uint64_t, req_id) + __field(uint64_t, ctx_id) + __field(int32_t, link_hdl) + __field(int32_t, session_hdl) + __field(int32_t, rc) + ), + TP_fast_assign( + __assign_str(entity, entity); + __assign_str(text, text); + __entry->req_id = req_id; + __entry->ctx_id = ctx_id; + __entry->link_hdl = link_hdl; + __entry->session_hdl = session_hdl; + __entry->rc = rc; + ), + TP_printk( + "%s: %s request=%lld ctx_id=%d link_hdl=0x%x session_hdl=0x%x rc=%d", + __get_str(entity), __get_str(text), __entry->req_id, + __entry->ctx_id, __entry->link_hdl, + __entry->session_hdl, __entry->rc + ) +); + +TRACE_EVENT(cam_submit_to_hw, + TP_PROTO(const char *entity, uint64_t req_id), + TP_ARGS(entity, req_id), + TP_STRUCT__entry( + __string(entity, entity) + __field(uint64_t, req_id) + ), + TP_fast_assign( + __assign_str(entity, entity); + __entry->req_id = req_id; + ), + TP_printk( + "%8s: submit request=%llu", + __get_str(entity), __entry->req_id + ) +); + +TRACE_EVENT(cam_irq_activated, + TP_PROTO(const char *entity, uint32_t irq_type), + TP_ARGS(entity, irq_type), + TP_STRUCT__entry( + __string(entity, entity) + __field(uint32_t, irq_type) + ), + TP_fast_assign( + __assign_str(entity, entity); + __entry->irq_type = irq_type; + ), + TP_printk( + "%8s: got irq type=%d", + __get_str(entity), __entry->irq_type + ) +); + +TRACE_EVENT(cam_irq_handled, + TP_PROTO(const char *entity, uint32_t irq_type), + TP_ARGS(entity, irq_type), + TP_STRUCT__entry( + __string(entity, entity) + __field(uint32_t, irq_type) + ), + TP_fast_assign( + __assign_str(entity, entity); + __entry->irq_type = irq_type; + ), + TP_printk( + "%8s: handled irq type=%d", + __get_str(entity), __entry->irq_type + ) +); + +TRACE_EVENT(cam_cdm_cb, + TP_PROTO(const char *entity, uint32_t status), + TP_ARGS(entity, status), + TP_STRUCT__entry( + __string(entity, entity) + __field(uint32_t, status) + ), + TP_fast_assign( + __assign_str(entity, entity); + __entry->status = status; + ), + TP_printk( + "%8s: cdm cb status=%d", + __get_str(entity), __entry->status + ) +); + +#endif /* _CAM_TRACE_H */ + +/* This part must be outside protection */ +#include diff --git a/techpack/camera-bengal/include/Kbuild b/techpack/camera-bengal/include/Kbuild new file mode 100644 index 0000000000000000000000000000000000000000..bab1145bc7a7d620c579e60abef2b6652603df78 --- /dev/null +++ b/techpack/camera-bengal/include/Kbuild @@ -0,0 +1,2 @@ +# Top-level Makefile calls into asm-$(ARCH) +# List only non-arch directories below diff --git a/techpack/camera-bengal/include/uapi/Kbuild b/techpack/camera-bengal/include/uapi/Kbuild new file mode 100644 index 0000000000000000000000000000000000000000..93dffc4bac8d6c34a0fdccf9cfaf3497d78d74c6 --- /dev/null +++ b/techpack/camera-bengal/include/uapi/Kbuild @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note + +header-y += media/ diff --git a/techpack/camera-bengal/include/uapi/media/Kbuild b/techpack/camera-bengal/include/uapi/media/Kbuild new file mode 100644 index 0000000000000000000000000000000000000000..e7971dac10518ef45c5db33df3a700c0673b4b47 --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/Kbuild @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note + +header-y += cam_cpas.h +header-y += cam_defs.h +header-y += cam_fd.h +header-y += cam_icp.h +header-y += cam_isp.h +header-y += cam_isp_vfe.h +header-y += cam_isp_ife.h +header-y += cam_jpeg.h +header-y += cam_req_mgr.h +header-y += cam_sensor.h +header-y += cam_sync.h +header-y += cam_lrme.h diff --git a/techpack/camera-bengal/include/uapi/media/cam_cpas.h b/techpack/camera-bengal/include/uapi/media/cam_cpas.h new file mode 100644 index 0000000000000000000000000000000000000000..2a44d93497b489657a7586af8f11c89e5097ea4a --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_cpas.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_CPAS_H__ +#define __UAPI_CAM_CPAS_H__ + +#include + +#define CAM_FAMILY_CAMERA_SS 1 +#define CAM_FAMILY_CPAS_SS 2 + +/* AXI BW Voting Version */ +#define CAM_AXI_BW_VOTING_V2 2 + +/* AXI BW Voting Transaction Type */ +#define CAM_AXI_TRANSACTION_READ 0 +#define CAM_AXI_TRANSACTION_WRITE 1 + +/* AXI BW Voting Path Data Type */ +#define CAM_AXI_PATH_DATA_IFE_START_OFFSET 0 +#define CAM_AXI_PATH_DATA_IFE_LINEAR (CAM_AXI_PATH_DATA_IFE_START_OFFSET + 0) +#define CAM_AXI_PATH_DATA_IFE_VID (CAM_AXI_PATH_DATA_IFE_START_OFFSET + 1) +#define CAM_AXI_PATH_DATA_IFE_DISP (CAM_AXI_PATH_DATA_IFE_START_OFFSET + 2) +#define CAM_AXI_PATH_DATA_IFE_STATS (CAM_AXI_PATH_DATA_IFE_START_OFFSET + 3) +#define CAM_AXI_PATH_DATA_IFE_RDI0 (CAM_AXI_PATH_DATA_IFE_START_OFFSET + 4) +#define CAM_AXI_PATH_DATA_IFE_RDI1 (CAM_AXI_PATH_DATA_IFE_START_OFFSET + 5) +#define CAM_AXI_PATH_DATA_IFE_RDI2 (CAM_AXI_PATH_DATA_IFE_START_OFFSET + 6) +#define CAM_AXI_PATH_DATA_IFE_RDI3 (CAM_AXI_PATH_DATA_IFE_START_OFFSET + 7) +#define CAM_AXI_PATH_DATA_IFE_PDAF (CAM_AXI_PATH_DATA_IFE_START_OFFSET + 8) +#define CAM_AXI_PATH_DATA_IFE_PIXEL_RAW \ + (CAM_AXI_PATH_DATA_IFE_START_OFFSET + 9) +#define CAM_AXI_PATH_DATA_IFE_MAX_OFFSET \ + (CAM_AXI_PATH_DATA_IFE_START_OFFSET + 31) + +#define CAM_AXI_PATH_DATA_IPE_START_OFFSET 32 +#define CAM_AXI_PATH_DATA_IPE_RD_IN (CAM_AXI_PATH_DATA_IPE_START_OFFSET + 0) +#define CAM_AXI_PATH_DATA_IPE_RD_REF (CAM_AXI_PATH_DATA_IPE_START_OFFSET + 1) +#define CAM_AXI_PATH_DATA_IPE_WR_VID (CAM_AXI_PATH_DATA_IPE_START_OFFSET + 2) +#define CAM_AXI_PATH_DATA_IPE_WR_DISP (CAM_AXI_PATH_DATA_IPE_START_OFFSET + 3) +#define CAM_AXI_PATH_DATA_IPE_WR_REF (CAM_AXI_PATH_DATA_IPE_START_OFFSET + 4) +#define CAM_AXI_PATH_DATA_IPE_MAX_OFFSET \ + (CAM_AXI_PATH_DATA_IPE_START_OFFSET + 31) + +#define CAM_AXI_PATH_DATA_OPE_START_OFFSET 64 +#define CAM_AXI_PATH_DATA_OPE_RD_IN (CAM_AXI_PATH_DATA_OPE_START_OFFSET + 0) +#define CAM_AXI_PATH_DATA_OPE_RD_REF (CAM_AXI_PATH_DATA_OPE_START_OFFSET + 1) +#define CAM_AXI_PATH_DATA_OPE_WR_VID (CAM_AXI_PATH_DATA_OPE_START_OFFSET + 2) +#define CAM_AXI_PATH_DATA_OPE_WR_DISP (CAM_AXI_PATH_DATA_OPE_START_OFFSET + 3) +#define CAM_AXI_PATH_DATA_OPE_WR_REF (CAM_AXI_PATH_DATA_OPE_START_OFFSET + 4) +#define CAM_AXI_PATH_DATA_OPE_MAX_OFFSET \ + (CAM_AXI_PATH_DATA_OPE_START_OFFSET + 31) + +#define CAM_AXI_PATH_DATA_ALL 256 + +/** + * struct cam_cpas_query_cap - CPAS query device capability payload + * + * @camera_family : Camera family type + * @reserved : Reserved field for alignment + * @camera_version : Camera platform version + * @cpas_version : Camera CPAS version within camera platform + * + */ +struct cam_cpas_query_cap { + uint32_t camera_family; + uint32_t reserved; + struct cam_hw_version camera_version; + struct cam_hw_version cpas_version; +}; + +/** + * struct cam_axi_per_path_bw_vote - Per path bandwidth vote information + * + * @usage_data client usage data (left/right/rdi) + * @transac_type Transaction type on the path (read/write) + * @path_data_type Path for which vote is given (video, display, rdi) + * @reserved Reserved for alignment + * @camnoc_bw CAMNOC bw for this path + * @mnoc_ab_bw MNOC AB bw for this path + * @mnoc_ib_bw MNOC IB bw for this path + * @ddr_ab_bw DDR AB bw for this path + * @ddr_ib_bw DDR IB bw for this path + */ +struct cam_axi_per_path_bw_vote { + uint32_t usage_data; + uint32_t transac_type; + uint32_t path_data_type; + uint32_t reserved; + uint64_t camnoc_bw; + uint64_t mnoc_ab_bw; + uint64_t mnoc_ib_bw; + uint64_t ddr_ab_bw; + uint64_t ddr_ib_bw; +}; + +#endif /* __UAPI_CAM_CPAS_H__ */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_custom.h b/techpack/camera-bengal/include/uapi/media/cam_custom.h new file mode 100644 index 0000000000000000000000000000000000000000..37edce171e4b68012b8d53b6317fc46af7992ba7 --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_custom.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_CUSTOM_H__ +#define __UAPI_CAM_CUSTOM_H__ + +#include "cam_defs.h" + +/* Custom driver name */ +#define CAM_CUSTOM_DEV_NAME "cam-custom" + +#define CAM_CUSTOM_NUM_SUB_DEVICES 2 + +/* HW type */ +#define CAM_CUSTOM_HW1 0 +#define CAM_CUSTOM_HW2 1 + +/* output path resource id's */ +#define CAM_CUSTOM_OUT_RES_UDI_0 1 +#define CAM_CUSTOM_OUT_RES_UDI_1 2 +#define CAM_CUSTOM_OUT_RES_UDI_2 3 + +/* input resource for custom hw */ +#define CAM_CUSTOM_IN_RES_UDI_0 1 + +/* Resource ID */ +#define CAM_CUSTOM_RES_ID_PORT 0 + +/* Packet opcode for Custom */ +#define CAM_CUSTOM_PACKET_OP_BASE 0 +#define CAM_CUSTOM_PACKET_INIT_DEV 1 +#define CAM_CUSTOM_PACKET_UPDATE_DEV 2 +#define CAM_CUSTOM_PACKET_OP_MAX 3 + +/* max number of vc-dt cfg for a given input */ +#define CAM_CUSTOM_VC_DT_CFG_MAX 4 + +/* phy input resource types */ +#define CAM_CUSTOM_IN_RES_BASE 0x5000 +#define CAM_CUSTOM_IN_RES_PHY_0 (CAM_CUSTOM_IN_RES_BASE + 1) +#define CAM_CUSTOM_IN_RES_PHY_1 (CAM_CUSTOM_IN_RES_BASE + 2) +#define CAM_CUSTOM_IN_RES_PHY_2 (CAM_CUSTOM_IN_RES_BASE + 3) +#define CAM_CUSTOM_IN_RES_PHY_3 (CAM_CUSTOM_IN_RES_BASE + 4) + +/* Query devices */ +/** + * struct cam_custom_dev_cap_info - A cap info for particular hw type + * + * @hw_type: Custom HW type + * @hw_version: Hardware version + * + */ +struct cam_custom_dev_cap_info { + uint32_t hw_type; + uint32_t hw_version; +}; + +/** + * struct cam_custom_query_cap_cmd - Custom HW query device capability payload + * + * @device_iommu: returned iommu handles for device + * @cdm_iommu: returned iommu handles for cdm + * @num_dev: returned number of device capabilities + * @reserved: reserved field for alignment + * @dev_caps: returned device capability array + * + */ +struct cam_custom_query_cap_cmd { + struct cam_iommu_handle device_iommu; + struct cam_iommu_handle cdm_iommu; + int32_t num_dev; + uint32_t reserved; + struct cam_custom_dev_cap_info dev_caps[CAM_CUSTOM_NUM_SUB_DEVICES]; +}; + +/* Acquire Device */ +/** + * struct cam_custom_out_port_info - An output port resource info + * + * @res_type: output resource type + * @format: output format of the resource + * @custom_info 1-3: custom params + * @reserved: reserved field for alignment + * + */ +struct cam_custom_out_port_info { + uint32_t res_type; + uint32_t format; + uint32_t custom_info1; + uint32_t custom_info2; + uint32_t custom_info3; + uint32_t reserved; +}; + +/** + * struct cam_custom_in_port_info - An input port resource info + * + * @res_type: input resource type + * @lane_type: lane type: c-phy or d-phy. + * @lane_num: active lane number + * @lane_cfg: lane configurations: 4 bits per lane + * @vc: input virtual channel number + * @dt: input data type number + * @num_valid_vc_dt: number of valid vc-dt + * @format: input format + * @test_pattern: test pattern for the testgen + * @usage_type: whether dual vfe is required + * @left_start: left input start offset in pixels + * @left_stop: left input stop offset in pixels + * @left_width: left input width in pixels + * @right_start: right input start offset in pixels. + * @right_stop: right input stop offset in pixels. + * @right_width: right input width in pixels. + * @line_start: top of the line number + * @line_stop: bottome of the line number + * @height: input height in lines + * @pixel_clk; sensor output clock + * @num_out_byte: number of valid output bytes per cycle + * @custom_info1: custom_info1 + * @custom_info2: custom info 2 + * @num_out_res: number of the output resource associated + * @data: payload that contains the output resources + * + */ +struct cam_custom_in_port_info { + uint32_t res_type; + uint32_t lane_type; + uint32_t lane_num; + uint32_t lane_cfg; + uint32_t vc[CAM_CUSTOM_VC_DT_CFG_MAX]; + uint32_t dt[CAM_CUSTOM_VC_DT_CFG_MAX]; + uint32_t num_valid_vc_dt; + uint32_t format; + uint32_t test_pattern; + uint32_t usage_type; + uint32_t left_start; + uint32_t left_stop; + uint32_t left_width; + uint32_t right_start; + uint32_t right_stop; + uint32_t right_width; + uint32_t line_start; + uint32_t line_stop; + uint32_t height; + uint32_t pixel_clk; + uint32_t num_bytes_out; + uint32_t custom_info1; + uint32_t custom_info2; + uint32_t num_out_res; + struct cam_custom_out_port_info data[1]; +}; + +/** + * struct cam_custom_resource - A resource bundle + * + * @resoruce_id: resource id for the resource bundle + * @length: length of the while resource blob + * @handle_type: type of the resource handle + * @reserved: reserved field for alignment + * @res_hdl: resource handle that points to the + * resource array; + */ +struct cam_custom_resource { + uint32_t resource_id; + uint32_t length; + uint32_t handle_type; + uint32_t reserved; + uint64_t res_hdl; +}; + +/** + * struct cam_custom_acquire_hw_info - Custom acquire HW params + * + * @num_inputs : Number of inputs + * @input_info_size : Size of input info struct used + * @input_info_offset : Offset of input info from start of data + * @reserved : reserved + * @data : Start of data region + */ +struct cam_custom_acquire_hw_info { + uint32_t num_inputs; + uint32_t input_info_size; + uint32_t input_info_offset; + uint32_t reserved; + uint64_t data; +}; + +/** + * struct cam_custom_cmd_buf_type_1 - cmd buf type 1 + * + * @custom_info: custom info + * @reserved: reserved + */ +struct cam_custom_cmd_buf_type_1 { + uint32_t custom_info; + uint32_t reserved; +}; + +/** + * struct cam_custom_cmd_buf_type_2 - cmd buf type 2 + * + * @custom_info1: Custom info 1 + * @custom_info2: Custom info 2 + * @custom_info3: Custom info 3 + * @reserved: reserved + */ +struct cam_custom_cmd_buf_type_2 { + uint32_t custom_info1; + uint32_t custom_info2; + uint32_t custom_info3; + uint32_t reserved; +}; +#endif /* __UAPI_CAM_CUSTOM_H__ */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_defs.h b/techpack/camera-bengal/include/uapi/media/cam_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..52d14a2d3fb3711c6c2f89ee396355ea56abf946 --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_defs.h @@ -0,0 +1,894 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_DEFS_H__ +#define __UAPI_CAM_DEFS_H__ + +#include +#include +#include + + +/* camera op codes */ +#define CAM_COMMON_OPCODE_BASE 0x100 +#define CAM_QUERY_CAP (CAM_COMMON_OPCODE_BASE + 0x1) +#define CAM_ACQUIRE_DEV (CAM_COMMON_OPCODE_BASE + 0x2) +#define CAM_START_DEV (CAM_COMMON_OPCODE_BASE + 0x3) +#define CAM_STOP_DEV (CAM_COMMON_OPCODE_BASE + 0x4) +#define CAM_CONFIG_DEV (CAM_COMMON_OPCODE_BASE + 0x5) +#define CAM_RELEASE_DEV (CAM_COMMON_OPCODE_BASE + 0x6) +#define CAM_SD_SHUTDOWN (CAM_COMMON_OPCODE_BASE + 0x7) +#define CAM_FLUSH_REQ (CAM_COMMON_OPCODE_BASE + 0x8) +#define CAM_COMMON_OPCODE_MAX (CAM_COMMON_OPCODE_BASE + 0x9) + +#define CAM_COMMON_OPCODE_BASE_v2 0x150 +#define CAM_ACQUIRE_HW (CAM_COMMON_OPCODE_BASE_v2 + 0x1) +#define CAM_RELEASE_HW (CAM_COMMON_OPCODE_BASE_v2 + 0x2) +#define CAM_DUMP_REQ (CAM_COMMON_OPCODE_BASE_v2 + 0x3) + +#define CAM_EXT_OPCODE_BASE 0x200 +#define CAM_CONFIG_DEV_EXTERNAL (CAM_EXT_OPCODE_BASE + 0x1) + +/* camera handle type */ +#define CAM_HANDLE_USER_POINTER 1 +#define CAM_HANDLE_MEM_HANDLE 2 + +/* Generic Blob CmdBuffer header properties */ +#define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_MASK 0xFFFFFF00 +#define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_SHIFT 8 +#define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_MASK 0xFF +#define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_SHIFT 0 + +/* Command Buffer Types */ +#define CAM_CMD_BUF_DMI 0x1 +#define CAM_CMD_BUF_DMI16 0x2 +#define CAM_CMD_BUF_DMI32 0x3 +#define CAM_CMD_BUF_DMI64 0x4 +#define CAM_CMD_BUF_DIRECT 0x5 +#define CAM_CMD_BUF_INDIRECT 0x6 +#define CAM_CMD_BUF_I2C 0x7 +#define CAM_CMD_BUF_FW 0x8 +#define CAM_CMD_BUF_GENERIC 0x9 +#define CAM_CMD_BUF_LEGACY 0xA + +/* UBWC API Version */ +#define CAM_UBWC_CFG_VERSION_1 1 +#define CAM_UBWC_CFG_VERSION_2 2 + +#define CAM_MAX_ACQ_RES 5 +#define CAM_MAX_HW_SPLIT 3 + + +/** + * enum flush_type_t - Identifies the various flush types + * + * @CAM_FLUSH_TYPE_REQ: Flush specific request + * @CAM_FLUSH_TYPE_ALL: Flush all requests belonging to a context + * @CAM_FLUSH_TYPE_MAX: Max enum to validate flush type + * + */ +enum flush_type_t { + CAM_FLUSH_TYPE_REQ, + CAM_FLUSH_TYPE_ALL, + CAM_FLUSH_TYPE_MAX +}; + +/** + * struct cam_control - Structure used by ioctl control for camera + * + * @op_code: This is the op code for camera control + * @size: Control command size + * @handle_type: User pointer or shared memory handle + * @reserved: Reserved field for 64 bit alignment + * @handle: Control command payload + */ +struct cam_control { + uint32_t op_code; + uint32_t size; + uint32_t handle_type; + uint32_t reserved; + uint64_t handle; +}; + +/* camera IOCTL */ +#define VIDIOC_CAM_CONTROL \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_control) + +/** + * struct cam_hw_version - Structure for HW version of camera devices + * + * @major : Hardware version major + * @minor : Hardware version minor + * @incr : Hardware version increment + * @reserved : Reserved for 64 bit aligngment + */ +struct cam_hw_version { + uint32_t major; + uint32_t minor; + uint32_t incr; + uint32_t reserved; +}; + +/** + * struct cam_iommu_handle - Structure for IOMMU handles of camera hw devices + * + * @non_secure: Device Non Secure IOMMU handle + * @secure: Device Secure IOMMU handle + * + */ +struct cam_iommu_handle { + int32_t non_secure; + int32_t secure; +}; + +/* camera secure mode */ +#define CAM_SECURE_MODE_NON_SECURE 0 +#define CAM_SECURE_MODE_SECURE 1 + +/* Camera Format Type */ +#define CAM_FORMAT_BASE 0 +#define CAM_FORMAT_MIPI_RAW_6 1 +#define CAM_FORMAT_MIPI_RAW_8 2 +#define CAM_FORMAT_MIPI_RAW_10 3 +#define CAM_FORMAT_MIPI_RAW_12 4 +#define CAM_FORMAT_MIPI_RAW_14 5 +#define CAM_FORMAT_MIPI_RAW_16 6 +#define CAM_FORMAT_MIPI_RAW_20 7 +#define CAM_FORMAT_QTI_RAW_8 8 +#define CAM_FORMAT_QTI_RAW_10 9 +#define CAM_FORMAT_QTI_RAW_12 10 +#define CAM_FORMAT_QTI_RAW_14 11 +#define CAM_FORMAT_PLAIN8 12 +#define CAM_FORMAT_PLAIN16_8 13 +#define CAM_FORMAT_PLAIN16_10 14 +#define CAM_FORMAT_PLAIN16_12 15 +#define CAM_FORMAT_PLAIN16_14 16 +#define CAM_FORMAT_PLAIN16_16 17 +#define CAM_FORMAT_PLAIN32_20 18 +#define CAM_FORMAT_PLAIN64 19 +#define CAM_FORMAT_PLAIN128 20 +#define CAM_FORMAT_ARGB 21 +#define CAM_FORMAT_ARGB_10 22 +#define CAM_FORMAT_ARGB_12 23 +#define CAM_FORMAT_ARGB_14 24 +#define CAM_FORMAT_DPCM_10_6_10 25 +#define CAM_FORMAT_DPCM_10_8_10 26 +#define CAM_FORMAT_DPCM_12_6_12 27 +#define CAM_FORMAT_DPCM_12_8_12 28 +#define CAM_FORMAT_DPCM_14_8_14 29 +#define CAM_FORMAT_DPCM_14_10_14 30 +#define CAM_FORMAT_NV21 31 +#define CAM_FORMAT_NV12 32 +#define CAM_FORMAT_TP10 33 +#define CAM_FORMAT_YUV422 34 +#define CAM_FORMAT_PD8 35 +#define CAM_FORMAT_PD10 36 +#define CAM_FORMAT_UBWC_NV12 37 +#define CAM_FORMAT_UBWC_NV12_4R 38 +#define CAM_FORMAT_UBWC_TP10 39 +#define CAM_FORMAT_UBWC_P010 40 +#define CAM_FORMAT_PLAIN8_SWAP 41 +#define CAM_FORMAT_PLAIN8_10 42 +#define CAM_FORMAT_PLAIN8_10_SWAP 43 +#define CAM_FORMAT_YV12 44 +#define CAM_FORMAT_Y_ONLY 45 +#define CAM_FORMAT_DPCM_12_10_12 46 +#define CAM_FORMAT_PLAIN32 47 +#define CAM_FORMAT_ARGB_16 48 +#define CAM_FORMAT_MAX 49 + +/* Pixel Patterns */ +#define PIXEL_PATTERN_RGRGRG 0x0 +#define PIXEL_PATTERN_GRGRGR 0x1 +#define PIXEL_PATTERN_BGBGBG 0x2 +#define PIXEL_PATTERN_GBGBGB 0x3 +#define PIXEL_PATTERN_YCBYCR 0x4 +#define PIXEL_PATTERN_YCRYCB 0x5 +#define PIXEL_PATTERN_CBYCRY 0x6 +#define PIXEL_PATTERN_CRYCBY 0x7 + +/* camera rotaion */ +#define CAM_ROTATE_CW_0_DEGREE 0 +#define CAM_ROTATE_CW_90_DEGREE 1 +#define CAM_RORATE_CW_180_DEGREE 2 +#define CAM_ROTATE_CW_270_DEGREE 3 + +/* camera Color Space */ +#define CAM_COLOR_SPACE_BASE 0 +#define CAM_COLOR_SPACE_BT601_FULL 1 +#define CAM_COLOR_SPACE_BT601625 2 +#define CAM_COLOR_SPACE_BT601525 3 +#define CAM_COLOR_SPACE_BT709 4 +#define CAM_COLOR_SPACE_DEPTH 5 +#define CAM_COLOR_SPACE_MAX 6 + +/* camera buffer direction */ +#define CAM_BUF_INPUT 1 +#define CAM_BUF_OUTPUT 2 +#define CAM_BUF_IN_OUT 3 + +/* camera packet device Type */ +#define CAM_PACKET_DEV_BASE 0 +#define CAM_PACKET_DEV_IMG_SENSOR 1 +#define CAM_PACKET_DEV_ACTUATOR 2 +#define CAM_PACKET_DEV_COMPANION 3 +#define CAM_PACKET_DEV_EEPOM 4 +#define CAM_PACKET_DEV_CSIPHY 5 +#define CAM_PACKET_DEV_OIS 6 +#define CAM_PACKET_DEV_FLASH 7 +#define CAM_PACKET_DEV_FD 8 +#define CAM_PACKET_DEV_JPEG_ENC 9 +#define CAM_PACKET_DEV_JPEG_DEC 10 +#define CAM_PACKET_DEV_VFE 11 +#define CAM_PACKET_DEV_CPP 12 +#define CAM_PACKET_DEV_CSID 13 +#define CAM_PACKET_DEV_ISPIF 14 +#define CAM_PACKET_DEV_IFE 15 +#define CAM_PACKET_DEV_ICP 16 +#define CAM_PACKET_DEV_LRME 17 +#define CAM_PACKET_DEV_TFE 18 +#define CAM_PACKET_DEV_OPE 19 +#define CAM_PACKET_DEV_MAX 20 + +/* Register base type */ +#define CAM_REG_DUMP_BASE_TYPE_ISP_LEFT 1 +#define CAM_REG_DUMP_BASE_TYPE_ISP_RIGHT 2 +#define CAM_REG_DUMP_BASE_TYPE_CAMNOC 3 + +/* Register dump read type */ +#define CAM_REG_DUMP_READ_TYPE_CONT_RANGE 1 +#define CAM_REG_DUMP_READ_TYPE_DMI 2 + +/* Max number of config writes to read from DMI */ +#define CAM_REG_DUMP_DMI_CONFIG_MAX 5 + + +/* constants */ +#define CAM_PACKET_MAX_PLANES 3 + +/** + * struct cam_plane_cfg - Plane configuration info + * + * @width: Plane width in pixels + * @height: Plane height in lines + * @plane_stride: Plane stride in pixel + * @slice_height: Slice height in line (not used by ISP) + * @meta_stride: UBWC metadata stride + * @meta_size: UBWC metadata plane size + * @meta_offset: UBWC metadata offset + * @packer_config: UBWC packer config + * @mode_config: UBWC mode config + * @tile_config: UBWC tile config + * @h_init: UBWC horizontal initial coordinate in pixels + * @v_init: UBWC vertical initial coordinate in lines + * + */ +struct cam_plane_cfg { + uint32_t width; + uint32_t height; + uint32_t plane_stride; + uint32_t slice_height; + uint32_t meta_stride; + uint32_t meta_size; + uint32_t meta_offset; + uint32_t packer_config; + uint32_t mode_config; + uint32_t tile_config; + uint32_t h_init; + uint32_t v_init; +}; + +/** + * struct cam_ubwc_plane_cfg_v1 - UBWC Plane configuration info + * + * @port_type: Port Type + * @meta_stride: UBWC metadata stride + * @meta_size: UBWC metadata plane size + * @meta_offset: UBWC metadata offset + * @packer_config: UBWC packer config + * @mode_config_0: UBWC mode config 0 + * @mode_config_1: UBWC 3 mode config 1 + * @tile_config: UBWC tile config + * @h_init: UBWC horizontal initial coordinate in pixels + * @v_init: UBWC vertical initial coordinate in lines + * + */ +struct cam_ubwc_plane_cfg_v1 { + uint32_t port_type; + uint32_t meta_stride; + uint32_t meta_size; + uint32_t meta_offset; + uint32_t packer_config; + uint32_t mode_config_0; + uint32_t mode_config_1; + uint32_t tile_config; + uint32_t h_init; + uint32_t v_init; +}; + +/** + * struct cam_ubwc_plane_cfg_v2 - UBWC Plane configuration info + * + * @port_type: Port Type + * @meta_stride: UBWC metadata stride + * @meta_size: UBWC metadata plane size + * @meta_offset: UBWC metadata offset + * @packer_config: UBWC packer config + * @mode_config: UBWC mode config + * @static ctrl: UBWC static ctrl + * @ctrl_2: UBWC ctrl 2 + * @tile_config: UBWC tile config + * @h_init: UBWC horizontal initial coordinate in pixels + * @v_init: UBWC vertical initial coordinate in lines + * @stats_ctrl_2: UBWC stats control + * @lossy_threshold0 UBWC lossy threshold 0 + * @lossy_threshold1 UBWC lossy threshold 1 + * @lossy_var_offset UBWC offset variance thrshold + * + */ +struct cam_ubwc_plane_cfg_v2 { + uint32_t port_type; + uint32_t meta_stride; + uint32_t meta_size; + uint32_t meta_offset; + uint32_t packer_config; + uint32_t mode_config_0; + uint32_t mode_config_1; + uint32_t tile_config; + uint32_t h_init; + uint32_t v_init; + uint32_t static_ctrl; + uint32_t ctrl_2; + uint32_t stats_ctrl_2; + uint32_t lossy_threshold_0; + uint32_t lossy_threshold_1; + uint32_t lossy_var_offset; + uint32_t bandwidth_limit; + uint32_t reserved[3]; +}; +/** + * struct cam_cmd_buf_desc - Command buffer descriptor + * + * @mem_handle: Command buffer handle + * @offset: Command start offset + * @size: Size of the command buffer in bytes + * @length: Used memory in command buffer in bytes + * @type: Type of the command buffer + * @meta_data: Data type for private command buffer + * Between UMD and KMD + * + */ +struct cam_cmd_buf_desc { + int32_t mem_handle; + uint32_t offset; + uint32_t size; + uint32_t length; + uint32_t type; + uint32_t meta_data; +}; + +/** + * struct cam_buf_io_cfg - Buffer io configuration for buffers + * + * @mem_handle: Mem_handle array for the buffers. + * @offsets: Offsets for each planes in the buffer + * @planes: Per plane information + * @width: Main plane width in pixel + * @height: Main plane height in lines + * @format: Format of the buffer + * @color_space: Color space for the buffer + * @color_pattern: Color pattern in the buffer + * @bpp: Bit per pixel + * @rotation: Rotation information for the buffer + * @resource_type: Resource type associated with the buffer + * @fence: Fence handle + * @early_fence: Fence handle for early signal + * @aux_cmd_buf: An auxiliary command buffer that may be + * used for programming the IO + * @direction: Direction of the config + * @batch_size: Batch size in HFR mode + * @subsample_pattern: Subsample pattern. Used in HFR mode. It + * should be consistent with batchSize and + * CAMIF programming. + * @subsample_period: Subsample period. Used in HFR mode. It + * should be consistent with batchSize and + * CAMIF programming. + * @framedrop_pattern: Framedrop pattern + * @framedrop_period: Framedrop period + * @flag: Flags for extra information + * @direction: Buffer direction: input or output + * @padding: Padding for the structure + * + */ +struct cam_buf_io_cfg { + int32_t mem_handle[CAM_PACKET_MAX_PLANES]; + uint32_t offsets[CAM_PACKET_MAX_PLANES]; + struct cam_plane_cfg planes[CAM_PACKET_MAX_PLANES]; + uint32_t format; + uint32_t color_space; + uint32_t color_pattern; + uint32_t bpp; + uint32_t rotation; + uint32_t resource_type; + int32_t fence; + int32_t early_fence; + struct cam_cmd_buf_desc aux_cmd_buf; + uint32_t direction; + uint32_t batch_size; + uint32_t subsample_pattern; + uint32_t subsample_period; + uint32_t framedrop_pattern; + uint32_t framedrop_period; + uint32_t flag; + uint32_t padding; +}; + +/** + * struct cam_packet_header - Camera packet header + * + * @op_code: Camera packet opcode + * @size: Size of the camera packet in bytes + * @request_id: Request id for this camera packet + * @flags: Flags for the camera packet + * @padding: Padding + * + */ +struct cam_packet_header { + uint32_t op_code; + uint32_t size; + uint64_t request_id; + uint32_t flags; + uint32_t padding; +}; + +/** + * struct cam_patch_desc - Patch structure + * + * @dst_buf_hdl: Memory handle for the dest buffer + * @dst_offset: Offset byte in the dest buffer + * @src_buf_hdl: Memory handle for the source buffer + * @src_offset: Offset byte in the source buffer + * + */ +struct cam_patch_desc { + int32_t dst_buf_hdl; + uint32_t dst_offset; + int32_t src_buf_hdl; + uint32_t src_offset; +}; + +/** + * struct cam_packet - Camera packet structure + * + * @header: Camera packet header + * @cmd_buf_offset: Command buffer start offset + * @num_cmd_buf: Number of the command buffer in the packet + * @io_config_offset: Buffer io configuration start offset + * @num_io_configs: Number of the buffer io configurations + * @patch_offset: Patch offset for the patch structure + * @num_patches: Number of the patch structure + * @kmd_cmd_buf_index: Command buffer index which contains extra + * space for the KMD buffer + * @kmd_cmd_buf_offset: Offset from the beginning of the command + * buffer for KMD usage. + * @payload: Camera packet payload + * + */ +struct cam_packet { + struct cam_packet_header header; + uint32_t cmd_buf_offset; + uint32_t num_cmd_buf; + uint32_t io_configs_offset; + uint32_t num_io_configs; + uint32_t patch_offset; + uint32_t num_patches; + uint32_t kmd_cmd_buf_index; + uint32_t kmd_cmd_buf_offset; + uint64_t payload[1]; + +}; + +/** + * struct cam_release_dev_cmd - Control payload for release devices + * + * @session_handle: Session handle for the release + * @dev_handle: Device handle for the release + */ +struct cam_release_dev_cmd { + int32_t session_handle; + int32_t dev_handle; +}; + +/** + * struct cam_start_stop_dev_cmd - Control payload for start/stop device + * + * @session_handle: Session handle for the start/stop command + * @dev_handle: Device handle for the start/stop command + * + */ +struct cam_start_stop_dev_cmd { + int32_t session_handle; + int32_t dev_handle; +}; + +/** + * struct cam_config_dev_cmd - Command payload for configure device + * + * @session_handle: Session handle for the command + * @dev_handle: Device handle for the command + * @offset: Offset byte in the packet handle. + * @packet_handle: Packet memory handle for the actual packet: + * struct cam_packet. + * + */ +struct cam_config_dev_cmd { + int32_t session_handle; + int32_t dev_handle; + uint64_t offset; + uint64_t packet_handle; +}; + +/** + * struct cam_query_cap_cmd - Payload for query device capability + * + * @size: Handle size + * @handle_type: User pointer or shared memory handle + * @caps_handle: Device specific query command payload + * + */ +struct cam_query_cap_cmd { + uint32_t size; + uint32_t handle_type; + uint64_t caps_handle; +}; + +/** + * struct cam_acquire_dev_cmd - Control payload for acquire devices + * + * @session_handle: Session handle for the acquire command + * @dev_handle: Device handle to be returned + * @handle_type: Resource handle type: + * 1 = user pointer, 2 = mem handle + * @num_resources: Number of the resources to be acquired + * @resources_hdl: Resource handle that refers to the actual + * resource array. Each item in this + * array is device specific resource structure + * + */ +struct cam_acquire_dev_cmd { + int32_t session_handle; + int32_t dev_handle; + uint32_t handle_type; + uint32_t num_resources; + uint64_t resource_hdl; +}; + +/* + * In old version, while acquiring device the num_resources in + * struct cam_acquire_dev_cmd will be a valid value. During ACQUIRE_DEV + * KMD driver will return dev_handle as well as associate HW to handle. + * If num_resources is set to the constant below, we are using + * the new version and we do not acquire HW in ACQUIRE_DEV IOCTL. + * ACQUIRE_DEV will only return handle and we should receive + * ACQUIRE_HW IOCTL after ACQUIRE_DEV and that is when the HW + * is associated with the dev_handle. + * + * (Data type): uint32_t + */ +#define CAM_API_COMPAT_CONSTANT 0xFEFEFEFE + +#define CAM_ACQUIRE_HW_STRUCT_VERSION_1 1 +#define CAM_ACQUIRE_HW_STRUCT_VERSION_2 2 + +/** + * struct cam_acquire_hw_cmd_v1 - Control payload for acquire HW IOCTL (Ver 1) + * + * @struct_version: = CAM_ACQUIRE_HW_STRUCT_VERSION_1 for this struct + * This value should be the first 32-bits in any structure + * related to this IOCTL. So that if the struct needs to + * change, we can first read the starting 32-bits, get the + * version number and then typecast the data to struct + * accordingly. + * @reserved: Reserved field for 64-bit alignment + * @session_handle: Session handle for the acquire command + * @dev_handle: Device handle to be returned + * @handle_type: Tells you how to interpret the variable resource_hdl- + * 1 = user pointer, 2 = mem handle + * @data_size: Total size of data contained in memory pointed + * to by resource_hdl + * @resource_hdl: Resource handle that refers to the actual + * resource data. + */ +struct cam_acquire_hw_cmd_v1 { + uint32_t struct_version; + uint32_t reserved; + int32_t session_handle; + int32_t dev_handle; + uint32_t handle_type; + uint32_t data_size; + uint64_t resource_hdl; +}; + +/** + * struct cam_acquired_hw_info - Update the acquired hardware info + * + * @acquired_hw_id: Acquired hardware mask + * @acquired_hw_path: Acquired path mask for an input + * if input splits into multiple paths, + * its updated per hardware + * valid_acquired_hw: Valid num of acquired hardware + */ +struct cam_acquired_hw_info { + uint32_t acquired_hw_id[CAM_MAX_ACQ_RES]; + uint32_t acquired_hw_path[CAM_MAX_ACQ_RES][CAM_MAX_HW_SPLIT]; + uint32_t valid_acquired_hw; +}; + +/** + * struct cam_acquire_hw_cmd_v2 - Control payload for acquire HW IOCTL (Ver 2) + * + * @struct_version: = CAM_ACQUIRE_HW_STRUCT_VERSION_2 for this struct + * This value should be the first 32-bits in any structure + * related to this IOCTL. So that if the struct needs to + * change, we can first read the starting 32-bits, get the + * version number and then typecast the data to struct + * accordingly. + * @reserved: Reserved field for 64-bit alignment + * @session_handle: Session handle for the acquire command + * @dev_handle: Device handle to be returned + * @handle_type: Tells you how to interpret the variable resource_hdl- + * 1 = user pointer, 2 = mem handle + * @data_size: Total size of data contained in memory pointed + * to by resource_hdl + * @resource_hdl: Resource handle that refers to the actual + * resource data. + */ +struct cam_acquire_hw_cmd_v2 { + uint32_t struct_version; + uint32_t reserved; + int32_t session_handle; + int32_t dev_handle; + uint32_t handle_type; + uint32_t data_size; + uint64_t resource_hdl; + struct cam_acquired_hw_info hw_info; +}; + +#define CAM_RELEASE_HW_STRUCT_VERSION_1 1 + +/** + * struct cam_release_hw_cmd_v1 - Control payload for release HW IOCTL (Ver 1) + * + * @struct_version: = CAM_RELEASE_HW_STRUCT_VERSION_1 for this struct + * This value should be the first 32-bits in any structure + * related to this IOCTL. So that if the struct needs to + * change, we can first read the starting 32-bits, get the + * version number and then typecast the data to struct + * accordingly. + * @reserved: Reserved field for 64-bit alignment + * @session_handle: Session handle for the release + * @dev_handle: Device handle for the release + */ +struct cam_release_hw_cmd_v1 { + uint32_t struct_version; + uint32_t reserved; + int32_t session_handle; + int32_t dev_handle; +}; + +/** + * struct cam_flush_dev_cmd - Control payload for flush devices + * + * @version: Version + * @session_handle: Session handle for the acquire command + * @dev_handle: Device handle to be returned + * @flush_type: Flush type: + * 0 = flush specific request + * 1 = flush all + * @reserved: Reserved for 64 bit aligngment + * @req_id: Request id that needs to cancel + * + */ +struct cam_flush_dev_cmd { + uint64_t version; + int32_t session_handle; + int32_t dev_handle; + uint32_t flush_type; + uint32_t reserved; + int64_t req_id; +}; + +/** + * struct cam_ubwc_config - UBWC Configuration Payload + * + * @api_version: UBWC config api version + * @num_ports: Number of ports to be configured + * @ubwc_plane_config: Array of UBWC configurations per port + * Size [CAM_PACKET_MAX_PLANES - 1] per port + * as UBWC is supported on Y & C planes + * and therefore a max size of 2 planes + * + */ +struct cam_ubwc_config { + uint32_t api_version; + uint32_t num_ports; + struct cam_ubwc_plane_cfg_v1 + ubwc_plane_cfg[1][CAM_PACKET_MAX_PLANES - 1]; +}; + +/** + * struct cam_ubwc_config_v2 - UBWC Configuration Payload + * + * @api_version: UBWC config api version + * @num_ports: Number of ports to be configured + * @ubwc_plane_config: Array of UBWC configurations per port + * Size [CAM_PACKET_MAX_PLANES - 1] per port + * as UBWC is supported on Y & C planes + * and therefore a max size of 2 planes + * + */ +struct cam_ubwc_config_v2 { + uint32_t api_version; + uint32_t num_ports; + struct cam_ubwc_plane_cfg_v2 + ubwc_plane_cfg[1][CAM_PACKET_MAX_PLANES - 1]; +}; + +/** + * struct cam_cmd_mem_region_info - + * Cmd buffer region info + * + * @mem_handle : Memory handle of the region + * @offset : Offset if any + * @size : Size of the region + * @flags : Flags if any + */ +struct cam_cmd_mem_region_info { + int32_t mem_handle; + uint32_t offset; + uint32_t size; + uint32_t flags; +}; + +/** + * struct cam_cmd_mem_regions - + * List of multiple memory descriptors of + * of different regions + * + * @version : Version number + * @num_regions : Number of regions + * @map_info_array : Array of all the regions + */ +struct cam_cmd_mem_regions { + uint32_t version; + uint32_t num_regions; + struct cam_cmd_mem_region_info map_info_array[1]; +}; + +/** + * struct cam_reg_write_desc - Register write descriptor + * + * @offset : Register offset at which 'value' needs to written + * @value : Register value to write + */ +struct cam_reg_write_desc { + uint32_t offset; + uint32_t value; +}; + +/** + * struct cam_reg_range_read_desc - Descriptor to provide read info + * + * @offset : Register offset address to start with + * @num_values : Number of values to read + */ +struct cam_reg_range_read_desc { + uint32_t offset; + uint32_t num_values; +}; + +/** + * struct cam_dmi_read_desc - Descriptor to provide DMI read info + * + * @num_pre_writes : Number of registers to write before reading DMI data + * @num_post_writes : Number of registers to write after reading DMI data + * @pre_read_config : Registers to write before reading DMI data + * @dmi_data_read : DMI Register, number of values to read to dump + * DMI data + * @post_read_config : Registers to write after reading DMI data + */ +struct cam_dmi_read_desc { + uint32_t num_pre_writes; + uint32_t num_post_writes; + struct cam_reg_write_desc pre_read_config[ + CAM_REG_DUMP_DMI_CONFIG_MAX]; + struct cam_reg_range_read_desc dmi_data_read; + struct cam_reg_write_desc post_read_config[ + CAM_REG_DUMP_DMI_CONFIG_MAX]; +}; + +/** + * struct cam_reg_read_info - Register read info for both reg continuous read + * or DMI read + * + * @type : Whether Register range read or DMI read + * @reg_read : Range of registers to read + * @dmi_read : DMI data to read + */ +struct cam_reg_read_info { + uint32_t type; + uint32_t reserved; + union { + struct cam_reg_range_read_desc reg_read; + struct cam_dmi_read_desc dmi_read; + }; +}; + +/** + * struct cam_reg_dump_out_buffer -Buffer info for dump data to be provided + * + * @req_id : Request ID corresponding to reg dump data + * @bytes_written : Number of bytes written + * @dump_data : Register dump data + */ +struct cam_reg_dump_out_buffer { + uint64_t req_id; + uint32_t bytes_written; + uint32_t dump_data[1]; +}; + +/** + * struct cam_reg_dump_desc - Descriptor to provide dump info + * + * @reg_base_type : Register base type, e.g. ISP_LEFT, ISP_RIGHT, CAMNOC + * @dump_buffer_offset : Offset from base of mem_handle at which Register dump + * will be written for this set + * @dump_buffer_size : Available size in bytes for writing dump values + * @num_read_range : Number register range reads (Continuous + DMI) + * @read_range : Read range info + */ +struct cam_reg_dump_desc { + uint32_t reg_base_type; + uint32_t dump_buffer_offset; + uint32_t dump_buffer_size; + uint32_t num_read_range; + struct cam_reg_read_info read_range[1]; +}; + +/** + * struct cam_reg_dump_input_info - Info about required dump sets + * + * @num_dump_sets : Number of different dump sets (base types) given + * @dump_set_offsets : Points to the given dump description structures + * (cam_reg_dump_desc) + */ +struct cam_reg_dump_input_info { + uint32_t num_dump_sets; + uint32_t dump_set_offsets[1]; +}; + +/** + * struct cam_dump_req_cmd - + * Dump the information of issue req id + * + * @issue_req_id : Issue Request Id + * @offset : Offset for the buffer + * @buf_handle : Buffer Handle + * @error_type : Error type, using it, dumping information can be extended + * @session_handle : Session Handle + * @link_hdl : link handle + * @dev_handle : Device Handle + */ +struct cam_dump_req_cmd { + uint64_t issue_req_id; + size_t offset; + uint32_t buf_handle; + uint32_t error_type; + int32_t session_handle; + int32_t link_hdl; + int32_t dev_handle; +}; + +#endif /* __UAPI_CAM_DEFS_H__ */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_fd.h b/techpack/camera-bengal/include/uapi/media/cam_fd.h new file mode 100644 index 0000000000000000000000000000000000000000..126be4555f69eb5a062ba1a54388285187ae5c38 --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_fd.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_FD_H__ +#define __UAPI_CAM_FD_H__ + +#include + +#define CAM_FD_MAX_FACES 35 +#define CAM_FD_RAW_RESULT_ENTRIES 512 + +/* FD Op Codes */ +#define CAM_PACKET_OPCODES_FD_FRAME_UPDATE 0x0 + +/* FD Command Buffer identifiers */ +#define CAM_FD_CMD_BUFFER_ID_GENERIC 0x0 +#define CAM_FD_CMD_BUFFER_ID_CDM 0x1 +#define CAM_FD_CMD_BUFFER_ID_MAX 0x2 + +/* FD Blob types */ +#define CAM_FD_BLOB_TYPE_SOC_CLOCK_BW_REQUEST 0x0 +#define CAM_FD_BLOB_TYPE_RAW_RESULTS_REQUIRED 0x1 + +/* FD Resource IDs */ +#define CAM_FD_INPUT_PORT_ID_IMAGE 0x0 +#define CAM_FD_INPUT_PORT_ID_MAX 0x1 + +#define CAM_FD_OUTPUT_PORT_ID_RESULTS 0x0 +#define CAM_FD_OUTPUT_PORT_ID_RAW_RESULTS 0x1 +#define CAM_FD_OUTPUT_PORT_ID_WORK_BUFFER 0x2 +#define CAM_FD_OUTPUT_PORT_ID_MAX 0x3 + +/** + * struct cam_fd_soc_clock_bw_request - SOC clock, bandwidth request info + * + * @clock_rate : Clock rate required while processing frame + * @bandwidth : Bandwidth required while processing frame + * @reserved : Reserved for future use + */ +struct cam_fd_soc_clock_bw_request { + uint64_t clock_rate; + uint64_t bandwidth; + uint64_t reserved[4]; +}; + +/** + * struct cam_fd_face - Face properties + * + * @prop1 : Property 1 of face + * @prop2 : Property 2 of face + * @prop3 : Property 3 of face + * @prop4 : Property 4 of face + * + * Do not change this layout, this is inline with how HW writes + * these values directly when the buffer is programmed to HW + */ +struct cam_fd_face { + uint32_t prop1; + uint32_t prop2; + uint32_t prop3; + uint32_t prop4; +}; + +/** + * struct cam_fd_results - FD results layout + * + * @faces : Array of faces with face properties + * @face_count : Number of faces detected + * @reserved : Reserved for alignment + * + * Do not change this layout, this is inline with how HW writes + * these values directly when the buffer is programmed to HW + */ +struct cam_fd_results { + struct cam_fd_face faces[CAM_FD_MAX_FACES]; + uint32_t face_count; + uint32_t reserved[3]; +}; + +/** + * struct cam_fd_hw_caps - Face properties + * + * @core_version : FD core version + * @wrapper_version : FD wrapper version + * @raw_results_available : Whether raw results are available on this HW + * @supported_modes : Modes supported by this HW. + * @reserved : Reserved for future use + */ +struct cam_fd_hw_caps { + struct cam_hw_version core_version; + struct cam_hw_version wrapper_version; + uint32_t raw_results_available; + uint32_t supported_modes; + uint64_t reserved; +}; + +/** + * struct cam_fd_query_cap_cmd - FD Query capabilities information + * + * @device_iommu : FD IOMMU handles + * @cdm_iommu : CDM iommu handles + * @hw_caps : FD HW capabilities + * @reserved : Reserved for alignment + */ +struct cam_fd_query_cap_cmd { + struct cam_iommu_handle device_iommu; + struct cam_iommu_handle cdm_iommu; + struct cam_fd_hw_caps hw_caps; + uint64_t reserved; +}; + +/** + * struct cam_fd_acquire_dev_info - FD acquire device information + * + * @clk_bw_request : SOC clock, bandwidth request + * @priority : Priority for this acquire + * @mode : Mode in which to run FD HW. + * @get_raw_results : Whether this acquire needs face raw results + * while frame processing + * @reserved : Reserved field for 64 bit alignment + */ +struct cam_fd_acquire_dev_info { + struct cam_fd_soc_clock_bw_request clk_bw_request; + uint32_t priority; + uint32_t mode; + uint32_t get_raw_results; + uint32_t reserved[13]; +}; + +#endif /* __UAPI_CAM_FD_H__ */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_icp.h b/techpack/camera-bengal/include/uapi/media/cam_icp.h new file mode 100644 index 0000000000000000000000000000000000000000..4b5419d2f21de1c12ce86ba52e74b875430adf42 --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_icp.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_ICP_H__ +#define __UAPI_CAM_ICP_H__ + +#include +#include + +/* icp, ipe, bps, cdm(ipe/bps) are used in querycap */ +#define CAM_ICP_DEV_TYPE_A5 1 +#define CAM_ICP_DEV_TYPE_IPE 2 +#define CAM_ICP_DEV_TYPE_BPS 3 +#define CAM_ICP_DEV_TYPE_IPE_CDM 4 +#define CAM_ICP_DEV_TYPE_BPS_CDM 5 +#define CAM_ICP_DEV_TYPE_MAX 5 + +/* definitions needed for icp aquire device */ +#define CAM_ICP_RES_TYPE_BPS 1 +#define CAM_ICP_RES_TYPE_IPE_RT 2 +#define CAM_ICP_RES_TYPE_IPE 3 +#define CAM_ICP_RES_TYPE_IPE_SEMI_RT 4 +#define CAM_ICP_RES_TYPE_BPS_RT 5 +#define CAM_ICP_RES_TYPE_BPS_SEMI_RT 6 +#define CAM_ICP_RES_TYPE_MAX 7 + +/* packet opcode types */ +#define CAM_ICP_OPCODE_IPE_UPDATE 0 +#define CAM_ICP_OPCODE_BPS_UPDATE 1 +#define CAM_ICP_OPCODE_IPE_SETTINGS 2 +#define CAM_ICP_OPCODE_BPS_SETTINGS 3 + + +/* IPE input port resource type */ +#define CAM_ICP_IPE_INPUT_IMAGE_FULL 0x0 +#define CAM_ICP_IPE_INPUT_IMAGE_DS4 0x1 +#define CAM_ICP_IPE_INPUT_IMAGE_DS16 0x2 +#define CAM_ICP_IPE_INPUT_IMAGE_DS64 0x3 +#define CAM_ICP_IPE_INPUT_IMAGE_FULL_REF 0x4 +#define CAM_ICP_IPE_INPUT_IMAGE_DS4_REF 0x5 +#define CAM_ICP_IPE_INPUT_IMAGE_DS16_REF 0x6 +#define CAM_ICP_IPE_INPUT_IMAGE_DS64_REF 0x7 + +/* IPE output port resource type */ +#define CAM_ICP_IPE_OUTPUT_IMAGE_DISPLAY 0x8 +#define CAM_ICP_IPE_OUTPUT_IMAGE_VIDEO 0x9 +#define CAM_ICP_IPE_OUTPUT_IMAGE_FULL_REF 0xA +#define CAM_ICP_IPE_OUTPUT_IMAGE_DS4_REF 0xB +#define CAM_ICP_IPE_OUTPUT_IMAGE_DS16_REF 0xC +#define CAM_ICP_IPE_OUTPUT_IMAGE_DS64_REF 0xD + +#define CAM_ICP_IPE_IMAGE_MAX 0xE + +/* BPS input port resource type */ +#define CAM_ICP_BPS_INPUT_IMAGE 0x0 + +/* BPS output port resource type */ +#define CAM_ICP_BPS_OUTPUT_IMAGE_FULL 0x1 +#define CAM_ICP_BPS_OUTPUT_IMAGE_DS4 0x2 +#define CAM_ICP_BPS_OUTPUT_IMAGE_DS16 0x3 +#define CAM_ICP_BPS_OUTPUT_IMAGE_DS64 0x4 +#define CAM_ICP_BPS_OUTPUT_IMAGE_STATS_BG 0x5 +#define CAM_ICP_BPS_OUTPUT_IMAGE_STATS_BHIST 0x6 +#define CAM_ICP_BPS_OUTPUT_IMAGE_REG1 0x7 +#define CAM_ICP_BPS_OUTPUT_IMAGE_REG2 0x8 + +#define CAM_ICP_BPS_IO_IMAGES_MAX 0x9 + +/* Command meta types */ +#define CAM_ICP_CMD_META_GENERIC_BLOB 0x1 + +/* Generic blob types */ +#define CAM_ICP_CMD_GENERIC_BLOB_CLK 0x1 +#define CAM_ICP_CMD_GENERIC_BLOB_CFG_IO 0x2 +#define CAM_ICP_CMD_GENERIC_BLOB_FW_MEM_MAP 0x3 +#define CAM_ICP_CMD_GENERIC_BLOB_FW_MEM_UNMAP 0x4 +#define CAM_ICP_CMD_GENERIC_BLOB_CLK_V2 0x5 + +/** + * struct cam_icp_clk_bw_request_v2 + * + * @budget_ns: Time required to process frame + * @frame_cycles: Frame cycles needed to process the frame + * @rt_flag: Flag to indicate real time stream + * @reserved: For memory alignment + * @num_paths: Number of axi paths in bw request + * @axi_path: Per path vote info for IPE/BPS + */ +struct cam_icp_clk_bw_request_v2 { + uint64_t budget_ns; + uint32_t frame_cycles; + uint32_t rt_flag; + uint32_t reserved; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[1]; +}; + +/** + * struct cam_icp_clk_bw_request + * + * @budget_ns: Time required to process frame + * @frame_cycles: Frame cycles needed to process the frame + * @rt_flag: Flag to indicate real time stream + * @uncompressed_bw: Bandwidth required to process frame + * @compressed_bw: Compressed bandwidth to process frame + */ +struct cam_icp_clk_bw_request { + uint64_t budget_ns; + uint32_t frame_cycles; + uint32_t rt_flag; + uint64_t uncompressed_bw; + uint64_t compressed_bw; +}; + +/** + * struct cam_icp_dev_ver - Device information for particular hw type + * + * This is used to get device version info of + * ICP, IPE, BPS and CDM related IPE and BPS from firmware + * and use this info in CAM_QUERY_CAP IOCTL + * + * @dev_type: hardware type for the cap info(icp, ipe, bps, cdm(ipe/bps)) + * @reserved: reserved field + * @hw_ver: major, minor and incr values of a device version + */ +struct cam_icp_dev_ver { + uint32_t dev_type; + uint32_t reserved; + struct cam_hw_version hw_ver; +}; + +/** + * struct cam_icp_ver - ICP version info + * + * This strcuture is used for fw and api version + * this is used to get firmware version and api version from firmware + * and use this info in CAM_QUERY_CAP IOCTL + * + * @major: FW version major + * @minor: FW version minor + * @revision: FW version increment + */ +struct cam_icp_ver { + uint32_t major; + uint32_t minor; + uint32_t revision; + uint32_t reserved; +}; + +/** + * struct cam_icp_query_cap_cmd - ICP query device capability payload + * + * @dev_iommu_handle: icp iommu handles for secure/non secure modes + * @cdm_iommu_handle: iommu handles for secure/non secure modes + * @fw_version: firmware version info + * @api_version: api version info + * @num_ipe: number of ipes + * @num_bps: number of bps + * @dev_ver: returned device capability array + */ +struct cam_icp_query_cap_cmd { + struct cam_iommu_handle dev_iommu_handle; + struct cam_iommu_handle cdm_iommu_handle; + struct cam_icp_ver fw_version; + struct cam_icp_ver api_version; + uint32_t num_ipe; + uint32_t num_bps; + struct cam_icp_dev_ver dev_ver[CAM_ICP_DEV_TYPE_MAX]; +}; + +/** + * struct cam_icp_res_info - ICP output resource info + * + * @format: format of the resource + * @width: width in pixels + * @height: height in lines + * @fps: fps + */ +struct cam_icp_res_info { + uint32_t format; + uint32_t width; + uint32_t height; + uint32_t fps; +}; + +/** + * struct cam_icp_acquire_dev_info - An ICP device info + * + * @scratch_mem_size: Output param - size of scratch memory + * @dev_type: device type (IPE_RT/IPE_NON_RT/BPS) + * @io_config_cmd_size: size of IO config command + * @io_config_cmd_handle: IO config command for each acquire + * @secure_mode: camera mode (secure/non secure) + * @chain_info: chaining info of FW device handles + * @in_res: resource info used for clock and bandwidth calculation + * @num_out_res: number of output resources + * @out_res: output resource + */ +struct cam_icp_acquire_dev_info { + uint32_t scratch_mem_size; + uint32_t dev_type; + uint32_t io_config_cmd_size; + int32_t io_config_cmd_handle; + uint32_t secure_mode; + int32_t chain_info; + struct cam_icp_res_info in_res; + uint32_t num_out_res; + struct cam_icp_res_info out_res[1]; +} __attribute__((__packed__)); + +#endif /* __UAPI_CAM_ICP_H__ */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_isp.h b/techpack/camera-bengal/include/uapi/media/cam_isp.h new file mode 100644 index 0000000000000000000000000000000000000000..e4778cfc9cc2fe797e45bb8eb6348732f73155e5 --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_isp.h @@ -0,0 +1,711 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_ISP_H__ +#define __UAPI_CAM_ISP_H__ + +#include +#include +#include +#include + +/* ISP driver name */ +#define CAM_ISP_DEV_NAME "cam-isp" + +/* HW type */ +#define CAM_ISP_HW_BASE 0 +#define CAM_ISP_HW_CSID 1 +#define CAM_ISP_HW_VFE 2 +#define CAM_ISP_HW_IFE 3 +#define CAM_ISP_HW_ISPIF 4 +#define CAM_ISP_HW_MAX 5 + +/* Color Pattern */ +#define CAM_ISP_PATTERN_BAYER_RGRGRG 0 +#define CAM_ISP_PATTERN_BAYER_GRGRGR 1 +#define CAM_ISP_PATTERN_BAYER_BGBGBG 2 +#define CAM_ISP_PATTERN_BAYER_GBGBGB 3 +#define CAM_ISP_PATTERN_YUV_YCBYCR 4 +#define CAM_ISP_PATTERN_YUV_YCRYCB 5 +#define CAM_ISP_PATTERN_YUV_CBYCRY 6 +#define CAM_ISP_PATTERN_YUV_CRYCBY 7 +#define CAM_ISP_PATTERN_MAX 8 + +/* Usage Type */ +#define CAM_ISP_RES_USAGE_SINGLE 0 +#define CAM_ISP_RES_USAGE_DUAL 1 +#define CAM_ISP_RES_USAGE_MAX 2 + +/* Resource ID */ +#define CAM_ISP_RES_ID_PORT 0 +#define CAM_ISP_RES_ID_CLK 1 +#define CAM_ISP_RES_ID_MAX 2 + +/* Resource Type - Type of resource for the resource id + * defined in cam_isp_vfe.h, cam_isp_ife.h + */ + +/* Lane Type in input resource for Port */ +#define CAM_ISP_LANE_TYPE_DPHY 0 +#define CAM_ISP_LANE_TYPE_CPHY 1 +#define CAM_ISP_LANE_TYPE_MAX 2 + +/* ISP Resurce Composite Group ID */ +#define CAM_ISP_RES_COMP_GROUP_NONE 0 +#define CAM_ISP_RES_COMP_GROUP_ID_0 1 +#define CAM_ISP_RES_COMP_GROUP_ID_1 2 +#define CAM_ISP_RES_COMP_GROUP_ID_2 3 +#define CAM_ISP_RES_COMP_GROUP_ID_3 4 +#define CAM_ISP_RES_COMP_GROUP_ID_4 5 +#define CAM_ISP_RES_COMP_GROUP_ID_5 6 +#define CAM_ISP_RES_COMP_GROUP_ID_MAX 6 + +/* ISP packet opcode for ISP */ +#define CAM_ISP_PACKET_OP_BASE 0 +#define CAM_ISP_PACKET_INIT_DEV 1 +#define CAM_ISP_PACKET_UPDATE_DEV 2 +#define CAM_ISP_PACKET_OP_MAX 3 + +/* ISP packet meta_data type for command buffer */ +#define CAM_ISP_PACKET_META_BASE 0 +#define CAM_ISP_PACKET_META_LEFT 1 +#define CAM_ISP_PACKET_META_RIGHT 2 +#define CAM_ISP_PACKET_META_COMMON 3 +#define CAM_ISP_PACKET_META_DMI_LEFT 4 +#define CAM_ISP_PACKET_META_DMI_RIGHT 5 +#define CAM_ISP_PACKET_META_DMI_COMMON 6 +#define CAM_ISP_PACKET_META_CLOCK 7 +#define CAM_ISP_PACKET_META_CSID 8 +#define CAM_ISP_PACKET_META_DUAL_CONFIG 9 +#define CAM_ISP_PACKET_META_GENERIC_BLOB_LEFT 10 +#define CAM_ISP_PACKET_META_GENERIC_BLOB_RIGHT 11 +#define CAM_ISP_PACKET_META_GENERIC_BLOB_COMMON 12 +#define CAM_ISP_PACKET_META_REG_DUMP_PER_REQUEST 13 +#define CAM_ISP_PACKET_META_REG_DUMP_ON_FLUSH 14 +#define CAM_ISP_PACKET_META_REG_DUMP_ON_ERROR 15 + +/* DSP mode */ +#define CAM_ISP_DSP_MODE_NONE 0 +#define CAM_ISP_DSP_MODE_ONE_WAY 1 +#define CAM_ISP_DSP_MODE_ROUND 2 + +/* ISP Generic Cmd Buffer Blob types */ +#define CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG 0 +#define CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1 +#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG 2 +#define CAM_ISP_GENERIC_BLOB_TYPE_UBWC_CONFIG 3 +#define CAM_ISP_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG 4 +#define CAM_ISP_GENERIC_BLOB_TYPE_FE_CONFIG 5 +#define CAM_ISP_GENERIC_BLOB_TYPE_UBWC_CONFIG_V2 6 +#define CAM_ISP_GENERIC_BLOB_TYPE_IFE_CORE_CONFIG 7 +#define CAM_ISP_GENERIC_BLOB_TYPE_VFE_OUT_CONFIG 8 +#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG_V2 9 +#define CAM_ISP_GENERIC_BLOB_TYPE_CSID_QCFA_CONFIG 12 + +#define CAM_ISP_VC_DT_CFG 4 + +#define CAM_ISP_IFE0_HW 0x1 +#define CAM_ISP_IFE1_HW 0x2 +#define CAM_ISP_IFE0_LITE_HW 0x4 +#define CAM_ISP_IFE1_LITE_HW 0x8 +#define CAM_ISP_IFE2_LITE_HW 0x10 + +#define CAM_ISP_PXL_PATH 0x1 +#define CAM_ISP_PPP_PATH 0x2 +#define CAM_ISP_LCR_PATH 0x4 +#define CAM_ISP_RDI0_PATH 0x8 +#define CAM_ISP_RDI1_PATH 0x10 +#define CAM_ISP_RDI2_PATH 0x20 +#define CAM_ISP_RDI3_PATH 0x40 + +/* Per Path Usage Data */ +#define CAM_ISP_USAGE_INVALID 0 +#define CAM_ISP_USAGE_LEFT_PX 1 +#define CAM_ISP_USAGE_RIGHT_PX 2 +#define CAM_ISP_USAGE_RDI 3 + +/* Acquire with custom hw */ +#define CAM_ISP_ACQ_CUSTOM_NONE 0 +#define CAM_ISP_ACQ_CUSTOM_PRIMARY 1 +#define CAM_ISP_ACQ_CUSTOM_SECONDARY 2 + +/* Query devices */ +/** + * struct cam_isp_dev_cap_info - A cap info for particular hw type + * + * @hw_type: Hardware type for the cap info + * @reserved: reserved field for alignment + * @hw_version: Hardware version + * + */ +struct cam_isp_dev_cap_info { + uint32_t hw_type; + uint32_t reserved; + struct cam_hw_version hw_version; +}; + +/** + * struct cam_isp_query_cap_cmd - ISP query device capability payload + * + * @device_iommu: returned iommu handles for device + * @cdm_iommu: returned iommu handles for cdm + * @num_dev: returned number of device capabilities + * @reserved: reserved field for alignment + * @dev_caps: returned device capability array + * + */ +struct cam_isp_query_cap_cmd { + struct cam_iommu_handle device_iommu; + struct cam_iommu_handle cdm_iommu; + int32_t num_dev; + uint32_t reserved; + struct cam_isp_dev_cap_info dev_caps[CAM_ISP_HW_MAX]; +}; + +/* Acquire Device */ +/** + * struct cam_isp_out_port_info - An output port resource info + * + * @res_type: output resource type defined in file + * cam_isp_vfe.h or cam_isp_ife.h + * @format: output format of the resource + * @wdith: output width in pixels + * @height: output height in lines + * @comp_grp_id: composite group id for the resource. + * @split_point: split point in pixels for the dual VFE. + * @secure_mode: flag to tell if output should be run in secure + * mode or not. See cam_defs.h for definition + * @reserved: reserved field for alignment + * + */ +struct cam_isp_out_port_info { + uint32_t res_type; + uint32_t format; + uint32_t width; + uint32_t height; + uint32_t comp_grp_id; + uint32_t split_point; + uint32_t secure_mode; + uint32_t reserved; +}; + +/** + * struct cam_isp_out_port_info_v2 - An output port resource info + * + * @res_type: output resource type defined in file + * cam_isp_vfe.h or cam_isp_ife.h + * @format: output format of the resource + * @wdith: output width in pixels + * @height: output height in lines + * @comp_grp_id: composite group id for the resource. + * @split_point: split point in pixels for the dual VFE. + * @secure_mode: flag to tell if output should be run in secure + * mode or not. See cam_defs.h for definition + * @wm_mode: WM mode + * @out_port_res1: Output reserved field + * @out_port_res2: Output reserved field + * + */ +struct cam_isp_out_port_info_v2 { + uint32_t res_type; + uint32_t format; + uint32_t width; + uint32_t height; + uint32_t comp_grp_id; + uint32_t split_point; + uint32_t secure_mode; + uint32_t wm_mode; + uint32_t out_port_res1; + uint32_t out_port_res2; +}; + +/** + * struct cam_isp_in_port_info - An input port resource info + * + * @res_type: input resource type define in file + * cam_isp_vfe.h or cam_isp_ife.h + * @lane_type: lane type: c-phy or d-phy. + * @lane_num: active lane number + * @lane_cfg: lane configurations: 4 bits per lane + * @vc: input virtual channel number + * @dt: input data type number + * @format: input format + * @test_pattern: test pattern for the testgen + * @usage_type: whether dual vfe is required + * @left_start: left input start offset in pixels + * @left_stop: left input stop offset in pixels + * @left_width: left input width in pixels + * @right_start: right input start offset in pixels. + * Only for Dual VFE + * @right_stop: right input stop offset in pixels. + * Only for Dual VFE + * @right_width: right input width in pixels. + * Only for dual VFE + * @line_start: top of the line number + * @line_stop: bottome of the line number + * @height: input height in lines + * @pixel_clk; sensor output clock + * @batch_size: batch size for HFR mode + * @dsp_mode: DSP stream mode (Defines as CAM_ISP_DSP_MODE_*) + * @hbi_cnt: HBI count for the camif input + * @reserved: Reserved field for alignment + * @num_out_res: number of the output resource associated + * @data: payload that contains the output resources + * + */ +struct cam_isp_in_port_info { + uint32_t res_type; + uint32_t lane_type; + uint32_t lane_num; + uint32_t lane_cfg; + uint32_t vc; + uint32_t dt; + uint32_t format; + uint32_t test_pattern; + uint32_t usage_type; + uint32_t left_start; + uint32_t left_stop; + uint32_t left_width; + uint32_t right_start; + uint32_t right_stop; + uint32_t right_width; + uint32_t line_start; + uint32_t line_stop; + uint32_t height; + uint32_t pixel_clk; + uint32_t batch_size; + uint32_t dsp_mode; + uint32_t hbi_cnt; + uint32_t reserved; + uint32_t num_out_res; + struct cam_isp_out_port_info data[1]; +}; + +/** + * struct cam_isp_in_port_info_v2 - An input port resource info + * + * @res_type: input resource type define in file + * cam_isp_vfe.h or cam_isp_ife.h + * @lane_type: lane type: c-phy or d-phy. + * @lane_num: active lane number + * @lane_cfg: lane configurations: 4 bits per lane + * @vc: input virtual channel number + * @dt: input data type number + * @num_valid_vc_dt: valid vc and dt in array + * @format: input format + * @test_pattern: test pattern for the testgen + * @usage_type: whether dual vfe is required + * @left_start: left input start offset in pixels + * @left_stop: left input stop offset in pixels + * @left_width: left input width in pixels + * @right_start: right input start offset in pixels. + * Only for Dual VFE + * @right_stop: right input stop offset in pixels. + * only for Dual VFE + * @right_width: right input width in pixels. + * only for dual VFE + * @line_start: top of the line number + * @line_stop: bottome of the line number + * @height: input height in lines + * @pixel_clk; sensor output clock + * @batch_size: batch size for HFR mode + * @dsp_mode: DSP stream mode (Defines as CAM_ISP_DSP_MODE_*) + * @hbi_cnt: HBI count for the camif input + * @cust_node: if any custom HW block is present before IFE + * @num_out_res: number of the output resource associated + * @horizontal_bin: Horizontal Binning info + * @qcfa_bin: Quadra Binning info + * @csid_res_1: payload for future use + * @csid_res_2: payload for future use + * @ife_res_1: payload for future use + * @ife_res_2: payload for future use + * @data: payload that contains the output resources + * + */ +struct cam_isp_in_port_info_v2 { + uint32_t res_type; + uint32_t lane_type; + uint32_t lane_num; + uint32_t lane_cfg; + uint32_t vc[CAM_ISP_VC_DT_CFG]; + uint32_t dt[CAM_ISP_VC_DT_CFG]; + uint32_t num_valid_vc_dt; + uint32_t format; + uint32_t test_pattern; + uint32_t usage_type; + uint32_t left_start; + uint32_t left_stop; + uint32_t left_width; + uint32_t right_start; + uint32_t right_stop; + uint32_t right_width; + uint32_t line_start; + uint32_t line_stop; + uint32_t height; + uint32_t pixel_clk; + uint32_t batch_size; + uint32_t dsp_mode; + uint32_t hbi_cnt; + uint32_t cust_node; + uint32_t num_out_res; + uint32_t offline_mode; + uint32_t horizontal_bin; + uint32_t qcfa_bin; + uint32_t csid_res_1; + uint32_t csid_res_2; + uint32_t ife_res_1; + uint32_t ife_res_2; + struct cam_isp_out_port_info_v2 data[1]; +}; + +/** + * struct cam_isp_resource - A resource bundle + * + * @resoruce_id: resource id for the resource bundle + * @length: length of the while resource blob + * @handle_type: type of the resource handle + * @reserved: reserved field for alignment + * @res_hdl: resource handle that points to the + * resource array; + * + */ +struct cam_isp_resource { + uint32_t resource_id; + uint32_t length; + uint32_t handle_type; + uint32_t reserved; + uint64_t res_hdl; +}; + +/** + * struct cam_isp_port_hfr_config - HFR configuration for this port + * + * @resource_type: Resource type + * @subsample_pattern: Subsample pattern. Used in HFR mode. It + * should be consistent with batchSize and + * CAMIF programming. + * @subsample_period: Subsample period. Used in HFR mode. It + * should be consistent with batchSize and + * CAMIF programming. + * @framedrop_pattern: Framedrop pattern + * @framedrop_period: Framedrop period + * @reserved: Reserved for alignment + */ +struct cam_isp_port_hfr_config { + uint32_t resource_type; + uint32_t subsample_pattern; + uint32_t subsample_period; + uint32_t framedrop_pattern; + uint32_t framedrop_period; + uint32_t reserved; +} __attribute__((packed)); + +/** + * struct cam_isp_resource_hfr_config - Resource HFR configuration + * + * @num_ports: Number of ports + * @reserved: Reserved for alignment + * @port_hfr_config: HFR configuration for each IO port + */ +struct cam_isp_resource_hfr_config { + uint32_t num_ports; + uint32_t reserved; + struct cam_isp_port_hfr_config port_hfr_config[1]; +} __attribute__((packed)); + +/** + * struct cam_isp_dual_split_params - dual isp spilt parameters + * + * @split_point: Split point information x, where (0 < x < width) + * left ISP's input ends at x + righ padding and + * Right ISP's input starts at x - left padding + * @right_padding: Padding added past the split point for left + * ISP's input + * @left_padding: Padding added before split point for right + * ISP's input + * @reserved: Reserved filed for alignment + * + */ +struct cam_isp_dual_split_params { + uint32_t split_point; + uint32_t right_padding; + uint32_t left_padding; + uint32_t reserved; +}; + +/** + * struct cam_isp_dual_stripe_config - stripe config per bus client + * + * @offset: Start horizontal offset relative to + * output buffer + * In UBWC mode, this value indicates the H_INIT + * value in pixel + * @width: Width of the stripe in bytes + * @tileconfig Ubwc meta tile config. Contain the partial + * tile info + * @port_id: port id of ISP output + * + */ +struct cam_isp_dual_stripe_config { + uint32_t offset; + uint32_t width; + uint32_t tileconfig; + uint32_t port_id; +}; + +/** + * struct cam_isp_dual_config - dual isp configuration + * + * @num_ports Number of isp output ports + * @reserved Reserved field for alignment + * @split_params: Inpput split parameters + * @stripes: Stripe information + * + */ +struct cam_isp_dual_config { + uint32_t num_ports; + uint32_t reserved; + struct cam_isp_dual_split_params split_params; + struct cam_isp_dual_stripe_config stripes[1]; +} __attribute__((packed)); + +/** + * struct cam_isp_clock_config - Clock configuration + * + * @usage_type: Usage type (Single/Dual) + * @num_rdi: Number of RDI votes + * @left_pix_hz: Pixel Clock for Left ISP + * @right_pix_hz: Pixel Clock for Right ISP, valid only if Dual + * @rdi_hz: RDI Clock. ISP clock will be max of RDI and + * PIX clocks. For a particular context which ISP + * HW the RDI is allocated to is not known to UMD. + * Hence pass the clock and let KMD decide. + */ +struct cam_isp_clock_config { + uint32_t usage_type; + uint32_t num_rdi; + uint64_t left_pix_hz; + uint64_t right_pix_hz; + uint64_t rdi_hz[1]; +} __attribute__((packed)); + +/** + * struct cam_isp_csid_clock_config - CSID clock configuration + * + * @csid_clock CSID clock + */ +struct cam_isp_csid_clock_config { + uint64_t csid_clock; +} __attribute__((packed)); + +/** + * struct cam_isp_csid_qcfa_config - CSID qcfa binning support configuration + * + * @csid_binning CSID binning + */ +struct cam_isp_csid_qcfa_config { + uint32_t csid_binning; +} __attribute__((packed)); + +/** + * struct cam_isp_bw_vote - Bandwidth vote information + * + * @resource_id: Resource ID + * @reserved: Reserved field for alignment + * @cam_bw_bps: Bandwidth vote for CAMNOC + * @ext_bw_bps: Bandwidth vote for path-to-DDR after CAMNOC + */ +struct cam_isp_bw_vote { + uint32_t resource_id; + uint32_t reserved; + uint64_t cam_bw_bps; + uint64_t ext_bw_bps; +} __attribute__((packed)); + +/** + * struct cam_isp_bw_config - Bandwidth configuration + * + * @usage_type: Usage type (Single/Dual) + * @num_rdi: Number of RDI votes + * @left_pix_vote: Bandwidth vote for left ISP + * @right_pix_vote: Bandwidth vote for right ISP + * @rdi_vote: RDI bandwidth requirements + */ +struct cam_isp_bw_config { + uint32_t usage_type; + uint32_t num_rdi; + struct cam_isp_bw_vote left_pix_vote; + struct cam_isp_bw_vote right_pix_vote; + struct cam_isp_bw_vote rdi_vote[1]; +} __attribute__((packed)); + +/** + * struct cam_isp_bw_config_v2 - Bandwidth configuration + * + * @usage_type: Usage type (Single/Dual) + * @num_paths: Number of axi data paths + * @axi_path Per path vote info + */ +struct cam_isp_bw_config_v2 { + uint32_t usage_type; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[1]; +} __attribute__((packed)); + +/** + * struct cam_fe_config - Fetch Engine configuration + * + * @version: fetch engine veriosn + * @min_vbi: require min vbi + * @fs_mode: indicates if fs mode enabled + * @fs_line_sync_en: frame level sync or line level + * sync for fetch engine + * @hbi_count: hbi count + * @fs_sync_enable: indicates if fetch engine working + * wokring in sync with write engine + * @go_cmd_sel: softwrae go_cmd or hw go_cmd + * @client_enable: enable read engine + * @source_addr: adrress of buffer to read from + * @width: buffer width + * @height: buffer height + * @stride: buffer stride (here equal to width) + * @format: format of image in buffer + * @unpacker_cfg: unpacker config type + * @latency_buf_size: latency buffer for read engine + */ +struct cam_fe_config { + uint64_t version; + uint32_t min_vbi; + uint32_t fs_mode; + uint32_t fs_line_sync_en; + uint32_t hbi_count; + uint32_t fs_sync_enable; + uint32_t go_cmd_sel; + uint32_t client_enable; + uint32_t source_addr; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t format; + uint32_t unpacker_cfg; + uint32_t latency_buf_size; +} __attribute__((packed)); + +/** + * struct cam_isp_core_config - ISP core registers configuration + * + * @version: Version info + * @vid_ds16_r2pd: Enables Y and C merging PD output for video DS16 + * @vid_ds4_r2pd: Enables Y and C merging PD output for video DS4 + * @disp_ds16_r2pd: Enables Y and C merging PD output for disp DS16 + * @disp_ds4_r2pd: Enables Y and C merging PD output for disp DS4 + * @dsp_streaming_tap_point: This selects source for DSP streaming interface + * @ihist_src_sel: Selects input for IHIST module + * @hdr_be_src_sel: Selects input for HDR BE module + * @hdr_bhist_src_sel: Selects input for HDR BHIST module + * @input_mux_sel_pdaf: Selects input for PDAF + * @input_mux_sel_pp: Selects input for Pixel Pipe + * @reserved: Reserved + */ +struct cam_isp_core_config { + uint32_t version; + uint32_t vid_ds16_r2pd; + uint32_t vid_ds4_r2pd; + uint32_t disp_ds16_r2pd; + uint32_t disp_ds4_r2pd; + uint32_t dsp_streaming_tap_point; + uint32_t ihist_src_sel; + uint32_t hdr_be_src_sel; + uint32_t hdr_bhist_src_sel; + uint32_t input_mux_sel_pdaf; + uint32_t input_mux_sel_pp; + uint32_t reserved; +} __attribute__((packed)); + +/** + * struct cam_isp_acquire_hw_info - ISP acquire HW params + * + * @common_info_version : Version of common info struct used + * @common_info_size : Size of common info struct used + * @common_info_offset : Offset of common info from start of data + * @num_inputs : Number of inputs + * @input_info_version : Version of input info struct used + * @input_info_size : Size of input info struct used + * @input_info_offset : Offset of input info from start of data + * @data : Start of data region + */ +struct cam_isp_acquire_hw_info { + uint16_t common_info_version; + uint16_t common_info_size; + uint32_t common_info_offset; + uint32_t num_inputs; + uint32_t input_info_version; + uint32_t input_info_size; + uint32_t input_info_offset; + uint64_t data; +}; + +/** + * struct cam_isp_vfe_wm_config - VFE write master config per port + * + * @port_type : Unique ID of output port + * @wm_mode : Write master mode + * 0x0 - Line based mode + * 0x1 - Frame based mode + * 0x2 - Index based mode, valid for BAF only + * @h_init : Horizontal starting coordinate in pixels. Must be a + * multiple of 3 for TP10 format + * @height : Height in pixels + * @width : Width in pixels + * @virtual_frame_en : Enabling virtual frame will prevent actual request from + * being sent to NOC + * @stride : Write master stride + * @offset : Write master offset + * @reserved_1 : Reserved field for Write master config + * @reserved_2 : Reserved field for Write master config + * @reserved_3 : Reserved field for Write master config + * @reserved_4 : Reserved field for Write master config + */ +struct cam_isp_vfe_wm_config { + uint32_t port_type; + uint32_t wm_mode; + uint32_t h_init; + uint32_t height; + uint32_t width; + uint32_t virtual_frame_en; + uint32_t stride; + uint32_t offset; + uint32_t reserved_1; + uint32_t reserved_2; + uint32_t reserved_3; + uint32_t reserved_4; +}; + +/** + * struct cam_isp_vfe_out_config - VFE write master config + * + * @num_ports : Number of ports + * @reserved : Reserved field + * @wm_config : VFE out config + */ +struct cam_isp_vfe_out_config { + uint32_t num_ports; + uint32_t reserved; + struct cam_isp_vfe_wm_config wm_config[1]; +}; + +#define CAM_ISP_ACQUIRE_COMMON_VER0 0x1000 + +#define CAM_ISP_ACQUIRE_COMMON_SIZE_VER0 0x0 + +#define CAM_ISP_ACQUIRE_INPUT_VER0 0x2000 + +#define CAM_ISP_ACQUIRE_INPUT_SIZE_VER0 sizeof(struct cam_isp_in_port_info) + +#define CAM_ISP_ACQUIRE_OUT_VER0 0x3000 + +#define CAM_ISP_ACQUIRE_OUT_SIZE_VER0 sizeof(struct cam_isp_out_port_info) + +#endif /* __UAPI_CAM_ISP_H__ */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_isp_ife.h b/techpack/camera-bengal/include/uapi/media/cam_isp_ife.h new file mode 100644 index 0000000000000000000000000000000000000000..34c1b3bd2bfe5ec6bec97a5c50fca78864085d7f --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_isp_ife.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_ISP_IFE_H__ +#define __UAPI_CAM_ISP_IFE_H__ + +/* IFE output port resource type (global unique)*/ +#define CAM_ISP_IFE_OUT_RES_BASE 0x3000 + +#define CAM_ISP_IFE_OUT_RES_FULL (CAM_ISP_IFE_OUT_RES_BASE + 0) +#define CAM_ISP_IFE_OUT_RES_DS4 (CAM_ISP_IFE_OUT_RES_BASE + 1) +#define CAM_ISP_IFE_OUT_RES_DS16 (CAM_ISP_IFE_OUT_RES_BASE + 2) +#define CAM_ISP_IFE_OUT_RES_RAW_DUMP (CAM_ISP_IFE_OUT_RES_BASE + 3) +#define CAM_ISP_IFE_OUT_RES_FD (CAM_ISP_IFE_OUT_RES_BASE + 4) +#define CAM_ISP_IFE_OUT_RES_PDAF (CAM_ISP_IFE_OUT_RES_BASE + 5) +#define CAM_ISP_IFE_OUT_RES_RDI_0 (CAM_ISP_IFE_OUT_RES_BASE + 6) +#define CAM_ISP_IFE_OUT_RES_RDI_1 (CAM_ISP_IFE_OUT_RES_BASE + 7) +#define CAM_ISP_IFE_OUT_RES_RDI_2 (CAM_ISP_IFE_OUT_RES_BASE + 8) +#define CAM_ISP_IFE_OUT_RES_RDI_3 (CAM_ISP_IFE_OUT_RES_BASE + 9) +#define CAM_ISP_IFE_OUT_RES_STATS_HDR_BE (CAM_ISP_IFE_OUT_RES_BASE + 10) +#define CAM_ISP_IFE_OUT_RES_STATS_HDR_BHIST (CAM_ISP_IFE_OUT_RES_BASE + 11) +#define CAM_ISP_IFE_OUT_RES_STATS_TL_BG (CAM_ISP_IFE_OUT_RES_BASE + 12) +#define CAM_ISP_IFE_OUT_RES_STATS_BF (CAM_ISP_IFE_OUT_RES_BASE + 13) +#define CAM_ISP_IFE_OUT_RES_STATS_AWB_BG (CAM_ISP_IFE_OUT_RES_BASE + 14) +#define CAM_ISP_IFE_OUT_RES_STATS_BHIST (CAM_ISP_IFE_OUT_RES_BASE + 15) +#define CAM_ISP_IFE_OUT_RES_STATS_RS (CAM_ISP_IFE_OUT_RES_BASE + 16) +#define CAM_ISP_IFE_OUT_RES_STATS_CS (CAM_ISP_IFE_OUT_RES_BASE + 17) +#define CAM_ISP_IFE_OUT_RES_STATS_IHIST (CAM_ISP_IFE_OUT_RES_BASE + 18) +#define CAM_ISP_IFE_OUT_RES_FULL_DISP (CAM_ISP_IFE_OUT_RES_BASE + 19) +#define CAM_ISP_IFE_OUT_RES_DS4_DISP (CAM_ISP_IFE_OUT_RES_BASE + 20) +#define CAM_ISP_IFE_OUT_RES_DS16_DISP (CAM_ISP_IFE_OUT_RES_BASE + 21) +#define CAM_ISP_IFE_OUT_RES_2PD (CAM_ISP_IFE_OUT_RES_BASE + 22) +#define CAM_ISP_IFE_OUT_RES_RDI_RD (CAM_ISP_IFE_OUT_RES_BASE + 23) +#define CAM_ISP_IFE_OUT_RES_LCR (CAM_ISP_IFE_OUT_RES_BASE + 24) + +#define CAM_ISP_IFE_OUT_RES_MAX (CAM_ISP_IFE_OUT_RES_BASE + 25) + + +/* IFE input port resource type (global unique) */ +#define CAM_ISP_IFE_IN_RES_BASE 0x4000 + +#define CAM_ISP_IFE_IN_RES_TPG (CAM_ISP_IFE_IN_RES_BASE + 0) +#define CAM_ISP_IFE_IN_RES_PHY_0 (CAM_ISP_IFE_IN_RES_BASE + 1) +#define CAM_ISP_IFE_IN_RES_PHY_1 (CAM_ISP_IFE_IN_RES_BASE + 2) +#define CAM_ISP_IFE_IN_RES_PHY_2 (CAM_ISP_IFE_IN_RES_BASE + 3) +#define CAM_ISP_IFE_IN_RES_PHY_3 (CAM_ISP_IFE_IN_RES_BASE + 4) +#define CAM_ISP_IFE_IN_RES_PHY_4 (CAM_ISP_IFE_IN_RES_BASE + 5) +#define CAM_ISP_IFE_IN_RES_PHY_5 (CAM_ISP_IFE_IN_RES_BASE + 6) +#define CAM_ISP_IFE_IN_RES_RD (CAM_ISP_IFE_IN_RES_BASE + 7) +#define CAM_ISP_IFE_IN_RES_MAX (CAM_ISP_IFE_IN_RES_BASE + 8) + +#endif /* __UAPI_CAM_ISP_IFE_H__ */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_isp_tfe.h b/techpack/camera-bengal/include/uapi/media/cam_isp_tfe.h new file mode 100644 index 0000000000000000000000000000000000000000..fc716311367d11190bf310b5e1537d808438a894 --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_isp_tfe.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_ISP_TFE_H__ +#define __UAPI_CAM_ISP_TFE_H__ + +/* TFE output port resource id number */ +#define CAM_ISP_TFE_OUT_RES_BASE 0x1 + +#define CAM_ISP_TFE_OUT_RES_FULL (CAM_ISP_TFE_OUT_RES_BASE + 0) +#define CAM_ISP_TFE_OUT_RES_RAW_DUMP (CAM_ISP_TFE_OUT_RES_BASE + 1) +#define CAM_ISP_TFE_OUT_RES_PDAF (CAM_ISP_TFE_OUT_RES_BASE + 2) +#define CAM_ISP_TFE_OUT_RES_RDI_0 (CAM_ISP_TFE_OUT_RES_BASE + 3) +#define CAM_ISP_TFE_OUT_RES_RDI_1 (CAM_ISP_TFE_OUT_RES_BASE + 4) +#define CAM_ISP_TFE_OUT_RES_RDI_2 (CAM_ISP_TFE_OUT_RES_BASE + 5) +#define CAM_ISP_TFE_OUT_RES_STATS_HDR_BE (CAM_ISP_TFE_OUT_RES_BASE + 6) +#define CAM_ISP_TFE_OUT_RES_STATS_HDR_BHIST (CAM_ISP_TFE_OUT_RES_BASE + 7) +#define CAM_ISP_TFE_OUT_RES_STATS_TL_BG (CAM_ISP_TFE_OUT_RES_BASE + 8) +#define CAM_ISP_TFE_OUT_RES_STATS_BF (CAM_ISP_TFE_OUT_RES_BASE + 9) +#define CAM_ISP_TFE_OUT_RES_STATS_AWB_BG (CAM_ISP_TFE_OUT_RES_BASE + 10) +#define CAM_ISP_TFE_OUT_RES_MAX (CAM_ISP_TFE_OUT_RES_BASE + 11) + + +/* TFE input port resource type */ +#define CAM_ISP_TFE_IN_RES_BASE 0x1 + +#define CAM_ISP_TFE_IN_RES_TPG (CAM_ISP_TFE_IN_RES_BASE + 0) +#define CAM_ISP_TFE_IN_RES_PHY_0 (CAM_ISP_TFE_IN_RES_BASE + 1) +#define CAM_ISP_TFE_IN_RES_PHY_1 (CAM_ISP_TFE_IN_RES_BASE + 2) +#define CAM_ISP_TFE_IN_RES_PHY_2 (CAM_ISP_TFE_IN_RES_BASE + 3) +#define CAM_ISP_TFE_IN_RES_MAX (CAM_ISP_TFE_IN_RES_BASE + 4) + +#endif /* __UAPI_CAM_ISP_TFE_H__ */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_isp_vfe.h b/techpack/camera-bengal/include/uapi/media/cam_isp_vfe.h new file mode 100644 index 0000000000000000000000000000000000000000..497093902ba35f6ba49386c18b284f9d2df8f4ca --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_isp_vfe.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_ISP_VFE_H__ +#define __UAPI_CAM_ISP_VFE_H__ + +/* VFE output port resource type (global unique) */ +#define CAM_ISP_VFE_OUT_RES_BASE 0x1000 + +#define CAM_ISP_VFE_OUT_RES_ENC (CAM_ISP_VFE_OUT_RES_BASE + 0) +#define CAM_ISP_VFE_OUT_RES_VIEW (CAM_ISP_VFE_OUT_RES_BASE + 1) +#define CAM_ISP_VFE_OUT_RES_VID (CAM_ISP_VFE_OUT_RES_BASE + 2) +#define CAM_ISP_VFE_OUT_RES_RDI_0 (CAM_ISP_VFE_OUT_RES_BASE + 3) +#define CAM_ISP_VFE_OUT_RES_RDI_1 (CAM_ISP_VFE_OUT_RES_BASE + 4) +#define CAM_ISP_VFE_OUT_RES_RDI_2 (CAM_ISP_VFE_OUT_RES_BASE + 5) +#define CAM_ISP_VFE_OUT_RES_RDI_3 (CAM_ISP_VFE_OUT_RES_BASE + 6) +#define CAM_ISP_VFE_OUT_RES_STATS_AEC (CAM_ISP_VFE_OUT_RES_BASE + 7) +#define CAM_ISP_VFE_OUT_RES_STATS_AF (CAM_ISP_VFE_OUT_RES_BASE + 8) +#define CAM_ISP_VFE_OUT_RES_STATS_AWB (CAM_ISP_VFE_OUT_RES_BASE + 9) +#define CAM_ISP_VFE_OUT_RES_STATS_RS (CAM_ISP_VFE_OUT_RES_BASE + 10) +#define CAM_ISP_VFE_OUT_RES_STATS_CS (CAM_ISP_VFE_OUT_RES_BASE + 11) +#define CAM_ISP_VFE_OUT_RES_STATS_IHIST (CAM_ISP_VFE_OUT_RES_BASE + 12) +#define CAM_ISP_VFE_OUT_RES_STATS_SKIN (CAM_ISP_VFE_OUT_RES_BASE + 13) +#define CAM_ISP_VFE_OUT_RES_STATS_BG (CAM_ISP_VFE_OUT_RES_BASE + 14) +#define CAM_ISP_VFE_OUT_RES_STATS_BF (CAM_ISP_VFE_OUT_RES_BASE + 15) +#define CAM_ISP_VFE_OUT_RES_STATS_BE (CAM_ISP_VFE_OUT_RES_BASE + 16) +#define CAM_ISP_VFE_OUT_RES_STATS_BHIST (CAM_ISP_VFE_OUT_RES_BASE + 17) +#define CAM_ISP_VFE_OUT_RES_STATS_BF_SCALE (CAM_ISP_VFE_OUT_RES_BASE + 18) +#define CAM_ISP_VFE_OUT_RES_STATS_HDR_BE (CAM_ISP_VFE_OUT_RES_BASE + 19) +#define CAM_ISP_VFE_OUT_RES_STATS_HDR_BHIST (CAM_ISP_VFE_OUT_RES_BASE + 20) +#define CAM_ISP_VFE_OUT_RES_STATS_AEC_BG (CAM_ISP_VFE_OUT_RES_BASE + 21) +#define CAM_ISP_VFE_OUT_RES_CAMIF_RAW (CAM_ISP_VFE_OUT_RES_BASE + 22) +#define CAM_ISP_VFE_OUT_RES_IDEAL_RAW (CAM_ISP_VFE_OUT_RES_BASE + 23) +#define CAM_ISP_VFE_OUT_RES_MAX (CAM_ISP_VFE_OUT_RES_BASE + 24) + +/* VFE input port_ resource type (global unique) */ +#define CAM_ISP_VFE_IN_RES_BASE 0x2000 + +#define CAM_ISP_VFE_IN_RES_TPG (CAM_ISP_VFE_IN_RES_BASE + 0) +#define CAM_ISP_VFE_IN_RES_PHY_0 (CAM_ISP_VFE_IN_RES_BASE + 1) +#define CAM_ISP_VFE_IN_RES_PHY_1 (CAM_ISP_VFE_IN_RES_BASE + 2) +#define CAM_ISP_VFE_IN_RES_PHY_2 (CAM_ISP_VFE_IN_RES_BASE + 3) +#define CAM_ISP_VFE_IN_RES_PHY_3 (CAM_ISP_VFE_IN_RES_BASE + 4) +#define CAM_ISP_VFE_IN_RES_PHY_4 (CAM_ISP_VFE_IN_RES_BASE + 5) +#define CAM_ISP_VFE_IN_RES_PHY_5 (CAM_ISP_VFE_IN_RES_BASE + 6) +#define CAM_ISP_VFE_IN_RES_FE (CAM_ISP_VFE_IN_RES_BASE + 7) +#define CAM_ISP_VFE_IN_RES_MAX (CAM_ISP_VFE_IN_RES_BASE + 8) + +#endif /* __UAPI_CAM_ISP_VFE_H__ */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_jpeg.h b/techpack/camera-bengal/include/uapi/media/cam_jpeg.h new file mode 100644 index 0000000000000000000000000000000000000000..fd0ed2a2cfdb3d8ce31ee3bd1a8470aeac063860 --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_jpeg.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_JPEG_H__ +#define __UAPI_CAM_JPEG_H__ + +#include + +/* enc, dma, cdm(enc/dma) are used in querycap */ +#define CAM_JPEG_DEV_TYPE_ENC 0 +#define CAM_JPEG_DEV_TYPE_DMA 1 +#define CAM_JPEG_DEV_TYPE_MAX 2 + +#define CAM_JPEG_NUM_DEV_PER_RES_MAX 1 + +/* definitions needed for jpeg aquire device */ +#define CAM_JPEG_RES_TYPE_ENC 0 +#define CAM_JPEG_RES_TYPE_DMA 1 +#define CAM_JPEG_RES_TYPE_MAX 2 + +/* packet opcode types */ +#define CAM_JPEG_OPCODE_ENC_UPDATE 0 +#define CAM_JPEG_OPCODE_DMA_UPDATE 1 + +/* ENC input port resource type */ +#define CAM_JPEG_ENC_INPUT_IMAGE 0x0 + +/* ENC output port resource type */ +#define CAM_JPEG_ENC_OUTPUT_IMAGE 0x1 + +#define CAM_JPEG_ENC_IO_IMAGES_MAX 0x2 + +/* DMA input port resource type */ +#define CAM_JPEG_DMA_INPUT_IMAGE 0x0 + +/* DMA output port resource type */ +#define CAM_JPEG_DMA_OUTPUT_IMAGE 0x1 + +#define CAM_JPEG_DMA_IO_IMAGES_MAX 0x2 + +#define CAM_JPEG_IMAGE_MAX 0x2 + +/** + * struct cam_jpeg_dev_ver - Device information for particular hw type + * + * This is used to get device version info of JPEG ENC, JPEG DMA + * from hardware and use this info in CAM_QUERY_CAP IOCTL + * + * @size : Size of struct passed + * @dev_type: Hardware type for the cap info(jpeg enc, jpeg dma) + * @hw_ver: Major, minor and incr values of a device version + */ +struct cam_jpeg_dev_ver { + uint32_t size; + uint32_t dev_type; + struct cam_hw_version hw_ver; +}; + +/** + * struct cam_jpeg_query_cap_cmd - JPEG query device capability payload + * + * @dev_iommu_handle: Jpeg iommu handles for secure/non secure + * modes + * @cdm_iommu_handle: Iommu handles for secure/non secure modes + * @num_enc: Number of encoder + * @num_dma: Number of dma + * @dev_ver: Returned device capability array + */ +struct cam_jpeg_query_cap_cmd { + struct cam_iommu_handle dev_iommu_handle; + struct cam_iommu_handle cdm_iommu_handle; + uint32_t num_enc; + uint32_t num_dma; + struct cam_jpeg_dev_ver dev_ver[CAM_JPEG_DEV_TYPE_MAX]; +}; + +/** + * struct cam_jpeg_res_info - JPEG output resource info + * + * @format: Format of the resource + * @width: Width in pixels + * @height: Height in lines + * @fps: Fps + */ +struct cam_jpeg_res_info { + uint32_t format; + uint32_t width; + uint32_t height; + uint32_t fps; +}; + +/** + * struct cam_jpeg_acquire_dev_info - An JPEG device info + * + * @dev_type: Device type (ENC/DMA) + * @reserved: Reserved Bytes + * @in_res: In resource info + * @in_res: Iut resource info + */ +struct cam_jpeg_acquire_dev_info { + uint32_t dev_type; + uint32_t reserved; + struct cam_jpeg_res_info in_res; + struct cam_jpeg_res_info out_res; +}; + +/** + * struct cam_jpeg_config_inout_param_info - JPEG Config time + * input output params + * + * @clk_index: Input Param- clock selection index.(-1 default) + * @output_size: Output Param - jpeg encode/dma output size in + * bytes + */ +struct cam_jpeg_config_inout_param_info { + int32_t clk_index; + int32_t output_size; +}; + +#endif /* __UAPI_CAM_JPEG_H__ */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_lrme.h b/techpack/camera-bengal/include/uapi/media/cam_lrme.h new file mode 100644 index 0000000000000000000000000000000000000000..e3bd9449f7ef8a8899942d496dad8d96f4d39d43 --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_lrme.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_LRME_H__ +#define __UAPI_CAM_LRME_H__ + +#include + +/* LRME Resource Types */ + +enum CAM_LRME_IO_TYPE { + CAM_LRME_IO_TYPE_TAR, + CAM_LRME_IO_TYPE_REF, + CAM_LRME_IO_TYPE_RES, + CAM_LRME_IO_TYPE_DS2, +}; + +#define CAM_LRME_INPUT_PORT_TYPE_TAR (1 << 0) +#define CAM_LRME_INPUT_PORT_TYPE_REF (1 << 1) + +#define CAM_LRME_OUTPUT_PORT_TYPE_DS2 (1 << 0) +#define CAM_LRME_OUTPUT_PORT_TYPE_RES (1 << 1) + +#define CAM_LRME_DEV_MAX 1 + + +struct cam_lrme_hw_version { + uint32_t gen; + uint32_t rev; + uint32_t step; +}; + +struct cam_lrme_dev_cap { + struct cam_lrme_hw_version clc_hw_version; + struct cam_lrme_hw_version bus_rd_hw_version; + struct cam_lrme_hw_version bus_wr_hw_version; + struct cam_lrme_hw_version top_hw_version; + struct cam_lrme_hw_version top_titan_version; +}; + +/** + * struct cam_lrme_query_cap_cmd - LRME query device capability payload + * + * @dev_iommu_handle: LRME iommu handles for secure/non secure + * modes + * @cdm_iommu_handle: Iommu handles for secure/non secure modes + * @num_devices: number of hardware devices + * @dev_caps: Returned device capability array + */ +struct cam_lrme_query_cap_cmd { + struct cam_iommu_handle device_iommu; + struct cam_iommu_handle cdm_iommu; + uint32_t num_devices; + struct cam_lrme_dev_cap dev_caps[CAM_LRME_DEV_MAX]; +}; + +struct cam_lrme_soc_info { + uint64_t clock_rate; + uint64_t bandwidth; + uint64_t reserved[4]; +}; + +struct cam_lrme_acquire_args { + struct cam_lrme_soc_info lrme_soc_info; +}; + +#endif /* __UAPI_CAM_LRME_H__ */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_ope.h b/techpack/camera-bengal/include/uapi/media/cam_ope.h new file mode 100644 index 0000000000000000000000000000000000000000..a2d9845430a25265362f07caf7c04920902bf01f --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_ope.h @@ -0,0 +1,336 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __UAPI_OPE_H__ +#define __UAPI_OPE_H__ + +#include "cam_defs.h" +#include "cam_cpas.h" + +#define OPE_DEV_NAME_SIZE 128 + +/* OPE HW TYPE */ +#define OPE_HW_TYPE_OPE 0x1 +#define OPE_HW_TYPE_OPE_CDM 0x2 +#define OPE_HW_TYPE_MAX 0x3 + +/* OPE Device type */ +#define OPE_DEV_TYPE_OPE_RT 0x1 +#define OPE_DEV_TYPE_OPE_NRT 0x2 +#define OPE_DEV_TYPE_OPE_SEMI_RT 0x3 +#define OPE_DEV_TYPE_MAX 0x4 + +/* OPE Input Res Ports */ +#define OPE_IN_RES_FULL 0x1 +#define OPE_IN_RES_MAX OPE_IN_RES_FULL + +/* OPE Output Res Ports */ +#define OPE_OUT_RES_VIDEO 0x1 +#define OPE_OUT_RES_DISP 0x2 +#define OPE_OUT_RES_ARGB 0x3 +#define OPE_OUT_RES_STATS_RS 0x4 +#define OPE_OUT_RES_STATS_IHIST 0x5 +#define OPE_OUT_RES_STATS_LTM 0x6 +#define OPE_OUT_RES_MAX OPE_OUT_RES_STATS_LTM + +/* OPE packet opcodes */ +#define OPE_OPCODE_CONFIG 0x1 + +/* OPE Command Buffer Scope */ +#define OPE_CMD_BUF_SCOPE_BATCH 0x1 +#define OPE_CMD_BUF_SCOPE_FRAME 0x2 +#define OPE_CMD_BUF_SCOPE_PASS 0x3 +#define OPE_CMD_BUF_SCOPE_STRIPE 0x4 + +/* OPE Command Buffer Types */ +#define OPE_CMD_BUF_TYPE_DIRECT 0x1 +#define OPE_CMD_BUF_TYPE_INDIRECT 0x2 + +/* OPE Command Buffer Usage */ +#define OPE_CMD_BUF_UMD 0x1 +#define OPE_CMD_BUF_KMD 0x2 +#define OPE_CMD_BUF_DEBUG 0x3 + +/* OPE Single/Double Buffered */ +#define OPE_CMD_BUF_SINGLE_BUFFERED 0x1 +#define OPE_CMD_BUF_DOUBLE_BUFFERED 0x2 + +/* Command meta types */ +#define OPE_CMD_META_GENERIC_BLOB 0x1 + +/* Generic blob types */ +#define OPE_CMD_GENERIC_BLOB_CLK_V2 0x1 + +/* Stripe location */ +#define OPE_STRIPE_FULL 0x0 +#define OPE_STRIPE_LEFT 0x1 +#define OPE_STRIPE_RIGHT 0x2 +#define OPE_STRIPE_MIDDLE 0x3 + +#define OPE_MAX_CMD_BUFS 64 +#define OPE_MAX_IO_BUFS (OPE_OUT_RES_MAX + OPE_IN_RES_MAX) +#define OPE_MAX_PASS 1 +#define OPE_MAX_PLANES 2 +#define OPE_MAX_STRIPES 64 +#define OPE_MAX_BATCH_SIZE 16 + +/** + * struct ope_stripe_info - OPE stripe Info + * + * @offset: Offset in Bytes + * @x_init: X_init + * @stripe_location: Stripe location (OPE_STRIPE_XXX) + * @width: Width of a stripe + * @height: Height of a stripe + * @disable_bus: Flag to disable BUS master + * @reserved: Reserved + * + */ +struct ope_stripe_info { + uint32_t offset; + uint32_t x_init; + uint32_t stripe_location; + uint32_t width; + uint32_t height; + uint32_t disable_bus; + uint32_t reserved; +}; + +/** + * struct ope_io_buf_info - OPE IO buffers meta + * + * @direction: Direction of a buffer of a port(Input/Output) + * @resource_type: Port type + * @num_planes: Number of planes for a port + * @pix_pattern: Pixel pattern for raw input + * @num_stripes: Stripes per plane + * @mem_handle: Memhandles of each Input/Output Port + * @plane_offset: Offsets of planes + * @length: Length of a plane buffer + * @plane_stride: Plane stride + * @height: Height of a plane buffer + * @format: Format + * @fence: Fence of a Port + * @stripe_info: Stripe Info + * + */ +struct ope_io_buf_info { + uint32_t direction; + uint32_t resource_type; + uint32_t num_planes; + uint32_t pix_pattern; + uint32_t num_stripes[OPE_MAX_PLANES]; + uint32_t mem_handle[OPE_MAX_PLANES]; + uint32_t plane_offset[OPE_MAX_PLANES]; + uint32_t length[OPE_MAX_PLANES]; + uint32_t plane_stride[OPE_MAX_PLANES]; + uint32_t height[OPE_MAX_PLANES]; + uint32_t format; + uint32_t fence; + struct ope_stripe_info stripe_info[OPE_MAX_PLANES][OPE_MAX_STRIPES]; +}; + +/** + * struct ope_frame_set - OPE frameset + * + * @num_io_bufs: Number of I/O buffers + * @reserved: Reserved + * @io_buf: IO buffer info for all Input and Output ports + * + */ +struct ope_frame_set { + uint32_t num_io_bufs; + uint32_t reserved; + struct ope_io_buf_info io_buf[OPE_MAX_IO_BUFS]; +}; + +/** + * struct ope_cmd_buf_info - OPE command buffer meta + * + * @mem_handle: Memory handle for command buffer + * @offset: Offset of a command buffer + * @size: Size of command buffer + * @length: Length of a command buffer + * @cmd_buf_scope : Scope of a command buffer (OPE_CMD_BUF_SCOPE_XXX) + * @type: Command buffer type (OPE_CMD_BUF_TYPE_XXX) + * @cmd_buf_usage: Usage of command buffer ( OPE_CMD_BUF_USAGE_XXX) + * @stripe_idx: Stripe index in a req, It is valid for SCOPE_STRIPE + * @cmd_buf_pass_idx: Pass index + * @prefetch_disable: Prefecth disable flag + * + */ + +struct ope_cmd_buf_info { + uint32_t mem_handle; + uint32_t offset; + uint32_t size; + uint32_t length; + uint32_t cmd_buf_scope; + uint32_t type; + uint32_t cmd_buf_usage; + uint32_t cmd_buf_buffered; + uint32_t stripe_idx; + uint32_t cmd_buf_pass_idx; + uint32_t prefetch_disable; +}; + +/** + * struct ope_packet_payload - payload for a request + * + * @num_cmd_bufs: Number of command buffers + * @batch_size: Batch size in HFR mode + * @ope_cmd_buf_info: Command buffer meta data + * @ope_io_buf_info: Io buffer Info + * + */ +struct ope_frame_process { + uint32_t num_cmd_bufs[OPE_MAX_BATCH_SIZE]; + uint32_t batch_size; + struct ope_cmd_buf_info cmd_buf[OPE_MAX_BATCH_SIZE][OPE_MAX_CMD_BUFS]; + struct ope_frame_set frame_set[OPE_MAX_BATCH_SIZE]; +}; + +/** + * struct ope_clk_bw_request_v2 - clock and bandwidth for a request + * + * @budget_ns: Time required to process frame + * @frame_cycles: Frame cycles needed to process the frame + * @rt_flag: Flag to indicate real time stream + * @reserved: For memory alignment + * @axi_path: Per path vote info for OPE + * + */ +struct ope_clk_bw_request_v2 { + uint64_t budget_ns; + uint32_t frame_cycles; + uint32_t rt_flag; + uint32_t reserved; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[1]; +}; + +/** + * struct ope_hw_ver - Device information for OPE + * + * This is used to get device version info of + * OPE, CDM and use this info in CAM_QUERY_CAP IOCTL + * + * @hw_type: Hardware type for the cap info(OPE_HW_TYPE_XXX) + * @reserved: Reserved field + * @hw_ver: Major, minor and incr values of a hardware version + * + */ +struct ope_hw_ver { + uint32_t hw_type; + uint32_t reserved; + struct cam_hw_version hw_ver; +}; + +/** + * struct ope_query_cap_cmd - OPE query device capability payload + * + * @dev_iommu_handle: OPE iommu handles for secure/non secure modes + * @cdm_iommu_handle: CDM iommu handles for secure/non secure modes + * @num_ope: Number of OPEs + * @reserved: Reserved Parameter + * @hw_ver: Hardware capability array + */ +struct ope_query_cap_cmd { + struct cam_iommu_handle dev_iommu_handle; + struct cam_iommu_handle cdm_iommu_handle; + uint32_t num_ope; + uint32_t reserved; + struct ope_hw_ver hw_ver[OPE_DEV_TYPE_MAX]; +}; + +/** + * struct ope_out_res_info - OPE Output resource info + * + * @res_id: Resource ID + * @format: Output resource format + * @width: Output width + * @height: Output Height + * @alignment: Alignment + * @packer_format: Packer format + * @subsample_period: Subsample period in HFR + * @subsample_pattern: Subsample pattern in HFR + * @pixel_pattern: Pixel pattern + * @reserved: Reserved Parameter + * + */ +struct ope_out_res_info { + uint32_t res_id; + uint32_t format; + uint32_t width; + uint32_t height; + uint32_t alignment; + uint32_t packer_format; + uint32_t subsample_period; + uint32_t subsample_pattern; + uint32_t pixel_pattern; + uint32_t reserved; +}; + +/** + * struct ope_in_res_info - OPE Input resource info + * + * @res_id: Resource ID + * @format: Input resource format + * @width: Input width + * @height: Input Height + * @pixel_pattern: Pixel pattern + * @alignment: Alignment + * @unpacker_format: Unpacker format + * @max_stripe_size: Max stripe size supported for this instance configuration + * @fps: Frames per second + * @reserved: Reserved Parameter + * + */ +struct ope_in_res_info { + uint32_t res_id; + uint32_t format; + uint32_t width; + uint32_t height; + uint32_t pixel_pattern; + uint32_t alignment; + uint32_t unpacker_format; + uint32_t max_stripe_size; + uint32_t fps; + uint32_t reserved; +}; + +/** + * struct ope_acquire_dev_info - OPE Acquire Info + * + * @hw_type: OPE HW Types (OPE) + * @dev_type: Nature of Device Instance (RT/NRT) + * @dev_name: Name of Device Instance + * @nrt_stripes_for_arb: Program num stripes in OPE CDM for NRT device + * before setting ARB bit + * @secure_mode: Mode of Device operation (Secure or Non Secure) + * @batch_size: Batch size + * @num_in_res: Number of input resources (OPE_IN_RES_XXX) + * @in_res: Input resource info + * @num_out_res: Number of output resources (OPE_OUT_RES_XXX) + * @reserved: Reserved Parameter + * @out_res: Output resource info + * + */ +struct ope_acquire_dev_info { + uint32_t hw_type; + uint32_t dev_type; + char dev_name[OPE_DEV_NAME_SIZE]; + uint32_t nrt_stripes_for_arb; + uint32_t secure_mode; + uint32_t batch_size; + uint32_t num_in_res; + struct ope_in_res_info in_res[OPE_IN_RES_MAX]; + uint32_t num_out_res; + uint32_t reserved; + struct ope_out_res_info out_res[OPE_OUT_RES_MAX]; +} __attribute__((__packed__)); + +#endif /* __UAPI_OPE_H__ */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_req_mgr.h b/techpack/camera-bengal/include/uapi/media/cam_req_mgr.h new file mode 100644 index 0000000000000000000000000000000000000000..ebec0b04b9162fa323a848e93480d6af66d3e8ed --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_req_mgr.h @@ -0,0 +1,504 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_LINUX_CAM_REQ_MGR_H +#define __UAPI_LINUX_CAM_REQ_MGR_H + +#include +#include +#include +#include +#include + +#define CAM_REQ_MGR_VNODE_NAME "cam-req-mgr-devnode" + +#define CAM_DEVICE_TYPE_BASE (MEDIA_ENT_F_OLD_BASE) +#define CAM_VNODE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE) +#define CAM_SENSOR_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 1) +#define CAM_IFE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 2) +#define CAM_ICP_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 3) +#define CAM_LRME_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 4) +#define CAM_JPEG_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 5) +#define CAM_FD_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 6) +#define CAM_CPAS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 7) +#define CAM_CSIPHY_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 8) +#define CAM_ACTUATOR_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 9) +#define CAM_CCI_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 10) +#define CAM_FLASH_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 11) +#define CAM_EEPROM_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 12) +#define CAM_OIS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 13) +#define CAM_CUSTOM_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 14) +#define CAM_OPE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 15) +#define CAM_TFE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 16) + +/* cam_req_mgr hdl info */ +#define CAM_REQ_MGR_HDL_IDX_POS 8 +#define CAM_REQ_MGR_HDL_IDX_MASK ((1 << CAM_REQ_MGR_HDL_IDX_POS) - 1) +#define CAM_REQ_MGR_GET_HDL_IDX(hdl) (hdl & CAM_REQ_MGR_HDL_IDX_MASK) + +/** + * Max handles supported by cam_req_mgr + * It includes both session and device handles + */ +#define CAM_REQ_MGR_MAX_HANDLES 64 +#define CAM_REQ_MGR_MAX_HANDLES_V2 128 +#define MAX_LINKS_PER_SESSION 2 + +/* V4L event type which user space will subscribe to */ +#define V4L_EVENT_CAM_REQ_MGR_EVENT (V4L2_EVENT_PRIVATE_START + 0) + +/* Specific event ids to get notified in user space */ +#define V4L_EVENT_CAM_REQ_MGR_SOF 0 +#define V4L_EVENT_CAM_REQ_MGR_ERROR 1 +#define V4L_EVENT_CAM_REQ_MGR_SOF_BOOT_TS 2 +#define V4L_EVENT_CAM_REQ_MGR_CUSTOM_EVT 3 + +/* SOF Event status */ +#define CAM_REQ_MGR_SOF_EVENT_SUCCESS 0 +#define CAM_REQ_MGR_SOF_EVENT_ERROR 1 + +/* Link control operations */ +#define CAM_REQ_MGR_LINK_ACTIVATE 0 +#define CAM_REQ_MGR_LINK_DEACTIVATE 1 + +/** + * Request Manager : flush_type + * @CAM_REQ_MGR_FLUSH_TYPE_ALL: Req mgr will remove all the pending + * requests from input/processing queue. + * @CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ: Req mgr will remove only particular + * request id from input/processing queue. + * @CAM_REQ_MGR_FLUSH_TYPE_MAX: Max number of the flush type + * @opcode: CAM_REQ_MGR_FLUSH_REQ + */ +#define CAM_REQ_MGR_FLUSH_TYPE_ALL 0 +#define CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ 1 +#define CAM_REQ_MGR_FLUSH_TYPE_MAX 2 + +/** + * Request Manager : Sync Mode type + * @CAM_REQ_MGR_SYNC_MODE_NO_SYNC: Req mgr will apply non-sync mode for this + * request. + * @CAM_REQ_MGR_SYNC_MODE_SYNC: Req mgr will apply sync mode for this request. + */ +#define CAM_REQ_MGR_SYNC_MODE_NO_SYNC 0 +#define CAM_REQ_MGR_SYNC_MODE_SYNC 1 + +/** + * struct cam_req_mgr_event_data + * @session_hdl: session handle + * @link_hdl: link handle + * @frame_id: frame id + * @reserved: reserved for 64 bit aligngment + * @req_id: request id + * @tv_sec: timestamp in seconds + * @tv_usec: timestamp in micro seconds + */ +struct cam_req_mgr_event_data { + int32_t session_hdl; + int32_t link_hdl; + int32_t frame_id; + int32_t reserved; + int64_t req_id; + uint64_t tv_sec; + uint64_t tv_usec; +}; + +/** + * struct cam_req_mgr_session_info + * @session_hdl: In/Output param - session_handle + * @opcode1: CAM_REQ_MGR_CREATE_SESSION + * @opcode2: CAM_REQ_MGR_DESTROY_SESSION + */ +struct cam_req_mgr_session_info { + int32_t session_hdl; + int32_t reserved; +}; + +/** + * struct cam_req_mgr_link_info + * @session_hdl: Input param - Identifier for CSL session + * @num_devices: Input Param - Num of devices to be linked + * @dev_hdls: Input param - List of device handles to be linked + * @link_hdl: Output Param -Identifier for link + * @opcode: CAM_REQ_MGR_LINK + */ +struct cam_req_mgr_link_info { + int32_t session_hdl; + uint32_t num_devices; + int32_t dev_hdls[CAM_REQ_MGR_MAX_HANDLES]; + int32_t link_hdl; +}; + +struct cam_req_mgr_link_info_v2 { + int32_t session_hdl; + uint32_t num_devices; + int32_t dev_hdls[CAM_REQ_MGR_MAX_HANDLES_V2]; + int32_t link_hdl; +}; + +struct cam_req_mgr_ver_info { + uint32_t version; + union { + struct cam_req_mgr_link_info link_info_v1; + struct cam_req_mgr_link_info_v2 link_info_v2; + } u; +}; +/** + * struct cam_req_mgr_unlink_info + * @session_hdl: input param - session handle + * @link_hdl: input param - link handle + * @opcode: CAM_REQ_MGR_UNLINK + */ +struct cam_req_mgr_unlink_info { + int32_t session_hdl; + int32_t link_hdl; +}; + +/** + * struct cam_req_mgr_flush_info + * @brief: User can tell drivers to flush a particular request id or + * flush all requests from its pending processing queue. Flush is a + * blocking call and driver shall ensure all requests are flushed + * before returning. + * @session_hdl: Input param - Identifier for CSL session + * @link_hdl: Input Param -Identifier for link + * @flush_type: User can cancel a particular req id or can flush + * all requests in queue + * @reserved: reserved for 64 bit aligngment + * @req_id: field is valid only if flush type is cancel request + * for flush all this field value is not considered. + * @opcode: CAM_REQ_MGR_FLUSH_REQ + */ +struct cam_req_mgr_flush_info { + int32_t session_hdl; + int32_t link_hdl; + uint32_t flush_type; + uint32_t reserved; + int64_t req_id; +}; + +/** struct cam_req_mgr_sched_info + * @session_hdl: Input param - Identifier for CSL session + * @link_hdl: Input Param -Identifier for link + * inluding itself. + * @bubble_enable: Input Param - Cam req mgr will do bubble recovery if this + * flag is set. + * @sync_mode: Type of Sync mode for this request + * @additional_timeout: Additional timeout value (in ms) associated with + * this request. This value needs to be 0 in cases where long exposure is + * not configured for the sensor.The max timeout that will be supported + * is 50000 ms + * @reserved: Reserved + * @req_id: Input Param - Request Id from which all requests will be flushed + */ +struct cam_req_mgr_sched_request { + int32_t session_hdl; + int32_t link_hdl; + int32_t bubble_enable; + int32_t sync_mode; + int32_t additional_timeout; + int32_t reserved; + int64_t req_id; +}; + +/** + * struct cam_req_mgr_sync_mode + * @session_hdl: Input param - Identifier for CSL session + * @sync_mode: Input Param - Type of sync mode + * @num_links: Input Param - Num of links in sync mode (Valid only + * when sync_mode is one of SYNC enabled modes) + * @link_hdls: Input Param - Array of link handles to be in sync mode + * (Valid only when sync_mode is one of SYNC + * enabled modes) + * @master_link_hdl: Input Param - To dictate which link's SOF drives system + * (Valid only when sync_mode is one of SYNC + * enabled modes) + * + * @opcode: CAM_REQ_MGR_SYNC_MODE + */ +struct cam_req_mgr_sync_mode { + int32_t session_hdl; + int32_t sync_mode; + int32_t num_links; + int32_t link_hdls[MAX_LINKS_PER_SESSION]; + int32_t master_link_hdl; + int32_t reserved; +}; + +/** + * struct cam_req_mgr_link_control + * @ops: Link operations: activate/deactive + * @session_hdl: Input param - Identifier for CSL session + * @num_links: Input Param - Num of links + * @reserved: reserved field + * @link_hdls: Input Param - Links to be activated/deactivated + * + * @opcode: CAM_REQ_MGR_LINK_CONTROL + */ +struct cam_req_mgr_link_control { + int32_t ops; + int32_t session_hdl; + int32_t num_links; + int32_t reserved; + int32_t link_hdls[MAX_LINKS_PER_SESSION]; +}; + +/** + * cam_req_mgr specific opcode ids + */ +#define CAM_REQ_MGR_CREATE_DEV_NODES (CAM_COMMON_OPCODE_MAX + 1) +#define CAM_REQ_MGR_CREATE_SESSION (CAM_COMMON_OPCODE_MAX + 2) +#define CAM_REQ_MGR_DESTROY_SESSION (CAM_COMMON_OPCODE_MAX + 3) +#define CAM_REQ_MGR_LINK (CAM_COMMON_OPCODE_MAX + 4) +#define CAM_REQ_MGR_UNLINK (CAM_COMMON_OPCODE_MAX + 5) +#define CAM_REQ_MGR_SCHED_REQ (CAM_COMMON_OPCODE_MAX + 6) +#define CAM_REQ_MGR_FLUSH_REQ (CAM_COMMON_OPCODE_MAX + 7) +#define CAM_REQ_MGR_SYNC_MODE (CAM_COMMON_OPCODE_MAX + 8) +#define CAM_REQ_MGR_ALLOC_BUF (CAM_COMMON_OPCODE_MAX + 9) +#define CAM_REQ_MGR_MAP_BUF (CAM_COMMON_OPCODE_MAX + 10) +#define CAM_REQ_MGR_RELEASE_BUF (CAM_COMMON_OPCODE_MAX + 11) +#define CAM_REQ_MGR_CACHE_OPS (CAM_COMMON_OPCODE_MAX + 12) +#define CAM_REQ_MGR_LINK_CONTROL (CAM_COMMON_OPCODE_MAX + 13) +#define CAM_REQ_MGR_LINK_V2 (CAM_COMMON_OPCODE_MAX + 14) +#define CAM_REQ_MGR_REQUEST_DUMP (CAM_COMMON_OPCODE_MAX + 15) + +/* end of cam_req_mgr opcodes */ + +#define CAM_MEM_FLAG_HW_READ_WRITE (1<<0) +#define CAM_MEM_FLAG_HW_READ_ONLY (1<<1) +#define CAM_MEM_FLAG_HW_WRITE_ONLY (1<<2) +#define CAM_MEM_FLAG_KMD_ACCESS (1<<3) +#define CAM_MEM_FLAG_UMD_ACCESS (1<<4) +#define CAM_MEM_FLAG_PROTECTED_MODE (1<<5) +#define CAM_MEM_FLAG_CMD_BUF_TYPE (1<<6) +#define CAM_MEM_FLAG_PIXEL_BUF_TYPE (1<<7) +#define CAM_MEM_FLAG_STATS_BUF_TYPE (1<<8) +#define CAM_MEM_FLAG_PACKET_BUF_TYPE (1<<9) +#define CAM_MEM_FLAG_CACHE (1<<10) +#define CAM_MEM_FLAG_HW_SHARED_ACCESS (1<<11) +#define CAM_MEM_FLAG_CDSP_OUTPUT (1<<12) +#define CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP (1<<13) +#define CAM_MEM_FLAG_KMD_DEBUG_FLAG (1<<14) + + +#define CAM_MEM_MMU_MAX_HANDLE 16 + +/* Maximum allowed buffers in existence */ +#define CAM_MEM_BUFQ_MAX 1024 + +#define CAM_MEM_MGR_SECURE_BIT_POS 15 +#define CAM_MEM_MGR_HDL_IDX_SIZE 15 +#define CAM_MEM_MGR_HDL_FD_SIZE 16 +#define CAM_MEM_MGR_HDL_IDX_END_POS 16 +#define CAM_MEM_MGR_HDL_FD_END_POS 32 + +#define CAM_MEM_MGR_HDL_IDX_MASK ((1 << CAM_MEM_MGR_HDL_IDX_SIZE) - 1) + +#define GET_MEM_HANDLE(idx, fd) \ + ((idx & CAM_MEM_MGR_HDL_IDX_MASK) | \ + (fd << (CAM_MEM_MGR_HDL_FD_END_POS - CAM_MEM_MGR_HDL_FD_SIZE))) \ + +#define GET_FD_FROM_HANDLE(hdl) \ + (hdl >> (CAM_MEM_MGR_HDL_FD_END_POS - CAM_MEM_MGR_HDL_FD_SIZE)) \ + +#define CAM_MEM_MGR_GET_HDL_IDX(hdl) (hdl & CAM_MEM_MGR_HDL_IDX_MASK) + +#define CAM_MEM_MGR_SET_SECURE_HDL(hdl, flag) \ + ((flag) ? (hdl |= (1 << CAM_MEM_MGR_SECURE_BIT_POS)) : \ + ((hdl) &= ~(1 << CAM_MEM_MGR_SECURE_BIT_POS))) + +#define CAM_MEM_MGR_IS_SECURE_HDL(hdl) \ + (((hdl) & \ + (1<> CAM_MEM_MGR_SECURE_BIT_POS) + +/** + * memory allocation type + */ +#define CAM_MEM_DMA_NONE 0 +#define CAM_MEM_DMA_BIDIRECTIONAL 1 +#define CAM_MEM_DMA_TO_DEVICE 2 +#define CAM_MEM_DMA_FROM_DEVICE 3 + + +/** + * memory cache operation + */ +#define CAM_MEM_CLEAN_CACHE 1 +#define CAM_MEM_INV_CACHE 2 +#define CAM_MEM_CLEAN_INV_CACHE 3 + + +/** + * struct cam_mem_alloc_out_params + * @buf_handle: buffer handle + * @fd: output buffer file descriptor + * @vaddr: virtual address pointer + */ +struct cam_mem_alloc_out_params { + uint32_t buf_handle; + int32_t fd; + uint64_t vaddr; +}; + +/** + * struct cam_mem_map_out_params + * @buf_handle: buffer handle + * @reserved: reserved for future + * @vaddr: virtual address pointer + */ +struct cam_mem_map_out_params { + uint32_t buf_handle; + uint32_t reserved; + uint64_t vaddr; +}; + +/** + * struct cam_mem_mgr_alloc_cmd + * @len: size of buffer to allocate + * @align: alignment of the buffer + * @mmu_hdls: array of mmu handles + * @num_hdl: number of handles + * @flags: flags of the buffer + * @out: out params + */ +/* CAM_REQ_MGR_ALLOC_BUF */ +struct cam_mem_mgr_alloc_cmd { + uint64_t len; + uint64_t align; + int32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE]; + uint32_t num_hdl; + uint32_t flags; + struct cam_mem_alloc_out_params out; +}; + +/** + * struct cam_mem_mgr_map_cmd + * @mmu_hdls: array of mmu handles + * @num_hdl: number of handles + * @flags: flags of the buffer + * @fd: output buffer file descriptor + * @reserved: reserved field + * @out: out params + */ + +/* CAM_REQ_MGR_MAP_BUF */ +struct cam_mem_mgr_map_cmd { + int32_t mmu_hdls[CAM_MEM_MMU_MAX_HANDLE]; + uint32_t num_hdl; + uint32_t flags; + int32_t fd; + uint32_t reserved; + struct cam_mem_map_out_params out; +}; + +/** + * struct cam_mem_mgr_map_cmd + * @buf_handle: buffer handle + * @reserved: reserved field + */ +/* CAM_REQ_MGR_RELEASE_BUF */ +struct cam_mem_mgr_release_cmd { + int32_t buf_handle; + uint32_t reserved; +}; + +/** + * struct cam_mem_mgr_map_cmd + * @buf_handle: buffer handle + * @ops: cache operations + */ +/* CAM_REQ_MGR_CACHE_OPS */ +struct cam_mem_cache_ops_cmd { + int32_t buf_handle; + uint32_t mem_cache_ops; +}; + +/** + * Request Manager : error message type + * @CAM_REQ_MGR_ERROR_TYPE_DEVICE: Device error message, fatal to session + * @CAM_REQ_MGR_ERROR_TYPE_REQUEST: Error on a single request, not fatal + * @CAM_REQ_MGR_ERROR_TYPE_BUFFER: Buffer was not filled, not fatal + * @CAM_REQ_MGR_ERROR_TYPE_RECOVERY: Fatal error, can be recovered + * @CAM_REQ_MGR_ERROR_TYPE_SOF_FREEZE: SOF freeze, can be recovered + * @CAM_REQ_MGR_ERROR_TYPE_FULL_RECOVERY: Full recovery, can be recovered + */ +#define CAM_REQ_MGR_ERROR_TYPE_DEVICE 0 +#define CAM_REQ_MGR_ERROR_TYPE_REQUEST 1 +#define CAM_REQ_MGR_ERROR_TYPE_BUFFER 2 +#define CAM_REQ_MGR_ERROR_TYPE_RECOVERY 3 +#define CAM_REQ_MGR_ERROR_TYPE_SOF_FREEZE 4 +#define CAM_REQ_MGR_ERROR_TYPE_FULL_RECOVERY 5 + +/** + * struct cam_req_mgr_error_msg + * @error_type: type of error + * @request_id: request id of frame + * @device_hdl: device handle + * @linke_hdl: link_hdl + * @resource_size: size of the resource + */ +struct cam_req_mgr_error_msg { + uint32_t error_type; + uint32_t request_id; + int32_t device_hdl; + int32_t link_hdl; + uint64_t resource_size; +}; + +/** + * struct cam_req_mgr_frame_msg + * @request_id: request id of the frame + * @frame_id: frame id of the frame + * @timestamp: timestamp of the frame + * @link_hdl: link handle associated with this message + * @sof_status: sof status success or fail + * @frame_id_meta: refers to the meta for + * that frame in specific usecases + * @reserved: reserved + */ +struct cam_req_mgr_frame_msg { + uint64_t request_id; + uint64_t frame_id; + uint64_t timestamp; + int32_t link_hdl; + uint32_t sof_status; + uint32_t frame_id_meta; + uint32_t reserved; +}; + +/** + * struct cam_req_mgr_custom_msg + * @custom_type: custom type + * @request_id: request id of the frame + * @frame_id: frame id of the frame + * @timestamp: timestamp of the frame + * @link_hdl: link handle associated with this message + * @custom_data: custom data + */ +struct cam_req_mgr_custom_msg { + uint32_t custom_type; + uint64_t request_id; + uint64_t frame_id; + uint64_t timestamp; + int32_t link_hdl; + uint64_t custom_data; +}; + +/** + * struct cam_req_mgr_message + * @session_hdl: session to which the frame belongs to + * @reserved: reserved field + * @u: union which can either be error/frame/custom message + */ +struct cam_req_mgr_message { + int32_t session_hdl; + int32_t reserved; + union { + struct cam_req_mgr_error_msg err_msg; + struct cam_req_mgr_frame_msg frame_msg; + struct cam_req_mgr_custom_msg custom_msg; + } u; +}; +#endif /* __UAPI_LINUX_CAM_REQ_MGR_H */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_sensor.h b/techpack/camera-bengal/include/uapi/media/cam_sensor.h new file mode 100644 index 0000000000000000000000000000000000000000..9d16af96190492e60226017ae343cd51a32e268c --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_sensor.h @@ -0,0 +1,488 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2016-2019, 2021 The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_SENSOR_H__ +#define __UAPI_CAM_SENSOR_H__ + +#include +#include +#include + +#define CAM_SENSOR_PROBE_CMD (CAM_COMMON_OPCODE_MAX + 1) +#define CAM_FLASH_MAX_LED_TRIGGERS 3 +#define MAX_OIS_NAME_SIZE 32 +#define CAM_CSIPHY_SECURE_MODE_ENABLED 1 +/** + * struct cam_sensor_query_cap - capabilities info for sensor + * + * @slot_info : Indicates about the slotId or cell Index + * @secure_camera : Camera is in secure/Non-secure mode + * @pos_pitch : Sensor position pitch + * @pos_roll : Sensor position roll + * @pos_yaw : Sensor position yaw + * @actuator_slot_id : Actuator slot id which connected to sensor + * @eeprom_slot_id : EEPROM slot id which connected to sensor + * @ois_slot_id : OIS slot id which connected to sensor + * @flash_slot_id : Flash slot id which connected to sensor + * @csiphy_slot_id : CSIphy slot id which connected to sensor + * + */ +struct cam_sensor_query_cap { + uint32_t slot_info; + uint32_t secure_camera; + uint32_t pos_pitch; + uint32_t pos_roll; + uint32_t pos_yaw; + uint32_t actuator_slot_id; + uint32_t eeprom_slot_id; + uint32_t ois_slot_id; + uint32_t flash_slot_id; + uint32_t csiphy_slot_id; +} __attribute__((packed)); + +/** + * struct cam_csiphy_query_cap - capabilities info for csiphy + * + * @slot_info : Indicates about the slotId or cell Index + * @version : CSIphy version + * @clk lane : Of the 5 lanes, informs lane configured + * as clock lane + * @reserved + */ +struct cam_csiphy_query_cap { + uint32_t slot_info; + uint32_t version; + uint32_t clk_lane; + uint32_t reserved; +} __attribute__((packed)); + +/** + * struct cam_actuator_query_cap - capabilities info for actuator + * + * @slot_info : Indicates about the slotId or cell Index + * @reserved + */ +struct cam_actuator_query_cap { + uint32_t slot_info; + uint32_t reserved; +} __attribute__((packed)); + +/** + * struct cam_eeprom_query_cap_t - capabilities info for eeprom + * + * @slot_info : Indicates about the slotId or cell Index + * @eeprom_kernel_probe : Indicates about the kernel or userspace probe + */ +struct cam_eeprom_query_cap_t { + uint32_t slot_info; + uint16_t eeprom_kernel_probe; + uint16_t is_multimodule_mode; +} __attribute__((packed)); + +/** + * struct cam_ois_query_cap_t - capabilities info for ois + * + * @slot_info : Indicates about the slotId or cell Index + */ +struct cam_ois_query_cap_t { + uint32_t slot_info; + uint16_t reserved; +} __attribute__((packed)); + +/** + * struct cam_cmd_i2c_info - Contains slave I2C related info + * + * @slave_addr : Slave address + * @i2c_freq_mode : 4 bits are used for I2c freq mode + * @cmd_type : Explains type of command + */ +struct cam_cmd_i2c_info { + uint32_t slave_addr; + uint8_t i2c_freq_mode; + uint8_t cmd_type; + uint16_t reserved; +} __attribute__((packed)); + +/** + * struct cam_ois_opcode - Contains OIS opcode + * + * @prog : OIS FW prog register address + * @coeff : OIS FW coeff register address + * @pheripheral : OIS pheripheral + * @memory : OIS memory + */ +struct cam_ois_opcode { + uint32_t prog; + uint32_t coeff; + uint32_t pheripheral; + uint32_t memory; +} __attribute__((packed)); + +/** + * struct cam_cmd_ois_info - Contains OIS slave info + * + * @slave_addr : OIS i2c slave address + * @i2c_freq_mode : i2c frequency mode + * @cmd_type : Explains type of command + * @ois_fw_flag : indicates if fw is present or not + * @is_ois_calib : indicates the calibration data is available + * @ois_name : OIS name + * @opcode : opcode + */ +struct cam_cmd_ois_info { + uint32_t slave_addr; + uint8_t i2c_freq_mode; + uint8_t cmd_type; + uint8_t ois_fw_flag; + uint8_t is_ois_calib; + char ois_name[MAX_OIS_NAME_SIZE]; + struct cam_ois_opcode opcode; +} __attribute__((packed)); + +/** + * struct cam_cmd_probe - Contains sensor slave info + * + * @data_type : Slave register data type + * @addr_type : Slave register address type + * @op_code : Don't Care + * @cmd_type : Explains type of command + * @reg_addr : Slave register address + * @expected_data : Data expected at slave register address + * @data_mask : Data mask if only few bits are valid + * @camera_id : Indicates the slot to which camera + * needs to be probed + * @reserved + */ +struct cam_cmd_probe { + uint8_t data_type; + uint8_t addr_type; + uint8_t op_code; + uint8_t cmd_type; + uint32_t reg_addr; + uint32_t expected_data; + uint32_t data_mask; + uint16_t camera_id; + uint16_t reserved; +} __attribute__((packed)); + +/** + * struct cam_power_settings - Contains sensor power setting info + * + * @power_seq_type : Type of power sequence + * @reserved + * @config_val_low : Lower 32 bit value configuration value + * @config_val_high : Higher 32 bit value configuration value + * + */ +struct cam_power_settings { + uint16_t power_seq_type; + uint16_t reserved; + uint32_t config_val_low; + uint32_t config_val_high; +} __attribute__((packed)); + +/** + * struct cam_cmd_power - Explains about the power settings + * + * @count : Number of power settings follows + * @reserved + * @cmd_type : Explains type of command + * @power_settings : Contains power setting info + */ +struct cam_cmd_power { + uint32_t count; + uint8_t reserved; + uint8_t cmd_type; + uint16_t more_reserved; + struct cam_power_settings power_settings[1]; +} __attribute__((packed)); + +/** + * struct i2c_rdwr_header - header of READ/WRITE I2C command + * + * @ count : Number of registers / data / reg-data pairs + * @ op_code : Operation code + * @ cmd_type : Command buffer type + * @ data_type : I2C data type + * @ addr_type : I2C address type + * @ reserved + */ +struct i2c_rdwr_header { + uint32_t count; + uint8_t op_code; + uint8_t cmd_type; + uint8_t data_type; + uint8_t addr_type; +} __attribute__((packed)); + +/** + * struct i2c_random_wr_payload - payload for I2C random write + * + * @ reg_addr : Register address + * @ reg_data : Register data + * + */ +struct i2c_random_wr_payload { + uint32_t reg_addr; + uint32_t reg_data; +} __attribute__((packed)); + +/** + * struct cam_cmd_i2c_random_wr - I2C random write command + * @ header : header of READ/WRITE I2C command + * @ random_wr_payload : payload for I2C random write + */ +struct cam_cmd_i2c_random_wr { + struct i2c_rdwr_header header; + struct i2c_random_wr_payload random_wr_payload[1]; +} __attribute__((packed)); + +/** + * struct cam_cmd_read - I2C read command + * @ reg_data : Register data + * @ reserved + */ +struct cam_cmd_read { + uint32_t reg_data; + uint32_t reserved; +} __attribute__((packed)); + +/** + * struct cam_cmd_i2c_continuous_wr - I2C continuous write command + * @ header : header of READ/WRITE I2C command + * @ reg_addr : Register address + * @ data_read : I2C read command + */ +struct cam_cmd_i2c_continuous_wr { + struct i2c_rdwr_header header; + uint32_t reg_addr; + struct cam_cmd_read data_read[1]; +} __attribute__((packed)); + +/** + * struct cam_cmd_i2c_random_rd - I2C random read command + * @ header : header of READ/WRITE I2C command + * @ data_read : I2C read command + */ +struct cam_cmd_i2c_random_rd { + struct i2c_rdwr_header header; + struct cam_cmd_read data_read[1]; +} __attribute__((packed)); + +/** + * struct cam_cmd_i2c_continuous_rd - I2C continuous continuous read command + * @ header : header of READ/WRITE I2C command + * @ reg_addr : Register address + * + */ +struct cam_cmd_i2c_continuous_rd { + struct i2c_rdwr_header header; + uint32_t reg_addr; +} __attribute__((packed)); + +/** + * struct cam_cmd_conditional_wait - Conditional wait command + * @data_type : Data type + * @addr_type : Address type + * @op_code : Opcode + * @cmd_type : Explains type of command + * @timeout : Timeout for retries + * @reserved + * @reg_addr : Register Address + * @reg_data : Register data + * @data_mask : Data mask if only few bits are valid + * @camera_id : Indicates the slot to which camera + * needs to be probed + * + */ +struct cam_cmd_conditional_wait { + uint8_t data_type; + uint8_t addr_type; + uint16_t reserved; + uint8_t op_code; + uint8_t cmd_type; + uint16_t timeout; + uint32_t reg_addr; + uint32_t reg_data; + uint32_t data_mask; +} __attribute__((packed)); + +/** + * struct cam_cmd_unconditional_wait - Un-conditional wait command + * @delay : Delay + * @op_code : Opcode + * @cmd_type : Explains type of command + */ +struct cam_cmd_unconditional_wait { + int16_t delay; + int16_t reserved; + uint8_t op_code; + uint8_t cmd_type; + uint16_t reserved1; +} __attribute__((packed)); + +/** + * cam_csiphy_info: Provides cmdbuffer structre + * @lane_mask : Lane mask details + * @lane_assign : Lane sensor will be using + * @csiphy_3phase : Total number of lanes + * @combo_mode : Info regarding combo_mode is enable / disable + * @lane_cnt : Total number of lanes + * @secure_mode : Secure mode flag to enable / disable + * @3phase : Details whether 3Phase / 2Phase operation + * @settle_time : Settling time in ms + * @data_rate : Data rate + * + */ +struct cam_csiphy_info { + uint16_t lane_mask; + uint16_t lane_assign; + uint8_t csiphy_3phase; + uint8_t combo_mode; + uint8_t lane_cnt; + uint8_t secure_mode; + uint64_t settle_time; + uint64_t data_rate; +} __attribute__((packed)); + +/** + * cam_csiphy_acquire_dev_info : Information needed for + * csiphy at the time of acquire + * @combo_mode : Indicates the device mode of operation + * @reserved + * + */ +struct cam_csiphy_acquire_dev_info { + uint32_t combo_mode; + uint32_t reserved; +} __attribute__((packed)); + +/** + * cam_sensor_acquire_dev : Updates sensor acuire cmd + * @device_handle : Updates device handle + * @session_handle : Session handle for acquiring device + * @handle_type : Resource handle type + * @reserved + * @info_handle : Handle to additional info + * needed for sensor sub modules + * + */ +struct cam_sensor_acquire_dev { + uint32_t session_handle; + uint32_t device_handle; + uint32_t handle_type; + uint32_t reserved; + uint64_t info_handle; +} __attribute__((packed)); + +/** + * cam_sensor_streamon_dev : StreamOn command for the sensor + * @session_handle : Session handle for acquiring device + * @device_handle : Updates device handle + * @handle_type : Resource handle type + * @reserved + * @info_handle : Information Needed at the time of streamOn + * + */ +struct cam_sensor_streamon_dev { + uint32_t session_handle; + uint32_t device_handle; + uint32_t handle_type; + uint32_t reserved; + uint64_t info_handle; +} __attribute__((packed)); + +/** + * struct cam_flash_init : Init command for the flash + * @flash_type : flash hw type + * @reserved + * @cmd_type : command buffer type + */ +struct cam_flash_init { + uint32_t flash_type; + uint8_t reserved; + uint8_t cmd_type; + uint16_t reserved1; +} __attribute__((packed)); + +/** + * struct cam_flash_set_rer : RedEyeReduction command buffer + * + * @count : Number of flash leds + * @opcode : Command buffer opcode + * CAM_FLASH_FIRE_RER + * @cmd_type : command buffer operation type + * @num_iteration : Number of led turn on/off sequence + * @reserved + * @led_on_delay_ms : flash led turn on time in ms + * @led_off_delay_ms : flash led turn off time in ms + * @led_current_ma : flash led current in ma + * + */ +struct cam_flash_set_rer { + uint32_t count; + uint8_t opcode; + uint8_t cmd_type; + uint16_t num_iteration; + uint32_t led_on_delay_ms; + uint32_t led_off_delay_ms; + uint32_t led_current_ma[CAM_FLASH_MAX_LED_TRIGGERS]; +} __attribute__((packed)); + +/** + * struct cam_flash_set_on_off : led turn on/off command buffer + * + * @count : Number of Flash leds + * @opcode : command buffer opcodes + * CAM_FLASH_FIRE_LOW + * CAM_FLASH_FIRE_HIGH + * CAM_FLASH_OFF + * @cmd_type : command buffer operation type + * @led_current_ma : flash led current in ma + * + */ +struct cam_flash_set_on_off { + uint32_t count; + uint8_t opcode; + uint8_t cmd_type; + uint16_t reserved; + uint32_t led_current_ma[CAM_FLASH_MAX_LED_TRIGGERS]; +} __attribute__((packed)); + +/** + * struct cam_flash_query_curr : query current command buffer + * + * @reserved + * @opcode : command buffer opcode + * @cmd_type : command buffer operation type + * @query_current_ma : battery current in ma + * + */ +struct cam_flash_query_curr { + uint16_t reserved; + uint8_t opcode; + uint8_t cmd_type; + uint32_t query_current_ma; +} __attribute__ ((packed)); + +/** + * struct cam_flash_query_cap : capabilities info for flash + * + * @slot_info : Indicates about the slotId or cell Index + * @max_current_flash : max supported current for flash + * @max_duration_flash : max flash turn on duration + * @max_current_torch : max supported current for torch + * @flash_type : Indicates about the flash type -I2C,GPIO,PMIC + * + */ +struct cam_flash_query_cap_info { + uint32_t slot_info; + uint32_t max_current_flash[CAM_FLASH_MAX_LED_TRIGGERS]; + uint32_t max_duration_flash[CAM_FLASH_MAX_LED_TRIGGERS]; + uint32_t max_current_torch[CAM_FLASH_MAX_LED_TRIGGERS]; + uint32_t flash_type; +} __attribute__ ((packed)); + +#endif diff --git a/techpack/camera-bengal/include/uapi/media/cam_sync.h b/techpack/camera-bengal/include/uapi/media/cam_sync.h new file mode 100644 index 0000000000000000000000000000000000000000..d1ab63fd4294e7a0621ebbc136cde299ef8a5914 --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_sync.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_SYNC_H__ +#define __UAPI_CAM_SYNC_H__ + +#include +#include +#include +#include + +#define CAM_SYNC_DEVICE_NAME "cam_sync_device" + +/* V4L event which user space will subscribe to */ +#define CAM_SYNC_V4L_EVENT (V4L2_EVENT_PRIVATE_START + 0) + +/* Specific event ids to get notified in user space */ +#define CAM_SYNC_V4L_EVENT_ID_CB_TRIG 0 + +/* Size of opaque payload sent to kernel for safekeeping until signal time */ +#define CAM_SYNC_USER_PAYLOAD_SIZE 2 + +/* Device type for sync device needed for device discovery */ +#define CAM_SYNC_DEVICE_TYPE (MEDIA_ENT_F_OLD_BASE) + +#define CAM_SYNC_GET_PAYLOAD_PTR(ev, type) \ + (type *)((char *)ev.u.data + sizeof(struct cam_sync_ev_header)) + +#define CAM_SYNC_GET_HEADER_PTR(ev) \ + ((struct cam_sync_ev_header *)ev.u.data) + +#define CAM_SYNC_STATE_INVALID 0 +#define CAM_SYNC_STATE_ACTIVE 1 +#define CAM_SYNC_STATE_SIGNALED_SUCCESS 2 +#define CAM_SYNC_STATE_SIGNALED_ERROR 3 + +/** + * struct cam_sync_ev_header - Event header for sync event notification + * + * @sync_obj: Sync object + * @status: Status of the object + */ +struct cam_sync_ev_header { + int32_t sync_obj; + int32_t status; +}; + +/** + * struct cam_sync_info - Sync object creation information + * + * @name: Optional string representation of the sync object + * @sync_obj: Sync object returned after creation in kernel + */ +struct cam_sync_info { + char name[64]; + int32_t sync_obj; +}; + +/** + * struct cam_sync_signal - Sync object signaling struct + * + * @sync_obj: Sync object to be signaled + * @sync_state: State of the sync object to which it should be signaled + */ +struct cam_sync_signal { + int32_t sync_obj; + uint32_t sync_state; +}; + +/** + * struct cam_sync_merge - Merge information for sync objects + * + * @sync_objs: Pointer to sync objects + * @num_objs: Number of objects in the array + * @merged: Merged sync object + */ +struct cam_sync_merge { + __u64 sync_objs; + uint32_t num_objs; + int32_t merged; +}; + +/** + * struct cam_sync_userpayload_info - Payload info from user space + * + * @sync_obj: Sync object for which payload has to be registered for + * @reserved: Reserved + * @payload: Pointer to user payload + */ +struct cam_sync_userpayload_info { + int32_t sync_obj; + uint32_t reserved; + __u64 payload[CAM_SYNC_USER_PAYLOAD_SIZE]; +}; + +/** + * struct cam_sync_wait - Sync object wait information + * + * @sync_obj: Sync object to wait on + * @reserved: Reserved + * @timeout_ms: Timeout in milliseconds + */ +struct cam_sync_wait { + int32_t sync_obj; + uint32_t reserved; + uint64_t timeout_ms; +}; + +/** + * struct cam_private_ioctl_arg - Sync driver ioctl argument + * + * @id: IOCTL command id + * @size: Size of command payload + * @result: Result of command execution + * @reserved: Reserved + * @ioctl_ptr: Pointer to user data + */ +struct cam_private_ioctl_arg { + __u32 id; + __u32 size; + __u32 result; + __u32 reserved; + __u64 ioctl_ptr; +}; + +#define CAM_PRIVATE_IOCTL_CMD \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_private_ioctl_arg) + +#define CAM_SYNC_CREATE 0 +#define CAM_SYNC_DESTROY 1 +#define CAM_SYNC_SIGNAL 2 +#define CAM_SYNC_MERGE 3 +#define CAM_SYNC_REGISTER_PAYLOAD 4 +#define CAM_SYNC_DEREGISTER_PAYLOAD 5 +#define CAM_SYNC_WAIT 6 + +#endif /* __UAPI_CAM_SYNC_H__ */ diff --git a/techpack/camera-bengal/include/uapi/media/cam_tfe.h b/techpack/camera-bengal/include/uapi/media/cam_tfe.h new file mode 100644 index 0000000000000000000000000000000000000000..7da5493466b06a3fc350534700b3612ffe2b1012 --- /dev/null +++ b/techpack/camera-bengal/include/uapi/media/cam_tfe.h @@ -0,0 +1,396 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_TFE_H__ +#define __UAPI_CAM_TFE_H__ + +#include "cam_defs.h" +#include "cam_isp_tfe.h" +#include "cam_cpas.h" + + +/* ISP TFE driver name */ +#define CAM_ISP_TFE_DEV_NAME "cam-isp" + +/* HW type */ +#define CAM_ISP_TFE_HW_BASE 0 +#define CAM_ISP_TFE_HW_CSID 1 +#define CAM_ISP_TFE_HW_TFE 2 +#define CAM_ISP_TFE_HW_MAX 3 + +/* Color Pattern */ +#define CAM_ISP_TFE_PATTERN_BAYER_RGRGRG 0 +#define CAM_ISP_TFE_PATTERN_BAYER_GRGRGR 1 +#define CAM_ISP_TFE_PATTERN_BAYER_BGBGBG 2 +#define CAM_ISP_TFE_PATTERN_BAYER_GBGBGB 3 +#define CAM_ISP_TFE_PATTERN_YUV_YCBYCR 4 +#define CAM_ISP_TFE_PATTERN_YUV_YCRYCB 5 +#define CAM_ISP_TFE_PATTERN_YUV_CBYCRY 6 +#define CAM_ISP_TFE_PATTERN_YUV_CRYCBY 7 +#define CAM_ISP_TFE_PATTERN_MAX 8 + +/* Usage Type */ +#define CAM_ISP_TFE_IN_RES_USAGE_SINGLE 0 +#define CAM_ISP_TFE_IN_RES_USAGE_DUAL 1 +#define CAM_ISP_TFE_IN_RES_USAGE_MAX 2 + +/* Resource ID */ +#define CAM_ISP_TFE_RES_ID_PORT 0 +#define CAM_ISP_TFE_RES_ID_MAX 1 + +/* Resource Type - Type of resource for the resource id + * defined in cam_isp_tfe.h + */ + +/* Lane Type in input resource for Port */ +#define CAM_ISP_TFE_IN_LANE_TYPE_DPHY 0 +#define CAM_ISP_TFE_IN_LANE_TYPE_CPHY 1 +#define CAM_ISP_TFE_IN_LANE_TYPE_MAX 2 + +/* ISP TFE packet opcode */ +#define CAM_ISP_TFE_PACKET_OP_BASE 0 +#define CAM_ISP_TFE_PACKET_INIT_DEV 1 +#define CAM_ISP_TFE_PACKET_CONFIG_DEV 2 +#define CAM_ISP_TFE_PACKET_OP_MAX 3 + +/* ISP TFE packet meta_data type for command buffer */ +#define CAM_ISP_TFE_PACKET_META_BASE 0 +#define CAM_ISP_TFE_PACKET_META_LEFT 1 +#define CAM_ISP_TFE_PACKET_META_RIGHT 2 +#define CAM_ISP_TFE_PACKET_META_COMMON 3 +#define CAM_ISP_TFE_PACKET_META_DUAL_CONFIG 4 +#define CAM_ISP_TFE_PACKET_META_GENERIC_BLOB_COMMON 5 +#define CAM_ISP_TFE_PACKET_META_REG_DUMP_PER_REQUEST 6 +#define CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_FLUSH 7 +#define CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_ERROR 8 + +/* ISP TFE Generic Cmd Buffer Blob types */ +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_HFR_CONFIG 0 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_BW_CONFIG_V2 2 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG 3 + +/* DSP mode */ +#define CAM_ISP_TFE_DSP_MODE_NONE 0 +#define CAM_ISP_TFE_DSP_MODE_ONE_WAY 1 +#define CAM_ISP_TFE_DSP_MODE_ROUND 2 + +/* Per Path Usage Data */ +#define CAM_ISP_TFE_USAGE_INVALID 0 +#define CAM_ISP_TFE_USAGE_LEFT_PX 1 +#define CAM_ISP_TFE_USAGE_RIGHT_PX 2 +#define CAM_ISP_TFE_USAGE_RDI 3 + +/* Bus write master modes */ +#define CAM_ISP_TFE_WM_FRAME_BASED_MODE 0 +#define CAM_ISP_TFE_WM_LINE_BASED_MODE 1 +#define CAM_ISP_TFE_WM_INDEX_BASED_MODE 2 + +/* Query devices */ +/** + * struct cam_isp_tfe_dev_cap_info - A cap info for particular hw type + * + * @hw_type: Hardware type for the cap info + * @reserved: reserved field for alignment + * @hw_version: Hardware version + * + */ +struct cam_isp_tfe_dev_cap_info { + uint32_t hw_type; + uint32_t reserved; + struct cam_hw_version hw_version; +}; + +/** + * struct cam_isp_tfe_query_cap_cmd - ISP TFE query device + * capability payload + * + * @device_iommu: returned iommu handles for device + * @cdm_iommu: returned iommu handles for cdm + * @num_dev: returned number of device capabilities + * @reserved: reserved field for alignment + * @dev_caps: returned device capability array + * + */ +struct cam_isp_tfe_query_cap_cmd { + struct cam_iommu_handle device_iommu; + struct cam_iommu_handle cdm_iommu; + int32_t num_dev; + uint32_t reserved; + struct cam_isp_tfe_dev_cap_info dev_caps[CAM_ISP_TFE_HW_MAX]; +}; + +/* Acquire Device */ +/** + * struct cam_isp_tfe_out_port_info - An output port resource info + * + * @res_id: output resource id defined in file + * cam_isp_tfe.h + * @format: output format of the resource + * @width: output width in pixels + * @height: output height in lines + * @stride: output stride + * @comp_grp_id: composite group id for the resource. + * @secure_mode: flag to tell if output should be run in secure + * mode or not. See cam_defs.h for definition + * @wm_mode: wm mode + * @reserved: reserved field for alignment + * + */ +struct cam_isp_tfe_out_port_info { + uint32_t res_id; + uint32_t format; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t comp_grp_id; + uint32_t secure_mode; + uint32_t wm_mode; + uint32_t reserved; +}; + +/** + * struct cam_isp_tfe_in_port_info - An input port resource info + * + * @res_id: input resource id CAM_ISP_TFE_IN_RES_XXX + * @lane_type: lane type: c-phy or d-phy. + * @lane_num: active lane number + * @lane_cfg: lane configurations: 4 bits per lane + * @vc: input virtual channel number + * @dt: input data type number + * @format: input format + * @pix_pattern: pixel pattern + * @usage_type: whether dual tfe is required + * @left_start: left input start offset in pixels + * @left_end: left input stop offset in pixels + * @left_width: left input width in pixels + * @right_start: right input start offset in pixels. + * Only for Dual TFE + * @right_end: right input stop offset in + * pixels. Only for Dual TFE + * @right_width: right input width in pixels. + * Only for dual TFE + * @line_start: top of the line number + * @line_stop: bottome of the line number + * @height: input height in lines + * @batch_size: batch size for HFR mode + * @dsp_mode: DSP stream mode(Defines as + * CAM_ISP_TFE_DSP_MODE_*) + * @sensor_width: sensor width + * @sensor_height: sensor height + * @hbi_value: sensor HBI value + * @vbi_value: sensor VBI value + * @sensor_fps: sensor fps + * @init_frame_drop init frame drop value. + * @num_out_res: number of the output resource associated + * @data: payload that contains the output resources, + * array of cam_isp_tfe_out_port_info data + * + */ +struct cam_isp_tfe_in_port_info { + uint32_t res_id; + uint32_t lane_type; + uint32_t lane_num; + uint32_t lane_cfg; + uint32_t vc; + uint32_t dt; + uint32_t format; + uint32_t pix_pattern; + uint32_t usage_type; + uint32_t left_start; + uint32_t left_end; + uint32_t left_width; + uint32_t right_start; + uint32_t right_end; + uint32_t right_width; + uint32_t line_start; + uint32_t line_end; + uint32_t height; + uint32_t batch_size; + uint32_t dsp_mode; + uint32_t sensor_width; + uint32_t sensor_height; + uint32_t sensor_hbi; + uint32_t sensor_vbi; + uint32_t sensor_fps; + uint32_t init_frame_drop; + uint32_t num_out_res; + struct cam_isp_tfe_out_port_info data[1]; +}; + +/** + * struct cam_isp_tfe_resource - A resource bundle + * + * @resoruce_id: resource id for the resource bundle + * @length: length of the while resource blob + * @handle_type: type of the resource handle + * @reserved: reserved field for alignment + * @res_hdl: resource handle that points to the + * resource array + * + */ +struct cam_isp_tfe_resource { + uint32_t resource_id; + uint32_t length; + uint32_t handle_type; + uint32_t reserved; + uint64_t res_hdl; +}; + +/** + * struct cam_isp_tfe_port_hfr_config - HFR configuration for + * this port + * + * @resource_type: Resource type + * @subsample_pattern: Subsample pattern. Used in HFR mode. It + * should be consistent with batchSize and + * CAMIF programming. + * @subsample_period: Subsample period. Used in HFR mode. It + * should be consistent with batchSize and + * CAMIF programming. + * @framedrop_pattern: Framedrop pattern + * @framedrop_period: Framedrop period + * @reserved: Reserved for alignment + */ +struct cam_isp_tfe_port_hfr_config { + uint32_t resource_type; + uint32_t subsample_pattern; + uint32_t subsample_period; + uint32_t framedrop_pattern; + uint32_t framedrop_period; + uint32_t reserved; +} __attribute__((packed)); + +/** + * struct cam_isp_tfe_resource_hfr_config - Resource HFR + * configuration + * + * @num_ports: Number of ports + * @reserved: Reserved for alignment + * @port_hfr_config: HFR configuration for each IO port + */ +struct cam_isp_tfe_resource_hfr_config { + uint32_t num_ports; + uint32_t reserved; + struct cam_isp_tfe_port_hfr_config port_hfr_config[1]; +} __attribute__((packed)); + +/** + * struct cam_isp_tfe_dual_stripe_config - stripe config per bus + * client + * + * @offset: Start horizontal offset relative to + * output buffer + * @width: Width of the stripe in pixels + * @port_id: Port id of ISP TFE output + * @reserved: Reserved for alignment + * + */ +struct cam_isp_tfe_dual_stripe_config { + uint32_t offset; + uint32_t width; + uint32_t port_id; + uint32_t reserved; +}; + +/** + * struct cam_isp_tfe_dual_config - dual isp configuration + * + * @num_ports Number of isp output ports + * @reserved Reserved field for alignment + * @stripes: Stripe information + * + */ +struct cam_isp_tfe_dual_config { + uint32_t num_ports; + uint32_t reserved; + struct cam_isp_tfe_dual_stripe_config stripes[1]; +} __attribute__((packed)); + +/** + * struct cam_isp_tfe_clock_config - Clock configuration + * + * @usage_type: Usage type (Single/Dual) + * @num_rdi: Number of RDI votes + * @left_pix_hz: Pixel Clock for Left ISP + * @right_pix_hz: Pixel Clock for Right ISP + * valid only if Dual + * @rdi_hz: RDI Clock. ISP TFE clock will be + * max of RDI and PIX clocks. For a + * particular context which ISP TFE + * HW the RDI is allocated to is + * not known to UMD. Hence pass the + * clock and let KMD decide. + */ +struct cam_isp_tfe_clock_config { + uint32_t usage_type; + uint32_t num_rdi; + uint64_t left_pix_hz; + uint64_t right_pix_hz; + uint64_t rdi_hz[1]; +} __attribute__((packed)); + +/** + * struct cam_isp_tfe_csid_clock_config - CSID clock + * configuration + * + * @csid_clock CSID clock + * @csi_phy_clock Phy clock valid if tpg is selected + */ +struct cam_isp_tfe_csid_clock_config { + uint64_t csid_clock; + uint64_t phy_clock; +} __attribute__((packed)); + +/** + * struct cam_isp_tfe_bw_config_v2 - Bandwidth configuration + * + * @usage_type: Usage type (Single/Dual) + * @num_paths: Number of axi data paths + * @axi_path Per path vote info + */ +struct cam_isp_tfe_bw_config_v2 { + uint32_t usage_type; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[1]; +} __attribute__((packed)); + +/** + * struct cam_isp_acquire_hw_info - ISP TFE acquire HW params + * + * @common_info_version : Version of common info struct used + * @common_info_size : Size of common info struct used + * @common_info_offset : Offset of common info from start of data + * @num_inputs : Number of inputs + * @input_info_version : Version of input info struct used + * @input_info_size : Size of input info struct used + * @input_info_offset : Offset of input info from start of data + * @data : Data pointer to point the cam_isp_tfe_in_port_info + * structure + */ +struct cam_isp_tfe_acquire_hw_info { + uint16_t common_info_version; + uint16_t common_info_size; + uint32_t common_info_offset; + uint32_t num_inputs; + uint32_t input_info_version; + uint32_t input_info_size; + uint32_t input_info_offset; + uint64_t data; +}; + +#define CAM_TFE_ACQUIRE_COMMON_VER0 0x1000 + +#define CAM_TFE_ACQUIRE_COMMON_SIZE_VER0 0x0 + +#define CAM_TFE_ACQUIRE_INPUT_VER0 0x2000 + +#define CAM_TFE_ACQUIRE_INPUT_SIZE_VER0 sizeof(struct cam_isp_tfe_in_port_info) + +#define CAM_TFE_ACQUIRE_OUT_VER0 0x3000 + +#define CAM_TFE_ACQUIRE_OUT_SIZE_VER0 sizeof(struct cam_isp_tfe_out_port_info) + +#endif /* __UAPI_CAM_TFE_H__ */ diff --git a/techpack/data/drivers/rmnet/perf/rmnet_perf_opt.c b/techpack/data/drivers/rmnet/perf/rmnet_perf_opt.c index d6b21f75dc2a8015d866444928e48d13a887d1a5..bd95f57a52571a9b010419e7cd169272f2987051 100644 --- a/techpack/data/drivers/rmnet/perf/rmnet_perf_opt.c +++ b/techpack/data/drivers/rmnet/perf/rmnet_perf_opt.c @@ -712,7 +712,7 @@ void rmnet_perf_opt_insert_pkt_in_flow( flow_node->next_seq += payload_len; } void -rmnet_perf_free_hash_table() +rmnet_perf_free_hash_table(void) { int i; struct rmnet_perf_opt_flow_node *flow_node; diff --git a/techpack/display/msm/dp/dp_audio.c b/techpack/display/msm/dp/dp_audio.c index 90c3ad16dba6245475fe600421d7fdac044cd5a8..bbbcaba0acefe2d11e0d1307fc3c5048b285fa46 100644 --- a/techpack/display/msm/dp/dp_audio.c +++ b/techpack/display/msm/dp/dp_audio.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -292,11 +293,19 @@ static void dp_audio_isrc_sdp(struct dp_audio_private *audio) static void dp_audio_setup_sdp(struct dp_audio_private *audio) { + struct sde_edid_ctrl *edid; + if (!atomic_read(&audio->session_on)) { DP_WARN("session inactive\n"); return; } + if (!audio->panel || !audio->panel->edid_ctrl) { + DP_ERR("Invalid panel data."); + return; + } + edid = audio->panel->edid_ctrl; + /* always program stream 0 first before actual stream cfg */ audio->catalog->stream_id = DP_STREAM_0; audio->catalog->config_sdp(audio->catalog); @@ -309,8 +318,14 @@ static void dp_audio_setup_sdp(struct dp_audio_private *audio) dp_audio_stream_sdp(audio); dp_audio_timestamp_sdp(audio); dp_audio_infoframe_sdp(audio); - dp_audio_copy_management_sdp(audio); - dp_audio_isrc_sdp(audio); + + DP_DEBUG("Sink supports ACP and ISRC: %d", + edid->hdmi_vsdb.supports_ai); + + if (edid->hdmi_vsdb.supports_ai) { + dp_audio_copy_management_sdp(audio); + dp_audio_isrc_sdp(audio); + } } static void dp_audio_setup_acr(struct dp_audio_private *audio) diff --git a/techpack/display/msm/msm_drv.c b/techpack/display/msm/msm_drv.c index 43e94d5b2cd6d48b61e79db72a1dccb116ead340..dc81dfaa74ce111e9639a77411a5945927af9cb0 100644 --- a/techpack/display/msm/msm_drv.c +++ b/techpack/display/msm/msm_drv.c @@ -1,3 +1,6 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat @@ -39,6 +42,7 @@ #include #include +#include #include #include @@ -68,6 +72,9 @@ #define MSM_VERSION_MINOR 3 #define MSM_VERSION_PATCHLEVEL 0 +#define IDLE_ENCODER_MASK_DEFAULT 1 +#define IDLE_TIMEOUT_MS_DEFAULT 100 + static DEFINE_MUTEX(msm_release_lock); static void msm_fb_output_poll_changed(struct drm_device *dev) @@ -722,6 +729,160 @@ static struct msm_kms *_msm_drm_init_helper(struct msm_drm_private *priv, return kms; } +static ssize_t idle_encoder_mask_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(device); + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + u32 encoder_mask = 0; + int rc; + unsigned long flags; + + rc = kstrtouint(buf, 0, &encoder_mask); + if (rc) + return rc; + + spin_lock_irqsave(&idle->lock, flags); + idle->encoder_mask = encoder_mask; + idle->active_mask &= encoder_mask; + spin_unlock_irqrestore(&idle->lock, flags); + + return count; +} + +static ssize_t idle_encoder_mask_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(device); + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + + return snprintf(buf, PAGE_SIZE, "0x%x\n", idle->encoder_mask); +} + +static ssize_t idle_timeout_ms_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(device); + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + u32 timeout_ms = 0; + int rc; + unsigned long flags; + + rc = kstrtouint(buf, 10, &timeout_ms); + if (rc) + return rc; + + spin_lock_irqsave(&idle->lock, flags); + idle->timeout_ms = timeout_ms; + spin_unlock_irqrestore(&idle->lock, flags); + + return count; +} + +static ssize_t idle_timeout_ms_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(device); + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + + return scnprintf(buf, PAGE_SIZE, "%d\n", idle->timeout_ms); +} + +static ssize_t idle_state_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(device); + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + const char *state; + unsigned long flags; + + spin_lock_irqsave(&idle->lock, flags); + if (idle->active_mask) { + state = "active"; + spin_unlock_irqrestore(&idle->lock, flags); + return scnprintf(buf, PAGE_SIZE, "%s (0x%x)\n", + state, idle->active_mask); + } else if (delayed_work_pending(&idle->work)) + state = "pending"; + else + state = "idle"; + spin_unlock_irqrestore(&idle->lock, flags); + + return scnprintf(buf, PAGE_SIZE, "%s\n", state); +} + +static DEVICE_ATTR_RW(idle_encoder_mask); +static DEVICE_ATTR_RW(idle_timeout_ms); +static DEVICE_ATTR_RO(idle_state); + +static const struct attribute *msm_idle_attrs[] = { + &dev_attr_idle_encoder_mask.attr, + &dev_attr_idle_timeout_ms.attr, + &dev_attr_idle_state.attr, + NULL +}; + +static void msm_idle_work(struct work_struct *work) +{ + struct delayed_work *dw = to_delayed_work(work); + struct msm_idle *idle = container_of(dw, struct msm_idle, work); + struct msm_drm_private *priv = container_of(idle, + struct msm_drm_private, idle); + + if (!idle->active_mask) + sysfs_notify(&priv->dev->dev->kobj, NULL, "idle_state"); +} + +void msm_idle_set_state(struct drm_encoder *encoder, bool active) +{ + struct drm_device *ddev = encoder->dev; + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + unsigned int mask = 1 << drm_encoder_index(encoder); + unsigned long flags; + + spin_lock_irqsave(&idle->lock, flags); + if (mask & idle->encoder_mask) { + if (active) + idle->active_mask |= mask; + else + idle->active_mask &= ~mask; + + if (idle->timeout_ms && !idle->active_mask) + mod_delayed_work(system_wq, &idle->work, + msecs_to_jiffies(idle->timeout_ms)); + else + cancel_delayed_work(&idle->work); + } + spin_unlock_irqrestore(&idle->lock, flags); +} + +static void msm_idle_init(struct drm_device *ddev) +{ + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + + if (sysfs_create_files(&ddev->dev->kobj, msm_idle_attrs) < 0) + pr_warn("failed to create idle state file"); + + idle->active_mask = 0; + idle->encoder_mask = IDLE_ENCODER_MASK_DEFAULT; + idle->timeout_ms = IDLE_TIMEOUT_MS_DEFAULT; + + INIT_DELAYED_WORK(&idle->work, msm_idle_work); + spin_lock_init(&idle->lock); +} + static int msm_drm_init(struct device *dev, struct drm_driver *drv) { struct platform_device *pdev = to_platform_device(dev); @@ -772,6 +933,8 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) goto dbg_init_fail; } + msm_idle_init(ddev); + /* Bind all our sub-components: */ ret = msm_component_bind_all(dev, ddev); if (ret) @@ -867,6 +1030,7 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) kfree(priv); priv_alloc_fail: drm_dev_put(ddev); + platform_set_drvdata(pdev, NULL); return ret; } diff --git a/techpack/display/msm/msm_drv.h b/techpack/display/msm/msm_drv.h index be832ad3f39a414dc5f73cad3db909fd95c93c8e..a5748bba7c33776cacf09d2dd86c520b5c873750 100644 --- a/techpack/display/msm/msm_drv.h +++ b/techpack/display/msm/msm_drv.h @@ -607,6 +607,15 @@ struct msm_drm_thread { struct kthread_worker worker; }; +struct msm_idle { + u32 timeout_ms; + u32 encoder_mask; + u32 active_mask; + + spinlock_t lock; + struct delayed_work work; +}; + struct msm_drm_private { struct drm_device *dev; @@ -721,6 +730,8 @@ struct msm_drm_private { /* update the flag when msm driver receives shutdown notification */ bool shutdown_in_progress; + + struct msm_idle idle; }; /* get struct msm_kms * from drm_device * */ @@ -987,6 +998,7 @@ static inline void __exit msm_mdp_unregister(void) } #endif +void msm_idle_set_state(struct drm_encoder *encoder, bool active); #ifdef CONFIG_DEBUG_FS void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); diff --git a/techpack/display/msm/sde/sde_encoder.c b/techpack/display/msm/sde/sde_encoder.c index 0bd39b44ea0664595d5d82caed4389c2a091e39a..68e4ae47862aaa8a24220ce033dbd3d1c2011243 100644 --- a/techpack/display/msm/sde/sde_encoder.c +++ b/techpack/display/msm/sde/sde_encoder.c @@ -2442,6 +2442,8 @@ static int _sde_encoder_rc_kickoff(struct drm_encoder *drm_enc, /* cancel delayed off work, if any */ _sde_encoder_rc_cancel_delayed(sde_enc, sw_event); + msm_idle_set_state(drm_enc, true); + mutex_lock(&sde_enc->rc_lock); /* return if the resource control is already in ON state */ @@ -2551,6 +2553,8 @@ static int _sde_encoder_rc_frame_done(struct drm_encoder *drm_enc, else idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION; + msm_idle_set_state(drm_enc, false); + if (!autorefresh_enabled) kthread_mod_delayed_work( &disp_thread->worker, diff --git a/techpack/display/msm/sde_edid_parser.c b/techpack/display/msm/sde_edid_parser.c index 0fc473da9f87a11f3f29037d9aef4f31c0c6b4df..961f351c39a1aa599f7abe20bace8e93e270e854 100644 --- a/techpack/display/msm/sde_edid_parser.c +++ b/techpack/display/msm/sde_edid_parser.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -86,6 +87,21 @@ for ((i) = (start); \ (i) < (end) && (i) + sde_cea_db_payload_len(&(cea)[(i)]) < (end); \ (i) += sde_cea_db_payload_len(&(cea)[(i)]) + 1) +static bool sde_cea_db_is_hdmi_vsdb(const u8 *db) +{ + int hdmi_id; + + if (sde_cea_db_tag(db) != VENDOR_SPECIFIC_DATA_BLOCK) + return false; + + if (sde_cea_db_payload_len(db) < 6) + return false; + + hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); + + return hdmi_id == HDMI_IEEE_OUI; +} + static bool sde_cea_db_is_hdmi_hf_vsdb(const u8 *db) { int hdmi_id; @@ -519,6 +535,46 @@ struct sde_edid_ctrl *sde_edid_init(void) return edid_ctrl; } +static void _sde_edid_extract_hdmi_vsdb_block( + struct sde_edid_ctrl *edid_ctrl) +{ + int i, start, end; + u8 *cea, *hdmi; + + memset(&edid_ctrl->hdmi_vsdb, 0, sizeof(edid_ctrl->hdmi_vsdb)); + + SDE_EDID_DEBUG("%s +\n", __func__); + + if (!edid_ctrl) { + SDE_ERROR("invalid input\n"); + goto out; + } + + cea = sde_find_cea_extension(edid_ctrl->edid); + + if (!cea) { + SDE_DEBUG("no cea extension\n"); + goto out; + } + + if (sde_cea_db_offsets(cea, &start, &end)) + goto out; + + sde_for_each_cea_db(cea, i, start, end) { + if (sde_cea_db_is_hdmi_vsdb(&cea[i])) { + hdmi = &cea[i]; + edid_ctrl->hdmi_vsdb.supports_ai = hdmi[6] & BIT(7); + SDE_DEBUG("HDMI VSDB block present"); + break; + } + } + + return; +out: + SDE_DEBUG("HDMI VSDB block NOT present."); +} + + void sde_free_edid(void **input) { struct sde_edid_ctrl *edid_ctrl = (struct sde_edid_ctrl *)(*input); @@ -607,6 +663,7 @@ void sde_parse_edid(void *input) sde_edid_extract_vendor_id(edid_ctrl); _sde_edid_extract_audio_data_blocks(edid_ctrl); _sde_edid_extract_speaker_allocation_data(edid_ctrl); + _sde_edid_extract_hdmi_vsdb_block(edid_ctrl); } else { SDE_ERROR("edid not present\n"); } diff --git a/techpack/display/msm/sde_edid_parser.h b/techpack/display/msm/sde_edid_parser.h index 6501f329d57f7ded1139a6f035ddb425b0666289..b07cb3e94e0590578fe58c66f1e160f16bf44438 100644 --- a/techpack/display/msm/sde_edid_parser.h +++ b/techpack/display/msm/sde_edid_parser.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _SDE_EDID_PARSER_H_ @@ -44,6 +45,13 @@ enum extended_data_block_types { #define SDE_EDID_DEBUG(fmt, args...) SDE_DEBUG(fmt, ##args) #endif +/* TODO: Add respective extension fields of HDMI VSDB block. + * Fields shall be populated using "sde_edid_extract_hdmi_vsdb_block" function. + */ +struct sink_hdmi_vsdb_block { + bool supports_ai; +}; + /* * struct hdmi_edid_hdr_data - HDR Static Metadata * @eotf: Electro-Optical Transfer Function @@ -83,6 +91,7 @@ struct sde_edid_ctrl { char vendor_id[EDID_VENDOR_ID_SIZE]; struct sde_edid_sink_caps sink_caps; struct sde_edid_hdr_data hdr_data; + struct sink_hdmi_vsdb_block hdmi_vsdb; }; /** diff --git a/techpack/video/msm/vidc/hfi_iris2.c b/techpack/video/msm/vidc/hfi_iris2.c index 179fb2abaefbf4f8b70fca5c7afe32c7cb9f9ecc..0f16e9b0044fe588b4d527b5ef2cea7acb4a4401 100644 --- a/techpack/video/msm/vidc/hfi_iris2.c +++ b/techpack/video/msm/vidc/hfi_iris2.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ +#include #include "msm_vidc_debug.h" #include "hfi_common.h" @@ -167,9 +168,9 @@ void __setup_ucregion_memory_map_iris2(struct venus_hfi_device *device, u32 sid) (u32)device->qdss.align_device_addr, sid); /* update queues vaddr for debug purpose */ __write_register(device, CPU_CS_VCICMDARG0_IRIS2, - (u32)device->iface_q_table.align_virtual_addr, sid); + (u32)((uintptr_t)device->iface_q_table.align_virtual_addr & UINT_MAX), sid); __write_register(device, CPU_CS_VCICMDARG1_IRIS2, - (u32)((u64)device->iface_q_table.align_virtual_addr >> 32), + (u32)((uintptr_t)device->iface_q_table.align_virtual_addr >> 32), sid); } diff --git a/techpack/video/msm/vidc/msm_v4l2_vidc.c b/techpack/video/msm/vidc/msm_v4l2_vidc.c index 5f6a82acd47f74f7f27928adfd16f281eb42ed7b..fe2aa0c9911f45c377eb98c9d520514b0db9a435 100644 --- a/techpack/video/msm/vidc/msm_v4l2_vidc.c +++ b/techpack/video/msm/vidc/msm_v4l2_vidc.c @@ -584,8 +584,10 @@ static int msm_vidc_probe_vidc_device(struct platform_device *pdev) list_add_tail(&core->list, &vidc_driver->cores); mutex_unlock(&vidc_driver->lock); +#ifdef CONFIG_DEBUG_FS core->debugfs_root = msm_vidc_debugfs_init_core( core, vidc_driver->debugfs_root); +#endif vidc_driver->sku_version = core->resources.sku_version; @@ -784,9 +786,12 @@ static int __init msm_vidc_init(void) INIT_LIST_HEAD(&vidc_driver->cores); mutex_init(&vidc_driver->lock); + +#ifdef CONFIG_DEBUG_FS vidc_driver->debugfs_root = msm_vidc_debugfs_init_drv(); if (!vidc_driver->debugfs_root) d_vpr_e("Failed to create debugfs for msm_vidc\n"); +#endif rc = platform_driver_register(&msm_vidc_driver); if (rc) { diff --git a/techpack/video/msm/vidc/msm_venc.c b/techpack/video/msm/vidc/msm_venc.c index 60b7cc734f39ac386ce4cf4d3bd71de3639fefce..69c26c565e021b14f06a6ca76742dfcae3c2d5a3 100644 --- a/techpack/video/msm/vidc/msm_venc.c +++ b/techpack/video/msm/vidc/msm_venc.c @@ -2884,7 +2884,7 @@ int msm_venc_set_frame_qp(struct msm_vidc_inst *inst) * Enable QP types which have been set by client. * When RC is OFF: * I_QP value must be set by client. - * If other QP value is invalid, then, assign I_QP value to it. + * If QP value is invalid, then, assign default QP. */ if (inst->rc_type != RATE_CONTROL_OFF) { if (!(inst->client_set_ctrls & CLIENT_SET_I_QP)) @@ -2900,7 +2900,7 @@ int msm_venc_set_frame_qp(struct msm_vidc_inst *inst) if (!(inst->client_set_ctrls & CLIENT_SET_I_QP)) { s_vpr_e(inst->sid, "%s: Client value is not valid\n", __func__); - return -EINVAL; + i_qp->val = DEFAULT_QP; } if (!(inst->client_set_ctrls & CLIENT_SET_P_QP)) p_qp->val = i_qp->val; @@ -4628,6 +4628,13 @@ int handle_all_intra_restrictions(struct msm_vidc_inst *inst) fps_max = capability->cap[CAP_ALLINTRA_MAX_FPS].max; s_vpr_h(inst->sid, "%s: rc_type %u, fps %u, fps_max %u\n", __func__, inst->rc_type, n_fps, fps_max); + if (inst->all_intra && n_fps > fps_max) { + inst->clk_data.frame_rate = fps_max << 16; + n_fps = fps_max; + s_vpr_h(inst->sid, + "%s:cap2 frame rate to %u for allintra encoding", + __func__, inst->clk_data.frame_rate >> 16); + } if ((inst->rc_type != V4L2_MPEG_VIDEO_BITRATE_MODE_VBR && inst->rc_type != RATE_CONTROL_OFF && inst->rc_type != RATE_CONTROL_LOSSLESS) || diff --git a/techpack/video/msm/vidc/msm_vidc.c b/techpack/video/msm/vidc/msm_vidc.c index cbb46852cbb9c3278cc9a8473d6f14547ea3528a..23ca574b6adda0080fa1b81473e0bcaf4a6e5c13 100644 --- a/techpack/video/msm/vidc/msm_vidc.c +++ b/techpack/video/msm/vidc/msm_vidc.c @@ -1543,8 +1543,10 @@ void *msm_vidc_open(int core_id, int session_type) msm_comm_scale_clocks_and_bus(inst, 1); +#ifdef CONFIG_DEBUG_FS inst->debugfs_root = msm_vidc_debugfs_init_inst(inst, core->debugfs_root); +#endif if (inst->session_type == MSM_VIDC_CVP) { rc = msm_comm_try_state(inst, MSM_VIDC_OPEN_DONE); diff --git a/techpack/video/msm/vidc/msm_vidc_common.c b/techpack/video/msm/vidc/msm_vidc_common.c index b7b23fd587530e69a52866cd6f00d644d71082c6..9152fcfc4f0abbc982a2e21c76160843e3ec71dd 100644 --- a/techpack/video/msm/vidc/msm_vidc_common.c +++ b/techpack/video/msm/vidc/msm_vidc_common.c @@ -5928,7 +5928,7 @@ int msm_comm_check_memory_supported(struct msm_vidc_inst *vidc_inst) "%s: video mem overshoot - reached %llu MB, max_limit %llu MB\n", __func__, total_mem_size >> 20, memory_limit_mbytes); msm_comm_print_insts_info(core); - return -EBUSY; + return -ENOMEM; } if (!is_secure_session(vidc_inst)) { @@ -5943,7 +5943,7 @@ int msm_comm_check_memory_supported(struct msm_vidc_inst *vidc_inst) "%s: insufficient device addr space, required %llu, available %llu\n", __func__, non_sec_mem_size, non_sec_cb_size); msm_comm_print_insts_info(core); - return -EINVAL; + return -ENOMEM; } } diff --git a/tools/bpf/bpftool/json_writer.c b/tools/bpf/bpftool/json_writer.c index c6eef76322ae915ff5b88295b6f153dafb0ddd7d..0c38c41269beebea7287840828c7fe54deaf2203 100644 --- a/tools/bpf/bpftool/json_writer.c +++ b/tools/bpf/bpftool/json_writer.c @@ -84,9 +84,6 @@ static void jsonw_puts(json_writer_t *self, const char *str) case '"': fputs("\\\"", self->out); break; - case '\'': - fputs("\\\'", self->out); - break; default: putc(*str, self->out); } diff --git a/tools/bpf/bpftool/xlated_dumper.c b/tools/bpf/bpftool/xlated_dumper.c index 3284759df98ad4f325b25f719db0cfef7ac9f61c..7f49347bf5aa48a4fe83262566863e85a13115d2 100644 --- a/tools/bpf/bpftool/xlated_dumper.c +++ b/tools/bpf/bpftool/xlated_dumper.c @@ -336,8 +336,15 @@ void dump_xlated_for_graph(struct dump_data *dd, void *buf_start, void *buf_end, struct bpf_insn *insn_start = buf_start; struct bpf_insn *insn_end = buf_end; struct bpf_insn *cur = insn_start; + bool double_insn = false; for (; cur <= insn_end; cur++) { + if (double_insn) { + double_insn = false; + continue; + } + double_insn = cur->code == (BPF_LD | BPF_IMM | BPF_DW); + printf("% 4d: ", (int)(cur - insn_start + start_idx)); print_bpf_insn(&cbs, cur, true); if (cur != insn_end) diff --git a/tools/iio/iio_generic_buffer.c b/tools/iio/iio_generic_buffer.c index 84545666a09c4d05ad643aba1e5f55911fcd5a52..ca9f33fa51c9fc8b043763768ef380a3c2965220 100644 --- a/tools/iio/iio_generic_buffer.c +++ b/tools/iio/iio_generic_buffer.c @@ -53,12 +53,15 @@ enum autochan { * Has the side effect of filling the channels[i].location values used * in processing the buffer output. **/ -int size_from_channelarray(struct iio_channel_info *channels, int num_channels) +static unsigned int size_from_channelarray(struct iio_channel_info *channels, int num_channels) { - int bytes = 0; - int i = 0; + unsigned int bytes = 0; + int i = 0, max = 0; + unsigned int misalignment; while (i < num_channels) { + if (channels[i].bytes > max) + max = channels[i].bytes; if (bytes % channels[i].bytes == 0) channels[i].location = bytes; else @@ -68,11 +71,19 @@ int size_from_channelarray(struct iio_channel_info *channels, int num_channels) bytes = channels[i].location + channels[i].bytes; i++; } + /* + * We want the data in next sample to also be properly aligned so + * we'll add padding at the end if needed. Adding padding only + * works for channel data which size is 2^n bytes. + */ + misalignment = bytes % max; + if (misalignment) + bytes += max - misalignment; return bytes; } -void print1byte(uint8_t input, struct iio_channel_info *info) +static void print1byte(uint8_t input, struct iio_channel_info *info) { /* * Shift before conversion to avoid sign extension @@ -89,7 +100,7 @@ void print1byte(uint8_t input, struct iio_channel_info *info) } } -void print2byte(uint16_t input, struct iio_channel_info *info) +static void print2byte(uint16_t input, struct iio_channel_info *info) { /* First swap if incorrect endian */ if (info->be) @@ -112,7 +123,7 @@ void print2byte(uint16_t input, struct iio_channel_info *info) } } -void print4byte(uint32_t input, struct iio_channel_info *info) +static void print4byte(uint32_t input, struct iio_channel_info *info) { /* First swap if incorrect endian */ if (info->be) @@ -135,7 +146,7 @@ void print4byte(uint32_t input, struct iio_channel_info *info) } } -void print8byte(uint64_t input, struct iio_channel_info *info) +static void print8byte(uint64_t input, struct iio_channel_info *info) { /* First swap if incorrect endian */ if (info->be) @@ -171,9 +182,8 @@ void print8byte(uint64_t input, struct iio_channel_info *info) * to fill the location offsets. * @num_channels: number of channels **/ -void process_scan(char *data, - struct iio_channel_info *channels, - int num_channels) +static void process_scan(char *data, struct iio_channel_info *channels, + int num_channels) { int k; @@ -242,7 +252,7 @@ static int enable_disable_all_channels(char *dev_dir_name, int enable) return 0; } -void print_usage(void) +static void print_usage(void) { fprintf(stderr, "Usage: generic_buffer [options]...\n" "Capture, convert and output data from IIO device buffer\n" @@ -261,12 +271,12 @@ void print_usage(void) " -w Set delay between reads in us (event-less mode)\n"); } -enum autochan autochannels = AUTOCHANNELS_DISABLED; -char *dev_dir_name = NULL; -char *buf_dir_name = NULL; -bool current_trigger_set = false; +static enum autochan autochannels = AUTOCHANNELS_DISABLED; +static char *dev_dir_name = NULL; +static char *buf_dir_name = NULL; +static bool current_trigger_set = false; -void cleanup(void) +static void cleanup(void) { int ret; @@ -298,14 +308,14 @@ void cleanup(void) } } -void sig_handler(int signum) +static void sig_handler(int signum) { fprintf(stderr, "Caught signal %d\n", signum); cleanup(); exit(-signum); } -void register_cleanup(void) +static void register_cleanup(void) { struct sigaction sa = { .sa_handler = sig_handler }; const int signums[] = { SIGINT, SIGTERM, SIGABRT }; @@ -347,7 +357,7 @@ int main(int argc, char **argv) ssize_t read_size; int dev_num = -1, trig_num = -1; char *buffer_access = NULL; - int scan_size; + unsigned int scan_size; int noevents = 0; int notrigger = 0; char *dummy; @@ -617,7 +627,16 @@ int main(int argc, char **argv) } scan_size = size_from_channelarray(channels, num_channels); - data = malloc(scan_size * buf_len); + + size_t total_buf_len = scan_size * buf_len; + + if (scan_size > 0 && total_buf_len / scan_size != buf_len) { + ret = -EFAULT; + perror("Integer overflow happened when calculate scan_size * buf_len"); + goto error; + } + + data = malloc(total_buf_len); if (!data) { ret = -ENOMEM; goto error; diff --git a/tools/iio/iio_utils.c b/tools/iio/iio_utils.c index d60a252577f0b0d77c91b4dc30fd52a139b48d81..d174487b2f2264398260fa4408a741be11fddef2 100644 --- a/tools/iio/iio_utils.c +++ b/tools/iio/iio_utils.c @@ -265,6 +265,7 @@ int iioutils_get_param_float(float *output, const char *param_name, if (fscanf(sysfsfp, "%f", output) != 1) ret = errno ? -errno : -ENODATA; + fclose(sysfsfp); break; } error_free_filename: @@ -345,9 +346,9 @@ int build_channel_array(const char *device_dir, } sysfsfp = fopen(filename, "r"); + free(filename); if (!sysfsfp) { ret = -errno; - free(filename); goto error_close_dir; } @@ -357,7 +358,6 @@ int build_channel_array(const char *device_dir, if (fclose(sysfsfp)) perror("build_channel_array(): Failed to close file"); - free(filename); goto error_close_dir; } if (ret == 1) @@ -365,11 +365,9 @@ int build_channel_array(const char *device_dir, if (fclose(sysfsfp)) { ret = -errno; - free(filename); goto error_close_dir; } - free(filename); } *ci_array = malloc(sizeof(**ci_array) * (*counter)); @@ -395,9 +393,9 @@ int build_channel_array(const char *device_dir, } sysfsfp = fopen(filename, "r"); + free(filename); if (!sysfsfp) { ret = -errno; - free(filename); count--; goto error_cleanup_array; } @@ -405,20 +403,17 @@ int build_channel_array(const char *device_dir, errno = 0; if (fscanf(sysfsfp, "%i", ¤t_enabled) != 1) { ret = errno ? -errno : -ENODATA; - free(filename); count--; goto error_cleanup_array; } if (fclose(sysfsfp)) { ret = -errno; - free(filename); count--; goto error_cleanup_array; } if (!current_enabled) { - free(filename); count--; continue; } @@ -429,7 +424,6 @@ int build_channel_array(const char *device_dir, strlen(ent->d_name) - strlen("_en")); if (!current->name) { - free(filename); ret = -ENOMEM; count--; goto error_cleanup_array; @@ -439,7 +433,6 @@ int build_channel_array(const char *device_dir, ret = iioutils_break_up_name(current->name, ¤t->generic_name); if (ret) { - free(filename); free(current->name); count--; goto error_cleanup_array; @@ -450,17 +443,16 @@ int build_channel_array(const char *device_dir, scan_el_dir, current->name); if (ret < 0) { - free(filename); ret = -ENOMEM; goto error_cleanup_array; } sysfsfp = fopen(filename, "r"); + free(filename); if (!sysfsfp) { ret = -errno; - fprintf(stderr, "failed to open %s\n", - filename); - free(filename); + fprintf(stderr, "failed to open %s/%s_index\n", + scan_el_dir, current->name); goto error_cleanup_array; } @@ -470,17 +462,14 @@ int build_channel_array(const char *device_dir, if (fclose(sysfsfp)) perror("build_channel_array(): Failed to close file"); - free(filename); goto error_cleanup_array; } if (fclose(sysfsfp)) { ret = -errno; - free(filename); goto error_cleanup_array; } - free(filename); /* Find the scale */ ret = iioutils_get_param_float(¤t->scale, "scale", diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h index 8658af518bdab4093baa386c2becd772c89a16db..0fe33356c251913f2c88526e61975a1235f67222 100644 --- a/tools/include/uapi/linux/bpf.h +++ b/tools/include/uapi/linux/bpf.h @@ -693,7 +693,9 @@ union bpf_attr { * performed again, if the helper is used in combination with * direct packet access. * Return - * 0 on success, or a negative error in case of failure. + * 0 on success, or a negative error in case of failure. Positive + * error indicates a potential drop or congestion in the target + * device. The particular positive error codes are not defined. * * u64 bpf_get_current_pid_tgid(void) * Return diff --git a/tools/lib/bpf/nlattr.c b/tools/lib/bpf/nlattr.c index 4719434278b20aac7147013f1636eb3362248d5c..ac979b4290559e4a895571061585f8fd1279f442 100644 --- a/tools/lib/bpf/nlattr.c +++ b/tools/lib/bpf/nlattr.c @@ -170,7 +170,7 @@ int nla_dump_errormsg(struct nlmsghdr *nlh) hlen += nlmsg_len(&err->msg); attr = (struct nlattr *) ((void *) err + hlen); - alen = nlh->nlmsg_len - hlen; + alen = (void *)nlh + nlh->nlmsg_len - (void *)attr; if (nla_parse(tb, NLMSGERR_ATTR_MAX, attr, alen, extack_policy) != 0) { fprintf(stderr, diff --git a/tools/perf/builtin-sched.c b/tools/perf/builtin-sched.c index cbf39dab19c1a570fa4f988aeec1aab64f918a9d..4562e3b2f4d36dd949e34a60f83f78800d69fbef 100644 --- a/tools/perf/builtin-sched.c +++ b/tools/perf/builtin-sched.c @@ -659,7 +659,7 @@ static void create_tasks(struct perf_sched *sched) err = pthread_attr_init(&attr); BUG_ON(err); err = pthread_attr_setstacksize(&attr, - (size_t) max(16 * 1024, PTHREAD_STACK_MIN)); + (size_t) max(16 * 1024, (int)PTHREAD_STACK_MIN)); BUG_ON(err); err = pthread_mutex_lock(&sched->start_work_mutex); BUG_ON(err); diff --git a/tools/perf/perf-completion.sh b/tools/perf/perf-completion.sh index fdf75d45efff7a413347d215851f93f2a8f5bfb3..978249d7868c22e875720e73550eaf0897999c64 100644 --- a/tools/perf/perf-completion.sh +++ b/tools/perf/perf-completion.sh @@ -165,7 +165,12 @@ __perf_main () local cur1=${COMP_WORDS[COMP_CWORD]} local raw_evts=$($cmd list --raw-dump) - local arr s tmp result + local arr s tmp result cpu_evts + + # aarch64 doesn't have /sys/bus/event_source/devices/cpu/events + if [[ `uname -m` != aarch64 ]]; then + cpu_evts=$(ls /sys/bus/event_source/devices/cpu/events) + fi if [[ "$cur1" == */* && ${cur1#*/} =~ ^[A-Z] ]]; then OLD_IFS="$IFS" @@ -183,9 +188,9 @@ __perf_main () fi done - evts=${result}" "$(ls /sys/bus/event_source/devices/cpu/events) + evts=${result}" "${cpu_evts} else - evts=${raw_evts}" "$(ls /sys/bus/event_source/devices/cpu/events) + evts=${raw_evts}" "${cpu_evts} fi if [[ "$cur1" == , ]]; then diff --git a/tools/perf/pmu-events/arch/powerpc/power9/other.json b/tools/perf/pmu-events/arch/powerpc/power9/other.json index 48cf4f920b3ff09d8b7a17309a515fefa1f16a6d..064341c0df5750fc3df29ddde71e5c948262dd7d 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/other.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/other.json @@ -1417,7 +1417,7 @@ {, "EventCode": "0x45054", "EventName": "PM_FMA_CMPL", - "BriefDescription": "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only. " + "BriefDescription": "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only." }, {, "EventCode": "0x201E8", @@ -2017,7 +2017,7 @@ {, "EventCode": "0xC0BC", "EventName": "PM_LSU_FLUSH_OTHER", - "BriefDescription": "Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC); Data Valid Flush Next (several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data); Bad Data Valid Flush Next (might be a few cases of this, one example is a larxa (D$ hit) return data and dval but can't allocate to LMQ (LMQ full or other reason). Already gave dval but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops)" + "BriefDescription": "Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC); Data Valid Flush Next (several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data); Bad Data Valid Flush Next (might be a few cases of this, one example is a larxa (D$ hit) return data and dval but can't allocate to LMQ (LMQ full or other reason). Already gave dval but can't watch it for snoop_hit_larx. Need to take the 'bad dval' back and flush all younger ops)" }, {, "EventCode": "0x5094", diff --git a/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json b/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json index b4772f54a271890e22824dfc510b65ddaaf140ce..e2f2ed0a3549601e71f173fdec17fd33098d95e0 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json @@ -442,7 +442,7 @@ {, "EventCode": "0x4D052", "EventName": "PM_2FLOP_CMPL", - "BriefDescription": "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg " + "BriefDescription": "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg" }, {, "EventCode": "0x1F142", diff --git a/tools/perf/tests/shell/test_uprobe_from_different_cu.sh b/tools/perf/tests/shell/test_uprobe_from_different_cu.sh new file mode 100644 index 0000000000000000000000000000000000000000..319f36ebb9a40aebe0626f1dcb94488686f9a296 --- /dev/null +++ b/tools/perf/tests/shell/test_uprobe_from_different_cu.sh @@ -0,0 +1,83 @@ +#!/bin/bash +# test perf probe of function from different CU +# SPDX-License-Identifier: GPL-2.0 + +set -e + +# skip if there's no gcc +if ! [ -x "$(command -v gcc)" ]; then + echo "failed: no gcc compiler" + exit 2 +fi + +temp_dir=$(mktemp -d /tmp/perf-uprobe-different-cu-sh.XXXXXXXXXX) + +cleanup() +{ + trap - EXIT TERM INT + if [[ "${temp_dir}" =~ ^/tmp/perf-uprobe-different-cu-sh.*$ ]]; then + echo "--- Cleaning up ---" + perf probe -x ${temp_dir}/testfile -d foo || true + rm -f "${temp_dir}/"* + rmdir "${temp_dir}" + fi +} + +trap_cleanup() +{ + cleanup + exit 1 +} + +trap trap_cleanup EXIT TERM INT + +cat > ${temp_dir}/testfile-foo.h << EOF +struct t +{ + int *p; + int c; +}; + +extern int foo (int i, struct t *t); +EOF + +cat > ${temp_dir}/testfile-foo.c << EOF +#include "testfile-foo.h" + +int +foo (int i, struct t *t) +{ + int j, res = 0; + for (j = 0; j < i && j < t->c; j++) + res += t->p[j]; + + return res; +} +EOF + +cat > ${temp_dir}/testfile-main.c << EOF +#include "testfile-foo.h" + +static struct t g; + +int +main (int argc, char **argv) +{ + int i; + int j[argc]; + g.c = argc; + g.p = j; + for (i = 0; i < argc; i++) + j[i] = (int) argv[i][0]; + return foo (3, &g); +} +EOF + +gcc -g -Og -flto -c ${temp_dir}/testfile-foo.c -o ${temp_dir}/testfile-foo.o +gcc -g -Og -c ${temp_dir}/testfile-main.c -o ${temp_dir}/testfile-main.o +gcc -g -Og -o ${temp_dir}/testfile ${temp_dir}/testfile-foo.o ${temp_dir}/testfile-main.o + +perf probe -x ${temp_dir}/testfile --funcs foo +perf probe -x ${temp_dir}/testfile foo + +cleanup diff --git a/tools/perf/ui/browsers/hists.c b/tools/perf/ui/browsers/hists.c index ed34902022c1f33a231daf161db0f8e8113e01b2..31e07e4b54111b14a22e672c7a6c6e63448b3112 100644 --- a/tools/perf/ui/browsers/hists.c +++ b/tools/perf/ui/browsers/hists.c @@ -1704,7 +1704,7 @@ static void hists_browser__hierarchy_headers(struct hist_browser *browser) hists_browser__scnprintf_hierarchy_headers(browser, headers, sizeof(headers)); - ui_browser__gotorc(&browser->b, 0, 0); + ui_browser__gotorc_title(&browser->b, 0, 0); ui_browser__set_color(&browser->b, HE_COLORSET_ROOT); ui_browser__write_nstring(&browser->b, headers, browser->b.width + 1); } diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c index 1e607403c94c165fb49cccdad92c694129798104..5ae37a83dca3b39ee8eb4f896116f51b48e12d9c 100644 --- a/tools/perf/util/auxtrace.c +++ b/tools/perf/util/auxtrace.c @@ -1793,6 +1793,7 @@ static int find_entire_kern_cb(void *arg, const char *name __maybe_unused, char type, u64 start) { struct sym_args *args = arg; + u64 size; if (!kallsyms__is_function(type)) return 0; @@ -1802,7 +1803,9 @@ static int find_entire_kern_cb(void *arg, const char *name __maybe_unused, args->start = start; } /* Don't know exactly where the kernel ends, so we add a page */ - args->size = round_up(start, page_size) + page_size - args->start; + size = round_up(start, page_size) + page_size - args->start; + if (size > args->size) + args->size = size; return 0; } diff --git a/tools/perf/util/dwarf-aux.c b/tools/perf/util/dwarf-aux.c index 6de57d9ee7cc24d0de288352e4cae023c30d67cc..db099dc20a6821aaf0e8298d64bf394d4b1fea57 100644 --- a/tools/perf/util/dwarf-aux.c +++ b/tools/perf/util/dwarf-aux.c @@ -1020,7 +1020,7 @@ int die_get_varname(Dwarf_Die *vr_die, struct strbuf *buf) ret = die_get_typename(vr_die, buf); if (ret < 0) { pr_debug("Failed to get type, make it unknown.\n"); - ret = strbuf_add(buf, " (unknown_type)", 14); + ret = strbuf_add(buf, "(unknown_type)", 14); } return ret < 0 ? ret : strbuf_addf(buf, "\t%s", dwarf_diename(vr_die)); diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c index e2a6c22959f26dfb9141c97b8424c4aee4784807..aabd423785520678d8a3bdc7b684e393c03b8a51 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c +++ b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c @@ -1499,6 +1499,8 @@ static void intel_pt_calc_cbr(struct intel_pt_decoder *decoder) decoder->cbr = cbr; decoder->cbr_cyc_to_tsc = decoder->max_non_turbo_ratio_fp / cbr; + decoder->cyc_ref_timestamp = decoder->timestamp; + decoder->cycle_cnt = 0; } static void intel_pt_calc_cyc_timestamp(struct intel_pt_decoder *decoder) diff --git a/tools/perf/util/llvm-utils.c b/tools/perf/util/llvm-utils.c index 46ec9a1bb94cc7b0382de4a92a47ea4d9bbc0bd5..1ff4788bcb4e5e3bed0f46dd15eef8530f437609 100644 --- a/tools/perf/util/llvm-utils.c +++ b/tools/perf/util/llvm-utils.c @@ -521,14 +521,37 @@ int llvm__compile_bpf(const char *path, void **p_obj_buf, pr_debug("llvm compiling command template: %s\n", template); + /* + * Below, substitute control characters for values that can cause the + * echo to misbehave, then substitute the values back. + */ err = -ENOMEM; - if (asprintf(&command_echo, "echo -n \"%s\"", template) < 0) + if (asprintf(&command_echo, "echo -n \a%s\a", template) < 0) goto errout; +#define SWAP_CHAR(a, b) do { if (*p == a) *p = b; } while (0) + for (char *p = command_echo; *p; p++) { + SWAP_CHAR('<', '\001'); + SWAP_CHAR('>', '\002'); + SWAP_CHAR('"', '\003'); + SWAP_CHAR('\'', '\004'); + SWAP_CHAR('|', '\005'); + SWAP_CHAR('&', '\006'); + SWAP_CHAR('\a', '"'); + } err = read_from_pipe(command_echo, (void **) &command_out, NULL); if (err) goto errout; + for (char *p = command_out; *p; p++) { + SWAP_CHAR('\001', '<'); + SWAP_CHAR('\002', '>'); + SWAP_CHAR('\003', '"'); + SWAP_CHAR('\004', '\''); + SWAP_CHAR('\005', '|'); + SWAP_CHAR('\006', '&'); + } +#undef SWAP_CHAR pr_debug("llvm compiling command : %s\n", command_out); err = read_from_pipe(template, &obj_buf, &obj_buf_sz); diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index 85ff4f68adc007a96b3b7f26724d5cff8bcae221..66e11e6bb7197d5a0d085b9ca04227d60668d305 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -735,8 +735,7 @@ static int hist_entry__dso_to_filter(struct hist_entry *he, int type, static int64_t sort__sym_from_cmp(struct hist_entry *left, struct hist_entry *right) { - struct addr_map_symbol *from_l = &left->branch_info->from; - struct addr_map_symbol *from_r = &right->branch_info->from; + struct addr_map_symbol *from_l, *from_r; if (!left->branch_info || !right->branch_info) return cmp_null(left->branch_info, right->branch_info); diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index 8dde4369fbcdb0ef6820555fdff1afbc79aab248..227dfe33063c9c0e2c1d355d0bf055ae30a4418f 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -517,7 +517,7 @@ static int elf_read_build_id(Elf *elf, void *bf, size_t size) size_t sz = min(size, descsz); memcpy(bf, ptr, sz); memset(bf + sz, 0, size - sz); - err = descsz; + err = sz; break; } } diff --git a/tools/power/cpupower/Makefile b/tools/power/cpupower/Makefile index 1dd5f4fcffd53f375ba00479bfed37d867399c4a..392906c8d3a62a0a4273ec09246dcdaeee5f50dd 100644 --- a/tools/power/cpupower/Makefile +++ b/tools/power/cpupower/Makefile @@ -278,14 +278,14 @@ clean: $(MAKE) -C bench O=$(OUTPUT) clean -install-lib: +install-lib: libcpupower $(INSTALL) -d $(DESTDIR)${libdir} $(CP) $(OUTPUT)libcpupower.so* $(DESTDIR)${libdir}/ $(INSTALL) -d $(DESTDIR)${includedir} $(INSTALL_DATA) lib/cpufreq.h $(DESTDIR)${includedir}/cpufreq.h $(INSTALL_DATA) lib/cpuidle.h $(DESTDIR)${includedir}/cpuidle.h -install-tools: +install-tools: $(OUTPUT)cpupower $(INSTALL) -d $(DESTDIR)${bindir} $(INSTALL_PROGRAM) $(OUTPUT)cpupower $(DESTDIR)${bindir} @@ -299,14 +299,14 @@ install-man: $(INSTALL_DATA) -D man/cpupower-info.1 $(DESTDIR)${mandir}/man1/cpupower-info.1 $(INSTALL_DATA) -D man/cpupower-monitor.1 $(DESTDIR)${mandir}/man1/cpupower-monitor.1 -install-gmo: +install-gmo: create-gmo $(INSTALL) -d $(DESTDIR)${localedir} for HLANG in $(LANGUAGES); do \ echo '$(INSTALL_DATA) -D $(OUTPUT)po/$$HLANG.gmo $(DESTDIR)${localedir}/$$HLANG/LC_MESSAGES/cpupower.mo'; \ $(INSTALL_DATA) -D $(OUTPUT)po/$$HLANG.gmo $(DESTDIR)${localedir}/$$HLANG/LC_MESSAGES/cpupower.mo; \ done; -install-bench: +install-bench: compile-bench @#DESTDIR must be set from outside to survive @sbindir=$(sbindir) bindir=$(bindir) docdir=$(docdir) confdir=$(confdir) $(MAKE) -C bench O=$(OUTPUT) install diff --git a/tools/power/cpupower/bench/Makefile b/tools/power/cpupower/bench/Makefile index f68b4bc5527397f285cb1b7bedcf5347ebca52cf..d9d9923af85c2e60ca9b2161fd93867df3346d1b 100644 --- a/tools/power/cpupower/bench/Makefile +++ b/tools/power/cpupower/bench/Makefile @@ -27,7 +27,7 @@ $(OUTPUT)cpufreq-bench: $(OBJS) all: $(OUTPUT)cpufreq-bench -install: +install: $(OUTPUT)cpufreq-bench mkdir -p $(DESTDIR)/$(sbindir) mkdir -p $(DESTDIR)/$(bindir) mkdir -p $(DESTDIR)/$(docdir) diff --git a/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c b/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c index d7c2a6d13dea1a1d4734fb51842eb12b86ef0317..2221e43c63ce09faa9fa7b3c78459fdfd0e76bb2 100644 --- a/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c +++ b/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c @@ -67,8 +67,8 @@ static int max_freq_mode; */ static unsigned long max_frequency; -static unsigned long long tsc_at_measure_start; -static unsigned long long tsc_at_measure_end; +static unsigned long long *tsc_at_measure_start; +static unsigned long long *tsc_at_measure_end; static unsigned long long *mperf_previous_count; static unsigned long long *aperf_previous_count; static unsigned long long *mperf_current_count; @@ -131,7 +131,7 @@ static int mperf_get_count_percent(unsigned int id, double *percent, aperf_diff = aperf_current_count[cpu] - aperf_previous_count[cpu]; if (max_freq_mode == MAX_FREQ_TSC_REF) { - tsc_diff = tsc_at_measure_end - tsc_at_measure_start; + tsc_diff = tsc_at_measure_end[cpu] - tsc_at_measure_start[cpu]; *percent = 100.0 * mperf_diff / tsc_diff; dprint("%s: TSC Ref - mperf_diff: %llu, tsc_diff: %llu\n", mperf_cstates[id].name, mperf_diff, tsc_diff); @@ -168,7 +168,7 @@ static int mperf_get_count_freq(unsigned int id, unsigned long long *count, if (max_freq_mode == MAX_FREQ_TSC_REF) { /* Calculate max_freq from TSC count */ - tsc_diff = tsc_at_measure_end - tsc_at_measure_start; + tsc_diff = tsc_at_measure_end[cpu] - tsc_at_measure_start[cpu]; time_diff = timespec_diff_us(time_start, time_end); max_frequency = tsc_diff / time_diff; } @@ -187,33 +187,27 @@ static int mperf_get_count_freq(unsigned int id, unsigned long long *count, static int mperf_start(void) { int cpu; - unsigned long long dbg; clock_gettime(CLOCK_REALTIME, &time_start); - mperf_get_tsc(&tsc_at_measure_start); - for (cpu = 0; cpu < cpu_count; cpu++) + for (cpu = 0; cpu < cpu_count; cpu++) { + mperf_get_tsc(&tsc_at_measure_start[cpu]); mperf_init_stats(cpu); + } - mperf_get_tsc(&dbg); - dprint("TSC diff: %llu\n", dbg - tsc_at_measure_start); return 0; } static int mperf_stop(void) { - unsigned long long dbg; int cpu; - for (cpu = 0; cpu < cpu_count; cpu++) + for (cpu = 0; cpu < cpu_count; cpu++) { mperf_measure_stats(cpu); + mperf_get_tsc(&tsc_at_measure_end[cpu]); + } - mperf_get_tsc(&tsc_at_measure_end); clock_gettime(CLOCK_REALTIME, &time_end); - - mperf_get_tsc(&dbg); - dprint("TSC diff: %llu\n", dbg - tsc_at_measure_end); - return 0; } @@ -311,7 +305,8 @@ struct cpuidle_monitor *mperf_register(void) aperf_previous_count = calloc(cpu_count, sizeof(unsigned long long)); mperf_current_count = calloc(cpu_count, sizeof(unsigned long long)); aperf_current_count = calloc(cpu_count, sizeof(unsigned long long)); - + tsc_at_measure_start = calloc(cpu_count, sizeof(unsigned long long)); + tsc_at_measure_end = calloc(cpu_count, sizeof(unsigned long long)); mperf_monitor.name_len = strlen(mperf_monitor.name); return &mperf_monitor; } @@ -322,6 +317,8 @@ void mperf_unregister(void) free(aperf_previous_count); free(mperf_current_count); free(aperf_current_count); + free(tsc_at_measure_start); + free(tsc_at_measure_end); free(is_valid); } diff --git a/tools/testing/ktest/ktest.pl b/tools/testing/ktest/ktest.pl index a0b53309c5d8ff81e27de77d32a654b6613c5f1f..128a7fe45a1e34877c6e160bd8803281b50e99d2 100755 --- a/tools/testing/ktest/ktest.pl +++ b/tools/testing/ktest/ktest.pl @@ -172,6 +172,7 @@ my $store_failures; my $store_successes; my $test_name; my $timeout; +my $run_timeout; my $connect_timeout; my $config_bisect_exec; my $booted_timeout; @@ -330,6 +331,7 @@ my %option_map = ( "STORE_SUCCESSES" => \$store_successes, "TEST_NAME" => \$test_name, "TIMEOUT" => \$timeout, + "RUN_TIMEOUT" => \$run_timeout, "CONNECT_TIMEOUT" => \$connect_timeout, "CONFIG_BISECT_EXEC" => \$config_bisect_exec, "BOOTED_TIMEOUT" => \$booted_timeout, @@ -1419,7 +1421,8 @@ sub reboot { # Still need to wait for the reboot to finish wait_for_monitor($time, $reboot_success_line); - + } + if ($powercycle || $time) { end_monitor; } } @@ -1749,6 +1752,14 @@ sub run_command { $command =~ s/\$SSH_USER/$ssh_user/g; $command =~ s/\$MACHINE/$machine/g; + if (!defined($timeout)) { + $timeout = $run_timeout; + } + + if (!defined($timeout)) { + $timeout = -1; # tell wait_for_input to wait indefinitely + } + doprint("$command ... "); $start_time = time; @@ -1777,13 +1788,10 @@ sub run_command { while (1) { my $fp = \*CMD; - if (defined($timeout)) { - doprint "timeout = $timeout\n"; - } my $line = wait_for_input($fp, $timeout); if (!defined($line)) { my $now = time; - if (defined($timeout) && (($now - $start_time) >= $timeout)) { + if ($timeout >= 0 && (($now - $start_time) >= $timeout)) { doprint "Hit timeout of $timeout, killing process\n"; $hit_timeout = 1; kill 9, $pid; @@ -1988,6 +1996,11 @@ sub wait_for_input $time = $timeout; } + if ($time < 0) { + # Negative number means wait indefinitely + undef $time; + } + $rin = ''; vec($rin, fileno($fp), 1) = 1; vec($rin, fileno(\*STDIN), 1) = 1; @@ -4243,6 +4256,9 @@ sub send_email { } sub cancel_test { + if ($monitor_cnt) { + end_monitor; + } if ($email_when_canceled) { send_email("KTEST: Your [$test_type] test was cancelled", "Your test started at $script_start_time was cancelled: sig int"); diff --git a/tools/testing/ktest/sample.conf b/tools/testing/ktest/sample.conf index 6ca6ca0ce695a25d907bde88e8596a3e5b056a52..b487e34bbf45b9dd34563407f85519c24c35c69c 100644 --- a/tools/testing/ktest/sample.conf +++ b/tools/testing/ktest/sample.conf @@ -775,6 +775,11 @@ # is issued instead of a reboot. # CONNECT_TIMEOUT = 25 +# The timeout in seconds for how long to wait for any running command +# to timeout. If not defined, it will let it go indefinitely. +# (default undefined) +#RUN_TIMEOUT = 600 + # In between tests, a reboot of the box may occur, and this # is the time to wait for the console after it stops producing # output. Some machines may not produce a large lag on reboot diff --git a/tools/testing/radix-tree/regression1.c b/tools/testing/radix-tree/regression1.c index 0aece092f40ebbdb865e94b5659417c718310c56..a247026042d441c9a820e9d02eb022b3eee0722f 100644 --- a/tools/testing/radix-tree/regression1.c +++ b/tools/testing/radix-tree/regression1.c @@ -198,7 +198,7 @@ void regression1_test(void) nr_threads = 2; pthread_barrier_init(&worker_barrier, NULL, nr_threads); - threads = malloc(nr_threads * sizeof(pthread_t *)); + threads = malloc(nr_threads * sizeof(*threads)); for (i = 0; i < nr_threads; i++) { arg = i; diff --git a/tools/testing/selftests/efivarfs/create-read.c b/tools/testing/selftests/efivarfs/create-read.c index 9674a19396a325e06336a55942861ab43d086f7e..7bc7af4eb2c17f5e301a01e6ec130e40e6b49173 100644 --- a/tools/testing/selftests/efivarfs/create-read.c +++ b/tools/testing/selftests/efivarfs/create-read.c @@ -32,8 +32,10 @@ int main(int argc, char **argv) rc = read(fd, buf, sizeof(buf)); if (rc != 0) { fprintf(stderr, "Reading a new var should return EOF\n"); + close(fd); return EXIT_FAILURE; } + close(fd); return EXIT_SUCCESS; } diff --git a/tools/testing/selftests/ftrace/test.d/ftrace/func_event_triggers.tc b/tools/testing/selftests/ftrace/test.d/ftrace/func_event_triggers.tc index 79d614f1fe8e4faad8992d6e1d3504e5c47e0deb..d620223a3f0f6d3294d8a7e9cc3b1d377fe6f15a 100644 --- a/tools/testing/selftests/ftrace/test.d/ftrace/func_event_triggers.tc +++ b/tools/testing/selftests/ftrace/test.d/ftrace/func_event_triggers.tc @@ -49,7 +49,7 @@ test_event_enabled() { while [ $check_times -ne 0 ]; do e=`cat $EVENT_ENABLE` - if [ "$e" == $val ]; then + if [ "$e" = $val ]; then return 0 fi sleep $SLEEP_TIME diff --git a/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc b/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc index 4fa0f79144f4abbf96ea294443a4c726d6296ee1..9473934a573a102fffd9b45ca07a89075bbb6516 100644 --- a/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc +++ b/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc @@ -43,7 +43,7 @@ instance_read() { instance_set() { while :; do - echo 1 > foo/events/sched/sched_switch + echo 1 > foo/events/sched/sched_switch/enable done 2> /dev/null } diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_non_uniq_symbol.tc b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_non_uniq_symbol.tc new file mode 100644 index 0000000000000000000000000000000000000000..bc9514428dbaf178b02a22b9ceae7f4351f31738 --- /dev/null +++ b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_non_uniq_symbol.tc @@ -0,0 +1,13 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# description: Test failure of registering kprobe on non unique symbol +# requires: kprobe_events + +SYMBOL='name_show' + +# We skip this test on kernel where SYMBOL is unique or does not exist. +if [ "$(grep -c -E "[[:alnum:]]+ t ${SYMBOL}" /proc/kallsyms)" -le '1' ]; then + exit_unsupported +fi + +! echo "p:test_non_unique ${SYMBOL}" > kprobe_events diff --git a/tools/testing/selftests/memfd/fuse_test.c b/tools/testing/selftests/memfd/fuse_test.c index b018e835737df55d2599dbe62f7b670fd7ec3458..cda63164d9d35c4210395d5d49dd7abd103f3b61 100644 --- a/tools/testing/selftests/memfd/fuse_test.c +++ b/tools/testing/selftests/memfd/fuse_test.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include diff --git a/tools/testing/selftests/net/fib_tests.sh b/tools/testing/selftests/net/fib_tests.sh index a5ba149761bf95c062724cfe091692c36460dd88..f34e14e34d0d4895ae8edc779508c2c827aafbf5 100755 --- a/tools/testing/selftests/net/fib_tests.sh +++ b/tools/testing/selftests/net/fib_tests.sh @@ -1379,6 +1379,8 @@ EOF ################################################################################ # main +trap cleanup EXIT + while getopts :t:pPhv o do case $o in diff --git a/tools/testing/selftests/net/forwarding/mirror_gre_changes.sh b/tools/testing/selftests/net/forwarding/mirror_gre_changes.sh index 135902aa8b11498bfbf99428a77084b4ee3de7fd..a372863c9efdbb486aaddbc303fb363bab56aafa 100755 --- a/tools/testing/selftests/net/forwarding/mirror_gre_changes.sh +++ b/tools/testing/selftests/net/forwarding/mirror_gre_changes.sh @@ -72,7 +72,8 @@ test_span_gre_ttl() RET=0 - mirror_install $swp1 ingress $tundev "matchall $tcflags" + mirror_install $swp1 ingress $tundev \ + "prot ip flower $tcflags ip_prot icmp" tc filter add dev $h3 ingress pref 77 prot $prot \ flower ip_ttl 50 action pass diff --git a/tools/testing/selftests/net/forwarding/tc_flower.sh b/tools/testing/selftests/net/forwarding/tc_flower.sh index 20d1077e5a3de9cb8ad9186d866837421b84d518..85faef980887aac11eba34366163263db26b6fa6 100755 --- a/tools/testing/selftests/net/forwarding/tc_flower.sh +++ b/tools/testing/selftests/net/forwarding/tc_flower.sh @@ -48,8 +48,8 @@ match_dst_mac_test() tc_check_packets "dev $h2 ingress" 101 1 check_fail $? "Matched on a wrong filter" - tc_check_packets "dev $h2 ingress" 102 1 - check_err $? "Did not match on correct filter" + tc_check_packets "dev $h2 ingress" 102 0 + check_fail $? "Did not match on correct filter" tc filter del dev $h2 ingress protocol ip pref 1 handle 101 flower tc filter del dev $h2 ingress protocol ip pref 2 handle 102 flower @@ -74,8 +74,8 @@ match_src_mac_test() tc_check_packets "dev $h2 ingress" 101 1 check_fail $? "Matched on a wrong filter" - tc_check_packets "dev $h2 ingress" 102 1 - check_err $? "Did not match on correct filter" + tc_check_packets "dev $h2 ingress" 102 0 + check_fail $? "Did not match on correct filter" tc filter del dev $h2 ingress protocol ip pref 1 handle 101 flower tc filter del dev $h2 ingress protocol ip pref 2 handle 102 flower diff --git a/tools/testing/selftests/net/tls.c b/tools/testing/selftests/net/tls.c index 7549d39ccafff21dcf28f7ee7bb54efedacbb3e9..92adfe4df4e6d1938bb7a489ee495f940d065363 100644 --- a/tools/testing/selftests/net/tls.c +++ b/tools/testing/selftests/net/tls.c @@ -199,11 +199,12 @@ TEST_F(tls, sendmsg_large) msg.msg_iov = &vec; msg.msg_iovlen = 1; - EXPECT_EQ(sendmsg(self->cfd, &msg, 0), send_len); + EXPECT_EQ(sendmsg(self->fd, &msg, 0), send_len); } - while (recvs++ < sends) - EXPECT_NE(recv(self->fd, mem, send_len, 0), -1); + while (recvs++ < sends) { + EXPECT_NE(recv(self->cfd, mem, send_len, 0), -1); + } free(mem); } @@ -231,9 +232,9 @@ TEST_F(tls, sendmsg_multiple) msg.msg_iov = vec; msg.msg_iovlen = iov_len; - EXPECT_EQ(sendmsg(self->cfd, &msg, 0), total_len); + EXPECT_EQ(sendmsg(self->fd, &msg, 0), total_len); buf = malloc(total_len); - EXPECT_NE(recv(self->fd, buf, total_len, 0), -1); + EXPECT_NE(recv(self->cfd, buf, total_len, 0), -1); for (i = 0; i < iov_len; i++) { EXPECT_EQ(memcmp(test_strs[i], buf + len_cmp, strlen(test_strs[i])), diff --git a/tools/testing/selftests/ptp/testptp.c b/tools/testing/selftests/ptp/testptp.c index a5d8f0ab0da000211fd750b10fef2386ae5cfa4b..60f0f24cee30ef76745a59c70d9e50932cbe4ecd 100644 --- a/tools/testing/selftests/ptp/testptp.c +++ b/tools/testing/selftests/ptp/testptp.c @@ -502,11 +502,11 @@ int main(int argc, char *argv[]) interval = t2 - t1; offset = (t2 + t1) / 2 - tp; - printf("system time: %lld.%u\n", + printf("system time: %lld.%09u\n", (pct+2*i)->sec, (pct+2*i)->nsec); - printf("phc time: %lld.%u\n", + printf("phc time: %lld.%09u\n", (pct+2*i+1)->sec, (pct+2*i+1)->nsec); - printf("system time: %lld.%u\n", + printf("system time: %lld.%09u\n", (pct+2*i+2)->sec, (pct+2*i+2)->nsec); printf("system/phc clock time offset is %" PRId64 " ns\n" "system clock time delay is %" PRId64 " ns\n", diff --git a/tools/testing/selftests/sigaltstack/current_stack_pointer.h b/tools/testing/selftests/sigaltstack/current_stack_pointer.h new file mode 100644 index 0000000000000000000000000000000000000000..ea9bdf3a90b16449a0ffcdfcdc54247125f1c806 --- /dev/null +++ b/tools/testing/selftests/sigaltstack/current_stack_pointer.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#if __alpha__ +register unsigned long sp asm("$30"); +#elif __arm__ || __aarch64__ || __csky__ || __m68k__ || __mips__ || __riscv +register unsigned long sp asm("sp"); +#elif __i386__ +register unsigned long sp asm("esp"); +#elif __loongarch64 +register unsigned long sp asm("$sp"); +#elif __ppc__ +register unsigned long sp asm("r1"); +#elif __s390x__ +register unsigned long sp asm("%15"); +#elif __sh__ +register unsigned long sp asm("r15"); +#elif __x86_64__ +register unsigned long sp asm("rsp"); +#elif __XTENSA__ +register unsigned long sp asm("a1"); +#else +#error "implement current_stack_pointer equivalent" +#endif diff --git a/tools/testing/selftests/sigaltstack/sas.c b/tools/testing/selftests/sigaltstack/sas.c index 228c2ae47687dd753250e696456f7fcedb99b17a..6069d97bf5063013e976affcb5ad3d842ef8edf6 100644 --- a/tools/testing/selftests/sigaltstack/sas.c +++ b/tools/testing/selftests/sigaltstack/sas.c @@ -19,6 +19,7 @@ #include #include "../kselftest.h" +#include "current_stack_pointer.h" #ifndef SS_AUTODISARM #define SS_AUTODISARM (1U << 31) @@ -40,12 +41,6 @@ void my_usr1(int sig, siginfo_t *si, void *u) stack_t stk; struct stk_data *p; -#if __s390x__ - register unsigned long sp asm("%15"); -#else - register unsigned long sp asm("sp"); -#endif - if (sp < (unsigned long)sstack || sp >= (unsigned long)sstack + SIGSTKSZ) { ksft_exit_fail_msg("SP is not on sigaltstack\n");